diff --git a/benchmark/MLPerfTiny_Rules.adoc b/benchmark/MLPerfTiny_Rules.adoc index 17b1db6d..df39cb07 100644 --- a/benchmark/MLPerfTiny_Rules.adoc +++ b/benchmark/MLPerfTiny_Rules.adoc @@ -177,6 +177,7 @@ The suite includes the following benchmarks: | Visual Wake Words | Binary image classification | Visual Wake Words Dataset | MobileNet | 80% (Top 1) | Image Classification | Small image classification | Cifar10 | ResNet | 85% (Top 1) | Anomaly Detection | Detecting anomalies in machine operating sounds | ToyADMOS | Deep AutoEncoder | 0.85 (AUC) +| Streaming Wakeword | Detecting wakewords in a continuous stream of audio| Custom | 1D DS-CNN | TBD |=== ==== Relaxed constraints for the Open division @@ -189,10 +190,13 @@ The suite includes the following benchmarks: == Benchmark Runner + + === EnergyRunnerâ„¢ benchmark framework -The benchmark suite is run using the EnergyRunnerâ„¢ benchmark framework, which detects the DUT, sends inputs, and reads outputs over UART. +The benchmark suite is run using the EnergyRunnerâ„¢ benchmark framework from EEMBC, which detects the DUT, sends inputs, and reads outputs over UART. The EEMBC runner is being phased out. It will be permitted for teh KWS, VWW, IC, and AD benchmarks in the summer 2015 submission. After that, only the MLCommons Runner will be permitted. The EEMBC runner does not support the streaming wakeword benchmark. -The runner is available here: https://github.com/eembc/energyrunner +The EEMBC runner is available here: https://github.com/eembc/energyrunner +The MLCommons runner is available in this repository: https://github.com/mlcommons/tiny/tree/master/benchmark/runner Note: The same code must be run for both the accuracy and performance Runner modes. @@ -332,7 +336,8 @@ The following techniques are disallowed: * Discarding non-zero weight elements, including pruning -* Caching queries or responses +* Caching queries or responses between files. However, in the streaming test, it is +permitted to store intermediate activations between frames of the same waveform. * Coalescing identical queries diff --git a/benchmark/interface/.gitignore b/benchmark/interface/.gitignore index 93675e5d..5e922f45 100644 --- a/benchmark/interface/.gitignore +++ b/benchmark/interface/.gitignore @@ -2,3 +2,5 @@ cmake-build-*/ /STM32CubeIDE/Debug/ /STM32CubeIDE/Release/ +STM32CubeIDE/.settings/ +.metadata/ diff --git a/benchmark/interface/.mxproject b/benchmark/interface/.mxproject index b9dbc8ad..9d56498b 100644 --- a/benchmark/interface/.mxproject +++ b/benchmark/interface/.mxproject @@ -1,72 +1,76 @@ -[PreviousLibFiles] -LibFiles=Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crs.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dmamux.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h;Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_utils.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_fmc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sram.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_xspi.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dlyb.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sai.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sai_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_sdmmc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sd.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sd_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_ucpd.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_usart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_lpuart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h;Middlewares/ST/threadx/common/inc/tx_api.h;Middlewares/ST/threadx/common/inc/tx_block_pool.h;Middlewares/ST/threadx/common/inc/tx_byte_pool.h;Middlewares/ST/threadx/common/inc/tx_event_flags.h;Middlewares/ST/threadx/common/inc/tx_initialize.h;Middlewares/ST/threadx/common/inc/tx_mutex.h;Middlewares/ST/threadx/common/inc/tx_queue.h;Middlewares/ST/threadx/common/inc/tx_semaphore.h;Middlewares/ST/threadx/common/inc/tx_thread.h;Middlewares/ST/threadx/common/inc/tx_timer.h;Middlewares/ST/threadx/common/inc/tx_trace.h;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_xspi.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dlyb.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_sdmmc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_ucpd.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c;Middlewares/ST/filex/common/src/fx_directory_attributes_read.c;Middlewares/ST/filex/common/src/fx_directory_attributes_set.c;Middlewares/ST/filex/common/src/fx_directory_create.c;Middlewares/ST/filex/common/src/fx_directory_default_get.c;Middlewares/ST/filex/common/src/fx_directory_default_get_copy.c;Middlewares/ST/filex/common/src/fx_directory_default_set.c;Middlewares/ST/filex/common/src/fx_directory_delete.c;Middlewares/ST/filex/common/src/fx_directory_entry_read.c;Middlewares/ST/filex/common/src/fx_directory_entry_write.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_entry_read.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_entry_write.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_free_search.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_unicode_entry_write.c;Middlewares/ST/filex/common/src/fx_directory_first_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_first_full_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_free_search.c;Middlewares/ST/filex/common/src/fx_directory_information_get.c;Middlewares/ST/filex/common/src/fx_directory_local_path_clear.c;Middlewares/ST/filex/common/src/fx_directory_local_path_get.c;Middlewares/ST/filex/common/src/fx_directory_local_path_get_copy.c;Middlewares/ST/filex/common/src/fx_directory_local_path_restore.c;Middlewares/ST/filex/common/src/fx_directory_local_path_set.c;Middlewares/ST/filex/common/src/fx_directory_long_name_get.c;Middlewares/ST/filex/common/src/fx_directory_long_name_get_extended.c;Middlewares/ST/filex/common/src/fx_directory_name_extract.c;Middlewares/ST/filex/common/src/fx_directory_name_test.c;Middlewares/ST/filex/common/src/fx_directory_next_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_next_full_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_rename.c;Middlewares/ST/filex/common/src/fx_directory_search.c;Middlewares/ST/filex/common/src/fx_directory_short_name_get.c;Middlewares/ST/filex/common/src/fx_directory_short_name_get_extended.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_bitmap_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_checksum_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_dir_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_FAT_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_apply_logs.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_calculate_checksum.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_cleanup_FAT_chain.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_create_log_file.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_enable.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_read_directory_sector.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_read_FAT.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_read_log_file.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_recover.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_reset_log_file.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_set_FAT_chain.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_end.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_fail.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_start.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_write_log_file.c;Middlewares/ST/filex/common/src/fx_file_allocate.c;Middlewares/ST/filex/common/src/fx_file_attributes_read.c;Middlewares/ST/filex/common/src/fx_file_attributes_set.c;Middlewares/ST/filex/common/src/fx_file_best_effort_allocate.c;Middlewares/ST/filex/common/src/fx_file_close.c;Middlewares/ST/filex/common/src/fx_file_create.c;Middlewares/ST/filex/common/src/fx_file_date_time_set.c;Middlewares/ST/filex/common/src/fx_file_delete.c;Middlewares/ST/filex/common/src/fx_file_extended_allocate.c;Middlewares/ST/filex/common/src/fx_file_extended_best_effort_allocate.c;Middlewares/ST/filex/common/src/fx_file_extended_relative_seek.c;Middlewares/ST/filex/common/src/fx_file_extended_seek.c;Middlewares/ST/filex/common/src/fx_file_extended_truncate.c;Middlewares/ST/filex/common/src/fx_file_extended_truncate_release.c;Middlewares/ST/filex/common/src/fx_file_open.c;Middlewares/ST/filex/common/src/fx_file_read.c;Middlewares/ST/filex/common/src/fx_file_relative_seek.c;Middlewares/ST/filex/common/src/fx_file_rename.c;Middlewares/ST/filex/common/src/fx_file_seek.c;Middlewares/ST/filex/common/src/fx_file_truncate.c;Middlewares/ST/filex/common/src/fx_file_truncate_release.c;Middlewares/ST/filex/common/src/fx_file_write.c;Middlewares/ST/filex/common/src/fx_file_write_notify_set.c;Middlewares/ST/filex/common/src/fx_media_abort.c;Middlewares/ST/filex/common/src/fx_media_boot_info_extract.c;Middlewares/ST/filex/common/src/fx_media_cache_invalidate.c;Middlewares/ST/filex/common/src/fx_media_check.c;Middlewares/ST/filex/common/src/fx_media_check_FAT_chain_check.c;Middlewares/ST/filex/common/src/fx_media_check_lost_cluster_check.c;Middlewares/ST/filex/common/src/fx_media_close.c;Middlewares/ST/filex/common/src/fx_media_close_notify_set.c;Middlewares/ST/filex/common/src/fx_media_exFAT_format.c;Middlewares/ST/filex/common/src/fx_media_extended_space_available.c;Middlewares/ST/filex/common/src/fx_media_flush.c;Middlewares/ST/filex/common/src/fx_media_format.c;Middlewares/ST/filex/common/src/fx_media_format_oem_name_set.c;Middlewares/ST/filex/common/src/fx_media_format_type_set.c;Middlewares/ST/filex/common/src/fx_media_format_volume_id_set.c;Middlewares/ST/filex/common/src/fx_media_open.c;Middlewares/ST/filex/common/src/fx_media_open_notify_set.c;Middlewares/ST/filex/common/src/fx_media_read.c;Middlewares/ST/filex/common/src/fx_media_space_available.c;Middlewares/ST/filex/common/src/fx_media_volume_get.c;Middlewares/ST/filex/common/src/fx_media_volume_get_extended.c;Middlewares/ST/filex/common/src/fx_media_volume_set.c;Middlewares/ST/filex/common/src/fx_media_write.c;Middlewares/ST/filex/common/src/fx_partition_offset_calculate.c;Middlewares/ST/filex/common/src/fx_system_date_get.c;Middlewares/ST/filex/common/src/fx_system_date_set.c;Middlewares/ST/filex/common/src/fx_system_initialize.c;Middlewares/ST/filex/common/src/fx_system_time_get.c;Middlewares/ST/filex/common/src/fx_system_time_set.c;Middlewares/ST/filex/common/src/fx_system_timer_entry.c;Middlewares/ST/filex/common/src/fx_unicode_directory_create.c;Middlewares/ST/filex/common/src/fx_unicode_directory_entry_change.c;Middlewares/ST/filex/common/src/fx_unicode_directory_entry_read.c;Middlewares/ST/filex/common/src/fx_unicode_directory_rename.c;Middlewares/ST/filex/common/src/fx_unicode_directory_search.c;Middlewares/ST/filex/common/src/fx_unicode_file_create.c;Middlewares/ST/filex/common/src/fx_unicode_file_rename.c;Middlewares/ST/filex/common/src/fx_unicode_length_get.c;Middlewares/ST/filex/common/src/fx_unicode_length_get_extended.c;Middlewares/ST/filex/common/src/fx_unicode_name_get.c;Middlewares/ST/filex/common/src/fx_unicode_name_get_extended.c;Middlewares/ST/filex/common/src/fx_unicode_short_name_get.c;Middlewares/ST/filex/common/src/fx_unicode_short_name_get_extended.c;Middlewares/ST/filex/common/src/fx_utility_16_unsigned_read.c;Middlewares/ST/filex/common/src/fx_utility_16_unsigned_write.c;Middlewares/ST/filex/common/src/fx_utility_32_unsigned_read.c;Middlewares/ST/filex/common/src/fx_utility_32_unsigned_write.c;Middlewares/ST/filex/common/src/fx_utility_64_unsigned_read.c;Middlewares/ST/filex/common/src/fx_utility_64_unsigned_write.c;Middlewares/ST/filex/common/src/fx_utility_absolute_path_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_allocate_new_cluster.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_cache_prepare.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_cache_update.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_flush.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_free_cluster_find.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_initialize.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_start_sector_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_free.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_state_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_state_set.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_geometry_check.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_name_hash_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_size_calculate.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_checksum_verify.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_checksum_write.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_format.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_sector_write.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_unicode_name_hash_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_upcase_table.c;Middlewares/ST/filex/common/src/fx_utility_FAT_entry_read.c;Middlewares/ST/filex/common/src/fx_utility_FAT_entry_write.c;Middlewares/ST/filex/common/src/fx_utility_FAT_flush.c;Middlewares/ST/filex/common/src/fx_utility_FAT_map_flush.c;Middlewares/ST/filex/common/src/fx_utility_FAT_sector_get.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_cache_entry_read.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_flush.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_read.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_write.c;Middlewares/ST/filex/common/src/fx_utility_memory_copy.c;Middlewares/ST/filex/common/src/fx_utility_memory_set.c;Middlewares/ST/filex/common/src/fx_utility_string_length_get.c;Middlewares/ST/filex/common/src/fx_utility_token_length_get.c;Middlewares/ST/filex/common/src/fxe_directory_attributes_read.c;Middlewares/ST/filex/common/src/fxe_directory_attributes_set.c;Middlewares/ST/filex/common/src/fxe_directory_create.c;Middlewares/ST/filex/common/src/fxe_directory_default_get.c;Middlewares/ST/filex/common/src/fxe_directory_default_get_copy.c;Middlewares/ST/filex/common/src/fxe_directory_default_set.c;Middlewares/ST/filex/common/src/fxe_directory_delete.c;Middlewares/ST/filex/common/src/fxe_directory_first_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_first_full_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_information_get.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_clear.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_get.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_get_copy.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_restore.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_set.c;Middlewares/ST/filex/common/src/fxe_directory_long_name_get.c;Middlewares/ST/filex/common/src/fxe_directory_long_name_get_extended.c;Middlewares/ST/filex/common/src/fxe_directory_name_test.c;Middlewares/ST/filex/common/src/fxe_directory_next_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_next_full_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_rename.c;Middlewares/ST/filex/common/src/fxe_directory_short_name_get.c;Middlewares/ST/filex/common/src/fxe_directory_short_name_get_extended.c;Middlewares/ST/filex/common/src/fxe_fault_tolerant_enable.c;Middlewares/ST/filex/common/src/fxe_file_allocate.c;Middlewares/ST/filex/common/src/fxe_file_attributes_read.c;Middlewares/ST/filex/common/src/fxe_file_attributes_set.c;Middlewares/ST/filex/common/src/fxe_file_best_effort_allocate.c;Middlewares/ST/filex/common/src/fxe_file_close.c;Middlewares/ST/filex/common/src/fxe_file_create.c;Middlewares/ST/filex/common/src/fxe_file_date_time_set.c;Middlewares/ST/filex/common/src/fxe_file_delete.c;Middlewares/ST/filex/common/src/fxe_file_extended_allocate.c;Middlewares/ST/filex/common/src/fxe_file_extended_best_effort_allocate.c;Middlewares/ST/filex/common/src/fxe_file_extended_relative_seek.c;Middlewares/ST/filex/common/src/fxe_file_extended_seek.c;Middlewares/ST/filex/common/src/fxe_file_extended_truncate.c;Middlewares/ST/filex/common/src/fxe_file_extended_truncate_release.c;Middlewares/ST/filex/common/src/fxe_file_open.c;Middlewares/ST/filex/common/src/fxe_file_read.c;Middlewares/ST/filex/common/src/fxe_file_relative_seek.c;Middlewares/ST/filex/common/src/fxe_file_rename.c;Middlewares/ST/filex/common/src/fxe_file_seek.c;Middlewares/ST/filex/common/src/fxe_file_truncate.c;Middlewares/ST/filex/common/src/fxe_file_truncate_release.c;Middlewares/ST/filex/common/src/fxe_file_write.c;Middlewares/ST/filex/common/src/fxe_file_write_notify_set.c;Middlewares/ST/filex/common/src/fxe_media_abort.c;Middlewares/ST/filex/common/src/fxe_media_cache_invalidate.c;Middlewares/ST/filex/common/src/fxe_media_check.c;Middlewares/ST/filex/common/src/fxe_media_close.c;Middlewares/ST/filex/common/src/fxe_media_close_notify_set.c;Middlewares/ST/filex/common/src/fxe_media_exFAT_format.c;Middlewares/ST/filex/common/src/fxe_media_extended_space_available.c;Middlewares/ST/filex/common/src/fxe_media_flush.c;Middlewares/ST/filex/common/src/fxe_media_format.c;Middlewares/ST/filex/common/src/fxe_media_open.c;Middlewares/ST/filex/common/src/fxe_media_open_notify_set.c;Middlewares/ST/filex/common/src/fxe_media_read.c;Middlewares/ST/filex/common/src/fxe_media_space_available.c;Middlewares/ST/filex/common/src/fxe_media_volume_get.c;Middlewares/ST/filex/common/src/fxe_media_volume_get_extended.c;Middlewares/ST/filex/common/src/fxe_media_volume_set.c;Middlewares/ST/filex/common/src/fxe_media_write.c;Middlewares/ST/filex/common/src/fxe_system_date_get.c;Middlewares/ST/filex/common/src/fxe_system_date_set.c;Middlewares/ST/filex/common/src/fxe_system_time_get.c;Middlewares/ST/filex/common/src/fxe_system_time_set.c;Middlewares/ST/filex/common/src/fxe_unicode_directory_create.c;Middlewares/ST/filex/common/src/fxe_unicode_directory_rename.c;Middlewares/ST/filex/common/src/fxe_unicode_file_create.c;Middlewares/ST/filex/common/src/fxe_unicode_file_rename.c;Middlewares/ST/filex/common/src/fxe_unicode_name_get.c;Middlewares/ST/filex/common/src/fxe_unicode_name_get_extended.c;Middlewares/ST/filex/common/src/fxe_unicode_short_name_get.c;Middlewares/ST/filex/common/src/fxe_unicode_short_name_get_extended.c;Middlewares/ST/filex/common/drivers/fx_stm32_sd_driver.c;Middlewares/ST/threadx/common/src/tx_initialize_high_level.c;Middlewares/ST/threadx/common/src/tx_initialize_kernel_enter.c;Middlewares/ST/threadx/common/src/tx_initialize_kernel_setup.c;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_context_restore.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_context_save.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_interrupt_control.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_interrupt_disable.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_interrupt_restore.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_schedule.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_stack_build.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_system_return.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_timer_interrupt.S;Middlewares/ST/threadx/common/src/tx_thread_stack_error_handler.c;Middlewares/ST/threadx/common/src/tx_thread_stack_error_notify.c;Middlewares/ST/threadx/common/src/tx_thread_system_resume.c;Middlewares/ST/threadx/common/src/tx_block_allocate.c;Middlewares/ST/threadx/common/src/tx_block_pool_cleanup.c;Middlewares/ST/threadx/common/src/tx_block_pool_create.c;Middlewares/ST/threadx/common/src/tx_block_pool_delete.c;Middlewares/ST/threadx/common/src/tx_block_pool_info_get.c;Middlewares/ST/threadx/common/src/tx_block_pool_initialize.c;Middlewares/ST/threadx/common/src/tx_block_pool_prioritize.c;Middlewares/ST/threadx/common/src/tx_block_release.c;Middlewares/ST/threadx/common/src/tx_byte_allocate.c;Middlewares/ST/threadx/common/src/tx_byte_pool_cleanup.c;Middlewares/ST/threadx/common/src/tx_byte_pool_create.c;Middlewares/ST/threadx/common/src/tx_byte_pool_delete.c;Middlewares/ST/threadx/common/src/tx_byte_pool_info_get.c;Middlewares/ST/threadx/common/src/tx_byte_pool_initialize.c;Middlewares/ST/threadx/common/src/tx_byte_pool_prioritize.c;Middlewares/ST/threadx/common/src/tx_byte_pool_search.c;Middlewares/ST/threadx/common/src/tx_byte_release.c;Middlewares/ST/threadx/common/src/tx_event_flags_cleanup.c;Middlewares/ST/threadx/common/src/tx_event_flags_create.c;Middlewares/ST/threadx/common/src/tx_event_flags_delete.c;Middlewares/ST/threadx/common/src/tx_event_flags_get.c;Middlewares/ST/threadx/common/src/tx_event_flags_info_get.c;Middlewares/ST/threadx/common/src/tx_event_flags_initialize.c;Middlewares/ST/threadx/common/src/tx_event_flags_set.c;Middlewares/ST/threadx/common/src/tx_event_flags_set_notify.c;Middlewares/ST/threadx/common/src/tx_mutex_cleanup.c;Middlewares/ST/threadx/common/src/tx_mutex_create.c;Middlewares/ST/threadx/common/src/tx_mutex_delete.c;Middlewares/ST/threadx/common/src/tx_mutex_get.c;Middlewares/ST/threadx/common/src/tx_mutex_info_get.c;Middlewares/ST/threadx/common/src/tx_mutex_initialize.c;Middlewares/ST/threadx/common/src/tx_mutex_prioritize.c;Middlewares/ST/threadx/common/src/tx_mutex_priority_change.c;Middlewares/ST/threadx/common/src/tx_mutex_put.c;Middlewares/ST/threadx/common/src/tx_queue_cleanup.c;Middlewares/ST/threadx/common/src/tx_queue_create.c;Middlewares/ST/threadx/common/src/tx_queue_delete.c;Middlewares/ST/threadx/common/src/tx_queue_flush.c;Middlewares/ST/threadx/common/src/tx_queue_front_send.c;Middlewares/ST/threadx/common/src/tx_queue_info_get.c;Middlewares/ST/threadx/common/src/tx_queue_initialize.c;Middlewares/ST/threadx/common/src/tx_queue_prioritize.c;Middlewares/ST/threadx/common/src/tx_queue_receive.c;Middlewares/ST/threadx/common/src/tx_queue_send.c;Middlewares/ST/threadx/common/src/tx_queue_send_notify.c;Middlewares/ST/threadx/common/src/tx_semaphore_ceiling_put.c;Middlewares/ST/threadx/common/src/tx_semaphore_cleanup.c;Middlewares/ST/threadx/common/src/tx_semaphore_create.c;Middlewares/ST/threadx/common/src/tx_semaphore_delete.c;Middlewares/ST/threadx/common/src/tx_semaphore_get.c;Middlewares/ST/threadx/common/src/tx_semaphore_info_get.c;Middlewares/ST/threadx/common/src/tx_semaphore_initialize.c;Middlewares/ST/threadx/common/src/tx_semaphore_prioritize.c;Middlewares/ST/threadx/common/src/tx_semaphore_put.c;Middlewares/ST/threadx/common/src/tx_semaphore_put_notify.c;Middlewares/ST/threadx/common/src/tx_thread_create.c;Middlewares/ST/threadx/common/src/tx_thread_delete.c;Middlewares/ST/threadx/common/src/tx_thread_entry_exit_notify.c;Middlewares/ST/threadx/common/src/tx_thread_identify.c;Middlewares/ST/threadx/common/src/tx_thread_info_get.c;Middlewares/ST/threadx/common/src/tx_thread_initialize.c;Middlewares/ST/threadx/common/src/tx_thread_preemption_change.c;Middlewares/ST/threadx/common/src/tx_thread_priority_change.c;Middlewares/ST/threadx/common/src/tx_thread_relinquish.c;Middlewares/ST/threadx/common/src/tx_thread_reset.c;Middlewares/ST/threadx/common/src/tx_thread_resume.c;Middlewares/ST/threadx/common/src/tx_thread_shell_entry.c;Middlewares/ST/threadx/common/src/tx_thread_sleep.c;Middlewares/ST/threadx/common/src/tx_thread_stack_analyze.c;Middlewares/ST/threadx/common/src/tx_thread_suspend.c;Middlewares/ST/threadx/common/src/tx_thread_system_preempt_check.c;Middlewares/ST/threadx/common/src/tx_thread_system_suspend.c;Middlewares/ST/threadx/common/src/tx_thread_terminate.c;Middlewares/ST/threadx/common/src/tx_thread_time_slice.c;Middlewares/ST/threadx/common/src/tx_thread_time_slice_change.c;Middlewares/ST/threadx/common/src/tx_thread_timeout.c;Middlewares/ST/threadx/common/src/tx_thread_wait_abort.c;Middlewares/ST/threadx/common/src/tx_time_get.c;Middlewares/ST/threadx/common/src/tx_time_set.c;Middlewares/ST/threadx/common/src/txe_block_allocate.c;Middlewares/ST/threadx/common/src/txe_block_pool_create.c;Middlewares/ST/threadx/common/src/txe_block_pool_delete.c;Middlewares/ST/threadx/common/src/txe_block_pool_info_get.c;Middlewares/ST/threadx/common/src/txe_block_pool_prioritize.c;Middlewares/ST/threadx/common/src/txe_block_release.c;Middlewares/ST/threadx/common/src/txe_byte_allocate.c;Middlewares/ST/threadx/common/src/txe_byte_pool_create.c;Middlewares/ST/threadx/common/src/txe_byte_pool_delete.c;Middlewares/ST/threadx/common/src/txe_byte_pool_info_get.c;Middlewares/ST/threadx/common/src/txe_byte_pool_prioritize.c;Middlewares/ST/threadx/common/src/txe_byte_release.c;Middlewares/ST/threadx/common/src/txe_event_flags_create.c;Middlewares/ST/threadx/common/src/txe_event_flags_delete.c;Middlewares/ST/threadx/common/src/txe_event_flags_get.c;Middlewares/ST/threadx/common/src/txe_event_flags_info_get.c;Middlewares/ST/threadx/common/src/txe_event_flags_set.c;Middlewares/ST/threadx/common/src/txe_event_flags_set_notify.c;Middlewares/ST/threadx/common/src/txe_mutex_create.c;Middlewares/ST/threadx/common/src/txe_mutex_delete.c;Middlewares/ST/threadx/common/src/txe_mutex_get.c;Middlewares/ST/threadx/common/src/txe_mutex_info_get.c;Middlewares/ST/threadx/common/src/txe_mutex_prioritize.c;Middlewares/ST/threadx/common/src/txe_mutex_put.c;Middlewares/ST/threadx/common/src/txe_queue_create.c;Middlewares/ST/threadx/common/src/txe_queue_delete.c;Middlewares/ST/threadx/common/src/txe_queue_flush.c;Middlewares/ST/threadx/common/src/txe_queue_front_send.c;Middlewares/ST/threadx/common/src/txe_queue_info_get.c;Middlewares/ST/threadx/common/src/txe_queue_prioritize.c;Middlewares/ST/threadx/common/src/txe_queue_receive.c;Middlewares/ST/threadx/common/src/txe_queue_send.c;Middlewares/ST/threadx/common/src/txe_queue_send_notify.c;Middlewares/ST/threadx/common/src/txe_semaphore_ceiling_put.c;Middlewares/ST/threadx/common/src/txe_semaphore_create.c;Middlewares/ST/threadx/common/src/txe_semaphore_delete.c;Middlewares/ST/threadx/common/src/txe_semaphore_get.c;Middlewares/ST/threadx/common/src/txe_semaphore_info_get.c;Middlewares/ST/threadx/common/src/txe_semaphore_prioritize.c;Middlewares/ST/threadx/common/src/txe_semaphore_put.c;Middlewares/ST/threadx/common/src/txe_semaphore_put_notify.c;Middlewares/ST/threadx/common/src/txe_thread_create.c;Middlewares/ST/threadx/common/src/txe_thread_delete.c;Middlewares/ST/threadx/common/src/txe_thread_entry_exit_notify.c;Middlewares/ST/threadx/common/src/txe_thread_info_get.c;Middlewares/ST/threadx/common/src/txe_thread_preemption_change.c;Middlewares/ST/threadx/common/src/txe_thread_priority_change.c;Middlewares/ST/threadx/common/src/txe_thread_relinquish.c;Middlewares/ST/threadx/common/src/txe_thread_reset.c;Middlewares/ST/threadx/common/src/txe_thread_resume.c;Middlewares/ST/threadx/common/src/txe_thread_suspend.c;Middlewares/ST/threadx/common/src/txe_thread_terminate.c;Middlewares/ST/threadx/common/src/txe_thread_time_slice_change.c;Middlewares/ST/threadx/common/src/txe_thread_wait_abort.c;Middlewares/ST/threadx/common/src/tx_timer_activate.c;Middlewares/ST/threadx/common/src/tx_timer_change.c;Middlewares/ST/threadx/common/src/tx_timer_create.c;Middlewares/ST/threadx/common/src/tx_timer_deactivate.c;Middlewares/ST/threadx/common/src/tx_timer_delete.c;Middlewares/ST/threadx/common/src/tx_timer_expiration_process.c;Middlewares/ST/threadx/common/src/tx_timer_info_get.c;Middlewares/ST/threadx/common/src/tx_timer_initialize.c;Middlewares/ST/threadx/common/src/tx_timer_system_activate.c;Middlewares/ST/threadx/common/src/tx_timer_system_deactivate.c;Middlewares/ST/threadx/common/src/tx_timer_thread_entry.c;Middlewares/ST/threadx/common/src/txe_timer_activate.c;Middlewares/ST/threadx/common/src/txe_timer_change.c;Middlewares/ST/threadx/common/src/txe_timer_create.c;Middlewares/ST/threadx/common/src/txe_timer_deactivate.c;Middlewares/ST/threadx/common/src/txe_timer_delete.c;Middlewares/ST/threadx/common/src/txe_timer_info_get.c;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crs.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dmamux.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h;Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_utils.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_fmc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sram.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_xspi.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dlyb.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sai.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sai_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_sdmmc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sd.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sd_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_ucpd.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_usart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_lpuart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h;Middlewares/ST/threadx/common/inc/tx_api.h;Middlewares/ST/threadx/common/inc/tx_block_pool.h;Middlewares/ST/threadx/common/inc/tx_byte_pool.h;Middlewares/ST/threadx/common/inc/tx_event_flags.h;Middlewares/ST/threadx/common/inc/tx_initialize.h;Middlewares/ST/threadx/common/inc/tx_mutex.h;Middlewares/ST/threadx/common/inc/tx_queue.h;Middlewares/ST/threadx/common/inc/tx_semaphore.h;Middlewares/ST/threadx/common/inc/tx_thread.h;Middlewares/ST/threadx/common/inc/tx_timer.h;Middlewares/ST/threadx/common/inc/tx_trace.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.c;Middlewares/ST/filex/common/inc/fx_media.h;Middlewares/ST/filex/common/inc/fx_api.h;Middlewares/ST/filex/common/inc/fx_directory.h;Middlewares/ST/filex/common/inc/fx_utility.h;Middlewares/ST/filex/common/inc/fx_user_sample.h;Middlewares/ST/filex/common/inc/fx_fault_tolerant.h;Middlewares/ST/filex/common/inc/fx_file.h;Middlewares/ST/filex/common/inc/fx_unicode.h;Middlewares/ST/filex/common/inc/fx_system.h;Middlewares/ST/filex/common/inc/fx_directory_exFAT.h;Middlewares/ST/filex/ports/generic/inc/fx_port.h;Middlewares/ST/threadx/ports/cortex_m33/gnu/inc/tx_port.h;Middlewares/ST/threadx/ports/cortex_m33/gnu/inc/tx_secure_interface.h;Middlewares/ST/filex/common/inc/fx_media.h;Middlewares/ST/filex/common/inc/fx_api.h;Middlewares/ST/filex/common/inc/fx_directory.h;Middlewares/ST/filex/common/inc/fx_utility.h;Middlewares/ST/filex/common/inc/fx_user_sample.h;Middlewares/ST/filex/common/inc/fx_fault_tolerant.h;Middlewares/ST/filex/common/inc/fx_file.h;Middlewares/ST/filex/common/inc/fx_unicode.h;Middlewares/ST/filex/common/inc/fx_system.h;Middlewares/ST/filex/common/inc/fx_directory_exFAT.h;Middlewares/ST/filex/ports/generic/inc/fx_port.h;Middlewares/ST/threadx/ports/cortex_m33/gnu/inc/tx_port.h;Middlewares/ST/threadx/ports/cortex_m33/gnu/inc/tx_secure_interface.h;Drivers/CMSIS/Include/core_cm85.h;Drivers/CMSIS/Include/cachel1_armv7.h;Drivers/CMSIS/Include/pac_armv81.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_cm35p.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_armv81mml.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm55.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/pmu_armv8.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_starmc1.h;Drivers/CMSIS/Include/cmsis_armclang_ltm.h; - -[PreviousUsedCubeIDEFiles] -SourceFiles=Core/Src/main.c;Core/Src/tx_initialize_low_level.S;Core/Src/gpio.c;Core/Src/adc.c;Core/Src/eth.c;FileX/App/app_filex.c;FileX/Target/fx_stm32_sd_driver_glue.c;Core/Src/fmc.c;Core/Src/gpdma.c;Core/Src/icache.c;Core/Src/linked_list.c;Core/Src/memorymap.c;Core/Src/octospi.c;Core/Src/sai.c;Core/Src/sdmmc.c;Core/Src/app_threadx.c;AZURE_RTOS/App/app_azure_rtos.c;Core/Src/ucpd.c;Core/Src/usart.c;Core/Src/stm32h5xx_it.c;Core/Src/stm32h5xx_hal_msp.c;Core/Src/stm32h5xx_hal_timebase_tim.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_utils.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_xspi.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dlyb.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_sdmmc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_ucpd.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c;Middlewares/ST/filex/common/src/fx_directory_attributes_read.c;Middlewares/ST/filex/common/src/fx_directory_attributes_set.c;Middlewares/ST/filex/common/src/fx_directory_create.c;Middlewares/ST/filex/common/src/fx_directory_default_get.c;Middlewares/ST/filex/common/src/fx_directory_default_get_copy.c;Middlewares/ST/filex/common/src/fx_directory_default_set.c;Middlewares/ST/filex/common/src/fx_directory_delete.c;Middlewares/ST/filex/common/src/fx_directory_entry_read.c;Middlewares/ST/filex/common/src/fx_directory_entry_write.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_entry_read.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_entry_write.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_free_search.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_unicode_entry_write.c;Middlewares/ST/filex/common/src/fx_directory_first_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_first_full_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_free_search.c;Middlewares/ST/filex/common/src/fx_directory_information_get.c;Middlewares/ST/filex/common/src/fx_directory_local_path_clear.c;Middlewares/ST/filex/common/src/fx_directory_local_path_get.c;Middlewares/ST/filex/common/src/fx_directory_local_path_get_copy.c;Middlewares/ST/filex/common/src/fx_directory_local_path_restore.c;Middlewares/ST/filex/common/src/fx_directory_local_path_set.c;Middlewares/ST/filex/common/src/fx_directory_long_name_get.c;Middlewares/ST/filex/common/src/fx_directory_long_name_get_extended.c;Middlewares/ST/filex/common/src/fx_directory_name_extract.c;Middlewares/ST/filex/common/src/fx_directory_name_test.c;Middlewares/ST/filex/common/src/fx_directory_next_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_next_full_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_rename.c;Middlewares/ST/filex/common/src/fx_directory_search.c;Middlewares/ST/filex/common/src/fx_directory_short_name_get.c;Middlewares/ST/filex/common/src/fx_directory_short_name_get_extended.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_bitmap_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_checksum_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_dir_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_FAT_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_apply_logs.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_calculate_checksum.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_cleanup_FAT_chain.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_create_log_file.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_enable.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_read_directory_sector.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_read_FAT.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_read_log_file.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_recover.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_reset_log_file.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_set_FAT_chain.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_end.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_fail.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_start.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_write_log_file.c;Middlewares/ST/filex/common/src/fx_file_allocate.c;Middlewares/ST/filex/common/src/fx_file_attributes_read.c;Middlewares/ST/filex/common/src/fx_file_attributes_set.c;Middlewares/ST/filex/common/src/fx_file_best_effort_allocate.c;Middlewares/ST/filex/common/src/fx_file_close.c;Middlewares/ST/filex/common/src/fx_file_create.c;Middlewares/ST/filex/common/src/fx_file_date_time_set.c;Middlewares/ST/filex/common/src/fx_file_delete.c;Middlewares/ST/filex/common/src/fx_file_extended_allocate.c;Middlewares/ST/filex/common/src/fx_file_extended_best_effort_allocate.c;Middlewares/ST/filex/common/src/fx_file_extended_relative_seek.c;Middlewares/ST/filex/common/src/fx_file_extended_seek.c;Middlewares/ST/filex/common/src/fx_file_extended_truncate.c;Middlewares/ST/filex/common/src/fx_file_extended_truncate_release.c;Middlewares/ST/filex/common/src/fx_file_open.c;Middlewares/ST/filex/common/src/fx_file_read.c;Middlewares/ST/filex/common/src/fx_file_relative_seek.c;Middlewares/ST/filex/common/src/fx_file_rename.c;Middlewares/ST/filex/common/src/fx_file_seek.c;Middlewares/ST/filex/common/src/fx_file_truncate.c;Middlewares/ST/filex/common/src/fx_file_truncate_release.c;Middlewares/ST/filex/common/src/fx_file_write.c;Middlewares/ST/filex/common/src/fx_file_write_notify_set.c;Middlewares/ST/filex/common/src/fx_media_abort.c;Middlewares/ST/filex/common/src/fx_media_boot_info_extract.c;Middlewares/ST/filex/common/src/fx_media_cache_invalidate.c;Middlewares/ST/filex/common/src/fx_media_check.c;Middlewares/ST/filex/common/src/fx_media_check_FAT_chain_check.c;Middlewares/ST/filex/common/src/fx_media_check_lost_cluster_check.c;Middlewares/ST/filex/common/src/fx_media_close.c;Middlewares/ST/filex/common/src/fx_media_close_notify_set.c;Middlewares/ST/filex/common/src/fx_media_exFAT_format.c;Middlewares/ST/filex/common/src/fx_media_extended_space_available.c;Middlewares/ST/filex/common/src/fx_media_flush.c;Middlewares/ST/filex/common/src/fx_media_format.c;Middlewares/ST/filex/common/src/fx_media_format_oem_name_set.c;Middlewares/ST/filex/common/src/fx_media_format_type_set.c;Middlewares/ST/filex/common/src/fx_media_format_volume_id_set.c;Middlewares/ST/filex/common/src/fx_media_open.c;Middlewares/ST/filex/common/src/fx_media_open_notify_set.c;Middlewares/ST/filex/common/src/fx_media_read.c;Middlewares/ST/filex/common/src/fx_media_space_available.c;Middlewares/ST/filex/common/src/fx_media_volume_get.c;Middlewares/ST/filex/common/src/fx_media_volume_get_extended.c;Middlewares/ST/filex/common/src/fx_media_volume_set.c;Middlewares/ST/filex/common/src/fx_media_write.c;Middlewares/ST/filex/common/src/fx_partition_offset_calculate.c;Middlewares/ST/filex/common/src/fx_system_date_get.c;Middlewares/ST/filex/common/src/fx_system_date_set.c;Middlewares/ST/filex/common/src/fx_system_initialize.c;Middlewares/ST/filex/common/src/fx_system_time_get.c;Middlewares/ST/filex/common/src/fx_system_time_set.c;Middlewares/ST/filex/common/src/fx_system_timer_entry.c;Middlewares/ST/filex/common/src/fx_unicode_directory_create.c;Middlewares/ST/filex/common/src/fx_unicode_directory_entry_change.c;Middlewares/ST/filex/common/src/fx_unicode_directory_entry_read.c;Middlewares/ST/filex/common/src/fx_unicode_directory_rename.c;Middlewares/ST/filex/common/src/fx_unicode_directory_search.c;Middlewares/ST/filex/common/src/fx_unicode_file_create.c;Middlewares/ST/filex/common/src/fx_unicode_file_rename.c;Middlewares/ST/filex/common/src/fx_unicode_length_get.c;Middlewares/ST/filex/common/src/fx_unicode_length_get_extended.c;Middlewares/ST/filex/common/src/fx_unicode_name_get.c;Middlewares/ST/filex/common/src/fx_unicode_name_get_extended.c;Middlewares/ST/filex/common/src/fx_unicode_short_name_get.c;Middlewares/ST/filex/common/src/fx_unicode_short_name_get_extended.c;Middlewares/ST/filex/common/src/fx_utility_16_unsigned_read.c;Middlewares/ST/filex/common/src/fx_utility_16_unsigned_write.c;Middlewares/ST/filex/common/src/fx_utility_32_unsigned_read.c;Middlewares/ST/filex/common/src/fx_utility_32_unsigned_write.c;Middlewares/ST/filex/common/src/fx_utility_64_unsigned_read.c;Middlewares/ST/filex/common/src/fx_utility_64_unsigned_write.c;Middlewares/ST/filex/common/src/fx_utility_absolute_path_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_allocate_new_cluster.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_cache_prepare.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_cache_update.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_flush.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_free_cluster_find.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_initialize.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_start_sector_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_free.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_state_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_state_set.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_geometry_check.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_name_hash_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_size_calculate.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_checksum_verify.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_checksum_write.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_format.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_sector_write.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_unicode_name_hash_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_upcase_table.c;Middlewares/ST/filex/common/src/fx_utility_FAT_entry_read.c;Middlewares/ST/filex/common/src/fx_utility_FAT_entry_write.c;Middlewares/ST/filex/common/src/fx_utility_FAT_flush.c;Middlewares/ST/filex/common/src/fx_utility_FAT_map_flush.c;Middlewares/ST/filex/common/src/fx_utility_FAT_sector_get.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_cache_entry_read.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_flush.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_read.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_write.c;Middlewares/ST/filex/common/src/fx_utility_memory_copy.c;Middlewares/ST/filex/common/src/fx_utility_memory_set.c;Middlewares/ST/filex/common/src/fx_utility_string_length_get.c;Middlewares/ST/filex/common/src/fx_utility_token_length_get.c;Middlewares/ST/filex/common/src/fxe_directory_attributes_read.c;Middlewares/ST/filex/common/src/fxe_directory_attributes_set.c;Middlewares/ST/filex/common/src/fxe_directory_create.c;Middlewares/ST/filex/common/src/fxe_directory_default_get.c;Middlewares/ST/filex/common/src/fxe_directory_default_get_copy.c;Middlewares/ST/filex/common/src/fxe_directory_default_set.c;Middlewares/ST/filex/common/src/fxe_directory_delete.c;Middlewares/ST/filex/common/src/fxe_directory_first_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_first_full_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_information_get.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_clear.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_get.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_get_copy.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_restore.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_set.c;Middlewares/ST/filex/common/src/fxe_directory_long_name_get.c;Middlewares/ST/filex/common/src/fxe_directory_long_name_get_extended.c;Middlewares/ST/filex/common/src/fxe_directory_name_test.c;Middlewares/ST/filex/common/src/fxe_directory_next_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_next_full_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_rename.c;Middlewares/ST/filex/common/src/fxe_directory_short_name_get.c;Middlewares/ST/filex/common/src/fxe_directory_short_name_get_extended.c;Middlewares/ST/filex/common/src/fxe_fault_tolerant_enable.c;Middlewares/ST/filex/common/src/fxe_file_allocate.c;Middlewares/ST/filex/common/src/fxe_file_attributes_read.c;Middlewares/ST/filex/common/src/fxe_file_attributes_set.c;Middlewares/ST/filex/common/src/fxe_file_best_effort_allocate.c;Middlewares/ST/filex/common/src/fxe_file_close.c;Middlewares/ST/filex/common/src/fxe_file_create.c;Middlewares/ST/filex/common/src/fxe_file_date_time_set.c;Middlewares/ST/filex/common/src/fxe_file_delete.c;Middlewares/ST/filex/common/src/fxe_file_extended_allocate.c;Middlewares/ST/filex/common/src/fxe_file_extended_best_effort_allocate.c;Middlewares/ST/filex/common/src/fxe_file_extended_relative_seek.c;Middlewares/ST/filex/common/src/fxe_file_extended_seek.c;Middlewares/ST/filex/common/src/fxe_file_extended_truncate.c;Middlewares/ST/filex/common/src/fxe_file_extended_truncate_release.c;Middlewares/ST/filex/common/src/fxe_file_open.c;Middlewares/ST/filex/common/src/fxe_file_read.c;Middlewares/ST/filex/common/src/fxe_file_relative_seek.c;Middlewares/ST/filex/common/src/fxe_file_rename.c;Middlewares/ST/filex/common/src/fxe_file_seek.c;Middlewares/ST/filex/common/src/fxe_file_truncate.c;Middlewares/ST/filex/common/src/fxe_file_truncate_release.c;Middlewares/ST/filex/common/src/fxe_file_write.c;Middlewares/ST/filex/common/src/fxe_file_write_notify_set.c;Middlewares/ST/filex/common/src/fxe_media_abort.c;Middlewares/ST/filex/common/src/fxe_media_cache_invalidate.c;Middlewares/ST/filex/common/src/fxe_media_check.c;Middlewares/ST/filex/common/src/fxe_media_close.c;Middlewares/ST/filex/common/src/fxe_media_close_notify_set.c;Middlewares/ST/filex/common/src/fxe_media_exFAT_format.c;Middlewares/ST/filex/common/src/fxe_media_extended_space_available.c;Middlewares/ST/filex/common/src/fxe_media_flush.c;Middlewares/ST/filex/common/src/fxe_media_format.c;Middlewares/ST/filex/common/src/fxe_media_open.c;Middlewares/ST/filex/common/src/fxe_media_open_notify_set.c;Middlewares/ST/filex/common/src/fxe_media_read.c;Middlewares/ST/filex/common/src/fxe_media_space_available.c;Middlewares/ST/filex/common/src/fxe_media_volume_get.c;Middlewares/ST/filex/common/src/fxe_media_volume_get_extended.c;Middlewares/ST/filex/common/src/fxe_media_volume_set.c;Middlewares/ST/filex/common/src/fxe_media_write.c;Middlewares/ST/filex/common/src/fxe_system_date_get.c;Middlewares/ST/filex/common/src/fxe_system_date_set.c;Middlewares/ST/filex/common/src/fxe_system_time_get.c;Middlewares/ST/filex/common/src/fxe_system_time_set.c;Middlewares/ST/filex/common/src/fxe_unicode_directory_create.c;Middlewares/ST/filex/common/src/fxe_unicode_directory_rename.c;Middlewares/ST/filex/common/src/fxe_unicode_file_create.c;Middlewares/ST/filex/common/src/fxe_unicode_file_rename.c;Middlewares/ST/filex/common/src/fxe_unicode_name_get.c;Middlewares/ST/filex/common/src/fxe_unicode_name_get_extended.c;Middlewares/ST/filex/common/src/fxe_unicode_short_name_get.c;Middlewares/ST/filex/common/src/fxe_unicode_short_name_get_extended.c;Middlewares/ST/filex/common/drivers/fx_stm32_sd_driver.c;Middlewares/ST/threadx/common/src/tx_initialize_high_level.c;Middlewares/ST/threadx/common/src/tx_initialize_kernel_enter.c;Middlewares/ST/threadx/common/src/tx_initialize_kernel_setup.c;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_context_restore.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_context_save.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_interrupt_control.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_interrupt_disable.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_interrupt_restore.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_schedule.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_stack_build.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_system_return.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_timer_interrupt.S;Middlewares/ST/threadx/common/src/tx_thread_stack_error_handler.c;Middlewares/ST/threadx/common/src/tx_thread_stack_error_notify.c;Middlewares/ST/threadx/common/src/tx_thread_system_resume.c;Middlewares/ST/threadx/common/src/tx_block_allocate.c;Middlewares/ST/threadx/common/src/tx_block_pool_cleanup.c;Middlewares/ST/threadx/common/src/tx_block_pool_create.c;Middlewares/ST/threadx/common/src/tx_block_pool_delete.c;Middlewares/ST/threadx/common/src/tx_block_pool_info_get.c;Middlewares/ST/threadx/common/src/tx_block_pool_initialize.c;Middlewares/ST/threadx/common/src/tx_block_pool_prioritize.c;Middlewares/ST/threadx/common/src/tx_block_release.c;Middlewares/ST/threadx/common/src/tx_byte_allocate.c;Middlewares/ST/threadx/common/src/tx_byte_pool_cleanup.c;Middlewares/ST/threadx/common/src/tx_byte_pool_create.c;Middlewares/ST/threadx/common/src/tx_byte_pool_delete.c;Middlewares/ST/threadx/common/src/tx_byte_pool_info_get.c;Middlewares/ST/threadx/common/src/tx_byte_pool_initialize.c;Middlewares/ST/threadx/common/src/tx_byte_pool_prioritize.c;Middlewares/ST/threadx/common/src/tx_byte_pool_search.c;Middlewares/ST/threadx/common/src/tx_byte_release.c;Middlewares/ST/threadx/common/src/tx_event_flags_cleanup.c;Middlewares/ST/threadx/common/src/tx_event_flags_create.c;Middlewares/ST/threadx/common/src/tx_event_flags_delete.c;Middlewares/ST/threadx/common/src/tx_event_flags_get.c;Middlewares/ST/threadx/common/src/tx_event_flags_info_get.c;Middlewares/ST/threadx/common/src/tx_event_flags_initialize.c;Middlewares/ST/threadx/common/src/tx_event_flags_set.c;Middlewares/ST/threadx/common/src/tx_event_flags_set_notify.c;Middlewares/ST/threadx/common/src/tx_mutex_cleanup.c;Middlewares/ST/threadx/common/src/tx_mutex_create.c;Middlewares/ST/threadx/common/src/tx_mutex_delete.c;Middlewares/ST/threadx/common/src/tx_mutex_get.c;Middlewares/ST/threadx/common/src/tx_mutex_info_get.c;Middlewares/ST/threadx/common/src/tx_mutex_initialize.c;Middlewares/ST/threadx/common/src/tx_mutex_prioritize.c;Middlewares/ST/threadx/common/src/tx_mutex_priority_change.c;Middlewares/ST/threadx/common/src/tx_mutex_put.c;Middlewares/ST/threadx/common/src/tx_queue_cleanup.c;Middlewares/ST/threadx/common/src/tx_queue_create.c;Middlewares/ST/threadx/common/src/tx_queue_delete.c;Middlewares/ST/threadx/common/src/tx_queue_flush.c;Middlewares/ST/threadx/common/src/tx_queue_front_send.c;Middlewares/ST/threadx/common/src/tx_queue_info_get.c;Middlewares/ST/threadx/common/src/tx_queue_initialize.c;Middlewares/ST/threadx/common/src/tx_queue_prioritize.c;Middlewares/ST/threadx/common/src/tx_queue_receive.c;Middlewares/ST/threadx/common/src/tx_queue_send.c;Middlewares/ST/threadx/common/src/tx_queue_send_notify.c;Middlewares/ST/threadx/common/src/tx_semaphore_ceiling_put.c;Middlewares/ST/threadx/common/src/tx_semaphore_cleanup.c;Middlewares/ST/threadx/common/src/tx_semaphore_create.c;Middlewares/ST/threadx/common/src/tx_semaphore_delete.c;Middlewares/ST/threadx/common/src/tx_semaphore_get.c;Middlewares/ST/threadx/common/src/tx_semaphore_info_get.c;Middlewares/ST/threadx/common/src/tx_semaphore_initialize.c;Middlewares/ST/threadx/common/src/tx_semaphore_prioritize.c;Middlewares/ST/threadx/common/src/tx_semaphore_put.c;Middlewares/ST/threadx/common/src/tx_semaphore_put_notify.c;Middlewares/ST/threadx/common/src/tx_thread_create.c;Middlewares/ST/threadx/common/src/tx_thread_delete.c;Middlewares/ST/threadx/common/src/tx_thread_entry_exit_notify.c;Middlewares/ST/threadx/common/src/tx_thread_identify.c;Middlewares/ST/threadx/common/src/tx_thread_info_get.c;Middlewares/ST/threadx/common/src/tx_thread_initialize.c;Middlewares/ST/threadx/common/src/tx_thread_preemption_change.c;Middlewares/ST/threadx/common/src/tx_thread_priority_change.c;Middlewares/ST/threadx/common/src/tx_thread_relinquish.c;Middlewares/ST/threadx/common/src/tx_thread_reset.c;Middlewares/ST/threadx/common/src/tx_thread_resume.c;Middlewares/ST/threadx/common/src/tx_thread_shell_entry.c;Middlewares/ST/threadx/common/src/tx_thread_sleep.c;Middlewares/ST/threadx/common/src/tx_thread_stack_analyze.c;Middlewares/ST/threadx/common/src/tx_thread_suspend.c;Middlewares/ST/threadx/common/src/tx_thread_system_preempt_check.c;Middlewares/ST/threadx/common/src/tx_thread_system_suspend.c;Middlewares/ST/threadx/common/src/tx_thread_terminate.c;Middlewares/ST/threadx/common/src/tx_thread_time_slice.c;Middlewares/ST/threadx/common/src/tx_thread_time_slice_change.c;Middlewares/ST/threadx/common/src/tx_thread_timeout.c;Middlewares/ST/threadx/common/src/tx_thread_wait_abort.c;Middlewares/ST/threadx/common/src/tx_time_get.c;Middlewares/ST/threadx/common/src/tx_time_set.c;Middlewares/ST/threadx/common/src/txe_block_allocate.c;Middlewares/ST/threadx/common/src/txe_block_pool_create.c;Middlewares/ST/threadx/common/src/txe_block_pool_delete.c;Middlewares/ST/threadx/common/src/txe_block_pool_info_get.c;Middlewares/ST/threadx/common/src/txe_block_pool_prioritize.c;Middlewares/ST/threadx/common/src/txe_block_release.c;Middlewares/ST/threadx/common/src/txe_byte_allocate.c;Middlewares/ST/threadx/common/src/txe_byte_pool_create.c;Middlewares/ST/threadx/common/src/txe_byte_pool_delete.c;Middlewares/ST/threadx/common/src/txe_byte_pool_info_get.c;Middlewares/ST/threadx/common/src/txe_byte_pool_prioritize.c;Middlewares/ST/threadx/common/src/txe_byte_release.c;Middlewares/ST/threadx/common/src/txe_event_flags_create.c;Middlewares/ST/threadx/common/src/txe_event_flags_delete.c;Middlewares/ST/threadx/common/src/txe_event_flags_get.c;Middlewares/ST/threadx/common/src/txe_event_flags_info_get.c;Middlewares/ST/threadx/common/src/txe_event_flags_set.c;Middlewares/ST/threadx/common/src/txe_event_flags_set_notify.c;Middlewares/ST/threadx/common/src/txe_mutex_create.c;Middlewares/ST/threadx/common/src/txe_mutex_delete.c;Middlewares/ST/threadx/common/src/txe_mutex_get.c;Middlewares/ST/threadx/common/src/txe_mutex_info_get.c;Middlewares/ST/threadx/common/src/txe_mutex_prioritize.c;Middlewares/ST/threadx/common/src/txe_mutex_put.c;Middlewares/ST/threadx/common/src/txe_queue_create.c;Middlewares/ST/threadx/common/src/txe_queue_delete.c;Middlewares/ST/threadx/common/src/txe_queue_flush.c;Middlewares/ST/threadx/common/src/txe_queue_front_send.c;Middlewares/ST/threadx/common/src/txe_queue_info_get.c;Middlewares/ST/threadx/common/src/txe_queue_prioritize.c;Middlewares/ST/threadx/common/src/txe_queue_receive.c;Middlewares/ST/threadx/common/src/txe_queue_send.c;Middlewares/ST/threadx/common/src/txe_queue_send_notify.c;Middlewares/ST/threadx/common/src/txe_semaphore_ceiling_put.c;Middlewares/ST/threadx/common/src/txe_semaphore_create.c;Middlewares/ST/threadx/common/src/txe_semaphore_delete.c;Middlewares/ST/threadx/common/src/txe_semaphore_get.c;Middlewares/ST/threadx/common/src/txe_semaphore_info_get.c;Middlewares/ST/threadx/common/src/txe_semaphore_prioritize.c;Middlewares/ST/threadx/common/src/txe_semaphore_put.c;Middlewares/ST/threadx/common/src/txe_semaphore_put_notify.c;Middlewares/ST/threadx/common/src/txe_thread_create.c;Middlewares/ST/threadx/common/src/txe_thread_delete.c;Middlewares/ST/threadx/common/src/txe_thread_entry_exit_notify.c;Middlewares/ST/threadx/common/src/txe_thread_info_get.c;Middlewares/ST/threadx/common/src/txe_thread_preemption_change.c;Middlewares/ST/threadx/common/src/txe_thread_priority_change.c;Middlewares/ST/threadx/common/src/txe_thread_relinquish.c;Middlewares/ST/threadx/common/src/txe_thread_reset.c;Middlewares/ST/threadx/common/src/txe_thread_resume.c;Middlewares/ST/threadx/common/src/txe_thread_suspend.c;Middlewares/ST/threadx/common/src/txe_thread_terminate.c;Middlewares/ST/threadx/common/src/txe_thread_time_slice_change.c;Middlewares/ST/threadx/common/src/txe_thread_wait_abort.c;Middlewares/ST/threadx/common/src/tx_timer_activate.c;Middlewares/ST/threadx/common/src/tx_timer_change.c;Middlewares/ST/threadx/common/src/tx_timer_create.c;Middlewares/ST/threadx/common/src/tx_timer_deactivate.c;Middlewares/ST/threadx/common/src/tx_timer_delete.c;Middlewares/ST/threadx/common/src/tx_timer_expiration_process.c;Middlewares/ST/threadx/common/src/tx_timer_info_get.c;Middlewares/ST/threadx/common/src/tx_timer_initialize.c;Middlewares/ST/threadx/common/src/tx_timer_system_activate.c;Middlewares/ST/threadx/common/src/tx_timer_system_deactivate.c;Middlewares/ST/threadx/common/src/tx_timer_thread_entry.c;Middlewares/ST/threadx/common/src/txe_timer_activate.c;Middlewares/ST/threadx/common/src/txe_timer_change.c;Middlewares/ST/threadx/common/src/txe_timer_create.c;Middlewares/ST/threadx/common/src/txe_timer_deactivate.c;Middlewares/ST/threadx/common/src/txe_timer_delete.c;Middlewares/ST/threadx/common/src/txe_timer_info_get.c;Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.c;Core/Src/system_stm32h5xx.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_utils.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_xspi.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dlyb.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_sdmmc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_ucpd.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c;Middlewares/ST/filex/common/src/fx_directory_attributes_read.c;Middlewares/ST/filex/common/src/fx_directory_attributes_set.c;Middlewares/ST/filex/common/src/fx_directory_create.c;Middlewares/ST/filex/common/src/fx_directory_default_get.c;Middlewares/ST/filex/common/src/fx_directory_default_get_copy.c;Middlewares/ST/filex/common/src/fx_directory_default_set.c;Middlewares/ST/filex/common/src/fx_directory_delete.c;Middlewares/ST/filex/common/src/fx_directory_entry_read.c;Middlewares/ST/filex/common/src/fx_directory_entry_write.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_entry_read.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_entry_write.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_free_search.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_unicode_entry_write.c;Middlewares/ST/filex/common/src/fx_directory_first_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_first_full_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_free_search.c;Middlewares/ST/filex/common/src/fx_directory_information_get.c;Middlewares/ST/filex/common/src/fx_directory_local_path_clear.c;Middlewares/ST/filex/common/src/fx_directory_local_path_get.c;Middlewares/ST/filex/common/src/fx_directory_local_path_get_copy.c;Middlewares/ST/filex/common/src/fx_directory_local_path_restore.c;Middlewares/ST/filex/common/src/fx_directory_local_path_set.c;Middlewares/ST/filex/common/src/fx_directory_long_name_get.c;Middlewares/ST/filex/common/src/fx_directory_long_name_get_extended.c;Middlewares/ST/filex/common/src/fx_directory_name_extract.c;Middlewares/ST/filex/common/src/fx_directory_name_test.c;Middlewares/ST/filex/common/src/fx_directory_next_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_next_full_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_rename.c;Middlewares/ST/filex/common/src/fx_directory_search.c;Middlewares/ST/filex/common/src/fx_directory_short_name_get.c;Middlewares/ST/filex/common/src/fx_directory_short_name_get_extended.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_bitmap_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_checksum_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_dir_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_FAT_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_apply_logs.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_calculate_checksum.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_cleanup_FAT_chain.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_create_log_file.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_enable.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_read_directory_sector.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_read_FAT.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_read_log_file.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_recover.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_reset_log_file.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_set_FAT_chain.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_end.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_fail.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_start.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_write_log_file.c;Middlewares/ST/filex/common/src/fx_file_allocate.c;Middlewares/ST/filex/common/src/fx_file_attributes_read.c;Middlewares/ST/filex/common/src/fx_file_attributes_set.c;Middlewares/ST/filex/common/src/fx_file_best_effort_allocate.c;Middlewares/ST/filex/common/src/fx_file_close.c;Middlewares/ST/filex/common/src/fx_file_create.c;Middlewares/ST/filex/common/src/fx_file_date_time_set.c;Middlewares/ST/filex/common/src/fx_file_delete.c;Middlewares/ST/filex/common/src/fx_file_extended_allocate.c;Middlewares/ST/filex/common/src/fx_file_extended_best_effort_allocate.c;Middlewares/ST/filex/common/src/fx_file_extended_relative_seek.c;Middlewares/ST/filex/common/src/fx_file_extended_seek.c;Middlewares/ST/filex/common/src/fx_file_extended_truncate.c;Middlewares/ST/filex/common/src/fx_file_extended_truncate_release.c;Middlewares/ST/filex/common/src/fx_file_open.c;Middlewares/ST/filex/common/src/fx_file_read.c;Middlewares/ST/filex/common/src/fx_file_relative_seek.c;Middlewares/ST/filex/common/src/fx_file_rename.c;Middlewares/ST/filex/common/src/fx_file_seek.c;Middlewares/ST/filex/common/src/fx_file_truncate.c;Middlewares/ST/filex/common/src/fx_file_truncate_release.c;Middlewares/ST/filex/common/src/fx_file_write.c;Middlewares/ST/filex/common/src/fx_file_write_notify_set.c;Middlewares/ST/filex/common/src/fx_media_abort.c;Middlewares/ST/filex/common/src/fx_media_boot_info_extract.c;Middlewares/ST/filex/common/src/fx_media_cache_invalidate.c;Middlewares/ST/filex/common/src/fx_media_check.c;Middlewares/ST/filex/common/src/fx_media_check_FAT_chain_check.c;Middlewares/ST/filex/common/src/fx_media_check_lost_cluster_check.c;Middlewares/ST/filex/common/src/fx_media_close.c;Middlewares/ST/filex/common/src/fx_media_close_notify_set.c;Middlewares/ST/filex/common/src/fx_media_exFAT_format.c;Middlewares/ST/filex/common/src/fx_media_extended_space_available.c;Middlewares/ST/filex/common/src/fx_media_flush.c;Middlewares/ST/filex/common/src/fx_media_format.c;Middlewares/ST/filex/common/src/fx_media_format_oem_name_set.c;Middlewares/ST/filex/common/src/fx_media_format_type_set.c;Middlewares/ST/filex/common/src/fx_media_format_volume_id_set.c;Middlewares/ST/filex/common/src/fx_media_open.c;Middlewares/ST/filex/common/src/fx_media_open_notify_set.c;Middlewares/ST/filex/common/src/fx_media_read.c;Middlewares/ST/filex/common/src/fx_media_space_available.c;Middlewares/ST/filex/common/src/fx_media_volume_get.c;Middlewares/ST/filex/common/src/fx_media_volume_get_extended.c;Middlewares/ST/filex/common/src/fx_media_volume_set.c;Middlewares/ST/filex/common/src/fx_media_write.c;Middlewares/ST/filex/common/src/fx_partition_offset_calculate.c;Middlewares/ST/filex/common/src/fx_system_date_get.c;Middlewares/ST/filex/common/src/fx_system_date_set.c;Middlewares/ST/filex/common/src/fx_system_initialize.c;Middlewares/ST/filex/common/src/fx_system_time_get.c;Middlewares/ST/filex/common/src/fx_system_time_set.c;Middlewares/ST/filex/common/src/fx_system_timer_entry.c;Middlewares/ST/filex/common/src/fx_unicode_directory_create.c;Middlewares/ST/filex/common/src/fx_unicode_directory_entry_change.c;Middlewares/ST/filex/common/src/fx_unicode_directory_entry_read.c;Middlewares/ST/filex/common/src/fx_unicode_directory_rename.c;Middlewares/ST/filex/common/src/fx_unicode_directory_search.c;Middlewares/ST/filex/common/src/fx_unicode_file_create.c;Middlewares/ST/filex/common/src/fx_unicode_file_rename.c;Middlewares/ST/filex/common/src/fx_unicode_length_get.c;Middlewares/ST/filex/common/src/fx_unicode_length_get_extended.c;Middlewares/ST/filex/common/src/fx_unicode_name_get.c;Middlewares/ST/filex/common/src/fx_unicode_name_get_extended.c;Middlewares/ST/filex/common/src/fx_unicode_short_name_get.c;Middlewares/ST/filex/common/src/fx_unicode_short_name_get_extended.c;Middlewares/ST/filex/common/src/fx_utility_16_unsigned_read.c;Middlewares/ST/filex/common/src/fx_utility_16_unsigned_write.c;Middlewares/ST/filex/common/src/fx_utility_32_unsigned_read.c;Middlewares/ST/filex/common/src/fx_utility_32_unsigned_write.c;Middlewares/ST/filex/common/src/fx_utility_64_unsigned_read.c;Middlewares/ST/filex/common/src/fx_utility_64_unsigned_write.c;Middlewares/ST/filex/common/src/fx_utility_absolute_path_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_allocate_new_cluster.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_cache_prepare.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_cache_update.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_flush.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_free_cluster_find.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_initialize.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_start_sector_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_free.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_state_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_state_set.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_geometry_check.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_name_hash_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_size_calculate.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_checksum_verify.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_checksum_write.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_format.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_sector_write.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_unicode_name_hash_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_upcase_table.c;Middlewares/ST/filex/common/src/fx_utility_FAT_entry_read.c;Middlewares/ST/filex/common/src/fx_utility_FAT_entry_write.c;Middlewares/ST/filex/common/src/fx_utility_FAT_flush.c;Middlewares/ST/filex/common/src/fx_utility_FAT_map_flush.c;Middlewares/ST/filex/common/src/fx_utility_FAT_sector_get.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_cache_entry_read.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_flush.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_read.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_write.c;Middlewares/ST/filex/common/src/fx_utility_memory_copy.c;Middlewares/ST/filex/common/src/fx_utility_memory_set.c;Middlewares/ST/filex/common/src/fx_utility_string_length_get.c;Middlewares/ST/filex/common/src/fx_utility_token_length_get.c;Middlewares/ST/filex/common/src/fxe_directory_attributes_read.c;Middlewares/ST/filex/common/src/fxe_directory_attributes_set.c;Middlewares/ST/filex/common/src/fxe_directory_create.c;Middlewares/ST/filex/common/src/fxe_directory_default_get.c;Middlewares/ST/filex/common/src/fxe_directory_default_get_copy.c;Middlewares/ST/filex/common/src/fxe_directory_default_set.c;Middlewares/ST/filex/common/src/fxe_directory_delete.c;Middlewares/ST/filex/common/src/fxe_directory_first_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_first_full_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_information_get.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_clear.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_get.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_get_copy.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_restore.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_set.c;Middlewares/ST/filex/common/src/fxe_directory_long_name_get.c;Middlewares/ST/filex/common/src/fxe_directory_long_name_get_extended.c;Middlewares/ST/filex/common/src/fxe_directory_name_test.c;Middlewares/ST/filex/common/src/fxe_directory_next_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_next_full_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_rename.c;Middlewares/ST/filex/common/src/fxe_directory_short_name_get.c;Middlewares/ST/filex/common/src/fxe_directory_short_name_get_extended.c;Middlewares/ST/filex/common/src/fxe_fault_tolerant_enable.c;Middlewares/ST/filex/common/src/fxe_file_allocate.c;Middlewares/ST/filex/common/src/fxe_file_attributes_read.c;Middlewares/ST/filex/common/src/fxe_file_attributes_set.c;Middlewares/ST/filex/common/src/fxe_file_best_effort_allocate.c;Middlewares/ST/filex/common/src/fxe_file_close.c;Middlewares/ST/filex/common/src/fxe_file_create.c;Middlewares/ST/filex/common/src/fxe_file_date_time_set.c;Middlewares/ST/filex/common/src/fxe_file_delete.c;Middlewares/ST/filex/common/src/fxe_file_extended_allocate.c;Middlewares/ST/filex/common/src/fxe_file_extended_best_effort_allocate.c;Middlewares/ST/filex/common/src/fxe_file_extended_relative_seek.c;Middlewares/ST/filex/common/src/fxe_file_extended_seek.c;Middlewares/ST/filex/common/src/fxe_file_extended_truncate.c;Middlewares/ST/filex/common/src/fxe_file_extended_truncate_release.c;Middlewares/ST/filex/common/src/fxe_file_open.c;Middlewares/ST/filex/common/src/fxe_file_read.c;Middlewares/ST/filex/common/src/fxe_file_relative_seek.c;Middlewares/ST/filex/common/src/fxe_file_rename.c;Middlewares/ST/filex/common/src/fxe_file_seek.c;Middlewares/ST/filex/common/src/fxe_file_truncate.c;Middlewares/ST/filex/common/src/fxe_file_truncate_release.c;Middlewares/ST/filex/common/src/fxe_file_write.c;Middlewares/ST/filex/common/src/fxe_file_write_notify_set.c;Middlewares/ST/filex/common/src/fxe_media_abort.c;Middlewares/ST/filex/common/src/fxe_media_cache_invalidate.c;Middlewares/ST/filex/common/src/fxe_media_check.c;Middlewares/ST/filex/common/src/fxe_media_close.c;Middlewares/ST/filex/common/src/fxe_media_close_notify_set.c;Middlewares/ST/filex/common/src/fxe_media_exFAT_format.c;Middlewares/ST/filex/common/src/fxe_media_extended_space_available.c;Middlewares/ST/filex/common/src/fxe_media_flush.c;Middlewares/ST/filex/common/src/fxe_media_format.c;Middlewares/ST/filex/common/src/fxe_media_open.c;Middlewares/ST/filex/common/src/fxe_media_open_notify_set.c;Middlewares/ST/filex/common/src/fxe_media_read.c;Middlewares/ST/filex/common/src/fxe_media_space_available.c;Middlewares/ST/filex/common/src/fxe_media_volume_get.c;Middlewares/ST/filex/common/src/fxe_media_volume_get_extended.c;Middlewares/ST/filex/common/src/fxe_media_volume_set.c;Middlewares/ST/filex/common/src/fxe_media_write.c;Middlewares/ST/filex/common/src/fxe_system_date_get.c;Middlewares/ST/filex/common/src/fxe_system_date_set.c;Middlewares/ST/filex/common/src/fxe_system_time_get.c;Middlewares/ST/filex/common/src/fxe_system_time_set.c;Middlewares/ST/filex/common/src/fxe_unicode_directory_create.c;Middlewares/ST/filex/common/src/fxe_unicode_directory_rename.c;Middlewares/ST/filex/common/src/fxe_unicode_file_create.c;Middlewares/ST/filex/common/src/fxe_unicode_file_rename.c;Middlewares/ST/filex/common/src/fxe_unicode_name_get.c;Middlewares/ST/filex/common/src/fxe_unicode_name_get_extended.c;Middlewares/ST/filex/common/src/fxe_unicode_short_name_get.c;Middlewares/ST/filex/common/src/fxe_unicode_short_name_get_extended.c;Middlewares/ST/filex/common/drivers/fx_stm32_sd_driver.c;Middlewares/ST/threadx/common/src/tx_initialize_high_level.c;Middlewares/ST/threadx/common/src/tx_initialize_kernel_enter.c;Middlewares/ST/threadx/common/src/tx_initialize_kernel_setup.c;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_context_restore.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_context_save.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_interrupt_control.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_interrupt_disable.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_interrupt_restore.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_schedule.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_stack_build.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_system_return.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_timer_interrupt.S;Middlewares/ST/threadx/common/src/tx_thread_stack_error_handler.c;Middlewares/ST/threadx/common/src/tx_thread_stack_error_notify.c;Middlewares/ST/threadx/common/src/tx_thread_system_resume.c;Middlewares/ST/threadx/common/src/tx_block_allocate.c;Middlewares/ST/threadx/common/src/tx_block_pool_cleanup.c;Middlewares/ST/threadx/common/src/tx_block_pool_create.c;Middlewares/ST/threadx/common/src/tx_block_pool_delete.c;Middlewares/ST/threadx/common/src/tx_block_pool_info_get.c;Middlewares/ST/threadx/common/src/tx_block_pool_initialize.c;Middlewares/ST/threadx/common/src/tx_block_pool_prioritize.c;Middlewares/ST/threadx/common/src/tx_block_release.c;Middlewares/ST/threadx/common/src/tx_byte_allocate.c;Middlewares/ST/threadx/common/src/tx_byte_pool_cleanup.c;Middlewares/ST/threadx/common/src/tx_byte_pool_create.c;Middlewares/ST/threadx/common/src/tx_byte_pool_delete.c;Middlewares/ST/threadx/common/src/tx_byte_pool_info_get.c;Middlewares/ST/threadx/common/src/tx_byte_pool_initialize.c;Middlewares/ST/threadx/common/src/tx_byte_pool_prioritize.c;Middlewares/ST/threadx/common/src/tx_byte_pool_search.c;Middlewares/ST/threadx/common/src/tx_byte_release.c;Middlewares/ST/threadx/common/src/tx_event_flags_cleanup.c;Middlewares/ST/threadx/common/src/tx_event_flags_create.c;Middlewares/ST/threadx/common/src/tx_event_flags_delete.c;Middlewares/ST/threadx/common/src/tx_event_flags_get.c;Middlewares/ST/threadx/common/src/tx_event_flags_info_get.c;Middlewares/ST/threadx/common/src/tx_event_flags_initialize.c;Middlewares/ST/threadx/common/src/tx_event_flags_set.c;Middlewares/ST/threadx/common/src/tx_event_flags_set_notify.c;Middlewares/ST/threadx/common/src/tx_mutex_cleanup.c;Middlewares/ST/threadx/common/src/tx_mutex_create.c;Middlewares/ST/threadx/common/src/tx_mutex_delete.c;Middlewares/ST/threadx/common/src/tx_mutex_get.c;Middlewares/ST/threadx/common/src/tx_mutex_info_get.c;Middlewares/ST/threadx/common/src/tx_mutex_initialize.c;Middlewares/ST/threadx/common/src/tx_mutex_prioritize.c;Middlewares/ST/threadx/common/src/tx_mutex_priority_change.c;Middlewares/ST/threadx/common/src/tx_mutex_put.c;Middlewares/ST/threadx/common/src/tx_queue_cleanup.c;Middlewares/ST/threadx/common/src/tx_queue_create.c;Middlewares/ST/threadx/common/src/tx_queue_delete.c;Middlewares/ST/threadx/common/src/tx_queue_flush.c;Middlewares/ST/threadx/common/src/tx_queue_front_send.c;Middlewares/ST/threadx/common/src/tx_queue_info_get.c;Middlewares/ST/threadx/common/src/tx_queue_initialize.c;Middlewares/ST/threadx/common/src/tx_queue_prioritize.c;Middlewares/ST/threadx/common/src/tx_queue_receive.c;Middlewares/ST/threadx/common/src/tx_queue_send.c;Middlewares/ST/threadx/common/src/tx_queue_send_notify.c;Middlewares/ST/threadx/common/src/tx_semaphore_ceiling_put.c;Middlewares/ST/threadx/common/src/tx_semaphore_cleanup.c;Middlewares/ST/threadx/common/src/tx_semaphore_create.c;Middlewares/ST/threadx/common/src/tx_semaphore_delete.c;Middlewares/ST/threadx/common/src/tx_semaphore_get.c;Middlewares/ST/threadx/common/src/tx_semaphore_info_get.c;Middlewares/ST/threadx/common/src/tx_semaphore_initialize.c;Middlewares/ST/threadx/common/src/tx_semaphore_prioritize.c;Middlewares/ST/threadx/common/src/tx_semaphore_put.c;Middlewares/ST/threadx/common/src/tx_semaphore_put_notify.c;Middlewares/ST/threadx/common/src/tx_thread_create.c;Middlewares/ST/threadx/common/src/tx_thread_delete.c;Middlewares/ST/threadx/common/src/tx_thread_entry_exit_notify.c;Middlewares/ST/threadx/common/src/tx_thread_identify.c;Middlewares/ST/threadx/common/src/tx_thread_info_get.c;Middlewares/ST/threadx/common/src/tx_thread_initialize.c;Middlewares/ST/threadx/common/src/tx_thread_preemption_change.c;Middlewares/ST/threadx/common/src/tx_thread_priority_change.c;Middlewares/ST/threadx/common/src/tx_thread_relinquish.c;Middlewares/ST/threadx/common/src/tx_thread_reset.c;Middlewares/ST/threadx/common/src/tx_thread_resume.c;Middlewares/ST/threadx/common/src/tx_thread_shell_entry.c;Middlewares/ST/threadx/common/src/tx_thread_sleep.c;Middlewares/ST/threadx/common/src/tx_thread_stack_analyze.c;Middlewares/ST/threadx/common/src/tx_thread_suspend.c;Middlewares/ST/threadx/common/src/tx_thread_system_preempt_check.c;Middlewares/ST/threadx/common/src/tx_thread_system_suspend.c;Middlewares/ST/threadx/common/src/tx_thread_terminate.c;Middlewares/ST/threadx/common/src/tx_thread_time_slice.c;Middlewares/ST/threadx/common/src/tx_thread_time_slice_change.c;Middlewares/ST/threadx/common/src/tx_thread_timeout.c;Middlewares/ST/threadx/common/src/tx_thread_wait_abort.c;Middlewares/ST/threadx/common/src/tx_time_get.c;Middlewares/ST/threadx/common/src/tx_time_set.c;Middlewares/ST/threadx/common/src/txe_block_allocate.c;Middlewares/ST/threadx/common/src/txe_block_pool_create.c;Middlewares/ST/threadx/common/src/txe_block_pool_delete.c;Middlewares/ST/threadx/common/src/txe_block_pool_info_get.c;Middlewares/ST/threadx/common/src/txe_block_pool_prioritize.c;Middlewares/ST/threadx/common/src/txe_block_release.c;Middlewares/ST/threadx/common/src/txe_byte_allocate.c;Middlewares/ST/threadx/common/src/txe_byte_pool_create.c;Middlewares/ST/threadx/common/src/txe_byte_pool_delete.c;Middlewares/ST/threadx/common/src/txe_byte_pool_info_get.c;Middlewares/ST/threadx/common/src/txe_byte_pool_prioritize.c;Middlewares/ST/threadx/common/src/txe_byte_release.c;Middlewares/ST/threadx/common/src/txe_event_flags_create.c;Middlewares/ST/threadx/common/src/txe_event_flags_delete.c;Middlewares/ST/threadx/common/src/txe_event_flags_get.c;Middlewares/ST/threadx/common/src/txe_event_flags_info_get.c;Middlewares/ST/threadx/common/src/txe_event_flags_set.c;Middlewares/ST/threadx/common/src/txe_event_flags_set_notify.c;Middlewares/ST/threadx/common/src/txe_mutex_create.c;Middlewares/ST/threadx/common/src/txe_mutex_delete.c;Middlewares/ST/threadx/common/src/txe_mutex_get.c;Middlewares/ST/threadx/common/src/txe_mutex_info_get.c;Middlewares/ST/threadx/common/src/txe_mutex_prioritize.c;Middlewares/ST/threadx/common/src/txe_mutex_put.c;Middlewares/ST/threadx/common/src/txe_queue_create.c;Middlewares/ST/threadx/common/src/txe_queue_delete.c;Middlewares/ST/threadx/common/src/txe_queue_flush.c;Middlewares/ST/threadx/common/src/txe_queue_front_send.c;Middlewares/ST/threadx/common/src/txe_queue_info_get.c;Middlewares/ST/threadx/common/src/txe_queue_prioritize.c;Middlewares/ST/threadx/common/src/txe_queue_receive.c;Middlewares/ST/threadx/common/src/txe_queue_send.c;Middlewares/ST/threadx/common/src/txe_queue_send_notify.c;Middlewares/ST/threadx/common/src/txe_semaphore_ceiling_put.c;Middlewares/ST/threadx/common/src/txe_semaphore_create.c;Middlewares/ST/threadx/common/src/txe_semaphore_delete.c;Middlewares/ST/threadx/common/src/txe_semaphore_get.c;Middlewares/ST/threadx/common/src/txe_semaphore_info_get.c;Middlewares/ST/threadx/common/src/txe_semaphore_prioritize.c;Middlewares/ST/threadx/common/src/txe_semaphore_put.c;Middlewares/ST/threadx/common/src/txe_semaphore_put_notify.c;Middlewares/ST/threadx/common/src/txe_thread_create.c;Middlewares/ST/threadx/common/src/txe_thread_delete.c;Middlewares/ST/threadx/common/src/txe_thread_entry_exit_notify.c;Middlewares/ST/threadx/common/src/txe_thread_info_get.c;Middlewares/ST/threadx/common/src/txe_thread_preemption_change.c;Middlewares/ST/threadx/common/src/txe_thread_priority_change.c;Middlewares/ST/threadx/common/src/txe_thread_relinquish.c;Middlewares/ST/threadx/common/src/txe_thread_reset.c;Middlewares/ST/threadx/common/src/txe_thread_resume.c;Middlewares/ST/threadx/common/src/txe_thread_suspend.c;Middlewares/ST/threadx/common/src/txe_thread_terminate.c;Middlewares/ST/threadx/common/src/txe_thread_time_slice_change.c;Middlewares/ST/threadx/common/src/txe_thread_wait_abort.c;Middlewares/ST/threadx/common/src/tx_timer_activate.c;Middlewares/ST/threadx/common/src/tx_timer_change.c;Middlewares/ST/threadx/common/src/tx_timer_create.c;Middlewares/ST/threadx/common/src/tx_timer_deactivate.c;Middlewares/ST/threadx/common/src/tx_timer_delete.c;Middlewares/ST/threadx/common/src/tx_timer_expiration_process.c;Middlewares/ST/threadx/common/src/tx_timer_info_get.c;Middlewares/ST/threadx/common/src/tx_timer_initialize.c;Middlewares/ST/threadx/common/src/tx_timer_system_activate.c;Middlewares/ST/threadx/common/src/tx_timer_system_deactivate.c;Middlewares/ST/threadx/common/src/tx_timer_thread_entry.c;Middlewares/ST/threadx/common/src/txe_timer_activate.c;Middlewares/ST/threadx/common/src/txe_timer_change.c;Middlewares/ST/threadx/common/src/txe_timer_create.c;Middlewares/ST/threadx/common/src/txe_timer_deactivate.c;Middlewares/ST/threadx/common/src/txe_timer_delete.c;Middlewares/ST/threadx/common/src/txe_timer_info_get.c;Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.c;Core/Src/system_stm32h5xx.c;;; -HeaderPath=Drivers/STM32H5xx_HAL_Driver/Inc;Drivers/STM32H5xx_HAL_Driver/Inc/Legacy;Middlewares/ST/threadx/common/inc;Drivers/CMSIS/Device/ST/STM32H5xx/Include;Middlewares/ST/filex/common/inc;Middlewares/ST/filex/ports/generic/inc;Middlewares/ST/threadx/ports/cortex_m33/gnu/inc;Drivers/CMSIS/Include;Core/Inc;FileX/App;FileX/Target;AZURE_RTOS/App; -CDefines=USE_FULL_LL_DRIVER;FX_INCLUDE_USER_DEFINE_FILE;TX_INCLUDE_USER_DEFINE_FILE;TX_SINGLE_MODE_NON_SECURE:1;USE_FULL_LL_DRIVER;USE_HAL_DRIVER;STM32H573xx;USE_FULL_LL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; -ADefines=TX_SINGLE_MODE_NON_SECURE:1; - -[PreviousGenFiles] -AdvancedFolderStructure=true -HeaderFileListSize=24 -HeaderFiles#0=../Core/Inc/gpio.h -HeaderFiles#1=../Core/Inc/adc.h -HeaderFiles#2=../Core/Inc/eth.h -HeaderFiles#3=../FileX/App/app_filex.h -HeaderFiles#4=../FileX/App/fx_user.h -HeaderFiles#5=../FileX/Target/fx_stm32_sd_driver.h -HeaderFiles#6=../Core/Inc/fmc.h -HeaderFiles#7=../Core/Inc/gpdma.h -HeaderFiles#8=../Core/Inc/icache.h -HeaderFiles#9=../Core/Inc/linked_list.h -HeaderFiles#10=../Core/Inc/memorymap.h -HeaderFiles#11=../Core/Inc/octospi.h -HeaderFiles#12=../Core/Inc/sai.h -HeaderFiles#13=../Core/Inc/sdmmc.h -HeaderFiles#14=../Core/Inc/app_threadx.h -HeaderFiles#15=../AZURE_RTOS/App/app_azure_rtos.h -HeaderFiles#16=../Core/Inc/tx_user.h -HeaderFiles#17=../AZURE_RTOS/App/app_azure_rtos_config.h -HeaderFiles#18=../Core/Inc/ucpd.h -HeaderFiles#19=../Core/Inc/usart.h -HeaderFiles#20=../Core/Inc/stm32h5xx_it.h -HeaderFiles#21=../Core/Inc/stm32_assert.h -HeaderFiles#22=../Core/Inc/stm32h5xx_hal_conf.h -HeaderFiles#23=../Core/Inc/main.h -HeaderFolderListSize=4 -HeaderPath#0=../Core/Inc -HeaderPath#1=../FileX/App -HeaderPath#2=../FileX/Target -HeaderPath#3=../AZURE_RTOS/App -HeaderFiles=; -SourceFileListSize=22 -SourceFiles#0=../Core/Src/tx_initialize_low_level.S -SourceFiles#1=../Core/Src/gpio.c -SourceFiles#2=../Core/Src/adc.c -SourceFiles#3=../Core/Src/eth.c -SourceFiles#4=../FileX/App/app_filex.c -SourceFiles#5=../FileX/Target/fx_stm32_sd_driver_glue.c -SourceFiles#6=../Core/Src/fmc.c -SourceFiles#7=../Core/Src/gpdma.c -SourceFiles#8=../Core/Src/icache.c -SourceFiles#9=../Core/Src/linked_list.c -SourceFiles#10=../Core/Src/memorymap.c -SourceFiles#11=../Core/Src/octospi.c -SourceFiles#12=../Core/Src/sai.c -SourceFiles#13=../Core/Src/sdmmc.c -SourceFiles#14=../Core/Src/app_threadx.c -SourceFiles#15=../AZURE_RTOS/App/app_azure_rtos.c -SourceFiles#16=../Core/Src/ucpd.c -SourceFiles#17=../Core/Src/usart.c -SourceFiles#18=../Core/Src/stm32h5xx_it.c -SourceFiles#19=../Core/Src/stm32h5xx_hal_msp.c -SourceFiles#20=../Core/Src/stm32h5xx_hal_timebase_tim.c -SourceFiles#21=../Core/Src/main.c -SourceFolderListSize=4 -SourcePath#0=../Core/Src -SourcePath#1=../FileX/App -SourcePath#2=../FileX/Target -SourcePath#3=../AZURE_RTOS/App -SourceFiles=; - +[PreviousLibFiles] +LibFiles=Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crs.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dmamux.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h;Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_utils.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_fmc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sram.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i2c.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_xspi.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dlyb.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sai.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sai_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_sdmmc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sd.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sd_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_tim.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_ucpd.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_usart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_lpuart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h;Middlewares/ST/threadx/common/inc/tx_api.h;Middlewares/ST/threadx/common/inc/tx_block_pool.h;Middlewares/ST/threadx/common/inc/tx_byte_pool.h;Middlewares/ST/threadx/common/inc/tx_event_flags.h;Middlewares/ST/threadx/common/inc/tx_initialize.h;Middlewares/ST/threadx/common/inc/tx_mutex.h;Middlewares/ST/threadx/common/inc/tx_queue.h;Middlewares/ST/threadx/common/inc/tx_semaphore.h;Middlewares/ST/threadx/common/inc/tx_thread.h;Middlewares/ST/threadx/common/inc/tx_timer.h;Middlewares/ST/threadx/common/inc/tx_trace.h;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_xspi.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dlyb.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_sdmmc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_ucpd.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c;Middlewares/ST/filex/common/src/fx_directory_attributes_read.c;Middlewares/ST/filex/common/src/fx_directory_attributes_set.c;Middlewares/ST/filex/common/src/fx_directory_create.c;Middlewares/ST/filex/common/src/fx_directory_default_get.c;Middlewares/ST/filex/common/src/fx_directory_default_get_copy.c;Middlewares/ST/filex/common/src/fx_directory_default_set.c;Middlewares/ST/filex/common/src/fx_directory_delete.c;Middlewares/ST/filex/common/src/fx_directory_entry_read.c;Middlewares/ST/filex/common/src/fx_directory_entry_write.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_entry_read.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_entry_write.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_free_search.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_unicode_entry_write.c;Middlewares/ST/filex/common/src/fx_directory_first_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_first_full_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_free_search.c;Middlewares/ST/filex/common/src/fx_directory_information_get.c;Middlewares/ST/filex/common/src/fx_directory_local_path_clear.c;Middlewares/ST/filex/common/src/fx_directory_local_path_get.c;Middlewares/ST/filex/common/src/fx_directory_local_path_get_copy.c;Middlewares/ST/filex/common/src/fx_directory_local_path_restore.c;Middlewares/ST/filex/common/src/fx_directory_local_path_set.c;Middlewares/ST/filex/common/src/fx_directory_long_name_get.c;Middlewares/ST/filex/common/src/fx_directory_long_name_get_extended.c;Middlewares/ST/filex/common/src/fx_directory_name_extract.c;Middlewares/ST/filex/common/src/fx_directory_name_test.c;Middlewares/ST/filex/common/src/fx_directory_next_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_next_full_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_rename.c;Middlewares/ST/filex/common/src/fx_directory_search.c;Middlewares/ST/filex/common/src/fx_directory_short_name_get.c;Middlewares/ST/filex/common/src/fx_directory_short_name_get_extended.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_bitmap_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_checksum_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_dir_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_FAT_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_apply_logs.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_calculate_checksum.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_cleanup_FAT_chain.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_create_log_file.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_enable.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_read_directory_sector.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_read_FAT.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_read_log_file.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_recover.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_reset_log_file.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_set_FAT_chain.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_end.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_fail.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_start.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_write_log_file.c;Middlewares/ST/filex/common/src/fx_file_allocate.c;Middlewares/ST/filex/common/src/fx_file_attributes_read.c;Middlewares/ST/filex/common/src/fx_file_attributes_set.c;Middlewares/ST/filex/common/src/fx_file_best_effort_allocate.c;Middlewares/ST/filex/common/src/fx_file_close.c;Middlewares/ST/filex/common/src/fx_file_create.c;Middlewares/ST/filex/common/src/fx_file_date_time_set.c;Middlewares/ST/filex/common/src/fx_file_delete.c;Middlewares/ST/filex/common/src/fx_file_extended_allocate.c;Middlewares/ST/filex/common/src/fx_file_extended_best_effort_allocate.c;Middlewares/ST/filex/common/src/fx_file_extended_relative_seek.c;Middlewares/ST/filex/common/src/fx_file_extended_seek.c;Middlewares/ST/filex/common/src/fx_file_extended_truncate.c;Middlewares/ST/filex/common/src/fx_file_extended_truncate_release.c;Middlewares/ST/filex/common/src/fx_file_open.c;Middlewares/ST/filex/common/src/fx_file_read.c;Middlewares/ST/filex/common/src/fx_file_relative_seek.c;Middlewares/ST/filex/common/src/fx_file_rename.c;Middlewares/ST/filex/common/src/fx_file_seek.c;Middlewares/ST/filex/common/src/fx_file_truncate.c;Middlewares/ST/filex/common/src/fx_file_truncate_release.c;Middlewares/ST/filex/common/src/fx_file_write.c;Middlewares/ST/filex/common/src/fx_file_write_notify_set.c;Middlewares/ST/filex/common/src/fx_media_abort.c;Middlewares/ST/filex/common/src/fx_media_boot_info_extract.c;Middlewares/ST/filex/common/src/fx_media_cache_invalidate.c;Middlewares/ST/filex/common/src/fx_media_check.c;Middlewares/ST/filex/common/src/fx_media_check_FAT_chain_check.c;Middlewares/ST/filex/common/src/fx_media_check_lost_cluster_check.c;Middlewares/ST/filex/common/src/fx_media_close.c;Middlewares/ST/filex/common/src/fx_media_close_notify_set.c;Middlewares/ST/filex/common/src/fx_media_exFAT_format.c;Middlewares/ST/filex/common/src/fx_media_extended_space_available.c;Middlewares/ST/filex/common/src/fx_media_flush.c;Middlewares/ST/filex/common/src/fx_media_format.c;Middlewares/ST/filex/common/src/fx_media_format_oem_name_set.c;Middlewares/ST/filex/common/src/fx_media_format_type_set.c;Middlewares/ST/filex/common/src/fx_media_format_volume_id_set.c;Middlewares/ST/filex/common/src/fx_media_open.c;Middlewares/ST/filex/common/src/fx_media_open_notify_set.c;Middlewares/ST/filex/common/src/fx_media_read.c;Middlewares/ST/filex/common/src/fx_media_space_available.c;Middlewares/ST/filex/common/src/fx_media_volume_get.c;Middlewares/ST/filex/common/src/fx_media_volume_get_extended.c;Middlewares/ST/filex/common/src/fx_media_volume_set.c;Middlewares/ST/filex/common/src/fx_media_write.c;Middlewares/ST/filex/common/src/fx_partition_offset_calculate.c;Middlewares/ST/filex/common/src/fx_system_date_get.c;Middlewares/ST/filex/common/src/fx_system_date_set.c;Middlewares/ST/filex/common/src/fx_system_initialize.c;Middlewares/ST/filex/common/src/fx_system_time_get.c;Middlewares/ST/filex/common/src/fx_system_time_set.c;Middlewares/ST/filex/common/src/fx_system_timer_entry.c;Middlewares/ST/filex/common/src/fx_unicode_directory_create.c;Middlewares/ST/filex/common/src/fx_unicode_directory_entry_change.c;Middlewares/ST/filex/common/src/fx_unicode_directory_entry_read.c;Middlewares/ST/filex/common/src/fx_unicode_directory_rename.c;Middlewares/ST/filex/common/src/fx_unicode_directory_search.c;Middlewares/ST/filex/common/src/fx_unicode_file_create.c;Middlewares/ST/filex/common/src/fx_unicode_file_rename.c;Middlewares/ST/filex/common/src/fx_unicode_length_get.c;Middlewares/ST/filex/common/src/fx_unicode_length_get_extended.c;Middlewares/ST/filex/common/src/fx_unicode_name_get.c;Middlewares/ST/filex/common/src/fx_unicode_name_get_extended.c;Middlewares/ST/filex/common/src/fx_unicode_short_name_get.c;Middlewares/ST/filex/common/src/fx_unicode_short_name_get_extended.c;Middlewares/ST/filex/common/src/fx_utility_16_unsigned_read.c;Middlewares/ST/filex/common/src/fx_utility_16_unsigned_write.c;Middlewares/ST/filex/common/src/fx_utility_32_unsigned_read.c;Middlewares/ST/filex/common/src/fx_utility_32_unsigned_write.c;Middlewares/ST/filex/common/src/fx_utility_64_unsigned_read.c;Middlewares/ST/filex/common/src/fx_utility_64_unsigned_write.c;Middlewares/ST/filex/common/src/fx_utility_absolute_path_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_allocate_new_cluster.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_cache_prepare.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_cache_update.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_flush.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_free_cluster_find.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_initialize.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_start_sector_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_free.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_state_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_state_set.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_geometry_check.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_name_hash_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_size_calculate.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_checksum_verify.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_checksum_write.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_format.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_sector_write.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_unicode_name_hash_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_upcase_table.c;Middlewares/ST/filex/common/src/fx_utility_FAT_entry_read.c;Middlewares/ST/filex/common/src/fx_utility_FAT_entry_write.c;Middlewares/ST/filex/common/src/fx_utility_FAT_flush.c;Middlewares/ST/filex/common/src/fx_utility_FAT_map_flush.c;Middlewares/ST/filex/common/src/fx_utility_FAT_sector_get.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_cache_entry_read.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_flush.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_read.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_write.c;Middlewares/ST/filex/common/src/fx_utility_memory_copy.c;Middlewares/ST/filex/common/src/fx_utility_memory_set.c;Middlewares/ST/filex/common/src/fx_utility_string_length_get.c;Middlewares/ST/filex/common/src/fx_utility_token_length_get.c;Middlewares/ST/filex/common/src/fxe_directory_attributes_read.c;Middlewares/ST/filex/common/src/fxe_directory_attributes_set.c;Middlewares/ST/filex/common/src/fxe_directory_create.c;Middlewares/ST/filex/common/src/fxe_directory_default_get.c;Middlewares/ST/filex/common/src/fxe_directory_default_get_copy.c;Middlewares/ST/filex/common/src/fxe_directory_default_set.c;Middlewares/ST/filex/common/src/fxe_directory_delete.c;Middlewares/ST/filex/common/src/fxe_directory_first_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_first_full_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_information_get.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_clear.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_get.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_get_copy.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_restore.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_set.c;Middlewares/ST/filex/common/src/fxe_directory_long_name_get.c;Middlewares/ST/filex/common/src/fxe_directory_long_name_get_extended.c;Middlewares/ST/filex/common/src/fxe_directory_name_test.c;Middlewares/ST/filex/common/src/fxe_directory_next_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_next_full_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_rename.c;Middlewares/ST/filex/common/src/fxe_directory_short_name_get.c;Middlewares/ST/filex/common/src/fxe_directory_short_name_get_extended.c;Middlewares/ST/filex/common/src/fxe_fault_tolerant_enable.c;Middlewares/ST/filex/common/src/fxe_file_allocate.c;Middlewares/ST/filex/common/src/fxe_file_attributes_read.c;Middlewares/ST/filex/common/src/fxe_file_attributes_set.c;Middlewares/ST/filex/common/src/fxe_file_best_effort_allocate.c;Middlewares/ST/filex/common/src/fxe_file_close.c;Middlewares/ST/filex/common/src/fxe_file_create.c;Middlewares/ST/filex/common/src/fxe_file_date_time_set.c;Middlewares/ST/filex/common/src/fxe_file_delete.c;Middlewares/ST/filex/common/src/fxe_file_extended_allocate.c;Middlewares/ST/filex/common/src/fxe_file_extended_best_effort_allocate.c;Middlewares/ST/filex/common/src/fxe_file_extended_relative_seek.c;Middlewares/ST/filex/common/src/fxe_file_extended_seek.c;Middlewares/ST/filex/common/src/fxe_file_extended_truncate.c;Middlewares/ST/filex/common/src/fxe_file_extended_truncate_release.c;Middlewares/ST/filex/common/src/fxe_file_open.c;Middlewares/ST/filex/common/src/fxe_file_read.c;Middlewares/ST/filex/common/src/fxe_file_relative_seek.c;Middlewares/ST/filex/common/src/fxe_file_rename.c;Middlewares/ST/filex/common/src/fxe_file_seek.c;Middlewares/ST/filex/common/src/fxe_file_truncate.c;Middlewares/ST/filex/common/src/fxe_file_truncate_release.c;Middlewares/ST/filex/common/src/fxe_file_write.c;Middlewares/ST/filex/common/src/fxe_file_write_notify_set.c;Middlewares/ST/filex/common/src/fxe_media_abort.c;Middlewares/ST/filex/common/src/fxe_media_cache_invalidate.c;Middlewares/ST/filex/common/src/fxe_media_check.c;Middlewares/ST/filex/common/src/fxe_media_close.c;Middlewares/ST/filex/common/src/fxe_media_close_notify_set.c;Middlewares/ST/filex/common/src/fxe_media_exFAT_format.c;Middlewares/ST/filex/common/src/fxe_media_extended_space_available.c;Middlewares/ST/filex/common/src/fxe_media_flush.c;Middlewares/ST/filex/common/src/fxe_media_format.c;Middlewares/ST/filex/common/src/fxe_media_open.c;Middlewares/ST/filex/common/src/fxe_media_open_notify_set.c;Middlewares/ST/filex/common/src/fxe_media_read.c;Middlewares/ST/filex/common/src/fxe_media_space_available.c;Middlewares/ST/filex/common/src/fxe_media_volume_get.c;Middlewares/ST/filex/common/src/fxe_media_volume_get_extended.c;Middlewares/ST/filex/common/src/fxe_media_volume_set.c;Middlewares/ST/filex/common/src/fxe_media_write.c;Middlewares/ST/filex/common/src/fxe_system_date_get.c;Middlewares/ST/filex/common/src/fxe_system_date_set.c;Middlewares/ST/filex/common/src/fxe_system_time_get.c;Middlewares/ST/filex/common/src/fxe_system_time_set.c;Middlewares/ST/filex/common/src/fxe_unicode_directory_create.c;Middlewares/ST/filex/common/src/fxe_unicode_directory_rename.c;Middlewares/ST/filex/common/src/fxe_unicode_file_create.c;Middlewares/ST/filex/common/src/fxe_unicode_file_rename.c;Middlewares/ST/filex/common/src/fxe_unicode_name_get.c;Middlewares/ST/filex/common/src/fxe_unicode_name_get_extended.c;Middlewares/ST/filex/common/src/fxe_unicode_short_name_get.c;Middlewares/ST/filex/common/src/fxe_unicode_short_name_get_extended.c;Middlewares/ST/filex/common/drivers/fx_stm32_sd_driver.c;Middlewares/ST/threadx/common/src/tx_initialize_high_level.c;Middlewares/ST/threadx/common/src/tx_initialize_kernel_enter.c;Middlewares/ST/threadx/common/src/tx_initialize_kernel_setup.c;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_context_restore.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_context_save.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_interrupt_control.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_interrupt_disable.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_interrupt_restore.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_schedule.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_stack_build.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_system_return.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_timer_interrupt.S;Middlewares/ST/threadx/common/src/tx_thread_stack_error_handler.c;Middlewares/ST/threadx/common/src/tx_thread_stack_error_notify.c;Middlewares/ST/threadx/common/src/tx_thread_system_resume.c;Middlewares/ST/threadx/common/src/tx_block_allocate.c;Middlewares/ST/threadx/common/src/tx_block_pool_cleanup.c;Middlewares/ST/threadx/common/src/tx_block_pool_create.c;Middlewares/ST/threadx/common/src/tx_block_pool_delete.c;Middlewares/ST/threadx/common/src/tx_block_pool_info_get.c;Middlewares/ST/threadx/common/src/tx_block_pool_initialize.c;Middlewares/ST/threadx/common/src/tx_block_pool_prioritize.c;Middlewares/ST/threadx/common/src/tx_block_release.c;Middlewares/ST/threadx/common/src/tx_byte_allocate.c;Middlewares/ST/threadx/common/src/tx_byte_pool_cleanup.c;Middlewares/ST/threadx/common/src/tx_byte_pool_create.c;Middlewares/ST/threadx/common/src/tx_byte_pool_delete.c;Middlewares/ST/threadx/common/src/tx_byte_pool_info_get.c;Middlewares/ST/threadx/common/src/tx_byte_pool_initialize.c;Middlewares/ST/threadx/common/src/tx_byte_pool_prioritize.c;Middlewares/ST/threadx/common/src/tx_byte_pool_search.c;Middlewares/ST/threadx/common/src/tx_byte_release.c;Middlewares/ST/threadx/common/src/tx_event_flags_cleanup.c;Middlewares/ST/threadx/common/src/tx_event_flags_create.c;Middlewares/ST/threadx/common/src/tx_event_flags_delete.c;Middlewares/ST/threadx/common/src/tx_event_flags_get.c;Middlewares/ST/threadx/common/src/tx_event_flags_info_get.c;Middlewares/ST/threadx/common/src/tx_event_flags_initialize.c;Middlewares/ST/threadx/common/src/tx_event_flags_set.c;Middlewares/ST/threadx/common/src/tx_event_flags_set_notify.c;Middlewares/ST/threadx/common/src/tx_mutex_cleanup.c;Middlewares/ST/threadx/common/src/tx_mutex_create.c;Middlewares/ST/threadx/common/src/tx_mutex_delete.c;Middlewares/ST/threadx/common/src/tx_mutex_get.c;Middlewares/ST/threadx/common/src/tx_mutex_info_get.c;Middlewares/ST/threadx/common/src/tx_mutex_initialize.c;Middlewares/ST/threadx/common/src/tx_mutex_prioritize.c;Middlewares/ST/threadx/common/src/tx_mutex_priority_change.c;Middlewares/ST/threadx/common/src/tx_mutex_put.c;Middlewares/ST/threadx/common/src/tx_queue_cleanup.c;Middlewares/ST/threadx/common/src/tx_queue_create.c;Middlewares/ST/threadx/common/src/tx_queue_delete.c;Middlewares/ST/threadx/common/src/tx_queue_flush.c;Middlewares/ST/threadx/common/src/tx_queue_front_send.c;Middlewares/ST/threadx/common/src/tx_queue_info_get.c;Middlewares/ST/threadx/common/src/tx_queue_initialize.c;Middlewares/ST/threadx/common/src/tx_queue_prioritize.c;Middlewares/ST/threadx/common/src/tx_queue_receive.c;Middlewares/ST/threadx/common/src/tx_queue_send.c;Middlewares/ST/threadx/common/src/tx_queue_send_notify.c;Middlewares/ST/threadx/common/src/tx_semaphore_ceiling_put.c;Middlewares/ST/threadx/common/src/tx_semaphore_cleanup.c;Middlewares/ST/threadx/common/src/tx_semaphore_create.c;Middlewares/ST/threadx/common/src/tx_semaphore_delete.c;Middlewares/ST/threadx/common/src/tx_semaphore_get.c;Middlewares/ST/threadx/common/src/tx_semaphore_info_get.c;Middlewares/ST/threadx/common/src/tx_semaphore_initialize.c;Middlewares/ST/threadx/common/src/tx_semaphore_prioritize.c;Middlewares/ST/threadx/common/src/tx_semaphore_put.c;Middlewares/ST/threadx/common/src/tx_semaphore_put_notify.c;Middlewares/ST/threadx/common/src/tx_thread_create.c;Middlewares/ST/threadx/common/src/tx_thread_delete.c;Middlewares/ST/threadx/common/src/tx_thread_entry_exit_notify.c;Middlewares/ST/threadx/common/src/tx_thread_identify.c;Middlewares/ST/threadx/common/src/tx_thread_info_get.c;Middlewares/ST/threadx/common/src/tx_thread_initialize.c;Middlewares/ST/threadx/common/src/tx_thread_preemption_change.c;Middlewares/ST/threadx/common/src/tx_thread_priority_change.c;Middlewares/ST/threadx/common/src/tx_thread_relinquish.c;Middlewares/ST/threadx/common/src/tx_thread_reset.c;Middlewares/ST/threadx/common/src/tx_thread_resume.c;Middlewares/ST/threadx/common/src/tx_thread_shell_entry.c;Middlewares/ST/threadx/common/src/tx_thread_sleep.c;Middlewares/ST/threadx/common/src/tx_thread_stack_analyze.c;Middlewares/ST/threadx/common/src/tx_thread_suspend.c;Middlewares/ST/threadx/common/src/tx_thread_system_preempt_check.c;Middlewares/ST/threadx/common/src/tx_thread_system_suspend.c;Middlewares/ST/threadx/common/src/tx_thread_terminate.c;Middlewares/ST/threadx/common/src/tx_thread_time_slice.c;Middlewares/ST/threadx/common/src/tx_thread_time_slice_change.c;Middlewares/ST/threadx/common/src/tx_thread_timeout.c;Middlewares/ST/threadx/common/src/tx_thread_wait_abort.c;Middlewares/ST/threadx/common/src/tx_time_get.c;Middlewares/ST/threadx/common/src/tx_time_set.c;Middlewares/ST/threadx/common/src/txe_block_allocate.c;Middlewares/ST/threadx/common/src/txe_block_pool_create.c;Middlewares/ST/threadx/common/src/txe_block_pool_delete.c;Middlewares/ST/threadx/common/src/txe_block_pool_info_get.c;Middlewares/ST/threadx/common/src/txe_block_pool_prioritize.c;Middlewares/ST/threadx/common/src/txe_block_release.c;Middlewares/ST/threadx/common/src/txe_byte_allocate.c;Middlewares/ST/threadx/common/src/txe_byte_pool_create.c;Middlewares/ST/threadx/common/src/txe_byte_pool_delete.c;Middlewares/ST/threadx/common/src/txe_byte_pool_info_get.c;Middlewares/ST/threadx/common/src/txe_byte_pool_prioritize.c;Middlewares/ST/threadx/common/src/txe_byte_release.c;Middlewares/ST/threadx/common/src/txe_event_flags_create.c;Middlewares/ST/threadx/common/src/txe_event_flags_delete.c;Middlewares/ST/threadx/common/src/txe_event_flags_get.c;Middlewares/ST/threadx/common/src/txe_event_flags_info_get.c;Middlewares/ST/threadx/common/src/txe_event_flags_set.c;Middlewares/ST/threadx/common/src/txe_event_flags_set_notify.c;Middlewares/ST/threadx/common/src/txe_mutex_create.c;Middlewares/ST/threadx/common/src/txe_mutex_delete.c;Middlewares/ST/threadx/common/src/txe_mutex_get.c;Middlewares/ST/threadx/common/src/txe_mutex_info_get.c;Middlewares/ST/threadx/common/src/txe_mutex_prioritize.c;Middlewares/ST/threadx/common/src/txe_mutex_put.c;Middlewares/ST/threadx/common/src/txe_queue_create.c;Middlewares/ST/threadx/common/src/txe_queue_delete.c;Middlewares/ST/threadx/common/src/txe_queue_flush.c;Middlewares/ST/threadx/common/src/txe_queue_front_send.c;Middlewares/ST/threadx/common/src/txe_queue_info_get.c;Middlewares/ST/threadx/common/src/txe_queue_prioritize.c;Middlewares/ST/threadx/common/src/txe_queue_receive.c;Middlewares/ST/threadx/common/src/txe_queue_send.c;Middlewares/ST/threadx/common/src/txe_queue_send_notify.c;Middlewares/ST/threadx/common/src/txe_semaphore_ceiling_put.c;Middlewares/ST/threadx/common/src/txe_semaphore_create.c;Middlewares/ST/threadx/common/src/txe_semaphore_delete.c;Middlewares/ST/threadx/common/src/txe_semaphore_get.c;Middlewares/ST/threadx/common/src/txe_semaphore_info_get.c;Middlewares/ST/threadx/common/src/txe_semaphore_prioritize.c;Middlewares/ST/threadx/common/src/txe_semaphore_put.c;Middlewares/ST/threadx/common/src/txe_semaphore_put_notify.c;Middlewares/ST/threadx/common/src/txe_thread_create.c;Middlewares/ST/threadx/common/src/txe_thread_delete.c;Middlewares/ST/threadx/common/src/txe_thread_entry_exit_notify.c;Middlewares/ST/threadx/common/src/txe_thread_info_get.c;Middlewares/ST/threadx/common/src/txe_thread_preemption_change.c;Middlewares/ST/threadx/common/src/txe_thread_priority_change.c;Middlewares/ST/threadx/common/src/txe_thread_relinquish.c;Middlewares/ST/threadx/common/src/txe_thread_reset.c;Middlewares/ST/threadx/common/src/txe_thread_resume.c;Middlewares/ST/threadx/common/src/txe_thread_suspend.c;Middlewares/ST/threadx/common/src/txe_thread_terminate.c;Middlewares/ST/threadx/common/src/txe_thread_time_slice_change.c;Middlewares/ST/threadx/common/src/txe_thread_wait_abort.c;Middlewares/ST/threadx/common/src/tx_timer_activate.c;Middlewares/ST/threadx/common/src/tx_timer_change.c;Middlewares/ST/threadx/common/src/tx_timer_create.c;Middlewares/ST/threadx/common/src/tx_timer_deactivate.c;Middlewares/ST/threadx/common/src/tx_timer_delete.c;Middlewares/ST/threadx/common/src/tx_timer_expiration_process.c;Middlewares/ST/threadx/common/src/tx_timer_info_get.c;Middlewares/ST/threadx/common/src/tx_timer_initialize.c;Middlewares/ST/threadx/common/src/tx_timer_system_activate.c;Middlewares/ST/threadx/common/src/tx_timer_system_deactivate.c;Middlewares/ST/threadx/common/src/tx_timer_thread_entry.c;Middlewares/ST/threadx/common/src/txe_timer_activate.c;Middlewares/ST/threadx/common/src/txe_timer_change.c;Middlewares/ST/threadx/common/src/txe_timer_create.c;Middlewares/ST/threadx/common/src/txe_timer_deactivate.c;Middlewares/ST/threadx/common/src/txe_timer_delete.c;Middlewares/ST/threadx/common/src/txe_timer_info_get.c;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crs.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dmamux.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h;Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_utils.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_fmc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sram.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i2c.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_xspi.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dlyb.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sai.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sai_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_sdmmc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sd.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sd_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_tim.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_ucpd.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_usart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_lpuart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h;Middlewares/ST/threadx/common/inc/tx_api.h;Middlewares/ST/threadx/common/inc/tx_block_pool.h;Middlewares/ST/threadx/common/inc/tx_byte_pool.h;Middlewares/ST/threadx/common/inc/tx_event_flags.h;Middlewares/ST/threadx/common/inc/tx_initialize.h;Middlewares/ST/threadx/common/inc/tx_mutex.h;Middlewares/ST/threadx/common/inc/tx_queue.h;Middlewares/ST/threadx/common/inc/tx_semaphore.h;Middlewares/ST/threadx/common/inc/tx_thread.h;Middlewares/ST/threadx/common/inc/tx_timer.h;Middlewares/ST/threadx/common/inc/tx_trace.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.c; + +[PreviousUsedCubeIDEFiles] +SourceFiles=Core/Src/main.c;Core/Src/tx_initialize_low_level.S;Core/Src/gpio.c;Core/Src/adc.c;Core/Src/eth.c;FileX/App/app_filex.c;FileX/Target/fx_stm32_sd_driver_glue.c;Core/Src/fmc.c;Core/Src/gpdma.c;Core/Src/i2c.c;Core/Src/icache.c;Core/Src/linked_list.c;Core/Src/memorymap.c;Core/Src/octospi.c;Core/Src/sai.c;Core/Src/sdmmc.c;Core/Src/app_threadx.c;AZURE_RTOS/App/app_azure_rtos.c;Core/Src/tim.c;Core/Src/ucpd.c;Core/Src/usart.c;Core/Src/stm32h5xx_it.c;Core/Src/stm32h5xx_hal_msp.c;Core/Src/stm32h5xx_hal_timebase_tim.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_utils.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_xspi.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dlyb.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_sdmmc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_ucpd.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c;Middlewares/ST/filex/common/src/fx_directory_attributes_read.c;Middlewares/ST/filex/common/src/fx_directory_attributes_set.c;Middlewares/ST/filex/common/src/fx_directory_create.c;Middlewares/ST/filex/common/src/fx_directory_default_get.c;Middlewares/ST/filex/common/src/fx_directory_default_get_copy.c;Middlewares/ST/filex/common/src/fx_directory_default_set.c;Middlewares/ST/filex/common/src/fx_directory_delete.c;Middlewares/ST/filex/common/src/fx_directory_entry_read.c;Middlewares/ST/filex/common/src/fx_directory_entry_write.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_entry_read.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_entry_write.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_free_search.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_unicode_entry_write.c;Middlewares/ST/filex/common/src/fx_directory_first_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_first_full_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_free_search.c;Middlewares/ST/filex/common/src/fx_directory_information_get.c;Middlewares/ST/filex/common/src/fx_directory_local_path_clear.c;Middlewares/ST/filex/common/src/fx_directory_local_path_get.c;Middlewares/ST/filex/common/src/fx_directory_local_path_get_copy.c;Middlewares/ST/filex/common/src/fx_directory_local_path_restore.c;Middlewares/ST/filex/common/src/fx_directory_local_path_set.c;Middlewares/ST/filex/common/src/fx_directory_long_name_get.c;Middlewares/ST/filex/common/src/fx_directory_long_name_get_extended.c;Middlewares/ST/filex/common/src/fx_directory_name_extract.c;Middlewares/ST/filex/common/src/fx_directory_name_test.c;Middlewares/ST/filex/common/src/fx_directory_next_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_next_full_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_rename.c;Middlewares/ST/filex/common/src/fx_directory_search.c;Middlewares/ST/filex/common/src/fx_directory_short_name_get.c;Middlewares/ST/filex/common/src/fx_directory_short_name_get_extended.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_bitmap_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_checksum_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_dir_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_FAT_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_apply_logs.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_calculate_checksum.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_cleanup_FAT_chain.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_create_log_file.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_enable.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_read_directory_sector.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_read_FAT.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_read_log_file.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_recover.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_reset_log_file.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_set_FAT_chain.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_end.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_fail.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_start.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_write_log_file.c;Middlewares/ST/filex/common/src/fx_file_allocate.c;Middlewares/ST/filex/common/src/fx_file_attributes_read.c;Middlewares/ST/filex/common/src/fx_file_attributes_set.c;Middlewares/ST/filex/common/src/fx_file_best_effort_allocate.c;Middlewares/ST/filex/common/src/fx_file_close.c;Middlewares/ST/filex/common/src/fx_file_create.c;Middlewares/ST/filex/common/src/fx_file_date_time_set.c;Middlewares/ST/filex/common/src/fx_file_delete.c;Middlewares/ST/filex/common/src/fx_file_extended_allocate.c;Middlewares/ST/filex/common/src/fx_file_extended_best_effort_allocate.c;Middlewares/ST/filex/common/src/fx_file_extended_relative_seek.c;Middlewares/ST/filex/common/src/fx_file_extended_seek.c;Middlewares/ST/filex/common/src/fx_file_extended_truncate.c;Middlewares/ST/filex/common/src/fx_file_extended_truncate_release.c;Middlewares/ST/filex/common/src/fx_file_open.c;Middlewares/ST/filex/common/src/fx_file_read.c;Middlewares/ST/filex/common/src/fx_file_relative_seek.c;Middlewares/ST/filex/common/src/fx_file_rename.c;Middlewares/ST/filex/common/src/fx_file_seek.c;Middlewares/ST/filex/common/src/fx_file_truncate.c;Middlewares/ST/filex/common/src/fx_file_truncate_release.c;Middlewares/ST/filex/common/src/fx_file_write.c;Middlewares/ST/filex/common/src/fx_file_write_notify_set.c;Middlewares/ST/filex/common/src/fx_media_abort.c;Middlewares/ST/filex/common/src/fx_media_boot_info_extract.c;Middlewares/ST/filex/common/src/fx_media_cache_invalidate.c;Middlewares/ST/filex/common/src/fx_media_check.c;Middlewares/ST/filex/common/src/fx_media_check_FAT_chain_check.c;Middlewares/ST/filex/common/src/fx_media_check_lost_cluster_check.c;Middlewares/ST/filex/common/src/fx_media_close.c;Middlewares/ST/filex/common/src/fx_media_close_notify_set.c;Middlewares/ST/filex/common/src/fx_media_exFAT_format.c;Middlewares/ST/filex/common/src/fx_media_extended_space_available.c;Middlewares/ST/filex/common/src/fx_media_flush.c;Middlewares/ST/filex/common/src/fx_media_format.c;Middlewares/ST/filex/common/src/fx_media_format_oem_name_set.c;Middlewares/ST/filex/common/src/fx_media_format_type_set.c;Middlewares/ST/filex/common/src/fx_media_format_volume_id_set.c;Middlewares/ST/filex/common/src/fx_media_open.c;Middlewares/ST/filex/common/src/fx_media_open_notify_set.c;Middlewares/ST/filex/common/src/fx_media_read.c;Middlewares/ST/filex/common/src/fx_media_space_available.c;Middlewares/ST/filex/common/src/fx_media_volume_get.c;Middlewares/ST/filex/common/src/fx_media_volume_get_extended.c;Middlewares/ST/filex/common/src/fx_media_volume_set.c;Middlewares/ST/filex/common/src/fx_media_write.c;Middlewares/ST/filex/common/src/fx_partition_offset_calculate.c;Middlewares/ST/filex/common/src/fx_system_date_get.c;Middlewares/ST/filex/common/src/fx_system_date_set.c;Middlewares/ST/filex/common/src/fx_system_initialize.c;Middlewares/ST/filex/common/src/fx_system_time_get.c;Middlewares/ST/filex/common/src/fx_system_time_set.c;Middlewares/ST/filex/common/src/fx_system_timer_entry.c;Middlewares/ST/filex/common/src/fx_unicode_directory_create.c;Middlewares/ST/filex/common/src/fx_unicode_directory_entry_change.c;Middlewares/ST/filex/common/src/fx_unicode_directory_entry_read.c;Middlewares/ST/filex/common/src/fx_unicode_directory_rename.c;Middlewares/ST/filex/common/src/fx_unicode_directory_search.c;Middlewares/ST/filex/common/src/fx_unicode_file_create.c;Middlewares/ST/filex/common/src/fx_unicode_file_rename.c;Middlewares/ST/filex/common/src/fx_unicode_length_get.c;Middlewares/ST/filex/common/src/fx_unicode_length_get_extended.c;Middlewares/ST/filex/common/src/fx_unicode_name_get.c;Middlewares/ST/filex/common/src/fx_unicode_name_get_extended.c;Middlewares/ST/filex/common/src/fx_unicode_short_name_get.c;Middlewares/ST/filex/common/src/fx_unicode_short_name_get_extended.c;Middlewares/ST/filex/common/src/fx_utility_16_unsigned_read.c;Middlewares/ST/filex/common/src/fx_utility_16_unsigned_write.c;Middlewares/ST/filex/common/src/fx_utility_32_unsigned_read.c;Middlewares/ST/filex/common/src/fx_utility_32_unsigned_write.c;Middlewares/ST/filex/common/src/fx_utility_64_unsigned_read.c;Middlewares/ST/filex/common/src/fx_utility_64_unsigned_write.c;Middlewares/ST/filex/common/src/fx_utility_absolute_path_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_allocate_new_cluster.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_cache_prepare.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_cache_update.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_flush.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_free_cluster_find.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_initialize.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_start_sector_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_free.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_state_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_state_set.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_geometry_check.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_name_hash_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_size_calculate.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_checksum_verify.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_checksum_write.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_format.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_sector_write.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_unicode_name_hash_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_upcase_table.c;Middlewares/ST/filex/common/src/fx_utility_FAT_entry_read.c;Middlewares/ST/filex/common/src/fx_utility_FAT_entry_write.c;Middlewares/ST/filex/common/src/fx_utility_FAT_flush.c;Middlewares/ST/filex/common/src/fx_utility_FAT_map_flush.c;Middlewares/ST/filex/common/src/fx_utility_FAT_sector_get.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_cache_entry_read.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_flush.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_read.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_write.c;Middlewares/ST/filex/common/src/fx_utility_memory_copy.c;Middlewares/ST/filex/common/src/fx_utility_memory_set.c;Middlewares/ST/filex/common/src/fx_utility_string_length_get.c;Middlewares/ST/filex/common/src/fx_utility_token_length_get.c;Middlewares/ST/filex/common/src/fxe_directory_attributes_read.c;Middlewares/ST/filex/common/src/fxe_directory_attributes_set.c;Middlewares/ST/filex/common/src/fxe_directory_create.c;Middlewares/ST/filex/common/src/fxe_directory_default_get.c;Middlewares/ST/filex/common/src/fxe_directory_default_get_copy.c;Middlewares/ST/filex/common/src/fxe_directory_default_set.c;Middlewares/ST/filex/common/src/fxe_directory_delete.c;Middlewares/ST/filex/common/src/fxe_directory_first_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_first_full_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_information_get.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_clear.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_get.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_get_copy.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_restore.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_set.c;Middlewares/ST/filex/common/src/fxe_directory_long_name_get.c;Middlewares/ST/filex/common/src/fxe_directory_long_name_get_extended.c;Middlewares/ST/filex/common/src/fxe_directory_name_test.c;Middlewares/ST/filex/common/src/fxe_directory_next_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_next_full_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_rename.c;Middlewares/ST/filex/common/src/fxe_directory_short_name_get.c;Middlewares/ST/filex/common/src/fxe_directory_short_name_get_extended.c;Middlewares/ST/filex/common/src/fxe_fault_tolerant_enable.c;Middlewares/ST/filex/common/src/fxe_file_allocate.c;Middlewares/ST/filex/common/src/fxe_file_attributes_read.c;Middlewares/ST/filex/common/src/fxe_file_attributes_set.c;Middlewares/ST/filex/common/src/fxe_file_best_effort_allocate.c;Middlewares/ST/filex/common/src/fxe_file_close.c;Middlewares/ST/filex/common/src/fxe_file_create.c;Middlewares/ST/filex/common/src/fxe_file_date_time_set.c;Middlewares/ST/filex/common/src/fxe_file_delete.c;Middlewares/ST/filex/common/src/fxe_file_extended_allocate.c;Middlewares/ST/filex/common/src/fxe_file_extended_best_effort_allocate.c;Middlewares/ST/filex/common/src/fxe_file_extended_relative_seek.c;Middlewares/ST/filex/common/src/fxe_file_extended_seek.c;Middlewares/ST/filex/common/src/fxe_file_extended_truncate.c;Middlewares/ST/filex/common/src/fxe_file_extended_truncate_release.c;Middlewares/ST/filex/common/src/fxe_file_open.c;Middlewares/ST/filex/common/src/fxe_file_read.c;Middlewares/ST/filex/common/src/fxe_file_relative_seek.c;Middlewares/ST/filex/common/src/fxe_file_rename.c;Middlewares/ST/filex/common/src/fxe_file_seek.c;Middlewares/ST/filex/common/src/fxe_file_truncate.c;Middlewares/ST/filex/common/src/fxe_file_truncate_release.c;Middlewares/ST/filex/common/src/fxe_file_write.c;Middlewares/ST/filex/common/src/fxe_file_write_notify_set.c;Middlewares/ST/filex/common/src/fxe_media_abort.c;Middlewares/ST/filex/common/src/fxe_media_cache_invalidate.c;Middlewares/ST/filex/common/src/fxe_media_check.c;Middlewares/ST/filex/common/src/fxe_media_close.c;Middlewares/ST/filex/common/src/fxe_media_close_notify_set.c;Middlewares/ST/filex/common/src/fxe_media_exFAT_format.c;Middlewares/ST/filex/common/src/fxe_media_extended_space_available.c;Middlewares/ST/filex/common/src/fxe_media_flush.c;Middlewares/ST/filex/common/src/fxe_media_format.c;Middlewares/ST/filex/common/src/fxe_media_open.c;Middlewares/ST/filex/common/src/fxe_media_open_notify_set.c;Middlewares/ST/filex/common/src/fxe_media_read.c;Middlewares/ST/filex/common/src/fxe_media_space_available.c;Middlewares/ST/filex/common/src/fxe_media_volume_get.c;Middlewares/ST/filex/common/src/fxe_media_volume_get_extended.c;Middlewares/ST/filex/common/src/fxe_media_volume_set.c;Middlewares/ST/filex/common/src/fxe_media_write.c;Middlewares/ST/filex/common/src/fxe_system_date_get.c;Middlewares/ST/filex/common/src/fxe_system_date_set.c;Middlewares/ST/filex/common/src/fxe_system_time_get.c;Middlewares/ST/filex/common/src/fxe_system_time_set.c;Middlewares/ST/filex/common/src/fxe_unicode_directory_create.c;Middlewares/ST/filex/common/src/fxe_unicode_directory_rename.c;Middlewares/ST/filex/common/src/fxe_unicode_file_create.c;Middlewares/ST/filex/common/src/fxe_unicode_file_rename.c;Middlewares/ST/filex/common/src/fxe_unicode_name_get.c;Middlewares/ST/filex/common/src/fxe_unicode_name_get_extended.c;Middlewares/ST/filex/common/src/fxe_unicode_short_name_get.c;Middlewares/ST/filex/common/src/fxe_unicode_short_name_get_extended.c;Middlewares/ST/filex/common/drivers/fx_stm32_sd_driver.c;Middlewares/ST/threadx/common/src/tx_initialize_high_level.c;Middlewares/ST/threadx/common/src/tx_initialize_kernel_enter.c;Middlewares/ST/threadx/common/src/tx_initialize_kernel_setup.c;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_context_restore.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_context_save.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_interrupt_control.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_interrupt_disable.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_interrupt_restore.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_schedule.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_stack_build.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_system_return.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_timer_interrupt.S;Middlewares/ST/threadx/common/src/tx_thread_stack_error_handler.c;Middlewares/ST/threadx/common/src/tx_thread_stack_error_notify.c;Middlewares/ST/threadx/common/src/tx_thread_system_resume.c;Middlewares/ST/threadx/common/src/tx_block_allocate.c;Middlewares/ST/threadx/common/src/tx_block_pool_cleanup.c;Middlewares/ST/threadx/common/src/tx_block_pool_create.c;Middlewares/ST/threadx/common/src/tx_block_pool_delete.c;Middlewares/ST/threadx/common/src/tx_block_pool_info_get.c;Middlewares/ST/threadx/common/src/tx_block_pool_initialize.c;Middlewares/ST/threadx/common/src/tx_block_pool_prioritize.c;Middlewares/ST/threadx/common/src/tx_block_release.c;Middlewares/ST/threadx/common/src/tx_byte_allocate.c;Middlewares/ST/threadx/common/src/tx_byte_pool_cleanup.c;Middlewares/ST/threadx/common/src/tx_byte_pool_create.c;Middlewares/ST/threadx/common/src/tx_byte_pool_delete.c;Middlewares/ST/threadx/common/src/tx_byte_pool_info_get.c;Middlewares/ST/threadx/common/src/tx_byte_pool_initialize.c;Middlewares/ST/threadx/common/src/tx_byte_pool_prioritize.c;Middlewares/ST/threadx/common/src/tx_byte_pool_search.c;Middlewares/ST/threadx/common/src/tx_byte_release.c;Middlewares/ST/threadx/common/src/tx_event_flags_cleanup.c;Middlewares/ST/threadx/common/src/tx_event_flags_create.c;Middlewares/ST/threadx/common/src/tx_event_flags_delete.c;Middlewares/ST/threadx/common/src/tx_event_flags_get.c;Middlewares/ST/threadx/common/src/tx_event_flags_info_get.c;Middlewares/ST/threadx/common/src/tx_event_flags_initialize.c;Middlewares/ST/threadx/common/src/tx_event_flags_set.c;Middlewares/ST/threadx/common/src/tx_event_flags_set_notify.c;Middlewares/ST/threadx/common/src/tx_mutex_cleanup.c;Middlewares/ST/threadx/common/src/tx_mutex_create.c;Middlewares/ST/threadx/common/src/tx_mutex_delete.c;Middlewares/ST/threadx/common/src/tx_mutex_get.c;Middlewares/ST/threadx/common/src/tx_mutex_info_get.c;Middlewares/ST/threadx/common/src/tx_mutex_initialize.c;Middlewares/ST/threadx/common/src/tx_mutex_prioritize.c;Middlewares/ST/threadx/common/src/tx_mutex_priority_change.c;Middlewares/ST/threadx/common/src/tx_mutex_put.c;Middlewares/ST/threadx/common/src/tx_queue_cleanup.c;Middlewares/ST/threadx/common/src/tx_queue_create.c;Middlewares/ST/threadx/common/src/tx_queue_delete.c;Middlewares/ST/threadx/common/src/tx_queue_flush.c;Middlewares/ST/threadx/common/src/tx_queue_front_send.c;Middlewares/ST/threadx/common/src/tx_queue_info_get.c;Middlewares/ST/threadx/common/src/tx_queue_initialize.c;Middlewares/ST/threadx/common/src/tx_queue_prioritize.c;Middlewares/ST/threadx/common/src/tx_queue_receive.c;Middlewares/ST/threadx/common/src/tx_queue_send.c;Middlewares/ST/threadx/common/src/tx_queue_send_notify.c;Middlewares/ST/threadx/common/src/tx_semaphore_ceiling_put.c;Middlewares/ST/threadx/common/src/tx_semaphore_cleanup.c;Middlewares/ST/threadx/common/src/tx_semaphore_create.c;Middlewares/ST/threadx/common/src/tx_semaphore_delete.c;Middlewares/ST/threadx/common/src/tx_semaphore_get.c;Middlewares/ST/threadx/common/src/tx_semaphore_info_get.c;Middlewares/ST/threadx/common/src/tx_semaphore_initialize.c;Middlewares/ST/threadx/common/src/tx_semaphore_prioritize.c;Middlewares/ST/threadx/common/src/tx_semaphore_put.c;Middlewares/ST/threadx/common/src/tx_semaphore_put_notify.c;Middlewares/ST/threadx/common/src/tx_thread_create.c;Middlewares/ST/threadx/common/src/tx_thread_delete.c;Middlewares/ST/threadx/common/src/tx_thread_entry_exit_notify.c;Middlewares/ST/threadx/common/src/tx_thread_identify.c;Middlewares/ST/threadx/common/src/tx_thread_info_get.c;Middlewares/ST/threadx/common/src/tx_thread_initialize.c;Middlewares/ST/threadx/common/src/tx_thread_preemption_change.c;Middlewares/ST/threadx/common/src/tx_thread_priority_change.c;Middlewares/ST/threadx/common/src/tx_thread_relinquish.c;Middlewares/ST/threadx/common/src/tx_thread_reset.c;Middlewares/ST/threadx/common/src/tx_thread_resume.c;Middlewares/ST/threadx/common/src/tx_thread_shell_entry.c;Middlewares/ST/threadx/common/src/tx_thread_sleep.c;Middlewares/ST/threadx/common/src/tx_thread_stack_analyze.c;Middlewares/ST/threadx/common/src/tx_thread_suspend.c;Middlewares/ST/threadx/common/src/tx_thread_system_preempt_check.c;Middlewares/ST/threadx/common/src/tx_thread_system_suspend.c;Middlewares/ST/threadx/common/src/tx_thread_terminate.c;Middlewares/ST/threadx/common/src/tx_thread_time_slice.c;Middlewares/ST/threadx/common/src/tx_thread_time_slice_change.c;Middlewares/ST/threadx/common/src/tx_thread_timeout.c;Middlewares/ST/threadx/common/src/tx_thread_wait_abort.c;Middlewares/ST/threadx/common/src/tx_time_get.c;Middlewares/ST/threadx/common/src/tx_time_set.c;Middlewares/ST/threadx/common/src/txe_block_allocate.c;Middlewares/ST/threadx/common/src/txe_block_pool_create.c;Middlewares/ST/threadx/common/src/txe_block_pool_delete.c;Middlewares/ST/threadx/common/src/txe_block_pool_info_get.c;Middlewares/ST/threadx/common/src/txe_block_pool_prioritize.c;Middlewares/ST/threadx/common/src/txe_block_release.c;Middlewares/ST/threadx/common/src/txe_byte_allocate.c;Middlewares/ST/threadx/common/src/txe_byte_pool_create.c;Middlewares/ST/threadx/common/src/txe_byte_pool_delete.c;Middlewares/ST/threadx/common/src/txe_byte_pool_info_get.c;Middlewares/ST/threadx/common/src/txe_byte_pool_prioritize.c;Middlewares/ST/threadx/common/src/txe_byte_release.c;Middlewares/ST/threadx/common/src/txe_event_flags_create.c;Middlewares/ST/threadx/common/src/txe_event_flags_delete.c;Middlewares/ST/threadx/common/src/txe_event_flags_get.c;Middlewares/ST/threadx/common/src/txe_event_flags_info_get.c;Middlewares/ST/threadx/common/src/txe_event_flags_set.c;Middlewares/ST/threadx/common/src/txe_event_flags_set_notify.c;Middlewares/ST/threadx/common/src/txe_mutex_create.c;Middlewares/ST/threadx/common/src/txe_mutex_delete.c;Middlewares/ST/threadx/common/src/txe_mutex_get.c;Middlewares/ST/threadx/common/src/txe_mutex_info_get.c;Middlewares/ST/threadx/common/src/txe_mutex_prioritize.c;Middlewares/ST/threadx/common/src/txe_mutex_put.c;Middlewares/ST/threadx/common/src/txe_queue_create.c;Middlewares/ST/threadx/common/src/txe_queue_delete.c;Middlewares/ST/threadx/common/src/txe_queue_flush.c;Middlewares/ST/threadx/common/src/txe_queue_front_send.c;Middlewares/ST/threadx/common/src/txe_queue_info_get.c;Middlewares/ST/threadx/common/src/txe_queue_prioritize.c;Middlewares/ST/threadx/common/src/txe_queue_receive.c;Middlewares/ST/threadx/common/src/txe_queue_send.c;Middlewares/ST/threadx/common/src/txe_queue_send_notify.c;Middlewares/ST/threadx/common/src/txe_semaphore_ceiling_put.c;Middlewares/ST/threadx/common/src/txe_semaphore_create.c;Middlewares/ST/threadx/common/src/txe_semaphore_delete.c;Middlewares/ST/threadx/common/src/txe_semaphore_get.c;Middlewares/ST/threadx/common/src/txe_semaphore_info_get.c;Middlewares/ST/threadx/common/src/txe_semaphore_prioritize.c;Middlewares/ST/threadx/common/src/txe_semaphore_put.c;Middlewares/ST/threadx/common/src/txe_semaphore_put_notify.c;Middlewares/ST/threadx/common/src/txe_thread_create.c;Middlewares/ST/threadx/common/src/txe_thread_delete.c;Middlewares/ST/threadx/common/src/txe_thread_entry_exit_notify.c;Middlewares/ST/threadx/common/src/txe_thread_info_get.c;Middlewares/ST/threadx/common/src/txe_thread_preemption_change.c;Middlewares/ST/threadx/common/src/txe_thread_priority_change.c;Middlewares/ST/threadx/common/src/txe_thread_relinquish.c;Middlewares/ST/threadx/common/src/txe_thread_reset.c;Middlewares/ST/threadx/common/src/txe_thread_resume.c;Middlewares/ST/threadx/common/src/txe_thread_suspend.c;Middlewares/ST/threadx/common/src/txe_thread_terminate.c;Middlewares/ST/threadx/common/src/txe_thread_time_slice_change.c;Middlewares/ST/threadx/common/src/txe_thread_wait_abort.c;Middlewares/ST/threadx/common/src/tx_timer_activate.c;Middlewares/ST/threadx/common/src/tx_timer_change.c;Middlewares/ST/threadx/common/src/tx_timer_create.c;Middlewares/ST/threadx/common/src/tx_timer_deactivate.c;Middlewares/ST/threadx/common/src/tx_timer_delete.c;Middlewares/ST/threadx/common/src/tx_timer_expiration_process.c;Middlewares/ST/threadx/common/src/tx_timer_info_get.c;Middlewares/ST/threadx/common/src/tx_timer_initialize.c;Middlewares/ST/threadx/common/src/tx_timer_system_activate.c;Middlewares/ST/threadx/common/src/tx_timer_system_deactivate.c;Middlewares/ST/threadx/common/src/tx_timer_thread_entry.c;Middlewares/ST/threadx/common/src/txe_timer_activate.c;Middlewares/ST/threadx/common/src/txe_timer_change.c;Middlewares/ST/threadx/common/src/txe_timer_create.c;Middlewares/ST/threadx/common/src/txe_timer_deactivate.c;Middlewares/ST/threadx/common/src/txe_timer_delete.c;Middlewares/ST/threadx/common/src/txe_timer_info_get.c;Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.c;Core/Src/system_stm32h5xx.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_utils.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_xspi.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dlyb.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_sdmmc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_ucpd.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c;Middlewares/ST/filex/common/src/fx_directory_attributes_read.c;Middlewares/ST/filex/common/src/fx_directory_attributes_set.c;Middlewares/ST/filex/common/src/fx_directory_create.c;Middlewares/ST/filex/common/src/fx_directory_default_get.c;Middlewares/ST/filex/common/src/fx_directory_default_get_copy.c;Middlewares/ST/filex/common/src/fx_directory_default_set.c;Middlewares/ST/filex/common/src/fx_directory_delete.c;Middlewares/ST/filex/common/src/fx_directory_entry_read.c;Middlewares/ST/filex/common/src/fx_directory_entry_write.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_entry_read.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_entry_write.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_free_search.c;Middlewares/ST/filex/common/src/fx_directory_exFAT_unicode_entry_write.c;Middlewares/ST/filex/common/src/fx_directory_first_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_first_full_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_free_search.c;Middlewares/ST/filex/common/src/fx_directory_information_get.c;Middlewares/ST/filex/common/src/fx_directory_local_path_clear.c;Middlewares/ST/filex/common/src/fx_directory_local_path_get.c;Middlewares/ST/filex/common/src/fx_directory_local_path_get_copy.c;Middlewares/ST/filex/common/src/fx_directory_local_path_restore.c;Middlewares/ST/filex/common/src/fx_directory_local_path_set.c;Middlewares/ST/filex/common/src/fx_directory_long_name_get.c;Middlewares/ST/filex/common/src/fx_directory_long_name_get_extended.c;Middlewares/ST/filex/common/src/fx_directory_name_extract.c;Middlewares/ST/filex/common/src/fx_directory_name_test.c;Middlewares/ST/filex/common/src/fx_directory_next_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_next_full_entry_find.c;Middlewares/ST/filex/common/src/fx_directory_rename.c;Middlewares/ST/filex/common/src/fx_directory_search.c;Middlewares/ST/filex/common/src/fx_directory_short_name_get.c;Middlewares/ST/filex/common/src/fx_directory_short_name_get_extended.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_bitmap_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_checksum_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_dir_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_add_FAT_log.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_apply_logs.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_calculate_checksum.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_cleanup_FAT_chain.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_create_log_file.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_enable.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_read_directory_sector.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_read_FAT.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_read_log_file.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_recover.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_reset_log_file.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_set_FAT_chain.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_end.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_fail.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_start.c;Middlewares/ST/filex/common/src/fx_fault_tolerant_write_log_file.c;Middlewares/ST/filex/common/src/fx_file_allocate.c;Middlewares/ST/filex/common/src/fx_file_attributes_read.c;Middlewares/ST/filex/common/src/fx_file_attributes_set.c;Middlewares/ST/filex/common/src/fx_file_best_effort_allocate.c;Middlewares/ST/filex/common/src/fx_file_close.c;Middlewares/ST/filex/common/src/fx_file_create.c;Middlewares/ST/filex/common/src/fx_file_date_time_set.c;Middlewares/ST/filex/common/src/fx_file_delete.c;Middlewares/ST/filex/common/src/fx_file_extended_allocate.c;Middlewares/ST/filex/common/src/fx_file_extended_best_effort_allocate.c;Middlewares/ST/filex/common/src/fx_file_extended_relative_seek.c;Middlewares/ST/filex/common/src/fx_file_extended_seek.c;Middlewares/ST/filex/common/src/fx_file_extended_truncate.c;Middlewares/ST/filex/common/src/fx_file_extended_truncate_release.c;Middlewares/ST/filex/common/src/fx_file_open.c;Middlewares/ST/filex/common/src/fx_file_read.c;Middlewares/ST/filex/common/src/fx_file_relative_seek.c;Middlewares/ST/filex/common/src/fx_file_rename.c;Middlewares/ST/filex/common/src/fx_file_seek.c;Middlewares/ST/filex/common/src/fx_file_truncate.c;Middlewares/ST/filex/common/src/fx_file_truncate_release.c;Middlewares/ST/filex/common/src/fx_file_write.c;Middlewares/ST/filex/common/src/fx_file_write_notify_set.c;Middlewares/ST/filex/common/src/fx_media_abort.c;Middlewares/ST/filex/common/src/fx_media_boot_info_extract.c;Middlewares/ST/filex/common/src/fx_media_cache_invalidate.c;Middlewares/ST/filex/common/src/fx_media_check.c;Middlewares/ST/filex/common/src/fx_media_check_FAT_chain_check.c;Middlewares/ST/filex/common/src/fx_media_check_lost_cluster_check.c;Middlewares/ST/filex/common/src/fx_media_close.c;Middlewares/ST/filex/common/src/fx_media_close_notify_set.c;Middlewares/ST/filex/common/src/fx_media_exFAT_format.c;Middlewares/ST/filex/common/src/fx_media_extended_space_available.c;Middlewares/ST/filex/common/src/fx_media_flush.c;Middlewares/ST/filex/common/src/fx_media_format.c;Middlewares/ST/filex/common/src/fx_media_format_oem_name_set.c;Middlewares/ST/filex/common/src/fx_media_format_type_set.c;Middlewares/ST/filex/common/src/fx_media_format_volume_id_set.c;Middlewares/ST/filex/common/src/fx_media_open.c;Middlewares/ST/filex/common/src/fx_media_open_notify_set.c;Middlewares/ST/filex/common/src/fx_media_read.c;Middlewares/ST/filex/common/src/fx_media_space_available.c;Middlewares/ST/filex/common/src/fx_media_volume_get.c;Middlewares/ST/filex/common/src/fx_media_volume_get_extended.c;Middlewares/ST/filex/common/src/fx_media_volume_set.c;Middlewares/ST/filex/common/src/fx_media_write.c;Middlewares/ST/filex/common/src/fx_partition_offset_calculate.c;Middlewares/ST/filex/common/src/fx_system_date_get.c;Middlewares/ST/filex/common/src/fx_system_date_set.c;Middlewares/ST/filex/common/src/fx_system_initialize.c;Middlewares/ST/filex/common/src/fx_system_time_get.c;Middlewares/ST/filex/common/src/fx_system_time_set.c;Middlewares/ST/filex/common/src/fx_system_timer_entry.c;Middlewares/ST/filex/common/src/fx_unicode_directory_create.c;Middlewares/ST/filex/common/src/fx_unicode_directory_entry_change.c;Middlewares/ST/filex/common/src/fx_unicode_directory_entry_read.c;Middlewares/ST/filex/common/src/fx_unicode_directory_rename.c;Middlewares/ST/filex/common/src/fx_unicode_directory_search.c;Middlewares/ST/filex/common/src/fx_unicode_file_create.c;Middlewares/ST/filex/common/src/fx_unicode_file_rename.c;Middlewares/ST/filex/common/src/fx_unicode_length_get.c;Middlewares/ST/filex/common/src/fx_unicode_length_get_extended.c;Middlewares/ST/filex/common/src/fx_unicode_name_get.c;Middlewares/ST/filex/common/src/fx_unicode_name_get_extended.c;Middlewares/ST/filex/common/src/fx_unicode_short_name_get.c;Middlewares/ST/filex/common/src/fx_unicode_short_name_get_extended.c;Middlewares/ST/filex/common/src/fx_utility_16_unsigned_read.c;Middlewares/ST/filex/common/src/fx_utility_16_unsigned_write.c;Middlewares/ST/filex/common/src/fx_utility_32_unsigned_read.c;Middlewares/ST/filex/common/src/fx_utility_32_unsigned_write.c;Middlewares/ST/filex/common/src/fx_utility_64_unsigned_read.c;Middlewares/ST/filex/common/src/fx_utility_64_unsigned_write.c;Middlewares/ST/filex/common/src/fx_utility_absolute_path_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_allocate_new_cluster.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_cache_prepare.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_cache_update.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_flush.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_free_cluster_find.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_initialize.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_start_sector_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_free.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_state_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_state_set.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_geometry_check.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_name_hash_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_size_calculate.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_checksum_verify.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_checksum_write.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_format.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_system_sector_write.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_unicode_name_hash_get.c;Middlewares/ST/filex/common/src/fx_utility_exFAT_upcase_table.c;Middlewares/ST/filex/common/src/fx_utility_FAT_entry_read.c;Middlewares/ST/filex/common/src/fx_utility_FAT_entry_write.c;Middlewares/ST/filex/common/src/fx_utility_FAT_flush.c;Middlewares/ST/filex/common/src/fx_utility_FAT_map_flush.c;Middlewares/ST/filex/common/src/fx_utility_FAT_sector_get.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_cache_entry_read.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_flush.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_read.c;Middlewares/ST/filex/common/src/fx_utility_logical_sector_write.c;Middlewares/ST/filex/common/src/fx_utility_memory_copy.c;Middlewares/ST/filex/common/src/fx_utility_memory_set.c;Middlewares/ST/filex/common/src/fx_utility_string_length_get.c;Middlewares/ST/filex/common/src/fx_utility_token_length_get.c;Middlewares/ST/filex/common/src/fxe_directory_attributes_read.c;Middlewares/ST/filex/common/src/fxe_directory_attributes_set.c;Middlewares/ST/filex/common/src/fxe_directory_create.c;Middlewares/ST/filex/common/src/fxe_directory_default_get.c;Middlewares/ST/filex/common/src/fxe_directory_default_get_copy.c;Middlewares/ST/filex/common/src/fxe_directory_default_set.c;Middlewares/ST/filex/common/src/fxe_directory_delete.c;Middlewares/ST/filex/common/src/fxe_directory_first_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_first_full_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_information_get.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_clear.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_get.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_get_copy.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_restore.c;Middlewares/ST/filex/common/src/fxe_directory_local_path_set.c;Middlewares/ST/filex/common/src/fxe_directory_long_name_get.c;Middlewares/ST/filex/common/src/fxe_directory_long_name_get_extended.c;Middlewares/ST/filex/common/src/fxe_directory_name_test.c;Middlewares/ST/filex/common/src/fxe_directory_next_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_next_full_entry_find.c;Middlewares/ST/filex/common/src/fxe_directory_rename.c;Middlewares/ST/filex/common/src/fxe_directory_short_name_get.c;Middlewares/ST/filex/common/src/fxe_directory_short_name_get_extended.c;Middlewares/ST/filex/common/src/fxe_fault_tolerant_enable.c;Middlewares/ST/filex/common/src/fxe_file_allocate.c;Middlewares/ST/filex/common/src/fxe_file_attributes_read.c;Middlewares/ST/filex/common/src/fxe_file_attributes_set.c;Middlewares/ST/filex/common/src/fxe_file_best_effort_allocate.c;Middlewares/ST/filex/common/src/fxe_file_close.c;Middlewares/ST/filex/common/src/fxe_file_create.c;Middlewares/ST/filex/common/src/fxe_file_date_time_set.c;Middlewares/ST/filex/common/src/fxe_file_delete.c;Middlewares/ST/filex/common/src/fxe_file_extended_allocate.c;Middlewares/ST/filex/common/src/fxe_file_extended_best_effort_allocate.c;Middlewares/ST/filex/common/src/fxe_file_extended_relative_seek.c;Middlewares/ST/filex/common/src/fxe_file_extended_seek.c;Middlewares/ST/filex/common/src/fxe_file_extended_truncate.c;Middlewares/ST/filex/common/src/fxe_file_extended_truncate_release.c;Middlewares/ST/filex/common/src/fxe_file_open.c;Middlewares/ST/filex/common/src/fxe_file_read.c;Middlewares/ST/filex/common/src/fxe_file_relative_seek.c;Middlewares/ST/filex/common/src/fxe_file_rename.c;Middlewares/ST/filex/common/src/fxe_file_seek.c;Middlewares/ST/filex/common/src/fxe_file_truncate.c;Middlewares/ST/filex/common/src/fxe_file_truncate_release.c;Middlewares/ST/filex/common/src/fxe_file_write.c;Middlewares/ST/filex/common/src/fxe_file_write_notify_set.c;Middlewares/ST/filex/common/src/fxe_media_abort.c;Middlewares/ST/filex/common/src/fxe_media_cache_invalidate.c;Middlewares/ST/filex/common/src/fxe_media_check.c;Middlewares/ST/filex/common/src/fxe_media_close.c;Middlewares/ST/filex/common/src/fxe_media_close_notify_set.c;Middlewares/ST/filex/common/src/fxe_media_exFAT_format.c;Middlewares/ST/filex/common/src/fxe_media_extended_space_available.c;Middlewares/ST/filex/common/src/fxe_media_flush.c;Middlewares/ST/filex/common/src/fxe_media_format.c;Middlewares/ST/filex/common/src/fxe_media_open.c;Middlewares/ST/filex/common/src/fxe_media_open_notify_set.c;Middlewares/ST/filex/common/src/fxe_media_read.c;Middlewares/ST/filex/common/src/fxe_media_space_available.c;Middlewares/ST/filex/common/src/fxe_media_volume_get.c;Middlewares/ST/filex/common/src/fxe_media_volume_get_extended.c;Middlewares/ST/filex/common/src/fxe_media_volume_set.c;Middlewares/ST/filex/common/src/fxe_media_write.c;Middlewares/ST/filex/common/src/fxe_system_date_get.c;Middlewares/ST/filex/common/src/fxe_system_date_set.c;Middlewares/ST/filex/common/src/fxe_system_time_get.c;Middlewares/ST/filex/common/src/fxe_system_time_set.c;Middlewares/ST/filex/common/src/fxe_unicode_directory_create.c;Middlewares/ST/filex/common/src/fxe_unicode_directory_rename.c;Middlewares/ST/filex/common/src/fxe_unicode_file_create.c;Middlewares/ST/filex/common/src/fxe_unicode_file_rename.c;Middlewares/ST/filex/common/src/fxe_unicode_name_get.c;Middlewares/ST/filex/common/src/fxe_unicode_name_get_extended.c;Middlewares/ST/filex/common/src/fxe_unicode_short_name_get.c;Middlewares/ST/filex/common/src/fxe_unicode_short_name_get_extended.c;Middlewares/ST/filex/common/drivers/fx_stm32_sd_driver.c;Middlewares/ST/threadx/common/src/tx_initialize_high_level.c;Middlewares/ST/threadx/common/src/tx_initialize_kernel_enter.c;Middlewares/ST/threadx/common/src/tx_initialize_kernel_setup.c;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_context_restore.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_context_save.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_interrupt_control.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_interrupt_disable.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_interrupt_restore.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_schedule.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_stack_build.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_system_return.S;Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_timer_interrupt.S;Middlewares/ST/threadx/common/src/tx_thread_stack_error_handler.c;Middlewares/ST/threadx/common/src/tx_thread_stack_error_notify.c;Middlewares/ST/threadx/common/src/tx_thread_system_resume.c;Middlewares/ST/threadx/common/src/tx_block_allocate.c;Middlewares/ST/threadx/common/src/tx_block_pool_cleanup.c;Middlewares/ST/threadx/common/src/tx_block_pool_create.c;Middlewares/ST/threadx/common/src/tx_block_pool_delete.c;Middlewares/ST/threadx/common/src/tx_block_pool_info_get.c;Middlewares/ST/threadx/common/src/tx_block_pool_initialize.c;Middlewares/ST/threadx/common/src/tx_block_pool_prioritize.c;Middlewares/ST/threadx/common/src/tx_block_release.c;Middlewares/ST/threadx/common/src/tx_byte_allocate.c;Middlewares/ST/threadx/common/src/tx_byte_pool_cleanup.c;Middlewares/ST/threadx/common/src/tx_byte_pool_create.c;Middlewares/ST/threadx/common/src/tx_byte_pool_delete.c;Middlewares/ST/threadx/common/src/tx_byte_pool_info_get.c;Middlewares/ST/threadx/common/src/tx_byte_pool_initialize.c;Middlewares/ST/threadx/common/src/tx_byte_pool_prioritize.c;Middlewares/ST/threadx/common/src/tx_byte_pool_search.c;Middlewares/ST/threadx/common/src/tx_byte_release.c;Middlewares/ST/threadx/common/src/tx_event_flags_cleanup.c;Middlewares/ST/threadx/common/src/tx_event_flags_create.c;Middlewares/ST/threadx/common/src/tx_event_flags_delete.c;Middlewares/ST/threadx/common/src/tx_event_flags_get.c;Middlewares/ST/threadx/common/src/tx_event_flags_info_get.c;Middlewares/ST/threadx/common/src/tx_event_flags_initialize.c;Middlewares/ST/threadx/common/src/tx_event_flags_set.c;Middlewares/ST/threadx/common/src/tx_event_flags_set_notify.c;Middlewares/ST/threadx/common/src/tx_mutex_cleanup.c;Middlewares/ST/threadx/common/src/tx_mutex_create.c;Middlewares/ST/threadx/common/src/tx_mutex_delete.c;Middlewares/ST/threadx/common/src/tx_mutex_get.c;Middlewares/ST/threadx/common/src/tx_mutex_info_get.c;Middlewares/ST/threadx/common/src/tx_mutex_initialize.c;Middlewares/ST/threadx/common/src/tx_mutex_prioritize.c;Middlewares/ST/threadx/common/src/tx_mutex_priority_change.c;Middlewares/ST/threadx/common/src/tx_mutex_put.c;Middlewares/ST/threadx/common/src/tx_queue_cleanup.c;Middlewares/ST/threadx/common/src/tx_queue_create.c;Middlewares/ST/threadx/common/src/tx_queue_delete.c;Middlewares/ST/threadx/common/src/tx_queue_flush.c;Middlewares/ST/threadx/common/src/tx_queue_front_send.c;Middlewares/ST/threadx/common/src/tx_queue_info_get.c;Middlewares/ST/threadx/common/src/tx_queue_initialize.c;Middlewares/ST/threadx/common/src/tx_queue_prioritize.c;Middlewares/ST/threadx/common/src/tx_queue_receive.c;Middlewares/ST/threadx/common/src/tx_queue_send.c;Middlewares/ST/threadx/common/src/tx_queue_send_notify.c;Middlewares/ST/threadx/common/src/tx_semaphore_ceiling_put.c;Middlewares/ST/threadx/common/src/tx_semaphore_cleanup.c;Middlewares/ST/threadx/common/src/tx_semaphore_create.c;Middlewares/ST/threadx/common/src/tx_semaphore_delete.c;Middlewares/ST/threadx/common/src/tx_semaphore_get.c;Middlewares/ST/threadx/common/src/tx_semaphore_info_get.c;Middlewares/ST/threadx/common/src/tx_semaphore_initialize.c;Middlewares/ST/threadx/common/src/tx_semaphore_prioritize.c;Middlewares/ST/threadx/common/src/tx_semaphore_put.c;Middlewares/ST/threadx/common/src/tx_semaphore_put_notify.c;Middlewares/ST/threadx/common/src/tx_thread_create.c;Middlewares/ST/threadx/common/src/tx_thread_delete.c;Middlewares/ST/threadx/common/src/tx_thread_entry_exit_notify.c;Middlewares/ST/threadx/common/src/tx_thread_identify.c;Middlewares/ST/threadx/common/src/tx_thread_info_get.c;Middlewares/ST/threadx/common/src/tx_thread_initialize.c;Middlewares/ST/threadx/common/src/tx_thread_preemption_change.c;Middlewares/ST/threadx/common/src/tx_thread_priority_change.c;Middlewares/ST/threadx/common/src/tx_thread_relinquish.c;Middlewares/ST/threadx/common/src/tx_thread_reset.c;Middlewares/ST/threadx/common/src/tx_thread_resume.c;Middlewares/ST/threadx/common/src/tx_thread_shell_entry.c;Middlewares/ST/threadx/common/src/tx_thread_sleep.c;Middlewares/ST/threadx/common/src/tx_thread_stack_analyze.c;Middlewares/ST/threadx/common/src/tx_thread_suspend.c;Middlewares/ST/threadx/common/src/tx_thread_system_preempt_check.c;Middlewares/ST/threadx/common/src/tx_thread_system_suspend.c;Middlewares/ST/threadx/common/src/tx_thread_terminate.c;Middlewares/ST/threadx/common/src/tx_thread_time_slice.c;Middlewares/ST/threadx/common/src/tx_thread_time_slice_change.c;Middlewares/ST/threadx/common/src/tx_thread_timeout.c;Middlewares/ST/threadx/common/src/tx_thread_wait_abort.c;Middlewares/ST/threadx/common/src/tx_time_get.c;Middlewares/ST/threadx/common/src/tx_time_set.c;Middlewares/ST/threadx/common/src/txe_block_allocate.c;Middlewares/ST/threadx/common/src/txe_block_pool_create.c;Middlewares/ST/threadx/common/src/txe_block_pool_delete.c;Middlewares/ST/threadx/common/src/txe_block_pool_info_get.c;Middlewares/ST/threadx/common/src/txe_block_pool_prioritize.c;Middlewares/ST/threadx/common/src/txe_block_release.c;Middlewares/ST/threadx/common/src/txe_byte_allocate.c;Middlewares/ST/threadx/common/src/txe_byte_pool_create.c;Middlewares/ST/threadx/common/src/txe_byte_pool_delete.c;Middlewares/ST/threadx/common/src/txe_byte_pool_info_get.c;Middlewares/ST/threadx/common/src/txe_byte_pool_prioritize.c;Middlewares/ST/threadx/common/src/txe_byte_release.c;Middlewares/ST/threadx/common/src/txe_event_flags_create.c;Middlewares/ST/threadx/common/src/txe_event_flags_delete.c;Middlewares/ST/threadx/common/src/txe_event_flags_get.c;Middlewares/ST/threadx/common/src/txe_event_flags_info_get.c;Middlewares/ST/threadx/common/src/txe_event_flags_set.c;Middlewares/ST/threadx/common/src/txe_event_flags_set_notify.c;Middlewares/ST/threadx/common/src/txe_mutex_create.c;Middlewares/ST/threadx/common/src/txe_mutex_delete.c;Middlewares/ST/threadx/common/src/txe_mutex_get.c;Middlewares/ST/threadx/common/src/txe_mutex_info_get.c;Middlewares/ST/threadx/common/src/txe_mutex_prioritize.c;Middlewares/ST/threadx/common/src/txe_mutex_put.c;Middlewares/ST/threadx/common/src/txe_queue_create.c;Middlewares/ST/threadx/common/src/txe_queue_delete.c;Middlewares/ST/threadx/common/src/txe_queue_flush.c;Middlewares/ST/threadx/common/src/txe_queue_front_send.c;Middlewares/ST/threadx/common/src/txe_queue_info_get.c;Middlewares/ST/threadx/common/src/txe_queue_prioritize.c;Middlewares/ST/threadx/common/src/txe_queue_receive.c;Middlewares/ST/threadx/common/src/txe_queue_send.c;Middlewares/ST/threadx/common/src/txe_queue_send_notify.c;Middlewares/ST/threadx/common/src/txe_semaphore_ceiling_put.c;Middlewares/ST/threadx/common/src/txe_semaphore_create.c;Middlewares/ST/threadx/common/src/txe_semaphore_delete.c;Middlewares/ST/threadx/common/src/txe_semaphore_get.c;Middlewares/ST/threadx/common/src/txe_semaphore_info_get.c;Middlewares/ST/threadx/common/src/txe_semaphore_prioritize.c;Middlewares/ST/threadx/common/src/txe_semaphore_put.c;Middlewares/ST/threadx/common/src/txe_semaphore_put_notify.c;Middlewares/ST/threadx/common/src/txe_thread_create.c;Middlewares/ST/threadx/common/src/txe_thread_delete.c;Middlewares/ST/threadx/common/src/txe_thread_entry_exit_notify.c;Middlewares/ST/threadx/common/src/txe_thread_info_get.c;Middlewares/ST/threadx/common/src/txe_thread_preemption_change.c;Middlewares/ST/threadx/common/src/txe_thread_priority_change.c;Middlewares/ST/threadx/common/src/txe_thread_relinquish.c;Middlewares/ST/threadx/common/src/txe_thread_reset.c;Middlewares/ST/threadx/common/src/txe_thread_resume.c;Middlewares/ST/threadx/common/src/txe_thread_suspend.c;Middlewares/ST/threadx/common/src/txe_thread_terminate.c;Middlewares/ST/threadx/common/src/txe_thread_time_slice_change.c;Middlewares/ST/threadx/common/src/txe_thread_wait_abort.c;Middlewares/ST/threadx/common/src/tx_timer_activate.c;Middlewares/ST/threadx/common/src/tx_timer_change.c;Middlewares/ST/threadx/common/src/tx_timer_create.c;Middlewares/ST/threadx/common/src/tx_timer_deactivate.c;Middlewares/ST/threadx/common/src/tx_timer_delete.c;Middlewares/ST/threadx/common/src/tx_timer_expiration_process.c;Middlewares/ST/threadx/common/src/tx_timer_info_get.c;Middlewares/ST/threadx/common/src/tx_timer_initialize.c;Middlewares/ST/threadx/common/src/tx_timer_system_activate.c;Middlewares/ST/threadx/common/src/tx_timer_system_deactivate.c;Middlewares/ST/threadx/common/src/tx_timer_thread_entry.c;Middlewares/ST/threadx/common/src/txe_timer_activate.c;Middlewares/ST/threadx/common/src/txe_timer_change.c;Middlewares/ST/threadx/common/src/txe_timer_create.c;Middlewares/ST/threadx/common/src/txe_timer_deactivate.c;Middlewares/ST/threadx/common/src/txe_timer_delete.c;Middlewares/ST/threadx/common/src/txe_timer_info_get.c;Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.c;Core/Src/system_stm32h5xx.c;;; +HeaderPath=../Drivers/STM32H5xx_HAL_Driver/Inc;../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy;../Middlewares/ST/threadx/common/inc;../Drivers/CMSIS/Device/ST/STM32H5xx/Include;Core/Inc;FileX/App;FileX/Target;AZURE_RTOS/App; +CDefines=USE_FULL_LL_DRIVER;FX_INCLUDE_USER_DEFINE_FILE;TX_INCLUDE_USER_DEFINE_FILE;TX_SINGLE_MODE_NON_SECURE:1;USE_FULL_LL_DRIVER;USE_HAL_DRIVER;STM32H573xx;USE_FULL_LL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; +ADefines=TX_SINGLE_MODE_NON_SECURE:1; + +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=26 +HeaderFiles#0=../Core/Inc/gpio.h +HeaderFiles#1=../Core/Inc/adc.h +HeaderFiles#2=../Core/Inc/eth.h +HeaderFiles#3=../FileX/App/app_filex.h +HeaderFiles#4=../FileX/App/fx_user.h +HeaderFiles#5=../FileX/Target/fx_stm32_sd_driver.h +HeaderFiles#6=../Core/Inc/fmc.h +HeaderFiles#7=../Core/Inc/gpdma.h +HeaderFiles#8=../Core/Inc/i2c.h +HeaderFiles#9=../Core/Inc/icache.h +HeaderFiles#10=../Core/Inc/linked_list.h +HeaderFiles#11=../Core/Inc/memorymap.h +HeaderFiles#12=../Core/Inc/octospi.h +HeaderFiles#13=../Core/Inc/sai.h +HeaderFiles#14=../Core/Inc/sdmmc.h +HeaderFiles#15=../Core/Inc/app_threadx.h +HeaderFiles#16=../AZURE_RTOS/App/app_azure_rtos.h +HeaderFiles#17=../Core/Inc/tx_user.h +HeaderFiles#18=../AZURE_RTOS/App/app_azure_rtos_config.h +HeaderFiles#19=../Core/Inc/tim.h +HeaderFiles#20=../Core/Inc/ucpd.h +HeaderFiles#21=../Core/Inc/usart.h +HeaderFiles#22=../Core/Inc/stm32h5xx_it.h +HeaderFiles#23=../Core/Inc/stm32_assert.h +HeaderFiles#24=../Core/Inc/stm32h5xx_hal_conf.h +HeaderFiles#25=../Core/Inc/main.h +HeaderFolderListSize=4 +HeaderPath#0=../Core/Inc +HeaderPath#1=../FileX/App +HeaderPath#2=../FileX/Target +HeaderPath#3=../AZURE_RTOS/App +HeaderFiles=; +SourceFileListSize=24 +SourceFiles#0=../Core/Src/tx_initialize_low_level.S +SourceFiles#1=../Core/Src/gpio.c +SourceFiles#2=../Core/Src/adc.c +SourceFiles#3=../Core/Src/eth.c +SourceFiles#4=../FileX/App/app_filex.c +SourceFiles#5=../FileX/Target/fx_stm32_sd_driver_glue.c +SourceFiles#6=../Core/Src/fmc.c +SourceFiles#7=../Core/Src/gpdma.c +SourceFiles#8=../Core/Src/i2c.c +SourceFiles#9=../Core/Src/icache.c +SourceFiles#10=../Core/Src/linked_list.c +SourceFiles#11=../Core/Src/memorymap.c +SourceFiles#12=../Core/Src/octospi.c +SourceFiles#13=../Core/Src/sai.c +SourceFiles#14=../Core/Src/sdmmc.c +SourceFiles#15=../Core/Src/app_threadx.c +SourceFiles#16=../AZURE_RTOS/App/app_azure_rtos.c +SourceFiles#17=../Core/Src/tim.c +SourceFiles#18=../Core/Src/ucpd.c +SourceFiles#19=../Core/Src/usart.c +SourceFiles#20=../Core/Src/stm32h5xx_it.c +SourceFiles#21=../Core/Src/stm32h5xx_hal_msp.c +SourceFiles#22=../Core/Src/stm32h5xx_hal_timebase_tim.c +SourceFiles#23=../Core/Src/main.c +SourceFolderListSize=4 +SourcePath#0=../Core/Src +SourcePath#1=../FileX/App +SourcePath#2=../FileX/Target +SourcePath#3=../AZURE_RTOS/App +SourceFiles=; + diff --git a/benchmark/interface/.project b/benchmark/interface/.project new file mode 100644 index 00000000..11a0048a --- /dev/null +++ b/benchmark/interface/.project @@ -0,0 +1,11 @@ + + + interface + + + + + + + + diff --git a/benchmark/interface/Application/CLI/InterfaceMenu.cpp b/benchmark/interface/Application/CLI/InterfaceMenu.cpp index 75985541..ca8811c2 100644 --- a/benchmark/interface/Application/CLI/InterfaceMenu.cpp +++ b/benchmark/interface/Application/CLI/InterfaceMenu.cpp @@ -1,6 +1,11 @@ #include "InterfaceMenu.hpp" #include "../IDataSource.hpp" +#include "../Audio/WaveSink.hpp" #include "../ResourceManager.hpp" +#include "usart.h" +#include "baud_config.h" + + void CLI_Init(TX_BYTE_POOL *byte_pool, UART_HandleTypeDef *huart) { @@ -14,6 +19,29 @@ void CLI_Run() CLI::InterfaceMenu::GetSingleton().Run(); } +void Record_WW_Detection() +{ + CLI::InterfaceMenu::GetSingleton().RecordOneDetection(); +} + +void Record_Dutycycle_Start() +{ + if( CLI::InterfaceMenu::InstanceInitialized() ) + { + // only call this if the CLI instance is initialized + CLI::InterfaceMenu::GetSingleton().DutycycleStart(); + } +} +void Record_Dutycycle_Stop() +{ + if( CLI::InterfaceMenu::InstanceInitialized() ) + { + // only call this if the CLI instance is initialized + CLI::InterfaceMenu::GetSingleton().DutycycleStop(); + } +} + + namespace CLI { InterfaceMenu *InterfaceMenu::instance = (InterfaceMenu *)TX_NULL; @@ -26,8 +54,22 @@ namespace CLI {"name", NameWrapper}, {"ls", ListWrapper}, {"play", PlayWrapper}, + {"setbaud", SetBaudWrapper}, + {"checkbaud", CheckBaudWrapper}, + {"record_detections", RecDetsWrapper}, + {"print_detections", PrintDetsWrapper}, + {"print_dutycycle", PrintDutycycleWrapper}, {"", DefaultWrapper} }; + bool InterfaceMenu::InstanceInitialized() + { + if( instance ) + return true; + else + return false; + } + + /** * Wrap the singleton function in a static function */ @@ -51,6 +93,43 @@ namespace CLI { instance->Play(args); } + /** + * Wrap the singleton function in a static function + */ + void InterfaceMenu::SetBaudWrapper(const std::string &args) + { + instance->SetBaud(args); + } + /** + * Wrap the singleton function in a static function + */ + void InterfaceMenu::CheckBaudWrapper(const std::string &args) + { + instance->CheckBaud(args); + } + /** + * Wrap the singleton function in a static function + */ + void InterfaceMenu::RecDetsWrapper(const std::string &args) + { + instance->RecordDetections(args); + } + + /** + * Wrap the singleton function in a static function + */ + void InterfaceMenu::PrintDetsWrapper(const std::string &args) + { + instance->PrintDetections(args); + } + + /** + * Wrap the singleton function in a static function + */ + void InterfaceMenu::PrintDutycycleWrapper(const std::string &args) + { + instance->PrintDutycycle(args); + } /** * Wrap the singleton function in a static function @@ -155,14 +234,132 @@ namespace CLI */ void InterfaceMenu::Play(const std::string &args) { + Audio::PlayerResult result; IDataSource *source = file_system.OpenFile(args); Audio::WaveSource wav(*source); - std::string *msg = new std::string("Playing "); +// if( !wav.valid_wave ) { +// std::string *msg = new std::string("Error. Not a valid wav file: "); +// msg->append(source->GetName()); +// msg->append("\n"); +// SendString(msg->c_str()); +// } + std::string *msg = new std::string("Attempting to play "); msg->append(source->GetName()); msg->append("\n"); SendString(msg->c_str()); - player.Play(wav); + result = player.Play(wav); + if( result == Audio::ERROR ) { + SendString("Error playing file. Check that the file exists and is a 2-channel wav file.\n"); + } + else { + SendString("succeeded.\n"); + } + SendEnd(); delete source; } + + /** + * Set the new baud rate for the board + */ + void InterfaceMenu::SetBaud(const std::string &args) + { + int baud = std::stoi(args); + SaveBaudRateToFlash(baud); // Save permanently to Flash + + SendString("set baud to: " + args + "\n"); + + SendEnd(); + NVIC_SystemReset(); //Reset the MCU + } + + + /** + * Check the current baud rate + */ + void InterfaceMenu::CheckBaud(const std::string &args) + { + int currentBaud = huart3.Init.BaudRate; + + SendString("baud is: " + std::to_string(currentBaud) + "\n"); + + SendEnd(); // End response + } + + + + + void InterfaceMenu::RecordDetections(const std::string &args) + { + // Sets the interface board into mode to capture detections, + // but the detections are recorded in an interrupt handler, + // so we can return here and proceed to playing the wav file + + __HAL_TIM_SET_COUNTER(&htim2, 0); + SendString("Now recording detections"); + SendEndLine(); + dut.StartRecordingDetections(); + SendEnd(); + } + + void InterfaceMenu::PrintDetections(const std::string &args) + { + uint32_t *timestamps = dut.GetDetections(); + uint32_t num_timestamps = dut.GetNumDetections(); + + SendString("Detection Timestamps (ms)"); + SendEndLine(); + for(uint32_t i=0; i #include "DeviceUnderTest.hpp" #include "usart.h" #include "../Tasks/ITask.hpp" @@ -31,8 +32,10 @@ class SendCommandTask : public Tasks::IIndirectTask }; - DeviceUnderTest::DeviceUnderTest(Tasks::TaskRunner &runner, IO::Uart *uart) : runner(runner), uart(*uart) + DeviceUnderTest::DeviceUnderTest(Tasks::TaskRunner &runner, IO::Uart *uart) : runner(runner), uart(*uart), wwdet_timestamp_idx(0) { +// procstart_timestamps = (uint32_t *)malloc(MAX_FRAMES*sizeof(uint32_t)); +// procstop_timestamps = (uint32_t *)malloc(MAX_FRAMES*sizeof(uint32_t)); } void DeviceUnderTest::SendCommand(const std::string &command, TX_QUEUE *queue) @@ -59,4 +62,98 @@ class SendCommandTask : public Tasks::IIndirectTask VOID *tx_msg = TX_NULL; tx_queue_send(queue, &tx_msg, TX_WAIT_FOREVER); } + + void DeviceUnderTest::RecordDetection() + { + // This function is called from the WW_DET_IN falling edge ISR + uint32_t current_time_ms = __HAL_TIM_GET_COUNTER(&htim2) / 100; // tim2 has 10us period + + // don't record two detections within 10ms and + // don't overrun the end of the allocated array + if((wwdet_timestamps[wwdet_timestamp_idx-1] < current_time_ms - 10 || + wwdet_timestamps[wwdet_timestamp_idx-1] > current_time_ms) && // if the timer rolled over + wwdet_timestamp_idx < MAX_TIMESTAMPS ) + { + wwdet_timestamps[wwdet_timestamp_idx++] = current_time_ms; + } + } + + void DeviceUnderTest::RecordDutycycleStart() + { + // This function is called from the DUT_DUTY_CYCLE rising edge ISR + uint32_t current_time_10us = __HAL_TIM_GET_COUNTER(&htim2); + + // don't overrun the end of the allocated array + if( procstart_timestamps_idx < MAX_FRAMES ) + { + procstart_timestamps[procstart_timestamps_idx++] = current_time_10us; + } + } + + void DeviceUnderTest::RecordDutycycleStop() + { + // This function is called from the DUT_DUTY_CYCLE falling edge ISR + uint32_t current_time_10us = __HAL_TIM_GET_COUNTER(&htim2); + + // don't overrun the end of the allocated array + if( procstop_timestamps_idx < MAX_FRAMES ) + { + procstop_timestamps[procstop_timestamps_idx++] = current_time_10us; + } + } + + + uint32_t *DeviceUnderTest::GetDetections() + { + return wwdet_timestamps; + } + + uint32_t DeviceUnderTest::GetNumDetections() + { + return wwdet_timestamp_idx; + } + + void DeviceUnderTest::ClearDetections() + { + std::memset(wwdet_timestamps, 0, sizeof(wwdet_timestamps)); + wwdet_timestamp_idx = 0; + } + + void DeviceUnderTest::ClearDutycycleTimestamps() + { + std::memset(procstart_timestamps, 0, sizeof(procstart_timestamps)); + procstart_timestamps_idx = 0; + + std::memset(procstop_timestamps, 0, sizeof(procstop_timestamps)); + procstop_timestamps_idx = 0; + } + + uint32_t DeviceUnderTest::GetNumDutycycleRisingEdges() + { + return procstart_timestamps_idx; + } + uint32_t *DeviceUnderTest::GetDutycycleRisingEdges() + { + return procstart_timestamps; + } + + uint32_t DeviceUnderTest::GetNumDutycycleFallingEdges() + { + return procstop_timestamps_idx; + } + + uint32_t *DeviceUnderTest::GetDutycycleFallingEdges() + { + return procstop_timestamps; + } + + + void DeviceUnderTest::StartRecordingDetections() + { + ClearDetections(); + ClearDutycycleTimestamps(); + dut_state=RecordingDetections; + } + } + diff --git a/benchmark/interface/Application/Test/DeviceUnderTest.hpp b/benchmark/interface/Application/Test/DeviceUnderTest.hpp index 01fdac30..97a9ad60 100644 --- a/benchmark/interface/Application/Test/DeviceUnderTest.hpp +++ b/benchmark/interface/Application/Test/DeviceUnderTest.hpp @@ -3,11 +3,21 @@ #include "tx_api.h" #include +#include #include "../IO/Uart.hpp" #include "../Tasks/TaskRunner.hpp" +#include "stm32h5xx_hal_tim.h" +#include "tim.h" + +#define MAX_TIMESTAMPS 10000 +#define MAX_FRAMES 100 namespace Test { + typedef enum dut_state_enum { + Idle, + RecordingDetections, + } dut_state_t; class SendCommandTask; /** @@ -29,11 +39,37 @@ namespace Test * @param queue The queue to send the response to */ void SendCommand(const std::string &command, TX_QUEUE *queue = (TX_QUEUE *) TX_NULL); + void RecordDetection(); + void ClearDetections(); + void RecordDutycycleStart(); + void RecordDutycycleStop(); + void ClearDutycycleTimestamps(); + void StartRecordingDetections(); + + uint32_t *GetDetections(); + uint32_t GetNumDetections(); + + uint32_t GetNumDutycycleRisingEdges(); + uint32_t *GetDutycycleRisingEdges(); + uint32_t GetNumDutycycleFallingEdges(); + uint32_t *GetDutycycleFallingEdges(); + + private: friend class SendCommandTask; Tasks::TaskRunner &runner; IO::Uart &uart; + dut_state_t dut_state=Idle; void IndirectSendCommand(const std::string &command, TX_QUEUE *queue = (TX_QUEUE *) TX_NULL); + uint32_t wwdet_timestamps[MAX_TIMESTAMPS] = {0}; + uint32_t wwdet_timestamp_idx = 0; + + uint32_t procstart_timestamps[MAX_FRAMES] = {0}; + uint32_t procstart_timestamps_idx = 0; + + uint32_t procstop_timestamps[MAX_FRAMES] = {0}; + uint32_t procstop_timestamps_idx = 0; + }; } diff --git a/benchmark/interface/Core/Inc/baud_config.h b/benchmark/interface/Core/Inc/baud_config.h new file mode 100644 index 00000000..7d5ede1e --- /dev/null +++ b/benchmark/interface/Core/Inc/baud_config.h @@ -0,0 +1,21 @@ +#ifndef BAUD_CONFIG_H +#define BAUD_CONFIG_H + +#include "stm32h5xx_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define DEFAULT_BAUDRATE 9600U + +// In baud_config.h +uint32_t LoadBaudRateFromFlash(void); +uint32_t LoadBaudRateFromFlashWithDefault(uint32_t fallback); +HAL_StatusTypeDef SaveBaudRateToFlash(uint32_t baud); + +#ifdef __cplusplus +} +#endif + +#endif // BAUD_CONFIG_H diff --git a/benchmark/interface/Core/Inc/i2c.h b/benchmark/interface/Core/Inc/i2c.h new file mode 100644 index 00000000..e5f10f58 --- /dev/null +++ b/benchmark/interface/Core/Inc/i2c.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file i2c.h + * @brief This file contains all the function prototypes for + * the i2c.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __I2C_H__ +#define __I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern I2C_HandleTypeDef hi2c1; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_I2C1_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __I2C_H__ */ + diff --git a/benchmark/interface/Core/Inc/main.h b/benchmark/interface/Core/Inc/main.h index b1abdef7..b20d1afe 100644 --- a/benchmark/interface/Core/Inc/main.h +++ b/benchmark/interface/Core/Inc/main.h @@ -1,294 +1,296 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file : main.h - * @brief : Header for main.c file. - * This file contains the common defines of the application. - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MAIN_H -#define __MAIN_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32h5xx_hal.h" - -#include "stm32h5xx_ll_ucpd.h" -#include "stm32h5xx_ll_bus.h" -#include "stm32h5xx_ll_cortex.h" -#include "stm32h5xx_ll_rcc.h" -#include "stm32h5xx_ll_system.h" -#include "stm32h5xx_ll_utils.h" -#include "stm32h5xx_ll_pwr.h" -#include "stm32h5xx_ll_gpio.h" -#include "stm32h5xx_ll_dma.h" - -#include "stm32h5xx_ll_exti.h" - -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Exported types ------------------------------------------------------------*/ -/* USER CODE BEGIN ET */ - -/* USER CODE END ET */ - -/* Exported constants --------------------------------------------------------*/ -/* USER CODE BEGIN EC */ - -/* USER CODE END EC */ - -/* Exported macro ------------------------------------------------------------*/ -/* USER CODE BEGIN EM */ - -/* USER CODE END EM */ - -/* Exported functions prototypes ---------------------------------------------*/ -void Error_Handler(void); - -/* USER CODE BEGIN EFP */ - -/* USER CODE END EFP */ - -/* Private defines -----------------------------------------------------------*/ -#define SAI2_FS_A_Pin GPIO_PIN_7 -#define SAI2_FS_A_GPIO_Port GPIOI -#define SAI2_SCK_A_Pin GPIO_PIN_5 -#define SAI2_SCK_A_GPIO_Port GPIOI -#define ARD_D3_Pin GPIO_PIN_5 -#define ARD_D3_GPIO_Port GPIOB -#define ARD_D2_Pin GPIO_PIN_15 -#define ARD_D2_GPIO_Port GPIOG -#define TRACED1_Pin GPIO_PIN_14 -#define TRACED1_GPIO_Port GPIOG -#define SAI2_SD_B_Pin GPIO_PIN_10 -#define SAI2_SD_B_GPIO_Port GPIOG -#define LCD_NWE_Pin GPIO_PIN_5 -#define LCD_NWE_GPIO_Port GPIOD -#define LCD_TE_Pin GPIO_PIN_3 -#define LCD_TE_GPIO_Port GPIOD -#define LCD_D3_Pin GPIO_PIN_1 -#define LCD_D3_GPIO_Port GPIOD -#define LCD_BL_CTRL_Pin GPIO_PIN_3 -#define LCD_BL_CTRL_GPIO_Port GPIOI -#define ARD_D13_Pin GPIO_PIN_1 -#define ARD_D13_GPIO_Port GPIOI -#define TRACED0_Pin GPIO_PIN_3 -#define TRACED0_GPIO_Port GPIOE -#define SAI2_MCLK_A_Pin GPIO_PIN_4 -#define SAI2_MCLK_A_GPIO_Port GPIOI -#define MEMS_LED_Pin GPIO_PIN_1 -#define MEMS_LED_GPIO_Port GPIOE -#define I2C1_SCL_Pin GPIO_PIN_6 -#define I2C1_SCL_GPIO_Port GPIOB -#define SWO_Pin GPIO_PIN_3 -#define SWO_GPIO_Port GPIOB -#define RMII_TXD1_Pin GPIO_PIN_12 -#define RMII_TXD1_GPIO_Port GPIOG -#define LCD_NOE_Pin GPIO_PIN_4 -#define LCD_NOE_GPIO_Port GPIOD -#define LCD_D2_Pin GPIO_PIN_0 -#define LCD_D2_GPIO_Port GPIOD -#define JTCK_Pin GPIO_PIN_14 -#define JTCK_GPIO_Port GPIOA -#define ARD_D12_Pin GPIO_PIN_2 -#define ARD_D12_GPIO_Port GPIOI -#define LCD_RST_Pin GPIO_PIN_13 -#define LCD_RST_GPIO_Port GPIOH -#define TRACED3_Pin GPIO_PIN_6 -#define TRACED3_GPIO_Port GPIOE -#define SAI2_SD_A_Pin GPIO_PIN_6 -#define SAI2_SD_A_GPIO_Port GPIOI -#define DETECTN_Pin GPIO_PIN_0 -#define DETECTN_GPIO_Port GPIOE -#define I2C1_SDA_Pin GPIO_PIN_7 -#define I2C1_SDA_GPIO_Port GPIOB -#define NJTRST_Pin GPIO_PIN_4 -#define NJTRST_GPIO_Port GPIOB -#define RMII_TXD0_Pin GPIO_PIN_13 -#define RMII_TXD0_GPIO_Port GPIOG -#define RMII_TX_EN_Pin GPIO_PIN_11 -#define RMII_TX_EN_GPIO_Port GPIOG -#define SDIO1_CMD_Pin GPIO_PIN_2 -#define SDIO1_CMD_GPIO_Port GPIOD -#define SDIO1_CK_Pin GPIO_PIN_12 -#define SDIO1_CK_GPIO_Port GPIOC -#define SDIO1_D3_Pin GPIO_PIN_11 -#define SDIO1_D3_GPIO_Port GPIOC -#define JTDI_Pin GPIO_PIN_15 -#define JTDI_GPIO_Port GPIOA -#define USB_FS_P_Pin GPIO_PIN_12 -#define USB_FS_P_GPIO_Port GPIOA -#define TRACED2_Pin GPIO_PIN_5 -#define TRACED2_GPIO_Port GPIOE -#define SDIO1_D2_Pin GPIO_PIN_10 -#define SDIO1_D2_GPIO_Port GPIOC -#define uSD_DETECT_Pin GPIO_PIN_14 -#define uSD_DETECT_GPIO_Port GPIOH -#define uSD_DETECT_EXTI_IRQn EXTI14_IRQn -#define USB_FS_N_Pin GPIO_PIN_11 -#define USB_FS_N_GPIO_Port GPIOA -#define GREEN_LED_Pin GPIO_PIN_9 -#define GREEN_LED_GPIO_Port GPIOI -#define ORANGE_LED_Pin GPIO_PIN_8 -#define ORANGE_LED_GPIO_Port GPIOI -#define WAKEUP_Pin GPIO_PIN_13 -#define WAKEUP_GPIO_Port GPIOC -#define JTMS_Pin GPIO_PIN_13 -#define JTMS_GPIO_Port GPIOA -#define STLK_VCP_TX_Pin GPIO_PIN_10 -#define STLK_VCP_TX_GPIO_Port GPIOA -#define STLK_VCP_RX_Pin GPIO_PIN_9 -#define STLK_VCP_RX_GPIO_Port GPIOA -#define RED_LED_Pin GPIO_PIN_1 -#define RED_LED_GPIO_Port GPIOF -#define LCD_A0_RS_Pin GPIO_PIN_0 -#define LCD_A0_RS_GPIO_Port GPIOF -#define AUDIO_NRST_Pin GPIO_PIN_11 -#define AUDIO_NRST_GPIO_Port GPIOI -#define RMII_RX_ER_Pin GPIO_PIN_10 -#define RMII_RX_ER_GPIO_Port GPIOI -#define SDIO1_D1_Pin GPIO_PIN_9 -#define SDIO1_D1_GPIO_Port GPIOC -#define SDIO1_D0_Pin GPIO_PIN_8 -#define SDIO1_D0_GPIO_Port GPIOC -#define ARD_D9_Pin GPIO_PIN_8 -#define ARD_D9_GPIO_Port GPIOA -#define BLUE_LED_Pin GPIO_PIN_4 -#define BLUE_LED_GPIO_Port GPIOF -#define STMOD_17_Pin GPIO_PIN_3 -#define STMOD_17_GPIO_Port GPIOF -#define LCD_PWR_ON_Pin GPIO_PIN_6 -#define LCD_PWR_ON_GPIO_Port GPIOC -#define ARD_D8_Pin GPIO_PIN_8 -#define ARD_D8_GPIO_Port GPIOG -#define LCD_CTP_INT_Pin GPIO_PIN_7 -#define LCD_CTP_INT_GPIO_Port GPIOG -#define LCD_CTP_RST_Pin GPIO_PIN_3 -#define LCD_CTP_RST_GPIO_Port GPIOG -#define ARD_D7_Pin GPIO_PIN_5 -#define ARD_D7_GPIO_Port GPIOG -#define LCD_D1_Pin GPIO_PIN_15 -#define LCD_D1_GPIO_Port GPIOD -#define ARD_D4_Pin GPIO_PIN_4 -#define ARD_D4_GPIO_Port GPIOG -#define LCD_D15_Pin GPIO_PIN_10 -#define LCD_D15_GPIO_Port GPIOD -#define LCD_D0_Pin GPIO_PIN_14 -#define LCD_D0_GPIO_Port GPIOD -#define RMII_MDC_Pin GPIO_PIN_1 -#define RMII_MDC_GPIO_Port GPIOC -#define RMII_REF_CLK_Pin GPIO_PIN_1 -#define RMII_REF_CLK_GPIO_Port GPIOA -#define STMOD_18_Pin GPIO_PIN_12 -#define STMOD_18_GPIO_Port GPIOB -#define LCD_D14_Pin GPIO_PIN_9 -#define LCD_D14_GPIO_Port GPIOD -#define RMII_MDIO_Pin GPIO_PIN_2 -#define RMII_MDIO_GPIO_Port GPIOA -#define ARD_A1_Pin GPIO_PIN_4 -#define ARD_A1_GPIO_Port GPIOA -#define ARD_D1_Pin GPIO_PIN_10 -#define ARD_D1_GPIO_Port GPIOB -#define STMOD_11_INT_Pin GPIO_PIN_9 -#define STMOD_11_INT_GPIO_Port GPIOH -#define STMOD_14_PWM_Pin GPIO_PIN_12 -#define STMOD_14_PWM_GPIO_Port GPIOH -#define ARD_D11_Pin GPIO_PIN_15 -#define ARD_D11_GPIO_Port GPIOB -#define LCD_D13_Pin GPIO_PIN_8 -#define LCD_D13_GPIO_Port GPIOD -#define PDM_SAI1_SD3_Pin GPIO_PIN_3 -#define PDM_SAI1_SD3_GPIO_Port GPIOC -#define RMII_RXD0_Pin GPIO_PIN_4 -#define RMII_RXD0_GPIO_Port GPIOC -#define ARD_D10_Pin GPIO_PIN_3 -#define ARD_D10_GPIO_Port GPIOA -#define ARD_A5_Pin GPIO_PIN_12 -#define ARD_A5_GPIO_Port GPIOF -#define LCD_D6_Pin GPIO_PIN_9 -#define LCD_D6_GPIO_Port GPIOE -#define LCD_D11_Pin GPIO_PIN_14 -#define LCD_D11_GPIO_Port GPIOE -#define LCD_D12_Pin GPIO_PIN_15 -#define LCD_D12_GPIO_Port GPIOE -#define ARD_D0_Pin GPIO_PIN_11 -#define ARD_D0_GPIO_Port GPIOB -#define STMOD_9_MISOs_Pin GPIO_PIN_8 -#define STMOD_9_MISOs_GPIO_Port GPIOH -#define ARD_D6_Pin GPIO_PIN_10 -#define ARD_D6_GPIO_Port GPIOH -#define UCPD_CC2_Pin GPIO_PIN_14 -#define UCPD_CC2_GPIO_Port GPIOB -#define STMOD_20_Pin GPIO_PIN_5 -#define STMOD_20_GPIO_Port GPIOH -#define ARD_A2_Pin GPIO_PIN_0 -#define ARD_A2_GPIO_Port GPIOA -#define RMII_RXD1_Pin GPIO_PIN_5 -#define RMII_RXD1_GPIO_Port GPIOC -#define ARD_A4_Pin GPIO_PIN_6 -#define ARD_A4_GPIO_Port GPIOA -#define IBUS_SENSE_Pin GPIO_PIN_13 -#define IBUS_SENSE_GPIO_Port GPIOF -#define UCPD_FLT_Pin GPIO_PIN_1 -#define UCPD_FLT_GPIO_Port GPIOG -#define LCD_D5_Pin GPIO_PIN_8 -#define LCD_D5_GPIO_Port GPIOE -#define LCD_D8_Pin GPIO_PIN_11 -#define LCD_D8_GPIO_Port GPIOE -#define LCD_D10_Pin GPIO_PIN_13 -#define LCD_D10_GPIO_Port GPIOE -#define STMOD_12_Pin GPIO_PIN_6 -#define STMOD_12_GPIO_Port GPIOH -#define STMOD_12_RST_Pin GPIO_PIN_7 -#define STMOD_12_RST_GPIO_Port GPIOH -#define ARD_D5_Pin GPIO_PIN_11 -#define ARD_D5_GPIO_Port GPIOH -#define STMOD_19_Pin GPIO_PIN_4 -#define STMOD_19_GPIO_Port GPIOH -#define ARD_A3_Pin GPIO_PIN_5 -#define ARD_A3_GPIO_Port GPIOA -#define RMII_CRS_DV_Pin GPIO_PIN_7 -#define RMII_CRS_DV_GPIO_Port GPIOA -#define ARD_A0_Pin GPIO_PIN_0 -#define ARD_A0_GPIO_Port GPIOB -#define STMOD_13_Pin GPIO_PIN_11 -#define STMOD_13_GPIO_Port GPIOF -#define VBUS_SENSE_Pin GPIO_PIN_14 -#define VBUS_SENSE_GPIO_Port GPIOF -#define UCPD_PWR_Pin GPIO_PIN_0 -#define UCPD_PWR_GPIO_Port GPIOG -#define LCD_D7_Pin GPIO_PIN_10 -#define LCD_D7_GPIO_Port GPIOE -#define LCD_D9_Pin GPIO_PIN_12 -#define LCD_D9_GPIO_Port GPIOE -#define UCPD_CC1_Pin GPIO_PIN_13 -#define UCPD_CC1_GPIO_Port GPIOB - -/* USER CODE BEGIN Private defines */ - -/* USER CODE END Private defines */ - -#ifdef __cplusplus -} -#endif - -#endif /* __MAIN_H */ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +#include "stm32h5xx_ll_ucpd.h" +#include "stm32h5xx_ll_bus.h" +#include "stm32h5xx_ll_cortex.h" +#include "stm32h5xx_ll_rcc.h" +#include "stm32h5xx_ll_system.h" +#include "stm32h5xx_ll_utils.h" +#include "stm32h5xx_ll_pwr.h" +#include "stm32h5xx_ll_gpio.h" +#include "stm32h5xx_ll_dma.h" + +#include "stm32h5xx_ll_exti.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define SAI2_FS_A_Pin GPIO_PIN_7 +#define SAI2_FS_A_GPIO_Port GPIOI +#define SAI2_SCK_A_Pin GPIO_PIN_5 +#define SAI2_SCK_A_GPIO_Port GPIOI +#define DUT_DUTY_CYCLE_Pin GPIO_PIN_5 +#define DUT_DUTY_CYCLE_GPIO_Port GPIOB +#define DUT_DUTY_CYCLE_EXTI_IRQn EXTI5_IRQn +#define WW_DET_IN_Pin GPIO_PIN_15 +#define WW_DET_IN_GPIO_Port GPIOG +#define WW_DET_IN_EXTI_IRQn EXTI15_IRQn +#define TRACED1_Pin GPIO_PIN_14 +#define TRACED1_GPIO_Port GPIOG +#define SAI2_SD_B_Pin GPIO_PIN_10 +#define SAI2_SD_B_GPIO_Port GPIOG +#define LCD_NWE_Pin GPIO_PIN_5 +#define LCD_NWE_GPIO_Port GPIOD +#define LCD_TE_Pin GPIO_PIN_3 +#define LCD_TE_GPIO_Port GPIOD +#define LCD_D3_Pin GPIO_PIN_1 +#define LCD_D3_GPIO_Port GPIOD +#define LCD_BL_CTRL_Pin GPIO_PIN_3 +#define LCD_BL_CTRL_GPIO_Port GPIOI +#define ARD_D13_Pin GPIO_PIN_1 +#define ARD_D13_GPIO_Port GPIOI +#define TRACED0_Pin GPIO_PIN_3 +#define TRACED0_GPIO_Port GPIOE +#define SAI2_MCLK_A_Pin GPIO_PIN_4 +#define SAI2_MCLK_A_GPIO_Port GPIOI +#define MEMS_LED_Pin GPIO_PIN_1 +#define MEMS_LED_GPIO_Port GPIOE +#define I2C1_SCL_Pin GPIO_PIN_6 +#define I2C1_SCL_GPIO_Port GPIOB +#define SWO_Pin GPIO_PIN_3 +#define SWO_GPIO_Port GPIOB +#define RMII_TXD1_Pin GPIO_PIN_12 +#define RMII_TXD1_GPIO_Port GPIOG +#define LCD_NOE_Pin GPIO_PIN_4 +#define LCD_NOE_GPIO_Port GPIOD +#define LCD_D2_Pin GPIO_PIN_0 +#define LCD_D2_GPIO_Port GPIOD +#define JTCK_Pin GPIO_PIN_14 +#define JTCK_GPIO_Port GPIOA +#define ARD_D12_Pin GPIO_PIN_2 +#define ARD_D12_GPIO_Port GPIOI +#define LCD_RST_Pin GPIO_PIN_13 +#define LCD_RST_GPIO_Port GPIOH +#define TRACED3_Pin GPIO_PIN_6 +#define TRACED3_GPIO_Port GPIOE +#define SAI2_SD_A_Pin GPIO_PIN_6 +#define SAI2_SD_A_GPIO_Port GPIOI +#define DETECTN_Pin GPIO_PIN_0 +#define DETECTN_GPIO_Port GPIOE +#define I2C1_SDA_Pin GPIO_PIN_7 +#define I2C1_SDA_GPIO_Port GPIOB +#define NJTRST_Pin GPIO_PIN_4 +#define NJTRST_GPIO_Port GPIOB +#define RMII_TXD0_Pin GPIO_PIN_13 +#define RMII_TXD0_GPIO_Port GPIOG +#define RMII_TX_EN_Pin GPIO_PIN_11 +#define RMII_TX_EN_GPIO_Port GPIOG +#define SDIO1_CMD_Pin GPIO_PIN_2 +#define SDIO1_CMD_GPIO_Port GPIOD +#define SDIO1_CK_Pin GPIO_PIN_12 +#define SDIO1_CK_GPIO_Port GPIOC +#define SDIO1_D3_Pin GPIO_PIN_11 +#define SDIO1_D3_GPIO_Port GPIOC +#define JTDI_Pin GPIO_PIN_15 +#define JTDI_GPIO_Port GPIOA +#define USB_FS_P_Pin GPIO_PIN_12 +#define USB_FS_P_GPIO_Port GPIOA +#define TRACED2_Pin GPIO_PIN_5 +#define TRACED2_GPIO_Port GPIOE +#define SDIO1_D2_Pin GPIO_PIN_10 +#define SDIO1_D2_GPIO_Port GPIOC +#define uSD_DETECT_Pin GPIO_PIN_14 +#define uSD_DETECT_GPIO_Port GPIOH +#define uSD_DETECT_EXTI_IRQn EXTI14_IRQn +#define USB_FS_N_Pin GPIO_PIN_11 +#define USB_FS_N_GPIO_Port GPIOA +#define GREEN_LED_Pin GPIO_PIN_9 +#define GREEN_LED_GPIO_Port GPIOI +#define ORANGE_LED_Pin GPIO_PIN_8 +#define ORANGE_LED_GPIO_Port GPIOI +#define WAKEUP_Pin GPIO_PIN_13 +#define WAKEUP_GPIO_Port GPIOC +#define JTMS_Pin GPIO_PIN_13 +#define JTMS_GPIO_Port GPIOA +#define STLK_VCP_TX_Pin GPIO_PIN_10 +#define STLK_VCP_TX_GPIO_Port GPIOA +#define STLK_VCP_RX_Pin GPIO_PIN_9 +#define STLK_VCP_RX_GPIO_Port GPIOA +#define RED_LED_Pin GPIO_PIN_1 +#define RED_LED_GPIO_Port GPIOF +#define LCD_A0_RS_Pin GPIO_PIN_0 +#define LCD_A0_RS_GPIO_Port GPIOF +#define AUDIO_NRST_Pin GPIO_PIN_11 +#define AUDIO_NRST_GPIO_Port GPIOI +#define RMII_RX_ER_Pin GPIO_PIN_10 +#define RMII_RX_ER_GPIO_Port GPIOI +#define SDIO1_D1_Pin GPIO_PIN_9 +#define SDIO1_D1_GPIO_Port GPIOC +#define SDIO1_D0_Pin GPIO_PIN_8 +#define SDIO1_D0_GPIO_Port GPIOC +#define ARD_D9_Pin GPIO_PIN_8 +#define ARD_D9_GPIO_Port GPIOA +#define BLUE_LED_Pin GPIO_PIN_4 +#define BLUE_LED_GPIO_Port GPIOF +#define STMOD_17_Pin GPIO_PIN_3 +#define STMOD_17_GPIO_Port GPIOF +#define LCD_PWR_ON_Pin GPIO_PIN_6 +#define LCD_PWR_ON_GPIO_Port GPIOC +#define ARD_D8_Pin GPIO_PIN_8 +#define ARD_D8_GPIO_Port GPIOG +#define LCD_CTP_INT_Pin GPIO_PIN_7 +#define LCD_CTP_INT_GPIO_Port GPIOG +#define LCD_CTP_RST_Pin GPIO_PIN_3 +#define LCD_CTP_RST_GPIO_Port GPIOG +#define ARD_D7_Pin GPIO_PIN_5 +#define ARD_D7_GPIO_Port GPIOG +#define LCD_D1_Pin GPIO_PIN_15 +#define LCD_D1_GPIO_Port GPIOD +#define ARD_D4_Pin GPIO_PIN_4 +#define ARD_D4_GPIO_Port GPIOG +#define LCD_D15_Pin GPIO_PIN_10 +#define LCD_D15_GPIO_Port GPIOD +#define LCD_D0_Pin GPIO_PIN_14 +#define LCD_D0_GPIO_Port GPIOD +#define RMII_MDC_Pin GPIO_PIN_1 +#define RMII_MDC_GPIO_Port GPIOC +#define RMII_REF_CLK_Pin GPIO_PIN_1 +#define RMII_REF_CLK_GPIO_Port GPIOA +#define STMOD_18_Pin GPIO_PIN_12 +#define STMOD_18_GPIO_Port GPIOB +#define LCD_D14_Pin GPIO_PIN_9 +#define LCD_D14_GPIO_Port GPIOD +#define RMII_MDIO_Pin GPIO_PIN_2 +#define RMII_MDIO_GPIO_Port GPIOA +#define ARD_A1_Pin GPIO_PIN_4 +#define ARD_A1_GPIO_Port GPIOA +#define ARD_D1_Pin GPIO_PIN_10 +#define ARD_D1_GPIO_Port GPIOB +#define STMOD_11_INT_Pin GPIO_PIN_9 +#define STMOD_11_INT_GPIO_Port GPIOH +#define STMOD_14_PWM_Pin GPIO_PIN_12 +#define STMOD_14_PWM_GPIO_Port GPIOH +#define ARD_D11_Pin GPIO_PIN_15 +#define ARD_D11_GPIO_Port GPIOB +#define LCD_D13_Pin GPIO_PIN_8 +#define LCD_D13_GPIO_Port GPIOD +#define PDM_SAI1_SD3_Pin GPIO_PIN_3 +#define PDM_SAI1_SD3_GPIO_Port GPIOC +#define RMII_RXD0_Pin GPIO_PIN_4 +#define RMII_RXD0_GPIO_Port GPIOC +#define ARD_D10_Pin GPIO_PIN_3 +#define ARD_D10_GPIO_Port GPIOA +#define ARD_A5_Pin GPIO_PIN_12 +#define ARD_A5_GPIO_Port GPIOF +#define LCD_D6_Pin GPIO_PIN_9 +#define LCD_D6_GPIO_Port GPIOE +#define LCD_D11_Pin GPIO_PIN_14 +#define LCD_D11_GPIO_Port GPIOE +#define LCD_D12_Pin GPIO_PIN_15 +#define LCD_D12_GPIO_Port GPIOE +#define ARD_D0_Pin GPIO_PIN_11 +#define ARD_D0_GPIO_Port GPIOB +#define STMOD_9_MISOs_Pin GPIO_PIN_8 +#define STMOD_9_MISOs_GPIO_Port GPIOH +#define ARD_D6_Pin GPIO_PIN_10 +#define ARD_D6_GPIO_Port GPIOH +#define UCPD_CC2_Pin GPIO_PIN_14 +#define UCPD_CC2_GPIO_Port GPIOB +#define STMOD_20_Pin GPIO_PIN_5 +#define STMOD_20_GPIO_Port GPIOH +#define ARD_A2_Pin GPIO_PIN_0 +#define ARD_A2_GPIO_Port GPIOA +#define RMII_RXD1_Pin GPIO_PIN_5 +#define RMII_RXD1_GPIO_Port GPIOC +#define ARD_A4_Pin GPIO_PIN_6 +#define ARD_A4_GPIO_Port GPIOA +#define IBUS_SENSE_Pin GPIO_PIN_13 +#define IBUS_SENSE_GPIO_Port GPIOF +#define UCPD_FLT_Pin GPIO_PIN_1 +#define UCPD_FLT_GPIO_Port GPIOG +#define LCD_D5_Pin GPIO_PIN_8 +#define LCD_D5_GPIO_Port GPIOE +#define LCD_D8_Pin GPIO_PIN_11 +#define LCD_D8_GPIO_Port GPIOE +#define LCD_D10_Pin GPIO_PIN_13 +#define LCD_D10_GPIO_Port GPIOE +#define STMOD_12_Pin GPIO_PIN_6 +#define STMOD_12_GPIO_Port GPIOH +#define STMOD_12_RST_Pin GPIO_PIN_7 +#define STMOD_12_RST_GPIO_Port GPIOH +#define ARD_D5_Pin GPIO_PIN_11 +#define ARD_D5_GPIO_Port GPIOH +#define STMOD_19_Pin GPIO_PIN_4 +#define STMOD_19_GPIO_Port GPIOH +#define ARD_A3_Pin GPIO_PIN_5 +#define ARD_A3_GPIO_Port GPIOA +#define RMII_CRS_DV_Pin GPIO_PIN_7 +#define RMII_CRS_DV_GPIO_Port GPIOA +#define ARD_A0_Pin GPIO_PIN_0 +#define ARD_A0_GPIO_Port GPIOB +#define STMOD_13_Pin GPIO_PIN_11 +#define STMOD_13_GPIO_Port GPIOF +#define VBUS_SENSE_Pin GPIO_PIN_14 +#define VBUS_SENSE_GPIO_Port GPIOF +#define UCPD_PWR_Pin GPIO_PIN_0 +#define UCPD_PWR_GPIO_Port GPIOG +#define LCD_D7_Pin GPIO_PIN_10 +#define LCD_D7_GPIO_Port GPIOE +#define LCD_D9_Pin GPIO_PIN_12 +#define LCD_D9_GPIO_Port GPIOE +#define UCPD_CC1_Pin GPIO_PIN_13 +#define UCPD_CC1_GPIO_Port GPIOB + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/benchmark/interface/Core/Inc/stm32h5xx_hal_conf.h b/benchmark/interface/Core/Inc/stm32h5xx_hal_conf.h index 212f83d1..876418f6 100644 --- a/benchmark/interface/Core/Inc/stm32h5xx_hal_conf.h +++ b/benchmark/interface/Core/Inc/stm32h5xx_hal_conf.h @@ -184,7 +184,7 @@ */ #define VDD_VALUE 3300UL /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ +#define TICK_INT_PRIORITY (0UL) /*!< tick interrupt priority (lowest by default) */ #define USE_RTOS 0U #define PREFETCH_ENABLE 0U /*!< Enable prefetch */ diff --git a/benchmark/interface/Core/Inc/stm32h5xx_it.h b/benchmark/interface/Core/Inc/stm32h5xx_it.h index 0dbc9961..1a18311b 100644 --- a/benchmark/interface/Core/Inc/stm32h5xx_it.h +++ b/benchmark/interface/Core/Inc/stm32h5xx_it.h @@ -1,70 +1,72 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file stm32h5xx_it.h - * @brief This file contains the headers of the interrupt handlers. - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32H5xx_IT_H -#define __STM32H5xx_IT_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Exported types ------------------------------------------------------------*/ -/* USER CODE BEGIN ET */ - -/* USER CODE END ET */ - -/* Exported constants --------------------------------------------------------*/ -/* USER CODE BEGIN EC */ - -/* USER CODE END EC */ - -/* Exported macro ------------------------------------------------------------*/ -/* USER CODE BEGIN EM */ - -/* USER CODE END EM */ - -/* Exported functions prototypes ---------------------------------------------*/ -void NMI_Handler(void); -void HardFault_Handler(void); -void MemManage_Handler(void); -void BusFault_Handler(void); -void UsageFault_Handler(void); -void DebugMon_Handler(void); -void EXTI14_IRQHandler(void); -void GPDMA1_Channel2_IRQHandler(void); -void TIM6_IRQHandler(void); -void USART1_IRQHandler(void); -void USART3_IRQHandler(void); -void SDMMC1_IRQHandler(void); -void GPDMA2_Channel2_IRQHandler(void); -/* USER CODE BEGIN EFP */ - -/* USER CODE END EFP */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32H5xx_IT_H */ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h5xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H5xx_IT_H +#define __STM32H5xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void DebugMon_Handler(void); +void EXTI5_IRQHandler(void); +void EXTI14_IRQHandler(void); +void EXTI15_IRQHandler(void); +void GPDMA1_Channel2_IRQHandler(void); +void TIM6_IRQHandler(void); +void USART1_IRQHandler(void); +void USART3_IRQHandler(void); +void SDMMC1_IRQHandler(void); +void GPDMA2_Channel2_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H5xx_IT_H */ diff --git a/benchmark/interface/Core/Inc/tim.h b/benchmark/interface/Core/Inc/tim.h new file mode 100644 index 00000000..f52bef69 --- /dev/null +++ b/benchmark/interface/Core/Inc/tim.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file tim.h + * @brief This file contains all the function prototypes for + * the tim.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TIM_H__ +#define __TIM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern TIM_HandleTypeDef htim2; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_TIM2_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIM_H__ */ + diff --git a/benchmark/interface/Core/Inc/usart.h b/benchmark/interface/Core/Inc/usart.h index 9e81135e..b90159ff 100644 --- a/benchmark/interface/Core/Inc/usart.h +++ b/benchmark/interface/Core/Inc/usart.h @@ -1,57 +1,57 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file usart.h - * @brief This file contains all the function prototypes for - * the usart.c file - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USART_H__ -#define __USART_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" - -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -extern UART_HandleTypeDef huart1; - -extern UART_HandleTypeDef huart3; - -/* USER CODE BEGIN Private defines */ - -/* USER CODE END Private defines */ - -void MX_USART1_UART_Init(void); -void MX_USART3_UART_Init(void); - -/* USER CODE BEGIN Prototypes */ - -void UART_SendString(UART_HandleTypeDef *huart, const char *string); - -/* USER CODE END Prototypes */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USART_H__ */ - +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart.h + * @brief This file contains all the function prototypes for + * the usart.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USART_H__ +#define __USART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern UART_HandleTypeDef huart1; + +extern UART_HandleTypeDef huart3; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_USART1_UART_Init(void); +void MX_USART3_UART_Init(void); + +/* USER CODE BEGIN Prototypes */ + +void UART_SendString(UART_HandleTypeDef *huart, const char *string); + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USART_H__ */ + diff --git a/benchmark/interface/Core/Src/baud_config.c b/benchmark/interface/Core/Src/baud_config.c new file mode 100644 index 00000000..09b193c0 --- /dev/null +++ b/benchmark/interface/Core/Src/baud_config.c @@ -0,0 +1,68 @@ +#include // <-- Fixes uint32_t issues +#include "stm32h5xx_hal.h" // <-- Fixes HAL_StatusTypeDef and Flash HAL +#include "baud_config.h" // Your header (if it exists) +#include "stm32h5xx_hal_flash.h" + +#define CONFIG_FLASH_ADDR ((uint32_t)0x080FF800U) // Ensure 16-byte aligned and valid range +#define CONFIG_FLASH_SECTOR FLASH_SECTOR_127 // Choose based on actual layout +#define CONFIG_FLASH_BANK FLASH_BANK_1 + +typedef struct __attribute__((aligned(16))) { + uint32_t baudrate; + uint32_t reserved[3]; +} FlashBaudRate_t; + +static const FlashBaudRate_t *flash_data = (FlashBaudRate_t *)CONFIG_FLASH_ADDR; + +uint32_t LoadBaudRateFromFlashWithDefault(uint32_t fallback) +{ + uint32_t baud = flash_data->baudrate; + + if (baud == 0xFFFFFFFF || baud == 0 || baud > 2000000) { + return fallback; + } + + return baud; +} +uint32_t LoadBaudRateFromFlash(void) +{ + return LoadBaudRateFromFlashWithDefault(DEFAULT_BAUDRATE); +} + +HAL_StatusTypeDef SaveBaudRateToFlash(uint32_t baud) +{ + HAL_StatusTypeDef status; + FlashBaudRate_t data_to_write = { + .baudrate = baud, + .reserved = {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF} + }; + + HAL_FLASH_Unlock(); + + FLASH_EraseInitTypeDef erase = { + .TypeErase = FLASH_TYPEERASE_SECTORS, + .Banks = CONFIG_FLASH_BANK, + .Sector = CONFIG_FLASH_SECTOR, + .NbSectors = 1 + }; + + uint32_t sector_error = 0; + status = HAL_FLASHEx_Erase(&erase, §or_error); + if (status != HAL_OK) { + HAL_FLASH_Lock(); + return status; + } + + status = HAL_FLASH_Program(FLASH_TYPEPROGRAM_QUADWORD, + CONFIG_FLASH_ADDR, + (uint32_t)&data_to_write); + + HAL_FLASH_Lock(); + + // Optional: Confirm write + if (status == HAL_OK && flash_data->baudrate != baud) { + return HAL_ERROR; + } + + return status; +} diff --git a/benchmark/interface/Core/Src/gpio.c b/benchmark/interface/Core/Src/gpio.c index f89021e6..08184bbe 100644 --- a/benchmark/interface/Core/Src/gpio.c +++ b/benchmark/interface/Core/Src/gpio.c @@ -1,277 +1,276 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file gpio.c - * @brief This file provides code for the configuration - * of all used GPIO pins. - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "gpio.h" - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/*----------------------------------------------------------------------------*/ -/* Configure GPIO */ -/*----------------------------------------------------------------------------*/ -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ - -/** Configure pins - PI7 ------> SAI2_FS_A - PI5 ------> SAI2_SCK_A - PB5 ------> S_TIM3_CH2 - PG14 ------> DEBUG_TRACED1 - PG10 ------> SAI2_SD_B - PI1 ------> SPI2_SCK - PE3 ------> DEBUG_TRACED0 - PI4 ------> SAI2_MCLK_A - PB6 ------> I2C1_SCL - PB3(JTDO/TRACESWO) ------> DEBUG_JTDO-SWO - PA14(JTCK/SWCLK) ------> DEBUG_JTCK-SWCLK - PI2 ------> SPI2_MISO - PE6 ------> DEBUG_TRACED3 - PI6 ------> SAI2_SD_A - PB7 ------> I2C1_SDA - PB4(NJTRST) ------> DEBUG_JTRST - PA15(JTDI) ------> DEBUG_JTDI - PA12 ------> USB_DP - PC15-OSC32_OUT(OSC32_OUT) ------> RCC_OSC32_OUT - PC14-OSC32_IN(OSC32_IN) ------> RCC_OSC32_IN - PE5 ------> DEBUG_TRACED2 - PE2 ------> DEBUG_TRACECLK - PA11 ------> USB_DM - PA13(JTMS/SWDIO) ------> DEBUG_JTMS-SWDIO - PA8 ------> S_TIM1_CH1 - PH0-OSC_IN(PH0) ------> RCC_OSC_IN - PB15 ------> SPI2_MOSI - PA3 ------> SPI2_NSS - PH8 ------> SPI5_MOSI - PH10 ------> S_TIM5_CH1 - PH7 ------> SPI5_MISO - PH11 ------> S_TIM5_CH2 -*/ -void MX_GPIO_Init(void) -{ - - GPIO_InitTypeDef GPIO_InitStruct = {0}; - - /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOI_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - __HAL_RCC_GPIOG_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); - __HAL_RCC_GPIOE_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOH_CLK_ENABLE(); - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOF_CLK_ENABLE(); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOG, ARD_D2_Pin|ARD_D8_Pin|LCD_CTP_RST_Pin|ARD_D7_Pin - |ARD_D4_Pin|UCPD_PWR_Pin, GPIO_PIN_RESET); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_Port, LCD_BL_CTRL_Pin, GPIO_PIN_RESET); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOE, MEMS_LED_Pin|DETECTN_Pin, GPIO_PIN_RESET); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOH, LCD_RST_Pin|STMOD_11_INT_Pin|STMOD_14_PWM_Pin|STMOD_20_Pin - |STMOD_12_Pin|STMOD_19_Pin, GPIO_PIN_RESET); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOI, GREEN_LED_Pin|ORANGE_LED_Pin|AUDIO_NRST_Pin, GPIO_PIN_SET); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOF, RED_LED_Pin|BLUE_LED_Pin, GPIO_PIN_SET); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(STMOD_17_GPIO_Port, STMOD_17_Pin, GPIO_PIN_RESET); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(LCD_PWR_ON_GPIO_Port, LCD_PWR_ON_Pin, GPIO_PIN_RESET); - - /*Configure GPIO pins : PIPin PIPin PIPin PIPin */ - GPIO_InitStruct.Pin = SAI2_FS_A_Pin|SAI2_SCK_A_Pin|SAI2_MCLK_A_Pin|SAI2_SD_A_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF10_SAI2; - HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); - - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = ARD_D3_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; - HAL_GPIO_Init(ARD_D3_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pins : PGPin PGPin PGPin PGPin - PGPin PGPin */ - GPIO_InitStruct.Pin = ARD_D2_Pin|ARD_D8_Pin|LCD_CTP_RST_Pin|ARD_D7_Pin - |ARD_D4_Pin|UCPD_PWR_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = SAI2_SD_B_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF10_SAI2; - HAL_GPIO_Init(SAI2_SD_B_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pins : PIPin PIPin PIPin PIPin */ - GPIO_InitStruct.Pin = LCD_BL_CTRL_Pin|GREEN_LED_Pin|ORANGE_LED_Pin|AUDIO_NRST_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); - - /*Configure GPIO pins : PIPin PIPin */ - GPIO_InitStruct.Pin = ARD_D13_Pin|ARD_D12_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; - HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); - - /*Configure GPIO pins : PEPin PEPin */ - GPIO_InitStruct.Pin = MEMS_LED_Pin|DETECTN_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - - /*Configure GPIO pins : PBPin PBPin */ - GPIO_InitStruct.Pin = I2C1_SCL_Pin|I2C1_SDA_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /*Configure GPIO pins : PHPin PHPin PHPin PHPin - PHPin PHPin */ - GPIO_InitStruct.Pin = LCD_RST_Pin|STMOD_11_INT_Pin|STMOD_14_PWM_Pin|STMOD_20_Pin - |STMOD_12_Pin|STMOD_19_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); - - /*Configure GPIO pins : PAPin PAPin */ - GPIO_InitStruct.Pin = USB_FS_P_Pin|USB_FS_N_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF10_USB; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = uSD_DETECT_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; - GPIO_InitStruct.Pull = GPIO_PULLUP; - HAL_GPIO_Init(uSD_DETECT_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = WAKEUP_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(WAKEUP_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pins : PFPin PFPin PFPin */ - GPIO_InitStruct.Pin = RED_LED_Pin|BLUE_LED_Pin|STMOD_17_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = ARD_D9_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF1_TIM1; - HAL_GPIO_Init(ARD_D9_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = LCD_PWR_ON_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(LCD_PWR_ON_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pins : PGPin PGPin */ - GPIO_InitStruct.Pin = LCD_CTP_INT_Pin|UCPD_FLT_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = STMOD_18_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(STMOD_18_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = ARD_D11_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; - HAL_GPIO_Init(ARD_D11_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = ARD_D10_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; - HAL_GPIO_Init(ARD_D10_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pins : PHPin PHPin */ - GPIO_InitStruct.Pin = STMOD_9_MISOs_Pin|STMOD_12_RST_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF5_SPI5; - HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); - - /*Configure GPIO pins : PHPin PHPin */ - GPIO_InitStruct.Pin = ARD_D6_Pin|ARD_D5_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF2_TIM5; - HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); - - /* EXTI interrupt init*/ - HAL_NVIC_SetPriority(EXTI14_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(EXTI14_IRQn); - -} - -/* USER CODE BEGIN 2 */ - -/* USER CODE END 2 */ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.c + * @brief This file provides code for the configuration + * of all used GPIO pins. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "gpio.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure GPIO */ +/*----------------------------------------------------------------------------*/ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** Configure pins + PI7 ------> SAI2_FS_A + PI5 ------> SAI2_SCK_A + PG14 ------> DEBUG_TRACED1 + PG10 ------> SAI2_SD_B + PI1 ------> SPI2_SCK + PE3 ------> DEBUG_TRACED0 + PI4 ------> SAI2_MCLK_A + PB3(JTDO/TRACESWO) ------> DEBUG_JTDO-SWO + PA14(JTCK/SWCLK) ------> DEBUG_JTCK-SWCLK + PI2 ------> SPI2_MISO + PE6 ------> DEBUG_TRACED3 + PI6 ------> SAI2_SD_A + PB4(NJTRST) ------> DEBUG_JTRST + PA15(JTDI) ------> DEBUG_JTDI + PA12 ------> USB_DP + PC15-OSC32_OUT(OSC32_OUT) ------> RCC_OSC32_OUT + PC14-OSC32_IN(OSC32_IN) ------> RCC_OSC32_IN + PE5 ------> DEBUG_TRACED2 + PE2 ------> DEBUG_TRACECLK + PA11 ------> USB_DM + PA13(JTMS/SWDIO) ------> DEBUG_JTMS-SWDIO + PA8 ------> S_TIM1_CH1 + PH0-OSC_IN(PH0) ------> RCC_OSC_IN + PB15 ------> SPI2_MOSI + PA3 ------> SPI2_NSS + PH8 ------> SPI5_MOSI + PH10 ------> S_TIM5_CH1 + PH7 ------> SPI5_MISO + PH11 ------> S_TIM5_CH2 +*/ +void MX_GPIO_Init(void) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOI_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_Port, LCD_BL_CTRL_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOE, MEMS_LED_Pin|DETECTN_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOH, LCD_RST_Pin|STMOD_11_INT_Pin|STMOD_14_PWM_Pin|STMOD_20_Pin + |STMOD_12_Pin|STMOD_19_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOI, GREEN_LED_Pin|ORANGE_LED_Pin|AUDIO_NRST_Pin, GPIO_PIN_SET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOF, RED_LED_Pin|BLUE_LED_Pin, GPIO_PIN_SET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(STMOD_17_GPIO_Port, STMOD_17_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(LCD_PWR_ON_GPIO_Port, LCD_PWR_ON_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOG, ARD_D8_Pin|LCD_CTP_RST_Pin|ARD_D7_Pin|ARD_D4_Pin + |UCPD_PWR_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pins : PIPin PIPin PIPin PIPin */ + GPIO_InitStruct.Pin = SAI2_FS_A_Pin|SAI2_SCK_A_Pin|SAI2_MCLK_A_Pin|SAI2_SD_A_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF10_SAI2; + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + + /*Configure GPIO pin : PtPin */ + GPIO_InitStruct.Pin = DUT_DUTY_CYCLE_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(DUT_DUTY_CYCLE_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : PtPin */ + GPIO_InitStruct.Pin = WW_DET_IN_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(WW_DET_IN_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : PtPin */ + GPIO_InitStruct.Pin = SAI2_SD_B_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF10_SAI2; + HAL_GPIO_Init(SAI2_SD_B_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : PIPin PIPin PIPin PIPin */ + GPIO_InitStruct.Pin = LCD_BL_CTRL_Pin|GREEN_LED_Pin|ORANGE_LED_Pin|AUDIO_NRST_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + + /*Configure GPIO pins : PIPin PIPin */ + GPIO_InitStruct.Pin = ARD_D13_Pin|ARD_D12_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + + /*Configure GPIO pins : PEPin PEPin */ + GPIO_InitStruct.Pin = MEMS_LED_Pin|DETECTN_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + /*Configure GPIO pins : PHPin PHPin PHPin PHPin + PHPin PHPin */ + GPIO_InitStruct.Pin = LCD_RST_Pin|STMOD_11_INT_Pin|STMOD_14_PWM_Pin|STMOD_20_Pin + |STMOD_12_Pin|STMOD_19_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + /*Configure GPIO pins : PAPin PAPin */ + GPIO_InitStruct.Pin = USB_FS_P_Pin|USB_FS_N_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF10_USB; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pin : PtPin */ + GPIO_InitStruct.Pin = uSD_DETECT_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(uSD_DETECT_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : PtPin */ + GPIO_InitStruct.Pin = WAKEUP_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(WAKEUP_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : PFPin PFPin PFPin */ + GPIO_InitStruct.Pin = RED_LED_Pin|BLUE_LED_Pin|STMOD_17_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /*Configure GPIO pin : PtPin */ + GPIO_InitStruct.Pin = ARD_D9_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF1_TIM1; + HAL_GPIO_Init(ARD_D9_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : PtPin */ + GPIO_InitStruct.Pin = LCD_PWR_ON_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(LCD_PWR_ON_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : PGPin PGPin PGPin PGPin + PGPin */ + GPIO_InitStruct.Pin = ARD_D8_Pin|LCD_CTP_RST_Pin|ARD_D7_Pin|ARD_D4_Pin + |UCPD_PWR_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /*Configure GPIO pins : PGPin PGPin */ + GPIO_InitStruct.Pin = LCD_CTP_INT_Pin|UCPD_FLT_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /*Configure GPIO pin : PtPin */ + GPIO_InitStruct.Pin = STMOD_18_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(STMOD_18_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : PtPin */ + GPIO_InitStruct.Pin = ARD_D11_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(ARD_D11_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : PtPin */ + GPIO_InitStruct.Pin = ARD_D10_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(ARD_D10_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : PHPin PHPin */ + GPIO_InitStruct.Pin = STMOD_9_MISOs_Pin|STMOD_12_RST_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI5; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + /*Configure GPIO pins : PHPin PHPin */ + GPIO_InitStruct.Pin = ARD_D6_Pin|ARD_D5_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF2_TIM5; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + /* EXTI interrupt init*/ + HAL_NVIC_SetPriority(EXTI5_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(EXTI5_IRQn); + + HAL_NVIC_SetPriority(EXTI14_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(EXTI14_IRQn); + + HAL_NVIC_SetPriority(EXTI15_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(EXTI15_IRQn); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ diff --git a/benchmark/interface/Core/Src/i2c.c b/benchmark/interface/Core/Src/i2c.c new file mode 100644 index 00000000..06d95873 --- /dev/null +++ b/benchmark/interface/Core/Src/i2c.c @@ -0,0 +1,140 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file i2c.c + * @brief This file provides code for the configuration + * of the I2C instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "i2c.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +I2C_HandleTypeDef hi2c1; + +/* I2C1 init function */ +void MX_I2C1_Init(void) +{ + + /* USER CODE BEGIN I2C1_Init 0 */ + + /* USER CODE END I2C1_Init 0 */ + + /* USER CODE BEGIN I2C1_Init 1 */ + + /* USER CODE END I2C1_Init 1 */ + hi2c1.Instance = I2C1; + hi2c1.Init.Timing = 0x108088B1; + hi2c1.Init.OwnAddress1 = 0; + hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + hi2c1.Init.OwnAddress2 = 0; + hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + if (HAL_I2C_Init(&hi2c1) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Analogue filter + */ + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN I2C1_Init 2 */ + + /* USER CODE END I2C1_Init 2 */ + +} + +void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(i2cHandle->Instance==I2C1) + { + /* USER CODE BEGIN I2C1_MspInit 0 */ + + /* USER CODE END I2C1_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C1; + PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**I2C1 GPIO Configuration + PB6 ------> I2C1_SCL + PB7 ------> I2C1_SDA + */ + GPIO_InitStruct.Pin = I2C1_SCL_Pin|I2C1_SDA_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* I2C1 clock enable */ + __HAL_RCC_I2C1_CLK_ENABLE(); + /* USER CODE BEGIN I2C1_MspInit 1 */ + + /* USER CODE END I2C1_MspInit 1 */ + } +} + +void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle) +{ + + if(i2cHandle->Instance==I2C1) + { + /* USER CODE BEGIN I2C1_MspDeInit 0 */ + + /* USER CODE END I2C1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_I2C1_CLK_DISABLE(); + + /**I2C1 GPIO Configuration + PB6 ------> I2C1_SCL + PB7 ------> I2C1_SDA + */ + HAL_GPIO_DeInit(I2C1_SCL_GPIO_Port, I2C1_SCL_Pin); + + HAL_GPIO_DeInit(I2C1_SDA_GPIO_Port, I2C1_SDA_Pin); + + /* USER CODE BEGIN I2C1_MspDeInit 1 */ + + /* USER CODE END I2C1_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/benchmark/interface/Core/Src/main.c b/benchmark/interface/Core/Src/main.c index 10411434..5fd26fcd 100644 --- a/benchmark/interface/Core/Src/main.c +++ b/benchmark/interface/Core/Src/main.c @@ -1,251 +1,253 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file : main.c - * @brief : Main program body - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ -/* Includes ------------------------------------------------------------------*/ -#include "app_threadx.h" -#include "main.h" -#include "adc.h" -#include "eth.h" -#include "gpdma.h" -#include "icache.h" -#include "memorymap.h" -#include "octospi.h" -#include "sai.h" -#include "sdmmc.h" -#include "ucpd.h" -#include "usart.h" -#include "gpio.h" -#include "fmc.h" - -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ - -#include"audio.h" - -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN PTD */ - -/* USER CODE END PTD */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN PD */ - -/* USER CODE END PD */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN PM */ - -/* USER CODE END PM */ - -/* Private variables ---------------------------------------------------------*/ - -/* USER CODE BEGIN PV */ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -void SystemClock_Config(void); -/* USER CODE BEGIN PFP */ - -/* USER CODE END PFP */ - -/* Private user code ---------------------------------------------------------*/ -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/** - * @brief The application entry point. - * @retval int - */ -int main(void) -{ - /* USER CODE BEGIN 1 */ - - /* USER CODE END 1 */ - - /* MCU Configuration--------------------------------------------------------*/ - - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); - - /* USER CODE BEGIN Init */ - - /* USER CODE END Init */ - - /* Configure the system clock */ - SystemClock_Config(); - - /* USER CODE BEGIN SysInit */ - - /* USER CODE END SysInit */ - - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - MX_GPDMA1_Init(); - MX_GPDMA2_Init(); - MX_ETH_Init(); - MX_FMC_Init(); - MX_ICACHE_Init(); - MX_OCTOSPI1_Init(); - MX_SDMMC1_SD_Init(); - MX_UCPD1_Init(); - MX_USART1_UART_Init(); - MX_USART3_UART_Init(); - MX_ADC1_Init(); - MX_ADC2_Init(); - MX_SAI1_Init(); - /* USER CODE BEGIN 2 */ - - /* USER CODE END 2 */ - - MX_ThreadX_Init(); - - /* We should never get here as control is now taken by the scheduler */ - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ - while (1) - { - /* USER CODE END WHILE */ - - /* USER CODE BEGIN 3 */ - } - /* USER CODE END 3 */ -} - -/** - * @brief System Clock Configuration - * @retval None - */ -void SystemClock_Config(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - - /** Configure the main internal regulator output voltage - */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); - - while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - - /** Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE - |RCC_OSCILLATORTYPE_CSI; - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.CSIState = RCC_CSI_ON; - RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 2; - RCC_OscInitStruct.PLL.PLLN = 10; - RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_3; - RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; - RCC_OscInitStruct.PLL.PLLFRACN = 1967; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } - - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 - |RCC_CLOCKTYPE_PCLK3; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) - { - Error_Handler(); - } -} - -/* USER CODE BEGIN 4 */ -int __io_putchar(int ch) -{ - // Write character to ITM ch.0 - ITM_SendChar(ch); - return(ch); -} -/* USER CODE END 4 */ - -/** - * @brief Period elapsed callback in non blocking mode - * @note This function is called when TIM6 interrupt took place, inside - * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment - * a global variable "uwTick" used as application time base. - * @param htim : TIM handle - * @retval None - */ -void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* USER CODE BEGIN Callback 0 */ - - /* USER CODE END Callback 0 */ - if (htim->Instance == TIM6) { - HAL_IncTick(); - } - /* USER CODE BEGIN Callback 1 */ - - /* USER CODE END Callback 1 */ -} - -/** - * @brief This function is executed in case of error occurrence. - * @retval None - */ -void Error_Handler(void) -{ - /* USER CODE BEGIN Error_Handler_Debug */ - /* User can add his own implementation to report the HAL error return state */ - __disable_irq(); - while (1) - { - } - /* USER CODE END Error_Handler_Debug */ -} - -#ifdef USE_FULL_ASSERT -/** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ -void assert_failed(uint8_t *file, uint32_t line) -{ - /* USER CODE BEGIN 6 */ - /* User can add his own implementation to report the file name and line number, - ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - /* USER CODE END 6 */ -} -#endif /* USE_FULL_ASSERT */ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "app_threadx.h" +#include "main.h" +#include "adc.h" +#include "eth.h" +#include "gpdma.h" +#include "i2c.h" +#include "icache.h" +#include "memorymap.h" +#include "octospi.h" +#include "sai.h" +#include "sdmmc.h" +#include "tim.h" +#include "ucpd.h" +#include "usart.h" +#include "gpio.h" +#include "fmc.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +#include"audio.h" + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_GPDMA1_Init(); + MX_GPDMA2_Init(); + MX_ETH_Init(); + MX_FMC_Init(); + MX_ICACHE_Init(); + MX_OCTOSPI1_Init(); + MX_SDMMC1_SD_Init(); + MX_UCPD1_Init(); + MX_USART1_UART_Init(); + MX_USART3_UART_Init(); + MX_ADC1_Init(); + MX_ADC2_Init(); + MX_SAI1_Init(); + MX_I2C1_Init(); + MX_TIM2_Init(); + /* USER CODE BEGIN 2 */ + HAL_TIM_Base_Start(&htim2); // start timer + + /* USER CODE END 2 */ + + MX_ThreadX_Init(); + + /* We should never get here as control is now taken by the scheduler */ + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 2; + RCC_OscInitStruct.PLL.PLLN = 10; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_3; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 1967; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + |RCC_CLOCKTYPE_PCLK3; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) + { + Error_Handler(); + } +} + +/* USER CODE BEGIN 4 */ +int __io_putchar(int ch) +{ + // Write character to ITM ch.0 + ITM_SendChar(ch); + return(ch); +} +/* USER CODE END 4 */ + +/** + * @brief Period elapsed callback in non blocking mode + * @note This function is called when TIM6 interrupt took place, inside + * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment + * a global variable "uwTick" used as application time base. + * @param htim : TIM handle + * @retval None + */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* USER CODE BEGIN Callback 0 */ + + /* USER CODE END Callback 0 */ + if (htim->Instance == TIM6) { + HAL_IncTick(); + } + /* USER CODE BEGIN Callback 1 */ + + /* USER CODE END Callback 1 */ +} + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/benchmark/interface/Core/Src/sai.c b/benchmark/interface/Core/Src/sai.c index 96e78890..a338ad41 100644 --- a/benchmark/interface/Core/Src/sai.c +++ b/benchmark/interface/Core/Src/sai.c @@ -1,212 +1,212 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * File Name : SAI.c - * Description : This file provides code for the configuration - * of the SAI instances. - ****************************************************************************** - * @attention - * - * Copyright (c) 2024 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "sai.h" - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -SAI_HandleTypeDef hsai_BlockB1; - -/* SAI1 init function */ -void MX_SAI1_Init(void) -{ - - /* USER CODE BEGIN SAI1_Init 0 */ - - /* USER CODE END SAI1_Init 0 */ - - /* USER CODE BEGIN SAI1_Init 1 */ - - /* USER CODE END SAI1_Init 1 */ - - hsai_BlockB1.Instance = SAI1_Block_B; - hsai_BlockB1.Init.AudioMode = SAI_MODEMASTER_TX; - hsai_BlockB1.Init.Synchro = SAI_ASYNCHRONOUS; - hsai_BlockB1.Init.OutputDrive = SAI_OUTPUTDRIVE_DISABLE; - hsai_BlockB1.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE; - hsai_BlockB1.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_EMPTY; - hsai_BlockB1.Init.AudioFrequency = SAI_AUDIO_FREQUENCY_192K; - hsai_BlockB1.Init.SynchroExt = SAI_SYNCEXT_DISABLE; - hsai_BlockB1.Init.MckOutput = SAI_MCK_OUTPUT_ENABLE; - hsai_BlockB1.Init.MonoStereoMode = SAI_STEREOMODE; - hsai_BlockB1.Init.CompandingMode = SAI_NOCOMPANDING; - hsai_BlockB1.Init.TriState = SAI_OUTPUT_NOTRELEASED; - if (HAL_SAI_InitProtocol(&hsai_BlockB1, SAI_I2S_STANDARD, SAI_PROTOCOL_DATASIZE_16BIT, 2) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN SAI1_Init 2 */ - - /* USER CODE END SAI1_Init 2 */ - -} -static uint32_t SAI1_client =0; - -void HAL_SAI_MspInit(SAI_HandleTypeDef* saiHandle) -{ - - GPIO_InitTypeDef GPIO_InitStruct; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; -/* SAI1 */ - if(saiHandle->Instance==SAI1_Block_A) - { - /* SAI1 clock enable */ - if (SAI1_client == 0) - { - __HAL_RCC_SAI1_CLK_ENABLE(); - } - SAI1_client ++; - - /**SAI1_A_Block_A GPIO Configuration - PD6 ------> SAI1_SD_A - PE4 ------> SAI1_D2 - PD11 ------> SAI1_CK1 - PC3 ------> SAI1_D3 - */ - GPIO_InitStruct.Pin = GPIO_PIN_6; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF6_SAI1; - HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_4; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF2_SAI1; - HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_11; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF2_SAI1; - HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = PDM_SAI1_SD3_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF2_SAI1; - HAL_GPIO_Init(PDM_SAI1_SD3_GPIO_Port, &GPIO_InitStruct); - - } - if(saiHandle->Instance==SAI1_Block_B) - { - /* SAI1 clock enable */ - - /** Initializes the peripherals clock - */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SAI1; - PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI; - PeriphClkInitStruct.PLL2.PLL2M = 1; - PeriphClkInitStruct.PLL2.PLL2N = 32; - PeriphClkInitStruct.PLL2.PLL2P = 2; - PeriphClkInitStruct.PLL2.PLL2Q = 2; - PeriphClkInitStruct.PLL2.PLL2R = 2; - PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; - PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; - PeriphClkInitStruct.PLL2.PLL2FRACN = 0; - PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVP; - PeriphClkInitStruct.Sai1ClockSelection = RCC_SAI1CLKSOURCE_PLL2P; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - { - Error_Handler(); - } - - if (SAI1_client == 0) - { - __HAL_RCC_SAI1_CLK_ENABLE(); - } - SAI1_client ++; - - /**SAI1_B_Block_B GPIO Configuration - PF6 ------> SAI1_SD_B - PF8 ------> SAI1_SCK_B - PF9 ------> SAI1_FS_B - PF7 ------> SAI1_MCLK_B - */ - GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_7; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF6_SAI1; - HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - - } -} - -void HAL_SAI_MspDeInit(SAI_HandleTypeDef* saiHandle) -{ - -/* SAI1 */ - if(saiHandle->Instance==SAI1_Block_A) - { - SAI1_client --; - if (SAI1_client == 0) - { - /* Peripheral clock disable */ - __HAL_RCC_SAI1_CLK_DISABLE(); - } - - /**SAI1_A_Block_A GPIO Configuration - PD6 ------> SAI1_SD_A - PE4 ------> SAI1_D2 - PD11 ------> SAI1_CK1 - PC3 ------> SAI1_D3 - */ - HAL_GPIO_DeInit(GPIOD, GPIO_PIN_6|GPIO_PIN_11); - - HAL_GPIO_DeInit(GPIOE, GPIO_PIN_4); - - HAL_GPIO_DeInit(PDM_SAI1_SD3_GPIO_Port, PDM_SAI1_SD3_Pin); - - } - if(saiHandle->Instance==SAI1_Block_B) - { - SAI1_client --; - if (SAI1_client == 0) - { - /* Peripheral clock disable */ - __HAL_RCC_SAI1_CLK_DISABLE(); - } - - /**SAI1_B_Block_B GPIO Configuration - PF6 ------> SAI1_SD_B - PF8 ------> SAI1_SCK_B - PF9 ------> SAI1_FS_B - PF7 ------> SAI1_MCLK_B - */ - HAL_GPIO_DeInit(GPIOF, GPIO_PIN_6|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_7); - - } -} - -/** - * @} - */ - -/** - * @} - */ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : SAI.c + * Description : This file provides code for the configuration + * of the SAI instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "sai.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +SAI_HandleTypeDef hsai_BlockB1; + +/* SAI1 init function */ +void MX_SAI1_Init(void) +{ + + /* USER CODE BEGIN SAI1_Init 0 */ + + /* USER CODE END SAI1_Init 0 */ + + /* USER CODE BEGIN SAI1_Init 1 */ + + /* USER CODE END SAI1_Init 1 */ + + hsai_BlockB1.Instance = SAI1_Block_B; + hsai_BlockB1.Init.AudioMode = SAI_MODEMASTER_TX; + hsai_BlockB1.Init.Synchro = SAI_ASYNCHRONOUS; + hsai_BlockB1.Init.OutputDrive = SAI_OUTPUTDRIVE_DISABLE; + hsai_BlockB1.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE; + hsai_BlockB1.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_EMPTY; + hsai_BlockB1.Init.AudioFrequency = SAI_AUDIO_FREQUENCY_16K; + hsai_BlockB1.Init.SynchroExt = SAI_SYNCEXT_DISABLE; + hsai_BlockB1.Init.MckOutput = SAI_MCK_OUTPUT_ENABLE; + hsai_BlockB1.Init.MonoStereoMode = SAI_STEREOMODE; + hsai_BlockB1.Init.CompandingMode = SAI_NOCOMPANDING; + hsai_BlockB1.Init.TriState = SAI_OUTPUT_NOTRELEASED; + if (HAL_SAI_InitProtocol(&hsai_BlockB1, SAI_I2S_STANDARD, SAI_PROTOCOL_DATASIZE_16BIT, 2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SAI1_Init 2 */ + + /* USER CODE END SAI1_Init 2 */ + +} +static uint32_t SAI1_client =0; + +void HAL_SAI_MspInit(SAI_HandleTypeDef* saiHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; +/* SAI1 */ + if(saiHandle->Instance==SAI1_Block_A) + { + /* SAI1 clock enable */ + if (SAI1_client == 0) + { + __HAL_RCC_SAI1_CLK_ENABLE(); + } + SAI1_client ++; + + /**SAI1_A_Block_A GPIO Configuration + PD6 ------> SAI1_SD_A + PE4 ------> SAI1_D2 + PD11 ------> SAI1_CK1 + PC3 ------> SAI1_D3 + */ + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF6_SAI1; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF2_SAI1; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF2_SAI1; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = PDM_SAI1_SD3_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF2_SAI1; + HAL_GPIO_Init(PDM_SAI1_SD3_GPIO_Port, &GPIO_InitStruct); + + } + if(saiHandle->Instance==SAI1_Block_B) + { + /* SAI1 clock enable */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SAI1; + PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSI; + PeriphClkInitStruct.PLL2.PLL2M = 25; + PeriphClkInitStruct.PLL2.PLL2N = 96; + PeriphClkInitStruct.PLL2.PLL2P = 5; + PeriphClkInitStruct.PLL2.PLL2Q = 2; + PeriphClkInitStruct.PLL2.PLL2R = 2; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_1; + PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; + PeriphClkInitStruct.PLL2.PLL2FRACN = 0; + PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVP; + PeriphClkInitStruct.Sai1ClockSelection = RCC_SAI1CLKSOURCE_PLL2P; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + if (SAI1_client == 0) + { + __HAL_RCC_SAI1_CLK_ENABLE(); + } + SAI1_client ++; + + /**SAI1_B_Block_B GPIO Configuration + PF6 ------> SAI1_SD_B + PF8 ------> SAI1_SCK_B + PF9 ------> SAI1_FS_B + PF7 ------> SAI1_MCLK_B + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF6_SAI1; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + } +} + +void HAL_SAI_MspDeInit(SAI_HandleTypeDef* saiHandle) +{ + +/* SAI1 */ + if(saiHandle->Instance==SAI1_Block_A) + { + SAI1_client --; + if (SAI1_client == 0) + { + /* Peripheral clock disable */ + __HAL_RCC_SAI1_CLK_DISABLE(); + } + + /**SAI1_A_Block_A GPIO Configuration + PD6 ------> SAI1_SD_A + PE4 ------> SAI1_D2 + PD11 ------> SAI1_CK1 + PC3 ------> SAI1_D3 + */ + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_6|GPIO_PIN_11); + + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_4); + + HAL_GPIO_DeInit(PDM_SAI1_SD3_GPIO_Port, PDM_SAI1_SD3_Pin); + + } + if(saiHandle->Instance==SAI1_Block_B) + { + SAI1_client --; + if (SAI1_client == 0) + { + /* Peripheral clock disable */ + __HAL_RCC_SAI1_CLK_DISABLE(); + } + + /**SAI1_B_Block_B GPIO Configuration + PF6 ------> SAI1_SD_B + PF8 ------> SAI1_SCK_B + PF9 ------> SAI1_FS_B + PF7 ------> SAI1_MCLK_B + */ + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_6|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_7); + + } +} + +/** + * @} + */ + +/** + * @} + */ diff --git a/benchmark/interface/Core/Src/sdmmc.c b/benchmark/interface/Core/Src/sdmmc.c index 187e2a99..a70b06b0 100644 --- a/benchmark/interface/Core/Src/sdmmc.c +++ b/benchmark/interface/Core/Src/sdmmc.c @@ -23,9 +23,9 @@ /* USER CODE BEGIN 0 */ #include "tx_api.h" -#define SD_DETECT_Pin GPIO_PIN_14 -#define SD_DETECT_GPIO_Port GPIOH -#define SD_DETECT_EXTI_IRQn EXTI14_IRQn +//#define SD_DETECT_Pin GPIO_PIN_14 +//#define SD_DETECT_GPIO_Port GPIOH +//#define SD_DETECT_EXTI_IRQn EXTI14_IRQn TX_SEMAPHORE card_in_semaphore; TX_SEMAPHORE card_out_semaphore; @@ -169,32 +169,12 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* sdHandle) /* USER CODE BEGIN 1 */ -/** - * @brief EXTI line detection callback. - * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. - * @retval None - */ -void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin) -{ - if(GPIO_Pin == SD_DETECT_Pin) - { - tx_semaphore_ceiling_put(&card_in_semaphore, 1); - } -} - -void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin) -{ - if(GPIO_Pin == SD_DETECT_Pin) - { - tx_semaphore_ceiling_put(&card_out_semaphore, 1); - } -} int32_t SD_IsDetected() { int32_t ret; /* Check SD card detect pin */ - if (HAL_GPIO_ReadPin(SD_DETECT_GPIO_Port, SD_DETECT_Pin) == GPIO_PIN_SET) + if (HAL_GPIO_ReadPin(uSD_DETECT_GPIO_Port, uSD_DETECT_Pin) == GPIO_PIN_SET) { ret = SD_NOT_PRESENT; } diff --git a/benchmark/interface/Core/Src/stm32h5xx_it.c b/benchmark/interface/Core/Src/stm32h5xx_it.c index fa71ba93..9b68ffbb 100644 --- a/benchmark/interface/Core/Src/stm32h5xx_it.c +++ b/benchmark/interface/Core/Src/stm32h5xx_it.c @@ -1,267 +1,295 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file stm32h5xx_it.c - * @brief Interrupt Service Routines. - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" -#include "stm32h5xx_it.h" -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN TD */ - -/* USER CODE END TD */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN PD */ - -/* USER CODE END PD */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN PM */ - -/* USER CODE END PM */ - -/* Private variables ---------------------------------------------------------*/ -/* USER CODE BEGIN PV */ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -/* USER CODE BEGIN PFP */ - -/* USER CODE END PFP */ - -/* Private user code ---------------------------------------------------------*/ -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/* External variables --------------------------------------------------------*/ -extern SAI_HandleTypeDef haudio_out_sai; -extern DMA_HandleTypeDef handle_GPDMA2_Channel2; -extern SD_HandleTypeDef hsd1; -extern UART_HandleTypeDef huart1; -extern UART_HandleTypeDef huart3; -extern TIM_HandleTypeDef htim6; - -/* USER CODE BEGIN EV */ - -/* USER CODE END EV */ - -/******************************************************************************/ -/* Cortex Processor Interruption and Exception Handlers */ -/******************************************************************************/ -/** - * @brief This function handles Non maskable interrupt. - */ -void NMI_Handler(void) -{ - /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ - - /* USER CODE END NonMaskableInt_IRQn 0 */ - /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ - while (1) - { - } - /* USER CODE END NonMaskableInt_IRQn 1 */ -} - -/** - * @brief This function handles Hard fault interrupt. - */ -void HardFault_Handler(void) -{ - /* USER CODE BEGIN HardFault_IRQn 0 */ - - /* USER CODE END HardFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_HardFault_IRQn 0 */ - /* USER CODE END W1_HardFault_IRQn 0 */ - } -} - -/** - * @brief This function handles Memory management fault. - */ -void MemManage_Handler(void) -{ - /* USER CODE BEGIN MemoryManagement_IRQn 0 */ - - /* USER CODE END MemoryManagement_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ - /* USER CODE END W1_MemoryManagement_IRQn 0 */ - } -} - -/** - * @brief This function handles Prefetch fault, memory access fault. - */ -void BusFault_Handler(void) -{ - /* USER CODE BEGIN BusFault_IRQn 0 */ - - /* USER CODE END BusFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_BusFault_IRQn 0 */ - /* USER CODE END W1_BusFault_IRQn 0 */ - } -} - -/** - * @brief This function handles Undefined instruction or illegal state. - */ -void UsageFault_Handler(void) -{ - /* USER CODE BEGIN UsageFault_IRQn 0 */ - - /* USER CODE END UsageFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ - /* USER CODE END W1_UsageFault_IRQn 0 */ - } -} - -/** - * @brief This function handles Debug monitor. - */ -void DebugMon_Handler(void) -{ - /* USER CODE BEGIN DebugMonitor_IRQn 0 */ - - /* USER CODE END DebugMonitor_IRQn 0 */ - /* USER CODE BEGIN DebugMonitor_IRQn 1 */ - - /* USER CODE END DebugMonitor_IRQn 1 */ -} - -/******************************************************************************/ -/* STM32H5xx Peripheral Interrupt Handlers */ -/* Add here the Interrupt Handlers for the used peripherals. */ -/* For the available peripheral interrupt handler names, */ -/* please refer to the startup file (startup_stm32h5xx.s). */ -/******************************************************************************/ - -/** - * @brief This function handles EXTI Line14 interrupt. - */ -void EXTI14_IRQHandler(void) -{ - /* USER CODE BEGIN EXTI14_IRQn 0 */ - - /* USER CODE END EXTI14_IRQn 0 */ - HAL_GPIO_EXTI_IRQHandler(uSD_DETECT_Pin); - /* USER CODE BEGIN EXTI14_IRQn 1 */ - - /* USER CODE END EXTI14_IRQn 1 */ -} - -/** - * @brief This function handles GPDMA1 Channel 2 global interrupt. - */ -void GPDMA1_Channel2_IRQHandler(void) -{ - /* USER CODE BEGIN GPDMA1_Channel2_IRQn 0 */ - - /* USER CODE END GPDMA1_Channel2_IRQn 0 */ - HAL_DMA_IRQHandler(haudio_out_sai.hdmatx); - /* USER CODE BEGIN GPDMA1_Channel2_IRQn 1 */ - - /* USER CODE END GPDMA1_Channel2_IRQn 1 */ -} - -/** - * @brief This function handles TIM6 global interrupt. - */ -void TIM6_IRQHandler(void) -{ - /* USER CODE BEGIN TIM6_IRQn 0 */ - - /* USER CODE END TIM6_IRQn 0 */ - HAL_TIM_IRQHandler(&htim6); - /* USER CODE BEGIN TIM6_IRQn 1 */ - - /* USER CODE END TIM6_IRQn 1 */ -} - -/** - * @brief This function handles USART1 global interrupt. - */ -void USART1_IRQHandler(void) -{ - /* USER CODE BEGIN USART1_IRQn 0 */ - - /* USER CODE END USART1_IRQn 0 */ - HAL_UART_IRQHandler(&huart1); - /* USER CODE BEGIN USART1_IRQn 1 */ - - /* USER CODE END USART1_IRQn 1 */ -} - -/** - * @brief This function handles USART3 global interrupt. - */ -void USART3_IRQHandler(void) -{ - /* USER CODE BEGIN USART3_IRQn 0 */ - - /* USER CODE END USART3_IRQn 0 */ - HAL_UART_IRQHandler(&huart3); - /* USER CODE BEGIN USART3_IRQn 1 */ - - /* USER CODE END USART3_IRQn 1 */ -} - -/** - * @brief This function handles SDMMC1 global interrupt. - */ -void SDMMC1_IRQHandler(void) -{ - /* USER CODE BEGIN SDMMC1_IRQn 0 */ - - /* USER CODE END SDMMC1_IRQn 0 */ - HAL_SD_IRQHandler(&hsd1); - /* USER CODE BEGIN SDMMC1_IRQn 1 */ - - /* USER CODE END SDMMC1_IRQn 1 */ -} - -/** - * @brief This function handles GPDMA2 Channel 2 global interrupt. - */ -void GPDMA2_Channel2_IRQHandler(void) -{ - /* USER CODE BEGIN GPDMA2_Channel2_IRQn 0 */ - - /* USER CODE END GPDMA2_Channel2_IRQn 0 */ - HAL_DMA_IRQHandler(&handle_GPDMA2_Channel2); - /* USER CODE BEGIN GPDMA2_Channel2_IRQn 1 */ - - /* USER CODE END GPDMA2_Channel2_IRQn 1 */ -} - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h5xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32h5xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern DMA_HandleTypeDef handle_GPDMA1_Channel2; +extern DMA_HandleTypeDef handle_GPDMA2_Channel2; +extern SD_HandleTypeDef hsd1; +extern UART_HandleTypeDef huart1; +extern UART_HandleTypeDef huart3; +extern TIM_HandleTypeDef htim6; + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32H5xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32h5xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles EXTI Line5 interrupt. + */ +void EXTI5_IRQHandler(void) +{ + /* USER CODE BEGIN EXTI5_IRQn 0 */ + + /* USER CODE END EXTI5_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(DUT_DUTY_CYCLE_Pin); + /* USER CODE BEGIN EXTI5_IRQn 1 */ + + /* USER CODE END EXTI5_IRQn 1 */ +} + +/** + * @brief This function handles EXTI Line14 interrupt. + */ +void EXTI14_IRQHandler(void) +{ + /* USER CODE BEGIN EXTI14_IRQn 0 */ + + /* USER CODE END EXTI14_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(uSD_DETECT_Pin); + /* USER CODE BEGIN EXTI14_IRQn 1 */ + + /* USER CODE END EXTI14_IRQn 1 */ +} + +/** + * @brief This function handles EXTI Line15 interrupt. + */ +void EXTI15_IRQHandler(void) +{ + /* USER CODE BEGIN EXTI15_IRQn 0 */ + + /* USER CODE END EXTI15_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(WW_DET_IN_Pin); + /* USER CODE BEGIN EXTI15_IRQn 1 */ + + /* USER CODE END EXTI15_IRQn 1 */ +} + +/** + * @brief This function handles GPDMA1 Channel 2 global interrupt. + */ +void GPDMA1_Channel2_IRQHandler(void) +{ + /* USER CODE BEGIN GPDMA1_Channel2_IRQn 0 */ + + /* USER CODE END GPDMA1_Channel2_IRQn 0 */ + HAL_DMA_IRQHandler(&handle_GPDMA1_Channel2); + /* USER CODE BEGIN GPDMA1_Channel2_IRQn 1 */ + + /* USER CODE END GPDMA1_Channel2_IRQn 1 */ +} + +/** + * @brief This function handles TIM6 global interrupt. + */ +void TIM6_IRQHandler(void) +{ + /* USER CODE BEGIN TIM6_IRQn 0 */ + + /* USER CODE END TIM6_IRQn 0 */ + HAL_TIM_IRQHandler(&htim6); + /* USER CODE BEGIN TIM6_IRQn 1 */ + + /* USER CODE END TIM6_IRQn 1 */ +} + +/** + * @brief This function handles USART1 global interrupt. + */ +void USART1_IRQHandler(void) +{ + /* USER CODE BEGIN USART1_IRQn 0 */ + + /* USER CODE END USART1_IRQn 0 */ + HAL_UART_IRQHandler(&huart1); + /* USER CODE BEGIN USART1_IRQn 1 */ + + /* USER CODE END USART1_IRQn 1 */ +} + +/** + * @brief This function handles USART3 global interrupt. + */ +void USART3_IRQHandler(void) +{ + /* USER CODE BEGIN USART3_IRQn 0 */ + + /* USER CODE END USART3_IRQn 0 */ + HAL_UART_IRQHandler(&huart3); + /* USER CODE BEGIN USART3_IRQn 1 */ + + /* USER CODE END USART3_IRQn 1 */ +} + +/** + * @brief This function handles SDMMC1 global interrupt. + */ +void SDMMC1_IRQHandler(void) +{ + /* USER CODE BEGIN SDMMC1_IRQn 0 */ + + /* USER CODE END SDMMC1_IRQn 0 */ + HAL_SD_IRQHandler(&hsd1); + /* USER CODE BEGIN SDMMC1_IRQn 1 */ + + /* USER CODE END SDMMC1_IRQn 1 */ +} + +/** + * @brief This function handles GPDMA2 Channel 2 global interrupt. + */ +void GPDMA2_Channel2_IRQHandler(void) +{ + /* USER CODE BEGIN GPDMA2_Channel2_IRQn 0 */ + + /* USER CODE END GPDMA2_Channel2_IRQn 0 */ + HAL_DMA_IRQHandler(&handle_GPDMA2_Channel2); + /* USER CODE BEGIN GPDMA2_Channel2_IRQn 1 */ + + /* USER CODE END GPDMA2_Channel2_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/benchmark/interface/Core/Src/tim.c b/benchmark/interface/Core/Src/tim.c new file mode 100644 index 00000000..5533aa8d --- /dev/null +++ b/benchmark/interface/Core/Src/tim.c @@ -0,0 +1,104 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file tim.c + * @brief This file provides code for the configuration + * of the TIM instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "tim.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +TIM_HandleTypeDef htim2; + +/* TIM2 init function */ +void MX_TIM2_Init(void) +{ + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + htim2.Init.Prescaler = 640-1; + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + htim2.Init.Period = 4294967295; + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim2) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + +} + +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) +{ + + if(tim_baseHandle->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* TIM2 clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + /* USER CODE BEGIN TIM2_MspInit 1 */ + + /* USER CODE END TIM2_MspInit 1 */ + } +} + +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle) +{ + + if(tim_baseHandle->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspDeInit 0 */ + + /* USER CODE END TIM2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM2_CLK_DISABLE(); + /* USER CODE BEGIN TIM2_MspDeInit 1 */ + + /* USER CODE END TIM2_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/benchmark/interface/Core/Src/usart.c b/benchmark/interface/Core/Src/usart.c index aa1e4aec..da52faa2 100644 --- a/benchmark/interface/Core/Src/usart.c +++ b/benchmark/interface/Core/Src/usart.c @@ -1,254 +1,254 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file usart.c - * @brief This file provides code for the configuration - * of the USART instances. - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ -/* Includes ------------------------------------------------------------------*/ -#include "usart.h" - -/* USER CODE BEGIN 0 */ - -#include - -/* USER CODE END 0 */ - -UART_HandleTypeDef huart1; -UART_HandleTypeDef huart3; - -/* USART1 init function */ - -void MX_USART1_UART_Init(void) -{ - - /* USER CODE BEGIN USART1_Init 0 */ - - /* USER CODE END USART1_Init 0 */ - - /* USER CODE BEGIN USART1_Init 1 */ - - /* USER CODE END USART1_Init 1 */ - huart1.Instance = USART1; - huart1.Init.BaudRate = 115200; // 921600; - huart1.Init.WordLength = UART_WORDLENGTH_8B; - huart1.Init.StopBits = UART_STOPBITS_1; - huart1.Init.Parity = UART_PARITY_NONE; - huart1.Init.Mode = UART_MODE_TX_RX; - huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; - huart1.Init.OverSampling = UART_OVERSAMPLING_16; - huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; - huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&huart1) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_EnableFifoMode(&huart1) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN USART1_Init 2 */ - - /* USER CODE END USART1_Init 2 */ - -} -/* USART3 init function */ - -void MX_USART3_UART_Init(void) -{ - - /* USER CODE BEGIN USART3_Init 0 */ - - /* USER CODE END USART3_Init 0 */ - - /* USER CODE BEGIN USART3_Init 1 */ - - /* USER CODE END USART3_Init 1 */ - huart3.Instance = USART3; - huart3.Init.BaudRate = 115200; // 9600; - huart3.Init.WordLength = UART_WORDLENGTH_8B; - huart3.Init.StopBits = UART_STOPBITS_1; - huart3.Init.Parity = UART_PARITY_NONE; - huart3.Init.Mode = UART_MODE_TX_RX; - huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; - huart3.Init.OverSampling = UART_OVERSAMPLING_16; - huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - huart3.Init.ClockPrescaler = UART_PRESCALER_DIV1; - huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&huart3) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_SetTxFifoThreshold(&huart3, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_SetRxFifoThreshold(&huart3, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_EnableFifoMode(&huart3) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN USART3_Init 2 */ - - /* USER CODE END USART3_Init 2 */ - -} - -void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) -{ - - GPIO_InitTypeDef GPIO_InitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - if(uartHandle->Instance==USART1) - { - /* USER CODE BEGIN USART1_MspInit 0 */ - - /* USER CODE END USART1_MspInit 0 */ - - /** Initializes the peripherals clock - */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; - PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - { - Error_Handler(); - } - - /* USART1 clock enable */ - __HAL_RCC_USART1_CLK_ENABLE(); - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration - PA10 ------> USART1_RX - PA9 ------> USART1_TX - */ - GPIO_InitStruct.Pin = STLK_VCP_TX_Pin|STLK_VCP_RX_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF7_USART1; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* USART1 interrupt Init */ - HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(USART1_IRQn); - /* USER CODE BEGIN USART1_MspInit 1 */ - - /* USER CODE END USART1_MspInit 1 */ - } - else if(uartHandle->Instance==USART3) - { - /* USER CODE BEGIN USART3_MspInit 0 */ - - /* USER CODE END USART3_MspInit 0 */ - - /** Initializes the peripherals clock - */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3; - PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - { - Error_Handler(); - } - - /* USART3 clock enable */ - __HAL_RCC_USART3_CLK_ENABLE(); - - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**USART3 GPIO Configuration - PB10 ------> USART3_TX - PB11 ------> USART3_RX - */ - GPIO_InitStruct.Pin = ARD_D1_Pin|ARD_D0_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF7_USART3; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /* USART3 interrupt Init */ - HAL_NVIC_SetPriority(USART3_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(USART3_IRQn); - /* USER CODE BEGIN USART3_MspInit 1 */ - - /* USER CODE END USART3_MspInit 1 */ - } -} - -void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) -{ - - if(uartHandle->Instance==USART1) - { - /* USER CODE BEGIN USART1_MspDeInit 0 */ - - /* USER CODE END USART1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration - PA10 ------> USART1_RX - PA9 ------> USART1_TX - */ - HAL_GPIO_DeInit(GPIOA, STLK_VCP_TX_Pin|STLK_VCP_RX_Pin); - - /* USART1 interrupt Deinit */ - HAL_NVIC_DisableIRQ(USART1_IRQn); - /* USER CODE BEGIN USART1_MspDeInit 1 */ - - /* USER CODE END USART1_MspDeInit 1 */ - } - else if(uartHandle->Instance==USART3) - { - /* USER CODE BEGIN USART3_MspDeInit 0 */ - - /* USER CODE END USART3_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration - PB10 ------> USART3_TX - PB11 ------> USART3_RX - */ - HAL_GPIO_DeInit(GPIOB, ARD_D1_Pin|ARD_D0_Pin); - - /* USART3 interrupt Deinit */ - HAL_NVIC_DisableIRQ(USART3_IRQn); - /* USER CODE BEGIN USART3_MspDeInit 1 */ - - /* USER CODE END USART3_MspDeInit 1 */ - } -} - -/* USER CODE BEGIN 1 */ - -void UART_SendString(UART_HandleTypeDef* huart, const char *string) -{ - HAL_UART_Transmit(huart, (uint8_t *)string, strlen(string), HAL_MAX_DELAY); -} - -/* USER CODE END 1 */ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart.c + * @brief This file provides code for the configuration + * of the USART instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "usart.h" + +/* USER CODE BEGIN 0 */ +#include "baud_config.h" +#include + +/* USER CODE END 0 */ + +UART_HandleTypeDef huart1; +UART_HandleTypeDef huart3; + +/* USART1 init function */ + +void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; + huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_EnableFifoMode(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} +/* USART3 init function */ + +void MX_USART3_UART_Init(void) +{ + + /* USER CODE BEGIN USART3_Init 0 */ + + /* USER CODE END USART3_Init 0 */ + + /* USER CODE BEGIN USART3_Init 1 */ + + /* USER CODE END USART3_Init 1 */ + huart3.Instance = USART3; + huart3.Init.BaudRate = LoadBaudRateFromFlash();; + huart3.Init.WordLength = UART_WORDLENGTH_8B; + huart3.Init.StopBits = UART_STOPBITS_1; + huart3.Init.Parity = UART_PARITY_NONE; + huart3.Init.Mode = UART_MODE_TX_RX; + huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart3.Init.OverSampling = UART_OVERSAMPLING_16; + huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart3.Init.ClockPrescaler = UART_PRESCALER_DIV1; + huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart3) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart3, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart3, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_EnableFifoMode(&huart3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART3_Init 2 */ + + /* USER CODE END USART3_Init 2 */ + +} + +void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; + PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* USART1 clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART1 GPIO Configuration + PA10 ------> USART1_RX + PA9 ------> USART1_TX + */ + GPIO_InitStruct.Pin = STLK_VCP_TX_Pin|STLK_VCP_RX_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USART1 interrupt Init */ + HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(USART1_IRQn); + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + else if(uartHandle->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspInit 0 */ + + /* USER CODE END USART3_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3; + PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* USART3 clock enable */ + __HAL_RCC_USART3_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**USART3 GPIO Configuration + PB10 ------> USART3_TX + PB11 ------> USART3_RX + */ + GPIO_InitStruct.Pin = ARD_D1_Pin|ARD_D0_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF7_USART3; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USART3 interrupt Init */ + HAL_NVIC_SetPriority(USART3_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(USART3_IRQn); + /* USER CODE BEGIN USART3_MspInit 1 */ + + /* USER CODE END USART3_MspInit 1 */ + } +} + +void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) +{ + + if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PA10 ------> USART1_RX + PA9 ------> USART1_TX + */ + HAL_GPIO_DeInit(GPIOA, STLK_VCP_TX_Pin|STLK_VCP_RX_Pin); + + /* USART1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(USART1_IRQn); + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + else if(uartHandle->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspDeInit 0 */ + + /* USER CODE END USART3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART3_CLK_DISABLE(); + + /**USART3 GPIO Configuration + PB10 ------> USART3_TX + PB11 ------> USART3_RX + */ + HAL_GPIO_DeInit(GPIOB, ARD_D1_Pin|ARD_D0_Pin); + + /* USART3 interrupt Deinit */ + HAL_NVIC_DisableIRQ(USART3_IRQn); + /* USER CODE BEGIN USART3_MspDeInit 1 */ + + /* USER CODE END USART3_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +void UART_SendString(UART_HandleTypeDef* huart, const char *string) +{ + HAL_UART_Transmit(huart, (uint8_t *)string, strlen(string), HAL_MAX_DELAY); +} + +/* USER CODE END 1 */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/cachel1_armv7.h b/benchmark/interface/Drivers/CMSIS/Core/Include/cachel1_armv7.h new file mode 100644 index 00000000..abebc95f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/cachel1_armv7.h @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.1 + * @date 19. April 2021 + ******************************************************************************/ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/cmsis_armcc.h b/benchmark/interface/Drivers/CMSIS/Core/Include/cmsis_armcc.h new file mode 100644 index 00000000..a955d471 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/cmsis_armcc.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/cmsis_armclang.h b/benchmark/interface/Drivers/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 00000000..69114177 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/cmsis_armclang_ltm.h b/benchmark/interface/Drivers/CMSIS/Core/Include/cmsis_armclang_ltm.h new file mode 100644 index 00000000..1e255d59 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/cmsis_compiler.h b/benchmark/interface/Drivers/CMSIS/Core/Include/cmsis_compiler.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/cmsis_compiler.h rename to benchmark/interface/Drivers/CMSIS/Core/Include/cmsis_compiler.h index 21a2c711..adbf296f 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/cmsis_compiler.h +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/cmsis_compiler.h @@ -1,283 +1,283 @@ -/**************************************************************************//** - * @file cmsis_compiler.h - * @brief CMSIS compiler generic header file - * @version V5.1.0 - * @date 09. October 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_COMPILER_H -#define __CMSIS_COMPILER_H - -#include - -/* - * Arm Compiler 4/5 - */ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - - -/* - * Arm Compiler 6.6 LTM (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) - #include "cmsis_armclang_ltm.h" - - /* - * Arm Compiler above 6.10.1 (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) - #include "cmsis_armclang.h" - - -/* - * GNU Compiler - */ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - - -/* - * IAR Compiler - */ -#elif defined ( __ICCARM__ ) - #include - - -/* - * TI Arm Compiler - */ -#elif defined ( __TI_ARM__ ) - #include - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __attribute__((packed)) - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed)) - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed)) - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) - #endif - #ifndef __RESTRICT - #define __RESTRICT __restrict - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -/* - * TASKING Compiler - */ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __packed__ - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __packed__ - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __packed__ - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __packed__ T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __align(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -/* - * COSMIC Compiler - */ -#elif defined ( __CSMC__ ) - #include - - #ifndef __ASM - #define __ASM _asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - // NO RETURN is automatically detected hence no warning here - #define __NO_RETURN - #endif - #ifndef __USED - #warning No compiler specific solution for __USED. __USED is ignored. - #define __USED - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __PACKED - #define __PACKED @packed - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT @packed struct - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION @packed union - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - @packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -#else - #error Unknown compiler. -#endif - - -#endif /* __CMSIS_COMPILER_H */ - +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/cmsis_gcc.h b/benchmark/interface/Drivers/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 00000000..67bda4ef --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/cmsis_iccarm.h b/benchmark/interface/Drivers/CMSIS/Core/Include/cmsis_iccarm.h new file mode 100644 index 00000000..65b824b0 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/cmsis_version.h b/benchmark/interface/Drivers/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 00000000..8b4765f1 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/core_armv81mml.h b/benchmark/interface/Drivers/CMSIS/Core/Include/core_armv81mml.h new file mode 100644 index 00000000..94128a1a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/core_armv81mml.h @@ -0,0 +1,4228 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.4.2 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/core_armv8mbl.h b/benchmark/interface/Drivers/CMSIS/Core/Include/core_armv8mbl.h new file mode 100644 index 00000000..932d3d18 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/core_armv8mbl.h @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/core_armv8mml.h b/benchmark/interface/Drivers/CMSIS/Core/Include/core_armv8mml.h new file mode 100644 index 00000000..c119fbf24 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/core_armv8mml.h @@ -0,0 +1,3209 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm0.h b/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm0.h new file mode 100644 index 00000000..6441ff34 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm0plus.h b/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm0plus.h new file mode 100644 index 00000000..4e7179a6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm1.h b/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm1.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm1.h rename to benchmark/interface/Drivers/CMSIS/Core/Include/core_cm1.h index 44c2a491..76b45697 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm1.h +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm1.h @@ -1,979 +1,979 @@ -/**************************************************************************//** - * @file core_cm1.h - * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File - * @version V1.0.1 - * @date 12. November 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM1_H_GENERIC -#define __CORE_CM1_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M1 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM1 definitions */ -#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ - __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (1U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM1_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM1_H_DEPENDANT -#define __CORE_CM1_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM1_REV - #define __CM1_REV 0x0100U - #warning "__CM1_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M1 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ -#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ - -#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ -#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M1 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - Address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)0x0U; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)0x0U; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM1_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm23.h b/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm23.h new file mode 100644 index 00000000..55fff995 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm23.h @@ -0,0 +1,2297 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 11. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm3.h b/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm3.h new file mode 100644 index 00000000..74fb87e5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm33.h b/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm33.h new file mode 100644 index 00000000..18a2e6fb --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm33.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm35p.h b/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm35p.h new file mode 100644 index 00000000..3843d954 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm35p.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.1.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm4.h b/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm4.h new file mode 100644 index 00000000..e21cd149 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm55.h b/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm55.h new file mode 100644 index 00000000..faa30ce3 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm55.h @@ -0,0 +1,4817 @@ +/**************************************************************************//** + * @file core_cm55.h + * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File + * @version V1.2.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2018-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ +#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ + __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ +#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ + +#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ +#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ + +#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ +#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ + +#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ +#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ + +#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ +#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ + +#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */ +#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */ + +#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */ +#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */ + +#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */ +#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __OM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sanple Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ + __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ + +} STL_Type; + +/* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (0x1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (0x1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (0x1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (0x1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (0x1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (0x1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/* STL Software Test Library Observation Register (STLIMPUOR) Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */ +#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ +#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ + +#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ +#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */ +#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ +#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ + +#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ +#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ + +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ + +/* 'SCnSCB' is deprecated and replaced by 'ICB' */ +typedef ICB_Type SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISCRITAXIRUW_Pos (ICB_ACTLR_DISCRITAXIRUW_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUW_Msk (ICB_ACTLR_DISCRITAXIRUW_Msk) + +#define SCnSCB_ACTLR_DISDI_Pos (ICB_ACTLR_DISDI_Pos) +#define SCnSCB_ACTLR_DISDI_Msk (ICB_ACTLR_DISDI_Msk) + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos (ICB_ACTLR_DISCRITAXIRUR_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (ICB_ACTLR_DISCRITAXIRUR_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_Pos (ICB_ACTLR_EVENTBUSEN_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_Msk (ICB_ACTLR_EVENTBUSEN_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_S_Pos (ICB_ACTLR_EVENTBUSEN_S_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_S_Msk (ICB_ACTLR_EVENTBUSEN_S_Msk) + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos (ICB_ACTLR_DISITMATBFLUSH_Pos) +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (ICB_ACTLR_DISITMATBFLUSH_Msk) + +#define SCnSCB_ACTLR_DISNWAMODE_Pos (ICB_ACTLR_DISNWAMODE_Pos) +#define SCnSCB_ACTLR_DISNWAMODE_Msk (ICB_ACTLR_DISNWAMODE_Msk) + +#define SCnSCB_ACTLR_FPEXCODIS_Pos (ICB_ACTLR_FPEXCODIS_Pos) +#define SCnSCB_ACTLR_FPEXCODIS_Msk (ICB_ACTLR_FPEXCODIS_Msk) + +#define SCnSCB_ACTLR_DISOLAP_Pos (ICB_ACTLR_DISOLAP_Pos) +#define SCnSCB_ACTLR_DISOLAP_Msk (ICB_ACTLR_DISOLAP_Msk) + +#define SCnSCB_ACTLR_DISOLAPS_Pos (ICB_ACTLR_DISOLAPS_Pos) +#define SCnSCB_ACTLR_DISOLAPS_Msk (ICB_ACTLR_DISOLAPS_Msk) + +#define SCnSCB_ACTLR_DISLOBR_Pos (ICB_ACTLR_DISLOBR_Pos) +#define SCnSCB_ACTLR_DISLOBR_Msk (ICB_ACTLR_DISLOBR_Msk) + +#define SCnSCB_ACTLR_DISLO_Pos (ICB_ACTLR_DISLO_Pos) +#define SCnSCB_ACTLR_DISLO_Msk (ICB_ACTLR_DISLO_Msk) + +#define SCnSCB_ACTLR_DISLOLEP_Pos (ICB_ACTLR_DISLOLEP_Pos) +#define SCnSCB_ACTLR_DISLOLEP_Msk (ICB_ACTLR_DISLOLEP_Msk) + +#define SCnSCB_ACTLR_DISFOLD_Pos (ICB_ACTLR_DISFOLD_Pos) +#define SCnSCB_ACTLR_DISFOLD_Msk (ICB_ACTLR_DISFOLD_Msk) + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos (ICB_ICTR_INTLINESNUM_Pos) +#define SCnSCB_ICTR_INTLINESNUM_Msk (ICB_ICTR_INTLINESNUM_Msk) + +#define SCnSCB (ICB) +#define SCnSCB_NS (ICB_NS) + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ +#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm7.h b/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm7.h new file mode 100644 index 00000000..010506e9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm7.h @@ -0,0 +1,2366 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.6 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ + uint32_t RESERVED7[5U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */ + +#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ +#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm85.h b/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm85.h new file mode 100644 index 00000000..60463111 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/core_cm85.h @@ -0,0 +1,4672 @@ +/**************************************************************************//** + * @file core_cm85.h + * @brief CMSIS Cortex-M85 Core Peripheral Access Layer Header File + * @version V1.0.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM85_H_GENERIC +#define __CORE_CM85_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M85 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM85 definitions */ + +#define __CORTEX_M (85U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM85_H_DEPENDANT +#define __CORE_CM85_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM85_REV + #define __CM85_REV 0x0001U + #warning "__CM85_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M85 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:1; /*!< bit: 20 Reserved */ + uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ + uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_B_Pos 21U /*!< xPSR: B Position */ +#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ + uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ + uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ + uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ + uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ +#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ + +#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ +#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ + +#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ +#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ + +#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ +#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ + +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U /*!< MEMSYSCTL PFCR: DIS_NLP Position */ +#define MEMSYSCTL_PFCR_DIS_NLP_Msk (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) /*!< MEMSYSCTL PFCR: DIS_NLP Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M85 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ +#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ +#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */ +#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ +#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< The prefetcher starts a line-fill */ +#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< The prefetcher stops prefetching */ +#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM85_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access on the P-AHB write interface */ +#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################### PAC Key functions ########################### */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) +#include "pac_armv81.h" +#endif + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/core_sc000.h b/benchmark/interface/Drivers/CMSIS/Core/Include/core_sc000.h new file mode 100644 index 00000000..dbc755ff --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/core_sc000.h @@ -0,0 +1,1030 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/core_sc300.h b/benchmark/interface/Drivers/CMSIS/Core/Include/core_sc300.h new file mode 100644 index 00000000..d6662103 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/core_sc300.h @@ -0,0 +1,1917 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.10 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/core_starmc1.h b/benchmark/interface/Drivers/CMSIS/Core/Include/core_starmc1.h new file mode 100644 index 00000000..d86c8d38 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/core_starmc1.h @@ -0,0 +1,3592 @@ +/**************************************************************************//** + * @file core_starmc1.h + * @brief CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File + * @version V1.0.2 + * @date 07. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. + * Copyright (c) 2018-2022 Arm China. + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_STAR_H_GENERIC +#define __CORE_STAR_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup STAR-MC1 + @{ + */ + +#include "cmsis_version.h" + +/* Macro Define for STAR-MC1 */ +#define __STAR_MC (1U) /*!< STAR-MC Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_STAR_H_DEPENDANT +#define __CORE_STAR_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __STAR_REV + #define __STAR_REV 0x0000U + #warning "__STAR_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group STAR-MC1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for STAR-MC1 processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED_ADD1[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +typedef struct +{ + __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ + __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ +}EMSS_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ +#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ + +#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ +#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ + + + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache line Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ +#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ + +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean line by Set-way Register Definitions */ +#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ +#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ + +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ +#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ + +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* ArmChina: Implementation Defined */ +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ +#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ + +#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ +#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ + +#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ +#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ + +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/** + \brief Software Reset + \details Initiates a system reset request to reset the CPU. + */ +__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ + SCB_AIRCR_SYSRESETREQ_Msk ); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/mpu_armv7.h b/benchmark/interface/Drivers/CMSIS/Core/Include/mpu_armv7.h new file mode 100644 index 00000000..d9eedf81 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/mpu_armv8.h b/benchmark/interface/Drivers/CMSIS/Core/Include/mpu_armv8.h new file mode 100644 index 00000000..3de16efc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.3 + * @date 03. February 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/pac_armv81.h b/benchmark/interface/Drivers/CMSIS/Core/Include/pac_armv81.h new file mode 100644 index 00000000..854b60a2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/pac_armv81.h @@ -0,0 +1,206 @@ +/****************************************************************************** + * @file pac_armv81.h + * @brief CMSIS PAC key functions for Armv8.1-M PAC extension + * @version V1.0.0 + * @date 23. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef PAC_ARMV81_H +#define PAC_ARMV81_H + + +/* ################### PAC Key functions ########################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions + \brief Functions that access the PAC keys. + @{ + */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + +/** + \brief read the PAC key used for privileged mode + \details Reads the PAC key stored in the PAC_KEY_P registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode + \details writes the given PAC key to the PAC_KEY_P registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode + \details Reads the PAC key stored in the PAC_KEY_U registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode + \details writes the given PAC key to the PAC_KEY_U registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + +/** + \brief read the PAC key used for privileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ + +#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ + +/*@} end of CMSIS_Core_PacKeyFunctions */ + + +#endif /* PAC_ARMV81_H */ diff --git a/benchmark/interface/Drivers/CMSIS/Core/Include/pmu_armv8.h b/benchmark/interface/Drivers/CMSIS/Core/Include/pmu_armv8.h new file mode 100644 index 00000000..f8f3d893 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/pmu_armv8.h @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.1 + * @date 15. April 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/tz_context.h b/benchmark/interface/Drivers/CMSIS/Core/Include/tz_context.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/tz_context.h rename to benchmark/interface/Drivers/CMSIS/Core/Include/tz_context.h index d4c1474f..0d09749f 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/tz_context.h +++ b/benchmark/interface/Drivers/CMSIS/Core/Include/tz_context.h @@ -1,70 +1,70 @@ -/****************************************************************************** - * @file tz_context.h - * @brief Context Management for Armv8-M TrustZone - * @version V1.0.1 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2017-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef TZ_CONTEXT_H -#define TZ_CONTEXT_H - -#include - -#ifndef TZ_MODULEID_T -#define TZ_MODULEID_T -/// \details Data type that identifies secure software modules called by a process. -typedef uint32_t TZ_ModuleId_t; -#endif - -/// \details TZ Memory ID identifies an allocated memory slot. -typedef uint32_t TZ_MemoryId_t; - -/// Initialize secure context memory system -/// \return execution status (1: success, 0: error) -uint32_t TZ_InitContextSystem_S (void); - -/// Allocate context memory for calling secure software modules in TrustZone -/// \param[in] module identifies software modules called from non-secure mode -/// \return value != 0 id TrustZone memory slot identifier -/// \return value 0 no memory available or internal error -TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); - -/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); - -/// Load secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); - -/// Store secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); - -#endif // TZ_CONTEXT_H +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/benchmark/interface/Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c b/benchmark/interface/Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c new file mode 100644 index 00000000..273607b2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c @@ -0,0 +1,58 @@ +/****************************************************************************** + * @file main_s.c + * @brief Code template for secure main function + * @version V1.1.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Use CMSE intrinsics */ +#include + +#include "RTE_Components.h" +#include CMSIS_device_header + +/* TZ_START_NS: Start address of non-secure application */ +#ifndef TZ_START_NS +#define TZ_START_NS (0x200000U) +#endif + +/* typedef for non-secure callback functions */ +typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); + +/* Secure main() */ +int main(void) { + funcptr_void NonSecure_ResetHandler; + + /* Add user setup code for secure part here*/ + + /* Set non-secure main stack (MSP_NS) */ + __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); + + /* Get non-secure reset handler */ + NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); + + /* Start non-secure state software application */ + NonSecure_ResetHandler(); + + /* Non-secure software does not return, this code is not executed */ + while (1) { + __NOP(); + } +} diff --git a/benchmark/interface/Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c b/benchmark/interface/Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c new file mode 100644 index 00000000..e2e82942 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c @@ -0,0 +1,200 @@ +/****************************************************************************** + * @file tz_context.c + * @brief Context Management for Armv8-M TrustZone - Sample implementation + * @version V1.1.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2016-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "RTE_Components.h" +#include CMSIS_device_header +#include "tz_context.h" + +/// Number of process slots (threads may call secure library code) +#ifndef TZ_PROCESS_STACK_SLOTS +#define TZ_PROCESS_STACK_SLOTS 8U +#endif + +/// Stack size of the secure library code +#ifndef TZ_PROCESS_STACK_SIZE +#define TZ_PROCESS_STACK_SIZE 256U +#endif + +typedef struct { + uint32_t sp_top; // stack space top + uint32_t sp_limit; // stack space limit + uint32_t sp; // current stack pointer +} stack_info_t; + +static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS]; +static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U]; +static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU; + + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_InitContextSystem_S (void) { + uint32_t n; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { + ProcessStackInfo[n].sp = 0U; + ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; + ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; + *((uint32_t *)ProcessStackMemory[n]) = n + 1U; + } + *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU; + + ProcessStackFreeSlot = 0U; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + // Privileged Thread Mode using PSP + __set_CONTROL(0x02U); + + return 1U; // Success +} + + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +__attribute__((cmse_nonsecure_entry)) +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) { + uint32_t slot; + + (void)module; // Ignore (fixed Stack size) + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if (ProcessStackFreeSlot == 0xFFFFFFFFU) { + return 0U; // No slot available + } + + slot = ProcessStackFreeSlot; + ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]); + + ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top; + + return (slot + 1U); +} + + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + ProcessStackInfo[slot].sp = 0U; + + *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot; + ProcessStackFreeSlot = slot; + + return 1U; // Success +} + + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + // Setup process stack pointer and stack limit + __set_PSPLIM(ProcessStackInfo[slot].sp_limit); + __set_PSP (ProcessStackInfo[slot].sp); + + return 1U; // Success +} + + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) { + uint32_t slot; + uint32_t sp; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + sp = __get_PSP(); + if ((sp < ProcessStackInfo[slot].sp_limit) || + (sp > ProcessStackInfo[slot].sp_top)) { + return 0U; // SP out of range + } + ProcessStackInfo[slot].sp = sp; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + return 1U; // Success +} diff --git a/benchmark/interface/Drivers/CMSIS/Core_A/Include/cmsis_armcc.h b/benchmark/interface/Drivers/CMSIS/Core_A/Include/cmsis_armcc.h new file mode 100644 index 00000000..0d9c3742 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core_A/Include/cmsis_armcc.h @@ -0,0 +1,563 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.5 + * @date 05. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A == 1)) + #define __ARM_ARCH_7A__ 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __forceinline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ########################## Core Instruction Access ######################### */ +/** + \brief No Operation + */ +#define __NOP __nop + +/** + \brief Wait For Interrupt + */ +#define __WFI __wfi + +/** + \brief Wait For Event + */ +#define __WFE __wfe + +/** + \brief Send Event + */ +#define __SEV __sev + +/** + \brief Instruction Synchronization Barrier + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + */ +#define __DMB() __dmb(0xF) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + +/** + \brief Rotate Right in unsigned value (32 bit) + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + +/** + \brief Breakpoint + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + +/** + \brief Reverse bit order of value + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + +/** + \brief Count leading zeros + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + +/* ########################### Core Function Access ########################### */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(void); */ + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + +/** + \brief Get FPSCR (Floating Point Status/Control) + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + +/** + \brief Set FPSCR (Floating Point Status/Control) + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + +/** \brief Get CPSR (Current Program Status Register) + \return CPSR Register value + */ +__STATIC_INLINE uint32_t __get_CPSR(void) +{ + register uint32_t __regCPSR __ASM("cpsr"); + return(__regCPSR); +} + + +/** \brief Set CPSR (Current Program Status Register) + \param [in] cpsr CPSR value to set + */ +__STATIC_INLINE void __set_CPSR(uint32_t cpsr) +{ + register uint32_t __regCPSR __ASM("cpsr"); + __regCPSR = cpsr; +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_INLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_INLINE __ASM void __set_mode(uint32_t mode) +{ + MOV r1, lr + MSR CPSR_C, r0 + BX r1 +} + +/** \brief Get Stack Pointer + \return Stack Pointer + */ +__STATIC_INLINE __ASM uint32_t __get_SP(void) +{ + MOV r0, sp + BX lr +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_INLINE __ASM void __set_SP(uint32_t stack) +{ + MOV sp, r0 + BX lr +} + + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYSStack Pointer + */ +__STATIC_INLINE __ASM uint32_t __get_SP_usr(void) +{ + ARM + PRESERVE8 + + MRS R1, CPSR + CPS #0x1F ;no effect in USR mode + MOV R0, SP + MSR CPSR_c, R1 ;no effect in USR mode + ISB + BX LR +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack) +{ + ARM + PRESERVE8 + + MRS R1, CPSR + CPS #0x1F ;no effect in USR mode + MOV SP, R0 + MSR CPSR_c, R1 ;no effect in USR mode + ISB + BX LR +} + +/** \brief Get FPEXC (Floating Point Exception Control Register) + \return Floating Point Exception Control Register value + */ +__STATIC_INLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpexc __ASM("fpexc"); + return(__regfpexc); +#else + return(0); +#endif +} + +/** \brief Set FPEXC (Floating Point Exception Control Register) + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_INLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpexc __ASM("fpexc"); + __regfpexc = (fpexc); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0) +#define __get_CP64(cp, op1, Rt, CRm) \ + do { \ + uint32_t ltmp, htmp; \ + __ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \ + (Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \ + } while(0) + +#define __set_CP64(cp, op1, Rt, CRm) \ + do { \ + const uint64_t tmp = (Rt); \ + const uint32_t ltmp = (uint32_t)(tmp); \ + const uint32_t htmp = (uint32_t)(tmp >> 32U); \ + __ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \ + } while(0) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE __ASM void __FPU_Enable(void) +{ + ARM + + //Permit access to VFP/NEON, registers by modifying CPACR + MRC p15,0,R1,c1,c0,2 + ORR R1,R1,#0x00F00000 + MCR p15,0,R1,c1,c0,2 + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + ISB + + //Enable VFP/NEON + VMRS R1,FPEXC + ORR R1,R1,#0x40000000 + VMSR FPEXC,R1 + + //Initialise VFP/NEON registers to 0 + MOV R2,#0 + + //Initialise D16 registers to 0 + VMOV D0, R2,R2 + VMOV D1, R2,R2 + VMOV D2, R2,R2 + VMOV D3, R2,R2 + VMOV D4, R2,R2 + VMOV D5, R2,R2 + VMOV D6, R2,R2 + VMOV D7, R2,R2 + VMOV D8, R2,R2 + VMOV D9, R2,R2 + VMOV D10,R2,R2 + VMOV D11,R2,R2 + VMOV D12,R2,R2 + VMOV D13,R2,R2 + VMOV D14,R2,R2 + VMOV D15,R2,R2 + + IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 + //Initialise D32 registers to 0 + VMOV D16,R2,R2 + VMOV D17,R2,R2 + VMOV D18,R2,R2 + VMOV D19,R2,R2 + VMOV D20,R2,R2 + VMOV D21,R2,R2 + VMOV D22,R2,R2 + VMOV D23,R2,R2 + VMOV D24,R2,R2 + VMOV D25,R2,R2 + VMOV D26,R2,R2 + VMOV D27,R2,R2 + VMOV D28,R2,R2 + VMOV D29,R2,R2 + VMOV D30,R2,R2 + VMOV D31,R2,R2 + ENDIF + + //Initialise FPSCR to a known state + VMRS R1,FPSCR + LDR R2,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + AND R1,R1,R2 + VMSR FPSCR,R1 + + BX LR +} + +#endif /* __CMSIS_ARMCC_H */ diff --git a/benchmark/interface/Drivers/CMSIS/Core_A/Include/cmsis_armclang.h b/benchmark/interface/Drivers/CMSIS/Core_A/Include/cmsis_armclang.h new file mode 100644 index 00000000..e64eba93 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core_A/Include/cmsis_armclang.h @@ -0,0 +1,614 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.2.1 + * @date 05. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __attribute__((always_inline)) +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ########################## Core Instruction Access ######################### */ +/** + \brief No Operation + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + */ +#define __WFI __builtin_arm_wfi + +/** + \brief Wait For Event + */ +#define __WFE __builtin_arm_wfe + +/** + \brief Send Event + */ +#define __SEV __builtin_arm_sev + +/** + \brief Instruction Synchronization Barrier + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + */ +#define __DSB() __builtin_arm_dsb(0xF) + +/** + \brief Data Memory Barrier + */ +#define __DMB() __builtin_arm_dmb(0xF) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + +/** + \brief Reverse bit order of value + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD8 __builtin_arm_qadd8 +#define __QSUB8 __builtin_arm_qsub8 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __SXTB16 __builtin_arm_sxtb16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSDX __builtin_arm_smlsdx +#define __USAT16 __builtin_arm_usat16 +#define __SSUB8 __builtin_arm_ssub8 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 + + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ + +/* ########################### Core Function Access ########################### */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#define __get_FPSCR __builtin_arm_get_fpscr + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#define __set_FPSCR __builtin_arm_set_fpscr + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : : "memory" + ); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory" + ); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#if (defined(__ARM_NEON) && (__ARM_NEON == 1)) + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R1,FPSCR \n" + " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 " + : : : "cc", "r1", "r2" + ); +} + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/benchmark/interface/Drivers/CMSIS/Core_A/Include/cmsis_compiler.h b/benchmark/interface/Drivers/CMSIS/Core_A/Include/cmsis_compiler.h new file mode 100644 index 00000000..dfd07a26 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core_A/Include/cmsis_compiler.h @@ -0,0 +1,213 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.2 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include "cmsis_iccarm.h" + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef CMSIS_DEPRECATED + #warning No compiler specific solution for CMSIS_DEPRECATED. CMSIS_DEPRECATED is ignored. + #define CMSIS_DEPRECATED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __UNALIGNED_UINT32 + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/benchmark/interface/Drivers/CMSIS/Core_A/Include/cmsis_cp15.h b/benchmark/interface/Drivers/CMSIS/Core_A/Include/cmsis_cp15.h new file mode 100644 index 00000000..891bec2a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core_A/Include/cmsis_cp15.h @@ -0,0 +1,514 @@ +/**************************************************************************//** + * @file cmsis_cp15.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.1 + * @date 07. Sep 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_CP15_H +#define __CMSIS_CP15_H + +/** \brief Get ACTLR + \return Auxiliary Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_ACTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 1); + return(result); +} + +/** \brief Set ACTLR + \param [in] actlr Auxiliary Control value to set + */ +__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr) +{ + __set_CP(15, 0, actlr, 1, 0, 1); +} + +/** \brief Get CPACR + \return Coprocessor Access Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 2); + return result; +} + +/** \brief Set CPACR + \param [in] cpacr Coprocessor Access Control value to set + */ +__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr) +{ + __set_CP(15, 0, cpacr, 1, 0, 2); +} + +/** \brief Get DFSR + \return Data Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 0); + return result; +} + +/** \brief Set DFSR + \param [in] dfsr Data Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr) +{ + __set_CP(15, 0, dfsr, 5, 0, 0); +} + +/** \brief Get IFSR + \return Instruction Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 1); + return result; +} + +/** \brief Set IFSR + \param [in] ifsr Instruction Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr) +{ + __set_CP(15, 0, ifsr, 5, 0, 1); +} + +/** \brief Get ISR + \return Interrupt Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ISR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 1, 0); + return result; +} + +/** \brief Get CBAR + \return Configuration Base Address register value + */ +__STATIC_FORCEINLINE uint32_t __get_CBAR(void) +{ + uint32_t result; + __get_CP(15, 4, result, 15, 0, 0); + return result; +} + +/** \brief Get TTBR0 + + This function returns the value of the Translation Table Base Register 0. + + \return Translation Table Base Register 0 value + */ +__STATIC_FORCEINLINE uint32_t __get_TTBR0(void) +{ + uint32_t result; + __get_CP(15, 0, result, 2, 0, 0); + return result; +} + +/** \brief Set TTBR0 + + This function assigns the given value to the Translation Table Base Register 0. + + \param [in] ttbr0 Translation Table Base Register 0 value to set + */ +__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0) +{ + __set_CP(15, 0, ttbr0, 2, 0, 0); +} + +/** \brief Get DACR + + This function returns the value of the Domain Access Control Register. + + \return Domain Access Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 3, 0, 0); + return result; +} + +/** \brief Set DACR + + This function assigns the given value to the Domain Access Control Register. + + \param [in] dacr Domain Access Control Register value to set + */ +__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr) +{ + __set_CP(15, 0, dacr, 3, 0, 0); +} + +/** \brief Set SCTLR + + This function assigns the given value to the System Control Register. + + \param [in] sctlr System Control Register value to set + */ +__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr) +{ + __set_CP(15, 0, sctlr, 1, 0, 0); +} + +/** \brief Get SCTLR + \return System Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_SCTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 0); + return result; +} + +/** \brief Set ACTRL + \param [in] actrl Auxiliary Control Register value to set + */ +__STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl) +{ + __set_CP(15, 0, actrl, 1, 0, 1); +} + +/** \brief Get ACTRL + \return Auxiliary Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ACTRL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 1); + return result; +} + +/** \brief Get MPIDR + + This function returns the value of the Multiprocessor Affinity Register. + + \return Multiprocessor Affinity Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MPIDR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 0, 5); + return result; +} + +/** \brief Get VBAR + + This function returns the value of the Vector Base Address Register. + + \return Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_VBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 0); + return result; +} + +/** \brief Set VBAR + + This function assigns the given value to the Vector Base Address Register. + + \param [in] vbar Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar) +{ + __set_CP(15, 0, vbar, 12, 0, 0); +} + +/** \brief Get MVBAR + + This function returns the value of the Monitor Vector Base Address Register. + + \return Monitor Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_MVBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 1); + return result; +} + +/** \brief Set MVBAR + + This function assigns the given value to the Monitor Vector Base Address Register. + + \param [in] mvbar Monitor Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar) +{ + __set_CP(15, 0, mvbar, 12, 0, 1); +} + +#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \ + defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \ + defined(DOXYGEN) + +/** \brief Set CNTFRQ + + This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \param [in] value CNTFRQ Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value) +{ + __set_CP(15, 0, value, 14, 0, 0); +} + +/** \brief Get CNTFRQ + + This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \return CNTFRQ Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 0 , 0); + return result; +} + +/** \brief Set CNTP_TVAL + + This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). + + \param [in] value CNTP_TVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 0); +} + +/** \brief Get CNTP_TVAL + + This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). + + \return CNTP_TVAL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 0); + return result; +} + +/** \brief Get CNTPCT + + This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT). + + \return CNTPCT Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void) +{ + uint64_t result; + __get_CP64(15, 0, result, 14); + return result; +} + +/** \brief Set CNTP_CVAL + + This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \param [in] value CNTP_CVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value) +{ + __set_CP64(15, 2, value, 14); +} + +/** \brief Get CNTP_CVAL + + This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \return CNTP_CVAL Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void) +{ + uint64_t result; + __get_CP64(15, 2, result, 14); + return result; +} + +/** \brief Set CNTP_CTL + + This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). + + \param [in] value CNTP_CTL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 1); +} + +/** \brief Get CNTP_CTL register + \return CNTP_CTL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 1); + return result; +} + +#endif + +/** \brief Set TLBIALL + + TLB Invalidate All + */ +__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value) +{ + __set_CP(15, 0, value, 8, 7, 0); +} + +/** \brief Set BPIALL. + + Branch Predictor Invalidate All + */ +__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 6); +} + +/** \brief Set ICIALLU + + Instruction Cache Invalidate All + */ +__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 0); +} + +/** \brief Set DCCMVAC + + Data cache clean + */ +__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 10, 1); +} + +/** \brief Set DCIMVAC + + Data cache invalidate + */ +__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 6, 1); +} + +/** \brief Set DCCIMVAC + + Data cache clean and invalidate + */ +__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 14, 1); +} + +/** \brief Set CSSELR + */ +__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value) +{ +// __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory"); + __set_CP(15, 2, value, 0, 0, 0); +} + +/** \brief Get CSSELR + \return CSSELR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CSSELR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 2, result, 0, 0, 0); + return result; +} + +/** \brief Set CCSIDR + \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead. + */ +CMSIS_DEPRECATED +__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value) +{ + __set_CSSELR(value); +} + +/** \brief Get CCSIDR + \return CCSIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 1, result, 0, 0, 0); + return result; +} + +/** \brief Get CLIDR + \return CLIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CLIDR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory"); + __get_CP(15, 1, result, 0, 0, 1); + return result; +} + +/** \brief Set DCISW + */ +__STATIC_FORCEINLINE void __set_DCISW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 6, 2); +} + +/** \brief Set DCCSW + */ +__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 10, 2); +} + +/** \brief Set DCCISW + */ +__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 14, 2); +} + +#endif diff --git a/benchmark/interface/Drivers/CMSIS/Core_A/Include/cmsis_gcc.h b/benchmark/interface/Drivers/CMSIS/Core_A/Include/cmsis_gcc.h new file mode 100644 index 00000000..920d6120 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core_A/Include/cmsis_gcc.h @@ -0,0 +1,917 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.3.2 + * @date 24. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __attribute__((always_inline)) +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + + +/* ########################## Core Instruction Access ######################### */ +/** + \brief No Operation + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + +/** + \brief Wait For Event + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + +/** + \brief Send Event + */ +#define __SEV() __ASM volatile ("sev") + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : "=r" (result) : "r" (value) ); + return result; +#endif +} + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + __ASM ("rev16 %0, %1" : "=r" (result) : "r" (value)); + return result; +} + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return result; +#endif +} + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return result; +} + +/** + \brief Count leading zeros + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +/* ########################### Core Function Access ########################### */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #if __has_builtin(__builtin_arm_get_fpscr) + // Re-enable using built-in when GCC has been fixed + // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); + #else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); + #endif + #else + return(0U); + #endif +} + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #if __has_builtin(__builtin_arm_set_fpscr) + // Re-enable using built-in when GCC has been fixed + // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); + #else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + #endif + #else + (void)fpscr; + #endif +} + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr = __get_CPSR(); + uint32_t result; + __ASM volatile( + "CPS #0x1F \n" + "MOV %0, sp " : "=r"(result) : : "memory" + ); + __set_CPSR(cpsr); + __ISB(); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr = __get_CPSR(); + __ASM volatile( + "CPS #0x1F \n" + "MOV sp, %0 " : : "r" (topOfProcStack) : "memory" + ); + __set_CPSR(cpsr); + __ISB(); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#if (defined(__ARM_NEON) && (__ARM_NEON == 1)) + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R1,FPSCR \n" + " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 " + : : : "cc", "r1", "r2" + ); +} + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/benchmark/interface/Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h b/benchmark/interface/Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h new file mode 100644 index 00000000..08aa2241 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h @@ -0,0 +1,573 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.7 + * @date 15. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// Copyright (c) 2018-2019 Arm Limited +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#pragma language=extended + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_7A__ +/* Macro already defined */ +#else + #if defined(__ARM7A__) + #define __ARM_ARCH_7A__ 1 + #endif +#endif + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + /* Needs IAR language extensions */ + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + /* Needs IAR language extensions */ + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + /* Needs IAR language extensions */ + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif + +#ifndef __UNALIGNED_UINT16_READ + #pragma language=save + #pragma language=extended + __IAR_FT uint16_t __iar_uint16_read(void const *ptr) + { + return *(__packed uint16_t*)(ptr); + } + #pragma language=restore + #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE + #pragma language=save + #pragma language=extended + __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) + { + *(__packed uint16_t*)(ptr) = val;; + } + #pragma language=restore + #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ + #pragma language=save + #pragma language=extended + __IAR_FT uint32_t __iar_uint32_read(void const *ptr) + { + return *(__packed uint32_t*)(ptr); + } + #pragma language=restore + #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE + #pragma language=save + #pragma language=extended + __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) + { + *(__packed uint32_t*)(ptr) = val;; + } + #pragma language=restore + #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#if 0 +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma language=save + #pragma language=extended + __packed struct __iar_u32 { uint32_t v; }; + #pragma language=restore + #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __enable_irq __iar_builtin_enable_interrupt + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + #if __FPU_PRESENT + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #else + #define __get_FPSCR() ( 0 ) + #endif + + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", VALUE)) + + #define __get_CPSR() (__arm_rsr("CPSR")) + #define __get_mode() (__get_CPSR() & 0x1FU) + + #define __set_CPSR(VALUE) (__arm_wsr("CPSR", (VALUE))) + #define __set_mode(VALUE) (__arm_wsr("CPSR_c", (VALUE))) + + + #define __get_FPEXC() (__arm_rsr("FPEXC")) + #define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE)) + + #define __get_CP(cp, op1, RT, CRn, CRm, op2) \ + ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2)) + + #define __set_CP(cp, op1, RT, CRn, CRm, op2) \ + (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT))) + + #define __get_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) + + #define __set_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + + #include "cmsis_cp15.h" + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #define __SSAT __iar_builtin_SSAT + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #define __USAT __iar_builtin_USAT + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if !__FPU_PRESENT + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if !__FPU_PRESENT + #define __get_FPSCR() (0) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + __IAR_FT void __set_mode(uint32_t mode) + { + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); + } + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + __IAR_FT uint32_t __get_FPEXC(void) + { + #if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); + #else + return(0); + #endif + } + + __IAR_FT void __set_FPEXC(uint32_t fpexc) + { + #if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); + #endif + } + + + #define __get_CP(cp, op1, Rt, CRn, CRm, op2) \ + __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) + #define __set_CP(cp, op1, Rt, CRn, CRm, op2) \ + __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) + #define __get_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) + #define __set_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + + #include "cmsis_cp15.h" + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + + +__IAR_FT uint32_t __get_SP_usr(void) +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory" + ); + return result; +} + +__IAR_FT void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory" + ); +} + +#define __get_mode() (__get_CPSR() & 0x1FU) + +__STATIC_INLINE +void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#ifdef __ARM_ADVANCED_SIMD__ + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R1,FPSCR \n" + " MOV32 R2,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 \n" + : : : "cc", "r1", "r2" + ); +} + + + +#undef __IAR_FT +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/benchmark/interface/Drivers/CMSIS/Core_A/Include/core_ca.h b/benchmark/interface/Drivers/CMSIS/Core_A/Include/core_ca.h new file mode 100644 index 00000000..c4f92690 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core_A/Include/core_ca.h @@ -0,0 +1,2614 @@ +/**************************************************************************//** + * @file core_ca.h + * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File + * @version V1.0.3 + * @date 28. January 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CA_H_GENERIC +#define __CORE_CA_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ + +/* CMSIS CA definitions */ +#define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS-Core(A) main version */ +#define __CA_CMSIS_VERSION_SUB (1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ +#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \ + __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */ + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CA_H_DEPENDANT +#define __CORE_CA_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + + /* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CA_REV + #define __CA_REV 0x0000U + #warning "__CA_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __GIC_PRESENT + #define __GIC_PRESENT 1U + #warning "__GIC_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __TIM_PRESENT + #define __TIM_PRESENT 1U + #warning "__TIM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __L2C_PRESENT + #define __L2C_PRESENT 0U + #warning "__L2C_PRESENT not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< \brief Defines 'read only' permissions */ +#else + #define __I volatile const /*!< \brief Defines 'read only' permissions */ +#endif +#define __O volatile /*!< \brief Defines 'write only' permissions */ +#define __IO volatile /*!< \brief Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */ +#define __OM volatile /*!< \brief Defines 'write only' structure member permissions */ +#define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */ +#define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas + + /******************************************************************************* + * Register Abstraction + Core Register contain: + - CPSR + - CP15 Registers + - L2C-310 Cache Controller + - Generic Interrupt Controller Distributor + - Generic Interrupt Controller Interface + ******************************************************************************/ + +/* Core Register CPSR */ +typedef union +{ + struct + { + uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */ + uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */ + uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */ + uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */ + uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */ + uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */ + uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */ + uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */ + RESERVED(0:4, uint32_t) + uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */ + uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */ + uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */ + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CPSR_Type; + + + +/* CPSR Register Definitions */ +#define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */ +#define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */ + +#define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */ +#define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */ + +#define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */ +#define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */ + +#define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */ +#define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */ + +#define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */ +#define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */ + +#define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */ +#define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */ + +#define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */ +#define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */ + +#define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */ +#define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */ + +#define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */ +#define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */ + +#define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */ +#define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */ + +#define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */ +#define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */ + +#define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */ +#define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */ + +#define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */ +#define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */ + +#define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */ +#define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */ + +#define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */ +#define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */ + +#define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */ +#define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */ +#define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */ +#define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */ +#define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */ +#define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */ +#define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */ +#define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */ +#define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */ + +/* CP15 Register SCTLR */ +typedef union +{ + struct + { + uint32_t M:1; /*!< \brief bit: 0 MMU enable */ + uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */ + uint32_t C:1; /*!< \brief bit: 2 Cache enable */ + RESERVED(0:2, uint32_t) + uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */ + RESERVED(1:1, uint32_t) + uint32_t B:1; /*!< \brief bit: 7 Endianness model */ + RESERVED(2:2, uint32_t) + uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */ + uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */ + uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */ + uint32_t V:1; /*!< \brief bit: 13 Vectors bit */ + uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */ + RESERVED(3:2, uint32_t) + uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */ + RESERVED(4:1, uint32_t) + uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */ + uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */ + uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */ + uint32_t U:1; /*!< \brief bit: 22 Alignment model */ + RESERVED(5:1, uint32_t) + uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */ + uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */ + RESERVED(6:1, uint32_t) + uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */ + uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */ + uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */ + uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */ + RESERVED(7:1, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} SCTLR_Type; + +#define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */ +#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */ + +#define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */ +#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */ + +#define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */ +#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */ + +#define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */ +#define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */ + +#define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */ +#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */ + +#define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */ +#define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */ + +#define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */ +#define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */ + +#define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */ +#define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */ + +#define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */ +#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */ + +#define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */ +#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */ + +#define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */ +#define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */ + +#define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */ +#define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */ + +#define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */ +#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */ + +#define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */ +#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */ + +#define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */ +#define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */ + +#define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */ +#define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */ + +#define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */ +#define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */ + +#define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */ +#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */ + +#define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */ +#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */ + +#define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */ +#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */ + +#define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */ +#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */ + +/* CP15 Register ACTLR */ +typedef union +{ +#if __CORTEX_A == 5 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A5 */ + struct + { + uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ + RESERVED(0:5, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ + RESERVED(1:2, uint32_t) + uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ + uint32_t DWBST:1; /*!< \brief bit: 11 AXI data write bursts to Normal memory */ + uint32_t RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ + uint32_t BP:2; /*!< \brief bit:16..15 Branch prediction policy */ + uint32_t RSDIS:1; /*!< \brief bit: 17 Disable return stack operation */ + uint32_t BTDIS:1; /*!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) */ + RESERVED(3:9, uint32_t) + uint32_t DBDI:1; /*!< \brief bit: 28 Disable branch dual issue */ + RESERVED(7:3, uint32_t) + } b; +#endif +#if __CORTEX_A == 7 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A7 */ + struct + { + RESERVED(0:6, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + RESERVED(1:3, uint32_t) + uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ + uint32_t L2RADIS:1; /*!< \brief bit: 11 L2 Data Cache read-allocate mode disable */ + uint32_t L1RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ + uint32_t DDVM:1; /*!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions */ + RESERVED(3:12, uint32_t) + uint32_t DDI:1; /*!< \brief bit: 28 Disable dual issue */ + RESERVED(7:3, uint32_t) + } b; +#endif +#if __CORTEX_A == 9 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A9 */ + struct + { + uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ + RESERVED(0:1, uint32_t) + uint32_t L1PE:1; /*!< \brief bit: 2 Dside prefetch */ + uint32_t WFLZM:1; /*!< \brief bit: 3 Cache and TLB maintenance broadcast */ + RESERVED(1:2, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ + uint32_t AOW:1; /*!< \brief bit: 8 Enable allocation in one cache way only */ + uint32_t PARITY:1; /*!< \brief bit: 9 Support for parity checking, if implemented */ + RESERVED(7:22, uint32_t) + } b; +#endif + uint32_t w; /*!< \brief Type used for word access */ +} ACTLR_Type; + +#define ACTLR_DDI_Pos 28U /*!< \brief ACTLR: DDI Position */ +#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< \brief ACTLR: DDI Mask */ + +#define ACTLR_DBDI_Pos 28U /*!< \brief ACTLR: DBDI Position */ +#define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /*!< \brief ACTLR: DBDI Mask */ + +#define ACTLR_BTDIS_Pos 18U /*!< \brief ACTLR: BTDIS Position */ +#define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /*!< \brief ACTLR: BTDIS Mask */ + +#define ACTLR_RSDIS_Pos 17U /*!< \brief ACTLR: RSDIS Position */ +#define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /*!< \brief ACTLR: RSDIS Mask */ + +#define ACTLR_BP_Pos 15U /*!< \brief ACTLR: BP Position */ +#define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /*!< \brief ACTLR: BP Mask */ + +#define ACTLR_DDVM_Pos 15U /*!< \brief ACTLR: DDVM Position */ +#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< \brief ACTLR: DDVM Mask */ + +#define ACTLR_L1PCTL_Pos 13U /*!< \brief ACTLR: L1PCTL Position */ +#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< \brief ACTLR: L1PCTL Mask */ + +#define ACTLR_RADIS_Pos 12U /*!< \brief ACTLR: RADIS Position */ +#define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /*!< \brief ACTLR: RADIS Mask */ + +#define ACTLR_L1RADIS_Pos 12U /*!< \brief ACTLR: L1RADIS Position */ +#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< \brief ACTLR: L1RADIS Mask */ + +#define ACTLR_DWBST_Pos 11U /*!< \brief ACTLR: DWBST Position */ +#define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /*!< \brief ACTLR: DWBST Mask */ + +#define ACTLR_L2RADIS_Pos 11U /*!< \brief ACTLR: L2RADIS Position */ +#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< \brief ACTLR: L2RADIS Mask */ + +#define ACTLR_DODMBS_Pos 10U /*!< \brief ACTLR: DODMBS Position */ +#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< \brief ACTLR: DODMBS Mask */ + +#define ACTLR_PARITY_Pos 9U /*!< \brief ACTLR: PARITY Position */ +#define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /*!< \brief ACTLR: PARITY Mask */ + +#define ACTLR_AOW_Pos 8U /*!< \brief ACTLR: AOW Position */ +#define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /*!< \brief ACTLR: AOW Mask */ + +#define ACTLR_EXCL_Pos 7U /*!< \brief ACTLR: EXCL Position */ +#define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /*!< \brief ACTLR: EXCL Mask */ + +#define ACTLR_SMP_Pos 6U /*!< \brief ACTLR: SMP Position */ +#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< \brief ACTLR: SMP Mask */ + +#define ACTLR_WFLZM_Pos 3U /*!< \brief ACTLR: WFLZM Position */ +#define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /*!< \brief ACTLR: WFLZM Mask */ + +#define ACTLR_L1PE_Pos 2U /*!< \brief ACTLR: L1PE Position */ +#define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /*!< \brief ACTLR: L1PE Mask */ + +#define ACTLR_FW_Pos 0U /*!< \brief ACTLR: FW Position */ +#define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /*!< \brief ACTLR: FW Mask */ + +/* CP15 Register CPACR */ +typedef union +{ + struct + { + uint32_t CP0:2; /*!< \brief bit: 0..1 Access rights for coprocessor 0 */ + uint32_t CP1:2; /*!< \brief bit: 2..3 Access rights for coprocessor 1 */ + uint32_t CP2:2; /*!< \brief bit: 4..5 Access rights for coprocessor 2 */ + uint32_t CP3:2; /*!< \brief bit: 6..7 Access rights for coprocessor 3 */ + uint32_t CP4:2; /*!< \brief bit: 8..9 Access rights for coprocessor 4 */ + uint32_t CP5:2; /*!< \brief bit:10..11 Access rights for coprocessor 5 */ + uint32_t CP6:2; /*!< \brief bit:12..13 Access rights for coprocessor 6 */ + uint32_t CP7:2; /*!< \brief bit:14..15 Access rights for coprocessor 7 */ + uint32_t CP8:2; /*!< \brief bit:16..17 Access rights for coprocessor 8 */ + uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */ + uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */ + uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */ + uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */ + uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */ + uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */ + RESERVED(0:1, uint32_t) + uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */ + uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */ + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CPACR_Type; + +#define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */ +#define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */ + +#define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */ +#define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ + +#define CPACR_TRCDIS_Pos 28U /*!< \brief CPACR: D32DIS Position */ +#define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ + +#define CPACR_CP_Pos_(n) (n*2U) /*!< \brief CPACR: CPn Position */ +#define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /*!< \brief CPACR: CPn Mask */ + +#define CPACR_CP_NA 0U /*!< \brief CPACR CPn field: Access denied. */ +#define CPACR_CP_PL1 1U /*!< \brief CPACR CPn field: Accessible from PL1 only. */ +#define CPACR_CP_FA 3U /*!< \brief CPACR CPn field: Full access. */ + +/* CP15 Register DFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ + uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */ + RESERVED(0:1, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ + uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ + RESERVED(1:18, uint32_t) + } s; /*!< \brief Structure used for bit access in short format */ + struct + { + uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */ + RESERVED(0:3, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + RESERVED(1:1, uint32_t) + uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ + RESERVED(2:18, uint32_t) + } l; /*!< \brief Structure used for bit access in long format */ + uint32_t w; /*!< \brief Type used for word access */ +} DFSR_Type; + +#define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */ +#define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */ + +#define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */ +#define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */ + +#define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */ +#define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */ + +#define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */ +#define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */ + +#define DFSR_LPAE_Pos 9U /*!< \brief DFSR: LPAE Position */ +#define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /*!< \brief DFSR: LPAE Mask */ + +#define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */ +#define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */ + +#define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */ +#define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */ + +#define DFSR_STATUS_Pos 0U /*!< \brief DFSR: STATUS Position */ +#define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /*!< \brief DFSR: STATUS Mask */ + +/* CP15 Register IFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ + RESERVED(0:5, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ + RESERVED(1:1, uint32_t) + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + RESERVED(2:19, uint32_t) + } s; /*!< \brief Structure used for bit access in short format */ + struct + { + uint32_t STATUS:6; /*!< \brief bit: 0.. 5 Fault Status bits */ + RESERVED(0:3, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + RESERVED(1:2, uint32_t) + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + RESERVED(2:19, uint32_t) + } l; /*!< \brief Structure used for bit access in long format */ + uint32_t w; /*!< \brief Type used for word access */ +} IFSR_Type; + +#define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */ +#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */ + +#define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */ +#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */ + +#define IFSR_LPAE_Pos 9U /*!< \brief IFSR: LPAE Position */ +#define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /*!< \brief IFSR: LPAE Mask */ + +#define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */ +#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */ + +#define IFSR_STATUS_Pos 0U /*!< \brief IFSR: STATUS Position */ +#define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /*!< \brief IFSR: STATUS Mask */ + +/* CP15 Register ISR */ +typedef union +{ + struct + { + RESERVED(0:6, uint32_t) + uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */ + uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */ + uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */ + RESERVED(1:23, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} ISR_Type; + +#define ISR_A_Pos 13U /*!< \brief ISR: A Position */ +#define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */ + +#define ISR_I_Pos 12U /*!< \brief ISR: I Position */ +#define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */ + +#define ISR_F_Pos 11U /*!< \brief ISR: F Position */ +#define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */ + +/* DACR Register */ +#define DACR_D_Pos_(n) (2U*n) /*!< \brief DACR: Dn Position */ +#define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /*!< \brief DACR: Dn Mask */ +#define DACR_Dn_NOACCESS 0U /*!< \brief DACR Dn field: No access */ +#define DACR_Dn_CLIENT 1U /*!< \brief DACR Dn field: Client */ +#define DACR_Dn_MANAGER 3U /*!< \brief DACR Dn field: Manager */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param [in] field Name of the register bit field. + \param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param [in] field Name of the register bit field. + \param [in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + + +/** + \brief Union type to access the L2C_310 Cache Controller. +*/ +#if (__L2C_PRESENT == 1U) || defined(DOXYGEN) +typedef struct +{ + __IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */ + __IM uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register */ + RESERVED(0[0x3e], uint32_t) + __IOM uint32_t CONTROL; /*!< \brief Offset: 0x0100 (R/W) Control Register */ + __IOM uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control */ + RESERVED(1[0x3e], uint32_t) + __IOM uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 (R/W) Event Counter Control */ + __IOM uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration */ + __IOM uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration */ + RESERVED(2[0x2], uint32_t) + __IOM uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask */ + __IM uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status */ + __IM uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status */ + __OM uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear */ + RESERVED(3[0x143], uint32_t) + __IOM uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 (R/W) Cache Sync */ + RESERVED(4[0xf], uint32_t) + __IOM uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA */ + RESERVED(6[2], uint32_t) + __IOM uint32_t INV_WAY; /*!< \brief Offset: 0x077c (R/W) Invalidate by Way */ + RESERVED(5[0xc], uint32_t) + __IOM uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA */ + RESERVED(7[1], uint32_t) + __IOM uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way */ + __IOM uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc (R/W) Clean by Way */ + RESERVED(8[0xc], uint32_t) + __IOM uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA */ + RESERVED(9[1], uint32_t) + __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way */ + __IOM uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way */ + RESERVED(10[0x40], uint32_t) + __IOM uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way */ + __IOM uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way */ + __IOM uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way */ + __IOM uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way */ + __IOM uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way */ + __IOM uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way */ + __IOM uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way */ + __IOM uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way */ + __IOM uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way */ + __IOM uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way */ + __IOM uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way */ + __IOM uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way */ + __IOM uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way */ + __IOM uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way */ + __IOM uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way */ + __IOM uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way */ + RESERVED(11[0x4], uint32_t) + __IOM uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable */ + __IOM uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way */ + RESERVED(12[0xaa], uint32_t) + __IOM uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start */ + __IOM uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End */ + RESERVED(13[0xce], uint32_t) + __IOM uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register */ +} L2C_310_TypeDef; + +#define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */ +#endif + +#if (__GIC_PRESENT == 1U) || defined(DOXYGEN) + +/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */ + __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */ + RESERVED(0, uint32_t) + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */ + RESERVED(1[11], uint32_t) + __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */ + RESERVED(2, uint32_t) + __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */ + RESERVED(3, uint32_t) + __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */ + RESERVED(4, uint32_t) + __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */ + RESERVED(5[9], uint32_t) + __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */ + __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */ + __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */ + __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */ + __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */ + __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */ + __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */ + __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */ + RESERVED(6, uint32_t) + __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */ + RESERVED(7, uint32_t) + __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */ + __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */ + RESERVED(8[32], uint32_t) + __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */ + __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */ + RESERVED(9[3], uint32_t) + __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */ + __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */ + RESERVED(10[5236], uint32_t) + __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */ +} GICDistributor_Type; + +#define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */ + +/** \brief Structure type to access the Generic Interrupt Controller Interface (GICC) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */ + __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */ + __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */ + __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */ + __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */ + __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */ + __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */ + __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */ + __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */ + __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */ + __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */ + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */ + RESERVED(1[40], uint32_t) + __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */ + __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */ + RESERVED(2[3], uint32_t) + __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */ + RESERVED(3[960], uint32_t) + __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */ +} GICInterface_Type; + +#define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */ +#endif + +#if (__TIM_PRESENT == 1U) || defined(DOXYGEN) +#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) +/** \brief Structure type to access the Private Timer +*/ +typedef struct +{ + __IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register + __IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register + __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register + __IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register + RESERVED(0[4], uint32_t) + __IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register + __IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register + __IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register + __IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register + __IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register + __OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register +} Timer_Type; +#define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer register struct */ +#endif +#endif + + /******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - L1 Cache Functions + - L2C-310 Cache Controller Functions + - PL1 Timer Functions + - GIC Functions + - MMU Functions + ******************************************************************************/ + +/* ########################## L1 Cache functions ################################# */ + +/** \brief Enable Caches by setting I and C bits in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_EnableCaches(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk); + __ISB(); +} + +/** \brief Disable Caches by clearing I and C bits in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_DisableCaches(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk)); + __ISB(); +} + +/** \brief Enable Branch Prediction by setting Z bit in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_EnableBTAC(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk); + __ISB(); +} + +/** \brief Disable Branch Prediction by clearing Z bit in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_DisableBTAC(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk)); + __ISB(); +} + +/** \brief Invalidate entire branch predictor array +*/ +__STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) { + __set_BPIALL(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new state +} + +/** \brief Invalidate the whole instruction cache +*/ +__STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) { + __set_ICIALLU(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new I cache state +} + +/** \brief Clean data cache line by address. +* \param [in] va Pointer to data to clear the cache for. +*/ +__STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) { + __set_DCCMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Invalidate data cache line by address. +* \param [in] va Pointer to data to invalidate the cache for. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) { + __set_DCIMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Clean and Invalidate data cache by address. +* \param [in] va Pointer to data to invalidate the cache for. +*/ +__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) { + __set_DCCIMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Calculate log2 rounded up +* - log(0) => 0 +* - log(1) => 0 +* - log(2) => 1 +* - log(3) => 2 +* - log(4) => 2 +* - log(5) => 3 +* : : +* - log(16) => 4 +* - log(32) => 5 +* : : +* \param [in] n input value parameter +* \return log2(n) +*/ +__STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n) +{ + if (n < 2U) { + return 0U; + } + uint8_t log = 0U; + uint32_t t = n; + while(t > 1U) + { + log++; + t >>= 1U; + } + if (n & 1U) { log++; } + return log; +} + +/** \brief Apply cache maintenance to given cache level. +* \param [in] level cache level to be maintained +* \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean +*/ +__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint) +{ + uint32_t Dummy; + uint32_t ccsidr; + uint32_t num_sets; + uint32_t num_ways; + uint32_t shift_way; + uint32_t log2_linesize; + int32_t log2_num_ways; + + Dummy = level << 1U; + /* set csselr, select ccsidr register */ + __set_CSSELR(Dummy); + /* get current ccsidr register */ + ccsidr = __get_CCSIDR(); + num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U; + num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U; + log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U; + log2_num_ways = __log2_up(num_ways); + if ((log2_num_ways < 0) || (log2_num_ways > 32)) { + return; // FATAL ERROR + } + shift_way = 32U - (uint32_t)log2_num_ways; + for(int32_t way = num_ways-1; way >= 0; way--) + { + for(int32_t set = num_sets-1; set >= 0; set--) + { + Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way); + switch (maint) + { + case 0U: __set_DCISW(Dummy); break; + case 1U: __set_DCCSW(Dummy); break; + default: __set_DCCISW(Dummy); break; + } + } + } + __DMB(); +} + +/** \brief Clean and Invalidate the entire data or unified cache +* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency +* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean +*/ +__STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) { + uint32_t clidr; + uint32_t cache_type; + clidr = __get_CLIDR(); + for(uint32_t i = 0U; i<7U; i++) + { + cache_type = (clidr >> i*3U) & 0x7UL; + if ((cache_type >= 2U) && (cache_type <= 4U)) + { + __L1C_MaintainDCacheSetWay(i, op); + } + } +} + +/** \brief Clean and Invalidate the entire data or unified cache +* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency +* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean +* \deprecated Use generic L1C_CleanInvalidateCache instead. +*/ +CMSIS_DEPRECATED +__STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) { + L1C_CleanInvalidateCache(op); +} + +/** \brief Invalidate the whole data cache. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) { + L1C_CleanInvalidateCache(0); +} + +/** \brief Clean the whole data cache. + */ +__STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) { + L1C_CleanInvalidateCache(1); +} + +/** \brief Clean and invalidate the whole data cache. + */ +__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) { + L1C_CleanInvalidateCache(2); +} + +/* ########################## L2 Cache functions ################################# */ +#if (__L2C_PRESENT == 1U) || defined(DOXYGEN) +/** \brief Cache Sync operation by writing CACHE_SYNC register. +*/ +__STATIC_INLINE void L2C_Sync(void) +{ + L2C_310->CACHE_SYNC = 0x0; +} + +/** \brief Read cache controller cache ID from CACHE_ID register. + * \return L2C_310_TypeDef::CACHE_ID + */ +__STATIC_INLINE int L2C_GetID (void) +{ + return L2C_310->CACHE_ID; +} + +/** \brief Read cache controller cache type from CACHE_TYPE register. +* \return L2C_310_TypeDef::CACHE_TYPE +*/ +__STATIC_INLINE int L2C_GetType (void) +{ + return L2C_310->CACHE_TYPE; +} + +/** \brief Invalidate all cache by way +*/ +__STATIC_INLINE void L2C_InvAllByWay (void) +{ + unsigned int assoc; + + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } + + L2C_310->INV_WAY = (1U << assoc) - 1U; + while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate + + L2C_Sync(); +} + +/** \brief Clean and Invalidate all cache by way +*/ +__STATIC_INLINE void L2C_CleanInvAllByWay (void) +{ + unsigned int assoc; + + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } + + L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U; + while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate + + L2C_Sync(); +} + +/** \brief Enable Level 2 Cache +*/ +__STATIC_INLINE void L2C_Enable(void) +{ + L2C_310->CONTROL = 0; + L2C_310->INTERRUPT_CLEAR = 0x000001FFuL; + L2C_310->DEBUG_CONTROL = 0; + L2C_310->DATA_LOCK_0_WAY = 0; + L2C_310->CACHE_SYNC = 0; + L2C_310->CONTROL = 0x01; + L2C_Sync(); +} + +/** \brief Disable Level 2 Cache +*/ +__STATIC_INLINE void L2C_Disable(void) +{ + L2C_310->CONTROL = 0x00; + L2C_Sync(); +} + +/** \brief Invalidate cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_InvPa (void *pa) +{ + L2C_310->INV_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} + +/** \brief Clean cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_CleanPa (void *pa) +{ + L2C_310->CLEAN_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} + +/** \brief Clean and invalidate cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_CleanInvPa (void *pa) +{ + L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} +#endif + +/* ########################## GIC functions ###################################### */ +#if (__GIC_PRESENT == 1U) || defined(DOXYGEN) + +/** \brief Enable the interrupt distributor using the GIC's CTLR register. +*/ +__STATIC_INLINE void GIC_EnableDistributor(void) +{ + GICDistributor->CTLR |= 1U; +} + +/** \brief Disable the interrupt distributor using the GIC's CTLR register. +*/ +__STATIC_INLINE void GIC_DisableDistributor(void) +{ + GICDistributor->CTLR &=~1U; +} + +/** \brief Read the GIC's TYPER register. +* \return GICDistributor_Type::TYPER +*/ +__STATIC_INLINE uint32_t GIC_DistributorInfo(void) +{ + return (GICDistributor->TYPER); +} + +/** \brief Reads the GIC's IIDR register. +* \return GICDistributor_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_DistributorImplementer(void) +{ + return (GICDistributor->IIDR); +} + +/** \brief Sets the GIC's ITARGETSR register for the given interrupt. +* \param [in] IRQn Interrupt to be configured. +* \param [in] cpu_target CPU interfaces to assign this interrupt to. +*/ +__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target) +{ + uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U)); +} + +/** \brief Read the GIC's ITARGETSR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return GICDistributor_Type::ITARGETSR +*/ +__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn) +{ + return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; +} + +/** \brief Enable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_EnableInterface(void) +{ + GICInterface->CTLR |= 1U; //enable interface +} + +/** \brief Disable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_DisableInterface(void) +{ + GICInterface->CTLR &=~1U; //disable distributor +} + +/** \brief Read the CPU's IAR register. +* \return GICInterface_Type::IAR +*/ +__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void) +{ + return (IRQn_Type)(GICInterface->IAR); +} + +/** \brief Writes the given interrupt number to the CPU's EOIR register. +* \param [in] IRQn The interrupt to be signaled as finished. +*/ +__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn) +{ + GICInterface->EOIR = IRQn; +} + +/** \brief Enables the given interrupt using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U); +} + +/** \brief Get interrupt enable status using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not enabled, 1 - interrupt is enabled. +*/ +__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn) +{ + return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} + +/** \brief Disables the given interrupt using GIC's ICENABLER register. +* \param [in] IRQn The interrupt to be disabled. +*/ +__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U); +} + +/** \brief Get interrupt pending status from GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not pending, 1 - interrupt is pendig. +*/ +__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn) +{ + uint32_t pend; + + if (IRQn >= 16U) { + pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; + } else { + // INTID 0-15 Software Generated Interrupt + pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; + // No CPU identification offered + if (pend != 0U) { + pend = 1U; + } else { + pend = 0U; + } + } + + return (pend); +} + +/** \brief Sets the given interrupt as pending using GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16U) { + GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + // Forward the interrupt to the CPU interface that requested it + GICDistributor->SGIR = (IRQn | 0x02000000U); + } +} + +/** \brief Clears the given interrupt from being pending using GIC's ICPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16U) { + GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); + } +} + +/** \brief Sets the interrupt configuration using GIC's ICFGR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config) +{ + uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U]; + uint32_t shift = (IRQn % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= ( int_config << shift); + + GICDistributor->ICFGR[IRQn / 16U] = icfgr; +} + +/** \brief Get the interrupt configuration from the GIC's ICFGR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn) +{ + return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U)); +} + +/** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] priority The priority for the interrupt, lower values denote higher priorities. +*/ +__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U)); +} + +/** \brief Read the current interrupt priority from GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be queried. +*/ +__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn) +{ + return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; +} + +/** \brief Set the interrupt priority mask using CPU's PMR register. +* \param [in] priority Priority mask to be set. +*/ +__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority) +{ + GICInterface->PMR = priority & 0xFFUL; //set priority mask +} + +/** \brief Read the current interrupt priority mask from CPU's PMR register. +* \result GICInterface_Type::PMR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void) +{ + return GICInterface->PMR; +} + +/** \brief Configures the group priority and subpriority split point using CPU's BPR register. +* \param [in] binary_point Amount of bits used as subpriority. +*/ +__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point) +{ + GICInterface->BPR = binary_point & 7U; //set binary point +} + +/** \brief Read the current group priority and subpriority split point from CPU's BPR register. +* \return GICInterface_Type::BPR +*/ +__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void) +{ + return GICInterface->BPR; +} + +/** \brief Get the status for a given interrupt. +* \param [in] IRQn The interrupt to get status for. +* \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active +*/ +__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) +{ + uint32_t pending, active; + + active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + + return ((active<<1U) | pending); +} + +/** \brief Generate a software interrupt using GIC's SGIR register. +* \param [in] IRQn Software interrupt to be generated. +* \param [in] target_list List of CPUs the software interrupt should be forwarded to. +* \param [in] filter_list Filter to be applied to determine interrupt receivers. +*/ +__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list) +{ + GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL); +} + +/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. +* \return GICInterface_Type::HPPIR +*/ +__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) +{ + return GICInterface->HPPIR; +} + +/** \brief Provides information about the implementer and revision of the CPU interface. +* \return GICInterface_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfaceId(void) +{ + return GICInterface->IIDR; +} + +/** \brief Set the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group) +{ + uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U]; + uint32_t shift = (IRQn % 32U); + + igroupr &= (~(1U << shift)); + igroupr |= ( (group & 1U) << shift); + + GICDistributor->IGROUPR[IRQn / 32U] = igroupr; +} +#define GIC_SetSecurity GIC_SetGroup + +/** \brief Get the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn) +{ + return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} +#define GIC_GetSecurity GIC_GetGroup + +/** \brief Initialize the interrupt distributor. +*/ +__STATIC_INLINE void GIC_DistInit(void) +{ + uint32_t i; + uint32_t num_irq = 0U; + uint32_t priority_field; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableDistributor(); + //Get the maximum number of interrupts that the GIC supports + num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); + + for (i = 32U; i < num_irq; i++) + { + //Disable the SPI interrupt + GIC_DisableIRQ((IRQn_Type)i); + //Set level-sensitive (and N-N model) + GIC_SetConfiguration((IRQn_Type)i, 0U); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field/2U); + //Set target list to CPU0 + GIC_SetTarget((IRQn_Type)i, 1U); + } + //Enable distributor + GIC_EnableDistributor(); +} + +/** \brief Initialize the CPU's interrupt interface +*/ +__STATIC_INLINE void GIC_CPUInterfaceInit(void) +{ + uint32_t i; + uint32_t priority_field; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableInterface(); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); + + //SGI and PPI + for (i = 0U; i < 32U; i++) + { + if(i > 15U) { + //Set level-sensitive (and N-N model) for PPI + GIC_SetConfiguration((IRQn_Type)i, 0U); + } + //Disable SGI and PPI interrupts + GIC_DisableIRQ((IRQn_Type)i); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field/2U); + } + //Enable interface + GIC_EnableInterface(); + //Set binary point to 0 + GIC_SetBinaryPoint(0U); + //Set priority mask + GIC_SetInterfacePriorityMask(0xFFU); +} + +/** \brief Initialize and enable the GIC +*/ +__STATIC_INLINE void GIC_Enable(void) +{ + GIC_DistInit(); + GIC_CPUInterfaceInit(); //per CPU +} +#endif + +/* ########################## Generic Timer functions ############################ */ +#if (__TIM_PRESENT == 1U) || defined(DOXYGEN) + +/* PL1 Physical Timer */ +#if (__CORTEX_A == 7U) || defined(DOXYGEN) + +/** \brief Physical Timer Control register */ +typedef union +{ + struct + { + uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */ + uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */ + uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */ + RESERVED(0:29, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CNTP_CTL_Type; + +/** \brief Configures the frequency the timer shall run at. +* \param [in] value The timer frequency in Hz. +*/ +__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value) +{ + __set_CNTFRQ(value); + __ISB(); +} + +/** \brief Sets the reset value of the timer. +* \param [in] value The value the timer is loaded with. +*/ +__STATIC_INLINE void PL1_SetLoadValue(uint32_t value) +{ + __set_CNTP_TVAL(value); + __ISB(); +} + +/** \brief Get the current counter value. +* \return Current counter value. +*/ +__STATIC_INLINE uint32_t PL1_GetCurrentValue(void) +{ + return(__get_CNTP_TVAL()); +} + +/** \brief Get the current physical counter value. +* \return Current physical counter value. +*/ +__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void) +{ + return(__get_CNTPCT()); +} + +/** \brief Set the physical compare value. +* \param [in] value New physical timer compare value. +*/ +__STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value) +{ + __set_CNTP_CVAL(value); + __ISB(); +} + +/** \brief Get the physical compare value. +* \return Physical compare value. +*/ +__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void) +{ + return(__get_CNTP_CVAL()); +} + +/** \brief Configure the timer by setting the control value. +* \param [in] value New timer control value. +*/ +__STATIC_INLINE void PL1_SetControl(uint32_t value) +{ + __set_CNTP_CTL(value); + __ISB(); +} + +/** \brief Get the control value. +* \return Control value. +*/ +__STATIC_INLINE uint32_t PL1_GetControl(void) +{ + return(__get_CNTP_CTL()); +} +#endif + +/* Private Timer */ +#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) +/** \brief Set the load value to timers LOAD register. +* \param [in] value The load value to be set. +*/ +__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) +{ + PTIM->LOAD = value; +} + +/** \brief Get the load value from timers LOAD register. +* \return Timer_Type::LOAD +*/ +__STATIC_INLINE uint32_t PTIM_GetLoadValue(void) +{ + return(PTIM->LOAD); +} + +/** \brief Set current counter value from its COUNTER register. +*/ +__STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value) +{ + PTIM->COUNTER = value; +} + +/** \brief Get current counter value from timers COUNTER register. +* \result Timer_Type::COUNTER +*/ +__STATIC_INLINE uint32_t PTIM_GetCurrentValue(void) +{ + return(PTIM->COUNTER); +} + +/** \brief Configure the timer using its CONTROL register. +* \param [in] value The new configuration value to be set. +*/ +__STATIC_INLINE void PTIM_SetControl(uint32_t value) +{ + PTIM->CONTROL = value; +} + +/** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register. +* \return Timer_Type::CONTROL +*/ +__STATIC_INLINE uint32_t PTIM_GetControl(void) +{ + return(PTIM->CONTROL); +} + +/** ref Timer_Type::CONTROL Get the event flag in timers ISR register. +* \return 0 - flag is not set, 1- flag is set +*/ +__STATIC_INLINE uint32_t PTIM_GetEventFlag(void) +{ + return (PTIM->ISR & 1UL); +} + +/** ref Timer_Type::CONTROL Clears the event flag in timers ISR register. +*/ +__STATIC_INLINE void PTIM_ClearEventFlag(void) +{ + PTIM->ISR = 1; +} +#endif +#endif + +/* ########################## MMU functions ###################################### */ + +#define SECTION_DESCRIPTOR (0x2) +#define SECTION_MASK (0xFFFFFFFC) + +#define SECTION_TEXCB_MASK (0xFFFF8FF3) +#define SECTION_B_SHIFT (2) +#define SECTION_C_SHIFT (3) +#define SECTION_TEX0_SHIFT (12) +#define SECTION_TEX1_SHIFT (13) +#define SECTION_TEX2_SHIFT (14) + +#define SECTION_XN_MASK (0xFFFFFFEF) +#define SECTION_XN_SHIFT (4) + +#define SECTION_DOMAIN_MASK (0xFFFFFE1F) +#define SECTION_DOMAIN_SHIFT (5) + +#define SECTION_P_MASK (0xFFFFFDFF) +#define SECTION_P_SHIFT (9) + +#define SECTION_AP_MASK (0xFFFF73FF) +#define SECTION_AP_SHIFT (10) +#define SECTION_AP2_SHIFT (15) + +#define SECTION_S_MASK (0xFFFEFFFF) +#define SECTION_S_SHIFT (16) + +#define SECTION_NG_MASK (0xFFFDFFFF) +#define SECTION_NG_SHIFT (17) + +#define SECTION_NS_MASK (0xFFF7FFFF) +#define SECTION_NS_SHIFT (19) + +#define PAGE_L1_DESCRIPTOR (0x1) +#define PAGE_L1_MASK (0xFFFFFFFC) + +#define PAGE_L2_4K_DESC (0x2) +#define PAGE_L2_4K_MASK (0xFFFFFFFD) + +#define PAGE_L2_64K_DESC (0x1) +#define PAGE_L2_64K_MASK (0xFFFFFFFC) + +#define PAGE_4K_TEXCB_MASK (0xFFFFFE33) +#define PAGE_4K_B_SHIFT (2) +#define PAGE_4K_C_SHIFT (3) +#define PAGE_4K_TEX0_SHIFT (6) +#define PAGE_4K_TEX1_SHIFT (7) +#define PAGE_4K_TEX2_SHIFT (8) + +#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3) +#define PAGE_64K_B_SHIFT (2) +#define PAGE_64K_C_SHIFT (3) +#define PAGE_64K_TEX0_SHIFT (12) +#define PAGE_64K_TEX1_SHIFT (13) +#define PAGE_64K_TEX2_SHIFT (14) + +#define PAGE_TEXCB_MASK (0xFFFF8FF3) +#define PAGE_B_SHIFT (2) +#define PAGE_C_SHIFT (3) +#define PAGE_TEX_SHIFT (12) + +#define PAGE_XN_4K_MASK (0xFFFFFFFE) +#define PAGE_XN_4K_SHIFT (0) +#define PAGE_XN_64K_MASK (0xFFFF7FFF) +#define PAGE_XN_64K_SHIFT (15) + +#define PAGE_DOMAIN_MASK (0xFFFFFE1F) +#define PAGE_DOMAIN_SHIFT (5) + +#define PAGE_P_MASK (0xFFFFFDFF) +#define PAGE_P_SHIFT (9) + +#define PAGE_AP_MASK (0xFFFFFDCF) +#define PAGE_AP_SHIFT (4) +#define PAGE_AP2_SHIFT (9) + +#define PAGE_S_MASK (0xFFFFFBFF) +#define PAGE_S_SHIFT (10) + +#define PAGE_NG_MASK (0xFFFFF7FF) +#define PAGE_NG_SHIFT (11) + +#define PAGE_NS_MASK (0xFFFFFFF7) +#define PAGE_NS_SHIFT (3) + +#define OFFSET_1M (0x00100000) +#define OFFSET_64K (0x00010000) +#define OFFSET_4K (0x00001000) + +#define DESCRIPTOR_FAULT (0x00000000) + +/* Attributes enumerations */ + +/* Region size attributes */ +typedef enum +{ + SECTION, + PAGE_4k, + PAGE_64k, +} mmu_region_size_Type; + +/* Region type attributes */ +typedef enum +{ + NORMAL, + DEVICE, + SHARED_DEVICE, + NON_SHARED_DEVICE, + STRONGLY_ORDERED +} mmu_memory_Type; + +/* Region cacheability attributes */ +typedef enum +{ + NON_CACHEABLE, + WB_WA, + WT, + WB_NO_WA, +} mmu_cacheability_Type; + +/* Region parity check attributes */ +typedef enum +{ + ECC_DISABLED, + ECC_ENABLED, +} mmu_ecc_check_Type; + +/* Region execution attributes */ +typedef enum +{ + EXECUTE, + NON_EXECUTE, +} mmu_execute_Type; + +/* Region global attributes */ +typedef enum +{ + GLOBAL, + NON_GLOBAL, +} mmu_global_Type; + +/* Region shareability attributes */ +typedef enum +{ + NON_SHARED, + SHARED, +} mmu_shared_Type; + +/* Region security attributes */ +typedef enum +{ + SECURE, + NON_SECURE, +} mmu_secure_Type; + +/* Region access attributes */ +typedef enum +{ + NO_ACCESS, + RW, + READ, +} mmu_access_Type; + +/* Memory Region definition */ +typedef struct RegionStruct { + mmu_region_size_Type rg_t; + mmu_memory_Type mem_t; + uint8_t domain; + mmu_cacheability_Type inner_norm_t; + mmu_cacheability_Type outer_norm_t; + mmu_ecc_check_Type e_t; + mmu_execute_Type xn_t; + mmu_global_Type g_t; + mmu_secure_Type sec_t; + mmu_access_Type priv_t; + mmu_access_Type user_t; + mmu_shared_Type sh_t; + +} mmu_region_attributes_Type; + +//Following macros define the descriptors and attributes +//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0 +#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0 +#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0 +#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_RO. Sect_Normal_Cod, but not executable +#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable +#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); +//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 +#define section_so(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0 +#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Device_RW. Sect_Device_RO, but writeable +#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); +//Page_4k_Device_RW. Shared device, not executable, rw, domain 0 +#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); + +//Page_64k_Device_RW. Shared device, not executable, rw, domain 0 +#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); + +/** \brief Set section execution-never attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE. + + \return 0 +*/ +__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn) +{ + *descriptor_l1 &= SECTION_XN_MASK; + *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT); + return 0; +} + +/** \brief Set section domain + + \param [out] descriptor_l1 L1 descriptor. + \param [in] domain Section domain + + \return 0 +*/ +__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain) +{ + *descriptor_l1 &= SECTION_DOMAIN_MASK; + *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT); + return 0; +} + +/** \brief Set section parity check + + \param [out] descriptor_l1 L1 descriptor. + \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED + + \return 0 +*/ +__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) +{ + *descriptor_l1 &= SECTION_P_MASK; + *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); + return 0; +} + +/** \brief Set section access privileges + + \param [out] descriptor_l1 L1 descriptor. + \param [in] user User Level Access: NO_ACCESS, RW, READ + \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ + \param [in] afe Access flag enable + + \return 0 +*/ +__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) +{ + uint32_t ap = 0; + + if (afe == 0) { //full access + if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } + else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == READ)) { ap = 0x2; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + else { //Simplified access + if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + *descriptor_l1 &= SECTION_AP_MASK; + *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT; + *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT; + + return 0; +} + +/** \brief Set section shareability + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit Section shareability: NON_SHARED, SHARED + + \return 0 +*/ +__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit) +{ + *descriptor_l1 &= SECTION_S_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT); + return 0; +} + +/** \brief Set section Global attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL + + \return 0 +*/ +__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit) +{ + *descriptor_l1 &= SECTION_NG_MASK; + *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT); + return 0; +} + +/** \brief Set section Security attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit Section Security attribute: SECURE, NON_SECURE + + \return 0 +*/ +__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit) +{ + *descriptor_l1 &= SECTION_NS_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT); + return 0; +} + +/* Page 4k or 64k */ +/** \brief Set 4k/64k page execution-never attribute + + \param [out] descriptor_l2 L2 descriptor. + \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE. + \param [in] page Page size: PAGE_4k, PAGE_64k, + + \return 0 +*/ +__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page) +{ + if (page == PAGE_4k) + { + *descriptor_l2 &= PAGE_XN_4K_MASK; + *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT); + } + else + { + *descriptor_l2 &= PAGE_XN_64K_MASK; + *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT); + } + return 0; +} + +/** \brief Set 4k/64k page domain + + \param [out] descriptor_l1 L1 descriptor. + \param [in] domain Page domain + + \return 0 +*/ +__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain) +{ + *descriptor_l1 &= PAGE_DOMAIN_MASK; + *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page parity check + + \param [out] descriptor_l1 L1 descriptor. + \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED + + \return 0 +*/ +__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) +{ + *descriptor_l1 &= SECTION_P_MASK; + *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page access privileges + + \param [out] descriptor_l2 L2 descriptor. + \param [in] user User Level Access: NO_ACCESS, RW, READ + \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ + \param [in] afe Access flag enable + + \return 0 +*/ +__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) +{ + uint32_t ap = 0; + + if (afe == 0) { //full access + if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } + else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == READ)) { ap = 0x2; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x6; } + } + + else { //Simplified access + if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + *descriptor_l2 &= PAGE_AP_MASK; + *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT; + *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT; + + return 0; +} + +/** \brief Set 4k/64k page shareability + + \param [out] descriptor_l2 L2 descriptor. + \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED + + \return 0 +*/ +__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit) +{ + *descriptor_l2 &= PAGE_S_MASK; + *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page Global attribute + + \param [out] descriptor_l2 L2 descriptor. + \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL + + \return 0 +*/ +__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit) +{ + *descriptor_l2 &= PAGE_NG_MASK; + *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page Security attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE + + \return 0 +*/ +__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit) +{ + *descriptor_l1 &= PAGE_NS_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT); + return 0; +} + +/** \brief Set Section memory attributes + + \param [out] descriptor_l1 L1 descriptor. + \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED + \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + + \return 0 +*/ +__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner) +{ + *descriptor_l1 &= SECTION_TEXCB_MASK; + + if (STRONGLY_ORDERED == mem) + { + return 0; + } + else if (SHARED_DEVICE == mem) + { + *descriptor_l1 |= (1 << SECTION_B_SHIFT); + } + else if (NON_SHARED_DEVICE == mem) + { + *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT); + } + else if (NORMAL == mem) + { + *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT; + switch(inner) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l1 |= (1 << SECTION_B_SHIFT); + break; + case WT: + *descriptor_l1 |= 1 << SECTION_C_SHIFT; + break; + case WB_NO_WA: + *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT); + break; + } + switch(outer) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT); + break; + case WT: + *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT; + break; + case WB_NO_WA: + *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT); + break; + } + } + return 0; +} + +/** \brief Set 4k/64k page memory attributes + + \param [out] descriptor_l2 L2 descriptor. + \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED + \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] page Page size + + \return 0 +*/ +__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page) +{ + *descriptor_l2 &= PAGE_4K_TEXCB_MASK; + + if (page == PAGE_64k) + { + //same as section + MMU_MemorySection(descriptor_l2, mem, outer, inner); + } + else + { + if (STRONGLY_ORDERED == mem) + { + return 0; + } + else if (SHARED_DEVICE == mem) + { + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); + } + else if (NON_SHARED_DEVICE == mem) + { + *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT); + } + else if (NORMAL == mem) + { + *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT; + switch(inner) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); + break; + case WT: + *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT; + break; + case WB_NO_WA: + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT); + break; + } + switch(outer) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT); + break; + case WT: + *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT; + break; + case WB_NO_WA: + *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT); + break; + } + } + } + + return 0; +} + +/** \brief Create a L1 section descriptor + + \param [out] descriptor L1 descriptor + \param [in] reg Section attributes + + \return 0 +*/ +__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg) +{ + *descriptor = 0; + + MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t); + MMU_XNSection(descriptor,reg.xn_t); + MMU_DomainSection(descriptor, reg.domain); + MMU_PSection(descriptor, reg.e_t); + MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1); + MMU_SharedSection(descriptor,reg.sh_t); + MMU_GlobalSection(descriptor,reg.g_t); + MMU_SecureSection(descriptor,reg.sec_t); + *descriptor &= SECTION_MASK; + *descriptor |= SECTION_DESCRIPTOR; + + return 0; +} + + +/** \brief Create a L1 and L2 4k/64k page descriptor + + \param [out] descriptor L1 descriptor + \param [out] descriptor2 L2 descriptor + \param [in] reg 4k/64k page attributes + + \return 0 +*/ +__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg) +{ + *descriptor = 0; + *descriptor2 = 0; + + switch (reg.rg_t) + { + case PAGE_4k: + MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k); + MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k); + MMU_DomainPage(descriptor, reg.domain); + MMU_PPage(descriptor, reg.e_t); + MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1); + MMU_SharedPage(descriptor2,reg.sh_t); + MMU_GlobalPage(descriptor2,reg.g_t); + MMU_SecurePage(descriptor,reg.sec_t); + *descriptor &= PAGE_L1_MASK; + *descriptor |= PAGE_L1_DESCRIPTOR; + *descriptor2 &= PAGE_L2_4K_MASK; + *descriptor2 |= PAGE_L2_4K_DESC; + break; + + case PAGE_64k: + MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k); + MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k); + MMU_DomainPage(descriptor, reg.domain); + MMU_PPage(descriptor, reg.e_t); + MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1); + MMU_SharedPage(descriptor2,reg.sh_t); + MMU_GlobalPage(descriptor2,reg.g_t); + MMU_SecurePage(descriptor,reg.sec_t); + *descriptor &= PAGE_L1_MASK; + *descriptor |= PAGE_L1_DESCRIPTOR; + *descriptor2 &= PAGE_L2_64K_MASK; + *descriptor2 |= PAGE_L2_64K_DESC; + break; + + case SECTION: + //error + break; + } + + return 0; +} + +/** \brief Create a 1MB Section + + \param [in] ttb Translation table base address + \param [in] base_address Section base address + \param [in] count Number of sections to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1) +{ + uint32_t offset; + uint32_t entry; + uint32_t i; + + offset = base_address >> 20; + entry = (base_address & 0xFFF00000) | descriptor_l1; + + //4 bytes aligned + ttb = ttb + offset; + + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb++ = entry; + entry += OFFSET_1M; + } +} + +/** \brief Create a 4k page entry + + \param [in] ttb L1 table base address + \param [in] base_address 4k base address + \param [in] count Number of 4k pages to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + \param [in] ttb_l2 L2 table base address + \param [in] descriptor_l2 L2 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) +{ + + uint32_t offset, offset2; + uint32_t entry, entry2; + uint32_t i; + + offset = base_address >> 20; + entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; + + //4 bytes aligned + ttb += offset; + //create l1_entry + *ttb = entry; + + offset2 = (base_address & 0xff000) >> 12; + ttb_l2 += offset2; + entry2 = (base_address & 0xFFFFF000) | descriptor_l2; + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb_l2++ = entry2; + entry2 += OFFSET_4K; + } +} + +/** \brief Create a 64k page entry + + \param [in] ttb L1 table base address + \param [in] base_address 64k base address + \param [in] count Number of 64k pages to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + \param [in] ttb_l2 L2 table base address + \param [in] descriptor_l2 L2 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) +{ + uint32_t offset, offset2; + uint32_t entry, entry2; + uint32_t i,j; + + + offset = base_address >> 20; + entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; + + //4 bytes aligned + ttb += offset; + //create l1_entry + *ttb = entry; + + offset2 = (base_address & 0xff000) >> 12; + ttb_l2 += offset2; + entry2 = (base_address & 0xFFFF0000) | descriptor_l2; + for (i = 0; i < count; i++ ) + { + //create 16 entries + for (j = 0; j < 16; j++) + { + //4 bytes aligned + *ttb_l2++ = entry2; + } + entry2 += OFFSET_64K; + } +} + +/** \brief Enable MMU +*/ +__STATIC_INLINE void MMU_Enable(void) +{ + // Set M bit 0 to enable the MMU + // Set AFE bit to enable simplified access permissions model + // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking + __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); + __ISB(); +} + +/** \brief Disable MMU +*/ +__STATIC_INLINE void MMU_Disable(void) +{ + // Clear M bit 0 to disable the MMU + __set_SCTLR( __get_SCTLR() & ~1); + __ISB(); +} + +/** \brief Invalidate entire unified TLB +*/ + +__STATIC_INLINE void MMU_InvalidateTLB(void) +{ + __set_TLBIALL(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new state +} + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/interface/Drivers/CMSIS/Core_A/Include/irq_ctrl.h b/benchmark/interface/Drivers/CMSIS/Core_A/Include/irq_ctrl.h new file mode 100644 index 00000000..1ca29a27 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core_A/Include/irq_ctrl.h @@ -0,0 +1,192 @@ +/**************************************************************************//** + * @file irq_ctrl.h + * @brief Interrupt Controller API header file + * @version V1.1.0 + * @date 03. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef IRQ_CTRL_H_ +#define IRQ_CTRL_H_ + +#include + +#ifndef IRQHANDLER_T +#define IRQHANDLER_T +/// Interrupt handler data type +typedef void (*IRQHandler_t) (void); +#endif + +#ifndef IRQN_ID_T +#define IRQN_ID_T +/// Interrupt ID number data type +typedef int32_t IRQn_ID_t; +#endif + +/* Interrupt mode bit-masks */ +#define IRQ_MODE_TRIG_Pos (0U) +#define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) +#define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt +#define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt +#define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt +#define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt + +#define IRQ_MODE_TYPE_Pos (3U) +#define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos) +#define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line +#define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line + +#define IRQ_MODE_DOMAIN_Pos (4U) +#define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos) +#define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain +#define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain + +#define IRQ_MODE_CPU_Pos (5U) +#define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos) +#define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs +#define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0 +#define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1 +#define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2 +#define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3 +#define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4 +#define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5 +#define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6 +#define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7 + +// Encoding in some early GIC implementations +#define IRQ_MODE_MODEL_Pos (13U) +#define IRQ_MODE_MODEL_Msk (0x1UL << IRQ_MODE_MODEL_Pos) +#define IRQ_MODE_MODEL_NN (0x0UL << IRQ_MODE_MODEL_Pos) ///< Corresponding interrupt is handled using the N-N model +#define IRQ_MODE_MODEL_1N (0x1UL << IRQ_MODE_MODEL_Pos) ///< Corresponding interrupt is handled using the 1-N model + +#define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error + +/* Interrupt priority bit-masks */ +#define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask +#define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error + +/// Initialize interrupt controller. +/// \return 0 on success, -1 on error. +int32_t IRQ_Initialize (void); + +/// Register interrupt handler. +/// \param[in] irqn interrupt ID number +/// \param[in] handler interrupt handler function address +/// \return 0 on success, -1 on error. +int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler); + +/// Get the registered interrupt handler. +/// \param[in] irqn interrupt ID number +/// \return registered interrupt handler function address. +IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn); + +/// Enable interrupt. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_Enable (IRQn_ID_t irqn); + +/// Disable interrupt. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_Disable (IRQn_ID_t irqn); + +/// Get interrupt enable state. +/// \param[in] irqn interrupt ID number +/// \return 0 - interrupt is disabled, 1 - interrupt is enabled. +uint32_t IRQ_GetEnableState (IRQn_ID_t irqn); + +/// Configure interrupt request mode. +/// \param[in] irqn interrupt ID number +/// \param[in] mode mode configuration +/// \return 0 on success, -1 on error. +int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode); + +/// Get interrupt mode configuration. +/// \param[in] irqn interrupt ID number +/// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set. +uint32_t IRQ_GetMode (IRQn_ID_t irqn); + +/// Get ID number of current interrupt request (IRQ). +/// \return interrupt ID number. +IRQn_ID_t IRQ_GetActiveIRQ (void); + +/// Get ID number of current fast interrupt request (FIQ). +/// \return interrupt ID number. +IRQn_ID_t IRQ_GetActiveFIQ (void); + +/// Signal end of interrupt processing. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn); + +/// Set interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPending (IRQn_ID_t irqn); + +/// Get interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 - interrupt is not pending, 1 - interrupt is pending. +uint32_t IRQ_GetPending (IRQn_ID_t irqn); + +/// Clear interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_ClearPending (IRQn_ID_t irqn); + +/// Set interrupt priority value. +/// \param[in] irqn interrupt ID number +/// \param[in] priority interrupt priority value +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority); + +/// Get interrupt priority. +/// \param[in] irqn interrupt ID number +/// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriority (IRQn_ID_t irqn); + +/// Set priority masking threshold. +/// \param[in] priority priority masking threshold value +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriorityMask (uint32_t priority); + +/// Get priority masking threshold +/// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriorityMask (void); + +/// Set priority grouping field split point +/// \param[in] bits number of MSB bits included in the group priority field comparison +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriorityGroupBits (uint32_t bits); + +/// Get priority grouping field split point +/// \return current number of MSB bits included in the group priority field comparison with +/// optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriorityGroupBits (void); + +#endif // IRQ_CTRL_H_ diff --git a/benchmark/interface/Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c b/benchmark/interface/Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c new file mode 100644 index 00000000..15588bff --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c @@ -0,0 +1,418 @@ +/**************************************************************************//** + * @file irq_ctrl_gic.c + * @brief Interrupt controller handling implementation for GIC + * @version V1.1.1 + * @date 29. March 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +#include "RTE_Components.h" +#include CMSIS_device_header + +#include "irq_ctrl.h" + +#if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U) + +/// Number of implemented interrupt lines +#ifndef IRQ_GIC_LINE_COUNT +#define IRQ_GIC_LINE_COUNT (1020U) +#endif + +static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U }; +static uint32_t IRQ_ID0; + +/// Initialize interrupt controller. +__WEAK int32_t IRQ_Initialize (void) { + uint32_t i; + + for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) { + IRQTable[i] = (IRQHandler_t)NULL; + } + GIC_Enable(); + return (0); +} + + +/// Register interrupt handler. +__WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + IRQTable[irqn] = handler; + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get the registered interrupt handler. +__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) { + IRQHandler_t h; + + // Ignore CPUID field (software generated interrupts) + irqn &= 0x3FFU; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + h = IRQTable[irqn]; + } else { + h = (IRQHandler_t)0; + } + + return (h); +} + + +/// Enable interrupt. +__WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_EnableIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Disable interrupt. +__WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_DisableIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get interrupt enable state. +__WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) { + uint32_t enable; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + enable = GIC_GetEnableIRQ((IRQn_Type)irqn); + } else { + enable = 0U; + } + + return (enable); +} + + +/// Configure interrupt request mode. +__WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) { + uint32_t val; + uint8_t cfg; + uint8_t secure; + uint8_t cpu; + int32_t status = 0; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + // Check triggering mode + val = (mode & IRQ_MODE_TRIG_Msk); + + if (val == IRQ_MODE_TRIG_LEVEL) { + cfg = 0x00U; + } else if (val == IRQ_MODE_TRIG_EDGE) { + cfg = 0x02U; + } else { + cfg = 0x00U; + status = -1; + } + + val = (mode & IRQ_MODE_MODEL_Msk); + if (val == IRQ_MODE_MODEL_1N) { + cfg |= 1; // 1-N model + } + + // Check interrupt type + val = mode & IRQ_MODE_TYPE_Msk; + + if (val != IRQ_MODE_TYPE_IRQ) { + status = -1; + } + + // Check interrupt domain + val = mode & IRQ_MODE_DOMAIN_Msk; + + if (val == IRQ_MODE_DOMAIN_NONSECURE) { + secure = 0U; + } else { + // Check security extensions support + val = GIC_DistributorInfo() & (1UL << 10U); + + if (val != 0U) { + // Security extensions are supported + secure = 1U; + } else { + secure = 0U; + status = -1; + } + } + + // Check interrupt CPU targets + val = mode & IRQ_MODE_CPU_Msk; + + if (val == IRQ_MODE_CPU_ALL) { + cpu = 0xFFU; + } else { + cpu = (uint8_t)(val >> IRQ_MODE_CPU_Pos); + } + + // Apply configuration if no mode error + if (status == 0) { + GIC_SetConfiguration((IRQn_Type)irqn, cfg); + GIC_SetTarget ((IRQn_Type)irqn, cpu); + + if (secure != 0U) { + GIC_SetGroup ((IRQn_Type)irqn, secure); + } + } + } + + return (status); +} + + +/// Get interrupt mode configuration. +__WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) { + uint32_t mode; + uint32_t val; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + mode = IRQ_MODE_TYPE_IRQ; + + // Get trigger mode + val = GIC_GetConfiguration((IRQn_Type)irqn); + + if ((val & 2U) != 0U) { + // Corresponding interrupt is edge triggered + mode |= IRQ_MODE_TRIG_EDGE; + } else { + // Corresponding interrupt is level triggered + mode |= IRQ_MODE_TRIG_LEVEL; + } + + if (val & 1U) { + mode |= IRQ_MODE_MODEL_1N; + } + // Get interrupt CPU targets + mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos; + + } else { + mode = IRQ_MODE_ERROR; + } + + return (mode); +} + + +/// Get ID number of current interrupt request (IRQ). +__WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) { + IRQn_ID_t irqn; + uint32_t prio; + + /* Dummy read to avoid GIC 390 errata 801120 */ + GIC_GetHighPendingIRQ(); + + irqn = GIC_AcknowledgePending(); + + __DSB(); + + /* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014) */ + /* The following workaround code is for a single-core system. It would be */ + /* different in a multi-core system. */ + /* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */ + /* so unlock it, otherwise service the interrupt as normal. */ + /* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2 */ + /* so will not occur here. */ + + if ((irqn == 0) || (irqn >= 0x3FE)) { + /* Unlock the CPU interface with a dummy write to Interrupt Priority Register */ + prio = GIC_GetPriority((IRQn_Type)0); + GIC_SetPriority ((IRQn_Type)0, prio); + + __DSB(); + + if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) { + /* If the ID is 0, is active and has not been seen before */ + IRQ_ID0 = 1U; + } + /* End of Workaround GIC 390 errata 733075 */ + } + + return (irqn); +} + + +/// Get ID number of current fast interrupt request (FIQ). +__WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) { + return ((IRQn_ID_t)-1); +} + + +/// Signal end of interrupt processing. +__WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) { + int32_t status; + IRQn_Type irq = (IRQn_Type)irqn; + + irqn &= 0x3FFU; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_EndInterrupt (irq); + + if (irqn == 0) { + IRQ_ID0 = 0U; + } + + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Set interrupt pending flag. +__WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_SetPendingIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + +/// Get interrupt pending flag. +__WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) { + uint32_t pending; + + if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + pending = GIC_GetPendingIRQ ((IRQn_Type)irqn); + } else { + pending = 0U; + } + + return (pending & 1U); +} + + +/// Clear interrupt pending flag. +__WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_ClearPendingIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Set interrupt priority value. +__WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_SetPriority ((IRQn_Type)irqn, priority); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get interrupt priority. +__WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) { + uint32_t priority; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + priority = GIC_GetPriority ((IRQn_Type)irqn); + } else { + priority = IRQ_PRIORITY_ERROR; + } + + return (priority); +} + + +/// Set priority masking threshold. +__WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) { + GIC_SetInterfacePriorityMask (priority); + return (0); +} + + +/// Get priority masking threshold +__WEAK uint32_t IRQ_GetPriorityMask (void) { + return GIC_GetInterfacePriorityMask(); +} + + +/// Set priority grouping field split point +__WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) { + int32_t status; + + if (bits == IRQ_PRIORITY_Msk) { + bits = 7U; + } + + if (bits < 8U) { + GIC_SetBinaryPoint (7U - bits); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get priority grouping field split point +__WEAK uint32_t IRQ_GetPriorityGroupBits (void) { + uint32_t bp; + + bp = GIC_GetBinaryPoint() & 0x07U; + + return (7U - bp); +} + +#endif diff --git a/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Config/DAP_config.h b/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Config/DAP_config.h new file mode 100644 index 00000000..5e62cf40 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Config/DAP_config.h @@ -0,0 +1,561 @@ +/* + * Copyright (c) 2013-2021 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 16. June 2021 + * $Revision: V2.1.0 + * + * Project: CMSIS-DAP Configuration + * Title: DAP_config.h CMSIS-DAP Configuration File (Template) + * + *---------------------------------------------------------------------------*/ + +#ifndef __DAP_CONFIG_H__ +#define __DAP_CONFIG_H__ + + +//************************************************************************************************** +/** +\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information +\ingroup DAP_ConfigIO_gr +@{ +Provides definitions about the hardware and configuration of the Debug Unit. + +This information includes: + - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit. + - Debug Unit Identification strings (Vendor, Product, Serial Number). + - Debug Unit communication packet size. + - Debug Access Port supported modes and settings (JTAG/SWD and SWO). + - Optional information about a connected Target Device (for Evaluation Boards). +*/ + +#ifdef _RTE_ +#include "RTE_Components.h" +#include CMSIS_device_header +#else +#include "device.h" // Debug Unit Cortex-M Processor Header File +#endif + +/// Processor Clock of the Cortex-M MCU used in the Debug Unit. +/// This value is used to calculate the SWD/JTAG clock speed. +#define CPU_CLOCK 100000000U ///< Specifies the CPU Clock in Hz. + +/// Number of processor cycles for I/O Port write operations. +/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O +/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors +/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses +/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be +/// required. +#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0. + +/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available. + +/// Indicate that JTAG communication mode is available at the Debug Port. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_JTAG 1 ///< JTAG Mode: 1 = available, 0 = not available. + +/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port. +/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255. +#define DAP_JTAG_DEV_CNT 8U ///< Maximum number of JTAG devices on scan chain. + +/// Default communication mode on the Debug Access Port. +/// Used for the command \ref DAP_Connect when Port Default mode is selected. +#define DAP_DEFAULT_PORT 1U ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG. + +/// Default communication speed on the Debug Access Port for SWD and JTAG mode. +/// Used to initialize the default SWD/JTAG clock frequency. +/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting. +#define DAP_DEFAULT_SWJ_CLOCK 1000000U ///< Default SWD/JTAG clock frequency in Hz. + +/// Maximum Package Size for Command and Response data. +/// This configuration settings is used to optimize the communication performance with the +/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB, +/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB. +#define DAP_PACKET_SIZE 512U ///< Specifies Packet Size in bytes. + +/// Maximum Package Buffers for Command and Response data. +/// This configuration settings is used to optimize the communication performance with the +/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the +/// setting can be reduced (valid range is 1 .. 255). +#define DAP_PACKET_COUNT 8U ///< Specifies number of packets buffered. + +/// Indicate that UART Serial Wire Output (SWO) trace is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define SWO_UART 1 ///< SWO UART: 1 = available, 0 = not available. + +/// USART Driver instance number for the UART SWO. +#define SWO_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#). + +/// Maximum SWO UART Baudrate. +#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz. + +/// Indicate that Manchester Serial Wire Output (SWO) trace is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available. + +/// SWO Trace Buffer Size. +#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n). + +/// SWO Streaming Trace. +#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available. + +/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. +#define TIMESTAMP_CLOCK 100000000U ///< Timestamp clock in Hz (0 = timestamps not supported). + +/// Indicate that UART Communication Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART 1 ///< DAP UART: 1 = available, 0 = not available. + +/// USART Driver instance number for the UART Communication Port. +#define DAP_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#). + +/// UART Receive Buffer Size. +#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n). + +/// UART Transmit Buffer Size. +#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n). + +/// Indicate that UART Communication via USB COM Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available. + +/// Debug Unit is connected to fixed Target Device. +/// The Debug Unit may be part of an evaluation board and always connected to a fixed +/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings +/// are stored and may be used by the debugger or IDE to configure device parameters. +#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown; + +#define TARGET_DEVICE_VENDOR "Arm" ///< String indicating the Silicon Vendor +#define TARGET_DEVICE_NAME "Cortex-M" ///< String indicating the Target Device +#define TARGET_BOARD_VENDOR "Arm" ///< String indicating the Board Vendor +#define TARGET_BOARD_NAME "Arm board" ///< String indicating the Board Name + +#if TARGET_FIXED != 0 +#include +static const char TargetDeviceVendor [] = TARGET_DEVICE_VENDOR; +static const char TargetDeviceName [] = TARGET_DEVICE_NAME; +static const char TargetBoardVendor [] = TARGET_BOARD_VENDOR; +static const char TargetBoardName [] = TARGET_BOARD_NAME; +#endif + +/** Get Vendor Name string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetVendorString (char *str) { + (void)str; + return (0U); +} + +/** Get Product Name string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetProductString (char *str) { + (void)str; + return (0U); +} + +/** Get Serial Number string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) { + (void)str; + return (0U); +} + +/** Get Target Device Vendor string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetTargetDeviceVendorString (char *str) { +#if TARGET_FIXED != 0 + uint8_t len; + + strcpy(str, TargetDeviceVendor); + len = (uint8_t)(strlen(TargetDeviceVendor) + 1U); + return (len); +#else + (void)str; + return (0U); +#endif +} + +/** Get Target Device Name string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetTargetDeviceNameString (char *str) { +#if TARGET_FIXED != 0 + uint8_t len; + + strcpy(str, TargetDeviceName); + len = (uint8_t)(strlen(TargetDeviceName) + 1U); + return (len); +#else + (void)str; + return (0U); +#endif +} + +/** Get Target Board Vendor string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetTargetBoardVendorString (char *str) { +#if TARGET_FIXED != 0 + uint8_t len; + + strcpy(str, TargetBoardVendor); + len = (uint8_t)(strlen(TargetBoardVendor) + 1U); + return (len); +#else + (void)str; + return (0U); +#endif +} + +/** Get Target Board Name string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetTargetBoardNameString (char *str) { +#if TARGET_FIXED != 0 + uint8_t len; + + strcpy(str, TargetBoardName); + len = (uint8_t)(strlen(TargetBoardName) + 1U); + return (len); +#else + (void)str; + return (0U); +#endif +} + +/** Get Product Firmware Version string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetProductFirmwareVersionString (char *str) { + (void)str; + return (0U); +} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access +\ingroup DAP_ConfigIO_gr +@{ + +Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode +and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug +interface of a device. The following I/O Pins are provided: + +JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode +---------------------------- | -------------------- | --------------------------------------------- +TCK: Test Clock | SWCLK: Clock | Output Push/Pull +TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data) +TDI: Test Data Input | | Output Push/Pull +TDO: Test Data Output | | Input +nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor +nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor + + +DAP Hardware I/O Pin Access Functions +------------------------------------- +The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to +these I/O Pins. + +For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only. +This functions are provided to achieve faster I/O that is possible with some advanced GPIO +peripherals that can independently write/read a single I/O pin without affecting any other pins +of the same I/O port. The following SWDIO I/O Pin functions are provided: + - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware. + - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware. + - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed. + - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed. +*/ + + +// Configure DAP I/O pins ------------------------------ + +/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET. +Configures the DAP Hardware I/O pins for JTAG mode: + - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level. + - TDO to input mode. +*/ +__STATIC_INLINE void PORT_JTAG_SETUP (void) { + ; +} + +/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET. +Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: + - SWCLK, SWDIO, nRESET to output mode and set to default high level. + - TDI, nTRST to HighZ mode (pins are unused in SWD mode). +*/ +__STATIC_INLINE void PORT_SWD_SETUP (void) { + ; +} + +/** Disable JTAG/SWD I/O Pins. +Disables the DAP Hardware I/O pins which configures: + - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode. +*/ +__STATIC_INLINE void PORT_OFF (void) { + ; +} + + +// SWCLK/TCK I/O pin ------------------------------------- + +/** SWCLK/TCK I/O pin: Get Input. +\return Current status of the SWCLK/TCK DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) { + return (0U); +} + +/** SWCLK/TCK I/O pin: Set Output to High. +Set the SWCLK/TCK DAP hardware I/O pin to high level. +*/ +__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) { + ; +} + +/** SWCLK/TCK I/O pin: Set Output to Low. +Set the SWCLK/TCK DAP hardware I/O pin to low level. +*/ +__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) { + ; +} + + +// SWDIO/TMS Pin I/O -------------------------------------- + +/** SWDIO/TMS I/O pin: Get Input. +\return Current status of the SWDIO/TMS DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) { + return (0U); +} + +/** SWDIO/TMS I/O pin: Set Output to High. +Set the SWDIO/TMS DAP hardware I/O pin to high level. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) { + ; +} + +/** SWDIO/TMS I/O pin: Set Output to Low. +Set the SWDIO/TMS DAP hardware I/O pin to low level. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) { + ; +} + +/** SWDIO I/O pin: Get Input (used in SWD mode only). +\return Current status of the SWDIO DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) { + return (0U); +} + +/** SWDIO I/O pin: Set Output (used in SWD mode only). +\param bit Output value for the SWDIO DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit) { + ; +} + +/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only). +Configure the SWDIO DAP hardware I/O pin to output mode. This function is +called prior \ref PIN_SWDIO_OUT function calls. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) { + ; +} + +/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only). +Configure the SWDIO DAP hardware I/O pin to input mode. This function is +called prior \ref PIN_SWDIO_IN function calls. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) { + ; +} + + +// TDI Pin I/O --------------------------------------------- + +/** TDI I/O pin: Get Input. +\return Current status of the TDI DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_TDI_IN (void) { + return (0U); +} + +/** TDI I/O pin: Set Output. +\param bit Output value for the TDI DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE void PIN_TDI_OUT (uint32_t bit) { + ; +} + + +// TDO Pin I/O --------------------------------------------- + +/** TDO I/O pin: Get Input. +\return Current status of the TDO DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_TDO_IN (void) { + return (0U); +} + + +// nTRST Pin I/O ------------------------------------------- + +/** nTRST I/O pin: Get Input. +\return Current status of the nTRST DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN (void) { + return (0U); +} + +/** nTRST I/O pin: Set Output. +\param bit JTAG TRST Test Reset pin status: + - 0: issue a JTAG TRST Test Reset. + - 1: release JTAG TRST Test Reset. +*/ +__STATIC_FORCEINLINE void PIN_nTRST_OUT (uint32_t bit) { + ; +} + +// nRESET Pin I/O------------------------------------------ + +/** nRESET I/O pin: Get Input. +\return Current status of the nRESET DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN (void) { + return (0U); +} + +/** nRESET I/O pin: Set Output. +\param bit target device hardware reset pin status: + - 0: issue a device hardware reset. + - 1: release device hardware reset. +*/ +__STATIC_FORCEINLINE void PIN_nRESET_OUT (uint32_t bit) { + ; +} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs +\ingroup DAP_ConfigIO_gr +@{ + +CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit. + +It is recommended to provide the following LEDs for status indication: + - Connect LED: is active when the DAP hardware is connected to a debugger. + - Running LED: is active when the debugger has put the target device into running state. +*/ + +/** Debug Unit: Set status of Connected LED. +\param bit status of the Connect LED. + - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit. + - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit. +*/ +__STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {} + +/** Debug Unit: Set status Target Running LED. +\param bit status of the Target Running LED. + - 1: Target Running LED ON: program execution in target started. + - 0: Target Running LED OFF: program execution in target stopped. +*/ +__STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp +\ingroup DAP_ConfigIO_gr +@{ +Access function for Test Domain Timer. + +The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By +default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK. + +*/ + +/** Get timestamp of Test Domain Timer. +\return Current timestamp value. +*/ +__STATIC_INLINE uint32_t TIMESTAMP_GET (void) { + return (DWT->CYCCNT); +} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization +\ingroup DAP_ConfigIO_gr +@{ + +CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP. +*/ + +/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized). +This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the +Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set: + - I/O clock system enabled. + - all I/O pins: input buffer enabled, output pins are set to HighZ mode. + - for nTRST, nRESET a weak pull-up (if available) is enabled. + - LED output pins are enabled and LEDs are turned off. +*/ +__STATIC_INLINE void DAP_SETUP (void) { + ; +} + +/** Reset Target Device with custom specific I/O pin or command sequence. +This function allows the optional implementation of a device specific reset sequence. +It is called when the command \ref DAP_ResetTarget and is for example required +when a device needs a time-critical unlock sequence that enables the debug port. +\return 0 = no device specific reset sequence is implemented.\n + 1 = a device specific reset sequence is implemented. +*/ +__STATIC_INLINE uint8_t RESET_TARGET (void) { + return (0U); // change to '1' when a device reset sequence is implemented +} + +///@} + + +#endif /* __DAP_CONFIG_H__ */ diff --git a/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Include/DAP.h b/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Include/DAP.h new file mode 100644 index 00000000..55cf686e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Include/DAP.h @@ -0,0 +1,367 @@ +/* + * Copyright (c) 2013-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 26. April 2022 + * $Revision: V2.1.1 + * + * Project: CMSIS-DAP Include + * Title: DAP.h Definitions + * + *---------------------------------------------------------------------------*/ + +#ifndef __DAP_H__ +#define __DAP_H__ + + +// DAP Firmware Version +#ifdef DAP_FW_V1 +#define DAP_FW_VER "1.3.0" +#else +#define DAP_FW_VER "2.1.1" +#endif + +// DAP Command IDs +#define ID_DAP_Info 0x00U +#define ID_DAP_HostStatus 0x01U +#define ID_DAP_Connect 0x02U +#define ID_DAP_Disconnect 0x03U +#define ID_DAP_TransferConfigure 0x04U +#define ID_DAP_Transfer 0x05U +#define ID_DAP_TransferBlock 0x06U +#define ID_DAP_TransferAbort 0x07U +#define ID_DAP_WriteABORT 0x08U +#define ID_DAP_Delay 0x09U +#define ID_DAP_ResetTarget 0x0AU +#define ID_DAP_SWJ_Pins 0x10U +#define ID_DAP_SWJ_Clock 0x11U +#define ID_DAP_SWJ_Sequence 0x12U +#define ID_DAP_SWD_Configure 0x13U +#define ID_DAP_SWD_Sequence 0x1DU +#define ID_DAP_JTAG_Sequence 0x14U +#define ID_DAP_JTAG_Configure 0x15U +#define ID_DAP_JTAG_IDCODE 0x16U +#define ID_DAP_SWO_Transport 0x17U +#define ID_DAP_SWO_Mode 0x18U +#define ID_DAP_SWO_Baudrate 0x19U +#define ID_DAP_SWO_Control 0x1AU +#define ID_DAP_SWO_Status 0x1BU +#define ID_DAP_SWO_ExtendedStatus 0x1EU +#define ID_DAP_SWO_Data 0x1CU +#define ID_DAP_UART_Transport 0x1FU +#define ID_DAP_UART_Configure 0x20U +#define ID_DAP_UART_Control 0x22U +#define ID_DAP_UART_Status 0x23U +#define ID_DAP_UART_Transfer 0x21U + +#define ID_DAP_QueueCommands 0x7EU +#define ID_DAP_ExecuteCommands 0x7FU + +// DAP Vendor Command IDs +#define ID_DAP_Vendor0 0x80U +#define ID_DAP_Vendor1 0x81U +#define ID_DAP_Vendor2 0x82U +#define ID_DAP_Vendor3 0x83U +#define ID_DAP_Vendor4 0x84U +#define ID_DAP_Vendor5 0x85U +#define ID_DAP_Vendor6 0x86U +#define ID_DAP_Vendor7 0x87U +#define ID_DAP_Vendor8 0x88U +#define ID_DAP_Vendor9 0x89U +#define ID_DAP_Vendor10 0x8AU +#define ID_DAP_Vendor11 0x8BU +#define ID_DAP_Vendor12 0x8CU +#define ID_DAP_Vendor13 0x8DU +#define ID_DAP_Vendor14 0x8EU +#define ID_DAP_Vendor15 0x8FU +#define ID_DAP_Vendor16 0x90U +#define ID_DAP_Vendor17 0x91U +#define ID_DAP_Vendor18 0x92U +#define ID_DAP_Vendor19 0x93U +#define ID_DAP_Vendor20 0x94U +#define ID_DAP_Vendor21 0x95U +#define ID_DAP_Vendor22 0x96U +#define ID_DAP_Vendor23 0x97U +#define ID_DAP_Vendor24 0x98U +#define ID_DAP_Vendor25 0x99U +#define ID_DAP_Vendor26 0x9AU +#define ID_DAP_Vendor27 0x9BU +#define ID_DAP_Vendor28 0x9CU +#define ID_DAP_Vendor29 0x9DU +#define ID_DAP_Vendor30 0x9EU +#define ID_DAP_Vendor31 0x9FU + +#define ID_DAP_Invalid 0xFFU + +// DAP Status Code +#define DAP_OK 0U +#define DAP_ERROR 0xFFU + +// DAP ID +#define DAP_ID_VENDOR 1U +#define DAP_ID_PRODUCT 2U +#define DAP_ID_SER_NUM 3U +#define DAP_ID_DAP_FW_VER 4U +#define DAP_ID_DEVICE_VENDOR 5U +#define DAP_ID_DEVICE_NAME 6U +#define DAP_ID_BOARD_VENDOR 7U +#define DAP_ID_BOARD_NAME 8U +#define DAP_ID_PRODUCT_FW_VER 9U +#define DAP_ID_CAPABILITIES 0xF0U +#define DAP_ID_TIMESTAMP_CLOCK 0xF1U +#define DAP_ID_UART_RX_BUFFER_SIZE 0xFBU +#define DAP_ID_UART_TX_BUFFER_SIZE 0xFCU +#define DAP_ID_SWO_BUFFER_SIZE 0xFDU +#define DAP_ID_PACKET_COUNT 0xFEU +#define DAP_ID_PACKET_SIZE 0xFFU + +// DAP Host Status +#define DAP_DEBUGGER_CONNECTED 0U +#define DAP_TARGET_RUNNING 1U + +// DAP Port +#define DAP_PORT_AUTODETECT 0U // Autodetect Port +#define DAP_PORT_DISABLED 0U // Port Disabled (I/O pins in High-Z) +#define DAP_PORT_SWD 1U // SWD Port (SWCLK, SWDIO) + nRESET +#define DAP_PORT_JTAG 2U // JTAG Port (TCK, TMS, TDI, TDO, nTRST) + nRESET + +// DAP SWJ Pins +#define DAP_SWJ_SWCLK_TCK 0 // SWCLK/TCK +#define DAP_SWJ_SWDIO_TMS 1 // SWDIO/TMS +#define DAP_SWJ_TDI 2 // TDI +#define DAP_SWJ_TDO 3 // TDO +#define DAP_SWJ_nTRST 5 // nTRST +#define DAP_SWJ_nRESET 7 // nRESET + +// DAP Transfer Request +#define DAP_TRANSFER_APnDP (1U<<0) +#define DAP_TRANSFER_RnW (1U<<1) +#define DAP_TRANSFER_A2 (1U<<2) +#define DAP_TRANSFER_A3 (1U<<3) +#define DAP_TRANSFER_MATCH_VALUE (1U<<4) +#define DAP_TRANSFER_MATCH_MASK (1U<<5) +#define DAP_TRANSFER_TIMESTAMP (1U<<7) + +// DAP Transfer Response +#define DAP_TRANSFER_OK (1U<<0) +#define DAP_TRANSFER_WAIT (1U<<1) +#define DAP_TRANSFER_FAULT (1U<<2) +#define DAP_TRANSFER_ERROR (1U<<3) +#define DAP_TRANSFER_MISMATCH (1U<<4) + +// DAP SWO Trace Mode +#define DAP_SWO_OFF 0U +#define DAP_SWO_UART 1U +#define DAP_SWO_MANCHESTER 2U + +// DAP SWO Trace Status +#define DAP_SWO_CAPTURE_ACTIVE (1U<<0) +#define DAP_SWO_CAPTURE_PAUSED (1U<<1) +#define DAP_SWO_STREAM_ERROR (1U<<6) +#define DAP_SWO_BUFFER_OVERRUN (1U<<7) + +// DAP UART Transport +#define DAP_UART_TRANSPORT_NONE 0U +#define DAP_UART_TRANSPORT_USB_COM_PORT 1U +#define DAP_UART_TRANSPORT_DAP_COMMAND 2U + +// DAP UART Control +#define DAP_UART_CONTROL_RX_ENABLE (1U<<0) +#define DAP_UART_CONTROL_RX_DISABLE (1U<<1) +#define DAP_UART_CONTROL_RX_BUF_FLUSH (1U<<2) +#define DAP_UART_CONTROL_TX_ENABLE (1U<<4) +#define DAP_UART_CONTROL_TX_DISABLE (1U<<5) +#define DAP_UART_CONTROL_TX_BUF_FLUSH (1U<<6) + +// DAP UART Status +#define DAP_UART_STATUS_RX_ENABLED (1U<<0) +#define DAP_UART_STATUS_RX_DATA_LOST (1U<<1) +#define DAP_UART_STATUS_FRAMING_ERROR (1U<<2) +#define DAP_UART_STATUS_PARITY_ERROR (1U<<3) +#define DAP_UART_STATUS_TX_ENABLED (1U<<4) + +// DAP UART Configure Error +#define DAP_UART_CFG_ERROR_DATA_BITS (1U<<0) +#define DAP_UART_CFG_ERROR_PARITY (1U<<1) +#define DAP_UART_CFG_ERROR_STOP_BITS (1U<<2) + +// Debug Port Register Addresses +#define DP_IDCODE 0x00U // IDCODE Register (SW Read only) +#define DP_ABORT 0x00U // Abort Register (SW Write only) +#define DP_CTRL_STAT 0x04U // Control & Status +#define DP_WCR 0x04U // Wire Control Register (SW Only) +#define DP_SELECT 0x08U // Select Register (JTAG R/W & SW W) +#define DP_RESEND 0x08U // Resend (SW Read Only) +#define DP_RDBUFF 0x0CU // Read Buffer (Read Only) + +// JTAG IR Codes +#define JTAG_ABORT 0x08U +#define JTAG_DPACC 0x0AU +#define JTAG_APACC 0x0BU +#define JTAG_IDCODE 0x0EU +#define JTAG_BYPASS 0x0FU + +// JTAG Sequence Info +#define JTAG_SEQUENCE_TCK 0x3FU // TCK count +#define JTAG_SEQUENCE_TMS 0x40U // TMS value +#define JTAG_SEQUENCE_TDO 0x80U // TDO capture + +// SWD Sequence Info +#define SWD_SEQUENCE_CLK 0x3FU // SWCLK count +#define SWD_SEQUENCE_DIN 0x80U // SWDIO capture + + +#include +#include +#include "cmsis_compiler.h" + +// DAP Data structure +typedef struct { + uint8_t debug_port; // Debug Port + uint8_t fast_clock; // Fast Clock Flag + uint8_t padding[2]; + uint32_t clock_delay; // Clock Delay + uint32_t timestamp; // Last captured Timestamp + struct { // Transfer Configuration + uint8_t idle_cycles; // Idle cycles after transfer + uint8_t padding[3]; + uint16_t retry_count; // Number of retries after WAIT response + uint16_t match_retry; // Number of retries if read value does not match + uint32_t match_mask; // Match Mask + } transfer; +#if (DAP_SWD != 0) + struct { // SWD Configuration + uint8_t turnaround; // Turnaround period + uint8_t data_phase; // Always generate Data Phase + } swd_conf; +#endif +#if (DAP_JTAG != 0) + struct { // JTAG Device Chain + uint8_t count; // Number of devices + uint8_t index; // Device index (device at TDO has index 0) +#if (DAP_JTAG_DEV_CNT != 0) + uint8_t ir_length[DAP_JTAG_DEV_CNT]; // IR Length in bits + uint16_t ir_before[DAP_JTAG_DEV_CNT]; // Bits before IR + uint16_t ir_after [DAP_JTAG_DEV_CNT]; // Bits after IR +#endif + } jtag_dev; +#endif +} DAP_Data_t; + +extern DAP_Data_t DAP_Data; // DAP Data +extern volatile uint8_t DAP_TransferAbort; // Transfer Abort Flag + + +#ifdef __cplusplus +extern "C" +{ +#endif + +// Functions +extern void SWJ_Sequence (uint32_t count, const uint8_t *data); +extern void SWD_Sequence (uint32_t info, const uint8_t *swdo, uint8_t *swdi); +extern void JTAG_Sequence (uint32_t info, const uint8_t *tdi, uint8_t *tdo); +extern void JTAG_IR (uint32_t ir); +extern uint32_t JTAG_ReadIDCode (void); +extern void JTAG_WriteAbort (uint32_t data); +extern uint8_t JTAG_Transfer (uint32_t request, uint32_t *data); +extern uint8_t SWD_Transfer (uint32_t request, uint32_t *data); + +extern void Delayms (uint32_t delay); + +extern uint32_t SWO_Transport (const uint8_t *request, uint8_t *response); +extern uint32_t SWO_Mode (const uint8_t *request, uint8_t *response); +extern uint32_t SWO_Baudrate (const uint8_t *request, uint8_t *response); +extern uint32_t SWO_Control (const uint8_t *request, uint8_t *response); +extern uint32_t SWO_Status (uint8_t *response); +extern uint32_t SWO_ExtendedStatus (const uint8_t *request, uint8_t *response); +extern uint32_t SWO_Data (const uint8_t *request, uint8_t *response); + +extern void SWO_QueueTransfer (uint8_t *buf, uint32_t num); +extern void SWO_AbortTransfer (void); +extern void SWO_TransferComplete (void); + +extern uint32_t SWO_Mode_UART (uint32_t enable); +extern uint32_t SWO_Baudrate_UART (uint32_t baudrate); +extern uint32_t SWO_Control_UART (uint32_t active); +extern void SWO_Capture_UART (uint8_t *buf, uint32_t num); +extern uint32_t SWO_GetCount_UART (void); + +extern uint32_t SWO_Mode_Manchester (uint32_t enable); +extern uint32_t SWO_Baudrate_Manchester (uint32_t baudrate); +extern uint32_t SWO_Control_Manchester (uint32_t active); +extern void SWO_Capture_Manchester (uint8_t *buf, uint32_t num); +extern uint32_t SWO_GetCount_Manchester (void); + +extern uint32_t UART_Transport (const uint8_t *request, uint8_t *response); +extern uint32_t UART_Configure (const uint8_t *request, uint8_t *response); +extern uint32_t UART_Control (const uint8_t *request, uint8_t *response); +extern uint32_t UART_Status (uint8_t *response); +extern uint32_t UART_Transfer (const uint8_t *request, uint8_t *response); + +extern uint8_t USB_COM_PORT_Activate (uint32_t cmd); + +extern uint32_t DAP_ProcessVendorCommand (const uint8_t *request, uint8_t *response); +extern uint32_t DAP_ProcessCommand (const uint8_t *request, uint8_t *response); +extern uint32_t DAP_ExecuteCommand (const uint8_t *request, uint8_t *response); + +extern void DAP_Setup (void); + +// Configurable delay for clock generation +#ifndef DELAY_SLOW_CYCLES +#define DELAY_SLOW_CYCLES 3U // Number of cycles for one iteration +#endif +#if defined(__CC_ARM) +__STATIC_FORCEINLINE void PIN_DELAY_SLOW (uint32_t delay) { + uint32_t count = delay; + while (--count); +} +#else +__STATIC_FORCEINLINE void PIN_DELAY_SLOW (uint32_t delay) { + __ASM volatile ( + ".syntax unified\n" + "0:\n\t" + "subs %0,%0,#1\n\t" + "bne 0b\n" + : "+l" (delay) : : "cc" + ); +} +#endif + +// Fixed delay for fast clock generation +#ifndef DELAY_FAST_CYCLES +#define DELAY_FAST_CYCLES 0U // Number of cycles: 0..3 +#endif +__STATIC_FORCEINLINE void PIN_DELAY_FAST (void) { +#if (DELAY_FAST_CYCLES >= 1U) + __NOP(); +#endif +#if (DELAY_FAST_CYCLES >= 2U) + __NOP(); +#endif +#if (DELAY_FAST_CYCLES >= 3U) + __NOP(); +#endif +} + +#ifdef __cplusplus +} +#endif + + +#endif /* __DAP_H__ */ diff --git a/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Source/DAP.c b/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Source/DAP.c new file mode 100644 index 00000000..606917ea --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Source/DAP.c @@ -0,0 +1,1812 @@ +/* + * Copyright (c) 2013-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 26. April 2022 + * $Revision: V2.1.1 + * + * Project: CMSIS-DAP Source + * Title: DAP.c CMSIS-DAP Commands + * + *---------------------------------------------------------------------------*/ + +#include +#include "DAP_config.h" +#include "DAP.h" + + +#if (DAP_PACKET_SIZE < 64U) +#error "Minimum Packet Size is 64!" +#endif +#if (DAP_PACKET_SIZE > 32768U) +#error "Maximum Packet Size is 32768!" +#endif +#if (DAP_PACKET_COUNT < 1U) +#error "Minimum Packet Count is 1!" +#endif +#if (DAP_PACKET_COUNT > 255U) +#error "Maximum Packet Count is 255!" +#endif + + +// Clock Macros +#define MAX_SWJ_CLOCK(delay_cycles) \ + ((CPU_CLOCK/2U) / (IO_PORT_WRITE_CYCLES + delay_cycles)) + + + DAP_Data_t DAP_Data; // DAP Data +volatile uint8_t DAP_TransferAbort; // Transfer Abort Flag + + +static const char DAP_FW_Ver [] = DAP_FW_VER; + + +// Common clock delay calculation routine +// clock: requested SWJ frequency in Hertz +static void Set_Clock_Delay(uint32_t clock) { + uint32_t delay; + + if (clock >= MAX_SWJ_CLOCK(DELAY_FAST_CYCLES)) { + DAP_Data.fast_clock = 1U; + DAP_Data.clock_delay = 1U; + } else { + DAP_Data.fast_clock = 0U; + + delay = ((CPU_CLOCK/2U) + (clock - 1U)) / clock; + if (delay > IO_PORT_WRITE_CYCLES) { + delay -= IO_PORT_WRITE_CYCLES; + delay = (delay + (DELAY_SLOW_CYCLES - 1U)) / DELAY_SLOW_CYCLES; + } else { + delay = 1U; + } + + DAP_Data.clock_delay = delay; + } +} + + +// Get DAP Information +// id: info identifier +// info: pointer to info data +// return: number of bytes in info data +static uint8_t DAP_Info(uint8_t id, uint8_t *info) { + uint8_t length = 0U; + + switch (id) { + case DAP_ID_VENDOR: + length = DAP_GetVendorString((char *)info); + break; + case DAP_ID_PRODUCT: + length = DAP_GetProductString((char *)info); + break; + case DAP_ID_SER_NUM: + length = DAP_GetSerNumString((char *)info); + break; + case DAP_ID_DAP_FW_VER: + length = (uint8_t)sizeof(DAP_FW_Ver); + memcpy(info, DAP_FW_Ver, length); + break; + case DAP_ID_DEVICE_VENDOR: + length = DAP_GetTargetDeviceVendorString((char *)info); + break; + case DAP_ID_DEVICE_NAME: + length = DAP_GetTargetDeviceNameString((char *)info); + break; + case DAP_ID_BOARD_VENDOR: + length = DAP_GetTargetBoardVendorString((char *)info); + break; + case DAP_ID_BOARD_NAME: + length = DAP_GetTargetBoardNameString((char *)info); + break; + case DAP_ID_PRODUCT_FW_VER: + length = DAP_GetProductFirmwareVersionString((char *)info); + break; + case DAP_ID_CAPABILITIES: + info[0] = ((DAP_SWD != 0) ? (1U << 0) : 0U) | + ((DAP_JTAG != 0) ? (1U << 1) : 0U) | + ((SWO_UART != 0) ? (1U << 2) : 0U) | + ((SWO_MANCHESTER != 0) ? (1U << 3) : 0U) | + /* Atomic Commands */ (1U << 4) | + ((TIMESTAMP_CLOCK != 0U) ? (1U << 5) : 0U) | + ((SWO_STREAM != 0U) ? (1U << 6) : 0U) | + ((DAP_UART != 0U) ? (1U << 7) : 0U); + + info[1] = ((DAP_UART_USB_COM_PORT != 0) ? (1U << 0) : 0U); + length = 2U; + break; + case DAP_ID_TIMESTAMP_CLOCK: +#if (TIMESTAMP_CLOCK != 0U) + info[0] = (uint8_t)(TIMESTAMP_CLOCK >> 0); + info[1] = (uint8_t)(TIMESTAMP_CLOCK >> 8); + info[2] = (uint8_t)(TIMESTAMP_CLOCK >> 16); + info[3] = (uint8_t)(TIMESTAMP_CLOCK >> 24); + length = 4U; +#endif + break; + case DAP_ID_UART_RX_BUFFER_SIZE: +#if (DAP_UART != 0) + info[0] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 0); + info[1] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 8); + info[2] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 16); + info[3] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 24); + length = 4U; +#endif + break; + case DAP_ID_UART_TX_BUFFER_SIZE: +#if (DAP_UART != 0) + info[0] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 0); + info[1] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 8); + info[2] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 16); + info[3] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 24); + length = 4U; +#endif + break; + case DAP_ID_SWO_BUFFER_SIZE: +#if ((SWO_UART != 0) || (SWO_MANCHESTER != 0)) + info[0] = (uint8_t)(SWO_BUFFER_SIZE >> 0); + info[1] = (uint8_t)(SWO_BUFFER_SIZE >> 8); + info[2] = (uint8_t)(SWO_BUFFER_SIZE >> 16); + info[3] = (uint8_t)(SWO_BUFFER_SIZE >> 24); + length = 4U; +#endif + break; + case DAP_ID_PACKET_SIZE: + info[0] = (uint8_t)(DAP_PACKET_SIZE >> 0); + info[1] = (uint8_t)(DAP_PACKET_SIZE >> 8); + length = 2U; + break; + case DAP_ID_PACKET_COUNT: + info[0] = DAP_PACKET_COUNT; + length = 1U; + break; + default: + break; + } + + return (length); +} + + +// Delay for specified time +// delay: delay time in ms +void Delayms(uint32_t delay) { + delay *= ((CPU_CLOCK/1000U) + (DELAY_SLOW_CYCLES-1U)) / DELAY_SLOW_CYCLES; + PIN_DELAY_SLOW(delay); +} + + +// Process Delay command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_Delay(const uint8_t *request, uint8_t *response) { + uint32_t delay; + + delay = (uint32_t)(*(request+0)) | + (uint32_t)(*(request+1) << 8); + delay *= ((CPU_CLOCK/1000000U) + (DELAY_SLOW_CYCLES-1U)) / DELAY_SLOW_CYCLES; + + PIN_DELAY_SLOW(delay); + + *response = DAP_OK; + return ((2U << 16) | 1U); +} + + +// Process Host Status command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_HostStatus(const uint8_t *request, uint8_t *response) { + + switch (*request) { + case DAP_DEBUGGER_CONNECTED: + LED_CONNECTED_OUT((*(request+1) & 1U)); + break; + case DAP_TARGET_RUNNING: + LED_RUNNING_OUT((*(request+1) & 1U)); + break; + default: + *response = DAP_ERROR; + return ((2U << 16) | 1U); + } + + *response = DAP_OK; + return ((2U << 16) | 1U); +} + + +// Process Connect command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_Connect(const uint8_t *request, uint8_t *response) { + uint32_t port; + + if (*request == DAP_PORT_AUTODETECT) { + port = DAP_DEFAULT_PORT; + } else { + port = *request; + } + + switch (port) { +#if (DAP_SWD != 0) + case DAP_PORT_SWD: + DAP_Data.debug_port = DAP_PORT_SWD; + PORT_SWD_SETUP(); + break; +#endif +#if (DAP_JTAG != 0) + case DAP_PORT_JTAG: + DAP_Data.debug_port = DAP_PORT_JTAG; + PORT_JTAG_SETUP(); + break; +#endif + default: + port = DAP_PORT_DISABLED; + break; + } + + *response = (uint8_t)port; + return ((1U << 16) | 1U); +} + + +// Process Disconnect command and prepare response +// response: pointer to response data +// return: number of bytes in response +static uint32_t DAP_Disconnect(uint8_t *response) { + + DAP_Data.debug_port = DAP_PORT_DISABLED; + PORT_OFF(); + + *response = DAP_OK; + return (1U); +} + + +// Process Reset Target command and prepare response +// response: pointer to response data +// return: number of bytes in response +static uint32_t DAP_ResetTarget(uint8_t *response) { + + *(response+1) = RESET_TARGET(); + *(response+0) = DAP_OK; + return (2U); +} + + +// Process SWJ Pins command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_SWJ_Pins(const uint8_t *request, uint8_t *response) { +#if ((DAP_SWD != 0) || (DAP_JTAG != 0)) + uint32_t value; + uint32_t select; + uint32_t wait; + uint32_t timestamp; + + value = (uint32_t) *(request+0); + select = (uint32_t) *(request+1); + wait = (uint32_t)(*(request+2) << 0) | + (uint32_t)(*(request+3) << 8) | + (uint32_t)(*(request+4) << 16) | + (uint32_t)(*(request+5) << 24); + + if ((select & (1U << DAP_SWJ_SWCLK_TCK)) != 0U) { + if ((value & (1U << DAP_SWJ_SWCLK_TCK)) != 0U) { + PIN_SWCLK_TCK_SET(); + } else { + PIN_SWCLK_TCK_CLR(); + } + } + if ((select & (1U << DAP_SWJ_SWDIO_TMS)) != 0U) { + if ((value & (1U << DAP_SWJ_SWDIO_TMS)) != 0U) { + PIN_SWDIO_TMS_SET(); + } else { + PIN_SWDIO_TMS_CLR(); + } + } + if ((select & (1U << DAP_SWJ_TDI)) != 0U) { + PIN_TDI_OUT(value >> DAP_SWJ_TDI); + } + if ((select & (1U << DAP_SWJ_nTRST)) != 0U) { + PIN_nTRST_OUT(value >> DAP_SWJ_nTRST); + } + if ((select & (1U << DAP_SWJ_nRESET)) != 0U){ + PIN_nRESET_OUT(value >> DAP_SWJ_nRESET); + } + + if (wait != 0U) { +#if (TIMESTAMP_CLOCK != 0U) + if (wait > 3000000U) { + wait = 3000000U; + } +#if (TIMESTAMP_CLOCK >= 1000000U) + wait *= TIMESTAMP_CLOCK / 1000000U; +#else + wait /= 1000000U / TIMESTAMP_CLOCK; +#endif +#else + wait = 1U; +#endif + timestamp = TIMESTAMP_GET(); + do { + if ((select & (1U << DAP_SWJ_SWCLK_TCK)) != 0U) { + if ((value >> DAP_SWJ_SWCLK_TCK) ^ PIN_SWCLK_TCK_IN()) { + continue; + } + } + if ((select & (1U << DAP_SWJ_SWDIO_TMS)) != 0U) { + if ((value >> DAP_SWJ_SWDIO_TMS) ^ PIN_SWDIO_TMS_IN()) { + continue; + } + } + if ((select & (1U << DAP_SWJ_TDI)) != 0U) { + if ((value >> DAP_SWJ_TDI) ^ PIN_TDI_IN()) { + continue; + } + } + if ((select & (1U << DAP_SWJ_nTRST)) != 0U) { + if ((value >> DAP_SWJ_nTRST) ^ PIN_nTRST_IN()) { + continue; + } + } + if ((select & (1U << DAP_SWJ_nRESET)) != 0U) { + if ((value >> DAP_SWJ_nRESET) ^ PIN_nRESET_IN()) { + continue; + } + } + break; + } while ((TIMESTAMP_GET() - timestamp) < wait); + } + + value = (PIN_SWCLK_TCK_IN() << DAP_SWJ_SWCLK_TCK) | + (PIN_SWDIO_TMS_IN() << DAP_SWJ_SWDIO_TMS) | + (PIN_TDI_IN() << DAP_SWJ_TDI) | + (PIN_TDO_IN() << DAP_SWJ_TDO) | + (PIN_nTRST_IN() << DAP_SWJ_nTRST) | + (PIN_nRESET_IN() << DAP_SWJ_nRESET); + + *response = (uint8_t)value; +#else + *response = 0U; +#endif + + return ((6U << 16) | 1U); +} + + +// Process SWJ Clock command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_SWJ_Clock(const uint8_t *request, uint8_t *response) { +#if ((DAP_SWD != 0) || (DAP_JTAG != 0)) + uint32_t clock; + uint32_t delay; + + clock = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + + if (clock == 0U) { + *response = DAP_ERROR; + return ((4U << 16) | 1U); + } + + Set_Clock_Delay(clock); + + *response = DAP_OK; +#else + *response = DAP_ERROR; +#endif + + return ((4U << 16) | 1U); +} + + +// Process SWJ Sequence command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_SWJ_Sequence(const uint8_t *request, uint8_t *response) { + uint32_t count; + + count = *request++; + if (count == 0U) { + count = 256U; + } + +#if ((DAP_SWD != 0) || (DAP_JTAG != 0)) + SWJ_Sequence(count, request); + *response = DAP_OK; +#else + *response = DAP_ERROR; +#endif + + count = (count + 7U) >> 3; + + return (((count + 1U) << 16) | 1U); +} + + +// Process SWD Configure command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_SWD_Configure(const uint8_t *request, uint8_t *response) { +#if (DAP_SWD != 0) + uint8_t value; + + value = *request; + DAP_Data.swd_conf.turnaround = (value & 0x03U) + 1U; + DAP_Data.swd_conf.data_phase = (value & 0x04U) ? 1U : 0U; + + *response = DAP_OK; +#else + *response = DAP_ERROR; +#endif + + return ((1U << 16) | 1U); +} + + +// Process SWD Sequence command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_SWD_Sequence(const uint8_t *request, uint8_t *response) { + uint32_t sequence_info; + uint32_t sequence_count; + uint32_t request_count; + uint32_t response_count; + uint32_t count; + +#if (DAP_SWD != 0) + *response++ = DAP_OK; +#else + *response++ = DAP_ERROR; +#endif + request_count = 1U; + response_count = 1U; + + sequence_count = *request++; + while (sequence_count--) { + sequence_info = *request++; + count = sequence_info & SWD_SEQUENCE_CLK; + if (count == 0U) { + count = 64U; + } + count = (count + 7U) / 8U; +#if (DAP_SWD != 0) + if ((sequence_info & SWD_SEQUENCE_DIN) != 0U) { + PIN_SWDIO_OUT_DISABLE(); + } else { + PIN_SWDIO_OUT_ENABLE(); + } + SWD_Sequence(sequence_info, request, response); + if (sequence_count == 0U) { + PIN_SWDIO_OUT_ENABLE(); + } +#endif + if ((sequence_info & SWD_SEQUENCE_DIN) != 0U) { + request_count++; +#if (DAP_SWD != 0) + response += count; + response_count += count; +#endif + } else { + request += count; + request_count += count + 1U; + } + } + + return ((request_count << 16) | response_count); +} + + +// Process JTAG Sequence command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_JTAG_Sequence(const uint8_t *request, uint8_t *response) { + uint32_t sequence_info; + uint32_t sequence_count; + uint32_t request_count; + uint32_t response_count; + uint32_t count; + +#if (DAP_JTAG != 0) + *response++ = DAP_OK; +#else + *response++ = DAP_ERROR; +#endif + request_count = 1U; + response_count = 1U; + + sequence_count = *request++; + while (sequence_count--) { + sequence_info = *request++; + count = sequence_info & JTAG_SEQUENCE_TCK; + if (count == 0U) { + count = 64U; + } + count = (count + 7U) / 8U; +#if (DAP_JTAG != 0) + JTAG_Sequence(sequence_info, request, response); +#endif + request += count; + request_count += count + 1U; +#if (DAP_JTAG != 0) + if ((sequence_info & JTAG_SEQUENCE_TDO) != 0U) { + response += count; + response_count += count; + } +#endif + } + + return ((request_count << 16) | response_count); +} + + +// Process JTAG Configure command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_JTAG_Configure(const uint8_t *request, uint8_t *response) { + uint32_t count; +#if (DAP_JTAG != 0) + uint32_t length; + uint32_t bits; + uint32_t n; + + count = *request++; + DAP_Data.jtag_dev.count = (uint8_t)count; + + bits = 0U; + for (n = 0U; n < count; n++) { + length = *request++; + DAP_Data.jtag_dev.ir_length[n] = (uint8_t)length; + DAP_Data.jtag_dev.ir_before[n] = (uint16_t)bits; + bits += length; + } + for (n = 0U; n < count; n++) { + bits -= DAP_Data.jtag_dev.ir_length[n]; + DAP_Data.jtag_dev.ir_after[n] = (uint16_t)bits; + } + + *response = DAP_OK; +#else + count = *request; + *response = DAP_ERROR; +#endif + + return (((count + 1U) << 16) | 1U); +} + + +// Process JTAG IDCODE command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_JTAG_IDCode(const uint8_t *request, uint8_t *response) { +#if (DAP_JTAG != 0) + uint32_t data; + + if (DAP_Data.debug_port != DAP_PORT_JTAG) { + goto id_error; + } + + // Device index (JTAP TAP) + DAP_Data.jtag_dev.index = *request; + if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) { + goto id_error; + } + + // Select JTAG chain + JTAG_IR(JTAG_IDCODE); + + // Read IDCODE register + data = JTAG_ReadIDCode(); + + // Store Data + *(response+0) = DAP_OK; + *(response+1) = (uint8_t)(data >> 0); + *(response+2) = (uint8_t)(data >> 8); + *(response+3) = (uint8_t)(data >> 16); + *(response+4) = (uint8_t)(data >> 24); + + return ((1U << 16) | 5U); + +id_error: +#endif + *response = DAP_ERROR; + return ((1U << 16) | 1U); +} + + +// Process Transfer Configure command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_TransferConfigure(const uint8_t *request, uint8_t *response) { + + DAP_Data.transfer.idle_cycles = *(request+0); + DAP_Data.transfer.retry_count = (uint16_t) *(request+1) | + (uint16_t)(*(request+2) << 8); + DAP_Data.transfer.match_retry = (uint16_t) *(request+3) | + (uint16_t)(*(request+4) << 8); + + *response = DAP_OK; + return ((5U << 16) | 1U); +} + + +// Process SWD Transfer command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +#if (DAP_SWD != 0) +static uint32_t DAP_SWD_Transfer(const uint8_t *request, uint8_t *response) { + const + uint8_t *request_head; + uint32_t request_count; + uint32_t request_value; + uint8_t *response_head; + uint32_t response_count; + uint32_t response_value; + uint32_t post_read; + uint32_t check_write; + uint32_t match_value; + uint32_t match_retry; + uint32_t retry; + uint32_t data; +#if (TIMESTAMP_CLOCK != 0U) + uint32_t timestamp; +#endif + + request_head = request; + + response_count = 0U; + response_value = 0U; + response_head = response; + response += 2; + + DAP_TransferAbort = 0U; + + post_read = 0U; + check_write = 0U; + + request++; // Ignore DAP index + + request_count = *request++; + + for (; request_count != 0U; request_count--) { + request_value = *request++; + if ((request_value & DAP_TRANSFER_RnW) != 0U) { + // Read register + if (post_read) { + // Read was posted before + retry = DAP_Data.transfer.retry_count; + if ((request_value & (DAP_TRANSFER_APnDP | DAP_TRANSFER_MATCH_VALUE)) == DAP_TRANSFER_APnDP) { + // Read previous AP data and post next AP read + do { + response_value = SWD_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } else { + // Read previous AP data + do { + response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + post_read = 0U; + } + if (response_value != DAP_TRANSFER_OK) { + break; + } + // Store previous AP data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); +#if (TIMESTAMP_CLOCK != 0U) + if (post_read) { + // Store Timestamp of next AP read + if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { + timestamp = DAP_Data.timestamp; + *response++ = (uint8_t) timestamp; + *response++ = (uint8_t)(timestamp >> 8); + *response++ = (uint8_t)(timestamp >> 16); + *response++ = (uint8_t)(timestamp >> 24); + } + } +#endif + } + if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) { + // Read with value match + match_value = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + request += 4; + match_retry = DAP_Data.transfer.match_retry; + if ((request_value & DAP_TRANSFER_APnDP) != 0U) { + // Post AP read + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(request_value, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } + } + do { + // Read register until its value matches or retry counter expires + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } + } while (((data & DAP_Data.transfer.match_mask) != match_value) && match_retry-- && !DAP_TransferAbort); + if ((data & DAP_Data.transfer.match_mask) != match_value) { + response_value |= DAP_TRANSFER_MISMATCH; + } + if (response_value != DAP_TRANSFER_OK) { + break; + } + } else { + // Normal read + retry = DAP_Data.transfer.retry_count; + if ((request_value & DAP_TRANSFER_APnDP) != 0U) { + // Read AP register + if (post_read == 0U) { + // Post AP read + do { + response_value = SWD_Transfer(request_value, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } +#if (TIMESTAMP_CLOCK != 0U) + // Store Timestamp + if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { + timestamp = DAP_Data.timestamp; + *response++ = (uint8_t) timestamp; + *response++ = (uint8_t)(timestamp >> 8); + *response++ = (uint8_t)(timestamp >> 16); + *response++ = (uint8_t)(timestamp >> 24); + } +#endif + post_read = 1U; + } + } else { + // Read DP register + do { + response_value = SWD_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } +#if (TIMESTAMP_CLOCK != 0U) + // Store Timestamp + if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { + timestamp = DAP_Data.timestamp; + *response++ = (uint8_t) timestamp; + *response++ = (uint8_t)(timestamp >> 8); + *response++ = (uint8_t)(timestamp >> 16); + *response++ = (uint8_t)(timestamp >> 24); + } +#endif + // Store data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); + } + } + check_write = 0U; + } else { + // Write register + if (post_read) { + // Read previous data + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } + // Store previous data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); + post_read = 0U; + } + // Load data + data = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + request += 4; + if ((request_value & DAP_TRANSFER_MATCH_MASK) != 0U) { + // Write match mask + DAP_Data.transfer.match_mask = data; + response_value = DAP_TRANSFER_OK; + } else { + // Write DP/AP register + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } +#if (TIMESTAMP_CLOCK != 0U) + // Store Timestamp + if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { + timestamp = DAP_Data.timestamp; + *response++ = (uint8_t) timestamp; + *response++ = (uint8_t)(timestamp >> 8); + *response++ = (uint8_t)(timestamp >> 16); + *response++ = (uint8_t)(timestamp >> 24); + } +#endif + check_write = 1U; + } + } + response_count++; + if (DAP_TransferAbort) { + break; + } + } + + for (; request_count != 0U; request_count--) { + // Process canceled requests + request_value = *request++; + if ((request_value & DAP_TRANSFER_RnW) != 0U) { + // Read register + if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) { + // Read with value match + request += 4; + } + } else { + // Write register + request += 4; + } + } + + if (response_value == DAP_TRANSFER_OK) { + if (post_read) { + // Read previous data + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + // Store previous data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); + } else if (check_write) { + // Check last write + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } + } + +end: + *(response_head+0) = (uint8_t)response_count; + *(response_head+1) = (uint8_t)response_value; + + return (((uint32_t)(request - request_head) << 16) | (uint32_t)(response - response_head)); +} +#endif + + +// Process JTAG Transfer command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +#if (DAP_JTAG != 0) +static uint32_t DAP_JTAG_Transfer(const uint8_t *request, uint8_t *response) { + const + uint8_t *request_head; + uint32_t request_count; + uint32_t request_value; + uint32_t request_ir; + uint8_t *response_head; + uint32_t response_count; + uint32_t response_value; + uint32_t post_read; + uint32_t match_value; + uint32_t match_retry; + uint32_t retry; + uint32_t data; + uint32_t ir; +#if (TIMESTAMP_CLOCK != 0U) + uint32_t timestamp; +#endif + + request_head = request; + + response_count = 0U; + response_value = 0U; + response_head = response; + response += 2; + + DAP_TransferAbort = 0U; + + ir = 0U; + post_read = 0U; + + // Device index (JTAP TAP) + DAP_Data.jtag_dev.index = *request++; + if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) { + goto end; + } + + request_count = *request++; + + for (; request_count != 0U; request_count--) { + request_value = *request++; + request_ir = (request_value & DAP_TRANSFER_APnDP) ? JTAG_APACC : JTAG_DPACC; + if ((request_value & DAP_TRANSFER_RnW) != 0U) { + // Read register + if (post_read) { + // Read was posted before + retry = DAP_Data.transfer.retry_count; + if ((ir == request_ir) && ((request_value & DAP_TRANSFER_MATCH_VALUE) == 0U)) { + // Read previous data and post next read + do { + response_value = JTAG_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } else { + // Select JTAG chain + if (ir != JTAG_DPACC) { + ir = JTAG_DPACC; + JTAG_IR(ir); + } + // Read previous data + do { + response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + post_read = 0U; + } + if (response_value != DAP_TRANSFER_OK) { + break; + } + // Store previous data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); +#if (TIMESTAMP_CLOCK != 0U) + if (post_read) { + // Store Timestamp of next AP read + if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { + timestamp = DAP_Data.timestamp; + *response++ = (uint8_t) timestamp; + *response++ = (uint8_t)(timestamp >> 8); + *response++ = (uint8_t)(timestamp >> 16); + *response++ = (uint8_t)(timestamp >> 24); + } + } +#endif + } + if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) { + // Read with value match + match_value = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + request += 4; + match_retry = DAP_Data.transfer.match_retry; + // Select JTAG chain + if (ir != request_ir) { + ir = request_ir; + JTAG_IR(ir); + } + // Post DP/AP read + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(request_value, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } + do { + // Read register until its value matches or retry counter expires + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } + } while (((data & DAP_Data.transfer.match_mask) != match_value) && match_retry-- && !DAP_TransferAbort); + if ((data & DAP_Data.transfer.match_mask) != match_value) { + response_value |= DAP_TRANSFER_MISMATCH; + } + if (response_value != DAP_TRANSFER_OK) { + break; + } + } else { + // Normal read + if (post_read == 0U) { + // Select JTAG chain + if (ir != request_ir) { + ir = request_ir; + JTAG_IR(ir); + } + // Post DP/AP read + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(request_value, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } +#if (TIMESTAMP_CLOCK != 0U) + // Store Timestamp + if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { + timestamp = DAP_Data.timestamp; + *response++ = (uint8_t) timestamp; + *response++ = (uint8_t)(timestamp >> 8); + *response++ = (uint8_t)(timestamp >> 16); + *response++ = (uint8_t)(timestamp >> 24); + } +#endif + post_read = 1U; + } + } + } else { + // Write register + if (post_read) { + // Select JTAG chain + if (ir != JTAG_DPACC) { + ir = JTAG_DPACC; + JTAG_IR(ir); + } + // Read previous data + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } + // Store previous data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); + post_read = 0U; + } + // Load data + data = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + request += 4; + if ((request_value & DAP_TRANSFER_MATCH_MASK) != 0U) { + // Write match mask + DAP_Data.transfer.match_mask = data; + response_value = DAP_TRANSFER_OK; + } else { + // Select JTAG chain + if (ir != request_ir) { + ir = request_ir; + JTAG_IR(ir); + } + // Write DP/AP register + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } +#if (TIMESTAMP_CLOCK != 0U) + // Store Timestamp + if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { + timestamp = DAP_Data.timestamp; + *response++ = (uint8_t) timestamp; + *response++ = (uint8_t)(timestamp >> 8); + *response++ = (uint8_t)(timestamp >> 16); + *response++ = (uint8_t)(timestamp >> 24); + } +#endif + } + } + response_count++; + if (DAP_TransferAbort) { + break; + } + } + + for (; request_count != 0U; request_count--) { + // Process canceled requests + request_value = *request++; + if ((request_value & DAP_TRANSFER_RnW) != 0U) { + // Read register + if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) { + // Read with value match + request += 4; + } + } else { + // Write register + request += 4; + } + } + + if (response_value == DAP_TRANSFER_OK) { + // Select JTAG chain + if (ir != JTAG_DPACC) { + ir = JTAG_DPACC; + JTAG_IR(ir); + } + if (post_read) { + // Read previous data + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + // Store previous data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); + } else { + // Check last write + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } + } + +end: + *(response_head+0) = (uint8_t)response_count; + *(response_head+1) = (uint8_t)response_value; + + return (((uint32_t)(request - request_head) << 16) | (uint32_t)(response - response_head)); +} +#endif + + +// Process Dummy Transfer command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_Dummy_Transfer(const uint8_t *request, uint8_t *response) { + const + uint8_t *request_head; + uint32_t request_count; + uint32_t request_value; + + request_head = request; + + request++; // Ignore DAP index + + request_count = *request++; + + for (; request_count != 0U; request_count--) { + // Process dummy requests + request_value = *request++; + if ((request_value & DAP_TRANSFER_RnW) != 0U) { + // Read register + if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) { + // Read with value match + request += 4; + } + } else { + // Write register + request += 4; + } + } + + *(response+0) = 0U; // Response count + *(response+1) = 0U; // Response value + + return (((uint32_t)(request - request_head) << 16) | 2U); +} + + +// Process Transfer command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_Transfer(const uint8_t *request, uint8_t *response) { + uint32_t num; + + switch (DAP_Data.debug_port) { +#if (DAP_SWD != 0) + case DAP_PORT_SWD: + num = DAP_SWD_Transfer(request, response); + break; +#endif +#if (DAP_JTAG != 0) + case DAP_PORT_JTAG: + num = DAP_JTAG_Transfer(request, response); + break; +#endif + default: + num = DAP_Dummy_Transfer(request, response); + break; + } + + return (num); +} + + +// Process SWD Transfer Block command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response +#if (DAP_SWD != 0) +static uint32_t DAP_SWD_TransferBlock(const uint8_t *request, uint8_t *response) { + uint32_t request_count; + uint32_t request_value; + uint32_t response_count; + uint32_t response_value; + uint8_t *response_head; + uint32_t retry; + uint32_t data; + + response_count = 0U; + response_value = 0U; + response_head = response; + response += 3; + + DAP_TransferAbort = 0U; + + request++; // Ignore DAP index + + request_count = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8); + request += 2; + if (request_count == 0U) { + goto end; + } + + request_value = *request++; + if ((request_value & DAP_TRANSFER_RnW) != 0U) { + // Read register block + if ((request_value & DAP_TRANSFER_APnDP) != 0U) { + // Post AP read + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(request_value, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + } + while (request_count--) { + // Read DP/AP register + if ((request_count == 0U) && ((request_value & DAP_TRANSFER_APnDP) != 0U)) { + // Last AP read + request_value = DP_RDBUFF | DAP_TRANSFER_RnW; + } + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + // Store data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); + response_count++; + } + } else { + // Write register block + while (request_count--) { + // Load data + data = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + request += 4; + // Write DP/AP register + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + response_count++; + } + // Check last write + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } + +end: + *(response_head+0) = (uint8_t)(response_count >> 0); + *(response_head+1) = (uint8_t)(response_count >> 8); + *(response_head+2) = (uint8_t) response_value; + + return ((uint32_t)(response - response_head)); +} +#endif + + +// Process JTAG Transfer Block command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response +#if (DAP_JTAG != 0) +static uint32_t DAP_JTAG_TransferBlock(const uint8_t *request, uint8_t *response) { + uint32_t request_count; + uint32_t request_value; + uint32_t response_count; + uint32_t response_value; + uint8_t *response_head; + uint32_t retry; + uint32_t data; + uint32_t ir; + + response_count = 0U; + response_value = 0U; + response_head = response; + response += 3; + + DAP_TransferAbort = 0U; + + // Device index (JTAP TAP) + DAP_Data.jtag_dev.index = *request++; + if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) { + goto end; + } + + request_count = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8); + request += 2; + if (request_count == 0U) { + goto end; + } + + request_value = *request++; + + // Select JTAG chain + ir = (request_value & DAP_TRANSFER_APnDP) ? JTAG_APACC : JTAG_DPACC; + JTAG_IR(ir); + + if ((request_value & DAP_TRANSFER_RnW) != 0U) { + // Post read + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(request_value, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + // Read register block + while (request_count--) { + // Read DP/AP register + if (request_count == 0U) { + // Last read + if (ir != JTAG_DPACC) { + JTAG_IR(JTAG_DPACC); + } + request_value = DP_RDBUFF | DAP_TRANSFER_RnW; + } + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + // Store data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); + response_count++; + } + } else { + // Write register block + while (request_count--) { + // Load data + data = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + request += 4; + // Write DP/AP register + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + response_count++; + } + // Check last write + if (ir != JTAG_DPACC) { + JTAG_IR(JTAG_DPACC); + } + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } + +end: + *(response_head+0) = (uint8_t)(response_count >> 0); + *(response_head+1) = (uint8_t)(response_count >> 8); + *(response_head+2) = (uint8_t) response_value; + + return ((uint32_t)(response - response_head)); +} +#endif + + +// Process Transfer Block command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_TransferBlock(const uint8_t *request, uint8_t *response) { + uint32_t num; + + switch (DAP_Data.debug_port) { +#if (DAP_SWD != 0) + case DAP_PORT_SWD: + num = DAP_SWD_TransferBlock (request, response); + break; +#endif +#if (DAP_JTAG != 0) + case DAP_PORT_JTAG: + num = DAP_JTAG_TransferBlock(request, response); + break; +#endif + default: + *(response+0) = 0U; // Response count [7:0] + *(response+1) = 0U; // Response count[15:8] + *(response+2) = 0U; // Response value + num = 3U; + break; + } + + if ((*(request+3) & DAP_TRANSFER_RnW) != 0U) { + // Read register block + num |= 4U << 16; + } else { + // Write register block + num |= (4U + (((uint32_t)(*(request+1)) | (uint32_t)(*(request+2) << 8)) * 4)) << 16; + } + + return (num); +} + + +// Process SWD Write ABORT command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response +#if (DAP_SWD != 0) +static uint32_t DAP_SWD_WriteAbort(const uint8_t *request, uint8_t *response) { + uint32_t data; + + // Load data (Ignore DAP index) + data = (uint32_t)(*(request+1) << 0) | + (uint32_t)(*(request+2) << 8) | + (uint32_t)(*(request+3) << 16) | + (uint32_t)(*(request+4) << 24); + + // Write Abort register + SWD_Transfer(DP_ABORT, &data); + + *response = DAP_OK; + return (1U); +} +#endif + + +// Process JTAG Write ABORT command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response +#if (DAP_JTAG != 0) +static uint32_t DAP_JTAG_WriteAbort(const uint8_t *request, uint8_t *response) { + uint32_t data; + + // Device index (JTAP TAP) + DAP_Data.jtag_dev.index = *request; + if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) { + *response = DAP_ERROR; + return (1U); + } + + // Select JTAG chain + JTAG_IR(JTAG_ABORT); + + // Load data + data = (uint32_t)(*(request+1) << 0) | + (uint32_t)(*(request+2) << 8) | + (uint32_t)(*(request+3) << 16) | + (uint32_t)(*(request+4) << 24); + + // Write Abort register + JTAG_WriteAbort(data); + + *response = DAP_OK; + return (1U); +} +#endif + + +// Process Write ABORT command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_WriteAbort(const uint8_t *request, uint8_t *response) { + uint32_t num; + + switch (DAP_Data.debug_port) { +#if (DAP_SWD != 0) + case DAP_PORT_SWD: + num = DAP_SWD_WriteAbort (request, response); + break; +#endif +#if (DAP_JTAG != 0) + case DAP_PORT_JTAG: + num = DAP_JTAG_WriteAbort(request, response); + break; +#endif + default: + *response = DAP_ERROR; + num = 1U; + break; + } + return ((5U << 16) | num); +} + + +// Process DAP Vendor command request and prepare response +// Default function (can be overridden) +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +__WEAK uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) { + (void)request; + *response = ID_DAP_Invalid; + return ((1U << 16) | 1U); +} + + +// Process DAP command request and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t DAP_ProcessCommand(const uint8_t *request, uint8_t *response) { + uint32_t num; + + if ((*request >= ID_DAP_Vendor0) && (*request <= ID_DAP_Vendor31)) { + return DAP_ProcessVendorCommand(request, response); + } + + *response++ = *request; + + switch (*request++) { + case ID_DAP_Info: + num = DAP_Info(*request, response+1); + *response = (uint8_t)num; + return ((2U << 16) + 2U + num); + + case ID_DAP_HostStatus: + num = DAP_HostStatus(request, response); + break; + + case ID_DAP_Connect: + num = DAP_Connect(request, response); + break; + case ID_DAP_Disconnect: + num = DAP_Disconnect(response); + break; + + case ID_DAP_Delay: + num = DAP_Delay(request, response); + break; + + case ID_DAP_ResetTarget: + num = DAP_ResetTarget(response); + break; + + case ID_DAP_SWJ_Pins: + num = DAP_SWJ_Pins(request, response); + break; + case ID_DAP_SWJ_Clock: + num = DAP_SWJ_Clock(request, response); + break; + case ID_DAP_SWJ_Sequence: + num = DAP_SWJ_Sequence(request, response); + break; + + case ID_DAP_SWD_Configure: + num = DAP_SWD_Configure(request, response); + break; + case ID_DAP_SWD_Sequence: + num = DAP_SWD_Sequence(request, response); + break; + + case ID_DAP_JTAG_Sequence: + num = DAP_JTAG_Sequence(request, response); + break; + case ID_DAP_JTAG_Configure: + num = DAP_JTAG_Configure(request, response); + break; + case ID_DAP_JTAG_IDCODE: + num = DAP_JTAG_IDCode(request, response); + break; + + case ID_DAP_TransferConfigure: + num = DAP_TransferConfigure(request, response); + break; + case ID_DAP_Transfer: + num = DAP_Transfer(request, response); + break; + case ID_DAP_TransferBlock: + num = DAP_TransferBlock(request, response); + break; + + case ID_DAP_WriteABORT: + num = DAP_WriteAbort(request, response); + break; + +#if ((SWO_UART != 0) || (SWO_MANCHESTER != 0)) + case ID_DAP_SWO_Transport: + num = SWO_Transport(request, response); + break; + case ID_DAP_SWO_Mode: + num = SWO_Mode(request, response); + break; + case ID_DAP_SWO_Baudrate: + num = SWO_Baudrate(request, response); + break; + case ID_DAP_SWO_Control: + num = SWO_Control(request, response); + break; + case ID_DAP_SWO_Status: + num = SWO_Status(response); + break; + case ID_DAP_SWO_ExtendedStatus: + num = SWO_ExtendedStatus(request, response); + break; + case ID_DAP_SWO_Data: + num = SWO_Data(request, response); + break; +#endif + +#if (DAP_UART != 0) + case ID_DAP_UART_Transport: + num = UART_Transport(request, response); + break; + case ID_DAP_UART_Configure: + num = UART_Configure(request, response); + break; + case ID_DAP_UART_Control: + num = UART_Control(request, response); + break; + case ID_DAP_UART_Status: + num = UART_Status(response); + break; + case ID_DAP_UART_Transfer: + num = UART_Transfer(request, response); + break; +#endif + + default: + *(response-1) = ID_DAP_Invalid; + return ((1U << 16) | 1U); + } + + return ((1U << 16) + 1U + num); +} + + +// Execute DAP command (process request and prepare response) +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t DAP_ExecuteCommand(const uint8_t *request, uint8_t *response) { + uint32_t cnt, num, n; + + if (*request == ID_DAP_ExecuteCommands) { + *response++ = *request++; + cnt = *request++; + *response++ = (uint8_t)cnt; + num = (2U << 16) | 2U; + while (cnt--) { + n = DAP_ProcessCommand(request, response); + num += n; + request += (uint16_t)(n >> 16); + response += (uint16_t) n; + } + return (num); + } + + return DAP_ProcessCommand(request, response); +} + + +// Setup DAP +void DAP_Setup(void) { + + // Default settings + DAP_Data.debug_port = 0U; + DAP_Data.transfer.idle_cycles = 0U; + DAP_Data.transfer.retry_count = 100U; + DAP_Data.transfer.match_retry = 0U; + DAP_Data.transfer.match_mask = 0x00000000U; +#if (DAP_SWD != 0) + DAP_Data.swd_conf.turnaround = 1U; + DAP_Data.swd_conf.data_phase = 0U; +#endif +#if (DAP_JTAG != 0) + DAP_Data.jtag_dev.count = 0U; +#endif + + // Sets DAP_Data.fast_clock and DAP_Data.clock_delay. + Set_Clock_Delay(DAP_DEFAULT_SWJ_CLOCK); + + DAP_SETUP(); // Device specific setup +} diff --git a/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Source/DAP_vendor.c b/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Source/DAP_vendor.c new file mode 100644 index 00000000..4f2477aa --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Source/DAP_vendor.c @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 1. December 2017 + * $Revision: V2.0.0 + * + * Project: CMSIS-DAP Source + * Title: DAP_vendor.c CMSIS-DAP Vendor Commands + * + *---------------------------------------------------------------------------*/ + +#include "DAP_config.h" +#include "DAP.h" + +//************************************************************************************************** +/** +\defgroup DAP_Vendor_Adapt_gr Adapt Vendor Commands +\ingroup DAP_Vendor_gr +@{ + +The file DAP_vendor.c provides template source code for extension of a Debug Unit with +Vendor Commands. Copy this file to the project folder of the Debug Unit and add the +file to the MDK-ARM project under the file group Configuration. +*/ + +/** Process DAP Vendor Command and prepare Response Data +\param request pointer to request data +\param response pointer to response data +\return number of bytes in response (lower 16 bits) + number of bytes in request (upper 16 bits) +*/ +uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) { + uint32_t num = (1U << 16) | 1U; + + *response++ = *request; // copy Command ID + + switch (*request++) { // first byte in request is Command ID + case ID_DAP_Vendor0: +#if 0 // example user command + num += 1U << 16; // increment request count + if (*request == 1U) { // when first command data byte is 1 + *response++ = 'X'; // send 'X' as response + num++; // increment response count + } +#endif + break; + + case ID_DAP_Vendor1: break; + case ID_DAP_Vendor2: break; + case ID_DAP_Vendor3: break; + case ID_DAP_Vendor4: break; + case ID_DAP_Vendor5: break; + case ID_DAP_Vendor6: break; + case ID_DAP_Vendor7: break; + case ID_DAP_Vendor8: break; + case ID_DAP_Vendor9: break; + case ID_DAP_Vendor10: break; + case ID_DAP_Vendor11: break; + case ID_DAP_Vendor12: break; + case ID_DAP_Vendor13: break; + case ID_DAP_Vendor14: break; + case ID_DAP_Vendor15: break; + case ID_DAP_Vendor16: break; + case ID_DAP_Vendor17: break; + case ID_DAP_Vendor18: break; + case ID_DAP_Vendor19: break; + case ID_DAP_Vendor20: break; + case ID_DAP_Vendor21: break; + case ID_DAP_Vendor22: break; + case ID_DAP_Vendor23: break; + case ID_DAP_Vendor24: break; + case ID_DAP_Vendor25: break; + case ID_DAP_Vendor26: break; + case ID_DAP_Vendor27: break; + case ID_DAP_Vendor28: break; + case ID_DAP_Vendor29: break; + case ID_DAP_Vendor30: break; + case ID_DAP_Vendor31: break; + } + + return (num); +} + +///@} diff --git a/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Source/JTAG_DP.c b/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Source/JTAG_DP.c new file mode 100644 index 00000000..24b1f3f9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Source/JTAG_DP.c @@ -0,0 +1,370 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 1. December 2017 + * $Revision: V2.0.0 + * + * Project: CMSIS-DAP Source + * Title: JTAG_DP.c CMSIS-DAP JTAG DP I/O + * + *---------------------------------------------------------------------------*/ + +#include "DAP_config.h" +#include "DAP.h" + + +// JTAG Macros + +#define PIN_TCK_SET PIN_SWCLK_TCK_SET +#define PIN_TCK_CLR PIN_SWCLK_TCK_CLR +#define PIN_TMS_SET PIN_SWDIO_TMS_SET +#define PIN_TMS_CLR PIN_SWDIO_TMS_CLR + +#define JTAG_CYCLE_TCK() \ + PIN_TCK_CLR(); \ + PIN_DELAY(); \ + PIN_TCK_SET(); \ + PIN_DELAY() + +#define JTAG_CYCLE_TDI(tdi) \ + PIN_TDI_OUT(tdi); \ + PIN_TCK_CLR(); \ + PIN_DELAY(); \ + PIN_TCK_SET(); \ + PIN_DELAY() + +#define JTAG_CYCLE_TDO(tdo) \ + PIN_TCK_CLR(); \ + PIN_DELAY(); \ + tdo = PIN_TDO_IN(); \ + PIN_TCK_SET(); \ + PIN_DELAY() + +#define JTAG_CYCLE_TDIO(tdi,tdo) \ + PIN_TDI_OUT(tdi); \ + PIN_TCK_CLR(); \ + PIN_DELAY(); \ + tdo = PIN_TDO_IN(); \ + PIN_TCK_SET(); \ + PIN_DELAY() + +#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay) + + +#if (DAP_JTAG != 0) + + +// Generate JTAG Sequence +// info: sequence information +// tdi: pointer to TDI generated data +// tdo: pointer to TDO captured data +// return: none +void JTAG_Sequence (uint32_t info, const uint8_t *tdi, uint8_t *tdo) { + uint32_t i_val; + uint32_t o_val; + uint32_t bit; + uint32_t n, k; + + n = info & JTAG_SEQUENCE_TCK; + if (n == 0U) { + n = 64U; + } + + if (info & JTAG_SEQUENCE_TMS) { + PIN_TMS_SET(); + } else { + PIN_TMS_CLR(); + } + + while (n) { + i_val = *tdi++; + o_val = 0U; + for (k = 8U; k && n; k--, n--) { + JTAG_CYCLE_TDIO(i_val, bit); + i_val >>= 1; + o_val >>= 1; + o_val |= bit << 7; + } + o_val >>= k; + if (info & JTAG_SEQUENCE_TDO) { + *tdo++ = (uint8_t)o_val; + } + } +} + + +// JTAG Set IR +// ir: IR value +// return: none +#define JTAG_IR_Function(speed) /**/ \ +static void JTAG_IR_##speed (uint32_t ir) { \ + uint32_t n; \ + \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TCK(); /* Select-DR-Scan */ \ + JTAG_CYCLE_TCK(); /* Select-IR-Scan */ \ + PIN_TMS_CLR(); \ + JTAG_CYCLE_TCK(); /* Capture-IR */ \ + JTAG_CYCLE_TCK(); /* Shift-IR */ \ + \ + PIN_TDI_OUT(1U); \ + for (n = DAP_Data.jtag_dev.ir_before[DAP_Data.jtag_dev.index]; n; n--) { \ + JTAG_CYCLE_TCK(); /* Bypass before data */ \ + } \ + for (n = DAP_Data.jtag_dev.ir_length[DAP_Data.jtag_dev.index] - 1U; n; n--) { \ + JTAG_CYCLE_TDI(ir); /* Set IR bits (except last) */ \ + ir >>= 1; \ + } \ + n = DAP_Data.jtag_dev.ir_after[DAP_Data.jtag_dev.index]; \ + if (n) { \ + JTAG_CYCLE_TDI(ir); /* Set last IR bit */ \ + PIN_TDI_OUT(1U); \ + for (--n; n; n--) { \ + JTAG_CYCLE_TCK(); /* Bypass after data */ \ + } \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TCK(); /* Bypass & Exit1-IR */ \ + } else { \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TDI(ir); /* Set last IR bit & Exit1-IR */ \ + } \ + \ + JTAG_CYCLE_TCK(); /* Update-IR */ \ + PIN_TMS_CLR(); \ + JTAG_CYCLE_TCK(); /* Idle */ \ + PIN_TDI_OUT(1U); \ +} + + +// JTAG Transfer I/O +// request: A[3:2] RnW APnDP +// data: DATA[31:0] +// return: ACK[2:0] +#define JTAG_TransferFunction(speed) /**/ \ +static uint8_t JTAG_Transfer##speed (uint32_t request, uint32_t *data) { \ + uint32_t ack; \ + uint32_t bit; \ + uint32_t val; \ + uint32_t n; \ + \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TCK(); /* Select-DR-Scan */ \ + PIN_TMS_CLR(); \ + JTAG_CYCLE_TCK(); /* Capture-DR */ \ + JTAG_CYCLE_TCK(); /* Shift-DR */ \ + \ + for (n = DAP_Data.jtag_dev.index; n; n--) { \ + JTAG_CYCLE_TCK(); /* Bypass before data */ \ + } \ + \ + JTAG_CYCLE_TDIO(request >> 1, bit); /* Set RnW, Get ACK.0 */ \ + ack = bit << 1; \ + JTAG_CYCLE_TDIO(request >> 2, bit); /* Set A2, Get ACK.1 */ \ + ack |= bit << 0; \ + JTAG_CYCLE_TDIO(request >> 3, bit); /* Set A3, Get ACK.2 */ \ + ack |= bit << 2; \ + \ + if (ack != DAP_TRANSFER_OK) { \ + /* Exit on error */ \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TCK(); /* Exit1-DR */ \ + goto exit; \ + } \ + \ + if (request & DAP_TRANSFER_RnW) { \ + /* Read Transfer */ \ + val = 0U; \ + for (n = 31U; n; n--) { \ + JTAG_CYCLE_TDO(bit); /* Get D0..D30 */ \ + val |= bit << 31; \ + val >>= 1; \ + } \ + n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U; \ + if (n) { \ + JTAG_CYCLE_TDO(bit); /* Get D31 */ \ + for (--n; n; n--) { \ + JTAG_CYCLE_TCK(); /* Bypass after data */ \ + } \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ \ + } else { \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TDO(bit); /* Get D31 & Exit1-DR */ \ + } \ + val |= bit << 31; \ + if (data) { *data = val; } \ + } else { \ + /* Write Transfer */ \ + val = *data; \ + for (n = 31U; n; n--) { \ + JTAG_CYCLE_TDI(val); /* Set D0..D30 */ \ + val >>= 1; \ + } \ + n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U; \ + if (n) { \ + JTAG_CYCLE_TDI(val); /* Set D31 */ \ + for (--n; n; n--) { \ + JTAG_CYCLE_TCK(); /* Bypass after data */ \ + } \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ \ + } else { \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TDI(val); /* Set D31 & Exit1-DR */ \ + } \ + } \ + \ +exit: \ + JTAG_CYCLE_TCK(); /* Update-DR */ \ + PIN_TMS_CLR(); \ + JTAG_CYCLE_TCK(); /* Idle */ \ + PIN_TDI_OUT(1U); \ + \ + /* Capture Timestamp */ \ + if (request & DAP_TRANSFER_TIMESTAMP) { \ + DAP_Data.timestamp = TIMESTAMP_GET(); \ + } \ + \ + /* Idle cycles */ \ + n = DAP_Data.transfer.idle_cycles; \ + while (n--) { \ + JTAG_CYCLE_TCK(); /* Idle */ \ + } \ + \ + return ((uint8_t)ack); \ +} + + +#undef PIN_DELAY +#define PIN_DELAY() PIN_DELAY_FAST() +JTAG_IR_Function(Fast) +JTAG_TransferFunction(Fast) + +#undef PIN_DELAY +#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay) +JTAG_IR_Function(Slow) +JTAG_TransferFunction(Slow) + + +// JTAG Read IDCODE register +// return: value read +uint32_t JTAG_ReadIDCode (void) { + uint32_t bit; + uint32_t val; + uint32_t n; + + PIN_TMS_SET(); + JTAG_CYCLE_TCK(); /* Select-DR-Scan */ + PIN_TMS_CLR(); + JTAG_CYCLE_TCK(); /* Capture-DR */ + JTAG_CYCLE_TCK(); /* Shift-DR */ + + for (n = DAP_Data.jtag_dev.index; n; n--) { + JTAG_CYCLE_TCK(); /* Bypass before data */ + } + + val = 0U; + for (n = 31U; n; n--) { + JTAG_CYCLE_TDO(bit); /* Get D0..D30 */ + val |= bit << 31; + val >>= 1; + } + PIN_TMS_SET(); + JTAG_CYCLE_TDO(bit); /* Get D31 & Exit1-DR */ + val |= bit << 31; + + JTAG_CYCLE_TCK(); /* Update-DR */ + PIN_TMS_CLR(); + JTAG_CYCLE_TCK(); /* Idle */ + + return (val); +} + + +// JTAG Write ABORT register +// data: value to write +// return: none +void JTAG_WriteAbort (uint32_t data) { + uint32_t n; + + PIN_TMS_SET(); + JTAG_CYCLE_TCK(); /* Select-DR-Scan */ + PIN_TMS_CLR(); + JTAG_CYCLE_TCK(); /* Capture-DR */ + JTAG_CYCLE_TCK(); /* Shift-DR */ + + for (n = DAP_Data.jtag_dev.index; n; n--) { + JTAG_CYCLE_TCK(); /* Bypass before data */ + } + + PIN_TDI_OUT(0U); + JTAG_CYCLE_TCK(); /* Set RnW=0 (Write) */ + JTAG_CYCLE_TCK(); /* Set A2=0 */ + JTAG_CYCLE_TCK(); /* Set A3=0 */ + + for (n = 31U; n; n--) { + JTAG_CYCLE_TDI(data); /* Set D0..D30 */ + data >>= 1; + } + n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U; + if (n) { + JTAG_CYCLE_TDI(data); /* Set D31 */ + for (--n; n; n--) { + JTAG_CYCLE_TCK(); /* Bypass after data */ + } + PIN_TMS_SET(); + JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ + } else { + PIN_TMS_SET(); + JTAG_CYCLE_TDI(data); /* Set D31 & Exit1-DR */ + } + + JTAG_CYCLE_TCK(); /* Update-DR */ + PIN_TMS_CLR(); + JTAG_CYCLE_TCK(); /* Idle */ + PIN_TDI_OUT(1U); +} + + +// JTAG Set IR +// ir: IR value +// return: none +void JTAG_IR (uint32_t ir) { + if (DAP_Data.fast_clock) { + JTAG_IR_Fast(ir); + } else { + JTAG_IR_Slow(ir); + } +} + + +// JTAG Transfer I/O +// request: A[3:2] RnW APnDP +// data: DATA[31:0] +// return: ACK[2:0] +uint8_t JTAG_Transfer(uint32_t request, uint32_t *data) { + if (DAP_Data.fast_clock) { + return JTAG_TransferFast(request, data); + } else { + return JTAG_TransferSlow(request, data); + } +} + + +#endif /* (DAP_JTAG != 0) */ diff --git a/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Source/SWO.c b/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Source/SWO.c new file mode 100644 index 00000000..4a850cf8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Source/SWO.c @@ -0,0 +1,798 @@ +/* + * Copyright (c) 2013-2021 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 29. March 2021 + * $Revision: V2.0.1 + * + * Project: CMSIS-DAP Source + * Title: SWO.c CMSIS-DAP SWO I/O + * + *---------------------------------------------------------------------------*/ + +#include "DAP_config.h" +#include "DAP.h" +#if (SWO_UART != 0) +#include "Driver_USART.h" +#endif +#if (SWO_STREAM != 0) +#include "cmsis_os2.h" +#define osObjectsExternal +#include "osObjects.h" +#endif + +#if (SWO_STREAM != 0) +#ifdef DAP_FW_V1 +#error "SWO Streaming Trace not supported in DAP V1!" +#endif +#endif + +#if (SWO_UART != 0) + +// USART Driver +#define _USART_Driver_(n) Driver_USART##n +#define USART_Driver_(n) _USART_Driver_(n) +extern ARM_DRIVER_USART USART_Driver_(SWO_UART_DRIVER); +#define pUSART (&USART_Driver_(SWO_UART_DRIVER)) + +static uint8_t USART_Ready = 0U; + +#endif /* (SWO_UART != 0) */ + + +#if ((SWO_UART != 0) || (SWO_MANCHESTER != 0)) + + +#define SWO_STREAM_TIMEOUT 50U /* Stream timeout in ms */ + +#define USB_BLOCK_SIZE 512U /* USB Block Size */ +#define TRACE_BLOCK_SIZE 64U /* Trace Block Size (2^n: 32...512) */ + +// Trace State +static uint8_t TraceTransport = 0U; /* Trace Transport */ +static uint8_t TraceMode = 0U; /* Trace Mode */ +static uint8_t TraceStatus = 0U; /* Trace Status without Errors */ +static uint8_t TraceError[2] = {0U, 0U}; /* Trace Error flags (banked) */ +static uint8_t TraceError_n = 0U; /* Active Trace Error bank */ + +// Trace Buffer +static uint8_t TraceBuf[SWO_BUFFER_SIZE]; /* Trace Buffer (must be 2^n) */ +static volatile uint32_t TraceIndexI = 0U; /* Incoming Trace Index */ +static volatile uint32_t TraceIndexO = 0U; /* Outgoing Trace Index */ +static volatile uint8_t TraceUpdate; /* Trace Update Flag */ +static uint32_t TraceBlockSize; /* Current Trace Block Size */ + +#if (TIMESTAMP_CLOCK != 0U) +// Trace Timestamp +static volatile struct { + uint32_t index; + uint32_t tick; +} TraceTimestamp; +#endif + +// Trace Helper functions +static void ClearTrace (void); +static void ResumeTrace (void); +static uint32_t GetTraceCount (void); +static uint8_t GetTraceStatus (void); +static void SetTraceError (uint8_t flag); + +#if (SWO_STREAM != 0) +extern osThreadId_t SWO_ThreadId; +static volatile uint8_t TransferBusy = 0U; /* Transfer Busy Flag */ +static uint32_t TransferSize; /* Current Transfer Size */ +#endif + + +#if (SWO_UART != 0) + +// USART Driver Callback function +// event: event mask +static void USART_Callback (uint32_t event) { + uint32_t index_i; + uint32_t index_o; + uint32_t count; + uint32_t num; + + if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) { +#if (TIMESTAMP_CLOCK != 0U) + TraceTimestamp.tick = TIMESTAMP_GET(); +#endif + index_o = TraceIndexO; + index_i = TraceIndexI; + index_i += TraceBlockSize; + TraceIndexI = index_i; +#if (TIMESTAMP_CLOCK != 0U) + TraceTimestamp.index = index_i; +#endif + num = TRACE_BLOCK_SIZE - (index_i & (TRACE_BLOCK_SIZE - 1U)); + count = index_i - index_o; + if (count <= (SWO_BUFFER_SIZE - num)) { + index_i &= SWO_BUFFER_SIZE - 1U; + TraceBlockSize = num; + pUSART->Receive(&TraceBuf[index_i], num); + } else { + TraceStatus = DAP_SWO_CAPTURE_ACTIVE | DAP_SWO_CAPTURE_PAUSED; + } + TraceUpdate = 1U; +#if (SWO_STREAM != 0) + if (TraceTransport == 2U) { + if (count >= (USB_BLOCK_SIZE - (index_o & (USB_BLOCK_SIZE - 1U)))) { + osThreadFlagsSet(SWO_ThreadId, 1U); + } + } +#endif + } + if (event & ARM_USART_EVENT_RX_OVERFLOW) { + SetTraceError(DAP_SWO_BUFFER_OVERRUN); + } + if (event & (ARM_USART_EVENT_RX_BREAK | + ARM_USART_EVENT_RX_FRAMING_ERROR | + ARM_USART_EVENT_RX_PARITY_ERROR)) { + SetTraceError(DAP_SWO_STREAM_ERROR); + } +} + +// Enable or disable SWO Mode (UART) +// enable: enable flag +// return: 1 - Success, 0 - Error +__WEAK uint32_t SWO_Mode_UART (uint32_t enable) { + int32_t status; + + USART_Ready = 0U; + + if (enable != 0U) { + status = pUSART->Initialize(USART_Callback); + if (status != ARM_DRIVER_OK) { + return (0U); + } + status = pUSART->PowerControl(ARM_POWER_FULL); + if (status != ARM_DRIVER_OK) { + pUSART->Uninitialize(); + return (0U); + } + } else { + pUSART->Control(ARM_USART_CONTROL_RX, 0U); + pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U); + pUSART->PowerControl(ARM_POWER_OFF); + pUSART->Uninitialize(); + } + return (1U); +} + +// Configure SWO Baudrate (UART) +// baudrate: requested baudrate +// return: actual baudrate or 0 when not configured +__WEAK uint32_t SWO_Baudrate_UART (uint32_t baudrate) { + int32_t status; + uint32_t index; + uint32_t num; + + if (baudrate > SWO_UART_MAX_BAUDRATE) { + baudrate = SWO_UART_MAX_BAUDRATE; + } + + if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) { + pUSART->Control(ARM_USART_CONTROL_RX, 0U); + if (pUSART->GetStatus().rx_busy) { + TraceIndexI += pUSART->GetRxCount(); + pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U); + } + } + + status = pUSART->Control(ARM_USART_MODE_ASYNCHRONOUS | + ARM_USART_DATA_BITS_8 | + ARM_USART_PARITY_NONE | + ARM_USART_STOP_BITS_1, + baudrate); + + if (status == ARM_DRIVER_OK) { + USART_Ready = 1U; + } else { + USART_Ready = 0U; + return (0U); + } + + if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) { + if ((TraceStatus & DAP_SWO_CAPTURE_PAUSED) == 0U) { + index = TraceIndexI & (SWO_BUFFER_SIZE - 1U); + num = TRACE_BLOCK_SIZE - (index & (TRACE_BLOCK_SIZE - 1U)); + TraceBlockSize = num; + pUSART->Receive(&TraceBuf[index], num); + } + pUSART->Control(ARM_USART_CONTROL_RX, 1U); + } + + return (baudrate); +} + +// Control SWO Capture (UART) +// active: active flag +// return: 1 - Success, 0 - Error +__WEAK uint32_t SWO_Control_UART (uint32_t active) { + int32_t status; + + if (active) { + if (!USART_Ready) { + return (0U); + } + TraceBlockSize = 1U; + status = pUSART->Receive(&TraceBuf[0], 1U); + if (status != ARM_DRIVER_OK) { + return (0U); + } + status = pUSART->Control(ARM_USART_CONTROL_RX, 1U); + if (status != ARM_DRIVER_OK) { + return (0U); + } + } else { + pUSART->Control(ARM_USART_CONTROL_RX, 0U); + if (pUSART->GetStatus().rx_busy) { + TraceIndexI += pUSART->GetRxCount(); + pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U); + } + } + return (1U); +} + +// Start SWO Capture (UART) +// buf: pointer to buffer for capturing +// num: number of bytes to capture +__WEAK void SWO_Capture_UART (uint8_t *buf, uint32_t num) { + TraceBlockSize = num; + pUSART->Receive(buf, num); +} + +// Get SWO Pending Trace Count (UART) +// return: number of pending trace data bytes +__WEAK uint32_t SWO_GetCount_UART (void) { + uint32_t count; + + if (pUSART->GetStatus().rx_busy) { + count = pUSART->GetRxCount(); + } else { + count = 0U; + } + return (count); +} + +#endif /* (SWO_UART != 0) */ + + +#if (SWO_MANCHESTER != 0) + +// Enable or disable SWO Mode (Manchester) +// enable: enable flag +// return: 1 - Success, 0 - Error +__WEAK uint32_t SWO_Mode_Manchester (uint32_t enable) { + return (0U); +} + +// Configure SWO Baudrate (Manchester) +// baudrate: requested baudrate +// return: actual baudrate or 0 when not configured +__WEAK uint32_t SWO_Baudrate_Manchester (uint32_t baudrate) { + return (0U); +} + +// Control SWO Capture (Manchester) +// active: active flag +// return: 1 - Success, 0 - Error +__WEAK uint32_t SWO_Control_Manchester (uint32_t active) { + return (0U); +} + +// Start SWO Capture (Manchester) +// buf: pointer to buffer for capturing +// num: number of bytes to capture +__WEAK void SWO_Capture_Manchester (uint8_t *buf, uint32_t num) { +} + +// Get SWO Pending Trace Count (Manchester) +// return: number of pending trace data bytes +__WEAK uint32_t SWO_GetCount_Manchester (void) { +} + +#endif /* (SWO_MANCHESTER != 0) */ + + +// Clear Trace Errors and Data +static void ClearTrace (void) { + +#if (SWO_STREAM != 0) + if (TraceTransport == 2U) { + if (TransferBusy != 0U) { + SWO_AbortTransfer(); + TransferBusy = 0U; + } + } +#endif + + TraceError[0] = 0U; + TraceError[1] = 0U; + TraceError_n = 0U; + TraceIndexI = 0U; + TraceIndexO = 0U; + +#if (TIMESTAMP_CLOCK != 0U) + TraceTimestamp.index = 0U; + TraceTimestamp.tick = 0U; +#endif +} + +// Resume Trace Capture +static void ResumeTrace (void) { + uint32_t index_i; + uint32_t index_o; + + if (TraceStatus == (DAP_SWO_CAPTURE_ACTIVE | DAP_SWO_CAPTURE_PAUSED)) { + index_i = TraceIndexI; + index_o = TraceIndexO; + if ((index_i - index_o) < SWO_BUFFER_SIZE) { + index_i &= SWO_BUFFER_SIZE - 1U; + switch (TraceMode) { +#if (SWO_UART != 0) + case DAP_SWO_UART: + TraceStatus = DAP_SWO_CAPTURE_ACTIVE; + SWO_Capture_UART(&TraceBuf[index_i], 1U); + break; +#endif +#if (SWO_MANCHESTER != 0) + case DAP_SWO_MANCHESTER: + TraceStatus = DAP_SWO_CAPTURE_ACTIVE; + SWO_Capture_Manchester(&TraceBuf[index_i], 1U); + break; +#endif + default: + break; + } + } + } +} + +// Get Trace Count +// return: number of available data bytes in trace buffer +static uint32_t GetTraceCount (void) { + uint32_t count; + + if (TraceStatus == DAP_SWO_CAPTURE_ACTIVE) { + do { + TraceUpdate = 0U; + count = TraceIndexI - TraceIndexO; + switch (TraceMode) { +#if (SWO_UART != 0) + case DAP_SWO_UART: + count += SWO_GetCount_UART(); + break; +#endif +#if (SWO_MANCHESTER != 0) + case DAP_SWO_MANCHESTER: + count += SWO_GetCount_Manchester(); + break; +#endif + default: + break; + } + } while (TraceUpdate != 0U); + } else { + count = TraceIndexI - TraceIndexO; + } + + return (count); +} + +// Get Trace Status (clear Error flags) +// return: Trace Status (Active flag and Error flags) +static uint8_t GetTraceStatus (void) { + uint8_t status; + uint32_t n; + + n = TraceError_n; + TraceError_n ^= 1U; + status = TraceStatus | TraceError[n]; + TraceError[n] = 0U; + + return (status); +} + +// Set Trace Error flag(s) +// flag: error flag(s) to set +static void SetTraceError (uint8_t flag) { + TraceError[TraceError_n] |= flag; +} + + +// Process SWO Transport command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t SWO_Transport (const uint8_t *request, uint8_t *response) { + uint8_t transport; + uint32_t result; + + if ((TraceStatus & DAP_SWO_CAPTURE_ACTIVE) == 0U) { + transport = *request; + switch (transport) { + case 0U: + case 1U: +#if (SWO_STREAM != 0) + case 2U: +#endif + TraceTransport = transport; + result = 1U; + break; + default: + result = 0U; + break; + } + } else { + result = 0U; + } + + if (result != 0U) { + *response = DAP_OK; + } else { + *response = DAP_ERROR; + } + + return ((1U << 16) | 1U); +} + + +// Process SWO Mode command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t SWO_Mode (const uint8_t *request, uint8_t *response) { + uint8_t mode; + uint32_t result; + + mode = *request; + + switch (TraceMode) { +#if (SWO_UART != 0) + case DAP_SWO_UART: + SWO_Mode_UART(0U); + break; +#endif +#if (SWO_MANCHESTER != 0) + case DAP_SWO_MANCHESTER: + SWO_Mode_Manchester(0U); + break; +#endif + default: + break; + } + + switch (mode) { + case DAP_SWO_OFF: + result = 1U; + break; +#if (SWO_UART != 0) + case DAP_SWO_UART: + result = SWO_Mode_UART(1U); + break; +#endif +#if (SWO_MANCHESTER != 0) + case DAP_SWO_MANCHESTER: + result = SWO_Mode_Manchester(1U); + break; +#endif + default: + result = 0U; + break; + } + if (result != 0U) { + TraceMode = mode; + } else { + TraceMode = DAP_SWO_OFF; + } + + TraceStatus = 0U; + + if (result != 0U) { + *response = DAP_OK; + } else { + *response = DAP_ERROR; + } + + return ((1U << 16) | 1U); +} + + +// Process SWO Baudrate command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t SWO_Baudrate (const uint8_t *request, uint8_t *response) { + uint32_t baudrate; + + baudrate = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + + switch (TraceMode) { +#if (SWO_UART != 0) + case DAP_SWO_UART: + baudrate = SWO_Baudrate_UART(baudrate); + break; +#endif +#if (SWO_MANCHESTER != 0) + case DAP_SWO_MANCHESTER: + baudrate = SWO_Baudrate_Manchester(baudrate); + break; +#endif + default: + baudrate = 0U; + break; + } + + if (baudrate == 0U) { + TraceStatus = 0U; + } + + *response++ = (uint8_t)(baudrate >> 0); + *response++ = (uint8_t)(baudrate >> 8); + *response++ = (uint8_t)(baudrate >> 16); + *response = (uint8_t)(baudrate >> 24); + + return ((4U << 16) | 4U); +} + + +// Process SWO Control command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t SWO_Control (const uint8_t *request, uint8_t *response) { + uint8_t active; + uint32_t result; + + active = *request & DAP_SWO_CAPTURE_ACTIVE; + + if (active != (TraceStatus & DAP_SWO_CAPTURE_ACTIVE)) { + if (active) { + ClearTrace(); + } + switch (TraceMode) { +#if (SWO_UART != 0) + case DAP_SWO_UART: + result = SWO_Control_UART(active); + break; +#endif +#if (SWO_MANCHESTER != 0) + case DAP_SWO_MANCHESTER: + result = SWO_Control_Manchester(active); + break; +#endif + default: + result = 0U; + break; + } + if (result != 0U) { + TraceStatus = active; +#if (SWO_STREAM != 0) + if (TraceTransport == 2U) { + osThreadFlagsSet(SWO_ThreadId, 1U); + } +#endif + } + } else { + result = 1U; + } + + if (result != 0U) { + *response = DAP_OK; + } else { + *response = DAP_ERROR; + } + + return ((1U << 16) | 1U); +} + + +// Process SWO Status command and prepare response +// response: pointer to response data +// return: number of bytes in response +uint32_t SWO_Status (uint8_t *response) { + uint8_t status; + uint32_t count; + + status = GetTraceStatus(); + count = GetTraceCount(); + + *response++ = status; + *response++ = (uint8_t)(count >> 0); + *response++ = (uint8_t)(count >> 8); + *response++ = (uint8_t)(count >> 16); + *response = (uint8_t)(count >> 24); + + return (5U); +} + + +// Process SWO Extended Status command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t SWO_ExtendedStatus (const uint8_t *request, uint8_t *response) { + uint8_t cmd; + uint8_t status; + uint32_t count; +#if (TIMESTAMP_CLOCK != 0U) + uint32_t index; + uint32_t tick; +#endif + uint32_t num; + + num = 0U; + cmd = *request; + + if (cmd & 0x01U) { + status = GetTraceStatus(); + *response++ = status; + num += 1U; + } + + if (cmd & 0x02U) { + count = GetTraceCount(); + *response++ = (uint8_t)(count >> 0); + *response++ = (uint8_t)(count >> 8); + *response++ = (uint8_t)(count >> 16); + *response++ = (uint8_t)(count >> 24); + num += 4U; + } + +#if (TIMESTAMP_CLOCK != 0U) + if (cmd & 0x04U) { + do { + TraceUpdate = 0U; + index = TraceTimestamp.index; + tick = TraceTimestamp.tick; + } while (TraceUpdate != 0U); + *response++ = (uint8_t)(index >> 0); + *response++ = (uint8_t)(index >> 8); + *response++ = (uint8_t)(index >> 16); + *response++ = (uint8_t)(index >> 24); + *response++ = (uint8_t)(tick >> 0); + *response++ = (uint8_t)(tick >> 8); + *response++ = (uint8_t)(tick >> 16); + *response++ = (uint8_t)(tick >> 24); + num += 4U; + } +#endif + + return ((1U << 16) | num); +} + + +// Process SWO Data command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t SWO_Data (const uint8_t *request, uint8_t *response) { + uint8_t status; + uint32_t count; + uint32_t index; + uint32_t n, i; + + status = GetTraceStatus(); + count = GetTraceCount(); + + if (TraceTransport == 1U) { + n = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8); + if (n > (DAP_PACKET_SIZE - 4U)) { + n = DAP_PACKET_SIZE - 4U; + } + if (count > n) { + count = n; + } + } else { + count = 0U; + } + + *response++ = status; + *response++ = (uint8_t)(count >> 0); + *response++ = (uint8_t)(count >> 8); + + if (TraceTransport == 1U) { + index = TraceIndexO; + for (i = index, n = count; n; n--) { + i &= SWO_BUFFER_SIZE - 1U; + *response++ = TraceBuf[i++]; + } + TraceIndexO = index + count; + ResumeTrace(); + } + + return ((2U << 16) | (3U + count)); +} + + +#if (SWO_STREAM != 0) + +// SWO Data Transfer complete callback +void SWO_TransferComplete (void) { + TraceIndexO += TransferSize; + TransferBusy = 0U; + ResumeTrace(); + osThreadFlagsSet(SWO_ThreadId, 1U); +} + +// SWO Thread +__NO_RETURN void SWO_Thread (void *argument) { + uint32_t timeout; + uint32_t flags; + uint32_t count; + uint32_t index; + uint32_t i, n; + (void) argument; + + timeout = osWaitForever; + + for (;;) { + flags = osThreadFlagsWait(1U, osFlagsWaitAny, timeout); + if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) { + timeout = SWO_STREAM_TIMEOUT; + } else { + timeout = osWaitForever; + flags = osFlagsErrorTimeout; + } + if (TransferBusy == 0U) { + count = GetTraceCount(); + if (count != 0U) { + index = TraceIndexO & (SWO_BUFFER_SIZE - 1U); + n = SWO_BUFFER_SIZE - index; + if (count > n) { + count = n; + } + if (flags != osFlagsErrorTimeout) { + i = index & (USB_BLOCK_SIZE - 1U); + if (i == 0U) { + count &= ~(USB_BLOCK_SIZE - 1U); + } else { + n = USB_BLOCK_SIZE - i; + if (count >= n) { + count = n; + } else { + count = 0U; + } + } + } + if (count != 0U) { + TransferSize = count; + TransferBusy = 1U; + SWO_QueueTransfer(&TraceBuf[index], count); + } + } + } + } +} + +#endif /* (SWO_STREAM != 0) */ + + +#endif /* ((SWO_UART != 0) || (SWO_MANCHESTER != 0)) */ diff --git a/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Source/SW_DP.c b/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Source/SW_DP.c new file mode 100644 index 00000000..803cf421 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Source/SW_DP.c @@ -0,0 +1,286 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 1. December 2017 + * $Revision: V2.0.0 + * + * Project: CMSIS-DAP Source + * Title: SW_DP.c CMSIS-DAP SW DP I/O + * + *---------------------------------------------------------------------------*/ + +#include "DAP_config.h" +#include "DAP.h" + + +// SW Macros + +#define PIN_SWCLK_SET PIN_SWCLK_TCK_SET +#define PIN_SWCLK_CLR PIN_SWCLK_TCK_CLR + +#define SW_CLOCK_CYCLE() \ + PIN_SWCLK_CLR(); \ + PIN_DELAY(); \ + PIN_SWCLK_SET(); \ + PIN_DELAY() + +#define SW_WRITE_BIT(bit) \ + PIN_SWDIO_OUT(bit); \ + PIN_SWCLK_CLR(); \ + PIN_DELAY(); \ + PIN_SWCLK_SET(); \ + PIN_DELAY() + +#define SW_READ_BIT(bit) \ + PIN_SWCLK_CLR(); \ + PIN_DELAY(); \ + bit = PIN_SWDIO_IN(); \ + PIN_SWCLK_SET(); \ + PIN_DELAY() + +#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay) + + +// Generate SWJ Sequence +// count: sequence bit count +// data: pointer to sequence bit data +// return: none +#if ((DAP_SWD != 0) || (DAP_JTAG != 0)) +void SWJ_Sequence (uint32_t count, const uint8_t *data) { + uint32_t val; + uint32_t n; + + val = 0U; + n = 0U; + while (count--) { + if (n == 0U) { + val = *data++; + n = 8U; + } + if (val & 1U) { + PIN_SWDIO_TMS_SET(); + } else { + PIN_SWDIO_TMS_CLR(); + } + SW_CLOCK_CYCLE(); + val >>= 1; + n--; + } +} +#endif + + +// Generate SWD Sequence +// info: sequence information +// swdo: pointer to SWDIO generated data +// swdi: pointer to SWDIO captured data +// return: none +#if (DAP_SWD != 0) +void SWD_Sequence (uint32_t info, const uint8_t *swdo, uint8_t *swdi) { + uint32_t val; + uint32_t bit; + uint32_t n, k; + + n = info & SWD_SEQUENCE_CLK; + if (n == 0U) { + n = 64U; + } + + if (info & SWD_SEQUENCE_DIN) { + while (n) { + val = 0U; + for (k = 8U; k && n; k--, n--) { + SW_READ_BIT(bit); + val >>= 1; + val |= bit << 7; + } + val >>= k; + *swdi++ = (uint8_t)val; + } + } else { + while (n) { + val = *swdo++; + for (k = 8U; k && n; k--, n--) { + SW_WRITE_BIT(val); + val >>= 1; + } + } + } +} +#endif + + +#if (DAP_SWD != 0) + + +// SWD Transfer I/O +// request: A[3:2] RnW APnDP +// data: DATA[31:0] +// return: ACK[2:0] +#define SWD_TransferFunction(speed) /**/ \ +static uint8_t SWD_Transfer##speed (uint32_t request, uint32_t *data) { \ + uint32_t ack; \ + uint32_t bit; \ + uint32_t val; \ + uint32_t parity; \ + \ + uint32_t n; \ + \ + /* Packet Request */ \ + parity = 0U; \ + SW_WRITE_BIT(1U); /* Start Bit */ \ + bit = request >> 0; \ + SW_WRITE_BIT(bit); /* APnDP Bit */ \ + parity += bit; \ + bit = request >> 1; \ + SW_WRITE_BIT(bit); /* RnW Bit */ \ + parity += bit; \ + bit = request >> 2; \ + SW_WRITE_BIT(bit); /* A2 Bit */ \ + parity += bit; \ + bit = request >> 3; \ + SW_WRITE_BIT(bit); /* A3 Bit */ \ + parity += bit; \ + SW_WRITE_BIT(parity); /* Parity Bit */ \ + SW_WRITE_BIT(0U); /* Stop Bit */ \ + SW_WRITE_BIT(1U); /* Park Bit */ \ + \ + /* Turnaround */ \ + PIN_SWDIO_OUT_DISABLE(); \ + for (n = DAP_Data.swd_conf.turnaround; n; n--) { \ + SW_CLOCK_CYCLE(); \ + } \ + \ + /* Acknowledge response */ \ + SW_READ_BIT(bit); \ + ack = bit << 0; \ + SW_READ_BIT(bit); \ + ack |= bit << 1; \ + SW_READ_BIT(bit); \ + ack |= bit << 2; \ + \ + if (ack == DAP_TRANSFER_OK) { /* OK response */ \ + /* Data transfer */ \ + if (request & DAP_TRANSFER_RnW) { \ + /* Read data */ \ + val = 0U; \ + parity = 0U; \ + for (n = 32U; n; n--) { \ + SW_READ_BIT(bit); /* Read RDATA[0:31] */ \ + parity += bit; \ + val >>= 1; \ + val |= bit << 31; \ + } \ + SW_READ_BIT(bit); /* Read Parity */ \ + if ((parity ^ bit) & 1U) { \ + ack = DAP_TRANSFER_ERROR; \ + } \ + if (data) { *data = val; } \ + /* Turnaround */ \ + for (n = DAP_Data.swd_conf.turnaround; n; n--) { \ + SW_CLOCK_CYCLE(); \ + } \ + PIN_SWDIO_OUT_ENABLE(); \ + } else { \ + /* Turnaround */ \ + for (n = DAP_Data.swd_conf.turnaround; n; n--) { \ + SW_CLOCK_CYCLE(); \ + } \ + PIN_SWDIO_OUT_ENABLE(); \ + /* Write data */ \ + val = *data; \ + parity = 0U; \ + for (n = 32U; n; n--) { \ + SW_WRITE_BIT(val); /* Write WDATA[0:31] */ \ + parity += val; \ + val >>= 1; \ + } \ + SW_WRITE_BIT(parity); /* Write Parity Bit */ \ + } \ + /* Capture Timestamp */ \ + if (request & DAP_TRANSFER_TIMESTAMP) { \ + DAP_Data.timestamp = TIMESTAMP_GET(); \ + } \ + /* Idle cycles */ \ + n = DAP_Data.transfer.idle_cycles; \ + if (n) { \ + PIN_SWDIO_OUT(0U); \ + for (; n; n--) { \ + SW_CLOCK_CYCLE(); \ + } \ + } \ + PIN_SWDIO_OUT(1U); \ + return ((uint8_t)ack); \ + } \ + \ + if ((ack == DAP_TRANSFER_WAIT) || (ack == DAP_TRANSFER_FAULT)) { \ + /* WAIT or FAULT response */ \ + if (DAP_Data.swd_conf.data_phase && ((request & DAP_TRANSFER_RnW) != 0U)) { \ + for (n = 32U+1U; n; n--) { \ + SW_CLOCK_CYCLE(); /* Dummy Read RDATA[0:31] + Parity */ \ + } \ + } \ + /* Turnaround */ \ + for (n = DAP_Data.swd_conf.turnaround; n; n--) { \ + SW_CLOCK_CYCLE(); \ + } \ + PIN_SWDIO_OUT_ENABLE(); \ + if (DAP_Data.swd_conf.data_phase && ((request & DAP_TRANSFER_RnW) == 0U)) { \ + PIN_SWDIO_OUT(0U); \ + for (n = 32U+1U; n; n--) { \ + SW_CLOCK_CYCLE(); /* Dummy Write WDATA[0:31] + Parity */ \ + } \ + } \ + PIN_SWDIO_OUT(1U); \ + return ((uint8_t)ack); \ + } \ + \ + /* Protocol error */ \ + for (n = DAP_Data.swd_conf.turnaround + 32U + 1U; n; n--) { \ + SW_CLOCK_CYCLE(); /* Back off data phase */ \ + } \ + PIN_SWDIO_OUT_ENABLE(); \ + PIN_SWDIO_OUT(1U); \ + return ((uint8_t)ack); \ +} + + +#undef PIN_DELAY +#define PIN_DELAY() PIN_DELAY_FAST() +SWD_TransferFunction(Fast) + +#undef PIN_DELAY +#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay) +SWD_TransferFunction(Slow) + + +// SWD Transfer I/O +// request: A[3:2] RnW APnDP +// data: DATA[31:0] +// return: ACK[2:0] +uint8_t SWD_Transfer(uint32_t request, uint32_t *data) { + if (DAP_Data.fast_clock) { + return SWD_TransferFast(request, data); + } else { + return SWD_TransferSlow(request, data); + } +} + + +#endif /* (DAP_SWD != 0) */ diff --git a/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Source/UART.c b/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Source/UART.c new file mode 100644 index 00000000..8e9eae50 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DAP/Firmware/Source/UART.c @@ -0,0 +1,652 @@ +/* + * Copyright (c) 2021 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 1. March 2021 + * $Revision: V1.0.0 + * + * Project: CMSIS-DAP Source + * Title: UART.c CMSIS-DAP UART + * + *---------------------------------------------------------------------------*/ + +#include "DAP_config.h" +#include "DAP.h" + +#if (DAP_UART != 0) + +#ifdef DAP_FW_V1 +#error "UART Communication Port not supported in DAP V1!" +#endif + +#include "Driver_USART.h" + +#include "cmsis_os2.h" +#include + +#define UART_RX_BLOCK_SIZE 32U /* Uart Rx Block Size (must be 2^n) */ + +// USART Driver +#define _USART_Driver_(n) Driver_USART##n +#define USART_Driver_(n) _USART_Driver_(n) +extern ARM_DRIVER_USART USART_Driver_(DAP_UART_DRIVER); +#define pUSART (&USART_Driver_(DAP_UART_DRIVER)) + +// UART Configuration +#if (DAP_UART_USB_COM_PORT != 0) +static uint8_t UartTransport = DAP_UART_TRANSPORT_USB_COM_PORT; +#else +static uint8_t UartTransport = DAP_UART_TRANSPORT_NONE; +#endif + +// UART Flags +static uint8_t UartConfigured = 0U; +static uint8_t UartReceiveEnabled = 0U; +static uint8_t UartTransmitEnabled = 0U; +static uint8_t UartTransmitActive = 0U; + +// UART TX Buffer +static uint8_t UartTxBuf[DAP_UART_TX_BUFFER_SIZE]; +static volatile uint32_t UartTxIndexI = 0U; +static volatile uint32_t UartTxIndexO = 0U; + +// UART RX Buffer +static uint8_t UartRxBuf[DAP_UART_RX_BUFFER_SIZE]; +static volatile uint32_t UartRxIndexI = 0U; +static volatile uint32_t UartRxIndexO = 0U; + +// Uart Errors +static volatile uint8_t UartErrorRxDataLost = 0U; +static volatile uint8_t UartErrorFraming = 0U; +static volatile uint8_t UartErrorParity = 0U; + +// UART Transmit +static uint32_t UartTxNum = 0U; + +// Function prototypes +static uint8_t UART_Init (void); +static void UART_Uninit (void); +static uint8_t UART_Get_Status (void); +static uint8_t UART_Receive_Enable (void); +static uint8_t UART_Transmit_Enable (void); +static void UART_Receive_Disable (void); +static void UART_Transmit_Disable (void); +static void UART_Receive_Flush (void); +static void UART_Transmit_Flush (void); +static void UART_Receive (void); +static void UART_Transmit (void); + + +// USART Driver Callback function +// event: event mask +static void USART_Callback (uint32_t event) { + if (event & ARM_USART_EVENT_SEND_COMPLETE) { + UartTxIndexO += UartTxNum; + UartTransmitActive = 0U; + UART_Transmit(); + } + if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) { + UartRxIndexI += UART_RX_BLOCK_SIZE; + UART_Receive(); + } + if (event & ARM_USART_EVENT_RX_OVERFLOW) { + UartErrorRxDataLost = 1U; + } + if (event & ARM_USART_EVENT_RX_FRAMING_ERROR) { + UartErrorFraming = 1U; + } + if (event & ARM_USART_EVENT_RX_PARITY_ERROR) { + UartErrorParity = 1U; + } +} + +// Init UART +// return: DAP_OK or DAP_ERROR +static uint8_t UART_Init (void) { + int32_t status; + uint8_t ret = DAP_ERROR; + + UartConfigured = 0U; + UartReceiveEnabled = 0U; + UartTransmitEnabled = 0U; + UartTransmitActive = 0U; + UartErrorRxDataLost = 0U; + UartErrorFraming = 0U; + UartErrorParity = 0U; + UartTxIndexI = 0U; + UartTxIndexO = 0U; + UartRxIndexI = 0U; + UartRxIndexO = 0U; + UartTxNum = 0U; + + status = pUSART->Initialize(USART_Callback); + if (status == ARM_DRIVER_OK) { + status = pUSART->PowerControl(ARM_POWER_FULL); + } + if (status == ARM_DRIVER_OK) { + ret = DAP_OK; + } + + return (ret); +} + +// Un-Init UART +static void UART_Uninit (void) { + UartConfigured = 0U; + + pUSART->PowerControl(ARM_POWER_OFF); + pUSART->Uninitialize(); +} + +// Get UART Status +// return: status +static uint8_t UART_Get_Status (void) { + uint8_t status = 0U; + + if (UartReceiveEnabled != 0U) { + status |= DAP_UART_STATUS_RX_ENABLED; + } + if (UartErrorRxDataLost != 0U) { + UartErrorRxDataLost = 0U; + status |= DAP_UART_STATUS_RX_DATA_LOST; + } + if (UartErrorFraming != 0U) { + UartErrorFraming = 0U; + status |= DAP_UART_STATUS_FRAMING_ERROR; + } + if (UartErrorParity != 0U) { + UartErrorParity = 0U; + status |= DAP_UART_STATUS_PARITY_ERROR; + } + if (UartTransmitEnabled != 0U) { + status |= DAP_UART_STATUS_TX_ENABLED; + } + + return (status); +} + +// Enable UART Receive +// return: DAP_OK or DAP_ERROR +static uint8_t UART_Receive_Enable (void) { + int32_t status; + uint8_t ret = DAP_ERROR; + + if (UartReceiveEnabled == 0U) { + // Flush Buffers + UartRxIndexI = 0U; + UartRxIndexO = 0U; + + UART_Receive(); + status = pUSART->Control(ARM_USART_CONTROL_RX, 1U); + if (status == ARM_DRIVER_OK) { + UartReceiveEnabled = 1U; + ret = DAP_OK; + } + } else { + ret = DAP_OK; + } + + return (ret); +} + +// Enable UART Transmit +// return: DAP_OK or DAP_ERROR +static uint8_t UART_Transmit_Enable (void) { + int32_t status; + uint8_t ret = DAP_ERROR; + + if (UartTransmitEnabled == 0U) { + // Flush Buffers + UartTransmitActive = 0U; + UartTxIndexI = 0U; + UartTxIndexO = 0U; + UartTxNum = 0U; + + status = pUSART->Control(ARM_USART_CONTROL_TX, 1U); + if (status == ARM_DRIVER_OK) { + UartTransmitEnabled = 1U; + ret = DAP_OK; + } + } else { + ret = DAP_OK; + } + + return (ret); +} + +// Disable UART Receive +static void UART_Receive_Disable (void) { + if (UartReceiveEnabled != 0U) { + pUSART->Control(ARM_USART_CONTROL_RX, 0U); + pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U); + UartReceiveEnabled = 0U; + } +} + +// Disable UART Transmit +static void UART_Transmit_Disable (void) { + if (UartTransmitEnabled != 0U) { + pUSART->Control(ARM_USART_ABORT_SEND, 0U); + pUSART->Control(ARM_USART_CONTROL_TX, 0U); + UartTransmitActive = 0U; + UartTransmitEnabled = 0U; + } +} + +// Flush UART Receive buffer +static void UART_Receive_Flush (void) { + pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U); + UartRxIndexI = 0U; + UartRxIndexO = 0U; + if (UartReceiveEnabled != 0U) { + UART_Receive(); + } +} + +// Flush UART Transmit buffer +static void UART_Transmit_Flush (void) { + pUSART->Control(ARM_USART_ABORT_SEND, 0U); + UartTransmitActive = 0U; + UartTxIndexI = 0U; + UartTxIndexO = 0U; + UartTxNum = 0U; +} + +// Receive data from target via UART +static void UART_Receive (void) { + uint32_t index; + + index = UartRxIndexI & (DAP_UART_RX_BUFFER_SIZE - 1U); + pUSART->Receive(&UartRxBuf[index], UART_RX_BLOCK_SIZE); +} + +// Transmit available data to target via UART +static void UART_Transmit (void) { + uint32_t count; + uint32_t index; + + count = UartTxIndexI - UartTxIndexO; + index = UartTxIndexO & (DAP_UART_TX_BUFFER_SIZE - 1U); + + if (count != 0U) { + if ((index + count) <= DAP_UART_TX_BUFFER_SIZE) { + UartTxNum = count; + } else { + UartTxNum = DAP_UART_TX_BUFFER_SIZE - index; + } + UartTransmitActive = 1U; + pUSART->Send(&UartTxBuf[index], UartTxNum); + } +} + +// Process UART Transport command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t UART_Transport (const uint8_t *request, uint8_t *response) { + uint8_t transport; + uint8_t ret = DAP_ERROR; + + transport = *request; + switch (transport) { + case DAP_UART_TRANSPORT_NONE: + switch (UartTransport) { + case DAP_UART_TRANSPORT_NONE: + ret = DAP_OK; + break; + case DAP_UART_TRANSPORT_USB_COM_PORT: +#if (DAP_UART_USB_COM_PORT != 0) + USB_COM_PORT_Activate(0U); + UartTransport = DAP_UART_TRANSPORT_NONE; + ret = DAP_OK; +#endif + break; + case DAP_UART_TRANSPORT_DAP_COMMAND: + UART_Receive_Disable(); + UART_Transmit_Disable(); + UART_Uninit(); + UartTransport = DAP_UART_TRANSPORT_NONE; + ret= DAP_OK; + break; + } + break; + case DAP_UART_TRANSPORT_USB_COM_PORT: + switch (UartTransport) { + case DAP_UART_TRANSPORT_NONE: +#if (DAP_UART_USB_COM_PORT != 0) + if (USB_COM_PORT_Activate(1U) == 0U) { + UartTransport = DAP_UART_TRANSPORT_USB_COM_PORT; + ret = DAP_OK; + } +#endif + break; + case DAP_UART_TRANSPORT_USB_COM_PORT: + ret = DAP_OK; + break; + case DAP_UART_TRANSPORT_DAP_COMMAND: + UART_Receive_Disable(); + UART_Transmit_Disable(); + UART_Uninit(); + UartTransport = DAP_UART_TRANSPORT_NONE; +#if (DAP_UART_USB_COM_PORT != 0) + if (USB_COM_PORT_Activate(1U) == 0U) { + UartTransport = DAP_UART_TRANSPORT_USB_COM_PORT; + ret = DAP_OK; + } +#endif + break; + } + break; + case DAP_UART_TRANSPORT_DAP_COMMAND: + switch (UartTransport) { + case DAP_UART_TRANSPORT_NONE: + ret = UART_Init(); + if (ret == DAP_OK) { + UartTransport = DAP_UART_TRANSPORT_DAP_COMMAND; + } + break; + case DAP_UART_TRANSPORT_USB_COM_PORT: +#if (DAP_UART_USB_COM_PORT != 0) + USB_COM_PORT_Activate(0U); + UartTransport = DAP_UART_TRANSPORT_NONE; +#endif + ret = UART_Init(); + if (ret == DAP_OK) { + UartTransport = DAP_UART_TRANSPORT_DAP_COMMAND; + } + break; + case DAP_UART_TRANSPORT_DAP_COMMAND: + ret = DAP_OK; + break; + } + break; + default: + break; + } + + *response = ret; + + return ((1U << 16) | 1U); +} + +// Process UART Configure command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t UART_Configure (const uint8_t *request, uint8_t *response) { + uint8_t control, status; + uint32_t baudrate; + int32_t result; + + if (UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) { + status = DAP_UART_CFG_ERROR_DATA_BITS | + DAP_UART_CFG_ERROR_PARITY | + DAP_UART_CFG_ERROR_STOP_BITS; + baudrate = 0U; // baudrate error + } else { + + status = 0U; + control = *request; + baudrate = (uint32_t)(*(request+1) << 0) | + (uint32_t)(*(request+2) << 8) | + (uint32_t)(*(request+3) << 16) | + (uint32_t)(*(request+4) << 24); + + result = pUSART->Control(control | + ARM_USART_MODE_ASYNCHRONOUS | + ARM_USART_FLOW_CONTROL_NONE, + baudrate); + if (result == ARM_DRIVER_OK) { + UartConfigured = 1U; + } else { + UartConfigured = 0U; + switch (result) { + case ARM_USART_ERROR_BAUDRATE: + status = 0U; + baudrate = 0U; + break; + case ARM_USART_ERROR_DATA_BITS: + status = DAP_UART_CFG_ERROR_DATA_BITS; + break; + case ARM_USART_ERROR_PARITY: + status = DAP_UART_CFG_ERROR_PARITY; + break; + case ARM_USART_ERROR_STOP_BITS: + status = DAP_UART_CFG_ERROR_STOP_BITS; + break; + default: + status = DAP_UART_CFG_ERROR_DATA_BITS | + DAP_UART_CFG_ERROR_PARITY | + DAP_UART_CFG_ERROR_STOP_BITS; + baudrate = 0U; + break; + } + } + } + + *response++ = status; + *response++ = (uint8_t)(baudrate >> 0); + *response++ = (uint8_t)(baudrate >> 8); + *response++ = (uint8_t)(baudrate >> 16); + *response = (uint8_t)(baudrate >> 24); + + return ((5U << 16) | 5U); +} + +// Process UART Control command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t UART_Control (const uint8_t *request, uint8_t *response) { + uint8_t control; + uint8_t result; + uint8_t ret = DAP_OK; + + if (UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) { + ret = DAP_ERROR; + } else { + + control = *request; + + if ((control & DAP_UART_CONTROL_RX_DISABLE) != 0U) { + // Receive disable + UART_Receive_Disable(); + } else if ((control & DAP_UART_CONTROL_RX_ENABLE) != 0U) { + // Receive enable + if (UartConfigured != 0U) { + result = UART_Receive_Enable(); + if (result != DAP_OK) { + ret = DAP_ERROR; + } + } else { + ret = DAP_ERROR; + } + } + if ((control & DAP_UART_CONTROL_RX_BUF_FLUSH) != 0U) { + UART_Receive_Flush(); + } + + if ((control & DAP_UART_CONTROL_TX_DISABLE) != 0U) { + // Transmit disable + UART_Transmit_Disable(); + } else if ((control & DAP_UART_CONTROL_TX_ENABLE) != 0U) { + // Transmit enable + if (UartConfigured != 0U) { + result = UART_Transmit_Enable(); + if (result != DAP_OK) { + ret = DAP_ERROR; + } + } else { + ret = DAP_ERROR; + } + } + if ((control & DAP_UART_CONTROL_TX_BUF_FLUSH) != 0U) { + UART_Transmit_Flush(); + } + } + + *response = ret; + + return ((1U << 16) | 1U); +} + +// Process UART Status command and prepare response +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t UART_Status (uint8_t *response) { + uint32_t rx_cnt, tx_cnt; + uint32_t cnt; + uint8_t status; + + if ((UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) || + (UartConfigured == 0U)) { + rx_cnt = 0U; + tx_cnt = 0U; + status = 0U; + } else { + + rx_cnt = UartRxIndexI - UartRxIndexO; + rx_cnt += pUSART->GetRxCount(); + if (rx_cnt > (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2))) { + // Overflow + UartErrorRxDataLost = 1U; + rx_cnt = (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2)); + UartRxIndexO = UartRxIndexI - rx_cnt; + } + + tx_cnt = UartTxIndexI - UartTxIndexO; + cnt = pUSART->GetTxCount(); + if (UartTransmitActive != 0U) { + tx_cnt -= cnt; + } + + status = UART_Get_Status(); + } + + *response++ = status; + *response++ = (uint8_t)(rx_cnt >> 0); + *response++ = (uint8_t)(rx_cnt >> 8); + *response++ = (uint8_t)(rx_cnt >> 16); + *response++ = (uint8_t)(rx_cnt >> 24); + *response++ = (uint8_t)(tx_cnt >> 0); + *response++ = (uint8_t)(tx_cnt >> 8); + *response++ = (uint8_t)(tx_cnt >> 16); + *response = (uint8_t)(tx_cnt >> 24); + + return ((0U << 16) | 9U); +} + +// Process UART Transfer command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t UART_Transfer (const uint8_t *request, uint8_t *response) { + uint32_t rx_cnt, tx_cnt; + uint32_t rx_num, tx_num; + uint8_t *rx_data; + const + uint8_t *tx_data; + uint32_t num; + uint32_t index; + uint8_t status; + + if (UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) { + status = 0U; + rx_cnt = 0U; + tx_cnt = 0U; + } else { + + // RX Data + rx_cnt = ((uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8)); + + if (rx_cnt > (DAP_PACKET_SIZE - 6U)) { + rx_cnt = (DAP_PACKET_SIZE - 6U); + } + rx_num = UartRxIndexI - UartRxIndexO; + rx_num += pUSART->GetRxCount(); + if (rx_num > (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2))) { + // Overflow + UartErrorRxDataLost = 1U; + rx_num = (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2)); + UartRxIndexO = UartRxIndexI - rx_num; + } + if (rx_cnt > rx_num) { + rx_cnt = rx_num; + } + + rx_data = (response+5); + index = UartRxIndexO & (DAP_UART_RX_BUFFER_SIZE - 1U); + if ((index + rx_cnt) <= DAP_UART_RX_BUFFER_SIZE) { + memcpy( rx_data, &UartRxBuf[index], rx_cnt); + } else { + num = DAP_UART_RX_BUFFER_SIZE - index; + memcpy( rx_data, &UartRxBuf[index], num); + memcpy(&rx_data[num], &UartRxBuf[0], rx_cnt - num); + } + UartRxIndexO += rx_cnt; + + // TX Data + tx_cnt = ((uint32_t)(*(request+2) << 0) | + (uint32_t)(*(request+3) << 8)); + tx_data = (request+4); + + if (tx_cnt > (DAP_PACKET_SIZE - 5U)) { + tx_cnt = (DAP_PACKET_SIZE - 5U); + } + tx_num = UartTxIndexI - UartTxIndexO; + num = pUSART->GetTxCount(); + if (UartTransmitActive != 0U) { + tx_num -= num; + } + if (tx_cnt > (DAP_UART_TX_BUFFER_SIZE - tx_num)) { + tx_cnt = (DAP_UART_TX_BUFFER_SIZE - tx_num); + } + + index = UartTxIndexI & (DAP_UART_TX_BUFFER_SIZE - 1U); + if ((index + tx_cnt) <= DAP_UART_TX_BUFFER_SIZE) { + memcpy(&UartTxBuf[index], tx_data, tx_cnt); + } else { + num = DAP_UART_TX_BUFFER_SIZE - index; + memcpy(&UartTxBuf[index], tx_data, num); + memcpy(&UartTxBuf[0], &tx_data[num], tx_cnt - num); + } + UartTxIndexI += tx_cnt; + + if (UartTransmitActive == 0U) { + UART_Transmit(); + } + + status = UART_Get_Status(); + } + + *response++ = status; + *response++ = (uint8_t)(tx_cnt >> 0); + *response++ = (uint8_t)(tx_cnt >> 8); + *response++ = (uint8_t)(rx_cnt >> 0); + *response = (uint8_t)(rx_cnt >> 8); + + return (((4U + tx_cnt) << 16) | (5U + rx_cnt)); +} + +#endif /* DAP_UART */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/ComputeLibrary/Include/NEMath.h b/benchmark/interface/Drivers/CMSIS/DSP/ComputeLibrary/Include/NEMath.h new file mode 100644 index 00000000..29838bdf --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/ComputeLibrary/Include/NEMath.h @@ -0,0 +1,414 @@ +/* + * Copyright (c) 2016, 2019 ARM Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef __ARM_COMPUTE_NEMATH_H__ +#define __ARM_COMPUTE_NEMATH_H__ + + +#if defined(ARM_MATH_NEON) +/** Calculate floor of a vector. + * + * @param[in] val Input vector value in F32 format. + * + * @return The calculated floor vector. + */ +static inline float32x4_t vfloorq_f32(float32x4_t val); + +/** Calculate inverse square root. + * + * @param[in] x Input value. + * + * @return The calculated inverse square root. + */ +static inline float32x2_t vinvsqrt_f32(float32x2_t x); + +/** Calculate inverse square root. + * + * @param[in] x Input value. + * + * @return The calculated inverse square root. + */ +static inline float32x4_t vinvsqrtq_f32(float32x4_t x); + +/** Calculate reciprocal. + * + * @param[in] x Input value. + * + * @return The calculated reciprocal. + */ +static inline float32x2_t vinv_f32(float32x2_t x); + +/** Calculate reciprocal. + * + * @param[in] x Input value. + * + * @return The calculated reciprocal. + */ +static inline float32x4_t vinvq_f32(float32x4_t x); + +/** Perform a 7th degree polynomial approximation using Estrin's method. + * + * @param[in] x Input vector value in F32 format. + * @param[in] coeffs Polynomial coefficients table. (array of flattened float32x4_t vectors) + * + * @return The calculated approximation. + */ +static inline float32x4_t vtaylor_polyq_f32(float32x4_t x, const float32_t *coeffs); + +/** Calculate exponential + * + * @param[in] x Input vector value in F32 format. + * + * @return The calculated exponent. + */ +static inline float32x4_t vexpq_f32(float32x4_t x); + +/** Calculate logarithm + * + * @param[in] x Input vector value in F32 format. + * + * @return The calculated logarithm. + */ +static inline float32x4_t vlogq_f32(float32x4_t x); + +/** Calculate hyperbolic tangent. + * + * tanh(x) = (e^2x - 1)/(e^2x + 1) + * + * @note We clamp x to [-5,5] to avoid overflowing issues. + * + * @param[in] val Input vector value in F32 format. + * + * @return The calculated Hyperbolic Tangent. + */ +static inline float32x4_t vtanhq_f32(float32x4_t val); + +/** Calculate n power of a number. + * + * pow(x,n) = e^(n*log(x)) + * + * @param[in] val Input vector value in F32 format. + * @param[in] n Powers to raise the input to. + * + * @return The calculated power. + */ +static inline float32x4_t vpowq_f32(float32x4_t val, float32x4_t n); + +#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +/** Calculate hyperbolic tangent. + * + * tanh(x) = (e^2x - 1)/(e^2x + 1) + * + * @note We clamp x to [-5,5] to avoid overflowing issues. + * + * @param[in] val Input vector value in F32 format. + * + * @return The calculated Hyperbolic Tangent. + */ +static inline float16x8_t vtanhq_f16(float16x8_t val); + +/** Calculate reciprocal. + * + * @param[in] x Input value. + * + * @return The calculated reciprocal. + */ +static inline float16x4_t vinv_f16(float16x4_t x); + +/** Calculate reciprocal. + * + * @param[in] x Input value. + * + * @return The calculated reciprocal. + */ +static inline float16x8_t vinvq_f16(float16x8_t x); + +/** Calculate inverse square root. + * + * @param[in] x Input value. + * + * @return The calculated inverse square root. + */ +static inline float16x4_t vinvsqrt_f16(float16x4_t x); + +/** Calculate inverse square root. + * + * @param[in] x Input value. + * + * @return The calculated inverse square root. + */ +static inline float16x8_t vinvsqrtq_f16(float16x8_t x); + +/** Calculate exponential + * + * @param[in] x Input vector value in F16 format. + * + * @return The calculated exponent. + */ +static inline float16x8_t vexpq_f16(float16x8_t x); + +/** Calculate n power of a number. + * + * pow(x,n) = e^(n*log(x)) + * + * @param[in] val Input vector value in F16 format. + * @param[in] n Powers to raise the input to. + * + * @return The calculated power. + */ +static inline float16x8_t vpowq_f16(float16x8_t val, float16x8_t n); +#endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */ + +/** Exponent polynomial coefficients */ +extern const float32_t exp_tab[4*8]; + + +/** Logarithm polynomial coefficients */ +extern const float32_t log_tab[4*8]; + +#ifndef DOXYGEN_SKIP_THIS +inline float32x4_t vfloorq_f32(float32x4_t val) +{ + static const float32_t CONST_1[4] = {1.f,1.f,1.f,1.f}; + + const int32x4_t z = vcvtq_s32_f32(val); + const float32x4_t r = vcvtq_f32_s32(z); + + return vbslq_f32(vcgtq_f32(r, val), vsubq_f32(r, vld1q_f32(CONST_1)), r); +} + +inline float32x2_t vinvsqrt_f32(float32x2_t x) +{ + float32x2_t sqrt_reciprocal = vrsqrte_f32(x); + sqrt_reciprocal = vmul_f32(vrsqrts_f32(vmul_f32(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal); + sqrt_reciprocal = vmul_f32(vrsqrts_f32(vmul_f32(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal); + + return sqrt_reciprocal; +} + +inline float32x4_t vinvsqrtq_f32(float32x4_t x) +{ + float32x4_t sqrt_reciprocal = vrsqrteq_f32(x); + sqrt_reciprocal = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal); + sqrt_reciprocal = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal); + + return sqrt_reciprocal; +} + +inline float32x2_t vinv_f32(float32x2_t x) +{ + float32x2_t recip = vrecpe_f32(x); + recip = vmul_f32(vrecps_f32(x, recip), recip); + recip = vmul_f32(vrecps_f32(x, recip), recip); + return recip; +} + +inline float32x4_t vinvq_f32(float32x4_t x) +{ + float32x4_t recip = vrecpeq_f32(x); + recip = vmulq_f32(vrecpsq_f32(x, recip), recip); + recip = vmulq_f32(vrecpsq_f32(x, recip), recip); + return recip; +} + +inline float32x4_t vtaylor_polyq_f32(float32x4_t x, const float32_t *coeffs) +{ + float32x4_t A = vmlaq_f32(vld1q_f32(&coeffs[4*0]), vld1q_f32(&coeffs[4*4]), x); + float32x4_t B = vmlaq_f32(vld1q_f32(&coeffs[4*2]), vld1q_f32(&coeffs[4*6]), x); + float32x4_t C = vmlaq_f32(vld1q_f32(&coeffs[4*1]), vld1q_f32(&coeffs[4*5]), x); + float32x4_t D = vmlaq_f32(vld1q_f32(&coeffs[4*3]), vld1q_f32(&coeffs[4*7]), x); + float32x4_t x2 = vmulq_f32(x, x); + float32x4_t x4 = vmulq_f32(x2, x2); + float32x4_t res = vmlaq_f32(vmlaq_f32(A, B, x2), vmlaq_f32(C, D, x2), x4); + return res; +} + +inline float32x4_t vexpq_f32(float32x4_t x) +{ + static const float32_t CONST_LN2[4] = {0.6931471805f,0.6931471805f,0.6931471805f,0.6931471805f}; // ln(2) + static const float32_t CONST_INV_LN2[4] = {1.4426950408f,1.4426950408f,1.4426950408f,1.4426950408f}; // 1/ln(2) + static const float32_t CONST_0[4] = {0.f,0.f,0.f,0.f}; + static const int32_t CONST_NEGATIVE_126[4] = {-126,-126,-126,-126}; + + // Perform range reduction [-log(2),log(2)] + int32x4_t m = vcvtq_s32_f32(vmulq_f32(x, vld1q_f32(CONST_INV_LN2))); + float32x4_t val = vmlsq_f32(x, vcvtq_f32_s32(m), vld1q_f32(CONST_LN2)); + + // Polynomial Approximation + float32x4_t poly = vtaylor_polyq_f32(val, exp_tab); + + // Reconstruct + poly = vreinterpretq_f32_s32(vqaddq_s32(vreinterpretq_s32_f32(poly), vqshlq_n_s32(m, 23))); + poly = vbslq_f32(vcltq_s32(m, vld1q_s32(CONST_NEGATIVE_126)), vld1q_f32(CONST_0), poly); + + return poly; +} + +inline float32x4_t vlogq_f32(float32x4_t x) +{ + static const int32_t CONST_127[4] = {127,127,127,127}; // 127 + static const float32_t CONST_LN2[4] = {0.6931471805f,0.6931471805f,0.6931471805f,0.6931471805f}; // ln(2) + + // Extract exponent + int32x4_t m = vsubq_s32(vreinterpretq_s32_u32(vshrq_n_u32(vreinterpretq_u32_f32(x), 23)), vld1q_s32(CONST_127)); + float32x4_t val = vreinterpretq_f32_s32(vsubq_s32(vreinterpretq_s32_f32(x), vshlq_n_s32(m, 23))); + + // Polynomial Approximation + float32x4_t poly = vtaylor_polyq_f32(val, log_tab); + + // Reconstruct + poly = vmlaq_f32(poly, vcvtq_f32_s32(m), vld1q_f32(CONST_LN2)); + + return poly; +} + +inline float32x4_t vtanhq_f32(float32x4_t val) +{ + static const float32_t CONST_1[4] = {1.f,1.f,1.f,1.f}; + static const float32_t CONST_2[4] = {2.f,2.f,2.f,2.f}; + static const float32_t CONST_MIN_TANH[4] = {-10.f,-10.f,-10.f,-10.f}; + static const float32_t CONST_MAX_TANH[4] = {10.f,10.f,10.f,10.f}; + + float32x4_t x = vminq_f32(vmaxq_f32(val, vld1q_f32(CONST_MIN_TANH)), vld1q_f32(CONST_MAX_TANH)); + float32x4_t exp2x = vexpq_f32(vmulq_f32(vld1q_f32(CONST_2), x)); + float32x4_t num = vsubq_f32(exp2x, vld1q_f32(CONST_1)); + float32x4_t den = vaddq_f32(exp2x, vld1q_f32(CONST_1)); + float32x4_t tanh = vmulq_f32(num, vinvq_f32(den)); + return tanh; +} + +inline float32x4_t vpowq_f32(float32x4_t val, float32x4_t n) +{ + return vexpq_f32(vmulq_f32(n, vlogq_f32(val))); +} +#endif /* DOXYGEN_SKIP_THIS */ + +#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +/** Exponent polynomial coefficients */ +/** Logarithm polynomial coefficients */ +#ifndef DOXYGEN_SKIP_THIS +inline float16x8_t vfloorq_f16(float16x8_t val) +{ + static const float16_t CONST_1[8] = {1.f,1.f,1.f,1.f,1.f,1.f,1.f,1.f}; + + const int16x8_t z = vcvtq_s16_f16(val); + const float16x8_t r = vcvtq_f16_s16(z); + + return vbslq_f16(vcgtq_f16(r, val), vsubq_f16(r, vld1q_f16(CONST_1)), r); +} +inline float16x4_t vinvsqrt_f16(float16x4_t x) +{ + float16x4_t sqrt_reciprocal = vrsqrte_f16(x); + sqrt_reciprocal = vmul_f16(vrsqrts_f16(vmul_f16(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal); + sqrt_reciprocal = vmul_f16(vrsqrts_f16(vmul_f16(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal); + return sqrt_reciprocal; +} + +inline float16x8_t vinvsqrtq_f16(float16x8_t x) +{ + float16x8_t sqrt_reciprocal = vrsqrteq_f16(x); + sqrt_reciprocal = vmulq_f16(vrsqrtsq_f16(vmulq_f16(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal); + sqrt_reciprocal = vmulq_f16(vrsqrtsq_f16(vmulq_f16(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal); + return sqrt_reciprocal; +} + +inline float16x4_t vinv_f16(float16x4_t x) +{ + float16x4_t recip = vrecpe_f16(x); + recip = vmul_f16(vrecps_f16(x, recip), recip); + recip = vmul_f16(vrecps_f16(x, recip), recip); + return recip; +} + +inline float16x8_t vinvq_f16(float16x8_t x) +{ + float16x8_t recip = vrecpeq_f16(x); + recip = vmulq_f16(vrecpsq_f16(x, recip), recip); + recip = vmulq_f16(vrecpsq_f16(x, recip), recip); + return recip; +} + +inline float16x8_t vtanhq_f16(float16x8_t val) +{ + const float16_t CONST_1[8] = {1.f,1.f,1.f,1.f,1.f,1.f,1.f,1.f}; + const float16_t CONST_2[8] = {2.f,2.f,2.f,2.f,2.f,2.f,2.f,2.f}; + const float16_t CONST_MIN_TANH[8] = {-10.f,-10.f,-10.f,-10.f,-10.f,-10.f,-10.f,-10.f}; + const float16_t CONST_MAX_TANH[8] = {10.f,10.f,10.f,10.f,10.f,10.f,10.f,10.f}; + + const float16x8_t x = vminq_f16(vmaxq_f16(val, vld1q_f16(CONST_MIN_TANH)), vld1q_f16(CONST_MAX_TANH)); + const float16x8_t exp2x = vexpq_f16(vmulq_f16(vld1q_f16(CONST_2), x)); + const float16x8_t num = vsubq_f16(exp2x, vld1q_f16(CONST_1)); + const float16x8_t den = vaddq_f16(exp2x, vld1q_f16(CONST_1)); + const float16x8_t tanh = vmulq_f16(num, vinvq_f16(den)); + return tanh; +} + +inline float16x8_t vtaylor_polyq_f16(float16x8_t x, const float16_t *coeffs) +{ + const float16x8_t A = vaddq_f16(vld1q_f16(&coeffs[8*0]), vmulq_f16(vld1q_f16(&coeffs[8*4]), x)); + const float16x8_t B = vaddq_f16(vld1q_f16(&coeffs[8*2]), vmulq_f16(vld1q_f16(&coeffs[8*6]), x)); + const float16x8_t C = vaddq_f16(vld1q_f16(&coeffs[8*1]), vmulq_f16(vld1q_f16(&coeffs[8*5]), x)); + const float16x8_t D = vaddq_f16(vld1q_f16(&coeffs[8*3]), vmulq_f16(vld1q_f16(&coeffs[8*7]), x)); + const float16x8_t x2 = vmulq_f16(x, x); + const float16x8_t x4 = vmulq_f16(x2, x2); + const float16x8_t res = vaddq_f16(vaddq_f16(A, vmulq_f16(B, x2)), vmulq_f16(vaddq_f16(C, vmulq_f16(D, x2)), x4)); + return res; +} + +inline float16x8_t vexpq_f16(float16x8_t x) +{ + // TODO (COMPMID-1535) : Revisit FP16 approximations + const float32x4_t x_high = vcvt_f32_f16(vget_high_f16(x)); + const float32x4_t x_low = vcvt_f32_f16(vget_low_f16(x)); + + const float16x8_t res = vcvt_high_f16_f32(vcvt_f16_f32(vexpq_f32(x_low)), vexpq_f32(x_high)); + return res; +} + +inline float16x8_t vlogq_f16(float16x8_t x) +{ + // TODO (COMPMID-1535) : Revisit FP16 approximations + const float32x4_t x_high = vcvt_f32_f16(vget_high_f16(x)); + const float32x4_t x_low = vcvt_f32_f16(vget_low_f16(x)); + + const float16x8_t res = vcvt_high_f16_f32(vcvt_f16_f32(vlogq_f32(x_low)), vlogq_f32(x_high)); + return res; +} + +inline float16x8_t vpowq_f16(float16x8_t val, float16x8_t n) +{ + // TODO (giaiod01) - COMPMID-1535 + float32x4_t n0_f32 = vcvt_f32_f16(vget_low_f16(n)); + float32x4_t n1_f32 = vcvt_f32_f16(vget_high_f16(n)); + float32x4_t val0_f32 = vcvt_f32_f16(vget_low_f16(val)); + float32x4_t val1_f32 = vcvt_f32_f16(vget_high_f16(val)); + + float32x4_t res0_f32 = vexpq_f32(vmulq_f32(n0_f32, vlogq_f32(val0_f32))); + float32x4_t res1_f32 = vexpq_f32(vmulq_f32(n1_f32, vlogq_f32(val1_f32))); + + return vcombine_f16(vcvt_f16_f32(res0_f32), vcvt_f16_f32(res1_f32)); +} +#endif /* DOXYGEN_SKIP_THIS */ +#endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */ +#endif +#endif /* __ARM_COMPUTE_NEMATH_H__ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/ComputeLibrary/LICENSE.txt b/benchmark/interface/Drivers/CMSIS/DSP/ComputeLibrary/LICENSE.txt new file mode 100644 index 00000000..54292789 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/ComputeLibrary/LICENSE.txt @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2017-2019 ARM Software + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/benchmark/interface/Drivers/CMSIS/DSP/ComputeLibrary/Source/arm_cl_tables.c b/benchmark/interface/Drivers/CMSIS/DSP/ComputeLibrary/Source/arm_cl_tables.c new file mode 100644 index 00000000..bdd39a6b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/ComputeLibrary/Source/arm_cl_tables.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2016, 2019 ARM Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#include "arm_math.h" +#include "NEMath.h" + +#if defined(ARM_MATH_NEON) + +/** Exponent polynomial coefficients */ +const float32_t exp_tab[4*8] = +{ + 1.f,1.f,1.f,1.f, + 0.0416598916054f,0.0416598916054f,0.0416598916054f,0.0416598916054f, + 0.500000596046f,0.500000596046f,0.500000596046f,0.500000596046f, + 0.0014122662833f,0.0014122662833f,0.0014122662833f,0.0014122662833f, + 1.00000011921f,1.00000011921f,1.00000011921f,1.00000011921f, + 0.00833693705499f,0.00833693705499f,0.00833693705499f,0.00833693705499f, + 0.166665703058f,0.166665703058f,0.166665703058f,0.166665703058f, + 0.000195780929062f,0.000195780929062f,0.000195780929062f,0.000195780929062f +}; + +/** Logarithm polynomial coefficients */ +const float32_t log_tab[4*8] = +{ + -2.29561495781f,-2.29561495781f,-2.29561495781f,-2.29561495781f, + -2.47071170807f,-2.47071170807f,-2.47071170807f,-2.47071170807f, + -5.68692588806f,-5.68692588806f,-5.68692588806f,-5.68692588806f, + -0.165253549814f,-0.165253549814f,-0.165253549814f,-0.165253549814f, + 5.17591238022f,5.17591238022f,5.17591238022f,5.17591238022f, + 0.844007015228f,0.844007015228f,0.844007015228f,0.844007015228f, + 4.58445882797f,4.58445882797f,4.58445882797f,4.58445882797f, + 0.0141278216615f,0.0141278216615f,0.0141278216615f,0.0141278216615f +}; + +#endif diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM0_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM0_config.txt new file mode 100644 index 00000000..13dc7839 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM3_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM3_config.txt new file mode 100644 index 00000000..55419ac8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM4_FP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM4_FP_config.txt new file mode 100644 index 00000000..fb9d24c9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM55_FP_MVE_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 00000000..4a65b1de --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM7_SP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM7_SP_config.txt new file mode 100644 index 00000000..82fc00c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/Abstract.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/Abstract.txt new file mode 100644 index 00000000..54e9bec5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_class_marks_example + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/CMakeLists.txt new file mode 100644 index 00000000..6ac92d46 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_bayes_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_bayes_example) + + +include(config) +configApp(arm_bayes_example ${ROOT}) + +target_sources(arm_bayes_example PRIVATE arm_bayes_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_bayes_example PRIVATE CMSISDSP) + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 00000000..f527fa11 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM0/system_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 00000000..66a364c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 00000000..0392a899 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM3/system_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 00000000..3c5eda7d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 00000000..90eee9dc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 00000000..9d983d2e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 00000000..0ab7e3e9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM55/system_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 00000000..b76ebb7c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 00000000..78584996 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 00000000..75f9c18e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/arm_bayes_example_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/arm_bayes_example_f32.c new file mode 100644 index 00000000..1be97d60 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/arm_bayes_example_f32.c @@ -0,0 +1,145 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2019-2020 ARM Limited. All rights reserved. +* +* $Date: 09. December 2019 +* $Revision: V1.0.0 +* +* Project: CMSIS DSP Library +* Title: arm_bayes_example_f32.c +* +* Description: Example code demonstrating how to use Bayes functions. +* +* Target Processor: Cortex-M/Cortex-A +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup BayesExample Bayes Example + * + * \par Description: + * \par + * Demonstrates the use of Bayesian classifier functions. It is complementing the tutorial + * about classical ML with CMSIS-DSP and python scikit-learn: + * https://developer.arm.com/solutions/machine-learning-on-arm/developer-material/how-to-guides/implement-classical-ml-with-arm-cmsis-dsp-libraries + * + */ + + +/** \example arm_bayes_example_f32.c + */ + +#include +#include +#include "arm_math.h" + +/* +Those parameters can be generated with the python library scikit-learn. +*/ +arm_gaussian_naive_bayes_instance_f32 S; + +#define NB_OF_CLASSES 3 +#define VECTOR_DIMENSION 2 + +const float32_t theta[NB_OF_CLASSES*VECTOR_DIMENSION] = { + 1.4539529436590528f, 0.8722776016801852f, + -1.5267934452462473f, 0.903204577814203f, + -0.15338006360932258f, -2.9997913665803964f +}; /**< Mean values for the Gaussians */ + +const float32_t sigma[NB_OF_CLASSES*VECTOR_DIMENSION] = { + 1.0063470889514925f, 0.9038018246524426f, + 1.0224479953244736f, 0.7768764290432544f, + 1.1217662403241206f, 1.2303890106020325f +}; /**< Variances for the Gaussians */ + +const float32_t classPriors[NB_OF_CLASSES] = { + 0.3333333333333333f, 0.3333333333333333f, 0.3333333333333333f +}; /**< Class prior probabilities */ + +int32_t main(void) +{ + /* Array of input data */ + float32_t in[2]; + + /* Result of the classifier */ + float32_t result[NB_OF_CLASSES]; + float32_t temp[NB_OF_CLASSES]; + float32_t maxProba; + uint32_t index; + + S.vectorDimension = VECTOR_DIMENSION; + S.numberOfClasses = NB_OF_CLASSES; + S.theta = theta; + S.sigma = sigma; + S.classPriors = classPriors; + S.epsilon=4.328939296523643e-09f; + + in[0] = 1.5f; + in[1] = 1.0f; + + index = arm_gaussian_naive_bayes_predict_f32(&S, in, result,temp); + + maxProba = result[index]; + +#if defined(SEMIHOSTING) + printf("Class = %d\n", index); +#endif + + in[0] = -1.5f; + in[1] = 1.0f; + + index = arm_gaussian_naive_bayes_predict_f32(&S, in, result,temp); + + maxProba = result[index]; + +#if defined(SEMIHOSTING) + printf("Class = %d\n", index); +#endif + + in[0] = 0.0f; + in[1] = -3.0f; + + index = arm_gaussian_naive_bayes_predict_f32(&S, in, result,temp); + + maxProba = result[index]; + +#if defined(SEMIHOSTING) + printf("Class = %d\n", index); +#endif + +#if !defined(SEMIHOSTING) + while (1); /* main function does not return */ +#endif +} + + + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM0_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM0_config.txt new file mode 100644 index 00000000..13dc7839 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM3_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM3_config.txt new file mode 100644 index 00000000..55419ac8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM4_FP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM4_FP_config.txt new file mode 100644 index 00000000..fb9d24c9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM55_FP_MVE_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 00000000..4a65b1de --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM7_SP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM7_SP_config.txt new file mode 100644 index 00000000..82fc00c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/Abstract.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/Abstract.txt new file mode 100644 index 00000000..54e9bec5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_class_marks_example + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/CMakeLists.txt new file mode 100644 index 00000000..a987446d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_class_marks_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_class_marks_example) + + +include(config) +configApp(arm_class_marks_example ${ROOT}) + +target_sources(arm_class_marks_example PRIVATE arm_class_marks_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_class_marks_example PRIVATE CMSISDSP) + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 00000000..f527fa11 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/system_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 00000000..66a364c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 00000000..0392a899 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/system_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 00000000..3c5eda7d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 00000000..90eee9dc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 00000000..9d983d2e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 00000000..0ab7e3e9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM55/system_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 00000000..b76ebb7c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 00000000..78584996 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 00000000..75f9c18e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c new file mode 100644 index 00000000..1bc2ad18 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c @@ -0,0 +1,221 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_class_marks_example_f32.c +* +* Description: Example code to calculate Minimum, Maximum +* Mean, std and variance of marks obtained in a class +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup ClassMarks Class Marks Example + * + * \par Description: + * \par + * Demonstrates the use the Maximum, Minimum, Mean, Standard Deviation, Variance + * and Matrix functions to calculate statistical values of marks obtained in a class. + * + * \note This example also demonstrates the usage of static initialization. + * + * \par Variables Description: + * \par + * \li \c testMarks_f32 points to the marks scored by 20 students in 4 subjects + * \li \c max_marks Maximum of all marks + * \li \c min_marks Minimum of all marks + * \li \c mean Mean of all marks + * \li \c var Variance of the marks + * \li \c std Standard deviation of the marks + * \li \c numStudents Total number of students in the class + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_mat_init_f32() + * - arm_mat_mult_f32() + * - arm_max_f32() + * - arm_min_f32() + * - arm_mean_f32() + * - arm_std_f32() + * - arm_var_f32() + * + * Refer + * \link arm_class_marks_example_f32.c \endlink + * + */ + + +/** \example arm_class_marks_example_f32.c + */ +#include "arm_math.h" + +#if defined(SEMIHOSTING) +#include +#endif + +#define USE_STATIC_INIT + + /* ---------------------------------------------------------------------- +** Global defines +** ------------------------------------------------------------------- */ + +#define TEST_LENGTH_SAMPLES (20*4) + +/* ---------------------------------------------------------------------- +** List of Marks scored by 20 students for 4 subjects +** ------------------------------------------------------------------- */ +const float32_t testMarks_f32[TEST_LENGTH_SAMPLES] = +{ + 42.000000, 37.000000, 81.000000, 28.000000, + 83.000000, 72.000000, 36.000000, 38.000000, + 32.000000, 51.000000, 63.000000, 64.000000, + 97.000000, 82.000000, 95.000000, 90.000000, + 66.000000, 51.000000, 54.000000, 42.000000, + 67.000000, 56.000000, 45.000000, 57.000000, + 67.000000, 69.000000, 35.000000, 52.000000, + 29.000000, 81.000000, 58.000000, 47.000000, + 38.000000, 76.000000, 100.000000, 29.000000, + 33.000000, 47.000000, 29.000000, 50.000000, + 34.000000, 41.000000, 61.000000, 46.000000, + 52.000000, 50.000000, 48.000000, 36.000000, + 47.000000, 55.000000, 44.000000, 40.000000, + 100.000000, 94.000000, 84.000000, 37.000000, + 32.000000, 71.000000, 47.000000, 77.000000, + 31.000000, 50.000000, 49.000000, 35.000000, + 63.000000, 67.000000, 40.000000, 31.000000, + 29.000000, 68.000000, 61.000000, 38.000000, + 31.000000, 28.000000, 28.000000, 76.000000, + 55.000000, 33.000000, 29.000000, 39.000000 +}; + + +/* ---------------------------------------------------------------------- +* Number of subjects X 1 +* ------------------------------------------------------------------- */ +const float32_t testUnity_f32[4] = +{ + 1.000, 1.000, 1.000, 1.000 +}; + + +/* ---------------------------------------------------------------------- +** f32 Output buffer +** ------------------------------------------------------------------- */ +static float32_t testOutput[TEST_LENGTH_SAMPLES]; + + +/* ------------------------------------------------------------------ +* Global defines +*------------------------------------------------------------------- */ +#define NUMSTUDENTS 20 +#define NUMSUBJECTS 4 + +/* ------------------------------------------------------------------ +* Global variables +*------------------------------------------------------------------- */ + + uint32_t numStudents = 20; + uint32_t numSubjects = 4; +float32_t max_marks, min_marks, mean, std, var; + uint32_t student_num; + +/* ---------------------------------------------------------------------------------- +* Main f32 test function. It returns maximum marks secured and student number +* ------------------------------------------------------------------------------- */ + +int32_t main() +{ + +#ifndef USE_STATIC_INIT + + arm_matrix_instance_f32 srcA; + arm_matrix_instance_f32 srcB; + arm_matrix_instance_f32 dstC; + + /* Input and output matrices initializations */ + arm_mat_init_f32(&srcA, numStudents, numSubjects, (float32_t *)testMarks_f32); + arm_mat_init_f32(&srcB, numSubjects, 1, (float32_t *)testUnity_f32); + arm_mat_init_f32(&dstC, numStudents, 1, testOutput); + +#else + + /* Static Initializations of Input and output matrix sizes and array */ + arm_matrix_instance_f32 srcA = {NUMSTUDENTS, NUMSUBJECTS, (float32_t *)testMarks_f32}; + arm_matrix_instance_f32 srcB = {NUMSUBJECTS, 1, (float32_t *)testUnity_f32}; + arm_matrix_instance_f32 dstC = {NUMSTUDENTS, 1, testOutput}; + +#endif + + + /* ---------------------------------------------------------------------- + *Call the Matrix multiplication process function + * ------------------------------------------------------------------- */ + arm_mat_mult_f32(&srcA, &srcB, &dstC); + + /* ---------------------------------------------------------------------- + ** Call the Max function to calculate max marks among numStudents + ** ------------------------------------------------------------------- */ + arm_max_f32(testOutput, numStudents, &max_marks, &student_num); + + /* ---------------------------------------------------------------------- + ** Call the Min function to calculate min marks among numStudents + ** ------------------------------------------------------------------- */ + arm_min_f32(testOutput, numStudents, &min_marks, &student_num); + + /* ---------------------------------------------------------------------- + ** Call the Mean function to calculate mean + ** ------------------------------------------------------------------- */ + arm_mean_f32(testOutput, numStudents, &mean); + + /* ---------------------------------------------------------------------- + ** Call the std function to calculate standard deviation + ** ------------------------------------------------------------------- */ + arm_std_f32(testOutput, numStudents, &std); + + /* ---------------------------------------------------------------------- + ** Call the var function to calculate variance + ** ------------------------------------------------------------------- */ + arm_var_f32(testOutput, numStudents, &var); + +#if defined(SEMIHOSTING) + printf("mean = %f, std = %f\n",mean,std); +#endif + +#if !defined(SEMIHOSTING) + while (1); /* main function does not return */ +#endif +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM0_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM0_config.txt new file mode 100644 index 00000000..13dc7839 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM3_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM3_config.txt new file mode 100644 index 00000000..55419ac8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM4_FP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM4_FP_config.txt new file mode 100644 index 00000000..fb9d24c9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM55_FP_MVE_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 00000000..4a65b1de --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM7_SP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM7_SP_config.txt new file mode 100644 index 00000000..82fc00c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/Abstract.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/Abstract.txt new file mode 100644 index 00000000..95aed2ed --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_convolution_example. + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/CMakeLists.txt new file mode 100644 index 00000000..c6acc7a5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_convolution_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_convolution_example) + + +include(config) +configApp(arm_convolution_example ${ROOT}) + +target_sources(arm_convolution_example PRIVATE arm_convolution_example_f32.c math_helper.c) + +### Sources and libs + +target_link_libraries(arm_convolution_example PRIVATE CMSISDSP) + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 00000000..f527fa11 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/system_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 00000000..66a364c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 00000000..0392a899 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/system_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 00000000..3c5eda7d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 00000000..90eee9dc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 00000000..9d983d2e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 00000000..0ab7e3e9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM55/system_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 00000000..b76ebb7c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 00000000..78584996 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 00000000..75f9c18e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c new file mode 100644 index 00000000..099f92e9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c @@ -0,0 +1,263 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_convolution_example_f32.c +* +* Description: Example code demonstrating Convolution of two input signals using fft. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup ConvolutionExample Convolution Example + * + * \par Description: + * \par + * Demonstrates the convolution theorem with the use of the Complex FFT, Complex-by-Complex + * Multiplication, and Support Functions. + * + * \par Algorithm: + * \par + * The convolution theorem states that convolution in the time domain corresponds to + * multiplication in the frequency domain. Therefore, the Fourier transform of the convoution of + * two signals is equal to the product of their individual Fourier transforms. + * The Fourier transform of a signal can be evaluated efficiently using the Fast Fourier Transform (FFT). + * \par + * Two input signals, a[n] and b[n], with lengths \c n1 and \c n2 respectively, + * are zero padded so that their lengths become \c N, which is greater than or equal to (n1+n2-1) + * and is a power of 4 as FFT implementation is radix-4. + * The convolution of a[n] and b[n] is obtained by taking the FFT of the input + * signals, multiplying the Fourier transforms of the two signals, and taking the inverse FFT of + * the multiplied result. + * \par + * This is denoted by the following equations: + *
 A[k] = FFT(a[n],N)
+ * B[k] = FFT(b[n],N)
+ * conv(a[n], b[n]) = IFFT(A[k] * B[k], N)
+ * where A[k] and B[k] are the N-point FFTs of the signals a[n] + * and b[n] respectively. + * The length of the convolved signal is (n1+n2-1). + * + * \par Block Diagram: + * \par + * \image html Convolution.gif + * + * \par Variables Description: + * \par + * \li \c testInputA_f32 points to the first input sequence + * \li \c srcALen length of the first input sequence + * \li \c testInputB_f32 points to the second input sequence + * \li \c srcBLen length of the second input sequence + * \li \c outLen length of convolution output sequence, (srcALen + srcBLen - 1) + * \li \c AxB points to the output array where the product of individual FFTs of inputs is stored. + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_fill_f32() + * - arm_copy_f32() + * - arm_cfft_radix4_init_f32() + * - arm_cfft_radix4_f32() + * - arm_cmplx_mult_cmplx_f32() + * + * Refer + * \link arm_convolution_example_f32.c \endlink + * + */ + + +/** \example arm_convolution_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +#if defined(SEMIHOSTING) +#include +#endif + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 128 +#define DELTA (0.000001f) +#define SNR_THRESHOLD 90 + +/* ---------------------------------------------------------------------- +* Declare I/O buffers +* ------------------------------------------------------------------- */ +float32_t Ak[MAX_BLOCKSIZE]; /* Input A */ +float32_t Bk[MAX_BLOCKSIZE]; /* Input B */ +float32_t AxB[MAX_BLOCKSIZE * 2]; /* Output */ + +/* ---------------------------------------------------------------------- +* Test input data for Floating point Convolution example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ +float32_t testInputA_f32[64] = +{ + -0.808920, 1.357369, 1.180861, -0.504544, 1.762637, -0.703285, + 1.696966, 0.620571, -0.151093, -0.100235, -0.872382, -0.403579, + -0.860749, -0.382648, -1.052338, 0.128113, -0.646269, 1.093377, + -2.209198, 0.471706, 0.408901, 1.266242, 0.598252, 1.176827, + -0.203421, 0.213596, -0.851964, -0.466958, 0.021841, -0.698938, + -0.604107, 0.461778, -0.318219, 0.942520, 0.577585, 0.417619, + 0.614665, 0.563679, -1.295073, -0.764437, 0.952194, -0.859222, + -0.618554, -2.268542, -1.210592, 1.655853, -2.627219, -0.994249, + -1.374704, 0.343799, 0.025619, 1.227481, -0.708031, 0.069355, + -1.845228, -1.570886, 1.010668, -1.802084, 1.630088, 1.286090, + -0.161050, -0.940794, 0.367961, 0.291907 + +}; + +float32_t testInputB_f32[64] = +{ + 0.933724, 0.046881, 1.316470, 0.438345, 0.332682, 2.094885, + 0.512081, 0.035546, 0.050894, -2.320371, 0.168711, -1.830493, + -0.444834, -1.003242, -0.531494, -1.365600, -0.155420, -0.757692, + -0.431880, -0.380021, 0.096243, -0.695835, 0.558850, -1.648962, + 0.020369, -0.363630, 0.887146, 0.845503, -0.252864, -0.330397, + 1.269131, -1.109295, -1.027876, 0.135940, 0.116721, -0.293399, + -1.349799, 0.166078, -0.802201, 0.369367, -0.964568, -2.266011, + 0.465178, 0.651222, -0.325426, 0.320245, -0.784178, -0.579456, + 0.093374, 0.604778, -0.048225, 0.376297, -0.394412, 0.578182, + -1.218141, -1.387326, 0.692462, -0.631297, 0.153137, -0.638952, + 0.635474, -0.970468, 1.334057, -0.111370 +}; + +const float testRefOutput_f32[127] = +{ + -0.818943, 1.229484, -0.533664, 1.016604, 0.341875, -1.963656, + 5.171476, 3.478033, 7.616361, 6.648384, 0.479069, 1.792012, + -1.295591, -7.447818, 0.315830, -10.657445, -2.483469, -6.524236, + -7.380591, -3.739005, -8.388957, 0.184147, -1.554888, 3.786508, + -1.684421, 5.400610, -1.578126, 7.403361, 8.315999, 2.080267, + 11.077776, 2.749673, 7.138962, 2.748762, 0.660363, 0.981552, + 1.442275, 0.552721, -2.576892, 4.703989, 0.989156, 8.759344, + -0.564825, -3.994680, 0.954710, -5.014144, 6.592329, 1.599488, + -13.979146, -0.391891, -4.453369, -2.311242, -2.948764, 1.761415, + -0.138322, 10.433007, -2.309103, 4.297153, 8.535523, 3.209462, + 8.695819, 5.569919, 2.514304, 5.582029, 2.060199, 0.642280, + 7.024616, 1.686615, -6.481756, 1.343084, -3.526451, 1.099073, + -2.965764, -0.173723, -4.111484, 6.528384, -6.965658, 1.726291, + 1.535172, 11.023435, 2.338401, -4.690188, 1.298210, 3.943885, + 8.407885, 5.168365, 0.684131, 1.559181, 1.859998, 2.852417, + 8.574070, -6.369078, 6.023458, 11.837963, -6.027632, 4.469678, + -6.799093, -2.674048, 6.250367, -6.809971, -3.459360, 9.112410, + -2.711621, -1.336678, 1.564249, -1.564297, -1.296760, 8.904013, + -3.230109, 6.878013, -7.819823, 3.369909, -1.657410, -2.007358, + -4.112825, 1.370685, -3.420525, -6.276605, 3.244873, -3.352638, + 1.545372, 0.902211, 0.197489, -1.408732, 0.523390, 0.348440, 0 +}; + + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +uint32_t srcALen = 64; /* Length of Input A */ +uint32_t srcBLen = 64; /* Length of Input B */ +uint32_t outLen; /* Length of convolution output */ +float32_t snr; /* output SNR */ + +int32_t main(void) +{ + arm_status status; /* Status of the example */ + arm_cfft_radix4_instance_f32 cfft_instance; /* CFFT Structure instance */ + +#if defined(SEMIHOSTING) + printf("START\n"); +#endif + + /* CFFT Structure instance pointer */ + arm_cfft_radix4_instance_f32 *cfft_instance_ptr = + (arm_cfft_radix4_instance_f32*) &cfft_instance; + + /* output length of convolution */ + outLen = srcALen + srcBLen - 1; + + /* Initialise the fft input buffers with all zeros */ + arm_fill_f32(0.0, Ak, MAX_BLOCKSIZE); + arm_fill_f32(0.0, Bk, MAX_BLOCKSIZE); + + /* Copy the input values to the fft input buffers */ + arm_copy_f32(testInputA_f32, Ak, MAX_BLOCKSIZE/2); + arm_copy_f32(testInputB_f32, Bk, MAX_BLOCKSIZE/2); + + /* Initialize the CFFT function to compute 64 point fft */ + status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 0, 1); + + /* Transform input a[n] from time domain to frequency domain A[k] */ + arm_cfft_radix4_f32(cfft_instance_ptr, Ak); + /* Transform input b[n] from time domain to frequency domain B[k] */ + arm_cfft_radix4_f32(cfft_instance_ptr, Bk); + + /* Complex Multiplication of the two input buffers in frequency domain */ + arm_cmplx_mult_cmplx_f32(Ak, Bk, AxB, MAX_BLOCKSIZE/2); + + /* Initialize the CIFFT function to compute 64 point ifft */ + status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 1, 1); + + /* Transform the multiplication output from frequency domain to time domain, + that gives the convolved output. */ + arm_cfft_radix4_f32(cfft_instance_ptr, AxB); + + /* SNR Calculation */ + snr = arm_snr_f32((float32_t *)testRefOutput_f32, AxB, srcALen + srcBLen - 1); + + /* Compare the SNR with threshold to test whether the + computed output is matched with the reference output values. */ + status = (snr <= SNR_THRESHOLD) ? ARM_MATH_TEST_FAILURE : ARM_MATH_SUCCESS; + + if (status != ARM_MATH_SUCCESS) + { +#if defined (SEMIHOSTING) + printf("FAILURE\n"); +#else + while (1); /* main function does not return */ +#endif + } + else + { +#if defined (SEMIHOSTING) + printf("SUCCESS\n"); +#else + while (1); /* main function does not return */ +#endif + } + +} + + /** \endlink */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.c new file mode 100644 index 00000000..950bf42b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.c @@ -0,0 +1,474 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/* + +Conflicting with the new clip functions in CMSIS-DSP and not used +in the examples. + +*/ +#if 0 +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + +#endif + + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.h b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.h new file mode 100644 index 00000000..a0dbdf73 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM0_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM0_config.txt new file mode 100644 index 00000000..13dc7839 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM3_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM3_config.txt new file mode 100644 index 00000000..55419ac8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM4_FP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM4_FP_config.txt new file mode 100644 index 00000000..fb9d24c9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM55_FP_MVE_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 00000000..4a65b1de --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM7_SP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM7_SP_config.txt new file mode 100644 index 00000000..82fc00c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt new file mode 100644 index 00000000..4d290d05 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_dotproduct_example. + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/CMakeLists.txt new file mode 100644 index 00000000..9f4496b0 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_dotproduct_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_dotproduct_example) + + +include(config) +configApp(arm_dotproduct_example ${ROOT}) + +target_sources(arm_dotproduct_example PRIVATE arm_dotproduct_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_dotproduct_example PRIVATE CMSISDSP) + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 00000000..f527fa11 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/system_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 00000000..66a364c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 00000000..0392a899 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/system_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 00000000..3c5eda7d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 00000000..90eee9dc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 00000000..9d983d2e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 00000000..0ab7e3e9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM55/system_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 00000000..b76ebb7c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 00000000..78584996 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 00000000..75f9c18e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c new file mode 100644 index 00000000..a94a415b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c @@ -0,0 +1,189 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_dotproduct_example_f32.c +* +* Description: Example code computing dot product of two vectors. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup DotproductExample Dot Product Example + * + * \par Description: + * \par + * Demonstrates the use of the Multiply and Add functions to perform the dot product. + * The dot product of two vectors is obtained by multiplying corresponding elements + * and summing the products. + + * \par Algorithm: + * \par + * The two input vectors \c A and \c B with length \c n, are multiplied element-by-element + * and then added to obtain dot product. + * \par + * This is denoted by the following equation: + *
  dotProduct = A[0] * B[0] + A[1] * B[1] + ... + A[n-1] * B[n-1]
+ * + * \par Block Diagram: + * \par + * \image html dotProduct.gif + * + * \par Variables Description: + * \par + * \li \c srcA_buf_f32 points to first input vector + * \li \c srcB_buf_f32 points to second input vector + * \li \c testOutput stores dot product of the two input vectors. + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_mult_f32() + * - arm_add_f32() + * + * Refer + * \link arm_dotproduct_example_f32.c \endlink + * + */ + + +/** \example arm_dotproduct_example_f32.c + */ + +#include +#include "arm_math.h" + +#if defined(SEMIHOSTING) +#include +#endif + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 32 +#define DELTA (0.000001f) + +/* ---------------------------------------------------------------------- +* Test input data for Floating point Dot Product example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ +/* ---------------------------------------------------------------------- +** Test input data of srcA for blockSize 32 +** ------------------------------------------------------------------- */ +float32_t srcA_buf_f32[MAX_BLOCKSIZE] = +{ + -0.4325648115282207, -1.6655843782380970, 0.1253323064748307, + 0.2876764203585489, -1.1464713506814637, 1.1909154656429988, + 1.1891642016521031, -0.0376332765933176, 0.3272923614086541, + 0.1746391428209245, -0.1867085776814394, 0.7257905482933027, + -0.5883165430141887, 2.1831858181971011, -0.1363958830865957, + 0.1139313135208096, 1.0667682113591888, 0.0592814605236053, + -0.0956484054836690, -0.8323494636500225, 0.2944108163926404, + -1.3361818579378040, 0.7143245518189522, 1.6235620644462707, + -0.6917757017022868, 0.8579966728282626, 1.2540014216025324, + -1.5937295764474768, -1.4409644319010200, 0.5711476236581780, + -0.3998855777153632, 0.6899973754643451 +}; + +/* ---------------------------------------------------------------------- +** Test input data of srcB for blockSize 32 +** ------------------------------------------------------------------- */ +float32_t srcB_buf_f32[MAX_BLOCKSIZE] = +{ + 1.7491401329284098, 0.1325982188803279, 0.3252281811989881, + -0.7938091410349637, 0.3149236145048914, -0.5272704888029532, + 0.9322666565031119, 1.1646643544607362, -2.0456694357357357, + -0.6443728590041911, 1.7410657940825480, 0.4867684246821860, + 1.0488288293660140, 1.4885752747099299, 1.2705014969484090, + -1.8561241921210170, 2.1343209047321410, 1.4358467535865909, + -0.9173023332875400, -1.1060770780029008, 0.8105708062681296, + 0.6985430696369063, -0.4015827425012831, 1.2687512030669628, + -0.7836083053674872, 0.2132664971465569, 0.7878984786088954, + 0.8966819356782295, -0.1869172943544062, 1.0131816724341454, + 0.2484350696132857, 0.0596083377937976 +}; + +/* Reference dot product output */ +float32_t refDotProdOut = 5.9273644806352142; + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +float32_t multOutput[MAX_BLOCKSIZE]; /* Intermediate output */ +float32_t testOutput; /* Final ouput */ + +arm_status status; /* Status of the example */ + +int32_t main(void) +{ + uint32_t i; /* Loop counter */ + float32_t diff; /* Difference between reference and test outputs */ + + /* Multiplication of two input buffers */ + arm_mult_f32(srcA_buf_f32, srcB_buf_f32, multOutput, MAX_BLOCKSIZE); + + /* Accumulate the multiplication output values to + get the dot product of the two inputs */ + for(i=0; i< MAX_BLOCKSIZE; i++) + { + arm_add_f32(&testOutput, &multOutput[i], &testOutput, 1); + } + + /* absolute value of difference between ref and test */ + diff = fabsf(refDotProdOut - testOutput); + + /* Comparison of dot product value with reference */ + status = (diff > DELTA) ? ARM_MATH_TEST_FAILURE : ARM_MATH_SUCCESS; + + if (status != ARM_MATH_SUCCESS) + { +#if defined (SEMIHOSTING) + printf("FAILURE\n"); +#else + while (1); /* main function does not return */ +#endif + } + else + { +#if defined (SEMIHOSTING) + printf("SUCCESS\n"); +#else + while (1); /* main function does not return */ +#endif + } +} + + /** \endlink */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM0_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM0_config.txt new file mode 100644 index 00000000..13dc7839 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM3_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM3_config.txt new file mode 100644 index 00000000..55419ac8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM4_FP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM4_FP_config.txt new file mode 100644 index 00000000..fb9d24c9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM55_FP_MVE_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 00000000..4a65b1de --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM7_SP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM7_SP_config.txt new file mode 100644 index 00000000..82fc00c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/Abstract.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/Abstract.txt new file mode 100644 index 00000000..8609b697 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_fft_bin_example. + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/CMakeLists.txt new file mode 100644 index 00000000..a56d0fb6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_fft_bin_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_fft_bin_example) + + +include(config) +configApp(arm_fft_bin_example ${ROOT}) + +target_sources(arm_fft_bin_example PRIVATE arm_fft_bin_data.c arm_fft_bin_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_fft_bin_example PRIVATE CMSISDSP) + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 00000000..f527fa11 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/system_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 00000000..66a364c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 00000000..0392a899 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/system_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 00000000..3c5eda7d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 00000000..90eee9dc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 00000000..9d983d2e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 00000000..0ab7e3e9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM55/system_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 00000000..b76ebb7c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 00000000..78584996 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 00000000..75f9c18e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.c new file mode 100644 index 00000000..b5159e5d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.c @@ -0,0 +1,308 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_fft_bin_data.c +* +* Description: Data file used for example code +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +Test Input signal contains 10KHz signal + Uniformly distributed white noise +** ------------------------------------------------------------------- */ + +float32_t testInput_f32_10khz[2048] = +{ +-0.865129623056441, 0.000000000000000, -2.655020678073846, 0.000000000000000, 0.600664612949661, 0.000000000000000, 0.080378093886515, 0.000000000000000, +-2.899160484012034, 0.000000000000000, 2.563004262857762, 0.000000000000000, 3.078328403304206, 0.000000000000000, 0.105906778385130, 0.000000000000000, +0.048366940168201, 0.000000000000000, -0.145696461188734, 0.000000000000000, -0.023417155362879, 0.000000000000000, 2.127729174988954, 0.000000000000000, +-1.176633086028377, 0.000000000000000, 3.690223557991855, 0.000000000000000, -0.622791766173194, 0.000000000000000, 0.722837373872203, 0.000000000000000, +2.739754205367484, 0.000000000000000, -0.062610410524552, 0.000000000000000, -0.891296810967338, 0.000000000000000, -1.845872258871811, 0.000000000000000, +1.195039415434387, 0.000000000000000, -2.177388969045026, 0.000000000000000, 1.078649103637905, 0.000000000000000, 2.570976050490193, 0.000000000000000, +-1.383551403404574, 0.000000000000000, 2.392141424058873, 0.000000000000000, 2.858002843205065, 0.000000000000000, -3.682433899725536, 0.000000000000000, +-3.488146646451150, 0.000000000000000, 1.323468578888120, 0.000000000000000, -0.099771155430726, 0.000000000000000, 1.561168082500454, 0.000000000000000, +1.025026795103179, 0.000000000000000, 0.928841900171200, 0.000000000000000, 2.930499509864950, 0.000000000000000, 2.013349089766430, 0.000000000000000, +2.381676148486737, 0.000000000000000, -3.081062307950236, 0.000000000000000, -0.389579115537544, 0.000000000000000, 0.181540149166620, 0.000000000000000, +-2.601953341353208, 0.000000000000000, 0.333435137783218, 0.000000000000000, -2.812945856162965, 0.000000000000000, 2.649109640172910, 0.000000000000000, +-1.003963025744654, 0.000000000000000, 1.552460768755035, 0.000000000000000, 0.088641345335247, 0.000000000000000, -2.519951327113426, 0.000000000000000, +-4.341348988610527, 0.000000000000000, 0.557772429359965, 0.000000000000000, -1.671267412948494, 0.000000000000000, 0.733951350960387, 0.000000000000000, +0.409263788034864, 0.000000000000000, 3.566033071952806, 0.000000000000000, 1.882565173848352, 0.000000000000000, -1.106017073793287, 0.000000000000000, +0.154456720778718, 0.000000000000000, -2.513205795512153, 0.000000000000000, 0.310978660939421, 0.000000000000000, 0.579706500111723, 0.000000000000000, +0.000086383683251, 0.000000000000000, -1.311866980897721, 0.000000000000000, 1.840007477574986, 0.000000000000000, -3.253005768451345, 0.000000000000000, +1.462584328739432, 0.000000000000000, 1.610103610851738, 0.000000000000000, 0.761914676858907, 0.000000000000000, 0.974541361089834, 0.000000000000000, +0.686845845885983, 0.000000000000000, 1.849153122025191, 0.000000000000000, 0.787800410401453, 0.000000000000000, -1.187438909666279, 0.000000000000000, +-0.754937911044720, 0.000000000000000, 0.084373858395232, 0.000000000000000, -2.600269011710521, 0.000000000000000, -0.962982842142644, 0.000000000000000, +-0.369328108540868, 0.000000000000000, 0.810791418361879, 0.000000000000000, 3.587016488699641, 0.000000000000000, -0.520776145083723, 0.000000000000000, +0.640249919627884, 0.000000000000000, 1.103122489464969, 0.000000000000000, 2.231779881455556, 0.000000000000000, -1.308035392685241, 0.000000000000000, +0.424070304330106, 0.000000000000000, -0.200383932651189, 0.000000000000000, -2.365526783356541, 0.000000000000000, -0.989114757436628, 0.000000000000000, +2.770807688959777, 0.000000000000000, -0.444172737462307, 0.000000000000000, 0.079760979374078, 0.000000000000000, -0.005199118412183, 0.000000000000000, +-0.664712668309527, 0.000000000000000, -0.624171857561896, 0.000000000000000, 0.537306979007338, 0.000000000000000, -2.575955675497642, 0.000000000000000, +1.562363235756780, 0.000000000000000, 1.814069369848895, 0.000000000000000, -1.293428583392509, 0.000000000000000, -1.026188449495686, 0.000000000000000, +-2.981771815588717, 0.000000000000000, -4.223468103075124, 0.000000000000000, 2.672674782004045, 0.000000000000000, -0.856096801117735, 0.000000000000000, +0.048517345512563, 0.000000000000000, -0.026860721136222, 0.000000000000000, 0.392932277758187, 0.000000000000000, -1.331740855093099, 0.000000000000000, +-1.894292129477081, 0.000000000000000, -1.425006468460681, 0.000000000000000, -2.721772427617057, 0.000000000000000, -1.616831100216806, 0.000000000000000, +3.551177651488947, 0.000000000000000, -0.069685667896087, 0.000000000000000, -3.134634907409102, 0.000000000000000, -0.263627598944639, 0.000000000000000, +-1.650469945991350, 0.000000000000000, -2.203580339374399, 0.000000000000000, -0.872203246123242, 0.000000000000000, 1.230782812607287, 0.000000000000000, +0.257288860093291, 0.000000000000000, 1.989083106173137, 0.000000000000000, -1.985638729453261, 0.000000000000000, -1.416185105842892, 0.000000000000000, +-1.131097688325772, 0.000000000000000, -2.245130805416057, 0.000000000000000, -1.938873996219074, 0.000000000000000, 2.043608361562645, 0.000000000000000, +-0.583727989880841, 0.000000000000000, -1.785266378212929, 0.000000000000000, 1.961457586224753, 0.000000000000000, 1.139400099963223, 0.000000000000000, +-1.979519343363991, 0.000000000000000, 2.003023322818429, 0.000000000000000, 0.229004069076829, 0.000000000000000, 3.452808862193135, 0.000000000000000, +2.882273808365857, 0.000000000000000, -1.549450501844438, 0.000000000000000, -3.283872089931876, 0.000000000000000, -0.327025884099064, 0.000000000000000, +-0.054979977136430, 0.000000000000000, -1.192280531479012, 0.000000000000000, 0.645539328365578, 0.000000000000000, 2.300832863404618, 0.000000000000000, +-1.092951789535240, 0.000000000000000, -1.017368249363773, 0.000000000000000, -0.142673056169787, 0.000000000000000, 0.831073544881250, 0.000000000000000, +-2.314612531587064, 0.000000000000000, -2.221456299106321, 0.000000000000000, 0.460261143885226, 0.000000000000000, 0.050585301888595, 0.000000000000000, +0.364373329183988, 0.000000000000000, -1.685956552069538, 0.000000000000000, 0.050664512351055, 0.000000000000000, -0.193355783902718, 0.000000000000000, +-0.158660446046828, 0.000000000000000, 2.394156453841953, 0.000000000000000, -1.562965718554525, 0.000000000000000, -2.199750600869900, 0.000000000000000, +1.544984022381773, 0.000000000000000, -1.988307216807315, 0.000000000000000, -0.628240722541046, 0.000000000000000, -1.436235771505429, 0.000000000000000, +1.677013691147313, 0.000000000000000, 1.600741781678228, 0.000000000000000, -0.757380959134706, 0.000000000000000, -4.784797439515566, 0.000000000000000, +0.265121462834569, 0.000000000000000, 3.862029485934378, 0.000000000000000, 2.386823577249430, 0.000000000000000, -3.655779745436893, 0.000000000000000, +-0.763541621368016, 0.000000000000000, -1.182140388432962, 0.000000000000000, -1.349106114858063, 0.000000000000000, -2.287533624396759, 0.000000000000000, +-0.028603745188423, 0.000000000000000, -1.353580755934427, 0.000000000000000, 0.461602380352937, 0.000000000000000, -0.059599055078928, 0.000000000000000, +-0.929946734342228, 0.000000000000000, 0.065773089295561, 0.000000000000000, 1.106565863102982, 0.000000000000000, 4.719295086373593, 0.000000000000000, +-2.108377703544395, 0.000000000000000, -2.226393620240159, 0.000000000000000, 1.375668397437521, 0.000000000000000, -0.960772428525443, 0.000000000000000, +-2.156313465390571, 0.000000000000000, 1.126060012375311, 0.000000000000000, 2.756485137030720, 0.000000000000000, 0.739639690862600, 0.000000000000000, +3.914769510295006, 0.000000000000000, 1.685232785586675, 0.000000000000000, 4.079058040970612, 0.000000000000000, -1.174598301660513, 0.000000000000000, +-2.885776587275580, 0.000000000000000, -0.241073635188767, 0.000000000000000, 3.080489872502403, 0.000000000000000, -2.051244183999421, 0.000000000000000, +0.664330486845139, 0.000000000000000, -1.697798999370016, 0.000000000000000, 1.452369423649782, 0.000000000000000, -1.523532831019280, 0.000000000000000, +0.171981186587481, 0.000000000000000, -4.685274721583927, 0.000000000000000, -1.336175835319380, 0.000000000000000, 1.419070770428945, 0.000000000000000, +-0.035791601713475, 0.000000000000000, 2.291937971632081, 0.000000000000000, -1.962559313450293, 0.000000000000000, -4.831595589339301, 0.000000000000000, +-1.857055284000925, 0.000000000000000, 2.606271522635512, 0.000000000000000, -0.576447978738030, 0.000000000000000, 0.082299166967720, 0.000000000000000, +1.888399453494614, 0.000000000000000, -3.564705298046079, 0.000000000000000, -0.939357831083889, 0.000000000000000, -1.903578203697778, 0.000000000000000, +-2.642492215447250, 0.000000000000000, -0.182990405251017, 0.000000000000000, 3.742026478011174, 0.000000000000000, 0.104295803798333, 0.000000000000000, +1.848678195370347, 0.000000000000000, -1.887384346896369, 0.000000000000000, 0.365048973046045, 0.000000000000000, -0.889638010354219, 0.000000000000000, +1.173877118428863, 0.000000000000000, -1.178562827540109, 0.000000000000000, 0.610271645685184, 0.000000000000000, 1.831284815697871, 0.000000000000000, +0.449575390102283, 0.000000000000000, 1.597171905253443, 0.000000000000000, 3.918574971904773, 0.000000000000000, 0.868104027970404, 0.000000000000000, +0.582643134746494, 0.000000000000000, 2.321256382353331, 0.000000000000000, -0.238118642223180, 0.000000000000000, -2.890287868054370, 0.000000000000000, +0.970995414625622, 0.000000000000000, 0.666137930891283, 0.000000000000000, -0.202435718709502, 0.000000000000000, 2.057930200518194, 0.000000000000000, +3.120583443719949, 0.000000000000000, -0.863945271701041, 0.000000000000000, 0.906848893874630, 0.000000000000000, -1.434124930222570, 0.000000000000000, +0.754659384848783, 0.000000000000000, -5.224154442713778, 0.000000000000000, 2.330229744098967, 0.000000000000000, 1.113946320164698, 0.000000000000000, +0.523324920322840, 0.000000000000000, 1.750740911548348, 0.000000000000000, -0.899333972913577, 0.000000000000000, 0.228705845203506, 0.000000000000000, +-1.934782624767648, 0.000000000000000, -3.508386237231303, 0.000000000000000, -2.107108523073510, 0.000000000000000, 0.380587645474815, 0.000000000000000, +-0.476200877183279, 0.000000000000000, -2.172086712642198, 0.000000000000000, 1.795372535780299, 0.000000000000000, -2.100318983391055, 0.000000000000000, +-0.022571122461405, 0.000000000000000, 0.674514020010955, 0.000000000000000, -0.148872569390857, 0.000000000000000, 0.298175890592737, 0.000000000000000, +-1.134244492493590, 0.000000000000000, -3.146848422289455, 0.000000000000000, -1.357950199087602, 0.000000000000000, 0.667362732020878, 0.000000000000000, +-3.119397998316724, 0.000000000000000, -1.189341126297637, 0.000000000000000, -1.532744386856668, 0.000000000000000, -1.672972484202534, 0.000000000000000, +-2.042283373871558, 0.000000000000000, -1.479481547595924, 0.000000000000000, -0.002668662875396, 0.000000000000000, 0.262737760129546, 0.000000000000000, +2.734456080621830, 0.000000000000000, -0.671945925075102, 0.000000000000000, -3.735078262179111, 0.000000000000000, -0.161705013319883, 0.000000000000000, +0.748963512361001, 0.000000000000000, 1.128046374367600, 0.000000000000000, 0.649651335592966, 0.000000000000000, 1.880020215025867, 0.000000000000000, +-1.095632293842306, 0.000000000000000, 1.197764876160487, 0.000000000000000, 0.323646656252985, 0.000000000000000, -1.655502751114502, 0.000000000000000, +3.666399062961496, 0.000000000000000, -0.334060899735197, 0.000000000000000, -2.119056978738397, 0.000000000000000, 3.721375117275012, 0.000000000000000, +0.044874186872307, 0.000000000000000, -2.733053897593234, 0.000000000000000, 1.590700278891042, 0.000000000000000, 3.215711772781902, 0.000000000000000, +-1.792085012843801, 0.000000000000000, -0.405797188885475, 0.000000000000000, -0.628080020080892, 0.000000000000000, -1.831815840843960, 0.000000000000000, +2.973656862522834, 0.000000000000000, -0.212032655138417, 0.000000000000000, 0.372437389437234, 0.000000000000000, -1.614030579023492, 0.000000000000000, +-0.704900996358698, 0.000000000000000, 1.123700273452105, 0.000000000000000, -0.136371848130819, 0.000000000000000, 3.020284357635585, 0.000000000000000, +-0.550211350877649, 0.000000000000000, 5.101256236381711, 0.000000000000000, 3.367051512192333, 0.000000000000000, -4.385131946669234, 0.000000000000000, +-3.967303337694391, 0.000000000000000, -0.965894936640022, 0.000000000000000, 0.328366945264681, 0.000000000000000, 0.199041562924914, 0.000000000000000, +1.067681999025495, 0.000000000000000, -1.939516091697170, 0.000000000000000, -1.092980954328824, 0.000000000000000, 0.273786079368066, 0.000000000000000, +-0.040928322190265, 0.000000000000000, -0.118368078577437, 0.000000000000000, 1.766589628899997, 0.000000000000000, 1.738321311635393, 0.000000000000000, +-2.895012794321649, 0.000000000000000, 1.213521771395142, 0.000000000000000, 0.922971726633985, 0.000000000000000, 1.091516563636489, 0.000000000000000, +3.226378465469620, 0.000000000000000, 1.149169778666974, 0.000000000000000, -1.695986327709386, 0.000000000000000, -0.974803077355813, 0.000000000000000, +-4.898035507513607, 0.000000000000000, 1.622719302889447, 0.000000000000000, 0.583891313586579, 0.000000000000000, -1.677182424094957, 0.000000000000000, +-1.915633132814685, 0.000000000000000, -1.980150370851616, 0.000000000000000, 0.604538269404190, 0.000000000000000, 0.939862406149365, 0.000000000000000, +-1.266939874246416, 0.000000000000000, -1.494771249200063, 0.000000000000000, 0.278042784093988, 0.000000000000000, 0.326627416008916, 0.000000000000000, +-1.914530157643303, 0.000000000000000, 1.908947721862196, 0.000000000000000, 0.531819285694044, 0.000000000000000, 3.056856632319658, 0.000000000000000, +-0.389241827774643, 0.000000000000000, -2.418606606780420, 0.000000000000000, 0.915299238878703, 0.000000000000000, -0.098774174295283, 0.000000000000000, +-0.906199428444304, 0.000000000000000, 0.316716451217743, 0.000000000000000, -4.367700643578311, 0.000000000000000, 1.491687997515293, 0.000000000000000, +-1.962381126288365, 0.000000000000000, -0.700829196527045, 0.000000000000000, 3.028958963615630, 0.000000000000000, -2.313461067462598, 0.000000000000000, +-1.431933239886712, 0.000000000000000, -0.831153039725342, 0.000000000000000, 3.939495598250743, 0.000000000000000, 0.342974753984771, 0.000000000000000, +-2.768330763002974, 0.000000000000000, -2.744010370019008, 0.000000000000000, 3.821352685212561, 0.000000000000000, 4.551065271455856, 0.000000000000000, +3.270136437041298, 0.000000000000000, -3.188028411950982, 0.000000000000000, -0.777075012417436, 0.000000000000000, 0.097110650265216, 0.000000000000000, +1.221216137608812, 0.000000000000000, -1.325824244541822, 0.000000000000000, -2.655296734084113, 0.000000000000000, -1.074792144885704, 0.000000000000000, +2.770401584439407, 0.000000000000000, 5.240270645610543, 0.000000000000000, 0.108576672208892, 0.000000000000000, -1.209394350650142, 0.000000000000000, +1.403344353838785, 0.000000000000000, -0.299032904177277, 0.000000000000000, 4.074959450638227, 0.000000000000000, 1.718727473952107, 0.000000000000000, +-3.061349227080806, 0.000000000000000, -1.158596888541269, 0.000000000000000, 3.381858904662625, 0.000000000000000, 0.957339964054052, 0.000000000000000, +0.179900074904899, 0.000000000000000, -3.909641902506081, 0.000000000000000, 0.805717289408649, 0.000000000000000, 2.047413793928261, 0.000000000000000, +-1.273580225826614, 0.000000000000000, -2.681359186869971, 0.000000000000000, -0.721241345822093, 0.000000000000000, -1.613090681569475, 0.000000000000000, +0.463138804815955, 0.000000000000000, 0.377223507800954, 0.000000000000000, 2.046550684968141, 0.000000000000000, 0.178508732797712, 0.000000000000000, +-0.477815330358845, 0.000000000000000, 3.763355908332053, 0.000000000000000, 1.300430303035163, 0.000000000000000, -0.214625793857725, 0.000000000000000, +1.343267891864081, 0.000000000000000, -0.340007682433245, 0.000000000000000, 2.062703194680005, 0.000000000000000, 0.042032160234235, 0.000000000000000, +0.643732569732250, 0.000000000000000, -1.913502543857589, 0.000000000000000, 3.771340762937158, 0.000000000000000, 1.050024807363386, 0.000000000000000, +-4.440489488592649, 0.000000000000000, 0.444904302066643, 0.000000000000000, 2.898702265650048, 0.000000000000000, 1.953232980548558, 0.000000000000000, +2.761564952735079, 0.000000000000000, 1.963537633260397, 0.000000000000000, -2.168858472916215, 0.000000000000000, -4.116235357699841, 0.000000000000000, +4.183678271896528, 0.000000000000000, 0.600422284944681, 0.000000000000000, -0.659352647255126, 0.000000000000000, -0.993127338218109, 0.000000000000000, +-2.463571314945747, 0.000000000000000, 0.937720951545881, 0.000000000000000, -3.098957308429730, 0.000000000000000, -2.354719140045463, 0.000000000000000, +-0.417285119323949, 0.000000000000000, 2.187974075975947, 0.000000000000000, 1.101468905172585, 0.000000000000000, -3.185800678152109, 0.000000000000000, +2.357534709345083, 0.000000000000000, 0.246645606729407, 0.000000000000000, 4.440905650784504, 0.000000000000000, -2.236807716637866, 0.000000000000000, +-2.171481518317550, 0.000000000000000, -2.029571795072690, 0.000000000000000, 0.135599790431348, 0.000000000000000, -1.277965265520191, 0.000000000000000, +-1.927976233157507, 0.000000000000000, -5.434492783745394, 0.000000000000000, -2.026375829312657, 0.000000000000000, 1.009666016819321, 0.000000000000000, +0.238549782367247, 0.000000000000000, -0.516403923971309, 0.000000000000000, -0.933977817429352, 0.000000000000000, 0.155803015935614, 0.000000000000000, +-0.396194809997929, 0.000000000000000, -0.915178100253214, 0.000000000000000, 0.666329367985015, 0.000000000000000, -1.517991149945785, 0.000000000000000, +0.458266744144822, 0.000000000000000, -1.242845974381418, 0.000000000000000, 0.057914823556477, 0.000000000000000, 0.994101307476875, 0.000000000000000, +-2.387209849199325, 0.000000000000000, 0.459297048883826, 0.000000000000000, 0.227711405683905, 0.000000000000000, 0.030255073506117, 0.000000000000000, +-1.323361608181337, 0.000000000000000, -4.650244457426706, 0.000000000000000, 0.062908579526021, 0.000000000000000, 3.462831028244432, 0.000000000000000, +1.303608183314856, 0.000000000000000, -1.430415193881612, 0.000000000000000, -1.672886118942142, 0.000000000000000, 0.992890699210099, 0.000000000000000, +-0.160814531784247, 0.000000000000000, -1.238132939350430, 0.000000000000000, -0.589223271459376, 0.000000000000000, 2.326363810561534, 0.000000000000000, +-4.433789496230785, 0.000000000000000, 1.664686987538929, 0.000000000000000, -2.366128834617921, 0.000000000000000, 1.212421570743837, 0.000000000000000, +-4.847914267690055, 0.000000000000000, 0.228485221404712, 0.000000000000000, 0.466139765470957, 0.000000000000000, -1.344202776943546, 0.000000000000000, +-1.012053673330574, 0.000000000000000, -2.844980626424742, 0.000000000000000, -1.552703722026340, 0.000000000000000, -1.448830983885038, 0.000000000000000, +0.127010756753980, 0.000000000000000, -1.667188263752299, 0.000000000000000, 3.424818052085100, 0.000000000000000, 0.956291135453840, 0.000000000000000, +-3.725533331754662, 0.000000000000000, -1.584534272368832, 0.000000000000000, -1.654148210472472, 0.000000000000000, 0.701610500675698, 0.000000000000000, +0.164954538683927, 0.000000000000000, -0.739260064712987, 0.000000000000000, -2.167324026090101, 0.000000000000000, -0.310240491909496, 0.000000000000000, +-2.281790349106906, 0.000000000000000, 1.719655331305361, 0.000000000000000, -2.997005923606441, 0.000000000000000, -1.999301431556852, 0.000000000000000, +-0.292229010068828, 0.000000000000000, 1.172317994855851, 0.000000000000000, 0.196734885241533, 0.000000000000000, 2.981365193477068, 0.000000000000000, +2.637726016926352, 0.000000000000000, 1.434045125217982, 0.000000000000000, 0.883627180451827, 0.000000000000000, -1.434040761445747, 0.000000000000000, +-1.528891971086553, 0.000000000000000, -3.306913135367542, 0.000000000000000, -0.399059265470646, 0.000000000000000, -0.265674394285178, 0.000000000000000, +3.502591252855384, 0.000000000000000, 0.830301156604454, 0.000000000000000, -0.220021317046083, 0.000000000000000, -0.090553770476646, 0.000000000000000, +0.771863477047951, 0.000000000000000, 1.351209629105760, 0.000000000000000, 3.773699756201963, 0.000000000000000, 0.472600118752329, 0.000000000000000, +2.332825668012222, 0.000000000000000, 1.853747950314528, 0.000000000000000, 0.759515251766178, 0.000000000000000, 1.327112776215496, 0.000000000000000, +2.518730296237868, 0.000000000000000, 0.764450208786353, 0.000000000000000, -0.278275349491296, 0.000000000000000, -0.041559465082020, 0.000000000000000, +1.387166083167787, 0.000000000000000, 2.612996769598122, 0.000000000000000, -0.385404831721799, 0.000000000000000, 2.005630016170309, 0.000000000000000, +-0.950500047307998, 0.000000000000000, -1.166884021392492, 0.000000000000000, 1.432973552928162, 0.000000000000000, 2.540370505384567, 0.000000000000000, +-1.140505295054501, 0.000000000000000, -3.673358835201185, 0.000000000000000, -0.450691288038056, 0.000000000000000, 1.601024294408014, 0.000000000000000, +0.773213556014045, 0.000000000000000, 2.973873693246168, 0.000000000000000, -1.361548406382279, 0.000000000000000, 1.409136332424815, 0.000000000000000, +-0.963382518314713, 0.000000000000000, -2.031268227368161, 0.000000000000000, 0.983309972085586, 0.000000000000000, -3.461412488471631, 0.000000000000000, +-2.601124929406039, 0.000000000000000, -0.533896239766343, 0.000000000000000, -2.627129008866350, 0.000000000000000, 0.622111169161305, 0.000000000000000, +-1.160926365580422, 0.000000000000000, -2.406196188132628, 0.000000000000000, -1.076870362758737, 0.000000000000000, -1.791866820937175, 0.000000000000000, +-0.749453071522325, 0.000000000000000, -5.324156615990973, 0.000000000000000, -1.038698022238289, 0.000000000000000, -2.106629944730630, 0.000000000000000, +0.659295598564773, 0.000000000000000, 0.520940881580988, 0.000000000000000, -0.055649203928700, 0.000000000000000, 0.292096765423137, 0.000000000000000, +-4.663743901790872, 0.000000000000000, -0.125066503391666, 0.000000000000000, -2.452620252445380, 0.000000000000000, -0.712128227397468, 0.000000000000000, +-0.048938037970968, 0.000000000000000, -1.821520226003361, 0.000000000000000, 0.810106421304257, 0.000000000000000, -0.196636623956257, 0.000000000000000, +-0.701769836763804, 0.000000000000000, 2.460345045649201, 0.000000000000000, 3.506597671641116, 0.000000000000000, -2.711322611972225, 0.000000000000000, +-0.658079876600542, 0.000000000000000, -2.040082099646173, 0.000000000000000, 2.201668355395807, 0.000000000000000, 1.181507395879711, 0.000000000000000, +-1.640739552179682, 0.000000000000000, -1.613393726467190, 0.000000000000000, -1.156741241731352, 0.000000000000000, 2.527773464519963, 0.000000000000000, +-0.497040638009502, 0.000000000000000, -0.975817112895589, 0.000000000000000, -2.866830755546166, 0.000000000000000, 1.120214498507878, 0.000000000000000, +5.986771654661698, 0.000000000000000, 0.398219252656757, 0.000000000000000, -3.545606013198135, 0.000000000000000, 0.312398099396191, 0.000000000000000, +-2.265327979531788, 0.000000000000000, 0.792121001107366, 0.000000000000000, -3.736145137670100, 0.000000000000000, 0.762228883650802, 0.000000000000000, +2.283545661214646, 0.000000000000000, 3.780020629583529, 0.000000000000000, 3.117260228608810, 0.000000000000000, -2.011159255609613, 0.000000000000000, +0.279107700476072, 0.000000000000000, 2.003369134246936, 0.000000000000000, -1.448171234480257, 0.000000000000000, 0.584697150310140, 0.000000000000000, +0.919508663636197, 0.000000000000000, -3.071349141675388, 0.000000000000000, -1.555923649263667, 0.000000000000000, 2.232497079438850, 0.000000000000000, +-0.012662139119883, 0.000000000000000, 0.372825540734715, 0.000000000000000, 2.378543590847629, 0.000000000000000, 1.459053407813062, 0.000000000000000, +-0.967913907390927, 0.000000000000000, 1.322825200678212, 0.000000000000000, -1.033775820061824, 0.000000000000000, -1.813629552693142, 0.000000000000000, +4.794348161661486, 0.000000000000000, 0.655279811518676, 0.000000000000000, -2.224590138589720, 0.000000000000000, 0.595329481295766, 0.000000000000000, +3.364055988866225, 0.000000000000000, 1.863416422998127, 0.000000000000000, 1.930305751828105, 0.000000000000000, -0.284467053432545, 0.000000000000000, +-0.923374905878938, 0.000000000000000, 1.922988234041399, 0.000000000000000, 0.310482143432719, 0.000000000000000, 0.332122302397134, 0.000000000000000, +-1.659487472408966, 0.000000000000000, -1.865943507877961, 0.000000000000000, -0.186775297569864, 0.000000000000000, -1.700543850628361, 0.000000000000000, +0.497157959366735, 0.000000000000000, -0.471244843957418, 0.000000000000000, -0.432013753969948, 0.000000000000000, -4.000189880113231, 0.000000000000000, +-0.415335170016467, 0.000000000000000, 0.317311950972859, 0.000000000000000, 0.038393428927595, 0.000000000000000, 0.177219909465206, 0.000000000000000, +0.531650958095143, 0.000000000000000, -2.711644985175806, 0.000000000000000, 0.328744077805156, 0.000000000000000, -0.938417707547928, 0.000000000000000, +0.970379584897379, 0.000000000000000, 1.873649473917137, 0.000000000000000, 0.177938226987023, 0.000000000000000, 0.155609346302393, 0.000000000000000, +-1.276504241867208, 0.000000000000000, -0.463725075928807, 0.000000000000000, -0.064748250389500, 0.000000000000000, -1.725568534062385, 0.000000000000000, +-0.139066584804067, 0.000000000000000, 1.975514554117767, 0.000000000000000, -0.807063199499478, 0.000000000000000, -0.326926659682788, 0.000000000000000, +1.445727032487938, 0.000000000000000, -0.597151107739100, 0.000000000000000, 2.732557531709386, 0.000000000000000, -2.907130934109188, 0.000000000000000, +-1.461264832679981, 0.000000000000000, -1.708588604968163, 0.000000000000000, 3.652851925431363, 0.000000000000000, 0.682050868282879, 0.000000000000000, +-0.281312579963294, 0.000000000000000, 0.554966483307825, 0.000000000000000, -0.981341739340932, 0.000000000000000, 1.279543331141603, 0.000000000000000, +0.036589747826856, 0.000000000000000, 2.312073745896073, 0.000000000000000, 1.754682200732425, 0.000000000000000, -0.957515875428627, 0.000000000000000, +-0.833596942819695, 0.000000000000000, 0.437054368791033, 0.000000000000000, -0.898819399360279, 0.000000000000000, -0.296050580896839, 0.000000000000000, +-0.785144257649601, 0.000000000000000, -2.541503089003311, 0.000000000000000, 2.225075846758761, 0.000000000000000, -1.587290487902002, 0.000000000000000, +-1.421404172056462, 0.000000000000000, -3.015149802293631, 0.000000000000000, 1.780874288867949, 0.000000000000000, -0.865812740882613, 0.000000000000000, +-2.845327531197112, 0.000000000000000, 1.445225867774367, 0.000000000000000, 2.183733236584647, 0.000000000000000, 1.163371072749080, 0.000000000000000, +0.883547693520409, 0.000000000000000, -1.224093106684675, 0.000000000000000, -1.854501116331044, 0.000000000000000, 1.783082089255796, 0.000000000000000, +2.301508706196191, 0.000000000000000, -0.539901944139077, 0.000000000000000, 1.962315832319967, 0.000000000000000, -0.060709041870503, 0.000000000000000, +-1.353139923300238, 0.000000000000000, -1.482887537805234, 0.000000000000000, 1.273732601967176, 0.000000000000000, -3.456609915556321, 0.000000000000000, +-3.752320586540873, 0.000000000000000, 3.536356614978951, 0.000000000000000, 0.206035952043233, 0.000000000000000, 5.933966913773842, 0.000000000000000, +-0.486633898075490, 0.000000000000000, -0.329595089863342, 0.000000000000000, 1.496414153905337, 0.000000000000000, 0.137868749388880, 0.000000000000000, +-0.437192030996792, 0.000000000000000, 2.682750615210656, 0.000000000000000, -2.440234892848570, 0.000000000000000, 1.433910252426186, 0.000000000000000, +-0.415051506104074, 0.000000000000000, 1.982003013708649, 0.000000000000000, 1.345796609972435, 0.000000000000000, -2.335949513404370, 0.000000000000000, +1.065988867433025, 0.000000000000000, 2.741844905000464, 0.000000000000000, -1.754047930934362, 0.000000000000000, 0.229252730015575, 0.000000000000000, +-0.679791016408669, 0.000000000000000, -2.274097820043743, 0.000000000000000, 0.149802252231876, 0.000000000000000, -0.139697151364830, 0.000000000000000, +-2.773367420505435, 0.000000000000000, -4.403400246165611, 0.000000000000000, -1.468974515184135, 0.000000000000000, 0.664990623095844, 0.000000000000000, +-3.446979775557143, 0.000000000000000, 1.850006428987618, 0.000000000000000, -1.550866747921936, 0.000000000000000, -3.632874882935257, 0.000000000000000, +0.828039662992464, 0.000000000000000, 2.794055182632816, 0.000000000000000, -0.593995716682633, 0.000000000000000, 0.142788156054200, 0.000000000000000, +0.552461945119668, 0.000000000000000, 0.842127129738758, 0.000000000000000, 1.414335509600077, 0.000000000000000, -0.311559241382430, 0.000000000000000, +1.510590844695250, 0.000000000000000, 1.692217183824300, 0.000000000000000, 0.613760285711957, 0.000000000000000, 0.065233463207770, 0.000000000000000, +-2.571912893711505, 0.000000000000000, -1.707001531141341, 0.000000000000000, 0.673884968382041, 0.000000000000000, 0.889863883420103, 0.000000000000000, +-2.395635435233346, 0.000000000000000, 1.129247296359819, 0.000000000000000, 0.569074704779735, 0.000000000000000, 6.139436017480722, 0.000000000000000, +0.822158309259017, 0.000000000000000, -3.289872016222589, 0.000000000000000, 0.417612988384414, 0.000000000000000, 1.493982103868165, 0.000000000000000, +-0.415353391377005, 0.000000000000000, 0.288670764933155, 0.000000000000000, -1.895650228872272, 0.000000000000000, -0.139631694475020, 0.000000000000000, +1.445103299005436, 0.000000000000000, 2.877182243683429, 0.000000000000000, 1.192428490172580, 0.000000000000000, -5.964591921763842, 0.000000000000000, +0.570859795882959, 0.000000000000000, 2.328333316356666, 0.000000000000000, 0.333755014930026, 0.000000000000000, 1.221901577771909, 0.000000000000000, +0.943358697415568, 0.000000000000000, 2.793063983613067, 0.000000000000000, 3.163005066073616, 0.000000000000000, 2.098300664513867, 0.000000000000000, +-3.915313164333447, 0.000000000000000, -2.475766769064539, 0.000000000000000, 1.720472044894277, 0.000000000000000, -1.273591949275665, 0.000000000000000, +-1.213451272938616, 0.000000000000000, 0.697439404325690, 0.000000000000000, -0.309902287574293, 0.000000000000000, 2.622575852162781, 0.000000000000000, +-2.075881936219060, 0.000000000000000, 0.777847545691770, 0.000000000000000, -3.967947986440650, 0.000000000000000, -3.066503371806472, 0.000000000000000, +1.193780625937845, 0.000000000000000, 0.214246579281311, 0.000000000000000, -2.610681491162162, 0.000000000000000, -1.261224183972745, 0.000000000000000, +-1.165071748544285, 0.000000000000000, -1.116548474834374, 0.000000000000000, 0.847202164846982, 0.000000000000000, -3.474301529532390, 0.000000000000000, +0.020799541946476, 0.000000000000000, -3.868995473288166, 0.000000000000000, 1.757979409638067, 0.000000000000000, 0.868115130183109, 0.000000000000000, +0.910167436737958, 0.000000000000000, -1.878855115563720, 0.000000000000000, 1.710357104174161, 0.000000000000000, -1.468933980990902, 0.000000000000000, +1.799544171601169, 0.000000000000000, -4.922332880027887, 0.000000000000000, 0.219424548939720, 0.000000000000000, -0.971671113451924, 0.000000000000000, +-0.940533475616266, 0.000000000000000, 0.122510114412152, 0.000000000000000, -1.373686254916911, 0.000000000000000, 1.760348103896323, 0.000000000000000, +0.391745067829643, 0.000000000000000, 2.521958505327354, 0.000000000000000, -1.300693516405092, 0.000000000000000, -0.538251788309178, 0.000000000000000, +0.797184135810173, 0.000000000000000, 2.908800548982588, 0.000000000000000, 1.590902251655215, 0.000000000000000, -1.070323714487264, 0.000000000000000, +-3.349764443340999, 0.000000000000000, -1.190563529731447, 0.000000000000000, 1.363369471291963, 0.000000000000000, -1.814270299924576, 0.000000000000000, +-0.023381588315711, 0.000000000000000, 1.719182048679569, 0.000000000000000, 0.839917213252626, 0.000000000000000, 1.006099633839122, 0.000000000000000, +0.812462674381527, 0.000000000000000, 1.755814336346739, 0.000000000000000, 2.546848681206319, 0.000000000000000, -1.555300208869455, 0.000000000000000, +1.017053811631167, 0.000000000000000, 0.996591039170903, 0.000000000000000, -1.228047247924881, 0.000000000000000, 4.809462271463009, 0.000000000000000, +2.318113116151685, 0.000000000000000, -1.206932520679733, 0.000000000000000, 1.273757685623312, 0.000000000000000, 0.724335352481802, 0.000000000000000, +1.519876652073198, 0.000000000000000, -2.749670314714158, 0.000000000000000, 3.424042481847581, 0.000000000000000, -3.714668360421517, 0.000000000000000, +1.612834197004014, 0.000000000000000, -2.038234723985566, 0.000000000000000, 1.470938786562152, 0.000000000000000, 2.111634918450302, 0.000000000000000, +1.030376670151787, 0.000000000000000, -0.420877189003829, 0.000000000000000, -1.502024800532894, 0.000000000000000, 0.452310749163804, 0.000000000000000, +-1.606059382300987, 0.000000000000000, -4.006159967834147, 0.000000000000000, -2.152801208196508, 0.000000000000000, 1.671674089372579, 0.000000000000000, +1.714536333564101, 0.000000000000000, -1.011518543005344, 0.000000000000000, -0.576410282180584, 0.000000000000000, 0.733689809480836, 0.000000000000000, +1.004245602717974, 0.000000000000000, 1.010090391888449, 0.000000000000000, 3.811459513385621, 0.000000000000000, -5.230621089271954, 0.000000000000000, +0.678044861034399, 0.000000000000000, 1.255935859598107, 0.000000000000000, 1.674521701615288, 0.000000000000000, -1.656695216761705, 0.000000000000000, +1.169286028869693, 0.000000000000000, 0.524915416191998, 0.000000000000000, 2.397642885039520, 0.000000000000000, 2.108711400616072, 0.000000000000000, +2.037618211018084, 0.000000000000000, -0.623664553406925, 0.000000000000000, 2.984106170984409, 0.000000000000000, 1.132182737400932, 0.000000000000000, +-2.859274340352130, 0.000000000000000, -0.975550071398723, 0.000000000000000, -1.359935119997407, 0.000000000000000, -2.963308211050121, 0.000000000000000, +-0.228726662781163, 0.000000000000000, -1.411110379682043, 0.000000000000000, 0.741553355734225, 0.000000000000000, 0.497554254758309, 0.000000000000000, +2.371907950598855, 0.000000000000000, 1.063465168988748, 0.000000000000000, -0.641082692081488, 0.000000000000000, -0.855439878540726, 0.000000000000000, +0.578321738578726, 0.000000000000000, 3.005809768796194, 0.000000000000000, 1.961458699064065, 0.000000000000000, -3.206261663772745, 0.000000000000000, +-0.364431989095434, 0.000000000000000, -0.263182496622273, 0.000000000000000, 1.843464680631139, 0.000000000000000, -0.419107530229249, 0.000000000000000, +1.662335873298487, 0.000000000000000, -0.853687563304005, 0.000000000000000, -2.584133404357169, 0.000000000000000, 3.466839568922895, 0.000000000000000, +0.881671345091973, 0.000000000000000, 0.454620014206908, 0.000000000000000, -1.737245187402739, 0.000000000000000, 2.162713238369243, 0.000000000000000, +-3.868539002714486, 0.000000000000000, 2.014114855933826, 0.000000000000000, -0.703233831811006, 0.000000000000000, -3.410319935997574, 0.000000000000000, +-1.851235811006584, 0.000000000000000, 0.909783907894036, 0.000000000000000, 0.091884002136728, 0.000000000000000, -2.688294201131650, 0.000000000000000, +-0.906134178460955, 0.000000000000000, 3.475054609035133, 0.000000000000000, -0.573927964170323, 0.000000000000000, -0.429542937515399, 0.000000000000000, +0.991348618739939, 0.000000000000000, 1.974804904926325, 0.000000000000000, 0.975783450796698, 0.000000000000000, -3.057119549071503, 0.000000000000000, +-3.899429237481194, 0.000000000000000, 0.362439009175350, 0.000000000000000, -1.124461670265618, 0.000000000000000, 1.806000360163583, 0.000000000000000, +-2.768333362600288, 0.000000000000000, 0.244387897900379, 0.000000000000000, 0.908767296720926, 0.000000000000000, 1.254669374391882, 0.000000000000000, +-1.420441929463686, 0.000000000000000, -0.875658895966293, 0.000000000000000, 0.183824603376167, 0.000000000000000, -3.361653917011686, 0.000000000000000, +-0.796615630227952, 0.000000000000000, -1.660226542658673, 0.000000000000000, 1.654439358307226, 0.000000000000000, 2.782812946709771, 0.000000000000000, +1.418064412811531, 0.000000000000000, -0.819645647243761, 0.000000000000000, 0.807724772592699, 0.000000000000000, -0.941967976379298, 0.000000000000000, +-2.312768306047469, 0.000000000000000, 0.872426936477443, 0.000000000000000, 0.919528961530845, 0.000000000000000, -2.084904575264847, 0.000000000000000, +-1.972464868459322, 0.000000000000000, -1.050687203338466, 0.000000000000000, 1.659579707007902, 0.000000000000000, -1.820640014705855, 0.000000000000000, +-1.195078061671045, 0.000000000000000, -1.639773173762048, 0.000000000000000, 1.616744338157063, 0.000000000000000, 4.019216096811563, 0.000000000000000, +3.461021102549681, 0.000000000000000, 1.642352734361484, 0.000000000000000, -0.046354693720813, 0.000000000000000, -0.041936252359677, 0.000000000000000, +-2.393307519480551, 0.000000000000000, -0.341471634615121, 0.000000000000000, -0.392073595257017, 0.000000000000000, -0.219299018372730, 0.000000000000000, +-2.016391579662071, 0.000000000000000, -0.653096251969787, 0.000000000000000, 1.466353155666821, 0.000000000000000, -2.872058864320412, 0.000000000000000, +-2.157180779503830, 0.000000000000000, 0.723257479841560, 0.000000000000000, 3.769951308104384, 0.000000000000000, -1.923392042420024, 0.000000000000000, +0.644899359942840, 0.000000000000000, -2.090226891621437, 0.000000000000000, -0.277043982890403, 0.000000000000000, -0.528271428321112, 0.000000000000000, +2.518120645960652, 0.000000000000000, 1.040820431111488, 0.000000000000000, -4.560583754742486, 0.000000000000000, -0.226899614918836, 0.000000000000000, +1.713331231108959, 0.000000000000000, -3.293941019163642, 0.000000000000000, -1.113331444648290, 0.000000000000000, -1.032308423149906, 0.000000000000000, +1.593774272982443, 0.000000000000000, -1.246840475090529, 0.000000000000000, -0.190344684920137, 0.000000000000000, -1.719386356896355, 0.000000000000000, +-2.827721754659679, 0.000000000000000, -0.092438285279020, 0.000000000000000, -0.565844430675246, 0.000000000000000, -1.077916121691716, 0.000000000000000, +-1.208665809504693, 0.000000000000000, -2.996014266381254, 0.000000000000000, 2.888573323402423, 0.000000000000000, 2.829507048720695, 0.000000000000000, +-0.859177034120755, 0.000000000000000, -1.969302377743254, 0.000000000000000, 0.777437674525362, 0.000000000000000, -0.124910190157646, 0.000000000000000, +0.129875493115290, 0.000000000000000, -4.192139262163992, 0.000000000000000, 3.023496047962126, 0.000000000000000, 1.149775163736637, 0.000000000000000, +2.038151304801731, 0.000000000000000, 3.016122489841263, 0.000000000000000, -4.829481812137012, 0.000000000000000, -1.668436615909279, 0.000000000000000, +0.958586784636918, 0.000000000000000, 1.550652410058678, 0.000000000000000, -1.456305257976716, 0.000000000000000, -0.079588392344731, 0.000000000000000, +-2.453213599392345, 0.000000000000000, 0.296795909127105, 0.000000000000000, -0.253426616607643, 0.000000000000000, 1.418937160028195, 0.000000000000000, +-1.672949529066915, 0.000000000000000, -1.620990298572947, 0.000000000000000, -1.085103073196045, 0.000000000000000, 0.738606361195386, 0.000000000000000, +-2.097831202853255, 0.000000000000000, 2.711952282071310, 0.000000000000000, 1.498539238246888, 0.000000000000000, 1.317457282535915, 0.000000000000000, +-0.302765938349717, 0.000000000000000, -0.044623707947201, 0.000000000000000, 2.337405215062395, 0.000000000000000, -3.980689173859100, 0.000000000000000, + + +}; + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.c new file mode 100644 index 00000000..c9fc8c49 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.c @@ -0,0 +1,167 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_fft_bin_example_f32.c +* +* Description: Example code demonstrating calculation of Max energy bin of +* frequency domain of input signal. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup FrequencyBin Frequency Bin Example + * + * \par Description + * \par + * Demonstrates the calculation of the maximum energy bin in the frequency + * domain of the input signal with the use of Complex FFT, Complex + * Magnitude, and Maximum functions. + * + * \par Algorithm: + * \par + * The input test signal contains a 10 kHz signal with uniformly distributed white noise. + * Calculating the FFT of the input signal will give us the maximum energy of the + * bin corresponding to the input frequency of 10 kHz. + * + * \par Block Diagram: + * \image html FFTBin.gif "Block Diagram" + * \par + * The figure below shows the time domain signal of 10 kHz signal with + * uniformly distributed white noise, and the next figure shows the input + * in the frequency domain. The bin with maximum energy corresponds to 10 kHz signal. + * \par + * \image html FFTBinInput.gif "Input signal in Time domain" + * \image html FFTBinOutput.gif "Input signal in Frequency domain" + * + * \par Variables Description: + * \par + * \li \c testInput_f32_10khz points to the input data + * \li \c testOutput points to the output data + * \li \c fftSize length of FFT + * \li \c ifftFlag flag for the selection of CFFT/CIFFT + * \li \c doBitReverse Flag for selection of normal order or bit reversed order + * \li \c refIndex reference index value at which maximum energy of bin ocuurs + * \li \c testIndex calculated index value at which maximum energy of bin ocuurs + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_cfft_f32() + * - arm_cmplx_mag_f32() + * - arm_max_f32() + * + * Refer + * \link arm_fft_bin_example_f32.c \endlink + * + */ + + +/** \example arm_fft_bin_example_f32.c + */ + + +#include "arm_math.h" +#include "arm_const_structs.h" + +#if defined(SEMIHOSTING) +#include +#endif + +#define TEST_LENGTH_SAMPLES 2048 + +/* ------------------------------------------------------------------- +* External Input and Output buffer Declarations for FFT Bin Example +* ------------------------------------------------------------------- */ +extern float32_t testInput_f32_10khz[TEST_LENGTH_SAMPLES]; +static float32_t testOutput[TEST_LENGTH_SAMPLES/2]; + +/* ------------------------------------------------------------------ +* Global variables for FFT Bin Example +* ------------------------------------------------------------------- */ +uint32_t fftSize = 1024; +uint32_t ifftFlag = 0; +uint32_t doBitReverse = 1; +arm_cfft_instance_f32 varInstCfftF32; + +/* Reference index at which max energy of bin ocuurs */ +uint32_t refIndex = 213, testIndex = 0; + +/* ---------------------------------------------------------------------- +* Max magnitude FFT Bin test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + + arm_status status; + float32_t maxValue; + + status = ARM_MATH_SUCCESS; + + status=arm_cfft_init_f32(&varInstCfftF32,fftSize); + + /* Process the data through the CFFT/CIFFT module */ + arm_cfft_f32(&varInstCfftF32, testInput_f32_10khz, ifftFlag, doBitReverse); + + /* Process the data through the Complex Magnitude Module for + calculating the magnitude at each bin */ + arm_cmplx_mag_f32(testInput_f32_10khz, testOutput, fftSize); + + /* Calculates maxValue and returns corresponding BIN value */ + arm_max_f32(testOutput, fftSize, &maxValue, &testIndex); + + status = (testIndex != refIndex) ? ARM_MATH_TEST_FAILURE : ARM_MATH_SUCCESS; + + if (status != ARM_MATH_SUCCESS) + { +#if defined (SEMIHOSTING) + printf("FAILURE\n"); +#else + while (1); /* main function does not return */ +#endif + } + else + { +#if defined (SEMIHOSTING) + printf("SUCCESS\n"); +#else + while (1); /* main function does not return */ +#endif + } +} + + /** \endlink */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM0_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM0_config.txt new file mode 100644 index 00000000..13dc7839 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM3_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM3_config.txt new file mode 100644 index 00000000..55419ac8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM4_FP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM4_FP_config.txt new file mode 100644 index 00000000..fb9d24c9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM55_FP_MVE_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 00000000..4a65b1de --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM7_SP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM7_SP_config.txt new file mode 100644 index 00000000..82fc00c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/Abstract.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/Abstract.txt new file mode 100644 index 00000000..06f68a20 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_fir_example. + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/CMakeLists.txt new file mode 100644 index 00000000..bf850442 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_fir_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_fir_example) + + +include(config) +configApp(arm_fir_example ${ROOT}) + +target_sources(arm_fir_example PRIVATE arm_fir_data.c math_helper.c arm_fir_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_fir_example PRIVATE CMSISDSP) + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 00000000..f527fa11 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/system_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 00000000..66a364c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 00000000..0392a899 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/system_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 00000000..3c5eda7d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 00000000..90eee9dc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 00000000..9d983d2e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 00000000..0ab7e3e9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM55/system_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 00000000..b76ebb7c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 00000000..78584996 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 00000000..75f9c18e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.c new file mode 100644 index 00000000..283a25e2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_fir_data.c +* +* Description: Data file used for example code +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +** Test input signal contains 1000Hz + 15000 Hz +** ------------------------------------------------------------------- */ + +float32_t testInput_f32_1kHz_15kHz[320] = +{ ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, +-0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, +-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, +-0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, +-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, +-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +}; + +float32_t refOutput[320] = +{ ++0.0000000000f, -0.0010797829f, -0.0007681386f, -0.0001982932f, +0.0000644313f, +0.0020854271f, +0.0036891871f, +0.0015855941f, +-0.0026280805f, -0.0075907658f, -0.0119390538f, -0.0086665968f, +0.0088981202f, +0.0430539279f, +0.0974468742f, +0.1740405600f, ++0.2681416601f, +0.3747720089f, +0.4893362230f, +0.6024154672f, +0.7058740791f, +0.7968348987f, +0.8715901940f, +0.9277881093f, ++0.9682182661f, +0.9934674267f, +1.0012052245f, +0.9925859371f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, -0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f +}; + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.c new file mode 100644 index 00000000..f28359fb --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.c @@ -0,0 +1,262 @@ +/* ---------------------------------------------------------------------- + * Copyright (C) 2010-2012 ARM Limited. All rights reserved. + * +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library + * Title: arm_fir_example_f32.c + * + * Description: Example code demonstrating how an FIR filter can be used + * as a low pass filter. + * + * Target Processor: Cortex-M4/Cortex-M3 + * +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup FIRLPF FIR Lowpass Filter Example + * + * \par Description: + * \par + * Removes high frequency signal components from the input using an FIR lowpass filter. + * The example demonstrates how to configure an FIR filter and then pass data through + * it in a block-by-block fashion. + * \image html FIRLPF_signalflow.gif + * + * \par Algorithm: + * \par + * The input signal is a sum of two sine waves: 1 kHz and 15 kHz. + * This is processed by an FIR lowpass filter with cutoff frequency 6 kHz. + * The lowpass filter eliminates the 15 kHz signal leaving only the 1 kHz sine wave at the output. + * \par + * The lowpass filter was designed using MATLAB with a sample rate of 48 kHz and + * a length of 29 points. + * The MATLAB code to generate the filter coefficients is shown below: + *
+ *     h = fir1(28, 6/24);
+ * 
+ * The first argument is the "order" of the filter and is always one less than the desired length. + * The second argument is the normalized cutoff frequency. This is in the range 0 (DC) to 1.0 (Nyquist). + * A 6 kHz cutoff with a Nyquist frequency of 24 kHz lies at a normalized frequency of 6/24 = 0.25. + * The CMSIS FIR filter function requires the coefficients to be in time reversed order. + *
+ *     fliplr(h)
+ * 
+ * The resulting filter coefficients and are shown below. + * Note that the filter is symmetric (a property of linear phase FIR filters) + * and the point of symmetry is sample 14. Thus the filter will have a delay of + * 14 samples for all frequencies. + * \par + * \image html FIRLPF_coeffs.gif + * \par + * The frequency response of the filter is shown next. + * The passband gain of the filter is 1.0 and it reaches 0.5 at the cutoff frequency 6 kHz. + * \par + * \image html FIRLPF_response.gif + * \par + * The input signal is shown below. + * The left hand side shows the signal in the time domain while the right hand side is a frequency domain representation. + * The two sine wave components can be clearly seen. + * \par + * \image html FIRLPF_input.gif + * \par + * The output of the filter is shown below. The 15 kHz component has been eliminated. + * \par + * \image html FIRLPF_output.gif + * + * \par Variables Description: + * \par + * \li \c testInput_f32_1kHz_15kHz points to the input data + * \li \c refOutput points to the reference output data + * \li \c testOutput points to the test output data + * \li \c firStateF32 points to state buffer + * \li \c firCoeffs32 points to coefficient buffer + * \li \c blockSize number of samples processed at a time + * \li \c numBlocks number of frames + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_fir_init_f32() + * - arm_fir_f32() + * + * Refer + * \link arm_fir_example_f32.c \endlink + * + */ + + +/** \example arm_fir_example_f32.c + */ + +/* ---------------------------------------------------------------------- +** Include Files +** ------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "math_helper.h" + +#if defined(SEMIHOSTING) +#include +#endif + + +/* ---------------------------------------------------------------------- +** Macro Defines +** ------------------------------------------------------------------- */ + +#define TEST_LENGTH_SAMPLES 320 +/* + +This SNR is a bit small. Need to understand why +this example is not giving better SNR ... + +*/ +#define SNR_THRESHOLD_F32 75.0f +#define BLOCK_SIZE 32 + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +/* Must be a multiple of 16 */ +#define NUM_TAPS_ARRAY_SIZE 32 +#else +#define NUM_TAPS_ARRAY_SIZE 29 +#endif + +#define NUM_TAPS 29 + +/* ------------------------------------------------------------------- + * The input signal and reference output (computed with MATLAB) + * are defined externally in arm_fir_lpf_data.c. + * ------------------------------------------------------------------- */ + +extern float32_t testInput_f32_1kHz_15kHz[TEST_LENGTH_SAMPLES]; +extern float32_t refOutput[TEST_LENGTH_SAMPLES]; + +/* ------------------------------------------------------------------- + * Declare Test output buffer + * ------------------------------------------------------------------- */ + +static float32_t testOutput[TEST_LENGTH_SAMPLES]; + +/* ------------------------------------------------------------------- + * Declare State buffer of size (numTaps + blockSize - 1) + * ------------------------------------------------------------------- */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +static float32_t firStateF32[2 * BLOCK_SIZE + NUM_TAPS - 1]; +#else +static float32_t firStateF32[BLOCK_SIZE + NUM_TAPS - 1]; +#endif + +/* ---------------------------------------------------------------------- +** FIR Coefficients buffer generated using fir1() MATLAB function. +** fir1(28, 6/24) +** ------------------------------------------------------------------- */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +const float32_t firCoeffs32[NUM_TAPS_ARRAY_SIZE] = { + -0.0018225230f, -0.0015879294f, +0.0000000000f, +0.0036977508f, +0.0080754303f, +0.0085302217f, -0.0000000000f, -0.0173976984f, + -0.0341458607f, -0.0333591565f, +0.0000000000f, +0.0676308395f, +0.1522061835f, +0.2229246956f, +0.2504960933f, +0.2229246956f, + +0.1522061835f, +0.0676308395f, +0.0000000000f, -0.0333591565f, -0.0341458607f, -0.0173976984f, -0.0000000000f, +0.0085302217f, + +0.0080754303f, +0.0036977508f, +0.0000000000f, -0.0015879294f, -0.0018225230f, 0.0f,0.0f,0.0f +}; +#else +const float32_t firCoeffs32[NUM_TAPS_ARRAY_SIZE] = { + -0.0018225230f, -0.0015879294f, +0.0000000000f, +0.0036977508f, +0.0080754303f, +0.0085302217f, -0.0000000000f, -0.0173976984f, + -0.0341458607f, -0.0333591565f, +0.0000000000f, +0.0676308395f, +0.1522061835f, +0.2229246956f, +0.2504960933f, +0.2229246956f, + +0.1522061835f, +0.0676308395f, +0.0000000000f, -0.0333591565f, -0.0341458607f, -0.0173976984f, -0.0000000000f, +0.0085302217f, + +0.0080754303f, +0.0036977508f, +0.0000000000f, -0.0015879294f, -0.0018225230f +}; +#endif + +/* ------------------------------------------------------------------ + * Global variables for FIR LPF Example + * ------------------------------------------------------------------- */ + +uint32_t blockSize = BLOCK_SIZE; +uint32_t numBlocks = TEST_LENGTH_SAMPLES/BLOCK_SIZE; + +float32_t snr; + +/* ---------------------------------------------------------------------- + * FIR LPF Example + * ------------------------------------------------------------------- */ + +int32_t main(void) +{ + uint32_t i; + arm_fir_instance_f32 S; + arm_status status; + float32_t *inputF32, *outputF32; + + /* Initialize input and output buffer pointers */ + inputF32 = &testInput_f32_1kHz_15kHz[0]; + outputF32 = &testOutput[0]; + + /* Call FIR init function to initialize the instance structure. */ + arm_fir_init_f32(&S, NUM_TAPS, (float32_t *)&firCoeffs32[0], &firStateF32[0], blockSize); + + /* ---------------------------------------------------------------------- + ** Call the FIR process function for every blockSize samples + ** ------------------------------------------------------------------- */ + + for(i=0; i < numBlocks; i++) + { + arm_fir_f32(&S, inputF32 + (i * blockSize), outputF32 + (i * blockSize), blockSize); + } + + /* ---------------------------------------------------------------------- + ** Compare the generated output against the reference output computed + ** in MATLAB. + ** ------------------------------------------------------------------- */ + + snr = arm_snr_f32(&refOutput[0], &testOutput[0], TEST_LENGTH_SAMPLES); + + status = (snr < SNR_THRESHOLD_F32) ? ARM_MATH_TEST_FAILURE : ARM_MATH_SUCCESS; + + if (status != ARM_MATH_SUCCESS) + { +#if defined (SEMIHOSTING) + printf("FAILURE\n"); +#else + while (1); /* main function does not return */ +#endif + } + else + { +#if defined (SEMIHOSTING) + printf("SUCCESS\n"); +#else + while (1); /* main function does not return */ +#endif + } +} + +/** \endlink */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.c new file mode 100644 index 00000000..950bf42b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.c @@ -0,0 +1,474 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/* + +Conflicting with the new clip functions in CMSIS-DSP and not used +in the examples. + +*/ +#if 0 +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + +#endif + + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.h b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.h new file mode 100644 index 00000000..a0dbdf73 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM0_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM0_config.txt new file mode 100644 index 00000000..13dc7839 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM3_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM3_config.txt new file mode 100644 index 00000000..55419ac8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM4_FP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM4_FP_config.txt new file mode 100644 index 00000000..fb9d24c9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM55_FP_MVE_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 00000000..4a65b1de --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM7_SP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM7_SP_config.txt new file mode 100644 index 00000000..82fc00c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/Abstract.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/Abstract.txt new file mode 100644 index 00000000..8c97744c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_graphic_equalizer_example. + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/CMakeLists.txt new file mode 100644 index 00000000..9cf05e17 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_graphic_equalizer_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_graphic_equalizer_example) + + +include(config) +configApp(arm_graphic_equalizer_example ${ROOT}) + +target_sources(arm_graphic_equalizer_example PRIVATE math_helper.c arm_graphic_equalizer_data.c arm_graphic_equalizer_example_q31.c) + +### Sources and libs + +target_link_libraries(arm_graphic_equalizer_example PRIVATE CMSISDSP) + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 00000000..f527fa11 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/system_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 00000000..66a364c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 00000000..0392a899 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/system_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 00000000..3c5eda7d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 00000000..90eee9dc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 00000000..9d983d2e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 00000000..0ab7e3e9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM55/system_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 00000000..b76ebb7c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 00000000..78584996 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 00000000..75f9c18e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c new file mode 100644 index 00000000..ffb0ff31 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_graphic_equalizer_data.c +* +* Description: Data file used for example code +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +#include "arm_math.h" + +float32_t testRefOutput_f32[320] = { + +0.000000000000000000, 0.001898396760225296, 0.004215449094772339, 0.007432077080011368, 0.010948467999696732, 0.015026375651359558, 0.019191544502973557, 0.023574527353048325, +0.027919445186853409, 0.032277785241603851, 0.036551639437675476, 0.040732793509960175, 0.044799156486988068, 0.048710610717535019, 0.052476800978183746, 0.056059073656797409, +0.059482168406248093, 0.062726479023694992, 0.065821025520563126, 0.068763464689254761, 0.071577839553356171, 0.074270240962505341, 0.076856281608343124, 0.079344697296619415, +0.081745062023401260, 0.084067162126302719, 0.086318407207727432, 0.088509257882833481, 0.090647127479314804, 0.092742368578910828, 0.094802625477313995, 0.096837285906076431, +0.098853722214698792, 0.100859899073839190, 0.102862443774938580, 0.104867763817310330, 0.106881409883499150, 0.108908228576183320, 0.110952425748109820, 0.113017357885837550, +0.115105822682380680, 0.117219865322113040, 0.119361080229282380, 0.121530555188655850, 0.123729091137647630, 0.125957202166318890, 0.128215309232473370, 0.130503740161657330, +0.132822841405868530, 0.135173004120588300, 0.137554679065942760, 0.139968376606702800, 0.142414685338735580, 0.144894234836101530, 0.147407654672861100, 0.149955596774816510, +0.152538605034351350, 0.155157200992107390, 0.157811731100082400, 0.160502441227436070, 0.163229387253522870, 0.165992442518472670, 0.168791320174932480, 0.171625509858131410, +0.174494370818138120, 0.177397061139345170, 0.180332608520984650, 0.183299910277128220, 0.186297744512557980, 0.189324837177991870, 0.192379791289567950, 0.195461250841617580, +0.198567759245634080, 0.201697919517755510, 0.204850304871797560, 0.208023533225059510, 0.211216274648904800, 0.214427210390567780, 0.217655111104249950, 0.220898788422346120, +0.224157124757766720, 0.227429077029228210, 0.230713658034801480, 0.234009962528944020, 0.237317133694887160, 0.240634419023990630, 0.243961080908775330, 0.247296508401632310, +0.250640105456113820, 0.253991369158029560, 0.257349837571382520, 0.260715119540691380, 0.264086868613958360, 0.267464816570281980, 0.270848698914051060, 0.274238351732492450, +0.277633611112833020, 0.281034380197525020, 0.284440591931343080, 0.287852220237255100, 0.291269283741712570, 0.294691801071166990, 0.298119872808456420, 0.301553562283515930, +0.304993014782667160, 0.308438356965780260, 0.311889752745628360, 0.315347377210855480, 0.318811416625976560, 0.322282072156667710, 0.325759567320346830, 0.329244095832109450, +0.332735907286405560, 0.336235217750072480, 0.339742250740528110, 0.343257248401641850, 0.346780419349670410, 0.350311983376741410, 0.353852160274982450, 0.357401121407747270, +0.360959105193614960, 0.364526227116584780, 0.368102725595235820, 0.371688675135374070, 0.375284302979707720, 0.378889638930559160, 0.382504884153604510, 0.386130042374134060, +0.389765247702598570, 0.393410529941320420, 0.397065933793783190, 0.400731507688760760, 0.404407206922769550, 0.408093083649873730, 0.411789052188396450, 0.415495119988918300, +0.419211201369762420, 0.422937240451574330, 0.426673140376806260, 0.430418811738491060, 0.434174135327339170, 0.437938995659351350, 0.441713258624076840, 0.445496778935194020, +0.449289388954639430, 0.453090950846672060, 0.456901267170906070, 0.460720170289278030, 0.464547459036111830, 0.468382950872182850, 0.472226426005363460, 0.476077698171138760, +0.479936532676219940, 0.483802750706672670, 0.487676106393337250, 0.491556398570537570, 0.495443399995565410, 0.499336875975131990, 0.503236617892980580, 0.507142387330532070, +0.511053957045078280, 0.514971107244491580, 0.518893606960773470, 0.522821225225925450, 0.526753749698400500, 0.530690938234329220, 0.534632585942745210, 0.538578454405069350, +0.542528338730335240, 0.546481993049383160, 0.550439231097698210, 0.554399792104959490, 0.558363504707813260, 0.562330115586519240, 0.566299438476562500, 0.570271246135234830, +0.574245333671569820, 0.578221492469310760, 0.582199502736330030, 0.586179181933403020, 0.590160276740789410, 0.594142623245716090, 0.598125983029603960, 0.602110169827938080, +0.606094967573881150, 0.610080175101757050, 0.614065583795309070, 0.618050977587699890, 0.622036151587963100, 0.626020893454551700, 0.630004994571208950, 0.633988231420516970, +0.637970402836799620, 0.641951277852058410, 0.645930647850036620, 0.649908289313316350, 0.653883971273899080, 0.657857488840818410, 0.661828581243753430, 0.665797054767608640, +0.669762641191482540, 0.673725124448537830, 0.677684243768453600, 0.681639779359102250, 0.685591462999582290, 0.689539063721895220, 0.693482317030429840, 0.697420965880155560, +0.701354760676622390, 0.705283410847187040, 0.709206689149141310, 0.713124278932809830, 0.717035952955484390, 0.720941375941038130, 0.724840316921472550, 0.728732451796531680, +0.732617516070604320, 0.736495196819305420, 0.740365199744701390, 0.744227230548858640, 0.748080968856811520, 0.751926124095916750, 0.755762357264757160, 0.759589381515979770, +0.763406842947006230, 0.767214450985193250, 0.771011855453252790, 0.774798732250928880, 0.778574761003255840, 0.782339565455913540, 0.786092851310968400, 0.789834223687648770, +0.793563373386859890, 0.797279909253120420, 0.800983514636754990, 0.804673787206411360, 0.808350402861833570, 0.812012966722249980, 0.815661124885082240, 0.819294504821300510, +0.822912722826004030, 0.826515413820743560, 0.830102190375328060, 0.833672653883695600, 0.837226435542106630, 0.840763118118047710, 0.844282336533069610, 0.847783654928207400, +0.851266715675592420, 0.854731071740388870, 0.858176350593566890, 0.861602116376161580, 0.865007970482110980, 0.868393491953611370, 0.871758259832859040, 0.875101849436759950, +0.878423850983381270, 0.881723806262016300, 0.885001312941312790, 0.888255912810564040, 0.891487173736095430, 0.894694659858942030, 0.897877920418977740, 0.901036512106657030, +0.904169965535402300, 0.907277844846248630, 0.910359673202037810, 0.913415014743804930, 0.916443370282649990, 0.919444311410188670, 0.922417331486940380, 0.925361987203359600, +0.928277771919965740, 0.931164238601922990, 0.934020876884460450, 0.936847217381000520, 0.939642757177352910, 0.942407000809907910, 0.945139460265636440, 0.947839632630348210, +0.950507018715143200, 0.953141096979379650, 0.955741371959447860, 0.958307322114706040, 0.960838429629802700, 0.963334184139966960, 0.965794049203395840, 0.968217510730028150, +0.970604017376899720, 0.972953058779239650, 0.975264083594083790, 0.977536566555500030, 0.979769956320524220, 0.981963708996772770, 0.984117280691862110, 0.986230112612247470, +0.988301653414964680, 0.990331344306468960, 0.992318630218505860, 0.994262944906950000, 0.996163722127676010, 0.998020399361848830, 0.999832402914762500, 1.001599155366420700, +1.003320086747407900, 1.004994612187147100, 1.006622135639190700, 1.008202098309993700, 1.009733878076076500, 1.011216927319765100, 1.012650609016418500, 1.014034371823072400, +1.015367589890956900, 1.016649682074785200, 1.017880033701658200, 1.019058048725128200, 1.020183108747005500, 1.021254621446132700, 1.022271949797868700, 1.023234523832798000, + +}; +/* ---------------------------------------------------------------------- +** Test input - logarithmic chirp signal +** ------------------------------------------------------------------- */ + +float32_t testInput_f32[320] = + { + 0.000000000000000061, 0.002622410992047861, 0.005253663973466970, 0.007893770384930297, 0.010542741395035495, 0.013200587895525877, 0.015867320496454066, 0.018542949521290073, +0.021227485001971542, 0.023920936673895138, 0.026623313970853074, 0.029334626019908643, 0.032054881636210709, 0.034784089317753723, 0.037522257240071598, 0.040269393250875855, +0.043025504864628375, 0.045790599257054837, 0.048564683259595690, 0.051347763353792118, 0.054139845665610427, 0.056940935959702531, 0.059751039633601337, 0.062570161711849828, +0.065398306840066575, 0.068235479278943648, 0.071081682898178900, 0.073936921170339814, 0.076801197164660218, 0.079674513540768196, 0.082556872542344922, 0.085448275990715375, +0.088348725278367082, 0.091258221362398390, 0.094176764757897533, 0.097104355531246703, 0.100040993293358240, 0.102986677192832010, 0.105941405909045980, 0.108905177645166230, +0.111877990121087980, 0.114859840566297130, 0.117850725712659680, 0.120850641787131110, 0.123859584504392860, 0.126877549059407400, 0.129904530119898690, 0.132940521818751430, +0.135985517746334080, 0.139039510942737950, 0.142102493889940090, 0.145174458503884160, 0.148255396126476810, 0.151345297517508140, 0.154444152846483080, 0.157551951684374300, +0.160668682995289720, 0.163794335128054890, 0.166928895807713030, 0.170072352126936720, 0.173224690537355760, 0.176385896840798810, 0.179555956180445340, 0.182734853031894270, +0.185922571194139130, 0.189119093780459800, 0.192324403209221870, 0.195538481194587030, 0.198761308737133020, 0.201992866114384050, 0.205233132871247170, 0.208482087810360570, +0.211739708982344370, 0.215005973675965020, 0.218280858408200220, 0.221564338914212730, 0.224856390137231970, 0.228156986218334190, 0.231466100486134670, 0.234783705446379690, +0.238109772771442410, 0.241444273289723230, 0.244787176974952890, 0.248138452935395580, 0.251498069402956710, 0.254865993722190930, 0.258242192339209860, 0.261626630790492030, +0.265019273691591620, 0.268420084725748410, 0.271829026632395280, 0.275246061195565440, 0.278671149232197430, 0.282104250580339830, 0.285545324087251580, 0.288994327597401960, +0.292451217940364990, 0.295915950918612280, 0.299388481295203350, 0.302868762781368150, 0.306356748023990040, 0.309852388592980640, 0.313355634968552230, 0.316866436528383590, +0.320384741534681720, 0.323910497121136620, 0.327443649279772870, 0.330984142847692230, 0.334531921493712690, 0.338086927704900790, 0.341649102772995210, 0.345218386780727190, +0.348794718588032520, 0.352378035818156910, 0.355968274843654950, 0.359565370772282730, 0.363169257432780890, 0.366779867360555120, 0.370397131783246010, 0.374020980606193880, +0.377651342397795690, 0.381288144374756830, 0.384931312387234990, 0.388580770903877330, 0.392236442996751310, 0.395898250326170650, 0.399566113125414350, 0.403239950185338420, +0.406919678838884410, 0.410605214945482130, 0.414296472875345100, 0.417993365493664670, 0.421695804144698540, 0.425403698635752780, 0.429116957221065130, 0.432835486585582130, +0.436559191828633180, 0.440287976447505720, 0.444021742320914510, 0.447760389692375140, 0.451503817153472210, 0.455251921627031540, 0.459004598350192470, 0.462761740857380200, +0.466523240963184150, 0.470288988745136360, 0.474058872526396560, 0.477832778858340690, 0.481610592503056990, 0.485392196415748600, 0.489177471727042850, 0.492966297725213780, +0.496758551838309250, 0.500554109616195060, 0.504352844712508190, 0.508154628866524960, 0.511959331884944910, 0.515766821623591440, 0.519576963969030530, 0.523389622820107150, +0.527204660069405030, 0.531021935584629400, 0.534841307189911630, 0.538662630647041900, 0.542485759636628150, 0.546310545739186690, 0.550136838416161340, 0.553964484990880020, +0.557793330629441700, 0.561623218321546380, 0.565453988861259300, 0.569285480827721570, 0.573117530565801950, 0.576949972166696630, 0.580782637448476910, 0.584615355936589420, +0.588447954844309340, 0.592280259053150400, 0.596112091093235260, 0.599943271123626440, 0.603773616912622660, 0.607602943818024150, 0.611431064767369080, 0.615257790238142090, +0.619082928237961740, 0.622906284284749700, 0.626727661386881850, 0.630546860023327600, 0.634363678123782030, 0.638177911048790960, 0.641989351569874020, 0.645797789849653410, +0.649603013421986450, 0.653404807172108140, 0.657202953316791350, 0.660997231384523490, 0.664787418195706640, 0.668573287842887610, 0.672354611671016960, 0.676131158257749170, +0.679902693393781730, 0.683668980063242500, 0.687429778424128110, 0.691184845788802130, 0.694933936604551380, 0.698676802434213370, 0.702413191936877570, 0.706142850848662460, +0.709865521963579990, 0.713580945114492330, 0.717288857154159800, 0.720988991936399870, 0.724681080297347790, 0.728364850036839040, 0.732040025899910680, 0.735706329558433620, +0.739363479592880620, 0.743011191474238440, 0.746649177546067850, 0.750277147006723990, 0.753894805891742180, 0.757501857056394940, 0.761098000158428880, 0.764682931640995540, +0.768256344715771980, 0.771817929346292900, 0.775367372231492210, 0.778904356789468790, 0.782428563141483460, 0.785939668096195860, 0.789437345134148760, 0.792921264392515420, +0.796391092650110770, 0.799846493312681210, 0.803287126398485760, 0.806712648524170680, 0.810122712890953390, 0.813516969271127150, 0.816895063994893090, 0.820256639937531280, +0.823601336506926020, 0.826928789631450890, 0.830238631748229430, 0.833530491791779850, 0.836803995183058700, 0.840058763818912760, 0.843294416061954100, 0.846510566730867220, +0.849706827091166740, 0.852882804846411770, 0.856038104129895340, 0.859172325496819990, 0.862285065916973510, 0.865375918767918860, 0.868444473828712590, 0.871490317274166260, +0.874513031669661770, 0.877512195966544280, 0.880487385498096800, 0.883438171976119850, 0.886364123488128100, 0.889264804495180530, 0.892139775830360640, 0.894988594697921020, +0.897810814673113080, 0.900605985702712770, 0.903373654106265470, 0.906113362578062300, 0.908824650189867690, 0.911507052394417540, 0.914160101029702910, 0.916783324324059180, +0.919376246902079860, 0.921938389791372770, 0.924469270430179120, 0.926968402675872660, 0.929435296814361430, 0.931869459570409790, 0.934270394118903560, 0.936637600097074200, +0.938970573617708970, 0.941268807283364040, 0.943531790201601380, 0.945759008001275100, 0.947949942849885320, 0.950104073472023970, 0.952220875168933280, 0.954299819839202090, +0.956340376000621160, 0.958342008813221960, 0.960304180103520260, 0.962226348389994210, 0.964107968909812760, 0.965948493646846980, 0.967747371360983650, 0.969504047618768740, +0.971217964825405680, 0.972888562258134030, 0.974515276101013520, 0.976097539481141750, 0.977634782506330400, 0.979126432304266880, 0.980571913063189360, 0.981970646074102120, +0.983322049774557390, 0.984625539794035220, 0.985880529000944810, 0.987086427551279730, 0.988242642938953360, 0.989348580047844540, 0.990403641205582440, 0.991407226239099710, +0.992358732531984260, 0.993257555083659870, 0.994103086570423680, 0.994894717408374870, 0.995631835818261310, 0.996313827892278070, 0.996940077662846650, 0.997509967173408010, + + }; diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c new file mode 100644 index 00000000..2f68584a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c @@ -0,0 +1,415 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_graphic_equalizer_example_q31.c +* +* Description: Example showing an audio graphic equalizer constructed +* out of Biquad filters. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup GEQ5Band Graphic Audio Equalizer Example + * + * \par Description: + * \par + * This example demonstrates how a 5-band graphic equalizer can be constructed + * using the Biquad cascade functions. + * A graphic equalizer is used in audio applications to vary the tonal quality + * of the audio. + * + * \par Block Diagram: + * \par + * The design is based on a cascade of 5 filter sections. + * \image html GEQ_signalflow.gif + * Each filter section is 4th order and consists of a cascade of two Biquads. + * Each filter has a nominal gain of 0 dB (1.0 in linear units) and + * boosts or cuts signals within a specific frequency range. + * The edge frequencies between the 5 bands are 100, 500, 2000, and 6000 Hz. + * Each band has an adjustable boost or cut in the range of +/- 9 dB. + * For example, the band that extends from 500 to 2000 Hz has the response shown below: + * \par + * \image html GEQ_bandresponse.gif + * \par + * With 1 dB steps, each filter has a total of 19 different settings. + * The filter coefficients for all possible 19 settings were precomputed + * in MATLAB and stored in a table. With 5 different tables, there are + * a total of 5 x 19 = 95 different 4th order filters. + * All 95 responses are shown below: + * \par + * \image html GEQ_allbandresponse.gif + * \par + * Each 4th order filter has 10 coefficents for a grand total of 950 different filter + * coefficients that must be tabulated. The input and output data is in Q31 format. + * For better noise performance, the two low frequency bands are implemented using the high + * precision 32x64-bit Biquad filters. The remaining 3 high frequency bands use standard + * 32x32-bit Biquad filters. The input signal used in the example is a logarithmic chirp. + * \par + * \image html GEQ_inputchirp.gif + * \par + * The array bandGains specifies the gain in dB to apply in each band. + * For example, if bandGains={0, -3, 6, 4, -6}; then the output signal will be: + * \par + * \image html GEQ_outputchirp.gif + * \par + * \note The output chirp signal follows the gain or boost of each band. + * \par + * + * \par Variables Description: + * \par + * \li \c testInput_f32 points to the input data + * \li \c testRefOutput_f32 points to the reference output data + * \li \c testOutput points to the test output data + * \li \c inputQ31 temporary input buffer + * \li \c outputQ31 temporary output buffer + * \li \c biquadStateBand1Q31 points to state buffer for band1 + * \li \c biquadStateBand2Q31 points to state buffer for band2 + * \li \c biquadStateBand3Q31 points to state buffer for band3 + * \li \c biquadStateBand4Q31 points to state buffer for band4 + * \li \c biquadStateBand5Q31 points to state buffer for band5 + * \li \c coeffTable points to coefficient buffer for all bands + * \li \c gainDB gain buffer which has gains applied for all the bands + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_biquad_cas_df1_32x64_init_q31() + * - arm_biquad_cas_df1_32x64_q31() + * - arm_biquad_cascade_df1_init_q31() + * - arm_biquad_cascade_df1_q31() + * - arm_scale_q31() + * - arm_scale_f32() + * - arm_float_to_q31() + * - arm_q31_to_float() + * + * Refer + * \link arm_graphic_equalizer_example_q31.c \endlink + * + */ + + +/** \example arm_graphic_equalizer_example_q31.c + */ + + +#include "arm_math.h" +#include "math_helper.h" + +#if defined(SEMIHOSTING) +#include +#endif + +/* Length of the overall data in the test */ +#define TESTLENGTH 320 + +/* Block size for the underlying processing */ +#define BLOCKSIZE 32 + +/* Total number of blocks to run */ +#define NUMBLOCKS (TESTLENGTH/BLOCKSIZE) + +/* Number of 2nd order Biquad stages per filter */ +#define NUMSTAGES 2 + +#define SNR_THRESHOLD_F32 98 + +/* ------------------------------------------------------------------- + * External Declarations for Input and Output buffers + * ------------------------------------------------------------------- */ + +extern float32_t testInput_f32[TESTLENGTH]; +static float32_t testOutput[TESTLENGTH]; + +extern float32_t testRefOutput_f32[TESTLENGTH]; + +/* ---------------------------------------------------------------------- +** Q31 state buffers for Band1, Band2, Band3, Band4, Band5 +** ------------------------------------------------------------------- */ + +static q63_t biquadStateBand1Q31[4 * 2]; +static q63_t biquadStateBand2Q31[4 * 2]; +static q31_t biquadStateBand3Q31[4 * 2]; +static q31_t biquadStateBand4Q31[4 * 2]; +static q31_t biquadStateBand5Q31[4 * 2]; + +/* ---------------------------------------------------------------------- +** Q31 input and output buffers +** ------------------------------------------------------------------- */ + +q31_t inputQ31[BLOCKSIZE]; +q31_t outputQ31[BLOCKSIZE]; + +/* ---------------------------------------------------------------------- +** Entire coefficient table. There are 10 coefficients per 4th order Biquad +** cascade filter. The first 10 coefficients correspond to the -9 dB gain +** setting of band 1; the next 10 coefficient correspond to the -8 dB gain +** setting of band 1; and so on. There are 10*19=190 coefficients in total +** for band 1 (gains = -9, -8, -7, ..., 9). After this come the 190 coefficients +** for band 2. +** +** The coefficients are in Q29 format and require a postShift of 2. +** ------------------------------------------------------------------- */ + +const q31_t coeffTable[950] = { + + /* Band 1, -9 dB gain */ + 535576962, -1071153923, 535576962, 1073741824, -536870912, 535576962, -1063501998, 527979313, 1060865294, -524146981, + /* Band 1, -8 dB gain */ + 535723226, -1071446451, 535723226, 1073741824, -536870912, 535723226, -1063568947, 527903217, 1061230578, -524503778, + 535868593, -1071737186, 535868593, 1073741824, -536870912, 535868593, -1063627467, 527819780, 1061585502, -524850686, + 536013181, -1072026363, 536013181, 1073741824, -536870912, 536013181, -1063677598, 527728935, 1061930361, -525187972, + 536157109, -1072314217, 536157109, 1073741824, -536870912, 536157109, -1063719372, 527630607, 1062265438, -525515897, + 536300492, -1072600983, 536300492, 1073741824, -536870912, 536300492, -1063752815, 527524720, 1062591011, -525834716, + 536443447, -1072886894, 536443447, 1073741824, -536870912, 536443447, -1063777945, 527411186, 1062907350, -526144676, + 536586091, -1073172183, 536586091, 1073741824, -536870912, 536586091, -1063794775, 527289917, 1063214717, -526446017, + 536728541, -1073457082, 536728541, 1073741824, -536870912, 536728541, -1063803308, 527160815, 1063513366, -526738975, + 536870912, -1073741824, 536870912, 1073741824, -536870912, 536870912, -1063803543, 527023777, 1063803543, -527023777, + 537013321, -1074026642, 537013321, 1073741824, -536870912, 537013321, -1063795470, 526878696, 1064085490, -527300648, + 537155884, -1074311768, 537155884, 1073741824, -536870912, 537155884, -1063779073, 526725455, 1064359439, -527569803, + 537298718, -1074597435, 537298718, 1073741824, -536870912, 537298718, -1063754328, 526563934, 1064625617, -527831454, + 537441939, -1074883878, 537441939, 1073741824, -536870912, 537441939, -1063721205, 526394005, 1064884245, -528085806, + 537585666, -1075171331, 537585666, 1073741824, -536870912, 537585666, -1063679666, 526215534, 1065135536, -528333059, + 537730015, -1075460030, 537730015, 1073741824, -536870912, 537730015, -1063629666, 526028380, 1065379699, -528573409, + 537875106, -1075750212, 537875106, 1073741824, -536870912, 537875106, -1063571152, 525832396, 1065616936, -528807045, + 538021057, -1076042114, 538021057, 1073741824, -536870912, 538021057, -1063504065, 525627429, 1065847444, -529034151, + 538167989, -1076335977, 538167989, 1073741824, -536870912, 538167989, -1063428338, 525413317, 1066071412, -529254907, + + /* Band 2, -9 dB gain */ + 531784976, -1055497692, 523873415, 1066213307, -529420241, 531784976, -1040357886, 509828014, 1028908252, -494627367, + /* Band 2, -8 dB gain */ + 532357636, -1056601982, 524400080, 1066115844, -529326645, 532357636, -1040623406, 509562600, 1030462237, -496062122, + 532927392, -1057707729, 524931110, 1066024274, -529239070, 532927392, -1040848253, 509262081, 1031969246, -497457090, + 533494678, -1058816094, 525467240, 1065939047, -529157961, 533494678, -1041032161, 508925950, 1033429976, -498812573, + 534059929, -1059928204, 526009170, 1065860582, -529083734, 534059929, -1041174868, 508553717, 1034845124, -500128887, + 534623580, -1061045148, 526557561, 1065789260, -529016764, 534623580, -1041276126, 508144920, 1036215393, -501406373, + 535186068, -1062167969, 527113032, 1065725420, -528957385, 535186068, -1041335703, 507699125, 1037541500, -502645399, + 535747827, -1063297666, 527676151, 1065669351, -528905879, 535747827, -1041353386, 507215934, 1038824183, -503846368, + 536309295, -1064435183, 528247436, 1065621289, -528862476, 536309295, -1041328990, 506694984, 1040064203, -505009724, + 536870912, -1065581413, 528827349, 1065581413, -528827349, 536870912, -1041262354, 506135953, 1041262354, -506135953, + 537433117, -1066737194, 529416295, 1065549847, -528800610, 537433117, -1041153346, 505538564, 1042419457, -507225588, + 537996352, -1067903307, 530014622, 1065526651, -528782316, 537996352, -1041001864, 504902578, 1043536370, -508279208, + 538561061, -1069080480, 530622620, 1065511830, -528772462, 538561061, -1040807833, 504227800, 1044613981, -509297437, + 539127690, -1070269387, 531240527, 1065505333, -528770987, 539127690, -1040571205, 503514074, 1045653211, -510280946, + 539696690, -1071470656, 531868525, 1065507054, -528777778, 539696690, -1040291951, 502761277, 1046655011, -511230450, + 540268512, -1072684867, 532506750, 1065516837, -528792672, 540268512, -1039970063, 501969320, 1047620358, -512146700, + 540843613, -1073912567, 533155297, 1065534483, -528815459, 540843613, -1039605542, 501138139, 1048550251, -513030484, + 541422451, -1075154268, 533814224, 1065559750, -528845892, 541422451, -1039198394, 500267687, 1049445708, -513882621, + 542005489, -1076410460, 534483561, 1065592362, -528883686, 542005489, -1038748624, 499357932, 1050307760, -514703956, + 518903861, -1001986830, 486725277, 1037235801, -502367695, 518903861, -945834422, 446371043, 902366163, -400700571, + 520899989, -1005630916, 488289126, 1036926846, -502147311, 520899989, -946490935, 445581846, 907921945, -404936158, + 522893209, -1009290002, 489869792, 1036650484, -501961419, 522893209, -947006359, 444685310, 913306106, -409075225, + 524884763, -1012968199, 491470256, 1036407567, -501810737, 524884763, -947377809, 443679533, 918521018, -413116221, + 526875910, -1016669649, 493093518, 1036198712, -501695739, 526875910, -947602324, 442562672, 923569247, -417057897, + 528867927, -1020398503, 494742575, 1036024293, -501616651, 528867927, -947676875, 441332970, 928453558, -420899319, + 530862111, -1024158905, 496420407, 1035884447, -501573457, 530862111, -947598385, 439988777, 933176909, -424639872, + 532859778, -1027954970, 498129955, 1035779077, -501565907, 532859778, -947363742, 438528571, 937742446, -428279254, + 534862260, -1031790763, 499874098, 1035707863, -501593525, 534862260, -946969823, 436950987, 942153486, -431817474, + 536870912, -1035670279, 501655630, 1035670279, -501655630, 536870912, -946413508, 435254839, 946413508, -435254839, + 538887107, -1039597419, 503477238, 1035665609, -501751354, 538887107, -945691703, 433439146, 950526127, -438591937, + 540912240, -1043575967, 505341475, 1035692963, -501879659, 540912240, -944801359, 431503152, 954495080, -441829621, + 542947726, -1047609569, 507250741, 1035751307, -502039364, 542947726, -943739490, 429446349, 958324201, -444968987, + 544995000, -1051701717, 509207261, 1035839473, -502229165, 544995000, -942503190, 427268492, 962017400, -448011351, + 547055523, -1055855728, 511213065, 1035956193, -502447657, 547055523, -941089647, 424969617, 965578640, -450958226, + 549130774, -1060074734, 513269973, 1036100110, -502693359, 549130774, -939496155, 422550049, 969011913, -453811298, + 551222259, -1064361672, 515379585, 1036269804, -502964731, 551222259, -937720119, 420010407, 972321228, -456572401, + 553331507, -1068719280, 517543273, 1036463810, -503260192, 553331507, -935759057, 417351601, 975510582, -459243495, + 555460072, -1073150100, 519762181, 1036680633, -503578144, 555460072, -933610600, 414574832, 978583948, -461826644, + 494084017, -851422604, 404056273, 930151631, -423619864, 494084017, -673714108, 339502486, 561843007, -265801750, + 498713542, -859177141, 406587077, 929211656, -423786402, 498713542, -673274906, 338185129, 573719128, -272222942, + 503369016, -867012190, 409148384, 928362985, -424054784, 503369016, -672533059, 336693984, 585290277, -278599028, + 508052536, -874935599, 411746438, 927604291, -424422151, 508052536, -671478538, 335026905, 596558312, -284920289, + 512766286, -882955583, 414387826, 926933782, -424885216, 512766286, -670100998, 333182045, 607525792, -291177811, + 517512534, -891080712, 417079474, 926349262, -425440318, 517512534, -668389789, 331157902, 618195914, -297363485, + 522293635, -899319903, 419828635, 925848177, -426083491, 522293635, -666333963, 328953368, 628572440, -303470012, + 527112032, -907682405, 422642886, 925427679, -426810526, 527112032, -663922286, 326567785, 638659631, -309490882, + 531970251, -916177781, 425530105, 925084675, -427617023, 531970251, -661143261, 324000998, 648462180, -315420352, + 536870912, -924815881, 428498454, 924815881, -428498454, 536870912, -657985147, 321253420, 657985147, -321253420, + 541816719, -933606817, 431556352, 924617870, -429450209, 541816719, -654435997, 318326093, 667233900, -326985786, + 546810467, -942560921, 434712438, 924487114, -430467639, 546810467, -650483688, 315220754, 676214053, -332613816, + 551855042, -951688708, 437975532, 924420027, -431546101, 551855042, -646115970, 311939896, 684931422, -338134495, + 556953421, -961000826, 441354588, 924413001, -432680993, 556953421, -641320513, 308486839, 693391970, -343545389, + 562108672, -970508005, 444858642, 924462435, -433867780, 562108672, -636084967, 304865786, 701601770, -348844597, + 567323959, -980220994, 448496743, 924564764, -435102022, 567323959, -630397020, 301081886, 709566963, -354030710, + 572602539, -990150500, 452277894, 924716482, -436379394, 572602539, -624244471, 297141281, 717293726, -359102767, + 577947763, -1000307125, 456210977, 924914158, -437695705, 577947763, -617615296, 293051155, 724788245, -364060214, + 583363084, -1010701292, 460304674, 925154455, -439046908, 583363084, -610497723, 288819761, 732056685, -368902865, + 387379495, -506912469, 196933274, 840112184, -347208270, 387379495, 506912469, 196933274, -840112184, -347208270, + 401658082, -532275898, 207149427, 833765363, -343175316, 401658082, 532275898, 207149427, -833765363, -343175316, + 416472483, -558722695, 217902617, 827270154, -339107319, 416472483, 558722695, 217902617, -827270154, -339107319, + 431841949, -586290861, 229212798, 820624988, -335007540, 431841949, 586290861, 229212798, -820624988, -335007540, + 447786335, -615019650, 241100489, 813828443, -330879528, 447786335, 615019650, 241100489, -813828443, -330879528, + 464326111, -644949597, 253586805, 806879270, -326727141, 464326111, 644949597, 253586805, -806879270, -326727141, + 481482377, -676122557, 266693475, 799776409, -322554559, 481482377, 676122557, 266693475, -799776409, -322554559, + 499276882, -708581728, 280442865, 792519013, -318366296, 499276882, 708581728, 280442865, -792519013, -318366296, + 517732032, -742371685, 294857996, 785106465, -314167221, 517732032, 742371685, 294857996, -785106465, -314167221, + 536870912, -777538408, 309962566, 777538408, -309962566, 536870912, 777538408, 309962566, -777538408, -309962566, + 556717294, -814129313, 325780968, 769814766, -305757943, 556717294, 814129313, 325780968, -769814766, -305757943, + 577295658, -852193284, 342338310, 761935777, -301559360, 577295658, 852193284, 342338310, -761935777, -301559360, + 598631206, -891780698, 359660433, 753902014, -297373230, 598631206, 891780698, 359660433, -753902014, -297373230, + 620749877, -932943463, 377773927, 745714425, -293206383, 620749877, 932943463, 377773927, -745714425, -293206383, + 643678365, -975735041, 396706151, 737374355, -289066077, 643678365, 975735041, 396706151, -737374355, -289066077, + 667444134, -1020210487, 416485252, 728883588, -284960004, 667444134, 1020210487, 416485252, -728883588, -284960004, + 692075438, -1066426476, 437140179, 720244375, -280896294, 692075438, 1066426476, 437140179, -720244375, -280896294, + 717601336, -1114441339, 458700704, 711459472, -276883515, 717601336, 1114441339, 458700704, -711459472, -276883515, + 744051710, -1164315096, 481197437, 702532174, -272930673, 744051710, 1164315096, 481197437, -702532174, -272930673 + +}; + +/* ---------------------------------------------------------------------- +** Desired gains, in dB, per band +** ------------------------------------------------------------------- */ + +int gainDB[5] = {0, -3, 6, 4, -6}; + +float32_t snr; + + +/* ---------------------------------------------------------------------- + * Graphic equalizer Example + * ------------------------------------------------------------------- */ + +int32_t main(void) +{ + float32_t *inputF32, *outputF32; + arm_biquad_cas_df1_32x64_ins_q31 S1; + arm_biquad_cas_df1_32x64_ins_q31 S2; + arm_biquad_casd_df1_inst_q31 S3; + arm_biquad_casd_df1_inst_q31 S4; + arm_biquad_casd_df1_inst_q31 S5; + int i; + int32_t status; + + inputF32 = &testInput_f32[0]; + outputF32 = &testOutput[0]; + + /* Initialize the state and coefficient buffers for all Biquad sections */ + + arm_biquad_cas_df1_32x64_init_q31(&S1, NUMSTAGES, + (q31_t *) &coeffTable[190*0 + 10*(gainDB[0] + 9)], + &biquadStateBand1Q31[0], 2); + + arm_biquad_cas_df1_32x64_init_q31(&S2, NUMSTAGES, + (q31_t *) &coeffTable[190*1 + 10*(gainDB[1] + 9)], + &biquadStateBand2Q31[0], 2); + + arm_biquad_cascade_df1_init_q31(&S3, NUMSTAGES, + (q31_t *) &coeffTable[190*2 + 10*(gainDB[2] + 9)], + &biquadStateBand3Q31[0], 2); + + arm_biquad_cascade_df1_init_q31(&S4, NUMSTAGES, + (q31_t *) &coeffTable[190*3 + 10*(gainDB[3] + 9)], + &biquadStateBand4Q31[0], 2); + + arm_biquad_cascade_df1_init_q31(&S5, NUMSTAGES, + (q31_t *) &coeffTable[190*4 + 10*(gainDB[4] + 9)], + &biquadStateBand5Q31[0], 2); + + + /* Call the process functions and needs to change filter coefficients + for varying the gain of each band */ + + for(i=0; i < NUMBLOCKS; i++) + { + + /* ---------------------------------------------------------------------- + ** Convert block of input data from float to Q31 + ** ------------------------------------------------------------------- */ + + arm_float_to_q31(inputF32 + (i*BLOCKSIZE), inputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Scale down by 1/8. This provides additional headroom so that the + ** graphic EQ can apply gain. + ** ------------------------------------------------------------------- */ + + arm_scale_q31(inputQ31, 0x7FFFFFFF, -3, inputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Call the Q31 Biquad Cascade DF1 32x64 process function for band1, band2 + ** ------------------------------------------------------------------- */ + + arm_biquad_cas_df1_32x64_q31(&S1, inputQ31, outputQ31, BLOCKSIZE); + arm_biquad_cas_df1_32x64_q31(&S2, outputQ31, outputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Call the Q31 Biquad Cascade DF1 process function for band3, band4, band5 + ** ------------------------------------------------------------------- */ + + arm_biquad_cascade_df1_q31(&S3, outputQ31, outputQ31, BLOCKSIZE); + arm_biquad_cascade_df1_q31(&S4, outputQ31, outputQ31, BLOCKSIZE); + arm_biquad_cascade_df1_q31(&S5, outputQ31, outputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Convert Q31 result back to float + ** ------------------------------------------------------------------- */ + + arm_q31_to_float(outputQ31, outputF32 + (i * BLOCKSIZE), BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Scale back up + ** ------------------------------------------------------------------- */ + + arm_scale_f32(outputF32 + (i * BLOCKSIZE), 8.0f, outputF32 + (i * BLOCKSIZE), BLOCKSIZE); + }; + + snr = arm_snr_f32(testRefOutput_f32, testOutput, TESTLENGTH); + + status = (snr < SNR_THRESHOLD_F32) ? ARM_MATH_TEST_FAILURE : ARM_MATH_SUCCESS; + + if (status != ARM_MATH_SUCCESS) + { +#if defined (SEMIHOSTING) + printf("FAILURE\n"); +#else + while (1); /* main function does not return */ +#endif + } + else + { +#if defined (SEMIHOSTING) + printf("SUCCESS\n"); +#else + while (1); /* main function does not return */ +#endif + } + +} + +/** \endlink */ + + + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.c new file mode 100644 index 00000000..3d3cbe57 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.c @@ -0,0 +1,472 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/* + +Conflicting with the new clip functions in CMSIS-DSP and not used +in the examples. + +*/ +#if 0 +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + + +#endif diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.h b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.h new file mode 100644 index 00000000..a0dbdf73 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM0_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM0_config.txt new file mode 100644 index 00000000..13dc7839 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM3_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM3_config.txt new file mode 100644 index 00000000..55419ac8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM4_FP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM4_FP_config.txt new file mode 100644 index 00000000..fb9d24c9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM55_FP_MVE_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 00000000..4a65b1de --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM7_SP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM7_SP_config.txt new file mode 100644 index 00000000..82fc00c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/Abstract.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/Abstract.txt new file mode 100644 index 00000000..629bd606 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_linear_interp_example. + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/CMakeLists.txt new file mode 100644 index 00000000..00b18cdf --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_linear_interp_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_linear_interp_example) + + +include(config) +configApp(arm_linear_interp_example ${ROOT}) + +target_sources(arm_linear_interp_example PRIVATE math_helper.c arm_linear_interp_data.c arm_linear_interp_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_linear_interp_example PRIVATE CMSISDSP) + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 00000000..f527fa11 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/system_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 00000000..66a364c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 00000000..0392a899 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/system_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 00000000..3c5eda7d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 00000000..90eee9dc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 00000000..9d983d2e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 00000000..0ab7e3e9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM55/system_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 00000000..b76ebb7c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 00000000..78584996 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 00000000..75f9c18e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.c new file mode 100644 index 00000000..5f01bf4d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.c @@ -0,0 +1,288 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2020 ARM Limited. All rights reserved. +* +* $Date: 23. March 2020 +* $Revision: V1.7.0 +* +* Project: CMSIS DSP Library +* Title: arm_linear_interp_data.c +* +* Description: Data file used for example. Generation method described +* below +* +* Target Processor: Cortex-M55/Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Table generated from following MATLAB Command +* x = -pi: 0.005 : (2*pi - 0.005); +* y = sin(x); +* where pi value is 3.141592653589793 +* --------------------------------------------------------------------*/ + +const float arm_linear_interep_table[1884] = { + -0.00000000000000012246, -0.00499997916669272461, -0.00999983333416657426, -0.01499943750632833778, -0.01999866669333321897, -0.02499739591471236352, -0.02999550020249558760, -0.03499285460433645967, + -0.03998933418663432049, -0.04498481403766028952, -0.04997916927067827531, -0.05497227502706801550, -0.05996400647944477580, -0.06495423883478267102, -0.06994284733753272643, -0.07492970727274264608, + -0.07991469396917287582, -0.08489768280241610787, -0.08987854919801102627, -0.09485716863455760650, -0.09983341664682836292, -0.10480716882888259367, -0.10977830083717481091, -0.11474668839366414241, + -0.11971220728891958374, -0.12467473338522781778, -0.12963414261969488650, -0.13459031100734822339, -0.13954311464423671540, -0.14449242971052655982, -0.14943813247359924445, -0.15438009929114335228, + -0.15931820661424622720, -0.16425233099048111574, -0.16918234906699605724, -0.17410813759359589081, -0.17902957342582445643, -0.18394653352804138380, -0.18885889497650065749, -0.19376653496242188246, + -0.19866933079506152171, -0.20356715990477816658, -0.20845989984609966661, -0.21334742830078226583, -0.21822962308086962802, -0.22310636213174564468, -0.22797752353518849211, -0.23284298551241677799, + -0.23770262642713491097, -0.24255632478857228063, -0.24740395925452304815, -0.25224540863437805438, -0.25708055189215500702, -0.26190926814952469881, -0.26673143668883125823, -0.27154693695611287207, + -0.27635564856411409806, -0.28115745129529429169, -0.28595222510483570000, -0.29073985012364278457, -0.29552020666133954618, -0.30029317520926179785, -0.30505863644344366481, -0.30981647122760291868, + -0.31456656061611770747, -0.31930878585700123162, -0.32404302839486853749, -0.32876916987390319980, -0.33348709214081440066, -0.33819667724779156615, -0.34289780745545156426, -0.34759036523578440425, + -0.35227423327508999851, -0.35694929447691170488, -0.36161543196496220842, -0.36627252908604768233, -0.37092046941298267848, -0.37555913674750113218, -0.38018841512316164932, -0.38480818880824513295, + -0.38941834230865052247, -0.39401876037078076287, -0.39860932798442311187, -0.40318993038562678244, -0.40776045305957026033, -0.41232078174342468024, -0.41687080242921104034, -0.42141040136664820182, + -0.42593946506599966728, -0.43045788030090881282, -0.43496553411123045629, -0.43946231380585343285, -0.44394810696551983975, -0.44842280144563440025, -0.45288628537906855387, -0.45733844717895566490, + -0.46177917554148295576, -0.46620835944867272671, -0.47062588817115835749, -0.47503165127095098308, -0.47942553860420311640, -0.48380744032396016951, -0.48817724688290742296, -0.49253484903610883494, + -0.49688013784373685766, -0.50121300467379792387, -0.50553334120484727521, -0.50984103942869607451, -0.51413599165311318906, -0.51841809050451703733, -0.52268722893065910906, -0.52694330020330160114, + -0.53118619792088350717, -0.53541581601118337641, -0.53963204873396963812, -0.54383479068364282139, -0.54802393679187377806, -0.55219938233022769491, -0.55636102291278377585, -0.56050875449874415501, + -0.56464247339503548240, -0.56876207625890007336, -0.57286746010048128497, -0.57695852228539701301, -0.58103516053730530633, -0.58509727294046220969, -0.58914475794226950356, -0.59317751435581278496, + -0.59719544136239222087, -0.60119843851404120016, -0.60518640573603954547, -0.60915924332941506769, -0.61311685197343401832, -0.61705913272808676773, -0.62098598703655971676, -0.62489731672769976978, + -0.62879302401846870474, -0.63267301151638644097, -0.63653718222196797871, -0.64038543953114723806, -0.64421768723769123888, -0.64803382953560739743, -0.65183377102153672311, -0.65561741669714024283, + -0.65938467197147310195, -0.66313544266334978339, -0.66686963500369800251, -0.67058715563790372016, -0.67428791162814527560, -0.67797181045571497382, -0.68163876002333423365, -0.68528866865745496906, + -0.68892144511055120049, -0.69253699856340145136, -0.69613523862735682268, -0.69971607534660351657, -0.70327941920041048274, -0.70682518110536607381, -0.71035327241760792827, -0.71386360493503686619, + -0.71735609089952279138, -0.72083064299909871409, -0.72428717437014267233, -0.72772559859955054939, -0.73114582972689612372, -0.73454778224657879537, -0.73793137110996287475, -0.74129651172750310462, + -0.74464311997085930184, -0.74797111217499967495, -0.75128040514029281738, -0.75457091613458637802, -0.75784256289527696104, -0.76109526363136648097, -0.76432893702550519510, -0.76754350223602707537, + -0.77073887889896930403, -0.77391498713008166632, -0.77707174752682406371, -0.78020908117035037144, -0.78332690962748341423, -0.78642515495267417691, -0.78950373968995057883, -0.79256258687485459102, + -0.79560162003636603067, -0.79862076319881414310, -0.80161994088377730439, -0.80459907811196917926, -0.80755810040511433190, -0.81049693378780995889, -0.81341550478937396651, -0.81631374044568350001, + -0.81919156830099826294, -0.82204891640977173495, -0.82488571333844995515, -0.82770188816725775993, -0.83049737049197047689, -0.83327209042567607078, -0.83602597860052074719, -0.83875896616944312090, + -0.84147098480789661590, -0.84416196671555643327, -0.84683184461801519483, -0.84948055176846437586, -0.85210802194936297038, -0.85471418947409338873, -0.85729898918860358847, -0.85986235647303466134, + -0.86240422724333842819, -0.86492453795287804752, -0.86742322559401685567, -0.86990022769969410632, -0.87235548234498638820, -0.87478892814865483185, -0.87720050427468176935, -0.87959015043378918630, + -0.88195780688494751498, -0.88430341443686910630, -0.88662691444948726893, -0.88892824883542254089, -0.89120736006143541630, -0.89346419114986364018, -0.89569868568004784581, -0.89791078778974076080, + -0.90010044217650508891, -0.90226759409909518261, -0.90441218937882594808, -0.90653417440092687318, -0.90863349611588339894, -0.91071010204076130456, -0.91276394026052121156, -0.91479495942931421393, + -0.91680310877176696138, -0.91878833808425064422, -0.92075059773613565639, -0.92268983867103304686, -0.92460601240802031686, -0.92649907104285411652, -0.92836896724916673218, -0.93021565427965069439, + -0.93203908596722639945, -0.93383921672619663035, -0.93561600155338597862, -0.93736939602926661053, -0.93909935631906760189, -0.94080583917387217152, -0.94248880193169759512, -0.94414820251856268474, + -0.94578399944953905898, -0.94739615182978875740, -0.94898461935558620084, -0.95054936231532616286, -0.95209034159051575408, -0.95360751865675374983, -0.95510085558469226541, -0.95657031504098599672, + -0.95801586028922502969, -0.95943745519085332774, -0.96083506420607267540, -0.96220865239473030162, -0.96355818541719306936, -0.96488362953520556697, -0.96618495161273409977, -0.96746211911679436124, + -0.96871510011826533759, -0.96994386329268711400, -0.97114837792104458103, -0.97232861389053459877, -0.97348454169531939417, -0.97461613243726408218, -0.97572335782665908788, -0.97680619018292724753, + -0.97786460243531625469, -0.97889856812357467497, -0.97990806139861430513, -0.98089305702315576774, -0.98185353037235978402, -0.98278945743444268146, -0.98370081481127658041, -0.98458757971897459260, + -0.98544972998846025458, -0.98628724406602152897, -0.98710010101385037284, -0.98788828051056520874, -0.98865176285171985082, -0.98939052895029533374, -0.99010456033717775259, -0.99079383916161978263, + -0.99145834819168643381, -0.99209807081468681655, -0.99271299103758847693, -0.99330309348741807618, -0.99386836341164486175, -0.99440878667855037154, -0.99492434977758092973, -0.99541503981968604275, + -0.99588084453764003090, -0.99632175228634944908, -0.99673775204314341014, -0.99712883340804969734, -0.99749498660405444550, -0.99783620247734694519, -0.99815247249754812664, -0.99844378875792394457, + -0.99871014397558299791, -0.99895153149165882844, -0.99916794527147601013, -0.99935937990470136150, -0.99952583060547905980, -0.99966729321255021201, -0.99978376418935699377, -0.99987524062413102310, + -0.99994172022996630211, -0.99998320134487606037, -0.99999968293183461032, -0.99999116457880310449, -0.99995764649874008256, -0.99989912952959558723, -0.99981561513429084709, -0.99970710540068152827, + -0.99957360304150510988, -0.99941511139431382649, -0.99923163442139051327, -0.99902317670964990715, -0.99878974347052396077, -0.99853134053983161333, -0.99824797437763246322, -0.99793965206806589663, + -0.99760638131917367399, -0.99724817046270708421, -0.99686502845391877781, -0.99645696487133927910, -0.99602398991653673388, -0.99556611441386244632, -0.99508334981018020660, -0.99457570817457985335, + -0.99404320219807595915, -0.99348584519329008469, -0.99290365109411848898, -0.99229663445538318634, -0.99166481045246857029, -0.99100819488094182841, -0.99032680415615803593, -0.98962065531284981734, + -0.98888976600470146483, -0.98813415450390762462, -0.98735383970071644022, -0.98654884110295737454, -0.98571917883555348894, -0.98486487364001817912, -0.98398594687393692304, -0.98308242051043293053, + -0.98215431713761847110, -0.98120165995802932635, -0.98022447278804547555, -0.97922278005729512795, -0.97819660680804465525, -0.97714597869457153756, -0.97607092198252420889, -0.97497146354826413894, + -0.97384763087819514737, -0.97269945206807539861, -0.97152695582231529681, -0.97033017145326005970, -0.96910912888045630531, -0.96786385862990509388, -0.96659439183329753931, -0.96530076022723765305, + -0.96398299615244809058, -0.96264113255296213101, -0.96127520297529989168, -0.95988524156762966566, -0.95847128307891416021, -0.95703336285804208039, -0.95557151685294383636, -0.95408578160969381710, + -0.95257619427159534453, -0.95104279257825341531, -0.94948561486463034509, -0.94790470006008820114, -0.94630008768741435965, -0.94467181786183496150, -0.94301993129001049354, -0.94134446926901937935, + -0.93964547368532491678, -0.93792298701372800451, -0.93617705231630599094, -0.93440771324133520270, -0.93261501402220048362, -0.93079899947628874646, -0.92895971500386931297, -0.92709720658695793372, + -0.92521152078816815134, -0.92330270474954678761, -0.92137080619139533066, -0.91941587341107711140, -0.91743795528180982490, -0.91543710125144361900, -0.91341336134122519397, -0.91136678614454669223, + -0.90929742682568159839, -0.90720533511850520725, -0.90509056332520076982, -0.90295316431495353804, -0.90079319152262726789, -0.89861069894742917619, -0.89640574115155979840, -0.89417837325884952371, + -0.89192865095337958703, -0.88965663047809040442, -0.88736236863337547565, -0.88504592277566129788, -0.88270735081597395677, -0.88034671121849061848, -0.87796406299907814308, -0.87555946572381770920, + -0.87313297950751633802, -0.87068466501220309617, -0.86821458344561253107, -0.86572279655965511669, -0.86320936664887359946, -0.86067435654888468921, -0.85811782963480887076, -0.85553984981968544954, + -0.85294048155287616186, -0.85031978981845190990, -0.84767784013356972661, -0.84501469854683375349, -0.84233043163664556019, -0.83962510650953781077, -0.83689879079849771593, -0.83415155266127583022, + -0.83138346077868308104, -0.82859458435287203226, -0.82578499310560804503, -0.82295475727652578346, -0.82010394762137406310, -0.81723263541024548928, -0.81434089242579588142, -0.81142879096144915341, + -0.80849640381958998159, -0.80554380430974481531, -0.80257106624674723339, -0.79957826394889397470, -0.79656547223608642483, -0.79353276642796100049, -0.79048022234200465697, -0.78740791629166062560, + -0.78431592508441982936, -0.78120432601990186239, -0.77807319688792120349, -0.77492261596654288258, -0.77175266202012560157, -0.76856341429735364201, -0.76535495252925345167, -0.76212735692720223746, + -0.75888070818092168146, -0.75561508745646188689, -0.75233057639417066920, -0.74902725710665341019, -0.74570521217671992265, -0.74236452465532121181, -0.73900527805947069382, -0.73562755637015875276, + -0.73223144403025131055, -0.72881702594237995907, -0.72538438746681943581, -0.72193361441935266498, -0.71846479306912613971, -0.71497801013649253665, -0.71147335279084422677, -0.70795090864843213119, + -0.70441076577017613936, -0.70085301265946364779, -0.69727773825993766277, -0.69368503195327169131, -0.69007498355693630554, -0.68644768332195305049, -0.68280322193063958114, -0.67914169049434047754, + -0.67546318055115084356, -0.67176778406362758211, -0.66805559341649090044, -0.66432670141431326982, -0.66058120127920061382, -0.65681918664846095091, -0.65304075157226471049, -0.64924599051129161520, + -0.64543499833437067981, -0.64160787031610766462, -0.63776470213450353608, -0.63390558986856326840, -0.63003062999589209969, -0.62613991939028512679, -0.62223355531930457651, -0.61831163544184919445, + -0.61437425780571164324, -0.61042152084512746324, -0.60645352337831459621, -0.60247036460500380528, -0.59847214410395643824, -0.59445896183047686190, -0.59043091811391257284, -0.58638811365514731389, + -0.58233064952408175596, -0.57825862715710785178, -0.57417214835457219824, -0.57007131527823284856, -0.56595623044870269069, -0.56182699674288816283, -0.55768371739141653354, -0.55352649597605652065, + -0.54935543642712658663, -0.54517064302089812688, -0.54097222037698844410, -0.53676027345574461869, -0.53253490755562105097, -0.52829622831054467991, -0.52404434168727598298, -0.51977935398275876278, + -0.51550137182146404946, -0.51121050215272290096, -0.50690685224805331899, -0.50259052969847872738, -0.49826164241183845682, -0.49392029861008907021, -0.48956660682659941530, -0.48520067590343696207, + -0.48082261498864814486, -0.47643253353352743584, -0.47203054128988253257, -0.46761674830728994223, -0.46319126493034507019, -0.45875420179590142844, -0.45430566983030634676, -0.44984578024662685847, + -0.44537464454187103424, -0.44089237449419821369, -0.43639908216012618380, -0.43189487987172925365, -0.42737988023382966762, -0.42285419612118396726, -0.41831794067565886142, -0.41377122730340420986, + -0.40921416967201718062, -0.40464688170770196640, -0.40006947759241939799, -0.39548207176103394866, -0.39088477889845207880, -0.38627771393675675027, -0.38166099205233156022, -0.37703472866298326505, + -0.37239903942505520051, -0.36775404023053764879, -0.36309984720416821347, -0.35843657670053008513, -0.35376434530114259092, -0.34908326981154819135, -0.34439346725838987373, -0.33969505488648726876, + -0.33498815015590455157, -0.33027287073901562264, -0.32554933451755990736, -0.32081765957969693437, -0.31607796421705369738, -0.31133036692176702109, -0.30657498638352281839, -0.30181194148658646581, + -0.29704135130683229082, -0.29226333510876589816, -0.28747801234254427571, -0.28268550264098690761, -0.27788592581658666525, -0.27307940185851381498, -0.26826605092961780530, -0.26344599336342072737, + -0.25861934966111072010, -0.25378624048852843620, -0.24894678667315245368, -0.24410110920107558341, -0.23924932921398228691, -0.23439156800611909981, -0.22952794702126408377, -0.22465858784968809059, + -0.21978361222511683115, -0.21490314202168656066, -0.21001729925089901441, -0.20512620605856862754, -0.20022998472177039320, -0.19532875764578278011, -0.19042264736102693101, -0.18551177652000533369, + -0.18059626789423280369, -0.17567624437116896585, -0.17075182895114521253, -0.16582314474429141193, -0.16089031496745564986, -0.15595346294112538699, -0.15101271208634373111, -0.14606818592162557069, + -0.14112000805986710250, -0.13616830220525713568, -0.13121319215018367732, -0.12625480177214090660, -0.12129325503062962643, -0.11632867596405992161, -0.11136118868664945936, -0.10639091738532231723, + -0.10141798631660174645, -0.09644251980350543318, -0.09146464223243663816, -0.08648447805007625222, -0.08150215176026900932, -0.07651778792091265546, -0.07153151114084313478, -0.06654344607672113554, + -0.06155371742991302270, -0.05656244994337508020, -0.05156976839853451289, -0.04657579761216946307, -0.04158066243329036626, -0.03658448774001610282, -0.03158739843645377854, -0.02658951944957526833, + -0.02159097572609583807, -0.01659189222934778080, -0.01159239393615815392, -0.00659260583372344670, -0.00159265291648670571, 0.00340733981698999704, 0.00840724736714873987, 0.01340694473656162643, + 0.01840630693305393001, 0.02340520897283157251, 0.02840352588360391117, 0.03340113270770895398, 0.03839790450523550280, 0.04339371635714930203, 0.04838844336841426758, 0.05338196067111569687, + 0.05837414342758021069, 0.06336486683349934479, 0.06835400612104790274, 0.07334143656200353689, 0.07832703347086542034, 0.08331067220796961603, 0.08829222818260772099, 0.09327157685613979288, + 0.09824859374510880317, 0.10322315442435085753, 0.10819513453010849713, 0.11316440976313804634, 0.11813085589181793189, 0.12309434875525272768, 0.12805476426637979470, 0.13301197841506973152, + 0.13796586727122742144, 0.14291630698788859721, 0.14786317380431862611, 0.15280634404910475865, 0.15774569414324876582, 0.16268110060325466359, 0.16761244004421843590, 0.17253958918291092961, + 0.17746242484086069413, 0.18238082394743185266, 0.18729466354290330576, 0.19220382078154110705, 0.19710817293466997846, 0.20200759739374196666, 0.20690197167339988149, 0.21179117341454209433, + 0.21667508038737973153, 0.22155357049449328488, 0.22642652177388328250, 0.23129381240202195880, 0.23615532069689712524, 0.24101092512105504184, 0.24586050428463715467, 0.25070393694841736076, + 0.25554110202683133490, 0.26037187859100452414, 0.26519614587177353648, 0.27001378326270797370, 0.27482467032312413169, 0.27962868678109636944, 0.28442571253646264928, 0.28921562766382935550, + 0.29399831241556773076, 0.29877364722480853620, 0.30354151270842943955, 0.30830178967004207014, 0.31305435910297030322, 0.31779910219322587972, 0.32253590032247908548, 0.32726463507102254713, + 0.33198518822073419532, 0.33669744175803123509, 0.34140127787682106320, 0.34609657898144485788, 0.35078322768961994749, 0.35546110683537274211, 0.36013009947196866767, 0.36479008887483416190, + 0.36944095854447722704, 0.37408259220939837908, 0.37871487382899815533, 0.38333768759647646185, 0.38795091794173042210, 0.39255444953424156740, 0.39714816728596030737, 0.40173195635418124105, + 0.40630570214441691368, 0.41086929031326063777, 0.41542260677124637214, 0.41996553768569905296, 0.42449796948358270443, 0.42901978885433855737, 0.43353088275271783880, 0.43803113840160834425, + 0.44252044329485257235, 0.44699868520006236228, 0.45146575216142326159, 0.45592153250249434215, 0.46036591482899841266, 0.46479878803160906697, 0.46922004128872724094, 0.47362956406925205144, + 0.47802724613534297582, 0.48241297754517775687, 0.48678664865569953868, 0.49114815012535872896, 0.49549737291684503582, 0.49983420829981556333, 0.50415854785361158275, 0.50847028346996991921, + 0.51276930735572390230, 0.51705551203550070838, 0.52132879035440660154, 0.52558903548070656786, 0.52983614090849351363, 0.53407000046035324470, 0.53829050829001767742, 0.54249755888501083323, + 0.54669104706928728366, 0.55087086800586004820, 0.55503691719942394034, 0.55918909049896592389, 0.56332728410037014033, 0.56745139454901150078, 0.57156131874234383794, 0.57565695393247651168, + 0.57973819772874324308, 0.58380494810026106745, 0.58785710337848284812, 0.59189456225973779979, 0.59591722380776435131, 0.59992498745623268341, 0.60391775301126071618, 0.60789542065391743986, + 0.61185789094271936239, 0.61580506481611496650, 0.61973684359496328256, 0.62365312898499980498, 0.62755382307929374885, 0.63143882836069553655, 0.63530804770427573569, 0.63916138437975222875, + 0.64299874205390883386, 0.64682002479300404474, 0.65062513706516744705, 0.65441398374279102779, 0.65818647010490505256, 0.66194250183954728151, 0.66568198504611930666, 0.66940482623773611692, + 0.67311093234356178527, 0.67680021071113694031, 0.68047256910869413637, 0.68412791572746478597, 0.68776615918397387972, 0.69138720852232482539, 0.69499097321647207437, 0.69857736317248630975, + 0.70214628873080553451, 0.70569766066847683383, 0.70923139020138625810, 0.71274738898647960195, 0.71624556912397063790, 0.71972584315953824774, 0.72318812408651222956, 0.72663232534805011209, + 0.73005836083929964708, 0.73346614490955241994, 0.73685559236438336050, 0.74022661846778314843, 0.74357913894427474233, 0.74691306998102069414, 0.75022832822991902813, 0.75352483080968579721, + 0.75680249530792831347, 0.76006123978320494494, 0.76330098276707347704, 0.76652164326612803880, 0.76972314076402448269, 0.77290539522349099855, 0.77606832708833239920, 0.77921185728541675353, + 0.78233590722665280470, 0.78544039881095495392, 0.78852525442619503249, 0.79159039695114352675, 0.79463574975739748041, 0.79766123671129407491, 0.80066678217581777055, 0.80365231101248835177, + 0.80661774858324053472, 0.80956302075228947501, 0.81248805388798428506, 0.81539277486464900591, 0.81827711106441036737, 0.82114099037901422395, 0.82398434121162578148, 0.82680709247862294031, + 0.82960917361137087589, 0.83239051455798740431, 0.83515104578509358202, 0.83789069827955253711, 0.84060940355019453385, 0.84330709362953004682, 0.84598370107544651475, 0.84863915897289776691, + 0.85127340093557457568, 0.85388636110756510611, 0.85647797416500115464, 0.85904817531769128713, 0.86159690031074054328, 0.86412408542615726237, 0.86662966748444436593, 0.86911358384618120354, + 0.87157577241358819009, 0.87401617163207945271, 0.87643472049180148886, 0.87883135852915883479, 0.88120602582832530114, 0.88355866302274232993, 0.88588921129660269660, 0.88819761238632033429, + 0.89048380858198861176, 0.89274774272882151394, 0.89498935822858360911, 0.89720859904100391802, 0.89940540968517768139, 0.90157973524095347262, 0.90373152135030576648, 0.90586071421869318598, + 0.90796726061640542493, 0.91005110787989218490, 0.91211220391308034383, 0.91415049718867658068, 0.91616593674945501213, 0.91815847220953161756, 0.92012805375562400911, 0.92207463214829554765, + 0.92399815872318802334, 0.92589858539223723888, 0.92777586464487560303, 0.92962994954921940316, 0.93146079375324264404, 0.93326835148593556557, 0.93505257755844939371, 0.93681342736522454917, + 0.93855085688510786479, 0.94026482268245192842, 0.94195528190820099201, 0.94362219230096244793, 0.94526551218806342813, 0.94688520048659219341, 0.94848121670442564479, 0.95005352094124184692, + 0.95160207388951612018, 0.95312683683550569747, 0.95462777166021639541, 0.95610484084035574082, 0.95755800744927122015, 0.95898723515787320792, 0.96039248823554335122, 0.96177373155102841018, + 0.96313093057331666813, 0.96446405137250368345, 0.96577306062063883463, 0.96705792559255909779, 0.96831861416670717002, 0.96955509482593427162, 0.97076733665828829345, 0.97195530935778684523, + 0.97311898322517387250, 0.97425832916866350608, 0.97537331870466648098, 0.97646392395850256651, 0.97753011766509712022, 0.97857187316966298685, 0.97958916442836685423, 0.98058196600898028805, + 0.98155025309151555657, 0.98249400146884580121, 0.98341318754731077423, 0.98430778834730647819, 0.98517778150385948432, 0.98602314526718615184, 0.98684385850323652623, 0.98763990069422247231, + 0.98841125193913059732, 0.98915789295421985283, 0.98987980507350392667, 0.99057697024921731455, 0.99124937105226695877, 0.99189699067266778876, 0.99251981291996316248, 0.99311782222362920969, + 0.99369100363346452021, 0.99423934281996362294, 0.99476282607467558794, 0.99526144031054608607, 0.99573517306224534895, 0.99618401248647925339, 0.99660794736228552892, 0.99700696709131431117, + 0.99738106169809326307, 0.99773022183027670895, 0.99805443875887944749, 0.99835370437849513259, 0.99862801120749888906, 0.99887735238823427419, 0.99910172168718480723, 0.99930111349512962260, + 0.99947552282728402417, 0.99962494532342371922, 0.99974937724799395333, 0.99984881549020332425, 0.99992325756410094240, 0.99997270160863860333, 0.99999714638771797226, 0.99999659129022078208, + 0.99997103633002448753, 0.99992048214600159906, 0.99984493000200436175, 0.99974438178683222578, 0.99961884001418532808, 0.99946830782260165371, 0.99929278897537787696, 0.99909228786047621362, + 0.99886680949041417588, 0.99861635950213900603, 0.99834094415688756641, 0.99804057034002902071, 0.99771524556089319358, 0.99736497795258272081, 0.99698977627176943450, 0.99658964989847598215, + 0.99616460883584057040, 0.99571466370986794203, 0.99523982576916258935, 0.99474010688464831187, 0.99421551954927123163, 0.99366607687768748747, 0.99309179260593527516, 0.99249268109109134439, + 0.99186875731091250774, 0.99122003686346060736, 0.99054653596671304872, 0.98984827145815734717, 0.98912526079436957627, 0.98837752205057904931, 0.98760507392021512629, 0.98680793571444103129, + 0.98598612736167012827, 0.98513966940706865216, 0.98426858301204134261, 0.98337288995370264466, 0.98245261262433225546, 0.98150777403081579386, 0.98053839779406870569, 0.97954450814844640227, + 0.97852612994113830069, 0.97748328863154654300, 0.97641601029064950534, 0.97532432160035020807, 0.97420824985280907171, 0.97306782294976124081, 0.97190306940182058515, 0.97071401832776471608, + 0.96950069945380856762, 0.96826314311286099112, 0.96700138024376580681, 0.96571544239052919956, 0.96440536170153046136, 0.96307117092871830089, 0.96171290342679316421, 0.96033059315237145892, + 0.95892427466313823192, 0.95749398311698219466, 0.95603975427111775875, 0.95456162448119030728, 0.95305963070036747720, 0.95153381047841534279, 0.94998420196076049926, 0.94841084388753493783, + 0.94681377559260859744, 0.94519303700260559609, 0.94354866863590625137, 0.94188071160163422402, 0.94018920759862834036, 0.93847419891440064799, 0.93673572842407859529, 0.93497383958933455439, + 0.93318857645729724748, 0.93137998365945207091, 0.92954810641052476594, 0.92769299050735110068, 0.92581468232773200810, 0.92391322882927429117, 0.92198867754821589582, 0.92004107659823930465, + 0.91807047466926661183, 0.91607692102624327379, 0.91406046550790653882, 0.91202115852553944375, 0.90995905106171026677, 0.90787419466899810239, 0.90576664146870400351, 0.90363644414954891193, + 0.90148365596635438024, 0.89930833073871296879, 0.89711052284964198922, 0.89489028724422425842, 0.89264767942823419755, 0.89038275546675049732, 0.88809557198275379530, 0.88578618615571291794, + 0.88345465572015269284, 0.88110103896421276826, 0.87872539472818933515, 0.87632778240306463680, 0.87390826192902193448, 0.87146689379394692843, 0.86900373903191607816, 0.86651885922166937970, + 0.86401231648507381689, 0.86148417348556682871, 0.85893449342659156098, 0.85636334005001668590, 0.85377077763454289894, 0.85115687099409531591, 0.84852168547620410166, 0.84586528696036911157, + 0.84318774185641620633, 0.84048911710283280563, 0.83776948016509722450, 0.83502889903399135640, 0.83226744222390069972, 0.82948517877110161667, 0.82668217823203571371, 0.82385851068156967791, + 0.82101424671124645371, 0.81814945742751654656, 0.81526421444996288734, 0.81235858990950959857, 0.80943265644661888114, 0.80648648720947491153, 0.80352015585215519344, 0.80053373653278914190, + 0.79752730391170367774, 0.79450093314955871904, 0.79145469990546535310, 0.78838868033509590383, 0.78530295108877989918, 0.78219758930958782628, 0.77907267263140256297, 0.77592827917697804185, + 0.77276448755598647899, 0.76958137686305472247, 0.76637902667578372551, 0.76315751705276135830, 0.75991692853156034282, 0.75665734212672508541, 0.75337883932774563078, 0.75008150209702162403, + 0.74676541286781195073, 0.74343065454217460708, 0.74007731048889391356, 0.73670546454139651527, 0.73331520099565583592, 0.72990660460808376442, 0.72647976059341234922, 0.72303475462256339146, + 0.71957167282050704671, 0.71609060176410799237, 0.71259162847996104784, 0.70907484044221602559, 0.70554032557039114693, 0.70198817222717391218, 0.69841846921621286715, 0.69483130577989704602, + 0.69122677159712608841, 0.68760495678106647865, 0.68396595187690023554, 0.68030984785955983529, 0.67663673613145614016, 0.67294670852019056184, 0.66923985727626122966, 0.66551627507075594714, + 0.66177605499303648884, 0.65801929054840968547, 0.65424607565579095958, 0.65045650464535575974, 0.64665067225618266811, 0.64282867363388296322, 0.63899060432822296640, 0.63513656029073550791, + 0.63126663787232040193, 0.62738093382083737204, 0.62347954527868487684, 0.61956256978037316241, 0.61563010525008554641, 0.61168224999923104246, 0.60771910272398499409, 0.60374076250282282530, + 0.59974732879404257790, 0.59573890143327967728, 0.59171558063100893055, 0.58767746697004086265, 0.58362466140300639506, 0.57955726524983441905, 0.57547538019521626840, 0.57137910828606597313, + 0.56726855192896752378, 0.56314381388761636238, 0.55900499728024832802, 0.55485220557706316225, 0.55068554259763680125, 0.54650511250832733978, 0.54231101981966889358, 0.53810336938376035487, + 0.53388226639164337861, 0.52964781637067259723, 0.52540012518187872992, 0.52113929901731992356, 0.51686544439742831969, 0.51257866816834640744, 0.50827907749925749226, 0.50396677987970384116, + 0.49964188311690155286, 0.49530449533304393706, 0.49095472496260045281, 0.48659268074960349004, 0.48221847174493104315, 0.47783220730358016981, 0.47343399708193417696, 0.46902395103501909324, + 0.46460217941375647754, 0.46016879276220612471, 0.45572390191480421917, 0.45126761799359005334, 0.44680005240542952638, 0.44232131683922926157, 0.43783152326314600522, 0.43333078392178486782, + 0.42881921133339495622, 0.42429691828705606849, 0.41976401783985833882, 0.41522062331407771918, 0.41066684829434035864, 0.40610280662478442926, 0.40152861240621368077, 0.39694437999324616584, + 0.39235022399145291772, 0.38774625925449479613, 0.38313260088125000724, 0.37850936421293840395, 0.37387666483023551667, 0.36923461855038458568, 0.36458334142430037783, 0.35992294973366972810, + 0.35525355998804170055, 0.35057528892191675007, 0.34588825349182744651, 0.34119257087341625656, 0.33648835845850372239, 0.33177573385215508583, 0.32705481486973969618, 0.32232571953398708731, + 0.31758856607203389544, 0.31284347291246999978, 0.30809055868237716913, 0.30332994220436321209, 0.29856174249359301864, 0.29378607875481060896, 0.28900307037936062704, 0.28421283694220295102, + 0.27941549819892491646, 0.27461117408274476892, 0.26979998470151522749, 0.26498205033471977643, 0.26015749143046751346, 0.25532642860247933836, 0.25048898262707436357, 0.24564527444014955249, + 0.24079542513415819194, 0.23593955595507989931, 0.23107778829939124021, 0.22621024371102996242, 0.22133704387835811955, 0.21645831063111725667, 0.21157416593738448407, 0.20668473190052233379, + 0.20179013075612792227, 0.19689048486897448020, 0.19198591672995404811, 0.18707654895301459308, 0.18216250427209446094, 0.17724390553805557946, 0.17232087571560969486, 0.16739353788024594061, + 0.16246201521515318822, 0.15752643100814200938, 0.15258690864856014335, 0.14764357162420929659, 0.14269654351825716843, 0.13774594800614961554, 0.13279190885251615506, 0.12783454990807766039, + 0.12287399510654904711, 0.11791036846154288875, 0.11294379406346635730, 0.10797439607642073112, 0.10300229873509640643, 0.09802762634166883871, 0.09305050326268833605, 0.08807105392597264215, + 0.08308940281749539747, 0.07810567447827571064, 0.07311999350126208164, 0.06813248452821923928, 0.06314327224661175908, 0.05815248138648638349, 0.05316023671735556344, 0.04816666304507556673, + 0.04317188520872811824, 0.03817602807749854305, 0.03317921654755580374, 0.02818157553892746553, 0.02318322999237843948, 0.01818430486628662066, 0.01318492513352068594, 0.00818521577831312665, + 0.00318530179313742355, -0.00181469182441765112, -0.00681464007477118605, -0.01181441795947778088, -0.01681390048435072240, -0.02181296266258772251, -0.02681147951789380687, -0.03180932608760837083, + -0.03680637742582747868, -0.04180250860652838518, -0.04679759472669089287, -0.05179151090942261254, -0.05678413230707906462, -0.06177533410438534184, -0.06676499152155691841, -0.07175297981741735054, + -0.07673917429251948807, -0.08172345029226112112, -0.08670568321000234058, -0.09168574849017877004, -0.09666352163141823939, -0.10163887818965149090, -0.10661169378122412055, -0.11158184408600446691, + -0.11654920485049420631, -0.12151365189093295271, -0.12647506109640369032, -0.13143330843193384849, -0.13638826994159863881, -0.14133982175161846628, -0.14628784007345638218, -0.15123220120691119317, + -0.15617278154321248551, -0.16110945756810918228, -0.16604210586495821156, -0.17097060311780823416, -0.17589482611448500893, -0.18081465174967009668, -0.18572995702797928663, -0.19064061906703580473, + -0.19554651510054482655, -0.20044752248136102346, -0.20534351868455516521, -0.21023438131047758604, -0.21511998808781651604, -0.22000021687665741177, -0.22487494567153470948, -0.22974405260448288457, + -0.23460741594808134924, -0.23946491411850023834, -0.24431642567853828485, -0.24916182934065958521, -0.25400100397002411956, -0.25883382858751863287, -0.26366018237277932812, -0.26847994466721347706, + -0.27329299497701375898, -0.27809921297617368197, -0.28289847850949351171, -0.28769067159558531221, -0.29247567242987065894, -0.29725336138757835203, -0.30202361902673330318, -0.30678632609114336871, + -0.31154136351337924360, -0.31628861241775330093, -0.32102795412329032665, -0.32575927014669442405, -0.33048244220531186599, -0.33519735222008639752, -0.33990388231851365042, -0.34460191483758617625, + -0.34929133232673625908, -0.35397201755076995733, -0.35864385349280092363, -0.36330672335717389965, -0.36796051057238560178, -0.37260509879399711375, -0.37724037190754533544, -0.38186621403144377362, + -0.38648250951988066815, -0.39108914296570845837, -0.39568599920333130671, -0.40027296331158268572, -0.40484992061659924589, -0.40941675669468591270, -0.41397335737517892973, -0.41851960874329868778, + -0.42305539714299816856, -0.42758060917980272864, -0.43209513172364766298, -0.43659885191170438867, -0.44109165715120285389, -0.44557343512224645288, -0.45004407378061850320, -0.45450346136058583646, + -0.45895148637769117572, -0.46338803763154118309, -0.46781300420858479283, -0.47222627548488838034, -0.47662774112889999545, -0.48101729110420810009, -0.48539481567229114667, -0.48976020539526338160, + -0.49411335113860904711, -0.49845414407391169798, -0.50278247568157319325, -0.50709823775352924624, -0.51140132239595281760, -0.51569162203195229033, -0.51996902940425959727, -0.52423343757791340813, + -0.52848473994293165834, -0.53272283021697686145, -0.53694760244801220672, -0.54115895101695243863, -0.54535677064030252392, -0.54954095637279054554, -0.55371140360999160368, -0.55786800809094105880, + -0.56201066590074388873, -0.56613927347317050121, -0.57025372759324721716, -0.57435392539983431970, -0.57843976438820066122, -0.58251114241258428184, -0.58656795768874714359, -0.59061010879651776317, + -0.59463749468232940387, -0.59865001466174472267, -0.60264756842197342301, -0.60663005602437913844, -0.61059737790697954374, -0.61454943488693414277, -0.61848612816302472872, -0.62240735931812363191, + -0.62631303032165663858, -0.63020304353205203185, -0.63407730169918252727, -0.63793570796679510693, -0.64177816587493419220, -0.64560457936235238208, -0.64941485276891164347, -0.65320889083797573083, + -0.65698659871878983818, -0.66074788196885403391, -0.66449264655628281773, -0.66822079886215701716, -0.67193224568286247234, -0.67562689423242239251, -0.67930465214481527969, -0.68296542747628530279, + -0.68660912870763923799, -0.69023566474653630376, -0.69384494492976445112, -0.69743687902550732804, -0.70101137723559914239, -0.70456835019777108720, -0.70810770898788422123, -0.71162936512215357876, + -0.71513323055935862360, -0.71861921770304615364, -0.72208723940371910555, -0.72553720896101603355, -0.72896904012587693256, -0.73238264710270173374, -0.73577794455149403419, -0.73915484758999416837, + -0.74251327179580250970, -0.74585313320848811713, -0.74917434833169005426, -0.75247683413520316531, -0.75576050805705463631, -0.75902528800556723354, -0.76227109236141132875, -0.76549783997964904181, + -0.76870545019175651191, -0.77189384280764572477, -0.77506293811766757695, -0.77821265689460439319, -0.78134292039565123034, -0.78445365036438186035, -0.78754476903271153354, -0.79061619912283220835, + -0.79366786384915377628, -0.79669968692021542189, -0.79971159254059875909, -0.80270350541282020629, -0.80567535073921381361, -0.80862705422380165565, -0.81155854207414879209, -0.81446974100321378742, + -0.81736057823117291843, -0.82023098148724815637, -0.82308087901150606136, -0.82591019955665734287, -0.82871887238983588109, -0.83150682729436709018, -0.83427399457152406903, -0.83702030504226743179, + -0.83974569004898047542, -0.84245008145717859005, -0.84513341165721778125, -0.84779561356598298616, -0.85043662062856495432, -0.85305636681992524917, -0.85565478664654404106, -0.85823181514806290426, + -0.86078738789890174576, -0.86332144100987662227, -0.86583391112979046778, -0.86832473544702148960, -0.87079385169109158049, -0.87324119813422318437, -0.87566671359288317245, -0.87807033742931006604, + -0.88045200955303482004, -0.88281167042237718157, -0.88514926104593882883, -0.88746472298407563795, -0.88975799835036006868, -0.89202902981302722996, -0.89427776059640884387, -0.89650413448235288794, + -0.89870809581162691693, -0.90088958948531416837, -0.90304856096618524308, -0.90518495628006578890, -0.90729872201718442248, -0.90938980533350777247, -0.91145815395206175591, -0.91350371616423864385, + -0.91552644083109002704, -0.91752627738460390550, -0.91950317582897100888, -0.92145708674183313125, -0.92338796127551925341, -0.92529575115826656617, -0.92718040869542739379, -0.92904188677066168456, + -0.93088013884711362511, -0.93269511896857837385, -0.93448678176064647882, -0.93625508243184163426, -0.93799997677473923030, -0.93972142116707157999, -0.94141937257281860241, -0.94309378854328340669, + -0.94474462721815444244, -0.94637184732654988650, -0.94797540818805281493, -0.94955526971372439249, -0.95111139240710917964, -0.95264373736522078850, -0.95415226627951510441, -0.95563694143684785320, + -0.95709772572041729166, -0.95853458261069279800, -0.95994747618632647601, -0.96133637112505265776, -0.96270123270457030884, -0.96404202680341100073, -0.96535871990179211721, -0.96665127908245462862, + -0.96791967203148676635, -0.96916386703913015577, -0.97038383300057517999, -0.97157953941673580456, -0.97275095639501407696, -0.97389805465004641860, -0.97502080550443648299, -0.97611918088947113858, + -0.97719315334582312893, -0.97824269602423696846, -0.97926778268620007228, -0.98026838770459978623, -0.98124448606436232012, -0.98219605336307969079, -0.98312306581161901242, -0.98402550023471724305, + -0.98490333407156094303, -0.98575654537634993524, -0.98658511281884597732, -0.98738901568490611282, -0.98816823387700059023, -0.98892274791471512785, -0.98965253893523819073, -0.99035758869383216929, + -0.99103787956429001405, -0.99169339453937521700, -0.99232411723124747116, -0.99293003187187267589, -0.99351112331341595585, -0.99406737702862180139, -0.99459877911117622329, -0.99510531627605480764, + -0.99558697585985489464, -0.99604374582111188108, -0.99647561474060075692, -0.99688257182162054448, -0.99726460689026596995, -0.99762171039567981712, -0.99795387341029329065, -0.99826108763004817170, + -0.99854334537460498478, -0.99880063958753495523, -0.99903296383649597967, -0.99924031231339405235, -0.99942267983452803826, -0.99958006184071934719, -0.99971245439742595362, -0.99981985419484109556, + -0.99990225854797520899, -0.99995966539672387352, -0.99999207330591877163, -0.99999948146536388194, -0.99998188968985557423, -0.99993929841918749446, -0.99987170871813890738, -0.99977912227644905041, + -0.99966154140877416800, -0.99951896905462955800, -0.99935140877831696304, -0.99915886476883430944, -0.99894134183977201236, -0.99869884542919173942, -0.99843138159949140764, -0.99813895703725263875, + -0.99782157905307422574, -0.99747925558138939017, -0.99711199518026705224, -0.99671980703119800182, -0.99630270093886552640, -0.99586068733090049587, -0.99539377725761979399, -0.99490198239175109407, + -0.99438531502814031526, -0.99384378808344475686, -0.99327741509580969037, -0.99268621022453029656, -0.99207018824969783743, -0.99142936457182928578, -0.99076375521148341008, -0.99007337680885953990, + -0.98935824662338167634, -0.98861838253326717041, -0.98785380303507996924, -0.98706452724326754211, -0.98625057488968337349, -0.98541196632309446812, -0.98454872250867075945, -0.98366086502746297171, + -0.98274841607586183034, -0.98181139846504350555, -0.98084983562039951277, -0.97986375158095095905, -0.97885317099874735725, -0.97781811913825045224, -0.97675862187570339223, -0.97567470569848213646, + -0.97456639770443476145, -0.97343372560120344783, -0.97227671770553181219, -0.97109540294255680681, -0.96988981084508585351, -0.96865997155285932241, -0.96740591581179447012, -0.96612767497322027399, + -0.96482528099309083913, -0.96349876643118781416, -0.96214816445030626468, -0.96077350881542522565, -0.95937483389286415392, -0.95795217464942283847, -0.95650556665150909819, -0.95503504606424649559, + -0.95354064965057394598, -0.95202241477032367722, -0.95048037937928853136, -0.94891458202827316804, -0.94732506186212961374, -0.94571185861877926637, -0.94407501262821902355, -0.94241456481151386626, + -0.94073055667977245609, -0.93902303033311051994, -0.93729202845959747048, -0.93553759433419036995, -0.93375977181765068558, -0.93195860535544849945, -0.93013413997665261856, -0.92828642129280103390, + -0.92641549549676571740, -0.92452140936159377116, -0.92260421023933991691, -0.92066394605988222111, -0.91870066532972438633, -0.91671441713078216651, -0.91470525111915690353, -0.91267321752389507505, + -0.91061836714572963469, -0.90854075135581380263, -0.90644042209443387303, -0.90431743186971202952, -0.90217183375629328435, -0.90000368139401865086, -0.89781302898658432721, -0.89559993130018611396, + -0.89336444366215139734, -0.89110662195955459008, -0.88882652263782058188, -0.88652420269931364594, -0.88419971970191224564, -0.88185313175757040760, -0.87948449753086399561, -0.87709387623752654850, + -0.87468132764296424586, -0.87224691206076765404, -0.86979069035119904729, -0.86731272391967317859, -0.86481307471522173014, -0.86229180522894477434, -0.85974897849244813486, -0.85718465807626731401, + -0.85459890808828042896, -0.85199179317210071982, -0.84936337850546672623, -0.84671372979860781705, -0.84404291329260350274, -0.84135099575772742675, -0.83863804449177770106, -0.83590412731839469629, + -0.83314931258536495395, -0.83037366916291421859, -0.82757726644198292831, -0.82476017433249360078, -0.82192246326160212089, -0.81906420417193759320, -0.81618546851982831658, -0.81328632827351565737, + -0.81036685591135471096, -0.80742712442000219575, -0.80446720729259302285, -0.80148717852690087859, -0.79848711262348970319, -0.79546708458385073648, -0.79242716990852768433, -0.78936744459522911743, + -0.78628798513692810257, -0.78318886851995150877, -0.78007017222205310425, -0.77693197421047766049, -0.77377435294001228883, -0.77059738735102401019, -0.76740115686748722190, -0.76418574139499750864, + -0.76095122131877424021, -0.75769767750165029074, -0.75442519128205276502, -0.75113384447196607230, -0.74782371935488911596, -0.74449489868377749513, -0.74114746567897449303, -0.73778150402613085213, + -0.73439709787411278086, -0.73099433183289752591, -0.72757329097145850838, -0.72413406081564013483, -0.72067672734601673223, -0.71720137699574493251, -0.71370809664840229036, -0.71019697363581579808, + -0.70666809573587785476, -0.70312155117035146645, -0.69955742860266734162, -0.69597581713570333406, -0.69237680630955966699, -0.68876048609931961320, -0.68512694691279985015, -0.68147627958829104511, + -0.67780857539228600572, -0.67412392601719872687, -0.67042242357907078087, -0.66670416061527193463, -0.66296923008218189288, -0.65921772535286937700, -0.65544974021475732595, -0.65166536886727777222, + -0.64786470591951750286, -0.64404784638785206319, -0.64021488569357121179, -0.63636591966049171898, -0.63250104451256550231, -0.62862035687146911034, -0.62472395375419165209, -0.62081193257060796054, + -0.61688439112104398454, -0.61294142759383130059, -0.60898314056285207663, -0.60500962898507726351, -0.60102099219808879926, -0.59701732991759859370, -0.59299874223495496750, -0.58896532961464087563, + -0.58491719289176158370, -0.58085443326952446164, -0.57677715231670834140, -0.57268545196512410378, -0.56857943450706882604, -0.56445920259276427533, -0.56032485922779384779, -0.55617650777052629607, + -0.55201425192953201826, -0.54783819576099013204, -0.54364844366608755521, -0.53944510038840820521, -0.53522827101131453809, -0.53099806095532275929, -0.52675457597546326838, -0.52249792215863943845, + -0.51822820592097507131, -0.51394553400515374797, -0.50965001347775029661, -0.50534175172655326769, -0.50102085645788385637, -0.49668743569389767201, -0.49234159776988828394, -0.48798345133157744469, + -0.48361310533239909581, -0.47923066903077560230, -0.47483625198738627082, -0.47042996406242826302, -0.46601191541286945963, -0.46158221648969754991, -0.45714097803515413299, -0.45268831107996920782, + -0.44822432694058478297, -0.44374913721637188058, -0.43926285378684049032, -0.43476558880884264013, -0.43025745471376780626, -0.42573856420473515927, -0.42120903025377121054, -0.41666896609898895765, + -0.41211848524175564989, -0.40755770144385583542, -0.40298672872464680328, -0.39840568135820858542, -0.39381467387048585405, -0.38921382103642837569, -0.38460323787711647725, -0.37998303965688906558, + -0.37535334188046098891, -0.37071426029003556879, -0.36606591086241091482, -0.36140840980608057720, -0.35674187355832848167, -0.35206641878231687004, -0.34738216236417329696, -0.34268922141006341597, + -0.33798771324326665200, -0.33327775540124238152, -0.32855946563269122773, -0.32383296189461174830, -0.31909836234935112786, -0.31435578536165070807, -0.30960534949568974117, -0.30484717351211659819, + -0.30008137636508314117, -0.29530807719926976951, -0.29052739534690708023, -0.28573945032479231010, -0.28094436183130161444, -0.27614224974339685037, -0.27133323411363174937, -0.26651743516714571092, + -0.26169497329866164836, -0.25686596906947500862, -0.25203054320444007175, -0.24718881658895158759, -0.24234091026592280427, -0.23748694543275927771, -0.23262704343832818488, -0.22776132577992797001, + -0.22288991410024580619, -0.21801293018431996962, -0.21313049595649438683, -0.20824273347737040640, -0.20334976494075546194, -0.19845171267060812692, -0.19354869911797917270, -0.18864084685795379226, + -0.18372827858658200006, -0.17881111711781472184, -0.17388948538043255687, -0.16896350641497262512, -0.16403330337065250011, -0.15909899950229147714, -0.15416071816722845544, -0.14921858282224129133, + -0.14427271702045540991, -0.13932324440825819001, -0.13437028872220715958, -0.12941397378593655354, -0.12445442350706158174, -0.11949176187408093452, -0.11452611295327697061, -0.10955760088561317112, + -0.10458634988363424423, -0.09961248422835543292, -0.09463612826615905305, -0.08965740640568498065, -0.08467644311472041774, -0.07969336291708821463, -0.07470829038953377688, -0.06972135015860976559, + -0.06473266689756400349, -0.05974236532321727799, -0.05475057019284905457, -0.04975740630107760437, -0.04476299847674015953, -0.03976747157977219421, -0.03477095049808595628, -0.02977356014444736479, + -0.02477542545335675514, -0.01977667137792019775, -0.01477742288672922490, -0.00977780496073574201, +}; + + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_example_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_example_f32.c new file mode 100644 index 00000000..f8120842 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_example_f32.c @@ -0,0 +1,208 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2020 ARM Limited. All rights reserved. +* +* $Date: 23. March 2020 +* $Revision: V1.7.0 +* +* Project: CMSIS DSP Library +* Title: arm_linear_interp_example_f32.c +* +* Description: Example code demonstrating usage of sin function +* and uses linear interpolation to get higher precision +* +* Target Processor: Cortex-M55/Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup LinearInterpExample Linear Interpolate Example + * + * CMSIS DSP Software Library -- Linear Interpolate Example + * + * Description + * This example demonstrates usage of linear interpolate modules and fast math modules. + * Method 1 uses fast math sine function to calculate sine values using cubic interpolation and method 2 uses + * linear interpolation function and results are compared to reference output. + * Example shows linear interpolation function can be used to get higher precision compared to fast math sin calculation. + * + * \par Block Diagram: + * \par + * \image html linearInterpExampleMethod1.gif "Method 1: Sine caluclation using fast math" + * \par + * \image html linearInterpExampleMethod2.gif "Method 2: Sine caluclation using interpolation function" + * + * \par Variables Description: + * \par + * \li \c testInputSin_f32 points to the input values for sine calculation + * \li \c testRefSinOutput32_f32 points to the reference values caculated from sin() matlab function + * \li \c testOutput points to output buffer calculation from cubic interpolation + * \li \c testLinIntOutput points to output buffer calculation from linear interpolation + * \li \c snr1 Signal to noise ratio for reference and cubic interpolation output + * \li \c snr2 Signal to noise ratio for reference and linear interpolation output + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_sin_f32() + * - arm_linear_interp_f32() + * + * Refer + * \link arm_linear_interp_example_f32.c \endlink + * + */ + + +/** \example arm_linear_interp_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +#if defined(SEMIHOSTING) +#include +#endif + +#define SNR_THRESHOLD 90 +#define TEST_LENGTH_SAMPLES 10 +#define XSPACING (0.005f) + +/* ---------------------------------------------------------------------- +* Test input data for F32 SIN function +* Generated by the MATLAB rand() function +* randn('state', 0) +* xi = (((1/4.18318581819710)* randn(blockSize, 1) * 2* pi)); +* --------------------------------------------------------------------*/ +float32_t testInputSin_f32[TEST_LENGTH_SAMPLES] = +{ + -0.649716504673081170, -2.501723745497831200, + 0.188250329003310100, 0.432092748487532540, + -1.722010988459680800, 1.788766476323060600, + 1.786136060975809500, -0.056525543169408797, + 0.491596272728153760, 0.262309671126153390 +}; + +/*------------------------------------------------------------------------------ +* Reference out of SIN F32 function for Block Size = 10 +* Calculated from sin(testInputSin_f32) +*------------------------------------------------------------------------------*/ +float32_t testRefSinOutput32_f32[TEST_LENGTH_SAMPLES] = +{ + -0.604960695383043530, -0.597090287967934840, + 0.187140422442966500, 0.418772124875992690, + -0.988588831792106880, 0.976338412038794010, + 0.976903856413481100, -0.056495446835214236, + 0.472033731854734240, 0.259311907228582830 +}; + +/*------------------------------------------------------------------------------ +* Method 1: Test out Buffer Calculated from Cubic Interpolation +*------------------------------------------------------------------------------*/ +float32_t testOutput[TEST_LENGTH_SAMPLES]; + +/*------------------------------------------------------------------------------ +* Method 2: Test out buffer Calculated from Linear Interpolation +*------------------------------------------------------------------------------*/ +float32_t testLinIntOutput[TEST_LENGTH_SAMPLES]; + +/*------------------------------------------------------------------------------ +* External table used for linear interpolation +*------------------------------------------------------------------------------*/ +extern const float arm_linear_interep_table[1884]; + +/* ---------------------------------------------------------------------- +* Global Variables for caluclating SNR's for Method1 & Method 2 +* ------------------------------------------------------------------- */ +float32_t snr1; +float32_t snr2; + +/* ---------------------------------------------------------------------------- +* Calculation of Sine values from Cubic Interpolation and Linear interpolation +* ---------------------------------------------------------------------------- */ +int32_t main(void) +{ + uint32_t i; + arm_status status; + + arm_linear_interp_instance_f32 S = {1884, -3.141592653589793238, XSPACING, (float*)&arm_linear_interep_table[0]}; + + /*------------------------------------------------------------------------------ + * Method 1: Test out Calculated from Cubic Interpolation + *------------------------------------------------------------------------------*/ + for(i=0; i< TEST_LENGTH_SAMPLES; i++) + { + testOutput[i] = arm_sin_f32(testInputSin_f32[i]); + } + + /*------------------------------------------------------------------------------ + * Method 2: Test out Calculated from Cubic Interpolation and Linear interpolation + *------------------------------------------------------------------------------*/ + + for(i=0; i< TEST_LENGTH_SAMPLES; i++) + { + testLinIntOutput[i] = arm_linear_interp_f32(&S, testInputSin_f32[i]); + } + + /*------------------------------------------------------------------------------ + * SNR calculation for method 1 + *------------------------------------------------------------------------------*/ + snr1 = arm_snr_f32(testRefSinOutput32_f32, testOutput, 2); + + /*------------------------------------------------------------------------------ + * SNR calculation for method 2 + *------------------------------------------------------------------------------*/ + snr2 = arm_snr_f32(testRefSinOutput32_f32, testLinIntOutput, 2); + + /*------------------------------------------------------------------------------ + * Initialise status depending on SNR calculations + *------------------------------------------------------------------------------*/ + status = (snr2 <= snr1) ? ARM_MATH_TEST_FAILURE : ARM_MATH_SUCCESS; + + if (status != ARM_MATH_SUCCESS) + { +#if defined (SEMIHOSTING) + printf("FAILURE\n"); +#else + while (1); /* main function does not return */ +#endif + } + else + { +#if defined (SEMIHOSTING) + printf("SUCCESS\n"); +#else + while (1); /* main function does not return */ +#endif + } + +} + + /** \endlink */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.c new file mode 100644 index 00000000..fce27d25 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.c @@ -0,0 +1,472 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/* + +Conflicting with the new clip functions in CMSIS-DSP and not used +in the examples. + +*/ +#if 0 +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + +#endif diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.h b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.h new file mode 100644 index 00000000..a0dbdf73 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM0_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM0_config.txt new file mode 100644 index 00000000..13dc7839 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM3_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM3_config.txt new file mode 100644 index 00000000..55419ac8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM4_FP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM4_FP_config.txt new file mode 100644 index 00000000..fb9d24c9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM55_FP_MVE_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 00000000..4a65b1de --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM7_SP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM7_SP_config.txt new file mode 100644 index 00000000..82fc00c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt new file mode 100644 index 00000000..a4cf1aa0 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_matrix_example. + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/CMakeLists.txt new file mode 100644 index 00000000..0b269426 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_matrix_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_matrix_example) + + +include(config) +configApp(arm_matrix_example ${ROOT}) + +target_sources(arm_matrix_example PRIVATE math_helper.c arm_matrix_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_matrix_example PRIVATE CMSISDSP) + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 00000000..f527fa11 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/system_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 00000000..66a364c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 00000000..0392a899 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/system_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 00000000..3c5eda7d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 00000000..90eee9dc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 00000000..9d983d2e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 00000000..0ab7e3e9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM55/system_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 00000000..b76ebb7c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 00000000..78584996 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 00000000..75f9c18e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c new file mode 100644 index 00000000..c292610a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c @@ -0,0 +1,235 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_matrix_example_f32.c +* +* Description: Example code demonstrating least square fit to data +* using matrix functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup MatrixExample Matrix Example + * + * \par Description: + * \par + * Demonstrates the use of Matrix Transpose, Matrix Muliplication, and Matrix Inverse + * functions to apply least squares fitting to input data. Least squares fitting is + * the procedure for finding the best-fitting curve that minimizes the sum of the + * squares of the offsets (least square error) from a given set of data. + * + * \par Algorithm: + * \par + * The linear combination of parameters considered is as follows: + * \par + * A * X = B, where \c X is the unknown value and can be estimated + * from \c A & \c B. + * \par + * The least squares estimate \c X is given by the following equation: + * \par + * X = Inverse(AT * A) * AT * B + * + * \par Block Diagram: + * \par + * + * \par Variables Description: + * \par + * \li \c A_f32 input matrix in the linear combination equation + * \li \c B_f32 output matrix in the linear combination equation + * \li \c X_f32 unknown matrix estimated using \c A_f32 & \c B_f32 matrices + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_mat_init_f32() + * - arm_mat_trans_f32() + * - arm_mat_mult_f32() + * - arm_mat_inverse_f32() + * + * Refer + * \link arm_matrix_example_f32.c \endlink + * + */ + + +/** \example arm_matrix_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +#if defined(SEMIHOSTING) +#include +#endif + +#define SNR_THRESHOLD 90 + +/* -------------------------------------------------------------------------------- +* Test input data(Cycles) taken from FIR Q15 module for differant cases of blockSize +* and tapSize +* --------------------------------------------------------------------------------- */ + +const float32_t B_f32[4] = +{ + 782.0, 7577.0, 470.0, 4505.0 +}; + +/* -------------------------------------------------------------------------------- +* Formula to fit is C1 + C2 * numTaps + C3 * blockSize + C4 * numTaps * blockSize +* -------------------------------------------------------------------------------- */ + +const float32_t A_f32[16] = +{ + /* Const, numTaps, blockSize, numTaps*blockSize */ + 1.0, 32.0, 4.0, 128.0, + 1.0, 32.0, 64.0, 2048.0, + 1.0, 16.0, 4.0, 64.0, + 1.0, 16.0, 64.0, 1024.0, +}; + + +/* ---------------------------------------------------------------------- +* Temporary buffers for storing intermediate values +* ------------------------------------------------------------------- */ +/* Transpose of A Buffer */ +float32_t AT_f32[16]; +/* (Transpose of A * A) Buffer */ +float32_t ATMA_f32[16]; +/* Inverse(Transpose of A * A) Buffer */ +float32_t ATMAI_f32[16]; +/* Test Output Buffer */ +float32_t X_f32[4]; + +/* ---------------------------------------------------------------------- +* Reference ouput buffer C1, C2, C3 and C4 taken from MATLAB +* ------------------------------------------------------------------- */ +const float32_t xRef_f32[4] = {73.0, 8.0, 21.25, 2.875}; + +float32_t snr; + + +/* ---------------------------------------------------------------------- +* Max magnitude FFT Bin test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + + arm_matrix_instance_f32 A; /* Matrix A Instance */ + arm_matrix_instance_f32 AT; /* Matrix AT(A transpose) instance */ + arm_matrix_instance_f32 ATMA; /* Matrix ATMA( AT multiply with A) instance */ + arm_matrix_instance_f32 ATMAI; /* Matrix ATMAI(Inverse of ATMA) instance */ + arm_matrix_instance_f32 B; /* Matrix B instance */ + arm_matrix_instance_f32 X; /* Matrix X(Unknown Matrix) instance */ + + uint32_t srcRows, srcColumns; /* Temporary variables */ + arm_status status; + + /* Initialise A Matrix Instance with numRows, numCols and data array(A_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&A, srcRows, srcColumns, (float32_t *)A_f32); + + /* Initialise Matrix Instance AT with numRows, numCols and data array(AT_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&AT, srcRows, srcColumns, AT_f32); + + /* calculation of A transpose */ + status = arm_mat_trans_f32(&A, &AT); + + + /* Initialise ATMA Matrix Instance with numRows, numCols and data array(ATMA_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&ATMA, srcRows, srcColumns, ATMA_f32); + + /* calculation of AT Multiply with A */ + status = arm_mat_mult_f32(&AT, &A, &ATMA); + + /* Initialise ATMAI Matrix Instance with numRows, numCols and data array(ATMAI_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&ATMAI, srcRows, srcColumns, ATMAI_f32); + + /* calculation of Inverse((Transpose(A) * A) */ + status = arm_mat_inverse_f32(&ATMA, &ATMAI); + + /* calculation of (Inverse((Transpose(A) * A)) * Transpose(A)) */ + status = arm_mat_mult_f32(&ATMAI, &AT, &ATMA); + + /* Initialise B Matrix Instance with numRows, numCols and data array(B_f32) */ + srcRows = 4; + srcColumns = 1; + arm_mat_init_f32(&B, srcRows, srcColumns, (float32_t *)B_f32); + + /* Initialise X Matrix Instance with numRows, numCols and data array(X_f32) */ + srcRows = 4; + srcColumns = 1; + arm_mat_init_f32(&X, srcRows, srcColumns, X_f32); + + /* calculation ((Inverse((Transpose(A) * A)) * Transpose(A)) * B) */ + status = arm_mat_mult_f32(&ATMA, &B, &X); + + /* Comparison of reference with test output */ + snr = arm_snr_f32((float32_t *)xRef_f32, X_f32, 4); + + /*------------------------------------------------------------------------------ + * Initialise status depending on SNR calculations + *------------------------------------------------------------------------------*/ + status = (snr < SNR_THRESHOLD) ? ARM_MATH_TEST_FAILURE : ARM_MATH_SUCCESS; + + if (status != ARM_MATH_SUCCESS) + { +#if defined (SEMIHOSTING) + printf("FAILURE\n"); +#else + while (1); /* main function does not return */ +#endif + } + else + { +#if defined (SEMIHOSTING) + printf("SUCCESS\n"); +#else + while (1); /* main function does not return */ +#endif + } + +} + + /** \endlink */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c new file mode 100644 index 00000000..f62043d6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c @@ -0,0 +1,473 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/* + +Conflicting with the new clip functions in CMSIS-DSP and not used +in the examples. + +*/ +#if 0 +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} +#endif + + + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h new file mode 100644 index 00000000..a0dbdf73 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM0_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM0_config.txt new file mode 100644 index 00000000..13dc7839 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM3_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM3_config.txt new file mode 100644 index 00000000..55419ac8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM4_FP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM4_FP_config.txt new file mode 100644 index 00000000..fb9d24c9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM55_FP_MVE_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 00000000..4a65b1de --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM7_SP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM7_SP_config.txt new file mode 100644 index 00000000..82fc00c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/Abstract.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/Abstract.txt new file mode 100644 index 00000000..1180b892 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_signal_converge_example. + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/CMakeLists.txt new file mode 100644 index 00000000..e516758f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_signal_convergence_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_signal_convergence_example) + + +include(config) +configApp(arm_signal_convergence_example ${ROOT}) + +target_sources(arm_signal_convergence_example PRIVATE math_helper.c arm_signal_converge_data.c arm_signal_converge_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_signal_convergence_example PRIVATE CMSISDSP) + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 00000000..f527fa11 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/system_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 00000000..66a364c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 00000000..0392a899 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/system_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 00000000..3c5eda7d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 00000000..90eee9dc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 00000000..9d983d2e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 00000000..0ab7e3e9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM55/system_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 00000000..b76ebb7c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 00000000..78584996 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 00000000..75f9c18e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.c new file mode 100644 index 00000000..ddb1278e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.c @@ -0,0 +1,269 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_signal_converge_data.c +* +* Description: Test input data for Floating point LMS Norm FIR filter +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +** Test input data for Floating point LMS Norm FIR filter +** Generated by the MATLAB randn() function +** ------------------------------------------------------------------- */ + +float32_t testInput_f32[1536] = +{ +-0.432565, -1.665584, 0.125332, 0.287676, -1.146471, 1.190915, 1.189164, -0.037633, +0.327292, 0.174639, -0.186709, 0.725791, -0.588317, 2.183186, -0.136396, 0.113931, +1.066768, 0.059281, -0.095648, -0.832349, 0.294411, -1.336182, 0.714325, 1.623562, +-0.691776, 0.857997, 1.254001, -1.593730, -1.440964, 0.571148, -0.399886, 0.689997, +0.815622, 0.711908, 1.290250, 0.668601, 1.190838, -1.202457, -0.019790, -0.156717, +-1.604086, 0.257304, -1.056473, 1.415141, -0.805090, 0.528743, 0.219321, -0.921902, +-2.170674, -0.059188, -1.010634, 0.614463, 0.507741, 1.692430, 0.591283, -0.643595, +0.380337, -1.009116, -0.019511, -0.048221, 0.000043, -0.317859, 1.095004, -1.873990, +0.428183, 0.895638, 0.730957, 0.577857, 0.040314, 0.677089, 0.568900, -0.255645, +-0.377469, -0.295887, -1.475135, -0.234004, 0.118445, 0.314809, 1.443508, -0.350975, +0.623234, 0.799049, 0.940890, -0.992092, 0.212035, 0.237882, -1.007763, -0.742045, +1.082295, -0.131500, 0.389880, 0.087987, -0.635465, -0.559573, 0.443653, -0.949904, +0.781182, 0.568961, -0.821714, -0.265607, -1.187777, -2.202321, 0.986337, -0.518635, +0.327368, 0.234057, 0.021466, -1.003944, -0.947146, -0.374429, -1.185886, -1.055903, +1.472480, 0.055744, -1.217317, -0.041227, -1.128344, -1.349278, -0.261102, 0.953465, +0.128644, 0.656468, -1.167819, -0.460605, -0.262440, -1.213152, -1.319437, 0.931218, +0.011245, -0.645146, 0.805729, 0.231626, -0.989760, 1.339586, 0.289502, 1.478917, +1.138028, -0.684139, -1.291936, -0.072926, -0.330599, -0.843628, 0.497770, 1.488490, +-0.546476, -0.846758, -0.246337, 0.663024, -0.854197, -1.201315, -0.119869, -0.065294, +0.485296, -0.595491, -0.149668, -0.434752, -0.079330, 1.535152, -0.606483, -1.347363, +0.469383, -0.903567, 0.035880, -0.627531, 0.535398, 0.552884, -0.203690, -2.054325, +0.132561, 1.592941, 1.018412, -1.580402, -0.078662, -0.681657, -1.024553, -1.234353, +0.288807, -0.429303, 0.055801, -0.367874, -0.464973, 0.370961, 0.728283, 2.112160, +-1.357298, -1.022610, 1.037834, -0.389800, -1.381266, 0.315543, 1.553243, 0.707894, +1.957385, 0.504542, 1.864529, -0.339812, -1.139779, -0.211123, 1.190245, -1.116209, +0.635274, -0.601412, 0.551185, -1.099840, 0.085991, -2.004563, -0.493088, 0.462048, +-0.321005, 1.236556, -0.631280, -2.325211, -1.231637, 1.055648, -0.113224, 0.379224, +0.944200, -2.120427, -0.644679, -0.704302, -1.018137, -0.182082, 1.521013, -0.038439, +1.227448, -0.696205, 0.007524, -0.782893, 0.586939, -0.251207, 0.480136, 0.668155, +-0.078321, 0.889173, 2.309287, 0.524639, -0.011787, 0.913141, 0.055941, -1.107070, +0.485498, -0.005005, -0.276218, 1.276452, 1.863401, -0.522559, 0.103424, -0.807649, +0.680439, -2.364590, 0.990115, 0.218899, 0.261662, 1.213444, -0.274667, -0.133134, +-1.270500, -1.663606, -0.703554, 0.280880, -0.541209, -1.333531, 1.072686, -0.712085, +-0.011286, -0.000817, -0.249436, 0.396575, -0.264013, -1.664011, -1.028975, 0.243095, +-1.256590, -0.347183, -0.941372, -1.174560, -1.021142, -0.401667, 0.173666, -0.116118, +1.064119, -0.245386, -1.517539, 0.009734, 0.071373, 0.316536, 0.499826, 1.278084, +-0.547816, 0.260808, -0.013177, -0.580264, 2.136308, -0.257617, -1.409528, 1.770101, +0.325546, -1.119040, 0.620350, 1.269782, -0.896043, 0.135175, -0.139040, -1.163395, +1.183720, -0.015430, 0.536219, -0.716429, -0.655559, 0.314363, 0.106814, 1.848216, +-0.275106, 2.212554, 1.508526, -1.945079, -1.680543, -0.573534, -0.185817, 0.008934, +0.836950, -0.722271, -0.721490, -0.201181, -0.020464, 0.278890, 1.058295, 0.621673, +-1.750615, 0.697348, 0.811486, 0.636345, 1.310080, 0.327098, -0.672993, -0.149327, +-2.449018, 0.473286, 0.116946, -0.591104, -0.654708, -1.080662, -0.047731, 0.379345, +-0.330361, -0.499898, -0.035979, -0.174760, -0.957265, 1.292548, 0.440910, 1.280941, +-0.497730, -1.118717, 0.807650, 0.041200, -0.756209, -0.089129, -2.008850, 1.083918, +-0.981191, -0.688489, 1.339479, -0.909243, -0.412858, -0.506163, 1.619748, 0.080901, +-1.081056, -1.124518, 1.735676, 1.937459, 1.635068, -1.255940, -0.213538, -0.198932, +0.307499, -0.572325, -0.977648, -0.446809, 1.082092, 2.372648, 0.229288, -0.266623, +0.701672, -0.487590, 1.862480, 1.106851, -1.227566, -0.669885, 1.340929, 0.388083, +0.393059, -1.707334, 0.227859, 0.685633, -0.636790, -1.002606, -0.185621, -1.054033, +-0.071539, 0.279198, 1.373275, 0.179841, -0.542017, 1.634191, 0.825215, 0.230761, +0.671634, -0.508078, 0.856352, 0.268503, 0.624975, -1.047338, 1.535670, 0.434426, +-1.917136, 0.469940, 1.274351, 0.638542, 1.380782, 1.319843, -0.909429, -2.305605, +1.788730, 0.390798, 0.020324, -0.405977, -1.534895, 0.221373, -1.374479, -0.839286, +-0.208643, 0.755913, 0.375734, -1.345413, 1.481876, 0.032736, 1.870453, -1.208991, +-0.782632, -0.767299, -0.107200, -0.977057, -0.963988, -2.379172, -0.838188, 0.257346, +-0.183834, -0.167615, -0.116989, 0.168488, -0.501206, -0.705076, 0.508165, -0.420922, +0.229133, -0.959497, -0.146043, 0.744538, -0.890496, 0.139062, -0.236144, -0.075459, +-0.358572, -2.077635, -0.143546, 1.393341, 0.651804, -0.377134, -0.661443, 0.248958, +-0.383516, -0.528480, 0.055388, 1.253769, -2.520004, 0.584856, -1.008064, 0.944285, +-2.423957, -0.223831, 0.058070, -0.424614, -0.202918, -1.513077, -1.126352, -0.815002, +0.366614, -0.586107, 1.537409, 0.140072, -1.862767, -0.454193, -0.652074, 0.103318, +-0.220632, -0.279043, -0.733662, -0.064534, -1.444004, 0.612340, -1.323503, -0.661577, +-0.146115, 0.248085, -0.076633, 1.738170, 1.621972, 0.626436, 0.091814, -0.807607, +-0.461337, -1.405969, -0.374530, -0.470911, 1.751296, 0.753225, 0.064989, -0.292764, +0.082823, 0.766191, 2.236850, 0.326887, 0.863304, 0.679387, 0.554758, 1.001630, +1.259365, 0.044151, -0.314138, 0.226708, 0.996692, 1.215912, -0.542702, 0.912228, +-0.172141, -0.335955, 0.541487, 0.932111, -0.570253, -1.498605, -0.050346, 0.553025, +0.083498, 1.577524, -0.330774, 0.795155, -0.784800, -1.263121, 0.666655, -1.392632, +-1.300562, -0.605022, -1.488565, 0.558543, -0.277354, -1.293685, -0.888435, -0.986520, +-0.071618, -2.414591, -0.694349, -1.391389, 0.329648, 0.598544, 0.147175, -0.101439, +-2.634981, 0.028053, -0.876310, -0.265477, -0.327578, -1.158247, 0.580053, 0.239756, +-0.350885, 0.892098, 1.578299, -1.108174, -0.025931, -1.110628, 0.750834, 0.500167, +-0.517261, -0.559209, -0.753371, 0.925813, -0.248520, -0.149835, -1.258415, 0.312620, +2.690277, 0.289696, -1.422803, 0.246786, -1.435773, 0.148573, -1.693073, 0.719188, +1.141773, 1.551936, 1.383630, -0.758092, 0.442663, 0.911098, -1.074086, 0.201762, +0.762863, -1.288187, -0.952962, 0.778175, -0.006331, 0.524487, 1.364272, 0.482039, +-0.787066, 0.751999, -0.166888, -0.816228, 2.094065, 0.080153, -0.937295, 0.635739, +1.682028, 0.593634, 0.790153, 0.105254, -0.158579, 0.870907, -0.194759, 0.075474, +-0.526635, -0.685484, -0.268388, -1.188346, 0.248579, 0.102452, -0.041007, -2.247582, +-0.510776, 0.249243, 0.369197, 0.179197, -0.037283, -1.603310, 0.339372, -0.131135, +0.485190, 0.598751, -0.086031, 0.325292, -0.335143, -0.322449, -0.382374, -0.953371, +0.233576, 1.235245, -0.578532, -0.501537, 0.722864, 0.039498, 1.541279, -1.701053, +-1.033741, -0.763708, 2.176426, 0.431612, -0.443765, 0.029996, -0.315671, 0.977846, +0.018295, 0.817963, 0.702341, -0.231271, -0.113690, 0.127941, -0.799410, -0.238612, +-0.089463, -1.023264, 0.937538, -1.131719, -0.710702, -1.169501, 1.065437, -0.680394, +-1.725773, 0.813200, 1.441867, 0.672272, 0.138665, -0.859534, -0.752251, 1.229615, +1.150754, -0.608025, 0.806158, 0.217133, -0.373461, -0.832030, 0.286866, -1.818892, +-1.573051, 2.015666, -0.071982, 2.628909, -0.243317, 0.173276, 0.923207, -0.178553, +-0.521705, 1.431962, -0.870117, 0.807542, -0.510635, 0.743514, 0.847898, -0.829901, +0.532994, 1.032848, -1.052024, 0.362114, -0.036787, -1.227636, -0.275099, -0.160435, +-1.083575, -1.954213, -0.909487, -0.005579, -1.723490, 1.263077, -0.600433, -2.063925, +0.110911, 1.487614, 0.053002, 0.161981, -0.026878, 0.173576, 0.882168, 0.182294, +0.755295, 0.508035, 0.131880, 0.280104, -0.982848, -0.944087, -0.013058, 0.354345, +-0.894709, 0.812111, 0.109537, 2.731644, 0.411079, -1.306862, 0.383806, 0.499504, +-0.510786, 0.234922, -0.597825, 0.020771, 0.419443, 1.191104, 0.771214, -2.644222, +0.285430, 0.826093, -0.008122, 0.858438, 0.774788, 1.305945, 1.231503, 0.958564, +-1.654548, -0.990396, 0.685236, -0.974870, -0.606726, 0.686794, 0.020049, 1.063801, +-1.341050, 0.479510, -1.633974, -1.442665, 0.293781, -0.140364, -1.130341, -0.292538, +-0.582536, -0.896348, 0.248601, -1.489663, 0.313509, -2.025084, 0.528990, 0.343471, +0.758193, -0.691940, 0.680179, -1.072541, 0.899772, -2.123092, 0.284712, -0.733323, +-0.773376, 0.151842, -0.336843, 0.970761, -0.107236, 1.013492, -0.475347, 0.068948, +0.398592, 1.116326, 0.620451, -0.287674, -1.371773, -0.685868, 0.331685, -0.997722, +0.291418, 1.107078, 0.244959, 0.164976, 0.406231, 1.215981, 1.448424, -1.025137, +0.205418, 0.588882, -0.264024, 2.495318, 0.855948, -0.850954, 0.811879, 0.700242, +0.759938, -1.712909, 1.537021, -1.609847, 1.109526, -1.109704, 0.385469, 0.965231, +0.818297, 0.037049, -0.926012, -0.111919, -0.803030, -1.665006, -0.901401, 0.588350, +0.554159, -0.415173, 0.061795, 0.457432, 0.199014, 0.257558, 2.080730, -2.277237, +0.339022, 0.289894, 0.662261, -0.580860, 0.887752, 0.171871, 0.848821, 0.963769, +1.321918, -0.064345, 1.317053, 0.228017, -1.429637, -0.149701, -0.504968, -1.729141, +-0.417472, -0.614969, 0.720777, 0.339364, 0.882845, 0.284245, -0.145541, -0.089646, +0.289161, 1.164831, 0.805729, -1.355643, 0.120893, -0.222178, 0.571732, -0.300140, +1.134277, -0.179356, -1.467067, 1.395346, 0.440836, 0.565384, -0.693623, 0.833869, +-2.237378, 1.097644, -0.001617, -1.614573, -1.228727, 0.207405, 0.220942, -1.006073, +-0.453067, 1.399453, -0.461964, 0.032716, 0.798783, 0.896816, 0.137892, -1.619146, +-1.646606, 0.428707, -0.737231, 0.564926, -1.384167, 0.460268, 0.629384, 0.379847, +-1.013330, -0.347243, 0.441912, -1.590240, -0.701417, -1.077601, 1.002220, 1.729481, +0.709032, -0.747897, 0.228862, -0.223497, -0.853275, 0.345627, 0.109764, -1.133039, +-0.683124, -0.277856, 0.654790, -1.248394, -0.597539, -0.481813, 0.983372, 1.762121, +1.427402, 0.911763, 0.326823, 0.069619, -1.499763, -0.418223, -0.021037, 0.228425, +-1.008196, -0.664622, 0.558177, -1.188542, -0.775481, 0.271042, 1.534976, -1.052283, +0.625559, -0.797626, -0.313522, -0.602210, 1.259060, 0.858484, -2.105292, -0.360937, +0.553557, -1.556384, -0.206666, -0.425568, 0.493778, -0.870908, 0.079828, -0.521619, +-1.413861, -0.384293, -0.457922, -0.291471, -0.301224, -1.588594, 1.094287, 1.324167, +-0.126480, -0.737164, 0.213719, -0.400529, 0.064938, -1.757996, 1.686748, 0.327400, +0.715967, 1.598648, -2.064741, -0.743632, 0.176185, 0.527839, -0.553153, 0.298280, +-1.226607, -0.189676, -0.301713, 0.956956, -0.533366, -0.901082, -0.892552, 0.278717, +-0.745807, 1.603464, 0.574270, 0.320655, -0.151383, 0.315762, 1.343703, -2.237832, +1.292906, -0.378459, 0.002521, 0.884641, 0.582450, -1.614244, -1.503666, 0.573586, +-0.910537, -1.631277, -0.359138, -0.397616, -1.161307, -1.109838, 0.290672, -1.910239, +1.314768, 0.665319, -0.275115, -0.023022, -0.907976, -1.043657, 0.373516, 0.901532, +1.278539, -0.128456, 0.612821, 1.956518, 2.266326, -0.373959, 2.238039, -0.159580, +-0.703281, 0.563477, -0.050296, 1.163593, 0.658808, -1.550089, -3.029118, 0.540578, +-1.008998, 0.908047, 1.582303, -0.979088, 1.007902, 0.158491, -0.586927, 1.574082, +-0.516649, 1.227800, 1.583876, -2.088950, 2.949545, 1.356125, 1.050068, -0.767170, +-0.257653, -1.371845, -1.267656, -0.894948, 0.589089, 1.842629, 1.347967, -0.491253, +-2.177568, 0.237000, -0.735411, -1.779419, 0.448030, 0.581214, 0.856607, -0.266263, +-0.417470, -0.205806, -0.174323, 0.217577, 1.684295, 0.119528, 0.650667, 2.080061, +-0.339225, 0.730113, 0.293969, -0.849109, -2.533858, -2.378941, -0.346276, -0.610937, +-0.408192, -1.415611, 0.227122, 0.207974, -0.719718, 0.757762, -1.643135, -1.056813, +-0.251662, -1.298441, 1.233255, 1.494625, 0.235938, -1.404359, 0.658791, -2.556613, +-0.534945, 3.202525, 0.439198, -1.149901, 0.886765, -0.283386, 1.035336, -0.364878, +1.341987, 1.008872, 0.213874, -0.299264, 0.255849, -0.190826, -0.079060, 0.699851, +-0.796540, -0.801284, -0.007599, -0.726810, -1.490902, 0.870335, -0.265675, -1.566695, +-0.394636, -0.143855, -2.334247, -1.357539, -1.815689, 1.108422, -0.142115, 1.112757, +0.559264, 0.478370, -0.679385, 0.284967, -1.332935, -0.723980, -0.663600, 0.198443, +-1.794868, -1.387673, 0.197768, 1.469328, 0.366493, -0.442775, -0.048563, 0.077709, +1.957910, -0.072848, 0.938810, -0.079608, -0.800959, 0.309424, 1.051826, -1.664211, +-1.090792, -0.191731, 0.463401, -0.924147, -0.649657, 0.622893, -1.335107, 1.047689, +0.863327, -0.642411, 0.660010, 1.294116, 0.314579, 0.859573, 0.128670, 0.016568, +-0.072801, -0.994310, -0.747358, -0.030814, 0.988355, -0.599017, 1.476644, -0.813801, +0.645040, -1.309919, -0.867425, -0.474233, 0.222417, 1.871323, 0.110001, -0.411341, +0.511242, -1.199117, -0.096361, 0.445817, -0.295825, -0.167996, 0.179543, 0.421118, +1.677678, 1.996949, 0.696964, -1.366382, 0.363045, -0.567044, -1.044154, 0.697139, +0.484026, -0.193751, -0.378095, -0.886374, -1.840197, -1.628195, -1.173789, -0.415411, +0.175088, 0.229433, -1.240889, 0.700004, 0.426877, 1.454803, -0.510186, -0.006657, +-0.525496, 0.717698, 1.088374, 0.500552, 2.771790, -0.160309, 0.429489, -1.966817, +-0.546019, -1.888395, -0.107952, -1.316144, -0.672632, -0.902365, -0.154798, 0.947242, +1.550375, 0.429040, -0.560795, 0.179304, -0.771509, -0.943390, -1.407569, -1.906131, +-0.065293, 0.672149, 0.206147, -0.008124, 0.020042, -0.558447, 1.886079, -0.219975, +-1.414395, -0.302811, -0.569574, -0.121495, -0.390171, -0.844287, -1.737757, -0.449520, +-1.547933, -0.095776, 0.907714, 2.369602, 0.519768, 0.410525, 1.052585, 0.428784, +1.295088, -0.186053, 0.130733, -0.657627, -0.759267, -0.595170, 0.812400, 0.069541, +-1.833687, 1.827363, 0.654075, -1.544769, -0.375109, 0.207688, -0.765615, -0.106355, +0.338769, 1.033461, -1.404822, -1.030570, -0.643372, 0.170787, 1.344839, 1.936273, +0.741336, 0.811980, -0.142808, -0.099858, -0.800131, 0.493249, 1.237574, 1.295951, +-0.278196, 0.217127, 0.630728, -0.548549, 0.229632, 0.355311, 0.521284, -0.615971, +1.345803, 0.974922, -2.377934, -1.092319, -0.325710, -2.012228, 1.567660, 0.233337, +0.646420, -1.129412, 0.197038, 1.696870, 0.726034, 0.792526, 0.603357, -0.058405, +-1.108666, 2.144229, -1.352821, 0.457021, 0.391175, 2.073013, -0.323318, 1.468132, +-0.502399, 0.209593, 0.754800, -0.948189, 0.613157, 1.760503, 0.088762, 2.595570, +-0.675470, 2.786804, -0.016827, 0.271651, -0.914102, -1.951371, -0.317418, 0.588333, +0.828996, -1.674851, -1.922293, -0.436662, 0.044974, 2.416609, -0.309892, 0.187583, +0.947699, -0.525703, -1.115605, -1.592320, 1.174844, 0.485144, 1.645480, -0.454233, +1.008768, 2.049403, 0.602020, 0.017860, -1.610426, 1.238752, 0.683587, -0.780716, +0.530979, 2.134498, 0.354361, 0.231700, 1.287980, -0.013488, -1.333345, -0.556343, +0.755597, -0.911854, 1.371684, 0.245580, 0.118845, 0.384690, -0.070152, -0.578309, +0.469308, 1.299687, 1.634798, -0.702809, 0.807253, -1.027451, 1.294496, 0.014930, +0.218705, 1.713188, -2.078805, 0.112917, -1.086491, -1.558311, 0.637406, -0.404576, +-0.403325, 0.084076, -0.435349, -0.562623, 0.878062, -0.814650, -0.258363, 0.493299, +-0.802694, -0.008329, 0.627571, 0.154382, 2.580735, -1.306246, 1.023526, 0.777795, +-0.833884, -0.586663, 0.065664, -0.012342, -0.076987, -1.558587, 1.702607, -0.468984, +0.094619, 0.287071, 0.919354, 0.510136, 0.245440, -1.400519, 0.969571, 1.593698, +-1.437917, -1.534230, -0.074710, 0.081459, -0.843240, -0.564640, -0.028207, -1.243702, +0.733039, 0.059580, 0.149144, 1.595857, -0.777250, 1.550277, 1.055002, -0.166654, +0.314484, 1.419571, 0.327348, 0.475653, 0.398754, -0.072770, 1.314784, 0.978279, +1.722114, -0.412302, 0.565133, 0.739851, 0.220138, 1.312807, 0.629152, -1.107987, +-0.447001, -0.725993, 0.354045, -0.506772, -2.103747, -0.664684, 1.450110, -0.329805, +2.701872, -1.634939, -0.536325, 0.547223, 1.492603, -0.455243, -0.496416, 1.235260, +0.040926, 0.748467, 1.230764, 0.304903, 1.077771, 0.765151, -1.319580, -0.509191, +0.555116, -1.957625, -0.760453, -2.443886, -0.659366, -0.114779, 0.300079, -0.583996, +-3.073745, 1.551042, -0.407369, 1.428095, -1.353242, 0.903970, 0.541671, -0.465020 +}; + + + +/* ---------------------------------------------------------------------- +** Coefficients for 32-tap filter for Floating point LMS FIR filter +* FIR high pass filter with cutoff freq 9.6kHz (transition 9.6KHz to 11.52KHz) +** ------------------------------------------------------------------- */ +float32_t lmsNormCoeff_f32[32] = { +-0.004240, 0.002301, 0.008860, -0.000000, -0.019782, -0.010543, 0.032881, 0.034736, +-0.037374, -0.069586, 0.022397, 0.102169, 0.014185, -0.115908, -0.061648, 0.101018, +0.101018, -0.061648, -0.115908, 0.014185, 0.102169, 0.022397, -0.069586, -0.037374, +0.034736, 0.032881, -0.010543, -0.019782, -0.000000, 0.008860, 0.002301, -0.004240 + +}; + +/* ---------------------------------------------------------------------- +** Coefficients for 32-tap filter for Floating point FIR filter +* FIR low pass filter with cutoff freq 24Hz (transition 24Hz to 240Hz) +** ------------------------------------------------------------------- */ +const float32_t FIRCoeff_f32[32] = { +0.004502, 0.005074, 0.006707, 0.009356, 0.012933, 0.017303, 0.022298, 0.027717, +0.033338, 0.038930, 0.044258, 0.049098, 0.053243, 0.056519, 0.058784, 0.059941, +0.059941, 0.058784, 0.056519, 0.053243, 0.049098, 0.044258, 0.038930, 0.033338, +0.027717, 0.022298, 0.017303, 0.012933, 0.009356, 0.006707, 0.005074, 0.004502 + +}; + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.c new file mode 100644 index 00000000..155c001d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.c @@ -0,0 +1,271 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_signal_converge_example_f32.c +* +* Description: Example code demonstrating convergence of an adaptive +* filter. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup SignalConvergence Signal Convergence Example + * + * \par Description: + * \par + * Demonstrates the ability of an adaptive filter to "learn" the transfer function of + * a FIR lowpass filter using the Normalized LMS Filter, Finite Impulse + * Response (FIR) Filter, and Basic Math Functions. + * + * \par Algorithm: + * \par + * The figure below illustrates the signal flow in this example. Uniformly distributed white + * noise is passed through an FIR lowpass filter. The output of the FIR filter serves as the + * reference input of the adaptive filter (normalized LMS filter). The white noise is input + * to the adaptive filter. The adaptive filter learns the transfer function of the FIR filter. + * The filter outputs two signals: (1) the output of the internal adaptive FIR filter, and + * (2) the error signal which is the difference between the adaptive filter and the reference + * output of the FIR filter. Over time as the adaptive filter learns the transfer function + * of the FIR filter, the first output approaches the reference output of the FIR filter, + * and the error signal approaches zero. + * \par + * The adaptive filter converges properly even if the input signal has a large dynamic + * range (i.e., varies from small to large values). The coefficients of the adaptive filter + * are initially zero, and then converge over 1536 samples. The internal function test_signal_converge() + * implements the stopping condition. The function checks if all of the values of the error signal have a + * magnitude below a threshold DELTA. + * + * \par Block Diagram: + * \par + * \image html SignalFlow.gif + * + * + * \par Variables Description: + * \par + * \li \c testInput_f32 points to the input data + * \li \c firStateF32 points to FIR state buffer + * \li \c lmsStateF32 points to Normalised Least mean square FIR filter state buffer + * \li \c FIRCoeff_f32 points to coefficient buffer + * \li \c lmsNormCoeff_f32 points to Normalised Least mean square FIR filter coefficient buffer + * \li \c wire1, wir2, wire3 temporary buffers + * \li \c errOutput, err_signal temporary error buffers + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_lms_norm_init_f32() + * - arm_fir_init_f32() + * - arm_fir_f32() + * - arm_lms_norm_f32() + * - arm_scale_f32() + * - arm_abs_f32() + * - arm_sub_f32() + * - arm_min_f32() + * - arm_copy_f32() + * + * Refer + * \link arm_signal_converge_example_f32.c \endlink + * + */ + + +/** \example arm_signal_converge_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +#if defined(SEMIHOSTING) +#include +#endif + +/* ---------------------------------------------------------------------- +** Global defines for the simulation +* ------------------------------------------------------------------- */ + +#define TEST_LENGTH_SAMPLES 1536 +#define NUMTAPS 32 +#define BLOCKSIZE 32 +#define DELTA_ERROR 0.00009f +#define DELTA_COEFF 0.0001f +#define MU 0.5f + +#define NUMFRAMES (TEST_LENGTH_SAMPLES / BLOCKSIZE) + +/* ---------------------------------------------------------------------- +* Declare FIR state buffers and structure +* ------------------------------------------------------------------- */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +float32_t firStateF32[2 * BLOCKSIZE + NUMTAPS - 1]; +#else +float32_t firStateF32[NUMTAPS + BLOCKSIZE]; +#endif + +arm_fir_instance_f32 LPF_instance; + +/* ---------------------------------------------------------------------- +* Declare LMSNorm state buffers and structure +* ------------------------------------------------------------------- */ + +float32_t lmsStateF32[NUMTAPS + BLOCKSIZE]; +float32_t errOutput[TEST_LENGTH_SAMPLES]; +arm_lms_norm_instance_f32 lmsNorm_instance; + + +/* ---------------------------------------------------------------------- +* Function Declarations for Signal Convergence Example +* ------------------------------------------------------------------- */ + +arm_status test_signal_converge_example( void ); + + +/* ---------------------------------------------------------------------- +* Internal functions +* ------------------------------------------------------------------- */ +arm_status test_signal_converge(float32_t* err_signal, + uint32_t blockSize); + +void getinput(float32_t* input, + uint32_t fr_cnt, + uint32_t blockSize); + +/* ---------------------------------------------------------------------- +* External Declarations for FIR F32 module Test +* ------------------------------------------------------------------- */ +extern float32_t testInput_f32[TEST_LENGTH_SAMPLES]; +extern float32_t lmsNormCoeff_f32[32]; +extern const float32_t FIRCoeff_f32[32]; +extern arm_lms_norm_instance_f32 lmsNorm_instance; + +/* ---------------------------------------------------------------------- +* Declare I/O buffers +* ------------------------------------------------------------------- */ + +float32_t wire1[BLOCKSIZE]; +float32_t wire2[BLOCKSIZE]; +float32_t wire3[BLOCKSIZE]; +float32_t err_signal[BLOCKSIZE]; + +/* ---------------------------------------------------------------------- +* Signal converge test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + uint32_t i; + arm_status status; + uint32_t index; + float32_t minValue; + + /* Initialize the LMSNorm data structure */ + arm_lms_norm_init_f32(&lmsNorm_instance, NUMTAPS, lmsNormCoeff_f32, lmsStateF32, MU, BLOCKSIZE); + + /* Initialize the FIR data structure */ + arm_fir_init_f32(&LPF_instance, NUMTAPS, (float32_t *)FIRCoeff_f32, firStateF32, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + * Loop over the frames of data and execute each of the processing + * functions in the system. + * ------------------------------------------------------------------- */ + + for(i=0; i < NUMFRAMES; i++) + { + /* Read the input data - uniformly distributed random noise - into wire1 */ + arm_copy_f32(testInput_f32 + (i * BLOCKSIZE), wire1, BLOCKSIZE); + + /* Execute the FIR processing function. Input wire1 and output wire2 */ + arm_fir_f32(&LPF_instance, wire1, wire2, BLOCKSIZE); + + /* Execute the LMS Norm processing function*/ + + arm_lms_norm_f32(&lmsNorm_instance, /* LMSNorm instance */ + wire1, /* Input signal */ + wire2, /* Reference Signal */ + wire3, /* Converged Signal */ + err_signal, /* Error Signal, this will become small as the signal converges */ + BLOCKSIZE); /* BlockSize */ + + /* apply overall gain */ + arm_scale_f32(wire3, 5, wire3, BLOCKSIZE); /* in-place buffer */ + } + + status = ARM_MATH_SUCCESS; + + /* ------------------------------------------------------------------------------- + * Test whether the error signal has reached towards 0. + * ----------------------------------------------------------------------------- */ + + arm_abs_f32(err_signal, err_signal, BLOCKSIZE); + arm_min_f32(err_signal, BLOCKSIZE, &minValue, &index); + + if (minValue > DELTA_ERROR) + { + status = ARM_MATH_TEST_FAILURE; + } + + /* ---------------------------------------------------------------------- + * Test whether the filter coefficients have converged. + * ------------------------------------------------------------------- */ + + arm_sub_f32((float32_t *)FIRCoeff_f32, lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS); + + arm_abs_f32(lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS); + arm_min_f32(lmsNormCoeff_f32, NUMTAPS, &minValue, &index); + + status = (minValue > DELTA_COEFF) ? ARM_MATH_TEST_FAILURE : ARM_MATH_SUCCESS; + + if (status != ARM_MATH_SUCCESS) + { +#if defined (SEMIHOSTING) + printf("FAILURE\n"); +#else + while (1); /* main function does not return */ +#endif + } + else + { +#if defined (SEMIHOSTING) + printf("SUCCESS\n"); +#else + while (1); /* main function does not return */ +#endif + } + +} + + /** \endlink */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.c new file mode 100644 index 00000000..c87c97d9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.c @@ -0,0 +1,472 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/* + +Conflicting with the new clip functions in CMSIS-DSP and not used +in the examples. + +*/ +#if 0 +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + +#endif + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.h b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.h new file mode 100644 index 00000000..a0dbdf73 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM0_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM0_config.txt new file mode 100644 index 00000000..13dc7839 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM3_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM3_config.txt new file mode 100644 index 00000000..55419ac8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM4_FP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM4_FP_config.txt new file mode 100644 index 00000000..fb9d24c9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM55_FP_MVE_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 00000000..4a65b1de --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM7_SP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM7_SP_config.txt new file mode 100644 index 00000000..82fc00c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/Abstract.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/Abstract.txt new file mode 100644 index 00000000..6b60d30b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_sin_cos_example. + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/CMakeLists.txt new file mode 100644 index 00000000..76c66491 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_sin_cos_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_sin_cos_example) + + +include(config) +configApp(arm_sin_cos_example ${ROOT}) + +target_sources(arm_sin_cos_example PRIVATE arm_sin_cos_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_sin_cos_example PRIVATE CMSISDSP) + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 00000000..f527fa11 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/system_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 00000000..66a364c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 00000000..0392a899 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/system_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 00000000..3c5eda7d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 00000000..90eee9dc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 00000000..9d983d2e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 00000000..0ab7e3e9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM55/system_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 00000000..b76ebb7c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 00000000..78584996 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 00000000..75f9c18e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.c new file mode 100644 index 00000000..41614fce --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.c @@ -0,0 +1,177 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 12. March 2014 +* $Revision: V1.4.3 +* +* Project: CMSIS DSP Library +* Title: arm_sin_cos_example_f32.c +* +* Description: Example code demonstrating sin and cos calculation of input signal. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup SinCosExample SineCosine Example + * + * \par Description: + * \par + * Demonstrates the Pythagorean trignometric identity with the use of Cosine, Sine, Vector + * Multiplication, and Vector Addition functions. + * + * \par Algorithm: + * \par + * Mathematically, the Pythagorean trignometric identity is defined by the following equation: + *
sin(x) * sin(x) + cos(x) * cos(x) = 1
+ * where \c x is the angle in radians. + * + * \par Block Diagram: + * \par + * \image html sinCos.gif + * + * \par Variables Description: + * \par + * \li \c testInput_f32 array of input angle in radians + * \li \c testOutput stores sum of the squares of sine and cosine values of input angle + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_cos_f32() + * - arm_sin_f32() + * - arm_mult_f32() + * - arm_add_f32() + * + * Refer + * \link arm_sin_cos_example_f32.c \endlink + * + */ + + +/** \example arm_sin_cos_example_f32.c + */ + +#include +#include "arm_math.h" + +#if defined(SEMIHOSTING) +#include +#endif + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 32 +#define DELTA (0.0001f) + + +/* ---------------------------------------------------------------------- +* Test input data for Floating point sin_cos example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ + +const float32_t testInput_f32[MAX_BLOCKSIZE] = +{ + -1.244916875853235400, -4.793533929171324800, 0.360705030233248850, 0.827929644170887320, -3.299532218312426900, 3.427441903227623800, 3.422401784294607700, -0.108308165334010680, + 0.941943896490312180, 0.502609575000365850, -0.537345278736373500, 2.088817392965764500, -1.693168684143455700, 6.283185307179590700, -0.392545884746175080, 0.327893095115825040, + 3.070147440456292300, 0.170611405884662230, -0.275275082396073010, -2.395492805446796300, 0.847311163536506600, -3.845517018083148800, 2.055818378415868300, 4.672594161978930800, + -1.990923030266425800, 2.469305197656249500, 3.609002606064021000, -4.586736582331667500, -4.147080139136136300, 1.643756718868359500, -1.150866392366494800, 1.985805026477433800 + + +}; + +const float32_t testRefOutput_f32 = 1.000000000; + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +uint32_t blockSize = 32; +float32_t testOutput; +float32_t cosOutput; +float32_t sinOutput; +float32_t cosSquareOutput; +float32_t sinSquareOutput; + +/* ---------------------------------------------------------------------- +* Max magnitude FFT Bin test +* ------------------------------------------------------------------- */ + +arm_status status; + +int32_t main(void) +{ + float32_t diff; + uint32_t i; + + for(i=0; i< blockSize; i++) + { + cosOutput = arm_cos_f32(testInput_f32[i]); + sinOutput = arm_sin_f32(testInput_f32[i]); + + arm_mult_f32(&cosOutput, &cosOutput, &cosSquareOutput, 1); + arm_mult_f32(&sinOutput, &sinOutput, &sinSquareOutput, 1); + + arm_add_f32(&cosSquareOutput, &sinSquareOutput, &testOutput, 1); + + /* absolute value of difference between ref and test */ + diff = fabsf(testRefOutput_f32 - testOutput); + + /* Comparison of sin_cos value with reference */ + status = (diff > DELTA) ? ARM_MATH_TEST_FAILURE : ARM_MATH_SUCCESS; + + if ( status == ARM_MATH_TEST_FAILURE) + { + break; + } + } + + if (status != ARM_MATH_SUCCESS) + { +#if defined (SEMIHOSTING) + printf("FAILURE\n"); +#else + while (1); /* main function does not return */ +#endif + } + else + { +#if defined (SEMIHOSTING) + printf("SUCCESS\n"); +#else + while (1); /* main function does not return */ +#endif + } + +} + + /** \endlink */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM0_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM0_config.txt new file mode 100644 index 00000000..13dc7839 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM3_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM3_config.txt new file mode 100644 index 00000000..55419ac8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM4_FP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM4_FP_config.txt new file mode 100644 index 00000000..fb9d24c9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM55_FP_MVE_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 00000000..4a65b1de --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM7_SP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM7_SP_config.txt new file mode 100644 index 00000000..82fc00c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/Abstract.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/Abstract.txt new file mode 100644 index 00000000..cad7ae10 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_svm_example. + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/CMakeLists.txt new file mode 100644 index 00000000..2fa5d18c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_svm_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_svm_example) + + +include(config) +configApp(arm_svm_example ${ROOT}) + +target_sources(arm_svm_example PRIVATE arm_svm_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_svm_example PRIVATE CMSISDSP) + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 00000000..f527fa11 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM0/system_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 00000000..66a364c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 00000000..0392a899 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM3/system_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 00000000..3c5eda7d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 00000000..90eee9dc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 00000000..9d983d2e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 00000000..0ab7e3e9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM55/system_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 00000000..b76ebb7c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 00000000..78584996 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 00000000..75f9c18e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/arm_svm_example_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/arm_svm_example_f32.c new file mode 100644 index 00000000..bcadcbc8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/arm_svm_example_f32.c @@ -0,0 +1,163 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2019-2020 ARM Limited. All rights reserved. +* +* $Date: 09. December 2019 +* $Revision: V1.0.0 +* +* Project: CMSIS DSP Library +* Title: arm_svm_example_f32.c +* +* Description: Example code demonstrating how to use SVM functions. +* +* Target Processor: Cortex-M/Cortex-A +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup SVMExample SVM Example + * + * \par Description: + * \par + * Demonstrates the use of SVM functions. It is complementing the tutorial + * about classical ML with CMSIS-DSP and python scikit-learn: + * https://developer.arm.com/solutions/machine-learning-on-arm/developer-material/how-to-guides/implement-classical-ml-with-arm-cmsis-dsp-libraries + * + */ + + +/** \example arm_svm_example_f32.c + */ + +#include +#include +#include "arm_math.h" + +/* + The polynomial SVM instance containing all parameters. + Those parameters can be generated with the python library scikit-learn. + */ +arm_svm_polynomial_instance_f32 params; + +/* + Parameters generated by a training of the SVM classifier + using scikit-learn and some random input data. + */ +#define NB_SUPPORT_VECTORS 11 + +/* + Dimension of the vector space. A vector is your feature. + It could, for instance, be the pixels of a picture or the FFT of a signal. + */ +#define VECTOR_DIMENSION 2 + +const float32_t dualCoefficients[NB_SUPPORT_VECTORS]={-0.01628988f, -0.0971605f, + -0.02707579f, 0.0249406f, 0.00223095f, 0.04117345f, + 0.0262687f, 0.00800358f, 0.00581823f, 0.02346904f, 0.00862162f}; /* Dual coefficients */ + +const float32_t supportVectors[NB_SUPPORT_VECTORS*VECTOR_DIMENSION]={ 1.2510991f, 0.47782799f, + -0.32711859f, -1.49880648f, -0.08905047f, 1.31907242f, + 1.14059333f, 2.63443767f, -2.62561524f, 1.02120701f, + -1.2361353f, -2.53145187f, + 2.28308122f, -1.58185875f, 2.73955981f, 0.35759327f, + 0.56662986f, 2.79702016f, + -2.51380816f, 1.29295364f, -0.56658669f, -2.81944734f}; /* Support vectors */ + +/* + Class A is identified with value 0. + Class B is identified with value 1. + + This array is used by the SVM functions to do a conversion and ease the comparison + with the Python code where different values could be used. + */ +const int32_t classes[2]={0,1}; + + +int32_t main(void) +{ + /* Array of input data */ + float32_t in[VECTOR_DIMENSION]; + + /* Result of the classifier */ + int32_t result; + + + /* + Initialization of the SVM instance parameters. + Additional parameters (intercept, degree, coef0 and gamma) are also coming from Python. + */ + arm_svm_polynomial_init_f32(¶ms, + NB_SUPPORT_VECTORS, + VECTOR_DIMENSION, + -1.661719f, /* Intercept */ + dualCoefficients, + supportVectors, + classes, + 3, /* degree */ + 1.100000f, /* Coef0 */ + 0.500000f /* Gamma */ + ); + + + /* + Input data. + It is corresponding to a point inside the first class. + */ + in[0] = 0.4f; + in[1] = 0.1f; + + arm_svm_polynomial_predict_f32(¶ms, in, &result); + + /* Result should be 0 : First class */ +#if defined(SEMIHOSTING) + printf("Result = %d\n", result); +#endif + + /* + This input vector is corresponding to a point inside the second class. + */ + in[0] = 3.0f; + in[1] = 0.0f; + + arm_svm_polynomial_predict_f32(¶ms, in, &result); + + /* Result should be 1 : Second class */ +#if defined(SEMIHOSTING) + printf("Result = %d\n", result); +#endif + +#if !defined(SEMIHOSTING) + while (1); /* main function does not return */ +#endif +} + + + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM0_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM0_config.txt new file mode 100644 index 00000000..13dc7839 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM3_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM3_config.txt new file mode 100644 index 00000000..55419ac8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM4_FP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM4_FP_config.txt new file mode 100644 index 00000000..fb9d24c9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM55_FP_MVE_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 00000000..4a65b1de --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM7_SP_config.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM7_SP_config.txt new file mode 100644 index 00000000..82fc00c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt new file mode 100644 index 00000000..d4712e84 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_variance_example. + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/CMakeLists.txt new file mode 100644 index 00000000..c7cdbd04 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_variance_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_variance_example) + + +include(config) +configApp(arm_variance_example ${ROOT}) + +target_sources(arm_variance_example PRIVATE arm_variance_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_variance_example PRIVATE CMSISDSP) + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 00000000..f527fa11 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/system_ARMCM0.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 00000000..66a364c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 00000000..0392a899 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/system_ARMCM3.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 00000000..3c5eda7d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 00000000..90eee9dc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 00000000..9d983d2e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 00000000..0ab7e3e9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM55/system_ARMCM55.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 00000000..b76ebb7c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 00000000..78584996 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 00000000..75f9c18e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c new file mode 100644 index 00000000..f40e0187 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c @@ -0,0 +1,224 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_variance_example_f32.c +* +* Description: Example code demonstrating variance calculation of input sequence. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup VarianceExample Variance Example + * + * \par Description: + * \par + * Demonstrates the use of Basic Math and Support Functions to calculate the variance of an + * input sequence with N samples. Uniformly distributed white noise is taken as input. + * + * \par Algorithm: + * \par + * The variance of a sequence is the mean of the squared deviation of the sequence from its mean. + * \par + * This is denoted by the following equation: + *
 variance = ((x[0] - x') * (x[0] - x') + (x[1] - x') * (x[1] - x') + ... + * (x[n-1] - x') * (x[n-1] - x')) / (N-1)
+ * where, x[n] is the input sequence, N is the number of input samples, and + * x' is the mean value of the input sequence, x[n]. + * \par + * The mean value x' is defined as: + *
 x' = (x[0] + x[1] + ... + x[n-1]) / N
+ * + * \par Block Diagram: + * \par + * \image html Variance.gif + * + * + * \par Variables Description: + * \par + * \li \c testInput_f32 points to the input data + * \li \c wire1, \c wir2, \c wire3 temporary buffers + * \li \c blockSize number of samples processed at a time + * \li \c refVarianceOut reference variance value + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_dot_prod_f32() + * - arm_mult_f32() + * - arm_sub_f32() + * - arm_fill_f32() + * - arm_copy_f32() + * + * Refer + * \link arm_variance_example_f32.c \endlink + * + */ + + +/** \example arm_variance_example_f32.c + */ + +#include +#include "arm_math.h" + +#if defined(SEMIHOSTING) +#include +#endif + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 32 +#define DELTA (0.000001f) + + +/* ---------------------------------------------------------------------- +* Declare I/O buffers +* ------------------------------------------------------------------- */ +float32_t wire1[MAX_BLOCKSIZE]; +float32_t wire2[MAX_BLOCKSIZE]; +float32_t wire3[MAX_BLOCKSIZE]; + +/* ---------------------------------------------------------------------- +* Test input data for Floating point Variance example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ + +float32_t testInput_f32[32] = +{ + -0.432564811528221, -1.665584378238097, 0.125332306474831, 0.287676420358549, + -1.146471350681464, 1.190915465642999, 1.189164201652103, -0.037633276593318, + 0.327292361408654, 0.174639142820925, -0.186708577681439, 0.725790548293303, + -0.588316543014189, 2.183185818197101, -0.136395883086596, 0.113931313520810, + 1.066768211359189, 0.059281460523605, -0.095648405483669, -0.832349463650022, + 0.294410816392640, -1.336181857937804, 0.714324551818952, 1.623562064446271, + -0.691775701702287, 0.857996672828263, 1.254001421602532, -1.593729576447477, + -1.440964431901020, 0.571147623658178, -0.399885577715363, 0.689997375464345 + +}; + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +uint32_t blockSize = 32; +float32_t refVarianceOut = 0.903941793931839; + +/* ---------------------------------------------------------------------- +* Variance calculation test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + arm_status status; + float32_t mean, oneByBlockSize; + float32_t variance; + float32_t diff; + + status = ARM_MATH_SUCCESS; + +#if defined(SEMIHOSTING) + printf("START\n"); +#endif + + + /* Calculation of mean value of input */ + + /* x' = 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */ + + /* Fill wire1 buffer with 1.0 value */ + arm_fill_f32(1.0, wire1, blockSize); + + /* Calculate the dot product of wire1 and wire2 */ + /* (x(0)* 1 + x(1) * 1 + ...+ x(n-1) * 1) */ + arm_dot_prod_f32(testInput_f32, wire1, blockSize, &mean); + + /* Calculation of 1/blockSize */ + oneByBlockSize = 1.0 / (blockSize); + + /* 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */ + arm_mult_f32(&mean, &oneByBlockSize, &mean, 1); + + + /* Calculation of variance value of input */ + + /* (1/blockSize) * (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */ + + /* Fill wire2 with mean value x' */ + arm_fill_f32(mean, wire2, blockSize); + + /* wire3 contains (x-x') */ + arm_sub_f32(testInput_f32, wire2, wire3, blockSize); + + /* wire2 contains (x-x') */ + arm_copy_f32(wire3, wire2, blockSize); + + /* (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */ + arm_dot_prod_f32(wire2, wire3, blockSize, &variance); + + /* Calculation of 1/blockSize */ + oneByBlockSize = 1.0 / (blockSize - 1); + + /* Calculation of variance */ + arm_mult_f32(&variance, &oneByBlockSize, &variance, 1); + + /* absolute value of difference between ref and test */ + diff = fabsf(refVarianceOut - variance); + + /* Comparison of variance value with reference */ + status = (diff > DELTA) ? ARM_MATH_TEST_FAILURE : ARM_MATH_SUCCESS; + + if (status != ARM_MATH_SUCCESS) + { +#if defined (SEMIHOSTING) + printf("FAILURE\n"); +#else + while (1); /* main function does not return */ +#endif + } + else + { +#if defined (SEMIHOSTING) + printf("SUCCESS\n"); +#else + while (1); /* main function does not return */ +#endif + } + +} + + /** \endlink */ + + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_common_tables.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_common_tables.h new file mode 100644 index 00000000..3e72c806 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_common_tables.h @@ -0,0 +1,539 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * @version V1.10.0 + * @date 08 July 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math_types.h" +#include "dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + /* Double Precision Float CFFT twiddles */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + extern const uint16_t armBitRevTable[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_16) + extern const uint64_t twiddleCoefF64_16[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_32) + extern const uint64_t twiddleCoefF64_32[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_64) + extern const uint64_t twiddleCoefF64_64[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_128) + extern const uint64_t twiddleCoefF64_128[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_256) + extern const uint64_t twiddleCoefF64_256[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_512) + extern const uint64_t twiddleCoefF64_512[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_1024) + extern const uint64_t twiddleCoefF64_1024[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_2048) + extern const uint64_t twiddleCoefF64_2048[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_4096) + extern const uint64_t twiddleCoefF64_4096[8192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) + extern const float32_t twiddleCoef_16[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + extern const float32_t twiddleCoef_32[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) + extern const float32_t twiddleCoef_64[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + extern const float32_t twiddleCoef_128[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) + extern const float32_t twiddleCoef_256[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + extern const float32_t twiddleCoef_512[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) + extern const float32_t twiddleCoef_1024[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + extern const float32_t twiddleCoef_2048[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + extern const float32_t twiddleCoef_4096[8192]; + #define twiddleCoef twiddleCoef_4096 + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + /* Q31 */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) + extern const q31_t twiddleCoef_16_q31[24]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) + extern const q31_t twiddleCoef_32_q31[48]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) + extern const q31_t twiddleCoef_64_q31[96]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) + extern const q31_t twiddleCoef_128_q31[192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) + extern const q31_t twiddleCoef_256_q31[384]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) + extern const q31_t twiddleCoef_512_q31[768]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) + extern const q31_t twiddleCoef_1024_q31[1536]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) + extern const q31_t twiddleCoef_2048_q31[3072]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) + extern const q31_t twiddleCoef_4096_q31[6144]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) + extern const q15_t twiddleCoef_16_q15[24]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) + extern const q15_t twiddleCoef_32_q15[48]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) + extern const q15_t twiddleCoef_64_q15[96]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) + extern const q15_t twiddleCoef_128_q15[192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) + extern const q15_t twiddleCoef_256_q15[384]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) + extern const q15_t twiddleCoef_512_q15[768]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) + extern const q15_t twiddleCoef_1024_q15[1536]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) + extern const q15_t twiddleCoef_2048_q15[3072]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) + extern const q15_t twiddleCoef_4096_q15[6144]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + /* Double Precision Float RFFT twiddles */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32) + extern const uint64_t twiddleCoefF64_rfft_32[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64) + extern const uint64_t twiddleCoefF64_rfft_64[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128) + extern const uint64_t twiddleCoefF64_rfft_128[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256) + extern const uint64_t twiddleCoefF64_rfft_256[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512) + extern const uint64_t twiddleCoefF64_rfft_512[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024) + extern const uint64_t twiddleCoefF64_rfft_1024[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048) + extern const uint64_t twiddleCoefF64_rfft_2048[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096) + extern const uint64_t twiddleCoefF64_rfft_4096[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32) + extern const float32_t twiddleCoef_rfft_32[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64) + extern const float32_t twiddleCoef_rfft_64[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128) + extern const float32_t twiddleCoef_rfft_128[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256) + extern const float32_t twiddleCoef_rfft_256[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512) + extern const float32_t twiddleCoef_rfft_512[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024) + extern const float32_t twiddleCoef_rfft_1024[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048) + extern const float32_t twiddleCoef_rfft_2048[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096) + extern const float32_t twiddleCoef_rfft_4096[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + /* Double precision floating-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_16) + #define ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH ((uint16_t)12) + extern const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_32) + #define ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH ((uint16_t)24) + extern const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_64) + #define ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_128) + #define ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH ((uint16_t)112) + extern const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_256) + #define ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH ((uint16_t)240) + extern const uint16_t armBitRevIndexTableF64_256[ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_512) + #define ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH ((uint16_t)480) + extern const uint16_t armBitRevIndexTableF64_512[ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_1024) + #define ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH ((uint16_t)992) + extern const uint16_t armBitRevIndexTableF64_1024[ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_2048) + #define ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH ((uint16_t)1984) + extern const uint16_t armBitRevIndexTableF64_2048[ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_4096) + #define ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTableF64_4096[ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + /* floating-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16) + #define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) + extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32) + #define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) + extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64) + #define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128) + #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) + extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256) + #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) + extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512) + #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) + extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024) + #define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) + extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048) + #define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) + extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096) + #define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + /* fixed-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16) + #define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) + extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32) + #define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) + extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64) + #define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128) + #define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) + extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256) + #define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) + extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512) + #define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) + extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024) + #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) + extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048) + #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) + extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096) + #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32) + extern const float32_t realCoefA[8192]; + extern const float32_t realCoefB[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31) + extern const q31_t realCoefAQ31[8192]; + extern const q31_t realCoefBQ31[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15) + extern const q15_t realCoefAQ15[8192]; + extern const q15_t realCoefBQ15[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128) + extern const float32_t Weights_128[256]; + extern const float32_t cos_factors_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512) + extern const float32_t Weights_512[1024]; + extern const float32_t cos_factors_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048) + extern const float32_t Weights_2048[4096]; + extern const float32_t cos_factors_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192) + extern const float32_t Weights_8192[16384]; + extern const float32_t cos_factors_8192[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128) + extern const q15_t WeightsQ15_128[256]; + extern const q15_t cos_factorsQ15_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512) + extern const q15_t WeightsQ15_512[1024]; + extern const q15_t cos_factorsQ15_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048) + extern const q15_t WeightsQ15_2048[4096]; + extern const q15_t cos_factorsQ15_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192) + extern const q15_t WeightsQ15_8192[16384]; + extern const q15_t cos_factorsQ15_8192[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128) + extern const q31_t WeightsQ31_128[256]; + extern const q31_t cos_factorsQ31_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512) + extern const q31_t WeightsQ31_512[1024]; + extern const q31_t cos_factorsQ31_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048) + extern const q31_t WeightsQ31_2048[4096]; + extern const q31_t cos_factorsQ31_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192) + extern const q31_t WeightsQ31_8192[16384]; + extern const q31_t cos_factorsQ31_8192[8192]; + #endif + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15) + extern const q15_t armRecipTableQ15[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31) + extern const q31_t armRecipTableQ31[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + /* Tables for Fast Math Sine and Cosine */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32) + extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31) + extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15) + extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + /* Fast vector sqrt */ + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) + extern const q31_t sqrtTable_Q31[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + #endif + + /* Accurate scalar sqrt */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q31) + extern const q31_t sqrt_initial_lut_q31[32]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q15) + extern const q15_t sqrt_initial_lut_q15[16]; + #endif + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE) + extern const q15_t sqrtTable_Q15[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + #endif + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */ + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + extern const float32_t exp_tab[8]; + extern const float32_t __logf_lut_f32[8]; +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) +extern const unsigned char hwLUT[256]; +#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ + +#ifdef __cplusplus +} +#endif + +#endif /* ARM_COMMON_TABLES_H */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_common_tables_f16.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_common_tables_f16.h new file mode 100644 index 00000000..f40c1a4e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_common_tables_f16.h @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables_f16.h + * Description: Extern declaration for common tables + * + * @version V1.9.0 + * @date 23 April 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_F16_H +#define _ARM_COMMON_TABLES_F16_H + +#include "arm_math_types_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + + /* F16 */ + #if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_16) + extern const float16_t twiddleCoefF16_16[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_32) + extern const float16_t twiddleCoefF16_32[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_64) + extern const float16_t twiddleCoefF16_64[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_128) + extern const float16_t twiddleCoefF16_128[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_256) + extern const float16_t twiddleCoefF16_256[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_512) + extern const float16_t twiddleCoefF16_512[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_1024) + extern const float16_t twiddleCoefF16_1024[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048) + extern const float16_t twiddleCoefF16_2048[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) + extern const float16_t twiddleCoefF16_4096[8192]; + #define twiddleCoefF16 twiddleCoefF16_4096 + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_32) + extern const float16_t twiddleCoefF16_rfft_32[32]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_64) + extern const float16_t twiddleCoefF16_rfft_64[64]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_128) + extern const float16_t twiddleCoefF16_rfft_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_256) + extern const float16_t twiddleCoefF16_rfft_256[256]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_512) + extern const float16_t twiddleCoefF16_rfft_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_1024) + extern const float16_t twiddleCoefF16_rfft_1024[1024]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_2048) + extern const float16_t twiddleCoefF16_rfft_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_4096) + extern const float16_t twiddleCoefF16_rfft_4096[4096]; + #endif + + #endif /* ARMAC5 */ + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED) + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + extern const float16_t exp_tab_f16[8]; + extern const float16_t __logf_lut_f16[8]; +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* _ARM_COMMON_TABLES_F16_H */ + + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_const_structs.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_const_structs.h new file mode 100644 index 00000000..59026db5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_const_structs.h @@ -0,0 +1,86 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * @version V1.10.0 + * @date 08 July 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math_types.h" +#include "arm_common_tables.h" +#include "dsp/transform_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len16; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len32; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len64; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len128; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len256; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len512; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len1024; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len2048; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len4096; + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_const_structs_f16.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_const_structs_f16.h new file mode 100644 index 00000000..0984d74a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_const_structs_f16.h @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs_f16.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f16() function. + * + * @version V1.10.0 + * @date 08 July 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_F16_H +#define _ARM_CONST_STRUCTS_F16_H + +#include "arm_math_types_f16.h" +#include "arm_common_tables.h" +#include "arm_common_tables_f16.h" +#include "dsp/transform_functions_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_16) && defined(ARM_TABLE_BITREVIDX_FLT_16)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len16; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_32) && defined(ARM_TABLE_BITREVIDX_FLT_32)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len32; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_64) && defined(ARM_TABLE_BITREVIDX_FLT_64)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len64; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_128) && defined(ARM_TABLE_BITREVIDX_FLT_128)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len128; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_256) && defined(ARM_TABLE_BITREVIDX_FLT_256)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len256; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_512) && defined(ARM_TABLE_BITREVIDX_FLT_512)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len512; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len1024; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len2048; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len4096; + #endif +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_helium_utils.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_helium_utils.h new file mode 100644 index 00000000..ae9037cf --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_helium_utils.h @@ -0,0 +1,753 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_helium_utils.h + * Description: Utility functions for Helium development + * + * @version V1.10.0 + * @date 08 July 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_UTILS_HELIUM_H_ +#define _ARM_UTILS_HELIUM_H_ + + +#ifdef __cplusplus +extern "C" +{ +#endif +/*************************************** + +Definitions available for MVEF and MVEI + +***************************************/ +#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define INACTIVELANE 0 /* inactive lane content */ + + +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) */ + +/*************************************** + +Definitions available for MVEF only + +***************************************/ +#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) + +__STATIC_FORCEINLINE float32_t vecAddAcrossF32Mve(float32x4_t in) +{ + float32_t acc; + + acc = vgetq_lane(in, 0) + vgetq_lane(in, 1) + + vgetq_lane(in, 2) + vgetq_lane(in, 3); + + return acc; +} + + + + +/* newton initial guess */ +#define INVSQRT_MAGIC_F32 0x5f3759df +#define INV_NEWTON_INIT_F32 0x7EF127EA + + +#define INVSQRT_NEWTON_MVE_F32(invSqrt, xHalf, xStart)\ +{ \ + float32x4_t tmp; \ + \ + /* tmp = xhalf * x * x */ \ + tmp = vmulq(xStart, xStart); \ + tmp = vmulq(tmp, xHalf); \ + /* (1.5f - xhalf * x * x) */ \ + tmp = vsubq(vdupq_n_f32(1.5f), tmp); \ + /* x = x*(1.5f-xhalf*x*x); */ \ + invSqrt = vmulq(tmp, xStart); \ +} +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) */ + + +/*************************************** + +Definitions available for f16 datatype with HW acceleration only + +***************************************/ +#if defined(ARM_FLOAT16_SUPPORTED) +#if defined (ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +__STATIC_FORCEINLINE float16_t vecAddAcrossF16Mve(float16x8_t in) +{ + float16x8_t tmpVec; + _Float16 acc; + + tmpVec = (float16x8_t) vrev32q_s16((int16x8_t) in); + in = vaddq_f16(tmpVec, in); + tmpVec = (float16x8_t) vrev64q_s32((int32x4_t) in); + in = vaddq_f16(tmpVec, in); + acc = (_Float16)vgetq_lane_f16(in, 0) + (_Float16)vgetq_lane_f16(in, 4); + + return acc; +} + +__STATIC_FORCEINLINE float16x8_t __mve_cmplx_sum_intra_vec_f16( + float16x8_t vecIn) +{ + float16x8_t vecTmp, vecOut; + uint32_t tmp; + + vecTmp = (float16x8_t) vrev64q_s32((int32x4_t) vecIn); + // TO TRACK : using canonical addition leads to unefficient code generation for f16 + // vecTmp = vecTmp + vecAccCpx0; + /* + * Compute + * re0+re1 | im0+im1 | re0+re1 | im0+im1 + * re2+re3 | im2+im3 | re2+re3 | im2+im3 + */ + vecTmp = vaddq_f16(vecTmp, vecIn); + vecOut = vecTmp; + /* + * shift left, random tmp insertion in bottom + */ + vecOut = vreinterpretq_f16_s32(vshlcq_s32(vreinterpretq_s32_f16(vecOut) , &tmp, 32)); + /* + * Compute: + * DONTCARE | DONTCARE | re0+re1+re0+re1 |im0+im1+im0+im1 + * re0+re1+re2+re3 | im0+im1+im2+im3 | re2+re3+re2+re3 |im2+im3+im2+im3 + */ + vecOut = vaddq_f16(vecOut, vecTmp); + /* + * Cmplx sum is in 4rd & 5th f16 elt + * return full vector + */ + return vecOut; +} + + +#define mve_cmplx_sum_intra_r_i_f16(vec, Re, Im) \ +{ \ + float16x8_t vecOut = __mve_cmplx_sum_intra_vec_f16(vec); \ + Re = vgetq_lane(vecOut, 4); \ + Im = vgetq_lane(vecOut, 5); \ +} + +__STATIC_FORCEINLINE void mve_cmplx_sum_intra_vec_f16( + float16x8_t vecIn, + float16_t *pOut) +{ + float16x8_t vecOut = __mve_cmplx_sum_intra_vec_f16(vecIn); + /* + * Cmplx sum is in 4rd & 5th f16 elt + * use 32-bit extraction + */ + *(float32_t *) pOut = ((float32x4_t) vecOut)[2]; +} + + +#define INVSQRT_MAGIC_F16 0x59ba /* ( 0x1ba = 0x3759df >> 13) */ + +/* canonical version of INVSQRT_NEWTON_MVE_F16 leads to bad performance */ +#define INVSQRT_NEWTON_MVE_F16(invSqrt, xHalf, xStart) \ +{ \ + float16x8_t tmp; \ + \ + /* tmp = xhalf * x * x */ \ + tmp = vmulq(xStart, xStart); \ + tmp = vmulq(tmp, xHalf); \ + /* (1.5f - xhalf * x * x) */ \ + tmp = vsubq(vdupq_n_f16((float16_t)1.5), tmp); \ + /* x = x*(1.5f-xhalf*x*x); */ \ + invSqrt = vmulq(tmp, xStart); \ +} + +#endif +#endif + +/*************************************** + +Definitions available for MVEI and MVEF only + +***************************************/ +#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE) +/* Following functions are used to transpose matrix in f32 and q31 cases */ +__STATIC_INLINE arm_status arm_mat_trans_32bit_2x2_mve( + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + static const uint32x4_t vecOffs = { 0, 2, 1, 3 }; + /* + * + * | 0 1 | => | 0 2 | + * | 2 3 | | 1 3 | + * + */ + uint32x4_t vecIn = vldrwq_u32((uint32_t const *)pDataSrc); + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs, vecIn); + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve( + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; + const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; + /* + * + * | 0 1 2 | | 0 3 6 | 4 x 32 flattened version | 0 3 6 1 | + * | 3 4 5 | => | 1 4 7 | => | 4 7 2 5 | + * | 6 7 8 | | 2 5 8 | (row major) | 8 . . . | + * + */ + uint32x4_t vecIn1 = vldrwq_u32((uint32_t const *) pDataSrc); + uint32x4_t vecIn2 = vldrwq_u32((uint32_t const *) &pDataSrc[4]); + + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs1, vecIn1); + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs2, vecIn2); + + pDataDest[8] = pDataSrc[8]; + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t * pDataSrc, uint32_t * pDataDest) +{ + /* + * 4x4 Matrix transposition + * is 4 x de-interleave operation + * + * 0 1 2 3 0 4 8 12 + * 4 5 6 7 1 5 9 13 + * 8 9 10 11 2 6 10 14 + * 12 13 14 15 3 7 11 15 + */ + + uint32x4x4_t vecIn; + + vecIn = vld4q((uint32_t const *) pDataSrc); + vstrwq(pDataDest, vecIn.val[0]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[1]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[2]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[3]); + + return (ARM_MATH_SUCCESS); +} + + +__STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve( + uint16_t srcRows, + uint16_t srcCols, + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + uint32x4_t vecOffs; + uint32_t i; + uint32_t blkCnt; + uint32_t const *pDataC; + uint32_t *pDataDestR; + uint32x4_t vecIn; + + vecOffs = vidupq_u32((uint32_t)0, 1); + vecOffs = vecOffs * srcCols; + + i = srcCols; + do + { + pDataC = (uint32_t const *) pDataSrc; + pDataDestR = pDataDest; + + blkCnt = srcRows >> 2; + while (blkCnt > 0U) + { + vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs); + vstrwq(pDataDestR, vecIn); + pDataDestR += 4; + pDataC = pDataC + srcCols * 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = srcRows & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs); + vstrwq_p(pDataDestR, vecIn, p0); + } + + pDataSrc += 1; + pDataDest += srcRows; + } + while (--i); + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_cmplx_trans_32bit( + uint16_t srcRows, + uint16_t srcCols, + uint32_t *pDataSrc, + uint16_t dstRows, + uint16_t dstCols, + uint32_t *pDataDest) +{ + uint32_t i; + uint32_t const *pDataC; + uint32_t *pDataRow; + uint32_t *pDataDestR, *pDataDestRow; + uint32x4_t vecOffsRef, vecOffsCur; + uint32_t blkCnt; + uint32x4_t vecIn; + +#ifdef ARM_MATH_MATRIX_CHECK + /* + * Check for matrix mismatch condition + */ + if ((srcRows != dstCols) || (srcCols != dstRows)) + { + /* + * Set status as ARM_MATH_SIZE_MISMATCH + */ + return ARM_MATH_SIZE_MISMATCH; + } +#else + (void)dstRows; + (void)dstCols; +#endif + + /* 2x2, 3x3 and 4x4 specialization to be added */ + + vecOffsRef[0] = 0; + vecOffsRef[1] = 1; + vecOffsRef[2] = srcCols << 1; + vecOffsRef[3] = (srcCols << 1) + 1; + + pDataRow = pDataSrc; + pDataDestRow = pDataDest; + i = srcCols; + do + { + pDataC = (uint32_t const *) pDataRow; + pDataDestR = pDataDestRow; + vecOffsCur = vecOffsRef; + + blkCnt = (srcRows * CMPLX_DIM) >> 2; + while (blkCnt > 0U) + { + vecIn = vldrwq_gather_shifted_offset(pDataC, vecOffsCur); + vstrwq(pDataDestR, vecIn); + pDataDestR += 4; + vecOffsCur = vaddq(vecOffsCur, (srcCols << 2)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (srcRows * CMPLX_DIM) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecIn = vldrwq_gather_shifted_offset(pDataC, vecOffsCur); + vstrwq_p(pDataDestR, vecIn, p0); + } + + pDataRow += CMPLX_DIM; + pDataDestRow += (srcRows * CMPLX_DIM); + } + while (--i); + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_trans_16bit_2x2(uint16_t * pDataSrc, uint16_t * pDataDest) +{ + pDataDest[0] = pDataSrc[0]; + pDataDest[3] = pDataSrc[3]; + pDataDest[2] = pDataSrc[1]; + pDataDest[1] = pDataSrc[2]; + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_trans_16bit_3x3_mve(uint16_t * pDataSrc, uint16_t * pDataDest) +{ + static const uint16_t stridesTr33[8] = { 0, 3, 6, 1, 4, 7, 2, 5 }; + uint16x8_t vecOffs1; + uint16x8_t vecIn1; + /* + * + * | 0 1 2 | | 0 3 6 | 8 x 16 flattened version | 0 3 6 1 4 7 2 5 | + * | 3 4 5 | => | 1 4 7 | => | 8 . . . . . . . | + * | 6 7 8 | | 2 5 8 | (row major) + * + */ + vecOffs1 = vldrhq_u16((uint16_t const *) stridesTr33); + vecIn1 = vldrhq_u16((uint16_t const *) pDataSrc); + + vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs1, vecIn1); + + pDataDest[8] = pDataSrc[8]; + + return (ARM_MATH_SUCCESS); +} + + +__STATIC_INLINE arm_status arm_mat_trans_16bit_4x4_mve(uint16_t * pDataSrc, uint16_t * pDataDest) +{ + static const uint16_t stridesTr44_1[8] = { 0, 4, 8, 12, 1, 5, 9, 13 }; + static const uint16_t stridesTr44_2[8] = { 2, 6, 10, 14, 3, 7, 11, 15 }; + uint16x8_t vecOffs1, vecOffs2; + uint16x8_t vecIn1, vecIn2; + uint16_t const * pDataSrcVec = (uint16_t const *) pDataSrc; + + /* + * 4x4 Matrix transposition + * + * | 0 1 2 3 | | 0 4 8 12 | 8 x 16 flattened version + * | 4 5 6 7 | => | 1 5 9 13 | => [0 4 8 12 1 5 9 13] + * | 8 9 10 11 | | 2 6 10 14 | [2 6 10 14 3 7 11 15] + * | 12 13 14 15 | | 3 7 11 15 | + */ + + vecOffs1 = vldrhq_u16((uint16_t const *) stridesTr44_1); + vecOffs2 = vldrhq_u16((uint16_t const *) stridesTr44_2); + vecIn1 = vldrhq_u16(pDataSrcVec); + pDataSrcVec += 8; + vecIn2 = vldrhq_u16(pDataSrcVec); + + vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs1, vecIn1); + vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs2, vecIn2); + + + return (ARM_MATH_SUCCESS); +} + + + +__STATIC_INLINE arm_status arm_mat_trans_16bit_generic( + uint16_t srcRows, + uint16_t srcCols, + uint16_t * pDataSrc, + uint16_t * pDataDest) +{ + uint16x8_t vecOffs; + uint32_t i; + uint32_t blkCnt; + uint16_t const *pDataC; + uint16_t *pDataDestR; + uint16x8_t vecIn; + + vecOffs = vidupq_u16((uint32_t)0, 1); + vecOffs = vecOffs * srcCols; + + i = srcCols; + while(i > 0U) + { + pDataC = (uint16_t const *) pDataSrc; + pDataDestR = pDataDest; + + blkCnt = srcRows >> 3; + while (blkCnt > 0U) + { + vecIn = vldrhq_gather_shifted_offset_u16(pDataC, vecOffs); + vstrhq_u16(pDataDestR, vecIn); + pDataDestR += 8; + pDataC = pDataC + srcCols * 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = srcRows & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecIn = vldrhq_gather_shifted_offset_u16(pDataC, vecOffs); + vstrhq_p_u16(pDataDestR, vecIn, p0); + } + pDataSrc += 1; + pDataDest += srcRows; + i--; + } + + return (ARM_MATH_SUCCESS); +} + + +__STATIC_INLINE arm_status arm_mat_cmplx_trans_16bit( + uint16_t srcRows, + uint16_t srcCols, + uint16_t *pDataSrc, + uint16_t dstRows, + uint16_t dstCols, + uint16_t *pDataDest) +{ + static const uint16_t loadCmplxCol[8] = { 0, 0, 1, 1, 2, 2, 3, 3 }; + int i; + uint16x8_t vecOffsRef, vecOffsCur; + uint16_t const *pDataC; + uint16_t *pDataRow; + uint16_t *pDataDestR, *pDataDestRow; + uint32_t blkCnt; + uint16x8_t vecIn; + +#ifdef ARM_MATH_MATRIX_CHECK + /* + * Check for matrix mismatch condition + */ + if ((srcRows != dstCols) || (srcCols != dstRows)) + { + /* + * Set status as ARM_MATH_SIZE_MISMATCH + */ + return ARM_MATH_SIZE_MISMATCH; + } +#else + (void)dstRows; + (void)dstCols; +#endif + + /* + * 2x2, 3x3 and 4x4 specialization to be added + */ + + + /* + * build [0, 1, 2xcol, 2xcol+1, 4xcol, 4xcol+1, 6xcol, 6xcol+1] + */ + vecOffsRef = vldrhq_u16((uint16_t const *) loadCmplxCol); + vecOffsRef = vmulq(vecOffsRef, (uint16_t) (srcCols * CMPLX_DIM)) + + viwdupq_u16((uint32_t)0, (uint16_t) 2, 1); + + pDataRow = pDataSrc; + pDataDestRow = pDataDest; + i = srcCols; + do + { + pDataC = (uint16_t const *) pDataRow; + pDataDestR = pDataDestRow; + vecOffsCur = vecOffsRef; + + blkCnt = (srcRows * CMPLX_DIM) >> 3; + while (blkCnt > 0U) + { + vecIn = vldrhq_gather_shifted_offset(pDataC, vecOffsCur); + vstrhq(pDataDestR, vecIn); + pDataDestR+= 8; // VEC_LANES_U16 + vecOffsCur = vaddq(vecOffsCur, (srcCols << 3)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (srcRows * CMPLX_DIM) & 0x7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecIn = vldrhq_gather_shifted_offset(pDataC, vecOffsCur); + vstrhq_p(pDataDestR, vecIn, p0); + } + + pDataRow += CMPLX_DIM; + pDataDestRow += (srcRows * CMPLX_DIM); + } + while (--i); + + return (ARM_MATH_SUCCESS); +} +#endif /* MVEF and MVEI */ + +/*************************************** + +Definitions available for MVEI only + +***************************************/ +#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_common_tables.h" + +#define MVE_ASRL_SAT16(acc, shift) ((sqrshrl_sat48(acc, -(32-shift)) >> 32) & 0xffffffff) +#define MVE_ASRL_SAT32(acc, shift) ((sqrshrl(acc, -(32-shift)) >> 32) & 0xffffffff) + + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) +__STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn) +{ + q63x2_t vecTmpLL; + q31x4_t vecTmp0, vecTmp1; + q31_t scale; + q63_t tmp64; + q31x4_t vecNrm, vecDst, vecIdx, vecSignBits; + + + vecSignBits = vclsq(vecIn); + vecSignBits = vbicq_n_s32(vecSignBits, 1); + /* + * in = in << no_of_sign_bits; + */ + vecNrm = vshlq(vecIn, vecSignBits); + /* + * index = in >> 24; + */ + vecIdx = vecNrm >> 24; + vecIdx = vecIdx << 1; + + vecTmp0 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, (uint32x4_t)vecIdx); + + vecIdx = vecIdx + 1; + + vecTmp1 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, (uint32x4_t)vecIdx); + + vecTmp1 = vqrdmulhq(vecTmp1, vecNrm); + vecTmp0 = vecTmp0 - vecTmp1; + vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0); + vecTmp1 = vqrdmulhq(vecNrm, vecTmp1); + vecTmp1 = vdupq_n_s32(0x18000000) - vecTmp1; + vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1); + vecTmpLL = vmullbq_int(vecNrm, vecTmp0); + + /* + * scale elements 0, 2 + */ + scale = 26 + (vecSignBits[0] >> 1); + tmp64 = asrl(vecTmpLL[0], scale); + vecDst[0] = (q31_t) tmp64; + + scale = 26 + (vecSignBits[2] >> 1); + tmp64 = asrl(vecTmpLL[1], scale); + vecDst[2] = (q31_t) tmp64; + + vecTmpLL = vmulltq_int(vecNrm, vecTmp0); + + /* + * scale elements 1, 3 + */ + scale = 26 + (vecSignBits[1] >> 1); + tmp64 = asrl(vecTmpLL[0], scale); + vecDst[1] = (q31_t) tmp64; + + scale = 26 + (vecSignBits[3] >> 1); + tmp64 = asrl(vecTmpLL[1], scale); + vecDst[3] = (q31_t) tmp64; + /* + * set negative values to 0 + */ + vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s32(vecIn, 0)); + + return vecDst; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE) +__STATIC_INLINE q15x8_t FAST_VSQRT_Q15(q15x8_t vecIn) +{ + q31x4_t vecTmpLev, vecTmpLodd, vecSignL; + q15x8_t vecTmp0, vecTmp1; + q15x8_t vecNrm, vecDst, vecIdx, vecSignBits; + + vecDst = vuninitializedq_s16(); + + vecSignBits = vclsq(vecIn); + vecSignBits = vbicq_n_s16(vecSignBits, 1); + /* + * in = in << no_of_sign_bits; + */ + vecNrm = vshlq(vecIn, vecSignBits); + + vecIdx = vecNrm >> 8; + vecIdx = vecIdx << 1; + + vecTmp0 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, (uint16x8_t)vecIdx); + + vecIdx = vecIdx + 1; + + vecTmp1 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, (uint16x8_t)vecIdx); + + vecTmp1 = vqrdmulhq(vecTmp1, vecNrm); + vecTmp0 = vecTmp0 - vecTmp1; + vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0); + vecTmp1 = vqrdmulhq(vecNrm, vecTmp1); + vecTmp1 = vdupq_n_s16(0x1800) - vecTmp1; + vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1); + + vecSignBits = vecSignBits >> 1; + + vecTmpLev = vmullbq_int(vecNrm, vecTmp0); + vecTmpLodd = vmulltq_int(vecNrm, vecTmp0); + + vecTmp0 = vecSignBits + 10; + /* + * negate sign to apply register based vshl + */ + vecTmp0 = -vecTmp0; + + /* + * shift even elements + */ + vecSignL = vmovlbq(vecTmp0); + vecTmpLev = vshlq(vecTmpLev, vecSignL); + /* + * shift odd elements + */ + vecSignL = vmovltq(vecTmp0); + vecTmpLodd = vshlq(vecTmpLodd, vecSignL); + /* + * merge and narrow odd and even parts + */ + vecDst = vmovnbq_s32(vecDst, vecTmpLev); + vecDst = vmovntq_s32(vecDst, vecTmpLodd); + /* + * set negative values to 0 + */ + vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s16(vecIn, 0)); + + return vecDst; +} +#endif + +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_math.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_math.h new file mode 100644 index 00000000..300c5cf4 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_math.h @@ -0,0 +1,236 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * \section intro Introduction + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M and Cortex-A processor + * based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filtering functions + * - Matrix functions + * - Transform functions + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * - Support Vector Machine functions (SVM) + * - Bayes classifier functions + * - Distance functions + * - Quaternion functions + * + * The library has generally separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * The library is providing vectorized versions of most algorthms for Helium + * and of most f32 algorithms for Neon. + * + * When using a vectorized version, provide a little bit of padding after the end of + * a buffer (3 words) because the vectorized code may read a little bit after the end + * of a buffer. You don't have to modify your buffers but just ensure that the + * end of buffer + padding is not outside of a memory region. + * + * \section using Using the Library + * + * The library is released in source form. It is strongly advised to compile the library using -Ofast to + * have the best performances. + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file. If you don't want to include everything, you can also rely + * on headers in Include/dsp folder and use only what you need. + * + * \section example Examples + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * \section toolchain Toolchain Support + * + * The library is now tested on Fast Models building with cmake. + * Core M0, M4, M7, M33, M55, A32 are tested. + * + * + * \section preprocessor Preprocessor Macros + * + * Each library project have different preprocessor macros. + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_LOOPUNROLL: + * + * Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions + * + * - ARM_MATH_NEON: + * + * Define macro ARM_MATH_NEON to enable Neon versions of the DSP functions. + * It is not enabled by default when Neon is available because performances are + * dependent on the compiler and target architecture. + * + * - ARM_MATH_NEON_EXPERIMENTAL: + * + * Define macro ARM_MATH_NEON_EXPERIMENTAL to enable experimental Neon versions of + * of some DSP functions. Experimental Neon versions currently do not have better + * performances than the scalar versions. + * + * - ARM_MATH_HELIUM: + * + * It implies the flags ARM_MATH_MVEF and ARM_MATH_MVEI and ARM_MATH_MVE_FLOAT16. + * + * - ARM_MATH_HELIUM_EXPERIMENTAL: + * + * Only taken into account when ARM_MATH_MVEF, ARM_MATH_MVEI or ARM_MATH_MVE_FLOAT16 are defined. + * Enable some vector versions which may have worse performance than scalar + * depending on the core / compiler configuration. + * + * - ARM_MATH_MVEF: + * + * Select Helium versions of the f32 algorithms. + * It implies ARM_MATH_FLOAT16 and ARM_MATH_MVEI. + * + * - ARM_MATH_MVEI: + * + * Select Helium versions of the int and fixed point algorithms. + * + * - ARM_MATH_MVE_FLOAT16: + * + * MVE Float16 implementations of some algorithms (Requires MVE extension). + * + * - DISABLEFLOAT16: + * + * Disable float16 algorithms when __fp16 is not supported for a + * specific compiler / core configuration. + * This is only valid for scalar. When vector architecture is + * supporting f16 then it can't be disabled. + * + * - ARM_MATH_AUTOVECTORIZE: + * + * With Helium or Neon, disable the use of vectorized code with C intrinsics + * and use pure C instead. The vectorization is then done by the compiler. + * + *
+ * \section pack CMSIS-DSP in ARM::CMSIS Pack + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |---------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP\\Include | DSP_Lib include files for using and building the lib + * |\b CMSIS\\DSP\\PrivateInclude | DSP_Lib private include files for building the lib | + * |\b CMSIS\\DSP\\Lib | DSP_Lib binaries | + * |\b CMSIS\\DSP\\Source | DSP_Lib source files | + * + *
+ * \section rev Revision History of CMSIS-DSP + * Please refer to \ref ChangeLog_pg. + */ + + + + + + + + + + + +/** + * @defgroup groupExamples Examples + */ + + + + + +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/basic_math_functions.h" +#include "dsp/interpolation_functions.h" +#include "dsp/bayes_functions.h" +#include "dsp/matrix_functions.h" +#include "dsp/complex_math_functions.h" +#include "dsp/statistics_functions.h" +#include "dsp/controller_functions.h" +#include "dsp/support_functions.h" +#include "dsp/distance_functions.h" +#include "dsp/svm_functions.h" +#include "dsp/fast_math_functions.h" +#include "dsp/transform_functions.h" +#include "dsp/filtering_functions.h" +#include "dsp/quaternion_math_functions.h" + + + +#ifdef __cplusplus +extern "C" +{ +#endif + + + + +//#define TABLE_SPACING_Q31 0x400000 +//#define TABLE_SPACING_Q15 0x80 + + + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_math_f16.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_math_f16.h new file mode 100644 index 00000000..daf0c53d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_math_f16.h @@ -0,0 +1,59 @@ +/****************************************************************************** + * @file arm_math_f16.h + * @brief Public header file for f16 function of the CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_MATH_F16_H +#define _ARM_MATH_F16_H + +#include "arm_math.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "arm_math_types_f16.h" +#include "dsp/none.h" +#include "dsp/utils.h" +#include "dsp/basic_math_functions_f16.h" +#include "dsp/interpolation_functions_f16.h" +#include "dsp/bayes_functions_f16.h" +#include "dsp/matrix_functions_f16.h" +#include "dsp/complex_math_functions_f16.h" +#include "dsp/statistics_functions_f16.h" +#include "dsp/controller_functions_f16.h" +#include "dsp/support_functions_f16.h" +#include "dsp/distance_functions_f16.h" +#include "dsp/svm_functions_f16.h" +#include "dsp/fast_math_functions_f16.h" +#include "dsp/transform_functions_f16.h" +#include "dsp/filtering_functions_f16.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _ARM_MATH_F16_H */ + + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_math_memory.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_math_memory.h new file mode 100644 index 00000000..7bd83dc2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_math_memory.h @@ -0,0 +1,206 @@ +/****************************************************************************** + * @file arm_math_memory.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_MATH_MEMORY_H_ + +#define _ARM_MATH_MEMORY_H_ + +#include "arm_math_types.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + @brief definition to read/write two 16 bit values. + @deprecated + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __un(aligned) int32_t +#elif defined(_MSC_VER ) + #define __SIMD32_TYPE int32_t +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr)) +#define __SIMD64(addr) (*( int64_t **) & (addr)) + + +/* SIMD replacement */ + + +/** + @brief Read 2 Q15 from Q15 pointer. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2 ( + q15_t const * pQ15) +{ + q31_t val; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, pQ15, 4); +#else + val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ; +#endif + + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +#define read_q15x2_ia(pQ15) read_q15x2((*(pQ15) += 2) - 2) + +/** + @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +#define read_q15x2_da(pQ15) read_q15x2((*(pQ15) -= 2) + 2) + +/** + @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2_ia ( + q15_t ** pQ15, + q31_t value) +{ + q31_t val = value; +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (*pQ15, &val, 4); +#else + (*pQ15)[0] = (q15_t)(val & 0x0FFFF); + (*pQ15)[1] = (q15_t)((val >> 16) & 0x0FFFF); +#endif + + *pQ15 += 2; +} + +/** + @brief Write 2 Q15 to Q15 pointer. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2 ( + q15_t * pQ15, + q31_t value) +{ + q31_t val = value; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (pQ15, &val, 4); +#else + pQ15[0] = (q15_t)(val & 0x0FFFF); + pQ15[1] = (q15_t)(val >> 16); +#endif +} + + +/** + @brief Read 4 Q7 from Q7 pointer + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4 ( + q7_t const * pQ7) +{ + q31_t val; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, pQ7, 4); +#else + val =((pQ7[3] & 0x0FF) << 24) | ((pQ7[2] & 0x0FF) << 16) | ((pQ7[1] & 0x0FF) << 8) | (pQ7[0] & 0x0FF); +#endif + return (val); +} + +/** + @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +#define read_q7x4_ia(pQ7) read_q7x4((*(pQ7) += 4) - 4) + +/** + @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +#define read_q7x4_da(pQ7) read_q7x4((*(pQ7) -= 4) + 4) + +/** + @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q7x4_ia ( + q7_t ** pQ7, + q31_t value) +{ + q31_t val = value; +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (*pQ7, &val, 4); +#else + (*pQ7)[0] = (q7_t)(val & 0x0FF); + (*pQ7)[1] = (q7_t)((val >> 8) & 0x0FF); + (*pQ7)[2] = (q7_t)((val >> 16) & 0x0FF); + (*pQ7)[3] = (q7_t)((val >> 24) & 0x0FF); + +#endif + *pQ7 += 4; +} + + +#ifdef __cplusplus +} +#endif + +#endif /*ifndef _ARM_MATH_MEMORY_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_math_types.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_math_types.h new file mode 100644 index 00000000..c615e667 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_math_types.h @@ -0,0 +1,616 @@ +/****************************************************************************** + * @file arm_math_types.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_MATH_TYPES_H_ + +#define _ARM_MATH_TYPES_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __APPLE_CC__ ) + #pragma GCC diagnostic ignored "-Wold-style-cast" + +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wsign-conversion" + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + + +/* Included for instrinsics definitions */ +#if defined (_MSC_VER ) +#include +#define __STATIC_FORCEINLINE static __forceinline +#define __STATIC_INLINE static __inline +#define __ALIGNED(x) __declspec(align(x)) +#elif defined ( __APPLE_CC__ ) +#include +#define __ALIGNED(x) __attribute__((aligned(x))) +#define __STATIC_FORCEINLINE static inline __attribute__((always_inline)) +#define __STATIC_INLINE static inline +#elif defined (__GNUC_PYTHON__) +#include +#define __ALIGNED(x) __attribute__((aligned(x))) +#define __STATIC_FORCEINLINE static inline __attribute__((always_inline)) +#define __STATIC_INLINE static inline + +#else +#include "cmsis_compiler.h" +#endif + + + +#include +#include +#include +#include + +/* evaluate ARM DSP feature */ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + #define ARM_MATH_DSP 1 +#endif + +#if defined(ARM_MATH_NEON) + #if defined(_MSC_VER) && defined(_M_ARM64EC) + #include + #else + #include + #endif + #if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && __ARM_FEATURE_FP16_VECTOR_ARITHMETIC + #if !defined(ARM_MATH_NEON_FLOAT16) + #define ARM_MATH_NEON_FLOAT16 + #endif + #endif +#endif + +#if !defined(ARM_MATH_AUTOVECTORIZE) + + +#if defined(__ARM_FEATURE_MVE) +#if __ARM_FEATURE_MVE + #if !defined(ARM_MATH_MVEI) + #define ARM_MATH_MVEI + #endif +#endif + +#if (__ARM_FEATURE_MVE & 2) + #if !defined(ARM_MATH_MVEF) + #define ARM_MATH_MVEF + #endif + #if !defined(ARM_MATH_MVE_FLOAT16) + #define ARM_MATH_MVE_FLOAT16 + #endif +#endif + +#endif /*defined(__ARM_FEATURE_MVE)*/ +#endif /*!defined(ARM_MATH_AUTOVECTORIZE)*/ + + +#if defined (ARM_MATH_HELIUM) + #if !defined(ARM_MATH_MVEF) + #define ARM_MATH_MVEF + #endif + + #if !defined(ARM_MATH_MVEI) + #define ARM_MATH_MVEI + #endif + + #if !defined(ARM_MATH_MVE_FLOAT16) + #define ARM_MATH_MVE_FLOAT16 + #endif +#endif + + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __APPLE_CC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT +#endif + + + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __APPLE_CC__ ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + +#ifdef __cplusplus +} +#endif + +#if defined(__ARM_FEATURE_MVE) && __ARM_FEATURE_MVE +#include +#endif + +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ +#if !defined(__ICCARM__) || !(__ARM_FEATURE_MVE & 2) + typedef float float32_t; +#endif + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief vector types + */ +#if defined(ARM_MATH_NEON) || (defined (ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)) + /** + * @brief 64-bit fractional 128-bit vector data type in 1.63 format + */ + typedef int64x2_t q63x2_t; + + /** + * @brief 32-bit fractional 128-bit vector data type in 1.31 format. + */ + typedef int32x4_t q31x4_t; + + /** + * @brief 16-bit fractional 128-bit vector data type with 16-bit alignment in 1.15 format. + */ + typedef __ALIGNED(2) int16x8_t q15x8_t; + + /** + * @brief 8-bit fractional 128-bit vector data type with 8-bit alignment in 1.7 format. + */ + typedef __ALIGNED(1) int8x16_t q7x16_t; + + /** + * @brief 32-bit fractional 128-bit vector pair data type in 1.31 format. + */ + typedef int32x4x2_t q31x4x2_t; + + /** + * @brief 32-bit fractional 128-bit vector quadruplet data type in 1.31 format. + */ + typedef int32x4x4_t q31x4x4_t; + + /** + * @brief 16-bit fractional 128-bit vector pair data type in 1.15 format. + */ + typedef int16x8x2_t q15x8x2_t; + + /** + * @brief 16-bit fractional 128-bit vector quadruplet data type in 1.15 format. + */ + typedef int16x8x4_t q15x8x4_t; + + /** + * @brief 8-bit fractional 128-bit vector pair data type in 1.7 format. + */ + typedef int8x16x2_t q7x16x2_t; + + /** + * @brief 8-bit fractional 128-bit vector quadruplet data type in 1.7 format. + */ + typedef int8x16x4_t q7x16x4_t; + + /** + * @brief 32-bit fractional data type in 9.23 format. + */ + typedef int32_t q23_t; + + /** + * @brief 32-bit fractional 128-bit vector data type in 9.23 format. + */ + typedef int32x4_t q23x4_t; + + /** + * @brief 64-bit status 128-bit vector data type. + */ + typedef int64x2_t status64x2_t; + + /** + * @brief 32-bit status 128-bit vector data type. + */ + typedef int32x4_t status32x4_t; + + /** + * @brief 16-bit status 128-bit vector data type. + */ + typedef int16x8_t status16x8_t; + + /** + * @brief 8-bit status 128-bit vector data type. + */ + typedef int8x16_t status8x16_t; + + +#endif + +#if defined(ARM_MATH_NEON) || (defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)) /* floating point vector*/ + /** + * @brief 32-bit floating-point 128-bit vector type + */ + typedef float32x4_t f32x4_t; + + /** + * @brief 32-bit floating-point 128-bit vector pair data type + */ + typedef float32x4x2_t f32x4x2_t; + + /** + * @brief 32-bit floating-point 128-bit vector quadruplet data type + */ + typedef float32x4x4_t f32x4x4_t; + + /** + * @brief 32-bit ubiquitous 128-bit vector data type + */ + typedef union _any32x4_t + { + float32x4_t f; + int32x4_t i; + } any32x4_t; + +#endif + +#if defined(ARM_MATH_NEON) + /** + * @brief 32-bit fractional 64-bit vector data type in 1.31 format. + */ + typedef int32x2_t q31x2_t; + + /** + * @brief 16-bit fractional 64-bit vector data type in 1.15 format. + */ + typedef __ALIGNED(2) int16x4_t q15x4_t; + + /** + * @brief 8-bit fractional 64-bit vector data type in 1.7 format. + */ + typedef __ALIGNED(1) int8x8_t q7x8_t; + + /** + * @brief 32-bit float 64-bit vector data type. + */ + typedef float32x2_t f32x2_t; + + /** + * @brief 32-bit floating-point 128-bit vector triplet data type + */ + typedef float32x4x3_t f32x4x3_t; + + + /** + * @brief 32-bit fractional 128-bit vector triplet data type in 1.31 format + */ + typedef int32x4x3_t q31x4x3_t; + + /** + * @brief 16-bit fractional 128-bit vector triplet data type in 1.15 format + */ + typedef int16x8x3_t q15x8x3_t; + + /** + * @brief 8-bit fractional 128-bit vector triplet data type in 1.7 format + */ + typedef int8x16x3_t q7x16x3_t; + + /** + * @brief 32-bit floating-point 64-bit vector pair data type + */ + typedef float32x2x2_t f32x2x2_t; + + /** + * @brief 32-bit floating-point 64-bit vector triplet data type + */ + typedef float32x2x3_t f32x2x3_t; + + /** + * @brief 32-bit floating-point 64-bit vector quadruplet data type + */ + typedef float32x2x4_t f32x2x4_t; + + + /** + * @brief 32-bit fractional 64-bit vector pair data type in 1.31 format + */ + typedef int32x2x2_t q31x2x2_t; + + /** + * @brief 32-bit fractional 64-bit vector triplet data type in 1.31 format + */ + typedef int32x2x3_t q31x2x3_t; + + /** + * @brief 32-bit fractional 64-bit vector quadruplet data type in 1.31 format + */ + typedef int32x4x3_t q31x2x4_t; + + /** + * @brief 16-bit fractional 64-bit vector pair data type in 1.15 format + */ + typedef int16x4x2_t q15x4x2_t; + + /** + * @brief 16-bit fractional 64-bit vector triplet data type in 1.15 format + */ + typedef int16x4x2_t q15x4x3_t; + + /** + * @brief 16-bit fractional 64-bit vector quadruplet data type in 1.15 format + */ + typedef int16x4x3_t q15x4x4_t; + + /** + * @brief 8-bit fractional 64-bit vector pair data type in 1.7 format + */ + typedef int8x8x2_t q7x8x2_t; + + /** + * @brief 8-bit fractional 64-bit vector triplet data type in 1.7 format + */ + typedef int8x8x3_t q7x8x3_t; + + /** + * @brief 8-bit fractional 64-bit vector quadruplet data type in 1.7 format + */ + typedef int8x8x4_t q7x8x4_t; + + /** + * @brief 32-bit ubiquitous 64-bit vector data type + */ + typedef union _any32x2_t + { + float32x2_t f; + int32x2_t i; + } any32x2_t; + + + /** + * @brief 32-bit status 64-bit vector data type. + */ + typedef int32x4_t status32x2_t; + + /** + * @brief 16-bit status 64-bit vector data type. + */ + typedef int16x8_t status16x4_t; + + /** + * @brief 8-bit status 64-bit vector data type. + */ + typedef int8x16_t status8x8_t; + +#endif + + + + + +#define F64_MAX ((float64_t)DBL_MAX) +#define F32_MAX ((float32_t)FLT_MAX) + + + +#define F64_MIN (-DBL_MAX) +#define F32_MIN (-FLT_MAX) + + + +#define F64_ABSMAX ((float64_t)DBL_MAX) +#define F32_ABSMAX ((float32_t)FLT_MAX) + + + +#define F64_ABSMIN ((float64_t)0.0) +#define F32_ABSMIN ((float32_t)0.0) + + +#define Q31_MAX ((q31_t)(0x7FFFFFFFL)) +#define Q15_MAX ((q15_t)(0x7FFF)) +#define Q7_MAX ((q7_t)(0x7F)) +#define Q31_MIN ((q31_t)(0x80000000L)) +#define Q15_MIN ((q15_t)(0x8000)) +#define Q7_MIN ((q7_t)(0x80)) + +#define Q31_ABSMAX ((q31_t)(0x7FFFFFFFL)) +#define Q15_ABSMAX ((q15_t)(0x7FFF)) +#define Q7_ABSMAX ((q7_t)(0x7F)) +#define Q31_ABSMIN ((q31_t)0) +#define Q15_ABSMIN ((q15_t)0) +#define Q7_ABSMIN ((q7_t)0) + + /* Dimension C vector space */ + #define CMPLX_DIM 2 + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */ + ARM_MATH_TEST_FAILURE = -6, /**< Test Failed */ + ARM_MATH_DECOMPOSITION_FAILURE = -7 /**< Decomposition Failed */ + } arm_status; + + +#ifdef __cplusplus +} +#endif + +#endif /*ifndef _ARM_MATH_TYPES_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_math_types_f16.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_math_types_f16.h new file mode 100644 index 00000000..744dc38f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_math_types_f16.h @@ -0,0 +1,163 @@ +/****************************************************************************** + * @file arm_math_types_f16.h + * @brief Public header file for f16 function of the CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_MATH_TYPES_F16_H +#define _ARM_MATH_TYPES_F16_H + +#include "arm_math_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if !defined( __CC_ARM ) + +/** + * @brief 16-bit floating-point type definition. + * This is already defined in arm_mve.h + * + * This is not fully supported on ARM AC5. + */ + +/* + +Check if the type __fp16 is available. +If it is not available, f16 version of the kernels +won't be built. + +*/ +#if !(__ARM_FEATURE_MVE & 2) + #if !defined(DISABLEFLOAT16) + #if defined(__ARM_FP16_FORMAT_IEEE) || defined(__ARM_FP16_FORMAT_ALTERNATIVE) + typedef __fp16 float16_t; + #define ARM_FLOAT16_SUPPORTED + #endif + #endif +#else + /* When Vector float16, this flag is always defined and can't be disabled */ + #define ARM_FLOAT16_SUPPORTED +#endif + +#if defined(ARM_MATH_NEON) || (defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)) /* floating point vector*/ + +#if defined(ARM_MATH_MVE_FLOAT16) || defined(ARM_MATH_NEON_FLOAT16) + + /** + * @brief 16-bit floating-point 128-bit vector data type + */ + typedef __ALIGNED(2) float16x8_t f16x8_t; + + /** + * @brief 16-bit floating-point 128-bit vector pair data type + */ + typedef float16x8x2_t f16x8x2_t; + + /** + * @brief 16-bit floating-point 128-bit vector quadruplet data type + */ + typedef float16x8x4_t f16x8x4_t; + + /** + * @brief 16-bit ubiquitous 128-bit vector data type + */ + typedef union _any16x8_t + { + float16x8_t f; + int16x8_t i; + } any16x8_t; +#endif + +#endif + +#if defined(ARM_MATH_NEON) + + +#if defined(ARM_MATH_NEON_FLOAT16) + /** + * @brief 16-bit float 64-bit vector data type. + */ + typedef __ALIGNED(2) float16x4_t f16x4_t; + + /** + * @brief 16-bit floating-point 128-bit vector triplet data type + */ + typedef float16x8x3_t f16x8x3_t; + + /** + * @brief 16-bit floating-point 64-bit vector pair data type + */ + typedef float16x4x2_t f16x4x2_t; + + /** + * @brief 16-bit floating-point 64-bit vector triplet data type + */ + typedef float16x4x3_t f16x4x3_t; + + /** + * @brief 16-bit floating-point 64-bit vector quadruplet data type + */ + typedef float16x4x4_t f16x4x4_t; + + /** + * @brief 16-bit ubiquitous 64-bit vector data type + */ + typedef union _any16x4_t + { + float16x4_t f; + int16x4_t i; + } any16x4_t; +#endif + +#endif + + + +#if defined(ARM_FLOAT16_SUPPORTED) + +#if defined(__ICCARM__) + +#define F16INFINITY ((float16_t) INFINITY) + +#else + +#define F16INFINITY ((float16_t)__builtin_inf()) + +#endif + +#define F16_MAX ((float16_t)__FLT16_MAX__) +#define F16_MIN (-(_Float16)__FLT16_MAX__) + +#define F16_ABSMAX ((float16_t)__FLT16_MAX__) +#define F16_ABSMIN ((float16_t)0.0f16) + +#endif /* ARM_FLOAT16_SUPPORTED*/ +#endif /* !defined( __CC_ARM ) */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ARM_MATH_F16_H */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_mve_tables.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_mve_tables.h new file mode 100644 index 00000000..c4f8bf08 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_mve_tables.h @@ -0,0 +1,231 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mve_tables.h + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * used for MVE implementation only + * + * @version V1.10.0 + * @date 04 October 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #ifndef _ARM_MVE_TABLES_H + #define _ARM_MVE_TABLES_H + +#include "arm_math_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2]; +extern float32_t rearranged_twiddle_stride1_16_f32[8]; +extern float32_t rearranged_twiddle_stride2_16_f32[8]; +extern float32_t rearranged_twiddle_stride3_16_f32[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3]; +extern float32_t rearranged_twiddle_stride1_64_f32[40]; +extern float32_t rearranged_twiddle_stride2_64_f32[40]; +extern float32_t rearranged_twiddle_stride3_64_f32[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4]; +extern float32_t rearranged_twiddle_stride1_256_f32[168]; +extern float32_t rearranged_twiddle_stride2_256_f32[168]; +extern float32_t rearranged_twiddle_stride3_256_f32[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5]; +extern float32_t rearranged_twiddle_stride1_1024_f32[680]; +extern float32_t rearranged_twiddle_stride2_1024_f32[680]; +extern float32_t rearranged_twiddle_stride3_1024_f32[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) || defined(ARM_TABLE_TWIDDLECOEF_F32_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6]; +extern float32_t rearranged_twiddle_stride1_4096_f32[2728]; +extern float32_t rearranged_twiddle_stride2_4096_f32[2728]; +extern float32_t rearranged_twiddle_stride3_4096_f32[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2]; +extern q31_t rearranged_twiddle_stride1_16_q31[8]; +extern q31_t rearranged_twiddle_stride2_16_q31[8]; +extern q31_t rearranged_twiddle_stride3_16_q31[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3]; +extern q31_t rearranged_twiddle_stride1_64_q31[40]; +extern q31_t rearranged_twiddle_stride2_64_q31[40]; +extern q31_t rearranged_twiddle_stride3_64_q31[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4]; +extern q31_t rearranged_twiddle_stride1_256_q31[168]; +extern q31_t rearranged_twiddle_stride2_256_q31[168]; +extern q31_t rearranged_twiddle_stride3_256_q31[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5]; +extern q31_t rearranged_twiddle_stride1_1024_q31[680]; +extern q31_t rearranged_twiddle_stride2_1024_q31[680]; +extern q31_t rearranged_twiddle_stride3_1024_q31[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q31_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6]; +extern q31_t rearranged_twiddle_stride1_4096_q31[2728]; +extern q31_t rearranged_twiddle_stride2_4096_q31[2728]; +extern q31_t rearranged_twiddle_stride3_4096_q31[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEI) */ + + + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2]; +extern q15_t rearranged_twiddle_stride1_16_q15[8]; +extern q15_t rearranged_twiddle_stride2_16_q15[8]; +extern q15_t rearranged_twiddle_stride3_16_q15[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3]; +extern q15_t rearranged_twiddle_stride1_64_q15[40]; +extern q15_t rearranged_twiddle_stride2_64_q15[40]; +extern q15_t rearranged_twiddle_stride3_64_q15[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4]; +extern q15_t rearranged_twiddle_stride1_256_q15[168]; +extern q15_t rearranged_twiddle_stride2_256_q15[168]; +extern q15_t rearranged_twiddle_stride3_256_q15[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5]; +extern q15_t rearranged_twiddle_stride1_1024_q15[680]; +extern q15_t rearranged_twiddle_stride2_1024_q15[680]; +extern q15_t rearranged_twiddle_stride3_1024_q15[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q15_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6]; +extern q15_t rearranged_twiddle_stride1_4096_q15[2728]; +extern q15_t rearranged_twiddle_stride2_4096_q15[2728]; +extern q15_t rearranged_twiddle_stride3_4096_q15[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEI) */ + + + +#ifdef __cplusplus +} +#endif + +#endif /*_ARM_MVE_TABLES_H*/ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_mve_tables_f16.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_mve_tables_f16.h new file mode 100644 index 00000000..dc952030 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_mve_tables_f16.h @@ -0,0 +1,109 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mve_tables_f16.h + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * used for MVE implementation only + * + * @version V1.10.0 + * @date 04 October 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #ifndef _ARM_MVE_TABLES_F16_H + #define _ARM_MVE_TABLES_F16_H + +#include "arm_math_types_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_16) || defined(ARM_TABLE_TWIDDLECOEF_F16_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f16[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f16[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f16[2]; +extern float16_t rearranged_twiddle_stride1_16_f16[8]; +extern float16_t rearranged_twiddle_stride2_16_f16[8]; +extern float16_t rearranged_twiddle_stride3_16_f16[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_64) || defined(ARM_TABLE_TWIDDLECOEF_F16_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f16[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f16[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f16[3]; +extern float16_t rearranged_twiddle_stride1_64_f16[40]; +extern float16_t rearranged_twiddle_stride2_64_f16[40]; +extern float16_t rearranged_twiddle_stride3_64_f16[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_256) || defined(ARM_TABLE_TWIDDLECOEF_F16_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f16[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f16[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f16[4]; +extern float16_t rearranged_twiddle_stride1_256_f16[168]; +extern float16_t rearranged_twiddle_stride2_256_f16[168]; +extern float16_t rearranged_twiddle_stride3_256_f16[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_1024) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f16[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f16[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f16[5]; +extern float16_t rearranged_twiddle_stride1_1024_f16[680]; +extern float16_t rearranged_twiddle_stride2_1024_f16[680]; +extern float16_t rearranged_twiddle_stride3_1024_f16[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) || defined(ARM_TABLE_TWIDDLECOEF_F16_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f16[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f16[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f16[6]; +extern float16_t rearranged_twiddle_stride1_4096_f16[2728]; +extern float16_t rearranged_twiddle_stride2_4096_f16[2728]; +extern float16_t rearranged_twiddle_stride3_4096_f16[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + + +#ifdef __cplusplus +} +#endif + +#endif /*_ARM_MVE_TABLES_F16_H*/ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_vec_math.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_vec_math.h new file mode 100644 index 00000000..d9134c54 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_vec_math.h @@ -0,0 +1,373 @@ +/****************************************************************************** + * @file arm_vec_math.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_VEC_MATH_H +#define _ARM_VEC_MATH_H + +#include "arm_math_types.h" +#include "arm_common_tables.h" +#include "arm_helium_utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define INV_NEWTON_INIT_F32 0x7EF127EA + +static const float32_t __logf_rng_f32=0.693147180f; + + +/* fast inverse approximation (3x newton) */ +__STATIC_INLINE f32x4_t vrecip_medprec_f32( + f32x4_t x) +{ + q31x4_t m; + f32x4_t b; + any32x4_t xinv; + f32x4_t ax = vabsq(x); + + xinv.f = ax; + m = 0x3F800000 - (xinv.i & 0x7F800000); + xinv.i = xinv.i + m; + xinv.f = 1.41176471f - 0.47058824f * xinv.f; + xinv.i = xinv.i + m; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f)); + /* + * restore sign + */ + xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f)); + + return xinv.f; +} + +/* fast inverse approximation (4x newton) */ +__STATIC_INLINE f32x4_t vrecip_hiprec_f32( + f32x4_t x) +{ + q31x4_t m; + f32x4_t b; + any32x4_t xinv; + f32x4_t ax = vabsq(x); + + xinv.f = ax; + + m = 0x3F800000 - (xinv.i & 0x7F800000); + xinv.i = xinv.i + m; + xinv.f = 1.41176471f - 0.47058824f * xinv.f; + xinv.i = xinv.i + m; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f)); + /* + * restore sign + */ + xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f)); + + return xinv.f; +} + +__STATIC_INLINE f32x4_t vdiv_f32( + f32x4_t num, f32x4_t den) +{ + return vmulq(num, vrecip_hiprec_f32(den)); +} + +/** + @brief Single-precision taylor dev. + @param[in] x f32 quad vector input + @param[in] coeffs f32 quad vector coeffs + @return destination f32 quad vector + */ + +__STATIC_INLINE f32x4_t vtaylor_polyq_f32( + f32x4_t x, + const float32_t * coeffs) +{ + f32x4_t A = vfmasq(vdupq_n_f32(coeffs[4]), x, coeffs[0]); + f32x4_t B = vfmasq(vdupq_n_f32(coeffs[6]), x, coeffs[2]); + f32x4_t C = vfmasq(vdupq_n_f32(coeffs[5]), x, coeffs[1]); + f32x4_t D = vfmasq(vdupq_n_f32(coeffs[7]), x, coeffs[3]); + f32x4_t x2 = vmulq(x, x); + f32x4_t x4 = vmulq(x2, x2); + f32x4_t res = vfmaq(vfmaq_f32(A, B, x2), vfmaq_f32(C, D, x2), x4); + + return res; +} + +__STATIC_INLINE f32x4_t vmant_exp_f32( + f32x4_t x, + int32x4_t * e) +{ + any32x4_t r; + int32x4_t n; + + r.f = x; + n = r.i >> 23; + n = n - 127; + r.i = r.i - (n << 23); + + *e = n; + return r.f; +} + + +__STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn) +{ + q31x4_t vecExpUnBiased; + f32x4_t vecTmpFlt0, vecTmpFlt1; + f32x4_t vecAcc0, vecAcc1, vecAcc2, vecAcc3; + f32x4_t vecExpUnBiasedFlt; + + /* + * extract exponent + */ + vecTmpFlt1 = vmant_exp_f32(vecIn, &vecExpUnBiased); + + vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1; + /* + * a = (__logf_lut_f32[4] * r.f) + (__logf_lut_f32[0]); + */ + vecAcc0 = vdupq_n_f32(__logf_lut_f32[0]); + vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f32[4]); + /* + * b = (__logf_lut_f32[6] * r.f) + (__logf_lut_f32[2]); + */ + vecAcc1 = vdupq_n_f32(__logf_lut_f32[2]); + vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f32[6]); + /* + * c = (__logf_lut_f32[5] * r.f) + (__logf_lut_f32[1]); + */ + vecAcc2 = vdupq_n_f32(__logf_lut_f32[1]); + vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f32[5]); + /* + * d = (__logf_lut_f32[7] * r.f) + (__logf_lut_f32[3]); + */ + vecAcc3 = vdupq_n_f32(__logf_lut_f32[3]); + vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f32[7]); + /* + * a = a + b * xx; + */ + vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0); + /* + * c = c + d * xx; + */ + vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0); + /* + * xx = xx * xx; + */ + vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0; + vecExpUnBiasedFlt = vcvtq_f32_s32(vecExpUnBiased); + /* + * r.f = a + c * xx; + */ + vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0); + /* + * add exponent + * r.f = r.f + ((float32_t) m) * __logf_rng_f32; + */ + vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f32); + // set log0 down to -inf + vecAcc0 = vdupq_m(vecAcc0, -INFINITY, vcmpeqq(vecIn, 0.0f)); + return vecAcc0; +} + +__STATIC_INLINE f32x4_t vexpq_f32( + f32x4_t x) +{ + // Perform range reduction [-log(2),log(2)] + int32x4_t m = vcvtq_s32_f32(vmulq_n_f32(x, 1.4426950408f)); + f32x4_t val = vfmsq_f32(x, vcvtq_f32_s32(m), vdupq_n_f32(0.6931471805f)); + + // Polynomial Approximation + f32x4_t poly = vtaylor_polyq_f32(val, exp_tab); + + // Reconstruct + poly = (f32x4_t) (vqaddq_s32((q31x4_t) (poly), vqshlq_n_s32(m, 23))); + + poly = vdupq_m(poly, 0.0f, vcmpltq_n_s32(m, -126)); + return poly; +} + +__STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb) +{ + f32x4_t r = x; + nb--; + while (nb > 0) { + r = vmulq(r, x); + nb--; + } + return (r); +} + +__STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn) +{ + f32x4_t vecSx, vecW, vecTmp; + any32x4_t v; + + vecSx = vabsq(vecIn); + + v.f = vecIn; + v.i = vsubq(vdupq_n_s32(INV_NEWTON_INIT_F32), v.i); + + vecW = vmulq(vecSx, v.f); + + // v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w))))))); + vecTmp = vsubq(vdupq_n_f32(8.0f), vecW); + vecTmp = vfmasq(vecW, vecTmp, -28.0f); + vecTmp = vfmasq(vecW, vecTmp, 56.0f); + vecTmp = vfmasq(vecW, vecTmp, -70.0f); + vecTmp = vfmasq(vecW, vecTmp, 56.0f); + vecTmp = vfmasq(vecW, vecTmp, -28.0f); + vecTmp = vfmasq(vecW, vecTmp, 8.0f); + v.f = vmulq(v.f, vecTmp); + + v.f = vdupq_m(v.f, INFINITY, vcmpeqq(vecIn, 0.0f)); + /* + * restore sign + */ + v.f = vnegq_m(v.f, v.f, vcmpltq(vecIn, 0.0f)); + return v.f; +} + +__STATIC_INLINE f32x4_t vtanhq_f32( + f32x4_t val) +{ + f32x4_t x = + vminnmq_f32(vmaxnmq_f32(val, vdupq_n_f32(-10.f)), vdupq_n_f32(10.0f)); + f32x4_t exp2x = vexpq_f32(vmulq_n_f32(x, 2.f)); + f32x4_t num = vsubq_n_f32(exp2x, 1.f); + f32x4_t den = vaddq_n_f32(exp2x, 1.f); + f32x4_t tanh = vmulq_f32(num, vrecip_f32(den)); + return tanh; +} + +__STATIC_INLINE f32x4_t vpowq_f32( + f32x4_t val, + f32x4_t n) +{ + return vexpq_f32(vmulq_f32(n, vlogq_f32(val))); +} + +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/ + +#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) +#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "NEMath.h" +/** + * @brief Vectorized integer exponentiation + * @param[in] x value + * @param[in] nb integer exponent >= 1 + * @return x^nb + * + */ +__STATIC_INLINE float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb) +{ + float32x4_t r = x; + nb --; + while(nb > 0) + { + r = vmulq_f32(r , x); + nb--; + } + return(r); +} + + +__STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x) +{ + float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN)); + float32x4_t e = vrsqrteq_f32(x1); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + return vmulq_f32(x, e); +} + +__STATIC_INLINE int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec) +{ + float32x4_t tempF; + int32x4_t tempHI,tempLO; + + tempLO = vmovl_s16(vget_low_s16(vec)); + tempF = vcvtq_n_f32_s32(tempLO,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempLO = vcvtq_n_s32_f32(tempF,15); + + tempHI = vmovl_s16(vget_high_s16(vec)); + tempF = vcvtq_n_f32_s32(tempHI,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempHI = vcvtq_n_s32_f32(tempF,15); + + return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI))); +} + +__STATIC_INLINE int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec) +{ + float32x4_t temp; + + temp = vcvtq_n_f32_s32(vec,31); + temp = __arm_vec_sqrt_f32_neon(temp); + return(vcvtq_n_s32_f32(temp,31)); +} + +#endif /* (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_VEC_MATH_H */ + +/** + * + * End of file. + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_vec_math_f16.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_vec_math_f16.h new file mode 100644 index 00000000..91bd28aa --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/arm_vec_math_f16.h @@ -0,0 +1,312 @@ +/****************************************************************************** + * @file arm_vec_math_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_VEC_MATH_F16_H +#define _ARM_VEC_MATH_F16_H + +#include "arm_math_types_f16.h" +#include "arm_common_tables_f16.h" +#include "arm_helium_utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + + +static const float16_t __logf_rng_f16=0.693147180f16; + +/* fast inverse approximation (3x newton) */ +__STATIC_INLINE f16x8_t vrecip_medprec_f16( + f16x8_t x) +{ + q15x8_t m; + f16x8_t b; + any16x8_t xinv; + f16x8_t ax = vabsq(x); + + xinv.f = ax; + + m = 0x03c00 - (xinv.i & 0x07c00); + xinv.i = xinv.i + m; + xinv.f = 1.41176471f16 - 0.47058824f16 * xinv.f; + xinv.i = xinv.i + m; + + b = 2.0f16 - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f16 - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f16 - xinv.f * ax; + xinv.f = xinv.f * b; + + xinv.f = vdupq_m_n_f16(xinv.f, F16INFINITY, vcmpeqq_n_f16(x, 0.0f)); + /* + * restore sign + */ + xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq_n_f16(x, 0.0f)); + + return xinv.f; +} + +/* fast inverse approximation (4x newton) */ +__STATIC_INLINE f16x8_t vrecip_hiprec_f16( + f16x8_t x) +{ + q15x8_t m; + f16x8_t b; + any16x8_t xinv; + f16x8_t ax = vabsq(x); + + xinv.f = ax; + + m = 0x03c00 - (xinv.i & 0x07c00); + xinv.i = xinv.i + m; + xinv.f = 1.41176471f16 - 0.47058824f16 * xinv.f; + xinv.i = xinv.i + m; + + b = 2.0f16 - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f16 - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f16 - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f16 - xinv.f * ax; + xinv.f = xinv.f * b; + + xinv.f = vdupq_m_n_f16(xinv.f, F16INFINITY, vcmpeqq_n_f16(x, 0.0f)); + /* + * restore sign + */ + xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq_n_f16(x, 0.0f)); + + return xinv.f; +} + +__STATIC_INLINE f16x8_t vdiv_f16( + f16x8_t num, f16x8_t den) +{ + return vmulq(num, vrecip_hiprec_f16(den)); +} + + +/** + @brief Single-precision taylor dev. + @param[in] x f16 vector input + @param[in] coeffs f16 vector coeffs + @return destination f16 vector + */ + +__STATIC_INLINE float16x8_t vtaylor_polyq_f16( + float16x8_t x, + const float16_t * coeffs) +{ + float16x8_t A = vfmasq(vdupq_n_f16(coeffs[4]), x, coeffs[0]); + float16x8_t B = vfmasq(vdupq_n_f16(coeffs[6]), x, coeffs[2]); + float16x8_t C = vfmasq(vdupq_n_f16(coeffs[5]), x, coeffs[1]); + float16x8_t D = vfmasq(vdupq_n_f16(coeffs[7]), x, coeffs[3]); + float16x8_t x2 = vmulq(x, x); + float16x8_t x4 = vmulq(x2, x2); + float16x8_t res = vfmaq(vfmaq_f16(A, B, x2), vfmaq_f16(C, D, x2), x4); + + return res; +} + +#define VMANT_EXP_F16(x) \ + any16x8_t r; \ + int16x8_t n; \ + \ + r.f = x; \ + n = r.i >> 10; \ + n = n - 15; \ + r.i = r.i - (n << 10);\ + \ + vecExpUnBiased = n; \ + vecTmpFlt1 = r.f; + +__STATIC_INLINE float16x8_t vlogq_f16(float16x8_t vecIn) +{ + q15x8_t vecExpUnBiased; + float16x8_t vecTmpFlt0, vecTmpFlt1; + float16x8_t vecAcc0, vecAcc1, vecAcc2, vecAcc3; + float16x8_t vecExpUnBiasedFlt; + + /* + * extract exponent + */ + VMANT_EXP_F16(vecIn); + + vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1; + /* + * a = (__logf_lut_f16[4] * r.f) + (__logf_lut_f16[0]); + */ + vecAcc0 = vdupq_n_f16(__logf_lut_f16[0]); + vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f16[4]); + /* + * b = (__logf_lut_f16[6] * r.f) + (__logf_lut_f16[2]); + */ + vecAcc1 = vdupq_n_f16(__logf_lut_f16[2]); + vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f16[6]); + /* + * c = (__logf_lut_f16[5] * r.f) + (__logf_lut_f16[1]); + */ + vecAcc2 = vdupq_n_f16(__logf_lut_f16[1]); + vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f16[5]); + /* + * d = (__logf_lut_f16[7] * r.f) + (__logf_lut_f16[3]); + */ + vecAcc3 = vdupq_n_f16(__logf_lut_f16[3]); + vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f16[7]); + /* + * a = a + b * xx; + */ + vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0); + /* + * c = c + d * xx; + */ + vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0); + /* + * xx = xx * xx; + */ + vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0; + vecExpUnBiasedFlt = vcvtq_f16_s16(vecExpUnBiased); + /* + * r.f = a + c * xx; + */ + vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0); + /* + * add exponent + * r.f = r.f + ((float32_t) m) * __logf_rng_f16; + */ + vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f16); + // set log0 down to -inf + vecAcc0 = vdupq_m_n_f16(vecAcc0, -(_Float16)F16INFINITY, vcmpeqq_n_f16(vecIn, 0.0f)); + return vecAcc0; +} + +__STATIC_INLINE float16x8_t vexpq_f16( + float16x8_t x) +{ + // Perform range reduction [-log(2),log(2)] + int16x8_t m = vcvtq_s16_f16(vmulq_n_f16(x, 1.4426950408f16)); + float16x8_t val = vfmsq_f16(x, vcvtq_f16_s16(m), vdupq_n_f16(0.6931471805f16)); + + // Polynomial Approximation + float16x8_t poly = vtaylor_polyq_f16(val, exp_tab_f16); + + // Reconstruct + poly = (float16x8_t) (vqaddq_s16((int16x8_t) (poly), vqshlq_n_s16(m, 10))); + + poly = vdupq_m_n_f16(poly, 0.0f16, vcmpltq_n_s16(m, -14)); + return poly; +} + +__STATIC_INLINE float16x8_t arm_vec_exponent_f16(float16x8_t x, int16_t nb) +{ + float16x8_t r = x; + nb--; + while (nb > 0) { + r = vmulq(r, x); + nb--; + } + return (r); +} + +__STATIC_INLINE f16x8_t vpowq_f16( + f16x8_t val, + f16x8_t n) +{ + return vexpq_f16(vmulq_f16(n, vlogq_f16(val))); +} + +#define INV_NEWTON_INIT_F16 0x7773 + +__STATIC_INLINE f16x8_t vrecip_f16(f16x8_t vecIn) +{ + f16x8_t vecSx, vecW, vecTmp; + any16x8_t v; + + vecSx = vabsq(vecIn); + + v.f = vecIn; + v.i = vsubq(vdupq_n_s16(INV_NEWTON_INIT_F16), v.i); + + vecW = vmulq(vecSx, v.f); + + // v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w))))))); + vecTmp = vsubq(vdupq_n_f16(8.0f16), vecW); + vecTmp = vfmasq_n_f16(vecW, vecTmp, -28.0f16); + vecTmp = vfmasq_n_f16(vecW, vecTmp, 56.0f16); + vecTmp = vfmasq_n_f16(vecW, vecTmp, -70.0f16); + vecTmp = vfmasq_n_f16(vecW, vecTmp, 56.0f16); + vecTmp = vfmasq_n_f16(vecW, vecTmp, -28.0f16); + vecTmp = vfmasq_n_f16(vecW, vecTmp, 8.0f16); + v.f = vmulq(v.f, vecTmp); + + v.f = vdupq_m_n_f16(v.f, F16INFINITY, vcmpeqq_n_f16(vecIn, 0.0f)); + /* + * restore sign + */ + v.f = vnegq_m(v.f, v.f, vcmpltq_n_f16(vecIn, 0.0f)); + return v.f; +} + +__STATIC_INLINE f16x8_t vtanhq_f16( + f16x8_t val) +{ + f16x8_t x = + vminnmq_f16(vmaxnmq_f16(val, vdupq_n_f16(-10.f16)), vdupq_n_f16(10.0f16)); + f16x8_t exp2x = vexpq_f16(vmulq_n_f16(x, 2.f16)); + f16x8_t num = vsubq_n_f16(exp2x, 1.f16); + f16x8_t den = vaddq_n_f16(exp2x, 1.f16); + f16x8_t tanh = vmulq_f16(num, vrecip_f16(den)); + return tanh; +} + +#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)*/ + + + +#ifdef __cplusplus +} +#endif + +#endif /* ARM FLOAT16 SUPPORTED */ + +#endif /* _ARM_VEC_MATH_F16_H */ + +/** + * + * End of file. + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/basic_math_functions.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/basic_math_functions.h new file mode 100644 index 00000000..dcc1f2a5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/basic_math_functions.h @@ -0,0 +1,880 @@ +/****************************************************************************** + * @file basic_math_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _BASIC_MATH_FUNCTIONS_H_ +#define _BASIC_MATH_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup groupMath Basic Math Functions + */ + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + +/** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_mult_f64( +const float64_t * pSrcA, +const float64_t * pSrcB, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + +/** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + const float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f64( + const float64_t * pSrc, + float64_t scale, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + const q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + const q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + const q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + +/** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ +void arm_abs_f64( +const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + +/** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ +void arm_dot_prod_f64( +const float64_t * pSrcA, +const float64_t * pSrcB, + uint32_t blockSize, + float64_t * result); + + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + const q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + const q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + const q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_offset_f64( +const float64_t * pSrc, + float64_t offset, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + const float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + const q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + const q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + const q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + +/** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_negate_f64( +const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u16( + const uint16_t * pSrc, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u32( + const uint32_t * pSrc, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u8( + const uint8_t * pSrc, + uint8_t * pDst, + uint32_t blockSize); + +/** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + @brief Elementwise floating-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +void arm_clip_f32(const float32_t * pSrc, + float32_t * pDst, + float32_t low, + float32_t high, + uint32_t numSamples); + + /** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +void arm_clip_q31(const q31_t * pSrc, + q31_t * pDst, + q31_t low, + q31_t high, + uint32_t numSamples); + + /** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +void arm_clip_q15(const q15_t * pSrc, + q15_t * pDst, + q15_t low, + q15_t high, + uint32_t numSamples); + + /** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +void arm_clip_q7(const q7_t * pSrc, + q7_t * pDst, + q7_t low, + q7_t high, + uint32_t numSamples); + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _BASIC_MATH_FUNCTIONS_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h new file mode 100644 index 00000000..de9f58ba --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h @@ -0,0 +1,168 @@ +/****************************************************************************** + * @file basic_math_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _BASIC_MATH_FUNCTIONS_F16_H_ +#define _BASIC_MATH_FUNCTIONS_F16_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + + +#if defined(ARM_FLOAT16_SUPPORTED) + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f16( + const float16_t * pSrc, + float16_t scale, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f16( + const float16_t * pSrc, + float16_t offset, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t * result); + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + /** + @brief Elementwise floating-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +void arm_clip_f16(const float16_t * pSrc, + float16_t * pDst, + float16_t low, + float16_t high, + uint32_t numSamples); + +#endif /* defined(ARM_FLOAT16_SUPPORTED)*/ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _BASIC_MATH_FUNCTIONS_F16_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/bayes_functions.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/bayes_functions.h new file mode 100644 index 00000000..824c50e8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/bayes_functions.h @@ -0,0 +1,89 @@ +/****************************************************************************** + * @file bayes_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _BAYES_FUNCTIONS_H_ +#define _BAYES_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/statistics_functions.h" + +/** + * @defgroup groupBayes Bayesian estimators + * + * Implement the naive gaussian Bayes estimator. + * The training must be done from scikit-learn. + * + * The parameters can be easily + * generated from the scikit-learn object. Some examples are given in + * DSP/Testing/PatternGeneration/Bayes.py + */ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @brief Instance structure for Naive Gaussian Bayesian estimator. + */ +typedef struct +{ + uint32_t vectorDimension; /**< Dimension of vector space */ + uint32_t numberOfClasses; /**< Number of different classes */ + const float32_t *theta; /**< Mean values for the Gaussians */ + const float32_t *sigma; /**< Variances for the Gaussians */ + const float32_t *classPriors; /**< Class prior probabilities */ + float32_t epsilon; /**< Additive value to variances */ +} arm_gaussian_naive_bayes_instance_f32; + +/** + * @brief Naive Gaussian Bayesian Estimator + * + * @param[in] S points to a naive bayes instance structure + * @param[in] in points to the elements of the input vector. + * @param[out] *pOutputProbabilities points to a buffer of length numberOfClasses containing estimated probabilities + * @param[out] *pBufferB points to a temporary buffer of length numberOfClasses + * @return The predicted class + * + */ + + +uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S, + const float32_t * in, + float32_t *pOutputProbabilities, + float32_t *pBufferB); + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _BAYES_FUNCTIONS_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/bayes_functions_f16.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/bayes_functions_f16.h new file mode 100644 index 00000000..f2c9ad82 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/bayes_functions_f16.h @@ -0,0 +1,80 @@ +/****************************************************************************** + * @file bayes_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _BAYES_FUNCTIONS_F16_H_ +#define _BAYES_FUNCTIONS_F16_H_ + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/statistics_functions_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + * @brief Instance structure for Naive Gaussian Bayesian estimator. + */ +typedef struct +{ + uint32_t vectorDimension; /**< Dimension of vector space */ + uint32_t numberOfClasses; /**< Number of different classes */ + const float16_t *theta; /**< Mean values for the Gaussians */ + const float16_t *sigma; /**< Variances for the Gaussians */ + const float16_t *classPriors; /**< Class prior probabilities */ + float16_t epsilon; /**< Additive value to variances */ +} arm_gaussian_naive_bayes_instance_f16; + +/** + * @brief Naive Gaussian Bayesian Estimator + * + * @param[in] S points to a naive bayes instance structure + * @param[in] in points to the elements of the input vector. + * @param[out] *pOutputProbabilities points to a buffer of length numberOfClasses containing estimated probabilities + * @param[out] *pBufferB points to a temporary buffer of length numberOfClasses + * @return The predicted class + * + */ + + +uint32_t arm_gaussian_naive_bayes_predict_f16(const arm_gaussian_naive_bayes_instance_f16 *S, + const float16_t * in, + float16_t *pOutputProbabilities, + float16_t *pBufferB); + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _BAYES_FUNCTIONS_F16_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/complex_math_functions.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/complex_math_functions.h new file mode 100644 index 00000000..1339ebae --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/complex_math_functions.h @@ -0,0 +1,345 @@ +/****************************************************************************** + * @file complex_math_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _COMPLEX_MATH_FUNCTIONS_H_ +#define _COMPLEX_MATH_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" +#include "dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + +/** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + +/** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_fast_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + const q15_t * pSrcCmplx, + const q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + const q31_t * pSrcCmplx, + const q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + const float32_t * pSrcCmplx, + const float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + +/** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void arm_cmplx_mult_cmplx_f64( +const float64_t * pSrcA, +const float64_t * pSrcB, + float64_t * pDst, + uint32_t numSamples); + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _COMPLEX_MATH_FUNCTIONS_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/complex_math_functions_f16.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/complex_math_functions_f16.h new file mode 100644 index 00000000..da78559b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/complex_math_functions_f16.h @@ -0,0 +1,123 @@ +/****************************************************************************** + * @file complex_math_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _COMPLEX_MATH_FUNCTIONS_F16_H_ +#define _COMPLEX_MATH_FUNCTIONS_F16_H_ + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" +#include "dsp/fast_math_functions_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t numSamples, + float16_t * realResult, + float16_t * imagResult); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f16( + const float16_t * pSrcCmplx, + const float16_t * pSrcReal, + float16_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t numSamples); + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _COMPLEX_MATH_FUNCTIONS_F16_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/controller_functions.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/controller_functions.h new file mode 100644 index 00000000..7c08c243 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/controller_functions.h @@ -0,0 +1,791 @@ +/****************************************************************************** + * @file controller_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _CONTROLLER_FUNCTIONS_H_ +#define _CONTROLLER_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + +#define CONTROLLER_Q31_SHIFT (32 - 9) + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + +/** + * @defgroup groupController Controller Functions + */ + + + /** + * @ingroup groupController + */ + + /** + * @addtogroup SinCos + * @{ + */ + +/** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + /** + * @} end of SinCos group + */ + + /** + * @ingroup groupController + */ + +/** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + *
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+   * 
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; /**< The derived gain A1 = -Kp - 2Kd */ + q15_t A2; /**< The derived gain A1 = Kd. */ +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return processed output sample. + */ + __STATIC_FORCEINLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + +/** + @brief Process function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ +__STATIC_FORCEINLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + +/** + @brief Process function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ +__STATIC_FORCEINLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((q31_t)(acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + * + * The function implements the forward Park transform. + * + */ + __STATIC_FORCEINLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + +/** + @brief Park transform for Q31 version + @param[in] Ialpha input two-phase vector coordinate alpha + @param[in] Ibeta input two-phase vector coordinate beta + @param[out] pId points to output rotor reference frame d + @param[out] pIq points to output rotor reference frame q + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + */ + __STATIC_FORCEINLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + +/** + @brief Inverse Park transform for Q31 version + @param[in] Id input coordinate of rotor reference frame d + @param[in] Iq input coordinate of rotor reference frame q + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + +/** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @return none + */ + __STATIC_FORCEINLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = (0.57735026919f * Ia + 1.15470053838f * Ib); + } + + +/** + @brief Clarke transform for Q31 version + @param[in] Ia input three-phase coordinate a + @param[in] Ib input three-phase coordinate b + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * @return none + */ + __STATIC_FORCEINLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + +/** + @brief Inverse Clarke transform for Q31 version + @param[in] Ialpha input two-phase orthogonal vector axis alpha + @param[in] Ibeta input two-phase orthogonal vector axis beta + @param[out] pIa points to output three-phase coordinate a + @param[out] pIb points to output three-phase coordinate b + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _CONTROLLER_FUNCTIONS_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/controller_functions_f16.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/controller_functions_f16.h new file mode 100644 index 00000000..b0bdd789 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/controller_functions_f16.h @@ -0,0 +1,41 @@ +/****************************************************************************** + * @file controller_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _CONTROLLER_FUNCTIONS_F16_H_ +#define _CONTROLLER_FUNCTIONS_F16_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _CONTROLLER_FUNCTIONS_F16_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/distance_functions.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/distance_functions.h new file mode 100644 index 00000000..3123fc3a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/distance_functions.h @@ -0,0 +1,341 @@ +/****************************************************************************** + * @file distance_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _DISTANCE_FUNCTIONS_H_ +#define _DISTANCE_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/statistics_functions.h" +#include "dsp/basic_math_functions.h" +#include "dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @defgroup groupDistance Distance functions + * + * Distance functions for use with clustering algorithms. + * There are distance functions for float vectors and boolean vectors. + * + */ + +/* 6.14 bug */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) && (__ARMCC_VERSION < 6150001) + +__attribute__((weak)) float __powisf2(float a, int b); + +#endif + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float64_t arm_euclidean_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize); + +/** + * @brief Bray-Curtis distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Canberra distance between two vectors + * + * This function may divide by zero when samples pA[i] and pB[i] are both zero. + * The result of the computation will be correct. So the division per zero may be + * ignored. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float64_t arm_chebyshev_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize); + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float64_t arm_cityblock_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize); + +/** + * @brief Correlation distance between two vectors + * + * The input vectors are modified in place ! + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize); + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float64_t arm_cosine_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize); + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x 0 and y 0, + * it will compute the right value (0) but a division per zero will occur + * and shoudl be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB,uint32_t blockSize); + +/** + * @brief Minkowski distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] n Norm order (>= 2) + * @param[in] blockSize vector length + * @return distance + * + */ + + + +float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize); + +/** + * @brief Dice distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] order Distance order + * @param[in] blockSize Number of samples + * @return distance + * + */ + + +float32_t arm_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Hamming distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Jaccard distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Kulsinski distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Roger Stanimoto distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Russell-Rao distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Sokal-Michener distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Sokal-Sneath distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Yule distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _DISTANCE_FUNCTIONS_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/distance_functions_f16.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/distance_functions_f16.h new file mode 100644 index 00000000..a7ceb3c1 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/distance_functions_f16.h @@ -0,0 +1,180 @@ +/****************************************************************************** + * @file distance_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _DISTANCE_FUNCTIONS_F16_H_ +#define _DISTANCE_FUNCTIONS_F16_H_ + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +/* 6.14 bug */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) && (__ARMCC_VERSION < 6150001) +/* Defined in minkowski_f32 */ +__attribute__((weak)) float __powisf2(float a, int b); +#endif + +#include "dsp/statistics_functions_f16.h" +#include "dsp/basic_math_functions_f16.h" + +#include "dsp/fast_math_functions_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float16_t arm_euclidean_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + +/** + * @brief Bray-Curtis distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float16_t arm_braycurtis_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + +/** + * @brief Canberra distance between two vectors + * + * This function may divide by zero when samples pA[i] and pB[i] are both zero. + * The result of the computation will be correct. So the division per zero may be + * ignored. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float16_t arm_canberra_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float16_t arm_chebyshev_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float16_t arm_cityblock_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + +/** + * @brief Correlation distance between two vectors + * + * The input vectors are modified in place ! + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float16_t arm_correlation_distance_f16(float16_t *pA,float16_t *pB, uint32_t blockSize); + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float16_t arm_cosine_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x 0 and y 0, + * it will compute the right value (0) but a division per zero will occur + * and shoudl be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float16_t arm_jensenshannon_distance_f16(const float16_t *pA,const float16_t *pB,uint32_t blockSize); + +/** + * @brief Minkowski distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] n Norm order (>= 2) + * @param[in] blockSize vector length + * @return distance + * + */ + + + +float16_t arm_minkowski_distance_f16(const float16_t *pA,const float16_t *pB, int32_t order, uint32_t blockSize); + + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _DISTANCE_FUNCTIONS_F16_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/fast_math_functions.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/fast_math_functions.h new file mode 100644 index 00000000..489f2140 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/fast_math_functions.h @@ -0,0 +1,389 @@ +/****************************************************************************** + * @file fast_math_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _FAST_MATH_FUNCTIONS_H_ +#define _FAST_MATH_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/basic_math_functions.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) + +#ifndef PI + #define PI 3.14159265358979f +#endif + + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + + /** + * @ingroup groupFastMath + */ + + +/** + @addtogroup sin + @{ + */ + +/** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + +/** + @} end of sin group + */ + +/** + @addtogroup cos + @{ + */ + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + +/** + @} end of cos group + */ + + +/** + @brief Floating-point vector of log values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vlog_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + +/** + @brief Floating-point vector of log values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vlog_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief q31 vector of log values. + * @param[in] pSrc points to the input vector in q31 + * @param[out] pDst points to the output vector in q5.26 + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_vlog_q31(const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief q15 vector of log values. + * @param[in] pSrc points to the input vector in q15 + * @param[out] pDst points to the output vector in q4.11 + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_vlog_q15(const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + +/** + @brief Floating-point vector of exp values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vexp_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + +/** + @brief Floating-point vector of exp values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vexp_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + *
+   *      x1 = x0 - f(x0)/f'(x0)
+   * 
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + *
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * 
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + +/** + @brief Floating-point square root function. + @param[in] in input value + @param[out] pOut square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +__STATIC_FORCEINLINE arm_status arm_sqrt_f32( + const float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + *pOut = __sqrtf(in); + #else + *pOut = sqrtf(in); + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); + #else + *pOut = sqrtf(in); + #endif + +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + +/** + @brief Q31 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + +/** + @brief Q15 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + + + /** + * @} end of SQRT group + */ + + /** + @brief Fixed point division + @param[in] numerator Numerator + @param[in] denominator Denominator + @param[out] quotient Quotient value normalized between -1.0 and 1.0 + @param[out] shift Shift left value to get the unnormalized quotient + @return error status + + When dividing by 0, an error ARM_MATH_NANINF is returned. And the quotient is forced + to the saturated negative or positive value. + */ + +arm_status arm_divide_q15(q15_t numerator, + q15_t denominator, + q15_t *quotient, + int16_t *shift); + + /** + @brief Fixed point division + @param[in] numerator Numerator + @param[in] denominator Denominator + @param[out] quotient Quotient value normalized between -1.0 and 1.0 + @param[out] shift Shift left value to get the unnormalized quotient + @return error status + + When dividing by 0, an error ARM_MATH_NANINF is returned. And the quotient is forced + to the saturated negative or positive value. + */ + +arm_status arm_divide_q31(q31_t numerator, + q31_t denominator, + q31_t *quotient, + int16_t *shift); + + + + /** + @brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant. + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result + @return error status. + */ + arm_status arm_atan2_f32(float32_t y,float32_t x,float32_t *result); + + + /** + @brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant. + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result in Q2.29 + @return error status. + */ + arm_status arm_atan2_q31(q31_t y,q31_t x,q31_t *result); + + /** + @brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant. + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result in Q2.13 + @return error status. + */ + arm_status arm_atan2_q15(q15_t y,q15_t x,q15_t *result); + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _FAST_MATH_FUNCTIONS_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/fast_math_functions_f16.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/fast_math_functions_f16.h new file mode 100644 index 00000000..46ae06dd --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/fast_math_functions_f16.h @@ -0,0 +1,125 @@ +/****************************************************************************** + * @file fast_math_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _FAST_MATH_FUNCTIONS_F16_H_ +#define _FAST_MATH_FUNCTIONS_F16_H_ + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +/* For sqrt_f32 */ +#include "dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + + /** + * @addtogroup SQRT + * @{ + */ + +/** + @brief Floating-point square root function. + @param[in] in input value + @param[out] pOut square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +__STATIC_FORCEINLINE arm_status arm_sqrt_f16( + float16_t in, + float16_t * pOut) + { + float32_t r; + arm_status status; + status=arm_sqrt_f32((float32_t)in,&r); + *pOut=(float16_t)r; + return(status); + } + + +/** + @} end of SQRT group + */ + +/** + @brief Floating-point vector of log values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vlog_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + +/** + @brief Floating-point vector of exp values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vexp_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + /** + @brief Floating-point vector of inverse values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vinverse_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + /** + @brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant. + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result + @return error status. + */ + arm_status arm_atan2_f16(float16_t y,float16_t x,float16_t *result); + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _FAST_MATH_FUNCTIONS_F16_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/filtering_functions.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/filtering_functions.h new file mode 100644 index 00000000..28a95689 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/filtering_functions.h @@ -0,0 +1,2529 @@ +/****************************************************************************** + * @file filtering_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _FILTERING_FUNCTIONS_H_ +#define _FILTERING_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/support_functions.h" +#include "dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +#define DELTA_Q31 ((q31_t)(0x100)) +#define DELTA_Q15 ((q15_t)0x5) + +/** + * @defgroup groupFilters Filtering Functions + */ + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float64_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float64_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f64; + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * + * For the MVE version, the coefficient length must be a multiple of 16. + * You can pad with zeros if you have less coefficients. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter (fast version). + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns either + * ARM_MATH_SUCCESS if initialization was successful or + * ARM_MATH_ARGUMENT_ERROR if numTaps is not a supported value. + * + * For the MVE version, the coefficient length must be a multiple of 8. + * You can pad with zeros if you have less coefficients. + * + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter (fast version). + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * + * For the MVE version, the coefficient length must be a multiple of 4. + * You can pad with zeros if you have less coefficients. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f64( + const arm_fir_instance_f64 * S, + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f64( + arm_fir_instance_f64 * S, + uint16_t numTaps, + const float64_t * pCoeffs, + float64_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + /** + * @brief Instance structure for the modified Biquad coefs required by vectorized code. + */ + typedef struct + { + float32_t coeffs[8][4]; /**< Points to the array of modified coefficients. The array is of length 32. There is one per stage */ + } arm_biquad_mod_coef_f32; +#endif + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + const q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pCoeffsMod points to the modified filter coefficients (only MVE version). + * @param[in] pState points to the state buffer. + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + void arm_biquad_cascade_df1_mve_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + arm_biquad_mod_coef_f32 * pCoeffsMod, + float32_t * pState); +#endif + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + +/** + @brief Instance structure for floating-point FIR decimator. + */ +typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + +/** + @brief Processing function for floating-point FIR decimator. + @param[in] S points to an instance of the floating-point FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + */ +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + @brief Initialization function for the floating-point FIR decimator. + @param[in,out] S points to an instance of the floating-point FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + */ +arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + +#if defined(ARM_MATH_NEON) +/** + @brief Compute new coefficient arrays for use in vectorized filter (Neon only). + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the original filter coefficients. + @param[in] pComputedCoeffs points to the new computed coefficients for the vectorized version. + @return none +*/ +void arm_biquad_cascade_df2T_compute_coefs_f32( + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pComputedCoeffs); +#endif + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + const float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + const q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + const q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f64( + const float64_t * pSrcA, + uint32_t srcALen, + const float64_t * pSrcB, + uint32_t srcBLen, + float64_t * pDst); + + +/** + @brief Correlation of Q15 sequences + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +*/ +void arm_correlate_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ +void arm_correlate_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ +void arm_correlate_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + +/** + @brief Correlation of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + + + + + /** + * @brief floating-point Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset; + int32_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q15_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q7_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ +void arm_levinson_durbin_f32(const float32_t *phi, + float32_t *a, + float32_t *err, + int nbCoefs); + + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ +void arm_levinson_durbin_q31(const q31_t *phi, + q31_t *a, + q31_t *err, + int nbCoefs); + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _FILTERING_FUNCTIONS_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/filtering_functions_f16.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/filtering_functions_f16.h new file mode 100644 index 00000000..fd8b0bba --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/filtering_functions_f16.h @@ -0,0 +1,237 @@ +/****************************************************************************** + * @file filtering_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _FILTERING_FUNCTIONS_F16_H_ +#define _FILTERING_FUNCTIONS_F16_H_ + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float16_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float16_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f16; + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f16( + arm_fir_instance_f16 * S, + uint16_t numTaps, + const float16_t * pCoeffs, + float16_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f16( + const arm_fir_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float16_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const float16_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f16; + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + /** + * @brief Instance structure for the modified Biquad coefs required by vectorized code. + */ + typedef struct + { + float16_t coeffs[12][8]; /**< Points to the array of modified coefficients. The array is of length 32. There is one per stage */ + } arm_biquad_mod_coef_f16; +#endif + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f16( + const arm_biquad_casd_df1_inst_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + void arm_biquad_cascade_df1_mve_init_f16( + arm_biquad_casd_df1_inst_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + arm_biquad_mod_coef_f16 * pCoeffsMod, + float16_t * pState); +#endif + + void arm_biquad_cascade_df1_init_f16( + arm_biquad_casd_df1_inst_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState); + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float16_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float16_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f16; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float16_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const float16_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f16; + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f16( + const arm_biquad_cascade_df2T_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f16( + const arm_biquad_cascade_stereo_df2T_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f16( + arm_biquad_cascade_df2T_instance_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState); + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f16( + arm_biquad_cascade_stereo_df2T_instance_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f16( + const float16_t * pSrcA, + uint32_t srcALen, + const float16_t * pSrcB, + uint32_t srcBLen, + float16_t * pDst); + + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ +void arm_levinson_durbin_f16(const float16_t *phi, + float16_t *a, + float16_t *err, + int nbCoefs); + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _FILTERING_FUNCTIONS_F16_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/interpolation_functions.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/interpolation_functions.h new file mode 100644 index 00000000..6e51f7c8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/interpolation_functions.h @@ -0,0 +1,319 @@ +/****************************************************************************** + * @file interpolation_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _INTERPOLATION_FUNCTIONS_H_ +#define _INTERPOLATION_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Struct for specifying cubic spline type + */ + typedef enum + { + ARM_SPLINE_NATURAL = 0, /**< Natural spline */ + ARM_SPLINE_PARABOLIC_RUNOUT = 1 /**< Parabolic runout spline */ + } arm_spline_type; + + /** + * @brief Instance structure for the floating-point cubic spline interpolation. + */ + typedef struct + { + arm_spline_type type; /**< Type (boundary conditions) */ + const float32_t * x; /**< x values */ + const float32_t * y; /**< y values */ + uint32_t n_x; /**< Number of known data points */ + float32_t * coeffs; /**< Coefficients buffer (b,c, and d) */ + } arm_spline_instance_f32; + + + + + /** + * @ingroup groupInterpolation + */ + + /** + * @addtogroup SplineInterpolate + * @{ + */ + + + /** + * @brief Processing function for the floating-point cubic spline interpolation. + * @param[in] S points to an instance of the floating-point spline structure. + * @param[in] xq points to the x values ot the interpolated data points. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples of output data. + */ + void arm_spline_f32( + arm_spline_instance_f32 * S, + const float32_t * xq, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point cubic spline interpolation. + * @param[in,out] S points to an instance of the floating-point spline structure. + * @param[in] type type of cubic spline interpolation (boundary conditions) + * @param[in] x points to the x values of the known data points. + * @param[in] y points to the y values of the known data points. + * @param[in] n number of known data points. + * @param[in] coeffs coefficients array for b, c, and d + * @param[in] tempBuffer buffer array for internal computations + */ + void arm_spline_init_f32( + arm_spline_instance_f32 * S, + arm_spline_type type, + const float32_t * x, + const float32_t * y, + uint32_t n, + float32_t * coeffs, + float32_t * tempBuffer); + + + /** + * @} end of SplineInterpolate group + */ + + + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x); + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + q31_t arm_linear_interp_q31( + const q31_t * pYData, + q31_t x, + uint32_t nValues); + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + q15_t arm_linear_interp_q15( + const q15_t * pYData, + q31_t x, + uint32_t nValues); + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ +q7_t arm_linear_interp_q7( + const q7_t * pYData, + q31_t x, + uint32_t nValues); + + /** + * @} end of LinearInterpolate group + */ + + + + + /** + * @ingroup groupInterpolation + */ + + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y); + + /** + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y); + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y); + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y); + /** + * @} end of BilinearInterpolate group + */ + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _INTERPOLATION_FUNCTIONS_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/interpolation_functions_f16.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/interpolation_functions_f16.h new file mode 100644 index 00000000..8b6e6a99 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/interpolation_functions_f16.h @@ -0,0 +1,107 @@ +/****************************************************************************** + * @file interpolation_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _INTERPOLATION_FUNCTIONS_F16_H_ +#define _INTERPOLATION_FUNCTIONS_F16_H_ + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + +typedef struct +{ + uint32_t nValues; /**< nValues */ + float16_t x1; /**< x1 */ + float16_t xSpacing; /**< xSpacing */ + float16_t *pYData; /**< pointer to the table of Y values */ +} arm_linear_interp_instance_f16; + +/** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ +typedef struct +{ + uint16_t numRows;/**< number of rows in the data table. */ + uint16_t numCols;/**< number of columns in the data table. */ + float16_t *pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_f16; + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + float16_t arm_linear_interp_f16( + arm_linear_interp_instance_f16 * S, + float16_t x); + + /** + * @} end of LinearInterpolate group + */ + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + float16_t arm_bilinear_interp_f16( + const arm_bilinear_interp_instance_f16 * S, + float16_t X, + float16_t Y); + + + /** + * @} end of BilinearInterpolate group + */ +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _INTERPOLATION_FUNCTIONS_F16_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/matrix_functions.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/matrix_functions.h new file mode 100644 index 00000000..f3801a98 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/matrix_functions.h @@ -0,0 +1,757 @@ +/****************************************************************************** + * @file matrix_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _MATRIX_FUNCTIONS_H_ +#define _MATRIX_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + *
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * 
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + *
+ *     pData[i*numCols + j]
+ * 
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to \ref arm_mat_init_f32(), \ref arm_mat_init_q31() and \ref arm_mat_init_q15() + * for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + *
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ * 
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + *
+ *     ARM_MATH_SIZE_MISMATCH
+ * 
+ * Otherwise the functions return + *
+ *     ARM_MATH_SUCCESS
+ * 
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + *
+ *     ARM_MATH_MATRIX_CHECK
+ * 
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q7 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q7_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q7; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + +/** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pDst); + + /** + * @brief Floating-point complex matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q15 complex matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q7 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q7( + const arm_matrix_instance_q7 * pSrc, + arm_matrix_instance_q7 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 complex matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f64( + const arm_matrix_instance_f64 * pSrcA, + const arm_matrix_instance_f64 * pSrcB, + arm_matrix_instance_f64 * pDst); + + /** + * @brief Floating-point matrix and vector multiplication + * @param[in] pSrcMat points to the input matrix structure + * @param[in] pVec points to vector + * @param[out] pDst points to output vector + */ +void arm_mat_vec_mult_f32( + const arm_matrix_instance_f32 *pSrcMat, + const float32_t *pVec, + float32_t *pDst); + + /** + * @brief Q7 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q7( + const arm_matrix_instance_q7 * pSrcA, + const arm_matrix_instance_q7 * pSrcB, + arm_matrix_instance_q7 * pDst, + q7_t * pState); + + /** + * @brief Q7 matrix and vector multiplication + * @param[in] pSrcMat points to the input matrix structure + * @param[in] pVec points to vector + * @param[out] pDst points to output vector + */ +void arm_mat_vec_mult_q7( + const arm_matrix_instance_q7 *pSrcMat, + const q7_t *pVec, + q7_t *pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix and vector multiplication + * @param[in] pSrcMat points to the input matrix structure + * @param[in] pVec points to vector + * @param[out] pDst points to output vector + */ +void arm_mat_vec_mult_q15( + const arm_matrix_instance_q15 *pSrcMat, + const q15_t *pVec, + q15_t *pDst); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_opt_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst, + q31_t *pState); + + /** + * @brief Q31 matrix and vector multiplication + * @param[in] pSrcMat points to the input matrix structure + * @param[in] pVec points to vector + * @param[out] pDst points to output vector + */ +void arm_mat_vec_mult_q31( + const arm_matrix_instance_q31 *pSrcMat, + const q31_t *pVec, + q31_t *pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_f64( + const arm_matrix_instance_f64 * pSrcA, + const arm_matrix_instance_f64 * pSrcB, + arm_matrix_instance_f64 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + /** + * @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE. + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition is returning a lower triangular matrix. + */ + arm_status arm_mat_cholesky_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + /** + * @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE. + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition is returning a lower triangular matrix. + */ + arm_status arm_mat_cholesky_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + /** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_upper_triangular_f32( + const arm_matrix_instance_f32 * ut, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst); + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_lower_triangular_f32( + const arm_matrix_instance_f32 * lt, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_upper_triangular_f64( + const arm_matrix_instance_f64 * ut, + const arm_matrix_instance_f64 * a, + arm_matrix_instance_f64 * dst); + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_lower_triangular_f64( + const arm_matrix_instance_f64 * lt, + const arm_matrix_instance_f64 * a, + arm_matrix_instance_f64 * dst); + + + /** + * @brief Floating-point LDL decomposition of Symmetric Positive Semi-Definite Matrix. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] l points to the instance of the output floating-point triangular matrix structure. + * @param[out] d points to the instance of the output floating-point diagonal matrix structure. + * @param[out] p points to the instance of the output floating-point permutation vector. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE. + * The decomposition is returning a lower triangular matrix. + */ + arm_status arm_mat_ldlt_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * l, + arm_matrix_instance_f32 * d, + uint16_t * pp); + + /** + * @brief Floating-point LDL decomposition of Symmetric Positive Semi-Definite Matrix. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] l points to the instance of the output floating-point triangular matrix structure. + * @param[out] d points to the instance of the output floating-point diagonal matrix structure. + * @param[out] p points to the instance of the output floating-point permutation vector. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE. + * The decomposition is returning a lower triangular matrix. + */ + arm_status arm_mat_ldlt_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * l, + arm_matrix_instance_f64 * d, + uint16_t * pp); + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _MATRIX_FUNCTIONS_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/matrix_functions_f16.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/matrix_functions_f16.h new file mode 100644 index 00000000..62876a76 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/matrix_functions_f16.h @@ -0,0 +1,221 @@ +/****************************************************************************** + * @file matrix_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _MATRIX_FUNCTIONS_F16_H_ +#define _MATRIX_FUNCTIONS_F16_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float16_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f16; + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point complex matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_trans_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst); + /** + * @brief Floating-point matrix and vector multiplication + * @param[in] pSrcMat points to the input matrix structure + * @param[in] pVec points to vector + * @param[out] pDst points to output vector + */ +void arm_mat_vec_mult_f16( + const arm_matrix_instance_f16 *pSrcMat, + const float16_t *pVec, + float16_t *pDst); + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_f16( + const arm_matrix_instance_f16 * pSrc, + float16_t scale, + arm_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_f16( + arm_matrix_instance_f16 * S, + uint16_t nRows, + uint16_t nColumns, + float16_t * pData); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f16( + const arm_matrix_instance_f16 * src, + arm_matrix_instance_f16 * dst); + + + /** + * @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE. + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition is returning a lower triangular matrix. + */ + arm_status arm_mat_cholesky_f16( + const arm_matrix_instance_f16 * src, + arm_matrix_instance_f16 * dst); + + /** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_upper_triangular_f16( + const arm_matrix_instance_f16 * ut, + const arm_matrix_instance_f16 * a, + arm_matrix_instance_f16 * dst); + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_lower_triangular_f16( + const arm_matrix_instance_f16 * lt, + const arm_matrix_instance_f16 * a, + arm_matrix_instance_f16 * dst); + + + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _MATRIX_FUNCTIONS_F16_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/none.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/none.h new file mode 100644 index 00000000..130386ee --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/none.h @@ -0,0 +1,576 @@ +/****************************************************************************** + * @file none.h + * @brief Intrinsincs when no DSP extension available + * @version V1.9.0 + * @date 20. July 2020 + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + +Definitions in this file are allowing to reuse some versions of the +CMSIS-DSP to build on a core (M0 for instance) or a host where +DSP extension are not available. + +Ideally a pure C version should have been used instead. +But those are not always available or use a restricted set +of intrinsics. + +*/ + +#ifndef _NONE_H_ +#define _NONE_H_ + +#include "arm_math_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +/* + +Normally those kind of definitions are in a compiler file +in Core or Core_A. + +But for MSVC compiler it is a bit special. The goal is very specific +to CMSIS-DSP and only to allow the use of this library from other +systems like Python or Matlab. + +MSVC is not going to be used to cross-compile to ARM. So, having a MSVC +compiler file in Core or Core_A would not make sense. + +*/ +#if defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) || defined(__APPLE_CC__) + __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } + + /** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +#endif + +/** + * @brief Clips Q63 to Q31 values. + */ + __STATIC_FORCEINLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + __STATIC_FORCEINLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + __STATIC_FORCEINLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y) ) ); + } + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + +#ifndef ARM_MATH_DSP + /** + * @brief definition to pack two 16 bit values. + */ + #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) + #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) +#endif + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) +#endif + + + + +/* + * @brief C custom defined intrinsic functions + */ +#if !defined (ARM_MATH_DSP) + + + /* + * @brief C custom defined QADD8 + */ + __STATIC_FORCEINLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 + */ + __STATIC_FORCEINLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 + */ + __STATIC_FORCEINLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 + */ + __STATIC_FORCEINLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 + */ + __STATIC_FORCEINLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 + */ + __STATIC_FORCEINLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX + */ + __STATIC_FORCEINLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX + */ + __STATIC_FORCEINLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX + */ + __STATIC_FORCEINLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX + */ + __STATIC_FORCEINLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX + */ + __STATIC_FORCEINLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX + */ + __STATIC_FORCEINLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD + */ + __STATIC_FORCEINLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB + */ + __STATIC_FORCEINLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD + */ + __STATIC_FORCEINLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX + */ + __STATIC_FORCEINLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX + */ + __STATIC_FORCEINLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD + */ + __STATIC_FORCEINLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX + */ + __STATIC_FORCEINLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD + */ + __STATIC_FORCEINLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD + */ + __STATIC_FORCEINLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 + */ + __STATIC_FORCEINLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA + */ + __STATIC_FORCEINLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _TRANSFORM_FUNCTIONS_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/quaternion_math_functions.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/quaternion_math_functions.h new file mode 100644 index 00000000..0c5d0674 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/quaternion_math_functions.h @@ -0,0 +1,159 @@ +/****************************************************************************** + * @file quaternion_math_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _QUATERNION_MATH_FUNCTIONS_H_ +#define _QUATERNION_MATH_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup groupQuaternionMath Quaternion Math Functions + * Functions to operates on quaternions and convert between a + * rotation and quaternion representation. + */ + + +/** + @brief Floating-point quaternion Norm. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pNorms points to the output vector of norms + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ + + + +void arm_quaternion_norm_f32(const float32_t *pInputQuaternions, + float32_t *pNorms, + uint32_t nbQuaternions); + + +/** + @brief Floating-point quaternion inverse. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pInverseQuaternions points to the output vector of inverse quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ + +void arm_quaternion_inverse_f32(const float32_t *pInputQuaternions, + float32_t *pInverseQuaternions, + uint32_t nbQuaternions); + +/** + @brief Floating-point quaternion conjugates. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pConjugateQuaternions points to the output vector of conjugate quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ +void arm_quaternion_conjugate_f32(const float32_t *inputQuaternions, + float32_t *pConjugateQuaternions, + uint32_t nbQuaternions); + +/** + @brief Floating-point normalization of quaternions. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pNormalizedQuaternions points to the output vector of normalized quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ +void arm_quaternion_normalize_f32(const float32_t *inputQuaternions, + float32_t *pNormalizedQuaternions, + uint32_t nbQuaternions); + + +/** + @brief Floating-point product of two quaternions. + @param[in] qa First quaternion + @param[in] qb Second quaternion + @param[out] r Product of two quaternions + @return none + */ +void arm_quaternion_product_single_f32(const float32_t *qa, + const float32_t *qb, + float32_t *r); + +/** + @brief Floating-point elementwise product two quaternions. + @param[in] qa First array of quaternions + @param[in] qb Second array of quaternions + @param[out] r Elementwise product of quaternions + @param[in] nbQuaternions Number of quaternions in the array + @return none + */ +void arm_quaternion_product_f32(const float32_t *qa, + const float32_t *qb, + float32_t *r, + uint32_t nbQuaternions); + +/** + * @brief Conversion of quaternion to equivalent rotation matrix. + * @param[in] pInputQuaternions points to an array of normalized quaternions + * @param[out] pOutputRotations points to an array of 3x3 rotations (in row order) + * @param[in] nbQuaternions in the array + * @return none. + * + * Format of rotation matrix + * \par + * The quaternion a + ib + jc + kd is converted into rotation matrix: + * a^2 + b^2 - c^2 - d^2 2bc - 2ad 2bd + 2ac + * 2bc + 2ad a^2 - b^2 + c^2 - d^2 2cd - 2ab + * 2bd - 2ac 2cd + 2ab a^2 - b^2 - c^2 + d^2 + * + * Rotation matrix is saved in row order : R00 R01 R02 R10 R11 R12 R20 R21 R22 + */ +void arm_quaternion2rotation_f32(const float32_t *pInputQuaternions, + float32_t *pOutputRotations, + uint32_t nbQuaternions); + +/** + * @brief Conversion of a rotation matrix to equivalent quaternion. + * @param[in] pInputRotations points to an array 3x3 rotation matrix (in row order) + * @param[out] pOutputQuaternions points to an array of quaternions + * @param[in] nbQuaternions in the array + * @return none. +*/ +void arm_rotation2quaternion_f32(const float32_t *pInputRotations, + float32_t *pOutputQuaternions, + uint32_t nbQuaternions); + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _QUATERNION_MATH_FUNCTIONS_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/statistics_functions.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/statistics_functions.h new file mode 100644 index 00000000..c5224c6d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/statistics_functions.h @@ -0,0 +1,977 @@ +/****************************************************************************** + * @file statistics_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _STATISTICS_FUNCTIONS_H_ +#define _STATISTICS_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/basic_math_functions.h" +#include "dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @defgroup groupStats Statistics Functions + */ + +/** + * @brief Computation of the LogSumExp + * + * In probabilistic computations, the dynamic of the probability values can be very + * wide because they come from gaussian functions. + * To avoid underflow and overflow issues, the values are represented by their log. + * In this representation, multiplying the original exp values is easy : their logs are added. + * But adding the original exp values is requiring some special handling and it is the + * goal of the LogSumExp function. + * + * If the values are x1...xn, the function is computing: + * + * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that + * rounding issues are minimised. + * + * The max xm of the values is extracted and the function is computing: + * xm + ln(exp(x1 - xm) + ... + exp(xn - xm)) + * + * @param[in] *in Pointer to an array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return LogSumExp + * + */ + + +float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize); + +/** + * @brief Dot product with log arithmetic + * + * Vectors are containing the log of the samples + * + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[in] pTmpBuffer temporary buffer of length blockSize + * @return The log of the dot product . + * + */ + + +float32_t arm_logsumexp_dot_prod_f32(const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t *pTmpBuffer); + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize); + + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float64_t arm_entropy_f64(const float64_t * pSrcA, uint32_t blockSize); + + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float32_t arm_kullback_leibler_f32(const float32_t * pSrcA + ,const float32_t * pSrcB + ,uint32_t blockSize); + + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, + const float64_t * pSrcB, + uint32_t blockSize); + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + const q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + const q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + const q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of absolute values of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_absmin_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of absolute values of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + */ + void arm_absmin_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * result); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Minimum value of absolute values of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_absmin_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + */ + void arm_absmin_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_absmin_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + */ + void arm_absmin_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_absmin_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + */ + void arm_absmin_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_absmin_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + */ + void arm_absmin_no_idx_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_absmax_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + */ + void arm_absmax_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_absmax_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Maximum value of absolute values of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + */ + void arm_absmax_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_absmax_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Maximum value of absolute values of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + */ + void arm_absmax_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_absmax_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Maximum value of absolute values of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + */ + void arm_absmax_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_absmax_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + */ + void arm_absmax_no_idx_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult); + + /** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); + + /** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + void arm_min_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); + + /** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_f64( + const float64_t *pSrc, + uint32_t blockSize, + float64_t *pResult); + + /** + @brief Maximum value of a q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_q31( + const q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult); + + /** + @brief Maximum value of a q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_q15( + const q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult); + + /** + @brief Maximum value of a q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_q7( + const q7_t *pSrc, + uint32_t blockSize, + q7_t *pResult); + + /** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + void arm_min_no_idx_f64( + const float64_t *pSrc, + uint32_t blockSize, + float64_t *pResult); + +/** + @brief Minimum value of a q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + void arm_min_no_idx_q31( + const q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult); + + /** + @brief Minimum value of a q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + void arm_min_no_idx_q15( + const q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult); + + /** + @brief Minimum value of a q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + void arm_min_no_idx_q7( + const q7_t *pSrc, + uint32_t blockSize, + q7_t *pResult); + +/** + @brief Mean square error between two Q7 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none +*/ + +void arm_mse_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q7_t * pResult); + +/** + @brief Mean square error between two Q15 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none +*/ + +void arm_mse_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q15_t * pResult); + +/** + @brief Mean square error between two Q31 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none +*/ + +void arm_mse_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q31_t * pResult); + +/** + @brief Mean square error between two single precision float vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none +*/ + +void arm_mse_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * pResult); + +/** + @brief Mean square error between two double precision float vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none +*/ + +void arm_mse_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + uint32_t blockSize, + float64_t * pResult); + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _STATISTICS_FUNCTIONS_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/statistics_functions_f16.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/statistics_functions_f16.h new file mode 100644 index 00000000..8ed3a844 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/statistics_functions_f16.h @@ -0,0 +1,218 @@ +/****************************************************************************** + * @file statistics_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _STATISTICS_FUNCTIONS_F16_H_ +#define _STATISTICS_FUNCTIONS_F16_H_ + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/basic_math_functions_f16.h" +#include "dsp/fast_math_functions_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_absmin_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_absmax_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex); + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float16_t arm_entropy_f16(const float16_t * pSrcA,uint32_t blockSize); + +float16_t arm_logsumexp_f16(const float16_t *in, uint32_t blockSize); + +/** + * @brief Dot product with log arithmetic + * + * Vectors are containing the log of the samples + * + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[in] pTmpBuffer temporary buffer of length blockSize + * @return The log of the dot product . + * + */ + + +float16_t arm_logsumexp_dot_prod_f16(const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t *pTmpBuffer); + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float16_t arm_kullback_leibler_f16(const float16_t * pSrcA + ,const float16_t * pSrcB + ,uint32_t blockSize); + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_f16( + const float16_t *pSrc, + uint32_t blockSize, + float16_t *pResult); + + + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _STATISTICS_FUNCTIONS_F16_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/support_functions.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/support_functions.h new file mode 100644 index 00000000..9c775932 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/support_functions.h @@ -0,0 +1,453 @@ +/****************************************************************************** + * @file support_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _SUPPORT_FUNCTIONS_H_ +#define _SUPPORT_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup groupSupport Support Functions + */ + + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + const q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + const q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + const q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + const q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + const q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + const q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + + + /** + * @brief Struct for specifying sorting algorithm + */ + typedef enum + { + ARM_SORT_BITONIC = 0, + /**< Bitonic sort */ + ARM_SORT_BUBBLE = 1, + /**< Bubble sort */ + ARM_SORT_HEAP = 2, + /**< Heap sort */ + ARM_SORT_INSERTION = 3, + /**< Insertion sort */ + ARM_SORT_QUICK = 4, + /**< Quick sort */ + ARM_SORT_SELECTION = 5 + /**< Selection sort */ + } arm_sort_alg; + + /** + * @brief Struct for specifying sorting algorithm + */ + typedef enum + { + ARM_SORT_DESCENDING = 0, + /**< Descending order (9 to 0) */ + ARM_SORT_ASCENDING = 1 + /**< Ascending order (0 to 9) */ + } arm_sort_dir; + + /** + * @brief Instance structure for the sorting algorithms. + */ + typedef struct + { + arm_sort_alg alg; /**< Sorting algorithm selected */ + arm_sort_dir dir; /**< Sorting order (direction) */ + } arm_sort_instance_f32; + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] alg Selected algorithm. + * @param[in] dir Sorting order. + */ + void arm_sort_init_f32( + arm_sort_instance_f32 * S, + arm_sort_alg alg, + arm_sort_dir dir); + + /** + * @brief Instance structure for the sorting algorithms. + */ + typedef struct + { + arm_sort_dir dir; /**< Sorting order (direction) */ + float32_t * buffer; /**< Working buffer */ + } arm_merge_sort_instance_f32; + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in,out] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_merge_sort_f32( + const arm_merge_sort_instance_f32 * S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] dir Sorting order. + * @param[in] buffer Working buffer. + */ + void arm_merge_sort_init_f32( + arm_merge_sort_instance_f32 * S, + arm_sort_dir dir, + float32_t * buffer); + + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f64( + float64_t value, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + + + + + + +/** + * @brief Weighted sum + * + * + * @param[in] *in Array of input values. + * @param[in] *weigths Weights + * @param[in] blockSize Number of samples in the input array. + * @return Weighted sum + * + */ +float32_t arm_weighted_sum_f32(const float32_t *in + , const float32_t *weigths + , uint32_t blockSize); + + +/** + * @brief Barycenter + * + * + * @param[in] in List of vectors + * @param[in] weights Weights of the vectors + * @param[out] out Barycenter + * @param[in] nbVectors Number of vectors + * @param[in] vecDim Dimension of space (vector dimension) + * @return None + * + */ +void arm_barycenter_f32(const float32_t *in + , const float32_t *weights + , float32_t *out + , uint32_t nbVectors + , uint32_t vecDim); + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _SUPPORT_FUNCTIONS_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/support_functions_f16.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/support_functions_f16.h new file mode 100644 index 00000000..47b6535f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/support_functions_f16.h @@ -0,0 +1,129 @@ +/****************************************************************************** + * @file support_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _SUPPORT_FUNCTIONS_F16_H_ +#define _SUPPORT_FUNCTIONS_F16_H_ + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_copy_f16(const float16_t * pSrc, float16_t * pDst, uint32_t blockSize); + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_fill_f16(float16_t value, float16_t * pDst, uint32_t blockSize); + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the f16 input vector + * @param[out] pDst points to the q15 output vector + * @param[in] blockSize length of the input vector + */ +void arm_f16_to_q15(const float16_t * pSrc, q15_t * pDst, uint32_t blockSize); + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the q15 input vector + * @param[out] pDst points to the f16 output vector + * @param[in] blockSize length of the input vector + */ +void arm_q15_to_f16(const q15_t * pSrc, float16_t * pDst, uint32_t blockSize); + + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the f32 input vector + * @param[out] pDst points to the f16 output vector + * @param[in] blockSize length of the input vector + */ +void arm_float_to_f16(const float32_t * pSrc, float16_t * pDst, uint32_t blockSize); + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the f16 input vector + * @param[out] pDst points to the f32 output vector + * @param[in] blockSize length of the input vector + */ +void arm_f16_to_float(const float16_t * pSrc, float32_t * pDst, uint32_t blockSize); + +/** + * @brief Weighted sum + * + * + * @param[in] *in Array of input values. + * @param[in] *weigths Weights + * @param[in] blockSize Number of samples in the input array. + * @return Weighted sum + * + */ +float16_t arm_weighted_sum_f16(const float16_t *in + , const float16_t *weigths + , uint32_t blockSize); + +/** + * @brief Barycenter + * + * + * @param[in] in List of vectors + * @param[in] weights Weights of the vectors + * @param[out] out Barycenter + * @param[in] nbVectors Number of vectors + * @param[in] vecDim Dimension of space (vector dimension) + * @return None + * + */ +void arm_barycenter_f16(const float16_t *in + , const float16_t *weights + , float16_t *out + , uint32_t nbVectors + , uint32_t vecDim); + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _SUPPORT_FUNCTIONS_F16_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/svm_defines.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/svm_defines.h new file mode 100644 index 00000000..f93e9530 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/svm_defines.h @@ -0,0 +1,46 @@ +/****************************************************************************** + * @file svm_defines.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _SVM_DEFINES_H_ +#define _SVM_DEFINES_H_ + +/** + * @brief Struct for specifying SVM Kernel + */ +typedef enum +{ + ARM_ML_KERNEL_LINEAR = 0, + /**< Linear kernel */ + ARM_ML_KERNEL_POLYNOMIAL = 1, + /**< Polynomial kernel */ + ARM_ML_KERNEL_RBF = 2, + /**< Radial Basis Function kernel */ + ARM_ML_KERNEL_SIGMOID = 3 + /**< Sigmoid kernel */ +} arm_ml_kernel_type; + +#endif diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/svm_functions.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/svm_functions.h new file mode 100644 index 00000000..3acc6211 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/svm_functions.h @@ -0,0 +1,299 @@ +/****************************************************************************** + * @file svm_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _SVM_FUNCTIONS_H_ +#define _SVM_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" +#include "dsp/svm_defines.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define STEP(x) (x) <= 0 ? 0 : 1 + +/** + * @defgroup groupSVM SVM Functions + * This set of functions is implementing SVM classification on 2 classes. + * The training must be done from scikit-learn. The parameters can be easily + * generated from the scikit-learn object. Some examples are given in + * DSP/Testing/PatternGeneration/SVM.py + * + * If more than 2 classes are needed, the functions in this folder + * will have to be used, as building blocks, to do multi-class classification. + * + * No multi-class classification is provided in this SVM folder. + * + */ + +/** + * @brief Integer exponentiation + * @param[in] x value + * @param[in] nb integer exponent >= 1 + * @return x^nb + * + */ +__STATIC_INLINE float32_t arm_exponent_f32(float32_t x, int32_t nb) +{ + float32_t r = x; + nb --; + while(nb > 0) + { + r = r * x; + nb--; + } + return(r); +} + + + + + +/** + * @brief Instance structure for linear SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ +} arm_svm_linear_instance_f32; + + +/** + * @brief Instance structure for polynomial SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + int32_t degree; /**< Polynomial degree */ + float32_t coef0; /**< Polynomial constant */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_polynomial_instance_f32; + +/** + * @brief Instance structure for rbf SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_rbf_instance_f32; + +/** + * @brief Instance structure for sigmoid SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float32_t coef0; /**< Independent constant */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_sigmoid_instance_f32; + +/** + * @brief SVM linear instance init function + * @param[in] S Parameters for SVM functions + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @return none. + * + */ + + +void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes); + +/** + * @brief SVM linear prediction + * @param[in] S Pointer to an instance of the linear SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +void arm_svm_linear_predict_f32(const arm_svm_linear_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + +/** + * @brief SVM polynomial instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] degree Polynomial degree + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + + +void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + int32_t degree, + float32_t coef0, + float32_t gamma + ); + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_polynomial_predict_f32(const arm_svm_polynomial_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + +/** + * @brief SVM radial basis function instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t gamma + ); + +/** + * @brief SVM rbf prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult decision value + * @return none. + * + */ +void arm_svm_rbf_predict_f32(const arm_svm_rbf_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + +/** + * @brief SVM sigmoid instance init function + * @param[in] S points to an instance of the rbf SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t coef0, + float32_t gamma + ); + +/** + * @brief SVM sigmoid prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_sigmoid_predict_f32(const arm_svm_sigmoid_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _SVM_FUNCTIONS_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/svm_functions_f16.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/svm_functions_f16.h new file mode 100644 index 00000000..b80ed7cf --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/svm_functions_f16.h @@ -0,0 +1,298 @@ +/****************************************************************************** + * @file svm_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _SVM_FUNCTIONS_F16_H_ +#define _SVM_FUNCTIONS_F16_H_ + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" +#include "dsp/svm_defines.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + +#define STEP(x) (x) <= 0 ? 0 : 1 + +/** + * @defgroup groupSVM SVM Functions + * This set of functions is implementing SVM classification on 2 classes. + * The training must be done from scikit-learn. The parameters can be easily + * generated from the scikit-learn object. Some examples are given in + * DSP/Testing/PatternGeneration/SVM.py + * + * If more than 2 classes are needed, the functions in this folder + * will have to be used, as building blocks, to do multi-class classification. + * + * No multi-class classification is provided in this SVM folder. + * + */ + +/** + * @brief Integer exponentiation + * @param[in] x value + * @param[in] nb integer exponent >= 1 + * @return x^nb + * + */ +__STATIC_INLINE float16_t arm_exponent_f16(float16_t x, int32_t nb) +{ + float16_t r = x; + nb --; + while(nb > 0) + { + r = r * x; + nb--; + } + return(r); +} + + +/** + * @brief Instance structure for linear SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float16_t intercept; /**< Intercept */ + const float16_t *dualCoefficients; /**< Dual coefficients */ + const float16_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ +} arm_svm_linear_instance_f16; + + +/** + * @brief Instance structure for polynomial SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float16_t intercept; /**< Intercept */ + const float16_t *dualCoefficients; /**< Dual coefficients */ + const float16_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + int32_t degree; /**< Polynomial degree */ + float16_t coef0; /**< Polynomial constant */ + float16_t gamma; /**< Gamma factor */ +} arm_svm_polynomial_instance_f16; + +/** + * @brief Instance structure for rbf SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float16_t intercept; /**< Intercept */ + const float16_t *dualCoefficients; /**< Dual coefficients */ + const float16_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float16_t gamma; /**< Gamma factor */ +} arm_svm_rbf_instance_f16; + +/** + * @brief Instance structure for sigmoid SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float16_t intercept; /**< Intercept */ + const float16_t *dualCoefficients; /**< Dual coefficients */ + const float16_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float16_t coef0; /**< Independent constant */ + float16_t gamma; /**< Gamma factor */ +} arm_svm_sigmoid_instance_f16; + +/** + * @brief SVM linear instance init function + * @param[in] S Parameters for SVM functions + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @return none. + * + */ + + +void arm_svm_linear_init_f16(arm_svm_linear_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes); + +/** + * @brief SVM linear prediction + * @param[in] S Pointer to an instance of the linear SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +void arm_svm_linear_predict_f16(const arm_svm_linear_instance_f16 *S, + const float16_t * in, + int32_t * pResult); + + +/** + * @brief SVM polynomial instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] degree Polynomial degree + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + + +void arm_svm_polynomial_init_f16(arm_svm_polynomial_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + int32_t degree, + float16_t coef0, + float16_t gamma + ); + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_polynomial_predict_f16(const arm_svm_polynomial_instance_f16 *S, + const float16_t * in, + int32_t * pResult); + + +/** + * @brief SVM radial basis function instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_rbf_init_f16(arm_svm_rbf_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + float16_t gamma + ); + +/** + * @brief SVM rbf prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult decision value + * @return none. + * + */ +void arm_svm_rbf_predict_f16(const arm_svm_rbf_instance_f16 *S, + const float16_t * in, + int32_t * pResult); + +/** + * @brief SVM sigmoid instance init function + * @param[in] S points to an instance of the rbf SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_sigmoid_init_f16(arm_svm_sigmoid_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + float16_t coef0, + float16_t gamma + ); + +/** + * @brief SVM sigmoid prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_sigmoid_predict_f16(const arm_svm_sigmoid_instance_f16 *S, + const float16_t * in, + int32_t * pResult); + + + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _SVM_FUNCTIONS_F16_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/transform_functions.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/transform_functions.h new file mode 100644 index 00000000..6270e10c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/transform_functions.h @@ -0,0 +1,735 @@ +/****************************************************************************** + * @file transform_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _TRANSFORM_FUNCTIONS_H_ +#define _TRANSFORM_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/basic_math_functions.h" +#include "dsp/complex_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @defgroup groupTransforms Transform Functions + */ + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + + + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const q15_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const q15_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const q15_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_q15; + +arm_status arm_cfft_init_q15( + arm_cfft_instance_q15 * S, + uint16_t fftLen); + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const q31_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const q31_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const q31_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_q31; + +arm_status arm_cfft_init_q31( + arm_cfft_instance_q31 * S, + uint16_t fftLen); + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const float32_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const float32_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const float32_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_f32; + + + + arm_status arm_cfft_init_f32( + arm_cfft_instance_f32 * S, + uint16_t fftLen); + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + + /** + * @brief Instance structure for the Double Precision Floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float64_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f64; + + arm_status arm_cfft_init_f64( + arm_cfft_instance_f64 * S, + uint16_t fftLen); + + void arm_cfft_f64( + const arm_cfft_instance_f64 * S, + float64_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + arm_cfft_instance_q15 cfftInst; +#else + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ +#endif + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + arm_cfft_instance_q31 cfftInst; +#else + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ +#endif + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the Double Precision Floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f64 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float64_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f64 ; + +arm_status arm_rfft_fast_init_f64 ( + arm_rfft_fast_instance_f64 * S, + uint16_t fftLen); + + +void arm_rfft_fast_f64( + arm_rfft_fast_instance_f64 * S, + float64_t * p, float64_t * pOut, + uint8_t ifftFlag); + + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + + + void arm_rfft_fast_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + const float32_t *pTwiddle; /**< points to the twiddle factor table. */ + const float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Instance structure for the Floating-point MFCC function. + */ +typedef struct + { + const float32_t *dctCoefs; /**< Internal DCT coefficients */ + const float32_t *filterCoefs; /**< Internal Mel filter coefficients */ + const float32_t *windowCoefs; /**< Windowing coefficients */ + const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */ + const uint32_t *filterLengths; /**< Internal Mel filter lengths */ + uint32_t fftLen; /**< FFT length */ + uint32_t nbMelFilters; /**< Number of Mel filters */ + uint32_t nbDctOutputs; /**< Number of DCT outputs */ +#if defined(ARM_MFCC_CFFT_BASED) + /* Implementation of the MFCC is using a CFFT */ + arm_cfft_instance_f32 cfft; /**< Internal CFFT instance */ +#else + /* Implementation of the MFCC is using a RFFT (default) */ + arm_rfft_fast_instance_f32 rfft; +#endif + } arm_mfcc_instance_f32 ; + +arm_status arm_mfcc_init_f32( + arm_mfcc_instance_f32 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const float32_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const float32_t *filterCoefs, + const float32_t *windowCoefs + ); + + +/** + @brief MFCC F32 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples + @param[out] pDst points to the output MFCC values + @param[inout] pTmp points to a temporary buffer of complex + @return none + */ + void arm_mfcc_f32( + const arm_mfcc_instance_f32 * S, + float32_t *pSrc, + float32_t *pDst, + float32_t *pTmp + ); + +typedef struct + { + const q31_t *dctCoefs; /**< Internal DCT coefficients */ + const q31_t *filterCoefs; /**< Internal Mel filter coefficients */ + const q31_t *windowCoefs; /**< Windowing coefficients */ + const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */ + const uint32_t *filterLengths; /**< Internal Mel filter lengths */ + uint32_t fftLen; /**< FFT length */ + uint32_t nbMelFilters; /**< Number of Mel filters */ + uint32_t nbDctOutputs; /**< Number of DCT outputs */ +#if defined(ARM_MFCC_CFFT_BASED) + /* Implementation of the MFCC is using a CFFT */ + arm_cfft_instance_q31 cfft; /**< Internal CFFT instance */ +#else + /* Implementation of the MFCC is using a RFFT (default) */ + arm_rfft_instance_q31 rfft; +#endif + } arm_mfcc_instance_q31 ; + +arm_status arm_mfcc_init_q31( + arm_mfcc_instance_q31 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const q31_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const q31_t *filterCoefs, + const q31_t *windowCoefs + ); + + +/** + @brief MFCC Q31 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples + @param[out] pDst points to the output MFCC values + @param[inout] pTmp points to a temporary buffer of complex + @return none + */ + arm_status arm_mfcc_q31( + const arm_mfcc_instance_q31 * S, + q31_t *pSrc, + q31_t *pDst, + q31_t *pTmp + ); + +typedef struct + { + const q15_t *dctCoefs; /**< Internal DCT coefficients */ + const q15_t *filterCoefs; /**< Internal Mel filter coefficients */ + const q15_t *windowCoefs; /**< Windowing coefficients */ + const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */ + const uint32_t *filterLengths; /**< Internal Mel filter lengths */ + uint32_t fftLen; /**< FFT length */ + uint32_t nbMelFilters; /**< Number of Mel filters */ + uint32_t nbDctOutputs; /**< Number of DCT outputs */ +#if defined(ARM_MFCC_CFFT_BASED) + /* Implementation of the MFCC is using a CFFT */ + arm_cfft_instance_q15 cfft; /**< Internal CFFT instance */ +#else + /* Implementation of the MFCC is using a RFFT (default) */ + arm_rfft_instance_q15 rfft; +#endif + } arm_mfcc_instance_q15 ; + +arm_status arm_mfcc_init_q15( + arm_mfcc_instance_q15 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const q15_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const q15_t *filterCoefs, + const q15_t *windowCoefs + ); + + +/** + @brief MFCC Q15 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples + @param[out] pDst points to the output MFCC values in q8.7 format + @param[inout] pTmp points to a temporary buffer of complex + @return error status + */ + arm_status arm_mfcc_q15( + const arm_mfcc_instance_q15 * S, + q15_t *pSrc, + q15_t *pDst, + q31_t *pTmp + ); + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _TRANSFORM_FUNCTIONS_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/transform_functions_f16.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/transform_functions_f16.h new file mode 100644 index 00000000..67f1adc2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/transform_functions_f16.h @@ -0,0 +1,157 @@ +/****************************************************************************** + * @file transform_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _TRANSFORM_FUNCTIONS_F16_H_ +#define _TRANSFORM_FUNCTIONS_F16_H_ + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +#if defined(ARM_FLOAT16_SUPPORTED) + + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float16_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float16_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f16; + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float16_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float16_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f16; + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float16_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const float16_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const float16_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const float16_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_f16; + + + arm_status arm_cfft_init_f16( + arm_cfft_instance_f16 * S, + uint16_t fftLen); + + void arm_cfft_f16( + const arm_cfft_instance_f16 * S, + float16_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f16 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float16_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f16 ; + +arm_status arm_rfft_fast_init_f16 ( + arm_rfft_fast_instance_f16 * S, + uint16_t fftLen); + + + void arm_rfft_fast_f16( + const arm_rfft_fast_instance_f16 * S, + float16_t * p, float16_t * pOut, + uint8_t ifftFlag); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f16( + arm_cfft_radix4_instance_f16 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f16( + const arm_cfft_radix4_instance_f16 * S, + float16_t * pSrc); + + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f16( + arm_cfft_radix2_instance_f16 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f16( + const arm_cfft_radix2_instance_f16 * S, + float16_t * pSrc); + +#endif /* defined(ARM_FLOAT16_SUPPORTED)*/ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _TRANSFORM_FUNCTIONS_F16_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/utils.h b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/utils.h new file mode 100644 index 00000000..7f5acb37 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Include/dsp/utils.h @@ -0,0 +1,240 @@ +/****************************************************************************** + * @file arm_math_utils.h + * @brief Public header file for CMSIS DSP Library + * @version V1.9.0 + * @date 20. July 2020 + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_MATH_UTILS_H_ + +#define _ARM_MATH_UTILS_H_ + +#include "arm_math_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define INDEX_MASK 0x0000003F + + +#define SQ(x) ((x) * (x)) + +#define ROUND_UP(N, S) ((((N) + (S) - 1) / (S)) * (S)) + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + __STATIC_FORCEINLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + const q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + __STATIC_FORCEINLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + const q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + +/** + * @brief 64-bit to 32-bit unsigned normalization + * @param[in] in is input unsigned long long value + * @param[out] normalized is the 32-bit normalized value + * @param[out] norm is norm scale + */ +__STATIC_INLINE void arm_norm_64_to_32u(uint64_t in, int32_t * normalized, int32_t *norm) +{ + int32_t n1; + int32_t hi = (int32_t) (in >> 32); + int32_t lo = (int32_t) ((in << 32) >> 32); + + n1 = __CLZ(hi) - 32; + if (!n1) + { + /* + * input fits in 32-bit + */ + n1 = __CLZ(lo); + if (!n1) + { + /* + * MSB set, need to scale down by 1 + */ + *norm = -1; + *normalized = (((uint32_t) lo) >> 1); + } else + { + if (n1 == 32) + { + /* + * input is zero + */ + *norm = 0; + *normalized = 0; + } else + { + /* + * 32-bit normalization + */ + *norm = n1 - 1; + *normalized = lo << *norm; + } + } + } else + { + /* + * input fits in 64-bit + */ + n1 = 1 - n1; + *norm = -n1; + /* + * 64 bit normalization + */ + *normalized = (((uint32_t) lo) >> n1) | (hi << (32 - n1)); + } +} + +__STATIC_INLINE q31_t arm_div_q63_to_q31(q63_t num, q31_t den) +{ + q31_t result; + uint64_t absNum; + int32_t normalized; + int32_t norm; + + /* + * if sum fits in 32bits + * avoid costly 64-bit division + */ + absNum = num > 0 ? num : -num; + arm_norm_64_to_32u(absNum, &normalized, &norm); + if (norm > 0) + /* + * 32-bit division + */ + result = (q31_t) num / den; + else + /* + * 64-bit division + */ + result = (q31_t) (num / den); + + return result; +} + + +#ifdef __cplusplus +} +#endif + +#endif /*ifndef _ARM_MATH_UTILS_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/PrivateInclude/arm_sorting.h b/benchmark/interface/Drivers/CMSIS/DSP/PrivateInclude/arm_sorting.h new file mode 100644 index 00000000..ec002b2f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/PrivateInclude/arm_sorting.h @@ -0,0 +1,200 @@ +/****************************************************************************** + * @file arm_sorting.h + * @brief Private header file for CMSIS DSP Library + * @version V1.7.0 + * @date 2019 + ******************************************************************************/ +/* + * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_SORTING_H_ +#define _ARM_SORTING_H_ + +#include "arm_math.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_bubble_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_heap_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_insertion_sort_f32( + const arm_sort_instance_f32 * S, + float32_t *pSrc, + float32_t* pDst, + uint32_t blockSize); + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_quick_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_selection_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_bitonic_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +#if defined(ARM_MATH_NEON) + +#define vtrn256_128q(a, b) \ +do { \ + float32x4_t vtrn128_temp = a.val[1]; \ + a.val[1] = b.val[0]; \ + b.val[0] = vtrn128_temp ; \ +} while (0) + +#define vtrn128_64q(a, b) \ +do { \ + float32x2_t ab, cd, ef, gh; \ + ab = vget_low_f32(a); \ + ef = vget_low_f32(b); \ + cd = vget_high_f32(a); \ + gh = vget_high_f32(b); \ + a = vcombine_f32(ab, ef); \ + b = vcombine_f32(cd, gh); \ +} while (0) + +#define vtrn256_64q(a, b) \ +do { \ + float32x2_t a_0, a_1, a_2, a_3; \ + float32x2_t b_0, b_1, b_2, b_3; \ + a_0 = vget_low_f32(a.val[0]); \ + a_1 = vget_high_f32(a.val[0]); \ + a_2 = vget_low_f32(a.val[1]); \ + a_3 = vget_high_f32(a.val[1]); \ + b_0 = vget_low_f32(b.val[0]); \ + b_1 = vget_high_f32(b.val[0]); \ + b_2 = vget_low_f32(b.val[1]); \ + b_3 = vget_high_f32(b.val[1]); \ + a.val[0] = vcombine_f32(a_0, b_0); \ + a.val[1] = vcombine_f32(a_2, b_2); \ + b.val[0] = vcombine_f32(a_1, b_1); \ + b.val[1] = vcombine_f32(a_3, b_3); \ +} while (0) + +#define vtrn128_32q(a, b) \ +do { \ + float32x4x2_t vtrn32_tmp = vtrnq_f32((a), (b)); \ + (a) = vtrn32_tmp.val[0]; \ + (b) = vtrn32_tmp.val[1]; \ +} while (0) + +#define vtrn256_32q(a, b) \ +do { \ + float32x4x2_t vtrn32_tmp_1 = vtrnq_f32((a.val[0]), (b.val[0])); \ + float32x4x2_t vtrn32_tmp_2 = vtrnq_f32((a.val[1]), (b.val[1])); \ + a.val[0] = vtrn32_tmp_1.val[0]; \ + a.val[1] = vtrn32_tmp_2.val[0]; \ + b.val[0] = vtrn32_tmp_1.val[1]; \ + b.val[1] = vtrn32_tmp_2.val[1]; \ +} while (0) + +#define vminmaxq(a, b) \ + do { \ + float32x4_t minmax_tmp = (a); \ + (a) = vminq_f32((a), (b)); \ + (b) = vmaxq_f32(minmax_tmp, (b)); \ +} while (0) + +#define vminmax256q(a, b) \ + do { \ + float32x4x2_t minmax256_tmp = (a); \ + a.val[0] = vminq_f32(a.val[0], b.val[0]); \ + a.val[1] = vminq_f32(a.val[1], b.val[1]); \ + b.val[0] = vmaxq_f32(minmax256_tmp.val[0], b.val[0]); \ + b.val[1] = vmaxq_f32(minmax256_tmp.val[1], b.val[1]); \ +} while (0) + +#define vrev128q_f32(a) \ + vcombine_f32(vrev64_f32(vget_high_f32(a)), vrev64_f32(vget_low_f32(a))) + +#define vrev256q_f32(a) \ + do { \ + float32x4_t rev_tmp = vcombine_f32(vrev64_f32(vget_high_f32(a.val[0])), vrev64_f32(vget_low_f32(a.val[0]))); \ + a.val[0] = vcombine_f32(vrev64_f32(vget_high_f32(a.val[1])), vrev64_f32(vget_low_f32(a.val[1]))); \ + a.val[1] = rev_tmp; \ +} while (0) + +#define vldrev128q_f32(a, p) \ + do { \ + a = vld1q_f32(p); \ + a = vrev128q_f32(a); \ +} while (0) + +#endif /* ARM_MATH_NEON */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ARM_SORTING_H */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/PrivateInclude/arm_vec_fft.h b/benchmark/interface/Drivers/CMSIS/DSP/PrivateInclude/arm_vec_fft.h new file mode 100644 index 00000000..fdf6498c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/PrivateInclude/arm_vec_fft.h @@ -0,0 +1,325 @@ +/****************************************************************************** + * @file arm_vec_fft.h + * @brief Private header file for CMSIS DSP Library + * @version V1.7.0 + * @date 07. January 2020 + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_VEC_FFT_H_ +#define _ARM_VEC_FFT_H_ + +#include "arm_math.h" +#include "arm_helium_utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MVE_CMPLX_ADD_A_ixB(A, B) vcaddq_rot90(A,B) +#define MVE_CMPLX_SUB_A_ixB(A,B) vcaddq_rot270(A,B) +#define MVE_CMPLX_MULT_FLT_AxB(A,B) vcmlaq_rot90(vcmulq(A, B), A, B) +#define MVE_CMPLX_MULT_FLT_Conj_AxB(A,B) vcmlaq_rot270(vcmulq(A, B), A, B) + +#define MVE_CMPLX_MULT_FX_AxB(A,B,TyA) vqdmladhxq(vqdmlsdhq((TyA)vuninitializedq_s32(), A, B), A, B) +#define MVE_CMPLX_MULT_FX_AxConjB(A,B,TyA) vqdmladhq(vqdmlsdhxq((TyA)vuninitializedq_s32(), A, B), A, B) + +#define MVE_CMPLX_ADD_FX_A_ixB(A, B) vhcaddq_rot90(A,B) +#define MVE_CMPLX_SUB_FX_A_ixB(A,B) vhcaddq_rot270(A,B) + + +/** + @brief In-place 32 bit reversal function for helium + @param[in,out] pSrc points to in-place buffer of unknown 32-bit data type + @param[in] bitRevLen bit reversal table length + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +__STATIC_INLINE void arm_bitreversal_32_inpl_mve( + uint32_t *pSrc, + const uint16_t bitRevLen, + const uint16_t *pBitRevTab) + +{ + uint64_t *src = (uint64_t *) pSrc; + int32_t blkCnt; /* loop counters */ + uint32x4_t bitRevTabOff; + uint32x4_t one = vdupq_n_u32(1); + uint64x2_t inLow, inHigh; + uint64x2_t bitRevOff1Low, bitRevOff0Low; + uint64x2_t bitRevOff1High, bitRevOff0High; + + /* load scheduling to increase gather load idx update / gather load distance */ + bitRevTabOff = vldrhq_u32(pBitRevTab); + pBitRevTab += 4; + + bitRevOff0Low = vmullbq_int_u32(bitRevTabOff, one); + bitRevOff0High = vmulltq_int_u32(bitRevTabOff, one); + + + blkCnt = bitRevLen / 8; + while (blkCnt > 0) { + bitRevTabOff = vldrhq_u32(pBitRevTab); + pBitRevTab += 4; + + /* 64-bit index expansion */ + bitRevOff1Low = vmullbq_int_u32(bitRevTabOff, one); + bitRevOff1High = vmulltq_int_u32(bitRevTabOff, one); + + inLow = vldrdq_gather_offset_u64(src, bitRevOff0Low); + inHigh = vldrdq_gather_offset_u64(src, bitRevOff0High); + + vstrdq_scatter_offset_u64(src, bitRevOff0Low, inHigh); + vstrdq_scatter_offset_u64(src, bitRevOff0High, inLow); + + + /* unrolled */ + bitRevTabOff = vldrhq_u32(pBitRevTab); + pBitRevTab += 4; + + bitRevOff0Low = vmullbq_int_u32(bitRevTabOff, one); + bitRevOff0High = vmulltq_int_u32(bitRevTabOff, one); + + inLow = vldrdq_gather_offset_u64(src, bitRevOff1Low); + inHigh = vldrdq_gather_offset_u64(src, bitRevOff1High); + + vstrdq_scatter_offset_u64(src, bitRevOff1Low, inHigh); + vstrdq_scatter_offset_u64(src, bitRevOff1High, inLow); + + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + if (bitRevLen & 7) { + /* FFT size = 16 */ + inLow = vldrdq_gather_offset_u64(src, bitRevOff0Low); + inHigh = vldrdq_gather_offset_u64(src, bitRevOff0High); + + vstrdq_scatter_offset_u64(src, bitRevOff0Low, inHigh); + vstrdq_scatter_offset_u64(src, bitRevOff0High, inLow); + } +} + + + +/** + @brief In-place 16 bit reversal function for helium + @param[in,out] pSrc points to in-place buffer of unknown 16-bit data type + @param[in] bitRevLen bit reversal table length + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +__STATIC_INLINE void arm_bitreversal_16_inpl_mve( + uint16_t *pSrc, + const uint16_t bitRevLen, + const uint16_t *pBitRevTab) + +{ + uint32_t *src = (uint32_t *) pSrc; + int32_t blkCnt; /* loop counters */ + uint32x4_t bitRevTabOff; + uint16x8_t one = vdupq_n_u16(1); + uint32x4_t bitRevOff1Low, bitRevOff0Low; + uint32x4_t bitRevOff1High, bitRevOff0High; + uint32x4_t inLow, inHigh; + + /* load scheduling to increase gather load idx update / gather load distance */ + bitRevTabOff = vldrhq_u16(pBitRevTab); + pBitRevTab += 8; + + bitRevOff0Low = vmullbq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff0High = vmulltq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff0Low = vshrq_n_u16((uint16x8_t)bitRevOff0Low, 3); + bitRevOff0High = vshrq_n_u16((uint16x8_t)bitRevOff0High, 3); + + blkCnt = (bitRevLen / 16); + while (blkCnt > 0) { + bitRevTabOff = vldrhq_u16(pBitRevTab); + pBitRevTab += 8; + + bitRevOff1Low = vmullbq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff1High = vmulltq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff1Low = vshrq_n_u16((uint16x8_t)bitRevOff1Low, 3); + bitRevOff1High = vshrq_n_u16((uint16x8_t)bitRevOff1High, 3); + + inLow = vldrwq_gather_shifted_offset_u32(src, bitRevOff0Low); + inHigh = vldrwq_gather_shifted_offset_u32(src, bitRevOff0High); + + vstrwq_scatter_shifted_offset_u32(src, bitRevOff0Low, inHigh); + vstrwq_scatter_shifted_offset_u32(src, bitRevOff0High, inLow); + + /* loop unrolling */ + bitRevTabOff = vldrhq_u16(pBitRevTab); + pBitRevTab += 8; + + bitRevOff0Low = vmullbq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff0High = vmulltq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff0Low = vshrq_n_u16((uint16x8_t)bitRevOff0Low, 3); + bitRevOff0High = vshrq_n_u16((uint16x8_t)bitRevOff0High, 3); + + inLow = vldrwq_gather_shifted_offset_u32(src, bitRevOff1Low); + inHigh = vldrwq_gather_shifted_offset_u32(src, bitRevOff1High); + + vstrwq_scatter_shifted_offset_u32(src, bitRevOff1Low, inHigh); + vstrwq_scatter_shifted_offset_u32(src, bitRevOff1High, inLow); + + blkCnt--; + } + + /* tail handling */ + blkCnt = bitRevLen & 0xf; + if (blkCnt == 8) { + inLow = vldrwq_gather_shifted_offset_u32(src, bitRevOff0Low); + inHigh = vldrwq_gather_shifted_offset_u32(src, bitRevOff0High); + + vstrwq_scatter_shifted_offset_u32(src, bitRevOff0Low, inHigh); + vstrwq_scatter_shifted_offset_u32(src, bitRevOff0High, inLow); + } else if (blkCnt == 12) { + /* FFT 16 special case */ + mve_pred16_t p = vctp16q(4); + + bitRevTabOff = vldrhq_z_u16(pBitRevTab, p); + + inLow = vldrwq_gather_shifted_offset_u32(src, bitRevOff0Low); + inHigh = vldrwq_gather_shifted_offset_u32(src, bitRevOff0High); + + vstrwq_scatter_shifted_offset_u32(src, bitRevOff0Low, inHigh); + vstrwq_scatter_shifted_offset_u32(src, bitRevOff0High, inLow); + + bitRevOff0Low = vmullbq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff0High = vmulltq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff0Low = vshrq_n_u16((uint16x8_t)bitRevOff0Low, 3); + bitRevOff0High = vshrq_n_u16((uint16x8_t)bitRevOff0High, 3); + + inLow = vldrwq_gather_shifted_offset_z_u32(src, bitRevOff0Low, p); + inHigh = vldrwq_gather_shifted_offset_z_u32(src, bitRevOff0High, p); + + vstrwq_scatter_shifted_offset_p_u32(src, bitRevOff0Low, inHigh, p); + vstrwq_scatter_shifted_offset_p_u32(src, bitRevOff0High, inLow, p); + } +} + +/** + @brief Out-of-place 32 bit reversal function for helium + @param[out] pDst points to destination buffer of unknown 32-bit data type + @param[in] pSrc points to input buffer of unknown 32-bit data type + @param[in] fftLen FFT length + @return none +*/ +__STATIC_INLINE void arm_bitreversal_32_outpl_mve(void *pDst, void *pSrc, uint32_t fftLen) +{ + uint32x4_t idxOffs0, idxOffs1, bitRevOffs0, bitRevOffs1; + uint32_t bitRevPos, blkCnt; + uint32_t *pDst32 = (uint32_t *) pDst; + + /* fwd indexes */ + idxOffs0 = vdupq_n_u32(0); + idxOffs1 = vdupq_n_u32(0); + idxOffs0[0] = 0; idxOffs0[2] = 4; + idxOffs1[0] = 8; idxOffs1[2] = 12; + + bitRevPos = (31 - __CLZ(fftLen)) + 5; + blkCnt = fftLen >> 2; + + /* issued earlier to increase gather load idx update / gather load distance */ + /* bit-reverse fwd indexes */ + bitRevOffs0 = vbrsrq(idxOffs0, bitRevPos); + bitRevOffs1 = vbrsrq(idxOffs1, bitRevPos); + while (blkCnt > 0) { + uint64x2_t vecIn; + + vecIn = vldrdq_gather_offset_u64(pSrc, (uint64x2_t) bitRevOffs0); + idxOffs0 = idxOffs0 + 16; + vst1q(pDst32, (uint32x4_t) vecIn); + pDst32 += 4; + bitRevOffs0 = vbrsrq(idxOffs0, bitRevPos); + + vecIn = vldrdq_gather_offset_u64(pSrc, (uint64x2_t) bitRevOffs1); + idxOffs1 = idxOffs1 + 16; + vst1q(pDst32, (uint32x4_t) vecIn); + pDst32 += 4; + bitRevOffs1 = vbrsrq(idxOffs1, bitRevPos); + + blkCnt--; + } +} + + +/** + @brief Out-of-place 16 bit reversal function for helium + @param[out] pDst points to destination buffer of unknown 16-bit data type + @param[in] pSrc points to input buffer of unknown 16-bit data type + @param[in] fftLen FFT length + @return none +*/ + +__STATIC_INLINE void arm_bitreversal_16_outpl_mve(void *pDst, void *pSrc, uint32_t fftLen) +{ + uint32x4_t idxOffs0, idxOffs1, bitRevOffs0, bitRevOffs1; + uint32_t bitRevPos, blkCnt; + uint16_t *pDst16 = (uint16_t *) pDst; + uint32_t incrIdx = 0; + + /* fwd indexes */ + idxOffs0 = vidupq_wb_u32(&incrIdx, 4); // {0, 4, 8, 12} + idxOffs1 = vidupq_wb_u32(&incrIdx, 4); // {16, 20, 24, 28} + + bitRevPos = (31 - __CLZ(fftLen)) + 4; + blkCnt = fftLen >> 3; + + /* issued earlier to increase gather load idx update / gather load distance */ + /* bit-reverse fwd indexes */ + bitRevOffs0 = vbrsrq(idxOffs0, bitRevPos); + bitRevOffs1 = vbrsrq(idxOffs1, bitRevPos); + while (blkCnt > 0) { + uint32x4_t vecIn; + + vecIn = vldrwq_gather_offset_s32(pSrc, bitRevOffs0); + idxOffs0 = idxOffs0 + 32; + vst1q(pDst16, (uint16x8_t) vecIn); + pDst16 += 8; + bitRevOffs0 = vbrsrq(idxOffs0, bitRevPos); + + vecIn = vldrwq_gather_offset_s32(pSrc, bitRevOffs1); + idxOffs1 = idxOffs1 + 32; + vst1q(pDst16, (uint16x8_t) vecIn); + pDst16 += 8; + bitRevOffs1 = vbrsrq(idxOffs1, bitRevPos); + + blkCnt--; + } +} + + +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/ + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_VEC_FFT_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/PrivateInclude/arm_vec_filtering.h b/benchmark/interface/Drivers/CMSIS/DSP/PrivateInclude/arm_vec_filtering.h new file mode 100644 index 00000000..b2a06903 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/PrivateInclude/arm_vec_filtering.h @@ -0,0 +1,1586 @@ +/****************************************************************************** + * @file arm_vec_filtering.h + * @brief Private header file for CMSIS DSP Library + * @version V1.7.0 + * @date 30. October 2019 + ******************************************************************************/ +/* + * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_VEC_FILTERING_H_ +#define _ARM_VEC_FILTERING_H_ + +#include "arm_math.h" +#include "arm_helium_utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_F32(acc0, acc1, acc2, acc3, pX, pY, count)\ +{ \ + float32_t const *pSrcX, *pSrcY; \ + f32x4_t acc0Vec, acc1Vec, acc2Vec, acc3Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f32(0.0f); \ + acc1Vec = vdupq_n_f32(0.0f); \ + acc2Vec = vdupq_n_f32(0.0f); \ + acc3Vec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + pSrcY = (float32_t const *) pY; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \ + xVec = vldrwq_f32(&pSrcX[2]); \ + acc2Vec = vfmaq_f32(acc2Vec, xVec, yVec); \ + xVec = vldrwq_f32(&pSrcX[3]); \ + acc3Vec = vfmaq_f32(acc3Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \ + xVec = vldrwq_f32(&pSrcX[2]); \ + acc2Vec = vfmaq_m_f32(acc2Vec, xVec, yVec, p0); \ + xVec = vldrwq_f32(&pSrcX[3]); \ + acc3Vec = vfmaq_m_f32(acc3Vec, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \ + } \ + \ + acc0 = vecAddAcrossF32Mve(acc0Vec); \ + acc1 = vecAddAcrossF32Mve(acc1Vec); \ + acc2 = vecAddAcrossF32Mve(acc2Vec); \ + acc3 = vecAddAcrossF32Mve(acc3Vec); \ +} + +#define MVE_INTR_CORR_SINGLE_F32(acc, pX, pY, count) \ +{ \ + float32_t const *pSrcX, *pSrcY; \ + f32x4_t accVec, xVec, yVec; \ + uint32_t k; \ + \ + accVec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + pSrcY = (float32_t const *) pY; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + accVec = vfmaq_f32(accVec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + accVec = vfmaq_m_f32(accVec, xVec, yVec, p0);\ + } \ + acc = vecAddAcrossF32Mve(accVec); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_F32(acc0, acc1, pX, pY, count)\ +{ \ + float32_t const *pSrcX, *pSrcY; \ + f32x4_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f32(0.0f); \ + acc1Vec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + pSrcY = (float32_t const *) pY; \ + k = (count-1) >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + k = (count-1) % 0x4U; \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp32q(k+1); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \ + \ + acc0 = vecAddAcrossF32Mve(acc0Vec); \ + acc1 = vecAddAcrossF32Mve(acc1Vec); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_F32(acc0, acc1, pX, pY, count)\ +{ \ + float32_t const *pSrcX, *pSrcY; \ + f32x4_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f32(0.0f); \ + acc1Vec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + pSrcY = (float32_t const *) pY; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \ + } \ + \ + acc0 = vecAddAcrossF32Mve(acc0Vec); \ + acc1 = vecAddAcrossF32Mve(acc1Vec); \ +} + +#define MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_F32(acc0, acc1, pX, pY, count)\ +{ \ + float32_t const *pSrcX, *pSrcY; \ + f32x4_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f32(0.0f); \ + acc1Vec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + pSrcY = (float32_t const *) pY; \ + k = count >> 2; \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + yVec = vldrwq_f32(&pSrcY[-1]); \ + acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x4U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + mve_pred16_t p0 = vctp32q(k+1); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + yVec = vldrwq_f32(&pSrcY[-1]); \ + acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec,p0); \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec,p0); \ + \ + acc0 = vecAddAcrossF32Mve(acc0Vec); \ + acc1 = vecAddAcrossF32Mve(acc1Vec); \ +} + +#define MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_F32(acc0, acc1, pX, pY, count) \ +{ \ + float32_t const *pSrcX; \ + f32x4_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f32(0.0f); \ + acc1Vec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + k = (count - 1) >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + pY-=4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = (count - 1) % 0x4U; \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + p0 = vctp32q(k+1); \ + acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \ + \ + acc0 = vecAddAcrossF32Mve(acc0Vec); \ + acc1 = vecAddAcrossF32Mve(acc1Vec); \ +} + +#define MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_F32(acc0, acc1, pX, pY, count) \ +{ \ + float32_t const *pSrcX; \ + f32x4_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f32(0.0f); \ + acc1Vec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + pY-=4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \ + } \ + acc0 = vecAddAcrossF32Mve(acc0Vec); \ + acc1 = vecAddAcrossF32Mve(acc1Vec); \ +} + +#define MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_F32(acc0, acc1, pX, pY, count)\ +{ \ + float32_t const *pSrcX; \ + const float32_t *pY1 = pY + 1; \ + f32x4_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f32(0.0f); \ + acc1Vec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + pY-=4; \ + acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \ + yVec = vldrwq_gather_shifted_offset_f32(pY1, decrIdxVec); \ + pY1-=4; \ + acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x4U; \ + /* use predication to finalize MAC sum */ \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + mve_pred16_t p0 = vctp32q(k); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \ + yVec = vldrwq_gather_shifted_offset_f32(pY1, decrIdxVec); \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp32q(k+1); \ + acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \ + \ + acc0 = vecAddAcrossF32Mve(acc0Vec); \ + acc1 = vecAddAcrossF32Mve(acc1Vec); \ +} + +#define MVE_INTR_CONV_SINGLE_F32(acc, pX, pY, count) \ +{ \ + float32_t const *pSrcX; \ + f32x4_t accVec, xVec, yVec; \ + uint32_t k; \ + \ + accVec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + pY-=4; \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + accVec = vfmaq_f32(accVec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + accVec = vfmaq_m_f32(accVec, xVec, yVec, p0); \ + } \ + acc = vecAddAcrossF32Mve(accVec); \ +} + +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/ + +#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) + +#define MVE_INTR_CONV_SINGLE_Q31(acc, pX, pY, count) \ +{ \ + q31_t const *pSrcX; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + pY-=4; \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc = vmlaldavaq(acc, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + acc = vmlaldavaq_p(acc, xVec, yVec, p0); \ + } \ + acc = asrl(acc, 31); \ +} + + + +#define MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_Q31(acc0, acc1, pX, pY, count)\ +{ \ + q31_t const *pSrcX; \ + const q31_t *pY1 = pY + 1; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + pY-=4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + yVec = vldrwq_gather_shifted_offset_s32(pY1, decrIdxVec); \ + pY1-=4; \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x4U; \ + /* use predication to finalize MAC sum */ \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + mve_pred16_t p0 = vctp32q(k); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + yVec = vldrwq_gather_shifted_offset_s32(pY1, decrIdxVec); \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp32q(k+1); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ +} + + + + +#define MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_Q31(acc0, acc1, pX, pY, count) \ +{ \ + q31_t const *pSrcX; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + k = (count-1) >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + pY-=4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = (count - 1) % 0x4U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp32q(k+1); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ +} + + + +#define MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_Q31(acc0, acc1, pX, pY, count) \ +{ \ + q31_t const *pSrcX; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + pY-=4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ +} + + + +#define MVE_INTR_CONV_QUAD_INC_X_FIXED_SIZE_Q31(acc0, acc1, acc2, acc3, pX, pY, count) \ +{ \ + q31_t const *pSrcX; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + pY-=4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vldrwq_s32(&pSrcX[2]); \ + acc2 = vmlaldavaq(acc2, xVec, yVec); \ + xVec = vldrwq_s32(&pSrcX[3]); \ + acc3 = vmlaldavaq(acc3, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vldrwq_s32(&pSrcX[2]); \ + acc2 = vmlaldavaq_p(acc2, xVec, yVec, p0); \ + xVec = vldrwq_s32(&pSrcX[3]); \ + acc3 = vmlaldavaq_p(acc3, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ + acc2 = asrl(acc2, 31); \ + acc3 = asrl(acc3, 31); \ +} + +#define MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_Q31(acc0, acc1, pX, pY, count)\ +{ \ + q31_t const *pSrcX, *pSrcY; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + pSrcY = (q31_t const *) pY; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_s32(&pSrcY[-1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x4U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + mve_pred16_t p0 = vctp32q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_s32(&pSrcY[-1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec,p0); \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec,p0); \ + \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ +} + +#define MVE_INTR_CORR_SINGLE_Q31(acc, pX, pY, count)\ +{ \ + q31_t const *pSrcX, *pSrcY; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + pSrcY = (q31_t const *) pY; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + acc = vmlaldavaq(acc, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + acc = vmlaldavaq_p(acc, xVec, yVec, p0); \ + } \ + acc = asrl(acc, 31); \ +} + +#define MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_Q31(acc0, acc1, acc2, acc3, pX, pY, count)\ +{ \ + q31_t const *pSrcX, *pSrcY; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + pSrcY = (q31_t const *) pY; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vldrwq_s32(&pSrcX[2]); \ + acc2 = vmlaldavaq(acc2, xVec, yVec); \ + xVec = vldrwq_s32(&pSrcX[3]); \ + acc3 = vmlaldavaq(acc3, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vldrwq_s32(&pSrcX[2]); \ + acc2 = vmlaldavaq_p(acc2, xVec, yVec, p0); \ + xVec = vldrwq_s32(&pSrcX[3]); \ + acc3 = vmlaldavaq_p(acc3, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ + acc2 = asrl(acc2, 31); \ + acc3 = asrl(acc3, 31); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_Q31(acc0, acc1, pX, pY, count)\ +{ \ + q31_t const *pSrcX, *pSrcY; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + pSrcY = (q31_t const *) pY; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_Q31(acc0, acc1, pX, pY, count)\ +{ \ + q31_t const *pSrcX, *pSrcY; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + pSrcY = (q31_t const *) pY; \ + k = (count-1) >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + k = (count-1) % 0x4U; \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp32q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ +} + +#define MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_Q15(acc0, acc1, pX, pY, count)\ +{ \ + q15_t const *pSrcX, *pSrcY; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + pSrcY = (q15_t const *) pY; \ + k = count >> 3; \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vldrhq_s16(&pSrcY[-1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x8U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + mve_pred16_t p0 = vctp16q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vldrhq_s16(&pSrcY[-1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec,p0); \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec,p0); \ + \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ +} + +#define MVE_INTR_CORR_SINGLE_Q15(acc, pX, pY, count)\ +{ \ + q15_t const *pSrcX, *pSrcY; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + pSrcY = (q15_t const *) pY; \ + k = count >> 3; \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + acc = vmlaldavaq(acc, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + acc = vmlaldavaq_p(acc, xVec, yVec, p0); \ + } \ + acc = asrl(acc, 15); \ + acc = __SSAT(acc, 16); \ +} + +#define MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_Q15(acc0, acc1, acc2, acc3, pX, pY, count)\ +{ \ + q15_t const *pSrcX, *pSrcY; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + pSrcY = (q15_t const *) pY; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vldrhq_s16(&pSrcX[2]); \ + acc2 = vmlaldavaq(acc2, xVec, yVec); \ + xVec = vldrhq_s16(&pSrcX[3]); \ + acc3 = vmlaldavaq(acc3, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vldrhq_s16(&pSrcX[2]); \ + acc2 = vmlaldavaq_p(acc2, xVec, yVec, p0); \ + xVec = vldrhq_s16(&pSrcX[3]); \ + acc3 = vmlaldavaq_p(acc3, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc2 = asrl(acc2, 15); \ + acc3 = asrl(acc3, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ + acc2 = __SSAT(acc2, 16); \ + acc3 = __SSAT(acc3, 16); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_Q15(acc0, acc1, pX, pY, count)\ +{ \ + q15_t const *pSrcX, *pSrcY; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + pSrcY = (q15_t const *) pY; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_Q15(acc0, acc1, pX, pY, count)\ +{ \ + q15_t const *pSrcX, *pSrcY; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + pSrcY = (q15_t const *) pY; \ + k = (count-1) >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + k = (count-1) % 0x8U; \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp16q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ +} + +#define MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_Q15(acc0, acc1, pX, pY, count)\ +{ \ + q15_t const *pSrcX; \ + const q15_t *pY1 = pY + 1; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + pY-=8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + yVec = vldrhq_gather_shifted_offset_s16(pY1, decrIdxVec); \ + pY1-=8; \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x8U; \ + /* use predication to finalize MAC sum */ \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + mve_pred16_t p0 = vctp16q(k); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + yVec = vldrhq_gather_shifted_offset_s16(pY1, decrIdxVec); \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp16q(k+1); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ +} + +#define MVE_INTR_CONV_SINGLE_Q15(acc, pX, pY, count) \ +{ \ + q15_t const *pSrcX; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + pY-=8; \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc = vmlaldavaq(acc, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + acc = vmlaldavaq_p(acc, xVec, yVec, p0); \ + } \ + acc = asrl(acc, 15); \ + acc = __SSAT(acc, 16); \ +} + +#define MVE_INTR_CONV_QUAD_INC_X_FIXED_SIZE_Q15(acc0, acc1, acc2, acc3, pX, pY, count) \ +{ \ + q15_t const *pSrcX; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + pY-=8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vldrhq_s16(&pSrcX[2]); \ + acc2 = vmlaldavaq(acc2, xVec, yVec); \ + xVec = vldrhq_s16(&pSrcX[3]); \ + acc3 = vmlaldavaq(acc3, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vldrhq_s16(&pSrcX[2]); \ + acc2 = vmlaldavaq_p(acc2, xVec, yVec, p0); \ + xVec = vldrhq_s16(&pSrcX[3]); \ + acc3 = vmlaldavaq_p(acc3, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc2 = asrl(acc2, 15); \ + acc3 = asrl(acc3, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ + acc2 = __SSAT(acc2, 16); \ + acc3 = __SSAT(acc3, 16); \ +} + +#define MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_Q15(acc0, acc1, pX, pY, count) \ +{ \ + q15_t const *pSrcX; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + pY-=8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ +} + +#define MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_Q15(acc0, acc1, pX, pY, count) \ +{ \ + q15_t const *pSrcX; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + k = (count-1) >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + pY-=8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = (count - 1) % 0x8U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp16q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ +} + +#define MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_Q7(acc0, acc1, pX, pY, count)\ +{ \ + q7_t const *pSrcX, *pSrcY; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + pSrcY = (q7_t const *) pY; \ + k = count >> 4; \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + yVec = vldrbq_s8(&pSrcY[-1]); \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x10U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + mve_pred16_t p0 = vctp8q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + yVec = vldrbq_s8(&pSrcY[-1]); \ + acc1 = vmladavaq_p(acc1, xVec, yVec,p0); \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + p0 = vctp8q(k); \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + acc0 = vmladavaq_p(acc0, xVec, yVec,p0); \ + \ + acc0 = (acc0 >> 7); \ + acc1 = (acc1 >> 7); \ + acc0 = __SSAT(acc0, 8); \ + acc1 = __SSAT(acc1, 8); \ +} + +#define MVE_INTR_CORR_SINGLE_Q7(acc, pX, pY, count)\ +{ \ + q7_t const *pSrcX, *pSrcY; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + pSrcY = (q7_t const *) pY; \ + k = count >> 4; \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + acc = vmladavaq(acc, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* tail predication expected here */ \ + k = count % 0x10U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp8q(k); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + acc = vmladavaq_p(acc, xVec, yVec, p0); \ + } \ + acc =(acc >> 7); \ + acc = __SSAT(acc, 8); \ +} + +#define MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_Q7(acc0, acc1, acc2, acc3, pX, pY, count)\ +{ \ + q7_t const *pSrcX, *pSrcY; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + pSrcY = (q7_t const *) pY; \ + k = count >> 4; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + xVec = vldrbq_s8(&pSrcX[2]); \ + acc2 = vmladavaq(acc2, xVec, yVec); \ + xVec = vldrbq_s8(&pSrcX[3]); \ + acc3 = vmladavaq(acc3, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x10U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp8q(k); \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \ + xVec = vldrbq_s8(&pSrcX[2]); \ + acc2 = vmladavaq_p(acc2, xVec, yVec, p0); \ + xVec = vldrbq_s8(&pSrcX[3]); \ + acc3 = vmladavaq_p(acc3, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \ + } \ + \ + acc0 = (acc0 >> 7); \ + acc1 = (acc1 >> 7); \ + acc2 = (acc2 >> 7); \ + acc3 = (acc3 >> 7); \ + acc0 = __SSAT(acc0, 8); \ + acc1 = __SSAT(acc1, 8); \ + acc2 = __SSAT(acc2, 8); \ + acc3 = __SSAT(acc3, 8); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_Q7(acc0, acc1, pX, pY, count)\ +{ \ + q7_t const *pSrcX, *pSrcY; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + pSrcY = (q7_t const *) pY; \ + k = count >> 4; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x10U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp8q(k); \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \ + } \ + \ + acc0 = (acc0 >> 7); \ + acc1 = (acc1 >> 7); \ + acc0 = __SSAT(acc0, 8); \ + acc1 = __SSAT(acc1, 8); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_Q7(acc0, acc1, pX, pY, count)\ +{ \ + q7_t const *pSrcX, *pSrcY; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + pSrcY = (q7_t const *) pY; \ + k = (count-1) >> 4; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + k = (count-1) % 0x10U; \ + mve_pred16_t p0 = vctp8q(k); \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp8q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \ + \ + acc0 = (acc0 >> 7); \ + acc1 = (acc1 >> 7); \ + acc0 = __SSAT(acc0, 8); \ + acc1 = __SSAT(acc1, 8); \ +} + +#define MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_Q7(acc0, acc1, pX, pY, count)\ +{ \ + q7_t const *pSrcX; \ + const q7_t *pY1 = pY + 1; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + k = count >> 4; \ + \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + pY-=16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + yVec = vldrbq_gather_offset_s8(pY1, decrIdxVec); \ + pY1-=16; \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x10U; \ + /* use predication to finalize MAC sum */ \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + mve_pred16_t p0 = vctp8q(k); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \ + yVec = vldrbq_gather_offset_s8(pY1, decrIdxVec); \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp8q(k+1); \ + acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \ + \ + acc0 = (acc0 >> 7); \ + acc1 = (acc1 >> 7); \ + acc0 = __SSAT(acc0, 8); \ + acc1 = __SSAT(acc1, 8); \ +} + +#define MVE_INTR_CONV_SINGLE_Q7(acc, pX, pY, count) \ +{ \ + q7_t const *pSrcX; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + k = count >> 4; \ + \ + while (k > 0U) \ + { \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + pY-=16; \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc = vmladavaq(acc, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x10U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp8q(k); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + acc = vmladavaq_p(acc, xVec, yVec, p0); \ + } \ + acc = __SSAT(acc >> 7, 8); \ +} + +#define MVE_INTR_CONV_QUAD_INC_X_FIXED_SIZE_Q7(acc0, acc1, acc2, acc3, pX, pY, count) \ +{ \ + q7_t const *pSrcX; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + k = count >> 4; \ + \ + while (k > 0U) \ + { \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + pY-=16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + xVec = vldrbq_s8(&pSrcX[2]); \ + acc2 = vmladavaq(acc2, xVec, yVec); \ + xVec = vldrbq_s8(&pSrcX[3]); \ + acc3 = vmladavaq(acc3, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x10U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp8q(k); \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \ + xVec = vldrbq_s8(&pSrcX[2]); \ + acc2 = vmladavaq_p(acc2, xVec, yVec, p0); \ + xVec = vldrbq_s8(&pSrcX[3]); \ + acc3 = vmladavaq_p(acc3, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \ + } \ + acc0 = __SSAT(acc0 >> 7, 8); \ + acc1 = __SSAT(acc1 >> 7, 8); \ + acc2 = __SSAT(acc2 >> 7, 8); \ + acc3 = __SSAT(acc3 >> 7, 8); \ +} + +#define MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_Q7(acc0, acc1, pX, pY, count) \ +{ \ + q7_t const *pSrcX; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + k = count >> 4; \ + \ + while (k > 0U) \ + { \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + pY-=16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x10U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp8q(k); \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \ + } \ + acc0 = __SSAT(acc0 >> 7, 8); \ + acc1 = __SSAT(acc1 >> 7, 8); \ +} + + +#define MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_Q7(acc0, acc1, pX, pY, count) \ +{ \ + q7_t const *pSrcX; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + k = (count-1) >> 4; \ + \ + while (k > 0U) \ + { \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + pY-=16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = (count - 1) % 0x10U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + mve_pred16_t p0 = vctp8q(k); \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp8q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \ + \ + acc0 = (acc0 >> 7); \ + acc1 = (acc1 >> 7); \ + acc0 = __SSAT(acc0, 8); \ + acc1 = __SSAT(acc1, 8); \ +} + +#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_VEC_FILTERING_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c new file mode 100644 index 00000000..7ade7478 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c @@ -0,0 +1,87 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: BasicMathFunctions.c + * Description: Combination of all basic math function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_abs_f32.c" +#include "arm_abs_f64.c" +#include "arm_abs_q15.c" +#include "arm_abs_q31.c" +#include "arm_abs_q7.c" +#include "arm_add_f32.c" +#include "arm_add_f64.c" +#include "arm_add_q15.c" +#include "arm_add_q31.c" +#include "arm_add_q7.c" +#include "arm_and_u16.c" +#include "arm_and_u32.c" +#include "arm_and_u8.c" +#include "arm_dot_prod_f32.c" +#include "arm_dot_prod_f64.c" +#include "arm_dot_prod_q15.c" +#include "arm_dot_prod_q31.c" +#include "arm_dot_prod_q7.c" +#include "arm_mult_f32.c" +#include "arm_mult_f64.c" +#include "arm_mult_q15.c" +#include "arm_mult_q31.c" +#include "arm_mult_q7.c" +#include "arm_negate_f32.c" +#include "arm_negate_f64.c" +#include "arm_negate_q15.c" +#include "arm_negate_q31.c" +#include "arm_negate_q7.c" +#include "arm_not_u16.c" +#include "arm_not_u32.c" +#include "arm_not_u8.c" +#include "arm_offset_f32.c" +#include "arm_offset_f64.c" +#include "arm_offset_q15.c" +#include "arm_offset_q31.c" +#include "arm_offset_q7.c" +#include "arm_or_u16.c" +#include "arm_or_u32.c" +#include "arm_or_u8.c" +#include "arm_scale_f32.c" +#include "arm_scale_f64.c" +#include "arm_scale_q15.c" +#include "arm_scale_q31.c" +#include "arm_scale_q7.c" +#include "arm_shift_q15.c" +#include "arm_shift_q31.c" +#include "arm_shift_q7.c" +#include "arm_sub_f32.c" +#include "arm_sub_f64.c" +#include "arm_sub_q15.c" +#include "arm_sub_q31.c" +#include "arm_sub_q7.c" +#include "arm_xor_u16.c" +#include "arm_xor_u32.c" +#include "arm_xor_u8.c" +#include "arm_clip_f32.c" +#include "arm_clip_q31.c" +#include "arm_clip_q15.c" +#include "arm_clip_q7.c" diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctionsF16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctionsF16.c new file mode 100644 index 00000000..f185db48 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctionsF16.c @@ -0,0 +1,37 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: BasicMathFunctionsF16.c + * Description: Combination of all basic math function f16 source files. + * + * $Date: 20. April 2020 + * $Revision: V1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_abs_f16.c" +#include "arm_add_f16.c" +#include "arm_dot_prod_f16.c" +#include "arm_mult_f16.c" +#include "arm_negate_f16.c" +#include "arm_offset_f16.c" +#include "arm_scale_f16.c" +#include "arm_sub_f16.c" +#include "arm_clip_f16.c" diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt new file mode 100644 index 00000000..37802a85 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt @@ -0,0 +1,41 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPBasicMath) + +include(configLib) +include(configDsp) + +file(GLOB SRCF64 "./*_f64.c") +file(GLOB SRCF32 "./*_f32.c") +file(GLOB SRCF16 "./*_f16.c") +file(GLOB SRCQ31 "./*_q31.c") +file(GLOB SRCQ15 "./*_q15.c") +file(GLOB SRCQ7 "./*_q7.c") + +file(GLOB SRCU32 "./*_u32.c") +file(GLOB SRCU16 "./*_u16.c") +file(GLOB SRCU8 "./*_u8.c") + +add_library(CMSISDSPBasicMath STATIC ${SRCF64}) +target_sources(CMSISDSPBasicMath PRIVATE ${SRCF32}) + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPBasicMath PRIVATE ${SRCF16}) +endif() + +target_sources(CMSISDSPBasicMath PRIVATE ${SRCQ31}) +target_sources(CMSISDSPBasicMath PRIVATE ${SRCQ15}) +target_sources(CMSISDSPBasicMath PRIVATE ${SRCQ7}) + +target_sources(CMSISDSPBasicMath PRIVATE ${SRCU32}) +target_sources(CMSISDSPBasicMath PRIVATE ${SRCU16}) +target_sources(CMSISDSPBasicMath PRIVATE ${SRCU8}) + +configLib(CMSISDSPBasicMath ${ROOT}) +configDsp(CMSISDSPBasicMath ${ROOT}) + +### Includes +target_include_directories(CMSISDSPBasicMath PUBLIC "${DSP}/Include") + + + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f16.c new file mode 100644 index 00000000..0d6568b8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f16.c @@ -0,0 +1,198 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_f16.c + * Description: Floating-point vector absolute value + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" +#include + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicAbs Vector Absolute Value + + Computes the absolute value of a vector on an element-by-element basis. + +
+      pDst[n] = abs(pSrc[n]),   0 <= n < blockSize.
+  
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Floating-point vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_abs_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + f16x8_t vec1; + f16x8_t res; + + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute values and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vabsq(vec1); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + + + if (blkCnt > 0U) + { + /* C = |A| */ + mve_pred16_t p0 = vctp16q(blkCnt); + vec1 = vld1q(pSrc); + vstrhq_p(pDst, vabsq(vec1), p0); + } + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_abs_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + f16x8_t vec1; + f16x8_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute values and then store the results in the destination buffer. */ + vec1 = vld1q_f16(pSrc); + res = vabsq_f16(vec1); + vst1q_f16(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute and store result in destination buffer. */ + *pDst++ = (_Float16)fabsf((float32_t)*pSrc++); + + *pDst++ = (_Float16)fabsf((float32_t)*pSrc++); + + *pDst++ = (_Float16)fabsf((float32_t)*pSrc++); + + *pDst++ = (_Float16)fabsf((float32_t)*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute and store result in destination buffer. */ + *pDst++ = (_Float16)fabsf((float32_t)*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_FLOAT16_SUPPORTED */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of BasicAbs group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c new file mode 100644 index 00000000..1e67f4e3 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c @@ -0,0 +1,196 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_f32.c + * Description: Floating-point vector absolute value + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" +#include + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicAbs Vector Absolute Value + + Computes the absolute value of a vector on an element-by-element basis. + +
+      pDst[n] = abs(pSrc[n]),   0 <= n < blockSize.
+  
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Floating-point vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_abs_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + f32x4_t vec1; + f32x4_t res; + + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute values and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vabsq(vec1); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + + + if (blkCnt > 0U) + { + /* C = |A| */ + mve_pred16_t p0 = vctp32q(blkCnt); + vec1 = vld1q(pSrc); + vstrwq_p(pDst, vabsq(vec1), p0); + } + +} + +#else +void arm_abs_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t vec1; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute values and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrc); + res = vabsq_f32(vec1); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute and store result in destination buffer. */ + *pDst++ = fabsf(*pSrc++); + + *pDst++ = fabsf(*pSrc++); + + *pDst++ = fabsf(*pSrc++); + + *pDst++ = fabsf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute and store result in destination buffer. */ + *pDst++ = fabsf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of BasicAbs group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f64.c new file mode 100644 index 00000000..04a79f7a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f64.c @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_f64.c + * Description: Floating-point vector absolute value + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" +#include + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Floating-point vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_abs_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute and store result in destination buffer. */ + *pDst++ = fabs(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicAbs group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c new file mode 100644 index 00000000..7c38ef51 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c @@ -0,0 +1,178 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_q15.c + * Description: Q15 vector absolute value + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Q15 vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_abs_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = |A| + * Calculate absolute and then store the results in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqabsq(vecSrc)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrc = vld1q(pSrc); + vstrhq_p(pDst, vqabsq(vecSrc), p0); + } +} + +#else +void arm_abs_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q15_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7fff) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7fff) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicAbs group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c new file mode 100644 index 00000000..7043aa0c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c @@ -0,0 +1,208 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_q31.c + * Description: Q31 vector absolute value + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Q31 vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_abs_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counters */ + q31x4_t vecSrc; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + /* + * C = |A| + * Calculate absolute and then store the results in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqabsq(vecSrc)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * Advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + } + /* + * Tail + */ + blkCnt = blockSize & 3; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrc = vld1q(pSrc); + vstrwq_p(pDst, vqabsq(vecSrc), p0); + } +} + +#else +void arm_abs_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in; /* Temporary variable */ + +#if defined(ARM_MATH_NEON) + int32x4_t vec1; + int32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + /* Calculate absolute and then store the results in the destination buffer. */ + + vec1 = vld1q_s32(pSrc); + res = vqabsq_s32(vec1); + vst1q_s32(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined (ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined (ARM_MATH_MVEI) */ +/** + @} end of BasicAbs group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c new file mode 100644 index 00000000..bd79582e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c @@ -0,0 +1,180 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_q7.c + * Description: Q7 vector absolute value + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Q7 vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Conditions for optimum performance + Input and output buffers should be aligned by 32-bit + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_abs_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = |A| + * Calculate absolute and then store the results in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqabsq(vecSrc)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrc = vld1q(pSrc); + vstrbq_p(pDst, vqabsq(vecSrc), p0); + } +} + +#else +void arm_abs_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q7_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7f) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q7_t)__QSUB8(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q7_t)__QSUB8(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q7_t)__QSUB8(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q7_t)__QSUB8(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7f) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q7_t) __QSUB8(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicAbs group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f16.c new file mode 100644 index 00000000..2b2ae8f1 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f16.c @@ -0,0 +1,169 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_f16.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicAdd Vector Addition + + Element-by-element addition of two vectors. + +
+      pDst[n] = pSrcA[n] + pSrcB[n],   0 <= n < blockSize.
+  
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Floating-point vector addition. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_add_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f16x8_t vec1; + f16x8_t vec2; + f16x8_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + res = vaddq(vec1, vec2); + vst1q(pDst, res); + + /* Increment pointers */ + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + + if (blkCnt > 0U) + { + /* C = A + B */ + mve_pred16_t p0 = vctp16q(blkCnt); + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + vstrhq_p(pDst, vaddq(vec1,vec2), p0); + } + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_add_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrcA++) + (_Float16)(*pSrcB++); + *pDst++ = (_Float16)(*pSrcA++) + (_Float16)(*pSrcB++); + *pDst++ = (_Float16)(*pSrcA++) + (_Float16)(*pSrcB++); + *pDst++ = (_Float16)(*pSrcA++) + (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrcA++) + (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_FLOAT16_SUPPORTED) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicAdd group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c new file mode 100644 index 00000000..9741e4a6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c @@ -0,0 +1,199 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_f32.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicAdd Vector Addition + + Element-by-element addition of two vectors. + +
+      pDst[n] = pSrcA[n] + pSrcB[n],   0 <= n < blockSize.
+  
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Floating-point vector addition. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_add_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f32x4_t vec1; + f32x4_t vec2; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + res = vaddq(vec1, vec2); + vst1q(pDst, res); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + + if (blkCnt > 0U) + { + /* C = A + B */ + mve_pred16_t p0 = vctp32q(blkCnt); + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + vstrwq_p(pDst, vaddq(vec1,vec2), p0); + } + +} + +#else +void arm_add_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t vec1; + f32x4_t vec2; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrcA); + vec2 = vld1q_f32(pSrcB); + res = vaddq_f32(vec1, vec2); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (*pSrcA++) + (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicAdd group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f64.c new file mode 100644 index 00000000..2d772339 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f64.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_f64.c + * Description: Floating-point vector addition + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Floating-point vector addition. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_add_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (*pSrcA++) + (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicAdd group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c new file mode 100644 index 00000000..0bf9d06a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c @@ -0,0 +1,176 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_q15.c + * Description: Q15 vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Q15 vector addition. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_add_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecA; + q15x8_t vecB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = A + B + * Add and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqaddq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrhq_p(pDst, vqaddq(vecA, vecB), p0); + } +} + +#else +void arm_add_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t inA1, inA2; + q31_t inB1, inB2; +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + +#if defined (ARM_MATH_DSP) + /* read 2 times 2 samples at a time from sourceA */ + inA1 = read_q15x2_ia (&pSrcA); + inA2 = read_q15x2_ia (&pSrcA); + /* read 2 times 2 samples at a time from sourceB */ + inB1 = read_q15x2_ia (&pSrcB); + inB2 = read_q15x2_ia (&pSrcB); + + /* Add and store 2 times 2 samples at a time */ + write_q15x2_ia (&pDst, __QADD16(inA1, inB1)); + write_q15x2_ia (&pDst, __QADD16(inA2, inB2)); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pDst++ = (q15_t) __QADD16(*pSrcA++, *pSrcB++); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ +/** + @} end of BasicAdd group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c new file mode 100644 index 00000000..a6783e7f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c @@ -0,0 +1,159 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_q31.c + * Description: Q31 vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Q31 vector addition. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_add_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + q31x4_t vecA; + q31x4_t vecB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = A + B + * Add and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqaddq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrwq_p(pDst, vqaddq(vecA, vecB), p0); + } +} + +#else +void arm_add_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#endif /* defined(ARM_MATH_MVEI) */ +/** + @} end of BasicAdd group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c new file mode 100644 index 00000000..f58ff866 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_q7.c + * Description: Q7 vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Q7 vector addition. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_add_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecA; + q7x16_t vecB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = A + B + * Add and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqaddq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 16; + pSrcB += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrbq_p(pDst, vqaddq(vecA, vecB), p0); + } +} +#else +void arm_add_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + +#if defined (ARM_MATH_DSP) + /* Add and store result in destination buffer (4 samples at a time). */ + write_q7x4_ia (&pDst, __QADD8 (read_q7x4_ia (&pSrcA), read_q7x4_ia (&pSrcB))); +#else + *pDst++ = (q7_t) __SSAT ((q15_t) *pSrcA++ + *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT ((q15_t) *pSrcA++ + *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT ((q15_t) *pSrcA++ + *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT ((q15_t) *pSrcA++ + *pSrcB++, 8); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ + *pSrcB++, 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ +/** + @} end of BasicAdd group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u16.c new file mode 100644 index 00000000..7a7427dc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u16.c @@ -0,0 +1,137 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_and_u16.c + * Description: uint16_t bitwise AND + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup And Vector bitwise AND + + Compute the logical bitwise AND. + + There are separate functions for uint32_t, uint16_t, and uint7_t data types. + */ + +/** + @addtogroup And + @{ + */ + +/** + @brief Compute the logical bitwise AND of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_and_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t vecSrcA, vecSrcB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, vandq_u16(vecSrcA, vecSrcB) ); + + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrhq_p(pDst, vandq_u16(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t vecA, vecB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + vecA = vld1q_u16(pSrcA); + vecB = vld1q_u16(pSrcB); + + vst1q_u16(pDst, vandq_u16(vecA, vecB) ); + + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)&(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of And group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u32.c new file mode 100644 index 00000000..ddf838c2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u32.c @@ -0,0 +1,129 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_and_u32.c + * Description: uint32_t bitwise AND + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup And + @{ + */ + +/** + @brief Compute the logical bitwise AND of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_and_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t vecSrcA, vecSrcB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, vandq_u32(vecSrcA, vecSrcB) ); + + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrwq_p(pDst, vandq_u32(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t vecA, vecB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + vecA = vld1q_u32(pSrcA); + vecB = vld1q_u32(pSrcB); + + vst1q_u32(pDst, vandq_u32(vecA, vecB) ); + + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)&(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of And group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u8.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u8.c new file mode 100644 index 00000000..bd1a1abe --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u8.c @@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_and_u8.c + * Description: uint8_t bitwise AND + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup And + @{ + */ + +/** + @brief Compute the logical bitwise AND of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_and_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t vecSrcA, vecSrcB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, vandq_u8(vecSrcA, vecSrcB) ); + + pSrcA += 16; + pSrcB += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrbq_p(pDst, vandq_u8(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t vecA, vecB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4U; + + while (blkCnt > 0U) + { + vecA = vld1q_u8(pSrcA); + vecB = vld1q_u8(pSrcB); + + vst1q_u8(pDst, vandq_u8(vecA, vecB) ); + + pSrcA += 16; + pSrcB += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)&(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of And group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_f16.c new file mode 100644 index 00000000..f784a238 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_f16.c @@ -0,0 +1,141 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_clip_f16.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup BasicClip + @{ + */ + +/** + @brief Elementwise floating-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_clip_f16(const float16_t * pSrc, + float16_t * pDst, + float16_t low, + float16_t high, + uint32_t numSamples) +{ + uint32_t blkCnt; + f16x8_t curVec0, curVec1; + f16x8_t vecLow, vecHigh; + + vecLow = vdupq_n_f16(low); + vecHigh = vdupq_n_f16(high); + + curVec0 = vld1q(pSrc); + pSrc += 8; + /* + * unrolled x 2 to allow + * vldr/vstr/vmin/vmax + * stall free interleaving + */ + blkCnt = numSamples >> 4; + while (blkCnt--) + { + curVec0 = vmaxnmq(curVec0, vecLow); + curVec1 = vld1q(pSrc); + pSrc += 8; + curVec0 = vminnmq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 8; + curVec1 = vmaxnmq(curVec1, vecLow); + curVec0 = vld1q(pSrc); + pSrc += 8; + curVec1 = vminnmq(curVec1, vecHigh); + vst1q(pDst, curVec1); + pDst += 8; + } + /* + * Tail handling + */ + blkCnt = numSamples - ((numSamples >> 4) << 4); + if (blkCnt >= 8) + { + curVec0 = vmaxnmq(curVec0, vecLow); + curVec0 = vminnmq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 8; + curVec0 = vld1q(pSrc); + pSrc += 8; + } + + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp16q(blkCnt & 7); + curVec0 = vmaxnmq(curVec0, vecLow); + curVec0 = vminnmq(curVec0, vecHigh); + vstrhq_p(pDst, curVec0, p0); + } +} + +#else + +#if defined(ARM_FLOAT16_SUPPORTED) + +void arm_clip_f16(const float16_t * pSrc, + float16_t * pDst, + float16_t low, + float16_t high, + uint32_t numSamples) +{ + for (uint32_t i = 0; i < numSamples; i++) + { + if ((_Float16)pSrc[i] > (_Float16)high) + pDst[i] = high; + else if ((_Float16)pSrc[i] < (_Float16)low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} +#endif /* defined(ARM_FLOAT16_SUPPORTED */ + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + @} end of BasicClip group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_f32.c new file mode 100644 index 00000000..4cc27994 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_f32.c @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_clip_f32.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicClip Elementwise clipping + + Element-by-element clipping of a value. + + The value is constrained between 2 bounds. + + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicClip + @{ + */ + +/** + @brief Elementwise floating-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_clip_f32(const float32_t * pSrc, + float32_t * pDst, + float32_t low, + float32_t high, + uint32_t numSamples) +{ + uint32_t blkCnt; + f32x4_t curVec0, curVec1; + f32x4_t vecLow, vecHigh; + + vecLow = vdupq_n_f32(low); + vecHigh = vdupq_n_f32(high); + + curVec0 = vld1q(pSrc); + pSrc += 4; + /* + * unrolled x 2 to allow + * vldr/vstr/vmin/vmax + * stall free interleaving + */ + blkCnt = numSamples >> 3; + while (blkCnt--) + { + curVec0 = vmaxnmq(curVec0, vecLow); + curVec1 = vld1q(pSrc); + pSrc += 4; + curVec0 = vminnmq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 4; + curVec1 = vmaxnmq(curVec1, vecLow); + curVec0 = vld1q(pSrc); + pSrc += 4; + curVec1 = vminnmq(curVec1, vecHigh); + vst1q(pDst, curVec1); + pDst += 4; + } + /* + * Tail handling + */ + blkCnt = numSamples - ((numSamples >> 3) << 3); + if (blkCnt >= 4) + { + curVec0 = vmaxnmq(curVec0, vecLow); + curVec0 = vminnmq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 4; + curVec0 = vld1q(pSrc); + pSrc += 4; + } + + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp32q(blkCnt & 3); + curVec0 = vmaxnmq(curVec0, vecLow); + curVec0 = vminnmq(curVec0, vecHigh); + vstrwq_p(pDst, curVec0, p0); + } +} + +#else +void arm_clip_f32(const float32_t * pSrc, + float32_t * pDst, + float32_t low, + float32_t high, + uint32_t numSamples) +{ + uint32_t i; + for (i = 0; i < numSamples; i++) + { + if (pSrc[i] > high) + pDst[i] = high; + else if (pSrc[i] < low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicClip group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q15.c new file mode 100644 index 00000000..0d67c376 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q15.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_clip_q15.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup BasicClip + @{ + */ + +/** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_clip_q15(const q15_t * pSrc, + q15_t * pDst, + q15_t low, + q15_t high, + uint32_t numSamples) +{ + uint32_t blkCnt; + q15x8_t curVec0, curVec1; + q15x8_t vecLow, vecHigh; + + vecLow = vdupq_n_s16(low); + vecHigh = vdupq_n_s16(high); + + curVec0 = vld1q(pSrc); + pSrc += 8; + /* + * unrolled x 2 to allow + * vldr/vstr/vmin/vmax + * stall free interleaving + */ + blkCnt = numSamples >> 4; + while (blkCnt--) + { + curVec0 = vmaxq(curVec0, vecLow); + curVec1 = vld1q(pSrc); + pSrc += 8; + curVec0 = vminq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 8; + curVec1 = vmaxq(curVec1, vecLow); + curVec0 = vld1q(pSrc); + pSrc += 8; + curVec1 = vminq(curVec1, vecHigh); + vst1q(pDst, curVec1); + pDst += 8; + } + /* + * Tail handling + */ + blkCnt = numSamples - ((numSamples >> 4) << 4); + if (blkCnt >= 8) + { + curVec0 = vmaxq(curVec0, vecLow); + curVec0 = vminq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 8; + curVec0 = vld1q(pSrc); + pSrc += 8; + } + + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp16q(blkCnt & 7); + curVec0 = vmaxq(curVec0, vecLow); + curVec0 = vminq(curVec0, vecHigh); + vstrhq_p(pDst, curVec0, p0); + } +} + +#else +void arm_clip_q15(const q15_t * pSrc, + q15_t * pDst, + q15_t low, + q15_t high, + uint32_t numSamples) +{ + uint32_t i; + for (i = 0; i < numSamples; i++) + { + if (pSrc[i] > high) + pDst[i] = high; + else if (pSrc[i] < low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicClip group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q31.c new file mode 100644 index 00000000..72b80d38 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q31.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_clip_q31.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup BasicClip + @{ + */ + +/** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_clip_q31(const q31_t * pSrc, + q31_t * pDst, + q31_t low, + q31_t high, + uint32_t numSamples) +{ + uint32_t blkCnt; + q31x4_t curVec0, curVec1; + q31x4_t vecLow, vecHigh; + + vecLow = vdupq_n_s32(low); + vecHigh = vdupq_n_s32(high); + + curVec0 = vld1q(pSrc); + pSrc += 4; + /* + * unrolled x 2 to allow + * vldr/vstr/vmin/vmax + * stall free interleaving + */ + blkCnt = numSamples >> 3; + while (blkCnt--) + { + curVec0 = vmaxq(curVec0, vecLow); + curVec1 = vld1q(pSrc); + pSrc += 4; + curVec0 = vminq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 4; + curVec1 = vmaxq(curVec1, vecLow); + curVec0 = vld1q(pSrc); + pSrc += 4; + curVec1 = vminq(curVec1, vecHigh); + vst1q(pDst, curVec1); + pDst += 4; + } + /* + * Tail handling + */ + blkCnt = numSamples - ((numSamples >> 3) << 3); + if (blkCnt >= 4) + { + curVec0 = vmaxq(curVec0, vecLow); + curVec0 = vminq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 4; + curVec0 = vld1q(pSrc); + pSrc += 4; + } + + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp32q(blkCnt & 3); + curVec0 = vmaxq(curVec0, vecLow); + curVec0 = vminq(curVec0, vecHigh); + vstrwq_p(pDst, curVec0, p0); + } +} + +#else +void arm_clip_q31(const q31_t * pSrc, + q31_t * pDst, + q31_t low, + q31_t high, + uint32_t numSamples) +{ + uint32_t i; + for (i = 0; i < numSamples; i++) + { + if (pSrc[i] > high) + pDst[i] = high; + else if (pSrc[i] < low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicClip group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q7.c new file mode 100644 index 00000000..a41e0c91 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q7.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_clip_q7.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup BasicClip + @{ + */ + +/** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_clip_q7(const q7_t * pSrc, + q7_t * pDst, + q7_t low, + q7_t high, + uint32_t numSamples) +{ + uint32_t blkCnt; + q7x16_t curVec0, curVec1; + q7x16_t vecLow, vecHigh; + + vecLow = vdupq_n_s8(low); + vecHigh = vdupq_n_s8(high); + + curVec0 = vld1q(pSrc); + pSrc += 16; + /* + * unrolled x 2 to allow + * vldr/vstr/vmin/vmax + * stall free interleaving + */ + blkCnt = numSamples >> 5; + while (blkCnt--) + { + curVec0 = vmaxq(curVec0, vecLow); + curVec1 = vld1q(pSrc); + pSrc += 16; + curVec0 = vminq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 16; + curVec1 = vmaxq(curVec1, vecLow); + curVec0 = vld1q(pSrc); + pSrc += 16; + curVec1 = vminq(curVec1, vecHigh); + vst1q(pDst, curVec1); + pDst += 16; + } + /* + * Tail handling + */ + blkCnt = numSamples - ((numSamples >> 5) << 5); + if (blkCnt >= 16) + { + curVec0 = vmaxq(curVec0, vecLow); + curVec0 = vminq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 16; + curVec0 = vld1q(pSrc); + pSrc += 16; + } + + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp8q(blkCnt & 0xf); + curVec0 = vmaxq(curVec0, vecLow); + curVec0 = vminq(curVec0, vecHigh); + vstrbq_p(pDst, curVec0, p0); + } +} + +#else +void arm_clip_q7(const q7_t * pSrc, + q7_t * pDst, + q7_t low, + q7_t high, + uint32_t numSamples) +{ + uint32_t i; + for (i = 0; i < numSamples; i++) + { + if (pSrc[i] > high) + pDst[i] = high; + else if (pSrc[i] < low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicClip group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f16.c new file mode 100644 index 00000000..55c88dfc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f16.c @@ -0,0 +1,184 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_f16.c + * Description: Floating-point dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicDotProd Vector Dot Product + + Computes the dot product of two vectors. + The vectors are multiplied element-by-element and then summed. + +
+      sum = pSrcA[0]*pSrcB[0] + pSrcA[1]*pSrcB[1] + ... + pSrcA[blockSize-1]*pSrcB[blockSize-1]
+  
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of floating-point vectors. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[in] blockSize number of samples in each vector. + @param[out] result output result returned here. + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + +void arm_dot_prod_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t * result) +{ + f16x8_t vecA, vecB; + f16x8_t vecSum; + uint32_t blkCnt; + float16_t sum = 0.0f; + vecSum = vdupq_n_f16(0.0f); + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + while (blkCnt > 0U) + { + /* + * C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] + * Calculate dot product and then store the result in a temporary buffer. + * and advance vector source and destination pointers + */ + vecA = vld1q(pSrcA); + pSrcA += 8; + + vecB = vld1q(pSrcB); + pSrcB += 8; + + vecSum = vfmaq(vecSum, vecA, vecB); + /* + * Decrement the blockSize loop counter + */ + blkCnt --; + } + + + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vecSum = vfmaq_m(vecSum, vecA, vecB, p0); + } + + sum = vecAddAcrossF16Mve(vecSum); + + /* Store result in destination buffer */ + *result = sum; + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_dot_prod_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 sum = 0.0f; /* Temporary return variable */ + + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + sum += (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + sum += (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + sum += (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = sum; +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of BasicDotProd group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c new file mode 100644 index 00000000..62b86578 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c @@ -0,0 +1,228 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_f32.c + * Description: Floating-point dot product + * + * $Date: 05 October 2021 + * $Revision: V1.9.1 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicDotProd Vector Dot Product + + Computes the dot product of two vectors. + The vectors are multiplied element-by-element and then summed. + +
+      sum = pSrcA[0]*pSrcB[0] + pSrcA[1]*pSrcB[1] + ... + pSrcA[blockSize-1]*pSrcB[blockSize-1]
+  
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of floating-point vectors. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[in] blockSize number of samples in each vector. + @param[out] result output result returned here. + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + +void arm_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result) +{ + f32x4_t vecA, vecB; + f32x4_t vecSum; + uint32_t blkCnt; + float32_t sum = 0.0f; + vecSum = vdupq_n_f32(0.0f); + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + /* + * C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] + * Calculate dot product and then store the result in a temporary buffer. + * and advance vector source and destination pointers + */ + vecA = vld1q(pSrcA); + pSrcA += 4; + + vecB = vld1q(pSrcB); + pSrcB += 4; + + vecSum = vfmaq(vecSum, vecA, vecB); + /* + * Decrement the blockSize loop counter + */ + blkCnt --; + } + + + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vecSum = vfmaq_m(vecSum, vecA, vecB, p0); + } + + sum = vecAddAcrossF32Mve(vecSum); + + /* Store result in destination buffer */ + *result = sum; + +} + +#else + +void arm_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary return variable */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t vec1; + f32x4_t vec2; + f32x4_t accum = vdupq_n_f32(0); +#if !defined(__aarch64__) + f32x2_t tmp = vdup_n_f32(0); +#endif + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + vec1 = vld1q_f32(pSrcA); + vec2 = vld1q_f32(pSrcB); + + while (blkCnt > 0U) + { + /* C = A[0]*B[0] + A[1]*B[1] + A[2]*B[2] + ... + A[blockSize-1]*B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer. */ + + accum = vmlaq_f32(accum, vec1, vec2); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + + vec1 = vld1q_f32(pSrcA); + vec2 = vld1q_f32(pSrcB); + + /* Decrement the loop counter */ + blkCnt--; + } + +#if defined(__aarch64__) + sum = vpadds_f32(vpadd_f32(vget_low_f32(accum), vget_high_f32(accum))); +#else + tmp = vpadd_f32(vget_low_f32(accum), vget_high_f32(accum)); + sum = vget_lane_f32(tmp, 0) + vget_lane_f32(tmp, 1); + +#endif + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += (*pSrcA++) * (*pSrcB++); + + sum += (*pSrcA++) * (*pSrcB++); + + sum += (*pSrcA++) * (*pSrcB++); + + sum += (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = sum; +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of BasicDotProd group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f64.c new file mode 100644 index 00000000..a4cd07cc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f64.c @@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_f64.c + * Description: Floating-point dot product + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of floating-point vectors. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[in] blockSize number of samples in each vector. + @param[out] result output result returned here. + @return none + */ + +void arm_dot_prod_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + uint32_t blockSize, + float64_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + float64_t sum = 0.; /* Temporary return variable */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = sum; +} + +/** + @} end of BasicDotProd group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c new file mode 100644 index 00000000..cb42609b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c @@ -0,0 +1,172 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_q15.c + * Description: Q15 dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of Q15 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in each vector + @param[out] result output result returned here + @return none + + @par Scaling and Overflow Behavior + The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these + results are added to a 64-bit accumulator in 34.30 format. + Nonsaturating additions are used and given that there are 33 guard bits in the accumulator + there is no risk of overflow. + The return result is in 34.30 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecA; + q15x8_t vecB; + q63_t sum = 0LL; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] + * Calculate dot product and then store the result in a temporary buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + sum = vmlaldavaq(sum, vecA, vecB); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + sum = vmlaldavaq_p(sum, vecA, vecB, p0); + } + + *result = sum; +} + +#else +void arm_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary return variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + +#if defined (ARM_MATH_DSP) + /* Calculate dot product and store result in a temporary buffer. */ + sum = __SMLALD(read_q15x2_ia (&pSrcA), read_q15x2_ia (&pSrcB), sum); + sum = __SMLALD(read_q15x2_ia (&pSrcA), read_q15x2_ia (&pSrcB), sum); +#else + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ +//#if defined (ARM_MATH_DSP) +// sum = __SMLALD(*pSrcA++, *pSrcB++, sum); +//#else + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); +//#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer in 34.30 format */ + *result = sum; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicDotProd group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c new file mode 100644 index 00000000..b85da379 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c @@ -0,0 +1,174 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_q31.c + * Description: Q31 dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of Q31 vectors. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[in] blockSize number of samples in each vector. + @param[out] result output result returned here. + @return none + + @par Scaling and Overflow Behavior + The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these + are truncated to 2.48 format by discarding the lower 14 bits. + The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. + There are 15 guard bits in the accumulator and there is no risk of overflow as long as + the length of the vectors is less than 2^16 elements. + The return result is in 16.48 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecA; + q31x4_t vecB; + q63_t sum = 0LL; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] + * Calculate dot product and then store the result in a temporary buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + sum = vrmlaldavhaq(sum, vecA, vecB); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + sum = vrmlaldavhaq_p(sum, vecA, vecB, p0); + } + + /* + * vrmlaldavhaq provides extra intermediate accumulator headroom. + * limiting the need of intermediate scaling + * Scalar variant uses 2.48 accu format by right shifting accumulators by 14. + * 16.48 output conversion is performed outside the loop by scaling accu. by 6 + */ + *result = asrl(sum, (14 - 8)); +} + +#else +void arm_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary return variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer in 16.48 format */ + *result = sum; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicDotProd group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c new file mode 100644 index 00000000..2de4e278 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c @@ -0,0 +1,191 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_q7.c + * Description: Q7 dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of Q7 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in each vector + @param[out] result output result returned here + @return none + + @par Scaling and Overflow Behavior + The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these + results are added to an accumulator in 18.14 format. + Nonsaturating additions are used and there is no danger of wrap around as long as + the vectors are less than 2^18 elements long. + The return result is in 18.14 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_dot_prod_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q31_t * result) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecA; + q7x16_t vecB; + q31_t sum = 0; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] + * Calculate dot product and then store the result in a temporary buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + sum = vmladavaq(sum, vecA, vecB); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 16; + pSrcB += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + sum = vmladavaq_p(sum, vecA, vecB, p0); + } + + *result = sum; +} +#else +void arm_dot_prod_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q31_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Temporary return variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t input1, input2; /* Temporary variables */ + q31_t inA1, inA2, inB1, inB2; /* Temporary variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + +#if defined (ARM_MATH_DSP) + /* read 4 samples at a time from sourceA */ + input1 = read_q7x4_ia (&pSrcA); + /* read 4 samples at a time from sourceB */ + input2 = read_q7x4_ia (&pSrcB); + + /* extract two q7_t samples to q15_t samples */ + inA1 = __SXTB16(__ROR(input1, 8)); + /* extract reminaing two samples */ + inA2 = __SXTB16(input1); + /* extract two q7_t samples to q15_t samples */ + inB1 = __SXTB16(__ROR(input2, 8)); + /* extract reminaing two samples */ + inB2 = __SXTB16(input2); + + /* multiply and accumulate two samples at a time */ + sum = __SMLAD(inA1, inB1, sum); + sum = __SMLAD(inA2, inB2, sum); +#else + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ +//#if defined (ARM_MATH_DSP) +// sum = __SMLAD(*pSrcA++, *pSrcB++, sum); +//#else + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); +//#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer in 18.14 format */ + *result = sum; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicDotProd group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f16.c new file mode 100644 index 00000000..c1115ac7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f16.c @@ -0,0 +1,171 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_f16.c + * Description: Floating-point vector multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicMult Vector Multiplication + + Element-by-element multiplication of two vectors. + +
+      pDst[n] = pSrcA[n] * pSrcB[n],   0 <= n < blockSize.
+  
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Floating-point vector multiplication. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_mult_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f16x8_t vec1; + f16x8_t vec2; + f16x8_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + res = vmulq(vec1, vec2); + vst1q(pDst, res); + + /* Increment pointers */ + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + if (blkCnt > 0U) + { + /* C = A + B */ + mve_pred16_t p0 = vctp16q(blkCnt); + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + vstrhq_p(pDst, vmulq(vec1,vec2), p0); + } + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_mult_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + *pDst++ = (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + *pDst++ = (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + *pDst++ = (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply input and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c new file mode 100644 index 00000000..4df04e96 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c @@ -0,0 +1,200 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_f32.c + * Description: Floating-point vector multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicMult Vector Multiplication + + Element-by-element multiplication of two vectors. + +
+      pDst[n] = pSrcA[n] * pSrcB[n],   0 <= n < blockSize.
+  
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Floating-point vector multiplication. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_mult_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f32x4_t vec1; + f32x4_t vec2; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + res = vmulq(vec1, vec2); + vst1q(pDst, res); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + if (blkCnt > 0U) + { + /* C = A + B */ + mve_pred16_t p0 = vctp32q(blkCnt); + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + vstrwq_p(pDst, vmulq(vec1,vec2), p0); + } + +} + +#else +void arm_mult_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t vec1; + f32x4_t vec2; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply the inputs and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrcA); + vec2 = vld1q_f32(pSrcB); + res = vmulq_f32(vec1, vec2); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + *pDst++ = (*pSrcA++) * (*pSrcB++); + + *pDst++ = (*pSrcA++) * (*pSrcB++); + + *pDst++ = (*pSrcA++) * (*pSrcB++); + + *pDst++ = (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply input and store result in destination buffer. */ + *pDst++ = (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f64.c new file mode 100644 index 00000000..1a5afd9a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f64.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_f64.c + * Description: Floating-point vector multiplication + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Floating-point vector multiplication. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + +void arm_mult_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply input and store result in destination buffer. */ + *pDst++ = (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c new file mode 100644 index 00000000..17951c7a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_q15.c + * Description: Q15 vector multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Q15 vector multiplication + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_mult_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecA, vecB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = A * B + * Multiply the inputs and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqdmulhq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrhq_p(pDst, vqdmulhq(vecA, vecB), p0); + } +} + +#else +void arm_mult_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t inA1, inA2, inB1, inB2; /* Temporary input variables */ + q15_t out1, out2, out3, out4; /* Temporary output variables */ + q31_t mul1, mul2, mul3, mul4; /* Temporary variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + +#if defined (ARM_MATH_DSP) + /* read 2 samples at a time from sourceA */ + inA1 = read_q15x2_ia (&pSrcA); + /* read 2 samples at a time from sourceB */ + inB1 = read_q15x2_ia (&pSrcB); + /* read 2 samples at a time from sourceA */ + inA2 = read_q15x2_ia (&pSrcA); + /* read 2 samples at a time from sourceB */ + inB2 = read_q15x2_ia (&pSrcB); + + /* multiply mul = sourceA * sourceB */ + mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16)); + mul2 = (q31_t) ((q15_t) (inA1 ) * (q15_t) (inB1 )); + mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16)); + mul4 = (q31_t) ((q15_t) (inA2 ) * (q15_t) (inB2 )); + + /* saturate result to 16 bit */ + out1 = (q15_t) __SSAT(mul1 >> 15, 16); + out2 = (q15_t) __SSAT(mul2 >> 15, 16); + out3 = (q15_t) __SSAT(mul3 >> 15, 16); + out4 = (q15_t) __SSAT(mul4 >> 15, 16); + + /* store result to destination */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(out2, out1, 16)); + write_q15x2_ia (&pDst, __PKHBT(out4, out3, 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(out1, out2, 16)); + write_q15x2_ia (&pDst, __PKHBT(out3, out4, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + +#else + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c new file mode 100644 index 00000000..63ad73c4 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c @@ -0,0 +1,168 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_q31.c + * Description: Q31 vector multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Q31 vector multiplication. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_mult_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecA, vecB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = A * B + * Multiply the inputs and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqdmulhq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrwq_p(pDst, vqdmulhq(vecA, vecB), p0); + } +} + +#else +void arm_mult_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t out; /* Temporary output variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + out = ((q63_t) *pSrcA++ * *pSrcB++) >> 32; + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + out = ((q63_t) *pSrcA++ * *pSrcB++) >> 32; + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + out = ((q63_t) *pSrcA++ * *pSrcB++) >> 32; + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + out = ((q63_t) *pSrcA++ * *pSrcB++) >> 32; + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + out = ((q63_t) *pSrcA++ * *pSrcB++) >> 32; + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c new file mode 100644 index 00000000..7be80db5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c @@ -0,0 +1,168 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_q7.c + * Description: Q7 vector multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Q7 vector multiplication + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_mult_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecA, vecB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = A * B + * Multiply the inputs and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqdmulhq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 16; + pSrcB += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrbq_p(pDst, vqdmulhq(vecA, vecB), p0); + } +} + +#else +void arm_mult_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q7_t out1, out2, out3, out4; /* Temporary output variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + +#if defined (ARM_MATH_DSP) + /* Multiply inputs and store results in temporary variables */ + out1 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + out2 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + out3 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + out4 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + + /* Pack and store result in destination buffer (in single write) */ + write_q7x4_ia (&pDst, __PACKq7(out1, out2, out3, out4)); +#else + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply input and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f16.c new file mode 100644 index 00000000..187e511b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f16.c @@ -0,0 +1,166 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_f16.c + * Description: Negates floating-point vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicNegate Vector Negate + + Negates the elements of a vector. + +
+      pDst[n] = -pSrc[n],   0 <= n < blockSize.
+  
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a floating-point vector. + @param[in] pSrc points to input vector. + @param[out] pDst points to output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_negate_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + f16x8_t vec1; + f16x8_t res; + + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute values and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vnegq(vec1); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + if (blkCnt > 0U) + { + /* C = |A| */ + mve_pred16_t p0 = vctp16q(blkCnt); + vec1 = vld1q((float16_t const *) pSrc); + vstrhq_p(pDst, vnegq(vec1), p0); + } + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_negate_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + *pDst++ = -(_Float16)*pSrc++; + + *pDst++ = -(_Float16)*pSrc++; + + *pDst++ = -(_Float16)*pSrc++; + + *pDst++ = -(_Float16)*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + *pDst++ = -(_Float16)*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicNegate group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c new file mode 100644 index 00000000..4f243cda --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_f32.c + * Description: Negates floating-point vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicNegate Vector Negate + + Negates the elements of a vector. + +
+      pDst[n] = -pSrc[n],   0 <= n < blockSize.
+  
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a floating-point vector. + @param[in] pSrc points to input vector. + @param[out] pDst points to output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_negate_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + f32x4_t vec1; + f32x4_t res; + + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute values and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vnegq(vec1); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + if (blkCnt > 0U) + { + /* C = |A| */ + mve_pred16_t p0 = vctp32q(blkCnt); + vec1 = vld1q((float32_t const *) pSrc); + vstrwq_p(pDst, vnegq(vec1), p0); + } + +} + +#else +void arm_negate_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON_EXPERIMENTAL) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t vec1; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrc); + res = vnegq_f32(vec1); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + *pDst++ = -*pSrc++; + + *pDst++ = -*pSrc++; + + *pDst++ = -*pSrc++; + + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON_EXPERIMENTAL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicNegate group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f64.c new file mode 100644 index 00000000..c8a73417 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f64.c @@ -0,0 +1,73 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_f64.c + * Description: Negates floating-point vectors + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a floating-point vector. + @param[in] pSrc points to input vector. + @param[out] pDst points to output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + +void arm_negate_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicNegate group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c new file mode 100644 index 00000000..43d5b0d0 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c @@ -0,0 +1,171 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_q15.c + * Description: Negates Q15 vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a Q15 vector. + @param[in] pSrc points to the input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + + @par Conditions for optimum performance + Input and output buffers should be aligned by 32-bit + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q15 value -1 (0x8000) is saturated to the maximum allowable positive value 0x7FFF. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_negate_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = -A + * Negate and then store the results in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqnegq(vecSrc)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrc = vld1q(pSrc); + vstrhq_p(pDst, vqnegq(vecSrc), p0); + } +} + +#else +void arm_negate_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q15_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t in1; /* Temporary input variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + +#if defined (ARM_MATH_DSP) + /* Negate and store result in destination buffer (2 samples at a time). */ + in1 = read_q15x2_ia (&pSrc); + write_q15x2_ia (&pDst, __QSUB16(0, in1)); + + in1 = read_q15x2_ia (&pSrc); + write_q15x2_ia (&pDst, __QSUB16(0, in1)); +#else + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; + + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; + + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; + + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicNegate group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c new file mode 100644 index 00000000..3ee77ed7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c @@ -0,0 +1,178 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_q31.c + * Description: Negates Q31 vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a Q31 vector. + @param[in] pSrc points to the input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q31 value -1 (0x80000000) is saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_negate_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = -A + * Negate and then store the results in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqnegq(vecSrc)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrc = vld1q(pSrc); + vstrwq_p(pDst, vqnegq(vecSrc), p0); + } +} + +#else +void arm_negate_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicNegate group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c new file mode 100644 index 00000000..9fd3122e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c @@ -0,0 +1,171 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_q7.c + * Description: Negates Q7 vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a Q7 vector. + @param[in] pSrc points to the input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q7 value -1 (0x80) is saturated to the maximum allowable positive value 0x7F. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_negate_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = -A + * Negate and then store the results in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqnegq(vecSrc)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrc = vld1q(pSrc); + vstrbq_p(pDst, vqnegq(vecSrc), p0); + } +} + +#else +void arm_negate_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q7_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t in1; /* Temporary input variable */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + +#if defined (ARM_MATH_DSP) + /* Negate and store result in destination buffer (4 samples at a time). */ + in1 = read_q7x4_ia (&pSrc); + write_q7x4_ia (&pDst, __QSUB8(0, in1)); +#else + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; + + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; + + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; + + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + in = *pSrc++; + +#if defined (ARM_MATH_DSP) + *pDst++ = (q7_t) __QSUB8(0, in); +#else + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicNegate group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u16.c new file mode 100644 index 00000000..e553d287 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u16.c @@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_not_u16.c + * Description: uint16_t bitwise NOT + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup Not Vector bitwise NOT + + Compute the logical bitwise NOT. + + There are separate functions for uint32_t, uint16_t, and uint8_t data types. + */ + +/** + @addtogroup Not + @{ + */ + +/** + @brief Compute the logical bitwise NOT of a fixed-point vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_not_u16( + const uint16_t * pSrc, + uint16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t vecSrc; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrc); + + vst1q(pDst, vmvnq_u16(vecSrc) ); + + pSrc += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrc = vld1q(pSrc); + vstrhq_p(pDst, vmvnq_u16(vecSrc), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t inV; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + inV = vld1q_u16(pSrc); + + vst1q_u16(pDst, vmvnq_u16(inV) ); + + pSrc += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = ~(*pSrc++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of Not group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u32.c new file mode 100644 index 00000000..f46284c8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u32.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_not_u32.c + * Description: uint32_t bitwise NOT + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Not + @{ + */ + +/** + @brief Compute the logical bitwise NOT of a fixed-point vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_not_u32( + const uint32_t * pSrc, + uint32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t vecSrc; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrc); + + vst1q(pDst, vmvnq_u32(vecSrc) ); + + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrc = vld1q(pSrc); + vstrwq_p(pDst, vmvnq_u32(vecSrc), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t inV; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + inV = vld1q_u32(pSrc); + + vst1q_u32(pDst, vmvnq_u32(inV) ); + + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = ~(*pSrc++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of Not group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u8.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u8.c new file mode 100644 index 00000000..e0682838 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u8.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_not_u8.c + * Description: uint8_t bitwise NOT + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Not + @{ + */ + +/** + @brief Compute the logical bitwise NOT of a fixed-point vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_not_u8( + const uint8_t * pSrc, + uint8_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t vecSrc; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrc); + + vst1q(pDst, vmvnq_u8(vecSrc) ); + + pSrc += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrc = vld1q(pSrc); + vstrbq_p(pDst, vmvnq_u8(vecSrc), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t inV; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4U; + + while (blkCnt > 0U) + { + inV = vld1q_u8(pSrc); + + vst1q_u8(pDst, vmvnq_u8(inV) ); + + pSrc += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = ~(*pSrc++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of Not group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f16.c new file mode 100644 index 00000000..9aeb1e75 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f16.c @@ -0,0 +1,170 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_f16.c + * Description: Floating-point vector offset + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicOffset Vector Offset + + Adds a constant offset to each element of a vector. + +
+      pDst[n] = pSrc[n] + offset,   0 <= n < blockSize.
+  
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_offset_f16( + const float16_t * pSrc, + float16_t offset, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f16x8_t vec1; + f16x8_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vaddq(vec1,offset); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vec1 = vld1q((float16_t const *) pSrc); + vstrhq_p(pDst, vaddq(vec1, offset), p0); + } + + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_offset_f16( + const float16_t * pSrc, + float16_t offset, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrc++) + (_Float16)offset; + + *pDst++ = (_Float16)(*pSrc++) + (_Float16)offset; + + *pDst++ = (_Float16)(*pSrc++) + (_Float16)offset; + + *pDst++ = (_Float16)(*pSrc++) + (_Float16)offset; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrc++) + (_Float16)offset; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicOffset group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c new file mode 100644 index 00000000..a68df050 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c @@ -0,0 +1,196 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_f32.c + * Description: Floating-point vector offset + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicOffset Vector Offset + + Adds a constant offset to each element of a vector. + +
+      pDst[n] = pSrc[n] + offset,   0 <= n < blockSize.
+  
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_offset_f32( + const float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f32x4_t vec1; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vaddq(vec1,offset); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vec1 = vld1q((float32_t const *) pSrc); + vstrwq_p(pDst, vaddq(vec1, offset), p0); + } + + +} + +#else +void arm_offset_f32( + const float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON_EXPERIMENTAL) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t vec1; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrc); + res = vaddq_f32(vec1,vdupq_n_f32(offset)); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (*pSrc++) + offset; + + *pDst++ = (*pSrc++) + offset; + + *pDst++ = (*pSrc++) + offset; + + *pDst++ = (*pSrc++) + offset; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON_EXPERIMENTAL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (*pSrc++) + offset; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicOffset group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f64.c new file mode 100644 index 00000000..0b39da43 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f64.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_f64.c + * Description: Floating-point vector offset + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_offset_f64( + const float64_t * pSrc, + float64_t offset, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (*pSrc++) + offset; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicOffset group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c new file mode 100644 index 00000000..211776d7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c @@ -0,0 +1,168 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_q15.c + * Description: Q15 vector offset + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_offset_q15( + const q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = A + offset + * Add offset and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqaddq(vecSrc, offset)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrc = vld1q(pSrc); + vstrhq_p(pDst, vqaddq(vecSrc, offset), p0); + } +} + + +#else +void arm_offset_q15( + const q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t offset_packed; /* Offset packed to 32 bit */ + + /* Offset is packed to 32 bit in order to use SIMD32 for addition */ + offset_packed = __PKHBT(offset, offset, 16); +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + +#if defined (ARM_MATH_DSP) + /* Add offset and store result in destination buffer (2 samples at a time). */ + write_q15x2_ia (&pDst, __QADD16(read_q15x2_ia (&pSrc), offset_packed)); + write_q15x2_ia (&pDst, __QADD16(read_q15x2_ia (&pSrc), offset_packed)); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pDst++ = (q15_t) __QADD16(*pSrc++, offset); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicOffset group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c new file mode 100644 index 00000000..2f702b0f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c @@ -0,0 +1,159 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_q31.c + * Description: Q31 vector offset + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_offset_q31( + const q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = A + offset + * Add offset and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqaddq(vecSrc, offset)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrc = vld1q(pSrc); + vstrwq_p(pDst, vqaddq(vecSrc, offset), p0); + } +} + +#else +void arm_offset_q31( + const q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = __QADD(*pSrc++, offset); + + *pDst++ = __QADD(*pSrc++, offset); + + *pDst++ = __QADD(*pSrc++, offset); + + *pDst++ = __QADD(*pSrc++, offset); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pDst++ = __QADD(*pSrc++, offset); +#else + *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicOffset group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c new file mode 100644 index 00000000..b53229d8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_q7.c + * Description: Q7 vector offset + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_offset_q7( + const q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = A + offset + * Add offset and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqaddq(vecSrc, offset)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrc = vld1q(pSrc); + vstrbq_p(pDst, vqaddq(vecSrc, offset), p0); + } +} + +#else +void arm_offset_q7( + const q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t offset_packed; /* Offset packed to 32 bit */ + + /* Offset is packed to 32 bit in order to use SIMD32 for addition */ + offset_packed = __PACKq7(offset, offset, offset, offset); +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + +#if defined (ARM_MATH_DSP) + /* Add offset and store result in destination buffer (4 samples at a time). */ + write_q7x4_ia (&pDst, __QADD8(read_q7x4_ia (&pSrc), offset_packed)); +#else + *pDst++ = (q7_t) __SSAT((q15_t) *pSrc++ + offset, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrc++ + offset, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrc++ + offset, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrc++ + offset, 8); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) *pSrc++ + offset, 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicOffset group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u16.c new file mode 100644 index 00000000..92d28036 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u16.c @@ -0,0 +1,137 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_or_u16.c + * Description: uint16_t bitwise inclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup Or Vector bitwise inclusive OR + + Compute the logical bitwise OR. + + There are separate functions for uint32_t, uint16_t, and uint8_t data types. + */ + +/** + @addtogroup Or + @{ + */ + +/** + @brief Compute the logical bitwise OR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_or_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t vecSrcA, vecSrcB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, vorrq_u16(vecSrcA, vecSrcB) ); + + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrhq_p(pDst, vorrq_u16(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t vecA, vecB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + vecA = vld1q_u16(pSrcA); + vecB = vld1q_u16(pSrcB); + + vst1q_u16(pDst, vorrq_u16(vecA, vecB) ); + + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)|(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of Or group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u32.c new file mode 100644 index 00000000..14cc83bb --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u32.c @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_or_u32.c + * Description: uint32_t bitwise inclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Or + @{ + */ + +/** + @brief Compute the logical bitwise OR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_or_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t vecSrcA, vecSrcB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, vorrq_u32(vecSrcA, vecSrcB) ); + + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrwq_p(pDst, vorrq_u32(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t vecA, vecB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + vecA = vld1q_u32(pSrcA); + vecB = vld1q_u32(pSrcB); + + vst1q_u32(pDst, vorrq_u32(vecA, vecB) ); + + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)|(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} +/** + @} end of Or group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u8.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u8.c new file mode 100644 index 00000000..beee07b6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u8.c @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_or_u8.c + * Description: uint8_t bitwise inclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Or + @{ + */ + +/** + @brief Compute the logical bitwise OR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_or_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t vecSrcA, vecSrcB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, vorrq_u8(vecSrcA, vecSrcB) ); + + pSrcA += 16; + pSrcB += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrbq_p(pDst, vorrq_u8(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t vecA, vecB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4U; + + while (blkCnt > 0U) + { + vecA = vld1q_u8(pSrcA); + vecB = vld1q_u8(pSrcB); + + vst1q_u8(pDst, vorrq_u8(vecA, vecB) ); + + pSrcA += 16; + pSrcB += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)|(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} +/** + @} end of Or group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f16.c new file mode 100644 index 00000000..b4b1c334 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f16.c @@ -0,0 +1,183 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_f16.c + * Description: Multiplies a floating-point vector by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicScale Vector Scale + + Multiply a vector by a scalar value. For floating-point data, the algorithm used is: + +
+      pDst[n] = pSrc[n] * scale,   0 <= n < blockSize.
+  
+ + In the fixed-point Q7, Q15, and Q31 functions, scale is represented by + a fractional multiplication scaleFract and an arithmetic shift shift. + The shift allows the gain of the scaling operation to exceed 1.0. + The algorithm used with fixed-point data is: + +
+      pDst[n] = (pSrc[n] * scaleFract) << shift,   0 <= n < blockSize.
+  
+ + The overall scale factor applied to the fixed-point data is +
+      scale = scaleFract * 2^shift.
+  
+ + The functions support in-place computation allowing the source and destination + pointers to reference the same memory buffer. + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a floating-point vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scale scale factor to be applied + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_scale_f16( + const float16_t * pSrc, + float16_t scale, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f16x8_t vec1; + f16x8_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vmulq(vec1,scale); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vec1 = vld1q((float16_t const *) pSrc); + vstrhq_p(pDst, vmulq(vec1, scale), p0); + } + + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_scale_f16( + const float16_t *pSrc, + float16_t scale, + float16_t *pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrc++) * (_Float16)scale; + + *pDst++ = (_Float16)(*pSrc++) * (_Float16)scale; + + *pDst++ = (_Float16)(*pSrc++) * (_Float16)scale; + + *pDst++ = (_Float16)(*pSrc++) * (_Float16)scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrc++) * (_Float16)scale; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicScale group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c new file mode 100644 index 00000000..59bc813f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c @@ -0,0 +1,216 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_f32.c + * Description: Multiplies a floating-point vector by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicScale Vector Scale + + Multiply a vector by a scalar value. For floating-point data, the algorithm used is: + +
+      pDst[n] = pSrc[n] * scale,   0 <= n < blockSize.
+  
+ + In the fixed-point Q7, Q15, and Q31 functions, scale is represented by + a fractional multiplication scaleFract and an arithmetic shift shift. + The shift allows the gain of the scaling operation to exceed 1.0. + The algorithm used with fixed-point data is: + +
+      pDst[n] = (pSrc[n] * scaleFract) << shift,   0 <= n < blockSize.
+  
+ + The overall scale factor applied to the fixed-point data is +
+      scale = scaleFract * 2^shift.
+  
+ + The functions support in-place computation allowing the source and destination + pointers to reference the same memory buffer. + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a floating-point vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scale scale factor to be applied + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_scale_f32( + const float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f32x4_t vec1; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vmulq(vec1,scale); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vec1 = vld1q((float32_t const *) pSrc); + vstrwq_p(pDst, vmulq(vec1, scale), p0); + } + + +} + +#else +void arm_scale_f32( + const float32_t *pSrc, + float32_t scale, + float32_t *pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ +#if defined(ARM_MATH_NEON_EXPERIMENTAL) + f32x4_t vec1; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale the input and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrc); + res = vmulq_f32(vec1, vdupq_n_f32(scale)); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + float32_t in1, in2, in3, in4; + + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in1 = (*pSrc++) * scale; + + in2 = (*pSrc++) * scale; + + in3 = (*pSrc++) * scale; + + in4 = (*pSrc++) * scale; + + *pDst++ = in1; + *pDst++ = in2; + *pDst++ = in3; + *pDst++ = in4; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON_EXPERIMENTAL) */ + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (*pSrc++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicScale group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f64.c new file mode 100644 index 00000000..cb2452b8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f64.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_f64.c + * Description: Multiplies a floating-point vector by a scalar + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a floating-point vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scale scale factor to be applied + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_scale_f64( + const float64_t *pSrc, + float64_t scale, + float64_t *pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (*pSrc++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicScale group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c new file mode 100644 index 00000000..fbad607f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c @@ -0,0 +1,201 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_q15.c + * Description: Multiplies a Q15 vector by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a Q15 vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scaleFract fractional portion of the scale value + @param[in] shift number of bits to shift the result by + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.15 format. + These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_scale_q15( + const q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q15x8_t vecDst; + + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + /* + * C = A * scale + * Scale the input and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vecDst = vmulhq(vecSrc, vdupq_n_s16(scaleFract)); + vecDst = vqshlq_r(vecDst, shift + 1); + vst1q(pDst, vecDst); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt);; + vecSrc = vld1q(pSrc); + vecDst = vmulhq(vecSrc, vdupq_n_s16(scaleFract)); + vecDst = vqshlq_r(vecDst, shift + 1); + vstrhq_p(pDst, vecDst, p0); + } + +} + + +#else +void arm_scale_q15( + const q15_t *pSrc, + q15_t scaleFract, + int8_t shift, + q15_t *pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + int8_t kShift = 15 - shift; /* Shift to apply after scaling */ + +#if defined (ARM_MATH_LOOPUNROLL) +#if defined (ARM_MATH_DSP) + q31_t inA1, inA2; + q31_t out1, out2, out3, out4; /* Temporary output variables */ + q15_t in1, in2, in3, in4; /* Temporary input variables */ +#endif +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * scale */ + +#if defined (ARM_MATH_DSP) + /* read 2 times 2 samples at a time from source */ + inA1 = read_q15x2_ia (&pSrc); + inA2 = read_q15x2_ia (&pSrc); + + /* Scale inputs and store result in temporary variables + * in single cycle by packing the outputs */ + out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract); + out2 = (q31_t) ((q15_t) (inA1 ) * scaleFract); + out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract); + out4 = (q31_t) ((q15_t) (inA2 ) * scaleFract); + + /* apply shifting */ + out1 = out1 >> kShift; + out2 = out2 >> kShift; + out3 = out3 >> kShift; + out4 = out4 >> kShift; + + /* saturate the output */ + in1 = (q15_t) (__SSAT(out1, 16)); + in2 = (q15_t) (__SSAT(out2, 16)); + in3 = (q15_t) (__SSAT(out3, 16)); + in4 = (q15_t) (__SSAT(out4, 16)); + + /* store result to destination */ + write_q15x2_ia (&pDst, __PKHBT(in2, in1, 16)); + write_q15x2_ia (&pDst, __PKHBT(in4, in3, 16)); +#else + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicScale group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c new file mode 100644 index 00000000..4e28441b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c @@ -0,0 +1,244 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_q31.c + * Description: Multiplies a Q31 vector by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a Q31 vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scaleFract fractional portion of the scale value + @param[in] shift number of bits to shift the result by + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.31 format. + These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_scale_q31( + const q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q31x4_t vecDst; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = A * scale + * Scale the input and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vecDst = vmulhq(vecSrc, vdupq_n_s32(scaleFract)); + vecDst = vqshlq_r(vecDst, shift + 1); + vst1q(pDst, vecDst); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrc = vld1q(pSrc); + vecDst = vmulhq(vecSrc, vdupq_n_s32(scaleFract)); + vecDst = vqshlq_r(vecDst, shift + 1); + vstrwq_p(pDst, vecDst, p0); + } +} + +#else +void arm_scale_q31( + const q31_t *pSrc, + q31_t scaleFract, + int8_t shift, + q31_t *pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in, out; /* Temporary variables */ + int8_t kShift = shift + 1; /* Shift to apply after scaling */ + int8_t sign = (kShift & 0x80); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in = *pSrc++; /* read input from source */ + in = ((q63_t) in * scaleFract) >> 32; /* multiply input with scaler value */ + out = in << kShift; /* apply shifting */ + if (in != (out >> kShift)) /* saturate the result */ + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; /* Store result destination */ + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in = *pSrc++; /* read four inputs from source */ + in = ((q63_t) in * scaleFract) >> 32; /* multiply input with scaler value */ + out = in >> -kShift; /* apply shifting */ + *pDst++ = out; /* Store result destination */ + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in >> -kShift; + *pDst++ = out; + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in >> -kShift; + *pDst++ = out; + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in >> -kShift; + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in >> -kShift; + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicScale group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c new file mode 100644 index 00000000..5bb4580f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c @@ -0,0 +1,186 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_q7.c + * Description: Multiplies a Q7 vector by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a Q7 vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scaleFract fractional portion of the scale value + @param[in] shift number of bits to shift the result by + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.7 format. + These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + +void arm_scale_q7( + const q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7x16_t vecDst; + + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + + while (blkCnt > 0U) + { + /* + * C = A * scale + * Scale the input and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vecDst = vmulhq(vecSrc, vdupq_n_s8(scaleFract)); + vecDst = vqshlq_r(vecDst, shift + 1); + vst1q(pDst, vecDst); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrc = vld1q(pSrc); + vecDst = vmulhq(vecSrc, vdupq_n_s8(scaleFract)); + vecDst = vqshlq_r(vecDst, shift + 1); + vstrbq_p(pDst, vecDst, p0); + } + +} + +#else +void arm_scale_q7( + const q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + int8_t kShift = 7 - shift; /* Shift to apply after scaling */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q7_t in1, in2, in3, in4; /* Temporary input variables */ + q7_t out1, out2, out3, out4; /* Temporary output variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * scale */ + +#if defined (ARM_MATH_DSP) + /* Reading 4 inputs from memory */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* Scale inputs and store result in the temporary variable. */ + out1 = (q7_t) (__SSAT(((in1) * scaleFract) >> kShift, 8)); + out2 = (q7_t) (__SSAT(((in2) * scaleFract) >> kShift, 8)); + out3 = (q7_t) (__SSAT(((in3) * scaleFract) >> kShift, 8)); + out4 = (q7_t) (__SSAT(((in4) * scaleFract) >> kShift, 8)); + + /* Pack and store result in destination buffer (in single write) */ + write_q7x4_ia (&pDst, __PACKq7(out1, out2, out3, out4)); +#else + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicScale group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c new file mode 100644 index 00000000..2de3b2b0 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c @@ -0,0 +1,251 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_shift_q15.c + * Description: Shifts the elements of a Q15 vector by a specified number of bits + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicShift + @{ + */ + +/** + @brief Shifts the elements of a Q15 vector a specified number of bits + @param[in] pSrc points to the input vector + @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_shift_q15( + const q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q15x8_t vecDst; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = A (>> or <<) shiftBits + * Shift the input and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vecDst = vqshlq_r(vecSrc, shiftBits); + vst1q(pDst, vecDst); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrc = vld1q(pSrc); + vecDst = vqshlq_r(vecSrc, shiftBits); + vstrhq_p(pDst, vecDst, p0); + } +} + +#else +void arm_shift_q15( + const q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q15_t in1, in2; /* Temporary input variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + +#if defined (ARM_MATH_DSP) + /* read 2 samples from source */ + in1 = *pSrc++; + in2 = *pSrc++; + + /* Shift the inputs and then store the results in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(__SSAT(((q31_t) in1 << shiftBits), 16), + __SSAT(((q31_t) in2 << shiftBits), 16), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(__SSAT(((q31_t) in2 << shiftBits), 16), + __SSAT(((q31_t) in1 << shiftBits), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* read 2 samples from source */ + in1 = *pSrc++; + in2 = *pSrc++; + +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(__SSAT(((q31_t) in1 << shiftBits), 16), + __SSAT(((q31_t) in2 << shiftBits), 16), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(__SSAT(((q31_t) in2 << shiftBits), 16), + __SSAT(((q31_t) in1 << shiftBits), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + +#else + *pDst++ = __SSAT(((q31_t) *pSrc++ << shiftBits), 16); + *pDst++ = __SSAT(((q31_t) *pSrc++ << shiftBits), 16); + *pDst++ = __SSAT(((q31_t) *pSrc++ << shiftBits), 16); + *pDst++ = __SSAT(((q31_t) *pSrc++ << shiftBits), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + +#if defined (ARM_MATH_DSP) + /* read 2 samples from source */ + in1 = *pSrc++; + in2 = *pSrc++; + + /* Shift the inputs and then store the results in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT((in1 >> -shiftBits), + (in2 >> -shiftBits), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT((in2 >> -shiftBits), + (in1 >> -shiftBits), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* read 2 samples from source */ + in1 = *pSrc++; + in2 = *pSrc++; + +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT((in1 >> -shiftBits), + (in2 >> -shiftBits), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT((in2 >> -shiftBits), + (in1 >> -shiftBits), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + +#else + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = __SSAT(((q31_t) *pSrc++ << shiftBits), 16); + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicShift group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c new file mode 100644 index 00000000..5405c241 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c @@ -0,0 +1,232 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_shift_q31.c + * Description: Shifts the elements of a Q31 vector by a specified number of bits + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ +/** + @defgroup BasicShift Vector Shift + + Shifts the elements of a fixed-point vector by a specified number of bits. + There are separate functions for Q7, Q15, and Q31 data types. + The underlying algorithm used is: + +
+      pDst[n] = pSrc[n] << shift,   0 <= n < blockSize.
+  
+ + If shift is positive then the elements of the vector are shifted to the left. + If shift is negative then the elements of the vector are shifted to the right. + + The functions support in-place computation allowing the source and destination + pointers to reference the same memory buffer. + */ + +/** + @addtogroup BasicShift + @{ + */ + +/** + @brief Shifts the elements of a Q31 vector a specified number of bits. + @param[in] pSrc points to the input vector + @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in the vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_shift_q31( + const q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q31x4_t vecDst; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = A (>> or <<) shiftBits + * Shift the input and then store the result in the destination buffer. + */ + vecSrc = vld1q((q31_t const *) pSrc); + vecDst = vqshlq_r(vecSrc, shiftBits); + vst1q(pDst, vecDst); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrc = vld1q((q31_t const *) pSrc); + vecDst = vqshlq_r(vecSrc, shiftBits); + vstrwq_p(pDst, vecDst, p0); + } +} + + +#else +void arm_shift_q31( + const q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */ + +#if defined (ARM_MATH_LOOPUNROLL) + + q31_t in, out; /* Temporary variables */ + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + + /* Shift input and store result in destination buffer. */ + in = *pSrc++; + out = in << shiftBits; + if (in != (out >> shiftBits)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + in = *pSrc++; + out = in << shiftBits; + if (in != (out >> shiftBits)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + in = *pSrc++; + out = in << shiftBits; + if (in != (out >> shiftBits)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + in = *pSrc++; + out = in << shiftBits; + if (in != (out >> shiftBits)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + + /* Shift input and store results in destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = clip_q63_to_q31((q63_t) *pSrc++ << shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicShift group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c new file mode 100644 index 00000000..4f83edcc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c @@ -0,0 +1,225 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_shift_q7.c + * Description: Processing function for the Q7 Shifting + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicShift + @{ + */ + +/** + @brief Shifts the elements of a Q7 vector a specified number of bits + @param[in] pSrc points to the input vector + @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par onditions for optimum performance + Input and output buffers should be aligned by 32-bit + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_shift_q7( + const q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7x16_t vecDst; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = A (>> or <<) shiftBits + * Shift the input and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vecDst = vqshlq_r(vecSrc, shiftBits); + vst1q(pDst, vecDst); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrc = vld1q(pSrc); + vecDst = vqshlq_r(vecSrc, shiftBits); + vstrbq_p(pDst, vecDst, p0); + } +} + +#else +void arm_shift_q7( + const q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q7_t in1, in2, in3, in4; /* Temporary input variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + +#if defined (ARM_MATH_DSP) + /* Read 4 inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* Pack and store result in destination buffer (in single write) */ + write_q7x4_ia (&pDst, __PACKq7(__SSAT(((q15_t) in1 << shiftBits), 8), + __SSAT(((q15_t) in2 << shiftBits), 8), + __SSAT(((q15_t) in3 << shiftBits), 8), + __SSAT(((q15_t) in4 << shiftBits), 8) )); +#else + *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); + *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); + *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); + *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + +#if defined (ARM_MATH_DSP) + /* Read 4 inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* Pack and store result in destination buffer (in single write) */ + write_q7x4_ia (&pDst, __PACKq7((in1 >> -shiftBits), + (in2 >> -shiftBits), + (in3 >> -shiftBits), + (in4 >> -shiftBits) )); +#else + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicShift group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f16.c new file mode 100644 index 00000000..836ad43b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f16.c @@ -0,0 +1,171 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_f16.c + * Description: Floating-point vector subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicSub Vector Subtraction + + Element-by-element subtraction of two vectors. + +
+      pDst[n] = pSrcA[n] - pSrcB[n],   0 <= n < blockSize.
+  
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Floating-point vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_helium_utils.h" + +void arm_sub_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f16x8_t vec1; + f16x8_t vec2; + f16x8_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + res = vsubq(vec1, vec2); + vst1q(pDst, res); + + /* Increment pointers */ + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + + if (blkCnt > 0U) + { + /* C = A + B */ + mve_pred16_t p0 = vctp16q(blkCnt); + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + vstrhq_p(pDst, vsubq(vec1,vec2), p0); + } + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_sub_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrcA++) - (_Float16)(*pSrcB++); + + *pDst++ = (_Float16)(*pSrcA++) - (_Float16)(*pSrcB++); + + *pDst++ = (_Float16)(*pSrcA++) - (_Float16)(*pSrcB++); + + *pDst++ = (_Float16)(*pSrcA++) - (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrcA++) - (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicSub group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c new file mode 100644 index 00000000..2a07c0c6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c @@ -0,0 +1,202 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_f32.c + * Description: Floating-point vector subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicSub Vector Subtraction + + Element-by-element subtraction of two vectors. + +
+      pDst[n] = pSrcA[n] - pSrcB[n],   0 <= n < blockSize.
+  
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Floating-point vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_sub_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f32x4_t vec1; + f32x4_t vec2; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + res = vsubq(vec1, vec2); + vst1q(pDst, res); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + + if (blkCnt > 0U) + { + /* C = A + B */ + mve_pred16_t p0 = vctp32q(blkCnt); + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + vstrwq_p(pDst, vsubq(vec1,vec2), p0); + } + +} + +#else +void arm_sub_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t vec1; + f32x4_t vec2; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrcA); + vec2 = vld1q_f32(pSrcB); + res = vsubq_f32(vec1, vec2); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (*pSrcA++) - (*pSrcB++); + + *pDst++ = (*pSrcA++) - (*pSrcB++); + + *pDst++ = (*pSrcA++) - (*pSrcB++); + + *pDst++ = (*pSrcA++) - (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (*pSrcA++) - (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicSub group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f64.c new file mode 100644 index 00000000..e409e2ae --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f64.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_f64.c + * Description: Floating-point vector subtraction + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Floating-point vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_sub_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (*pSrcA++) - (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicSub group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c new file mode 100644 index 00000000..575bd9f4 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c @@ -0,0 +1,178 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_q15.c + * Description: Q15 vector subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Q15 vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_sub_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecA; + q15x8_t vecB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = A - B + * Subtract and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqsubq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrhq_p(pDst, vqsubq(vecA, vecB), p0); + } +} + + +#else +void arm_sub_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t inA1, inA2; + q31_t inB1, inB2; +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + +#if defined (ARM_MATH_DSP) + /* read 2 times 2 samples at a time from sourceA */ + inA1 = read_q15x2_ia (&pSrcA); + inA2 = read_q15x2_ia (&pSrcA); + /* read 2 times 2 samples at a time from sourceB */ + inB1 = read_q15x2_ia (&pSrcB); + inB2 = read_q15x2_ia (&pSrcB); + + /* Subtract and store 2 times 2 samples at a time */ + write_q15x2_ia (&pDst, __QSUB16(inA1, inB1)); + write_q15x2_ia (&pDst, __QSUB16(inA2, inB2)); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pDst++ = (q15_t) __QSUB16(*pSrcA++, *pSrcB++); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicSub group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c new file mode 100644 index 00000000..ed879a1e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c @@ -0,0 +1,159 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_q31.c + * Description: Q31 vector subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Q31 vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_sub_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + q31x4_t vecA; + q31x4_t vecB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = A + B + * Add and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqsubq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrwq_p(pDst, vqsubq(vecA, vecB), p0); + } +} + +#else +void arm_sub_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicSub group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c new file mode 100644 index 00000000..1de152e1 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c @@ -0,0 +1,158 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_q7.c + * Description: Q7 vector subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Q7 vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_sub_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecA; + q7x16_t vecB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = A - B + * Subtract and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqsubq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 16; + pSrcB += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrbq_p(pDst, vqsubq(vecA, vecB), p0); + } +} +#else +void arm_sub_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + +#if defined (ARM_MATH_DSP) + /* Subtract and store result in destination buffer (4 samples at a time). */ + write_q7x4_ia (&pDst, __QSUB8(read_q7x4_ia (&pSrcA), read_q7x4_ia (&pSrcB))); +#else + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicSub group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u16.c new file mode 100644 index 00000000..54042ea7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u16.c @@ -0,0 +1,137 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_xor_u16.c + * Description: uint16_t bitwise exclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup Xor Vector bitwise exclusive OR + + Compute the logical bitwise XOR. + + There are separate functions for uint32_t, uint16_t, and uint8_t data types. + */ + +/** + @addtogroup Xor + @{ + */ + +/** + @brief Compute the logical bitwise XOR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_xor_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t vecSrcA, vecSrcB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, veorq_u16(vecSrcA, vecSrcB) ); + + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrhq_p(pDst, veorq_u16(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t vecA, vecB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + vecA = vld1q_u16(pSrcA); + vecB = vld1q_u16(pSrcB); + + vst1q_u16(pDst, veorq_u16(vecA, vecB) ); + + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)^(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of Xor group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u32.c new file mode 100644 index 00000000..9d149084 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u32.c @@ -0,0 +1,129 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_xor_u32.c + * Description: uint32_t bitwise exclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Xor + @{ + */ + +/** + @brief Compute the logical bitwise XOR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_xor_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t vecSrcA, vecSrcB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, veorq_u32(vecSrcA, vecSrcB) ); + + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrwq_p(pDst, veorq_u32(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t vecA, vecB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + vecA = vld1q_u32(pSrcA); + vecB = vld1q_u32(pSrcB); + + vst1q_u32(pDst, veorq_u32(vecA, vecB) ); + + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)^(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of Xor group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u8.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u8.c new file mode 100644 index 00000000..d708cd4e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u8.c @@ -0,0 +1,129 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_xor_u8.c + * Description: uint8_t bitwise exclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Xor + @{ + */ + +/** + @brief Compute the logical bitwise XOR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_xor_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t vecSrcA, vecSrcB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, veorq_u8(vecSrcA, vecSrcB) ); + + pSrcA += 16; + pSrcB += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrbq_p(pDst, veorq_u8(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t vecA, vecB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4U; + + while (blkCnt > 0U) + { + vecA = vld1q_u8(pSrcA); + vecB = vld1q_u8(pSrcB); + + vst1q_u8(pDst, veorq_u8(vecA, vecB) ); + + pSrcA += 16; + pSrcB += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)^(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of Xor group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BayesFunctions/BayesFunctions.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BayesFunctions/BayesFunctions.c new file mode 100644 index 00000000..4a553dc1 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BayesFunctions/BayesFunctions.c @@ -0,0 +1,29 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: BayesFunctions.c + * Description: Combination of all bayes function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_gaussian_naive_bayes_predict_f32.c" diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BayesFunctions/BayesFunctionsF16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BayesFunctions/BayesFunctionsF16.c new file mode 100644 index 00000000..57ced8ca --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BayesFunctions/BayesFunctionsF16.c @@ -0,0 +1,27 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: BayesFunctions.c + * Description: Combination of all bayes function f16 source files. + * + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_gaussian_naive_bayes_predict_f16.c" diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BayesFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Source/BayesFunctions/CMakeLists.txt new file mode 100644 index 00000000..72a202da --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BayesFunctions/CMakeLists.txt @@ -0,0 +1,23 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPBayes) + +include(configLib) +include(configDsp) + +file(GLOB SRC "./*_*.c") + +add_library(CMSISDSPBayes STATIC) + +target_sources(CMSISDSPBayes PRIVATE arm_gaussian_naive_bayes_predict_f32.c) + +configLib(CMSISDSPBayes ${ROOT}) +configDsp(CMSISDSPBayes ${ROOT}) + +### Includes +target_include_directories(CMSISDSPBayes PUBLIC "${DSP}/Include") + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPBayes PRIVATE arm_gaussian_naive_bayes_predict_f16.c) +endif() + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BayesFunctions/arm_gaussian_naive_bayes_predict_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BayesFunctions/arm_gaussian_naive_bayes_predict_f16.c new file mode 100644 index 00000000..b918f704 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BayesFunctions/arm_gaussian_naive_bayes_predict_f16.c @@ -0,0 +1,208 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_naive_gaussian_bayes_predict_f16 + * Description: Naive Gaussian Bayesian Estimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/bayes_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +#define PI_F 3.1415926535897932384626433832795f16 + +/** + * @addtogroup groupBayes + * @{ + */ + +/** + * @brief Naive Gaussian Bayesian Estimator + * + * @param[in] *S points to a naive bayes instance structure + * @param[in] *in points to the elements of the input vector. + * @param[out] *pOutputProbabilities points to a buffer of length numberOfClasses containing estimated probabilities + * @param[out] *pBufferB points to a temporary buffer of length numberOfClasses + * @return The predicted class + * + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math_f16.h" + +uint32_t arm_gaussian_naive_bayes_predict_f16(const arm_gaussian_naive_bayes_instance_f16 *S, + const float16_t * in, + float16_t *pOutputProbabilities, + float16_t *pBufferB + ) +{ + uint32_t nbClass; + const float16_t *pTheta = S->theta; + const float16_t *pSigma = S->sigma; + float16_t *buffer = pOutputProbabilities; + const float16_t *pIn = in; + float16_t result; + f16x8_t vsigma; + _Float16 tmp; + f16x8_t vacc1, vacc2; + uint32_t index; + float16_t *logclassPriors=pBufferB; + float16_t *pLogPrior = logclassPriors; + + arm_vlog_f16((float16_t *) S->classPriors, logclassPriors, S->numberOfClasses); + + pTheta = S->theta; + pSigma = S->sigma; + + for (nbClass = 0; nbClass < S->numberOfClasses; nbClass++) { + pIn = in; + + vacc1 = vdupq_n_f16(0.0f16); + vacc2 = vdupq_n_f16(0.0f16); + + uint32_t blkCnt =S->vectorDimension >> 3; + while (blkCnt > 0U) { + f16x8_t vinvSigma, vtmp; + + vsigma = vaddq_n_f16(vld1q(pSigma), S->epsilon); + vacc1 = vaddq(vacc1, vlogq_f16(vmulq_n_f16(vsigma, 2.0f16 * (_Float16)PI))); + + vinvSigma = vrecip_medprec_f16(vsigma); + + vtmp = vsubq(vld1q(pIn), vld1q(pTheta)); + /* squaring */ + vtmp = vmulq(vtmp, vtmp); + + vacc2 = vfmaq(vacc2, vtmp, vinvSigma); + + pIn += 8; + pTheta += 8; + pSigma += 8; + blkCnt--; + } + + blkCnt = S->vectorDimension & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vinvSigma, vtmp; + + vsigma = vaddq_n_f16(vld1q(pSigma), S->epsilon); + vacc1 = + vaddq_m_f16(vacc1, vacc1, vlogq_f16(vmulq_n_f16(vsigma, 2.0f16 * (_Float16)PI)), p0); + + vinvSigma = vrecip_medprec_f16(vsigma); + + vtmp = vsubq(vld1q(pIn), vld1q(pTheta)); + /* squaring */ + vtmp = vmulq(vtmp, vtmp); + + vacc2 = vfmaq_m_f16(vacc2, vtmp, vinvSigma, p0); + + pTheta += blkCnt; + pSigma += blkCnt; + } + + tmp = -0.5f16 * (_Float16)vecAddAcrossF16Mve(vacc1); + tmp -= 0.5f16 * (_Float16)vecAddAcrossF16Mve(vacc2); + + *buffer = tmp + *pLogPrior++; + buffer++; + } + + arm_max_f16(pOutputProbabilities, S->numberOfClasses, &result, &index); + + return (index); +} + +#else + +uint32_t arm_gaussian_naive_bayes_predict_f16(const arm_gaussian_naive_bayes_instance_f16 *S, + const float16_t * in, + float16_t *pOutputProbabilities, + float16_t *pBufferB) +{ + uint32_t nbClass; + uint32_t nbDim; + const float16_t *pPrior = S->classPriors; + const float16_t *pTheta = S->theta; + const float16_t *pSigma = S->sigma; + float16_t *buffer = pOutputProbabilities; + const float16_t *pIn=in; + float16_t result; + _Float16 sigma; + _Float16 tmp; + _Float16 acc1,acc2; + uint32_t index; + (void)pBufferB; + + pTheta=S->theta; + pSigma=S->sigma; + + for(nbClass = 0; nbClass < S->numberOfClasses; nbClass++) + { + + + pIn = in; + + tmp = 0.0f16; + acc1 = 0.0f16; + acc2 = 0.0f16; + for(nbDim = 0; nbDim < S->vectorDimension; nbDim++) + { + sigma = *pSigma + S->epsilon; + acc1 += logf(2.0f16 * (_Float16)PI_F * sigma); + acc2 += (*pIn - *pTheta) * (*pIn - *pTheta) / sigma; + + pIn++; + pTheta++; + pSigma++; + } + + tmp = -0.5f16 * acc1; + tmp -= 0.5f16 * acc2; + + + *buffer = tmp + logf(*pPrior++); + buffer++; + } + + arm_max_f16(pOutputProbabilities,S->numberOfClasses,&result,&index); + + return(index); +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of groupBayes group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/BayesFunctions/arm_gaussian_naive_bayes_predict_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/BayesFunctions/arm_gaussian_naive_bayes_predict_f32.c new file mode 100644 index 00000000..56331ff5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/BayesFunctions/arm_gaussian_naive_bayes_predict_f32.c @@ -0,0 +1,396 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_naive_gaussian_bayes_predict_f32 + * Description: Naive Gaussian Bayesian Estimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/bayes_functions.h" +#include +#include + +#define PI_F 3.1415926535897932384626433832795f +#define DPI_F (2.0f*3.1415926535897932384626433832795f) + +/** + * @addtogroup groupBayes + * @{ + */ + +/** + * @brief Naive Gaussian Bayesian Estimator + * + * @param[in] *S points to a naive bayes instance structure + * @param[in] *in points to the elements of the input vector. + * @param[out] *pOutputProbabilities points to a buffer of length numberOfClasses containing estimated probabilities + * @param[out] *pBufferB points to a temporary buffer of length numberOfClasses + * @return The predicted class + * + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S, + const float32_t * in, + float32_t *pOutputProbabilities, + float32_t *pBufferB + ) +{ + uint32_t nbClass; + const float32_t *pTheta = S->theta; + const float32_t *pSigma = S->sigma; + float32_t *buffer = pOutputProbabilities; + const float32_t *pIn = in; + float32_t result; + f32x4_t vsigma; + float32_t tmp; + f32x4_t vacc1, vacc2; + uint32_t index; + float32_t *logclassPriors=pBufferB; + float32_t *pLogPrior = logclassPriors; + + arm_vlog_f32((float32_t *) S->classPriors, logclassPriors, S->numberOfClasses); + + pTheta = S->theta; + pSigma = S->sigma; + + for (nbClass = 0; nbClass < S->numberOfClasses; nbClass++) { + pIn = in; + + vacc1 = vdupq_n_f32(0); + vacc2 = vdupq_n_f32(0); + + uint32_t blkCnt =S->vectorDimension >> 2; + while (blkCnt > 0U) { + f32x4_t vinvSigma, vtmp; + + vsigma = vaddq_n_f32(vld1q(pSigma), S->epsilon); + vacc1 = vaddq(vacc1, vlogq_f32(vmulq_n_f32(vsigma, 2.0f * PI))); + + vinvSigma = vrecip_medprec_f32(vsigma); + + vtmp = vsubq(vld1q(pIn), vld1q(pTheta)); + /* squaring */ + vtmp = vmulq(vtmp, vtmp); + + vacc2 = vfmaq(vacc2, vtmp, vinvSigma); + + pIn += 4; + pTheta += 4; + pSigma += 4; + blkCnt--; + } + + blkCnt = S->vectorDimension & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vinvSigma, vtmp; + + vsigma = vaddq_n_f32(vld1q(pSigma), S->epsilon); + vacc1 = + vaddq_m_f32(vacc1, vacc1, vlogq_f32(vmulq_n_f32(vsigma, 2.0f * PI)), p0); + + vinvSigma = vrecip_medprec_f32(vsigma); + + vtmp = vsubq(vld1q(pIn), vld1q(pTheta)); + /* squaring */ + vtmp = vmulq(vtmp, vtmp); + + vacc2 = vfmaq_m_f32(vacc2, vtmp, vinvSigma, p0); + + pTheta += blkCnt; + pSigma += blkCnt; + } + + tmp = -0.5f * vecAddAcrossF32Mve(vacc1); + tmp -= 0.5f * vecAddAcrossF32Mve(vacc2); + + *buffer = tmp + *pLogPrior++; + buffer++; + } + + arm_max_f32(pOutputProbabilities, S->numberOfClasses, &result, &index); + + return (index); +} + +#else + +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + + + +uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S, + const float32_t * in, + float32_t *pOutputProbabilities, + float32_t *pBufferB) +{ + + const float32_t *pPrior = S->classPriors; + + const float32_t *pTheta = S->theta; + const float32_t *pSigma = S->sigma; + + const float32_t *pTheta1 = S->theta + S->vectorDimension; + const float32_t *pSigma1 = S->sigma + S->vectorDimension; + + float32_t *buffer = pOutputProbabilities; + const float32_t *pIn=in; + + float32_t result; + float32_t sigma,sigma1; + float32_t tmp,tmp1; + uint32_t index; + uint32_t vecBlkCnt; + uint32_t classBlkCnt; + float32x4_t epsilonV; + float32x4_t sigmaV,sigmaV1; + float32x4_t tmpV,tmpVb,tmpV1; + float32x2_t tmpV2; + float32x4_t thetaV,thetaV1; + float32x4_t inV; + (void)pBufferB; + + epsilonV = vdupq_n_f32(S->epsilon); + + classBlkCnt = S->numberOfClasses >> 1; + while(classBlkCnt > 0) + { + + + pIn = in; + + tmp = logf(*pPrior++); + tmp1 = logf(*pPrior++); + tmpV = vdupq_n_f32(0.0f); + tmpV1 = vdupq_n_f32(0.0f); + + vecBlkCnt = S->vectorDimension >> 2; + while(vecBlkCnt > 0) + { + sigmaV = vld1q_f32(pSigma); + thetaV = vld1q_f32(pTheta); + + sigmaV1 = vld1q_f32(pSigma1); + thetaV1 = vld1q_f32(pTheta1); + + inV = vld1q_f32(pIn); + + sigmaV = vaddq_f32(sigmaV, epsilonV); + sigmaV1 = vaddq_f32(sigmaV1, epsilonV); + + tmpVb = vmulq_n_f32(sigmaV,DPI_F); + tmpVb = vlogq_f32(tmpVb); + tmpV = vmlsq_n_f32(tmpV,tmpVb,0.5f); + + tmpVb = vmulq_n_f32(sigmaV1,DPI_F); + tmpVb = vlogq_f32(tmpVb); + tmpV1 = vmlsq_n_f32(tmpV1,tmpVb,0.5f); + + tmpVb = vsubq_f32(inV,thetaV); + tmpVb = vmulq_f32(tmpVb,tmpVb); + tmpVb = vmulq_f32(tmpVb, vinvq_f32(sigmaV)); + tmpV = vmlsq_n_f32(tmpV,tmpVb,0.5f); + + tmpVb = vsubq_f32(inV,thetaV1); + tmpVb = vmulq_f32(tmpVb,tmpVb); + tmpVb = vmulq_f32(tmpVb, vinvq_f32(sigmaV1)); + tmpV1 = vmlsq_n_f32(tmpV1,tmpVb,0.5f); + + pIn += 4; + pTheta += 4; + pSigma += 4; + pTheta1 += 4; + pSigma1 += 4; + + vecBlkCnt--; + } + tmpV2 = vpadd_f32(vget_low_f32(tmpV),vget_high_f32(tmpV)); + tmp += vget_lane_f32(tmpV2, 0) + vget_lane_f32(tmpV2, 1); + + tmpV2 = vpadd_f32(vget_low_f32(tmpV1),vget_high_f32(tmpV1)); + tmp1 += vget_lane_f32(tmpV2, 0) + vget_lane_f32(tmpV2, 1); + + vecBlkCnt = S->vectorDimension & 3; + while(vecBlkCnt > 0) + { + sigma = *pSigma + S->epsilon; + sigma1 = *pSigma1 + S->epsilon; + + tmp -= 0.5f*logf(2.0f * PI_F * sigma); + tmp -= 0.5f*(*pIn - *pTheta) * (*pIn - *pTheta) / sigma; + + tmp1 -= 0.5f*logf(2.0f * PI_F * sigma1); + tmp1 -= 0.5f*(*pIn - *pTheta1) * (*pIn - *pTheta1) / sigma1; + + pIn++; + pTheta++; + pSigma++; + pTheta1++; + pSigma1++; + vecBlkCnt--; + } + + *buffer++ = tmp; + *buffer++ = tmp1; + + pSigma += S->vectorDimension; + pTheta += S->vectorDimension; + pSigma1 += S->vectorDimension; + pTheta1 += S->vectorDimension; + + classBlkCnt--; + } + + classBlkCnt = S->numberOfClasses & 1; + + while(classBlkCnt > 0) + { + + + pIn = in; + + tmp = logf(*pPrior++); + tmpV = vdupq_n_f32(0.0f); + + vecBlkCnt = S->vectorDimension >> 2; + while(vecBlkCnt > 0) + { + sigmaV = vld1q_f32(pSigma); + thetaV = vld1q_f32(pTheta); + inV = vld1q_f32(pIn); + + sigmaV = vaddq_f32(sigmaV, epsilonV); + + tmpVb = vmulq_n_f32(sigmaV,DPI_F); + tmpVb = vlogq_f32(tmpVb); + tmpV = vmlsq_n_f32(tmpV,tmpVb,0.5f); + + tmpVb = vsubq_f32(inV,thetaV); + tmpVb = vmulq_f32(tmpVb,tmpVb); + tmpVb = vmulq_f32(tmpVb, vinvq_f32(sigmaV)); + tmpV = vmlsq_n_f32(tmpV,tmpVb,0.5f); + + pIn += 4; + pTheta += 4; + pSigma += 4; + + vecBlkCnt--; + } + tmpV2 = vpadd_f32(vget_low_f32(tmpV),vget_high_f32(tmpV)); + tmp += vget_lane_f32(tmpV2, 0) + vget_lane_f32(tmpV2, 1); + + vecBlkCnt = S->vectorDimension & 3; + while(vecBlkCnt > 0) + { + sigma = *pSigma + S->epsilon; + tmp -= 0.5f*logf(2.0f * PI_F * sigma); + tmp -= 0.5f*(*pIn - *pTheta) * (*pIn - *pTheta) / sigma; + + pIn++; + pTheta++; + pSigma++; + vecBlkCnt--; + } + + *buffer++ = tmp; + + classBlkCnt--; + } + + arm_max_f32(pOutputProbabilities,S->numberOfClasses,&result,&index); + + return(index); +} + +#else + +uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S, + const float32_t * in, + float32_t *pOutputProbabilities, + float32_t *pBufferB) +{ + uint32_t nbClass; + uint32_t nbDim; + const float32_t *pPrior = S->classPriors; + const float32_t *pTheta = S->theta; + const float32_t *pSigma = S->sigma; + float32_t *buffer = pOutputProbabilities; + const float32_t *pIn=in; + float32_t result; + float32_t sigma; + float32_t tmp; + float32_t acc1,acc2; + uint32_t index; + + (void)pBufferB; + + pTheta=S->theta; + pSigma=S->sigma; + + for(nbClass = 0; nbClass < S->numberOfClasses; nbClass++) + { + + + pIn = in; + + tmp = 0.0; + acc1 = 0.0f; + acc2 = 0.0f; + for(nbDim = 0; nbDim < S->vectorDimension; nbDim++) + { + sigma = *pSigma + S->epsilon; + acc1 += logf(2.0f * PI_F * sigma); + acc2 += (*pIn - *pTheta) * (*pIn - *pTheta) / sigma; + + pIn++; + pTheta++; + pSigma++; + } + + tmp = -0.5f * acc1; + tmp -= 0.5f * acc2; + + + *buffer = tmp + logf(*pPrior++); + buffer++; + } + + arm_max_f32(pOutputProbabilities,S->numberOfClasses,&result,&index); + + return(index); +} + +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of groupBayes group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Source/CMakeLists.txt new file mode 100644 index 00000000..35952855 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/CMakeLists.txt @@ -0,0 +1,310 @@ +cmake_minimum_required (VERSION 3.14) +cmake_policy(SET CMP0077 NEW) +project(CMSISDSP) + +# DSP Sources +SET(DSP ${ROOT}/CMSIS/DSP) + +list(APPEND CMAKE_MODULE_PATH ${DSP}/Source) +list(APPEND CMAKE_MODULE_PATH ${DSP}) + + +include(configLib) + + +option(NEON "Neon acceleration" OFF) +option(NEONEXPERIMENTAL "Neon experimental acceleration" OFF) +option(HELIUMEXPERIMENTAL "Helium experimental acceleration" OFF) +option(LOOPUNROLL "Loop unrolling" ON) +option(ROUNDING "Rounding" OFF) +option(MATRIXCHECK "Matrix Checks" OFF) +option(HELIUM "Helium acceleration (MVEF and MVEI supported)" OFF) +option(MVEF "MVEF intrinsics supported" OFF) +option(MVEI "MVEI intrinsics supported" OFF) +option(MVEFLOAT16 "Float16 MVE intrinsics supported" OFF) +option(DISABLEFLOAT16 "Disable building float16 kernels" OFF) +option(HOST "Build for host" OFF) + +# Select which parts of the CMSIS-DSP must be compiled. +# There are some dependencies between the parts but they are not tracked +# by this cmake. So, enabling some functions may require to enable some +# other ones. +option(BASICMATH "Basic Math Functions" ON) +option(COMPLEXMATH "Complex Math Functions" ON) +option(CONTROLLER "Controller Functions" ON) +option(FASTMATH "Fast Math Functions" ON) +option(FILTERING "Filtering Functions" ON) +option(MATRIX "Matrix Functions" ON) +option(STATISTICS "Statistics Functions" ON) +option(SUPPORT "Support Functions" ON) +option(TRANSFORM "Transform Functions" ON) +option(SVM "Support Vector Machine Functions" ON) +option(BAYES "Bayesian Estimators" ON) +option(DISTANCE "Distance Functions" ON) +option(INTERPOLATION "Interpolation Functions" ON) +option(QUATERNIONMATH "Quaternion Math Functions" ON) + +# When OFF it is the default behavior : all tables are included. +option(CONFIGTABLE "Configuration of table allowed" OFF) + +# When CONFIGTABLE is ON, select if all interpolation tables must be included +option(ALLFAST "All interpolation tables included" OFF) +# When CONFIGTABLE is ON, select if all FFT tables must be included +option(ALLFFT "All fft tables included" OFF) + +# Features which require inclusion of a data table. +# Since some tables may be big, the corresponding feature can be +# disabled. +# Those options are taken into account only when CONFIGTABLE is ON +option(ARM_COS_F32 "cos f32" OFF) +option(ARM_COS_Q31 "cos q31" OFF) +option(ARM_COS_Q15 "cos q15" OFF) +option(ARM_SIN_F32 "sin f32" OFF) +option(ARM_SIN_Q31 "sin q31" OFF) +option(ARM_SIN_Q15 "sin q15" OFF) +option(ARM_SIN_COS_F32 "sin cos f32" OFF) +option(ARM_SIN_COS_Q31 "sin cos q31" OFF) + +option(ARM_LMS_NORM_Q31 "lms norm q31" OFF) +option(ARM_LMS_NORM_Q15 "lms norm q15" OFF) + +option(CFFT_F64_16 "cfft f64 16" OFF) +option(CFFT_F64_32 "cfft f64 32" OFF) +option(CFFT_F64_64 "cfft f64 64" OFF) +option(CFFT_F64_128 "cfft f64 128" OFF) +option(CFFT_F64_256 "cfft f64 256" OFF) +option(CFFT_F64_512 "cfft f64 512" OFF) +option(CFFT_F64_1024 "cfft f64 1024" OFF) +option(CFFT_F64_2048 "cfft f64 2048" OFF) +option(CFFT_F64_4096 "cfft f64 4096" OFF) + +option(CFFT_F32_16 "cfft f32 16" OFF) +option(CFFT_F32_32 "cfft f32 32" OFF) +option(CFFT_F32_64 "cfft f32 64" OFF) +option(CFFT_F32_128 "cfft f32 128" OFF) +option(CFFT_F32_256 "cfft f32 256" OFF) +option(CFFT_F32_512 "cfft f32 512" OFF) +option(CFFT_F32_1024 "cfft f32 1024" OFF) +option(CFFT_F32_2048 "cfft f32 2048" OFF) +option(CFFT_F32_4096 "cfft f32 4096" OFF) + +option(CFFT_Q31_16 "cfft q31 16" OFF) +option(CFFT_Q31_32 "cfft q31 32" OFF) +option(CFFT_Q31_64 "cfft q31 64" OFF) +option(CFFT_Q31_128 "cfft q31 128" OFF) +option(CFFT_Q31_256 "cfft q31 256" OFF) +option(CFFT_Q31_512 "cfft q31 512" OFF) +option(CFFT_Q31_1024 "cfft q31 1024" OFF) +option(CFFT_Q31_2048 "cfft q31 2048" OFF) +option(CFFT_Q31_4096 "cfft q31 4096" OFF) + +option(CFFT_Q15_16 "cfft q15 16" OFF) +option(CFFT_Q15_32 "cfft q15 32" OFF) +option(CFFT_Q15_64 "cfft q15 64" OFF) +option(CFFT_Q15_128 "cfft q15 128" OFF) +option(CFFT_Q15_256 "cfft q15 256" OFF) +option(CFFT_Q15_512 "cfft q15 512" OFF) +option(CFFT_Q15_1024 "cfft q15 1024" OFF) +option(CFFT_Q15_2048 "cfft q15 2048" OFF) +option(CFFT_Q15_4096 "cfft q15 4096" OFF) + +option(RFFT_FAST_F32_32 "rfft fast f32 32" OFF) +option(RFFT_FAST_F32_64 "rfft fast f32 64" OFF) +option(RFFT_FAST_F32_128 "rfft fast f32 128" OFF) +option(RFFT_FAST_F32_256 "rfft fast f32 256" OFF) +option(RFFT_FAST_F32_512 "rfft fast f32 512" OFF) +option(RFFT_FAST_F32_1024 "rfft fast f32 1024" OFF) +option(RFFT_FAST_F32_2048 "rfft fast f32 2048" OFF) +option(RFFT_FAST_F32_4096 "rfft fast f32 4096" OFF) + + +option(RFFT_F32_128 "rfft f32 128" OFF) +option(RFFT_F32_512 "rfft f32 512" OFF) +option(RFFT_F32_2048 "rfft f32 2048" OFF) +option(RFFT_F32_8192 "rfft f32 8192" OFF) + +option(RFFT_FAST_F64_32 "rfft fast f64 32" OFF) +option(RFFT_FAST_F64_64 "rfft fast f64 64" OFF) +option(RFFT_FAST_F64_128 "rfft fast f64 128" OFF) +option(RFFT_FAST_F64_256 "rfft fast f64 256" OFF) +option(RFFT_FAST_F64_512 "rfft fast f64 512" OFF) +option(RFFT_FAST_F64_1024 "rfft fast f64 1024" OFF) +option(RFFT_FAST_F64_2048 "rfft fast f64 2048" OFF) +option(RFFT_FAST_F64_4096 "rfft fast f64 4096" OFF) + + +option(RFFT_F64_128 "rfft f64 128" OFF) +option(RFFT_F64_512 "rfft f64 512" OFF) +option(RFFT_F64_2048 "rfft f64 2048" OFF) +option(RFFT_F64_8192 "rfft f64 8192" OFF) + +option(RFFT_FAST_F16_32 "rfft fast f16 32" OFF) +option(RFFT_FAST_F16_64 "rfft fast f16 64" OFF) +option(RFFT_FAST_F16_128 "rfft fast f16 128" OFF) +option(RFFT_FAST_F16_256 "rfft fast f16 256" OFF) +option(RFFT_FAST_F16_512 "rfft fast f16 512" OFF) +option(RFFT_FAST_F16_1024 "rfft fast f16 1024" OFF) +option(RFFT_FAST_F16_2048 "rfft fast f16 2048" OFF) +option(RFFT_FAST_F16_4096 "rfft fast f16 4096" OFF) + +option(RFFT_Q31_32 "rfft q31 32" OFF) +option(RFFT_Q31_64 "rfft q31 64" OFF) +option(RFFT_Q31_128 "rfft q31 128" OFF) +option(RFFT_Q31_256 "rfft q31 256" OFF) +option(RFFT_Q31_512 "rfft q31 512" OFF) +option(RFFT_Q31_1024 "rfft q31 1024" OFF) +option(RFFT_Q31_2048 "rfft q31 2048" OFF) +option(RFFT_Q31_4096 "rfft q31 4096" OFF) +option(RFFT_Q31_8192 "rfft q31 8192" OFF) + +option(RFFT_Q15_32 "rfft q15 32" OFF) +option(RFFT_Q15_64 "rfft q15 64" OFF) +option(RFFT_Q15_128 "rfft q15 128" OFF) +option(RFFT_Q15_256 "rfft q15 256" OFF) +option(RFFT_Q15_512 "rfft q15 512" OFF) +option(RFFT_Q15_1024 "rfft q15 1024" OFF) +option(RFFT_Q15_2048 "rfft q15 2048" OFF) +option(RFFT_Q15_4096 "rfft q15 4096" OFF) +option(RFFT_Q15_8192 "rfft q15 8192" OFF) + +option(DCT4_F32_128 "dct4 f32 128" OFF) +option(DCT4_F32_512 "dct4 f32 512" OFF) +option(DCT4_F32_2048 "dct4 f32 2048" OFF) +option(DCT4_F32_8192 "dct4 f32 8192" OFF) + +option(DCT4_Q31_128 "dct4 q31 128" OFF) +option(DCT4_Q31_512 "dct4 q31 512" OFF) +option(DCT4_Q31_2048 "dct4 q31 2048" OFF) +option(DCT4_Q31_8192 "dct4 q31 8192" OFF) + +option(DCT4_Q15_128 "dct4 q15 128" OFF) +option(DCT4_Q15_512 "dct4 q15 512" OFF) +option(DCT4_Q15_2048 "dct4 q15 2048" OFF) +option(DCT4_Q15_8192 "dct4 q15 8192" OFF) + +option(ARM_CFFT_RADIX2_Q15 "deprecated q15 radix2 cfft" OFF) +option(ARM_CFFT_RADIX4_Q15 "deprecated q15 radix4 cfft" OFF) + +option(ARM_CFFT_RADIX2_Q31 "deprecated q31 radix2 cfft" OFF) +option(ARM_CFFT_RADIX4_Q31 "deprecated q31 radix4 cfft" OFF) + +########################### +# +# CMSIS DSP +# +########################### + + + +add_library(CMSISDSP INTERFACE) + +if (BASICMATH) + add_subdirectory(BasicMathFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPBasicMath) +endif() + +if (COMPLEXMATH) + add_subdirectory(ComplexMathFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPComplexMath) +endif() + +if (QUATERNIONMATH) + add_subdirectory(QuaternionMathFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPQuaternionMath) +endif() + +if (CONTROLLER) + add_subdirectory(ControllerFunctions) + # Fast tables inclusion is allowed + if (CONFIGTABLE) + target_compile_definitions(CMSISDSPController PUBLIC ARM_FAST_ALLOW_TABLES) + endif() + target_link_libraries(CMSISDSP INTERFACE CMSISDSPController) +endif() + +if (FASTMATH) + add_subdirectory(FastMathFunctions) + # Fast tables inclusion is allowed + if (CONFIGTABLE) + target_compile_definitions(CMSISDSPFastMath PUBLIC ARM_FAST_ALLOW_TABLES) + endif() + target_link_libraries(CMSISDSP INTERFACE CMSISDSPFastMath) +endif() + +if (FILTERING) + add_subdirectory(FilteringFunctions) + # Fast tables inclusion is allowed + if (CONFIGTABLE) + target_compile_definitions(CMSISDSPFiltering PUBLIC ARM_FAST_ALLOW_TABLES) + endif() + target_link_libraries(CMSISDSP INTERFACE CMSISDSPFiltering) +endif() + +if (MATRIX) + add_subdirectory(MatrixFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPMatrix) +endif() + +if (STATISTICS) + add_subdirectory(StatisticsFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPStatistics) +endif() + +if (SUPPORT) + add_subdirectory(SupportFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPSupport) +endif() + +if (TRANSFORM) + add_subdirectory(TransformFunctions) + # FFT tables inclusion is allowed + if (CONFIGTABLE) + target_compile_definitions(CMSISDSPTransform PUBLIC ARM_FFT_ALLOW_TABLES) + endif() + target_link_libraries(CMSISDSP INTERFACE CMSISDSPTransform) +endif() + +if (FILTERING OR CONTROLLER OR FASTMATH OR TRANSFORM OR SVM OR DISTANCE) + add_subdirectory(CommonTables) + if (TRANSFORM) + # FFT tables inclusion is allowed + if (CONFIGTABLE) + target_compile_definitions(CMSISDSPCommon PUBLIC ARM_FFT_ALLOW_TABLES) + endif() + endif() + if (FILTERING OR CONTROLLER OR FASTMATH) + # Select which tables to include + if (CONFIGTABLE) + target_compile_definitions(CMSISDSPCommon PUBLIC ARM_FAST_ALLOW_TABLES) + endif() + endif() + target_link_libraries(CMSISDSP INTERFACE CMSISDSPCommon) + # Common project is adding ComputeLibrary tables used by SVM and Distance + # when NEon is ON. +endif() + +if (SVM) + add_subdirectory(SVMFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPSVM) +endif() + +if (BAYES) + add_subdirectory(BayesFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPBayes) +endif() + +if (DISTANCE) + add_subdirectory(DistanceFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPDistance) +endif() + +if (INTERPOLATION) + add_subdirectory(InterpolationFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPInterpolation) +endif() + +### Includes +target_include_directories(CMSISDSP INTERFACE "${DSP}/Include") + + + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/CMakeLists.txt new file mode 100644 index 00000000..b6e0ed43 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/CMakeLists.txt @@ -0,0 +1,52 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPCommon) + +include(configLib) +include(configDsp) + +add_library(CMSISDSPCommon STATIC arm_common_tables.c arm_common_tables_f16.c) + +configLib(CMSISDSPCommon ${ROOT}) +configDsp(CMSISDSPCommon ${ROOT}) + +if (CONFIGTABLE AND ALLFFT) + target_compile_definitions(CMSISDSPCommon PUBLIC ARM_ALL_FFT_TABLES) +endif() + +if (CONFIGTABLE AND ALLFAST) + target_compile_definitions(CMSISDSPCommon PUBLIC ARM_ALL_FAST_TABLES) +endif() + +include(fft) +fft(CMSISDSPCommon) + +include(interpol) +interpol(CMSISDSPCommon) + +target_sources(CMSISDSPCommon PRIVATE arm_const_structs.c) +target_sources(CMSISDSPCommon PRIVATE arm_const_structs_f16.c) + + +### Includes +target_include_directories(CMSISDSPCommon PUBLIC "${DSP}/Include") + +if (NEON OR NEONEXPERIMENTAL) + target_sources(CMSISDSPCommon PRIVATE "${DSP}/ComputeLibrary/Source/arm_cl_tables.c") +endif() + +if (HELIUM OR MVEF) + target_sources(CMSISDSPCommon PRIVATE "${DSP}/Source/CommonTables/arm_mve_tables.c") + target_sources(CMSISDSPCommon PRIVATE "${DSP}/Source/CommonTables/arm_mve_tables_f16.c") +endif() + + +if (WRAPPER) + target_compile_definitions(CMSISDSPCommon PUBLIC ARM_TABLE_BITREV_1024) + target_compile_definitions(CMSISDSPCommon PUBLIC ARM_TABLE_TWIDDLECOEF_F32_4096) + target_compile_definitions(CMSISDSPCommon PUBLIC ARM_TABLE_TWIDDLECOEF_Q31_4096) + target_compile_definitions(CMSISDSPCommon PUBLIC ARM_TABLE_TWIDDLECOEF_Q15_4096) + if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) + target_compile_definitions(CMSISDSPCommon PUBLIC ARM_TABLE_TWIDDLECOEF_F16_4096) + endif() +endif() \ No newline at end of file diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/CommonTables.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/CommonTables.c new file mode 100644 index 00000000..1a387c35 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/CommonTables.c @@ -0,0 +1,31 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: CommonTables.c + * Description: Combination of all common table source files. + * + * $Date: 08. January 2020 + * $Revision: V1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_common_tables.c" +#include "arm_const_structs.c" +#include "arm_mve_tables.c" diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/CommonTablesF16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/CommonTablesF16.c new file mode 100644 index 00000000..c3e79d74 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/CommonTablesF16.c @@ -0,0 +1,31 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: CommonTables.c + * Description: Combination of all common table source files. + * + * $Date: 08. January 2020 + * $Revision: V1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_common_tables_f16.c" +#include "arm_const_structs_f16.c" +#include "arm_mve_tables_f16.c" diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.c new file mode 100644 index 00000000..b3cb89cd --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.c @@ -0,0 +1,70576 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.c + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math_types.h" +#include "arm_common_tables.h" + +/** + @ingroup ComplexFFT + */ + +/** + @addtogroup CFFT_CIFFT Complex FFT Tables + @{ + */ + +/** + @par + Pseudo code for Generation of Bit reversal Table is + @par +
for (l = 1; l <= N/4; l++)
+  {
+    for (i = 0; i< logN2; i++)
+    {
+      a[i] = l & (1 << i);
+    }
+    for (j = 0; j < logN2; j++)
+    {
+      if (a[j] != 0)
+      y[l] += (1 << ((logN2 - 1) - j));
+    }
+    y[l] = y[l] >> 1;
+   } 
+ @par + where N = 4096, logN2 = 12 + @par + N is the maximum FFT Size supported +*/ + +/** + @brief Table for bit reversal process +*/ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) +const uint16_t armBitRevTable[1024] = { + 0x400, 0x200, 0x600, 0x100, 0x500, 0x300, 0x700, 0x080, 0x480, 0x280, + 0x680, 0x180, 0x580, 0x380, 0x780, 0x040, 0x440, 0x240, 0x640, 0x140, + 0x540, 0x340, 0x740, 0x0c0, 0x4c0, 0x2c0, 0x6c0, 0x1c0, 0x5c0, 0x3c0, + 0x7c0, 0x020, 0x420, 0x220, 0x620, 0x120, 0x520, 0x320, 0x720, 0x0a0, + 0x4a0, 0x2a0, 0x6a0, 0x1a0, 0x5a0, 0x3a0, 0x7a0, 0x060, 0x460, 0x260, + 0x660, 0x160, 0x560, 0x360, 0x760, 0x0e0, 0x4e0, 0x2e0, 0x6e0, 0x1e0, + 0x5e0, 0x3e0, 0x7e0, 0x010, 0x410, 0x210, 0x610, 0x110, 0x510, 0x310, + 0x710, 0x090, 0x490, 0x290, 0x690, 0x190, 0x590, 0x390, 0x790, 0x050, + 0x450, 0x250, 0x650, 0x150, 0x550, 0x350, 0x750, 0x0d0, 0x4d0, 0x2d0, + 0x6d0, 0x1d0, 0x5d0, 0x3d0, 0x7d0, 0x030, 0x430, 0x230, 0x630, 0x130, + 0x530, 0x330, 0x730, 0x0b0, 0x4b0, 0x2b0, 0x6b0, 0x1b0, 0x5b0, 0x3b0, + 0x7b0, 0x070, 0x470, 0x270, 0x670, 0x170, 0x570, 0x370, 0x770, 0x0f0, + 0x4f0, 0x2f0, 0x6f0, 0x1f0, 0x5f0, 0x3f0, 0x7f0, 0x008, 0x408, 0x208, + 0x608, 0x108, 0x508, 0x308, 0x708, 0x088, 0x488, 0x288, 0x688, 0x188, + 0x588, 0x388, 0x788, 0x048, 0x448, 0x248, 0x648, 0x148, 0x548, 0x348, + 0x748, 0x0c8, 0x4c8, 0x2c8, 0x6c8, 0x1c8, 0x5c8, 0x3c8, 0x7c8, 0x028, + 0x428, 0x228, 0x628, 0x128, 0x528, 0x328, 0x728, 0x0a8, 0x4a8, 0x2a8, + 0x6a8, 0x1a8, 0x5a8, 0x3a8, 0x7a8, 0x068, 0x468, 0x268, 0x668, 0x168, + 0x568, 0x368, 0x768, 0x0e8, 0x4e8, 0x2e8, 0x6e8, 0x1e8, 0x5e8, 0x3e8, + 0x7e8, 0x018, 0x418, 0x218, 0x618, 0x118, 0x518, 0x318, 0x718, 0x098, + 0x498, 0x298, 0x698, 0x198, 0x598, 0x398, 0x798, 0x058, 0x458, 0x258, + 0x658, 0x158, 0x558, 0x358, 0x758, 0x0d8, 0x4d8, 0x2d8, 0x6d8, 0x1d8, + 0x5d8, 0x3d8, 0x7d8, 0x038, 0x438, 0x238, 0x638, 0x138, 0x538, 0x338, + 0x738, 0x0b8, 0x4b8, 0x2b8, 0x6b8, 0x1b8, 0x5b8, 0x3b8, 0x7b8, 0x078, + 0x478, 0x278, 0x678, 0x178, 0x578, 0x378, 0x778, 0x0f8, 0x4f8, 0x2f8, + 0x6f8, 0x1f8, 0x5f8, 0x3f8, 0x7f8, 0x004, 0x404, 0x204, 0x604, 0x104, + 0x504, 0x304, 0x704, 0x084, 0x484, 0x284, 0x684, 0x184, 0x584, 0x384, + 0x784, 0x044, 0x444, 0x244, 0x644, 0x144, 0x544, 0x344, 0x744, 0x0c4, + 0x4c4, 0x2c4, 0x6c4, 0x1c4, 0x5c4, 0x3c4, 0x7c4, 0x024, 0x424, 0x224, + 0x624, 0x124, 0x524, 0x324, 0x724, 0x0a4, 0x4a4, 0x2a4, 0x6a4, 0x1a4, + 0x5a4, 0x3a4, 0x7a4, 0x064, 0x464, 0x264, 0x664, 0x164, 0x564, 0x364, + 0x764, 0x0e4, 0x4e4, 0x2e4, 0x6e4, 0x1e4, 0x5e4, 0x3e4, 0x7e4, 0x014, + 0x414, 0x214, 0x614, 0x114, 0x514, 0x314, 0x714, 0x094, 0x494, 0x294, + 0x694, 0x194, 0x594, 0x394, 0x794, 0x054, 0x454, 0x254, 0x654, 0x154, + 0x554, 0x354, 0x754, 0x0d4, 0x4d4, 0x2d4, 0x6d4, 0x1d4, 0x5d4, 0x3d4, + 0x7d4, 0x034, 0x434, 0x234, 0x634, 0x134, 0x534, 0x334, 0x734, 0x0b4, + 0x4b4, 0x2b4, 0x6b4, 0x1b4, 0x5b4, 0x3b4, 0x7b4, 0x074, 0x474, 0x274, + 0x674, 0x174, 0x574, 0x374, 0x774, 0x0f4, 0x4f4, 0x2f4, 0x6f4, 0x1f4, + 0x5f4, 0x3f4, 0x7f4, 0x00c, 0x40c, 0x20c, 0x60c, 0x10c, 0x50c, 0x30c, + 0x70c, 0x08c, 0x48c, 0x28c, 0x68c, 0x18c, 0x58c, 0x38c, 0x78c, 0x04c, + 0x44c, 0x24c, 0x64c, 0x14c, 0x54c, 0x34c, 0x74c, 0x0cc, 0x4cc, 0x2cc, + 0x6cc, 0x1cc, 0x5cc, 0x3cc, 0x7cc, 0x02c, 0x42c, 0x22c, 0x62c, 0x12c, + 0x52c, 0x32c, 0x72c, 0x0ac, 0x4ac, 0x2ac, 0x6ac, 0x1ac, 0x5ac, 0x3ac, + 0x7ac, 0x06c, 0x46c, 0x26c, 0x66c, 0x16c, 0x56c, 0x36c, 0x76c, 0x0ec, + 0x4ec, 0x2ec, 0x6ec, 0x1ec, 0x5ec, 0x3ec, 0x7ec, 0x01c, 0x41c, 0x21c, + 0x61c, 0x11c, 0x51c, 0x31c, 0x71c, 0x09c, 0x49c, 0x29c, 0x69c, 0x19c, + 0x59c, 0x39c, 0x79c, 0x05c, 0x45c, 0x25c, 0x65c, 0x15c, 0x55c, 0x35c, + 0x75c, 0x0dc, 0x4dc, 0x2dc, 0x6dc, 0x1dc, 0x5dc, 0x3dc, 0x7dc, 0x03c, + 0x43c, 0x23c, 0x63c, 0x13c, 0x53c, 0x33c, 0x73c, 0x0bc, 0x4bc, 0x2bc, + 0x6bc, 0x1bc, 0x5bc, 0x3bc, 0x7bc, 0x07c, 0x47c, 0x27c, 0x67c, 0x17c, + 0x57c, 0x37c, 0x77c, 0x0fc, 0x4fc, 0x2fc, 0x6fc, 0x1fc, 0x5fc, 0x3fc, + 0x7fc, 0x002, 0x402, 0x202, 0x602, 0x102, 0x502, 0x302, 0x702, 0x082, + 0x482, 0x282, 0x682, 0x182, 0x582, 0x382, 0x782, 0x042, 0x442, 0x242, + 0x642, 0x142, 0x542, 0x342, 0x742, 0x0c2, 0x4c2, 0x2c2, 0x6c2, 0x1c2, + 0x5c2, 0x3c2, 0x7c2, 0x022, 0x422, 0x222, 0x622, 0x122, 0x522, 0x322, + 0x722, 0x0a2, 0x4a2, 0x2a2, 0x6a2, 0x1a2, 0x5a2, 0x3a2, 0x7a2, 0x062, + 0x462, 0x262, 0x662, 0x162, 0x562, 0x362, 0x762, 0x0e2, 0x4e2, 0x2e2, + 0x6e2, 0x1e2, 0x5e2, 0x3e2, 0x7e2, 0x012, 0x412, 0x212, 0x612, 0x112, + 0x512, 0x312, 0x712, 0x092, 0x492, 0x292, 0x692, 0x192, 0x592, 0x392, + 0x792, 0x052, 0x452, 0x252, 0x652, 0x152, 0x552, 0x352, 0x752, 0x0d2, + 0x4d2, 0x2d2, 0x6d2, 0x1d2, 0x5d2, 0x3d2, 0x7d2, 0x032, 0x432, 0x232, + 0x632, 0x132, 0x532, 0x332, 0x732, 0x0b2, 0x4b2, 0x2b2, 0x6b2, 0x1b2, + 0x5b2, 0x3b2, 0x7b2, 0x072, 0x472, 0x272, 0x672, 0x172, 0x572, 0x372, + 0x772, 0x0f2, 0x4f2, 0x2f2, 0x6f2, 0x1f2, 0x5f2, 0x3f2, 0x7f2, 0x00a, + 0x40a, 0x20a, 0x60a, 0x10a, 0x50a, 0x30a, 0x70a, 0x08a, 0x48a, 0x28a, + 0x68a, 0x18a, 0x58a, 0x38a, 0x78a, 0x04a, 0x44a, 0x24a, 0x64a, 0x14a, + 0x54a, 0x34a, 0x74a, 0x0ca, 0x4ca, 0x2ca, 0x6ca, 0x1ca, 0x5ca, 0x3ca, + 0x7ca, 0x02a, 0x42a, 0x22a, 0x62a, 0x12a, 0x52a, 0x32a, 0x72a, 0x0aa, + 0x4aa, 0x2aa, 0x6aa, 0x1aa, 0x5aa, 0x3aa, 0x7aa, 0x06a, 0x46a, 0x26a, + 0x66a, 0x16a, 0x56a, 0x36a, 0x76a, 0x0ea, 0x4ea, 0x2ea, 0x6ea, 0x1ea, + 0x5ea, 0x3ea, 0x7ea, 0x01a, 0x41a, 0x21a, 0x61a, 0x11a, 0x51a, 0x31a, + 0x71a, 0x09a, 0x49a, 0x29a, 0x69a, 0x19a, 0x59a, 0x39a, 0x79a, 0x5a, + 0x45a, 0x25a, 0x65a, 0x15a, 0x55a, 0x35a, 0x75a, 0x0da, 0x4da, 0x2da, + 0x6da, 0x1da, 0x5da, 0x3da, 0x7da, 0x03a, 0x43a, 0x23a, 0x63a, 0x13a, + 0x53a, 0x33a, 0x73a, 0x0ba, 0x4ba, 0x2ba, 0x6ba, 0x1ba, 0x5ba, 0x3ba, + 0x7ba, 0x07a, 0x47a, 0x27a, 0x67a, 0x17a, 0x57a, 0x37a, 0x77a, 0x0fa, + 0x4fa, 0x2fa, 0x6fa, 0x1fa, 0x5fa, 0x3fa, 0x7fa, 0x006, 0x406, 0x206, + 0x606, 0x106, 0x506, 0x306, 0x706, 0x086, 0x486, 0x286, 0x686, 0x186, + 0x586, 0x386, 0x786, 0x046, 0x446, 0x246, 0x646, 0x146, 0x546, 0x346, + 0x746, 0x0c6, 0x4c6, 0x2c6, 0x6c6, 0x1c6, 0x5c6, 0x3c6, 0x7c6, 0x026, + 0x426, 0x226, 0x626, 0x126, 0x526, 0x326, 0x726, 0x0a6, 0x4a6, 0x2a6, + 0x6a6, 0x1a6, 0x5a6, 0x3a6, 0x7a6, 0x066, 0x466, 0x266, 0x666, 0x166, + 0x566, 0x366, 0x766, 0x0e6, 0x4e6, 0x2e6, 0x6e6, 0x1e6, 0x5e6, 0x3e6, + 0x7e6, 0x016, 0x416, 0x216, 0x616, 0x116, 0x516, 0x316, 0x716, 0x096, + 0x496, 0x296, 0x696, 0x196, 0x596, 0x396, 0x796, 0x056, 0x456, 0x256, + 0x656, 0x156, 0x556, 0x356, 0x756, 0x0d6, 0x4d6, 0x2d6, 0x6d6, 0x1d6, + 0x5d6, 0x3d6, 0x7d6, 0x036, 0x436, 0x236, 0x636, 0x136, 0x536, 0x336, + 0x736, 0x0b6, 0x4b6, 0x2b6, 0x6b6, 0x1b6, 0x5b6, 0x3b6, 0x7b6, 0x076, + 0x476, 0x276, 0x676, 0x176, 0x576, 0x376, 0x776, 0x0f6, 0x4f6, 0x2f6, + 0x6f6, 0x1f6, 0x5f6, 0x3f6, 0x7f6, 0x00e, 0x40e, 0x20e, 0x60e, 0x10e, + 0x50e, 0x30e, 0x70e, 0x08e, 0x48e, 0x28e, 0x68e, 0x18e, 0x58e, 0x38e, + 0x78e, 0x04e, 0x44e, 0x24e, 0x64e, 0x14e, 0x54e, 0x34e, 0x74e, 0x0ce, + 0x4ce, 0x2ce, 0x6ce, 0x1ce, 0x5ce, 0x3ce, 0x7ce, 0x02e, 0x42e, 0x22e, + 0x62e, 0x12e, 0x52e, 0x32e, 0x72e, 0x0ae, 0x4ae, 0x2ae, 0x6ae, 0x1ae, + 0x5ae, 0x3ae, 0x7ae, 0x06e, 0x46e, 0x26e, 0x66e, 0x16e, 0x56e, 0x36e, + 0x76e, 0x0ee, 0x4ee, 0x2ee, 0x6ee, 0x1ee, 0x5ee, 0x3ee, 0x7ee, 0x01e, + 0x41e, 0x21e, 0x61e, 0x11e, 0x51e, 0x31e, 0x71e, 0x09e, 0x49e, 0x29e, + 0x69e, 0x19e, 0x59e, 0x39e, 0x79e, 0x05e, 0x45e, 0x25e, 0x65e, 0x15e, + 0x55e, 0x35e, 0x75e, 0x0de, 0x4de, 0x2de, 0x6de, 0x1de, 0x5de, 0x3de, + 0x7de, 0x03e, 0x43e, 0x23e, 0x63e, 0x13e, 0x53e, 0x33e, 0x73e, 0x0be, + 0x4be, 0x2be, 0x6be, 0x1be, 0x5be, 0x3be, 0x7be, 0x07e, 0x47e, 0x27e, + 0x67e, 0x17e, 0x57e, 0x37e, 0x77e, 0x0fe, 0x4fe, 0x2fe, 0x6fe, 0x1fe, + 0x5fe, 0x3fe, 0x7fe, 0x001 +}; +#endif + +/** + @brief Double Precision Floating-point Twiddle factors Table Generation +*/ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_16) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par +
for (i = 0; i < N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(double)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(double)N);
+  } 
+ @par + where N = 16, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_16[32] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, //-0.38268, 0.92388' + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, //-0.70711, 0.70711' + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, //-0.92388, 0.38268' + 0xbff0000000000000, 0x0000000000000000, // -1, 0' + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, //-0.92388,-0.38268' + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, //-0.70711,-0.70711' + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, //-0.38268,-0.92388' + 0x0000000000000000, 0xbff0000000000000, // 0, -1' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268,-0.92388' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711,-0.70711' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388,-0.38268' +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_32) + +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par +
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/N);
+  } 
+ @par + where N = 32, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_32[64] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, //-0.19509, 0.98079' + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, //-0.38268, 0.92388' + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, //-0.55557, 0.83147' + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, //-0.70711, 0.70711' + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, //-0.83147, 0.55557' + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, //-0.92388, 0.38268' + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, //-0.98079, 0.19509' + 0xbff0000000000000, 0x0000000000000000, // -1, 0' + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, //-0.98079,-0.19509' + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, //-0.92388,-0.38268' + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, //-0.83147,-0.55557' + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, //-0.70711,-0.70711' + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, //-0.55557,-0.83147' + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, //-0.38268,-0.92388' + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, //-0.19509,-0.98079' + 0x0000000000000000, 0xbff0000000000000, // 0, -1' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509,-0.98079' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268,-0.92388' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557,-0.83147' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711,-0.70711' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147,-0.55557' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388,-0.38268' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079,-0.19509' +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_64) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par +
for(i = 0; i < N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 64, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_64[128] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518' + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, //-0.098017, 0.99518' + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079' + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694' + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388' + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192' + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147' + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301' + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711' + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439' + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557' + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714' + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268' + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028' + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509' + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017' + 0xbff0000000000000, 0x0000000000000000, // -1, 0' + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518,-0.098017' + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509' + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028' + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268' + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714' + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557' + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439' + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711' + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301' + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147' + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192' + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388' + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694' + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079' + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, //-0.098017, -0.99518' + 0x0000000000000000, 0xbff0000000000000, // 0, -1' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017' + }; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_128) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par +
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 128, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_128[256] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518' + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988' + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, //-0.049068, 0.9988' + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, //-0.098017, 0.99518' + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918' + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079' + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003' + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694' + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154' + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388' + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399' + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192' + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773' + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147' + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321' + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301' + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095' + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711' + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156' + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439' + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957' + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557' + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141' + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714' + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756' + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268' + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689' + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028' + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298' + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509' + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673' + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017' + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068' + 0xbff0000000000000, 0x0000000000000000, // -1, 0' + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988,-0.049068' + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518,-0.098017' + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673' + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509' + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298' + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028' + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689' + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268' + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756' + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714' + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141' + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557' + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957' + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439' + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156' + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711' + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095' + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301' + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321' + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147' + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773' + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192' + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399' + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388' + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154' + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694' + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003' + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079' + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918' + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, //-0.098017, -0.99518' + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, //-0.049068, -0.9988' + 0x0000000000000000, 0xbff0000000000000, // 0, -1' + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518' + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017' + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068' +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_256) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par +
for(i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 256, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_256[512] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0xbf992155f7a3667e, 0x3feffd886084cd0d, //-0.024541, 0.9997 + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, //-0.049068, 0.9988 + 0xbfb2d52092ce19f6, 0x3fefe9cdad01883a, //-0.073565, 0.99729 + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, //-0.098017, 0.99518 + 0xbfbf564e56a9730e, 0x3fefc26470e19fd3, // -0.12241, 0.99248 + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918 + 0xbfc5e214448b3fc6, 0x3fef8764fa714ba9, // -0.17096, 0.98528 + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079 + 0xbfcc0b826a7e4f63, 0x3fef38f3ac64e589, // -0.2191, 0.9757 + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003 + 0xbfd111d262b1f677, 0x3feed740e7684963, // -0.26671, 0.96378 + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694 + 0xbfd4135c94176602, 0x3fee6288ec48e112, // -0.31368, 0.94953 + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154 + 0xbfd7088530fa459e, 0x3feddb13b6ccc23d, // -0.3599, 0.93299 + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388 + 0xbfd9ef7943a8ed8a, 0x3fed4134d14dc93a, // -0.40524, 0.91421 + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399 + 0xbfdcc66e9931c45d, 0x3fec954b213411f5, // -0.44961, 0.89322 + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192 + 0xbfdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // -0.4929, 0.87009 + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773 + 0xbfe11eb3541b4b22, 0x3feb090a58150200, // -0.535, 0.84485 + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147 + 0xbfe26d054cdd12df, 0x3fea29a7a0462782, // -0.57581, 0.81758 + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321 + 0xbfe3affa292050b9, 0x3fe93a22499263fc, // -0.61523, 0.78835 + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301 + 0xbfe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // -0.65317, 0.75721 + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095 + 0xbfe610b7551d2cde, 0x3fe72d0837efff97, // -0.68954, 0.72425 + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711 + 0xbfe72d0837efff97, 0x3fe610b7551d2cde, // -0.72425, 0.68954 + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156 + 0xbfe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // -0.75721, 0.65317 + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439 + 0xbfe93a22499263fc, 0x3fe3affa292050b9, // -0.78835, 0.61523 + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957 + 0xbfea29a7a0462782, 0x3fe26d054cdd12df, // -0.81758, 0.57581 + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557 + 0xbfeb090a58150200, 0x3fe11eb3541b4b22, // -0.84485, 0.535 + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141 + 0xbfebd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // -0.87009, 0.4929 + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714 + 0xbfec954b213411f5, 0x3fdcc66e9931c45d, // -0.89322, 0.44961 + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756 + 0xbfed4134d14dc93a, 0x3fd9ef7943a8ed8a, // -0.91421, 0.40524 + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268 + 0xbfeddb13b6ccc23d, 0x3fd7088530fa459e, // -0.93299, 0.3599 + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689 + 0xbfee6288ec48e112, 0x3fd4135c94176602, // -0.94953, 0.31368 + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028 + 0xbfeed740e7684963, 0x3fd111d262b1f677, // -0.96378, 0.26671 + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298 + 0xbfef38f3ac64e589, 0x3fcc0b826a7e4f63, // -0.9757, 0.2191 + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509 + 0xbfef8764fa714ba9, 0x3fc5e214448b3fc6, // -0.98528, 0.17096 + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673 + 0xbfefc26470e19fd3, 0x3fbf564e56a9730e, // -0.99248, 0.12241 + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017 + 0xbfefe9cdad01883a, 0x3fb2d52092ce19f6, // -0.99729, 0.073565 + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068 + 0xbfeffd886084cd0d, 0x3f992155f7a3667e, // -0.9997, 0.024541 + 0xbff0000000000000, 0x0000000000000000, // -1, 0 + 0xbfeffd886084cd0d, 0xbf992155f7a3667e, // -0.9997,-0.024541 + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988,-0.049068 + 0xbfefe9cdad01883a, 0xbfb2d52092ce19f6, // -0.99729,-0.073565 + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518,-0.098017 + 0xbfefc26470e19fd3, 0xbfbf564e56a9730e, // -0.99248, -0.12241 + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673 + 0xbfef8764fa714ba9, 0xbfc5e214448b3fc6, // -0.98528, -0.17096 + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509 + 0xbfef38f3ac64e589, 0xbfcc0b826a7e4f63, // -0.9757, -0.2191 + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298 + 0xbfeed740e7684963, 0xbfd111d262b1f677, // -0.96378, -0.26671 + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028 + 0xbfee6288ec48e112, 0xbfd4135c94176602, // -0.94953, -0.31368 + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689 + 0xbfeddb13b6ccc23d, 0xbfd7088530fa459e, // -0.93299, -0.3599 + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268 + 0xbfed4134d14dc93a, 0xbfd9ef7943a8ed8a, // -0.91421, -0.40524 + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756 + 0xbfec954b213411f5, 0xbfdcc66e9931c45d, // -0.89322, -0.44961 + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714 + 0xbfebd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // -0.87009, -0.4929 + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141 + 0xbfeb090a58150200, 0xbfe11eb3541b4b22, // -0.84485, -0.535 + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557 + 0xbfea29a7a0462782, 0xbfe26d054cdd12df, // -0.81758, -0.57581 + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957 + 0xbfe93a22499263fc, 0xbfe3affa292050b9, // -0.78835, -0.61523 + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439 + 0xbfe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // -0.75721, -0.65317 + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156 + 0xbfe72d0837efff97, 0xbfe610b7551d2cde, // -0.72425, -0.68954 + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711 + 0xbfe610b7551d2cde, 0xbfe72d0837efff97, // -0.68954, -0.72425 + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095 + 0xbfe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // -0.65317, -0.75721 + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301 + 0xbfe3affa292050b9, 0xbfe93a22499263fc, // -0.61523, -0.78835 + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321 + 0xbfe26d054cdd12df, 0xbfea29a7a0462782, // -0.57581, -0.81758 + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147 + 0xbfe11eb3541b4b22, 0xbfeb090a58150200, // -0.535, -0.84485 + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773 + 0xbfdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // -0.4929, -0.87009 + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192 + 0xbfdcc66e9931c45d, 0xbfec954b213411f5, // -0.44961, -0.89322 + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399 + 0xbfd9ef7943a8ed8a, 0xbfed4134d14dc93a, // -0.40524, -0.91421 + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388 + 0xbfd7088530fa459e, 0xbfeddb13b6ccc23d, // -0.3599, -0.93299 + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154 + 0xbfd4135c94176602, 0xbfee6288ec48e112, // -0.31368, -0.94953 + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694 + 0xbfd111d262b1f677, 0xbfeed740e7684963, // -0.26671, -0.96378 + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003 + 0xbfcc0b826a7e4f63, 0xbfef38f3ac64e589, // -0.2191, -0.9757 + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079 + 0xbfc5e214448b3fc6, 0xbfef8764fa714ba9, // -0.17096, -0.98528 + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918 + 0xbfbf564e56a9730e, 0xbfefc26470e19fd3, // -0.12241, -0.99248 + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, //-0.098017, -0.99518 + 0xbfb2d52092ce19f6, 0xbfefe9cdad01883a, //-0.073565, -0.99729 + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, //-0.049068, -0.9988 + 0xbf992155f7a3667e, 0xbfeffd886084cd0d, //-0.024541, -0.9997 + 0x0000000000000000, 0xbff0000000000000, // 0, -1 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729,-0.073565 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997,-0.024541 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_512) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par +
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 512, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_512[1024] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0xbf8921d1fcdec784, 0x3fefff62169b92db, //-0.012272, 0.99992 + 0xbf992155f7a3667e, 0x3feffd886084cd0d, //-0.024541, 0.9997 + 0xbfa2d865759455cd, 0x3feffa72effef75d, //-0.036807, 0.99932 + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, //-0.049068, 0.9988 + 0xbfaf656e79f820e0, 0x3feff095658e71ad, //-0.061321, 0.99812 + 0xbfb2d52092ce19f6, 0x3fefe9cdad01883a, //-0.073565, 0.99729 + 0xbfb5f6d00a9aa419, 0x3fefe1cafcbd5b09, //-0.085797, 0.99631 + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, //-0.098017, 0.99518 + 0xbfbc3785c79ec2d5, 0x3fefce15fd6da67b, // -0.11022, 0.99391 + 0xbfbf564e56a9730e, 0x3fefc26470e19fd3, // -0.12241, 0.99248 + 0xbfc139f0cedaf576, 0x3fefb5797195d741, // -0.13458, 0.9909 + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918 + 0xbfc45576b1293e5a, 0x3fef97f924c9099b, // -0.15886, 0.9873 + 0xbfc5e214448b3fc6, 0x3fef8764fa714ba9, // -0.17096, 0.98528 + 0xbfc76dd9de50bf31, 0x3fef7599a3a12077, // -0.18304, 0.98311 + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079 + 0xbfca82a025b00451, 0x3fef4e603b0b2f2d, // -0.20711, 0.97832 + 0xbfcc0b826a7e4f63, 0x3fef38f3ac64e589, // -0.2191, 0.9757 + 0xbfcd934fe5454311, 0x3fef2252f7763ada, // -0.23106, 0.97294 + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003 + 0xbfd04fb80e37fdae, 0x3feef178a3e473c2, // -0.25487, 0.96698 + 0xbfd111d262b1f677, 0x3feed740e7684963, // -0.26671, 0.96378 + 0xbfd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // -0.27852, 0.96043 + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694 + 0xbfd35410c2e18152, 0x3fee817bab4cd10d, // -0.30201, 0.95331 + 0xbfd4135c94176602, 0x3fee6288ec48e112, // -0.31368, 0.94953 + 0xbfd4d1e24278e76a, 0x3fee426a4b2bc17e, // -0.32531, 0.94561 + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154 + 0xbfd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // -0.34842, 0.93734 + 0xbfd7088530fa459e, 0x3feddb13b6ccc23d, // -0.3599, 0.93299 + 0xbfd7c3a9311dcce7, 0x3fedb6526238a09b, // -0.37132, 0.92851 + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388 + 0xbfd9372a63bc93d7, 0x3fed696173c9e68b, // -0.39399, 0.91911 + 0xbfd9ef7943a8ed8a, 0x3fed4134d14dc93a, // -0.40524, 0.91421 + 0xbfdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // -0.41643, 0.90917 + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399 + 0xbfdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // -0.43862, 0.89867 + 0xbfdcc66e9931c45d, 0x3fec954b213411f5, // -0.44961, 0.89322 + 0xbfdd79775b86e389, 0x3fec678b3488739b, // -0.46054, 0.88764 + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192 + 0xbfdedc1952ef78d5, 0x3fec08c426725549, // -0.48218, 0.87607 + 0xbfdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // -0.4929, 0.87009 + 0xbfe01cfc874c3eb7, 0x3feba5aa673590d2, // -0.50354, 0.86397 + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773 + 0xbfe0c9704d5d898f, 0x3feb3e4d3ef55712, // -0.52459, 0.85136 + 0xbfe11eb3541b4b22, 0x3feb090a58150200, // -0.535, 0.84485 + 0xbfe1734d63dedb49, 0x3fead2bc9e21d511, // -0.54532, 0.83822 + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147 + 0xbfe21a799933eb58, 0x3fea63091b02fae2, // -0.56573, 0.82459 + 0xbfe26d054cdd12df, 0x3fea29a7a0462782, // -0.57581, 0.81758 + 0xbfe2bedb25faf3ea, 0x3fe9ef43ef29af94, // -0.5858, 0.81046 + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321 + 0xbfe36058b10659f3, 0x3fe9777ef4c7d742, // -0.60551, 0.79584 + 0xbfe3affa292050b9, 0x3fe93a22499263fc, // -0.61523, 0.78835 + 0xbfe3fed9534556d4, 0x3fe8fbcca3ef940d, // -0.62486, 0.78074 + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301 + 0xbfe49a449b9b0938, 0x3fe87c400fba2ebf, // -0.64383, 0.76517 + 0xbfe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // -0.65317, 0.75721 + 0xbfe5328292a35596, 0x3fe7f8ece3571771, // -0.66242, 0.74914 + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095 + 0xbfe5c77bbe65018c, 0x3fe771e75f037261, // -0.6806, 0.73265 + 0xbfe610b7551d2cde, 0x3fe72d0837efff97, // -0.68954, 0.72425 + 0xbfe6591925f0783e, 0x3fe6e74454eaa8ae, // -0.69838, 0.71573 + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711 + 0xbfe6e74454eaa8ae, 0x3fe6591925f0783e, // -0.71573, 0.69838 + 0xbfe72d0837efff97, 0x3fe610b7551d2cde, // -0.72425, 0.68954 + 0xbfe771e75f037261, 0x3fe5c77bbe65018c, // -0.73265, 0.6806 + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156 + 0xbfe7f8ece3571771, 0x3fe5328292a35596, // -0.74914, 0.66242 + 0xbfe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // -0.75721, 0.65317 + 0xbfe87c400fba2ebf, 0x3fe49a449b9b0938, // -0.76517, 0.64383 + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439 + 0xbfe8fbcca3ef940d, 0x3fe3fed9534556d4, // -0.78074, 0.62486 + 0xbfe93a22499263fc, 0x3fe3affa292050b9, // -0.78835, 0.61523 + 0xbfe9777ef4c7d742, 0x3fe36058b10659f3, // -0.79584, 0.60551 + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957 + 0xbfe9ef43ef29af94, 0x3fe2bedb25faf3ea, // -0.81046, 0.5858 + 0xbfea29a7a0462782, 0x3fe26d054cdd12df, // -0.81758, 0.57581 + 0xbfea63091b02fae2, 0x3fe21a799933eb58, // -0.82459, 0.56573 + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557 + 0xbfead2bc9e21d511, 0x3fe1734d63dedb49, // -0.83822, 0.54532 + 0xbfeb090a58150200, 0x3fe11eb3541b4b22, // -0.84485, 0.535 + 0xbfeb3e4d3ef55712, 0x3fe0c9704d5d898f, // -0.85136, 0.52459 + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141 + 0xbfeba5aa673590d2, 0x3fe01cfc874c3eb7, // -0.86397, 0.50354 + 0xbfebd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // -0.87009, 0.4929 + 0xbfec08c426725549, 0x3fdedc1952ef78d5, // -0.87607, 0.48218 + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714 + 0xbfec678b3488739b, 0x3fdd79775b86e389, // -0.88764, 0.46054 + 0xbfec954b213411f5, 0x3fdcc66e9931c45d, // -0.89322, 0.44961 + 0xbfecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // -0.89867, 0.43862 + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756 + 0xbfed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // -0.90917, 0.41643 + 0xbfed4134d14dc93a, 0x3fd9ef7943a8ed8a, // -0.91421, 0.40524 + 0xbfed696173c9e68b, 0x3fd9372a63bc93d7, // -0.91911, 0.39399 + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268 + 0xbfedb6526238a09b, 0x3fd7c3a9311dcce7, // -0.92851, 0.37132 + 0xbfeddb13b6ccc23d, 0x3fd7088530fa459e, // -0.93299, 0.3599 + 0xbfedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // -0.93734, 0.34842 + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689 + 0xbfee426a4b2bc17e, 0x3fd4d1e24278e76a, // -0.94561, 0.32531 + 0xbfee6288ec48e112, 0x3fd4135c94176602, // -0.94953, 0.31368 + 0xbfee817bab4cd10d, 0x3fd35410c2e18152, // -0.95331, 0.30201 + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028 + 0xbfeebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // -0.96043, 0.27852 + 0xbfeed740e7684963, 0x3fd111d262b1f677, // -0.96378, 0.26671 + 0xbfeef178a3e473c2, 0x3fd04fb80e37fdae, // -0.96698, 0.25487 + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298 + 0xbfef2252f7763ada, 0x3fcd934fe5454311, // -0.97294, 0.23106 + 0xbfef38f3ac64e589, 0x3fcc0b826a7e4f63, // -0.9757, 0.2191 + 0xbfef4e603b0b2f2d, 0x3fca82a025b00451, // -0.97832, 0.20711 + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509 + 0xbfef7599a3a12077, 0x3fc76dd9de50bf31, // -0.98311, 0.18304 + 0xbfef8764fa714ba9, 0x3fc5e214448b3fc6, // -0.98528, 0.17096 + 0xbfef97f924c9099b, 0x3fc45576b1293e5a, // -0.9873, 0.15886 + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673 + 0xbfefb5797195d741, 0x3fc139f0cedaf576, // -0.9909, 0.13458 + 0xbfefc26470e19fd3, 0x3fbf564e56a9730e, // -0.99248, 0.12241 + 0xbfefce15fd6da67b, 0x3fbc3785c79ec2d5, // -0.99391, 0.11022 + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017 + 0xbfefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // -0.99631, 0.085797 + 0xbfefe9cdad01883a, 0x3fb2d52092ce19f6, // -0.99729, 0.073565 + 0xbfeff095658e71ad, 0x3faf656e79f820e0, // -0.99812, 0.061321 + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068 + 0xbfeffa72effef75d, 0x3fa2d865759455cd, // -0.99932, 0.036807 + 0xbfeffd886084cd0d, 0x3f992155f7a3667e, // -0.9997, 0.024541 + 0xbfefff62169b92db, 0x3f8921d1fcdec784, // -0.99992, 0.012272 + 0xbff0000000000000, 0x0000000000000000, // -1, 0 + 0xbfefff62169b92db, 0xbf8921d1fcdec784, // -0.99992,-0.012272 + 0xbfeffd886084cd0d, 0xbf992155f7a3667e, // -0.9997,-0.024541 + 0xbfeffa72effef75d, 0xbfa2d865759455cd, // -0.99932,-0.036807 + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988,-0.049068 + 0xbfeff095658e71ad, 0xbfaf656e79f820e0, // -0.99812,-0.061321 + 0xbfefe9cdad01883a, 0xbfb2d52092ce19f6, // -0.99729,-0.073565 + 0xbfefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // -0.99631,-0.085797 + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518,-0.098017 + 0xbfefce15fd6da67b, 0xbfbc3785c79ec2d5, // -0.99391, -0.11022 + 0xbfefc26470e19fd3, 0xbfbf564e56a9730e, // -0.99248, -0.12241 + 0xbfefb5797195d741, 0xbfc139f0cedaf576, // -0.9909, -0.13458 + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673 + 0xbfef97f924c9099b, 0xbfc45576b1293e5a, // -0.9873, -0.15886 + 0xbfef8764fa714ba9, 0xbfc5e214448b3fc6, // -0.98528, -0.17096 + 0xbfef7599a3a12077, 0xbfc76dd9de50bf31, // -0.98311, -0.18304 + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509 + 0xbfef4e603b0b2f2d, 0xbfca82a025b00451, // -0.97832, -0.20711 + 0xbfef38f3ac64e589, 0xbfcc0b826a7e4f63, // -0.9757, -0.2191 + 0xbfef2252f7763ada, 0xbfcd934fe5454311, // -0.97294, -0.23106 + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298 + 0xbfeef178a3e473c2, 0xbfd04fb80e37fdae, // -0.96698, -0.25487 + 0xbfeed740e7684963, 0xbfd111d262b1f677, // -0.96378, -0.26671 + 0xbfeebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // -0.96043, -0.27852 + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028 + 0xbfee817bab4cd10d, 0xbfd35410c2e18152, // -0.95331, -0.30201 + 0xbfee6288ec48e112, 0xbfd4135c94176602, // -0.94953, -0.31368 + 0xbfee426a4b2bc17e, 0xbfd4d1e24278e76a, // -0.94561, -0.32531 + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689 + 0xbfedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // -0.93734, -0.34842 + 0xbfeddb13b6ccc23d, 0xbfd7088530fa459e, // -0.93299, -0.3599 + 0xbfedb6526238a09b, 0xbfd7c3a9311dcce7, // -0.92851, -0.37132 + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268 + 0xbfed696173c9e68b, 0xbfd9372a63bc93d7, // -0.91911, -0.39399 + 0xbfed4134d14dc93a, 0xbfd9ef7943a8ed8a, // -0.91421, -0.40524 + 0xbfed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // -0.90917, -0.41643 + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756 + 0xbfecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // -0.89867, -0.43862 + 0xbfec954b213411f5, 0xbfdcc66e9931c45d, // -0.89322, -0.44961 + 0xbfec678b3488739b, 0xbfdd79775b86e389, // -0.88764, -0.46054 + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714 + 0xbfec08c426725549, 0xbfdedc1952ef78d5, // -0.87607, -0.48218 + 0xbfebd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // -0.87009, -0.4929 + 0xbfeba5aa673590d2, 0xbfe01cfc874c3eb7, // -0.86397, -0.50354 + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141 + 0xbfeb3e4d3ef55712, 0xbfe0c9704d5d898f, // -0.85136, -0.52459 + 0xbfeb090a58150200, 0xbfe11eb3541b4b22, // -0.84485, -0.535 + 0xbfead2bc9e21d511, 0xbfe1734d63dedb49, // -0.83822, -0.54532 + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557 + 0xbfea63091b02fae2, 0xbfe21a799933eb58, // -0.82459, -0.56573 + 0xbfea29a7a0462782, 0xbfe26d054cdd12df, // -0.81758, -0.57581 + 0xbfe9ef43ef29af94, 0xbfe2bedb25faf3ea, // -0.81046, -0.5858 + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957 + 0xbfe9777ef4c7d742, 0xbfe36058b10659f3, // -0.79584, -0.60551 + 0xbfe93a22499263fc, 0xbfe3affa292050b9, // -0.78835, -0.61523 + 0xbfe8fbcca3ef940d, 0xbfe3fed9534556d4, // -0.78074, -0.62486 + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439 + 0xbfe87c400fba2ebf, 0xbfe49a449b9b0938, // -0.76517, -0.64383 + 0xbfe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // -0.75721, -0.65317 + 0xbfe7f8ece3571771, 0xbfe5328292a35596, // -0.74914, -0.66242 + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156 + 0xbfe771e75f037261, 0xbfe5c77bbe65018c, // -0.73265, -0.6806 + 0xbfe72d0837efff97, 0xbfe610b7551d2cde, // -0.72425, -0.68954 + 0xbfe6e74454eaa8ae, 0xbfe6591925f0783e, // -0.71573, -0.69838 + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711 + 0xbfe6591925f0783e, 0xbfe6e74454eaa8ae, // -0.69838, -0.71573 + 0xbfe610b7551d2cde, 0xbfe72d0837efff97, // -0.68954, -0.72425 + 0xbfe5c77bbe65018c, 0xbfe771e75f037261, // -0.6806, -0.73265 + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095 + 0xbfe5328292a35596, 0xbfe7f8ece3571771, // -0.66242, -0.74914 + 0xbfe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // -0.65317, -0.75721 + 0xbfe49a449b9b0938, 0xbfe87c400fba2ebf, // -0.64383, -0.76517 + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301 + 0xbfe3fed9534556d4, 0xbfe8fbcca3ef940d, // -0.62486, -0.78074 + 0xbfe3affa292050b9, 0xbfe93a22499263fc, // -0.61523, -0.78835 + 0xbfe36058b10659f3, 0xbfe9777ef4c7d742, // -0.60551, -0.79584 + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321 + 0xbfe2bedb25faf3ea, 0xbfe9ef43ef29af94, // -0.5858, -0.81046 + 0xbfe26d054cdd12df, 0xbfea29a7a0462782, // -0.57581, -0.81758 + 0xbfe21a799933eb58, 0xbfea63091b02fae2, // -0.56573, -0.82459 + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147 + 0xbfe1734d63dedb49, 0xbfead2bc9e21d511, // -0.54532, -0.83822 + 0xbfe11eb3541b4b22, 0xbfeb090a58150200, // -0.535, -0.84485 + 0xbfe0c9704d5d898f, 0xbfeb3e4d3ef55712, // -0.52459, -0.85136 + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773 + 0xbfe01cfc874c3eb7, 0xbfeba5aa673590d2, // -0.50354, -0.86397 + 0xbfdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // -0.4929, -0.87009 + 0xbfdedc1952ef78d5, 0xbfec08c426725549, // -0.48218, -0.87607 + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192 + 0xbfdd79775b86e389, 0xbfec678b3488739b, // -0.46054, -0.88764 + 0xbfdcc66e9931c45d, 0xbfec954b213411f5, // -0.44961, -0.89322 + 0xbfdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // -0.43862, -0.89867 + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399 + 0xbfdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // -0.41643, -0.90917 + 0xbfd9ef7943a8ed8a, 0xbfed4134d14dc93a, // -0.40524, -0.91421 + 0xbfd9372a63bc93d7, 0xbfed696173c9e68b, // -0.39399, -0.91911 + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388 + 0xbfd7c3a9311dcce7, 0xbfedb6526238a09b, // -0.37132, -0.92851 + 0xbfd7088530fa459e, 0xbfeddb13b6ccc23d, // -0.3599, -0.93299 + 0xbfd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // -0.34842, -0.93734 + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154 + 0xbfd4d1e24278e76a, 0xbfee426a4b2bc17e, // -0.32531, -0.94561 + 0xbfd4135c94176602, 0xbfee6288ec48e112, // -0.31368, -0.94953 + 0xbfd35410c2e18152, 0xbfee817bab4cd10d, // -0.30201, -0.95331 + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694 + 0xbfd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // -0.27852, -0.96043 + 0xbfd111d262b1f677, 0xbfeed740e7684963, // -0.26671, -0.96378 + 0xbfd04fb80e37fdae, 0xbfeef178a3e473c2, // -0.25487, -0.96698 + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003 + 0xbfcd934fe5454311, 0xbfef2252f7763ada, // -0.23106, -0.97294 + 0xbfcc0b826a7e4f63, 0xbfef38f3ac64e589, // -0.2191, -0.9757 + 0xbfca82a025b00451, 0xbfef4e603b0b2f2d, // -0.20711, -0.97832 + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079 + 0xbfc76dd9de50bf31, 0xbfef7599a3a12077, // -0.18304, -0.98311 + 0xbfc5e214448b3fc6, 0xbfef8764fa714ba9, // -0.17096, -0.98528 + 0xbfc45576b1293e5a, 0xbfef97f924c9099b, // -0.15886, -0.9873 + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918 + 0xbfc139f0cedaf576, 0xbfefb5797195d741, // -0.13458, -0.9909 + 0xbfbf564e56a9730e, 0xbfefc26470e19fd3, // -0.12241, -0.99248 + 0xbfbc3785c79ec2d5, 0xbfefce15fd6da67b, // -0.11022, -0.99391 + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, //-0.098017, -0.99518 + 0xbfb5f6d00a9aa419, 0xbfefe1cafcbd5b09, //-0.085797, -0.99631 + 0xbfb2d52092ce19f6, 0xbfefe9cdad01883a, //-0.073565, -0.99729 + 0xbfaf656e79f820e0, 0xbfeff095658e71ad, //-0.061321, -0.99812 + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, //-0.049068, -0.9988 + 0xbfa2d865759455cd, 0xbfeffa72effef75d, //-0.036807, -0.99932 + 0xbf992155f7a3667e, 0xbfeffd886084cd0d, //-0.024541, -0.9997 + 0xbf8921d1fcdec784, 0xbfefff62169b92db, //-0.012272, -0.99992 + 0x0000000000000000, 0xbff0000000000000, // 0, -1 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631,-0.085797 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729,-0.073565 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812,-0.061321 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932,-0.036807 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997,-0.024541 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992,-0.012272 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_1024) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par +
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 1024, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_1024[2048] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, // 0.0061359, 0.99998 + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0xbf7921f0fe670071, 0x3fefffd8858e8a92, //-0.0061359, 0.99998 + 0xbf8921d1fcdec784, 0x3fefff62169b92db, // -0.012272, 0.99992 + 0xbf92d936bbe30efd, 0x3feffe9cb44b51a1, // -0.018407, 0.99983 + 0xbf992155f7a3667e, 0x3feffd886084cd0d, // -0.024541, 0.9997 + 0xbf9f693731d1cf01, 0x3feffc251df1d3f8, // -0.030675, 0.99953 + 0xbfa2d865759455cd, 0x3feffa72effef75d, // -0.036807, 0.99932 + 0xbfa5fc00d290cd43, 0x3feff871dadb81df, // -0.042938, 0.99908 + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, // -0.049068, 0.9988 + 0xbfac428d12c0d7e3, 0x3feff3830f8d575c, // -0.055195, 0.99848 + 0xbfaf656e79f820e0, 0x3feff095658e71ad, // -0.061321, 0.99812 + 0xbfb1440134d709b2, 0x3fefed58ecb673c4, // -0.067444, 0.99772 + 0xbfb2d52092ce19f6, 0x3fefe9cdad01883a, // -0.073565, 0.99729 + 0xbfb4661179272096, 0x3fefe5f3af2e3940, // -0.079682, 0.99682 + 0xbfb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // -0.085797, 0.99631 + 0xbfb787586a5d5b21, 0x3fefdd539ff1f456, // -0.091909, 0.99577 + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, // -0.098017, 0.99518 + 0xbfbaa7b724495c04, 0x3fefd37914220b84, // -0.10412, 0.99456 + 0xbfbc3785c79ec2d5, 0x3fefce15fd6da67b, // -0.11022, 0.99391 + 0xbfbdc70ecbae9fc8, 0x3fefc8646cfeb721, // -0.11632, 0.99321 + 0xbfbf564e56a9730e, 0x3fefc26470e19fd3, // -0.12241, 0.99248 + 0xbfc072a047ba831d, 0x3fefbc1617e44186, // -0.1285, 0.99171 + 0xbfc139f0cedaf576, 0x3fefb5797195d741, // -0.13458, 0.9909 + 0xbfc20116d4ec7bce, 0x3fefae8e8e46cfbb, // -0.14066, 0.99006 + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918 + 0xbfc38edbb0cd8d14, 0x3fef9fce55adb2c8, // -0.1528, 0.98826 + 0xbfc45576b1293e5a, 0x3fef97f924c9099b, // -0.15886, 0.9873 + 0xbfc51bdf8597c5f2, 0x3fef8fd5ffae41db, // -0.16491, 0.98631 + 0xbfc5e214448b3fc6, 0x3fef8764fa714ba9, // -0.17096, 0.98528 + 0xbfc6a81304f64ab2, 0x3fef7ea629e63d6e, // -0.177, 0.98421 + 0xbfc76dd9de50bf31, 0x3fef7599a3a12077, // -0.18304, 0.98311 + 0xbfc83366e89c64c5, 0x3fef6c3f7df5bbb7, // -0.18907, 0.98196 + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079 + 0xbfc9bdcbf2dc4366, 0x3fef58a2b1789e84, // -0.2011, 0.97957 + 0xbfca82a025b00451, 0x3fef4e603b0b2f2d, // -0.20711, 0.97832 + 0xbfcb4732ef3d6722, 0x3fef43d085ff92dd, // -0.21311, 0.97703 + 0xbfcc0b826a7e4f63, 0x3fef38f3ac64e589, // -0.2191, 0.9757 + 0xbfcccf8cb312b286, 0x3fef2dc9c9089a9d, // -0.22508, 0.97434 + 0xbfcd934fe5454311, 0x3fef2252f7763ada, // -0.23106, 0.97294 + 0xbfce56ca1e101a1b, 0x3fef168f53f7205d, // -0.23702, 0.9715 + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003 + 0xbfcfdcdc1adfedf8, 0x3feefe220c0b95ec, // -0.24893, 0.96852 + 0xbfd04fb80e37fdae, 0x3feef178a3e473c2, // -0.25487, 0.96698 + 0xbfd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // -0.26079, 0.96539 + 0xbfd111d262b1f677, 0x3feed740e7684963, // -0.26671, 0.96378 + 0xbfd172a0d7765177, 0x3feec9b2d3c3bf84, // -0.27262, 0.96212 + 0xbfd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // -0.27852, 0.96043 + 0xbfd233bbabc3bb72, 0x3feeadb2e8e7a88e, // -0.28441, 0.9587 + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694 + 0xbfd2f422daec0386, 0x3fee9084361df7f3, // -0.29615, 0.95514 + 0xbfd35410c2e18152, 0x3fee817bab4cd10d, // -0.30201, 0.95331 + 0xbfd3b3cefa0414b7, 0x3fee7227db6a9744, // -0.30785, 0.95144 + 0xbfd4135c94176602, 0x3fee6288ec48e112, // -0.31368, 0.94953 + 0xbfd472b8a5571054, 0x3fee529f04729ffc, // -0.3195, 0.94759 + 0xbfd4d1e24278e76a, 0x3fee426a4b2bc17e, // -0.32531, 0.94561 + 0xbfd530d880af3c24, 0x3fee31eae870ce25, // -0.33111, 0.94359 + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154 + 0xbfd5ee27379ea693, 0x3fee100cca2980ac, // -0.34266, 0.93946 + 0xbfd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // -0.34842, 0.93734 + 0xbfd6aa9d7dc77e16, 0x3feded05f7de47da, // -0.35416, 0.93518 + 0xbfd7088530fa459e, 0x3feddb13b6ccc23d, // -0.3599, 0.93299 + 0xbfd766340f2418f6, 0x3fedc8d7cb410260, // -0.36561, 0.93077 + 0xbfd7c3a9311dcce7, 0x3fedb6526238a09b, // -0.37132, 0.92851 + 0xbfd820e3b04eaac4, 0x3feda383a9668988, // -0.37701, 0.92621 + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388 + 0xbfd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // -0.38835, 0.92151 + 0xbfd9372a63bc93d7, 0x3fed696173c9e68b, // -0.39399, 0.91911 + 0xbfd993716141bdfe, 0x3fed556f52e93eb1, // -0.39962, 0.91668 + 0xbfd9ef7943a8ed8a, 0x3fed4134d14dc93a, // -0.40524, 0.91421 + 0xbfda4b4127dea1e4, 0x3fed2cb220e0ef9f, // -0.41084, 0.91171 + 0xbfdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // -0.41643, 0.90917 + 0xbfdb020d6c7f4009, 0x3fed02d4feb2bd92, // -0.422, 0.9066 + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399 + 0xbfdbb7cf2304bd01, 0x3fecd7d9898b32f6, // -0.43309, 0.90135 + 0xbfdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // -0.43862, 0.89867 + 0xbfdc6c7f4997000a, 0x3fecabc169a0b901, // -0.44412, 0.89597 + 0xbfdcc66e9931c45d, 0x3fec954b213411f5, // -0.44961, 0.89322 + 0xbfdd2016e8e9db5b, 0x3fec7e8e52233cf3, // -0.45508, 0.89045 + 0xbfdd79775b86e389, 0x3fec678b3488739b, // -0.46054, 0.88764 + 0xbfddd28f1481cc58, 0x3fec5042012b6907, // -0.46598, 0.8848 + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192 + 0xbfde83e0eaf85113, 0x3fec20de3fa971b0, // -0.4768, 0.87901 + 0xbfdedc1952ef78d5, 0x3fec08c426725549, // -0.48218, 0.87607 + 0xbfdf3405963fd068, 0x3febf064e15377dd, // -0.48755, 0.87309 + 0xbfdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // -0.4929, 0.87009 + 0xbfdfe2f64be7120f, 0x3febbed7c49380ea, // -0.49823, 0.86705 + 0xbfe01cfc874c3eb7, 0x3feba5aa673590d2, // -0.50354, 0.86397 + 0xbfe0485626ae221a, 0x3feb8c38d27504e9, // -0.50883, 0.86087 + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773 + 0xbfe09e907417c5e1, 0x3feb5889fe921405, // -0.51936, 0.85456 + 0xbfe0c9704d5d898f, 0x3feb3e4d3ef55712, // -0.52459, 0.85136 + 0xbfe0f426bb2a8e7d, 0x3feb23cd470013b4, // -0.5298, 0.84812 + 0xbfe11eb3541b4b22, 0x3feb090a58150200, // -0.535, 0.84485 + 0xbfe14915af336ceb, 0x3feaee04b43c1474, // -0.54017, 0.84155 + 0xbfe1734d63dedb49, 0x3fead2bc9e21d511, // -0.54532, 0.83822 + 0xbfe19d5a09f2b9b8, 0x3feab7325916c0d4, // -0.55046, 0.83486 + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147 + 0xbfe1f0f08bbc861b, 0x3fea7f58529fe69d, // -0.56066, 0.82805 + 0xbfe21a799933eb58, 0x3fea63091b02fae2, // -0.56573, 0.82459 + 0xbfe243d5fb98ac1f, 0x3fea4678c8119ac8, // -0.57078, 0.8211 + 0xbfe26d054cdd12df, 0x3fea29a7a0462782, // -0.57581, 0.81758 + 0xbfe2960727629ca8, 0x3fea0c95eabaf937, // -0.58081, 0.81404 + 0xbfe2bedb25faf3ea, 0x3fe9ef43ef29af94, // -0.5858, 0.81046 + 0xbfe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // -0.59076, 0.80685 + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321 + 0xbfe338400d0c8e57, 0x3fe995cf2ed80d22, // -0.60062, 0.79954 + 0xbfe36058b10659f3, 0x3fe9777ef4c7d742, // -0.60551, 0.79584 + 0xbfe3884185dfeb22, 0x3fe958efe48e6dd7, // -0.61038, 0.79211 + 0xbfe3affa292050b9, 0x3fe93a22499263fc, // -0.61523, 0.78835 + 0xbfe3d78238c58343, 0x3fe91b166fd49da2, // -0.62006, 0.78456 + 0xbfe3fed9534556d4, 0x3fe8fbcca3ef940d, // -0.62486, 0.78074 + 0xbfe425ff178e6bb1, 0x3fe8dc45331698cc, // -0.62964, 0.77689 + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301 + 0xbfe473b51b987347, 0x3fe89c7e9a4dd4ab, // -0.63912, 0.7691 + 0xbfe49a449b9b0938, 0x3fe87c400fba2ebf, // -0.64383, 0.76517 + 0xbfe4c0a145ec0004, 0x3fe85bc51ae958cc, // -0.64851, 0.7612 + 0xbfe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // -0.65317, 0.75721 + 0xbfe50cc09f59a09b, 0x3fe81a1b33b57acc, // -0.65781, 0.75319 + 0xbfe5328292a35596, 0x3fe7f8ece3571771, // -0.66242, 0.74914 + 0xbfe5581038975137, 0x3fe7d7836cc33db2, // -0.667, 0.74506 + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095 + 0xbfe5a28d2a5d7250, 0x3fe79400574f55e4, // -0.67609, 0.73682 + 0xbfe5c77bbe65018c, 0x3fe771e75f037261, // -0.6806, 0.73265 + 0xbfe5ec3495837074, 0x3fe74f948da8d28d, // -0.68508, 0.72846 + 0xbfe610b7551d2cde, 0x3fe72d0837efff97, // -0.68954, 0.72425 + 0xbfe63503a31c1be8, 0x3fe70a42b3176d7a, // -0.69397, 0.72 + 0xbfe6591925f0783e, 0x3fe6e74454eaa8ae, // -0.69838, 0.71573 + 0xbfe67cf78491af10, 0x3fe6c40d73c18275, // -0.70275, 0.71143 + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711 + 0xbfe6c40d73c18275, 0x3fe67cf78491af10, // -0.71143, 0.70275 + 0xbfe6e74454eaa8ae, 0x3fe6591925f0783e, // -0.71573, 0.69838 + 0xbfe70a42b3176d7a, 0x3fe63503a31c1be8, // -0.72, 0.69397 + 0xbfe72d0837efff97, 0x3fe610b7551d2cde, // -0.72425, 0.68954 + 0xbfe74f948da8d28d, 0x3fe5ec3495837074, // -0.72846, 0.68508 + 0xbfe771e75f037261, 0x3fe5c77bbe65018c, // -0.73265, 0.6806 + 0xbfe79400574f55e4, 0x3fe5a28d2a5d7250, // -0.73682, 0.67609 + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156 + 0xbfe7d7836cc33db2, 0x3fe5581038975137, // -0.74506, 0.667 + 0xbfe7f8ece3571771, 0x3fe5328292a35596, // -0.74914, 0.66242 + 0xbfe81a1b33b57acc, 0x3fe50cc09f59a09b, // -0.75319, 0.65781 + 0xbfe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // -0.75721, 0.65317 + 0xbfe85bc51ae958cc, 0x3fe4c0a145ec0004, // -0.7612, 0.64851 + 0xbfe87c400fba2ebf, 0x3fe49a449b9b0938, // -0.76517, 0.64383 + 0xbfe89c7e9a4dd4ab, 0x3fe473b51b987347, // -0.7691, 0.63912 + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439 + 0xbfe8dc45331698cc, 0x3fe425ff178e6bb1, // -0.77689, 0.62964 + 0xbfe8fbcca3ef940d, 0x3fe3fed9534556d4, // -0.78074, 0.62486 + 0xbfe91b166fd49da2, 0x3fe3d78238c58343, // -0.78456, 0.62006 + 0xbfe93a22499263fc, 0x3fe3affa292050b9, // -0.78835, 0.61523 + 0xbfe958efe48e6dd7, 0x3fe3884185dfeb22, // -0.79211, 0.61038 + 0xbfe9777ef4c7d742, 0x3fe36058b10659f3, // -0.79584, 0.60551 + 0xbfe995cf2ed80d22, 0x3fe338400d0c8e57, // -0.79954, 0.60062 + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957 + 0xbfe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // -0.80685, 0.59076 + 0xbfe9ef43ef29af94, 0x3fe2bedb25faf3ea, // -0.81046, 0.5858 + 0xbfea0c95eabaf937, 0x3fe2960727629ca8, // -0.81404, 0.58081 + 0xbfea29a7a0462782, 0x3fe26d054cdd12df, // -0.81758, 0.57581 + 0xbfea4678c8119ac8, 0x3fe243d5fb98ac1f, // -0.8211, 0.57078 + 0xbfea63091b02fae2, 0x3fe21a799933eb58, // -0.82459, 0.56573 + 0xbfea7f58529fe69d, 0x3fe1f0f08bbc861b, // -0.82805, 0.56066 + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557 + 0xbfeab7325916c0d4, 0x3fe19d5a09f2b9b8, // -0.83486, 0.55046 + 0xbfead2bc9e21d511, 0x3fe1734d63dedb49, // -0.83822, 0.54532 + 0xbfeaee04b43c1474, 0x3fe14915af336ceb, // -0.84155, 0.54017 + 0xbfeb090a58150200, 0x3fe11eb3541b4b22, // -0.84485, 0.535 + 0xbfeb23cd470013b4, 0x3fe0f426bb2a8e7d, // -0.84812, 0.5298 + 0xbfeb3e4d3ef55712, 0x3fe0c9704d5d898f, // -0.85136, 0.52459 + 0xbfeb5889fe921405, 0x3fe09e907417c5e1, // -0.85456, 0.51936 + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141 + 0xbfeb8c38d27504e9, 0x3fe0485626ae221a, // -0.86087, 0.50883 + 0xbfeba5aa673590d2, 0x3fe01cfc874c3eb7, // -0.86397, 0.50354 + 0xbfebbed7c49380ea, 0x3fdfe2f64be7120f, // -0.86705, 0.49823 + 0xbfebd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // -0.87009, 0.4929 + 0xbfebf064e15377dd, 0x3fdf3405963fd068, // -0.87309, 0.48755 + 0xbfec08c426725549, 0x3fdedc1952ef78d5, // -0.87607, 0.48218 + 0xbfec20de3fa971b0, 0x3fde83e0eaf85113, // -0.87901, 0.4768 + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714 + 0xbfec5042012b6907, 0x3fddd28f1481cc58, // -0.8848, 0.46598 + 0xbfec678b3488739b, 0x3fdd79775b86e389, // -0.88764, 0.46054 + 0xbfec7e8e52233cf3, 0x3fdd2016e8e9db5b, // -0.89045, 0.45508 + 0xbfec954b213411f5, 0x3fdcc66e9931c45d, // -0.89322, 0.44961 + 0xbfecabc169a0b901, 0x3fdc6c7f4997000a, // -0.89597, 0.44412 + 0xbfecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // -0.89867, 0.43862 + 0xbfecd7d9898b32f6, 0x3fdbb7cf2304bd01, // -0.90135, 0.43309 + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756 + 0xbfed02d4feb2bd92, 0x3fdb020d6c7f4009, // -0.9066, 0.422 + 0xbfed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // -0.90917, 0.41643 + 0xbfed2cb220e0ef9f, 0x3fda4b4127dea1e4, // -0.91171, 0.41084 + 0xbfed4134d14dc93a, 0x3fd9ef7943a8ed8a, // -0.91421, 0.40524 + 0xbfed556f52e93eb1, 0x3fd993716141bdfe, // -0.91668, 0.39962 + 0xbfed696173c9e68b, 0x3fd9372a63bc93d7, // -0.91911, 0.39399 + 0xbfed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // -0.92151, 0.38835 + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268 + 0xbfeda383a9668988, 0x3fd820e3b04eaac4, // -0.92621, 0.37701 + 0xbfedb6526238a09b, 0x3fd7c3a9311dcce7, // -0.92851, 0.37132 + 0xbfedc8d7cb410260, 0x3fd766340f2418f6, // -0.93077, 0.36561 + 0xbfeddb13b6ccc23d, 0x3fd7088530fa459e, // -0.93299, 0.3599 + 0xbfeded05f7de47da, 0x3fd6aa9d7dc77e16, // -0.93518, 0.35416 + 0xbfedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // -0.93734, 0.34842 + 0xbfee100cca2980ac, 0x3fd5ee27379ea693, // -0.93946, 0.34266 + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689 + 0xbfee31eae870ce25, 0x3fd530d880af3c24, // -0.94359, 0.33111 + 0xbfee426a4b2bc17e, 0x3fd4d1e24278e76a, // -0.94561, 0.32531 + 0xbfee529f04729ffc, 0x3fd472b8a5571054, // -0.94759, 0.3195 + 0xbfee6288ec48e112, 0x3fd4135c94176602, // -0.94953, 0.31368 + 0xbfee7227db6a9744, 0x3fd3b3cefa0414b7, // -0.95144, 0.30785 + 0xbfee817bab4cd10d, 0x3fd35410c2e18152, // -0.95331, 0.30201 + 0xbfee9084361df7f3, 0x3fd2f422daec0386, // -0.95514, 0.29615 + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028 + 0xbfeeadb2e8e7a88e, 0x3fd233bbabc3bb72, // -0.9587, 0.28441 + 0xbfeebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // -0.96043, 0.27852 + 0xbfeec9b2d3c3bf84, 0x3fd172a0d7765177, // -0.96212, 0.27262 + 0xbfeed740e7684963, 0x3fd111d262b1f677, // -0.96378, 0.26671 + 0xbfeee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // -0.96539, 0.26079 + 0xbfeef178a3e473c2, 0x3fd04fb80e37fdae, // -0.96698, 0.25487 + 0xbfeefe220c0b95ec, 0x3fcfdcdc1adfedf8, // -0.96852, 0.24893 + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298 + 0xbfef168f53f7205d, 0x3fce56ca1e101a1b, // -0.9715, 0.23702 + 0xbfef2252f7763ada, 0x3fcd934fe5454311, // -0.97294, 0.23106 + 0xbfef2dc9c9089a9d, 0x3fcccf8cb312b286, // -0.97434, 0.22508 + 0xbfef38f3ac64e589, 0x3fcc0b826a7e4f63, // -0.9757, 0.2191 + 0xbfef43d085ff92dd, 0x3fcb4732ef3d6722, // -0.97703, 0.21311 + 0xbfef4e603b0b2f2d, 0x3fca82a025b00451, // -0.97832, 0.20711 + 0xbfef58a2b1789e84, 0x3fc9bdcbf2dc4366, // -0.97957, 0.2011 + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509 + 0xbfef6c3f7df5bbb7, 0x3fc83366e89c64c5, // -0.98196, 0.18907 + 0xbfef7599a3a12077, 0x3fc76dd9de50bf31, // -0.98311, 0.18304 + 0xbfef7ea629e63d6e, 0x3fc6a81304f64ab2, // -0.98421, 0.177 + 0xbfef8764fa714ba9, 0x3fc5e214448b3fc6, // -0.98528, 0.17096 + 0xbfef8fd5ffae41db, 0x3fc51bdf8597c5f2, // -0.98631, 0.16491 + 0xbfef97f924c9099b, 0x3fc45576b1293e5a, // -0.9873, 0.15886 + 0xbfef9fce55adb2c8, 0x3fc38edbb0cd8d14, // -0.98826, 0.1528 + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673 + 0xbfefae8e8e46cfbb, 0x3fc20116d4ec7bce, // -0.99006, 0.14066 + 0xbfefb5797195d741, 0x3fc139f0cedaf576, // -0.9909, 0.13458 + 0xbfefbc1617e44186, 0x3fc072a047ba831d, // -0.99171, 0.1285 + 0xbfefc26470e19fd3, 0x3fbf564e56a9730e, // -0.99248, 0.12241 + 0xbfefc8646cfeb721, 0x3fbdc70ecbae9fc8, // -0.99321, 0.11632 + 0xbfefce15fd6da67b, 0x3fbc3785c79ec2d5, // -0.99391, 0.11022 + 0xbfefd37914220b84, 0x3fbaa7b724495c04, // -0.99456, 0.10412 + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017 + 0xbfefdd539ff1f456, 0x3fb787586a5d5b21, // -0.99577, 0.091909 + 0xbfefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // -0.99631, 0.085797 + 0xbfefe5f3af2e3940, 0x3fb4661179272096, // -0.99682, 0.079682 + 0xbfefe9cdad01883a, 0x3fb2d52092ce19f6, // -0.99729, 0.073565 + 0xbfefed58ecb673c4, 0x3fb1440134d709b2, // -0.99772, 0.067444 + 0xbfeff095658e71ad, 0x3faf656e79f820e0, // -0.99812, 0.061321 + 0xbfeff3830f8d575c, 0x3fac428d12c0d7e3, // -0.99848, 0.055195 + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068 + 0xbfeff871dadb81df, 0x3fa5fc00d290cd43, // -0.99908, 0.042938 + 0xbfeffa72effef75d, 0x3fa2d865759455cd, // -0.99932, 0.036807 + 0xbfeffc251df1d3f8, 0x3f9f693731d1cf01, // -0.99953, 0.030675 + 0xbfeffd886084cd0d, 0x3f992155f7a3667e, // -0.9997, 0.024541 + 0xbfeffe9cb44b51a1, 0x3f92d936bbe30efd, // -0.99983, 0.018407 + 0xbfefff62169b92db, 0x3f8921d1fcdec784, // -0.99992, 0.012272 + 0xbfefffd8858e8a92, 0x3f7921f0fe670071, // -0.99998, 0.0061359 + 0xbff0000000000000, 0x0000000000000000, // -1, 0 + 0xbfefffd8858e8a92, 0xbf7921f0fe670071, // -0.99998,-0.0061359 + 0xbfefff62169b92db, 0xbf8921d1fcdec784, // -0.99992, -0.012272 + 0xbfeffe9cb44b51a1, 0xbf92d936bbe30efd, // -0.99983, -0.018407 + 0xbfeffd886084cd0d, 0xbf992155f7a3667e, // -0.9997, -0.024541 + 0xbfeffc251df1d3f8, 0xbf9f693731d1cf01, // -0.99953, -0.030675 + 0xbfeffa72effef75d, 0xbfa2d865759455cd, // -0.99932, -0.036807 + 0xbfeff871dadb81df, 0xbfa5fc00d290cd43, // -0.99908, -0.042938 + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988, -0.049068 + 0xbfeff3830f8d575c, 0xbfac428d12c0d7e3, // -0.99848, -0.055195 + 0xbfeff095658e71ad, 0xbfaf656e79f820e0, // -0.99812, -0.061321 + 0xbfefed58ecb673c4, 0xbfb1440134d709b2, // -0.99772, -0.067444 + 0xbfefe9cdad01883a, 0xbfb2d52092ce19f6, // -0.99729, -0.073565 + 0xbfefe5f3af2e3940, 0xbfb4661179272096, // -0.99682, -0.079682 + 0xbfefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // -0.99631, -0.085797 + 0xbfefdd539ff1f456, 0xbfb787586a5d5b21, // -0.99577, -0.091909 + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518, -0.098017 + 0xbfefd37914220b84, 0xbfbaa7b724495c04, // -0.99456, -0.10412 + 0xbfefce15fd6da67b, 0xbfbc3785c79ec2d5, // -0.99391, -0.11022 + 0xbfefc8646cfeb721, 0xbfbdc70ecbae9fc8, // -0.99321, -0.11632 + 0xbfefc26470e19fd3, 0xbfbf564e56a9730e, // -0.99248, -0.12241 + 0xbfefbc1617e44186, 0xbfc072a047ba831d, // -0.99171, -0.1285 + 0xbfefb5797195d741, 0xbfc139f0cedaf576, // -0.9909, -0.13458 + 0xbfefae8e8e46cfbb, 0xbfc20116d4ec7bce, // -0.99006, -0.14066 + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673 + 0xbfef9fce55adb2c8, 0xbfc38edbb0cd8d14, // -0.98826, -0.1528 + 0xbfef97f924c9099b, 0xbfc45576b1293e5a, // -0.9873, -0.15886 + 0xbfef8fd5ffae41db, 0xbfc51bdf8597c5f2, // -0.98631, -0.16491 + 0xbfef8764fa714ba9, 0xbfc5e214448b3fc6, // -0.98528, -0.17096 + 0xbfef7ea629e63d6e, 0xbfc6a81304f64ab2, // -0.98421, -0.177 + 0xbfef7599a3a12077, 0xbfc76dd9de50bf31, // -0.98311, -0.18304 + 0xbfef6c3f7df5bbb7, 0xbfc83366e89c64c5, // -0.98196, -0.18907 + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509 + 0xbfef58a2b1789e84, 0xbfc9bdcbf2dc4366, // -0.97957, -0.2011 + 0xbfef4e603b0b2f2d, 0xbfca82a025b00451, // -0.97832, -0.20711 + 0xbfef43d085ff92dd, 0xbfcb4732ef3d6722, // -0.97703, -0.21311 + 0xbfef38f3ac64e589, 0xbfcc0b826a7e4f63, // -0.9757, -0.2191 + 0xbfef2dc9c9089a9d, 0xbfcccf8cb312b286, // -0.97434, -0.22508 + 0xbfef2252f7763ada, 0xbfcd934fe5454311, // -0.97294, -0.23106 + 0xbfef168f53f7205d, 0xbfce56ca1e101a1b, // -0.9715, -0.23702 + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298 + 0xbfeefe220c0b95ec, 0xbfcfdcdc1adfedf8, // -0.96852, -0.24893 + 0xbfeef178a3e473c2, 0xbfd04fb80e37fdae, // -0.96698, -0.25487 + 0xbfeee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // -0.96539, -0.26079 + 0xbfeed740e7684963, 0xbfd111d262b1f677, // -0.96378, -0.26671 + 0xbfeec9b2d3c3bf84, 0xbfd172a0d7765177, // -0.96212, -0.27262 + 0xbfeebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // -0.96043, -0.27852 + 0xbfeeadb2e8e7a88e, 0xbfd233bbabc3bb72, // -0.9587, -0.28441 + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028 + 0xbfee9084361df7f3, 0xbfd2f422daec0386, // -0.95514, -0.29615 + 0xbfee817bab4cd10d, 0xbfd35410c2e18152, // -0.95331, -0.30201 + 0xbfee7227db6a9744, 0xbfd3b3cefa0414b7, // -0.95144, -0.30785 + 0xbfee6288ec48e112, 0xbfd4135c94176602, // -0.94953, -0.31368 + 0xbfee529f04729ffc, 0xbfd472b8a5571054, // -0.94759, -0.3195 + 0xbfee426a4b2bc17e, 0xbfd4d1e24278e76a, // -0.94561, -0.32531 + 0xbfee31eae870ce25, 0xbfd530d880af3c24, // -0.94359, -0.33111 + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689 + 0xbfee100cca2980ac, 0xbfd5ee27379ea693, // -0.93946, -0.34266 + 0xbfedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // -0.93734, -0.34842 + 0xbfeded05f7de47da, 0xbfd6aa9d7dc77e16, // -0.93518, -0.35416 + 0xbfeddb13b6ccc23d, 0xbfd7088530fa459e, // -0.93299, -0.3599 + 0xbfedc8d7cb410260, 0xbfd766340f2418f6, // -0.93077, -0.36561 + 0xbfedb6526238a09b, 0xbfd7c3a9311dcce7, // -0.92851, -0.37132 + 0xbfeda383a9668988, 0xbfd820e3b04eaac4, // -0.92621, -0.37701 + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268 + 0xbfed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // -0.92151, -0.38835 + 0xbfed696173c9e68b, 0xbfd9372a63bc93d7, // -0.91911, -0.39399 + 0xbfed556f52e93eb1, 0xbfd993716141bdfe, // -0.91668, -0.39962 + 0xbfed4134d14dc93a, 0xbfd9ef7943a8ed8a, // -0.91421, -0.40524 + 0xbfed2cb220e0ef9f, 0xbfda4b4127dea1e4, // -0.91171, -0.41084 + 0xbfed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // -0.90917, -0.41643 + 0xbfed02d4feb2bd92, 0xbfdb020d6c7f4009, // -0.9066, -0.422 + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756 + 0xbfecd7d9898b32f6, 0xbfdbb7cf2304bd01, // -0.90135, -0.43309 + 0xbfecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // -0.89867, -0.43862 + 0xbfecabc169a0b901, 0xbfdc6c7f4997000a, // -0.89597, -0.44412 + 0xbfec954b213411f5, 0xbfdcc66e9931c45d, // -0.89322, -0.44961 + 0xbfec7e8e52233cf3, 0xbfdd2016e8e9db5b, // -0.89045, -0.45508 + 0xbfec678b3488739b, 0xbfdd79775b86e389, // -0.88764, -0.46054 + 0xbfec5042012b6907, 0xbfddd28f1481cc58, // -0.8848, -0.46598 + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714 + 0xbfec20de3fa971b0, 0xbfde83e0eaf85113, // -0.87901, -0.4768 + 0xbfec08c426725549, 0xbfdedc1952ef78d5, // -0.87607, -0.48218 + 0xbfebf064e15377dd, 0xbfdf3405963fd068, // -0.87309, -0.48755 + 0xbfebd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // -0.87009, -0.4929 + 0xbfebbed7c49380ea, 0xbfdfe2f64be7120f, // -0.86705, -0.49823 + 0xbfeba5aa673590d2, 0xbfe01cfc874c3eb7, // -0.86397, -0.50354 + 0xbfeb8c38d27504e9, 0xbfe0485626ae221a, // -0.86087, -0.50883 + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141 + 0xbfeb5889fe921405, 0xbfe09e907417c5e1, // -0.85456, -0.51936 + 0xbfeb3e4d3ef55712, 0xbfe0c9704d5d898f, // -0.85136, -0.52459 + 0xbfeb23cd470013b4, 0xbfe0f426bb2a8e7d, // -0.84812, -0.5298 + 0xbfeb090a58150200, 0xbfe11eb3541b4b22, // -0.84485, -0.535 + 0xbfeaee04b43c1474, 0xbfe14915af336ceb, // -0.84155, -0.54017 + 0xbfead2bc9e21d511, 0xbfe1734d63dedb49, // -0.83822, -0.54532 + 0xbfeab7325916c0d4, 0xbfe19d5a09f2b9b8, // -0.83486, -0.55046 + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557 + 0xbfea7f58529fe69d, 0xbfe1f0f08bbc861b, // -0.82805, -0.56066 + 0xbfea63091b02fae2, 0xbfe21a799933eb58, // -0.82459, -0.56573 + 0xbfea4678c8119ac8, 0xbfe243d5fb98ac1f, // -0.8211, -0.57078 + 0xbfea29a7a0462782, 0xbfe26d054cdd12df, // -0.81758, -0.57581 + 0xbfea0c95eabaf937, 0xbfe2960727629ca8, // -0.81404, -0.58081 + 0xbfe9ef43ef29af94, 0xbfe2bedb25faf3ea, // -0.81046, -0.5858 + 0xbfe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // -0.80685, -0.59076 + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957 + 0xbfe995cf2ed80d22, 0xbfe338400d0c8e57, // -0.79954, -0.60062 + 0xbfe9777ef4c7d742, 0xbfe36058b10659f3, // -0.79584, -0.60551 + 0xbfe958efe48e6dd7, 0xbfe3884185dfeb22, // -0.79211, -0.61038 + 0xbfe93a22499263fc, 0xbfe3affa292050b9, // -0.78835, -0.61523 + 0xbfe91b166fd49da2, 0xbfe3d78238c58343, // -0.78456, -0.62006 + 0xbfe8fbcca3ef940d, 0xbfe3fed9534556d4, // -0.78074, -0.62486 + 0xbfe8dc45331698cc, 0xbfe425ff178e6bb1, // -0.77689, -0.62964 + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439 + 0xbfe89c7e9a4dd4ab, 0xbfe473b51b987347, // -0.7691, -0.63912 + 0xbfe87c400fba2ebf, 0xbfe49a449b9b0938, // -0.76517, -0.64383 + 0xbfe85bc51ae958cc, 0xbfe4c0a145ec0004, // -0.7612, -0.64851 + 0xbfe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // -0.75721, -0.65317 + 0xbfe81a1b33b57acc, 0xbfe50cc09f59a09b, // -0.75319, -0.65781 + 0xbfe7f8ece3571771, 0xbfe5328292a35596, // -0.74914, -0.66242 + 0xbfe7d7836cc33db2, 0xbfe5581038975137, // -0.74506, -0.667 + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156 + 0xbfe79400574f55e4, 0xbfe5a28d2a5d7250, // -0.73682, -0.67609 + 0xbfe771e75f037261, 0xbfe5c77bbe65018c, // -0.73265, -0.6806 + 0xbfe74f948da8d28d, 0xbfe5ec3495837074, // -0.72846, -0.68508 + 0xbfe72d0837efff97, 0xbfe610b7551d2cde, // -0.72425, -0.68954 + 0xbfe70a42b3176d7a, 0xbfe63503a31c1be8, // -0.72, -0.69397 + 0xbfe6e74454eaa8ae, 0xbfe6591925f0783e, // -0.71573, -0.69838 + 0xbfe6c40d73c18275, 0xbfe67cf78491af10, // -0.71143, -0.70275 + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711 + 0xbfe67cf78491af10, 0xbfe6c40d73c18275, // -0.70275, -0.71143 + 0xbfe6591925f0783e, 0xbfe6e74454eaa8ae, // -0.69838, -0.71573 + 0xbfe63503a31c1be8, 0xbfe70a42b3176d7a, // -0.69397, -0.72 + 0xbfe610b7551d2cde, 0xbfe72d0837efff97, // -0.68954, -0.72425 + 0xbfe5ec3495837074, 0xbfe74f948da8d28d, // -0.68508, -0.72846 + 0xbfe5c77bbe65018c, 0xbfe771e75f037261, // -0.6806, -0.73265 + 0xbfe5a28d2a5d7250, 0xbfe79400574f55e4, // -0.67609, -0.73682 + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095 + 0xbfe5581038975137, 0xbfe7d7836cc33db2, // -0.667, -0.74506 + 0xbfe5328292a35596, 0xbfe7f8ece3571771, // -0.66242, -0.74914 + 0xbfe50cc09f59a09b, 0xbfe81a1b33b57acc, // -0.65781, -0.75319 + 0xbfe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // -0.65317, -0.75721 + 0xbfe4c0a145ec0004, 0xbfe85bc51ae958cc, // -0.64851, -0.7612 + 0xbfe49a449b9b0938, 0xbfe87c400fba2ebf, // -0.64383, -0.76517 + 0xbfe473b51b987347, 0xbfe89c7e9a4dd4ab, // -0.63912, -0.7691 + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301 + 0xbfe425ff178e6bb1, 0xbfe8dc45331698cc, // -0.62964, -0.77689 + 0xbfe3fed9534556d4, 0xbfe8fbcca3ef940d, // -0.62486, -0.78074 + 0xbfe3d78238c58343, 0xbfe91b166fd49da2, // -0.62006, -0.78456 + 0xbfe3affa292050b9, 0xbfe93a22499263fc, // -0.61523, -0.78835 + 0xbfe3884185dfeb22, 0xbfe958efe48e6dd7, // -0.61038, -0.79211 + 0xbfe36058b10659f3, 0xbfe9777ef4c7d742, // -0.60551, -0.79584 + 0xbfe338400d0c8e57, 0xbfe995cf2ed80d22, // -0.60062, -0.79954 + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321 + 0xbfe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // -0.59076, -0.80685 + 0xbfe2bedb25faf3ea, 0xbfe9ef43ef29af94, // -0.5858, -0.81046 + 0xbfe2960727629ca8, 0xbfea0c95eabaf937, // -0.58081, -0.81404 + 0xbfe26d054cdd12df, 0xbfea29a7a0462782, // -0.57581, -0.81758 + 0xbfe243d5fb98ac1f, 0xbfea4678c8119ac8, // -0.57078, -0.8211 + 0xbfe21a799933eb58, 0xbfea63091b02fae2, // -0.56573, -0.82459 + 0xbfe1f0f08bbc861b, 0xbfea7f58529fe69d, // -0.56066, -0.82805 + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147 + 0xbfe19d5a09f2b9b8, 0xbfeab7325916c0d4, // -0.55046, -0.83486 + 0xbfe1734d63dedb49, 0xbfead2bc9e21d511, // -0.54532, -0.83822 + 0xbfe14915af336ceb, 0xbfeaee04b43c1474, // -0.54017, -0.84155 + 0xbfe11eb3541b4b22, 0xbfeb090a58150200, // -0.535, -0.84485 + 0xbfe0f426bb2a8e7d, 0xbfeb23cd470013b4, // -0.5298, -0.84812 + 0xbfe0c9704d5d898f, 0xbfeb3e4d3ef55712, // -0.52459, -0.85136 + 0xbfe09e907417c5e1, 0xbfeb5889fe921405, // -0.51936, -0.85456 + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773 + 0xbfe0485626ae221a, 0xbfeb8c38d27504e9, // -0.50883, -0.86087 + 0xbfe01cfc874c3eb7, 0xbfeba5aa673590d2, // -0.50354, -0.86397 + 0xbfdfe2f64be7120f, 0xbfebbed7c49380ea, // -0.49823, -0.86705 + 0xbfdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // -0.4929, -0.87009 + 0xbfdf3405963fd068, 0xbfebf064e15377dd, // -0.48755, -0.87309 + 0xbfdedc1952ef78d5, 0xbfec08c426725549, // -0.48218, -0.87607 + 0xbfde83e0eaf85113, 0xbfec20de3fa971b0, // -0.4768, -0.87901 + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192 + 0xbfddd28f1481cc58, 0xbfec5042012b6907, // -0.46598, -0.8848 + 0xbfdd79775b86e389, 0xbfec678b3488739b, // -0.46054, -0.88764 + 0xbfdd2016e8e9db5b, 0xbfec7e8e52233cf3, // -0.45508, -0.89045 + 0xbfdcc66e9931c45d, 0xbfec954b213411f5, // -0.44961, -0.89322 + 0xbfdc6c7f4997000a, 0xbfecabc169a0b901, // -0.44412, -0.89597 + 0xbfdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // -0.43862, -0.89867 + 0xbfdbb7cf2304bd01, 0xbfecd7d9898b32f6, // -0.43309, -0.90135 + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399 + 0xbfdb020d6c7f4009, 0xbfed02d4feb2bd92, // -0.422, -0.9066 + 0xbfdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // -0.41643, -0.90917 + 0xbfda4b4127dea1e4, 0xbfed2cb220e0ef9f, // -0.41084, -0.91171 + 0xbfd9ef7943a8ed8a, 0xbfed4134d14dc93a, // -0.40524, -0.91421 + 0xbfd993716141bdfe, 0xbfed556f52e93eb1, // -0.39962, -0.91668 + 0xbfd9372a63bc93d7, 0xbfed696173c9e68b, // -0.39399, -0.91911 + 0xbfd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // -0.38835, -0.92151 + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388 + 0xbfd820e3b04eaac4, 0xbfeda383a9668988, // -0.37701, -0.92621 + 0xbfd7c3a9311dcce7, 0xbfedb6526238a09b, // -0.37132, -0.92851 + 0xbfd766340f2418f6, 0xbfedc8d7cb410260, // -0.36561, -0.93077 + 0xbfd7088530fa459e, 0xbfeddb13b6ccc23d, // -0.3599, -0.93299 + 0xbfd6aa9d7dc77e16, 0xbfeded05f7de47da, // -0.35416, -0.93518 + 0xbfd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // -0.34842, -0.93734 + 0xbfd5ee27379ea693, 0xbfee100cca2980ac, // -0.34266, -0.93946 + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154 + 0xbfd530d880af3c24, 0xbfee31eae870ce25, // -0.33111, -0.94359 + 0xbfd4d1e24278e76a, 0xbfee426a4b2bc17e, // -0.32531, -0.94561 + 0xbfd472b8a5571054, 0xbfee529f04729ffc, // -0.3195, -0.94759 + 0xbfd4135c94176602, 0xbfee6288ec48e112, // -0.31368, -0.94953 + 0xbfd3b3cefa0414b7, 0xbfee7227db6a9744, // -0.30785, -0.95144 + 0xbfd35410c2e18152, 0xbfee817bab4cd10d, // -0.30201, -0.95331 + 0xbfd2f422daec0386, 0xbfee9084361df7f3, // -0.29615, -0.95514 + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694 + 0xbfd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // -0.28441, -0.9587 + 0xbfd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // -0.27852, -0.96043 + 0xbfd172a0d7765177, 0xbfeec9b2d3c3bf84, // -0.27262, -0.96212 + 0xbfd111d262b1f677, 0xbfeed740e7684963, // -0.26671, -0.96378 + 0xbfd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // -0.26079, -0.96539 + 0xbfd04fb80e37fdae, 0xbfeef178a3e473c2, // -0.25487, -0.96698 + 0xbfcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // -0.24893, -0.96852 + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003 + 0xbfce56ca1e101a1b, 0xbfef168f53f7205d, // -0.23702, -0.9715 + 0xbfcd934fe5454311, 0xbfef2252f7763ada, // -0.23106, -0.97294 + 0xbfcccf8cb312b286, 0xbfef2dc9c9089a9d, // -0.22508, -0.97434 + 0xbfcc0b826a7e4f63, 0xbfef38f3ac64e589, // -0.2191, -0.9757 + 0xbfcb4732ef3d6722, 0xbfef43d085ff92dd, // -0.21311, -0.97703 + 0xbfca82a025b00451, 0xbfef4e603b0b2f2d, // -0.20711, -0.97832 + 0xbfc9bdcbf2dc4366, 0xbfef58a2b1789e84, // -0.2011, -0.97957 + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079 + 0xbfc83366e89c64c5, 0xbfef6c3f7df5bbb7, // -0.18907, -0.98196 + 0xbfc76dd9de50bf31, 0xbfef7599a3a12077, // -0.18304, -0.98311 + 0xbfc6a81304f64ab2, 0xbfef7ea629e63d6e, // -0.177, -0.98421 + 0xbfc5e214448b3fc6, 0xbfef8764fa714ba9, // -0.17096, -0.98528 + 0xbfc51bdf8597c5f2, 0xbfef8fd5ffae41db, // -0.16491, -0.98631 + 0xbfc45576b1293e5a, 0xbfef97f924c9099b, // -0.15886, -0.9873 + 0xbfc38edbb0cd8d14, 0xbfef9fce55adb2c8, // -0.1528, -0.98826 + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918 + 0xbfc20116d4ec7bce, 0xbfefae8e8e46cfbb, // -0.14066, -0.99006 + 0xbfc139f0cedaf576, 0xbfefb5797195d741, // -0.13458, -0.9909 + 0xbfc072a047ba831d, 0xbfefbc1617e44186, // -0.1285, -0.99171 + 0xbfbf564e56a9730e, 0xbfefc26470e19fd3, // -0.12241, -0.99248 + 0xbfbdc70ecbae9fc8, 0xbfefc8646cfeb721, // -0.11632, -0.99321 + 0xbfbc3785c79ec2d5, 0xbfefce15fd6da67b, // -0.11022, -0.99391 + 0xbfbaa7b724495c04, 0xbfefd37914220b84, // -0.10412, -0.99456 + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, // -0.098017, -0.99518 + 0xbfb787586a5d5b21, 0xbfefdd539ff1f456, // -0.091909, -0.99577 + 0xbfb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // -0.085797, -0.99631 + 0xbfb4661179272096, 0xbfefe5f3af2e3940, // -0.079682, -0.99682 + 0xbfb2d52092ce19f6, 0xbfefe9cdad01883a, // -0.073565, -0.99729 + 0xbfb1440134d709b2, 0xbfefed58ecb673c4, // -0.067444, -0.99772 + 0xbfaf656e79f820e0, 0xbfeff095658e71ad, // -0.061321, -0.99812 + 0xbfac428d12c0d7e3, 0xbfeff3830f8d575c, // -0.055195, -0.99848 + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, // -0.049068, -0.9988 + 0xbfa5fc00d290cd43, 0xbfeff871dadb81df, // -0.042938, -0.99908 + 0xbfa2d865759455cd, 0xbfeffa72effef75d, // -0.036807, -0.99932 + 0xbf9f693731d1cf01, 0xbfeffc251df1d3f8, // -0.030675, -0.99953 + 0xbf992155f7a3667e, 0xbfeffd886084cd0d, // -0.024541, -0.9997 + 0xbf92d936bbe30efd, 0xbfeffe9cb44b51a1, // -0.018407, -0.99983 + 0xbf8921d1fcdec784, 0xbfefff62169b92db, // -0.012272, -0.99992 + 0xbf7921f0fe670071, 0xbfefffd8858e8a92, //-0.0061359, -0.99998 + 0x0000000000000000, 0xbff0000000000000, // 0, -1 + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, // 0.0061359, -0.99998 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017 + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797 + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565 + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321 + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068 + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807 + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541 + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272 + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_2048) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par +
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 2048, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_2048[4096] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffff621621d02, 0x3f6921f8becca4ba, // 1, 0.003068 + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359 + 0x3fefffa72c978c4f, 0x3f82d96b0e509703, // 0.99996, 0.0092038 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3fefff0943c53bd1, 0x3f8f6a296ab997ca, // 0.99988, 0.015339 + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407 + 0x3feffe1c6870cb77, 0x3f95fd4d21fab226, // 0.99977, 0.021474 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffce09ce2a679, 0x3f9c454f4ce53b1c, // 0.99962, 0.027608 + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675 + 0x3feffb55e425fdae, 0x3fa14685db42c17e, // 0.99943, 0.033741 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feff97c4208c014, 0x3fa46a396ff86179, // 0.9992, 0.039873 + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938 + 0x3feff753bb1b9164, 0x3fa78dbaa5874685, // 0.99894, 0.046003 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff4dc54b1bed3, 0x3faab101bd5f8317, // 0.99864, 0.052132 + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195 + 0x3feff21614e131ed, 0x3fadd406f9808ec8, // 0.9983, 0.058258 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3fefef0102826191, 0x3fb07b614e463064, // 0.99793, 0.064383 + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444 + 0x3fefeb9d2530410f, 0x3fb20c9674ed444c, // 0.99751, 0.070505 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefe7ea85482d60, 0x3fb39d9f12c5a299, // 0.99706, 0.076624 + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682 + 0x3fefe3e92be9d886, 0x3fb52e774a4d4d0a, // 0.99657, 0.08274 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefdf9922f73307, 0x3fb6bf1b3e79b129, // 0.99604, 0.088854 + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909 + 0x3fefdafa7514538c, 0x3fb84f8712c130a0, // 0.99548, 0.094963 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // 0.99488, 0.10107 + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412 + 0x3fefd0d158d86087, 0x3fbb6fa6ec38f64c, // 0.99424, 0.10717 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefcb4703914354, 0x3fbcff533b307dc1, // 0.99356, 0.11327 + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632 + 0x3fefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // 0.99285, 0.11937 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // 0.9921, 0.12545 + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285 + 0x3fefb8d18d66adb7, 0x3fc0d64dbcb26786, // 0.99131, 0.13154 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefb20dc681d54d, 0x3fc19d8940be24e7, // 0.99049, 0.13762 + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066 + 0x3fefaafbcb0cfddc, 0x3fc264994dfd340a, // 0.98962, 0.1437 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fefa39bac7a1791, 0x3fc32b7bf94516a7, // 0.98872, 0.14976 + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528 + 0x3fef9bed7cfbde29, 0x3fc3f22f57db4893, // 0.98778, 0.15583 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef93f14f85ac08, 0x3fc4b8b17f79fa88, // 0.98681, 0.16189 + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491 + 0x3fef8ba737cb4b78, 0x3fc57f008654cbde, // 0.9858, 0.16794 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef830f4a40c60c, 0x3fc6451a831d830d, // 0.98475, 0.17398 + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177 + 0x3fef7a299c1a322a, 0x3fc70afd8d08c4ff, // 0.98366, 0.18002 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // 0.98254, 0.18606 + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907 + 0x3fef677556883cee, 0x3fc8961727c41804, // 0.98138, 0.19208 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef5da6ed43685d, 0x3fc95b49e9b62af9, // 0.98018, 0.1981 + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011 + 0x3fef538b1faf2d07, 0x3fca203e1b1831da, // 0.97895, 0.20411 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef492206bcabb4, 0x3fcae4f1d5f3b9ab, // 0.97768, 0.21011 + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311 + 0x3fef3e6bbc1bbc65, 0x3fcba96334f15dad, // 0.97637, 0.21611 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef33685a3aaef0, 0x3fcc6d90535d74dc, // 0.97503, 0.22209 + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508 + 0x3fef2817fc4609ce, 0x3fcd31774d2cbdee, // 0.97364, 0.22807 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef1c7abe284708, 0x3fcdf5163f01099a, // 0.97223, 0.23404 + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702 + 0x3fef1090bc898f5f, 0x3fceb86b462de348, // 0.97077, 0.24 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3fef045a14cf738c, 0x3fcf7b7480bd3801, // 0.96928, 0.24596 + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893 + 0x3feef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // 0.96775, 0.2519 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feeeb074c50a544, 0x3fd0804e05eb661e, // 0.96619, 0.25783 + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079 + 0x3feeddeb6a078651, 0x3fd0e15b4e1749cd, // 0.96459, 0.26375 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feed0835e999009, 0x3fd1423eefc69378, // 0.96295, 0.26967 + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262 + 0x3feec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // 0.96128, 0.27557 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3feeb4cf515b8811, 0x3fd2038583d727bd, // 0.95957, 0.28146 + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441 + 0x3feea68393e65800, 0x3fd263e6995554ba, // 0.95783, 0.28735 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3fee97ec36016b30, 0x3fd2c41a4e954520, // 0.95605, 0.29322 + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615 + 0x3fee89095bad6025, 0x3fd3241fb638baaf, // 0.95423, 0.29908 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee79db29a5165a, 0x3fd383f5e353b6aa, // 0.95238, 0.30493 + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785 + 0x3fee6a61c55d53a7, 0x3fd3e39be96ec271, // 0.95049, 0.31077 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee5a9d550467d3, 0x3fd44310dc8936f0, // 0.94856, 0.31659 + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195 + 0x3fee4a8dff81ce5e, 0x3fd4a253d11b82f3, // 0.9466, 0.32241 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee3a33ec75ce85, 0x3fd50163dc197047, // 0.9446, 0.32821 + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111 + 0x3fee298f4439197a, 0x3fd5604012f467b4, // 0.94257, 0.334 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee18a02fdc66d9, 0x3fd5bee78b9db3b6, // 0.94051, 0.33978 + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266 + 0x3fee0766d9280f54, 0x3fd61d595c88c203, // 0.9384, 0.34554 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3fedf5e36a9ba59c, 0x3fd67b949cad63ca, // 0.93627, 0.35129 + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416 + 0x3fede4160f6d8d81, 0x3fd6d998638a0cb5, // 0.93409, 0.35703 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fedd1fef38a915a, 0x3fd73763c9261092, // 0.93188, 0.36276 + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561 + 0x3fedbf9e4395759a, 0x3fd794f5e613dfae, // 0.92964, 0.36847 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3fedacf42ce68ab9, 0x3fd7f24dd37341e3, // 0.92736, 0.37416 + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701 + 0x3fed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // 0.92505, 0.37985 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed86c48445a450, 0x3fd8ac4b86d5ed44, // 0.9227, 0.38552 + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835 + 0x3fed733f508c0dff, 0x3fd908ef81ef7bd1, // 0.92032, 0.39117 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed5f7172888a7f, 0x3fd96555b7ab948f, // 0.9179, 0.39681 + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962 + 0x3fed4b5b1b187524, 0x3fd9c17d440df9f2, // 0.91545, 0.40243 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // 0.91296, 0.40804 + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084 + 0x3fed2255c6e5a4e1, 0x3fda790cd3dbf31a, // 0.91044, 0.41364 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3fed0d672f59d2b9, 0x3fdad473125cdc08, // 0.90789, 0.41922 + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422 + 0x3fecf830e8ce467b, 0x3fdb2f971db31972, // 0.9053, 0.42478 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fece2b32799a060, 0x3fdb8a7814fd5693, // 0.90267, 0.43033 + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309 + 0x3fecccee20c2de9f, 0x3fdbe51517ffc0d9, // 0.90002, 0.43586 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fecb6e20a00da99, 0x3fdc3f6d47263129, // 0.89732, 0.44137 + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412 + 0x3feca08f19b9c449, 0x3fdc997fc3865388, // 0.8946, 0.44687 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec89f587029c13, 0x3fdcf34baee1cd21, // 0.89184, 0.45235 + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508 + 0x3fec7315899eaad7, 0x3fdd4cd02ba8609c, // 0.88905, 0.45781 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec5bef59fef85a, 0x3fdda60c5cfa10d8, // 0.88622, 0.46326 + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598 + 0x3fec44833141c004, 0x3fddfeff66a941de, // 0.88336, 0.46869 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec2cd14931e3f1, 0x3fde57a86d3cd824, // 0.88047, 0.4741 + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768 + 0x3fec14d9dc465e58, 0x3fdeb00695f25620, // 0.87755, 0.47949 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3febfc9d25a1b147, 0x3fdf081906bff7fd, // 0.87459, 0.48487 + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755 + 0x3febe41b611154c1, 0x3fdf5fdee656cda3, // 0.8716, 0.49023 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3febcb54cb0d2327, 0x3fdfb7575c24d2de, // 0.86857, 0.49557 + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823 + 0x3febb249a0b6c40d, 0x3fe00740c82b82e0, // 0.86551, 0.50089 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3feb98fa1fd9155e, 0x3fe032ae55edbd95, // 0.86242, 0.50619 + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883 + 0x3feb7f6686e792ea, 0x3fe05df3ec31b8b6, // 0.8593, 0.51147 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb658f14fdbc47, 0x3fe089112032b08c, // 0.85615, 0.51673 + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936 + 0x3feb4b7409de7925, 0x3fe0b405878f85ec, // 0.85296, 0.52198 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // 0.84974, 0.5272 + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298 + 0x3feb16742a4ca2f5, 0x3fe1097248d0a956, // 0.84649, 0.5324 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feafb8fd89f57b6, 0x3fe133e9cfee254e, // 0.84321, 0.53759 + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017 + 0x3feae068f345ecef, 0x3fe15e36e4dbe2bc, // 0.83989, 0.54275 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3feac4ffbd3efac8, 0x3fe188591f3a46e5, // 0.83655, 0.54789 + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046 + 0x3feaa9547a2cb98e, 0x3fe1b250171373be, // 0.83317, 0.55302 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3fea8d676e545ad2, 0x3fe1dc1b64dc4872, // 0.82976, 0.55812 + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066 + 0x3fea7138de9d60f5, 0x3fe205baa17560d6, // 0.82632, 0.5632 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea54c91090f524, 0x3fe22f2d662c13e1, // 0.82285, 0.56826 + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078 + 0x3fea38184a593bc6, 0x3fe258734cbb7110, // 0.81935, 0.5733 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea1b26d2c0a75e, 0x3fe2818bef4d3cba, // 0.81581, 0.57831 + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081 + 0x3fe9fdf4f13149de, 0x3fe2aa76e87aeb58, // 0.81225, 0.58331 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9e082edb42472, 0x3fe2d333d34e9bb7, // 0.80866, 0.58828 + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076 + 0x3fe9c2d110f075c3, 0x3fe2fbc24b441015, // 0.80503, 0.59323 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe9a4dfa42b06b2, 0x3fe32421ec49a620, // 0.80138, 0.59816 + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062 + 0x3fe986aef1457594, 0x3fe34c5252c14de1, // 0.79769, 0.60307 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe9683f42bd7fe1, 0x3fe374531b817f8d, // 0.79398, 0.60795 + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038 + 0x3fe94990e3ac4a6c, 0x3fe39c23e3d63029, // 0.79023, 0.61281 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe92aa41fc5a815, 0x3fe3c3c44981c517, // 0.78646, 0.61765 + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006 + 0x3fe90b7943575efe, 0x3fe3eb33eabe0680, // 0.78265, 0.62246 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe8ec109b486c49, 0x3fe41272663d108c, // 0.77882, 0.62725 + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964 + 0x3fe8cc6a75184655, 0x3fe4397f5b2a4380, // 0.77495, 0.63202 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe8ac871ede1d88, 0x3fe4605a692b32a2, // 0.77106, 0.63676 + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912 + 0x3fe88c66e7481ba1, 0x3fe48703306091fe, // 0.76714, 0.64148 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe86c0a1d9aa195, 0x3fe4ad79516722f0, // 0.76319, 0.64618 + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851 + 0x3fe84b7111af83f9, 0x3fe4d3bc6d589f80, // 0.75921, 0.65085 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe82a9c13f545ff, 0x3fe4f9cc25cca486, // 0.7552, 0.65549 + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781 + 0x3fe8098b756e52fa, 0x3fe51fa81cd99aa6, // 0.75117, 0.66011 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe7e83f87b03686, 0x3fe5454ff5159dfb, // 0.7471, 0.66471 + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667 + 0x3fe7c6b89ce2d333, 0x3fe56ac35197649e, // 0.74301, 0.66928 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe7a4f707bf97d2, 0x3fe59001d5f723df, // 0.73889, 0.67383 + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609 + 0x3fe782fb1b90b35b, 0x3fe5b50b264f7448, // 0.73474, 0.67835 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe760c52c304764, 0x3fe5d9dee73e345c, // 0.73056, 0.68285 + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508 + 0x3fe73e558e079942, 0x3fe5fe7cbde56a0f, // 0.72636, 0.68732 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe71bac960e41bf, 0x3fe622e44fec22ff, // 0.72213, 0.69176 + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397 + 0x3fe6f8ca99c95b75, 0x3fe64715437f535b, // 0.71787, 0.69618 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6d5afef4aafcc, 0x3fe66b0f3f52b386, // 0.71358, 0.70057 + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275 + 0x3fe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // 0.70927, 0.70493 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // 0.70493, 0.70927 + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143 + 0x3fe66b0f3f52b386, 0x3fe6d5afef4aafcc, // 0.70057, 0.71358 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe64715437f535b, 0x3fe6f8ca99c95b75, // 0.69618, 0.71787 + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72 + 0x3fe622e44fec22ff, 0x3fe71bac960e41bf, // 0.69176, 0.72213 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe5fe7cbde56a0f, 0x3fe73e558e079942, // 0.68732, 0.72636 + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846 + 0x3fe5d9dee73e345c, 0x3fe760c52c304764, // 0.68285, 0.73056 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe5b50b264f7448, 0x3fe782fb1b90b35b, // 0.67835, 0.73474 + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682 + 0x3fe59001d5f723df, 0x3fe7a4f707bf97d2, // 0.67383, 0.73889 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe56ac35197649e, 0x3fe7c6b89ce2d333, // 0.66928, 0.74301 + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506 + 0x3fe5454ff5159dfb, 0x3fe7e83f87b03686, // 0.66471, 0.7471 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe51fa81cd99aa6, 0x3fe8098b756e52fa, // 0.66011, 0.75117 + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319 + 0x3fe4f9cc25cca486, 0x3fe82a9c13f545ff, // 0.65549, 0.7552 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe4d3bc6d589f80, 0x3fe84b7111af83f9, // 0.65085, 0.75921 + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612 + 0x3fe4ad79516722f0, 0x3fe86c0a1d9aa195, // 0.64618, 0.76319 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe48703306091fe, 0x3fe88c66e7481ba1, // 0.64148, 0.76714 + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691 + 0x3fe4605a692b32a2, 0x3fe8ac871ede1d88, // 0.63676, 0.77106 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe4397f5b2a4380, 0x3fe8cc6a75184655, // 0.63202, 0.77495 + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689 + 0x3fe41272663d108c, 0x3fe8ec109b486c49, // 0.62725, 0.77882 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe3eb33eabe0680, 0x3fe90b7943575efe, // 0.62246, 0.78265 + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456 + 0x3fe3c3c44981c517, 0x3fe92aa41fc5a815, // 0.61765, 0.78646 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe39c23e3d63029, 0x3fe94990e3ac4a6c, // 0.61281, 0.79023 + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211 + 0x3fe374531b817f8d, 0x3fe9683f42bd7fe1, // 0.60795, 0.79398 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe34c5252c14de1, 0x3fe986aef1457594, // 0.60307, 0.79769 + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954 + 0x3fe32421ec49a620, 0x3fe9a4dfa42b06b2, // 0.59816, 0.80138 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe2fbc24b441015, 0x3fe9c2d110f075c3, // 0.59323, 0.80503 + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685 + 0x3fe2d333d34e9bb7, 0x3fe9e082edb42472, // 0.58828, 0.80866 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe2aa76e87aeb58, 0x3fe9fdf4f13149de, // 0.58331, 0.81225 + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404 + 0x3fe2818bef4d3cba, 0x3fea1b26d2c0a75e, // 0.57831, 0.81581 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe258734cbb7110, 0x3fea38184a593bc6, // 0.5733, 0.81935 + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211 + 0x3fe22f2d662c13e1, 0x3fea54c91090f524, // 0.56826, 0.82285 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe205baa17560d6, 0x3fea7138de9d60f5, // 0.5632, 0.82632 + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805 + 0x3fe1dc1b64dc4872, 0x3fea8d676e545ad2, // 0.55812, 0.82976 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe1b250171373be, 0x3feaa9547a2cb98e, // 0.55302, 0.83317 + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486 + 0x3fe188591f3a46e5, 0x3feac4ffbd3efac8, // 0.54789, 0.83655 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe15e36e4dbe2bc, 0x3feae068f345ecef, // 0.54275, 0.83989 + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155 + 0x3fe133e9cfee254e, 0x3feafb8fd89f57b6, // 0.53759, 0.84321 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe1097248d0a956, 0x3feb16742a4ca2f5, // 0.5324, 0.84649 + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812 + 0x3fe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // 0.5272, 0.84974 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe0b405878f85ec, 0x3feb4b7409de7925, // 0.52198, 0.85296 + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456 + 0x3fe089112032b08c, 0x3feb658f14fdbc47, // 0.51673, 0.85615 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe05df3ec31b8b6, 0x3feb7f6686e792ea, // 0.51147, 0.8593 + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087 + 0x3fe032ae55edbd95, 0x3feb98fa1fd9155e, // 0.50619, 0.86242 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fe00740c82b82e0, 0x3febb249a0b6c40d, // 0.50089, 0.86551 + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705 + 0x3fdfb7575c24d2de, 0x3febcb54cb0d2327, // 0.49557, 0.86857 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdf5fdee656cda3, 0x3febe41b611154c1, // 0.49023, 0.8716 + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309 + 0x3fdf081906bff7fd, 0x3febfc9d25a1b147, // 0.48487, 0.87459 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fdeb00695f25620, 0x3fec14d9dc465e58, // 0.47949, 0.87755 + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901 + 0x3fde57a86d3cd824, 0x3fec2cd14931e3f1, // 0.4741, 0.88047 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fddfeff66a941de, 0x3fec44833141c004, // 0.46869, 0.88336 + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848 + 0x3fdda60c5cfa10d8, 0x3fec5bef59fef85a, // 0.46326, 0.88622 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdd4cd02ba8609c, 0x3fec7315899eaad7, // 0.45781, 0.88905 + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045 + 0x3fdcf34baee1cd21, 0x3fec89f587029c13, // 0.45235, 0.89184 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdc997fc3865388, 0x3feca08f19b9c449, // 0.44687, 0.8946 + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597 + 0x3fdc3f6d47263129, 0x3fecb6e20a00da99, // 0.44137, 0.89732 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdbe51517ffc0d9, 0x3fecccee20c2de9f, // 0.43586, 0.90002 + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135 + 0x3fdb8a7814fd5693, 0x3fece2b32799a060, // 0.43033, 0.90267 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdb2f971db31972, 0x3fecf830e8ce467b, // 0.42478, 0.9053 + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066 + 0x3fdad473125cdc08, 0x3fed0d672f59d2b9, // 0.41922, 0.90789 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fda790cd3dbf31a, 0x3fed2255c6e5a4e1, // 0.41364, 0.91044 + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171 + 0x3fda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // 0.40804, 0.91296 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fd9c17d440df9f2, 0x3fed4b5b1b187524, // 0.40243, 0.91545 + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668 + 0x3fd96555b7ab948f, 0x3fed5f7172888a7f, // 0.39681, 0.9179 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd908ef81ef7bd1, 0x3fed733f508c0dff, // 0.39117, 0.92032 + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151 + 0x3fd8ac4b86d5ed44, 0x3fed86c48445a450, // 0.38552, 0.9227 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // 0.37985, 0.92505 + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621 + 0x3fd7f24dd37341e3, 0x3fedacf42ce68ab9, // 0.37416, 0.92736 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd794f5e613dfae, 0x3fedbf9e4395759a, // 0.36847, 0.92964 + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077 + 0x3fd73763c9261092, 0x3fedd1fef38a915a, // 0.36276, 0.93188 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd6d998638a0cb5, 0x3fede4160f6d8d81, // 0.35703, 0.93409 + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518 + 0x3fd67b949cad63ca, 0x3fedf5e36a9ba59c, // 0.35129, 0.93627 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd61d595c88c203, 0x3fee0766d9280f54, // 0.34554, 0.9384 + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946 + 0x3fd5bee78b9db3b6, 0x3fee18a02fdc66d9, // 0.33978, 0.94051 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd5604012f467b4, 0x3fee298f4439197a, // 0.334, 0.94257 + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359 + 0x3fd50163dc197047, 0x3fee3a33ec75ce85, // 0.32821, 0.9446 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd4a253d11b82f3, 0x3fee4a8dff81ce5e, // 0.32241, 0.9466 + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759 + 0x3fd44310dc8936f0, 0x3fee5a9d550467d3, // 0.31659, 0.94856 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd3e39be96ec271, 0x3fee6a61c55d53a7, // 0.31077, 0.95049 + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144 + 0x3fd383f5e353b6aa, 0x3fee79db29a5165a, // 0.30493, 0.95238 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd3241fb638baaf, 0x3fee89095bad6025, // 0.29908, 0.95423 + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514 + 0x3fd2c41a4e954520, 0x3fee97ec36016b30, // 0.29322, 0.95605 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd263e6995554ba, 0x3feea68393e65800, // 0.28735, 0.95783 + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587 + 0x3fd2038583d727bd, 0x3feeb4cf515b8811, // 0.28146, 0.95957 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // 0.27557, 0.96128 + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212 + 0x3fd1423eefc69378, 0x3feed0835e999009, // 0.26967, 0.96295 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd0e15b4e1749cd, 0x3feeddeb6a078651, // 0.26375, 0.96459 + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539 + 0x3fd0804e05eb661e, 0x3feeeb074c50a544, // 0.25783, 0.96619 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // 0.2519, 0.96775 + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852 + 0x3fcf7b7480bd3801, 0x3fef045a14cf738c, // 0.24596, 0.96928 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fceb86b462de348, 0x3fef1090bc898f5f, // 0.24, 0.97077 + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715 + 0x3fcdf5163f01099a, 0x3fef1c7abe284708, // 0.23404, 0.97223 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcd31774d2cbdee, 0x3fef2817fc4609ce, // 0.22807, 0.97364 + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434 + 0x3fcc6d90535d74dc, 0x3fef33685a3aaef0, // 0.22209, 0.97503 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcba96334f15dad, 0x3fef3e6bbc1bbc65, // 0.21611, 0.97637 + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703 + 0x3fcae4f1d5f3b9ab, 0x3fef492206bcabb4, // 0.21011, 0.97768 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fca203e1b1831da, 0x3fef538b1faf2d07, // 0.20411, 0.97895 + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957 + 0x3fc95b49e9b62af9, 0x3fef5da6ed43685d, // 0.1981, 0.98018 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc8961727c41804, 0x3fef677556883cee, // 0.19208, 0.98138 + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196 + 0x3fc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // 0.18606, 0.98254 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc70afd8d08c4ff, 0x3fef7a299c1a322a, // 0.18002, 0.98366 + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421 + 0x3fc6451a831d830d, 0x3fef830f4a40c60c, // 0.17398, 0.98475 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc57f008654cbde, 0x3fef8ba737cb4b78, // 0.16794, 0.9858 + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631 + 0x3fc4b8b17f79fa88, 0x3fef93f14f85ac08, // 0.16189, 0.98681 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc3f22f57db4893, 0x3fef9bed7cfbde29, // 0.15583, 0.98778 + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826 + 0x3fc32b7bf94516a7, 0x3fefa39bac7a1791, // 0.14976, 0.98872 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc264994dfd340a, 0x3fefaafbcb0cfddc, // 0.1437, 0.98962 + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006 + 0x3fc19d8940be24e7, 0x3fefb20dc681d54d, // 0.13762, 0.99049 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fc0d64dbcb26786, 0x3fefb8d18d66adb7, // 0.13154, 0.99131 + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171 + 0x3fc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // 0.12545, 0.9921 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // 0.11937, 0.99285 + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321 + 0x3fbcff533b307dc1, 0x3fefcb4703914354, // 0.11327, 0.99356 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fbb6fa6ec38f64c, 0x3fefd0d158d86087, // 0.10717, 0.99424 + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456 + 0x3fb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // 0.10107, 0.99488 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb84f8712c130a0, 0x3fefdafa7514538c, // 0.094963, 0.99548 + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577 + 0x3fb6bf1b3e79b129, 0x3fefdf9922f73307, // 0.088854, 0.99604 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb52e774a4d4d0a, 0x3fefe3e92be9d886, // 0.08274, 0.99657 + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682 + 0x3fb39d9f12c5a299, 0x3fefe7ea85482d60, // 0.076624, 0.99706 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fb20c9674ed444c, 0x3fefeb9d2530410f, // 0.070505, 0.99751 + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772 + 0x3fb07b614e463064, 0x3fefef0102826191, // 0.064383, 0.99793 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fadd406f9808ec8, 0x3feff21614e131ed, // 0.058258, 0.9983 + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848 + 0x3faab101bd5f8317, 0x3feff4dc54b1bed3, // 0.052132, 0.99864 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3fa78dbaa5874685, 0x3feff753bb1b9164, // 0.046003, 0.99894 + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908 + 0x3fa46a396ff86179, 0x3feff97c4208c014, // 0.039873, 0.9992 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3fa14685db42c17e, 0x3feffb55e425fdae, // 0.033741, 0.99943 + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953 + 0x3f9c454f4ce53b1c, 0x3feffce09ce2a679, // 0.027608, 0.99962 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f95fd4d21fab226, 0x3feffe1c6870cb77, // 0.021474, 0.99977 + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983 + 0x3f8f6a296ab997ca, 0x3fefff0943c53bd1, // 0.015339, 0.99988 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x3f82d96b0e509703, 0x3fefffa72c978c4f, // 0.0092038, 0.99996 + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, // 0.0061359, 0.99998 + 0x3f6921f8becca4ba, 0x3feffff621621d02, // 0.003068, 1 + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0xbf6921f8becca4ba, 0x3feffff621621d02, // -0.003068, 1 + 0xbf7921f0fe670071, 0x3fefffd8858e8a92, //-0.0061359, 0.99998 + 0xbf82d96b0e509703, 0x3fefffa72c978c4f, //-0.0092038, 0.99996 + 0xbf8921d1fcdec784, 0x3fefff62169b92db, // -0.012272, 0.99992 + 0xbf8f6a296ab997ca, 0x3fefff0943c53bd1, // -0.015339, 0.99988 + 0xbf92d936bbe30efd, 0x3feffe9cb44b51a1, // -0.018407, 0.99983 + 0xbf95fd4d21fab226, 0x3feffe1c6870cb77, // -0.021474, 0.99977 + 0xbf992155f7a3667e, 0x3feffd886084cd0d, // -0.024541, 0.9997 + 0xbf9c454f4ce53b1c, 0x3feffce09ce2a679, // -0.027608, 0.99962 + 0xbf9f693731d1cf01, 0x3feffc251df1d3f8, // -0.030675, 0.99953 + 0xbfa14685db42c17e, 0x3feffb55e425fdae, // -0.033741, 0.99943 + 0xbfa2d865759455cd, 0x3feffa72effef75d, // -0.036807, 0.99932 + 0xbfa46a396ff86179, 0x3feff97c4208c014, // -0.039873, 0.9992 + 0xbfa5fc00d290cd43, 0x3feff871dadb81df, // -0.042938, 0.99908 + 0xbfa78dbaa5874685, 0x3feff753bb1b9164, // -0.046003, 0.99894 + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, // -0.049068, 0.9988 + 0xbfaab101bd5f8317, 0x3feff4dc54b1bed3, // -0.052132, 0.99864 + 0xbfac428d12c0d7e3, 0x3feff3830f8d575c, // -0.055195, 0.99848 + 0xbfadd406f9808ec8, 0x3feff21614e131ed, // -0.058258, 0.9983 + 0xbfaf656e79f820e0, 0x3feff095658e71ad, // -0.061321, 0.99812 + 0xbfb07b614e463064, 0x3fefef0102826191, // -0.064383, 0.99793 + 0xbfb1440134d709b2, 0x3fefed58ecb673c4, // -0.067444, 0.99772 + 0xbfb20c9674ed444c, 0x3fefeb9d2530410f, // -0.070505, 0.99751 + 0xbfb2d52092ce19f6, 0x3fefe9cdad01883a, // -0.073565, 0.99729 + 0xbfb39d9f12c5a299, 0x3fefe7ea85482d60, // -0.076624, 0.99706 + 0xbfb4661179272096, 0x3fefe5f3af2e3940, // -0.079682, 0.99682 + 0xbfb52e774a4d4d0a, 0x3fefe3e92be9d886, // -0.08274, 0.99657 + 0xbfb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // -0.085797, 0.99631 + 0xbfb6bf1b3e79b129, 0x3fefdf9922f73307, // -0.088854, 0.99604 + 0xbfb787586a5d5b21, 0x3fefdd539ff1f456, // -0.091909, 0.99577 + 0xbfb84f8712c130a0, 0x3fefdafa7514538c, // -0.094963, 0.99548 + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, // -0.098017, 0.99518 + 0xbfb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // -0.10107, 0.99488 + 0xbfbaa7b724495c04, 0x3fefd37914220b84, // -0.10412, 0.99456 + 0xbfbb6fa6ec38f64c, 0x3fefd0d158d86087, // -0.10717, 0.99424 + 0xbfbc3785c79ec2d5, 0x3fefce15fd6da67b, // -0.11022, 0.99391 + 0xbfbcff533b307dc1, 0x3fefcb4703914354, // -0.11327, 0.99356 + 0xbfbdc70ecbae9fc8, 0x3fefc8646cfeb721, // -0.11632, 0.99321 + 0xbfbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // -0.11937, 0.99285 + 0xbfbf564e56a9730e, 0x3fefc26470e19fd3, // -0.12241, 0.99248 + 0xbfc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // -0.12545, 0.9921 + 0xbfc072a047ba831d, 0x3fefbc1617e44186, // -0.1285, 0.99171 + 0xbfc0d64dbcb26786, 0x3fefb8d18d66adb7, // -0.13154, 0.99131 + 0xbfc139f0cedaf576, 0x3fefb5797195d741, // -0.13458, 0.9909 + 0xbfc19d8940be24e7, 0x3fefb20dc681d54d, // -0.13762, 0.99049 + 0xbfc20116d4ec7bce, 0x3fefae8e8e46cfbb, // -0.14066, 0.99006 + 0xbfc264994dfd340a, 0x3fefaafbcb0cfddc, // -0.1437, 0.98962 + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918 + 0xbfc32b7bf94516a7, 0x3fefa39bac7a1791, // -0.14976, 0.98872 + 0xbfc38edbb0cd8d14, 0x3fef9fce55adb2c8, // -0.1528, 0.98826 + 0xbfc3f22f57db4893, 0x3fef9bed7cfbde29, // -0.15583, 0.98778 + 0xbfc45576b1293e5a, 0x3fef97f924c9099b, // -0.15886, 0.9873 + 0xbfc4b8b17f79fa88, 0x3fef93f14f85ac08, // -0.16189, 0.98681 + 0xbfc51bdf8597c5f2, 0x3fef8fd5ffae41db, // -0.16491, 0.98631 + 0xbfc57f008654cbde, 0x3fef8ba737cb4b78, // -0.16794, 0.9858 + 0xbfc5e214448b3fc6, 0x3fef8764fa714ba9, // -0.17096, 0.98528 + 0xbfc6451a831d830d, 0x3fef830f4a40c60c, // -0.17398, 0.98475 + 0xbfc6a81304f64ab2, 0x3fef7ea629e63d6e, // -0.177, 0.98421 + 0xbfc70afd8d08c4ff, 0x3fef7a299c1a322a, // -0.18002, 0.98366 + 0xbfc76dd9de50bf31, 0x3fef7599a3a12077, // -0.18304, 0.98311 + 0xbfc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // -0.18606, 0.98254 + 0xbfc83366e89c64c5, 0x3fef6c3f7df5bbb7, // -0.18907, 0.98196 + 0xbfc8961727c41804, 0x3fef677556883cee, // -0.19208, 0.98138 + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079 + 0xbfc95b49e9b62af9, 0x3fef5da6ed43685d, // -0.1981, 0.98018 + 0xbfc9bdcbf2dc4366, 0x3fef58a2b1789e84, // -0.2011, 0.97957 + 0xbfca203e1b1831da, 0x3fef538b1faf2d07, // -0.20411, 0.97895 + 0xbfca82a025b00451, 0x3fef4e603b0b2f2d, // -0.20711, 0.97832 + 0xbfcae4f1d5f3b9ab, 0x3fef492206bcabb4, // -0.21011, 0.97768 + 0xbfcb4732ef3d6722, 0x3fef43d085ff92dd, // -0.21311, 0.97703 + 0xbfcba96334f15dad, 0x3fef3e6bbc1bbc65, // -0.21611, 0.97637 + 0xbfcc0b826a7e4f63, 0x3fef38f3ac64e589, // -0.2191, 0.9757 + 0xbfcc6d90535d74dc, 0x3fef33685a3aaef0, // -0.22209, 0.97503 + 0xbfcccf8cb312b286, 0x3fef2dc9c9089a9d, // -0.22508, 0.97434 + 0xbfcd31774d2cbdee, 0x3fef2817fc4609ce, // -0.22807, 0.97364 + 0xbfcd934fe5454311, 0x3fef2252f7763ada, // -0.23106, 0.97294 + 0xbfcdf5163f01099a, 0x3fef1c7abe284708, // -0.23404, 0.97223 + 0xbfce56ca1e101a1b, 0x3fef168f53f7205d, // -0.23702, 0.9715 + 0xbfceb86b462de348, 0x3fef1090bc898f5f, // -0.24, 0.97077 + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003 + 0xbfcf7b7480bd3801, 0x3fef045a14cf738c, // -0.24596, 0.96928 + 0xbfcfdcdc1adfedf8, 0x3feefe220c0b95ec, // -0.24893, 0.96852 + 0xbfd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // -0.2519, 0.96775 + 0xbfd04fb80e37fdae, 0x3feef178a3e473c2, // -0.25487, 0.96698 + 0xbfd0804e05eb661e, 0x3feeeb074c50a544, // -0.25783, 0.96619 + 0xbfd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // -0.26079, 0.96539 + 0xbfd0e15b4e1749cd, 0x3feeddeb6a078651, // -0.26375, 0.96459 + 0xbfd111d262b1f677, 0x3feed740e7684963, // -0.26671, 0.96378 + 0xbfd1423eefc69378, 0x3feed0835e999009, // -0.26967, 0.96295 + 0xbfd172a0d7765177, 0x3feec9b2d3c3bf84, // -0.27262, 0.96212 + 0xbfd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // -0.27557, 0.96128 + 0xbfd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // -0.27852, 0.96043 + 0xbfd2038583d727bd, 0x3feeb4cf515b8811, // -0.28146, 0.95957 + 0xbfd233bbabc3bb72, 0x3feeadb2e8e7a88e, // -0.28441, 0.9587 + 0xbfd263e6995554ba, 0x3feea68393e65800, // -0.28735, 0.95783 + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694 + 0xbfd2c41a4e954520, 0x3fee97ec36016b30, // -0.29322, 0.95605 + 0xbfd2f422daec0386, 0x3fee9084361df7f3, // -0.29615, 0.95514 + 0xbfd3241fb638baaf, 0x3fee89095bad6025, // -0.29908, 0.95423 + 0xbfd35410c2e18152, 0x3fee817bab4cd10d, // -0.30201, 0.95331 + 0xbfd383f5e353b6aa, 0x3fee79db29a5165a, // -0.30493, 0.95238 + 0xbfd3b3cefa0414b7, 0x3fee7227db6a9744, // -0.30785, 0.95144 + 0xbfd3e39be96ec271, 0x3fee6a61c55d53a7, // -0.31077, 0.95049 + 0xbfd4135c94176602, 0x3fee6288ec48e112, // -0.31368, 0.94953 + 0xbfd44310dc8936f0, 0x3fee5a9d550467d3, // -0.31659, 0.94856 + 0xbfd472b8a5571054, 0x3fee529f04729ffc, // -0.3195, 0.94759 + 0xbfd4a253d11b82f3, 0x3fee4a8dff81ce5e, // -0.32241, 0.9466 + 0xbfd4d1e24278e76a, 0x3fee426a4b2bc17e, // -0.32531, 0.94561 + 0xbfd50163dc197047, 0x3fee3a33ec75ce85, // -0.32821, 0.9446 + 0xbfd530d880af3c24, 0x3fee31eae870ce25, // -0.33111, 0.94359 + 0xbfd5604012f467b4, 0x3fee298f4439197a, // -0.334, 0.94257 + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154 + 0xbfd5bee78b9db3b6, 0x3fee18a02fdc66d9, // -0.33978, 0.94051 + 0xbfd5ee27379ea693, 0x3fee100cca2980ac, // -0.34266, 0.93946 + 0xbfd61d595c88c203, 0x3fee0766d9280f54, // -0.34554, 0.9384 + 0xbfd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // -0.34842, 0.93734 + 0xbfd67b949cad63ca, 0x3fedf5e36a9ba59c, // -0.35129, 0.93627 + 0xbfd6aa9d7dc77e16, 0x3feded05f7de47da, // -0.35416, 0.93518 + 0xbfd6d998638a0cb5, 0x3fede4160f6d8d81, // -0.35703, 0.93409 + 0xbfd7088530fa459e, 0x3feddb13b6ccc23d, // -0.3599, 0.93299 + 0xbfd73763c9261092, 0x3fedd1fef38a915a, // -0.36276, 0.93188 + 0xbfd766340f2418f6, 0x3fedc8d7cb410260, // -0.36561, 0.93077 + 0xbfd794f5e613dfae, 0x3fedbf9e4395759a, // -0.36847, 0.92964 + 0xbfd7c3a9311dcce7, 0x3fedb6526238a09b, // -0.37132, 0.92851 + 0xbfd7f24dd37341e3, 0x3fedacf42ce68ab9, // -0.37416, 0.92736 + 0xbfd820e3b04eaac4, 0x3feda383a9668988, // -0.37701, 0.92621 + 0xbfd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // -0.37985, 0.92505 + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388 + 0xbfd8ac4b86d5ed44, 0x3fed86c48445a450, // -0.38552, 0.9227 + 0xbfd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // -0.38835, 0.92151 + 0xbfd908ef81ef7bd1, 0x3fed733f508c0dff, // -0.39117, 0.92032 + 0xbfd9372a63bc93d7, 0x3fed696173c9e68b, // -0.39399, 0.91911 + 0xbfd96555b7ab948f, 0x3fed5f7172888a7f, // -0.39681, 0.9179 + 0xbfd993716141bdfe, 0x3fed556f52e93eb1, // -0.39962, 0.91668 + 0xbfd9c17d440df9f2, 0x3fed4b5b1b187524, // -0.40243, 0.91545 + 0xbfd9ef7943a8ed8a, 0x3fed4134d14dc93a, // -0.40524, 0.91421 + 0xbfda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // -0.40804, 0.91296 + 0xbfda4b4127dea1e4, 0x3fed2cb220e0ef9f, // -0.41084, 0.91171 + 0xbfda790cd3dbf31a, 0x3fed2255c6e5a4e1, // -0.41364, 0.91044 + 0xbfdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // -0.41643, 0.90917 + 0xbfdad473125cdc08, 0x3fed0d672f59d2b9, // -0.41922, 0.90789 + 0xbfdb020d6c7f4009, 0x3fed02d4feb2bd92, // -0.422, 0.9066 + 0xbfdb2f971db31972, 0x3fecf830e8ce467b, // -0.42478, 0.9053 + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399 + 0xbfdb8a7814fd5693, 0x3fece2b32799a060, // -0.43033, 0.90267 + 0xbfdbb7cf2304bd01, 0x3fecd7d9898b32f6, // -0.43309, 0.90135 + 0xbfdbe51517ffc0d9, 0x3fecccee20c2de9f, // -0.43586, 0.90002 + 0xbfdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // -0.43862, 0.89867 + 0xbfdc3f6d47263129, 0x3fecb6e20a00da99, // -0.44137, 0.89732 + 0xbfdc6c7f4997000a, 0x3fecabc169a0b901, // -0.44412, 0.89597 + 0xbfdc997fc3865388, 0x3feca08f19b9c449, // -0.44687, 0.8946 + 0xbfdcc66e9931c45d, 0x3fec954b213411f5, // -0.44961, 0.89322 + 0xbfdcf34baee1cd21, 0x3fec89f587029c13, // -0.45235, 0.89184 + 0xbfdd2016e8e9db5b, 0x3fec7e8e52233cf3, // -0.45508, 0.89045 + 0xbfdd4cd02ba8609c, 0x3fec7315899eaad7, // -0.45781, 0.88905 + 0xbfdd79775b86e389, 0x3fec678b3488739b, // -0.46054, 0.88764 + 0xbfdda60c5cfa10d8, 0x3fec5bef59fef85a, // -0.46326, 0.88622 + 0xbfddd28f1481cc58, 0x3fec5042012b6907, // -0.46598, 0.8848 + 0xbfddfeff66a941de, 0x3fec44833141c004, // -0.46869, 0.88336 + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192 + 0xbfde57a86d3cd824, 0x3fec2cd14931e3f1, // -0.4741, 0.88047 + 0xbfde83e0eaf85113, 0x3fec20de3fa971b0, // -0.4768, 0.87901 + 0xbfdeb00695f25620, 0x3fec14d9dc465e58, // -0.47949, 0.87755 + 0xbfdedc1952ef78d5, 0x3fec08c426725549, // -0.48218, 0.87607 + 0xbfdf081906bff7fd, 0x3febfc9d25a1b147, // -0.48487, 0.87459 + 0xbfdf3405963fd068, 0x3febf064e15377dd, // -0.48755, 0.87309 + 0xbfdf5fdee656cda3, 0x3febe41b611154c1, // -0.49023, 0.8716 + 0xbfdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // -0.4929, 0.87009 + 0xbfdfb7575c24d2de, 0x3febcb54cb0d2327, // -0.49557, 0.86857 + 0xbfdfe2f64be7120f, 0x3febbed7c49380ea, // -0.49823, 0.86705 + 0xbfe00740c82b82e0, 0x3febb249a0b6c40d, // -0.50089, 0.86551 + 0xbfe01cfc874c3eb7, 0x3feba5aa673590d2, // -0.50354, 0.86397 + 0xbfe032ae55edbd95, 0x3feb98fa1fd9155e, // -0.50619, 0.86242 + 0xbfe0485626ae221a, 0x3feb8c38d27504e9, // -0.50883, 0.86087 + 0xbfe05df3ec31b8b6, 0x3feb7f6686e792ea, // -0.51147, 0.8593 + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773 + 0xbfe089112032b08c, 0x3feb658f14fdbc47, // -0.51673, 0.85615 + 0xbfe09e907417c5e1, 0x3feb5889fe921405, // -0.51936, 0.85456 + 0xbfe0b405878f85ec, 0x3feb4b7409de7925, // -0.52198, 0.85296 + 0xbfe0c9704d5d898f, 0x3feb3e4d3ef55712, // -0.52459, 0.85136 + 0xbfe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // -0.5272, 0.84974 + 0xbfe0f426bb2a8e7d, 0x3feb23cd470013b4, // -0.5298, 0.84812 + 0xbfe1097248d0a956, 0x3feb16742a4ca2f5, // -0.5324, 0.84649 + 0xbfe11eb3541b4b22, 0x3feb090a58150200, // -0.535, 0.84485 + 0xbfe133e9cfee254e, 0x3feafb8fd89f57b6, // -0.53759, 0.84321 + 0xbfe14915af336ceb, 0x3feaee04b43c1474, // -0.54017, 0.84155 + 0xbfe15e36e4dbe2bc, 0x3feae068f345ecef, // -0.54275, 0.83989 + 0xbfe1734d63dedb49, 0x3fead2bc9e21d511, // -0.54532, 0.83822 + 0xbfe188591f3a46e5, 0x3feac4ffbd3efac8, // -0.54789, 0.83655 + 0xbfe19d5a09f2b9b8, 0x3feab7325916c0d4, // -0.55046, 0.83486 + 0xbfe1b250171373be, 0x3feaa9547a2cb98e, // -0.55302, 0.83317 + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147 + 0xbfe1dc1b64dc4872, 0x3fea8d676e545ad2, // -0.55812, 0.82976 + 0xbfe1f0f08bbc861b, 0x3fea7f58529fe69d, // -0.56066, 0.82805 + 0xbfe205baa17560d6, 0x3fea7138de9d60f5, // -0.5632, 0.82632 + 0xbfe21a799933eb58, 0x3fea63091b02fae2, // -0.56573, 0.82459 + 0xbfe22f2d662c13e1, 0x3fea54c91090f524, // -0.56826, 0.82285 + 0xbfe243d5fb98ac1f, 0x3fea4678c8119ac8, // -0.57078, 0.8211 + 0xbfe258734cbb7110, 0x3fea38184a593bc6, // -0.5733, 0.81935 + 0xbfe26d054cdd12df, 0x3fea29a7a0462782, // -0.57581, 0.81758 + 0xbfe2818bef4d3cba, 0x3fea1b26d2c0a75e, // -0.57831, 0.81581 + 0xbfe2960727629ca8, 0x3fea0c95eabaf937, // -0.58081, 0.81404 + 0xbfe2aa76e87aeb58, 0x3fe9fdf4f13149de, // -0.58331, 0.81225 + 0xbfe2bedb25faf3ea, 0x3fe9ef43ef29af94, // -0.5858, 0.81046 + 0xbfe2d333d34e9bb7, 0x3fe9e082edb42472, // -0.58828, 0.80866 + 0xbfe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // -0.59076, 0.80685 + 0xbfe2fbc24b441015, 0x3fe9c2d110f075c3, // -0.59323, 0.80503 + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321 + 0xbfe32421ec49a620, 0x3fe9a4dfa42b06b2, // -0.59816, 0.80138 + 0xbfe338400d0c8e57, 0x3fe995cf2ed80d22, // -0.60062, 0.79954 + 0xbfe34c5252c14de1, 0x3fe986aef1457594, // -0.60307, 0.79769 + 0xbfe36058b10659f3, 0x3fe9777ef4c7d742, // -0.60551, 0.79584 + 0xbfe374531b817f8d, 0x3fe9683f42bd7fe1, // -0.60795, 0.79398 + 0xbfe3884185dfeb22, 0x3fe958efe48e6dd7, // -0.61038, 0.79211 + 0xbfe39c23e3d63029, 0x3fe94990e3ac4a6c, // -0.61281, 0.79023 + 0xbfe3affa292050b9, 0x3fe93a22499263fc, // -0.61523, 0.78835 + 0xbfe3c3c44981c517, 0x3fe92aa41fc5a815, // -0.61765, 0.78646 + 0xbfe3d78238c58343, 0x3fe91b166fd49da2, // -0.62006, 0.78456 + 0xbfe3eb33eabe0680, 0x3fe90b7943575efe, // -0.62246, 0.78265 + 0xbfe3fed9534556d4, 0x3fe8fbcca3ef940d, // -0.62486, 0.78074 + 0xbfe41272663d108c, 0x3fe8ec109b486c49, // -0.62725, 0.77882 + 0xbfe425ff178e6bb1, 0x3fe8dc45331698cc, // -0.62964, 0.77689 + 0xbfe4397f5b2a4380, 0x3fe8cc6a75184655, // -0.63202, 0.77495 + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301 + 0xbfe4605a692b32a2, 0x3fe8ac871ede1d88, // -0.63676, 0.77106 + 0xbfe473b51b987347, 0x3fe89c7e9a4dd4ab, // -0.63912, 0.7691 + 0xbfe48703306091fe, 0x3fe88c66e7481ba1, // -0.64148, 0.76714 + 0xbfe49a449b9b0938, 0x3fe87c400fba2ebf, // -0.64383, 0.76517 + 0xbfe4ad79516722f0, 0x3fe86c0a1d9aa195, // -0.64618, 0.76319 + 0xbfe4c0a145ec0004, 0x3fe85bc51ae958cc, // -0.64851, 0.7612 + 0xbfe4d3bc6d589f80, 0x3fe84b7111af83f9, // -0.65085, 0.75921 + 0xbfe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // -0.65317, 0.75721 + 0xbfe4f9cc25cca486, 0x3fe82a9c13f545ff, // -0.65549, 0.7552 + 0xbfe50cc09f59a09b, 0x3fe81a1b33b57acc, // -0.65781, 0.75319 + 0xbfe51fa81cd99aa6, 0x3fe8098b756e52fa, // -0.66011, 0.75117 + 0xbfe5328292a35596, 0x3fe7f8ece3571771, // -0.66242, 0.74914 + 0xbfe5454ff5159dfb, 0x3fe7e83f87b03686, // -0.66471, 0.7471 + 0xbfe5581038975137, 0x3fe7d7836cc33db2, // -0.667, 0.74506 + 0xbfe56ac35197649e, 0x3fe7c6b89ce2d333, // -0.66928, 0.74301 + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095 + 0xbfe59001d5f723df, 0x3fe7a4f707bf97d2, // -0.67383, 0.73889 + 0xbfe5a28d2a5d7250, 0x3fe79400574f55e4, // -0.67609, 0.73682 + 0xbfe5b50b264f7448, 0x3fe782fb1b90b35b, // -0.67835, 0.73474 + 0xbfe5c77bbe65018c, 0x3fe771e75f037261, // -0.6806, 0.73265 + 0xbfe5d9dee73e345c, 0x3fe760c52c304764, // -0.68285, 0.73056 + 0xbfe5ec3495837074, 0x3fe74f948da8d28d, // -0.68508, 0.72846 + 0xbfe5fe7cbde56a0f, 0x3fe73e558e079942, // -0.68732, 0.72636 + 0xbfe610b7551d2cde, 0x3fe72d0837efff97, // -0.68954, 0.72425 + 0xbfe622e44fec22ff, 0x3fe71bac960e41bf, // -0.69176, 0.72213 + 0xbfe63503a31c1be8, 0x3fe70a42b3176d7a, // -0.69397, 0.72 + 0xbfe64715437f535b, 0x3fe6f8ca99c95b75, // -0.69618, 0.71787 + 0xbfe6591925f0783e, 0x3fe6e74454eaa8ae, // -0.69838, 0.71573 + 0xbfe66b0f3f52b386, 0x3fe6d5afef4aafcc, // -0.70057, 0.71358 + 0xbfe67cf78491af10, 0x3fe6c40d73c18275, // -0.70275, 0.71143 + 0xbfe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // -0.70493, 0.70927 + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711 + 0xbfe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // -0.70927, 0.70493 + 0xbfe6c40d73c18275, 0x3fe67cf78491af10, // -0.71143, 0.70275 + 0xbfe6d5afef4aafcc, 0x3fe66b0f3f52b386, // -0.71358, 0.70057 + 0xbfe6e74454eaa8ae, 0x3fe6591925f0783e, // -0.71573, 0.69838 + 0xbfe6f8ca99c95b75, 0x3fe64715437f535b, // -0.71787, 0.69618 + 0xbfe70a42b3176d7a, 0x3fe63503a31c1be8, // -0.72, 0.69397 + 0xbfe71bac960e41bf, 0x3fe622e44fec22ff, // -0.72213, 0.69176 + 0xbfe72d0837efff97, 0x3fe610b7551d2cde, // -0.72425, 0.68954 + 0xbfe73e558e079942, 0x3fe5fe7cbde56a0f, // -0.72636, 0.68732 + 0xbfe74f948da8d28d, 0x3fe5ec3495837074, // -0.72846, 0.68508 + 0xbfe760c52c304764, 0x3fe5d9dee73e345c, // -0.73056, 0.68285 + 0xbfe771e75f037261, 0x3fe5c77bbe65018c, // -0.73265, 0.6806 + 0xbfe782fb1b90b35b, 0x3fe5b50b264f7448, // -0.73474, 0.67835 + 0xbfe79400574f55e4, 0x3fe5a28d2a5d7250, // -0.73682, 0.67609 + 0xbfe7a4f707bf97d2, 0x3fe59001d5f723df, // -0.73889, 0.67383 + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156 + 0xbfe7c6b89ce2d333, 0x3fe56ac35197649e, // -0.74301, 0.66928 + 0xbfe7d7836cc33db2, 0x3fe5581038975137, // -0.74506, 0.667 + 0xbfe7e83f87b03686, 0x3fe5454ff5159dfb, // -0.7471, 0.66471 + 0xbfe7f8ece3571771, 0x3fe5328292a35596, // -0.74914, 0.66242 + 0xbfe8098b756e52fa, 0x3fe51fa81cd99aa6, // -0.75117, 0.66011 + 0xbfe81a1b33b57acc, 0x3fe50cc09f59a09b, // -0.75319, 0.65781 + 0xbfe82a9c13f545ff, 0x3fe4f9cc25cca486, // -0.7552, 0.65549 + 0xbfe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // -0.75721, 0.65317 + 0xbfe84b7111af83f9, 0x3fe4d3bc6d589f80, // -0.75921, 0.65085 + 0xbfe85bc51ae958cc, 0x3fe4c0a145ec0004, // -0.7612, 0.64851 + 0xbfe86c0a1d9aa195, 0x3fe4ad79516722f0, // -0.76319, 0.64618 + 0xbfe87c400fba2ebf, 0x3fe49a449b9b0938, // -0.76517, 0.64383 + 0xbfe88c66e7481ba1, 0x3fe48703306091fe, // -0.76714, 0.64148 + 0xbfe89c7e9a4dd4ab, 0x3fe473b51b987347, // -0.7691, 0.63912 + 0xbfe8ac871ede1d88, 0x3fe4605a692b32a2, // -0.77106, 0.63676 + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439 + 0xbfe8cc6a75184655, 0x3fe4397f5b2a4380, // -0.77495, 0.63202 + 0xbfe8dc45331698cc, 0x3fe425ff178e6bb1, // -0.77689, 0.62964 + 0xbfe8ec109b486c49, 0x3fe41272663d108c, // -0.77882, 0.62725 + 0xbfe8fbcca3ef940d, 0x3fe3fed9534556d4, // -0.78074, 0.62486 + 0xbfe90b7943575efe, 0x3fe3eb33eabe0680, // -0.78265, 0.62246 + 0xbfe91b166fd49da2, 0x3fe3d78238c58343, // -0.78456, 0.62006 + 0xbfe92aa41fc5a815, 0x3fe3c3c44981c517, // -0.78646, 0.61765 + 0xbfe93a22499263fc, 0x3fe3affa292050b9, // -0.78835, 0.61523 + 0xbfe94990e3ac4a6c, 0x3fe39c23e3d63029, // -0.79023, 0.61281 + 0xbfe958efe48e6dd7, 0x3fe3884185dfeb22, // -0.79211, 0.61038 + 0xbfe9683f42bd7fe1, 0x3fe374531b817f8d, // -0.79398, 0.60795 + 0xbfe9777ef4c7d742, 0x3fe36058b10659f3, // -0.79584, 0.60551 + 0xbfe986aef1457594, 0x3fe34c5252c14de1, // -0.79769, 0.60307 + 0xbfe995cf2ed80d22, 0x3fe338400d0c8e57, // -0.79954, 0.60062 + 0xbfe9a4dfa42b06b2, 0x3fe32421ec49a620, // -0.80138, 0.59816 + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957 + 0xbfe9c2d110f075c3, 0x3fe2fbc24b441015, // -0.80503, 0.59323 + 0xbfe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // -0.80685, 0.59076 + 0xbfe9e082edb42472, 0x3fe2d333d34e9bb7, // -0.80866, 0.58828 + 0xbfe9ef43ef29af94, 0x3fe2bedb25faf3ea, // -0.81046, 0.5858 + 0xbfe9fdf4f13149de, 0x3fe2aa76e87aeb58, // -0.81225, 0.58331 + 0xbfea0c95eabaf937, 0x3fe2960727629ca8, // -0.81404, 0.58081 + 0xbfea1b26d2c0a75e, 0x3fe2818bef4d3cba, // -0.81581, 0.57831 + 0xbfea29a7a0462782, 0x3fe26d054cdd12df, // -0.81758, 0.57581 + 0xbfea38184a593bc6, 0x3fe258734cbb7110, // -0.81935, 0.5733 + 0xbfea4678c8119ac8, 0x3fe243d5fb98ac1f, // -0.8211, 0.57078 + 0xbfea54c91090f524, 0x3fe22f2d662c13e1, // -0.82285, 0.56826 + 0xbfea63091b02fae2, 0x3fe21a799933eb58, // -0.82459, 0.56573 + 0xbfea7138de9d60f5, 0x3fe205baa17560d6, // -0.82632, 0.5632 + 0xbfea7f58529fe69d, 0x3fe1f0f08bbc861b, // -0.82805, 0.56066 + 0xbfea8d676e545ad2, 0x3fe1dc1b64dc4872, // -0.82976, 0.55812 + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557 + 0xbfeaa9547a2cb98e, 0x3fe1b250171373be, // -0.83317, 0.55302 + 0xbfeab7325916c0d4, 0x3fe19d5a09f2b9b8, // -0.83486, 0.55046 + 0xbfeac4ffbd3efac8, 0x3fe188591f3a46e5, // -0.83655, 0.54789 + 0xbfead2bc9e21d511, 0x3fe1734d63dedb49, // -0.83822, 0.54532 + 0xbfeae068f345ecef, 0x3fe15e36e4dbe2bc, // -0.83989, 0.54275 + 0xbfeaee04b43c1474, 0x3fe14915af336ceb, // -0.84155, 0.54017 + 0xbfeafb8fd89f57b6, 0x3fe133e9cfee254e, // -0.84321, 0.53759 + 0xbfeb090a58150200, 0x3fe11eb3541b4b22, // -0.84485, 0.535 + 0xbfeb16742a4ca2f5, 0x3fe1097248d0a956, // -0.84649, 0.5324 + 0xbfeb23cd470013b4, 0x3fe0f426bb2a8e7d, // -0.84812, 0.5298 + 0xbfeb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // -0.84974, 0.5272 + 0xbfeb3e4d3ef55712, 0x3fe0c9704d5d898f, // -0.85136, 0.52459 + 0xbfeb4b7409de7925, 0x3fe0b405878f85ec, // -0.85296, 0.52198 + 0xbfeb5889fe921405, 0x3fe09e907417c5e1, // -0.85456, 0.51936 + 0xbfeb658f14fdbc47, 0x3fe089112032b08c, // -0.85615, 0.51673 + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141 + 0xbfeb7f6686e792ea, 0x3fe05df3ec31b8b6, // -0.8593, 0.51147 + 0xbfeb8c38d27504e9, 0x3fe0485626ae221a, // -0.86087, 0.50883 + 0xbfeb98fa1fd9155e, 0x3fe032ae55edbd95, // -0.86242, 0.50619 + 0xbfeba5aa673590d2, 0x3fe01cfc874c3eb7, // -0.86397, 0.50354 + 0xbfebb249a0b6c40d, 0x3fe00740c82b82e0, // -0.86551, 0.50089 + 0xbfebbed7c49380ea, 0x3fdfe2f64be7120f, // -0.86705, 0.49823 + 0xbfebcb54cb0d2327, 0x3fdfb7575c24d2de, // -0.86857, 0.49557 + 0xbfebd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // -0.87009, 0.4929 + 0xbfebe41b611154c1, 0x3fdf5fdee656cda3, // -0.8716, 0.49023 + 0xbfebf064e15377dd, 0x3fdf3405963fd068, // -0.87309, 0.48755 + 0xbfebfc9d25a1b147, 0x3fdf081906bff7fd, // -0.87459, 0.48487 + 0xbfec08c426725549, 0x3fdedc1952ef78d5, // -0.87607, 0.48218 + 0xbfec14d9dc465e58, 0x3fdeb00695f25620, // -0.87755, 0.47949 + 0xbfec20de3fa971b0, 0x3fde83e0eaf85113, // -0.87901, 0.4768 + 0xbfec2cd14931e3f1, 0x3fde57a86d3cd824, // -0.88047, 0.4741 + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714 + 0xbfec44833141c004, 0x3fddfeff66a941de, // -0.88336, 0.46869 + 0xbfec5042012b6907, 0x3fddd28f1481cc58, // -0.8848, 0.46598 + 0xbfec5bef59fef85a, 0x3fdda60c5cfa10d8, // -0.88622, 0.46326 + 0xbfec678b3488739b, 0x3fdd79775b86e389, // -0.88764, 0.46054 + 0xbfec7315899eaad7, 0x3fdd4cd02ba8609c, // -0.88905, 0.45781 + 0xbfec7e8e52233cf3, 0x3fdd2016e8e9db5b, // -0.89045, 0.45508 + 0xbfec89f587029c13, 0x3fdcf34baee1cd21, // -0.89184, 0.45235 + 0xbfec954b213411f5, 0x3fdcc66e9931c45d, // -0.89322, 0.44961 + 0xbfeca08f19b9c449, 0x3fdc997fc3865388, // -0.8946, 0.44687 + 0xbfecabc169a0b901, 0x3fdc6c7f4997000a, // -0.89597, 0.44412 + 0xbfecb6e20a00da99, 0x3fdc3f6d47263129, // -0.89732, 0.44137 + 0xbfecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // -0.89867, 0.43862 + 0xbfecccee20c2de9f, 0x3fdbe51517ffc0d9, // -0.90002, 0.43586 + 0xbfecd7d9898b32f6, 0x3fdbb7cf2304bd01, // -0.90135, 0.43309 + 0xbfece2b32799a060, 0x3fdb8a7814fd5693, // -0.90267, 0.43033 + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756 + 0xbfecf830e8ce467b, 0x3fdb2f971db31972, // -0.9053, 0.42478 + 0xbfed02d4feb2bd92, 0x3fdb020d6c7f4009, // -0.9066, 0.422 + 0xbfed0d672f59d2b9, 0x3fdad473125cdc08, // -0.90789, 0.41922 + 0xbfed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // -0.90917, 0.41643 + 0xbfed2255c6e5a4e1, 0x3fda790cd3dbf31a, // -0.91044, 0.41364 + 0xbfed2cb220e0ef9f, 0x3fda4b4127dea1e4, // -0.91171, 0.41084 + 0xbfed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // -0.91296, 0.40804 + 0xbfed4134d14dc93a, 0x3fd9ef7943a8ed8a, // -0.91421, 0.40524 + 0xbfed4b5b1b187524, 0x3fd9c17d440df9f2, // -0.91545, 0.40243 + 0xbfed556f52e93eb1, 0x3fd993716141bdfe, // -0.91668, 0.39962 + 0xbfed5f7172888a7f, 0x3fd96555b7ab948f, // -0.9179, 0.39681 + 0xbfed696173c9e68b, 0x3fd9372a63bc93d7, // -0.91911, 0.39399 + 0xbfed733f508c0dff, 0x3fd908ef81ef7bd1, // -0.92032, 0.39117 + 0xbfed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // -0.92151, 0.38835 + 0xbfed86c48445a450, 0x3fd8ac4b86d5ed44, // -0.9227, 0.38552 + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268 + 0xbfed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // -0.92505, 0.37985 + 0xbfeda383a9668988, 0x3fd820e3b04eaac4, // -0.92621, 0.37701 + 0xbfedacf42ce68ab9, 0x3fd7f24dd37341e3, // -0.92736, 0.37416 + 0xbfedb6526238a09b, 0x3fd7c3a9311dcce7, // -0.92851, 0.37132 + 0xbfedbf9e4395759a, 0x3fd794f5e613dfae, // -0.92964, 0.36847 + 0xbfedc8d7cb410260, 0x3fd766340f2418f6, // -0.93077, 0.36561 + 0xbfedd1fef38a915a, 0x3fd73763c9261092, // -0.93188, 0.36276 + 0xbfeddb13b6ccc23d, 0x3fd7088530fa459e, // -0.93299, 0.3599 + 0xbfede4160f6d8d81, 0x3fd6d998638a0cb5, // -0.93409, 0.35703 + 0xbfeded05f7de47da, 0x3fd6aa9d7dc77e16, // -0.93518, 0.35416 + 0xbfedf5e36a9ba59c, 0x3fd67b949cad63ca, // -0.93627, 0.35129 + 0xbfedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // -0.93734, 0.34842 + 0xbfee0766d9280f54, 0x3fd61d595c88c203, // -0.9384, 0.34554 + 0xbfee100cca2980ac, 0x3fd5ee27379ea693, // -0.93946, 0.34266 + 0xbfee18a02fdc66d9, 0x3fd5bee78b9db3b6, // -0.94051, 0.33978 + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689 + 0xbfee298f4439197a, 0x3fd5604012f467b4, // -0.94257, 0.334 + 0xbfee31eae870ce25, 0x3fd530d880af3c24, // -0.94359, 0.33111 + 0xbfee3a33ec75ce85, 0x3fd50163dc197047, // -0.9446, 0.32821 + 0xbfee426a4b2bc17e, 0x3fd4d1e24278e76a, // -0.94561, 0.32531 + 0xbfee4a8dff81ce5e, 0x3fd4a253d11b82f3, // -0.9466, 0.32241 + 0xbfee529f04729ffc, 0x3fd472b8a5571054, // -0.94759, 0.3195 + 0xbfee5a9d550467d3, 0x3fd44310dc8936f0, // -0.94856, 0.31659 + 0xbfee6288ec48e112, 0x3fd4135c94176602, // -0.94953, 0.31368 + 0xbfee6a61c55d53a7, 0x3fd3e39be96ec271, // -0.95049, 0.31077 + 0xbfee7227db6a9744, 0x3fd3b3cefa0414b7, // -0.95144, 0.30785 + 0xbfee79db29a5165a, 0x3fd383f5e353b6aa, // -0.95238, 0.30493 + 0xbfee817bab4cd10d, 0x3fd35410c2e18152, // -0.95331, 0.30201 + 0xbfee89095bad6025, 0x3fd3241fb638baaf, // -0.95423, 0.29908 + 0xbfee9084361df7f3, 0x3fd2f422daec0386, // -0.95514, 0.29615 + 0xbfee97ec36016b30, 0x3fd2c41a4e954520, // -0.95605, 0.29322 + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028 + 0xbfeea68393e65800, 0x3fd263e6995554ba, // -0.95783, 0.28735 + 0xbfeeadb2e8e7a88e, 0x3fd233bbabc3bb72, // -0.9587, 0.28441 + 0xbfeeb4cf515b8811, 0x3fd2038583d727bd, // -0.95957, 0.28146 + 0xbfeebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // -0.96043, 0.27852 + 0xbfeec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // -0.96128, 0.27557 + 0xbfeec9b2d3c3bf84, 0x3fd172a0d7765177, // -0.96212, 0.27262 + 0xbfeed0835e999009, 0x3fd1423eefc69378, // -0.96295, 0.26967 + 0xbfeed740e7684963, 0x3fd111d262b1f677, // -0.96378, 0.26671 + 0xbfeeddeb6a078651, 0x3fd0e15b4e1749cd, // -0.96459, 0.26375 + 0xbfeee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // -0.96539, 0.26079 + 0xbfeeeb074c50a544, 0x3fd0804e05eb661e, // -0.96619, 0.25783 + 0xbfeef178a3e473c2, 0x3fd04fb80e37fdae, // -0.96698, 0.25487 + 0xbfeef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // -0.96775, 0.2519 + 0xbfeefe220c0b95ec, 0x3fcfdcdc1adfedf8, // -0.96852, 0.24893 + 0xbfef045a14cf738c, 0x3fcf7b7480bd3801, // -0.96928, 0.24596 + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298 + 0xbfef1090bc898f5f, 0x3fceb86b462de348, // -0.97077, 0.24 + 0xbfef168f53f7205d, 0x3fce56ca1e101a1b, // -0.9715, 0.23702 + 0xbfef1c7abe284708, 0x3fcdf5163f01099a, // -0.97223, 0.23404 + 0xbfef2252f7763ada, 0x3fcd934fe5454311, // -0.97294, 0.23106 + 0xbfef2817fc4609ce, 0x3fcd31774d2cbdee, // -0.97364, 0.22807 + 0xbfef2dc9c9089a9d, 0x3fcccf8cb312b286, // -0.97434, 0.22508 + 0xbfef33685a3aaef0, 0x3fcc6d90535d74dc, // -0.97503, 0.22209 + 0xbfef38f3ac64e589, 0x3fcc0b826a7e4f63, // -0.9757, 0.2191 + 0xbfef3e6bbc1bbc65, 0x3fcba96334f15dad, // -0.97637, 0.21611 + 0xbfef43d085ff92dd, 0x3fcb4732ef3d6722, // -0.97703, 0.21311 + 0xbfef492206bcabb4, 0x3fcae4f1d5f3b9ab, // -0.97768, 0.21011 + 0xbfef4e603b0b2f2d, 0x3fca82a025b00451, // -0.97832, 0.20711 + 0xbfef538b1faf2d07, 0x3fca203e1b1831da, // -0.97895, 0.20411 + 0xbfef58a2b1789e84, 0x3fc9bdcbf2dc4366, // -0.97957, 0.2011 + 0xbfef5da6ed43685d, 0x3fc95b49e9b62af9, // -0.98018, 0.1981 + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509 + 0xbfef677556883cee, 0x3fc8961727c41804, // -0.98138, 0.19208 + 0xbfef6c3f7df5bbb7, 0x3fc83366e89c64c5, // -0.98196, 0.18907 + 0xbfef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // -0.98254, 0.18606 + 0xbfef7599a3a12077, 0x3fc76dd9de50bf31, // -0.98311, 0.18304 + 0xbfef7a299c1a322a, 0x3fc70afd8d08c4ff, // -0.98366, 0.18002 + 0xbfef7ea629e63d6e, 0x3fc6a81304f64ab2, // -0.98421, 0.177 + 0xbfef830f4a40c60c, 0x3fc6451a831d830d, // -0.98475, 0.17398 + 0xbfef8764fa714ba9, 0x3fc5e214448b3fc6, // -0.98528, 0.17096 + 0xbfef8ba737cb4b78, 0x3fc57f008654cbde, // -0.9858, 0.16794 + 0xbfef8fd5ffae41db, 0x3fc51bdf8597c5f2, // -0.98631, 0.16491 + 0xbfef93f14f85ac08, 0x3fc4b8b17f79fa88, // -0.98681, 0.16189 + 0xbfef97f924c9099b, 0x3fc45576b1293e5a, // -0.9873, 0.15886 + 0xbfef9bed7cfbde29, 0x3fc3f22f57db4893, // -0.98778, 0.15583 + 0xbfef9fce55adb2c8, 0x3fc38edbb0cd8d14, // -0.98826, 0.1528 + 0xbfefa39bac7a1791, 0x3fc32b7bf94516a7, // -0.98872, 0.14976 + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673 + 0xbfefaafbcb0cfddc, 0x3fc264994dfd340a, // -0.98962, 0.1437 + 0xbfefae8e8e46cfbb, 0x3fc20116d4ec7bce, // -0.99006, 0.14066 + 0xbfefb20dc681d54d, 0x3fc19d8940be24e7, // -0.99049, 0.13762 + 0xbfefb5797195d741, 0x3fc139f0cedaf576, // -0.9909, 0.13458 + 0xbfefb8d18d66adb7, 0x3fc0d64dbcb26786, // -0.99131, 0.13154 + 0xbfefbc1617e44186, 0x3fc072a047ba831d, // -0.99171, 0.1285 + 0xbfefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // -0.9921, 0.12545 + 0xbfefc26470e19fd3, 0x3fbf564e56a9730e, // -0.99248, 0.12241 + 0xbfefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // -0.99285, 0.11937 + 0xbfefc8646cfeb721, 0x3fbdc70ecbae9fc8, // -0.99321, 0.11632 + 0xbfefcb4703914354, 0x3fbcff533b307dc1, // -0.99356, 0.11327 + 0xbfefce15fd6da67b, 0x3fbc3785c79ec2d5, // -0.99391, 0.11022 + 0xbfefd0d158d86087, 0x3fbb6fa6ec38f64c, // -0.99424, 0.10717 + 0xbfefd37914220b84, 0x3fbaa7b724495c04, // -0.99456, 0.10412 + 0xbfefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // -0.99488, 0.10107 + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017 + 0xbfefdafa7514538c, 0x3fb84f8712c130a0, // -0.99548, 0.094963 + 0xbfefdd539ff1f456, 0x3fb787586a5d5b21, // -0.99577, 0.091909 + 0xbfefdf9922f73307, 0x3fb6bf1b3e79b129, // -0.99604, 0.088854 + 0xbfefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // -0.99631, 0.085797 + 0xbfefe3e92be9d886, 0x3fb52e774a4d4d0a, // -0.99657, 0.08274 + 0xbfefe5f3af2e3940, 0x3fb4661179272096, // -0.99682, 0.079682 + 0xbfefe7ea85482d60, 0x3fb39d9f12c5a299, // -0.99706, 0.076624 + 0xbfefe9cdad01883a, 0x3fb2d52092ce19f6, // -0.99729, 0.073565 + 0xbfefeb9d2530410f, 0x3fb20c9674ed444c, // -0.99751, 0.070505 + 0xbfefed58ecb673c4, 0x3fb1440134d709b2, // -0.99772, 0.067444 + 0xbfefef0102826191, 0x3fb07b614e463064, // -0.99793, 0.064383 + 0xbfeff095658e71ad, 0x3faf656e79f820e0, // -0.99812, 0.061321 + 0xbfeff21614e131ed, 0x3fadd406f9808ec8, // -0.9983, 0.058258 + 0xbfeff3830f8d575c, 0x3fac428d12c0d7e3, // -0.99848, 0.055195 + 0xbfeff4dc54b1bed3, 0x3faab101bd5f8317, // -0.99864, 0.052132 + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068 + 0xbfeff753bb1b9164, 0x3fa78dbaa5874685, // -0.99894, 0.046003 + 0xbfeff871dadb81df, 0x3fa5fc00d290cd43, // -0.99908, 0.042938 + 0xbfeff97c4208c014, 0x3fa46a396ff86179, // -0.9992, 0.039873 + 0xbfeffa72effef75d, 0x3fa2d865759455cd, // -0.99932, 0.036807 + 0xbfeffb55e425fdae, 0x3fa14685db42c17e, // -0.99943, 0.033741 + 0xbfeffc251df1d3f8, 0x3f9f693731d1cf01, // -0.99953, 0.030675 + 0xbfeffce09ce2a679, 0x3f9c454f4ce53b1c, // -0.99962, 0.027608 + 0xbfeffd886084cd0d, 0x3f992155f7a3667e, // -0.9997, 0.024541 + 0xbfeffe1c6870cb77, 0x3f95fd4d21fab226, // -0.99977, 0.021474 + 0xbfeffe9cb44b51a1, 0x3f92d936bbe30efd, // -0.99983, 0.018407 + 0xbfefff0943c53bd1, 0x3f8f6a296ab997ca, // -0.99988, 0.015339 + 0xbfefff62169b92db, 0x3f8921d1fcdec784, // -0.99992, 0.012272 + 0xbfefffa72c978c4f, 0x3f82d96b0e509703, // -0.99996, 0.0092038 + 0xbfefffd8858e8a92, 0x3f7921f0fe670071, // -0.99998, 0.0061359 + 0xbfeffff621621d02, 0x3f6921f8becca4ba, // -1, 0.003068 + 0xbff0000000000000, 0x0000000000000000, // -1, 0 + 0xbfeffff621621d02, 0xbf6921f8becca4ba, // -1, -0.003068 + 0xbfefffd8858e8a92, 0xbf7921f0fe670071, // -0.99998,-0.0061359 + 0xbfefffa72c978c4f, 0xbf82d96b0e509703, // -0.99996,-0.0092038 + 0xbfefff62169b92db, 0xbf8921d1fcdec784, // -0.99992, -0.012272 + 0xbfefff0943c53bd1, 0xbf8f6a296ab997ca, // -0.99988, -0.015339 + 0xbfeffe9cb44b51a1, 0xbf92d936bbe30efd, // -0.99983, -0.018407 + 0xbfeffe1c6870cb77, 0xbf95fd4d21fab226, // -0.99977, -0.021474 + 0xbfeffd886084cd0d, 0xbf992155f7a3667e, // -0.9997, -0.024541 + 0xbfeffce09ce2a679, 0xbf9c454f4ce53b1c, // -0.99962, -0.027608 + 0xbfeffc251df1d3f8, 0xbf9f693731d1cf01, // -0.99953, -0.030675 + 0xbfeffb55e425fdae, 0xbfa14685db42c17e, // -0.99943, -0.033741 + 0xbfeffa72effef75d, 0xbfa2d865759455cd, // -0.99932, -0.036807 + 0xbfeff97c4208c014, 0xbfa46a396ff86179, // -0.9992, -0.039873 + 0xbfeff871dadb81df, 0xbfa5fc00d290cd43, // -0.99908, -0.042938 + 0xbfeff753bb1b9164, 0xbfa78dbaa5874685, // -0.99894, -0.046003 + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988, -0.049068 + 0xbfeff4dc54b1bed3, 0xbfaab101bd5f8317, // -0.99864, -0.052132 + 0xbfeff3830f8d575c, 0xbfac428d12c0d7e3, // -0.99848, -0.055195 + 0xbfeff21614e131ed, 0xbfadd406f9808ec8, // -0.9983, -0.058258 + 0xbfeff095658e71ad, 0xbfaf656e79f820e0, // -0.99812, -0.061321 + 0xbfefef0102826191, 0xbfb07b614e463064, // -0.99793, -0.064383 + 0xbfefed58ecb673c4, 0xbfb1440134d709b2, // -0.99772, -0.067444 + 0xbfefeb9d2530410f, 0xbfb20c9674ed444c, // -0.99751, -0.070505 + 0xbfefe9cdad01883a, 0xbfb2d52092ce19f6, // -0.99729, -0.073565 + 0xbfefe7ea85482d60, 0xbfb39d9f12c5a299, // -0.99706, -0.076624 + 0xbfefe5f3af2e3940, 0xbfb4661179272096, // -0.99682, -0.079682 + 0xbfefe3e92be9d886, 0xbfb52e774a4d4d0a, // -0.99657, -0.08274 + 0xbfefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // -0.99631, -0.085797 + 0xbfefdf9922f73307, 0xbfb6bf1b3e79b129, // -0.99604, -0.088854 + 0xbfefdd539ff1f456, 0xbfb787586a5d5b21, // -0.99577, -0.091909 + 0xbfefdafa7514538c, 0xbfb84f8712c130a0, // -0.99548, -0.094963 + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518, -0.098017 + 0xbfefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // -0.99488, -0.10107 + 0xbfefd37914220b84, 0xbfbaa7b724495c04, // -0.99456, -0.10412 + 0xbfefd0d158d86087, 0xbfbb6fa6ec38f64c, // -0.99424, -0.10717 + 0xbfefce15fd6da67b, 0xbfbc3785c79ec2d5, // -0.99391, -0.11022 + 0xbfefcb4703914354, 0xbfbcff533b307dc1, // -0.99356, -0.11327 + 0xbfefc8646cfeb721, 0xbfbdc70ecbae9fc8, // -0.99321, -0.11632 + 0xbfefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // -0.99285, -0.11937 + 0xbfefc26470e19fd3, 0xbfbf564e56a9730e, // -0.99248, -0.12241 + 0xbfefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // -0.9921, -0.12545 + 0xbfefbc1617e44186, 0xbfc072a047ba831d, // -0.99171, -0.1285 + 0xbfefb8d18d66adb7, 0xbfc0d64dbcb26786, // -0.99131, -0.13154 + 0xbfefb5797195d741, 0xbfc139f0cedaf576, // -0.9909, -0.13458 + 0xbfefb20dc681d54d, 0xbfc19d8940be24e7, // -0.99049, -0.13762 + 0xbfefae8e8e46cfbb, 0xbfc20116d4ec7bce, // -0.99006, -0.14066 + 0xbfefaafbcb0cfddc, 0xbfc264994dfd340a, // -0.98962, -0.1437 + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673 + 0xbfefa39bac7a1791, 0xbfc32b7bf94516a7, // -0.98872, -0.14976 + 0xbfef9fce55adb2c8, 0xbfc38edbb0cd8d14, // -0.98826, -0.1528 + 0xbfef9bed7cfbde29, 0xbfc3f22f57db4893, // -0.98778, -0.15583 + 0xbfef97f924c9099b, 0xbfc45576b1293e5a, // -0.9873, -0.15886 + 0xbfef93f14f85ac08, 0xbfc4b8b17f79fa88, // -0.98681, -0.16189 + 0xbfef8fd5ffae41db, 0xbfc51bdf8597c5f2, // -0.98631, -0.16491 + 0xbfef8ba737cb4b78, 0xbfc57f008654cbde, // -0.9858, -0.16794 + 0xbfef8764fa714ba9, 0xbfc5e214448b3fc6, // -0.98528, -0.17096 + 0xbfef830f4a40c60c, 0xbfc6451a831d830d, // -0.98475, -0.17398 + 0xbfef7ea629e63d6e, 0xbfc6a81304f64ab2, // -0.98421, -0.177 + 0xbfef7a299c1a322a, 0xbfc70afd8d08c4ff, // -0.98366, -0.18002 + 0xbfef7599a3a12077, 0xbfc76dd9de50bf31, // -0.98311, -0.18304 + 0xbfef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // -0.98254, -0.18606 + 0xbfef6c3f7df5bbb7, 0xbfc83366e89c64c5, // -0.98196, -0.18907 + 0xbfef677556883cee, 0xbfc8961727c41804, // -0.98138, -0.19208 + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509 + 0xbfef5da6ed43685d, 0xbfc95b49e9b62af9, // -0.98018, -0.1981 + 0xbfef58a2b1789e84, 0xbfc9bdcbf2dc4366, // -0.97957, -0.2011 + 0xbfef538b1faf2d07, 0xbfca203e1b1831da, // -0.97895, -0.20411 + 0xbfef4e603b0b2f2d, 0xbfca82a025b00451, // -0.97832, -0.20711 + 0xbfef492206bcabb4, 0xbfcae4f1d5f3b9ab, // -0.97768, -0.21011 + 0xbfef43d085ff92dd, 0xbfcb4732ef3d6722, // -0.97703, -0.21311 + 0xbfef3e6bbc1bbc65, 0xbfcba96334f15dad, // -0.97637, -0.21611 + 0xbfef38f3ac64e589, 0xbfcc0b826a7e4f63, // -0.9757, -0.2191 + 0xbfef33685a3aaef0, 0xbfcc6d90535d74dc, // -0.97503, -0.22209 + 0xbfef2dc9c9089a9d, 0xbfcccf8cb312b286, // -0.97434, -0.22508 + 0xbfef2817fc4609ce, 0xbfcd31774d2cbdee, // -0.97364, -0.22807 + 0xbfef2252f7763ada, 0xbfcd934fe5454311, // -0.97294, -0.23106 + 0xbfef1c7abe284708, 0xbfcdf5163f01099a, // -0.97223, -0.23404 + 0xbfef168f53f7205d, 0xbfce56ca1e101a1b, // -0.9715, -0.23702 + 0xbfef1090bc898f5f, 0xbfceb86b462de348, // -0.97077, -0.24 + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298 + 0xbfef045a14cf738c, 0xbfcf7b7480bd3801, // -0.96928, -0.24596 + 0xbfeefe220c0b95ec, 0xbfcfdcdc1adfedf8, // -0.96852, -0.24893 + 0xbfeef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // -0.96775, -0.2519 + 0xbfeef178a3e473c2, 0xbfd04fb80e37fdae, // -0.96698, -0.25487 + 0xbfeeeb074c50a544, 0xbfd0804e05eb661e, // -0.96619, -0.25783 + 0xbfeee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // -0.96539, -0.26079 + 0xbfeeddeb6a078651, 0xbfd0e15b4e1749cd, // -0.96459, -0.26375 + 0xbfeed740e7684963, 0xbfd111d262b1f677, // -0.96378, -0.26671 + 0xbfeed0835e999009, 0xbfd1423eefc69378, // -0.96295, -0.26967 + 0xbfeec9b2d3c3bf84, 0xbfd172a0d7765177, // -0.96212, -0.27262 + 0xbfeec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // -0.96128, -0.27557 + 0xbfeebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // -0.96043, -0.27852 + 0xbfeeb4cf515b8811, 0xbfd2038583d727bd, // -0.95957, -0.28146 + 0xbfeeadb2e8e7a88e, 0xbfd233bbabc3bb72, // -0.9587, -0.28441 + 0xbfeea68393e65800, 0xbfd263e6995554ba, // -0.95783, -0.28735 + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028 + 0xbfee97ec36016b30, 0xbfd2c41a4e954520, // -0.95605, -0.29322 + 0xbfee9084361df7f3, 0xbfd2f422daec0386, // -0.95514, -0.29615 + 0xbfee89095bad6025, 0xbfd3241fb638baaf, // -0.95423, -0.29908 + 0xbfee817bab4cd10d, 0xbfd35410c2e18152, // -0.95331, -0.30201 + 0xbfee79db29a5165a, 0xbfd383f5e353b6aa, // -0.95238, -0.30493 + 0xbfee7227db6a9744, 0xbfd3b3cefa0414b7, // -0.95144, -0.30785 + 0xbfee6a61c55d53a7, 0xbfd3e39be96ec271, // -0.95049, -0.31077 + 0xbfee6288ec48e112, 0xbfd4135c94176602, // -0.94953, -0.31368 + 0xbfee5a9d550467d3, 0xbfd44310dc8936f0, // -0.94856, -0.31659 + 0xbfee529f04729ffc, 0xbfd472b8a5571054, // -0.94759, -0.3195 + 0xbfee4a8dff81ce5e, 0xbfd4a253d11b82f3, // -0.9466, -0.32241 + 0xbfee426a4b2bc17e, 0xbfd4d1e24278e76a, // -0.94561, -0.32531 + 0xbfee3a33ec75ce85, 0xbfd50163dc197047, // -0.9446, -0.32821 + 0xbfee31eae870ce25, 0xbfd530d880af3c24, // -0.94359, -0.33111 + 0xbfee298f4439197a, 0xbfd5604012f467b4, // -0.94257, -0.334 + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689 + 0xbfee18a02fdc66d9, 0xbfd5bee78b9db3b6, // -0.94051, -0.33978 + 0xbfee100cca2980ac, 0xbfd5ee27379ea693, // -0.93946, -0.34266 + 0xbfee0766d9280f54, 0xbfd61d595c88c203, // -0.9384, -0.34554 + 0xbfedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // -0.93734, -0.34842 + 0xbfedf5e36a9ba59c, 0xbfd67b949cad63ca, // -0.93627, -0.35129 + 0xbfeded05f7de47da, 0xbfd6aa9d7dc77e16, // -0.93518, -0.35416 + 0xbfede4160f6d8d81, 0xbfd6d998638a0cb5, // -0.93409, -0.35703 + 0xbfeddb13b6ccc23d, 0xbfd7088530fa459e, // -0.93299, -0.3599 + 0xbfedd1fef38a915a, 0xbfd73763c9261092, // -0.93188, -0.36276 + 0xbfedc8d7cb410260, 0xbfd766340f2418f6, // -0.93077, -0.36561 + 0xbfedbf9e4395759a, 0xbfd794f5e613dfae, // -0.92964, -0.36847 + 0xbfedb6526238a09b, 0xbfd7c3a9311dcce7, // -0.92851, -0.37132 + 0xbfedacf42ce68ab9, 0xbfd7f24dd37341e3, // -0.92736, -0.37416 + 0xbfeda383a9668988, 0xbfd820e3b04eaac4, // -0.92621, -0.37701 + 0xbfed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // -0.92505, -0.37985 + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268 + 0xbfed86c48445a450, 0xbfd8ac4b86d5ed44, // -0.9227, -0.38552 + 0xbfed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // -0.92151, -0.38835 + 0xbfed733f508c0dff, 0xbfd908ef81ef7bd1, // -0.92032, -0.39117 + 0xbfed696173c9e68b, 0xbfd9372a63bc93d7, // -0.91911, -0.39399 + 0xbfed5f7172888a7f, 0xbfd96555b7ab948f, // -0.9179, -0.39681 + 0xbfed556f52e93eb1, 0xbfd993716141bdfe, // -0.91668, -0.39962 + 0xbfed4b5b1b187524, 0xbfd9c17d440df9f2, // -0.91545, -0.40243 + 0xbfed4134d14dc93a, 0xbfd9ef7943a8ed8a, // -0.91421, -0.40524 + 0xbfed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // -0.91296, -0.40804 + 0xbfed2cb220e0ef9f, 0xbfda4b4127dea1e4, // -0.91171, -0.41084 + 0xbfed2255c6e5a4e1, 0xbfda790cd3dbf31a, // -0.91044, -0.41364 + 0xbfed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // -0.90917, -0.41643 + 0xbfed0d672f59d2b9, 0xbfdad473125cdc08, // -0.90789, -0.41922 + 0xbfed02d4feb2bd92, 0xbfdb020d6c7f4009, // -0.9066, -0.422 + 0xbfecf830e8ce467b, 0xbfdb2f971db31972, // -0.9053, -0.42478 + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756 + 0xbfece2b32799a060, 0xbfdb8a7814fd5693, // -0.90267, -0.43033 + 0xbfecd7d9898b32f6, 0xbfdbb7cf2304bd01, // -0.90135, -0.43309 + 0xbfecccee20c2de9f, 0xbfdbe51517ffc0d9, // -0.90002, -0.43586 + 0xbfecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // -0.89867, -0.43862 + 0xbfecb6e20a00da99, 0xbfdc3f6d47263129, // -0.89732, -0.44137 + 0xbfecabc169a0b901, 0xbfdc6c7f4997000a, // -0.89597, -0.44412 + 0xbfeca08f19b9c449, 0xbfdc997fc3865388, // -0.8946, -0.44687 + 0xbfec954b213411f5, 0xbfdcc66e9931c45d, // -0.89322, -0.44961 + 0xbfec89f587029c13, 0xbfdcf34baee1cd21, // -0.89184, -0.45235 + 0xbfec7e8e52233cf3, 0xbfdd2016e8e9db5b, // -0.89045, -0.45508 + 0xbfec7315899eaad7, 0xbfdd4cd02ba8609c, // -0.88905, -0.45781 + 0xbfec678b3488739b, 0xbfdd79775b86e389, // -0.88764, -0.46054 + 0xbfec5bef59fef85a, 0xbfdda60c5cfa10d8, // -0.88622, -0.46326 + 0xbfec5042012b6907, 0xbfddd28f1481cc58, // -0.8848, -0.46598 + 0xbfec44833141c004, 0xbfddfeff66a941de, // -0.88336, -0.46869 + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714 + 0xbfec2cd14931e3f1, 0xbfde57a86d3cd824, // -0.88047, -0.4741 + 0xbfec20de3fa971b0, 0xbfde83e0eaf85113, // -0.87901, -0.4768 + 0xbfec14d9dc465e58, 0xbfdeb00695f25620, // -0.87755, -0.47949 + 0xbfec08c426725549, 0xbfdedc1952ef78d5, // -0.87607, -0.48218 + 0xbfebfc9d25a1b147, 0xbfdf081906bff7fd, // -0.87459, -0.48487 + 0xbfebf064e15377dd, 0xbfdf3405963fd068, // -0.87309, -0.48755 + 0xbfebe41b611154c1, 0xbfdf5fdee656cda3, // -0.8716, -0.49023 + 0xbfebd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // -0.87009, -0.4929 + 0xbfebcb54cb0d2327, 0xbfdfb7575c24d2de, // -0.86857, -0.49557 + 0xbfebbed7c49380ea, 0xbfdfe2f64be7120f, // -0.86705, -0.49823 + 0xbfebb249a0b6c40d, 0xbfe00740c82b82e0, // -0.86551, -0.50089 + 0xbfeba5aa673590d2, 0xbfe01cfc874c3eb7, // -0.86397, -0.50354 + 0xbfeb98fa1fd9155e, 0xbfe032ae55edbd95, // -0.86242, -0.50619 + 0xbfeb8c38d27504e9, 0xbfe0485626ae221a, // -0.86087, -0.50883 + 0xbfeb7f6686e792ea, 0xbfe05df3ec31b8b6, // -0.8593, -0.51147 + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141 + 0xbfeb658f14fdbc47, 0xbfe089112032b08c, // -0.85615, -0.51673 + 0xbfeb5889fe921405, 0xbfe09e907417c5e1, // -0.85456, -0.51936 + 0xbfeb4b7409de7925, 0xbfe0b405878f85ec, // -0.85296, -0.52198 + 0xbfeb3e4d3ef55712, 0xbfe0c9704d5d898f, // -0.85136, -0.52459 + 0xbfeb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // -0.84974, -0.5272 + 0xbfeb23cd470013b4, 0xbfe0f426bb2a8e7d, // -0.84812, -0.5298 + 0xbfeb16742a4ca2f5, 0xbfe1097248d0a956, // -0.84649, -0.5324 + 0xbfeb090a58150200, 0xbfe11eb3541b4b22, // -0.84485, -0.535 + 0xbfeafb8fd89f57b6, 0xbfe133e9cfee254e, // -0.84321, -0.53759 + 0xbfeaee04b43c1474, 0xbfe14915af336ceb, // -0.84155, -0.54017 + 0xbfeae068f345ecef, 0xbfe15e36e4dbe2bc, // -0.83989, -0.54275 + 0xbfead2bc9e21d511, 0xbfe1734d63dedb49, // -0.83822, -0.54532 + 0xbfeac4ffbd3efac8, 0xbfe188591f3a46e5, // -0.83655, -0.54789 + 0xbfeab7325916c0d4, 0xbfe19d5a09f2b9b8, // -0.83486, -0.55046 + 0xbfeaa9547a2cb98e, 0xbfe1b250171373be, // -0.83317, -0.55302 + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557 + 0xbfea8d676e545ad2, 0xbfe1dc1b64dc4872, // -0.82976, -0.55812 + 0xbfea7f58529fe69d, 0xbfe1f0f08bbc861b, // -0.82805, -0.56066 + 0xbfea7138de9d60f5, 0xbfe205baa17560d6, // -0.82632, -0.5632 + 0xbfea63091b02fae2, 0xbfe21a799933eb58, // -0.82459, -0.56573 + 0xbfea54c91090f524, 0xbfe22f2d662c13e1, // -0.82285, -0.56826 + 0xbfea4678c8119ac8, 0xbfe243d5fb98ac1f, // -0.8211, -0.57078 + 0xbfea38184a593bc6, 0xbfe258734cbb7110, // -0.81935, -0.5733 + 0xbfea29a7a0462782, 0xbfe26d054cdd12df, // -0.81758, -0.57581 + 0xbfea1b26d2c0a75e, 0xbfe2818bef4d3cba, // -0.81581, -0.57831 + 0xbfea0c95eabaf937, 0xbfe2960727629ca8, // -0.81404, -0.58081 + 0xbfe9fdf4f13149de, 0xbfe2aa76e87aeb58, // -0.81225, -0.58331 + 0xbfe9ef43ef29af94, 0xbfe2bedb25faf3ea, // -0.81046, -0.5858 + 0xbfe9e082edb42472, 0xbfe2d333d34e9bb7, // -0.80866, -0.58828 + 0xbfe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // -0.80685, -0.59076 + 0xbfe9c2d110f075c3, 0xbfe2fbc24b441015, // -0.80503, -0.59323 + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957 + 0xbfe9a4dfa42b06b2, 0xbfe32421ec49a620, // -0.80138, -0.59816 + 0xbfe995cf2ed80d22, 0xbfe338400d0c8e57, // -0.79954, -0.60062 + 0xbfe986aef1457594, 0xbfe34c5252c14de1, // -0.79769, -0.60307 + 0xbfe9777ef4c7d742, 0xbfe36058b10659f3, // -0.79584, -0.60551 + 0xbfe9683f42bd7fe1, 0xbfe374531b817f8d, // -0.79398, -0.60795 + 0xbfe958efe48e6dd7, 0xbfe3884185dfeb22, // -0.79211, -0.61038 + 0xbfe94990e3ac4a6c, 0xbfe39c23e3d63029, // -0.79023, -0.61281 + 0xbfe93a22499263fc, 0xbfe3affa292050b9, // -0.78835, -0.61523 + 0xbfe92aa41fc5a815, 0xbfe3c3c44981c517, // -0.78646, -0.61765 + 0xbfe91b166fd49da2, 0xbfe3d78238c58343, // -0.78456, -0.62006 + 0xbfe90b7943575efe, 0xbfe3eb33eabe0680, // -0.78265, -0.62246 + 0xbfe8fbcca3ef940d, 0xbfe3fed9534556d4, // -0.78074, -0.62486 + 0xbfe8ec109b486c49, 0xbfe41272663d108c, // -0.77882, -0.62725 + 0xbfe8dc45331698cc, 0xbfe425ff178e6bb1, // -0.77689, -0.62964 + 0xbfe8cc6a75184655, 0xbfe4397f5b2a4380, // -0.77495, -0.63202 + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439 + 0xbfe8ac871ede1d88, 0xbfe4605a692b32a2, // -0.77106, -0.63676 + 0xbfe89c7e9a4dd4ab, 0xbfe473b51b987347, // -0.7691, -0.63912 + 0xbfe88c66e7481ba1, 0xbfe48703306091fe, // -0.76714, -0.64148 + 0xbfe87c400fba2ebf, 0xbfe49a449b9b0938, // -0.76517, -0.64383 + 0xbfe86c0a1d9aa195, 0xbfe4ad79516722f0, // -0.76319, -0.64618 + 0xbfe85bc51ae958cc, 0xbfe4c0a145ec0004, // -0.7612, -0.64851 + 0xbfe84b7111af83f9, 0xbfe4d3bc6d589f80, // -0.75921, -0.65085 + 0xbfe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // -0.75721, -0.65317 + 0xbfe82a9c13f545ff, 0xbfe4f9cc25cca486, // -0.7552, -0.65549 + 0xbfe81a1b33b57acc, 0xbfe50cc09f59a09b, // -0.75319, -0.65781 + 0xbfe8098b756e52fa, 0xbfe51fa81cd99aa6, // -0.75117, -0.66011 + 0xbfe7f8ece3571771, 0xbfe5328292a35596, // -0.74914, -0.66242 + 0xbfe7e83f87b03686, 0xbfe5454ff5159dfb, // -0.7471, -0.66471 + 0xbfe7d7836cc33db2, 0xbfe5581038975137, // -0.74506, -0.667 + 0xbfe7c6b89ce2d333, 0xbfe56ac35197649e, // -0.74301, -0.66928 + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156 + 0xbfe7a4f707bf97d2, 0xbfe59001d5f723df, // -0.73889, -0.67383 + 0xbfe79400574f55e4, 0xbfe5a28d2a5d7250, // -0.73682, -0.67609 + 0xbfe782fb1b90b35b, 0xbfe5b50b264f7448, // -0.73474, -0.67835 + 0xbfe771e75f037261, 0xbfe5c77bbe65018c, // -0.73265, -0.6806 + 0xbfe760c52c304764, 0xbfe5d9dee73e345c, // -0.73056, -0.68285 + 0xbfe74f948da8d28d, 0xbfe5ec3495837074, // -0.72846, -0.68508 + 0xbfe73e558e079942, 0xbfe5fe7cbde56a0f, // -0.72636, -0.68732 + 0xbfe72d0837efff97, 0xbfe610b7551d2cde, // -0.72425, -0.68954 + 0xbfe71bac960e41bf, 0xbfe622e44fec22ff, // -0.72213, -0.69176 + 0xbfe70a42b3176d7a, 0xbfe63503a31c1be8, // -0.72, -0.69397 + 0xbfe6f8ca99c95b75, 0xbfe64715437f535b, // -0.71787, -0.69618 + 0xbfe6e74454eaa8ae, 0xbfe6591925f0783e, // -0.71573, -0.69838 + 0xbfe6d5afef4aafcc, 0xbfe66b0f3f52b386, // -0.71358, -0.70057 + 0xbfe6c40d73c18275, 0xbfe67cf78491af10, // -0.71143, -0.70275 + 0xbfe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // -0.70927, -0.70493 + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711 + 0xbfe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // -0.70493, -0.70927 + 0xbfe67cf78491af10, 0xbfe6c40d73c18275, // -0.70275, -0.71143 + 0xbfe66b0f3f52b386, 0xbfe6d5afef4aafcc, // -0.70057, -0.71358 + 0xbfe6591925f0783e, 0xbfe6e74454eaa8ae, // -0.69838, -0.71573 + 0xbfe64715437f535b, 0xbfe6f8ca99c95b75, // -0.69618, -0.71787 + 0xbfe63503a31c1be8, 0xbfe70a42b3176d7a, // -0.69397, -0.72 + 0xbfe622e44fec22ff, 0xbfe71bac960e41bf, // -0.69176, -0.72213 + 0xbfe610b7551d2cde, 0xbfe72d0837efff97, // -0.68954, -0.72425 + 0xbfe5fe7cbde56a0f, 0xbfe73e558e079942, // -0.68732, -0.72636 + 0xbfe5ec3495837074, 0xbfe74f948da8d28d, // -0.68508, -0.72846 + 0xbfe5d9dee73e345c, 0xbfe760c52c304764, // -0.68285, -0.73056 + 0xbfe5c77bbe65018c, 0xbfe771e75f037261, // -0.6806, -0.73265 + 0xbfe5b50b264f7448, 0xbfe782fb1b90b35b, // -0.67835, -0.73474 + 0xbfe5a28d2a5d7250, 0xbfe79400574f55e4, // -0.67609, -0.73682 + 0xbfe59001d5f723df, 0xbfe7a4f707bf97d2, // -0.67383, -0.73889 + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095 + 0xbfe56ac35197649e, 0xbfe7c6b89ce2d333, // -0.66928, -0.74301 + 0xbfe5581038975137, 0xbfe7d7836cc33db2, // -0.667, -0.74506 + 0xbfe5454ff5159dfb, 0xbfe7e83f87b03686, // -0.66471, -0.7471 + 0xbfe5328292a35596, 0xbfe7f8ece3571771, // -0.66242, -0.74914 + 0xbfe51fa81cd99aa6, 0xbfe8098b756e52fa, // -0.66011, -0.75117 + 0xbfe50cc09f59a09b, 0xbfe81a1b33b57acc, // -0.65781, -0.75319 + 0xbfe4f9cc25cca486, 0xbfe82a9c13f545ff, // -0.65549, -0.7552 + 0xbfe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // -0.65317, -0.75721 + 0xbfe4d3bc6d589f80, 0xbfe84b7111af83f9, // -0.65085, -0.75921 + 0xbfe4c0a145ec0004, 0xbfe85bc51ae958cc, // -0.64851, -0.7612 + 0xbfe4ad79516722f0, 0xbfe86c0a1d9aa195, // -0.64618, -0.76319 + 0xbfe49a449b9b0938, 0xbfe87c400fba2ebf, // -0.64383, -0.76517 + 0xbfe48703306091fe, 0xbfe88c66e7481ba1, // -0.64148, -0.76714 + 0xbfe473b51b987347, 0xbfe89c7e9a4dd4ab, // -0.63912, -0.7691 + 0xbfe4605a692b32a2, 0xbfe8ac871ede1d88, // -0.63676, -0.77106 + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301 + 0xbfe4397f5b2a4380, 0xbfe8cc6a75184655, // -0.63202, -0.77495 + 0xbfe425ff178e6bb1, 0xbfe8dc45331698cc, // -0.62964, -0.77689 + 0xbfe41272663d108c, 0xbfe8ec109b486c49, // -0.62725, -0.77882 + 0xbfe3fed9534556d4, 0xbfe8fbcca3ef940d, // -0.62486, -0.78074 + 0xbfe3eb33eabe0680, 0xbfe90b7943575efe, // -0.62246, -0.78265 + 0xbfe3d78238c58343, 0xbfe91b166fd49da2, // -0.62006, -0.78456 + 0xbfe3c3c44981c517, 0xbfe92aa41fc5a815, // -0.61765, -0.78646 + 0xbfe3affa292050b9, 0xbfe93a22499263fc, // -0.61523, -0.78835 + 0xbfe39c23e3d63029, 0xbfe94990e3ac4a6c, // -0.61281, -0.79023 + 0xbfe3884185dfeb22, 0xbfe958efe48e6dd7, // -0.61038, -0.79211 + 0xbfe374531b817f8d, 0xbfe9683f42bd7fe1, // -0.60795, -0.79398 + 0xbfe36058b10659f3, 0xbfe9777ef4c7d742, // -0.60551, -0.79584 + 0xbfe34c5252c14de1, 0xbfe986aef1457594, // -0.60307, -0.79769 + 0xbfe338400d0c8e57, 0xbfe995cf2ed80d22, // -0.60062, -0.79954 + 0xbfe32421ec49a620, 0xbfe9a4dfa42b06b2, // -0.59816, -0.80138 + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321 + 0xbfe2fbc24b441015, 0xbfe9c2d110f075c3, // -0.59323, -0.80503 + 0xbfe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // -0.59076, -0.80685 + 0xbfe2d333d34e9bb7, 0xbfe9e082edb42472, // -0.58828, -0.80866 + 0xbfe2bedb25faf3ea, 0xbfe9ef43ef29af94, // -0.5858, -0.81046 + 0xbfe2aa76e87aeb58, 0xbfe9fdf4f13149de, // -0.58331, -0.81225 + 0xbfe2960727629ca8, 0xbfea0c95eabaf937, // -0.58081, -0.81404 + 0xbfe2818bef4d3cba, 0xbfea1b26d2c0a75e, // -0.57831, -0.81581 + 0xbfe26d054cdd12df, 0xbfea29a7a0462782, // -0.57581, -0.81758 + 0xbfe258734cbb7110, 0xbfea38184a593bc6, // -0.5733, -0.81935 + 0xbfe243d5fb98ac1f, 0xbfea4678c8119ac8, // -0.57078, -0.8211 + 0xbfe22f2d662c13e1, 0xbfea54c91090f524, // -0.56826, -0.82285 + 0xbfe21a799933eb58, 0xbfea63091b02fae2, // -0.56573, -0.82459 + 0xbfe205baa17560d6, 0xbfea7138de9d60f5, // -0.5632, -0.82632 + 0xbfe1f0f08bbc861b, 0xbfea7f58529fe69d, // -0.56066, -0.82805 + 0xbfe1dc1b64dc4872, 0xbfea8d676e545ad2, // -0.55812, -0.82976 + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147 + 0xbfe1b250171373be, 0xbfeaa9547a2cb98e, // -0.55302, -0.83317 + 0xbfe19d5a09f2b9b8, 0xbfeab7325916c0d4, // -0.55046, -0.83486 + 0xbfe188591f3a46e5, 0xbfeac4ffbd3efac8, // -0.54789, -0.83655 + 0xbfe1734d63dedb49, 0xbfead2bc9e21d511, // -0.54532, -0.83822 + 0xbfe15e36e4dbe2bc, 0xbfeae068f345ecef, // -0.54275, -0.83989 + 0xbfe14915af336ceb, 0xbfeaee04b43c1474, // -0.54017, -0.84155 + 0xbfe133e9cfee254e, 0xbfeafb8fd89f57b6, // -0.53759, -0.84321 + 0xbfe11eb3541b4b22, 0xbfeb090a58150200, // -0.535, -0.84485 + 0xbfe1097248d0a956, 0xbfeb16742a4ca2f5, // -0.5324, -0.84649 + 0xbfe0f426bb2a8e7d, 0xbfeb23cd470013b4, // -0.5298, -0.84812 + 0xbfe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // -0.5272, -0.84974 + 0xbfe0c9704d5d898f, 0xbfeb3e4d3ef55712, // -0.52459, -0.85136 + 0xbfe0b405878f85ec, 0xbfeb4b7409de7925, // -0.52198, -0.85296 + 0xbfe09e907417c5e1, 0xbfeb5889fe921405, // -0.51936, -0.85456 + 0xbfe089112032b08c, 0xbfeb658f14fdbc47, // -0.51673, -0.85615 + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773 + 0xbfe05df3ec31b8b6, 0xbfeb7f6686e792ea, // -0.51147, -0.8593 + 0xbfe0485626ae221a, 0xbfeb8c38d27504e9, // -0.50883, -0.86087 + 0xbfe032ae55edbd95, 0xbfeb98fa1fd9155e, // -0.50619, -0.86242 + 0xbfe01cfc874c3eb7, 0xbfeba5aa673590d2, // -0.50354, -0.86397 + 0xbfe00740c82b82e0, 0xbfebb249a0b6c40d, // -0.50089, -0.86551 + 0xbfdfe2f64be7120f, 0xbfebbed7c49380ea, // -0.49823, -0.86705 + 0xbfdfb7575c24d2de, 0xbfebcb54cb0d2327, // -0.49557, -0.86857 + 0xbfdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // -0.4929, -0.87009 + 0xbfdf5fdee656cda3, 0xbfebe41b611154c1, // -0.49023, -0.8716 + 0xbfdf3405963fd068, 0xbfebf064e15377dd, // -0.48755, -0.87309 + 0xbfdf081906bff7fd, 0xbfebfc9d25a1b147, // -0.48487, -0.87459 + 0xbfdedc1952ef78d5, 0xbfec08c426725549, // -0.48218, -0.87607 + 0xbfdeb00695f25620, 0xbfec14d9dc465e58, // -0.47949, -0.87755 + 0xbfde83e0eaf85113, 0xbfec20de3fa971b0, // -0.4768, -0.87901 + 0xbfde57a86d3cd824, 0xbfec2cd14931e3f1, // -0.4741, -0.88047 + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192 + 0xbfddfeff66a941de, 0xbfec44833141c004, // -0.46869, -0.88336 + 0xbfddd28f1481cc58, 0xbfec5042012b6907, // -0.46598, -0.8848 + 0xbfdda60c5cfa10d8, 0xbfec5bef59fef85a, // -0.46326, -0.88622 + 0xbfdd79775b86e389, 0xbfec678b3488739b, // -0.46054, -0.88764 + 0xbfdd4cd02ba8609c, 0xbfec7315899eaad7, // -0.45781, -0.88905 + 0xbfdd2016e8e9db5b, 0xbfec7e8e52233cf3, // -0.45508, -0.89045 + 0xbfdcf34baee1cd21, 0xbfec89f587029c13, // -0.45235, -0.89184 + 0xbfdcc66e9931c45d, 0xbfec954b213411f5, // -0.44961, -0.89322 + 0xbfdc997fc3865388, 0xbfeca08f19b9c449, // -0.44687, -0.8946 + 0xbfdc6c7f4997000a, 0xbfecabc169a0b901, // -0.44412, -0.89597 + 0xbfdc3f6d47263129, 0xbfecb6e20a00da99, // -0.44137, -0.89732 + 0xbfdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // -0.43862, -0.89867 + 0xbfdbe51517ffc0d9, 0xbfecccee20c2de9f, // -0.43586, -0.90002 + 0xbfdbb7cf2304bd01, 0xbfecd7d9898b32f6, // -0.43309, -0.90135 + 0xbfdb8a7814fd5693, 0xbfece2b32799a060, // -0.43033, -0.90267 + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399 + 0xbfdb2f971db31972, 0xbfecf830e8ce467b, // -0.42478, -0.9053 + 0xbfdb020d6c7f4009, 0xbfed02d4feb2bd92, // -0.422, -0.9066 + 0xbfdad473125cdc08, 0xbfed0d672f59d2b9, // -0.41922, -0.90789 + 0xbfdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // -0.41643, -0.90917 + 0xbfda790cd3dbf31a, 0xbfed2255c6e5a4e1, // -0.41364, -0.91044 + 0xbfda4b4127dea1e4, 0xbfed2cb220e0ef9f, // -0.41084, -0.91171 + 0xbfda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // -0.40804, -0.91296 + 0xbfd9ef7943a8ed8a, 0xbfed4134d14dc93a, // -0.40524, -0.91421 + 0xbfd9c17d440df9f2, 0xbfed4b5b1b187524, // -0.40243, -0.91545 + 0xbfd993716141bdfe, 0xbfed556f52e93eb1, // -0.39962, -0.91668 + 0xbfd96555b7ab948f, 0xbfed5f7172888a7f, // -0.39681, -0.9179 + 0xbfd9372a63bc93d7, 0xbfed696173c9e68b, // -0.39399, -0.91911 + 0xbfd908ef81ef7bd1, 0xbfed733f508c0dff, // -0.39117, -0.92032 + 0xbfd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // -0.38835, -0.92151 + 0xbfd8ac4b86d5ed44, 0xbfed86c48445a450, // -0.38552, -0.9227 + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388 + 0xbfd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // -0.37985, -0.92505 + 0xbfd820e3b04eaac4, 0xbfeda383a9668988, // -0.37701, -0.92621 + 0xbfd7f24dd37341e3, 0xbfedacf42ce68ab9, // -0.37416, -0.92736 + 0xbfd7c3a9311dcce7, 0xbfedb6526238a09b, // -0.37132, -0.92851 + 0xbfd794f5e613dfae, 0xbfedbf9e4395759a, // -0.36847, -0.92964 + 0xbfd766340f2418f6, 0xbfedc8d7cb410260, // -0.36561, -0.93077 + 0xbfd73763c9261092, 0xbfedd1fef38a915a, // -0.36276, -0.93188 + 0xbfd7088530fa459e, 0xbfeddb13b6ccc23d, // -0.3599, -0.93299 + 0xbfd6d998638a0cb5, 0xbfede4160f6d8d81, // -0.35703, -0.93409 + 0xbfd6aa9d7dc77e16, 0xbfeded05f7de47da, // -0.35416, -0.93518 + 0xbfd67b949cad63ca, 0xbfedf5e36a9ba59c, // -0.35129, -0.93627 + 0xbfd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // -0.34842, -0.93734 + 0xbfd61d595c88c203, 0xbfee0766d9280f54, // -0.34554, -0.9384 + 0xbfd5ee27379ea693, 0xbfee100cca2980ac, // -0.34266, -0.93946 + 0xbfd5bee78b9db3b6, 0xbfee18a02fdc66d9, // -0.33978, -0.94051 + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154 + 0xbfd5604012f467b4, 0xbfee298f4439197a, // -0.334, -0.94257 + 0xbfd530d880af3c24, 0xbfee31eae870ce25, // -0.33111, -0.94359 + 0xbfd50163dc197047, 0xbfee3a33ec75ce85, // -0.32821, -0.9446 + 0xbfd4d1e24278e76a, 0xbfee426a4b2bc17e, // -0.32531, -0.94561 + 0xbfd4a253d11b82f3, 0xbfee4a8dff81ce5e, // -0.32241, -0.9466 + 0xbfd472b8a5571054, 0xbfee529f04729ffc, // -0.3195, -0.94759 + 0xbfd44310dc8936f0, 0xbfee5a9d550467d3, // -0.31659, -0.94856 + 0xbfd4135c94176602, 0xbfee6288ec48e112, // -0.31368, -0.94953 + 0xbfd3e39be96ec271, 0xbfee6a61c55d53a7, // -0.31077, -0.95049 + 0xbfd3b3cefa0414b7, 0xbfee7227db6a9744, // -0.30785, -0.95144 + 0xbfd383f5e353b6aa, 0xbfee79db29a5165a, // -0.30493, -0.95238 + 0xbfd35410c2e18152, 0xbfee817bab4cd10d, // -0.30201, -0.95331 + 0xbfd3241fb638baaf, 0xbfee89095bad6025, // -0.29908, -0.95423 + 0xbfd2f422daec0386, 0xbfee9084361df7f3, // -0.29615, -0.95514 + 0xbfd2c41a4e954520, 0xbfee97ec36016b30, // -0.29322, -0.95605 + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694 + 0xbfd263e6995554ba, 0xbfeea68393e65800, // -0.28735, -0.95783 + 0xbfd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // -0.28441, -0.9587 + 0xbfd2038583d727bd, 0xbfeeb4cf515b8811, // -0.28146, -0.95957 + 0xbfd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // -0.27852, -0.96043 + 0xbfd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // -0.27557, -0.96128 + 0xbfd172a0d7765177, 0xbfeec9b2d3c3bf84, // -0.27262, -0.96212 + 0xbfd1423eefc69378, 0xbfeed0835e999009, // -0.26967, -0.96295 + 0xbfd111d262b1f677, 0xbfeed740e7684963, // -0.26671, -0.96378 + 0xbfd0e15b4e1749cd, 0xbfeeddeb6a078651, // -0.26375, -0.96459 + 0xbfd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // -0.26079, -0.96539 + 0xbfd0804e05eb661e, 0xbfeeeb074c50a544, // -0.25783, -0.96619 + 0xbfd04fb80e37fdae, 0xbfeef178a3e473c2, // -0.25487, -0.96698 + 0xbfd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // -0.2519, -0.96775 + 0xbfcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // -0.24893, -0.96852 + 0xbfcf7b7480bd3801, 0xbfef045a14cf738c, // -0.24596, -0.96928 + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003 + 0xbfceb86b462de348, 0xbfef1090bc898f5f, // -0.24, -0.97077 + 0xbfce56ca1e101a1b, 0xbfef168f53f7205d, // -0.23702, -0.9715 + 0xbfcdf5163f01099a, 0xbfef1c7abe284708, // -0.23404, -0.97223 + 0xbfcd934fe5454311, 0xbfef2252f7763ada, // -0.23106, -0.97294 + 0xbfcd31774d2cbdee, 0xbfef2817fc4609ce, // -0.22807, -0.97364 + 0xbfcccf8cb312b286, 0xbfef2dc9c9089a9d, // -0.22508, -0.97434 + 0xbfcc6d90535d74dc, 0xbfef33685a3aaef0, // -0.22209, -0.97503 + 0xbfcc0b826a7e4f63, 0xbfef38f3ac64e589, // -0.2191, -0.9757 + 0xbfcba96334f15dad, 0xbfef3e6bbc1bbc65, // -0.21611, -0.97637 + 0xbfcb4732ef3d6722, 0xbfef43d085ff92dd, // -0.21311, -0.97703 + 0xbfcae4f1d5f3b9ab, 0xbfef492206bcabb4, // -0.21011, -0.97768 + 0xbfca82a025b00451, 0xbfef4e603b0b2f2d, // -0.20711, -0.97832 + 0xbfca203e1b1831da, 0xbfef538b1faf2d07, // -0.20411, -0.97895 + 0xbfc9bdcbf2dc4366, 0xbfef58a2b1789e84, // -0.2011, -0.97957 + 0xbfc95b49e9b62af9, 0xbfef5da6ed43685d, // -0.1981, -0.98018 + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079 + 0xbfc8961727c41804, 0xbfef677556883cee, // -0.19208, -0.98138 + 0xbfc83366e89c64c5, 0xbfef6c3f7df5bbb7, // -0.18907, -0.98196 + 0xbfc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // -0.18606, -0.98254 + 0xbfc76dd9de50bf31, 0xbfef7599a3a12077, // -0.18304, -0.98311 + 0xbfc70afd8d08c4ff, 0xbfef7a299c1a322a, // -0.18002, -0.98366 + 0xbfc6a81304f64ab2, 0xbfef7ea629e63d6e, // -0.177, -0.98421 + 0xbfc6451a831d830d, 0xbfef830f4a40c60c, // -0.17398, -0.98475 + 0xbfc5e214448b3fc6, 0xbfef8764fa714ba9, // -0.17096, -0.98528 + 0xbfc57f008654cbde, 0xbfef8ba737cb4b78, // -0.16794, -0.9858 + 0xbfc51bdf8597c5f2, 0xbfef8fd5ffae41db, // -0.16491, -0.98631 + 0xbfc4b8b17f79fa88, 0xbfef93f14f85ac08, // -0.16189, -0.98681 + 0xbfc45576b1293e5a, 0xbfef97f924c9099b, // -0.15886, -0.9873 + 0xbfc3f22f57db4893, 0xbfef9bed7cfbde29, // -0.15583, -0.98778 + 0xbfc38edbb0cd8d14, 0xbfef9fce55adb2c8, // -0.1528, -0.98826 + 0xbfc32b7bf94516a7, 0xbfefa39bac7a1791, // -0.14976, -0.98872 + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918 + 0xbfc264994dfd340a, 0xbfefaafbcb0cfddc, // -0.1437, -0.98962 + 0xbfc20116d4ec7bce, 0xbfefae8e8e46cfbb, // -0.14066, -0.99006 + 0xbfc19d8940be24e7, 0xbfefb20dc681d54d, // -0.13762, -0.99049 + 0xbfc139f0cedaf576, 0xbfefb5797195d741, // -0.13458, -0.9909 + 0xbfc0d64dbcb26786, 0xbfefb8d18d66adb7, // -0.13154, -0.99131 + 0xbfc072a047ba831d, 0xbfefbc1617e44186, // -0.1285, -0.99171 + 0xbfc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // -0.12545, -0.9921 + 0xbfbf564e56a9730e, 0xbfefc26470e19fd3, // -0.12241, -0.99248 + 0xbfbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // -0.11937, -0.99285 + 0xbfbdc70ecbae9fc8, 0xbfefc8646cfeb721, // -0.11632, -0.99321 + 0xbfbcff533b307dc1, 0xbfefcb4703914354, // -0.11327, -0.99356 + 0xbfbc3785c79ec2d5, 0xbfefce15fd6da67b, // -0.11022, -0.99391 + 0xbfbb6fa6ec38f64c, 0xbfefd0d158d86087, // -0.10717, -0.99424 + 0xbfbaa7b724495c04, 0xbfefd37914220b84, // -0.10412, -0.99456 + 0xbfb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // -0.10107, -0.99488 + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, // -0.098017, -0.99518 + 0xbfb84f8712c130a0, 0xbfefdafa7514538c, // -0.094963, -0.99548 + 0xbfb787586a5d5b21, 0xbfefdd539ff1f456, // -0.091909, -0.99577 + 0xbfb6bf1b3e79b129, 0xbfefdf9922f73307, // -0.088854, -0.99604 + 0xbfb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // -0.085797, -0.99631 + 0xbfb52e774a4d4d0a, 0xbfefe3e92be9d886, // -0.08274, -0.99657 + 0xbfb4661179272096, 0xbfefe5f3af2e3940, // -0.079682, -0.99682 + 0xbfb39d9f12c5a299, 0xbfefe7ea85482d60, // -0.076624, -0.99706 + 0xbfb2d52092ce19f6, 0xbfefe9cdad01883a, // -0.073565, -0.99729 + 0xbfb20c9674ed444c, 0xbfefeb9d2530410f, // -0.070505, -0.99751 + 0xbfb1440134d709b2, 0xbfefed58ecb673c4, // -0.067444, -0.99772 + 0xbfb07b614e463064, 0xbfefef0102826191, // -0.064383, -0.99793 + 0xbfaf656e79f820e0, 0xbfeff095658e71ad, // -0.061321, -0.99812 + 0xbfadd406f9808ec8, 0xbfeff21614e131ed, // -0.058258, -0.9983 + 0xbfac428d12c0d7e3, 0xbfeff3830f8d575c, // -0.055195, -0.99848 + 0xbfaab101bd5f8317, 0xbfeff4dc54b1bed3, // -0.052132, -0.99864 + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, // -0.049068, -0.9988 + 0xbfa78dbaa5874685, 0xbfeff753bb1b9164, // -0.046003, -0.99894 + 0xbfa5fc00d290cd43, 0xbfeff871dadb81df, // -0.042938, -0.99908 + 0xbfa46a396ff86179, 0xbfeff97c4208c014, // -0.039873, -0.9992 + 0xbfa2d865759455cd, 0xbfeffa72effef75d, // -0.036807, -0.99932 + 0xbfa14685db42c17e, 0xbfeffb55e425fdae, // -0.033741, -0.99943 + 0xbf9f693731d1cf01, 0xbfeffc251df1d3f8, // -0.030675, -0.99953 + 0xbf9c454f4ce53b1c, 0xbfeffce09ce2a679, // -0.027608, -0.99962 + 0xbf992155f7a3667e, 0xbfeffd886084cd0d, // -0.024541, -0.9997 + 0xbf95fd4d21fab226, 0xbfeffe1c6870cb77, // -0.021474, -0.99977 + 0xbf92d936bbe30efd, 0xbfeffe9cb44b51a1, // -0.018407, -0.99983 + 0xbf8f6a296ab997ca, 0xbfefff0943c53bd1, // -0.015339, -0.99988 + 0xbf8921d1fcdec784, 0xbfefff62169b92db, // -0.012272, -0.99992 + 0xbf82d96b0e509703, 0xbfefffa72c978c4f, //-0.0092038, -0.99996 + 0xbf7921f0fe670071, 0xbfefffd8858e8a92, //-0.0061359, -0.99998 + 0xbf6921f8becca4ba, 0xbfeffff621621d02, // -0.003068, -1 + 0x0000000000000000, 0xbff0000000000000, // 0, -1 + 0x3f6921f8becca4ba, 0xbfeffff621621d02, // 0.003068, -1 + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, // 0.0061359, -0.99998 + 0x3f82d96b0e509703, 0xbfefffa72c978c4f, // 0.0092038, -0.99996 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f8f6a296ab997ca, 0xbfefff0943c53bd1, // 0.015339, -0.99988 + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983 + 0x3f95fd4d21fab226, 0xbfeffe1c6870cb77, // 0.021474, -0.99977 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3f9c454f4ce53b1c, 0xbfeffce09ce2a679, // 0.027608, -0.99962 + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953 + 0x3fa14685db42c17e, 0xbfeffb55e425fdae, // 0.033741, -0.99943 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa46a396ff86179, 0xbfeff97c4208c014, // 0.039873, -0.9992 + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908 + 0x3fa78dbaa5874685, 0xbfeff753bb1b9164, // 0.046003, -0.99894 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3faab101bd5f8317, 0xbfeff4dc54b1bed3, // 0.052132, -0.99864 + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848 + 0x3fadd406f9808ec8, 0xbfeff21614e131ed, // 0.058258, -0.9983 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fb07b614e463064, 0xbfefef0102826191, // 0.064383, -0.99793 + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772 + 0x3fb20c9674ed444c, 0xbfefeb9d2530410f, // 0.070505, -0.99751 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb39d9f12c5a299, 0xbfefe7ea85482d60, // 0.076624, -0.99706 + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682 + 0x3fb52e774a4d4d0a, 0xbfefe3e92be9d886, // 0.08274, -0.99657 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb6bf1b3e79b129, 0xbfefdf9922f73307, // 0.088854, -0.99604 + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577 + 0x3fb84f8712c130a0, 0xbfefdafa7514538c, // 0.094963, -0.99548 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // 0.10107, -0.99488 + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456 + 0x3fbb6fa6ec38f64c, 0xbfefd0d158d86087, // 0.10717, -0.99424 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbcff533b307dc1, 0xbfefcb4703914354, // 0.11327, -0.99356 + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321 + 0x3fbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // 0.11937, -0.99285 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // 0.12545, -0.9921 + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171 + 0x3fc0d64dbcb26786, 0xbfefb8d18d66adb7, // 0.13154, -0.99131 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc19d8940be24e7, 0xbfefb20dc681d54d, // 0.13762, -0.99049 + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006 + 0x3fc264994dfd340a, 0xbfefaafbcb0cfddc, // 0.1437, -0.98962 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc32b7bf94516a7, 0xbfefa39bac7a1791, // 0.14976, -0.98872 + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826 + 0x3fc3f22f57db4893, 0xbfef9bed7cfbde29, // 0.15583, -0.98778 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc4b8b17f79fa88, 0xbfef93f14f85ac08, // 0.16189, -0.98681 + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631 + 0x3fc57f008654cbde, 0xbfef8ba737cb4b78, // 0.16794, -0.9858 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc6451a831d830d, 0xbfef830f4a40c60c, // 0.17398, -0.98475 + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421 + 0x3fc70afd8d08c4ff, 0xbfef7a299c1a322a, // 0.18002, -0.98366 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // 0.18606, -0.98254 + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196 + 0x3fc8961727c41804, 0xbfef677556883cee, // 0.19208, -0.98138 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc95b49e9b62af9, 0xbfef5da6ed43685d, // 0.1981, -0.98018 + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957 + 0x3fca203e1b1831da, 0xbfef538b1faf2d07, // 0.20411, -0.97895 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fcae4f1d5f3b9ab, 0xbfef492206bcabb4, // 0.21011, -0.97768 + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703 + 0x3fcba96334f15dad, 0xbfef3e6bbc1bbc65, // 0.21611, -0.97637 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcc6d90535d74dc, 0xbfef33685a3aaef0, // 0.22209, -0.97503 + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434 + 0x3fcd31774d2cbdee, 0xbfef2817fc4609ce, // 0.22807, -0.97364 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fcdf5163f01099a, 0xbfef1c7abe284708, // 0.23404, -0.97223 + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715 + 0x3fceb86b462de348, 0xbfef1090bc898f5f, // 0.24, -0.97077 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fcf7b7480bd3801, 0xbfef045a14cf738c, // 0.24596, -0.96928 + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852 + 0x3fd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // 0.2519, -0.96775 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd0804e05eb661e, 0xbfeeeb074c50a544, // 0.25783, -0.96619 + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539 + 0x3fd0e15b4e1749cd, 0xbfeeddeb6a078651, // 0.26375, -0.96459 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd1423eefc69378, 0xbfeed0835e999009, // 0.26967, -0.96295 + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212 + 0x3fd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // 0.27557, -0.96128 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd2038583d727bd, 0xbfeeb4cf515b8811, // 0.28146, -0.95957 + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587 + 0x3fd263e6995554ba, 0xbfeea68393e65800, // 0.28735, -0.95783 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd2c41a4e954520, 0xbfee97ec36016b30, // 0.29322, -0.95605 + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514 + 0x3fd3241fb638baaf, 0xbfee89095bad6025, // 0.29908, -0.95423 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd383f5e353b6aa, 0xbfee79db29a5165a, // 0.30493, -0.95238 + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144 + 0x3fd3e39be96ec271, 0xbfee6a61c55d53a7, // 0.31077, -0.95049 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd44310dc8936f0, 0xbfee5a9d550467d3, // 0.31659, -0.94856 + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759 + 0x3fd4a253d11b82f3, 0xbfee4a8dff81ce5e, // 0.32241, -0.9466 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd50163dc197047, 0xbfee3a33ec75ce85, // 0.32821, -0.9446 + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359 + 0x3fd5604012f467b4, 0xbfee298f4439197a, // 0.334, -0.94257 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd5bee78b9db3b6, 0xbfee18a02fdc66d9, // 0.33978, -0.94051 + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946 + 0x3fd61d595c88c203, 0xbfee0766d9280f54, // 0.34554, -0.9384 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd67b949cad63ca, 0xbfedf5e36a9ba59c, // 0.35129, -0.93627 + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518 + 0x3fd6d998638a0cb5, 0xbfede4160f6d8d81, // 0.35703, -0.93409 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd73763c9261092, 0xbfedd1fef38a915a, // 0.36276, -0.93188 + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077 + 0x3fd794f5e613dfae, 0xbfedbf9e4395759a, // 0.36847, -0.92964 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd7f24dd37341e3, 0xbfedacf42ce68ab9, // 0.37416, -0.92736 + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621 + 0x3fd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // 0.37985, -0.92505 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd8ac4b86d5ed44, 0xbfed86c48445a450, // 0.38552, -0.9227 + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151 + 0x3fd908ef81ef7bd1, 0xbfed733f508c0dff, // 0.39117, -0.92032 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd96555b7ab948f, 0xbfed5f7172888a7f, // 0.39681, -0.9179 + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668 + 0x3fd9c17d440df9f2, 0xbfed4b5b1b187524, // 0.40243, -0.91545 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // 0.40804, -0.91296 + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171 + 0x3fda790cd3dbf31a, 0xbfed2255c6e5a4e1, // 0.41364, -0.91044 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fdad473125cdc08, 0xbfed0d672f59d2b9, // 0.41922, -0.90789 + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066 + 0x3fdb2f971db31972, 0xbfecf830e8ce467b, // 0.42478, -0.9053 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdb8a7814fd5693, 0xbfece2b32799a060, // 0.43033, -0.90267 + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135 + 0x3fdbe51517ffc0d9, 0xbfecccee20c2de9f, // 0.43586, -0.90002 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdc3f6d47263129, 0xbfecb6e20a00da99, // 0.44137, -0.89732 + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597 + 0x3fdc997fc3865388, 0xbfeca08f19b9c449, // 0.44687, -0.8946 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdcf34baee1cd21, 0xbfec89f587029c13, // 0.45235, -0.89184 + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045 + 0x3fdd4cd02ba8609c, 0xbfec7315899eaad7, // 0.45781, -0.88905 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fdda60c5cfa10d8, 0xbfec5bef59fef85a, // 0.46326, -0.88622 + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848 + 0x3fddfeff66a941de, 0xbfec44833141c004, // 0.46869, -0.88336 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fde57a86d3cd824, 0xbfec2cd14931e3f1, // 0.4741, -0.88047 + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901 + 0x3fdeb00695f25620, 0xbfec14d9dc465e58, // 0.47949, -0.87755 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdf081906bff7fd, 0xbfebfc9d25a1b147, // 0.48487, -0.87459 + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309 + 0x3fdf5fdee656cda3, 0xbfebe41b611154c1, // 0.49023, -0.8716 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fdfb7575c24d2de, 0xbfebcb54cb0d2327, // 0.49557, -0.86857 + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705 + 0x3fe00740c82b82e0, 0xbfebb249a0b6c40d, // 0.50089, -0.86551 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe032ae55edbd95, 0xbfeb98fa1fd9155e, // 0.50619, -0.86242 + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087 + 0x3fe05df3ec31b8b6, 0xbfeb7f6686e792ea, // 0.51147, -0.8593 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe089112032b08c, 0xbfeb658f14fdbc47, // 0.51673, -0.85615 + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456 + 0x3fe0b405878f85ec, 0xbfeb4b7409de7925, // 0.52198, -0.85296 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // 0.5272, -0.84974 + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812 + 0x3fe1097248d0a956, 0xbfeb16742a4ca2f5, // 0.5324, -0.84649 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe133e9cfee254e, 0xbfeafb8fd89f57b6, // 0.53759, -0.84321 + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155 + 0x3fe15e36e4dbe2bc, 0xbfeae068f345ecef, // 0.54275, -0.83989 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe188591f3a46e5, 0xbfeac4ffbd3efac8, // 0.54789, -0.83655 + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486 + 0x3fe1b250171373be, 0xbfeaa9547a2cb98e, // 0.55302, -0.83317 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe1dc1b64dc4872, 0xbfea8d676e545ad2, // 0.55812, -0.82976 + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805 + 0x3fe205baa17560d6, 0xbfea7138de9d60f5, // 0.5632, -0.82632 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe22f2d662c13e1, 0xbfea54c91090f524, // 0.56826, -0.82285 + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211 + 0x3fe258734cbb7110, 0xbfea38184a593bc6, // 0.5733, -0.81935 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe2818bef4d3cba, 0xbfea1b26d2c0a75e, // 0.57831, -0.81581 + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404 + 0x3fe2aa76e87aeb58, 0xbfe9fdf4f13149de, // 0.58331, -0.81225 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe2d333d34e9bb7, 0xbfe9e082edb42472, // 0.58828, -0.80866 + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685 + 0x3fe2fbc24b441015, 0xbfe9c2d110f075c3, // 0.59323, -0.80503 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe32421ec49a620, 0xbfe9a4dfa42b06b2, // 0.59816, -0.80138 + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954 + 0x3fe34c5252c14de1, 0xbfe986aef1457594, // 0.60307, -0.79769 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe374531b817f8d, 0xbfe9683f42bd7fe1, // 0.60795, -0.79398 + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211 + 0x3fe39c23e3d63029, 0xbfe94990e3ac4a6c, // 0.61281, -0.79023 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe3c3c44981c517, 0xbfe92aa41fc5a815, // 0.61765, -0.78646 + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456 + 0x3fe3eb33eabe0680, 0xbfe90b7943575efe, // 0.62246, -0.78265 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe41272663d108c, 0xbfe8ec109b486c49, // 0.62725, -0.77882 + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689 + 0x3fe4397f5b2a4380, 0xbfe8cc6a75184655, // 0.63202, -0.77495 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe4605a692b32a2, 0xbfe8ac871ede1d88, // 0.63676, -0.77106 + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691 + 0x3fe48703306091fe, 0xbfe88c66e7481ba1, // 0.64148, -0.76714 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe4ad79516722f0, 0xbfe86c0a1d9aa195, // 0.64618, -0.76319 + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612 + 0x3fe4d3bc6d589f80, 0xbfe84b7111af83f9, // 0.65085, -0.75921 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe4f9cc25cca486, 0xbfe82a9c13f545ff, // 0.65549, -0.7552 + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319 + 0x3fe51fa81cd99aa6, 0xbfe8098b756e52fa, // 0.66011, -0.75117 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe5454ff5159dfb, 0xbfe7e83f87b03686, // 0.66471, -0.7471 + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506 + 0x3fe56ac35197649e, 0xbfe7c6b89ce2d333, // 0.66928, -0.74301 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe59001d5f723df, 0xbfe7a4f707bf97d2, // 0.67383, -0.73889 + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682 + 0x3fe5b50b264f7448, 0xbfe782fb1b90b35b, // 0.67835, -0.73474 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe5d9dee73e345c, 0xbfe760c52c304764, // 0.68285, -0.73056 + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846 + 0x3fe5fe7cbde56a0f, 0xbfe73e558e079942, // 0.68732, -0.72636 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe622e44fec22ff, 0xbfe71bac960e41bf, // 0.69176, -0.72213 + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72 + 0x3fe64715437f535b, 0xbfe6f8ca99c95b75, // 0.69618, -0.71787 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe66b0f3f52b386, 0xbfe6d5afef4aafcc, // 0.70057, -0.71358 + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143 + 0x3fe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // 0.70493, -0.70927 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // 0.70927, -0.70493 + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275 + 0x3fe6d5afef4aafcc, 0xbfe66b0f3f52b386, // 0.71358, -0.70057 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe6f8ca99c95b75, 0xbfe64715437f535b, // 0.71787, -0.69618 + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397 + 0x3fe71bac960e41bf, 0xbfe622e44fec22ff, // 0.72213, -0.69176 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe73e558e079942, 0xbfe5fe7cbde56a0f, // 0.72636, -0.68732 + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508 + 0x3fe760c52c304764, 0xbfe5d9dee73e345c, // 0.73056, -0.68285 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe782fb1b90b35b, 0xbfe5b50b264f7448, // 0.73474, -0.67835 + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609 + 0x3fe7a4f707bf97d2, 0xbfe59001d5f723df, // 0.73889, -0.67383 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7c6b89ce2d333, 0xbfe56ac35197649e, // 0.74301, -0.66928 + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667 + 0x3fe7e83f87b03686, 0xbfe5454ff5159dfb, // 0.7471, -0.66471 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe8098b756e52fa, 0xbfe51fa81cd99aa6, // 0.75117, -0.66011 + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781 + 0x3fe82a9c13f545ff, 0xbfe4f9cc25cca486, // 0.7552, -0.65549 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe84b7111af83f9, 0xbfe4d3bc6d589f80, // 0.75921, -0.65085 + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851 + 0x3fe86c0a1d9aa195, 0xbfe4ad79516722f0, // 0.76319, -0.64618 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe88c66e7481ba1, 0xbfe48703306091fe, // 0.76714, -0.64148 + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912 + 0x3fe8ac871ede1d88, 0xbfe4605a692b32a2, // 0.77106, -0.63676 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8cc6a75184655, 0xbfe4397f5b2a4380, // 0.77495, -0.63202 + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964 + 0x3fe8ec109b486c49, 0xbfe41272663d108c, // 0.77882, -0.62725 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe90b7943575efe, 0xbfe3eb33eabe0680, // 0.78265, -0.62246 + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006 + 0x3fe92aa41fc5a815, 0xbfe3c3c44981c517, // 0.78646, -0.61765 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe94990e3ac4a6c, 0xbfe39c23e3d63029, // 0.79023, -0.61281 + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038 + 0x3fe9683f42bd7fe1, 0xbfe374531b817f8d, // 0.79398, -0.60795 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe986aef1457594, 0xbfe34c5252c14de1, // 0.79769, -0.60307 + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062 + 0x3fe9a4dfa42b06b2, 0xbfe32421ec49a620, // 0.80138, -0.59816 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9c2d110f075c3, 0xbfe2fbc24b441015, // 0.80503, -0.59323 + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076 + 0x3fe9e082edb42472, 0xbfe2d333d34e9bb7, // 0.80866, -0.58828 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fe9fdf4f13149de, 0xbfe2aa76e87aeb58, // 0.81225, -0.58331 + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081 + 0x3fea1b26d2c0a75e, 0xbfe2818bef4d3cba, // 0.81581, -0.57831 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea38184a593bc6, 0xbfe258734cbb7110, // 0.81935, -0.5733 + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078 + 0x3fea54c91090f524, 0xbfe22f2d662c13e1, // 0.82285, -0.56826 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea7138de9d60f5, 0xbfe205baa17560d6, // 0.82632, -0.5632 + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066 + 0x3fea8d676e545ad2, 0xbfe1dc1b64dc4872, // 0.82976, -0.55812 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3feaa9547a2cb98e, 0xbfe1b250171373be, // 0.83317, -0.55302 + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046 + 0x3feac4ffbd3efac8, 0xbfe188591f3a46e5, // 0.83655, -0.54789 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3feae068f345ecef, 0xbfe15e36e4dbe2bc, // 0.83989, -0.54275 + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017 + 0x3feafb8fd89f57b6, 0xbfe133e9cfee254e, // 0.84321, -0.53759 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb16742a4ca2f5, 0xbfe1097248d0a956, // 0.84649, -0.5324 + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298 + 0x3feb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // 0.84974, -0.5272 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb4b7409de7925, 0xbfe0b405878f85ec, // 0.85296, -0.52198 + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936 + 0x3feb658f14fdbc47, 0xbfe089112032b08c, // 0.85615, -0.51673 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb7f6686e792ea, 0xbfe05df3ec31b8b6, // 0.8593, -0.51147 + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883 + 0x3feb98fa1fd9155e, 0xbfe032ae55edbd95, // 0.86242, -0.50619 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3febb249a0b6c40d, 0xbfe00740c82b82e0, // 0.86551, -0.50089 + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823 + 0x3febcb54cb0d2327, 0xbfdfb7575c24d2de, // 0.86857, -0.49557 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3febe41b611154c1, 0xbfdf5fdee656cda3, // 0.8716, -0.49023 + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755 + 0x3febfc9d25a1b147, 0xbfdf081906bff7fd, // 0.87459, -0.48487 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3fec14d9dc465e58, 0xbfdeb00695f25620, // 0.87755, -0.47949 + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768 + 0x3fec2cd14931e3f1, 0xbfde57a86d3cd824, // 0.88047, -0.4741 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec44833141c004, 0xbfddfeff66a941de, // 0.88336, -0.46869 + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598 + 0x3fec5bef59fef85a, 0xbfdda60c5cfa10d8, // 0.88622, -0.46326 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec7315899eaad7, 0xbfdd4cd02ba8609c, // 0.88905, -0.45781 + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508 + 0x3fec89f587029c13, 0xbfdcf34baee1cd21, // 0.89184, -0.45235 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3feca08f19b9c449, 0xbfdc997fc3865388, // 0.8946, -0.44687 + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412 + 0x3fecb6e20a00da99, 0xbfdc3f6d47263129, // 0.89732, -0.44137 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3fecccee20c2de9f, 0xbfdbe51517ffc0d9, // 0.90002, -0.43586 + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309 + 0x3fece2b32799a060, 0xbfdb8a7814fd5693, // 0.90267, -0.43033 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fecf830e8ce467b, 0xbfdb2f971db31972, // 0.9053, -0.42478 + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422 + 0x3fed0d672f59d2b9, 0xbfdad473125cdc08, // 0.90789, -0.41922 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed2255c6e5a4e1, 0xbfda790cd3dbf31a, // 0.91044, -0.41364 + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084 + 0x3fed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // 0.91296, -0.40804 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed4b5b1b187524, 0xbfd9c17d440df9f2, // 0.91545, -0.40243 + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962 + 0x3fed5f7172888a7f, 0xbfd96555b7ab948f, // 0.9179, -0.39681 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed733f508c0dff, 0xbfd908ef81ef7bd1, // 0.92032, -0.39117 + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835 + 0x3fed86c48445a450, 0xbfd8ac4b86d5ed44, // 0.9227, -0.38552 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // 0.92505, -0.37985 + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701 + 0x3fedacf42ce68ab9, 0xbfd7f24dd37341e3, // 0.92736, -0.37416 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3fedbf9e4395759a, 0xbfd794f5e613dfae, // 0.92964, -0.36847 + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561 + 0x3fedd1fef38a915a, 0xbfd73763c9261092, // 0.93188, -0.36276 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fede4160f6d8d81, 0xbfd6d998638a0cb5, // 0.93409, -0.35703 + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416 + 0x3fedf5e36a9ba59c, 0xbfd67b949cad63ca, // 0.93627, -0.35129 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fee0766d9280f54, 0xbfd61d595c88c203, // 0.9384, -0.34554 + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266 + 0x3fee18a02fdc66d9, 0xbfd5bee78b9db3b6, // 0.94051, -0.33978 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee298f4439197a, 0xbfd5604012f467b4, // 0.94257, -0.334 + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111 + 0x3fee3a33ec75ce85, 0xbfd50163dc197047, // 0.9446, -0.32821 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee4a8dff81ce5e, 0xbfd4a253d11b82f3, // 0.9466, -0.32241 + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195 + 0x3fee5a9d550467d3, 0xbfd44310dc8936f0, // 0.94856, -0.31659 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee6a61c55d53a7, 0xbfd3e39be96ec271, // 0.95049, -0.31077 + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785 + 0x3fee79db29a5165a, 0xbfd383f5e353b6aa, // 0.95238, -0.30493 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee89095bad6025, 0xbfd3241fb638baaf, // 0.95423, -0.29908 + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615 + 0x3fee97ec36016b30, 0xbfd2c41a4e954520, // 0.95605, -0.29322 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3feea68393e65800, 0xbfd263e6995554ba, // 0.95783, -0.28735 + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441 + 0x3feeb4cf515b8811, 0xbfd2038583d727bd, // 0.95957, -0.28146 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // 0.96128, -0.27557 + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262 + 0x3feed0835e999009, 0xbfd1423eefc69378, // 0.96295, -0.26967 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feeddeb6a078651, 0xbfd0e15b4e1749cd, // 0.96459, -0.26375 + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079 + 0x3feeeb074c50a544, 0xbfd0804e05eb661e, // 0.96619, -0.25783 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3feef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // 0.96775, -0.2519 + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893 + 0x3fef045a14cf738c, 0xbfcf7b7480bd3801, // 0.96928, -0.24596 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef1090bc898f5f, 0xbfceb86b462de348, // 0.97077, -0.24 + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702 + 0x3fef1c7abe284708, 0xbfcdf5163f01099a, // 0.97223, -0.23404 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef2817fc4609ce, 0xbfcd31774d2cbdee, // 0.97364, -0.22807 + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508 + 0x3fef33685a3aaef0, 0xbfcc6d90535d74dc, // 0.97503, -0.22209 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef3e6bbc1bbc65, 0xbfcba96334f15dad, // 0.97637, -0.21611 + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311 + 0x3fef492206bcabb4, 0xbfcae4f1d5f3b9ab, // 0.97768, -0.21011 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef538b1faf2d07, 0xbfca203e1b1831da, // 0.97895, -0.20411 + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011 + 0x3fef5da6ed43685d, 0xbfc95b49e9b62af9, // 0.98018, -0.1981 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef677556883cee, 0xbfc8961727c41804, // 0.98138, -0.19208 + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907 + 0x3fef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // 0.98254, -0.18606 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef7a299c1a322a, 0xbfc70afd8d08c4ff, // 0.98366, -0.18002 + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177 + 0x3fef830f4a40c60c, 0xbfc6451a831d830d, // 0.98475, -0.17398 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef8ba737cb4b78, 0xbfc57f008654cbde, // 0.9858, -0.16794 + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491 + 0x3fef93f14f85ac08, 0xbfc4b8b17f79fa88, // 0.98681, -0.16189 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fef9bed7cfbde29, 0xbfc3f22f57db4893, // 0.98778, -0.15583 + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528 + 0x3fefa39bac7a1791, 0xbfc32b7bf94516a7, // 0.98872, -0.14976 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefaafbcb0cfddc, 0xbfc264994dfd340a, // 0.98962, -0.1437 + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066 + 0x3fefb20dc681d54d, 0xbfc19d8940be24e7, // 0.99049, -0.13762 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefb8d18d66adb7, 0xbfc0d64dbcb26786, // 0.99131, -0.13154 + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285 + 0x3fefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // 0.9921, -0.12545 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // 0.99285, -0.11937 + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632 + 0x3fefcb4703914354, 0xbfbcff533b307dc1, // 0.99356, -0.11327 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefd0d158d86087, 0xbfbb6fa6ec38f64c, // 0.99424, -0.10717 + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412 + 0x3fefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // 0.99488, -0.10107 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017 + 0x3fefdafa7514538c, 0xbfb84f8712c130a0, // 0.99548, -0.094963 + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909 + 0x3fefdf9922f73307, 0xbfb6bf1b3e79b129, // 0.99604, -0.088854 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797 + 0x3fefe3e92be9d886, 0xbfb52e774a4d4d0a, // 0.99657, -0.08274 + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682 + 0x3fefe7ea85482d60, 0xbfb39d9f12c5a299, // 0.99706, -0.076624 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565 + 0x3fefeb9d2530410f, 0xbfb20c9674ed444c, // 0.99751, -0.070505 + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444 + 0x3fefef0102826191, 0xbfb07b614e463064, // 0.99793, -0.064383 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321 + 0x3feff21614e131ed, 0xbfadd406f9808ec8, // 0.9983, -0.058258 + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195 + 0x3feff4dc54b1bed3, 0xbfaab101bd5f8317, // 0.99864, -0.052132 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068 + 0x3feff753bb1b9164, 0xbfa78dbaa5874685, // 0.99894, -0.046003 + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938 + 0x3feff97c4208c014, 0xbfa46a396ff86179, // 0.9992, -0.039873 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807 + 0x3feffb55e425fdae, 0xbfa14685db42c17e, // 0.99943, -0.033741 + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675 + 0x3feffce09ce2a679, 0xbf9c454f4ce53b1c, // 0.99962, -0.027608 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541 + 0x3feffe1c6870cb77, 0xbf95fd4d21fab226, // 0.99977, -0.021474 + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407 + 0x3fefff0943c53bd1, 0xbf8f6a296ab997ca, // 0.99988, -0.015339 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272 + 0x3fefffa72c978c4f, 0xbf82d96b0e509703, // 0.99996,-0.0092038 + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359 + 0x3feffff621621d02, 0xbf6921f8becca4ba, // 1, -0.003068 + +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_4096) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par +
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 4096, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_4096[8192] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffffd88586ee6, 0x3f5921faaee6472d, // 1, 0.001534 + 0x3feffff621621d02, 0x3f6921f8becca4ba, // 1, 0.003068 + 0x3fefffe9cb1e2e8d, 0x3f72d97822f996bc, // 0.99999, 0.0046019 + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359 + 0x3fefffc250b5daef, 0x3f7f6a65f9a2a3c5, // 0.99997, 0.0076698 + 0x3fefffa72c978c4f, 0x3f82d96b0e509703, // 0.99996, 0.0092038 + 0x3fefff871937ce2f, 0x3f85fda037ac05e0, // 0.99994, 0.010738 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3fefff3824c88f6f, 0x3f8c45ffe1e48ad9, // 0.9999, 0.013805 + 0x3fefff0943c53bd1, 0x3f8f6a296ab997ca, // 0.99988, 0.015339 + 0x3feffed57398d2b7, 0x3f9147270dad7132, // 0.99986, 0.016873 + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407 + 0x3feffe5f05e578db, 0x3f946b4381fce81c, // 0.9998, 0.01994 + 0x3feffe1c6870cb77, 0x3f95fd4d21fab226, // 0.99977, 0.021474 + 0x3feffdd4dbf78f52, 0x3f978f535ddc9f03, // 0.99974, 0.023008 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffd36f624500c, 0x3f9ab354b1504fca, // 0.99966, 0.026075 + 0x3feffce09ce2a679, 0x3f9c454f4ce53b1c, // 0.99962, 0.027608 + 0x3feffc8554cd213a, 0x3f9dd7458c64ab39, // 0.99958, 0.029142 + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675 + 0x3feffbbff85f9515, 0x3fa07d91ff984580, // 0.99948, 0.032208 + 0x3feffb55e425fdae, 0x3fa14685db42c17e, // 0.99943, 0.033741 + 0x3feffae6e1556998, 0x3fa20f770ceb11c6, // 0.99938, 0.035274 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feff9fa10348837, 0x3fa3a150f6421afc, // 0.99926, 0.03834 + 0x3feff97c4208c014, 0x3fa46a396ff86179, // 0.9992, 0.039873 + 0x3feff8f9858f058b, 0x3fa5331ec3bba0eb, // 0.99914, 0.041406 + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938 + 0x3feff7e5420320f9, 0x3fa6c4df7d7d5b84, // 0.99901, 0.044471 + 0x3feff753bb1b9164, 0x3fa78dbaa5874685, // 0.99894, 0.046003 + 0x3feff6bd463b444d, 0x3fa856922bb513c1, // 0.99887, 0.047535 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff58192ee0358, 0x3fa9e835d6993c87, // 0.99872, 0.0506 + 0x3feff4dc54b1bed3, 0x3faab101bd5f8317, // 0.99864, 0.052132 + 0x3feff43228de1b77, 0x3fab79c986698b78, // 0.99856, 0.053664 + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195 + 0x3feff2cf08da7321, 0x3fad0b4c436f91d0, // 0.99839, 0.056727 + 0x3feff21614e131ed, 0x3fadd406f9808ec8, // 0.9983, 0.058258 + 0x3feff15833be1965, 0x3fae9cbd15ff5527, // 0.99821, 0.05979 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3fefefcdaa704562, 0x3fb0170d833bf421, // 0.99802, 0.062852 + 0x3fefef0102826191, 0x3fb07b614e463064, // 0.99793, 0.064383 + 0x3fefee2f6de455ba, 0x3fb0dfb28ea201e6, // 0.99783, 0.065913 + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444 + 0x3fefec7d7f19cffc, 0x3fb1a84d316d4f8a, // 0.99762, 0.068974 + 0x3fefeb9d2530410f, 0x3fb20c9674ed444c, // 0.99751, 0.070505 + 0x3fefeab7df1c6005, 0x3fb270dcefdfc45b, // 0.9974, 0.072035 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefe8de8f03d75c, 0x3fb339614e41ffa5, // 0.99718, 0.075094 + 0x3fefe7ea85482d60, 0x3fb39d9f12c5a299, // 0.99706, 0.076624 + 0x3fefe6f18ff42c84, 0x3fb401d9d0e3a507, // 0.99694, 0.078153 + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682 + 0x3fefe4f0e31d7a4a, 0x3fb4ca45fc1ba8b6, // 0.9967, 0.081211 + 0x3fefe3e92be9d886, 0x3fb52e774a4d4d0a, // 0.99657, 0.08274 + 0x3fefe2dc89bbff08, 0x3fb592a554489bc8, // 0.99644, 0.084269 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefe0b485181be3, 0x3fb65af75dd0f87b, // 0.99618, 0.087326 + 0x3fefdf9922f73307, 0x3fb6bf1b3e79b129, // 0.99604, 0.088854 + 0x3fefde78d68653fd, 0x3fb7233b9d236e71, // 0.99591, 0.090381 + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909 + 0x3fefdc297f674ba9, 0x3fb7eb7196b72ee4, // 0.99563, 0.093436 + 0x3fefdafa7514538c, 0x3fb84f8712c130a0, // 0.99548, 0.094963 + 0x3fefd9c68127c78c, 0x3fb8b398cf0c38e0, // 0.99533, 0.09649 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefd74fdd40abbf, 0x3fb97bb0caaba56f, // 0.99503, 0.099544 + 0x3fefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // 0.99488, 0.10107 + 0x3fefd4c59536fae4, 0x3fba43b90e27f3c4, // 0.99472, 0.1026 + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412 + 0x3fefd227aa9bd53b, 0x3fbb0bb11e1d5559, // 0.9944, 0.10565 + 0x3fefd0d158d86087, 0x3fbb6fa6ec38f64c, // 0.99424, 0.10717 + 0x3fefcf761f0c77a3, 0x3fbbd3987f31fa0e, // 0.99407, 0.1087 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefccb0f4323aa3, 0x3fbc9b6eb6165c42, // 0.99374, 0.11175 + 0x3fefcb4703914354, 0x3fbcff533b307dc1, // 0.99356, 0.11327 + 0x3fefc9d82bc2915e, 0x3fbd633347858ce4, // 0.99339, 0.11479 + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632 + 0x3fefc6ebc77f0887, 0x3fbe2ae5b8457f77, // 0.99303, 0.11784 + 0x3fefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // 0.99285, 0.11937 + 0x3fefc3ebc935454c, 0x3fbef2858d27561b, // 0.99267, 0.12089 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefc0d832bf043a, 0x3fbfba124b07ad85, // 0.99229, 0.12393 + 0x3fefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // 0.9921, 0.12545 + 0x3fefbdb106021816, 0x3fc040c5bb67747e, // 0.99191, 0.12698 + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285 + 0x3fefba7644f068b5, 0x3fc0a4784ab8bf1d, // 0.99151, 0.13002 + 0x3fefb8d18d66adb7, 0x3fc0d64dbcb26786, // 0.99131, 0.13154 + 0x3fefb727f187f1c7, 0x3fc1082095f820b0, // 0.99111, 0.13306 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefb3c60dd2c199, 0x3fc16bbe5fac5865, // 0.9907, 0.1361 + 0x3fefb20dc681d54d, 0x3fc19d8940be24e7, // 0.99049, 0.13762 + 0x3fefb0509be6f7db, 0x3fc1cf516a62a077, // 0.99027, 0.13914 + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066 + 0x3fefacc79de6c44f, 0x3fc232d978aed413, // 0.98984, 0.14218 + 0x3fefaafbcb0cfddc, 0x3fc264994dfd340a, // 0.98962, 0.1437 + 0x3fefa92b1600657c, 0x3fc296564d2b953e, // 0.9894, 0.14521 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fefa57b066e2754, 0x3fc2f9c7aa7a72af, // 0.98895, 0.14825 + 0x3fefa39bac7a1791, 0x3fc32b7bf94516a7, // 0.98872, 0.14976 + 0x3fefa1b7717661d5, 0x3fc35d2d53440db2, // 0.98849, 0.15128 + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528 + 0x3fef9de0596b77a3, 0x3fc3c0870a383ff6, // 0.98802, 0.15431 + 0x3fef9bed7cfbde29, 0x3fc3f22f57db4893, // 0.98778, 0.15583 + 0x3fef99f5c0abd496, 0x3fc423d4920e4166, // 0.98754, 0.15734 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef95f7a9a1ec47, 0x3fc48715ad84cdf5, // 0.98706, 0.16037 + 0x3fef93f14f85ac08, 0x3fc4b8b17f79fa88, // 0.98681, 0.16189 + 0x3fef91e616c43891, 0x3fc4ea4a1f624b61, // 0.98656, 0.1634 + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491 + 0x3fef8dc10a95380d, 0x3fc54d71aa74ef02, // 0.98605, 0.16643 + 0x3fef8ba737cb4b78, 0x3fc57f008654cbde, // 0.9858, 0.16794 + 0x3fef898887a36c84, 0x3fc5b08c1192e381, // 0.98554, 0.16945 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef853c9089595e, 0x3fc61399179a6e94, // 0.98501, 0.17247 + 0x3fef830f4a40c60c, 0x3fc6451a831d830d, // 0.98475, 0.17398 + 0x3fef80dd27ed8204, 0x3fc676987f7216b8, // 0.98448, 0.17549 + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177 + 0x3fef7c6a50826840, 0x3fc6d98a0c08c8da, // 0.98394, 0.17851 + 0x3fef7a299c1a322a, 0x3fc70afd8d08c4ff, // 0.98366, 0.18002 + 0x3fef77e40d068a90, 0x3fc73c6d8055fe0a, // 0.98339, 0.18153 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef734a60446279, 0x3fc79f429f59e11d, // 0.98282, 0.18455 + 0x3fef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // 0.98254, 0.18606 + 0x3fef6e9d4d1262ca, 0x3fc802092c1d744b, // 0.98225, 0.18756 + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907 + 0x3fef69dcd652f5de, 0x3fc864c0e9b2b6cf, // 0.98167, 0.19057 + 0x3fef677556883cee, 0x3fc8961727c41804, // 0.98138, 0.19208 + 0x3fef6508fef47bd5, 0x3fc8c7699b34ca7e, // 0.98108, 0.19359 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef6021c9f148c2, 0x3fc92a0303c8194f, // 0.98048, 0.19659 + 0x3fef5da6ed43685d, 0x3fc95b49e9b62af9, // 0.98018, 0.1981 + 0x3fef5b273a4fa2d9, 0x3fc98c8ce69a7aec, // 0.97988, 0.1996 + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011 + 0x3fef56195321c090, 0x3fc9ef0706e35a35, // 0.97926, 0.20261 + 0x3fef538b1faf2d07, 0x3fca203e1b1831da, // 0.97895, 0.20411 + 0x3fef50f81785c6b9, 0x3fca517127e3dabc, // 0.97863, 0.20561 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef4bc38aa5c694, 0x3fcab3cb0ce6fe44, // 0.978, 0.20861 + 0x3fef492206bcabb4, 0x3fcae4f1d5f3b9ab, // 0.97768, 0.21011 + 0x3fef467bafb7bbe0, 0x3fcb16147941ca2a, // 0.97735, 0.21161 + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311 + 0x3fef412089fd8adc, 0x3fcb784d30536cda, // 0.9767, 0.21461 + 0x3fef3e6bbc1bbc65, 0x3fcba96334f15dad, // 0.97637, 0.21611 + 0x3fef3bb21cc4fe47, 0x3fcbda74f5856330, // 0.97604, 0.2176 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef36306b67c556, 0x3fcc3c8b8c4b9dd7, // 0.97536, 0.2206 + 0x3fef33685a3aaef0, 0x3fcc6d90535d74dc, // 0.97503, 0.22209 + 0x3fef309b794b719f, 0x3fcc9e90b824a6a9, // 0.97468, 0.22359 + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508 + 0x3fef2af349e17507, 0x3fcd00843c99c5f9, // 0.97399, 0.22658 + 0x3fef2817fc4609ce, 0x3fcd31774d2cbdee, // 0.97364, 0.22807 + 0x3fef2537e0a71f9f, 0x3fcd6265dd3f27e3, // 0.97329, 0.22957 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef1f6941259d7a, 0x3fcdc4355db40195, // 0.97258, 0.23255 + 0x3fef1c7abe284708, 0x3fcdf5163f01099a, // 0.97223, 0.23404 + 0x3fef19876ef1f486, 0x3fce25f281a2b684, // 0.97187, 0.23553 + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702 + 0x3fef13926dad024e, 0x3fce879d0cc0fdaf, // 0.97114, 0.23851 + 0x3fef1090bc898f5f, 0x3fceb86b462de348, // 0.97077, 0.24 + 0x3fef0d8a410379c5, 0x3fcee934c2d006c7, // 0.9704, 0.24149 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3fef076eecade0fa, 0x3fcf4ab9679c9f5c, // 0.96966, 0.24447 + 0x3fef045a14cf738c, 0x3fcf7b7480bd3801, // 0.96928, 0.24596 + 0x3fef014074708ed3, 0x3fcfac2abeff57ff, // 0.9689, 0.24744 + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893 + 0x3feefafedc1ba8b7, 0x3fd006c4466e54af, // 0.96814, 0.25041 + 0x3feef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // 0.96775, 0.2519 + 0x3feef4aa278b2032, 0x3fd037694a928cac, // 0.96737, 0.25338 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feeee425aa6b09a, 0x3fd068044deab002, // 0.96658, 0.25635 + 0x3feeeb074c50a544, 0x3fd0804e05eb661e, // 0.96619, 0.25783 + 0x3feee7c77961dc9e, 0x3fd09895327b465e, // 0.96579, 0.25931 + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079 + 0x3feee13987bbebdc, 0x3fd0c91bda4f158d, // 0.96499, 0.26227 + 0x3feeddeb6a078651, 0x3fd0e15b4e1749cd, // 0.96459, 0.26375 + 0x3feeda9889bfe86a, 0x3fd0f998277733f7, // 0.96418, 0.26523 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feed3e483849c51, 0x3fd12a09fc0b1b12, // 0.96337, 0.26819 + 0x3feed0835e999009, 0x3fd1423eefc69378, // 0.96295, 0.26967 + 0x3feecd1d792c8f10, 0x3fd15a713a28b9d9, // 0.96254, 0.27115 + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262 + 0x3feec6436ee60309, 0x3fd18acdc3f4873a, // 0.9617, 0.2741 + 0x3feec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // 0.96128, 0.27557 + 0x3feebf5668eaf2ef, 0x3fd1bb1f7b999480, // 0.96086, 0.27705 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3feeb8566b810f2a, 0x3fd1eb6643499fbb, // 0.96, 0.27999 + 0x3feeb4cf515b8811, 0x3fd2038583d727bd, // 0.95957, 0.28146 + 0x3feeb1437af9bb34, 0x3fd21ba1fd3d2623, // 0.95914, 0.28294 + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441 + 0x3feeaa1d9bb20af3, 0x3fd24bd28bb37672, // 0.95827, 0.28588 + 0x3feea68393e65800, 0x3fd263e6995554ba, // 0.95783, 0.28735 + 0x3feea2e4d212c000, 0x3fd27bf7d0f2c346, // 0.95738, 0.28882 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3fee9b99229046f8, 0x3fd2ac11af483572, // 0.95649, 0.29175 + 0x3fee97ec36016b30, 0x3fd2c41a4e954520, // 0.95605, 0.29322 + 0x3fee943a91aab4b4, 0x3fd2dc200907fe51, // 0.95559, 0.29469 + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615 + 0x3fee8cc923edc388, 0x3fd30c22c08d6a13, // 0.95469, 0.29762 + 0x3fee89095bad6025, 0x3fd3241fb638baaf, // 0.95423, 0.29908 + 0x3fee8544ddf0d075, 0x3fd33c19b83af207, // 0.95377, 0.30054 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee7dadc456d850, 0x3fd36c04d27a4edf, // 0.95284, 0.30347 + 0x3fee79db29a5165a, 0x3fd383f5e353b6aa, // 0.95238, 0.30493 + 0x3fee7603dbce74e9, 0x3fd39be3f1bc8aef, // 0.95191, 0.30639 + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785 + 0x3fee6e472911da27, 0x3fd3cbb6f87a146e, // 0.95096, 0.30931 + 0x3fee6a61c55d53a7, 0x3fd3e39be96ec271, // 0.95049, 0.31077 + 0x3fee6677b0e6d31e, 0x3fd3fb7dc932cfa4, // 0.95001, 0.31222 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee5e95781ebf1c, 0x3fd42b38466e2928, // 0.94905, 0.31514 + 0x3fee5a9d550467d3, 0x3fd44310dc8936f0, // 0.94856, 0.31659 + 0x3fee56a083968eb1, 0x3fd45ae652bb2800, // 0.94807, 0.31805 + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195 + 0x3fee4e98d836c0af, 0x3fd48a87d0b07fd7, // 0.94709, 0.32096 + 0x3fee4a8dff81ce5e, 0x3fd4a253d11b82f3, // 0.9466, 0.32241 + 0x3fee467e7af35f23, 0x3fd4ba1ca2eca31c, // 0.94611, 0.32386 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee3e5170cbfc46, 0x3fd4e9a4ac15d520, // 0.94511, 0.32676 + 0x3fee3a33ec75ce85, 0x3fd50163dc197047, // 0.9446, 0.32821 + 0x3fee3611becbaf69, 0x3fd5191fceda3c35, // 0.9441, 0.32966 + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111 + 0x3fee2dbf6a0911d9, 0x3fd5488dedeff3be, // 0.94308, 0.33255 + 0x3fee298f4439197a, 0x3fd5604012f467b4, // 0.94257, 0.334 + 0x3fee255a77a63bb8, 0x3fd577eeec151e47, // 0.94206, 0.33545 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee1ce2ecd0c0d8, 0x3fd5a742ac0ff78d, // 0.94103, 0.33833 + 0x3fee18a02fdc66d9, 0x3fd5bee78b9db3b6, // 0.94051, 0.33978 + 0x3fee1458cec1ad83, 0x3fd5d68910aee686, // 0.93998, 0.34122 + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266 + 0x3fee0bbc22bd8349, 0x3fd605c1fcc88f63, // 0.93893, 0.3441 + 0x3fee0766d9280f54, 0x3fd61d595c88c203, // 0.9384, 0.34554 + 0x3fee030cee1435b8, 0x3fd634ed533be58e, // 0.93787, 0.34698 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3fedfa4b3621271d, 0x3fd6640af6f03d9e, // 0.9368, 0.34986 + 0x3fedf5e36a9ba59c, 0x3fd67b949cad63ca, // 0.93627, 0.35129 + 0x3fedf177004b2534, 0x3fd6931acad55f51, // 0.93573, 0.35273 + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416 + 0x3fede890520465ce, 0x3fd6c21cb1e39771, // 0.93464, 0.3556 + 0x3fede4160f6d8d81, 0x3fd6d998638a0cb5, // 0.93409, 0.35703 + 0x3feddf9730ca837b, 0x3fd6f1108f1bc9c5, // 0.93354, 0.35846 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fedd68ba2267a25, 0x3fd71ff6458782ec, // 0.93244, 0.36133 + 0x3fedd1fef38a915a, 0x3fd73763c9261092, // 0.93188, 0.36276 + 0x3fedcd6dabaca3a5, 0x3fd74ecdb8390a3e, // 0.93133, 0.36418 + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561 + 0x3fedc43d52fcb453, 0x3fd77d96ca4b73a6, // 0.93021, 0.36704 + 0x3fedbf9e4395759a, 0x3fd794f5e613dfae, // 0.92964, 0.36847 + 0x3fedbafa9dc1b78d, 0x3fd7ac515ee2b172, // 0.92907, 0.36989 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3fedb1a591b20c38, 0x3fd7dafd592ba621, // 0.92794, 0.37274 + 0x3fedacf42ce68ab9, 0x3fd7f24dd37341e3, // 0.92736, 0.37416 + 0x3feda83e348f613b, 0x3fd8099a9c5c362d, // 0.92679, 0.37559 + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701 + 0x3fed9ec48c26b1f3, 0x3fd838290bb359c8, // 0.92563, 0.37843 + 0x3fed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // 0.92505, 0.37985 + 0x3fed95389e50429b, 0x3fd866a88a792ea0, // 0.92447, 0.38127 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed8b9a70ef9cb4, 0x3fd89518fbff098e, // 0.92329, 0.3841 + 0x3fed86c48445a450, 0x3fd8ac4b86d5ed44, // 0.9227, 0.38552 + 0x3fed81ea09f38b63, 0x3fd8c37a439f884f, // 0.92211, 0.38693 + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835 + 0x3fed78276f5617c6, 0x3fd8f1cc44bea329, // 0.92092, 0.38976 + 0x3fed733f508c0dff, 0x3fd908ef81ef7bd1, // 0.92032, 0.39117 + 0x3fed6e52a71c8547, 0x3fd9200ee2c9be97, // 0.91972, 0.39258 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed646bb7574de5, 0x3fd94e420137bce3, // 0.91851, 0.3954 + 0x3fed5f7172888a7f, 0x3fd96555b7ab948f, // 0.9179, 0.39681 + 0x3fed5a72a6221e73, 0x3fd97c6583890fc2, // 0.91729, 0.39822 + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962 + 0x3fed506779a3d2d9, 0x3fd9aa794d47c9ee, // 0.91606, 0.40103 + 0x3fed4b5b1b187524, 0x3fd9c17d440df9f2, // 0.91545, 0.40243 + 0x3fed464a380e7242, 0x3fd9d87d4207b0ab, // 0.91483, 0.40384 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed3c1ae79f2b4e, 0x3fda067145664d57, // 0.91359, 0.40664 + 0x3fed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // 0.91296, 0.40804 + 0x3fed31d98e9e503a, 0x3fda34553b0afee5, // 0.91234, 0.40944 + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084 + 0x3fed2786335f52fc, 0x3fda622906a70b63, // 0.91107, 0.41224 + 0x3fed2255c6e5a4e1, 0x3fda790cd3dbf31a, // 0.91044, 0.41364 + 0x3fed1d20dc40c15c, 0x3fda8fec8bf5b166, // 0.90981, 0.41503 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3fed12a98fac410c, 0x3fdabd9faebc3980, // 0.90853, 0.41782 + 0x3fed0d672f59d2b9, 0x3fdad473125cdc08, // 0.90789, 0.41922 + 0x3fed082054168bac, 0x3fdaeb4252ca07ab, // 0.90724, 0.42061 + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422 + 0x3fecfd852fff6ad4, 0x3fdb18d45bf8aca6, // 0.90595, 0.42339 + 0x3fecf830e8ce467b, 0x3fdb2f971db31972, // 0.9053, 0.42478 + 0x3fecf2d829f1b40e, 0x3fdb4655ae2bf757, // 0.90464, 0.42617 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fece819488344ce, 0x3fdb73c62d520624, // 0.90333, 0.42894 + 0x3fece2b32799a060, 0x3fdb8a7814fd5693, // 0.90267, 0.43033 + 0x3fecdd489254fe65, 0x3fdba125bd63583e, // 0.90201, 0.43171 + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309 + 0x3fecd2660e12c1e6, 0x3fdbce744262deee, // 0.90068, 0.43448 + 0x3fecccee20c2de9f, 0x3fdbe51517ffc0d9, // 0.90002, 0.43586 + 0x3fecc771c2736c09, 0x3fdbfbb1a05e0edc, // 0.89935, 0.43724 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fecbc6bb638d10b, 0x3fdc28ddbb6cf145, // 0.898, 0.43999 + 0x3fecb6e20a00da99, 0x3fdc3f6d47263129, // 0.89732, 0.44137 + 0x3fecb153f02fb87d, 0x3fdc55f877b23537, // 0.89665, 0.44275 + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412 + 0x3feca62a772fd919, 0x3fdc8301b95b40c2, // 0.89528, 0.4455 + 0x3feca08f19b9c449, 0x3fdc997fc3865388, // 0.8946, 0.44687 + 0x3fec9aef521bd480, 0x3fdcaff964a0421d, // 0.89391, 0.44824 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec8fa287e13305, 0x3fdcdcdf5dc440ce, // 0.89253, 0.45098 + 0x3fec89f587029c13, 0x3fdcf34baee1cd21, // 0.89184, 0.45235 + 0x3fec84441f785f61, 0x3fdd09b389152ec1, // 0.89115, 0.45372 + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508 + 0x3fec78d41fe4a267, 0x3fdd3675caebf962, // 0.88975, 0.45645 + 0x3fec7315899eaad7, 0x3fdd4cd02ba8609c, // 0.88905, 0.45781 + 0x3fec6d5290341eb2, 0x3fdd632607ac9aa9, // 0.88835, 0.45918 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec61bf777fcc48, 0x3fdd8fc423c62a25, // 0.88693, 0.4619 + 0x3fec5bef59fef85a, 0x3fdda60c5cfa10d8, // 0.88622, 0.46326 + 0x3fec561adceb743e, 0x3fddbc5003b2edf8, // 0.88551, 0.46462 + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598 + 0x3fec4a64c7a5ac4c, 0x3fdde8c98bf86bd6, // 0.88408, 0.46733 + 0x3fec44833141c004, 0x3fddfeff66a941de, // 0.88336, 0.46869 + 0x3fec3e9d3ee7d262, 0x3fde1530a12779f4, // 0.88264, 0.47004 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec32c449f60831, 0x3fde418527dc4ffa, // 0.8812, 0.47275 + 0x3fec2cd14931e3f1, 0x3fde57a86d3cd824, // 0.88047, 0.4741 + 0x3fec26d9f01f2eaf, 0x3fde6dc704be97e2, // 0.87974, 0.47545 + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768 + 0x3fec1ade38bce19b, 0x3fde99f61c817eda, // 0.87828, 0.47815 + 0x3fec14d9dc465e58, 0x3fdeb00695f25620, // 0.87755, 0.47949 + 0x3fec0ed12b3372e9, 0x3fdec61253e3c61b, // 0.87681, 0.48084 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3fec02b2cef1e641, 0x3fdef21b8fafd3b5, // 0.87533, 0.48353 + 0x3febfc9d25a1b147, 0x3fdf081906bff7fd, // 0.87459, 0.48487 + 0x3febf6832b71ec5b, 0x3fdf1e11b4bbc35c, // 0.87384, 0.48621 + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755 + 0x3febea424837de6d, 0x3fdf49f4a7e97729, // 0.87235, 0.48889 + 0x3febe41b611154c1, 0x3fdf5fdee656cda3, // 0.8716, 0.49023 + 0x3febddf02cd2b983, 0x3fdf75c44e26a852, // 0.87084, 0.49156 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3febd18ce0dc19d6, 0x3fdfa1808c6cf7e0, // 0.86933, 0.49423 + 0x3febcb54cb0d2327, 0x3fdfb7575c24d2de, // 0.86857, 0.49557 + 0x3febc5186bf8361d, 0x3fdfcd2947c1ff57, // 0.86781, 0.4969 + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823 + 0x3febb892d5d5dad5, 0x3fdff8be6537615e, // 0.86628, 0.49956 + 0x3febb249a0b6c40d, 0x3fe00740c82b82e0, // 0.86551, 0.50089 + 0x3febabfc262e6586, 0x3fe0121fe4f56d2c, // 0.86474, 0.50221 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3feb9f5464c5bffc, 0x3fe027d6ad83287e, // 0.8632, 0.50486 + 0x3feb98fa1fd9155e, 0x3fe032ae55edbd95, // 0.86242, 0.50619 + 0x3feb929b996a5b7f, 0x3fe03d837edff370, // 0.86165, 0.50751 + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883 + 0x3feb85d1cbf52c02, 0x3fe053264bad0483, // 0.86009, 0.51015 + 0x3feb7f6686e792ea, 0x3fe05df3ec31b8b6, // 0.8593, 0.51147 + 0x3feb78f70449a34b, 0x3fe068bf0691c028, // 0.85852, 0.51279 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb6c0b4a55ac17, 0x3fe07e4da23bc102, // 0.85694, 0.51542 + 0x3feb658f14fdbc47, 0x3fe089112032b08c, // 0.85615, 0.51673 + 0x3feb5f0ea611a532, 0x3fe093d2115ee018, // 0.85535, 0.51804 + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936 + 0x3feb52011f805c92, 0x3fe0a94c46b53d0b, // 0.85376, 0.52067 + 0x3feb4b7409de7925, 0x3fe0b405878f85ec, // 0.85296, 0.52198 + 0x3feb44e2beaf0a61, 0x3fe0bebc34ff4646, // 0.85216, 0.52328 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb37b38bb54c09, 0x3fe0d421cf03c12b, // 0.85055, 0.5259 + 0x3feb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // 0.84974, 0.5272 + 0x3feb2a738eb51f33, 0x3fe0e97d078fd23b, // 0.84893, 0.5285 + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298 + 0x3feb1d22cfdadcc6, 0x3fe0fecdd1770537, // 0.84731, 0.5311 + 0x3feb16742a4ca2f5, 0x3fe1097248d0a956, // 0.84649, 0.5324 + 0x3feb0fc1575d33db, 0x3fe114141f935545, // 0.84567, 0.5337 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feb024f2d7d24a9, 0x3fe1294fe4c5350a, // 0.84403, 0.53629 + 0x3feafb8fd89f57b6, 0x3fe133e9cfee254e, // 0.84321, 0.53759 + 0x3feaf4cc5a85fb73, 0x3fe13e8113f396c1, // 0.84238, 0.53888 + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017 + 0x3feae738e6cd4b67, 0x3fe153a7a00bf453, // 0.84073, 0.54146 + 0x3feae068f345ecef, 0x3fe15e36e4dbe2bc, // 0.83989, 0.54275 + 0x3fead994dab2e979, 0x3fe168c37c025764, // 0.83906, 0.54404 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3feacbe03ea0e73b, 0x3fe17dd49ad16161, // 0.83739, 0.54661 + 0x3feac4ffbd3efac8, 0x3fe188591f3a46e5, // 0.83655, 0.54789 + 0x3feabe1b1b0b8dac, 0x3fe192daef7a5386, // 0.83571, 0.54918 + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046 + 0x3feab045787157ff, 0x3fe1a7d66d0516e6, // 0.83402, 0.55174 + 0x3feaa9547a2cb98e, 0x3fe1b250171373be, // 0.83317, 0.55302 + 0x3feaa25f5f5aee60, 0x3fe1bcc706804467, // 0.83232, 0.55429 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3fea9468d85b20ae, 0x3fe1d1acaf012cc2, // 0.83062, 0.55685 + 0x3fea8d676e545ad2, 0x3fe1dc1b64dc4872, // 0.82976, 0.55812 + 0x3fea8661ec0ee133, 0x3fe1e68759a3e074, // 0.8289, 0.55939 + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066 + 0x3fea784aa31d3f55, 0x3fe1fb56f98b37b8, // 0.82718, 0.56193 + 0x3fea7138de9d60f5, 0x3fe205baa17560d6, // 0.82632, 0.5632 + 0x3fea6a230637623b, 0x3fe2101b81e0da78, // 0.82546, 0.56447 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea5beb1e188375, 0x3fe224d4e5d5482e, // 0.82372, 0.567 + 0x3fea54c91090f524, 0x3fe22f2d662c13e1, // 0.82285, 0.56826 + 0x3fea4da2f385e997, 0x3fe23983189fdfd5, // 0.82198, 0.56952 + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078 + 0x3fea3f4a8f4ee2d2, 0x3fe24e260d7ee7c9, // 0.82023, 0.57204 + 0x3fea38184a593bc6, 0x3fe258734cbb7110, // 0.81935, 0.5733 + 0x3fea30e1fa4cbf81, 0x3fe262bdb7b795a2, // 0.81847, 0.57455 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea22693d62ccb9, 0x3fe2774a0a961612, // 0.8167, 0.57706 + 0x3fea1b26d2c0a75e, 0x3fe2818bef4d3cba, // 0.81581, 0.57831 + 0x3fea13e0617e4ec7, 0x3fe28bcaf96d94ba, // 0.81493, 0.57956 + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081 + 0x3fea05476f967bb5, 0x3fe2a040779843fb, // 0.81314, 0.58206 + 0x3fe9fdf4f13149de, 0x3fe2aa76e87aeb58, // 0.81225, 0.58331 + 0x3fe9f69e70ac75bc, 0x3fe2b4aa787764c4, // 0.81135, 0.58455 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9e7e56dcb45bd, 0x3fe2c908ef734e57, // 0.80956, 0.58704 + 0x3fe9e082edb42472, 0x3fe2d333d34e9bb7, // 0.80866, 0.58828 + 0x3fe9d91c7007d5a6, 0x3fe2dd5bcffb7616, // 0.80775, 0.58952 + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076 + 0x3fe9ca438080eadb, 0x3fe2f1a30d86773a, // 0.80594, 0.592 + 0x3fe9c2d110f075c3, 0x3fe2fbc24b441015, // 0.80503, 0.59323 + 0x3fe9bb5aa85f2098, 0x3fe305de9b921a94, // 0.80412, 0.59447 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe9ac61f0d4e247, 0x3fe31a0e6da35e44, // 0.80229, 0.59693 + 0x3fe9a4dfa42b06b2, 0x3fe32421ec49a620, // 0.80138, 0.59816 + 0x3fe99d59631e65d5, 0x3fe32e3277467d6b, // 0.80046, 0.59939 + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062 + 0x3fe98e410881a600, 0x3fe3424aac0ef7d6, // 0.79861, 0.60184 + 0x3fe986aef1457594, 0x3fe34c5252c14de1, // 0.79769, 0.60307 + 0x3fe97f18ea4e5c9e, 0x3fe35656ff9799ae, // 0.79676, 0.60429 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe96fe111ddfce0, 0x3fe36a576582831b, // 0.79491, 0.60673 + 0x3fe9683f42bd7fe1, 0x3fe374531b817f8d, // 0.79398, 0.60795 + 0x3fe960998893ad8c, 0x3fe37e4bd1792fe2, // 0.79304, 0.60917 + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038 + 0x3fe9514257dc4335, 0x3fe39234372c7f04, // 0.79117, 0.6116 + 0x3fe94990e3ac4a6c, 0x3fe39c23e3d63029, // 0.79023, 0.61281 + 0x3fe941db892e3a65, 0x3fe3a6108a54ba58, // 0.78929, 0.61402 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe932652609b1cf, 0x3fe3b9e0beb19e18, // 0.7874, 0.61644 + 0x3fe92aa41fc5a815, 0x3fe3c3c44981c517, // 0.78646, 0.61765 + 0x3fe922df37f8646a, 0x3fe3cda4c80a6076, // 0.78551, 0.61885 + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006 + 0x3fe91349c88da398, 0x3fe3e15c9a2db922, // 0.7836, 0.62126 + 0x3fe90b7943575efe, 0x3fe3eb33eabe0680, // 0.78265, 0.62246 + 0x3fe903a4e1665133, 0x3fe3f50828f1e8d2, // 0.78169, 0.62366 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe8f3f08c28d9ac, 0x3fe408a76834c0c0, // 0.77978, 0.62606 + 0x3fe8ec109b486c49, 0x3fe41272663d108c, // 0.77882, 0.62725 + 0x3fe8e42cd2852e0a, 0x3fe41c3a4bdbaa26, // 0.77785, 0.62845 + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964 + 0x3fe8d459be34bdfa, 0x3fe42fc0c7d3adbb, // 0.77592, 0.63083 + 0x3fe8cc6a75184655, 0x3fe4397f5b2a4380, // 0.77495, 0.63202 + 0x3fe8c47758fa71cb, 0x3fe4433ad0117b1d, // 0.77398, 0.63321 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe8b485aca2a468, 0x3fe456a858917046, // 0.77204, 0.63558 + 0x3fe8ac871ede1d88, 0x3fe4605a692b32a2, // 0.77106, 0.63676 + 0x3fe8a484c3031d50, 0x3fe46a095557a0f1, // 0.77008, 0.63794 + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912 + 0x3fe89474a5fb0a84, 0x3fe47d5dba6fde01, // 0.76812, 0.6403 + 0x3fe88c66e7481ba1, 0x3fe48703306091fe, // 0.76714, 0.64148 + 0x3fe884555f72fa6b, 0x3fe490a57bedbcdf, // 0.76615, 0.64266 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe87426f95cd5bd, 0x3fe4a3e08dec9ed6, // 0.76418, 0.645 + 0x3fe86c0a1d9aa195, 0x3fe4ad79516722f0, // 0.76319, 0.64618 + 0x3fe863e97db3d95a, 0x3fe4b70ee48fb869, // 0.7622, 0.64735 + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851 + 0x3fe8539cf67c9029, 0x3fe4ca30740218a3, // 0.76021, 0.64968 + 0x3fe84b7111af83f9, 0x3fe4d3bc6d589f80, // 0.75921, 0.65085 + 0x3fe843416dc4cce2, 0x3fe4dd453076b064, // 0.75821, 0.65201 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe832d6eda3a3e0, 0x3fe4f04d0e2859aa, // 0.75621, 0.65433 + 0x3fe82a9c13f545ff, 0x3fe4f9cc25cca486, // 0.7552, 0.65549 + 0x3fe8225d803964e5, 0x3fe503480159ded2, // 0.75419, 0.65665 + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781 + 0x3fe811d52faf94dc, 0x3fe51635fe5601d7, // 0.75218, 0.65896 + 0x3fe8098b756e52fa, 0x3fe51fa81cd99aa6, // 0.75117, 0.66011 + 0x3fe8013e0638e795, 0x3fe52916f96f8388, // 0.75015, 0.66127 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe7f0980e113978, 0x3fe53beae7012abe, // 0.74812, 0.66356 + 0x3fe7e83f87b03686, 0x3fe5454ff5159dfb, // 0.7471, 0.66471 + 0x3fe7dfe3517d8937, 0x3fe54eb1bb6dcb8f, // 0.74608, 0.66586 + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667 + 0x3fe7cf1fdacbf179, 0x3fe5616b6b204e6e, // 0.74403, 0.66814 + 0x3fe7c6b89ce2d333, 0x3fe56ac35197649e, // 0.74301, 0.66928 + 0x3fe7be4db453a27c, 0x3fe57417ea8bb75c, // 0.74198, 0.67042 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe7ad6ce874dbb6, 0x3fe586b72e2b2cfd, // 0.73992, 0.67269 + 0x3fe7a4f707bf97d2, 0x3fe59001d5f723df, // 0.73889, 0.67383 + 0x3fe79c7d8198e56e, 0x3fe599492a81ffbc, // 0.73785, 0.67496 + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609 + 0x3fe78b7f8a320a52, 0x3fe5abcdd41bb0d8, // 0.73578, 0.67722 + 0x3fe782fb1b90b35b, 0x3fe5b50b264f7448, // 0.73474, 0.67835 + 0x3fe77a730cbb9100, 0x3fe5be451f8bf980, // 0.7337, 0.67948 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe7695813b9b594, 0x3fe5d0af016ed1d4, // 0.73161, 0.68172 + 0x3fe760c52c304764, 0x3fe5d9dee73e345c, // 0.73056, 0.68285 + 0x3fe7582ea9b9a329, 0x3fe5e30b6e6877f3, // 0.72951, 0.68397 + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508 + 0x3fe746f6d9516d59, 0x3fe5f55a5b2576f8, // 0.72741, 0.6862 + 0x3fe73e558e079942, 0x3fe5fe7cbde56a0f, // 0.72636, 0.68732 + 0x3fe735b0ad2009b2, 0x3fe6079bbc5aadfa, // 0.7253, 0.68843 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe7245c2fcd492a, 0x3fe619cf86c55702, // 0.72319, 0.69065 + 0x3fe71bac960e41bf, 0x3fe622e44fec22ff, // 0.72213, 0.69176 + 0x3fe712f96c09d18d, 0x3fe62bf5af2b0dfd, // 0.72107, 0.69287 + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397 + 0x3fe701886c8f16e6, 0x3fe63e0e2a59d7aa, // 0.71894, 0.69508 + 0x3fe6f8ca99c95b75, 0x3fe64715437f535b, // 0.71787, 0.69618 + 0x3fe6f0093c1f54de, 0x3fe65018ed28287f, // 0.7168, 0.69728 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6de7be585881d, 0x3fe66215ec74eb91, // 0.71466, 0.69947 + 0x3fe6d5afef4aafcc, 0x3fe66b0f3f52b386, // 0.71358, 0.70057 + 0x3fe6cce07395679f, 0x3fe674051d27896c, // 0.71251, 0.70166 + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275 + 0x3fe6bb36f12b5e06, 0x3fe685e6742feeef, // 0.71035, 0.70385 + 0x3fe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // 0.70927, 0.70493 + 0x3fe6a97f692c82ea, 0x3fe697b9e686941c, // 0.70819, 0.70602 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe697b9e686941c, 0x3fe6a97f692c82ea, // 0.70602, 0.70819 + 0x3fe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // 0.70493, 0.70927 + 0x3fe685e6742feeef, 0x3fe6bb36f12b5e06, // 0.70385, 0.71035 + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143 + 0x3fe674051d27896c, 0x3fe6cce07395679f, // 0.70166, 0.71251 + 0x3fe66b0f3f52b386, 0x3fe6d5afef4aafcc, // 0.70057, 0.71358 + 0x3fe66215ec74eb91, 0x3fe6de7be585881d, // 0.69947, 0.71466 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe65018ed28287f, 0x3fe6f0093c1f54de, // 0.69728, 0.7168 + 0x3fe64715437f535b, 0x3fe6f8ca99c95b75, // 0.69618, 0.71787 + 0x3fe63e0e2a59d7aa, 0x3fe701886c8f16e6, // 0.69508, 0.71894 + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72 + 0x3fe62bf5af2b0dfd, 0x3fe712f96c09d18d, // 0.69287, 0.72107 + 0x3fe622e44fec22ff, 0x3fe71bac960e41bf, // 0.69176, 0.72213 + 0x3fe619cf86c55702, 0x3fe7245c2fcd492a, // 0.69065, 0.72319 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe6079bbc5aadfa, 0x3fe735b0ad2009b2, // 0.68843, 0.7253 + 0x3fe5fe7cbde56a0f, 0x3fe73e558e079942, // 0.68732, 0.72636 + 0x3fe5f55a5b2576f8, 0x3fe746f6d9516d59, // 0.6862, 0.72741 + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846 + 0x3fe5e30b6e6877f3, 0x3fe7582ea9b9a329, // 0.68397, 0.72951 + 0x3fe5d9dee73e345c, 0x3fe760c52c304764, // 0.68285, 0.73056 + 0x3fe5d0af016ed1d4, 0x3fe7695813b9b594, // 0.68172, 0.73161 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe5be451f8bf980, 0x3fe77a730cbb9100, // 0.67948, 0.7337 + 0x3fe5b50b264f7448, 0x3fe782fb1b90b35b, // 0.67835, 0.73474 + 0x3fe5abcdd41bb0d8, 0x3fe78b7f8a320a52, // 0.67722, 0.73578 + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682 + 0x3fe599492a81ffbc, 0x3fe79c7d8198e56e, // 0.67496, 0.73785 + 0x3fe59001d5f723df, 0x3fe7a4f707bf97d2, // 0.67383, 0.73889 + 0x3fe586b72e2b2cfd, 0x3fe7ad6ce874dbb6, // 0.67269, 0.73992 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe57417ea8bb75c, 0x3fe7be4db453a27c, // 0.67042, 0.74198 + 0x3fe56ac35197649e, 0x3fe7c6b89ce2d333, // 0.66928, 0.74301 + 0x3fe5616b6b204e6e, 0x3fe7cf1fdacbf179, // 0.66814, 0.74403 + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506 + 0x3fe54eb1bb6dcb8f, 0x3fe7dfe3517d8937, // 0.66586, 0.74608 + 0x3fe5454ff5159dfb, 0x3fe7e83f87b03686, // 0.66471, 0.7471 + 0x3fe53beae7012abe, 0x3fe7f0980e113978, // 0.66356, 0.74812 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe52916f96f8388, 0x3fe8013e0638e795, // 0.66127, 0.75015 + 0x3fe51fa81cd99aa6, 0x3fe8098b756e52fa, // 0.66011, 0.75117 + 0x3fe51635fe5601d7, 0x3fe811d52faf94dc, // 0.65896, 0.75218 + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319 + 0x3fe503480159ded2, 0x3fe8225d803964e5, // 0.65665, 0.75419 + 0x3fe4f9cc25cca486, 0x3fe82a9c13f545ff, // 0.65549, 0.7552 + 0x3fe4f04d0e2859aa, 0x3fe832d6eda3a3e0, // 0.65433, 0.75621 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe4dd453076b064, 0x3fe843416dc4cce2, // 0.65201, 0.75821 + 0x3fe4d3bc6d589f80, 0x3fe84b7111af83f9, // 0.65085, 0.75921 + 0x3fe4ca30740218a3, 0x3fe8539cf67c9029, // 0.64968, 0.76021 + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612 + 0x3fe4b70ee48fb869, 0x3fe863e97db3d95a, // 0.64735, 0.7622 + 0x3fe4ad79516722f0, 0x3fe86c0a1d9aa195, // 0.64618, 0.76319 + 0x3fe4a3e08dec9ed6, 0x3fe87426f95cd5bd, // 0.645, 0.76418 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe490a57bedbcdf, 0x3fe884555f72fa6b, // 0.64266, 0.76615 + 0x3fe48703306091fe, 0x3fe88c66e7481ba1, // 0.64148, 0.76714 + 0x3fe47d5dba6fde01, 0x3fe89474a5fb0a84, // 0.6403, 0.76812 + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691 + 0x3fe46a095557a0f1, 0x3fe8a484c3031d50, // 0.63794, 0.77008 + 0x3fe4605a692b32a2, 0x3fe8ac871ede1d88, // 0.63676, 0.77106 + 0x3fe456a858917046, 0x3fe8b485aca2a468, // 0.63558, 0.77204 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe4433ad0117b1d, 0x3fe8c47758fa71cb, // 0.63321, 0.77398 + 0x3fe4397f5b2a4380, 0x3fe8cc6a75184655, // 0.63202, 0.77495 + 0x3fe42fc0c7d3adbb, 0x3fe8d459be34bdfa, // 0.63083, 0.77592 + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689 + 0x3fe41c3a4bdbaa26, 0x3fe8e42cd2852e0a, // 0.62845, 0.77785 + 0x3fe41272663d108c, 0x3fe8ec109b486c49, // 0.62725, 0.77882 + 0x3fe408a76834c0c0, 0x3fe8f3f08c28d9ac, // 0.62606, 0.77978 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe3f50828f1e8d2, 0x3fe903a4e1665133, // 0.62366, 0.78169 + 0x3fe3eb33eabe0680, 0x3fe90b7943575efe, // 0.62246, 0.78265 + 0x3fe3e15c9a2db922, 0x3fe91349c88da398, // 0.62126, 0.7836 + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456 + 0x3fe3cda4c80a6076, 0x3fe922df37f8646a, // 0.61885, 0.78551 + 0x3fe3c3c44981c517, 0x3fe92aa41fc5a815, // 0.61765, 0.78646 + 0x3fe3b9e0beb19e18, 0x3fe932652609b1cf, // 0.61644, 0.7874 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe3a6108a54ba58, 0x3fe941db892e3a65, // 0.61402, 0.78929 + 0x3fe39c23e3d63029, 0x3fe94990e3ac4a6c, // 0.61281, 0.79023 + 0x3fe39234372c7f04, 0x3fe9514257dc4335, // 0.6116, 0.79117 + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211 + 0x3fe37e4bd1792fe2, 0x3fe960998893ad8c, // 0.60917, 0.79304 + 0x3fe374531b817f8d, 0x3fe9683f42bd7fe1, // 0.60795, 0.79398 + 0x3fe36a576582831b, 0x3fe96fe111ddfce0, // 0.60673, 0.79491 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe35656ff9799ae, 0x3fe97f18ea4e5c9e, // 0.60429, 0.79676 + 0x3fe34c5252c14de1, 0x3fe986aef1457594, // 0.60307, 0.79769 + 0x3fe3424aac0ef7d6, 0x3fe98e410881a600, // 0.60184, 0.79861 + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954 + 0x3fe32e3277467d6b, 0x3fe99d59631e65d5, // 0.59939, 0.80046 + 0x3fe32421ec49a620, 0x3fe9a4dfa42b06b2, // 0.59816, 0.80138 + 0x3fe31a0e6da35e44, 0x3fe9ac61f0d4e247, // 0.59693, 0.80229 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe305de9b921a94, 0x3fe9bb5aa85f2098, // 0.59447, 0.80412 + 0x3fe2fbc24b441015, 0x3fe9c2d110f075c3, // 0.59323, 0.80503 + 0x3fe2f1a30d86773a, 0x3fe9ca438080eadb, // 0.592, 0.80594 + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685 + 0x3fe2dd5bcffb7616, 0x3fe9d91c7007d5a6, // 0.58952, 0.80775 + 0x3fe2d333d34e9bb7, 0x3fe9e082edb42472, // 0.58828, 0.80866 + 0x3fe2c908ef734e57, 0x3fe9e7e56dcb45bd, // 0.58704, 0.80956 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe2b4aa787764c4, 0x3fe9f69e70ac75bc, // 0.58455, 0.81135 + 0x3fe2aa76e87aeb58, 0x3fe9fdf4f13149de, // 0.58331, 0.81225 + 0x3fe2a040779843fb, 0x3fea05476f967bb5, // 0.58206, 0.81314 + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404 + 0x3fe28bcaf96d94ba, 0x3fea13e0617e4ec7, // 0.57956, 0.81493 + 0x3fe2818bef4d3cba, 0x3fea1b26d2c0a75e, // 0.57831, 0.81581 + 0x3fe2774a0a961612, 0x3fea22693d62ccb9, // 0.57706, 0.8167 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe262bdb7b795a2, 0x3fea30e1fa4cbf81, // 0.57455, 0.81847 + 0x3fe258734cbb7110, 0x3fea38184a593bc6, // 0.5733, 0.81935 + 0x3fe24e260d7ee7c9, 0x3fea3f4a8f4ee2d2, // 0.57204, 0.82023 + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211 + 0x3fe23983189fdfd5, 0x3fea4da2f385e997, // 0.56952, 0.82198 + 0x3fe22f2d662c13e1, 0x3fea54c91090f524, // 0.56826, 0.82285 + 0x3fe224d4e5d5482e, 0x3fea5beb1e188375, // 0.567, 0.82372 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe2101b81e0da78, 0x3fea6a230637623b, // 0.56447, 0.82546 + 0x3fe205baa17560d6, 0x3fea7138de9d60f5, // 0.5632, 0.82632 + 0x3fe1fb56f98b37b8, 0x3fea784aa31d3f55, // 0.56193, 0.82718 + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805 + 0x3fe1e68759a3e074, 0x3fea8661ec0ee133, // 0.55939, 0.8289 + 0x3fe1dc1b64dc4872, 0x3fea8d676e545ad2, // 0.55812, 0.82976 + 0x3fe1d1acaf012cc2, 0x3fea9468d85b20ae, // 0.55685, 0.83062 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe1bcc706804467, 0x3feaa25f5f5aee60, // 0.55429, 0.83232 + 0x3fe1b250171373be, 0x3feaa9547a2cb98e, // 0.55302, 0.83317 + 0x3fe1a7d66d0516e6, 0x3feab045787157ff, // 0.55174, 0.83402 + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486 + 0x3fe192daef7a5386, 0x3feabe1b1b0b8dac, // 0.54918, 0.83571 + 0x3fe188591f3a46e5, 0x3feac4ffbd3efac8, // 0.54789, 0.83655 + 0x3fe17dd49ad16161, 0x3feacbe03ea0e73b, // 0.54661, 0.83739 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe168c37c025764, 0x3fead994dab2e979, // 0.54404, 0.83906 + 0x3fe15e36e4dbe2bc, 0x3feae068f345ecef, // 0.54275, 0.83989 + 0x3fe153a7a00bf453, 0x3feae738e6cd4b67, // 0.54146, 0.84073 + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155 + 0x3fe13e8113f396c1, 0x3feaf4cc5a85fb73, // 0.53888, 0.84238 + 0x3fe133e9cfee254e, 0x3feafb8fd89f57b6, // 0.53759, 0.84321 + 0x3fe1294fe4c5350a, 0x3feb024f2d7d24a9, // 0.53629, 0.84403 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe114141f935545, 0x3feb0fc1575d33db, // 0.5337, 0.84567 + 0x3fe1097248d0a956, 0x3feb16742a4ca2f5, // 0.5324, 0.84649 + 0x3fe0fecdd1770537, 0x3feb1d22cfdadcc6, // 0.5311, 0.84731 + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812 + 0x3fe0e97d078fd23b, 0x3feb2a738eb51f33, // 0.5285, 0.84893 + 0x3fe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // 0.5272, 0.84974 + 0x3fe0d421cf03c12b, 0x3feb37b38bb54c09, // 0.5259, 0.85055 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe0bebc34ff4646, 0x3feb44e2beaf0a61, // 0.52328, 0.85216 + 0x3fe0b405878f85ec, 0x3feb4b7409de7925, // 0.52198, 0.85296 + 0x3fe0a94c46b53d0b, 0x3feb52011f805c92, // 0.52067, 0.85376 + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456 + 0x3fe093d2115ee018, 0x3feb5f0ea611a532, // 0.51804, 0.85535 + 0x3fe089112032b08c, 0x3feb658f14fdbc47, // 0.51673, 0.85615 + 0x3fe07e4da23bc102, 0x3feb6c0b4a55ac17, // 0.51542, 0.85694 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe068bf0691c028, 0x3feb78f70449a34b, // 0.51279, 0.85852 + 0x3fe05df3ec31b8b6, 0x3feb7f6686e792ea, // 0.51147, 0.8593 + 0x3fe053264bad0483, 0x3feb85d1cbf52c02, // 0.51015, 0.86009 + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087 + 0x3fe03d837edff370, 0x3feb929b996a5b7f, // 0.50751, 0.86165 + 0x3fe032ae55edbd95, 0x3feb98fa1fd9155e, // 0.50619, 0.86242 + 0x3fe027d6ad83287e, 0x3feb9f5464c5bffc, // 0.50486, 0.8632 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fe0121fe4f56d2c, 0x3febabfc262e6586, // 0.50221, 0.86474 + 0x3fe00740c82b82e0, 0x3febb249a0b6c40d, // 0.50089, 0.86551 + 0x3fdff8be6537615e, 0x3febb892d5d5dad5, // 0.49956, 0.86628 + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705 + 0x3fdfcd2947c1ff57, 0x3febc5186bf8361d, // 0.4969, 0.86781 + 0x3fdfb7575c24d2de, 0x3febcb54cb0d2327, // 0.49557, 0.86857 + 0x3fdfa1808c6cf7e0, 0x3febd18ce0dc19d6, // 0.49423, 0.86933 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdf75c44e26a852, 0x3febddf02cd2b983, // 0.49156, 0.87084 + 0x3fdf5fdee656cda3, 0x3febe41b611154c1, // 0.49023, 0.8716 + 0x3fdf49f4a7e97729, 0x3febea424837de6d, // 0.48889, 0.87235 + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309 + 0x3fdf1e11b4bbc35c, 0x3febf6832b71ec5b, // 0.48621, 0.87384 + 0x3fdf081906bff7fd, 0x3febfc9d25a1b147, // 0.48487, 0.87459 + 0x3fdef21b8fafd3b5, 0x3fec02b2cef1e641, // 0.48353, 0.87533 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fdec61253e3c61b, 0x3fec0ed12b3372e9, // 0.48084, 0.87681 + 0x3fdeb00695f25620, 0x3fec14d9dc465e58, // 0.47949, 0.87755 + 0x3fde99f61c817eda, 0x3fec1ade38bce19b, // 0.47815, 0.87828 + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901 + 0x3fde6dc704be97e2, 0x3fec26d9f01f2eaf, // 0.47545, 0.87974 + 0x3fde57a86d3cd824, 0x3fec2cd14931e3f1, // 0.4741, 0.88047 + 0x3fde418527dc4ffa, 0x3fec32c449f60831, // 0.47275, 0.8812 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fde1530a12779f4, 0x3fec3e9d3ee7d262, // 0.47004, 0.88264 + 0x3fddfeff66a941de, 0x3fec44833141c004, // 0.46869, 0.88336 + 0x3fdde8c98bf86bd6, 0x3fec4a64c7a5ac4c, // 0.46733, 0.88408 + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848 + 0x3fddbc5003b2edf8, 0x3fec561adceb743e, // 0.46462, 0.88551 + 0x3fdda60c5cfa10d8, 0x3fec5bef59fef85a, // 0.46326, 0.88622 + 0x3fdd8fc423c62a25, 0x3fec61bf777fcc48, // 0.4619, 0.88693 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdd632607ac9aa9, 0x3fec6d5290341eb2, // 0.45918, 0.88835 + 0x3fdd4cd02ba8609c, 0x3fec7315899eaad7, // 0.45781, 0.88905 + 0x3fdd3675caebf962, 0x3fec78d41fe4a267, // 0.45645, 0.88975 + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045 + 0x3fdd09b389152ec1, 0x3fec84441f785f61, // 0.45372, 0.89115 + 0x3fdcf34baee1cd21, 0x3fec89f587029c13, // 0.45235, 0.89184 + 0x3fdcdcdf5dc440ce, 0x3fec8fa287e13305, // 0.45098, 0.89253 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdcaff964a0421d, 0x3fec9aef521bd480, // 0.44824, 0.89391 + 0x3fdc997fc3865388, 0x3feca08f19b9c449, // 0.44687, 0.8946 + 0x3fdc8301b95b40c2, 0x3feca62a772fd919, // 0.4455, 0.89528 + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597 + 0x3fdc55f877b23537, 0x3fecb153f02fb87d, // 0.44275, 0.89665 + 0x3fdc3f6d47263129, 0x3fecb6e20a00da99, // 0.44137, 0.89732 + 0x3fdc28ddbb6cf145, 0x3fecbc6bb638d10b, // 0.43999, 0.898 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdbfbb1a05e0edc, 0x3fecc771c2736c09, // 0.43724, 0.89935 + 0x3fdbe51517ffc0d9, 0x3fecccee20c2de9f, // 0.43586, 0.90002 + 0x3fdbce744262deee, 0x3fecd2660e12c1e6, // 0.43448, 0.90068 + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135 + 0x3fdba125bd63583e, 0x3fecdd489254fe65, // 0.43171, 0.90201 + 0x3fdb8a7814fd5693, 0x3fece2b32799a060, // 0.43033, 0.90267 + 0x3fdb73c62d520624, 0x3fece819488344ce, // 0.42894, 0.90333 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdb4655ae2bf757, 0x3fecf2d829f1b40e, // 0.42617, 0.90464 + 0x3fdb2f971db31972, 0x3fecf830e8ce467b, // 0.42478, 0.9053 + 0x3fdb18d45bf8aca6, 0x3fecfd852fff6ad4, // 0.42339, 0.90595 + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066 + 0x3fdaeb4252ca07ab, 0x3fed082054168bac, // 0.42061, 0.90724 + 0x3fdad473125cdc08, 0x3fed0d672f59d2b9, // 0.41922, 0.90789 + 0x3fdabd9faebc3980, 0x3fed12a98fac410c, // 0.41782, 0.90853 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fda8fec8bf5b166, 0x3fed1d20dc40c15c, // 0.41503, 0.90981 + 0x3fda790cd3dbf31a, 0x3fed2255c6e5a4e1, // 0.41364, 0.91044 + 0x3fda622906a70b63, 0x3fed2786335f52fc, // 0.41224, 0.91107 + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171 + 0x3fda34553b0afee5, 0x3fed31d98e9e503a, // 0.40944, 0.91234 + 0x3fda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // 0.40804, 0.91296 + 0x3fda067145664d57, 0x3fed3c1ae79f2b4e, // 0.40664, 0.91359 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fd9d87d4207b0ab, 0x3fed464a380e7242, // 0.40384, 0.91483 + 0x3fd9c17d440df9f2, 0x3fed4b5b1b187524, // 0.40243, 0.91545 + 0x3fd9aa794d47c9ee, 0x3fed506779a3d2d9, // 0.40103, 0.91606 + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668 + 0x3fd97c6583890fc2, 0x3fed5a72a6221e73, // 0.39822, 0.91729 + 0x3fd96555b7ab948f, 0x3fed5f7172888a7f, // 0.39681, 0.9179 + 0x3fd94e420137bce3, 0x3fed646bb7574de5, // 0.3954, 0.91851 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd9200ee2c9be97, 0x3fed6e52a71c8547, // 0.39258, 0.91972 + 0x3fd908ef81ef7bd1, 0x3fed733f508c0dff, // 0.39117, 0.92032 + 0x3fd8f1cc44bea329, 0x3fed78276f5617c6, // 0.38976, 0.92092 + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151 + 0x3fd8c37a439f884f, 0x3fed81ea09f38b63, // 0.38693, 0.92211 + 0x3fd8ac4b86d5ed44, 0x3fed86c48445a450, // 0.38552, 0.9227 + 0x3fd89518fbff098e, 0x3fed8b9a70ef9cb4, // 0.3841, 0.92329 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd866a88a792ea0, 0x3fed95389e50429b, // 0.38127, 0.92447 + 0x3fd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // 0.37985, 0.92505 + 0x3fd838290bb359c8, 0x3fed9ec48c26b1f3, // 0.37843, 0.92563 + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621 + 0x3fd8099a9c5c362d, 0x3feda83e348f613b, // 0.37559, 0.92679 + 0x3fd7f24dd37341e3, 0x3fedacf42ce68ab9, // 0.37416, 0.92736 + 0x3fd7dafd592ba621, 0x3fedb1a591b20c38, // 0.37274, 0.92794 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd7ac515ee2b172, 0x3fedbafa9dc1b78d, // 0.36989, 0.92907 + 0x3fd794f5e613dfae, 0x3fedbf9e4395759a, // 0.36847, 0.92964 + 0x3fd77d96ca4b73a6, 0x3fedc43d52fcb453, // 0.36704, 0.93021 + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077 + 0x3fd74ecdb8390a3e, 0x3fedcd6dabaca3a5, // 0.36418, 0.93133 + 0x3fd73763c9261092, 0x3fedd1fef38a915a, // 0.36276, 0.93188 + 0x3fd71ff6458782ec, 0x3fedd68ba2267a25, // 0.36133, 0.93244 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd6f1108f1bc9c5, 0x3feddf9730ca837b, // 0.35846, 0.93354 + 0x3fd6d998638a0cb5, 0x3fede4160f6d8d81, // 0.35703, 0.93409 + 0x3fd6c21cb1e39771, 0x3fede890520465ce, // 0.3556, 0.93464 + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518 + 0x3fd6931acad55f51, 0x3fedf177004b2534, // 0.35273, 0.93573 + 0x3fd67b949cad63ca, 0x3fedf5e36a9ba59c, // 0.35129, 0.93627 + 0x3fd6640af6f03d9e, 0x3fedfa4b3621271d, // 0.34986, 0.9368 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd634ed533be58e, 0x3fee030cee1435b8, // 0.34698, 0.93787 + 0x3fd61d595c88c203, 0x3fee0766d9280f54, // 0.34554, 0.9384 + 0x3fd605c1fcc88f63, 0x3fee0bbc22bd8349, // 0.3441, 0.93893 + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946 + 0x3fd5d68910aee686, 0x3fee1458cec1ad83, // 0.34122, 0.93998 + 0x3fd5bee78b9db3b6, 0x3fee18a02fdc66d9, // 0.33978, 0.94051 + 0x3fd5a742ac0ff78d, 0x3fee1ce2ecd0c0d8, // 0.33833, 0.94103 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd577eeec151e47, 0x3fee255a77a63bb8, // 0.33545, 0.94206 + 0x3fd5604012f467b4, 0x3fee298f4439197a, // 0.334, 0.94257 + 0x3fd5488dedeff3be, 0x3fee2dbf6a0911d9, // 0.33255, 0.94308 + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359 + 0x3fd5191fceda3c35, 0x3fee3611becbaf69, // 0.32966, 0.9441 + 0x3fd50163dc197047, 0x3fee3a33ec75ce85, // 0.32821, 0.9446 + 0x3fd4e9a4ac15d520, 0x3fee3e5170cbfc46, // 0.32676, 0.94511 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd4ba1ca2eca31c, 0x3fee467e7af35f23, // 0.32386, 0.94611 + 0x3fd4a253d11b82f3, 0x3fee4a8dff81ce5e, // 0.32241, 0.9466 + 0x3fd48a87d0b07fd7, 0x3fee4e98d836c0af, // 0.32096, 0.94709 + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759 + 0x3fd45ae652bb2800, 0x3fee56a083968eb1, // 0.31805, 0.94807 + 0x3fd44310dc8936f0, 0x3fee5a9d550467d3, // 0.31659, 0.94856 + 0x3fd42b38466e2928, 0x3fee5e95781ebf1c, // 0.31514, 0.94905 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd3fb7dc932cfa4, 0x3fee6677b0e6d31e, // 0.31222, 0.95001 + 0x3fd3e39be96ec271, 0x3fee6a61c55d53a7, // 0.31077, 0.95049 + 0x3fd3cbb6f87a146e, 0x3fee6e472911da27, // 0.30931, 0.95096 + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144 + 0x3fd39be3f1bc8aef, 0x3fee7603dbce74e9, // 0.30639, 0.95191 + 0x3fd383f5e353b6aa, 0x3fee79db29a5165a, // 0.30493, 0.95238 + 0x3fd36c04d27a4edf, 0x3fee7dadc456d850, // 0.30347, 0.95284 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd33c19b83af207, 0x3fee8544ddf0d075, // 0.30054, 0.95377 + 0x3fd3241fb638baaf, 0x3fee89095bad6025, // 0.29908, 0.95423 + 0x3fd30c22c08d6a13, 0x3fee8cc923edc388, // 0.29762, 0.95469 + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514 + 0x3fd2dc200907fe51, 0x3fee943a91aab4b4, // 0.29469, 0.95559 + 0x3fd2c41a4e954520, 0x3fee97ec36016b30, // 0.29322, 0.95605 + 0x3fd2ac11af483572, 0x3fee9b99229046f8, // 0.29175, 0.95649 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd27bf7d0f2c346, 0x3feea2e4d212c000, // 0.28882, 0.95738 + 0x3fd263e6995554ba, 0x3feea68393e65800, // 0.28735, 0.95783 + 0x3fd24bd28bb37672, 0x3feeaa1d9bb20af3, // 0.28588, 0.95827 + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587 + 0x3fd21ba1fd3d2623, 0x3feeb1437af9bb34, // 0.28294, 0.95914 + 0x3fd2038583d727bd, 0x3feeb4cf515b8811, // 0.28146, 0.95957 + 0x3fd1eb6643499fbb, 0x3feeb8566b810f2a, // 0.27999, 0.96 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd1bb1f7b999480, 0x3feebf5668eaf2ef, // 0.27705, 0.96086 + 0x3fd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // 0.27557, 0.96128 + 0x3fd18acdc3f4873a, 0x3feec6436ee60309, // 0.2741, 0.9617 + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212 + 0x3fd15a713a28b9d9, 0x3feecd1d792c8f10, // 0.27115, 0.96254 + 0x3fd1423eefc69378, 0x3feed0835e999009, // 0.26967, 0.96295 + 0x3fd12a09fc0b1b12, 0x3feed3e483849c51, // 0.26819, 0.96337 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd0f998277733f7, 0x3feeda9889bfe86a, // 0.26523, 0.96418 + 0x3fd0e15b4e1749cd, 0x3feeddeb6a078651, // 0.26375, 0.96459 + 0x3fd0c91bda4f158d, 0x3feee13987bbebdc, // 0.26227, 0.96499 + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539 + 0x3fd09895327b465e, 0x3feee7c77961dc9e, // 0.25931, 0.96579 + 0x3fd0804e05eb661e, 0x3feeeb074c50a544, // 0.25783, 0.96619 + 0x3fd068044deab002, 0x3feeee425aa6b09a, // 0.25635, 0.96658 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fd037694a928cac, 0x3feef4aa278b2032, // 0.25338, 0.96737 + 0x3fd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // 0.2519, 0.96775 + 0x3fd006c4466e54af, 0x3feefafedc1ba8b7, // 0.25041, 0.96814 + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852 + 0x3fcfac2abeff57ff, 0x3fef014074708ed3, // 0.24744, 0.9689 + 0x3fcf7b7480bd3801, 0x3fef045a14cf738c, // 0.24596, 0.96928 + 0x3fcf4ab9679c9f5c, 0x3fef076eecade0fa, // 0.24447, 0.96966 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fcee934c2d006c7, 0x3fef0d8a410379c5, // 0.24149, 0.9704 + 0x3fceb86b462de348, 0x3fef1090bc898f5f, // 0.24, 0.97077 + 0x3fce879d0cc0fdaf, 0x3fef13926dad024e, // 0.23851, 0.97114 + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715 + 0x3fce25f281a2b684, 0x3fef19876ef1f486, // 0.23553, 0.97187 + 0x3fcdf5163f01099a, 0x3fef1c7abe284708, // 0.23404, 0.97223 + 0x3fcdc4355db40195, 0x3fef1f6941259d7a, // 0.23255, 0.97258 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcd6265dd3f27e3, 0x3fef2537e0a71f9f, // 0.22957, 0.97329 + 0x3fcd31774d2cbdee, 0x3fef2817fc4609ce, // 0.22807, 0.97364 + 0x3fcd00843c99c5f9, 0x3fef2af349e17507, // 0.22658, 0.97399 + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434 + 0x3fcc9e90b824a6a9, 0x3fef309b794b719f, // 0.22359, 0.97468 + 0x3fcc6d90535d74dc, 0x3fef33685a3aaef0, // 0.22209, 0.97503 + 0x3fcc3c8b8c4b9dd7, 0x3fef36306b67c556, // 0.2206, 0.97536 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcbda74f5856330, 0x3fef3bb21cc4fe47, // 0.2176, 0.97604 + 0x3fcba96334f15dad, 0x3fef3e6bbc1bbc65, // 0.21611, 0.97637 + 0x3fcb784d30536cda, 0x3fef412089fd8adc, // 0.21461, 0.9767 + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703 + 0x3fcb16147941ca2a, 0x3fef467bafb7bbe0, // 0.21161, 0.97735 + 0x3fcae4f1d5f3b9ab, 0x3fef492206bcabb4, // 0.21011, 0.97768 + 0x3fcab3cb0ce6fe44, 0x3fef4bc38aa5c694, // 0.20861, 0.978 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fca517127e3dabc, 0x3fef50f81785c6b9, // 0.20561, 0.97863 + 0x3fca203e1b1831da, 0x3fef538b1faf2d07, // 0.20411, 0.97895 + 0x3fc9ef0706e35a35, 0x3fef56195321c090, // 0.20261, 0.97926 + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957 + 0x3fc98c8ce69a7aec, 0x3fef5b273a4fa2d9, // 0.1996, 0.97988 + 0x3fc95b49e9b62af9, 0x3fef5da6ed43685d, // 0.1981, 0.98018 + 0x3fc92a0303c8194f, 0x3fef6021c9f148c2, // 0.19659, 0.98048 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc8c7699b34ca7e, 0x3fef6508fef47bd5, // 0.19359, 0.98108 + 0x3fc8961727c41804, 0x3fef677556883cee, // 0.19208, 0.98138 + 0x3fc864c0e9b2b6cf, 0x3fef69dcd652f5de, // 0.19057, 0.98167 + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196 + 0x3fc802092c1d744b, 0x3fef6e9d4d1262ca, // 0.18756, 0.98225 + 0x3fc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // 0.18606, 0.98254 + 0x3fc79f429f59e11d, 0x3fef734a60446279, // 0.18455, 0.98282 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc73c6d8055fe0a, 0x3fef77e40d068a90, // 0.18153, 0.98339 + 0x3fc70afd8d08c4ff, 0x3fef7a299c1a322a, // 0.18002, 0.98366 + 0x3fc6d98a0c08c8da, 0x3fef7c6a50826840, // 0.17851, 0.98394 + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421 + 0x3fc676987f7216b8, 0x3fef80dd27ed8204, // 0.17549, 0.98448 + 0x3fc6451a831d830d, 0x3fef830f4a40c60c, // 0.17398, 0.98475 + 0x3fc61399179a6e94, 0x3fef853c9089595e, // 0.17247, 0.98501 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc5b08c1192e381, 0x3fef898887a36c84, // 0.16945, 0.98554 + 0x3fc57f008654cbde, 0x3fef8ba737cb4b78, // 0.16794, 0.9858 + 0x3fc54d71aa74ef02, 0x3fef8dc10a95380d, // 0.16643, 0.98605 + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631 + 0x3fc4ea4a1f624b61, 0x3fef91e616c43891, // 0.1634, 0.98656 + 0x3fc4b8b17f79fa88, 0x3fef93f14f85ac08, // 0.16189, 0.98681 + 0x3fc48715ad84cdf5, 0x3fef95f7a9a1ec47, // 0.16037, 0.98706 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc423d4920e4166, 0x3fef99f5c0abd496, // 0.15734, 0.98754 + 0x3fc3f22f57db4893, 0x3fef9bed7cfbde29, // 0.15583, 0.98778 + 0x3fc3c0870a383ff6, 0x3fef9de0596b77a3, // 0.15431, 0.98802 + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826 + 0x3fc35d2d53440db2, 0x3fefa1b7717661d5, // 0.15128, 0.98849 + 0x3fc32b7bf94516a7, 0x3fefa39bac7a1791, // 0.14976, 0.98872 + 0x3fc2f9c7aa7a72af, 0x3fefa57b066e2754, // 0.14825, 0.98895 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc296564d2b953e, 0x3fefa92b1600657c, // 0.14521, 0.9894 + 0x3fc264994dfd340a, 0x3fefaafbcb0cfddc, // 0.1437, 0.98962 + 0x3fc232d978aed413, 0x3fefacc79de6c44f, // 0.14218, 0.98984 + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006 + 0x3fc1cf516a62a077, 0x3fefb0509be6f7db, // 0.13914, 0.99027 + 0x3fc19d8940be24e7, 0x3fefb20dc681d54d, // 0.13762, 0.99049 + 0x3fc16bbe5fac5865, 0x3fefb3c60dd2c199, // 0.1361, 0.9907 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fc1082095f820b0, 0x3fefb727f187f1c7, // 0.13306, 0.99111 + 0x3fc0d64dbcb26786, 0x3fefb8d18d66adb7, // 0.13154, 0.99131 + 0x3fc0a4784ab8bf1d, 0x3fefba7644f068b5, // 0.13002, 0.99151 + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171 + 0x3fc040c5bb67747e, 0x3fefbdb106021816, // 0.12698, 0.99191 + 0x3fc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // 0.12545, 0.9921 + 0x3fbfba124b07ad85, 0x3fefc0d832bf043a, // 0.12393, 0.99229 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fbef2858d27561b, 0x3fefc3ebc935454c, // 0.12089, 0.99267 + 0x3fbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // 0.11937, 0.99285 + 0x3fbe2ae5b8457f77, 0x3fefc6ebc77f0887, // 0.11784, 0.99303 + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321 + 0x3fbd633347858ce4, 0x3fefc9d82bc2915e, // 0.11479, 0.99339 + 0x3fbcff533b307dc1, 0x3fefcb4703914354, // 0.11327, 0.99356 + 0x3fbc9b6eb6165c42, 0x3fefccb0f4323aa3, // 0.11175, 0.99374 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fbbd3987f31fa0e, 0x3fefcf761f0c77a3, // 0.1087, 0.99407 + 0x3fbb6fa6ec38f64c, 0x3fefd0d158d86087, // 0.10717, 0.99424 + 0x3fbb0bb11e1d5559, 0x3fefd227aa9bd53b, // 0.10565, 0.9944 + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456 + 0x3fba43b90e27f3c4, 0x3fefd4c59536fae4, // 0.1026, 0.99472 + 0x3fb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // 0.10107, 0.99488 + 0x3fb97bb0caaba56f, 0x3fefd74fdd40abbf, // 0.099544, 0.99503 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb8b398cf0c38e0, 0x3fefd9c68127c78c, // 0.09649, 0.99533 + 0x3fb84f8712c130a0, 0x3fefdafa7514538c, // 0.094963, 0.99548 + 0x3fb7eb7196b72ee4, 0x3fefdc297f674ba9, // 0.093436, 0.99563 + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577 + 0x3fb7233b9d236e71, 0x3fefde78d68653fd, // 0.090381, 0.99591 + 0x3fb6bf1b3e79b129, 0x3fefdf9922f73307, // 0.088854, 0.99604 + 0x3fb65af75dd0f87b, 0x3fefe0b485181be3, // 0.087326, 0.99618 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb592a554489bc8, 0x3fefe2dc89bbff08, // 0.084269, 0.99644 + 0x3fb52e774a4d4d0a, 0x3fefe3e92be9d886, // 0.08274, 0.99657 + 0x3fb4ca45fc1ba8b6, 0x3fefe4f0e31d7a4a, // 0.081211, 0.9967 + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682 + 0x3fb401d9d0e3a507, 0x3fefe6f18ff42c84, // 0.078153, 0.99694 + 0x3fb39d9f12c5a299, 0x3fefe7ea85482d60, // 0.076624, 0.99706 + 0x3fb339614e41ffa5, 0x3fefe8de8f03d75c, // 0.075094, 0.99718 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fb270dcefdfc45b, 0x3fefeab7df1c6005, // 0.072035, 0.9974 + 0x3fb20c9674ed444c, 0x3fefeb9d2530410f, // 0.070505, 0.99751 + 0x3fb1a84d316d4f8a, 0x3fefec7d7f19cffc, // 0.068974, 0.99762 + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772 + 0x3fb0dfb28ea201e6, 0x3fefee2f6de455ba, // 0.065913, 0.99783 + 0x3fb07b614e463064, 0x3fefef0102826191, // 0.064383, 0.99793 + 0x3fb0170d833bf421, 0x3fefefcdaa704562, // 0.062852, 0.99802 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fae9cbd15ff5527, 0x3feff15833be1965, // 0.05979, 0.99821 + 0x3fadd406f9808ec8, 0x3feff21614e131ed, // 0.058258, 0.9983 + 0x3fad0b4c436f91d0, 0x3feff2cf08da7321, // 0.056727, 0.99839 + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848 + 0x3fab79c986698b78, 0x3feff43228de1b77, // 0.053664, 0.99856 + 0x3faab101bd5f8317, 0x3feff4dc54b1bed3, // 0.052132, 0.99864 + 0x3fa9e835d6993c87, 0x3feff58192ee0358, // 0.0506, 0.99872 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3fa856922bb513c1, 0x3feff6bd463b444d, // 0.047535, 0.99887 + 0x3fa78dbaa5874685, 0x3feff753bb1b9164, // 0.046003, 0.99894 + 0x3fa6c4df7d7d5b84, 0x3feff7e5420320f9, // 0.044471, 0.99901 + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908 + 0x3fa5331ec3bba0eb, 0x3feff8f9858f058b, // 0.041406, 0.99914 + 0x3fa46a396ff86179, 0x3feff97c4208c014, // 0.039873, 0.9992 + 0x3fa3a150f6421afc, 0x3feff9fa10348837, // 0.03834, 0.99926 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3fa20f770ceb11c6, 0x3feffae6e1556998, // 0.035274, 0.99938 + 0x3fa14685db42c17e, 0x3feffb55e425fdae, // 0.033741, 0.99943 + 0x3fa07d91ff984580, 0x3feffbbff85f9515, // 0.032208, 0.99948 + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953 + 0x3f9dd7458c64ab39, 0x3feffc8554cd213a, // 0.029142, 0.99958 + 0x3f9c454f4ce53b1c, 0x3feffce09ce2a679, // 0.027608, 0.99962 + 0x3f9ab354b1504fca, 0x3feffd36f624500c, // 0.026075, 0.99966 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f978f535ddc9f03, 0x3feffdd4dbf78f52, // 0.023008, 0.99974 + 0x3f95fd4d21fab226, 0x3feffe1c6870cb77, // 0.021474, 0.99977 + 0x3f946b4381fce81c, 0x3feffe5f05e578db, // 0.01994, 0.9998 + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983 + 0x3f9147270dad7132, 0x3feffed57398d2b7, // 0.016873, 0.99986 + 0x3f8f6a296ab997ca, 0x3fefff0943c53bd1, // 0.015339, 0.99988 + 0x3f8c45ffe1e48ad9, 0x3fefff3824c88f6f, // 0.013805, 0.9999 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x3f85fda037ac05e0, 0x3fefff871937ce2f, // 0.010738, 0.99994 + 0x3f82d96b0e509703, 0x3fefffa72c978c4f, // 0.0092038, 0.99996 + 0x3f7f6a65f9a2a3c5, 0x3fefffc250b5daef, // 0.0076698, 0.99997 + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, // 0.0061359, 0.99998 + 0x3f72d97822f996bc, 0x3fefffe9cb1e2e8d, // 0.0046019, 0.99999 + 0x3f6921f8becca4ba, 0x3feffff621621d02, // 0.003068, 1 + 0x3f5921faaee6472d, 0x3feffffd88586ee6, // 0.001534, 1 + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0xbf5921faaee6472d, 0x3feffffd88586ee6, // -0.001534, 1 + 0xbf6921f8becca4ba, 0x3feffff621621d02, // -0.003068, 1 + 0xbf72d97822f996bc, 0x3fefffe9cb1e2e8d, //-0.0046019, 0.99999 + 0xbf7921f0fe670071, 0x3fefffd8858e8a92, //-0.0061359, 0.99998 + 0xbf7f6a65f9a2a3c5, 0x3fefffc250b5daef, //-0.0076698, 0.99997 + 0xbf82d96b0e509703, 0x3fefffa72c978c4f, //-0.0092038, 0.99996 + 0xbf85fda037ac05e0, 0x3fefff871937ce2f, // -0.010738, 0.99994 + 0xbf8921d1fcdec784, 0x3fefff62169b92db, // -0.012272, 0.99992 + 0xbf8c45ffe1e48ad9, 0x3fefff3824c88f6f, // -0.013805, 0.9999 + 0xbf8f6a296ab997ca, 0x3fefff0943c53bd1, // -0.015339, 0.99988 + 0xbf9147270dad7132, 0x3feffed57398d2b7, // -0.016873, 0.99986 + 0xbf92d936bbe30efd, 0x3feffe9cb44b51a1, // -0.018407, 0.99983 + 0xbf946b4381fce81c, 0x3feffe5f05e578db, // -0.01994, 0.9998 + 0xbf95fd4d21fab226, 0x3feffe1c6870cb77, // -0.021474, 0.99977 + 0xbf978f535ddc9f03, 0x3feffdd4dbf78f52, // -0.023008, 0.99974 + 0xbf992155f7a3667e, 0x3feffd886084cd0d, // -0.024541, 0.9997 + 0xbf9ab354b1504fca, 0x3feffd36f624500c, // -0.026075, 0.99966 + 0xbf9c454f4ce53b1c, 0x3feffce09ce2a679, // -0.027608, 0.99962 + 0xbf9dd7458c64ab39, 0x3feffc8554cd213a, // -0.029142, 0.99958 + 0xbf9f693731d1cf01, 0x3feffc251df1d3f8, // -0.030675, 0.99953 + 0xbfa07d91ff984580, 0x3feffbbff85f9515, // -0.032208, 0.99948 + 0xbfa14685db42c17e, 0x3feffb55e425fdae, // -0.033741, 0.99943 + 0xbfa20f770ceb11c6, 0x3feffae6e1556998, // -0.035274, 0.99938 + 0xbfa2d865759455cd, 0x3feffa72effef75d, // -0.036807, 0.99932 + 0xbfa3a150f6421afc, 0x3feff9fa10348837, // -0.03834, 0.99926 + 0xbfa46a396ff86179, 0x3feff97c4208c014, // -0.039873, 0.9992 + 0xbfa5331ec3bba0eb, 0x3feff8f9858f058b, // -0.041406, 0.99914 + 0xbfa5fc00d290cd43, 0x3feff871dadb81df, // -0.042938, 0.99908 + 0xbfa6c4df7d7d5b84, 0x3feff7e5420320f9, // -0.044471, 0.99901 + 0xbfa78dbaa5874685, 0x3feff753bb1b9164, // -0.046003, 0.99894 + 0xbfa856922bb513c1, 0x3feff6bd463b444d, // -0.047535, 0.99887 + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, // -0.049068, 0.9988 + 0xbfa9e835d6993c87, 0x3feff58192ee0358, // -0.0506, 0.99872 + 0xbfaab101bd5f8317, 0x3feff4dc54b1bed3, // -0.052132, 0.99864 + 0xbfab79c986698b78, 0x3feff43228de1b77, // -0.053664, 0.99856 + 0xbfac428d12c0d7e3, 0x3feff3830f8d575c, // -0.055195, 0.99848 + 0xbfad0b4c436f91d0, 0x3feff2cf08da7321, // -0.056727, 0.99839 + 0xbfadd406f9808ec8, 0x3feff21614e131ed, // -0.058258, 0.9983 + 0xbfae9cbd15ff5527, 0x3feff15833be1965, // -0.05979, 0.99821 + 0xbfaf656e79f820e0, 0x3feff095658e71ad, // -0.061321, 0.99812 + 0xbfb0170d833bf421, 0x3fefefcdaa704562, // -0.062852, 0.99802 + 0xbfb07b614e463064, 0x3fefef0102826191, // -0.064383, 0.99793 + 0xbfb0dfb28ea201e6, 0x3fefee2f6de455ba, // -0.065913, 0.99783 + 0xbfb1440134d709b2, 0x3fefed58ecb673c4, // -0.067444, 0.99772 + 0xbfb1a84d316d4f8a, 0x3fefec7d7f19cffc, // -0.068974, 0.99762 + 0xbfb20c9674ed444c, 0x3fefeb9d2530410f, // -0.070505, 0.99751 + 0xbfb270dcefdfc45b, 0x3fefeab7df1c6005, // -0.072035, 0.9974 + 0xbfb2d52092ce19f6, 0x3fefe9cdad01883a, // -0.073565, 0.99729 + 0xbfb339614e41ffa5, 0x3fefe8de8f03d75c, // -0.075094, 0.99718 + 0xbfb39d9f12c5a299, 0x3fefe7ea85482d60, // -0.076624, 0.99706 + 0xbfb401d9d0e3a507, 0x3fefe6f18ff42c84, // -0.078153, 0.99694 + 0xbfb4661179272096, 0x3fefe5f3af2e3940, // -0.079682, 0.99682 + 0xbfb4ca45fc1ba8b6, 0x3fefe4f0e31d7a4a, // -0.081211, 0.9967 + 0xbfb52e774a4d4d0a, 0x3fefe3e92be9d886, // -0.08274, 0.99657 + 0xbfb592a554489bc8, 0x3fefe2dc89bbff08, // -0.084269, 0.99644 + 0xbfb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // -0.085797, 0.99631 + 0xbfb65af75dd0f87b, 0x3fefe0b485181be3, // -0.087326, 0.99618 + 0xbfb6bf1b3e79b129, 0x3fefdf9922f73307, // -0.088854, 0.99604 + 0xbfb7233b9d236e71, 0x3fefde78d68653fd, // -0.090381, 0.99591 + 0xbfb787586a5d5b21, 0x3fefdd539ff1f456, // -0.091909, 0.99577 + 0xbfb7eb7196b72ee4, 0x3fefdc297f674ba9, // -0.093436, 0.99563 + 0xbfb84f8712c130a0, 0x3fefdafa7514538c, // -0.094963, 0.99548 + 0xbfb8b398cf0c38e0, 0x3fefd9c68127c78c, // -0.09649, 0.99533 + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, // -0.098017, 0.99518 + 0xbfb97bb0caaba56f, 0x3fefd74fdd40abbf, // -0.099544, 0.99503 + 0xbfb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // -0.10107, 0.99488 + 0xbfba43b90e27f3c4, 0x3fefd4c59536fae4, // -0.1026, 0.99472 + 0xbfbaa7b724495c04, 0x3fefd37914220b84, // -0.10412, 0.99456 + 0xbfbb0bb11e1d5559, 0x3fefd227aa9bd53b, // -0.10565, 0.9944 + 0xbfbb6fa6ec38f64c, 0x3fefd0d158d86087, // -0.10717, 0.99424 + 0xbfbbd3987f31fa0e, 0x3fefcf761f0c77a3, // -0.1087, 0.99407 + 0xbfbc3785c79ec2d5, 0x3fefce15fd6da67b, // -0.11022, 0.99391 + 0xbfbc9b6eb6165c42, 0x3fefccb0f4323aa3, // -0.11175, 0.99374 + 0xbfbcff533b307dc1, 0x3fefcb4703914354, // -0.11327, 0.99356 + 0xbfbd633347858ce4, 0x3fefc9d82bc2915e, // -0.11479, 0.99339 + 0xbfbdc70ecbae9fc8, 0x3fefc8646cfeb721, // -0.11632, 0.99321 + 0xbfbe2ae5b8457f77, 0x3fefc6ebc77f0887, // -0.11784, 0.99303 + 0xbfbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // -0.11937, 0.99285 + 0xbfbef2858d27561b, 0x3fefc3ebc935454c, // -0.12089, 0.99267 + 0xbfbf564e56a9730e, 0x3fefc26470e19fd3, // -0.12241, 0.99248 + 0xbfbfba124b07ad85, 0x3fefc0d832bf043a, // -0.12393, 0.99229 + 0xbfc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // -0.12545, 0.9921 + 0xbfc040c5bb67747e, 0x3fefbdb106021816, // -0.12698, 0.99191 + 0xbfc072a047ba831d, 0x3fefbc1617e44186, // -0.1285, 0.99171 + 0xbfc0a4784ab8bf1d, 0x3fefba7644f068b5, // -0.13002, 0.99151 + 0xbfc0d64dbcb26786, 0x3fefb8d18d66adb7, // -0.13154, 0.99131 + 0xbfc1082095f820b0, 0x3fefb727f187f1c7, // -0.13306, 0.99111 + 0xbfc139f0cedaf576, 0x3fefb5797195d741, // -0.13458, 0.9909 + 0xbfc16bbe5fac5865, 0x3fefb3c60dd2c199, // -0.1361, 0.9907 + 0xbfc19d8940be24e7, 0x3fefb20dc681d54d, // -0.13762, 0.99049 + 0xbfc1cf516a62a077, 0x3fefb0509be6f7db, // -0.13914, 0.99027 + 0xbfc20116d4ec7bce, 0x3fefae8e8e46cfbb, // -0.14066, 0.99006 + 0xbfc232d978aed413, 0x3fefacc79de6c44f, // -0.14218, 0.98984 + 0xbfc264994dfd340a, 0x3fefaafbcb0cfddc, // -0.1437, 0.98962 + 0xbfc296564d2b953e, 0x3fefa92b1600657c, // -0.14521, 0.9894 + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918 + 0xbfc2f9c7aa7a72af, 0x3fefa57b066e2754, // -0.14825, 0.98895 + 0xbfc32b7bf94516a7, 0x3fefa39bac7a1791, // -0.14976, 0.98872 + 0xbfc35d2d53440db2, 0x3fefa1b7717661d5, // -0.15128, 0.98849 + 0xbfc38edbb0cd8d14, 0x3fef9fce55adb2c8, // -0.1528, 0.98826 + 0xbfc3c0870a383ff6, 0x3fef9de0596b77a3, // -0.15431, 0.98802 + 0xbfc3f22f57db4893, 0x3fef9bed7cfbde29, // -0.15583, 0.98778 + 0xbfc423d4920e4166, 0x3fef99f5c0abd496, // -0.15734, 0.98754 + 0xbfc45576b1293e5a, 0x3fef97f924c9099b, // -0.15886, 0.9873 + 0xbfc48715ad84cdf5, 0x3fef95f7a9a1ec47, // -0.16037, 0.98706 + 0xbfc4b8b17f79fa88, 0x3fef93f14f85ac08, // -0.16189, 0.98681 + 0xbfc4ea4a1f624b61, 0x3fef91e616c43891, // -0.1634, 0.98656 + 0xbfc51bdf8597c5f2, 0x3fef8fd5ffae41db, // -0.16491, 0.98631 + 0xbfc54d71aa74ef02, 0x3fef8dc10a95380d, // -0.16643, 0.98605 + 0xbfc57f008654cbde, 0x3fef8ba737cb4b78, // -0.16794, 0.9858 + 0xbfc5b08c1192e381, 0x3fef898887a36c84, // -0.16945, 0.98554 + 0xbfc5e214448b3fc6, 0x3fef8764fa714ba9, // -0.17096, 0.98528 + 0xbfc61399179a6e94, 0x3fef853c9089595e, // -0.17247, 0.98501 + 0xbfc6451a831d830d, 0x3fef830f4a40c60c, // -0.17398, 0.98475 + 0xbfc676987f7216b8, 0x3fef80dd27ed8204, // -0.17549, 0.98448 + 0xbfc6a81304f64ab2, 0x3fef7ea629e63d6e, // -0.177, 0.98421 + 0xbfc6d98a0c08c8da, 0x3fef7c6a50826840, // -0.17851, 0.98394 + 0xbfc70afd8d08c4ff, 0x3fef7a299c1a322a, // -0.18002, 0.98366 + 0xbfc73c6d8055fe0a, 0x3fef77e40d068a90, // -0.18153, 0.98339 + 0xbfc76dd9de50bf31, 0x3fef7599a3a12077, // -0.18304, 0.98311 + 0xbfc79f429f59e11d, 0x3fef734a60446279, // -0.18455, 0.98282 + 0xbfc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // -0.18606, 0.98254 + 0xbfc802092c1d744b, 0x3fef6e9d4d1262ca, // -0.18756, 0.98225 + 0xbfc83366e89c64c5, 0x3fef6c3f7df5bbb7, // -0.18907, 0.98196 + 0xbfc864c0e9b2b6cf, 0x3fef69dcd652f5de, // -0.19057, 0.98167 + 0xbfc8961727c41804, 0x3fef677556883cee, // -0.19208, 0.98138 + 0xbfc8c7699b34ca7e, 0x3fef6508fef47bd5, // -0.19359, 0.98108 + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079 + 0xbfc92a0303c8194f, 0x3fef6021c9f148c2, // -0.19659, 0.98048 + 0xbfc95b49e9b62af9, 0x3fef5da6ed43685d, // -0.1981, 0.98018 + 0xbfc98c8ce69a7aec, 0x3fef5b273a4fa2d9, // -0.1996, 0.97988 + 0xbfc9bdcbf2dc4366, 0x3fef58a2b1789e84, // -0.2011, 0.97957 + 0xbfc9ef0706e35a35, 0x3fef56195321c090, // -0.20261, 0.97926 + 0xbfca203e1b1831da, 0x3fef538b1faf2d07, // -0.20411, 0.97895 + 0xbfca517127e3dabc, 0x3fef50f81785c6b9, // -0.20561, 0.97863 + 0xbfca82a025b00451, 0x3fef4e603b0b2f2d, // -0.20711, 0.97832 + 0xbfcab3cb0ce6fe44, 0x3fef4bc38aa5c694, // -0.20861, 0.978 + 0xbfcae4f1d5f3b9ab, 0x3fef492206bcabb4, // -0.21011, 0.97768 + 0xbfcb16147941ca2a, 0x3fef467bafb7bbe0, // -0.21161, 0.97735 + 0xbfcb4732ef3d6722, 0x3fef43d085ff92dd, // -0.21311, 0.97703 + 0xbfcb784d30536cda, 0x3fef412089fd8adc, // -0.21461, 0.9767 + 0xbfcba96334f15dad, 0x3fef3e6bbc1bbc65, // -0.21611, 0.97637 + 0xbfcbda74f5856330, 0x3fef3bb21cc4fe47, // -0.2176, 0.97604 + 0xbfcc0b826a7e4f63, 0x3fef38f3ac64e589, // -0.2191, 0.9757 + 0xbfcc3c8b8c4b9dd7, 0x3fef36306b67c556, // -0.2206, 0.97536 + 0xbfcc6d90535d74dc, 0x3fef33685a3aaef0, // -0.22209, 0.97503 + 0xbfcc9e90b824a6a9, 0x3fef309b794b719f, // -0.22359, 0.97468 + 0xbfcccf8cb312b286, 0x3fef2dc9c9089a9d, // -0.22508, 0.97434 + 0xbfcd00843c99c5f9, 0x3fef2af349e17507, // -0.22658, 0.97399 + 0xbfcd31774d2cbdee, 0x3fef2817fc4609ce, // -0.22807, 0.97364 + 0xbfcd6265dd3f27e3, 0x3fef2537e0a71f9f, // -0.22957, 0.97329 + 0xbfcd934fe5454311, 0x3fef2252f7763ada, // -0.23106, 0.97294 + 0xbfcdc4355db40195, 0x3fef1f6941259d7a, // -0.23255, 0.97258 + 0xbfcdf5163f01099a, 0x3fef1c7abe284708, // -0.23404, 0.97223 + 0xbfce25f281a2b684, 0x3fef19876ef1f486, // -0.23553, 0.97187 + 0xbfce56ca1e101a1b, 0x3fef168f53f7205d, // -0.23702, 0.9715 + 0xbfce879d0cc0fdaf, 0x3fef13926dad024e, // -0.23851, 0.97114 + 0xbfceb86b462de348, 0x3fef1090bc898f5f, // -0.24, 0.97077 + 0xbfcee934c2d006c7, 0x3fef0d8a410379c5, // -0.24149, 0.9704 + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003 + 0xbfcf4ab9679c9f5c, 0x3fef076eecade0fa, // -0.24447, 0.96966 + 0xbfcf7b7480bd3801, 0x3fef045a14cf738c, // -0.24596, 0.96928 + 0xbfcfac2abeff57ff, 0x3fef014074708ed3, // -0.24744, 0.9689 + 0xbfcfdcdc1adfedf8, 0x3feefe220c0b95ec, // -0.24893, 0.96852 + 0xbfd006c4466e54af, 0x3feefafedc1ba8b7, // -0.25041, 0.96814 + 0xbfd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // -0.2519, 0.96775 + 0xbfd037694a928cac, 0x3feef4aa278b2032, // -0.25338, 0.96737 + 0xbfd04fb80e37fdae, 0x3feef178a3e473c2, // -0.25487, 0.96698 + 0xbfd068044deab002, 0x3feeee425aa6b09a, // -0.25635, 0.96658 + 0xbfd0804e05eb661e, 0x3feeeb074c50a544, // -0.25783, 0.96619 + 0xbfd09895327b465e, 0x3feee7c77961dc9e, // -0.25931, 0.96579 + 0xbfd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // -0.26079, 0.96539 + 0xbfd0c91bda4f158d, 0x3feee13987bbebdc, // -0.26227, 0.96499 + 0xbfd0e15b4e1749cd, 0x3feeddeb6a078651, // -0.26375, 0.96459 + 0xbfd0f998277733f7, 0x3feeda9889bfe86a, // -0.26523, 0.96418 + 0xbfd111d262b1f677, 0x3feed740e7684963, // -0.26671, 0.96378 + 0xbfd12a09fc0b1b12, 0x3feed3e483849c51, // -0.26819, 0.96337 + 0xbfd1423eefc69378, 0x3feed0835e999009, // -0.26967, 0.96295 + 0xbfd15a713a28b9d9, 0x3feecd1d792c8f10, // -0.27115, 0.96254 + 0xbfd172a0d7765177, 0x3feec9b2d3c3bf84, // -0.27262, 0.96212 + 0xbfd18acdc3f4873a, 0x3feec6436ee60309, // -0.2741, 0.9617 + 0xbfd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // -0.27557, 0.96128 + 0xbfd1bb1f7b999480, 0x3feebf5668eaf2ef, // -0.27705, 0.96086 + 0xbfd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // -0.27852, 0.96043 + 0xbfd1eb6643499fbb, 0x3feeb8566b810f2a, // -0.27999, 0.96 + 0xbfd2038583d727bd, 0x3feeb4cf515b8811, // -0.28146, 0.95957 + 0xbfd21ba1fd3d2623, 0x3feeb1437af9bb34, // -0.28294, 0.95914 + 0xbfd233bbabc3bb72, 0x3feeadb2e8e7a88e, // -0.28441, 0.9587 + 0xbfd24bd28bb37672, 0x3feeaa1d9bb20af3, // -0.28588, 0.95827 + 0xbfd263e6995554ba, 0x3feea68393e65800, // -0.28735, 0.95783 + 0xbfd27bf7d0f2c346, 0x3feea2e4d212c000, // -0.28882, 0.95738 + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694 + 0xbfd2ac11af483572, 0x3fee9b99229046f8, // -0.29175, 0.95649 + 0xbfd2c41a4e954520, 0x3fee97ec36016b30, // -0.29322, 0.95605 + 0xbfd2dc200907fe51, 0x3fee943a91aab4b4, // -0.29469, 0.95559 + 0xbfd2f422daec0386, 0x3fee9084361df7f3, // -0.29615, 0.95514 + 0xbfd30c22c08d6a13, 0x3fee8cc923edc388, // -0.29762, 0.95469 + 0xbfd3241fb638baaf, 0x3fee89095bad6025, // -0.29908, 0.95423 + 0xbfd33c19b83af207, 0x3fee8544ddf0d075, // -0.30054, 0.95377 + 0xbfd35410c2e18152, 0x3fee817bab4cd10d, // -0.30201, 0.95331 + 0xbfd36c04d27a4edf, 0x3fee7dadc456d850, // -0.30347, 0.95284 + 0xbfd383f5e353b6aa, 0x3fee79db29a5165a, // -0.30493, 0.95238 + 0xbfd39be3f1bc8aef, 0x3fee7603dbce74e9, // -0.30639, 0.95191 + 0xbfd3b3cefa0414b7, 0x3fee7227db6a9744, // -0.30785, 0.95144 + 0xbfd3cbb6f87a146e, 0x3fee6e472911da27, // -0.30931, 0.95096 + 0xbfd3e39be96ec271, 0x3fee6a61c55d53a7, // -0.31077, 0.95049 + 0xbfd3fb7dc932cfa4, 0x3fee6677b0e6d31e, // -0.31222, 0.95001 + 0xbfd4135c94176602, 0x3fee6288ec48e112, // -0.31368, 0.94953 + 0xbfd42b38466e2928, 0x3fee5e95781ebf1c, // -0.31514, 0.94905 + 0xbfd44310dc8936f0, 0x3fee5a9d550467d3, // -0.31659, 0.94856 + 0xbfd45ae652bb2800, 0x3fee56a083968eb1, // -0.31805, 0.94807 + 0xbfd472b8a5571054, 0x3fee529f04729ffc, // -0.3195, 0.94759 + 0xbfd48a87d0b07fd7, 0x3fee4e98d836c0af, // -0.32096, 0.94709 + 0xbfd4a253d11b82f3, 0x3fee4a8dff81ce5e, // -0.32241, 0.9466 + 0xbfd4ba1ca2eca31c, 0x3fee467e7af35f23, // -0.32386, 0.94611 + 0xbfd4d1e24278e76a, 0x3fee426a4b2bc17e, // -0.32531, 0.94561 + 0xbfd4e9a4ac15d520, 0x3fee3e5170cbfc46, // -0.32676, 0.94511 + 0xbfd50163dc197047, 0x3fee3a33ec75ce85, // -0.32821, 0.9446 + 0xbfd5191fceda3c35, 0x3fee3611becbaf69, // -0.32966, 0.9441 + 0xbfd530d880af3c24, 0x3fee31eae870ce25, // -0.33111, 0.94359 + 0xbfd5488dedeff3be, 0x3fee2dbf6a0911d9, // -0.33255, 0.94308 + 0xbfd5604012f467b4, 0x3fee298f4439197a, // -0.334, 0.94257 + 0xbfd577eeec151e47, 0x3fee255a77a63bb8, // -0.33545, 0.94206 + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154 + 0xbfd5a742ac0ff78d, 0x3fee1ce2ecd0c0d8, // -0.33833, 0.94103 + 0xbfd5bee78b9db3b6, 0x3fee18a02fdc66d9, // -0.33978, 0.94051 + 0xbfd5d68910aee686, 0x3fee1458cec1ad83, // -0.34122, 0.93998 + 0xbfd5ee27379ea693, 0x3fee100cca2980ac, // -0.34266, 0.93946 + 0xbfd605c1fcc88f63, 0x3fee0bbc22bd8349, // -0.3441, 0.93893 + 0xbfd61d595c88c203, 0x3fee0766d9280f54, // -0.34554, 0.9384 + 0xbfd634ed533be58e, 0x3fee030cee1435b8, // -0.34698, 0.93787 + 0xbfd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // -0.34842, 0.93734 + 0xbfd6640af6f03d9e, 0x3fedfa4b3621271d, // -0.34986, 0.9368 + 0xbfd67b949cad63ca, 0x3fedf5e36a9ba59c, // -0.35129, 0.93627 + 0xbfd6931acad55f51, 0x3fedf177004b2534, // -0.35273, 0.93573 + 0xbfd6aa9d7dc77e16, 0x3feded05f7de47da, // -0.35416, 0.93518 + 0xbfd6c21cb1e39771, 0x3fede890520465ce, // -0.3556, 0.93464 + 0xbfd6d998638a0cb5, 0x3fede4160f6d8d81, // -0.35703, 0.93409 + 0xbfd6f1108f1bc9c5, 0x3feddf9730ca837b, // -0.35846, 0.93354 + 0xbfd7088530fa459e, 0x3feddb13b6ccc23d, // -0.3599, 0.93299 + 0xbfd71ff6458782ec, 0x3fedd68ba2267a25, // -0.36133, 0.93244 + 0xbfd73763c9261092, 0x3fedd1fef38a915a, // -0.36276, 0.93188 + 0xbfd74ecdb8390a3e, 0x3fedcd6dabaca3a5, // -0.36418, 0.93133 + 0xbfd766340f2418f6, 0x3fedc8d7cb410260, // -0.36561, 0.93077 + 0xbfd77d96ca4b73a6, 0x3fedc43d52fcb453, // -0.36704, 0.93021 + 0xbfd794f5e613dfae, 0x3fedbf9e4395759a, // -0.36847, 0.92964 + 0xbfd7ac515ee2b172, 0x3fedbafa9dc1b78d, // -0.36989, 0.92907 + 0xbfd7c3a9311dcce7, 0x3fedb6526238a09b, // -0.37132, 0.92851 + 0xbfd7dafd592ba621, 0x3fedb1a591b20c38, // -0.37274, 0.92794 + 0xbfd7f24dd37341e3, 0x3fedacf42ce68ab9, // -0.37416, 0.92736 + 0xbfd8099a9c5c362d, 0x3feda83e348f613b, // -0.37559, 0.92679 + 0xbfd820e3b04eaac4, 0x3feda383a9668988, // -0.37701, 0.92621 + 0xbfd838290bb359c8, 0x3fed9ec48c26b1f3, // -0.37843, 0.92563 + 0xbfd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // -0.37985, 0.92505 + 0xbfd866a88a792ea0, 0x3fed95389e50429b, // -0.38127, 0.92447 + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388 + 0xbfd89518fbff098e, 0x3fed8b9a70ef9cb4, // -0.3841, 0.92329 + 0xbfd8ac4b86d5ed44, 0x3fed86c48445a450, // -0.38552, 0.9227 + 0xbfd8c37a439f884f, 0x3fed81ea09f38b63, // -0.38693, 0.92211 + 0xbfd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // -0.38835, 0.92151 + 0xbfd8f1cc44bea329, 0x3fed78276f5617c6, // -0.38976, 0.92092 + 0xbfd908ef81ef7bd1, 0x3fed733f508c0dff, // -0.39117, 0.92032 + 0xbfd9200ee2c9be97, 0x3fed6e52a71c8547, // -0.39258, 0.91972 + 0xbfd9372a63bc93d7, 0x3fed696173c9e68b, // -0.39399, 0.91911 + 0xbfd94e420137bce3, 0x3fed646bb7574de5, // -0.3954, 0.91851 + 0xbfd96555b7ab948f, 0x3fed5f7172888a7f, // -0.39681, 0.9179 + 0xbfd97c6583890fc2, 0x3fed5a72a6221e73, // -0.39822, 0.91729 + 0xbfd993716141bdfe, 0x3fed556f52e93eb1, // -0.39962, 0.91668 + 0xbfd9aa794d47c9ee, 0x3fed506779a3d2d9, // -0.40103, 0.91606 + 0xbfd9c17d440df9f2, 0x3fed4b5b1b187524, // -0.40243, 0.91545 + 0xbfd9d87d4207b0ab, 0x3fed464a380e7242, // -0.40384, 0.91483 + 0xbfd9ef7943a8ed8a, 0x3fed4134d14dc93a, // -0.40524, 0.91421 + 0xbfda067145664d57, 0x3fed3c1ae79f2b4e, // -0.40664, 0.91359 + 0xbfda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // -0.40804, 0.91296 + 0xbfda34553b0afee5, 0x3fed31d98e9e503a, // -0.40944, 0.91234 + 0xbfda4b4127dea1e4, 0x3fed2cb220e0ef9f, // -0.41084, 0.91171 + 0xbfda622906a70b63, 0x3fed2786335f52fc, // -0.41224, 0.91107 + 0xbfda790cd3dbf31a, 0x3fed2255c6e5a4e1, // -0.41364, 0.91044 + 0xbfda8fec8bf5b166, 0x3fed1d20dc40c15c, // -0.41503, 0.90981 + 0xbfdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // -0.41643, 0.90917 + 0xbfdabd9faebc3980, 0x3fed12a98fac410c, // -0.41782, 0.90853 + 0xbfdad473125cdc08, 0x3fed0d672f59d2b9, // -0.41922, 0.90789 + 0xbfdaeb4252ca07ab, 0x3fed082054168bac, // -0.42061, 0.90724 + 0xbfdb020d6c7f4009, 0x3fed02d4feb2bd92, // -0.422, 0.9066 + 0xbfdb18d45bf8aca6, 0x3fecfd852fff6ad4, // -0.42339, 0.90595 + 0xbfdb2f971db31972, 0x3fecf830e8ce467b, // -0.42478, 0.9053 + 0xbfdb4655ae2bf757, 0x3fecf2d829f1b40e, // -0.42617, 0.90464 + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399 + 0xbfdb73c62d520624, 0x3fece819488344ce, // -0.42894, 0.90333 + 0xbfdb8a7814fd5693, 0x3fece2b32799a060, // -0.43033, 0.90267 + 0xbfdba125bd63583e, 0x3fecdd489254fe65, // -0.43171, 0.90201 + 0xbfdbb7cf2304bd01, 0x3fecd7d9898b32f6, // -0.43309, 0.90135 + 0xbfdbce744262deee, 0x3fecd2660e12c1e6, // -0.43448, 0.90068 + 0xbfdbe51517ffc0d9, 0x3fecccee20c2de9f, // -0.43586, 0.90002 + 0xbfdbfbb1a05e0edc, 0x3fecc771c2736c09, // -0.43724, 0.89935 + 0xbfdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // -0.43862, 0.89867 + 0xbfdc28ddbb6cf145, 0x3fecbc6bb638d10b, // -0.43999, 0.898 + 0xbfdc3f6d47263129, 0x3fecb6e20a00da99, // -0.44137, 0.89732 + 0xbfdc55f877b23537, 0x3fecb153f02fb87d, // -0.44275, 0.89665 + 0xbfdc6c7f4997000a, 0x3fecabc169a0b901, // -0.44412, 0.89597 + 0xbfdc8301b95b40c2, 0x3feca62a772fd919, // -0.4455, 0.89528 + 0xbfdc997fc3865388, 0x3feca08f19b9c449, // -0.44687, 0.8946 + 0xbfdcaff964a0421d, 0x3fec9aef521bd480, // -0.44824, 0.89391 + 0xbfdcc66e9931c45d, 0x3fec954b213411f5, // -0.44961, 0.89322 + 0xbfdcdcdf5dc440ce, 0x3fec8fa287e13305, // -0.45098, 0.89253 + 0xbfdcf34baee1cd21, 0x3fec89f587029c13, // -0.45235, 0.89184 + 0xbfdd09b389152ec1, 0x3fec84441f785f61, // -0.45372, 0.89115 + 0xbfdd2016e8e9db5b, 0x3fec7e8e52233cf3, // -0.45508, 0.89045 + 0xbfdd3675caebf962, 0x3fec78d41fe4a267, // -0.45645, 0.88975 + 0xbfdd4cd02ba8609c, 0x3fec7315899eaad7, // -0.45781, 0.88905 + 0xbfdd632607ac9aa9, 0x3fec6d5290341eb2, // -0.45918, 0.88835 + 0xbfdd79775b86e389, 0x3fec678b3488739b, // -0.46054, 0.88764 + 0xbfdd8fc423c62a25, 0x3fec61bf777fcc48, // -0.4619, 0.88693 + 0xbfdda60c5cfa10d8, 0x3fec5bef59fef85a, // -0.46326, 0.88622 + 0xbfddbc5003b2edf8, 0x3fec561adceb743e, // -0.46462, 0.88551 + 0xbfddd28f1481cc58, 0x3fec5042012b6907, // -0.46598, 0.8848 + 0xbfdde8c98bf86bd6, 0x3fec4a64c7a5ac4c, // -0.46733, 0.88408 + 0xbfddfeff66a941de, 0x3fec44833141c004, // -0.46869, 0.88336 + 0xbfde1530a12779f4, 0x3fec3e9d3ee7d262, // -0.47004, 0.88264 + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192 + 0xbfde418527dc4ffa, 0x3fec32c449f60831, // -0.47275, 0.8812 + 0xbfde57a86d3cd824, 0x3fec2cd14931e3f1, // -0.4741, 0.88047 + 0xbfde6dc704be97e2, 0x3fec26d9f01f2eaf, // -0.47545, 0.87974 + 0xbfde83e0eaf85113, 0x3fec20de3fa971b0, // -0.4768, 0.87901 + 0xbfde99f61c817eda, 0x3fec1ade38bce19b, // -0.47815, 0.87828 + 0xbfdeb00695f25620, 0x3fec14d9dc465e58, // -0.47949, 0.87755 + 0xbfdec61253e3c61b, 0x3fec0ed12b3372e9, // -0.48084, 0.87681 + 0xbfdedc1952ef78d5, 0x3fec08c426725549, // -0.48218, 0.87607 + 0xbfdef21b8fafd3b5, 0x3fec02b2cef1e641, // -0.48353, 0.87533 + 0xbfdf081906bff7fd, 0x3febfc9d25a1b147, // -0.48487, 0.87459 + 0xbfdf1e11b4bbc35c, 0x3febf6832b71ec5b, // -0.48621, 0.87384 + 0xbfdf3405963fd068, 0x3febf064e15377dd, // -0.48755, 0.87309 + 0xbfdf49f4a7e97729, 0x3febea424837de6d, // -0.48889, 0.87235 + 0xbfdf5fdee656cda3, 0x3febe41b611154c1, // -0.49023, 0.8716 + 0xbfdf75c44e26a852, 0x3febddf02cd2b983, // -0.49156, 0.87084 + 0xbfdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // -0.4929, 0.87009 + 0xbfdfa1808c6cf7e0, 0x3febd18ce0dc19d6, // -0.49423, 0.86933 + 0xbfdfb7575c24d2de, 0x3febcb54cb0d2327, // -0.49557, 0.86857 + 0xbfdfcd2947c1ff57, 0x3febc5186bf8361d, // -0.4969, 0.86781 + 0xbfdfe2f64be7120f, 0x3febbed7c49380ea, // -0.49823, 0.86705 + 0xbfdff8be6537615e, 0x3febb892d5d5dad5, // -0.49956, 0.86628 + 0xbfe00740c82b82e0, 0x3febb249a0b6c40d, // -0.50089, 0.86551 + 0xbfe0121fe4f56d2c, 0x3febabfc262e6586, // -0.50221, 0.86474 + 0xbfe01cfc874c3eb7, 0x3feba5aa673590d2, // -0.50354, 0.86397 + 0xbfe027d6ad83287e, 0x3feb9f5464c5bffc, // -0.50486, 0.8632 + 0xbfe032ae55edbd95, 0x3feb98fa1fd9155e, // -0.50619, 0.86242 + 0xbfe03d837edff370, 0x3feb929b996a5b7f, // -0.50751, 0.86165 + 0xbfe0485626ae221a, 0x3feb8c38d27504e9, // -0.50883, 0.86087 + 0xbfe053264bad0483, 0x3feb85d1cbf52c02, // -0.51015, 0.86009 + 0xbfe05df3ec31b8b6, 0x3feb7f6686e792ea, // -0.51147, 0.8593 + 0xbfe068bf0691c028, 0x3feb78f70449a34b, // -0.51279, 0.85852 + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773 + 0xbfe07e4da23bc102, 0x3feb6c0b4a55ac17, // -0.51542, 0.85694 + 0xbfe089112032b08c, 0x3feb658f14fdbc47, // -0.51673, 0.85615 + 0xbfe093d2115ee018, 0x3feb5f0ea611a532, // -0.51804, 0.85535 + 0xbfe09e907417c5e1, 0x3feb5889fe921405, // -0.51936, 0.85456 + 0xbfe0a94c46b53d0b, 0x3feb52011f805c92, // -0.52067, 0.85376 + 0xbfe0b405878f85ec, 0x3feb4b7409de7925, // -0.52198, 0.85296 + 0xbfe0bebc34ff4646, 0x3feb44e2beaf0a61, // -0.52328, 0.85216 + 0xbfe0c9704d5d898f, 0x3feb3e4d3ef55712, // -0.52459, 0.85136 + 0xbfe0d421cf03c12b, 0x3feb37b38bb54c09, // -0.5259, 0.85055 + 0xbfe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // -0.5272, 0.84974 + 0xbfe0e97d078fd23b, 0x3feb2a738eb51f33, // -0.5285, 0.84893 + 0xbfe0f426bb2a8e7d, 0x3feb23cd470013b4, // -0.5298, 0.84812 + 0xbfe0fecdd1770537, 0x3feb1d22cfdadcc6, // -0.5311, 0.84731 + 0xbfe1097248d0a956, 0x3feb16742a4ca2f5, // -0.5324, 0.84649 + 0xbfe114141f935545, 0x3feb0fc1575d33db, // -0.5337, 0.84567 + 0xbfe11eb3541b4b22, 0x3feb090a58150200, // -0.535, 0.84485 + 0xbfe1294fe4c5350a, 0x3feb024f2d7d24a9, // -0.53629, 0.84403 + 0xbfe133e9cfee254e, 0x3feafb8fd89f57b6, // -0.53759, 0.84321 + 0xbfe13e8113f396c1, 0x3feaf4cc5a85fb73, // -0.53888, 0.84238 + 0xbfe14915af336ceb, 0x3feaee04b43c1474, // -0.54017, 0.84155 + 0xbfe153a7a00bf453, 0x3feae738e6cd4b67, // -0.54146, 0.84073 + 0xbfe15e36e4dbe2bc, 0x3feae068f345ecef, // -0.54275, 0.83989 + 0xbfe168c37c025764, 0x3fead994dab2e979, // -0.54404, 0.83906 + 0xbfe1734d63dedb49, 0x3fead2bc9e21d511, // -0.54532, 0.83822 + 0xbfe17dd49ad16161, 0x3feacbe03ea0e73b, // -0.54661, 0.83739 + 0xbfe188591f3a46e5, 0x3feac4ffbd3efac8, // -0.54789, 0.83655 + 0xbfe192daef7a5386, 0x3feabe1b1b0b8dac, // -0.54918, 0.83571 + 0xbfe19d5a09f2b9b8, 0x3feab7325916c0d4, // -0.55046, 0.83486 + 0xbfe1a7d66d0516e6, 0x3feab045787157ff, // -0.55174, 0.83402 + 0xbfe1b250171373be, 0x3feaa9547a2cb98e, // -0.55302, 0.83317 + 0xbfe1bcc706804467, 0x3feaa25f5f5aee60, // -0.55429, 0.83232 + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147 + 0xbfe1d1acaf012cc2, 0x3fea9468d85b20ae, // -0.55685, 0.83062 + 0xbfe1dc1b64dc4872, 0x3fea8d676e545ad2, // -0.55812, 0.82976 + 0xbfe1e68759a3e074, 0x3fea8661ec0ee133, // -0.55939, 0.8289 + 0xbfe1f0f08bbc861b, 0x3fea7f58529fe69d, // -0.56066, 0.82805 + 0xbfe1fb56f98b37b8, 0x3fea784aa31d3f55, // -0.56193, 0.82718 + 0xbfe205baa17560d6, 0x3fea7138de9d60f5, // -0.5632, 0.82632 + 0xbfe2101b81e0da78, 0x3fea6a230637623b, // -0.56447, 0.82546 + 0xbfe21a799933eb58, 0x3fea63091b02fae2, // -0.56573, 0.82459 + 0xbfe224d4e5d5482e, 0x3fea5beb1e188375, // -0.567, 0.82372 + 0xbfe22f2d662c13e1, 0x3fea54c91090f524, // -0.56826, 0.82285 + 0xbfe23983189fdfd5, 0x3fea4da2f385e997, // -0.56952, 0.82198 + 0xbfe243d5fb98ac1f, 0x3fea4678c8119ac8, // -0.57078, 0.8211 + 0xbfe24e260d7ee7c9, 0x3fea3f4a8f4ee2d2, // -0.57204, 0.82023 + 0xbfe258734cbb7110, 0x3fea38184a593bc6, // -0.5733, 0.81935 + 0xbfe262bdb7b795a2, 0x3fea30e1fa4cbf81, // -0.57455, 0.81847 + 0xbfe26d054cdd12df, 0x3fea29a7a0462782, // -0.57581, 0.81758 + 0xbfe2774a0a961612, 0x3fea22693d62ccb9, // -0.57706, 0.8167 + 0xbfe2818bef4d3cba, 0x3fea1b26d2c0a75e, // -0.57831, 0.81581 + 0xbfe28bcaf96d94ba, 0x3fea13e0617e4ec7, // -0.57956, 0.81493 + 0xbfe2960727629ca8, 0x3fea0c95eabaf937, // -0.58081, 0.81404 + 0xbfe2a040779843fb, 0x3fea05476f967bb5, // -0.58206, 0.81314 + 0xbfe2aa76e87aeb58, 0x3fe9fdf4f13149de, // -0.58331, 0.81225 + 0xbfe2b4aa787764c4, 0x3fe9f69e70ac75bc, // -0.58455, 0.81135 + 0xbfe2bedb25faf3ea, 0x3fe9ef43ef29af94, // -0.5858, 0.81046 + 0xbfe2c908ef734e57, 0x3fe9e7e56dcb45bd, // -0.58704, 0.80956 + 0xbfe2d333d34e9bb7, 0x3fe9e082edb42472, // -0.58828, 0.80866 + 0xbfe2dd5bcffb7616, 0x3fe9d91c7007d5a6, // -0.58952, 0.80775 + 0xbfe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // -0.59076, 0.80685 + 0xbfe2f1a30d86773a, 0x3fe9ca438080eadb, // -0.592, 0.80594 + 0xbfe2fbc24b441015, 0x3fe9c2d110f075c3, // -0.59323, 0.80503 + 0xbfe305de9b921a94, 0x3fe9bb5aa85f2098, // -0.59447, 0.80412 + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321 + 0xbfe31a0e6da35e44, 0x3fe9ac61f0d4e247, // -0.59693, 0.80229 + 0xbfe32421ec49a620, 0x3fe9a4dfa42b06b2, // -0.59816, 0.80138 + 0xbfe32e3277467d6b, 0x3fe99d59631e65d5, // -0.59939, 0.80046 + 0xbfe338400d0c8e57, 0x3fe995cf2ed80d22, // -0.60062, 0.79954 + 0xbfe3424aac0ef7d6, 0x3fe98e410881a600, // -0.60184, 0.79861 + 0xbfe34c5252c14de1, 0x3fe986aef1457594, // -0.60307, 0.79769 + 0xbfe35656ff9799ae, 0x3fe97f18ea4e5c9e, // -0.60429, 0.79676 + 0xbfe36058b10659f3, 0x3fe9777ef4c7d742, // -0.60551, 0.79584 + 0xbfe36a576582831b, 0x3fe96fe111ddfce0, // -0.60673, 0.79491 + 0xbfe374531b817f8d, 0x3fe9683f42bd7fe1, // -0.60795, 0.79398 + 0xbfe37e4bd1792fe2, 0x3fe960998893ad8c, // -0.60917, 0.79304 + 0xbfe3884185dfeb22, 0x3fe958efe48e6dd7, // -0.61038, 0.79211 + 0xbfe39234372c7f04, 0x3fe9514257dc4335, // -0.6116, 0.79117 + 0xbfe39c23e3d63029, 0x3fe94990e3ac4a6c, // -0.61281, 0.79023 + 0xbfe3a6108a54ba58, 0x3fe941db892e3a65, // -0.61402, 0.78929 + 0xbfe3affa292050b9, 0x3fe93a22499263fc, // -0.61523, 0.78835 + 0xbfe3b9e0beb19e18, 0x3fe932652609b1cf, // -0.61644, 0.7874 + 0xbfe3c3c44981c517, 0x3fe92aa41fc5a815, // -0.61765, 0.78646 + 0xbfe3cda4c80a6076, 0x3fe922df37f8646a, // -0.61885, 0.78551 + 0xbfe3d78238c58343, 0x3fe91b166fd49da2, // -0.62006, 0.78456 + 0xbfe3e15c9a2db922, 0x3fe91349c88da398, // -0.62126, 0.7836 + 0xbfe3eb33eabe0680, 0x3fe90b7943575efe, // -0.62246, 0.78265 + 0xbfe3f50828f1e8d2, 0x3fe903a4e1665133, // -0.62366, 0.78169 + 0xbfe3fed9534556d4, 0x3fe8fbcca3ef940d, // -0.62486, 0.78074 + 0xbfe408a76834c0c0, 0x3fe8f3f08c28d9ac, // -0.62606, 0.77978 + 0xbfe41272663d108c, 0x3fe8ec109b486c49, // -0.62725, 0.77882 + 0xbfe41c3a4bdbaa26, 0x3fe8e42cd2852e0a, // -0.62845, 0.77785 + 0xbfe425ff178e6bb1, 0x3fe8dc45331698cc, // -0.62964, 0.77689 + 0xbfe42fc0c7d3adbb, 0x3fe8d459be34bdfa, // -0.63083, 0.77592 + 0xbfe4397f5b2a4380, 0x3fe8cc6a75184655, // -0.63202, 0.77495 + 0xbfe4433ad0117b1d, 0x3fe8c47758fa71cb, // -0.63321, 0.77398 + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301 + 0xbfe456a858917046, 0x3fe8b485aca2a468, // -0.63558, 0.77204 + 0xbfe4605a692b32a2, 0x3fe8ac871ede1d88, // -0.63676, 0.77106 + 0xbfe46a095557a0f1, 0x3fe8a484c3031d50, // -0.63794, 0.77008 + 0xbfe473b51b987347, 0x3fe89c7e9a4dd4ab, // -0.63912, 0.7691 + 0xbfe47d5dba6fde01, 0x3fe89474a5fb0a84, // -0.6403, 0.76812 + 0xbfe48703306091fe, 0x3fe88c66e7481ba1, // -0.64148, 0.76714 + 0xbfe490a57bedbcdf, 0x3fe884555f72fa6b, // -0.64266, 0.76615 + 0xbfe49a449b9b0938, 0x3fe87c400fba2ebf, // -0.64383, 0.76517 + 0xbfe4a3e08dec9ed6, 0x3fe87426f95cd5bd, // -0.645, 0.76418 + 0xbfe4ad79516722f0, 0x3fe86c0a1d9aa195, // -0.64618, 0.76319 + 0xbfe4b70ee48fb869, 0x3fe863e97db3d95a, // -0.64735, 0.7622 + 0xbfe4c0a145ec0004, 0x3fe85bc51ae958cc, // -0.64851, 0.7612 + 0xbfe4ca30740218a3, 0x3fe8539cf67c9029, // -0.64968, 0.76021 + 0xbfe4d3bc6d589f80, 0x3fe84b7111af83f9, // -0.65085, 0.75921 + 0xbfe4dd453076b064, 0x3fe843416dc4cce2, // -0.65201, 0.75821 + 0xbfe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // -0.65317, 0.75721 + 0xbfe4f04d0e2859aa, 0x3fe832d6eda3a3e0, // -0.65433, 0.75621 + 0xbfe4f9cc25cca486, 0x3fe82a9c13f545ff, // -0.65549, 0.7552 + 0xbfe503480159ded2, 0x3fe8225d803964e5, // -0.65665, 0.75419 + 0xbfe50cc09f59a09b, 0x3fe81a1b33b57acc, // -0.65781, 0.75319 + 0xbfe51635fe5601d7, 0x3fe811d52faf94dc, // -0.65896, 0.75218 + 0xbfe51fa81cd99aa6, 0x3fe8098b756e52fa, // -0.66011, 0.75117 + 0xbfe52916f96f8388, 0x3fe8013e0638e795, // -0.66127, 0.75015 + 0xbfe5328292a35596, 0x3fe7f8ece3571771, // -0.66242, 0.74914 + 0xbfe53beae7012abe, 0x3fe7f0980e113978, // -0.66356, 0.74812 + 0xbfe5454ff5159dfb, 0x3fe7e83f87b03686, // -0.66471, 0.7471 + 0xbfe54eb1bb6dcb8f, 0x3fe7dfe3517d8937, // -0.66586, 0.74608 + 0xbfe5581038975137, 0x3fe7d7836cc33db2, // -0.667, 0.74506 + 0xbfe5616b6b204e6e, 0x3fe7cf1fdacbf179, // -0.66814, 0.74403 + 0xbfe56ac35197649e, 0x3fe7c6b89ce2d333, // -0.66928, 0.74301 + 0xbfe57417ea8bb75c, 0x3fe7be4db453a27c, // -0.67042, 0.74198 + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095 + 0xbfe586b72e2b2cfd, 0x3fe7ad6ce874dbb6, // -0.67269, 0.73992 + 0xbfe59001d5f723df, 0x3fe7a4f707bf97d2, // -0.67383, 0.73889 + 0xbfe599492a81ffbc, 0x3fe79c7d8198e56e, // -0.67496, 0.73785 + 0xbfe5a28d2a5d7250, 0x3fe79400574f55e4, // -0.67609, 0.73682 + 0xbfe5abcdd41bb0d8, 0x3fe78b7f8a320a52, // -0.67722, 0.73578 + 0xbfe5b50b264f7448, 0x3fe782fb1b90b35b, // -0.67835, 0.73474 + 0xbfe5be451f8bf980, 0x3fe77a730cbb9100, // -0.67948, 0.7337 + 0xbfe5c77bbe65018c, 0x3fe771e75f037261, // -0.6806, 0.73265 + 0xbfe5d0af016ed1d4, 0x3fe7695813b9b594, // -0.68172, 0.73161 + 0xbfe5d9dee73e345c, 0x3fe760c52c304764, // -0.68285, 0.73056 + 0xbfe5e30b6e6877f3, 0x3fe7582ea9b9a329, // -0.68397, 0.72951 + 0xbfe5ec3495837074, 0x3fe74f948da8d28d, // -0.68508, 0.72846 + 0xbfe5f55a5b2576f8, 0x3fe746f6d9516d59, // -0.6862, 0.72741 + 0xbfe5fe7cbde56a0f, 0x3fe73e558e079942, // -0.68732, 0.72636 + 0xbfe6079bbc5aadfa, 0x3fe735b0ad2009b2, // -0.68843, 0.7253 + 0xbfe610b7551d2cde, 0x3fe72d0837efff97, // -0.68954, 0.72425 + 0xbfe619cf86c55702, 0x3fe7245c2fcd492a, // -0.69065, 0.72319 + 0xbfe622e44fec22ff, 0x3fe71bac960e41bf, // -0.69176, 0.72213 + 0xbfe62bf5af2b0dfd, 0x3fe712f96c09d18d, // -0.69287, 0.72107 + 0xbfe63503a31c1be8, 0x3fe70a42b3176d7a, // -0.69397, 0.72 + 0xbfe63e0e2a59d7aa, 0x3fe701886c8f16e6, // -0.69508, 0.71894 + 0xbfe64715437f535b, 0x3fe6f8ca99c95b75, // -0.69618, 0.71787 + 0xbfe65018ed28287f, 0x3fe6f0093c1f54de, // -0.69728, 0.7168 + 0xbfe6591925f0783e, 0x3fe6e74454eaa8ae, // -0.69838, 0.71573 + 0xbfe66215ec74eb91, 0x3fe6de7be585881d, // -0.69947, 0.71466 + 0xbfe66b0f3f52b386, 0x3fe6d5afef4aafcc, // -0.70057, 0.71358 + 0xbfe674051d27896c, 0x3fe6cce07395679f, // -0.70166, 0.71251 + 0xbfe67cf78491af10, 0x3fe6c40d73c18275, // -0.70275, 0.71143 + 0xbfe685e6742feeef, 0x3fe6bb36f12b5e06, // -0.70385, 0.71035 + 0xbfe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // -0.70493, 0.70927 + 0xbfe697b9e686941c, 0x3fe6a97f692c82ea, // -0.70602, 0.70819 + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711 + 0xbfe6a97f692c82ea, 0x3fe697b9e686941c, // -0.70819, 0.70602 + 0xbfe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // -0.70927, 0.70493 + 0xbfe6bb36f12b5e06, 0x3fe685e6742feeef, // -0.71035, 0.70385 + 0xbfe6c40d73c18275, 0x3fe67cf78491af10, // -0.71143, 0.70275 + 0xbfe6cce07395679f, 0x3fe674051d27896c, // -0.71251, 0.70166 + 0xbfe6d5afef4aafcc, 0x3fe66b0f3f52b386, // -0.71358, 0.70057 + 0xbfe6de7be585881d, 0x3fe66215ec74eb91, // -0.71466, 0.69947 + 0xbfe6e74454eaa8ae, 0x3fe6591925f0783e, // -0.71573, 0.69838 + 0xbfe6f0093c1f54de, 0x3fe65018ed28287f, // -0.7168, 0.69728 + 0xbfe6f8ca99c95b75, 0x3fe64715437f535b, // -0.71787, 0.69618 + 0xbfe701886c8f16e6, 0x3fe63e0e2a59d7aa, // -0.71894, 0.69508 + 0xbfe70a42b3176d7a, 0x3fe63503a31c1be8, // -0.72, 0.69397 + 0xbfe712f96c09d18d, 0x3fe62bf5af2b0dfd, // -0.72107, 0.69287 + 0xbfe71bac960e41bf, 0x3fe622e44fec22ff, // -0.72213, 0.69176 + 0xbfe7245c2fcd492a, 0x3fe619cf86c55702, // -0.72319, 0.69065 + 0xbfe72d0837efff97, 0x3fe610b7551d2cde, // -0.72425, 0.68954 + 0xbfe735b0ad2009b2, 0x3fe6079bbc5aadfa, // -0.7253, 0.68843 + 0xbfe73e558e079942, 0x3fe5fe7cbde56a0f, // -0.72636, 0.68732 + 0xbfe746f6d9516d59, 0x3fe5f55a5b2576f8, // -0.72741, 0.6862 + 0xbfe74f948da8d28d, 0x3fe5ec3495837074, // -0.72846, 0.68508 + 0xbfe7582ea9b9a329, 0x3fe5e30b6e6877f3, // -0.72951, 0.68397 + 0xbfe760c52c304764, 0x3fe5d9dee73e345c, // -0.73056, 0.68285 + 0xbfe7695813b9b594, 0x3fe5d0af016ed1d4, // -0.73161, 0.68172 + 0xbfe771e75f037261, 0x3fe5c77bbe65018c, // -0.73265, 0.6806 + 0xbfe77a730cbb9100, 0x3fe5be451f8bf980, // -0.7337, 0.67948 + 0xbfe782fb1b90b35b, 0x3fe5b50b264f7448, // -0.73474, 0.67835 + 0xbfe78b7f8a320a52, 0x3fe5abcdd41bb0d8, // -0.73578, 0.67722 + 0xbfe79400574f55e4, 0x3fe5a28d2a5d7250, // -0.73682, 0.67609 + 0xbfe79c7d8198e56e, 0x3fe599492a81ffbc, // -0.73785, 0.67496 + 0xbfe7a4f707bf97d2, 0x3fe59001d5f723df, // -0.73889, 0.67383 + 0xbfe7ad6ce874dbb6, 0x3fe586b72e2b2cfd, // -0.73992, 0.67269 + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156 + 0xbfe7be4db453a27c, 0x3fe57417ea8bb75c, // -0.74198, 0.67042 + 0xbfe7c6b89ce2d333, 0x3fe56ac35197649e, // -0.74301, 0.66928 + 0xbfe7cf1fdacbf179, 0x3fe5616b6b204e6e, // -0.74403, 0.66814 + 0xbfe7d7836cc33db2, 0x3fe5581038975137, // -0.74506, 0.667 + 0xbfe7dfe3517d8937, 0x3fe54eb1bb6dcb8f, // -0.74608, 0.66586 + 0xbfe7e83f87b03686, 0x3fe5454ff5159dfb, // -0.7471, 0.66471 + 0xbfe7f0980e113978, 0x3fe53beae7012abe, // -0.74812, 0.66356 + 0xbfe7f8ece3571771, 0x3fe5328292a35596, // -0.74914, 0.66242 + 0xbfe8013e0638e795, 0x3fe52916f96f8388, // -0.75015, 0.66127 + 0xbfe8098b756e52fa, 0x3fe51fa81cd99aa6, // -0.75117, 0.66011 + 0xbfe811d52faf94dc, 0x3fe51635fe5601d7, // -0.75218, 0.65896 + 0xbfe81a1b33b57acc, 0x3fe50cc09f59a09b, // -0.75319, 0.65781 + 0xbfe8225d803964e5, 0x3fe503480159ded2, // -0.75419, 0.65665 + 0xbfe82a9c13f545ff, 0x3fe4f9cc25cca486, // -0.7552, 0.65549 + 0xbfe832d6eda3a3e0, 0x3fe4f04d0e2859aa, // -0.75621, 0.65433 + 0xbfe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // -0.75721, 0.65317 + 0xbfe843416dc4cce2, 0x3fe4dd453076b064, // -0.75821, 0.65201 + 0xbfe84b7111af83f9, 0x3fe4d3bc6d589f80, // -0.75921, 0.65085 + 0xbfe8539cf67c9029, 0x3fe4ca30740218a3, // -0.76021, 0.64968 + 0xbfe85bc51ae958cc, 0x3fe4c0a145ec0004, // -0.7612, 0.64851 + 0xbfe863e97db3d95a, 0x3fe4b70ee48fb869, // -0.7622, 0.64735 + 0xbfe86c0a1d9aa195, 0x3fe4ad79516722f0, // -0.76319, 0.64618 + 0xbfe87426f95cd5bd, 0x3fe4a3e08dec9ed6, // -0.76418, 0.645 + 0xbfe87c400fba2ebf, 0x3fe49a449b9b0938, // -0.76517, 0.64383 + 0xbfe884555f72fa6b, 0x3fe490a57bedbcdf, // -0.76615, 0.64266 + 0xbfe88c66e7481ba1, 0x3fe48703306091fe, // -0.76714, 0.64148 + 0xbfe89474a5fb0a84, 0x3fe47d5dba6fde01, // -0.76812, 0.6403 + 0xbfe89c7e9a4dd4ab, 0x3fe473b51b987347, // -0.7691, 0.63912 + 0xbfe8a484c3031d50, 0x3fe46a095557a0f1, // -0.77008, 0.63794 + 0xbfe8ac871ede1d88, 0x3fe4605a692b32a2, // -0.77106, 0.63676 + 0xbfe8b485aca2a468, 0x3fe456a858917046, // -0.77204, 0.63558 + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439 + 0xbfe8c47758fa71cb, 0x3fe4433ad0117b1d, // -0.77398, 0.63321 + 0xbfe8cc6a75184655, 0x3fe4397f5b2a4380, // -0.77495, 0.63202 + 0xbfe8d459be34bdfa, 0x3fe42fc0c7d3adbb, // -0.77592, 0.63083 + 0xbfe8dc45331698cc, 0x3fe425ff178e6bb1, // -0.77689, 0.62964 + 0xbfe8e42cd2852e0a, 0x3fe41c3a4bdbaa26, // -0.77785, 0.62845 + 0xbfe8ec109b486c49, 0x3fe41272663d108c, // -0.77882, 0.62725 + 0xbfe8f3f08c28d9ac, 0x3fe408a76834c0c0, // -0.77978, 0.62606 + 0xbfe8fbcca3ef940d, 0x3fe3fed9534556d4, // -0.78074, 0.62486 + 0xbfe903a4e1665133, 0x3fe3f50828f1e8d2, // -0.78169, 0.62366 + 0xbfe90b7943575efe, 0x3fe3eb33eabe0680, // -0.78265, 0.62246 + 0xbfe91349c88da398, 0x3fe3e15c9a2db922, // -0.7836, 0.62126 + 0xbfe91b166fd49da2, 0x3fe3d78238c58343, // -0.78456, 0.62006 + 0xbfe922df37f8646a, 0x3fe3cda4c80a6076, // -0.78551, 0.61885 + 0xbfe92aa41fc5a815, 0x3fe3c3c44981c517, // -0.78646, 0.61765 + 0xbfe932652609b1cf, 0x3fe3b9e0beb19e18, // -0.7874, 0.61644 + 0xbfe93a22499263fc, 0x3fe3affa292050b9, // -0.78835, 0.61523 + 0xbfe941db892e3a65, 0x3fe3a6108a54ba58, // -0.78929, 0.61402 + 0xbfe94990e3ac4a6c, 0x3fe39c23e3d63029, // -0.79023, 0.61281 + 0xbfe9514257dc4335, 0x3fe39234372c7f04, // -0.79117, 0.6116 + 0xbfe958efe48e6dd7, 0x3fe3884185dfeb22, // -0.79211, 0.61038 + 0xbfe960998893ad8c, 0x3fe37e4bd1792fe2, // -0.79304, 0.60917 + 0xbfe9683f42bd7fe1, 0x3fe374531b817f8d, // -0.79398, 0.60795 + 0xbfe96fe111ddfce0, 0x3fe36a576582831b, // -0.79491, 0.60673 + 0xbfe9777ef4c7d742, 0x3fe36058b10659f3, // -0.79584, 0.60551 + 0xbfe97f18ea4e5c9e, 0x3fe35656ff9799ae, // -0.79676, 0.60429 + 0xbfe986aef1457594, 0x3fe34c5252c14de1, // -0.79769, 0.60307 + 0xbfe98e410881a600, 0x3fe3424aac0ef7d6, // -0.79861, 0.60184 + 0xbfe995cf2ed80d22, 0x3fe338400d0c8e57, // -0.79954, 0.60062 + 0xbfe99d59631e65d5, 0x3fe32e3277467d6b, // -0.80046, 0.59939 + 0xbfe9a4dfa42b06b2, 0x3fe32421ec49a620, // -0.80138, 0.59816 + 0xbfe9ac61f0d4e247, 0x3fe31a0e6da35e44, // -0.80229, 0.59693 + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957 + 0xbfe9bb5aa85f2098, 0x3fe305de9b921a94, // -0.80412, 0.59447 + 0xbfe9c2d110f075c3, 0x3fe2fbc24b441015, // -0.80503, 0.59323 + 0xbfe9ca438080eadb, 0x3fe2f1a30d86773a, // -0.80594, 0.592 + 0xbfe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // -0.80685, 0.59076 + 0xbfe9d91c7007d5a6, 0x3fe2dd5bcffb7616, // -0.80775, 0.58952 + 0xbfe9e082edb42472, 0x3fe2d333d34e9bb7, // -0.80866, 0.58828 + 0xbfe9e7e56dcb45bd, 0x3fe2c908ef734e57, // -0.80956, 0.58704 + 0xbfe9ef43ef29af94, 0x3fe2bedb25faf3ea, // -0.81046, 0.5858 + 0xbfe9f69e70ac75bc, 0x3fe2b4aa787764c4, // -0.81135, 0.58455 + 0xbfe9fdf4f13149de, 0x3fe2aa76e87aeb58, // -0.81225, 0.58331 + 0xbfea05476f967bb5, 0x3fe2a040779843fb, // -0.81314, 0.58206 + 0xbfea0c95eabaf937, 0x3fe2960727629ca8, // -0.81404, 0.58081 + 0xbfea13e0617e4ec7, 0x3fe28bcaf96d94ba, // -0.81493, 0.57956 + 0xbfea1b26d2c0a75e, 0x3fe2818bef4d3cba, // -0.81581, 0.57831 + 0xbfea22693d62ccb9, 0x3fe2774a0a961612, // -0.8167, 0.57706 + 0xbfea29a7a0462782, 0x3fe26d054cdd12df, // -0.81758, 0.57581 + 0xbfea30e1fa4cbf81, 0x3fe262bdb7b795a2, // -0.81847, 0.57455 + 0xbfea38184a593bc6, 0x3fe258734cbb7110, // -0.81935, 0.5733 + 0xbfea3f4a8f4ee2d2, 0x3fe24e260d7ee7c9, // -0.82023, 0.57204 + 0xbfea4678c8119ac8, 0x3fe243d5fb98ac1f, // -0.8211, 0.57078 + 0xbfea4da2f385e997, 0x3fe23983189fdfd5, // -0.82198, 0.56952 + 0xbfea54c91090f524, 0x3fe22f2d662c13e1, // -0.82285, 0.56826 + 0xbfea5beb1e188375, 0x3fe224d4e5d5482e, // -0.82372, 0.567 + 0xbfea63091b02fae2, 0x3fe21a799933eb58, // -0.82459, 0.56573 + 0xbfea6a230637623b, 0x3fe2101b81e0da78, // -0.82546, 0.56447 + 0xbfea7138de9d60f5, 0x3fe205baa17560d6, // -0.82632, 0.5632 + 0xbfea784aa31d3f55, 0x3fe1fb56f98b37b8, // -0.82718, 0.56193 + 0xbfea7f58529fe69d, 0x3fe1f0f08bbc861b, // -0.82805, 0.56066 + 0xbfea8661ec0ee133, 0x3fe1e68759a3e074, // -0.8289, 0.55939 + 0xbfea8d676e545ad2, 0x3fe1dc1b64dc4872, // -0.82976, 0.55812 + 0xbfea9468d85b20ae, 0x3fe1d1acaf012cc2, // -0.83062, 0.55685 + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557 + 0xbfeaa25f5f5aee60, 0x3fe1bcc706804467, // -0.83232, 0.55429 + 0xbfeaa9547a2cb98e, 0x3fe1b250171373be, // -0.83317, 0.55302 + 0xbfeab045787157ff, 0x3fe1a7d66d0516e6, // -0.83402, 0.55174 + 0xbfeab7325916c0d4, 0x3fe19d5a09f2b9b8, // -0.83486, 0.55046 + 0xbfeabe1b1b0b8dac, 0x3fe192daef7a5386, // -0.83571, 0.54918 + 0xbfeac4ffbd3efac8, 0x3fe188591f3a46e5, // -0.83655, 0.54789 + 0xbfeacbe03ea0e73b, 0x3fe17dd49ad16161, // -0.83739, 0.54661 + 0xbfead2bc9e21d511, 0x3fe1734d63dedb49, // -0.83822, 0.54532 + 0xbfead994dab2e979, 0x3fe168c37c025764, // -0.83906, 0.54404 + 0xbfeae068f345ecef, 0x3fe15e36e4dbe2bc, // -0.83989, 0.54275 + 0xbfeae738e6cd4b67, 0x3fe153a7a00bf453, // -0.84073, 0.54146 + 0xbfeaee04b43c1474, 0x3fe14915af336ceb, // -0.84155, 0.54017 + 0xbfeaf4cc5a85fb73, 0x3fe13e8113f396c1, // -0.84238, 0.53888 + 0xbfeafb8fd89f57b6, 0x3fe133e9cfee254e, // -0.84321, 0.53759 + 0xbfeb024f2d7d24a9, 0x3fe1294fe4c5350a, // -0.84403, 0.53629 + 0xbfeb090a58150200, 0x3fe11eb3541b4b22, // -0.84485, 0.535 + 0xbfeb0fc1575d33db, 0x3fe114141f935545, // -0.84567, 0.5337 + 0xbfeb16742a4ca2f5, 0x3fe1097248d0a956, // -0.84649, 0.5324 + 0xbfeb1d22cfdadcc6, 0x3fe0fecdd1770537, // -0.84731, 0.5311 + 0xbfeb23cd470013b4, 0x3fe0f426bb2a8e7d, // -0.84812, 0.5298 + 0xbfeb2a738eb51f33, 0x3fe0e97d078fd23b, // -0.84893, 0.5285 + 0xbfeb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // -0.84974, 0.5272 + 0xbfeb37b38bb54c09, 0x3fe0d421cf03c12b, // -0.85055, 0.5259 + 0xbfeb3e4d3ef55712, 0x3fe0c9704d5d898f, // -0.85136, 0.52459 + 0xbfeb44e2beaf0a61, 0x3fe0bebc34ff4646, // -0.85216, 0.52328 + 0xbfeb4b7409de7925, 0x3fe0b405878f85ec, // -0.85296, 0.52198 + 0xbfeb52011f805c92, 0x3fe0a94c46b53d0b, // -0.85376, 0.52067 + 0xbfeb5889fe921405, 0x3fe09e907417c5e1, // -0.85456, 0.51936 + 0xbfeb5f0ea611a532, 0x3fe093d2115ee018, // -0.85535, 0.51804 + 0xbfeb658f14fdbc47, 0x3fe089112032b08c, // -0.85615, 0.51673 + 0xbfeb6c0b4a55ac17, 0x3fe07e4da23bc102, // -0.85694, 0.51542 + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141 + 0xbfeb78f70449a34b, 0x3fe068bf0691c028, // -0.85852, 0.51279 + 0xbfeb7f6686e792ea, 0x3fe05df3ec31b8b6, // -0.8593, 0.51147 + 0xbfeb85d1cbf52c02, 0x3fe053264bad0483, // -0.86009, 0.51015 + 0xbfeb8c38d27504e9, 0x3fe0485626ae221a, // -0.86087, 0.50883 + 0xbfeb929b996a5b7f, 0x3fe03d837edff370, // -0.86165, 0.50751 + 0xbfeb98fa1fd9155e, 0x3fe032ae55edbd95, // -0.86242, 0.50619 + 0xbfeb9f5464c5bffc, 0x3fe027d6ad83287e, // -0.8632, 0.50486 + 0xbfeba5aa673590d2, 0x3fe01cfc874c3eb7, // -0.86397, 0.50354 + 0xbfebabfc262e6586, 0x3fe0121fe4f56d2c, // -0.86474, 0.50221 + 0xbfebb249a0b6c40d, 0x3fe00740c82b82e0, // -0.86551, 0.50089 + 0xbfebb892d5d5dad5, 0x3fdff8be6537615e, // -0.86628, 0.49956 + 0xbfebbed7c49380ea, 0x3fdfe2f64be7120f, // -0.86705, 0.49823 + 0xbfebc5186bf8361d, 0x3fdfcd2947c1ff57, // -0.86781, 0.4969 + 0xbfebcb54cb0d2327, 0x3fdfb7575c24d2de, // -0.86857, 0.49557 + 0xbfebd18ce0dc19d6, 0x3fdfa1808c6cf7e0, // -0.86933, 0.49423 + 0xbfebd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // -0.87009, 0.4929 + 0xbfebddf02cd2b983, 0x3fdf75c44e26a852, // -0.87084, 0.49156 + 0xbfebe41b611154c1, 0x3fdf5fdee656cda3, // -0.8716, 0.49023 + 0xbfebea424837de6d, 0x3fdf49f4a7e97729, // -0.87235, 0.48889 + 0xbfebf064e15377dd, 0x3fdf3405963fd068, // -0.87309, 0.48755 + 0xbfebf6832b71ec5b, 0x3fdf1e11b4bbc35c, // -0.87384, 0.48621 + 0xbfebfc9d25a1b147, 0x3fdf081906bff7fd, // -0.87459, 0.48487 + 0xbfec02b2cef1e641, 0x3fdef21b8fafd3b5, // -0.87533, 0.48353 + 0xbfec08c426725549, 0x3fdedc1952ef78d5, // -0.87607, 0.48218 + 0xbfec0ed12b3372e9, 0x3fdec61253e3c61b, // -0.87681, 0.48084 + 0xbfec14d9dc465e58, 0x3fdeb00695f25620, // -0.87755, 0.47949 + 0xbfec1ade38bce19b, 0x3fde99f61c817eda, // -0.87828, 0.47815 + 0xbfec20de3fa971b0, 0x3fde83e0eaf85113, // -0.87901, 0.4768 + 0xbfec26d9f01f2eaf, 0x3fde6dc704be97e2, // -0.87974, 0.47545 + 0xbfec2cd14931e3f1, 0x3fde57a86d3cd824, // -0.88047, 0.4741 + 0xbfec32c449f60831, 0x3fde418527dc4ffa, // -0.8812, 0.47275 + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714 + 0xbfec3e9d3ee7d262, 0x3fde1530a12779f4, // -0.88264, 0.47004 + 0xbfec44833141c004, 0x3fddfeff66a941de, // -0.88336, 0.46869 + 0xbfec4a64c7a5ac4c, 0x3fdde8c98bf86bd6, // -0.88408, 0.46733 + 0xbfec5042012b6907, 0x3fddd28f1481cc58, // -0.8848, 0.46598 + 0xbfec561adceb743e, 0x3fddbc5003b2edf8, // -0.88551, 0.46462 + 0xbfec5bef59fef85a, 0x3fdda60c5cfa10d8, // -0.88622, 0.46326 + 0xbfec61bf777fcc48, 0x3fdd8fc423c62a25, // -0.88693, 0.4619 + 0xbfec678b3488739b, 0x3fdd79775b86e389, // -0.88764, 0.46054 + 0xbfec6d5290341eb2, 0x3fdd632607ac9aa9, // -0.88835, 0.45918 + 0xbfec7315899eaad7, 0x3fdd4cd02ba8609c, // -0.88905, 0.45781 + 0xbfec78d41fe4a267, 0x3fdd3675caebf962, // -0.88975, 0.45645 + 0xbfec7e8e52233cf3, 0x3fdd2016e8e9db5b, // -0.89045, 0.45508 + 0xbfec84441f785f61, 0x3fdd09b389152ec1, // -0.89115, 0.45372 + 0xbfec89f587029c13, 0x3fdcf34baee1cd21, // -0.89184, 0.45235 + 0xbfec8fa287e13305, 0x3fdcdcdf5dc440ce, // -0.89253, 0.45098 + 0xbfec954b213411f5, 0x3fdcc66e9931c45d, // -0.89322, 0.44961 + 0xbfec9aef521bd480, 0x3fdcaff964a0421d, // -0.89391, 0.44824 + 0xbfeca08f19b9c449, 0x3fdc997fc3865388, // -0.8946, 0.44687 + 0xbfeca62a772fd919, 0x3fdc8301b95b40c2, // -0.89528, 0.4455 + 0xbfecabc169a0b901, 0x3fdc6c7f4997000a, // -0.89597, 0.44412 + 0xbfecb153f02fb87d, 0x3fdc55f877b23537, // -0.89665, 0.44275 + 0xbfecb6e20a00da99, 0x3fdc3f6d47263129, // -0.89732, 0.44137 + 0xbfecbc6bb638d10b, 0x3fdc28ddbb6cf145, // -0.898, 0.43999 + 0xbfecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // -0.89867, 0.43862 + 0xbfecc771c2736c09, 0x3fdbfbb1a05e0edc, // -0.89935, 0.43724 + 0xbfecccee20c2de9f, 0x3fdbe51517ffc0d9, // -0.90002, 0.43586 + 0xbfecd2660e12c1e6, 0x3fdbce744262deee, // -0.90068, 0.43448 + 0xbfecd7d9898b32f6, 0x3fdbb7cf2304bd01, // -0.90135, 0.43309 + 0xbfecdd489254fe65, 0x3fdba125bd63583e, // -0.90201, 0.43171 + 0xbfece2b32799a060, 0x3fdb8a7814fd5693, // -0.90267, 0.43033 + 0xbfece819488344ce, 0x3fdb73c62d520624, // -0.90333, 0.42894 + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756 + 0xbfecf2d829f1b40e, 0x3fdb4655ae2bf757, // -0.90464, 0.42617 + 0xbfecf830e8ce467b, 0x3fdb2f971db31972, // -0.9053, 0.42478 + 0xbfecfd852fff6ad4, 0x3fdb18d45bf8aca6, // -0.90595, 0.42339 + 0xbfed02d4feb2bd92, 0x3fdb020d6c7f4009, // -0.9066, 0.422 + 0xbfed082054168bac, 0x3fdaeb4252ca07ab, // -0.90724, 0.42061 + 0xbfed0d672f59d2b9, 0x3fdad473125cdc08, // -0.90789, 0.41922 + 0xbfed12a98fac410c, 0x3fdabd9faebc3980, // -0.90853, 0.41782 + 0xbfed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // -0.90917, 0.41643 + 0xbfed1d20dc40c15c, 0x3fda8fec8bf5b166, // -0.90981, 0.41503 + 0xbfed2255c6e5a4e1, 0x3fda790cd3dbf31a, // -0.91044, 0.41364 + 0xbfed2786335f52fc, 0x3fda622906a70b63, // -0.91107, 0.41224 + 0xbfed2cb220e0ef9f, 0x3fda4b4127dea1e4, // -0.91171, 0.41084 + 0xbfed31d98e9e503a, 0x3fda34553b0afee5, // -0.91234, 0.40944 + 0xbfed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // -0.91296, 0.40804 + 0xbfed3c1ae79f2b4e, 0x3fda067145664d57, // -0.91359, 0.40664 + 0xbfed4134d14dc93a, 0x3fd9ef7943a8ed8a, // -0.91421, 0.40524 + 0xbfed464a380e7242, 0x3fd9d87d4207b0ab, // -0.91483, 0.40384 + 0xbfed4b5b1b187524, 0x3fd9c17d440df9f2, // -0.91545, 0.40243 + 0xbfed506779a3d2d9, 0x3fd9aa794d47c9ee, // -0.91606, 0.40103 + 0xbfed556f52e93eb1, 0x3fd993716141bdfe, // -0.91668, 0.39962 + 0xbfed5a72a6221e73, 0x3fd97c6583890fc2, // -0.91729, 0.39822 + 0xbfed5f7172888a7f, 0x3fd96555b7ab948f, // -0.9179, 0.39681 + 0xbfed646bb7574de5, 0x3fd94e420137bce3, // -0.91851, 0.3954 + 0xbfed696173c9e68b, 0x3fd9372a63bc93d7, // -0.91911, 0.39399 + 0xbfed6e52a71c8547, 0x3fd9200ee2c9be97, // -0.91972, 0.39258 + 0xbfed733f508c0dff, 0x3fd908ef81ef7bd1, // -0.92032, 0.39117 + 0xbfed78276f5617c6, 0x3fd8f1cc44bea329, // -0.92092, 0.38976 + 0xbfed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // -0.92151, 0.38835 + 0xbfed81ea09f38b63, 0x3fd8c37a439f884f, // -0.92211, 0.38693 + 0xbfed86c48445a450, 0x3fd8ac4b86d5ed44, // -0.9227, 0.38552 + 0xbfed8b9a70ef9cb4, 0x3fd89518fbff098e, // -0.92329, 0.3841 + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268 + 0xbfed95389e50429b, 0x3fd866a88a792ea0, // -0.92447, 0.38127 + 0xbfed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // -0.92505, 0.37985 + 0xbfed9ec48c26b1f3, 0x3fd838290bb359c8, // -0.92563, 0.37843 + 0xbfeda383a9668988, 0x3fd820e3b04eaac4, // -0.92621, 0.37701 + 0xbfeda83e348f613b, 0x3fd8099a9c5c362d, // -0.92679, 0.37559 + 0xbfedacf42ce68ab9, 0x3fd7f24dd37341e3, // -0.92736, 0.37416 + 0xbfedb1a591b20c38, 0x3fd7dafd592ba621, // -0.92794, 0.37274 + 0xbfedb6526238a09b, 0x3fd7c3a9311dcce7, // -0.92851, 0.37132 + 0xbfedbafa9dc1b78d, 0x3fd7ac515ee2b172, // -0.92907, 0.36989 + 0xbfedbf9e4395759a, 0x3fd794f5e613dfae, // -0.92964, 0.36847 + 0xbfedc43d52fcb453, 0x3fd77d96ca4b73a6, // -0.93021, 0.36704 + 0xbfedc8d7cb410260, 0x3fd766340f2418f6, // -0.93077, 0.36561 + 0xbfedcd6dabaca3a5, 0x3fd74ecdb8390a3e, // -0.93133, 0.36418 + 0xbfedd1fef38a915a, 0x3fd73763c9261092, // -0.93188, 0.36276 + 0xbfedd68ba2267a25, 0x3fd71ff6458782ec, // -0.93244, 0.36133 + 0xbfeddb13b6ccc23d, 0x3fd7088530fa459e, // -0.93299, 0.3599 + 0xbfeddf9730ca837b, 0x3fd6f1108f1bc9c5, // -0.93354, 0.35846 + 0xbfede4160f6d8d81, 0x3fd6d998638a0cb5, // -0.93409, 0.35703 + 0xbfede890520465ce, 0x3fd6c21cb1e39771, // -0.93464, 0.3556 + 0xbfeded05f7de47da, 0x3fd6aa9d7dc77e16, // -0.93518, 0.35416 + 0xbfedf177004b2534, 0x3fd6931acad55f51, // -0.93573, 0.35273 + 0xbfedf5e36a9ba59c, 0x3fd67b949cad63ca, // -0.93627, 0.35129 + 0xbfedfa4b3621271d, 0x3fd6640af6f03d9e, // -0.9368, 0.34986 + 0xbfedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // -0.93734, 0.34842 + 0xbfee030cee1435b8, 0x3fd634ed533be58e, // -0.93787, 0.34698 + 0xbfee0766d9280f54, 0x3fd61d595c88c203, // -0.9384, 0.34554 + 0xbfee0bbc22bd8349, 0x3fd605c1fcc88f63, // -0.93893, 0.3441 + 0xbfee100cca2980ac, 0x3fd5ee27379ea693, // -0.93946, 0.34266 + 0xbfee1458cec1ad83, 0x3fd5d68910aee686, // -0.93998, 0.34122 + 0xbfee18a02fdc66d9, 0x3fd5bee78b9db3b6, // -0.94051, 0.33978 + 0xbfee1ce2ecd0c0d8, 0x3fd5a742ac0ff78d, // -0.94103, 0.33833 + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689 + 0xbfee255a77a63bb8, 0x3fd577eeec151e47, // -0.94206, 0.33545 + 0xbfee298f4439197a, 0x3fd5604012f467b4, // -0.94257, 0.334 + 0xbfee2dbf6a0911d9, 0x3fd5488dedeff3be, // -0.94308, 0.33255 + 0xbfee31eae870ce25, 0x3fd530d880af3c24, // -0.94359, 0.33111 + 0xbfee3611becbaf69, 0x3fd5191fceda3c35, // -0.9441, 0.32966 + 0xbfee3a33ec75ce85, 0x3fd50163dc197047, // -0.9446, 0.32821 + 0xbfee3e5170cbfc46, 0x3fd4e9a4ac15d520, // -0.94511, 0.32676 + 0xbfee426a4b2bc17e, 0x3fd4d1e24278e76a, // -0.94561, 0.32531 + 0xbfee467e7af35f23, 0x3fd4ba1ca2eca31c, // -0.94611, 0.32386 + 0xbfee4a8dff81ce5e, 0x3fd4a253d11b82f3, // -0.9466, 0.32241 + 0xbfee4e98d836c0af, 0x3fd48a87d0b07fd7, // -0.94709, 0.32096 + 0xbfee529f04729ffc, 0x3fd472b8a5571054, // -0.94759, 0.3195 + 0xbfee56a083968eb1, 0x3fd45ae652bb2800, // -0.94807, 0.31805 + 0xbfee5a9d550467d3, 0x3fd44310dc8936f0, // -0.94856, 0.31659 + 0xbfee5e95781ebf1c, 0x3fd42b38466e2928, // -0.94905, 0.31514 + 0xbfee6288ec48e112, 0x3fd4135c94176602, // -0.94953, 0.31368 + 0xbfee6677b0e6d31e, 0x3fd3fb7dc932cfa4, // -0.95001, 0.31222 + 0xbfee6a61c55d53a7, 0x3fd3e39be96ec271, // -0.95049, 0.31077 + 0xbfee6e472911da27, 0x3fd3cbb6f87a146e, // -0.95096, 0.30931 + 0xbfee7227db6a9744, 0x3fd3b3cefa0414b7, // -0.95144, 0.30785 + 0xbfee7603dbce74e9, 0x3fd39be3f1bc8aef, // -0.95191, 0.30639 + 0xbfee79db29a5165a, 0x3fd383f5e353b6aa, // -0.95238, 0.30493 + 0xbfee7dadc456d850, 0x3fd36c04d27a4edf, // -0.95284, 0.30347 + 0xbfee817bab4cd10d, 0x3fd35410c2e18152, // -0.95331, 0.30201 + 0xbfee8544ddf0d075, 0x3fd33c19b83af207, // -0.95377, 0.30054 + 0xbfee89095bad6025, 0x3fd3241fb638baaf, // -0.95423, 0.29908 + 0xbfee8cc923edc388, 0x3fd30c22c08d6a13, // -0.95469, 0.29762 + 0xbfee9084361df7f3, 0x3fd2f422daec0386, // -0.95514, 0.29615 + 0xbfee943a91aab4b4, 0x3fd2dc200907fe51, // -0.95559, 0.29469 + 0xbfee97ec36016b30, 0x3fd2c41a4e954520, // -0.95605, 0.29322 + 0xbfee9b99229046f8, 0x3fd2ac11af483572, // -0.95649, 0.29175 + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028 + 0xbfeea2e4d212c000, 0x3fd27bf7d0f2c346, // -0.95738, 0.28882 + 0xbfeea68393e65800, 0x3fd263e6995554ba, // -0.95783, 0.28735 + 0xbfeeaa1d9bb20af3, 0x3fd24bd28bb37672, // -0.95827, 0.28588 + 0xbfeeadb2e8e7a88e, 0x3fd233bbabc3bb72, // -0.9587, 0.28441 + 0xbfeeb1437af9bb34, 0x3fd21ba1fd3d2623, // -0.95914, 0.28294 + 0xbfeeb4cf515b8811, 0x3fd2038583d727bd, // -0.95957, 0.28146 + 0xbfeeb8566b810f2a, 0x3fd1eb6643499fbb, // -0.96, 0.27999 + 0xbfeebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // -0.96043, 0.27852 + 0xbfeebf5668eaf2ef, 0x3fd1bb1f7b999480, // -0.96086, 0.27705 + 0xbfeec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // -0.96128, 0.27557 + 0xbfeec6436ee60309, 0x3fd18acdc3f4873a, // -0.9617, 0.2741 + 0xbfeec9b2d3c3bf84, 0x3fd172a0d7765177, // -0.96212, 0.27262 + 0xbfeecd1d792c8f10, 0x3fd15a713a28b9d9, // -0.96254, 0.27115 + 0xbfeed0835e999009, 0x3fd1423eefc69378, // -0.96295, 0.26967 + 0xbfeed3e483849c51, 0x3fd12a09fc0b1b12, // -0.96337, 0.26819 + 0xbfeed740e7684963, 0x3fd111d262b1f677, // -0.96378, 0.26671 + 0xbfeeda9889bfe86a, 0x3fd0f998277733f7, // -0.96418, 0.26523 + 0xbfeeddeb6a078651, 0x3fd0e15b4e1749cd, // -0.96459, 0.26375 + 0xbfeee13987bbebdc, 0x3fd0c91bda4f158d, // -0.96499, 0.26227 + 0xbfeee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // -0.96539, 0.26079 + 0xbfeee7c77961dc9e, 0x3fd09895327b465e, // -0.96579, 0.25931 + 0xbfeeeb074c50a544, 0x3fd0804e05eb661e, // -0.96619, 0.25783 + 0xbfeeee425aa6b09a, 0x3fd068044deab002, // -0.96658, 0.25635 + 0xbfeef178a3e473c2, 0x3fd04fb80e37fdae, // -0.96698, 0.25487 + 0xbfeef4aa278b2032, 0x3fd037694a928cac, // -0.96737, 0.25338 + 0xbfeef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // -0.96775, 0.2519 + 0xbfeefafedc1ba8b7, 0x3fd006c4466e54af, // -0.96814, 0.25041 + 0xbfeefe220c0b95ec, 0x3fcfdcdc1adfedf8, // -0.96852, 0.24893 + 0xbfef014074708ed3, 0x3fcfac2abeff57ff, // -0.9689, 0.24744 + 0xbfef045a14cf738c, 0x3fcf7b7480bd3801, // -0.96928, 0.24596 + 0xbfef076eecade0fa, 0x3fcf4ab9679c9f5c, // -0.96966, 0.24447 + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298 + 0xbfef0d8a410379c5, 0x3fcee934c2d006c7, // -0.9704, 0.24149 + 0xbfef1090bc898f5f, 0x3fceb86b462de348, // -0.97077, 0.24 + 0xbfef13926dad024e, 0x3fce879d0cc0fdaf, // -0.97114, 0.23851 + 0xbfef168f53f7205d, 0x3fce56ca1e101a1b, // -0.9715, 0.23702 + 0xbfef19876ef1f486, 0x3fce25f281a2b684, // -0.97187, 0.23553 + 0xbfef1c7abe284708, 0x3fcdf5163f01099a, // -0.97223, 0.23404 + 0xbfef1f6941259d7a, 0x3fcdc4355db40195, // -0.97258, 0.23255 + 0xbfef2252f7763ada, 0x3fcd934fe5454311, // -0.97294, 0.23106 + 0xbfef2537e0a71f9f, 0x3fcd6265dd3f27e3, // -0.97329, 0.22957 + 0xbfef2817fc4609ce, 0x3fcd31774d2cbdee, // -0.97364, 0.22807 + 0xbfef2af349e17507, 0x3fcd00843c99c5f9, // -0.97399, 0.22658 + 0xbfef2dc9c9089a9d, 0x3fcccf8cb312b286, // -0.97434, 0.22508 + 0xbfef309b794b719f, 0x3fcc9e90b824a6a9, // -0.97468, 0.22359 + 0xbfef33685a3aaef0, 0x3fcc6d90535d74dc, // -0.97503, 0.22209 + 0xbfef36306b67c556, 0x3fcc3c8b8c4b9dd7, // -0.97536, 0.2206 + 0xbfef38f3ac64e589, 0x3fcc0b826a7e4f63, // -0.9757, 0.2191 + 0xbfef3bb21cc4fe47, 0x3fcbda74f5856330, // -0.97604, 0.2176 + 0xbfef3e6bbc1bbc65, 0x3fcba96334f15dad, // -0.97637, 0.21611 + 0xbfef412089fd8adc, 0x3fcb784d30536cda, // -0.9767, 0.21461 + 0xbfef43d085ff92dd, 0x3fcb4732ef3d6722, // -0.97703, 0.21311 + 0xbfef467bafb7bbe0, 0x3fcb16147941ca2a, // -0.97735, 0.21161 + 0xbfef492206bcabb4, 0x3fcae4f1d5f3b9ab, // -0.97768, 0.21011 + 0xbfef4bc38aa5c694, 0x3fcab3cb0ce6fe44, // -0.978, 0.20861 + 0xbfef4e603b0b2f2d, 0x3fca82a025b00451, // -0.97832, 0.20711 + 0xbfef50f81785c6b9, 0x3fca517127e3dabc, // -0.97863, 0.20561 + 0xbfef538b1faf2d07, 0x3fca203e1b1831da, // -0.97895, 0.20411 + 0xbfef56195321c090, 0x3fc9ef0706e35a35, // -0.97926, 0.20261 + 0xbfef58a2b1789e84, 0x3fc9bdcbf2dc4366, // -0.97957, 0.2011 + 0xbfef5b273a4fa2d9, 0x3fc98c8ce69a7aec, // -0.97988, 0.1996 + 0xbfef5da6ed43685d, 0x3fc95b49e9b62af9, // -0.98018, 0.1981 + 0xbfef6021c9f148c2, 0x3fc92a0303c8194f, // -0.98048, 0.19659 + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509 + 0xbfef6508fef47bd5, 0x3fc8c7699b34ca7e, // -0.98108, 0.19359 + 0xbfef677556883cee, 0x3fc8961727c41804, // -0.98138, 0.19208 + 0xbfef69dcd652f5de, 0x3fc864c0e9b2b6cf, // -0.98167, 0.19057 + 0xbfef6c3f7df5bbb7, 0x3fc83366e89c64c5, // -0.98196, 0.18907 + 0xbfef6e9d4d1262ca, 0x3fc802092c1d744b, // -0.98225, 0.18756 + 0xbfef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // -0.98254, 0.18606 + 0xbfef734a60446279, 0x3fc79f429f59e11d, // -0.98282, 0.18455 + 0xbfef7599a3a12077, 0x3fc76dd9de50bf31, // -0.98311, 0.18304 + 0xbfef77e40d068a90, 0x3fc73c6d8055fe0a, // -0.98339, 0.18153 + 0xbfef7a299c1a322a, 0x3fc70afd8d08c4ff, // -0.98366, 0.18002 + 0xbfef7c6a50826840, 0x3fc6d98a0c08c8da, // -0.98394, 0.17851 + 0xbfef7ea629e63d6e, 0x3fc6a81304f64ab2, // -0.98421, 0.177 + 0xbfef80dd27ed8204, 0x3fc676987f7216b8, // -0.98448, 0.17549 + 0xbfef830f4a40c60c, 0x3fc6451a831d830d, // -0.98475, 0.17398 + 0xbfef853c9089595e, 0x3fc61399179a6e94, // -0.98501, 0.17247 + 0xbfef8764fa714ba9, 0x3fc5e214448b3fc6, // -0.98528, 0.17096 + 0xbfef898887a36c84, 0x3fc5b08c1192e381, // -0.98554, 0.16945 + 0xbfef8ba737cb4b78, 0x3fc57f008654cbde, // -0.9858, 0.16794 + 0xbfef8dc10a95380d, 0x3fc54d71aa74ef02, // -0.98605, 0.16643 + 0xbfef8fd5ffae41db, 0x3fc51bdf8597c5f2, // -0.98631, 0.16491 + 0xbfef91e616c43891, 0x3fc4ea4a1f624b61, // -0.98656, 0.1634 + 0xbfef93f14f85ac08, 0x3fc4b8b17f79fa88, // -0.98681, 0.16189 + 0xbfef95f7a9a1ec47, 0x3fc48715ad84cdf5, // -0.98706, 0.16037 + 0xbfef97f924c9099b, 0x3fc45576b1293e5a, // -0.9873, 0.15886 + 0xbfef99f5c0abd496, 0x3fc423d4920e4166, // -0.98754, 0.15734 + 0xbfef9bed7cfbde29, 0x3fc3f22f57db4893, // -0.98778, 0.15583 + 0xbfef9de0596b77a3, 0x3fc3c0870a383ff6, // -0.98802, 0.15431 + 0xbfef9fce55adb2c8, 0x3fc38edbb0cd8d14, // -0.98826, 0.1528 + 0xbfefa1b7717661d5, 0x3fc35d2d53440db2, // -0.98849, 0.15128 + 0xbfefa39bac7a1791, 0x3fc32b7bf94516a7, // -0.98872, 0.14976 + 0xbfefa57b066e2754, 0x3fc2f9c7aa7a72af, // -0.98895, 0.14825 + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673 + 0xbfefa92b1600657c, 0x3fc296564d2b953e, // -0.9894, 0.14521 + 0xbfefaafbcb0cfddc, 0x3fc264994dfd340a, // -0.98962, 0.1437 + 0xbfefacc79de6c44f, 0x3fc232d978aed413, // -0.98984, 0.14218 + 0xbfefae8e8e46cfbb, 0x3fc20116d4ec7bce, // -0.99006, 0.14066 + 0xbfefb0509be6f7db, 0x3fc1cf516a62a077, // -0.99027, 0.13914 + 0xbfefb20dc681d54d, 0x3fc19d8940be24e7, // -0.99049, 0.13762 + 0xbfefb3c60dd2c199, 0x3fc16bbe5fac5865, // -0.9907, 0.1361 + 0xbfefb5797195d741, 0x3fc139f0cedaf576, // -0.9909, 0.13458 + 0xbfefb727f187f1c7, 0x3fc1082095f820b0, // -0.99111, 0.13306 + 0xbfefb8d18d66adb7, 0x3fc0d64dbcb26786, // -0.99131, 0.13154 + 0xbfefba7644f068b5, 0x3fc0a4784ab8bf1d, // -0.99151, 0.13002 + 0xbfefbc1617e44186, 0x3fc072a047ba831d, // -0.99171, 0.1285 + 0xbfefbdb106021816, 0x3fc040c5bb67747e, // -0.99191, 0.12698 + 0xbfefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // -0.9921, 0.12545 + 0xbfefc0d832bf043a, 0x3fbfba124b07ad85, // -0.99229, 0.12393 + 0xbfefc26470e19fd3, 0x3fbf564e56a9730e, // -0.99248, 0.12241 + 0xbfefc3ebc935454c, 0x3fbef2858d27561b, // -0.99267, 0.12089 + 0xbfefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // -0.99285, 0.11937 + 0xbfefc6ebc77f0887, 0x3fbe2ae5b8457f77, // -0.99303, 0.11784 + 0xbfefc8646cfeb721, 0x3fbdc70ecbae9fc8, // -0.99321, 0.11632 + 0xbfefc9d82bc2915e, 0x3fbd633347858ce4, // -0.99339, 0.11479 + 0xbfefcb4703914354, 0x3fbcff533b307dc1, // -0.99356, 0.11327 + 0xbfefccb0f4323aa3, 0x3fbc9b6eb6165c42, // -0.99374, 0.11175 + 0xbfefce15fd6da67b, 0x3fbc3785c79ec2d5, // -0.99391, 0.11022 + 0xbfefcf761f0c77a3, 0x3fbbd3987f31fa0e, // -0.99407, 0.1087 + 0xbfefd0d158d86087, 0x3fbb6fa6ec38f64c, // -0.99424, 0.10717 + 0xbfefd227aa9bd53b, 0x3fbb0bb11e1d5559, // -0.9944, 0.10565 + 0xbfefd37914220b84, 0x3fbaa7b724495c04, // -0.99456, 0.10412 + 0xbfefd4c59536fae4, 0x3fba43b90e27f3c4, // -0.99472, 0.1026 + 0xbfefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // -0.99488, 0.10107 + 0xbfefd74fdd40abbf, 0x3fb97bb0caaba56f, // -0.99503, 0.099544 + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017 + 0xbfefd9c68127c78c, 0x3fb8b398cf0c38e0, // -0.99533, 0.09649 + 0xbfefdafa7514538c, 0x3fb84f8712c130a0, // -0.99548, 0.094963 + 0xbfefdc297f674ba9, 0x3fb7eb7196b72ee4, // -0.99563, 0.093436 + 0xbfefdd539ff1f456, 0x3fb787586a5d5b21, // -0.99577, 0.091909 + 0xbfefde78d68653fd, 0x3fb7233b9d236e71, // -0.99591, 0.090381 + 0xbfefdf9922f73307, 0x3fb6bf1b3e79b129, // -0.99604, 0.088854 + 0xbfefe0b485181be3, 0x3fb65af75dd0f87b, // -0.99618, 0.087326 + 0xbfefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // -0.99631, 0.085797 + 0xbfefe2dc89bbff08, 0x3fb592a554489bc8, // -0.99644, 0.084269 + 0xbfefe3e92be9d886, 0x3fb52e774a4d4d0a, // -0.99657, 0.08274 + 0xbfefe4f0e31d7a4a, 0x3fb4ca45fc1ba8b6, // -0.9967, 0.081211 + 0xbfefe5f3af2e3940, 0x3fb4661179272096, // -0.99682, 0.079682 + 0xbfefe6f18ff42c84, 0x3fb401d9d0e3a507, // -0.99694, 0.078153 + 0xbfefe7ea85482d60, 0x3fb39d9f12c5a299, // -0.99706, 0.076624 + 0xbfefe8de8f03d75c, 0x3fb339614e41ffa5, // -0.99718, 0.075094 + 0xbfefe9cdad01883a, 0x3fb2d52092ce19f6, // -0.99729, 0.073565 + 0xbfefeab7df1c6005, 0x3fb270dcefdfc45b, // -0.9974, 0.072035 + 0xbfefeb9d2530410f, 0x3fb20c9674ed444c, // -0.99751, 0.070505 + 0xbfefec7d7f19cffc, 0x3fb1a84d316d4f8a, // -0.99762, 0.068974 + 0xbfefed58ecb673c4, 0x3fb1440134d709b2, // -0.99772, 0.067444 + 0xbfefee2f6de455ba, 0x3fb0dfb28ea201e6, // -0.99783, 0.065913 + 0xbfefef0102826191, 0x3fb07b614e463064, // -0.99793, 0.064383 + 0xbfefefcdaa704562, 0x3fb0170d833bf421, // -0.99802, 0.062852 + 0xbfeff095658e71ad, 0x3faf656e79f820e0, // -0.99812, 0.061321 + 0xbfeff15833be1965, 0x3fae9cbd15ff5527, // -0.99821, 0.05979 + 0xbfeff21614e131ed, 0x3fadd406f9808ec8, // -0.9983, 0.058258 + 0xbfeff2cf08da7321, 0x3fad0b4c436f91d0, // -0.99839, 0.056727 + 0xbfeff3830f8d575c, 0x3fac428d12c0d7e3, // -0.99848, 0.055195 + 0xbfeff43228de1b77, 0x3fab79c986698b78, // -0.99856, 0.053664 + 0xbfeff4dc54b1bed3, 0x3faab101bd5f8317, // -0.99864, 0.052132 + 0xbfeff58192ee0358, 0x3fa9e835d6993c87, // -0.99872, 0.0506 + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068 + 0xbfeff6bd463b444d, 0x3fa856922bb513c1, // -0.99887, 0.047535 + 0xbfeff753bb1b9164, 0x3fa78dbaa5874685, // -0.99894, 0.046003 + 0xbfeff7e5420320f9, 0x3fa6c4df7d7d5b84, // -0.99901, 0.044471 + 0xbfeff871dadb81df, 0x3fa5fc00d290cd43, // -0.99908, 0.042938 + 0xbfeff8f9858f058b, 0x3fa5331ec3bba0eb, // -0.99914, 0.041406 + 0xbfeff97c4208c014, 0x3fa46a396ff86179, // -0.9992, 0.039873 + 0xbfeff9fa10348837, 0x3fa3a150f6421afc, // -0.99926, 0.03834 + 0xbfeffa72effef75d, 0x3fa2d865759455cd, // -0.99932, 0.036807 + 0xbfeffae6e1556998, 0x3fa20f770ceb11c6, // -0.99938, 0.035274 + 0xbfeffb55e425fdae, 0x3fa14685db42c17e, // -0.99943, 0.033741 + 0xbfeffbbff85f9515, 0x3fa07d91ff984580, // -0.99948, 0.032208 + 0xbfeffc251df1d3f8, 0x3f9f693731d1cf01, // -0.99953, 0.030675 + 0xbfeffc8554cd213a, 0x3f9dd7458c64ab39, // -0.99958, 0.029142 + 0xbfeffce09ce2a679, 0x3f9c454f4ce53b1c, // -0.99962, 0.027608 + 0xbfeffd36f624500c, 0x3f9ab354b1504fca, // -0.99966, 0.026075 + 0xbfeffd886084cd0d, 0x3f992155f7a3667e, // -0.9997, 0.024541 + 0xbfeffdd4dbf78f52, 0x3f978f535ddc9f03, // -0.99974, 0.023008 + 0xbfeffe1c6870cb77, 0x3f95fd4d21fab226, // -0.99977, 0.021474 + 0xbfeffe5f05e578db, 0x3f946b4381fce81c, // -0.9998, 0.01994 + 0xbfeffe9cb44b51a1, 0x3f92d936bbe30efd, // -0.99983, 0.018407 + 0xbfeffed57398d2b7, 0x3f9147270dad7132, // -0.99986, 0.016873 + 0xbfefff0943c53bd1, 0x3f8f6a296ab997ca, // -0.99988, 0.015339 + 0xbfefff3824c88f6f, 0x3f8c45ffe1e48ad9, // -0.9999, 0.013805 + 0xbfefff62169b92db, 0x3f8921d1fcdec784, // -0.99992, 0.012272 + 0xbfefff871937ce2f, 0x3f85fda037ac05e0, // -0.99994, 0.010738 + 0xbfefffa72c978c4f, 0x3f82d96b0e509703, // -0.99996, 0.0092038 + 0xbfefffc250b5daef, 0x3f7f6a65f9a2a3c5, // -0.99997, 0.0076698 + 0xbfefffd8858e8a92, 0x3f7921f0fe670071, // -0.99998, 0.0061359 + 0xbfefffe9cb1e2e8d, 0x3f72d97822f996bc, // -0.99999, 0.0046019 + 0xbfeffff621621d02, 0x3f6921f8becca4ba, // -1, 0.003068 + 0xbfeffffd88586ee6, 0x3f5921faaee6472d, // -1, 0.001534 + 0xbff0000000000000, 0x0000000000000000, // -1, 0 + 0xbfeffffd88586ee6, 0xbf5921faaee6472d, // -1, -0.001534 + 0xbfeffff621621d02, 0xbf6921f8becca4ba, // -1, -0.003068 + 0xbfefffe9cb1e2e8d, 0xbf72d97822f996bc, // -0.99999,-0.0046019 + 0xbfefffd8858e8a92, 0xbf7921f0fe670071, // -0.99998,-0.0061359 + 0xbfefffc250b5daef, 0xbf7f6a65f9a2a3c5, // -0.99997,-0.0076698 + 0xbfefffa72c978c4f, 0xbf82d96b0e509703, // -0.99996,-0.0092038 + 0xbfefff871937ce2f, 0xbf85fda037ac05e0, // -0.99994, -0.010738 + 0xbfefff62169b92db, 0xbf8921d1fcdec784, // -0.99992, -0.012272 + 0xbfefff3824c88f6f, 0xbf8c45ffe1e48ad9, // -0.9999, -0.013805 + 0xbfefff0943c53bd1, 0xbf8f6a296ab997ca, // -0.99988, -0.015339 + 0xbfeffed57398d2b7, 0xbf9147270dad7132, // -0.99986, -0.016873 + 0xbfeffe9cb44b51a1, 0xbf92d936bbe30efd, // -0.99983, -0.018407 + 0xbfeffe5f05e578db, 0xbf946b4381fce81c, // -0.9998, -0.01994 + 0xbfeffe1c6870cb77, 0xbf95fd4d21fab226, // -0.99977, -0.021474 + 0xbfeffdd4dbf78f52, 0xbf978f535ddc9f03, // -0.99974, -0.023008 + 0xbfeffd886084cd0d, 0xbf992155f7a3667e, // -0.9997, -0.024541 + 0xbfeffd36f624500c, 0xbf9ab354b1504fca, // -0.99966, -0.026075 + 0xbfeffce09ce2a679, 0xbf9c454f4ce53b1c, // -0.99962, -0.027608 + 0xbfeffc8554cd213a, 0xbf9dd7458c64ab39, // -0.99958, -0.029142 + 0xbfeffc251df1d3f8, 0xbf9f693731d1cf01, // -0.99953, -0.030675 + 0xbfeffbbff85f9515, 0xbfa07d91ff984580, // -0.99948, -0.032208 + 0xbfeffb55e425fdae, 0xbfa14685db42c17e, // -0.99943, -0.033741 + 0xbfeffae6e1556998, 0xbfa20f770ceb11c6, // -0.99938, -0.035274 + 0xbfeffa72effef75d, 0xbfa2d865759455cd, // -0.99932, -0.036807 + 0xbfeff9fa10348837, 0xbfa3a150f6421afc, // -0.99926, -0.03834 + 0xbfeff97c4208c014, 0xbfa46a396ff86179, // -0.9992, -0.039873 + 0xbfeff8f9858f058b, 0xbfa5331ec3bba0eb, // -0.99914, -0.041406 + 0xbfeff871dadb81df, 0xbfa5fc00d290cd43, // -0.99908, -0.042938 + 0xbfeff7e5420320f9, 0xbfa6c4df7d7d5b84, // -0.99901, -0.044471 + 0xbfeff753bb1b9164, 0xbfa78dbaa5874685, // -0.99894, -0.046003 + 0xbfeff6bd463b444d, 0xbfa856922bb513c1, // -0.99887, -0.047535 + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988, -0.049068 + 0xbfeff58192ee0358, 0xbfa9e835d6993c87, // -0.99872, -0.0506 + 0xbfeff4dc54b1bed3, 0xbfaab101bd5f8317, // -0.99864, -0.052132 + 0xbfeff43228de1b77, 0xbfab79c986698b78, // -0.99856, -0.053664 + 0xbfeff3830f8d575c, 0xbfac428d12c0d7e3, // -0.99848, -0.055195 + 0xbfeff2cf08da7321, 0xbfad0b4c436f91d0, // -0.99839, -0.056727 + 0xbfeff21614e131ed, 0xbfadd406f9808ec8, // -0.9983, -0.058258 + 0xbfeff15833be1965, 0xbfae9cbd15ff5527, // -0.99821, -0.05979 + 0xbfeff095658e71ad, 0xbfaf656e79f820e0, // -0.99812, -0.061321 + 0xbfefefcdaa704562, 0xbfb0170d833bf421, // -0.99802, -0.062852 + 0xbfefef0102826191, 0xbfb07b614e463064, // -0.99793, -0.064383 + 0xbfefee2f6de455ba, 0xbfb0dfb28ea201e6, // -0.99783, -0.065913 + 0xbfefed58ecb673c4, 0xbfb1440134d709b2, // -0.99772, -0.067444 + 0xbfefec7d7f19cffc, 0xbfb1a84d316d4f8a, // -0.99762, -0.068974 + 0xbfefeb9d2530410f, 0xbfb20c9674ed444c, // -0.99751, -0.070505 + 0xbfefeab7df1c6005, 0xbfb270dcefdfc45b, // -0.9974, -0.072035 + 0xbfefe9cdad01883a, 0xbfb2d52092ce19f6, // -0.99729, -0.073565 + 0xbfefe8de8f03d75c, 0xbfb339614e41ffa5, // -0.99718, -0.075094 + 0xbfefe7ea85482d60, 0xbfb39d9f12c5a299, // -0.99706, -0.076624 + 0xbfefe6f18ff42c84, 0xbfb401d9d0e3a507, // -0.99694, -0.078153 + 0xbfefe5f3af2e3940, 0xbfb4661179272096, // -0.99682, -0.079682 + 0xbfefe4f0e31d7a4a, 0xbfb4ca45fc1ba8b6, // -0.9967, -0.081211 + 0xbfefe3e92be9d886, 0xbfb52e774a4d4d0a, // -0.99657, -0.08274 + 0xbfefe2dc89bbff08, 0xbfb592a554489bc8, // -0.99644, -0.084269 + 0xbfefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // -0.99631, -0.085797 + 0xbfefe0b485181be3, 0xbfb65af75dd0f87b, // -0.99618, -0.087326 + 0xbfefdf9922f73307, 0xbfb6bf1b3e79b129, // -0.99604, -0.088854 + 0xbfefde78d68653fd, 0xbfb7233b9d236e71, // -0.99591, -0.090381 + 0xbfefdd539ff1f456, 0xbfb787586a5d5b21, // -0.99577, -0.091909 + 0xbfefdc297f674ba9, 0xbfb7eb7196b72ee4, // -0.99563, -0.093436 + 0xbfefdafa7514538c, 0xbfb84f8712c130a0, // -0.99548, -0.094963 + 0xbfefd9c68127c78c, 0xbfb8b398cf0c38e0, // -0.99533, -0.09649 + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518, -0.098017 + 0xbfefd74fdd40abbf, 0xbfb97bb0caaba56f, // -0.99503, -0.099544 + 0xbfefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // -0.99488, -0.10107 + 0xbfefd4c59536fae4, 0xbfba43b90e27f3c4, // -0.99472, -0.1026 + 0xbfefd37914220b84, 0xbfbaa7b724495c04, // -0.99456, -0.10412 + 0xbfefd227aa9bd53b, 0xbfbb0bb11e1d5559, // -0.9944, -0.10565 + 0xbfefd0d158d86087, 0xbfbb6fa6ec38f64c, // -0.99424, -0.10717 + 0xbfefcf761f0c77a3, 0xbfbbd3987f31fa0e, // -0.99407, -0.1087 + 0xbfefce15fd6da67b, 0xbfbc3785c79ec2d5, // -0.99391, -0.11022 + 0xbfefccb0f4323aa3, 0xbfbc9b6eb6165c42, // -0.99374, -0.11175 + 0xbfefcb4703914354, 0xbfbcff533b307dc1, // -0.99356, -0.11327 + 0xbfefc9d82bc2915e, 0xbfbd633347858ce4, // -0.99339, -0.11479 + 0xbfefc8646cfeb721, 0xbfbdc70ecbae9fc8, // -0.99321, -0.11632 + 0xbfefc6ebc77f0887, 0xbfbe2ae5b8457f77, // -0.99303, -0.11784 + 0xbfefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // -0.99285, -0.11937 + 0xbfefc3ebc935454c, 0xbfbef2858d27561b, // -0.99267, -0.12089 + 0xbfefc26470e19fd3, 0xbfbf564e56a9730e, // -0.99248, -0.12241 + 0xbfefc0d832bf043a, 0xbfbfba124b07ad85, // -0.99229, -0.12393 + 0xbfefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // -0.9921, -0.12545 + 0xbfefbdb106021816, 0xbfc040c5bb67747e, // -0.99191, -0.12698 + 0xbfefbc1617e44186, 0xbfc072a047ba831d, // -0.99171, -0.1285 + 0xbfefba7644f068b5, 0xbfc0a4784ab8bf1d, // -0.99151, -0.13002 + 0xbfefb8d18d66adb7, 0xbfc0d64dbcb26786, // -0.99131, -0.13154 + 0xbfefb727f187f1c7, 0xbfc1082095f820b0, // -0.99111, -0.13306 + 0xbfefb5797195d741, 0xbfc139f0cedaf576, // -0.9909, -0.13458 + 0xbfefb3c60dd2c199, 0xbfc16bbe5fac5865, // -0.9907, -0.1361 + 0xbfefb20dc681d54d, 0xbfc19d8940be24e7, // -0.99049, -0.13762 + 0xbfefb0509be6f7db, 0xbfc1cf516a62a077, // -0.99027, -0.13914 + 0xbfefae8e8e46cfbb, 0xbfc20116d4ec7bce, // -0.99006, -0.14066 + 0xbfefacc79de6c44f, 0xbfc232d978aed413, // -0.98984, -0.14218 + 0xbfefaafbcb0cfddc, 0xbfc264994dfd340a, // -0.98962, -0.1437 + 0xbfefa92b1600657c, 0xbfc296564d2b953e, // -0.9894, -0.14521 + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673 + 0xbfefa57b066e2754, 0xbfc2f9c7aa7a72af, // -0.98895, -0.14825 + 0xbfefa39bac7a1791, 0xbfc32b7bf94516a7, // -0.98872, -0.14976 + 0xbfefa1b7717661d5, 0xbfc35d2d53440db2, // -0.98849, -0.15128 + 0xbfef9fce55adb2c8, 0xbfc38edbb0cd8d14, // -0.98826, -0.1528 + 0xbfef9de0596b77a3, 0xbfc3c0870a383ff6, // -0.98802, -0.15431 + 0xbfef9bed7cfbde29, 0xbfc3f22f57db4893, // -0.98778, -0.15583 + 0xbfef99f5c0abd496, 0xbfc423d4920e4166, // -0.98754, -0.15734 + 0xbfef97f924c9099b, 0xbfc45576b1293e5a, // -0.9873, -0.15886 + 0xbfef95f7a9a1ec47, 0xbfc48715ad84cdf5, // -0.98706, -0.16037 + 0xbfef93f14f85ac08, 0xbfc4b8b17f79fa88, // -0.98681, -0.16189 + 0xbfef91e616c43891, 0xbfc4ea4a1f624b61, // -0.98656, -0.1634 + 0xbfef8fd5ffae41db, 0xbfc51bdf8597c5f2, // -0.98631, -0.16491 + 0xbfef8dc10a95380d, 0xbfc54d71aa74ef02, // -0.98605, -0.16643 + 0xbfef8ba737cb4b78, 0xbfc57f008654cbde, // -0.9858, -0.16794 + 0xbfef898887a36c84, 0xbfc5b08c1192e381, // -0.98554, -0.16945 + 0xbfef8764fa714ba9, 0xbfc5e214448b3fc6, // -0.98528, -0.17096 + 0xbfef853c9089595e, 0xbfc61399179a6e94, // -0.98501, -0.17247 + 0xbfef830f4a40c60c, 0xbfc6451a831d830d, // -0.98475, -0.17398 + 0xbfef80dd27ed8204, 0xbfc676987f7216b8, // -0.98448, -0.17549 + 0xbfef7ea629e63d6e, 0xbfc6a81304f64ab2, // -0.98421, -0.177 + 0xbfef7c6a50826840, 0xbfc6d98a0c08c8da, // -0.98394, -0.17851 + 0xbfef7a299c1a322a, 0xbfc70afd8d08c4ff, // -0.98366, -0.18002 + 0xbfef77e40d068a90, 0xbfc73c6d8055fe0a, // -0.98339, -0.18153 + 0xbfef7599a3a12077, 0xbfc76dd9de50bf31, // -0.98311, -0.18304 + 0xbfef734a60446279, 0xbfc79f429f59e11d, // -0.98282, -0.18455 + 0xbfef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // -0.98254, -0.18606 + 0xbfef6e9d4d1262ca, 0xbfc802092c1d744b, // -0.98225, -0.18756 + 0xbfef6c3f7df5bbb7, 0xbfc83366e89c64c5, // -0.98196, -0.18907 + 0xbfef69dcd652f5de, 0xbfc864c0e9b2b6cf, // -0.98167, -0.19057 + 0xbfef677556883cee, 0xbfc8961727c41804, // -0.98138, -0.19208 + 0xbfef6508fef47bd5, 0xbfc8c7699b34ca7e, // -0.98108, -0.19359 + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509 + 0xbfef6021c9f148c2, 0xbfc92a0303c8194f, // -0.98048, -0.19659 + 0xbfef5da6ed43685d, 0xbfc95b49e9b62af9, // -0.98018, -0.1981 + 0xbfef5b273a4fa2d9, 0xbfc98c8ce69a7aec, // -0.97988, -0.1996 + 0xbfef58a2b1789e84, 0xbfc9bdcbf2dc4366, // -0.97957, -0.2011 + 0xbfef56195321c090, 0xbfc9ef0706e35a35, // -0.97926, -0.20261 + 0xbfef538b1faf2d07, 0xbfca203e1b1831da, // -0.97895, -0.20411 + 0xbfef50f81785c6b9, 0xbfca517127e3dabc, // -0.97863, -0.20561 + 0xbfef4e603b0b2f2d, 0xbfca82a025b00451, // -0.97832, -0.20711 + 0xbfef4bc38aa5c694, 0xbfcab3cb0ce6fe44, // -0.978, -0.20861 + 0xbfef492206bcabb4, 0xbfcae4f1d5f3b9ab, // -0.97768, -0.21011 + 0xbfef467bafb7bbe0, 0xbfcb16147941ca2a, // -0.97735, -0.21161 + 0xbfef43d085ff92dd, 0xbfcb4732ef3d6722, // -0.97703, -0.21311 + 0xbfef412089fd8adc, 0xbfcb784d30536cda, // -0.9767, -0.21461 + 0xbfef3e6bbc1bbc65, 0xbfcba96334f15dad, // -0.97637, -0.21611 + 0xbfef3bb21cc4fe47, 0xbfcbda74f5856330, // -0.97604, -0.2176 + 0xbfef38f3ac64e589, 0xbfcc0b826a7e4f63, // -0.9757, -0.2191 + 0xbfef36306b67c556, 0xbfcc3c8b8c4b9dd7, // -0.97536, -0.2206 + 0xbfef33685a3aaef0, 0xbfcc6d90535d74dc, // -0.97503, -0.22209 + 0xbfef309b794b719f, 0xbfcc9e90b824a6a9, // -0.97468, -0.22359 + 0xbfef2dc9c9089a9d, 0xbfcccf8cb312b286, // -0.97434, -0.22508 + 0xbfef2af349e17507, 0xbfcd00843c99c5f9, // -0.97399, -0.22658 + 0xbfef2817fc4609ce, 0xbfcd31774d2cbdee, // -0.97364, -0.22807 + 0xbfef2537e0a71f9f, 0xbfcd6265dd3f27e3, // -0.97329, -0.22957 + 0xbfef2252f7763ada, 0xbfcd934fe5454311, // -0.97294, -0.23106 + 0xbfef1f6941259d7a, 0xbfcdc4355db40195, // -0.97258, -0.23255 + 0xbfef1c7abe284708, 0xbfcdf5163f01099a, // -0.97223, -0.23404 + 0xbfef19876ef1f486, 0xbfce25f281a2b684, // -0.97187, -0.23553 + 0xbfef168f53f7205d, 0xbfce56ca1e101a1b, // -0.9715, -0.23702 + 0xbfef13926dad024e, 0xbfce879d0cc0fdaf, // -0.97114, -0.23851 + 0xbfef1090bc898f5f, 0xbfceb86b462de348, // -0.97077, -0.24 + 0xbfef0d8a410379c5, 0xbfcee934c2d006c7, // -0.9704, -0.24149 + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298 + 0xbfef076eecade0fa, 0xbfcf4ab9679c9f5c, // -0.96966, -0.24447 + 0xbfef045a14cf738c, 0xbfcf7b7480bd3801, // -0.96928, -0.24596 + 0xbfef014074708ed3, 0xbfcfac2abeff57ff, // -0.9689, -0.24744 + 0xbfeefe220c0b95ec, 0xbfcfdcdc1adfedf8, // -0.96852, -0.24893 + 0xbfeefafedc1ba8b7, 0xbfd006c4466e54af, // -0.96814, -0.25041 + 0xbfeef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // -0.96775, -0.2519 + 0xbfeef4aa278b2032, 0xbfd037694a928cac, // -0.96737, -0.25338 + 0xbfeef178a3e473c2, 0xbfd04fb80e37fdae, // -0.96698, -0.25487 + 0xbfeeee425aa6b09a, 0xbfd068044deab002, // -0.96658, -0.25635 + 0xbfeeeb074c50a544, 0xbfd0804e05eb661e, // -0.96619, -0.25783 + 0xbfeee7c77961dc9e, 0xbfd09895327b465e, // -0.96579, -0.25931 + 0xbfeee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // -0.96539, -0.26079 + 0xbfeee13987bbebdc, 0xbfd0c91bda4f158d, // -0.96499, -0.26227 + 0xbfeeddeb6a078651, 0xbfd0e15b4e1749cd, // -0.96459, -0.26375 + 0xbfeeda9889bfe86a, 0xbfd0f998277733f7, // -0.96418, -0.26523 + 0xbfeed740e7684963, 0xbfd111d262b1f677, // -0.96378, -0.26671 + 0xbfeed3e483849c51, 0xbfd12a09fc0b1b12, // -0.96337, -0.26819 + 0xbfeed0835e999009, 0xbfd1423eefc69378, // -0.96295, -0.26967 + 0xbfeecd1d792c8f10, 0xbfd15a713a28b9d9, // -0.96254, -0.27115 + 0xbfeec9b2d3c3bf84, 0xbfd172a0d7765177, // -0.96212, -0.27262 + 0xbfeec6436ee60309, 0xbfd18acdc3f4873a, // -0.9617, -0.2741 + 0xbfeec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // -0.96128, -0.27557 + 0xbfeebf5668eaf2ef, 0xbfd1bb1f7b999480, // -0.96086, -0.27705 + 0xbfeebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // -0.96043, -0.27852 + 0xbfeeb8566b810f2a, 0xbfd1eb6643499fbb, // -0.96, -0.27999 + 0xbfeeb4cf515b8811, 0xbfd2038583d727bd, // -0.95957, -0.28146 + 0xbfeeb1437af9bb34, 0xbfd21ba1fd3d2623, // -0.95914, -0.28294 + 0xbfeeadb2e8e7a88e, 0xbfd233bbabc3bb72, // -0.9587, -0.28441 + 0xbfeeaa1d9bb20af3, 0xbfd24bd28bb37672, // -0.95827, -0.28588 + 0xbfeea68393e65800, 0xbfd263e6995554ba, // -0.95783, -0.28735 + 0xbfeea2e4d212c000, 0xbfd27bf7d0f2c346, // -0.95738, -0.28882 + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028 + 0xbfee9b99229046f8, 0xbfd2ac11af483572, // -0.95649, -0.29175 + 0xbfee97ec36016b30, 0xbfd2c41a4e954520, // -0.95605, -0.29322 + 0xbfee943a91aab4b4, 0xbfd2dc200907fe51, // -0.95559, -0.29469 + 0xbfee9084361df7f3, 0xbfd2f422daec0386, // -0.95514, -0.29615 + 0xbfee8cc923edc388, 0xbfd30c22c08d6a13, // -0.95469, -0.29762 + 0xbfee89095bad6025, 0xbfd3241fb638baaf, // -0.95423, -0.29908 + 0xbfee8544ddf0d075, 0xbfd33c19b83af207, // -0.95377, -0.30054 + 0xbfee817bab4cd10d, 0xbfd35410c2e18152, // -0.95331, -0.30201 + 0xbfee7dadc456d850, 0xbfd36c04d27a4edf, // -0.95284, -0.30347 + 0xbfee79db29a5165a, 0xbfd383f5e353b6aa, // -0.95238, -0.30493 + 0xbfee7603dbce74e9, 0xbfd39be3f1bc8aef, // -0.95191, -0.30639 + 0xbfee7227db6a9744, 0xbfd3b3cefa0414b7, // -0.95144, -0.30785 + 0xbfee6e472911da27, 0xbfd3cbb6f87a146e, // -0.95096, -0.30931 + 0xbfee6a61c55d53a7, 0xbfd3e39be96ec271, // -0.95049, -0.31077 + 0xbfee6677b0e6d31e, 0xbfd3fb7dc932cfa4, // -0.95001, -0.31222 + 0xbfee6288ec48e112, 0xbfd4135c94176602, // -0.94953, -0.31368 + 0xbfee5e95781ebf1c, 0xbfd42b38466e2928, // -0.94905, -0.31514 + 0xbfee5a9d550467d3, 0xbfd44310dc8936f0, // -0.94856, -0.31659 + 0xbfee56a083968eb1, 0xbfd45ae652bb2800, // -0.94807, -0.31805 + 0xbfee529f04729ffc, 0xbfd472b8a5571054, // -0.94759, -0.3195 + 0xbfee4e98d836c0af, 0xbfd48a87d0b07fd7, // -0.94709, -0.32096 + 0xbfee4a8dff81ce5e, 0xbfd4a253d11b82f3, // -0.9466, -0.32241 + 0xbfee467e7af35f23, 0xbfd4ba1ca2eca31c, // -0.94611, -0.32386 + 0xbfee426a4b2bc17e, 0xbfd4d1e24278e76a, // -0.94561, -0.32531 + 0xbfee3e5170cbfc46, 0xbfd4e9a4ac15d520, // -0.94511, -0.32676 + 0xbfee3a33ec75ce85, 0xbfd50163dc197047, // -0.9446, -0.32821 + 0xbfee3611becbaf69, 0xbfd5191fceda3c35, // -0.9441, -0.32966 + 0xbfee31eae870ce25, 0xbfd530d880af3c24, // -0.94359, -0.33111 + 0xbfee2dbf6a0911d9, 0xbfd5488dedeff3be, // -0.94308, -0.33255 + 0xbfee298f4439197a, 0xbfd5604012f467b4, // -0.94257, -0.334 + 0xbfee255a77a63bb8, 0xbfd577eeec151e47, // -0.94206, -0.33545 + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689 + 0xbfee1ce2ecd0c0d8, 0xbfd5a742ac0ff78d, // -0.94103, -0.33833 + 0xbfee18a02fdc66d9, 0xbfd5bee78b9db3b6, // -0.94051, -0.33978 + 0xbfee1458cec1ad83, 0xbfd5d68910aee686, // -0.93998, -0.34122 + 0xbfee100cca2980ac, 0xbfd5ee27379ea693, // -0.93946, -0.34266 + 0xbfee0bbc22bd8349, 0xbfd605c1fcc88f63, // -0.93893, -0.3441 + 0xbfee0766d9280f54, 0xbfd61d595c88c203, // -0.9384, -0.34554 + 0xbfee030cee1435b8, 0xbfd634ed533be58e, // -0.93787, -0.34698 + 0xbfedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // -0.93734, -0.34842 + 0xbfedfa4b3621271d, 0xbfd6640af6f03d9e, // -0.9368, -0.34986 + 0xbfedf5e36a9ba59c, 0xbfd67b949cad63ca, // -0.93627, -0.35129 + 0xbfedf177004b2534, 0xbfd6931acad55f51, // -0.93573, -0.35273 + 0xbfeded05f7de47da, 0xbfd6aa9d7dc77e16, // -0.93518, -0.35416 + 0xbfede890520465ce, 0xbfd6c21cb1e39771, // -0.93464, -0.3556 + 0xbfede4160f6d8d81, 0xbfd6d998638a0cb5, // -0.93409, -0.35703 + 0xbfeddf9730ca837b, 0xbfd6f1108f1bc9c5, // -0.93354, -0.35846 + 0xbfeddb13b6ccc23d, 0xbfd7088530fa459e, // -0.93299, -0.3599 + 0xbfedd68ba2267a25, 0xbfd71ff6458782ec, // -0.93244, -0.36133 + 0xbfedd1fef38a915a, 0xbfd73763c9261092, // -0.93188, -0.36276 + 0xbfedcd6dabaca3a5, 0xbfd74ecdb8390a3e, // -0.93133, -0.36418 + 0xbfedc8d7cb410260, 0xbfd766340f2418f6, // -0.93077, -0.36561 + 0xbfedc43d52fcb453, 0xbfd77d96ca4b73a6, // -0.93021, -0.36704 + 0xbfedbf9e4395759a, 0xbfd794f5e613dfae, // -0.92964, -0.36847 + 0xbfedbafa9dc1b78d, 0xbfd7ac515ee2b172, // -0.92907, -0.36989 + 0xbfedb6526238a09b, 0xbfd7c3a9311dcce7, // -0.92851, -0.37132 + 0xbfedb1a591b20c38, 0xbfd7dafd592ba621, // -0.92794, -0.37274 + 0xbfedacf42ce68ab9, 0xbfd7f24dd37341e3, // -0.92736, -0.37416 + 0xbfeda83e348f613b, 0xbfd8099a9c5c362d, // -0.92679, -0.37559 + 0xbfeda383a9668988, 0xbfd820e3b04eaac4, // -0.92621, -0.37701 + 0xbfed9ec48c26b1f3, 0xbfd838290bb359c8, // -0.92563, -0.37843 + 0xbfed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // -0.92505, -0.37985 + 0xbfed95389e50429b, 0xbfd866a88a792ea0, // -0.92447, -0.38127 + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268 + 0xbfed8b9a70ef9cb4, 0xbfd89518fbff098e, // -0.92329, -0.3841 + 0xbfed86c48445a450, 0xbfd8ac4b86d5ed44, // -0.9227, -0.38552 + 0xbfed81ea09f38b63, 0xbfd8c37a439f884f, // -0.92211, -0.38693 + 0xbfed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // -0.92151, -0.38835 + 0xbfed78276f5617c6, 0xbfd8f1cc44bea329, // -0.92092, -0.38976 + 0xbfed733f508c0dff, 0xbfd908ef81ef7bd1, // -0.92032, -0.39117 + 0xbfed6e52a71c8547, 0xbfd9200ee2c9be97, // -0.91972, -0.39258 + 0xbfed696173c9e68b, 0xbfd9372a63bc93d7, // -0.91911, -0.39399 + 0xbfed646bb7574de5, 0xbfd94e420137bce3, // -0.91851, -0.3954 + 0xbfed5f7172888a7f, 0xbfd96555b7ab948f, // -0.9179, -0.39681 + 0xbfed5a72a6221e73, 0xbfd97c6583890fc2, // -0.91729, -0.39822 + 0xbfed556f52e93eb1, 0xbfd993716141bdfe, // -0.91668, -0.39962 + 0xbfed506779a3d2d9, 0xbfd9aa794d47c9ee, // -0.91606, -0.40103 + 0xbfed4b5b1b187524, 0xbfd9c17d440df9f2, // -0.91545, -0.40243 + 0xbfed464a380e7242, 0xbfd9d87d4207b0ab, // -0.91483, -0.40384 + 0xbfed4134d14dc93a, 0xbfd9ef7943a8ed8a, // -0.91421, -0.40524 + 0xbfed3c1ae79f2b4e, 0xbfda067145664d57, // -0.91359, -0.40664 + 0xbfed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // -0.91296, -0.40804 + 0xbfed31d98e9e503a, 0xbfda34553b0afee5, // -0.91234, -0.40944 + 0xbfed2cb220e0ef9f, 0xbfda4b4127dea1e4, // -0.91171, -0.41084 + 0xbfed2786335f52fc, 0xbfda622906a70b63, // -0.91107, -0.41224 + 0xbfed2255c6e5a4e1, 0xbfda790cd3dbf31a, // -0.91044, -0.41364 + 0xbfed1d20dc40c15c, 0xbfda8fec8bf5b166, // -0.90981, -0.41503 + 0xbfed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // -0.90917, -0.41643 + 0xbfed12a98fac410c, 0xbfdabd9faebc3980, // -0.90853, -0.41782 + 0xbfed0d672f59d2b9, 0xbfdad473125cdc08, // -0.90789, -0.41922 + 0xbfed082054168bac, 0xbfdaeb4252ca07ab, // -0.90724, -0.42061 + 0xbfed02d4feb2bd92, 0xbfdb020d6c7f4009, // -0.9066, -0.422 + 0xbfecfd852fff6ad4, 0xbfdb18d45bf8aca6, // -0.90595, -0.42339 + 0xbfecf830e8ce467b, 0xbfdb2f971db31972, // -0.9053, -0.42478 + 0xbfecf2d829f1b40e, 0xbfdb4655ae2bf757, // -0.90464, -0.42617 + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756 + 0xbfece819488344ce, 0xbfdb73c62d520624, // -0.90333, -0.42894 + 0xbfece2b32799a060, 0xbfdb8a7814fd5693, // -0.90267, -0.43033 + 0xbfecdd489254fe65, 0xbfdba125bd63583e, // -0.90201, -0.43171 + 0xbfecd7d9898b32f6, 0xbfdbb7cf2304bd01, // -0.90135, -0.43309 + 0xbfecd2660e12c1e6, 0xbfdbce744262deee, // -0.90068, -0.43448 + 0xbfecccee20c2de9f, 0xbfdbe51517ffc0d9, // -0.90002, -0.43586 + 0xbfecc771c2736c09, 0xbfdbfbb1a05e0edc, // -0.89935, -0.43724 + 0xbfecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // -0.89867, -0.43862 + 0xbfecbc6bb638d10b, 0xbfdc28ddbb6cf145, // -0.898, -0.43999 + 0xbfecb6e20a00da99, 0xbfdc3f6d47263129, // -0.89732, -0.44137 + 0xbfecb153f02fb87d, 0xbfdc55f877b23537, // -0.89665, -0.44275 + 0xbfecabc169a0b901, 0xbfdc6c7f4997000a, // -0.89597, -0.44412 + 0xbfeca62a772fd919, 0xbfdc8301b95b40c2, // -0.89528, -0.4455 + 0xbfeca08f19b9c449, 0xbfdc997fc3865388, // -0.8946, -0.44687 + 0xbfec9aef521bd480, 0xbfdcaff964a0421d, // -0.89391, -0.44824 + 0xbfec954b213411f5, 0xbfdcc66e9931c45d, // -0.89322, -0.44961 + 0xbfec8fa287e13305, 0xbfdcdcdf5dc440ce, // -0.89253, -0.45098 + 0xbfec89f587029c13, 0xbfdcf34baee1cd21, // -0.89184, -0.45235 + 0xbfec84441f785f61, 0xbfdd09b389152ec1, // -0.89115, -0.45372 + 0xbfec7e8e52233cf3, 0xbfdd2016e8e9db5b, // -0.89045, -0.45508 + 0xbfec78d41fe4a267, 0xbfdd3675caebf962, // -0.88975, -0.45645 + 0xbfec7315899eaad7, 0xbfdd4cd02ba8609c, // -0.88905, -0.45781 + 0xbfec6d5290341eb2, 0xbfdd632607ac9aa9, // -0.88835, -0.45918 + 0xbfec678b3488739b, 0xbfdd79775b86e389, // -0.88764, -0.46054 + 0xbfec61bf777fcc48, 0xbfdd8fc423c62a25, // -0.88693, -0.4619 + 0xbfec5bef59fef85a, 0xbfdda60c5cfa10d8, // -0.88622, -0.46326 + 0xbfec561adceb743e, 0xbfddbc5003b2edf8, // -0.88551, -0.46462 + 0xbfec5042012b6907, 0xbfddd28f1481cc58, // -0.8848, -0.46598 + 0xbfec4a64c7a5ac4c, 0xbfdde8c98bf86bd6, // -0.88408, -0.46733 + 0xbfec44833141c004, 0xbfddfeff66a941de, // -0.88336, -0.46869 + 0xbfec3e9d3ee7d262, 0xbfde1530a12779f4, // -0.88264, -0.47004 + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714 + 0xbfec32c449f60831, 0xbfde418527dc4ffa, // -0.8812, -0.47275 + 0xbfec2cd14931e3f1, 0xbfde57a86d3cd824, // -0.88047, -0.4741 + 0xbfec26d9f01f2eaf, 0xbfde6dc704be97e2, // -0.87974, -0.47545 + 0xbfec20de3fa971b0, 0xbfde83e0eaf85113, // -0.87901, -0.4768 + 0xbfec1ade38bce19b, 0xbfde99f61c817eda, // -0.87828, -0.47815 + 0xbfec14d9dc465e58, 0xbfdeb00695f25620, // -0.87755, -0.47949 + 0xbfec0ed12b3372e9, 0xbfdec61253e3c61b, // -0.87681, -0.48084 + 0xbfec08c426725549, 0xbfdedc1952ef78d5, // -0.87607, -0.48218 + 0xbfec02b2cef1e641, 0xbfdef21b8fafd3b5, // -0.87533, -0.48353 + 0xbfebfc9d25a1b147, 0xbfdf081906bff7fd, // -0.87459, -0.48487 + 0xbfebf6832b71ec5b, 0xbfdf1e11b4bbc35c, // -0.87384, -0.48621 + 0xbfebf064e15377dd, 0xbfdf3405963fd068, // -0.87309, -0.48755 + 0xbfebea424837de6d, 0xbfdf49f4a7e97729, // -0.87235, -0.48889 + 0xbfebe41b611154c1, 0xbfdf5fdee656cda3, // -0.8716, -0.49023 + 0xbfebddf02cd2b983, 0xbfdf75c44e26a852, // -0.87084, -0.49156 + 0xbfebd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // -0.87009, -0.4929 + 0xbfebd18ce0dc19d6, 0xbfdfa1808c6cf7e0, // -0.86933, -0.49423 + 0xbfebcb54cb0d2327, 0xbfdfb7575c24d2de, // -0.86857, -0.49557 + 0xbfebc5186bf8361d, 0xbfdfcd2947c1ff57, // -0.86781, -0.4969 + 0xbfebbed7c49380ea, 0xbfdfe2f64be7120f, // -0.86705, -0.49823 + 0xbfebb892d5d5dad5, 0xbfdff8be6537615e, // -0.86628, -0.49956 + 0xbfebb249a0b6c40d, 0xbfe00740c82b82e0, // -0.86551, -0.50089 + 0xbfebabfc262e6586, 0xbfe0121fe4f56d2c, // -0.86474, -0.50221 + 0xbfeba5aa673590d2, 0xbfe01cfc874c3eb7, // -0.86397, -0.50354 + 0xbfeb9f5464c5bffc, 0xbfe027d6ad83287e, // -0.8632, -0.50486 + 0xbfeb98fa1fd9155e, 0xbfe032ae55edbd95, // -0.86242, -0.50619 + 0xbfeb929b996a5b7f, 0xbfe03d837edff370, // -0.86165, -0.50751 + 0xbfeb8c38d27504e9, 0xbfe0485626ae221a, // -0.86087, -0.50883 + 0xbfeb85d1cbf52c02, 0xbfe053264bad0483, // -0.86009, -0.51015 + 0xbfeb7f6686e792ea, 0xbfe05df3ec31b8b6, // -0.8593, -0.51147 + 0xbfeb78f70449a34b, 0xbfe068bf0691c028, // -0.85852, -0.51279 + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141 + 0xbfeb6c0b4a55ac17, 0xbfe07e4da23bc102, // -0.85694, -0.51542 + 0xbfeb658f14fdbc47, 0xbfe089112032b08c, // -0.85615, -0.51673 + 0xbfeb5f0ea611a532, 0xbfe093d2115ee018, // -0.85535, -0.51804 + 0xbfeb5889fe921405, 0xbfe09e907417c5e1, // -0.85456, -0.51936 + 0xbfeb52011f805c92, 0xbfe0a94c46b53d0b, // -0.85376, -0.52067 + 0xbfeb4b7409de7925, 0xbfe0b405878f85ec, // -0.85296, -0.52198 + 0xbfeb44e2beaf0a61, 0xbfe0bebc34ff4646, // -0.85216, -0.52328 + 0xbfeb3e4d3ef55712, 0xbfe0c9704d5d898f, // -0.85136, -0.52459 + 0xbfeb37b38bb54c09, 0xbfe0d421cf03c12b, // -0.85055, -0.5259 + 0xbfeb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // -0.84974, -0.5272 + 0xbfeb2a738eb51f33, 0xbfe0e97d078fd23b, // -0.84893, -0.5285 + 0xbfeb23cd470013b4, 0xbfe0f426bb2a8e7d, // -0.84812, -0.5298 + 0xbfeb1d22cfdadcc6, 0xbfe0fecdd1770537, // -0.84731, -0.5311 + 0xbfeb16742a4ca2f5, 0xbfe1097248d0a956, // -0.84649, -0.5324 + 0xbfeb0fc1575d33db, 0xbfe114141f935545, // -0.84567, -0.5337 + 0xbfeb090a58150200, 0xbfe11eb3541b4b22, // -0.84485, -0.535 + 0xbfeb024f2d7d24a9, 0xbfe1294fe4c5350a, // -0.84403, -0.53629 + 0xbfeafb8fd89f57b6, 0xbfe133e9cfee254e, // -0.84321, -0.53759 + 0xbfeaf4cc5a85fb73, 0xbfe13e8113f396c1, // -0.84238, -0.53888 + 0xbfeaee04b43c1474, 0xbfe14915af336ceb, // -0.84155, -0.54017 + 0xbfeae738e6cd4b67, 0xbfe153a7a00bf453, // -0.84073, -0.54146 + 0xbfeae068f345ecef, 0xbfe15e36e4dbe2bc, // -0.83989, -0.54275 + 0xbfead994dab2e979, 0xbfe168c37c025764, // -0.83906, -0.54404 + 0xbfead2bc9e21d511, 0xbfe1734d63dedb49, // -0.83822, -0.54532 + 0xbfeacbe03ea0e73b, 0xbfe17dd49ad16161, // -0.83739, -0.54661 + 0xbfeac4ffbd3efac8, 0xbfe188591f3a46e5, // -0.83655, -0.54789 + 0xbfeabe1b1b0b8dac, 0xbfe192daef7a5386, // -0.83571, -0.54918 + 0xbfeab7325916c0d4, 0xbfe19d5a09f2b9b8, // -0.83486, -0.55046 + 0xbfeab045787157ff, 0xbfe1a7d66d0516e6, // -0.83402, -0.55174 + 0xbfeaa9547a2cb98e, 0xbfe1b250171373be, // -0.83317, -0.55302 + 0xbfeaa25f5f5aee60, 0xbfe1bcc706804467, // -0.83232, -0.55429 + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557 + 0xbfea9468d85b20ae, 0xbfe1d1acaf012cc2, // -0.83062, -0.55685 + 0xbfea8d676e545ad2, 0xbfe1dc1b64dc4872, // -0.82976, -0.55812 + 0xbfea8661ec0ee133, 0xbfe1e68759a3e074, // -0.8289, -0.55939 + 0xbfea7f58529fe69d, 0xbfe1f0f08bbc861b, // -0.82805, -0.56066 + 0xbfea784aa31d3f55, 0xbfe1fb56f98b37b8, // -0.82718, -0.56193 + 0xbfea7138de9d60f5, 0xbfe205baa17560d6, // -0.82632, -0.5632 + 0xbfea6a230637623b, 0xbfe2101b81e0da78, // -0.82546, -0.56447 + 0xbfea63091b02fae2, 0xbfe21a799933eb58, // -0.82459, -0.56573 + 0xbfea5beb1e188375, 0xbfe224d4e5d5482e, // -0.82372, -0.567 + 0xbfea54c91090f524, 0xbfe22f2d662c13e1, // -0.82285, -0.56826 + 0xbfea4da2f385e997, 0xbfe23983189fdfd5, // -0.82198, -0.56952 + 0xbfea4678c8119ac8, 0xbfe243d5fb98ac1f, // -0.8211, -0.57078 + 0xbfea3f4a8f4ee2d2, 0xbfe24e260d7ee7c9, // -0.82023, -0.57204 + 0xbfea38184a593bc6, 0xbfe258734cbb7110, // -0.81935, -0.5733 + 0xbfea30e1fa4cbf81, 0xbfe262bdb7b795a2, // -0.81847, -0.57455 + 0xbfea29a7a0462782, 0xbfe26d054cdd12df, // -0.81758, -0.57581 + 0xbfea22693d62ccb9, 0xbfe2774a0a961612, // -0.8167, -0.57706 + 0xbfea1b26d2c0a75e, 0xbfe2818bef4d3cba, // -0.81581, -0.57831 + 0xbfea13e0617e4ec7, 0xbfe28bcaf96d94ba, // -0.81493, -0.57956 + 0xbfea0c95eabaf937, 0xbfe2960727629ca8, // -0.81404, -0.58081 + 0xbfea05476f967bb5, 0xbfe2a040779843fb, // -0.81314, -0.58206 + 0xbfe9fdf4f13149de, 0xbfe2aa76e87aeb58, // -0.81225, -0.58331 + 0xbfe9f69e70ac75bc, 0xbfe2b4aa787764c4, // -0.81135, -0.58455 + 0xbfe9ef43ef29af94, 0xbfe2bedb25faf3ea, // -0.81046, -0.5858 + 0xbfe9e7e56dcb45bd, 0xbfe2c908ef734e57, // -0.80956, -0.58704 + 0xbfe9e082edb42472, 0xbfe2d333d34e9bb7, // -0.80866, -0.58828 + 0xbfe9d91c7007d5a6, 0xbfe2dd5bcffb7616, // -0.80775, -0.58952 + 0xbfe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // -0.80685, -0.59076 + 0xbfe9ca438080eadb, 0xbfe2f1a30d86773a, // -0.80594, -0.592 + 0xbfe9c2d110f075c3, 0xbfe2fbc24b441015, // -0.80503, -0.59323 + 0xbfe9bb5aa85f2098, 0xbfe305de9b921a94, // -0.80412, -0.59447 + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957 + 0xbfe9ac61f0d4e247, 0xbfe31a0e6da35e44, // -0.80229, -0.59693 + 0xbfe9a4dfa42b06b2, 0xbfe32421ec49a620, // -0.80138, -0.59816 + 0xbfe99d59631e65d5, 0xbfe32e3277467d6b, // -0.80046, -0.59939 + 0xbfe995cf2ed80d22, 0xbfe338400d0c8e57, // -0.79954, -0.60062 + 0xbfe98e410881a600, 0xbfe3424aac0ef7d6, // -0.79861, -0.60184 + 0xbfe986aef1457594, 0xbfe34c5252c14de1, // -0.79769, -0.60307 + 0xbfe97f18ea4e5c9e, 0xbfe35656ff9799ae, // -0.79676, -0.60429 + 0xbfe9777ef4c7d742, 0xbfe36058b10659f3, // -0.79584, -0.60551 + 0xbfe96fe111ddfce0, 0xbfe36a576582831b, // -0.79491, -0.60673 + 0xbfe9683f42bd7fe1, 0xbfe374531b817f8d, // -0.79398, -0.60795 + 0xbfe960998893ad8c, 0xbfe37e4bd1792fe2, // -0.79304, -0.60917 + 0xbfe958efe48e6dd7, 0xbfe3884185dfeb22, // -0.79211, -0.61038 + 0xbfe9514257dc4335, 0xbfe39234372c7f04, // -0.79117, -0.6116 + 0xbfe94990e3ac4a6c, 0xbfe39c23e3d63029, // -0.79023, -0.61281 + 0xbfe941db892e3a65, 0xbfe3a6108a54ba58, // -0.78929, -0.61402 + 0xbfe93a22499263fc, 0xbfe3affa292050b9, // -0.78835, -0.61523 + 0xbfe932652609b1cf, 0xbfe3b9e0beb19e18, // -0.7874, -0.61644 + 0xbfe92aa41fc5a815, 0xbfe3c3c44981c517, // -0.78646, -0.61765 + 0xbfe922df37f8646a, 0xbfe3cda4c80a6076, // -0.78551, -0.61885 + 0xbfe91b166fd49da2, 0xbfe3d78238c58343, // -0.78456, -0.62006 + 0xbfe91349c88da398, 0xbfe3e15c9a2db922, // -0.7836, -0.62126 + 0xbfe90b7943575efe, 0xbfe3eb33eabe0680, // -0.78265, -0.62246 + 0xbfe903a4e1665133, 0xbfe3f50828f1e8d2, // -0.78169, -0.62366 + 0xbfe8fbcca3ef940d, 0xbfe3fed9534556d4, // -0.78074, -0.62486 + 0xbfe8f3f08c28d9ac, 0xbfe408a76834c0c0, // -0.77978, -0.62606 + 0xbfe8ec109b486c49, 0xbfe41272663d108c, // -0.77882, -0.62725 + 0xbfe8e42cd2852e0a, 0xbfe41c3a4bdbaa26, // -0.77785, -0.62845 + 0xbfe8dc45331698cc, 0xbfe425ff178e6bb1, // -0.77689, -0.62964 + 0xbfe8d459be34bdfa, 0xbfe42fc0c7d3adbb, // -0.77592, -0.63083 + 0xbfe8cc6a75184655, 0xbfe4397f5b2a4380, // -0.77495, -0.63202 + 0xbfe8c47758fa71cb, 0xbfe4433ad0117b1d, // -0.77398, -0.63321 + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439 + 0xbfe8b485aca2a468, 0xbfe456a858917046, // -0.77204, -0.63558 + 0xbfe8ac871ede1d88, 0xbfe4605a692b32a2, // -0.77106, -0.63676 + 0xbfe8a484c3031d50, 0xbfe46a095557a0f1, // -0.77008, -0.63794 + 0xbfe89c7e9a4dd4ab, 0xbfe473b51b987347, // -0.7691, -0.63912 + 0xbfe89474a5fb0a84, 0xbfe47d5dba6fde01, // -0.76812, -0.6403 + 0xbfe88c66e7481ba1, 0xbfe48703306091fe, // -0.76714, -0.64148 + 0xbfe884555f72fa6b, 0xbfe490a57bedbcdf, // -0.76615, -0.64266 + 0xbfe87c400fba2ebf, 0xbfe49a449b9b0938, // -0.76517, -0.64383 + 0xbfe87426f95cd5bd, 0xbfe4a3e08dec9ed6, // -0.76418, -0.645 + 0xbfe86c0a1d9aa195, 0xbfe4ad79516722f0, // -0.76319, -0.64618 + 0xbfe863e97db3d95a, 0xbfe4b70ee48fb869, // -0.7622, -0.64735 + 0xbfe85bc51ae958cc, 0xbfe4c0a145ec0004, // -0.7612, -0.64851 + 0xbfe8539cf67c9029, 0xbfe4ca30740218a3, // -0.76021, -0.64968 + 0xbfe84b7111af83f9, 0xbfe4d3bc6d589f80, // -0.75921, -0.65085 + 0xbfe843416dc4cce2, 0xbfe4dd453076b064, // -0.75821, -0.65201 + 0xbfe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // -0.75721, -0.65317 + 0xbfe832d6eda3a3e0, 0xbfe4f04d0e2859aa, // -0.75621, -0.65433 + 0xbfe82a9c13f545ff, 0xbfe4f9cc25cca486, // -0.7552, -0.65549 + 0xbfe8225d803964e5, 0xbfe503480159ded2, // -0.75419, -0.65665 + 0xbfe81a1b33b57acc, 0xbfe50cc09f59a09b, // -0.75319, -0.65781 + 0xbfe811d52faf94dc, 0xbfe51635fe5601d7, // -0.75218, -0.65896 + 0xbfe8098b756e52fa, 0xbfe51fa81cd99aa6, // -0.75117, -0.66011 + 0xbfe8013e0638e795, 0xbfe52916f96f8388, // -0.75015, -0.66127 + 0xbfe7f8ece3571771, 0xbfe5328292a35596, // -0.74914, -0.66242 + 0xbfe7f0980e113978, 0xbfe53beae7012abe, // -0.74812, -0.66356 + 0xbfe7e83f87b03686, 0xbfe5454ff5159dfb, // -0.7471, -0.66471 + 0xbfe7dfe3517d8937, 0xbfe54eb1bb6dcb8f, // -0.74608, -0.66586 + 0xbfe7d7836cc33db2, 0xbfe5581038975137, // -0.74506, -0.667 + 0xbfe7cf1fdacbf179, 0xbfe5616b6b204e6e, // -0.74403, -0.66814 + 0xbfe7c6b89ce2d333, 0xbfe56ac35197649e, // -0.74301, -0.66928 + 0xbfe7be4db453a27c, 0xbfe57417ea8bb75c, // -0.74198, -0.67042 + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156 + 0xbfe7ad6ce874dbb6, 0xbfe586b72e2b2cfd, // -0.73992, -0.67269 + 0xbfe7a4f707bf97d2, 0xbfe59001d5f723df, // -0.73889, -0.67383 + 0xbfe79c7d8198e56e, 0xbfe599492a81ffbc, // -0.73785, -0.67496 + 0xbfe79400574f55e4, 0xbfe5a28d2a5d7250, // -0.73682, -0.67609 + 0xbfe78b7f8a320a52, 0xbfe5abcdd41bb0d8, // -0.73578, -0.67722 + 0xbfe782fb1b90b35b, 0xbfe5b50b264f7448, // -0.73474, -0.67835 + 0xbfe77a730cbb9100, 0xbfe5be451f8bf980, // -0.7337, -0.67948 + 0xbfe771e75f037261, 0xbfe5c77bbe65018c, // -0.73265, -0.6806 + 0xbfe7695813b9b594, 0xbfe5d0af016ed1d4, // -0.73161, -0.68172 + 0xbfe760c52c304764, 0xbfe5d9dee73e345c, // -0.73056, -0.68285 + 0xbfe7582ea9b9a329, 0xbfe5e30b6e6877f3, // -0.72951, -0.68397 + 0xbfe74f948da8d28d, 0xbfe5ec3495837074, // -0.72846, -0.68508 + 0xbfe746f6d9516d59, 0xbfe5f55a5b2576f8, // -0.72741, -0.6862 + 0xbfe73e558e079942, 0xbfe5fe7cbde56a0f, // -0.72636, -0.68732 + 0xbfe735b0ad2009b2, 0xbfe6079bbc5aadfa, // -0.7253, -0.68843 + 0xbfe72d0837efff97, 0xbfe610b7551d2cde, // -0.72425, -0.68954 + 0xbfe7245c2fcd492a, 0xbfe619cf86c55702, // -0.72319, -0.69065 + 0xbfe71bac960e41bf, 0xbfe622e44fec22ff, // -0.72213, -0.69176 + 0xbfe712f96c09d18d, 0xbfe62bf5af2b0dfd, // -0.72107, -0.69287 + 0xbfe70a42b3176d7a, 0xbfe63503a31c1be8, // -0.72, -0.69397 + 0xbfe701886c8f16e6, 0xbfe63e0e2a59d7aa, // -0.71894, -0.69508 + 0xbfe6f8ca99c95b75, 0xbfe64715437f535b, // -0.71787, -0.69618 + 0xbfe6f0093c1f54de, 0xbfe65018ed28287f, // -0.7168, -0.69728 + 0xbfe6e74454eaa8ae, 0xbfe6591925f0783e, // -0.71573, -0.69838 + 0xbfe6de7be585881d, 0xbfe66215ec74eb91, // -0.71466, -0.69947 + 0xbfe6d5afef4aafcc, 0xbfe66b0f3f52b386, // -0.71358, -0.70057 + 0xbfe6cce07395679f, 0xbfe674051d27896c, // -0.71251, -0.70166 + 0xbfe6c40d73c18275, 0xbfe67cf78491af10, // -0.71143, -0.70275 + 0xbfe6bb36f12b5e06, 0xbfe685e6742feeef, // -0.71035, -0.70385 + 0xbfe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // -0.70927, -0.70493 + 0xbfe6a97f692c82ea, 0xbfe697b9e686941c, // -0.70819, -0.70602 + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711 + 0xbfe697b9e686941c, 0xbfe6a97f692c82ea, // -0.70602, -0.70819 + 0xbfe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // -0.70493, -0.70927 + 0xbfe685e6742feeef, 0xbfe6bb36f12b5e06, // -0.70385, -0.71035 + 0xbfe67cf78491af10, 0xbfe6c40d73c18275, // -0.70275, -0.71143 + 0xbfe674051d27896c, 0xbfe6cce07395679f, // -0.70166, -0.71251 + 0xbfe66b0f3f52b386, 0xbfe6d5afef4aafcc, // -0.70057, -0.71358 + 0xbfe66215ec74eb91, 0xbfe6de7be585881d, // -0.69947, -0.71466 + 0xbfe6591925f0783e, 0xbfe6e74454eaa8ae, // -0.69838, -0.71573 + 0xbfe65018ed28287f, 0xbfe6f0093c1f54de, // -0.69728, -0.7168 + 0xbfe64715437f535b, 0xbfe6f8ca99c95b75, // -0.69618, -0.71787 + 0xbfe63e0e2a59d7aa, 0xbfe701886c8f16e6, // -0.69508, -0.71894 + 0xbfe63503a31c1be8, 0xbfe70a42b3176d7a, // -0.69397, -0.72 + 0xbfe62bf5af2b0dfd, 0xbfe712f96c09d18d, // -0.69287, -0.72107 + 0xbfe622e44fec22ff, 0xbfe71bac960e41bf, // -0.69176, -0.72213 + 0xbfe619cf86c55702, 0xbfe7245c2fcd492a, // -0.69065, -0.72319 + 0xbfe610b7551d2cde, 0xbfe72d0837efff97, // -0.68954, -0.72425 + 0xbfe6079bbc5aadfa, 0xbfe735b0ad2009b2, // -0.68843, -0.7253 + 0xbfe5fe7cbde56a0f, 0xbfe73e558e079942, // -0.68732, -0.72636 + 0xbfe5f55a5b2576f8, 0xbfe746f6d9516d59, // -0.6862, -0.72741 + 0xbfe5ec3495837074, 0xbfe74f948da8d28d, // -0.68508, -0.72846 + 0xbfe5e30b6e6877f3, 0xbfe7582ea9b9a329, // -0.68397, -0.72951 + 0xbfe5d9dee73e345c, 0xbfe760c52c304764, // -0.68285, -0.73056 + 0xbfe5d0af016ed1d4, 0xbfe7695813b9b594, // -0.68172, -0.73161 + 0xbfe5c77bbe65018c, 0xbfe771e75f037261, // -0.6806, -0.73265 + 0xbfe5be451f8bf980, 0xbfe77a730cbb9100, // -0.67948, -0.7337 + 0xbfe5b50b264f7448, 0xbfe782fb1b90b35b, // -0.67835, -0.73474 + 0xbfe5abcdd41bb0d8, 0xbfe78b7f8a320a52, // -0.67722, -0.73578 + 0xbfe5a28d2a5d7250, 0xbfe79400574f55e4, // -0.67609, -0.73682 + 0xbfe599492a81ffbc, 0xbfe79c7d8198e56e, // -0.67496, -0.73785 + 0xbfe59001d5f723df, 0xbfe7a4f707bf97d2, // -0.67383, -0.73889 + 0xbfe586b72e2b2cfd, 0xbfe7ad6ce874dbb6, // -0.67269, -0.73992 + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095 + 0xbfe57417ea8bb75c, 0xbfe7be4db453a27c, // -0.67042, -0.74198 + 0xbfe56ac35197649e, 0xbfe7c6b89ce2d333, // -0.66928, -0.74301 + 0xbfe5616b6b204e6e, 0xbfe7cf1fdacbf179, // -0.66814, -0.74403 + 0xbfe5581038975137, 0xbfe7d7836cc33db2, // -0.667, -0.74506 + 0xbfe54eb1bb6dcb8f, 0xbfe7dfe3517d8937, // -0.66586, -0.74608 + 0xbfe5454ff5159dfb, 0xbfe7e83f87b03686, // -0.66471, -0.7471 + 0xbfe53beae7012abe, 0xbfe7f0980e113978, // -0.66356, -0.74812 + 0xbfe5328292a35596, 0xbfe7f8ece3571771, // -0.66242, -0.74914 + 0xbfe52916f96f8388, 0xbfe8013e0638e795, // -0.66127, -0.75015 + 0xbfe51fa81cd99aa6, 0xbfe8098b756e52fa, // -0.66011, -0.75117 + 0xbfe51635fe5601d7, 0xbfe811d52faf94dc, // -0.65896, -0.75218 + 0xbfe50cc09f59a09b, 0xbfe81a1b33b57acc, // -0.65781, -0.75319 + 0xbfe503480159ded2, 0xbfe8225d803964e5, // -0.65665, -0.75419 + 0xbfe4f9cc25cca486, 0xbfe82a9c13f545ff, // -0.65549, -0.7552 + 0xbfe4f04d0e2859aa, 0xbfe832d6eda3a3e0, // -0.65433, -0.75621 + 0xbfe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // -0.65317, -0.75721 + 0xbfe4dd453076b064, 0xbfe843416dc4cce2, // -0.65201, -0.75821 + 0xbfe4d3bc6d589f80, 0xbfe84b7111af83f9, // -0.65085, -0.75921 + 0xbfe4ca30740218a3, 0xbfe8539cf67c9029, // -0.64968, -0.76021 + 0xbfe4c0a145ec0004, 0xbfe85bc51ae958cc, // -0.64851, -0.7612 + 0xbfe4b70ee48fb869, 0xbfe863e97db3d95a, // -0.64735, -0.7622 + 0xbfe4ad79516722f0, 0xbfe86c0a1d9aa195, // -0.64618, -0.76319 + 0xbfe4a3e08dec9ed6, 0xbfe87426f95cd5bd, // -0.645, -0.76418 + 0xbfe49a449b9b0938, 0xbfe87c400fba2ebf, // -0.64383, -0.76517 + 0xbfe490a57bedbcdf, 0xbfe884555f72fa6b, // -0.64266, -0.76615 + 0xbfe48703306091fe, 0xbfe88c66e7481ba1, // -0.64148, -0.76714 + 0xbfe47d5dba6fde01, 0xbfe89474a5fb0a84, // -0.6403, -0.76812 + 0xbfe473b51b987347, 0xbfe89c7e9a4dd4ab, // -0.63912, -0.7691 + 0xbfe46a095557a0f1, 0xbfe8a484c3031d50, // -0.63794, -0.77008 + 0xbfe4605a692b32a2, 0xbfe8ac871ede1d88, // -0.63676, -0.77106 + 0xbfe456a858917046, 0xbfe8b485aca2a468, // -0.63558, -0.77204 + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301 + 0xbfe4433ad0117b1d, 0xbfe8c47758fa71cb, // -0.63321, -0.77398 + 0xbfe4397f5b2a4380, 0xbfe8cc6a75184655, // -0.63202, -0.77495 + 0xbfe42fc0c7d3adbb, 0xbfe8d459be34bdfa, // -0.63083, -0.77592 + 0xbfe425ff178e6bb1, 0xbfe8dc45331698cc, // -0.62964, -0.77689 + 0xbfe41c3a4bdbaa26, 0xbfe8e42cd2852e0a, // -0.62845, -0.77785 + 0xbfe41272663d108c, 0xbfe8ec109b486c49, // -0.62725, -0.77882 + 0xbfe408a76834c0c0, 0xbfe8f3f08c28d9ac, // -0.62606, -0.77978 + 0xbfe3fed9534556d4, 0xbfe8fbcca3ef940d, // -0.62486, -0.78074 + 0xbfe3f50828f1e8d2, 0xbfe903a4e1665133, // -0.62366, -0.78169 + 0xbfe3eb33eabe0680, 0xbfe90b7943575efe, // -0.62246, -0.78265 + 0xbfe3e15c9a2db922, 0xbfe91349c88da398, // -0.62126, -0.7836 + 0xbfe3d78238c58343, 0xbfe91b166fd49da2, // -0.62006, -0.78456 + 0xbfe3cda4c80a6076, 0xbfe922df37f8646a, // -0.61885, -0.78551 + 0xbfe3c3c44981c517, 0xbfe92aa41fc5a815, // -0.61765, -0.78646 + 0xbfe3b9e0beb19e18, 0xbfe932652609b1cf, // -0.61644, -0.7874 + 0xbfe3affa292050b9, 0xbfe93a22499263fc, // -0.61523, -0.78835 + 0xbfe3a6108a54ba58, 0xbfe941db892e3a65, // -0.61402, -0.78929 + 0xbfe39c23e3d63029, 0xbfe94990e3ac4a6c, // -0.61281, -0.79023 + 0xbfe39234372c7f04, 0xbfe9514257dc4335, // -0.6116, -0.79117 + 0xbfe3884185dfeb22, 0xbfe958efe48e6dd7, // -0.61038, -0.79211 + 0xbfe37e4bd1792fe2, 0xbfe960998893ad8c, // -0.60917, -0.79304 + 0xbfe374531b817f8d, 0xbfe9683f42bd7fe1, // -0.60795, -0.79398 + 0xbfe36a576582831b, 0xbfe96fe111ddfce0, // -0.60673, -0.79491 + 0xbfe36058b10659f3, 0xbfe9777ef4c7d742, // -0.60551, -0.79584 + 0xbfe35656ff9799ae, 0xbfe97f18ea4e5c9e, // -0.60429, -0.79676 + 0xbfe34c5252c14de1, 0xbfe986aef1457594, // -0.60307, -0.79769 + 0xbfe3424aac0ef7d6, 0xbfe98e410881a600, // -0.60184, -0.79861 + 0xbfe338400d0c8e57, 0xbfe995cf2ed80d22, // -0.60062, -0.79954 + 0xbfe32e3277467d6b, 0xbfe99d59631e65d5, // -0.59939, -0.80046 + 0xbfe32421ec49a620, 0xbfe9a4dfa42b06b2, // -0.59816, -0.80138 + 0xbfe31a0e6da35e44, 0xbfe9ac61f0d4e247, // -0.59693, -0.80229 + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321 + 0xbfe305de9b921a94, 0xbfe9bb5aa85f2098, // -0.59447, -0.80412 + 0xbfe2fbc24b441015, 0xbfe9c2d110f075c3, // -0.59323, -0.80503 + 0xbfe2f1a30d86773a, 0xbfe9ca438080eadb, // -0.592, -0.80594 + 0xbfe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // -0.59076, -0.80685 + 0xbfe2dd5bcffb7616, 0xbfe9d91c7007d5a6, // -0.58952, -0.80775 + 0xbfe2d333d34e9bb7, 0xbfe9e082edb42472, // -0.58828, -0.80866 + 0xbfe2c908ef734e57, 0xbfe9e7e56dcb45bd, // -0.58704, -0.80956 + 0xbfe2bedb25faf3ea, 0xbfe9ef43ef29af94, // -0.5858, -0.81046 + 0xbfe2b4aa787764c4, 0xbfe9f69e70ac75bc, // -0.58455, -0.81135 + 0xbfe2aa76e87aeb58, 0xbfe9fdf4f13149de, // -0.58331, -0.81225 + 0xbfe2a040779843fb, 0xbfea05476f967bb5, // -0.58206, -0.81314 + 0xbfe2960727629ca8, 0xbfea0c95eabaf937, // -0.58081, -0.81404 + 0xbfe28bcaf96d94ba, 0xbfea13e0617e4ec7, // -0.57956, -0.81493 + 0xbfe2818bef4d3cba, 0xbfea1b26d2c0a75e, // -0.57831, -0.81581 + 0xbfe2774a0a961612, 0xbfea22693d62ccb9, // -0.57706, -0.8167 + 0xbfe26d054cdd12df, 0xbfea29a7a0462782, // -0.57581, -0.81758 + 0xbfe262bdb7b795a2, 0xbfea30e1fa4cbf81, // -0.57455, -0.81847 + 0xbfe258734cbb7110, 0xbfea38184a593bc6, // -0.5733, -0.81935 + 0xbfe24e260d7ee7c9, 0xbfea3f4a8f4ee2d2, // -0.57204, -0.82023 + 0xbfe243d5fb98ac1f, 0xbfea4678c8119ac8, // -0.57078, -0.8211 + 0xbfe23983189fdfd5, 0xbfea4da2f385e997, // -0.56952, -0.82198 + 0xbfe22f2d662c13e1, 0xbfea54c91090f524, // -0.56826, -0.82285 + 0xbfe224d4e5d5482e, 0xbfea5beb1e188375, // -0.567, -0.82372 + 0xbfe21a799933eb58, 0xbfea63091b02fae2, // -0.56573, -0.82459 + 0xbfe2101b81e0da78, 0xbfea6a230637623b, // -0.56447, -0.82546 + 0xbfe205baa17560d6, 0xbfea7138de9d60f5, // -0.5632, -0.82632 + 0xbfe1fb56f98b37b8, 0xbfea784aa31d3f55, // -0.56193, -0.82718 + 0xbfe1f0f08bbc861b, 0xbfea7f58529fe69d, // -0.56066, -0.82805 + 0xbfe1e68759a3e074, 0xbfea8661ec0ee133, // -0.55939, -0.8289 + 0xbfe1dc1b64dc4872, 0xbfea8d676e545ad2, // -0.55812, -0.82976 + 0xbfe1d1acaf012cc2, 0xbfea9468d85b20ae, // -0.55685, -0.83062 + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147 + 0xbfe1bcc706804467, 0xbfeaa25f5f5aee60, // -0.55429, -0.83232 + 0xbfe1b250171373be, 0xbfeaa9547a2cb98e, // -0.55302, -0.83317 + 0xbfe1a7d66d0516e6, 0xbfeab045787157ff, // -0.55174, -0.83402 + 0xbfe19d5a09f2b9b8, 0xbfeab7325916c0d4, // -0.55046, -0.83486 + 0xbfe192daef7a5386, 0xbfeabe1b1b0b8dac, // -0.54918, -0.83571 + 0xbfe188591f3a46e5, 0xbfeac4ffbd3efac8, // -0.54789, -0.83655 + 0xbfe17dd49ad16161, 0xbfeacbe03ea0e73b, // -0.54661, -0.83739 + 0xbfe1734d63dedb49, 0xbfead2bc9e21d511, // -0.54532, -0.83822 + 0xbfe168c37c025764, 0xbfead994dab2e979, // -0.54404, -0.83906 + 0xbfe15e36e4dbe2bc, 0xbfeae068f345ecef, // -0.54275, -0.83989 + 0xbfe153a7a00bf453, 0xbfeae738e6cd4b67, // -0.54146, -0.84073 + 0xbfe14915af336ceb, 0xbfeaee04b43c1474, // -0.54017, -0.84155 + 0xbfe13e8113f396c1, 0xbfeaf4cc5a85fb73, // -0.53888, -0.84238 + 0xbfe133e9cfee254e, 0xbfeafb8fd89f57b6, // -0.53759, -0.84321 + 0xbfe1294fe4c5350a, 0xbfeb024f2d7d24a9, // -0.53629, -0.84403 + 0xbfe11eb3541b4b22, 0xbfeb090a58150200, // -0.535, -0.84485 + 0xbfe114141f935545, 0xbfeb0fc1575d33db, // -0.5337, -0.84567 + 0xbfe1097248d0a956, 0xbfeb16742a4ca2f5, // -0.5324, -0.84649 + 0xbfe0fecdd1770537, 0xbfeb1d22cfdadcc6, // -0.5311, -0.84731 + 0xbfe0f426bb2a8e7d, 0xbfeb23cd470013b4, // -0.5298, -0.84812 + 0xbfe0e97d078fd23b, 0xbfeb2a738eb51f33, // -0.5285, -0.84893 + 0xbfe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // -0.5272, -0.84974 + 0xbfe0d421cf03c12b, 0xbfeb37b38bb54c09, // -0.5259, -0.85055 + 0xbfe0c9704d5d898f, 0xbfeb3e4d3ef55712, // -0.52459, -0.85136 + 0xbfe0bebc34ff4646, 0xbfeb44e2beaf0a61, // -0.52328, -0.85216 + 0xbfe0b405878f85ec, 0xbfeb4b7409de7925, // -0.52198, -0.85296 + 0xbfe0a94c46b53d0b, 0xbfeb52011f805c92, // -0.52067, -0.85376 + 0xbfe09e907417c5e1, 0xbfeb5889fe921405, // -0.51936, -0.85456 + 0xbfe093d2115ee018, 0xbfeb5f0ea611a532, // -0.51804, -0.85535 + 0xbfe089112032b08c, 0xbfeb658f14fdbc47, // -0.51673, -0.85615 + 0xbfe07e4da23bc102, 0xbfeb6c0b4a55ac17, // -0.51542, -0.85694 + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773 + 0xbfe068bf0691c028, 0xbfeb78f70449a34b, // -0.51279, -0.85852 + 0xbfe05df3ec31b8b6, 0xbfeb7f6686e792ea, // -0.51147, -0.8593 + 0xbfe053264bad0483, 0xbfeb85d1cbf52c02, // -0.51015, -0.86009 + 0xbfe0485626ae221a, 0xbfeb8c38d27504e9, // -0.50883, -0.86087 + 0xbfe03d837edff370, 0xbfeb929b996a5b7f, // -0.50751, -0.86165 + 0xbfe032ae55edbd95, 0xbfeb98fa1fd9155e, // -0.50619, -0.86242 + 0xbfe027d6ad83287e, 0xbfeb9f5464c5bffc, // -0.50486, -0.8632 + 0xbfe01cfc874c3eb7, 0xbfeba5aa673590d2, // -0.50354, -0.86397 + 0xbfe0121fe4f56d2c, 0xbfebabfc262e6586, // -0.50221, -0.86474 + 0xbfe00740c82b82e0, 0xbfebb249a0b6c40d, // -0.50089, -0.86551 + 0xbfdff8be6537615e, 0xbfebb892d5d5dad5, // -0.49956, -0.86628 + 0xbfdfe2f64be7120f, 0xbfebbed7c49380ea, // -0.49823, -0.86705 + 0xbfdfcd2947c1ff57, 0xbfebc5186bf8361d, // -0.4969, -0.86781 + 0xbfdfb7575c24d2de, 0xbfebcb54cb0d2327, // -0.49557, -0.86857 + 0xbfdfa1808c6cf7e0, 0xbfebd18ce0dc19d6, // -0.49423, -0.86933 + 0xbfdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // -0.4929, -0.87009 + 0xbfdf75c44e26a852, 0xbfebddf02cd2b983, // -0.49156, -0.87084 + 0xbfdf5fdee656cda3, 0xbfebe41b611154c1, // -0.49023, -0.8716 + 0xbfdf49f4a7e97729, 0xbfebea424837de6d, // -0.48889, -0.87235 + 0xbfdf3405963fd068, 0xbfebf064e15377dd, // -0.48755, -0.87309 + 0xbfdf1e11b4bbc35c, 0xbfebf6832b71ec5b, // -0.48621, -0.87384 + 0xbfdf081906bff7fd, 0xbfebfc9d25a1b147, // -0.48487, -0.87459 + 0xbfdef21b8fafd3b5, 0xbfec02b2cef1e641, // -0.48353, -0.87533 + 0xbfdedc1952ef78d5, 0xbfec08c426725549, // -0.48218, -0.87607 + 0xbfdec61253e3c61b, 0xbfec0ed12b3372e9, // -0.48084, -0.87681 + 0xbfdeb00695f25620, 0xbfec14d9dc465e58, // -0.47949, -0.87755 + 0xbfde99f61c817eda, 0xbfec1ade38bce19b, // -0.47815, -0.87828 + 0xbfde83e0eaf85113, 0xbfec20de3fa971b0, // -0.4768, -0.87901 + 0xbfde6dc704be97e2, 0xbfec26d9f01f2eaf, // -0.47545, -0.87974 + 0xbfde57a86d3cd824, 0xbfec2cd14931e3f1, // -0.4741, -0.88047 + 0xbfde418527dc4ffa, 0xbfec32c449f60831, // -0.47275, -0.8812 + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192 + 0xbfde1530a12779f4, 0xbfec3e9d3ee7d262, // -0.47004, -0.88264 + 0xbfddfeff66a941de, 0xbfec44833141c004, // -0.46869, -0.88336 + 0xbfdde8c98bf86bd6, 0xbfec4a64c7a5ac4c, // -0.46733, -0.88408 + 0xbfddd28f1481cc58, 0xbfec5042012b6907, // -0.46598, -0.8848 + 0xbfddbc5003b2edf8, 0xbfec561adceb743e, // -0.46462, -0.88551 + 0xbfdda60c5cfa10d8, 0xbfec5bef59fef85a, // -0.46326, -0.88622 + 0xbfdd8fc423c62a25, 0xbfec61bf777fcc48, // -0.4619, -0.88693 + 0xbfdd79775b86e389, 0xbfec678b3488739b, // -0.46054, -0.88764 + 0xbfdd632607ac9aa9, 0xbfec6d5290341eb2, // -0.45918, -0.88835 + 0xbfdd4cd02ba8609c, 0xbfec7315899eaad7, // -0.45781, -0.88905 + 0xbfdd3675caebf962, 0xbfec78d41fe4a267, // -0.45645, -0.88975 + 0xbfdd2016e8e9db5b, 0xbfec7e8e52233cf3, // -0.45508, -0.89045 + 0xbfdd09b389152ec1, 0xbfec84441f785f61, // -0.45372, -0.89115 + 0xbfdcf34baee1cd21, 0xbfec89f587029c13, // -0.45235, -0.89184 + 0xbfdcdcdf5dc440ce, 0xbfec8fa287e13305, // -0.45098, -0.89253 + 0xbfdcc66e9931c45d, 0xbfec954b213411f5, // -0.44961, -0.89322 + 0xbfdcaff964a0421d, 0xbfec9aef521bd480, // -0.44824, -0.89391 + 0xbfdc997fc3865388, 0xbfeca08f19b9c449, // -0.44687, -0.8946 + 0xbfdc8301b95b40c2, 0xbfeca62a772fd919, // -0.4455, -0.89528 + 0xbfdc6c7f4997000a, 0xbfecabc169a0b901, // -0.44412, -0.89597 + 0xbfdc55f877b23537, 0xbfecb153f02fb87d, // -0.44275, -0.89665 + 0xbfdc3f6d47263129, 0xbfecb6e20a00da99, // -0.44137, -0.89732 + 0xbfdc28ddbb6cf145, 0xbfecbc6bb638d10b, // -0.43999, -0.898 + 0xbfdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // -0.43862, -0.89867 + 0xbfdbfbb1a05e0edc, 0xbfecc771c2736c09, // -0.43724, -0.89935 + 0xbfdbe51517ffc0d9, 0xbfecccee20c2de9f, // -0.43586, -0.90002 + 0xbfdbce744262deee, 0xbfecd2660e12c1e6, // -0.43448, -0.90068 + 0xbfdbb7cf2304bd01, 0xbfecd7d9898b32f6, // -0.43309, -0.90135 + 0xbfdba125bd63583e, 0xbfecdd489254fe65, // -0.43171, -0.90201 + 0xbfdb8a7814fd5693, 0xbfece2b32799a060, // -0.43033, -0.90267 + 0xbfdb73c62d520624, 0xbfece819488344ce, // -0.42894, -0.90333 + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399 + 0xbfdb4655ae2bf757, 0xbfecf2d829f1b40e, // -0.42617, -0.90464 + 0xbfdb2f971db31972, 0xbfecf830e8ce467b, // -0.42478, -0.9053 + 0xbfdb18d45bf8aca6, 0xbfecfd852fff6ad4, // -0.42339, -0.90595 + 0xbfdb020d6c7f4009, 0xbfed02d4feb2bd92, // -0.422, -0.9066 + 0xbfdaeb4252ca07ab, 0xbfed082054168bac, // -0.42061, -0.90724 + 0xbfdad473125cdc08, 0xbfed0d672f59d2b9, // -0.41922, -0.90789 + 0xbfdabd9faebc3980, 0xbfed12a98fac410c, // -0.41782, -0.90853 + 0xbfdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // -0.41643, -0.90917 + 0xbfda8fec8bf5b166, 0xbfed1d20dc40c15c, // -0.41503, -0.90981 + 0xbfda790cd3dbf31a, 0xbfed2255c6e5a4e1, // -0.41364, -0.91044 + 0xbfda622906a70b63, 0xbfed2786335f52fc, // -0.41224, -0.91107 + 0xbfda4b4127dea1e4, 0xbfed2cb220e0ef9f, // -0.41084, -0.91171 + 0xbfda34553b0afee5, 0xbfed31d98e9e503a, // -0.40944, -0.91234 + 0xbfda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // -0.40804, -0.91296 + 0xbfda067145664d57, 0xbfed3c1ae79f2b4e, // -0.40664, -0.91359 + 0xbfd9ef7943a8ed8a, 0xbfed4134d14dc93a, // -0.40524, -0.91421 + 0xbfd9d87d4207b0ab, 0xbfed464a380e7242, // -0.40384, -0.91483 + 0xbfd9c17d440df9f2, 0xbfed4b5b1b187524, // -0.40243, -0.91545 + 0xbfd9aa794d47c9ee, 0xbfed506779a3d2d9, // -0.40103, -0.91606 + 0xbfd993716141bdfe, 0xbfed556f52e93eb1, // -0.39962, -0.91668 + 0xbfd97c6583890fc2, 0xbfed5a72a6221e73, // -0.39822, -0.91729 + 0xbfd96555b7ab948f, 0xbfed5f7172888a7f, // -0.39681, -0.9179 + 0xbfd94e420137bce3, 0xbfed646bb7574de5, // -0.3954, -0.91851 + 0xbfd9372a63bc93d7, 0xbfed696173c9e68b, // -0.39399, -0.91911 + 0xbfd9200ee2c9be97, 0xbfed6e52a71c8547, // -0.39258, -0.91972 + 0xbfd908ef81ef7bd1, 0xbfed733f508c0dff, // -0.39117, -0.92032 + 0xbfd8f1cc44bea329, 0xbfed78276f5617c6, // -0.38976, -0.92092 + 0xbfd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // -0.38835, -0.92151 + 0xbfd8c37a439f884f, 0xbfed81ea09f38b63, // -0.38693, -0.92211 + 0xbfd8ac4b86d5ed44, 0xbfed86c48445a450, // -0.38552, -0.9227 + 0xbfd89518fbff098e, 0xbfed8b9a70ef9cb4, // -0.3841, -0.92329 + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388 + 0xbfd866a88a792ea0, 0xbfed95389e50429b, // -0.38127, -0.92447 + 0xbfd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // -0.37985, -0.92505 + 0xbfd838290bb359c8, 0xbfed9ec48c26b1f3, // -0.37843, -0.92563 + 0xbfd820e3b04eaac4, 0xbfeda383a9668988, // -0.37701, -0.92621 + 0xbfd8099a9c5c362d, 0xbfeda83e348f613b, // -0.37559, -0.92679 + 0xbfd7f24dd37341e3, 0xbfedacf42ce68ab9, // -0.37416, -0.92736 + 0xbfd7dafd592ba621, 0xbfedb1a591b20c38, // -0.37274, -0.92794 + 0xbfd7c3a9311dcce7, 0xbfedb6526238a09b, // -0.37132, -0.92851 + 0xbfd7ac515ee2b172, 0xbfedbafa9dc1b78d, // -0.36989, -0.92907 + 0xbfd794f5e613dfae, 0xbfedbf9e4395759a, // -0.36847, -0.92964 + 0xbfd77d96ca4b73a6, 0xbfedc43d52fcb453, // -0.36704, -0.93021 + 0xbfd766340f2418f6, 0xbfedc8d7cb410260, // -0.36561, -0.93077 + 0xbfd74ecdb8390a3e, 0xbfedcd6dabaca3a5, // -0.36418, -0.93133 + 0xbfd73763c9261092, 0xbfedd1fef38a915a, // -0.36276, -0.93188 + 0xbfd71ff6458782ec, 0xbfedd68ba2267a25, // -0.36133, -0.93244 + 0xbfd7088530fa459e, 0xbfeddb13b6ccc23d, // -0.3599, -0.93299 + 0xbfd6f1108f1bc9c5, 0xbfeddf9730ca837b, // -0.35846, -0.93354 + 0xbfd6d998638a0cb5, 0xbfede4160f6d8d81, // -0.35703, -0.93409 + 0xbfd6c21cb1e39771, 0xbfede890520465ce, // -0.3556, -0.93464 + 0xbfd6aa9d7dc77e16, 0xbfeded05f7de47da, // -0.35416, -0.93518 + 0xbfd6931acad55f51, 0xbfedf177004b2534, // -0.35273, -0.93573 + 0xbfd67b949cad63ca, 0xbfedf5e36a9ba59c, // -0.35129, -0.93627 + 0xbfd6640af6f03d9e, 0xbfedfa4b3621271d, // -0.34986, -0.9368 + 0xbfd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // -0.34842, -0.93734 + 0xbfd634ed533be58e, 0xbfee030cee1435b8, // -0.34698, -0.93787 + 0xbfd61d595c88c203, 0xbfee0766d9280f54, // -0.34554, -0.9384 + 0xbfd605c1fcc88f63, 0xbfee0bbc22bd8349, // -0.3441, -0.93893 + 0xbfd5ee27379ea693, 0xbfee100cca2980ac, // -0.34266, -0.93946 + 0xbfd5d68910aee686, 0xbfee1458cec1ad83, // -0.34122, -0.93998 + 0xbfd5bee78b9db3b6, 0xbfee18a02fdc66d9, // -0.33978, -0.94051 + 0xbfd5a742ac0ff78d, 0xbfee1ce2ecd0c0d8, // -0.33833, -0.94103 + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154 + 0xbfd577eeec151e47, 0xbfee255a77a63bb8, // -0.33545, -0.94206 + 0xbfd5604012f467b4, 0xbfee298f4439197a, // -0.334, -0.94257 + 0xbfd5488dedeff3be, 0xbfee2dbf6a0911d9, // -0.33255, -0.94308 + 0xbfd530d880af3c24, 0xbfee31eae870ce25, // -0.33111, -0.94359 + 0xbfd5191fceda3c35, 0xbfee3611becbaf69, // -0.32966, -0.9441 + 0xbfd50163dc197047, 0xbfee3a33ec75ce85, // -0.32821, -0.9446 + 0xbfd4e9a4ac15d520, 0xbfee3e5170cbfc46, // -0.32676, -0.94511 + 0xbfd4d1e24278e76a, 0xbfee426a4b2bc17e, // -0.32531, -0.94561 + 0xbfd4ba1ca2eca31c, 0xbfee467e7af35f23, // -0.32386, -0.94611 + 0xbfd4a253d11b82f3, 0xbfee4a8dff81ce5e, // -0.32241, -0.9466 + 0xbfd48a87d0b07fd7, 0xbfee4e98d836c0af, // -0.32096, -0.94709 + 0xbfd472b8a5571054, 0xbfee529f04729ffc, // -0.3195, -0.94759 + 0xbfd45ae652bb2800, 0xbfee56a083968eb1, // -0.31805, -0.94807 + 0xbfd44310dc8936f0, 0xbfee5a9d550467d3, // -0.31659, -0.94856 + 0xbfd42b38466e2928, 0xbfee5e95781ebf1c, // -0.31514, -0.94905 + 0xbfd4135c94176602, 0xbfee6288ec48e112, // -0.31368, -0.94953 + 0xbfd3fb7dc932cfa4, 0xbfee6677b0e6d31e, // -0.31222, -0.95001 + 0xbfd3e39be96ec271, 0xbfee6a61c55d53a7, // -0.31077, -0.95049 + 0xbfd3cbb6f87a146e, 0xbfee6e472911da27, // -0.30931, -0.95096 + 0xbfd3b3cefa0414b7, 0xbfee7227db6a9744, // -0.30785, -0.95144 + 0xbfd39be3f1bc8aef, 0xbfee7603dbce74e9, // -0.30639, -0.95191 + 0xbfd383f5e353b6aa, 0xbfee79db29a5165a, // -0.30493, -0.95238 + 0xbfd36c04d27a4edf, 0xbfee7dadc456d850, // -0.30347, -0.95284 + 0xbfd35410c2e18152, 0xbfee817bab4cd10d, // -0.30201, -0.95331 + 0xbfd33c19b83af207, 0xbfee8544ddf0d075, // -0.30054, -0.95377 + 0xbfd3241fb638baaf, 0xbfee89095bad6025, // -0.29908, -0.95423 + 0xbfd30c22c08d6a13, 0xbfee8cc923edc388, // -0.29762, -0.95469 + 0xbfd2f422daec0386, 0xbfee9084361df7f3, // -0.29615, -0.95514 + 0xbfd2dc200907fe51, 0xbfee943a91aab4b4, // -0.29469, -0.95559 + 0xbfd2c41a4e954520, 0xbfee97ec36016b30, // -0.29322, -0.95605 + 0xbfd2ac11af483572, 0xbfee9b99229046f8, // -0.29175, -0.95649 + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694 + 0xbfd27bf7d0f2c346, 0xbfeea2e4d212c000, // -0.28882, -0.95738 + 0xbfd263e6995554ba, 0xbfeea68393e65800, // -0.28735, -0.95783 + 0xbfd24bd28bb37672, 0xbfeeaa1d9bb20af3, // -0.28588, -0.95827 + 0xbfd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // -0.28441, -0.9587 + 0xbfd21ba1fd3d2623, 0xbfeeb1437af9bb34, // -0.28294, -0.95914 + 0xbfd2038583d727bd, 0xbfeeb4cf515b8811, // -0.28146, -0.95957 + 0xbfd1eb6643499fbb, 0xbfeeb8566b810f2a, // -0.27999, -0.96 + 0xbfd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // -0.27852, -0.96043 + 0xbfd1bb1f7b999480, 0xbfeebf5668eaf2ef, // -0.27705, -0.96086 + 0xbfd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // -0.27557, -0.96128 + 0xbfd18acdc3f4873a, 0xbfeec6436ee60309, // -0.2741, -0.9617 + 0xbfd172a0d7765177, 0xbfeec9b2d3c3bf84, // -0.27262, -0.96212 + 0xbfd15a713a28b9d9, 0xbfeecd1d792c8f10, // -0.27115, -0.96254 + 0xbfd1423eefc69378, 0xbfeed0835e999009, // -0.26967, -0.96295 + 0xbfd12a09fc0b1b12, 0xbfeed3e483849c51, // -0.26819, -0.96337 + 0xbfd111d262b1f677, 0xbfeed740e7684963, // -0.26671, -0.96378 + 0xbfd0f998277733f7, 0xbfeeda9889bfe86a, // -0.26523, -0.96418 + 0xbfd0e15b4e1749cd, 0xbfeeddeb6a078651, // -0.26375, -0.96459 + 0xbfd0c91bda4f158d, 0xbfeee13987bbebdc, // -0.26227, -0.96499 + 0xbfd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // -0.26079, -0.96539 + 0xbfd09895327b465e, 0xbfeee7c77961dc9e, // -0.25931, -0.96579 + 0xbfd0804e05eb661e, 0xbfeeeb074c50a544, // -0.25783, -0.96619 + 0xbfd068044deab002, 0xbfeeee425aa6b09a, // -0.25635, -0.96658 + 0xbfd04fb80e37fdae, 0xbfeef178a3e473c2, // -0.25487, -0.96698 + 0xbfd037694a928cac, 0xbfeef4aa278b2032, // -0.25338, -0.96737 + 0xbfd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // -0.2519, -0.96775 + 0xbfd006c4466e54af, 0xbfeefafedc1ba8b7, // -0.25041, -0.96814 + 0xbfcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // -0.24893, -0.96852 + 0xbfcfac2abeff57ff, 0xbfef014074708ed3, // -0.24744, -0.9689 + 0xbfcf7b7480bd3801, 0xbfef045a14cf738c, // -0.24596, -0.96928 + 0xbfcf4ab9679c9f5c, 0xbfef076eecade0fa, // -0.24447, -0.96966 + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003 + 0xbfcee934c2d006c7, 0xbfef0d8a410379c5, // -0.24149, -0.9704 + 0xbfceb86b462de348, 0xbfef1090bc898f5f, // -0.24, -0.97077 + 0xbfce879d0cc0fdaf, 0xbfef13926dad024e, // -0.23851, -0.97114 + 0xbfce56ca1e101a1b, 0xbfef168f53f7205d, // -0.23702, -0.9715 + 0xbfce25f281a2b684, 0xbfef19876ef1f486, // -0.23553, -0.97187 + 0xbfcdf5163f01099a, 0xbfef1c7abe284708, // -0.23404, -0.97223 + 0xbfcdc4355db40195, 0xbfef1f6941259d7a, // -0.23255, -0.97258 + 0xbfcd934fe5454311, 0xbfef2252f7763ada, // -0.23106, -0.97294 + 0xbfcd6265dd3f27e3, 0xbfef2537e0a71f9f, // -0.22957, -0.97329 + 0xbfcd31774d2cbdee, 0xbfef2817fc4609ce, // -0.22807, -0.97364 + 0xbfcd00843c99c5f9, 0xbfef2af349e17507, // -0.22658, -0.97399 + 0xbfcccf8cb312b286, 0xbfef2dc9c9089a9d, // -0.22508, -0.97434 + 0xbfcc9e90b824a6a9, 0xbfef309b794b719f, // -0.22359, -0.97468 + 0xbfcc6d90535d74dc, 0xbfef33685a3aaef0, // -0.22209, -0.97503 + 0xbfcc3c8b8c4b9dd7, 0xbfef36306b67c556, // -0.2206, -0.97536 + 0xbfcc0b826a7e4f63, 0xbfef38f3ac64e589, // -0.2191, -0.9757 + 0xbfcbda74f5856330, 0xbfef3bb21cc4fe47, // -0.2176, -0.97604 + 0xbfcba96334f15dad, 0xbfef3e6bbc1bbc65, // -0.21611, -0.97637 + 0xbfcb784d30536cda, 0xbfef412089fd8adc, // -0.21461, -0.9767 + 0xbfcb4732ef3d6722, 0xbfef43d085ff92dd, // -0.21311, -0.97703 + 0xbfcb16147941ca2a, 0xbfef467bafb7bbe0, // -0.21161, -0.97735 + 0xbfcae4f1d5f3b9ab, 0xbfef492206bcabb4, // -0.21011, -0.97768 + 0xbfcab3cb0ce6fe44, 0xbfef4bc38aa5c694, // -0.20861, -0.978 + 0xbfca82a025b00451, 0xbfef4e603b0b2f2d, // -0.20711, -0.97832 + 0xbfca517127e3dabc, 0xbfef50f81785c6b9, // -0.20561, -0.97863 + 0xbfca203e1b1831da, 0xbfef538b1faf2d07, // -0.20411, -0.97895 + 0xbfc9ef0706e35a35, 0xbfef56195321c090, // -0.20261, -0.97926 + 0xbfc9bdcbf2dc4366, 0xbfef58a2b1789e84, // -0.2011, -0.97957 + 0xbfc98c8ce69a7aec, 0xbfef5b273a4fa2d9, // -0.1996, -0.97988 + 0xbfc95b49e9b62af9, 0xbfef5da6ed43685d, // -0.1981, -0.98018 + 0xbfc92a0303c8194f, 0xbfef6021c9f148c2, // -0.19659, -0.98048 + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079 + 0xbfc8c7699b34ca7e, 0xbfef6508fef47bd5, // -0.19359, -0.98108 + 0xbfc8961727c41804, 0xbfef677556883cee, // -0.19208, -0.98138 + 0xbfc864c0e9b2b6cf, 0xbfef69dcd652f5de, // -0.19057, -0.98167 + 0xbfc83366e89c64c5, 0xbfef6c3f7df5bbb7, // -0.18907, -0.98196 + 0xbfc802092c1d744b, 0xbfef6e9d4d1262ca, // -0.18756, -0.98225 + 0xbfc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // -0.18606, -0.98254 + 0xbfc79f429f59e11d, 0xbfef734a60446279, // -0.18455, -0.98282 + 0xbfc76dd9de50bf31, 0xbfef7599a3a12077, // -0.18304, -0.98311 + 0xbfc73c6d8055fe0a, 0xbfef77e40d068a90, // -0.18153, -0.98339 + 0xbfc70afd8d08c4ff, 0xbfef7a299c1a322a, // -0.18002, -0.98366 + 0xbfc6d98a0c08c8da, 0xbfef7c6a50826840, // -0.17851, -0.98394 + 0xbfc6a81304f64ab2, 0xbfef7ea629e63d6e, // -0.177, -0.98421 + 0xbfc676987f7216b8, 0xbfef80dd27ed8204, // -0.17549, -0.98448 + 0xbfc6451a831d830d, 0xbfef830f4a40c60c, // -0.17398, -0.98475 + 0xbfc61399179a6e94, 0xbfef853c9089595e, // -0.17247, -0.98501 + 0xbfc5e214448b3fc6, 0xbfef8764fa714ba9, // -0.17096, -0.98528 + 0xbfc5b08c1192e381, 0xbfef898887a36c84, // -0.16945, -0.98554 + 0xbfc57f008654cbde, 0xbfef8ba737cb4b78, // -0.16794, -0.9858 + 0xbfc54d71aa74ef02, 0xbfef8dc10a95380d, // -0.16643, -0.98605 + 0xbfc51bdf8597c5f2, 0xbfef8fd5ffae41db, // -0.16491, -0.98631 + 0xbfc4ea4a1f624b61, 0xbfef91e616c43891, // -0.1634, -0.98656 + 0xbfc4b8b17f79fa88, 0xbfef93f14f85ac08, // -0.16189, -0.98681 + 0xbfc48715ad84cdf5, 0xbfef95f7a9a1ec47, // -0.16037, -0.98706 + 0xbfc45576b1293e5a, 0xbfef97f924c9099b, // -0.15886, -0.9873 + 0xbfc423d4920e4166, 0xbfef99f5c0abd496, // -0.15734, -0.98754 + 0xbfc3f22f57db4893, 0xbfef9bed7cfbde29, // -0.15583, -0.98778 + 0xbfc3c0870a383ff6, 0xbfef9de0596b77a3, // -0.15431, -0.98802 + 0xbfc38edbb0cd8d14, 0xbfef9fce55adb2c8, // -0.1528, -0.98826 + 0xbfc35d2d53440db2, 0xbfefa1b7717661d5, // -0.15128, -0.98849 + 0xbfc32b7bf94516a7, 0xbfefa39bac7a1791, // -0.14976, -0.98872 + 0xbfc2f9c7aa7a72af, 0xbfefa57b066e2754, // -0.14825, -0.98895 + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918 + 0xbfc296564d2b953e, 0xbfefa92b1600657c, // -0.14521, -0.9894 + 0xbfc264994dfd340a, 0xbfefaafbcb0cfddc, // -0.1437, -0.98962 + 0xbfc232d978aed413, 0xbfefacc79de6c44f, // -0.14218, -0.98984 + 0xbfc20116d4ec7bce, 0xbfefae8e8e46cfbb, // -0.14066, -0.99006 + 0xbfc1cf516a62a077, 0xbfefb0509be6f7db, // -0.13914, -0.99027 + 0xbfc19d8940be24e7, 0xbfefb20dc681d54d, // -0.13762, -0.99049 + 0xbfc16bbe5fac5865, 0xbfefb3c60dd2c199, // -0.1361, -0.9907 + 0xbfc139f0cedaf576, 0xbfefb5797195d741, // -0.13458, -0.9909 + 0xbfc1082095f820b0, 0xbfefb727f187f1c7, // -0.13306, -0.99111 + 0xbfc0d64dbcb26786, 0xbfefb8d18d66adb7, // -0.13154, -0.99131 + 0xbfc0a4784ab8bf1d, 0xbfefba7644f068b5, // -0.13002, -0.99151 + 0xbfc072a047ba831d, 0xbfefbc1617e44186, // -0.1285, -0.99171 + 0xbfc040c5bb67747e, 0xbfefbdb106021816, // -0.12698, -0.99191 + 0xbfc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // -0.12545, -0.9921 + 0xbfbfba124b07ad85, 0xbfefc0d832bf043a, // -0.12393, -0.99229 + 0xbfbf564e56a9730e, 0xbfefc26470e19fd3, // -0.12241, -0.99248 + 0xbfbef2858d27561b, 0xbfefc3ebc935454c, // -0.12089, -0.99267 + 0xbfbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // -0.11937, -0.99285 + 0xbfbe2ae5b8457f77, 0xbfefc6ebc77f0887, // -0.11784, -0.99303 + 0xbfbdc70ecbae9fc8, 0xbfefc8646cfeb721, // -0.11632, -0.99321 + 0xbfbd633347858ce4, 0xbfefc9d82bc2915e, // -0.11479, -0.99339 + 0xbfbcff533b307dc1, 0xbfefcb4703914354, // -0.11327, -0.99356 + 0xbfbc9b6eb6165c42, 0xbfefccb0f4323aa3, // -0.11175, -0.99374 + 0xbfbc3785c79ec2d5, 0xbfefce15fd6da67b, // -0.11022, -0.99391 + 0xbfbbd3987f31fa0e, 0xbfefcf761f0c77a3, // -0.1087, -0.99407 + 0xbfbb6fa6ec38f64c, 0xbfefd0d158d86087, // -0.10717, -0.99424 + 0xbfbb0bb11e1d5559, 0xbfefd227aa9bd53b, // -0.10565, -0.9944 + 0xbfbaa7b724495c04, 0xbfefd37914220b84, // -0.10412, -0.99456 + 0xbfba43b90e27f3c4, 0xbfefd4c59536fae4, // -0.1026, -0.99472 + 0xbfb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // -0.10107, -0.99488 + 0xbfb97bb0caaba56f, 0xbfefd74fdd40abbf, // -0.099544, -0.99503 + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, // -0.098017, -0.99518 + 0xbfb8b398cf0c38e0, 0xbfefd9c68127c78c, // -0.09649, -0.99533 + 0xbfb84f8712c130a0, 0xbfefdafa7514538c, // -0.094963, -0.99548 + 0xbfb7eb7196b72ee4, 0xbfefdc297f674ba9, // -0.093436, -0.99563 + 0xbfb787586a5d5b21, 0xbfefdd539ff1f456, // -0.091909, -0.99577 + 0xbfb7233b9d236e71, 0xbfefde78d68653fd, // -0.090381, -0.99591 + 0xbfb6bf1b3e79b129, 0xbfefdf9922f73307, // -0.088854, -0.99604 + 0xbfb65af75dd0f87b, 0xbfefe0b485181be3, // -0.087326, -0.99618 + 0xbfb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // -0.085797, -0.99631 + 0xbfb592a554489bc8, 0xbfefe2dc89bbff08, // -0.084269, -0.99644 + 0xbfb52e774a4d4d0a, 0xbfefe3e92be9d886, // -0.08274, -0.99657 + 0xbfb4ca45fc1ba8b6, 0xbfefe4f0e31d7a4a, // -0.081211, -0.9967 + 0xbfb4661179272096, 0xbfefe5f3af2e3940, // -0.079682, -0.99682 + 0xbfb401d9d0e3a507, 0xbfefe6f18ff42c84, // -0.078153, -0.99694 + 0xbfb39d9f12c5a299, 0xbfefe7ea85482d60, // -0.076624, -0.99706 + 0xbfb339614e41ffa5, 0xbfefe8de8f03d75c, // -0.075094, -0.99718 + 0xbfb2d52092ce19f6, 0xbfefe9cdad01883a, // -0.073565, -0.99729 + 0xbfb270dcefdfc45b, 0xbfefeab7df1c6005, // -0.072035, -0.9974 + 0xbfb20c9674ed444c, 0xbfefeb9d2530410f, // -0.070505, -0.99751 + 0xbfb1a84d316d4f8a, 0xbfefec7d7f19cffc, // -0.068974, -0.99762 + 0xbfb1440134d709b2, 0xbfefed58ecb673c4, // -0.067444, -0.99772 + 0xbfb0dfb28ea201e6, 0xbfefee2f6de455ba, // -0.065913, -0.99783 + 0xbfb07b614e463064, 0xbfefef0102826191, // -0.064383, -0.99793 + 0xbfb0170d833bf421, 0xbfefefcdaa704562, // -0.062852, -0.99802 + 0xbfaf656e79f820e0, 0xbfeff095658e71ad, // -0.061321, -0.99812 + 0xbfae9cbd15ff5527, 0xbfeff15833be1965, // -0.05979, -0.99821 + 0xbfadd406f9808ec8, 0xbfeff21614e131ed, // -0.058258, -0.9983 + 0xbfad0b4c436f91d0, 0xbfeff2cf08da7321, // -0.056727, -0.99839 + 0xbfac428d12c0d7e3, 0xbfeff3830f8d575c, // -0.055195, -0.99848 + 0xbfab79c986698b78, 0xbfeff43228de1b77, // -0.053664, -0.99856 + 0xbfaab101bd5f8317, 0xbfeff4dc54b1bed3, // -0.052132, -0.99864 + 0xbfa9e835d6993c87, 0xbfeff58192ee0358, // -0.0506, -0.99872 + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, // -0.049068, -0.9988 + 0xbfa856922bb513c1, 0xbfeff6bd463b444d, // -0.047535, -0.99887 + 0xbfa78dbaa5874685, 0xbfeff753bb1b9164, // -0.046003, -0.99894 + 0xbfa6c4df7d7d5b84, 0xbfeff7e5420320f9, // -0.044471, -0.99901 + 0xbfa5fc00d290cd43, 0xbfeff871dadb81df, // -0.042938, -0.99908 + 0xbfa5331ec3bba0eb, 0xbfeff8f9858f058b, // -0.041406, -0.99914 + 0xbfa46a396ff86179, 0xbfeff97c4208c014, // -0.039873, -0.9992 + 0xbfa3a150f6421afc, 0xbfeff9fa10348837, // -0.03834, -0.99926 + 0xbfa2d865759455cd, 0xbfeffa72effef75d, // -0.036807, -0.99932 + 0xbfa20f770ceb11c6, 0xbfeffae6e1556998, // -0.035274, -0.99938 + 0xbfa14685db42c17e, 0xbfeffb55e425fdae, // -0.033741, -0.99943 + 0xbfa07d91ff984580, 0xbfeffbbff85f9515, // -0.032208, -0.99948 + 0xbf9f693731d1cf01, 0xbfeffc251df1d3f8, // -0.030675, -0.99953 + 0xbf9dd7458c64ab39, 0xbfeffc8554cd213a, // -0.029142, -0.99958 + 0xbf9c454f4ce53b1c, 0xbfeffce09ce2a679, // -0.027608, -0.99962 + 0xbf9ab354b1504fca, 0xbfeffd36f624500c, // -0.026075, -0.99966 + 0xbf992155f7a3667e, 0xbfeffd886084cd0d, // -0.024541, -0.9997 + 0xbf978f535ddc9f03, 0xbfeffdd4dbf78f52, // -0.023008, -0.99974 + 0xbf95fd4d21fab226, 0xbfeffe1c6870cb77, // -0.021474, -0.99977 + 0xbf946b4381fce81c, 0xbfeffe5f05e578db, // -0.01994, -0.9998 + 0xbf92d936bbe30efd, 0xbfeffe9cb44b51a1, // -0.018407, -0.99983 + 0xbf9147270dad7132, 0xbfeffed57398d2b7, // -0.016873, -0.99986 + 0xbf8f6a296ab997ca, 0xbfefff0943c53bd1, // -0.015339, -0.99988 + 0xbf8c45ffe1e48ad9, 0xbfefff3824c88f6f, // -0.013805, -0.9999 + 0xbf8921d1fcdec784, 0xbfefff62169b92db, // -0.012272, -0.99992 + 0xbf85fda037ac05e0, 0xbfefff871937ce2f, // -0.010738, -0.99994 + 0xbf82d96b0e509703, 0xbfefffa72c978c4f, //-0.0092038, -0.99996 + 0xbf7f6a65f9a2a3c5, 0xbfefffc250b5daef, //-0.0076698, -0.99997 + 0xbf7921f0fe670071, 0xbfefffd8858e8a92, //-0.0061359, -0.99998 + 0xbf72d97822f996bc, 0xbfefffe9cb1e2e8d, //-0.0046019, -0.99999 + 0xbf6921f8becca4ba, 0xbfeffff621621d02, // -0.003068, -1 + 0xbf5921faaee6472d, 0xbfeffffd88586ee6, // -0.001534, -1 + 0x0000000000000000, 0xbff0000000000000, // 0, -1 + 0x3f5921faaee6472d, 0xbfeffffd88586ee6, // 0.001534, -1 + 0x3f6921f8becca4ba, 0xbfeffff621621d02, // 0.003068, -1 + 0x3f72d97822f996bc, 0xbfefffe9cb1e2e8d, // 0.0046019, -0.99999 + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, // 0.0061359, -0.99998 + 0x3f7f6a65f9a2a3c5, 0xbfefffc250b5daef, // 0.0076698, -0.99997 + 0x3f82d96b0e509703, 0xbfefffa72c978c4f, // 0.0092038, -0.99996 + 0x3f85fda037ac05e0, 0xbfefff871937ce2f, // 0.010738, -0.99994 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f8c45ffe1e48ad9, 0xbfefff3824c88f6f, // 0.013805, -0.9999 + 0x3f8f6a296ab997ca, 0xbfefff0943c53bd1, // 0.015339, -0.99988 + 0x3f9147270dad7132, 0xbfeffed57398d2b7, // 0.016873, -0.99986 + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983 + 0x3f946b4381fce81c, 0xbfeffe5f05e578db, // 0.01994, -0.9998 + 0x3f95fd4d21fab226, 0xbfeffe1c6870cb77, // 0.021474, -0.99977 + 0x3f978f535ddc9f03, 0xbfeffdd4dbf78f52, // 0.023008, -0.99974 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3f9ab354b1504fca, 0xbfeffd36f624500c, // 0.026075, -0.99966 + 0x3f9c454f4ce53b1c, 0xbfeffce09ce2a679, // 0.027608, -0.99962 + 0x3f9dd7458c64ab39, 0xbfeffc8554cd213a, // 0.029142, -0.99958 + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953 + 0x3fa07d91ff984580, 0xbfeffbbff85f9515, // 0.032208, -0.99948 + 0x3fa14685db42c17e, 0xbfeffb55e425fdae, // 0.033741, -0.99943 + 0x3fa20f770ceb11c6, 0xbfeffae6e1556998, // 0.035274, -0.99938 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa3a150f6421afc, 0xbfeff9fa10348837, // 0.03834, -0.99926 + 0x3fa46a396ff86179, 0xbfeff97c4208c014, // 0.039873, -0.9992 + 0x3fa5331ec3bba0eb, 0xbfeff8f9858f058b, // 0.041406, -0.99914 + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908 + 0x3fa6c4df7d7d5b84, 0xbfeff7e5420320f9, // 0.044471, -0.99901 + 0x3fa78dbaa5874685, 0xbfeff753bb1b9164, // 0.046003, -0.99894 + 0x3fa856922bb513c1, 0xbfeff6bd463b444d, // 0.047535, -0.99887 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3fa9e835d6993c87, 0xbfeff58192ee0358, // 0.0506, -0.99872 + 0x3faab101bd5f8317, 0xbfeff4dc54b1bed3, // 0.052132, -0.99864 + 0x3fab79c986698b78, 0xbfeff43228de1b77, // 0.053664, -0.99856 + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848 + 0x3fad0b4c436f91d0, 0xbfeff2cf08da7321, // 0.056727, -0.99839 + 0x3fadd406f9808ec8, 0xbfeff21614e131ed, // 0.058258, -0.9983 + 0x3fae9cbd15ff5527, 0xbfeff15833be1965, // 0.05979, -0.99821 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fb0170d833bf421, 0xbfefefcdaa704562, // 0.062852, -0.99802 + 0x3fb07b614e463064, 0xbfefef0102826191, // 0.064383, -0.99793 + 0x3fb0dfb28ea201e6, 0xbfefee2f6de455ba, // 0.065913, -0.99783 + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772 + 0x3fb1a84d316d4f8a, 0xbfefec7d7f19cffc, // 0.068974, -0.99762 + 0x3fb20c9674ed444c, 0xbfefeb9d2530410f, // 0.070505, -0.99751 + 0x3fb270dcefdfc45b, 0xbfefeab7df1c6005, // 0.072035, -0.9974 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb339614e41ffa5, 0xbfefe8de8f03d75c, // 0.075094, -0.99718 + 0x3fb39d9f12c5a299, 0xbfefe7ea85482d60, // 0.076624, -0.99706 + 0x3fb401d9d0e3a507, 0xbfefe6f18ff42c84, // 0.078153, -0.99694 + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682 + 0x3fb4ca45fc1ba8b6, 0xbfefe4f0e31d7a4a, // 0.081211, -0.9967 + 0x3fb52e774a4d4d0a, 0xbfefe3e92be9d886, // 0.08274, -0.99657 + 0x3fb592a554489bc8, 0xbfefe2dc89bbff08, // 0.084269, -0.99644 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb65af75dd0f87b, 0xbfefe0b485181be3, // 0.087326, -0.99618 + 0x3fb6bf1b3e79b129, 0xbfefdf9922f73307, // 0.088854, -0.99604 + 0x3fb7233b9d236e71, 0xbfefde78d68653fd, // 0.090381, -0.99591 + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577 + 0x3fb7eb7196b72ee4, 0xbfefdc297f674ba9, // 0.093436, -0.99563 + 0x3fb84f8712c130a0, 0xbfefdafa7514538c, // 0.094963, -0.99548 + 0x3fb8b398cf0c38e0, 0xbfefd9c68127c78c, // 0.09649, -0.99533 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fb97bb0caaba56f, 0xbfefd74fdd40abbf, // 0.099544, -0.99503 + 0x3fb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // 0.10107, -0.99488 + 0x3fba43b90e27f3c4, 0xbfefd4c59536fae4, // 0.1026, -0.99472 + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456 + 0x3fbb0bb11e1d5559, 0xbfefd227aa9bd53b, // 0.10565, -0.9944 + 0x3fbb6fa6ec38f64c, 0xbfefd0d158d86087, // 0.10717, -0.99424 + 0x3fbbd3987f31fa0e, 0xbfefcf761f0c77a3, // 0.1087, -0.99407 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbc9b6eb6165c42, 0xbfefccb0f4323aa3, // 0.11175, -0.99374 + 0x3fbcff533b307dc1, 0xbfefcb4703914354, // 0.11327, -0.99356 + 0x3fbd633347858ce4, 0xbfefc9d82bc2915e, // 0.11479, -0.99339 + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321 + 0x3fbe2ae5b8457f77, 0xbfefc6ebc77f0887, // 0.11784, -0.99303 + 0x3fbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // 0.11937, -0.99285 + 0x3fbef2858d27561b, 0xbfefc3ebc935454c, // 0.12089, -0.99267 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fbfba124b07ad85, 0xbfefc0d832bf043a, // 0.12393, -0.99229 + 0x3fc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // 0.12545, -0.9921 + 0x3fc040c5bb67747e, 0xbfefbdb106021816, // 0.12698, -0.99191 + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171 + 0x3fc0a4784ab8bf1d, 0xbfefba7644f068b5, // 0.13002, -0.99151 + 0x3fc0d64dbcb26786, 0xbfefb8d18d66adb7, // 0.13154, -0.99131 + 0x3fc1082095f820b0, 0xbfefb727f187f1c7, // 0.13306, -0.99111 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc16bbe5fac5865, 0xbfefb3c60dd2c199, // 0.1361, -0.9907 + 0x3fc19d8940be24e7, 0xbfefb20dc681d54d, // 0.13762, -0.99049 + 0x3fc1cf516a62a077, 0xbfefb0509be6f7db, // 0.13914, -0.99027 + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006 + 0x3fc232d978aed413, 0xbfefacc79de6c44f, // 0.14218, -0.98984 + 0x3fc264994dfd340a, 0xbfefaafbcb0cfddc, // 0.1437, -0.98962 + 0x3fc296564d2b953e, 0xbfefa92b1600657c, // 0.14521, -0.9894 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc2f9c7aa7a72af, 0xbfefa57b066e2754, // 0.14825, -0.98895 + 0x3fc32b7bf94516a7, 0xbfefa39bac7a1791, // 0.14976, -0.98872 + 0x3fc35d2d53440db2, 0xbfefa1b7717661d5, // 0.15128, -0.98849 + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826 + 0x3fc3c0870a383ff6, 0xbfef9de0596b77a3, // 0.15431, -0.98802 + 0x3fc3f22f57db4893, 0xbfef9bed7cfbde29, // 0.15583, -0.98778 + 0x3fc423d4920e4166, 0xbfef99f5c0abd496, // 0.15734, -0.98754 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc48715ad84cdf5, 0xbfef95f7a9a1ec47, // 0.16037, -0.98706 + 0x3fc4b8b17f79fa88, 0xbfef93f14f85ac08, // 0.16189, -0.98681 + 0x3fc4ea4a1f624b61, 0xbfef91e616c43891, // 0.1634, -0.98656 + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631 + 0x3fc54d71aa74ef02, 0xbfef8dc10a95380d, // 0.16643, -0.98605 + 0x3fc57f008654cbde, 0xbfef8ba737cb4b78, // 0.16794, -0.9858 + 0x3fc5b08c1192e381, 0xbfef898887a36c84, // 0.16945, -0.98554 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc61399179a6e94, 0xbfef853c9089595e, // 0.17247, -0.98501 + 0x3fc6451a831d830d, 0xbfef830f4a40c60c, // 0.17398, -0.98475 + 0x3fc676987f7216b8, 0xbfef80dd27ed8204, // 0.17549, -0.98448 + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421 + 0x3fc6d98a0c08c8da, 0xbfef7c6a50826840, // 0.17851, -0.98394 + 0x3fc70afd8d08c4ff, 0xbfef7a299c1a322a, // 0.18002, -0.98366 + 0x3fc73c6d8055fe0a, 0xbfef77e40d068a90, // 0.18153, -0.98339 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc79f429f59e11d, 0xbfef734a60446279, // 0.18455, -0.98282 + 0x3fc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // 0.18606, -0.98254 + 0x3fc802092c1d744b, 0xbfef6e9d4d1262ca, // 0.18756, -0.98225 + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196 + 0x3fc864c0e9b2b6cf, 0xbfef69dcd652f5de, // 0.19057, -0.98167 + 0x3fc8961727c41804, 0xbfef677556883cee, // 0.19208, -0.98138 + 0x3fc8c7699b34ca7e, 0xbfef6508fef47bd5, // 0.19359, -0.98108 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc92a0303c8194f, 0xbfef6021c9f148c2, // 0.19659, -0.98048 + 0x3fc95b49e9b62af9, 0xbfef5da6ed43685d, // 0.1981, -0.98018 + 0x3fc98c8ce69a7aec, 0xbfef5b273a4fa2d9, // 0.1996, -0.97988 + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957 + 0x3fc9ef0706e35a35, 0xbfef56195321c090, // 0.20261, -0.97926 + 0x3fca203e1b1831da, 0xbfef538b1faf2d07, // 0.20411, -0.97895 + 0x3fca517127e3dabc, 0xbfef50f81785c6b9, // 0.20561, -0.97863 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fcab3cb0ce6fe44, 0xbfef4bc38aa5c694, // 0.20861, -0.978 + 0x3fcae4f1d5f3b9ab, 0xbfef492206bcabb4, // 0.21011, -0.97768 + 0x3fcb16147941ca2a, 0xbfef467bafb7bbe0, // 0.21161, -0.97735 + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703 + 0x3fcb784d30536cda, 0xbfef412089fd8adc, // 0.21461, -0.9767 + 0x3fcba96334f15dad, 0xbfef3e6bbc1bbc65, // 0.21611, -0.97637 + 0x3fcbda74f5856330, 0xbfef3bb21cc4fe47, // 0.2176, -0.97604 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcc3c8b8c4b9dd7, 0xbfef36306b67c556, // 0.2206, -0.97536 + 0x3fcc6d90535d74dc, 0xbfef33685a3aaef0, // 0.22209, -0.97503 + 0x3fcc9e90b824a6a9, 0xbfef309b794b719f, // 0.22359, -0.97468 + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434 + 0x3fcd00843c99c5f9, 0xbfef2af349e17507, // 0.22658, -0.97399 + 0x3fcd31774d2cbdee, 0xbfef2817fc4609ce, // 0.22807, -0.97364 + 0x3fcd6265dd3f27e3, 0xbfef2537e0a71f9f, // 0.22957, -0.97329 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fcdc4355db40195, 0xbfef1f6941259d7a, // 0.23255, -0.97258 + 0x3fcdf5163f01099a, 0xbfef1c7abe284708, // 0.23404, -0.97223 + 0x3fce25f281a2b684, 0xbfef19876ef1f486, // 0.23553, -0.97187 + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715 + 0x3fce879d0cc0fdaf, 0xbfef13926dad024e, // 0.23851, -0.97114 + 0x3fceb86b462de348, 0xbfef1090bc898f5f, // 0.24, -0.97077 + 0x3fcee934c2d006c7, 0xbfef0d8a410379c5, // 0.24149, -0.9704 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fcf4ab9679c9f5c, 0xbfef076eecade0fa, // 0.24447, -0.96966 + 0x3fcf7b7480bd3801, 0xbfef045a14cf738c, // 0.24596, -0.96928 + 0x3fcfac2abeff57ff, 0xbfef014074708ed3, // 0.24744, -0.9689 + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852 + 0x3fd006c4466e54af, 0xbfeefafedc1ba8b7, // 0.25041, -0.96814 + 0x3fd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // 0.2519, -0.96775 + 0x3fd037694a928cac, 0xbfeef4aa278b2032, // 0.25338, -0.96737 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd068044deab002, 0xbfeeee425aa6b09a, // 0.25635, -0.96658 + 0x3fd0804e05eb661e, 0xbfeeeb074c50a544, // 0.25783, -0.96619 + 0x3fd09895327b465e, 0xbfeee7c77961dc9e, // 0.25931, -0.96579 + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539 + 0x3fd0c91bda4f158d, 0xbfeee13987bbebdc, // 0.26227, -0.96499 + 0x3fd0e15b4e1749cd, 0xbfeeddeb6a078651, // 0.26375, -0.96459 + 0x3fd0f998277733f7, 0xbfeeda9889bfe86a, // 0.26523, -0.96418 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd12a09fc0b1b12, 0xbfeed3e483849c51, // 0.26819, -0.96337 + 0x3fd1423eefc69378, 0xbfeed0835e999009, // 0.26967, -0.96295 + 0x3fd15a713a28b9d9, 0xbfeecd1d792c8f10, // 0.27115, -0.96254 + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212 + 0x3fd18acdc3f4873a, 0xbfeec6436ee60309, // 0.2741, -0.9617 + 0x3fd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // 0.27557, -0.96128 + 0x3fd1bb1f7b999480, 0xbfeebf5668eaf2ef, // 0.27705, -0.96086 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd1eb6643499fbb, 0xbfeeb8566b810f2a, // 0.27999, -0.96 + 0x3fd2038583d727bd, 0xbfeeb4cf515b8811, // 0.28146, -0.95957 + 0x3fd21ba1fd3d2623, 0xbfeeb1437af9bb34, // 0.28294, -0.95914 + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587 + 0x3fd24bd28bb37672, 0xbfeeaa1d9bb20af3, // 0.28588, -0.95827 + 0x3fd263e6995554ba, 0xbfeea68393e65800, // 0.28735, -0.95783 + 0x3fd27bf7d0f2c346, 0xbfeea2e4d212c000, // 0.28882, -0.95738 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd2ac11af483572, 0xbfee9b99229046f8, // 0.29175, -0.95649 + 0x3fd2c41a4e954520, 0xbfee97ec36016b30, // 0.29322, -0.95605 + 0x3fd2dc200907fe51, 0xbfee943a91aab4b4, // 0.29469, -0.95559 + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514 + 0x3fd30c22c08d6a13, 0xbfee8cc923edc388, // 0.29762, -0.95469 + 0x3fd3241fb638baaf, 0xbfee89095bad6025, // 0.29908, -0.95423 + 0x3fd33c19b83af207, 0xbfee8544ddf0d075, // 0.30054, -0.95377 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd36c04d27a4edf, 0xbfee7dadc456d850, // 0.30347, -0.95284 + 0x3fd383f5e353b6aa, 0xbfee79db29a5165a, // 0.30493, -0.95238 + 0x3fd39be3f1bc8aef, 0xbfee7603dbce74e9, // 0.30639, -0.95191 + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144 + 0x3fd3cbb6f87a146e, 0xbfee6e472911da27, // 0.30931, -0.95096 + 0x3fd3e39be96ec271, 0xbfee6a61c55d53a7, // 0.31077, -0.95049 + 0x3fd3fb7dc932cfa4, 0xbfee6677b0e6d31e, // 0.31222, -0.95001 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd42b38466e2928, 0xbfee5e95781ebf1c, // 0.31514, -0.94905 + 0x3fd44310dc8936f0, 0xbfee5a9d550467d3, // 0.31659, -0.94856 + 0x3fd45ae652bb2800, 0xbfee56a083968eb1, // 0.31805, -0.94807 + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759 + 0x3fd48a87d0b07fd7, 0xbfee4e98d836c0af, // 0.32096, -0.94709 + 0x3fd4a253d11b82f3, 0xbfee4a8dff81ce5e, // 0.32241, -0.9466 + 0x3fd4ba1ca2eca31c, 0xbfee467e7af35f23, // 0.32386, -0.94611 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd4e9a4ac15d520, 0xbfee3e5170cbfc46, // 0.32676, -0.94511 + 0x3fd50163dc197047, 0xbfee3a33ec75ce85, // 0.32821, -0.9446 + 0x3fd5191fceda3c35, 0xbfee3611becbaf69, // 0.32966, -0.9441 + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359 + 0x3fd5488dedeff3be, 0xbfee2dbf6a0911d9, // 0.33255, -0.94308 + 0x3fd5604012f467b4, 0xbfee298f4439197a, // 0.334, -0.94257 + 0x3fd577eeec151e47, 0xbfee255a77a63bb8, // 0.33545, -0.94206 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd5a742ac0ff78d, 0xbfee1ce2ecd0c0d8, // 0.33833, -0.94103 + 0x3fd5bee78b9db3b6, 0xbfee18a02fdc66d9, // 0.33978, -0.94051 + 0x3fd5d68910aee686, 0xbfee1458cec1ad83, // 0.34122, -0.93998 + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946 + 0x3fd605c1fcc88f63, 0xbfee0bbc22bd8349, // 0.3441, -0.93893 + 0x3fd61d595c88c203, 0xbfee0766d9280f54, // 0.34554, -0.9384 + 0x3fd634ed533be58e, 0xbfee030cee1435b8, // 0.34698, -0.93787 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd6640af6f03d9e, 0xbfedfa4b3621271d, // 0.34986, -0.9368 + 0x3fd67b949cad63ca, 0xbfedf5e36a9ba59c, // 0.35129, -0.93627 + 0x3fd6931acad55f51, 0xbfedf177004b2534, // 0.35273, -0.93573 + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518 + 0x3fd6c21cb1e39771, 0xbfede890520465ce, // 0.3556, -0.93464 + 0x3fd6d998638a0cb5, 0xbfede4160f6d8d81, // 0.35703, -0.93409 + 0x3fd6f1108f1bc9c5, 0xbfeddf9730ca837b, // 0.35846, -0.93354 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd71ff6458782ec, 0xbfedd68ba2267a25, // 0.36133, -0.93244 + 0x3fd73763c9261092, 0xbfedd1fef38a915a, // 0.36276, -0.93188 + 0x3fd74ecdb8390a3e, 0xbfedcd6dabaca3a5, // 0.36418, -0.93133 + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077 + 0x3fd77d96ca4b73a6, 0xbfedc43d52fcb453, // 0.36704, -0.93021 + 0x3fd794f5e613dfae, 0xbfedbf9e4395759a, // 0.36847, -0.92964 + 0x3fd7ac515ee2b172, 0xbfedbafa9dc1b78d, // 0.36989, -0.92907 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd7dafd592ba621, 0xbfedb1a591b20c38, // 0.37274, -0.92794 + 0x3fd7f24dd37341e3, 0xbfedacf42ce68ab9, // 0.37416, -0.92736 + 0x3fd8099a9c5c362d, 0xbfeda83e348f613b, // 0.37559, -0.92679 + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621 + 0x3fd838290bb359c8, 0xbfed9ec48c26b1f3, // 0.37843, -0.92563 + 0x3fd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // 0.37985, -0.92505 + 0x3fd866a88a792ea0, 0xbfed95389e50429b, // 0.38127, -0.92447 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd89518fbff098e, 0xbfed8b9a70ef9cb4, // 0.3841, -0.92329 + 0x3fd8ac4b86d5ed44, 0xbfed86c48445a450, // 0.38552, -0.9227 + 0x3fd8c37a439f884f, 0xbfed81ea09f38b63, // 0.38693, -0.92211 + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151 + 0x3fd8f1cc44bea329, 0xbfed78276f5617c6, // 0.38976, -0.92092 + 0x3fd908ef81ef7bd1, 0xbfed733f508c0dff, // 0.39117, -0.92032 + 0x3fd9200ee2c9be97, 0xbfed6e52a71c8547, // 0.39258, -0.91972 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd94e420137bce3, 0xbfed646bb7574de5, // 0.3954, -0.91851 + 0x3fd96555b7ab948f, 0xbfed5f7172888a7f, // 0.39681, -0.9179 + 0x3fd97c6583890fc2, 0xbfed5a72a6221e73, // 0.39822, -0.91729 + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668 + 0x3fd9aa794d47c9ee, 0xbfed506779a3d2d9, // 0.40103, -0.91606 + 0x3fd9c17d440df9f2, 0xbfed4b5b1b187524, // 0.40243, -0.91545 + 0x3fd9d87d4207b0ab, 0xbfed464a380e7242, // 0.40384, -0.91483 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fda067145664d57, 0xbfed3c1ae79f2b4e, // 0.40664, -0.91359 + 0x3fda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // 0.40804, -0.91296 + 0x3fda34553b0afee5, 0xbfed31d98e9e503a, // 0.40944, -0.91234 + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171 + 0x3fda622906a70b63, 0xbfed2786335f52fc, // 0.41224, -0.91107 + 0x3fda790cd3dbf31a, 0xbfed2255c6e5a4e1, // 0.41364, -0.91044 + 0x3fda8fec8bf5b166, 0xbfed1d20dc40c15c, // 0.41503, -0.90981 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fdabd9faebc3980, 0xbfed12a98fac410c, // 0.41782, -0.90853 + 0x3fdad473125cdc08, 0xbfed0d672f59d2b9, // 0.41922, -0.90789 + 0x3fdaeb4252ca07ab, 0xbfed082054168bac, // 0.42061, -0.90724 + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066 + 0x3fdb18d45bf8aca6, 0xbfecfd852fff6ad4, // 0.42339, -0.90595 + 0x3fdb2f971db31972, 0xbfecf830e8ce467b, // 0.42478, -0.9053 + 0x3fdb4655ae2bf757, 0xbfecf2d829f1b40e, // 0.42617, -0.90464 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdb73c62d520624, 0xbfece819488344ce, // 0.42894, -0.90333 + 0x3fdb8a7814fd5693, 0xbfece2b32799a060, // 0.43033, -0.90267 + 0x3fdba125bd63583e, 0xbfecdd489254fe65, // 0.43171, -0.90201 + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135 + 0x3fdbce744262deee, 0xbfecd2660e12c1e6, // 0.43448, -0.90068 + 0x3fdbe51517ffc0d9, 0xbfecccee20c2de9f, // 0.43586, -0.90002 + 0x3fdbfbb1a05e0edc, 0xbfecc771c2736c09, // 0.43724, -0.89935 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdc28ddbb6cf145, 0xbfecbc6bb638d10b, // 0.43999, -0.898 + 0x3fdc3f6d47263129, 0xbfecb6e20a00da99, // 0.44137, -0.89732 + 0x3fdc55f877b23537, 0xbfecb153f02fb87d, // 0.44275, -0.89665 + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597 + 0x3fdc8301b95b40c2, 0xbfeca62a772fd919, // 0.4455, -0.89528 + 0x3fdc997fc3865388, 0xbfeca08f19b9c449, // 0.44687, -0.8946 + 0x3fdcaff964a0421d, 0xbfec9aef521bd480, // 0.44824, -0.89391 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdcdcdf5dc440ce, 0xbfec8fa287e13305, // 0.45098, -0.89253 + 0x3fdcf34baee1cd21, 0xbfec89f587029c13, // 0.45235, -0.89184 + 0x3fdd09b389152ec1, 0xbfec84441f785f61, // 0.45372, -0.89115 + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045 + 0x3fdd3675caebf962, 0xbfec78d41fe4a267, // 0.45645, -0.88975 + 0x3fdd4cd02ba8609c, 0xbfec7315899eaad7, // 0.45781, -0.88905 + 0x3fdd632607ac9aa9, 0xbfec6d5290341eb2, // 0.45918, -0.88835 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fdd8fc423c62a25, 0xbfec61bf777fcc48, // 0.4619, -0.88693 + 0x3fdda60c5cfa10d8, 0xbfec5bef59fef85a, // 0.46326, -0.88622 + 0x3fddbc5003b2edf8, 0xbfec561adceb743e, // 0.46462, -0.88551 + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848 + 0x3fdde8c98bf86bd6, 0xbfec4a64c7a5ac4c, // 0.46733, -0.88408 + 0x3fddfeff66a941de, 0xbfec44833141c004, // 0.46869, -0.88336 + 0x3fde1530a12779f4, 0xbfec3e9d3ee7d262, // 0.47004, -0.88264 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fde418527dc4ffa, 0xbfec32c449f60831, // 0.47275, -0.8812 + 0x3fde57a86d3cd824, 0xbfec2cd14931e3f1, // 0.4741, -0.88047 + 0x3fde6dc704be97e2, 0xbfec26d9f01f2eaf, // 0.47545, -0.87974 + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901 + 0x3fde99f61c817eda, 0xbfec1ade38bce19b, // 0.47815, -0.87828 + 0x3fdeb00695f25620, 0xbfec14d9dc465e58, // 0.47949, -0.87755 + 0x3fdec61253e3c61b, 0xbfec0ed12b3372e9, // 0.48084, -0.87681 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdef21b8fafd3b5, 0xbfec02b2cef1e641, // 0.48353, -0.87533 + 0x3fdf081906bff7fd, 0xbfebfc9d25a1b147, // 0.48487, -0.87459 + 0x3fdf1e11b4bbc35c, 0xbfebf6832b71ec5b, // 0.48621, -0.87384 + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309 + 0x3fdf49f4a7e97729, 0xbfebea424837de6d, // 0.48889, -0.87235 + 0x3fdf5fdee656cda3, 0xbfebe41b611154c1, // 0.49023, -0.8716 + 0x3fdf75c44e26a852, 0xbfebddf02cd2b983, // 0.49156, -0.87084 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fdfa1808c6cf7e0, 0xbfebd18ce0dc19d6, // 0.49423, -0.86933 + 0x3fdfb7575c24d2de, 0xbfebcb54cb0d2327, // 0.49557, -0.86857 + 0x3fdfcd2947c1ff57, 0xbfebc5186bf8361d, // 0.4969, -0.86781 + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705 + 0x3fdff8be6537615e, 0xbfebb892d5d5dad5, // 0.49956, -0.86628 + 0x3fe00740c82b82e0, 0xbfebb249a0b6c40d, // 0.50089, -0.86551 + 0x3fe0121fe4f56d2c, 0xbfebabfc262e6586, // 0.50221, -0.86474 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe027d6ad83287e, 0xbfeb9f5464c5bffc, // 0.50486, -0.8632 + 0x3fe032ae55edbd95, 0xbfeb98fa1fd9155e, // 0.50619, -0.86242 + 0x3fe03d837edff370, 0xbfeb929b996a5b7f, // 0.50751, -0.86165 + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087 + 0x3fe053264bad0483, 0xbfeb85d1cbf52c02, // 0.51015, -0.86009 + 0x3fe05df3ec31b8b6, 0xbfeb7f6686e792ea, // 0.51147, -0.8593 + 0x3fe068bf0691c028, 0xbfeb78f70449a34b, // 0.51279, -0.85852 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe07e4da23bc102, 0xbfeb6c0b4a55ac17, // 0.51542, -0.85694 + 0x3fe089112032b08c, 0xbfeb658f14fdbc47, // 0.51673, -0.85615 + 0x3fe093d2115ee018, 0xbfeb5f0ea611a532, // 0.51804, -0.85535 + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456 + 0x3fe0a94c46b53d0b, 0xbfeb52011f805c92, // 0.52067, -0.85376 + 0x3fe0b405878f85ec, 0xbfeb4b7409de7925, // 0.52198, -0.85296 + 0x3fe0bebc34ff4646, 0xbfeb44e2beaf0a61, // 0.52328, -0.85216 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe0d421cf03c12b, 0xbfeb37b38bb54c09, // 0.5259, -0.85055 + 0x3fe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // 0.5272, -0.84974 + 0x3fe0e97d078fd23b, 0xbfeb2a738eb51f33, // 0.5285, -0.84893 + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812 + 0x3fe0fecdd1770537, 0xbfeb1d22cfdadcc6, // 0.5311, -0.84731 + 0x3fe1097248d0a956, 0xbfeb16742a4ca2f5, // 0.5324, -0.84649 + 0x3fe114141f935545, 0xbfeb0fc1575d33db, // 0.5337, -0.84567 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe1294fe4c5350a, 0xbfeb024f2d7d24a9, // 0.53629, -0.84403 + 0x3fe133e9cfee254e, 0xbfeafb8fd89f57b6, // 0.53759, -0.84321 + 0x3fe13e8113f396c1, 0xbfeaf4cc5a85fb73, // 0.53888, -0.84238 + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155 + 0x3fe153a7a00bf453, 0xbfeae738e6cd4b67, // 0.54146, -0.84073 + 0x3fe15e36e4dbe2bc, 0xbfeae068f345ecef, // 0.54275, -0.83989 + 0x3fe168c37c025764, 0xbfead994dab2e979, // 0.54404, -0.83906 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe17dd49ad16161, 0xbfeacbe03ea0e73b, // 0.54661, -0.83739 + 0x3fe188591f3a46e5, 0xbfeac4ffbd3efac8, // 0.54789, -0.83655 + 0x3fe192daef7a5386, 0xbfeabe1b1b0b8dac, // 0.54918, -0.83571 + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486 + 0x3fe1a7d66d0516e6, 0xbfeab045787157ff, // 0.55174, -0.83402 + 0x3fe1b250171373be, 0xbfeaa9547a2cb98e, // 0.55302, -0.83317 + 0x3fe1bcc706804467, 0xbfeaa25f5f5aee60, // 0.55429, -0.83232 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe1d1acaf012cc2, 0xbfea9468d85b20ae, // 0.55685, -0.83062 + 0x3fe1dc1b64dc4872, 0xbfea8d676e545ad2, // 0.55812, -0.82976 + 0x3fe1e68759a3e074, 0xbfea8661ec0ee133, // 0.55939, -0.8289 + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805 + 0x3fe1fb56f98b37b8, 0xbfea784aa31d3f55, // 0.56193, -0.82718 + 0x3fe205baa17560d6, 0xbfea7138de9d60f5, // 0.5632, -0.82632 + 0x3fe2101b81e0da78, 0xbfea6a230637623b, // 0.56447, -0.82546 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe224d4e5d5482e, 0xbfea5beb1e188375, // 0.567, -0.82372 + 0x3fe22f2d662c13e1, 0xbfea54c91090f524, // 0.56826, -0.82285 + 0x3fe23983189fdfd5, 0xbfea4da2f385e997, // 0.56952, -0.82198 + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211 + 0x3fe24e260d7ee7c9, 0xbfea3f4a8f4ee2d2, // 0.57204, -0.82023 + 0x3fe258734cbb7110, 0xbfea38184a593bc6, // 0.5733, -0.81935 + 0x3fe262bdb7b795a2, 0xbfea30e1fa4cbf81, // 0.57455, -0.81847 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe2774a0a961612, 0xbfea22693d62ccb9, // 0.57706, -0.8167 + 0x3fe2818bef4d3cba, 0xbfea1b26d2c0a75e, // 0.57831, -0.81581 + 0x3fe28bcaf96d94ba, 0xbfea13e0617e4ec7, // 0.57956, -0.81493 + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404 + 0x3fe2a040779843fb, 0xbfea05476f967bb5, // 0.58206, -0.81314 + 0x3fe2aa76e87aeb58, 0xbfe9fdf4f13149de, // 0.58331, -0.81225 + 0x3fe2b4aa787764c4, 0xbfe9f69e70ac75bc, // 0.58455, -0.81135 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe2c908ef734e57, 0xbfe9e7e56dcb45bd, // 0.58704, -0.80956 + 0x3fe2d333d34e9bb7, 0xbfe9e082edb42472, // 0.58828, -0.80866 + 0x3fe2dd5bcffb7616, 0xbfe9d91c7007d5a6, // 0.58952, -0.80775 + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685 + 0x3fe2f1a30d86773a, 0xbfe9ca438080eadb, // 0.592, -0.80594 + 0x3fe2fbc24b441015, 0xbfe9c2d110f075c3, // 0.59323, -0.80503 + 0x3fe305de9b921a94, 0xbfe9bb5aa85f2098, // 0.59447, -0.80412 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe31a0e6da35e44, 0xbfe9ac61f0d4e247, // 0.59693, -0.80229 + 0x3fe32421ec49a620, 0xbfe9a4dfa42b06b2, // 0.59816, -0.80138 + 0x3fe32e3277467d6b, 0xbfe99d59631e65d5, // 0.59939, -0.80046 + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954 + 0x3fe3424aac0ef7d6, 0xbfe98e410881a600, // 0.60184, -0.79861 + 0x3fe34c5252c14de1, 0xbfe986aef1457594, // 0.60307, -0.79769 + 0x3fe35656ff9799ae, 0xbfe97f18ea4e5c9e, // 0.60429, -0.79676 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe36a576582831b, 0xbfe96fe111ddfce0, // 0.60673, -0.79491 + 0x3fe374531b817f8d, 0xbfe9683f42bd7fe1, // 0.60795, -0.79398 + 0x3fe37e4bd1792fe2, 0xbfe960998893ad8c, // 0.60917, -0.79304 + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211 + 0x3fe39234372c7f04, 0xbfe9514257dc4335, // 0.6116, -0.79117 + 0x3fe39c23e3d63029, 0xbfe94990e3ac4a6c, // 0.61281, -0.79023 + 0x3fe3a6108a54ba58, 0xbfe941db892e3a65, // 0.61402, -0.78929 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe3b9e0beb19e18, 0xbfe932652609b1cf, // 0.61644, -0.7874 + 0x3fe3c3c44981c517, 0xbfe92aa41fc5a815, // 0.61765, -0.78646 + 0x3fe3cda4c80a6076, 0xbfe922df37f8646a, // 0.61885, -0.78551 + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456 + 0x3fe3e15c9a2db922, 0xbfe91349c88da398, // 0.62126, -0.7836 + 0x3fe3eb33eabe0680, 0xbfe90b7943575efe, // 0.62246, -0.78265 + 0x3fe3f50828f1e8d2, 0xbfe903a4e1665133, // 0.62366, -0.78169 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe408a76834c0c0, 0xbfe8f3f08c28d9ac, // 0.62606, -0.77978 + 0x3fe41272663d108c, 0xbfe8ec109b486c49, // 0.62725, -0.77882 + 0x3fe41c3a4bdbaa26, 0xbfe8e42cd2852e0a, // 0.62845, -0.77785 + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689 + 0x3fe42fc0c7d3adbb, 0xbfe8d459be34bdfa, // 0.63083, -0.77592 + 0x3fe4397f5b2a4380, 0xbfe8cc6a75184655, // 0.63202, -0.77495 + 0x3fe4433ad0117b1d, 0xbfe8c47758fa71cb, // 0.63321, -0.77398 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe456a858917046, 0xbfe8b485aca2a468, // 0.63558, -0.77204 + 0x3fe4605a692b32a2, 0xbfe8ac871ede1d88, // 0.63676, -0.77106 + 0x3fe46a095557a0f1, 0xbfe8a484c3031d50, // 0.63794, -0.77008 + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691 + 0x3fe47d5dba6fde01, 0xbfe89474a5fb0a84, // 0.6403, -0.76812 + 0x3fe48703306091fe, 0xbfe88c66e7481ba1, // 0.64148, -0.76714 + 0x3fe490a57bedbcdf, 0xbfe884555f72fa6b, // 0.64266, -0.76615 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe4a3e08dec9ed6, 0xbfe87426f95cd5bd, // 0.645, -0.76418 + 0x3fe4ad79516722f0, 0xbfe86c0a1d9aa195, // 0.64618, -0.76319 + 0x3fe4b70ee48fb869, 0xbfe863e97db3d95a, // 0.64735, -0.7622 + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612 + 0x3fe4ca30740218a3, 0xbfe8539cf67c9029, // 0.64968, -0.76021 + 0x3fe4d3bc6d589f80, 0xbfe84b7111af83f9, // 0.65085, -0.75921 + 0x3fe4dd453076b064, 0xbfe843416dc4cce2, // 0.65201, -0.75821 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe4f04d0e2859aa, 0xbfe832d6eda3a3e0, // 0.65433, -0.75621 + 0x3fe4f9cc25cca486, 0xbfe82a9c13f545ff, // 0.65549, -0.7552 + 0x3fe503480159ded2, 0xbfe8225d803964e5, // 0.65665, -0.75419 + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319 + 0x3fe51635fe5601d7, 0xbfe811d52faf94dc, // 0.65896, -0.75218 + 0x3fe51fa81cd99aa6, 0xbfe8098b756e52fa, // 0.66011, -0.75117 + 0x3fe52916f96f8388, 0xbfe8013e0638e795, // 0.66127, -0.75015 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe53beae7012abe, 0xbfe7f0980e113978, // 0.66356, -0.74812 + 0x3fe5454ff5159dfb, 0xbfe7e83f87b03686, // 0.66471, -0.7471 + 0x3fe54eb1bb6dcb8f, 0xbfe7dfe3517d8937, // 0.66586, -0.74608 + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506 + 0x3fe5616b6b204e6e, 0xbfe7cf1fdacbf179, // 0.66814, -0.74403 + 0x3fe56ac35197649e, 0xbfe7c6b89ce2d333, // 0.66928, -0.74301 + 0x3fe57417ea8bb75c, 0xbfe7be4db453a27c, // 0.67042, -0.74198 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe586b72e2b2cfd, 0xbfe7ad6ce874dbb6, // 0.67269, -0.73992 + 0x3fe59001d5f723df, 0xbfe7a4f707bf97d2, // 0.67383, -0.73889 + 0x3fe599492a81ffbc, 0xbfe79c7d8198e56e, // 0.67496, -0.73785 + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682 + 0x3fe5abcdd41bb0d8, 0xbfe78b7f8a320a52, // 0.67722, -0.73578 + 0x3fe5b50b264f7448, 0xbfe782fb1b90b35b, // 0.67835, -0.73474 + 0x3fe5be451f8bf980, 0xbfe77a730cbb9100, // 0.67948, -0.7337 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe5d0af016ed1d4, 0xbfe7695813b9b594, // 0.68172, -0.73161 + 0x3fe5d9dee73e345c, 0xbfe760c52c304764, // 0.68285, -0.73056 + 0x3fe5e30b6e6877f3, 0xbfe7582ea9b9a329, // 0.68397, -0.72951 + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846 + 0x3fe5f55a5b2576f8, 0xbfe746f6d9516d59, // 0.6862, -0.72741 + 0x3fe5fe7cbde56a0f, 0xbfe73e558e079942, // 0.68732, -0.72636 + 0x3fe6079bbc5aadfa, 0xbfe735b0ad2009b2, // 0.68843, -0.7253 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe619cf86c55702, 0xbfe7245c2fcd492a, // 0.69065, -0.72319 + 0x3fe622e44fec22ff, 0xbfe71bac960e41bf, // 0.69176, -0.72213 + 0x3fe62bf5af2b0dfd, 0xbfe712f96c09d18d, // 0.69287, -0.72107 + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72 + 0x3fe63e0e2a59d7aa, 0xbfe701886c8f16e6, // 0.69508, -0.71894 + 0x3fe64715437f535b, 0xbfe6f8ca99c95b75, // 0.69618, -0.71787 + 0x3fe65018ed28287f, 0xbfe6f0093c1f54de, // 0.69728, -0.7168 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe66215ec74eb91, 0xbfe6de7be585881d, // 0.69947, -0.71466 + 0x3fe66b0f3f52b386, 0xbfe6d5afef4aafcc, // 0.70057, -0.71358 + 0x3fe674051d27896c, 0xbfe6cce07395679f, // 0.70166, -0.71251 + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143 + 0x3fe685e6742feeef, 0xbfe6bb36f12b5e06, // 0.70385, -0.71035 + 0x3fe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // 0.70493, -0.70927 + 0x3fe697b9e686941c, 0xbfe6a97f692c82ea, // 0.70602, -0.70819 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe6a97f692c82ea, 0xbfe697b9e686941c, // 0.70819, -0.70602 + 0x3fe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // 0.70927, -0.70493 + 0x3fe6bb36f12b5e06, 0xbfe685e6742feeef, // 0.71035, -0.70385 + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275 + 0x3fe6cce07395679f, 0xbfe674051d27896c, // 0.71251, -0.70166 + 0x3fe6d5afef4aafcc, 0xbfe66b0f3f52b386, // 0.71358, -0.70057 + 0x3fe6de7be585881d, 0xbfe66215ec74eb91, // 0.71466, -0.69947 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe6f0093c1f54de, 0xbfe65018ed28287f, // 0.7168, -0.69728 + 0x3fe6f8ca99c95b75, 0xbfe64715437f535b, // 0.71787, -0.69618 + 0x3fe701886c8f16e6, 0xbfe63e0e2a59d7aa, // 0.71894, -0.69508 + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397 + 0x3fe712f96c09d18d, 0xbfe62bf5af2b0dfd, // 0.72107, -0.69287 + 0x3fe71bac960e41bf, 0xbfe622e44fec22ff, // 0.72213, -0.69176 + 0x3fe7245c2fcd492a, 0xbfe619cf86c55702, // 0.72319, -0.69065 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe735b0ad2009b2, 0xbfe6079bbc5aadfa, // 0.7253, -0.68843 + 0x3fe73e558e079942, 0xbfe5fe7cbde56a0f, // 0.72636, -0.68732 + 0x3fe746f6d9516d59, 0xbfe5f55a5b2576f8, // 0.72741, -0.6862 + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508 + 0x3fe7582ea9b9a329, 0xbfe5e30b6e6877f3, // 0.72951, -0.68397 + 0x3fe760c52c304764, 0xbfe5d9dee73e345c, // 0.73056, -0.68285 + 0x3fe7695813b9b594, 0xbfe5d0af016ed1d4, // 0.73161, -0.68172 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe77a730cbb9100, 0xbfe5be451f8bf980, // 0.7337, -0.67948 + 0x3fe782fb1b90b35b, 0xbfe5b50b264f7448, // 0.73474, -0.67835 + 0x3fe78b7f8a320a52, 0xbfe5abcdd41bb0d8, // 0.73578, -0.67722 + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609 + 0x3fe79c7d8198e56e, 0xbfe599492a81ffbc, // 0.73785, -0.67496 + 0x3fe7a4f707bf97d2, 0xbfe59001d5f723df, // 0.73889, -0.67383 + 0x3fe7ad6ce874dbb6, 0xbfe586b72e2b2cfd, // 0.73992, -0.67269 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7be4db453a27c, 0xbfe57417ea8bb75c, // 0.74198, -0.67042 + 0x3fe7c6b89ce2d333, 0xbfe56ac35197649e, // 0.74301, -0.66928 + 0x3fe7cf1fdacbf179, 0xbfe5616b6b204e6e, // 0.74403, -0.66814 + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667 + 0x3fe7dfe3517d8937, 0xbfe54eb1bb6dcb8f, // 0.74608, -0.66586 + 0x3fe7e83f87b03686, 0xbfe5454ff5159dfb, // 0.7471, -0.66471 + 0x3fe7f0980e113978, 0xbfe53beae7012abe, // 0.74812, -0.66356 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe8013e0638e795, 0xbfe52916f96f8388, // 0.75015, -0.66127 + 0x3fe8098b756e52fa, 0xbfe51fa81cd99aa6, // 0.75117, -0.66011 + 0x3fe811d52faf94dc, 0xbfe51635fe5601d7, // 0.75218, -0.65896 + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781 + 0x3fe8225d803964e5, 0xbfe503480159ded2, // 0.75419, -0.65665 + 0x3fe82a9c13f545ff, 0xbfe4f9cc25cca486, // 0.7552, -0.65549 + 0x3fe832d6eda3a3e0, 0xbfe4f04d0e2859aa, // 0.75621, -0.65433 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe843416dc4cce2, 0xbfe4dd453076b064, // 0.75821, -0.65201 + 0x3fe84b7111af83f9, 0xbfe4d3bc6d589f80, // 0.75921, -0.65085 + 0x3fe8539cf67c9029, 0xbfe4ca30740218a3, // 0.76021, -0.64968 + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851 + 0x3fe863e97db3d95a, 0xbfe4b70ee48fb869, // 0.7622, -0.64735 + 0x3fe86c0a1d9aa195, 0xbfe4ad79516722f0, // 0.76319, -0.64618 + 0x3fe87426f95cd5bd, 0xbfe4a3e08dec9ed6, // 0.76418, -0.645 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe884555f72fa6b, 0xbfe490a57bedbcdf, // 0.76615, -0.64266 + 0x3fe88c66e7481ba1, 0xbfe48703306091fe, // 0.76714, -0.64148 + 0x3fe89474a5fb0a84, 0xbfe47d5dba6fde01, // 0.76812, -0.6403 + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912 + 0x3fe8a484c3031d50, 0xbfe46a095557a0f1, // 0.77008, -0.63794 + 0x3fe8ac871ede1d88, 0xbfe4605a692b32a2, // 0.77106, -0.63676 + 0x3fe8b485aca2a468, 0xbfe456a858917046, // 0.77204, -0.63558 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8c47758fa71cb, 0xbfe4433ad0117b1d, // 0.77398, -0.63321 + 0x3fe8cc6a75184655, 0xbfe4397f5b2a4380, // 0.77495, -0.63202 + 0x3fe8d459be34bdfa, 0xbfe42fc0c7d3adbb, // 0.77592, -0.63083 + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964 + 0x3fe8e42cd2852e0a, 0xbfe41c3a4bdbaa26, // 0.77785, -0.62845 + 0x3fe8ec109b486c49, 0xbfe41272663d108c, // 0.77882, -0.62725 + 0x3fe8f3f08c28d9ac, 0xbfe408a76834c0c0, // 0.77978, -0.62606 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe903a4e1665133, 0xbfe3f50828f1e8d2, // 0.78169, -0.62366 + 0x3fe90b7943575efe, 0xbfe3eb33eabe0680, // 0.78265, -0.62246 + 0x3fe91349c88da398, 0xbfe3e15c9a2db922, // 0.7836, -0.62126 + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006 + 0x3fe922df37f8646a, 0xbfe3cda4c80a6076, // 0.78551, -0.61885 + 0x3fe92aa41fc5a815, 0xbfe3c3c44981c517, // 0.78646, -0.61765 + 0x3fe932652609b1cf, 0xbfe3b9e0beb19e18, // 0.7874, -0.61644 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe941db892e3a65, 0xbfe3a6108a54ba58, // 0.78929, -0.61402 + 0x3fe94990e3ac4a6c, 0xbfe39c23e3d63029, // 0.79023, -0.61281 + 0x3fe9514257dc4335, 0xbfe39234372c7f04, // 0.79117, -0.6116 + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038 + 0x3fe960998893ad8c, 0xbfe37e4bd1792fe2, // 0.79304, -0.60917 + 0x3fe9683f42bd7fe1, 0xbfe374531b817f8d, // 0.79398, -0.60795 + 0x3fe96fe111ddfce0, 0xbfe36a576582831b, // 0.79491, -0.60673 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe97f18ea4e5c9e, 0xbfe35656ff9799ae, // 0.79676, -0.60429 + 0x3fe986aef1457594, 0xbfe34c5252c14de1, // 0.79769, -0.60307 + 0x3fe98e410881a600, 0xbfe3424aac0ef7d6, // 0.79861, -0.60184 + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062 + 0x3fe99d59631e65d5, 0xbfe32e3277467d6b, // 0.80046, -0.59939 + 0x3fe9a4dfa42b06b2, 0xbfe32421ec49a620, // 0.80138, -0.59816 + 0x3fe9ac61f0d4e247, 0xbfe31a0e6da35e44, // 0.80229, -0.59693 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9bb5aa85f2098, 0xbfe305de9b921a94, // 0.80412, -0.59447 + 0x3fe9c2d110f075c3, 0xbfe2fbc24b441015, // 0.80503, -0.59323 + 0x3fe9ca438080eadb, 0xbfe2f1a30d86773a, // 0.80594, -0.592 + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076 + 0x3fe9d91c7007d5a6, 0xbfe2dd5bcffb7616, // 0.80775, -0.58952 + 0x3fe9e082edb42472, 0xbfe2d333d34e9bb7, // 0.80866, -0.58828 + 0x3fe9e7e56dcb45bd, 0xbfe2c908ef734e57, // 0.80956, -0.58704 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fe9f69e70ac75bc, 0xbfe2b4aa787764c4, // 0.81135, -0.58455 + 0x3fe9fdf4f13149de, 0xbfe2aa76e87aeb58, // 0.81225, -0.58331 + 0x3fea05476f967bb5, 0xbfe2a040779843fb, // 0.81314, -0.58206 + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081 + 0x3fea13e0617e4ec7, 0xbfe28bcaf96d94ba, // 0.81493, -0.57956 + 0x3fea1b26d2c0a75e, 0xbfe2818bef4d3cba, // 0.81581, -0.57831 + 0x3fea22693d62ccb9, 0xbfe2774a0a961612, // 0.8167, -0.57706 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea30e1fa4cbf81, 0xbfe262bdb7b795a2, // 0.81847, -0.57455 + 0x3fea38184a593bc6, 0xbfe258734cbb7110, // 0.81935, -0.5733 + 0x3fea3f4a8f4ee2d2, 0xbfe24e260d7ee7c9, // 0.82023, -0.57204 + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078 + 0x3fea4da2f385e997, 0xbfe23983189fdfd5, // 0.82198, -0.56952 + 0x3fea54c91090f524, 0xbfe22f2d662c13e1, // 0.82285, -0.56826 + 0x3fea5beb1e188375, 0xbfe224d4e5d5482e, // 0.82372, -0.567 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea6a230637623b, 0xbfe2101b81e0da78, // 0.82546, -0.56447 + 0x3fea7138de9d60f5, 0xbfe205baa17560d6, // 0.82632, -0.5632 + 0x3fea784aa31d3f55, 0xbfe1fb56f98b37b8, // 0.82718, -0.56193 + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066 + 0x3fea8661ec0ee133, 0xbfe1e68759a3e074, // 0.8289, -0.55939 + 0x3fea8d676e545ad2, 0xbfe1dc1b64dc4872, // 0.82976, -0.55812 + 0x3fea9468d85b20ae, 0xbfe1d1acaf012cc2, // 0.83062, -0.55685 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3feaa25f5f5aee60, 0xbfe1bcc706804467, // 0.83232, -0.55429 + 0x3feaa9547a2cb98e, 0xbfe1b250171373be, // 0.83317, -0.55302 + 0x3feab045787157ff, 0xbfe1a7d66d0516e6, // 0.83402, -0.55174 + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046 + 0x3feabe1b1b0b8dac, 0xbfe192daef7a5386, // 0.83571, -0.54918 + 0x3feac4ffbd3efac8, 0xbfe188591f3a46e5, // 0.83655, -0.54789 + 0x3feacbe03ea0e73b, 0xbfe17dd49ad16161, // 0.83739, -0.54661 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3fead994dab2e979, 0xbfe168c37c025764, // 0.83906, -0.54404 + 0x3feae068f345ecef, 0xbfe15e36e4dbe2bc, // 0.83989, -0.54275 + 0x3feae738e6cd4b67, 0xbfe153a7a00bf453, // 0.84073, -0.54146 + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017 + 0x3feaf4cc5a85fb73, 0xbfe13e8113f396c1, // 0.84238, -0.53888 + 0x3feafb8fd89f57b6, 0xbfe133e9cfee254e, // 0.84321, -0.53759 + 0x3feb024f2d7d24a9, 0xbfe1294fe4c5350a, // 0.84403, -0.53629 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb0fc1575d33db, 0xbfe114141f935545, // 0.84567, -0.5337 + 0x3feb16742a4ca2f5, 0xbfe1097248d0a956, // 0.84649, -0.5324 + 0x3feb1d22cfdadcc6, 0xbfe0fecdd1770537, // 0.84731, -0.5311 + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298 + 0x3feb2a738eb51f33, 0xbfe0e97d078fd23b, // 0.84893, -0.5285 + 0x3feb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // 0.84974, -0.5272 + 0x3feb37b38bb54c09, 0xbfe0d421cf03c12b, // 0.85055, -0.5259 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb44e2beaf0a61, 0xbfe0bebc34ff4646, // 0.85216, -0.52328 + 0x3feb4b7409de7925, 0xbfe0b405878f85ec, // 0.85296, -0.52198 + 0x3feb52011f805c92, 0xbfe0a94c46b53d0b, // 0.85376, -0.52067 + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936 + 0x3feb5f0ea611a532, 0xbfe093d2115ee018, // 0.85535, -0.51804 + 0x3feb658f14fdbc47, 0xbfe089112032b08c, // 0.85615, -0.51673 + 0x3feb6c0b4a55ac17, 0xbfe07e4da23bc102, // 0.85694, -0.51542 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb78f70449a34b, 0xbfe068bf0691c028, // 0.85852, -0.51279 + 0x3feb7f6686e792ea, 0xbfe05df3ec31b8b6, // 0.8593, -0.51147 + 0x3feb85d1cbf52c02, 0xbfe053264bad0483, // 0.86009, -0.51015 + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883 + 0x3feb929b996a5b7f, 0xbfe03d837edff370, // 0.86165, -0.50751 + 0x3feb98fa1fd9155e, 0xbfe032ae55edbd95, // 0.86242, -0.50619 + 0x3feb9f5464c5bffc, 0xbfe027d6ad83287e, // 0.8632, -0.50486 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3febabfc262e6586, 0xbfe0121fe4f56d2c, // 0.86474, -0.50221 + 0x3febb249a0b6c40d, 0xbfe00740c82b82e0, // 0.86551, -0.50089 + 0x3febb892d5d5dad5, 0xbfdff8be6537615e, // 0.86628, -0.49956 + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823 + 0x3febc5186bf8361d, 0xbfdfcd2947c1ff57, // 0.86781, -0.4969 + 0x3febcb54cb0d2327, 0xbfdfb7575c24d2de, // 0.86857, -0.49557 + 0x3febd18ce0dc19d6, 0xbfdfa1808c6cf7e0, // 0.86933, -0.49423 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3febddf02cd2b983, 0xbfdf75c44e26a852, // 0.87084, -0.49156 + 0x3febe41b611154c1, 0xbfdf5fdee656cda3, // 0.8716, -0.49023 + 0x3febea424837de6d, 0xbfdf49f4a7e97729, // 0.87235, -0.48889 + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755 + 0x3febf6832b71ec5b, 0xbfdf1e11b4bbc35c, // 0.87384, -0.48621 + 0x3febfc9d25a1b147, 0xbfdf081906bff7fd, // 0.87459, -0.48487 + 0x3fec02b2cef1e641, 0xbfdef21b8fafd3b5, // 0.87533, -0.48353 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3fec0ed12b3372e9, 0xbfdec61253e3c61b, // 0.87681, -0.48084 + 0x3fec14d9dc465e58, 0xbfdeb00695f25620, // 0.87755, -0.47949 + 0x3fec1ade38bce19b, 0xbfde99f61c817eda, // 0.87828, -0.47815 + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768 + 0x3fec26d9f01f2eaf, 0xbfde6dc704be97e2, // 0.87974, -0.47545 + 0x3fec2cd14931e3f1, 0xbfde57a86d3cd824, // 0.88047, -0.4741 + 0x3fec32c449f60831, 0xbfde418527dc4ffa, // 0.8812, -0.47275 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec3e9d3ee7d262, 0xbfde1530a12779f4, // 0.88264, -0.47004 + 0x3fec44833141c004, 0xbfddfeff66a941de, // 0.88336, -0.46869 + 0x3fec4a64c7a5ac4c, 0xbfdde8c98bf86bd6, // 0.88408, -0.46733 + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598 + 0x3fec561adceb743e, 0xbfddbc5003b2edf8, // 0.88551, -0.46462 + 0x3fec5bef59fef85a, 0xbfdda60c5cfa10d8, // 0.88622, -0.46326 + 0x3fec61bf777fcc48, 0xbfdd8fc423c62a25, // 0.88693, -0.4619 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec6d5290341eb2, 0xbfdd632607ac9aa9, // 0.88835, -0.45918 + 0x3fec7315899eaad7, 0xbfdd4cd02ba8609c, // 0.88905, -0.45781 + 0x3fec78d41fe4a267, 0xbfdd3675caebf962, // 0.88975, -0.45645 + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508 + 0x3fec84441f785f61, 0xbfdd09b389152ec1, // 0.89115, -0.45372 + 0x3fec89f587029c13, 0xbfdcf34baee1cd21, // 0.89184, -0.45235 + 0x3fec8fa287e13305, 0xbfdcdcdf5dc440ce, // 0.89253, -0.45098 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fec9aef521bd480, 0xbfdcaff964a0421d, // 0.89391, -0.44824 + 0x3feca08f19b9c449, 0xbfdc997fc3865388, // 0.8946, -0.44687 + 0x3feca62a772fd919, 0xbfdc8301b95b40c2, // 0.89528, -0.4455 + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412 + 0x3fecb153f02fb87d, 0xbfdc55f877b23537, // 0.89665, -0.44275 + 0x3fecb6e20a00da99, 0xbfdc3f6d47263129, // 0.89732, -0.44137 + 0x3fecbc6bb638d10b, 0xbfdc28ddbb6cf145, // 0.898, -0.43999 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3fecc771c2736c09, 0xbfdbfbb1a05e0edc, // 0.89935, -0.43724 + 0x3fecccee20c2de9f, 0xbfdbe51517ffc0d9, // 0.90002, -0.43586 + 0x3fecd2660e12c1e6, 0xbfdbce744262deee, // 0.90068, -0.43448 + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309 + 0x3fecdd489254fe65, 0xbfdba125bd63583e, // 0.90201, -0.43171 + 0x3fece2b32799a060, 0xbfdb8a7814fd5693, // 0.90267, -0.43033 + 0x3fece819488344ce, 0xbfdb73c62d520624, // 0.90333, -0.42894 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fecf2d829f1b40e, 0xbfdb4655ae2bf757, // 0.90464, -0.42617 + 0x3fecf830e8ce467b, 0xbfdb2f971db31972, // 0.9053, -0.42478 + 0x3fecfd852fff6ad4, 0xbfdb18d45bf8aca6, // 0.90595, -0.42339 + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422 + 0x3fed082054168bac, 0xbfdaeb4252ca07ab, // 0.90724, -0.42061 + 0x3fed0d672f59d2b9, 0xbfdad473125cdc08, // 0.90789, -0.41922 + 0x3fed12a98fac410c, 0xbfdabd9faebc3980, // 0.90853, -0.41782 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed1d20dc40c15c, 0xbfda8fec8bf5b166, // 0.90981, -0.41503 + 0x3fed2255c6e5a4e1, 0xbfda790cd3dbf31a, // 0.91044, -0.41364 + 0x3fed2786335f52fc, 0xbfda622906a70b63, // 0.91107, -0.41224 + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084 + 0x3fed31d98e9e503a, 0xbfda34553b0afee5, // 0.91234, -0.40944 + 0x3fed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // 0.91296, -0.40804 + 0x3fed3c1ae79f2b4e, 0xbfda067145664d57, // 0.91359, -0.40664 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed464a380e7242, 0xbfd9d87d4207b0ab, // 0.91483, -0.40384 + 0x3fed4b5b1b187524, 0xbfd9c17d440df9f2, // 0.91545, -0.40243 + 0x3fed506779a3d2d9, 0xbfd9aa794d47c9ee, // 0.91606, -0.40103 + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962 + 0x3fed5a72a6221e73, 0xbfd97c6583890fc2, // 0.91729, -0.39822 + 0x3fed5f7172888a7f, 0xbfd96555b7ab948f, // 0.9179, -0.39681 + 0x3fed646bb7574de5, 0xbfd94e420137bce3, // 0.91851, -0.3954 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed6e52a71c8547, 0xbfd9200ee2c9be97, // 0.91972, -0.39258 + 0x3fed733f508c0dff, 0xbfd908ef81ef7bd1, // 0.92032, -0.39117 + 0x3fed78276f5617c6, 0xbfd8f1cc44bea329, // 0.92092, -0.38976 + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835 + 0x3fed81ea09f38b63, 0xbfd8c37a439f884f, // 0.92211, -0.38693 + 0x3fed86c48445a450, 0xbfd8ac4b86d5ed44, // 0.9227, -0.38552 + 0x3fed8b9a70ef9cb4, 0xbfd89518fbff098e, // 0.92329, -0.3841 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fed95389e50429b, 0xbfd866a88a792ea0, // 0.92447, -0.38127 + 0x3fed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // 0.92505, -0.37985 + 0x3fed9ec48c26b1f3, 0xbfd838290bb359c8, // 0.92563, -0.37843 + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701 + 0x3feda83e348f613b, 0xbfd8099a9c5c362d, // 0.92679, -0.37559 + 0x3fedacf42ce68ab9, 0xbfd7f24dd37341e3, // 0.92736, -0.37416 + 0x3fedb1a591b20c38, 0xbfd7dafd592ba621, // 0.92794, -0.37274 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3fedbafa9dc1b78d, 0xbfd7ac515ee2b172, // 0.92907, -0.36989 + 0x3fedbf9e4395759a, 0xbfd794f5e613dfae, // 0.92964, -0.36847 + 0x3fedc43d52fcb453, 0xbfd77d96ca4b73a6, // 0.93021, -0.36704 + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561 + 0x3fedcd6dabaca3a5, 0xbfd74ecdb8390a3e, // 0.93133, -0.36418 + 0x3fedd1fef38a915a, 0xbfd73763c9261092, // 0.93188, -0.36276 + 0x3fedd68ba2267a25, 0xbfd71ff6458782ec, // 0.93244, -0.36133 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3feddf9730ca837b, 0xbfd6f1108f1bc9c5, // 0.93354, -0.35846 + 0x3fede4160f6d8d81, 0xbfd6d998638a0cb5, // 0.93409, -0.35703 + 0x3fede890520465ce, 0xbfd6c21cb1e39771, // 0.93464, -0.3556 + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416 + 0x3fedf177004b2534, 0xbfd6931acad55f51, // 0.93573, -0.35273 + 0x3fedf5e36a9ba59c, 0xbfd67b949cad63ca, // 0.93627, -0.35129 + 0x3fedfa4b3621271d, 0xbfd6640af6f03d9e, // 0.9368, -0.34986 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fee030cee1435b8, 0xbfd634ed533be58e, // 0.93787, -0.34698 + 0x3fee0766d9280f54, 0xbfd61d595c88c203, // 0.9384, -0.34554 + 0x3fee0bbc22bd8349, 0xbfd605c1fcc88f63, // 0.93893, -0.3441 + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266 + 0x3fee1458cec1ad83, 0xbfd5d68910aee686, // 0.93998, -0.34122 + 0x3fee18a02fdc66d9, 0xbfd5bee78b9db3b6, // 0.94051, -0.33978 + 0x3fee1ce2ecd0c0d8, 0xbfd5a742ac0ff78d, // 0.94103, -0.33833 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee255a77a63bb8, 0xbfd577eeec151e47, // 0.94206, -0.33545 + 0x3fee298f4439197a, 0xbfd5604012f467b4, // 0.94257, -0.334 + 0x3fee2dbf6a0911d9, 0xbfd5488dedeff3be, // 0.94308, -0.33255 + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111 + 0x3fee3611becbaf69, 0xbfd5191fceda3c35, // 0.9441, -0.32966 + 0x3fee3a33ec75ce85, 0xbfd50163dc197047, // 0.9446, -0.32821 + 0x3fee3e5170cbfc46, 0xbfd4e9a4ac15d520, // 0.94511, -0.32676 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee467e7af35f23, 0xbfd4ba1ca2eca31c, // 0.94611, -0.32386 + 0x3fee4a8dff81ce5e, 0xbfd4a253d11b82f3, // 0.9466, -0.32241 + 0x3fee4e98d836c0af, 0xbfd48a87d0b07fd7, // 0.94709, -0.32096 + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195 + 0x3fee56a083968eb1, 0xbfd45ae652bb2800, // 0.94807, -0.31805 + 0x3fee5a9d550467d3, 0xbfd44310dc8936f0, // 0.94856, -0.31659 + 0x3fee5e95781ebf1c, 0xbfd42b38466e2928, // 0.94905, -0.31514 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee6677b0e6d31e, 0xbfd3fb7dc932cfa4, // 0.95001, -0.31222 + 0x3fee6a61c55d53a7, 0xbfd3e39be96ec271, // 0.95049, -0.31077 + 0x3fee6e472911da27, 0xbfd3cbb6f87a146e, // 0.95096, -0.30931 + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785 + 0x3fee7603dbce74e9, 0xbfd39be3f1bc8aef, // 0.95191, -0.30639 + 0x3fee79db29a5165a, 0xbfd383f5e353b6aa, // 0.95238, -0.30493 + 0x3fee7dadc456d850, 0xbfd36c04d27a4edf, // 0.95284, -0.30347 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee8544ddf0d075, 0xbfd33c19b83af207, // 0.95377, -0.30054 + 0x3fee89095bad6025, 0xbfd3241fb638baaf, // 0.95423, -0.29908 + 0x3fee8cc923edc388, 0xbfd30c22c08d6a13, // 0.95469, -0.29762 + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615 + 0x3fee943a91aab4b4, 0xbfd2dc200907fe51, // 0.95559, -0.29469 + 0x3fee97ec36016b30, 0xbfd2c41a4e954520, // 0.95605, -0.29322 + 0x3fee9b99229046f8, 0xbfd2ac11af483572, // 0.95649, -0.29175 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3feea2e4d212c000, 0xbfd27bf7d0f2c346, // 0.95738, -0.28882 + 0x3feea68393e65800, 0xbfd263e6995554ba, // 0.95783, -0.28735 + 0x3feeaa1d9bb20af3, 0xbfd24bd28bb37672, // 0.95827, -0.28588 + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441 + 0x3feeb1437af9bb34, 0xbfd21ba1fd3d2623, // 0.95914, -0.28294 + 0x3feeb4cf515b8811, 0xbfd2038583d727bd, // 0.95957, -0.28146 + 0x3feeb8566b810f2a, 0xbfd1eb6643499fbb, // 0.96, -0.27999 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feebf5668eaf2ef, 0xbfd1bb1f7b999480, // 0.96086, -0.27705 + 0x3feec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // 0.96128, -0.27557 + 0x3feec6436ee60309, 0xbfd18acdc3f4873a, // 0.9617, -0.2741 + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262 + 0x3feecd1d792c8f10, 0xbfd15a713a28b9d9, // 0.96254, -0.27115 + 0x3feed0835e999009, 0xbfd1423eefc69378, // 0.96295, -0.26967 + 0x3feed3e483849c51, 0xbfd12a09fc0b1b12, // 0.96337, -0.26819 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feeda9889bfe86a, 0xbfd0f998277733f7, // 0.96418, -0.26523 + 0x3feeddeb6a078651, 0xbfd0e15b4e1749cd, // 0.96459, -0.26375 + 0x3feee13987bbebdc, 0xbfd0c91bda4f158d, // 0.96499, -0.26227 + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079 + 0x3feee7c77961dc9e, 0xbfd09895327b465e, // 0.96579, -0.25931 + 0x3feeeb074c50a544, 0xbfd0804e05eb661e, // 0.96619, -0.25783 + 0x3feeee425aa6b09a, 0xbfd068044deab002, // 0.96658, -0.25635 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3feef4aa278b2032, 0xbfd037694a928cac, // 0.96737, -0.25338 + 0x3feef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // 0.96775, -0.2519 + 0x3feefafedc1ba8b7, 0xbfd006c4466e54af, // 0.96814, -0.25041 + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893 + 0x3fef014074708ed3, 0xbfcfac2abeff57ff, // 0.9689, -0.24744 + 0x3fef045a14cf738c, 0xbfcf7b7480bd3801, // 0.96928, -0.24596 + 0x3fef076eecade0fa, 0xbfcf4ab9679c9f5c, // 0.96966, -0.24447 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef0d8a410379c5, 0xbfcee934c2d006c7, // 0.9704, -0.24149 + 0x3fef1090bc898f5f, 0xbfceb86b462de348, // 0.97077, -0.24 + 0x3fef13926dad024e, 0xbfce879d0cc0fdaf, // 0.97114, -0.23851 + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702 + 0x3fef19876ef1f486, 0xbfce25f281a2b684, // 0.97187, -0.23553 + 0x3fef1c7abe284708, 0xbfcdf5163f01099a, // 0.97223, -0.23404 + 0x3fef1f6941259d7a, 0xbfcdc4355db40195, // 0.97258, -0.23255 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef2537e0a71f9f, 0xbfcd6265dd3f27e3, // 0.97329, -0.22957 + 0x3fef2817fc4609ce, 0xbfcd31774d2cbdee, // 0.97364, -0.22807 + 0x3fef2af349e17507, 0xbfcd00843c99c5f9, // 0.97399, -0.22658 + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508 + 0x3fef309b794b719f, 0xbfcc9e90b824a6a9, // 0.97468, -0.22359 + 0x3fef33685a3aaef0, 0xbfcc6d90535d74dc, // 0.97503, -0.22209 + 0x3fef36306b67c556, 0xbfcc3c8b8c4b9dd7, // 0.97536, -0.2206 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef3bb21cc4fe47, 0xbfcbda74f5856330, // 0.97604, -0.2176 + 0x3fef3e6bbc1bbc65, 0xbfcba96334f15dad, // 0.97637, -0.21611 + 0x3fef412089fd8adc, 0xbfcb784d30536cda, // 0.9767, -0.21461 + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311 + 0x3fef467bafb7bbe0, 0xbfcb16147941ca2a, // 0.97735, -0.21161 + 0x3fef492206bcabb4, 0xbfcae4f1d5f3b9ab, // 0.97768, -0.21011 + 0x3fef4bc38aa5c694, 0xbfcab3cb0ce6fe44, // 0.978, -0.20861 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef50f81785c6b9, 0xbfca517127e3dabc, // 0.97863, -0.20561 + 0x3fef538b1faf2d07, 0xbfca203e1b1831da, // 0.97895, -0.20411 + 0x3fef56195321c090, 0xbfc9ef0706e35a35, // 0.97926, -0.20261 + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011 + 0x3fef5b273a4fa2d9, 0xbfc98c8ce69a7aec, // 0.97988, -0.1996 + 0x3fef5da6ed43685d, 0xbfc95b49e9b62af9, // 0.98018, -0.1981 + 0x3fef6021c9f148c2, 0xbfc92a0303c8194f, // 0.98048, -0.19659 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef6508fef47bd5, 0xbfc8c7699b34ca7e, // 0.98108, -0.19359 + 0x3fef677556883cee, 0xbfc8961727c41804, // 0.98138, -0.19208 + 0x3fef69dcd652f5de, 0xbfc864c0e9b2b6cf, // 0.98167, -0.19057 + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907 + 0x3fef6e9d4d1262ca, 0xbfc802092c1d744b, // 0.98225, -0.18756 + 0x3fef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // 0.98254, -0.18606 + 0x3fef734a60446279, 0xbfc79f429f59e11d, // 0.98282, -0.18455 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef77e40d068a90, 0xbfc73c6d8055fe0a, // 0.98339, -0.18153 + 0x3fef7a299c1a322a, 0xbfc70afd8d08c4ff, // 0.98366, -0.18002 + 0x3fef7c6a50826840, 0xbfc6d98a0c08c8da, // 0.98394, -0.17851 + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177 + 0x3fef80dd27ed8204, 0xbfc676987f7216b8, // 0.98448, -0.17549 + 0x3fef830f4a40c60c, 0xbfc6451a831d830d, // 0.98475, -0.17398 + 0x3fef853c9089595e, 0xbfc61399179a6e94, // 0.98501, -0.17247 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef898887a36c84, 0xbfc5b08c1192e381, // 0.98554, -0.16945 + 0x3fef8ba737cb4b78, 0xbfc57f008654cbde, // 0.9858, -0.16794 + 0x3fef8dc10a95380d, 0xbfc54d71aa74ef02, // 0.98605, -0.16643 + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491 + 0x3fef91e616c43891, 0xbfc4ea4a1f624b61, // 0.98656, -0.1634 + 0x3fef93f14f85ac08, 0xbfc4b8b17f79fa88, // 0.98681, -0.16189 + 0x3fef95f7a9a1ec47, 0xbfc48715ad84cdf5, // 0.98706, -0.16037 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fef99f5c0abd496, 0xbfc423d4920e4166, // 0.98754, -0.15734 + 0x3fef9bed7cfbde29, 0xbfc3f22f57db4893, // 0.98778, -0.15583 + 0x3fef9de0596b77a3, 0xbfc3c0870a383ff6, // 0.98802, -0.15431 + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528 + 0x3fefa1b7717661d5, 0xbfc35d2d53440db2, // 0.98849, -0.15128 + 0x3fefa39bac7a1791, 0xbfc32b7bf94516a7, // 0.98872, -0.14976 + 0x3fefa57b066e2754, 0xbfc2f9c7aa7a72af, // 0.98895, -0.14825 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefa92b1600657c, 0xbfc296564d2b953e, // 0.9894, -0.14521 + 0x3fefaafbcb0cfddc, 0xbfc264994dfd340a, // 0.98962, -0.1437 + 0x3fefacc79de6c44f, 0xbfc232d978aed413, // 0.98984, -0.14218 + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066 + 0x3fefb0509be6f7db, 0xbfc1cf516a62a077, // 0.99027, -0.13914 + 0x3fefb20dc681d54d, 0xbfc19d8940be24e7, // 0.99049, -0.13762 + 0x3fefb3c60dd2c199, 0xbfc16bbe5fac5865, // 0.9907, -0.1361 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefb727f187f1c7, 0xbfc1082095f820b0, // 0.99111, -0.13306 + 0x3fefb8d18d66adb7, 0xbfc0d64dbcb26786, // 0.99131, -0.13154 + 0x3fefba7644f068b5, 0xbfc0a4784ab8bf1d, // 0.99151, -0.13002 + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285 + 0x3fefbdb106021816, 0xbfc040c5bb67747e, // 0.99191, -0.12698 + 0x3fefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // 0.9921, -0.12545 + 0x3fefc0d832bf043a, 0xbfbfba124b07ad85, // 0.99229, -0.12393 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefc3ebc935454c, 0xbfbef2858d27561b, // 0.99267, -0.12089 + 0x3fefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // 0.99285, -0.11937 + 0x3fefc6ebc77f0887, 0xbfbe2ae5b8457f77, // 0.99303, -0.11784 + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632 + 0x3fefc9d82bc2915e, 0xbfbd633347858ce4, // 0.99339, -0.11479 + 0x3fefcb4703914354, 0xbfbcff533b307dc1, // 0.99356, -0.11327 + 0x3fefccb0f4323aa3, 0xbfbc9b6eb6165c42, // 0.99374, -0.11175 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefcf761f0c77a3, 0xbfbbd3987f31fa0e, // 0.99407, -0.1087 + 0x3fefd0d158d86087, 0xbfbb6fa6ec38f64c, // 0.99424, -0.10717 + 0x3fefd227aa9bd53b, 0xbfbb0bb11e1d5559, // 0.9944, -0.10565 + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412 + 0x3fefd4c59536fae4, 0xbfba43b90e27f3c4, // 0.99472, -0.1026 + 0x3fefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // 0.99488, -0.10107 + 0x3fefd74fdd40abbf, 0xbfb97bb0caaba56f, // 0.99503, -0.099544 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017 + 0x3fefd9c68127c78c, 0xbfb8b398cf0c38e0, // 0.99533, -0.09649 + 0x3fefdafa7514538c, 0xbfb84f8712c130a0, // 0.99548, -0.094963 + 0x3fefdc297f674ba9, 0xbfb7eb7196b72ee4, // 0.99563, -0.093436 + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909 + 0x3fefde78d68653fd, 0xbfb7233b9d236e71, // 0.99591, -0.090381 + 0x3fefdf9922f73307, 0xbfb6bf1b3e79b129, // 0.99604, -0.088854 + 0x3fefe0b485181be3, 0xbfb65af75dd0f87b, // 0.99618, -0.087326 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797 + 0x3fefe2dc89bbff08, 0xbfb592a554489bc8, // 0.99644, -0.084269 + 0x3fefe3e92be9d886, 0xbfb52e774a4d4d0a, // 0.99657, -0.08274 + 0x3fefe4f0e31d7a4a, 0xbfb4ca45fc1ba8b6, // 0.9967, -0.081211 + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682 + 0x3fefe6f18ff42c84, 0xbfb401d9d0e3a507, // 0.99694, -0.078153 + 0x3fefe7ea85482d60, 0xbfb39d9f12c5a299, // 0.99706, -0.076624 + 0x3fefe8de8f03d75c, 0xbfb339614e41ffa5, // 0.99718, -0.075094 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565 + 0x3fefeab7df1c6005, 0xbfb270dcefdfc45b, // 0.9974, -0.072035 + 0x3fefeb9d2530410f, 0xbfb20c9674ed444c, // 0.99751, -0.070505 + 0x3fefec7d7f19cffc, 0xbfb1a84d316d4f8a, // 0.99762, -0.068974 + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444 + 0x3fefee2f6de455ba, 0xbfb0dfb28ea201e6, // 0.99783, -0.065913 + 0x3fefef0102826191, 0xbfb07b614e463064, // 0.99793, -0.064383 + 0x3fefefcdaa704562, 0xbfb0170d833bf421, // 0.99802, -0.062852 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321 + 0x3feff15833be1965, 0xbfae9cbd15ff5527, // 0.99821, -0.05979 + 0x3feff21614e131ed, 0xbfadd406f9808ec8, // 0.9983, -0.058258 + 0x3feff2cf08da7321, 0xbfad0b4c436f91d0, // 0.99839, -0.056727 + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195 + 0x3feff43228de1b77, 0xbfab79c986698b78, // 0.99856, -0.053664 + 0x3feff4dc54b1bed3, 0xbfaab101bd5f8317, // 0.99864, -0.052132 + 0x3feff58192ee0358, 0xbfa9e835d6993c87, // 0.99872, -0.0506 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068 + 0x3feff6bd463b444d, 0xbfa856922bb513c1, // 0.99887, -0.047535 + 0x3feff753bb1b9164, 0xbfa78dbaa5874685, // 0.99894, -0.046003 + 0x3feff7e5420320f9, 0xbfa6c4df7d7d5b84, // 0.99901, -0.044471 + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938 + 0x3feff8f9858f058b, 0xbfa5331ec3bba0eb, // 0.99914, -0.041406 + 0x3feff97c4208c014, 0xbfa46a396ff86179, // 0.9992, -0.039873 + 0x3feff9fa10348837, 0xbfa3a150f6421afc, // 0.99926, -0.03834 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807 + 0x3feffae6e1556998, 0xbfa20f770ceb11c6, // 0.99938, -0.035274 + 0x3feffb55e425fdae, 0xbfa14685db42c17e, // 0.99943, -0.033741 + 0x3feffbbff85f9515, 0xbfa07d91ff984580, // 0.99948, -0.032208 + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675 + 0x3feffc8554cd213a, 0xbf9dd7458c64ab39, // 0.99958, -0.029142 + 0x3feffce09ce2a679, 0xbf9c454f4ce53b1c, // 0.99962, -0.027608 + 0x3feffd36f624500c, 0xbf9ab354b1504fca, // 0.99966, -0.026075 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541 + 0x3feffdd4dbf78f52, 0xbf978f535ddc9f03, // 0.99974, -0.023008 + 0x3feffe1c6870cb77, 0xbf95fd4d21fab226, // 0.99977, -0.021474 + 0x3feffe5f05e578db, 0xbf946b4381fce81c, // 0.9998, -0.01994 + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407 + 0x3feffed57398d2b7, 0xbf9147270dad7132, // 0.99986, -0.016873 + 0x3fefff0943c53bd1, 0xbf8f6a296ab997ca, // 0.99988, -0.015339 + 0x3fefff3824c88f6f, 0xbf8c45ffe1e48ad9, // 0.9999, -0.013805 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272 + 0x3fefff871937ce2f, 0xbf85fda037ac05e0, // 0.99994, -0.010738 + 0x3fefffa72c978c4f, 0xbf82d96b0e509703, // 0.99996,-0.0092038 + 0x3fefffc250b5daef, 0xbf7f6a65f9a2a3c5, // 0.99997,-0.0076698 + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359 + 0x3fefffe9cb1e2e8d, 0xbf72d97822f996bc, // 0.99999,-0.0046019 + 0x3feffff621621d02, 0xbf6921f8becca4ba, // 1, -0.003068 + 0x3feffffd88586ee6, 0xbf5921faaee6472d, // 1, -0.001534 + + +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par +
for (i = 0; i < N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 16, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_16[32] = { + 1.000000000f, 0.000000000f, + 0.923879533f, 0.382683432f, + 0.707106781f, 0.707106781f, + 0.382683432f, 0.923879533f, + 0.000000000f, 1.000000000f, + -0.382683432f, 0.923879533f, + -0.707106781f, 0.707106781f, + -0.923879533f, 0.382683432f, + -1.000000000f, 0.000000000f, + -0.923879533f, -0.382683432f, + -0.707106781f, -0.707106781f, + -0.382683432f, -0.923879533f, + -0.000000000f, -1.000000000f, + 0.382683432f, -0.923879533f, + 0.707106781f, -0.707106781f, + 0.923879533f, -0.382683432f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par +
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 32, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_32[64] = { + 1.000000000f, 0.000000000f, + 0.980785280f, 0.195090322f, + 0.923879533f, 0.382683432f, + 0.831469612f, 0.555570233f, + 0.707106781f, 0.707106781f, + 0.555570233f, 0.831469612f, + 0.382683432f, 0.923879533f, + 0.195090322f, 0.980785280f, + 0.000000000f, 1.000000000f, + -0.195090322f, 0.980785280f, + -0.382683432f, 0.923879533f, + -0.555570233f, 0.831469612f, + -0.707106781f, 0.707106781f, + -0.831469612f, 0.555570233f, + -0.923879533f, 0.382683432f, + -0.980785280f, 0.195090322f, + -1.000000000f, 0.000000000f, + -0.980785280f, -0.195090322f, + -0.923879533f, -0.382683432f, + -0.831469612f, -0.555570233f, + -0.707106781f, -0.707106781f, + -0.555570233f, -0.831469612f, + -0.382683432f, -0.923879533f, + -0.195090322f, -0.980785280f, + -0.000000000f, -1.000000000f, + 0.195090322f, -0.980785280f, + 0.382683432f, -0.923879533f, + 0.555570233f, -0.831469612f, + 0.707106781f, -0.707106781f, + 0.831469612f, -0.555570233f, + 0.923879533f, -0.382683432f, + 0.980785280f, -0.195090322f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par +
for(i = 0; i < N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 64, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_64[128] = { + 1.000000000f, 0.000000000f, + 0.995184727f, 0.098017140f, + 0.980785280f, 0.195090322f, + 0.956940336f, 0.290284677f, + 0.923879533f, 0.382683432f, + 0.881921264f, 0.471396737f, + 0.831469612f, 0.555570233f, + 0.773010453f, 0.634393284f, + 0.707106781f, 0.707106781f, + 0.634393284f, 0.773010453f, + 0.555570233f, 0.831469612f, + 0.471396737f, 0.881921264f, + 0.382683432f, 0.923879533f, + 0.290284677f, 0.956940336f, + 0.195090322f, 0.980785280f, + 0.098017140f, 0.995184727f, + 0.000000000f, 1.000000000f, + -0.098017140f, 0.995184727f, + -0.195090322f, 0.980785280f, + -0.290284677f, 0.956940336f, + -0.382683432f, 0.923879533f, + -0.471396737f, 0.881921264f, + -0.555570233f, 0.831469612f, + -0.634393284f, 0.773010453f, + -0.707106781f, 0.707106781f, + -0.773010453f, 0.634393284f, + -0.831469612f, 0.555570233f, + -0.881921264f, 0.471396737f, + -0.923879533f, 0.382683432f, + -0.956940336f, 0.290284677f, + -0.980785280f, 0.195090322f, + -0.995184727f, 0.098017140f, + -1.000000000f, 0.000000000f, + -0.995184727f, -0.098017140f, + -0.980785280f, -0.195090322f, + -0.956940336f, -0.290284677f, + -0.923879533f, -0.382683432f, + -0.881921264f, -0.471396737f, + -0.831469612f, -0.555570233f, + -0.773010453f, -0.634393284f, + -0.707106781f, -0.707106781f, + -0.634393284f, -0.773010453f, + -0.555570233f, -0.831469612f, + -0.471396737f, -0.881921264f, + -0.382683432f, -0.923879533f, + -0.290284677f, -0.956940336f, + -0.195090322f, -0.980785280f, + -0.098017140f, -0.995184727f, + -0.000000000f, -1.000000000f, + 0.098017140f, -0.995184727f, + 0.195090322f, -0.980785280f, + 0.290284677f, -0.956940336f, + 0.382683432f, -0.923879533f, + 0.471396737f, -0.881921264f, + 0.555570233f, -0.831469612f, + 0.634393284f, -0.773010453f, + 0.707106781f, -0.707106781f, + 0.773010453f, -0.634393284f, + 0.831469612f, -0.555570233f, + 0.881921264f, -0.471396737f, + 0.923879533f, -0.382683432f, + 0.956940336f, -0.290284677f, + 0.980785280f, -0.195090322f, + 0.995184727f, -0.098017140f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par +
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 128, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_128[256] = { + 1.000000000f, 0.000000000f, + 0.998795456f, 0.049067674f, + 0.995184727f, 0.098017140f, + 0.989176510f, 0.146730474f, + 0.980785280f, 0.195090322f, + 0.970031253f, 0.242980180f, + 0.956940336f, 0.290284677f, + 0.941544065f, 0.336889853f, + 0.923879533f, 0.382683432f, + 0.903989293f, 0.427555093f, + 0.881921264f, 0.471396737f, + 0.857728610f, 0.514102744f, + 0.831469612f, 0.555570233f, + 0.803207531f, 0.595699304f, + 0.773010453f, 0.634393284f, + 0.740951125f, 0.671558955f, + 0.707106781f, 0.707106781f, + 0.671558955f, 0.740951125f, + 0.634393284f, 0.773010453f, + 0.595699304f, 0.803207531f, + 0.555570233f, 0.831469612f, + 0.514102744f, 0.857728610f, + 0.471396737f, 0.881921264f, + 0.427555093f, 0.903989293f, + 0.382683432f, 0.923879533f, + 0.336889853f, 0.941544065f, + 0.290284677f, 0.956940336f, + 0.242980180f, 0.970031253f, + 0.195090322f, 0.980785280f, + 0.146730474f, 0.989176510f, + 0.098017140f, 0.995184727f, + 0.049067674f, 0.998795456f, + 0.000000000f, 1.000000000f, + -0.049067674f, 0.998795456f, + -0.098017140f, 0.995184727f, + -0.146730474f, 0.989176510f, + -0.195090322f, 0.980785280f, + -0.242980180f, 0.970031253f, + -0.290284677f, 0.956940336f, + -0.336889853f, 0.941544065f, + -0.382683432f, 0.923879533f, + -0.427555093f, 0.903989293f, + -0.471396737f, 0.881921264f, + -0.514102744f, 0.857728610f, + -0.555570233f, 0.831469612f, + -0.595699304f, 0.803207531f, + -0.634393284f, 0.773010453f, + -0.671558955f, 0.740951125f, + -0.707106781f, 0.707106781f, + -0.740951125f, 0.671558955f, + -0.773010453f, 0.634393284f, + -0.803207531f, 0.595699304f, + -0.831469612f, 0.555570233f, + -0.857728610f, 0.514102744f, + -0.881921264f, 0.471396737f, + -0.903989293f, 0.427555093f, + -0.923879533f, 0.382683432f, + -0.941544065f, 0.336889853f, + -0.956940336f, 0.290284677f, + -0.970031253f, 0.242980180f, + -0.980785280f, 0.195090322f, + -0.989176510f, 0.146730474f, + -0.995184727f, 0.098017140f, + -0.998795456f, 0.049067674f, + -1.000000000f, 0.000000000f, + -0.998795456f, -0.049067674f, + -0.995184727f, -0.098017140f, + -0.989176510f, -0.146730474f, + -0.980785280f, -0.195090322f, + -0.970031253f, -0.242980180f, + -0.956940336f, -0.290284677f, + -0.941544065f, -0.336889853f, + -0.923879533f, -0.382683432f, + -0.903989293f, -0.427555093f, + -0.881921264f, -0.471396737f, + -0.857728610f, -0.514102744f, + -0.831469612f, -0.555570233f, + -0.803207531f, -0.595699304f, + -0.773010453f, -0.634393284f, + -0.740951125f, -0.671558955f, + -0.707106781f, -0.707106781f, + -0.671558955f, -0.740951125f, + -0.634393284f, -0.773010453f, + -0.595699304f, -0.803207531f, + -0.555570233f, -0.831469612f, + -0.514102744f, -0.857728610f, + -0.471396737f, -0.881921264f, + -0.427555093f, -0.903989293f, + -0.382683432f, -0.923879533f, + -0.336889853f, -0.941544065f, + -0.290284677f, -0.956940336f, + -0.242980180f, -0.970031253f, + -0.195090322f, -0.980785280f, + -0.146730474f, -0.989176510f, + -0.098017140f, -0.995184727f, + -0.049067674f, -0.998795456f, + -0.000000000f, -1.000000000f, + 0.049067674f, -0.998795456f, + 0.098017140f, -0.995184727f, + 0.146730474f, -0.989176510f, + 0.195090322f, -0.980785280f, + 0.242980180f, -0.970031253f, + 0.290284677f, -0.956940336f, + 0.336889853f, -0.941544065f, + 0.382683432f, -0.923879533f, + 0.427555093f, -0.903989293f, + 0.471396737f, -0.881921264f, + 0.514102744f, -0.857728610f, + 0.555570233f, -0.831469612f, + 0.595699304f, -0.803207531f, + 0.634393284f, -0.773010453f, + 0.671558955f, -0.740951125f, + 0.707106781f, -0.707106781f, + 0.740951125f, -0.671558955f, + 0.773010453f, -0.634393284f, + 0.803207531f, -0.595699304f, + 0.831469612f, -0.555570233f, + 0.857728610f, -0.514102744f, + 0.881921264f, -0.471396737f, + 0.903989293f, -0.427555093f, + 0.923879533f, -0.382683432f, + 0.941544065f, -0.336889853f, + 0.956940336f, -0.290284677f, + 0.970031253f, -0.242980180f, + 0.980785280f, -0.195090322f, + 0.989176510f, -0.146730474f, + 0.995184727f, -0.098017140f, + 0.998795456f, -0.049067674f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par +
for(i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 256, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_256[512] = { + 1.000000000f, 0.000000000f, + 0.999698819f, 0.024541229f, + 0.998795456f, 0.049067674f, + 0.997290457f, 0.073564564f, + 0.995184727f, 0.098017140f, + 0.992479535f, 0.122410675f, + 0.989176510f, 0.146730474f, + 0.985277642f, 0.170961889f, + 0.980785280f, 0.195090322f, + 0.975702130f, 0.219101240f, + 0.970031253f, 0.242980180f, + 0.963776066f, 0.266712757f, + 0.956940336f, 0.290284677f, + 0.949528181f, 0.313681740f, + 0.941544065f, 0.336889853f, + 0.932992799f, 0.359895037f, + 0.923879533f, 0.382683432f, + 0.914209756f, 0.405241314f, + 0.903989293f, 0.427555093f, + 0.893224301f, 0.449611330f, + 0.881921264f, 0.471396737f, + 0.870086991f, 0.492898192f, + 0.857728610f, 0.514102744f, + 0.844853565f, 0.534997620f, + 0.831469612f, 0.555570233f, + 0.817584813f, 0.575808191f, + 0.803207531f, 0.595699304f, + 0.788346428f, 0.615231591f, + 0.773010453f, 0.634393284f, + 0.757208847f, 0.653172843f, + 0.740951125f, 0.671558955f, + 0.724247083f, 0.689540545f, + 0.707106781f, 0.707106781f, + 0.689540545f, 0.724247083f, + 0.671558955f, 0.740951125f, + 0.653172843f, 0.757208847f, + 0.634393284f, 0.773010453f, + 0.615231591f, 0.788346428f, + 0.595699304f, 0.803207531f, + 0.575808191f, 0.817584813f, + 0.555570233f, 0.831469612f, + 0.534997620f, 0.844853565f, + 0.514102744f, 0.857728610f, + 0.492898192f, 0.870086991f, + 0.471396737f, 0.881921264f, + 0.449611330f, 0.893224301f, + 0.427555093f, 0.903989293f, + 0.405241314f, 0.914209756f, + 0.382683432f, 0.923879533f, + 0.359895037f, 0.932992799f, + 0.336889853f, 0.941544065f, + 0.313681740f, 0.949528181f, + 0.290284677f, 0.956940336f, + 0.266712757f, 0.963776066f, + 0.242980180f, 0.970031253f, + 0.219101240f, 0.975702130f, + 0.195090322f, 0.980785280f, + 0.170961889f, 0.985277642f, + 0.146730474f, 0.989176510f, + 0.122410675f, 0.992479535f, + 0.098017140f, 0.995184727f, + 0.073564564f, 0.997290457f, + 0.049067674f, 0.998795456f, + 0.024541229f, 0.999698819f, + 0.000000000f, 1.000000000f, + -0.024541229f, 0.999698819f, + -0.049067674f, 0.998795456f, + -0.073564564f, 0.997290457f, + -0.098017140f, 0.995184727f, + -0.122410675f, 0.992479535f, + -0.146730474f, 0.989176510f, + -0.170961889f, 0.985277642f, + -0.195090322f, 0.980785280f, + -0.219101240f, 0.975702130f, + -0.242980180f, 0.970031253f, + -0.266712757f, 0.963776066f, + -0.290284677f, 0.956940336f, + -0.313681740f, 0.949528181f, + -0.336889853f, 0.941544065f, + -0.359895037f, 0.932992799f, + -0.382683432f, 0.923879533f, + -0.405241314f, 0.914209756f, + -0.427555093f, 0.903989293f, + -0.449611330f, 0.893224301f, + -0.471396737f, 0.881921264f, + -0.492898192f, 0.870086991f, + -0.514102744f, 0.857728610f, + -0.534997620f, 0.844853565f, + -0.555570233f, 0.831469612f, + -0.575808191f, 0.817584813f, + -0.595699304f, 0.803207531f, + -0.615231591f, 0.788346428f, + -0.634393284f, 0.773010453f, + -0.653172843f, 0.757208847f, + -0.671558955f, 0.740951125f, + -0.689540545f, 0.724247083f, + -0.707106781f, 0.707106781f, + -0.724247083f, 0.689540545f, + -0.740951125f, 0.671558955f, + -0.757208847f, 0.653172843f, + -0.773010453f, 0.634393284f, + -0.788346428f, 0.615231591f, + -0.803207531f, 0.595699304f, + -0.817584813f, 0.575808191f, + -0.831469612f, 0.555570233f, + -0.844853565f, 0.534997620f, + -0.857728610f, 0.514102744f, + -0.870086991f, 0.492898192f, + -0.881921264f, 0.471396737f, + -0.893224301f, 0.449611330f, + -0.903989293f, 0.427555093f, + -0.914209756f, 0.405241314f, + -0.923879533f, 0.382683432f, + -0.932992799f, 0.359895037f, + -0.941544065f, 0.336889853f, + -0.949528181f, 0.313681740f, + -0.956940336f, 0.290284677f, + -0.963776066f, 0.266712757f, + -0.970031253f, 0.242980180f, + -0.975702130f, 0.219101240f, + -0.980785280f, 0.195090322f, + -0.985277642f, 0.170961889f, + -0.989176510f, 0.146730474f, + -0.992479535f, 0.122410675f, + -0.995184727f, 0.098017140f, + -0.997290457f, 0.073564564f, + -0.998795456f, 0.049067674f, + -0.999698819f, 0.024541229f, + -1.000000000f, 0.000000000f, + -0.999698819f, -0.024541229f, + -0.998795456f, -0.049067674f, + -0.997290457f, -0.073564564f, + -0.995184727f, -0.098017140f, + -0.992479535f, -0.122410675f, + -0.989176510f, -0.146730474f, + -0.985277642f, -0.170961889f, + -0.980785280f, -0.195090322f, + -0.975702130f, -0.219101240f, + -0.970031253f, -0.242980180f, + -0.963776066f, -0.266712757f, + -0.956940336f, -0.290284677f, + -0.949528181f, -0.313681740f, + -0.941544065f, -0.336889853f, + -0.932992799f, -0.359895037f, + -0.923879533f, -0.382683432f, + -0.914209756f, -0.405241314f, + -0.903989293f, -0.427555093f, + -0.893224301f, -0.449611330f, + -0.881921264f, -0.471396737f, + -0.870086991f, -0.492898192f, + -0.857728610f, -0.514102744f, + -0.844853565f, -0.534997620f, + -0.831469612f, -0.555570233f, + -0.817584813f, -0.575808191f, + -0.803207531f, -0.595699304f, + -0.788346428f, -0.615231591f, + -0.773010453f, -0.634393284f, + -0.757208847f, -0.653172843f, + -0.740951125f, -0.671558955f, + -0.724247083f, -0.689540545f, + -0.707106781f, -0.707106781f, + -0.689540545f, -0.724247083f, + -0.671558955f, -0.740951125f, + -0.653172843f, -0.757208847f, + -0.634393284f, -0.773010453f, + -0.615231591f, -0.788346428f, + -0.595699304f, -0.803207531f, + -0.575808191f, -0.817584813f, + -0.555570233f, -0.831469612f, + -0.534997620f, -0.844853565f, + -0.514102744f, -0.857728610f, + -0.492898192f, -0.870086991f, + -0.471396737f, -0.881921264f, + -0.449611330f, -0.893224301f, + -0.427555093f, -0.903989293f, + -0.405241314f, -0.914209756f, + -0.382683432f, -0.923879533f, + -0.359895037f, -0.932992799f, + -0.336889853f, -0.941544065f, + -0.313681740f, -0.949528181f, + -0.290284677f, -0.956940336f, + -0.266712757f, -0.963776066f, + -0.242980180f, -0.970031253f, + -0.219101240f, -0.975702130f, + -0.195090322f, -0.980785280f, + -0.170961889f, -0.985277642f, + -0.146730474f, -0.989176510f, + -0.122410675f, -0.992479535f, + -0.098017140f, -0.995184727f, + -0.073564564f, -0.997290457f, + -0.049067674f, -0.998795456f, + -0.024541229f, -0.999698819f, + -0.000000000f, -1.000000000f, + 0.024541229f, -0.999698819f, + 0.049067674f, -0.998795456f, + 0.073564564f, -0.997290457f, + 0.098017140f, -0.995184727f, + 0.122410675f, -0.992479535f, + 0.146730474f, -0.989176510f, + 0.170961889f, -0.985277642f, + 0.195090322f, -0.980785280f, + 0.219101240f, -0.975702130f, + 0.242980180f, -0.970031253f, + 0.266712757f, -0.963776066f, + 0.290284677f, -0.956940336f, + 0.313681740f, -0.949528181f, + 0.336889853f, -0.941544065f, + 0.359895037f, -0.932992799f, + 0.382683432f, -0.923879533f, + 0.405241314f, -0.914209756f, + 0.427555093f, -0.903989293f, + 0.449611330f, -0.893224301f, + 0.471396737f, -0.881921264f, + 0.492898192f, -0.870086991f, + 0.514102744f, -0.857728610f, + 0.534997620f, -0.844853565f, + 0.555570233f, -0.831469612f, + 0.575808191f, -0.817584813f, + 0.595699304f, -0.803207531f, + 0.615231591f, -0.788346428f, + 0.634393284f, -0.773010453f, + 0.653172843f, -0.757208847f, + 0.671558955f, -0.740951125f, + 0.689540545f, -0.724247083f, + 0.707106781f, -0.707106781f, + 0.724247083f, -0.689540545f, + 0.740951125f, -0.671558955f, + 0.757208847f, -0.653172843f, + 0.773010453f, -0.634393284f, + 0.788346428f, -0.615231591f, + 0.803207531f, -0.595699304f, + 0.817584813f, -0.575808191f, + 0.831469612f, -0.555570233f, + 0.844853565f, -0.534997620f, + 0.857728610f, -0.514102744f, + 0.870086991f, -0.492898192f, + 0.881921264f, -0.471396737f, + 0.893224301f, -0.449611330f, + 0.903989293f, -0.427555093f, + 0.914209756f, -0.405241314f, + 0.923879533f, -0.382683432f, + 0.932992799f, -0.359895037f, + 0.941544065f, -0.336889853f, + 0.949528181f, -0.313681740f, + 0.956940336f, -0.290284677f, + 0.963776066f, -0.266712757f, + 0.970031253f, -0.242980180f, + 0.975702130f, -0.219101240f, + 0.980785280f, -0.195090322f, + 0.985277642f, -0.170961889f, + 0.989176510f, -0.146730474f, + 0.992479535f, -0.122410675f, + 0.995184727f, -0.098017140f, + 0.997290457f, -0.073564564f, + 0.998795456f, -0.049067674f, + 0.999698819f, -0.024541229f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par +
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 512, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_512[1024] = { + 1.000000000f, 0.000000000f, + 0.999924702f, 0.012271538f, + 0.999698819f, 0.024541229f, + 0.999322385f, 0.036807223f, + 0.998795456f, 0.049067674f, + 0.998118113f, 0.061320736f, + 0.997290457f, 0.073564564f, + 0.996312612f, 0.085797312f, + 0.995184727f, 0.098017140f, + 0.993906970f, 0.110222207f, + 0.992479535f, 0.122410675f, + 0.990902635f, 0.134580709f, + 0.989176510f, 0.146730474f, + 0.987301418f, 0.158858143f, + 0.985277642f, 0.170961889f, + 0.983105487f, 0.183039888f, + 0.980785280f, 0.195090322f, + 0.978317371f, 0.207111376f, + 0.975702130f, 0.219101240f, + 0.972939952f, 0.231058108f, + 0.970031253f, 0.242980180f, + 0.966976471f, 0.254865660f, + 0.963776066f, 0.266712757f, + 0.960430519f, 0.278519689f, + 0.956940336f, 0.290284677f, + 0.953306040f, 0.302005949f, + 0.949528181f, 0.313681740f, + 0.945607325f, 0.325310292f, + 0.941544065f, 0.336889853f, + 0.937339012f, 0.348418680f, + 0.932992799f, 0.359895037f, + 0.928506080f, 0.371317194f, + 0.923879533f, 0.382683432f, + 0.919113852f, 0.393992040f, + 0.914209756f, 0.405241314f, + 0.909167983f, 0.416429560f, + 0.903989293f, 0.427555093f, + 0.898674466f, 0.438616239f, + 0.893224301f, 0.449611330f, + 0.887639620f, 0.460538711f, + 0.881921264f, 0.471396737f, + 0.876070094f, 0.482183772f, + 0.870086991f, 0.492898192f, + 0.863972856f, 0.503538384f, + 0.857728610f, 0.514102744f, + 0.851355193f, 0.524589683f, + 0.844853565f, 0.534997620f, + 0.838224706f, 0.545324988f, + 0.831469612f, 0.555570233f, + 0.824589303f, 0.565731811f, + 0.817584813f, 0.575808191f, + 0.810457198f, 0.585797857f, + 0.803207531f, 0.595699304f, + 0.795836905f, 0.605511041f, + 0.788346428f, 0.615231591f, + 0.780737229f, 0.624859488f, + 0.773010453f, 0.634393284f, + 0.765167266f, 0.643831543f, + 0.757208847f, 0.653172843f, + 0.749136395f, 0.662415778f, + 0.740951125f, 0.671558955f, + 0.732654272f, 0.680600998f, + 0.724247083f, 0.689540545f, + 0.715730825f, 0.698376249f, + 0.707106781f, 0.707106781f, + 0.698376249f, 0.715730825f, + 0.689540545f, 0.724247083f, + 0.680600998f, 0.732654272f, + 0.671558955f, 0.740951125f, + 0.662415778f, 0.749136395f, + 0.653172843f, 0.757208847f, + 0.643831543f, 0.765167266f, + 0.634393284f, 0.773010453f, + 0.624859488f, 0.780737229f, + 0.615231591f, 0.788346428f, + 0.605511041f, 0.795836905f, + 0.595699304f, 0.803207531f, + 0.585797857f, 0.810457198f, + 0.575808191f, 0.817584813f, + 0.565731811f, 0.824589303f, + 0.555570233f, 0.831469612f, + 0.545324988f, 0.838224706f, + 0.534997620f, 0.844853565f, + 0.524589683f, 0.851355193f, + 0.514102744f, 0.857728610f, + 0.503538384f, 0.863972856f, + 0.492898192f, 0.870086991f, + 0.482183772f, 0.876070094f, + 0.471396737f, 0.881921264f, + 0.460538711f, 0.887639620f, + 0.449611330f, 0.893224301f, + 0.438616239f, 0.898674466f, + 0.427555093f, 0.903989293f, + 0.416429560f, 0.909167983f, + 0.405241314f, 0.914209756f, + 0.393992040f, 0.919113852f, + 0.382683432f, 0.923879533f, + 0.371317194f, 0.928506080f, + 0.359895037f, 0.932992799f, + 0.348418680f, 0.937339012f, + 0.336889853f, 0.941544065f, + 0.325310292f, 0.945607325f, + 0.313681740f, 0.949528181f, + 0.302005949f, 0.953306040f, + 0.290284677f, 0.956940336f, + 0.278519689f, 0.960430519f, + 0.266712757f, 0.963776066f, + 0.254865660f, 0.966976471f, + 0.242980180f, 0.970031253f, + 0.231058108f, 0.972939952f, + 0.219101240f, 0.975702130f, + 0.207111376f, 0.978317371f, + 0.195090322f, 0.980785280f, + 0.183039888f, 0.983105487f, + 0.170961889f, 0.985277642f, + 0.158858143f, 0.987301418f, + 0.146730474f, 0.989176510f, + 0.134580709f, 0.990902635f, + 0.122410675f, 0.992479535f, + 0.110222207f, 0.993906970f, + 0.098017140f, 0.995184727f, + 0.085797312f, 0.996312612f, + 0.073564564f, 0.997290457f, + 0.061320736f, 0.998118113f, + 0.049067674f, 0.998795456f, + 0.036807223f, 0.999322385f, + 0.024541229f, 0.999698819f, + 0.012271538f, 0.999924702f, + 0.000000000f, 1.000000000f, + -0.012271538f, 0.999924702f, + -0.024541229f, 0.999698819f, + -0.036807223f, 0.999322385f, + -0.049067674f, 0.998795456f, + -0.061320736f, 0.998118113f, + -0.073564564f, 0.997290457f, + -0.085797312f, 0.996312612f, + -0.098017140f, 0.995184727f, + -0.110222207f, 0.993906970f, + -0.122410675f, 0.992479535f, + -0.134580709f, 0.990902635f, + -0.146730474f, 0.989176510f, + -0.158858143f, 0.987301418f, + -0.170961889f, 0.985277642f, + -0.183039888f, 0.983105487f, + -0.195090322f, 0.980785280f, + -0.207111376f, 0.978317371f, + -0.219101240f, 0.975702130f, + -0.231058108f, 0.972939952f, + -0.242980180f, 0.970031253f, + -0.254865660f, 0.966976471f, + -0.266712757f, 0.963776066f, + -0.278519689f, 0.960430519f, + -0.290284677f, 0.956940336f, + -0.302005949f, 0.953306040f, + -0.313681740f, 0.949528181f, + -0.325310292f, 0.945607325f, + -0.336889853f, 0.941544065f, + -0.348418680f, 0.937339012f, + -0.359895037f, 0.932992799f, + -0.371317194f, 0.928506080f, + -0.382683432f, 0.923879533f, + -0.393992040f, 0.919113852f, + -0.405241314f, 0.914209756f, + -0.416429560f, 0.909167983f, + -0.427555093f, 0.903989293f, + -0.438616239f, 0.898674466f, + -0.449611330f, 0.893224301f, + -0.460538711f, 0.887639620f, + -0.471396737f, 0.881921264f, + -0.482183772f, 0.876070094f, + -0.492898192f, 0.870086991f, + -0.503538384f, 0.863972856f, + -0.514102744f, 0.857728610f, + -0.524589683f, 0.851355193f, + -0.534997620f, 0.844853565f, + -0.545324988f, 0.838224706f, + -0.555570233f, 0.831469612f, + -0.565731811f, 0.824589303f, + -0.575808191f, 0.817584813f, + -0.585797857f, 0.810457198f, + -0.595699304f, 0.803207531f, + -0.605511041f, 0.795836905f, + -0.615231591f, 0.788346428f, + -0.624859488f, 0.780737229f, + -0.634393284f, 0.773010453f, + -0.643831543f, 0.765167266f, + -0.653172843f, 0.757208847f, + -0.662415778f, 0.749136395f, + -0.671558955f, 0.740951125f, + -0.680600998f, 0.732654272f, + -0.689540545f, 0.724247083f, + -0.698376249f, 0.715730825f, + -0.707106781f, 0.707106781f, + -0.715730825f, 0.698376249f, + -0.724247083f, 0.689540545f, + -0.732654272f, 0.680600998f, + -0.740951125f, 0.671558955f, + -0.749136395f, 0.662415778f, + -0.757208847f, 0.653172843f, + -0.765167266f, 0.643831543f, + -0.773010453f, 0.634393284f, + -0.780737229f, 0.624859488f, + -0.788346428f, 0.615231591f, + -0.795836905f, 0.605511041f, + -0.803207531f, 0.595699304f, + -0.810457198f, 0.585797857f, + -0.817584813f, 0.575808191f, + -0.824589303f, 0.565731811f, + -0.831469612f, 0.555570233f, + -0.838224706f, 0.545324988f, + -0.844853565f, 0.534997620f, + -0.851355193f, 0.524589683f, + -0.857728610f, 0.514102744f, + -0.863972856f, 0.503538384f, + -0.870086991f, 0.492898192f, + -0.876070094f, 0.482183772f, + -0.881921264f, 0.471396737f, + -0.887639620f, 0.460538711f, + -0.893224301f, 0.449611330f, + -0.898674466f, 0.438616239f, + -0.903989293f, 0.427555093f, + -0.909167983f, 0.416429560f, + -0.914209756f, 0.405241314f, + -0.919113852f, 0.393992040f, + -0.923879533f, 0.382683432f, + -0.928506080f, 0.371317194f, + -0.932992799f, 0.359895037f, + -0.937339012f, 0.348418680f, + -0.941544065f, 0.336889853f, + -0.945607325f, 0.325310292f, + -0.949528181f, 0.313681740f, + -0.953306040f, 0.302005949f, + -0.956940336f, 0.290284677f, + -0.960430519f, 0.278519689f, + -0.963776066f, 0.266712757f, + -0.966976471f, 0.254865660f, + -0.970031253f, 0.242980180f, + -0.972939952f, 0.231058108f, + -0.975702130f, 0.219101240f, + -0.978317371f, 0.207111376f, + -0.980785280f, 0.195090322f, + -0.983105487f, 0.183039888f, + -0.985277642f, 0.170961889f, + -0.987301418f, 0.158858143f, + -0.989176510f, 0.146730474f, + -0.990902635f, 0.134580709f, + -0.992479535f, 0.122410675f, + -0.993906970f, 0.110222207f, + -0.995184727f, 0.098017140f, + -0.996312612f, 0.085797312f, + -0.997290457f, 0.073564564f, + -0.998118113f, 0.061320736f, + -0.998795456f, 0.049067674f, + -0.999322385f, 0.036807223f, + -0.999698819f, 0.024541229f, + -0.999924702f, 0.012271538f, + -1.000000000f, 0.000000000f, + -0.999924702f, -0.012271538f, + -0.999698819f, -0.024541229f, + -0.999322385f, -0.036807223f, + -0.998795456f, -0.049067674f, + -0.998118113f, -0.061320736f, + -0.997290457f, -0.073564564f, + -0.996312612f, -0.085797312f, + -0.995184727f, -0.098017140f, + -0.993906970f, -0.110222207f, + -0.992479535f, -0.122410675f, + -0.990902635f, -0.134580709f, + -0.989176510f, -0.146730474f, + -0.987301418f, -0.158858143f, + -0.985277642f, -0.170961889f, + -0.983105487f, -0.183039888f, + -0.980785280f, -0.195090322f, + -0.978317371f, -0.207111376f, + -0.975702130f, -0.219101240f, + -0.972939952f, -0.231058108f, + -0.970031253f, -0.242980180f, + -0.966976471f, -0.254865660f, + -0.963776066f, -0.266712757f, + -0.960430519f, -0.278519689f, + -0.956940336f, -0.290284677f, + -0.953306040f, -0.302005949f, + -0.949528181f, -0.313681740f, + -0.945607325f, -0.325310292f, + -0.941544065f, -0.336889853f, + -0.937339012f, -0.348418680f, + -0.932992799f, -0.359895037f, + -0.928506080f, -0.371317194f, + -0.923879533f, -0.382683432f, + -0.919113852f, -0.393992040f, + -0.914209756f, -0.405241314f, + -0.909167983f, -0.416429560f, + -0.903989293f, -0.427555093f, + -0.898674466f, -0.438616239f, + -0.893224301f, -0.449611330f, + -0.887639620f, -0.460538711f, + -0.881921264f, -0.471396737f, + -0.876070094f, -0.482183772f, + -0.870086991f, -0.492898192f, + -0.863972856f, -0.503538384f, + -0.857728610f, -0.514102744f, + -0.851355193f, -0.524589683f, + -0.844853565f, -0.534997620f, + -0.838224706f, -0.545324988f, + -0.831469612f, -0.555570233f, + -0.824589303f, -0.565731811f, + -0.817584813f, -0.575808191f, + -0.810457198f, -0.585797857f, + -0.803207531f, -0.595699304f, + -0.795836905f, -0.605511041f, + -0.788346428f, -0.615231591f, + -0.780737229f, -0.624859488f, + -0.773010453f, -0.634393284f, + -0.765167266f, -0.643831543f, + -0.757208847f, -0.653172843f, + -0.749136395f, -0.662415778f, + -0.740951125f, -0.671558955f, + -0.732654272f, -0.680600998f, + -0.724247083f, -0.689540545f, + -0.715730825f, -0.698376249f, + -0.707106781f, -0.707106781f, + -0.698376249f, -0.715730825f, + -0.689540545f, -0.724247083f, + -0.680600998f, -0.732654272f, + -0.671558955f, -0.740951125f, + -0.662415778f, -0.749136395f, + -0.653172843f, -0.757208847f, + -0.643831543f, -0.765167266f, + -0.634393284f, -0.773010453f, + -0.624859488f, -0.780737229f, + -0.615231591f, -0.788346428f, + -0.605511041f, -0.795836905f, + -0.595699304f, -0.803207531f, + -0.585797857f, -0.810457198f, + -0.575808191f, -0.817584813f, + -0.565731811f, -0.824589303f, + -0.555570233f, -0.831469612f, + -0.545324988f, -0.838224706f, + -0.534997620f, -0.844853565f, + -0.524589683f, -0.851355193f, + -0.514102744f, -0.857728610f, + -0.503538384f, -0.863972856f, + -0.492898192f, -0.870086991f, + -0.482183772f, -0.876070094f, + -0.471396737f, -0.881921264f, + -0.460538711f, -0.887639620f, + -0.449611330f, -0.893224301f, + -0.438616239f, -0.898674466f, + -0.427555093f, -0.903989293f, + -0.416429560f, -0.909167983f, + -0.405241314f, -0.914209756f, + -0.393992040f, -0.919113852f, + -0.382683432f, -0.923879533f, + -0.371317194f, -0.928506080f, + -0.359895037f, -0.932992799f, + -0.348418680f, -0.937339012f, + -0.336889853f, -0.941544065f, + -0.325310292f, -0.945607325f, + -0.313681740f, -0.949528181f, + -0.302005949f, -0.953306040f, + -0.290284677f, -0.956940336f, + -0.278519689f, -0.960430519f, + -0.266712757f, -0.963776066f, + -0.254865660f, -0.966976471f, + -0.242980180f, -0.970031253f, + -0.231058108f, -0.972939952f, + -0.219101240f, -0.975702130f, + -0.207111376f, -0.978317371f, + -0.195090322f, -0.980785280f, + -0.183039888f, -0.983105487f, + -0.170961889f, -0.985277642f, + -0.158858143f, -0.987301418f, + -0.146730474f, -0.989176510f, + -0.134580709f, -0.990902635f, + -0.122410675f, -0.992479535f, + -0.110222207f, -0.993906970f, + -0.098017140f, -0.995184727f, + -0.085797312f, -0.996312612f, + -0.073564564f, -0.997290457f, + -0.061320736f, -0.998118113f, + -0.049067674f, -0.998795456f, + -0.036807223f, -0.999322385f, + -0.024541229f, -0.999698819f, + -0.012271538f, -0.999924702f, + -0.000000000f, -1.000000000f, + 0.012271538f, -0.999924702f, + 0.024541229f, -0.999698819f, + 0.036807223f, -0.999322385f, + 0.049067674f, -0.998795456f, + 0.061320736f, -0.998118113f, + 0.073564564f, -0.997290457f, + 0.085797312f, -0.996312612f, + 0.098017140f, -0.995184727f, + 0.110222207f, -0.993906970f, + 0.122410675f, -0.992479535f, + 0.134580709f, -0.990902635f, + 0.146730474f, -0.989176510f, + 0.158858143f, -0.987301418f, + 0.170961889f, -0.985277642f, + 0.183039888f, -0.983105487f, + 0.195090322f, -0.980785280f, + 0.207111376f, -0.978317371f, + 0.219101240f, -0.975702130f, + 0.231058108f, -0.972939952f, + 0.242980180f, -0.970031253f, + 0.254865660f, -0.966976471f, + 0.266712757f, -0.963776066f, + 0.278519689f, -0.960430519f, + 0.290284677f, -0.956940336f, + 0.302005949f, -0.953306040f, + 0.313681740f, -0.949528181f, + 0.325310292f, -0.945607325f, + 0.336889853f, -0.941544065f, + 0.348418680f, -0.937339012f, + 0.359895037f, -0.932992799f, + 0.371317194f, -0.928506080f, + 0.382683432f, -0.923879533f, + 0.393992040f, -0.919113852f, + 0.405241314f, -0.914209756f, + 0.416429560f, -0.909167983f, + 0.427555093f, -0.903989293f, + 0.438616239f, -0.898674466f, + 0.449611330f, -0.893224301f, + 0.460538711f, -0.887639620f, + 0.471396737f, -0.881921264f, + 0.482183772f, -0.876070094f, + 0.492898192f, -0.870086991f, + 0.503538384f, -0.863972856f, + 0.514102744f, -0.857728610f, + 0.524589683f, -0.851355193f, + 0.534997620f, -0.844853565f, + 0.545324988f, -0.838224706f, + 0.555570233f, -0.831469612f, + 0.565731811f, -0.824589303f, + 0.575808191f, -0.817584813f, + 0.585797857f, -0.810457198f, + 0.595699304f, -0.803207531f, + 0.605511041f, -0.795836905f, + 0.615231591f, -0.788346428f, + 0.624859488f, -0.780737229f, + 0.634393284f, -0.773010453f, + 0.643831543f, -0.765167266f, + 0.653172843f, -0.757208847f, + 0.662415778f, -0.749136395f, + 0.671558955f, -0.740951125f, + 0.680600998f, -0.732654272f, + 0.689540545f, -0.724247083f, + 0.698376249f, -0.715730825f, + 0.707106781f, -0.707106781f, + 0.715730825f, -0.698376249f, + 0.724247083f, -0.689540545f, + 0.732654272f, -0.680600998f, + 0.740951125f, -0.671558955f, + 0.749136395f, -0.662415778f, + 0.757208847f, -0.653172843f, + 0.765167266f, -0.643831543f, + 0.773010453f, -0.634393284f, + 0.780737229f, -0.624859488f, + 0.788346428f, -0.615231591f, + 0.795836905f, -0.605511041f, + 0.803207531f, -0.595699304f, + 0.810457198f, -0.585797857f, + 0.817584813f, -0.575808191f, + 0.824589303f, -0.565731811f, + 0.831469612f, -0.555570233f, + 0.838224706f, -0.545324988f, + 0.844853565f, -0.534997620f, + 0.851355193f, -0.524589683f, + 0.857728610f, -0.514102744f, + 0.863972856f, -0.503538384f, + 0.870086991f, -0.492898192f, + 0.876070094f, -0.482183772f, + 0.881921264f, -0.471396737f, + 0.887639620f, -0.460538711f, + 0.893224301f, -0.449611330f, + 0.898674466f, -0.438616239f, + 0.903989293f, -0.427555093f, + 0.909167983f, -0.416429560f, + 0.914209756f, -0.405241314f, + 0.919113852f, -0.393992040f, + 0.923879533f, -0.382683432f, + 0.928506080f, -0.371317194f, + 0.932992799f, -0.359895037f, + 0.937339012f, -0.348418680f, + 0.941544065f, -0.336889853f, + 0.945607325f, -0.325310292f, + 0.949528181f, -0.313681740f, + 0.953306040f, -0.302005949f, + 0.956940336f, -0.290284677f, + 0.960430519f, -0.278519689f, + 0.963776066f, -0.266712757f, + 0.966976471f, -0.254865660f, + 0.970031253f, -0.242980180f, + 0.972939952f, -0.231058108f, + 0.975702130f, -0.219101240f, + 0.978317371f, -0.207111376f, + 0.980785280f, -0.195090322f, + 0.983105487f, -0.183039888f, + 0.985277642f, -0.170961889f, + 0.987301418f, -0.158858143f, + 0.989176510f, -0.146730474f, + 0.990902635f, -0.134580709f, + 0.992479535f, -0.122410675f, + 0.993906970f, -0.110222207f, + 0.995184727f, -0.098017140f, + 0.996312612f, -0.085797312f, + 0.997290457f, -0.073564564f, + 0.998118113f, -0.061320736f, + 0.998795456f, -0.049067674f, + 0.999322385f, -0.036807223f, + 0.999698819f, -0.024541229f, + 0.999924702f, -0.012271538f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par +
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 1024, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_1024[2048] = { + 1.000000000f, 0.000000000f, + 0.999981175f, 0.006135885f, + 0.999924702f, 0.012271538f, + 0.999830582f, 0.018406730f, + 0.999698819f, 0.024541229f, + 0.999529418f, 0.030674803f, + 0.999322385f, 0.036807223f, + 0.999077728f, 0.042938257f, + 0.998795456f, 0.049067674f, + 0.998475581f, 0.055195244f, + 0.998118113f, 0.061320736f, + 0.997723067f, 0.067443920f, + 0.997290457f, 0.073564564f, + 0.996820299f, 0.079682438f, + 0.996312612f, 0.085797312f, + 0.995767414f, 0.091908956f, + 0.995184727f, 0.098017140f, + 0.994564571f, 0.104121634f, + 0.993906970f, 0.110222207f, + 0.993211949f, 0.116318631f, + 0.992479535f, 0.122410675f, + 0.991709754f, 0.128498111f, + 0.990902635f, 0.134580709f, + 0.990058210f, 0.140658239f, + 0.989176510f, 0.146730474f, + 0.988257568f, 0.152797185f, + 0.987301418f, 0.158858143f, + 0.986308097f, 0.164913120f, + 0.985277642f, 0.170961889f, + 0.984210092f, 0.177004220f, + 0.983105487f, 0.183039888f, + 0.981963869f, 0.189068664f, + 0.980785280f, 0.195090322f, + 0.979569766f, 0.201104635f, + 0.978317371f, 0.207111376f, + 0.977028143f, 0.213110320f, + 0.975702130f, 0.219101240f, + 0.974339383f, 0.225083911f, + 0.972939952f, 0.231058108f, + 0.971503891f, 0.237023606f, + 0.970031253f, 0.242980180f, + 0.968522094f, 0.248927606f, + 0.966976471f, 0.254865660f, + 0.965394442f, 0.260794118f, + 0.963776066f, 0.266712757f, + 0.962121404f, 0.272621355f, + 0.960430519f, 0.278519689f, + 0.958703475f, 0.284407537f, + 0.956940336f, 0.290284677f, + 0.955141168f, 0.296150888f, + 0.953306040f, 0.302005949f, + 0.951435021f, 0.307849640f, + 0.949528181f, 0.313681740f, + 0.947585591f, 0.319502031f, + 0.945607325f, 0.325310292f, + 0.943593458f, 0.331106306f, + 0.941544065f, 0.336889853f, + 0.939459224f, 0.342660717f, + 0.937339012f, 0.348418680f, + 0.935183510f, 0.354163525f, + 0.932992799f, 0.359895037f, + 0.930766961f, 0.365612998f, + 0.928506080f, 0.371317194f, + 0.926210242f, 0.377007410f, + 0.923879533f, 0.382683432f, + 0.921514039f, 0.388345047f, + 0.919113852f, 0.393992040f, + 0.916679060f, 0.399624200f, + 0.914209756f, 0.405241314f, + 0.911706032f, 0.410843171f, + 0.909167983f, 0.416429560f, + 0.906595705f, 0.422000271f, + 0.903989293f, 0.427555093f, + 0.901348847f, 0.433093819f, + 0.898674466f, 0.438616239f, + 0.895966250f, 0.444122145f, + 0.893224301f, 0.449611330f, + 0.890448723f, 0.455083587f, + 0.887639620f, 0.460538711f, + 0.884797098f, 0.465976496f, + 0.881921264f, 0.471396737f, + 0.879012226f, 0.476799230f, + 0.876070094f, 0.482183772f, + 0.873094978f, 0.487550160f, + 0.870086991f, 0.492898192f, + 0.867046246f, 0.498227667f, + 0.863972856f, 0.503538384f, + 0.860866939f, 0.508830143f, + 0.857728610f, 0.514102744f, + 0.854557988f, 0.519355990f, + 0.851355193f, 0.524589683f, + 0.848120345f, 0.529803625f, + 0.844853565f, 0.534997620f, + 0.841554977f, 0.540171473f, + 0.838224706f, 0.545324988f, + 0.834862875f, 0.550457973f, + 0.831469612f, 0.555570233f, + 0.828045045f, 0.560661576f, + 0.824589303f, 0.565731811f, + 0.821102515f, 0.570780746f, + 0.817584813f, 0.575808191f, + 0.814036330f, 0.580813958f, + 0.810457198f, 0.585797857f, + 0.806847554f, 0.590759702f, + 0.803207531f, 0.595699304f, + 0.799537269f, 0.600616479f, + 0.795836905f, 0.605511041f, + 0.792106577f, 0.610382806f, + 0.788346428f, 0.615231591f, + 0.784556597f, 0.620057212f, + 0.780737229f, 0.624859488f, + 0.776888466f, 0.629638239f, + 0.773010453f, 0.634393284f, + 0.769103338f, 0.639124445f, + 0.765167266f, 0.643831543f, + 0.761202385f, 0.648514401f, + 0.757208847f, 0.653172843f, + 0.753186799f, 0.657806693f, + 0.749136395f, 0.662415778f, + 0.745057785f, 0.666999922f, + 0.740951125f, 0.671558955f, + 0.736816569f, 0.676092704f, + 0.732654272f, 0.680600998f, + 0.728464390f, 0.685083668f, + 0.724247083f, 0.689540545f, + 0.720002508f, 0.693971461f, + 0.715730825f, 0.698376249f, + 0.711432196f, 0.702754744f, + 0.707106781f, 0.707106781f, + 0.702754744f, 0.711432196f, + 0.698376249f, 0.715730825f, + 0.693971461f, 0.720002508f, + 0.689540545f, 0.724247083f, + 0.685083668f, 0.728464390f, + 0.680600998f, 0.732654272f, + 0.676092704f, 0.736816569f, + 0.671558955f, 0.740951125f, + 0.666999922f, 0.745057785f, + 0.662415778f, 0.749136395f, + 0.657806693f, 0.753186799f, + 0.653172843f, 0.757208847f, + 0.648514401f, 0.761202385f, + 0.643831543f, 0.765167266f, + 0.639124445f, 0.769103338f, + 0.634393284f, 0.773010453f, + 0.629638239f, 0.776888466f, + 0.624859488f, 0.780737229f, + 0.620057212f, 0.784556597f, + 0.615231591f, 0.788346428f, + 0.610382806f, 0.792106577f, + 0.605511041f, 0.795836905f, + 0.600616479f, 0.799537269f, + 0.595699304f, 0.803207531f, + 0.590759702f, 0.806847554f, + 0.585797857f, 0.810457198f, + 0.580813958f, 0.814036330f, + 0.575808191f, 0.817584813f, + 0.570780746f, 0.821102515f, + 0.565731811f, 0.824589303f, + 0.560661576f, 0.828045045f, + 0.555570233f, 0.831469612f, + 0.550457973f, 0.834862875f, + 0.545324988f, 0.838224706f, + 0.540171473f, 0.841554977f, + 0.534997620f, 0.844853565f, + 0.529803625f, 0.848120345f, + 0.524589683f, 0.851355193f, + 0.519355990f, 0.854557988f, + 0.514102744f, 0.857728610f, + 0.508830143f, 0.860866939f, + 0.503538384f, 0.863972856f, + 0.498227667f, 0.867046246f, + 0.492898192f, 0.870086991f, + 0.487550160f, 0.873094978f, + 0.482183772f, 0.876070094f, + 0.476799230f, 0.879012226f, + 0.471396737f, 0.881921264f, + 0.465976496f, 0.884797098f, + 0.460538711f, 0.887639620f, + 0.455083587f, 0.890448723f, + 0.449611330f, 0.893224301f, + 0.444122145f, 0.895966250f, + 0.438616239f, 0.898674466f, + 0.433093819f, 0.901348847f, + 0.427555093f, 0.903989293f, + 0.422000271f, 0.906595705f, + 0.416429560f, 0.909167983f, + 0.410843171f, 0.911706032f, + 0.405241314f, 0.914209756f, + 0.399624200f, 0.916679060f, + 0.393992040f, 0.919113852f, + 0.388345047f, 0.921514039f, + 0.382683432f, 0.923879533f, + 0.377007410f, 0.926210242f, + 0.371317194f, 0.928506080f, + 0.365612998f, 0.930766961f, + 0.359895037f, 0.932992799f, + 0.354163525f, 0.935183510f, + 0.348418680f, 0.937339012f, + 0.342660717f, 0.939459224f, + 0.336889853f, 0.941544065f, + 0.331106306f, 0.943593458f, + 0.325310292f, 0.945607325f, + 0.319502031f, 0.947585591f, + 0.313681740f, 0.949528181f, + 0.307849640f, 0.951435021f, + 0.302005949f, 0.953306040f, + 0.296150888f, 0.955141168f, + 0.290284677f, 0.956940336f, + 0.284407537f, 0.958703475f, + 0.278519689f, 0.960430519f, + 0.272621355f, 0.962121404f, + 0.266712757f, 0.963776066f, + 0.260794118f, 0.965394442f, + 0.254865660f, 0.966976471f, + 0.248927606f, 0.968522094f, + 0.242980180f, 0.970031253f, + 0.237023606f, 0.971503891f, + 0.231058108f, 0.972939952f, + 0.225083911f, 0.974339383f, + 0.219101240f, 0.975702130f, + 0.213110320f, 0.977028143f, + 0.207111376f, 0.978317371f, + 0.201104635f, 0.979569766f, + 0.195090322f, 0.980785280f, + 0.189068664f, 0.981963869f, + 0.183039888f, 0.983105487f, + 0.177004220f, 0.984210092f, + 0.170961889f, 0.985277642f, + 0.164913120f, 0.986308097f, + 0.158858143f, 0.987301418f, + 0.152797185f, 0.988257568f, + 0.146730474f, 0.989176510f, + 0.140658239f, 0.990058210f, + 0.134580709f, 0.990902635f, + 0.128498111f, 0.991709754f, + 0.122410675f, 0.992479535f, + 0.116318631f, 0.993211949f, + 0.110222207f, 0.993906970f, + 0.104121634f, 0.994564571f, + 0.098017140f, 0.995184727f, + 0.091908956f, 0.995767414f, + 0.085797312f, 0.996312612f, + 0.079682438f, 0.996820299f, + 0.073564564f, 0.997290457f, + 0.067443920f, 0.997723067f, + 0.061320736f, 0.998118113f, + 0.055195244f, 0.998475581f, + 0.049067674f, 0.998795456f, + 0.042938257f, 0.999077728f, + 0.036807223f, 0.999322385f, + 0.030674803f, 0.999529418f, + 0.024541229f, 0.999698819f, + 0.018406730f, 0.999830582f, + 0.012271538f, 0.999924702f, + 0.006135885f, 0.999981175f, + 0.000000000f, 1.000000000f, + -0.006135885f, 0.999981175f, + -0.012271538f, 0.999924702f, + -0.018406730f, 0.999830582f, + -0.024541229f, 0.999698819f, + -0.030674803f, 0.999529418f, + -0.036807223f, 0.999322385f, + -0.042938257f, 0.999077728f, + -0.049067674f, 0.998795456f, + -0.055195244f, 0.998475581f, + -0.061320736f, 0.998118113f, + -0.067443920f, 0.997723067f, + -0.073564564f, 0.997290457f, + -0.079682438f, 0.996820299f, + -0.085797312f, 0.996312612f, + -0.091908956f, 0.995767414f, + -0.098017140f, 0.995184727f, + -0.104121634f, 0.994564571f, + -0.110222207f, 0.993906970f, + -0.116318631f, 0.993211949f, + -0.122410675f, 0.992479535f, + -0.128498111f, 0.991709754f, + -0.134580709f, 0.990902635f, + -0.140658239f, 0.990058210f, + -0.146730474f, 0.989176510f, + -0.152797185f, 0.988257568f, + -0.158858143f, 0.987301418f, + -0.164913120f, 0.986308097f, + -0.170961889f, 0.985277642f, + -0.177004220f, 0.984210092f, + -0.183039888f, 0.983105487f, + -0.189068664f, 0.981963869f, + -0.195090322f, 0.980785280f, + -0.201104635f, 0.979569766f, + -0.207111376f, 0.978317371f, + -0.213110320f, 0.977028143f, + -0.219101240f, 0.975702130f, + -0.225083911f, 0.974339383f, + -0.231058108f, 0.972939952f, + -0.237023606f, 0.971503891f, + -0.242980180f, 0.970031253f, + -0.248927606f, 0.968522094f, + -0.254865660f, 0.966976471f, + -0.260794118f, 0.965394442f, + -0.266712757f, 0.963776066f, + -0.272621355f, 0.962121404f, + -0.278519689f, 0.960430519f, + -0.284407537f, 0.958703475f, + -0.290284677f, 0.956940336f, + -0.296150888f, 0.955141168f, + -0.302005949f, 0.953306040f, + -0.307849640f, 0.951435021f, + -0.313681740f, 0.949528181f, + -0.319502031f, 0.947585591f, + -0.325310292f, 0.945607325f, + -0.331106306f, 0.943593458f, + -0.336889853f, 0.941544065f, + -0.342660717f, 0.939459224f, + -0.348418680f, 0.937339012f, + -0.354163525f, 0.935183510f, + -0.359895037f, 0.932992799f, + -0.365612998f, 0.930766961f, + -0.371317194f, 0.928506080f, + -0.377007410f, 0.926210242f, + -0.382683432f, 0.923879533f, + -0.388345047f, 0.921514039f, + -0.393992040f, 0.919113852f, + -0.399624200f, 0.916679060f, + -0.405241314f, 0.914209756f, + -0.410843171f, 0.911706032f, + -0.416429560f, 0.909167983f, + -0.422000271f, 0.906595705f, + -0.427555093f, 0.903989293f, + -0.433093819f, 0.901348847f, + -0.438616239f, 0.898674466f, + -0.444122145f, 0.895966250f, + -0.449611330f, 0.893224301f, + -0.455083587f, 0.890448723f, + -0.460538711f, 0.887639620f, + -0.465976496f, 0.884797098f, + -0.471396737f, 0.881921264f, + -0.476799230f, 0.879012226f, + -0.482183772f, 0.876070094f, + -0.487550160f, 0.873094978f, + -0.492898192f, 0.870086991f, + -0.498227667f, 0.867046246f, + -0.503538384f, 0.863972856f, + -0.508830143f, 0.860866939f, + -0.514102744f, 0.857728610f, + -0.519355990f, 0.854557988f, + -0.524589683f, 0.851355193f, + -0.529803625f, 0.848120345f, + -0.534997620f, 0.844853565f, + -0.540171473f, 0.841554977f, + -0.545324988f, 0.838224706f, + -0.550457973f, 0.834862875f, + -0.555570233f, 0.831469612f, + -0.560661576f, 0.828045045f, + -0.565731811f, 0.824589303f, + -0.570780746f, 0.821102515f, + -0.575808191f, 0.817584813f, + -0.580813958f, 0.814036330f, + -0.585797857f, 0.810457198f, + -0.590759702f, 0.806847554f, + -0.595699304f, 0.803207531f, + -0.600616479f, 0.799537269f, + -0.605511041f, 0.795836905f, + -0.610382806f, 0.792106577f, + -0.615231591f, 0.788346428f, + -0.620057212f, 0.784556597f, + -0.624859488f, 0.780737229f, + -0.629638239f, 0.776888466f, + -0.634393284f, 0.773010453f, + -0.639124445f, 0.769103338f, + -0.643831543f, 0.765167266f, + -0.648514401f, 0.761202385f, + -0.653172843f, 0.757208847f, + -0.657806693f, 0.753186799f, + -0.662415778f, 0.749136395f, + -0.666999922f, 0.745057785f, + -0.671558955f, 0.740951125f, + -0.676092704f, 0.736816569f, + -0.680600998f, 0.732654272f, + -0.685083668f, 0.728464390f, + -0.689540545f, 0.724247083f, + -0.693971461f, 0.720002508f, + -0.698376249f, 0.715730825f, + -0.702754744f, 0.711432196f, + -0.707106781f, 0.707106781f, + -0.711432196f, 0.702754744f, + -0.715730825f, 0.698376249f, + -0.720002508f, 0.693971461f, + -0.724247083f, 0.689540545f, + -0.728464390f, 0.685083668f, + -0.732654272f, 0.680600998f, + -0.736816569f, 0.676092704f, + -0.740951125f, 0.671558955f, + -0.745057785f, 0.666999922f, + -0.749136395f, 0.662415778f, + -0.753186799f, 0.657806693f, + -0.757208847f, 0.653172843f, + -0.761202385f, 0.648514401f, + -0.765167266f, 0.643831543f, + -0.769103338f, 0.639124445f, + -0.773010453f, 0.634393284f, + -0.776888466f, 0.629638239f, + -0.780737229f, 0.624859488f, + -0.784556597f, 0.620057212f, + -0.788346428f, 0.615231591f, + -0.792106577f, 0.610382806f, + -0.795836905f, 0.605511041f, + -0.799537269f, 0.600616479f, + -0.803207531f, 0.595699304f, + -0.806847554f, 0.590759702f, + -0.810457198f, 0.585797857f, + -0.814036330f, 0.580813958f, + -0.817584813f, 0.575808191f, + -0.821102515f, 0.570780746f, + -0.824589303f, 0.565731811f, + -0.828045045f, 0.560661576f, + -0.831469612f, 0.555570233f, + -0.834862875f, 0.550457973f, + -0.838224706f, 0.545324988f, + -0.841554977f, 0.540171473f, + -0.844853565f, 0.534997620f, + -0.848120345f, 0.529803625f, + -0.851355193f, 0.524589683f, + -0.854557988f, 0.519355990f, + -0.857728610f, 0.514102744f, + -0.860866939f, 0.508830143f, + -0.863972856f, 0.503538384f, + -0.867046246f, 0.498227667f, + -0.870086991f, 0.492898192f, + -0.873094978f, 0.487550160f, + -0.876070094f, 0.482183772f, + -0.879012226f, 0.476799230f, + -0.881921264f, 0.471396737f, + -0.884797098f, 0.465976496f, + -0.887639620f, 0.460538711f, + -0.890448723f, 0.455083587f, + -0.893224301f, 0.449611330f, + -0.895966250f, 0.444122145f, + -0.898674466f, 0.438616239f, + -0.901348847f, 0.433093819f, + -0.903989293f, 0.427555093f, + -0.906595705f, 0.422000271f, + -0.909167983f, 0.416429560f, + -0.911706032f, 0.410843171f, + -0.914209756f, 0.405241314f, + -0.916679060f, 0.399624200f, + -0.919113852f, 0.393992040f, + -0.921514039f, 0.388345047f, + -0.923879533f, 0.382683432f, + -0.926210242f, 0.377007410f, + -0.928506080f, 0.371317194f, + -0.930766961f, 0.365612998f, + -0.932992799f, 0.359895037f, + -0.935183510f, 0.354163525f, + -0.937339012f, 0.348418680f, + -0.939459224f, 0.342660717f, + -0.941544065f, 0.336889853f, + -0.943593458f, 0.331106306f, + -0.945607325f, 0.325310292f, + -0.947585591f, 0.319502031f, + -0.949528181f, 0.313681740f, + -0.951435021f, 0.307849640f, + -0.953306040f, 0.302005949f, + -0.955141168f, 0.296150888f, + -0.956940336f, 0.290284677f, + -0.958703475f, 0.284407537f, + -0.960430519f, 0.278519689f, + -0.962121404f, 0.272621355f, + -0.963776066f, 0.266712757f, + -0.965394442f, 0.260794118f, + -0.966976471f, 0.254865660f, + -0.968522094f, 0.248927606f, + -0.970031253f, 0.242980180f, + -0.971503891f, 0.237023606f, + -0.972939952f, 0.231058108f, + -0.974339383f, 0.225083911f, + -0.975702130f, 0.219101240f, + -0.977028143f, 0.213110320f, + -0.978317371f, 0.207111376f, + -0.979569766f, 0.201104635f, + -0.980785280f, 0.195090322f, + -0.981963869f, 0.189068664f, + -0.983105487f, 0.183039888f, + -0.984210092f, 0.177004220f, + -0.985277642f, 0.170961889f, + -0.986308097f, 0.164913120f, + -0.987301418f, 0.158858143f, + -0.988257568f, 0.152797185f, + -0.989176510f, 0.146730474f, + -0.990058210f, 0.140658239f, + -0.990902635f, 0.134580709f, + -0.991709754f, 0.128498111f, + -0.992479535f, 0.122410675f, + -0.993211949f, 0.116318631f, + -0.993906970f, 0.110222207f, + -0.994564571f, 0.104121634f, + -0.995184727f, 0.098017140f, + -0.995767414f, 0.091908956f, + -0.996312612f, 0.085797312f, + -0.996820299f, 0.079682438f, + -0.997290457f, 0.073564564f, + -0.997723067f, 0.067443920f, + -0.998118113f, 0.061320736f, + -0.998475581f, 0.055195244f, + -0.998795456f, 0.049067674f, + -0.999077728f, 0.042938257f, + -0.999322385f, 0.036807223f, + -0.999529418f, 0.030674803f, + -0.999698819f, 0.024541229f, + -0.999830582f, 0.018406730f, + -0.999924702f, 0.012271538f, + -0.999981175f, 0.006135885f, + -1.000000000f, 0.000000000f, + -0.999981175f, -0.006135885f, + -0.999924702f, -0.012271538f, + -0.999830582f, -0.018406730f, + -0.999698819f, -0.024541229f, + -0.999529418f, -0.030674803f, + -0.999322385f, -0.036807223f, + -0.999077728f, -0.042938257f, + -0.998795456f, -0.049067674f, + -0.998475581f, -0.055195244f, + -0.998118113f, -0.061320736f, + -0.997723067f, -0.067443920f, + -0.997290457f, -0.073564564f, + -0.996820299f, -0.079682438f, + -0.996312612f, -0.085797312f, + -0.995767414f, -0.091908956f, + -0.995184727f, -0.098017140f, + -0.994564571f, -0.104121634f, + -0.993906970f, -0.110222207f, + -0.993211949f, -0.116318631f, + -0.992479535f, -0.122410675f, + -0.991709754f, -0.128498111f, + -0.990902635f, -0.134580709f, + -0.990058210f, -0.140658239f, + -0.989176510f, -0.146730474f, + -0.988257568f, -0.152797185f, + -0.987301418f, -0.158858143f, + -0.986308097f, -0.164913120f, + -0.985277642f, -0.170961889f, + -0.984210092f, -0.177004220f, + -0.983105487f, -0.183039888f, + -0.981963869f, -0.189068664f, + -0.980785280f, -0.195090322f, + -0.979569766f, -0.201104635f, + -0.978317371f, -0.207111376f, + -0.977028143f, -0.213110320f, + -0.975702130f, -0.219101240f, + -0.974339383f, -0.225083911f, + -0.972939952f, -0.231058108f, + -0.971503891f, -0.237023606f, + -0.970031253f, -0.242980180f, + -0.968522094f, -0.248927606f, + -0.966976471f, -0.254865660f, + -0.965394442f, -0.260794118f, + -0.963776066f, -0.266712757f, + -0.962121404f, -0.272621355f, + -0.960430519f, -0.278519689f, + -0.958703475f, -0.284407537f, + -0.956940336f, -0.290284677f, + -0.955141168f, -0.296150888f, + -0.953306040f, -0.302005949f, + -0.951435021f, -0.307849640f, + -0.949528181f, -0.313681740f, + -0.947585591f, -0.319502031f, + -0.945607325f, -0.325310292f, + -0.943593458f, -0.331106306f, + -0.941544065f, -0.336889853f, + -0.939459224f, -0.342660717f, + -0.937339012f, -0.348418680f, + -0.935183510f, -0.354163525f, + -0.932992799f, -0.359895037f, + -0.930766961f, -0.365612998f, + -0.928506080f, -0.371317194f, + -0.926210242f, -0.377007410f, + -0.923879533f, -0.382683432f, + -0.921514039f, -0.388345047f, + -0.919113852f, -0.393992040f, + -0.916679060f, -0.399624200f, + -0.914209756f, -0.405241314f, + -0.911706032f, -0.410843171f, + -0.909167983f, -0.416429560f, + -0.906595705f, -0.422000271f, + -0.903989293f, -0.427555093f, + -0.901348847f, -0.433093819f, + -0.898674466f, -0.438616239f, + -0.895966250f, -0.444122145f, + -0.893224301f, -0.449611330f, + -0.890448723f, -0.455083587f, + -0.887639620f, -0.460538711f, + -0.884797098f, -0.465976496f, + -0.881921264f, -0.471396737f, + -0.879012226f, -0.476799230f, + -0.876070094f, -0.482183772f, + -0.873094978f, -0.487550160f, + -0.870086991f, -0.492898192f, + -0.867046246f, -0.498227667f, + -0.863972856f, -0.503538384f, + -0.860866939f, -0.508830143f, + -0.857728610f, -0.514102744f, + -0.854557988f, -0.519355990f, + -0.851355193f, -0.524589683f, + -0.848120345f, -0.529803625f, + -0.844853565f, -0.534997620f, + -0.841554977f, -0.540171473f, + -0.838224706f, -0.545324988f, + -0.834862875f, -0.550457973f, + -0.831469612f, -0.555570233f, + -0.828045045f, -0.560661576f, + -0.824589303f, -0.565731811f, + -0.821102515f, -0.570780746f, + -0.817584813f, -0.575808191f, + -0.814036330f, -0.580813958f, + -0.810457198f, -0.585797857f, + -0.806847554f, -0.590759702f, + -0.803207531f, -0.595699304f, + -0.799537269f, -0.600616479f, + -0.795836905f, -0.605511041f, + -0.792106577f, -0.610382806f, + -0.788346428f, -0.615231591f, + -0.784556597f, -0.620057212f, + -0.780737229f, -0.624859488f, + -0.776888466f, -0.629638239f, + -0.773010453f, -0.634393284f, + -0.769103338f, -0.639124445f, + -0.765167266f, -0.643831543f, + -0.761202385f, -0.648514401f, + -0.757208847f, -0.653172843f, + -0.753186799f, -0.657806693f, + -0.749136395f, -0.662415778f, + -0.745057785f, -0.666999922f, + -0.740951125f, -0.671558955f, + -0.736816569f, -0.676092704f, + -0.732654272f, -0.680600998f, + -0.728464390f, -0.685083668f, + -0.724247083f, -0.689540545f, + -0.720002508f, -0.693971461f, + -0.715730825f, -0.698376249f, + -0.711432196f, -0.702754744f, + -0.707106781f, -0.707106781f, + -0.702754744f, -0.711432196f, + -0.698376249f, -0.715730825f, + -0.693971461f, -0.720002508f, + -0.689540545f, -0.724247083f, + -0.685083668f, -0.728464390f, + -0.680600998f, -0.732654272f, + -0.676092704f, -0.736816569f, + -0.671558955f, -0.740951125f, + -0.666999922f, -0.745057785f, + -0.662415778f, -0.749136395f, + -0.657806693f, -0.753186799f, + -0.653172843f, -0.757208847f, + -0.648514401f, -0.761202385f, + -0.643831543f, -0.765167266f, + -0.639124445f, -0.769103338f, + -0.634393284f, -0.773010453f, + -0.629638239f, -0.776888466f, + -0.624859488f, -0.780737229f, + -0.620057212f, -0.784556597f, + -0.615231591f, -0.788346428f, + -0.610382806f, -0.792106577f, + -0.605511041f, -0.795836905f, + -0.600616479f, -0.799537269f, + -0.595699304f, -0.803207531f, + -0.590759702f, -0.806847554f, + -0.585797857f, -0.810457198f, + -0.580813958f, -0.814036330f, + -0.575808191f, -0.817584813f, + -0.570780746f, -0.821102515f, + -0.565731811f, -0.824589303f, + -0.560661576f, -0.828045045f, + -0.555570233f, -0.831469612f, + -0.550457973f, -0.834862875f, + -0.545324988f, -0.838224706f, + -0.540171473f, -0.841554977f, + -0.534997620f, -0.844853565f, + -0.529803625f, -0.848120345f, + -0.524589683f, -0.851355193f, + -0.519355990f, -0.854557988f, + -0.514102744f, -0.857728610f, + -0.508830143f, -0.860866939f, + -0.503538384f, -0.863972856f, + -0.498227667f, -0.867046246f, + -0.492898192f, -0.870086991f, + -0.487550160f, -0.873094978f, + -0.482183772f, -0.876070094f, + -0.476799230f, -0.879012226f, + -0.471396737f, -0.881921264f, + -0.465976496f, -0.884797098f, + -0.460538711f, -0.887639620f, + -0.455083587f, -0.890448723f, + -0.449611330f, -0.893224301f, + -0.444122145f, -0.895966250f, + -0.438616239f, -0.898674466f, + -0.433093819f, -0.901348847f, + -0.427555093f, -0.903989293f, + -0.422000271f, -0.906595705f, + -0.416429560f, -0.909167983f, + -0.410843171f, -0.911706032f, + -0.405241314f, -0.914209756f, + -0.399624200f, -0.916679060f, + -0.393992040f, -0.919113852f, + -0.388345047f, -0.921514039f, + -0.382683432f, -0.923879533f, + -0.377007410f, -0.926210242f, + -0.371317194f, -0.928506080f, + -0.365612998f, -0.930766961f, + -0.359895037f, -0.932992799f, + -0.354163525f, -0.935183510f, + -0.348418680f, -0.937339012f, + -0.342660717f, -0.939459224f, + -0.336889853f, -0.941544065f, + -0.331106306f, -0.943593458f, + -0.325310292f, -0.945607325f, + -0.319502031f, -0.947585591f, + -0.313681740f, -0.949528181f, + -0.307849640f, -0.951435021f, + -0.302005949f, -0.953306040f, + -0.296150888f, -0.955141168f, + -0.290284677f, -0.956940336f, + -0.284407537f, -0.958703475f, + -0.278519689f, -0.960430519f, + -0.272621355f, -0.962121404f, + -0.266712757f, -0.963776066f, + -0.260794118f, -0.965394442f, + -0.254865660f, -0.966976471f, + -0.248927606f, -0.968522094f, + -0.242980180f, -0.970031253f, + -0.237023606f, -0.971503891f, + -0.231058108f, -0.972939952f, + -0.225083911f, -0.974339383f, + -0.219101240f, -0.975702130f, + -0.213110320f, -0.977028143f, + -0.207111376f, -0.978317371f, + -0.201104635f, -0.979569766f, + -0.195090322f, -0.980785280f, + -0.189068664f, -0.981963869f, + -0.183039888f, -0.983105487f, + -0.177004220f, -0.984210092f, + -0.170961889f, -0.985277642f, + -0.164913120f, -0.986308097f, + -0.158858143f, -0.987301418f, + -0.152797185f, -0.988257568f, + -0.146730474f, -0.989176510f, + -0.140658239f, -0.990058210f, + -0.134580709f, -0.990902635f, + -0.128498111f, -0.991709754f, + -0.122410675f, -0.992479535f, + -0.116318631f, -0.993211949f, + -0.110222207f, -0.993906970f, + -0.104121634f, -0.994564571f, + -0.098017140f, -0.995184727f, + -0.091908956f, -0.995767414f, + -0.085797312f, -0.996312612f, + -0.079682438f, -0.996820299f, + -0.073564564f, -0.997290457f, + -0.067443920f, -0.997723067f, + -0.061320736f, -0.998118113f, + -0.055195244f, -0.998475581f, + -0.049067674f, -0.998795456f, + -0.042938257f, -0.999077728f, + -0.036807223f, -0.999322385f, + -0.030674803f, -0.999529418f, + -0.024541229f, -0.999698819f, + -0.018406730f, -0.999830582f, + -0.012271538f, -0.999924702f, + -0.006135885f, -0.999981175f, + -0.000000000f, -1.000000000f, + 0.006135885f, -0.999981175f, + 0.012271538f, -0.999924702f, + 0.018406730f, -0.999830582f, + 0.024541229f, -0.999698819f, + 0.030674803f, -0.999529418f, + 0.036807223f, -0.999322385f, + 0.042938257f, -0.999077728f, + 0.049067674f, -0.998795456f, + 0.055195244f, -0.998475581f, + 0.061320736f, -0.998118113f, + 0.067443920f, -0.997723067f, + 0.073564564f, -0.997290457f, + 0.079682438f, -0.996820299f, + 0.085797312f, -0.996312612f, + 0.091908956f, -0.995767414f, + 0.098017140f, -0.995184727f, + 0.104121634f, -0.994564571f, + 0.110222207f, -0.993906970f, + 0.116318631f, -0.993211949f, + 0.122410675f, -0.992479535f, + 0.128498111f, -0.991709754f, + 0.134580709f, -0.990902635f, + 0.140658239f, -0.990058210f, + 0.146730474f, -0.989176510f, + 0.152797185f, -0.988257568f, + 0.158858143f, -0.987301418f, + 0.164913120f, -0.986308097f, + 0.170961889f, -0.985277642f, + 0.177004220f, -0.984210092f, + 0.183039888f, -0.983105487f, + 0.189068664f, -0.981963869f, + 0.195090322f, -0.980785280f, + 0.201104635f, -0.979569766f, + 0.207111376f, -0.978317371f, + 0.213110320f, -0.977028143f, + 0.219101240f, -0.975702130f, + 0.225083911f, -0.974339383f, + 0.231058108f, -0.972939952f, + 0.237023606f, -0.971503891f, + 0.242980180f, -0.970031253f, + 0.248927606f, -0.968522094f, + 0.254865660f, -0.966976471f, + 0.260794118f, -0.965394442f, + 0.266712757f, -0.963776066f, + 0.272621355f, -0.962121404f, + 0.278519689f, -0.960430519f, + 0.284407537f, -0.958703475f, + 0.290284677f, -0.956940336f, + 0.296150888f, -0.955141168f, + 0.302005949f, -0.953306040f, + 0.307849640f, -0.951435021f, + 0.313681740f, -0.949528181f, + 0.319502031f, -0.947585591f, + 0.325310292f, -0.945607325f, + 0.331106306f, -0.943593458f, + 0.336889853f, -0.941544065f, + 0.342660717f, -0.939459224f, + 0.348418680f, -0.937339012f, + 0.354163525f, -0.935183510f, + 0.359895037f, -0.932992799f, + 0.365612998f, -0.930766961f, + 0.371317194f, -0.928506080f, + 0.377007410f, -0.926210242f, + 0.382683432f, -0.923879533f, + 0.388345047f, -0.921514039f, + 0.393992040f, -0.919113852f, + 0.399624200f, -0.916679060f, + 0.405241314f, -0.914209756f, + 0.410843171f, -0.911706032f, + 0.416429560f, -0.909167983f, + 0.422000271f, -0.906595705f, + 0.427555093f, -0.903989293f, + 0.433093819f, -0.901348847f, + 0.438616239f, -0.898674466f, + 0.444122145f, -0.895966250f, + 0.449611330f, -0.893224301f, + 0.455083587f, -0.890448723f, + 0.460538711f, -0.887639620f, + 0.465976496f, -0.884797098f, + 0.471396737f, -0.881921264f, + 0.476799230f, -0.879012226f, + 0.482183772f, -0.876070094f, + 0.487550160f, -0.873094978f, + 0.492898192f, -0.870086991f, + 0.498227667f, -0.867046246f, + 0.503538384f, -0.863972856f, + 0.508830143f, -0.860866939f, + 0.514102744f, -0.857728610f, + 0.519355990f, -0.854557988f, + 0.524589683f, -0.851355193f, + 0.529803625f, -0.848120345f, + 0.534997620f, -0.844853565f, + 0.540171473f, -0.841554977f, + 0.545324988f, -0.838224706f, + 0.550457973f, -0.834862875f, + 0.555570233f, -0.831469612f, + 0.560661576f, -0.828045045f, + 0.565731811f, -0.824589303f, + 0.570780746f, -0.821102515f, + 0.575808191f, -0.817584813f, + 0.580813958f, -0.814036330f, + 0.585797857f, -0.810457198f, + 0.590759702f, -0.806847554f, + 0.595699304f, -0.803207531f, + 0.600616479f, -0.799537269f, + 0.605511041f, -0.795836905f, + 0.610382806f, -0.792106577f, + 0.615231591f, -0.788346428f, + 0.620057212f, -0.784556597f, + 0.624859488f, -0.780737229f, + 0.629638239f, -0.776888466f, + 0.634393284f, -0.773010453f, + 0.639124445f, -0.769103338f, + 0.643831543f, -0.765167266f, + 0.648514401f, -0.761202385f, + 0.653172843f, -0.757208847f, + 0.657806693f, -0.753186799f, + 0.662415778f, -0.749136395f, + 0.666999922f, -0.745057785f, + 0.671558955f, -0.740951125f, + 0.676092704f, -0.736816569f, + 0.680600998f, -0.732654272f, + 0.685083668f, -0.728464390f, + 0.689540545f, -0.724247083f, + 0.693971461f, -0.720002508f, + 0.698376249f, -0.715730825f, + 0.702754744f, -0.711432196f, + 0.707106781f, -0.707106781f, + 0.711432196f, -0.702754744f, + 0.715730825f, -0.698376249f, + 0.720002508f, -0.693971461f, + 0.724247083f, -0.689540545f, + 0.728464390f, -0.685083668f, + 0.732654272f, -0.680600998f, + 0.736816569f, -0.676092704f, + 0.740951125f, -0.671558955f, + 0.745057785f, -0.666999922f, + 0.749136395f, -0.662415778f, + 0.753186799f, -0.657806693f, + 0.757208847f, -0.653172843f, + 0.761202385f, -0.648514401f, + 0.765167266f, -0.643831543f, + 0.769103338f, -0.639124445f, + 0.773010453f, -0.634393284f, + 0.776888466f, -0.629638239f, + 0.780737229f, -0.624859488f, + 0.784556597f, -0.620057212f, + 0.788346428f, -0.615231591f, + 0.792106577f, -0.610382806f, + 0.795836905f, -0.605511041f, + 0.799537269f, -0.600616479f, + 0.803207531f, -0.595699304f, + 0.806847554f, -0.590759702f, + 0.810457198f, -0.585797857f, + 0.814036330f, -0.580813958f, + 0.817584813f, -0.575808191f, + 0.821102515f, -0.570780746f, + 0.824589303f, -0.565731811f, + 0.828045045f, -0.560661576f, + 0.831469612f, -0.555570233f, + 0.834862875f, -0.550457973f, + 0.838224706f, -0.545324988f, + 0.841554977f, -0.540171473f, + 0.844853565f, -0.534997620f, + 0.848120345f, -0.529803625f, + 0.851355193f, -0.524589683f, + 0.854557988f, -0.519355990f, + 0.857728610f, -0.514102744f, + 0.860866939f, -0.508830143f, + 0.863972856f, -0.503538384f, + 0.867046246f, -0.498227667f, + 0.870086991f, -0.492898192f, + 0.873094978f, -0.487550160f, + 0.876070094f, -0.482183772f, + 0.879012226f, -0.476799230f, + 0.881921264f, -0.471396737f, + 0.884797098f, -0.465976496f, + 0.887639620f, -0.460538711f, + 0.890448723f, -0.455083587f, + 0.893224301f, -0.449611330f, + 0.895966250f, -0.444122145f, + 0.898674466f, -0.438616239f, + 0.901348847f, -0.433093819f, + 0.903989293f, -0.427555093f, + 0.906595705f, -0.422000271f, + 0.909167983f, -0.416429560f, + 0.911706032f, -0.410843171f, + 0.914209756f, -0.405241314f, + 0.916679060f, -0.399624200f, + 0.919113852f, -0.393992040f, + 0.921514039f, -0.388345047f, + 0.923879533f, -0.382683432f, + 0.926210242f, -0.377007410f, + 0.928506080f, -0.371317194f, + 0.930766961f, -0.365612998f, + 0.932992799f, -0.359895037f, + 0.935183510f, -0.354163525f, + 0.937339012f, -0.348418680f, + 0.939459224f, -0.342660717f, + 0.941544065f, -0.336889853f, + 0.943593458f, -0.331106306f, + 0.945607325f, -0.325310292f, + 0.947585591f, -0.319502031f, + 0.949528181f, -0.313681740f, + 0.951435021f, -0.307849640f, + 0.953306040f, -0.302005949f, + 0.955141168f, -0.296150888f, + 0.956940336f, -0.290284677f, + 0.958703475f, -0.284407537f, + 0.960430519f, -0.278519689f, + 0.962121404f, -0.272621355f, + 0.963776066f, -0.266712757f, + 0.965394442f, -0.260794118f, + 0.966976471f, -0.254865660f, + 0.968522094f, -0.248927606f, + 0.970031253f, -0.242980180f, + 0.971503891f, -0.237023606f, + 0.972939952f, -0.231058108f, + 0.974339383f, -0.225083911f, + 0.975702130f, -0.219101240f, + 0.977028143f, -0.213110320f, + 0.978317371f, -0.207111376f, + 0.979569766f, -0.201104635f, + 0.980785280f, -0.195090322f, + 0.981963869f, -0.189068664f, + 0.983105487f, -0.183039888f, + 0.984210092f, -0.177004220f, + 0.985277642f, -0.170961889f, + 0.986308097f, -0.164913120f, + 0.987301418f, -0.158858143f, + 0.988257568f, -0.152797185f, + 0.989176510f, -0.146730474f, + 0.990058210f, -0.140658239f, + 0.990902635f, -0.134580709f, + 0.991709754f, -0.128498111f, + 0.992479535f, -0.122410675f, + 0.993211949f, -0.116318631f, + 0.993906970f, -0.110222207f, + 0.994564571f, -0.104121634f, + 0.995184727f, -0.098017140f, + 0.995767414f, -0.091908956f, + 0.996312612f, -0.085797312f, + 0.996820299f, -0.079682438f, + 0.997290457f, -0.073564564f, + 0.997723067f, -0.067443920f, + 0.998118113f, -0.061320736f, + 0.998475581f, -0.055195244f, + 0.998795456f, -0.049067674f, + 0.999077728f, -0.042938257f, + 0.999322385f, -0.036807223f, + 0.999529418f, -0.030674803f, + 0.999698819f, -0.024541229f, + 0.999830582f, -0.018406730f, + 0.999924702f, -0.012271538f, + 0.999981175f, -0.006135885f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par +
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 2048, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_2048[4096] = { + 1.000000000f, 0.000000000f, + 0.999995294f, 0.003067957f, + 0.999981175f, 0.006135885f, + 0.999957645f, 0.009203755f, + 0.999924702f, 0.012271538f, + 0.999882347f, 0.015339206f, + 0.999830582f, 0.018406730f, + 0.999769405f, 0.021474080f, + 0.999698819f, 0.024541229f, + 0.999618822f, 0.027608146f, + 0.999529418f, 0.030674803f, + 0.999430605f, 0.033741172f, + 0.999322385f, 0.036807223f, + 0.999204759f, 0.039872928f, + 0.999077728f, 0.042938257f, + 0.998941293f, 0.046003182f, + 0.998795456f, 0.049067674f, + 0.998640218f, 0.052131705f, + 0.998475581f, 0.055195244f, + 0.998301545f, 0.058258265f, + 0.998118113f, 0.061320736f, + 0.997925286f, 0.064382631f, + 0.997723067f, 0.067443920f, + 0.997511456f, 0.070504573f, + 0.997290457f, 0.073564564f, + 0.997060070f, 0.076623861f, + 0.996820299f, 0.079682438f, + 0.996571146f, 0.082740265f, + 0.996312612f, 0.085797312f, + 0.996044701f, 0.088853553f, + 0.995767414f, 0.091908956f, + 0.995480755f, 0.094963495f, + 0.995184727f, 0.098017140f, + 0.994879331f, 0.101069863f, + 0.994564571f, 0.104121634f, + 0.994240449f, 0.107172425f, + 0.993906970f, 0.110222207f, + 0.993564136f, 0.113270952f, + 0.993211949f, 0.116318631f, + 0.992850414f, 0.119365215f, + 0.992479535f, 0.122410675f, + 0.992099313f, 0.125454983f, + 0.991709754f, 0.128498111f, + 0.991310860f, 0.131540029f, + 0.990902635f, 0.134580709f, + 0.990485084f, 0.137620122f, + 0.990058210f, 0.140658239f, + 0.989622017f, 0.143695033f, + 0.989176510f, 0.146730474f, + 0.988721692f, 0.149764535f, + 0.988257568f, 0.152797185f, + 0.987784142f, 0.155828398f, + 0.987301418f, 0.158858143f, + 0.986809402f, 0.161886394f, + 0.986308097f, 0.164913120f, + 0.985797509f, 0.167938295f, + 0.985277642f, 0.170961889f, + 0.984748502f, 0.173983873f, + 0.984210092f, 0.177004220f, + 0.983662419f, 0.180022901f, + 0.983105487f, 0.183039888f, + 0.982539302f, 0.186055152f, + 0.981963869f, 0.189068664f, + 0.981379193f, 0.192080397f, + 0.980785280f, 0.195090322f, + 0.980182136f, 0.198098411f, + 0.979569766f, 0.201104635f, + 0.978948175f, 0.204108966f, + 0.978317371f, 0.207111376f, + 0.977677358f, 0.210111837f, + 0.977028143f, 0.213110320f, + 0.976369731f, 0.216106797f, + 0.975702130f, 0.219101240f, + 0.975025345f, 0.222093621f, + 0.974339383f, 0.225083911f, + 0.973644250f, 0.228072083f, + 0.972939952f, 0.231058108f, + 0.972226497f, 0.234041959f, + 0.971503891f, 0.237023606f, + 0.970772141f, 0.240003022f, + 0.970031253f, 0.242980180f, + 0.969281235f, 0.245955050f, + 0.968522094f, 0.248927606f, + 0.967753837f, 0.251897818f, + 0.966976471f, 0.254865660f, + 0.966190003f, 0.257831102f, + 0.965394442f, 0.260794118f, + 0.964589793f, 0.263754679f, + 0.963776066f, 0.266712757f, + 0.962953267f, 0.269668326f, + 0.962121404f, 0.272621355f, + 0.961280486f, 0.275571819f, + 0.960430519f, 0.278519689f, + 0.959571513f, 0.281464938f, + 0.958703475f, 0.284407537f, + 0.957826413f, 0.287347460f, + 0.956940336f, 0.290284677f, + 0.956045251f, 0.293219163f, + 0.955141168f, 0.296150888f, + 0.954228095f, 0.299079826f, + 0.953306040f, 0.302005949f, + 0.952375013f, 0.304929230f, + 0.951435021f, 0.307849640f, + 0.950486074f, 0.310767153f, + 0.949528181f, 0.313681740f, + 0.948561350f, 0.316593376f, + 0.947585591f, 0.319502031f, + 0.946600913f, 0.322407679f, + 0.945607325f, 0.325310292f, + 0.944604837f, 0.328209844f, + 0.943593458f, 0.331106306f, + 0.942573198f, 0.333999651f, + 0.941544065f, 0.336889853f, + 0.940506071f, 0.339776884f, + 0.939459224f, 0.342660717f, + 0.938403534f, 0.345541325f, + 0.937339012f, 0.348418680f, + 0.936265667f, 0.351292756f, + 0.935183510f, 0.354163525f, + 0.934092550f, 0.357030961f, + 0.932992799f, 0.359895037f, + 0.931884266f, 0.362755724f, + 0.930766961f, 0.365612998f, + 0.929640896f, 0.368466830f, + 0.928506080f, 0.371317194f, + 0.927362526f, 0.374164063f, + 0.926210242f, 0.377007410f, + 0.925049241f, 0.379847209f, + 0.923879533f, 0.382683432f, + 0.922701128f, 0.385516054f, + 0.921514039f, 0.388345047f, + 0.920318277f, 0.391170384f, + 0.919113852f, 0.393992040f, + 0.917900776f, 0.396809987f, + 0.916679060f, 0.399624200f, + 0.915448716f, 0.402434651f, + 0.914209756f, 0.405241314f, + 0.912962190f, 0.408044163f, + 0.911706032f, 0.410843171f, + 0.910441292f, 0.413638312f, + 0.909167983f, 0.416429560f, + 0.907886116f, 0.419216888f, + 0.906595705f, 0.422000271f, + 0.905296759f, 0.424779681f, + 0.903989293f, 0.427555093f, + 0.902673318f, 0.430326481f, + 0.901348847f, 0.433093819f, + 0.900015892f, 0.435857080f, + 0.898674466f, 0.438616239f, + 0.897324581f, 0.441371269f, + 0.895966250f, 0.444122145f, + 0.894599486f, 0.446868840f, + 0.893224301f, 0.449611330f, + 0.891840709f, 0.452349587f, + 0.890448723f, 0.455083587f, + 0.889048356f, 0.457813304f, + 0.887639620f, 0.460538711f, + 0.886222530f, 0.463259784f, + 0.884797098f, 0.465976496f, + 0.883363339f, 0.468688822f, + 0.881921264f, 0.471396737f, + 0.880470889f, 0.474100215f, + 0.879012226f, 0.476799230f, + 0.877545290f, 0.479493758f, + 0.876070094f, 0.482183772f, + 0.874586652f, 0.484869248f, + 0.873094978f, 0.487550160f, + 0.871595087f, 0.490226483f, + 0.870086991f, 0.492898192f, + 0.868570706f, 0.495565262f, + 0.867046246f, 0.498227667f, + 0.865513624f, 0.500885383f, + 0.863972856f, 0.503538384f, + 0.862423956f, 0.506186645f, + 0.860866939f, 0.508830143f, + 0.859301818f, 0.511468850f, + 0.857728610f, 0.514102744f, + 0.856147328f, 0.516731799f, + 0.854557988f, 0.519355990f, + 0.852960605f, 0.521975293f, + 0.851355193f, 0.524589683f, + 0.849741768f, 0.527199135f, + 0.848120345f, 0.529803625f, + 0.846490939f, 0.532403128f, + 0.844853565f, 0.534997620f, + 0.843208240f, 0.537587076f, + 0.841554977f, 0.540171473f, + 0.839893794f, 0.542750785f, + 0.838224706f, 0.545324988f, + 0.836547727f, 0.547894059f, + 0.834862875f, 0.550457973f, + 0.833170165f, 0.553016706f, + 0.831469612f, 0.555570233f, + 0.829761234f, 0.558118531f, + 0.828045045f, 0.560661576f, + 0.826321063f, 0.563199344f, + 0.824589303f, 0.565731811f, + 0.822849781f, 0.568258953f, + 0.821102515f, 0.570780746f, + 0.819347520f, 0.573297167f, + 0.817584813f, 0.575808191f, + 0.815814411f, 0.578313796f, + 0.814036330f, 0.580813958f, + 0.812250587f, 0.583308653f, + 0.810457198f, 0.585797857f, + 0.808656182f, 0.588281548f, + 0.806847554f, 0.590759702f, + 0.805031331f, 0.593232295f, + 0.803207531f, 0.595699304f, + 0.801376172f, 0.598160707f, + 0.799537269f, 0.600616479f, + 0.797690841f, 0.603066599f, + 0.795836905f, 0.605511041f, + 0.793975478f, 0.607949785f, + 0.792106577f, 0.610382806f, + 0.790230221f, 0.612810082f, + 0.788346428f, 0.615231591f, + 0.786455214f, 0.617647308f, + 0.784556597f, 0.620057212f, + 0.782650596f, 0.622461279f, + 0.780737229f, 0.624859488f, + 0.778816512f, 0.627251815f, + 0.776888466f, 0.629638239f, + 0.774953107f, 0.632018736f, + 0.773010453f, 0.634393284f, + 0.771060524f, 0.636761861f, + 0.769103338f, 0.639124445f, + 0.767138912f, 0.641481013f, + 0.765167266f, 0.643831543f, + 0.763188417f, 0.646176013f, + 0.761202385f, 0.648514401f, + 0.759209189f, 0.650846685f, + 0.757208847f, 0.653172843f, + 0.755201377f, 0.655492853f, + 0.753186799f, 0.657806693f, + 0.751165132f, 0.660114342f, + 0.749136395f, 0.662415778f, + 0.747100606f, 0.664710978f, + 0.745057785f, 0.666999922f, + 0.743007952f, 0.669282588f, + 0.740951125f, 0.671558955f, + 0.738887324f, 0.673829000f, + 0.736816569f, 0.676092704f, + 0.734738878f, 0.678350043f, + 0.732654272f, 0.680600998f, + 0.730562769f, 0.682845546f, + 0.728464390f, 0.685083668f, + 0.726359155f, 0.687315341f, + 0.724247083f, 0.689540545f, + 0.722128194f, 0.691759258f, + 0.720002508f, 0.693971461f, + 0.717870045f, 0.696177131f, + 0.715730825f, 0.698376249f, + 0.713584869f, 0.700568794f, + 0.711432196f, 0.702754744f, + 0.709272826f, 0.704934080f, + 0.707106781f, 0.707106781f, + 0.704934080f, 0.709272826f, + 0.702754744f, 0.711432196f, + 0.700568794f, 0.713584869f, + 0.698376249f, 0.715730825f, + 0.696177131f, 0.717870045f, + 0.693971461f, 0.720002508f, + 0.691759258f, 0.722128194f, + 0.689540545f, 0.724247083f, + 0.687315341f, 0.726359155f, + 0.685083668f, 0.728464390f, + 0.682845546f, 0.730562769f, + 0.680600998f, 0.732654272f, + 0.678350043f, 0.734738878f, + 0.676092704f, 0.736816569f, + 0.673829000f, 0.738887324f, + 0.671558955f, 0.740951125f, + 0.669282588f, 0.743007952f, + 0.666999922f, 0.745057785f, + 0.664710978f, 0.747100606f, + 0.662415778f, 0.749136395f, + 0.660114342f, 0.751165132f, + 0.657806693f, 0.753186799f, + 0.655492853f, 0.755201377f, + 0.653172843f, 0.757208847f, + 0.650846685f, 0.759209189f, + 0.648514401f, 0.761202385f, + 0.646176013f, 0.763188417f, + 0.643831543f, 0.765167266f, + 0.641481013f, 0.767138912f, + 0.639124445f, 0.769103338f, + 0.636761861f, 0.771060524f, + 0.634393284f, 0.773010453f, + 0.632018736f, 0.774953107f, + 0.629638239f, 0.776888466f, + 0.627251815f, 0.778816512f, + 0.624859488f, 0.780737229f, + 0.622461279f, 0.782650596f, + 0.620057212f, 0.784556597f, + 0.617647308f, 0.786455214f, + 0.615231591f, 0.788346428f, + 0.612810082f, 0.790230221f, + 0.610382806f, 0.792106577f, + 0.607949785f, 0.793975478f, + 0.605511041f, 0.795836905f, + 0.603066599f, 0.797690841f, + 0.600616479f, 0.799537269f, + 0.598160707f, 0.801376172f, + 0.595699304f, 0.803207531f, + 0.593232295f, 0.805031331f, + 0.590759702f, 0.806847554f, + 0.588281548f, 0.808656182f, + 0.585797857f, 0.810457198f, + 0.583308653f, 0.812250587f, + 0.580813958f, 0.814036330f, + 0.578313796f, 0.815814411f, + 0.575808191f, 0.817584813f, + 0.573297167f, 0.819347520f, + 0.570780746f, 0.821102515f, + 0.568258953f, 0.822849781f, + 0.565731811f, 0.824589303f, + 0.563199344f, 0.826321063f, + 0.560661576f, 0.828045045f, + 0.558118531f, 0.829761234f, + 0.555570233f, 0.831469612f, + 0.553016706f, 0.833170165f, + 0.550457973f, 0.834862875f, + 0.547894059f, 0.836547727f, + 0.545324988f, 0.838224706f, + 0.542750785f, 0.839893794f, + 0.540171473f, 0.841554977f, + 0.537587076f, 0.843208240f, + 0.534997620f, 0.844853565f, + 0.532403128f, 0.846490939f, + 0.529803625f, 0.848120345f, + 0.527199135f, 0.849741768f, + 0.524589683f, 0.851355193f, + 0.521975293f, 0.852960605f, + 0.519355990f, 0.854557988f, + 0.516731799f, 0.856147328f, + 0.514102744f, 0.857728610f, + 0.511468850f, 0.859301818f, + 0.508830143f, 0.860866939f, + 0.506186645f, 0.862423956f, + 0.503538384f, 0.863972856f, + 0.500885383f, 0.865513624f, + 0.498227667f, 0.867046246f, + 0.495565262f, 0.868570706f, + 0.492898192f, 0.870086991f, + 0.490226483f, 0.871595087f, + 0.487550160f, 0.873094978f, + 0.484869248f, 0.874586652f, + 0.482183772f, 0.876070094f, + 0.479493758f, 0.877545290f, + 0.476799230f, 0.879012226f, + 0.474100215f, 0.880470889f, + 0.471396737f, 0.881921264f, + 0.468688822f, 0.883363339f, + 0.465976496f, 0.884797098f, + 0.463259784f, 0.886222530f, + 0.460538711f, 0.887639620f, + 0.457813304f, 0.889048356f, + 0.455083587f, 0.890448723f, + 0.452349587f, 0.891840709f, + 0.449611330f, 0.893224301f, + 0.446868840f, 0.894599486f, + 0.444122145f, 0.895966250f, + 0.441371269f, 0.897324581f, + 0.438616239f, 0.898674466f, + 0.435857080f, 0.900015892f, + 0.433093819f, 0.901348847f, + 0.430326481f, 0.902673318f, + 0.427555093f, 0.903989293f, + 0.424779681f, 0.905296759f, + 0.422000271f, 0.906595705f, + 0.419216888f, 0.907886116f, + 0.416429560f, 0.909167983f, + 0.413638312f, 0.910441292f, + 0.410843171f, 0.911706032f, + 0.408044163f, 0.912962190f, + 0.405241314f, 0.914209756f, + 0.402434651f, 0.915448716f, + 0.399624200f, 0.916679060f, + 0.396809987f, 0.917900776f, + 0.393992040f, 0.919113852f, + 0.391170384f, 0.920318277f, + 0.388345047f, 0.921514039f, + 0.385516054f, 0.922701128f, + 0.382683432f, 0.923879533f, + 0.379847209f, 0.925049241f, + 0.377007410f, 0.926210242f, + 0.374164063f, 0.927362526f, + 0.371317194f, 0.928506080f, + 0.368466830f, 0.929640896f, + 0.365612998f, 0.930766961f, + 0.362755724f, 0.931884266f, + 0.359895037f, 0.932992799f, + 0.357030961f, 0.934092550f, + 0.354163525f, 0.935183510f, + 0.351292756f, 0.936265667f, + 0.348418680f, 0.937339012f, + 0.345541325f, 0.938403534f, + 0.342660717f, 0.939459224f, + 0.339776884f, 0.940506071f, + 0.336889853f, 0.941544065f, + 0.333999651f, 0.942573198f, + 0.331106306f, 0.943593458f, + 0.328209844f, 0.944604837f, + 0.325310292f, 0.945607325f, + 0.322407679f, 0.946600913f, + 0.319502031f, 0.947585591f, + 0.316593376f, 0.948561350f, + 0.313681740f, 0.949528181f, + 0.310767153f, 0.950486074f, + 0.307849640f, 0.951435021f, + 0.304929230f, 0.952375013f, + 0.302005949f, 0.953306040f, + 0.299079826f, 0.954228095f, + 0.296150888f, 0.955141168f, + 0.293219163f, 0.956045251f, + 0.290284677f, 0.956940336f, + 0.287347460f, 0.957826413f, + 0.284407537f, 0.958703475f, + 0.281464938f, 0.959571513f, + 0.278519689f, 0.960430519f, + 0.275571819f, 0.961280486f, + 0.272621355f, 0.962121404f, + 0.269668326f, 0.962953267f, + 0.266712757f, 0.963776066f, + 0.263754679f, 0.964589793f, + 0.260794118f, 0.965394442f, + 0.257831102f, 0.966190003f, + 0.254865660f, 0.966976471f, + 0.251897818f, 0.967753837f, + 0.248927606f, 0.968522094f, + 0.245955050f, 0.969281235f, + 0.242980180f, 0.970031253f, + 0.240003022f, 0.970772141f, + 0.237023606f, 0.971503891f, + 0.234041959f, 0.972226497f, + 0.231058108f, 0.972939952f, + 0.228072083f, 0.973644250f, + 0.225083911f, 0.974339383f, + 0.222093621f, 0.975025345f, + 0.219101240f, 0.975702130f, + 0.216106797f, 0.976369731f, + 0.213110320f, 0.977028143f, + 0.210111837f, 0.977677358f, + 0.207111376f, 0.978317371f, + 0.204108966f, 0.978948175f, + 0.201104635f, 0.979569766f, + 0.198098411f, 0.980182136f, + 0.195090322f, 0.980785280f, + 0.192080397f, 0.981379193f, + 0.189068664f, 0.981963869f, + 0.186055152f, 0.982539302f, + 0.183039888f, 0.983105487f, + 0.180022901f, 0.983662419f, + 0.177004220f, 0.984210092f, + 0.173983873f, 0.984748502f, + 0.170961889f, 0.985277642f, + 0.167938295f, 0.985797509f, + 0.164913120f, 0.986308097f, + 0.161886394f, 0.986809402f, + 0.158858143f, 0.987301418f, + 0.155828398f, 0.987784142f, + 0.152797185f, 0.988257568f, + 0.149764535f, 0.988721692f, + 0.146730474f, 0.989176510f, + 0.143695033f, 0.989622017f, + 0.140658239f, 0.990058210f, + 0.137620122f, 0.990485084f, + 0.134580709f, 0.990902635f, + 0.131540029f, 0.991310860f, + 0.128498111f, 0.991709754f, + 0.125454983f, 0.992099313f, + 0.122410675f, 0.992479535f, + 0.119365215f, 0.992850414f, + 0.116318631f, 0.993211949f, + 0.113270952f, 0.993564136f, + 0.110222207f, 0.993906970f, + 0.107172425f, 0.994240449f, + 0.104121634f, 0.994564571f, + 0.101069863f, 0.994879331f, + 0.098017140f, 0.995184727f, + 0.094963495f, 0.995480755f, + 0.091908956f, 0.995767414f, + 0.088853553f, 0.996044701f, + 0.085797312f, 0.996312612f, + 0.082740265f, 0.996571146f, + 0.079682438f, 0.996820299f, + 0.076623861f, 0.997060070f, + 0.073564564f, 0.997290457f, + 0.070504573f, 0.997511456f, + 0.067443920f, 0.997723067f, + 0.064382631f, 0.997925286f, + 0.061320736f, 0.998118113f, + 0.058258265f, 0.998301545f, + 0.055195244f, 0.998475581f, + 0.052131705f, 0.998640218f, + 0.049067674f, 0.998795456f, + 0.046003182f, 0.998941293f, + 0.042938257f, 0.999077728f, + 0.039872928f, 0.999204759f, + 0.036807223f, 0.999322385f, + 0.033741172f, 0.999430605f, + 0.030674803f, 0.999529418f, + 0.027608146f, 0.999618822f, + 0.024541229f, 0.999698819f, + 0.021474080f, 0.999769405f, + 0.018406730f, 0.999830582f, + 0.015339206f, 0.999882347f, + 0.012271538f, 0.999924702f, + 0.009203755f, 0.999957645f, + 0.006135885f, 0.999981175f, + 0.003067957f, 0.999995294f, + 0.000000000f, 1.000000000f, + -0.003067957f, 0.999995294f, + -0.006135885f, 0.999981175f, + -0.009203755f, 0.999957645f, + -0.012271538f, 0.999924702f, + -0.015339206f, 0.999882347f, + -0.018406730f, 0.999830582f, + -0.021474080f, 0.999769405f, + -0.024541229f, 0.999698819f, + -0.027608146f, 0.999618822f, + -0.030674803f, 0.999529418f, + -0.033741172f, 0.999430605f, + -0.036807223f, 0.999322385f, + -0.039872928f, 0.999204759f, + -0.042938257f, 0.999077728f, + -0.046003182f, 0.998941293f, + -0.049067674f, 0.998795456f, + -0.052131705f, 0.998640218f, + -0.055195244f, 0.998475581f, + -0.058258265f, 0.998301545f, + -0.061320736f, 0.998118113f, + -0.064382631f, 0.997925286f, + -0.067443920f, 0.997723067f, + -0.070504573f, 0.997511456f, + -0.073564564f, 0.997290457f, + -0.076623861f, 0.997060070f, + -0.079682438f, 0.996820299f, + -0.082740265f, 0.996571146f, + -0.085797312f, 0.996312612f, + -0.088853553f, 0.996044701f, + -0.091908956f, 0.995767414f, + -0.094963495f, 0.995480755f, + -0.098017140f, 0.995184727f, + -0.101069863f, 0.994879331f, + -0.104121634f, 0.994564571f, + -0.107172425f, 0.994240449f, + -0.110222207f, 0.993906970f, + -0.113270952f, 0.993564136f, + -0.116318631f, 0.993211949f, + -0.119365215f, 0.992850414f, + -0.122410675f, 0.992479535f, + -0.125454983f, 0.992099313f, + -0.128498111f, 0.991709754f, + -0.131540029f, 0.991310860f, + -0.134580709f, 0.990902635f, + -0.137620122f, 0.990485084f, + -0.140658239f, 0.990058210f, + -0.143695033f, 0.989622017f, + -0.146730474f, 0.989176510f, + -0.149764535f, 0.988721692f, + -0.152797185f, 0.988257568f, + -0.155828398f, 0.987784142f, + -0.158858143f, 0.987301418f, + -0.161886394f, 0.986809402f, + -0.164913120f, 0.986308097f, + -0.167938295f, 0.985797509f, + -0.170961889f, 0.985277642f, + -0.173983873f, 0.984748502f, + -0.177004220f, 0.984210092f, + -0.180022901f, 0.983662419f, + -0.183039888f, 0.983105487f, + -0.186055152f, 0.982539302f, + -0.189068664f, 0.981963869f, + -0.192080397f, 0.981379193f, + -0.195090322f, 0.980785280f, + -0.198098411f, 0.980182136f, + -0.201104635f, 0.979569766f, + -0.204108966f, 0.978948175f, + -0.207111376f, 0.978317371f, + -0.210111837f, 0.977677358f, + -0.213110320f, 0.977028143f, + -0.216106797f, 0.976369731f, + -0.219101240f, 0.975702130f, + -0.222093621f, 0.975025345f, + -0.225083911f, 0.974339383f, + -0.228072083f, 0.973644250f, + -0.231058108f, 0.972939952f, + -0.234041959f, 0.972226497f, + -0.237023606f, 0.971503891f, + -0.240003022f, 0.970772141f, + -0.242980180f, 0.970031253f, + -0.245955050f, 0.969281235f, + -0.248927606f, 0.968522094f, + -0.251897818f, 0.967753837f, + -0.254865660f, 0.966976471f, + -0.257831102f, 0.966190003f, + -0.260794118f, 0.965394442f, + -0.263754679f, 0.964589793f, + -0.266712757f, 0.963776066f, + -0.269668326f, 0.962953267f, + -0.272621355f, 0.962121404f, + -0.275571819f, 0.961280486f, + -0.278519689f, 0.960430519f, + -0.281464938f, 0.959571513f, + -0.284407537f, 0.958703475f, + -0.287347460f, 0.957826413f, + -0.290284677f, 0.956940336f, + -0.293219163f, 0.956045251f, + -0.296150888f, 0.955141168f, + -0.299079826f, 0.954228095f, + -0.302005949f, 0.953306040f, + -0.304929230f, 0.952375013f, + -0.307849640f, 0.951435021f, + -0.310767153f, 0.950486074f, + -0.313681740f, 0.949528181f, + -0.316593376f, 0.948561350f, + -0.319502031f, 0.947585591f, + -0.322407679f, 0.946600913f, + -0.325310292f, 0.945607325f, + -0.328209844f, 0.944604837f, + -0.331106306f, 0.943593458f, + -0.333999651f, 0.942573198f, + -0.336889853f, 0.941544065f, + -0.339776884f, 0.940506071f, + -0.342660717f, 0.939459224f, + -0.345541325f, 0.938403534f, + -0.348418680f, 0.937339012f, + -0.351292756f, 0.936265667f, + -0.354163525f, 0.935183510f, + -0.357030961f, 0.934092550f, + -0.359895037f, 0.932992799f, + -0.362755724f, 0.931884266f, + -0.365612998f, 0.930766961f, + -0.368466830f, 0.929640896f, + -0.371317194f, 0.928506080f, + -0.374164063f, 0.927362526f, + -0.377007410f, 0.926210242f, + -0.379847209f, 0.925049241f, + -0.382683432f, 0.923879533f, + -0.385516054f, 0.922701128f, + -0.388345047f, 0.921514039f, + -0.391170384f, 0.920318277f, + -0.393992040f, 0.919113852f, + -0.396809987f, 0.917900776f, + -0.399624200f, 0.916679060f, + -0.402434651f, 0.915448716f, + -0.405241314f, 0.914209756f, + -0.408044163f, 0.912962190f, + -0.410843171f, 0.911706032f, + -0.413638312f, 0.910441292f, + -0.416429560f, 0.909167983f, + -0.419216888f, 0.907886116f, + -0.422000271f, 0.906595705f, + -0.424779681f, 0.905296759f, + -0.427555093f, 0.903989293f, + -0.430326481f, 0.902673318f, + -0.433093819f, 0.901348847f, + -0.435857080f, 0.900015892f, + -0.438616239f, 0.898674466f, + -0.441371269f, 0.897324581f, + -0.444122145f, 0.895966250f, + -0.446868840f, 0.894599486f, + -0.449611330f, 0.893224301f, + -0.452349587f, 0.891840709f, + -0.455083587f, 0.890448723f, + -0.457813304f, 0.889048356f, + -0.460538711f, 0.887639620f, + -0.463259784f, 0.886222530f, + -0.465976496f, 0.884797098f, + -0.468688822f, 0.883363339f, + -0.471396737f, 0.881921264f, + -0.474100215f, 0.880470889f, + -0.476799230f, 0.879012226f, + -0.479493758f, 0.877545290f, + -0.482183772f, 0.876070094f, + -0.484869248f, 0.874586652f, + -0.487550160f, 0.873094978f, + -0.490226483f, 0.871595087f, + -0.492898192f, 0.870086991f, + -0.495565262f, 0.868570706f, + -0.498227667f, 0.867046246f, + -0.500885383f, 0.865513624f, + -0.503538384f, 0.863972856f, + -0.506186645f, 0.862423956f, + -0.508830143f, 0.860866939f, + -0.511468850f, 0.859301818f, + -0.514102744f, 0.857728610f, + -0.516731799f, 0.856147328f, + -0.519355990f, 0.854557988f, + -0.521975293f, 0.852960605f, + -0.524589683f, 0.851355193f, + -0.527199135f, 0.849741768f, + -0.529803625f, 0.848120345f, + -0.532403128f, 0.846490939f, + -0.534997620f, 0.844853565f, + -0.537587076f, 0.843208240f, + -0.540171473f, 0.841554977f, + -0.542750785f, 0.839893794f, + -0.545324988f, 0.838224706f, + -0.547894059f, 0.836547727f, + -0.550457973f, 0.834862875f, + -0.553016706f, 0.833170165f, + -0.555570233f, 0.831469612f, + -0.558118531f, 0.829761234f, + -0.560661576f, 0.828045045f, + -0.563199344f, 0.826321063f, + -0.565731811f, 0.824589303f, + -0.568258953f, 0.822849781f, + -0.570780746f, 0.821102515f, + -0.573297167f, 0.819347520f, + -0.575808191f, 0.817584813f, + -0.578313796f, 0.815814411f, + -0.580813958f, 0.814036330f, + -0.583308653f, 0.812250587f, + -0.585797857f, 0.810457198f, + -0.588281548f, 0.808656182f, + -0.590759702f, 0.806847554f, + -0.593232295f, 0.805031331f, + -0.595699304f, 0.803207531f, + -0.598160707f, 0.801376172f, + -0.600616479f, 0.799537269f, + -0.603066599f, 0.797690841f, + -0.605511041f, 0.795836905f, + -0.607949785f, 0.793975478f, + -0.610382806f, 0.792106577f, + -0.612810082f, 0.790230221f, + -0.615231591f, 0.788346428f, + -0.617647308f, 0.786455214f, + -0.620057212f, 0.784556597f, + -0.622461279f, 0.782650596f, + -0.624859488f, 0.780737229f, + -0.627251815f, 0.778816512f, + -0.629638239f, 0.776888466f, + -0.632018736f, 0.774953107f, + -0.634393284f, 0.773010453f, + -0.636761861f, 0.771060524f, + -0.639124445f, 0.769103338f, + -0.641481013f, 0.767138912f, + -0.643831543f, 0.765167266f, + -0.646176013f, 0.763188417f, + -0.648514401f, 0.761202385f, + -0.650846685f, 0.759209189f, + -0.653172843f, 0.757208847f, + -0.655492853f, 0.755201377f, + -0.657806693f, 0.753186799f, + -0.660114342f, 0.751165132f, + -0.662415778f, 0.749136395f, + -0.664710978f, 0.747100606f, + -0.666999922f, 0.745057785f, + -0.669282588f, 0.743007952f, + -0.671558955f, 0.740951125f, + -0.673829000f, 0.738887324f, + -0.676092704f, 0.736816569f, + -0.678350043f, 0.734738878f, + -0.680600998f, 0.732654272f, + -0.682845546f, 0.730562769f, + -0.685083668f, 0.728464390f, + -0.687315341f, 0.726359155f, + -0.689540545f, 0.724247083f, + -0.691759258f, 0.722128194f, + -0.693971461f, 0.720002508f, + -0.696177131f, 0.717870045f, + -0.698376249f, 0.715730825f, + -0.700568794f, 0.713584869f, + -0.702754744f, 0.711432196f, + -0.704934080f, 0.709272826f, + -0.707106781f, 0.707106781f, + -0.709272826f, 0.704934080f, + -0.711432196f, 0.702754744f, + -0.713584869f, 0.700568794f, + -0.715730825f, 0.698376249f, + -0.717870045f, 0.696177131f, + -0.720002508f, 0.693971461f, + -0.722128194f, 0.691759258f, + -0.724247083f, 0.689540545f, + -0.726359155f, 0.687315341f, + -0.728464390f, 0.685083668f, + -0.730562769f, 0.682845546f, + -0.732654272f, 0.680600998f, + -0.734738878f, 0.678350043f, + -0.736816569f, 0.676092704f, + -0.738887324f, 0.673829000f, + -0.740951125f, 0.671558955f, + -0.743007952f, 0.669282588f, + -0.745057785f, 0.666999922f, + -0.747100606f, 0.664710978f, + -0.749136395f, 0.662415778f, + -0.751165132f, 0.660114342f, + -0.753186799f, 0.657806693f, + -0.755201377f, 0.655492853f, + -0.757208847f, 0.653172843f, + -0.759209189f, 0.650846685f, + -0.761202385f, 0.648514401f, + -0.763188417f, 0.646176013f, + -0.765167266f, 0.643831543f, + -0.767138912f, 0.641481013f, + -0.769103338f, 0.639124445f, + -0.771060524f, 0.636761861f, + -0.773010453f, 0.634393284f, + -0.774953107f, 0.632018736f, + -0.776888466f, 0.629638239f, + -0.778816512f, 0.627251815f, + -0.780737229f, 0.624859488f, + -0.782650596f, 0.622461279f, + -0.784556597f, 0.620057212f, + -0.786455214f, 0.617647308f, + -0.788346428f, 0.615231591f, + -0.790230221f, 0.612810082f, + -0.792106577f, 0.610382806f, + -0.793975478f, 0.607949785f, + -0.795836905f, 0.605511041f, + -0.797690841f, 0.603066599f, + -0.799537269f, 0.600616479f, + -0.801376172f, 0.598160707f, + -0.803207531f, 0.595699304f, + -0.805031331f, 0.593232295f, + -0.806847554f, 0.590759702f, + -0.808656182f, 0.588281548f, + -0.810457198f, 0.585797857f, + -0.812250587f, 0.583308653f, + -0.814036330f, 0.580813958f, + -0.815814411f, 0.578313796f, + -0.817584813f, 0.575808191f, + -0.819347520f, 0.573297167f, + -0.821102515f, 0.570780746f, + -0.822849781f, 0.568258953f, + -0.824589303f, 0.565731811f, + -0.826321063f, 0.563199344f, + -0.828045045f, 0.560661576f, + -0.829761234f, 0.558118531f, + -0.831469612f, 0.555570233f, + -0.833170165f, 0.553016706f, + -0.834862875f, 0.550457973f, + -0.836547727f, 0.547894059f, + -0.838224706f, 0.545324988f, + -0.839893794f, 0.542750785f, + -0.841554977f, 0.540171473f, + -0.843208240f, 0.537587076f, + -0.844853565f, 0.534997620f, + -0.846490939f, 0.532403128f, + -0.848120345f, 0.529803625f, + -0.849741768f, 0.527199135f, + -0.851355193f, 0.524589683f, + -0.852960605f, 0.521975293f, + -0.854557988f, 0.519355990f, + -0.856147328f, 0.516731799f, + -0.857728610f, 0.514102744f, + -0.859301818f, 0.511468850f, + -0.860866939f, 0.508830143f, + -0.862423956f, 0.506186645f, + -0.863972856f, 0.503538384f, + -0.865513624f, 0.500885383f, + -0.867046246f, 0.498227667f, + -0.868570706f, 0.495565262f, + -0.870086991f, 0.492898192f, + -0.871595087f, 0.490226483f, + -0.873094978f, 0.487550160f, + -0.874586652f, 0.484869248f, + -0.876070094f, 0.482183772f, + -0.877545290f, 0.479493758f, + -0.879012226f, 0.476799230f, + -0.880470889f, 0.474100215f, + -0.881921264f, 0.471396737f, + -0.883363339f, 0.468688822f, + -0.884797098f, 0.465976496f, + -0.886222530f, 0.463259784f, + -0.887639620f, 0.460538711f, + -0.889048356f, 0.457813304f, + -0.890448723f, 0.455083587f, + -0.891840709f, 0.452349587f, + -0.893224301f, 0.449611330f, + -0.894599486f, 0.446868840f, + -0.895966250f, 0.444122145f, + -0.897324581f, 0.441371269f, + -0.898674466f, 0.438616239f, + -0.900015892f, 0.435857080f, + -0.901348847f, 0.433093819f, + -0.902673318f, 0.430326481f, + -0.903989293f, 0.427555093f, + -0.905296759f, 0.424779681f, + -0.906595705f, 0.422000271f, + -0.907886116f, 0.419216888f, + -0.909167983f, 0.416429560f, + -0.910441292f, 0.413638312f, + -0.911706032f, 0.410843171f, + -0.912962190f, 0.408044163f, + -0.914209756f, 0.405241314f, + -0.915448716f, 0.402434651f, + -0.916679060f, 0.399624200f, + -0.917900776f, 0.396809987f, + -0.919113852f, 0.393992040f, + -0.920318277f, 0.391170384f, + -0.921514039f, 0.388345047f, + -0.922701128f, 0.385516054f, + -0.923879533f, 0.382683432f, + -0.925049241f, 0.379847209f, + -0.926210242f, 0.377007410f, + -0.927362526f, 0.374164063f, + -0.928506080f, 0.371317194f, + -0.929640896f, 0.368466830f, + -0.930766961f, 0.365612998f, + -0.931884266f, 0.362755724f, + -0.932992799f, 0.359895037f, + -0.934092550f, 0.357030961f, + -0.935183510f, 0.354163525f, + -0.936265667f, 0.351292756f, + -0.937339012f, 0.348418680f, + -0.938403534f, 0.345541325f, + -0.939459224f, 0.342660717f, + -0.940506071f, 0.339776884f, + -0.941544065f, 0.336889853f, + -0.942573198f, 0.333999651f, + -0.943593458f, 0.331106306f, + -0.944604837f, 0.328209844f, + -0.945607325f, 0.325310292f, + -0.946600913f, 0.322407679f, + -0.947585591f, 0.319502031f, + -0.948561350f, 0.316593376f, + -0.949528181f, 0.313681740f, + -0.950486074f, 0.310767153f, + -0.951435021f, 0.307849640f, + -0.952375013f, 0.304929230f, + -0.953306040f, 0.302005949f, + -0.954228095f, 0.299079826f, + -0.955141168f, 0.296150888f, + -0.956045251f, 0.293219163f, + -0.956940336f, 0.290284677f, + -0.957826413f, 0.287347460f, + -0.958703475f, 0.284407537f, + -0.959571513f, 0.281464938f, + -0.960430519f, 0.278519689f, + -0.961280486f, 0.275571819f, + -0.962121404f, 0.272621355f, + -0.962953267f, 0.269668326f, + -0.963776066f, 0.266712757f, + -0.964589793f, 0.263754679f, + -0.965394442f, 0.260794118f, + -0.966190003f, 0.257831102f, + -0.966976471f, 0.254865660f, + -0.967753837f, 0.251897818f, + -0.968522094f, 0.248927606f, + -0.969281235f, 0.245955050f, + -0.970031253f, 0.242980180f, + -0.970772141f, 0.240003022f, + -0.971503891f, 0.237023606f, + -0.972226497f, 0.234041959f, + -0.972939952f, 0.231058108f, + -0.973644250f, 0.228072083f, + -0.974339383f, 0.225083911f, + -0.975025345f, 0.222093621f, + -0.975702130f, 0.219101240f, + -0.976369731f, 0.216106797f, + -0.977028143f, 0.213110320f, + -0.977677358f, 0.210111837f, + -0.978317371f, 0.207111376f, + -0.978948175f, 0.204108966f, + -0.979569766f, 0.201104635f, + -0.980182136f, 0.198098411f, + -0.980785280f, 0.195090322f, + -0.981379193f, 0.192080397f, + -0.981963869f, 0.189068664f, + -0.982539302f, 0.186055152f, + -0.983105487f, 0.183039888f, + -0.983662419f, 0.180022901f, + -0.984210092f, 0.177004220f, + -0.984748502f, 0.173983873f, + -0.985277642f, 0.170961889f, + -0.985797509f, 0.167938295f, + -0.986308097f, 0.164913120f, + -0.986809402f, 0.161886394f, + -0.987301418f, 0.158858143f, + -0.987784142f, 0.155828398f, + -0.988257568f, 0.152797185f, + -0.988721692f, 0.149764535f, + -0.989176510f, 0.146730474f, + -0.989622017f, 0.143695033f, + -0.990058210f, 0.140658239f, + -0.990485084f, 0.137620122f, + -0.990902635f, 0.134580709f, + -0.991310860f, 0.131540029f, + -0.991709754f, 0.128498111f, + -0.992099313f, 0.125454983f, + -0.992479535f, 0.122410675f, + -0.992850414f, 0.119365215f, + -0.993211949f, 0.116318631f, + -0.993564136f, 0.113270952f, + -0.993906970f, 0.110222207f, + -0.994240449f, 0.107172425f, + -0.994564571f, 0.104121634f, + -0.994879331f, 0.101069863f, + -0.995184727f, 0.098017140f, + -0.995480755f, 0.094963495f, + -0.995767414f, 0.091908956f, + -0.996044701f, 0.088853553f, + -0.996312612f, 0.085797312f, + -0.996571146f, 0.082740265f, + -0.996820299f, 0.079682438f, + -0.997060070f, 0.076623861f, + -0.997290457f, 0.073564564f, + -0.997511456f, 0.070504573f, + -0.997723067f, 0.067443920f, + -0.997925286f, 0.064382631f, + -0.998118113f, 0.061320736f, + -0.998301545f, 0.058258265f, + -0.998475581f, 0.055195244f, + -0.998640218f, 0.052131705f, + -0.998795456f, 0.049067674f, + -0.998941293f, 0.046003182f, + -0.999077728f, 0.042938257f, + -0.999204759f, 0.039872928f, + -0.999322385f, 0.036807223f, + -0.999430605f, 0.033741172f, + -0.999529418f, 0.030674803f, + -0.999618822f, 0.027608146f, + -0.999698819f, 0.024541229f, + -0.999769405f, 0.021474080f, + -0.999830582f, 0.018406730f, + -0.999882347f, 0.015339206f, + -0.999924702f, 0.012271538f, + -0.999957645f, 0.009203755f, + -0.999981175f, 0.006135885f, + -0.999995294f, 0.003067957f, + -1.000000000f, 0.000000000f, + -0.999995294f, -0.003067957f, + -0.999981175f, -0.006135885f, + -0.999957645f, -0.009203755f, + -0.999924702f, -0.012271538f, + -0.999882347f, -0.015339206f, + -0.999830582f, -0.018406730f, + -0.999769405f, -0.021474080f, + -0.999698819f, -0.024541229f, + -0.999618822f, -0.027608146f, + -0.999529418f, -0.030674803f, + -0.999430605f, -0.033741172f, + -0.999322385f, -0.036807223f, + -0.999204759f, -0.039872928f, + -0.999077728f, -0.042938257f, + -0.998941293f, -0.046003182f, + -0.998795456f, -0.049067674f, + -0.998640218f, -0.052131705f, + -0.998475581f, -0.055195244f, + -0.998301545f, -0.058258265f, + -0.998118113f, -0.061320736f, + -0.997925286f, -0.064382631f, + -0.997723067f, -0.067443920f, + -0.997511456f, -0.070504573f, + -0.997290457f, -0.073564564f, + -0.997060070f, -0.076623861f, + -0.996820299f, -0.079682438f, + -0.996571146f, -0.082740265f, + -0.996312612f, -0.085797312f, + -0.996044701f, -0.088853553f, + -0.995767414f, -0.091908956f, + -0.995480755f, -0.094963495f, + -0.995184727f, -0.098017140f, + -0.994879331f, -0.101069863f, + -0.994564571f, -0.104121634f, + -0.994240449f, -0.107172425f, + -0.993906970f, -0.110222207f, + -0.993564136f, -0.113270952f, + -0.993211949f, -0.116318631f, + -0.992850414f, -0.119365215f, + -0.992479535f, -0.122410675f, + -0.992099313f, -0.125454983f, + -0.991709754f, -0.128498111f, + -0.991310860f, -0.131540029f, + -0.990902635f, -0.134580709f, + -0.990485084f, -0.137620122f, + -0.990058210f, -0.140658239f, + -0.989622017f, -0.143695033f, + -0.989176510f, -0.146730474f, + -0.988721692f, -0.149764535f, + -0.988257568f, -0.152797185f, + -0.987784142f, -0.155828398f, + -0.987301418f, -0.158858143f, + -0.986809402f, -0.161886394f, + -0.986308097f, -0.164913120f, + -0.985797509f, -0.167938295f, + -0.985277642f, -0.170961889f, + -0.984748502f, -0.173983873f, + -0.984210092f, -0.177004220f, + -0.983662419f, -0.180022901f, + -0.983105487f, -0.183039888f, + -0.982539302f, -0.186055152f, + -0.981963869f, -0.189068664f, + -0.981379193f, -0.192080397f, + -0.980785280f, -0.195090322f, + -0.980182136f, -0.198098411f, + -0.979569766f, -0.201104635f, + -0.978948175f, -0.204108966f, + -0.978317371f, -0.207111376f, + -0.977677358f, -0.210111837f, + -0.977028143f, -0.213110320f, + -0.976369731f, -0.216106797f, + -0.975702130f, -0.219101240f, + -0.975025345f, -0.222093621f, + -0.974339383f, -0.225083911f, + -0.973644250f, -0.228072083f, + -0.972939952f, -0.231058108f, + -0.972226497f, -0.234041959f, + -0.971503891f, -0.237023606f, + -0.970772141f, -0.240003022f, + -0.970031253f, -0.242980180f, + -0.969281235f, -0.245955050f, + -0.968522094f, -0.248927606f, + -0.967753837f, -0.251897818f, + -0.966976471f, -0.254865660f, + -0.966190003f, -0.257831102f, + -0.965394442f, -0.260794118f, + -0.964589793f, -0.263754679f, + -0.963776066f, -0.266712757f, + -0.962953267f, -0.269668326f, + -0.962121404f, -0.272621355f, + -0.961280486f, -0.275571819f, + -0.960430519f, -0.278519689f, + -0.959571513f, -0.281464938f, + -0.958703475f, -0.284407537f, + -0.957826413f, -0.287347460f, + -0.956940336f, -0.290284677f, + -0.956045251f, -0.293219163f, + -0.955141168f, -0.296150888f, + -0.954228095f, -0.299079826f, + -0.953306040f, -0.302005949f, + -0.952375013f, -0.304929230f, + -0.951435021f, -0.307849640f, + -0.950486074f, -0.310767153f, + -0.949528181f, -0.313681740f, + -0.948561350f, -0.316593376f, + -0.947585591f, -0.319502031f, + -0.946600913f, -0.322407679f, + -0.945607325f, -0.325310292f, + -0.944604837f, -0.328209844f, + -0.943593458f, -0.331106306f, + -0.942573198f, -0.333999651f, + -0.941544065f, -0.336889853f, + -0.940506071f, -0.339776884f, + -0.939459224f, -0.342660717f, + -0.938403534f, -0.345541325f, + -0.937339012f, -0.348418680f, + -0.936265667f, -0.351292756f, + -0.935183510f, -0.354163525f, + -0.934092550f, -0.357030961f, + -0.932992799f, -0.359895037f, + -0.931884266f, -0.362755724f, + -0.930766961f, -0.365612998f, + -0.929640896f, -0.368466830f, + -0.928506080f, -0.371317194f, + -0.927362526f, -0.374164063f, + -0.926210242f, -0.377007410f, + -0.925049241f, -0.379847209f, + -0.923879533f, -0.382683432f, + -0.922701128f, -0.385516054f, + -0.921514039f, -0.388345047f, + -0.920318277f, -0.391170384f, + -0.919113852f, -0.393992040f, + -0.917900776f, -0.396809987f, + -0.916679060f, -0.399624200f, + -0.915448716f, -0.402434651f, + -0.914209756f, -0.405241314f, + -0.912962190f, -0.408044163f, + -0.911706032f, -0.410843171f, + -0.910441292f, -0.413638312f, + -0.909167983f, -0.416429560f, + -0.907886116f, -0.419216888f, + -0.906595705f, -0.422000271f, + -0.905296759f, -0.424779681f, + -0.903989293f, -0.427555093f, + -0.902673318f, -0.430326481f, + -0.901348847f, -0.433093819f, + -0.900015892f, -0.435857080f, + -0.898674466f, -0.438616239f, + -0.897324581f, -0.441371269f, + -0.895966250f, -0.444122145f, + -0.894599486f, -0.446868840f, + -0.893224301f, -0.449611330f, + -0.891840709f, -0.452349587f, + -0.890448723f, -0.455083587f, + -0.889048356f, -0.457813304f, + -0.887639620f, -0.460538711f, + -0.886222530f, -0.463259784f, + -0.884797098f, -0.465976496f, + -0.883363339f, -0.468688822f, + -0.881921264f, -0.471396737f, + -0.880470889f, -0.474100215f, + -0.879012226f, -0.476799230f, + -0.877545290f, -0.479493758f, + -0.876070094f, -0.482183772f, + -0.874586652f, -0.484869248f, + -0.873094978f, -0.487550160f, + -0.871595087f, -0.490226483f, + -0.870086991f, -0.492898192f, + -0.868570706f, -0.495565262f, + -0.867046246f, -0.498227667f, + -0.865513624f, -0.500885383f, + -0.863972856f, -0.503538384f, + -0.862423956f, -0.506186645f, + -0.860866939f, -0.508830143f, + -0.859301818f, -0.511468850f, + -0.857728610f, -0.514102744f, + -0.856147328f, -0.516731799f, + -0.854557988f, -0.519355990f, + -0.852960605f, -0.521975293f, + -0.851355193f, -0.524589683f, + -0.849741768f, -0.527199135f, + -0.848120345f, -0.529803625f, + -0.846490939f, -0.532403128f, + -0.844853565f, -0.534997620f, + -0.843208240f, -0.537587076f, + -0.841554977f, -0.540171473f, + -0.839893794f, -0.542750785f, + -0.838224706f, -0.545324988f, + -0.836547727f, -0.547894059f, + -0.834862875f, -0.550457973f, + -0.833170165f, -0.553016706f, + -0.831469612f, -0.555570233f, + -0.829761234f, -0.558118531f, + -0.828045045f, -0.560661576f, + -0.826321063f, -0.563199344f, + -0.824589303f, -0.565731811f, + -0.822849781f, -0.568258953f, + -0.821102515f, -0.570780746f, + -0.819347520f, -0.573297167f, + -0.817584813f, -0.575808191f, + -0.815814411f, -0.578313796f, + -0.814036330f, -0.580813958f, + -0.812250587f, -0.583308653f, + -0.810457198f, -0.585797857f, + -0.808656182f, -0.588281548f, + -0.806847554f, -0.590759702f, + -0.805031331f, -0.593232295f, + -0.803207531f, -0.595699304f, + -0.801376172f, -0.598160707f, + -0.799537269f, -0.600616479f, + -0.797690841f, -0.603066599f, + -0.795836905f, -0.605511041f, + -0.793975478f, -0.607949785f, + -0.792106577f, -0.610382806f, + -0.790230221f, -0.612810082f, + -0.788346428f, -0.615231591f, + -0.786455214f, -0.617647308f, + -0.784556597f, -0.620057212f, + -0.782650596f, -0.622461279f, + -0.780737229f, -0.624859488f, + -0.778816512f, -0.627251815f, + -0.776888466f, -0.629638239f, + -0.774953107f, -0.632018736f, + -0.773010453f, -0.634393284f, + -0.771060524f, -0.636761861f, + -0.769103338f, -0.639124445f, + -0.767138912f, -0.641481013f, + -0.765167266f, -0.643831543f, + -0.763188417f, -0.646176013f, + -0.761202385f, -0.648514401f, + -0.759209189f, -0.650846685f, + -0.757208847f, -0.653172843f, + -0.755201377f, -0.655492853f, + -0.753186799f, -0.657806693f, + -0.751165132f, -0.660114342f, + -0.749136395f, -0.662415778f, + -0.747100606f, -0.664710978f, + -0.745057785f, -0.666999922f, + -0.743007952f, -0.669282588f, + -0.740951125f, -0.671558955f, + -0.738887324f, -0.673829000f, + -0.736816569f, -0.676092704f, + -0.734738878f, -0.678350043f, + -0.732654272f, -0.680600998f, + -0.730562769f, -0.682845546f, + -0.728464390f, -0.685083668f, + -0.726359155f, -0.687315341f, + -0.724247083f, -0.689540545f, + -0.722128194f, -0.691759258f, + -0.720002508f, -0.693971461f, + -0.717870045f, -0.696177131f, + -0.715730825f, -0.698376249f, + -0.713584869f, -0.700568794f, + -0.711432196f, -0.702754744f, + -0.709272826f, -0.704934080f, + -0.707106781f, -0.707106781f, + -0.704934080f, -0.709272826f, + -0.702754744f, -0.711432196f, + -0.700568794f, -0.713584869f, + -0.698376249f, -0.715730825f, + -0.696177131f, -0.717870045f, + -0.693971461f, -0.720002508f, + -0.691759258f, -0.722128194f, + -0.689540545f, -0.724247083f, + -0.687315341f, -0.726359155f, + -0.685083668f, -0.728464390f, + -0.682845546f, -0.730562769f, + -0.680600998f, -0.732654272f, + -0.678350043f, -0.734738878f, + -0.676092704f, -0.736816569f, + -0.673829000f, -0.738887324f, + -0.671558955f, -0.740951125f, + -0.669282588f, -0.743007952f, + -0.666999922f, -0.745057785f, + -0.664710978f, -0.747100606f, + -0.662415778f, -0.749136395f, + -0.660114342f, -0.751165132f, + -0.657806693f, -0.753186799f, + -0.655492853f, -0.755201377f, + -0.653172843f, -0.757208847f, + -0.650846685f, -0.759209189f, + -0.648514401f, -0.761202385f, + -0.646176013f, -0.763188417f, + -0.643831543f, -0.765167266f, + -0.641481013f, -0.767138912f, + -0.639124445f, -0.769103338f, + -0.636761861f, -0.771060524f, + -0.634393284f, -0.773010453f, + -0.632018736f, -0.774953107f, + -0.629638239f, -0.776888466f, + -0.627251815f, -0.778816512f, + -0.624859488f, -0.780737229f, + -0.622461279f, -0.782650596f, + -0.620057212f, -0.784556597f, + -0.617647308f, -0.786455214f, + -0.615231591f, -0.788346428f, + -0.612810082f, -0.790230221f, + -0.610382806f, -0.792106577f, + -0.607949785f, -0.793975478f, + -0.605511041f, -0.795836905f, + -0.603066599f, -0.797690841f, + -0.600616479f, -0.799537269f, + -0.598160707f, -0.801376172f, + -0.595699304f, -0.803207531f, + -0.593232295f, -0.805031331f, + -0.590759702f, -0.806847554f, + -0.588281548f, -0.808656182f, + -0.585797857f, -0.810457198f, + -0.583308653f, -0.812250587f, + -0.580813958f, -0.814036330f, + -0.578313796f, -0.815814411f, + -0.575808191f, -0.817584813f, + -0.573297167f, -0.819347520f, + -0.570780746f, -0.821102515f, + -0.568258953f, -0.822849781f, + -0.565731811f, -0.824589303f, + -0.563199344f, -0.826321063f, + -0.560661576f, -0.828045045f, + -0.558118531f, -0.829761234f, + -0.555570233f, -0.831469612f, + -0.553016706f, -0.833170165f, + -0.550457973f, -0.834862875f, + -0.547894059f, -0.836547727f, + -0.545324988f, -0.838224706f, + -0.542750785f, -0.839893794f, + -0.540171473f, -0.841554977f, + -0.537587076f, -0.843208240f, + -0.534997620f, -0.844853565f, + -0.532403128f, -0.846490939f, + -0.529803625f, -0.848120345f, + -0.527199135f, -0.849741768f, + -0.524589683f, -0.851355193f, + -0.521975293f, -0.852960605f, + -0.519355990f, -0.854557988f, + -0.516731799f, -0.856147328f, + -0.514102744f, -0.857728610f, + -0.511468850f, -0.859301818f, + -0.508830143f, -0.860866939f, + -0.506186645f, -0.862423956f, + -0.503538384f, -0.863972856f, + -0.500885383f, -0.865513624f, + -0.498227667f, -0.867046246f, + -0.495565262f, -0.868570706f, + -0.492898192f, -0.870086991f, + -0.490226483f, -0.871595087f, + -0.487550160f, -0.873094978f, + -0.484869248f, -0.874586652f, + -0.482183772f, -0.876070094f, + -0.479493758f, -0.877545290f, + -0.476799230f, -0.879012226f, + -0.474100215f, -0.880470889f, + -0.471396737f, -0.881921264f, + -0.468688822f, -0.883363339f, + -0.465976496f, -0.884797098f, + -0.463259784f, -0.886222530f, + -0.460538711f, -0.887639620f, + -0.457813304f, -0.889048356f, + -0.455083587f, -0.890448723f, + -0.452349587f, -0.891840709f, + -0.449611330f, -0.893224301f, + -0.446868840f, -0.894599486f, + -0.444122145f, -0.895966250f, + -0.441371269f, -0.897324581f, + -0.438616239f, -0.898674466f, + -0.435857080f, -0.900015892f, + -0.433093819f, -0.901348847f, + -0.430326481f, -0.902673318f, + -0.427555093f, -0.903989293f, + -0.424779681f, -0.905296759f, + -0.422000271f, -0.906595705f, + -0.419216888f, -0.907886116f, + -0.416429560f, -0.909167983f, + -0.413638312f, -0.910441292f, + -0.410843171f, -0.911706032f, + -0.408044163f, -0.912962190f, + -0.405241314f, -0.914209756f, + -0.402434651f, -0.915448716f, + -0.399624200f, -0.916679060f, + -0.396809987f, -0.917900776f, + -0.393992040f, -0.919113852f, + -0.391170384f, -0.920318277f, + -0.388345047f, -0.921514039f, + -0.385516054f, -0.922701128f, + -0.382683432f, -0.923879533f, + -0.379847209f, -0.925049241f, + -0.377007410f, -0.926210242f, + -0.374164063f, -0.927362526f, + -0.371317194f, -0.928506080f, + -0.368466830f, -0.929640896f, + -0.365612998f, -0.930766961f, + -0.362755724f, -0.931884266f, + -0.359895037f, -0.932992799f, + -0.357030961f, -0.934092550f, + -0.354163525f, -0.935183510f, + -0.351292756f, -0.936265667f, + -0.348418680f, -0.937339012f, + -0.345541325f, -0.938403534f, + -0.342660717f, -0.939459224f, + -0.339776884f, -0.940506071f, + -0.336889853f, -0.941544065f, + -0.333999651f, -0.942573198f, + -0.331106306f, -0.943593458f, + -0.328209844f, -0.944604837f, + -0.325310292f, -0.945607325f, + -0.322407679f, -0.946600913f, + -0.319502031f, -0.947585591f, + -0.316593376f, -0.948561350f, + -0.313681740f, -0.949528181f, + -0.310767153f, -0.950486074f, + -0.307849640f, -0.951435021f, + -0.304929230f, -0.952375013f, + -0.302005949f, -0.953306040f, + -0.299079826f, -0.954228095f, + -0.296150888f, -0.955141168f, + -0.293219163f, -0.956045251f, + -0.290284677f, -0.956940336f, + -0.287347460f, -0.957826413f, + -0.284407537f, -0.958703475f, + -0.281464938f, -0.959571513f, + -0.278519689f, -0.960430519f, + -0.275571819f, -0.961280486f, + -0.272621355f, -0.962121404f, + -0.269668326f, -0.962953267f, + -0.266712757f, -0.963776066f, + -0.263754679f, -0.964589793f, + -0.260794118f, -0.965394442f, + -0.257831102f, -0.966190003f, + -0.254865660f, -0.966976471f, + -0.251897818f, -0.967753837f, + -0.248927606f, -0.968522094f, + -0.245955050f, -0.969281235f, + -0.242980180f, -0.970031253f, + -0.240003022f, -0.970772141f, + -0.237023606f, -0.971503891f, + -0.234041959f, -0.972226497f, + -0.231058108f, -0.972939952f, + -0.228072083f, -0.973644250f, + -0.225083911f, -0.974339383f, + -0.222093621f, -0.975025345f, + -0.219101240f, -0.975702130f, + -0.216106797f, -0.976369731f, + -0.213110320f, -0.977028143f, + -0.210111837f, -0.977677358f, + -0.207111376f, -0.978317371f, + -0.204108966f, -0.978948175f, + -0.201104635f, -0.979569766f, + -0.198098411f, -0.980182136f, + -0.195090322f, -0.980785280f, + -0.192080397f, -0.981379193f, + -0.189068664f, -0.981963869f, + -0.186055152f, -0.982539302f, + -0.183039888f, -0.983105487f, + -0.180022901f, -0.983662419f, + -0.177004220f, -0.984210092f, + -0.173983873f, -0.984748502f, + -0.170961889f, -0.985277642f, + -0.167938295f, -0.985797509f, + -0.164913120f, -0.986308097f, + -0.161886394f, -0.986809402f, + -0.158858143f, -0.987301418f, + -0.155828398f, -0.987784142f, + -0.152797185f, -0.988257568f, + -0.149764535f, -0.988721692f, + -0.146730474f, -0.989176510f, + -0.143695033f, -0.989622017f, + -0.140658239f, -0.990058210f, + -0.137620122f, -0.990485084f, + -0.134580709f, -0.990902635f, + -0.131540029f, -0.991310860f, + -0.128498111f, -0.991709754f, + -0.125454983f, -0.992099313f, + -0.122410675f, -0.992479535f, + -0.119365215f, -0.992850414f, + -0.116318631f, -0.993211949f, + -0.113270952f, -0.993564136f, + -0.110222207f, -0.993906970f, + -0.107172425f, -0.994240449f, + -0.104121634f, -0.994564571f, + -0.101069863f, -0.994879331f, + -0.098017140f, -0.995184727f, + -0.094963495f, -0.995480755f, + -0.091908956f, -0.995767414f, + -0.088853553f, -0.996044701f, + -0.085797312f, -0.996312612f, + -0.082740265f, -0.996571146f, + -0.079682438f, -0.996820299f, + -0.076623861f, -0.997060070f, + -0.073564564f, -0.997290457f, + -0.070504573f, -0.997511456f, + -0.067443920f, -0.997723067f, + -0.064382631f, -0.997925286f, + -0.061320736f, -0.998118113f, + -0.058258265f, -0.998301545f, + -0.055195244f, -0.998475581f, + -0.052131705f, -0.998640218f, + -0.049067674f, -0.998795456f, + -0.046003182f, -0.998941293f, + -0.042938257f, -0.999077728f, + -0.039872928f, -0.999204759f, + -0.036807223f, -0.999322385f, + -0.033741172f, -0.999430605f, + -0.030674803f, -0.999529418f, + -0.027608146f, -0.999618822f, + -0.024541229f, -0.999698819f, + -0.021474080f, -0.999769405f, + -0.018406730f, -0.999830582f, + -0.015339206f, -0.999882347f, + -0.012271538f, -0.999924702f, + -0.009203755f, -0.999957645f, + -0.006135885f, -0.999981175f, + -0.003067957f, -0.999995294f, + -0.000000000f, -1.000000000f, + 0.003067957f, -0.999995294f, + 0.006135885f, -0.999981175f, + 0.009203755f, -0.999957645f, + 0.012271538f, -0.999924702f, + 0.015339206f, -0.999882347f, + 0.018406730f, -0.999830582f, + 0.021474080f, -0.999769405f, + 0.024541229f, -0.999698819f, + 0.027608146f, -0.999618822f, + 0.030674803f, -0.999529418f, + 0.033741172f, -0.999430605f, + 0.036807223f, -0.999322385f, + 0.039872928f, -0.999204759f, + 0.042938257f, -0.999077728f, + 0.046003182f, -0.998941293f, + 0.049067674f, -0.998795456f, + 0.052131705f, -0.998640218f, + 0.055195244f, -0.998475581f, + 0.058258265f, -0.998301545f, + 0.061320736f, -0.998118113f, + 0.064382631f, -0.997925286f, + 0.067443920f, -0.997723067f, + 0.070504573f, -0.997511456f, + 0.073564564f, -0.997290457f, + 0.076623861f, -0.997060070f, + 0.079682438f, -0.996820299f, + 0.082740265f, -0.996571146f, + 0.085797312f, -0.996312612f, + 0.088853553f, -0.996044701f, + 0.091908956f, -0.995767414f, + 0.094963495f, -0.995480755f, + 0.098017140f, -0.995184727f, + 0.101069863f, -0.994879331f, + 0.104121634f, -0.994564571f, + 0.107172425f, -0.994240449f, + 0.110222207f, -0.993906970f, + 0.113270952f, -0.993564136f, + 0.116318631f, -0.993211949f, + 0.119365215f, -0.992850414f, + 0.122410675f, -0.992479535f, + 0.125454983f, -0.992099313f, + 0.128498111f, -0.991709754f, + 0.131540029f, -0.991310860f, + 0.134580709f, -0.990902635f, + 0.137620122f, -0.990485084f, + 0.140658239f, -0.990058210f, + 0.143695033f, -0.989622017f, + 0.146730474f, -0.989176510f, + 0.149764535f, -0.988721692f, + 0.152797185f, -0.988257568f, + 0.155828398f, -0.987784142f, + 0.158858143f, -0.987301418f, + 0.161886394f, -0.986809402f, + 0.164913120f, -0.986308097f, + 0.167938295f, -0.985797509f, + 0.170961889f, -0.985277642f, + 0.173983873f, -0.984748502f, + 0.177004220f, -0.984210092f, + 0.180022901f, -0.983662419f, + 0.183039888f, -0.983105487f, + 0.186055152f, -0.982539302f, + 0.189068664f, -0.981963869f, + 0.192080397f, -0.981379193f, + 0.195090322f, -0.980785280f, + 0.198098411f, -0.980182136f, + 0.201104635f, -0.979569766f, + 0.204108966f, -0.978948175f, + 0.207111376f, -0.978317371f, + 0.210111837f, -0.977677358f, + 0.213110320f, -0.977028143f, + 0.216106797f, -0.976369731f, + 0.219101240f, -0.975702130f, + 0.222093621f, -0.975025345f, + 0.225083911f, -0.974339383f, + 0.228072083f, -0.973644250f, + 0.231058108f, -0.972939952f, + 0.234041959f, -0.972226497f, + 0.237023606f, -0.971503891f, + 0.240003022f, -0.970772141f, + 0.242980180f, -0.970031253f, + 0.245955050f, -0.969281235f, + 0.248927606f, -0.968522094f, + 0.251897818f, -0.967753837f, + 0.254865660f, -0.966976471f, + 0.257831102f, -0.966190003f, + 0.260794118f, -0.965394442f, + 0.263754679f, -0.964589793f, + 0.266712757f, -0.963776066f, + 0.269668326f, -0.962953267f, + 0.272621355f, -0.962121404f, + 0.275571819f, -0.961280486f, + 0.278519689f, -0.960430519f, + 0.281464938f, -0.959571513f, + 0.284407537f, -0.958703475f, + 0.287347460f, -0.957826413f, + 0.290284677f, -0.956940336f, + 0.293219163f, -0.956045251f, + 0.296150888f, -0.955141168f, + 0.299079826f, -0.954228095f, + 0.302005949f, -0.953306040f, + 0.304929230f, -0.952375013f, + 0.307849640f, -0.951435021f, + 0.310767153f, -0.950486074f, + 0.313681740f, -0.949528181f, + 0.316593376f, -0.948561350f, + 0.319502031f, -0.947585591f, + 0.322407679f, -0.946600913f, + 0.325310292f, -0.945607325f, + 0.328209844f, -0.944604837f, + 0.331106306f, -0.943593458f, + 0.333999651f, -0.942573198f, + 0.336889853f, -0.941544065f, + 0.339776884f, -0.940506071f, + 0.342660717f, -0.939459224f, + 0.345541325f, -0.938403534f, + 0.348418680f, -0.937339012f, + 0.351292756f, -0.936265667f, + 0.354163525f, -0.935183510f, + 0.357030961f, -0.934092550f, + 0.359895037f, -0.932992799f, + 0.362755724f, -0.931884266f, + 0.365612998f, -0.930766961f, + 0.368466830f, -0.929640896f, + 0.371317194f, -0.928506080f, + 0.374164063f, -0.927362526f, + 0.377007410f, -0.926210242f, + 0.379847209f, -0.925049241f, + 0.382683432f, -0.923879533f, + 0.385516054f, -0.922701128f, + 0.388345047f, -0.921514039f, + 0.391170384f, -0.920318277f, + 0.393992040f, -0.919113852f, + 0.396809987f, -0.917900776f, + 0.399624200f, -0.916679060f, + 0.402434651f, -0.915448716f, + 0.405241314f, -0.914209756f, + 0.408044163f, -0.912962190f, + 0.410843171f, -0.911706032f, + 0.413638312f, -0.910441292f, + 0.416429560f, -0.909167983f, + 0.419216888f, -0.907886116f, + 0.422000271f, -0.906595705f, + 0.424779681f, -0.905296759f, + 0.427555093f, -0.903989293f, + 0.430326481f, -0.902673318f, + 0.433093819f, -0.901348847f, + 0.435857080f, -0.900015892f, + 0.438616239f, -0.898674466f, + 0.441371269f, -0.897324581f, + 0.444122145f, -0.895966250f, + 0.446868840f, -0.894599486f, + 0.449611330f, -0.893224301f, + 0.452349587f, -0.891840709f, + 0.455083587f, -0.890448723f, + 0.457813304f, -0.889048356f, + 0.460538711f, -0.887639620f, + 0.463259784f, -0.886222530f, + 0.465976496f, -0.884797098f, + 0.468688822f, -0.883363339f, + 0.471396737f, -0.881921264f, + 0.474100215f, -0.880470889f, + 0.476799230f, -0.879012226f, + 0.479493758f, -0.877545290f, + 0.482183772f, -0.876070094f, + 0.484869248f, -0.874586652f, + 0.487550160f, -0.873094978f, + 0.490226483f, -0.871595087f, + 0.492898192f, -0.870086991f, + 0.495565262f, -0.868570706f, + 0.498227667f, -0.867046246f, + 0.500885383f, -0.865513624f, + 0.503538384f, -0.863972856f, + 0.506186645f, -0.862423956f, + 0.508830143f, -0.860866939f, + 0.511468850f, -0.859301818f, + 0.514102744f, -0.857728610f, + 0.516731799f, -0.856147328f, + 0.519355990f, -0.854557988f, + 0.521975293f, -0.852960605f, + 0.524589683f, -0.851355193f, + 0.527199135f, -0.849741768f, + 0.529803625f, -0.848120345f, + 0.532403128f, -0.846490939f, + 0.534997620f, -0.844853565f, + 0.537587076f, -0.843208240f, + 0.540171473f, -0.841554977f, + 0.542750785f, -0.839893794f, + 0.545324988f, -0.838224706f, + 0.547894059f, -0.836547727f, + 0.550457973f, -0.834862875f, + 0.553016706f, -0.833170165f, + 0.555570233f, -0.831469612f, + 0.558118531f, -0.829761234f, + 0.560661576f, -0.828045045f, + 0.563199344f, -0.826321063f, + 0.565731811f, -0.824589303f, + 0.568258953f, -0.822849781f, + 0.570780746f, -0.821102515f, + 0.573297167f, -0.819347520f, + 0.575808191f, -0.817584813f, + 0.578313796f, -0.815814411f, + 0.580813958f, -0.814036330f, + 0.583308653f, -0.812250587f, + 0.585797857f, -0.810457198f, + 0.588281548f, -0.808656182f, + 0.590759702f, -0.806847554f, + 0.593232295f, -0.805031331f, + 0.595699304f, -0.803207531f, + 0.598160707f, -0.801376172f, + 0.600616479f, -0.799537269f, + 0.603066599f, -0.797690841f, + 0.605511041f, -0.795836905f, + 0.607949785f, -0.793975478f, + 0.610382806f, -0.792106577f, + 0.612810082f, -0.790230221f, + 0.615231591f, -0.788346428f, + 0.617647308f, -0.786455214f, + 0.620057212f, -0.784556597f, + 0.622461279f, -0.782650596f, + 0.624859488f, -0.780737229f, + 0.627251815f, -0.778816512f, + 0.629638239f, -0.776888466f, + 0.632018736f, -0.774953107f, + 0.634393284f, -0.773010453f, + 0.636761861f, -0.771060524f, + 0.639124445f, -0.769103338f, + 0.641481013f, -0.767138912f, + 0.643831543f, -0.765167266f, + 0.646176013f, -0.763188417f, + 0.648514401f, -0.761202385f, + 0.650846685f, -0.759209189f, + 0.653172843f, -0.757208847f, + 0.655492853f, -0.755201377f, + 0.657806693f, -0.753186799f, + 0.660114342f, -0.751165132f, + 0.662415778f, -0.749136395f, + 0.664710978f, -0.747100606f, + 0.666999922f, -0.745057785f, + 0.669282588f, -0.743007952f, + 0.671558955f, -0.740951125f, + 0.673829000f, -0.738887324f, + 0.676092704f, -0.736816569f, + 0.678350043f, -0.734738878f, + 0.680600998f, -0.732654272f, + 0.682845546f, -0.730562769f, + 0.685083668f, -0.728464390f, + 0.687315341f, -0.726359155f, + 0.689540545f, -0.724247083f, + 0.691759258f, -0.722128194f, + 0.693971461f, -0.720002508f, + 0.696177131f, -0.717870045f, + 0.698376249f, -0.715730825f, + 0.700568794f, -0.713584869f, + 0.702754744f, -0.711432196f, + 0.704934080f, -0.709272826f, + 0.707106781f, -0.707106781f, + 0.709272826f, -0.704934080f, + 0.711432196f, -0.702754744f, + 0.713584869f, -0.700568794f, + 0.715730825f, -0.698376249f, + 0.717870045f, -0.696177131f, + 0.720002508f, -0.693971461f, + 0.722128194f, -0.691759258f, + 0.724247083f, -0.689540545f, + 0.726359155f, -0.687315341f, + 0.728464390f, -0.685083668f, + 0.730562769f, -0.682845546f, + 0.732654272f, -0.680600998f, + 0.734738878f, -0.678350043f, + 0.736816569f, -0.676092704f, + 0.738887324f, -0.673829000f, + 0.740951125f, -0.671558955f, + 0.743007952f, -0.669282588f, + 0.745057785f, -0.666999922f, + 0.747100606f, -0.664710978f, + 0.749136395f, -0.662415778f, + 0.751165132f, -0.660114342f, + 0.753186799f, -0.657806693f, + 0.755201377f, -0.655492853f, + 0.757208847f, -0.653172843f, + 0.759209189f, -0.650846685f, + 0.761202385f, -0.648514401f, + 0.763188417f, -0.646176013f, + 0.765167266f, -0.643831543f, + 0.767138912f, -0.641481013f, + 0.769103338f, -0.639124445f, + 0.771060524f, -0.636761861f, + 0.773010453f, -0.634393284f, + 0.774953107f, -0.632018736f, + 0.776888466f, -0.629638239f, + 0.778816512f, -0.627251815f, + 0.780737229f, -0.624859488f, + 0.782650596f, -0.622461279f, + 0.784556597f, -0.620057212f, + 0.786455214f, -0.617647308f, + 0.788346428f, -0.615231591f, + 0.790230221f, -0.612810082f, + 0.792106577f, -0.610382806f, + 0.793975478f, -0.607949785f, + 0.795836905f, -0.605511041f, + 0.797690841f, -0.603066599f, + 0.799537269f, -0.600616479f, + 0.801376172f, -0.598160707f, + 0.803207531f, -0.595699304f, + 0.805031331f, -0.593232295f, + 0.806847554f, -0.590759702f, + 0.808656182f, -0.588281548f, + 0.810457198f, -0.585797857f, + 0.812250587f, -0.583308653f, + 0.814036330f, -0.580813958f, + 0.815814411f, -0.578313796f, + 0.817584813f, -0.575808191f, + 0.819347520f, -0.573297167f, + 0.821102515f, -0.570780746f, + 0.822849781f, -0.568258953f, + 0.824589303f, -0.565731811f, + 0.826321063f, -0.563199344f, + 0.828045045f, -0.560661576f, + 0.829761234f, -0.558118531f, + 0.831469612f, -0.555570233f, + 0.833170165f, -0.553016706f, + 0.834862875f, -0.550457973f, + 0.836547727f, -0.547894059f, + 0.838224706f, -0.545324988f, + 0.839893794f, -0.542750785f, + 0.841554977f, -0.540171473f, + 0.843208240f, -0.537587076f, + 0.844853565f, -0.534997620f, + 0.846490939f, -0.532403128f, + 0.848120345f, -0.529803625f, + 0.849741768f, -0.527199135f, + 0.851355193f, -0.524589683f, + 0.852960605f, -0.521975293f, + 0.854557988f, -0.519355990f, + 0.856147328f, -0.516731799f, + 0.857728610f, -0.514102744f, + 0.859301818f, -0.511468850f, + 0.860866939f, -0.508830143f, + 0.862423956f, -0.506186645f, + 0.863972856f, -0.503538384f, + 0.865513624f, -0.500885383f, + 0.867046246f, -0.498227667f, + 0.868570706f, -0.495565262f, + 0.870086991f, -0.492898192f, + 0.871595087f, -0.490226483f, + 0.873094978f, -0.487550160f, + 0.874586652f, -0.484869248f, + 0.876070094f, -0.482183772f, + 0.877545290f, -0.479493758f, + 0.879012226f, -0.476799230f, + 0.880470889f, -0.474100215f, + 0.881921264f, -0.471396737f, + 0.883363339f, -0.468688822f, + 0.884797098f, -0.465976496f, + 0.886222530f, -0.463259784f, + 0.887639620f, -0.460538711f, + 0.889048356f, -0.457813304f, + 0.890448723f, -0.455083587f, + 0.891840709f, -0.452349587f, + 0.893224301f, -0.449611330f, + 0.894599486f, -0.446868840f, + 0.895966250f, -0.444122145f, + 0.897324581f, -0.441371269f, + 0.898674466f, -0.438616239f, + 0.900015892f, -0.435857080f, + 0.901348847f, -0.433093819f, + 0.902673318f, -0.430326481f, + 0.903989293f, -0.427555093f, + 0.905296759f, -0.424779681f, + 0.906595705f, -0.422000271f, + 0.907886116f, -0.419216888f, + 0.909167983f, -0.416429560f, + 0.910441292f, -0.413638312f, + 0.911706032f, -0.410843171f, + 0.912962190f, -0.408044163f, + 0.914209756f, -0.405241314f, + 0.915448716f, -0.402434651f, + 0.916679060f, -0.399624200f, + 0.917900776f, -0.396809987f, + 0.919113852f, -0.393992040f, + 0.920318277f, -0.391170384f, + 0.921514039f, -0.388345047f, + 0.922701128f, -0.385516054f, + 0.923879533f, -0.382683432f, + 0.925049241f, -0.379847209f, + 0.926210242f, -0.377007410f, + 0.927362526f, -0.374164063f, + 0.928506080f, -0.371317194f, + 0.929640896f, -0.368466830f, + 0.930766961f, -0.365612998f, + 0.931884266f, -0.362755724f, + 0.932992799f, -0.359895037f, + 0.934092550f, -0.357030961f, + 0.935183510f, -0.354163525f, + 0.936265667f, -0.351292756f, + 0.937339012f, -0.348418680f, + 0.938403534f, -0.345541325f, + 0.939459224f, -0.342660717f, + 0.940506071f, -0.339776884f, + 0.941544065f, -0.336889853f, + 0.942573198f, -0.333999651f, + 0.943593458f, -0.331106306f, + 0.944604837f, -0.328209844f, + 0.945607325f, -0.325310292f, + 0.946600913f, -0.322407679f, + 0.947585591f, -0.319502031f, + 0.948561350f, -0.316593376f, + 0.949528181f, -0.313681740f, + 0.950486074f, -0.310767153f, + 0.951435021f, -0.307849640f, + 0.952375013f, -0.304929230f, + 0.953306040f, -0.302005949f, + 0.954228095f, -0.299079826f, + 0.955141168f, -0.296150888f, + 0.956045251f, -0.293219163f, + 0.956940336f, -0.290284677f, + 0.957826413f, -0.287347460f, + 0.958703475f, -0.284407537f, + 0.959571513f, -0.281464938f, + 0.960430519f, -0.278519689f, + 0.961280486f, -0.275571819f, + 0.962121404f, -0.272621355f, + 0.962953267f, -0.269668326f, + 0.963776066f, -0.266712757f, + 0.964589793f, -0.263754679f, + 0.965394442f, -0.260794118f, + 0.966190003f, -0.257831102f, + 0.966976471f, -0.254865660f, + 0.967753837f, -0.251897818f, + 0.968522094f, -0.248927606f, + 0.969281235f, -0.245955050f, + 0.970031253f, -0.242980180f, + 0.970772141f, -0.240003022f, + 0.971503891f, -0.237023606f, + 0.972226497f, -0.234041959f, + 0.972939952f, -0.231058108f, + 0.973644250f, -0.228072083f, + 0.974339383f, -0.225083911f, + 0.975025345f, -0.222093621f, + 0.975702130f, -0.219101240f, + 0.976369731f, -0.216106797f, + 0.977028143f, -0.213110320f, + 0.977677358f, -0.210111837f, + 0.978317371f, -0.207111376f, + 0.978948175f, -0.204108966f, + 0.979569766f, -0.201104635f, + 0.980182136f, -0.198098411f, + 0.980785280f, -0.195090322f, + 0.981379193f, -0.192080397f, + 0.981963869f, -0.189068664f, + 0.982539302f, -0.186055152f, + 0.983105487f, -0.183039888f, + 0.983662419f, -0.180022901f, + 0.984210092f, -0.177004220f, + 0.984748502f, -0.173983873f, + 0.985277642f, -0.170961889f, + 0.985797509f, -0.167938295f, + 0.986308097f, -0.164913120f, + 0.986809402f, -0.161886394f, + 0.987301418f, -0.158858143f, + 0.987784142f, -0.155828398f, + 0.988257568f, -0.152797185f, + 0.988721692f, -0.149764535f, + 0.989176510f, -0.146730474f, + 0.989622017f, -0.143695033f, + 0.990058210f, -0.140658239f, + 0.990485084f, -0.137620122f, + 0.990902635f, -0.134580709f, + 0.991310860f, -0.131540029f, + 0.991709754f, -0.128498111f, + 0.992099313f, -0.125454983f, + 0.992479535f, -0.122410675f, + 0.992850414f, -0.119365215f, + 0.993211949f, -0.116318631f, + 0.993564136f, -0.113270952f, + 0.993906970f, -0.110222207f, + 0.994240449f, -0.107172425f, + 0.994564571f, -0.104121634f, + 0.994879331f, -0.101069863f, + 0.995184727f, -0.098017140f, + 0.995480755f, -0.094963495f, + 0.995767414f, -0.091908956f, + 0.996044701f, -0.088853553f, + 0.996312612f, -0.085797312f, + 0.996571146f, -0.082740265f, + 0.996820299f, -0.079682438f, + 0.997060070f, -0.076623861f, + 0.997290457f, -0.073564564f, + 0.997511456f, -0.070504573f, + 0.997723067f, -0.067443920f, + 0.997925286f, -0.064382631f, + 0.998118113f, -0.061320736f, + 0.998301545f, -0.058258265f, + 0.998475581f, -0.055195244f, + 0.998640218f, -0.052131705f, + 0.998795456f, -0.049067674f, + 0.998941293f, -0.046003182f, + 0.999077728f, -0.042938257f, + 0.999204759f, -0.039872928f, + 0.999322385f, -0.036807223f, + 0.999430605f, -0.033741172f, + 0.999529418f, -0.030674803f, + 0.999618822f, -0.027608146f, + 0.999698819f, -0.024541229f, + 0.999769405f, -0.021474080f, + 0.999830582f, -0.018406730f, + 0.999882347f, -0.015339206f, + 0.999924702f, -0.012271538f, + 0.999957645f, -0.009203755f, + 0.999981175f, -0.006135885f, + 0.999995294f, -0.003067957f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par +
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 4096, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_4096[8192] = { + 1.000000000f, 0.000000000f, + 0.999998823f, 0.001533980f, + 0.999995294f, 0.003067957f, + 0.999989411f, 0.004601926f, + 0.999981175f, 0.006135885f, + 0.999970586f, 0.007669829f, + 0.999957645f, 0.009203755f, + 0.999942350f, 0.010737659f, + 0.999924702f, 0.012271538f, + 0.999904701f, 0.013805389f, + 0.999882347f, 0.015339206f, + 0.999857641f, 0.016872988f, + 0.999830582f, 0.018406730f, + 0.999801170f, 0.019940429f, + 0.999769405f, 0.021474080f, + 0.999735288f, 0.023007681f, + 0.999698819f, 0.024541229f, + 0.999659997f, 0.026074718f, + 0.999618822f, 0.027608146f, + 0.999575296f, 0.029141509f, + 0.999529418f, 0.030674803f, + 0.999481187f, 0.032208025f, + 0.999430605f, 0.033741172f, + 0.999377670f, 0.035274239f, + 0.999322385f, 0.036807223f, + 0.999264747f, 0.038340120f, + 0.999204759f, 0.039872928f, + 0.999142419f, 0.041405641f, + 0.999077728f, 0.042938257f, + 0.999010686f, 0.044470772f, + 0.998941293f, 0.046003182f, + 0.998869550f, 0.047535484f, + 0.998795456f, 0.049067674f, + 0.998719012f, 0.050599749f, + 0.998640218f, 0.052131705f, + 0.998559074f, 0.053663538f, + 0.998475581f, 0.055195244f, + 0.998389737f, 0.056726821f, + 0.998301545f, 0.058258265f, + 0.998211003f, 0.059789571f, + 0.998118113f, 0.061320736f, + 0.998022874f, 0.062851758f, + 0.997925286f, 0.064382631f, + 0.997825350f, 0.065913353f, + 0.997723067f, 0.067443920f, + 0.997618435f, 0.068974328f, + 0.997511456f, 0.070504573f, + 0.997402130f, 0.072034653f, + 0.997290457f, 0.073564564f, + 0.997176437f, 0.075094301f, + 0.997060070f, 0.076623861f, + 0.996941358f, 0.078153242f, + 0.996820299f, 0.079682438f, + 0.996696895f, 0.081211447f, + 0.996571146f, 0.082740265f, + 0.996443051f, 0.084268888f, + 0.996312612f, 0.085797312f, + 0.996179829f, 0.087325535f, + 0.996044701f, 0.088853553f, + 0.995907229f, 0.090381361f, + 0.995767414f, 0.091908956f, + 0.995625256f, 0.093436336f, + 0.995480755f, 0.094963495f, + 0.995333912f, 0.096490431f, + 0.995184727f, 0.098017140f, + 0.995033199f, 0.099543619f, + 0.994879331f, 0.101069863f, + 0.994723121f, 0.102595869f, + 0.994564571f, 0.104121634f, + 0.994403680f, 0.105647154f, + 0.994240449f, 0.107172425f, + 0.994074879f, 0.108697444f, + 0.993906970f, 0.110222207f, + 0.993736722f, 0.111746711f, + 0.993564136f, 0.113270952f, + 0.993389211f, 0.114794927f, + 0.993211949f, 0.116318631f, + 0.993032350f, 0.117842062f, + 0.992850414f, 0.119365215f, + 0.992666142f, 0.120888087f, + 0.992479535f, 0.122410675f, + 0.992290591f, 0.123932975f, + 0.992099313f, 0.125454983f, + 0.991905700f, 0.126976696f, + 0.991709754f, 0.128498111f, + 0.991511473f, 0.130019223f, + 0.991310860f, 0.131540029f, + 0.991107914f, 0.133060525f, + 0.990902635f, 0.134580709f, + 0.990695025f, 0.136100575f, + 0.990485084f, 0.137620122f, + 0.990272812f, 0.139139344f, + 0.990058210f, 0.140658239f, + 0.989841278f, 0.142176804f, + 0.989622017f, 0.143695033f, + 0.989400428f, 0.145212925f, + 0.989176510f, 0.146730474f, + 0.988950265f, 0.148247679f, + 0.988721692f, 0.149764535f, + 0.988490793f, 0.151281038f, + 0.988257568f, 0.152797185f, + 0.988022017f, 0.154312973f, + 0.987784142f, 0.155828398f, + 0.987543942f, 0.157343456f, + 0.987301418f, 0.158858143f, + 0.987056571f, 0.160372457f, + 0.986809402f, 0.161886394f, + 0.986559910f, 0.163399949f, + 0.986308097f, 0.164913120f, + 0.986053963f, 0.166425904f, + 0.985797509f, 0.167938295f, + 0.985538735f, 0.169450291f, + 0.985277642f, 0.170961889f, + 0.985014231f, 0.172473084f, + 0.984748502f, 0.173983873f, + 0.984480455f, 0.175494253f, + 0.984210092f, 0.177004220f, + 0.983937413f, 0.178513771f, + 0.983662419f, 0.180022901f, + 0.983385110f, 0.181531608f, + 0.983105487f, 0.183039888f, + 0.982823551f, 0.184547737f, + 0.982539302f, 0.186055152f, + 0.982252741f, 0.187562129f, + 0.981963869f, 0.189068664f, + 0.981672686f, 0.190574755f, + 0.981379193f, 0.192080397f, + 0.981083391f, 0.193585587f, + 0.980785280f, 0.195090322f, + 0.980484862f, 0.196594598f, + 0.980182136f, 0.198098411f, + 0.979877104f, 0.199601758f, + 0.979569766f, 0.201104635f, + 0.979260123f, 0.202607039f, + 0.978948175f, 0.204108966f, + 0.978633924f, 0.205610413f, + 0.978317371f, 0.207111376f, + 0.977998515f, 0.208611852f, + 0.977677358f, 0.210111837f, + 0.977353900f, 0.211611327f, + 0.977028143f, 0.213110320f, + 0.976700086f, 0.214608811f, + 0.976369731f, 0.216106797f, + 0.976037079f, 0.217604275f, + 0.975702130f, 0.219101240f, + 0.975364885f, 0.220597690f, + 0.975025345f, 0.222093621f, + 0.974683511f, 0.223589029f, + 0.974339383f, 0.225083911f, + 0.973992962f, 0.226578264f, + 0.973644250f, 0.228072083f, + 0.973293246f, 0.229565366f, + 0.972939952f, 0.231058108f, + 0.972584369f, 0.232550307f, + 0.972226497f, 0.234041959f, + 0.971866337f, 0.235533059f, + 0.971503891f, 0.237023606f, + 0.971139158f, 0.238513595f, + 0.970772141f, 0.240003022f, + 0.970402839f, 0.241491885f, + 0.970031253f, 0.242980180f, + 0.969657385f, 0.244467903f, + 0.969281235f, 0.245955050f, + 0.968902805f, 0.247441619f, + 0.968522094f, 0.248927606f, + 0.968139105f, 0.250413007f, + 0.967753837f, 0.251897818f, + 0.967366292f, 0.253382037f, + 0.966976471f, 0.254865660f, + 0.966584374f, 0.256348682f, + 0.966190003f, 0.257831102f, + 0.965793359f, 0.259312915f, + 0.965394442f, 0.260794118f, + 0.964993253f, 0.262274707f, + 0.964589793f, 0.263754679f, + 0.964184064f, 0.265234030f, + 0.963776066f, 0.266712757f, + 0.963365800f, 0.268190857f, + 0.962953267f, 0.269668326f, + 0.962538468f, 0.271145160f, + 0.962121404f, 0.272621355f, + 0.961702077f, 0.274096910f, + 0.961280486f, 0.275571819f, + 0.960856633f, 0.277046080f, + 0.960430519f, 0.278519689f, + 0.960002146f, 0.279992643f, + 0.959571513f, 0.281464938f, + 0.959138622f, 0.282936570f, + 0.958703475f, 0.284407537f, + 0.958266071f, 0.285877835f, + 0.957826413f, 0.287347460f, + 0.957384501f, 0.288816408f, + 0.956940336f, 0.290284677f, + 0.956493919f, 0.291752263f, + 0.956045251f, 0.293219163f, + 0.955594334f, 0.294685372f, + 0.955141168f, 0.296150888f, + 0.954685755f, 0.297615707f, + 0.954228095f, 0.299079826f, + 0.953768190f, 0.300543241f, + 0.953306040f, 0.302005949f, + 0.952841648f, 0.303467947f, + 0.952375013f, 0.304929230f, + 0.951906137f, 0.306389795f, + 0.951435021f, 0.307849640f, + 0.950961666f, 0.309308760f, + 0.950486074f, 0.310767153f, + 0.950008245f, 0.312224814f, + 0.949528181f, 0.313681740f, + 0.949045882f, 0.315137929f, + 0.948561350f, 0.316593376f, + 0.948074586f, 0.318048077f, + 0.947585591f, 0.319502031f, + 0.947094366f, 0.320955232f, + 0.946600913f, 0.322407679f, + 0.946105232f, 0.323859367f, + 0.945607325f, 0.325310292f, + 0.945107193f, 0.326760452f, + 0.944604837f, 0.328209844f, + 0.944100258f, 0.329658463f, + 0.943593458f, 0.331106306f, + 0.943084437f, 0.332553370f, + 0.942573198f, 0.333999651f, + 0.942059740f, 0.335445147f, + 0.941544065f, 0.336889853f, + 0.941026175f, 0.338333767f, + 0.940506071f, 0.339776884f, + 0.939983753f, 0.341219202f, + 0.939459224f, 0.342660717f, + 0.938932484f, 0.344101426f, + 0.938403534f, 0.345541325f, + 0.937872376f, 0.346980411f, + 0.937339012f, 0.348418680f, + 0.936803442f, 0.349856130f, + 0.936265667f, 0.351292756f, + 0.935725689f, 0.352728556f, + 0.935183510f, 0.354163525f, + 0.934639130f, 0.355597662f, + 0.934092550f, 0.357030961f, + 0.933543773f, 0.358463421f, + 0.932992799f, 0.359895037f, + 0.932439629f, 0.361325806f, + 0.931884266f, 0.362755724f, + 0.931326709f, 0.364184790f, + 0.930766961f, 0.365612998f, + 0.930205023f, 0.367040346f, + 0.929640896f, 0.368466830f, + 0.929074581f, 0.369892447f, + 0.928506080f, 0.371317194f, + 0.927935395f, 0.372741067f, + 0.927362526f, 0.374164063f, + 0.926787474f, 0.375586178f, + 0.926210242f, 0.377007410f, + 0.925630831f, 0.378427755f, + 0.925049241f, 0.379847209f, + 0.924465474f, 0.381265769f, + 0.923879533f, 0.382683432f, + 0.923291417f, 0.384100195f, + 0.922701128f, 0.385516054f, + 0.922108669f, 0.386931006f, + 0.921514039f, 0.388345047f, + 0.920917242f, 0.389758174f, + 0.920318277f, 0.391170384f, + 0.919717146f, 0.392581674f, + 0.919113852f, 0.393992040f, + 0.918508394f, 0.395401479f, + 0.917900776f, 0.396809987f, + 0.917290997f, 0.398217562f, + 0.916679060f, 0.399624200f, + 0.916064966f, 0.401029897f, + 0.915448716f, 0.402434651f, + 0.914830312f, 0.403838458f, + 0.914209756f, 0.405241314f, + 0.913587048f, 0.406643217f, + 0.912962190f, 0.408044163f, + 0.912335185f, 0.409444149f, + 0.911706032f, 0.410843171f, + 0.911074734f, 0.412241227f, + 0.910441292f, 0.413638312f, + 0.909805708f, 0.415034424f, + 0.909167983f, 0.416429560f, + 0.908528119f, 0.417823716f, + 0.907886116f, 0.419216888f, + 0.907241978f, 0.420609074f, + 0.906595705f, 0.422000271f, + 0.905947298f, 0.423390474f, + 0.905296759f, 0.424779681f, + 0.904644091f, 0.426167889f, + 0.903989293f, 0.427555093f, + 0.903332368f, 0.428941292f, + 0.902673318f, 0.430326481f, + 0.902012144f, 0.431710658f, + 0.901348847f, 0.433093819f, + 0.900683429f, 0.434475961f, + 0.900015892f, 0.435857080f, + 0.899346237f, 0.437237174f, + 0.898674466f, 0.438616239f, + 0.898000580f, 0.439994271f, + 0.897324581f, 0.441371269f, + 0.896646470f, 0.442747228f, + 0.895966250f, 0.444122145f, + 0.895283921f, 0.445496017f, + 0.894599486f, 0.446868840f, + 0.893912945f, 0.448240612f, + 0.893224301f, 0.449611330f, + 0.892533555f, 0.450980989f, + 0.891840709f, 0.452349587f, + 0.891145765f, 0.453717121f, + 0.890448723f, 0.455083587f, + 0.889749586f, 0.456448982f, + 0.889048356f, 0.457813304f, + 0.888345033f, 0.459176548f, + 0.887639620f, 0.460538711f, + 0.886932119f, 0.461899791f, + 0.886222530f, 0.463259784f, + 0.885510856f, 0.464618686f, + 0.884797098f, 0.465976496f, + 0.884081259f, 0.467333209f, + 0.883363339f, 0.468688822f, + 0.882643340f, 0.470043332f, + 0.881921264f, 0.471396737f, + 0.881197113f, 0.472749032f, + 0.880470889f, 0.474100215f, + 0.879742593f, 0.475450282f, + 0.879012226f, 0.476799230f, + 0.878279792f, 0.478147056f, + 0.877545290f, 0.479493758f, + 0.876808724f, 0.480839331f, + 0.876070094f, 0.482183772f, + 0.875329403f, 0.483527079f, + 0.874586652f, 0.484869248f, + 0.873841843f, 0.486210276f, + 0.873094978f, 0.487550160f, + 0.872346059f, 0.488888897f, + 0.871595087f, 0.490226483f, + 0.870842063f, 0.491562916f, + 0.870086991f, 0.492898192f, + 0.869329871f, 0.494232309f, + 0.868570706f, 0.495565262f, + 0.867809497f, 0.496897049f, + 0.867046246f, 0.498227667f, + 0.866280954f, 0.499557113f, + 0.865513624f, 0.500885383f, + 0.864744258f, 0.502212474f, + 0.863972856f, 0.503538384f, + 0.863199422f, 0.504863109f, + 0.862423956f, 0.506186645f, + 0.861646461f, 0.507508991f, + 0.860866939f, 0.508830143f, + 0.860085390f, 0.510150097f, + 0.859301818f, 0.511468850f, + 0.858516224f, 0.512786401f, + 0.857728610f, 0.514102744f, + 0.856938977f, 0.515417878f, + 0.856147328f, 0.516731799f, + 0.855353665f, 0.518044504f, + 0.854557988f, 0.519355990f, + 0.853760301f, 0.520666254f, + 0.852960605f, 0.521975293f, + 0.852158902f, 0.523283103f, + 0.851355193f, 0.524589683f, + 0.850549481f, 0.525895027f, + 0.849741768f, 0.527199135f, + 0.848932055f, 0.528502002f, + 0.848120345f, 0.529803625f, + 0.847306639f, 0.531104001f, + 0.846490939f, 0.532403128f, + 0.845673247f, 0.533701002f, + 0.844853565f, 0.534997620f, + 0.844031895f, 0.536292979f, + 0.843208240f, 0.537587076f, + 0.842382600f, 0.538879909f, + 0.841554977f, 0.540171473f, + 0.840725375f, 0.541461766f, + 0.839893794f, 0.542750785f, + 0.839060237f, 0.544038527f, + 0.838224706f, 0.545324988f, + 0.837387202f, 0.546610167f, + 0.836547727f, 0.547894059f, + 0.835706284f, 0.549176662f, + 0.834862875f, 0.550457973f, + 0.834017501f, 0.551737988f, + 0.833170165f, 0.553016706f, + 0.832320868f, 0.554294121f, + 0.831469612f, 0.555570233f, + 0.830616400f, 0.556845037f, + 0.829761234f, 0.558118531f, + 0.828904115f, 0.559390712f, + 0.828045045f, 0.560661576f, + 0.827184027f, 0.561931121f, + 0.826321063f, 0.563199344f, + 0.825456154f, 0.564466242f, + 0.824589303f, 0.565731811f, + 0.823720511f, 0.566996049f, + 0.822849781f, 0.568258953f, + 0.821977115f, 0.569520519f, + 0.821102515f, 0.570780746f, + 0.820225983f, 0.572039629f, + 0.819347520f, 0.573297167f, + 0.818467130f, 0.574553355f, + 0.817584813f, 0.575808191f, + 0.816700573f, 0.577061673f, + 0.815814411f, 0.578313796f, + 0.814926329f, 0.579564559f, + 0.814036330f, 0.580813958f, + 0.813144415f, 0.582061990f, + 0.812250587f, 0.583308653f, + 0.811354847f, 0.584553943f, + 0.810457198f, 0.585797857f, + 0.809557642f, 0.587040394f, + 0.808656182f, 0.588281548f, + 0.807752818f, 0.589521319f, + 0.806847554f, 0.590759702f, + 0.805940391f, 0.591996695f, + 0.805031331f, 0.593232295f, + 0.804120377f, 0.594466499f, + 0.803207531f, 0.595699304f, + 0.802292796f, 0.596930708f, + 0.801376172f, 0.598160707f, + 0.800457662f, 0.599389298f, + 0.799537269f, 0.600616479f, + 0.798614995f, 0.601842247f, + 0.797690841f, 0.603066599f, + 0.796764810f, 0.604289531f, + 0.795836905f, 0.605511041f, + 0.794907126f, 0.606731127f, + 0.793975478f, 0.607949785f, + 0.793041960f, 0.609167012f, + 0.792106577f, 0.610382806f, + 0.791169330f, 0.611597164f, + 0.790230221f, 0.612810082f, + 0.789289253f, 0.614021559f, + 0.788346428f, 0.615231591f, + 0.787401747f, 0.616440175f, + 0.786455214f, 0.617647308f, + 0.785506830f, 0.618852988f, + 0.784556597f, 0.620057212f, + 0.783604519f, 0.621259977f, + 0.782650596f, 0.622461279f, + 0.781694832f, 0.623661118f, + 0.780737229f, 0.624859488f, + 0.779777788f, 0.626056388f, + 0.778816512f, 0.627251815f, + 0.777853404f, 0.628445767f, + 0.776888466f, 0.629638239f, + 0.775921699f, 0.630829230f, + 0.774953107f, 0.632018736f, + 0.773982691f, 0.633206755f, + 0.773010453f, 0.634393284f, + 0.772036397f, 0.635578320f, + 0.771060524f, 0.636761861f, + 0.770082837f, 0.637943904f, + 0.769103338f, 0.639124445f, + 0.768122029f, 0.640303482f, + 0.767138912f, 0.641481013f, + 0.766153990f, 0.642657034f, + 0.765167266f, 0.643831543f, + 0.764178741f, 0.645004537f, + 0.763188417f, 0.646176013f, + 0.762196298f, 0.647345969f, + 0.761202385f, 0.648514401f, + 0.760206682f, 0.649681307f, + 0.759209189f, 0.650846685f, + 0.758209910f, 0.652010531f, + 0.757208847f, 0.653172843f, + 0.756206001f, 0.654333618f, + 0.755201377f, 0.655492853f, + 0.754194975f, 0.656650546f, + 0.753186799f, 0.657806693f, + 0.752176850f, 0.658961293f, + 0.751165132f, 0.660114342f, + 0.750151646f, 0.661265838f, + 0.749136395f, 0.662415778f, + 0.748119380f, 0.663564159f, + 0.747100606f, 0.664710978f, + 0.746080074f, 0.665856234f, + 0.745057785f, 0.666999922f, + 0.744033744f, 0.668142041f, + 0.743007952f, 0.669282588f, + 0.741980412f, 0.670421560f, + 0.740951125f, 0.671558955f, + 0.739920095f, 0.672694769f, + 0.738887324f, 0.673829000f, + 0.737852815f, 0.674961646f, + 0.736816569f, 0.676092704f, + 0.735778589f, 0.677222170f, + 0.734738878f, 0.678350043f, + 0.733697438f, 0.679476320f, + 0.732654272f, 0.680600998f, + 0.731609381f, 0.681724074f, + 0.730562769f, 0.682845546f, + 0.729514438f, 0.683965412f, + 0.728464390f, 0.685083668f, + 0.727412629f, 0.686200312f, + 0.726359155f, 0.687315341f, + 0.725303972f, 0.688428753f, + 0.724247083f, 0.689540545f, + 0.723188489f, 0.690650714f, + 0.722128194f, 0.691759258f, + 0.721066199f, 0.692866175f, + 0.720002508f, 0.693971461f, + 0.718937122f, 0.695075114f, + 0.717870045f, 0.696177131f, + 0.716801279f, 0.697277511f, + 0.715730825f, 0.698376249f, + 0.714658688f, 0.699473345f, + 0.713584869f, 0.700568794f, + 0.712509371f, 0.701662595f, + 0.711432196f, 0.702754744f, + 0.710353347f, 0.703845241f, + 0.709272826f, 0.704934080f, + 0.708190637f, 0.706021261f, + 0.707106781f, 0.707106781f, + 0.706021261f, 0.708190637f, + 0.704934080f, 0.709272826f, + 0.703845241f, 0.710353347f, + 0.702754744f, 0.711432196f, + 0.701662595f, 0.712509371f, + 0.700568794f, 0.713584869f, + 0.699473345f, 0.714658688f, + 0.698376249f, 0.715730825f, + 0.697277511f, 0.716801279f, + 0.696177131f, 0.717870045f, + 0.695075114f, 0.718937122f, + 0.693971461f, 0.720002508f, + 0.692866175f, 0.721066199f, + 0.691759258f, 0.722128194f, + 0.690650714f, 0.723188489f, + 0.689540545f, 0.724247083f, + 0.688428753f, 0.725303972f, + 0.687315341f, 0.726359155f, + 0.686200312f, 0.727412629f, + 0.685083668f, 0.728464390f, + 0.683965412f, 0.729514438f, + 0.682845546f, 0.730562769f, + 0.681724074f, 0.731609381f, + 0.680600998f, 0.732654272f, + 0.679476320f, 0.733697438f, + 0.678350043f, 0.734738878f, + 0.677222170f, 0.735778589f, + 0.676092704f, 0.736816569f, + 0.674961646f, 0.737852815f, + 0.673829000f, 0.738887324f, + 0.672694769f, 0.739920095f, + 0.671558955f, 0.740951125f, + 0.670421560f, 0.741980412f, + 0.669282588f, 0.743007952f, + 0.668142041f, 0.744033744f, + 0.666999922f, 0.745057785f, + 0.665856234f, 0.746080074f, + 0.664710978f, 0.747100606f, + 0.663564159f, 0.748119380f, + 0.662415778f, 0.749136395f, + 0.661265838f, 0.750151646f, + 0.660114342f, 0.751165132f, + 0.658961293f, 0.752176850f, + 0.657806693f, 0.753186799f, + 0.656650546f, 0.754194975f, + 0.655492853f, 0.755201377f, + 0.654333618f, 0.756206001f, + 0.653172843f, 0.757208847f, + 0.652010531f, 0.758209910f, + 0.650846685f, 0.759209189f, + 0.649681307f, 0.760206682f, + 0.648514401f, 0.761202385f, + 0.647345969f, 0.762196298f, + 0.646176013f, 0.763188417f, + 0.645004537f, 0.764178741f, + 0.643831543f, 0.765167266f, + 0.642657034f, 0.766153990f, + 0.641481013f, 0.767138912f, + 0.640303482f, 0.768122029f, + 0.639124445f, 0.769103338f, + 0.637943904f, 0.770082837f, + 0.636761861f, 0.771060524f, + 0.635578320f, 0.772036397f, + 0.634393284f, 0.773010453f, + 0.633206755f, 0.773982691f, + 0.632018736f, 0.774953107f, + 0.630829230f, 0.775921699f, + 0.629638239f, 0.776888466f, + 0.628445767f, 0.777853404f, + 0.627251815f, 0.778816512f, + 0.626056388f, 0.779777788f, + 0.624859488f, 0.780737229f, + 0.623661118f, 0.781694832f, + 0.622461279f, 0.782650596f, + 0.621259977f, 0.783604519f, + 0.620057212f, 0.784556597f, + 0.618852988f, 0.785506830f, + 0.617647308f, 0.786455214f, + 0.616440175f, 0.787401747f, + 0.615231591f, 0.788346428f, + 0.614021559f, 0.789289253f, + 0.612810082f, 0.790230221f, + 0.611597164f, 0.791169330f, + 0.610382806f, 0.792106577f, + 0.609167012f, 0.793041960f, + 0.607949785f, 0.793975478f, + 0.606731127f, 0.794907126f, + 0.605511041f, 0.795836905f, + 0.604289531f, 0.796764810f, + 0.603066599f, 0.797690841f, + 0.601842247f, 0.798614995f, + 0.600616479f, 0.799537269f, + 0.599389298f, 0.800457662f, + 0.598160707f, 0.801376172f, + 0.596930708f, 0.802292796f, + 0.595699304f, 0.803207531f, + 0.594466499f, 0.804120377f, + 0.593232295f, 0.805031331f, + 0.591996695f, 0.805940391f, + 0.590759702f, 0.806847554f, + 0.589521319f, 0.807752818f, + 0.588281548f, 0.808656182f, + 0.587040394f, 0.809557642f, + 0.585797857f, 0.810457198f, + 0.584553943f, 0.811354847f, + 0.583308653f, 0.812250587f, + 0.582061990f, 0.813144415f, + 0.580813958f, 0.814036330f, + 0.579564559f, 0.814926329f, + 0.578313796f, 0.815814411f, + 0.577061673f, 0.816700573f, + 0.575808191f, 0.817584813f, + 0.574553355f, 0.818467130f, + 0.573297167f, 0.819347520f, + 0.572039629f, 0.820225983f, + 0.570780746f, 0.821102515f, + 0.569520519f, 0.821977115f, + 0.568258953f, 0.822849781f, + 0.566996049f, 0.823720511f, + 0.565731811f, 0.824589303f, + 0.564466242f, 0.825456154f, + 0.563199344f, 0.826321063f, + 0.561931121f, 0.827184027f, + 0.560661576f, 0.828045045f, + 0.559390712f, 0.828904115f, + 0.558118531f, 0.829761234f, + 0.556845037f, 0.830616400f, + 0.555570233f, 0.831469612f, + 0.554294121f, 0.832320868f, + 0.553016706f, 0.833170165f, + 0.551737988f, 0.834017501f, + 0.550457973f, 0.834862875f, + 0.549176662f, 0.835706284f, + 0.547894059f, 0.836547727f, + 0.546610167f, 0.837387202f, + 0.545324988f, 0.838224706f, + 0.544038527f, 0.839060237f, + 0.542750785f, 0.839893794f, + 0.541461766f, 0.840725375f, + 0.540171473f, 0.841554977f, + 0.538879909f, 0.842382600f, + 0.537587076f, 0.843208240f, + 0.536292979f, 0.844031895f, + 0.534997620f, 0.844853565f, + 0.533701002f, 0.845673247f, + 0.532403128f, 0.846490939f, + 0.531104001f, 0.847306639f, + 0.529803625f, 0.848120345f, + 0.528502002f, 0.848932055f, + 0.527199135f, 0.849741768f, + 0.525895027f, 0.850549481f, + 0.524589683f, 0.851355193f, + 0.523283103f, 0.852158902f, + 0.521975293f, 0.852960605f, + 0.520666254f, 0.853760301f, + 0.519355990f, 0.854557988f, + 0.518044504f, 0.855353665f, + 0.516731799f, 0.856147328f, + 0.515417878f, 0.856938977f, + 0.514102744f, 0.857728610f, + 0.512786401f, 0.858516224f, + 0.511468850f, 0.859301818f, + 0.510150097f, 0.860085390f, + 0.508830143f, 0.860866939f, + 0.507508991f, 0.861646461f, + 0.506186645f, 0.862423956f, + 0.504863109f, 0.863199422f, + 0.503538384f, 0.863972856f, + 0.502212474f, 0.864744258f, + 0.500885383f, 0.865513624f, + 0.499557113f, 0.866280954f, + 0.498227667f, 0.867046246f, + 0.496897049f, 0.867809497f, + 0.495565262f, 0.868570706f, + 0.494232309f, 0.869329871f, + 0.492898192f, 0.870086991f, + 0.491562916f, 0.870842063f, + 0.490226483f, 0.871595087f, + 0.488888897f, 0.872346059f, + 0.487550160f, 0.873094978f, + 0.486210276f, 0.873841843f, + 0.484869248f, 0.874586652f, + 0.483527079f, 0.875329403f, + 0.482183772f, 0.876070094f, + 0.480839331f, 0.876808724f, + 0.479493758f, 0.877545290f, + 0.478147056f, 0.878279792f, + 0.476799230f, 0.879012226f, + 0.475450282f, 0.879742593f, + 0.474100215f, 0.880470889f, + 0.472749032f, 0.881197113f, + 0.471396737f, 0.881921264f, + 0.470043332f, 0.882643340f, + 0.468688822f, 0.883363339f, + 0.467333209f, 0.884081259f, + 0.465976496f, 0.884797098f, + 0.464618686f, 0.885510856f, + 0.463259784f, 0.886222530f, + 0.461899791f, 0.886932119f, + 0.460538711f, 0.887639620f, + 0.459176548f, 0.888345033f, + 0.457813304f, 0.889048356f, + 0.456448982f, 0.889749586f, + 0.455083587f, 0.890448723f, + 0.453717121f, 0.891145765f, + 0.452349587f, 0.891840709f, + 0.450980989f, 0.892533555f, + 0.449611330f, 0.893224301f, + 0.448240612f, 0.893912945f, + 0.446868840f, 0.894599486f, + 0.445496017f, 0.895283921f, + 0.444122145f, 0.895966250f, + 0.442747228f, 0.896646470f, + 0.441371269f, 0.897324581f, + 0.439994271f, 0.898000580f, + 0.438616239f, 0.898674466f, + 0.437237174f, 0.899346237f, + 0.435857080f, 0.900015892f, + 0.434475961f, 0.900683429f, + 0.433093819f, 0.901348847f, + 0.431710658f, 0.902012144f, + 0.430326481f, 0.902673318f, + 0.428941292f, 0.903332368f, + 0.427555093f, 0.903989293f, + 0.426167889f, 0.904644091f, + 0.424779681f, 0.905296759f, + 0.423390474f, 0.905947298f, + 0.422000271f, 0.906595705f, + 0.420609074f, 0.907241978f, + 0.419216888f, 0.907886116f, + 0.417823716f, 0.908528119f, + 0.416429560f, 0.909167983f, + 0.415034424f, 0.909805708f, + 0.413638312f, 0.910441292f, + 0.412241227f, 0.911074734f, + 0.410843171f, 0.911706032f, + 0.409444149f, 0.912335185f, + 0.408044163f, 0.912962190f, + 0.406643217f, 0.913587048f, + 0.405241314f, 0.914209756f, + 0.403838458f, 0.914830312f, + 0.402434651f, 0.915448716f, + 0.401029897f, 0.916064966f, + 0.399624200f, 0.916679060f, + 0.398217562f, 0.917290997f, + 0.396809987f, 0.917900776f, + 0.395401479f, 0.918508394f, + 0.393992040f, 0.919113852f, + 0.392581674f, 0.919717146f, + 0.391170384f, 0.920318277f, + 0.389758174f, 0.920917242f, + 0.388345047f, 0.921514039f, + 0.386931006f, 0.922108669f, + 0.385516054f, 0.922701128f, + 0.384100195f, 0.923291417f, + 0.382683432f, 0.923879533f, + 0.381265769f, 0.924465474f, + 0.379847209f, 0.925049241f, + 0.378427755f, 0.925630831f, + 0.377007410f, 0.926210242f, + 0.375586178f, 0.926787474f, + 0.374164063f, 0.927362526f, + 0.372741067f, 0.927935395f, + 0.371317194f, 0.928506080f, + 0.369892447f, 0.929074581f, + 0.368466830f, 0.929640896f, + 0.367040346f, 0.930205023f, + 0.365612998f, 0.930766961f, + 0.364184790f, 0.931326709f, + 0.362755724f, 0.931884266f, + 0.361325806f, 0.932439629f, + 0.359895037f, 0.932992799f, + 0.358463421f, 0.933543773f, + 0.357030961f, 0.934092550f, + 0.355597662f, 0.934639130f, + 0.354163525f, 0.935183510f, + 0.352728556f, 0.935725689f, + 0.351292756f, 0.936265667f, + 0.349856130f, 0.936803442f, + 0.348418680f, 0.937339012f, + 0.346980411f, 0.937872376f, + 0.345541325f, 0.938403534f, + 0.344101426f, 0.938932484f, + 0.342660717f, 0.939459224f, + 0.341219202f, 0.939983753f, + 0.339776884f, 0.940506071f, + 0.338333767f, 0.941026175f, + 0.336889853f, 0.941544065f, + 0.335445147f, 0.942059740f, + 0.333999651f, 0.942573198f, + 0.332553370f, 0.943084437f, + 0.331106306f, 0.943593458f, + 0.329658463f, 0.944100258f, + 0.328209844f, 0.944604837f, + 0.326760452f, 0.945107193f, + 0.325310292f, 0.945607325f, + 0.323859367f, 0.946105232f, + 0.322407679f, 0.946600913f, + 0.320955232f, 0.947094366f, + 0.319502031f, 0.947585591f, + 0.318048077f, 0.948074586f, + 0.316593376f, 0.948561350f, + 0.315137929f, 0.949045882f, + 0.313681740f, 0.949528181f, + 0.312224814f, 0.950008245f, + 0.310767153f, 0.950486074f, + 0.309308760f, 0.950961666f, + 0.307849640f, 0.951435021f, + 0.306389795f, 0.951906137f, + 0.304929230f, 0.952375013f, + 0.303467947f, 0.952841648f, + 0.302005949f, 0.953306040f, + 0.300543241f, 0.953768190f, + 0.299079826f, 0.954228095f, + 0.297615707f, 0.954685755f, + 0.296150888f, 0.955141168f, + 0.294685372f, 0.955594334f, + 0.293219163f, 0.956045251f, + 0.291752263f, 0.956493919f, + 0.290284677f, 0.956940336f, + 0.288816408f, 0.957384501f, + 0.287347460f, 0.957826413f, + 0.285877835f, 0.958266071f, + 0.284407537f, 0.958703475f, + 0.282936570f, 0.959138622f, + 0.281464938f, 0.959571513f, + 0.279992643f, 0.960002146f, + 0.278519689f, 0.960430519f, + 0.277046080f, 0.960856633f, + 0.275571819f, 0.961280486f, + 0.274096910f, 0.961702077f, + 0.272621355f, 0.962121404f, + 0.271145160f, 0.962538468f, + 0.269668326f, 0.962953267f, + 0.268190857f, 0.963365800f, + 0.266712757f, 0.963776066f, + 0.265234030f, 0.964184064f, + 0.263754679f, 0.964589793f, + 0.262274707f, 0.964993253f, + 0.260794118f, 0.965394442f, + 0.259312915f, 0.965793359f, + 0.257831102f, 0.966190003f, + 0.256348682f, 0.966584374f, + 0.254865660f, 0.966976471f, + 0.253382037f, 0.967366292f, + 0.251897818f, 0.967753837f, + 0.250413007f, 0.968139105f, + 0.248927606f, 0.968522094f, + 0.247441619f, 0.968902805f, + 0.245955050f, 0.969281235f, + 0.244467903f, 0.969657385f, + 0.242980180f, 0.970031253f, + 0.241491885f, 0.970402839f, + 0.240003022f, 0.970772141f, + 0.238513595f, 0.971139158f, + 0.237023606f, 0.971503891f, + 0.235533059f, 0.971866337f, + 0.234041959f, 0.972226497f, + 0.232550307f, 0.972584369f, + 0.231058108f, 0.972939952f, + 0.229565366f, 0.973293246f, + 0.228072083f, 0.973644250f, + 0.226578264f, 0.973992962f, + 0.225083911f, 0.974339383f, + 0.223589029f, 0.974683511f, + 0.222093621f, 0.975025345f, + 0.220597690f, 0.975364885f, + 0.219101240f, 0.975702130f, + 0.217604275f, 0.976037079f, + 0.216106797f, 0.976369731f, + 0.214608811f, 0.976700086f, + 0.213110320f, 0.977028143f, + 0.211611327f, 0.977353900f, + 0.210111837f, 0.977677358f, + 0.208611852f, 0.977998515f, + 0.207111376f, 0.978317371f, + 0.205610413f, 0.978633924f, + 0.204108966f, 0.978948175f, + 0.202607039f, 0.979260123f, + 0.201104635f, 0.979569766f, + 0.199601758f, 0.979877104f, + 0.198098411f, 0.980182136f, + 0.196594598f, 0.980484862f, + 0.195090322f, 0.980785280f, + 0.193585587f, 0.981083391f, + 0.192080397f, 0.981379193f, + 0.190574755f, 0.981672686f, + 0.189068664f, 0.981963869f, + 0.187562129f, 0.982252741f, + 0.186055152f, 0.982539302f, + 0.184547737f, 0.982823551f, + 0.183039888f, 0.983105487f, + 0.181531608f, 0.983385110f, + 0.180022901f, 0.983662419f, + 0.178513771f, 0.983937413f, + 0.177004220f, 0.984210092f, + 0.175494253f, 0.984480455f, + 0.173983873f, 0.984748502f, + 0.172473084f, 0.985014231f, + 0.170961889f, 0.985277642f, + 0.169450291f, 0.985538735f, + 0.167938295f, 0.985797509f, + 0.166425904f, 0.986053963f, + 0.164913120f, 0.986308097f, + 0.163399949f, 0.986559910f, + 0.161886394f, 0.986809402f, + 0.160372457f, 0.987056571f, + 0.158858143f, 0.987301418f, + 0.157343456f, 0.987543942f, + 0.155828398f, 0.987784142f, + 0.154312973f, 0.988022017f, + 0.152797185f, 0.988257568f, + 0.151281038f, 0.988490793f, + 0.149764535f, 0.988721692f, + 0.148247679f, 0.988950265f, + 0.146730474f, 0.989176510f, + 0.145212925f, 0.989400428f, + 0.143695033f, 0.989622017f, + 0.142176804f, 0.989841278f, + 0.140658239f, 0.990058210f, + 0.139139344f, 0.990272812f, + 0.137620122f, 0.990485084f, + 0.136100575f, 0.990695025f, + 0.134580709f, 0.990902635f, + 0.133060525f, 0.991107914f, + 0.131540029f, 0.991310860f, + 0.130019223f, 0.991511473f, + 0.128498111f, 0.991709754f, + 0.126976696f, 0.991905700f, + 0.125454983f, 0.992099313f, + 0.123932975f, 0.992290591f, + 0.122410675f, 0.992479535f, + 0.120888087f, 0.992666142f, + 0.119365215f, 0.992850414f, + 0.117842062f, 0.993032350f, + 0.116318631f, 0.993211949f, + 0.114794927f, 0.993389211f, + 0.113270952f, 0.993564136f, + 0.111746711f, 0.993736722f, + 0.110222207f, 0.993906970f, + 0.108697444f, 0.994074879f, + 0.107172425f, 0.994240449f, + 0.105647154f, 0.994403680f, + 0.104121634f, 0.994564571f, + 0.102595869f, 0.994723121f, + 0.101069863f, 0.994879331f, + 0.099543619f, 0.995033199f, + 0.098017140f, 0.995184727f, + 0.096490431f, 0.995333912f, + 0.094963495f, 0.995480755f, + 0.093436336f, 0.995625256f, + 0.091908956f, 0.995767414f, + 0.090381361f, 0.995907229f, + 0.088853553f, 0.996044701f, + 0.087325535f, 0.996179829f, + 0.085797312f, 0.996312612f, + 0.084268888f, 0.996443051f, + 0.082740265f, 0.996571146f, + 0.081211447f, 0.996696895f, + 0.079682438f, 0.996820299f, + 0.078153242f, 0.996941358f, + 0.076623861f, 0.997060070f, + 0.075094301f, 0.997176437f, + 0.073564564f, 0.997290457f, + 0.072034653f, 0.997402130f, + 0.070504573f, 0.997511456f, + 0.068974328f, 0.997618435f, + 0.067443920f, 0.997723067f, + 0.065913353f, 0.997825350f, + 0.064382631f, 0.997925286f, + 0.062851758f, 0.998022874f, + 0.061320736f, 0.998118113f, + 0.059789571f, 0.998211003f, + 0.058258265f, 0.998301545f, + 0.056726821f, 0.998389737f, + 0.055195244f, 0.998475581f, + 0.053663538f, 0.998559074f, + 0.052131705f, 0.998640218f, + 0.050599749f, 0.998719012f, + 0.049067674f, 0.998795456f, + 0.047535484f, 0.998869550f, + 0.046003182f, 0.998941293f, + 0.044470772f, 0.999010686f, + 0.042938257f, 0.999077728f, + 0.041405641f, 0.999142419f, + 0.039872928f, 0.999204759f, + 0.038340120f, 0.999264747f, + 0.036807223f, 0.999322385f, + 0.035274239f, 0.999377670f, + 0.033741172f, 0.999430605f, + 0.032208025f, 0.999481187f, + 0.030674803f, 0.999529418f, + 0.029141509f, 0.999575296f, + 0.027608146f, 0.999618822f, + 0.026074718f, 0.999659997f, + 0.024541229f, 0.999698819f, + 0.023007681f, 0.999735288f, + 0.021474080f, 0.999769405f, + 0.019940429f, 0.999801170f, + 0.018406730f, 0.999830582f, + 0.016872988f, 0.999857641f, + 0.015339206f, 0.999882347f, + 0.013805389f, 0.999904701f, + 0.012271538f, 0.999924702f, + 0.010737659f, 0.999942350f, + 0.009203755f, 0.999957645f, + 0.007669829f, 0.999970586f, + 0.006135885f, 0.999981175f, + 0.004601926f, 0.999989411f, + 0.003067957f, 0.999995294f, + 0.001533980f, 0.999998823f, + 0.000000000f, 1.000000000f, + -0.001533980f, 0.999998823f, + -0.003067957f, 0.999995294f, + -0.004601926f, 0.999989411f, + -0.006135885f, 0.999981175f, + -0.007669829f, 0.999970586f, + -0.009203755f, 0.999957645f, + -0.010737659f, 0.999942350f, + -0.012271538f, 0.999924702f, + -0.013805389f, 0.999904701f, + -0.015339206f, 0.999882347f, + -0.016872988f, 0.999857641f, + -0.018406730f, 0.999830582f, + -0.019940429f, 0.999801170f, + -0.021474080f, 0.999769405f, + -0.023007681f, 0.999735288f, + -0.024541229f, 0.999698819f, + -0.026074718f, 0.999659997f, + -0.027608146f, 0.999618822f, + -0.029141509f, 0.999575296f, + -0.030674803f, 0.999529418f, + -0.032208025f, 0.999481187f, + -0.033741172f, 0.999430605f, + -0.035274239f, 0.999377670f, + -0.036807223f, 0.999322385f, + -0.038340120f, 0.999264747f, + -0.039872928f, 0.999204759f, + -0.041405641f, 0.999142419f, + -0.042938257f, 0.999077728f, + -0.044470772f, 0.999010686f, + -0.046003182f, 0.998941293f, + -0.047535484f, 0.998869550f, + -0.049067674f, 0.998795456f, + -0.050599749f, 0.998719012f, + -0.052131705f, 0.998640218f, + -0.053663538f, 0.998559074f, + -0.055195244f, 0.998475581f, + -0.056726821f, 0.998389737f, + -0.058258265f, 0.998301545f, + -0.059789571f, 0.998211003f, + -0.061320736f, 0.998118113f, + -0.062851758f, 0.998022874f, + -0.064382631f, 0.997925286f, + -0.065913353f, 0.997825350f, + -0.067443920f, 0.997723067f, + -0.068974328f, 0.997618435f, + -0.070504573f, 0.997511456f, + -0.072034653f, 0.997402130f, + -0.073564564f, 0.997290457f, + -0.075094301f, 0.997176437f, + -0.076623861f, 0.997060070f, + -0.078153242f, 0.996941358f, + -0.079682438f, 0.996820299f, + -0.081211447f, 0.996696895f, + -0.082740265f, 0.996571146f, + -0.084268888f, 0.996443051f, + -0.085797312f, 0.996312612f, + -0.087325535f, 0.996179829f, + -0.088853553f, 0.996044701f, + -0.090381361f, 0.995907229f, + -0.091908956f, 0.995767414f, + -0.093436336f, 0.995625256f, + -0.094963495f, 0.995480755f, + -0.096490431f, 0.995333912f, + -0.098017140f, 0.995184727f, + -0.099543619f, 0.995033199f, + -0.101069863f, 0.994879331f, + -0.102595869f, 0.994723121f, + -0.104121634f, 0.994564571f, + -0.105647154f, 0.994403680f, + -0.107172425f, 0.994240449f, + -0.108697444f, 0.994074879f, + -0.110222207f, 0.993906970f, + -0.111746711f, 0.993736722f, + -0.113270952f, 0.993564136f, + -0.114794927f, 0.993389211f, + -0.116318631f, 0.993211949f, + -0.117842062f, 0.993032350f, + -0.119365215f, 0.992850414f, + -0.120888087f, 0.992666142f, + -0.122410675f, 0.992479535f, + -0.123932975f, 0.992290591f, + -0.125454983f, 0.992099313f, + -0.126976696f, 0.991905700f, + -0.128498111f, 0.991709754f, + -0.130019223f, 0.991511473f, + -0.131540029f, 0.991310860f, + -0.133060525f, 0.991107914f, + -0.134580709f, 0.990902635f, + -0.136100575f, 0.990695025f, + -0.137620122f, 0.990485084f, + -0.139139344f, 0.990272812f, + -0.140658239f, 0.990058210f, + -0.142176804f, 0.989841278f, + -0.143695033f, 0.989622017f, + -0.145212925f, 0.989400428f, + -0.146730474f, 0.989176510f, + -0.148247679f, 0.988950265f, + -0.149764535f, 0.988721692f, + -0.151281038f, 0.988490793f, + -0.152797185f, 0.988257568f, + -0.154312973f, 0.988022017f, + -0.155828398f, 0.987784142f, + -0.157343456f, 0.987543942f, + -0.158858143f, 0.987301418f, + -0.160372457f, 0.987056571f, + -0.161886394f, 0.986809402f, + -0.163399949f, 0.986559910f, + -0.164913120f, 0.986308097f, + -0.166425904f, 0.986053963f, + -0.167938295f, 0.985797509f, + -0.169450291f, 0.985538735f, + -0.170961889f, 0.985277642f, + -0.172473084f, 0.985014231f, + -0.173983873f, 0.984748502f, + -0.175494253f, 0.984480455f, + -0.177004220f, 0.984210092f, + -0.178513771f, 0.983937413f, + -0.180022901f, 0.983662419f, + -0.181531608f, 0.983385110f, + -0.183039888f, 0.983105487f, + -0.184547737f, 0.982823551f, + -0.186055152f, 0.982539302f, + -0.187562129f, 0.982252741f, + -0.189068664f, 0.981963869f, + -0.190574755f, 0.981672686f, + -0.192080397f, 0.981379193f, + -0.193585587f, 0.981083391f, + -0.195090322f, 0.980785280f, + -0.196594598f, 0.980484862f, + -0.198098411f, 0.980182136f, + -0.199601758f, 0.979877104f, + -0.201104635f, 0.979569766f, + -0.202607039f, 0.979260123f, + -0.204108966f, 0.978948175f, + -0.205610413f, 0.978633924f, + -0.207111376f, 0.978317371f, + -0.208611852f, 0.977998515f, + -0.210111837f, 0.977677358f, + -0.211611327f, 0.977353900f, + -0.213110320f, 0.977028143f, + -0.214608811f, 0.976700086f, + -0.216106797f, 0.976369731f, + -0.217604275f, 0.976037079f, + -0.219101240f, 0.975702130f, + -0.220597690f, 0.975364885f, + -0.222093621f, 0.975025345f, + -0.223589029f, 0.974683511f, + -0.225083911f, 0.974339383f, + -0.226578264f, 0.973992962f, + -0.228072083f, 0.973644250f, + -0.229565366f, 0.973293246f, + -0.231058108f, 0.972939952f, + -0.232550307f, 0.972584369f, + -0.234041959f, 0.972226497f, + -0.235533059f, 0.971866337f, + -0.237023606f, 0.971503891f, + -0.238513595f, 0.971139158f, + -0.240003022f, 0.970772141f, + -0.241491885f, 0.970402839f, + -0.242980180f, 0.970031253f, + -0.244467903f, 0.969657385f, + -0.245955050f, 0.969281235f, + -0.247441619f, 0.968902805f, + -0.248927606f, 0.968522094f, + -0.250413007f, 0.968139105f, + -0.251897818f, 0.967753837f, + -0.253382037f, 0.967366292f, + -0.254865660f, 0.966976471f, + -0.256348682f, 0.966584374f, + -0.257831102f, 0.966190003f, + -0.259312915f, 0.965793359f, + -0.260794118f, 0.965394442f, + -0.262274707f, 0.964993253f, + -0.263754679f, 0.964589793f, + -0.265234030f, 0.964184064f, + -0.266712757f, 0.963776066f, + -0.268190857f, 0.963365800f, + -0.269668326f, 0.962953267f, + -0.271145160f, 0.962538468f, + -0.272621355f, 0.962121404f, + -0.274096910f, 0.961702077f, + -0.275571819f, 0.961280486f, + -0.277046080f, 0.960856633f, + -0.278519689f, 0.960430519f, + -0.279992643f, 0.960002146f, + -0.281464938f, 0.959571513f, + -0.282936570f, 0.959138622f, + -0.284407537f, 0.958703475f, + -0.285877835f, 0.958266071f, + -0.287347460f, 0.957826413f, + -0.288816408f, 0.957384501f, + -0.290284677f, 0.956940336f, + -0.291752263f, 0.956493919f, + -0.293219163f, 0.956045251f, + -0.294685372f, 0.955594334f, + -0.296150888f, 0.955141168f, + -0.297615707f, 0.954685755f, + -0.299079826f, 0.954228095f, + -0.300543241f, 0.953768190f, + -0.302005949f, 0.953306040f, + -0.303467947f, 0.952841648f, + -0.304929230f, 0.952375013f, + -0.306389795f, 0.951906137f, + -0.307849640f, 0.951435021f, + -0.309308760f, 0.950961666f, + -0.310767153f, 0.950486074f, + -0.312224814f, 0.950008245f, + -0.313681740f, 0.949528181f, + -0.315137929f, 0.949045882f, + -0.316593376f, 0.948561350f, + -0.318048077f, 0.948074586f, + -0.319502031f, 0.947585591f, + -0.320955232f, 0.947094366f, + -0.322407679f, 0.946600913f, + -0.323859367f, 0.946105232f, + -0.325310292f, 0.945607325f, + -0.326760452f, 0.945107193f, + -0.328209844f, 0.944604837f, + -0.329658463f, 0.944100258f, + -0.331106306f, 0.943593458f, + -0.332553370f, 0.943084437f, + -0.333999651f, 0.942573198f, + -0.335445147f, 0.942059740f, + -0.336889853f, 0.941544065f, + -0.338333767f, 0.941026175f, + -0.339776884f, 0.940506071f, + -0.341219202f, 0.939983753f, + -0.342660717f, 0.939459224f, + -0.344101426f, 0.938932484f, + -0.345541325f, 0.938403534f, + -0.346980411f, 0.937872376f, + -0.348418680f, 0.937339012f, + -0.349856130f, 0.936803442f, + -0.351292756f, 0.936265667f, + -0.352728556f, 0.935725689f, + -0.354163525f, 0.935183510f, + -0.355597662f, 0.934639130f, + -0.357030961f, 0.934092550f, + -0.358463421f, 0.933543773f, + -0.359895037f, 0.932992799f, + -0.361325806f, 0.932439629f, + -0.362755724f, 0.931884266f, + -0.364184790f, 0.931326709f, + -0.365612998f, 0.930766961f, + -0.367040346f, 0.930205023f, + -0.368466830f, 0.929640896f, + -0.369892447f, 0.929074581f, + -0.371317194f, 0.928506080f, + -0.372741067f, 0.927935395f, + -0.374164063f, 0.927362526f, + -0.375586178f, 0.926787474f, + -0.377007410f, 0.926210242f, + -0.378427755f, 0.925630831f, + -0.379847209f, 0.925049241f, + -0.381265769f, 0.924465474f, + -0.382683432f, 0.923879533f, + -0.384100195f, 0.923291417f, + -0.385516054f, 0.922701128f, + -0.386931006f, 0.922108669f, + -0.388345047f, 0.921514039f, + -0.389758174f, 0.920917242f, + -0.391170384f, 0.920318277f, + -0.392581674f, 0.919717146f, + -0.393992040f, 0.919113852f, + -0.395401479f, 0.918508394f, + -0.396809987f, 0.917900776f, + -0.398217562f, 0.917290997f, + -0.399624200f, 0.916679060f, + -0.401029897f, 0.916064966f, + -0.402434651f, 0.915448716f, + -0.403838458f, 0.914830312f, + -0.405241314f, 0.914209756f, + -0.406643217f, 0.913587048f, + -0.408044163f, 0.912962190f, + -0.409444149f, 0.912335185f, + -0.410843171f, 0.911706032f, + -0.412241227f, 0.911074734f, + -0.413638312f, 0.910441292f, + -0.415034424f, 0.909805708f, + -0.416429560f, 0.909167983f, + -0.417823716f, 0.908528119f, + -0.419216888f, 0.907886116f, + -0.420609074f, 0.907241978f, + -0.422000271f, 0.906595705f, + -0.423390474f, 0.905947298f, + -0.424779681f, 0.905296759f, + -0.426167889f, 0.904644091f, + -0.427555093f, 0.903989293f, + -0.428941292f, 0.903332368f, + -0.430326481f, 0.902673318f, + -0.431710658f, 0.902012144f, + -0.433093819f, 0.901348847f, + -0.434475961f, 0.900683429f, + -0.435857080f, 0.900015892f, + -0.437237174f, 0.899346237f, + -0.438616239f, 0.898674466f, + -0.439994271f, 0.898000580f, + -0.441371269f, 0.897324581f, + -0.442747228f, 0.896646470f, + -0.444122145f, 0.895966250f, + -0.445496017f, 0.895283921f, + -0.446868840f, 0.894599486f, + -0.448240612f, 0.893912945f, + -0.449611330f, 0.893224301f, + -0.450980989f, 0.892533555f, + -0.452349587f, 0.891840709f, + -0.453717121f, 0.891145765f, + -0.455083587f, 0.890448723f, + -0.456448982f, 0.889749586f, + -0.457813304f, 0.889048356f, + -0.459176548f, 0.888345033f, + -0.460538711f, 0.887639620f, + -0.461899791f, 0.886932119f, + -0.463259784f, 0.886222530f, + -0.464618686f, 0.885510856f, + -0.465976496f, 0.884797098f, + -0.467333209f, 0.884081259f, + -0.468688822f, 0.883363339f, + -0.470043332f, 0.882643340f, + -0.471396737f, 0.881921264f, + -0.472749032f, 0.881197113f, + -0.474100215f, 0.880470889f, + -0.475450282f, 0.879742593f, + -0.476799230f, 0.879012226f, + -0.478147056f, 0.878279792f, + -0.479493758f, 0.877545290f, + -0.480839331f, 0.876808724f, + -0.482183772f, 0.876070094f, + -0.483527079f, 0.875329403f, + -0.484869248f, 0.874586652f, + -0.486210276f, 0.873841843f, + -0.487550160f, 0.873094978f, + -0.488888897f, 0.872346059f, + -0.490226483f, 0.871595087f, + -0.491562916f, 0.870842063f, + -0.492898192f, 0.870086991f, + -0.494232309f, 0.869329871f, + -0.495565262f, 0.868570706f, + -0.496897049f, 0.867809497f, + -0.498227667f, 0.867046246f, + -0.499557113f, 0.866280954f, + -0.500885383f, 0.865513624f, + -0.502212474f, 0.864744258f, + -0.503538384f, 0.863972856f, + -0.504863109f, 0.863199422f, + -0.506186645f, 0.862423956f, + -0.507508991f, 0.861646461f, + -0.508830143f, 0.860866939f, + -0.510150097f, 0.860085390f, + -0.511468850f, 0.859301818f, + -0.512786401f, 0.858516224f, + -0.514102744f, 0.857728610f, + -0.515417878f, 0.856938977f, + -0.516731799f, 0.856147328f, + -0.518044504f, 0.855353665f, + -0.519355990f, 0.854557988f, + -0.520666254f, 0.853760301f, + -0.521975293f, 0.852960605f, + -0.523283103f, 0.852158902f, + -0.524589683f, 0.851355193f, + -0.525895027f, 0.850549481f, + -0.527199135f, 0.849741768f, + -0.528502002f, 0.848932055f, + -0.529803625f, 0.848120345f, + -0.531104001f, 0.847306639f, + -0.532403128f, 0.846490939f, + -0.533701002f, 0.845673247f, + -0.534997620f, 0.844853565f, + -0.536292979f, 0.844031895f, + -0.537587076f, 0.843208240f, + -0.538879909f, 0.842382600f, + -0.540171473f, 0.841554977f, + -0.541461766f, 0.840725375f, + -0.542750785f, 0.839893794f, + -0.544038527f, 0.839060237f, + -0.545324988f, 0.838224706f, + -0.546610167f, 0.837387202f, + -0.547894059f, 0.836547727f, + -0.549176662f, 0.835706284f, + -0.550457973f, 0.834862875f, + -0.551737988f, 0.834017501f, + -0.553016706f, 0.833170165f, + -0.554294121f, 0.832320868f, + -0.555570233f, 0.831469612f, + -0.556845037f, 0.830616400f, + -0.558118531f, 0.829761234f, + -0.559390712f, 0.828904115f, + -0.560661576f, 0.828045045f, + -0.561931121f, 0.827184027f, + -0.563199344f, 0.826321063f, + -0.564466242f, 0.825456154f, + -0.565731811f, 0.824589303f, + -0.566996049f, 0.823720511f, + -0.568258953f, 0.822849781f, + -0.569520519f, 0.821977115f, + -0.570780746f, 0.821102515f, + -0.572039629f, 0.820225983f, + -0.573297167f, 0.819347520f, + -0.574553355f, 0.818467130f, + -0.575808191f, 0.817584813f, + -0.577061673f, 0.816700573f, + -0.578313796f, 0.815814411f, + -0.579564559f, 0.814926329f, + -0.580813958f, 0.814036330f, + -0.582061990f, 0.813144415f, + -0.583308653f, 0.812250587f, + -0.584553943f, 0.811354847f, + -0.585797857f, 0.810457198f, + -0.587040394f, 0.809557642f, + -0.588281548f, 0.808656182f, + -0.589521319f, 0.807752818f, + -0.590759702f, 0.806847554f, + -0.591996695f, 0.805940391f, + -0.593232295f, 0.805031331f, + -0.594466499f, 0.804120377f, + -0.595699304f, 0.803207531f, + -0.596930708f, 0.802292796f, + -0.598160707f, 0.801376172f, + -0.599389298f, 0.800457662f, + -0.600616479f, 0.799537269f, + -0.601842247f, 0.798614995f, + -0.603066599f, 0.797690841f, + -0.604289531f, 0.796764810f, + -0.605511041f, 0.795836905f, + -0.606731127f, 0.794907126f, + -0.607949785f, 0.793975478f, + -0.609167012f, 0.793041960f, + -0.610382806f, 0.792106577f, + -0.611597164f, 0.791169330f, + -0.612810082f, 0.790230221f, + -0.614021559f, 0.789289253f, + -0.615231591f, 0.788346428f, + -0.616440175f, 0.787401747f, + -0.617647308f, 0.786455214f, + -0.618852988f, 0.785506830f, + -0.620057212f, 0.784556597f, + -0.621259977f, 0.783604519f, + -0.622461279f, 0.782650596f, + -0.623661118f, 0.781694832f, + -0.624859488f, 0.780737229f, + -0.626056388f, 0.779777788f, + -0.627251815f, 0.778816512f, + -0.628445767f, 0.777853404f, + -0.629638239f, 0.776888466f, + -0.630829230f, 0.775921699f, + -0.632018736f, 0.774953107f, + -0.633206755f, 0.773982691f, + -0.634393284f, 0.773010453f, + -0.635578320f, 0.772036397f, + -0.636761861f, 0.771060524f, + -0.637943904f, 0.770082837f, + -0.639124445f, 0.769103338f, + -0.640303482f, 0.768122029f, + -0.641481013f, 0.767138912f, + -0.642657034f, 0.766153990f, + -0.643831543f, 0.765167266f, + -0.645004537f, 0.764178741f, + -0.646176013f, 0.763188417f, + -0.647345969f, 0.762196298f, + -0.648514401f, 0.761202385f, + -0.649681307f, 0.760206682f, + -0.650846685f, 0.759209189f, + -0.652010531f, 0.758209910f, + -0.653172843f, 0.757208847f, + -0.654333618f, 0.756206001f, + -0.655492853f, 0.755201377f, + -0.656650546f, 0.754194975f, + -0.657806693f, 0.753186799f, + -0.658961293f, 0.752176850f, + -0.660114342f, 0.751165132f, + -0.661265838f, 0.750151646f, + -0.662415778f, 0.749136395f, + -0.663564159f, 0.748119380f, + -0.664710978f, 0.747100606f, + -0.665856234f, 0.746080074f, + -0.666999922f, 0.745057785f, + -0.668142041f, 0.744033744f, + -0.669282588f, 0.743007952f, + -0.670421560f, 0.741980412f, + -0.671558955f, 0.740951125f, + -0.672694769f, 0.739920095f, + -0.673829000f, 0.738887324f, + -0.674961646f, 0.737852815f, + -0.676092704f, 0.736816569f, + -0.677222170f, 0.735778589f, + -0.678350043f, 0.734738878f, + -0.679476320f, 0.733697438f, + -0.680600998f, 0.732654272f, + -0.681724074f, 0.731609381f, + -0.682845546f, 0.730562769f, + -0.683965412f, 0.729514438f, + -0.685083668f, 0.728464390f, + -0.686200312f, 0.727412629f, + -0.687315341f, 0.726359155f, + -0.688428753f, 0.725303972f, + -0.689540545f, 0.724247083f, + -0.690650714f, 0.723188489f, + -0.691759258f, 0.722128194f, + -0.692866175f, 0.721066199f, + -0.693971461f, 0.720002508f, + -0.695075114f, 0.718937122f, + -0.696177131f, 0.717870045f, + -0.697277511f, 0.716801279f, + -0.698376249f, 0.715730825f, + -0.699473345f, 0.714658688f, + -0.700568794f, 0.713584869f, + -0.701662595f, 0.712509371f, + -0.702754744f, 0.711432196f, + -0.703845241f, 0.710353347f, + -0.704934080f, 0.709272826f, + -0.706021261f, 0.708190637f, + -0.707106781f, 0.707106781f, + -0.708190637f, 0.706021261f, + -0.709272826f, 0.704934080f, + -0.710353347f, 0.703845241f, + -0.711432196f, 0.702754744f, + -0.712509371f, 0.701662595f, + -0.713584869f, 0.700568794f, + -0.714658688f, 0.699473345f, + -0.715730825f, 0.698376249f, + -0.716801279f, 0.697277511f, + -0.717870045f, 0.696177131f, + -0.718937122f, 0.695075114f, + -0.720002508f, 0.693971461f, + -0.721066199f, 0.692866175f, + -0.722128194f, 0.691759258f, + -0.723188489f, 0.690650714f, + -0.724247083f, 0.689540545f, + -0.725303972f, 0.688428753f, + -0.726359155f, 0.687315341f, + -0.727412629f, 0.686200312f, + -0.728464390f, 0.685083668f, + -0.729514438f, 0.683965412f, + -0.730562769f, 0.682845546f, + -0.731609381f, 0.681724074f, + -0.732654272f, 0.680600998f, + -0.733697438f, 0.679476320f, + -0.734738878f, 0.678350043f, + -0.735778589f, 0.677222170f, + -0.736816569f, 0.676092704f, + -0.737852815f, 0.674961646f, + -0.738887324f, 0.673829000f, + -0.739920095f, 0.672694769f, + -0.740951125f, 0.671558955f, + -0.741980412f, 0.670421560f, + -0.743007952f, 0.669282588f, + -0.744033744f, 0.668142041f, + -0.745057785f, 0.666999922f, + -0.746080074f, 0.665856234f, + -0.747100606f, 0.664710978f, + -0.748119380f, 0.663564159f, + -0.749136395f, 0.662415778f, + -0.750151646f, 0.661265838f, + -0.751165132f, 0.660114342f, + -0.752176850f, 0.658961293f, + -0.753186799f, 0.657806693f, + -0.754194975f, 0.656650546f, + -0.755201377f, 0.655492853f, + -0.756206001f, 0.654333618f, + -0.757208847f, 0.653172843f, + -0.758209910f, 0.652010531f, + -0.759209189f, 0.650846685f, + -0.760206682f, 0.649681307f, + -0.761202385f, 0.648514401f, + -0.762196298f, 0.647345969f, + -0.763188417f, 0.646176013f, + -0.764178741f, 0.645004537f, + -0.765167266f, 0.643831543f, + -0.766153990f, 0.642657034f, + -0.767138912f, 0.641481013f, + -0.768122029f, 0.640303482f, + -0.769103338f, 0.639124445f, + -0.770082837f, 0.637943904f, + -0.771060524f, 0.636761861f, + -0.772036397f, 0.635578320f, + -0.773010453f, 0.634393284f, + -0.773982691f, 0.633206755f, + -0.774953107f, 0.632018736f, + -0.775921699f, 0.630829230f, + -0.776888466f, 0.629638239f, + -0.777853404f, 0.628445767f, + -0.778816512f, 0.627251815f, + -0.779777788f, 0.626056388f, + -0.780737229f, 0.624859488f, + -0.781694832f, 0.623661118f, + -0.782650596f, 0.622461279f, + -0.783604519f, 0.621259977f, + -0.784556597f, 0.620057212f, + -0.785506830f, 0.618852988f, + -0.786455214f, 0.617647308f, + -0.787401747f, 0.616440175f, + -0.788346428f, 0.615231591f, + -0.789289253f, 0.614021559f, + -0.790230221f, 0.612810082f, + -0.791169330f, 0.611597164f, + -0.792106577f, 0.610382806f, + -0.793041960f, 0.609167012f, + -0.793975478f, 0.607949785f, + -0.794907126f, 0.606731127f, + -0.795836905f, 0.605511041f, + -0.796764810f, 0.604289531f, + -0.797690841f, 0.603066599f, + -0.798614995f, 0.601842247f, + -0.799537269f, 0.600616479f, + -0.800457662f, 0.599389298f, + -0.801376172f, 0.598160707f, + -0.802292796f, 0.596930708f, + -0.803207531f, 0.595699304f, + -0.804120377f, 0.594466499f, + -0.805031331f, 0.593232295f, + -0.805940391f, 0.591996695f, + -0.806847554f, 0.590759702f, + -0.807752818f, 0.589521319f, + -0.808656182f, 0.588281548f, + -0.809557642f, 0.587040394f, + -0.810457198f, 0.585797857f, + -0.811354847f, 0.584553943f, + -0.812250587f, 0.583308653f, + -0.813144415f, 0.582061990f, + -0.814036330f, 0.580813958f, + -0.814926329f, 0.579564559f, + -0.815814411f, 0.578313796f, + -0.816700573f, 0.577061673f, + -0.817584813f, 0.575808191f, + -0.818467130f, 0.574553355f, + -0.819347520f, 0.573297167f, + -0.820225983f, 0.572039629f, + -0.821102515f, 0.570780746f, + -0.821977115f, 0.569520519f, + -0.822849781f, 0.568258953f, + -0.823720511f, 0.566996049f, + -0.824589303f, 0.565731811f, + -0.825456154f, 0.564466242f, + -0.826321063f, 0.563199344f, + -0.827184027f, 0.561931121f, + -0.828045045f, 0.560661576f, + -0.828904115f, 0.559390712f, + -0.829761234f, 0.558118531f, + -0.830616400f, 0.556845037f, + -0.831469612f, 0.555570233f, + -0.832320868f, 0.554294121f, + -0.833170165f, 0.553016706f, + -0.834017501f, 0.551737988f, + -0.834862875f, 0.550457973f, + -0.835706284f, 0.549176662f, + -0.836547727f, 0.547894059f, + -0.837387202f, 0.546610167f, + -0.838224706f, 0.545324988f, + -0.839060237f, 0.544038527f, + -0.839893794f, 0.542750785f, + -0.840725375f, 0.541461766f, + -0.841554977f, 0.540171473f, + -0.842382600f, 0.538879909f, + -0.843208240f, 0.537587076f, + -0.844031895f, 0.536292979f, + -0.844853565f, 0.534997620f, + -0.845673247f, 0.533701002f, + -0.846490939f, 0.532403128f, + -0.847306639f, 0.531104001f, + -0.848120345f, 0.529803625f, + -0.848932055f, 0.528502002f, + -0.849741768f, 0.527199135f, + -0.850549481f, 0.525895027f, + -0.851355193f, 0.524589683f, + -0.852158902f, 0.523283103f, + -0.852960605f, 0.521975293f, + -0.853760301f, 0.520666254f, + -0.854557988f, 0.519355990f, + -0.855353665f, 0.518044504f, + -0.856147328f, 0.516731799f, + -0.856938977f, 0.515417878f, + -0.857728610f, 0.514102744f, + -0.858516224f, 0.512786401f, + -0.859301818f, 0.511468850f, + -0.860085390f, 0.510150097f, + -0.860866939f, 0.508830143f, + -0.861646461f, 0.507508991f, + -0.862423956f, 0.506186645f, + -0.863199422f, 0.504863109f, + -0.863972856f, 0.503538384f, + -0.864744258f, 0.502212474f, + -0.865513624f, 0.500885383f, + -0.866280954f, 0.499557113f, + -0.867046246f, 0.498227667f, + -0.867809497f, 0.496897049f, + -0.868570706f, 0.495565262f, + -0.869329871f, 0.494232309f, + -0.870086991f, 0.492898192f, + -0.870842063f, 0.491562916f, + -0.871595087f, 0.490226483f, + -0.872346059f, 0.488888897f, + -0.873094978f, 0.487550160f, + -0.873841843f, 0.486210276f, + -0.874586652f, 0.484869248f, + -0.875329403f, 0.483527079f, + -0.876070094f, 0.482183772f, + -0.876808724f, 0.480839331f, + -0.877545290f, 0.479493758f, + -0.878279792f, 0.478147056f, + -0.879012226f, 0.476799230f, + -0.879742593f, 0.475450282f, + -0.880470889f, 0.474100215f, + -0.881197113f, 0.472749032f, + -0.881921264f, 0.471396737f, + -0.882643340f, 0.470043332f, + -0.883363339f, 0.468688822f, + -0.884081259f, 0.467333209f, + -0.884797098f, 0.465976496f, + -0.885510856f, 0.464618686f, + -0.886222530f, 0.463259784f, + -0.886932119f, 0.461899791f, + -0.887639620f, 0.460538711f, + -0.888345033f, 0.459176548f, + -0.889048356f, 0.457813304f, + -0.889749586f, 0.456448982f, + -0.890448723f, 0.455083587f, + -0.891145765f, 0.453717121f, + -0.891840709f, 0.452349587f, + -0.892533555f, 0.450980989f, + -0.893224301f, 0.449611330f, + -0.893912945f, 0.448240612f, + -0.894599486f, 0.446868840f, + -0.895283921f, 0.445496017f, + -0.895966250f, 0.444122145f, + -0.896646470f, 0.442747228f, + -0.897324581f, 0.441371269f, + -0.898000580f, 0.439994271f, + -0.898674466f, 0.438616239f, + -0.899346237f, 0.437237174f, + -0.900015892f, 0.435857080f, + -0.900683429f, 0.434475961f, + -0.901348847f, 0.433093819f, + -0.902012144f, 0.431710658f, + -0.902673318f, 0.430326481f, + -0.903332368f, 0.428941292f, + -0.903989293f, 0.427555093f, + -0.904644091f, 0.426167889f, + -0.905296759f, 0.424779681f, + -0.905947298f, 0.423390474f, + -0.906595705f, 0.422000271f, + -0.907241978f, 0.420609074f, + -0.907886116f, 0.419216888f, + -0.908528119f, 0.417823716f, + -0.909167983f, 0.416429560f, + -0.909805708f, 0.415034424f, + -0.910441292f, 0.413638312f, + -0.911074734f, 0.412241227f, + -0.911706032f, 0.410843171f, + -0.912335185f, 0.409444149f, + -0.912962190f, 0.408044163f, + -0.913587048f, 0.406643217f, + -0.914209756f, 0.405241314f, + -0.914830312f, 0.403838458f, + -0.915448716f, 0.402434651f, + -0.916064966f, 0.401029897f, + -0.916679060f, 0.399624200f, + -0.917290997f, 0.398217562f, + -0.917900776f, 0.396809987f, + -0.918508394f, 0.395401479f, + -0.919113852f, 0.393992040f, + -0.919717146f, 0.392581674f, + -0.920318277f, 0.391170384f, + -0.920917242f, 0.389758174f, + -0.921514039f, 0.388345047f, + -0.922108669f, 0.386931006f, + -0.922701128f, 0.385516054f, + -0.923291417f, 0.384100195f, + -0.923879533f, 0.382683432f, + -0.924465474f, 0.381265769f, + -0.925049241f, 0.379847209f, + -0.925630831f, 0.378427755f, + -0.926210242f, 0.377007410f, + -0.926787474f, 0.375586178f, + -0.927362526f, 0.374164063f, + -0.927935395f, 0.372741067f, + -0.928506080f, 0.371317194f, + -0.929074581f, 0.369892447f, + -0.929640896f, 0.368466830f, + -0.930205023f, 0.367040346f, + -0.930766961f, 0.365612998f, + -0.931326709f, 0.364184790f, + -0.931884266f, 0.362755724f, + -0.932439629f, 0.361325806f, + -0.932992799f, 0.359895037f, + -0.933543773f, 0.358463421f, + -0.934092550f, 0.357030961f, + -0.934639130f, 0.355597662f, + -0.935183510f, 0.354163525f, + -0.935725689f, 0.352728556f, + -0.936265667f, 0.351292756f, + -0.936803442f, 0.349856130f, + -0.937339012f, 0.348418680f, + -0.937872376f, 0.346980411f, + -0.938403534f, 0.345541325f, + -0.938932484f, 0.344101426f, + -0.939459224f, 0.342660717f, + -0.939983753f, 0.341219202f, + -0.940506071f, 0.339776884f, + -0.941026175f, 0.338333767f, + -0.941544065f, 0.336889853f, + -0.942059740f, 0.335445147f, + -0.942573198f, 0.333999651f, + -0.943084437f, 0.332553370f, + -0.943593458f, 0.331106306f, + -0.944100258f, 0.329658463f, + -0.944604837f, 0.328209844f, + -0.945107193f, 0.326760452f, + -0.945607325f, 0.325310292f, + -0.946105232f, 0.323859367f, + -0.946600913f, 0.322407679f, + -0.947094366f, 0.320955232f, + -0.947585591f, 0.319502031f, + -0.948074586f, 0.318048077f, + -0.948561350f, 0.316593376f, + -0.949045882f, 0.315137929f, + -0.949528181f, 0.313681740f, + -0.950008245f, 0.312224814f, + -0.950486074f, 0.310767153f, + -0.950961666f, 0.309308760f, + -0.951435021f, 0.307849640f, + -0.951906137f, 0.306389795f, + -0.952375013f, 0.304929230f, + -0.952841648f, 0.303467947f, + -0.953306040f, 0.302005949f, + -0.953768190f, 0.300543241f, + -0.954228095f, 0.299079826f, + -0.954685755f, 0.297615707f, + -0.955141168f, 0.296150888f, + -0.955594334f, 0.294685372f, + -0.956045251f, 0.293219163f, + -0.956493919f, 0.291752263f, + -0.956940336f, 0.290284677f, + -0.957384501f, 0.288816408f, + -0.957826413f, 0.287347460f, + -0.958266071f, 0.285877835f, + -0.958703475f, 0.284407537f, + -0.959138622f, 0.282936570f, + -0.959571513f, 0.281464938f, + -0.960002146f, 0.279992643f, + -0.960430519f, 0.278519689f, + -0.960856633f, 0.277046080f, + -0.961280486f, 0.275571819f, + -0.961702077f, 0.274096910f, + -0.962121404f, 0.272621355f, + -0.962538468f, 0.271145160f, + -0.962953267f, 0.269668326f, + -0.963365800f, 0.268190857f, + -0.963776066f, 0.266712757f, + -0.964184064f, 0.265234030f, + -0.964589793f, 0.263754679f, + -0.964993253f, 0.262274707f, + -0.965394442f, 0.260794118f, + -0.965793359f, 0.259312915f, + -0.966190003f, 0.257831102f, + -0.966584374f, 0.256348682f, + -0.966976471f, 0.254865660f, + -0.967366292f, 0.253382037f, + -0.967753837f, 0.251897818f, + -0.968139105f, 0.250413007f, + -0.968522094f, 0.248927606f, + -0.968902805f, 0.247441619f, + -0.969281235f, 0.245955050f, + -0.969657385f, 0.244467903f, + -0.970031253f, 0.242980180f, + -0.970402839f, 0.241491885f, + -0.970772141f, 0.240003022f, + -0.971139158f, 0.238513595f, + -0.971503891f, 0.237023606f, + -0.971866337f, 0.235533059f, + -0.972226497f, 0.234041959f, + -0.972584369f, 0.232550307f, + -0.972939952f, 0.231058108f, + -0.973293246f, 0.229565366f, + -0.973644250f, 0.228072083f, + -0.973992962f, 0.226578264f, + -0.974339383f, 0.225083911f, + -0.974683511f, 0.223589029f, + -0.975025345f, 0.222093621f, + -0.975364885f, 0.220597690f, + -0.975702130f, 0.219101240f, + -0.976037079f, 0.217604275f, + -0.976369731f, 0.216106797f, + -0.976700086f, 0.214608811f, + -0.977028143f, 0.213110320f, + -0.977353900f, 0.211611327f, + -0.977677358f, 0.210111837f, + -0.977998515f, 0.208611852f, + -0.978317371f, 0.207111376f, + -0.978633924f, 0.205610413f, + -0.978948175f, 0.204108966f, + -0.979260123f, 0.202607039f, + -0.979569766f, 0.201104635f, + -0.979877104f, 0.199601758f, + -0.980182136f, 0.198098411f, + -0.980484862f, 0.196594598f, + -0.980785280f, 0.195090322f, + -0.981083391f, 0.193585587f, + -0.981379193f, 0.192080397f, + -0.981672686f, 0.190574755f, + -0.981963869f, 0.189068664f, + -0.982252741f, 0.187562129f, + -0.982539302f, 0.186055152f, + -0.982823551f, 0.184547737f, + -0.983105487f, 0.183039888f, + -0.983385110f, 0.181531608f, + -0.983662419f, 0.180022901f, + -0.983937413f, 0.178513771f, + -0.984210092f, 0.177004220f, + -0.984480455f, 0.175494253f, + -0.984748502f, 0.173983873f, + -0.985014231f, 0.172473084f, + -0.985277642f, 0.170961889f, + -0.985538735f, 0.169450291f, + -0.985797509f, 0.167938295f, + -0.986053963f, 0.166425904f, + -0.986308097f, 0.164913120f, + -0.986559910f, 0.163399949f, + -0.986809402f, 0.161886394f, + -0.987056571f, 0.160372457f, + -0.987301418f, 0.158858143f, + -0.987543942f, 0.157343456f, + -0.987784142f, 0.155828398f, + -0.988022017f, 0.154312973f, + -0.988257568f, 0.152797185f, + -0.988490793f, 0.151281038f, + -0.988721692f, 0.149764535f, + -0.988950265f, 0.148247679f, + -0.989176510f, 0.146730474f, + -0.989400428f, 0.145212925f, + -0.989622017f, 0.143695033f, + -0.989841278f, 0.142176804f, + -0.990058210f, 0.140658239f, + -0.990272812f, 0.139139344f, + -0.990485084f, 0.137620122f, + -0.990695025f, 0.136100575f, + -0.990902635f, 0.134580709f, + -0.991107914f, 0.133060525f, + -0.991310860f, 0.131540029f, + -0.991511473f, 0.130019223f, + -0.991709754f, 0.128498111f, + -0.991905700f, 0.126976696f, + -0.992099313f, 0.125454983f, + -0.992290591f, 0.123932975f, + -0.992479535f, 0.122410675f, + -0.992666142f, 0.120888087f, + -0.992850414f, 0.119365215f, + -0.993032350f, 0.117842062f, + -0.993211949f, 0.116318631f, + -0.993389211f, 0.114794927f, + -0.993564136f, 0.113270952f, + -0.993736722f, 0.111746711f, + -0.993906970f, 0.110222207f, + -0.994074879f, 0.108697444f, + -0.994240449f, 0.107172425f, + -0.994403680f, 0.105647154f, + -0.994564571f, 0.104121634f, + -0.994723121f, 0.102595869f, + -0.994879331f, 0.101069863f, + -0.995033199f, 0.099543619f, + -0.995184727f, 0.098017140f, + -0.995333912f, 0.096490431f, + -0.995480755f, 0.094963495f, + -0.995625256f, 0.093436336f, + -0.995767414f, 0.091908956f, + -0.995907229f, 0.090381361f, + -0.996044701f, 0.088853553f, + -0.996179829f, 0.087325535f, + -0.996312612f, 0.085797312f, + -0.996443051f, 0.084268888f, + -0.996571146f, 0.082740265f, + -0.996696895f, 0.081211447f, + -0.996820299f, 0.079682438f, + -0.996941358f, 0.078153242f, + -0.997060070f, 0.076623861f, + -0.997176437f, 0.075094301f, + -0.997290457f, 0.073564564f, + -0.997402130f, 0.072034653f, + -0.997511456f, 0.070504573f, + -0.997618435f, 0.068974328f, + -0.997723067f, 0.067443920f, + -0.997825350f, 0.065913353f, + -0.997925286f, 0.064382631f, + -0.998022874f, 0.062851758f, + -0.998118113f, 0.061320736f, + -0.998211003f, 0.059789571f, + -0.998301545f, 0.058258265f, + -0.998389737f, 0.056726821f, + -0.998475581f, 0.055195244f, + -0.998559074f, 0.053663538f, + -0.998640218f, 0.052131705f, + -0.998719012f, 0.050599749f, + -0.998795456f, 0.049067674f, + -0.998869550f, 0.047535484f, + -0.998941293f, 0.046003182f, + -0.999010686f, 0.044470772f, + -0.999077728f, 0.042938257f, + -0.999142419f, 0.041405641f, + -0.999204759f, 0.039872928f, + -0.999264747f, 0.038340120f, + -0.999322385f, 0.036807223f, + -0.999377670f, 0.035274239f, + -0.999430605f, 0.033741172f, + -0.999481187f, 0.032208025f, + -0.999529418f, 0.030674803f, + -0.999575296f, 0.029141509f, + -0.999618822f, 0.027608146f, + -0.999659997f, 0.026074718f, + -0.999698819f, 0.024541229f, + -0.999735288f, 0.023007681f, + -0.999769405f, 0.021474080f, + -0.999801170f, 0.019940429f, + -0.999830582f, 0.018406730f, + -0.999857641f, 0.016872988f, + -0.999882347f, 0.015339206f, + -0.999904701f, 0.013805389f, + -0.999924702f, 0.012271538f, + -0.999942350f, 0.010737659f, + -0.999957645f, 0.009203755f, + -0.999970586f, 0.007669829f, + -0.999981175f, 0.006135885f, + -0.999989411f, 0.004601926f, + -0.999995294f, 0.003067957f, + -0.999998823f, 0.001533980f, + -1.000000000f, 0.000000000f, + -0.999998823f, -0.001533980f, + -0.999995294f, -0.003067957f, + -0.999989411f, -0.004601926f, + -0.999981175f, -0.006135885f, + -0.999970586f, -0.007669829f, + -0.999957645f, -0.009203755f, + -0.999942350f, -0.010737659f, + -0.999924702f, -0.012271538f, + -0.999904701f, -0.013805389f, + -0.999882347f, -0.015339206f, + -0.999857641f, -0.016872988f, + -0.999830582f, -0.018406730f, + -0.999801170f, -0.019940429f, + -0.999769405f, -0.021474080f, + -0.999735288f, -0.023007681f, + -0.999698819f, -0.024541229f, + -0.999659997f, -0.026074718f, + -0.999618822f, -0.027608146f, + -0.999575296f, -0.029141509f, + -0.999529418f, -0.030674803f, + -0.999481187f, -0.032208025f, + -0.999430605f, -0.033741172f, + -0.999377670f, -0.035274239f, + -0.999322385f, -0.036807223f, + -0.999264747f, -0.038340120f, + -0.999204759f, -0.039872928f, + -0.999142419f, -0.041405641f, + -0.999077728f, -0.042938257f, + -0.999010686f, -0.044470772f, + -0.998941293f, -0.046003182f, + -0.998869550f, -0.047535484f, + -0.998795456f, -0.049067674f, + -0.998719012f, -0.050599749f, + -0.998640218f, -0.052131705f, + -0.998559074f, -0.053663538f, + -0.998475581f, -0.055195244f, + -0.998389737f, -0.056726821f, + -0.998301545f, -0.058258265f, + -0.998211003f, -0.059789571f, + -0.998118113f, -0.061320736f, + -0.998022874f, -0.062851758f, + -0.997925286f, -0.064382631f, + -0.997825350f, -0.065913353f, + -0.997723067f, -0.067443920f, + -0.997618435f, -0.068974328f, + -0.997511456f, -0.070504573f, + -0.997402130f, -0.072034653f, + -0.997290457f, -0.073564564f, + -0.997176437f, -0.075094301f, + -0.997060070f, -0.076623861f, + -0.996941358f, -0.078153242f, + -0.996820299f, -0.079682438f, + -0.996696895f, -0.081211447f, + -0.996571146f, -0.082740265f, + -0.996443051f, -0.084268888f, + -0.996312612f, -0.085797312f, + -0.996179829f, -0.087325535f, + -0.996044701f, -0.088853553f, + -0.995907229f, -0.090381361f, + -0.995767414f, -0.091908956f, + -0.995625256f, -0.093436336f, + -0.995480755f, -0.094963495f, + -0.995333912f, -0.096490431f, + -0.995184727f, -0.098017140f, + -0.995033199f, -0.099543619f, + -0.994879331f, -0.101069863f, + -0.994723121f, -0.102595869f, + -0.994564571f, -0.104121634f, + -0.994403680f, -0.105647154f, + -0.994240449f, -0.107172425f, + -0.994074879f, -0.108697444f, + -0.993906970f, -0.110222207f, + -0.993736722f, -0.111746711f, + -0.993564136f, -0.113270952f, + -0.993389211f, -0.114794927f, + -0.993211949f, -0.116318631f, + -0.993032350f, -0.117842062f, + -0.992850414f, -0.119365215f, + -0.992666142f, -0.120888087f, + -0.992479535f, -0.122410675f, + -0.992290591f, -0.123932975f, + -0.992099313f, -0.125454983f, + -0.991905700f, -0.126976696f, + -0.991709754f, -0.128498111f, + -0.991511473f, -0.130019223f, + -0.991310860f, -0.131540029f, + -0.991107914f, -0.133060525f, + -0.990902635f, -0.134580709f, + -0.990695025f, -0.136100575f, + -0.990485084f, -0.137620122f, + -0.990272812f, -0.139139344f, + -0.990058210f, -0.140658239f, + -0.989841278f, -0.142176804f, + -0.989622017f, -0.143695033f, + -0.989400428f, -0.145212925f, + -0.989176510f, -0.146730474f, + -0.988950265f, -0.148247679f, + -0.988721692f, -0.149764535f, + -0.988490793f, -0.151281038f, + -0.988257568f, -0.152797185f, + -0.988022017f, -0.154312973f, + -0.987784142f, -0.155828398f, + -0.987543942f, -0.157343456f, + -0.987301418f, -0.158858143f, + -0.987056571f, -0.160372457f, + -0.986809402f, -0.161886394f, + -0.986559910f, -0.163399949f, + -0.986308097f, -0.164913120f, + -0.986053963f, -0.166425904f, + -0.985797509f, -0.167938295f, + -0.985538735f, -0.169450291f, + -0.985277642f, -0.170961889f, + -0.985014231f, -0.172473084f, + -0.984748502f, -0.173983873f, + -0.984480455f, -0.175494253f, + -0.984210092f, -0.177004220f, + -0.983937413f, -0.178513771f, + -0.983662419f, -0.180022901f, + -0.983385110f, -0.181531608f, + -0.983105487f, -0.183039888f, + -0.982823551f, -0.184547737f, + -0.982539302f, -0.186055152f, + -0.982252741f, -0.187562129f, + -0.981963869f, -0.189068664f, + -0.981672686f, -0.190574755f, + -0.981379193f, -0.192080397f, + -0.981083391f, -0.193585587f, + -0.980785280f, -0.195090322f, + -0.980484862f, -0.196594598f, + -0.980182136f, -0.198098411f, + -0.979877104f, -0.199601758f, + -0.979569766f, -0.201104635f, + -0.979260123f, -0.202607039f, + -0.978948175f, -0.204108966f, + -0.978633924f, -0.205610413f, + -0.978317371f, -0.207111376f, + -0.977998515f, -0.208611852f, + -0.977677358f, -0.210111837f, + -0.977353900f, -0.211611327f, + -0.977028143f, -0.213110320f, + -0.976700086f, -0.214608811f, + -0.976369731f, -0.216106797f, + -0.976037079f, -0.217604275f, + -0.975702130f, -0.219101240f, + -0.975364885f, -0.220597690f, + -0.975025345f, -0.222093621f, + -0.974683511f, -0.223589029f, + -0.974339383f, -0.225083911f, + -0.973992962f, -0.226578264f, + -0.973644250f, -0.228072083f, + -0.973293246f, -0.229565366f, + -0.972939952f, -0.231058108f, + -0.972584369f, -0.232550307f, + -0.972226497f, -0.234041959f, + -0.971866337f, -0.235533059f, + -0.971503891f, -0.237023606f, + -0.971139158f, -0.238513595f, + -0.970772141f, -0.240003022f, + -0.970402839f, -0.241491885f, + -0.970031253f, -0.242980180f, + -0.969657385f, -0.244467903f, + -0.969281235f, -0.245955050f, + -0.968902805f, -0.247441619f, + -0.968522094f, -0.248927606f, + -0.968139105f, -0.250413007f, + -0.967753837f, -0.251897818f, + -0.967366292f, -0.253382037f, + -0.966976471f, -0.254865660f, + -0.966584374f, -0.256348682f, + -0.966190003f, -0.257831102f, + -0.965793359f, -0.259312915f, + -0.965394442f, -0.260794118f, + -0.964993253f, -0.262274707f, + -0.964589793f, -0.263754679f, + -0.964184064f, -0.265234030f, + -0.963776066f, -0.266712757f, + -0.963365800f, -0.268190857f, + -0.962953267f, -0.269668326f, + -0.962538468f, -0.271145160f, + -0.962121404f, -0.272621355f, + -0.961702077f, -0.274096910f, + -0.961280486f, -0.275571819f, + -0.960856633f, -0.277046080f, + -0.960430519f, -0.278519689f, + -0.960002146f, -0.279992643f, + -0.959571513f, -0.281464938f, + -0.959138622f, -0.282936570f, + -0.958703475f, -0.284407537f, + -0.958266071f, -0.285877835f, + -0.957826413f, -0.287347460f, + -0.957384501f, -0.288816408f, + -0.956940336f, -0.290284677f, + -0.956493919f, -0.291752263f, + -0.956045251f, -0.293219163f, + -0.955594334f, -0.294685372f, + -0.955141168f, -0.296150888f, + -0.954685755f, -0.297615707f, + -0.954228095f, -0.299079826f, + -0.953768190f, -0.300543241f, + -0.953306040f, -0.302005949f, + -0.952841648f, -0.303467947f, + -0.952375013f, -0.304929230f, + -0.951906137f, -0.306389795f, + -0.951435021f, -0.307849640f, + -0.950961666f, -0.309308760f, + -0.950486074f, -0.310767153f, + -0.950008245f, -0.312224814f, + -0.949528181f, -0.313681740f, + -0.949045882f, -0.315137929f, + -0.948561350f, -0.316593376f, + -0.948074586f, -0.318048077f, + -0.947585591f, -0.319502031f, + -0.947094366f, -0.320955232f, + -0.946600913f, -0.322407679f, + -0.946105232f, -0.323859367f, + -0.945607325f, -0.325310292f, + -0.945107193f, -0.326760452f, + -0.944604837f, -0.328209844f, + -0.944100258f, -0.329658463f, + -0.943593458f, -0.331106306f, + -0.943084437f, -0.332553370f, + -0.942573198f, -0.333999651f, + -0.942059740f, -0.335445147f, + -0.941544065f, -0.336889853f, + -0.941026175f, -0.338333767f, + -0.940506071f, -0.339776884f, + -0.939983753f, -0.341219202f, + -0.939459224f, -0.342660717f, + -0.938932484f, -0.344101426f, + -0.938403534f, -0.345541325f, + -0.937872376f, -0.346980411f, + -0.937339012f, -0.348418680f, + -0.936803442f, -0.349856130f, + -0.936265667f, -0.351292756f, + -0.935725689f, -0.352728556f, + -0.935183510f, -0.354163525f, + -0.934639130f, -0.355597662f, + -0.934092550f, -0.357030961f, + -0.933543773f, -0.358463421f, + -0.932992799f, -0.359895037f, + -0.932439629f, -0.361325806f, + -0.931884266f, -0.362755724f, + -0.931326709f, -0.364184790f, + -0.930766961f, -0.365612998f, + -0.930205023f, -0.367040346f, + -0.929640896f, -0.368466830f, + -0.929074581f, -0.369892447f, + -0.928506080f, -0.371317194f, + -0.927935395f, -0.372741067f, + -0.927362526f, -0.374164063f, + -0.926787474f, -0.375586178f, + -0.926210242f, -0.377007410f, + -0.925630831f, -0.378427755f, + -0.925049241f, -0.379847209f, + -0.924465474f, -0.381265769f, + -0.923879533f, -0.382683432f, + -0.923291417f, -0.384100195f, + -0.922701128f, -0.385516054f, + -0.922108669f, -0.386931006f, + -0.921514039f, -0.388345047f, + -0.920917242f, -0.389758174f, + -0.920318277f, -0.391170384f, + -0.919717146f, -0.392581674f, + -0.919113852f, -0.393992040f, + -0.918508394f, -0.395401479f, + -0.917900776f, -0.396809987f, + -0.917290997f, -0.398217562f, + -0.916679060f, -0.399624200f, + -0.916064966f, -0.401029897f, + -0.915448716f, -0.402434651f, + -0.914830312f, -0.403838458f, + -0.914209756f, -0.405241314f, + -0.913587048f, -0.406643217f, + -0.912962190f, -0.408044163f, + -0.912335185f, -0.409444149f, + -0.911706032f, -0.410843171f, + -0.911074734f, -0.412241227f, + -0.910441292f, -0.413638312f, + -0.909805708f, -0.415034424f, + -0.909167983f, -0.416429560f, + -0.908528119f, -0.417823716f, + -0.907886116f, -0.419216888f, + -0.907241978f, -0.420609074f, + -0.906595705f, -0.422000271f, + -0.905947298f, -0.423390474f, + -0.905296759f, -0.424779681f, + -0.904644091f, -0.426167889f, + -0.903989293f, -0.427555093f, + -0.903332368f, -0.428941292f, + -0.902673318f, -0.430326481f, + -0.902012144f, -0.431710658f, + -0.901348847f, -0.433093819f, + -0.900683429f, -0.434475961f, + -0.900015892f, -0.435857080f, + -0.899346237f, -0.437237174f, + -0.898674466f, -0.438616239f, + -0.898000580f, -0.439994271f, + -0.897324581f, -0.441371269f, + -0.896646470f, -0.442747228f, + -0.895966250f, -0.444122145f, + -0.895283921f, -0.445496017f, + -0.894599486f, -0.446868840f, + -0.893912945f, -0.448240612f, + -0.893224301f, -0.449611330f, + -0.892533555f, -0.450980989f, + -0.891840709f, -0.452349587f, + -0.891145765f, -0.453717121f, + -0.890448723f, -0.455083587f, + -0.889749586f, -0.456448982f, + -0.889048356f, -0.457813304f, + -0.888345033f, -0.459176548f, + -0.887639620f, -0.460538711f, + -0.886932119f, -0.461899791f, + -0.886222530f, -0.463259784f, + -0.885510856f, -0.464618686f, + -0.884797098f, -0.465976496f, + -0.884081259f, -0.467333209f, + -0.883363339f, -0.468688822f, + -0.882643340f, -0.470043332f, + -0.881921264f, -0.471396737f, + -0.881197113f, -0.472749032f, + -0.880470889f, -0.474100215f, + -0.879742593f, -0.475450282f, + -0.879012226f, -0.476799230f, + -0.878279792f, -0.478147056f, + -0.877545290f, -0.479493758f, + -0.876808724f, -0.480839331f, + -0.876070094f, -0.482183772f, + -0.875329403f, -0.483527079f, + -0.874586652f, -0.484869248f, + -0.873841843f, -0.486210276f, + -0.873094978f, -0.487550160f, + -0.872346059f, -0.488888897f, + -0.871595087f, -0.490226483f, + -0.870842063f, -0.491562916f, + -0.870086991f, -0.492898192f, + -0.869329871f, -0.494232309f, + -0.868570706f, -0.495565262f, + -0.867809497f, -0.496897049f, + -0.867046246f, -0.498227667f, + -0.866280954f, -0.499557113f, + -0.865513624f, -0.500885383f, + -0.864744258f, -0.502212474f, + -0.863972856f, -0.503538384f, + -0.863199422f, -0.504863109f, + -0.862423956f, -0.506186645f, + -0.861646461f, -0.507508991f, + -0.860866939f, -0.508830143f, + -0.860085390f, -0.510150097f, + -0.859301818f, -0.511468850f, + -0.858516224f, -0.512786401f, + -0.857728610f, -0.514102744f, + -0.856938977f, -0.515417878f, + -0.856147328f, -0.516731799f, + -0.855353665f, -0.518044504f, + -0.854557988f, -0.519355990f, + -0.853760301f, -0.520666254f, + -0.852960605f, -0.521975293f, + -0.852158902f, -0.523283103f, + -0.851355193f, -0.524589683f, + -0.850549481f, -0.525895027f, + -0.849741768f, -0.527199135f, + -0.848932055f, -0.528502002f, + -0.848120345f, -0.529803625f, + -0.847306639f, -0.531104001f, + -0.846490939f, -0.532403128f, + -0.845673247f, -0.533701002f, + -0.844853565f, -0.534997620f, + -0.844031895f, -0.536292979f, + -0.843208240f, -0.537587076f, + -0.842382600f, -0.538879909f, + -0.841554977f, -0.540171473f, + -0.840725375f, -0.541461766f, + -0.839893794f, -0.542750785f, + -0.839060237f, -0.544038527f, + -0.838224706f, -0.545324988f, + -0.837387202f, -0.546610167f, + -0.836547727f, -0.547894059f, + -0.835706284f, -0.549176662f, + -0.834862875f, -0.550457973f, + -0.834017501f, -0.551737988f, + -0.833170165f, -0.553016706f, + -0.832320868f, -0.554294121f, + -0.831469612f, -0.555570233f, + -0.830616400f, -0.556845037f, + -0.829761234f, -0.558118531f, + -0.828904115f, -0.559390712f, + -0.828045045f, -0.560661576f, + -0.827184027f, -0.561931121f, + -0.826321063f, -0.563199344f, + -0.825456154f, -0.564466242f, + -0.824589303f, -0.565731811f, + -0.823720511f, -0.566996049f, + -0.822849781f, -0.568258953f, + -0.821977115f, -0.569520519f, + -0.821102515f, -0.570780746f, + -0.820225983f, -0.572039629f, + -0.819347520f, -0.573297167f, + -0.818467130f, -0.574553355f, + -0.817584813f, -0.575808191f, + -0.816700573f, -0.577061673f, + -0.815814411f, -0.578313796f, + -0.814926329f, -0.579564559f, + -0.814036330f, -0.580813958f, + -0.813144415f, -0.582061990f, + -0.812250587f, -0.583308653f, + -0.811354847f, -0.584553943f, + -0.810457198f, -0.585797857f, + -0.809557642f, -0.587040394f, + -0.808656182f, -0.588281548f, + -0.807752818f, -0.589521319f, + -0.806847554f, -0.590759702f, + -0.805940391f, -0.591996695f, + -0.805031331f, -0.593232295f, + -0.804120377f, -0.594466499f, + -0.803207531f, -0.595699304f, + -0.802292796f, -0.596930708f, + -0.801376172f, -0.598160707f, + -0.800457662f, -0.599389298f, + -0.799537269f, -0.600616479f, + -0.798614995f, -0.601842247f, + -0.797690841f, -0.603066599f, + -0.796764810f, -0.604289531f, + -0.795836905f, -0.605511041f, + -0.794907126f, -0.606731127f, + -0.793975478f, -0.607949785f, + -0.793041960f, -0.609167012f, + -0.792106577f, -0.610382806f, + -0.791169330f, -0.611597164f, + -0.790230221f, -0.612810082f, + -0.789289253f, -0.614021559f, + -0.788346428f, -0.615231591f, + -0.787401747f, -0.616440175f, + -0.786455214f, -0.617647308f, + -0.785506830f, -0.618852988f, + -0.784556597f, -0.620057212f, + -0.783604519f, -0.621259977f, + -0.782650596f, -0.622461279f, + -0.781694832f, -0.623661118f, + -0.780737229f, -0.624859488f, + -0.779777788f, -0.626056388f, + -0.778816512f, -0.627251815f, + -0.777853404f, -0.628445767f, + -0.776888466f, -0.629638239f, + -0.775921699f, -0.630829230f, + -0.774953107f, -0.632018736f, + -0.773982691f, -0.633206755f, + -0.773010453f, -0.634393284f, + -0.772036397f, -0.635578320f, + -0.771060524f, -0.636761861f, + -0.770082837f, -0.637943904f, + -0.769103338f, -0.639124445f, + -0.768122029f, -0.640303482f, + -0.767138912f, -0.641481013f, + -0.766153990f, -0.642657034f, + -0.765167266f, -0.643831543f, + -0.764178741f, -0.645004537f, + -0.763188417f, -0.646176013f, + -0.762196298f, -0.647345969f, + -0.761202385f, -0.648514401f, + -0.760206682f, -0.649681307f, + -0.759209189f, -0.650846685f, + -0.758209910f, -0.652010531f, + -0.757208847f, -0.653172843f, + -0.756206001f, -0.654333618f, + -0.755201377f, -0.655492853f, + -0.754194975f, -0.656650546f, + -0.753186799f, -0.657806693f, + -0.752176850f, -0.658961293f, + -0.751165132f, -0.660114342f, + -0.750151646f, -0.661265838f, + -0.749136395f, -0.662415778f, + -0.748119380f, -0.663564159f, + -0.747100606f, -0.664710978f, + -0.746080074f, -0.665856234f, + -0.745057785f, -0.666999922f, + -0.744033744f, -0.668142041f, + -0.743007952f, -0.669282588f, + -0.741980412f, -0.670421560f, + -0.740951125f, -0.671558955f, + -0.739920095f, -0.672694769f, + -0.738887324f, -0.673829000f, + -0.737852815f, -0.674961646f, + -0.736816569f, -0.676092704f, + -0.735778589f, -0.677222170f, + -0.734738878f, -0.678350043f, + -0.733697438f, -0.679476320f, + -0.732654272f, -0.680600998f, + -0.731609381f, -0.681724074f, + -0.730562769f, -0.682845546f, + -0.729514438f, -0.683965412f, + -0.728464390f, -0.685083668f, + -0.727412629f, -0.686200312f, + -0.726359155f, -0.687315341f, + -0.725303972f, -0.688428753f, + -0.724247083f, -0.689540545f, + -0.723188489f, -0.690650714f, + -0.722128194f, -0.691759258f, + -0.721066199f, -0.692866175f, + -0.720002508f, -0.693971461f, + -0.718937122f, -0.695075114f, + -0.717870045f, -0.696177131f, + -0.716801279f, -0.697277511f, + -0.715730825f, -0.698376249f, + -0.714658688f, -0.699473345f, + -0.713584869f, -0.700568794f, + -0.712509371f, -0.701662595f, + -0.711432196f, -0.702754744f, + -0.710353347f, -0.703845241f, + -0.709272826f, -0.704934080f, + -0.708190637f, -0.706021261f, + -0.707106781f, -0.707106781f, + -0.706021261f, -0.708190637f, + -0.704934080f, -0.709272826f, + -0.703845241f, -0.710353347f, + -0.702754744f, -0.711432196f, + -0.701662595f, -0.712509371f, + -0.700568794f, -0.713584869f, + -0.699473345f, -0.714658688f, + -0.698376249f, -0.715730825f, + -0.697277511f, -0.716801279f, + -0.696177131f, -0.717870045f, + -0.695075114f, -0.718937122f, + -0.693971461f, -0.720002508f, + -0.692866175f, -0.721066199f, + -0.691759258f, -0.722128194f, + -0.690650714f, -0.723188489f, + -0.689540545f, -0.724247083f, + -0.688428753f, -0.725303972f, + -0.687315341f, -0.726359155f, + -0.686200312f, -0.727412629f, + -0.685083668f, -0.728464390f, + -0.683965412f, -0.729514438f, + -0.682845546f, -0.730562769f, + -0.681724074f, -0.731609381f, + -0.680600998f, -0.732654272f, + -0.679476320f, -0.733697438f, + -0.678350043f, -0.734738878f, + -0.677222170f, -0.735778589f, + -0.676092704f, -0.736816569f, + -0.674961646f, -0.737852815f, + -0.673829000f, -0.738887324f, + -0.672694769f, -0.739920095f, + -0.671558955f, -0.740951125f, + -0.670421560f, -0.741980412f, + -0.669282588f, -0.743007952f, + -0.668142041f, -0.744033744f, + -0.666999922f, -0.745057785f, + -0.665856234f, -0.746080074f, + -0.664710978f, -0.747100606f, + -0.663564159f, -0.748119380f, + -0.662415778f, -0.749136395f, + -0.661265838f, -0.750151646f, + -0.660114342f, -0.751165132f, + -0.658961293f, -0.752176850f, + -0.657806693f, -0.753186799f, + -0.656650546f, -0.754194975f, + -0.655492853f, -0.755201377f, + -0.654333618f, -0.756206001f, + -0.653172843f, -0.757208847f, + -0.652010531f, -0.758209910f, + -0.650846685f, -0.759209189f, + -0.649681307f, -0.760206682f, + -0.648514401f, -0.761202385f, + -0.647345969f, -0.762196298f, + -0.646176013f, -0.763188417f, + -0.645004537f, -0.764178741f, + -0.643831543f, -0.765167266f, + -0.642657034f, -0.766153990f, + -0.641481013f, -0.767138912f, + -0.640303482f, -0.768122029f, + -0.639124445f, -0.769103338f, + -0.637943904f, -0.770082837f, + -0.636761861f, -0.771060524f, + -0.635578320f, -0.772036397f, + -0.634393284f, -0.773010453f, + -0.633206755f, -0.773982691f, + -0.632018736f, -0.774953107f, + -0.630829230f, -0.775921699f, + -0.629638239f, -0.776888466f, + -0.628445767f, -0.777853404f, + -0.627251815f, -0.778816512f, + -0.626056388f, -0.779777788f, + -0.624859488f, -0.780737229f, + -0.623661118f, -0.781694832f, + -0.622461279f, -0.782650596f, + -0.621259977f, -0.783604519f, + -0.620057212f, -0.784556597f, + -0.618852988f, -0.785506830f, + -0.617647308f, -0.786455214f, + -0.616440175f, -0.787401747f, + -0.615231591f, -0.788346428f, + -0.614021559f, -0.789289253f, + -0.612810082f, -0.790230221f, + -0.611597164f, -0.791169330f, + -0.610382806f, -0.792106577f, + -0.609167012f, -0.793041960f, + -0.607949785f, -0.793975478f, + -0.606731127f, -0.794907126f, + -0.605511041f, -0.795836905f, + -0.604289531f, -0.796764810f, + -0.603066599f, -0.797690841f, + -0.601842247f, -0.798614995f, + -0.600616479f, -0.799537269f, + -0.599389298f, -0.800457662f, + -0.598160707f, -0.801376172f, + -0.596930708f, -0.802292796f, + -0.595699304f, -0.803207531f, + -0.594466499f, -0.804120377f, + -0.593232295f, -0.805031331f, + -0.591996695f, -0.805940391f, + -0.590759702f, -0.806847554f, + -0.589521319f, -0.807752818f, + -0.588281548f, -0.808656182f, + -0.587040394f, -0.809557642f, + -0.585797857f, -0.810457198f, + -0.584553943f, -0.811354847f, + -0.583308653f, -0.812250587f, + -0.582061990f, -0.813144415f, + -0.580813958f, -0.814036330f, + -0.579564559f, -0.814926329f, + -0.578313796f, -0.815814411f, + -0.577061673f, -0.816700573f, + -0.575808191f, -0.817584813f, + -0.574553355f, -0.818467130f, + -0.573297167f, -0.819347520f, + -0.572039629f, -0.820225983f, + -0.570780746f, -0.821102515f, + -0.569520519f, -0.821977115f, + -0.568258953f, -0.822849781f, + -0.566996049f, -0.823720511f, + -0.565731811f, -0.824589303f, + -0.564466242f, -0.825456154f, + -0.563199344f, -0.826321063f, + -0.561931121f, -0.827184027f, + -0.560661576f, -0.828045045f, + -0.559390712f, -0.828904115f, + -0.558118531f, -0.829761234f, + -0.556845037f, -0.830616400f, + -0.555570233f, -0.831469612f, + -0.554294121f, -0.832320868f, + -0.553016706f, -0.833170165f, + -0.551737988f, -0.834017501f, + -0.550457973f, -0.834862875f, + -0.549176662f, -0.835706284f, + -0.547894059f, -0.836547727f, + -0.546610167f, -0.837387202f, + -0.545324988f, -0.838224706f, + -0.544038527f, -0.839060237f, + -0.542750785f, -0.839893794f, + -0.541461766f, -0.840725375f, + -0.540171473f, -0.841554977f, + -0.538879909f, -0.842382600f, + -0.537587076f, -0.843208240f, + -0.536292979f, -0.844031895f, + -0.534997620f, -0.844853565f, + -0.533701002f, -0.845673247f, + -0.532403128f, -0.846490939f, + -0.531104001f, -0.847306639f, + -0.529803625f, -0.848120345f, + -0.528502002f, -0.848932055f, + -0.527199135f, -0.849741768f, + -0.525895027f, -0.850549481f, + -0.524589683f, -0.851355193f, + -0.523283103f, -0.852158902f, + -0.521975293f, -0.852960605f, + -0.520666254f, -0.853760301f, + -0.519355990f, -0.854557988f, + -0.518044504f, -0.855353665f, + -0.516731799f, -0.856147328f, + -0.515417878f, -0.856938977f, + -0.514102744f, -0.857728610f, + -0.512786401f, -0.858516224f, + -0.511468850f, -0.859301818f, + -0.510150097f, -0.860085390f, + -0.508830143f, -0.860866939f, + -0.507508991f, -0.861646461f, + -0.506186645f, -0.862423956f, + -0.504863109f, -0.863199422f, + -0.503538384f, -0.863972856f, + -0.502212474f, -0.864744258f, + -0.500885383f, -0.865513624f, + -0.499557113f, -0.866280954f, + -0.498227667f, -0.867046246f, + -0.496897049f, -0.867809497f, + -0.495565262f, -0.868570706f, + -0.494232309f, -0.869329871f, + -0.492898192f, -0.870086991f, + -0.491562916f, -0.870842063f, + -0.490226483f, -0.871595087f, + -0.488888897f, -0.872346059f, + -0.487550160f, -0.873094978f, + -0.486210276f, -0.873841843f, + -0.484869248f, -0.874586652f, + -0.483527079f, -0.875329403f, + -0.482183772f, -0.876070094f, + -0.480839331f, -0.876808724f, + -0.479493758f, -0.877545290f, + -0.478147056f, -0.878279792f, + -0.476799230f, -0.879012226f, + -0.475450282f, -0.879742593f, + -0.474100215f, -0.880470889f, + -0.472749032f, -0.881197113f, + -0.471396737f, -0.881921264f, + -0.470043332f, -0.882643340f, + -0.468688822f, -0.883363339f, + -0.467333209f, -0.884081259f, + -0.465976496f, -0.884797098f, + -0.464618686f, -0.885510856f, + -0.463259784f, -0.886222530f, + -0.461899791f, -0.886932119f, + -0.460538711f, -0.887639620f, + -0.459176548f, -0.888345033f, + -0.457813304f, -0.889048356f, + -0.456448982f, -0.889749586f, + -0.455083587f, -0.890448723f, + -0.453717121f, -0.891145765f, + -0.452349587f, -0.891840709f, + -0.450980989f, -0.892533555f, + -0.449611330f, -0.893224301f, + -0.448240612f, -0.893912945f, + -0.446868840f, -0.894599486f, + -0.445496017f, -0.895283921f, + -0.444122145f, -0.895966250f, + -0.442747228f, -0.896646470f, + -0.441371269f, -0.897324581f, + -0.439994271f, -0.898000580f, + -0.438616239f, -0.898674466f, + -0.437237174f, -0.899346237f, + -0.435857080f, -0.900015892f, + -0.434475961f, -0.900683429f, + -0.433093819f, -0.901348847f, + -0.431710658f, -0.902012144f, + -0.430326481f, -0.902673318f, + -0.428941292f, -0.903332368f, + -0.427555093f, -0.903989293f, + -0.426167889f, -0.904644091f, + -0.424779681f, -0.905296759f, + -0.423390474f, -0.905947298f, + -0.422000271f, -0.906595705f, + -0.420609074f, -0.907241978f, + -0.419216888f, -0.907886116f, + -0.417823716f, -0.908528119f, + -0.416429560f, -0.909167983f, + -0.415034424f, -0.909805708f, + -0.413638312f, -0.910441292f, + -0.412241227f, -0.911074734f, + -0.410843171f, -0.911706032f, + -0.409444149f, -0.912335185f, + -0.408044163f, -0.912962190f, + -0.406643217f, -0.913587048f, + -0.405241314f, -0.914209756f, + -0.403838458f, -0.914830312f, + -0.402434651f, -0.915448716f, + -0.401029897f, -0.916064966f, + -0.399624200f, -0.916679060f, + -0.398217562f, -0.917290997f, + -0.396809987f, -0.917900776f, + -0.395401479f, -0.918508394f, + -0.393992040f, -0.919113852f, + -0.392581674f, -0.919717146f, + -0.391170384f, -0.920318277f, + -0.389758174f, -0.920917242f, + -0.388345047f, -0.921514039f, + -0.386931006f, -0.922108669f, + -0.385516054f, -0.922701128f, + -0.384100195f, -0.923291417f, + -0.382683432f, -0.923879533f, + -0.381265769f, -0.924465474f, + -0.379847209f, -0.925049241f, + -0.378427755f, -0.925630831f, + -0.377007410f, -0.926210242f, + -0.375586178f, -0.926787474f, + -0.374164063f, -0.927362526f, + -0.372741067f, -0.927935395f, + -0.371317194f, -0.928506080f, + -0.369892447f, -0.929074581f, + -0.368466830f, -0.929640896f, + -0.367040346f, -0.930205023f, + -0.365612998f, -0.930766961f, + -0.364184790f, -0.931326709f, + -0.362755724f, -0.931884266f, + -0.361325806f, -0.932439629f, + -0.359895037f, -0.932992799f, + -0.358463421f, -0.933543773f, + -0.357030961f, -0.934092550f, + -0.355597662f, -0.934639130f, + -0.354163525f, -0.935183510f, + -0.352728556f, -0.935725689f, + -0.351292756f, -0.936265667f, + -0.349856130f, -0.936803442f, + -0.348418680f, -0.937339012f, + -0.346980411f, -0.937872376f, + -0.345541325f, -0.938403534f, + -0.344101426f, -0.938932484f, + -0.342660717f, -0.939459224f, + -0.341219202f, -0.939983753f, + -0.339776884f, -0.940506071f, + -0.338333767f, -0.941026175f, + -0.336889853f, -0.941544065f, + -0.335445147f, -0.942059740f, + -0.333999651f, -0.942573198f, + -0.332553370f, -0.943084437f, + -0.331106306f, -0.943593458f, + -0.329658463f, -0.944100258f, + -0.328209844f, -0.944604837f, + -0.326760452f, -0.945107193f, + -0.325310292f, -0.945607325f, + -0.323859367f, -0.946105232f, + -0.322407679f, -0.946600913f, + -0.320955232f, -0.947094366f, + -0.319502031f, -0.947585591f, + -0.318048077f, -0.948074586f, + -0.316593376f, -0.948561350f, + -0.315137929f, -0.949045882f, + -0.313681740f, -0.949528181f, + -0.312224814f, -0.950008245f, + -0.310767153f, -0.950486074f, + -0.309308760f, -0.950961666f, + -0.307849640f, -0.951435021f, + -0.306389795f, -0.951906137f, + -0.304929230f, -0.952375013f, + -0.303467947f, -0.952841648f, + -0.302005949f, -0.953306040f, + -0.300543241f, -0.953768190f, + -0.299079826f, -0.954228095f, + -0.297615707f, -0.954685755f, + -0.296150888f, -0.955141168f, + -0.294685372f, -0.955594334f, + -0.293219163f, -0.956045251f, + -0.291752263f, -0.956493919f, + -0.290284677f, -0.956940336f, + -0.288816408f, -0.957384501f, + -0.287347460f, -0.957826413f, + -0.285877835f, -0.958266071f, + -0.284407537f, -0.958703475f, + -0.282936570f, -0.959138622f, + -0.281464938f, -0.959571513f, + -0.279992643f, -0.960002146f, + -0.278519689f, -0.960430519f, + -0.277046080f, -0.960856633f, + -0.275571819f, -0.961280486f, + -0.274096910f, -0.961702077f, + -0.272621355f, -0.962121404f, + -0.271145160f, -0.962538468f, + -0.269668326f, -0.962953267f, + -0.268190857f, -0.963365800f, + -0.266712757f, -0.963776066f, + -0.265234030f, -0.964184064f, + -0.263754679f, -0.964589793f, + -0.262274707f, -0.964993253f, + -0.260794118f, -0.965394442f, + -0.259312915f, -0.965793359f, + -0.257831102f, -0.966190003f, + -0.256348682f, -0.966584374f, + -0.254865660f, -0.966976471f, + -0.253382037f, -0.967366292f, + -0.251897818f, -0.967753837f, + -0.250413007f, -0.968139105f, + -0.248927606f, -0.968522094f, + -0.247441619f, -0.968902805f, + -0.245955050f, -0.969281235f, + -0.244467903f, -0.969657385f, + -0.242980180f, -0.970031253f, + -0.241491885f, -0.970402839f, + -0.240003022f, -0.970772141f, + -0.238513595f, -0.971139158f, + -0.237023606f, -0.971503891f, + -0.235533059f, -0.971866337f, + -0.234041959f, -0.972226497f, + -0.232550307f, -0.972584369f, + -0.231058108f, -0.972939952f, + -0.229565366f, -0.973293246f, + -0.228072083f, -0.973644250f, + -0.226578264f, -0.973992962f, + -0.225083911f, -0.974339383f, + -0.223589029f, -0.974683511f, + -0.222093621f, -0.975025345f, + -0.220597690f, -0.975364885f, + -0.219101240f, -0.975702130f, + -0.217604275f, -0.976037079f, + -0.216106797f, -0.976369731f, + -0.214608811f, -0.976700086f, + -0.213110320f, -0.977028143f, + -0.211611327f, -0.977353900f, + -0.210111837f, -0.977677358f, + -0.208611852f, -0.977998515f, + -0.207111376f, -0.978317371f, + -0.205610413f, -0.978633924f, + -0.204108966f, -0.978948175f, + -0.202607039f, -0.979260123f, + -0.201104635f, -0.979569766f, + -0.199601758f, -0.979877104f, + -0.198098411f, -0.980182136f, + -0.196594598f, -0.980484862f, + -0.195090322f, -0.980785280f, + -0.193585587f, -0.981083391f, + -0.192080397f, -0.981379193f, + -0.190574755f, -0.981672686f, + -0.189068664f, -0.981963869f, + -0.187562129f, -0.982252741f, + -0.186055152f, -0.982539302f, + -0.184547737f, -0.982823551f, + -0.183039888f, -0.983105487f, + -0.181531608f, -0.983385110f, + -0.180022901f, -0.983662419f, + -0.178513771f, -0.983937413f, + -0.177004220f, -0.984210092f, + -0.175494253f, -0.984480455f, + -0.173983873f, -0.984748502f, + -0.172473084f, -0.985014231f, + -0.170961889f, -0.985277642f, + -0.169450291f, -0.985538735f, + -0.167938295f, -0.985797509f, + -0.166425904f, -0.986053963f, + -0.164913120f, -0.986308097f, + -0.163399949f, -0.986559910f, + -0.161886394f, -0.986809402f, + -0.160372457f, -0.987056571f, + -0.158858143f, -0.987301418f, + -0.157343456f, -0.987543942f, + -0.155828398f, -0.987784142f, + -0.154312973f, -0.988022017f, + -0.152797185f, -0.988257568f, + -0.151281038f, -0.988490793f, + -0.149764535f, -0.988721692f, + -0.148247679f, -0.988950265f, + -0.146730474f, -0.989176510f, + -0.145212925f, -0.989400428f, + -0.143695033f, -0.989622017f, + -0.142176804f, -0.989841278f, + -0.140658239f, -0.990058210f, + -0.139139344f, -0.990272812f, + -0.137620122f, -0.990485084f, + -0.136100575f, -0.990695025f, + -0.134580709f, -0.990902635f, + -0.133060525f, -0.991107914f, + -0.131540029f, -0.991310860f, + -0.130019223f, -0.991511473f, + -0.128498111f, -0.991709754f, + -0.126976696f, -0.991905700f, + -0.125454983f, -0.992099313f, + -0.123932975f, -0.992290591f, + -0.122410675f, -0.992479535f, + -0.120888087f, -0.992666142f, + -0.119365215f, -0.992850414f, + -0.117842062f, -0.993032350f, + -0.116318631f, -0.993211949f, + -0.114794927f, -0.993389211f, + -0.113270952f, -0.993564136f, + -0.111746711f, -0.993736722f, + -0.110222207f, -0.993906970f, + -0.108697444f, -0.994074879f, + -0.107172425f, -0.994240449f, + -0.105647154f, -0.994403680f, + -0.104121634f, -0.994564571f, + -0.102595869f, -0.994723121f, + -0.101069863f, -0.994879331f, + -0.099543619f, -0.995033199f, + -0.098017140f, -0.995184727f, + -0.096490431f, -0.995333912f, + -0.094963495f, -0.995480755f, + -0.093436336f, -0.995625256f, + -0.091908956f, -0.995767414f, + -0.090381361f, -0.995907229f, + -0.088853553f, -0.996044701f, + -0.087325535f, -0.996179829f, + -0.085797312f, -0.996312612f, + -0.084268888f, -0.996443051f, + -0.082740265f, -0.996571146f, + -0.081211447f, -0.996696895f, + -0.079682438f, -0.996820299f, + -0.078153242f, -0.996941358f, + -0.076623861f, -0.997060070f, + -0.075094301f, -0.997176437f, + -0.073564564f, -0.997290457f, + -0.072034653f, -0.997402130f, + -0.070504573f, -0.997511456f, + -0.068974328f, -0.997618435f, + -0.067443920f, -0.997723067f, + -0.065913353f, -0.997825350f, + -0.064382631f, -0.997925286f, + -0.062851758f, -0.998022874f, + -0.061320736f, -0.998118113f, + -0.059789571f, -0.998211003f, + -0.058258265f, -0.998301545f, + -0.056726821f, -0.998389737f, + -0.055195244f, -0.998475581f, + -0.053663538f, -0.998559074f, + -0.052131705f, -0.998640218f, + -0.050599749f, -0.998719012f, + -0.049067674f, -0.998795456f, + -0.047535484f, -0.998869550f, + -0.046003182f, -0.998941293f, + -0.044470772f, -0.999010686f, + -0.042938257f, -0.999077728f, + -0.041405641f, -0.999142419f, + -0.039872928f, -0.999204759f, + -0.038340120f, -0.999264747f, + -0.036807223f, -0.999322385f, + -0.035274239f, -0.999377670f, + -0.033741172f, -0.999430605f, + -0.032208025f, -0.999481187f, + -0.030674803f, -0.999529418f, + -0.029141509f, -0.999575296f, + -0.027608146f, -0.999618822f, + -0.026074718f, -0.999659997f, + -0.024541229f, -0.999698819f, + -0.023007681f, -0.999735288f, + -0.021474080f, -0.999769405f, + -0.019940429f, -0.999801170f, + -0.018406730f, -0.999830582f, + -0.016872988f, -0.999857641f, + -0.015339206f, -0.999882347f, + -0.013805389f, -0.999904701f, + -0.012271538f, -0.999924702f, + -0.010737659f, -0.999942350f, + -0.009203755f, -0.999957645f, + -0.007669829f, -0.999970586f, + -0.006135885f, -0.999981175f, + -0.004601926f, -0.999989411f, + -0.003067957f, -0.999995294f, + -0.001533980f, -0.999998823f, + -0.000000000f, -1.000000000f, + 0.001533980f, -0.999998823f, + 0.003067957f, -0.999995294f, + 0.004601926f, -0.999989411f, + 0.006135885f, -0.999981175f, + 0.007669829f, -0.999970586f, + 0.009203755f, -0.999957645f, + 0.010737659f, -0.999942350f, + 0.012271538f, -0.999924702f, + 0.013805389f, -0.999904701f, + 0.015339206f, -0.999882347f, + 0.016872988f, -0.999857641f, + 0.018406730f, -0.999830582f, + 0.019940429f, -0.999801170f, + 0.021474080f, -0.999769405f, + 0.023007681f, -0.999735288f, + 0.024541229f, -0.999698819f, + 0.026074718f, -0.999659997f, + 0.027608146f, -0.999618822f, + 0.029141509f, -0.999575296f, + 0.030674803f, -0.999529418f, + 0.032208025f, -0.999481187f, + 0.033741172f, -0.999430605f, + 0.035274239f, -0.999377670f, + 0.036807223f, -0.999322385f, + 0.038340120f, -0.999264747f, + 0.039872928f, -0.999204759f, + 0.041405641f, -0.999142419f, + 0.042938257f, -0.999077728f, + 0.044470772f, -0.999010686f, + 0.046003182f, -0.998941293f, + 0.047535484f, -0.998869550f, + 0.049067674f, -0.998795456f, + 0.050599749f, -0.998719012f, + 0.052131705f, -0.998640218f, + 0.053663538f, -0.998559074f, + 0.055195244f, -0.998475581f, + 0.056726821f, -0.998389737f, + 0.058258265f, -0.998301545f, + 0.059789571f, -0.998211003f, + 0.061320736f, -0.998118113f, + 0.062851758f, -0.998022874f, + 0.064382631f, -0.997925286f, + 0.065913353f, -0.997825350f, + 0.067443920f, -0.997723067f, + 0.068974328f, -0.997618435f, + 0.070504573f, -0.997511456f, + 0.072034653f, -0.997402130f, + 0.073564564f, -0.997290457f, + 0.075094301f, -0.997176437f, + 0.076623861f, -0.997060070f, + 0.078153242f, -0.996941358f, + 0.079682438f, -0.996820299f, + 0.081211447f, -0.996696895f, + 0.082740265f, -0.996571146f, + 0.084268888f, -0.996443051f, + 0.085797312f, -0.996312612f, + 0.087325535f, -0.996179829f, + 0.088853553f, -0.996044701f, + 0.090381361f, -0.995907229f, + 0.091908956f, -0.995767414f, + 0.093436336f, -0.995625256f, + 0.094963495f, -0.995480755f, + 0.096490431f, -0.995333912f, + 0.098017140f, -0.995184727f, + 0.099543619f, -0.995033199f, + 0.101069863f, -0.994879331f, + 0.102595869f, -0.994723121f, + 0.104121634f, -0.994564571f, + 0.105647154f, -0.994403680f, + 0.107172425f, -0.994240449f, + 0.108697444f, -0.994074879f, + 0.110222207f, -0.993906970f, + 0.111746711f, -0.993736722f, + 0.113270952f, -0.993564136f, + 0.114794927f, -0.993389211f, + 0.116318631f, -0.993211949f, + 0.117842062f, -0.993032350f, + 0.119365215f, -0.992850414f, + 0.120888087f, -0.992666142f, + 0.122410675f, -0.992479535f, + 0.123932975f, -0.992290591f, + 0.125454983f, -0.992099313f, + 0.126976696f, -0.991905700f, + 0.128498111f, -0.991709754f, + 0.130019223f, -0.991511473f, + 0.131540029f, -0.991310860f, + 0.133060525f, -0.991107914f, + 0.134580709f, -0.990902635f, + 0.136100575f, -0.990695025f, + 0.137620122f, -0.990485084f, + 0.139139344f, -0.990272812f, + 0.140658239f, -0.990058210f, + 0.142176804f, -0.989841278f, + 0.143695033f, -0.989622017f, + 0.145212925f, -0.989400428f, + 0.146730474f, -0.989176510f, + 0.148247679f, -0.988950265f, + 0.149764535f, -0.988721692f, + 0.151281038f, -0.988490793f, + 0.152797185f, -0.988257568f, + 0.154312973f, -0.988022017f, + 0.155828398f, -0.987784142f, + 0.157343456f, -0.987543942f, + 0.158858143f, -0.987301418f, + 0.160372457f, -0.987056571f, + 0.161886394f, -0.986809402f, + 0.163399949f, -0.986559910f, + 0.164913120f, -0.986308097f, + 0.166425904f, -0.986053963f, + 0.167938295f, -0.985797509f, + 0.169450291f, -0.985538735f, + 0.170961889f, -0.985277642f, + 0.172473084f, -0.985014231f, + 0.173983873f, -0.984748502f, + 0.175494253f, -0.984480455f, + 0.177004220f, -0.984210092f, + 0.178513771f, -0.983937413f, + 0.180022901f, -0.983662419f, + 0.181531608f, -0.983385110f, + 0.183039888f, -0.983105487f, + 0.184547737f, -0.982823551f, + 0.186055152f, -0.982539302f, + 0.187562129f, -0.982252741f, + 0.189068664f, -0.981963869f, + 0.190574755f, -0.981672686f, + 0.192080397f, -0.981379193f, + 0.193585587f, -0.981083391f, + 0.195090322f, -0.980785280f, + 0.196594598f, -0.980484862f, + 0.198098411f, -0.980182136f, + 0.199601758f, -0.979877104f, + 0.201104635f, -0.979569766f, + 0.202607039f, -0.979260123f, + 0.204108966f, -0.978948175f, + 0.205610413f, -0.978633924f, + 0.207111376f, -0.978317371f, + 0.208611852f, -0.977998515f, + 0.210111837f, -0.977677358f, + 0.211611327f, -0.977353900f, + 0.213110320f, -0.977028143f, + 0.214608811f, -0.976700086f, + 0.216106797f, -0.976369731f, + 0.217604275f, -0.976037079f, + 0.219101240f, -0.975702130f, + 0.220597690f, -0.975364885f, + 0.222093621f, -0.975025345f, + 0.223589029f, -0.974683511f, + 0.225083911f, -0.974339383f, + 0.226578264f, -0.973992962f, + 0.228072083f, -0.973644250f, + 0.229565366f, -0.973293246f, + 0.231058108f, -0.972939952f, + 0.232550307f, -0.972584369f, + 0.234041959f, -0.972226497f, + 0.235533059f, -0.971866337f, + 0.237023606f, -0.971503891f, + 0.238513595f, -0.971139158f, + 0.240003022f, -0.970772141f, + 0.241491885f, -0.970402839f, + 0.242980180f, -0.970031253f, + 0.244467903f, -0.969657385f, + 0.245955050f, -0.969281235f, + 0.247441619f, -0.968902805f, + 0.248927606f, -0.968522094f, + 0.250413007f, -0.968139105f, + 0.251897818f, -0.967753837f, + 0.253382037f, -0.967366292f, + 0.254865660f, -0.966976471f, + 0.256348682f, -0.966584374f, + 0.257831102f, -0.966190003f, + 0.259312915f, -0.965793359f, + 0.260794118f, -0.965394442f, + 0.262274707f, -0.964993253f, + 0.263754679f, -0.964589793f, + 0.265234030f, -0.964184064f, + 0.266712757f, -0.963776066f, + 0.268190857f, -0.963365800f, + 0.269668326f, -0.962953267f, + 0.271145160f, -0.962538468f, + 0.272621355f, -0.962121404f, + 0.274096910f, -0.961702077f, + 0.275571819f, -0.961280486f, + 0.277046080f, -0.960856633f, + 0.278519689f, -0.960430519f, + 0.279992643f, -0.960002146f, + 0.281464938f, -0.959571513f, + 0.282936570f, -0.959138622f, + 0.284407537f, -0.958703475f, + 0.285877835f, -0.958266071f, + 0.287347460f, -0.957826413f, + 0.288816408f, -0.957384501f, + 0.290284677f, -0.956940336f, + 0.291752263f, -0.956493919f, + 0.293219163f, -0.956045251f, + 0.294685372f, -0.955594334f, + 0.296150888f, -0.955141168f, + 0.297615707f, -0.954685755f, + 0.299079826f, -0.954228095f, + 0.300543241f, -0.953768190f, + 0.302005949f, -0.953306040f, + 0.303467947f, -0.952841648f, + 0.304929230f, -0.952375013f, + 0.306389795f, -0.951906137f, + 0.307849640f, -0.951435021f, + 0.309308760f, -0.950961666f, + 0.310767153f, -0.950486074f, + 0.312224814f, -0.950008245f, + 0.313681740f, -0.949528181f, + 0.315137929f, -0.949045882f, + 0.316593376f, -0.948561350f, + 0.318048077f, -0.948074586f, + 0.319502031f, -0.947585591f, + 0.320955232f, -0.947094366f, + 0.322407679f, -0.946600913f, + 0.323859367f, -0.946105232f, + 0.325310292f, -0.945607325f, + 0.326760452f, -0.945107193f, + 0.328209844f, -0.944604837f, + 0.329658463f, -0.944100258f, + 0.331106306f, -0.943593458f, + 0.332553370f, -0.943084437f, + 0.333999651f, -0.942573198f, + 0.335445147f, -0.942059740f, + 0.336889853f, -0.941544065f, + 0.338333767f, -0.941026175f, + 0.339776884f, -0.940506071f, + 0.341219202f, -0.939983753f, + 0.342660717f, -0.939459224f, + 0.344101426f, -0.938932484f, + 0.345541325f, -0.938403534f, + 0.346980411f, -0.937872376f, + 0.348418680f, -0.937339012f, + 0.349856130f, -0.936803442f, + 0.351292756f, -0.936265667f, + 0.352728556f, -0.935725689f, + 0.354163525f, -0.935183510f, + 0.355597662f, -0.934639130f, + 0.357030961f, -0.934092550f, + 0.358463421f, -0.933543773f, + 0.359895037f, -0.932992799f, + 0.361325806f, -0.932439629f, + 0.362755724f, -0.931884266f, + 0.364184790f, -0.931326709f, + 0.365612998f, -0.930766961f, + 0.367040346f, -0.930205023f, + 0.368466830f, -0.929640896f, + 0.369892447f, -0.929074581f, + 0.371317194f, -0.928506080f, + 0.372741067f, -0.927935395f, + 0.374164063f, -0.927362526f, + 0.375586178f, -0.926787474f, + 0.377007410f, -0.926210242f, + 0.378427755f, -0.925630831f, + 0.379847209f, -0.925049241f, + 0.381265769f, -0.924465474f, + 0.382683432f, -0.923879533f, + 0.384100195f, -0.923291417f, + 0.385516054f, -0.922701128f, + 0.386931006f, -0.922108669f, + 0.388345047f, -0.921514039f, + 0.389758174f, -0.920917242f, + 0.391170384f, -0.920318277f, + 0.392581674f, -0.919717146f, + 0.393992040f, -0.919113852f, + 0.395401479f, -0.918508394f, + 0.396809987f, -0.917900776f, + 0.398217562f, -0.917290997f, + 0.399624200f, -0.916679060f, + 0.401029897f, -0.916064966f, + 0.402434651f, -0.915448716f, + 0.403838458f, -0.914830312f, + 0.405241314f, -0.914209756f, + 0.406643217f, -0.913587048f, + 0.408044163f, -0.912962190f, + 0.409444149f, -0.912335185f, + 0.410843171f, -0.911706032f, + 0.412241227f, -0.911074734f, + 0.413638312f, -0.910441292f, + 0.415034424f, -0.909805708f, + 0.416429560f, -0.909167983f, + 0.417823716f, -0.908528119f, + 0.419216888f, -0.907886116f, + 0.420609074f, -0.907241978f, + 0.422000271f, -0.906595705f, + 0.423390474f, -0.905947298f, + 0.424779681f, -0.905296759f, + 0.426167889f, -0.904644091f, + 0.427555093f, -0.903989293f, + 0.428941292f, -0.903332368f, + 0.430326481f, -0.902673318f, + 0.431710658f, -0.902012144f, + 0.433093819f, -0.901348847f, + 0.434475961f, -0.900683429f, + 0.435857080f, -0.900015892f, + 0.437237174f, -0.899346237f, + 0.438616239f, -0.898674466f, + 0.439994271f, -0.898000580f, + 0.441371269f, -0.897324581f, + 0.442747228f, -0.896646470f, + 0.444122145f, -0.895966250f, + 0.445496017f, -0.895283921f, + 0.446868840f, -0.894599486f, + 0.448240612f, -0.893912945f, + 0.449611330f, -0.893224301f, + 0.450980989f, -0.892533555f, + 0.452349587f, -0.891840709f, + 0.453717121f, -0.891145765f, + 0.455083587f, -0.890448723f, + 0.456448982f, -0.889749586f, + 0.457813304f, -0.889048356f, + 0.459176548f, -0.888345033f, + 0.460538711f, -0.887639620f, + 0.461899791f, -0.886932119f, + 0.463259784f, -0.886222530f, + 0.464618686f, -0.885510856f, + 0.465976496f, -0.884797098f, + 0.467333209f, -0.884081259f, + 0.468688822f, -0.883363339f, + 0.470043332f, -0.882643340f, + 0.471396737f, -0.881921264f, + 0.472749032f, -0.881197113f, + 0.474100215f, -0.880470889f, + 0.475450282f, -0.879742593f, + 0.476799230f, -0.879012226f, + 0.478147056f, -0.878279792f, + 0.479493758f, -0.877545290f, + 0.480839331f, -0.876808724f, + 0.482183772f, -0.876070094f, + 0.483527079f, -0.875329403f, + 0.484869248f, -0.874586652f, + 0.486210276f, -0.873841843f, + 0.487550160f, -0.873094978f, + 0.488888897f, -0.872346059f, + 0.490226483f, -0.871595087f, + 0.491562916f, -0.870842063f, + 0.492898192f, -0.870086991f, + 0.494232309f, -0.869329871f, + 0.495565262f, -0.868570706f, + 0.496897049f, -0.867809497f, + 0.498227667f, -0.867046246f, + 0.499557113f, -0.866280954f, + 0.500885383f, -0.865513624f, + 0.502212474f, -0.864744258f, + 0.503538384f, -0.863972856f, + 0.504863109f, -0.863199422f, + 0.506186645f, -0.862423956f, + 0.507508991f, -0.861646461f, + 0.508830143f, -0.860866939f, + 0.510150097f, -0.860085390f, + 0.511468850f, -0.859301818f, + 0.512786401f, -0.858516224f, + 0.514102744f, -0.857728610f, + 0.515417878f, -0.856938977f, + 0.516731799f, -0.856147328f, + 0.518044504f, -0.855353665f, + 0.519355990f, -0.854557988f, + 0.520666254f, -0.853760301f, + 0.521975293f, -0.852960605f, + 0.523283103f, -0.852158902f, + 0.524589683f, -0.851355193f, + 0.525895027f, -0.850549481f, + 0.527199135f, -0.849741768f, + 0.528502002f, -0.848932055f, + 0.529803625f, -0.848120345f, + 0.531104001f, -0.847306639f, + 0.532403128f, -0.846490939f, + 0.533701002f, -0.845673247f, + 0.534997620f, -0.844853565f, + 0.536292979f, -0.844031895f, + 0.537587076f, -0.843208240f, + 0.538879909f, -0.842382600f, + 0.540171473f, -0.841554977f, + 0.541461766f, -0.840725375f, + 0.542750785f, -0.839893794f, + 0.544038527f, -0.839060237f, + 0.545324988f, -0.838224706f, + 0.546610167f, -0.837387202f, + 0.547894059f, -0.836547727f, + 0.549176662f, -0.835706284f, + 0.550457973f, -0.834862875f, + 0.551737988f, -0.834017501f, + 0.553016706f, -0.833170165f, + 0.554294121f, -0.832320868f, + 0.555570233f, -0.831469612f, + 0.556845037f, -0.830616400f, + 0.558118531f, -0.829761234f, + 0.559390712f, -0.828904115f, + 0.560661576f, -0.828045045f, + 0.561931121f, -0.827184027f, + 0.563199344f, -0.826321063f, + 0.564466242f, -0.825456154f, + 0.565731811f, -0.824589303f, + 0.566996049f, -0.823720511f, + 0.568258953f, -0.822849781f, + 0.569520519f, -0.821977115f, + 0.570780746f, -0.821102515f, + 0.572039629f, -0.820225983f, + 0.573297167f, -0.819347520f, + 0.574553355f, -0.818467130f, + 0.575808191f, -0.817584813f, + 0.577061673f, -0.816700573f, + 0.578313796f, -0.815814411f, + 0.579564559f, -0.814926329f, + 0.580813958f, -0.814036330f, + 0.582061990f, -0.813144415f, + 0.583308653f, -0.812250587f, + 0.584553943f, -0.811354847f, + 0.585797857f, -0.810457198f, + 0.587040394f, -0.809557642f, + 0.588281548f, -0.808656182f, + 0.589521319f, -0.807752818f, + 0.590759702f, -0.806847554f, + 0.591996695f, -0.805940391f, + 0.593232295f, -0.805031331f, + 0.594466499f, -0.804120377f, + 0.595699304f, -0.803207531f, + 0.596930708f, -0.802292796f, + 0.598160707f, -0.801376172f, + 0.599389298f, -0.800457662f, + 0.600616479f, -0.799537269f, + 0.601842247f, -0.798614995f, + 0.603066599f, -0.797690841f, + 0.604289531f, -0.796764810f, + 0.605511041f, -0.795836905f, + 0.606731127f, -0.794907126f, + 0.607949785f, -0.793975478f, + 0.609167012f, -0.793041960f, + 0.610382806f, -0.792106577f, + 0.611597164f, -0.791169330f, + 0.612810082f, -0.790230221f, + 0.614021559f, -0.789289253f, + 0.615231591f, -0.788346428f, + 0.616440175f, -0.787401747f, + 0.617647308f, -0.786455214f, + 0.618852988f, -0.785506830f, + 0.620057212f, -0.784556597f, + 0.621259977f, -0.783604519f, + 0.622461279f, -0.782650596f, + 0.623661118f, -0.781694832f, + 0.624859488f, -0.780737229f, + 0.626056388f, -0.779777788f, + 0.627251815f, -0.778816512f, + 0.628445767f, -0.777853404f, + 0.629638239f, -0.776888466f, + 0.630829230f, -0.775921699f, + 0.632018736f, -0.774953107f, + 0.633206755f, -0.773982691f, + 0.634393284f, -0.773010453f, + 0.635578320f, -0.772036397f, + 0.636761861f, -0.771060524f, + 0.637943904f, -0.770082837f, + 0.639124445f, -0.769103338f, + 0.640303482f, -0.768122029f, + 0.641481013f, -0.767138912f, + 0.642657034f, -0.766153990f, + 0.643831543f, -0.765167266f, + 0.645004537f, -0.764178741f, + 0.646176013f, -0.763188417f, + 0.647345969f, -0.762196298f, + 0.648514401f, -0.761202385f, + 0.649681307f, -0.760206682f, + 0.650846685f, -0.759209189f, + 0.652010531f, -0.758209910f, + 0.653172843f, -0.757208847f, + 0.654333618f, -0.756206001f, + 0.655492853f, -0.755201377f, + 0.656650546f, -0.754194975f, + 0.657806693f, -0.753186799f, + 0.658961293f, -0.752176850f, + 0.660114342f, -0.751165132f, + 0.661265838f, -0.750151646f, + 0.662415778f, -0.749136395f, + 0.663564159f, -0.748119380f, + 0.664710978f, -0.747100606f, + 0.665856234f, -0.746080074f, + 0.666999922f, -0.745057785f, + 0.668142041f, -0.744033744f, + 0.669282588f, -0.743007952f, + 0.670421560f, -0.741980412f, + 0.671558955f, -0.740951125f, + 0.672694769f, -0.739920095f, + 0.673829000f, -0.738887324f, + 0.674961646f, -0.737852815f, + 0.676092704f, -0.736816569f, + 0.677222170f, -0.735778589f, + 0.678350043f, -0.734738878f, + 0.679476320f, -0.733697438f, + 0.680600998f, -0.732654272f, + 0.681724074f, -0.731609381f, + 0.682845546f, -0.730562769f, + 0.683965412f, -0.729514438f, + 0.685083668f, -0.728464390f, + 0.686200312f, -0.727412629f, + 0.687315341f, -0.726359155f, + 0.688428753f, -0.725303972f, + 0.689540545f, -0.724247083f, + 0.690650714f, -0.723188489f, + 0.691759258f, -0.722128194f, + 0.692866175f, -0.721066199f, + 0.693971461f, -0.720002508f, + 0.695075114f, -0.718937122f, + 0.696177131f, -0.717870045f, + 0.697277511f, -0.716801279f, + 0.698376249f, -0.715730825f, + 0.699473345f, -0.714658688f, + 0.700568794f, -0.713584869f, + 0.701662595f, -0.712509371f, + 0.702754744f, -0.711432196f, + 0.703845241f, -0.710353347f, + 0.704934080f, -0.709272826f, + 0.706021261f, -0.708190637f, + 0.707106781f, -0.707106781f, + 0.708190637f, -0.706021261f, + 0.709272826f, -0.704934080f, + 0.710353347f, -0.703845241f, + 0.711432196f, -0.702754744f, + 0.712509371f, -0.701662595f, + 0.713584869f, -0.700568794f, + 0.714658688f, -0.699473345f, + 0.715730825f, -0.698376249f, + 0.716801279f, -0.697277511f, + 0.717870045f, -0.696177131f, + 0.718937122f, -0.695075114f, + 0.720002508f, -0.693971461f, + 0.721066199f, -0.692866175f, + 0.722128194f, -0.691759258f, + 0.723188489f, -0.690650714f, + 0.724247083f, -0.689540545f, + 0.725303972f, -0.688428753f, + 0.726359155f, -0.687315341f, + 0.727412629f, -0.686200312f, + 0.728464390f, -0.685083668f, + 0.729514438f, -0.683965412f, + 0.730562769f, -0.682845546f, + 0.731609381f, -0.681724074f, + 0.732654272f, -0.680600998f, + 0.733697438f, -0.679476320f, + 0.734738878f, -0.678350043f, + 0.735778589f, -0.677222170f, + 0.736816569f, -0.676092704f, + 0.737852815f, -0.674961646f, + 0.738887324f, -0.673829000f, + 0.739920095f, -0.672694769f, + 0.740951125f, -0.671558955f, + 0.741980412f, -0.670421560f, + 0.743007952f, -0.669282588f, + 0.744033744f, -0.668142041f, + 0.745057785f, -0.666999922f, + 0.746080074f, -0.665856234f, + 0.747100606f, -0.664710978f, + 0.748119380f, -0.663564159f, + 0.749136395f, -0.662415778f, + 0.750151646f, -0.661265838f, + 0.751165132f, -0.660114342f, + 0.752176850f, -0.658961293f, + 0.753186799f, -0.657806693f, + 0.754194975f, -0.656650546f, + 0.755201377f, -0.655492853f, + 0.756206001f, -0.654333618f, + 0.757208847f, -0.653172843f, + 0.758209910f, -0.652010531f, + 0.759209189f, -0.650846685f, + 0.760206682f, -0.649681307f, + 0.761202385f, -0.648514401f, + 0.762196298f, -0.647345969f, + 0.763188417f, -0.646176013f, + 0.764178741f, -0.645004537f, + 0.765167266f, -0.643831543f, + 0.766153990f, -0.642657034f, + 0.767138912f, -0.641481013f, + 0.768122029f, -0.640303482f, + 0.769103338f, -0.639124445f, + 0.770082837f, -0.637943904f, + 0.771060524f, -0.636761861f, + 0.772036397f, -0.635578320f, + 0.773010453f, -0.634393284f, + 0.773982691f, -0.633206755f, + 0.774953107f, -0.632018736f, + 0.775921699f, -0.630829230f, + 0.776888466f, -0.629638239f, + 0.777853404f, -0.628445767f, + 0.778816512f, -0.627251815f, + 0.779777788f, -0.626056388f, + 0.780737229f, -0.624859488f, + 0.781694832f, -0.623661118f, + 0.782650596f, -0.622461279f, + 0.783604519f, -0.621259977f, + 0.784556597f, -0.620057212f, + 0.785506830f, -0.618852988f, + 0.786455214f, -0.617647308f, + 0.787401747f, -0.616440175f, + 0.788346428f, -0.615231591f, + 0.789289253f, -0.614021559f, + 0.790230221f, -0.612810082f, + 0.791169330f, -0.611597164f, + 0.792106577f, -0.610382806f, + 0.793041960f, -0.609167012f, + 0.793975478f, -0.607949785f, + 0.794907126f, -0.606731127f, + 0.795836905f, -0.605511041f, + 0.796764810f, -0.604289531f, + 0.797690841f, -0.603066599f, + 0.798614995f, -0.601842247f, + 0.799537269f, -0.600616479f, + 0.800457662f, -0.599389298f, + 0.801376172f, -0.598160707f, + 0.802292796f, -0.596930708f, + 0.803207531f, -0.595699304f, + 0.804120377f, -0.594466499f, + 0.805031331f, -0.593232295f, + 0.805940391f, -0.591996695f, + 0.806847554f, -0.590759702f, + 0.807752818f, -0.589521319f, + 0.808656182f, -0.588281548f, + 0.809557642f, -0.587040394f, + 0.810457198f, -0.585797857f, + 0.811354847f, -0.584553943f, + 0.812250587f, -0.583308653f, + 0.813144415f, -0.582061990f, + 0.814036330f, -0.580813958f, + 0.814926329f, -0.579564559f, + 0.815814411f, -0.578313796f, + 0.816700573f, -0.577061673f, + 0.817584813f, -0.575808191f, + 0.818467130f, -0.574553355f, + 0.819347520f, -0.573297167f, + 0.820225983f, -0.572039629f, + 0.821102515f, -0.570780746f, + 0.821977115f, -0.569520519f, + 0.822849781f, -0.568258953f, + 0.823720511f, -0.566996049f, + 0.824589303f, -0.565731811f, + 0.825456154f, -0.564466242f, + 0.826321063f, -0.563199344f, + 0.827184027f, -0.561931121f, + 0.828045045f, -0.560661576f, + 0.828904115f, -0.559390712f, + 0.829761234f, -0.558118531f, + 0.830616400f, -0.556845037f, + 0.831469612f, -0.555570233f, + 0.832320868f, -0.554294121f, + 0.833170165f, -0.553016706f, + 0.834017501f, -0.551737988f, + 0.834862875f, -0.550457973f, + 0.835706284f, -0.549176662f, + 0.836547727f, -0.547894059f, + 0.837387202f, -0.546610167f, + 0.838224706f, -0.545324988f, + 0.839060237f, -0.544038527f, + 0.839893794f, -0.542750785f, + 0.840725375f, -0.541461766f, + 0.841554977f, -0.540171473f, + 0.842382600f, -0.538879909f, + 0.843208240f, -0.537587076f, + 0.844031895f, -0.536292979f, + 0.844853565f, -0.534997620f, + 0.845673247f, -0.533701002f, + 0.846490939f, -0.532403128f, + 0.847306639f, -0.531104001f, + 0.848120345f, -0.529803625f, + 0.848932055f, -0.528502002f, + 0.849741768f, -0.527199135f, + 0.850549481f, -0.525895027f, + 0.851355193f, -0.524589683f, + 0.852158902f, -0.523283103f, + 0.852960605f, -0.521975293f, + 0.853760301f, -0.520666254f, + 0.854557988f, -0.519355990f, + 0.855353665f, -0.518044504f, + 0.856147328f, -0.516731799f, + 0.856938977f, -0.515417878f, + 0.857728610f, -0.514102744f, + 0.858516224f, -0.512786401f, + 0.859301818f, -0.511468850f, + 0.860085390f, -0.510150097f, + 0.860866939f, -0.508830143f, + 0.861646461f, -0.507508991f, + 0.862423956f, -0.506186645f, + 0.863199422f, -0.504863109f, + 0.863972856f, -0.503538384f, + 0.864744258f, -0.502212474f, + 0.865513624f, -0.500885383f, + 0.866280954f, -0.499557113f, + 0.867046246f, -0.498227667f, + 0.867809497f, -0.496897049f, + 0.868570706f, -0.495565262f, + 0.869329871f, -0.494232309f, + 0.870086991f, -0.492898192f, + 0.870842063f, -0.491562916f, + 0.871595087f, -0.490226483f, + 0.872346059f, -0.488888897f, + 0.873094978f, -0.487550160f, + 0.873841843f, -0.486210276f, + 0.874586652f, -0.484869248f, + 0.875329403f, -0.483527079f, + 0.876070094f, -0.482183772f, + 0.876808724f, -0.480839331f, + 0.877545290f, -0.479493758f, + 0.878279792f, -0.478147056f, + 0.879012226f, -0.476799230f, + 0.879742593f, -0.475450282f, + 0.880470889f, -0.474100215f, + 0.881197113f, -0.472749032f, + 0.881921264f, -0.471396737f, + 0.882643340f, -0.470043332f, + 0.883363339f, -0.468688822f, + 0.884081259f, -0.467333209f, + 0.884797098f, -0.465976496f, + 0.885510856f, -0.464618686f, + 0.886222530f, -0.463259784f, + 0.886932119f, -0.461899791f, + 0.887639620f, -0.460538711f, + 0.888345033f, -0.459176548f, + 0.889048356f, -0.457813304f, + 0.889749586f, -0.456448982f, + 0.890448723f, -0.455083587f, + 0.891145765f, -0.453717121f, + 0.891840709f, -0.452349587f, + 0.892533555f, -0.450980989f, + 0.893224301f, -0.449611330f, + 0.893912945f, -0.448240612f, + 0.894599486f, -0.446868840f, + 0.895283921f, -0.445496017f, + 0.895966250f, -0.444122145f, + 0.896646470f, -0.442747228f, + 0.897324581f, -0.441371269f, + 0.898000580f, -0.439994271f, + 0.898674466f, -0.438616239f, + 0.899346237f, -0.437237174f, + 0.900015892f, -0.435857080f, + 0.900683429f, -0.434475961f, + 0.901348847f, -0.433093819f, + 0.902012144f, -0.431710658f, + 0.902673318f, -0.430326481f, + 0.903332368f, -0.428941292f, + 0.903989293f, -0.427555093f, + 0.904644091f, -0.426167889f, + 0.905296759f, -0.424779681f, + 0.905947298f, -0.423390474f, + 0.906595705f, -0.422000271f, + 0.907241978f, -0.420609074f, + 0.907886116f, -0.419216888f, + 0.908528119f, -0.417823716f, + 0.909167983f, -0.416429560f, + 0.909805708f, -0.415034424f, + 0.910441292f, -0.413638312f, + 0.911074734f, -0.412241227f, + 0.911706032f, -0.410843171f, + 0.912335185f, -0.409444149f, + 0.912962190f, -0.408044163f, + 0.913587048f, -0.406643217f, + 0.914209756f, -0.405241314f, + 0.914830312f, -0.403838458f, + 0.915448716f, -0.402434651f, + 0.916064966f, -0.401029897f, + 0.916679060f, -0.399624200f, + 0.917290997f, -0.398217562f, + 0.917900776f, -0.396809987f, + 0.918508394f, -0.395401479f, + 0.919113852f, -0.393992040f, + 0.919717146f, -0.392581674f, + 0.920318277f, -0.391170384f, + 0.920917242f, -0.389758174f, + 0.921514039f, -0.388345047f, + 0.922108669f, -0.386931006f, + 0.922701128f, -0.385516054f, + 0.923291417f, -0.384100195f, + 0.923879533f, -0.382683432f, + 0.924465474f, -0.381265769f, + 0.925049241f, -0.379847209f, + 0.925630831f, -0.378427755f, + 0.926210242f, -0.377007410f, + 0.926787474f, -0.375586178f, + 0.927362526f, -0.374164063f, + 0.927935395f, -0.372741067f, + 0.928506080f, -0.371317194f, + 0.929074581f, -0.369892447f, + 0.929640896f, -0.368466830f, + 0.930205023f, -0.367040346f, + 0.930766961f, -0.365612998f, + 0.931326709f, -0.364184790f, + 0.931884266f, -0.362755724f, + 0.932439629f, -0.361325806f, + 0.932992799f, -0.359895037f, + 0.933543773f, -0.358463421f, + 0.934092550f, -0.357030961f, + 0.934639130f, -0.355597662f, + 0.935183510f, -0.354163525f, + 0.935725689f, -0.352728556f, + 0.936265667f, -0.351292756f, + 0.936803442f, -0.349856130f, + 0.937339012f, -0.348418680f, + 0.937872376f, -0.346980411f, + 0.938403534f, -0.345541325f, + 0.938932484f, -0.344101426f, + 0.939459224f, -0.342660717f, + 0.939983753f, -0.341219202f, + 0.940506071f, -0.339776884f, + 0.941026175f, -0.338333767f, + 0.941544065f, -0.336889853f, + 0.942059740f, -0.335445147f, + 0.942573198f, -0.333999651f, + 0.943084437f, -0.332553370f, + 0.943593458f, -0.331106306f, + 0.944100258f, -0.329658463f, + 0.944604837f, -0.328209844f, + 0.945107193f, -0.326760452f, + 0.945607325f, -0.325310292f, + 0.946105232f, -0.323859367f, + 0.946600913f, -0.322407679f, + 0.947094366f, -0.320955232f, + 0.947585591f, -0.319502031f, + 0.948074586f, -0.318048077f, + 0.948561350f, -0.316593376f, + 0.949045882f, -0.315137929f, + 0.949528181f, -0.313681740f, + 0.950008245f, -0.312224814f, + 0.950486074f, -0.310767153f, + 0.950961666f, -0.309308760f, + 0.951435021f, -0.307849640f, + 0.951906137f, -0.306389795f, + 0.952375013f, -0.304929230f, + 0.952841648f, -0.303467947f, + 0.953306040f, -0.302005949f, + 0.953768190f, -0.300543241f, + 0.954228095f, -0.299079826f, + 0.954685755f, -0.297615707f, + 0.955141168f, -0.296150888f, + 0.955594334f, -0.294685372f, + 0.956045251f, -0.293219163f, + 0.956493919f, -0.291752263f, + 0.956940336f, -0.290284677f, + 0.957384501f, -0.288816408f, + 0.957826413f, -0.287347460f, + 0.958266071f, -0.285877835f, + 0.958703475f, -0.284407537f, + 0.959138622f, -0.282936570f, + 0.959571513f, -0.281464938f, + 0.960002146f, -0.279992643f, + 0.960430519f, -0.278519689f, + 0.960856633f, -0.277046080f, + 0.961280486f, -0.275571819f, + 0.961702077f, -0.274096910f, + 0.962121404f, -0.272621355f, + 0.962538468f, -0.271145160f, + 0.962953267f, -0.269668326f, + 0.963365800f, -0.268190857f, + 0.963776066f, -0.266712757f, + 0.964184064f, -0.265234030f, + 0.964589793f, -0.263754679f, + 0.964993253f, -0.262274707f, + 0.965394442f, -0.260794118f, + 0.965793359f, -0.259312915f, + 0.966190003f, -0.257831102f, + 0.966584374f, -0.256348682f, + 0.966976471f, -0.254865660f, + 0.967366292f, -0.253382037f, + 0.967753837f, -0.251897818f, + 0.968139105f, -0.250413007f, + 0.968522094f, -0.248927606f, + 0.968902805f, -0.247441619f, + 0.969281235f, -0.245955050f, + 0.969657385f, -0.244467903f, + 0.970031253f, -0.242980180f, + 0.970402839f, -0.241491885f, + 0.970772141f, -0.240003022f, + 0.971139158f, -0.238513595f, + 0.971503891f, -0.237023606f, + 0.971866337f, -0.235533059f, + 0.972226497f, -0.234041959f, + 0.972584369f, -0.232550307f, + 0.972939952f, -0.231058108f, + 0.973293246f, -0.229565366f, + 0.973644250f, -0.228072083f, + 0.973992962f, -0.226578264f, + 0.974339383f, -0.225083911f, + 0.974683511f, -0.223589029f, + 0.975025345f, -0.222093621f, + 0.975364885f, -0.220597690f, + 0.975702130f, -0.219101240f, + 0.976037079f, -0.217604275f, + 0.976369731f, -0.216106797f, + 0.976700086f, -0.214608811f, + 0.977028143f, -0.213110320f, + 0.977353900f, -0.211611327f, + 0.977677358f, -0.210111837f, + 0.977998515f, -0.208611852f, + 0.978317371f, -0.207111376f, + 0.978633924f, -0.205610413f, + 0.978948175f, -0.204108966f, + 0.979260123f, -0.202607039f, + 0.979569766f, -0.201104635f, + 0.979877104f, -0.199601758f, + 0.980182136f, -0.198098411f, + 0.980484862f, -0.196594598f, + 0.980785280f, -0.195090322f, + 0.981083391f, -0.193585587f, + 0.981379193f, -0.192080397f, + 0.981672686f, -0.190574755f, + 0.981963869f, -0.189068664f, + 0.982252741f, -0.187562129f, + 0.982539302f, -0.186055152f, + 0.982823551f, -0.184547737f, + 0.983105487f, -0.183039888f, + 0.983385110f, -0.181531608f, + 0.983662419f, -0.180022901f, + 0.983937413f, -0.178513771f, + 0.984210092f, -0.177004220f, + 0.984480455f, -0.175494253f, + 0.984748502f, -0.173983873f, + 0.985014231f, -0.172473084f, + 0.985277642f, -0.170961889f, + 0.985538735f, -0.169450291f, + 0.985797509f, -0.167938295f, + 0.986053963f, -0.166425904f, + 0.986308097f, -0.164913120f, + 0.986559910f, -0.163399949f, + 0.986809402f, -0.161886394f, + 0.987056571f, -0.160372457f, + 0.987301418f, -0.158858143f, + 0.987543942f, -0.157343456f, + 0.987784142f, -0.155828398f, + 0.988022017f, -0.154312973f, + 0.988257568f, -0.152797185f, + 0.988490793f, -0.151281038f, + 0.988721692f, -0.149764535f, + 0.988950265f, -0.148247679f, + 0.989176510f, -0.146730474f, + 0.989400428f, -0.145212925f, + 0.989622017f, -0.143695033f, + 0.989841278f, -0.142176804f, + 0.990058210f, -0.140658239f, + 0.990272812f, -0.139139344f, + 0.990485084f, -0.137620122f, + 0.990695025f, -0.136100575f, + 0.990902635f, -0.134580709f, + 0.991107914f, -0.133060525f, + 0.991310860f, -0.131540029f, + 0.991511473f, -0.130019223f, + 0.991709754f, -0.128498111f, + 0.991905700f, -0.126976696f, + 0.992099313f, -0.125454983f, + 0.992290591f, -0.123932975f, + 0.992479535f, -0.122410675f, + 0.992666142f, -0.120888087f, + 0.992850414f, -0.119365215f, + 0.993032350f, -0.117842062f, + 0.993211949f, -0.116318631f, + 0.993389211f, -0.114794927f, + 0.993564136f, -0.113270952f, + 0.993736722f, -0.111746711f, + 0.993906970f, -0.110222207f, + 0.994074879f, -0.108697444f, + 0.994240449f, -0.107172425f, + 0.994403680f, -0.105647154f, + 0.994564571f, -0.104121634f, + 0.994723121f, -0.102595869f, + 0.994879331f, -0.101069863f, + 0.995033199f, -0.099543619f, + 0.995184727f, -0.098017140f, + 0.995333912f, -0.096490431f, + 0.995480755f, -0.094963495f, + 0.995625256f, -0.093436336f, + 0.995767414f, -0.091908956f, + 0.995907229f, -0.090381361f, + 0.996044701f, -0.088853553f, + 0.996179829f, -0.087325535f, + 0.996312612f, -0.085797312f, + 0.996443051f, -0.084268888f, + 0.996571146f, -0.082740265f, + 0.996696895f, -0.081211447f, + 0.996820299f, -0.079682438f, + 0.996941358f, -0.078153242f, + 0.997060070f, -0.076623861f, + 0.997176437f, -0.075094301f, + 0.997290457f, -0.073564564f, + 0.997402130f, -0.072034653f, + 0.997511456f, -0.070504573f, + 0.997618435f, -0.068974328f, + 0.997723067f, -0.067443920f, + 0.997825350f, -0.065913353f, + 0.997925286f, -0.064382631f, + 0.998022874f, -0.062851758f, + 0.998118113f, -0.061320736f, + 0.998211003f, -0.059789571f, + 0.998301545f, -0.058258265f, + 0.998389737f, -0.056726821f, + 0.998475581f, -0.055195244f, + 0.998559074f, -0.053663538f, + 0.998640218f, -0.052131705f, + 0.998719012f, -0.050599749f, + 0.998795456f, -0.049067674f, + 0.998869550f, -0.047535484f, + 0.998941293f, -0.046003182f, + 0.999010686f, -0.044470772f, + 0.999077728f, -0.042938257f, + 0.999142419f, -0.041405641f, + 0.999204759f, -0.039872928f, + 0.999264747f, -0.038340120f, + 0.999322385f, -0.036807223f, + 0.999377670f, -0.035274239f, + 0.999430605f, -0.033741172f, + 0.999481187f, -0.032208025f, + 0.999529418f, -0.030674803f, + 0.999575296f, -0.029141509f, + 0.999618822f, -0.027608146f, + 0.999659997f, -0.026074718f, + 0.999698819f, -0.024541229f, + 0.999735288f, -0.023007681f, + 0.999769405f, -0.021474080f, + 0.999801170f, -0.019940429f, + 0.999830582f, -0.018406730f, + 0.999857641f, -0.016872988f, + 0.999882347f, -0.015339206f, + 0.999904701f, -0.013805389f, + 0.999924702f, -0.012271538f, + 0.999942350f, -0.010737659f, + 0.999957645f, -0.009203755f, + 0.999970586f, -0.007669829f, + 0.999981175f, -0.006135885f, + 0.999989411f, -0.004601926f, + 0.999995294f, -0.003067957f, + 0.999998823f, -0.001533980f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + +/** + @brief Q31 Twiddle factors Table +*/ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par +
 for(i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 16, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_16_q31[24] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, + (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, + (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, + (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, + (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xCF043AB2, (q31_t)0x89BE50C3 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par +
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 32, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_32_q31[48] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, + (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, + (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x471CECE6, (q31_t)0x6A6D98A4, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, + (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, + (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xB8E31319, (q31_t)0x6A6D98A4, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, + (q31_t)0x9592675B, (q31_t)0x471CECE6, + (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, + (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x8275A0C0, (q31_t)0xE70747C3, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, + (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xB8E31319, (q31_t)0x9592675B, + (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xE70747C3, (q31_t)0x8275A0C0 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par +
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 64, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_64_q31[96] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7641AF3C, + (q31_t)0x30FBC54D, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x62F201AC, + (q31_t)0x5133CC94, (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x471CECE6, + (q31_t)0x6A6D98A4, (q31_t)0x3C56BA70, (q31_t)0x70E2CBC6, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x25280C5D, + (q31_t)0x7A7D055B, (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x00000000, + (q31_t)0x7FFFFFFF, (q31_t)0xF3742CA1, (q31_t)0x7F62368F, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xDAD7F3A2, + (q31_t)0x7A7D055B, (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xB8E31319, + (q31_t)0x6A6D98A4, (q31_t)0xAECC336B, (q31_t)0x62F201AC, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0x9D0DFE53, + (q31_t)0x5133CC94, (q31_t)0x9592675B, (q31_t)0x471CECE6, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x89BE50C3, + (q31_t)0x30FBC54D, (q31_t)0x8582FAA4, (q31_t)0x25280C5D, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x809DC970, + (q31_t)0x0C8BD35E, (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x8275A0C0, + (q31_t)0xE70747C3, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8F1D343A, + (q31_t)0xC3A9458F, (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0xA57D8666, + (q31_t)0xA57D8666, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xC3A9458F, + (q31_t)0x8F1D343A, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xE70747C3, + (q31_t)0x8275A0C0, (q31_t)0xF3742CA1, (q31_t)0x809DC970 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par +
for (i = 0; i < 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 128, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_128_q31[192] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FD8878D, + (q31_t)0x0647D97C, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7D8A5F3F, + (q31_t)0x18F8B83C, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x78848413, + (q31_t)0x2B1F34EB, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x70E2CBC6, + (q31_t)0x3C56BA70, (q31_t)0x6DCA0D14, (q31_t)0x41CE1E64, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x66CF811F, + (q31_t)0x4C3FDFF3, (q31_t)0x62F201AC, (q31_t)0x5133CC94, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5A82799A, + (q31_t)0x5A82799A, (q31_t)0x55F5A4D2, (q31_t)0x5ED77C89, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x4C3FDFF3, + (q31_t)0x66CF811F, (q31_t)0x471CECE6, (q31_t)0x6A6D98A4, + (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x3C56BA70, + (q31_t)0x70E2CBC6, (q31_t)0x36BA2013, (q31_t)0x73B5EBD0, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x2B1F34EB, + (q31_t)0x78848413, (q31_t)0x25280C5D, (q31_t)0x7A7D055B, + (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x18F8B83C, + (q31_t)0x7D8A5F3F, (q31_t)0x12C8106E, (q31_t)0x7E9D55FC, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x0647D97C, + (q31_t)0x7FD8878D, (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF3742CA1, + (q31_t)0x7F62368F, (q31_t)0xED37EF91, (q31_t)0x7E9D55FC, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE0E60684, + (q31_t)0x7C29FBEE, (q31_t)0xDAD7F3A2, (q31_t)0x7A7D055B, + (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xCF043AB2, + (q31_t)0x7641AF3C, (q31_t)0xC945DFEC, (q31_t)0x73B5EBD0, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xBE31E19B, + (q31_t)0x6DCA0D14, (q31_t)0xB8E31319, (q31_t)0x6A6D98A4, + (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xAECC336B, + (q31_t)0x62F201AC, (q31_t)0xAA0A5B2D, (q31_t)0x5ED77C89, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA1288376, + (q31_t)0x55F5A4D2, (q31_t)0x9D0DFE53, (q31_t)0x5133CC94, + (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9592675B, + (q31_t)0x471CECE6, (q31_t)0x9235F2EB, (q31_t)0x41CE1E64, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8C4A142F, + (q31_t)0x36BA2013, (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x8582FAA4, + (q31_t)0x25280C5D, (q31_t)0x83D60411, (q31_t)0x1F19F97B, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x8162AA03, + (q31_t)0x12C8106E, (q31_t)0x809DC970, (q31_t)0x0C8BD35E, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x80000000, + (q31_t)0x00000000, (q31_t)0x80277872, (q31_t)0xF9B82683, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x8162AA03, + (q31_t)0xED37EF91, (q31_t)0x8275A0C0, (q31_t)0xE70747C3, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x8582FAA4, + (q31_t)0xDAD7F3A2, (q31_t)0x877B7BEC, (q31_t)0xD4E0CB14, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8C4A142F, + (q31_t)0xC945DFEC, (q31_t)0x8F1D343A, (q31_t)0xC3A9458F, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x9592675B, + (q31_t)0xB8E31319, (q31_t)0x99307EE0, (q31_t)0xB3C0200C, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0xA1288376, + (q31_t)0xAA0A5B2D, (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAECC336B, + (q31_t)0x9D0DFE53, (q31_t)0xB3C0200C, (q31_t)0x99307EE0, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBE31E19B, + (q31_t)0x9235F2EB, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCF043AB2, + (q31_t)0x89BE50C3, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xE0E60684, + (q31_t)0x83D60411, (q31_t)0xE70747C3, (q31_t)0x8275A0C0, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xF3742CA1, + (q31_t)0x809DC970, (q31_t)0xF9B82683, (q31_t)0x80277872 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par +
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 256, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + + */ +const q31_t twiddleCoef_256_q31[384] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FF62182, + (q31_t)0x03242ABF, (q31_t)0x7FD8878D, (q31_t)0x0647D97C, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7F0991C3, (q31_t)0x0FAB272B, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E1D93E9, + (q31_t)0x15E21444, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7C29FBEE, + (q31_t)0x1F19F97B, (q31_t)0x7B5D039D, (q31_t)0x2223A4C5, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x798A23B1, + (q31_t)0x2826B928, (q31_t)0x78848413, (q31_t)0x2B1F34EB, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x7641AF3C, + (q31_t)0x30FBC54D, (q31_t)0x7504D345, (q31_t)0x33DEF287, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x72552C84, + (q31_t)0x398CDD32, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6DCA0D14, + (q31_t)0x41CE1E64, (q31_t)0x6C242960, (q31_t)0x447ACD50, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x68A69E81, + (q31_t)0x49B41533, (q31_t)0x66CF811F, (q31_t)0x4C3FDFF3, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x62F201AC, + (q31_t)0x5133CC94, (q31_t)0x60EC3830, (q31_t)0x539B2AEF, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5CB420DF, + (q31_t)0x5842DD54, (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x55F5A4D2, + (q31_t)0x5ED77C89, (q31_t)0x539B2AEF, (q31_t)0x60EC3830, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x4EBFE8A4, + (q31_t)0x64E88926, (q31_t)0x4C3FDFF3, (q31_t)0x66CF811F, + (q31_t)0x49B41533, (q31_t)0x68A69E81, (q31_t)0x471CECE6, + (q31_t)0x6A6D98A4, (q31_t)0x447ACD50, (q31_t)0x6C242960, + (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x3F1749B7, + (q31_t)0x6F5F02B1, (q31_t)0x3C56BA70, (q31_t)0x70E2CBC6, + (q31_t)0x398CDD32, (q31_t)0x72552C84, (q31_t)0x36BA2013, + (q31_t)0x73B5EBD0, (q31_t)0x33DEF287, (q31_t)0x7504D345, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x2E110A62, + (q31_t)0x776C4EDB, (q31_t)0x2B1F34EB, (q31_t)0x78848413, + (q31_t)0x2826B928, (q31_t)0x798A23B1, (q31_t)0x25280C5D, + (q31_t)0x7A7D055B, (q31_t)0x2223A4C5, (q31_t)0x7B5D039D, + (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x1C0B826A, + (q31_t)0x7CE3CEB1, (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x15E21444, (q31_t)0x7E1D93E9, (q31_t)0x12C8106E, + (q31_t)0x7E9D55FC, (q31_t)0x0FAB272B, (q31_t)0x7F0991C3, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x096A9049, + (q31_t)0x7FA736B4, (q31_t)0x0647D97C, (q31_t)0x7FD8878D, + (q31_t)0x03242ABF, (q31_t)0x7FF62182, (q31_t)0x00000000, + (q31_t)0x7FFFFFFF, (q31_t)0xFCDBD541, (q31_t)0x7FF62182, + (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF6956FB6, + (q31_t)0x7FA736B4, (q31_t)0xF3742CA1, (q31_t)0x7F62368F, + (q31_t)0xF054D8D4, (q31_t)0x7F0991C3, (q31_t)0xED37EF91, + (q31_t)0x7E9D55FC, (q31_t)0xEA1DEBBB, (q31_t)0x7E1D93E9, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE3F47D95, + (q31_t)0x7CE3CEB1, (q31_t)0xE0E60684, (q31_t)0x7C29FBEE, + (q31_t)0xDDDC5B3A, (q31_t)0x7B5D039D, (q31_t)0xDAD7F3A2, + (q31_t)0x7A7D055B, (q31_t)0xD7D946D7, (q31_t)0x798A23B1, + (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xD1EEF59E, + (q31_t)0x776C4EDB, (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xCC210D78, (q31_t)0x7504D345, (q31_t)0xC945DFEC, + (q31_t)0x73B5EBD0, (q31_t)0xC67322CD, (q31_t)0x72552C84, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xC0E8B648, + (q31_t)0x6F5F02B1, (q31_t)0xBE31E19B, (q31_t)0x6DCA0D14, + (q31_t)0xBB8532AF, (q31_t)0x6C242960, (q31_t)0xB8E31319, + (q31_t)0x6A6D98A4, (q31_t)0xB64BEACC, (q31_t)0x68A69E81, + (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xB140175B, + (q31_t)0x64E88926, (q31_t)0xAECC336B, (q31_t)0x62F201AC, + (q31_t)0xAC64D510, (q31_t)0x60EC3830, (q31_t)0xAA0A5B2D, + (q31_t)0x5ED77C89, (q31_t)0xA7BD22AB, (q31_t)0x5CB420DF, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA34BDF20, + (q31_t)0x5842DD54, (q31_t)0xA1288376, (q31_t)0x55F5A4D2, + (q31_t)0x9F13C7D0, (q31_t)0x539B2AEF, (q31_t)0x9D0DFE53, + (q31_t)0x5133CC94, (q31_t)0x9B1776D9, (q31_t)0x4EBFE8A4, + (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9759617E, + (q31_t)0x49B41533, (q31_t)0x9592675B, (q31_t)0x471CECE6, + (q31_t)0x93DBD69F, (q31_t)0x447ACD50, (q31_t)0x9235F2EB, + (q31_t)0x41CE1E64, (q31_t)0x90A0FD4E, (q31_t)0x3F1749B7, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8DAAD37B, + (q31_t)0x398CDD32, (q31_t)0x8C4A142F, (q31_t)0x36BA2013, + (q31_t)0x8AFB2CBA, (q31_t)0x33DEF287, (q31_t)0x89BE50C3, + (q31_t)0x30FBC54D, (q31_t)0x8893B124, (q31_t)0x2E110A62, + (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x8675DC4E, + (q31_t)0x2826B928, (q31_t)0x8582FAA4, (q31_t)0x25280C5D, + (q31_t)0x84A2FC62, (q31_t)0x2223A4C5, (q31_t)0x83D60411, + (q31_t)0x1F19F97B, (q31_t)0x831C314E, (q31_t)0x1C0B826A, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x81E26C16, + (q31_t)0x15E21444, (q31_t)0x8162AA03, (q31_t)0x12C8106E, + (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x809DC970, + (q31_t)0x0C8BD35E, (q31_t)0x8058C94C, (q31_t)0x096A9049, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x8009DE7D, + (q31_t)0x03242ABF, (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x80277872, + (q31_t)0xF9B82683, (q31_t)0x8058C94C, (q31_t)0xF6956FB6, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80F66E3C, + (q31_t)0xF054D8D4, (q31_t)0x8162AA03, (q31_t)0xED37EF91, + (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x8275A0C0, + (q31_t)0xE70747C3, (q31_t)0x831C314E, (q31_t)0xE3F47D95, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x84A2FC62, + (q31_t)0xDDDC5B3A, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2, + (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x877B7BEC, + (q31_t)0xD4E0CB14, (q31_t)0x8893B124, (q31_t)0xD1EEF59E, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8AFB2CBA, + (q31_t)0xCC210D78, (q31_t)0x8C4A142F, (q31_t)0xC945DFEC, + (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8F1D343A, + (q31_t)0xC3A9458F, (q31_t)0x90A0FD4E, (q31_t)0xC0E8B648, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x93DBD69F, + (q31_t)0xBB8532AF, (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x99307EE0, + (q31_t)0xB3C0200C, (q31_t)0x9B1776D9, (q31_t)0xB140175B, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9F13C7D0, + (q31_t)0xAC64D510, (q31_t)0xA1288376, (q31_t)0xAA0A5B2D, + (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA57D8666, + (q31_t)0xA57D8666, (q31_t)0xA7BD22AB, (q31_t)0xA34BDF20, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAC64D510, + (q31_t)0x9F13C7D0, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53, + (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB3C0200C, + (q31_t)0x99307EE0, (q31_t)0xB64BEACC, (q31_t)0x9759617E, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBB8532AF, + (q31_t)0x93DBD69F, (q31_t)0xBE31E19B, (q31_t)0x9235F2EB, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC3A9458F, + (q31_t)0x8F1D343A, (q31_t)0xC67322CD, (q31_t)0x8DAAD37B, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCC210D78, + (q31_t)0x8AFB2CBA, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD4E0CB14, + (q31_t)0x877B7BEC, (q31_t)0xD7D946D7, (q31_t)0x8675DC4E, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDDDC5B3A, + (q31_t)0x84A2FC62, (q31_t)0xE0E60684, (q31_t)0x83D60411, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE70747C3, + (q31_t)0x8275A0C0, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xF054D8D4, + (q31_t)0x80F66E3C, (q31_t)0xF3742CA1, (q31_t)0x809DC970, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF9B82683, + (q31_t)0x80277872, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par +
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 512, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + + */ +const q31_t twiddleCoef_512_q31[768] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFD885A, + (q31_t)0x01921D1F, (q31_t)0x7FF62182, (q31_t)0x03242ABF, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FD8878D, + (q31_t)0x0647D97C, (q31_t)0x7FC25596, (q31_t)0x07D95B9E, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F872BF3, + (q31_t)0x0AFB6805, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E, + (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F0991C3, + (q31_t)0x0FAB272B, (q31_t)0x7ED5E5C6, (q31_t)0x1139F0CE, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E5FE493, + (q31_t)0x145576B1, (q31_t)0x7E1D93E9, (q31_t)0x15E21444, + (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7D8A5F3F, + (q31_t)0x18F8B83C, (q31_t)0x7D3980EC, (q31_t)0x1A82A025, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7C894BDD, + (q31_t)0x1D934FE5, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B, + (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7B5D039D, + (q31_t)0x2223A4C5, (q31_t)0x7AEF6323, (q31_t)0x23A6887E, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A05EEAD, + (q31_t)0x26A82185, (q31_t)0x798A23B1, (q31_t)0x2826B928, + (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78848413, + (q31_t)0x2B1F34EB, (q31_t)0x77FAB988, (q31_t)0x2C98FBBA, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x76D94988, + (q31_t)0x2F875262, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x7504D345, + (q31_t)0x33DEF287, (q31_t)0x745F9DD1, (q31_t)0x354D9056, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x7307C3D0, + (q31_t)0x382493B0, (q31_t)0x72552C84, (q31_t)0x398CDD32, + (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x70E2CBC6, + (q31_t)0x3C56BA70, (q31_t)0x70231099, (q31_t)0x3DB832A5, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6E96A99C, + (q31_t)0x4073F21D, (q31_t)0x6DCA0D14, (q31_t)0x41CE1E64, + (q31_t)0x6CF934FB, (q31_t)0x4325C135, (q31_t)0x6C242960, + (q31_t)0x447ACD50, (q31_t)0x6B4AF278, (q31_t)0x45CD358F, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x698C246C, + (q31_t)0x4869E664, (q31_t)0x68A69E81, (q31_t)0x49B41533, + (q31_t)0x67BD0FBC, (q31_t)0x4AFB6C97, (q31_t)0x66CF811F, + (q31_t)0x4C3FDFF3, (q31_t)0x65DDFBD3, (q31_t)0x4D8162C4, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x63EF328F, + (q31_t)0x4FFB654D, (q31_t)0x62F201AC, (q31_t)0x5133CC94, + (q31_t)0x61F1003E, (q31_t)0x5269126E, (q31_t)0x60EC3830, + (q31_t)0x539B2AEF, (q31_t)0x5FE3B38D, (q31_t)0x54CA0A4A, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5DC79D7C, + (q31_t)0x571DEEF9, (q31_t)0x5CB420DF, (q31_t)0x5842DD54, + (q31_t)0x5B9D1153, (q31_t)0x59646497, (q31_t)0x5A82799A, + (q31_t)0x5A82799A, (q31_t)0x59646497, (q31_t)0x5B9D1153, + (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x571DEEF9, + (q31_t)0x5DC79D7C, (q31_t)0x55F5A4D2, (q31_t)0x5ED77C89, + (q31_t)0x54CA0A4A, (q31_t)0x5FE3B38D, (q31_t)0x539B2AEF, + (q31_t)0x60EC3830, (q31_t)0x5269126E, (q31_t)0x61F1003E, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x4FFB654D, + (q31_t)0x63EF328F, (q31_t)0x4EBFE8A4, (q31_t)0x64E88926, + (q31_t)0x4D8162C4, (q31_t)0x65DDFBD3, (q31_t)0x4C3FDFF3, + (q31_t)0x66CF811F, (q31_t)0x4AFB6C97, (q31_t)0x67BD0FBC, + (q31_t)0x49B41533, (q31_t)0x68A69E81, (q31_t)0x4869E664, + (q31_t)0x698C246C, (q31_t)0x471CECE6, (q31_t)0x6A6D98A4, + (q31_t)0x45CD358F, (q31_t)0x6B4AF278, (q31_t)0x447ACD50, + (q31_t)0x6C242960, (q31_t)0x4325C135, (q31_t)0x6CF934FB, + (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x4073F21D, + (q31_t)0x6E96A99C, (q31_t)0x3F1749B7, (q31_t)0x6F5F02B1, + (q31_t)0x3DB832A5, (q31_t)0x70231099, (q31_t)0x3C56BA70, + (q31_t)0x70E2CBC6, (q31_t)0x3AF2EEB7, (q31_t)0x719E2CD2, + (q31_t)0x398CDD32, (q31_t)0x72552C84, (q31_t)0x382493B0, + (q31_t)0x7307C3D0, (q31_t)0x36BA2013, (q31_t)0x73B5EBD0, + (q31_t)0x354D9056, (q31_t)0x745F9DD1, (q31_t)0x33DEF287, + (q31_t)0x7504D345, (q31_t)0x326E54C7, (q31_t)0x75A585CF, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x2F875262, + (q31_t)0x76D94988, (q31_t)0x2E110A62, (q31_t)0x776C4EDB, + (q31_t)0x2C98FBBA, (q31_t)0x77FAB988, (q31_t)0x2B1F34EB, + (q31_t)0x78848413, (q31_t)0x29A3C484, (q31_t)0x7909A92C, + (q31_t)0x2826B928, (q31_t)0x798A23B1, (q31_t)0x26A82185, + (q31_t)0x7A05EEAD, (q31_t)0x25280C5D, (q31_t)0x7A7D055B, + (q31_t)0x23A6887E, (q31_t)0x7AEF6323, (q31_t)0x2223A4C5, + (q31_t)0x7B5D039D, (q31_t)0x209F701C, (q31_t)0x7BC5E28F, + (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x1D934FE5, + (q31_t)0x7C894BDD, (q31_t)0x1C0B826A, (q31_t)0x7CE3CEB1, + (q31_t)0x1A82A025, (q31_t)0x7D3980EC, (q31_t)0x18F8B83C, + (q31_t)0x7D8A5F3F, (q31_t)0x176DD9DE, (q31_t)0x7DD6668E, + (q31_t)0x15E21444, (q31_t)0x7E1D93E9, (q31_t)0x145576B1, + (q31_t)0x7E5FE493, (q31_t)0x12C8106E, (q31_t)0x7E9D55FC, + (q31_t)0x1139F0CE, (q31_t)0x7ED5E5C6, (q31_t)0x0FAB272B, + (q31_t)0x7F0991C3, (q31_t)0x0E1BC2E3, (q31_t)0x7F3857F5, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x0AFB6805, + (q31_t)0x7F872BF3, (q31_t)0x096A9049, (q31_t)0x7FA736B4, + (q31_t)0x07D95B9E, (q31_t)0x7FC25596, (q31_t)0x0647D97C, + (q31_t)0x7FD8878D, (q31_t)0x04B6195D, (q31_t)0x7FE9CBC0, + (q31_t)0x03242ABF, (q31_t)0x7FF62182, (q31_t)0x01921D1F, + (q31_t)0x7FFD885A, (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xFE6DE2E0, (q31_t)0x7FFD885A, (q31_t)0xFCDBD541, + (q31_t)0x7FF62182, (q31_t)0xFB49E6A2, (q31_t)0x7FE9CBC0, + (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF826A461, + (q31_t)0x7FC25596, (q31_t)0xF6956FB6, (q31_t)0x7FA736B4, + (q31_t)0xF50497FA, (q31_t)0x7F872BF3, (q31_t)0xF3742CA1, + (q31_t)0x7F62368F, (q31_t)0xF1E43D1C, (q31_t)0x7F3857F5, + (q31_t)0xF054D8D4, (q31_t)0x7F0991C3, (q31_t)0xEEC60F31, + (q31_t)0x7ED5E5C6, (q31_t)0xED37EF91, (q31_t)0x7E9D55FC, + (q31_t)0xEBAA894E, (q31_t)0x7E5FE493, (q31_t)0xEA1DEBBB, + (q31_t)0x7E1D93E9, (q31_t)0xE8922621, (q31_t)0x7DD6668E, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE57D5FDA, + (q31_t)0x7D3980EC, (q31_t)0xE3F47D95, (q31_t)0x7CE3CEB1, + (q31_t)0xE26CB01A, (q31_t)0x7C894BDD, (q31_t)0xE0E60684, + (q31_t)0x7C29FBEE, (q31_t)0xDF608FE3, (q31_t)0x7BC5E28F, + (q31_t)0xDDDC5B3A, (q31_t)0x7B5D039D, (q31_t)0xDC597781, + (q31_t)0x7AEF6323, (q31_t)0xDAD7F3A2, (q31_t)0x7A7D055B, + (q31_t)0xD957DE7A, (q31_t)0x7A05EEAD, (q31_t)0xD7D946D7, + (q31_t)0x798A23B1, (q31_t)0xD65C3B7B, (q31_t)0x7909A92C, + (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xD3670445, + (q31_t)0x77FAB988, (q31_t)0xD1EEF59E, (q31_t)0x776C4EDB, + (q31_t)0xD078AD9D, (q31_t)0x76D94988, (q31_t)0xCF043AB2, + (q31_t)0x7641AF3C, (q31_t)0xCD91AB38, (q31_t)0x75A585CF, + (q31_t)0xCC210D78, (q31_t)0x7504D345, (q31_t)0xCAB26FA9, + (q31_t)0x745F9DD1, (q31_t)0xC945DFEC, (q31_t)0x73B5EBD0, + (q31_t)0xC7DB6C50, (q31_t)0x7307C3D0, (q31_t)0xC67322CD, + (q31_t)0x72552C84, (q31_t)0xC50D1148, (q31_t)0x719E2CD2, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xC247CD5A, + (q31_t)0x70231099, (q31_t)0xC0E8B648, (q31_t)0x6F5F02B1, + (q31_t)0xBF8C0DE2, (q31_t)0x6E96A99C, (q31_t)0xBE31E19B, + (q31_t)0x6DCA0D14, (q31_t)0xBCDA3ECA, (q31_t)0x6CF934FB, + (q31_t)0xBB8532AF, (q31_t)0x6C242960, (q31_t)0xBA32CA70, + (q31_t)0x6B4AF278, (q31_t)0xB8E31319, (q31_t)0x6A6D98A4, + (q31_t)0xB796199B, (q31_t)0x698C246C, (q31_t)0xB64BEACC, + (q31_t)0x68A69E81, (q31_t)0xB5049368, (q31_t)0x67BD0FBC, + (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xB27E9D3B, + (q31_t)0x65DDFBD3, (q31_t)0xB140175B, (q31_t)0x64E88926, + (q31_t)0xB0049AB2, (q31_t)0x63EF328F, (q31_t)0xAECC336B, + (q31_t)0x62F201AC, (q31_t)0xAD96ED91, (q31_t)0x61F1003E, + (q31_t)0xAC64D510, (q31_t)0x60EC3830, (q31_t)0xAB35F5B5, + (q31_t)0x5FE3B38D, (q31_t)0xAA0A5B2D, (q31_t)0x5ED77C89, + (q31_t)0xA8E21106, (q31_t)0x5DC79D7C, (q31_t)0xA7BD22AB, + (q31_t)0x5CB420DF, (q31_t)0xA69B9B68, (q31_t)0x5B9D1153, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA462EEAC, + (q31_t)0x59646497, (q31_t)0xA34BDF20, (q31_t)0x5842DD54, + (q31_t)0xA2386283, (q31_t)0x571DEEF9, (q31_t)0xA1288376, + (q31_t)0x55F5A4D2, (q31_t)0xA01C4C72, (q31_t)0x54CA0A4A, + (q31_t)0x9F13C7D0, (q31_t)0x539B2AEF, (q31_t)0x9E0EFFC1, + (q31_t)0x5269126E, (q31_t)0x9D0DFE53, (q31_t)0x5133CC94, + (q31_t)0x9C10CD70, (q31_t)0x4FFB654D, (q31_t)0x9B1776D9, + (q31_t)0x4EBFE8A4, (q31_t)0x9A22042C, (q31_t)0x4D8162C4, + (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9842F043, + (q31_t)0x4AFB6C97, (q31_t)0x9759617E, (q31_t)0x49B41533, + (q31_t)0x9673DB94, (q31_t)0x4869E664, (q31_t)0x9592675B, + (q31_t)0x471CECE6, (q31_t)0x94B50D87, (q31_t)0x45CD358F, + (q31_t)0x93DBD69F, (q31_t)0x447ACD50, (q31_t)0x9306CB04, + (q31_t)0x4325C135, (q31_t)0x9235F2EB, (q31_t)0x41CE1E64, + (q31_t)0x91695663, (q31_t)0x4073F21D, (q31_t)0x90A0FD4E, + (q31_t)0x3F1749B7, (q31_t)0x8FDCEF66, (q31_t)0x3DB832A5, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8E61D32D, + (q31_t)0x3AF2EEB7, (q31_t)0x8DAAD37B, (q31_t)0x398CDD32, + (q31_t)0x8CF83C30, (q31_t)0x382493B0, (q31_t)0x8C4A142F, + (q31_t)0x36BA2013, (q31_t)0x8BA0622F, (q31_t)0x354D9056, + (q31_t)0x8AFB2CBA, (q31_t)0x33DEF287, (q31_t)0x8A5A7A30, + (q31_t)0x326E54C7, (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x8926B677, (q31_t)0x2F875262, (q31_t)0x8893B124, + (q31_t)0x2E110A62, (q31_t)0x88054677, (q31_t)0x2C98FBBA, + (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x86F656D3, + (q31_t)0x29A3C484, (q31_t)0x8675DC4E, (q31_t)0x2826B928, + (q31_t)0x85FA1152, (q31_t)0x26A82185, (q31_t)0x8582FAA4, + (q31_t)0x25280C5D, (q31_t)0x85109CDC, (q31_t)0x23A6887E, + (q31_t)0x84A2FC62, (q31_t)0x2223A4C5, (q31_t)0x843A1D70, + (q31_t)0x209F701C, (q31_t)0x83D60411, (q31_t)0x1F19F97B, + (q31_t)0x8376B422, (q31_t)0x1D934FE5, (q31_t)0x831C314E, + (q31_t)0x1C0B826A, (q31_t)0x82C67F13, (q31_t)0x1A82A025, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x82299971, + (q31_t)0x176DD9DE, (q31_t)0x81E26C16, (q31_t)0x15E21444, + (q31_t)0x81A01B6C, (q31_t)0x145576B1, (q31_t)0x8162AA03, + (q31_t)0x12C8106E, (q31_t)0x812A1A39, (q31_t)0x1139F0CE, + (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x80C7A80A, + (q31_t)0x0E1BC2E3, (q31_t)0x809DC970, (q31_t)0x0C8BD35E, + (q31_t)0x8078D40D, (q31_t)0x0AFB6805, (q31_t)0x8058C94C, + (q31_t)0x096A9049, (q31_t)0x803DAA69, (q31_t)0x07D95B9E, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x80163440, + (q31_t)0x04B6195D, (q31_t)0x8009DE7D, (q31_t)0x03242ABF, + (q31_t)0x800277A5, (q31_t)0x01921D1F, (q31_t)0x80000000, + (q31_t)0x00000000, (q31_t)0x800277A5, (q31_t)0xFE6DE2E0, + (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x80163440, + (q31_t)0xFB49E6A2, (q31_t)0x80277872, (q31_t)0xF9B82683, + (q31_t)0x803DAA69, (q31_t)0xF826A461, (q31_t)0x8058C94C, + (q31_t)0xF6956FB6, (q31_t)0x8078D40D, (q31_t)0xF50497FA, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80C7A80A, + (q31_t)0xF1E43D1C, (q31_t)0x80F66E3C, (q31_t)0xF054D8D4, + (q31_t)0x812A1A39, (q31_t)0xEEC60F31, (q31_t)0x8162AA03, + (q31_t)0xED37EF91, (q31_t)0x81A01B6C, (q31_t)0xEBAA894E, + (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x82299971, + (q31_t)0xE8922621, (q31_t)0x8275A0C0, (q31_t)0xE70747C3, + (q31_t)0x82C67F13, (q31_t)0xE57D5FDA, (q31_t)0x831C314E, + (q31_t)0xE3F47D95, (q31_t)0x8376B422, (q31_t)0xE26CB01A, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x843A1D70, + (q31_t)0xDF608FE3, (q31_t)0x84A2FC62, (q31_t)0xDDDC5B3A, + (q31_t)0x85109CDC, (q31_t)0xDC597781, (q31_t)0x8582FAA4, + (q31_t)0xDAD7F3A2, (q31_t)0x85FA1152, (q31_t)0xD957DE7A, + (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x86F656D3, + (q31_t)0xD65C3B7B, (q31_t)0x877B7BEC, (q31_t)0xD4E0CB14, + (q31_t)0x88054677, (q31_t)0xD3670445, (q31_t)0x8893B124, + (q31_t)0xD1EEF59E, (q31_t)0x8926B677, (q31_t)0xD078AD9D, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8A5A7A30, + (q31_t)0xCD91AB38, (q31_t)0x8AFB2CBA, (q31_t)0xCC210D78, + (q31_t)0x8BA0622F, (q31_t)0xCAB26FA9, (q31_t)0x8C4A142F, + (q31_t)0xC945DFEC, (q31_t)0x8CF83C30, (q31_t)0xC7DB6C50, + (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8E61D32D, + (q31_t)0xC50D1148, (q31_t)0x8F1D343A, (q31_t)0xC3A9458F, + (q31_t)0x8FDCEF66, (q31_t)0xC247CD5A, (q31_t)0x90A0FD4E, + (q31_t)0xC0E8B648, (q31_t)0x91695663, (q31_t)0xBF8C0DE2, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x9306CB04, + (q31_t)0xBCDA3ECA, (q31_t)0x93DBD69F, (q31_t)0xBB8532AF, + (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x9592675B, + (q31_t)0xB8E31319, (q31_t)0x9673DB94, (q31_t)0xB796199B, + (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x9842F043, + (q31_t)0xB5049368, (q31_t)0x99307EE0, (q31_t)0xB3C0200C, + (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9B1776D9, + (q31_t)0xB140175B, (q31_t)0x9C10CD70, (q31_t)0xB0049AB2, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9E0EFFC1, + (q31_t)0xAD96ED91, (q31_t)0x9F13C7D0, (q31_t)0xAC64D510, + (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA1288376, + (q31_t)0xAA0A5B2D, (q31_t)0xA2386283, (q31_t)0xA8E21106, + (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA462EEAC, + (q31_t)0xA69B9B68, (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA7BD22AB, + (q31_t)0xA34BDF20, (q31_t)0xA8E21106, (q31_t)0xA2386283, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAB35F5B5, + (q31_t)0xA01C4C72, (q31_t)0xAC64D510, (q31_t)0x9F13C7D0, + (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xAECC336B, + (q31_t)0x9D0DFE53, (q31_t)0xB0049AB2, (q31_t)0x9C10CD70, + (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB27E9D3B, + (q31_t)0x9A22042C, (q31_t)0xB3C0200C, (q31_t)0x99307EE0, + (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB64BEACC, + (q31_t)0x9759617E, (q31_t)0xB796199B, (q31_t)0x9673DB94, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBA32CA70, + (q31_t)0x94B50D87, (q31_t)0xBB8532AF, (q31_t)0x93DBD69F, + (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBE31E19B, + (q31_t)0x9235F2EB, (q31_t)0xBF8C0DE2, (q31_t)0x91695663, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC247CD5A, + (q31_t)0x8FDCEF66, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A, + (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC67322CD, + (q31_t)0x8DAAD37B, (q31_t)0xC7DB6C50, (q31_t)0x8CF83C30, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCAB26FA9, + (q31_t)0x8BA0622F, (q31_t)0xCC210D78, (q31_t)0x8AFB2CBA, + (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCF043AB2, + (q31_t)0x89BE50C3, (q31_t)0xD078AD9D, (q31_t)0x8926B677, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD3670445, + (q31_t)0x88054677, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC, + (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD7D946D7, + (q31_t)0x8675DC4E, (q31_t)0xD957DE7A, (q31_t)0x85FA1152, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDC597781, + (q31_t)0x85109CDC, (q31_t)0xDDDC5B3A, (q31_t)0x84A2FC62, + (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xE0E60684, + (q31_t)0x83D60411, (q31_t)0xE26CB01A, (q31_t)0x8376B422, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE57D5FDA, + (q31_t)0x82C67F13, (q31_t)0xE70747C3, (q31_t)0x8275A0C0, + (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xEA1DEBBB, + (q31_t)0x81E26C16, (q31_t)0xEBAA894E, (q31_t)0x81A01B6C, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xEEC60F31, + (q31_t)0x812A1A39, (q31_t)0xF054D8D4, (q31_t)0x80F66E3C, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF3742CA1, + (q31_t)0x809DC970, (q31_t)0xF50497FA, (q31_t)0x8078D40D, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF826A461, + (q31_t)0x803DAA69, (q31_t)0xF9B82683, (q31_t)0x80277872, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFCDBD541, + (q31_t)0x8009DE7D, (q31_t)0xFE6DE2E0, (q31_t)0x800277A5 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par +
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 1024, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + + */ +const q31_t twiddleCoef_1024_q31[1536] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFF6216, + (q31_t)0x00C90F88, (q31_t)0x7FFD885A, (q31_t)0x01921D1F, + (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF62182, + (q31_t)0x03242ABF, (q31_t)0x7FF09477, (q31_t)0x03ED26E6, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE1C76B, + (q31_t)0x057F0034, (q31_t)0x7FD8878D, (q31_t)0x0647D97C, + (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FC25596, + (q31_t)0x07D95B9E, (q31_t)0x7FB563B2, (q31_t)0x08A2009A, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F97CEBC, + (q31_t)0x0A3308BC, (q31_t)0x7F872BF3, (q31_t)0x0AFB6805, + (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7F4DE450, (q31_t)0x0D53DB92, + (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F2191B4, + (q31_t)0x0EE38765, (q31_t)0x7F0991C3, (q31_t)0x0FAB272B, + (q31_t)0x7EF0585F, (q31_t)0x1072A047, (q31_t)0x7ED5E5C6, + (q31_t)0x1139F0CE, (q31_t)0x7EBA3A39, (q31_t)0x120116D4, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E7F3956, + (q31_t)0x138EDBB0, (q31_t)0x7E5FE493, (q31_t)0x145576B1, + (q31_t)0x7E3F57FE, (q31_t)0x151BDF85, (q31_t)0x7E1D93E9, + (q31_t)0x15E21444, (q31_t)0x7DFA98A7, (q31_t)0x16A81305, + (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7DB0FDF7, + (q31_t)0x183366E8, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7D628AC5, (q31_t)0x19BDCBF2, (q31_t)0x7D3980EC, + (q31_t)0x1A82A025, (q31_t)0x7D0F4218, (q31_t)0x1B4732EF, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7CB72724, + (q31_t)0x1CCF8CB3, (q31_t)0x7C894BDD, (q31_t)0x1D934FE5, + (q31_t)0x7C5A3D4F, (q31_t)0x1E56CA1E, (q31_t)0x7C29FBEE, + (q31_t)0x1F19F97B, (q31_t)0x7BF88830, (q31_t)0x1FDCDC1A, + (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7B920B89, + (q31_t)0x2161B39F, (q31_t)0x7B5D039D, (q31_t)0x2223A4C5, + (q31_t)0x7B26CB4F, (q31_t)0x22E541AE, (q31_t)0x7AEF6323, + (q31_t)0x23A6887E, (q31_t)0x7AB6CBA3, (q31_t)0x24677757, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A4210D8, + (q31_t)0x25E845B5, (q31_t)0x7A05EEAD, (q31_t)0x26A82185, + (q31_t)0x79C89F6D, (q31_t)0x27679DF4, (q31_t)0x798A23B1, + (q31_t)0x2826B928, (q31_t)0x794A7C11, (q31_t)0x28E5714A, + (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78C7ABA1, + (q31_t)0x2A61B101, (q31_t)0x78848413, (q31_t)0x2B1F34EB, + (q31_t)0x78403328, (q31_t)0x2BDC4E6F, (q31_t)0x77FAB988, + (q31_t)0x2C98FBBA, (q31_t)0x77B417DF, (q31_t)0x2D553AFB, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x77235F2D, + (q31_t)0x2ECC681E, (q31_t)0x76D94988, (q31_t)0x2F875262, + (q31_t)0x768E0EA5, (q31_t)0x3041C760, (q31_t)0x7641AF3C, + (q31_t)0x30FBC54D, (q31_t)0x75F42C0A, (q31_t)0x31B54A5D, + (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x7555BD4B, + (q31_t)0x3326E2C2, (q31_t)0x7504D345, (q31_t)0x33DEF287, + (q31_t)0x74B2C883, (q31_t)0x3496824F, (q31_t)0x745F9DD1, + (q31_t)0x354D9056, (q31_t)0x740B53FA, (q31_t)0x36041AD9, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x735F6626, + (q31_t)0x376F9E46, (q31_t)0x7307C3D0, (q31_t)0x382493B0, + (q31_t)0x72AF05A6, (q31_t)0x38D8FE93, (q31_t)0x72552C84, + (q31_t)0x398CDD32, (q31_t)0x71FA3948, (q31_t)0x3A402DD1, + (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x71410804, + (q31_t)0x3BA51E29, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70, + (q31_t)0x708378FE, (q31_t)0x3D07C1D5, (q31_t)0x70231099, + (q31_t)0x3DB832A5, (q31_t)0x6FC19385, (q31_t)0x3E680B2C, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6EFB5F12, + (q31_t)0x3FC5EC97, (q31_t)0x6E96A99C, (q31_t)0x4073F21D, + (q31_t)0x6E30E349, (q31_t)0x4121589A, (q31_t)0x6DCA0D14, + (q31_t)0x41CE1E64, (q31_t)0x6D6227FA, (q31_t)0x427A41D0, + (q31_t)0x6CF934FB, (q31_t)0x4325C135, (q31_t)0x6C8F351C, + (q31_t)0x43D09AEC, (q31_t)0x6C242960, (q31_t)0x447ACD50, + (q31_t)0x6BB812D0, (q31_t)0x452456BC, (q31_t)0x6B4AF278, + (q31_t)0x45CD358F, (q31_t)0x6ADCC964, (q31_t)0x46756827, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x69FD614A, + (q31_t)0x47C3C22E, (q31_t)0x698C246C, (q31_t)0x4869E664, + (q31_t)0x6919E320, (q31_t)0x490F57EE, (q31_t)0x68A69E81, + (q31_t)0x49B41533, (q31_t)0x683257AA, (q31_t)0x4A581C9D, + (q31_t)0x67BD0FBC, (q31_t)0x4AFB6C97, (q31_t)0x6746C7D7, + (q31_t)0x4B9E038F, (q31_t)0x66CF811F, (q31_t)0x4C3FDFF3, + (q31_t)0x66573CBB, (q31_t)0x4CE10034, (q31_t)0x65DDFBD3, + (q31_t)0x4D8162C4, (q31_t)0x6563BF92, (q31_t)0x4E210617, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x646C59BF, + (q31_t)0x4F5E08E3, (q31_t)0x63EF328F, (q31_t)0x4FFB654D, + (q31_t)0x637114CC, (q31_t)0x5097FC5E, (q31_t)0x62F201AC, + (q31_t)0x5133CC94, (q31_t)0x6271FA69, (q31_t)0x51CED46E, + (q31_t)0x61F1003E, (q31_t)0x5269126E, (q31_t)0x616F146B, + (q31_t)0x53028517, (q31_t)0x60EC3830, (q31_t)0x539B2AEF, + (q31_t)0x60686CCE, (q31_t)0x5433027D, (q31_t)0x5FE3B38D, + (q31_t)0x54CA0A4A, (q31_t)0x5F5E0DB3, (q31_t)0x556040E2, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5E50015D, + (q31_t)0x568A34A9, (q31_t)0x5DC79D7C, (q31_t)0x571DEEF9, + (q31_t)0x5D3E5236, (q31_t)0x57B0D256, (q31_t)0x5CB420DF, + (q31_t)0x5842DD54, (q31_t)0x5C290ACC, (q31_t)0x58D40E8C, + (q31_t)0x5B9D1153, (q31_t)0x59646497, (q31_t)0x5B1035CF, + (q31_t)0x59F3DE12, (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x59F3DE12, (q31_t)0x5B1035CF, (q31_t)0x59646497, + (q31_t)0x5B9D1153, (q31_t)0x58D40E8C, (q31_t)0x5C290ACC, + (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x57B0D256, + (q31_t)0x5D3E5236, (q31_t)0x571DEEF9, (q31_t)0x5DC79D7C, + (q31_t)0x568A34A9, (q31_t)0x5E50015D, (q31_t)0x55F5A4D2, + (q31_t)0x5ED77C89, (q31_t)0x556040E2, (q31_t)0x5F5E0DB3, + (q31_t)0x54CA0A4A, (q31_t)0x5FE3B38D, (q31_t)0x5433027D, + (q31_t)0x60686CCE, (q31_t)0x539B2AEF, (q31_t)0x60EC3830, + (q31_t)0x53028517, (q31_t)0x616F146B, (q31_t)0x5269126E, + (q31_t)0x61F1003E, (q31_t)0x51CED46E, (q31_t)0x6271FA69, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x5097FC5E, + (q31_t)0x637114CC, (q31_t)0x4FFB654D, (q31_t)0x63EF328F, + (q31_t)0x4F5E08E3, (q31_t)0x646C59BF, (q31_t)0x4EBFE8A4, + (q31_t)0x64E88926, (q31_t)0x4E210617, (q31_t)0x6563BF92, + (q31_t)0x4D8162C4, (q31_t)0x65DDFBD3, (q31_t)0x4CE10034, + (q31_t)0x66573CBB, (q31_t)0x4C3FDFF3, (q31_t)0x66CF811F, + (q31_t)0x4B9E038F, (q31_t)0x6746C7D7, (q31_t)0x4AFB6C97, + (q31_t)0x67BD0FBC, (q31_t)0x4A581C9D, (q31_t)0x683257AA, + (q31_t)0x49B41533, (q31_t)0x68A69E81, (q31_t)0x490F57EE, + (q31_t)0x6919E320, (q31_t)0x4869E664, (q31_t)0x698C246C, + (q31_t)0x47C3C22E, (q31_t)0x69FD614A, (q31_t)0x471CECE6, + (q31_t)0x6A6D98A4, (q31_t)0x46756827, (q31_t)0x6ADCC964, + (q31_t)0x45CD358F, (q31_t)0x6B4AF278, (q31_t)0x452456BC, + (q31_t)0x6BB812D0, (q31_t)0x447ACD50, (q31_t)0x6C242960, + (q31_t)0x43D09AEC, (q31_t)0x6C8F351C, (q31_t)0x4325C135, + (q31_t)0x6CF934FB, (q31_t)0x427A41D0, (q31_t)0x6D6227FA, + (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x4121589A, + (q31_t)0x6E30E349, (q31_t)0x4073F21D, (q31_t)0x6E96A99C, + (q31_t)0x3FC5EC97, (q31_t)0x6EFB5F12, (q31_t)0x3F1749B7, + (q31_t)0x6F5F02B1, (q31_t)0x3E680B2C, (q31_t)0x6FC19385, + (q31_t)0x3DB832A5, (q31_t)0x70231099, (q31_t)0x3D07C1D5, + (q31_t)0x708378FE, (q31_t)0x3C56BA70, (q31_t)0x70E2CBC6, + (q31_t)0x3BA51E29, (q31_t)0x71410804, (q31_t)0x3AF2EEB7, + (q31_t)0x719E2CD2, (q31_t)0x3A402DD1, (q31_t)0x71FA3948, + (q31_t)0x398CDD32, (q31_t)0x72552C84, (q31_t)0x38D8FE93, + (q31_t)0x72AF05A6, (q31_t)0x382493B0, (q31_t)0x7307C3D0, + (q31_t)0x376F9E46, (q31_t)0x735F6626, (q31_t)0x36BA2013, + (q31_t)0x73B5EBD0, (q31_t)0x36041AD9, (q31_t)0x740B53FA, + (q31_t)0x354D9056, (q31_t)0x745F9DD1, (q31_t)0x3496824F, + (q31_t)0x74B2C883, (q31_t)0x33DEF287, (q31_t)0x7504D345, + (q31_t)0x3326E2C2, (q31_t)0x7555BD4B, (q31_t)0x326E54C7, + (q31_t)0x75A585CF, (q31_t)0x31B54A5D, (q31_t)0x75F42C0A, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x3041C760, + (q31_t)0x768E0EA5, (q31_t)0x2F875262, (q31_t)0x76D94988, + (q31_t)0x2ECC681E, (q31_t)0x77235F2D, (q31_t)0x2E110A62, + (q31_t)0x776C4EDB, (q31_t)0x2D553AFB, (q31_t)0x77B417DF, + (q31_t)0x2C98FBBA, (q31_t)0x77FAB988, (q31_t)0x2BDC4E6F, + (q31_t)0x78403328, (q31_t)0x2B1F34EB, (q31_t)0x78848413, + (q31_t)0x2A61B101, (q31_t)0x78C7ABA1, (q31_t)0x29A3C484, + (q31_t)0x7909A92C, (q31_t)0x28E5714A, (q31_t)0x794A7C11, + (q31_t)0x2826B928, (q31_t)0x798A23B1, (q31_t)0x27679DF4, + (q31_t)0x79C89F6D, (q31_t)0x26A82185, (q31_t)0x7A05EEAD, + (q31_t)0x25E845B5, (q31_t)0x7A4210D8, (q31_t)0x25280C5D, + (q31_t)0x7A7D055B, (q31_t)0x24677757, (q31_t)0x7AB6CBA3, + (q31_t)0x23A6887E, (q31_t)0x7AEF6323, (q31_t)0x22E541AE, + (q31_t)0x7B26CB4F, (q31_t)0x2223A4C5, (q31_t)0x7B5D039D, + (q31_t)0x2161B39F, (q31_t)0x7B920B89, (q31_t)0x209F701C, + (q31_t)0x7BC5E28F, (q31_t)0x1FDCDC1A, (q31_t)0x7BF88830, + (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x1E56CA1E, + (q31_t)0x7C5A3D4F, (q31_t)0x1D934FE5, (q31_t)0x7C894BDD, + (q31_t)0x1CCF8CB3, (q31_t)0x7CB72724, (q31_t)0x1C0B826A, + (q31_t)0x7CE3CEB1, (q31_t)0x1B4732EF, (q31_t)0x7D0F4218, + (q31_t)0x1A82A025, (q31_t)0x7D3980EC, (q31_t)0x19BDCBF2, + (q31_t)0x7D628AC5, (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x183366E8, (q31_t)0x7DB0FDF7, (q31_t)0x176DD9DE, + (q31_t)0x7DD6668E, (q31_t)0x16A81305, (q31_t)0x7DFA98A7, + (q31_t)0x15E21444, (q31_t)0x7E1D93E9, (q31_t)0x151BDF85, + (q31_t)0x7E3F57FE, (q31_t)0x145576B1, (q31_t)0x7E5FE493, + (q31_t)0x138EDBB0, (q31_t)0x7E7F3956, (q31_t)0x12C8106E, + (q31_t)0x7E9D55FC, (q31_t)0x120116D4, (q31_t)0x7EBA3A39, + (q31_t)0x1139F0CE, (q31_t)0x7ED5E5C6, (q31_t)0x1072A047, + (q31_t)0x7EF0585F, (q31_t)0x0FAB272B, (q31_t)0x7F0991C3, + (q31_t)0x0EE38765, (q31_t)0x7F2191B4, (q31_t)0x0E1BC2E3, + (q31_t)0x7F3857F5, (q31_t)0x0D53DB92, (q31_t)0x7F4DE450, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x0BC3AC35, + (q31_t)0x7F754E7F, (q31_t)0x0AFB6805, (q31_t)0x7F872BF3, + (q31_t)0x0A3308BC, (q31_t)0x7F97CEBC, (q31_t)0x096A9049, + (q31_t)0x7FA736B4, (q31_t)0x08A2009A, (q31_t)0x7FB563B2, + (q31_t)0x07D95B9E, (q31_t)0x7FC25596, (q31_t)0x0710A344, + (q31_t)0x7FCE0C3E, (q31_t)0x0647D97C, (q31_t)0x7FD8878D, + (q31_t)0x057F0034, (q31_t)0x7FE1C76B, (q31_t)0x04B6195D, + (q31_t)0x7FE9CBC0, (q31_t)0x03ED26E6, (q31_t)0x7FF09477, + (q31_t)0x03242ABF, (q31_t)0x7FF62182, (q31_t)0x025B26D7, + (q31_t)0x7FFA72D1, (q31_t)0x01921D1F, (q31_t)0x7FFD885A, + (q31_t)0x00C90F88, (q31_t)0x7FFF6216, (q31_t)0x00000000, + (q31_t)0x7FFFFFFF, (q31_t)0xFF36F078, (q31_t)0x7FFF6216, + (q31_t)0xFE6DE2E0, (q31_t)0x7FFD885A, (q31_t)0xFDA4D928, + (q31_t)0x7FFA72D1, (q31_t)0xFCDBD541, (q31_t)0x7FF62182, + (q31_t)0xFC12D919, (q31_t)0x7FF09477, (q31_t)0xFB49E6A2, + (q31_t)0x7FE9CBC0, (q31_t)0xFA80FFCB, (q31_t)0x7FE1C76B, + (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF8EF5CBB, + (q31_t)0x7FCE0C3E, (q31_t)0xF826A461, (q31_t)0x7FC25596, + (q31_t)0xF75DFF65, (q31_t)0x7FB563B2, (q31_t)0xF6956FB6, + (q31_t)0x7FA736B4, (q31_t)0xF5CCF743, (q31_t)0x7F97CEBC, + (q31_t)0xF50497FA, (q31_t)0x7F872BF3, (q31_t)0xF43C53CA, + (q31_t)0x7F754E7F, (q31_t)0xF3742CA1, (q31_t)0x7F62368F, + (q31_t)0xF2AC246D, (q31_t)0x7F4DE450, (q31_t)0xF1E43D1C, + (q31_t)0x7F3857F5, (q31_t)0xF11C789A, (q31_t)0x7F2191B4, + (q31_t)0xF054D8D4, (q31_t)0x7F0991C3, (q31_t)0xEF8D5FB8, + (q31_t)0x7EF0585F, (q31_t)0xEEC60F31, (q31_t)0x7ED5E5C6, + (q31_t)0xEDFEE92B, (q31_t)0x7EBA3A39, (q31_t)0xED37EF91, + (q31_t)0x7E9D55FC, (q31_t)0xEC71244F, (q31_t)0x7E7F3956, + (q31_t)0xEBAA894E, (q31_t)0x7E5FE493, (q31_t)0xEAE4207A, + (q31_t)0x7E3F57FE, (q31_t)0xEA1DEBBB, (q31_t)0x7E1D93E9, + (q31_t)0xE957ECFB, (q31_t)0x7DFA98A7, (q31_t)0xE8922621, + (q31_t)0x7DD6668E, (q31_t)0xE7CC9917, (q31_t)0x7DB0FDF7, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE642340D, + (q31_t)0x7D628AC5, (q31_t)0xE57D5FDA, (q31_t)0x7D3980EC, + (q31_t)0xE4B8CD10, (q31_t)0x7D0F4218, (q31_t)0xE3F47D95, + (q31_t)0x7CE3CEB1, (q31_t)0xE330734C, (q31_t)0x7CB72724, + (q31_t)0xE26CB01A, (q31_t)0x7C894BDD, (q31_t)0xE1A935E1, + (q31_t)0x7C5A3D4F, (q31_t)0xE0E60684, (q31_t)0x7C29FBEE, + (q31_t)0xE02323E5, (q31_t)0x7BF88830, (q31_t)0xDF608FE3, + (q31_t)0x7BC5E28F, (q31_t)0xDE9E4C60, (q31_t)0x7B920B89, + (q31_t)0xDDDC5B3A, (q31_t)0x7B5D039D, (q31_t)0xDD1ABE51, + (q31_t)0x7B26CB4F, (q31_t)0xDC597781, (q31_t)0x7AEF6323, + (q31_t)0xDB9888A8, (q31_t)0x7AB6CBA3, (q31_t)0xDAD7F3A2, + (q31_t)0x7A7D055B, (q31_t)0xDA17BA4A, (q31_t)0x7A4210D8, + (q31_t)0xD957DE7A, (q31_t)0x7A05EEAD, (q31_t)0xD898620C, + (q31_t)0x79C89F6D, (q31_t)0xD7D946D7, (q31_t)0x798A23B1, + (q31_t)0xD71A8EB5, (q31_t)0x794A7C11, (q31_t)0xD65C3B7B, + (q31_t)0x7909A92C, (q31_t)0xD59E4EFE, (q31_t)0x78C7ABA1, + (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xD423B190, + (q31_t)0x78403328, (q31_t)0xD3670445, (q31_t)0x77FAB988, + (q31_t)0xD2AAC504, (q31_t)0x77B417DF, (q31_t)0xD1EEF59E, + (q31_t)0x776C4EDB, (q31_t)0xD13397E1, (q31_t)0x77235F2D, + (q31_t)0xD078AD9D, (q31_t)0x76D94988, (q31_t)0xCFBE389F, + (q31_t)0x768E0EA5, (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xCE4AB5A2, (q31_t)0x75F42C0A, (q31_t)0xCD91AB38, + (q31_t)0x75A585CF, (q31_t)0xCCD91D3D, (q31_t)0x7555BD4B, + (q31_t)0xCC210D78, (q31_t)0x7504D345, (q31_t)0xCB697DB0, + (q31_t)0x74B2C883, (q31_t)0xCAB26FA9, (q31_t)0x745F9DD1, + (q31_t)0xC9FBE527, (q31_t)0x740B53FA, (q31_t)0xC945DFEC, + (q31_t)0x73B5EBD0, (q31_t)0xC89061BA, (q31_t)0x735F6626, + (q31_t)0xC7DB6C50, (q31_t)0x7307C3D0, (q31_t)0xC727016C, + (q31_t)0x72AF05A6, (q31_t)0xC67322CD, (q31_t)0x72552C84, + (q31_t)0xC5BFD22E, (q31_t)0x71FA3948, (q31_t)0xC50D1148, + (q31_t)0x719E2CD2, (q31_t)0xC45AE1D7, (q31_t)0x71410804, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xC2F83E2A, + (q31_t)0x708378FE, (q31_t)0xC247CD5A, (q31_t)0x70231099, + (q31_t)0xC197F4D3, (q31_t)0x6FC19385, (q31_t)0xC0E8B648, + (q31_t)0x6F5F02B1, (q31_t)0xC03A1368, (q31_t)0x6EFB5F12, + (q31_t)0xBF8C0DE2, (q31_t)0x6E96A99C, (q31_t)0xBEDEA765, + (q31_t)0x6E30E349, (q31_t)0xBE31E19B, (q31_t)0x6DCA0D14, + (q31_t)0xBD85BE2F, (q31_t)0x6D6227FA, (q31_t)0xBCDA3ECA, + (q31_t)0x6CF934FB, (q31_t)0xBC2F6513, (q31_t)0x6C8F351C, + (q31_t)0xBB8532AF, (q31_t)0x6C242960, (q31_t)0xBADBA943, + (q31_t)0x6BB812D0, (q31_t)0xBA32CA70, (q31_t)0x6B4AF278, + (q31_t)0xB98A97D8, (q31_t)0x6ADCC964, (q31_t)0xB8E31319, + (q31_t)0x6A6D98A4, (q31_t)0xB83C3DD1, (q31_t)0x69FD614A, + (q31_t)0xB796199B, (q31_t)0x698C246C, (q31_t)0xB6F0A811, + (q31_t)0x6919E320, (q31_t)0xB64BEACC, (q31_t)0x68A69E81, + (q31_t)0xB5A7E362, (q31_t)0x683257AA, (q31_t)0xB5049368, + (q31_t)0x67BD0FBC, (q31_t)0xB461FC70, (q31_t)0x6746C7D7, + (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xB31EFFCB, + (q31_t)0x66573CBB, (q31_t)0xB27E9D3B, (q31_t)0x65DDFBD3, + (q31_t)0xB1DEF9E8, (q31_t)0x6563BF92, (q31_t)0xB140175B, + (q31_t)0x64E88926, (q31_t)0xB0A1F71C, (q31_t)0x646C59BF, + (q31_t)0xB0049AB2, (q31_t)0x63EF328F, (q31_t)0xAF6803A1, + (q31_t)0x637114CC, (q31_t)0xAECC336B, (q31_t)0x62F201AC, + (q31_t)0xAE312B91, (q31_t)0x6271FA69, (q31_t)0xAD96ED91, + (q31_t)0x61F1003E, (q31_t)0xACFD7AE8, (q31_t)0x616F146B, + (q31_t)0xAC64D510, (q31_t)0x60EC3830, (q31_t)0xABCCFD82, + (q31_t)0x60686CCE, (q31_t)0xAB35F5B5, (q31_t)0x5FE3B38D, + (q31_t)0xAA9FBF1D, (q31_t)0x5F5E0DB3, (q31_t)0xAA0A5B2D, + (q31_t)0x5ED77C89, (q31_t)0xA975CB56, (q31_t)0x5E50015D, + (q31_t)0xA8E21106, (q31_t)0x5DC79D7C, (q31_t)0xA84F2DA9, + (q31_t)0x5D3E5236, (q31_t)0xA7BD22AB, (q31_t)0x5CB420DF, + (q31_t)0xA72BF173, (q31_t)0x5C290ACC, (q31_t)0xA69B9B68, + (q31_t)0x5B9D1153, (q31_t)0xA60C21ED, (q31_t)0x5B1035CF, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA4EFCA31, + (q31_t)0x59F3DE12, (q31_t)0xA462EEAC, (q31_t)0x59646497, + (q31_t)0xA3D6F533, (q31_t)0x58D40E8C, (q31_t)0xA34BDF20, + (q31_t)0x5842DD54, (q31_t)0xA2C1ADC9, (q31_t)0x57B0D256, + (q31_t)0xA2386283, (q31_t)0x571DEEF9, (q31_t)0xA1AFFEA2, + (q31_t)0x568A34A9, (q31_t)0xA1288376, (q31_t)0x55F5A4D2, + (q31_t)0xA0A1F24C, (q31_t)0x556040E2, (q31_t)0xA01C4C72, + (q31_t)0x54CA0A4A, (q31_t)0x9F979331, (q31_t)0x5433027D, + (q31_t)0x9F13C7D0, (q31_t)0x539B2AEF, (q31_t)0x9E90EB94, + (q31_t)0x53028517, (q31_t)0x9E0EFFC1, (q31_t)0x5269126E, + (q31_t)0x9D8E0596, (q31_t)0x51CED46E, (q31_t)0x9D0DFE53, + (q31_t)0x5133CC94, (q31_t)0x9C8EEB33, (q31_t)0x5097FC5E, + (q31_t)0x9C10CD70, (q31_t)0x4FFB654D, (q31_t)0x9B93A640, + (q31_t)0x4F5E08E3, (q31_t)0x9B1776D9, (q31_t)0x4EBFE8A4, + (q31_t)0x9A9C406D, (q31_t)0x4E210617, (q31_t)0x9A22042C, + (q31_t)0x4D8162C4, (q31_t)0x99A8C344, (q31_t)0x4CE10034, + (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x98B93828, + (q31_t)0x4B9E038F, (q31_t)0x9842F043, (q31_t)0x4AFB6C97, + (q31_t)0x97CDA855, (q31_t)0x4A581C9D, (q31_t)0x9759617E, + (q31_t)0x49B41533, (q31_t)0x96E61CDF, (q31_t)0x490F57EE, + (q31_t)0x9673DB94, (q31_t)0x4869E664, (q31_t)0x96029EB5, + (q31_t)0x47C3C22E, (q31_t)0x9592675B, (q31_t)0x471CECE6, + (q31_t)0x9523369B, (q31_t)0x46756827, (q31_t)0x94B50D87, + (q31_t)0x45CD358F, (q31_t)0x9447ED2F, (q31_t)0x452456BC, + (q31_t)0x93DBD69F, (q31_t)0x447ACD50, (q31_t)0x9370CAE4, + (q31_t)0x43D09AEC, (q31_t)0x9306CB04, (q31_t)0x4325C135, + (q31_t)0x929DD805, (q31_t)0x427A41D0, (q31_t)0x9235F2EB, + (q31_t)0x41CE1E64, (q31_t)0x91CF1CB6, (q31_t)0x4121589A, + (q31_t)0x91695663, (q31_t)0x4073F21D, (q31_t)0x9104A0ED, + (q31_t)0x3FC5EC97, (q31_t)0x90A0FD4E, (q31_t)0x3F1749B7, + (q31_t)0x903E6C7A, (q31_t)0x3E680B2C, (q31_t)0x8FDCEF66, + (q31_t)0x3DB832A5, (q31_t)0x8F7C8701, (q31_t)0x3D07C1D5, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8EBEF7FB, + (q31_t)0x3BA51E29, (q31_t)0x8E61D32D, (q31_t)0x3AF2EEB7, + (q31_t)0x8E05C6B7, (q31_t)0x3A402DD1, (q31_t)0x8DAAD37B, + (q31_t)0x398CDD32, (q31_t)0x8D50FA59, (q31_t)0x38D8FE93, + (q31_t)0x8CF83C30, (q31_t)0x382493B0, (q31_t)0x8CA099D9, + (q31_t)0x376F9E46, (q31_t)0x8C4A142F, (q31_t)0x36BA2013, + (q31_t)0x8BF4AC05, (q31_t)0x36041AD9, (q31_t)0x8BA0622F, + (q31_t)0x354D9056, (q31_t)0x8B4D377C, (q31_t)0x3496824F, + (q31_t)0x8AFB2CBA, (q31_t)0x33DEF287, (q31_t)0x8AAA42B4, + (q31_t)0x3326E2C2, (q31_t)0x8A5A7A30, (q31_t)0x326E54C7, + (q31_t)0x8A0BD3F5, (q31_t)0x31B54A5D, (q31_t)0x89BE50C3, + (q31_t)0x30FBC54D, (q31_t)0x8971F15A, (q31_t)0x3041C760, + (q31_t)0x8926B677, (q31_t)0x2F875262, (q31_t)0x88DCA0D3, + (q31_t)0x2ECC681E, (q31_t)0x8893B124, (q31_t)0x2E110A62, + (q31_t)0x884BE820, (q31_t)0x2D553AFB, (q31_t)0x88054677, + (q31_t)0x2C98FBBA, (q31_t)0x87BFCCD7, (q31_t)0x2BDC4E6F, + (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x8738545E, + (q31_t)0x2A61B101, (q31_t)0x86F656D3, (q31_t)0x29A3C484, + (q31_t)0x86B583EE, (q31_t)0x28E5714A, (q31_t)0x8675DC4E, + (q31_t)0x2826B928, (q31_t)0x86376092, (q31_t)0x27679DF4, + (q31_t)0x85FA1152, (q31_t)0x26A82185, (q31_t)0x85BDEF27, + (q31_t)0x25E845B5, (q31_t)0x8582FAA4, (q31_t)0x25280C5D, + (q31_t)0x8549345C, (q31_t)0x24677757, (q31_t)0x85109CDC, + (q31_t)0x23A6887E, (q31_t)0x84D934B0, (q31_t)0x22E541AE, + (q31_t)0x84A2FC62, (q31_t)0x2223A4C5, (q31_t)0x846DF476, + (q31_t)0x2161B39F, (q31_t)0x843A1D70, (q31_t)0x209F701C, + (q31_t)0x840777CF, (q31_t)0x1FDCDC1A, (q31_t)0x83D60411, + (q31_t)0x1F19F97B, (q31_t)0x83A5C2B0, (q31_t)0x1E56CA1E, + (q31_t)0x8376B422, (q31_t)0x1D934FE5, (q31_t)0x8348D8DB, + (q31_t)0x1CCF8CB3, (q31_t)0x831C314E, (q31_t)0x1C0B826A, + (q31_t)0x82F0BDE8, (q31_t)0x1B4732EF, (q31_t)0x82C67F13, + (q31_t)0x1A82A025, (q31_t)0x829D753A, (q31_t)0x19BDCBF2, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x824F0208, + (q31_t)0x183366E8, (q31_t)0x82299971, (q31_t)0x176DD9DE, + (q31_t)0x82056758, (q31_t)0x16A81305, (q31_t)0x81E26C16, + (q31_t)0x15E21444, (q31_t)0x81C0A801, (q31_t)0x151BDF85, + (q31_t)0x81A01B6C, (q31_t)0x145576B1, (q31_t)0x8180C6A9, + (q31_t)0x138EDBB0, (q31_t)0x8162AA03, (q31_t)0x12C8106E, + (q31_t)0x8145C5C6, (q31_t)0x120116D4, (q31_t)0x812A1A39, + (q31_t)0x1139F0CE, (q31_t)0x810FA7A0, (q31_t)0x1072A047, + (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x80DE6E4C, + (q31_t)0x0EE38765, (q31_t)0x80C7A80A, (q31_t)0x0E1BC2E3, + (q31_t)0x80B21BAF, (q31_t)0x0D53DB92, (q31_t)0x809DC970, + (q31_t)0x0C8BD35E, (q31_t)0x808AB180, (q31_t)0x0BC3AC35, + (q31_t)0x8078D40D, (q31_t)0x0AFB6805, (q31_t)0x80683143, + (q31_t)0x0A3308BC, (q31_t)0x8058C94C, (q31_t)0x096A9049, + (q31_t)0x804A9C4D, (q31_t)0x08A2009A, (q31_t)0x803DAA69, + (q31_t)0x07D95B9E, (q31_t)0x8031F3C1, (q31_t)0x0710A344, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x801E3894, + (q31_t)0x057F0034, (q31_t)0x80163440, (q31_t)0x04B6195D, + (q31_t)0x800F6B88, (q31_t)0x03ED26E6, (q31_t)0x8009DE7D, + (q31_t)0x03242ABF, (q31_t)0x80058D2E, (q31_t)0x025B26D7, + (q31_t)0x800277A5, (q31_t)0x01921D1F, (q31_t)0x80009DE9, + (q31_t)0x00C90F88, (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x80009DE9, (q31_t)0xFF36F078, (q31_t)0x800277A5, + (q31_t)0xFE6DE2E0, (q31_t)0x80058D2E, (q31_t)0xFDA4D928, + (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x800F6B88, + (q31_t)0xFC12D919, (q31_t)0x80163440, (q31_t)0xFB49E6A2, + (q31_t)0x801E3894, (q31_t)0xFA80FFCB, (q31_t)0x80277872, + (q31_t)0xF9B82683, (q31_t)0x8031F3C1, (q31_t)0xF8EF5CBB, + (q31_t)0x803DAA69, (q31_t)0xF826A461, (q31_t)0x804A9C4D, + (q31_t)0xF75DFF65, (q31_t)0x8058C94C, (q31_t)0xF6956FB6, + (q31_t)0x80683143, (q31_t)0xF5CCF743, (q31_t)0x8078D40D, + (q31_t)0xF50497FA, (q31_t)0x808AB180, (q31_t)0xF43C53CA, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80B21BAF, + (q31_t)0xF2AC246D, (q31_t)0x80C7A80A, (q31_t)0xF1E43D1C, + (q31_t)0x80DE6E4C, (q31_t)0xF11C789A, (q31_t)0x80F66E3C, + (q31_t)0xF054D8D4, (q31_t)0x810FA7A0, (q31_t)0xEF8D5FB8, + (q31_t)0x812A1A39, (q31_t)0xEEC60F31, (q31_t)0x8145C5C6, + (q31_t)0xEDFEE92B, (q31_t)0x8162AA03, (q31_t)0xED37EF91, + (q31_t)0x8180C6A9, (q31_t)0xEC71244F, (q31_t)0x81A01B6C, + (q31_t)0xEBAA894E, (q31_t)0x81C0A801, (q31_t)0xEAE4207A, + (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x82056758, + (q31_t)0xE957ECFB, (q31_t)0x82299971, (q31_t)0xE8922621, + (q31_t)0x824F0208, (q31_t)0xE7CC9917, (q31_t)0x8275A0C0, + (q31_t)0xE70747C3, (q31_t)0x829D753A, (q31_t)0xE642340D, + (q31_t)0x82C67F13, (q31_t)0xE57D5FDA, (q31_t)0x82F0BDE8, + (q31_t)0xE4B8CD10, (q31_t)0x831C314E, (q31_t)0xE3F47D95, + (q31_t)0x8348D8DB, (q31_t)0xE330734C, (q31_t)0x8376B422, + (q31_t)0xE26CB01A, (q31_t)0x83A5C2B0, (q31_t)0xE1A935E1, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x840777CF, + (q31_t)0xE02323E5, (q31_t)0x843A1D70, (q31_t)0xDF608FE3, + (q31_t)0x846DF476, (q31_t)0xDE9E4C60, (q31_t)0x84A2FC62, + (q31_t)0xDDDC5B3A, (q31_t)0x84D934B0, (q31_t)0xDD1ABE51, + (q31_t)0x85109CDC, (q31_t)0xDC597781, (q31_t)0x8549345C, + (q31_t)0xDB9888A8, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2, + (q31_t)0x85BDEF27, (q31_t)0xDA17BA4A, (q31_t)0x85FA1152, + (q31_t)0xD957DE7A, (q31_t)0x86376092, (q31_t)0xD898620C, + (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x86B583EE, + (q31_t)0xD71A8EB5, (q31_t)0x86F656D3, (q31_t)0xD65C3B7B, + (q31_t)0x8738545E, (q31_t)0xD59E4EFE, (q31_t)0x877B7BEC, + (q31_t)0xD4E0CB14, (q31_t)0x87BFCCD7, (q31_t)0xD423B190, + (q31_t)0x88054677, (q31_t)0xD3670445, (q31_t)0x884BE820, + (q31_t)0xD2AAC504, (q31_t)0x8893B124, (q31_t)0xD1EEF59E, + (q31_t)0x88DCA0D3, (q31_t)0xD13397E1, (q31_t)0x8926B677, + (q31_t)0xD078AD9D, (q31_t)0x8971F15A, (q31_t)0xCFBE389F, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8A0BD3F5, + (q31_t)0xCE4AB5A2, (q31_t)0x8A5A7A30, (q31_t)0xCD91AB38, + (q31_t)0x8AAA42B4, (q31_t)0xCCD91D3D, (q31_t)0x8AFB2CBA, + (q31_t)0xCC210D78, (q31_t)0x8B4D377C, (q31_t)0xCB697DB0, + (q31_t)0x8BA0622F, (q31_t)0xCAB26FA9, (q31_t)0x8BF4AC05, + (q31_t)0xC9FBE527, (q31_t)0x8C4A142F, (q31_t)0xC945DFEC, + (q31_t)0x8CA099D9, (q31_t)0xC89061BA, (q31_t)0x8CF83C30, + (q31_t)0xC7DB6C50, (q31_t)0x8D50FA59, (q31_t)0xC727016C, + (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8E05C6B7, + (q31_t)0xC5BFD22E, (q31_t)0x8E61D32D, (q31_t)0xC50D1148, + (q31_t)0x8EBEF7FB, (q31_t)0xC45AE1D7, (q31_t)0x8F1D343A, + (q31_t)0xC3A9458F, (q31_t)0x8F7C8701, (q31_t)0xC2F83E2A, + (q31_t)0x8FDCEF66, (q31_t)0xC247CD5A, (q31_t)0x903E6C7A, + (q31_t)0xC197F4D3, (q31_t)0x90A0FD4E, (q31_t)0xC0E8B648, + (q31_t)0x9104A0ED, (q31_t)0xC03A1368, (q31_t)0x91695663, + (q31_t)0xBF8C0DE2, (q31_t)0x91CF1CB6, (q31_t)0xBEDEA765, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x929DD805, + (q31_t)0xBD85BE2F, (q31_t)0x9306CB04, (q31_t)0xBCDA3ECA, + (q31_t)0x9370CAE4, (q31_t)0xBC2F6513, (q31_t)0x93DBD69F, + (q31_t)0xBB8532AF, (q31_t)0x9447ED2F, (q31_t)0xBADBA943, + (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x9523369B, + (q31_t)0xB98A97D8, (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0x96029EB5, (q31_t)0xB83C3DD1, (q31_t)0x9673DB94, + (q31_t)0xB796199B, (q31_t)0x96E61CDF, (q31_t)0xB6F0A811, + (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x97CDA855, + (q31_t)0xB5A7E362, (q31_t)0x9842F043, (q31_t)0xB5049368, + (q31_t)0x98B93828, (q31_t)0xB461FC70, (q31_t)0x99307EE0, + (q31_t)0xB3C0200C, (q31_t)0x99A8C344, (q31_t)0xB31EFFCB, + (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9A9C406D, + (q31_t)0xB1DEF9E8, (q31_t)0x9B1776D9, (q31_t)0xB140175B, + (q31_t)0x9B93A640, (q31_t)0xB0A1F71C, (q31_t)0x9C10CD70, + (q31_t)0xB0049AB2, (q31_t)0x9C8EEB33, (q31_t)0xAF6803A1, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9D8E0596, + (q31_t)0xAE312B91, (q31_t)0x9E0EFFC1, (q31_t)0xAD96ED91, + (q31_t)0x9E90EB94, (q31_t)0xACFD7AE8, (q31_t)0x9F13C7D0, + (q31_t)0xAC64D510, (q31_t)0x9F979331, (q31_t)0xABCCFD82, + (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA0A1F24C, + (q31_t)0xAA9FBF1D, (q31_t)0xA1288376, (q31_t)0xAA0A5B2D, + (q31_t)0xA1AFFEA2, (q31_t)0xA975CB56, (q31_t)0xA2386283, + (q31_t)0xA8E21106, (q31_t)0xA2C1ADC9, (q31_t)0xA84F2DA9, + (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA3D6F533, + (q31_t)0xA72BF173, (q31_t)0xA462EEAC, (q31_t)0xA69B9B68, + (q31_t)0xA4EFCA31, (q31_t)0xA60C21ED, (q31_t)0xA57D8666, + (q31_t)0xA57D8666, (q31_t)0xA60C21ED, (q31_t)0xA4EFCA31, + (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA72BF173, + (q31_t)0xA3D6F533, (q31_t)0xA7BD22AB, (q31_t)0xA34BDF20, + (q31_t)0xA84F2DA9, (q31_t)0xA2C1ADC9, (q31_t)0xA8E21106, + (q31_t)0xA2386283, (q31_t)0xA975CB56, (q31_t)0xA1AFFEA2, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAA9FBF1D, + (q31_t)0xA0A1F24C, (q31_t)0xAB35F5B5, (q31_t)0xA01C4C72, + (q31_t)0xABCCFD82, (q31_t)0x9F979331, (q31_t)0xAC64D510, + (q31_t)0x9F13C7D0, (q31_t)0xACFD7AE8, (q31_t)0x9E90EB94, + (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xAE312B91, + (q31_t)0x9D8E0596, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53, + (q31_t)0xAF6803A1, (q31_t)0x9C8EEB33, (q31_t)0xB0049AB2, + (q31_t)0x9C10CD70, (q31_t)0xB0A1F71C, (q31_t)0x9B93A640, + (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB1DEF9E8, + (q31_t)0x9A9C406D, (q31_t)0xB27E9D3B, (q31_t)0x9A22042C, + (q31_t)0xB31EFFCB, (q31_t)0x99A8C344, (q31_t)0xB3C0200C, + (q31_t)0x99307EE0, (q31_t)0xB461FC70, (q31_t)0x98B93828, + (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB5A7E362, + (q31_t)0x97CDA855, (q31_t)0xB64BEACC, (q31_t)0x9759617E, + (q31_t)0xB6F0A811, (q31_t)0x96E61CDF, (q31_t)0xB796199B, + (q31_t)0x9673DB94, (q31_t)0xB83C3DD1, (q31_t)0x96029EB5, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xB98A97D8, + (q31_t)0x9523369B, (q31_t)0xBA32CA70, (q31_t)0x94B50D87, + (q31_t)0xBADBA943, (q31_t)0x9447ED2F, (q31_t)0xBB8532AF, + (q31_t)0x93DBD69F, (q31_t)0xBC2F6513, (q31_t)0x9370CAE4, + (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBD85BE2F, + (q31_t)0x929DD805, (q31_t)0xBE31E19B, (q31_t)0x9235F2EB, + (q31_t)0xBEDEA765, (q31_t)0x91CF1CB6, (q31_t)0xBF8C0DE2, + (q31_t)0x91695663, (q31_t)0xC03A1368, (q31_t)0x9104A0ED, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC197F4D3, + (q31_t)0x903E6C7A, (q31_t)0xC247CD5A, (q31_t)0x8FDCEF66, + (q31_t)0xC2F83E2A, (q31_t)0x8F7C8701, (q31_t)0xC3A9458F, + (q31_t)0x8F1D343A, (q31_t)0xC45AE1D7, (q31_t)0x8EBEF7FB, + (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC5BFD22E, + (q31_t)0x8E05C6B7, (q31_t)0xC67322CD, (q31_t)0x8DAAD37B, + (q31_t)0xC727016C, (q31_t)0x8D50FA59, (q31_t)0xC7DB6C50, + (q31_t)0x8CF83C30, (q31_t)0xC89061BA, (q31_t)0x8CA099D9, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xC9FBE527, + (q31_t)0x8BF4AC05, (q31_t)0xCAB26FA9, (q31_t)0x8BA0622F, + (q31_t)0xCB697DB0, (q31_t)0x8B4D377C, (q31_t)0xCC210D78, + (q31_t)0x8AFB2CBA, (q31_t)0xCCD91D3D, (q31_t)0x8AAA42B4, + (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCE4AB5A2, + (q31_t)0x8A0BD3F5, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xCFBE389F, (q31_t)0x8971F15A, (q31_t)0xD078AD9D, + (q31_t)0x8926B677, (q31_t)0xD13397E1, (q31_t)0x88DCA0D3, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD2AAC504, + (q31_t)0x884BE820, (q31_t)0xD3670445, (q31_t)0x88054677, + (q31_t)0xD423B190, (q31_t)0x87BFCCD7, (q31_t)0xD4E0CB14, + (q31_t)0x877B7BEC, (q31_t)0xD59E4EFE, (q31_t)0x8738545E, + (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD71A8EB5, + (q31_t)0x86B583EE, (q31_t)0xD7D946D7, (q31_t)0x8675DC4E, + (q31_t)0xD898620C, (q31_t)0x86376092, (q31_t)0xD957DE7A, + (q31_t)0x85FA1152, (q31_t)0xDA17BA4A, (q31_t)0x85BDEF27, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDB9888A8, + (q31_t)0x8549345C, (q31_t)0xDC597781, (q31_t)0x85109CDC, + (q31_t)0xDD1ABE51, (q31_t)0x84D934B0, (q31_t)0xDDDC5B3A, + (q31_t)0x84A2FC62, (q31_t)0xDE9E4C60, (q31_t)0x846DF476, + (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xE02323E5, + (q31_t)0x840777CF, (q31_t)0xE0E60684, (q31_t)0x83D60411, + (q31_t)0xE1A935E1, (q31_t)0x83A5C2B0, (q31_t)0xE26CB01A, + (q31_t)0x8376B422, (q31_t)0xE330734C, (q31_t)0x8348D8DB, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE4B8CD10, + (q31_t)0x82F0BDE8, (q31_t)0xE57D5FDA, (q31_t)0x82C67F13, + (q31_t)0xE642340D, (q31_t)0x829D753A, (q31_t)0xE70747C3, + (q31_t)0x8275A0C0, (q31_t)0xE7CC9917, (q31_t)0x824F0208, + (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xE957ECFB, + (q31_t)0x82056758, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16, + (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEBAA894E, + (q31_t)0x81A01B6C, (q31_t)0xEC71244F, (q31_t)0x8180C6A9, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xEDFEE92B, + (q31_t)0x8145C5C6, (q31_t)0xEEC60F31, (q31_t)0x812A1A39, + (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xF054D8D4, + (q31_t)0x80F66E3C, (q31_t)0xF11C789A, (q31_t)0x80DE6E4C, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF2AC246D, + (q31_t)0x80B21BAF, (q31_t)0xF3742CA1, (q31_t)0x809DC970, + (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF50497FA, + (q31_t)0x8078D40D, (q31_t)0xF5CCF743, (q31_t)0x80683143, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF75DFF65, + (q31_t)0x804A9C4D, (q31_t)0xF826A461, (q31_t)0x803DAA69, + (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF9B82683, + (q31_t)0x80277872, (q31_t)0xFA80FFCB, (q31_t)0x801E3894, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFC12D919, + (q31_t)0x800F6B88, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D, + (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFE6DE2E0, + (q31_t)0x800277A5, (q31_t)0xFF36F078, (q31_t)0x80009DE9 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par +
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 2048, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_2048_q31[3072] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFFD885, + (q31_t)0x006487E3, (q31_t)0x7FFF6216, (q31_t)0x00C90F88, + (q31_t)0x7FFE9CB2, (q31_t)0x012D96B0, (q31_t)0x7FFD885A, + (q31_t)0x01921D1F, (q31_t)0x7FFC250F, (q31_t)0x01F6A296, + (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF871A1, + (q31_t)0x02BFA9A4, (q31_t)0x7FF62182, (q31_t)0x03242ABF, + (q31_t)0x7FF38273, (q31_t)0x0388A9E9, (q31_t)0x7FF09477, + (q31_t)0x03ED26E6, (q31_t)0x7FED5790, (q31_t)0x0451A176, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE5F108, + (q31_t)0x051A8E5C, (q31_t)0x7FE1C76B, (q31_t)0x057F0034, + (q31_t)0x7FDD4EEC, (q31_t)0x05E36EA9, (q31_t)0x7FD8878D, + (q31_t)0x0647D97C, (q31_t)0x7FD37152, (q31_t)0x06AC406F, + (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FC85853, + (q31_t)0x077501BE, (q31_t)0x7FC25596, (q31_t)0x07D95B9E, + (q31_t)0x7FBC040A, (q31_t)0x083DB0A7, (q31_t)0x7FB563B2, + (q31_t)0x08A2009A, (q31_t)0x7FAE7494, (q31_t)0x09064B3A, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F9FAA15, + (q31_t)0x09CECF89, (q31_t)0x7F97CEBC, (q31_t)0x0A3308BC, + (q31_t)0x7F8FA4AF, (q31_t)0x0A973BA5, (q31_t)0x7F872BF3, + (q31_t)0x0AFB6805, (q31_t)0x7F7E648B, (q31_t)0x0B5F8D9F, + (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F6BE9D4, + (q31_t)0x0C27C389, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E, + (q31_t)0x7F5834B6, (q31_t)0x0CEFDB75, (q31_t)0x7F4DE450, + (q31_t)0x0D53DB92, (q31_t)0x7F434563, (q31_t)0x0DB7D376, + (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F2D1C0E, + (q31_t)0x0E7FA99D, (q31_t)0x7F2191B4, (q31_t)0x0EE38765, + (q31_t)0x7F15B8EE, (q31_t)0x0F475BFE, (q31_t)0x7F0991C3, + (q31_t)0x0FAB272B, (q31_t)0x7EFD1C3C, (q31_t)0x100EE8AD, + (q31_t)0x7EF0585F, (q31_t)0x1072A047, (q31_t)0x7EE34635, + (q31_t)0x10D64DBC, (q31_t)0x7ED5E5C6, (q31_t)0x1139F0CE, + (q31_t)0x7EC8371A, (q31_t)0x119D8940, (q31_t)0x7EBA3A39, + (q31_t)0x120116D4, (q31_t)0x7EABEF2C, (q31_t)0x1264994E, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E8E6EB1, + (q31_t)0x132B7BF9, (q31_t)0x7E7F3956, (q31_t)0x138EDBB0, + (q31_t)0x7E6FB5F3, (q31_t)0x13F22F57, (q31_t)0x7E5FE493, + (q31_t)0x145576B1, (q31_t)0x7E4FC53E, (q31_t)0x14B8B17F, + (q31_t)0x7E3F57FE, (q31_t)0x151BDF85, (q31_t)0x7E2E9CDF, + (q31_t)0x157F0086, (q31_t)0x7E1D93E9, (q31_t)0x15E21444, + (q31_t)0x7E0C3D29, (q31_t)0x16451A83, (q31_t)0x7DFA98A7, + (q31_t)0x16A81305, (q31_t)0x7DE8A670, (q31_t)0x170AFD8D, + (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7DC3D90D, + (q31_t)0x17D0A7BB, (q31_t)0x7DB0FDF7, (q31_t)0x183366E8, + (q31_t)0x7D9DD55A, (q31_t)0x18961727, (q31_t)0x7D8A5F3F, + (q31_t)0x18F8B83C, (q31_t)0x7D769BB5, (q31_t)0x195B49E9, + (q31_t)0x7D628AC5, (q31_t)0x19BDCBF2, (q31_t)0x7D4E2C7E, + (q31_t)0x1A203E1B, (q31_t)0x7D3980EC, (q31_t)0x1A82A025, + (q31_t)0x7D24881A, (q31_t)0x1AE4F1D6, (q31_t)0x7D0F4218, + (q31_t)0x1B4732EF, (q31_t)0x7CF9AEF0, (q31_t)0x1BA96334, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7CCDA168, + (q31_t)0x1C6D9053, (q31_t)0x7CB72724, (q31_t)0x1CCF8CB3, + (q31_t)0x7CA05FF1, (q31_t)0x1D31774D, (q31_t)0x7C894BDD, + (q31_t)0x1D934FE5, (q31_t)0x7C71EAF8, (q31_t)0x1DF5163F, + (q31_t)0x7C5A3D4F, (q31_t)0x1E56CA1E, (q31_t)0x7C4242F2, + (q31_t)0x1EB86B46, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B, + (q31_t)0x7C116853, (q31_t)0x1F7B7480, (q31_t)0x7BF88830, + (q31_t)0x1FDCDC1A, (q31_t)0x7BDF5B94, (q31_t)0x203E300D, + (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7BAC1D31, + (q31_t)0x21009C0B, (q31_t)0x7B920B89, (q31_t)0x2161B39F, + (q31_t)0x7B77ADA8, (q31_t)0x21C2B69C, (q31_t)0x7B5D039D, + (q31_t)0x2223A4C5, (q31_t)0x7B420D7A, (q31_t)0x22847DDF, + (q31_t)0x7B26CB4F, (q31_t)0x22E541AE, (q31_t)0x7B0B3D2C, + (q31_t)0x2345EFF7, (q31_t)0x7AEF6323, (q31_t)0x23A6887E, + (q31_t)0x7AD33D45, (q31_t)0x24070B07, (q31_t)0x7AB6CBA3, + (q31_t)0x24677757, (q31_t)0x7A9A0E4F, (q31_t)0x24C7CD32, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A5FB0D8, + (q31_t)0x2588349D, (q31_t)0x7A4210D8, (q31_t)0x25E845B5, + (q31_t)0x7A24256E, (q31_t)0x26483F6C, (q31_t)0x7A05EEAD, + (q31_t)0x26A82185, (q31_t)0x79E76CA6, (q31_t)0x2707EBC6, + (q31_t)0x79C89F6D, (q31_t)0x27679DF4, (q31_t)0x79A98715, + (q31_t)0x27C737D2, (q31_t)0x798A23B1, (q31_t)0x2826B928, + (q31_t)0x796A7554, (q31_t)0x288621B9, (q31_t)0x794A7C11, + (q31_t)0x28E5714A, (q31_t)0x792A37FE, (q31_t)0x2944A7A2, + (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78E8CFB1, + (q31_t)0x2A02C7B8, (q31_t)0x78C7ABA1, (q31_t)0x2A61B101, + (q31_t)0x78A63D10, (q31_t)0x2AC08025, (q31_t)0x78848413, + (q31_t)0x2B1F34EB, (q31_t)0x786280BF, (q31_t)0x2B7DCF17, + (q31_t)0x78403328, (q31_t)0x2BDC4E6F, (q31_t)0x781D9B64, + (q31_t)0x2C3AB2B9, (q31_t)0x77FAB988, (q31_t)0x2C98FBBA, + (q31_t)0x77D78DAA, (q31_t)0x2CF72939, (q31_t)0x77B417DF, + (q31_t)0x2D553AFB, (q31_t)0x7790583D, (q31_t)0x2DB330C7, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x7747FBCE, + (q31_t)0x2E6EC792, (q31_t)0x77235F2D, (q31_t)0x2ECC681E, + (q31_t)0x76FE790E, (q31_t)0x2F29EBCC, (q31_t)0x76D94988, + (q31_t)0x2F875262, (q31_t)0x76B3D0B3, (q31_t)0x2FE49BA6, + (q31_t)0x768E0EA5, (q31_t)0x3041C760, (q31_t)0x76680376, + (q31_t)0x309ED555, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x761B1211, (q31_t)0x3158970D, (q31_t)0x75F42C0A, + (q31_t)0x31B54A5D, (q31_t)0x75CCFD42, (q31_t)0x3211DF03, + (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x757DC5CA, + (q31_t)0x32CAAB6F, (q31_t)0x7555BD4B, (q31_t)0x3326E2C2, + (q31_t)0x752D6C6C, (q31_t)0x3382FA88, (q31_t)0x7504D345, + (q31_t)0x33DEF287, (q31_t)0x74DBF1EF, (q31_t)0x343ACA87, + (q31_t)0x74B2C883, (q31_t)0x3496824F, (q31_t)0x7489571B, + (q31_t)0x34F219A7, (q31_t)0x745F9DD1, (q31_t)0x354D9056, + (q31_t)0x74359CBD, (q31_t)0x35A8E624, (q31_t)0x740B53FA, + (q31_t)0x36041AD9, (q31_t)0x73E0C3A3, (q31_t)0x365F2E3B, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x738ACC9E, + (q31_t)0x3714F02A, (q31_t)0x735F6626, (q31_t)0x376F9E46, + (q31_t)0x7333B883, (q31_t)0x37CA2A30, (q31_t)0x7307C3D0, + (q31_t)0x382493B0, (q31_t)0x72DB8828, (q31_t)0x387EDA8E, + (q31_t)0x72AF05A6, (q31_t)0x38D8FE93, (q31_t)0x72823C66, + (q31_t)0x3932FF87, (q31_t)0x72552C84, (q31_t)0x398CDD32, + (q31_t)0x7227D61C, (q31_t)0x39E6975D, (q31_t)0x71FA3948, + (q31_t)0x3A402DD1, (q31_t)0x71CC5626, (q31_t)0x3A99A057, + (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x716FBD68, + (q31_t)0x3B4C18BA, (q31_t)0x71410804, (q31_t)0x3BA51E29, + (q31_t)0x71120CC5, (q31_t)0x3BFDFECD, (q31_t)0x70E2CBC6, + (q31_t)0x3C56BA70, (q31_t)0x70B34524, (q31_t)0x3CAF50DA, + (q31_t)0x708378FE, (q31_t)0x3D07C1D5, (q31_t)0x70536771, + (q31_t)0x3D600D2B, (q31_t)0x70231099, (q31_t)0x3DB832A5, + (q31_t)0x6FF27496, (q31_t)0x3E10320D, (q31_t)0x6FC19385, + (q31_t)0x3E680B2C, (q31_t)0x6F906D84, (q31_t)0x3EBFBDCC, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6F2D532C, + (q31_t)0x3F6EAEB8, (q31_t)0x6EFB5F12, (q31_t)0x3FC5EC97, + (q31_t)0x6EC92682, (q31_t)0x401D0320, (q31_t)0x6E96A99C, + (q31_t)0x4073F21D, (q31_t)0x6E63E87F, (q31_t)0x40CAB957, + (q31_t)0x6E30E349, (q31_t)0x4121589A, (q31_t)0x6DFD9A1B, + (q31_t)0x4177CFB0, (q31_t)0x6DCA0D14, (q31_t)0x41CE1E64, + (q31_t)0x6D963C54, (q31_t)0x42244480, (q31_t)0x6D6227FA, + (q31_t)0x427A41D0, (q31_t)0x6D2DD027, (q31_t)0x42D0161E, + (q31_t)0x6CF934FB, (q31_t)0x4325C135, (q31_t)0x6CC45697, + (q31_t)0x437B42E1, (q31_t)0x6C8F351C, (q31_t)0x43D09AEC, + (q31_t)0x6C59D0A9, (q31_t)0x4425C923, (q31_t)0x6C242960, + (q31_t)0x447ACD50, (q31_t)0x6BEE3F62, (q31_t)0x44CFA73F, + (q31_t)0x6BB812D0, (q31_t)0x452456BC, (q31_t)0x6B81A3CD, + (q31_t)0x4578DB93, (q31_t)0x6B4AF278, (q31_t)0x45CD358F, + (q31_t)0x6B13FEF5, (q31_t)0x4621647C, (q31_t)0x6ADCC964, + (q31_t)0x46756827, (q31_t)0x6AA551E8, (q31_t)0x46C9405C, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x6A359DB9, + (q31_t)0x47706D93, (q31_t)0x69FD614A, (q31_t)0x47C3C22E, + (q31_t)0x69C4E37A, (q31_t)0x4816EA85, (q31_t)0x698C246C, + (q31_t)0x4869E664, (q31_t)0x69532442, (q31_t)0x48BCB598, + (q31_t)0x6919E320, (q31_t)0x490F57EE, (q31_t)0x68E06129, + (q31_t)0x4961CD32, (q31_t)0x68A69E81, (q31_t)0x49B41533, + (q31_t)0x686C9B4B, (q31_t)0x4A062FBD, (q31_t)0x683257AA, + (q31_t)0x4A581C9D, (q31_t)0x67F7D3C4, (q31_t)0x4AA9DBA1, + (q31_t)0x67BD0FBC, (q31_t)0x4AFB6C97, (q31_t)0x67820BB6, + (q31_t)0x4B4CCF4D, (q31_t)0x6746C7D7, (q31_t)0x4B9E038F, + (q31_t)0x670B4443, (q31_t)0x4BEF092D, (q31_t)0x66CF811F, + (q31_t)0x4C3FDFF3, (q31_t)0x66937E90, (q31_t)0x4C9087B1, + (q31_t)0x66573CBB, (q31_t)0x4CE10034, (q31_t)0x661ABBC5, + (q31_t)0x4D31494B, (q31_t)0x65DDFBD3, (q31_t)0x4D8162C4, + (q31_t)0x65A0FD0B, (q31_t)0x4DD14C6E, (q31_t)0x6563BF92, + (q31_t)0x4E210617, (q31_t)0x6526438E, (q31_t)0x4E708F8F, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x64AA907F, + (q31_t)0x4F0F1126, (q31_t)0x646C59BF, (q31_t)0x4F5E08E3, + (q31_t)0x642DE50D, (q31_t)0x4FACCFAB, (q31_t)0x63EF328F, + (q31_t)0x4FFB654D, (q31_t)0x63B0426D, (q31_t)0x5049C999, + (q31_t)0x637114CC, (q31_t)0x5097FC5E, (q31_t)0x6331A9D4, + (q31_t)0x50E5FD6C, (q31_t)0x62F201AC, (q31_t)0x5133CC94, + (q31_t)0x62B21C7B, (q31_t)0x518169A4, (q31_t)0x6271FA69, + (q31_t)0x51CED46E, (q31_t)0x62319B9D, (q31_t)0x521C0CC1, + (q31_t)0x61F1003E, (q31_t)0x5269126E, (q31_t)0x61B02876, + (q31_t)0x52B5E545, (q31_t)0x616F146B, (q31_t)0x53028517, + (q31_t)0x612DC446, (q31_t)0x534EF1B5, (q31_t)0x60EC3830, + (q31_t)0x539B2AEF, (q31_t)0x60AA704F, (q31_t)0x53E73097, + (q31_t)0x60686CCE, (q31_t)0x5433027D, (q31_t)0x60262DD5, + (q31_t)0x547EA073, (q31_t)0x5FE3B38D, (q31_t)0x54CA0A4A, + (q31_t)0x5FA0FE1E, (q31_t)0x55153FD4, (q31_t)0x5F5E0DB3, + (q31_t)0x556040E2, (q31_t)0x5F1AE273, (q31_t)0x55AB0D46, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5E93DC1F, + (q31_t)0x56400757, (q31_t)0x5E50015D, (q31_t)0x568A34A9, + (q31_t)0x5E0BEC6E, (q31_t)0x56D42C99, (q31_t)0x5DC79D7C, + (q31_t)0x571DEEF9, (q31_t)0x5D8314B0, (q31_t)0x57677B9D, + (q31_t)0x5D3E5236, (q31_t)0x57B0D256, (q31_t)0x5CF95638, + (q31_t)0x57F9F2F7, (q31_t)0x5CB420DF, (q31_t)0x5842DD54, + (q31_t)0x5C6EB258, (q31_t)0x588B913F, (q31_t)0x5C290ACC, + (q31_t)0x58D40E8C, (q31_t)0x5BE32A67, (q31_t)0x591C550E, + (q31_t)0x5B9D1153, (q31_t)0x59646497, (q31_t)0x5B56BFBD, + (q31_t)0x59AC3CFD, (q31_t)0x5B1035CF, (q31_t)0x59F3DE12, + (q31_t)0x5AC973B4, (q31_t)0x5A3B47AA, (q31_t)0x5A82799A, + (q31_t)0x5A82799A, (q31_t)0x5A3B47AA, (q31_t)0x5AC973B4, + (q31_t)0x59F3DE12, (q31_t)0x5B1035CF, (q31_t)0x59AC3CFD, + (q31_t)0x5B56BFBD, (q31_t)0x59646497, (q31_t)0x5B9D1153, + (q31_t)0x591C550E, (q31_t)0x5BE32A67, (q31_t)0x58D40E8C, + (q31_t)0x5C290ACC, (q31_t)0x588B913F, (q31_t)0x5C6EB258, + (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x57F9F2F7, + (q31_t)0x5CF95638, (q31_t)0x57B0D256, (q31_t)0x5D3E5236, + (q31_t)0x57677B9D, (q31_t)0x5D8314B0, (q31_t)0x571DEEF9, + (q31_t)0x5DC79D7C, (q31_t)0x56D42C99, (q31_t)0x5E0BEC6E, + (q31_t)0x568A34A9, (q31_t)0x5E50015D, (q31_t)0x56400757, + (q31_t)0x5E93DC1F, (q31_t)0x55F5A4D2, (q31_t)0x5ED77C89, + (q31_t)0x55AB0D46, (q31_t)0x5F1AE273, (q31_t)0x556040E2, + (q31_t)0x5F5E0DB3, (q31_t)0x55153FD4, (q31_t)0x5FA0FE1E, + (q31_t)0x54CA0A4A, (q31_t)0x5FE3B38D, (q31_t)0x547EA073, + (q31_t)0x60262DD5, (q31_t)0x5433027D, (q31_t)0x60686CCE, + (q31_t)0x53E73097, (q31_t)0x60AA704F, (q31_t)0x539B2AEF, + (q31_t)0x60EC3830, (q31_t)0x534EF1B5, (q31_t)0x612DC446, + (q31_t)0x53028517, (q31_t)0x616F146B, (q31_t)0x52B5E545, + (q31_t)0x61B02876, (q31_t)0x5269126E, (q31_t)0x61F1003E, + (q31_t)0x521C0CC1, (q31_t)0x62319B9D, (q31_t)0x51CED46E, + (q31_t)0x6271FA69, (q31_t)0x518169A4, (q31_t)0x62B21C7B, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x50E5FD6C, + (q31_t)0x6331A9D4, (q31_t)0x5097FC5E, (q31_t)0x637114CC, + (q31_t)0x5049C999, (q31_t)0x63B0426D, (q31_t)0x4FFB654D, + (q31_t)0x63EF328F, (q31_t)0x4FACCFAB, (q31_t)0x642DE50D, + (q31_t)0x4F5E08E3, (q31_t)0x646C59BF, (q31_t)0x4F0F1126, + (q31_t)0x64AA907F, (q31_t)0x4EBFE8A4, (q31_t)0x64E88926, + (q31_t)0x4E708F8F, (q31_t)0x6526438E, (q31_t)0x4E210617, + (q31_t)0x6563BF92, (q31_t)0x4DD14C6E, (q31_t)0x65A0FD0B, + (q31_t)0x4D8162C4, (q31_t)0x65DDFBD3, (q31_t)0x4D31494B, + (q31_t)0x661ABBC5, (q31_t)0x4CE10034, (q31_t)0x66573CBB, + (q31_t)0x4C9087B1, (q31_t)0x66937E90, (q31_t)0x4C3FDFF3, + (q31_t)0x66CF811F, (q31_t)0x4BEF092D, (q31_t)0x670B4443, + (q31_t)0x4B9E038F, (q31_t)0x6746C7D7, (q31_t)0x4B4CCF4D, + (q31_t)0x67820BB6, (q31_t)0x4AFB6C97, (q31_t)0x67BD0FBC, + (q31_t)0x4AA9DBA1, (q31_t)0x67F7D3C4, (q31_t)0x4A581C9D, + (q31_t)0x683257AA, (q31_t)0x4A062FBD, (q31_t)0x686C9B4B, + (q31_t)0x49B41533, (q31_t)0x68A69E81, (q31_t)0x4961CD32, + (q31_t)0x68E06129, (q31_t)0x490F57EE, (q31_t)0x6919E320, + (q31_t)0x48BCB598, (q31_t)0x69532442, (q31_t)0x4869E664, + (q31_t)0x698C246C, (q31_t)0x4816EA85, (q31_t)0x69C4E37A, + (q31_t)0x47C3C22E, (q31_t)0x69FD614A, (q31_t)0x47706D93, + (q31_t)0x6A359DB9, (q31_t)0x471CECE6, (q31_t)0x6A6D98A4, + (q31_t)0x46C9405C, (q31_t)0x6AA551E8, (q31_t)0x46756827, + (q31_t)0x6ADCC964, (q31_t)0x4621647C, (q31_t)0x6B13FEF5, + (q31_t)0x45CD358F, (q31_t)0x6B4AF278, (q31_t)0x4578DB93, + (q31_t)0x6B81A3CD, (q31_t)0x452456BC, (q31_t)0x6BB812D0, + (q31_t)0x44CFA73F, (q31_t)0x6BEE3F62, (q31_t)0x447ACD50, + (q31_t)0x6C242960, (q31_t)0x4425C923, (q31_t)0x6C59D0A9, + (q31_t)0x43D09AEC, (q31_t)0x6C8F351C, (q31_t)0x437B42E1, + (q31_t)0x6CC45697, (q31_t)0x4325C135, (q31_t)0x6CF934FB, + (q31_t)0x42D0161E, (q31_t)0x6D2DD027, (q31_t)0x427A41D0, + (q31_t)0x6D6227FA, (q31_t)0x42244480, (q31_t)0x6D963C54, + (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x4177CFB0, + (q31_t)0x6DFD9A1B, (q31_t)0x4121589A, (q31_t)0x6E30E349, + (q31_t)0x40CAB957, (q31_t)0x6E63E87F, (q31_t)0x4073F21D, + (q31_t)0x6E96A99C, (q31_t)0x401D0320, (q31_t)0x6EC92682, + (q31_t)0x3FC5EC97, (q31_t)0x6EFB5F12, (q31_t)0x3F6EAEB8, + (q31_t)0x6F2D532C, (q31_t)0x3F1749B7, (q31_t)0x6F5F02B1, + (q31_t)0x3EBFBDCC, (q31_t)0x6F906D84, (q31_t)0x3E680B2C, + (q31_t)0x6FC19385, (q31_t)0x3E10320D, (q31_t)0x6FF27496, + (q31_t)0x3DB832A5, (q31_t)0x70231099, (q31_t)0x3D600D2B, + (q31_t)0x70536771, (q31_t)0x3D07C1D5, (q31_t)0x708378FE, + (q31_t)0x3CAF50DA, (q31_t)0x70B34524, (q31_t)0x3C56BA70, + (q31_t)0x70E2CBC6, (q31_t)0x3BFDFECD, (q31_t)0x71120CC5, + (q31_t)0x3BA51E29, (q31_t)0x71410804, (q31_t)0x3B4C18BA, + (q31_t)0x716FBD68, (q31_t)0x3AF2EEB7, (q31_t)0x719E2CD2, + (q31_t)0x3A99A057, (q31_t)0x71CC5626, (q31_t)0x3A402DD1, + (q31_t)0x71FA3948, (q31_t)0x39E6975D, (q31_t)0x7227D61C, + (q31_t)0x398CDD32, (q31_t)0x72552C84, (q31_t)0x3932FF87, + (q31_t)0x72823C66, (q31_t)0x38D8FE93, (q31_t)0x72AF05A6, + (q31_t)0x387EDA8E, (q31_t)0x72DB8828, (q31_t)0x382493B0, + (q31_t)0x7307C3D0, (q31_t)0x37CA2A30, (q31_t)0x7333B883, + (q31_t)0x376F9E46, (q31_t)0x735F6626, (q31_t)0x3714F02A, + (q31_t)0x738ACC9E, (q31_t)0x36BA2013, (q31_t)0x73B5EBD0, + (q31_t)0x365F2E3B, (q31_t)0x73E0C3A3, (q31_t)0x36041AD9, + (q31_t)0x740B53FA, (q31_t)0x35A8E624, (q31_t)0x74359CBD, + (q31_t)0x354D9056, (q31_t)0x745F9DD1, (q31_t)0x34F219A7, + (q31_t)0x7489571B, (q31_t)0x3496824F, (q31_t)0x74B2C883, + (q31_t)0x343ACA87, (q31_t)0x74DBF1EF, (q31_t)0x33DEF287, + (q31_t)0x7504D345, (q31_t)0x3382FA88, (q31_t)0x752D6C6C, + (q31_t)0x3326E2C2, (q31_t)0x7555BD4B, (q31_t)0x32CAAB6F, + (q31_t)0x757DC5CA, (q31_t)0x326E54C7, (q31_t)0x75A585CF, + (q31_t)0x3211DF03, (q31_t)0x75CCFD42, (q31_t)0x31B54A5D, + (q31_t)0x75F42C0A, (q31_t)0x3158970D, (q31_t)0x761B1211, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x309ED555, + (q31_t)0x76680376, (q31_t)0x3041C760, (q31_t)0x768E0EA5, + (q31_t)0x2FE49BA6, (q31_t)0x76B3D0B3, (q31_t)0x2F875262, + (q31_t)0x76D94988, (q31_t)0x2F29EBCC, (q31_t)0x76FE790E, + (q31_t)0x2ECC681E, (q31_t)0x77235F2D, (q31_t)0x2E6EC792, + (q31_t)0x7747FBCE, (q31_t)0x2E110A62, (q31_t)0x776C4EDB, + (q31_t)0x2DB330C7, (q31_t)0x7790583D, (q31_t)0x2D553AFB, + (q31_t)0x77B417DF, (q31_t)0x2CF72939, (q31_t)0x77D78DAA, + (q31_t)0x2C98FBBA, (q31_t)0x77FAB988, (q31_t)0x2C3AB2B9, + (q31_t)0x781D9B64, (q31_t)0x2BDC4E6F, (q31_t)0x78403328, + (q31_t)0x2B7DCF17, (q31_t)0x786280BF, (q31_t)0x2B1F34EB, + (q31_t)0x78848413, (q31_t)0x2AC08025, (q31_t)0x78A63D10, + (q31_t)0x2A61B101, (q31_t)0x78C7ABA1, (q31_t)0x2A02C7B8, + (q31_t)0x78E8CFB1, (q31_t)0x29A3C484, (q31_t)0x7909A92C, + (q31_t)0x2944A7A2, (q31_t)0x792A37FE, (q31_t)0x28E5714A, + (q31_t)0x794A7C11, (q31_t)0x288621B9, (q31_t)0x796A7554, + (q31_t)0x2826B928, (q31_t)0x798A23B1, (q31_t)0x27C737D2, + (q31_t)0x79A98715, (q31_t)0x27679DF4, (q31_t)0x79C89F6D, + (q31_t)0x2707EBC6, (q31_t)0x79E76CA6, (q31_t)0x26A82185, + (q31_t)0x7A05EEAD, (q31_t)0x26483F6C, (q31_t)0x7A24256E, + (q31_t)0x25E845B5, (q31_t)0x7A4210D8, (q31_t)0x2588349D, + (q31_t)0x7A5FB0D8, (q31_t)0x25280C5D, (q31_t)0x7A7D055B, + (q31_t)0x24C7CD32, (q31_t)0x7A9A0E4F, (q31_t)0x24677757, + (q31_t)0x7AB6CBA3, (q31_t)0x24070B07, (q31_t)0x7AD33D45, + (q31_t)0x23A6887E, (q31_t)0x7AEF6323, (q31_t)0x2345EFF7, + (q31_t)0x7B0B3D2C, (q31_t)0x22E541AE, (q31_t)0x7B26CB4F, + (q31_t)0x22847DDF, (q31_t)0x7B420D7A, (q31_t)0x2223A4C5, + (q31_t)0x7B5D039D, (q31_t)0x21C2B69C, (q31_t)0x7B77ADA8, + (q31_t)0x2161B39F, (q31_t)0x7B920B89, (q31_t)0x21009C0B, + (q31_t)0x7BAC1D31, (q31_t)0x209F701C, (q31_t)0x7BC5E28F, + (q31_t)0x203E300D, (q31_t)0x7BDF5B94, (q31_t)0x1FDCDC1A, + (q31_t)0x7BF88830, (q31_t)0x1F7B7480, (q31_t)0x7C116853, + (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x1EB86B46, + (q31_t)0x7C4242F2, (q31_t)0x1E56CA1E, (q31_t)0x7C5A3D4F, + (q31_t)0x1DF5163F, (q31_t)0x7C71EAF8, (q31_t)0x1D934FE5, + (q31_t)0x7C894BDD, (q31_t)0x1D31774D, (q31_t)0x7CA05FF1, + (q31_t)0x1CCF8CB3, (q31_t)0x7CB72724, (q31_t)0x1C6D9053, + (q31_t)0x7CCDA168, (q31_t)0x1C0B826A, (q31_t)0x7CE3CEB1, + (q31_t)0x1BA96334, (q31_t)0x7CF9AEF0, (q31_t)0x1B4732EF, + (q31_t)0x7D0F4218, (q31_t)0x1AE4F1D6, (q31_t)0x7D24881A, + (q31_t)0x1A82A025, (q31_t)0x7D3980EC, (q31_t)0x1A203E1B, + (q31_t)0x7D4E2C7E, (q31_t)0x19BDCBF2, (q31_t)0x7D628AC5, + (q31_t)0x195B49E9, (q31_t)0x7D769BB5, (q31_t)0x18F8B83C, + (q31_t)0x7D8A5F3F, (q31_t)0x18961727, (q31_t)0x7D9DD55A, + (q31_t)0x183366E8, (q31_t)0x7DB0FDF7, (q31_t)0x17D0A7BB, + (q31_t)0x7DC3D90D, (q31_t)0x176DD9DE, (q31_t)0x7DD6668E, + (q31_t)0x170AFD8D, (q31_t)0x7DE8A670, (q31_t)0x16A81305, + (q31_t)0x7DFA98A7, (q31_t)0x16451A83, (q31_t)0x7E0C3D29, + (q31_t)0x15E21444, (q31_t)0x7E1D93E9, (q31_t)0x157F0086, + (q31_t)0x7E2E9CDF, (q31_t)0x151BDF85, (q31_t)0x7E3F57FE, + (q31_t)0x14B8B17F, (q31_t)0x7E4FC53E, (q31_t)0x145576B1, + (q31_t)0x7E5FE493, (q31_t)0x13F22F57, (q31_t)0x7E6FB5F3, + (q31_t)0x138EDBB0, (q31_t)0x7E7F3956, (q31_t)0x132B7BF9, + (q31_t)0x7E8E6EB1, (q31_t)0x12C8106E, (q31_t)0x7E9D55FC, + (q31_t)0x1264994E, (q31_t)0x7EABEF2C, (q31_t)0x120116D4, + (q31_t)0x7EBA3A39, (q31_t)0x119D8940, (q31_t)0x7EC8371A, + (q31_t)0x1139F0CE, (q31_t)0x7ED5E5C6, (q31_t)0x10D64DBC, + (q31_t)0x7EE34635, (q31_t)0x1072A047, (q31_t)0x7EF0585F, + (q31_t)0x100EE8AD, (q31_t)0x7EFD1C3C, (q31_t)0x0FAB272B, + (q31_t)0x7F0991C3, (q31_t)0x0F475BFE, (q31_t)0x7F15B8EE, + (q31_t)0x0EE38765, (q31_t)0x7F2191B4, (q31_t)0x0E7FA99D, + (q31_t)0x7F2D1C0E, (q31_t)0x0E1BC2E3, (q31_t)0x7F3857F5, + (q31_t)0x0DB7D376, (q31_t)0x7F434563, (q31_t)0x0D53DB92, + (q31_t)0x7F4DE450, (q31_t)0x0CEFDB75, (q31_t)0x7F5834B6, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x0C27C389, + (q31_t)0x7F6BE9D4, (q31_t)0x0BC3AC35, (q31_t)0x7F754E7F, + (q31_t)0x0B5F8D9F, (q31_t)0x7F7E648B, (q31_t)0x0AFB6805, + (q31_t)0x7F872BF3, (q31_t)0x0A973BA5, (q31_t)0x7F8FA4AF, + (q31_t)0x0A3308BC, (q31_t)0x7F97CEBC, (q31_t)0x09CECF89, + (q31_t)0x7F9FAA15, (q31_t)0x096A9049, (q31_t)0x7FA736B4, + (q31_t)0x09064B3A, (q31_t)0x7FAE7494, (q31_t)0x08A2009A, + (q31_t)0x7FB563B2, (q31_t)0x083DB0A7, (q31_t)0x7FBC040A, + (q31_t)0x07D95B9E, (q31_t)0x7FC25596, (q31_t)0x077501BE, + (q31_t)0x7FC85853, (q31_t)0x0710A344, (q31_t)0x7FCE0C3E, + (q31_t)0x06AC406F, (q31_t)0x7FD37152, (q31_t)0x0647D97C, + (q31_t)0x7FD8878D, (q31_t)0x05E36EA9, (q31_t)0x7FDD4EEC, + (q31_t)0x057F0034, (q31_t)0x7FE1C76B, (q31_t)0x051A8E5C, + (q31_t)0x7FE5F108, (q31_t)0x04B6195D, (q31_t)0x7FE9CBC0, + (q31_t)0x0451A176, (q31_t)0x7FED5790, (q31_t)0x03ED26E6, + (q31_t)0x7FF09477, (q31_t)0x0388A9E9, (q31_t)0x7FF38273, + (q31_t)0x03242ABF, (q31_t)0x7FF62182, (q31_t)0x02BFA9A4, + (q31_t)0x7FF871A1, (q31_t)0x025B26D7, (q31_t)0x7FFA72D1, + (q31_t)0x01F6A296, (q31_t)0x7FFC250F, (q31_t)0x01921D1F, + (q31_t)0x7FFD885A, (q31_t)0x012D96B0, (q31_t)0x7FFE9CB2, + (q31_t)0x00C90F88, (q31_t)0x7FFF6216, (q31_t)0x006487E3, + (q31_t)0x7FFFD885, (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xFF9B781D, (q31_t)0x7FFFD885, (q31_t)0xFF36F078, + (q31_t)0x7FFF6216, (q31_t)0xFED2694F, (q31_t)0x7FFE9CB2, + (q31_t)0xFE6DE2E0, (q31_t)0x7FFD885A, (q31_t)0xFE095D69, + (q31_t)0x7FFC250F, (q31_t)0xFDA4D928, (q31_t)0x7FFA72D1, + (q31_t)0xFD40565B, (q31_t)0x7FF871A1, (q31_t)0xFCDBD541, + (q31_t)0x7FF62182, (q31_t)0xFC775616, (q31_t)0x7FF38273, + (q31_t)0xFC12D919, (q31_t)0x7FF09477, (q31_t)0xFBAE5E89, + (q31_t)0x7FED5790, (q31_t)0xFB49E6A2, (q31_t)0x7FE9CBC0, + (q31_t)0xFAE571A4, (q31_t)0x7FE5F108, (q31_t)0xFA80FFCB, + (q31_t)0x7FE1C76B, (q31_t)0xFA1C9156, (q31_t)0x7FDD4EEC, + (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF953BF90, + (q31_t)0x7FD37152, (q31_t)0xF8EF5CBB, (q31_t)0x7FCE0C3E, + (q31_t)0xF88AFE41, (q31_t)0x7FC85853, (q31_t)0xF826A461, + (q31_t)0x7FC25596, (q31_t)0xF7C24F58, (q31_t)0x7FBC040A, + (q31_t)0xF75DFF65, (q31_t)0x7FB563B2, (q31_t)0xF6F9B4C5, + (q31_t)0x7FAE7494, (q31_t)0xF6956FB6, (q31_t)0x7FA736B4, + (q31_t)0xF6313076, (q31_t)0x7F9FAA15, (q31_t)0xF5CCF743, + (q31_t)0x7F97CEBC, (q31_t)0xF568C45A, (q31_t)0x7F8FA4AF, + (q31_t)0xF50497FA, (q31_t)0x7F872BF3, (q31_t)0xF4A07260, + (q31_t)0x7F7E648B, (q31_t)0xF43C53CA, (q31_t)0x7F754E7F, + (q31_t)0xF3D83C76, (q31_t)0x7F6BE9D4, (q31_t)0xF3742CA1, + (q31_t)0x7F62368F, (q31_t)0xF310248A, (q31_t)0x7F5834B6, + (q31_t)0xF2AC246D, (q31_t)0x7F4DE450, (q31_t)0xF2482C89, + (q31_t)0x7F434563, (q31_t)0xF1E43D1C, (q31_t)0x7F3857F5, + (q31_t)0xF1805662, (q31_t)0x7F2D1C0E, (q31_t)0xF11C789A, + (q31_t)0x7F2191B4, (q31_t)0xF0B8A401, (q31_t)0x7F15B8EE, + (q31_t)0xF054D8D4, (q31_t)0x7F0991C3, (q31_t)0xEFF11752, + (q31_t)0x7EFD1C3C, (q31_t)0xEF8D5FB8, (q31_t)0x7EF0585F, + (q31_t)0xEF29B243, (q31_t)0x7EE34635, (q31_t)0xEEC60F31, + (q31_t)0x7ED5E5C6, (q31_t)0xEE6276BF, (q31_t)0x7EC8371A, + (q31_t)0xEDFEE92B, (q31_t)0x7EBA3A39, (q31_t)0xED9B66B2, + (q31_t)0x7EABEF2C, (q31_t)0xED37EF91, (q31_t)0x7E9D55FC, + (q31_t)0xECD48406, (q31_t)0x7E8E6EB1, (q31_t)0xEC71244F, + (q31_t)0x7E7F3956, (q31_t)0xEC0DD0A8, (q31_t)0x7E6FB5F3, + (q31_t)0xEBAA894E, (q31_t)0x7E5FE493, (q31_t)0xEB474E80, + (q31_t)0x7E4FC53E, (q31_t)0xEAE4207A, (q31_t)0x7E3F57FE, + (q31_t)0xEA80FF79, (q31_t)0x7E2E9CDF, (q31_t)0xEA1DEBBB, + (q31_t)0x7E1D93E9, (q31_t)0xE9BAE57C, (q31_t)0x7E0C3D29, + (q31_t)0xE957ECFB, (q31_t)0x7DFA98A7, (q31_t)0xE8F50273, + (q31_t)0x7DE8A670, (q31_t)0xE8922621, (q31_t)0x7DD6668E, + (q31_t)0xE82F5844, (q31_t)0x7DC3D90D, (q31_t)0xE7CC9917, + (q31_t)0x7DB0FDF7, (q31_t)0xE769E8D8, (q31_t)0x7D9DD55A, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE6A4B616, + (q31_t)0x7D769BB5, (q31_t)0xE642340D, (q31_t)0x7D628AC5, + (q31_t)0xE5DFC1E4, (q31_t)0x7D4E2C7E, (q31_t)0xE57D5FDA, + (q31_t)0x7D3980EC, (q31_t)0xE51B0E2A, (q31_t)0x7D24881A, + (q31_t)0xE4B8CD10, (q31_t)0x7D0F4218, (q31_t)0xE4569CCB, + (q31_t)0x7CF9AEF0, (q31_t)0xE3F47D95, (q31_t)0x7CE3CEB1, + (q31_t)0xE3926FAC, (q31_t)0x7CCDA168, (q31_t)0xE330734C, + (q31_t)0x7CB72724, (q31_t)0xE2CE88B2, (q31_t)0x7CA05FF1, + (q31_t)0xE26CB01A, (q31_t)0x7C894BDD, (q31_t)0xE20AE9C1, + (q31_t)0x7C71EAF8, (q31_t)0xE1A935E1, (q31_t)0x7C5A3D4F, + (q31_t)0xE14794B9, (q31_t)0x7C4242F2, (q31_t)0xE0E60684, + (q31_t)0x7C29FBEE, (q31_t)0xE0848B7F, (q31_t)0x7C116853, + (q31_t)0xE02323E5, (q31_t)0x7BF88830, (q31_t)0xDFC1CFF2, + (q31_t)0x7BDF5B94, (q31_t)0xDF608FE3, (q31_t)0x7BC5E28F, + (q31_t)0xDEFF63F4, (q31_t)0x7BAC1D31, (q31_t)0xDE9E4C60, + (q31_t)0x7B920B89, (q31_t)0xDE3D4963, (q31_t)0x7B77ADA8, + (q31_t)0xDDDC5B3A, (q31_t)0x7B5D039D, (q31_t)0xDD7B8220, + (q31_t)0x7B420D7A, (q31_t)0xDD1ABE51, (q31_t)0x7B26CB4F, + (q31_t)0xDCBA1008, (q31_t)0x7B0B3D2C, (q31_t)0xDC597781, + (q31_t)0x7AEF6323, (q31_t)0xDBF8F4F8, (q31_t)0x7AD33D45, + (q31_t)0xDB9888A8, (q31_t)0x7AB6CBA3, (q31_t)0xDB3832CD, + (q31_t)0x7A9A0E4F, (q31_t)0xDAD7F3A2, (q31_t)0x7A7D055B, + (q31_t)0xDA77CB62, (q31_t)0x7A5FB0D8, (q31_t)0xDA17BA4A, + (q31_t)0x7A4210D8, (q31_t)0xD9B7C093, (q31_t)0x7A24256E, + (q31_t)0xD957DE7A, (q31_t)0x7A05EEAD, (q31_t)0xD8F81439, + (q31_t)0x79E76CA6, (q31_t)0xD898620C, (q31_t)0x79C89F6D, + (q31_t)0xD838C82D, (q31_t)0x79A98715, (q31_t)0xD7D946D7, + (q31_t)0x798A23B1, (q31_t)0xD779DE46, (q31_t)0x796A7554, + (q31_t)0xD71A8EB5, (q31_t)0x794A7C11, (q31_t)0xD6BB585D, + (q31_t)0x792A37FE, (q31_t)0xD65C3B7B, (q31_t)0x7909A92C, + (q31_t)0xD5FD3847, (q31_t)0x78E8CFB1, (q31_t)0xD59E4EFE, + (q31_t)0x78C7ABA1, (q31_t)0xD53F7FDA, (q31_t)0x78A63D10, + (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xD48230E8, + (q31_t)0x786280BF, (q31_t)0xD423B190, (q31_t)0x78403328, + (q31_t)0xD3C54D46, (q31_t)0x781D9B64, (q31_t)0xD3670445, + (q31_t)0x77FAB988, (q31_t)0xD308D6C6, (q31_t)0x77D78DAA, + (q31_t)0xD2AAC504, (q31_t)0x77B417DF, (q31_t)0xD24CCF38, + (q31_t)0x7790583D, (q31_t)0xD1EEF59E, (q31_t)0x776C4EDB, + (q31_t)0xD191386D, (q31_t)0x7747FBCE, (q31_t)0xD13397E1, + (q31_t)0x77235F2D, (q31_t)0xD0D61433, (q31_t)0x76FE790E, + (q31_t)0xD078AD9D, (q31_t)0x76D94988, (q31_t)0xD01B6459, + (q31_t)0x76B3D0B3, (q31_t)0xCFBE389F, (q31_t)0x768E0EA5, + (q31_t)0xCF612AAA, (q31_t)0x76680376, (q31_t)0xCF043AB2, + (q31_t)0x7641AF3C, (q31_t)0xCEA768F2, (q31_t)0x761B1211, + (q31_t)0xCE4AB5A2, (q31_t)0x75F42C0A, (q31_t)0xCDEE20FC, + (q31_t)0x75CCFD42, (q31_t)0xCD91AB38, (q31_t)0x75A585CF, + (q31_t)0xCD355490, (q31_t)0x757DC5CA, (q31_t)0xCCD91D3D, + (q31_t)0x7555BD4B, (q31_t)0xCC7D0577, (q31_t)0x752D6C6C, + (q31_t)0xCC210D78, (q31_t)0x7504D345, (q31_t)0xCBC53578, + (q31_t)0x74DBF1EF, (q31_t)0xCB697DB0, (q31_t)0x74B2C883, + (q31_t)0xCB0DE658, (q31_t)0x7489571B, (q31_t)0xCAB26FA9, + (q31_t)0x745F9DD1, (q31_t)0xCA5719DB, (q31_t)0x74359CBD, + (q31_t)0xC9FBE527, (q31_t)0x740B53FA, (q31_t)0xC9A0D1C4, + (q31_t)0x73E0C3A3, (q31_t)0xC945DFEC, (q31_t)0x73B5EBD0, + (q31_t)0xC8EB0FD6, (q31_t)0x738ACC9E, (q31_t)0xC89061BA, + (q31_t)0x735F6626, (q31_t)0xC835D5D0, (q31_t)0x7333B883, + (q31_t)0xC7DB6C50, (q31_t)0x7307C3D0, (q31_t)0xC7812571, + (q31_t)0x72DB8828, (q31_t)0xC727016C, (q31_t)0x72AF05A6, + (q31_t)0xC6CD0079, (q31_t)0x72823C66, (q31_t)0xC67322CD, + (q31_t)0x72552C84, (q31_t)0xC61968A2, (q31_t)0x7227D61C, + (q31_t)0xC5BFD22E, (q31_t)0x71FA3948, (q31_t)0xC5665FA8, + (q31_t)0x71CC5626, (q31_t)0xC50D1148, (q31_t)0x719E2CD2, + (q31_t)0xC4B3E746, (q31_t)0x716FBD68, (q31_t)0xC45AE1D7, + (q31_t)0x71410804, (q31_t)0xC4020132, (q31_t)0x71120CC5, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xC350AF25, + (q31_t)0x70B34524, (q31_t)0xC2F83E2A, (q31_t)0x708378FE, + (q31_t)0xC29FF2D4, (q31_t)0x70536771, (q31_t)0xC247CD5A, + (q31_t)0x70231099, (q31_t)0xC1EFCDF2, (q31_t)0x6FF27496, + (q31_t)0xC197F4D3, (q31_t)0x6FC19385, (q31_t)0xC1404233, + (q31_t)0x6F906D84, (q31_t)0xC0E8B648, (q31_t)0x6F5F02B1, + (q31_t)0xC0915147, (q31_t)0x6F2D532C, (q31_t)0xC03A1368, + (q31_t)0x6EFB5F12, (q31_t)0xBFE2FCDF, (q31_t)0x6EC92682, + (q31_t)0xBF8C0DE2, (q31_t)0x6E96A99C, (q31_t)0xBF3546A8, + (q31_t)0x6E63E87F, (q31_t)0xBEDEA765, (q31_t)0x6E30E349, + (q31_t)0xBE88304F, (q31_t)0x6DFD9A1B, (q31_t)0xBE31E19B, + (q31_t)0x6DCA0D14, (q31_t)0xBDDBBB7F, (q31_t)0x6D963C54, + (q31_t)0xBD85BE2F, (q31_t)0x6D6227FA, (q31_t)0xBD2FE9E1, + (q31_t)0x6D2DD027, (q31_t)0xBCDA3ECA, (q31_t)0x6CF934FB, + (q31_t)0xBC84BD1E, (q31_t)0x6CC45697, (q31_t)0xBC2F6513, + (q31_t)0x6C8F351C, (q31_t)0xBBDA36DC, (q31_t)0x6C59D0A9, + (q31_t)0xBB8532AF, (q31_t)0x6C242960, (q31_t)0xBB3058C0, + (q31_t)0x6BEE3F62, (q31_t)0xBADBA943, (q31_t)0x6BB812D0, + (q31_t)0xBA87246C, (q31_t)0x6B81A3CD, (q31_t)0xBA32CA70, + (q31_t)0x6B4AF278, (q31_t)0xB9DE9B83, (q31_t)0x6B13FEF5, + (q31_t)0xB98A97D8, (q31_t)0x6ADCC964, (q31_t)0xB936BFA3, + (q31_t)0x6AA551E8, (q31_t)0xB8E31319, (q31_t)0x6A6D98A4, + (q31_t)0xB88F926C, (q31_t)0x6A359DB9, (q31_t)0xB83C3DD1, + (q31_t)0x69FD614A, (q31_t)0xB7E9157A, (q31_t)0x69C4E37A, + (q31_t)0xB796199B, (q31_t)0x698C246C, (q31_t)0xB7434A67, + (q31_t)0x69532442, (q31_t)0xB6F0A811, (q31_t)0x6919E320, + (q31_t)0xB69E32CD, (q31_t)0x68E06129, (q31_t)0xB64BEACC, + (q31_t)0x68A69E81, (q31_t)0xB5F9D042, (q31_t)0x686C9B4B, + (q31_t)0xB5A7E362, (q31_t)0x683257AA, (q31_t)0xB556245E, + (q31_t)0x67F7D3C4, (q31_t)0xB5049368, (q31_t)0x67BD0FBC, + (q31_t)0xB4B330B2, (q31_t)0x67820BB6, (q31_t)0xB461FC70, + (q31_t)0x6746C7D7, (q31_t)0xB410F6D2, (q31_t)0x670B4443, + (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xB36F784E, + (q31_t)0x66937E90, (q31_t)0xB31EFFCB, (q31_t)0x66573CBB, + (q31_t)0xB2CEB6B5, (q31_t)0x661ABBC5, (q31_t)0xB27E9D3B, + (q31_t)0x65DDFBD3, (q31_t)0xB22EB392, (q31_t)0x65A0FD0B, + (q31_t)0xB1DEF9E8, (q31_t)0x6563BF92, (q31_t)0xB18F7070, + (q31_t)0x6526438E, (q31_t)0xB140175B, (q31_t)0x64E88926, + (q31_t)0xB0F0EEDA, (q31_t)0x64AA907F, (q31_t)0xB0A1F71C, + (q31_t)0x646C59BF, (q31_t)0xB0533055, (q31_t)0x642DE50D, + (q31_t)0xB0049AB2, (q31_t)0x63EF328F, (q31_t)0xAFB63667, + (q31_t)0x63B0426D, (q31_t)0xAF6803A1, (q31_t)0x637114CC, + (q31_t)0xAF1A0293, (q31_t)0x6331A9D4, (q31_t)0xAECC336B, + (q31_t)0x62F201AC, (q31_t)0xAE7E965B, (q31_t)0x62B21C7B, + (q31_t)0xAE312B91, (q31_t)0x6271FA69, (q31_t)0xADE3F33E, + (q31_t)0x62319B9D, (q31_t)0xAD96ED91, (q31_t)0x61F1003E, + (q31_t)0xAD4A1ABA, (q31_t)0x61B02876, (q31_t)0xACFD7AE8, + (q31_t)0x616F146B, (q31_t)0xACB10E4A, (q31_t)0x612DC446, + (q31_t)0xAC64D510, (q31_t)0x60EC3830, (q31_t)0xAC18CF68, + (q31_t)0x60AA704F, (q31_t)0xABCCFD82, (q31_t)0x60686CCE, + (q31_t)0xAB815F8C, (q31_t)0x60262DD5, (q31_t)0xAB35F5B5, + (q31_t)0x5FE3B38D, (q31_t)0xAAEAC02B, (q31_t)0x5FA0FE1E, + (q31_t)0xAA9FBF1D, (q31_t)0x5F5E0DB3, (q31_t)0xAA54F2B9, + (q31_t)0x5F1AE273, (q31_t)0xAA0A5B2D, (q31_t)0x5ED77C89, + (q31_t)0xA9BFF8A8, (q31_t)0x5E93DC1F, (q31_t)0xA975CB56, + (q31_t)0x5E50015D, (q31_t)0xA92BD366, (q31_t)0x5E0BEC6E, + (q31_t)0xA8E21106, (q31_t)0x5DC79D7C, (q31_t)0xA8988463, + (q31_t)0x5D8314B0, (q31_t)0xA84F2DA9, (q31_t)0x5D3E5236, + (q31_t)0xA8060D08, (q31_t)0x5CF95638, (q31_t)0xA7BD22AB, + (q31_t)0x5CB420DF, (q31_t)0xA7746EC0, (q31_t)0x5C6EB258, + (q31_t)0xA72BF173, (q31_t)0x5C290ACC, (q31_t)0xA6E3AAF2, + (q31_t)0x5BE32A67, (q31_t)0xA69B9B68, (q31_t)0x5B9D1153, + (q31_t)0xA653C302, (q31_t)0x5B56BFBD, (q31_t)0xA60C21ED, + (q31_t)0x5B1035CF, (q31_t)0xA5C4B855, (q31_t)0x5AC973B4, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA5368C4B, + (q31_t)0x5A3B47AA, (q31_t)0xA4EFCA31, (q31_t)0x59F3DE12, + (q31_t)0xA4A94042, (q31_t)0x59AC3CFD, (q31_t)0xA462EEAC, + (q31_t)0x59646497, (q31_t)0xA41CD598, (q31_t)0x591C550E, + (q31_t)0xA3D6F533, (q31_t)0x58D40E8C, (q31_t)0xA3914DA7, + (q31_t)0x588B913F, (q31_t)0xA34BDF20, (q31_t)0x5842DD54, + (q31_t)0xA306A9C7, (q31_t)0x57F9F2F7, (q31_t)0xA2C1ADC9, + (q31_t)0x57B0D256, (q31_t)0xA27CEB4F, (q31_t)0x57677B9D, + (q31_t)0xA2386283, (q31_t)0x571DEEF9, (q31_t)0xA1F41391, + (q31_t)0x56D42C99, (q31_t)0xA1AFFEA2, (q31_t)0x568A34A9, + (q31_t)0xA16C23E1, (q31_t)0x56400757, (q31_t)0xA1288376, + (q31_t)0x55F5A4D2, (q31_t)0xA0E51D8C, (q31_t)0x55AB0D46, + (q31_t)0xA0A1F24C, (q31_t)0x556040E2, (q31_t)0xA05F01E1, + (q31_t)0x55153FD4, (q31_t)0xA01C4C72, (q31_t)0x54CA0A4A, + (q31_t)0x9FD9D22A, (q31_t)0x547EA073, (q31_t)0x9F979331, + (q31_t)0x5433027D, (q31_t)0x9F558FB0, (q31_t)0x53E73097, + (q31_t)0x9F13C7D0, (q31_t)0x539B2AEF, (q31_t)0x9ED23BB9, + (q31_t)0x534EF1B5, (q31_t)0x9E90EB94, (q31_t)0x53028517, + (q31_t)0x9E4FD789, (q31_t)0x52B5E545, (q31_t)0x9E0EFFC1, + (q31_t)0x5269126E, (q31_t)0x9DCE6462, (q31_t)0x521C0CC1, + (q31_t)0x9D8E0596, (q31_t)0x51CED46E, (q31_t)0x9D4DE384, + (q31_t)0x518169A4, (q31_t)0x9D0DFE53, (q31_t)0x5133CC94, + (q31_t)0x9CCE562B, (q31_t)0x50E5FD6C, (q31_t)0x9C8EEB33, + (q31_t)0x5097FC5E, (q31_t)0x9C4FBD92, (q31_t)0x5049C999, + (q31_t)0x9C10CD70, (q31_t)0x4FFB654D, (q31_t)0x9BD21AF2, + (q31_t)0x4FACCFAB, (q31_t)0x9B93A640, (q31_t)0x4F5E08E3, + (q31_t)0x9B556F80, (q31_t)0x4F0F1126, (q31_t)0x9B1776D9, + (q31_t)0x4EBFE8A4, (q31_t)0x9AD9BC71, (q31_t)0x4E708F8F, + (q31_t)0x9A9C406D, (q31_t)0x4E210617, (q31_t)0x9A5F02F5, + (q31_t)0x4DD14C6E, (q31_t)0x9A22042C, (q31_t)0x4D8162C4, + (q31_t)0x99E5443A, (q31_t)0x4D31494B, (q31_t)0x99A8C344, + (q31_t)0x4CE10034, (q31_t)0x996C816F, (q31_t)0x4C9087B1, + (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x98F4BBBC, + (q31_t)0x4BEF092D, (q31_t)0x98B93828, (q31_t)0x4B9E038F, + (q31_t)0x987DF449, (q31_t)0x4B4CCF4D, (q31_t)0x9842F043, + (q31_t)0x4AFB6C97, (q31_t)0x98082C3B, (q31_t)0x4AA9DBA1, + (q31_t)0x97CDA855, (q31_t)0x4A581C9D, (q31_t)0x979364B5, + (q31_t)0x4A062FBD, (q31_t)0x9759617E, (q31_t)0x49B41533, + (q31_t)0x971F9ED6, (q31_t)0x4961CD32, (q31_t)0x96E61CDF, + (q31_t)0x490F57EE, (q31_t)0x96ACDBBD, (q31_t)0x48BCB598, + (q31_t)0x9673DB94, (q31_t)0x4869E664, (q31_t)0x963B1C85, + (q31_t)0x4816EA85, (q31_t)0x96029EB5, (q31_t)0x47C3C22E, + (q31_t)0x95CA6246, (q31_t)0x47706D93, (q31_t)0x9592675B, + (q31_t)0x471CECE6, (q31_t)0x955AAE17, (q31_t)0x46C9405C, + (q31_t)0x9523369B, (q31_t)0x46756827, (q31_t)0x94EC010B, + (q31_t)0x4621647C, (q31_t)0x94B50D87, (q31_t)0x45CD358F, + (q31_t)0x947E5C32, (q31_t)0x4578DB93, (q31_t)0x9447ED2F, + (q31_t)0x452456BC, (q31_t)0x9411C09D, (q31_t)0x44CFA73F, + (q31_t)0x93DBD69F, (q31_t)0x447ACD50, (q31_t)0x93A62F56, + (q31_t)0x4425C923, (q31_t)0x9370CAE4, (q31_t)0x43D09AEC, + (q31_t)0x933BA968, (q31_t)0x437B42E1, (q31_t)0x9306CB04, + (q31_t)0x4325C135, (q31_t)0x92D22FD8, (q31_t)0x42D0161E, + (q31_t)0x929DD805, (q31_t)0x427A41D0, (q31_t)0x9269C3AC, + (q31_t)0x42244480, (q31_t)0x9235F2EB, (q31_t)0x41CE1E64, + (q31_t)0x920265E4, (q31_t)0x4177CFB0, (q31_t)0x91CF1CB6, + (q31_t)0x4121589A, (q31_t)0x919C1780, (q31_t)0x40CAB957, + (q31_t)0x91695663, (q31_t)0x4073F21D, (q31_t)0x9136D97D, + (q31_t)0x401D0320, (q31_t)0x9104A0ED, (q31_t)0x3FC5EC97, + (q31_t)0x90D2ACD3, (q31_t)0x3F6EAEB8, (q31_t)0x90A0FD4E, + (q31_t)0x3F1749B7, (q31_t)0x906F927B, (q31_t)0x3EBFBDCC, + (q31_t)0x903E6C7A, (q31_t)0x3E680B2C, (q31_t)0x900D8B69, + (q31_t)0x3E10320D, (q31_t)0x8FDCEF66, (q31_t)0x3DB832A5, + (q31_t)0x8FAC988E, (q31_t)0x3D600D2B, (q31_t)0x8F7C8701, + (q31_t)0x3D07C1D5, (q31_t)0x8F4CBADB, (q31_t)0x3CAF50DA, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8EEDF33B, + (q31_t)0x3BFDFECD, (q31_t)0x8EBEF7FB, (q31_t)0x3BA51E29, + (q31_t)0x8E904298, (q31_t)0x3B4C18BA, (q31_t)0x8E61D32D, + (q31_t)0x3AF2EEB7, (q31_t)0x8E33A9D9, (q31_t)0x3A99A057, + (q31_t)0x8E05C6B7, (q31_t)0x3A402DD1, (q31_t)0x8DD829E4, + (q31_t)0x39E6975D, (q31_t)0x8DAAD37B, (q31_t)0x398CDD32, + (q31_t)0x8D7DC399, (q31_t)0x3932FF87, (q31_t)0x8D50FA59, + (q31_t)0x38D8FE93, (q31_t)0x8D2477D8, (q31_t)0x387EDA8E, + (q31_t)0x8CF83C30, (q31_t)0x382493B0, (q31_t)0x8CCC477D, + (q31_t)0x37CA2A30, (q31_t)0x8CA099D9, (q31_t)0x376F9E46, + (q31_t)0x8C753361, (q31_t)0x3714F02A, (q31_t)0x8C4A142F, + (q31_t)0x36BA2013, (q31_t)0x8C1F3C5C, (q31_t)0x365F2E3B, + (q31_t)0x8BF4AC05, (q31_t)0x36041AD9, (q31_t)0x8BCA6342, + (q31_t)0x35A8E624, (q31_t)0x8BA0622F, (q31_t)0x354D9056, + (q31_t)0x8B76A8E4, (q31_t)0x34F219A7, (q31_t)0x8B4D377C, + (q31_t)0x3496824F, (q31_t)0x8B240E10, (q31_t)0x343ACA87, + (q31_t)0x8AFB2CBA, (q31_t)0x33DEF287, (q31_t)0x8AD29393, + (q31_t)0x3382FA88, (q31_t)0x8AAA42B4, (q31_t)0x3326E2C2, + (q31_t)0x8A823A35, (q31_t)0x32CAAB6F, (q31_t)0x8A5A7A30, + (q31_t)0x326E54C7, (q31_t)0x8A3302BD, (q31_t)0x3211DF03, + (q31_t)0x8A0BD3F5, (q31_t)0x31B54A5D, (q31_t)0x89E4EDEE, + (q31_t)0x3158970D, (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x8997FC89, (q31_t)0x309ED555, (q31_t)0x8971F15A, + (q31_t)0x3041C760, (q31_t)0x894C2F4C, (q31_t)0x2FE49BA6, + (q31_t)0x8926B677, (q31_t)0x2F875262, (q31_t)0x890186F1, + (q31_t)0x2F29EBCC, (q31_t)0x88DCA0D3, (q31_t)0x2ECC681E, + (q31_t)0x88B80431, (q31_t)0x2E6EC792, (q31_t)0x8893B124, + (q31_t)0x2E110A62, (q31_t)0x886FA7C2, (q31_t)0x2DB330C7, + (q31_t)0x884BE820, (q31_t)0x2D553AFB, (q31_t)0x88287255, + (q31_t)0x2CF72939, (q31_t)0x88054677, (q31_t)0x2C98FBBA, + (q31_t)0x87E2649B, (q31_t)0x2C3AB2B9, (q31_t)0x87BFCCD7, + (q31_t)0x2BDC4E6F, (q31_t)0x879D7F40, (q31_t)0x2B7DCF17, + (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x8759C2EF, + (q31_t)0x2AC08025, (q31_t)0x8738545E, (q31_t)0x2A61B101, + (q31_t)0x8717304E, (q31_t)0x2A02C7B8, (q31_t)0x86F656D3, + (q31_t)0x29A3C484, (q31_t)0x86D5C802, (q31_t)0x2944A7A2, + (q31_t)0x86B583EE, (q31_t)0x28E5714A, (q31_t)0x86958AAB, + (q31_t)0x288621B9, (q31_t)0x8675DC4E, (q31_t)0x2826B928, + (q31_t)0x865678EA, (q31_t)0x27C737D2, (q31_t)0x86376092, + (q31_t)0x27679DF4, (q31_t)0x86189359, (q31_t)0x2707EBC6, + (q31_t)0x85FA1152, (q31_t)0x26A82185, (q31_t)0x85DBDA91, + (q31_t)0x26483F6C, (q31_t)0x85BDEF27, (q31_t)0x25E845B5, + (q31_t)0x85A04F28, (q31_t)0x2588349D, (q31_t)0x8582FAA4, + (q31_t)0x25280C5D, (q31_t)0x8565F1B0, (q31_t)0x24C7CD32, + (q31_t)0x8549345C, (q31_t)0x24677757, (q31_t)0x852CC2BA, + (q31_t)0x24070B07, (q31_t)0x85109CDC, (q31_t)0x23A6887E, + (q31_t)0x84F4C2D3, (q31_t)0x2345EFF7, (q31_t)0x84D934B0, + (q31_t)0x22E541AE, (q31_t)0x84BDF285, (q31_t)0x22847DDF, + (q31_t)0x84A2FC62, (q31_t)0x2223A4C5, (q31_t)0x84885257, + (q31_t)0x21C2B69C, (q31_t)0x846DF476, (q31_t)0x2161B39F, + (q31_t)0x8453E2CE, (q31_t)0x21009C0B, (q31_t)0x843A1D70, + (q31_t)0x209F701C, (q31_t)0x8420A46B, (q31_t)0x203E300D, + (q31_t)0x840777CF, (q31_t)0x1FDCDC1A, (q31_t)0x83EE97AC, + (q31_t)0x1F7B7480, (q31_t)0x83D60411, (q31_t)0x1F19F97B, + (q31_t)0x83BDBD0D, (q31_t)0x1EB86B46, (q31_t)0x83A5C2B0, + (q31_t)0x1E56CA1E, (q31_t)0x838E1507, (q31_t)0x1DF5163F, + (q31_t)0x8376B422, (q31_t)0x1D934FE5, (q31_t)0x835FA00E, + (q31_t)0x1D31774D, (q31_t)0x8348D8DB, (q31_t)0x1CCF8CB3, + (q31_t)0x83325E97, (q31_t)0x1C6D9053, (q31_t)0x831C314E, + (q31_t)0x1C0B826A, (q31_t)0x8306510F, (q31_t)0x1BA96334, + (q31_t)0x82F0BDE8, (q31_t)0x1B4732EF, (q31_t)0x82DB77E5, + (q31_t)0x1AE4F1D6, (q31_t)0x82C67F13, (q31_t)0x1A82A025, + (q31_t)0x82B1D381, (q31_t)0x1A203E1B, (q31_t)0x829D753A, + (q31_t)0x19BDCBF2, (q31_t)0x8289644A, (q31_t)0x195B49E9, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x82622AA5, + (q31_t)0x18961727, (q31_t)0x824F0208, (q31_t)0x183366E8, + (q31_t)0x823C26F2, (q31_t)0x17D0A7BB, (q31_t)0x82299971, + (q31_t)0x176DD9DE, (q31_t)0x8217598F, (q31_t)0x170AFD8D, + (q31_t)0x82056758, (q31_t)0x16A81305, (q31_t)0x81F3C2D7, + (q31_t)0x16451A83, (q31_t)0x81E26C16, (q31_t)0x15E21444, + (q31_t)0x81D16320, (q31_t)0x157F0086, (q31_t)0x81C0A801, + (q31_t)0x151BDF85, (q31_t)0x81B03AC1, (q31_t)0x14B8B17F, + (q31_t)0x81A01B6C, (q31_t)0x145576B1, (q31_t)0x81904A0C, + (q31_t)0x13F22F57, (q31_t)0x8180C6A9, (q31_t)0x138EDBB0, + (q31_t)0x8171914E, (q31_t)0x132B7BF9, (q31_t)0x8162AA03, + (q31_t)0x12C8106E, (q31_t)0x815410D3, (q31_t)0x1264994E, + (q31_t)0x8145C5C6, (q31_t)0x120116D4, (q31_t)0x8137C8E6, + (q31_t)0x119D8940, (q31_t)0x812A1A39, (q31_t)0x1139F0CE, + (q31_t)0x811CB9CA, (q31_t)0x10D64DBC, (q31_t)0x810FA7A0, + (q31_t)0x1072A047, (q31_t)0x8102E3C3, (q31_t)0x100EE8AD, + (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x80EA4712, + (q31_t)0x0F475BFE, (q31_t)0x80DE6E4C, (q31_t)0x0EE38765, + (q31_t)0x80D2E3F1, (q31_t)0x0E7FA99D, (q31_t)0x80C7A80A, + (q31_t)0x0E1BC2E3, (q31_t)0x80BCBA9C, (q31_t)0x0DB7D376, + (q31_t)0x80B21BAF, (q31_t)0x0D53DB92, (q31_t)0x80A7CB49, + (q31_t)0x0CEFDB75, (q31_t)0x809DC970, (q31_t)0x0C8BD35E, + (q31_t)0x8094162B, (q31_t)0x0C27C389, (q31_t)0x808AB180, + (q31_t)0x0BC3AC35, (q31_t)0x80819B74, (q31_t)0x0B5F8D9F, + (q31_t)0x8078D40D, (q31_t)0x0AFB6805, (q31_t)0x80705B50, + (q31_t)0x0A973BA5, (q31_t)0x80683143, (q31_t)0x0A3308BC, + (q31_t)0x806055EA, (q31_t)0x09CECF89, (q31_t)0x8058C94C, + (q31_t)0x096A9049, (q31_t)0x80518B6B, (q31_t)0x09064B3A, + (q31_t)0x804A9C4D, (q31_t)0x08A2009A, (q31_t)0x8043FBF6, + (q31_t)0x083DB0A7, (q31_t)0x803DAA69, (q31_t)0x07D95B9E, + (q31_t)0x8037A7AC, (q31_t)0x077501BE, (q31_t)0x8031F3C1, + (q31_t)0x0710A344, (q31_t)0x802C8EAD, (q31_t)0x06AC406F, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x8022B113, + (q31_t)0x05E36EA9, (q31_t)0x801E3894, (q31_t)0x057F0034, + (q31_t)0x801A0EF7, (q31_t)0x051A8E5C, (q31_t)0x80163440, + (q31_t)0x04B6195D, (q31_t)0x8012A86F, (q31_t)0x0451A176, + (q31_t)0x800F6B88, (q31_t)0x03ED26E6, (q31_t)0x800C7D8C, + (q31_t)0x0388A9E9, (q31_t)0x8009DE7D, (q31_t)0x03242ABF, + (q31_t)0x80078E5E, (q31_t)0x02BFA9A4, (q31_t)0x80058D2E, + (q31_t)0x025B26D7, (q31_t)0x8003DAF0, (q31_t)0x01F6A296, + (q31_t)0x800277A5, (q31_t)0x01921D1F, (q31_t)0x8001634D, + (q31_t)0x012D96B0, (q31_t)0x80009DE9, (q31_t)0x00C90F88, + (q31_t)0x8000277A, (q31_t)0x006487E3, (q31_t)0x80000000, + (q31_t)0x00000000, (q31_t)0x8000277A, (q31_t)0xFF9B781D, + (q31_t)0x80009DE9, (q31_t)0xFF36F078, (q31_t)0x8001634D, + (q31_t)0xFED2694F, (q31_t)0x800277A5, (q31_t)0xFE6DE2E0, + (q31_t)0x8003DAF0, (q31_t)0xFE095D69, (q31_t)0x80058D2E, + (q31_t)0xFDA4D928, (q31_t)0x80078E5E, (q31_t)0xFD40565B, + (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x800C7D8C, + (q31_t)0xFC775616, (q31_t)0x800F6B88, (q31_t)0xFC12D919, + (q31_t)0x8012A86F, (q31_t)0xFBAE5E89, (q31_t)0x80163440, + (q31_t)0xFB49E6A2, (q31_t)0x801A0EF7, (q31_t)0xFAE571A4, + (q31_t)0x801E3894, (q31_t)0xFA80FFCB, (q31_t)0x8022B113, + (q31_t)0xFA1C9156, (q31_t)0x80277872, (q31_t)0xF9B82683, + (q31_t)0x802C8EAD, (q31_t)0xF953BF90, (q31_t)0x8031F3C1, + (q31_t)0xF8EF5CBB, (q31_t)0x8037A7AC, (q31_t)0xF88AFE41, + (q31_t)0x803DAA69, (q31_t)0xF826A461, (q31_t)0x8043FBF6, + (q31_t)0xF7C24F58, (q31_t)0x804A9C4D, (q31_t)0xF75DFF65, + (q31_t)0x80518B6B, (q31_t)0xF6F9B4C5, (q31_t)0x8058C94C, + (q31_t)0xF6956FB6, (q31_t)0x806055EA, (q31_t)0xF6313076, + (q31_t)0x80683143, (q31_t)0xF5CCF743, (q31_t)0x80705B50, + (q31_t)0xF568C45A, (q31_t)0x8078D40D, (q31_t)0xF50497FA, + (q31_t)0x80819B74, (q31_t)0xF4A07260, (q31_t)0x808AB180, + (q31_t)0xF43C53CA, (q31_t)0x8094162B, (q31_t)0xF3D83C76, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80A7CB49, + (q31_t)0xF310248A, (q31_t)0x80B21BAF, (q31_t)0xF2AC246D, + (q31_t)0x80BCBA9C, (q31_t)0xF2482C89, (q31_t)0x80C7A80A, + (q31_t)0xF1E43D1C, (q31_t)0x80D2E3F1, (q31_t)0xF1805662, + (q31_t)0x80DE6E4C, (q31_t)0xF11C789A, (q31_t)0x80EA4712, + (q31_t)0xF0B8A401, (q31_t)0x80F66E3C, (q31_t)0xF054D8D4, + (q31_t)0x8102E3C3, (q31_t)0xEFF11752, (q31_t)0x810FA7A0, + (q31_t)0xEF8D5FB8, (q31_t)0x811CB9CA, (q31_t)0xEF29B243, + (q31_t)0x812A1A39, (q31_t)0xEEC60F31, (q31_t)0x8137C8E6, + (q31_t)0xEE6276BF, (q31_t)0x8145C5C6, (q31_t)0xEDFEE92B, + (q31_t)0x815410D3, (q31_t)0xED9B66B2, (q31_t)0x8162AA03, + (q31_t)0xED37EF91, (q31_t)0x8171914E, (q31_t)0xECD48406, + (q31_t)0x8180C6A9, (q31_t)0xEC71244F, (q31_t)0x81904A0C, + (q31_t)0xEC0DD0A8, (q31_t)0x81A01B6C, (q31_t)0xEBAA894E, + (q31_t)0x81B03AC1, (q31_t)0xEB474E80, (q31_t)0x81C0A801, + (q31_t)0xEAE4207A, (q31_t)0x81D16320, (q31_t)0xEA80FF79, + (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x81F3C2D7, + (q31_t)0xE9BAE57C, (q31_t)0x82056758, (q31_t)0xE957ECFB, + (q31_t)0x8217598F, (q31_t)0xE8F50273, (q31_t)0x82299971, + (q31_t)0xE8922621, (q31_t)0x823C26F2, (q31_t)0xE82F5844, + (q31_t)0x824F0208, (q31_t)0xE7CC9917, (q31_t)0x82622AA5, + (q31_t)0xE769E8D8, (q31_t)0x8275A0C0, (q31_t)0xE70747C3, + (q31_t)0x8289644A, (q31_t)0xE6A4B616, (q31_t)0x829D753A, + (q31_t)0xE642340D, (q31_t)0x82B1D381, (q31_t)0xE5DFC1E4, + (q31_t)0x82C67F13, (q31_t)0xE57D5FDA, (q31_t)0x82DB77E5, + (q31_t)0xE51B0E2A, (q31_t)0x82F0BDE8, (q31_t)0xE4B8CD10, + (q31_t)0x8306510F, (q31_t)0xE4569CCB, (q31_t)0x831C314E, + (q31_t)0xE3F47D95, (q31_t)0x83325E97, (q31_t)0xE3926FAC, + (q31_t)0x8348D8DB, (q31_t)0xE330734C, (q31_t)0x835FA00E, + (q31_t)0xE2CE88B2, (q31_t)0x8376B422, (q31_t)0xE26CB01A, + (q31_t)0x838E1507, (q31_t)0xE20AE9C1, (q31_t)0x83A5C2B0, + (q31_t)0xE1A935E1, (q31_t)0x83BDBD0D, (q31_t)0xE14794B9, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x83EE97AC, + (q31_t)0xE0848B7F, (q31_t)0x840777CF, (q31_t)0xE02323E5, + (q31_t)0x8420A46B, (q31_t)0xDFC1CFF2, (q31_t)0x843A1D70, + (q31_t)0xDF608FE3, (q31_t)0x8453E2CE, (q31_t)0xDEFF63F4, + (q31_t)0x846DF476, (q31_t)0xDE9E4C60, (q31_t)0x84885257, + (q31_t)0xDE3D4963, (q31_t)0x84A2FC62, (q31_t)0xDDDC5B3A, + (q31_t)0x84BDF285, (q31_t)0xDD7B8220, (q31_t)0x84D934B0, + (q31_t)0xDD1ABE51, (q31_t)0x84F4C2D3, (q31_t)0xDCBA1008, + (q31_t)0x85109CDC, (q31_t)0xDC597781, (q31_t)0x852CC2BA, + (q31_t)0xDBF8F4F8, (q31_t)0x8549345C, (q31_t)0xDB9888A8, + (q31_t)0x8565F1B0, (q31_t)0xDB3832CD, (q31_t)0x8582FAA4, + (q31_t)0xDAD7F3A2, (q31_t)0x85A04F28, (q31_t)0xDA77CB62, + (q31_t)0x85BDEF27, (q31_t)0xDA17BA4A, (q31_t)0x85DBDA91, + (q31_t)0xD9B7C093, (q31_t)0x85FA1152, (q31_t)0xD957DE7A, + (q31_t)0x86189359, (q31_t)0xD8F81439, (q31_t)0x86376092, + (q31_t)0xD898620C, (q31_t)0x865678EA, (q31_t)0xD838C82D, + (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x86958AAB, + (q31_t)0xD779DE46, (q31_t)0x86B583EE, (q31_t)0xD71A8EB5, + (q31_t)0x86D5C802, (q31_t)0xD6BB585D, (q31_t)0x86F656D3, + (q31_t)0xD65C3B7B, (q31_t)0x8717304E, (q31_t)0xD5FD3847, + (q31_t)0x8738545E, (q31_t)0xD59E4EFE, (q31_t)0x8759C2EF, + (q31_t)0xD53F7FDA, (q31_t)0x877B7BEC, (q31_t)0xD4E0CB14, + (q31_t)0x879D7F40, (q31_t)0xD48230E8, (q31_t)0x87BFCCD7, + (q31_t)0xD423B190, (q31_t)0x87E2649B, (q31_t)0xD3C54D46, + (q31_t)0x88054677, (q31_t)0xD3670445, (q31_t)0x88287255, + (q31_t)0xD308D6C6, (q31_t)0x884BE820, (q31_t)0xD2AAC504, + (q31_t)0x886FA7C2, (q31_t)0xD24CCF38, (q31_t)0x8893B124, + (q31_t)0xD1EEF59E, (q31_t)0x88B80431, (q31_t)0xD191386D, + (q31_t)0x88DCA0D3, (q31_t)0xD13397E1, (q31_t)0x890186F1, + (q31_t)0xD0D61433, (q31_t)0x8926B677, (q31_t)0xD078AD9D, + (q31_t)0x894C2F4C, (q31_t)0xD01B6459, (q31_t)0x8971F15A, + (q31_t)0xCFBE389F, (q31_t)0x8997FC89, (q31_t)0xCF612AAA, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x89E4EDEE, + (q31_t)0xCEA768F2, (q31_t)0x8A0BD3F5, (q31_t)0xCE4AB5A2, + (q31_t)0x8A3302BD, (q31_t)0xCDEE20FC, (q31_t)0x8A5A7A30, + (q31_t)0xCD91AB38, (q31_t)0x8A823A35, (q31_t)0xCD355490, + (q31_t)0x8AAA42B4, (q31_t)0xCCD91D3D, (q31_t)0x8AD29393, + (q31_t)0xCC7D0577, (q31_t)0x8AFB2CBA, (q31_t)0xCC210D78, + (q31_t)0x8B240E10, (q31_t)0xCBC53578, (q31_t)0x8B4D377C, + (q31_t)0xCB697DB0, (q31_t)0x8B76A8E4, (q31_t)0xCB0DE658, + (q31_t)0x8BA0622F, (q31_t)0xCAB26FA9, (q31_t)0x8BCA6342, + (q31_t)0xCA5719DB, (q31_t)0x8BF4AC05, (q31_t)0xC9FBE527, + (q31_t)0x8C1F3C5C, (q31_t)0xC9A0D1C4, (q31_t)0x8C4A142F, + (q31_t)0xC945DFEC, (q31_t)0x8C753361, (q31_t)0xC8EB0FD6, + (q31_t)0x8CA099D9, (q31_t)0xC89061BA, (q31_t)0x8CCC477D, + (q31_t)0xC835D5D0, (q31_t)0x8CF83C30, (q31_t)0xC7DB6C50, + (q31_t)0x8D2477D8, (q31_t)0xC7812571, (q31_t)0x8D50FA59, + (q31_t)0xC727016C, (q31_t)0x8D7DC399, (q31_t)0xC6CD0079, + (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8DD829E4, + (q31_t)0xC61968A2, (q31_t)0x8E05C6B7, (q31_t)0xC5BFD22E, + (q31_t)0x8E33A9D9, (q31_t)0xC5665FA8, (q31_t)0x8E61D32D, + (q31_t)0xC50D1148, (q31_t)0x8E904298, (q31_t)0xC4B3E746, + (q31_t)0x8EBEF7FB, (q31_t)0xC45AE1D7, (q31_t)0x8EEDF33B, + (q31_t)0xC4020132, (q31_t)0x8F1D343A, (q31_t)0xC3A9458F, + (q31_t)0x8F4CBADB, (q31_t)0xC350AF25, (q31_t)0x8F7C8701, + (q31_t)0xC2F83E2A, (q31_t)0x8FAC988E, (q31_t)0xC29FF2D4, + (q31_t)0x8FDCEF66, (q31_t)0xC247CD5A, (q31_t)0x900D8B69, + (q31_t)0xC1EFCDF2, (q31_t)0x903E6C7A, (q31_t)0xC197F4D3, + (q31_t)0x906F927B, (q31_t)0xC1404233, (q31_t)0x90A0FD4E, + (q31_t)0xC0E8B648, (q31_t)0x90D2ACD3, (q31_t)0xC0915147, + (q31_t)0x9104A0ED, (q31_t)0xC03A1368, (q31_t)0x9136D97D, + (q31_t)0xBFE2FCDF, (q31_t)0x91695663, (q31_t)0xBF8C0DE2, + (q31_t)0x919C1780, (q31_t)0xBF3546A8, (q31_t)0x91CF1CB6, + (q31_t)0xBEDEA765, (q31_t)0x920265E4, (q31_t)0xBE88304F, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x9269C3AC, + (q31_t)0xBDDBBB7F, (q31_t)0x929DD805, (q31_t)0xBD85BE2F, + (q31_t)0x92D22FD8, (q31_t)0xBD2FE9E1, (q31_t)0x9306CB04, + (q31_t)0xBCDA3ECA, (q31_t)0x933BA968, (q31_t)0xBC84BD1E, + (q31_t)0x9370CAE4, (q31_t)0xBC2F6513, (q31_t)0x93A62F56, + (q31_t)0xBBDA36DC, (q31_t)0x93DBD69F, (q31_t)0xBB8532AF, + (q31_t)0x9411C09D, (q31_t)0xBB3058C0, (q31_t)0x9447ED2F, + (q31_t)0xBADBA943, (q31_t)0x947E5C32, (q31_t)0xBA87246C, + (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x94EC010B, + (q31_t)0xB9DE9B83, (q31_t)0x9523369B, (q31_t)0xB98A97D8, + (q31_t)0x955AAE17, (q31_t)0xB936BFA3, (q31_t)0x9592675B, + (q31_t)0xB8E31319, (q31_t)0x95CA6246, (q31_t)0xB88F926C, + (q31_t)0x96029EB5, (q31_t)0xB83C3DD1, (q31_t)0x963B1C85, + (q31_t)0xB7E9157A, (q31_t)0x9673DB94, (q31_t)0xB796199B, + (q31_t)0x96ACDBBD, (q31_t)0xB7434A67, (q31_t)0x96E61CDF, + (q31_t)0xB6F0A811, (q31_t)0x971F9ED6, (q31_t)0xB69E32CD, + (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x979364B5, + (q31_t)0xB5F9D042, (q31_t)0x97CDA855, (q31_t)0xB5A7E362, + (q31_t)0x98082C3B, (q31_t)0xB556245E, (q31_t)0x9842F043, + (q31_t)0xB5049368, (q31_t)0x987DF449, (q31_t)0xB4B330B2, + (q31_t)0x98B93828, (q31_t)0xB461FC70, (q31_t)0x98F4BBBC, + (q31_t)0xB410F6D2, (q31_t)0x99307EE0, (q31_t)0xB3C0200C, + (q31_t)0x996C816F, (q31_t)0xB36F784E, (q31_t)0x99A8C344, + (q31_t)0xB31EFFCB, (q31_t)0x99E5443A, (q31_t)0xB2CEB6B5, + (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9A5F02F5, + (q31_t)0xB22EB392, (q31_t)0x9A9C406D, (q31_t)0xB1DEF9E8, + (q31_t)0x9AD9BC71, (q31_t)0xB18F7070, (q31_t)0x9B1776D9, + (q31_t)0xB140175B, (q31_t)0x9B556F80, (q31_t)0xB0F0EEDA, + (q31_t)0x9B93A640, (q31_t)0xB0A1F71C, (q31_t)0x9BD21AF2, + (q31_t)0xB0533055, (q31_t)0x9C10CD70, (q31_t)0xB0049AB2, + (q31_t)0x9C4FBD92, (q31_t)0xAFB63667, (q31_t)0x9C8EEB33, + (q31_t)0xAF6803A1, (q31_t)0x9CCE562B, (q31_t)0xAF1A0293, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9D4DE384, + (q31_t)0xAE7E965B, (q31_t)0x9D8E0596, (q31_t)0xAE312B91, + (q31_t)0x9DCE6462, (q31_t)0xADE3F33E, (q31_t)0x9E0EFFC1, + (q31_t)0xAD96ED91, (q31_t)0x9E4FD789, (q31_t)0xAD4A1ABA, + (q31_t)0x9E90EB94, (q31_t)0xACFD7AE8, (q31_t)0x9ED23BB9, + (q31_t)0xACB10E4A, (q31_t)0x9F13C7D0, (q31_t)0xAC64D510, + (q31_t)0x9F558FB0, (q31_t)0xAC18CF68, (q31_t)0x9F979331, + (q31_t)0xABCCFD82, (q31_t)0x9FD9D22A, (q31_t)0xAB815F8C, + (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA05F01E1, + (q31_t)0xAAEAC02B, (q31_t)0xA0A1F24C, (q31_t)0xAA9FBF1D, + (q31_t)0xA0E51D8C, (q31_t)0xAA54F2B9, (q31_t)0xA1288376, + (q31_t)0xAA0A5B2D, (q31_t)0xA16C23E1, (q31_t)0xA9BFF8A8, + (q31_t)0xA1AFFEA2, (q31_t)0xA975CB56, (q31_t)0xA1F41391, + (q31_t)0xA92BD366, (q31_t)0xA2386283, (q31_t)0xA8E21106, + (q31_t)0xA27CEB4F, (q31_t)0xA8988463, (q31_t)0xA2C1ADC9, + (q31_t)0xA84F2DA9, (q31_t)0xA306A9C7, (q31_t)0xA8060D08, + (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA3914DA7, + (q31_t)0xA7746EC0, (q31_t)0xA3D6F533, (q31_t)0xA72BF173, + (q31_t)0xA41CD598, (q31_t)0xA6E3AAF2, (q31_t)0xA462EEAC, + (q31_t)0xA69B9B68, (q31_t)0xA4A94042, (q31_t)0xA653C302, + (q31_t)0xA4EFCA31, (q31_t)0xA60C21ED, (q31_t)0xA5368C4B, + (q31_t)0xA5C4B855, (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xA5C4B855, (q31_t)0xA5368C4B, (q31_t)0xA60C21ED, + (q31_t)0xA4EFCA31, (q31_t)0xA653C302, (q31_t)0xA4A94042, + (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA6E3AAF2, + (q31_t)0xA41CD598, (q31_t)0xA72BF173, (q31_t)0xA3D6F533, + (q31_t)0xA7746EC0, (q31_t)0xA3914DA7, (q31_t)0xA7BD22AB, + (q31_t)0xA34BDF20, (q31_t)0xA8060D08, (q31_t)0xA306A9C7, + (q31_t)0xA84F2DA9, (q31_t)0xA2C1ADC9, (q31_t)0xA8988463, + (q31_t)0xA27CEB4F, (q31_t)0xA8E21106, (q31_t)0xA2386283, + (q31_t)0xA92BD366, (q31_t)0xA1F41391, (q31_t)0xA975CB56, + (q31_t)0xA1AFFEA2, (q31_t)0xA9BFF8A8, (q31_t)0xA16C23E1, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAA54F2B9, + (q31_t)0xA0E51D8C, (q31_t)0xAA9FBF1D, (q31_t)0xA0A1F24C, + (q31_t)0xAAEAC02B, (q31_t)0xA05F01E1, (q31_t)0xAB35F5B5, + (q31_t)0xA01C4C72, (q31_t)0xAB815F8C, (q31_t)0x9FD9D22A, + (q31_t)0xABCCFD82, (q31_t)0x9F979331, (q31_t)0xAC18CF68, + (q31_t)0x9F558FB0, (q31_t)0xAC64D510, (q31_t)0x9F13C7D0, + (q31_t)0xACB10E4A, (q31_t)0x9ED23BB9, (q31_t)0xACFD7AE8, + (q31_t)0x9E90EB94, (q31_t)0xAD4A1ABA, (q31_t)0x9E4FD789, + (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xADE3F33E, + (q31_t)0x9DCE6462, (q31_t)0xAE312B91, (q31_t)0x9D8E0596, + (q31_t)0xAE7E965B, (q31_t)0x9D4DE384, (q31_t)0xAECC336B, + (q31_t)0x9D0DFE53, (q31_t)0xAF1A0293, (q31_t)0x9CCE562B, + (q31_t)0xAF6803A1, (q31_t)0x9C8EEB33, (q31_t)0xAFB63667, + (q31_t)0x9C4FBD92, (q31_t)0xB0049AB2, (q31_t)0x9C10CD70, + (q31_t)0xB0533055, (q31_t)0x9BD21AF2, (q31_t)0xB0A1F71C, + (q31_t)0x9B93A640, (q31_t)0xB0F0EEDA, (q31_t)0x9B556F80, + (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB18F7070, + (q31_t)0x9AD9BC71, (q31_t)0xB1DEF9E8, (q31_t)0x9A9C406D, + (q31_t)0xB22EB392, (q31_t)0x9A5F02F5, (q31_t)0xB27E9D3B, + (q31_t)0x9A22042C, (q31_t)0xB2CEB6B5, (q31_t)0x99E5443A, + (q31_t)0xB31EFFCB, (q31_t)0x99A8C344, (q31_t)0xB36F784E, + (q31_t)0x996C816F, (q31_t)0xB3C0200C, (q31_t)0x99307EE0, + (q31_t)0xB410F6D2, (q31_t)0x98F4BBBC, (q31_t)0xB461FC70, + (q31_t)0x98B93828, (q31_t)0xB4B330B2, (q31_t)0x987DF449, + (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB556245E, + (q31_t)0x98082C3B, (q31_t)0xB5A7E362, (q31_t)0x97CDA855, + (q31_t)0xB5F9D042, (q31_t)0x979364B5, (q31_t)0xB64BEACC, + (q31_t)0x9759617E, (q31_t)0xB69E32CD, (q31_t)0x971F9ED6, + (q31_t)0xB6F0A811, (q31_t)0x96E61CDF, (q31_t)0xB7434A67, + (q31_t)0x96ACDBBD, (q31_t)0xB796199B, (q31_t)0x9673DB94, + (q31_t)0xB7E9157A, (q31_t)0x963B1C85, (q31_t)0xB83C3DD1, + (q31_t)0x96029EB5, (q31_t)0xB88F926C, (q31_t)0x95CA6246, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xB936BFA3, + (q31_t)0x955AAE17, (q31_t)0xB98A97D8, (q31_t)0x9523369B, + (q31_t)0xB9DE9B83, (q31_t)0x94EC010B, (q31_t)0xBA32CA70, + (q31_t)0x94B50D87, (q31_t)0xBA87246C, (q31_t)0x947E5C32, + (q31_t)0xBADBA943, (q31_t)0x9447ED2F, (q31_t)0xBB3058C0, + (q31_t)0x9411C09D, (q31_t)0xBB8532AF, (q31_t)0x93DBD69F, + (q31_t)0xBBDA36DC, (q31_t)0x93A62F56, (q31_t)0xBC2F6513, + (q31_t)0x9370CAE4, (q31_t)0xBC84BD1E, (q31_t)0x933BA968, + (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBD2FE9E1, + (q31_t)0x92D22FD8, (q31_t)0xBD85BE2F, (q31_t)0x929DD805, + (q31_t)0xBDDBBB7F, (q31_t)0x9269C3AC, (q31_t)0xBE31E19B, + (q31_t)0x9235F2EB, (q31_t)0xBE88304F, (q31_t)0x920265E4, + (q31_t)0xBEDEA765, (q31_t)0x91CF1CB6, (q31_t)0xBF3546A8, + (q31_t)0x919C1780, (q31_t)0xBF8C0DE2, (q31_t)0x91695663, + (q31_t)0xBFE2FCDF, (q31_t)0x9136D97D, (q31_t)0xC03A1368, + (q31_t)0x9104A0ED, (q31_t)0xC0915147, (q31_t)0x90D2ACD3, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC1404233, + (q31_t)0x906F927B, (q31_t)0xC197F4D3, (q31_t)0x903E6C7A, + (q31_t)0xC1EFCDF2, (q31_t)0x900D8B69, (q31_t)0xC247CD5A, + (q31_t)0x8FDCEF66, (q31_t)0xC29FF2D4, (q31_t)0x8FAC988E, + (q31_t)0xC2F83E2A, (q31_t)0x8F7C8701, (q31_t)0xC350AF25, + (q31_t)0x8F4CBADB, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A, + (q31_t)0xC4020132, (q31_t)0x8EEDF33B, (q31_t)0xC45AE1D7, + (q31_t)0x8EBEF7FB, (q31_t)0xC4B3E746, (q31_t)0x8E904298, + (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC5665FA8, + (q31_t)0x8E33A9D9, (q31_t)0xC5BFD22E, (q31_t)0x8E05C6B7, + (q31_t)0xC61968A2, (q31_t)0x8DD829E4, (q31_t)0xC67322CD, + (q31_t)0x8DAAD37B, (q31_t)0xC6CD0079, (q31_t)0x8D7DC399, + (q31_t)0xC727016C, (q31_t)0x8D50FA59, (q31_t)0xC7812571, + (q31_t)0x8D2477D8, (q31_t)0xC7DB6C50, (q31_t)0x8CF83C30, + (q31_t)0xC835D5D0, (q31_t)0x8CCC477D, (q31_t)0xC89061BA, + (q31_t)0x8CA099D9, (q31_t)0xC8EB0FD6, (q31_t)0x8C753361, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xC9A0D1C4, + (q31_t)0x8C1F3C5C, (q31_t)0xC9FBE527, (q31_t)0x8BF4AC05, + (q31_t)0xCA5719DB, (q31_t)0x8BCA6342, (q31_t)0xCAB26FA9, + (q31_t)0x8BA0622F, (q31_t)0xCB0DE658, (q31_t)0x8B76A8E4, + (q31_t)0xCB697DB0, (q31_t)0x8B4D377C, (q31_t)0xCBC53578, + (q31_t)0x8B240E10, (q31_t)0xCC210D78, (q31_t)0x8AFB2CBA, + (q31_t)0xCC7D0577, (q31_t)0x8AD29393, (q31_t)0xCCD91D3D, + (q31_t)0x8AAA42B4, (q31_t)0xCD355490, (q31_t)0x8A823A35, + (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCDEE20FC, + (q31_t)0x8A3302BD, (q31_t)0xCE4AB5A2, (q31_t)0x8A0BD3F5, + (q31_t)0xCEA768F2, (q31_t)0x89E4EDEE, (q31_t)0xCF043AB2, + (q31_t)0x89BE50C3, (q31_t)0xCF612AAA, (q31_t)0x8997FC89, + (q31_t)0xCFBE389F, (q31_t)0x8971F15A, (q31_t)0xD01B6459, + (q31_t)0x894C2F4C, (q31_t)0xD078AD9D, (q31_t)0x8926B677, + (q31_t)0xD0D61433, (q31_t)0x890186F1, (q31_t)0xD13397E1, + (q31_t)0x88DCA0D3, (q31_t)0xD191386D, (q31_t)0x88B80431, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD24CCF38, + (q31_t)0x886FA7C2, (q31_t)0xD2AAC504, (q31_t)0x884BE820, + (q31_t)0xD308D6C6, (q31_t)0x88287255, (q31_t)0xD3670445, + (q31_t)0x88054677, (q31_t)0xD3C54D46, (q31_t)0x87E2649B, + (q31_t)0xD423B190, (q31_t)0x87BFCCD7, (q31_t)0xD48230E8, + (q31_t)0x879D7F40, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC, + (q31_t)0xD53F7FDA, (q31_t)0x8759C2EF, (q31_t)0xD59E4EFE, + (q31_t)0x8738545E, (q31_t)0xD5FD3847, (q31_t)0x8717304E, + (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD6BB585D, + (q31_t)0x86D5C802, (q31_t)0xD71A8EB5, (q31_t)0x86B583EE, + (q31_t)0xD779DE46, (q31_t)0x86958AAB, (q31_t)0xD7D946D7, + (q31_t)0x8675DC4E, (q31_t)0xD838C82D, (q31_t)0x865678EA, + (q31_t)0xD898620C, (q31_t)0x86376092, (q31_t)0xD8F81439, + (q31_t)0x86189359, (q31_t)0xD957DE7A, (q31_t)0x85FA1152, + (q31_t)0xD9B7C093, (q31_t)0x85DBDA91, (q31_t)0xDA17BA4A, + (q31_t)0x85BDEF27, (q31_t)0xDA77CB62, (q31_t)0x85A04F28, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDB3832CD, + (q31_t)0x8565F1B0, (q31_t)0xDB9888A8, (q31_t)0x8549345C, + (q31_t)0xDBF8F4F8, (q31_t)0x852CC2BA, (q31_t)0xDC597781, + (q31_t)0x85109CDC, (q31_t)0xDCBA1008, (q31_t)0x84F4C2D3, + (q31_t)0xDD1ABE51, (q31_t)0x84D934B0, (q31_t)0xDD7B8220, + (q31_t)0x84BDF285, (q31_t)0xDDDC5B3A, (q31_t)0x84A2FC62, + (q31_t)0xDE3D4963, (q31_t)0x84885257, (q31_t)0xDE9E4C60, + (q31_t)0x846DF476, (q31_t)0xDEFF63F4, (q31_t)0x8453E2CE, + (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xDFC1CFF2, + (q31_t)0x8420A46B, (q31_t)0xE02323E5, (q31_t)0x840777CF, + (q31_t)0xE0848B7F, (q31_t)0x83EE97AC, (q31_t)0xE0E60684, + (q31_t)0x83D60411, (q31_t)0xE14794B9, (q31_t)0x83BDBD0D, + (q31_t)0xE1A935E1, (q31_t)0x83A5C2B0, (q31_t)0xE20AE9C1, + (q31_t)0x838E1507, (q31_t)0xE26CB01A, (q31_t)0x8376B422, + (q31_t)0xE2CE88B2, (q31_t)0x835FA00E, (q31_t)0xE330734C, + (q31_t)0x8348D8DB, (q31_t)0xE3926FAC, (q31_t)0x83325E97, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE4569CCB, + (q31_t)0x8306510F, (q31_t)0xE4B8CD10, (q31_t)0x82F0BDE8, + (q31_t)0xE51B0E2A, (q31_t)0x82DB77E5, (q31_t)0xE57D5FDA, + (q31_t)0x82C67F13, (q31_t)0xE5DFC1E4, (q31_t)0x82B1D381, + (q31_t)0xE642340D, (q31_t)0x829D753A, (q31_t)0xE6A4B616, + (q31_t)0x8289644A, (q31_t)0xE70747C3, (q31_t)0x8275A0C0, + (q31_t)0xE769E8D8, (q31_t)0x82622AA5, (q31_t)0xE7CC9917, + (q31_t)0x824F0208, (q31_t)0xE82F5844, (q31_t)0x823C26F2, + (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xE8F50273, + (q31_t)0x8217598F, (q31_t)0xE957ECFB, (q31_t)0x82056758, + (q31_t)0xE9BAE57C, (q31_t)0x81F3C2D7, (q31_t)0xEA1DEBBB, + (q31_t)0x81E26C16, (q31_t)0xEA80FF79, (q31_t)0x81D16320, + (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEB474E80, + (q31_t)0x81B03AC1, (q31_t)0xEBAA894E, (q31_t)0x81A01B6C, + (q31_t)0xEC0DD0A8, (q31_t)0x81904A0C, (q31_t)0xEC71244F, + (q31_t)0x8180C6A9, (q31_t)0xECD48406, (q31_t)0x8171914E, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xED9B66B2, + (q31_t)0x815410D3, (q31_t)0xEDFEE92B, (q31_t)0x8145C5C6, + (q31_t)0xEE6276BF, (q31_t)0x8137C8E6, (q31_t)0xEEC60F31, + (q31_t)0x812A1A39, (q31_t)0xEF29B243, (q31_t)0x811CB9CA, + (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xEFF11752, + (q31_t)0x8102E3C3, (q31_t)0xF054D8D4, (q31_t)0x80F66E3C, + (q31_t)0xF0B8A401, (q31_t)0x80EA4712, (q31_t)0xF11C789A, + (q31_t)0x80DE6E4C, (q31_t)0xF1805662, (q31_t)0x80D2E3F1, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF2482C89, + (q31_t)0x80BCBA9C, (q31_t)0xF2AC246D, (q31_t)0x80B21BAF, + (q31_t)0xF310248A, (q31_t)0x80A7CB49, (q31_t)0xF3742CA1, + (q31_t)0x809DC970, (q31_t)0xF3D83C76, (q31_t)0x8094162B, + (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF4A07260, + (q31_t)0x80819B74, (q31_t)0xF50497FA, (q31_t)0x8078D40D, + (q31_t)0xF568C45A, (q31_t)0x80705B50, (q31_t)0xF5CCF743, + (q31_t)0x80683143, (q31_t)0xF6313076, (q31_t)0x806055EA, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF6F9B4C5, + (q31_t)0x80518B6B, (q31_t)0xF75DFF65, (q31_t)0x804A9C4D, + (q31_t)0xF7C24F58, (q31_t)0x8043FBF6, (q31_t)0xF826A461, + (q31_t)0x803DAA69, (q31_t)0xF88AFE41, (q31_t)0x8037A7AC, + (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF953BF90, + (q31_t)0x802C8EAD, (q31_t)0xF9B82683, (q31_t)0x80277872, + (q31_t)0xFA1C9156, (q31_t)0x8022B113, (q31_t)0xFA80FFCB, + (q31_t)0x801E3894, (q31_t)0xFAE571A4, (q31_t)0x801A0EF7, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFBAE5E89, + (q31_t)0x8012A86F, (q31_t)0xFC12D919, (q31_t)0x800F6B88, + (q31_t)0xFC775616, (q31_t)0x800C7D8C, (q31_t)0xFCDBD541, + (q31_t)0x8009DE7D, (q31_t)0xFD40565B, (q31_t)0x80078E5E, + (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFE095D69, + (q31_t)0x8003DAF0, (q31_t)0xFE6DE2E0, (q31_t)0x800277A5, + (q31_t)0xFED2694F, (q31_t)0x8001634D, (q31_t)0xFF36F078, + (q31_t)0x80009DE9, (q31_t)0xFF9B781D, (q31_t)0x8000277A +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par +
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 4096, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_4096_q31[6144] = +{ + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFFF621, + (q31_t)0x003243F5, (q31_t)0x7FFFD885, (q31_t)0x006487E3, + (q31_t)0x7FFFA72C, (q31_t)0x0096CBC1, (q31_t)0x7FFF6216, + (q31_t)0x00C90F88, (q31_t)0x7FFF0942, (q31_t)0x00FB532F, + (q31_t)0x7FFE9CB2, (q31_t)0x012D96B0, (q31_t)0x7FFE1C64, + (q31_t)0x015FDA03, (q31_t)0x7FFD885A, (q31_t)0x01921D1F, + (q31_t)0x7FFCE093, (q31_t)0x01C45FFE, (q31_t)0x7FFC250F, + (q31_t)0x01F6A296, (q31_t)0x7FFB55CE, (q31_t)0x0228E4E1, + (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF97C17, + (q31_t)0x028D6870, (q31_t)0x7FF871A1, (q31_t)0x02BFA9A4, + (q31_t)0x7FF7536F, (q31_t)0x02F1EA6B, (q31_t)0x7FF62182, + (q31_t)0x03242ABF, (q31_t)0x7FF4DBD8, (q31_t)0x03566A96, + (q31_t)0x7FF38273, (q31_t)0x0388A9E9, (q31_t)0x7FF21553, + (q31_t)0x03BAE8B1, (q31_t)0x7FF09477, (q31_t)0x03ED26E6, + (q31_t)0x7FEEFFE1, (q31_t)0x041F647F, (q31_t)0x7FED5790, + (q31_t)0x0451A176, (q31_t)0x7FEB9B85, (q31_t)0x0483DDC3, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE7E840, + (q31_t)0x04E8543D, (q31_t)0x7FE5F108, (q31_t)0x051A8E5C, + (q31_t)0x7FE3E616, (q31_t)0x054CC7B0, (q31_t)0x7FE1C76B, + (q31_t)0x057F0034, (q31_t)0x7FDF9508, (q31_t)0x05B137DF, + (q31_t)0x7FDD4EEC, (q31_t)0x05E36EA9, (q31_t)0x7FDAF518, + (q31_t)0x0615A48A, (q31_t)0x7FD8878D, (q31_t)0x0647D97C, + (q31_t)0x7FD6064B, (q31_t)0x067A0D75, (q31_t)0x7FD37152, + (q31_t)0x06AC406F, (q31_t)0x7FD0C8A3, (q31_t)0x06DE7261, + (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FCB3C23, + (q31_t)0x0742D310, (q31_t)0x7FC85853, (q31_t)0x077501BE, + (q31_t)0x7FC560CF, (q31_t)0x07A72F45, (q31_t)0x7FC25596, + (q31_t)0x07D95B9E, (q31_t)0x7FBF36A9, (q31_t)0x080B86C1, + (q31_t)0x7FBC040A, (q31_t)0x083DB0A7, (q31_t)0x7FB8BDB7, + (q31_t)0x086FD947, (q31_t)0x7FB563B2, (q31_t)0x08A2009A, + (q31_t)0x7FB1F5FC, (q31_t)0x08D42698, (q31_t)0x7FAE7494, + (q31_t)0x09064B3A, (q31_t)0x7FAADF7C, (q31_t)0x09386E77, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7FA37A3C, + (q31_t)0x099CB0A7, (q31_t)0x7F9FAA15, (q31_t)0x09CECF89, + (q31_t)0x7F9BC63F, (q31_t)0x0A00ECE8, (q31_t)0x7F97CEBC, + (q31_t)0x0A3308BC, (q31_t)0x7F93C38C, (q31_t)0x0A6522FE, + (q31_t)0x7F8FA4AF, (q31_t)0x0A973BA5, (q31_t)0x7F8B7226, + (q31_t)0x0AC952AA, (q31_t)0x7F872BF3, (q31_t)0x0AFB6805, + (q31_t)0x7F82D214, (q31_t)0x0B2D7BAE, (q31_t)0x7F7E648B, + (q31_t)0x0B5F8D9F, (q31_t)0x7F79E35A, (q31_t)0x0B919DCE, + (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F70A5FD, + (q31_t)0x0BF5B8CB, (q31_t)0x7F6BE9D4, (q31_t)0x0C27C389, + (q31_t)0x7F671A04, (q31_t)0x0C59CC67, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7F5D3F75, (q31_t)0x0CBDD865, + (q31_t)0x7F5834B6, (q31_t)0x0CEFDB75, (q31_t)0x7F531654, + (q31_t)0x0D21DC87, (q31_t)0x7F4DE450, (q31_t)0x0D53DB92, + (q31_t)0x7F489EAA, (q31_t)0x0D85D88F, (q31_t)0x7F434563, + (q31_t)0x0DB7D376, (q31_t)0x7F3DD87C, (q31_t)0x0DE9CC3F, + (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F32C3D0, + (q31_t)0x0E4DB75B, (q31_t)0x7F2D1C0E, (q31_t)0x0E7FA99D, + (q31_t)0x7F2760AF, (q31_t)0x0EB199A3, (q31_t)0x7F2191B4, + (q31_t)0x0EE38765, (q31_t)0x7F1BAF1E, (q31_t)0x0F1572DC, + (q31_t)0x7F15B8EE, (q31_t)0x0F475BFE, (q31_t)0x7F0FAF24, + (q31_t)0x0F7942C6, (q31_t)0x7F0991C3, (q31_t)0x0FAB272B, + (q31_t)0x7F0360CB, (q31_t)0x0FDD0925, (q31_t)0x7EFD1C3C, + (q31_t)0x100EE8AD, (q31_t)0x7EF6C418, (q31_t)0x1040C5BB, + (q31_t)0x7EF0585F, (q31_t)0x1072A047, (q31_t)0x7EE9D913, + (q31_t)0x10A4784A, (q31_t)0x7EE34635, (q31_t)0x10D64DBC, + (q31_t)0x7EDC9FC6, (q31_t)0x11082096, (q31_t)0x7ED5E5C6, + (q31_t)0x1139F0CE, (q31_t)0x7ECF1837, (q31_t)0x116BBE5F, + (q31_t)0x7EC8371A, (q31_t)0x119D8940, (q31_t)0x7EC1426F, + (q31_t)0x11CF516A, (q31_t)0x7EBA3A39, (q31_t)0x120116D4, + (q31_t)0x7EB31E77, (q31_t)0x1232D978, (q31_t)0x7EABEF2C, + (q31_t)0x1264994E, (q31_t)0x7EA4AC58, (q31_t)0x1296564D, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E95EC19, + (q31_t)0x12F9C7AA, (q31_t)0x7E8E6EB1, (q31_t)0x132B7BF9, + (q31_t)0x7E86DDC5, (q31_t)0x135D2D53, (q31_t)0x7E7F3956, + (q31_t)0x138EDBB0, (q31_t)0x7E778165, (q31_t)0x13C0870A, + (q31_t)0x7E6FB5F3, (q31_t)0x13F22F57, (q31_t)0x7E67D702, + (q31_t)0x1423D492, (q31_t)0x7E5FE493, (q31_t)0x145576B1, + (q31_t)0x7E57DEA6, (q31_t)0x148715AD, (q31_t)0x7E4FC53E, + (q31_t)0x14B8B17F, (q31_t)0x7E47985B, (q31_t)0x14EA4A1F, + (q31_t)0x7E3F57FE, (q31_t)0x151BDF85, (q31_t)0x7E37042A, + (q31_t)0x154D71AA, (q31_t)0x7E2E9CDF, (q31_t)0x157F0086, + (q31_t)0x7E26221E, (q31_t)0x15B08C11, (q31_t)0x7E1D93E9, + (q31_t)0x15E21444, (q31_t)0x7E14F242, (q31_t)0x16139917, + (q31_t)0x7E0C3D29, (q31_t)0x16451A83, (q31_t)0x7E03749F, + (q31_t)0x1676987F, (q31_t)0x7DFA98A7, (q31_t)0x16A81305, + (q31_t)0x7DF1A942, (q31_t)0x16D98A0C, (q31_t)0x7DE8A670, + (q31_t)0x170AFD8D, (q31_t)0x7DDF9034, (q31_t)0x173C6D80, + (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7DCD2981, + (q31_t)0x179F429F, (q31_t)0x7DC3D90D, (q31_t)0x17D0A7BB, + (q31_t)0x7DBA7534, (q31_t)0x1802092C, (q31_t)0x7DB0FDF7, + (q31_t)0x183366E8, (q31_t)0x7DA77359, (q31_t)0x1864C0E9, + (q31_t)0x7D9DD55A, (q31_t)0x18961727, (q31_t)0x7D9423FB, + (q31_t)0x18C7699B, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7D808727, (q31_t)0x192A0303, (q31_t)0x7D769BB5, + (q31_t)0x195B49E9, (q31_t)0x7D6C9CE9, (q31_t)0x198C8CE6, + (q31_t)0x7D628AC5, (q31_t)0x19BDCBF2, (q31_t)0x7D58654C, + (q31_t)0x19EF0706, (q31_t)0x7D4E2C7E, (q31_t)0x1A203E1B, + (q31_t)0x7D43E05E, (q31_t)0x1A517127, (q31_t)0x7D3980EC, + (q31_t)0x1A82A025, (q31_t)0x7D2F0E2A, (q31_t)0x1AB3CB0C, + (q31_t)0x7D24881A, (q31_t)0x1AE4F1D6, (q31_t)0x7D19EEBE, + (q31_t)0x1B161479, (q31_t)0x7D0F4218, (q31_t)0x1B4732EF, + (q31_t)0x7D048228, (q31_t)0x1B784D30, (q31_t)0x7CF9AEF0, + (q31_t)0x1BA96334, (q31_t)0x7CEEC873, (q31_t)0x1BDA74F5, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7CD8C1AD, + (q31_t)0x1C3C8B8C, (q31_t)0x7CCDA168, (q31_t)0x1C6D9053, + (q31_t)0x7CC26DE5, (q31_t)0x1C9E90B8, (q31_t)0x7CB72724, + (q31_t)0x1CCF8CB3, (q31_t)0x7CABCD27, (q31_t)0x1D00843C, + (q31_t)0x7CA05FF1, (q31_t)0x1D31774D, (q31_t)0x7C94DF82, + (q31_t)0x1D6265DD, (q31_t)0x7C894BDD, (q31_t)0x1D934FE5, + (q31_t)0x7C7DA504, (q31_t)0x1DC4355D, (q31_t)0x7C71EAF8, + (q31_t)0x1DF5163F, (q31_t)0x7C661DBB, (q31_t)0x1E25F281, + (q31_t)0x7C5A3D4F, (q31_t)0x1E56CA1E, (q31_t)0x7C4E49B6, + (q31_t)0x1E879D0C, (q31_t)0x7C4242F2, (q31_t)0x1EB86B46, + (q31_t)0x7C362904, (q31_t)0x1EE934C2, (q31_t)0x7C29FBEE, + (q31_t)0x1F19F97B, (q31_t)0x7C1DBBB2, (q31_t)0x1F4AB967, + (q31_t)0x7C116853, (q31_t)0x1F7B7480, (q31_t)0x7C0501D1, + (q31_t)0x1FAC2ABF, (q31_t)0x7BF88830, (q31_t)0x1FDCDC1A, + (q31_t)0x7BEBFB70, (q31_t)0x200D888C, (q31_t)0x7BDF5B94, + (q31_t)0x203E300D, (q31_t)0x7BD2A89E, (q31_t)0x206ED295, + (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7BB9096A, + (q31_t)0x20D0089B, (q31_t)0x7BAC1D31, (q31_t)0x21009C0B, + (q31_t)0x7B9F1DE5, (q31_t)0x21312A65, (q31_t)0x7B920B89, + (q31_t)0x2161B39F, (q31_t)0x7B84E61E, (q31_t)0x219237B4, + (q31_t)0x7B77ADA8, (q31_t)0x21C2B69C, (q31_t)0x7B6A6227, + (q31_t)0x21F3304E, (q31_t)0x7B5D039D, (q31_t)0x2223A4C5, + (q31_t)0x7B4F920E, (q31_t)0x225413F8, (q31_t)0x7B420D7A, + (q31_t)0x22847DDF, (q31_t)0x7B3475E4, (q31_t)0x22B4E274, + (q31_t)0x7B26CB4F, (q31_t)0x22E541AE, (q31_t)0x7B190DBB, + (q31_t)0x23159B87, (q31_t)0x7B0B3D2C, (q31_t)0x2345EFF7, + (q31_t)0x7AFD59A3, (q31_t)0x23763EF7, (q31_t)0x7AEF6323, + (q31_t)0x23A6887E, (q31_t)0x7AE159AE, (q31_t)0x23D6CC86, + (q31_t)0x7AD33D45, (q31_t)0x24070B07, (q31_t)0x7AC50DEB, + (q31_t)0x243743FA, (q31_t)0x7AB6CBA3, (q31_t)0x24677757, + (q31_t)0x7AA8766E, (q31_t)0x2497A517, (q31_t)0x7A9A0E4F, + (q31_t)0x24C7CD32, (q31_t)0x7A8B9348, (q31_t)0x24F7EFA1, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A6E648A, + (q31_t)0x2558235E, (q31_t)0x7A5FB0D8, (q31_t)0x2588349D, + (q31_t)0x7A50EA46, (q31_t)0x25B84012, (q31_t)0x7A4210D8, + (q31_t)0x25E845B5, (q31_t)0x7A33248F, (q31_t)0x26184581, + (q31_t)0x7A24256E, (q31_t)0x26483F6C, (q31_t)0x7A151377, + (q31_t)0x26783370, (q31_t)0x7A05EEAD, (q31_t)0x26A82185, + (q31_t)0x79F6B711, (q31_t)0x26D809A5, (q31_t)0x79E76CA6, + (q31_t)0x2707EBC6, (q31_t)0x79D80F6F, (q31_t)0x2737C7E3, + (q31_t)0x79C89F6D, (q31_t)0x27679DF4, (q31_t)0x79B91CA4, + (q31_t)0x27976DF1, (q31_t)0x79A98715, (q31_t)0x27C737D2, + (q31_t)0x7999DEC3, (q31_t)0x27F6FB92, (q31_t)0x798A23B1, + (q31_t)0x2826B928, (q31_t)0x797A55E0, (q31_t)0x2856708C, + (q31_t)0x796A7554, (q31_t)0x288621B9, (q31_t)0x795A820E, + (q31_t)0x28B5CCA5, (q31_t)0x794A7C11, (q31_t)0x28E5714A, + (q31_t)0x793A6360, (q31_t)0x29150FA1, (q31_t)0x792A37FE, + (q31_t)0x2944A7A2, (q31_t)0x7919F9EB, (q31_t)0x29743945, + (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78F945C3, + (q31_t)0x29D34958, (q31_t)0x78E8CFB1, (q31_t)0x2A02C7B8, + (q31_t)0x78D846FB, (q31_t)0x2A323F9D, (q31_t)0x78C7ABA1, + (q31_t)0x2A61B101, (q31_t)0x78B6FDA8, (q31_t)0x2A911BDB, + (q31_t)0x78A63D10, (q31_t)0x2AC08025, (q31_t)0x789569DE, + (q31_t)0x2AEFDDD8, (q31_t)0x78848413, (q31_t)0x2B1F34EB, + (q31_t)0x78738BB3, (q31_t)0x2B4E8558, (q31_t)0x786280BF, + (q31_t)0x2B7DCF17, (q31_t)0x7851633B, (q31_t)0x2BAD1221, + (q31_t)0x78403328, (q31_t)0x2BDC4E6F, (q31_t)0x782EF08B, + (q31_t)0x2C0B83F9, (q31_t)0x781D9B64, (q31_t)0x2C3AB2B9, + (q31_t)0x780C33B8, (q31_t)0x2C69DAA6, (q31_t)0x77FAB988, + (q31_t)0x2C98FBBA, (q31_t)0x77E92CD8, (q31_t)0x2CC815ED, + (q31_t)0x77D78DAA, (q31_t)0x2CF72939, (q31_t)0x77C5DC01, + (q31_t)0x2D263595, (q31_t)0x77B417DF, (q31_t)0x2D553AFB, + (q31_t)0x77A24148, (q31_t)0x2D843963, (q31_t)0x7790583D, + (q31_t)0x2DB330C7, (q31_t)0x777E5CC3, (q31_t)0x2DE2211E, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x775A2E88, + (q31_t)0x2E3FEC8B, (q31_t)0x7747FBCE, (q31_t)0x2E6EC792, + (q31_t)0x7735B6AE, (q31_t)0x2E9D9B70, (q31_t)0x77235F2D, + (q31_t)0x2ECC681E, (q31_t)0x7710F54B, (q31_t)0x2EFB2D94, + (q31_t)0x76FE790E, (q31_t)0x2F29EBCC, (q31_t)0x76EBEA77, + (q31_t)0x2F58A2BD, (q31_t)0x76D94988, (q31_t)0x2F875262, + (q31_t)0x76C69646, (q31_t)0x2FB5FAB2, (q31_t)0x76B3D0B3, + (q31_t)0x2FE49BA6, (q31_t)0x76A0F8D2, (q31_t)0x30133538, + (q31_t)0x768E0EA5, (q31_t)0x3041C760, (q31_t)0x767B1230, + (q31_t)0x30705217, (q31_t)0x76680376, (q31_t)0x309ED555, + (q31_t)0x7654E279, (q31_t)0x30CD5114, (q31_t)0x7641AF3C, + (q31_t)0x30FBC54D, (q31_t)0x762E69C3, (q31_t)0x312A31F8, + (q31_t)0x761B1211, (q31_t)0x3158970D, (q31_t)0x7607A827, + (q31_t)0x3186F487, (q31_t)0x75F42C0A, (q31_t)0x31B54A5D, + (q31_t)0x75E09DBD, (q31_t)0x31E39889, (q31_t)0x75CCFD42, + (q31_t)0x3211DF03, (q31_t)0x75B94A9C, (q31_t)0x32401DC5, + (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x7591AEDD, + (q31_t)0x329C8402, (q31_t)0x757DC5CA, (q31_t)0x32CAAB6F, + (q31_t)0x7569CA98, (q31_t)0x32F8CB07, (q31_t)0x7555BD4B, + (q31_t)0x3326E2C2, (q31_t)0x75419DE6, (q31_t)0x3354F29A, + (q31_t)0x752D6C6C, (q31_t)0x3382FA88, (q31_t)0x751928E0, + (q31_t)0x33B0FA84, (q31_t)0x7504D345, (q31_t)0x33DEF287, + (q31_t)0x74F06B9E, (q31_t)0x340CE28A, (q31_t)0x74DBF1EF, + (q31_t)0x343ACA87, (q31_t)0x74C7663A, (q31_t)0x3468AA76, + (q31_t)0x74B2C883, (q31_t)0x3496824F, (q31_t)0x749E18CD, + (q31_t)0x34C4520D, (q31_t)0x7489571B, (q31_t)0x34F219A7, + (q31_t)0x74748371, (q31_t)0x351FD917, (q31_t)0x745F9DD1, + (q31_t)0x354D9056, (q31_t)0x744AA63E, (q31_t)0x357B3F5D, + (q31_t)0x74359CBD, (q31_t)0x35A8E624, (q31_t)0x74208150, + (q31_t)0x35D684A5, (q31_t)0x740B53FA, (q31_t)0x36041AD9, + (q31_t)0x73F614C0, (q31_t)0x3631A8B7, (q31_t)0x73E0C3A3, + (q31_t)0x365F2E3B, (q31_t)0x73CB60A7, (q31_t)0x368CAB5C, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x73A06522, + (q31_t)0x36E78C5A, (q31_t)0x738ACC9E, (q31_t)0x3714F02A, + (q31_t)0x73752249, (q31_t)0x37424B7A, (q31_t)0x735F6626, + (q31_t)0x376F9E46, (q31_t)0x73499838, (q31_t)0x379CE884, + (q31_t)0x7333B883, (q31_t)0x37CA2A30, (q31_t)0x731DC709, + (q31_t)0x37F76340, (q31_t)0x7307C3D0, (q31_t)0x382493B0, + (q31_t)0x72F1AED8, (q31_t)0x3851BB76, (q31_t)0x72DB8828, + (q31_t)0x387EDA8E, (q31_t)0x72C54FC0, (q31_t)0x38ABF0EF, + (q31_t)0x72AF05A6, (q31_t)0x38D8FE93, (q31_t)0x7298A9DC, + (q31_t)0x39060372, (q31_t)0x72823C66, (q31_t)0x3932FF87, + (q31_t)0x726BBD48, (q31_t)0x395FF2C9, (q31_t)0x72552C84, + (q31_t)0x398CDD32, (q31_t)0x723E8A1F, (q31_t)0x39B9BEBB, + (q31_t)0x7227D61C, (q31_t)0x39E6975D, (q31_t)0x7211107D, + (q31_t)0x3A136712, (q31_t)0x71FA3948, (q31_t)0x3A402DD1, + (q31_t)0x71E3507F, (q31_t)0x3A6CEB95, (q31_t)0x71CC5626, + (q31_t)0x3A99A057, (q31_t)0x71B54A40, (q31_t)0x3AC64C0F, + (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x7186FDDE, + (q31_t)0x3B1F8847, (q31_t)0x716FBD68, (q31_t)0x3B4C18BA, + (q31_t)0x71586B73, (q31_t)0x3B78A007, (q31_t)0x71410804, + (q31_t)0x3BA51E29, (q31_t)0x7129931E, (q31_t)0x3BD19317, + (q31_t)0x71120CC5, (q31_t)0x3BFDFECD, (q31_t)0x70FA74FB, + (q31_t)0x3C2A6142, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70, + (q31_t)0x70CB1127, (q31_t)0x3C830A4F, (q31_t)0x70B34524, + (q31_t)0x3CAF50DA, (q31_t)0x709B67C0, (q31_t)0x3CDB8E09, + (q31_t)0x708378FE, (q31_t)0x3D07C1D5, (q31_t)0x706B78E3, + (q31_t)0x3D33EC39, (q31_t)0x70536771, (q31_t)0x3D600D2B, + (q31_t)0x703B44AC, (q31_t)0x3D8C24A7, (q31_t)0x70231099, + (q31_t)0x3DB832A5, (q31_t)0x700ACB3B, (q31_t)0x3DE4371F, + (q31_t)0x6FF27496, (q31_t)0x3E10320D, (q31_t)0x6FDA0CAD, + (q31_t)0x3E3C2369, (q31_t)0x6FC19385, (q31_t)0x3E680B2C, + (q31_t)0x6FA90920, (q31_t)0x3E93E94F, (q31_t)0x6F906D84, + (q31_t)0x3EBFBDCC, (q31_t)0x6F77C0B3, (q31_t)0x3EEB889C, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6F463383, + (q31_t)0x3F430118, (q31_t)0x6F2D532C, (q31_t)0x3F6EAEB8, + (q31_t)0x6F1461AF, (q31_t)0x3F9A528F, (q31_t)0x6EFB5F12, + (q31_t)0x3FC5EC97, (q31_t)0x6EE24B57, (q31_t)0x3FF17CCA, + (q31_t)0x6EC92682, (q31_t)0x401D0320, (q31_t)0x6EAFF098, + (q31_t)0x40487F93, (q31_t)0x6E96A99C, (q31_t)0x4073F21D, + (q31_t)0x6E7D5193, (q31_t)0x409F5AB6, (q31_t)0x6E63E87F, + (q31_t)0x40CAB957, (q31_t)0x6E4A6E65, (q31_t)0x40F60DFB, + (q31_t)0x6E30E349, (q31_t)0x4121589A, (q31_t)0x6E17472F, + (q31_t)0x414C992E, (q31_t)0x6DFD9A1B, (q31_t)0x4177CFB0, + (q31_t)0x6DE3DC11, (q31_t)0x41A2FC1A, (q31_t)0x6DCA0D14, + (q31_t)0x41CE1E64, (q31_t)0x6DB02D29, (q31_t)0x41F93688, + (q31_t)0x6D963C54, (q31_t)0x42244480, (q31_t)0x6D7C3A98, + (q31_t)0x424F4845, (q31_t)0x6D6227FA, (q31_t)0x427A41D0, + (q31_t)0x6D48047E, (q31_t)0x42A5311A, (q31_t)0x6D2DD027, + (q31_t)0x42D0161E, (q31_t)0x6D138AFA, (q31_t)0x42FAF0D4, + (q31_t)0x6CF934FB, (q31_t)0x4325C135, (q31_t)0x6CDECE2E, + (q31_t)0x4350873C, (q31_t)0x6CC45697, (q31_t)0x437B42E1, + (q31_t)0x6CA9CE3A, (q31_t)0x43A5F41E, (q31_t)0x6C8F351C, + (q31_t)0x43D09AEC, (q31_t)0x6C748B3F, (q31_t)0x43FB3745, + (q31_t)0x6C59D0A9, (q31_t)0x4425C923, (q31_t)0x6C3F055D, + (q31_t)0x4450507E, (q31_t)0x6C242960, (q31_t)0x447ACD50, + (q31_t)0x6C093CB6, (q31_t)0x44A53F93, (q31_t)0x6BEE3F62, + (q31_t)0x44CFA73F, (q31_t)0x6BD3316A, (q31_t)0x44FA044F, + (q31_t)0x6BB812D0, (q31_t)0x452456BC, (q31_t)0x6B9CE39B, + (q31_t)0x454E9E80, (q31_t)0x6B81A3CD, (q31_t)0x4578DB93, + (q31_t)0x6B66536A, (q31_t)0x45A30DF0, (q31_t)0x6B4AF278, + (q31_t)0x45CD358F, (q31_t)0x6B2F80FA, (q31_t)0x45F7526B, + (q31_t)0x6B13FEF5, (q31_t)0x4621647C, (q31_t)0x6AF86C6C, + (q31_t)0x464B6BBD, (q31_t)0x6ADCC964, (q31_t)0x46756827, + (q31_t)0x6AC115E1, (q31_t)0x469F59B4, (q31_t)0x6AA551E8, + (q31_t)0x46C9405C, (q31_t)0x6A897D7D, (q31_t)0x46F31C1A, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x6A51A361, + (q31_t)0x4746B2BC, (q31_t)0x6A359DB9, (q31_t)0x47706D93, + (q31_t)0x6A1987B0, (q31_t)0x479A1D66, (q31_t)0x69FD614A, + (q31_t)0x47C3C22E, (q31_t)0x69E12A8C, (q31_t)0x47ED5BE6, + (q31_t)0x69C4E37A, (q31_t)0x4816EA85, (q31_t)0x69A88C18, + (q31_t)0x48406E07, (q31_t)0x698C246C, (q31_t)0x4869E664, + (q31_t)0x696FAC78, (q31_t)0x48935397, (q31_t)0x69532442, + (q31_t)0x48BCB598, (q31_t)0x69368BCE, (q31_t)0x48E60C62, + (q31_t)0x6919E320, (q31_t)0x490F57EE, (q31_t)0x68FD2A3D, + (q31_t)0x49389836, (q31_t)0x68E06129, (q31_t)0x4961CD32, + (q31_t)0x68C387E9, (q31_t)0x498AF6DE, (q31_t)0x68A69E81, + (q31_t)0x49B41533, (q31_t)0x6889A4F5, (q31_t)0x49DD282A, + (q31_t)0x686C9B4B, (q31_t)0x4A062FBD, (q31_t)0x684F8186, + (q31_t)0x4A2F2BE5, (q31_t)0x683257AA, (q31_t)0x4A581C9D, + (q31_t)0x68151DBE, (q31_t)0x4A8101DE, (q31_t)0x67F7D3C4, + (q31_t)0x4AA9DBA1, (q31_t)0x67DA79C2, (q31_t)0x4AD2A9E1, + (q31_t)0x67BD0FBC, (q31_t)0x4AFB6C97, (q31_t)0x679F95B7, + (q31_t)0x4B2423BD, (q31_t)0x67820BB6, (q31_t)0x4B4CCF4D, + (q31_t)0x676471C0, (q31_t)0x4B756F3F, (q31_t)0x6746C7D7, + (q31_t)0x4B9E038F, (q31_t)0x67290E02, (q31_t)0x4BC68C36, + (q31_t)0x670B4443, (q31_t)0x4BEF092D, (q31_t)0x66ED6AA1, + (q31_t)0x4C177A6E, (q31_t)0x66CF811F, (q31_t)0x4C3FDFF3, + (q31_t)0x66B187C3, (q31_t)0x4C6839B6, (q31_t)0x66937E90, + (q31_t)0x4C9087B1, (q31_t)0x6675658C, (q31_t)0x4CB8C9DD, + (q31_t)0x66573CBB, (q31_t)0x4CE10034, (q31_t)0x66390422, + (q31_t)0x4D092AB0, (q31_t)0x661ABBC5, (q31_t)0x4D31494B, + (q31_t)0x65FC63A9, (q31_t)0x4D595BFE, (q31_t)0x65DDFBD3, + (q31_t)0x4D8162C4, (q31_t)0x65BF8447, (q31_t)0x4DA95D96, + (q31_t)0x65A0FD0B, (q31_t)0x4DD14C6E, (q31_t)0x65826622, + (q31_t)0x4DF92F45, (q31_t)0x6563BF92, (q31_t)0x4E210617, + (q31_t)0x6545095F, (q31_t)0x4E48D0DC, (q31_t)0x6526438E, + (q31_t)0x4E708F8F, (q31_t)0x65076E24, (q31_t)0x4E984229, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x64C99498, + (q31_t)0x4EE782FA, (q31_t)0x64AA907F, (q31_t)0x4F0F1126, + (q31_t)0x648B7CDF, (q31_t)0x4F369320, (q31_t)0x646C59BF, + (q31_t)0x4F5E08E3, (q31_t)0x644D2722, (q31_t)0x4F857268, + (q31_t)0x642DE50D, (q31_t)0x4FACCFAB, (q31_t)0x640E9385, + (q31_t)0x4FD420A3, (q31_t)0x63EF328F, (q31_t)0x4FFB654D, + (q31_t)0x63CFC230, (q31_t)0x50229DA0, (q31_t)0x63B0426D, + (q31_t)0x5049C999, (q31_t)0x6390B34A, (q31_t)0x5070E92F, + (q31_t)0x637114CC, (q31_t)0x5097FC5E, (q31_t)0x635166F8, + (q31_t)0x50BF031F, (q31_t)0x6331A9D4, (q31_t)0x50E5FD6C, + (q31_t)0x6311DD63, (q31_t)0x510CEB40, (q31_t)0x62F201AC, + (q31_t)0x5133CC94, (q31_t)0x62D216B2, (q31_t)0x515AA162, + (q31_t)0x62B21C7B, (q31_t)0x518169A4, (q31_t)0x6292130C, + (q31_t)0x51A82555, (q31_t)0x6271FA69, (q31_t)0x51CED46E, + (q31_t)0x6251D297, (q31_t)0x51F576E9, (q31_t)0x62319B9D, + (q31_t)0x521C0CC1, (q31_t)0x6211557D, (q31_t)0x524295EF, + (q31_t)0x61F1003E, (q31_t)0x5269126E, (q31_t)0x61D09BE5, + (q31_t)0x528F8237, (q31_t)0x61B02876, (q31_t)0x52B5E545, + (q31_t)0x618FA5F6, (q31_t)0x52DC3B92, (q31_t)0x616F146B, + (q31_t)0x53028517, (q31_t)0x614E73D9, (q31_t)0x5328C1D0, + (q31_t)0x612DC446, (q31_t)0x534EF1B5, (q31_t)0x610D05B7, + (q31_t)0x537514C1, (q31_t)0x60EC3830, (q31_t)0x539B2AEF, + (q31_t)0x60CB5BB6, (q31_t)0x53C13438, (q31_t)0x60AA704F, + (q31_t)0x53E73097, (q31_t)0x60897600, (q31_t)0x540D2005, + (q31_t)0x60686CCE, (q31_t)0x5433027D, (q31_t)0x604754BE, + (q31_t)0x5458D7F9, (q31_t)0x60262DD5, (q31_t)0x547EA073, + (q31_t)0x6004F818, (q31_t)0x54A45BE5, (q31_t)0x5FE3B38D, + (q31_t)0x54CA0A4A, (q31_t)0x5FC26038, (q31_t)0x54EFAB9C, + (q31_t)0x5FA0FE1E, (q31_t)0x55153FD4, (q31_t)0x5F7F8D46, + (q31_t)0x553AC6ED, (q31_t)0x5F5E0DB3, (q31_t)0x556040E2, + (q31_t)0x5F3C7F6B, (q31_t)0x5585ADAC, (q31_t)0x5F1AE273, + (q31_t)0x55AB0D46, (q31_t)0x5EF936D1, (q31_t)0x55D05FAA, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5EB5B3A1, + (q31_t)0x561ADCB8, (q31_t)0x5E93DC1F, (q31_t)0x56400757, + (q31_t)0x5E71F606, (q31_t)0x566524AA, (q31_t)0x5E50015D, + (q31_t)0x568A34A9, (q31_t)0x5E2DFE28, (q31_t)0x56AF3750, + (q31_t)0x5E0BEC6E, (q31_t)0x56D42C99, (q31_t)0x5DE9CC32, + (q31_t)0x56F9147E, (q31_t)0x5DC79D7C, (q31_t)0x571DEEF9, + (q31_t)0x5DA5604E, (q31_t)0x5742BC05, (q31_t)0x5D8314B0, + (q31_t)0x57677B9D, (q31_t)0x5D60BAA6, (q31_t)0x578C2DB9, + (q31_t)0x5D3E5236, (q31_t)0x57B0D256, (q31_t)0x5D1BDB65, + (q31_t)0x57D5696C, (q31_t)0x5CF95638, (q31_t)0x57F9F2F7, + (q31_t)0x5CD6C2B4, (q31_t)0x581E6EF1, (q31_t)0x5CB420DF, + (q31_t)0x5842DD54, (q31_t)0x5C9170BF, (q31_t)0x58673E1B, + (q31_t)0x5C6EB258, (q31_t)0x588B913F, (q31_t)0x5C4BE5B0, + (q31_t)0x58AFD6BC, (q31_t)0x5C290ACC, (q31_t)0x58D40E8C, + (q31_t)0x5C0621B2, (q31_t)0x58F838A9, (q31_t)0x5BE32A67, + (q31_t)0x591C550E, (q31_t)0x5BC024F0, (q31_t)0x594063B4, + (q31_t)0x5B9D1153, (q31_t)0x59646497, (q31_t)0x5B79EF96, + (q31_t)0x598857B1, (q31_t)0x5B56BFBD, (q31_t)0x59AC3CFD, + (q31_t)0x5B3381CE, (q31_t)0x59D01474, (q31_t)0x5B1035CF, + (q31_t)0x59F3DE12, (q31_t)0x5AECDBC4, (q31_t)0x5A1799D0, + (q31_t)0x5AC973B4, (q31_t)0x5A3B47AA, (q31_t)0x5AA5FDA4, + (q31_t)0x5A5EE79A, (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x5A5EE79A, (q31_t)0x5AA5FDA4, (q31_t)0x5A3B47AA, + (q31_t)0x5AC973B4, (q31_t)0x5A1799D0, (q31_t)0x5AECDBC4, + (q31_t)0x59F3DE12, (q31_t)0x5B1035CF, (q31_t)0x59D01474, + (q31_t)0x5B3381CE, (q31_t)0x59AC3CFD, (q31_t)0x5B56BFBD, + (q31_t)0x598857B1, (q31_t)0x5B79EF96, (q31_t)0x59646497, + (q31_t)0x5B9D1153, (q31_t)0x594063B4, (q31_t)0x5BC024F0, + (q31_t)0x591C550E, (q31_t)0x5BE32A67, (q31_t)0x58F838A9, + (q31_t)0x5C0621B2, (q31_t)0x58D40E8C, (q31_t)0x5C290ACC, + (q31_t)0x58AFD6BC, (q31_t)0x5C4BE5B0, (q31_t)0x588B913F, + (q31_t)0x5C6EB258, (q31_t)0x58673E1B, (q31_t)0x5C9170BF, + (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x581E6EF1, + (q31_t)0x5CD6C2B4, (q31_t)0x57F9F2F7, (q31_t)0x5CF95638, + (q31_t)0x57D5696C, (q31_t)0x5D1BDB65, (q31_t)0x57B0D256, + (q31_t)0x5D3E5236, (q31_t)0x578C2DB9, (q31_t)0x5D60BAA6, + (q31_t)0x57677B9D, (q31_t)0x5D8314B0, (q31_t)0x5742BC05, + (q31_t)0x5DA5604E, (q31_t)0x571DEEF9, (q31_t)0x5DC79D7C, + (q31_t)0x56F9147E, (q31_t)0x5DE9CC32, (q31_t)0x56D42C99, + (q31_t)0x5E0BEC6E, (q31_t)0x56AF3750, (q31_t)0x5E2DFE28, + (q31_t)0x568A34A9, (q31_t)0x5E50015D, (q31_t)0x566524AA, + (q31_t)0x5E71F606, (q31_t)0x56400757, (q31_t)0x5E93DC1F, + (q31_t)0x561ADCB8, (q31_t)0x5EB5B3A1, (q31_t)0x55F5A4D2, + (q31_t)0x5ED77C89, (q31_t)0x55D05FAA, (q31_t)0x5EF936D1, + (q31_t)0x55AB0D46, (q31_t)0x5F1AE273, (q31_t)0x5585ADAC, + (q31_t)0x5F3C7F6B, (q31_t)0x556040E2, (q31_t)0x5F5E0DB3, + (q31_t)0x553AC6ED, (q31_t)0x5F7F8D46, (q31_t)0x55153FD4, + (q31_t)0x5FA0FE1E, (q31_t)0x54EFAB9C, (q31_t)0x5FC26038, + (q31_t)0x54CA0A4A, (q31_t)0x5FE3B38D, (q31_t)0x54A45BE5, + (q31_t)0x6004F818, (q31_t)0x547EA073, (q31_t)0x60262DD5, + (q31_t)0x5458D7F9, (q31_t)0x604754BE, (q31_t)0x5433027D, + (q31_t)0x60686CCE, (q31_t)0x540D2005, (q31_t)0x60897600, + (q31_t)0x53E73097, (q31_t)0x60AA704F, (q31_t)0x53C13438, + (q31_t)0x60CB5BB6, (q31_t)0x539B2AEF, (q31_t)0x60EC3830, + (q31_t)0x537514C1, (q31_t)0x610D05B7, (q31_t)0x534EF1B5, + (q31_t)0x612DC446, (q31_t)0x5328C1D0, (q31_t)0x614E73D9, + (q31_t)0x53028517, (q31_t)0x616F146B, (q31_t)0x52DC3B92, + (q31_t)0x618FA5F6, (q31_t)0x52B5E545, (q31_t)0x61B02876, + (q31_t)0x528F8237, (q31_t)0x61D09BE5, (q31_t)0x5269126E, + (q31_t)0x61F1003E, (q31_t)0x524295EF, (q31_t)0x6211557D, + (q31_t)0x521C0CC1, (q31_t)0x62319B9D, (q31_t)0x51F576E9, + (q31_t)0x6251D297, (q31_t)0x51CED46E, (q31_t)0x6271FA69, + (q31_t)0x51A82555, (q31_t)0x6292130C, (q31_t)0x518169A4, + (q31_t)0x62B21C7B, (q31_t)0x515AA162, (q31_t)0x62D216B2, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x510CEB40, + (q31_t)0x6311DD63, (q31_t)0x50E5FD6C, (q31_t)0x6331A9D4, + (q31_t)0x50BF031F, (q31_t)0x635166F8, (q31_t)0x5097FC5E, + (q31_t)0x637114CC, (q31_t)0x5070E92F, (q31_t)0x6390B34A, + (q31_t)0x5049C999, (q31_t)0x63B0426D, (q31_t)0x50229DA0, + (q31_t)0x63CFC230, (q31_t)0x4FFB654D, (q31_t)0x63EF328F, + (q31_t)0x4FD420A3, (q31_t)0x640E9385, (q31_t)0x4FACCFAB, + (q31_t)0x642DE50D, (q31_t)0x4F857268, (q31_t)0x644D2722, + (q31_t)0x4F5E08E3, (q31_t)0x646C59BF, (q31_t)0x4F369320, + (q31_t)0x648B7CDF, (q31_t)0x4F0F1126, (q31_t)0x64AA907F, + (q31_t)0x4EE782FA, (q31_t)0x64C99498, (q31_t)0x4EBFE8A4, + (q31_t)0x64E88926, (q31_t)0x4E984229, (q31_t)0x65076E24, + (q31_t)0x4E708F8F, (q31_t)0x6526438E, (q31_t)0x4E48D0DC, + (q31_t)0x6545095F, (q31_t)0x4E210617, (q31_t)0x6563BF92, + (q31_t)0x4DF92F45, (q31_t)0x65826622, (q31_t)0x4DD14C6E, + (q31_t)0x65A0FD0B, (q31_t)0x4DA95D96, (q31_t)0x65BF8447, + (q31_t)0x4D8162C4, (q31_t)0x65DDFBD3, (q31_t)0x4D595BFE, + (q31_t)0x65FC63A9, (q31_t)0x4D31494B, (q31_t)0x661ABBC5, + (q31_t)0x4D092AB0, (q31_t)0x66390422, (q31_t)0x4CE10034, + (q31_t)0x66573CBB, (q31_t)0x4CB8C9DD, (q31_t)0x6675658C, + (q31_t)0x4C9087B1, (q31_t)0x66937E90, (q31_t)0x4C6839B6, + (q31_t)0x66B187C3, (q31_t)0x4C3FDFF3, (q31_t)0x66CF811F, + (q31_t)0x4C177A6E, (q31_t)0x66ED6AA1, (q31_t)0x4BEF092D, + (q31_t)0x670B4443, (q31_t)0x4BC68C36, (q31_t)0x67290E02, + (q31_t)0x4B9E038F, (q31_t)0x6746C7D7, (q31_t)0x4B756F3F, + (q31_t)0x676471C0, (q31_t)0x4B4CCF4D, (q31_t)0x67820BB6, + (q31_t)0x4B2423BD, (q31_t)0x679F95B7, (q31_t)0x4AFB6C97, + (q31_t)0x67BD0FBC, (q31_t)0x4AD2A9E1, (q31_t)0x67DA79C2, + (q31_t)0x4AA9DBA1, (q31_t)0x67F7D3C4, (q31_t)0x4A8101DE, + (q31_t)0x68151DBE, (q31_t)0x4A581C9D, (q31_t)0x683257AA, + (q31_t)0x4A2F2BE5, (q31_t)0x684F8186, (q31_t)0x4A062FBD, + (q31_t)0x686C9B4B, (q31_t)0x49DD282A, (q31_t)0x6889A4F5, + (q31_t)0x49B41533, (q31_t)0x68A69E81, (q31_t)0x498AF6DE, + (q31_t)0x68C387E9, (q31_t)0x4961CD32, (q31_t)0x68E06129, + (q31_t)0x49389836, (q31_t)0x68FD2A3D, (q31_t)0x490F57EE, + (q31_t)0x6919E320, (q31_t)0x48E60C62, (q31_t)0x69368BCE, + (q31_t)0x48BCB598, (q31_t)0x69532442, (q31_t)0x48935397, + (q31_t)0x696FAC78, (q31_t)0x4869E664, (q31_t)0x698C246C, + (q31_t)0x48406E07, (q31_t)0x69A88C18, (q31_t)0x4816EA85, + (q31_t)0x69C4E37A, (q31_t)0x47ED5BE6, (q31_t)0x69E12A8C, + (q31_t)0x47C3C22E, (q31_t)0x69FD614A, (q31_t)0x479A1D66, + (q31_t)0x6A1987B0, (q31_t)0x47706D93, (q31_t)0x6A359DB9, + (q31_t)0x4746B2BC, (q31_t)0x6A51A361, (q31_t)0x471CECE6, + (q31_t)0x6A6D98A4, (q31_t)0x46F31C1A, (q31_t)0x6A897D7D, + (q31_t)0x46C9405C, (q31_t)0x6AA551E8, (q31_t)0x469F59B4, + (q31_t)0x6AC115E1, (q31_t)0x46756827, (q31_t)0x6ADCC964, + (q31_t)0x464B6BBD, (q31_t)0x6AF86C6C, (q31_t)0x4621647C, + (q31_t)0x6B13FEF5, (q31_t)0x45F7526B, (q31_t)0x6B2F80FA, + (q31_t)0x45CD358F, (q31_t)0x6B4AF278, (q31_t)0x45A30DF0, + (q31_t)0x6B66536A, (q31_t)0x4578DB93, (q31_t)0x6B81A3CD, + (q31_t)0x454E9E80, (q31_t)0x6B9CE39B, (q31_t)0x452456BC, + (q31_t)0x6BB812D0, (q31_t)0x44FA044F, (q31_t)0x6BD3316A, + (q31_t)0x44CFA73F, (q31_t)0x6BEE3F62, (q31_t)0x44A53F93, + (q31_t)0x6C093CB6, (q31_t)0x447ACD50, (q31_t)0x6C242960, + (q31_t)0x4450507E, (q31_t)0x6C3F055D, (q31_t)0x4425C923, + (q31_t)0x6C59D0A9, (q31_t)0x43FB3745, (q31_t)0x6C748B3F, + (q31_t)0x43D09AEC, (q31_t)0x6C8F351C, (q31_t)0x43A5F41E, + (q31_t)0x6CA9CE3A, (q31_t)0x437B42E1, (q31_t)0x6CC45697, + (q31_t)0x4350873C, (q31_t)0x6CDECE2E, (q31_t)0x4325C135, + (q31_t)0x6CF934FB, (q31_t)0x42FAF0D4, (q31_t)0x6D138AFA, + (q31_t)0x42D0161E, (q31_t)0x6D2DD027, (q31_t)0x42A5311A, + (q31_t)0x6D48047E, (q31_t)0x427A41D0, (q31_t)0x6D6227FA, + (q31_t)0x424F4845, (q31_t)0x6D7C3A98, (q31_t)0x42244480, + (q31_t)0x6D963C54, (q31_t)0x41F93688, (q31_t)0x6DB02D29, + (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x41A2FC1A, + (q31_t)0x6DE3DC11, (q31_t)0x4177CFB0, (q31_t)0x6DFD9A1B, + (q31_t)0x414C992E, (q31_t)0x6E17472F, (q31_t)0x4121589A, + (q31_t)0x6E30E349, (q31_t)0x40F60DFB, (q31_t)0x6E4A6E65, + (q31_t)0x40CAB957, (q31_t)0x6E63E87F, (q31_t)0x409F5AB6, + (q31_t)0x6E7D5193, (q31_t)0x4073F21D, (q31_t)0x6E96A99C, + (q31_t)0x40487F93, (q31_t)0x6EAFF098, (q31_t)0x401D0320, + (q31_t)0x6EC92682, (q31_t)0x3FF17CCA, (q31_t)0x6EE24B57, + (q31_t)0x3FC5EC97, (q31_t)0x6EFB5F12, (q31_t)0x3F9A528F, + (q31_t)0x6F1461AF, (q31_t)0x3F6EAEB8, (q31_t)0x6F2D532C, + (q31_t)0x3F430118, (q31_t)0x6F463383, (q31_t)0x3F1749B7, + (q31_t)0x6F5F02B1, (q31_t)0x3EEB889C, (q31_t)0x6F77C0B3, + (q31_t)0x3EBFBDCC, (q31_t)0x6F906D84, (q31_t)0x3E93E94F, + (q31_t)0x6FA90920, (q31_t)0x3E680B2C, (q31_t)0x6FC19385, + (q31_t)0x3E3C2369, (q31_t)0x6FDA0CAD, (q31_t)0x3E10320D, + (q31_t)0x6FF27496, (q31_t)0x3DE4371F, (q31_t)0x700ACB3B, + (q31_t)0x3DB832A5, (q31_t)0x70231099, (q31_t)0x3D8C24A7, + (q31_t)0x703B44AC, (q31_t)0x3D600D2B, (q31_t)0x70536771, + (q31_t)0x3D33EC39, (q31_t)0x706B78E3, (q31_t)0x3D07C1D5, + (q31_t)0x708378FE, (q31_t)0x3CDB8E09, (q31_t)0x709B67C0, + (q31_t)0x3CAF50DA, (q31_t)0x70B34524, (q31_t)0x3C830A4F, + (q31_t)0x70CB1127, (q31_t)0x3C56BA70, (q31_t)0x70E2CBC6, + (q31_t)0x3C2A6142, (q31_t)0x70FA74FB, (q31_t)0x3BFDFECD, + (q31_t)0x71120CC5, (q31_t)0x3BD19317, (q31_t)0x7129931E, + (q31_t)0x3BA51E29, (q31_t)0x71410804, (q31_t)0x3B78A007, + (q31_t)0x71586B73, (q31_t)0x3B4C18BA, (q31_t)0x716FBD68, + (q31_t)0x3B1F8847, (q31_t)0x7186FDDE, (q31_t)0x3AF2EEB7, + (q31_t)0x719E2CD2, (q31_t)0x3AC64C0F, (q31_t)0x71B54A40, + (q31_t)0x3A99A057, (q31_t)0x71CC5626, (q31_t)0x3A6CEB95, + (q31_t)0x71E3507F, (q31_t)0x3A402DD1, (q31_t)0x71FA3948, + (q31_t)0x3A136712, (q31_t)0x7211107D, (q31_t)0x39E6975D, + (q31_t)0x7227D61C, (q31_t)0x39B9BEBB, (q31_t)0x723E8A1F, + (q31_t)0x398CDD32, (q31_t)0x72552C84, (q31_t)0x395FF2C9, + (q31_t)0x726BBD48, (q31_t)0x3932FF87, (q31_t)0x72823C66, + (q31_t)0x39060372, (q31_t)0x7298A9DC, (q31_t)0x38D8FE93, + (q31_t)0x72AF05A6, (q31_t)0x38ABF0EF, (q31_t)0x72C54FC0, + (q31_t)0x387EDA8E, (q31_t)0x72DB8828, (q31_t)0x3851BB76, + (q31_t)0x72F1AED8, (q31_t)0x382493B0, (q31_t)0x7307C3D0, + (q31_t)0x37F76340, (q31_t)0x731DC709, (q31_t)0x37CA2A30, + (q31_t)0x7333B883, (q31_t)0x379CE884, (q31_t)0x73499838, + (q31_t)0x376F9E46, (q31_t)0x735F6626, (q31_t)0x37424B7A, + (q31_t)0x73752249, (q31_t)0x3714F02A, (q31_t)0x738ACC9E, + (q31_t)0x36E78C5A, (q31_t)0x73A06522, (q31_t)0x36BA2013, + (q31_t)0x73B5EBD0, (q31_t)0x368CAB5C, (q31_t)0x73CB60A7, + (q31_t)0x365F2E3B, (q31_t)0x73E0C3A3, (q31_t)0x3631A8B7, + (q31_t)0x73F614C0, (q31_t)0x36041AD9, (q31_t)0x740B53FA, + (q31_t)0x35D684A5, (q31_t)0x74208150, (q31_t)0x35A8E624, + (q31_t)0x74359CBD, (q31_t)0x357B3F5D, (q31_t)0x744AA63E, + (q31_t)0x354D9056, (q31_t)0x745F9DD1, (q31_t)0x351FD917, + (q31_t)0x74748371, (q31_t)0x34F219A7, (q31_t)0x7489571B, + (q31_t)0x34C4520D, (q31_t)0x749E18CD, (q31_t)0x3496824F, + (q31_t)0x74B2C883, (q31_t)0x3468AA76, (q31_t)0x74C7663A, + (q31_t)0x343ACA87, (q31_t)0x74DBF1EF, (q31_t)0x340CE28A, + (q31_t)0x74F06B9E, (q31_t)0x33DEF287, (q31_t)0x7504D345, + (q31_t)0x33B0FA84, (q31_t)0x751928E0, (q31_t)0x3382FA88, + (q31_t)0x752D6C6C, (q31_t)0x3354F29A, (q31_t)0x75419DE6, + (q31_t)0x3326E2C2, (q31_t)0x7555BD4B, (q31_t)0x32F8CB07, + (q31_t)0x7569CA98, (q31_t)0x32CAAB6F, (q31_t)0x757DC5CA, + (q31_t)0x329C8402, (q31_t)0x7591AEDD, (q31_t)0x326E54C7, + (q31_t)0x75A585CF, (q31_t)0x32401DC5, (q31_t)0x75B94A9C, + (q31_t)0x3211DF03, (q31_t)0x75CCFD42, (q31_t)0x31E39889, + (q31_t)0x75E09DBD, (q31_t)0x31B54A5D, (q31_t)0x75F42C0A, + (q31_t)0x3186F487, (q31_t)0x7607A827, (q31_t)0x3158970D, + (q31_t)0x761B1211, (q31_t)0x312A31F8, (q31_t)0x762E69C3, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x30CD5114, + (q31_t)0x7654E279, (q31_t)0x309ED555, (q31_t)0x76680376, + (q31_t)0x30705217, (q31_t)0x767B1230, (q31_t)0x3041C760, + (q31_t)0x768E0EA5, (q31_t)0x30133538, (q31_t)0x76A0F8D2, + (q31_t)0x2FE49BA6, (q31_t)0x76B3D0B3, (q31_t)0x2FB5FAB2, + (q31_t)0x76C69646, (q31_t)0x2F875262, (q31_t)0x76D94988, + (q31_t)0x2F58A2BD, (q31_t)0x76EBEA77, (q31_t)0x2F29EBCC, + (q31_t)0x76FE790E, (q31_t)0x2EFB2D94, (q31_t)0x7710F54B, + (q31_t)0x2ECC681E, (q31_t)0x77235F2D, (q31_t)0x2E9D9B70, + (q31_t)0x7735B6AE, (q31_t)0x2E6EC792, (q31_t)0x7747FBCE, + (q31_t)0x2E3FEC8B, (q31_t)0x775A2E88, (q31_t)0x2E110A62, + (q31_t)0x776C4EDB, (q31_t)0x2DE2211E, (q31_t)0x777E5CC3, + (q31_t)0x2DB330C7, (q31_t)0x7790583D, (q31_t)0x2D843963, + (q31_t)0x77A24148, (q31_t)0x2D553AFB, (q31_t)0x77B417DF, + (q31_t)0x2D263595, (q31_t)0x77C5DC01, (q31_t)0x2CF72939, + (q31_t)0x77D78DAA, (q31_t)0x2CC815ED, (q31_t)0x77E92CD8, + (q31_t)0x2C98FBBA, (q31_t)0x77FAB988, (q31_t)0x2C69DAA6, + (q31_t)0x780C33B8, (q31_t)0x2C3AB2B9, (q31_t)0x781D9B64, + (q31_t)0x2C0B83F9, (q31_t)0x782EF08B, (q31_t)0x2BDC4E6F, + (q31_t)0x78403328, (q31_t)0x2BAD1221, (q31_t)0x7851633B, + (q31_t)0x2B7DCF17, (q31_t)0x786280BF, (q31_t)0x2B4E8558, + (q31_t)0x78738BB3, (q31_t)0x2B1F34EB, (q31_t)0x78848413, + (q31_t)0x2AEFDDD8, (q31_t)0x789569DE, (q31_t)0x2AC08025, + (q31_t)0x78A63D10, (q31_t)0x2A911BDB, (q31_t)0x78B6FDA8, + (q31_t)0x2A61B101, (q31_t)0x78C7ABA1, (q31_t)0x2A323F9D, + (q31_t)0x78D846FB, (q31_t)0x2A02C7B8, (q31_t)0x78E8CFB1, + (q31_t)0x29D34958, (q31_t)0x78F945C3, (q31_t)0x29A3C484, + (q31_t)0x7909A92C, (q31_t)0x29743945, (q31_t)0x7919F9EB, + (q31_t)0x2944A7A2, (q31_t)0x792A37FE, (q31_t)0x29150FA1, + (q31_t)0x793A6360, (q31_t)0x28E5714A, (q31_t)0x794A7C11, + (q31_t)0x28B5CCA5, (q31_t)0x795A820E, (q31_t)0x288621B9, + (q31_t)0x796A7554, (q31_t)0x2856708C, (q31_t)0x797A55E0, + (q31_t)0x2826B928, (q31_t)0x798A23B1, (q31_t)0x27F6FB92, + (q31_t)0x7999DEC3, (q31_t)0x27C737D2, (q31_t)0x79A98715, + (q31_t)0x27976DF1, (q31_t)0x79B91CA4, (q31_t)0x27679DF4, + (q31_t)0x79C89F6D, (q31_t)0x2737C7E3, (q31_t)0x79D80F6F, + (q31_t)0x2707EBC6, (q31_t)0x79E76CA6, (q31_t)0x26D809A5, + (q31_t)0x79F6B711, (q31_t)0x26A82185, (q31_t)0x7A05EEAD, + (q31_t)0x26783370, (q31_t)0x7A151377, (q31_t)0x26483F6C, + (q31_t)0x7A24256E, (q31_t)0x26184581, (q31_t)0x7A33248F, + (q31_t)0x25E845B5, (q31_t)0x7A4210D8, (q31_t)0x25B84012, + (q31_t)0x7A50EA46, (q31_t)0x2588349D, (q31_t)0x7A5FB0D8, + (q31_t)0x2558235E, (q31_t)0x7A6E648A, (q31_t)0x25280C5D, + (q31_t)0x7A7D055B, (q31_t)0x24F7EFA1, (q31_t)0x7A8B9348, + (q31_t)0x24C7CD32, (q31_t)0x7A9A0E4F, (q31_t)0x2497A517, + (q31_t)0x7AA8766E, (q31_t)0x24677757, (q31_t)0x7AB6CBA3, + (q31_t)0x243743FA, (q31_t)0x7AC50DEB, (q31_t)0x24070B07, + (q31_t)0x7AD33D45, (q31_t)0x23D6CC86, (q31_t)0x7AE159AE, + (q31_t)0x23A6887E, (q31_t)0x7AEF6323, (q31_t)0x23763EF7, + (q31_t)0x7AFD59A3, (q31_t)0x2345EFF7, (q31_t)0x7B0B3D2C, + (q31_t)0x23159B87, (q31_t)0x7B190DBB, (q31_t)0x22E541AE, + (q31_t)0x7B26CB4F, (q31_t)0x22B4E274, (q31_t)0x7B3475E4, + (q31_t)0x22847DDF, (q31_t)0x7B420D7A, (q31_t)0x225413F8, + (q31_t)0x7B4F920E, (q31_t)0x2223A4C5, (q31_t)0x7B5D039D, + (q31_t)0x21F3304E, (q31_t)0x7B6A6227, (q31_t)0x21C2B69C, + (q31_t)0x7B77ADA8, (q31_t)0x219237B4, (q31_t)0x7B84E61E, + (q31_t)0x2161B39F, (q31_t)0x7B920B89, (q31_t)0x21312A65, + (q31_t)0x7B9F1DE5, (q31_t)0x21009C0B, (q31_t)0x7BAC1D31, + (q31_t)0x20D0089B, (q31_t)0x7BB9096A, (q31_t)0x209F701C, + (q31_t)0x7BC5E28F, (q31_t)0x206ED295, (q31_t)0x7BD2A89E, + (q31_t)0x203E300D, (q31_t)0x7BDF5B94, (q31_t)0x200D888C, + (q31_t)0x7BEBFB70, (q31_t)0x1FDCDC1A, (q31_t)0x7BF88830, + (q31_t)0x1FAC2ABF, (q31_t)0x7C0501D1, (q31_t)0x1F7B7480, + (q31_t)0x7C116853, (q31_t)0x1F4AB967, (q31_t)0x7C1DBBB2, + (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x1EE934C2, + (q31_t)0x7C362904, (q31_t)0x1EB86B46, (q31_t)0x7C4242F2, + (q31_t)0x1E879D0C, (q31_t)0x7C4E49B6, (q31_t)0x1E56CA1E, + (q31_t)0x7C5A3D4F, (q31_t)0x1E25F281, (q31_t)0x7C661DBB, + (q31_t)0x1DF5163F, (q31_t)0x7C71EAF8, (q31_t)0x1DC4355D, + (q31_t)0x7C7DA504, (q31_t)0x1D934FE5, (q31_t)0x7C894BDD, + (q31_t)0x1D6265DD, (q31_t)0x7C94DF82, (q31_t)0x1D31774D, + (q31_t)0x7CA05FF1, (q31_t)0x1D00843C, (q31_t)0x7CABCD27, + (q31_t)0x1CCF8CB3, (q31_t)0x7CB72724, (q31_t)0x1C9E90B8, + (q31_t)0x7CC26DE5, (q31_t)0x1C6D9053, (q31_t)0x7CCDA168, + (q31_t)0x1C3C8B8C, (q31_t)0x7CD8C1AD, (q31_t)0x1C0B826A, + (q31_t)0x7CE3CEB1, (q31_t)0x1BDA74F5, (q31_t)0x7CEEC873, + (q31_t)0x1BA96334, (q31_t)0x7CF9AEF0, (q31_t)0x1B784D30, + (q31_t)0x7D048228, (q31_t)0x1B4732EF, (q31_t)0x7D0F4218, + (q31_t)0x1B161479, (q31_t)0x7D19EEBE, (q31_t)0x1AE4F1D6, + (q31_t)0x7D24881A, (q31_t)0x1AB3CB0C, (q31_t)0x7D2F0E2A, + (q31_t)0x1A82A025, (q31_t)0x7D3980EC, (q31_t)0x1A517127, + (q31_t)0x7D43E05E, (q31_t)0x1A203E1B, (q31_t)0x7D4E2C7E, + (q31_t)0x19EF0706, (q31_t)0x7D58654C, (q31_t)0x19BDCBF2, + (q31_t)0x7D628AC5, (q31_t)0x198C8CE6, (q31_t)0x7D6C9CE9, + (q31_t)0x195B49E9, (q31_t)0x7D769BB5, (q31_t)0x192A0303, + (q31_t)0x7D808727, (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x18C7699B, (q31_t)0x7D9423FB, (q31_t)0x18961727, + (q31_t)0x7D9DD55A, (q31_t)0x1864C0E9, (q31_t)0x7DA77359, + (q31_t)0x183366E8, (q31_t)0x7DB0FDF7, (q31_t)0x1802092C, + (q31_t)0x7DBA7534, (q31_t)0x17D0A7BB, (q31_t)0x7DC3D90D, + (q31_t)0x179F429F, (q31_t)0x7DCD2981, (q31_t)0x176DD9DE, + (q31_t)0x7DD6668E, (q31_t)0x173C6D80, (q31_t)0x7DDF9034, + (q31_t)0x170AFD8D, (q31_t)0x7DE8A670, (q31_t)0x16D98A0C, + (q31_t)0x7DF1A942, (q31_t)0x16A81305, (q31_t)0x7DFA98A7, + (q31_t)0x1676987F, (q31_t)0x7E03749F, (q31_t)0x16451A83, + (q31_t)0x7E0C3D29, (q31_t)0x16139917, (q31_t)0x7E14F242, + (q31_t)0x15E21444, (q31_t)0x7E1D93E9, (q31_t)0x15B08C11, + (q31_t)0x7E26221E, (q31_t)0x157F0086, (q31_t)0x7E2E9CDF, + (q31_t)0x154D71AA, (q31_t)0x7E37042A, (q31_t)0x151BDF85, + (q31_t)0x7E3F57FE, (q31_t)0x14EA4A1F, (q31_t)0x7E47985B, + (q31_t)0x14B8B17F, (q31_t)0x7E4FC53E, (q31_t)0x148715AD, + (q31_t)0x7E57DEA6, (q31_t)0x145576B1, (q31_t)0x7E5FE493, + (q31_t)0x1423D492, (q31_t)0x7E67D702, (q31_t)0x13F22F57, + (q31_t)0x7E6FB5F3, (q31_t)0x13C0870A, (q31_t)0x7E778165, + (q31_t)0x138EDBB0, (q31_t)0x7E7F3956, (q31_t)0x135D2D53, + (q31_t)0x7E86DDC5, (q31_t)0x132B7BF9, (q31_t)0x7E8E6EB1, + (q31_t)0x12F9C7AA, (q31_t)0x7E95EC19, (q31_t)0x12C8106E, + (q31_t)0x7E9D55FC, (q31_t)0x1296564D, (q31_t)0x7EA4AC58, + (q31_t)0x1264994E, (q31_t)0x7EABEF2C, (q31_t)0x1232D978, + (q31_t)0x7EB31E77, (q31_t)0x120116D4, (q31_t)0x7EBA3A39, + (q31_t)0x11CF516A, (q31_t)0x7EC1426F, (q31_t)0x119D8940, + (q31_t)0x7EC8371A, (q31_t)0x116BBE5F, (q31_t)0x7ECF1837, + (q31_t)0x1139F0CE, (q31_t)0x7ED5E5C6, (q31_t)0x11082096, + (q31_t)0x7EDC9FC6, (q31_t)0x10D64DBC, (q31_t)0x7EE34635, + (q31_t)0x10A4784A, (q31_t)0x7EE9D913, (q31_t)0x1072A047, + (q31_t)0x7EF0585F, (q31_t)0x1040C5BB, (q31_t)0x7EF6C418, + (q31_t)0x100EE8AD, (q31_t)0x7EFD1C3C, (q31_t)0x0FDD0925, + (q31_t)0x7F0360CB, (q31_t)0x0FAB272B, (q31_t)0x7F0991C3, + (q31_t)0x0F7942C6, (q31_t)0x7F0FAF24, (q31_t)0x0F475BFE, + (q31_t)0x7F15B8EE, (q31_t)0x0F1572DC, (q31_t)0x7F1BAF1E, + (q31_t)0x0EE38765, (q31_t)0x7F2191B4, (q31_t)0x0EB199A3, + (q31_t)0x7F2760AF, (q31_t)0x0E7FA99D, (q31_t)0x7F2D1C0E, + (q31_t)0x0E4DB75B, (q31_t)0x7F32C3D0, (q31_t)0x0E1BC2E3, + (q31_t)0x7F3857F5, (q31_t)0x0DE9CC3F, (q31_t)0x7F3DD87C, + (q31_t)0x0DB7D376, (q31_t)0x7F434563, (q31_t)0x0D85D88F, + (q31_t)0x7F489EAA, (q31_t)0x0D53DB92, (q31_t)0x7F4DE450, + (q31_t)0x0D21DC87, (q31_t)0x7F531654, (q31_t)0x0CEFDB75, + (q31_t)0x7F5834B6, (q31_t)0x0CBDD865, (q31_t)0x7F5D3F75, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x0C59CC67, + (q31_t)0x7F671A04, (q31_t)0x0C27C389, (q31_t)0x7F6BE9D4, + (q31_t)0x0BF5B8CB, (q31_t)0x7F70A5FD, (q31_t)0x0BC3AC35, + (q31_t)0x7F754E7F, (q31_t)0x0B919DCE, (q31_t)0x7F79E35A, + (q31_t)0x0B5F8D9F, (q31_t)0x7F7E648B, (q31_t)0x0B2D7BAE, + (q31_t)0x7F82D214, (q31_t)0x0AFB6805, (q31_t)0x7F872BF3, + (q31_t)0x0AC952AA, (q31_t)0x7F8B7226, (q31_t)0x0A973BA5, + (q31_t)0x7F8FA4AF, (q31_t)0x0A6522FE, (q31_t)0x7F93C38C, + (q31_t)0x0A3308BC, (q31_t)0x7F97CEBC, (q31_t)0x0A00ECE8, + (q31_t)0x7F9BC63F, (q31_t)0x09CECF89, (q31_t)0x7F9FAA15, + (q31_t)0x099CB0A7, (q31_t)0x7FA37A3C, (q31_t)0x096A9049, + (q31_t)0x7FA736B4, (q31_t)0x09386E77, (q31_t)0x7FAADF7C, + (q31_t)0x09064B3A, (q31_t)0x7FAE7494, (q31_t)0x08D42698, + (q31_t)0x7FB1F5FC, (q31_t)0x08A2009A, (q31_t)0x7FB563B2, + (q31_t)0x086FD947, (q31_t)0x7FB8BDB7, (q31_t)0x083DB0A7, + (q31_t)0x7FBC040A, (q31_t)0x080B86C1, (q31_t)0x7FBF36A9, + (q31_t)0x07D95B9E, (q31_t)0x7FC25596, (q31_t)0x07A72F45, + (q31_t)0x7FC560CF, (q31_t)0x077501BE, (q31_t)0x7FC85853, + (q31_t)0x0742D310, (q31_t)0x7FCB3C23, (q31_t)0x0710A344, + (q31_t)0x7FCE0C3E, (q31_t)0x06DE7261, (q31_t)0x7FD0C8A3, + (q31_t)0x06AC406F, (q31_t)0x7FD37152, (q31_t)0x067A0D75, + (q31_t)0x7FD6064B, (q31_t)0x0647D97C, (q31_t)0x7FD8878D, + (q31_t)0x0615A48A, (q31_t)0x7FDAF518, (q31_t)0x05E36EA9, + (q31_t)0x7FDD4EEC, (q31_t)0x05B137DF, (q31_t)0x7FDF9508, + (q31_t)0x057F0034, (q31_t)0x7FE1C76B, (q31_t)0x054CC7B0, + (q31_t)0x7FE3E616, (q31_t)0x051A8E5C, (q31_t)0x7FE5F108, + (q31_t)0x04E8543D, (q31_t)0x7FE7E840, (q31_t)0x04B6195D, + (q31_t)0x7FE9CBC0, (q31_t)0x0483DDC3, (q31_t)0x7FEB9B85, + (q31_t)0x0451A176, (q31_t)0x7FED5790, (q31_t)0x041F647F, + (q31_t)0x7FEEFFE1, (q31_t)0x03ED26E6, (q31_t)0x7FF09477, + (q31_t)0x03BAE8B1, (q31_t)0x7FF21553, (q31_t)0x0388A9E9, + (q31_t)0x7FF38273, (q31_t)0x03566A96, (q31_t)0x7FF4DBD8, + (q31_t)0x03242ABF, (q31_t)0x7FF62182, (q31_t)0x02F1EA6B, + (q31_t)0x7FF7536F, (q31_t)0x02BFA9A4, (q31_t)0x7FF871A1, + (q31_t)0x028D6870, (q31_t)0x7FF97C17, (q31_t)0x025B26D7, + (q31_t)0x7FFA72D1, (q31_t)0x0228E4E1, (q31_t)0x7FFB55CE, + (q31_t)0x01F6A296, (q31_t)0x7FFC250F, (q31_t)0x01C45FFE, + (q31_t)0x7FFCE093, (q31_t)0x01921D1F, (q31_t)0x7FFD885A, + (q31_t)0x015FDA03, (q31_t)0x7FFE1C64, (q31_t)0x012D96B0, + (q31_t)0x7FFE9CB2, (q31_t)0x00FB532F, (q31_t)0x7FFF0942, + (q31_t)0x00C90F88, (q31_t)0x7FFF6216, (q31_t)0x0096CBC1, + (q31_t)0x7FFFA72C, (q31_t)0x006487E3, (q31_t)0x7FFFD885, + (q31_t)0x003243F5, (q31_t)0x7FFFF621, (q31_t)0x00000000, + (q31_t)0x7FFFFFFF, (q31_t)0xFFCDBC0A, (q31_t)0x7FFFF621, + (q31_t)0xFF9B781D, (q31_t)0x7FFFD885, (q31_t)0xFF69343E, + (q31_t)0x7FFFA72C, (q31_t)0xFF36F078, (q31_t)0x7FFF6216, + (q31_t)0xFF04ACD0, (q31_t)0x7FFF0942, (q31_t)0xFED2694F, + (q31_t)0x7FFE9CB2, (q31_t)0xFEA025FC, (q31_t)0x7FFE1C64, + (q31_t)0xFE6DE2E0, (q31_t)0x7FFD885A, (q31_t)0xFE3BA001, + (q31_t)0x7FFCE093, (q31_t)0xFE095D69, (q31_t)0x7FFC250F, + (q31_t)0xFDD71B1E, (q31_t)0x7FFB55CE, (q31_t)0xFDA4D928, + (q31_t)0x7FFA72D1, (q31_t)0xFD72978F, (q31_t)0x7FF97C17, + (q31_t)0xFD40565B, (q31_t)0x7FF871A1, (q31_t)0xFD0E1594, + (q31_t)0x7FF7536F, (q31_t)0xFCDBD541, (q31_t)0x7FF62182, + (q31_t)0xFCA99569, (q31_t)0x7FF4DBD8, (q31_t)0xFC775616, + (q31_t)0x7FF38273, (q31_t)0xFC45174E, (q31_t)0x7FF21553, + (q31_t)0xFC12D919, (q31_t)0x7FF09477, (q31_t)0xFBE09B80, + (q31_t)0x7FEEFFE1, (q31_t)0xFBAE5E89, (q31_t)0x7FED5790, + (q31_t)0xFB7C223C, (q31_t)0x7FEB9B85, (q31_t)0xFB49E6A2, + (q31_t)0x7FE9CBC0, (q31_t)0xFB17ABC2, (q31_t)0x7FE7E840, + (q31_t)0xFAE571A4, (q31_t)0x7FE5F108, (q31_t)0xFAB3384F, + (q31_t)0x7FE3E616, (q31_t)0xFA80FFCB, (q31_t)0x7FE1C76B, + (q31_t)0xFA4EC820, (q31_t)0x7FDF9508, (q31_t)0xFA1C9156, + (q31_t)0x7FDD4EEC, (q31_t)0xF9EA5B75, (q31_t)0x7FDAF518, + (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF985F28A, + (q31_t)0x7FD6064B, (q31_t)0xF953BF90, (q31_t)0x7FD37152, + (q31_t)0xF9218D9E, (q31_t)0x7FD0C8A3, (q31_t)0xF8EF5CBB, + (q31_t)0x7FCE0C3E, (q31_t)0xF8BD2CEF, (q31_t)0x7FCB3C23, + (q31_t)0xF88AFE41, (q31_t)0x7FC85853, (q31_t)0xF858D0BA, + (q31_t)0x7FC560CF, (q31_t)0xF826A461, (q31_t)0x7FC25596, + (q31_t)0xF7F4793E, (q31_t)0x7FBF36A9, (q31_t)0xF7C24F58, + (q31_t)0x7FBC040A, (q31_t)0xF79026B8, (q31_t)0x7FB8BDB7, + (q31_t)0xF75DFF65, (q31_t)0x7FB563B2, (q31_t)0xF72BD967, + (q31_t)0x7FB1F5FC, (q31_t)0xF6F9B4C5, (q31_t)0x7FAE7494, + (q31_t)0xF6C79188, (q31_t)0x7FAADF7C, (q31_t)0xF6956FB6, + (q31_t)0x7FA736B4, (q31_t)0xF6634F58, (q31_t)0x7FA37A3C, + (q31_t)0xF6313076, (q31_t)0x7F9FAA15, (q31_t)0xF5FF1317, + (q31_t)0x7F9BC63F, (q31_t)0xF5CCF743, (q31_t)0x7F97CEBC, + (q31_t)0xF59ADD01, (q31_t)0x7F93C38C, (q31_t)0xF568C45A, + (q31_t)0x7F8FA4AF, (q31_t)0xF536AD55, (q31_t)0x7F8B7226, + (q31_t)0xF50497FA, (q31_t)0x7F872BF3, (q31_t)0xF4D28451, + (q31_t)0x7F82D214, (q31_t)0xF4A07260, (q31_t)0x7F7E648B, + (q31_t)0xF46E6231, (q31_t)0x7F79E35A, (q31_t)0xF43C53CA, + (q31_t)0x7F754E7F, (q31_t)0xF40A4734, (q31_t)0x7F70A5FD, + (q31_t)0xF3D83C76, (q31_t)0x7F6BE9D4, (q31_t)0xF3A63398, + (q31_t)0x7F671A04, (q31_t)0xF3742CA1, (q31_t)0x7F62368F, + (q31_t)0xF342279A, (q31_t)0x7F5D3F75, (q31_t)0xF310248A, + (q31_t)0x7F5834B6, (q31_t)0xF2DE2378, (q31_t)0x7F531654, + (q31_t)0xF2AC246D, (q31_t)0x7F4DE450, (q31_t)0xF27A2770, + (q31_t)0x7F489EAA, (q31_t)0xF2482C89, (q31_t)0x7F434563, + (q31_t)0xF21633C0, (q31_t)0x7F3DD87C, (q31_t)0xF1E43D1C, + (q31_t)0x7F3857F5, (q31_t)0xF1B248A5, (q31_t)0x7F32C3D0, + (q31_t)0xF1805662, (q31_t)0x7F2D1C0E, (q31_t)0xF14E665C, + (q31_t)0x7F2760AF, (q31_t)0xF11C789A, (q31_t)0x7F2191B4, + (q31_t)0xF0EA8D23, (q31_t)0x7F1BAF1E, (q31_t)0xF0B8A401, + (q31_t)0x7F15B8EE, (q31_t)0xF086BD39, (q31_t)0x7F0FAF24, + (q31_t)0xF054D8D4, (q31_t)0x7F0991C3, (q31_t)0xF022F6DA, + (q31_t)0x7F0360CB, (q31_t)0xEFF11752, (q31_t)0x7EFD1C3C, + (q31_t)0xEFBF3A44, (q31_t)0x7EF6C418, (q31_t)0xEF8D5FB8, + (q31_t)0x7EF0585F, (q31_t)0xEF5B87B5, (q31_t)0x7EE9D913, + (q31_t)0xEF29B243, (q31_t)0x7EE34635, (q31_t)0xEEF7DF6A, + (q31_t)0x7EDC9FC6, (q31_t)0xEEC60F31, (q31_t)0x7ED5E5C6, + (q31_t)0xEE9441A0, (q31_t)0x7ECF1837, (q31_t)0xEE6276BF, + (q31_t)0x7EC8371A, (q31_t)0xEE30AE95, (q31_t)0x7EC1426F, + (q31_t)0xEDFEE92B, (q31_t)0x7EBA3A39, (q31_t)0xEDCD2687, + (q31_t)0x7EB31E77, (q31_t)0xED9B66B2, (q31_t)0x7EABEF2C, + (q31_t)0xED69A9B2, (q31_t)0x7EA4AC58, (q31_t)0xED37EF91, + (q31_t)0x7E9D55FC, (q31_t)0xED063855, (q31_t)0x7E95EC19, + (q31_t)0xECD48406, (q31_t)0x7E8E6EB1, (q31_t)0xECA2D2AC, + (q31_t)0x7E86DDC5, (q31_t)0xEC71244F, (q31_t)0x7E7F3956, + (q31_t)0xEC3F78F5, (q31_t)0x7E778165, (q31_t)0xEC0DD0A8, + (q31_t)0x7E6FB5F3, (q31_t)0xEBDC2B6D, (q31_t)0x7E67D702, + (q31_t)0xEBAA894E, (q31_t)0x7E5FE493, (q31_t)0xEB78EA52, + (q31_t)0x7E57DEA6, (q31_t)0xEB474E80, (q31_t)0x7E4FC53E, + (q31_t)0xEB15B5E0, (q31_t)0x7E47985B, (q31_t)0xEAE4207A, + (q31_t)0x7E3F57FE, (q31_t)0xEAB28E55, (q31_t)0x7E37042A, + (q31_t)0xEA80FF79, (q31_t)0x7E2E9CDF, (q31_t)0xEA4F73EE, + (q31_t)0x7E26221E, (q31_t)0xEA1DEBBB, (q31_t)0x7E1D93E9, + (q31_t)0xE9EC66E8, (q31_t)0x7E14F242, (q31_t)0xE9BAE57C, + (q31_t)0x7E0C3D29, (q31_t)0xE9896780, (q31_t)0x7E03749F, + (q31_t)0xE957ECFB, (q31_t)0x7DFA98A7, (q31_t)0xE92675F4, + (q31_t)0x7DF1A942, (q31_t)0xE8F50273, (q31_t)0x7DE8A670, + (q31_t)0xE8C3927F, (q31_t)0x7DDF9034, (q31_t)0xE8922621, + (q31_t)0x7DD6668E, (q31_t)0xE860BD60, (q31_t)0x7DCD2981, + (q31_t)0xE82F5844, (q31_t)0x7DC3D90D, (q31_t)0xE7FDF6D3, + (q31_t)0x7DBA7534, (q31_t)0xE7CC9917, (q31_t)0x7DB0FDF7, + (q31_t)0xE79B3F16, (q31_t)0x7DA77359, (q31_t)0xE769E8D8, + (q31_t)0x7D9DD55A, (q31_t)0xE7389664, (q31_t)0x7D9423FB, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE6D5FCFC, + (q31_t)0x7D808727, (q31_t)0xE6A4B616, (q31_t)0x7D769BB5, + (q31_t)0xE6737319, (q31_t)0x7D6C9CE9, (q31_t)0xE642340D, + (q31_t)0x7D628AC5, (q31_t)0xE610F8F9, (q31_t)0x7D58654C, + (q31_t)0xE5DFC1E4, (q31_t)0x7D4E2C7E, (q31_t)0xE5AE8ED8, + (q31_t)0x7D43E05E, (q31_t)0xE57D5FDA, (q31_t)0x7D3980EC, + (q31_t)0xE54C34F3, (q31_t)0x7D2F0E2A, (q31_t)0xE51B0E2A, + (q31_t)0x7D24881A, (q31_t)0xE4E9EB86, (q31_t)0x7D19EEBE, + (q31_t)0xE4B8CD10, (q31_t)0x7D0F4218, (q31_t)0xE487B2CF, + (q31_t)0x7D048228, (q31_t)0xE4569CCB, (q31_t)0x7CF9AEF0, + (q31_t)0xE4258B0A, (q31_t)0x7CEEC873, (q31_t)0xE3F47D95, + (q31_t)0x7CE3CEB1, (q31_t)0xE3C37473, (q31_t)0x7CD8C1AD, + (q31_t)0xE3926FAC, (q31_t)0x7CCDA168, (q31_t)0xE3616F47, + (q31_t)0x7CC26DE5, (q31_t)0xE330734C, (q31_t)0x7CB72724, + (q31_t)0xE2FF7BC3, (q31_t)0x7CABCD27, (q31_t)0xE2CE88B2, + (q31_t)0x7CA05FF1, (q31_t)0xE29D9A22, (q31_t)0x7C94DF82, + (q31_t)0xE26CB01A, (q31_t)0x7C894BDD, (q31_t)0xE23BCAA2, + (q31_t)0x7C7DA504, (q31_t)0xE20AE9C1, (q31_t)0x7C71EAF8, + (q31_t)0xE1DA0D7E, (q31_t)0x7C661DBB, (q31_t)0xE1A935E1, + (q31_t)0x7C5A3D4F, (q31_t)0xE17862F3, (q31_t)0x7C4E49B6, + (q31_t)0xE14794B9, (q31_t)0x7C4242F2, (q31_t)0xE116CB3D, + (q31_t)0x7C362904, (q31_t)0xE0E60684, (q31_t)0x7C29FBEE, + (q31_t)0xE0B54698, (q31_t)0x7C1DBBB2, (q31_t)0xE0848B7F, + (q31_t)0x7C116853, (q31_t)0xE053D541, (q31_t)0x7C0501D1, + (q31_t)0xE02323E5, (q31_t)0x7BF88830, (q31_t)0xDFF27773, + (q31_t)0x7BEBFB70, (q31_t)0xDFC1CFF2, (q31_t)0x7BDF5B94, + (q31_t)0xDF912D6A, (q31_t)0x7BD2A89E, (q31_t)0xDF608FE3, + (q31_t)0x7BC5E28F, (q31_t)0xDF2FF764, (q31_t)0x7BB9096A, + (q31_t)0xDEFF63F4, (q31_t)0x7BAC1D31, (q31_t)0xDECED59B, + (q31_t)0x7B9F1DE5, (q31_t)0xDE9E4C60, (q31_t)0x7B920B89, + (q31_t)0xDE6DC84B, (q31_t)0x7B84E61E, (q31_t)0xDE3D4963, + (q31_t)0x7B77ADA8, (q31_t)0xDE0CCFB1, (q31_t)0x7B6A6227, + (q31_t)0xDDDC5B3A, (q31_t)0x7B5D039D, (q31_t)0xDDABEC07, + (q31_t)0x7B4F920E, (q31_t)0xDD7B8220, (q31_t)0x7B420D7A, + (q31_t)0xDD4B1D8B, (q31_t)0x7B3475E4, (q31_t)0xDD1ABE51, + (q31_t)0x7B26CB4F, (q31_t)0xDCEA6478, (q31_t)0x7B190DBB, + (q31_t)0xDCBA1008, (q31_t)0x7B0B3D2C, (q31_t)0xDC89C108, + (q31_t)0x7AFD59A3, (q31_t)0xDC597781, (q31_t)0x7AEF6323, + (q31_t)0xDC293379, (q31_t)0x7AE159AE, (q31_t)0xDBF8F4F8, + (q31_t)0x7AD33D45, (q31_t)0xDBC8BC05, (q31_t)0x7AC50DEB, + (q31_t)0xDB9888A8, (q31_t)0x7AB6CBA3, (q31_t)0xDB685AE8, + (q31_t)0x7AA8766E, (q31_t)0xDB3832CD, (q31_t)0x7A9A0E4F, + (q31_t)0xDB08105E, (q31_t)0x7A8B9348, (q31_t)0xDAD7F3A2, + (q31_t)0x7A7D055B, (q31_t)0xDAA7DCA1, (q31_t)0x7A6E648A, + (q31_t)0xDA77CB62, (q31_t)0x7A5FB0D8, (q31_t)0xDA47BFED, + (q31_t)0x7A50EA46, (q31_t)0xDA17BA4A, (q31_t)0x7A4210D8, + (q31_t)0xD9E7BA7E, (q31_t)0x7A33248F, (q31_t)0xD9B7C093, + (q31_t)0x7A24256E, (q31_t)0xD987CC8F, (q31_t)0x7A151377, + (q31_t)0xD957DE7A, (q31_t)0x7A05EEAD, (q31_t)0xD927F65B, + (q31_t)0x79F6B711, (q31_t)0xD8F81439, (q31_t)0x79E76CA6, + (q31_t)0xD8C8381C, (q31_t)0x79D80F6F, (q31_t)0xD898620C, + (q31_t)0x79C89F6D, (q31_t)0xD868920F, (q31_t)0x79B91CA4, + (q31_t)0xD838C82D, (q31_t)0x79A98715, (q31_t)0xD809046D, + (q31_t)0x7999DEC3, (q31_t)0xD7D946D7, (q31_t)0x798A23B1, + (q31_t)0xD7A98F73, (q31_t)0x797A55E0, (q31_t)0xD779DE46, + (q31_t)0x796A7554, (q31_t)0xD74A335A, (q31_t)0x795A820E, + (q31_t)0xD71A8EB5, (q31_t)0x794A7C11, (q31_t)0xD6EAF05E, + (q31_t)0x793A6360, (q31_t)0xD6BB585D, (q31_t)0x792A37FE, + (q31_t)0xD68BC6BA, (q31_t)0x7919F9EB, (q31_t)0xD65C3B7B, + (q31_t)0x7909A92C, (q31_t)0xD62CB6A7, (q31_t)0x78F945C3, + (q31_t)0xD5FD3847, (q31_t)0x78E8CFB1, (q31_t)0xD5CDC062, + (q31_t)0x78D846FB, (q31_t)0xD59E4EFE, (q31_t)0x78C7ABA1, + (q31_t)0xD56EE424, (q31_t)0x78B6FDA8, (q31_t)0xD53F7FDA, + (q31_t)0x78A63D10, (q31_t)0xD5102227, (q31_t)0x789569DE, + (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xD4B17AA7, + (q31_t)0x78738BB3, (q31_t)0xD48230E8, (q31_t)0x786280BF, + (q31_t)0xD452EDDE, (q31_t)0x7851633B, (q31_t)0xD423B190, + (q31_t)0x78403328, (q31_t)0xD3F47C06, (q31_t)0x782EF08B, + (q31_t)0xD3C54D46, (q31_t)0x781D9B64, (q31_t)0xD3962559, + (q31_t)0x780C33B8, (q31_t)0xD3670445, (q31_t)0x77FAB988, + (q31_t)0xD337EA12, (q31_t)0x77E92CD8, (q31_t)0xD308D6C6, + (q31_t)0x77D78DAA, (q31_t)0xD2D9CA6A, (q31_t)0x77C5DC01, + (q31_t)0xD2AAC504, (q31_t)0x77B417DF, (q31_t)0xD27BC69C, + (q31_t)0x77A24148, (q31_t)0xD24CCF38, (q31_t)0x7790583D, + (q31_t)0xD21DDEE1, (q31_t)0x777E5CC3, (q31_t)0xD1EEF59E, + (q31_t)0x776C4EDB, (q31_t)0xD1C01374, (q31_t)0x775A2E88, + (q31_t)0xD191386D, (q31_t)0x7747FBCE, (q31_t)0xD162648F, + (q31_t)0x7735B6AE, (q31_t)0xD13397E1, (q31_t)0x77235F2D, + (q31_t)0xD104D26B, (q31_t)0x7710F54B, (q31_t)0xD0D61433, + (q31_t)0x76FE790E, (q31_t)0xD0A75D42, (q31_t)0x76EBEA77, + (q31_t)0xD078AD9D, (q31_t)0x76D94988, (q31_t)0xD04A054D, + (q31_t)0x76C69646, (q31_t)0xD01B6459, (q31_t)0x76B3D0B3, + (q31_t)0xCFECCAC7, (q31_t)0x76A0F8D2, (q31_t)0xCFBE389F, + (q31_t)0x768E0EA5, (q31_t)0xCF8FADE8, (q31_t)0x767B1230, + (q31_t)0xCF612AAA, (q31_t)0x76680376, (q31_t)0xCF32AEEB, + (q31_t)0x7654E279, (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xCED5CE08, (q31_t)0x762E69C3, (q31_t)0xCEA768F2, + (q31_t)0x761B1211, (q31_t)0xCE790B78, (q31_t)0x7607A827, + (q31_t)0xCE4AB5A2, (q31_t)0x75F42C0A, (q31_t)0xCE1C6776, + (q31_t)0x75E09DBD, (q31_t)0xCDEE20FC, (q31_t)0x75CCFD42, + (q31_t)0xCDBFE23A, (q31_t)0x75B94A9C, (q31_t)0xCD91AB38, + (q31_t)0x75A585CF, (q31_t)0xCD637BFD, (q31_t)0x7591AEDD, + (q31_t)0xCD355490, (q31_t)0x757DC5CA, (q31_t)0xCD0734F8, + (q31_t)0x7569CA98, (q31_t)0xCCD91D3D, (q31_t)0x7555BD4B, + (q31_t)0xCCAB0D65, (q31_t)0x75419DE6, (q31_t)0xCC7D0577, + (q31_t)0x752D6C6C, (q31_t)0xCC4F057B, (q31_t)0x751928E0, + (q31_t)0xCC210D78, (q31_t)0x7504D345, (q31_t)0xCBF31D75, + (q31_t)0x74F06B9E, (q31_t)0xCBC53578, (q31_t)0x74DBF1EF, + (q31_t)0xCB975589, (q31_t)0x74C7663A, (q31_t)0xCB697DB0, + (q31_t)0x74B2C883, (q31_t)0xCB3BADF2, (q31_t)0x749E18CD, + (q31_t)0xCB0DE658, (q31_t)0x7489571B, (q31_t)0xCAE026E8, + (q31_t)0x74748371, (q31_t)0xCAB26FA9, (q31_t)0x745F9DD1, + (q31_t)0xCA84C0A2, (q31_t)0x744AA63E, (q31_t)0xCA5719DB, + (q31_t)0x74359CBD, (q31_t)0xCA297B5A, (q31_t)0x74208150, + (q31_t)0xC9FBE527, (q31_t)0x740B53FA, (q31_t)0xC9CE5748, + (q31_t)0x73F614C0, (q31_t)0xC9A0D1C4, (q31_t)0x73E0C3A3, + (q31_t)0xC97354A3, (q31_t)0x73CB60A7, (q31_t)0xC945DFEC, + (q31_t)0x73B5EBD0, (q31_t)0xC91873A5, (q31_t)0x73A06522, + (q31_t)0xC8EB0FD6, (q31_t)0x738ACC9E, (q31_t)0xC8BDB485, + (q31_t)0x73752249, (q31_t)0xC89061BA, (q31_t)0x735F6626, + (q31_t)0xC863177B, (q31_t)0x73499838, (q31_t)0xC835D5D0, + (q31_t)0x7333B883, (q31_t)0xC8089CBF, (q31_t)0x731DC709, + (q31_t)0xC7DB6C50, (q31_t)0x7307C3D0, (q31_t)0xC7AE4489, + (q31_t)0x72F1AED8, (q31_t)0xC7812571, (q31_t)0x72DB8828, + (q31_t)0xC7540F10, (q31_t)0x72C54FC0, (q31_t)0xC727016C, + (q31_t)0x72AF05A6, (q31_t)0xC6F9FC8D, (q31_t)0x7298A9DC, + (q31_t)0xC6CD0079, (q31_t)0x72823C66, (q31_t)0xC6A00D36, + (q31_t)0x726BBD48, (q31_t)0xC67322CD, (q31_t)0x72552C84, + (q31_t)0xC6464144, (q31_t)0x723E8A1F, (q31_t)0xC61968A2, + (q31_t)0x7227D61C, (q31_t)0xC5EC98ED, (q31_t)0x7211107D, + (q31_t)0xC5BFD22E, (q31_t)0x71FA3948, (q31_t)0xC593146A, + (q31_t)0x71E3507F, (q31_t)0xC5665FA8, (q31_t)0x71CC5626, + (q31_t)0xC539B3F0, (q31_t)0x71B54A40, (q31_t)0xC50D1148, + (q31_t)0x719E2CD2, (q31_t)0xC4E077B8, (q31_t)0x7186FDDE, + (q31_t)0xC4B3E746, (q31_t)0x716FBD68, (q31_t)0xC4875FF8, + (q31_t)0x71586B73, (q31_t)0xC45AE1D7, (q31_t)0x71410804, + (q31_t)0xC42E6CE8, (q31_t)0x7129931E, (q31_t)0xC4020132, + (q31_t)0x71120CC5, (q31_t)0xC3D59EBD, (q31_t)0x70FA74FB, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xC37CF5B0, + (q31_t)0x70CB1127, (q31_t)0xC350AF25, (q31_t)0x70B34524, + (q31_t)0xC32471F6, (q31_t)0x709B67C0, (q31_t)0xC2F83E2A, + (q31_t)0x708378FE, (q31_t)0xC2CC13C7, (q31_t)0x706B78E3, + (q31_t)0xC29FF2D4, (q31_t)0x70536771, (q31_t)0xC273DB58, + (q31_t)0x703B44AC, (q31_t)0xC247CD5A, (q31_t)0x70231099, + (q31_t)0xC21BC8E0, (q31_t)0x700ACB3B, (q31_t)0xC1EFCDF2, + (q31_t)0x6FF27496, (q31_t)0xC1C3DC96, (q31_t)0x6FDA0CAD, + (q31_t)0xC197F4D3, (q31_t)0x6FC19385, (q31_t)0xC16C16B0, + (q31_t)0x6FA90920, (q31_t)0xC1404233, (q31_t)0x6F906D84, + (q31_t)0xC1147763, (q31_t)0x6F77C0B3, (q31_t)0xC0E8B648, + (q31_t)0x6F5F02B1, (q31_t)0xC0BCFEE7, (q31_t)0x6F463383, + (q31_t)0xC0915147, (q31_t)0x6F2D532C, (q31_t)0xC065AD70, + (q31_t)0x6F1461AF, (q31_t)0xC03A1368, (q31_t)0x6EFB5F12, + (q31_t)0xC00E8335, (q31_t)0x6EE24B57, (q31_t)0xBFE2FCDF, + (q31_t)0x6EC92682, (q31_t)0xBFB7806C, (q31_t)0x6EAFF098, + (q31_t)0xBF8C0DE2, (q31_t)0x6E96A99C, (q31_t)0xBF60A54A, + (q31_t)0x6E7D5193, (q31_t)0xBF3546A8, (q31_t)0x6E63E87F, + (q31_t)0xBF09F204, (q31_t)0x6E4A6E65, (q31_t)0xBEDEA765, + (q31_t)0x6E30E349, (q31_t)0xBEB366D1, (q31_t)0x6E17472F, + (q31_t)0xBE88304F, (q31_t)0x6DFD9A1B, (q31_t)0xBE5D03E5, + (q31_t)0x6DE3DC11, (q31_t)0xBE31E19B, (q31_t)0x6DCA0D14, + (q31_t)0xBE06C977, (q31_t)0x6DB02D29, (q31_t)0xBDDBBB7F, + (q31_t)0x6D963C54, (q31_t)0xBDB0B7BA, (q31_t)0x6D7C3A98, + (q31_t)0xBD85BE2F, (q31_t)0x6D6227FA, (q31_t)0xBD5ACEE5, + (q31_t)0x6D48047E, (q31_t)0xBD2FE9E1, (q31_t)0x6D2DD027, + (q31_t)0xBD050F2C, (q31_t)0x6D138AFA, (q31_t)0xBCDA3ECA, + (q31_t)0x6CF934FB, (q31_t)0xBCAF78C3, (q31_t)0x6CDECE2E, + (q31_t)0xBC84BD1E, (q31_t)0x6CC45697, (q31_t)0xBC5A0BE1, + (q31_t)0x6CA9CE3A, (q31_t)0xBC2F6513, (q31_t)0x6C8F351C, + (q31_t)0xBC04C8BA, (q31_t)0x6C748B3F, (q31_t)0xBBDA36DC, + (q31_t)0x6C59D0A9, (q31_t)0xBBAFAF81, (q31_t)0x6C3F055D, + (q31_t)0xBB8532AF, (q31_t)0x6C242960, (q31_t)0xBB5AC06C, + (q31_t)0x6C093CB6, (q31_t)0xBB3058C0, (q31_t)0x6BEE3F62, + (q31_t)0xBB05FBB0, (q31_t)0x6BD3316A, (q31_t)0xBADBA943, + (q31_t)0x6BB812D0, (q31_t)0xBAB1617F, (q31_t)0x6B9CE39B, + (q31_t)0xBA87246C, (q31_t)0x6B81A3CD, (q31_t)0xBA5CF210, + (q31_t)0x6B66536A, (q31_t)0xBA32CA70, (q31_t)0x6B4AF278, + (q31_t)0xBA08AD94, (q31_t)0x6B2F80FA, (q31_t)0xB9DE9B83, + (q31_t)0x6B13FEF5, (q31_t)0xB9B49442, (q31_t)0x6AF86C6C, + (q31_t)0xB98A97D8, (q31_t)0x6ADCC964, (q31_t)0xB960A64B, + (q31_t)0x6AC115E1, (q31_t)0xB936BFA3, (q31_t)0x6AA551E8, + (q31_t)0xB90CE3E6, (q31_t)0x6A897D7D, (q31_t)0xB8E31319, + (q31_t)0x6A6D98A4, (q31_t)0xB8B94D44, (q31_t)0x6A51A361, + (q31_t)0xB88F926C, (q31_t)0x6A359DB9, (q31_t)0xB865E299, + (q31_t)0x6A1987B0, (q31_t)0xB83C3DD1, (q31_t)0x69FD614A, + (q31_t)0xB812A419, (q31_t)0x69E12A8C, (q31_t)0xB7E9157A, + (q31_t)0x69C4E37A, (q31_t)0xB7BF91F8, (q31_t)0x69A88C18, + (q31_t)0xB796199B, (q31_t)0x698C246C, (q31_t)0xB76CAC68, + (q31_t)0x696FAC78, (q31_t)0xB7434A67, (q31_t)0x69532442, + (q31_t)0xB719F39D, (q31_t)0x69368BCE, (q31_t)0xB6F0A811, + (q31_t)0x6919E320, (q31_t)0xB6C767CA, (q31_t)0x68FD2A3D, + (q31_t)0xB69E32CD, (q31_t)0x68E06129, (q31_t)0xB6750921, + (q31_t)0x68C387E9, (q31_t)0xB64BEACC, (q31_t)0x68A69E81, + (q31_t)0xB622D7D5, (q31_t)0x6889A4F5, (q31_t)0xB5F9D042, + (q31_t)0x686C9B4B, (q31_t)0xB5D0D41A, (q31_t)0x684F8186, + (q31_t)0xB5A7E362, (q31_t)0x683257AA, (q31_t)0xB57EFE21, + (q31_t)0x68151DBE, (q31_t)0xB556245E, (q31_t)0x67F7D3C4, + (q31_t)0xB52D561E, (q31_t)0x67DA79C2, (q31_t)0xB5049368, + (q31_t)0x67BD0FBC, (q31_t)0xB4DBDC42, (q31_t)0x679F95B7, + (q31_t)0xB4B330B2, (q31_t)0x67820BB6, (q31_t)0xB48A90C0, + (q31_t)0x676471C0, (q31_t)0xB461FC70, (q31_t)0x6746C7D7, + (q31_t)0xB43973C9, (q31_t)0x67290E02, (q31_t)0xB410F6D2, + (q31_t)0x670B4443, (q31_t)0xB3E88591, (q31_t)0x66ED6AA1, + (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xB397C649, + (q31_t)0x66B187C3, (q31_t)0xB36F784E, (q31_t)0x66937E90, + (q31_t)0xB3473622, (q31_t)0x6675658C, (q31_t)0xB31EFFCB, + (q31_t)0x66573CBB, (q31_t)0xB2F6D54F, (q31_t)0x66390422, + (q31_t)0xB2CEB6B5, (q31_t)0x661ABBC5, (q31_t)0xB2A6A401, + (q31_t)0x65FC63A9, (q31_t)0xB27E9D3B, (q31_t)0x65DDFBD3, + (q31_t)0xB256A26A, (q31_t)0x65BF8447, (q31_t)0xB22EB392, + (q31_t)0x65A0FD0B, (q31_t)0xB206D0BA, (q31_t)0x65826622, + (q31_t)0xB1DEF9E8, (q31_t)0x6563BF92, (q31_t)0xB1B72F23, + (q31_t)0x6545095F, (q31_t)0xB18F7070, (q31_t)0x6526438E, + (q31_t)0xB167BDD6, (q31_t)0x65076E24, (q31_t)0xB140175B, + (q31_t)0x64E88926, (q31_t)0xB1187D05, (q31_t)0x64C99498, + (q31_t)0xB0F0EEDA, (q31_t)0x64AA907F, (q31_t)0xB0C96CDF, + (q31_t)0x648B7CDF, (q31_t)0xB0A1F71C, (q31_t)0x646C59BF, + (q31_t)0xB07A8D97, (q31_t)0x644D2722, (q31_t)0xB0533055, + (q31_t)0x642DE50D, (q31_t)0xB02BDF5C, (q31_t)0x640E9385, + (q31_t)0xB0049AB2, (q31_t)0x63EF328F, (q31_t)0xAFDD625F, + (q31_t)0x63CFC230, (q31_t)0xAFB63667, (q31_t)0x63B0426D, + (q31_t)0xAF8F16D0, (q31_t)0x6390B34A, (q31_t)0xAF6803A1, + (q31_t)0x637114CC, (q31_t)0xAF40FCE0, (q31_t)0x635166F8, + (q31_t)0xAF1A0293, (q31_t)0x6331A9D4, (q31_t)0xAEF314BF, + (q31_t)0x6311DD63, (q31_t)0xAECC336B, (q31_t)0x62F201AC, + (q31_t)0xAEA55E9D, (q31_t)0x62D216B2, (q31_t)0xAE7E965B, + (q31_t)0x62B21C7B, (q31_t)0xAE57DAAA, (q31_t)0x6292130C, + (q31_t)0xAE312B91, (q31_t)0x6271FA69, (q31_t)0xAE0A8916, + (q31_t)0x6251D297, (q31_t)0xADE3F33E, (q31_t)0x62319B9D, + (q31_t)0xADBD6A10, (q31_t)0x6211557D, (q31_t)0xAD96ED91, + (q31_t)0x61F1003E, (q31_t)0xAD707DC8, (q31_t)0x61D09BE5, + (q31_t)0xAD4A1ABA, (q31_t)0x61B02876, (q31_t)0xAD23C46D, + (q31_t)0x618FA5F6, (q31_t)0xACFD7AE8, (q31_t)0x616F146B, + (q31_t)0xACD73E30, (q31_t)0x614E73D9, (q31_t)0xACB10E4A, + (q31_t)0x612DC446, (q31_t)0xAC8AEB3E, (q31_t)0x610D05B7, + (q31_t)0xAC64D510, (q31_t)0x60EC3830, (q31_t)0xAC3ECBC7, + (q31_t)0x60CB5BB6, (q31_t)0xAC18CF68, (q31_t)0x60AA704F, + (q31_t)0xABF2DFFA, (q31_t)0x60897600, (q31_t)0xABCCFD82, + (q31_t)0x60686CCE, (q31_t)0xABA72806, (q31_t)0x604754BE, + (q31_t)0xAB815F8C, (q31_t)0x60262DD5, (q31_t)0xAB5BA41A, + (q31_t)0x6004F818, (q31_t)0xAB35F5B5, (q31_t)0x5FE3B38D, + (q31_t)0xAB105464, (q31_t)0x5FC26038, (q31_t)0xAAEAC02B, + (q31_t)0x5FA0FE1E, (q31_t)0xAAC53912, (q31_t)0x5F7F8D46, + (q31_t)0xAA9FBF1D, (q31_t)0x5F5E0DB3, (q31_t)0xAA7A5253, + (q31_t)0x5F3C7F6B, (q31_t)0xAA54F2B9, (q31_t)0x5F1AE273, + (q31_t)0xAA2FA055, (q31_t)0x5EF936D1, (q31_t)0xAA0A5B2D, + (q31_t)0x5ED77C89, (q31_t)0xA9E52347, (q31_t)0x5EB5B3A1, + (q31_t)0xA9BFF8A8, (q31_t)0x5E93DC1F, (q31_t)0xA99ADB56, + (q31_t)0x5E71F606, (q31_t)0xA975CB56, (q31_t)0x5E50015D, + (q31_t)0xA950C8AF, (q31_t)0x5E2DFE28, (q31_t)0xA92BD366, + (q31_t)0x5E0BEC6E, (q31_t)0xA906EB81, (q31_t)0x5DE9CC32, + (q31_t)0xA8E21106, (q31_t)0x5DC79D7C, (q31_t)0xA8BD43FA, + (q31_t)0x5DA5604E, (q31_t)0xA8988463, (q31_t)0x5D8314B0, + (q31_t)0xA873D246, (q31_t)0x5D60BAA6, (q31_t)0xA84F2DA9, + (q31_t)0x5D3E5236, (q31_t)0xA82A9693, (q31_t)0x5D1BDB65, + (q31_t)0xA8060D08, (q31_t)0x5CF95638, (q31_t)0xA7E1910E, + (q31_t)0x5CD6C2B4, (q31_t)0xA7BD22AB, (q31_t)0x5CB420DF, + (q31_t)0xA798C1E4, (q31_t)0x5C9170BF, (q31_t)0xA7746EC0, + (q31_t)0x5C6EB258, (q31_t)0xA7502943, (q31_t)0x5C4BE5B0, + (q31_t)0xA72BF173, (q31_t)0x5C290ACC, (q31_t)0xA707C756, + (q31_t)0x5C0621B2, (q31_t)0xA6E3AAF2, (q31_t)0x5BE32A67, + (q31_t)0xA6BF9C4B, (q31_t)0x5BC024F0, (q31_t)0xA69B9B68, + (q31_t)0x5B9D1153, (q31_t)0xA677A84E, (q31_t)0x5B79EF96, + (q31_t)0xA653C302, (q31_t)0x5B56BFBD, (q31_t)0xA62FEB8B, + (q31_t)0x5B3381CE, (q31_t)0xA60C21ED, (q31_t)0x5B1035CF, + (q31_t)0xA5E8662F, (q31_t)0x5AECDBC4, (q31_t)0xA5C4B855, + (q31_t)0x5AC973B4, (q31_t)0xA5A11865, (q31_t)0x5AA5FDA4, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA55A025B, + (q31_t)0x5A5EE79A, (q31_t)0xA5368C4B, (q31_t)0x5A3B47AA, + (q31_t)0xA513243B, (q31_t)0x5A1799D0, (q31_t)0xA4EFCA31, + (q31_t)0x59F3DE12, (q31_t)0xA4CC7E31, (q31_t)0x59D01474, + (q31_t)0xA4A94042, (q31_t)0x59AC3CFD, (q31_t)0xA4861069, + (q31_t)0x598857B1, (q31_t)0xA462EEAC, (q31_t)0x59646497, + (q31_t)0xA43FDB0F, (q31_t)0x594063B4, (q31_t)0xA41CD598, + (q31_t)0x591C550E, (q31_t)0xA3F9DE4D, (q31_t)0x58F838A9, + (q31_t)0xA3D6F533, (q31_t)0x58D40E8C, (q31_t)0xA3B41A4F, + (q31_t)0x58AFD6BC, (q31_t)0xA3914DA7, (q31_t)0x588B913F, + (q31_t)0xA36E8F40, (q31_t)0x58673E1B, (q31_t)0xA34BDF20, + (q31_t)0x5842DD54, (q31_t)0xA3293D4B, (q31_t)0x581E6EF1, + (q31_t)0xA306A9C7, (q31_t)0x57F9F2F7, (q31_t)0xA2E4249A, + (q31_t)0x57D5696C, (q31_t)0xA2C1ADC9, (q31_t)0x57B0D256, + (q31_t)0xA29F4559, (q31_t)0x578C2DB9, (q31_t)0xA27CEB4F, + (q31_t)0x57677B9D, (q31_t)0xA25A9FB1, (q31_t)0x5742BC05, + (q31_t)0xA2386283, (q31_t)0x571DEEF9, (q31_t)0xA21633CD, + (q31_t)0x56F9147E, (q31_t)0xA1F41391, (q31_t)0x56D42C99, + (q31_t)0xA1D201D7, (q31_t)0x56AF3750, (q31_t)0xA1AFFEA2, + (q31_t)0x568A34A9, (q31_t)0xA18E09F9, (q31_t)0x566524AA, + (q31_t)0xA16C23E1, (q31_t)0x56400757, (q31_t)0xA14A4C5E, + (q31_t)0x561ADCB8, (q31_t)0xA1288376, (q31_t)0x55F5A4D2, + (q31_t)0xA106C92E, (q31_t)0x55D05FAA, (q31_t)0xA0E51D8C, + (q31_t)0x55AB0D46, (q31_t)0xA0C38094, (q31_t)0x5585ADAC, + (q31_t)0xA0A1F24C, (q31_t)0x556040E2, (q31_t)0xA08072BA, + (q31_t)0x553AC6ED, (q31_t)0xA05F01E1, (q31_t)0x55153FD4, + (q31_t)0xA03D9FC7, (q31_t)0x54EFAB9C, (q31_t)0xA01C4C72, + (q31_t)0x54CA0A4A, (q31_t)0x9FFB07E7, (q31_t)0x54A45BE5, + (q31_t)0x9FD9D22A, (q31_t)0x547EA073, (q31_t)0x9FB8AB41, + (q31_t)0x5458D7F9, (q31_t)0x9F979331, (q31_t)0x5433027D, + (q31_t)0x9F7689FF, (q31_t)0x540D2005, (q31_t)0x9F558FB0, + (q31_t)0x53E73097, (q31_t)0x9F34A449, (q31_t)0x53C13438, + (q31_t)0x9F13C7D0, (q31_t)0x539B2AEF, (q31_t)0x9EF2FA48, + (q31_t)0x537514C1, (q31_t)0x9ED23BB9, (q31_t)0x534EF1B5, + (q31_t)0x9EB18C26, (q31_t)0x5328C1D0, (q31_t)0x9E90EB94, + (q31_t)0x53028517, (q31_t)0x9E705A09, (q31_t)0x52DC3B92, + (q31_t)0x9E4FD789, (q31_t)0x52B5E545, (q31_t)0x9E2F641A, + (q31_t)0x528F8237, (q31_t)0x9E0EFFC1, (q31_t)0x5269126E, + (q31_t)0x9DEEAA82, (q31_t)0x524295EF, (q31_t)0x9DCE6462, + (q31_t)0x521C0CC1, (q31_t)0x9DAE2D68, (q31_t)0x51F576E9, + (q31_t)0x9D8E0596, (q31_t)0x51CED46E, (q31_t)0x9D6DECF4, + (q31_t)0x51A82555, (q31_t)0x9D4DE384, (q31_t)0x518169A4, + (q31_t)0x9D2DE94D, (q31_t)0x515AA162, (q31_t)0x9D0DFE53, + (q31_t)0x5133CC94, (q31_t)0x9CEE229C, (q31_t)0x510CEB40, + (q31_t)0x9CCE562B, (q31_t)0x50E5FD6C, (q31_t)0x9CAE9907, + (q31_t)0x50BF031F, (q31_t)0x9C8EEB33, (q31_t)0x5097FC5E, + (q31_t)0x9C6F4CB5, (q31_t)0x5070E92F, (q31_t)0x9C4FBD92, + (q31_t)0x5049C999, (q31_t)0x9C303DCF, (q31_t)0x50229DA0, + (q31_t)0x9C10CD70, (q31_t)0x4FFB654D, (q31_t)0x9BF16C7A, + (q31_t)0x4FD420A3, (q31_t)0x9BD21AF2, (q31_t)0x4FACCFAB, + (q31_t)0x9BB2D8DD, (q31_t)0x4F857268, (q31_t)0x9B93A640, + (q31_t)0x4F5E08E3, (q31_t)0x9B748320, (q31_t)0x4F369320, + (q31_t)0x9B556F80, (q31_t)0x4F0F1126, (q31_t)0x9B366B67, + (q31_t)0x4EE782FA, (q31_t)0x9B1776D9, (q31_t)0x4EBFE8A4, + (q31_t)0x9AF891DB, (q31_t)0x4E984229, (q31_t)0x9AD9BC71, + (q31_t)0x4E708F8F, (q31_t)0x9ABAF6A0, (q31_t)0x4E48D0DC, + (q31_t)0x9A9C406D, (q31_t)0x4E210617, (q31_t)0x9A7D99DD, + (q31_t)0x4DF92F45, (q31_t)0x9A5F02F5, (q31_t)0x4DD14C6E, + (q31_t)0x9A407BB8, (q31_t)0x4DA95D96, (q31_t)0x9A22042C, + (q31_t)0x4D8162C4, (q31_t)0x9A039C56, (q31_t)0x4D595BFE, + (q31_t)0x99E5443A, (q31_t)0x4D31494B, (q31_t)0x99C6FBDE, + (q31_t)0x4D092AB0, (q31_t)0x99A8C344, (q31_t)0x4CE10034, + (q31_t)0x998A9A73, (q31_t)0x4CB8C9DD, (q31_t)0x996C816F, + (q31_t)0x4C9087B1, (q31_t)0x994E783C, (q31_t)0x4C6839B6, + (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9912955E, + (q31_t)0x4C177A6E, (q31_t)0x98F4BBBC, (q31_t)0x4BEF092D, + (q31_t)0x98D6F1FE, (q31_t)0x4BC68C36, (q31_t)0x98B93828, + (q31_t)0x4B9E038F, (q31_t)0x989B8E3F, (q31_t)0x4B756F3F, + (q31_t)0x987DF449, (q31_t)0x4B4CCF4D, (q31_t)0x98606A48, + (q31_t)0x4B2423BD, (q31_t)0x9842F043, (q31_t)0x4AFB6C97, + (q31_t)0x9825863D, (q31_t)0x4AD2A9E1, (q31_t)0x98082C3B, + (q31_t)0x4AA9DBA1, (q31_t)0x97EAE241, (q31_t)0x4A8101DE, + (q31_t)0x97CDA855, (q31_t)0x4A581C9D, (q31_t)0x97B07E7A, + (q31_t)0x4A2F2BE5, (q31_t)0x979364B5, (q31_t)0x4A062FBD, + (q31_t)0x97765B0A, (q31_t)0x49DD282A, (q31_t)0x9759617E, + (q31_t)0x49B41533, (q31_t)0x973C7816, (q31_t)0x498AF6DE, + (q31_t)0x971F9ED6, (q31_t)0x4961CD32, (q31_t)0x9702D5C2, + (q31_t)0x49389836, (q31_t)0x96E61CDF, (q31_t)0x490F57EE, + (q31_t)0x96C97431, (q31_t)0x48E60C62, (q31_t)0x96ACDBBD, + (q31_t)0x48BCB598, (q31_t)0x96905387, (q31_t)0x48935397, + (q31_t)0x9673DB94, (q31_t)0x4869E664, (q31_t)0x965773E7, + (q31_t)0x48406E07, (q31_t)0x963B1C85, (q31_t)0x4816EA85, + (q31_t)0x961ED573, (q31_t)0x47ED5BE6, (q31_t)0x96029EB5, + (q31_t)0x47C3C22E, (q31_t)0x95E6784F, (q31_t)0x479A1D66, + (q31_t)0x95CA6246, (q31_t)0x47706D93, (q31_t)0x95AE5C9E, + (q31_t)0x4746B2BC, (q31_t)0x9592675B, (q31_t)0x471CECE6, + (q31_t)0x95768282, (q31_t)0x46F31C1A, (q31_t)0x955AAE17, + (q31_t)0x46C9405C, (q31_t)0x953EEA1E, (q31_t)0x469F59B4, + (q31_t)0x9523369B, (q31_t)0x46756827, (q31_t)0x95079393, + (q31_t)0x464B6BBD, (q31_t)0x94EC010B, (q31_t)0x4621647C, + (q31_t)0x94D07F05, (q31_t)0x45F7526B, (q31_t)0x94B50D87, + (q31_t)0x45CD358F, (q31_t)0x9499AC95, (q31_t)0x45A30DF0, + (q31_t)0x947E5C32, (q31_t)0x4578DB93, (q31_t)0x94631C64, + (q31_t)0x454E9E80, (q31_t)0x9447ED2F, (q31_t)0x452456BC, + (q31_t)0x942CCE95, (q31_t)0x44FA044F, (q31_t)0x9411C09D, + (q31_t)0x44CFA73F, (q31_t)0x93F6C34A, (q31_t)0x44A53F93, + (q31_t)0x93DBD69F, (q31_t)0x447ACD50, (q31_t)0x93C0FAA2, + (q31_t)0x4450507E, (q31_t)0x93A62F56, (q31_t)0x4425C923, + (q31_t)0x938B74C0, (q31_t)0x43FB3745, (q31_t)0x9370CAE4, + (q31_t)0x43D09AEC, (q31_t)0x935631C5, (q31_t)0x43A5F41E, + (q31_t)0x933BA968, (q31_t)0x437B42E1, (q31_t)0x932131D1, + (q31_t)0x4350873C, (q31_t)0x9306CB04, (q31_t)0x4325C135, + (q31_t)0x92EC7505, (q31_t)0x42FAF0D4, (q31_t)0x92D22FD8, + (q31_t)0x42D0161E, (q31_t)0x92B7FB82, (q31_t)0x42A5311A, + (q31_t)0x929DD805, (q31_t)0x427A41D0, (q31_t)0x9283C567, + (q31_t)0x424F4845, (q31_t)0x9269C3AC, (q31_t)0x42244480, + (q31_t)0x924FD2D6, (q31_t)0x41F93688, (q31_t)0x9235F2EB, + (q31_t)0x41CE1E64, (q31_t)0x921C23EE, (q31_t)0x41A2FC1A, + (q31_t)0x920265E4, (q31_t)0x4177CFB0, (q31_t)0x91E8B8D0, + (q31_t)0x414C992E, (q31_t)0x91CF1CB6, (q31_t)0x4121589A, + (q31_t)0x91B5919A, (q31_t)0x40F60DFB, (q31_t)0x919C1780, + (q31_t)0x40CAB957, (q31_t)0x9182AE6C, (q31_t)0x409F5AB6, + (q31_t)0x91695663, (q31_t)0x4073F21D, (q31_t)0x91500F67, + (q31_t)0x40487F93, (q31_t)0x9136D97D, (q31_t)0x401D0320, + (q31_t)0x911DB4A8, (q31_t)0x3FF17CCA, (q31_t)0x9104A0ED, + (q31_t)0x3FC5EC97, (q31_t)0x90EB9E50, (q31_t)0x3F9A528F, + (q31_t)0x90D2ACD3, (q31_t)0x3F6EAEB8, (q31_t)0x90B9CC7C, + (q31_t)0x3F430118, (q31_t)0x90A0FD4E, (q31_t)0x3F1749B7, + (q31_t)0x90883F4C, (q31_t)0x3EEB889C, (q31_t)0x906F927B, + (q31_t)0x3EBFBDCC, (q31_t)0x9056F6DF, (q31_t)0x3E93E94F, + (q31_t)0x903E6C7A, (q31_t)0x3E680B2C, (q31_t)0x9025F352, + (q31_t)0x3E3C2369, (q31_t)0x900D8B69, (q31_t)0x3E10320D, + (q31_t)0x8FF534C4, (q31_t)0x3DE4371F, (q31_t)0x8FDCEF66, + (q31_t)0x3DB832A5, (q31_t)0x8FC4BB53, (q31_t)0x3D8C24A7, + (q31_t)0x8FAC988E, (q31_t)0x3D600D2B, (q31_t)0x8F94871D, + (q31_t)0x3D33EC39, (q31_t)0x8F7C8701, (q31_t)0x3D07C1D5, + (q31_t)0x8F64983F, (q31_t)0x3CDB8E09, (q31_t)0x8F4CBADB, + (q31_t)0x3CAF50DA, (q31_t)0x8F34EED8, (q31_t)0x3C830A4F, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8F058B04, + (q31_t)0x3C2A6142, (q31_t)0x8EEDF33B, (q31_t)0x3BFDFECD, + (q31_t)0x8ED66CE1, (q31_t)0x3BD19317, (q31_t)0x8EBEF7FB, + (q31_t)0x3BA51E29, (q31_t)0x8EA7948C, (q31_t)0x3B78A007, + (q31_t)0x8E904298, (q31_t)0x3B4C18BA, (q31_t)0x8E790222, + (q31_t)0x3B1F8847, (q31_t)0x8E61D32D, (q31_t)0x3AF2EEB7, + (q31_t)0x8E4AB5BF, (q31_t)0x3AC64C0F, (q31_t)0x8E33A9D9, + (q31_t)0x3A99A057, (q31_t)0x8E1CAF80, (q31_t)0x3A6CEB95, + (q31_t)0x8E05C6B7, (q31_t)0x3A402DD1, (q31_t)0x8DEEEF82, + (q31_t)0x3A136712, (q31_t)0x8DD829E4, (q31_t)0x39E6975D, + (q31_t)0x8DC175E0, (q31_t)0x39B9BEBB, (q31_t)0x8DAAD37B, + (q31_t)0x398CDD32, (q31_t)0x8D9442B7, (q31_t)0x395FF2C9, + (q31_t)0x8D7DC399, (q31_t)0x3932FF87, (q31_t)0x8D675623, + (q31_t)0x39060372, (q31_t)0x8D50FA59, (q31_t)0x38D8FE93, + (q31_t)0x8D3AB03F, (q31_t)0x38ABF0EF, (q31_t)0x8D2477D8, + (q31_t)0x387EDA8E, (q31_t)0x8D0E5127, (q31_t)0x3851BB76, + (q31_t)0x8CF83C30, (q31_t)0x382493B0, (q31_t)0x8CE238F6, + (q31_t)0x37F76340, (q31_t)0x8CCC477D, (q31_t)0x37CA2A30, + (q31_t)0x8CB667C7, (q31_t)0x379CE884, (q31_t)0x8CA099D9, + (q31_t)0x376F9E46, (q31_t)0x8C8ADDB6, (q31_t)0x37424B7A, + (q31_t)0x8C753361, (q31_t)0x3714F02A, (q31_t)0x8C5F9ADD, + (q31_t)0x36E78C5A, (q31_t)0x8C4A142F, (q31_t)0x36BA2013, + (q31_t)0x8C349F58, (q31_t)0x368CAB5C, (q31_t)0x8C1F3C5C, + (q31_t)0x365F2E3B, (q31_t)0x8C09EB40, (q31_t)0x3631A8B7, + (q31_t)0x8BF4AC05, (q31_t)0x36041AD9, (q31_t)0x8BDF7EAF, + (q31_t)0x35D684A5, (q31_t)0x8BCA6342, (q31_t)0x35A8E624, + (q31_t)0x8BB559C1, (q31_t)0x357B3F5D, (q31_t)0x8BA0622F, + (q31_t)0x354D9056, (q31_t)0x8B8B7C8F, (q31_t)0x351FD917, + (q31_t)0x8B76A8E4, (q31_t)0x34F219A7, (q31_t)0x8B61E732, + (q31_t)0x34C4520D, (q31_t)0x8B4D377C, (q31_t)0x3496824F, + (q31_t)0x8B3899C5, (q31_t)0x3468AA76, (q31_t)0x8B240E10, + (q31_t)0x343ACA87, (q31_t)0x8B0F9461, (q31_t)0x340CE28A, + (q31_t)0x8AFB2CBA, (q31_t)0x33DEF287, (q31_t)0x8AE6D71F, + (q31_t)0x33B0FA84, (q31_t)0x8AD29393, (q31_t)0x3382FA88, + (q31_t)0x8ABE6219, (q31_t)0x3354F29A, (q31_t)0x8AAA42B4, + (q31_t)0x3326E2C2, (q31_t)0x8A963567, (q31_t)0x32F8CB07, + (q31_t)0x8A823A35, (q31_t)0x32CAAB6F, (q31_t)0x8A6E5122, + (q31_t)0x329C8402, (q31_t)0x8A5A7A30, (q31_t)0x326E54C7, + (q31_t)0x8A46B563, (q31_t)0x32401DC5, (q31_t)0x8A3302BD, + (q31_t)0x3211DF03, (q31_t)0x8A1F6242, (q31_t)0x31E39889, + (q31_t)0x8A0BD3F5, (q31_t)0x31B54A5D, (q31_t)0x89F857D8, + (q31_t)0x3186F487, (q31_t)0x89E4EDEE, (q31_t)0x3158970D, + (q31_t)0x89D1963C, (q31_t)0x312A31F8, (q31_t)0x89BE50C3, + (q31_t)0x30FBC54D, (q31_t)0x89AB1D86, (q31_t)0x30CD5114, + (q31_t)0x8997FC89, (q31_t)0x309ED555, (q31_t)0x8984EDCF, + (q31_t)0x30705217, (q31_t)0x8971F15A, (q31_t)0x3041C760, + (q31_t)0x895F072D, (q31_t)0x30133538, (q31_t)0x894C2F4C, + (q31_t)0x2FE49BA6, (q31_t)0x893969B9, (q31_t)0x2FB5FAB2, + (q31_t)0x8926B677, (q31_t)0x2F875262, (q31_t)0x89141589, + (q31_t)0x2F58A2BD, (q31_t)0x890186F1, (q31_t)0x2F29EBCC, + (q31_t)0x88EF0AB4, (q31_t)0x2EFB2D94, (q31_t)0x88DCA0D3, + (q31_t)0x2ECC681E, (q31_t)0x88CA4951, (q31_t)0x2E9D9B70, + (q31_t)0x88B80431, (q31_t)0x2E6EC792, (q31_t)0x88A5D177, + (q31_t)0x2E3FEC8B, (q31_t)0x8893B124, (q31_t)0x2E110A62, + (q31_t)0x8881A33C, (q31_t)0x2DE2211E, (q31_t)0x886FA7C2, + (q31_t)0x2DB330C7, (q31_t)0x885DBEB7, (q31_t)0x2D843963, + (q31_t)0x884BE820, (q31_t)0x2D553AFB, (q31_t)0x883A23FE, + (q31_t)0x2D263595, (q31_t)0x88287255, (q31_t)0x2CF72939, + (q31_t)0x8816D327, (q31_t)0x2CC815ED, (q31_t)0x88054677, + (q31_t)0x2C98FBBA, (q31_t)0x87F3CC47, (q31_t)0x2C69DAA6, + (q31_t)0x87E2649B, (q31_t)0x2C3AB2B9, (q31_t)0x87D10F75, + (q31_t)0x2C0B83F9, (q31_t)0x87BFCCD7, (q31_t)0x2BDC4E6F, + (q31_t)0x87AE9CC5, (q31_t)0x2BAD1221, (q31_t)0x879D7F40, + (q31_t)0x2B7DCF17, (q31_t)0x878C744C, (q31_t)0x2B4E8558, + (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x876A9621, + (q31_t)0x2AEFDDD8, (q31_t)0x8759C2EF, (q31_t)0x2AC08025, + (q31_t)0x87490257, (q31_t)0x2A911BDB, (q31_t)0x8738545E, + (q31_t)0x2A61B101, (q31_t)0x8727B904, (q31_t)0x2A323F9D, + (q31_t)0x8717304E, (q31_t)0x2A02C7B8, (q31_t)0x8706BA3C, + (q31_t)0x29D34958, (q31_t)0x86F656D3, (q31_t)0x29A3C484, + (q31_t)0x86E60614, (q31_t)0x29743945, (q31_t)0x86D5C802, + (q31_t)0x2944A7A2, (q31_t)0x86C59C9F, (q31_t)0x29150FA1, + (q31_t)0x86B583EE, (q31_t)0x28E5714A, (q31_t)0x86A57DF1, + (q31_t)0x28B5CCA5, (q31_t)0x86958AAB, (q31_t)0x288621B9, + (q31_t)0x8685AA1F, (q31_t)0x2856708C, (q31_t)0x8675DC4E, + (q31_t)0x2826B928, (q31_t)0x8666213C, (q31_t)0x27F6FB92, + (q31_t)0x865678EA, (q31_t)0x27C737D2, (q31_t)0x8646E35B, + (q31_t)0x27976DF1, (q31_t)0x86376092, (q31_t)0x27679DF4, + (q31_t)0x8627F090, (q31_t)0x2737C7E3, (q31_t)0x86189359, + (q31_t)0x2707EBC6, (q31_t)0x860948EE, (q31_t)0x26D809A5, + (q31_t)0x85FA1152, (q31_t)0x26A82185, (q31_t)0x85EAEC88, + (q31_t)0x26783370, (q31_t)0x85DBDA91, (q31_t)0x26483F6C, + (q31_t)0x85CCDB70, (q31_t)0x26184581, (q31_t)0x85BDEF27, + (q31_t)0x25E845B5, (q31_t)0x85AF15B9, (q31_t)0x25B84012, + (q31_t)0x85A04F28, (q31_t)0x2588349D, (q31_t)0x85919B75, + (q31_t)0x2558235E, (q31_t)0x8582FAA4, (q31_t)0x25280C5D, + (q31_t)0x85746CB7, (q31_t)0x24F7EFA1, (q31_t)0x8565F1B0, + (q31_t)0x24C7CD32, (q31_t)0x85578991, (q31_t)0x2497A517, + (q31_t)0x8549345C, (q31_t)0x24677757, (q31_t)0x853AF214, + (q31_t)0x243743FA, (q31_t)0x852CC2BA, (q31_t)0x24070B07, + (q31_t)0x851EA652, (q31_t)0x23D6CC86, (q31_t)0x85109CDC, + (q31_t)0x23A6887E, (q31_t)0x8502A65C, (q31_t)0x23763EF7, + (q31_t)0x84F4C2D3, (q31_t)0x2345EFF7, (q31_t)0x84E6F244, + (q31_t)0x23159B87, (q31_t)0x84D934B0, (q31_t)0x22E541AE, + (q31_t)0x84CB8A1B, (q31_t)0x22B4E274, (q31_t)0x84BDF285, + (q31_t)0x22847DDF, (q31_t)0x84B06DF1, (q31_t)0x225413F8, + (q31_t)0x84A2FC62, (q31_t)0x2223A4C5, (q31_t)0x84959DD9, + (q31_t)0x21F3304E, (q31_t)0x84885257, (q31_t)0x21C2B69C, + (q31_t)0x847B19E1, (q31_t)0x219237B4, (q31_t)0x846DF476, + (q31_t)0x2161B39F, (q31_t)0x8460E21A, (q31_t)0x21312A65, + (q31_t)0x8453E2CE, (q31_t)0x21009C0B, (q31_t)0x8446F695, + (q31_t)0x20D0089B, (q31_t)0x843A1D70, (q31_t)0x209F701C, + (q31_t)0x842D5761, (q31_t)0x206ED295, (q31_t)0x8420A46B, + (q31_t)0x203E300D, (q31_t)0x8414048F, (q31_t)0x200D888C, + (q31_t)0x840777CF, (q31_t)0x1FDCDC1A, (q31_t)0x83FAFE2E, + (q31_t)0x1FAC2ABF, (q31_t)0x83EE97AC, (q31_t)0x1F7B7480, + (q31_t)0x83E2444D, (q31_t)0x1F4AB967, (q31_t)0x83D60411, + (q31_t)0x1F19F97B, (q31_t)0x83C9D6FB, (q31_t)0x1EE934C2, + (q31_t)0x83BDBD0D, (q31_t)0x1EB86B46, (q31_t)0x83B1B649, + (q31_t)0x1E879D0C, (q31_t)0x83A5C2B0, (q31_t)0x1E56CA1E, + (q31_t)0x8399E244, (q31_t)0x1E25F281, (q31_t)0x838E1507, + (q31_t)0x1DF5163F, (q31_t)0x83825AFB, (q31_t)0x1DC4355D, + (q31_t)0x8376B422, (q31_t)0x1D934FE5, (q31_t)0x836B207D, + (q31_t)0x1D6265DD, (q31_t)0x835FA00E, (q31_t)0x1D31774D, + (q31_t)0x835432D8, (q31_t)0x1D00843C, (q31_t)0x8348D8DB, + (q31_t)0x1CCF8CB3, (q31_t)0x833D921A, (q31_t)0x1C9E90B8, + (q31_t)0x83325E97, (q31_t)0x1C6D9053, (q31_t)0x83273E52, + (q31_t)0x1C3C8B8C, (q31_t)0x831C314E, (q31_t)0x1C0B826A, + (q31_t)0x8311378C, (q31_t)0x1BDA74F5, (q31_t)0x8306510F, + (q31_t)0x1BA96334, (q31_t)0x82FB7DD8, (q31_t)0x1B784D30, + (q31_t)0x82F0BDE8, (q31_t)0x1B4732EF, (q31_t)0x82E61141, + (q31_t)0x1B161479, (q31_t)0x82DB77E5, (q31_t)0x1AE4F1D6, + (q31_t)0x82D0F1D5, (q31_t)0x1AB3CB0C, (q31_t)0x82C67F13, + (q31_t)0x1A82A025, (q31_t)0x82BC1FA1, (q31_t)0x1A517127, + (q31_t)0x82B1D381, (q31_t)0x1A203E1B, (q31_t)0x82A79AB3, + (q31_t)0x19EF0706, (q31_t)0x829D753A, (q31_t)0x19BDCBF2, + (q31_t)0x82936316, (q31_t)0x198C8CE6, (q31_t)0x8289644A, + (q31_t)0x195B49E9, (q31_t)0x827F78D8, (q31_t)0x192A0303, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x826BDC04, + (q31_t)0x18C7699B, (q31_t)0x82622AA5, (q31_t)0x18961727, + (q31_t)0x82588CA6, (q31_t)0x1864C0E9, (q31_t)0x824F0208, + (q31_t)0x183366E8, (q31_t)0x82458ACB, (q31_t)0x1802092C, + (q31_t)0x823C26F2, (q31_t)0x17D0A7BB, (q31_t)0x8232D67E, + (q31_t)0x179F429F, (q31_t)0x82299971, (q31_t)0x176DD9DE, + (q31_t)0x82206FCB, (q31_t)0x173C6D80, (q31_t)0x8217598F, + (q31_t)0x170AFD8D, (q31_t)0x820E56BE, (q31_t)0x16D98A0C, + (q31_t)0x82056758, (q31_t)0x16A81305, (q31_t)0x81FC8B60, + (q31_t)0x1676987F, (q31_t)0x81F3C2D7, (q31_t)0x16451A83, + (q31_t)0x81EB0DBD, (q31_t)0x16139917, (q31_t)0x81E26C16, + (q31_t)0x15E21444, (q31_t)0x81D9DDE1, (q31_t)0x15B08C11, + (q31_t)0x81D16320, (q31_t)0x157F0086, (q31_t)0x81C8FBD5, + (q31_t)0x154D71AA, (q31_t)0x81C0A801, (q31_t)0x151BDF85, + (q31_t)0x81B867A4, (q31_t)0x14EA4A1F, (q31_t)0x81B03AC1, + (q31_t)0x14B8B17F, (q31_t)0x81A82159, (q31_t)0x148715AD, + (q31_t)0x81A01B6C, (q31_t)0x145576B1, (q31_t)0x819828FD, + (q31_t)0x1423D492, (q31_t)0x81904A0C, (q31_t)0x13F22F57, + (q31_t)0x81887E9A, (q31_t)0x13C0870A, (q31_t)0x8180C6A9, + (q31_t)0x138EDBB0, (q31_t)0x8179223A, (q31_t)0x135D2D53, + (q31_t)0x8171914E, (q31_t)0x132B7BF9, (q31_t)0x816A13E6, + (q31_t)0x12F9C7AA, (q31_t)0x8162AA03, (q31_t)0x12C8106E, + (q31_t)0x815B53A8, (q31_t)0x1296564D, (q31_t)0x815410D3, + (q31_t)0x1264994E, (q31_t)0x814CE188, (q31_t)0x1232D978, + (q31_t)0x8145C5C6, (q31_t)0x120116D4, (q31_t)0x813EBD90, + (q31_t)0x11CF516A, (q31_t)0x8137C8E6, (q31_t)0x119D8940, + (q31_t)0x8130E7C8, (q31_t)0x116BBE5F, (q31_t)0x812A1A39, + (q31_t)0x1139F0CE, (q31_t)0x81236039, (q31_t)0x11082096, + (q31_t)0x811CB9CA, (q31_t)0x10D64DBC, (q31_t)0x811626EC, + (q31_t)0x10A4784A, (q31_t)0x810FA7A0, (q31_t)0x1072A047, + (q31_t)0x81093BE8, (q31_t)0x1040C5BB, (q31_t)0x8102E3C3, + (q31_t)0x100EE8AD, (q31_t)0x80FC9F35, (q31_t)0x0FDD0925, + (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x80F050DB, + (q31_t)0x0F7942C6, (q31_t)0x80EA4712, (q31_t)0x0F475BFE, + (q31_t)0x80E450E2, (q31_t)0x0F1572DC, (q31_t)0x80DE6E4C, + (q31_t)0x0EE38765, (q31_t)0x80D89F51, (q31_t)0x0EB199A3, + (q31_t)0x80D2E3F1, (q31_t)0x0E7FA99D, (q31_t)0x80CD3C2F, + (q31_t)0x0E4DB75B, (q31_t)0x80C7A80A, (q31_t)0x0E1BC2E3, + (q31_t)0x80C22783, (q31_t)0x0DE9CC3F, (q31_t)0x80BCBA9C, + (q31_t)0x0DB7D376, (q31_t)0x80B76155, (q31_t)0x0D85D88F, + (q31_t)0x80B21BAF, (q31_t)0x0D53DB92, (q31_t)0x80ACE9AB, + (q31_t)0x0D21DC87, (q31_t)0x80A7CB49, (q31_t)0x0CEFDB75, + (q31_t)0x80A2C08B, (q31_t)0x0CBDD865, (q31_t)0x809DC970, + (q31_t)0x0C8BD35E, (q31_t)0x8098E5FB, (q31_t)0x0C59CC67, + (q31_t)0x8094162B, (q31_t)0x0C27C389, (q31_t)0x808F5A02, + (q31_t)0x0BF5B8CB, (q31_t)0x808AB180, (q31_t)0x0BC3AC35, + (q31_t)0x80861CA5, (q31_t)0x0B919DCE, (q31_t)0x80819B74, + (q31_t)0x0B5F8D9F, (q31_t)0x807D2DEB, (q31_t)0x0B2D7BAE, + (q31_t)0x8078D40D, (q31_t)0x0AFB6805, (q31_t)0x80748DD9, + (q31_t)0x0AC952AA, (q31_t)0x80705B50, (q31_t)0x0A973BA5, + (q31_t)0x806C3C73, (q31_t)0x0A6522FE, (q31_t)0x80683143, + (q31_t)0x0A3308BC, (q31_t)0x806439C0, (q31_t)0x0A00ECE8, + (q31_t)0x806055EA, (q31_t)0x09CECF89, (q31_t)0x805C85C3, + (q31_t)0x099CB0A7, (q31_t)0x8058C94C, (q31_t)0x096A9049, + (q31_t)0x80552083, (q31_t)0x09386E77, (q31_t)0x80518B6B, + (q31_t)0x09064B3A, (q31_t)0x804E0A03, (q31_t)0x08D42698, + (q31_t)0x804A9C4D, (q31_t)0x08A2009A, (q31_t)0x80474248, + (q31_t)0x086FD947, (q31_t)0x8043FBF6, (q31_t)0x083DB0A7, + (q31_t)0x8040C956, (q31_t)0x080B86C1, (q31_t)0x803DAA69, + (q31_t)0x07D95B9E, (q31_t)0x803A9F31, (q31_t)0x07A72F45, + (q31_t)0x8037A7AC, (q31_t)0x077501BE, (q31_t)0x8034C3DC, + (q31_t)0x0742D310, (q31_t)0x8031F3C1, (q31_t)0x0710A344, + (q31_t)0x802F375C, (q31_t)0x06DE7261, (q31_t)0x802C8EAD, + (q31_t)0x06AC406F, (q31_t)0x8029F9B4, (q31_t)0x067A0D75, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x80250AE7, + (q31_t)0x0615A48A, (q31_t)0x8022B113, (q31_t)0x05E36EA9, + (q31_t)0x80206AF8, (q31_t)0x05B137DF, (q31_t)0x801E3894, + (q31_t)0x057F0034, (q31_t)0x801C19E9, (q31_t)0x054CC7B0, + (q31_t)0x801A0EF7, (q31_t)0x051A8E5C, (q31_t)0x801817BF, + (q31_t)0x04E8543D, (q31_t)0x80163440, (q31_t)0x04B6195D, + (q31_t)0x8014647A, (q31_t)0x0483DDC3, (q31_t)0x8012A86F, + (q31_t)0x0451A176, (q31_t)0x8011001E, (q31_t)0x041F647F, + (q31_t)0x800F6B88, (q31_t)0x03ED26E6, (q31_t)0x800DEAAC, + (q31_t)0x03BAE8B1, (q31_t)0x800C7D8C, (q31_t)0x0388A9E9, + (q31_t)0x800B2427, (q31_t)0x03566A96, (q31_t)0x8009DE7D, + (q31_t)0x03242ABF, (q31_t)0x8008AC90, (q31_t)0x02F1EA6B, + (q31_t)0x80078E5E, (q31_t)0x02BFA9A4, (q31_t)0x800683E8, + (q31_t)0x028D6870, (q31_t)0x80058D2E, (q31_t)0x025B26D7, + (q31_t)0x8004AA31, (q31_t)0x0228E4E1, (q31_t)0x8003DAF0, + (q31_t)0x01F6A296, (q31_t)0x80031F6C, (q31_t)0x01C45FFE, + (q31_t)0x800277A5, (q31_t)0x01921D1F, (q31_t)0x8001E39B, + (q31_t)0x015FDA03, (q31_t)0x8001634D, (q31_t)0x012D96B0, + (q31_t)0x8000F6BD, (q31_t)0x00FB532F, (q31_t)0x80009DE9, + (q31_t)0x00C90F88, (q31_t)0x800058D3, (q31_t)0x0096CBC1, + (q31_t)0x8000277A, (q31_t)0x006487E3, (q31_t)0x800009DE, + (q31_t)0x003243F5, (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x800009DE, (q31_t)0xFFCDBC0A, (q31_t)0x8000277A, + (q31_t)0xFF9B781D, (q31_t)0x800058D3, (q31_t)0xFF69343E, + (q31_t)0x80009DE9, (q31_t)0xFF36F078, (q31_t)0x8000F6BD, + (q31_t)0xFF04ACD0, (q31_t)0x8001634D, (q31_t)0xFED2694F, + (q31_t)0x8001E39B, (q31_t)0xFEA025FC, (q31_t)0x800277A5, + (q31_t)0xFE6DE2E0, (q31_t)0x80031F6C, (q31_t)0xFE3BA001, + (q31_t)0x8003DAF0, (q31_t)0xFE095D69, (q31_t)0x8004AA31, + (q31_t)0xFDD71B1E, (q31_t)0x80058D2E, (q31_t)0xFDA4D928, + (q31_t)0x800683E8, (q31_t)0xFD72978F, (q31_t)0x80078E5E, + (q31_t)0xFD40565B, (q31_t)0x8008AC90, (q31_t)0xFD0E1594, + (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x800B2427, + (q31_t)0xFCA99569, (q31_t)0x800C7D8C, (q31_t)0xFC775616, + (q31_t)0x800DEAAC, (q31_t)0xFC45174E, (q31_t)0x800F6B88, + (q31_t)0xFC12D919, (q31_t)0x8011001E, (q31_t)0xFBE09B80, + (q31_t)0x8012A86F, (q31_t)0xFBAE5E89, (q31_t)0x8014647A, + (q31_t)0xFB7C223C, (q31_t)0x80163440, (q31_t)0xFB49E6A2, + (q31_t)0x801817BF, (q31_t)0xFB17ABC2, (q31_t)0x801A0EF7, + (q31_t)0xFAE571A4, (q31_t)0x801C19E9, (q31_t)0xFAB3384F, + (q31_t)0x801E3894, (q31_t)0xFA80FFCB, (q31_t)0x80206AF8, + (q31_t)0xFA4EC820, (q31_t)0x8022B113, (q31_t)0xFA1C9156, + (q31_t)0x80250AE7, (q31_t)0xF9EA5B75, (q31_t)0x80277872, + (q31_t)0xF9B82683, (q31_t)0x8029F9B4, (q31_t)0xF985F28A, + (q31_t)0x802C8EAD, (q31_t)0xF953BF90, (q31_t)0x802F375C, + (q31_t)0xF9218D9E, (q31_t)0x8031F3C1, (q31_t)0xF8EF5CBB, + (q31_t)0x8034C3DC, (q31_t)0xF8BD2CEF, (q31_t)0x8037A7AC, + (q31_t)0xF88AFE41, (q31_t)0x803A9F31, (q31_t)0xF858D0BA, + (q31_t)0x803DAA69, (q31_t)0xF826A461, (q31_t)0x8040C956, + (q31_t)0xF7F4793E, (q31_t)0x8043FBF6, (q31_t)0xF7C24F58, + (q31_t)0x80474248, (q31_t)0xF79026B8, (q31_t)0x804A9C4D, + (q31_t)0xF75DFF65, (q31_t)0x804E0A03, (q31_t)0xF72BD967, + (q31_t)0x80518B6B, (q31_t)0xF6F9B4C5, (q31_t)0x80552083, + (q31_t)0xF6C79188, (q31_t)0x8058C94C, (q31_t)0xF6956FB6, + (q31_t)0x805C85C3, (q31_t)0xF6634F58, (q31_t)0x806055EA, + (q31_t)0xF6313076, (q31_t)0x806439C0, (q31_t)0xF5FF1317, + (q31_t)0x80683143, (q31_t)0xF5CCF743, (q31_t)0x806C3C73, + (q31_t)0xF59ADD01, (q31_t)0x80705B50, (q31_t)0xF568C45A, + (q31_t)0x80748DD9, (q31_t)0xF536AD55, (q31_t)0x8078D40D, + (q31_t)0xF50497FA, (q31_t)0x807D2DEB, (q31_t)0xF4D28451, + (q31_t)0x80819B74, (q31_t)0xF4A07260, (q31_t)0x80861CA5, + (q31_t)0xF46E6231, (q31_t)0x808AB180, (q31_t)0xF43C53CA, + (q31_t)0x808F5A02, (q31_t)0xF40A4734, (q31_t)0x8094162B, + (q31_t)0xF3D83C76, (q31_t)0x8098E5FB, (q31_t)0xF3A63398, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80A2C08B, + (q31_t)0xF342279A, (q31_t)0x80A7CB49, (q31_t)0xF310248A, + (q31_t)0x80ACE9AB, (q31_t)0xF2DE2378, (q31_t)0x80B21BAF, + (q31_t)0xF2AC246D, (q31_t)0x80B76155, (q31_t)0xF27A2770, + (q31_t)0x80BCBA9C, (q31_t)0xF2482C89, (q31_t)0x80C22783, + (q31_t)0xF21633C0, (q31_t)0x80C7A80A, (q31_t)0xF1E43D1C, + (q31_t)0x80CD3C2F, (q31_t)0xF1B248A5, (q31_t)0x80D2E3F1, + (q31_t)0xF1805662, (q31_t)0x80D89F51, (q31_t)0xF14E665C, + (q31_t)0x80DE6E4C, (q31_t)0xF11C789A, (q31_t)0x80E450E2, + (q31_t)0xF0EA8D23, (q31_t)0x80EA4712, (q31_t)0xF0B8A401, + (q31_t)0x80F050DB, (q31_t)0xF086BD39, (q31_t)0x80F66E3C, + (q31_t)0xF054D8D4, (q31_t)0x80FC9F35, (q31_t)0xF022F6DA, + (q31_t)0x8102E3C3, (q31_t)0xEFF11752, (q31_t)0x81093BE8, + (q31_t)0xEFBF3A44, (q31_t)0x810FA7A0, (q31_t)0xEF8D5FB8, + (q31_t)0x811626EC, (q31_t)0xEF5B87B5, (q31_t)0x811CB9CA, + (q31_t)0xEF29B243, (q31_t)0x81236039, (q31_t)0xEEF7DF6A, + (q31_t)0x812A1A39, (q31_t)0xEEC60F31, (q31_t)0x8130E7C8, + (q31_t)0xEE9441A0, (q31_t)0x8137C8E6, (q31_t)0xEE6276BF, + (q31_t)0x813EBD90, (q31_t)0xEE30AE95, (q31_t)0x8145C5C6, + (q31_t)0xEDFEE92B, (q31_t)0x814CE188, (q31_t)0xEDCD2687, + (q31_t)0x815410D3, (q31_t)0xED9B66B2, (q31_t)0x815B53A8, + (q31_t)0xED69A9B2, (q31_t)0x8162AA03, (q31_t)0xED37EF91, + (q31_t)0x816A13E6, (q31_t)0xED063855, (q31_t)0x8171914E, + (q31_t)0xECD48406, (q31_t)0x8179223A, (q31_t)0xECA2D2AC, + (q31_t)0x8180C6A9, (q31_t)0xEC71244F, (q31_t)0x81887E9A, + (q31_t)0xEC3F78F5, (q31_t)0x81904A0C, (q31_t)0xEC0DD0A8, + (q31_t)0x819828FD, (q31_t)0xEBDC2B6D, (q31_t)0x81A01B6C, + (q31_t)0xEBAA894E, (q31_t)0x81A82159, (q31_t)0xEB78EA52, + (q31_t)0x81B03AC1, (q31_t)0xEB474E80, (q31_t)0x81B867A4, + (q31_t)0xEB15B5E0, (q31_t)0x81C0A801, (q31_t)0xEAE4207A, + (q31_t)0x81C8FBD5, (q31_t)0xEAB28E55, (q31_t)0x81D16320, + (q31_t)0xEA80FF79, (q31_t)0x81D9DDE1, (q31_t)0xEA4F73EE, + (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x81EB0DBD, + (q31_t)0xE9EC66E8, (q31_t)0x81F3C2D7, (q31_t)0xE9BAE57C, + (q31_t)0x81FC8B60, (q31_t)0xE9896780, (q31_t)0x82056758, + (q31_t)0xE957ECFB, (q31_t)0x820E56BE, (q31_t)0xE92675F4, + (q31_t)0x8217598F, (q31_t)0xE8F50273, (q31_t)0x82206FCB, + (q31_t)0xE8C3927F, (q31_t)0x82299971, (q31_t)0xE8922621, + (q31_t)0x8232D67E, (q31_t)0xE860BD60, (q31_t)0x823C26F2, + (q31_t)0xE82F5844, (q31_t)0x82458ACB, (q31_t)0xE7FDF6D3, + (q31_t)0x824F0208, (q31_t)0xE7CC9917, (q31_t)0x82588CA6, + (q31_t)0xE79B3F16, (q31_t)0x82622AA5, (q31_t)0xE769E8D8, + (q31_t)0x826BDC04, (q31_t)0xE7389664, (q31_t)0x8275A0C0, + (q31_t)0xE70747C3, (q31_t)0x827F78D8, (q31_t)0xE6D5FCFC, + (q31_t)0x8289644A, (q31_t)0xE6A4B616, (q31_t)0x82936316, + (q31_t)0xE6737319, (q31_t)0x829D753A, (q31_t)0xE642340D, + (q31_t)0x82A79AB3, (q31_t)0xE610F8F9, (q31_t)0x82B1D381, + (q31_t)0xE5DFC1E4, (q31_t)0x82BC1FA1, (q31_t)0xE5AE8ED8, + (q31_t)0x82C67F13, (q31_t)0xE57D5FDA, (q31_t)0x82D0F1D5, + (q31_t)0xE54C34F3, (q31_t)0x82DB77E5, (q31_t)0xE51B0E2A, + (q31_t)0x82E61141, (q31_t)0xE4E9EB86, (q31_t)0x82F0BDE8, + (q31_t)0xE4B8CD10, (q31_t)0x82FB7DD8, (q31_t)0xE487B2CF, + (q31_t)0x8306510F, (q31_t)0xE4569CCB, (q31_t)0x8311378C, + (q31_t)0xE4258B0A, (q31_t)0x831C314E, (q31_t)0xE3F47D95, + (q31_t)0x83273E52, (q31_t)0xE3C37473, (q31_t)0x83325E97, + (q31_t)0xE3926FAC, (q31_t)0x833D921A, (q31_t)0xE3616F47, + (q31_t)0x8348D8DB, (q31_t)0xE330734C, (q31_t)0x835432D8, + (q31_t)0xE2FF7BC3, (q31_t)0x835FA00E, (q31_t)0xE2CE88B2, + (q31_t)0x836B207D, (q31_t)0xE29D9A22, (q31_t)0x8376B422, + (q31_t)0xE26CB01A, (q31_t)0x83825AFB, (q31_t)0xE23BCAA2, + (q31_t)0x838E1507, (q31_t)0xE20AE9C1, (q31_t)0x8399E244, + (q31_t)0xE1DA0D7E, (q31_t)0x83A5C2B0, (q31_t)0xE1A935E1, + (q31_t)0x83B1B649, (q31_t)0xE17862F3, (q31_t)0x83BDBD0D, + (q31_t)0xE14794B9, (q31_t)0x83C9D6FB, (q31_t)0xE116CB3D, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x83E2444D, + (q31_t)0xE0B54698, (q31_t)0x83EE97AC, (q31_t)0xE0848B7F, + (q31_t)0x83FAFE2E, (q31_t)0xE053D541, (q31_t)0x840777CF, + (q31_t)0xE02323E5, (q31_t)0x8414048F, (q31_t)0xDFF27773, + (q31_t)0x8420A46B, (q31_t)0xDFC1CFF2, (q31_t)0x842D5761, + (q31_t)0xDF912D6A, (q31_t)0x843A1D70, (q31_t)0xDF608FE3, + (q31_t)0x8446F695, (q31_t)0xDF2FF764, (q31_t)0x8453E2CE, + (q31_t)0xDEFF63F4, (q31_t)0x8460E21A, (q31_t)0xDECED59B, + (q31_t)0x846DF476, (q31_t)0xDE9E4C60, (q31_t)0x847B19E1, + (q31_t)0xDE6DC84B, (q31_t)0x84885257, (q31_t)0xDE3D4963, + (q31_t)0x84959DD9, (q31_t)0xDE0CCFB1, (q31_t)0x84A2FC62, + (q31_t)0xDDDC5B3A, (q31_t)0x84B06DF1, (q31_t)0xDDABEC07, + (q31_t)0x84BDF285, (q31_t)0xDD7B8220, (q31_t)0x84CB8A1B, + (q31_t)0xDD4B1D8B, (q31_t)0x84D934B0, (q31_t)0xDD1ABE51, + (q31_t)0x84E6F244, (q31_t)0xDCEA6478, (q31_t)0x84F4C2D3, + (q31_t)0xDCBA1008, (q31_t)0x8502A65C, (q31_t)0xDC89C108, + (q31_t)0x85109CDC, (q31_t)0xDC597781, (q31_t)0x851EA652, + (q31_t)0xDC293379, (q31_t)0x852CC2BA, (q31_t)0xDBF8F4F8, + (q31_t)0x853AF214, (q31_t)0xDBC8BC05, (q31_t)0x8549345C, + (q31_t)0xDB9888A8, (q31_t)0x85578991, (q31_t)0xDB685AE8, + (q31_t)0x8565F1B0, (q31_t)0xDB3832CD, (q31_t)0x85746CB7, + (q31_t)0xDB08105E, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2, + (q31_t)0x85919B75, (q31_t)0xDAA7DCA1, (q31_t)0x85A04F28, + (q31_t)0xDA77CB62, (q31_t)0x85AF15B9, (q31_t)0xDA47BFED, + (q31_t)0x85BDEF27, (q31_t)0xDA17BA4A, (q31_t)0x85CCDB70, + (q31_t)0xD9E7BA7E, (q31_t)0x85DBDA91, (q31_t)0xD9B7C093, + (q31_t)0x85EAEC88, (q31_t)0xD987CC8F, (q31_t)0x85FA1152, + (q31_t)0xD957DE7A, (q31_t)0x860948EE, (q31_t)0xD927F65B, + (q31_t)0x86189359, (q31_t)0xD8F81439, (q31_t)0x8627F090, + (q31_t)0xD8C8381C, (q31_t)0x86376092, (q31_t)0xD898620C, + (q31_t)0x8646E35B, (q31_t)0xD868920F, (q31_t)0x865678EA, + (q31_t)0xD838C82D, (q31_t)0x8666213C, (q31_t)0xD809046D, + (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x8685AA1F, + (q31_t)0xD7A98F73, (q31_t)0x86958AAB, (q31_t)0xD779DE46, + (q31_t)0x86A57DF1, (q31_t)0xD74A335A, (q31_t)0x86B583EE, + (q31_t)0xD71A8EB5, (q31_t)0x86C59C9F, (q31_t)0xD6EAF05E, + (q31_t)0x86D5C802, (q31_t)0xD6BB585D, (q31_t)0x86E60614, + (q31_t)0xD68BC6BA, (q31_t)0x86F656D3, (q31_t)0xD65C3B7B, + (q31_t)0x8706BA3C, (q31_t)0xD62CB6A7, (q31_t)0x8717304E, + (q31_t)0xD5FD3847, (q31_t)0x8727B904, (q31_t)0xD5CDC062, + (q31_t)0x8738545E, (q31_t)0xD59E4EFE, (q31_t)0x87490257, + (q31_t)0xD56EE424, (q31_t)0x8759C2EF, (q31_t)0xD53F7FDA, + (q31_t)0x876A9621, (q31_t)0xD5102227, (q31_t)0x877B7BEC, + (q31_t)0xD4E0CB14, (q31_t)0x878C744C, (q31_t)0xD4B17AA7, + (q31_t)0x879D7F40, (q31_t)0xD48230E8, (q31_t)0x87AE9CC5, + (q31_t)0xD452EDDE, (q31_t)0x87BFCCD7, (q31_t)0xD423B190, + (q31_t)0x87D10F75, (q31_t)0xD3F47C06, (q31_t)0x87E2649B, + (q31_t)0xD3C54D46, (q31_t)0x87F3CC47, (q31_t)0xD3962559, + (q31_t)0x88054677, (q31_t)0xD3670445, (q31_t)0x8816D327, + (q31_t)0xD337EA12, (q31_t)0x88287255, (q31_t)0xD308D6C6, + (q31_t)0x883A23FE, (q31_t)0xD2D9CA6A, (q31_t)0x884BE820, + (q31_t)0xD2AAC504, (q31_t)0x885DBEB7, (q31_t)0xD27BC69C, + (q31_t)0x886FA7C2, (q31_t)0xD24CCF38, (q31_t)0x8881A33C, + (q31_t)0xD21DDEE1, (q31_t)0x8893B124, (q31_t)0xD1EEF59E, + (q31_t)0x88A5D177, (q31_t)0xD1C01374, (q31_t)0x88B80431, + (q31_t)0xD191386D, (q31_t)0x88CA4951, (q31_t)0xD162648F, + (q31_t)0x88DCA0D3, (q31_t)0xD13397E1, (q31_t)0x88EF0AB4, + (q31_t)0xD104D26B, (q31_t)0x890186F1, (q31_t)0xD0D61433, + (q31_t)0x89141589, (q31_t)0xD0A75D42, (q31_t)0x8926B677, + (q31_t)0xD078AD9D, (q31_t)0x893969B9, (q31_t)0xD04A054D, + (q31_t)0x894C2F4C, (q31_t)0xD01B6459, (q31_t)0x895F072D, + (q31_t)0xCFECCAC7, (q31_t)0x8971F15A, (q31_t)0xCFBE389F, + (q31_t)0x8984EDCF, (q31_t)0xCF8FADE8, (q31_t)0x8997FC89, + (q31_t)0xCF612AAA, (q31_t)0x89AB1D86, (q31_t)0xCF32AEEB, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x89D1963C, + (q31_t)0xCED5CE08, (q31_t)0x89E4EDEE, (q31_t)0xCEA768F2, + (q31_t)0x89F857D8, (q31_t)0xCE790B78, (q31_t)0x8A0BD3F5, + (q31_t)0xCE4AB5A2, (q31_t)0x8A1F6242, (q31_t)0xCE1C6776, + (q31_t)0x8A3302BD, (q31_t)0xCDEE20FC, (q31_t)0x8A46B563, + (q31_t)0xCDBFE23A, (q31_t)0x8A5A7A30, (q31_t)0xCD91AB38, + (q31_t)0x8A6E5122, (q31_t)0xCD637BFD, (q31_t)0x8A823A35, + (q31_t)0xCD355490, (q31_t)0x8A963567, (q31_t)0xCD0734F8, + (q31_t)0x8AAA42B4, (q31_t)0xCCD91D3D, (q31_t)0x8ABE6219, + (q31_t)0xCCAB0D65, (q31_t)0x8AD29393, (q31_t)0xCC7D0577, + (q31_t)0x8AE6D71F, (q31_t)0xCC4F057B, (q31_t)0x8AFB2CBA, + (q31_t)0xCC210D78, (q31_t)0x8B0F9461, (q31_t)0xCBF31D75, + (q31_t)0x8B240E10, (q31_t)0xCBC53578, (q31_t)0x8B3899C5, + (q31_t)0xCB975589, (q31_t)0x8B4D377C, (q31_t)0xCB697DB0, + (q31_t)0x8B61E732, (q31_t)0xCB3BADF2, (q31_t)0x8B76A8E4, + (q31_t)0xCB0DE658, (q31_t)0x8B8B7C8F, (q31_t)0xCAE026E8, + (q31_t)0x8BA0622F, (q31_t)0xCAB26FA9, (q31_t)0x8BB559C1, + (q31_t)0xCA84C0A2, (q31_t)0x8BCA6342, (q31_t)0xCA5719DB, + (q31_t)0x8BDF7EAF, (q31_t)0xCA297B5A, (q31_t)0x8BF4AC05, + (q31_t)0xC9FBE527, (q31_t)0x8C09EB40, (q31_t)0xC9CE5748, + (q31_t)0x8C1F3C5C, (q31_t)0xC9A0D1C4, (q31_t)0x8C349F58, + (q31_t)0xC97354A3, (q31_t)0x8C4A142F, (q31_t)0xC945DFEC, + (q31_t)0x8C5F9ADD, (q31_t)0xC91873A5, (q31_t)0x8C753361, + (q31_t)0xC8EB0FD6, (q31_t)0x8C8ADDB6, (q31_t)0xC8BDB485, + (q31_t)0x8CA099D9, (q31_t)0xC89061BA, (q31_t)0x8CB667C7, + (q31_t)0xC863177B, (q31_t)0x8CCC477D, (q31_t)0xC835D5D0, + (q31_t)0x8CE238F6, (q31_t)0xC8089CBF, (q31_t)0x8CF83C30, + (q31_t)0xC7DB6C50, (q31_t)0x8D0E5127, (q31_t)0xC7AE4489, + (q31_t)0x8D2477D8, (q31_t)0xC7812571, (q31_t)0x8D3AB03F, + (q31_t)0xC7540F10, (q31_t)0x8D50FA59, (q31_t)0xC727016C, + (q31_t)0x8D675623, (q31_t)0xC6F9FC8D, (q31_t)0x8D7DC399, + (q31_t)0xC6CD0079, (q31_t)0x8D9442B7, (q31_t)0xC6A00D36, + (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8DC175E0, + (q31_t)0xC6464144, (q31_t)0x8DD829E4, (q31_t)0xC61968A2, + (q31_t)0x8DEEEF82, (q31_t)0xC5EC98ED, (q31_t)0x8E05C6B7, + (q31_t)0xC5BFD22E, (q31_t)0x8E1CAF80, (q31_t)0xC593146A, + (q31_t)0x8E33A9D9, (q31_t)0xC5665FA8, (q31_t)0x8E4AB5BF, + (q31_t)0xC539B3F0, (q31_t)0x8E61D32D, (q31_t)0xC50D1148, + (q31_t)0x8E790222, (q31_t)0xC4E077B8, (q31_t)0x8E904298, + (q31_t)0xC4B3E746, (q31_t)0x8EA7948C, (q31_t)0xC4875FF8, + (q31_t)0x8EBEF7FB, (q31_t)0xC45AE1D7, (q31_t)0x8ED66CE1, + (q31_t)0xC42E6CE8, (q31_t)0x8EEDF33B, (q31_t)0xC4020132, + (q31_t)0x8F058B04, (q31_t)0xC3D59EBD, (q31_t)0x8F1D343A, + (q31_t)0xC3A9458F, (q31_t)0x8F34EED8, (q31_t)0xC37CF5B0, + (q31_t)0x8F4CBADB, (q31_t)0xC350AF25, (q31_t)0x8F64983F, + (q31_t)0xC32471F6, (q31_t)0x8F7C8701, (q31_t)0xC2F83E2A, + (q31_t)0x8F94871D, (q31_t)0xC2CC13C7, (q31_t)0x8FAC988E, + (q31_t)0xC29FF2D4, (q31_t)0x8FC4BB53, (q31_t)0xC273DB58, + (q31_t)0x8FDCEF66, (q31_t)0xC247CD5A, (q31_t)0x8FF534C4, + (q31_t)0xC21BC8E0, (q31_t)0x900D8B69, (q31_t)0xC1EFCDF2, + (q31_t)0x9025F352, (q31_t)0xC1C3DC96, (q31_t)0x903E6C7A, + (q31_t)0xC197F4D3, (q31_t)0x9056F6DF, (q31_t)0xC16C16B0, + (q31_t)0x906F927B, (q31_t)0xC1404233, (q31_t)0x90883F4C, + (q31_t)0xC1147763, (q31_t)0x90A0FD4E, (q31_t)0xC0E8B648, + (q31_t)0x90B9CC7C, (q31_t)0xC0BCFEE7, (q31_t)0x90D2ACD3, + (q31_t)0xC0915147, (q31_t)0x90EB9E50, (q31_t)0xC065AD70, + (q31_t)0x9104A0ED, (q31_t)0xC03A1368, (q31_t)0x911DB4A8, + (q31_t)0xC00E8335, (q31_t)0x9136D97D, (q31_t)0xBFE2FCDF, + (q31_t)0x91500F67, (q31_t)0xBFB7806C, (q31_t)0x91695663, + (q31_t)0xBF8C0DE2, (q31_t)0x9182AE6C, (q31_t)0xBF60A54A, + (q31_t)0x919C1780, (q31_t)0xBF3546A8, (q31_t)0x91B5919A, + (q31_t)0xBF09F204, (q31_t)0x91CF1CB6, (q31_t)0xBEDEA765, + (q31_t)0x91E8B8D0, (q31_t)0xBEB366D1, (q31_t)0x920265E4, + (q31_t)0xBE88304F, (q31_t)0x921C23EE, (q31_t)0xBE5D03E5, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x924FD2D6, + (q31_t)0xBE06C977, (q31_t)0x9269C3AC, (q31_t)0xBDDBBB7F, + (q31_t)0x9283C567, (q31_t)0xBDB0B7BA, (q31_t)0x929DD805, + (q31_t)0xBD85BE2F, (q31_t)0x92B7FB82, (q31_t)0xBD5ACEE5, + (q31_t)0x92D22FD8, (q31_t)0xBD2FE9E1, (q31_t)0x92EC7505, + (q31_t)0xBD050F2C, (q31_t)0x9306CB04, (q31_t)0xBCDA3ECA, + (q31_t)0x932131D1, (q31_t)0xBCAF78C3, (q31_t)0x933BA968, + (q31_t)0xBC84BD1E, (q31_t)0x935631C5, (q31_t)0xBC5A0BE1, + (q31_t)0x9370CAE4, (q31_t)0xBC2F6513, (q31_t)0x938B74C0, + (q31_t)0xBC04C8BA, (q31_t)0x93A62F56, (q31_t)0xBBDA36DC, + (q31_t)0x93C0FAA2, (q31_t)0xBBAFAF81, (q31_t)0x93DBD69F, + (q31_t)0xBB8532AF, (q31_t)0x93F6C34A, (q31_t)0xBB5AC06C, + (q31_t)0x9411C09D, (q31_t)0xBB3058C0, (q31_t)0x942CCE95, + (q31_t)0xBB05FBB0, (q31_t)0x9447ED2F, (q31_t)0xBADBA943, + (q31_t)0x94631C64, (q31_t)0xBAB1617F, (q31_t)0x947E5C32, + (q31_t)0xBA87246C, (q31_t)0x9499AC95, (q31_t)0xBA5CF210, + (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x94D07F05, + (q31_t)0xBA08AD94, (q31_t)0x94EC010B, (q31_t)0xB9DE9B83, + (q31_t)0x95079393, (q31_t)0xB9B49442, (q31_t)0x9523369B, + (q31_t)0xB98A97D8, (q31_t)0x953EEA1E, (q31_t)0xB960A64B, + (q31_t)0x955AAE17, (q31_t)0xB936BFA3, (q31_t)0x95768282, + (q31_t)0xB90CE3E6, (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0x95AE5C9E, (q31_t)0xB8B94D44, (q31_t)0x95CA6246, + (q31_t)0xB88F926C, (q31_t)0x95E6784F, (q31_t)0xB865E299, + (q31_t)0x96029EB5, (q31_t)0xB83C3DD1, (q31_t)0x961ED573, + (q31_t)0xB812A419, (q31_t)0x963B1C85, (q31_t)0xB7E9157A, + (q31_t)0x965773E7, (q31_t)0xB7BF91F8, (q31_t)0x9673DB94, + (q31_t)0xB796199B, (q31_t)0x96905387, (q31_t)0xB76CAC68, + (q31_t)0x96ACDBBD, (q31_t)0xB7434A67, (q31_t)0x96C97431, + (q31_t)0xB719F39D, (q31_t)0x96E61CDF, (q31_t)0xB6F0A811, + (q31_t)0x9702D5C2, (q31_t)0xB6C767CA, (q31_t)0x971F9ED6, + (q31_t)0xB69E32CD, (q31_t)0x973C7816, (q31_t)0xB6750921, + (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x97765B0A, + (q31_t)0xB622D7D5, (q31_t)0x979364B5, (q31_t)0xB5F9D042, + (q31_t)0x97B07E7A, (q31_t)0xB5D0D41A, (q31_t)0x97CDA855, + (q31_t)0xB5A7E362, (q31_t)0x97EAE241, (q31_t)0xB57EFE21, + (q31_t)0x98082C3B, (q31_t)0xB556245E, (q31_t)0x9825863D, + (q31_t)0xB52D561E, (q31_t)0x9842F043, (q31_t)0xB5049368, + (q31_t)0x98606A48, (q31_t)0xB4DBDC42, (q31_t)0x987DF449, + (q31_t)0xB4B330B2, (q31_t)0x989B8E3F, (q31_t)0xB48A90C0, + (q31_t)0x98B93828, (q31_t)0xB461FC70, (q31_t)0x98D6F1FE, + (q31_t)0xB43973C9, (q31_t)0x98F4BBBC, (q31_t)0xB410F6D2, + (q31_t)0x9912955E, (q31_t)0xB3E88591, (q31_t)0x99307EE0, + (q31_t)0xB3C0200C, (q31_t)0x994E783C, (q31_t)0xB397C649, + (q31_t)0x996C816F, (q31_t)0xB36F784E, (q31_t)0x998A9A73, + (q31_t)0xB3473622, (q31_t)0x99A8C344, (q31_t)0xB31EFFCB, + (q31_t)0x99C6FBDE, (q31_t)0xB2F6D54F, (q31_t)0x99E5443A, + (q31_t)0xB2CEB6B5, (q31_t)0x9A039C56, (q31_t)0xB2A6A401, + (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9A407BB8, + (q31_t)0xB256A26A, (q31_t)0x9A5F02F5, (q31_t)0xB22EB392, + (q31_t)0x9A7D99DD, (q31_t)0xB206D0BA, (q31_t)0x9A9C406D, + (q31_t)0xB1DEF9E8, (q31_t)0x9ABAF6A0, (q31_t)0xB1B72F23, + (q31_t)0x9AD9BC71, (q31_t)0xB18F7070, (q31_t)0x9AF891DB, + (q31_t)0xB167BDD6, (q31_t)0x9B1776D9, (q31_t)0xB140175B, + (q31_t)0x9B366B67, (q31_t)0xB1187D05, (q31_t)0x9B556F80, + (q31_t)0xB0F0EEDA, (q31_t)0x9B748320, (q31_t)0xB0C96CDF, + (q31_t)0x9B93A640, (q31_t)0xB0A1F71C, (q31_t)0x9BB2D8DD, + (q31_t)0xB07A8D97, (q31_t)0x9BD21AF2, (q31_t)0xB0533055, + (q31_t)0x9BF16C7A, (q31_t)0xB02BDF5C, (q31_t)0x9C10CD70, + (q31_t)0xB0049AB2, (q31_t)0x9C303DCF, (q31_t)0xAFDD625F, + (q31_t)0x9C4FBD92, (q31_t)0xAFB63667, (q31_t)0x9C6F4CB5, + (q31_t)0xAF8F16D0, (q31_t)0x9C8EEB33, (q31_t)0xAF6803A1, + (q31_t)0x9CAE9907, (q31_t)0xAF40FCE0, (q31_t)0x9CCE562B, + (q31_t)0xAF1A0293, (q31_t)0x9CEE229C, (q31_t)0xAEF314BF, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9D2DE94D, + (q31_t)0xAEA55E9D, (q31_t)0x9D4DE384, (q31_t)0xAE7E965B, + (q31_t)0x9D6DECF4, (q31_t)0xAE57DAAA, (q31_t)0x9D8E0596, + (q31_t)0xAE312B91, (q31_t)0x9DAE2D68, (q31_t)0xAE0A8916, + (q31_t)0x9DCE6462, (q31_t)0xADE3F33E, (q31_t)0x9DEEAA82, + (q31_t)0xADBD6A10, (q31_t)0x9E0EFFC1, (q31_t)0xAD96ED91, + (q31_t)0x9E2F641A, (q31_t)0xAD707DC8, (q31_t)0x9E4FD789, + (q31_t)0xAD4A1ABA, (q31_t)0x9E705A09, (q31_t)0xAD23C46D, + (q31_t)0x9E90EB94, (q31_t)0xACFD7AE8, (q31_t)0x9EB18C26, + (q31_t)0xACD73E30, (q31_t)0x9ED23BB9, (q31_t)0xACB10E4A, + (q31_t)0x9EF2FA48, (q31_t)0xAC8AEB3E, (q31_t)0x9F13C7D0, + (q31_t)0xAC64D510, (q31_t)0x9F34A449, (q31_t)0xAC3ECBC7, + (q31_t)0x9F558FB0, (q31_t)0xAC18CF68, (q31_t)0x9F7689FF, + (q31_t)0xABF2DFFA, (q31_t)0x9F979331, (q31_t)0xABCCFD82, + (q31_t)0x9FB8AB41, (q31_t)0xABA72806, (q31_t)0x9FD9D22A, + (q31_t)0xAB815F8C, (q31_t)0x9FFB07E7, (q31_t)0xAB5BA41A, + (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA03D9FC7, + (q31_t)0xAB105464, (q31_t)0xA05F01E1, (q31_t)0xAAEAC02B, + (q31_t)0xA08072BA, (q31_t)0xAAC53912, (q31_t)0xA0A1F24C, + (q31_t)0xAA9FBF1D, (q31_t)0xA0C38094, (q31_t)0xAA7A5253, + (q31_t)0xA0E51D8C, (q31_t)0xAA54F2B9, (q31_t)0xA106C92E, + (q31_t)0xAA2FA055, (q31_t)0xA1288376, (q31_t)0xAA0A5B2D, + (q31_t)0xA14A4C5E, (q31_t)0xA9E52347, (q31_t)0xA16C23E1, + (q31_t)0xA9BFF8A8, (q31_t)0xA18E09F9, (q31_t)0xA99ADB56, + (q31_t)0xA1AFFEA2, (q31_t)0xA975CB56, (q31_t)0xA1D201D7, + (q31_t)0xA950C8AF, (q31_t)0xA1F41391, (q31_t)0xA92BD366, + (q31_t)0xA21633CD, (q31_t)0xA906EB81, (q31_t)0xA2386283, + (q31_t)0xA8E21106, (q31_t)0xA25A9FB1, (q31_t)0xA8BD43FA, + (q31_t)0xA27CEB4F, (q31_t)0xA8988463, (q31_t)0xA29F4559, + (q31_t)0xA873D246, (q31_t)0xA2C1ADC9, (q31_t)0xA84F2DA9, + (q31_t)0xA2E4249A, (q31_t)0xA82A9693, (q31_t)0xA306A9C7, + (q31_t)0xA8060D08, (q31_t)0xA3293D4B, (q31_t)0xA7E1910E, + (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA36E8F40, + (q31_t)0xA798C1E4, (q31_t)0xA3914DA7, (q31_t)0xA7746EC0, + (q31_t)0xA3B41A4F, (q31_t)0xA7502943, (q31_t)0xA3D6F533, + (q31_t)0xA72BF173, (q31_t)0xA3F9DE4D, (q31_t)0xA707C756, + (q31_t)0xA41CD598, (q31_t)0xA6E3AAF2, (q31_t)0xA43FDB0F, + (q31_t)0xA6BF9C4B, (q31_t)0xA462EEAC, (q31_t)0xA69B9B68, + (q31_t)0xA4861069, (q31_t)0xA677A84E, (q31_t)0xA4A94042, + (q31_t)0xA653C302, (q31_t)0xA4CC7E31, (q31_t)0xA62FEB8B, + (q31_t)0xA4EFCA31, (q31_t)0xA60C21ED, (q31_t)0xA513243B, + (q31_t)0xA5E8662F, (q31_t)0xA5368C4B, (q31_t)0xA5C4B855, + (q31_t)0xA55A025B, (q31_t)0xA5A11865, (q31_t)0xA57D8666, + (q31_t)0xA57D8666, (q31_t)0xA5A11865, (q31_t)0xA55A025B, + (q31_t)0xA5C4B855, (q31_t)0xA5368C4B, (q31_t)0xA5E8662F, + (q31_t)0xA513243B, (q31_t)0xA60C21ED, (q31_t)0xA4EFCA31, + (q31_t)0xA62FEB8B, (q31_t)0xA4CC7E31, (q31_t)0xA653C302, + (q31_t)0xA4A94042, (q31_t)0xA677A84E, (q31_t)0xA4861069, + (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA6BF9C4B, + (q31_t)0xA43FDB0F, (q31_t)0xA6E3AAF2, (q31_t)0xA41CD598, + (q31_t)0xA707C756, (q31_t)0xA3F9DE4D, (q31_t)0xA72BF173, + (q31_t)0xA3D6F533, (q31_t)0xA7502943, (q31_t)0xA3B41A4F, + (q31_t)0xA7746EC0, (q31_t)0xA3914DA7, (q31_t)0xA798C1E4, + (q31_t)0xA36E8F40, (q31_t)0xA7BD22AB, (q31_t)0xA34BDF20, + (q31_t)0xA7E1910E, (q31_t)0xA3293D4B, (q31_t)0xA8060D08, + (q31_t)0xA306A9C7, (q31_t)0xA82A9693, (q31_t)0xA2E4249A, + (q31_t)0xA84F2DA9, (q31_t)0xA2C1ADC9, (q31_t)0xA873D246, + (q31_t)0xA29F4559, (q31_t)0xA8988463, (q31_t)0xA27CEB4F, + (q31_t)0xA8BD43FA, (q31_t)0xA25A9FB1, (q31_t)0xA8E21106, + (q31_t)0xA2386283, (q31_t)0xA906EB81, (q31_t)0xA21633CD, + (q31_t)0xA92BD366, (q31_t)0xA1F41391, (q31_t)0xA950C8AF, + (q31_t)0xA1D201D7, (q31_t)0xA975CB56, (q31_t)0xA1AFFEA2, + (q31_t)0xA99ADB56, (q31_t)0xA18E09F9, (q31_t)0xA9BFF8A8, + (q31_t)0xA16C23E1, (q31_t)0xA9E52347, (q31_t)0xA14A4C5E, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAA2FA055, + (q31_t)0xA106C92E, (q31_t)0xAA54F2B9, (q31_t)0xA0E51D8C, + (q31_t)0xAA7A5253, (q31_t)0xA0C38094, (q31_t)0xAA9FBF1D, + (q31_t)0xA0A1F24C, (q31_t)0xAAC53912, (q31_t)0xA08072BA, + (q31_t)0xAAEAC02B, (q31_t)0xA05F01E1, (q31_t)0xAB105464, + (q31_t)0xA03D9FC7, (q31_t)0xAB35F5B5, (q31_t)0xA01C4C72, + (q31_t)0xAB5BA41A, (q31_t)0x9FFB07E7, (q31_t)0xAB815F8C, + (q31_t)0x9FD9D22A, (q31_t)0xABA72806, (q31_t)0x9FB8AB41, + (q31_t)0xABCCFD82, (q31_t)0x9F979331, (q31_t)0xABF2DFFA, + (q31_t)0x9F7689FF, (q31_t)0xAC18CF68, (q31_t)0x9F558FB0, + (q31_t)0xAC3ECBC7, (q31_t)0x9F34A449, (q31_t)0xAC64D510, + (q31_t)0x9F13C7D0, (q31_t)0xAC8AEB3E, (q31_t)0x9EF2FA48, + (q31_t)0xACB10E4A, (q31_t)0x9ED23BB9, (q31_t)0xACD73E30, + (q31_t)0x9EB18C26, (q31_t)0xACFD7AE8, (q31_t)0x9E90EB94, + (q31_t)0xAD23C46D, (q31_t)0x9E705A09, (q31_t)0xAD4A1ABA, + (q31_t)0x9E4FD789, (q31_t)0xAD707DC8, (q31_t)0x9E2F641A, + (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xADBD6A10, + (q31_t)0x9DEEAA82, (q31_t)0xADE3F33E, (q31_t)0x9DCE6462, + (q31_t)0xAE0A8916, (q31_t)0x9DAE2D68, (q31_t)0xAE312B91, + (q31_t)0x9D8E0596, (q31_t)0xAE57DAAA, (q31_t)0x9D6DECF4, + (q31_t)0xAE7E965B, (q31_t)0x9D4DE384, (q31_t)0xAEA55E9D, + (q31_t)0x9D2DE94D, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53, + (q31_t)0xAEF314BF, (q31_t)0x9CEE229C, (q31_t)0xAF1A0293, + (q31_t)0x9CCE562B, (q31_t)0xAF40FCE0, (q31_t)0x9CAE9907, + (q31_t)0xAF6803A1, (q31_t)0x9C8EEB33, (q31_t)0xAF8F16D0, + (q31_t)0x9C6F4CB5, (q31_t)0xAFB63667, (q31_t)0x9C4FBD92, + (q31_t)0xAFDD625F, (q31_t)0x9C303DCF, (q31_t)0xB0049AB2, + (q31_t)0x9C10CD70, (q31_t)0xB02BDF5C, (q31_t)0x9BF16C7A, + (q31_t)0xB0533055, (q31_t)0x9BD21AF2, (q31_t)0xB07A8D97, + (q31_t)0x9BB2D8DD, (q31_t)0xB0A1F71C, (q31_t)0x9B93A640, + (q31_t)0xB0C96CDF, (q31_t)0x9B748320, (q31_t)0xB0F0EEDA, + (q31_t)0x9B556F80, (q31_t)0xB1187D05, (q31_t)0x9B366B67, + (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB167BDD6, + (q31_t)0x9AF891DB, (q31_t)0xB18F7070, (q31_t)0x9AD9BC71, + (q31_t)0xB1B72F23, (q31_t)0x9ABAF6A0, (q31_t)0xB1DEF9E8, + (q31_t)0x9A9C406D, (q31_t)0xB206D0BA, (q31_t)0x9A7D99DD, + (q31_t)0xB22EB392, (q31_t)0x9A5F02F5, (q31_t)0xB256A26A, + (q31_t)0x9A407BB8, (q31_t)0xB27E9D3B, (q31_t)0x9A22042C, + (q31_t)0xB2A6A401, (q31_t)0x9A039C56, (q31_t)0xB2CEB6B5, + (q31_t)0x99E5443A, (q31_t)0xB2F6D54F, (q31_t)0x99C6FBDE, + (q31_t)0xB31EFFCB, (q31_t)0x99A8C344, (q31_t)0xB3473622, + (q31_t)0x998A9A73, (q31_t)0xB36F784E, (q31_t)0x996C816F, + (q31_t)0xB397C649, (q31_t)0x994E783C, (q31_t)0xB3C0200C, + (q31_t)0x99307EE0, (q31_t)0xB3E88591, (q31_t)0x9912955E, + (q31_t)0xB410F6D2, (q31_t)0x98F4BBBC, (q31_t)0xB43973C9, + (q31_t)0x98D6F1FE, (q31_t)0xB461FC70, (q31_t)0x98B93828, + (q31_t)0xB48A90C0, (q31_t)0x989B8E3F, (q31_t)0xB4B330B2, + (q31_t)0x987DF449, (q31_t)0xB4DBDC42, (q31_t)0x98606A48, + (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB52D561E, + (q31_t)0x9825863D, (q31_t)0xB556245E, (q31_t)0x98082C3B, + (q31_t)0xB57EFE21, (q31_t)0x97EAE241, (q31_t)0xB5A7E362, + (q31_t)0x97CDA855, (q31_t)0xB5D0D41A, (q31_t)0x97B07E7A, + (q31_t)0xB5F9D042, (q31_t)0x979364B5, (q31_t)0xB622D7D5, + (q31_t)0x97765B0A, (q31_t)0xB64BEACC, (q31_t)0x9759617E, + (q31_t)0xB6750921, (q31_t)0x973C7816, (q31_t)0xB69E32CD, + (q31_t)0x971F9ED6, (q31_t)0xB6C767CA, (q31_t)0x9702D5C2, + (q31_t)0xB6F0A811, (q31_t)0x96E61CDF, (q31_t)0xB719F39D, + (q31_t)0x96C97431, (q31_t)0xB7434A67, (q31_t)0x96ACDBBD, + (q31_t)0xB76CAC68, (q31_t)0x96905387, (q31_t)0xB796199B, + (q31_t)0x9673DB94, (q31_t)0xB7BF91F8, (q31_t)0x965773E7, + (q31_t)0xB7E9157A, (q31_t)0x963B1C85, (q31_t)0xB812A419, + (q31_t)0x961ED573, (q31_t)0xB83C3DD1, (q31_t)0x96029EB5, + (q31_t)0xB865E299, (q31_t)0x95E6784F, (q31_t)0xB88F926C, + (q31_t)0x95CA6246, (q31_t)0xB8B94D44, (q31_t)0x95AE5C9E, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xB90CE3E6, + (q31_t)0x95768282, (q31_t)0xB936BFA3, (q31_t)0x955AAE17, + (q31_t)0xB960A64B, (q31_t)0x953EEA1E, (q31_t)0xB98A97D8, + (q31_t)0x9523369B, (q31_t)0xB9B49442, (q31_t)0x95079393, + (q31_t)0xB9DE9B83, (q31_t)0x94EC010B, (q31_t)0xBA08AD94, + (q31_t)0x94D07F05, (q31_t)0xBA32CA70, (q31_t)0x94B50D87, + (q31_t)0xBA5CF210, (q31_t)0x9499AC95, (q31_t)0xBA87246C, + (q31_t)0x947E5C32, (q31_t)0xBAB1617F, (q31_t)0x94631C64, + (q31_t)0xBADBA943, (q31_t)0x9447ED2F, (q31_t)0xBB05FBB0, + (q31_t)0x942CCE95, (q31_t)0xBB3058C0, (q31_t)0x9411C09D, + (q31_t)0xBB5AC06C, (q31_t)0x93F6C34A, (q31_t)0xBB8532AF, + (q31_t)0x93DBD69F, (q31_t)0xBBAFAF81, (q31_t)0x93C0FAA2, + (q31_t)0xBBDA36DC, (q31_t)0x93A62F56, (q31_t)0xBC04C8BA, + (q31_t)0x938B74C0, (q31_t)0xBC2F6513, (q31_t)0x9370CAE4, + (q31_t)0xBC5A0BE1, (q31_t)0x935631C5, (q31_t)0xBC84BD1E, + (q31_t)0x933BA968, (q31_t)0xBCAF78C3, (q31_t)0x932131D1, + (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBD050F2C, + (q31_t)0x92EC7505, (q31_t)0xBD2FE9E1, (q31_t)0x92D22FD8, + (q31_t)0xBD5ACEE5, (q31_t)0x92B7FB82, (q31_t)0xBD85BE2F, + (q31_t)0x929DD805, (q31_t)0xBDB0B7BA, (q31_t)0x9283C567, + (q31_t)0xBDDBBB7F, (q31_t)0x9269C3AC, (q31_t)0xBE06C977, + (q31_t)0x924FD2D6, (q31_t)0xBE31E19B, (q31_t)0x9235F2EB, + (q31_t)0xBE5D03E5, (q31_t)0x921C23EE, (q31_t)0xBE88304F, + (q31_t)0x920265E4, (q31_t)0xBEB366D1, (q31_t)0x91E8B8D0, + (q31_t)0xBEDEA765, (q31_t)0x91CF1CB6, (q31_t)0xBF09F204, + (q31_t)0x91B5919A, (q31_t)0xBF3546A8, (q31_t)0x919C1780, + (q31_t)0xBF60A54A, (q31_t)0x9182AE6C, (q31_t)0xBF8C0DE2, + (q31_t)0x91695663, (q31_t)0xBFB7806C, (q31_t)0x91500F67, + (q31_t)0xBFE2FCDF, (q31_t)0x9136D97D, (q31_t)0xC00E8335, + (q31_t)0x911DB4A8, (q31_t)0xC03A1368, (q31_t)0x9104A0ED, + (q31_t)0xC065AD70, (q31_t)0x90EB9E50, (q31_t)0xC0915147, + (q31_t)0x90D2ACD3, (q31_t)0xC0BCFEE7, (q31_t)0x90B9CC7C, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC1147763, + (q31_t)0x90883F4C, (q31_t)0xC1404233, (q31_t)0x906F927B, + (q31_t)0xC16C16B0, (q31_t)0x9056F6DF, (q31_t)0xC197F4D3, + (q31_t)0x903E6C7A, (q31_t)0xC1C3DC96, (q31_t)0x9025F352, + (q31_t)0xC1EFCDF2, (q31_t)0x900D8B69, (q31_t)0xC21BC8E0, + (q31_t)0x8FF534C4, (q31_t)0xC247CD5A, (q31_t)0x8FDCEF66, + (q31_t)0xC273DB58, (q31_t)0x8FC4BB53, (q31_t)0xC29FF2D4, + (q31_t)0x8FAC988E, (q31_t)0xC2CC13C7, (q31_t)0x8F94871D, + (q31_t)0xC2F83E2A, (q31_t)0x8F7C8701, (q31_t)0xC32471F6, + (q31_t)0x8F64983F, (q31_t)0xC350AF25, (q31_t)0x8F4CBADB, + (q31_t)0xC37CF5B0, (q31_t)0x8F34EED8, (q31_t)0xC3A9458F, + (q31_t)0x8F1D343A, (q31_t)0xC3D59EBD, (q31_t)0x8F058B04, + (q31_t)0xC4020132, (q31_t)0x8EEDF33B, (q31_t)0xC42E6CE8, + (q31_t)0x8ED66CE1, (q31_t)0xC45AE1D7, (q31_t)0x8EBEF7FB, + (q31_t)0xC4875FF8, (q31_t)0x8EA7948C, (q31_t)0xC4B3E746, + (q31_t)0x8E904298, (q31_t)0xC4E077B8, (q31_t)0x8E790222, + (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC539B3F0, + (q31_t)0x8E4AB5BF, (q31_t)0xC5665FA8, (q31_t)0x8E33A9D9, + (q31_t)0xC593146A, (q31_t)0x8E1CAF80, (q31_t)0xC5BFD22E, + (q31_t)0x8E05C6B7, (q31_t)0xC5EC98ED, (q31_t)0x8DEEEF82, + (q31_t)0xC61968A2, (q31_t)0x8DD829E4, (q31_t)0xC6464144, + (q31_t)0x8DC175E0, (q31_t)0xC67322CD, (q31_t)0x8DAAD37B, + (q31_t)0xC6A00D36, (q31_t)0x8D9442B7, (q31_t)0xC6CD0079, + (q31_t)0x8D7DC399, (q31_t)0xC6F9FC8D, (q31_t)0x8D675623, + (q31_t)0xC727016C, (q31_t)0x8D50FA59, (q31_t)0xC7540F10, + (q31_t)0x8D3AB03F, (q31_t)0xC7812571, (q31_t)0x8D2477D8, + (q31_t)0xC7AE4489, (q31_t)0x8D0E5127, (q31_t)0xC7DB6C50, + (q31_t)0x8CF83C30, (q31_t)0xC8089CBF, (q31_t)0x8CE238F6, + (q31_t)0xC835D5D0, (q31_t)0x8CCC477D, (q31_t)0xC863177B, + (q31_t)0x8CB667C7, (q31_t)0xC89061BA, (q31_t)0x8CA099D9, + (q31_t)0xC8BDB485, (q31_t)0x8C8ADDB6, (q31_t)0xC8EB0FD6, + (q31_t)0x8C753361, (q31_t)0xC91873A5, (q31_t)0x8C5F9ADD, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xC97354A3, + (q31_t)0x8C349F58, (q31_t)0xC9A0D1C4, (q31_t)0x8C1F3C5C, + (q31_t)0xC9CE5748, (q31_t)0x8C09EB40, (q31_t)0xC9FBE527, + (q31_t)0x8BF4AC05, (q31_t)0xCA297B5A, (q31_t)0x8BDF7EAF, + (q31_t)0xCA5719DB, (q31_t)0x8BCA6342, (q31_t)0xCA84C0A2, + (q31_t)0x8BB559C1, (q31_t)0xCAB26FA9, (q31_t)0x8BA0622F, + (q31_t)0xCAE026E8, (q31_t)0x8B8B7C8F, (q31_t)0xCB0DE658, + (q31_t)0x8B76A8E4, (q31_t)0xCB3BADF2, (q31_t)0x8B61E732, + (q31_t)0xCB697DB0, (q31_t)0x8B4D377C, (q31_t)0xCB975589, + (q31_t)0x8B3899C5, (q31_t)0xCBC53578, (q31_t)0x8B240E10, + (q31_t)0xCBF31D75, (q31_t)0x8B0F9461, (q31_t)0xCC210D78, + (q31_t)0x8AFB2CBA, (q31_t)0xCC4F057B, (q31_t)0x8AE6D71F, + (q31_t)0xCC7D0577, (q31_t)0x8AD29393, (q31_t)0xCCAB0D65, + (q31_t)0x8ABE6219, (q31_t)0xCCD91D3D, (q31_t)0x8AAA42B4, + (q31_t)0xCD0734F8, (q31_t)0x8A963567, (q31_t)0xCD355490, + (q31_t)0x8A823A35, (q31_t)0xCD637BFD, (q31_t)0x8A6E5122, + (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCDBFE23A, + (q31_t)0x8A46B563, (q31_t)0xCDEE20FC, (q31_t)0x8A3302BD, + (q31_t)0xCE1C6776, (q31_t)0x8A1F6242, (q31_t)0xCE4AB5A2, + (q31_t)0x8A0BD3F5, (q31_t)0xCE790B78, (q31_t)0x89F857D8, + (q31_t)0xCEA768F2, (q31_t)0x89E4EDEE, (q31_t)0xCED5CE08, + (q31_t)0x89D1963C, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xCF32AEEB, (q31_t)0x89AB1D86, (q31_t)0xCF612AAA, + (q31_t)0x8997FC89, (q31_t)0xCF8FADE8, (q31_t)0x8984EDCF, + (q31_t)0xCFBE389F, (q31_t)0x8971F15A, (q31_t)0xCFECCAC7, + (q31_t)0x895F072D, (q31_t)0xD01B6459, (q31_t)0x894C2F4C, + (q31_t)0xD04A054D, (q31_t)0x893969B9, (q31_t)0xD078AD9D, + (q31_t)0x8926B677, (q31_t)0xD0A75D42, (q31_t)0x89141589, + (q31_t)0xD0D61433, (q31_t)0x890186F1, (q31_t)0xD104D26B, + (q31_t)0x88EF0AB4, (q31_t)0xD13397E1, (q31_t)0x88DCA0D3, + (q31_t)0xD162648F, (q31_t)0x88CA4951, (q31_t)0xD191386D, + (q31_t)0x88B80431, (q31_t)0xD1C01374, (q31_t)0x88A5D177, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD21DDEE1, + (q31_t)0x8881A33C, (q31_t)0xD24CCF38, (q31_t)0x886FA7C2, + (q31_t)0xD27BC69C, (q31_t)0x885DBEB7, (q31_t)0xD2AAC504, + (q31_t)0x884BE820, (q31_t)0xD2D9CA6A, (q31_t)0x883A23FE, + (q31_t)0xD308D6C6, (q31_t)0x88287255, (q31_t)0xD337EA12, + (q31_t)0x8816D327, (q31_t)0xD3670445, (q31_t)0x88054677, + (q31_t)0xD3962559, (q31_t)0x87F3CC47, (q31_t)0xD3C54D46, + (q31_t)0x87E2649B, (q31_t)0xD3F47C06, (q31_t)0x87D10F75, + (q31_t)0xD423B190, (q31_t)0x87BFCCD7, (q31_t)0xD452EDDE, + (q31_t)0x87AE9CC5, (q31_t)0xD48230E8, (q31_t)0x879D7F40, + (q31_t)0xD4B17AA7, (q31_t)0x878C744C, (q31_t)0xD4E0CB14, + (q31_t)0x877B7BEC, (q31_t)0xD5102227, (q31_t)0x876A9621, + (q31_t)0xD53F7FDA, (q31_t)0x8759C2EF, (q31_t)0xD56EE424, + (q31_t)0x87490257, (q31_t)0xD59E4EFE, (q31_t)0x8738545E, + (q31_t)0xD5CDC062, (q31_t)0x8727B904, (q31_t)0xD5FD3847, + (q31_t)0x8717304E, (q31_t)0xD62CB6A7, (q31_t)0x8706BA3C, + (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD68BC6BA, + (q31_t)0x86E60614, (q31_t)0xD6BB585D, (q31_t)0x86D5C802, + (q31_t)0xD6EAF05E, (q31_t)0x86C59C9F, (q31_t)0xD71A8EB5, + (q31_t)0x86B583EE, (q31_t)0xD74A335A, (q31_t)0x86A57DF1, + (q31_t)0xD779DE46, (q31_t)0x86958AAB, (q31_t)0xD7A98F73, + (q31_t)0x8685AA1F, (q31_t)0xD7D946D7, (q31_t)0x8675DC4E, + (q31_t)0xD809046D, (q31_t)0x8666213C, (q31_t)0xD838C82D, + (q31_t)0x865678EA, (q31_t)0xD868920F, (q31_t)0x8646E35B, + (q31_t)0xD898620C, (q31_t)0x86376092, (q31_t)0xD8C8381C, + (q31_t)0x8627F090, (q31_t)0xD8F81439, (q31_t)0x86189359, + (q31_t)0xD927F65B, (q31_t)0x860948EE, (q31_t)0xD957DE7A, + (q31_t)0x85FA1152, (q31_t)0xD987CC8F, (q31_t)0x85EAEC88, + (q31_t)0xD9B7C093, (q31_t)0x85DBDA91, (q31_t)0xD9E7BA7E, + (q31_t)0x85CCDB70, (q31_t)0xDA17BA4A, (q31_t)0x85BDEF27, + (q31_t)0xDA47BFED, (q31_t)0x85AF15B9, (q31_t)0xDA77CB62, + (q31_t)0x85A04F28, (q31_t)0xDAA7DCA1, (q31_t)0x85919B75, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDB08105E, + (q31_t)0x85746CB7, (q31_t)0xDB3832CD, (q31_t)0x8565F1B0, + (q31_t)0xDB685AE8, (q31_t)0x85578991, (q31_t)0xDB9888A8, + (q31_t)0x8549345C, (q31_t)0xDBC8BC05, (q31_t)0x853AF214, + (q31_t)0xDBF8F4F8, (q31_t)0x852CC2BA, (q31_t)0xDC293379, + (q31_t)0x851EA652, (q31_t)0xDC597781, (q31_t)0x85109CDC, + (q31_t)0xDC89C108, (q31_t)0x8502A65C, (q31_t)0xDCBA1008, + (q31_t)0x84F4C2D3, (q31_t)0xDCEA6478, (q31_t)0x84E6F244, + (q31_t)0xDD1ABE51, (q31_t)0x84D934B0, (q31_t)0xDD4B1D8B, + (q31_t)0x84CB8A1B, (q31_t)0xDD7B8220, (q31_t)0x84BDF285, + (q31_t)0xDDABEC07, (q31_t)0x84B06DF1, (q31_t)0xDDDC5B3A, + (q31_t)0x84A2FC62, (q31_t)0xDE0CCFB1, (q31_t)0x84959DD9, + (q31_t)0xDE3D4963, (q31_t)0x84885257, (q31_t)0xDE6DC84B, + (q31_t)0x847B19E1, (q31_t)0xDE9E4C60, (q31_t)0x846DF476, + (q31_t)0xDECED59B, (q31_t)0x8460E21A, (q31_t)0xDEFF63F4, + (q31_t)0x8453E2CE, (q31_t)0xDF2FF764, (q31_t)0x8446F695, + (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xDF912D6A, + (q31_t)0x842D5761, (q31_t)0xDFC1CFF2, (q31_t)0x8420A46B, + (q31_t)0xDFF27773, (q31_t)0x8414048F, (q31_t)0xE02323E5, + (q31_t)0x840777CF, (q31_t)0xE053D541, (q31_t)0x83FAFE2E, + (q31_t)0xE0848B7F, (q31_t)0x83EE97AC, (q31_t)0xE0B54698, + (q31_t)0x83E2444D, (q31_t)0xE0E60684, (q31_t)0x83D60411, + (q31_t)0xE116CB3D, (q31_t)0x83C9D6FB, (q31_t)0xE14794B9, + (q31_t)0x83BDBD0D, (q31_t)0xE17862F3, (q31_t)0x83B1B649, + (q31_t)0xE1A935E1, (q31_t)0x83A5C2B0, (q31_t)0xE1DA0D7E, + (q31_t)0x8399E244, (q31_t)0xE20AE9C1, (q31_t)0x838E1507, + (q31_t)0xE23BCAA2, (q31_t)0x83825AFB, (q31_t)0xE26CB01A, + (q31_t)0x8376B422, (q31_t)0xE29D9A22, (q31_t)0x836B207D, + (q31_t)0xE2CE88B2, (q31_t)0x835FA00E, (q31_t)0xE2FF7BC3, + (q31_t)0x835432D8, (q31_t)0xE330734C, (q31_t)0x8348D8DB, + (q31_t)0xE3616F47, (q31_t)0x833D921A, (q31_t)0xE3926FAC, + (q31_t)0x83325E97, (q31_t)0xE3C37473, (q31_t)0x83273E52, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE4258B0A, + (q31_t)0x8311378C, (q31_t)0xE4569CCB, (q31_t)0x8306510F, + (q31_t)0xE487B2CF, (q31_t)0x82FB7DD8, (q31_t)0xE4B8CD10, + (q31_t)0x82F0BDE8, (q31_t)0xE4E9EB86, (q31_t)0x82E61141, + (q31_t)0xE51B0E2A, (q31_t)0x82DB77E5, (q31_t)0xE54C34F3, + (q31_t)0x82D0F1D5, (q31_t)0xE57D5FDA, (q31_t)0x82C67F13, + (q31_t)0xE5AE8ED8, (q31_t)0x82BC1FA1, (q31_t)0xE5DFC1E4, + (q31_t)0x82B1D381, (q31_t)0xE610F8F9, (q31_t)0x82A79AB3, + (q31_t)0xE642340D, (q31_t)0x829D753A, (q31_t)0xE6737319, + (q31_t)0x82936316, (q31_t)0xE6A4B616, (q31_t)0x8289644A, + (q31_t)0xE6D5FCFC, (q31_t)0x827F78D8, (q31_t)0xE70747C3, + (q31_t)0x8275A0C0, (q31_t)0xE7389664, (q31_t)0x826BDC04, + (q31_t)0xE769E8D8, (q31_t)0x82622AA5, (q31_t)0xE79B3F16, + (q31_t)0x82588CA6, (q31_t)0xE7CC9917, (q31_t)0x824F0208, + (q31_t)0xE7FDF6D3, (q31_t)0x82458ACB, (q31_t)0xE82F5844, + (q31_t)0x823C26F2, (q31_t)0xE860BD60, (q31_t)0x8232D67E, + (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xE8C3927F, + (q31_t)0x82206FCB, (q31_t)0xE8F50273, (q31_t)0x8217598F, + (q31_t)0xE92675F4, (q31_t)0x820E56BE, (q31_t)0xE957ECFB, + (q31_t)0x82056758, (q31_t)0xE9896780, (q31_t)0x81FC8B60, + (q31_t)0xE9BAE57C, (q31_t)0x81F3C2D7, (q31_t)0xE9EC66E8, + (q31_t)0x81EB0DBD, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16, + (q31_t)0xEA4F73EE, (q31_t)0x81D9DDE1, (q31_t)0xEA80FF79, + (q31_t)0x81D16320, (q31_t)0xEAB28E55, (q31_t)0x81C8FBD5, + (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEB15B5E0, + (q31_t)0x81B867A4, (q31_t)0xEB474E80, (q31_t)0x81B03AC1, + (q31_t)0xEB78EA52, (q31_t)0x81A82159, (q31_t)0xEBAA894E, + (q31_t)0x81A01B6C, (q31_t)0xEBDC2B6D, (q31_t)0x819828FD, + (q31_t)0xEC0DD0A8, (q31_t)0x81904A0C, (q31_t)0xEC3F78F5, + (q31_t)0x81887E9A, (q31_t)0xEC71244F, (q31_t)0x8180C6A9, + (q31_t)0xECA2D2AC, (q31_t)0x8179223A, (q31_t)0xECD48406, + (q31_t)0x8171914E, (q31_t)0xED063855, (q31_t)0x816A13E6, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xED69A9B2, + (q31_t)0x815B53A8, (q31_t)0xED9B66B2, (q31_t)0x815410D3, + (q31_t)0xEDCD2687, (q31_t)0x814CE188, (q31_t)0xEDFEE92B, + (q31_t)0x8145C5C6, (q31_t)0xEE30AE95, (q31_t)0x813EBD90, + (q31_t)0xEE6276BF, (q31_t)0x8137C8E6, (q31_t)0xEE9441A0, + (q31_t)0x8130E7C8, (q31_t)0xEEC60F31, (q31_t)0x812A1A39, + (q31_t)0xEEF7DF6A, (q31_t)0x81236039, (q31_t)0xEF29B243, + (q31_t)0x811CB9CA, (q31_t)0xEF5B87B5, (q31_t)0x811626EC, + (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xEFBF3A44, + (q31_t)0x81093BE8, (q31_t)0xEFF11752, (q31_t)0x8102E3C3, + (q31_t)0xF022F6DA, (q31_t)0x80FC9F35, (q31_t)0xF054D8D4, + (q31_t)0x80F66E3C, (q31_t)0xF086BD39, (q31_t)0x80F050DB, + (q31_t)0xF0B8A401, (q31_t)0x80EA4712, (q31_t)0xF0EA8D23, + (q31_t)0x80E450E2, (q31_t)0xF11C789A, (q31_t)0x80DE6E4C, + (q31_t)0xF14E665C, (q31_t)0x80D89F51, (q31_t)0xF1805662, + (q31_t)0x80D2E3F1, (q31_t)0xF1B248A5, (q31_t)0x80CD3C2F, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF21633C0, + (q31_t)0x80C22783, (q31_t)0xF2482C89, (q31_t)0x80BCBA9C, + (q31_t)0xF27A2770, (q31_t)0x80B76155, (q31_t)0xF2AC246D, + (q31_t)0x80B21BAF, (q31_t)0xF2DE2378, (q31_t)0x80ACE9AB, + (q31_t)0xF310248A, (q31_t)0x80A7CB49, (q31_t)0xF342279A, + (q31_t)0x80A2C08B, (q31_t)0xF3742CA1, (q31_t)0x809DC970, + (q31_t)0xF3A63398, (q31_t)0x8098E5FB, (q31_t)0xF3D83C76, + (q31_t)0x8094162B, (q31_t)0xF40A4734, (q31_t)0x808F5A02, + (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF46E6231, + (q31_t)0x80861CA5, (q31_t)0xF4A07260, (q31_t)0x80819B74, + (q31_t)0xF4D28451, (q31_t)0x807D2DEB, (q31_t)0xF50497FA, + (q31_t)0x8078D40D, (q31_t)0xF536AD55, (q31_t)0x80748DD9, + (q31_t)0xF568C45A, (q31_t)0x80705B50, (q31_t)0xF59ADD01, + (q31_t)0x806C3C73, (q31_t)0xF5CCF743, (q31_t)0x80683143, + (q31_t)0xF5FF1317, (q31_t)0x806439C0, (q31_t)0xF6313076, + (q31_t)0x806055EA, (q31_t)0xF6634F58, (q31_t)0x805C85C3, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF6C79188, + (q31_t)0x80552083, (q31_t)0xF6F9B4C5, (q31_t)0x80518B6B, + (q31_t)0xF72BD967, (q31_t)0x804E0A03, (q31_t)0xF75DFF65, + (q31_t)0x804A9C4D, (q31_t)0xF79026B8, (q31_t)0x80474248, + (q31_t)0xF7C24F58, (q31_t)0x8043FBF6, (q31_t)0xF7F4793E, + (q31_t)0x8040C956, (q31_t)0xF826A461, (q31_t)0x803DAA69, + (q31_t)0xF858D0BA, (q31_t)0x803A9F31, (q31_t)0xF88AFE41, + (q31_t)0x8037A7AC, (q31_t)0xF8BD2CEF, (q31_t)0x8034C3DC, + (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF9218D9E, + (q31_t)0x802F375C, (q31_t)0xF953BF90, (q31_t)0x802C8EAD, + (q31_t)0xF985F28A, (q31_t)0x8029F9B4, (q31_t)0xF9B82683, + (q31_t)0x80277872, (q31_t)0xF9EA5B75, (q31_t)0x80250AE7, + (q31_t)0xFA1C9156, (q31_t)0x8022B113, (q31_t)0xFA4EC820, + (q31_t)0x80206AF8, (q31_t)0xFA80FFCB, (q31_t)0x801E3894, + (q31_t)0xFAB3384F, (q31_t)0x801C19E9, (q31_t)0xFAE571A4, + (q31_t)0x801A0EF7, (q31_t)0xFB17ABC2, (q31_t)0x801817BF, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFB7C223C, + (q31_t)0x8014647A, (q31_t)0xFBAE5E89, (q31_t)0x8012A86F, + (q31_t)0xFBE09B80, (q31_t)0x8011001E, (q31_t)0xFC12D919, + (q31_t)0x800F6B88, (q31_t)0xFC45174E, (q31_t)0x800DEAAC, + (q31_t)0xFC775616, (q31_t)0x800C7D8C, (q31_t)0xFCA99569, + (q31_t)0x800B2427, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D, + (q31_t)0xFD0E1594, (q31_t)0x8008AC90, (q31_t)0xFD40565B, + (q31_t)0x80078E5E, (q31_t)0xFD72978F, (q31_t)0x800683E8, + (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFDD71B1E, + (q31_t)0x8004AA31, (q31_t)0xFE095D69, (q31_t)0x8003DAF0, + (q31_t)0xFE3BA001, (q31_t)0x80031F6C, (q31_t)0xFE6DE2E0, + (q31_t)0x800277A5, (q31_t)0xFEA025FC, (q31_t)0x8001E39B, + (q31_t)0xFED2694F, (q31_t)0x8001634D, (q31_t)0xFF04ACD0, + (q31_t)0x8000F6BD, (q31_t)0xFF36F078, (q31_t)0x80009DE9, + (q31_t)0xFF69343E, (q31_t)0x800058D3, (q31_t)0xFF9B781D, + (q31_t)0x8000277A, (q31_t)0xFFCDBC0A, (q31_t)0x800009DE +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +/** + @brief q15 Twiddle factors Table +*/ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) + +/** + @par + Example code for q15 Twiddle factors Generation:: + @par +
fori = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 16, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_16_q15[24] = { + (q15_t)0x7FFF, (q15_t)0x0000, + (q15_t)0x7641, (q15_t)0x30FB, + (q15_t)0x5A82, (q15_t)0x5A82, + (q15_t)0x30FB, (q15_t)0x7641, + (q15_t)0x0000, (q15_t)0x7FFF, + (q15_t)0xCF04, (q15_t)0x7641, + (q15_t)0xA57D, (q15_t)0x5A82, + (q15_t)0x89BE, (q15_t)0x30FB, + (q15_t)0x8000, (q15_t)0x0000, + (q15_t)0x89BE, (q15_t)0xCF04, + (q15_t)0xA57D, (q15_t)0xA57D, + (q15_t)0xCF04, (q15_t)0x89BE +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par +
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 32, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_32_q15[48] = { + (q15_t)0x7FFF, (q15_t)0x0000, + (q15_t)0x7D8A, (q15_t)0x18F8, + (q15_t)0x7641, (q15_t)0x30FB, + (q15_t)0x6A6D, (q15_t)0x471C, + (q15_t)0x5A82, (q15_t)0x5A82, + (q15_t)0x471C, (q15_t)0x6A6D, + (q15_t)0x30FB, (q15_t)0x7641, + (q15_t)0x18F8, (q15_t)0x7D8A, + (q15_t)0x0000, (q15_t)0x7FFF, + (q15_t)0xE707, (q15_t)0x7D8A, + (q15_t)0xCF04, (q15_t)0x7641, + (q15_t)0xB8E3, (q15_t)0x6A6D, + (q15_t)0xA57D, (q15_t)0x5A82, + (q15_t)0x9592, (q15_t)0x471C, + (q15_t)0x89BE, (q15_t)0x30FB, + (q15_t)0x8275, (q15_t)0x18F8, + (q15_t)0x8000, (q15_t)0x0000, + (q15_t)0x8275, (q15_t)0xE707, + (q15_t)0x89BE, (q15_t)0xCF04, + (q15_t)0x9592, (q15_t)0xB8E3, + (q15_t)0xA57D, (q15_t)0xA57D, + (q15_t)0xB8E3, (q15_t)0x9592, + (q15_t)0xCF04, (q15_t)0x89BE, + (q15_t)0xE707, (q15_t)0x8275 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par +
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 64, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_64_q15[96] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7F62, (q15_t)0x0C8B, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7A7D, (q15_t)0x2528, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x70E2, (q15_t)0x3C56, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x62F2, (q15_t)0x5133, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5133, (q15_t)0x62F2, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x3C56, (q15_t)0x70E2, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2528, (q15_t)0x7A7D, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x0C8B, (q15_t)0x7F62, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xF374, (q15_t)0x7F62, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xDAD7, (q15_t)0x7A7D, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xC3A9, (q15_t)0x70E2, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xAECC, (q15_t)0x62F2, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0x9D0D, (q15_t)0x5133, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x8F1D, (q15_t)0x3C56, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8582, (q15_t)0x2528, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x809D, (q15_t)0x0C8B, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x809D, (q15_t)0xF374, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x8582, (q15_t)0xDAD7, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8F1D, (q15_t)0xC3A9, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9D0D, (q15_t)0xAECC, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xAECC, (q15_t)0x9D0D, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xC3A9, (q15_t)0x8F1D, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xDAD7, (q15_t)0x8582, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xF374, (q15_t)0x809D +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par +
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 128, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_128_q15[192] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FD8, (q15_t)0x0647, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7E9D, (q15_t)0x12C8, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7C29, (q15_t)0x1F19, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7884, (q15_t)0x2B1F, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x73B5, (q15_t)0x36BA, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x6DCA, (q15_t)0x41CE, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x66CF, (q15_t)0x4C3F, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x5ED7, (q15_t)0x55F5, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x55F5, (q15_t)0x5ED7, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4C3F, (q15_t)0x66CF, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x41CE, (q15_t)0x6DCA, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x36BA, (q15_t)0x73B5, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2B1F, (q15_t)0x7884, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x1F19, (q15_t)0x7C29, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x12C8, (q15_t)0x7E9D, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0647, (q15_t)0x7FD8, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xF9B8, (q15_t)0x7FD8, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xED37, (q15_t)0x7E9D, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE0E6, (q15_t)0x7C29, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD4E0, (q15_t)0x7884, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xC945, (q15_t)0x73B5, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xBE31, (q15_t)0x6DCA, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB3C0, (q15_t)0x66CF, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAA0A, (q15_t)0x5ED7, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA128, (q15_t)0x55F5, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9930, (q15_t)0x4C3F, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x9235, (q15_t)0x41CE, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8C4A, (q15_t)0x36BA, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x877B, (q15_t)0x2B1F, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x83D6, (q15_t)0x1F19, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x8162, (q15_t)0x12C8, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8027, (q15_t)0x0647, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8027, (q15_t)0xF9B8, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x8162, (q15_t)0xED37, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x83D6, (q15_t)0xE0E6, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x877B, (q15_t)0xD4E0, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8C4A, (q15_t)0xC945, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x9235, (q15_t)0xBE31, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9930, (q15_t)0xB3C0, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0xA128, (q15_t)0xAA0A, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xAA0A, (q15_t)0xA128, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB3C0, (q15_t)0x9930, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBE31, (q15_t)0x9235, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC945, (q15_t)0x8C4A, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD4E0, (q15_t)0x877B, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xE0E6, (q15_t)0x83D6, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xED37, (q15_t)0x8162, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF9B8, (q15_t)0x8027 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par +
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 256, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_256_q15[384] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FF6, (q15_t)0x0324, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FA7, (q15_t)0x096A, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F09, (q15_t)0x0FAB, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E1D, (q15_t)0x15E2, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7CE3, (q15_t)0x1C0B, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7B5D, (q15_t)0x2223, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x798A, (q15_t)0x2826, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x776C, (q15_t)0x2E11, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x7504, (q15_t)0x33DE, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x7255, (q15_t)0x398C, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x6F5F, (q15_t)0x3F17, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6C24, (q15_t)0x447A, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x68A6, (q15_t)0x49B4, + (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x64E8, (q15_t)0x4EBF, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x60EC, (q15_t)0x539B, + (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5CB4, (q15_t)0x5842, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5842, (q15_t)0x5CB4, + (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x539B, (q15_t)0x60EC, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4EBF, (q15_t)0x64E8, + (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x49B4, (q15_t)0x68A6, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x447A, (q15_t)0x6C24, + (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x3F17, (q15_t)0x6F5F, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x398C, (q15_t)0x7255, + (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x33DE, (q15_t)0x7504, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2E11, (q15_t)0x776C, + (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x2826, (q15_t)0x798A, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x2223, (q15_t)0x7B5D, + (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1C0B, (q15_t)0x7CE3, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x15E2, (q15_t)0x7E1D, + (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x0FAB, (q15_t)0x7F09, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x096A, (q15_t)0x7FA7, + (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x0324, (q15_t)0x7FF6, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFCDB, (q15_t)0x7FF6, + (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF695, (q15_t)0x7FA7, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF054, (q15_t)0x7F09, + (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xEA1D, (q15_t)0x7E1D, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE3F4, (q15_t)0x7CE3, + (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xDDDC, (q15_t)0x7B5D, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD7D9, (q15_t)0x798A, + (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD1EE, (q15_t)0x776C, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCC21, (q15_t)0x7504, + (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC673, (q15_t)0x7255, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC0E8, (q15_t)0x6F5F, + (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBB85, (q15_t)0x6C24, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB64B, (q15_t)0x68A6, + (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB140, (q15_t)0x64E8, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAC64, (q15_t)0x60EC, + (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA7BD, (q15_t)0x5CB4, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA34B, (q15_t)0x5842, + (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0x9F13, (q15_t)0x539B, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9B17, (q15_t)0x4EBF, + (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x9759, (q15_t)0x49B4, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x93DB, (q15_t)0x447A, + (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x90A0, (q15_t)0x3F17, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8DAA, (q15_t)0x398C, + (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8AFB, (q15_t)0x33DE, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8893, (q15_t)0x2E11, + (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x8675, (q15_t)0x2826, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x84A2, (q15_t)0x2223, + (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x831C, (q15_t)0x1C0B, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x81E2, (q15_t)0x15E2, + (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x80F6, (q15_t)0x0FAB, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8058, (q15_t)0x096A, + (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8009, (q15_t)0x0324, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8009, (q15_t)0xFCDB, + (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x8058, (q15_t)0xF695, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80F6, (q15_t)0xF054, + (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x81E2, (q15_t)0xEA1D, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x831C, (q15_t)0xE3F4, + (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x84A2, (q15_t)0xDDDC, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x8675, (q15_t)0xD7D9, + (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x8893, (q15_t)0xD1EE, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8AFB, (q15_t)0xCC21, + (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8DAA, (q15_t)0xC673, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x90A0, (q15_t)0xC0E8, + (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x93DB, (q15_t)0xBB85, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9759, (q15_t)0xB64B, + (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x9B17, (q15_t)0xB140, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9F13, (q15_t)0xAC64, + (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA34B, (q15_t)0xA7BD, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA7BD, (q15_t)0xA34B, + (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAC64, (q15_t)0x9F13, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB140, (q15_t)0x9B17, + (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB64B, (q15_t)0x9759, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBB85, (q15_t)0x93DB, + (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xC0E8, (q15_t)0x90A0, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC673, (q15_t)0x8DAA, + (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xCC21, (q15_t)0x8AFB, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD1EE, (q15_t)0x8893, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD7D9, (q15_t)0x8675, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDDDC, (q15_t)0x84A2, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE3F4, (q15_t)0x831C, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xEA1D, (q15_t)0x81E2, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xF054, (q15_t)0x80F6, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF695, (q15_t)0x8058, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFCDB, (q15_t)0x8009 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par +
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 512, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_512_q15[768] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFD, (q15_t)0x0192, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FE9, (q15_t)0x04B6, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FC2, (q15_t)0x07D9, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F87, (q15_t)0x0AFB, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F38, (q15_t)0x0E1B, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7ED5, (q15_t)0x1139, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E5F, (q15_t)0x1455, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7DD6, (q15_t)0x176D, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D39, (q15_t)0x1A82, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7C89, (q15_t)0x1D93, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7BC5, (q15_t)0x209F, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7AEF, (q15_t)0x23A6, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A05, (q15_t)0x26A8, + (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x7909, (q15_t)0x29A3, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x77FA, (q15_t)0x2C98, + (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x76D9, (q15_t)0x2F87, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x75A5, (q15_t)0x326E, + (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x745F, (q15_t)0x354D, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x7307, (q15_t)0x3824, + (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x719E, (q15_t)0x3AF2, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x7023, (q15_t)0x3DB8, + (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6E96, (q15_t)0x4073, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6CF9, (q15_t)0x4325, + (q15_t)0x6C24, (q15_t)0x447A, (q15_t)0x6B4A, (q15_t)0x45CD, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x698C, (q15_t)0x4869, + (q15_t)0x68A6, (q15_t)0x49B4, (q15_t)0x67BD, (q15_t)0x4AFB, + (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x65DD, (q15_t)0x4D81, + (q15_t)0x64E8, (q15_t)0x4EBF, (q15_t)0x63EF, (q15_t)0x4FFB, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x61F1, (q15_t)0x5269, + (q15_t)0x60EC, (q15_t)0x539B, (q15_t)0x5FE3, (q15_t)0x54CA, + (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5DC7, (q15_t)0x571D, + (q15_t)0x5CB4, (q15_t)0x5842, (q15_t)0x5B9D, (q15_t)0x5964, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5964, (q15_t)0x5B9D, + (q15_t)0x5842, (q15_t)0x5CB4, (q15_t)0x571D, (q15_t)0x5DC7, + (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x54CA, (q15_t)0x5FE3, + (q15_t)0x539B, (q15_t)0x60EC, (q15_t)0x5269, (q15_t)0x61F1, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4FFB, (q15_t)0x63EF, + (q15_t)0x4EBF, (q15_t)0x64E8, (q15_t)0x4D81, (q15_t)0x65DD, + (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x4AFB, (q15_t)0x67BD, + (q15_t)0x49B4, (q15_t)0x68A6, (q15_t)0x4869, (q15_t)0x698C, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x45CD, (q15_t)0x6B4A, + (q15_t)0x447A, (q15_t)0x6C24, (q15_t)0x4325, (q15_t)0x6CF9, + (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x4073, (q15_t)0x6E96, + (q15_t)0x3F17, (q15_t)0x6F5F, (q15_t)0x3DB8, (q15_t)0x7023, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x3AF2, (q15_t)0x719E, + (q15_t)0x398C, (q15_t)0x7255, (q15_t)0x3824, (q15_t)0x7307, + (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x354D, (q15_t)0x745F, + (q15_t)0x33DE, (q15_t)0x7504, (q15_t)0x326E, (q15_t)0x75A5, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2F87, (q15_t)0x76D9, + (q15_t)0x2E11, (q15_t)0x776C, (q15_t)0x2C98, (q15_t)0x77FA, + (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x29A3, (q15_t)0x7909, + (q15_t)0x2826, (q15_t)0x798A, (q15_t)0x26A8, (q15_t)0x7A05, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x23A6, (q15_t)0x7AEF, + (q15_t)0x2223, (q15_t)0x7B5D, (q15_t)0x209F, (q15_t)0x7BC5, + (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1D93, (q15_t)0x7C89, + (q15_t)0x1C0B, (q15_t)0x7CE3, (q15_t)0x1A82, (q15_t)0x7D39, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x176D, (q15_t)0x7DD6, + (q15_t)0x15E2, (q15_t)0x7E1D, (q15_t)0x1455, (q15_t)0x7E5F, + (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x1139, (q15_t)0x7ED5, + (q15_t)0x0FAB, (q15_t)0x7F09, (q15_t)0x0E1B, (q15_t)0x7F38, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0AFB, (q15_t)0x7F87, + (q15_t)0x096A, (q15_t)0x7FA7, (q15_t)0x07D9, (q15_t)0x7FC2, + (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x04B6, (q15_t)0x7FE9, + (q15_t)0x0324, (q15_t)0x7FF6, (q15_t)0x0192, (q15_t)0x7FFD, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFE6D, (q15_t)0x7FFD, + (q15_t)0xFCDB, (q15_t)0x7FF6, (q15_t)0xFB49, (q15_t)0x7FE9, + (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF826, (q15_t)0x7FC2, + (q15_t)0xF695, (q15_t)0x7FA7, (q15_t)0xF504, (q15_t)0x7F87, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF1E4, (q15_t)0x7F38, + (q15_t)0xF054, (q15_t)0x7F09, (q15_t)0xEEC6, (q15_t)0x7ED5, + (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xEBAA, (q15_t)0x7E5F, + (q15_t)0xEA1D, (q15_t)0x7E1D, (q15_t)0xE892, (q15_t)0x7DD6, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE57D, (q15_t)0x7D39, + (q15_t)0xE3F4, (q15_t)0x7CE3, (q15_t)0xE26C, (q15_t)0x7C89, + (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xDF60, (q15_t)0x7BC5, + (q15_t)0xDDDC, (q15_t)0x7B5D, (q15_t)0xDC59, (q15_t)0x7AEF, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD957, (q15_t)0x7A05, + (q15_t)0xD7D9, (q15_t)0x798A, (q15_t)0xD65C, (q15_t)0x7909, + (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD367, (q15_t)0x77FA, + (q15_t)0xD1EE, (q15_t)0x776C, (q15_t)0xD078, (q15_t)0x76D9, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCD91, (q15_t)0x75A5, + (q15_t)0xCC21, (q15_t)0x7504, (q15_t)0xCAB2, (q15_t)0x745F, + (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC7DB, (q15_t)0x7307, + (q15_t)0xC673, (q15_t)0x7255, (q15_t)0xC50D, (q15_t)0x719E, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC247, (q15_t)0x7023, + (q15_t)0xC0E8, (q15_t)0x6F5F, (q15_t)0xBF8C, (q15_t)0x6E96, + (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBCDA, (q15_t)0x6CF9, + (q15_t)0xBB85, (q15_t)0x6C24, (q15_t)0xBA32, (q15_t)0x6B4A, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB796, (q15_t)0x698C, + (q15_t)0xB64B, (q15_t)0x68A6, (q15_t)0xB504, (q15_t)0x67BD, + (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB27E, (q15_t)0x65DD, + (q15_t)0xB140, (q15_t)0x64E8, (q15_t)0xB004, (q15_t)0x63EF, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAD96, (q15_t)0x61F1, + (q15_t)0xAC64, (q15_t)0x60EC, (q15_t)0xAB35, (q15_t)0x5FE3, + (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA8E2, (q15_t)0x5DC7, + (q15_t)0xA7BD, (q15_t)0x5CB4, (q15_t)0xA69B, (q15_t)0x5B9D, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA462, (q15_t)0x5964, + (q15_t)0xA34B, (q15_t)0x5842, (q15_t)0xA238, (q15_t)0x571D, + (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0xA01C, (q15_t)0x54CA, + (q15_t)0x9F13, (q15_t)0x539B, (q15_t)0x9E0E, (q15_t)0x5269, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9C10, (q15_t)0x4FFB, + (q15_t)0x9B17, (q15_t)0x4EBF, (q15_t)0x9A22, (q15_t)0x4D81, + (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x9842, (q15_t)0x4AFB, + (q15_t)0x9759, (q15_t)0x49B4, (q15_t)0x9673, (q15_t)0x4869, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x94B5, (q15_t)0x45CD, + (q15_t)0x93DB, (q15_t)0x447A, (q15_t)0x9306, (q15_t)0x4325, + (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x9169, (q15_t)0x4073, + (q15_t)0x90A0, (q15_t)0x3F17, (q15_t)0x8FDC, (q15_t)0x3DB8, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8E61, (q15_t)0x3AF2, + (q15_t)0x8DAA, (q15_t)0x398C, (q15_t)0x8CF8, (q15_t)0x3824, + (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8BA0, (q15_t)0x354D, + (q15_t)0x8AFB, (q15_t)0x33DE, (q15_t)0x8A5A, (q15_t)0x326E, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8926, (q15_t)0x2F87, + (q15_t)0x8893, (q15_t)0x2E11, (q15_t)0x8805, (q15_t)0x2C98, + (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x86F6, (q15_t)0x29A3, + (q15_t)0x8675, (q15_t)0x2826, (q15_t)0x85FA, (q15_t)0x26A8, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x8510, (q15_t)0x23A6, + (q15_t)0x84A2, (q15_t)0x2223, (q15_t)0x843A, (q15_t)0x209F, + (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x8376, (q15_t)0x1D93, + (q15_t)0x831C, (q15_t)0x1C0B, (q15_t)0x82C6, (q15_t)0x1A82, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x8229, (q15_t)0x176D, + (q15_t)0x81E2, (q15_t)0x15E2, (q15_t)0x81A0, (q15_t)0x1455, + (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x812A, (q15_t)0x1139, + (q15_t)0x80F6, (q15_t)0x0FAB, (q15_t)0x80C7, (q15_t)0x0E1B, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8078, (q15_t)0x0AFB, + (q15_t)0x8058, (q15_t)0x096A, (q15_t)0x803D, (q15_t)0x07D9, + (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8016, (q15_t)0x04B6, + (q15_t)0x8009, (q15_t)0x0324, (q15_t)0x8002, (q15_t)0x0192, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8002, (q15_t)0xFE6D, + (q15_t)0x8009, (q15_t)0xFCDB, (q15_t)0x8016, (q15_t)0xFB49, + (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x803D, (q15_t)0xF826, + (q15_t)0x8058, (q15_t)0xF695, (q15_t)0x8078, (q15_t)0xF504, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80C7, (q15_t)0xF1E4, + (q15_t)0x80F6, (q15_t)0xF054, (q15_t)0x812A, (q15_t)0xEEC6, + (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x81A0, (q15_t)0xEBAA, + (q15_t)0x81E2, (q15_t)0xEA1D, (q15_t)0x8229, (q15_t)0xE892, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x82C6, (q15_t)0xE57D, + (q15_t)0x831C, (q15_t)0xE3F4, (q15_t)0x8376, (q15_t)0xE26C, + (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x843A, (q15_t)0xDF60, + (q15_t)0x84A2, (q15_t)0xDDDC, (q15_t)0x8510, (q15_t)0xDC59, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x85FA, (q15_t)0xD957, + (q15_t)0x8675, (q15_t)0xD7D9, (q15_t)0x86F6, (q15_t)0xD65C, + (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x8805, (q15_t)0xD367, + (q15_t)0x8893, (q15_t)0xD1EE, (q15_t)0x8926, (q15_t)0xD078, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8A5A, (q15_t)0xCD91, + (q15_t)0x8AFB, (q15_t)0xCC21, (q15_t)0x8BA0, (q15_t)0xCAB2, + (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8CF8, (q15_t)0xC7DB, + (q15_t)0x8DAA, (q15_t)0xC673, (q15_t)0x8E61, (q15_t)0xC50D, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x8FDC, (q15_t)0xC247, + (q15_t)0x90A0, (q15_t)0xC0E8, (q15_t)0x9169, (q15_t)0xBF8C, + (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x9306, (q15_t)0xBCDA, + (q15_t)0x93DB, (q15_t)0xBB85, (q15_t)0x94B5, (q15_t)0xBA32, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9673, (q15_t)0xB796, + (q15_t)0x9759, (q15_t)0xB64B, (q15_t)0x9842, (q15_t)0xB504, + (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x9A22, (q15_t)0xB27E, + (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9C10, (q15_t)0xB004, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9E0E, (q15_t)0xAD96, + (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0xA01C, (q15_t)0xAB35, + (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA238, (q15_t)0xA8E2, + (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA462, (q15_t)0xA69B, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA69B, (q15_t)0xA462, + (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA8E2, (q15_t)0xA238, + (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAB35, (q15_t)0xA01C, + (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xAD96, (q15_t)0x9E0E, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB004, (q15_t)0x9C10, + (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB27E, (q15_t)0x9A22, + (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB504, (q15_t)0x9842, + (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB796, (q15_t)0x9673, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBA32, (q15_t)0x94B5, + (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBCDA, (q15_t)0x9306, + (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBF8C, (q15_t)0x9169, + (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC247, (q15_t)0x8FDC, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC50D, (q15_t)0x8E61, + (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC7DB, (q15_t)0x8CF8, + (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xCAB2, (q15_t)0x8BA0, + (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCD91, (q15_t)0x8A5A, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD078, (q15_t)0x8926, + (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD367, (q15_t)0x8805, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD65C, (q15_t)0x86F6, + (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD957, (q15_t)0x85FA, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDC59, (q15_t)0x8510, + (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDF60, (q15_t)0x843A, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE26C, (q15_t)0x8376, + (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE57D, (q15_t)0x82C6, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE892, (q15_t)0x8229, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEBAA, (q15_t)0x81A0, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xEEC6, (q15_t)0x812A, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF1E4, (q15_t)0x80C7, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF504, (q15_t)0x8078, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF826, (q15_t)0x803D, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFB49, (q15_t)0x8016, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFE6D, (q15_t)0x8002 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par +
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 1024, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + + */ +const q15_t twiddleCoef_1024_q15[1536] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x00C9, + (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFA, (q15_t)0x025B, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF0, (q15_t)0x03ED, + (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE1, (q15_t)0x057F, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FCE, (q15_t)0x0710, + (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FB5, (q15_t)0x08A2, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F97, (q15_t)0x0A33, + (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F75, (q15_t)0x0BC3, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F4D, (q15_t)0x0D53, + (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F21, (q15_t)0x0EE3, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7EF0, (q15_t)0x1072, + (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7EBA, (q15_t)0x1201, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E7F, (q15_t)0x138E, + (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E3F, (q15_t)0x151B, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7DFA, (q15_t)0x16A8, + (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DB0, (q15_t)0x1833, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D62, (q15_t)0x19BD, + (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D0F, (q15_t)0x1B47, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CB7, (q15_t)0x1CCF, + (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C5A, (q15_t)0x1E56, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7BF8, (q15_t)0x1FDC, + (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7B92, (q15_t)0x2161, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B26, (q15_t)0x22E5, + (q15_t)0x7AEF, (q15_t)0x23A6, (q15_t)0x7AB6, (q15_t)0x2467, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A42, (q15_t)0x25E8, + (q15_t)0x7A05, (q15_t)0x26A8, (q15_t)0x79C8, (q15_t)0x2767, + (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x794A, (q15_t)0x28E5, + (q15_t)0x7909, (q15_t)0x29A3, (q15_t)0x78C7, (q15_t)0x2A61, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x7840, (q15_t)0x2BDC, + (q15_t)0x77FA, (q15_t)0x2C98, (q15_t)0x77B4, (q15_t)0x2D55, + (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x7723, (q15_t)0x2ECC, + (q15_t)0x76D9, (q15_t)0x2F87, (q15_t)0x768E, (q15_t)0x3041, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x75F4, (q15_t)0x31B5, + (q15_t)0x75A5, (q15_t)0x326E, (q15_t)0x7555, (q15_t)0x3326, + (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x74B2, (q15_t)0x3496, + (q15_t)0x745F, (q15_t)0x354D, (q15_t)0x740B, (q15_t)0x3604, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x735F, (q15_t)0x376F, + (q15_t)0x7307, (q15_t)0x3824, (q15_t)0x72AF, (q15_t)0x38D8, + (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x71FA, (q15_t)0x3A40, + (q15_t)0x719E, (q15_t)0x3AF2, (q15_t)0x7141, (q15_t)0x3BA5, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x7083, (q15_t)0x3D07, + (q15_t)0x7023, (q15_t)0x3DB8, (q15_t)0x6FC1, (q15_t)0x3E68, + (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6EFB, (q15_t)0x3FC5, + (q15_t)0x6E96, (q15_t)0x4073, (q15_t)0x6E30, (q15_t)0x4121, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6D62, (q15_t)0x427A, + (q15_t)0x6CF9, (q15_t)0x4325, (q15_t)0x6C8F, (q15_t)0x43D0, + (q15_t)0x6C24, (q15_t)0x447A, (q15_t)0x6BB8, (q15_t)0x4524, + (q15_t)0x6B4A, (q15_t)0x45CD, (q15_t)0x6ADC, (q15_t)0x4675, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x69FD, (q15_t)0x47C3, + (q15_t)0x698C, (q15_t)0x4869, (q15_t)0x6919, (q15_t)0x490F, + (q15_t)0x68A6, (q15_t)0x49B4, (q15_t)0x6832, (q15_t)0x4A58, + (q15_t)0x67BD, (q15_t)0x4AFB, (q15_t)0x6746, (q15_t)0x4B9E, + (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x6657, (q15_t)0x4CE1, + (q15_t)0x65DD, (q15_t)0x4D81, (q15_t)0x6563, (q15_t)0x4E21, + (q15_t)0x64E8, (q15_t)0x4EBF, (q15_t)0x646C, (q15_t)0x4F5E, + (q15_t)0x63EF, (q15_t)0x4FFB, (q15_t)0x6371, (q15_t)0x5097, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x6271, (q15_t)0x51CE, + (q15_t)0x61F1, (q15_t)0x5269, (q15_t)0x616F, (q15_t)0x5302, + (q15_t)0x60EC, (q15_t)0x539B, (q15_t)0x6068, (q15_t)0x5433, + (q15_t)0x5FE3, (q15_t)0x54CA, (q15_t)0x5F5E, (q15_t)0x5560, + (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5E50, (q15_t)0x568A, + (q15_t)0x5DC7, (q15_t)0x571D, (q15_t)0x5D3E, (q15_t)0x57B0, + (q15_t)0x5CB4, (q15_t)0x5842, (q15_t)0x5C29, (q15_t)0x58D4, + (q15_t)0x5B9D, (q15_t)0x5964, (q15_t)0x5B10, (q15_t)0x59F3, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x59F3, (q15_t)0x5B10, + (q15_t)0x5964, (q15_t)0x5B9D, (q15_t)0x58D4, (q15_t)0x5C29, + (q15_t)0x5842, (q15_t)0x5CB4, (q15_t)0x57B0, (q15_t)0x5D3E, + (q15_t)0x571D, (q15_t)0x5DC7, (q15_t)0x568A, (q15_t)0x5E50, + (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x5560, (q15_t)0x5F5E, + (q15_t)0x54CA, (q15_t)0x5FE3, (q15_t)0x5433, (q15_t)0x6068, + (q15_t)0x539B, (q15_t)0x60EC, (q15_t)0x5302, (q15_t)0x616F, + (q15_t)0x5269, (q15_t)0x61F1, (q15_t)0x51CE, (q15_t)0x6271, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x5097, (q15_t)0x6371, + (q15_t)0x4FFB, (q15_t)0x63EF, (q15_t)0x4F5E, (q15_t)0x646C, + (q15_t)0x4EBF, (q15_t)0x64E8, (q15_t)0x4E21, (q15_t)0x6563, + (q15_t)0x4D81, (q15_t)0x65DD, (q15_t)0x4CE1, (q15_t)0x6657, + (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x4B9E, (q15_t)0x6746, + (q15_t)0x4AFB, (q15_t)0x67BD, (q15_t)0x4A58, (q15_t)0x6832, + (q15_t)0x49B4, (q15_t)0x68A6, (q15_t)0x490F, (q15_t)0x6919, + (q15_t)0x4869, (q15_t)0x698C, (q15_t)0x47C3, (q15_t)0x69FD, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x4675, (q15_t)0x6ADC, + (q15_t)0x45CD, (q15_t)0x6B4A, (q15_t)0x4524, (q15_t)0x6BB8, + (q15_t)0x447A, (q15_t)0x6C24, (q15_t)0x43D0, (q15_t)0x6C8F, + (q15_t)0x4325, (q15_t)0x6CF9, (q15_t)0x427A, (q15_t)0x6D62, + (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x4121, (q15_t)0x6E30, + (q15_t)0x4073, (q15_t)0x6E96, (q15_t)0x3FC5, (q15_t)0x6EFB, + (q15_t)0x3F17, (q15_t)0x6F5F, (q15_t)0x3E68, (q15_t)0x6FC1, + (q15_t)0x3DB8, (q15_t)0x7023, (q15_t)0x3D07, (q15_t)0x7083, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x3BA5, (q15_t)0x7141, + (q15_t)0x3AF2, (q15_t)0x719E, (q15_t)0x3A40, (q15_t)0x71FA, + (q15_t)0x398C, (q15_t)0x7255, (q15_t)0x38D8, (q15_t)0x72AF, + (q15_t)0x3824, (q15_t)0x7307, (q15_t)0x376F, (q15_t)0x735F, + (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x3604, (q15_t)0x740B, + (q15_t)0x354D, (q15_t)0x745F, (q15_t)0x3496, (q15_t)0x74B2, + (q15_t)0x33DE, (q15_t)0x7504, (q15_t)0x3326, (q15_t)0x7555, + (q15_t)0x326E, (q15_t)0x75A5, (q15_t)0x31B5, (q15_t)0x75F4, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x3041, (q15_t)0x768E, + (q15_t)0x2F87, (q15_t)0x76D9, (q15_t)0x2ECC, (q15_t)0x7723, + (q15_t)0x2E11, (q15_t)0x776C, (q15_t)0x2D55, (q15_t)0x77B4, + (q15_t)0x2C98, (q15_t)0x77FA, (q15_t)0x2BDC, (q15_t)0x7840, + (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x2A61, (q15_t)0x78C7, + (q15_t)0x29A3, (q15_t)0x7909, (q15_t)0x28E5, (q15_t)0x794A, + (q15_t)0x2826, (q15_t)0x798A, (q15_t)0x2767, (q15_t)0x79C8, + (q15_t)0x26A8, (q15_t)0x7A05, (q15_t)0x25E8, (q15_t)0x7A42, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x2467, (q15_t)0x7AB6, + (q15_t)0x23A6, (q15_t)0x7AEF, (q15_t)0x22E5, (q15_t)0x7B26, + (q15_t)0x2223, (q15_t)0x7B5D, (q15_t)0x2161, (q15_t)0x7B92, + (q15_t)0x209F, (q15_t)0x7BC5, (q15_t)0x1FDC, (q15_t)0x7BF8, + (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1E56, (q15_t)0x7C5A, + (q15_t)0x1D93, (q15_t)0x7C89, (q15_t)0x1CCF, (q15_t)0x7CB7, + (q15_t)0x1C0B, (q15_t)0x7CE3, (q15_t)0x1B47, (q15_t)0x7D0F, + (q15_t)0x1A82, (q15_t)0x7D39, (q15_t)0x19BD, (q15_t)0x7D62, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x1833, (q15_t)0x7DB0, + (q15_t)0x176D, (q15_t)0x7DD6, (q15_t)0x16A8, (q15_t)0x7DFA, + (q15_t)0x15E2, (q15_t)0x7E1D, (q15_t)0x151B, (q15_t)0x7E3F, + (q15_t)0x1455, (q15_t)0x7E5F, (q15_t)0x138E, (q15_t)0x7E7F, + (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x1201, (q15_t)0x7EBA, + (q15_t)0x1139, (q15_t)0x7ED5, (q15_t)0x1072, (q15_t)0x7EF0, + (q15_t)0x0FAB, (q15_t)0x7F09, (q15_t)0x0EE3, (q15_t)0x7F21, + (q15_t)0x0E1B, (q15_t)0x7F38, (q15_t)0x0D53, (q15_t)0x7F4D, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0BC3, (q15_t)0x7F75, + (q15_t)0x0AFB, (q15_t)0x7F87, (q15_t)0x0A33, (q15_t)0x7F97, + (q15_t)0x096A, (q15_t)0x7FA7, (q15_t)0x08A2, (q15_t)0x7FB5, + (q15_t)0x07D9, (q15_t)0x7FC2, (q15_t)0x0710, (q15_t)0x7FCE, + (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x057F, (q15_t)0x7FE1, + (q15_t)0x04B6, (q15_t)0x7FE9, (q15_t)0x03ED, (q15_t)0x7FF0, + (q15_t)0x0324, (q15_t)0x7FF6, (q15_t)0x025B, (q15_t)0x7FFA, + (q15_t)0x0192, (q15_t)0x7FFD, (q15_t)0x00C9, (q15_t)0x7FFF, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFF36, (q15_t)0x7FFF, + (q15_t)0xFE6D, (q15_t)0x7FFD, (q15_t)0xFDA4, (q15_t)0x7FFA, + (q15_t)0xFCDB, (q15_t)0x7FF6, (q15_t)0xFC12, (q15_t)0x7FF0, + (q15_t)0xFB49, (q15_t)0x7FE9, (q15_t)0xFA80, (q15_t)0x7FE1, + (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF8EF, (q15_t)0x7FCE, + (q15_t)0xF826, (q15_t)0x7FC2, (q15_t)0xF75D, (q15_t)0x7FB5, + (q15_t)0xF695, (q15_t)0x7FA7, (q15_t)0xF5CC, (q15_t)0x7F97, + (q15_t)0xF504, (q15_t)0x7F87, (q15_t)0xF43C, (q15_t)0x7F75, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF2AC, (q15_t)0x7F4D, + (q15_t)0xF1E4, (q15_t)0x7F38, (q15_t)0xF11C, (q15_t)0x7F21, + (q15_t)0xF054, (q15_t)0x7F09, (q15_t)0xEF8D, (q15_t)0x7EF0, + (q15_t)0xEEC6, (q15_t)0x7ED5, (q15_t)0xEDFE, (q15_t)0x7EBA, + (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xEC71, (q15_t)0x7E7F, + (q15_t)0xEBAA, (q15_t)0x7E5F, (q15_t)0xEAE4, (q15_t)0x7E3F, + (q15_t)0xEA1D, (q15_t)0x7E1D, (q15_t)0xE957, (q15_t)0x7DFA, + (q15_t)0xE892, (q15_t)0x7DD6, (q15_t)0xE7CC, (q15_t)0x7DB0, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE642, (q15_t)0x7D62, + (q15_t)0xE57D, (q15_t)0x7D39, (q15_t)0xE4B8, (q15_t)0x7D0F, + (q15_t)0xE3F4, (q15_t)0x7CE3, (q15_t)0xE330, (q15_t)0x7CB7, + (q15_t)0xE26C, (q15_t)0x7C89, (q15_t)0xE1A9, (q15_t)0x7C5A, + (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xE023, (q15_t)0x7BF8, + (q15_t)0xDF60, (q15_t)0x7BC5, (q15_t)0xDE9E, (q15_t)0x7B92, + (q15_t)0xDDDC, (q15_t)0x7B5D, (q15_t)0xDD1A, (q15_t)0x7B26, + (q15_t)0xDC59, (q15_t)0x7AEF, (q15_t)0xDB98, (q15_t)0x7AB6, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xDA17, (q15_t)0x7A42, + (q15_t)0xD957, (q15_t)0x7A05, (q15_t)0xD898, (q15_t)0x79C8, + (q15_t)0xD7D9, (q15_t)0x798A, (q15_t)0xD71A, (q15_t)0x794A, + (q15_t)0xD65C, (q15_t)0x7909, (q15_t)0xD59E, (q15_t)0x78C7, + (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD423, (q15_t)0x7840, + (q15_t)0xD367, (q15_t)0x77FA, (q15_t)0xD2AA, (q15_t)0x77B4, + (q15_t)0xD1EE, (q15_t)0x776C, (q15_t)0xD133, (q15_t)0x7723, + (q15_t)0xD078, (q15_t)0x76D9, (q15_t)0xCFBE, (q15_t)0x768E, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCE4A, (q15_t)0x75F4, + (q15_t)0xCD91, (q15_t)0x75A5, (q15_t)0xCCD9, (q15_t)0x7555, + (q15_t)0xCC21, (q15_t)0x7504, (q15_t)0xCB69, (q15_t)0x74B2, + (q15_t)0xCAB2, (q15_t)0x745F, (q15_t)0xC9FB, (q15_t)0x740B, + (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC890, (q15_t)0x735F, + (q15_t)0xC7DB, (q15_t)0x7307, (q15_t)0xC727, (q15_t)0x72AF, + (q15_t)0xC673, (q15_t)0x7255, (q15_t)0xC5BF, (q15_t)0x71FA, + (q15_t)0xC50D, (q15_t)0x719E, (q15_t)0xC45A, (q15_t)0x7141, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC2F8, (q15_t)0x7083, + (q15_t)0xC247, (q15_t)0x7023, (q15_t)0xC197, (q15_t)0x6FC1, + (q15_t)0xC0E8, (q15_t)0x6F5F, (q15_t)0xC03A, (q15_t)0x6EFB, + (q15_t)0xBF8C, (q15_t)0x6E96, (q15_t)0xBEDE, (q15_t)0x6E30, + (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBD85, (q15_t)0x6D62, + (q15_t)0xBCDA, (q15_t)0x6CF9, (q15_t)0xBC2F, (q15_t)0x6C8F, + (q15_t)0xBB85, (q15_t)0x6C24, (q15_t)0xBADB, (q15_t)0x6BB8, + (q15_t)0xBA32, (q15_t)0x6B4A, (q15_t)0xB98A, (q15_t)0x6ADC, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB83C, (q15_t)0x69FD, + (q15_t)0xB796, (q15_t)0x698C, (q15_t)0xB6F0, (q15_t)0x6919, + (q15_t)0xB64B, (q15_t)0x68A6, (q15_t)0xB5A7, (q15_t)0x6832, + (q15_t)0xB504, (q15_t)0x67BD, (q15_t)0xB461, (q15_t)0x6746, + (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB31E, (q15_t)0x6657, + (q15_t)0xB27E, (q15_t)0x65DD, (q15_t)0xB1DE, (q15_t)0x6563, + (q15_t)0xB140, (q15_t)0x64E8, (q15_t)0xB0A1, (q15_t)0x646C, + (q15_t)0xB004, (q15_t)0x63EF, (q15_t)0xAF68, (q15_t)0x6371, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAE31, (q15_t)0x6271, + (q15_t)0xAD96, (q15_t)0x61F1, (q15_t)0xACFD, (q15_t)0x616F, + (q15_t)0xAC64, (q15_t)0x60EC, (q15_t)0xABCC, (q15_t)0x6068, + (q15_t)0xAB35, (q15_t)0x5FE3, (q15_t)0xAA9F, (q15_t)0x5F5E, + (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA975, (q15_t)0x5E50, + (q15_t)0xA8E2, (q15_t)0x5DC7, (q15_t)0xA84F, (q15_t)0x5D3E, + (q15_t)0xA7BD, (q15_t)0x5CB4, (q15_t)0xA72B, (q15_t)0x5C29, + (q15_t)0xA69B, (q15_t)0x5B9D, (q15_t)0xA60C, (q15_t)0x5B10, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA4EF, (q15_t)0x59F3, + (q15_t)0xA462, (q15_t)0x5964, (q15_t)0xA3D6, (q15_t)0x58D4, + (q15_t)0xA34B, (q15_t)0x5842, (q15_t)0xA2C1, (q15_t)0x57B0, + (q15_t)0xA238, (q15_t)0x571D, (q15_t)0xA1AF, (q15_t)0x568A, + (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0xA0A1, (q15_t)0x5560, + (q15_t)0xA01C, (q15_t)0x54CA, (q15_t)0x9F97, (q15_t)0x5433, + (q15_t)0x9F13, (q15_t)0x539B, (q15_t)0x9E90, (q15_t)0x5302, + (q15_t)0x9E0E, (q15_t)0x5269, (q15_t)0x9D8E, (q15_t)0x51CE, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9C8E, (q15_t)0x5097, + (q15_t)0x9C10, (q15_t)0x4FFB, (q15_t)0x9B93, (q15_t)0x4F5E, + (q15_t)0x9B17, (q15_t)0x4EBF, (q15_t)0x9A9C, (q15_t)0x4E21, + (q15_t)0x9A22, (q15_t)0x4D81, (q15_t)0x99A8, (q15_t)0x4CE1, + (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x98B9, (q15_t)0x4B9E, + (q15_t)0x9842, (q15_t)0x4AFB, (q15_t)0x97CD, (q15_t)0x4A58, + (q15_t)0x9759, (q15_t)0x49B4, (q15_t)0x96E6, (q15_t)0x490F, + (q15_t)0x9673, (q15_t)0x4869, (q15_t)0x9602, (q15_t)0x47C3, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x9523, (q15_t)0x4675, + (q15_t)0x94B5, (q15_t)0x45CD, (q15_t)0x9447, (q15_t)0x4524, + (q15_t)0x93DB, (q15_t)0x447A, (q15_t)0x9370, (q15_t)0x43D0, + (q15_t)0x9306, (q15_t)0x4325, (q15_t)0x929D, (q15_t)0x427A, + (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x91CF, (q15_t)0x4121, + (q15_t)0x9169, (q15_t)0x4073, (q15_t)0x9104, (q15_t)0x3FC5, + (q15_t)0x90A0, (q15_t)0x3F17, (q15_t)0x903E, (q15_t)0x3E68, + (q15_t)0x8FDC, (q15_t)0x3DB8, (q15_t)0x8F7C, (q15_t)0x3D07, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8EBE, (q15_t)0x3BA5, + (q15_t)0x8E61, (q15_t)0x3AF2, (q15_t)0x8E05, (q15_t)0x3A40, + (q15_t)0x8DAA, (q15_t)0x398C, (q15_t)0x8D50, (q15_t)0x38D8, + (q15_t)0x8CF8, (q15_t)0x3824, (q15_t)0x8CA0, (q15_t)0x376F, + (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8BF4, (q15_t)0x3604, + (q15_t)0x8BA0, (q15_t)0x354D, (q15_t)0x8B4D, (q15_t)0x3496, + (q15_t)0x8AFB, (q15_t)0x33DE, (q15_t)0x8AAA, (q15_t)0x3326, + (q15_t)0x8A5A, (q15_t)0x326E, (q15_t)0x8A0B, (q15_t)0x31B5, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8971, (q15_t)0x3041, + (q15_t)0x8926, (q15_t)0x2F87, (q15_t)0x88DC, (q15_t)0x2ECC, + (q15_t)0x8893, (q15_t)0x2E11, (q15_t)0x884B, (q15_t)0x2D55, + (q15_t)0x8805, (q15_t)0x2C98, (q15_t)0x87BF, (q15_t)0x2BDC, + (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x8738, (q15_t)0x2A61, + (q15_t)0x86F6, (q15_t)0x29A3, (q15_t)0x86B5, (q15_t)0x28E5, + (q15_t)0x8675, (q15_t)0x2826, (q15_t)0x8637, (q15_t)0x2767, + (q15_t)0x85FA, (q15_t)0x26A8, (q15_t)0x85BD, (q15_t)0x25E8, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x8549, (q15_t)0x2467, + (q15_t)0x8510, (q15_t)0x23A6, (q15_t)0x84D9, (q15_t)0x22E5, + (q15_t)0x84A2, (q15_t)0x2223, (q15_t)0x846D, (q15_t)0x2161, + (q15_t)0x843A, (q15_t)0x209F, (q15_t)0x8407, (q15_t)0x1FDC, + (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x83A5, (q15_t)0x1E56, + (q15_t)0x8376, (q15_t)0x1D93, (q15_t)0x8348, (q15_t)0x1CCF, + (q15_t)0x831C, (q15_t)0x1C0B, (q15_t)0x82F0, (q15_t)0x1B47, + (q15_t)0x82C6, (q15_t)0x1A82, (q15_t)0x829D, (q15_t)0x19BD, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x824F, (q15_t)0x1833, + (q15_t)0x8229, (q15_t)0x176D, (q15_t)0x8205, (q15_t)0x16A8, + (q15_t)0x81E2, (q15_t)0x15E2, (q15_t)0x81C0, (q15_t)0x151B, + (q15_t)0x81A0, (q15_t)0x1455, (q15_t)0x8180, (q15_t)0x138E, + (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x8145, (q15_t)0x1201, + (q15_t)0x812A, (q15_t)0x1139, (q15_t)0x810F, (q15_t)0x1072, + (q15_t)0x80F6, (q15_t)0x0FAB, (q15_t)0x80DE, (q15_t)0x0EE3, + (q15_t)0x80C7, (q15_t)0x0E1B, (q15_t)0x80B2, (q15_t)0x0D53, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x808A, (q15_t)0x0BC3, + (q15_t)0x8078, (q15_t)0x0AFB, (q15_t)0x8068, (q15_t)0x0A33, + (q15_t)0x8058, (q15_t)0x096A, (q15_t)0x804A, (q15_t)0x08A2, + (q15_t)0x803D, (q15_t)0x07D9, (q15_t)0x8031, (q15_t)0x0710, + (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x801E, (q15_t)0x057F, + (q15_t)0x8016, (q15_t)0x04B6, (q15_t)0x800F, (q15_t)0x03ED, + (q15_t)0x8009, (q15_t)0x0324, (q15_t)0x8005, (q15_t)0x025B, + (q15_t)0x8002, (q15_t)0x0192, (q15_t)0x8000, (q15_t)0x00C9, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8000, (q15_t)0xFF36, + (q15_t)0x8002, (q15_t)0xFE6D, (q15_t)0x8005, (q15_t)0xFDA4, + (q15_t)0x8009, (q15_t)0xFCDB, (q15_t)0x800F, (q15_t)0xFC12, + (q15_t)0x8016, (q15_t)0xFB49, (q15_t)0x801E, (q15_t)0xFA80, + (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x8031, (q15_t)0xF8EF, + (q15_t)0x803D, (q15_t)0xF826, (q15_t)0x804A, (q15_t)0xF75D, + (q15_t)0x8058, (q15_t)0xF695, (q15_t)0x8068, (q15_t)0xF5CC, + (q15_t)0x8078, (q15_t)0xF504, (q15_t)0x808A, (q15_t)0xF43C, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80B2, (q15_t)0xF2AC, + (q15_t)0x80C7, (q15_t)0xF1E4, (q15_t)0x80DE, (q15_t)0xF11C, + (q15_t)0x80F6, (q15_t)0xF054, (q15_t)0x810F, (q15_t)0xEF8D, + (q15_t)0x812A, (q15_t)0xEEC6, (q15_t)0x8145, (q15_t)0xEDFE, + (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x8180, (q15_t)0xEC71, + (q15_t)0x81A0, (q15_t)0xEBAA, (q15_t)0x81C0, (q15_t)0xEAE4, + (q15_t)0x81E2, (q15_t)0xEA1D, (q15_t)0x8205, (q15_t)0xE957, + (q15_t)0x8229, (q15_t)0xE892, (q15_t)0x824F, (q15_t)0xE7CC, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x829D, (q15_t)0xE642, + (q15_t)0x82C6, (q15_t)0xE57D, (q15_t)0x82F0, (q15_t)0xE4B8, + (q15_t)0x831C, (q15_t)0xE3F4, (q15_t)0x8348, (q15_t)0xE330, + (q15_t)0x8376, (q15_t)0xE26C, (q15_t)0x83A5, (q15_t)0xE1A9, + (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x8407, (q15_t)0xE023, + (q15_t)0x843A, (q15_t)0xDF60, (q15_t)0x846D, (q15_t)0xDE9E, + (q15_t)0x84A2, (q15_t)0xDDDC, (q15_t)0x84D9, (q15_t)0xDD1A, + (q15_t)0x8510, (q15_t)0xDC59, (q15_t)0x8549, (q15_t)0xDB98, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x85BD, (q15_t)0xDA17, + (q15_t)0x85FA, (q15_t)0xD957, (q15_t)0x8637, (q15_t)0xD898, + (q15_t)0x8675, (q15_t)0xD7D9, (q15_t)0x86B5, (q15_t)0xD71A, + (q15_t)0x86F6, (q15_t)0xD65C, (q15_t)0x8738, (q15_t)0xD59E, + (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x87BF, (q15_t)0xD423, + (q15_t)0x8805, (q15_t)0xD367, (q15_t)0x884B, (q15_t)0xD2AA, + (q15_t)0x8893, (q15_t)0xD1EE, (q15_t)0x88DC, (q15_t)0xD133, + (q15_t)0x8926, (q15_t)0xD078, (q15_t)0x8971, (q15_t)0xCFBE, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8A0B, (q15_t)0xCE4A, + (q15_t)0x8A5A, (q15_t)0xCD91, (q15_t)0x8AAA, (q15_t)0xCCD9, + (q15_t)0x8AFB, (q15_t)0xCC21, (q15_t)0x8B4D, (q15_t)0xCB69, + (q15_t)0x8BA0, (q15_t)0xCAB2, (q15_t)0x8BF4, (q15_t)0xC9FB, + (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8CA0, (q15_t)0xC890, + (q15_t)0x8CF8, (q15_t)0xC7DB, (q15_t)0x8D50, (q15_t)0xC727, + (q15_t)0x8DAA, (q15_t)0xC673, (q15_t)0x8E05, (q15_t)0xC5BF, + (q15_t)0x8E61, (q15_t)0xC50D, (q15_t)0x8EBE, (q15_t)0xC45A, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x8F7C, (q15_t)0xC2F8, + (q15_t)0x8FDC, (q15_t)0xC247, (q15_t)0x903E, (q15_t)0xC197, + (q15_t)0x90A0, (q15_t)0xC0E8, (q15_t)0x9104, (q15_t)0xC03A, + (q15_t)0x9169, (q15_t)0xBF8C, (q15_t)0x91CF, (q15_t)0xBEDE, + (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x929D, (q15_t)0xBD85, + (q15_t)0x9306, (q15_t)0xBCDA, (q15_t)0x9370, (q15_t)0xBC2F, + (q15_t)0x93DB, (q15_t)0xBB85, (q15_t)0x9447, (q15_t)0xBADB, + (q15_t)0x94B5, (q15_t)0xBA32, (q15_t)0x9523, (q15_t)0xB98A, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9602, (q15_t)0xB83C, + (q15_t)0x9673, (q15_t)0xB796, (q15_t)0x96E6, (q15_t)0xB6F0, + (q15_t)0x9759, (q15_t)0xB64B, (q15_t)0x97CD, (q15_t)0xB5A7, + (q15_t)0x9842, (q15_t)0xB504, (q15_t)0x98B9, (q15_t)0xB461, + (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x99A8, (q15_t)0xB31E, + (q15_t)0x9A22, (q15_t)0xB27E, (q15_t)0x9A9C, (q15_t)0xB1DE, + (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9B93, (q15_t)0xB0A1, + (q15_t)0x9C10, (q15_t)0xB004, (q15_t)0x9C8E, (q15_t)0xAF68, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9D8E, (q15_t)0xAE31, + (q15_t)0x9E0E, (q15_t)0xAD96, (q15_t)0x9E90, (q15_t)0xACFD, + (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0x9F97, (q15_t)0xABCC, + (q15_t)0xA01C, (q15_t)0xAB35, (q15_t)0xA0A1, (q15_t)0xAA9F, + (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA1AF, (q15_t)0xA975, + (q15_t)0xA238, (q15_t)0xA8E2, (q15_t)0xA2C1, (q15_t)0xA84F, + (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA3D6, (q15_t)0xA72B, + (q15_t)0xA462, (q15_t)0xA69B, (q15_t)0xA4EF, (q15_t)0xA60C, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA60C, (q15_t)0xA4EF, + (q15_t)0xA69B, (q15_t)0xA462, (q15_t)0xA72B, (q15_t)0xA3D6, + (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA84F, (q15_t)0xA2C1, + (q15_t)0xA8E2, (q15_t)0xA238, (q15_t)0xA975, (q15_t)0xA1AF, + (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAA9F, (q15_t)0xA0A1, + (q15_t)0xAB35, (q15_t)0xA01C, (q15_t)0xABCC, (q15_t)0x9F97, + (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xACFD, (q15_t)0x9E90, + (q15_t)0xAD96, (q15_t)0x9E0E, (q15_t)0xAE31, (q15_t)0x9D8E, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xAF68, (q15_t)0x9C8E, + (q15_t)0xB004, (q15_t)0x9C10, (q15_t)0xB0A1, (q15_t)0x9B93, + (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB1DE, (q15_t)0x9A9C, + (q15_t)0xB27E, (q15_t)0x9A22, (q15_t)0xB31E, (q15_t)0x99A8, + (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB461, (q15_t)0x98B9, + (q15_t)0xB504, (q15_t)0x9842, (q15_t)0xB5A7, (q15_t)0x97CD, + (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB6F0, (q15_t)0x96E6, + (q15_t)0xB796, (q15_t)0x9673, (q15_t)0xB83C, (q15_t)0x9602, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xB98A, (q15_t)0x9523, + (q15_t)0xBA32, (q15_t)0x94B5, (q15_t)0xBADB, (q15_t)0x9447, + (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBC2F, (q15_t)0x9370, + (q15_t)0xBCDA, (q15_t)0x9306, (q15_t)0xBD85, (q15_t)0x929D, + (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBEDE, (q15_t)0x91CF, + (q15_t)0xBF8C, (q15_t)0x9169, (q15_t)0xC03A, (q15_t)0x9104, + (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC197, (q15_t)0x903E, + (q15_t)0xC247, (q15_t)0x8FDC, (q15_t)0xC2F8, (q15_t)0x8F7C, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC45A, (q15_t)0x8EBE, + (q15_t)0xC50D, (q15_t)0x8E61, (q15_t)0xC5BF, (q15_t)0x8E05, + (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC727, (q15_t)0x8D50, + (q15_t)0xC7DB, (q15_t)0x8CF8, (q15_t)0xC890, (q15_t)0x8CA0, + (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xC9FB, (q15_t)0x8BF4, + (q15_t)0xCAB2, (q15_t)0x8BA0, (q15_t)0xCB69, (q15_t)0x8B4D, + (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCCD9, (q15_t)0x8AAA, + (q15_t)0xCD91, (q15_t)0x8A5A, (q15_t)0xCE4A, (q15_t)0x8A0B, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xCFBE, (q15_t)0x8971, + (q15_t)0xD078, (q15_t)0x8926, (q15_t)0xD133, (q15_t)0x88DC, + (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD2AA, (q15_t)0x884B, + (q15_t)0xD367, (q15_t)0x8805, (q15_t)0xD423, (q15_t)0x87BF, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD59E, (q15_t)0x8738, + (q15_t)0xD65C, (q15_t)0x86F6, (q15_t)0xD71A, (q15_t)0x86B5, + (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD898, (q15_t)0x8637, + (q15_t)0xD957, (q15_t)0x85FA, (q15_t)0xDA17, (q15_t)0x85BD, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDB98, (q15_t)0x8549, + (q15_t)0xDC59, (q15_t)0x8510, (q15_t)0xDD1A, (q15_t)0x84D9, + (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDE9E, (q15_t)0x846D, + (q15_t)0xDF60, (q15_t)0x843A, (q15_t)0xE023, (q15_t)0x8407, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE1A9, (q15_t)0x83A5, + (q15_t)0xE26C, (q15_t)0x8376, (q15_t)0xE330, (q15_t)0x8348, + (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE4B8, (q15_t)0x82F0, + (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE642, (q15_t)0x829D, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE7CC, (q15_t)0x824F, + (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE957, (q15_t)0x8205, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEAE4, (q15_t)0x81C0, + (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEC71, (q15_t)0x8180, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xEDFE, (q15_t)0x8145, + (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEF8D, (q15_t)0x810F, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF11C, (q15_t)0x80DE, + (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF2AC, (q15_t)0x80B2, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF43C, (q15_t)0x808A, + (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF5CC, (q15_t)0x8068, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF75D, (q15_t)0x804A, + (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF8EF, (q15_t)0x8031, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFA80, (q15_t)0x801E, + (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFC12, (q15_t)0x800F, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFDA4, (q15_t)0x8005, + (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFF36, (q15_t)0x8000 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par +
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 2048, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_2048_q15[3072] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x0064, + (q15_t)0x7FFF, (q15_t)0x00C9, (q15_t)0x7FFE, (q15_t)0x012D, + (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFC, (q15_t)0x01F6, + (q15_t)0x7FFA, (q15_t)0x025B, (q15_t)0x7FF8, (q15_t)0x02BF, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF3, (q15_t)0x0388, + (q15_t)0x7FF0, (q15_t)0x03ED, (q15_t)0x7FED, (q15_t)0x0451, + (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE5, (q15_t)0x051A, + (q15_t)0x7FE1, (q15_t)0x057F, (q15_t)0x7FDD, (q15_t)0x05E3, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FD3, (q15_t)0x06AC, + (q15_t)0x7FCE, (q15_t)0x0710, (q15_t)0x7FC8, (q15_t)0x0775, + (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FBC, (q15_t)0x083D, + (q15_t)0x7FB5, (q15_t)0x08A2, (q15_t)0x7FAE, (q15_t)0x0906, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F9F, (q15_t)0x09CE, + (q15_t)0x7F97, (q15_t)0x0A33, (q15_t)0x7F8F, (q15_t)0x0A97, + (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F7E, (q15_t)0x0B5F, + (q15_t)0x7F75, (q15_t)0x0BC3, (q15_t)0x7F6B, (q15_t)0x0C27, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F58, (q15_t)0x0CEF, + (q15_t)0x7F4D, (q15_t)0x0D53, (q15_t)0x7F43, (q15_t)0x0DB7, + (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F2D, (q15_t)0x0E7F, + (q15_t)0x7F21, (q15_t)0x0EE3, (q15_t)0x7F15, (q15_t)0x0F47, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7EFD, (q15_t)0x100E, + (q15_t)0x7EF0, (q15_t)0x1072, (q15_t)0x7EE3, (q15_t)0x10D6, + (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7EC8, (q15_t)0x119D, + (q15_t)0x7EBA, (q15_t)0x1201, (q15_t)0x7EAB, (q15_t)0x1264, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E8E, (q15_t)0x132B, + (q15_t)0x7E7F, (q15_t)0x138E, (q15_t)0x7E6F, (q15_t)0x13F2, + (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E4F, (q15_t)0x14B8, + (q15_t)0x7E3F, (q15_t)0x151B, (q15_t)0x7E2E, (q15_t)0x157F, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7E0C, (q15_t)0x1645, + (q15_t)0x7DFA, (q15_t)0x16A8, (q15_t)0x7DE8, (q15_t)0x170A, + (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DC3, (q15_t)0x17D0, + (q15_t)0x7DB0, (q15_t)0x1833, (q15_t)0x7D9D, (q15_t)0x1896, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D76, (q15_t)0x195B, + (q15_t)0x7D62, (q15_t)0x19BD, (q15_t)0x7D4E, (q15_t)0x1A20, + (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D24, (q15_t)0x1AE4, + (q15_t)0x7D0F, (q15_t)0x1B47, (q15_t)0x7CF9, (q15_t)0x1BA9, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CCD, (q15_t)0x1C6D, + (q15_t)0x7CB7, (q15_t)0x1CCF, (q15_t)0x7CA0, (q15_t)0x1D31, + (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C71, (q15_t)0x1DF5, + (q15_t)0x7C5A, (q15_t)0x1E56, (q15_t)0x7C42, (q15_t)0x1EB8, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7C11, (q15_t)0x1F7B, + (q15_t)0x7BF8, (q15_t)0x1FDC, (q15_t)0x7BDF, (q15_t)0x203E, + (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7BAC, (q15_t)0x2100, + (q15_t)0x7B92, (q15_t)0x2161, (q15_t)0x7B77, (q15_t)0x21C2, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B42, (q15_t)0x2284, + (q15_t)0x7B26, (q15_t)0x22E5, (q15_t)0x7B0B, (q15_t)0x2345, + (q15_t)0x7AEF, (q15_t)0x23A6, (q15_t)0x7AD3, (q15_t)0x2407, + (q15_t)0x7AB6, (q15_t)0x2467, (q15_t)0x7A9A, (q15_t)0x24C7, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A5F, (q15_t)0x2588, + (q15_t)0x7A42, (q15_t)0x25E8, (q15_t)0x7A24, (q15_t)0x2648, + (q15_t)0x7A05, (q15_t)0x26A8, (q15_t)0x79E7, (q15_t)0x2707, + (q15_t)0x79C8, (q15_t)0x2767, (q15_t)0x79A9, (q15_t)0x27C7, + (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x796A, (q15_t)0x2886, + (q15_t)0x794A, (q15_t)0x28E5, (q15_t)0x792A, (q15_t)0x2944, + (q15_t)0x7909, (q15_t)0x29A3, (q15_t)0x78E8, (q15_t)0x2A02, + (q15_t)0x78C7, (q15_t)0x2A61, (q15_t)0x78A6, (q15_t)0x2AC0, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x7862, (q15_t)0x2B7D, + (q15_t)0x7840, (q15_t)0x2BDC, (q15_t)0x781D, (q15_t)0x2C3A, + (q15_t)0x77FA, (q15_t)0x2C98, (q15_t)0x77D7, (q15_t)0x2CF7, + (q15_t)0x77B4, (q15_t)0x2D55, (q15_t)0x7790, (q15_t)0x2DB3, + (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x7747, (q15_t)0x2E6E, + (q15_t)0x7723, (q15_t)0x2ECC, (q15_t)0x76FE, (q15_t)0x2F29, + (q15_t)0x76D9, (q15_t)0x2F87, (q15_t)0x76B3, (q15_t)0x2FE4, + (q15_t)0x768E, (q15_t)0x3041, (q15_t)0x7668, (q15_t)0x309E, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x761B, (q15_t)0x3158, + (q15_t)0x75F4, (q15_t)0x31B5, (q15_t)0x75CC, (q15_t)0x3211, + (q15_t)0x75A5, (q15_t)0x326E, (q15_t)0x757D, (q15_t)0x32CA, + (q15_t)0x7555, (q15_t)0x3326, (q15_t)0x752D, (q15_t)0x3382, + (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x74DB, (q15_t)0x343A, + (q15_t)0x74B2, (q15_t)0x3496, (q15_t)0x7489, (q15_t)0x34F2, + (q15_t)0x745F, (q15_t)0x354D, (q15_t)0x7435, (q15_t)0x35A8, + (q15_t)0x740B, (q15_t)0x3604, (q15_t)0x73E0, (q15_t)0x365F, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x738A, (q15_t)0x3714, + (q15_t)0x735F, (q15_t)0x376F, (q15_t)0x7333, (q15_t)0x37CA, + (q15_t)0x7307, (q15_t)0x3824, (q15_t)0x72DB, (q15_t)0x387E, + (q15_t)0x72AF, (q15_t)0x38D8, (q15_t)0x7282, (q15_t)0x3932, + (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x7227, (q15_t)0x39E6, + (q15_t)0x71FA, (q15_t)0x3A40, (q15_t)0x71CC, (q15_t)0x3A99, + (q15_t)0x719E, (q15_t)0x3AF2, (q15_t)0x716F, (q15_t)0x3B4C, + (q15_t)0x7141, (q15_t)0x3BA5, (q15_t)0x7112, (q15_t)0x3BFD, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x70B3, (q15_t)0x3CAF, + (q15_t)0x7083, (q15_t)0x3D07, (q15_t)0x7053, (q15_t)0x3D60, + (q15_t)0x7023, (q15_t)0x3DB8, (q15_t)0x6FF2, (q15_t)0x3E10, + (q15_t)0x6FC1, (q15_t)0x3E68, (q15_t)0x6F90, (q15_t)0x3EBF, + (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6F2D, (q15_t)0x3F6E, + (q15_t)0x6EFB, (q15_t)0x3FC5, (q15_t)0x6EC9, (q15_t)0x401D, + (q15_t)0x6E96, (q15_t)0x4073, (q15_t)0x6E63, (q15_t)0x40CA, + (q15_t)0x6E30, (q15_t)0x4121, (q15_t)0x6DFD, (q15_t)0x4177, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6D96, (q15_t)0x4224, + (q15_t)0x6D62, (q15_t)0x427A, (q15_t)0x6D2D, (q15_t)0x42D0, + (q15_t)0x6CF9, (q15_t)0x4325, (q15_t)0x6CC4, (q15_t)0x437B, + (q15_t)0x6C8F, (q15_t)0x43D0, (q15_t)0x6C59, (q15_t)0x4425, + (q15_t)0x6C24, (q15_t)0x447A, (q15_t)0x6BEE, (q15_t)0x44CF, + (q15_t)0x6BB8, (q15_t)0x4524, (q15_t)0x6B81, (q15_t)0x4578, + (q15_t)0x6B4A, (q15_t)0x45CD, (q15_t)0x6B13, (q15_t)0x4621, + (q15_t)0x6ADC, (q15_t)0x4675, (q15_t)0x6AA5, (q15_t)0x46C9, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x6A35, (q15_t)0x4770, + (q15_t)0x69FD, (q15_t)0x47C3, (q15_t)0x69C4, (q15_t)0x4816, + (q15_t)0x698C, (q15_t)0x4869, (q15_t)0x6953, (q15_t)0x48BC, + (q15_t)0x6919, (q15_t)0x490F, (q15_t)0x68E0, (q15_t)0x4961, + (q15_t)0x68A6, (q15_t)0x49B4, (q15_t)0x686C, (q15_t)0x4A06, + (q15_t)0x6832, (q15_t)0x4A58, (q15_t)0x67F7, (q15_t)0x4AA9, + (q15_t)0x67BD, (q15_t)0x4AFB, (q15_t)0x6782, (q15_t)0x4B4C, + (q15_t)0x6746, (q15_t)0x4B9E, (q15_t)0x670B, (q15_t)0x4BEF, + (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x6693, (q15_t)0x4C90, + (q15_t)0x6657, (q15_t)0x4CE1, (q15_t)0x661A, (q15_t)0x4D31, + (q15_t)0x65DD, (q15_t)0x4D81, (q15_t)0x65A0, (q15_t)0x4DD1, + (q15_t)0x6563, (q15_t)0x4E21, (q15_t)0x6526, (q15_t)0x4E70, + (q15_t)0x64E8, (q15_t)0x4EBF, (q15_t)0x64AA, (q15_t)0x4F0F, + (q15_t)0x646C, (q15_t)0x4F5E, (q15_t)0x642D, (q15_t)0x4FAC, + (q15_t)0x63EF, (q15_t)0x4FFB, (q15_t)0x63B0, (q15_t)0x5049, + (q15_t)0x6371, (q15_t)0x5097, (q15_t)0x6331, (q15_t)0x50E5, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x62B2, (q15_t)0x5181, + (q15_t)0x6271, (q15_t)0x51CE, (q15_t)0x6231, (q15_t)0x521C, + (q15_t)0x61F1, (q15_t)0x5269, (q15_t)0x61B0, (q15_t)0x52B5, + (q15_t)0x616F, (q15_t)0x5302, (q15_t)0x612D, (q15_t)0x534E, + (q15_t)0x60EC, (q15_t)0x539B, (q15_t)0x60AA, (q15_t)0x53E7, + (q15_t)0x6068, (q15_t)0x5433, (q15_t)0x6026, (q15_t)0x547E, + (q15_t)0x5FE3, (q15_t)0x54CA, (q15_t)0x5FA0, (q15_t)0x5515, + (q15_t)0x5F5E, (q15_t)0x5560, (q15_t)0x5F1A, (q15_t)0x55AB, + (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5E93, (q15_t)0x5640, + (q15_t)0x5E50, (q15_t)0x568A, (q15_t)0x5E0B, (q15_t)0x56D4, + (q15_t)0x5DC7, (q15_t)0x571D, (q15_t)0x5D83, (q15_t)0x5767, + (q15_t)0x5D3E, (q15_t)0x57B0, (q15_t)0x5CF9, (q15_t)0x57F9, + (q15_t)0x5CB4, (q15_t)0x5842, (q15_t)0x5C6E, (q15_t)0x588B, + (q15_t)0x5C29, (q15_t)0x58D4, (q15_t)0x5BE3, (q15_t)0x591C, + (q15_t)0x5B9D, (q15_t)0x5964, (q15_t)0x5B56, (q15_t)0x59AC, + (q15_t)0x5B10, (q15_t)0x59F3, (q15_t)0x5AC9, (q15_t)0x5A3B, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5A3B, (q15_t)0x5AC9, + (q15_t)0x59F3, (q15_t)0x5B10, (q15_t)0x59AC, (q15_t)0x5B56, + (q15_t)0x5964, (q15_t)0x5B9D, (q15_t)0x591C, (q15_t)0x5BE3, + (q15_t)0x58D4, (q15_t)0x5C29, (q15_t)0x588B, (q15_t)0x5C6E, + (q15_t)0x5842, (q15_t)0x5CB4, (q15_t)0x57F9, (q15_t)0x5CF9, + (q15_t)0x57B0, (q15_t)0x5D3E, (q15_t)0x5767, (q15_t)0x5D83, + (q15_t)0x571D, (q15_t)0x5DC7, (q15_t)0x56D4, (q15_t)0x5E0B, + (q15_t)0x568A, (q15_t)0x5E50, (q15_t)0x5640, (q15_t)0x5E93, + (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x55AB, (q15_t)0x5F1A, + (q15_t)0x5560, (q15_t)0x5F5E, (q15_t)0x5515, (q15_t)0x5FA0, + (q15_t)0x54CA, (q15_t)0x5FE3, (q15_t)0x547E, (q15_t)0x6026, + (q15_t)0x5433, (q15_t)0x6068, (q15_t)0x53E7, (q15_t)0x60AA, + (q15_t)0x539B, (q15_t)0x60EC, (q15_t)0x534E, (q15_t)0x612D, + (q15_t)0x5302, (q15_t)0x616F, (q15_t)0x52B5, (q15_t)0x61B0, + (q15_t)0x5269, (q15_t)0x61F1, (q15_t)0x521C, (q15_t)0x6231, + (q15_t)0x51CE, (q15_t)0x6271, (q15_t)0x5181, (q15_t)0x62B2, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x50E5, (q15_t)0x6331, + (q15_t)0x5097, (q15_t)0x6371, (q15_t)0x5049, (q15_t)0x63B0, + (q15_t)0x4FFB, (q15_t)0x63EF, (q15_t)0x4FAC, (q15_t)0x642D, + (q15_t)0x4F5E, (q15_t)0x646C, (q15_t)0x4F0F, (q15_t)0x64AA, + (q15_t)0x4EBF, (q15_t)0x64E8, (q15_t)0x4E70, (q15_t)0x6526, + (q15_t)0x4E21, (q15_t)0x6563, (q15_t)0x4DD1, (q15_t)0x65A0, + (q15_t)0x4D81, (q15_t)0x65DD, (q15_t)0x4D31, (q15_t)0x661A, + (q15_t)0x4CE1, (q15_t)0x6657, (q15_t)0x4C90, (q15_t)0x6693, + (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x4BEF, (q15_t)0x670B, + (q15_t)0x4B9E, (q15_t)0x6746, (q15_t)0x4B4C, (q15_t)0x6782, + (q15_t)0x4AFB, (q15_t)0x67BD, (q15_t)0x4AA9, (q15_t)0x67F7, + (q15_t)0x4A58, (q15_t)0x6832, (q15_t)0x4A06, (q15_t)0x686C, + (q15_t)0x49B4, (q15_t)0x68A6, (q15_t)0x4961, (q15_t)0x68E0, + (q15_t)0x490F, (q15_t)0x6919, (q15_t)0x48BC, (q15_t)0x6953, + (q15_t)0x4869, (q15_t)0x698C, (q15_t)0x4816, (q15_t)0x69C4, + (q15_t)0x47C3, (q15_t)0x69FD, (q15_t)0x4770, (q15_t)0x6A35, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x46C9, (q15_t)0x6AA5, + (q15_t)0x4675, (q15_t)0x6ADC, (q15_t)0x4621, (q15_t)0x6B13, + (q15_t)0x45CD, (q15_t)0x6B4A, (q15_t)0x4578, (q15_t)0x6B81, + (q15_t)0x4524, (q15_t)0x6BB8, (q15_t)0x44CF, (q15_t)0x6BEE, + (q15_t)0x447A, (q15_t)0x6C24, (q15_t)0x4425, (q15_t)0x6C59, + (q15_t)0x43D0, (q15_t)0x6C8F, (q15_t)0x437B, (q15_t)0x6CC4, + (q15_t)0x4325, (q15_t)0x6CF9, (q15_t)0x42D0, (q15_t)0x6D2D, + (q15_t)0x427A, (q15_t)0x6D62, (q15_t)0x4224, (q15_t)0x6D96, + (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x4177, (q15_t)0x6DFD, + (q15_t)0x4121, (q15_t)0x6E30, (q15_t)0x40CA, (q15_t)0x6E63, + (q15_t)0x4073, (q15_t)0x6E96, (q15_t)0x401D, (q15_t)0x6EC9, + (q15_t)0x3FC5, (q15_t)0x6EFB, (q15_t)0x3F6E, (q15_t)0x6F2D, + (q15_t)0x3F17, (q15_t)0x6F5F, (q15_t)0x3EBF, (q15_t)0x6F90, + (q15_t)0x3E68, (q15_t)0x6FC1, (q15_t)0x3E10, (q15_t)0x6FF2, + (q15_t)0x3DB8, (q15_t)0x7023, (q15_t)0x3D60, (q15_t)0x7053, + (q15_t)0x3D07, (q15_t)0x7083, (q15_t)0x3CAF, (q15_t)0x70B3, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x3BFD, (q15_t)0x7112, + (q15_t)0x3BA5, (q15_t)0x7141, (q15_t)0x3B4C, (q15_t)0x716F, + (q15_t)0x3AF2, (q15_t)0x719E, (q15_t)0x3A99, (q15_t)0x71CC, + (q15_t)0x3A40, (q15_t)0x71FA, (q15_t)0x39E6, (q15_t)0x7227, + (q15_t)0x398C, (q15_t)0x7255, (q15_t)0x3932, (q15_t)0x7282, + (q15_t)0x38D8, (q15_t)0x72AF, (q15_t)0x387E, (q15_t)0x72DB, + (q15_t)0x3824, (q15_t)0x7307, (q15_t)0x37CA, (q15_t)0x7333, + (q15_t)0x376F, (q15_t)0x735F, (q15_t)0x3714, (q15_t)0x738A, + (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x365F, (q15_t)0x73E0, + (q15_t)0x3604, (q15_t)0x740B, (q15_t)0x35A8, (q15_t)0x7435, + (q15_t)0x354D, (q15_t)0x745F, (q15_t)0x34F2, (q15_t)0x7489, + (q15_t)0x3496, (q15_t)0x74B2, (q15_t)0x343A, (q15_t)0x74DB, + (q15_t)0x33DE, (q15_t)0x7504, (q15_t)0x3382, (q15_t)0x752D, + (q15_t)0x3326, (q15_t)0x7555, (q15_t)0x32CA, (q15_t)0x757D, + (q15_t)0x326E, (q15_t)0x75A5, (q15_t)0x3211, (q15_t)0x75CC, + (q15_t)0x31B5, (q15_t)0x75F4, (q15_t)0x3158, (q15_t)0x761B, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x309E, (q15_t)0x7668, + (q15_t)0x3041, (q15_t)0x768E, (q15_t)0x2FE4, (q15_t)0x76B3, + (q15_t)0x2F87, (q15_t)0x76D9, (q15_t)0x2F29, (q15_t)0x76FE, + (q15_t)0x2ECC, (q15_t)0x7723, (q15_t)0x2E6E, (q15_t)0x7747, + (q15_t)0x2E11, (q15_t)0x776C, (q15_t)0x2DB3, (q15_t)0x7790, + (q15_t)0x2D55, (q15_t)0x77B4, (q15_t)0x2CF7, (q15_t)0x77D7, + (q15_t)0x2C98, (q15_t)0x77FA, (q15_t)0x2C3A, (q15_t)0x781D, + (q15_t)0x2BDC, (q15_t)0x7840, (q15_t)0x2B7D, (q15_t)0x7862, + (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x2AC0, (q15_t)0x78A6, + (q15_t)0x2A61, (q15_t)0x78C7, (q15_t)0x2A02, (q15_t)0x78E8, + (q15_t)0x29A3, (q15_t)0x7909, (q15_t)0x2944, (q15_t)0x792A, + (q15_t)0x28E5, (q15_t)0x794A, (q15_t)0x2886, (q15_t)0x796A, + (q15_t)0x2826, (q15_t)0x798A, (q15_t)0x27C7, (q15_t)0x79A9, + (q15_t)0x2767, (q15_t)0x79C8, (q15_t)0x2707, (q15_t)0x79E7, + (q15_t)0x26A8, (q15_t)0x7A05, (q15_t)0x2648, (q15_t)0x7A24, + (q15_t)0x25E8, (q15_t)0x7A42, (q15_t)0x2588, (q15_t)0x7A5F, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x24C7, (q15_t)0x7A9A, + (q15_t)0x2467, (q15_t)0x7AB6, (q15_t)0x2407, (q15_t)0x7AD3, + (q15_t)0x23A6, (q15_t)0x7AEF, (q15_t)0x2345, (q15_t)0x7B0B, + (q15_t)0x22E5, (q15_t)0x7B26, (q15_t)0x2284, (q15_t)0x7B42, + (q15_t)0x2223, (q15_t)0x7B5D, (q15_t)0x21C2, (q15_t)0x7B77, + (q15_t)0x2161, (q15_t)0x7B92, (q15_t)0x2100, (q15_t)0x7BAC, + (q15_t)0x209F, (q15_t)0x7BC5, (q15_t)0x203E, (q15_t)0x7BDF, + (q15_t)0x1FDC, (q15_t)0x7BF8, (q15_t)0x1F7B, (q15_t)0x7C11, + (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1EB8, (q15_t)0x7C42, + (q15_t)0x1E56, (q15_t)0x7C5A, (q15_t)0x1DF5, (q15_t)0x7C71, + (q15_t)0x1D93, (q15_t)0x7C89, (q15_t)0x1D31, (q15_t)0x7CA0, + (q15_t)0x1CCF, (q15_t)0x7CB7, (q15_t)0x1C6D, (q15_t)0x7CCD, + (q15_t)0x1C0B, (q15_t)0x7CE3, (q15_t)0x1BA9, (q15_t)0x7CF9, + (q15_t)0x1B47, (q15_t)0x7D0F, (q15_t)0x1AE4, (q15_t)0x7D24, + (q15_t)0x1A82, (q15_t)0x7D39, (q15_t)0x1A20, (q15_t)0x7D4E, + (q15_t)0x19BD, (q15_t)0x7D62, (q15_t)0x195B, (q15_t)0x7D76, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x1896, (q15_t)0x7D9D, + (q15_t)0x1833, (q15_t)0x7DB0, (q15_t)0x17D0, (q15_t)0x7DC3, + (q15_t)0x176D, (q15_t)0x7DD6, (q15_t)0x170A, (q15_t)0x7DE8, + (q15_t)0x16A8, (q15_t)0x7DFA, (q15_t)0x1645, (q15_t)0x7E0C, + (q15_t)0x15E2, (q15_t)0x7E1D, (q15_t)0x157F, (q15_t)0x7E2E, + (q15_t)0x151B, (q15_t)0x7E3F, (q15_t)0x14B8, (q15_t)0x7E4F, + (q15_t)0x1455, (q15_t)0x7E5F, (q15_t)0x13F2, (q15_t)0x7E6F, + (q15_t)0x138E, (q15_t)0x7E7F, (q15_t)0x132B, (q15_t)0x7E8E, + (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x1264, (q15_t)0x7EAB, + (q15_t)0x1201, (q15_t)0x7EBA, (q15_t)0x119D, (q15_t)0x7EC8, + (q15_t)0x1139, (q15_t)0x7ED5, (q15_t)0x10D6, (q15_t)0x7EE3, + (q15_t)0x1072, (q15_t)0x7EF0, (q15_t)0x100E, (q15_t)0x7EFD, + (q15_t)0x0FAB, (q15_t)0x7F09, (q15_t)0x0F47, (q15_t)0x7F15, + (q15_t)0x0EE3, (q15_t)0x7F21, (q15_t)0x0E7F, (q15_t)0x7F2D, + (q15_t)0x0E1B, (q15_t)0x7F38, (q15_t)0x0DB7, (q15_t)0x7F43, + (q15_t)0x0D53, (q15_t)0x7F4D, (q15_t)0x0CEF, (q15_t)0x7F58, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0C27, (q15_t)0x7F6B, + (q15_t)0x0BC3, (q15_t)0x7F75, (q15_t)0x0B5F, (q15_t)0x7F7E, + (q15_t)0x0AFB, (q15_t)0x7F87, (q15_t)0x0A97, (q15_t)0x7F8F, + (q15_t)0x0A33, (q15_t)0x7F97, (q15_t)0x09CE, (q15_t)0x7F9F, + (q15_t)0x096A, (q15_t)0x7FA7, (q15_t)0x0906, (q15_t)0x7FAE, + (q15_t)0x08A2, (q15_t)0x7FB5, (q15_t)0x083D, (q15_t)0x7FBC, + (q15_t)0x07D9, (q15_t)0x7FC2, (q15_t)0x0775, (q15_t)0x7FC8, + (q15_t)0x0710, (q15_t)0x7FCE, (q15_t)0x06AC, (q15_t)0x7FD3, + (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x05E3, (q15_t)0x7FDD, + (q15_t)0x057F, (q15_t)0x7FE1, (q15_t)0x051A, (q15_t)0x7FE5, + (q15_t)0x04B6, (q15_t)0x7FE9, (q15_t)0x0451, (q15_t)0x7FED, + (q15_t)0x03ED, (q15_t)0x7FF0, (q15_t)0x0388, (q15_t)0x7FF3, + (q15_t)0x0324, (q15_t)0x7FF6, (q15_t)0x02BF, (q15_t)0x7FF8, + (q15_t)0x025B, (q15_t)0x7FFA, (q15_t)0x01F6, (q15_t)0x7FFC, + (q15_t)0x0192, (q15_t)0x7FFD, (q15_t)0x012D, (q15_t)0x7FFE, + (q15_t)0x00C9, (q15_t)0x7FFF, (q15_t)0x0064, (q15_t)0x7FFF, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFF9B, (q15_t)0x7FFF, + (q15_t)0xFF36, (q15_t)0x7FFF, (q15_t)0xFED2, (q15_t)0x7FFE, + (q15_t)0xFE6D, (q15_t)0x7FFD, (q15_t)0xFE09, (q15_t)0x7FFC, + (q15_t)0xFDA4, (q15_t)0x7FFA, (q15_t)0xFD40, (q15_t)0x7FF8, + (q15_t)0xFCDB, (q15_t)0x7FF6, (q15_t)0xFC77, (q15_t)0x7FF3, + (q15_t)0xFC12, (q15_t)0x7FF0, (q15_t)0xFBAE, (q15_t)0x7FED, + (q15_t)0xFB49, (q15_t)0x7FE9, (q15_t)0xFAE5, (q15_t)0x7FE5, + (q15_t)0xFA80, (q15_t)0x7FE1, (q15_t)0xFA1C, (q15_t)0x7FDD, + (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF953, (q15_t)0x7FD3, + (q15_t)0xF8EF, (q15_t)0x7FCE, (q15_t)0xF88A, (q15_t)0x7FC8, + (q15_t)0xF826, (q15_t)0x7FC2, (q15_t)0xF7C2, (q15_t)0x7FBC, + (q15_t)0xF75D, (q15_t)0x7FB5, (q15_t)0xF6F9, (q15_t)0x7FAE, + (q15_t)0xF695, (q15_t)0x7FA7, (q15_t)0xF631, (q15_t)0x7F9F, + (q15_t)0xF5CC, (q15_t)0x7F97, (q15_t)0xF568, (q15_t)0x7F8F, + (q15_t)0xF504, (q15_t)0x7F87, (q15_t)0xF4A0, (q15_t)0x7F7E, + (q15_t)0xF43C, (q15_t)0x7F75, (q15_t)0xF3D8, (q15_t)0x7F6B, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF310, (q15_t)0x7F58, + (q15_t)0xF2AC, (q15_t)0x7F4D, (q15_t)0xF248, (q15_t)0x7F43, + (q15_t)0xF1E4, (q15_t)0x7F38, (q15_t)0xF180, (q15_t)0x7F2D, + (q15_t)0xF11C, (q15_t)0x7F21, (q15_t)0xF0B8, (q15_t)0x7F15, + (q15_t)0xF054, (q15_t)0x7F09, (q15_t)0xEFF1, (q15_t)0x7EFD, + (q15_t)0xEF8D, (q15_t)0x7EF0, (q15_t)0xEF29, (q15_t)0x7EE3, + (q15_t)0xEEC6, (q15_t)0x7ED5, (q15_t)0xEE62, (q15_t)0x7EC8, + (q15_t)0xEDFE, (q15_t)0x7EBA, (q15_t)0xED9B, (q15_t)0x7EAB, + (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xECD4, (q15_t)0x7E8E, + (q15_t)0xEC71, (q15_t)0x7E7F, (q15_t)0xEC0D, (q15_t)0x7E6F, + (q15_t)0xEBAA, (q15_t)0x7E5F, (q15_t)0xEB47, (q15_t)0x7E4F, + (q15_t)0xEAE4, (q15_t)0x7E3F, (q15_t)0xEA80, (q15_t)0x7E2E, + (q15_t)0xEA1D, (q15_t)0x7E1D, (q15_t)0xE9BA, (q15_t)0x7E0C, + (q15_t)0xE957, (q15_t)0x7DFA, (q15_t)0xE8F5, (q15_t)0x7DE8, + (q15_t)0xE892, (q15_t)0x7DD6, (q15_t)0xE82F, (q15_t)0x7DC3, + (q15_t)0xE7CC, (q15_t)0x7DB0, (q15_t)0xE769, (q15_t)0x7D9D, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE6A4, (q15_t)0x7D76, + (q15_t)0xE642, (q15_t)0x7D62, (q15_t)0xE5DF, (q15_t)0x7D4E, + (q15_t)0xE57D, (q15_t)0x7D39, (q15_t)0xE51B, (q15_t)0x7D24, + (q15_t)0xE4B8, (q15_t)0x7D0F, (q15_t)0xE456, (q15_t)0x7CF9, + (q15_t)0xE3F4, (q15_t)0x7CE3, (q15_t)0xE392, (q15_t)0x7CCD, + (q15_t)0xE330, (q15_t)0x7CB7, (q15_t)0xE2CE, (q15_t)0x7CA0, + (q15_t)0xE26C, (q15_t)0x7C89, (q15_t)0xE20A, (q15_t)0x7C71, + (q15_t)0xE1A9, (q15_t)0x7C5A, (q15_t)0xE147, (q15_t)0x7C42, + (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xE084, (q15_t)0x7C11, + (q15_t)0xE023, (q15_t)0x7BF8, (q15_t)0xDFC1, (q15_t)0x7BDF, + (q15_t)0xDF60, (q15_t)0x7BC5, (q15_t)0xDEFF, (q15_t)0x7BAC, + (q15_t)0xDE9E, (q15_t)0x7B92, (q15_t)0xDE3D, (q15_t)0x7B77, + (q15_t)0xDDDC, (q15_t)0x7B5D, (q15_t)0xDD7B, (q15_t)0x7B42, + (q15_t)0xDD1A, (q15_t)0x7B26, (q15_t)0xDCBA, (q15_t)0x7B0B, + (q15_t)0xDC59, (q15_t)0x7AEF, (q15_t)0xDBF8, (q15_t)0x7AD3, + (q15_t)0xDB98, (q15_t)0x7AB6, (q15_t)0xDB38, (q15_t)0x7A9A, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xDA77, (q15_t)0x7A5F, + (q15_t)0xDA17, (q15_t)0x7A42, (q15_t)0xD9B7, (q15_t)0x7A24, + (q15_t)0xD957, (q15_t)0x7A05, (q15_t)0xD8F8, (q15_t)0x79E7, + (q15_t)0xD898, (q15_t)0x79C8, (q15_t)0xD838, (q15_t)0x79A9, + (q15_t)0xD7D9, (q15_t)0x798A, (q15_t)0xD779, (q15_t)0x796A, + (q15_t)0xD71A, (q15_t)0x794A, (q15_t)0xD6BB, (q15_t)0x792A, + (q15_t)0xD65C, (q15_t)0x7909, (q15_t)0xD5FD, (q15_t)0x78E8, + (q15_t)0xD59E, (q15_t)0x78C7, (q15_t)0xD53F, (q15_t)0x78A6, + (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD482, (q15_t)0x7862, + (q15_t)0xD423, (q15_t)0x7840, (q15_t)0xD3C5, (q15_t)0x781D, + (q15_t)0xD367, (q15_t)0x77FA, (q15_t)0xD308, (q15_t)0x77D7, + (q15_t)0xD2AA, (q15_t)0x77B4, (q15_t)0xD24C, (q15_t)0x7790, + (q15_t)0xD1EE, (q15_t)0x776C, (q15_t)0xD191, (q15_t)0x7747, + (q15_t)0xD133, (q15_t)0x7723, (q15_t)0xD0D6, (q15_t)0x76FE, + (q15_t)0xD078, (q15_t)0x76D9, (q15_t)0xD01B, (q15_t)0x76B3, + (q15_t)0xCFBE, (q15_t)0x768E, (q15_t)0xCF61, (q15_t)0x7668, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCEA7, (q15_t)0x761B, + (q15_t)0xCE4A, (q15_t)0x75F4, (q15_t)0xCDEE, (q15_t)0x75CC, + (q15_t)0xCD91, (q15_t)0x75A5, (q15_t)0xCD35, (q15_t)0x757D, + (q15_t)0xCCD9, (q15_t)0x7555, (q15_t)0xCC7D, (q15_t)0x752D, + (q15_t)0xCC21, (q15_t)0x7504, (q15_t)0xCBC5, (q15_t)0x74DB, + (q15_t)0xCB69, (q15_t)0x74B2, (q15_t)0xCB0D, (q15_t)0x7489, + (q15_t)0xCAB2, (q15_t)0x745F, (q15_t)0xCA57, (q15_t)0x7435, + (q15_t)0xC9FB, (q15_t)0x740B, (q15_t)0xC9A0, (q15_t)0x73E0, + (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC8EB, (q15_t)0x738A, + (q15_t)0xC890, (q15_t)0x735F, (q15_t)0xC835, (q15_t)0x7333, + (q15_t)0xC7DB, (q15_t)0x7307, (q15_t)0xC781, (q15_t)0x72DB, + (q15_t)0xC727, (q15_t)0x72AF, (q15_t)0xC6CD, (q15_t)0x7282, + (q15_t)0xC673, (q15_t)0x7255, (q15_t)0xC619, (q15_t)0x7227, + (q15_t)0xC5BF, (q15_t)0x71FA, (q15_t)0xC566, (q15_t)0x71CC, + (q15_t)0xC50D, (q15_t)0x719E, (q15_t)0xC4B3, (q15_t)0x716F, + (q15_t)0xC45A, (q15_t)0x7141, (q15_t)0xC402, (q15_t)0x7112, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC350, (q15_t)0x70B3, + (q15_t)0xC2F8, (q15_t)0x7083, (q15_t)0xC29F, (q15_t)0x7053, + (q15_t)0xC247, (q15_t)0x7023, (q15_t)0xC1EF, (q15_t)0x6FF2, + (q15_t)0xC197, (q15_t)0x6FC1, (q15_t)0xC140, (q15_t)0x6F90, + (q15_t)0xC0E8, (q15_t)0x6F5F, (q15_t)0xC091, (q15_t)0x6F2D, + (q15_t)0xC03A, (q15_t)0x6EFB, (q15_t)0xBFE2, (q15_t)0x6EC9, + (q15_t)0xBF8C, (q15_t)0x6E96, (q15_t)0xBF35, (q15_t)0x6E63, + (q15_t)0xBEDE, (q15_t)0x6E30, (q15_t)0xBE88, (q15_t)0x6DFD, + (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBDDB, (q15_t)0x6D96, + (q15_t)0xBD85, (q15_t)0x6D62, (q15_t)0xBD2F, (q15_t)0x6D2D, + (q15_t)0xBCDA, (q15_t)0x6CF9, (q15_t)0xBC84, (q15_t)0x6CC4, + (q15_t)0xBC2F, (q15_t)0x6C8F, (q15_t)0xBBDA, (q15_t)0x6C59, + (q15_t)0xBB85, (q15_t)0x6C24, (q15_t)0xBB30, (q15_t)0x6BEE, + (q15_t)0xBADB, (q15_t)0x6BB8, (q15_t)0xBA87, (q15_t)0x6B81, + (q15_t)0xBA32, (q15_t)0x6B4A, (q15_t)0xB9DE, (q15_t)0x6B13, + (q15_t)0xB98A, (q15_t)0x6ADC, (q15_t)0xB936, (q15_t)0x6AA5, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB88F, (q15_t)0x6A35, + (q15_t)0xB83C, (q15_t)0x69FD, (q15_t)0xB7E9, (q15_t)0x69C4, + (q15_t)0xB796, (q15_t)0x698C, (q15_t)0xB743, (q15_t)0x6953, + (q15_t)0xB6F0, (q15_t)0x6919, (q15_t)0xB69E, (q15_t)0x68E0, + (q15_t)0xB64B, (q15_t)0x68A6, (q15_t)0xB5F9, (q15_t)0x686C, + (q15_t)0xB5A7, (q15_t)0x6832, (q15_t)0xB556, (q15_t)0x67F7, + (q15_t)0xB504, (q15_t)0x67BD, (q15_t)0xB4B3, (q15_t)0x6782, + (q15_t)0xB461, (q15_t)0x6746, (q15_t)0xB410, (q15_t)0x670B, + (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB36F, (q15_t)0x6693, + (q15_t)0xB31E, (q15_t)0x6657, (q15_t)0xB2CE, (q15_t)0x661A, + (q15_t)0xB27E, (q15_t)0x65DD, (q15_t)0xB22E, (q15_t)0x65A0, + (q15_t)0xB1DE, (q15_t)0x6563, (q15_t)0xB18F, (q15_t)0x6526, + (q15_t)0xB140, (q15_t)0x64E8, (q15_t)0xB0F0, (q15_t)0x64AA, + (q15_t)0xB0A1, (q15_t)0x646C, (q15_t)0xB053, (q15_t)0x642D, + (q15_t)0xB004, (q15_t)0x63EF, (q15_t)0xAFB6, (q15_t)0x63B0, + (q15_t)0xAF68, (q15_t)0x6371, (q15_t)0xAF1A, (q15_t)0x6331, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAE7E, (q15_t)0x62B2, + (q15_t)0xAE31, (q15_t)0x6271, (q15_t)0xADE3, (q15_t)0x6231, + (q15_t)0xAD96, (q15_t)0x61F1, (q15_t)0xAD4A, (q15_t)0x61B0, + (q15_t)0xACFD, (q15_t)0x616F, (q15_t)0xACB1, (q15_t)0x612D, + (q15_t)0xAC64, (q15_t)0x60EC, (q15_t)0xAC18, (q15_t)0x60AA, + (q15_t)0xABCC, (q15_t)0x6068, (q15_t)0xAB81, (q15_t)0x6026, + (q15_t)0xAB35, (q15_t)0x5FE3, (q15_t)0xAAEA, (q15_t)0x5FA0, + (q15_t)0xAA9F, (q15_t)0x5F5E, (q15_t)0xAA54, (q15_t)0x5F1A, + (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA9BF, (q15_t)0x5E93, + (q15_t)0xA975, (q15_t)0x5E50, (q15_t)0xA92B, (q15_t)0x5E0B, + (q15_t)0xA8E2, (q15_t)0x5DC7, (q15_t)0xA898, (q15_t)0x5D83, + (q15_t)0xA84F, (q15_t)0x5D3E, (q15_t)0xA806, (q15_t)0x5CF9, + (q15_t)0xA7BD, (q15_t)0x5CB4, (q15_t)0xA774, (q15_t)0x5C6E, + (q15_t)0xA72B, (q15_t)0x5C29, (q15_t)0xA6E3, (q15_t)0x5BE3, + (q15_t)0xA69B, (q15_t)0x5B9D, (q15_t)0xA653, (q15_t)0x5B56, + (q15_t)0xA60C, (q15_t)0x5B10, (q15_t)0xA5C4, (q15_t)0x5AC9, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA536, (q15_t)0x5A3B, + (q15_t)0xA4EF, (q15_t)0x59F3, (q15_t)0xA4A9, (q15_t)0x59AC, + (q15_t)0xA462, (q15_t)0x5964, (q15_t)0xA41C, (q15_t)0x591C, + (q15_t)0xA3D6, (q15_t)0x58D4, (q15_t)0xA391, (q15_t)0x588B, + (q15_t)0xA34B, (q15_t)0x5842, (q15_t)0xA306, (q15_t)0x57F9, + (q15_t)0xA2C1, (q15_t)0x57B0, (q15_t)0xA27C, (q15_t)0x5767, + (q15_t)0xA238, (q15_t)0x571D, (q15_t)0xA1F4, (q15_t)0x56D4, + (q15_t)0xA1AF, (q15_t)0x568A, (q15_t)0xA16C, (q15_t)0x5640, + (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0xA0E5, (q15_t)0x55AB, + (q15_t)0xA0A1, (q15_t)0x5560, (q15_t)0xA05F, (q15_t)0x5515, + (q15_t)0xA01C, (q15_t)0x54CA, (q15_t)0x9FD9, (q15_t)0x547E, + (q15_t)0x9F97, (q15_t)0x5433, (q15_t)0x9F55, (q15_t)0x53E7, + (q15_t)0x9F13, (q15_t)0x539B, (q15_t)0x9ED2, (q15_t)0x534E, + (q15_t)0x9E90, (q15_t)0x5302, (q15_t)0x9E4F, (q15_t)0x52B5, + (q15_t)0x9E0E, (q15_t)0x5269, (q15_t)0x9DCE, (q15_t)0x521C, + (q15_t)0x9D8E, (q15_t)0x51CE, (q15_t)0x9D4D, (q15_t)0x5181, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9CCE, (q15_t)0x50E5, + (q15_t)0x9C8E, (q15_t)0x5097, (q15_t)0x9C4F, (q15_t)0x5049, + (q15_t)0x9C10, (q15_t)0x4FFB, (q15_t)0x9BD2, (q15_t)0x4FAC, + (q15_t)0x9B93, (q15_t)0x4F5E, (q15_t)0x9B55, (q15_t)0x4F0F, + (q15_t)0x9B17, (q15_t)0x4EBF, (q15_t)0x9AD9, (q15_t)0x4E70, + (q15_t)0x9A9C, (q15_t)0x4E21, (q15_t)0x9A5F, (q15_t)0x4DD1, + (q15_t)0x9A22, (q15_t)0x4D81, (q15_t)0x99E5, (q15_t)0x4D31, + (q15_t)0x99A8, (q15_t)0x4CE1, (q15_t)0x996C, (q15_t)0x4C90, + (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x98F4, (q15_t)0x4BEF, + (q15_t)0x98B9, (q15_t)0x4B9E, (q15_t)0x987D, (q15_t)0x4B4C, + (q15_t)0x9842, (q15_t)0x4AFB, (q15_t)0x9808, (q15_t)0x4AA9, + (q15_t)0x97CD, (q15_t)0x4A58, (q15_t)0x9793, (q15_t)0x4A06, + (q15_t)0x9759, (q15_t)0x49B4, (q15_t)0x971F, (q15_t)0x4961, + (q15_t)0x96E6, (q15_t)0x490F, (q15_t)0x96AC, (q15_t)0x48BC, + (q15_t)0x9673, (q15_t)0x4869, (q15_t)0x963B, (q15_t)0x4816, + (q15_t)0x9602, (q15_t)0x47C3, (q15_t)0x95CA, (q15_t)0x4770, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x955A, (q15_t)0x46C9, + (q15_t)0x9523, (q15_t)0x4675, (q15_t)0x94EC, (q15_t)0x4621, + (q15_t)0x94B5, (q15_t)0x45CD, (q15_t)0x947E, (q15_t)0x4578, + (q15_t)0x9447, (q15_t)0x4524, (q15_t)0x9411, (q15_t)0x44CF, + (q15_t)0x93DB, (q15_t)0x447A, (q15_t)0x93A6, (q15_t)0x4425, + (q15_t)0x9370, (q15_t)0x43D0, (q15_t)0x933B, (q15_t)0x437B, + (q15_t)0x9306, (q15_t)0x4325, (q15_t)0x92D2, (q15_t)0x42D0, + (q15_t)0x929D, (q15_t)0x427A, (q15_t)0x9269, (q15_t)0x4224, + (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x9202, (q15_t)0x4177, + (q15_t)0x91CF, (q15_t)0x4121, (q15_t)0x919C, (q15_t)0x40CA, + (q15_t)0x9169, (q15_t)0x4073, (q15_t)0x9136, (q15_t)0x401D, + (q15_t)0x9104, (q15_t)0x3FC5, (q15_t)0x90D2, (q15_t)0x3F6E, + (q15_t)0x90A0, (q15_t)0x3F17, (q15_t)0x906F, (q15_t)0x3EBF, + (q15_t)0x903E, (q15_t)0x3E68, (q15_t)0x900D, (q15_t)0x3E10, + (q15_t)0x8FDC, (q15_t)0x3DB8, (q15_t)0x8FAC, (q15_t)0x3D60, + (q15_t)0x8F7C, (q15_t)0x3D07, (q15_t)0x8F4C, (q15_t)0x3CAF, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8EED, (q15_t)0x3BFD, + (q15_t)0x8EBE, (q15_t)0x3BA5, (q15_t)0x8E90, (q15_t)0x3B4C, + (q15_t)0x8E61, (q15_t)0x3AF2, (q15_t)0x8E33, (q15_t)0x3A99, + (q15_t)0x8E05, (q15_t)0x3A40, (q15_t)0x8DD8, (q15_t)0x39E6, + (q15_t)0x8DAA, (q15_t)0x398C, (q15_t)0x8D7D, (q15_t)0x3932, + (q15_t)0x8D50, (q15_t)0x38D8, (q15_t)0x8D24, (q15_t)0x387E, + (q15_t)0x8CF8, (q15_t)0x3824, (q15_t)0x8CCC, (q15_t)0x37CA, + (q15_t)0x8CA0, (q15_t)0x376F, (q15_t)0x8C75, (q15_t)0x3714, + (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8C1F, (q15_t)0x365F, + (q15_t)0x8BF4, (q15_t)0x3604, (q15_t)0x8BCA, (q15_t)0x35A8, + (q15_t)0x8BA0, (q15_t)0x354D, (q15_t)0x8B76, (q15_t)0x34F2, + (q15_t)0x8B4D, (q15_t)0x3496, (q15_t)0x8B24, (q15_t)0x343A, + (q15_t)0x8AFB, (q15_t)0x33DE, (q15_t)0x8AD2, (q15_t)0x3382, + (q15_t)0x8AAA, (q15_t)0x3326, (q15_t)0x8A82, (q15_t)0x32CA, + (q15_t)0x8A5A, (q15_t)0x326E, (q15_t)0x8A33, (q15_t)0x3211, + (q15_t)0x8A0B, (q15_t)0x31B5, (q15_t)0x89E4, (q15_t)0x3158, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8997, (q15_t)0x309E, + (q15_t)0x8971, (q15_t)0x3041, (q15_t)0x894C, (q15_t)0x2FE4, + (q15_t)0x8926, (q15_t)0x2F87, (q15_t)0x8901, (q15_t)0x2F29, + (q15_t)0x88DC, (q15_t)0x2ECC, (q15_t)0x88B8, (q15_t)0x2E6E, + (q15_t)0x8893, (q15_t)0x2E11, (q15_t)0x886F, (q15_t)0x2DB3, + (q15_t)0x884B, (q15_t)0x2D55, (q15_t)0x8828, (q15_t)0x2CF7, + (q15_t)0x8805, (q15_t)0x2C98, (q15_t)0x87E2, (q15_t)0x2C3A, + (q15_t)0x87BF, (q15_t)0x2BDC, (q15_t)0x879D, (q15_t)0x2B7D, + (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x8759, (q15_t)0x2AC0, + (q15_t)0x8738, (q15_t)0x2A61, (q15_t)0x8717, (q15_t)0x2A02, + (q15_t)0x86F6, (q15_t)0x29A3, (q15_t)0x86D5, (q15_t)0x2944, + (q15_t)0x86B5, (q15_t)0x28E5, (q15_t)0x8695, (q15_t)0x2886, + (q15_t)0x8675, (q15_t)0x2826, (q15_t)0x8656, (q15_t)0x27C7, + (q15_t)0x8637, (q15_t)0x2767, (q15_t)0x8618, (q15_t)0x2707, + (q15_t)0x85FA, (q15_t)0x26A8, (q15_t)0x85DB, (q15_t)0x2648, + (q15_t)0x85BD, (q15_t)0x25E8, (q15_t)0x85A0, (q15_t)0x2588, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x8565, (q15_t)0x24C7, + (q15_t)0x8549, (q15_t)0x2467, (q15_t)0x852C, (q15_t)0x2407, + (q15_t)0x8510, (q15_t)0x23A6, (q15_t)0x84F4, (q15_t)0x2345, + (q15_t)0x84D9, (q15_t)0x22E5, (q15_t)0x84BD, (q15_t)0x2284, + (q15_t)0x84A2, (q15_t)0x2223, (q15_t)0x8488, (q15_t)0x21C2, + (q15_t)0x846D, (q15_t)0x2161, (q15_t)0x8453, (q15_t)0x2100, + (q15_t)0x843A, (q15_t)0x209F, (q15_t)0x8420, (q15_t)0x203E, + (q15_t)0x8407, (q15_t)0x1FDC, (q15_t)0x83EE, (q15_t)0x1F7B, + (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x83BD, (q15_t)0x1EB8, + (q15_t)0x83A5, (q15_t)0x1E56, (q15_t)0x838E, (q15_t)0x1DF5, + (q15_t)0x8376, (q15_t)0x1D93, (q15_t)0x835F, (q15_t)0x1D31, + (q15_t)0x8348, (q15_t)0x1CCF, (q15_t)0x8332, (q15_t)0x1C6D, + (q15_t)0x831C, (q15_t)0x1C0B, (q15_t)0x8306, (q15_t)0x1BA9, + (q15_t)0x82F0, (q15_t)0x1B47, (q15_t)0x82DB, (q15_t)0x1AE4, + (q15_t)0x82C6, (q15_t)0x1A82, (q15_t)0x82B1, (q15_t)0x1A20, + (q15_t)0x829D, (q15_t)0x19BD, (q15_t)0x8289, (q15_t)0x195B, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x8262, (q15_t)0x1896, + (q15_t)0x824F, (q15_t)0x1833, (q15_t)0x823C, (q15_t)0x17D0, + (q15_t)0x8229, (q15_t)0x176D, (q15_t)0x8217, (q15_t)0x170A, + (q15_t)0x8205, (q15_t)0x16A8, (q15_t)0x81F3, (q15_t)0x1645, + (q15_t)0x81E2, (q15_t)0x15E2, (q15_t)0x81D1, (q15_t)0x157F, + (q15_t)0x81C0, (q15_t)0x151B, (q15_t)0x81B0, (q15_t)0x14B8, + (q15_t)0x81A0, (q15_t)0x1455, (q15_t)0x8190, (q15_t)0x13F2, + (q15_t)0x8180, (q15_t)0x138E, (q15_t)0x8171, (q15_t)0x132B, + (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x8154, (q15_t)0x1264, + (q15_t)0x8145, (q15_t)0x1201, (q15_t)0x8137, (q15_t)0x119D, + (q15_t)0x812A, (q15_t)0x1139, (q15_t)0x811C, (q15_t)0x10D6, + (q15_t)0x810F, (q15_t)0x1072, (q15_t)0x8102, (q15_t)0x100E, + (q15_t)0x80F6, (q15_t)0x0FAB, (q15_t)0x80EA, (q15_t)0x0F47, + (q15_t)0x80DE, (q15_t)0x0EE3, (q15_t)0x80D2, (q15_t)0x0E7F, + (q15_t)0x80C7, (q15_t)0x0E1B, (q15_t)0x80BC, (q15_t)0x0DB7, + (q15_t)0x80B2, (q15_t)0x0D53, (q15_t)0x80A7, (q15_t)0x0CEF, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8094, (q15_t)0x0C27, + (q15_t)0x808A, (q15_t)0x0BC3, (q15_t)0x8081, (q15_t)0x0B5F, + (q15_t)0x8078, (q15_t)0x0AFB, (q15_t)0x8070, (q15_t)0x0A97, + (q15_t)0x8068, (q15_t)0x0A33, (q15_t)0x8060, (q15_t)0x09CE, + (q15_t)0x8058, (q15_t)0x096A, (q15_t)0x8051, (q15_t)0x0906, + (q15_t)0x804A, (q15_t)0x08A2, (q15_t)0x8043, (q15_t)0x083D, + (q15_t)0x803D, (q15_t)0x07D9, (q15_t)0x8037, (q15_t)0x0775, + (q15_t)0x8031, (q15_t)0x0710, (q15_t)0x802C, (q15_t)0x06AC, + (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8022, (q15_t)0x05E3, + (q15_t)0x801E, (q15_t)0x057F, (q15_t)0x801A, (q15_t)0x051A, + (q15_t)0x8016, (q15_t)0x04B6, (q15_t)0x8012, (q15_t)0x0451, + (q15_t)0x800F, (q15_t)0x03ED, (q15_t)0x800C, (q15_t)0x0388, + (q15_t)0x8009, (q15_t)0x0324, (q15_t)0x8007, (q15_t)0x02BF, + (q15_t)0x8005, (q15_t)0x025B, (q15_t)0x8003, (q15_t)0x01F6, + (q15_t)0x8002, (q15_t)0x0192, (q15_t)0x8001, (q15_t)0x012D, + (q15_t)0x8000, (q15_t)0x00C9, (q15_t)0x8000, (q15_t)0x0064, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8000, (q15_t)0xFF9B, + (q15_t)0x8000, (q15_t)0xFF36, (q15_t)0x8001, (q15_t)0xFED2, + (q15_t)0x8002, (q15_t)0xFE6D, (q15_t)0x8003, (q15_t)0xFE09, + (q15_t)0x8005, (q15_t)0xFDA4, (q15_t)0x8007, (q15_t)0xFD40, + (q15_t)0x8009, (q15_t)0xFCDB, (q15_t)0x800C, (q15_t)0xFC77, + (q15_t)0x800F, (q15_t)0xFC12, (q15_t)0x8012, (q15_t)0xFBAE, + (q15_t)0x8016, (q15_t)0xFB49, (q15_t)0x801A, (q15_t)0xFAE5, + (q15_t)0x801E, (q15_t)0xFA80, (q15_t)0x8022, (q15_t)0xFA1C, + (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x802C, (q15_t)0xF953, + (q15_t)0x8031, (q15_t)0xF8EF, (q15_t)0x8037, (q15_t)0xF88A, + (q15_t)0x803D, (q15_t)0xF826, (q15_t)0x8043, (q15_t)0xF7C2, + (q15_t)0x804A, (q15_t)0xF75D, (q15_t)0x8051, (q15_t)0xF6F9, + (q15_t)0x8058, (q15_t)0xF695, (q15_t)0x8060, (q15_t)0xF631, + (q15_t)0x8068, (q15_t)0xF5CC, (q15_t)0x8070, (q15_t)0xF568, + (q15_t)0x8078, (q15_t)0xF504, (q15_t)0x8081, (q15_t)0xF4A0, + (q15_t)0x808A, (q15_t)0xF43C, (q15_t)0x8094, (q15_t)0xF3D8, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80A7, (q15_t)0xF310, + (q15_t)0x80B2, (q15_t)0xF2AC, (q15_t)0x80BC, (q15_t)0xF248, + (q15_t)0x80C7, (q15_t)0xF1E4, (q15_t)0x80D2, (q15_t)0xF180, + (q15_t)0x80DE, (q15_t)0xF11C, (q15_t)0x80EA, (q15_t)0xF0B8, + (q15_t)0x80F6, (q15_t)0xF054, (q15_t)0x8102, (q15_t)0xEFF1, + (q15_t)0x810F, (q15_t)0xEF8D, (q15_t)0x811C, (q15_t)0xEF29, + (q15_t)0x812A, (q15_t)0xEEC6, (q15_t)0x8137, (q15_t)0xEE62, + (q15_t)0x8145, (q15_t)0xEDFE, (q15_t)0x8154, (q15_t)0xED9B, + (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x8171, (q15_t)0xECD4, + (q15_t)0x8180, (q15_t)0xEC71, (q15_t)0x8190, (q15_t)0xEC0D, + (q15_t)0x81A0, (q15_t)0xEBAA, (q15_t)0x81B0, (q15_t)0xEB47, + (q15_t)0x81C0, (q15_t)0xEAE4, (q15_t)0x81D1, (q15_t)0xEA80, + (q15_t)0x81E2, (q15_t)0xEA1D, (q15_t)0x81F3, (q15_t)0xE9BA, + (q15_t)0x8205, (q15_t)0xE957, (q15_t)0x8217, (q15_t)0xE8F5, + (q15_t)0x8229, (q15_t)0xE892, (q15_t)0x823C, (q15_t)0xE82F, + (q15_t)0x824F, (q15_t)0xE7CC, (q15_t)0x8262, (q15_t)0xE769, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x8289, (q15_t)0xE6A4, + (q15_t)0x829D, (q15_t)0xE642, (q15_t)0x82B1, (q15_t)0xE5DF, + (q15_t)0x82C6, (q15_t)0xE57D, (q15_t)0x82DB, (q15_t)0xE51B, + (q15_t)0x82F0, (q15_t)0xE4B8, (q15_t)0x8306, (q15_t)0xE456, + (q15_t)0x831C, (q15_t)0xE3F4, (q15_t)0x8332, (q15_t)0xE392, + (q15_t)0x8348, (q15_t)0xE330, (q15_t)0x835F, (q15_t)0xE2CE, + (q15_t)0x8376, (q15_t)0xE26C, (q15_t)0x838E, (q15_t)0xE20A, + (q15_t)0x83A5, (q15_t)0xE1A9, (q15_t)0x83BD, (q15_t)0xE147, + (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x83EE, (q15_t)0xE084, + (q15_t)0x8407, (q15_t)0xE023, (q15_t)0x8420, (q15_t)0xDFC1, + (q15_t)0x843A, (q15_t)0xDF60, (q15_t)0x8453, (q15_t)0xDEFF, + (q15_t)0x846D, (q15_t)0xDE9E, (q15_t)0x8488, (q15_t)0xDE3D, + (q15_t)0x84A2, (q15_t)0xDDDC, (q15_t)0x84BD, (q15_t)0xDD7B, + (q15_t)0x84D9, (q15_t)0xDD1A, (q15_t)0x84F4, (q15_t)0xDCBA, + (q15_t)0x8510, (q15_t)0xDC59, (q15_t)0x852C, (q15_t)0xDBF8, + (q15_t)0x8549, (q15_t)0xDB98, (q15_t)0x8565, (q15_t)0xDB38, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x85A0, (q15_t)0xDA77, + (q15_t)0x85BD, (q15_t)0xDA17, (q15_t)0x85DB, (q15_t)0xD9B7, + (q15_t)0x85FA, (q15_t)0xD957, (q15_t)0x8618, (q15_t)0xD8F8, + (q15_t)0x8637, (q15_t)0xD898, (q15_t)0x8656, (q15_t)0xD838, + (q15_t)0x8675, (q15_t)0xD7D9, (q15_t)0x8695, (q15_t)0xD779, + (q15_t)0x86B5, (q15_t)0xD71A, (q15_t)0x86D5, (q15_t)0xD6BB, + (q15_t)0x86F6, (q15_t)0xD65C, (q15_t)0x8717, (q15_t)0xD5FD, + (q15_t)0x8738, (q15_t)0xD59E, (q15_t)0x8759, (q15_t)0xD53F, + (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x879D, (q15_t)0xD482, + (q15_t)0x87BF, (q15_t)0xD423, (q15_t)0x87E2, (q15_t)0xD3C5, + (q15_t)0x8805, (q15_t)0xD367, (q15_t)0x8828, (q15_t)0xD308, + (q15_t)0x884B, (q15_t)0xD2AA, (q15_t)0x886F, (q15_t)0xD24C, + (q15_t)0x8893, (q15_t)0xD1EE, (q15_t)0x88B8, (q15_t)0xD191, + (q15_t)0x88DC, (q15_t)0xD133, (q15_t)0x8901, (q15_t)0xD0D6, + (q15_t)0x8926, (q15_t)0xD078, (q15_t)0x894C, (q15_t)0xD01B, + (q15_t)0x8971, (q15_t)0xCFBE, (q15_t)0x8997, (q15_t)0xCF61, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x89E4, (q15_t)0xCEA7, + (q15_t)0x8A0B, (q15_t)0xCE4A, (q15_t)0x8A33, (q15_t)0xCDEE, + (q15_t)0x8A5A, (q15_t)0xCD91, (q15_t)0x8A82, (q15_t)0xCD35, + (q15_t)0x8AAA, (q15_t)0xCCD9, (q15_t)0x8AD2, (q15_t)0xCC7D, + (q15_t)0x8AFB, (q15_t)0xCC21, (q15_t)0x8B24, (q15_t)0xCBC5, + (q15_t)0x8B4D, (q15_t)0xCB69, (q15_t)0x8B76, (q15_t)0xCB0D, + (q15_t)0x8BA0, (q15_t)0xCAB2, (q15_t)0x8BCA, (q15_t)0xCA57, + (q15_t)0x8BF4, (q15_t)0xC9FB, (q15_t)0x8C1F, (q15_t)0xC9A0, + (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8C75, (q15_t)0xC8EB, + (q15_t)0x8CA0, (q15_t)0xC890, (q15_t)0x8CCC, (q15_t)0xC835, + (q15_t)0x8CF8, (q15_t)0xC7DB, (q15_t)0x8D24, (q15_t)0xC781, + (q15_t)0x8D50, (q15_t)0xC727, (q15_t)0x8D7D, (q15_t)0xC6CD, + (q15_t)0x8DAA, (q15_t)0xC673, (q15_t)0x8DD8, (q15_t)0xC619, + (q15_t)0x8E05, (q15_t)0xC5BF, (q15_t)0x8E33, (q15_t)0xC566, + (q15_t)0x8E61, (q15_t)0xC50D, (q15_t)0x8E90, (q15_t)0xC4B3, + (q15_t)0x8EBE, (q15_t)0xC45A, (q15_t)0x8EED, (q15_t)0xC402, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x8F4C, (q15_t)0xC350, + (q15_t)0x8F7C, (q15_t)0xC2F8, (q15_t)0x8FAC, (q15_t)0xC29F, + (q15_t)0x8FDC, (q15_t)0xC247, (q15_t)0x900D, (q15_t)0xC1EF, + (q15_t)0x903E, (q15_t)0xC197, (q15_t)0x906F, (q15_t)0xC140, + (q15_t)0x90A0, (q15_t)0xC0E8, (q15_t)0x90D2, (q15_t)0xC091, + (q15_t)0x9104, (q15_t)0xC03A, (q15_t)0x9136, (q15_t)0xBFE2, + (q15_t)0x9169, (q15_t)0xBF8C, (q15_t)0x919C, (q15_t)0xBF35, + (q15_t)0x91CF, (q15_t)0xBEDE, (q15_t)0x9202, (q15_t)0xBE88, + (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x9269, (q15_t)0xBDDB, + (q15_t)0x929D, (q15_t)0xBD85, (q15_t)0x92D2, (q15_t)0xBD2F, + (q15_t)0x9306, (q15_t)0xBCDA, (q15_t)0x933B, (q15_t)0xBC84, + (q15_t)0x9370, (q15_t)0xBC2F, (q15_t)0x93A6, (q15_t)0xBBDA, + (q15_t)0x93DB, (q15_t)0xBB85, (q15_t)0x9411, (q15_t)0xBB30, + (q15_t)0x9447, (q15_t)0xBADB, (q15_t)0x947E, (q15_t)0xBA87, + (q15_t)0x94B5, (q15_t)0xBA32, (q15_t)0x94EC, (q15_t)0xB9DE, + (q15_t)0x9523, (q15_t)0xB98A, (q15_t)0x955A, (q15_t)0xB936, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x95CA, (q15_t)0xB88F, + (q15_t)0x9602, (q15_t)0xB83C, (q15_t)0x963B, (q15_t)0xB7E9, + (q15_t)0x9673, (q15_t)0xB796, (q15_t)0x96AC, (q15_t)0xB743, + (q15_t)0x96E6, (q15_t)0xB6F0, (q15_t)0x971F, (q15_t)0xB69E, + (q15_t)0x9759, (q15_t)0xB64B, (q15_t)0x9793, (q15_t)0xB5F9, + (q15_t)0x97CD, (q15_t)0xB5A7, (q15_t)0x9808, (q15_t)0xB556, + (q15_t)0x9842, (q15_t)0xB504, (q15_t)0x987D, (q15_t)0xB4B3, + (q15_t)0x98B9, (q15_t)0xB461, (q15_t)0x98F4, (q15_t)0xB410, + (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x996C, (q15_t)0xB36F, + (q15_t)0x99A8, (q15_t)0xB31E, (q15_t)0x99E5, (q15_t)0xB2CE, + (q15_t)0x9A22, (q15_t)0xB27E, (q15_t)0x9A5F, (q15_t)0xB22E, + (q15_t)0x9A9C, (q15_t)0xB1DE, (q15_t)0x9AD9, (q15_t)0xB18F, + (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9B55, (q15_t)0xB0F0, + (q15_t)0x9B93, (q15_t)0xB0A1, (q15_t)0x9BD2, (q15_t)0xB053, + (q15_t)0x9C10, (q15_t)0xB004, (q15_t)0x9C4F, (q15_t)0xAFB6, + (q15_t)0x9C8E, (q15_t)0xAF68, (q15_t)0x9CCE, (q15_t)0xAF1A, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9D4D, (q15_t)0xAE7E, + (q15_t)0x9D8E, (q15_t)0xAE31, (q15_t)0x9DCE, (q15_t)0xADE3, + (q15_t)0x9E0E, (q15_t)0xAD96, (q15_t)0x9E4F, (q15_t)0xAD4A, + (q15_t)0x9E90, (q15_t)0xACFD, (q15_t)0x9ED2, (q15_t)0xACB1, + (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0x9F55, (q15_t)0xAC18, + (q15_t)0x9F97, (q15_t)0xABCC, (q15_t)0x9FD9, (q15_t)0xAB81, + (q15_t)0xA01C, (q15_t)0xAB35, (q15_t)0xA05F, (q15_t)0xAAEA, + (q15_t)0xA0A1, (q15_t)0xAA9F, (q15_t)0xA0E5, (q15_t)0xAA54, + (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA16C, (q15_t)0xA9BF, + (q15_t)0xA1AF, (q15_t)0xA975, (q15_t)0xA1F4, (q15_t)0xA92B, + (q15_t)0xA238, (q15_t)0xA8E2, (q15_t)0xA27C, (q15_t)0xA898, + (q15_t)0xA2C1, (q15_t)0xA84F, (q15_t)0xA306, (q15_t)0xA806, + (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA391, (q15_t)0xA774, + (q15_t)0xA3D6, (q15_t)0xA72B, (q15_t)0xA41C, (q15_t)0xA6E3, + (q15_t)0xA462, (q15_t)0xA69B, (q15_t)0xA4A9, (q15_t)0xA653, + (q15_t)0xA4EF, (q15_t)0xA60C, (q15_t)0xA536, (q15_t)0xA5C4, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA5C4, (q15_t)0xA536, + (q15_t)0xA60C, (q15_t)0xA4EF, (q15_t)0xA653, (q15_t)0xA4A9, + (q15_t)0xA69B, (q15_t)0xA462, (q15_t)0xA6E3, (q15_t)0xA41C, + (q15_t)0xA72B, (q15_t)0xA3D6, (q15_t)0xA774, (q15_t)0xA391, + (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA806, (q15_t)0xA306, + (q15_t)0xA84F, (q15_t)0xA2C1, (q15_t)0xA898, (q15_t)0xA27C, + (q15_t)0xA8E2, (q15_t)0xA238, (q15_t)0xA92B, (q15_t)0xA1F4, + (q15_t)0xA975, (q15_t)0xA1AF, (q15_t)0xA9BF, (q15_t)0xA16C, + (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAA54, (q15_t)0xA0E5, + (q15_t)0xAA9F, (q15_t)0xA0A1, (q15_t)0xAAEA, (q15_t)0xA05F, + (q15_t)0xAB35, (q15_t)0xA01C, (q15_t)0xAB81, (q15_t)0x9FD9, + (q15_t)0xABCC, (q15_t)0x9F97, (q15_t)0xAC18, (q15_t)0x9F55, + (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xACB1, (q15_t)0x9ED2, + (q15_t)0xACFD, (q15_t)0x9E90, (q15_t)0xAD4A, (q15_t)0x9E4F, + (q15_t)0xAD96, (q15_t)0x9E0E, (q15_t)0xADE3, (q15_t)0x9DCE, + (q15_t)0xAE31, (q15_t)0x9D8E, (q15_t)0xAE7E, (q15_t)0x9D4D, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xAF1A, (q15_t)0x9CCE, + (q15_t)0xAF68, (q15_t)0x9C8E, (q15_t)0xAFB6, (q15_t)0x9C4F, + (q15_t)0xB004, (q15_t)0x9C10, (q15_t)0xB053, (q15_t)0x9BD2, + (q15_t)0xB0A1, (q15_t)0x9B93, (q15_t)0xB0F0, (q15_t)0x9B55, + (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB18F, (q15_t)0x9AD9, + (q15_t)0xB1DE, (q15_t)0x9A9C, (q15_t)0xB22E, (q15_t)0x9A5F, + (q15_t)0xB27E, (q15_t)0x9A22, (q15_t)0xB2CE, (q15_t)0x99E5, + (q15_t)0xB31E, (q15_t)0x99A8, (q15_t)0xB36F, (q15_t)0x996C, + (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB410, (q15_t)0x98F4, + (q15_t)0xB461, (q15_t)0x98B9, (q15_t)0xB4B3, (q15_t)0x987D, + (q15_t)0xB504, (q15_t)0x9842, (q15_t)0xB556, (q15_t)0x9808, + (q15_t)0xB5A7, (q15_t)0x97CD, (q15_t)0xB5F9, (q15_t)0x9793, + (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB69E, (q15_t)0x971F, + (q15_t)0xB6F0, (q15_t)0x96E6, (q15_t)0xB743, (q15_t)0x96AC, + (q15_t)0xB796, (q15_t)0x9673, (q15_t)0xB7E9, (q15_t)0x963B, + (q15_t)0xB83C, (q15_t)0x9602, (q15_t)0xB88F, (q15_t)0x95CA, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xB936, (q15_t)0x955A, + (q15_t)0xB98A, (q15_t)0x9523, (q15_t)0xB9DE, (q15_t)0x94EC, + (q15_t)0xBA32, (q15_t)0x94B5, (q15_t)0xBA87, (q15_t)0x947E, + (q15_t)0xBADB, (q15_t)0x9447, (q15_t)0xBB30, (q15_t)0x9411, + (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBBDA, (q15_t)0x93A6, + (q15_t)0xBC2F, (q15_t)0x9370, (q15_t)0xBC84, (q15_t)0x933B, + (q15_t)0xBCDA, (q15_t)0x9306, (q15_t)0xBD2F, (q15_t)0x92D2, + (q15_t)0xBD85, (q15_t)0x929D, (q15_t)0xBDDB, (q15_t)0x9269, + (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBE88, (q15_t)0x9202, + (q15_t)0xBEDE, (q15_t)0x91CF, (q15_t)0xBF35, (q15_t)0x919C, + (q15_t)0xBF8C, (q15_t)0x9169, (q15_t)0xBFE2, (q15_t)0x9136, + (q15_t)0xC03A, (q15_t)0x9104, (q15_t)0xC091, (q15_t)0x90D2, + (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC140, (q15_t)0x906F, + (q15_t)0xC197, (q15_t)0x903E, (q15_t)0xC1EF, (q15_t)0x900D, + (q15_t)0xC247, (q15_t)0x8FDC, (q15_t)0xC29F, (q15_t)0x8FAC, + (q15_t)0xC2F8, (q15_t)0x8F7C, (q15_t)0xC350, (q15_t)0x8F4C, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC402, (q15_t)0x8EED, + (q15_t)0xC45A, (q15_t)0x8EBE, (q15_t)0xC4B3, (q15_t)0x8E90, + (q15_t)0xC50D, (q15_t)0x8E61, (q15_t)0xC566, (q15_t)0x8E33, + (q15_t)0xC5BF, (q15_t)0x8E05, (q15_t)0xC619, (q15_t)0x8DD8, + (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC6CD, (q15_t)0x8D7D, + (q15_t)0xC727, (q15_t)0x8D50, (q15_t)0xC781, (q15_t)0x8D24, + (q15_t)0xC7DB, (q15_t)0x8CF8, (q15_t)0xC835, (q15_t)0x8CCC, + (q15_t)0xC890, (q15_t)0x8CA0, (q15_t)0xC8EB, (q15_t)0x8C75, + (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xC9A0, (q15_t)0x8C1F, + (q15_t)0xC9FB, (q15_t)0x8BF4, (q15_t)0xCA57, (q15_t)0x8BCA, + (q15_t)0xCAB2, (q15_t)0x8BA0, (q15_t)0xCB0D, (q15_t)0x8B76, + (q15_t)0xCB69, (q15_t)0x8B4D, (q15_t)0xCBC5, (q15_t)0x8B24, + (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCC7D, (q15_t)0x8AD2, + (q15_t)0xCCD9, (q15_t)0x8AAA, (q15_t)0xCD35, (q15_t)0x8A82, + (q15_t)0xCD91, (q15_t)0x8A5A, (q15_t)0xCDEE, (q15_t)0x8A33, + (q15_t)0xCE4A, (q15_t)0x8A0B, (q15_t)0xCEA7, (q15_t)0x89E4, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xCF61, (q15_t)0x8997, + (q15_t)0xCFBE, (q15_t)0x8971, (q15_t)0xD01B, (q15_t)0x894C, + (q15_t)0xD078, (q15_t)0x8926, (q15_t)0xD0D6, (q15_t)0x8901, + (q15_t)0xD133, (q15_t)0x88DC, (q15_t)0xD191, (q15_t)0x88B8, + (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD24C, (q15_t)0x886F, + (q15_t)0xD2AA, (q15_t)0x884B, (q15_t)0xD308, (q15_t)0x8828, + (q15_t)0xD367, (q15_t)0x8805, (q15_t)0xD3C5, (q15_t)0x87E2, + (q15_t)0xD423, (q15_t)0x87BF, (q15_t)0xD482, (q15_t)0x879D, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD53F, (q15_t)0x8759, + (q15_t)0xD59E, (q15_t)0x8738, (q15_t)0xD5FD, (q15_t)0x8717, + (q15_t)0xD65C, (q15_t)0x86F6, (q15_t)0xD6BB, (q15_t)0x86D5, + (q15_t)0xD71A, (q15_t)0x86B5, (q15_t)0xD779, (q15_t)0x8695, + (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD838, (q15_t)0x8656, + (q15_t)0xD898, (q15_t)0x8637, (q15_t)0xD8F8, (q15_t)0x8618, + (q15_t)0xD957, (q15_t)0x85FA, (q15_t)0xD9B7, (q15_t)0x85DB, + (q15_t)0xDA17, (q15_t)0x85BD, (q15_t)0xDA77, (q15_t)0x85A0, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDB38, (q15_t)0x8565, + (q15_t)0xDB98, (q15_t)0x8549, (q15_t)0xDBF8, (q15_t)0x852C, + (q15_t)0xDC59, (q15_t)0x8510, (q15_t)0xDCBA, (q15_t)0x84F4, + (q15_t)0xDD1A, (q15_t)0x84D9, (q15_t)0xDD7B, (q15_t)0x84BD, + (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDE3D, (q15_t)0x8488, + (q15_t)0xDE9E, (q15_t)0x846D, (q15_t)0xDEFF, (q15_t)0x8453, + (q15_t)0xDF60, (q15_t)0x843A, (q15_t)0xDFC1, (q15_t)0x8420, + (q15_t)0xE023, (q15_t)0x8407, (q15_t)0xE084, (q15_t)0x83EE, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE147, (q15_t)0x83BD, + (q15_t)0xE1A9, (q15_t)0x83A5, (q15_t)0xE20A, (q15_t)0x838E, + (q15_t)0xE26C, (q15_t)0x8376, (q15_t)0xE2CE, (q15_t)0x835F, + (q15_t)0xE330, (q15_t)0x8348, (q15_t)0xE392, (q15_t)0x8332, + (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE456, (q15_t)0x8306, + (q15_t)0xE4B8, (q15_t)0x82F0, (q15_t)0xE51B, (q15_t)0x82DB, + (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE5DF, (q15_t)0x82B1, + (q15_t)0xE642, (q15_t)0x829D, (q15_t)0xE6A4, (q15_t)0x8289, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE769, (q15_t)0x8262, + (q15_t)0xE7CC, (q15_t)0x824F, (q15_t)0xE82F, (q15_t)0x823C, + (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE8F5, (q15_t)0x8217, + (q15_t)0xE957, (q15_t)0x8205, (q15_t)0xE9BA, (q15_t)0x81F3, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEA80, (q15_t)0x81D1, + (q15_t)0xEAE4, (q15_t)0x81C0, (q15_t)0xEB47, (q15_t)0x81B0, + (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEC0D, (q15_t)0x8190, + (q15_t)0xEC71, (q15_t)0x8180, (q15_t)0xECD4, (q15_t)0x8171, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xED9B, (q15_t)0x8154, + (q15_t)0xEDFE, (q15_t)0x8145, (q15_t)0xEE62, (q15_t)0x8137, + (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEF29, (q15_t)0x811C, + (q15_t)0xEF8D, (q15_t)0x810F, (q15_t)0xEFF1, (q15_t)0x8102, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF0B8, (q15_t)0x80EA, + (q15_t)0xF11C, (q15_t)0x80DE, (q15_t)0xF180, (q15_t)0x80D2, + (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF248, (q15_t)0x80BC, + (q15_t)0xF2AC, (q15_t)0x80B2, (q15_t)0xF310, (q15_t)0x80A7, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF3D8, (q15_t)0x8094, + (q15_t)0xF43C, (q15_t)0x808A, (q15_t)0xF4A0, (q15_t)0x8081, + (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF568, (q15_t)0x8070, + (q15_t)0xF5CC, (q15_t)0x8068, (q15_t)0xF631, (q15_t)0x8060, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF6F9, (q15_t)0x8051, + (q15_t)0xF75D, (q15_t)0x804A, (q15_t)0xF7C2, (q15_t)0x8043, + (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF88A, (q15_t)0x8037, + (q15_t)0xF8EF, (q15_t)0x8031, (q15_t)0xF953, (q15_t)0x802C, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFA1C, (q15_t)0x8022, + (q15_t)0xFA80, (q15_t)0x801E, (q15_t)0xFAE5, (q15_t)0x801A, + (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFBAE, (q15_t)0x8012, + (q15_t)0xFC12, (q15_t)0x800F, (q15_t)0xFC77, (q15_t)0x800C, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFD40, (q15_t)0x8007, + (q15_t)0xFDA4, (q15_t)0x8005, (q15_t)0xFE09, (q15_t)0x8003, + (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFED2, (q15_t)0x8001, + (q15_t)0xFF36, (q15_t)0x8000, (q15_t)0xFF9B, (q15_t)0x8000 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par +
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  } 
+ @par + where N = 4096, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_4096_q15[6144] = +{ + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x0032, + (q15_t)0x7FFF, (q15_t)0x0064, (q15_t)0x7FFF, (q15_t)0x0096, + (q15_t)0x7FFF, (q15_t)0x00C9, (q15_t)0x7FFF, (q15_t)0x00FB, + (q15_t)0x7FFE, (q15_t)0x012D, (q15_t)0x7FFE, (q15_t)0x015F, + (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFC, (q15_t)0x01C4, + (q15_t)0x7FFC, (q15_t)0x01F6, (q15_t)0x7FFB, (q15_t)0x0228, + (q15_t)0x7FFA, (q15_t)0x025B, (q15_t)0x7FF9, (q15_t)0x028D, + (q15_t)0x7FF8, (q15_t)0x02BF, (q15_t)0x7FF7, (q15_t)0x02F1, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF4, (q15_t)0x0356, + (q15_t)0x7FF3, (q15_t)0x0388, (q15_t)0x7FF2, (q15_t)0x03BA, + (q15_t)0x7FF0, (q15_t)0x03ED, (q15_t)0x7FEE, (q15_t)0x041F, + (q15_t)0x7FED, (q15_t)0x0451, (q15_t)0x7FEB, (q15_t)0x0483, + (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE7, (q15_t)0x04E8, + (q15_t)0x7FE5, (q15_t)0x051A, (q15_t)0x7FE3, (q15_t)0x054C, + (q15_t)0x7FE1, (q15_t)0x057F, (q15_t)0x7FDF, (q15_t)0x05B1, + (q15_t)0x7FDD, (q15_t)0x05E3, (q15_t)0x7FDA, (q15_t)0x0615, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FD6, (q15_t)0x067A, + (q15_t)0x7FD3, (q15_t)0x06AC, (q15_t)0x7FD0, (q15_t)0x06DE, + (q15_t)0x7FCE, (q15_t)0x0710, (q15_t)0x7FCB, (q15_t)0x0742, + (q15_t)0x7FC8, (q15_t)0x0775, (q15_t)0x7FC5, (q15_t)0x07A7, + (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FBF, (q15_t)0x080B, + (q15_t)0x7FBC, (q15_t)0x083D, (q15_t)0x7FB8, (q15_t)0x086F, + (q15_t)0x7FB5, (q15_t)0x08A2, (q15_t)0x7FB1, (q15_t)0x08D4, + (q15_t)0x7FAE, (q15_t)0x0906, (q15_t)0x7FAA, (q15_t)0x0938, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7FA3, (q15_t)0x099C, + (q15_t)0x7F9F, (q15_t)0x09CE, (q15_t)0x7F9B, (q15_t)0x0A00, + (q15_t)0x7F97, (q15_t)0x0A33, (q15_t)0x7F93, (q15_t)0x0A65, + (q15_t)0x7F8F, (q15_t)0x0A97, (q15_t)0x7F8B, (q15_t)0x0AC9, + (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F82, (q15_t)0x0B2D, + (q15_t)0x7F7E, (q15_t)0x0B5F, (q15_t)0x7F79, (q15_t)0x0B91, + (q15_t)0x7F75, (q15_t)0x0BC3, (q15_t)0x7F70, (q15_t)0x0BF5, + (q15_t)0x7F6B, (q15_t)0x0C27, (q15_t)0x7F67, (q15_t)0x0C59, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F5D, (q15_t)0x0CBD, + (q15_t)0x7F58, (q15_t)0x0CEF, (q15_t)0x7F53, (q15_t)0x0D21, + (q15_t)0x7F4D, (q15_t)0x0D53, (q15_t)0x7F48, (q15_t)0x0D85, + (q15_t)0x7F43, (q15_t)0x0DB7, (q15_t)0x7F3D, (q15_t)0x0DE9, + (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F32, (q15_t)0x0E4D, + (q15_t)0x7F2D, (q15_t)0x0E7F, (q15_t)0x7F27, (q15_t)0x0EB1, + (q15_t)0x7F21, (q15_t)0x0EE3, (q15_t)0x7F1B, (q15_t)0x0F15, + (q15_t)0x7F15, (q15_t)0x0F47, (q15_t)0x7F0F, (q15_t)0x0F79, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7F03, (q15_t)0x0FDD, + (q15_t)0x7EFD, (q15_t)0x100E, (q15_t)0x7EF6, (q15_t)0x1040, + (q15_t)0x7EF0, (q15_t)0x1072, (q15_t)0x7EE9, (q15_t)0x10A4, + (q15_t)0x7EE3, (q15_t)0x10D6, (q15_t)0x7EDC, (q15_t)0x1108, + (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7ECF, (q15_t)0x116B, + (q15_t)0x7EC8, (q15_t)0x119D, (q15_t)0x7EC1, (q15_t)0x11CF, + (q15_t)0x7EBA, (q15_t)0x1201, (q15_t)0x7EB3, (q15_t)0x1232, + (q15_t)0x7EAB, (q15_t)0x1264, (q15_t)0x7EA4, (q15_t)0x1296, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E95, (q15_t)0x12F9, + (q15_t)0x7E8E, (q15_t)0x132B, (q15_t)0x7E86, (q15_t)0x135D, + (q15_t)0x7E7F, (q15_t)0x138E, (q15_t)0x7E77, (q15_t)0x13C0, + (q15_t)0x7E6F, (q15_t)0x13F2, (q15_t)0x7E67, (q15_t)0x1423, + (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E57, (q15_t)0x1487, + (q15_t)0x7E4F, (q15_t)0x14B8, (q15_t)0x7E47, (q15_t)0x14EA, + (q15_t)0x7E3F, (q15_t)0x151B, (q15_t)0x7E37, (q15_t)0x154D, + (q15_t)0x7E2E, (q15_t)0x157F, (q15_t)0x7E26, (q15_t)0x15B0, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7E14, (q15_t)0x1613, + (q15_t)0x7E0C, (q15_t)0x1645, (q15_t)0x7E03, (q15_t)0x1676, + (q15_t)0x7DFA, (q15_t)0x16A8, (q15_t)0x7DF1, (q15_t)0x16D9, + (q15_t)0x7DE8, (q15_t)0x170A, (q15_t)0x7DDF, (q15_t)0x173C, + (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DCD, (q15_t)0x179F, + (q15_t)0x7DC3, (q15_t)0x17D0, (q15_t)0x7DBA, (q15_t)0x1802, + (q15_t)0x7DB0, (q15_t)0x1833, (q15_t)0x7DA7, (q15_t)0x1864, + (q15_t)0x7D9D, (q15_t)0x1896, (q15_t)0x7D94, (q15_t)0x18C7, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D80, (q15_t)0x192A, + (q15_t)0x7D76, (q15_t)0x195B, (q15_t)0x7D6C, (q15_t)0x198C, + (q15_t)0x7D62, (q15_t)0x19BD, (q15_t)0x7D58, (q15_t)0x19EF, + (q15_t)0x7D4E, (q15_t)0x1A20, (q15_t)0x7D43, (q15_t)0x1A51, + (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D2F, (q15_t)0x1AB3, + (q15_t)0x7D24, (q15_t)0x1AE4, (q15_t)0x7D19, (q15_t)0x1B16, + (q15_t)0x7D0F, (q15_t)0x1B47, (q15_t)0x7D04, (q15_t)0x1B78, + (q15_t)0x7CF9, (q15_t)0x1BA9, (q15_t)0x7CEE, (q15_t)0x1BDA, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CD8, (q15_t)0x1C3C, + (q15_t)0x7CCD, (q15_t)0x1C6D, (q15_t)0x7CC2, (q15_t)0x1C9E, + (q15_t)0x7CB7, (q15_t)0x1CCF, (q15_t)0x7CAB, (q15_t)0x1D00, + (q15_t)0x7CA0, (q15_t)0x1D31, (q15_t)0x7C94, (q15_t)0x1D62, + (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C7D, (q15_t)0x1DC4, + (q15_t)0x7C71, (q15_t)0x1DF5, (q15_t)0x7C66, (q15_t)0x1E25, + (q15_t)0x7C5A, (q15_t)0x1E56, (q15_t)0x7C4E, (q15_t)0x1E87, + (q15_t)0x7C42, (q15_t)0x1EB8, (q15_t)0x7C36, (q15_t)0x1EE9, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7C1D, (q15_t)0x1F4A, + (q15_t)0x7C11, (q15_t)0x1F7B, (q15_t)0x7C05, (q15_t)0x1FAC, + (q15_t)0x7BF8, (q15_t)0x1FDC, (q15_t)0x7BEB, (q15_t)0x200D, + (q15_t)0x7BDF, (q15_t)0x203E, (q15_t)0x7BD2, (q15_t)0x206E, + (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7BB9, (q15_t)0x20D0, + (q15_t)0x7BAC, (q15_t)0x2100, (q15_t)0x7B9F, (q15_t)0x2131, + (q15_t)0x7B92, (q15_t)0x2161, (q15_t)0x7B84, (q15_t)0x2192, + (q15_t)0x7B77, (q15_t)0x21C2, (q15_t)0x7B6A, (q15_t)0x21F3, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B4F, (q15_t)0x2254, + (q15_t)0x7B42, (q15_t)0x2284, (q15_t)0x7B34, (q15_t)0x22B4, + (q15_t)0x7B26, (q15_t)0x22E5, (q15_t)0x7B19, (q15_t)0x2315, + (q15_t)0x7B0B, (q15_t)0x2345, (q15_t)0x7AFD, (q15_t)0x2376, + (q15_t)0x7AEF, (q15_t)0x23A6, (q15_t)0x7AE1, (q15_t)0x23D6, + (q15_t)0x7AD3, (q15_t)0x2407, (q15_t)0x7AC5, (q15_t)0x2437, + (q15_t)0x7AB6, (q15_t)0x2467, (q15_t)0x7AA8, (q15_t)0x2497, + (q15_t)0x7A9A, (q15_t)0x24C7, (q15_t)0x7A8B, (q15_t)0x24F7, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A6E, (q15_t)0x2558, + (q15_t)0x7A5F, (q15_t)0x2588, (q15_t)0x7A50, (q15_t)0x25B8, + (q15_t)0x7A42, (q15_t)0x25E8, (q15_t)0x7A33, (q15_t)0x2618, + (q15_t)0x7A24, (q15_t)0x2648, (q15_t)0x7A15, (q15_t)0x2678, + (q15_t)0x7A05, (q15_t)0x26A8, (q15_t)0x79F6, (q15_t)0x26D8, + (q15_t)0x79E7, (q15_t)0x2707, (q15_t)0x79D8, (q15_t)0x2737, + (q15_t)0x79C8, (q15_t)0x2767, (q15_t)0x79B9, (q15_t)0x2797, + (q15_t)0x79A9, (q15_t)0x27C7, (q15_t)0x7999, (q15_t)0x27F6, + (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x797A, (q15_t)0x2856, + (q15_t)0x796A, (q15_t)0x2886, (q15_t)0x795A, (q15_t)0x28B5, + (q15_t)0x794A, (q15_t)0x28E5, (q15_t)0x793A, (q15_t)0x2915, + (q15_t)0x792A, (q15_t)0x2944, (q15_t)0x7919, (q15_t)0x2974, + (q15_t)0x7909, (q15_t)0x29A3, (q15_t)0x78F9, (q15_t)0x29D3, + (q15_t)0x78E8, (q15_t)0x2A02, (q15_t)0x78D8, (q15_t)0x2A32, + (q15_t)0x78C7, (q15_t)0x2A61, (q15_t)0x78B6, (q15_t)0x2A91, + (q15_t)0x78A6, (q15_t)0x2AC0, (q15_t)0x7895, (q15_t)0x2AEF, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x7873, (q15_t)0x2B4E, + (q15_t)0x7862, (q15_t)0x2B7D, (q15_t)0x7851, (q15_t)0x2BAD, + (q15_t)0x7840, (q15_t)0x2BDC, (q15_t)0x782E, (q15_t)0x2C0B, + (q15_t)0x781D, (q15_t)0x2C3A, (q15_t)0x780C, (q15_t)0x2C69, + (q15_t)0x77FA, (q15_t)0x2C98, (q15_t)0x77E9, (q15_t)0x2CC8, + (q15_t)0x77D7, (q15_t)0x2CF7, (q15_t)0x77C5, (q15_t)0x2D26, + (q15_t)0x77B4, (q15_t)0x2D55, (q15_t)0x77A2, (q15_t)0x2D84, + (q15_t)0x7790, (q15_t)0x2DB3, (q15_t)0x777E, (q15_t)0x2DE2, + (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x775A, (q15_t)0x2E3F, + (q15_t)0x7747, (q15_t)0x2E6E, (q15_t)0x7735, (q15_t)0x2E9D, + (q15_t)0x7723, (q15_t)0x2ECC, (q15_t)0x7710, (q15_t)0x2EFB, + (q15_t)0x76FE, (q15_t)0x2F29, (q15_t)0x76EB, (q15_t)0x2F58, + (q15_t)0x76D9, (q15_t)0x2F87, (q15_t)0x76C6, (q15_t)0x2FB5, + (q15_t)0x76B3, (q15_t)0x2FE4, (q15_t)0x76A0, (q15_t)0x3013, + (q15_t)0x768E, (q15_t)0x3041, (q15_t)0x767B, (q15_t)0x3070, + (q15_t)0x7668, (q15_t)0x309E, (q15_t)0x7654, (q15_t)0x30CD, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x762E, (q15_t)0x312A, + (q15_t)0x761B, (q15_t)0x3158, (q15_t)0x7607, (q15_t)0x3186, + (q15_t)0x75F4, (q15_t)0x31B5, (q15_t)0x75E0, (q15_t)0x31E3, + (q15_t)0x75CC, (q15_t)0x3211, (q15_t)0x75B9, (q15_t)0x3240, + (q15_t)0x75A5, (q15_t)0x326E, (q15_t)0x7591, (q15_t)0x329C, + (q15_t)0x757D, (q15_t)0x32CA, (q15_t)0x7569, (q15_t)0x32F8, + (q15_t)0x7555, (q15_t)0x3326, (q15_t)0x7541, (q15_t)0x3354, + (q15_t)0x752D, (q15_t)0x3382, (q15_t)0x7519, (q15_t)0x33B0, + (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x74F0, (q15_t)0x340C, + (q15_t)0x74DB, (q15_t)0x343A, (q15_t)0x74C7, (q15_t)0x3468, + (q15_t)0x74B2, (q15_t)0x3496, (q15_t)0x749E, (q15_t)0x34C4, + (q15_t)0x7489, (q15_t)0x34F2, (q15_t)0x7474, (q15_t)0x351F, + (q15_t)0x745F, (q15_t)0x354D, (q15_t)0x744A, (q15_t)0x357B, + (q15_t)0x7435, (q15_t)0x35A8, (q15_t)0x7420, (q15_t)0x35D6, + (q15_t)0x740B, (q15_t)0x3604, (q15_t)0x73F6, (q15_t)0x3631, + (q15_t)0x73E0, (q15_t)0x365F, (q15_t)0x73CB, (q15_t)0x368C, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x73A0, (q15_t)0x36E7, + (q15_t)0x738A, (q15_t)0x3714, (q15_t)0x7375, (q15_t)0x3742, + (q15_t)0x735F, (q15_t)0x376F, (q15_t)0x7349, (q15_t)0x379C, + (q15_t)0x7333, (q15_t)0x37CA, (q15_t)0x731D, (q15_t)0x37F7, + (q15_t)0x7307, (q15_t)0x3824, (q15_t)0x72F1, (q15_t)0x3851, + (q15_t)0x72DB, (q15_t)0x387E, (q15_t)0x72C5, (q15_t)0x38AB, + (q15_t)0x72AF, (q15_t)0x38D8, (q15_t)0x7298, (q15_t)0x3906, + (q15_t)0x7282, (q15_t)0x3932, (q15_t)0x726B, (q15_t)0x395F, + (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x723E, (q15_t)0x39B9, + (q15_t)0x7227, (q15_t)0x39E6, (q15_t)0x7211, (q15_t)0x3A13, + (q15_t)0x71FA, (q15_t)0x3A40, (q15_t)0x71E3, (q15_t)0x3A6C, + (q15_t)0x71CC, (q15_t)0x3A99, (q15_t)0x71B5, (q15_t)0x3AC6, + (q15_t)0x719E, (q15_t)0x3AF2, (q15_t)0x7186, (q15_t)0x3B1F, + (q15_t)0x716F, (q15_t)0x3B4C, (q15_t)0x7158, (q15_t)0x3B78, + (q15_t)0x7141, (q15_t)0x3BA5, (q15_t)0x7129, (q15_t)0x3BD1, + (q15_t)0x7112, (q15_t)0x3BFD, (q15_t)0x70FA, (q15_t)0x3C2A, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x70CB, (q15_t)0x3C83, + (q15_t)0x70B3, (q15_t)0x3CAF, (q15_t)0x709B, (q15_t)0x3CDB, + (q15_t)0x7083, (q15_t)0x3D07, (q15_t)0x706B, (q15_t)0x3D33, + (q15_t)0x7053, (q15_t)0x3D60, (q15_t)0x703B, (q15_t)0x3D8C, + (q15_t)0x7023, (q15_t)0x3DB8, (q15_t)0x700A, (q15_t)0x3DE4, + (q15_t)0x6FF2, (q15_t)0x3E10, (q15_t)0x6FDA, (q15_t)0x3E3C, + (q15_t)0x6FC1, (q15_t)0x3E68, (q15_t)0x6FA9, (q15_t)0x3E93, + (q15_t)0x6F90, (q15_t)0x3EBF, (q15_t)0x6F77, (q15_t)0x3EEB, + (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6F46, (q15_t)0x3F43, + (q15_t)0x6F2D, (q15_t)0x3F6E, (q15_t)0x6F14, (q15_t)0x3F9A, + (q15_t)0x6EFB, (q15_t)0x3FC5, (q15_t)0x6EE2, (q15_t)0x3FF1, + (q15_t)0x6EC9, (q15_t)0x401D, (q15_t)0x6EAF, (q15_t)0x4048, + (q15_t)0x6E96, (q15_t)0x4073, (q15_t)0x6E7D, (q15_t)0x409F, + (q15_t)0x6E63, (q15_t)0x40CA, (q15_t)0x6E4A, (q15_t)0x40F6, + (q15_t)0x6E30, (q15_t)0x4121, (q15_t)0x6E17, (q15_t)0x414C, + (q15_t)0x6DFD, (q15_t)0x4177, (q15_t)0x6DE3, (q15_t)0x41A2, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6DB0, (q15_t)0x41F9, + (q15_t)0x6D96, (q15_t)0x4224, (q15_t)0x6D7C, (q15_t)0x424F, + (q15_t)0x6D62, (q15_t)0x427A, (q15_t)0x6D48, (q15_t)0x42A5, + (q15_t)0x6D2D, (q15_t)0x42D0, (q15_t)0x6D13, (q15_t)0x42FA, + (q15_t)0x6CF9, (q15_t)0x4325, (q15_t)0x6CDE, (q15_t)0x4350, + (q15_t)0x6CC4, (q15_t)0x437B, (q15_t)0x6CA9, (q15_t)0x43A5, + (q15_t)0x6C8F, (q15_t)0x43D0, (q15_t)0x6C74, (q15_t)0x43FB, + (q15_t)0x6C59, (q15_t)0x4425, (q15_t)0x6C3F, (q15_t)0x4450, + (q15_t)0x6C24, (q15_t)0x447A, (q15_t)0x6C09, (q15_t)0x44A5, + (q15_t)0x6BEE, (q15_t)0x44CF, (q15_t)0x6BD3, (q15_t)0x44FA, + (q15_t)0x6BB8, (q15_t)0x4524, (q15_t)0x6B9C, (q15_t)0x454E, + (q15_t)0x6B81, (q15_t)0x4578, (q15_t)0x6B66, (q15_t)0x45A3, + (q15_t)0x6B4A, (q15_t)0x45CD, (q15_t)0x6B2F, (q15_t)0x45F7, + (q15_t)0x6B13, (q15_t)0x4621, (q15_t)0x6AF8, (q15_t)0x464B, + (q15_t)0x6ADC, (q15_t)0x4675, (q15_t)0x6AC1, (q15_t)0x469F, + (q15_t)0x6AA5, (q15_t)0x46C9, (q15_t)0x6A89, (q15_t)0x46F3, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x6A51, (q15_t)0x4746, + (q15_t)0x6A35, (q15_t)0x4770, (q15_t)0x6A19, (q15_t)0x479A, + (q15_t)0x69FD, (q15_t)0x47C3, (q15_t)0x69E1, (q15_t)0x47ED, + (q15_t)0x69C4, (q15_t)0x4816, (q15_t)0x69A8, (q15_t)0x4840, + (q15_t)0x698C, (q15_t)0x4869, (q15_t)0x696F, (q15_t)0x4893, + (q15_t)0x6953, (q15_t)0x48BC, (q15_t)0x6936, (q15_t)0x48E6, + (q15_t)0x6919, (q15_t)0x490F, (q15_t)0x68FD, (q15_t)0x4938, + (q15_t)0x68E0, (q15_t)0x4961, (q15_t)0x68C3, (q15_t)0x498A, + (q15_t)0x68A6, (q15_t)0x49B4, (q15_t)0x6889, (q15_t)0x49DD, + (q15_t)0x686C, (q15_t)0x4A06, (q15_t)0x684F, (q15_t)0x4A2F, + (q15_t)0x6832, (q15_t)0x4A58, (q15_t)0x6815, (q15_t)0x4A81, + (q15_t)0x67F7, (q15_t)0x4AA9, (q15_t)0x67DA, (q15_t)0x4AD2, + (q15_t)0x67BD, (q15_t)0x4AFB, (q15_t)0x679F, (q15_t)0x4B24, + (q15_t)0x6782, (q15_t)0x4B4C, (q15_t)0x6764, (q15_t)0x4B75, + (q15_t)0x6746, (q15_t)0x4B9E, (q15_t)0x6729, (q15_t)0x4BC6, + (q15_t)0x670B, (q15_t)0x4BEF, (q15_t)0x66ED, (q15_t)0x4C17, + (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x66B1, (q15_t)0x4C68, + (q15_t)0x6693, (q15_t)0x4C90, (q15_t)0x6675, (q15_t)0x4CB8, + (q15_t)0x6657, (q15_t)0x4CE1, (q15_t)0x6639, (q15_t)0x4D09, + (q15_t)0x661A, (q15_t)0x4D31, (q15_t)0x65FC, (q15_t)0x4D59, + (q15_t)0x65DD, (q15_t)0x4D81, (q15_t)0x65BF, (q15_t)0x4DA9, + (q15_t)0x65A0, (q15_t)0x4DD1, (q15_t)0x6582, (q15_t)0x4DF9, + (q15_t)0x6563, (q15_t)0x4E21, (q15_t)0x6545, (q15_t)0x4E48, + (q15_t)0x6526, (q15_t)0x4E70, (q15_t)0x6507, (q15_t)0x4E98, + (q15_t)0x64E8, (q15_t)0x4EBF, (q15_t)0x64C9, (q15_t)0x4EE7, + (q15_t)0x64AA, (q15_t)0x4F0F, (q15_t)0x648B, (q15_t)0x4F36, + (q15_t)0x646C, (q15_t)0x4F5E, (q15_t)0x644D, (q15_t)0x4F85, + (q15_t)0x642D, (q15_t)0x4FAC, (q15_t)0x640E, (q15_t)0x4FD4, + (q15_t)0x63EF, (q15_t)0x4FFB, (q15_t)0x63CF, (q15_t)0x5022, + (q15_t)0x63B0, (q15_t)0x5049, (q15_t)0x6390, (q15_t)0x5070, + (q15_t)0x6371, (q15_t)0x5097, (q15_t)0x6351, (q15_t)0x50BF, + (q15_t)0x6331, (q15_t)0x50E5, (q15_t)0x6311, (q15_t)0x510C, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x62D2, (q15_t)0x515A, + (q15_t)0x62B2, (q15_t)0x5181, (q15_t)0x6292, (q15_t)0x51A8, + (q15_t)0x6271, (q15_t)0x51CE, (q15_t)0x6251, (q15_t)0x51F5, + (q15_t)0x6231, (q15_t)0x521C, (q15_t)0x6211, (q15_t)0x5242, + (q15_t)0x61F1, (q15_t)0x5269, (q15_t)0x61D0, (q15_t)0x528F, + (q15_t)0x61B0, (q15_t)0x52B5, (q15_t)0x618F, (q15_t)0x52DC, + (q15_t)0x616F, (q15_t)0x5302, (q15_t)0x614E, (q15_t)0x5328, + (q15_t)0x612D, (q15_t)0x534E, (q15_t)0x610D, (q15_t)0x5375, + (q15_t)0x60EC, (q15_t)0x539B, (q15_t)0x60CB, (q15_t)0x53C1, + (q15_t)0x60AA, (q15_t)0x53E7, (q15_t)0x6089, (q15_t)0x540D, + (q15_t)0x6068, (q15_t)0x5433, (q15_t)0x6047, (q15_t)0x5458, + (q15_t)0x6026, (q15_t)0x547E, (q15_t)0x6004, (q15_t)0x54A4, + (q15_t)0x5FE3, (q15_t)0x54CA, (q15_t)0x5FC2, (q15_t)0x54EF, + (q15_t)0x5FA0, (q15_t)0x5515, (q15_t)0x5F7F, (q15_t)0x553A, + (q15_t)0x5F5E, (q15_t)0x5560, (q15_t)0x5F3C, (q15_t)0x5585, + (q15_t)0x5F1A, (q15_t)0x55AB, (q15_t)0x5EF9, (q15_t)0x55D0, + (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5EB5, (q15_t)0x561A, + (q15_t)0x5E93, (q15_t)0x5640, (q15_t)0x5E71, (q15_t)0x5665, + (q15_t)0x5E50, (q15_t)0x568A, (q15_t)0x5E2D, (q15_t)0x56AF, + (q15_t)0x5E0B, (q15_t)0x56D4, (q15_t)0x5DE9, (q15_t)0x56F9, + (q15_t)0x5DC7, (q15_t)0x571D, (q15_t)0x5DA5, (q15_t)0x5742, + (q15_t)0x5D83, (q15_t)0x5767, (q15_t)0x5D60, (q15_t)0x578C, + (q15_t)0x5D3E, (q15_t)0x57B0, (q15_t)0x5D1B, (q15_t)0x57D5, + (q15_t)0x5CF9, (q15_t)0x57F9, (q15_t)0x5CD6, (q15_t)0x581E, + (q15_t)0x5CB4, (q15_t)0x5842, (q15_t)0x5C91, (q15_t)0x5867, + (q15_t)0x5C6E, (q15_t)0x588B, (q15_t)0x5C4B, (q15_t)0x58AF, + (q15_t)0x5C29, (q15_t)0x58D4, (q15_t)0x5C06, (q15_t)0x58F8, + (q15_t)0x5BE3, (q15_t)0x591C, (q15_t)0x5BC0, (q15_t)0x5940, + (q15_t)0x5B9D, (q15_t)0x5964, (q15_t)0x5B79, (q15_t)0x5988, + (q15_t)0x5B56, (q15_t)0x59AC, (q15_t)0x5B33, (q15_t)0x59D0, + (q15_t)0x5B10, (q15_t)0x59F3, (q15_t)0x5AEC, (q15_t)0x5A17, + (q15_t)0x5AC9, (q15_t)0x5A3B, (q15_t)0x5AA5, (q15_t)0x5A5E, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5A5E, (q15_t)0x5AA5, + (q15_t)0x5A3B, (q15_t)0x5AC9, (q15_t)0x5A17, (q15_t)0x5AEC, + (q15_t)0x59F3, (q15_t)0x5B10, (q15_t)0x59D0, (q15_t)0x5B33, + (q15_t)0x59AC, (q15_t)0x5B56, (q15_t)0x5988, (q15_t)0x5B79, + (q15_t)0x5964, (q15_t)0x5B9D, (q15_t)0x5940, (q15_t)0x5BC0, + (q15_t)0x591C, (q15_t)0x5BE3, (q15_t)0x58F8, (q15_t)0x5C06, + (q15_t)0x58D4, (q15_t)0x5C29, (q15_t)0x58AF, (q15_t)0x5C4B, + (q15_t)0x588B, (q15_t)0x5C6E, (q15_t)0x5867, (q15_t)0x5C91, + (q15_t)0x5842, (q15_t)0x5CB4, (q15_t)0x581E, (q15_t)0x5CD6, + (q15_t)0x57F9, (q15_t)0x5CF9, (q15_t)0x57D5, (q15_t)0x5D1B, + (q15_t)0x57B0, (q15_t)0x5D3E, (q15_t)0x578C, (q15_t)0x5D60, + (q15_t)0x5767, (q15_t)0x5D83, (q15_t)0x5742, (q15_t)0x5DA5, + (q15_t)0x571D, (q15_t)0x5DC7, (q15_t)0x56F9, (q15_t)0x5DE9, + (q15_t)0x56D4, (q15_t)0x5E0B, (q15_t)0x56AF, (q15_t)0x5E2D, + (q15_t)0x568A, (q15_t)0x5E50, (q15_t)0x5665, (q15_t)0x5E71, + (q15_t)0x5640, (q15_t)0x5E93, (q15_t)0x561A, (q15_t)0x5EB5, + (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x55D0, (q15_t)0x5EF9, + (q15_t)0x55AB, (q15_t)0x5F1A, (q15_t)0x5585, (q15_t)0x5F3C, + (q15_t)0x5560, (q15_t)0x5F5E, (q15_t)0x553A, (q15_t)0x5F7F, + (q15_t)0x5515, (q15_t)0x5FA0, (q15_t)0x54EF, (q15_t)0x5FC2, + (q15_t)0x54CA, (q15_t)0x5FE3, (q15_t)0x54A4, (q15_t)0x6004, + (q15_t)0x547E, (q15_t)0x6026, (q15_t)0x5458, (q15_t)0x6047, + (q15_t)0x5433, (q15_t)0x6068, (q15_t)0x540D, (q15_t)0x6089, + (q15_t)0x53E7, (q15_t)0x60AA, (q15_t)0x53C1, (q15_t)0x60CB, + (q15_t)0x539B, (q15_t)0x60EC, (q15_t)0x5375, (q15_t)0x610D, + (q15_t)0x534E, (q15_t)0x612D, (q15_t)0x5328, (q15_t)0x614E, + (q15_t)0x5302, (q15_t)0x616F, (q15_t)0x52DC, (q15_t)0x618F, + (q15_t)0x52B5, (q15_t)0x61B0, (q15_t)0x528F, (q15_t)0x61D0, + (q15_t)0x5269, (q15_t)0x61F1, (q15_t)0x5242, (q15_t)0x6211, + (q15_t)0x521C, (q15_t)0x6231, (q15_t)0x51F5, (q15_t)0x6251, + (q15_t)0x51CE, (q15_t)0x6271, (q15_t)0x51A8, (q15_t)0x6292, + (q15_t)0x5181, (q15_t)0x62B2, (q15_t)0x515A, (q15_t)0x62D2, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x510C, (q15_t)0x6311, + (q15_t)0x50E5, (q15_t)0x6331, (q15_t)0x50BF, (q15_t)0x6351, + (q15_t)0x5097, (q15_t)0x6371, (q15_t)0x5070, (q15_t)0x6390, + (q15_t)0x5049, (q15_t)0x63B0, (q15_t)0x5022, (q15_t)0x63CF, + (q15_t)0x4FFB, (q15_t)0x63EF, (q15_t)0x4FD4, (q15_t)0x640E, + (q15_t)0x4FAC, (q15_t)0x642D, (q15_t)0x4F85, (q15_t)0x644D, + (q15_t)0x4F5E, (q15_t)0x646C, (q15_t)0x4F36, (q15_t)0x648B, + (q15_t)0x4F0F, (q15_t)0x64AA, (q15_t)0x4EE7, (q15_t)0x64C9, + (q15_t)0x4EBF, (q15_t)0x64E8, (q15_t)0x4E98, (q15_t)0x6507, + (q15_t)0x4E70, (q15_t)0x6526, (q15_t)0x4E48, (q15_t)0x6545, + (q15_t)0x4E21, (q15_t)0x6563, (q15_t)0x4DF9, (q15_t)0x6582, + (q15_t)0x4DD1, (q15_t)0x65A0, (q15_t)0x4DA9, (q15_t)0x65BF, + (q15_t)0x4D81, (q15_t)0x65DD, (q15_t)0x4D59, (q15_t)0x65FC, + (q15_t)0x4D31, (q15_t)0x661A, (q15_t)0x4D09, (q15_t)0x6639, + (q15_t)0x4CE1, (q15_t)0x6657, (q15_t)0x4CB8, (q15_t)0x6675, + (q15_t)0x4C90, (q15_t)0x6693, (q15_t)0x4C68, (q15_t)0x66B1, + (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x4C17, (q15_t)0x66ED, + (q15_t)0x4BEF, (q15_t)0x670B, (q15_t)0x4BC6, (q15_t)0x6729, + (q15_t)0x4B9E, (q15_t)0x6746, (q15_t)0x4B75, (q15_t)0x6764, + (q15_t)0x4B4C, (q15_t)0x6782, (q15_t)0x4B24, (q15_t)0x679F, + (q15_t)0x4AFB, (q15_t)0x67BD, (q15_t)0x4AD2, (q15_t)0x67DA, + (q15_t)0x4AA9, (q15_t)0x67F7, (q15_t)0x4A81, (q15_t)0x6815, + (q15_t)0x4A58, (q15_t)0x6832, (q15_t)0x4A2F, (q15_t)0x684F, + (q15_t)0x4A06, (q15_t)0x686C, (q15_t)0x49DD, (q15_t)0x6889, + (q15_t)0x49B4, (q15_t)0x68A6, (q15_t)0x498A, (q15_t)0x68C3, + (q15_t)0x4961, (q15_t)0x68E0, (q15_t)0x4938, (q15_t)0x68FD, + (q15_t)0x490F, (q15_t)0x6919, (q15_t)0x48E6, (q15_t)0x6936, + (q15_t)0x48BC, (q15_t)0x6953, (q15_t)0x4893, (q15_t)0x696F, + (q15_t)0x4869, (q15_t)0x698C, (q15_t)0x4840, (q15_t)0x69A8, + (q15_t)0x4816, (q15_t)0x69C4, (q15_t)0x47ED, (q15_t)0x69E1, + (q15_t)0x47C3, (q15_t)0x69FD, (q15_t)0x479A, (q15_t)0x6A19, + (q15_t)0x4770, (q15_t)0x6A35, (q15_t)0x4746, (q15_t)0x6A51, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x46F3, (q15_t)0x6A89, + (q15_t)0x46C9, (q15_t)0x6AA5, (q15_t)0x469F, (q15_t)0x6AC1, + (q15_t)0x4675, (q15_t)0x6ADC, (q15_t)0x464B, (q15_t)0x6AF8, + (q15_t)0x4621, (q15_t)0x6B13, (q15_t)0x45F7, (q15_t)0x6B2F, + (q15_t)0x45CD, (q15_t)0x6B4A, (q15_t)0x45A3, (q15_t)0x6B66, + (q15_t)0x4578, (q15_t)0x6B81, (q15_t)0x454E, (q15_t)0x6B9C, + (q15_t)0x4524, (q15_t)0x6BB8, (q15_t)0x44FA, (q15_t)0x6BD3, + (q15_t)0x44CF, (q15_t)0x6BEE, (q15_t)0x44A5, (q15_t)0x6C09, + (q15_t)0x447A, (q15_t)0x6C24, (q15_t)0x4450, (q15_t)0x6C3F, + (q15_t)0x4425, (q15_t)0x6C59, (q15_t)0x43FB, (q15_t)0x6C74, + (q15_t)0x43D0, (q15_t)0x6C8F, (q15_t)0x43A5, (q15_t)0x6CA9, + (q15_t)0x437B, (q15_t)0x6CC4, (q15_t)0x4350, (q15_t)0x6CDE, + (q15_t)0x4325, (q15_t)0x6CF9, (q15_t)0x42FA, (q15_t)0x6D13, + (q15_t)0x42D0, (q15_t)0x6D2D, (q15_t)0x42A5, (q15_t)0x6D48, + (q15_t)0x427A, (q15_t)0x6D62, (q15_t)0x424F, (q15_t)0x6D7C, + (q15_t)0x4224, (q15_t)0x6D96, (q15_t)0x41F9, (q15_t)0x6DB0, + (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x41A2, (q15_t)0x6DE3, + (q15_t)0x4177, (q15_t)0x6DFD, (q15_t)0x414C, (q15_t)0x6E17, + (q15_t)0x4121, (q15_t)0x6E30, (q15_t)0x40F6, (q15_t)0x6E4A, + (q15_t)0x40CA, (q15_t)0x6E63, (q15_t)0x409F, (q15_t)0x6E7D, + (q15_t)0x4073, (q15_t)0x6E96, (q15_t)0x4048, (q15_t)0x6EAF, + (q15_t)0x401D, (q15_t)0x6EC9, (q15_t)0x3FF1, (q15_t)0x6EE2, + (q15_t)0x3FC5, (q15_t)0x6EFB, (q15_t)0x3F9A, (q15_t)0x6F14, + (q15_t)0x3F6E, (q15_t)0x6F2D, (q15_t)0x3F43, (q15_t)0x6F46, + (q15_t)0x3F17, (q15_t)0x6F5F, (q15_t)0x3EEB, (q15_t)0x6F77, + (q15_t)0x3EBF, (q15_t)0x6F90, (q15_t)0x3E93, (q15_t)0x6FA9, + (q15_t)0x3E68, (q15_t)0x6FC1, (q15_t)0x3E3C, (q15_t)0x6FDA, + (q15_t)0x3E10, (q15_t)0x6FF2, (q15_t)0x3DE4, (q15_t)0x700A, + (q15_t)0x3DB8, (q15_t)0x7023, (q15_t)0x3D8C, (q15_t)0x703B, + (q15_t)0x3D60, (q15_t)0x7053, (q15_t)0x3D33, (q15_t)0x706B, + (q15_t)0x3D07, (q15_t)0x7083, (q15_t)0x3CDB, (q15_t)0x709B, + (q15_t)0x3CAF, (q15_t)0x70B3, (q15_t)0x3C83, (q15_t)0x70CB, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x3C2A, (q15_t)0x70FA, + (q15_t)0x3BFD, (q15_t)0x7112, (q15_t)0x3BD1, (q15_t)0x7129, + (q15_t)0x3BA5, (q15_t)0x7141, (q15_t)0x3B78, (q15_t)0x7158, + (q15_t)0x3B4C, (q15_t)0x716F, (q15_t)0x3B1F, (q15_t)0x7186, + (q15_t)0x3AF2, (q15_t)0x719E, (q15_t)0x3AC6, (q15_t)0x71B5, + (q15_t)0x3A99, (q15_t)0x71CC, (q15_t)0x3A6C, (q15_t)0x71E3, + (q15_t)0x3A40, (q15_t)0x71FA, (q15_t)0x3A13, (q15_t)0x7211, + (q15_t)0x39E6, (q15_t)0x7227, (q15_t)0x39B9, (q15_t)0x723E, + (q15_t)0x398C, (q15_t)0x7255, (q15_t)0x395F, (q15_t)0x726B, + (q15_t)0x3932, (q15_t)0x7282, (q15_t)0x3906, (q15_t)0x7298, + (q15_t)0x38D8, (q15_t)0x72AF, (q15_t)0x38AB, (q15_t)0x72C5, + (q15_t)0x387E, (q15_t)0x72DB, (q15_t)0x3851, (q15_t)0x72F1, + (q15_t)0x3824, (q15_t)0x7307, (q15_t)0x37F7, (q15_t)0x731D, + (q15_t)0x37CA, (q15_t)0x7333, (q15_t)0x379C, (q15_t)0x7349, + (q15_t)0x376F, (q15_t)0x735F, (q15_t)0x3742, (q15_t)0x7375, + (q15_t)0x3714, (q15_t)0x738A, (q15_t)0x36E7, (q15_t)0x73A0, + (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x368C, (q15_t)0x73CB, + (q15_t)0x365F, (q15_t)0x73E0, (q15_t)0x3631, (q15_t)0x73F6, + (q15_t)0x3604, (q15_t)0x740B, (q15_t)0x35D6, (q15_t)0x7420, + (q15_t)0x35A8, (q15_t)0x7435, (q15_t)0x357B, (q15_t)0x744A, + (q15_t)0x354D, (q15_t)0x745F, (q15_t)0x351F, (q15_t)0x7474, + (q15_t)0x34F2, (q15_t)0x7489, (q15_t)0x34C4, (q15_t)0x749E, + (q15_t)0x3496, (q15_t)0x74B2, (q15_t)0x3468, (q15_t)0x74C7, + (q15_t)0x343A, (q15_t)0x74DB, (q15_t)0x340C, (q15_t)0x74F0, + (q15_t)0x33DE, (q15_t)0x7504, (q15_t)0x33B0, (q15_t)0x7519, + (q15_t)0x3382, (q15_t)0x752D, (q15_t)0x3354, (q15_t)0x7541, + (q15_t)0x3326, (q15_t)0x7555, (q15_t)0x32F8, (q15_t)0x7569, + (q15_t)0x32CA, (q15_t)0x757D, (q15_t)0x329C, (q15_t)0x7591, + (q15_t)0x326E, (q15_t)0x75A5, (q15_t)0x3240, (q15_t)0x75B9, + (q15_t)0x3211, (q15_t)0x75CC, (q15_t)0x31E3, (q15_t)0x75E0, + (q15_t)0x31B5, (q15_t)0x75F4, (q15_t)0x3186, (q15_t)0x7607, + (q15_t)0x3158, (q15_t)0x761B, (q15_t)0x312A, (q15_t)0x762E, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x30CD, (q15_t)0x7654, + (q15_t)0x309E, (q15_t)0x7668, (q15_t)0x3070, (q15_t)0x767B, + (q15_t)0x3041, (q15_t)0x768E, (q15_t)0x3013, (q15_t)0x76A0, + (q15_t)0x2FE4, (q15_t)0x76B3, (q15_t)0x2FB5, (q15_t)0x76C6, + (q15_t)0x2F87, (q15_t)0x76D9, (q15_t)0x2F58, (q15_t)0x76EB, + (q15_t)0x2F29, (q15_t)0x76FE, (q15_t)0x2EFB, (q15_t)0x7710, + (q15_t)0x2ECC, (q15_t)0x7723, (q15_t)0x2E9D, (q15_t)0x7735, + (q15_t)0x2E6E, (q15_t)0x7747, (q15_t)0x2E3F, (q15_t)0x775A, + (q15_t)0x2E11, (q15_t)0x776C, (q15_t)0x2DE2, (q15_t)0x777E, + (q15_t)0x2DB3, (q15_t)0x7790, (q15_t)0x2D84, (q15_t)0x77A2, + (q15_t)0x2D55, (q15_t)0x77B4, (q15_t)0x2D26, (q15_t)0x77C5, + (q15_t)0x2CF7, (q15_t)0x77D7, (q15_t)0x2CC8, (q15_t)0x77E9, + (q15_t)0x2C98, (q15_t)0x77FA, (q15_t)0x2C69, (q15_t)0x780C, + (q15_t)0x2C3A, (q15_t)0x781D, (q15_t)0x2C0B, (q15_t)0x782E, + (q15_t)0x2BDC, (q15_t)0x7840, (q15_t)0x2BAD, (q15_t)0x7851, + (q15_t)0x2B7D, (q15_t)0x7862, (q15_t)0x2B4E, (q15_t)0x7873, + (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x2AEF, (q15_t)0x7895, + (q15_t)0x2AC0, (q15_t)0x78A6, (q15_t)0x2A91, (q15_t)0x78B6, + (q15_t)0x2A61, (q15_t)0x78C7, (q15_t)0x2A32, (q15_t)0x78D8, + (q15_t)0x2A02, (q15_t)0x78E8, (q15_t)0x29D3, (q15_t)0x78F9, + (q15_t)0x29A3, (q15_t)0x7909, (q15_t)0x2974, (q15_t)0x7919, + (q15_t)0x2944, (q15_t)0x792A, (q15_t)0x2915, (q15_t)0x793A, + (q15_t)0x28E5, (q15_t)0x794A, (q15_t)0x28B5, (q15_t)0x795A, + (q15_t)0x2886, (q15_t)0x796A, (q15_t)0x2856, (q15_t)0x797A, + (q15_t)0x2826, (q15_t)0x798A, (q15_t)0x27F6, (q15_t)0x7999, + (q15_t)0x27C7, (q15_t)0x79A9, (q15_t)0x2797, (q15_t)0x79B9, + (q15_t)0x2767, (q15_t)0x79C8, (q15_t)0x2737, (q15_t)0x79D8, + (q15_t)0x2707, (q15_t)0x79E7, (q15_t)0x26D8, (q15_t)0x79F6, + (q15_t)0x26A8, (q15_t)0x7A05, (q15_t)0x2678, (q15_t)0x7A15, + (q15_t)0x2648, (q15_t)0x7A24, (q15_t)0x2618, (q15_t)0x7A33, + (q15_t)0x25E8, (q15_t)0x7A42, (q15_t)0x25B8, (q15_t)0x7A50, + (q15_t)0x2588, (q15_t)0x7A5F, (q15_t)0x2558, (q15_t)0x7A6E, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x24F7, (q15_t)0x7A8B, + (q15_t)0x24C7, (q15_t)0x7A9A, (q15_t)0x2497, (q15_t)0x7AA8, + (q15_t)0x2467, (q15_t)0x7AB6, (q15_t)0x2437, (q15_t)0x7AC5, + (q15_t)0x2407, (q15_t)0x7AD3, (q15_t)0x23D6, (q15_t)0x7AE1, + (q15_t)0x23A6, (q15_t)0x7AEF, (q15_t)0x2376, (q15_t)0x7AFD, + (q15_t)0x2345, (q15_t)0x7B0B, (q15_t)0x2315, (q15_t)0x7B19, + (q15_t)0x22E5, (q15_t)0x7B26, (q15_t)0x22B4, (q15_t)0x7B34, + (q15_t)0x2284, (q15_t)0x7B42, (q15_t)0x2254, (q15_t)0x7B4F, + (q15_t)0x2223, (q15_t)0x7B5D, (q15_t)0x21F3, (q15_t)0x7B6A, + (q15_t)0x21C2, (q15_t)0x7B77, (q15_t)0x2192, (q15_t)0x7B84, + (q15_t)0x2161, (q15_t)0x7B92, (q15_t)0x2131, (q15_t)0x7B9F, + (q15_t)0x2100, (q15_t)0x7BAC, (q15_t)0x20D0, (q15_t)0x7BB9, + (q15_t)0x209F, (q15_t)0x7BC5, (q15_t)0x206E, (q15_t)0x7BD2, + (q15_t)0x203E, (q15_t)0x7BDF, (q15_t)0x200D, (q15_t)0x7BEB, + (q15_t)0x1FDC, (q15_t)0x7BF8, (q15_t)0x1FAC, (q15_t)0x7C05, + (q15_t)0x1F7B, (q15_t)0x7C11, (q15_t)0x1F4A, (q15_t)0x7C1D, + (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1EE9, (q15_t)0x7C36, + (q15_t)0x1EB8, (q15_t)0x7C42, (q15_t)0x1E87, (q15_t)0x7C4E, + (q15_t)0x1E56, (q15_t)0x7C5A, (q15_t)0x1E25, (q15_t)0x7C66, + (q15_t)0x1DF5, (q15_t)0x7C71, (q15_t)0x1DC4, (q15_t)0x7C7D, + (q15_t)0x1D93, (q15_t)0x7C89, (q15_t)0x1D62, (q15_t)0x7C94, + (q15_t)0x1D31, (q15_t)0x7CA0, (q15_t)0x1D00, (q15_t)0x7CAB, + (q15_t)0x1CCF, (q15_t)0x7CB7, (q15_t)0x1C9E, (q15_t)0x7CC2, + (q15_t)0x1C6D, (q15_t)0x7CCD, (q15_t)0x1C3C, (q15_t)0x7CD8, + (q15_t)0x1C0B, (q15_t)0x7CE3, (q15_t)0x1BDA, (q15_t)0x7CEE, + (q15_t)0x1BA9, (q15_t)0x7CF9, (q15_t)0x1B78, (q15_t)0x7D04, + (q15_t)0x1B47, (q15_t)0x7D0F, (q15_t)0x1B16, (q15_t)0x7D19, + (q15_t)0x1AE4, (q15_t)0x7D24, (q15_t)0x1AB3, (q15_t)0x7D2F, + (q15_t)0x1A82, (q15_t)0x7D39, (q15_t)0x1A51, (q15_t)0x7D43, + (q15_t)0x1A20, (q15_t)0x7D4E, (q15_t)0x19EF, (q15_t)0x7D58, + (q15_t)0x19BD, (q15_t)0x7D62, (q15_t)0x198C, (q15_t)0x7D6C, + (q15_t)0x195B, (q15_t)0x7D76, (q15_t)0x192A, (q15_t)0x7D80, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x18C7, (q15_t)0x7D94, + (q15_t)0x1896, (q15_t)0x7D9D, (q15_t)0x1864, (q15_t)0x7DA7, + (q15_t)0x1833, (q15_t)0x7DB0, (q15_t)0x1802, (q15_t)0x7DBA, + (q15_t)0x17D0, (q15_t)0x7DC3, (q15_t)0x179F, (q15_t)0x7DCD, + (q15_t)0x176D, (q15_t)0x7DD6, (q15_t)0x173C, (q15_t)0x7DDF, + (q15_t)0x170A, (q15_t)0x7DE8, (q15_t)0x16D9, (q15_t)0x7DF1, + (q15_t)0x16A8, (q15_t)0x7DFA, (q15_t)0x1676, (q15_t)0x7E03, + (q15_t)0x1645, (q15_t)0x7E0C, (q15_t)0x1613, (q15_t)0x7E14, + (q15_t)0x15E2, (q15_t)0x7E1D, (q15_t)0x15B0, (q15_t)0x7E26, + (q15_t)0x157F, (q15_t)0x7E2E, (q15_t)0x154D, (q15_t)0x7E37, + (q15_t)0x151B, (q15_t)0x7E3F, (q15_t)0x14EA, (q15_t)0x7E47, + (q15_t)0x14B8, (q15_t)0x7E4F, (q15_t)0x1487, (q15_t)0x7E57, + (q15_t)0x1455, (q15_t)0x7E5F, (q15_t)0x1423, (q15_t)0x7E67, + (q15_t)0x13F2, (q15_t)0x7E6F, (q15_t)0x13C0, (q15_t)0x7E77, + (q15_t)0x138E, (q15_t)0x7E7F, (q15_t)0x135D, (q15_t)0x7E86, + (q15_t)0x132B, (q15_t)0x7E8E, (q15_t)0x12F9, (q15_t)0x7E95, + (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x1296, (q15_t)0x7EA4, + (q15_t)0x1264, (q15_t)0x7EAB, (q15_t)0x1232, (q15_t)0x7EB3, + (q15_t)0x1201, (q15_t)0x7EBA, (q15_t)0x11CF, (q15_t)0x7EC1, + (q15_t)0x119D, (q15_t)0x7EC8, (q15_t)0x116B, (q15_t)0x7ECF, + (q15_t)0x1139, (q15_t)0x7ED5, (q15_t)0x1108, (q15_t)0x7EDC, + (q15_t)0x10D6, (q15_t)0x7EE3, (q15_t)0x10A4, (q15_t)0x7EE9, + (q15_t)0x1072, (q15_t)0x7EF0, (q15_t)0x1040, (q15_t)0x7EF6, + (q15_t)0x100E, (q15_t)0x7EFD, (q15_t)0x0FDD, (q15_t)0x7F03, + (q15_t)0x0FAB, (q15_t)0x7F09, (q15_t)0x0F79, (q15_t)0x7F0F, + (q15_t)0x0F47, (q15_t)0x7F15, (q15_t)0x0F15, (q15_t)0x7F1B, + (q15_t)0x0EE3, (q15_t)0x7F21, (q15_t)0x0EB1, (q15_t)0x7F27, + (q15_t)0x0E7F, (q15_t)0x7F2D, (q15_t)0x0E4D, (q15_t)0x7F32, + (q15_t)0x0E1B, (q15_t)0x7F38, (q15_t)0x0DE9, (q15_t)0x7F3D, + (q15_t)0x0DB7, (q15_t)0x7F43, (q15_t)0x0D85, (q15_t)0x7F48, + (q15_t)0x0D53, (q15_t)0x7F4D, (q15_t)0x0D21, (q15_t)0x7F53, + (q15_t)0x0CEF, (q15_t)0x7F58, (q15_t)0x0CBD, (q15_t)0x7F5D, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0C59, (q15_t)0x7F67, + (q15_t)0x0C27, (q15_t)0x7F6B, (q15_t)0x0BF5, (q15_t)0x7F70, + (q15_t)0x0BC3, (q15_t)0x7F75, (q15_t)0x0B91, (q15_t)0x7F79, + (q15_t)0x0B5F, (q15_t)0x7F7E, (q15_t)0x0B2D, (q15_t)0x7F82, + (q15_t)0x0AFB, (q15_t)0x7F87, (q15_t)0x0AC9, (q15_t)0x7F8B, + (q15_t)0x0A97, (q15_t)0x7F8F, (q15_t)0x0A65, (q15_t)0x7F93, + (q15_t)0x0A33, (q15_t)0x7F97, (q15_t)0x0A00, (q15_t)0x7F9B, + (q15_t)0x09CE, (q15_t)0x7F9F, (q15_t)0x099C, (q15_t)0x7FA3, + (q15_t)0x096A, (q15_t)0x7FA7, (q15_t)0x0938, (q15_t)0x7FAA, + (q15_t)0x0906, (q15_t)0x7FAE, (q15_t)0x08D4, (q15_t)0x7FB1, + (q15_t)0x08A2, (q15_t)0x7FB5, (q15_t)0x086F, (q15_t)0x7FB8, + (q15_t)0x083D, (q15_t)0x7FBC, (q15_t)0x080B, (q15_t)0x7FBF, + (q15_t)0x07D9, (q15_t)0x7FC2, (q15_t)0x07A7, (q15_t)0x7FC5, + (q15_t)0x0775, (q15_t)0x7FC8, (q15_t)0x0742, (q15_t)0x7FCB, + (q15_t)0x0710, (q15_t)0x7FCE, (q15_t)0x06DE, (q15_t)0x7FD0, + (q15_t)0x06AC, (q15_t)0x7FD3, (q15_t)0x067A, (q15_t)0x7FD6, + (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x0615, (q15_t)0x7FDA, + (q15_t)0x05E3, (q15_t)0x7FDD, (q15_t)0x05B1, (q15_t)0x7FDF, + (q15_t)0x057F, (q15_t)0x7FE1, (q15_t)0x054C, (q15_t)0x7FE3, + (q15_t)0x051A, (q15_t)0x7FE5, (q15_t)0x04E8, (q15_t)0x7FE7, + (q15_t)0x04B6, (q15_t)0x7FE9, (q15_t)0x0483, (q15_t)0x7FEB, + (q15_t)0x0451, (q15_t)0x7FED, (q15_t)0x041F, (q15_t)0x7FEE, + (q15_t)0x03ED, (q15_t)0x7FF0, (q15_t)0x03BA, (q15_t)0x7FF2, + (q15_t)0x0388, (q15_t)0x7FF3, (q15_t)0x0356, (q15_t)0x7FF4, + (q15_t)0x0324, (q15_t)0x7FF6, (q15_t)0x02F1, (q15_t)0x7FF7, + (q15_t)0x02BF, (q15_t)0x7FF8, (q15_t)0x028D, (q15_t)0x7FF9, + (q15_t)0x025B, (q15_t)0x7FFA, (q15_t)0x0228, (q15_t)0x7FFB, + (q15_t)0x01F6, (q15_t)0x7FFC, (q15_t)0x01C4, (q15_t)0x7FFC, + (q15_t)0x0192, (q15_t)0x7FFD, (q15_t)0x015F, (q15_t)0x7FFE, + (q15_t)0x012D, (q15_t)0x7FFE, (q15_t)0x00FB, (q15_t)0x7FFF, + (q15_t)0x00C9, (q15_t)0x7FFF, (q15_t)0x0096, (q15_t)0x7FFF, + (q15_t)0x0064, (q15_t)0x7FFF, (q15_t)0x0032, (q15_t)0x7FFF, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFFCD, (q15_t)0x7FFF, + (q15_t)0xFF9B, (q15_t)0x7FFF, (q15_t)0xFF69, (q15_t)0x7FFF, + (q15_t)0xFF36, (q15_t)0x7FFF, (q15_t)0xFF04, (q15_t)0x7FFF, + (q15_t)0xFED2, (q15_t)0x7FFE, (q15_t)0xFEA0, (q15_t)0x7FFE, + (q15_t)0xFE6D, (q15_t)0x7FFD, (q15_t)0xFE3B, (q15_t)0x7FFC, + (q15_t)0xFE09, (q15_t)0x7FFC, (q15_t)0xFDD7, (q15_t)0x7FFB, + (q15_t)0xFDA4, (q15_t)0x7FFA, (q15_t)0xFD72, (q15_t)0x7FF9, + (q15_t)0xFD40, (q15_t)0x7FF8, (q15_t)0xFD0E, (q15_t)0x7FF7, + (q15_t)0xFCDB, (q15_t)0x7FF6, (q15_t)0xFCA9, (q15_t)0x7FF4, + (q15_t)0xFC77, (q15_t)0x7FF3, (q15_t)0xFC45, (q15_t)0x7FF2, + (q15_t)0xFC12, (q15_t)0x7FF0, (q15_t)0xFBE0, (q15_t)0x7FEE, + (q15_t)0xFBAE, (q15_t)0x7FED, (q15_t)0xFB7C, (q15_t)0x7FEB, + (q15_t)0xFB49, (q15_t)0x7FE9, (q15_t)0xFB17, (q15_t)0x7FE7, + (q15_t)0xFAE5, (q15_t)0x7FE5, (q15_t)0xFAB3, (q15_t)0x7FE3, + (q15_t)0xFA80, (q15_t)0x7FE1, (q15_t)0xFA4E, (q15_t)0x7FDF, + (q15_t)0xFA1C, (q15_t)0x7FDD, (q15_t)0xF9EA, (q15_t)0x7FDA, + (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF985, (q15_t)0x7FD6, + (q15_t)0xF953, (q15_t)0x7FD3, (q15_t)0xF921, (q15_t)0x7FD0, + (q15_t)0xF8EF, (q15_t)0x7FCE, (q15_t)0xF8BD, (q15_t)0x7FCB, + (q15_t)0xF88A, (q15_t)0x7FC8, (q15_t)0xF858, (q15_t)0x7FC5, + (q15_t)0xF826, (q15_t)0x7FC2, (q15_t)0xF7F4, (q15_t)0x7FBF, + (q15_t)0xF7C2, (q15_t)0x7FBC, (q15_t)0xF790, (q15_t)0x7FB8, + (q15_t)0xF75D, (q15_t)0x7FB5, (q15_t)0xF72B, (q15_t)0x7FB1, + (q15_t)0xF6F9, (q15_t)0x7FAE, (q15_t)0xF6C7, (q15_t)0x7FAA, + (q15_t)0xF695, (q15_t)0x7FA7, (q15_t)0xF663, (q15_t)0x7FA3, + (q15_t)0xF631, (q15_t)0x7F9F, (q15_t)0xF5FF, (q15_t)0x7F9B, + (q15_t)0xF5CC, (q15_t)0x7F97, (q15_t)0xF59A, (q15_t)0x7F93, + (q15_t)0xF568, (q15_t)0x7F8F, (q15_t)0xF536, (q15_t)0x7F8B, + (q15_t)0xF504, (q15_t)0x7F87, (q15_t)0xF4D2, (q15_t)0x7F82, + (q15_t)0xF4A0, (q15_t)0x7F7E, (q15_t)0xF46E, (q15_t)0x7F79, + (q15_t)0xF43C, (q15_t)0x7F75, (q15_t)0xF40A, (q15_t)0x7F70, + (q15_t)0xF3D8, (q15_t)0x7F6B, (q15_t)0xF3A6, (q15_t)0x7F67, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF342, (q15_t)0x7F5D, + (q15_t)0xF310, (q15_t)0x7F58, (q15_t)0xF2DE, (q15_t)0x7F53, + (q15_t)0xF2AC, (q15_t)0x7F4D, (q15_t)0xF27A, (q15_t)0x7F48, + (q15_t)0xF248, (q15_t)0x7F43, (q15_t)0xF216, (q15_t)0x7F3D, + (q15_t)0xF1E4, (q15_t)0x7F38, (q15_t)0xF1B2, (q15_t)0x7F32, + (q15_t)0xF180, (q15_t)0x7F2D, (q15_t)0xF14E, (q15_t)0x7F27, + (q15_t)0xF11C, (q15_t)0x7F21, (q15_t)0xF0EA, (q15_t)0x7F1B, + (q15_t)0xF0B8, (q15_t)0x7F15, (q15_t)0xF086, (q15_t)0x7F0F, + (q15_t)0xF054, (q15_t)0x7F09, (q15_t)0xF022, (q15_t)0x7F03, + (q15_t)0xEFF1, (q15_t)0x7EFD, (q15_t)0xEFBF, (q15_t)0x7EF6, + (q15_t)0xEF8D, (q15_t)0x7EF0, (q15_t)0xEF5B, (q15_t)0x7EE9, + (q15_t)0xEF29, (q15_t)0x7EE3, (q15_t)0xEEF7, (q15_t)0x7EDC, + (q15_t)0xEEC6, (q15_t)0x7ED5, (q15_t)0xEE94, (q15_t)0x7ECF, + (q15_t)0xEE62, (q15_t)0x7EC8, (q15_t)0xEE30, (q15_t)0x7EC1, + (q15_t)0xEDFE, (q15_t)0x7EBA, (q15_t)0xEDCD, (q15_t)0x7EB3, + (q15_t)0xED9B, (q15_t)0x7EAB, (q15_t)0xED69, (q15_t)0x7EA4, + (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xED06, (q15_t)0x7E95, + (q15_t)0xECD4, (q15_t)0x7E8E, (q15_t)0xECA2, (q15_t)0x7E86, + (q15_t)0xEC71, (q15_t)0x7E7F, (q15_t)0xEC3F, (q15_t)0x7E77, + (q15_t)0xEC0D, (q15_t)0x7E6F, (q15_t)0xEBDC, (q15_t)0x7E67, + (q15_t)0xEBAA, (q15_t)0x7E5F, (q15_t)0xEB78, (q15_t)0x7E57, + (q15_t)0xEB47, (q15_t)0x7E4F, (q15_t)0xEB15, (q15_t)0x7E47, + (q15_t)0xEAE4, (q15_t)0x7E3F, (q15_t)0xEAB2, (q15_t)0x7E37, + (q15_t)0xEA80, (q15_t)0x7E2E, (q15_t)0xEA4F, (q15_t)0x7E26, + (q15_t)0xEA1D, (q15_t)0x7E1D, (q15_t)0xE9EC, (q15_t)0x7E14, + (q15_t)0xE9BA, (q15_t)0x7E0C, (q15_t)0xE989, (q15_t)0x7E03, + (q15_t)0xE957, (q15_t)0x7DFA, (q15_t)0xE926, (q15_t)0x7DF1, + (q15_t)0xE8F5, (q15_t)0x7DE8, (q15_t)0xE8C3, (q15_t)0x7DDF, + (q15_t)0xE892, (q15_t)0x7DD6, (q15_t)0xE860, (q15_t)0x7DCD, + (q15_t)0xE82F, (q15_t)0x7DC3, (q15_t)0xE7FD, (q15_t)0x7DBA, + (q15_t)0xE7CC, (q15_t)0x7DB0, (q15_t)0xE79B, (q15_t)0x7DA7, + (q15_t)0xE769, (q15_t)0x7D9D, (q15_t)0xE738, (q15_t)0x7D94, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE6D5, (q15_t)0x7D80, + (q15_t)0xE6A4, (q15_t)0x7D76, (q15_t)0xE673, (q15_t)0x7D6C, + (q15_t)0xE642, (q15_t)0x7D62, (q15_t)0xE610, (q15_t)0x7D58, + (q15_t)0xE5DF, (q15_t)0x7D4E, (q15_t)0xE5AE, (q15_t)0x7D43, + (q15_t)0xE57D, (q15_t)0x7D39, (q15_t)0xE54C, (q15_t)0x7D2F, + (q15_t)0xE51B, (q15_t)0x7D24, (q15_t)0xE4E9, (q15_t)0x7D19, + (q15_t)0xE4B8, (q15_t)0x7D0F, (q15_t)0xE487, (q15_t)0x7D04, + (q15_t)0xE456, (q15_t)0x7CF9, (q15_t)0xE425, (q15_t)0x7CEE, + (q15_t)0xE3F4, (q15_t)0x7CE3, (q15_t)0xE3C3, (q15_t)0x7CD8, + (q15_t)0xE392, (q15_t)0x7CCD, (q15_t)0xE361, (q15_t)0x7CC2, + (q15_t)0xE330, (q15_t)0x7CB7, (q15_t)0xE2FF, (q15_t)0x7CAB, + (q15_t)0xE2CE, (q15_t)0x7CA0, (q15_t)0xE29D, (q15_t)0x7C94, + (q15_t)0xE26C, (q15_t)0x7C89, (q15_t)0xE23B, (q15_t)0x7C7D, + (q15_t)0xE20A, (q15_t)0x7C71, (q15_t)0xE1DA, (q15_t)0x7C66, + (q15_t)0xE1A9, (q15_t)0x7C5A, (q15_t)0xE178, (q15_t)0x7C4E, + (q15_t)0xE147, (q15_t)0x7C42, (q15_t)0xE116, (q15_t)0x7C36, + (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xE0B5, (q15_t)0x7C1D, + (q15_t)0xE084, (q15_t)0x7C11, (q15_t)0xE053, (q15_t)0x7C05, + (q15_t)0xE023, (q15_t)0x7BF8, (q15_t)0xDFF2, (q15_t)0x7BEB, + (q15_t)0xDFC1, (q15_t)0x7BDF, (q15_t)0xDF91, (q15_t)0x7BD2, + (q15_t)0xDF60, (q15_t)0x7BC5, (q15_t)0xDF2F, (q15_t)0x7BB9, + (q15_t)0xDEFF, (q15_t)0x7BAC, (q15_t)0xDECE, (q15_t)0x7B9F, + (q15_t)0xDE9E, (q15_t)0x7B92, (q15_t)0xDE6D, (q15_t)0x7B84, + (q15_t)0xDE3D, (q15_t)0x7B77, (q15_t)0xDE0C, (q15_t)0x7B6A, + (q15_t)0xDDDC, (q15_t)0x7B5D, (q15_t)0xDDAB, (q15_t)0x7B4F, + (q15_t)0xDD7B, (q15_t)0x7B42, (q15_t)0xDD4B, (q15_t)0x7B34, + (q15_t)0xDD1A, (q15_t)0x7B26, (q15_t)0xDCEA, (q15_t)0x7B19, + (q15_t)0xDCBA, (q15_t)0x7B0B, (q15_t)0xDC89, (q15_t)0x7AFD, + (q15_t)0xDC59, (q15_t)0x7AEF, (q15_t)0xDC29, (q15_t)0x7AE1, + (q15_t)0xDBF8, (q15_t)0x7AD3, (q15_t)0xDBC8, (q15_t)0x7AC5, + (q15_t)0xDB98, (q15_t)0x7AB6, (q15_t)0xDB68, (q15_t)0x7AA8, + (q15_t)0xDB38, (q15_t)0x7A9A, (q15_t)0xDB08, (q15_t)0x7A8B, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xDAA7, (q15_t)0x7A6E, + (q15_t)0xDA77, (q15_t)0x7A5F, (q15_t)0xDA47, (q15_t)0x7A50, + (q15_t)0xDA17, (q15_t)0x7A42, (q15_t)0xD9E7, (q15_t)0x7A33, + (q15_t)0xD9B7, (q15_t)0x7A24, (q15_t)0xD987, (q15_t)0x7A15, + (q15_t)0xD957, (q15_t)0x7A05, (q15_t)0xD927, (q15_t)0x79F6, + (q15_t)0xD8F8, (q15_t)0x79E7, (q15_t)0xD8C8, (q15_t)0x79D8, + (q15_t)0xD898, (q15_t)0x79C8, (q15_t)0xD868, (q15_t)0x79B9, + (q15_t)0xD838, (q15_t)0x79A9, (q15_t)0xD809, (q15_t)0x7999, + (q15_t)0xD7D9, (q15_t)0x798A, (q15_t)0xD7A9, (q15_t)0x797A, + (q15_t)0xD779, (q15_t)0x796A, (q15_t)0xD74A, (q15_t)0x795A, + (q15_t)0xD71A, (q15_t)0x794A, (q15_t)0xD6EA, (q15_t)0x793A, + (q15_t)0xD6BB, (q15_t)0x792A, (q15_t)0xD68B, (q15_t)0x7919, + (q15_t)0xD65C, (q15_t)0x7909, (q15_t)0xD62C, (q15_t)0x78F9, + (q15_t)0xD5FD, (q15_t)0x78E8, (q15_t)0xD5CD, (q15_t)0x78D8, + (q15_t)0xD59E, (q15_t)0x78C7, (q15_t)0xD56E, (q15_t)0x78B6, + (q15_t)0xD53F, (q15_t)0x78A6, (q15_t)0xD510, (q15_t)0x7895, + (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD4B1, (q15_t)0x7873, + (q15_t)0xD482, (q15_t)0x7862, (q15_t)0xD452, (q15_t)0x7851, + (q15_t)0xD423, (q15_t)0x7840, (q15_t)0xD3F4, (q15_t)0x782E, + (q15_t)0xD3C5, (q15_t)0x781D, (q15_t)0xD396, (q15_t)0x780C, + (q15_t)0xD367, (q15_t)0x77FA, (q15_t)0xD337, (q15_t)0x77E9, + (q15_t)0xD308, (q15_t)0x77D7, (q15_t)0xD2D9, (q15_t)0x77C5, + (q15_t)0xD2AA, (q15_t)0x77B4, (q15_t)0xD27B, (q15_t)0x77A2, + (q15_t)0xD24C, (q15_t)0x7790, (q15_t)0xD21D, (q15_t)0x777E, + (q15_t)0xD1EE, (q15_t)0x776C, (q15_t)0xD1C0, (q15_t)0x775A, + (q15_t)0xD191, (q15_t)0x7747, (q15_t)0xD162, (q15_t)0x7735, + (q15_t)0xD133, (q15_t)0x7723, (q15_t)0xD104, (q15_t)0x7710, + (q15_t)0xD0D6, (q15_t)0x76FE, (q15_t)0xD0A7, (q15_t)0x76EB, + (q15_t)0xD078, (q15_t)0x76D9, (q15_t)0xD04A, (q15_t)0x76C6, + (q15_t)0xD01B, (q15_t)0x76B3, (q15_t)0xCFEC, (q15_t)0x76A0, + (q15_t)0xCFBE, (q15_t)0x768E, (q15_t)0xCF8F, (q15_t)0x767B, + (q15_t)0xCF61, (q15_t)0x7668, (q15_t)0xCF32, (q15_t)0x7654, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCED5, (q15_t)0x762E, + (q15_t)0xCEA7, (q15_t)0x761B, (q15_t)0xCE79, (q15_t)0x7607, + (q15_t)0xCE4A, (q15_t)0x75F4, (q15_t)0xCE1C, (q15_t)0x75E0, + (q15_t)0xCDEE, (q15_t)0x75CC, (q15_t)0xCDBF, (q15_t)0x75B9, + (q15_t)0xCD91, (q15_t)0x75A5, (q15_t)0xCD63, (q15_t)0x7591, + (q15_t)0xCD35, (q15_t)0x757D, (q15_t)0xCD07, (q15_t)0x7569, + (q15_t)0xCCD9, (q15_t)0x7555, (q15_t)0xCCAB, (q15_t)0x7541, + (q15_t)0xCC7D, (q15_t)0x752D, (q15_t)0xCC4F, (q15_t)0x7519, + (q15_t)0xCC21, (q15_t)0x7504, (q15_t)0xCBF3, (q15_t)0x74F0, + (q15_t)0xCBC5, (q15_t)0x74DB, (q15_t)0xCB97, (q15_t)0x74C7, + (q15_t)0xCB69, (q15_t)0x74B2, (q15_t)0xCB3B, (q15_t)0x749E, + (q15_t)0xCB0D, (q15_t)0x7489, (q15_t)0xCAE0, (q15_t)0x7474, + (q15_t)0xCAB2, (q15_t)0x745F, (q15_t)0xCA84, (q15_t)0x744A, + (q15_t)0xCA57, (q15_t)0x7435, (q15_t)0xCA29, (q15_t)0x7420, + (q15_t)0xC9FB, (q15_t)0x740B, (q15_t)0xC9CE, (q15_t)0x73F6, + (q15_t)0xC9A0, (q15_t)0x73E0, (q15_t)0xC973, (q15_t)0x73CB, + (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC918, (q15_t)0x73A0, + (q15_t)0xC8EB, (q15_t)0x738A, (q15_t)0xC8BD, (q15_t)0x7375, + (q15_t)0xC890, (q15_t)0x735F, (q15_t)0xC863, (q15_t)0x7349, + (q15_t)0xC835, (q15_t)0x7333, (q15_t)0xC808, (q15_t)0x731D, + (q15_t)0xC7DB, (q15_t)0x7307, (q15_t)0xC7AE, (q15_t)0x72F1, + (q15_t)0xC781, (q15_t)0x72DB, (q15_t)0xC754, (q15_t)0x72C5, + (q15_t)0xC727, (q15_t)0x72AF, (q15_t)0xC6F9, (q15_t)0x7298, + (q15_t)0xC6CD, (q15_t)0x7282, (q15_t)0xC6A0, (q15_t)0x726B, + (q15_t)0xC673, (q15_t)0x7255, (q15_t)0xC646, (q15_t)0x723E, + (q15_t)0xC619, (q15_t)0x7227, (q15_t)0xC5EC, (q15_t)0x7211, + (q15_t)0xC5BF, (q15_t)0x71FA, (q15_t)0xC593, (q15_t)0x71E3, + (q15_t)0xC566, (q15_t)0x71CC, (q15_t)0xC539, (q15_t)0x71B5, + (q15_t)0xC50D, (q15_t)0x719E, (q15_t)0xC4E0, (q15_t)0x7186, + (q15_t)0xC4B3, (q15_t)0x716F, (q15_t)0xC487, (q15_t)0x7158, + (q15_t)0xC45A, (q15_t)0x7141, (q15_t)0xC42E, (q15_t)0x7129, + (q15_t)0xC402, (q15_t)0x7112, (q15_t)0xC3D5, (q15_t)0x70FA, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC37C, (q15_t)0x70CB, + (q15_t)0xC350, (q15_t)0x70B3, (q15_t)0xC324, (q15_t)0x709B, + (q15_t)0xC2F8, (q15_t)0x7083, (q15_t)0xC2CC, (q15_t)0x706B, + (q15_t)0xC29F, (q15_t)0x7053, (q15_t)0xC273, (q15_t)0x703B, + (q15_t)0xC247, (q15_t)0x7023, (q15_t)0xC21B, (q15_t)0x700A, + (q15_t)0xC1EF, (q15_t)0x6FF2, (q15_t)0xC1C3, (q15_t)0x6FDA, + (q15_t)0xC197, (q15_t)0x6FC1, (q15_t)0xC16C, (q15_t)0x6FA9, + (q15_t)0xC140, (q15_t)0x6F90, (q15_t)0xC114, (q15_t)0x6F77, + (q15_t)0xC0E8, (q15_t)0x6F5F, (q15_t)0xC0BC, (q15_t)0x6F46, + (q15_t)0xC091, (q15_t)0x6F2D, (q15_t)0xC065, (q15_t)0x6F14, + (q15_t)0xC03A, (q15_t)0x6EFB, (q15_t)0xC00E, (q15_t)0x6EE2, + (q15_t)0xBFE2, (q15_t)0x6EC9, (q15_t)0xBFB7, (q15_t)0x6EAF, + (q15_t)0xBF8C, (q15_t)0x6E96, (q15_t)0xBF60, (q15_t)0x6E7D, + (q15_t)0xBF35, (q15_t)0x6E63, (q15_t)0xBF09, (q15_t)0x6E4A, + (q15_t)0xBEDE, (q15_t)0x6E30, (q15_t)0xBEB3, (q15_t)0x6E17, + (q15_t)0xBE88, (q15_t)0x6DFD, (q15_t)0xBE5D, (q15_t)0x6DE3, + (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBE06, (q15_t)0x6DB0, + (q15_t)0xBDDB, (q15_t)0x6D96, (q15_t)0xBDB0, (q15_t)0x6D7C, + (q15_t)0xBD85, (q15_t)0x6D62, (q15_t)0xBD5A, (q15_t)0x6D48, + (q15_t)0xBD2F, (q15_t)0x6D2D, (q15_t)0xBD05, (q15_t)0x6D13, + (q15_t)0xBCDA, (q15_t)0x6CF9, (q15_t)0xBCAF, (q15_t)0x6CDE, + (q15_t)0xBC84, (q15_t)0x6CC4, (q15_t)0xBC5A, (q15_t)0x6CA9, + (q15_t)0xBC2F, (q15_t)0x6C8F, (q15_t)0xBC04, (q15_t)0x6C74, + (q15_t)0xBBDA, (q15_t)0x6C59, (q15_t)0xBBAF, (q15_t)0x6C3F, + (q15_t)0xBB85, (q15_t)0x6C24, (q15_t)0xBB5A, (q15_t)0x6C09, + (q15_t)0xBB30, (q15_t)0x6BEE, (q15_t)0xBB05, (q15_t)0x6BD3, + (q15_t)0xBADB, (q15_t)0x6BB8, (q15_t)0xBAB1, (q15_t)0x6B9C, + (q15_t)0xBA87, (q15_t)0x6B81, (q15_t)0xBA5C, (q15_t)0x6B66, + (q15_t)0xBA32, (q15_t)0x6B4A, (q15_t)0xBA08, (q15_t)0x6B2F, + (q15_t)0xB9DE, (q15_t)0x6B13, (q15_t)0xB9B4, (q15_t)0x6AF8, + (q15_t)0xB98A, (q15_t)0x6ADC, (q15_t)0xB960, (q15_t)0x6AC1, + (q15_t)0xB936, (q15_t)0x6AA5, (q15_t)0xB90C, (q15_t)0x6A89, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB8B9, (q15_t)0x6A51, + (q15_t)0xB88F, (q15_t)0x6A35, (q15_t)0xB865, (q15_t)0x6A19, + (q15_t)0xB83C, (q15_t)0x69FD, (q15_t)0xB812, (q15_t)0x69E1, + (q15_t)0xB7E9, (q15_t)0x69C4, (q15_t)0xB7BF, (q15_t)0x69A8, + (q15_t)0xB796, (q15_t)0x698C, (q15_t)0xB76C, (q15_t)0x696F, + (q15_t)0xB743, (q15_t)0x6953, (q15_t)0xB719, (q15_t)0x6936, + (q15_t)0xB6F0, (q15_t)0x6919, (q15_t)0xB6C7, (q15_t)0x68FD, + (q15_t)0xB69E, (q15_t)0x68E0, (q15_t)0xB675, (q15_t)0x68C3, + (q15_t)0xB64B, (q15_t)0x68A6, (q15_t)0xB622, (q15_t)0x6889, + (q15_t)0xB5F9, (q15_t)0x686C, (q15_t)0xB5D0, (q15_t)0x684F, + (q15_t)0xB5A7, (q15_t)0x6832, (q15_t)0xB57E, (q15_t)0x6815, + (q15_t)0xB556, (q15_t)0x67F7, (q15_t)0xB52D, (q15_t)0x67DA, + (q15_t)0xB504, (q15_t)0x67BD, (q15_t)0xB4DB, (q15_t)0x679F, + (q15_t)0xB4B3, (q15_t)0x6782, (q15_t)0xB48A, (q15_t)0x6764, + (q15_t)0xB461, (q15_t)0x6746, (q15_t)0xB439, (q15_t)0x6729, + (q15_t)0xB410, (q15_t)0x670B, (q15_t)0xB3E8, (q15_t)0x66ED, + (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB397, (q15_t)0x66B1, + (q15_t)0xB36F, (q15_t)0x6693, (q15_t)0xB347, (q15_t)0x6675, + (q15_t)0xB31E, (q15_t)0x6657, (q15_t)0xB2F6, (q15_t)0x6639, + (q15_t)0xB2CE, (q15_t)0x661A, (q15_t)0xB2A6, (q15_t)0x65FC, + (q15_t)0xB27E, (q15_t)0x65DD, (q15_t)0xB256, (q15_t)0x65BF, + (q15_t)0xB22E, (q15_t)0x65A0, (q15_t)0xB206, (q15_t)0x6582, + (q15_t)0xB1DE, (q15_t)0x6563, (q15_t)0xB1B7, (q15_t)0x6545, + (q15_t)0xB18F, (q15_t)0x6526, (q15_t)0xB167, (q15_t)0x6507, + (q15_t)0xB140, (q15_t)0x64E8, (q15_t)0xB118, (q15_t)0x64C9, + (q15_t)0xB0F0, (q15_t)0x64AA, (q15_t)0xB0C9, (q15_t)0x648B, + (q15_t)0xB0A1, (q15_t)0x646C, (q15_t)0xB07A, (q15_t)0x644D, + (q15_t)0xB053, (q15_t)0x642D, (q15_t)0xB02B, (q15_t)0x640E, + (q15_t)0xB004, (q15_t)0x63EF, (q15_t)0xAFDD, (q15_t)0x63CF, + (q15_t)0xAFB6, (q15_t)0x63B0, (q15_t)0xAF8F, (q15_t)0x6390, + (q15_t)0xAF68, (q15_t)0x6371, (q15_t)0xAF40, (q15_t)0x6351, + (q15_t)0xAF1A, (q15_t)0x6331, (q15_t)0xAEF3, (q15_t)0x6311, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAEA5, (q15_t)0x62D2, + (q15_t)0xAE7E, (q15_t)0x62B2, (q15_t)0xAE57, (q15_t)0x6292, + (q15_t)0xAE31, (q15_t)0x6271, (q15_t)0xAE0A, (q15_t)0x6251, + (q15_t)0xADE3, (q15_t)0x6231, (q15_t)0xADBD, (q15_t)0x6211, + (q15_t)0xAD96, (q15_t)0x61F1, (q15_t)0xAD70, (q15_t)0x61D0, + (q15_t)0xAD4A, (q15_t)0x61B0, (q15_t)0xAD23, (q15_t)0x618F, + (q15_t)0xACFD, (q15_t)0x616F, (q15_t)0xACD7, (q15_t)0x614E, + (q15_t)0xACB1, (q15_t)0x612D, (q15_t)0xAC8A, (q15_t)0x610D, + (q15_t)0xAC64, (q15_t)0x60EC, (q15_t)0xAC3E, (q15_t)0x60CB, + (q15_t)0xAC18, (q15_t)0x60AA, (q15_t)0xABF2, (q15_t)0x6089, + (q15_t)0xABCC, (q15_t)0x6068, (q15_t)0xABA7, (q15_t)0x6047, + (q15_t)0xAB81, (q15_t)0x6026, (q15_t)0xAB5B, (q15_t)0x6004, + (q15_t)0xAB35, (q15_t)0x5FE3, (q15_t)0xAB10, (q15_t)0x5FC2, + (q15_t)0xAAEA, (q15_t)0x5FA0, (q15_t)0xAAC5, (q15_t)0x5F7F, + (q15_t)0xAA9F, (q15_t)0x5F5E, (q15_t)0xAA7A, (q15_t)0x5F3C, + (q15_t)0xAA54, (q15_t)0x5F1A, (q15_t)0xAA2F, (q15_t)0x5EF9, + (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA9E5, (q15_t)0x5EB5, + (q15_t)0xA9BF, (q15_t)0x5E93, (q15_t)0xA99A, (q15_t)0x5E71, + (q15_t)0xA975, (q15_t)0x5E50, (q15_t)0xA950, (q15_t)0x5E2D, + (q15_t)0xA92B, (q15_t)0x5E0B, (q15_t)0xA906, (q15_t)0x5DE9, + (q15_t)0xA8E2, (q15_t)0x5DC7, (q15_t)0xA8BD, (q15_t)0x5DA5, + (q15_t)0xA898, (q15_t)0x5D83, (q15_t)0xA873, (q15_t)0x5D60, + (q15_t)0xA84F, (q15_t)0x5D3E, (q15_t)0xA82A, (q15_t)0x5D1B, + (q15_t)0xA806, (q15_t)0x5CF9, (q15_t)0xA7E1, (q15_t)0x5CD6, + (q15_t)0xA7BD, (q15_t)0x5CB4, (q15_t)0xA798, (q15_t)0x5C91, + (q15_t)0xA774, (q15_t)0x5C6E, (q15_t)0xA750, (q15_t)0x5C4B, + (q15_t)0xA72B, (q15_t)0x5C29, (q15_t)0xA707, (q15_t)0x5C06, + (q15_t)0xA6E3, (q15_t)0x5BE3, (q15_t)0xA6BF, (q15_t)0x5BC0, + (q15_t)0xA69B, (q15_t)0x5B9D, (q15_t)0xA677, (q15_t)0x5B79, + (q15_t)0xA653, (q15_t)0x5B56, (q15_t)0xA62F, (q15_t)0x5B33, + (q15_t)0xA60C, (q15_t)0x5B10, (q15_t)0xA5E8, (q15_t)0x5AEC, + (q15_t)0xA5C4, (q15_t)0x5AC9, (q15_t)0xA5A1, (q15_t)0x5AA5, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA55A, (q15_t)0x5A5E, + (q15_t)0xA536, (q15_t)0x5A3B, (q15_t)0xA513, (q15_t)0x5A17, + (q15_t)0xA4EF, (q15_t)0x59F3, (q15_t)0xA4CC, (q15_t)0x59D0, + (q15_t)0xA4A9, (q15_t)0x59AC, (q15_t)0xA486, (q15_t)0x5988, + (q15_t)0xA462, (q15_t)0x5964, (q15_t)0xA43F, (q15_t)0x5940, + (q15_t)0xA41C, (q15_t)0x591C, (q15_t)0xA3F9, (q15_t)0x58F8, + (q15_t)0xA3D6, (q15_t)0x58D4, (q15_t)0xA3B4, (q15_t)0x58AF, + (q15_t)0xA391, (q15_t)0x588B, (q15_t)0xA36E, (q15_t)0x5867, + (q15_t)0xA34B, (q15_t)0x5842, (q15_t)0xA329, (q15_t)0x581E, + (q15_t)0xA306, (q15_t)0x57F9, (q15_t)0xA2E4, (q15_t)0x57D5, + (q15_t)0xA2C1, (q15_t)0x57B0, (q15_t)0xA29F, (q15_t)0x578C, + (q15_t)0xA27C, (q15_t)0x5767, (q15_t)0xA25A, (q15_t)0x5742, + (q15_t)0xA238, (q15_t)0x571D, (q15_t)0xA216, (q15_t)0x56F9, + (q15_t)0xA1F4, (q15_t)0x56D4, (q15_t)0xA1D2, (q15_t)0x56AF, + (q15_t)0xA1AF, (q15_t)0x568A, (q15_t)0xA18E, (q15_t)0x5665, + (q15_t)0xA16C, (q15_t)0x5640, (q15_t)0xA14A, (q15_t)0x561A, + (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0xA106, (q15_t)0x55D0, + (q15_t)0xA0E5, (q15_t)0x55AB, (q15_t)0xA0C3, (q15_t)0x5585, + (q15_t)0xA0A1, (q15_t)0x5560, (q15_t)0xA080, (q15_t)0x553A, + (q15_t)0xA05F, (q15_t)0x5515, (q15_t)0xA03D, (q15_t)0x54EF, + (q15_t)0xA01C, (q15_t)0x54CA, (q15_t)0x9FFB, (q15_t)0x54A4, + (q15_t)0x9FD9, (q15_t)0x547E, (q15_t)0x9FB8, (q15_t)0x5458, + (q15_t)0x9F97, (q15_t)0x5433, (q15_t)0x9F76, (q15_t)0x540D, + (q15_t)0x9F55, (q15_t)0x53E7, (q15_t)0x9F34, (q15_t)0x53C1, + (q15_t)0x9F13, (q15_t)0x539B, (q15_t)0x9EF2, (q15_t)0x5375, + (q15_t)0x9ED2, (q15_t)0x534E, (q15_t)0x9EB1, (q15_t)0x5328, + (q15_t)0x9E90, (q15_t)0x5302, (q15_t)0x9E70, (q15_t)0x52DC, + (q15_t)0x9E4F, (q15_t)0x52B5, (q15_t)0x9E2F, (q15_t)0x528F, + (q15_t)0x9E0E, (q15_t)0x5269, (q15_t)0x9DEE, (q15_t)0x5242, + (q15_t)0x9DCE, (q15_t)0x521C, (q15_t)0x9DAE, (q15_t)0x51F5, + (q15_t)0x9D8E, (q15_t)0x51CE, (q15_t)0x9D6D, (q15_t)0x51A8, + (q15_t)0x9D4D, (q15_t)0x5181, (q15_t)0x9D2D, (q15_t)0x515A, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9CEE, (q15_t)0x510C, + (q15_t)0x9CCE, (q15_t)0x50E5, (q15_t)0x9CAE, (q15_t)0x50BF, + (q15_t)0x9C8E, (q15_t)0x5097, (q15_t)0x9C6F, (q15_t)0x5070, + (q15_t)0x9C4F, (q15_t)0x5049, (q15_t)0x9C30, (q15_t)0x5022, + (q15_t)0x9C10, (q15_t)0x4FFB, (q15_t)0x9BF1, (q15_t)0x4FD4, + (q15_t)0x9BD2, (q15_t)0x4FAC, (q15_t)0x9BB2, (q15_t)0x4F85, + (q15_t)0x9B93, (q15_t)0x4F5E, (q15_t)0x9B74, (q15_t)0x4F36, + (q15_t)0x9B55, (q15_t)0x4F0F, (q15_t)0x9B36, (q15_t)0x4EE7, + (q15_t)0x9B17, (q15_t)0x4EBF, (q15_t)0x9AF8, (q15_t)0x4E98, + (q15_t)0x9AD9, (q15_t)0x4E70, (q15_t)0x9ABA, (q15_t)0x4E48, + (q15_t)0x9A9C, (q15_t)0x4E21, (q15_t)0x9A7D, (q15_t)0x4DF9, + (q15_t)0x9A5F, (q15_t)0x4DD1, (q15_t)0x9A40, (q15_t)0x4DA9, + (q15_t)0x9A22, (q15_t)0x4D81, (q15_t)0x9A03, (q15_t)0x4D59, + (q15_t)0x99E5, (q15_t)0x4D31, (q15_t)0x99C6, (q15_t)0x4D09, + (q15_t)0x99A8, (q15_t)0x4CE1, (q15_t)0x998A, (q15_t)0x4CB8, + (q15_t)0x996C, (q15_t)0x4C90, (q15_t)0x994E, (q15_t)0x4C68, + (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x9912, (q15_t)0x4C17, + (q15_t)0x98F4, (q15_t)0x4BEF, (q15_t)0x98D6, (q15_t)0x4BC6, + (q15_t)0x98B9, (q15_t)0x4B9E, (q15_t)0x989B, (q15_t)0x4B75, + (q15_t)0x987D, (q15_t)0x4B4C, (q15_t)0x9860, (q15_t)0x4B24, + (q15_t)0x9842, (q15_t)0x4AFB, (q15_t)0x9825, (q15_t)0x4AD2, + (q15_t)0x9808, (q15_t)0x4AA9, (q15_t)0x97EA, (q15_t)0x4A81, + (q15_t)0x97CD, (q15_t)0x4A58, (q15_t)0x97B0, (q15_t)0x4A2F, + (q15_t)0x9793, (q15_t)0x4A06, (q15_t)0x9776, (q15_t)0x49DD, + (q15_t)0x9759, (q15_t)0x49B4, (q15_t)0x973C, (q15_t)0x498A, + (q15_t)0x971F, (q15_t)0x4961, (q15_t)0x9702, (q15_t)0x4938, + (q15_t)0x96E6, (q15_t)0x490F, (q15_t)0x96C9, (q15_t)0x48E6, + (q15_t)0x96AC, (q15_t)0x48BC, (q15_t)0x9690, (q15_t)0x4893, + (q15_t)0x9673, (q15_t)0x4869, (q15_t)0x9657, (q15_t)0x4840, + (q15_t)0x963B, (q15_t)0x4816, (q15_t)0x961E, (q15_t)0x47ED, + (q15_t)0x9602, (q15_t)0x47C3, (q15_t)0x95E6, (q15_t)0x479A, + (q15_t)0x95CA, (q15_t)0x4770, (q15_t)0x95AE, (q15_t)0x4746, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x9576, (q15_t)0x46F3, + (q15_t)0x955A, (q15_t)0x46C9, (q15_t)0x953E, (q15_t)0x469F, + (q15_t)0x9523, (q15_t)0x4675, (q15_t)0x9507, (q15_t)0x464B, + (q15_t)0x94EC, (q15_t)0x4621, (q15_t)0x94D0, (q15_t)0x45F7, + (q15_t)0x94B5, (q15_t)0x45CD, (q15_t)0x9499, (q15_t)0x45A3, + (q15_t)0x947E, (q15_t)0x4578, (q15_t)0x9463, (q15_t)0x454E, + (q15_t)0x9447, (q15_t)0x4524, (q15_t)0x942C, (q15_t)0x44FA, + (q15_t)0x9411, (q15_t)0x44CF, (q15_t)0x93F6, (q15_t)0x44A5, + (q15_t)0x93DB, (q15_t)0x447A, (q15_t)0x93C0, (q15_t)0x4450, + (q15_t)0x93A6, (q15_t)0x4425, (q15_t)0x938B, (q15_t)0x43FB, + (q15_t)0x9370, (q15_t)0x43D0, (q15_t)0x9356, (q15_t)0x43A5, + (q15_t)0x933B, (q15_t)0x437B, (q15_t)0x9321, (q15_t)0x4350, + (q15_t)0x9306, (q15_t)0x4325, (q15_t)0x92EC, (q15_t)0x42FA, + (q15_t)0x92D2, (q15_t)0x42D0, (q15_t)0x92B7, (q15_t)0x42A5, + (q15_t)0x929D, (q15_t)0x427A, (q15_t)0x9283, (q15_t)0x424F, + (q15_t)0x9269, (q15_t)0x4224, (q15_t)0x924F, (q15_t)0x41F9, + (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x921C, (q15_t)0x41A2, + (q15_t)0x9202, (q15_t)0x4177, (q15_t)0x91E8, (q15_t)0x414C, + (q15_t)0x91CF, (q15_t)0x4121, (q15_t)0x91B5, (q15_t)0x40F6, + (q15_t)0x919C, (q15_t)0x40CA, (q15_t)0x9182, (q15_t)0x409F, + (q15_t)0x9169, (q15_t)0x4073, (q15_t)0x9150, (q15_t)0x4048, + (q15_t)0x9136, (q15_t)0x401D, (q15_t)0x911D, (q15_t)0x3FF1, + (q15_t)0x9104, (q15_t)0x3FC5, (q15_t)0x90EB, (q15_t)0x3F9A, + (q15_t)0x90D2, (q15_t)0x3F6E, (q15_t)0x90B9, (q15_t)0x3F43, + (q15_t)0x90A0, (q15_t)0x3F17, (q15_t)0x9088, (q15_t)0x3EEB, + (q15_t)0x906F, (q15_t)0x3EBF, (q15_t)0x9056, (q15_t)0x3E93, + (q15_t)0x903E, (q15_t)0x3E68, (q15_t)0x9025, (q15_t)0x3E3C, + (q15_t)0x900D, (q15_t)0x3E10, (q15_t)0x8FF5, (q15_t)0x3DE4, + (q15_t)0x8FDC, (q15_t)0x3DB8, (q15_t)0x8FC4, (q15_t)0x3D8C, + (q15_t)0x8FAC, (q15_t)0x3D60, (q15_t)0x8F94, (q15_t)0x3D33, + (q15_t)0x8F7C, (q15_t)0x3D07, (q15_t)0x8F64, (q15_t)0x3CDB, + (q15_t)0x8F4C, (q15_t)0x3CAF, (q15_t)0x8F34, (q15_t)0x3C83, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8F05, (q15_t)0x3C2A, + (q15_t)0x8EED, (q15_t)0x3BFD, (q15_t)0x8ED6, (q15_t)0x3BD1, + (q15_t)0x8EBE, (q15_t)0x3BA5, (q15_t)0x8EA7, (q15_t)0x3B78, + (q15_t)0x8E90, (q15_t)0x3B4C, (q15_t)0x8E79, (q15_t)0x3B1F, + (q15_t)0x8E61, (q15_t)0x3AF2, (q15_t)0x8E4A, (q15_t)0x3AC6, + (q15_t)0x8E33, (q15_t)0x3A99, (q15_t)0x8E1C, (q15_t)0x3A6C, + (q15_t)0x8E05, (q15_t)0x3A40, (q15_t)0x8DEE, (q15_t)0x3A13, + (q15_t)0x8DD8, (q15_t)0x39E6, (q15_t)0x8DC1, (q15_t)0x39B9, + (q15_t)0x8DAA, (q15_t)0x398C, (q15_t)0x8D94, (q15_t)0x395F, + (q15_t)0x8D7D, (q15_t)0x3932, (q15_t)0x8D67, (q15_t)0x3906, + (q15_t)0x8D50, (q15_t)0x38D8, (q15_t)0x8D3A, (q15_t)0x38AB, + (q15_t)0x8D24, (q15_t)0x387E, (q15_t)0x8D0E, (q15_t)0x3851, + (q15_t)0x8CF8, (q15_t)0x3824, (q15_t)0x8CE2, (q15_t)0x37F7, + (q15_t)0x8CCC, (q15_t)0x37CA, (q15_t)0x8CB6, (q15_t)0x379C, + (q15_t)0x8CA0, (q15_t)0x376F, (q15_t)0x8C8A, (q15_t)0x3742, + (q15_t)0x8C75, (q15_t)0x3714, (q15_t)0x8C5F, (q15_t)0x36E7, + (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8C34, (q15_t)0x368C, + (q15_t)0x8C1F, (q15_t)0x365F, (q15_t)0x8C09, (q15_t)0x3631, + (q15_t)0x8BF4, (q15_t)0x3604, (q15_t)0x8BDF, (q15_t)0x35D6, + (q15_t)0x8BCA, (q15_t)0x35A8, (q15_t)0x8BB5, (q15_t)0x357B, + (q15_t)0x8BA0, (q15_t)0x354D, (q15_t)0x8B8B, (q15_t)0x351F, + (q15_t)0x8B76, (q15_t)0x34F2, (q15_t)0x8B61, (q15_t)0x34C4, + (q15_t)0x8B4D, (q15_t)0x3496, (q15_t)0x8B38, (q15_t)0x3468, + (q15_t)0x8B24, (q15_t)0x343A, (q15_t)0x8B0F, (q15_t)0x340C, + (q15_t)0x8AFB, (q15_t)0x33DE, (q15_t)0x8AE6, (q15_t)0x33B0, + (q15_t)0x8AD2, (q15_t)0x3382, (q15_t)0x8ABE, (q15_t)0x3354, + (q15_t)0x8AAA, (q15_t)0x3326, (q15_t)0x8A96, (q15_t)0x32F8, + (q15_t)0x8A82, (q15_t)0x32CA, (q15_t)0x8A6E, (q15_t)0x329C, + (q15_t)0x8A5A, (q15_t)0x326E, (q15_t)0x8A46, (q15_t)0x3240, + (q15_t)0x8A33, (q15_t)0x3211, (q15_t)0x8A1F, (q15_t)0x31E3, + (q15_t)0x8A0B, (q15_t)0x31B5, (q15_t)0x89F8, (q15_t)0x3186, + (q15_t)0x89E4, (q15_t)0x3158, (q15_t)0x89D1, (q15_t)0x312A, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x89AB, (q15_t)0x30CD, + (q15_t)0x8997, (q15_t)0x309E, (q15_t)0x8984, (q15_t)0x3070, + (q15_t)0x8971, (q15_t)0x3041, (q15_t)0x895F, (q15_t)0x3013, + (q15_t)0x894C, (q15_t)0x2FE4, (q15_t)0x8939, (q15_t)0x2FB5, + (q15_t)0x8926, (q15_t)0x2F87, (q15_t)0x8914, (q15_t)0x2F58, + (q15_t)0x8901, (q15_t)0x2F29, (q15_t)0x88EF, (q15_t)0x2EFB, + (q15_t)0x88DC, (q15_t)0x2ECC, (q15_t)0x88CA, (q15_t)0x2E9D, + (q15_t)0x88B8, (q15_t)0x2E6E, (q15_t)0x88A5, (q15_t)0x2E3F, + (q15_t)0x8893, (q15_t)0x2E11, (q15_t)0x8881, (q15_t)0x2DE2, + (q15_t)0x886F, (q15_t)0x2DB3, (q15_t)0x885D, (q15_t)0x2D84, + (q15_t)0x884B, (q15_t)0x2D55, (q15_t)0x883A, (q15_t)0x2D26, + (q15_t)0x8828, (q15_t)0x2CF7, (q15_t)0x8816, (q15_t)0x2CC8, + (q15_t)0x8805, (q15_t)0x2C98, (q15_t)0x87F3, (q15_t)0x2C69, + (q15_t)0x87E2, (q15_t)0x2C3A, (q15_t)0x87D1, (q15_t)0x2C0B, + (q15_t)0x87BF, (q15_t)0x2BDC, (q15_t)0x87AE, (q15_t)0x2BAD, + (q15_t)0x879D, (q15_t)0x2B7D, (q15_t)0x878C, (q15_t)0x2B4E, + (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x876A, (q15_t)0x2AEF, + (q15_t)0x8759, (q15_t)0x2AC0, (q15_t)0x8749, (q15_t)0x2A91, + (q15_t)0x8738, (q15_t)0x2A61, (q15_t)0x8727, (q15_t)0x2A32, + (q15_t)0x8717, (q15_t)0x2A02, (q15_t)0x8706, (q15_t)0x29D3, + (q15_t)0x86F6, (q15_t)0x29A3, (q15_t)0x86E6, (q15_t)0x2974, + (q15_t)0x86D5, (q15_t)0x2944, (q15_t)0x86C5, (q15_t)0x2915, + (q15_t)0x86B5, (q15_t)0x28E5, (q15_t)0x86A5, (q15_t)0x28B5, + (q15_t)0x8695, (q15_t)0x2886, (q15_t)0x8685, (q15_t)0x2856, + (q15_t)0x8675, (q15_t)0x2826, (q15_t)0x8666, (q15_t)0x27F6, + (q15_t)0x8656, (q15_t)0x27C7, (q15_t)0x8646, (q15_t)0x2797, + (q15_t)0x8637, (q15_t)0x2767, (q15_t)0x8627, (q15_t)0x2737, + (q15_t)0x8618, (q15_t)0x2707, (q15_t)0x8609, (q15_t)0x26D8, + (q15_t)0x85FA, (q15_t)0x26A8, (q15_t)0x85EA, (q15_t)0x2678, + (q15_t)0x85DB, (q15_t)0x2648, (q15_t)0x85CC, (q15_t)0x2618, + (q15_t)0x85BD, (q15_t)0x25E8, (q15_t)0x85AF, (q15_t)0x25B8, + (q15_t)0x85A0, (q15_t)0x2588, (q15_t)0x8591, (q15_t)0x2558, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x8574, (q15_t)0x24F7, + (q15_t)0x8565, (q15_t)0x24C7, (q15_t)0x8557, (q15_t)0x2497, + (q15_t)0x8549, (q15_t)0x2467, (q15_t)0x853A, (q15_t)0x2437, + (q15_t)0x852C, (q15_t)0x2407, (q15_t)0x851E, (q15_t)0x23D6, + (q15_t)0x8510, (q15_t)0x23A6, (q15_t)0x8502, (q15_t)0x2376, + (q15_t)0x84F4, (q15_t)0x2345, (q15_t)0x84E6, (q15_t)0x2315, + (q15_t)0x84D9, (q15_t)0x22E5, (q15_t)0x84CB, (q15_t)0x22B4, + (q15_t)0x84BD, (q15_t)0x2284, (q15_t)0x84B0, (q15_t)0x2254, + (q15_t)0x84A2, (q15_t)0x2223, (q15_t)0x8495, (q15_t)0x21F3, + (q15_t)0x8488, (q15_t)0x21C2, (q15_t)0x847B, (q15_t)0x2192, + (q15_t)0x846D, (q15_t)0x2161, (q15_t)0x8460, (q15_t)0x2131, + (q15_t)0x8453, (q15_t)0x2100, (q15_t)0x8446, (q15_t)0x20D0, + (q15_t)0x843A, (q15_t)0x209F, (q15_t)0x842D, (q15_t)0x206E, + (q15_t)0x8420, (q15_t)0x203E, (q15_t)0x8414, (q15_t)0x200D, + (q15_t)0x8407, (q15_t)0x1FDC, (q15_t)0x83FA, (q15_t)0x1FAC, + (q15_t)0x83EE, (q15_t)0x1F7B, (q15_t)0x83E2, (q15_t)0x1F4A, + (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x83C9, (q15_t)0x1EE9, + (q15_t)0x83BD, (q15_t)0x1EB8, (q15_t)0x83B1, (q15_t)0x1E87, + (q15_t)0x83A5, (q15_t)0x1E56, (q15_t)0x8399, (q15_t)0x1E25, + (q15_t)0x838E, (q15_t)0x1DF5, (q15_t)0x8382, (q15_t)0x1DC4, + (q15_t)0x8376, (q15_t)0x1D93, (q15_t)0x836B, (q15_t)0x1D62, + (q15_t)0x835F, (q15_t)0x1D31, (q15_t)0x8354, (q15_t)0x1D00, + (q15_t)0x8348, (q15_t)0x1CCF, (q15_t)0x833D, (q15_t)0x1C9E, + (q15_t)0x8332, (q15_t)0x1C6D, (q15_t)0x8327, (q15_t)0x1C3C, + (q15_t)0x831C, (q15_t)0x1C0B, (q15_t)0x8311, (q15_t)0x1BDA, + (q15_t)0x8306, (q15_t)0x1BA9, (q15_t)0x82FB, (q15_t)0x1B78, + (q15_t)0x82F0, (q15_t)0x1B47, (q15_t)0x82E6, (q15_t)0x1B16, + (q15_t)0x82DB, (q15_t)0x1AE4, (q15_t)0x82D0, (q15_t)0x1AB3, + (q15_t)0x82C6, (q15_t)0x1A82, (q15_t)0x82BC, (q15_t)0x1A51, + (q15_t)0x82B1, (q15_t)0x1A20, (q15_t)0x82A7, (q15_t)0x19EF, + (q15_t)0x829D, (q15_t)0x19BD, (q15_t)0x8293, (q15_t)0x198C, + (q15_t)0x8289, (q15_t)0x195B, (q15_t)0x827F, (q15_t)0x192A, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x826B, (q15_t)0x18C7, + (q15_t)0x8262, (q15_t)0x1896, (q15_t)0x8258, (q15_t)0x1864, + (q15_t)0x824F, (q15_t)0x1833, (q15_t)0x8245, (q15_t)0x1802, + (q15_t)0x823C, (q15_t)0x17D0, (q15_t)0x8232, (q15_t)0x179F, + (q15_t)0x8229, (q15_t)0x176D, (q15_t)0x8220, (q15_t)0x173C, + (q15_t)0x8217, (q15_t)0x170A, (q15_t)0x820E, (q15_t)0x16D9, + (q15_t)0x8205, (q15_t)0x16A8, (q15_t)0x81FC, (q15_t)0x1676, + (q15_t)0x81F3, (q15_t)0x1645, (q15_t)0x81EB, (q15_t)0x1613, + (q15_t)0x81E2, (q15_t)0x15E2, (q15_t)0x81D9, (q15_t)0x15B0, + (q15_t)0x81D1, (q15_t)0x157F, (q15_t)0x81C8, (q15_t)0x154D, + (q15_t)0x81C0, (q15_t)0x151B, (q15_t)0x81B8, (q15_t)0x14EA, + (q15_t)0x81B0, (q15_t)0x14B8, (q15_t)0x81A8, (q15_t)0x1487, + (q15_t)0x81A0, (q15_t)0x1455, (q15_t)0x8198, (q15_t)0x1423, + (q15_t)0x8190, (q15_t)0x13F2, (q15_t)0x8188, (q15_t)0x13C0, + (q15_t)0x8180, (q15_t)0x138E, (q15_t)0x8179, (q15_t)0x135D, + (q15_t)0x8171, (q15_t)0x132B, (q15_t)0x816A, (q15_t)0x12F9, + (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x815B, (q15_t)0x1296, + (q15_t)0x8154, (q15_t)0x1264, (q15_t)0x814C, (q15_t)0x1232, + (q15_t)0x8145, (q15_t)0x1201, (q15_t)0x813E, (q15_t)0x11CF, + (q15_t)0x8137, (q15_t)0x119D, (q15_t)0x8130, (q15_t)0x116B, + (q15_t)0x812A, (q15_t)0x1139, (q15_t)0x8123, (q15_t)0x1108, + (q15_t)0x811C, (q15_t)0x10D6, (q15_t)0x8116, (q15_t)0x10A4, + (q15_t)0x810F, (q15_t)0x1072, (q15_t)0x8109, (q15_t)0x1040, + (q15_t)0x8102, (q15_t)0x100E, (q15_t)0x80FC, (q15_t)0x0FDD, + (q15_t)0x80F6, (q15_t)0x0FAB, (q15_t)0x80F0, (q15_t)0x0F79, + (q15_t)0x80EA, (q15_t)0x0F47, (q15_t)0x80E4, (q15_t)0x0F15, + (q15_t)0x80DE, (q15_t)0x0EE3, (q15_t)0x80D8, (q15_t)0x0EB1, + (q15_t)0x80D2, (q15_t)0x0E7F, (q15_t)0x80CD, (q15_t)0x0E4D, + (q15_t)0x80C7, (q15_t)0x0E1B, (q15_t)0x80C2, (q15_t)0x0DE9, + (q15_t)0x80BC, (q15_t)0x0DB7, (q15_t)0x80B7, (q15_t)0x0D85, + (q15_t)0x80B2, (q15_t)0x0D53, (q15_t)0x80AC, (q15_t)0x0D21, + (q15_t)0x80A7, (q15_t)0x0CEF, (q15_t)0x80A2, (q15_t)0x0CBD, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8098, (q15_t)0x0C59, + (q15_t)0x8094, (q15_t)0x0C27, (q15_t)0x808F, (q15_t)0x0BF5, + (q15_t)0x808A, (q15_t)0x0BC3, (q15_t)0x8086, (q15_t)0x0B91, + (q15_t)0x8081, (q15_t)0x0B5F, (q15_t)0x807D, (q15_t)0x0B2D, + (q15_t)0x8078, (q15_t)0x0AFB, (q15_t)0x8074, (q15_t)0x0AC9, + (q15_t)0x8070, (q15_t)0x0A97, (q15_t)0x806C, (q15_t)0x0A65, + (q15_t)0x8068, (q15_t)0x0A33, (q15_t)0x8064, (q15_t)0x0A00, + (q15_t)0x8060, (q15_t)0x09CE, (q15_t)0x805C, (q15_t)0x099C, + (q15_t)0x8058, (q15_t)0x096A, (q15_t)0x8055, (q15_t)0x0938, + (q15_t)0x8051, (q15_t)0x0906, (q15_t)0x804E, (q15_t)0x08D4, + (q15_t)0x804A, (q15_t)0x08A2, (q15_t)0x8047, (q15_t)0x086F, + (q15_t)0x8043, (q15_t)0x083D, (q15_t)0x8040, (q15_t)0x080B, + (q15_t)0x803D, (q15_t)0x07D9, (q15_t)0x803A, (q15_t)0x07A7, + (q15_t)0x8037, (q15_t)0x0775, (q15_t)0x8034, (q15_t)0x0742, + (q15_t)0x8031, (q15_t)0x0710, (q15_t)0x802F, (q15_t)0x06DE, + (q15_t)0x802C, (q15_t)0x06AC, (q15_t)0x8029, (q15_t)0x067A, + (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8025, (q15_t)0x0615, + (q15_t)0x8022, (q15_t)0x05E3, (q15_t)0x8020, (q15_t)0x05B1, + (q15_t)0x801E, (q15_t)0x057F, (q15_t)0x801C, (q15_t)0x054C, + (q15_t)0x801A, (q15_t)0x051A, (q15_t)0x8018, (q15_t)0x04E8, + (q15_t)0x8016, (q15_t)0x04B6, (q15_t)0x8014, (q15_t)0x0483, + (q15_t)0x8012, (q15_t)0x0451, (q15_t)0x8011, (q15_t)0x041F, + (q15_t)0x800F, (q15_t)0x03ED, (q15_t)0x800D, (q15_t)0x03BA, + (q15_t)0x800C, (q15_t)0x0388, (q15_t)0x800B, (q15_t)0x0356, + (q15_t)0x8009, (q15_t)0x0324, (q15_t)0x8008, (q15_t)0x02F1, + (q15_t)0x8007, (q15_t)0x02BF, (q15_t)0x8006, (q15_t)0x028D, + (q15_t)0x8005, (q15_t)0x025B, (q15_t)0x8004, (q15_t)0x0228, + (q15_t)0x8003, (q15_t)0x01F6, (q15_t)0x8003, (q15_t)0x01C4, + (q15_t)0x8002, (q15_t)0x0192, (q15_t)0x8001, (q15_t)0x015F, + (q15_t)0x8001, (q15_t)0x012D, (q15_t)0x8000, (q15_t)0x00FB, + (q15_t)0x8000, (q15_t)0x00C9, (q15_t)0x8000, (q15_t)0x0096, + (q15_t)0x8000, (q15_t)0x0064, (q15_t)0x8000, (q15_t)0x0032, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8000, (q15_t)0xFFCD, + (q15_t)0x8000, (q15_t)0xFF9B, (q15_t)0x8000, (q15_t)0xFF69, + (q15_t)0x8000, (q15_t)0xFF36, (q15_t)0x8000, (q15_t)0xFF04, + (q15_t)0x8001, (q15_t)0xFED2, (q15_t)0x8001, (q15_t)0xFEA0, + (q15_t)0x8002, (q15_t)0xFE6D, (q15_t)0x8003, (q15_t)0xFE3B, + (q15_t)0x8003, (q15_t)0xFE09, (q15_t)0x8004, (q15_t)0xFDD7, + (q15_t)0x8005, (q15_t)0xFDA4, (q15_t)0x8006, (q15_t)0xFD72, + (q15_t)0x8007, (q15_t)0xFD40, (q15_t)0x8008, (q15_t)0xFD0E, + (q15_t)0x8009, (q15_t)0xFCDB, (q15_t)0x800B, (q15_t)0xFCA9, + (q15_t)0x800C, (q15_t)0xFC77, (q15_t)0x800D, (q15_t)0xFC45, + (q15_t)0x800F, (q15_t)0xFC12, (q15_t)0x8011, (q15_t)0xFBE0, + (q15_t)0x8012, (q15_t)0xFBAE, (q15_t)0x8014, (q15_t)0xFB7C, + (q15_t)0x8016, (q15_t)0xFB49, (q15_t)0x8018, (q15_t)0xFB17, + (q15_t)0x801A, (q15_t)0xFAE5, (q15_t)0x801C, (q15_t)0xFAB3, + (q15_t)0x801E, (q15_t)0xFA80, (q15_t)0x8020, (q15_t)0xFA4E, + (q15_t)0x8022, (q15_t)0xFA1C, (q15_t)0x8025, (q15_t)0xF9EA, + (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x8029, (q15_t)0xF985, + (q15_t)0x802C, (q15_t)0xF953, (q15_t)0x802F, (q15_t)0xF921, + (q15_t)0x8031, (q15_t)0xF8EF, (q15_t)0x8034, (q15_t)0xF8BD, + (q15_t)0x8037, (q15_t)0xF88A, (q15_t)0x803A, (q15_t)0xF858, + (q15_t)0x803D, (q15_t)0xF826, (q15_t)0x8040, (q15_t)0xF7F4, + (q15_t)0x8043, (q15_t)0xF7C2, (q15_t)0x8047, (q15_t)0xF790, + (q15_t)0x804A, (q15_t)0xF75D, (q15_t)0x804E, (q15_t)0xF72B, + (q15_t)0x8051, (q15_t)0xF6F9, (q15_t)0x8055, (q15_t)0xF6C7, + (q15_t)0x8058, (q15_t)0xF695, (q15_t)0x805C, (q15_t)0xF663, + (q15_t)0x8060, (q15_t)0xF631, (q15_t)0x8064, (q15_t)0xF5FF, + (q15_t)0x8068, (q15_t)0xF5CC, (q15_t)0x806C, (q15_t)0xF59A, + (q15_t)0x8070, (q15_t)0xF568, (q15_t)0x8074, (q15_t)0xF536, + (q15_t)0x8078, (q15_t)0xF504, (q15_t)0x807D, (q15_t)0xF4D2, + (q15_t)0x8081, (q15_t)0xF4A0, (q15_t)0x8086, (q15_t)0xF46E, + (q15_t)0x808A, (q15_t)0xF43C, (q15_t)0x808F, (q15_t)0xF40A, + (q15_t)0x8094, (q15_t)0xF3D8, (q15_t)0x8098, (q15_t)0xF3A6, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80A2, (q15_t)0xF342, + (q15_t)0x80A7, (q15_t)0xF310, (q15_t)0x80AC, (q15_t)0xF2DE, + (q15_t)0x80B2, (q15_t)0xF2AC, (q15_t)0x80B7, (q15_t)0xF27A, + (q15_t)0x80BC, (q15_t)0xF248, (q15_t)0x80C2, (q15_t)0xF216, + (q15_t)0x80C7, (q15_t)0xF1E4, (q15_t)0x80CD, (q15_t)0xF1B2, + (q15_t)0x80D2, (q15_t)0xF180, (q15_t)0x80D8, (q15_t)0xF14E, + (q15_t)0x80DE, (q15_t)0xF11C, (q15_t)0x80E4, (q15_t)0xF0EA, + (q15_t)0x80EA, (q15_t)0xF0B8, (q15_t)0x80F0, (q15_t)0xF086, + (q15_t)0x80F6, (q15_t)0xF054, (q15_t)0x80FC, (q15_t)0xF022, + (q15_t)0x8102, (q15_t)0xEFF1, (q15_t)0x8109, (q15_t)0xEFBF, + (q15_t)0x810F, (q15_t)0xEF8D, (q15_t)0x8116, (q15_t)0xEF5B, + (q15_t)0x811C, (q15_t)0xEF29, (q15_t)0x8123, (q15_t)0xEEF7, + (q15_t)0x812A, (q15_t)0xEEC6, (q15_t)0x8130, (q15_t)0xEE94, + (q15_t)0x8137, (q15_t)0xEE62, (q15_t)0x813E, (q15_t)0xEE30, + (q15_t)0x8145, (q15_t)0xEDFE, (q15_t)0x814C, (q15_t)0xEDCD, + (q15_t)0x8154, (q15_t)0xED9B, (q15_t)0x815B, (q15_t)0xED69, + (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x816A, (q15_t)0xED06, + (q15_t)0x8171, (q15_t)0xECD4, (q15_t)0x8179, (q15_t)0xECA2, + (q15_t)0x8180, (q15_t)0xEC71, (q15_t)0x8188, (q15_t)0xEC3F, + (q15_t)0x8190, (q15_t)0xEC0D, (q15_t)0x8198, (q15_t)0xEBDC, + (q15_t)0x81A0, (q15_t)0xEBAA, (q15_t)0x81A8, (q15_t)0xEB78, + (q15_t)0x81B0, (q15_t)0xEB47, (q15_t)0x81B8, (q15_t)0xEB15, + (q15_t)0x81C0, (q15_t)0xEAE4, (q15_t)0x81C8, (q15_t)0xEAB2, + (q15_t)0x81D1, (q15_t)0xEA80, (q15_t)0x81D9, (q15_t)0xEA4F, + (q15_t)0x81E2, (q15_t)0xEA1D, (q15_t)0x81EB, (q15_t)0xE9EC, + (q15_t)0x81F3, (q15_t)0xE9BA, (q15_t)0x81FC, (q15_t)0xE989, + (q15_t)0x8205, (q15_t)0xE957, (q15_t)0x820E, (q15_t)0xE926, + (q15_t)0x8217, (q15_t)0xE8F5, (q15_t)0x8220, (q15_t)0xE8C3, + (q15_t)0x8229, (q15_t)0xE892, (q15_t)0x8232, (q15_t)0xE860, + (q15_t)0x823C, (q15_t)0xE82F, (q15_t)0x8245, (q15_t)0xE7FD, + (q15_t)0x824F, (q15_t)0xE7CC, (q15_t)0x8258, (q15_t)0xE79B, + (q15_t)0x8262, (q15_t)0xE769, (q15_t)0x826B, (q15_t)0xE738, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x827F, (q15_t)0xE6D5, + (q15_t)0x8289, (q15_t)0xE6A4, (q15_t)0x8293, (q15_t)0xE673, + (q15_t)0x829D, (q15_t)0xE642, (q15_t)0x82A7, (q15_t)0xE610, + (q15_t)0x82B1, (q15_t)0xE5DF, (q15_t)0x82BC, (q15_t)0xE5AE, + (q15_t)0x82C6, (q15_t)0xE57D, (q15_t)0x82D0, (q15_t)0xE54C, + (q15_t)0x82DB, (q15_t)0xE51B, (q15_t)0x82E6, (q15_t)0xE4E9, + (q15_t)0x82F0, (q15_t)0xE4B8, (q15_t)0x82FB, (q15_t)0xE487, + (q15_t)0x8306, (q15_t)0xE456, (q15_t)0x8311, (q15_t)0xE425, + (q15_t)0x831C, (q15_t)0xE3F4, (q15_t)0x8327, (q15_t)0xE3C3, + (q15_t)0x8332, (q15_t)0xE392, (q15_t)0x833D, (q15_t)0xE361, + (q15_t)0x8348, (q15_t)0xE330, (q15_t)0x8354, (q15_t)0xE2FF, + (q15_t)0x835F, (q15_t)0xE2CE, (q15_t)0x836B, (q15_t)0xE29D, + (q15_t)0x8376, (q15_t)0xE26C, (q15_t)0x8382, (q15_t)0xE23B, + (q15_t)0x838E, (q15_t)0xE20A, (q15_t)0x8399, (q15_t)0xE1DA, + (q15_t)0x83A5, (q15_t)0xE1A9, (q15_t)0x83B1, (q15_t)0xE178, + (q15_t)0x83BD, (q15_t)0xE147, (q15_t)0x83C9, (q15_t)0xE116, + (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x83E2, (q15_t)0xE0B5, + (q15_t)0x83EE, (q15_t)0xE084, (q15_t)0x83FA, (q15_t)0xE053, + (q15_t)0x8407, (q15_t)0xE023, (q15_t)0x8414, (q15_t)0xDFF2, + (q15_t)0x8420, (q15_t)0xDFC1, (q15_t)0x842D, (q15_t)0xDF91, + (q15_t)0x843A, (q15_t)0xDF60, (q15_t)0x8446, (q15_t)0xDF2F, + (q15_t)0x8453, (q15_t)0xDEFF, (q15_t)0x8460, (q15_t)0xDECE, + (q15_t)0x846D, (q15_t)0xDE9E, (q15_t)0x847B, (q15_t)0xDE6D, + (q15_t)0x8488, (q15_t)0xDE3D, (q15_t)0x8495, (q15_t)0xDE0C, + (q15_t)0x84A2, (q15_t)0xDDDC, (q15_t)0x84B0, (q15_t)0xDDAB, + (q15_t)0x84BD, (q15_t)0xDD7B, (q15_t)0x84CB, (q15_t)0xDD4B, + (q15_t)0x84D9, (q15_t)0xDD1A, (q15_t)0x84E6, (q15_t)0xDCEA, + (q15_t)0x84F4, (q15_t)0xDCBA, (q15_t)0x8502, (q15_t)0xDC89, + (q15_t)0x8510, (q15_t)0xDC59, (q15_t)0x851E, (q15_t)0xDC29, + (q15_t)0x852C, (q15_t)0xDBF8, (q15_t)0x853A, (q15_t)0xDBC8, + (q15_t)0x8549, (q15_t)0xDB98, (q15_t)0x8557, (q15_t)0xDB68, + (q15_t)0x8565, (q15_t)0xDB38, (q15_t)0x8574, (q15_t)0xDB08, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x8591, (q15_t)0xDAA7, + (q15_t)0x85A0, (q15_t)0xDA77, (q15_t)0x85AF, (q15_t)0xDA47, + (q15_t)0x85BD, (q15_t)0xDA17, (q15_t)0x85CC, (q15_t)0xD9E7, + (q15_t)0x85DB, (q15_t)0xD9B7, (q15_t)0x85EA, (q15_t)0xD987, + (q15_t)0x85FA, (q15_t)0xD957, (q15_t)0x8609, (q15_t)0xD927, + (q15_t)0x8618, (q15_t)0xD8F8, (q15_t)0x8627, (q15_t)0xD8C8, + (q15_t)0x8637, (q15_t)0xD898, (q15_t)0x8646, (q15_t)0xD868, + (q15_t)0x8656, (q15_t)0xD838, (q15_t)0x8666, (q15_t)0xD809, + (q15_t)0x8675, (q15_t)0xD7D9, (q15_t)0x8685, (q15_t)0xD7A9, + (q15_t)0x8695, (q15_t)0xD779, (q15_t)0x86A5, (q15_t)0xD74A, + (q15_t)0x86B5, (q15_t)0xD71A, (q15_t)0x86C5, (q15_t)0xD6EA, + (q15_t)0x86D5, (q15_t)0xD6BB, (q15_t)0x86E6, (q15_t)0xD68B, + (q15_t)0x86F6, (q15_t)0xD65C, (q15_t)0x8706, (q15_t)0xD62C, + (q15_t)0x8717, (q15_t)0xD5FD, (q15_t)0x8727, (q15_t)0xD5CD, + (q15_t)0x8738, (q15_t)0xD59E, (q15_t)0x8749, (q15_t)0xD56E, + (q15_t)0x8759, (q15_t)0xD53F, (q15_t)0x876A, (q15_t)0xD510, + (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x878C, (q15_t)0xD4B1, + (q15_t)0x879D, (q15_t)0xD482, (q15_t)0x87AE, (q15_t)0xD452, + (q15_t)0x87BF, (q15_t)0xD423, (q15_t)0x87D1, (q15_t)0xD3F4, + (q15_t)0x87E2, (q15_t)0xD3C5, (q15_t)0x87F3, (q15_t)0xD396, + (q15_t)0x8805, (q15_t)0xD367, (q15_t)0x8816, (q15_t)0xD337, + (q15_t)0x8828, (q15_t)0xD308, (q15_t)0x883A, (q15_t)0xD2D9, + (q15_t)0x884B, (q15_t)0xD2AA, (q15_t)0x885D, (q15_t)0xD27B, + (q15_t)0x886F, (q15_t)0xD24C, (q15_t)0x8881, (q15_t)0xD21D, + (q15_t)0x8893, (q15_t)0xD1EE, (q15_t)0x88A5, (q15_t)0xD1C0, + (q15_t)0x88B8, (q15_t)0xD191, (q15_t)0x88CA, (q15_t)0xD162, + (q15_t)0x88DC, (q15_t)0xD133, (q15_t)0x88EF, (q15_t)0xD104, + (q15_t)0x8901, (q15_t)0xD0D6, (q15_t)0x8914, (q15_t)0xD0A7, + (q15_t)0x8926, (q15_t)0xD078, (q15_t)0x8939, (q15_t)0xD04A, + (q15_t)0x894C, (q15_t)0xD01B, (q15_t)0x895F, (q15_t)0xCFEC, + (q15_t)0x8971, (q15_t)0xCFBE, (q15_t)0x8984, (q15_t)0xCF8F, + (q15_t)0x8997, (q15_t)0xCF61, (q15_t)0x89AB, (q15_t)0xCF32, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x89D1, (q15_t)0xCED5, + (q15_t)0x89E4, (q15_t)0xCEA7, (q15_t)0x89F8, (q15_t)0xCE79, + (q15_t)0x8A0B, (q15_t)0xCE4A, (q15_t)0x8A1F, (q15_t)0xCE1C, + (q15_t)0x8A33, (q15_t)0xCDEE, (q15_t)0x8A46, (q15_t)0xCDBF, + (q15_t)0x8A5A, (q15_t)0xCD91, (q15_t)0x8A6E, (q15_t)0xCD63, + (q15_t)0x8A82, (q15_t)0xCD35, (q15_t)0x8A96, (q15_t)0xCD07, + (q15_t)0x8AAA, (q15_t)0xCCD9, (q15_t)0x8ABE, (q15_t)0xCCAB, + (q15_t)0x8AD2, (q15_t)0xCC7D, (q15_t)0x8AE6, (q15_t)0xCC4F, + (q15_t)0x8AFB, (q15_t)0xCC21, (q15_t)0x8B0F, (q15_t)0xCBF3, + (q15_t)0x8B24, (q15_t)0xCBC5, (q15_t)0x8B38, (q15_t)0xCB97, + (q15_t)0x8B4D, (q15_t)0xCB69, (q15_t)0x8B61, (q15_t)0xCB3B, + (q15_t)0x8B76, (q15_t)0xCB0D, (q15_t)0x8B8B, (q15_t)0xCAE0, + (q15_t)0x8BA0, (q15_t)0xCAB2, (q15_t)0x8BB5, (q15_t)0xCA84, + (q15_t)0x8BCA, (q15_t)0xCA57, (q15_t)0x8BDF, (q15_t)0xCA29, + (q15_t)0x8BF4, (q15_t)0xC9FB, (q15_t)0x8C09, (q15_t)0xC9CE, + (q15_t)0x8C1F, (q15_t)0xC9A0, (q15_t)0x8C34, (q15_t)0xC973, + (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8C5F, (q15_t)0xC918, + (q15_t)0x8C75, (q15_t)0xC8EB, (q15_t)0x8C8A, (q15_t)0xC8BD, + (q15_t)0x8CA0, (q15_t)0xC890, (q15_t)0x8CB6, (q15_t)0xC863, + (q15_t)0x8CCC, (q15_t)0xC835, (q15_t)0x8CE2, (q15_t)0xC808, + (q15_t)0x8CF8, (q15_t)0xC7DB, (q15_t)0x8D0E, (q15_t)0xC7AE, + (q15_t)0x8D24, (q15_t)0xC781, (q15_t)0x8D3A, (q15_t)0xC754, + (q15_t)0x8D50, (q15_t)0xC727, (q15_t)0x8D67, (q15_t)0xC6F9, + (q15_t)0x8D7D, (q15_t)0xC6CD, (q15_t)0x8D94, (q15_t)0xC6A0, + (q15_t)0x8DAA, (q15_t)0xC673, (q15_t)0x8DC1, (q15_t)0xC646, + (q15_t)0x8DD8, (q15_t)0xC619, (q15_t)0x8DEE, (q15_t)0xC5EC, + (q15_t)0x8E05, (q15_t)0xC5BF, (q15_t)0x8E1C, (q15_t)0xC593, + (q15_t)0x8E33, (q15_t)0xC566, (q15_t)0x8E4A, (q15_t)0xC539, + (q15_t)0x8E61, (q15_t)0xC50D, (q15_t)0x8E79, (q15_t)0xC4E0, + (q15_t)0x8E90, (q15_t)0xC4B3, (q15_t)0x8EA7, (q15_t)0xC487, + (q15_t)0x8EBE, (q15_t)0xC45A, (q15_t)0x8ED6, (q15_t)0xC42E, + (q15_t)0x8EED, (q15_t)0xC402, (q15_t)0x8F05, (q15_t)0xC3D5, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x8F34, (q15_t)0xC37C, + (q15_t)0x8F4C, (q15_t)0xC350, (q15_t)0x8F64, (q15_t)0xC324, + (q15_t)0x8F7C, (q15_t)0xC2F8, (q15_t)0x8F94, (q15_t)0xC2CC, + (q15_t)0x8FAC, (q15_t)0xC29F, (q15_t)0x8FC4, (q15_t)0xC273, + (q15_t)0x8FDC, (q15_t)0xC247, (q15_t)0x8FF5, (q15_t)0xC21B, + (q15_t)0x900D, (q15_t)0xC1EF, (q15_t)0x9025, (q15_t)0xC1C3, + (q15_t)0x903E, (q15_t)0xC197, (q15_t)0x9056, (q15_t)0xC16C, + (q15_t)0x906F, (q15_t)0xC140, (q15_t)0x9088, (q15_t)0xC114, + (q15_t)0x90A0, (q15_t)0xC0E8, (q15_t)0x90B9, (q15_t)0xC0BC, + (q15_t)0x90D2, (q15_t)0xC091, (q15_t)0x90EB, (q15_t)0xC065, + (q15_t)0x9104, (q15_t)0xC03A, (q15_t)0x911D, (q15_t)0xC00E, + (q15_t)0x9136, (q15_t)0xBFE2, (q15_t)0x9150, (q15_t)0xBFB7, + (q15_t)0x9169, (q15_t)0xBF8C, (q15_t)0x9182, (q15_t)0xBF60, + (q15_t)0x919C, (q15_t)0xBF35, (q15_t)0x91B5, (q15_t)0xBF09, + (q15_t)0x91CF, (q15_t)0xBEDE, (q15_t)0x91E8, (q15_t)0xBEB3, + (q15_t)0x9202, (q15_t)0xBE88, (q15_t)0x921C, (q15_t)0xBE5D, + (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x924F, (q15_t)0xBE06, + (q15_t)0x9269, (q15_t)0xBDDB, (q15_t)0x9283, (q15_t)0xBDB0, + (q15_t)0x929D, (q15_t)0xBD85, (q15_t)0x92B7, (q15_t)0xBD5A, + (q15_t)0x92D2, (q15_t)0xBD2F, (q15_t)0x92EC, (q15_t)0xBD05, + (q15_t)0x9306, (q15_t)0xBCDA, (q15_t)0x9321, (q15_t)0xBCAF, + (q15_t)0x933B, (q15_t)0xBC84, (q15_t)0x9356, (q15_t)0xBC5A, + (q15_t)0x9370, (q15_t)0xBC2F, (q15_t)0x938B, (q15_t)0xBC04, + (q15_t)0x93A6, (q15_t)0xBBDA, (q15_t)0x93C0, (q15_t)0xBBAF, + (q15_t)0x93DB, (q15_t)0xBB85, (q15_t)0x93F6, (q15_t)0xBB5A, + (q15_t)0x9411, (q15_t)0xBB30, (q15_t)0x942C, (q15_t)0xBB05, + (q15_t)0x9447, (q15_t)0xBADB, (q15_t)0x9463, (q15_t)0xBAB1, + (q15_t)0x947E, (q15_t)0xBA87, (q15_t)0x9499, (q15_t)0xBA5C, + (q15_t)0x94B5, (q15_t)0xBA32, (q15_t)0x94D0, (q15_t)0xBA08, + (q15_t)0x94EC, (q15_t)0xB9DE, (q15_t)0x9507, (q15_t)0xB9B4, + (q15_t)0x9523, (q15_t)0xB98A, (q15_t)0x953E, (q15_t)0xB960, + (q15_t)0x955A, (q15_t)0xB936, (q15_t)0x9576, (q15_t)0xB90C, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x95AE, (q15_t)0xB8B9, + (q15_t)0x95CA, (q15_t)0xB88F, (q15_t)0x95E6, (q15_t)0xB865, + (q15_t)0x9602, (q15_t)0xB83C, (q15_t)0x961E, (q15_t)0xB812, + (q15_t)0x963B, (q15_t)0xB7E9, (q15_t)0x9657, (q15_t)0xB7BF, + (q15_t)0x9673, (q15_t)0xB796, (q15_t)0x9690, (q15_t)0xB76C, + (q15_t)0x96AC, (q15_t)0xB743, (q15_t)0x96C9, (q15_t)0xB719, + (q15_t)0x96E6, (q15_t)0xB6F0, (q15_t)0x9702, (q15_t)0xB6C7, + (q15_t)0x971F, (q15_t)0xB69E, (q15_t)0x973C, (q15_t)0xB675, + (q15_t)0x9759, (q15_t)0xB64B, (q15_t)0x9776, (q15_t)0xB622, + (q15_t)0x9793, (q15_t)0xB5F9, (q15_t)0x97B0, (q15_t)0xB5D0, + (q15_t)0x97CD, (q15_t)0xB5A7, (q15_t)0x97EA, (q15_t)0xB57E, + (q15_t)0x9808, (q15_t)0xB556, (q15_t)0x9825, (q15_t)0xB52D, + (q15_t)0x9842, (q15_t)0xB504, (q15_t)0x9860, (q15_t)0xB4DB, + (q15_t)0x987D, (q15_t)0xB4B3, (q15_t)0x989B, (q15_t)0xB48A, + (q15_t)0x98B9, (q15_t)0xB461, (q15_t)0x98D6, (q15_t)0xB439, + (q15_t)0x98F4, (q15_t)0xB410, (q15_t)0x9912, (q15_t)0xB3E8, + (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x994E, (q15_t)0xB397, + (q15_t)0x996C, (q15_t)0xB36F, (q15_t)0x998A, (q15_t)0xB347, + (q15_t)0x99A8, (q15_t)0xB31E, (q15_t)0x99C6, (q15_t)0xB2F6, + (q15_t)0x99E5, (q15_t)0xB2CE, (q15_t)0x9A03, (q15_t)0xB2A6, + (q15_t)0x9A22, (q15_t)0xB27E, (q15_t)0x9A40, (q15_t)0xB256, + (q15_t)0x9A5F, (q15_t)0xB22E, (q15_t)0x9A7D, (q15_t)0xB206, + (q15_t)0x9A9C, (q15_t)0xB1DE, (q15_t)0x9ABA, (q15_t)0xB1B7, + (q15_t)0x9AD9, (q15_t)0xB18F, (q15_t)0x9AF8, (q15_t)0xB167, + (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9B36, (q15_t)0xB118, + (q15_t)0x9B55, (q15_t)0xB0F0, (q15_t)0x9B74, (q15_t)0xB0C9, + (q15_t)0x9B93, (q15_t)0xB0A1, (q15_t)0x9BB2, (q15_t)0xB07A, + (q15_t)0x9BD2, (q15_t)0xB053, (q15_t)0x9BF1, (q15_t)0xB02B, + (q15_t)0x9C10, (q15_t)0xB004, (q15_t)0x9C30, (q15_t)0xAFDD, + (q15_t)0x9C4F, (q15_t)0xAFB6, (q15_t)0x9C6F, (q15_t)0xAF8F, + (q15_t)0x9C8E, (q15_t)0xAF68, (q15_t)0x9CAE, (q15_t)0xAF40, + (q15_t)0x9CCE, (q15_t)0xAF1A, (q15_t)0x9CEE, (q15_t)0xAEF3, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9D2D, (q15_t)0xAEA5, + (q15_t)0x9D4D, (q15_t)0xAE7E, (q15_t)0x9D6D, (q15_t)0xAE57, + (q15_t)0x9D8E, (q15_t)0xAE31, (q15_t)0x9DAE, (q15_t)0xAE0A, + (q15_t)0x9DCE, (q15_t)0xADE3, (q15_t)0x9DEE, (q15_t)0xADBD, + (q15_t)0x9E0E, (q15_t)0xAD96, (q15_t)0x9E2F, (q15_t)0xAD70, + (q15_t)0x9E4F, (q15_t)0xAD4A, (q15_t)0x9E70, (q15_t)0xAD23, + (q15_t)0x9E90, (q15_t)0xACFD, (q15_t)0x9EB1, (q15_t)0xACD7, + (q15_t)0x9ED2, (q15_t)0xACB1, (q15_t)0x9EF2, (q15_t)0xAC8A, + (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0x9F34, (q15_t)0xAC3E, + (q15_t)0x9F55, (q15_t)0xAC18, (q15_t)0x9F76, (q15_t)0xABF2, + (q15_t)0x9F97, (q15_t)0xABCC, (q15_t)0x9FB8, (q15_t)0xABA7, + (q15_t)0x9FD9, (q15_t)0xAB81, (q15_t)0x9FFB, (q15_t)0xAB5B, + (q15_t)0xA01C, (q15_t)0xAB35, (q15_t)0xA03D, (q15_t)0xAB10, + (q15_t)0xA05F, (q15_t)0xAAEA, (q15_t)0xA080, (q15_t)0xAAC5, + (q15_t)0xA0A1, (q15_t)0xAA9F, (q15_t)0xA0C3, (q15_t)0xAA7A, + (q15_t)0xA0E5, (q15_t)0xAA54, (q15_t)0xA106, (q15_t)0xAA2F, + (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA14A, (q15_t)0xA9E5, + (q15_t)0xA16C, (q15_t)0xA9BF, (q15_t)0xA18E, (q15_t)0xA99A, + (q15_t)0xA1AF, (q15_t)0xA975, (q15_t)0xA1D2, (q15_t)0xA950, + (q15_t)0xA1F4, (q15_t)0xA92B, (q15_t)0xA216, (q15_t)0xA906, + (q15_t)0xA238, (q15_t)0xA8E2, (q15_t)0xA25A, (q15_t)0xA8BD, + (q15_t)0xA27C, (q15_t)0xA898, (q15_t)0xA29F, (q15_t)0xA873, + (q15_t)0xA2C1, (q15_t)0xA84F, (q15_t)0xA2E4, (q15_t)0xA82A, + (q15_t)0xA306, (q15_t)0xA806, (q15_t)0xA329, (q15_t)0xA7E1, + (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA36E, (q15_t)0xA798, + (q15_t)0xA391, (q15_t)0xA774, (q15_t)0xA3B4, (q15_t)0xA750, + (q15_t)0xA3D6, (q15_t)0xA72B, (q15_t)0xA3F9, (q15_t)0xA707, + (q15_t)0xA41C, (q15_t)0xA6E3, (q15_t)0xA43F, (q15_t)0xA6BF, + (q15_t)0xA462, (q15_t)0xA69B, (q15_t)0xA486, (q15_t)0xA677, + (q15_t)0xA4A9, (q15_t)0xA653, (q15_t)0xA4CC, (q15_t)0xA62F, + (q15_t)0xA4EF, (q15_t)0xA60C, (q15_t)0xA513, (q15_t)0xA5E8, + (q15_t)0xA536, (q15_t)0xA5C4, (q15_t)0xA55A, (q15_t)0xA5A1, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA5A1, (q15_t)0xA55A, + (q15_t)0xA5C4, (q15_t)0xA536, (q15_t)0xA5E8, (q15_t)0xA513, + (q15_t)0xA60C, (q15_t)0xA4EF, (q15_t)0xA62F, (q15_t)0xA4CC, + (q15_t)0xA653, (q15_t)0xA4A9, (q15_t)0xA677, (q15_t)0xA486, + (q15_t)0xA69B, (q15_t)0xA462, (q15_t)0xA6BF, (q15_t)0xA43F, + (q15_t)0xA6E3, (q15_t)0xA41C, (q15_t)0xA707, (q15_t)0xA3F9, + (q15_t)0xA72B, (q15_t)0xA3D6, (q15_t)0xA750, (q15_t)0xA3B4, + (q15_t)0xA774, (q15_t)0xA391, (q15_t)0xA798, (q15_t)0xA36E, + (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA7E1, (q15_t)0xA329, + (q15_t)0xA806, (q15_t)0xA306, (q15_t)0xA82A, (q15_t)0xA2E4, + (q15_t)0xA84F, (q15_t)0xA2C1, (q15_t)0xA873, (q15_t)0xA29F, + (q15_t)0xA898, (q15_t)0xA27C, (q15_t)0xA8BD, (q15_t)0xA25A, + (q15_t)0xA8E2, (q15_t)0xA238, (q15_t)0xA906, (q15_t)0xA216, + (q15_t)0xA92B, (q15_t)0xA1F4, (q15_t)0xA950, (q15_t)0xA1D2, + (q15_t)0xA975, (q15_t)0xA1AF, (q15_t)0xA99A, (q15_t)0xA18E, + (q15_t)0xA9BF, (q15_t)0xA16C, (q15_t)0xA9E5, (q15_t)0xA14A, + (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAA2F, (q15_t)0xA106, + (q15_t)0xAA54, (q15_t)0xA0E5, (q15_t)0xAA7A, (q15_t)0xA0C3, + (q15_t)0xAA9F, (q15_t)0xA0A1, (q15_t)0xAAC5, (q15_t)0xA080, + (q15_t)0xAAEA, (q15_t)0xA05F, (q15_t)0xAB10, (q15_t)0xA03D, + (q15_t)0xAB35, (q15_t)0xA01C, (q15_t)0xAB5B, (q15_t)0x9FFB, + (q15_t)0xAB81, (q15_t)0x9FD9, (q15_t)0xABA7, (q15_t)0x9FB8, + (q15_t)0xABCC, (q15_t)0x9F97, (q15_t)0xABF2, (q15_t)0x9F76, + (q15_t)0xAC18, (q15_t)0x9F55, (q15_t)0xAC3E, (q15_t)0x9F34, + (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xAC8A, (q15_t)0x9EF2, + (q15_t)0xACB1, (q15_t)0x9ED2, (q15_t)0xACD7, (q15_t)0x9EB1, + (q15_t)0xACFD, (q15_t)0x9E90, (q15_t)0xAD23, (q15_t)0x9E70, + (q15_t)0xAD4A, (q15_t)0x9E4F, (q15_t)0xAD70, (q15_t)0x9E2F, + (q15_t)0xAD96, (q15_t)0x9E0E, (q15_t)0xADBD, (q15_t)0x9DEE, + (q15_t)0xADE3, (q15_t)0x9DCE, (q15_t)0xAE0A, (q15_t)0x9DAE, + (q15_t)0xAE31, (q15_t)0x9D8E, (q15_t)0xAE57, (q15_t)0x9D6D, + (q15_t)0xAE7E, (q15_t)0x9D4D, (q15_t)0xAEA5, (q15_t)0x9D2D, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xAEF3, (q15_t)0x9CEE, + (q15_t)0xAF1A, (q15_t)0x9CCE, (q15_t)0xAF40, (q15_t)0x9CAE, + (q15_t)0xAF68, (q15_t)0x9C8E, (q15_t)0xAF8F, (q15_t)0x9C6F, + (q15_t)0xAFB6, (q15_t)0x9C4F, (q15_t)0xAFDD, (q15_t)0x9C30, + (q15_t)0xB004, (q15_t)0x9C10, (q15_t)0xB02B, (q15_t)0x9BF1, + (q15_t)0xB053, (q15_t)0x9BD2, (q15_t)0xB07A, (q15_t)0x9BB2, + (q15_t)0xB0A1, (q15_t)0x9B93, (q15_t)0xB0C9, (q15_t)0x9B74, + (q15_t)0xB0F0, (q15_t)0x9B55, (q15_t)0xB118, (q15_t)0x9B36, + (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB167, (q15_t)0x9AF8, + (q15_t)0xB18F, (q15_t)0x9AD9, (q15_t)0xB1B7, (q15_t)0x9ABA, + (q15_t)0xB1DE, (q15_t)0x9A9C, (q15_t)0xB206, (q15_t)0x9A7D, + (q15_t)0xB22E, (q15_t)0x9A5F, (q15_t)0xB256, (q15_t)0x9A40, + (q15_t)0xB27E, (q15_t)0x9A22, (q15_t)0xB2A6, (q15_t)0x9A03, + (q15_t)0xB2CE, (q15_t)0x99E5, (q15_t)0xB2F6, (q15_t)0x99C6, + (q15_t)0xB31E, (q15_t)0x99A8, (q15_t)0xB347, (q15_t)0x998A, + (q15_t)0xB36F, (q15_t)0x996C, (q15_t)0xB397, (q15_t)0x994E, + (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB3E8, (q15_t)0x9912, + (q15_t)0xB410, (q15_t)0x98F4, (q15_t)0xB439, (q15_t)0x98D6, + (q15_t)0xB461, (q15_t)0x98B9, (q15_t)0xB48A, (q15_t)0x989B, + (q15_t)0xB4B3, (q15_t)0x987D, (q15_t)0xB4DB, (q15_t)0x9860, + (q15_t)0xB504, (q15_t)0x9842, (q15_t)0xB52D, (q15_t)0x9825, + (q15_t)0xB556, (q15_t)0x9808, (q15_t)0xB57E, (q15_t)0x97EA, + (q15_t)0xB5A7, (q15_t)0x97CD, (q15_t)0xB5D0, (q15_t)0x97B0, + (q15_t)0xB5F9, (q15_t)0x9793, (q15_t)0xB622, (q15_t)0x9776, + (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB675, (q15_t)0x973C, + (q15_t)0xB69E, (q15_t)0x971F, (q15_t)0xB6C7, (q15_t)0x9702, + (q15_t)0xB6F0, (q15_t)0x96E6, (q15_t)0xB719, (q15_t)0x96C9, + (q15_t)0xB743, (q15_t)0x96AC, (q15_t)0xB76C, (q15_t)0x9690, + (q15_t)0xB796, (q15_t)0x9673, (q15_t)0xB7BF, (q15_t)0x9657, + (q15_t)0xB7E9, (q15_t)0x963B, (q15_t)0xB812, (q15_t)0x961E, + (q15_t)0xB83C, (q15_t)0x9602, (q15_t)0xB865, (q15_t)0x95E6, + (q15_t)0xB88F, (q15_t)0x95CA, (q15_t)0xB8B9, (q15_t)0x95AE, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xB90C, (q15_t)0x9576, + (q15_t)0xB936, (q15_t)0x955A, (q15_t)0xB960, (q15_t)0x953E, + (q15_t)0xB98A, (q15_t)0x9523, (q15_t)0xB9B4, (q15_t)0x9507, + (q15_t)0xB9DE, (q15_t)0x94EC, (q15_t)0xBA08, (q15_t)0x94D0, + (q15_t)0xBA32, (q15_t)0x94B5, (q15_t)0xBA5C, (q15_t)0x9499, + (q15_t)0xBA87, (q15_t)0x947E, (q15_t)0xBAB1, (q15_t)0x9463, + (q15_t)0xBADB, (q15_t)0x9447, (q15_t)0xBB05, (q15_t)0x942C, + (q15_t)0xBB30, (q15_t)0x9411, (q15_t)0xBB5A, (q15_t)0x93F6, + (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBBAF, (q15_t)0x93C0, + (q15_t)0xBBDA, (q15_t)0x93A6, (q15_t)0xBC04, (q15_t)0x938B, + (q15_t)0xBC2F, (q15_t)0x9370, (q15_t)0xBC5A, (q15_t)0x9356, + (q15_t)0xBC84, (q15_t)0x933B, (q15_t)0xBCAF, (q15_t)0x9321, + (q15_t)0xBCDA, (q15_t)0x9306, (q15_t)0xBD05, (q15_t)0x92EC, + (q15_t)0xBD2F, (q15_t)0x92D2, (q15_t)0xBD5A, (q15_t)0x92B7, + (q15_t)0xBD85, (q15_t)0x929D, (q15_t)0xBDB0, (q15_t)0x9283, + (q15_t)0xBDDB, (q15_t)0x9269, (q15_t)0xBE06, (q15_t)0x924F, + (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBE5D, (q15_t)0x921C, + (q15_t)0xBE88, (q15_t)0x9202, (q15_t)0xBEB3, (q15_t)0x91E8, + (q15_t)0xBEDE, (q15_t)0x91CF, (q15_t)0xBF09, (q15_t)0x91B5, + (q15_t)0xBF35, (q15_t)0x919C, (q15_t)0xBF60, (q15_t)0x9182, + (q15_t)0xBF8C, (q15_t)0x9169, (q15_t)0xBFB7, (q15_t)0x9150, + (q15_t)0xBFE2, (q15_t)0x9136, (q15_t)0xC00E, (q15_t)0x911D, + (q15_t)0xC03A, (q15_t)0x9104, (q15_t)0xC065, (q15_t)0x90EB, + (q15_t)0xC091, (q15_t)0x90D2, (q15_t)0xC0BC, (q15_t)0x90B9, + (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC114, (q15_t)0x9088, + (q15_t)0xC140, (q15_t)0x906F, (q15_t)0xC16C, (q15_t)0x9056, + (q15_t)0xC197, (q15_t)0x903E, (q15_t)0xC1C3, (q15_t)0x9025, + (q15_t)0xC1EF, (q15_t)0x900D, (q15_t)0xC21B, (q15_t)0x8FF5, + (q15_t)0xC247, (q15_t)0x8FDC, (q15_t)0xC273, (q15_t)0x8FC4, + (q15_t)0xC29F, (q15_t)0x8FAC, (q15_t)0xC2CC, (q15_t)0x8F94, + (q15_t)0xC2F8, (q15_t)0x8F7C, (q15_t)0xC324, (q15_t)0x8F64, + (q15_t)0xC350, (q15_t)0x8F4C, (q15_t)0xC37C, (q15_t)0x8F34, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC3D5, (q15_t)0x8F05, + (q15_t)0xC402, (q15_t)0x8EED, (q15_t)0xC42E, (q15_t)0x8ED6, + (q15_t)0xC45A, (q15_t)0x8EBE, (q15_t)0xC487, (q15_t)0x8EA7, + (q15_t)0xC4B3, (q15_t)0x8E90, (q15_t)0xC4E0, (q15_t)0x8E79, + (q15_t)0xC50D, (q15_t)0x8E61, (q15_t)0xC539, (q15_t)0x8E4A, + (q15_t)0xC566, (q15_t)0x8E33, (q15_t)0xC593, (q15_t)0x8E1C, + (q15_t)0xC5BF, (q15_t)0x8E05, (q15_t)0xC5EC, (q15_t)0x8DEE, + (q15_t)0xC619, (q15_t)0x8DD8, (q15_t)0xC646, (q15_t)0x8DC1, + (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC6A0, (q15_t)0x8D94, + (q15_t)0xC6CD, (q15_t)0x8D7D, (q15_t)0xC6F9, (q15_t)0x8D67, + (q15_t)0xC727, (q15_t)0x8D50, (q15_t)0xC754, (q15_t)0x8D3A, + (q15_t)0xC781, (q15_t)0x8D24, (q15_t)0xC7AE, (q15_t)0x8D0E, + (q15_t)0xC7DB, (q15_t)0x8CF8, (q15_t)0xC808, (q15_t)0x8CE2, + (q15_t)0xC835, (q15_t)0x8CCC, (q15_t)0xC863, (q15_t)0x8CB6, + (q15_t)0xC890, (q15_t)0x8CA0, (q15_t)0xC8BD, (q15_t)0x8C8A, + (q15_t)0xC8EB, (q15_t)0x8C75, (q15_t)0xC918, (q15_t)0x8C5F, + (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xC973, (q15_t)0x8C34, + (q15_t)0xC9A0, (q15_t)0x8C1F, (q15_t)0xC9CE, (q15_t)0x8C09, + (q15_t)0xC9FB, (q15_t)0x8BF4, (q15_t)0xCA29, (q15_t)0x8BDF, + (q15_t)0xCA57, (q15_t)0x8BCA, (q15_t)0xCA84, (q15_t)0x8BB5, + (q15_t)0xCAB2, (q15_t)0x8BA0, (q15_t)0xCAE0, (q15_t)0x8B8B, + (q15_t)0xCB0D, (q15_t)0x8B76, (q15_t)0xCB3B, (q15_t)0x8B61, + (q15_t)0xCB69, (q15_t)0x8B4D, (q15_t)0xCB97, (q15_t)0x8B38, + (q15_t)0xCBC5, (q15_t)0x8B24, (q15_t)0xCBF3, (q15_t)0x8B0F, + (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCC4F, (q15_t)0x8AE6, + (q15_t)0xCC7D, (q15_t)0x8AD2, (q15_t)0xCCAB, (q15_t)0x8ABE, + (q15_t)0xCCD9, (q15_t)0x8AAA, (q15_t)0xCD07, (q15_t)0x8A96, + (q15_t)0xCD35, (q15_t)0x8A82, (q15_t)0xCD63, (q15_t)0x8A6E, + (q15_t)0xCD91, (q15_t)0x8A5A, (q15_t)0xCDBF, (q15_t)0x8A46, + (q15_t)0xCDEE, (q15_t)0x8A33, (q15_t)0xCE1C, (q15_t)0x8A1F, + (q15_t)0xCE4A, (q15_t)0x8A0B, (q15_t)0xCE79, (q15_t)0x89F8, + (q15_t)0xCEA7, (q15_t)0x89E4, (q15_t)0xCED5, (q15_t)0x89D1, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xCF32, (q15_t)0x89AB, + (q15_t)0xCF61, (q15_t)0x8997, (q15_t)0xCF8F, (q15_t)0x8984, + (q15_t)0xCFBE, (q15_t)0x8971, (q15_t)0xCFEC, (q15_t)0x895F, + (q15_t)0xD01B, (q15_t)0x894C, (q15_t)0xD04A, (q15_t)0x8939, + (q15_t)0xD078, (q15_t)0x8926, (q15_t)0xD0A7, (q15_t)0x8914, + (q15_t)0xD0D6, (q15_t)0x8901, (q15_t)0xD104, (q15_t)0x88EF, + (q15_t)0xD133, (q15_t)0x88DC, (q15_t)0xD162, (q15_t)0x88CA, + (q15_t)0xD191, (q15_t)0x88B8, (q15_t)0xD1C0, (q15_t)0x88A5, + (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD21D, (q15_t)0x8881, + (q15_t)0xD24C, (q15_t)0x886F, (q15_t)0xD27B, (q15_t)0x885D, + (q15_t)0xD2AA, (q15_t)0x884B, (q15_t)0xD2D9, (q15_t)0x883A, + (q15_t)0xD308, (q15_t)0x8828, (q15_t)0xD337, (q15_t)0x8816, + (q15_t)0xD367, (q15_t)0x8805, (q15_t)0xD396, (q15_t)0x87F3, + (q15_t)0xD3C5, (q15_t)0x87E2, (q15_t)0xD3F4, (q15_t)0x87D1, + (q15_t)0xD423, (q15_t)0x87BF, (q15_t)0xD452, (q15_t)0x87AE, + (q15_t)0xD482, (q15_t)0x879D, (q15_t)0xD4B1, (q15_t)0x878C, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD510, (q15_t)0x876A, + (q15_t)0xD53F, (q15_t)0x8759, (q15_t)0xD56E, (q15_t)0x8749, + (q15_t)0xD59E, (q15_t)0x8738, (q15_t)0xD5CD, (q15_t)0x8727, + (q15_t)0xD5FD, (q15_t)0x8717, (q15_t)0xD62C, (q15_t)0x8706, + (q15_t)0xD65C, (q15_t)0x86F6, (q15_t)0xD68B, (q15_t)0x86E6, + (q15_t)0xD6BB, (q15_t)0x86D5, (q15_t)0xD6EA, (q15_t)0x86C5, + (q15_t)0xD71A, (q15_t)0x86B5, (q15_t)0xD74A, (q15_t)0x86A5, + (q15_t)0xD779, (q15_t)0x8695, (q15_t)0xD7A9, (q15_t)0x8685, + (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD809, (q15_t)0x8666, + (q15_t)0xD838, (q15_t)0x8656, (q15_t)0xD868, (q15_t)0x8646, + (q15_t)0xD898, (q15_t)0x8637, (q15_t)0xD8C8, (q15_t)0x8627, + (q15_t)0xD8F8, (q15_t)0x8618, (q15_t)0xD927, (q15_t)0x8609, + (q15_t)0xD957, (q15_t)0x85FA, (q15_t)0xD987, (q15_t)0x85EA, + (q15_t)0xD9B7, (q15_t)0x85DB, (q15_t)0xD9E7, (q15_t)0x85CC, + (q15_t)0xDA17, (q15_t)0x85BD, (q15_t)0xDA47, (q15_t)0x85AF, + (q15_t)0xDA77, (q15_t)0x85A0, (q15_t)0xDAA7, (q15_t)0x8591, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDB08, (q15_t)0x8574, + (q15_t)0xDB38, (q15_t)0x8565, (q15_t)0xDB68, (q15_t)0x8557, + (q15_t)0xDB98, (q15_t)0x8549, (q15_t)0xDBC8, (q15_t)0x853A, + (q15_t)0xDBF8, (q15_t)0x852C, (q15_t)0xDC29, (q15_t)0x851E, + (q15_t)0xDC59, (q15_t)0x8510, (q15_t)0xDC89, (q15_t)0x8502, + (q15_t)0xDCBA, (q15_t)0x84F4, (q15_t)0xDCEA, (q15_t)0x84E6, + (q15_t)0xDD1A, (q15_t)0x84D9, (q15_t)0xDD4B, (q15_t)0x84CB, + (q15_t)0xDD7B, (q15_t)0x84BD, (q15_t)0xDDAB, (q15_t)0x84B0, + (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDE0C, (q15_t)0x8495, + (q15_t)0xDE3D, (q15_t)0x8488, (q15_t)0xDE6D, (q15_t)0x847B, + (q15_t)0xDE9E, (q15_t)0x846D, (q15_t)0xDECE, (q15_t)0x8460, + (q15_t)0xDEFF, (q15_t)0x8453, (q15_t)0xDF2F, (q15_t)0x8446, + (q15_t)0xDF60, (q15_t)0x843A, (q15_t)0xDF91, (q15_t)0x842D, + (q15_t)0xDFC1, (q15_t)0x8420, (q15_t)0xDFF2, (q15_t)0x8414, + (q15_t)0xE023, (q15_t)0x8407, (q15_t)0xE053, (q15_t)0x83FA, + (q15_t)0xE084, (q15_t)0x83EE, (q15_t)0xE0B5, (q15_t)0x83E2, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE116, (q15_t)0x83C9, + (q15_t)0xE147, (q15_t)0x83BD, (q15_t)0xE178, (q15_t)0x83B1, + (q15_t)0xE1A9, (q15_t)0x83A5, (q15_t)0xE1DA, (q15_t)0x8399, + (q15_t)0xE20A, (q15_t)0x838E, (q15_t)0xE23B, (q15_t)0x8382, + (q15_t)0xE26C, (q15_t)0x8376, (q15_t)0xE29D, (q15_t)0x836B, + (q15_t)0xE2CE, (q15_t)0x835F, (q15_t)0xE2FF, (q15_t)0x8354, + (q15_t)0xE330, (q15_t)0x8348, (q15_t)0xE361, (q15_t)0x833D, + (q15_t)0xE392, (q15_t)0x8332, (q15_t)0xE3C3, (q15_t)0x8327, + (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE425, (q15_t)0x8311, + (q15_t)0xE456, (q15_t)0x8306, (q15_t)0xE487, (q15_t)0x82FB, + (q15_t)0xE4B8, (q15_t)0x82F0, (q15_t)0xE4E9, (q15_t)0x82E6, + (q15_t)0xE51B, (q15_t)0x82DB, (q15_t)0xE54C, (q15_t)0x82D0, + (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE5AE, (q15_t)0x82BC, + (q15_t)0xE5DF, (q15_t)0x82B1, (q15_t)0xE610, (q15_t)0x82A7, + (q15_t)0xE642, (q15_t)0x829D, (q15_t)0xE673, (q15_t)0x8293, + (q15_t)0xE6A4, (q15_t)0x8289, (q15_t)0xE6D5, (q15_t)0x827F, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE738, (q15_t)0x826B, + (q15_t)0xE769, (q15_t)0x8262, (q15_t)0xE79B, (q15_t)0x8258, + (q15_t)0xE7CC, (q15_t)0x824F, (q15_t)0xE7FD, (q15_t)0x8245, + (q15_t)0xE82F, (q15_t)0x823C, (q15_t)0xE860, (q15_t)0x8232, + (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE8C3, (q15_t)0x8220, + (q15_t)0xE8F5, (q15_t)0x8217, (q15_t)0xE926, (q15_t)0x820E, + (q15_t)0xE957, (q15_t)0x8205, (q15_t)0xE989, (q15_t)0x81FC, + (q15_t)0xE9BA, (q15_t)0x81F3, (q15_t)0xE9EC, (q15_t)0x81EB, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEA4F, (q15_t)0x81D9, + (q15_t)0xEA80, (q15_t)0x81D1, (q15_t)0xEAB2, (q15_t)0x81C8, + (q15_t)0xEAE4, (q15_t)0x81C0, (q15_t)0xEB15, (q15_t)0x81B8, + (q15_t)0xEB47, (q15_t)0x81B0, (q15_t)0xEB78, (q15_t)0x81A8, + (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEBDC, (q15_t)0x8198, + (q15_t)0xEC0D, (q15_t)0x8190, (q15_t)0xEC3F, (q15_t)0x8188, + (q15_t)0xEC71, (q15_t)0x8180, (q15_t)0xECA2, (q15_t)0x8179, + (q15_t)0xECD4, (q15_t)0x8171, (q15_t)0xED06, (q15_t)0x816A, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xED69, (q15_t)0x815B, + (q15_t)0xED9B, (q15_t)0x8154, (q15_t)0xEDCD, (q15_t)0x814C, + (q15_t)0xEDFE, (q15_t)0x8145, (q15_t)0xEE30, (q15_t)0x813E, + (q15_t)0xEE62, (q15_t)0x8137, (q15_t)0xEE94, (q15_t)0x8130, + (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEEF7, (q15_t)0x8123, + (q15_t)0xEF29, (q15_t)0x811C, (q15_t)0xEF5B, (q15_t)0x8116, + (q15_t)0xEF8D, (q15_t)0x810F, (q15_t)0xEFBF, (q15_t)0x8109, + (q15_t)0xEFF1, (q15_t)0x8102, (q15_t)0xF022, (q15_t)0x80FC, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF086, (q15_t)0x80F0, + (q15_t)0xF0B8, (q15_t)0x80EA, (q15_t)0xF0EA, (q15_t)0x80E4, + (q15_t)0xF11C, (q15_t)0x80DE, (q15_t)0xF14E, (q15_t)0x80D8, + (q15_t)0xF180, (q15_t)0x80D2, (q15_t)0xF1B2, (q15_t)0x80CD, + (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF216, (q15_t)0x80C2, + (q15_t)0xF248, (q15_t)0x80BC, (q15_t)0xF27A, (q15_t)0x80B7, + (q15_t)0xF2AC, (q15_t)0x80B2, (q15_t)0xF2DE, (q15_t)0x80AC, + (q15_t)0xF310, (q15_t)0x80A7, (q15_t)0xF342, (q15_t)0x80A2, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF3A6, (q15_t)0x8098, + (q15_t)0xF3D8, (q15_t)0x8094, (q15_t)0xF40A, (q15_t)0x808F, + (q15_t)0xF43C, (q15_t)0x808A, (q15_t)0xF46E, (q15_t)0x8086, + (q15_t)0xF4A0, (q15_t)0x8081, (q15_t)0xF4D2, (q15_t)0x807D, + (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF536, (q15_t)0x8074, + (q15_t)0xF568, (q15_t)0x8070, (q15_t)0xF59A, (q15_t)0x806C, + (q15_t)0xF5CC, (q15_t)0x8068, (q15_t)0xF5FF, (q15_t)0x8064, + (q15_t)0xF631, (q15_t)0x8060, (q15_t)0xF663, (q15_t)0x805C, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF6C7, (q15_t)0x8055, + (q15_t)0xF6F9, (q15_t)0x8051, (q15_t)0xF72B, (q15_t)0x804E, + (q15_t)0xF75D, (q15_t)0x804A, (q15_t)0xF790, (q15_t)0x8047, + (q15_t)0xF7C2, (q15_t)0x8043, (q15_t)0xF7F4, (q15_t)0x8040, + (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF858, (q15_t)0x803A, + (q15_t)0xF88A, (q15_t)0x8037, (q15_t)0xF8BD, (q15_t)0x8034, + (q15_t)0xF8EF, (q15_t)0x8031, (q15_t)0xF921, (q15_t)0x802F, + (q15_t)0xF953, (q15_t)0x802C, (q15_t)0xF985, (q15_t)0x8029, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xF9EA, (q15_t)0x8025, + (q15_t)0xFA1C, (q15_t)0x8022, (q15_t)0xFA4E, (q15_t)0x8020, + (q15_t)0xFA80, (q15_t)0x801E, (q15_t)0xFAB3, (q15_t)0x801C, + (q15_t)0xFAE5, (q15_t)0x801A, (q15_t)0xFB17, (q15_t)0x8018, + (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFB7C, (q15_t)0x8014, + (q15_t)0xFBAE, (q15_t)0x8012, (q15_t)0xFBE0, (q15_t)0x8011, + (q15_t)0xFC12, (q15_t)0x800F, (q15_t)0xFC45, (q15_t)0x800D, + (q15_t)0xFC77, (q15_t)0x800C, (q15_t)0xFCA9, (q15_t)0x800B, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFD0E, (q15_t)0x8008, + (q15_t)0xFD40, (q15_t)0x8007, (q15_t)0xFD72, (q15_t)0x8006, + (q15_t)0xFDA4, (q15_t)0x8005, (q15_t)0xFDD7, (q15_t)0x8004, + (q15_t)0xFE09, (q15_t)0x8003, (q15_t)0xFE3B, (q15_t)0x8003, + (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFEA0, (q15_t)0x8001, + (q15_t)0xFED2, (q15_t)0x8001, (q15_t)0xFF04, (q15_t)0x8000, + (q15_t)0xFF36, (q15_t)0x8000, (q15_t)0xFF69, (q15_t)0x8000, + (q15_t)0xFF9B, (q15_t)0x8000, (q15_t)0xFFCD, (q15_t)0x8000 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +/** + @} end of CFFT_CIFFT group +*/ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_16) + +const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH] = +{ + /* radix 4, size 12 */ + 8,64, 16,32, 24,96, 40,80, 56,112, 88,104 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_32) +const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH] = +{ + /* 4x2, size 24 */ + 8,128, 16,64, 24,192, 40,160, 48,96, 56,224, 72,144, + 88,208, 104,176, 120,240, 152,200, 184,232 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_64) +const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH] = +{ + /* radix 4, size 56 */ + 8,256, 16,128, 24,384, 32,64, 40,320, 48,192, 56,448, 72,288, 80,160, 88,416, 104,352, + 112,224, 120,480, 136,272, 152,400, 168,336, 176,208, 184,464, 200,304, 216,432, + 232,368, 248,496, 280,392, 296,328, 312,456, 344,424, 376,488, 440,472 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_128) +const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH] = +{ + /* 4x2, size 112 */ + 8,512, 16,256, 24,768, 32,128, 40,640, 48,384, 56,896, 72,576, 80,320, 88,832, 96,192, + 104,704, 112,448, 120,960, 136,544, 144,288, 152,800, 168,672, 176,416, 184,928, 200,608, + 208,352, 216,864, 232,736, 240,480, 248,992, 264,528, 280,784, 296,656, 304,400, 312,912, + 328,592, 344,848, 360,720, 368,464, 376,976, 392,560, 408,816, 424,688, 440,944, 456,624, + 472,880, 488,752, 504,1008, 536,776, 552,648, 568,904, 600,840, 616,712, 632,968, + 664,808, 696,936, 728,872, 760,1000, 824,920, 888,984 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_256) +const uint16_t armBitRevIndexTableF64_256[ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH] = +{ + /* radix 4, size 240 */ + 8,1024, 16,512, 24,1536, 32,256, 40,1280, 48,768, 56,1792, 64,128, 72,1152, 80,640, + 88,1664, 96,384, 104,1408, 112,896, 120,1920, 136,1088, 144,576, 152,1600, 160,320, + 168,1344, 176,832, 184,1856, 200,1216, 208,704, 216,1728, 224,448, 232,1472, 240,960, + 248,1984, 264,1056, 272,544, 280,1568, 296,1312, 304,800, 312,1824, 328,1184, 336,672, + 344,1696, 352,416, 360,1440, 368,928, 376,1952, 392,1120, 400,608, 408,1632, 424,1376, + 432,864, 440,1888, 456,1248, 464,736, 472,1760, 488,1504, 496,992, 504,2016, 520,1040, + 536,1552, 552,1296, 560,784, 568,1808, 584,1168, 592,656, 600,1680, 616,1424, 624,912, + 632,1936, 648,1104, 664,1616, 680,1360, 688,848, 696,1872, 712,1232, 728,1744, 744,1488, + 752,976, 760,2000, 776,1072, 792,1584, 808,1328, 824,1840, 840,1200, 856,1712, 872,1456, + 880,944, 888,1968, 904,1136, 920,1648, 936,1392, 952,1904, 968,1264, 984,1776, 1000,1520, + 1016,2032, 1048,1544, 1064,1288, 1080,1800, 1096,1160, 1112,1672, 1128,1416, 1144,1928, + 1176,1608, 1192,1352, 1208,1864, 1240,1736, 1256,1480, 1272,1992, 1304,1576, 1336,1832, + 1368,1704, 1384,1448, 1400,1960, 1432,1640, 1464,1896, 1496,1768, 1528,2024, 1592,1816, + 1624,1688, 1656,1944, 1720,1880, 1784,2008, 1912,1976 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_512) +const uint16_t armBitRevIndexTableF64_512[ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH] = +{ + /* 4x2, size 480 */ + 8,2048, 16,1024, 24,3072, 32,512, 40,2560, 48,1536, 56,3584, 64,256, 72,2304, 80,1280, + 88,3328, 96,768, 104,2816, 112,1792, 120,3840, 136,2176, 144,1152, 152,3200, 160,640, + 168,2688, 176,1664, 184,3712, 192,384, 200,2432, 208,1408, 216,3456, 224,896, 232,2944, + 240,1920, 248,3968, 264,2112, 272,1088, 280,3136, 288,576, 296,2624, 304,1600, 312,3648, + 328,2368, 336,1344, 344,3392, 352,832, 360,2880, 368,1856, 376,3904, 392,2240, 400,1216, + 408,3264, 416,704, 424,2752, 432,1728, 440,3776, 456,2496, 464,1472, 472,3520, 480,960, + 488,3008, 496,1984, 504,4032, 520,2080, 528,1056, 536,3104, 552,2592, 560,1568, 568,3616, + 584,2336, 592,1312, 600,3360, 608,800, 616,2848, 624,1824, 632,3872, 648,2208, 656,1184, + 664,3232, 680,2720, 688,1696, 696,3744, 712,2464, 720,1440, 728,3488, 736,928, 744,2976, + 752,1952, 760,4000, 776,2144, 784,1120, 792,3168, 808,2656, 816,1632, 824,3680, 840,2400, + 848,1376, 856,3424, 872,2912, 880,1888, 888,3936, 904,2272, 912,1248, 920,3296, 936,2784, + 944,1760, 952,3808, 968,2528, 976,1504, 984,3552, 1000,3040, 1008,2016, 1016,4064, + 1032,2064, 1048,3088, 1064,2576, 1072,1552, 1080,3600, 1096,2320, 1104,1296, 1112,3344, + 1128,2832, 1136,1808, 1144,3856, 1160,2192, 1176,3216, 1192,2704, 1200,1680, 1208,3728, + 1224,2448, 1232,1424, 1240,3472, 1256,2960, 1264,1936, 1272,3984, 1288,2128, 1304,3152, + 1320,2640, 1328,1616, 1336,3664, 1352,2384, 1368,3408, 1384,2896, 1392,1872, 1400,3920, + 1416,2256, 1432,3280, 1448,2768, 1456,1744, 1464,3792, 1480,2512, 1496,3536, 1512,3024, + 1520,2000, 1528,4048, 1544,2096, 1560,3120, 1576,2608, 1592,3632, 1608,2352, 1624,3376, + 1640,2864, 1648,1840, 1656,3888, 1672,2224, 1688,3248, 1704,2736, 1720,3760, 1736,2480, + 1752,3504, 1768,2992, 1776,1968, 1784,4016, 1800,2160, 1816,3184, 1832,2672, 1848,3696, + 1864,2416, 1880,3440, 1896,2928, 1912,3952, 1928,2288, 1944,3312, 1960,2800, 1976,3824, + 1992,2544, 2008,3568, 2024,3056, 2040,4080, 2072,3080, 2088,2568, 2104,3592, 2120,2312, + 2136,3336, 2152,2824, 2168,3848, 2200,3208, 2216,2696, 2232,3720, 2248,2440, 2264,3464, + 2280,2952, 2296,3976, 2328,3144, 2344,2632, 2360,3656, 2392,3400, 2408,2888, 2424,3912, + 2456,3272, 2472,2760, 2488,3784, 2520,3528, 2536,3016, 2552,4040, 2584,3112, 2616,3624, + 2648,3368, 2664,2856, 2680,3880, 2712,3240, 2744,3752, 2776,3496, 2792,2984, 2808,4008, + 2840,3176, 2872,3688, 2904,3432, 2936,3944, 2968,3304, 3000,3816, 3032,3560, 3064,4072, + 3128,3608, 3160,3352, 3192,3864, 3256,3736, 3288,3480, 3320,3992, 3384,3672, 3448,3928, + 3512,3800, 3576,4056, 3704,3896, 3832,4024 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_1024) +const uint16_t armBitRevIndexTableF64_1024[ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH] = +{ + /* radix 4, size 992 */ + 8,4096, 16,2048, 24,6144, 32,1024, 40,5120, 48,3072, 56,7168, 64,512, 72,4608, + 80,2560, 88,6656, 96,1536, 104,5632, 112,3584, 120,7680, 128,256, 136,4352, + 144,2304, 152,6400, 160,1280, 168,5376, 176,3328, 184,7424, 192,768, 200,4864, + 208,2816, 216,6912, 224,1792, 232,5888, 240,3840, 248,7936, 264,4224, 272,2176, + 280,6272, 288,1152, 296,5248, 304,3200, 312,7296, 320,640, 328,4736, 336,2688, + 344,6784, 352,1664, 360,5760, 368,3712, 376,7808, 392,4480, 400,2432, 408,6528, + 416,1408, 424,5504, 432,3456, 440,7552, 448,896, 456,4992, 464,2944, 472,7040, + 480,1920, 488,6016, 496,3968, 504,8064, 520,4160, 528,2112, 536,6208, 544,1088, + 552,5184, 560,3136, 568,7232, 584,4672, 592,2624, 600,6720, 608,1600, 616,5696, + 624,3648, 632,7744, 648,4416, 656,2368, 664,6464, 672,1344, 680,5440, 688,3392, + 696,7488, 704,832, 712,4928, 720,2880, 728,6976, 736,1856, 744,5952, 752,3904, + 760,8000, 776,4288, 784,2240, 792,6336, 800,1216, 808,5312, 816,3264, 824,7360, + 840,4800, 848,2752, 856,6848, 864,1728, 872,5824, 880,3776, 888,7872, 904,4544, + 912,2496, 920,6592, 928,1472, 936,5568, 944,3520, 952,7616, 968,5056, 976,3008, + 984,7104, 992,1984, 1000,6080, 1008,4032, 1016,8128, 1032,4128, 1040,2080, + 1048,6176, 1064,5152, 1072,3104, 1080,7200, 1096,4640, 1104,2592, 1112,6688, + 1120,1568, 1128,5664, 1136,3616, 1144,7712, 1160,4384, 1168,2336, 1176,6432, + 1184,1312, 1192,5408, 1200,3360, 1208,7456, 1224,4896, 1232,2848, 1240,6944, + 1248,1824, 1256,5920, 1264,3872, 1272,7968, 1288,4256, 1296,2208, 1304,6304, + 1320,5280, 1328,3232, 1336,7328, 1352,4768, 1360,2720, 1368,6816, 1376,1696, + 1384,5792, 1392,3744, 1400,7840, 1416,4512, 1424,2464, 1432,6560, 1448,5536, + 1456,3488, 1464,7584, 1480,5024, 1488,2976, 1496,7072, 1504,1952, 1512,6048, + 1520,4000, 1528,8096, 1544,4192, 1552,2144, 1560,6240, 1576,5216, 1584,3168, + 1592,7264, 1608,4704, 1616,2656, 1624,6752, 1640,5728, 1648,3680, 1656,7776, + 1672,4448, 1680,2400, 1688,6496, 1704,5472, 1712,3424, 1720,7520, 1736,4960, + 1744,2912, 1752,7008, 1760,1888, 1768,5984, 1776,3936, 1784,8032, 1800,4320, + 1808,2272, 1816,6368, 1832,5344, 1840,3296, 1848,7392, 1864,4832, 1872,2784, + 1880,6880, 1896,5856, 1904,3808, 1912,7904, 1928,4576, 1936,2528, 1944,6624, + 1960,5600, 1968,3552, 1976,7648, 1992,5088, 2000,3040, 2008,7136, 2024,6112, + 2032,4064, 2040,8160, 2056,4112, 2072,6160, 2088,5136, 2096,3088, 2104,7184, + 2120,4624, 2128,2576, 2136,6672, 2152,5648, 2160,3600, 2168,7696, 2184,4368, + 2192,2320, 2200,6416, 2216,5392, 2224,3344, 2232,7440, 2248,4880, 2256,2832, + 2264,6928, 2280,5904, 2288,3856, 2296,7952, 2312,4240, 2328,6288, 2344,5264, + 2352,3216, 2360,7312, 2376,4752, 2384,2704, 2392,6800, 2408,5776, 2416,3728, + 2424,7824, 2440,4496, 2456,6544, 2472,5520, 2480,3472, 2488,7568, 2504,5008, + 2512,2960, 2520,7056, 2536,6032, 2544,3984, 2552,8080, 2568,4176, 2584,6224, + 2600,5200, 2608,3152, 2616,7248, 2632,4688, 2648,6736, 2664,5712, 2672,3664, + 2680,7760, 2696,4432, 2712,6480, 2728,5456, 2736,3408, 2744,7504, 2760,4944, + 2768,2896, 2776,6992, 2792,5968, 2800,3920, 2808,8016, 2824,4304, 2840,6352, + 2856,5328, 2864,3280, 2872,7376, 2888,4816, 2904,6864, 2920,5840, 2928,3792, + 2936,7888, 2952,4560, 2968,6608, 2984,5584, 2992,3536, 3000,7632, 3016,5072, + 3032,7120, 3048,6096, 3056,4048, 3064,8144, 3080,4144, 3096,6192, 3112,5168, + 3128,7216, 3144,4656, 3160,6704, 3176,5680, 3184,3632, 3192,7728, 3208,4400, + 3224,6448, 3240,5424, 3248,3376, 3256,7472, 3272,4912, 3288,6960, 3304,5936, + 3312,3888, 3320,7984, 3336,4272, 3352,6320, 3368,5296, 3384,7344, 3400,4784, + 3416,6832, 3432,5808, 3440,3760, 3448,7856, 3464,4528, 3480,6576, 3496,5552, + 3512,7600, 3528,5040, 3544,7088, 3560,6064, 3568,4016, 3576,8112, 3592,4208, + 3608,6256, 3624,5232, 3640,7280, 3656,4720, 3672,6768, 3688,5744, 3704,7792, + 3720,4464, 3736,6512, 3752,5488, 3768,7536, 3784,4976, 3800,7024, 3816,6000, + 3824,3952, 3832,8048, 3848,4336, 3864,6384, 3880,5360, 3896,7408, 3912,4848, + 3928,6896, 3944,5872, 3960,7920, 3976,4592, 3992,6640, 4008,5616, 4024,7664, + 4040,5104, 4056,7152, 4072,6128, 4088,8176, 4120,6152, 4136,5128, 4152,7176, + 4168,4616, 4184,6664, 4200,5640, 4216,7688, 4232,4360, 4248,6408, 4264,5384, + 4280,7432, 4296,4872, 4312,6920, 4328,5896, 4344,7944, 4376,6280, 4392,5256, + 4408,7304, 4424,4744, 4440,6792, 4456,5768, 4472,7816, 4504,6536, 4520,5512, + 4536,7560, 4552,5000, 4568,7048, 4584,6024, 4600,8072, 4632,6216, 4648,5192, + 4664,7240, 4696,6728, 4712,5704, 4728,7752, 4760,6472, 4776,5448, 4792,7496, + 4808,4936, 4824,6984, 4840,5960, 4856,8008, 4888,6344, 4904,5320, 4920,7368, + 4952,6856, 4968,5832, 4984,7880, 5016,6600, 5032,5576, 5048,7624, 5080,7112, + 5096,6088, 5112,8136, 5144,6184, 5176,7208, 5208,6696, 5224,5672, 5240,7720, + 5272,6440, 5288,5416, 5304,7464, 5336,6952, 5352,5928, 5368,7976, 5400,6312, + 5432,7336, 5464,6824, 5480,5800, 5496,7848, 5528,6568, 5560,7592, 5592,7080, + 5608,6056, 5624,8104, 5656,6248, 5688,7272, 5720,6760, 5752,7784, 5784,6504, + 5816,7528, 5848,7016, 5864,5992, 5880,8040, 5912,6376, 5944,7400, 5976,6888, + 6008,7912, 6040,6632, 6072,7656, 6104,7144, 6136,8168, 6200,7192, 6232,6680, + 6264,7704, 6296,6424, 6328,7448, 6360,6936, 6392,7960, 6456,7320, 6488,6808, + 6520,7832, 6584,7576, 6616,7064, 6648,8088, 6712,7256, 6776,7768, 6840,7512, + 6872,7000, 6904,8024, 6968,7384, 7032,7896, 7096,7640, 7160,8152, 7288,7736, + 7352,7480, 7416,7992, 7544,7864, 7672,8120, 7928,8056 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_2048) +const uint16_t armBitRevIndexTableF64_2048[ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH] = +{ + /* 4x2, size 1984 */ + 8,8192, 16,4096, 24,12288, 32,2048, 40,10240, 48,6144, 56,14336, 64,1024, + 72,9216, 80,5120, 88,13312, 96,3072, 104,11264, 112,7168, 120,15360, 128,512, + 136,8704, 144,4608, 152,12800, 160,2560, 168,10752, 176,6656, 184,14848, + 192,1536, 200,9728, 208,5632, 216,13824, 224,3584, 232,11776, 240,7680, + 248,15872, 264,8448, 272,4352, 280,12544, 288,2304, 296,10496, 304,6400, + 312,14592, 320,1280, 328,9472, 336,5376, 344,13568, 352,3328, 360,11520, + 368,7424, 376,15616, 384,768, 392,8960, 400,4864, 408,13056, 416,2816, + 424,11008, 432,6912, 440,15104, 448,1792, 456,9984, 464,5888, 472,14080, + 480,3840, 488,12032, 496,7936, 504,16128, 520,8320, 528,4224, 536,12416, + 544,2176, 552,10368, 560,6272, 568,14464, 576,1152, 584,9344, 592,5248, + 600,13440, 608,3200, 616,11392, 624,7296, 632,15488, 648,8832, 656,4736, + 664,12928, 672,2688, 680,10880, 688,6784, 696,14976, 704,1664, 712,9856, + 720,5760, 728,13952, 736,3712, 744,11904, 752,7808, 760,16000, 776,8576, + 784,4480, 792,12672, 800,2432, 808,10624, 816,6528, 824,14720, 832,1408, + 840,9600, 848,5504, 856,13696, 864,3456, 872,11648, 880,7552, 888,15744, + 904,9088, 912,4992, 920,13184, 928,2944, 936,11136, 944,7040, 952,15232, + 960,1920, 968,10112, 976,6016, 984,14208, 992,3968, 1000,12160, 1008,8064, + 1016,16256, 1032,8256, 1040,4160, 1048,12352, 1056,2112, 1064,10304, 1072,6208, + 1080,14400, 1096,9280, 1104,5184, 1112,13376, 1120,3136, 1128,11328, 1136,7232, + 1144,15424, 1160,8768, 1168,4672, 1176,12864, 1184,2624, 1192,10816, 1200,6720, + 1208,14912, 1216,1600, 1224,9792, 1232,5696, 1240,13888, 1248,3648, 1256,11840, + 1264,7744, 1272,15936, 1288,8512, 1296,4416, 1304,12608, 1312,2368, 1320,10560, + 1328,6464, 1336,14656, 1352,9536, 1360,5440, 1368,13632, 1376,3392, 1384,11584, + 1392,7488, 1400,15680, 1416,9024, 1424,4928, 1432,13120, 1440,2880, 1448,11072, + 1456,6976, 1464,15168, 1472,1856, 1480,10048, 1488,5952, 1496,14144, 1504,3904, + 1512,12096, 1520,8000, 1528,16192, 1544,8384, 1552,4288, 1560,12480, 1568,2240, + 1576,10432, 1584,6336, 1592,14528, 1608,9408, 1616,5312, 1624,13504, 1632,3264, + 1640,11456, 1648,7360, 1656,15552, 1672,8896, 1680,4800, 1688,12992, 1696,2752, + 1704,10944, 1712,6848, 1720,15040, 1736,9920, 1744,5824, 1752,14016, 1760,3776, + 1768,11968, 1776,7872, 1784,16064, 1800,8640, 1808,4544, 1816,12736, 1824,2496, + 1832,10688, 1840,6592, 1848,14784, 1864,9664, 1872,5568, 1880,13760, 1888,3520, + 1896,11712, 1904,7616, 1912,15808, 1928,9152, 1936,5056, 1944,13248, 1952,3008, + 1960,11200, 1968,7104, 1976,15296, 1992,10176, 2000,6080, 2008,14272, 2016,4032, + 2024,12224, 2032,8128, 2040,16320, 2056,8224, 2064,4128, 2072,12320, 2088,10272, + 2096,6176, 2104,14368, 2120,9248, 2128,5152, 2136,13344, 2144,3104, 2152,11296, + 2160,7200, 2168,15392, 2184,8736, 2192,4640, 2200,12832, 2208,2592, 2216,10784, + 2224,6688, 2232,14880, 2248,9760, 2256,5664, 2264,13856, 2272,3616, 2280,11808, + 2288,7712, 2296,15904, 2312,8480, 2320,4384, 2328,12576, 2344,10528, 2352,6432, + 2360,14624, 2376,9504, 2384,5408, 2392,13600, 2400,3360, 2408,11552, 2416,7456, + 2424,15648, 2440,8992, 2448,4896, 2456,13088, 2464,2848, 2472,11040, 2480,6944, + 2488,15136, 2504,10016, 2512,5920, 2520,14112, 2528,3872, 2536,12064, 2544,7968, + 2552,16160, 2568,8352, 2576,4256, 2584,12448, 2600,10400, 2608,6304, 2616,14496, + 2632,9376, 2640,5280, 2648,13472, 2656,3232, 2664,11424, 2672,7328, 2680,15520, + 2696,8864, 2704,4768, 2712,12960, 2728,10912, 2736,6816, 2744,15008, 2760,9888, + 2768,5792, 2776,13984, 2784,3744, 2792,11936, 2800,7840, 2808,16032, 2824,8608, + 2832,4512, 2840,12704, 2856,10656, 2864,6560, 2872,14752, 2888,9632, 2896,5536, + 2904,13728, 2912,3488, 2920,11680, 2928,7584, 2936,15776, 2952,9120, 2960,5024, + 2968,13216, 2984,11168, 2992,7072, 3000,15264, 3016,10144, 3024,6048, + 3032,14240, 3040,4000, 3048,12192, 3056,8096, 3064,16288, 3080,8288, 3088,4192, + 3096,12384, 3112,10336, 3120,6240, 3128,14432, 3144,9312, 3152,5216, 3160,13408, + 3176,11360, 3184,7264, 3192,15456, 3208,8800, 3216,4704, 3224,12896, 3240,10848, + 3248,6752, 3256,14944, 3272,9824, 3280,5728, 3288,13920, 3296,3680, 3304,11872, + 3312,7776, 3320,15968, 3336,8544, 3344,4448, 3352,12640, 3368,10592, 3376,6496, + 3384,14688, 3400,9568, 3408,5472, 3416,13664, 3432,11616, 3440,7520, 3448,15712, + 3464,9056, 3472,4960, 3480,13152, 3496,11104, 3504,7008, 3512,15200, 3528,10080, + 3536,5984, 3544,14176, 3552,3936, 3560,12128, 3568,8032, 3576,16224, 3592,8416, + 3600,4320, 3608,12512, 3624,10464, 3632,6368, 3640,14560, 3656,9440, 3664,5344, + 3672,13536, 3688,11488, 3696,7392, 3704,15584, 3720,8928, 3728,4832, 3736,13024, + 3752,10976, 3760,6880, 3768,15072, 3784,9952, 3792,5856, 3800,14048, 3816,12000, + 3824,7904, 3832,16096, 3848,8672, 3856,4576, 3864,12768, 3880,10720, 3888,6624, + 3896,14816, 3912,9696, 3920,5600, 3928,13792, 3944,11744, 3952,7648, 3960,15840, + 3976,9184, 3984,5088, 3992,13280, 4008,11232, 4016,7136, 4024,15328, 4040,10208, + 4048,6112, 4056,14304, 4072,12256, 4080,8160, 4088,16352, 4104,8208, 4120,12304, + 4136,10256, 4144,6160, 4152,14352, 4168,9232, 4176,5136, 4184,13328, 4200,11280, + 4208,7184, 4216,15376, 4232,8720, 4240,4624, 4248,12816, 4264,10768, 4272,6672, + 4280,14864, 4296,9744, 4304,5648, 4312,13840, 4328,11792, 4336,7696, 4344,15888, + 4360,8464, 4376,12560, 4392,10512, 4400,6416, 4408,14608, 4424,9488, 4432,5392, + 4440,13584, 4456,11536, 4464,7440, 4472,15632, 4488,8976, 4496,4880, 4504,13072, + 4520,11024, 4528,6928, 4536,15120, 4552,10000, 4560,5904, 4568,14096, + 4584,12048, 4592,7952, 4600,16144, 4616,8336, 4632,12432, 4648,10384, 4656,6288, + 4664,14480, 4680,9360, 4688,5264, 4696,13456, 4712,11408, 4720,7312, 4728,15504, + 4744,8848, 4760,12944, 4776,10896, 4784,6800, 4792,14992, 4808,9872, 4816,5776, + 4824,13968, 4840,11920, 4848,7824, 4856,16016, 4872,8592, 4888,12688, + 4904,10640, 4912,6544, 4920,14736, 4936,9616, 4944,5520, 4952,13712, 4968,11664, + 4976,7568, 4984,15760, 5000,9104, 5016,13200, 5032,11152, 5040,7056, 5048,15248, + 5064,10128, 5072,6032, 5080,14224, 5096,12176, 5104,8080, 5112,16272, 5128,8272, + 5144,12368, 5160,10320, 5168,6224, 5176,14416, 5192,9296, 5208,13392, + 5224,11344, 5232,7248, 5240,15440, 5256,8784, 5272,12880, 5288,10832, 5296,6736, + 5304,14928, 5320,9808, 5328,5712, 5336,13904, 5352,11856, 5360,7760, 5368,15952, + 5384,8528, 5400,12624, 5416,10576, 5424,6480, 5432,14672, 5448,9552, 5464,13648, + 5480,11600, 5488,7504, 5496,15696, 5512,9040, 5528,13136, 5544,11088, 5552,6992, + 5560,15184, 5576,10064, 5584,5968, 5592,14160, 5608,12112, 5616,8016, + 5624,16208, 5640,8400, 5656,12496, 5672,10448, 5680,6352, 5688,14544, 5704,9424, + 5720,13520, 5736,11472, 5744,7376, 5752,15568, 5768,8912, 5784,13008, + 5800,10960, 5808,6864, 5816,15056, 5832,9936, 5848,14032, 5864,11984, 5872,7888, + 5880,16080, 5896,8656, 5912,12752, 5928,10704, 5936,6608, 5944,14800, 5960,9680, + 5976,13776, 5992,11728, 6000,7632, 6008,15824, 6024,9168, 6040,13264, + 6056,11216, 6064,7120, 6072,15312, 6088,10192, 6104,14288, 6120,12240, + 6128,8144, 6136,16336, 6152,8240, 6168,12336, 6184,10288, 6200,14384, 6216,9264, + 6232,13360, 6248,11312, 6256,7216, 6264,15408, 6280,8752, 6296,12848, + 6312,10800, 6320,6704, 6328,14896, 6344,9776, 6360,13872, 6376,11824, 6384,7728, + 6392,15920, 6408,8496, 6424,12592, 6440,10544, 6456,14640, 6472,9520, + 6488,13616, 6504,11568, 6512,7472, 6520,15664, 6536,9008, 6552,13104, + 6568,11056, 6576,6960, 6584,15152, 6600,10032, 6616,14128, 6632,12080, + 6640,7984, 6648,16176, 6664,8368, 6680,12464, 6696,10416, 6712,14512, 6728,9392, + 6744,13488, 6760,11440, 6768,7344, 6776,15536, 6792,8880, 6808,12976, + 6824,10928, 6840,15024, 6856,9904, 6872,14000, 6888,11952, 6896,7856, + 6904,16048, 6920,8624, 6936,12720, 6952,10672, 6968,14768, 6984,9648, + 7000,13744, 7016,11696, 7024,7600, 7032,15792, 7048,9136, 7064,13232, + 7080,11184, 7096,15280, 7112,10160, 7128,14256, 7144,12208, 7152,8112, + 7160,16304, 7176,8304, 7192,12400, 7208,10352, 7224,14448, 7240,9328, + 7256,13424, 7272,11376, 7288,15472, 7304,8816, 7320,12912, 7336,10864, + 7352,14960, 7368,9840, 7384,13936, 7400,11888, 7408,7792, 7416,15984, 7432,8560, + 7448,12656, 7464,10608, 7480,14704, 7496,9584, 7512,13680, 7528,11632, + 7544,15728, 7560,9072, 7576,13168, 7592,11120, 7608,15216, 7624,10096, + 7640,14192, 7656,12144, 7664,8048, 7672,16240, 7688,8432, 7704,12528, + 7720,10480, 7736,14576, 7752,9456, 7768,13552, 7784,11504, 7800,15600, + 7816,8944, 7832,13040, 7848,10992, 7864,15088, 7880,9968, 7896,14064, + 7912,12016, 7928,16112, 7944,8688, 7960,12784, 7976,10736, 7992,14832, + 8008,9712, 8024,13808, 8040,11760, 8056,15856, 8072,9200, 8088,13296, + 8104,11248, 8120,15344, 8136,10224, 8152,14320, 8168,12272, 8184,16368, + 8216,12296, 8232,10248, 8248,14344, 8264,9224, 8280,13320, 8296,11272, + 8312,15368, 8328,8712, 8344,12808, 8360,10760, 8376,14856, 8392,9736, + 8408,13832, 8424,11784, 8440,15880, 8472,12552, 8488,10504, 8504,14600, + 8520,9480, 8536,13576, 8552,11528, 8568,15624, 8584,8968, 8600,13064, + 8616,11016, 8632,15112, 8648,9992, 8664,14088, 8680,12040, 8696,16136, + 8728,12424, 8744,10376, 8760,14472, 8776,9352, 8792,13448, 8808,11400, + 8824,15496, 8856,12936, 8872,10888, 8888,14984, 8904,9864, 8920,13960, + 8936,11912, 8952,16008, 8984,12680, 9000,10632, 9016,14728, 9032,9608, + 9048,13704, 9064,11656, 9080,15752, 9112,13192, 9128,11144, 9144,15240, + 9160,10120, 9176,14216, 9192,12168, 9208,16264, 9240,12360, 9256,10312, + 9272,14408, 9304,13384, 9320,11336, 9336,15432, 9368,12872, 9384,10824, + 9400,14920, 9416,9800, 9432,13896, 9448,11848, 9464,15944, 9496,12616, + 9512,10568, 9528,14664, 9560,13640, 9576,11592, 9592,15688, 9624,13128, + 9640,11080, 9656,15176, 9672,10056, 9688,14152, 9704,12104, 9720,16200, + 9752,12488, 9768,10440, 9784,14536, 9816,13512, 9832,11464, 9848,15560, + 9880,13000, 9896,10952, 9912,15048, 9944,14024, 9960,11976, 9976,16072, + 10008,12744, 10024,10696, 10040,14792, 10072,13768, 10088,11720, 10104,15816, + 10136,13256, 10152,11208, 10168,15304, 10200,14280, 10216,12232, 10232,16328, + 10264,12328, 10296,14376, 10328,13352, 10344,11304, 10360,15400, 10392,12840, + 10408,10792, 10424,14888, 10456,13864, 10472,11816, 10488,15912, 10520,12584, + 10552,14632, 10584,13608, 10600,11560, 10616,15656, 10648,13096, 10664,11048, + 10680,15144, 10712,14120, 10728,12072, 10744,16168, 10776,12456, 10808,14504, + 10840,13480, 10856,11432, 10872,15528, 10904,12968, 10936,15016, 10968,13992, + 10984,11944, 11000,16040, 11032,12712, 11064,14760, 11096,13736, 11112,11688, + 11128,15784, 11160,13224, 11192,15272, 11224,14248, 11240,12200, 11256,16296, + 11288,12392, 11320,14440, 11352,13416, 11384,15464, 11416,12904, 11448,14952, + 11480,13928, 11496,11880, 11512,15976, 11544,12648, 11576,14696, 11608,13672, + 11640,15720, 11672,13160, 11704,15208, 11736,14184, 11752,12136, 11768,16232, + 11800,12520, 11832,14568, 11864,13544, 11896,15592, 11928,13032, 11960,15080, + 11992,14056, 12024,16104, 12056,12776, 12088,14824, 12120,13800, 12152,15848, + 12184,13288, 12216,15336, 12248,14312, 12280,16360, 12344,14360, 12376,13336, + 12408,15384, 12440,12824, 12472,14872, 12504,13848, 12536,15896, 12600,14616, + 12632,13592, 12664,15640, 12696,13080, 12728,15128, 12760,14104, 12792,16152, + 12856,14488, 12888,13464, 12920,15512, 12984,15000, 13016,13976, 13048,16024, + 13112,14744, 13144,13720, 13176,15768, 13240,15256, 13272,14232, 13304,16280, + 13368,14424, 13432,15448, 13496,14936, 13528,13912, 13560,15960, 13624,14680, + 13688,15704, 13752,15192, 13784,14168, 13816,16216, 13880,14552, 13944,15576, + 14008,15064, 14072,16088, 14136,14808, 14200,15832, 14264,15320, 14328,16344, + 14456,15416, 14520,14904, 14584,15928, 14712,15672, 14776,15160, 14840,16184, + 14968,15544, 15096,16056, 15224,15800, 15352,16312, 15608,15992, 15864,16248 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_4096) +const uint16_t armBitRevIndexTableF64_4096[ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH] = +{ + /* radix 4, size 4032 */ + 8,16384, 16,8192, 24,24576, 32,4096, 40,20480, 48,12288, 56,28672, 64,2048, + 72,18432, 80,10240, 88,26624, 96,6144, 104,22528, 112,14336, 120,30720, + 128,1024, 136,17408, 144,9216, 152,25600, 160,5120, 168,21504, 176,13312, + 184,29696, 192,3072, 200,19456, 208,11264, 216,27648, 224,7168, 232,23552, + 240,15360, 248,31744, 256,512, 264,16896, 272,8704, 280,25088, 288,4608, + 296,20992, 304,12800, 312,29184, 320,2560, 328,18944, 336,10752, 344,27136, + 352,6656, 360,23040, 368,14848, 376,31232, 384,1536, 392,17920, 400,9728, + 408,26112, 416,5632, 424,22016, 432,13824, 440,30208, 448,3584, 456,19968, + 464,11776, 472,28160, 480,7680, 488,24064, 496,15872, 504,32256, 520,16640, + 528,8448, 536,24832, 544,4352, 552,20736, 560,12544, 568,28928, 576,2304, + 584,18688, 592,10496, 600,26880, 608,6400, 616,22784, 624,14592, 632,30976, + 640,1280, 648,17664, 656,9472, 664,25856, 672,5376, 680,21760, 688,13568, + 696,29952, 704,3328, 712,19712, 720,11520, 728,27904, 736,7424, 744,23808, + 752,15616, 760,32000, 776,17152, 784,8960, 792,25344, 800,4864, 808,21248, + 816,13056, 824,29440, 832,2816, 840,19200, 848,11008, 856,27392, 864,6912, + 872,23296, 880,15104, 888,31488, 896,1792, 904,18176, 912,9984, 920,26368, + 928,5888, 936,22272, 944,14080, 952,30464, 960,3840, 968,20224, 976,12032, + 984,28416, 992,7936, 1000,24320, 1008,16128, 1016,32512, 1032,16512, 1040,8320, + 1048,24704, 1056,4224, 1064,20608, 1072,12416, 1080,28800, 1088,2176, + 1096,18560, 1104,10368, 1112,26752, 1120,6272, 1128,22656, 1136,14464, + 1144,30848, 1160,17536, 1168,9344, 1176,25728, 1184,5248, 1192,21632, + 1200,13440, 1208,29824, 1216,3200, 1224,19584, 1232,11392, 1240,27776, + 1248,7296, 1256,23680, 1264,15488, 1272,31872, 1288,17024, 1296,8832, + 1304,25216, 1312,4736, 1320,21120, 1328,12928, 1336,29312, 1344,2688, + 1352,19072, 1360,10880, 1368,27264, 1376,6784, 1384,23168, 1392,14976, + 1400,31360, 1408,1664, 1416,18048, 1424,9856, 1432,26240, 1440,5760, 1448,22144, + 1456,13952, 1464,30336, 1472,3712, 1480,20096, 1488,11904, 1496,28288, + 1504,7808, 1512,24192, 1520,16000, 1528,32384, 1544,16768, 1552,8576, + 1560,24960, 1568,4480, 1576,20864, 1584,12672, 1592,29056, 1600,2432, + 1608,18816, 1616,10624, 1624,27008, 1632,6528, 1640,22912, 1648,14720, + 1656,31104, 1672,17792, 1680,9600, 1688,25984, 1696,5504, 1704,21888, + 1712,13696, 1720,30080, 1728,3456, 1736,19840, 1744,11648, 1752,28032, + 1760,7552, 1768,23936, 1776,15744, 1784,32128, 1800,17280, 1808,9088, + 1816,25472, 1824,4992, 1832,21376, 1840,13184, 1848,29568, 1856,2944, + 1864,19328, 1872,11136, 1880,27520, 1888,7040, 1896,23424, 1904,15232, + 1912,31616, 1928,18304, 1936,10112, 1944,26496, 1952,6016, 1960,22400, + 1968,14208, 1976,30592, 1984,3968, 1992,20352, 2000,12160, 2008,28544, + 2016,8064, 2024,24448, 2032,16256, 2040,32640, 2056,16448, 2064,8256, + 2072,24640, 2080,4160, 2088,20544, 2096,12352, 2104,28736, 2120,18496, + 2128,10304, 2136,26688, 2144,6208, 2152,22592, 2160,14400, 2168,30784, + 2184,17472, 2192,9280, 2200,25664, 2208,5184, 2216,21568, 2224,13376, + 2232,29760, 2240,3136, 2248,19520, 2256,11328, 2264,27712, 2272,7232, + 2280,23616, 2288,15424, 2296,31808, 2312,16960, 2320,8768, 2328,25152, + 2336,4672, 2344,21056, 2352,12864, 2360,29248, 2368,2624, 2376,19008, + 2384,10816, 2392,27200, 2400,6720, 2408,23104, 2416,14912, 2424,31296, + 2440,17984, 2448,9792, 2456,26176, 2464,5696, 2472,22080, 2480,13888, + 2488,30272, 2496,3648, 2504,20032, 2512,11840, 2520,28224, 2528,7744, + 2536,24128, 2544,15936, 2552,32320, 2568,16704, 2576,8512, 2584,24896, + 2592,4416, 2600,20800, 2608,12608, 2616,28992, 2632,18752, 2640,10560, + 2648,26944, 2656,6464, 2664,22848, 2672,14656, 2680,31040, 2696,17728, + 2704,9536, 2712,25920, 2720,5440, 2728,21824, 2736,13632, 2744,30016, 2752,3392, + 2760,19776, 2768,11584, 2776,27968, 2784,7488, 2792,23872, 2800,15680, + 2808,32064, 2824,17216, 2832,9024, 2840,25408, 2848,4928, 2856,21312, + 2864,13120, 2872,29504, 2888,19264, 2896,11072, 2904,27456, 2912,6976, + 2920,23360, 2928,15168, 2936,31552, 2952,18240, 2960,10048, 2968,26432, + 2976,5952, 2984,22336, 2992,14144, 3000,30528, 3008,3904, 3016,20288, + 3024,12096, 3032,28480, 3040,8000, 3048,24384, 3056,16192, 3064,32576, + 3080,16576, 3088,8384, 3096,24768, 3104,4288, 3112,20672, 3120,12480, + 3128,28864, 3144,18624, 3152,10432, 3160,26816, 3168,6336, 3176,22720, + 3184,14528, 3192,30912, 3208,17600, 3216,9408, 3224,25792, 3232,5312, + 3240,21696, 3248,13504, 3256,29888, 3272,19648, 3280,11456, 3288,27840, + 3296,7360, 3304,23744, 3312,15552, 3320,31936, 3336,17088, 3344,8896, + 3352,25280, 3360,4800, 3368,21184, 3376,12992, 3384,29376, 3400,19136, + 3408,10944, 3416,27328, 3424,6848, 3432,23232, 3440,15040, 3448,31424, + 3464,18112, 3472,9920, 3480,26304, 3488,5824, 3496,22208, 3504,14016, + 3512,30400, 3520,3776, 3528,20160, 3536,11968, 3544,28352, 3552,7872, + 3560,24256, 3568,16064, 3576,32448, 3592,16832, 3600,8640, 3608,25024, + 3616,4544, 3624,20928, 3632,12736, 3640,29120, 3656,18880, 3664,10688, + 3672,27072, 3680,6592, 3688,22976, 3696,14784, 3704,31168, 3720,17856, + 3728,9664, 3736,26048, 3744,5568, 3752,21952, 3760,13760, 3768,30144, + 3784,19904, 3792,11712, 3800,28096, 3808,7616, 3816,24000, 3824,15808, + 3832,32192, 3848,17344, 3856,9152, 3864,25536, 3872,5056, 3880,21440, + 3888,13248, 3896,29632, 3912,19392, 3920,11200, 3928,27584, 3936,7104, + 3944,23488, 3952,15296, 3960,31680, 3976,18368, 3984,10176, 3992,26560, + 4000,6080, 4008,22464, 4016,14272, 4024,30656, 4040,20416, 4048,12224, + 4056,28608, 4064,8128, 4072,24512, 4080,16320, 4088,32704, 4104,16416, + 4112,8224, 4120,24608, 4136,20512, 4144,12320, 4152,28704, 4168,18464, + 4176,10272, 4184,26656, 4192,6176, 4200,22560, 4208,14368, 4216,30752, + 4232,17440, 4240,9248, 4248,25632, 4256,5152, 4264,21536, 4272,13344, + 4280,29728, 4296,19488, 4304,11296, 4312,27680, 4320,7200, 4328,23584, + 4336,15392, 4344,31776, 4360,16928, 4368,8736, 4376,25120, 4384,4640, + 4392,21024, 4400,12832, 4408,29216, 4424,18976, 4432,10784, 4440,27168, + 4448,6688, 4456,23072, 4464,14880, 4472,31264, 4488,17952, 4496,9760, + 4504,26144, 4512,5664, 4520,22048, 4528,13856, 4536,30240, 4552,20000, + 4560,11808, 4568,28192, 4576,7712, 4584,24096, 4592,15904, 4600,32288, + 4616,16672, 4624,8480, 4632,24864, 4648,20768, 4656,12576, 4664,28960, + 4680,18720, 4688,10528, 4696,26912, 4704,6432, 4712,22816, 4720,14624, + 4728,31008, 4744,17696, 4752,9504, 4760,25888, 4768,5408, 4776,21792, + 4784,13600, 4792,29984, 4808,19744, 4816,11552, 4824,27936, 4832,7456, + 4840,23840, 4848,15648, 4856,32032, 4872,17184, 4880,8992, 4888,25376, + 4904,21280, 4912,13088, 4920,29472, 4936,19232, 4944,11040, 4952,27424, + 4960,6944, 4968,23328, 4976,15136, 4984,31520, 5000,18208, 5008,10016, + 5016,26400, 5024,5920, 5032,22304, 5040,14112, 5048,30496, 5064,20256, + 5072,12064, 5080,28448, 5088,7968, 5096,24352, 5104,16160, 5112,32544, + 5128,16544, 5136,8352, 5144,24736, 5160,20640, 5168,12448, 5176,28832, + 5192,18592, 5200,10400, 5208,26784, 5216,6304, 5224,22688, 5232,14496, + 5240,30880, 5256,17568, 5264,9376, 5272,25760, 5288,21664, 5296,13472, + 5304,29856, 5320,19616, 5328,11424, 5336,27808, 5344,7328, 5352,23712, + 5360,15520, 5368,31904, 5384,17056, 5392,8864, 5400,25248, 5416,21152, + 5424,12960, 5432,29344, 5448,19104, 5456,10912, 5464,27296, 5472,6816, + 5480,23200, 5488,15008, 5496,31392, 5512,18080, 5520,9888, 5528,26272, + 5536,5792, 5544,22176, 5552,13984, 5560,30368, 5576,20128, 5584,11936, + 5592,28320, 5600,7840, 5608,24224, 5616,16032, 5624,32416, 5640,16800, + 5648,8608, 5656,24992, 5672,20896, 5680,12704, 5688,29088, 5704,18848, + 5712,10656, 5720,27040, 5728,6560, 5736,22944, 5744,14752, 5752,31136, + 5768,17824, 5776,9632, 5784,26016, 5800,21920, 5808,13728, 5816,30112, + 5832,19872, 5840,11680, 5848,28064, 5856,7584, 5864,23968, 5872,15776, + 5880,32160, 5896,17312, 5904,9120, 5912,25504, 5928,21408, 5936,13216, + 5944,29600, 5960,19360, 5968,11168, 5976,27552, 5984,7072, 5992,23456, + 6000,15264, 6008,31648, 6024,18336, 6032,10144, 6040,26528, 6056,22432, + 6064,14240, 6072,30624, 6088,20384, 6096,12192, 6104,28576, 6112,8096, + 6120,24480, 6128,16288, 6136,32672, 6152,16480, 6160,8288, 6168,24672, + 6184,20576, 6192,12384, 6200,28768, 6216,18528, 6224,10336, 6232,26720, + 6248,22624, 6256,14432, 6264,30816, 6280,17504, 6288,9312, 6296,25696, + 6312,21600, 6320,13408, 6328,29792, 6344,19552, 6352,11360, 6360,27744, + 6368,7264, 6376,23648, 6384,15456, 6392,31840, 6408,16992, 6416,8800, + 6424,25184, 6440,21088, 6448,12896, 6456,29280, 6472,19040, 6480,10848, + 6488,27232, 6496,6752, 6504,23136, 6512,14944, 6520,31328, 6536,18016, + 6544,9824, 6552,26208, 6568,22112, 6576,13920, 6584,30304, 6600,20064, + 6608,11872, 6616,28256, 6624,7776, 6632,24160, 6640,15968, 6648,32352, + 6664,16736, 6672,8544, 6680,24928, 6696,20832, 6704,12640, 6712,29024, + 6728,18784, 6736,10592, 6744,26976, 6760,22880, 6768,14688, 6776,31072, + 6792,17760, 6800,9568, 6808,25952, 6824,21856, 6832,13664, 6840,30048, + 6856,19808, 6864,11616, 6872,28000, 6880,7520, 6888,23904, 6896,15712, + 6904,32096, 6920,17248, 6928,9056, 6936,25440, 6952,21344, 6960,13152, + 6968,29536, 6984,19296, 6992,11104, 7000,27488, 7016,23392, 7024,15200, + 7032,31584, 7048,18272, 7056,10080, 7064,26464, 7080,22368, 7088,14176, + 7096,30560, 7112,20320, 7120,12128, 7128,28512, 7136,8032, 7144,24416, + 7152,16224, 7160,32608, 7176,16608, 7184,8416, 7192,24800, 7208,20704, + 7216,12512, 7224,28896, 7240,18656, 7248,10464, 7256,26848, 7272,22752, + 7280,14560, 7288,30944, 7304,17632, 7312,9440, 7320,25824, 7336,21728, + 7344,13536, 7352,29920, 7368,19680, 7376,11488, 7384,27872, 7400,23776, + 7408,15584, 7416,31968, 7432,17120, 7440,8928, 7448,25312, 7464,21216, + 7472,13024, 7480,29408, 7496,19168, 7504,10976, 7512,27360, 7528,23264, + 7536,15072, 7544,31456, 7560,18144, 7568,9952, 7576,26336, 7592,22240, + 7600,14048, 7608,30432, 7624,20192, 7632,12000, 7640,28384, 7648,7904, + 7656,24288, 7664,16096, 7672,32480, 7688,16864, 7696,8672, 7704,25056, + 7720,20960, 7728,12768, 7736,29152, 7752,18912, 7760,10720, 7768,27104, + 7784,23008, 7792,14816, 7800,31200, 7816,17888, 7824,9696, 7832,26080, + 7848,21984, 7856,13792, 7864,30176, 7880,19936, 7888,11744, 7896,28128, + 7912,24032, 7920,15840, 7928,32224, 7944,17376, 7952,9184, 7960,25568, + 7976,21472, 7984,13280, 7992,29664, 8008,19424, 8016,11232, 8024,27616, + 8040,23520, 8048,15328, 8056,31712, 8072,18400, 8080,10208, 8088,26592, + 8104,22496, 8112,14304, 8120,30688, 8136,20448, 8144,12256, 8152,28640, + 8168,24544, 8176,16352, 8184,32736, 8200,16400, 8216,24592, 8232,20496, + 8240,12304, 8248,28688, 8264,18448, 8272,10256, 8280,26640, 8296,22544, + 8304,14352, 8312,30736, 8328,17424, 8336,9232, 8344,25616, 8360,21520, + 8368,13328, 8376,29712, 8392,19472, 8400,11280, 8408,27664, 8424,23568, + 8432,15376, 8440,31760, 8456,16912, 8464,8720, 8472,25104, 8488,21008, + 8496,12816, 8504,29200, 8520,18960, 8528,10768, 8536,27152, 8552,23056, + 8560,14864, 8568,31248, 8584,17936, 8592,9744, 8600,26128, 8616,22032, + 8624,13840, 8632,30224, 8648,19984, 8656,11792, 8664,28176, 8680,24080, + 8688,15888, 8696,32272, 8712,16656, 8728,24848, 8744,20752, 8752,12560, + 8760,28944, 8776,18704, 8784,10512, 8792,26896, 8808,22800, 8816,14608, + 8824,30992, 8840,17680, 8848,9488, 8856,25872, 8872,21776, 8880,13584, + 8888,29968, 8904,19728, 8912,11536, 8920,27920, 8936,23824, 8944,15632, + 8952,32016, 8968,17168, 8984,25360, 9000,21264, 9008,13072, 9016,29456, + 9032,19216, 9040,11024, 9048,27408, 9064,23312, 9072,15120, 9080,31504, + 9096,18192, 9104,10000, 9112,26384, 9128,22288, 9136,14096, 9144,30480, + 9160,20240, 9168,12048, 9176,28432, 9192,24336, 9200,16144, 9208,32528, + 9224,16528, 9240,24720, 9256,20624, 9264,12432, 9272,28816, 9288,18576, + 9296,10384, 9304,26768, 9320,22672, 9328,14480, 9336,30864, 9352,17552, + 9368,25744, 9384,21648, 9392,13456, 9400,29840, 9416,19600, 9424,11408, + 9432,27792, 9448,23696, 9456,15504, 9464,31888, 9480,17040, 9496,25232, + 9512,21136, 9520,12944, 9528,29328, 9544,19088, 9552,10896, 9560,27280, + 9576,23184, 9584,14992, 9592,31376, 9608,18064, 9616,9872, 9624,26256, + 9640,22160, 9648,13968, 9656,30352, 9672,20112, 9680,11920, 9688,28304, + 9704,24208, 9712,16016, 9720,32400, 9736,16784, 9752,24976, 9768,20880, + 9776,12688, 9784,29072, 9800,18832, 9808,10640, 9816,27024, 9832,22928, + 9840,14736, 9848,31120, 9864,17808, 9880,26000, 9896,21904, 9904,13712, + 9912,30096, 9928,19856, 9936,11664, 9944,28048, 9960,23952, 9968,15760, + 9976,32144, 9992,17296, 10008,25488, 10024,21392, 10032,13200, 10040,29584, + 10056,19344, 10064,11152, 10072,27536, 10088,23440, 10096,15248, 10104,31632, + 10120,18320, 10136,26512, 10152,22416, 10160,14224, 10168,30608, 10184,20368, + 10192,12176, 10200,28560, 10216,24464, 10224,16272, 10232,32656, 10248,16464, + 10264,24656, 10280,20560, 10288,12368, 10296,28752, 10312,18512, 10328,26704, + 10344,22608, 10352,14416, 10360,30800, 10376,17488, 10392,25680, 10408,21584, + 10416,13392, 10424,29776, 10440,19536, 10448,11344, 10456,27728, 10472,23632, + 10480,15440, 10488,31824, 10504,16976, 10520,25168, 10536,21072, 10544,12880, + 10552,29264, 10568,19024, 10576,10832, 10584,27216, 10600,23120, 10608,14928, + 10616,31312, 10632,18000, 10648,26192, 10664,22096, 10672,13904, 10680,30288, + 10696,20048, 10704,11856, 10712,28240, 10728,24144, 10736,15952, 10744,32336, + 10760,16720, 10776,24912, 10792,20816, 10800,12624, 10808,29008, 10824,18768, + 10840,26960, 10856,22864, 10864,14672, 10872,31056, 10888,17744, 10904,25936, + 10920,21840, 10928,13648, 10936,30032, 10952,19792, 10960,11600, 10968,27984, + 10984,23888, 10992,15696, 11000,32080, 11016,17232, 11032,25424, 11048,21328, + 11056,13136, 11064,29520, 11080,19280, 11096,27472, 11112,23376, 11120,15184, + 11128,31568, 11144,18256, 11160,26448, 11176,22352, 11184,14160, 11192,30544, + 11208,20304, 11216,12112, 11224,28496, 11240,24400, 11248,16208, 11256,32592, + 11272,16592, 11288,24784, 11304,20688, 11312,12496, 11320,28880, 11336,18640, + 11352,26832, 11368,22736, 11376,14544, 11384,30928, 11400,17616, 11416,25808, + 11432,21712, 11440,13520, 11448,29904, 11464,19664, 11480,27856, 11496,23760, + 11504,15568, 11512,31952, 11528,17104, 11544,25296, 11560,21200, 11568,13008, + 11576,29392, 11592,19152, 11608,27344, 11624,23248, 11632,15056, 11640,31440, + 11656,18128, 11672,26320, 11688,22224, 11696,14032, 11704,30416, 11720,20176, + 11728,11984, 11736,28368, 11752,24272, 11760,16080, 11768,32464, 11784,16848, + 11800,25040, 11816,20944, 11824,12752, 11832,29136, 11848,18896, 11864,27088, + 11880,22992, 11888,14800, 11896,31184, 11912,17872, 11928,26064, 11944,21968, + 11952,13776, 11960,30160, 11976,19920, 11992,28112, 12008,24016, 12016,15824, + 12024,32208, 12040,17360, 12056,25552, 12072,21456, 12080,13264, 12088,29648, + 12104,19408, 12120,27600, 12136,23504, 12144,15312, 12152,31696, 12168,18384, + 12184,26576, 12200,22480, 12208,14288, 12216,30672, 12232,20432, 12248,28624, + 12264,24528, 12272,16336, 12280,32720, 12296,16432, 12312,24624, 12328,20528, + 12344,28720, 12360,18480, 12376,26672, 12392,22576, 12400,14384, 12408,30768, + 12424,17456, 12440,25648, 12456,21552, 12464,13360, 12472,29744, 12488,19504, + 12504,27696, 12520,23600, 12528,15408, 12536,31792, 12552,16944, 12568,25136, + 12584,21040, 12592,12848, 12600,29232, 12616,18992, 12632,27184, 12648,23088, + 12656,14896, 12664,31280, 12680,17968, 12696,26160, 12712,22064, 12720,13872, + 12728,30256, 12744,20016, 12760,28208, 12776,24112, 12784,15920, 12792,32304, + 12808,16688, 12824,24880, 12840,20784, 12856,28976, 12872,18736, 12888,26928, + 12904,22832, 12912,14640, 12920,31024, 12936,17712, 12952,25904, 12968,21808, + 12976,13616, 12984,30000, 13000,19760, 13016,27952, 13032,23856, 13040,15664, + 13048,32048, 13064,17200, 13080,25392, 13096,21296, 13112,29488, 13128,19248, + 13144,27440, 13160,23344, 13168,15152, 13176,31536, 13192,18224, 13208,26416, + 13224,22320, 13232,14128, 13240,30512, 13256,20272, 13272,28464, 13288,24368, + 13296,16176, 13304,32560, 13320,16560, 13336,24752, 13352,20656, 13368,28848, + 13384,18608, 13400,26800, 13416,22704, 13424,14512, 13432,30896, 13448,17584, + 13464,25776, 13480,21680, 13496,29872, 13512,19632, 13528,27824, 13544,23728, + 13552,15536, 13560,31920, 13576,17072, 13592,25264, 13608,21168, 13624,29360, + 13640,19120, 13656,27312, 13672,23216, 13680,15024, 13688,31408, 13704,18096, + 13720,26288, 13736,22192, 13744,14000, 13752,30384, 13768,20144, 13784,28336, + 13800,24240, 13808,16048, 13816,32432, 13832,16816, 13848,25008, 13864,20912, + 13880,29104, 13896,18864, 13912,27056, 13928,22960, 13936,14768, 13944,31152, + 13960,17840, 13976,26032, 13992,21936, 14008,30128, 14024,19888, 14040,28080, + 14056,23984, 14064,15792, 14072,32176, 14088,17328, 14104,25520, 14120,21424, + 14136,29616, 14152,19376, 14168,27568, 14184,23472, 14192,15280, 14200,31664, + 14216,18352, 14232,26544, 14248,22448, 14264,30640, 14280,20400, 14296,28592, + 14312,24496, 14320,16304, 14328,32688, 14344,16496, 14360,24688, 14376,20592, + 14392,28784, 14408,18544, 14424,26736, 14440,22640, 14456,30832, 14472,17520, + 14488,25712, 14504,21616, 14520,29808, 14536,19568, 14552,27760, 14568,23664, + 14576,15472, 14584,31856, 14600,17008, 14616,25200, 14632,21104, 14648,29296, + 14664,19056, 14680,27248, 14696,23152, 14704,14960, 14712,31344, 14728,18032, + 14744,26224, 14760,22128, 14776,30320, 14792,20080, 14808,28272, 14824,24176, + 14832,15984, 14840,32368, 14856,16752, 14872,24944, 14888,20848, 14904,29040, + 14920,18800, 14936,26992, 14952,22896, 14968,31088, 14984,17776, 15000,25968, + 15016,21872, 15032,30064, 15048,19824, 15064,28016, 15080,23920, 15088,15728, + 15096,32112, 15112,17264, 15128,25456, 15144,21360, 15160,29552, 15176,19312, + 15192,27504, 15208,23408, 15224,31600, 15240,18288, 15256,26480, 15272,22384, + 15288,30576, 15304,20336, 15320,28528, 15336,24432, 15344,16240, 15352,32624, + 15368,16624, 15384,24816, 15400,20720, 15416,28912, 15432,18672, 15448,26864, + 15464,22768, 15480,30960, 15496,17648, 15512,25840, 15528,21744, 15544,29936, + 15560,19696, 15576,27888, 15592,23792, 15608,31984, 15624,17136, 15640,25328, + 15656,21232, 15672,29424, 15688,19184, 15704,27376, 15720,23280, 15736,31472, + 15752,18160, 15768,26352, 15784,22256, 15800,30448, 15816,20208, 15832,28400, + 15848,24304, 15856,16112, 15864,32496, 15880,16880, 15896,25072, 15912,20976, + 15928,29168, 15944,18928, 15960,27120, 15976,23024, 15992,31216, 16008,17904, + 16024,26096, 16040,22000, 16056,30192, 16072,19952, 16088,28144, 16104,24048, + 16120,32240, 16136,17392, 16152,25584, 16168,21488, 16184,29680, 16200,19440, + 16216,27632, 16232,23536, 16248,31728, 16264,18416, 16280,26608, 16296,22512, + 16312,30704, 16328,20464, 16344,28656, 16360,24560, 16376,32752, 16408,24584, + 16424,20488, 16440,28680, 16456,18440, 16472,26632, 16488,22536, 16504,30728, + 16520,17416, 16536,25608, 16552,21512, 16568,29704, 16584,19464, 16600,27656, + 16616,23560, 16632,31752, 16648,16904, 16664,25096, 16680,21000, 16696,29192, + 16712,18952, 16728,27144, 16744,23048, 16760,31240, 16776,17928, 16792,26120, + 16808,22024, 16824,30216, 16840,19976, 16856,28168, 16872,24072, 16888,32264, + 16920,24840, 16936,20744, 16952,28936, 16968,18696, 16984,26888, 17000,22792, + 17016,30984, 17032,17672, 17048,25864, 17064,21768, 17080,29960, 17096,19720, + 17112,27912, 17128,23816, 17144,32008, 17176,25352, 17192,21256, 17208,29448, + 17224,19208, 17240,27400, 17256,23304, 17272,31496, 17288,18184, 17304,26376, + 17320,22280, 17336,30472, 17352,20232, 17368,28424, 17384,24328, 17400,32520, + 17432,24712, 17448,20616, 17464,28808, 17480,18568, 17496,26760, 17512,22664, + 17528,30856, 17560,25736, 17576,21640, 17592,29832, 17608,19592, 17624,27784, + 17640,23688, 17656,31880, 17688,25224, 17704,21128, 17720,29320, 17736,19080, + 17752,27272, 17768,23176, 17784,31368, 17800,18056, 17816,26248, 17832,22152, + 17848,30344, 17864,20104, 17880,28296, 17896,24200, 17912,32392, 17944,24968, + 17960,20872, 17976,29064, 17992,18824, 18008,27016, 18024,22920, 18040,31112, + 18072,25992, 18088,21896, 18104,30088, 18120,19848, 18136,28040, 18152,23944, + 18168,32136, 18200,25480, 18216,21384, 18232,29576, 18248,19336, 18264,27528, + 18280,23432, 18296,31624, 18328,26504, 18344,22408, 18360,30600, 18376,20360, + 18392,28552, 18408,24456, 18424,32648, 18456,24648, 18472,20552, 18488,28744, + 18520,26696, 18536,22600, 18552,30792, 18584,25672, 18600,21576, 18616,29768, + 18632,19528, 18648,27720, 18664,23624, 18680,31816, 18712,25160, 18728,21064, + 18744,29256, 18760,19016, 18776,27208, 18792,23112, 18808,31304, 18840,26184, + 18856,22088, 18872,30280, 18888,20040, 18904,28232, 18920,24136, 18936,32328, + 18968,24904, 18984,20808, 19000,29000, 19032,26952, 19048,22856, 19064,31048, + 19096,25928, 19112,21832, 19128,30024, 19144,19784, 19160,27976, 19176,23880, + 19192,32072, 19224,25416, 19240,21320, 19256,29512, 19288,27464, 19304,23368, + 19320,31560, 19352,26440, 19368,22344, 19384,30536, 19400,20296, 19416,28488, + 19432,24392, 19448,32584, 19480,24776, 19496,20680, 19512,28872, 19544,26824, + 19560,22728, 19576,30920, 19608,25800, 19624,21704, 19640,29896, 19672,27848, + 19688,23752, 19704,31944, 19736,25288, 19752,21192, 19768,29384, 19800,27336, + 19816,23240, 19832,31432, 19864,26312, 19880,22216, 19896,30408, 19912,20168, + 19928,28360, 19944,24264, 19960,32456, 19992,25032, 20008,20936, 20024,29128, + 20056,27080, 20072,22984, 20088,31176, 20120,26056, 20136,21960, 20152,30152, + 20184,28104, 20200,24008, 20216,32200, 20248,25544, 20264,21448, 20280,29640, + 20312,27592, 20328,23496, 20344,31688, 20376,26568, 20392,22472, 20408,30664, + 20440,28616, 20456,24520, 20472,32712, 20504,24616, 20536,28712, 20568,26664, + 20584,22568, 20600,30760, 20632,25640, 20648,21544, 20664,29736, 20696,27688, + 20712,23592, 20728,31784, 20760,25128, 20776,21032, 20792,29224, 20824,27176, + 20840,23080, 20856,31272, 20888,26152, 20904,22056, 20920,30248, 20952,28200, + 20968,24104, 20984,32296, 21016,24872, 21048,28968, 21080,26920, 21096,22824, + 21112,31016, 21144,25896, 21160,21800, 21176,29992, 21208,27944, 21224,23848, + 21240,32040, 21272,25384, 21304,29480, 21336,27432, 21352,23336, 21368,31528, + 21400,26408, 21416,22312, 21432,30504, 21464,28456, 21480,24360, 21496,32552, + 21528,24744, 21560,28840, 21592,26792, 21608,22696, 21624,30888, 21656,25768, + 21688,29864, 21720,27816, 21736,23720, 21752,31912, 21784,25256, 21816,29352, + 21848,27304, 21864,23208, 21880,31400, 21912,26280, 21928,22184, 21944,30376, + 21976,28328, 21992,24232, 22008,32424, 22040,25000, 22072,29096, 22104,27048, + 22120,22952, 22136,31144, 22168,26024, 22200,30120, 22232,28072, 22248,23976, + 22264,32168, 22296,25512, 22328,29608, 22360,27560, 22376,23464, 22392,31656, + 22424,26536, 22456,30632, 22488,28584, 22504,24488, 22520,32680, 22552,24680, + 22584,28776, 22616,26728, 22648,30824, 22680,25704, 22712,29800, 22744,27752, + 22760,23656, 22776,31848, 22808,25192, 22840,29288, 22872,27240, 22888,23144, + 22904,31336, 22936,26216, 22968,30312, 23000,28264, 23016,24168, 23032,32360, + 23064,24936, 23096,29032, 23128,26984, 23160,31080, 23192,25960, 23224,30056, + 23256,28008, 23272,23912, 23288,32104, 23320,25448, 23352,29544, 23384,27496, + 23416,31592, 23448,26472, 23480,30568, 23512,28520, 23528,24424, 23544,32616, + 23576,24808, 23608,28904, 23640,26856, 23672,30952, 23704,25832, 23736,29928, + 23768,27880, 23800,31976, 23832,25320, 23864,29416, 23896,27368, 23928,31464, + 23960,26344, 23992,30440, 24024,28392, 24040,24296, 24056,32488, 24088,25064, + 24120,29160, 24152,27112, 24184,31208, 24216,26088, 24248,30184, 24280,28136, + 24312,32232, 24344,25576, 24376,29672, 24408,27624, 24440,31720, 24472,26600, + 24504,30696, 24536,28648, 24568,32744, 24632,28696, 24664,26648, 24696,30744, + 24728,25624, 24760,29720, 24792,27672, 24824,31768, 24856,25112, 24888,29208, + 24920,27160, 24952,31256, 24984,26136, 25016,30232, 25048,28184, 25080,32280, + 25144,28952, 25176,26904, 25208,31000, 25240,25880, 25272,29976, 25304,27928, + 25336,32024, 25400,29464, 25432,27416, 25464,31512, 25496,26392, 25528,30488, + 25560,28440, 25592,32536, 25656,28824, 25688,26776, 25720,30872, 25784,29848, + 25816,27800, 25848,31896, 25912,29336, 25944,27288, 25976,31384, 26008,26264, + 26040,30360, 26072,28312, 26104,32408, 26168,29080, 26200,27032, 26232,31128, + 26296,30104, 26328,28056, 26360,32152, 26424,29592, 26456,27544, 26488,31640, + 26552,30616, 26584,28568, 26616,32664, 26680,28760, 26744,30808, 26808,29784, + 26840,27736, 26872,31832, 26936,29272, 26968,27224, 27000,31320, 27064,30296, + 27096,28248, 27128,32344, 27192,29016, 27256,31064, 27320,30040, 27352,27992, + 27384,32088, 27448,29528, 27512,31576, 27576,30552, 27608,28504, 27640,32600, + 27704,28888, 27768,30936, 27832,29912, 27896,31960, 27960,29400, 28024,31448, + 28088,30424, 28120,28376, 28152,32472, 28216,29144, 28280,31192, 28344,30168, + 28408,32216, 28472,29656, 28536,31704, 28600,30680, 28664,32728, 28792,30776, + 28856,29752, 28920,31800, 28984,29240, 29048,31288, 29112,30264, 29176,32312, + 29304,31032, 29368,30008, 29432,32056, 29560,31544, 29624,30520, 29688,32568, + 29816,30904, 29944,31928, 30072,31416, 30136,30392, 30200,32440, 30328,31160, + 30456,32184, 30584,31672, 30712,32696, 30968,31864, 31096,31352, 31224,32376, + 31480,32120, 31736,32632, 32248,32504 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16) + +const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH] = +{ + /* 8x2, size 20 */ + 8,64, 24,72, 16,64, 40,80, 32,64, 56,88, 48,72, 88,104, 72,96, 104,112 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32) + +const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH] = +{ + /* 8x4, size 48 */ + 8,64, 16,128, 24,192, 32,64, 40,72, 48,136, 56,200, 64,128, 72,80, 88,208, + 80,144, 96,192, 104,208, 112,152, 120,216, 136,192, 144,160, 168,208, + 152,224, 176,208, 184,232, 216,240, 200,224, 232,240 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64) + +const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH] = +{ + /* radix 8, size 56 */ + 8,64, 16,128, 24,192, 32,256, 40,320, 48,384, 56,448, 80,136, 88,200, + 96,264, 104,328, 112,392, 120,456, 152,208, 160,272, 168,336, 176,400, + 184,464, 224,280, 232,344, 240,408, 248,472, 296,352, 304,416, 312,480, + 368,424, 376,488, 440,496 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128) + +const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH] = +{ + /* 8x2, size 208 */ + 8,512, 16,64, 24,576, 32,128, 40,640, 48,192, 56,704, 64,256, 72,768, + 80,320, 88,832, 96,384, 104,896, 112,448, 120,960, 128,512, 136,520, + 144,768, 152,584, 160,520, 168,648, 176,200, 184,712, 192,264, 200,776, + 208,328, 216,840, 224,392, 232,904, 240,456, 248,968, 264,528, 272,320, + 280,592, 288,768, 296,656, 304,328, 312,720, 328,784, 344,848, 352,400, + 360,912, 368,464, 376,976, 384,576, 392,536, 400,832, 408,600, 416,584, + 424,664, 432,840, 440,728, 448,592, 456,792, 464,848, 472,856, 480,600, + 488,920, 496,856, 504,984, 520,544, 528,576, 536,608, 552,672, 560,608, + 568,736, 576,768, 584,800, 592,832, 600,864, 608,800, 616,928, 624,864, + 632,992, 648,672, 656,896, 664,928, 688,904, 696,744, 704,896, 712,808, + 720,912, 728,872, 736,928, 744,936, 752,920, 760,1000, 776,800, 784,832, + 792,864, 808,904, 816,864, 824,920, 840,864, 856,880, 872,944, 888,1008, + 904,928, 912,960, 920,992, 944,968, 952,1000, 968,992, 984,1008 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256) + +const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH] = +{ + /* 8x4, size 440 */ + 8,512, 16,1024, 24,1536, 32,64, 40,576, 48,1088, 56,1600, 64,128, 72,640, + 80,1152, 88,1664, 96,192, 104,704, 112,1216, 120,1728, 128,256, 136,768, + 144,1280, 152,1792, 160,320, 168,832, 176,1344, 184,1856, 192,384, + 200,896, 208,1408, 216,1920, 224,448, 232,960, 240,1472, 248,1984, + 256,512, 264,520, 272,1032, 280,1544, 288,640, 296,584, 304,1096, 312,1608, + 320,768, 328,648, 336,1160, 344,1672, 352,896, 360,712, 368,1224, 376,1736, + 384,520, 392,776, 400,1288, 408,1800, 416,648, 424,840, 432,1352, 440,1864, + 448,776, 456,904, 464,1416, 472,1928, 480,904, 488,968, 496,1480, 504,1992, + 520,528, 512,1024, 528,1040, 536,1552, 544,1152, 552,592, 560,1104, + 568,1616, 576,1280, 584,656, 592,1168, 600,1680, 608,1408, 616,720, + 624,1232, 632,1744, 640,1032, 648,784, 656,1296, 664,1808, 672,1160, + 680,848, 688,1360, 696,1872, 704,1288, 712,912, 720,1424, 728,1936, + 736,1416, 744,976, 752,1488, 760,2000, 768,1536, 776,1552, 784,1048, + 792,1560, 800,1664, 808,1680, 816,1112, 824,1624, 832,1792, 840,1808, + 848,1176, 856,1688, 864,1920, 872,1936, 880,1240, 888,1752, 896,1544, + 904,1560, 912,1304, 920,1816, 928,1672, 936,1688, 944,1368, 952,1880, + 960,1800, 968,1816, 976,1432, 984,1944, 992,1928, 1000,1944, 1008,1496, + 1016,2008, 1032,1152, 1040,1056, 1048,1568, 1064,1408, 1072,1120, + 1080,1632, 1088,1536, 1096,1160, 1104,1184, 1112,1696, 1120,1552, + 1128,1416, 1136,1248, 1144,1760, 1160,1664, 1168,1312, 1176,1824, + 1184,1544, 1192,1920, 1200,1376, 1208,1888, 1216,1568, 1224,1672, + 1232,1440, 1240,1952, 1248,1560, 1256,1928, 1264,1504, 1272,2016, + 1288,1312, 1296,1408, 1304,1576, 1320,1424, 1328,1416, 1336,1640, + 1344,1792, 1352,1824, 1360,1920, 1368,1704, 1376,1800, 1384,1432, + 1392,1928, 1400,1768, 1416,1680, 1432,1832, 1440,1576, 1448,1936, + 1456,1832, 1464,1896, 1472,1808, 1480,1688, 1488,1936, 1496,1960, + 1504,1816, 1512,1944, 1520,1944, 1528,2024, 1560,1584, 1592,1648, + 1600,1792, 1608,1920, 1616,1800, 1624,1712, 1632,1808, 1640,1936, + 1648,1816, 1656,1776, 1672,1696, 1688,1840, 1704,1952, 1712,1928, + 1720,1904, 1728,1824, 1736,1952, 1744,1832, 1752,1968, 1760,1840, + 1768,1960, 1776,1944, 1784,2032, 1864,1872, 1848,1944, 1872,1888, + 1880,1904, 1888,1984, 1896,2000, 1912,2032, 1904,2016, 1976,2032, + 1960,1968, 2008,2032, 1992,2016, 2024,2032 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512) + +const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH] = +{ + /* radix 8, size 448 */ + 8,512, 16,1024, 24,1536, 32,2048, 40,2560, 48,3072, 56,3584, 72,576, + 80,1088, 88,1600, 96,2112, 104,2624, 112,3136, 120,3648, 136,640, 144,1152, + 152,1664, 160,2176, 168,2688, 176,3200, 184,3712, 200,704, 208,1216, + 216,1728, 224,2240, 232,2752, 240,3264, 248,3776, 264,768, 272,1280, + 280,1792, 288,2304, 296,2816, 304,3328, 312,3840, 328,832, 336,1344, + 344,1856, 352,2368, 360,2880, 368,3392, 376,3904, 392,896, 400,1408, + 408,1920, 416,2432, 424,2944, 432,3456, 440,3968, 456,960, 464,1472, + 472,1984, 480,2496, 488,3008, 496,3520, 504,4032, 528,1032, 536,1544, + 544,2056, 552,2568, 560,3080, 568,3592, 592,1096, 600,1608, 608,2120, + 616,2632, 624,3144, 632,3656, 656,1160, 664,1672, 672,2184, 680,2696, + 688,3208, 696,3720, 720,1224, 728,1736, 736,2248, 744,2760, 752,3272, + 760,3784, 784,1288, 792,1800, 800,2312, 808,2824, 816,3336, 824,3848, + 848,1352, 856,1864, 864,2376, 872,2888, 880,3400, 888,3912, 912,1416, + 920,1928, 928,2440, 936,2952, 944,3464, 952,3976, 976,1480, 984,1992, + 992,2504, 1000,3016, 1008,3528, 1016,4040, 1048,1552, 1056,2064, 1064,2576, + 1072,3088, 1080,3600, 1112,1616, 1120,2128, 1128,2640, 1136,3152, + 1144,3664, 1176,1680, 1184,2192, 1192,2704, 1200,3216, 1208,3728, + 1240,1744, 1248,2256, 1256,2768, 1264,3280, 1272,3792, 1304,1808, + 1312,2320, 1320,2832, 1328,3344, 1336,3856, 1368,1872, 1376,2384, + 1384,2896, 1392,3408, 1400,3920, 1432,1936, 1440,2448, 1448,2960, + 1456,3472, 1464,3984, 1496,2000, 1504,2512, 1512,3024, 1520,3536, + 1528,4048, 1568,2072, 1576,2584, 1584,3096, 1592,3608, 1632,2136, + 1640,2648, 1648,3160, 1656,3672, 1696,2200, 1704,2712, 1712,3224, + 1720,3736, 1760,2264, 1768,2776, 1776,3288, 1784,3800, 1824,2328, + 1832,2840, 1840,3352, 1848,3864, 1888,2392, 1896,2904, 1904,3416, + 1912,3928, 1952,2456, 1960,2968, 1968,3480, 1976,3992, 2016,2520, + 2024,3032, 2032,3544, 2040,4056, 2088,2592, 2096,3104, 2104,3616, + 2152,2656, 2160,3168, 2168,3680, 2216,2720, 2224,3232, 2232,3744, + 2280,2784, 2288,3296, 2296,3808, 2344,2848, 2352,3360, 2360,3872, + 2408,2912, 2416,3424, 2424,3936, 2472,2976, 2480,3488, 2488,4000, + 2536,3040, 2544,3552, 2552,4064, 2608,3112, 2616,3624, 2672,3176, + 2680,3688, 2736,3240, 2744,3752, 2800,3304, 2808,3816, 2864,3368, + 2872,3880, 2928,3432, 2936,3944, 2992,3496, 3000,4008, 3056,3560, + 3064,4072, 3128,3632, 3192,3696, 3256,3760, 3320,3824, 3384,3888, + 3448,3952, 3512,4016, 3576,4080 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024) + +const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH] = +{ + /* 8x2, size 1800 */ + 8,4096, 16,512, 24,4608, 32,1024, 40,5120, 48,1536, 56,5632, 64,2048, + 72,6144, 80,2560, 88,6656, 96,3072, 104,7168, 112,3584, 120,7680, 128,2048, + 136,4160, 144,576, 152,4672, 160,1088, 168,5184, 176,1600, 184,5696, + 192,2112, 200,6208, 208,2624, 216,6720, 224,3136, 232,7232, 240,3648, + 248,7744, 256,2048, 264,4224, 272,640, 280,4736, 288,1152, 296,5248, + 304,1664, 312,5760, 320,2176, 328,6272, 336,2688, 344,6784, 352,3200, + 360,7296, 368,3712, 376,7808, 384,2112, 392,4288, 400,704, 408,4800, + 416,1216, 424,5312, 432,1728, 440,5824, 448,2240, 456,6336, 464,2752, + 472,6848, 480,3264, 488,7360, 496,3776, 504,7872, 512,2048, 520,4352, + 528,768, 536,4864, 544,1280, 552,5376, 560,1792, 568,5888, 576,2304, + 584,6400, 592,2816, 600,6912, 608,3328, 616,7424, 624,3840, 632,7936, + 640,2176, 648,4416, 656,832, 664,4928, 672,1344, 680,5440, 688,1856, + 696,5952, 704,2368, 712,6464, 720,2880, 728,6976, 736,3392, 744,7488, + 752,3904, 760,8000, 768,2112, 776,4480, 784,896, 792,4992, 800,1408, + 808,5504, 816,1920, 824,6016, 832,2432, 840,6528, 848,2944, 856,7040, + 864,3456, 872,7552, 880,3968, 888,8064, 896,2240, 904,4544, 912,960, + 920,5056, 928,1472, 936,5568, 944,1984, 952,6080, 960,2496, 968,6592, + 976,3008, 984,7104, 992,3520, 1000,7616, 1008,4032, 1016,8128, 1024,4096, + 1032,4104, 1040,4352, 1048,4616, 1056,4104, 1064,5128, 1072,1544, + 1080,5640, 1088,2056, 1096,6152, 1104,2568, 1112,6664, 1120,3080, + 1128,7176, 1136,3592, 1144,7688, 1152,6144, 1160,4168, 1168,6400, + 1176,4680, 1184,6152, 1192,5192, 1200,1608, 1208,5704, 1216,2120, + 1224,6216, 1232,2632, 1240,6728, 1248,3144, 1256,7240, 1264,3656, + 1272,7752, 1280,4160, 1288,4232, 1296,4416, 1304,4744, 1312,4168, + 1320,5256, 1328,1672, 1336,5768, 1344,2184, 1352,6280, 1360,2696, + 1368,6792, 1376,3208, 1384,7304, 1392,3720, 1400,7816, 1408,6208, + 1416,4296, 1424,6464, 1432,4808, 1440,6216, 1448,5320, 1456,1736, + 1464,5832, 1472,2248, 1480,6344, 1488,2760, 1496,6856, 1504,3272, + 1512,7368, 1520,3784, 1528,7880, 1536,4224, 1544,4360, 1552,4480, + 1560,4872, 1568,4232, 1576,5384, 1584,1800, 1592,5896, 1600,2312, + 1608,6408, 1616,2824, 1624,6920, 1632,3336, 1640,7432, 1648,3848, + 1656,7944, 1664,6272, 1672,4424, 1680,6528, 1688,4936, 1696,6280, + 1704,5448, 1712,1864, 1720,5960, 1728,2376, 1736,6472, 1744,2888, + 1752,6984, 1760,3400, 1768,7496, 1776,3912, 1784,8008, 1792,4288, + 1800,4488, 1808,4544, 1816,5000, 1824,4296, 1832,5512, 1840,1928, + 1848,6024, 1856,2440, 1864,6536, 1872,2952, 1880,7048, 1888,3464, + 1896,7560, 1904,3976, 1912,8072, 1920,6336, 1928,4552, 1936,6592, + 1944,5064, 1952,6344, 1960,5576, 1968,1992, 1976,6088, 1984,2504, + 1992,6600, 2000,3016, 2008,7112, 2016,3528, 2024,7624, 2032,4040, + 2040,8136, 2056,4112, 2064,2112, 2072,4624, 2080,4352, 2088,5136, + 2096,4480, 2104,5648, 2120,6160, 2128,2576, 2136,6672, 2144,3088, + 2152,7184, 2160,3600, 2168,7696, 2176,2560, 2184,4176, 2192,2816, + 2200,4688, 2208,2568, 2216,5200, 2224,2824, 2232,5712, 2240,2576, + 2248,6224, 2256,2640, 2264,6736, 2272,3152, 2280,7248, 2288,3664, + 2296,7760, 2312,4240, 2320,2432, 2328,4752, 2336,6400, 2344,5264, + 2352,6528, 2360,5776, 2368,2816, 2376,6288, 2384,2704, 2392,6800, + 2400,3216, 2408,7312, 2416,3728, 2424,7824, 2432,2624, 2440,4304, + 2448,2880, 2456,4816, 2464,2632, 2472,5328, 2480,2888, 2488,5840, + 2496,2640, 2504,6352, 2512,2768, 2520,6864, 2528,3280, 2536,7376, + 2544,3792, 2552,7888, 2568,4368, 2584,4880, 2592,4416, 2600,5392, + 2608,4544, 2616,5904, 2632,6416, 2640,2832, 2648,6928, 2656,3344, + 2664,7440, 2672,3856, 2680,7952, 2696,4432, 2704,2944, 2712,4944, + 2720,4432, 2728,5456, 2736,2952, 2744,5968, 2752,2944, 2760,6480, + 2768,2896, 2776,6992, 2784,3408, 2792,7504, 2800,3920, 2808,8016, + 2824,4496, 2840,5008, 2848,6464, 2856,5520, 2864,6592, 2872,6032, + 2888,6544, 2896,2960, 2904,7056, 2912,3472, 2920,7568, 2928,3984, + 2936,8080, 2952,4560, 2960,3008, 2968,5072, 2976,6480, 2984,5584, + 2992,3016, 3000,6096, 3016,6608, 3032,7120, 3040,3536, 3048,7632, + 3056,4048, 3064,8144, 3072,4608, 3080,4120, 3088,4864, 3096,4632, + 3104,4616, 3112,5144, 3120,4872, 3128,5656, 3136,4624, 3144,6168, + 3152,4880, 3160,6680, 3168,4632, 3176,7192, 3184,3608, 3192,7704, + 3200,6656, 3208,4184, 3216,6912, 3224,4696, 3232,6664, 3240,5208, + 3248,6920, 3256,5720, 3264,6672, 3272,6232, 3280,6928, 3288,6744, + 3296,6680, 3304,7256, 3312,3672, 3320,7768, 3328,4672, 3336,4248, + 3344,4928, 3352,4760, 3360,4680, 3368,5272, 3376,4936, 3384,5784, + 3392,4688, 3400,6296, 3408,4944, 3416,6808, 3424,4696, 3432,7320, + 3440,3736, 3448,7832, 3456,6720, 3464,4312, 3472,6976, 3480,4824, + 3488,6728, 3496,5336, 3504,6984, 3512,5848, 3520,6736, 3528,6360, + 3536,6992, 3544,6872, 3552,6744, 3560,7384, 3568,3800, 3576,7896, + 3584,4736, 3592,4376, 3600,4992, 3608,4888, 3616,4744, 3624,5400, + 3632,5000, 3640,5912, 3648,4752, 3656,6424, 3664,5008, 3672,6936, + 3680,4760, 3688,7448, 3696,3864, 3704,7960, 3712,6784, 3720,4440, + 3728,7040, 3736,4952, 3744,6792, 3752,5464, 3760,7048, 3768,5976, + 3776,6800, 3784,6488, 3792,7056, 3800,7000, 3808,6808, 3816,7512, + 3824,3928, 3832,8024, 3840,4800, 3848,4504, 3856,5056, 3864,5016, + 3872,4808, 3880,5528, 3888,5064, 3896,6040, 3904,4816, 3912,6552, + 3920,5072, 3928,7064, 3936,4824, 3944,7576, 3952,3992, 3960,8088, + 3968,6848, 3976,4568, 3984,7104, 3992,5080, 4000,6856, 4008,5592, + 4016,7112, 4024,6104, 4032,6864, 4040,6616, 4048,7120, 4056,7128, + 4064,6872, 4072,7640, 4080,7128, 4088,8152, 4104,4128, 4112,4160, + 4120,4640, 4136,5152, 4144,4232, 4152,5664, 4160,4352, 4168,6176, + 4176,4416, 4184,6688, 4192,4616, 4200,7200, 4208,4744, 4216,7712, + 4224,4608, 4232,4616, 4240,4672, 4248,4704, 4256,4640, 4264,5216, + 4272,4704, 4280,5728, 4288,4864, 4296,6240, 4304,4928, 4312,6752, + 4320,4632, 4328,7264, 4336,4760, 4344,7776, 4360,4640, 4368,4416, + 4376,4768, 4384,6152, 4392,5280, 4400,6280, 4408,5792, 4424,6304, + 4440,6816, 4448,6664, 4456,7328, 4464,6792, 4472,7840, 4480,4624, + 4488,4632, 4496,4688, 4504,4832, 4512,6168, 4520,5344, 4528,6296, + 4536,5856, 4544,4880, 4552,6368, 4560,4944, 4568,6880, 4576,6680, + 4584,7392, 4592,6808, 4600,7904, 4608,6144, 4616,6152, 4624,6208, + 4632,4896, 4640,6176, 4648,5408, 4656,6240, 4664,5920, 4672,6400, + 4680,6432, 4688,6464, 4696,6944, 4704,6432, 4712,7456, 4720,4808, + 4728,7968, 4736,6656, 4744,6664, 4752,6720, 4760,4960, 4768,6688, + 4776,5472, 4784,6752, 4792,5984, 4800,6912, 4808,6496, 4816,6976, + 4824,7008, 4832,6944, 4840,7520, 4848,7008, 4856,8032, 4864,6160, + 4872,6168, 4880,6224, 4888,5024, 4896,6216, 4904,5536, 4912,6344, + 4920,6048, 4928,6416, 4936,6560, 4944,6480, 4952,7072, 4960,6728, + 4968,7584, 4976,6856, 4984,8096, 4992,6672, 5000,6680, 5008,6736, + 5016,5088, 5024,6232, 5032,5600, 5040,6360, 5048,6112, 5056,6928, + 5064,6624, 5072,6992, 5080,7136, 5088,6744, 5096,7648, 5104,6872, + 5112,8160, 5128,5152, 5136,5376, 5144,5408, 5168,5384, 5176,5672, + 5184,5376, 5192,6184, 5200,5392, 5208,6696, 5216,5408, 5224,7208, + 5232,5400, 5240,7720, 5248,7168, 5256,7200, 5264,7424, 5272,7456, + 5280,7176, 5288,7208, 5296,7432, 5304,5736, 5312,7184, 5320,6248, + 5328,7440, 5336,6760, 5344,7192, 5352,7272, 5360,7448, 5368,7784, + 5384,5408, 5392,5440, 5400,5472, 5408,6184, 5416,7208, 5424,5448, + 5432,5800, 5448,6312, 5464,6824, 5472,6696, 5480,7336, 5488,6824, + 5496,7848, 5504,7232, 5512,7264, 5520,7488, 5528,7520, 5536,7240, + 5544,7272, 5552,7496, 5560,5864, 5568,7248, 5576,6376, 5584,7504, + 5592,6888, 5600,7256, 5608,7400, 5616,7512, 5624,7912, 5632,7168, + 5640,7176, 5648,7232, 5656,7240, 5664,7200, 5672,7208, 5680,7264, + 5688,5928, 5696,7424, 5704,6440, 5712,7488, 5720,6952, 5728,7456, + 5736,7464, 5744,7520, 5752,7976, 5760,7296, 5768,7328, 5776,7552, + 5784,7584, 5792,7304, 5800,7336, 5808,7560, 5816,5992, 5824,7312, + 5832,6504, 5840,7568, 5848,7016, 5856,7320, 5864,7528, 5872,7576, + 5880,8040, 5888,7184, 5896,7192, 5904,7248, 5912,7256, 5920,6248, + 5928,7272, 5936,6376, 5944,6056, 5952,7440, 5960,6568, 5968,7504, + 5976,7080, 5984,6760, 5992,7592, 6000,6888, 6008,8104, 6016,7360, + 6024,7392, 6032,7616, 6040,7648, 6048,7368, 6056,7400, 6064,7624, + 6072,6120, 6080,7376, 6088,6632, 6096,7632, 6104,7144, 6112,7384, + 6120,7656, 6128,7640, 6136,8168, 6168,6240, 6192,6216, 6200,7264, + 6232,6704, 6248,7216, 6256,6680, 6264,7728, 6272,6656, 6280,6664, + 6288,6912, 6296,6496, 6304,6688, 6312,6696, 6320,6944, 6328,7520, + 6336,6672, 6344,6680, 6352,6928, 6360,6768, 6368,6704, 6376,7280, + 6384,6744, 6392,7792, 6408,6432, 6424,6752, 6440,7432, 6448,6536, + 6456,7560, 6472,6944, 6488,6832, 6496,6920, 6504,7344, 6512,7048, + 6520,7856, 6528,6720, 6536,6728, 6544,6976, 6552,7008, 6560,6752, + 6568,7448, 6576,7008, 6584,7576, 6592,6736, 6600,6744, 6608,6992, + 6616,6896, 6624,6936, 6632,7408, 6640,7064, 6648,7920, 6712,7280, + 6744,6960, 6760,7472, 6768,6936, 6776,7984, 6800,6848, 6808,6856, + 6832,6880, 6840,6888, 6848,7040, 6856,7048, 6864,7104, 6872,7024, + 6880,7072, 6888,7536, 6896,7136, 6904,8048, 6952,7496, 6968,7624, + 6984,7008, 7000,7088, 7016,7600, 7024,7112, 7032,8112, 7056,7104, + 7064,7112, 7080,7512, 7088,7136, 7096,7640, 7128,7152, 7144,7664, + 7160,8176, 7176,7200, 7192,7216, 7224,7272, 7240,7264, 7256,7280, + 7288,7736, 7296,7680, 7304,7712, 7312,7936, 7320,7968, 7328,7688, + 7336,7720, 7344,7944, 7352,7976, 7360,7696, 7368,7728, 7376,7952, + 7384,7984, 7392,7704, 7400,7736, 7408,7960, 7416,7800, 7432,7456, + 7448,7472, 7480,7592, 7496,7520, 7512,7536, 7528,7976, 7544,7864, + 7552,7744, 7560,7776, 7568,8000, 7576,8032, 7584,7752, 7592,7784, + 7600,8008, 7608,8040, 7616,7760, 7624,7792, 7632,8016, 7640,8048, + 7648,7768, 7656,7800, 7664,8024, 7672,7928, 7688,7712, 7704,7728, + 7752,7776, 7768,7792, 7800,7992, 7816,7840, 7824,8064, 7832,8096, + 7856,8072, 7864,8104, 7872,8064, 7880,8072, 7888,8080, 7896,8112, + 7904,8096, 7912,8104, 7920,8088, 7928,8056, 7944,7968, 7960,7984, + 8008,8032, 8024,8048, 8056,8120, 8072,8096, 8080,8128, 8088,8160, + 8112,8136, 8120,8168, 8136,8160, 8152,8176 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048) + +const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH] = +{ + /* 8x2, size 3808 */ + 8,4096, 16,8192, 24,12288, 32,512, 40,4608, 48,8704, 56,12800, 64,1024, + 72,5120, 80,9216, 88,13312, 96,1536, 104,5632, 112,9728, 120,13824, + 128,2048, 136,6144, 144,10240, 152,14336, 160,2560, 168,6656, 176,10752, + 184,14848, 192,3072, 200,7168, 208,11264, 216,15360, 224,3584, 232,7680, + 240,11776, 248,15872, 256,1024, 264,4160, 272,8256, 280,12352, 288,576, + 296,4672, 304,8768, 312,12864, 320,1088, 328,5184, 336,9280, 344,13376, + 352,1600, 360,5696, 368,9792, 376,13888, 384,2112, 392,6208, 400,10304, + 408,14400, 416,2624, 424,6720, 432,10816, 440,14912, 448,3136, 456,7232, + 464,11328, 472,15424, 480,3648, 488,7744, 496,11840, 504,15936, 512,2048, + 520,4224, 528,8320, 536,12416, 544,640, 552,4736, 560,8832, 568,12928, + 576,1152, 584,5248, 592,9344, 600,13440, 608,1664, 616,5760, 624,9856, + 632,13952, 640,2176, 648,6272, 656,10368, 664,14464, 672,2688, 680,6784, + 688,10880, 696,14976, 704,3200, 712,7296, 720,11392, 728,15488, 736,3712, + 744,7808, 752,11904, 760,16000, 768,3072, 776,4288, 784,8384, 792,12480, + 800,3200, 808,4800, 816,8896, 824,12992, 832,1216, 840,5312, 848,9408, + 856,13504, 864,1728, 872,5824, 880,9920, 888,14016, 896,2240, 904,6336, + 912,10432, 920,14528, 928,2752, 936,6848, 944,10944, 952,15040, 960,3264, + 968,7360, 976,11456, 984,15552, 992,3776, 1000,7872, 1008,11968, 1016,16064, + 1032,4352, 1040,8448, 1048,12544, 1056,3072, 1064,4864, 1072,8960, + 1080,13056, 1088,1280, 1096,5376, 1104,9472, 1112,13568, 1120,1792, + 1128,5888, 1136,9984, 1144,14080, 1152,2304, 1160,6400, 1168,10496, + 1176,14592, 1184,2816, 1192,6912, 1200,11008, 1208,15104, 1216,3328, + 1224,7424, 1232,11520, 1240,15616, 1248,3840, 1256,7936, 1264,12032, + 1272,16128, 1288,4416, 1296,8512, 1304,12608, 1312,3328, 1320,4928, + 1328,9024, 1336,13120, 1352,5440, 1360,9536, 1368,13632, 1376,1856, + 1384,5952, 1392,10048, 1400,14144, 1408,2368, 1416,6464, 1424,10560, + 1432,14656, 1440,2880, 1448,6976, 1456,11072, 1464,15168, 1472,3392, + 1480,7488, 1488,11584, 1496,15680, 1504,3904, 1512,8000, 1520,12096, + 1528,16192, 1536,2112, 1544,4480, 1552,8576, 1560,12672, 1568,2240, + 1576,4992, 1584,9088, 1592,13184, 1600,2368, 1608,5504, 1616,9600, + 1624,13696, 1632,1920, 1640,6016, 1648,10112, 1656,14208, 1664,2432, + 1672,6528, 1680,10624, 1688,14720, 1696,2944, 1704,7040, 1712,11136, + 1720,15232, 1728,3456, 1736,7552, 1744,11648, 1752,15744, 1760,3968, + 1768,8064, 1776,12160, 1784,16256, 1792,3136, 1800,4544, 1808,8640, + 1816,12736, 1824,3264, 1832,5056, 1840,9152, 1848,13248, 1856,3392, + 1864,5568, 1872,9664, 1880,13760, 1888,1984, 1896,6080, 1904,10176, + 1912,14272, 1920,2496, 1928,6592, 1936,10688, 1944,14784, 1952,3008, + 1960,7104, 1968,11200, 1976,15296, 1984,3520, 1992,7616, 2000,11712, + 2008,15808, 2016,4032, 2024,8128, 2032,12224, 2040,16320, 2048,4096, + 2056,4104, 2064,8200, 2072,12296, 2080,4224, 2088,4616, 2096,8712, + 2104,12808, 2112,4352, 2120,5128, 2128,9224, 2136,13320, 2144,4480, + 2152,5640, 2160,9736, 2168,13832, 2176,4104, 2184,6152, 2192,10248, + 2200,14344, 2208,2568, 2216,6664, 2224,10760, 2232,14856, 2240,3080, + 2248,7176, 2256,11272, 2264,15368, 2272,3592, 2280,7688, 2288,11784, + 2296,15880, 2304,5120, 2312,4168, 2320,8264, 2328,12360, 2336,5248, + 2344,4680, 2352,8776, 2360,12872, 2368,5376, 2376,5192, 2384,9288, + 2392,13384, 2400,5504, 2408,5704, 2416,9800, 2424,13896, 2432,5128, + 2440,6216, 2448,10312, 2456,14408, 2464,2632, 2472,6728, 2480,10824, + 2488,14920, 2496,3144, 2504,7240, 2512,11336, 2520,15432, 2528,3656, + 2536,7752, 2544,11848, 2552,15944, 2560,6144, 2568,4232, 2576,8328, + 2584,12424, 2592,6272, 2600,4744, 2608,8840, 2616,12936, 2624,6400, + 2632,5256, 2640,9352, 2648,13448, 2656,6528, 2664,5768, 2672,9864, + 2680,13960, 2688,6152, 2696,6280, 2704,10376, 2712,14472, 2720,6280, + 2728,6792, 2736,10888, 2744,14984, 2752,3208, 2760,7304, 2768,11400, + 2776,15496, 2784,3720, 2792,7816, 2800,11912, 2808,16008, 2816,7168, + 2824,4296, 2832,8392, 2840,12488, 2848,7296, 2856,4808, 2864,8904, + 2872,13000, 2880,7424, 2888,5320, 2896,9416, 2904,13512, 2912,7552, + 2920,5832, 2928,9928, 2936,14024, 2944,7176, 2952,6344, 2960,10440, + 2968,14536, 2976,7304, 2984,6856, 2992,10952, 3000,15048, 3008,3272, + 3016,7368, 3024,11464, 3032,15560, 3040,3784, 3048,7880, 3056,11976, + 3064,16072, 3072,4160, 3080,4360, 3088,8456, 3096,12552, 3104,4288, + 3112,4872, 3120,8968, 3128,13064, 3136,4416, 3144,5384, 3152,9480, + 3160,13576, 3168,4544, 3176,5896, 3184,9992, 3192,14088, 3200,4168, + 3208,6408, 3216,10504, 3224,14600, 3232,4296, 3240,6920, 3248,11016, + 3256,15112, 3264,3336, 3272,7432, 3280,11528, 3288,15624, 3296,3848, + 3304,7944, 3312,12040, 3320,16136, 3328,5184, 3336,4424, 3344,8520, + 3352,12616, 3360,5312, 3368,4936, 3376,9032, 3384,13128, 3392,5440, + 3400,5448, 3408,9544, 3416,13640, 3424,5568, 3432,5960, 3440,10056, + 3448,14152, 3456,5192, 3464,6472, 3472,10568, 3480,14664, 3488,5320, + 3496,6984, 3504,11080, 3512,15176, 3520,5448, 3528,7496, 3536,11592, + 3544,15688, 3552,3912, 3560,8008, 3568,12104, 3576,16200, 3584,6208, + 3592,4488, 3600,8584, 3608,12680, 3616,6336, 3624,5000, 3632,9096, + 3640,13192, 3648,6464, 3656,5512, 3664,9608, 3672,13704, 3680,6592, + 3688,6024, 3696,10120, 3704,14216, 3712,6216, 3720,6536, 3728,10632, + 3736,14728, 3744,6344, 3752,7048, 3760,11144, 3768,15240, 3776,6472, + 3784,7560, 3792,11656, 3800,15752, 3808,3976, 3816,8072, 3824,12168, + 3832,16264, 3840,7232, 3848,4552, 3856,8648, 3864,12744, 3872,7360, + 3880,5064, 3888,9160, 3896,13256, 3904,7488, 3912,5576, 3920,9672, + 3928,13768, 3936,7616, 3944,6088, 3952,10184, 3960,14280, 3968,7240, + 3976,6600, 3984,10696, 3992,14792, 4000,7368, 4008,7112, 4016,11208, + 4024,15304, 4032,7496, 4040,7624, 4048,11720, 4056,15816, 4064,7624, + 4072,8136, 4080,12232, 4088,16328, 4096,8192, 4104,4112, 4112,8208, + 4120,12304, 4128,8320, 4136,4624, 4144,8720, 4152,12816, 4160,8448, + 4168,5136, 4176,9232, 4184,13328, 4192,8576, 4200,5648, 4208,9744, + 4216,13840, 4224,8200, 4232,6160, 4240,10256, 4248,14352, 4256,8328, + 4264,6672, 4272,10768, 4280,14864, 4288,8456, 4296,7184, 4304,11280, + 4312,15376, 4320,8584, 4328,7696, 4336,11792, 4344,15888, 4352,9216, + 4360,9232, 4368,8272, 4376,12368, 4384,9344, 4392,4688, 4400,8784, + 4408,12880, 4416,9472, 4424,5200, 4432,9296, 4440,13392, 4448,9600, + 4456,5712, 4464,9808, 4472,13904, 4480,9224, 4488,6224, 4496,10320, + 4504,14416, 4512,9352, 4520,6736, 4528,10832, 4536,14928, 4544,9480, + 4552,7248, 4560,11344, 4568,15440, 4576,9608, 4584,7760, 4592,11856, + 4600,15952, 4608,10240, 4616,10256, 4624,8336, 4632,12432, 4640,10368, + 4648,4752, 4656,8848, 4664,12944, 4672,10496, 4680,5264, 4688,9360, + 4696,13456, 4704,10624, 4712,5776, 4720,9872, 4728,13968, 4736,10248, + 4744,6288, 4752,10384, 4760,14480, 4768,10376, 4776,6800, 4784,10896, + 4792,14992, 4800,10504, 4808,7312, 4816,11408, 4824,15504, 4832,10632, + 4840,7824, 4848,11920, 4856,16016, 4864,11264, 4872,11280, 4880,8400, + 4888,12496, 4896,11392, 4904,11408, 4912,8912, 4920,13008, 4928,11520, + 4936,5328, 4944,9424, 4952,13520, 4960,11648, 4968,5840, 4976,9936, + 4984,14032, 4992,11272, 5000,6352, 5008,10448, 5016,14544, 5024,11400, + 5032,6864, 5040,10960, 5048,15056, 5056,11528, 5064,7376, 5072,11472, + 5080,15568, 5088,11656, 5096,7888, 5104,11984, 5112,16080, 5120,8256, + 5128,8272, 5136,8464, 5144,12560, 5152,8384, 5160,8400, 5168,8976, + 5176,13072, 5184,8512, 5192,5392, 5200,9488, 5208,13584, 5216,8640, + 5224,5904, 5232,10000, 5240,14096, 5248,8264, 5256,6416, 5264,10512, + 5272,14608, 5280,8392, 5288,6928, 5296,11024, 5304,15120, 5312,8520, + 5320,7440, 5328,11536, 5336,15632, 5344,8648, 5352,7952, 5360,12048, + 5368,16144, 5376,9280, 5384,9296, 5392,8528, 5400,12624, 5408,9408, + 5416,9424, 5424,9040, 5432,13136, 5440,9536, 5448,5456, 5456,9552, + 5464,13648, 5472,9664, 5480,5968, 5488,10064, 5496,14160, 5504,9288, + 5512,6480, 5520,10576, 5528,14672, 5536,9416, 5544,6992, 5552,11088, + 5560,15184, 5568,9544, 5576,7504, 5584,11600, 5592,15696, 5600,9672, + 5608,8016, 5616,12112, 5624,16208, 5632,10304, 5640,10320, 5648,8592, + 5656,12688, 5664,10432, 5672,10448, 5680,9104, 5688,13200, 5696,10560, + 5704,10576, 5712,9616, 5720,13712, 5728,10688, 5736,6032, 5744,10128, + 5752,14224, 5760,10312, 5768,6544, 5776,10640, 5784,14736, 5792,10440, + 5800,7056, 5808,11152, 5816,15248, 5824,10568, 5832,7568, 5840,11664, + 5848,15760, 5856,10696, 5864,8080, 5872,12176, 5880,16272, 5888,11328, + 5896,11344, 5904,8656, 5912,12752, 5920,11456, 5928,11472, 5936,9168, + 5944,13264, 5952,11584, 5960,11600, 5968,9680, 5976,13776, 5984,11712, + 5992,6096, 6000,10192, 6008,14288, 6016,11336, 6024,6608, 6032,10704, + 6040,14800, 6048,11464, 6056,7120, 6064,11216, 6072,15312, 6080,11592, + 6088,7632, 6096,11728, 6104,15824, 6112,11720, 6120,8144, 6128,12240, + 6136,16336, 6144,12288, 6152,12304, 6160,8216, 6168,12312, 6176,12416, + 6184,12432, 6192,8728, 6200,12824, 6208,12544, 6216,12560, 6224,9240, + 6232,13336, 6240,12672, 6248,12688, 6256,9752, 6264,13848, 6272,12296, + 6280,12312, 6288,10264, 6296,14360, 6304,12424, 6312,6680, 6320,10776, + 6328,14872, 6336,12552, 6344,7192, 6352,11288, 6360,15384, 6368,12680, + 6376,7704, 6384,11800, 6392,15896, 6400,13312, 6408,13328, 6416,8280, + 6424,12376, 6432,13440, 6440,13456, 6448,8792, 6456,12888, 6464,13568, + 6472,13584, 6480,9304, 6488,13400, 6496,13696, 6504,13712, 6512,9816, + 6520,13912, 6528,13320, 6536,13336, 6544,10328, 6552,14424, 6560,13448, + 6568,6744, 6576,10840, 6584,14936, 6592,13576, 6600,7256, 6608,11352, + 6616,15448, 6624,13704, 6632,7768, 6640,11864, 6648,15960, 6656,14336, + 6664,14352, 6672,8344, 6680,12440, 6688,14464, 6696,14480, 6704,8856, + 6712,12952, 6720,14592, 6728,14608, 6736,9368, 6744,13464, 6752,14720, + 6760,14736, 6768,9880, 6776,13976, 6784,14344, 6792,14360, 6800,10392, + 6808,14488, 6816,14472, 6824,14488, 6832,10904, 6840,15000, 6848,14600, + 6856,7320, 6864,11416, 6872,15512, 6880,14728, 6888,7832, 6896,11928, + 6904,16024, 6912,15360, 6920,15376, 6928,8408, 6936,12504, 6944,15488, + 6952,15504, 6960,8920, 6968,13016, 6976,15616, 6984,15632, 6992,9432, + 7000,13528, 7008,15744, 7016,15760, 7024,9944, 7032,14040, 7040,15368, + 7048,15384, 7056,10456, 7064,14552, 7072,15496, 7080,15512, 7088,10968, + 7096,15064, 7104,15624, 7112,7384, 7120,11480, 7128,15576, 7136,15752, + 7144,7896, 7152,11992, 7160,16088, 7168,12352, 7176,12368, 7184,8472, + 7192,12568, 7200,12480, 7208,12496, 7216,8984, 7224,13080, 7232,12608, + 7240,12624, 7248,9496, 7256,13592, 7264,12736, 7272,12752, 7280,10008, + 7288,14104, 7296,12360, 7304,12376, 7312,10520, 7320,14616, 7328,12488, + 7336,12504, 7344,11032, 7352,15128, 7360,12616, 7368,7448, 7376,11544, + 7384,15640, 7392,12744, 7400,7960, 7408,12056, 7416,16152, 7424,13376, + 7432,13392, 7440,8536, 7448,12632, 7456,13504, 7464,13520, 7472,9048, + 7480,13144, 7488,13632, 7496,13648, 7504,9560, 7512,13656, 7520,13760, + 7528,13776, 7536,10072, 7544,14168, 7552,13384, 7560,13400, 7568,10584, + 7576,14680, 7584,13512, 7592,13528, 7600,11096, 7608,15192, 7616,13640, + 7624,13656, 7632,11608, 7640,15704, 7648,13768, 7656,8024, 7664,12120, + 7672,16216, 7680,14400, 7688,14416, 7696,8600, 7704,12696, 7712,14528, + 7720,14544, 7728,9112, 7736,13208, 7744,14656, 7752,14672, 7760,9624, + 7768,13720, 7776,14784, 7784,14800, 7792,10136, 7800,14232, 7808,14408, + 7816,14424, 7824,10648, 7832,14744, 7840,14536, 7848,14552, 7856,11160, + 7864,15256, 7872,14664, 7880,14680, 7888,11672, 7896,15768, 7904,14792, + 7912,8088, 7920,12184, 7928,16280, 7936,15424, 7944,15440, 7952,8664, + 7960,12760, 7968,15552, 7976,15568, 7984,9176, 7992,13272, 8000,15680, + 8008,15696, 8016,9688, 8024,13784, 8032,15808, 8040,15824, 8048,10200, + 8056,14296, 8064,15432, 8072,15448, 8080,10712, 8088,14808, 8096,15560, + 8104,15576, 8112,11224, 8120,15320, 8128,15688, 8136,15704, 8144,11736, + 8152,15832, 8160,15816, 8168,15832, 8176,12248, 8184,16344, 8200,8320, + 8208,8224, 8216,12320, 8232,10368, 8240,8736, 8248,12832, 8256,8448, + 8264,8384, 8272,9248, 8280,13344, 8288,9232, 8296,10432, 8304,9760, + 8312,13856, 8328,12416, 8336,10272, 8344,14368, 8352,12296, 8360,14464, + 8368,10784, 8376,14880, 8384,8456, 8392,12480, 8400,11296, 8408,15392, + 8416,12552, 8424,14528, 8432,11808, 8440,15904, 8448,9216, 8456,8576, + 8464,9232, 8472,12384, 8480,9248, 8488,10624, 8496,8800, 8504,12896, + 8512,9472, 8520,8640, 8528,9312, 8536,13408, 8544,9296, 8552,10688, + 8560,9824, 8568,13920, 8576,9224, 8584,12672, 8592,10336, 8600,14432, + 8608,13320, 8616,14720, 8624,10848, 8632,14944, 8640,9480, 8648,12736, + 8656,11360, 8664,15456, 8672,13576, 8680,14784, 8688,11872, 8696,15968, + 8704,12288, 8712,12416, 8720,12296, 8728,12448, 8736,12304, 8744,10376, + 8752,8864, 8760,12960, 8768,12352, 8776,12480, 8784,9376, 8792,13472, + 8800,12368, 8808,10440, 8816,9888, 8824,13984, 8832,12320, 8840,12424, + 8848,10400, 8856,14496, 8864,12312, 8872,14472, 8880,10912, 8888,15008, + 8896,12384, 8904,12488, 8912,11424, 8920,15520, 8928,12568, 8936,14536, + 8944,11936, 8952,16032, 8960,12544, 8968,12672, 8976,12552, 8984,12512, + 8992,12560, 9000,10632, 9008,12568, 9016,13024, 9024,12608, 9032,12736, + 9040,9440, 9048,13536, 9056,12624, 9064,10696, 9072,9952, 9080,14048, + 9088,9240, 9096,12680, 9104,10464, 9112,14560, 9120,13336, 9128,14728, + 9136,10976, 9144,15072, 9152,9496, 9160,12744, 9168,11488, 9176,15584, + 9184,13592, 9192,14792, 9200,12000, 9208,16096, 9224,9344, 9232,9248, + 9240,12576, 9256,11392, 9264,12560, 9272,13088, 9280,9472, 9288,9408, + 9296,9504, 9304,13600, 9312,9488, 9320,11456, 9328,10016, 9336,14112, + 9352,13440, 9360,10528, 9368,14624, 9376,12360, 9384,15488, 9392,11040, + 9400,15136, 9408,9480, 9416,13504, 9424,11552, 9432,15648, 9440,12616, + 9448,15552, 9456,12064, 9464,16160, 9480,9600, 9488,9504, 9496,12640, + 9512,11648, 9520,12624, 9528,13152, 9544,9664, 9552,9568, 9560,13664, + 9576,11712, 9584,10080, 9592,14176, 9608,13696, 9616,10592, 9624,14688, + 9632,13384, 9640,15744, 9648,11104, 9656,15200, 9672,13760, 9680,11616, + 9688,15712, 9696,13640, 9704,15808, 9712,12128, 9720,16224, 9728,13312, + 9736,13440, 9744,13320, 9752,12704, 9760,13328, 9768,11400, 9776,13336, + 9784,13216, 9792,13376, 9800,13504, 9808,13384, 9816,13728, 9824,13392, + 9832,11464, 9840,10144, 9848,14240, 9856,13344, 9864,13448, 9872,10656, + 9880,14752, 9888,12376, 9896,15496, 9904,11168, 9912,15264, 9920,13408, + 9928,13512, 9936,11680, 9944,15776, 9952,12632, 9960,15560, 9968,12192, + 9976,16288, 9984,13568, 9992,13696, 10000,13576, 10008,12768, 10016,13584, + 10024,11656, 10032,13592, 10040,13280, 10048,13632, 10056,13760, + 10064,13640, 10072,13792, 10080,13648, 10088,11720, 10096,10208, + 10104,14304, 10112,13600, 10120,13704, 10128,10720, 10136,14816, + 10144,13400, 10152,15752, 10160,11232, 10168,15328, 10176,13664, + 10184,13768, 10192,11744, 10200,15840, 10208,13656, 10216,15816, + 10224,12256, 10232,16352, 10248,10272, 10256,10368, 10264,12328, + 10280,10384, 10288,10376, 10296,12840, 10304,11264, 10312,11296, + 10320,11392, 10328,13352, 10336,11272, 10344,10448, 10352,11400, + 10360,13864, 10376,12432, 10392,14376, 10400,12328, 10408,14480, + 10416,10792, 10424,14888, 10432,11280, 10440,12496, 10448,11304, + 10456,15400, 10464,11288, 10472,14544, 10480,11816, 10488,15912, + 10496,11264, 10504,11272, 10512,11280, 10520,12392, 10528,11296, + 10536,10640, 10544,12496, 10552,12904, 10560,11328, 10568,11360, + 10576,11456, 10584,13416, 10592,11336, 10600,10704, 10608,11464, + 10616,13928, 10624,11392, 10632,12688, 10640,11304, 10648,14440, + 10656,13352, 10664,14736, 10672,10856, 10680,14952, 10688,11344, + 10696,12752, 10704,11368, 10712,15464, 10720,11352, 10728,14800, + 10736,11880, 10744,15976, 10752,14336, 10760,14368, 10768,14464, + 10776,12456, 10784,14344, 10792,14376, 10800,14472, 10808,12968, + 10816,15360, 10824,15392, 10832,15488, 10840,13480, 10848,15368, + 10856,15400, 10864,15496, 10872,13992, 10880,14352, 10888,12440, + 10896,14480, 10904,14504, 10912,14360, 10920,14488, 10928,14488, + 10936,15016, 10944,15376, 10952,12504, 10960,11432, 10968,15528, + 10976,15384, 10984,14552, 10992,11944, 11000,16040, 11008,14400, + 11016,14432, 11024,14528, 11032,12520, 11040,14408, 11048,14440, + 11056,14536, 11064,13032, 11072,15424, 11080,15456, 11088,15552, + 11096,13544, 11104,15432, 11112,15464, 11120,15560, 11128,14056, + 11136,14416, 11144,12696, 11152,14544, 11160,14568, 11168,14424, + 11176,14744, 11184,14552, 11192,15080, 11200,15440, 11208,12760, + 11216,11496, 11224,15592, 11232,15448, 11240,14808, 11248,12008, + 11256,16104, 11272,11296, 11280,11392, 11288,12584, 11304,11408, + 11312,12688, 11320,13096, 11328,11520, 11336,11552, 11344,11648, + 11352,13608, 11360,11528, 11368,11472, 11376,11656, 11384,14120, + 11400,13456, 11416,14632, 11424,12392, 11432,15504, 11440,14440, + 11448,15144, 11456,11536, 11464,13520, 11472,11560, 11480,15656, + 11488,11544, 11496,15568, 11504,12072, 11512,16168, 11528,11552, + 11536,11648, 11544,12648, 11560,11664, 11568,12752, 11576,13160, + 11592,11616, 11600,11712, 11608,13672, 11624,11728, 11632,11720, + 11640,14184, 11656,13712, 11672,14696, 11680,13416, 11688,15760, + 11696,15464, 11704,15208, 11720,13776, 11736,15720, 11744,13672, + 11752,15824, 11760,12136, 11768,16232, 11776,14592, 11784,14624, + 11792,14720, 11800,12712, 11808,14600, 11816,14632, 11824,14728, + 11832,13224, 11840,15616, 11848,15648, 11856,15744, 11864,13736, + 11872,15624, 11880,15656, 11888,15752, 11896,14248, 11904,14608, + 11912,13464, 11920,14736, 11928,14760, 11936,14616, 11944,15512, + 11952,14744, 11960,15272, 11968,15632, 11976,13528, 11984,15760, + 11992,15784, 12000,15640, 12008,15576, 12016,12200, 12024,16296, + 12032,14656, 12040,14688, 12048,14784, 12056,12776, 12064,14664, + 12072,14696, 12080,14792, 12088,13288, 12096,15680, 12104,15712, + 12112,15808, 12120,13800, 12128,15688, 12136,15720, 12144,15816, + 12152,14312, 12160,14672, 12168,13720, 12176,14800, 12184,14824, + 12192,14680, 12200,15768, 12208,14808, 12216,15336, 12224,15696, + 12232,13784, 12240,15824, 12248,15848, 12256,15704, 12264,15832, + 12272,15832, 12280,16360, 12312,12336, 12344,12848, 12352,12544, + 12360,12552, 12368,12560, 12376,13360, 12384,12576, 12392,12584, + 12400,13336, 12408,13872, 12424,12448, 12440,14384, 12456,14496, + 12464,14472, 12472,14896, 12480,12672, 12488,12512, 12496,12688, + 12504,15408, 12512,12680, 12520,14560, 12528,14728, 12536,15920, + 12544,13312, 12552,13320, 12560,13328, 12568,13336, 12576,13344, + 12584,13352, 12592,13360, 12600,12912, 12608,13568, 12616,13576, + 12624,13584, 12632,13424, 12640,13600, 12648,13608, 12656,13400, + 12664,13936, 12672,13440, 12680,12704, 12688,13456, 12696,14448, + 12704,13448, 12712,14752, 12720,15496, 12728,14960, 12736,13696, + 12744,12768, 12752,13712, 12760,15472, 12768,13704, 12776,14816, + 12784,15752, 12792,15984, 12800,14336, 12808,14464, 12816,14344, + 12824,14472, 12832,14352, 12840,14480, 12848,14360, 12856,12976, + 12864,14400, 12872,14528, 12880,14408, 12888,13488, 12896,14416, + 12904,14544, 12912,14424, 12920,14000, 12928,14368, 12936,14496, + 12944,14376, 12952,14512, 12960,14384, 12968,14504, 12976,14488, + 12984,15024, 12992,14432, 13000,14560, 13008,14440, 13016,15536, + 13024,14448, 13032,14568, 13040,14744, 13048,16048, 13056,14592, + 13064,14720, 13072,14600, 13080,14728, 13088,14608, 13096,14736, + 13104,14616, 13112,14744, 13120,14656, 13128,14784, 13136,14664, + 13144,13552, 13152,14672, 13160,14800, 13168,14680, 13176,14064, + 13184,14624, 13192,14752, 13200,14632, 13208,14576, 13216,13464, + 13224,14760, 13232,15512, 13240,15088, 13248,14688, 13256,14816, + 13264,14696, 13272,15600, 13280,13720, 13288,14824, 13296,15768, + 13304,16112, 13336,13360, 13368,14616, 13376,13568, 13384,13576, + 13392,13584, 13400,13616, 13408,13600, 13416,13608, 13424,13592, + 13432,14128, 13448,13472, 13464,14640, 13480,15520, 13488,14536, + 13496,15152, 13504,13696, 13512,13536, 13520,13712, 13528,15664, + 13536,13704, 13544,15584, 13552,14792, 13560,16176, 13592,13616, + 13624,14680, 13656,13680, 13688,14192, 13704,13728, 13720,14704, + 13736,15776, 13744,15560, 13752,15216, 13768,13792, 13784,15728, + 13800,15840, 13808,15816, 13816,16240, 13824,15360, 13832,15488, + 13840,15368, 13848,15496, 13856,15376, 13864,15504, 13872,15384, + 13880,15512, 13888,15424, 13896,15552, 13904,15432, 13912,15560, + 13920,15440, 13928,15568, 13936,15448, 13944,14256, 13952,15392, + 13960,15520, 13968,15400, 13976,14768, 13984,15408, 13992,15528, + 14000,14552, 14008,15280, 14016,15456, 14024,15584, 14032,15464, + 14040,15792, 14048,15472, 14056,15592, 14064,14808, 14072,16304, + 14080,15616, 14088,15744, 14096,15624, 14104,15752, 14112,15632, + 14120,15760, 14128,15640, 14136,15768, 14144,15680, 14152,15808, + 14160,15688, 14168,15816, 14176,15696, 14184,15824, 14192,15704, + 14200,14320, 14208,15648, 14216,15776, 14224,15656, 14232,14832, + 14240,15664, 14248,15784, 14256,15576, 14264,15344, 14272,15712, + 14280,15840, 14288,15720, 14296,15856, 14304,15728, 14312,15848, + 14320,15832, 14328,16368, 14392,14488, 14400,14592, 14408,14600, + 14416,14608, 14424,14616, 14432,14624, 14440,14632, 14448,14640, + 14456,15512, 14504,14512, 14520,14904, 14528,14720, 14536,14728, + 14544,14736, 14552,15416, 14560,14752, 14568,14576, 14584,15928, + 14576,14760, 14592,15360, 14600,15368, 14608,15376, 14616,15384, + 14624,15392, 14632,15400, 14640,15408, 14648,15416, 14656,15616, + 14664,15624, 14672,15632, 14680,15640, 14688,15648, 14696,15656, + 14704,15664, 14712,15576, 14720,15488, 14728,15496, 14736,15504, + 14744,15512, 14752,15520, 14760,14768, 14776,14968, 14768,15528, + 14784,15744, 14792,15752, 14800,15760, 14808,15480, 14816,15776, + 14824,14832, 14840,15992, 14832,15784, 14856,14864, 14864,14880, + 14872,14896, 14880,14976, 14888,14992, 14896,15008, 14904,15024, + 14912,15104, 14920,15120, 14928,15136, 14936,15152, 14944,15232, + 14952,15248, 14960,15264, 14968,15280, 14984,15008, 15000,15024, + 15016,15024, 15040,15112, 15048,15128, 15056,15144, 15064,15544, + 15072,15240, 15080,15256, 15088,15272, 15096,16056, 15104,15872, + 15112,15888, 15120,15904, 15128,15920, 15136,16000, 15144,16016, + 15152,16032, 15160,16048, 15168,16128, 15176,16144, 15184,16160, + 15192,16176, 15200,16256, 15208,16272, 15216,16288, 15224,16304, + 15232,15880, 15240,15896, 15248,15912, 15256,15928, 15264,16008, + 15272,16024, 15280,16040, 15288,16056, 15296,16136, 15304,16152, + 15312,16168, 15320,15608, 15328,16264, 15336,16280, 15344,16296, + 15352,16120, 15416,15512, 15424,15616, 15432,15624, 15440,15632, + 15448,15640, 15456,15648, 15464,15656, 15472,15664, 15480,15768, + 15528,15536, 15544,16048, 15552,15744, 15560,15752, 15568,15760, + 15576,15672, 15584,15776, 15592,15600, 15600,15784, 15608,16184, + 15672,15768, 15736,15832, 15784,15792, 15800,16304, 15848,15856, + 15880,16000, 15864,16248, 15888,16000, 15896,16008, 15904,16000, + 15912,16016, 15920,16008, 15928,16024, 15936,16128, 15944,16160, + 15952,16256, 15960,16288, 15968,16136, 15976,16168, 15984,16264, + 15992,16296, 16008,16032, 16024,16040, 16064,16144, 16040,16048, + 16072,16176, 16080,16272, 16088,16304, 16096,16152, 16104,16184, + 16112,16280, 16136,16256, 16120,16312, 16144,16256, 16152,16264, + 16160,16256, 16168,16272, 16176,16264, 16184,16280, 16200,16208, + 16208,16224, 16216,16240, 16224,16320, 16232,16336, 16240,16352, + 16248,16368, 16264,16288, 16280,16296, 16296,16304, 16344,16368, + 16328,16352, 16360,16368 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096) + +const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH] = +{ + /* radix 8, size 4032 */ + 8,4096, 16,8192, 24,12288, 32,16384, 40,20480, 48,24576, 56,28672, 64,512, + 72,4608, 80,8704, 88,12800, 96,16896, 104,20992, 112,25088, 120,29184, + 128,1024, 136,5120, 144,9216, 152,13312, 160,17408, 168,21504, 176,25600, + 184,29696, 192,1536, 200,5632, 208,9728, 216,13824, 224,17920, 232,22016, + 240,26112, 248,30208, 256,2048, 264,6144, 272,10240, 280,14336, 288,18432, + 296,22528, 304,26624, 312,30720, 320,2560, 328,6656, 336,10752, 344,14848, + 352,18944, 360,23040, 368,27136, 376,31232, 384,3072, 392,7168, 400,11264, + 408,15360, 416,19456, 424,23552, 432,27648, 440,31744, 448,3584, 456,7680, + 464,11776, 472,15872, 480,19968, 488,24064, 496,28160, 504,32256, 520,4160, + 528,8256, 536,12352, 544,16448, 552,20544, 560,24640, 568,28736, 584,4672, + 592,8768, 600,12864, 608,16960, 616,21056, 624,25152, 632,29248, 640,1088, + 648,5184, 656,9280, 664,13376, 672,17472, 680,21568, 688,25664, 696,29760, + 704,1600, 712,5696, 720,9792, 728,13888, 736,17984, 744,22080, 752,26176, + 760,30272, 768,2112, 776,6208, 784,10304, 792,14400, 800,18496, 808,22592, + 816,26688, 824,30784, 832,2624, 840,6720, 848,10816, 856,14912, 864,19008, + 872,23104, 880,27200, 888,31296, 896,3136, 904,7232, 912,11328, 920,15424, + 928,19520, 936,23616, 944,27712, 952,31808, 960,3648, 968,7744, 976,11840, + 984,15936, 992,20032, 1000,24128, 1008,28224, 1016,32320, 1032,4224, + 1040,8320, 1048,12416, 1056,16512, 1064,20608, 1072,24704, 1080,28800, + 1096,4736, 1104,8832, 1112,12928, 1120,17024, 1128,21120, 1136,25216, + 1144,29312, 1160,5248, 1168,9344, 1176,13440, 1184,17536, 1192,21632, + 1200,25728, 1208,29824, 1216,1664, 1224,5760, 1232,9856, 1240,13952, + 1248,18048, 1256,22144, 1264,26240, 1272,30336, 1280,2176, 1288,6272, + 1296,10368, 1304,14464, 1312,18560, 1320,22656, 1328,26752, 1336,30848, + 1344,2688, 1352,6784, 1360,10880, 1368,14976, 1376,19072, 1384,23168, + 1392,27264, 1400,31360, 1408,3200, 1416,7296, 1424,11392, 1432,15488, + 1440,19584, 1448,23680, 1456,27776, 1464,31872, 1472,3712, 1480,7808, + 1488,11904, 1496,16000, 1504,20096, 1512,24192, 1520,28288, 1528,32384, + 1544,4288, 1552,8384, 1560,12480, 1568,16576, 1576,20672, 1584,24768, + 1592,28864, 1608,4800, 1616,8896, 1624,12992, 1632,17088, 1640,21184, + 1648,25280, 1656,29376, 1672,5312, 1680,9408, 1688,13504, 1696,17600, + 1704,21696, 1712,25792, 1720,29888, 1736,5824, 1744,9920, 1752,14016, + 1760,18112, 1768,22208, 1776,26304, 1784,30400, 1792,2240, 1800,6336, + 1808,10432, 1816,14528, 1824,18624, 1832,22720, 1840,26816, 1848,30912, + 1856,2752, 1864,6848, 1872,10944, 1880,15040, 1888,19136, 1896,23232, + 1904,27328, 1912,31424, 1920,3264, 1928,7360, 1936,11456, 1944,15552, + 1952,19648, 1960,23744, 1968,27840, 1976,31936, 1984,3776, 1992,7872, + 2000,11968, 2008,16064, 2016,20160, 2024,24256, 2032,28352, 2040,32448, + 2056,4352, 2064,8448, 2072,12544, 2080,16640, 2088,20736, 2096,24832, + 2104,28928, 2120,4864, 2128,8960, 2136,13056, 2144,17152, 2152,21248, + 2160,25344, 2168,29440, 2184,5376, 2192,9472, 2200,13568, 2208,17664, + 2216,21760, 2224,25856, 2232,29952, 2248,5888, 2256,9984, 2264,14080, + 2272,18176, 2280,22272, 2288,26368, 2296,30464, 2312,6400, 2320,10496, + 2328,14592, 2336,18688, 2344,22784, 2352,26880, 2360,30976, 2368,2816, + 2376,6912, 2384,11008, 2392,15104, 2400,19200, 2408,23296, 2416,27392, + 2424,31488, 2432,3328, 2440,7424, 2448,11520, 2456,15616, 2464,19712, + 2472,23808, 2480,27904, 2488,32000, 2496,3840, 2504,7936, 2512,12032, + 2520,16128, 2528,20224, 2536,24320, 2544,28416, 2552,32512, 2568,4416, + 2576,8512, 2584,12608, 2592,16704, 2600,20800, 2608,24896, 2616,28992, + 2632,4928, 2640,9024, 2648,13120, 2656,17216, 2664,21312, 2672,25408, + 2680,29504, 2696,5440, 2704,9536, 2712,13632, 2720,17728, 2728,21824, + 2736,25920, 2744,30016, 2760,5952, 2768,10048, 2776,14144, 2784,18240, + 2792,22336, 2800,26432, 2808,30528, 2824,6464, 2832,10560, 2840,14656, + 2848,18752, 2856,22848, 2864,26944, 2872,31040, 2888,6976, 2896,11072, + 2904,15168, 2912,19264, 2920,23360, 2928,27456, 2936,31552, 2944,3392, + 2952,7488, 2960,11584, 2968,15680, 2976,19776, 2984,23872, 2992,27968, + 3000,32064, 3008,3904, 3016,8000, 3024,12096, 3032,16192, 3040,20288, + 3048,24384, 3056,28480, 3064,32576, 3080,4480, 3088,8576, 3096,12672, + 3104,16768, 3112,20864, 3120,24960, 3128,29056, 3144,4992, 3152,9088, + 3160,13184, 3168,17280, 3176,21376, 3184,25472, 3192,29568, 3208,5504, + 3216,9600, 3224,13696, 3232,17792, 3240,21888, 3248,25984, 3256,30080, + 3272,6016, 3280,10112, 3288,14208, 3296,18304, 3304,22400, 3312,26496, + 3320,30592, 3336,6528, 3344,10624, 3352,14720, 3360,18816, 3368,22912, + 3376,27008, 3384,31104, 3400,7040, 3408,11136, 3416,15232, 3424,19328, + 3432,23424, 3440,27520, 3448,31616, 3464,7552, 3472,11648, 3480,15744, + 3488,19840, 3496,23936, 3504,28032, 3512,32128, 3520,3968, 3528,8064, + 3536,12160, 3544,16256, 3552,20352, 3560,24448, 3568,28544, 3576,32640, + 3592,4544, 3600,8640, 3608,12736, 3616,16832, 3624,20928, 3632,25024, + 3640,29120, 3656,5056, 3664,9152, 3672,13248, 3680,17344, 3688,21440, + 3696,25536, 3704,29632, 3720,5568, 3728,9664, 3736,13760, 3744,17856, + 3752,21952, 3760,26048, 3768,30144, 3784,6080, 3792,10176, 3800,14272, + 3808,18368, 3816,22464, 3824,26560, 3832,30656, 3848,6592, 3856,10688, + 3864,14784, 3872,18880, 3880,22976, 3888,27072, 3896,31168, 3912,7104, + 3920,11200, 3928,15296, 3936,19392, 3944,23488, 3952,27584, 3960,31680, + 3976,7616, 3984,11712, 3992,15808, 4000,19904, 4008,24000, 4016,28096, + 4024,32192, 4040,8128, 4048,12224, 4056,16320, 4064,20416, 4072,24512, + 4080,28608, 4088,32704, 4112,8200, 4120,12296, 4128,16392, 4136,20488, + 4144,24584, 4152,28680, 4168,4616, 4176,8712, 4184,12808, 4192,16904, + 4200,21000, 4208,25096, 4216,29192, 4232,5128, 4240,9224, 4248,13320, + 4256,17416, 4264,21512, 4272,25608, 4280,29704, 4296,5640, 4304,9736, + 4312,13832, 4320,17928, 4328,22024, 4336,26120, 4344,30216, 4360,6152, + 4368,10248, 4376,14344, 4384,18440, 4392,22536, 4400,26632, 4408,30728, + 4424,6664, 4432,10760, 4440,14856, 4448,18952, 4456,23048, 4464,27144, + 4472,31240, 4488,7176, 4496,11272, 4504,15368, 4512,19464, 4520,23560, + 4528,27656, 4536,31752, 4552,7688, 4560,11784, 4568,15880, 4576,19976, + 4584,24072, 4592,28168, 4600,32264, 4624,8264, 4632,12360, 4640,16456, + 4648,20552, 4656,24648, 4664,28744, 4688,8776, 4696,12872, 4704,16968, + 4712,21064, 4720,25160, 4728,29256, 4744,5192, 4752,9288, 4760,13384, + 4768,17480, 4776,21576, 4784,25672, 4792,29768, 4808,5704, 4816,9800, + 4824,13896, 4832,17992, 4840,22088, 4848,26184, 4856,30280, 4872,6216, + 4880,10312, 4888,14408, 4896,18504, 4904,22600, 4912,26696, 4920,30792, + 4936,6728, 4944,10824, 4952,14920, 4960,19016, 4968,23112, 4976,27208, + 4984,31304, 5000,7240, 5008,11336, 5016,15432, 5024,19528, 5032,23624, + 5040,27720, 5048,31816, 5064,7752, 5072,11848, 5080,15944, 5088,20040, + 5096,24136, 5104,28232, 5112,32328, 5136,8328, 5144,12424, 5152,16520, + 5160,20616, 5168,24712, 5176,28808, 5200,8840, 5208,12936, 5216,17032, + 5224,21128, 5232,25224, 5240,29320, 5264,9352, 5272,13448, 5280,17544, + 5288,21640, 5296,25736, 5304,29832, 5320,5768, 5328,9864, 5336,13960, + 5344,18056, 5352,22152, 5360,26248, 5368,30344, 5384,6280, 5392,10376, + 5400,14472, 5408,18568, 5416,22664, 5424,26760, 5432,30856, 5448,6792, + 5456,10888, 5464,14984, 5472,19080, 5480,23176, 5488,27272, 5496,31368, + 5512,7304, 5520,11400, 5528,15496, 5536,19592, 5544,23688, 5552,27784, + 5560,31880, 5576,7816, 5584,11912, 5592,16008, 5600,20104, 5608,24200, + 5616,28296, 5624,32392, 5648,8392, 5656,12488, 5664,16584, 5672,20680, + 5680,24776, 5688,28872, 5712,8904, 5720,13000, 5728,17096, 5736,21192, + 5744,25288, 5752,29384, 5776,9416, 5784,13512, 5792,17608, 5800,21704, + 5808,25800, 5816,29896, 5840,9928, 5848,14024, 5856,18120, 5864,22216, + 5872,26312, 5880,30408, 5896,6344, 5904,10440, 5912,14536, 5920,18632, + 5928,22728, 5936,26824, 5944,30920, 5960,6856, 5968,10952, 5976,15048, + 5984,19144, 5992,23240, 6000,27336, 6008,31432, 6024,7368, 6032,11464, + 6040,15560, 6048,19656, 6056,23752, 6064,27848, 6072,31944, 6088,7880, + 6096,11976, 6104,16072, 6112,20168, 6120,24264, 6128,28360, 6136,32456, + 6160,8456, 6168,12552, 6176,16648, 6184,20744, 6192,24840, 6200,28936, + 6224,8968, 6232,13064, 6240,17160, 6248,21256, 6256,25352, 6264,29448, + 6288,9480, 6296,13576, 6304,17672, 6312,21768, 6320,25864, 6328,29960, + 6352,9992, 6360,14088, 6368,18184, 6376,22280, 6384,26376, 6392,30472, + 6416,10504, 6424,14600, 6432,18696, 6440,22792, 6448,26888, 6456,30984, + 6472,6920, 6480,11016, 6488,15112, 6496,19208, 6504,23304, 6512,27400, + 6520,31496, 6536,7432, 6544,11528, 6552,15624, 6560,19720, 6568,23816, + 6576,27912, 6584,32008, 6600,7944, 6608,12040, 6616,16136, 6624,20232, + 6632,24328, 6640,28424, 6648,32520, 6672,8520, 6680,12616, 6688,16712, + 6696,20808, 6704,24904, 6712,29000, 6736,9032, 6744,13128, 6752,17224, + 6760,21320, 6768,25416, 6776,29512, 6800,9544, 6808,13640, 6816,17736, + 6824,21832, 6832,25928, 6840,30024, 6864,10056, 6872,14152, 6880,18248, + 6888,22344, 6896,26440, 6904,30536, 6928,10568, 6936,14664, 6944,18760, + 6952,22856, 6960,26952, 6968,31048, 6992,11080, 7000,15176, 7008,19272, + 7016,23368, 7024,27464, 7032,31560, 7048,7496, 7056,11592, 7064,15688, + 7072,19784, 7080,23880, 7088,27976, 7096,32072, 7112,8008, 7120,12104, + 7128,16200, 7136,20296, 7144,24392, 7152,28488, 7160,32584, 7184,8584, + 7192,12680, 7200,16776, 7208,20872, 7216,24968, 7224,29064, 7248,9096, + 7256,13192, 7264,17288, 7272,21384, 7280,25480, 7288,29576, 7312,9608, + 7320,13704, 7328,17800, 7336,21896, 7344,25992, 7352,30088, 7376,10120, + 7384,14216, 7392,18312, 7400,22408, 7408,26504, 7416,30600, 7440,10632, + 7448,14728, 7456,18824, 7464,22920, 7472,27016, 7480,31112, 7504,11144, + 7512,15240, 7520,19336, 7528,23432, 7536,27528, 7544,31624, 7568,11656, + 7576,15752, 7584,19848, 7592,23944, 7600,28040, 7608,32136, 7624,8072, + 7632,12168, 7640,16264, 7648,20360, 7656,24456, 7664,28552, 7672,32648, + 7696,8648, 7704,12744, 7712,16840, 7720,20936, 7728,25032, 7736,29128, + 7760,9160, 7768,13256, 7776,17352, 7784,21448, 7792,25544, 7800,29640, + 7824,9672, 7832,13768, 7840,17864, 7848,21960, 7856,26056, 7864,30152, + 7888,10184, 7896,14280, 7904,18376, 7912,22472, 7920,26568, 7928,30664, + 7952,10696, 7960,14792, 7968,18888, 7976,22984, 7984,27080, 7992,31176, + 8016,11208, 8024,15304, 8032,19400, 8040,23496, 8048,27592, 8056,31688, + 8080,11720, 8088,15816, 8096,19912, 8104,24008, 8112,28104, 8120,32200, + 8144,12232, 8152,16328, 8160,20424, 8168,24520, 8176,28616, 8184,32712, + 8216,12304, 8224,16400, 8232,20496, 8240,24592, 8248,28688, 8272,8720, + 8280,12816, 8288,16912, 8296,21008, 8304,25104, 8312,29200, 8336,9232, + 8344,13328, 8352,17424, 8360,21520, 8368,25616, 8376,29712, 8400,9744, + 8408,13840, 8416,17936, 8424,22032, 8432,26128, 8440,30224, 8464,10256, + 8472,14352, 8480,18448, 8488,22544, 8496,26640, 8504,30736, 8528,10768, + 8536,14864, 8544,18960, 8552,23056, 8560,27152, 8568,31248, 8592,11280, + 8600,15376, 8608,19472, 8616,23568, 8624,27664, 8632,31760, 8656,11792, + 8664,15888, 8672,19984, 8680,24080, 8688,28176, 8696,32272, 8728,12368, + 8736,16464, 8744,20560, 8752,24656, 8760,28752, 8792,12880, 8800,16976, + 8808,21072, 8816,25168, 8824,29264, 8848,9296, 8856,13392, 8864,17488, + 8872,21584, 8880,25680, 8888,29776, 8912,9808, 8920,13904, 8928,18000, + 8936,22096, 8944,26192, 8952,30288, 8976,10320, 8984,14416, 8992,18512, + 9000,22608, 9008,26704, 9016,30800, 9040,10832, 9048,14928, 9056,19024, + 9064,23120, 9072,27216, 9080,31312, 9104,11344, 9112,15440, 9120,19536, + 9128,23632, 9136,27728, 9144,31824, 9168,11856, 9176,15952, 9184,20048, + 9192,24144, 9200,28240, 9208,32336, 9240,12432, 9248,16528, 9256,20624, + 9264,24720, 9272,28816, 9304,12944, 9312,17040, 9320,21136, 9328,25232, + 9336,29328, 9368,13456, 9376,17552, 9384,21648, 9392,25744, 9400,29840, + 9424,9872, 9432,13968, 9440,18064, 9448,22160, 9456,26256, 9464,30352, + 9488,10384, 9496,14480, 9504,18576, 9512,22672, 9520,26768, 9528,30864, + 9552,10896, 9560,14992, 9568,19088, 9576,23184, 9584,27280, 9592,31376, + 9616,11408, 9624,15504, 9632,19600, 9640,23696, 9648,27792, 9656,31888, + 9680,11920, 9688,16016, 9696,20112, 9704,24208, 9712,28304, 9720,32400, + 9752,12496, 9760,16592, 9768,20688, 9776,24784, 9784,28880, 9816,13008, + 9824,17104, 9832,21200, 9840,25296, 9848,29392, 9880,13520, 9888,17616, + 9896,21712, 9904,25808, 9912,29904, 9944,14032, 9952,18128, 9960,22224, + 9968,26320, 9976,30416, 10000,10448, 10008,14544, 10016,18640, 10024,22736, + 10032,26832, 10040,30928, 10064,10960, 10072,15056, 10080,19152, + 10088,23248, 10096,27344, 10104,31440, 10128,11472, 10136,15568, + 10144,19664, 10152,23760, 10160,27856, 10168,31952, 10192,11984, + 10200,16080, 10208,20176, 10216,24272, 10224,28368, 10232,32464, + 10264,12560, 10272,16656, 10280,20752, 10288,24848, 10296,28944, + 10328,13072, 10336,17168, 10344,21264, 10352,25360, 10360,29456, + 10392,13584, 10400,17680, 10408,21776, 10416,25872, 10424,29968, + 10456,14096, 10464,18192, 10472,22288, 10480,26384, 10488,30480, + 10520,14608, 10528,18704, 10536,22800, 10544,26896, 10552,30992, + 10576,11024, 10584,15120, 10592,19216, 10600,23312, 10608,27408, + 10616,31504, 10640,11536, 10648,15632, 10656,19728, 10664,23824, + 10672,27920, 10680,32016, 10704,12048, 10712,16144, 10720,20240, + 10728,24336, 10736,28432, 10744,32528, 10776,12624, 10784,16720, + 10792,20816, 10800,24912, 10808,29008, 10840,13136, 10848,17232, + 10856,21328, 10864,25424, 10872,29520, 10904,13648, 10912,17744, + 10920,21840, 10928,25936, 10936,30032, 10968,14160, 10976,18256, + 10984,22352, 10992,26448, 11000,30544, 11032,14672, 11040,18768, + 11048,22864, 11056,26960, 11064,31056, 11096,15184, 11104,19280, + 11112,23376, 11120,27472, 11128,31568, 11152,11600, 11160,15696, + 11168,19792, 11176,23888, 11184,27984, 11192,32080, 11216,12112, + 11224,16208, 11232,20304, 11240,24400, 11248,28496, 11256,32592, + 11288,12688, 11296,16784, 11304,20880, 11312,24976, 11320,29072, + 11352,13200, 11360,17296, 11368,21392, 11376,25488, 11384,29584, + 11416,13712, 11424,17808, 11432,21904, 11440,26000, 11448,30096, + 11480,14224, 11488,18320, 11496,22416, 11504,26512, 11512,30608, + 11544,14736, 11552,18832, 11560,22928, 11568,27024, 11576,31120, + 11608,15248, 11616,19344, 11624,23440, 11632,27536, 11640,31632, + 11672,15760, 11680,19856, 11688,23952, 11696,28048, 11704,32144, + 11728,12176, 11736,16272, 11744,20368, 11752,24464, 11760,28560, + 11768,32656, 11800,12752, 11808,16848, 11816,20944, 11824,25040, + 11832,29136, 11864,13264, 11872,17360, 11880,21456, 11888,25552, + 11896,29648, 11928,13776, 11936,17872, 11944,21968, 11952,26064, + 11960,30160, 11992,14288, 12000,18384, 12008,22480, 12016,26576, + 12024,30672, 12056,14800, 12064,18896, 12072,22992, 12080,27088, + 12088,31184, 12120,15312, 12128,19408, 12136,23504, 12144,27600, + 12152,31696, 12184,15824, 12192,19920, 12200,24016, 12208,28112, + 12216,32208, 12248,16336, 12256,20432, 12264,24528, 12272,28624, + 12280,32720, 12320,16408, 12328,20504, 12336,24600, 12344,28696, + 12376,12824, 12384,16920, 12392,21016, 12400,25112, 12408,29208, + 12440,13336, 12448,17432, 12456,21528, 12464,25624, 12472,29720, + 12504,13848, 12512,17944, 12520,22040, 12528,26136, 12536,30232, + 12568,14360, 12576,18456, 12584,22552, 12592,26648, 12600,30744, + 12632,14872, 12640,18968, 12648,23064, 12656,27160, 12664,31256, + 12696,15384, 12704,19480, 12712,23576, 12720,27672, 12728,31768, + 12760,15896, 12768,19992, 12776,24088, 12784,28184, 12792,32280, + 12832,16472, 12840,20568, 12848,24664, 12856,28760, 12896,16984, + 12904,21080, 12912,25176, 12920,29272, 12952,13400, 12960,17496, + 12968,21592, 12976,25688, 12984,29784, 13016,13912, 13024,18008, + 13032,22104, 13040,26200, 13048,30296, 13080,14424, 13088,18520, + 13096,22616, 13104,26712, 13112,30808, 13144,14936, 13152,19032, + 13160,23128, 13168,27224, 13176,31320, 13208,15448, 13216,19544, + 13224,23640, 13232,27736, 13240,31832, 13272,15960, 13280,20056, + 13288,24152, 13296,28248, 13304,32344, 13344,16536, 13352,20632, + 13360,24728, 13368,28824, 13408,17048, 13416,21144, 13424,25240, + 13432,29336, 13472,17560, 13480,21656, 13488,25752, 13496,29848, + 13528,13976, 13536,18072, 13544,22168, 13552,26264, 13560,30360, + 13592,14488, 13600,18584, 13608,22680, 13616,26776, 13624,30872, + 13656,15000, 13664,19096, 13672,23192, 13680,27288, 13688,31384, + 13720,15512, 13728,19608, 13736,23704, 13744,27800, 13752,31896, + 13784,16024, 13792,20120, 13800,24216, 13808,28312, 13816,32408, + 13856,16600, 13864,20696, 13872,24792, 13880,28888, 13920,17112, + 13928,21208, 13936,25304, 13944,29400, 13984,17624, 13992,21720, + 14000,25816, 14008,29912, 14048,18136, 14056,22232, 14064,26328, + 14072,30424, 14104,14552, 14112,18648, 14120,22744, 14128,26840, + 14136,30936, 14168,15064, 14176,19160, 14184,23256, 14192,27352, + 14200,31448, 14232,15576, 14240,19672, 14248,23768, 14256,27864, + 14264,31960, 14296,16088, 14304,20184, 14312,24280, 14320,28376, + 14328,32472, 14368,16664, 14376,20760, 14384,24856, 14392,28952, + 14432,17176, 14440,21272, 14448,25368, 14456,29464, 14496,17688, + 14504,21784, 14512,25880, 14520,29976, 14560,18200, 14568,22296, + 14576,26392, 14584,30488, 14624,18712, 14632,22808, 14640,26904, + 14648,31000, 14680,15128, 14688,19224, 14696,23320, 14704,27416, + 14712,31512, 14744,15640, 14752,19736, 14760,23832, 14768,27928, + 14776,32024, 14808,16152, 14816,20248, 14824,24344, 14832,28440, + 14840,32536, 14880,16728, 14888,20824, 14896,24920, 14904,29016, + 14944,17240, 14952,21336, 14960,25432, 14968,29528, 15008,17752, + 15016,21848, 15024,25944, 15032,30040, 15072,18264, 15080,22360, + 15088,26456, 15096,30552, 15136,18776, 15144,22872, 15152,26968, + 15160,31064, 15200,19288, 15208,23384, 15216,27480, 15224,31576, + 15256,15704, 15264,19800, 15272,23896, 15280,27992, 15288,32088, + 15320,16216, 15328,20312, 15336,24408, 15344,28504, 15352,32600, + 15392,16792, 15400,20888, 15408,24984, 15416,29080, 15456,17304, + 15464,21400, 15472,25496, 15480,29592, 15520,17816, 15528,21912, + 15536,26008, 15544,30104, 15584,18328, 15592,22424, 15600,26520, + 15608,30616, 15648,18840, 15656,22936, 15664,27032, 15672,31128, + 15712,19352, 15720,23448, 15728,27544, 15736,31640, 15776,19864, + 15784,23960, 15792,28056, 15800,32152, 15832,16280, 15840,20376, + 15848,24472, 15856,28568, 15864,32664, 15904,16856, 15912,20952, + 15920,25048, 15928,29144, 15968,17368, 15976,21464, 15984,25560, + 15992,29656, 16032,17880, 16040,21976, 16048,26072, 16056,30168, + 16096,18392, 16104,22488, 16112,26584, 16120,30680, 16160,18904, + 16168,23000, 16176,27096, 16184,31192, 16224,19416, 16232,23512, + 16240,27608, 16248,31704, 16288,19928, 16296,24024, 16304,28120, + 16312,32216, 16352,20440, 16360,24536, 16368,28632, 16376,32728, + 16424,20512, 16432,24608, 16440,28704, 16480,16928, 16488,21024, + 16496,25120, 16504,29216, 16544,17440, 16552,21536, 16560,25632, + 16568,29728, 16608,17952, 16616,22048, 16624,26144, 16632,30240, + 16672,18464, 16680,22560, 16688,26656, 16696,30752, 16736,18976, + 16744,23072, 16752,27168, 16760,31264, 16800,19488, 16808,23584, + 16816,27680, 16824,31776, 16864,20000, 16872,24096, 16880,28192, + 16888,32288, 16936,20576, 16944,24672, 16952,28768, 17000,21088, + 17008,25184, 17016,29280, 17056,17504, 17064,21600, 17072,25696, + 17080,29792, 17120,18016, 17128,22112, 17136,26208, 17144,30304, + 17184,18528, 17192,22624, 17200,26720, 17208,30816, 17248,19040, + 17256,23136, 17264,27232, 17272,31328, 17312,19552, 17320,23648, + 17328,27744, 17336,31840, 17376,20064, 17384,24160, 17392,28256, + 17400,32352, 17448,20640, 17456,24736, 17464,28832, 17512,21152, + 17520,25248, 17528,29344, 17576,21664, 17584,25760, 17592,29856, + 17632,18080, 17640,22176, 17648,26272, 17656,30368, 17696,18592, + 17704,22688, 17712,26784, 17720,30880, 17760,19104, 17768,23200, + 17776,27296, 17784,31392, 17824,19616, 17832,23712, 17840,27808, + 17848,31904, 17888,20128, 17896,24224, 17904,28320, 17912,32416, + 17960,20704, 17968,24800, 17976,28896, 18024,21216, 18032,25312, + 18040,29408, 18088,21728, 18096,25824, 18104,29920, 18152,22240, + 18160,26336, 18168,30432, 18208,18656, 18216,22752, 18224,26848, + 18232,30944, 18272,19168, 18280,23264, 18288,27360, 18296,31456, + 18336,19680, 18344,23776, 18352,27872, 18360,31968, 18400,20192, + 18408,24288, 18416,28384, 18424,32480, 18472,20768, 18480,24864, + 18488,28960, 18536,21280, 18544,25376, 18552,29472, 18600,21792, + 18608,25888, 18616,29984, 18664,22304, 18672,26400, 18680,30496, + 18728,22816, 18736,26912, 18744,31008, 18784,19232, 18792,23328, + 18800,27424, 18808,31520, 18848,19744, 18856,23840, 18864,27936, + 18872,32032, 18912,20256, 18920,24352, 18928,28448, 18936,32544, + 18984,20832, 18992,24928, 19000,29024, 19048,21344, 19056,25440, + 19064,29536, 19112,21856, 19120,25952, 19128,30048, 19176,22368, + 19184,26464, 19192,30560, 19240,22880, 19248,26976, 19256,31072, + 19304,23392, 19312,27488, 19320,31584, 19360,19808, 19368,23904, + 19376,28000, 19384,32096, 19424,20320, 19432,24416, 19440,28512, + 19448,32608, 19496,20896, 19504,24992, 19512,29088, 19560,21408, + 19568,25504, 19576,29600, 19624,21920, 19632,26016, 19640,30112, + 19688,22432, 19696,26528, 19704,30624, 19752,22944, 19760,27040, + 19768,31136, 19816,23456, 19824,27552, 19832,31648, 19880,23968, + 19888,28064, 19896,32160, 19936,20384, 19944,24480, 19952,28576, + 19960,32672, 20008,20960, 20016,25056, 20024,29152, 20072,21472, + 20080,25568, 20088,29664, 20136,21984, 20144,26080, 20152,30176, + 20200,22496, 20208,26592, 20216,30688, 20264,23008, 20272,27104, + 20280,31200, 20328,23520, 20336,27616, 20344,31712, 20392,24032, + 20400,28128, 20408,32224, 20456,24544, 20464,28640, 20472,32736, + 20528,24616, 20536,28712, 20584,21032, 20592,25128, 20600,29224, + 20648,21544, 20656,25640, 20664,29736, 20712,22056, 20720,26152, + 20728,30248, 20776,22568, 20784,26664, 20792,30760, 20840,23080, + 20848,27176, 20856,31272, 20904,23592, 20912,27688, 20920,31784, + 20968,24104, 20976,28200, 20984,32296, 21040,24680, 21048,28776, + 21104,25192, 21112,29288, 21160,21608, 21168,25704, 21176,29800, + 21224,22120, 21232,26216, 21240,30312, 21288,22632, 21296,26728, + 21304,30824, 21352,23144, 21360,27240, 21368,31336, 21416,23656, + 21424,27752, 21432,31848, 21480,24168, 21488,28264, 21496,32360, + 21552,24744, 21560,28840, 21616,25256, 21624,29352, 21680,25768, + 21688,29864, 21736,22184, 21744,26280, 21752,30376, 21800,22696, + 21808,26792, 21816,30888, 21864,23208, 21872,27304, 21880,31400, + 21928,23720, 21936,27816, 21944,31912, 21992,24232, 22000,28328, + 22008,32424, 22064,24808, 22072,28904, 22128,25320, 22136,29416, + 22192,25832, 22200,29928, 22256,26344, 22264,30440, 22312,22760, + 22320,26856, 22328,30952, 22376,23272, 22384,27368, 22392,31464, + 22440,23784, 22448,27880, 22456,31976, 22504,24296, 22512,28392, + 22520,32488, 22576,24872, 22584,28968, 22640,25384, 22648,29480, + 22704,25896, 22712,29992, 22768,26408, 22776,30504, 22832,26920, + 22840,31016, 22888,23336, 22896,27432, 22904,31528, 22952,23848, + 22960,27944, 22968,32040, 23016,24360, 23024,28456, 23032,32552, + 23088,24936, 23096,29032, 23152,25448, 23160,29544, 23216,25960, + 23224,30056, 23280,26472, 23288,30568, 23344,26984, 23352,31080, + 23408,27496, 23416,31592, 23464,23912, 23472,28008, 23480,32104, + 23528,24424, 23536,28520, 23544,32616, 23600,25000, 23608,29096, + 23664,25512, 23672,29608, 23728,26024, 23736,30120, 23792,26536, + 23800,30632, 23856,27048, 23864,31144, 23920,27560, 23928,31656, + 23984,28072, 23992,32168, 24040,24488, 24048,28584, 24056,32680, + 24112,25064, 24120,29160, 24176,25576, 24184,29672, 24240,26088, + 24248,30184, 24304,26600, 24312,30696, 24368,27112, 24376,31208, + 24432,27624, 24440,31720, 24496,28136, 24504,32232, 24560,28648, + 24568,32744, 24632,28720, 24688,25136, 24696,29232, 24752,25648, + 24760,29744, 24816,26160, 24824,30256, 24880,26672, 24888,30768, + 24944,27184, 24952,31280, 25008,27696, 25016,31792, 25072,28208, + 25080,32304, 25144,28784, 25208,29296, 25264,25712, 25272,29808, + 25328,26224, 25336,30320, 25392,26736, 25400,30832, 25456,27248, + 25464,31344, 25520,27760, 25528,31856, 25584,28272, 25592,32368, + 25656,28848, 25720,29360, 25784,29872, 25840,26288, 25848,30384, + 25904,26800, 25912,30896, 25968,27312, 25976,31408, 26032,27824, + 26040,31920, 26096,28336, 26104,32432, 26168,28912, 26232,29424, + 26296,29936, 26360,30448, 26416,26864, 26424,30960, 26480,27376, + 26488,31472, 26544,27888, 26552,31984, 26608,28400, 26616,32496, + 26680,28976, 26744,29488, 26808,30000, 26872,30512, 26936,31024, + 26992,27440, 27000,31536, 27056,27952, 27064,32048, 27120,28464, + 27128,32560, 27192,29040, 27256,29552, 27320,30064, 27384,30576, + 27448,31088, 27512,31600, 27568,28016, 27576,32112, 27632,28528, + 27640,32624, 27704,29104, 27768,29616, 27832,30128, 27896,30640, + 27960,31152, 28024,31664, 28088,32176, 28144,28592, 28152,32688, + 28216,29168, 28280,29680, 28344,30192, 28408,30704, 28472,31216, + 28536,31728, 28600,32240, 28664,32752, 28792,29240, 28856,29752, + 28920,30264, 28984,30776, 29048,31288, 29112,31800, 29176,32312, + 29368,29816, 29432,30328, 29496,30840, 29560,31352, 29624,31864, + 29688,32376, 29944,30392, 30008,30904, 30072,31416, 30136,31928, + 30200,32440, 30520,30968, 30584,31480, 30648,31992, 30712,32504, + 31096,31544, 31160,32056, 31224,32568, 31672,32120, 31736,32632, + 32248,32696 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16) + +const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH] = +{ + /* radix 4, size 12 */ + 8,64, 16,32, 24,96, 40,80, 56,112, 88,104 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32) +const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH] = +{ + /* 4x2, size 24 */ + 8,128, 16,64, 24,192, 40,160, 48,96, 56,224, 72,144, + 88,208, 104,176, 120,240, 152,200, 184,232 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64) +const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH] = +{ + /* radix 4, size 56 */ + 8,256, 16,128, 24,384, 32,64, 40,320, 48,192, 56,448, 72,288, 80,160, 88,416, 104,352, + 112,224, 120,480, 136,272, 152,400, 168,336, 176,208, 184,464, 200,304, 216,432, + 232,368, 248,496, 280,392, 296,328, 312,456, 344,424, 376,488, 440,472 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128) +const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH] = +{ + /* 4x2, size 112 */ + 8,512, 16,256, 24,768, 32,128, 40,640, 48,384, 56,896, 72,576, 80,320, 88,832, 96,192, + 104,704, 112,448, 120,960, 136,544, 144,288, 152,800, 168,672, 176,416, 184,928, 200,608, + 208,352, 216,864, 232,736, 240,480, 248,992, 264,528, 280,784, 296,656, 304,400, 312,912, + 328,592, 344,848, 360,720, 368,464, 376,976, 392,560, 408,816, 424,688, 440,944, 456,624, + 472,880, 488,752, 504,1008, 536,776, 552,648, 568,904, 600,840, 616,712, 632,968, + 664,808, 696,936, 728,872, 760,1000, 824,920, 888,984 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256) +const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH] = +{ + /* radix 4, size 240 */ + 8,1024, 16,512, 24,1536, 32,256, 40,1280, 48,768, 56,1792, 64,128, 72,1152, 80,640, + 88,1664, 96,384, 104,1408, 112,896, 120,1920, 136,1088, 144,576, 152,1600, 160,320, + 168,1344, 176,832, 184,1856, 200,1216, 208,704, 216,1728, 224,448, 232,1472, 240,960, + 248,1984, 264,1056, 272,544, 280,1568, 296,1312, 304,800, 312,1824, 328,1184, 336,672, + 344,1696, 352,416, 360,1440, 368,928, 376,1952, 392,1120, 400,608, 408,1632, 424,1376, + 432,864, 440,1888, 456,1248, 464,736, 472,1760, 488,1504, 496,992, 504,2016, 520,1040, + 536,1552, 552,1296, 560,784, 568,1808, 584,1168, 592,656, 600,1680, 616,1424, 624,912, + 632,1936, 648,1104, 664,1616, 680,1360, 688,848, 696,1872, 712,1232, 728,1744, 744,1488, + 752,976, 760,2000, 776,1072, 792,1584, 808,1328, 824,1840, 840,1200, 856,1712, 872,1456, + 880,944, 888,1968, 904,1136, 920,1648, 936,1392, 952,1904, 968,1264, 984,1776, 1000,1520, + 1016,2032, 1048,1544, 1064,1288, 1080,1800, 1096,1160, 1112,1672, 1128,1416, 1144,1928, + 1176,1608, 1192,1352, 1208,1864, 1240,1736, 1256,1480, 1272,1992, 1304,1576, 1336,1832, + 1368,1704, 1384,1448, 1400,1960, 1432,1640, 1464,1896, 1496,1768, 1528,2024, 1592,1816, + 1624,1688, 1656,1944, 1720,1880, 1784,2008, 1912,1976 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512) +const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH] = +{ + /* 4x2, size 480 */ + 8,2048, 16,1024, 24,3072, 32,512, 40,2560, 48,1536, 56,3584, 64,256, 72,2304, 80,1280, + 88,3328, 96,768, 104,2816, 112,1792, 120,3840, 136,2176, 144,1152, 152,3200, 160,640, + 168,2688, 176,1664, 184,3712, 192,384, 200,2432, 208,1408, 216,3456, 224,896, 232,2944, + 240,1920, 248,3968, 264,2112, 272,1088, 280,3136, 288,576, 296,2624, 304,1600, 312,3648, + 328,2368, 336,1344, 344,3392, 352,832, 360,2880, 368,1856, 376,3904, 392,2240, 400,1216, + 408,3264, 416,704, 424,2752, 432,1728, 440,3776, 456,2496, 464,1472, 472,3520, 480,960, + 488,3008, 496,1984, 504,4032, 520,2080, 528,1056, 536,3104, 552,2592, 560,1568, 568,3616, + 584,2336, 592,1312, 600,3360, 608,800, 616,2848, 624,1824, 632,3872, 648,2208, 656,1184, + 664,3232, 680,2720, 688,1696, 696,3744, 712,2464, 720,1440, 728,3488, 736,928, 744,2976, + 752,1952, 760,4000, 776,2144, 784,1120, 792,3168, 808,2656, 816,1632, 824,3680, 840,2400, + 848,1376, 856,3424, 872,2912, 880,1888, 888,3936, 904,2272, 912,1248, 920,3296, 936,2784, + 944,1760, 952,3808, 968,2528, 976,1504, 984,3552, 1000,3040, 1008,2016, 1016,4064, + 1032,2064, 1048,3088, 1064,2576, 1072,1552, 1080,3600, 1096,2320, 1104,1296, 1112,3344, + 1128,2832, 1136,1808, 1144,3856, 1160,2192, 1176,3216, 1192,2704, 1200,1680, 1208,3728, + 1224,2448, 1232,1424, 1240,3472, 1256,2960, 1264,1936, 1272,3984, 1288,2128, 1304,3152, + 1320,2640, 1328,1616, 1336,3664, 1352,2384, 1368,3408, 1384,2896, 1392,1872, 1400,3920, + 1416,2256, 1432,3280, 1448,2768, 1456,1744, 1464,3792, 1480,2512, 1496,3536, 1512,3024, + 1520,2000, 1528,4048, 1544,2096, 1560,3120, 1576,2608, 1592,3632, 1608,2352, 1624,3376, + 1640,2864, 1648,1840, 1656,3888, 1672,2224, 1688,3248, 1704,2736, 1720,3760, 1736,2480, + 1752,3504, 1768,2992, 1776,1968, 1784,4016, 1800,2160, 1816,3184, 1832,2672, 1848,3696, + 1864,2416, 1880,3440, 1896,2928, 1912,3952, 1928,2288, 1944,3312, 1960,2800, 1976,3824, + 1992,2544, 2008,3568, 2024,3056, 2040,4080, 2072,3080, 2088,2568, 2104,3592, 2120,2312, + 2136,3336, 2152,2824, 2168,3848, 2200,3208, 2216,2696, 2232,3720, 2248,2440, 2264,3464, + 2280,2952, 2296,3976, 2328,3144, 2344,2632, 2360,3656, 2392,3400, 2408,2888, 2424,3912, + 2456,3272, 2472,2760, 2488,3784, 2520,3528, 2536,3016, 2552,4040, 2584,3112, 2616,3624, + 2648,3368, 2664,2856, 2680,3880, 2712,3240, 2744,3752, 2776,3496, 2792,2984, 2808,4008, + 2840,3176, 2872,3688, 2904,3432, 2936,3944, 2968,3304, 3000,3816, 3032,3560, 3064,4072, + 3128,3608, 3160,3352, 3192,3864, 3256,3736, 3288,3480, 3320,3992, 3384,3672, 3448,3928, + 3512,3800, 3576,4056, 3704,3896, 3832,4024 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024) +const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH] = +{ + /* radix 4, size 992 */ + 8,4096, 16,2048, 24,6144, 32,1024, 40,5120, 48,3072, 56,7168, 64,512, 72,4608, + 80,2560, 88,6656, 96,1536, 104,5632, 112,3584, 120,7680, 128,256, 136,4352, + 144,2304, 152,6400, 160,1280, 168,5376, 176,3328, 184,7424, 192,768, 200,4864, + 208,2816, 216,6912, 224,1792, 232,5888, 240,3840, 248,7936, 264,4224, 272,2176, + 280,6272, 288,1152, 296,5248, 304,3200, 312,7296, 320,640, 328,4736, 336,2688, + 344,6784, 352,1664, 360,5760, 368,3712, 376,7808, 392,4480, 400,2432, 408,6528, + 416,1408, 424,5504, 432,3456, 440,7552, 448,896, 456,4992, 464,2944, 472,7040, + 480,1920, 488,6016, 496,3968, 504,8064, 520,4160, 528,2112, 536,6208, 544,1088, + 552,5184, 560,3136, 568,7232, 584,4672, 592,2624, 600,6720, 608,1600, 616,5696, + 624,3648, 632,7744, 648,4416, 656,2368, 664,6464, 672,1344, 680,5440, 688,3392, + 696,7488, 704,832, 712,4928, 720,2880, 728,6976, 736,1856, 744,5952, 752,3904, + 760,8000, 776,4288, 784,2240, 792,6336, 800,1216, 808,5312, 816,3264, 824,7360, + 840,4800, 848,2752, 856,6848, 864,1728, 872,5824, 880,3776, 888,7872, 904,4544, + 912,2496, 920,6592, 928,1472, 936,5568, 944,3520, 952,7616, 968,5056, 976,3008, + 984,7104, 992,1984, 1000,6080, 1008,4032, 1016,8128, 1032,4128, 1040,2080, + 1048,6176, 1064,5152, 1072,3104, 1080,7200, 1096,4640, 1104,2592, 1112,6688, + 1120,1568, 1128,5664, 1136,3616, 1144,7712, 1160,4384, 1168,2336, 1176,6432, + 1184,1312, 1192,5408, 1200,3360, 1208,7456, 1224,4896, 1232,2848, 1240,6944, + 1248,1824, 1256,5920, 1264,3872, 1272,7968, 1288,4256, 1296,2208, 1304,6304, + 1320,5280, 1328,3232, 1336,7328, 1352,4768, 1360,2720, 1368,6816, 1376,1696, + 1384,5792, 1392,3744, 1400,7840, 1416,4512, 1424,2464, 1432,6560, 1448,5536, + 1456,3488, 1464,7584, 1480,5024, 1488,2976, 1496,7072, 1504,1952, 1512,6048, + 1520,4000, 1528,8096, 1544,4192, 1552,2144, 1560,6240, 1576,5216, 1584,3168, + 1592,7264, 1608,4704, 1616,2656, 1624,6752, 1640,5728, 1648,3680, 1656,7776, + 1672,4448, 1680,2400, 1688,6496, 1704,5472, 1712,3424, 1720,7520, 1736,4960, + 1744,2912, 1752,7008, 1760,1888, 1768,5984, 1776,3936, 1784,8032, 1800,4320, + 1808,2272, 1816,6368, 1832,5344, 1840,3296, 1848,7392, 1864,4832, 1872,2784, + 1880,6880, 1896,5856, 1904,3808, 1912,7904, 1928,4576, 1936,2528, 1944,6624, + 1960,5600, 1968,3552, 1976,7648, 1992,5088, 2000,3040, 2008,7136, 2024,6112, + 2032,4064, 2040,8160, 2056,4112, 2072,6160, 2088,5136, 2096,3088, 2104,7184, + 2120,4624, 2128,2576, 2136,6672, 2152,5648, 2160,3600, 2168,7696, 2184,4368, + 2192,2320, 2200,6416, 2216,5392, 2224,3344, 2232,7440, 2248,4880, 2256,2832, + 2264,6928, 2280,5904, 2288,3856, 2296,7952, 2312,4240, 2328,6288, 2344,5264, + 2352,3216, 2360,7312, 2376,4752, 2384,2704, 2392,6800, 2408,5776, 2416,3728, + 2424,7824, 2440,4496, 2456,6544, 2472,5520, 2480,3472, 2488,7568, 2504,5008, + 2512,2960, 2520,7056, 2536,6032, 2544,3984, 2552,8080, 2568,4176, 2584,6224, + 2600,5200, 2608,3152, 2616,7248, 2632,4688, 2648,6736, 2664,5712, 2672,3664, + 2680,7760, 2696,4432, 2712,6480, 2728,5456, 2736,3408, 2744,7504, 2760,4944, + 2768,2896, 2776,6992, 2792,5968, 2800,3920, 2808,8016, 2824,4304, 2840,6352, + 2856,5328, 2864,3280, 2872,7376, 2888,4816, 2904,6864, 2920,5840, 2928,3792, + 2936,7888, 2952,4560, 2968,6608, 2984,5584, 2992,3536, 3000,7632, 3016,5072, + 3032,7120, 3048,6096, 3056,4048, 3064,8144, 3080,4144, 3096,6192, 3112,5168, + 3128,7216, 3144,4656, 3160,6704, 3176,5680, 3184,3632, 3192,7728, 3208,4400, + 3224,6448, 3240,5424, 3248,3376, 3256,7472, 3272,4912, 3288,6960, 3304,5936, + 3312,3888, 3320,7984, 3336,4272, 3352,6320, 3368,5296, 3384,7344, 3400,4784, + 3416,6832, 3432,5808, 3440,3760, 3448,7856, 3464,4528, 3480,6576, 3496,5552, + 3512,7600, 3528,5040, 3544,7088, 3560,6064, 3568,4016, 3576,8112, 3592,4208, + 3608,6256, 3624,5232, 3640,7280, 3656,4720, 3672,6768, 3688,5744, 3704,7792, + 3720,4464, 3736,6512, 3752,5488, 3768,7536, 3784,4976, 3800,7024, 3816,6000, + 3824,3952, 3832,8048, 3848,4336, 3864,6384, 3880,5360, 3896,7408, 3912,4848, + 3928,6896, 3944,5872, 3960,7920, 3976,4592, 3992,6640, 4008,5616, 4024,7664, + 4040,5104, 4056,7152, 4072,6128, 4088,8176, 4120,6152, 4136,5128, 4152,7176, + 4168,4616, 4184,6664, 4200,5640, 4216,7688, 4232,4360, 4248,6408, 4264,5384, + 4280,7432, 4296,4872, 4312,6920, 4328,5896, 4344,7944, 4376,6280, 4392,5256, + 4408,7304, 4424,4744, 4440,6792, 4456,5768, 4472,7816, 4504,6536, 4520,5512, + 4536,7560, 4552,5000, 4568,7048, 4584,6024, 4600,8072, 4632,6216, 4648,5192, + 4664,7240, 4696,6728, 4712,5704, 4728,7752, 4760,6472, 4776,5448, 4792,7496, + 4808,4936, 4824,6984, 4840,5960, 4856,8008, 4888,6344, 4904,5320, 4920,7368, + 4952,6856, 4968,5832, 4984,7880, 5016,6600, 5032,5576, 5048,7624, 5080,7112, + 5096,6088, 5112,8136, 5144,6184, 5176,7208, 5208,6696, 5224,5672, 5240,7720, + 5272,6440, 5288,5416, 5304,7464, 5336,6952, 5352,5928, 5368,7976, 5400,6312, + 5432,7336, 5464,6824, 5480,5800, 5496,7848, 5528,6568, 5560,7592, 5592,7080, + 5608,6056, 5624,8104, 5656,6248, 5688,7272, 5720,6760, 5752,7784, 5784,6504, + 5816,7528, 5848,7016, 5864,5992, 5880,8040, 5912,6376, 5944,7400, 5976,6888, + 6008,7912, 6040,6632, 6072,7656, 6104,7144, 6136,8168, 6200,7192, 6232,6680, + 6264,7704, 6296,6424, 6328,7448, 6360,6936, 6392,7960, 6456,7320, 6488,6808, + 6520,7832, 6584,7576, 6616,7064, 6648,8088, 6712,7256, 6776,7768, 6840,7512, + 6872,7000, 6904,8024, 6968,7384, 7032,7896, 7096,7640, 7160,8152, 7288,7736, + 7352,7480, 7416,7992, 7544,7864, 7672,8120, 7928,8056 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048) +const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH] = +{ + /* 4x2, size 1984 */ + 8,8192, 16,4096, 24,12288, 32,2048, 40,10240, 48,6144, 56,14336, 64,1024, + 72,9216, 80,5120, 88,13312, 96,3072, 104,11264, 112,7168, 120,15360, 128,512, + 136,8704, 144,4608, 152,12800, 160,2560, 168,10752, 176,6656, 184,14848, + 192,1536, 200,9728, 208,5632, 216,13824, 224,3584, 232,11776, 240,7680, + 248,15872, 264,8448, 272,4352, 280,12544, 288,2304, 296,10496, 304,6400, + 312,14592, 320,1280, 328,9472, 336,5376, 344,13568, 352,3328, 360,11520, + 368,7424, 376,15616, 384,768, 392,8960, 400,4864, 408,13056, 416,2816, + 424,11008, 432,6912, 440,15104, 448,1792, 456,9984, 464,5888, 472,14080, + 480,3840, 488,12032, 496,7936, 504,16128, 520,8320, 528,4224, 536,12416, + 544,2176, 552,10368, 560,6272, 568,14464, 576,1152, 584,9344, 592,5248, + 600,13440, 608,3200, 616,11392, 624,7296, 632,15488, 648,8832, 656,4736, + 664,12928, 672,2688, 680,10880, 688,6784, 696,14976, 704,1664, 712,9856, + 720,5760, 728,13952, 736,3712, 744,11904, 752,7808, 760,16000, 776,8576, + 784,4480, 792,12672, 800,2432, 808,10624, 816,6528, 824,14720, 832,1408, + 840,9600, 848,5504, 856,13696, 864,3456, 872,11648, 880,7552, 888,15744, + 904,9088, 912,4992, 920,13184, 928,2944, 936,11136, 944,7040, 952,15232, + 960,1920, 968,10112, 976,6016, 984,14208, 992,3968, 1000,12160, 1008,8064, + 1016,16256, 1032,8256, 1040,4160, 1048,12352, 1056,2112, 1064,10304, 1072,6208, + 1080,14400, 1096,9280, 1104,5184, 1112,13376, 1120,3136, 1128,11328, 1136,7232, + 1144,15424, 1160,8768, 1168,4672, 1176,12864, 1184,2624, 1192,10816, 1200,6720, + 1208,14912, 1216,1600, 1224,9792, 1232,5696, 1240,13888, 1248,3648, 1256,11840, + 1264,7744, 1272,15936, 1288,8512, 1296,4416, 1304,12608, 1312,2368, 1320,10560, + 1328,6464, 1336,14656, 1352,9536, 1360,5440, 1368,13632, 1376,3392, 1384,11584, + 1392,7488, 1400,15680, 1416,9024, 1424,4928, 1432,13120, 1440,2880, 1448,11072, + 1456,6976, 1464,15168, 1472,1856, 1480,10048, 1488,5952, 1496,14144, 1504,3904, + 1512,12096, 1520,8000, 1528,16192, 1544,8384, 1552,4288, 1560,12480, 1568,2240, + 1576,10432, 1584,6336, 1592,14528, 1608,9408, 1616,5312, 1624,13504, 1632,3264, + 1640,11456, 1648,7360, 1656,15552, 1672,8896, 1680,4800, 1688,12992, 1696,2752, + 1704,10944, 1712,6848, 1720,15040, 1736,9920, 1744,5824, 1752,14016, 1760,3776, + 1768,11968, 1776,7872, 1784,16064, 1800,8640, 1808,4544, 1816,12736, 1824,2496, + 1832,10688, 1840,6592, 1848,14784, 1864,9664, 1872,5568, 1880,13760, 1888,3520, + 1896,11712, 1904,7616, 1912,15808, 1928,9152, 1936,5056, 1944,13248, 1952,3008, + 1960,11200, 1968,7104, 1976,15296, 1992,10176, 2000,6080, 2008,14272, 2016,4032, + 2024,12224, 2032,8128, 2040,16320, 2056,8224, 2064,4128, 2072,12320, 2088,10272, + 2096,6176, 2104,14368, 2120,9248, 2128,5152, 2136,13344, 2144,3104, 2152,11296, + 2160,7200, 2168,15392, 2184,8736, 2192,4640, 2200,12832, 2208,2592, 2216,10784, + 2224,6688, 2232,14880, 2248,9760, 2256,5664, 2264,13856, 2272,3616, 2280,11808, + 2288,7712, 2296,15904, 2312,8480, 2320,4384, 2328,12576, 2344,10528, 2352,6432, + 2360,14624, 2376,9504, 2384,5408, 2392,13600, 2400,3360, 2408,11552, 2416,7456, + 2424,15648, 2440,8992, 2448,4896, 2456,13088, 2464,2848, 2472,11040, 2480,6944, + 2488,15136, 2504,10016, 2512,5920, 2520,14112, 2528,3872, 2536,12064, 2544,7968, + 2552,16160, 2568,8352, 2576,4256, 2584,12448, 2600,10400, 2608,6304, 2616,14496, + 2632,9376, 2640,5280, 2648,13472, 2656,3232, 2664,11424, 2672,7328, 2680,15520, + 2696,8864, 2704,4768, 2712,12960, 2728,10912, 2736,6816, 2744,15008, 2760,9888, + 2768,5792, 2776,13984, 2784,3744, 2792,11936, 2800,7840, 2808,16032, 2824,8608, + 2832,4512, 2840,12704, 2856,10656, 2864,6560, 2872,14752, 2888,9632, 2896,5536, + 2904,13728, 2912,3488, 2920,11680, 2928,7584, 2936,15776, 2952,9120, 2960,5024, + 2968,13216, 2984,11168, 2992,7072, 3000,15264, 3016,10144, 3024,6048, + 3032,14240, 3040,4000, 3048,12192, 3056,8096, 3064,16288, 3080,8288, 3088,4192, + 3096,12384, 3112,10336, 3120,6240, 3128,14432, 3144,9312, 3152,5216, 3160,13408, + 3176,11360, 3184,7264, 3192,15456, 3208,8800, 3216,4704, 3224,12896, 3240,10848, + 3248,6752, 3256,14944, 3272,9824, 3280,5728, 3288,13920, 3296,3680, 3304,11872, + 3312,7776, 3320,15968, 3336,8544, 3344,4448, 3352,12640, 3368,10592, 3376,6496, + 3384,14688, 3400,9568, 3408,5472, 3416,13664, 3432,11616, 3440,7520, 3448,15712, + 3464,9056, 3472,4960, 3480,13152, 3496,11104, 3504,7008, 3512,15200, 3528,10080, + 3536,5984, 3544,14176, 3552,3936, 3560,12128, 3568,8032, 3576,16224, 3592,8416, + 3600,4320, 3608,12512, 3624,10464, 3632,6368, 3640,14560, 3656,9440, 3664,5344, + 3672,13536, 3688,11488, 3696,7392, 3704,15584, 3720,8928, 3728,4832, 3736,13024, + 3752,10976, 3760,6880, 3768,15072, 3784,9952, 3792,5856, 3800,14048, 3816,12000, + 3824,7904, 3832,16096, 3848,8672, 3856,4576, 3864,12768, 3880,10720, 3888,6624, + 3896,14816, 3912,9696, 3920,5600, 3928,13792, 3944,11744, 3952,7648, 3960,15840, + 3976,9184, 3984,5088, 3992,13280, 4008,11232, 4016,7136, 4024,15328, 4040,10208, + 4048,6112, 4056,14304, 4072,12256, 4080,8160, 4088,16352, 4104,8208, 4120,12304, + 4136,10256, 4144,6160, 4152,14352, 4168,9232, 4176,5136, 4184,13328, 4200,11280, + 4208,7184, 4216,15376, 4232,8720, 4240,4624, 4248,12816, 4264,10768, 4272,6672, + 4280,14864, 4296,9744, 4304,5648, 4312,13840, 4328,11792, 4336,7696, 4344,15888, + 4360,8464, 4376,12560, 4392,10512, 4400,6416, 4408,14608, 4424,9488, 4432,5392, + 4440,13584, 4456,11536, 4464,7440, 4472,15632, 4488,8976, 4496,4880, 4504,13072, + 4520,11024, 4528,6928, 4536,15120, 4552,10000, 4560,5904, 4568,14096, + 4584,12048, 4592,7952, 4600,16144, 4616,8336, 4632,12432, 4648,10384, 4656,6288, + 4664,14480, 4680,9360, 4688,5264, 4696,13456, 4712,11408, 4720,7312, 4728,15504, + 4744,8848, 4760,12944, 4776,10896, 4784,6800, 4792,14992, 4808,9872, 4816,5776, + 4824,13968, 4840,11920, 4848,7824, 4856,16016, 4872,8592, 4888,12688, + 4904,10640, 4912,6544, 4920,14736, 4936,9616, 4944,5520, 4952,13712, 4968,11664, + 4976,7568, 4984,15760, 5000,9104, 5016,13200, 5032,11152, 5040,7056, 5048,15248, + 5064,10128, 5072,6032, 5080,14224, 5096,12176, 5104,8080, 5112,16272, 5128,8272, + 5144,12368, 5160,10320, 5168,6224, 5176,14416, 5192,9296, 5208,13392, + 5224,11344, 5232,7248, 5240,15440, 5256,8784, 5272,12880, 5288,10832, 5296,6736, + 5304,14928, 5320,9808, 5328,5712, 5336,13904, 5352,11856, 5360,7760, 5368,15952, + 5384,8528, 5400,12624, 5416,10576, 5424,6480, 5432,14672, 5448,9552, 5464,13648, + 5480,11600, 5488,7504, 5496,15696, 5512,9040, 5528,13136, 5544,11088, 5552,6992, + 5560,15184, 5576,10064, 5584,5968, 5592,14160, 5608,12112, 5616,8016, + 5624,16208, 5640,8400, 5656,12496, 5672,10448, 5680,6352, 5688,14544, 5704,9424, + 5720,13520, 5736,11472, 5744,7376, 5752,15568, 5768,8912, 5784,13008, + 5800,10960, 5808,6864, 5816,15056, 5832,9936, 5848,14032, 5864,11984, 5872,7888, + 5880,16080, 5896,8656, 5912,12752, 5928,10704, 5936,6608, 5944,14800, 5960,9680, + 5976,13776, 5992,11728, 6000,7632, 6008,15824, 6024,9168, 6040,13264, + 6056,11216, 6064,7120, 6072,15312, 6088,10192, 6104,14288, 6120,12240, + 6128,8144, 6136,16336, 6152,8240, 6168,12336, 6184,10288, 6200,14384, 6216,9264, + 6232,13360, 6248,11312, 6256,7216, 6264,15408, 6280,8752, 6296,12848, + 6312,10800, 6320,6704, 6328,14896, 6344,9776, 6360,13872, 6376,11824, 6384,7728, + 6392,15920, 6408,8496, 6424,12592, 6440,10544, 6456,14640, 6472,9520, + 6488,13616, 6504,11568, 6512,7472, 6520,15664, 6536,9008, 6552,13104, + 6568,11056, 6576,6960, 6584,15152, 6600,10032, 6616,14128, 6632,12080, + 6640,7984, 6648,16176, 6664,8368, 6680,12464, 6696,10416, 6712,14512, 6728,9392, + 6744,13488, 6760,11440, 6768,7344, 6776,15536, 6792,8880, 6808,12976, + 6824,10928, 6840,15024, 6856,9904, 6872,14000, 6888,11952, 6896,7856, + 6904,16048, 6920,8624, 6936,12720, 6952,10672, 6968,14768, 6984,9648, + 7000,13744, 7016,11696, 7024,7600, 7032,15792, 7048,9136, 7064,13232, + 7080,11184, 7096,15280, 7112,10160, 7128,14256, 7144,12208, 7152,8112, + 7160,16304, 7176,8304, 7192,12400, 7208,10352, 7224,14448, 7240,9328, + 7256,13424, 7272,11376, 7288,15472, 7304,8816, 7320,12912, 7336,10864, + 7352,14960, 7368,9840, 7384,13936, 7400,11888, 7408,7792, 7416,15984, 7432,8560, + 7448,12656, 7464,10608, 7480,14704, 7496,9584, 7512,13680, 7528,11632, + 7544,15728, 7560,9072, 7576,13168, 7592,11120, 7608,15216, 7624,10096, + 7640,14192, 7656,12144, 7664,8048, 7672,16240, 7688,8432, 7704,12528, + 7720,10480, 7736,14576, 7752,9456, 7768,13552, 7784,11504, 7800,15600, + 7816,8944, 7832,13040, 7848,10992, 7864,15088, 7880,9968, 7896,14064, + 7912,12016, 7928,16112, 7944,8688, 7960,12784, 7976,10736, 7992,14832, + 8008,9712, 8024,13808, 8040,11760, 8056,15856, 8072,9200, 8088,13296, + 8104,11248, 8120,15344, 8136,10224, 8152,14320, 8168,12272, 8184,16368, + 8216,12296, 8232,10248, 8248,14344, 8264,9224, 8280,13320, 8296,11272, + 8312,15368, 8328,8712, 8344,12808, 8360,10760, 8376,14856, 8392,9736, + 8408,13832, 8424,11784, 8440,15880, 8472,12552, 8488,10504, 8504,14600, + 8520,9480, 8536,13576, 8552,11528, 8568,15624, 8584,8968, 8600,13064, + 8616,11016, 8632,15112, 8648,9992, 8664,14088, 8680,12040, 8696,16136, + 8728,12424, 8744,10376, 8760,14472, 8776,9352, 8792,13448, 8808,11400, + 8824,15496, 8856,12936, 8872,10888, 8888,14984, 8904,9864, 8920,13960, + 8936,11912, 8952,16008, 8984,12680, 9000,10632, 9016,14728, 9032,9608, + 9048,13704, 9064,11656, 9080,15752, 9112,13192, 9128,11144, 9144,15240, + 9160,10120, 9176,14216, 9192,12168, 9208,16264, 9240,12360, 9256,10312, + 9272,14408, 9304,13384, 9320,11336, 9336,15432, 9368,12872, 9384,10824, + 9400,14920, 9416,9800, 9432,13896, 9448,11848, 9464,15944, 9496,12616, + 9512,10568, 9528,14664, 9560,13640, 9576,11592, 9592,15688, 9624,13128, + 9640,11080, 9656,15176, 9672,10056, 9688,14152, 9704,12104, 9720,16200, + 9752,12488, 9768,10440, 9784,14536, 9816,13512, 9832,11464, 9848,15560, + 9880,13000, 9896,10952, 9912,15048, 9944,14024, 9960,11976, 9976,16072, + 10008,12744, 10024,10696, 10040,14792, 10072,13768, 10088,11720, 10104,15816, + 10136,13256, 10152,11208, 10168,15304, 10200,14280, 10216,12232, 10232,16328, + 10264,12328, 10296,14376, 10328,13352, 10344,11304, 10360,15400, 10392,12840, + 10408,10792, 10424,14888, 10456,13864, 10472,11816, 10488,15912, 10520,12584, + 10552,14632, 10584,13608, 10600,11560, 10616,15656, 10648,13096, 10664,11048, + 10680,15144, 10712,14120, 10728,12072, 10744,16168, 10776,12456, 10808,14504, + 10840,13480, 10856,11432, 10872,15528, 10904,12968, 10936,15016, 10968,13992, + 10984,11944, 11000,16040, 11032,12712, 11064,14760, 11096,13736, 11112,11688, + 11128,15784, 11160,13224, 11192,15272, 11224,14248, 11240,12200, 11256,16296, + 11288,12392, 11320,14440, 11352,13416, 11384,15464, 11416,12904, 11448,14952, + 11480,13928, 11496,11880, 11512,15976, 11544,12648, 11576,14696, 11608,13672, + 11640,15720, 11672,13160, 11704,15208, 11736,14184, 11752,12136, 11768,16232, + 11800,12520, 11832,14568, 11864,13544, 11896,15592, 11928,13032, 11960,15080, + 11992,14056, 12024,16104, 12056,12776, 12088,14824, 12120,13800, 12152,15848, + 12184,13288, 12216,15336, 12248,14312, 12280,16360, 12344,14360, 12376,13336, + 12408,15384, 12440,12824, 12472,14872, 12504,13848, 12536,15896, 12600,14616, + 12632,13592, 12664,15640, 12696,13080, 12728,15128, 12760,14104, 12792,16152, + 12856,14488, 12888,13464, 12920,15512, 12984,15000, 13016,13976, 13048,16024, + 13112,14744, 13144,13720, 13176,15768, 13240,15256, 13272,14232, 13304,16280, + 13368,14424, 13432,15448, 13496,14936, 13528,13912, 13560,15960, 13624,14680, + 13688,15704, 13752,15192, 13784,14168, 13816,16216, 13880,14552, 13944,15576, + 14008,15064, 14072,16088, 14136,14808, 14200,15832, 14264,15320, 14328,16344, + 14456,15416, 14520,14904, 14584,15928, 14712,15672, 14776,15160, 14840,16184, + 14968,15544, 15096,16056, 15224,15800, 15352,16312, 15608,15992, 15864,16248 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096) +const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH] = +{ + /* radix 4, size 4032 */ + 8,16384, 16,8192, 24,24576, 32,4096, 40,20480, 48,12288, 56,28672, 64,2048, + 72,18432, 80,10240, 88,26624, 96,6144, 104,22528, 112,14336, 120,30720, + 128,1024, 136,17408, 144,9216, 152,25600, 160,5120, 168,21504, 176,13312, + 184,29696, 192,3072, 200,19456, 208,11264, 216,27648, 224,7168, 232,23552, + 240,15360, 248,31744, 256,512, 264,16896, 272,8704, 280,25088, 288,4608, + 296,20992, 304,12800, 312,29184, 320,2560, 328,18944, 336,10752, 344,27136, + 352,6656, 360,23040, 368,14848, 376,31232, 384,1536, 392,17920, 400,9728, + 408,26112, 416,5632, 424,22016, 432,13824, 440,30208, 448,3584, 456,19968, + 464,11776, 472,28160, 480,7680, 488,24064, 496,15872, 504,32256, 520,16640, + 528,8448, 536,24832, 544,4352, 552,20736, 560,12544, 568,28928, 576,2304, + 584,18688, 592,10496, 600,26880, 608,6400, 616,22784, 624,14592, 632,30976, + 640,1280, 648,17664, 656,9472, 664,25856, 672,5376, 680,21760, 688,13568, + 696,29952, 704,3328, 712,19712, 720,11520, 728,27904, 736,7424, 744,23808, + 752,15616, 760,32000, 776,17152, 784,8960, 792,25344, 800,4864, 808,21248, + 816,13056, 824,29440, 832,2816, 840,19200, 848,11008, 856,27392, 864,6912, + 872,23296, 880,15104, 888,31488, 896,1792, 904,18176, 912,9984, 920,26368, + 928,5888, 936,22272, 944,14080, 952,30464, 960,3840, 968,20224, 976,12032, + 984,28416, 992,7936, 1000,24320, 1008,16128, 1016,32512, 1032,16512, 1040,8320, + 1048,24704, 1056,4224, 1064,20608, 1072,12416, 1080,28800, 1088,2176, + 1096,18560, 1104,10368, 1112,26752, 1120,6272, 1128,22656, 1136,14464, + 1144,30848, 1160,17536, 1168,9344, 1176,25728, 1184,5248, 1192,21632, + 1200,13440, 1208,29824, 1216,3200, 1224,19584, 1232,11392, 1240,27776, + 1248,7296, 1256,23680, 1264,15488, 1272,31872, 1288,17024, 1296,8832, + 1304,25216, 1312,4736, 1320,21120, 1328,12928, 1336,29312, 1344,2688, + 1352,19072, 1360,10880, 1368,27264, 1376,6784, 1384,23168, 1392,14976, + 1400,31360, 1408,1664, 1416,18048, 1424,9856, 1432,26240, 1440,5760, 1448,22144, + 1456,13952, 1464,30336, 1472,3712, 1480,20096, 1488,11904, 1496,28288, + 1504,7808, 1512,24192, 1520,16000, 1528,32384, 1544,16768, 1552,8576, + 1560,24960, 1568,4480, 1576,20864, 1584,12672, 1592,29056, 1600,2432, + 1608,18816, 1616,10624, 1624,27008, 1632,6528, 1640,22912, 1648,14720, + 1656,31104, 1672,17792, 1680,9600, 1688,25984, 1696,5504, 1704,21888, + 1712,13696, 1720,30080, 1728,3456, 1736,19840, 1744,11648, 1752,28032, + 1760,7552, 1768,23936, 1776,15744, 1784,32128, 1800,17280, 1808,9088, + 1816,25472, 1824,4992, 1832,21376, 1840,13184, 1848,29568, 1856,2944, + 1864,19328, 1872,11136, 1880,27520, 1888,7040, 1896,23424, 1904,15232, + 1912,31616, 1928,18304, 1936,10112, 1944,26496, 1952,6016, 1960,22400, + 1968,14208, 1976,30592, 1984,3968, 1992,20352, 2000,12160, 2008,28544, + 2016,8064, 2024,24448, 2032,16256, 2040,32640, 2056,16448, 2064,8256, + 2072,24640, 2080,4160, 2088,20544, 2096,12352, 2104,28736, 2120,18496, + 2128,10304, 2136,26688, 2144,6208, 2152,22592, 2160,14400, 2168,30784, + 2184,17472, 2192,9280, 2200,25664, 2208,5184, 2216,21568, 2224,13376, + 2232,29760, 2240,3136, 2248,19520, 2256,11328, 2264,27712, 2272,7232, + 2280,23616, 2288,15424, 2296,31808, 2312,16960, 2320,8768, 2328,25152, + 2336,4672, 2344,21056, 2352,12864, 2360,29248, 2368,2624, 2376,19008, + 2384,10816, 2392,27200, 2400,6720, 2408,23104, 2416,14912, 2424,31296, + 2440,17984, 2448,9792, 2456,26176, 2464,5696, 2472,22080, 2480,13888, + 2488,30272, 2496,3648, 2504,20032, 2512,11840, 2520,28224, 2528,7744, + 2536,24128, 2544,15936, 2552,32320, 2568,16704, 2576,8512, 2584,24896, + 2592,4416, 2600,20800, 2608,12608, 2616,28992, 2632,18752, 2640,10560, + 2648,26944, 2656,6464, 2664,22848, 2672,14656, 2680,31040, 2696,17728, + 2704,9536, 2712,25920, 2720,5440, 2728,21824, 2736,13632, 2744,30016, 2752,3392, + 2760,19776, 2768,11584, 2776,27968, 2784,7488, 2792,23872, 2800,15680, + 2808,32064, 2824,17216, 2832,9024, 2840,25408, 2848,4928, 2856,21312, + 2864,13120, 2872,29504, 2888,19264, 2896,11072, 2904,27456, 2912,6976, + 2920,23360, 2928,15168, 2936,31552, 2952,18240, 2960,10048, 2968,26432, + 2976,5952, 2984,22336, 2992,14144, 3000,30528, 3008,3904, 3016,20288, + 3024,12096, 3032,28480, 3040,8000, 3048,24384, 3056,16192, 3064,32576, + 3080,16576, 3088,8384, 3096,24768, 3104,4288, 3112,20672, 3120,12480, + 3128,28864, 3144,18624, 3152,10432, 3160,26816, 3168,6336, 3176,22720, + 3184,14528, 3192,30912, 3208,17600, 3216,9408, 3224,25792, 3232,5312, + 3240,21696, 3248,13504, 3256,29888, 3272,19648, 3280,11456, 3288,27840, + 3296,7360, 3304,23744, 3312,15552, 3320,31936, 3336,17088, 3344,8896, + 3352,25280, 3360,4800, 3368,21184, 3376,12992, 3384,29376, 3400,19136, + 3408,10944, 3416,27328, 3424,6848, 3432,23232, 3440,15040, 3448,31424, + 3464,18112, 3472,9920, 3480,26304, 3488,5824, 3496,22208, 3504,14016, + 3512,30400, 3520,3776, 3528,20160, 3536,11968, 3544,28352, 3552,7872, + 3560,24256, 3568,16064, 3576,32448, 3592,16832, 3600,8640, 3608,25024, + 3616,4544, 3624,20928, 3632,12736, 3640,29120, 3656,18880, 3664,10688, + 3672,27072, 3680,6592, 3688,22976, 3696,14784, 3704,31168, 3720,17856, + 3728,9664, 3736,26048, 3744,5568, 3752,21952, 3760,13760, 3768,30144, + 3784,19904, 3792,11712, 3800,28096, 3808,7616, 3816,24000, 3824,15808, + 3832,32192, 3848,17344, 3856,9152, 3864,25536, 3872,5056, 3880,21440, + 3888,13248, 3896,29632, 3912,19392, 3920,11200, 3928,27584, 3936,7104, + 3944,23488, 3952,15296, 3960,31680, 3976,18368, 3984,10176, 3992,26560, + 4000,6080, 4008,22464, 4016,14272, 4024,30656, 4040,20416, 4048,12224, + 4056,28608, 4064,8128, 4072,24512, 4080,16320, 4088,32704, 4104,16416, + 4112,8224, 4120,24608, 4136,20512, 4144,12320, 4152,28704, 4168,18464, + 4176,10272, 4184,26656, 4192,6176, 4200,22560, 4208,14368, 4216,30752, + 4232,17440, 4240,9248, 4248,25632, 4256,5152, 4264,21536, 4272,13344, + 4280,29728, 4296,19488, 4304,11296, 4312,27680, 4320,7200, 4328,23584, + 4336,15392, 4344,31776, 4360,16928, 4368,8736, 4376,25120, 4384,4640, + 4392,21024, 4400,12832, 4408,29216, 4424,18976, 4432,10784, 4440,27168, + 4448,6688, 4456,23072, 4464,14880, 4472,31264, 4488,17952, 4496,9760, + 4504,26144, 4512,5664, 4520,22048, 4528,13856, 4536,30240, 4552,20000, + 4560,11808, 4568,28192, 4576,7712, 4584,24096, 4592,15904, 4600,32288, + 4616,16672, 4624,8480, 4632,24864, 4648,20768, 4656,12576, 4664,28960, + 4680,18720, 4688,10528, 4696,26912, 4704,6432, 4712,22816, 4720,14624, + 4728,31008, 4744,17696, 4752,9504, 4760,25888, 4768,5408, 4776,21792, + 4784,13600, 4792,29984, 4808,19744, 4816,11552, 4824,27936, 4832,7456, + 4840,23840, 4848,15648, 4856,32032, 4872,17184, 4880,8992, 4888,25376, + 4904,21280, 4912,13088, 4920,29472, 4936,19232, 4944,11040, 4952,27424, + 4960,6944, 4968,23328, 4976,15136, 4984,31520, 5000,18208, 5008,10016, + 5016,26400, 5024,5920, 5032,22304, 5040,14112, 5048,30496, 5064,20256, + 5072,12064, 5080,28448, 5088,7968, 5096,24352, 5104,16160, 5112,32544, + 5128,16544, 5136,8352, 5144,24736, 5160,20640, 5168,12448, 5176,28832, + 5192,18592, 5200,10400, 5208,26784, 5216,6304, 5224,22688, 5232,14496, + 5240,30880, 5256,17568, 5264,9376, 5272,25760, 5288,21664, 5296,13472, + 5304,29856, 5320,19616, 5328,11424, 5336,27808, 5344,7328, 5352,23712, + 5360,15520, 5368,31904, 5384,17056, 5392,8864, 5400,25248, 5416,21152, + 5424,12960, 5432,29344, 5448,19104, 5456,10912, 5464,27296, 5472,6816, + 5480,23200, 5488,15008, 5496,31392, 5512,18080, 5520,9888, 5528,26272, + 5536,5792, 5544,22176, 5552,13984, 5560,30368, 5576,20128, 5584,11936, + 5592,28320, 5600,7840, 5608,24224, 5616,16032, 5624,32416, 5640,16800, + 5648,8608, 5656,24992, 5672,20896, 5680,12704, 5688,29088, 5704,18848, + 5712,10656, 5720,27040, 5728,6560, 5736,22944, 5744,14752, 5752,31136, + 5768,17824, 5776,9632, 5784,26016, 5800,21920, 5808,13728, 5816,30112, + 5832,19872, 5840,11680, 5848,28064, 5856,7584, 5864,23968, 5872,15776, + 5880,32160, 5896,17312, 5904,9120, 5912,25504, 5928,21408, 5936,13216, + 5944,29600, 5960,19360, 5968,11168, 5976,27552, 5984,7072, 5992,23456, + 6000,15264, 6008,31648, 6024,18336, 6032,10144, 6040,26528, 6056,22432, + 6064,14240, 6072,30624, 6088,20384, 6096,12192, 6104,28576, 6112,8096, + 6120,24480, 6128,16288, 6136,32672, 6152,16480, 6160,8288, 6168,24672, + 6184,20576, 6192,12384, 6200,28768, 6216,18528, 6224,10336, 6232,26720, + 6248,22624, 6256,14432, 6264,30816, 6280,17504, 6288,9312, 6296,25696, + 6312,21600, 6320,13408, 6328,29792, 6344,19552, 6352,11360, 6360,27744, + 6368,7264, 6376,23648, 6384,15456, 6392,31840, 6408,16992, 6416,8800, + 6424,25184, 6440,21088, 6448,12896, 6456,29280, 6472,19040, 6480,10848, + 6488,27232, 6496,6752, 6504,23136, 6512,14944, 6520,31328, 6536,18016, + 6544,9824, 6552,26208, 6568,22112, 6576,13920, 6584,30304, 6600,20064, + 6608,11872, 6616,28256, 6624,7776, 6632,24160, 6640,15968, 6648,32352, + 6664,16736, 6672,8544, 6680,24928, 6696,20832, 6704,12640, 6712,29024, + 6728,18784, 6736,10592, 6744,26976, 6760,22880, 6768,14688, 6776,31072, + 6792,17760, 6800,9568, 6808,25952, 6824,21856, 6832,13664, 6840,30048, + 6856,19808, 6864,11616, 6872,28000, 6880,7520, 6888,23904, 6896,15712, + 6904,32096, 6920,17248, 6928,9056, 6936,25440, 6952,21344, 6960,13152, + 6968,29536, 6984,19296, 6992,11104, 7000,27488, 7016,23392, 7024,15200, + 7032,31584, 7048,18272, 7056,10080, 7064,26464, 7080,22368, 7088,14176, + 7096,30560, 7112,20320, 7120,12128, 7128,28512, 7136,8032, 7144,24416, + 7152,16224, 7160,32608, 7176,16608, 7184,8416, 7192,24800, 7208,20704, + 7216,12512, 7224,28896, 7240,18656, 7248,10464, 7256,26848, 7272,22752, + 7280,14560, 7288,30944, 7304,17632, 7312,9440, 7320,25824, 7336,21728, + 7344,13536, 7352,29920, 7368,19680, 7376,11488, 7384,27872, 7400,23776, + 7408,15584, 7416,31968, 7432,17120, 7440,8928, 7448,25312, 7464,21216, + 7472,13024, 7480,29408, 7496,19168, 7504,10976, 7512,27360, 7528,23264, + 7536,15072, 7544,31456, 7560,18144, 7568,9952, 7576,26336, 7592,22240, + 7600,14048, 7608,30432, 7624,20192, 7632,12000, 7640,28384, 7648,7904, + 7656,24288, 7664,16096, 7672,32480, 7688,16864, 7696,8672, 7704,25056, + 7720,20960, 7728,12768, 7736,29152, 7752,18912, 7760,10720, 7768,27104, + 7784,23008, 7792,14816, 7800,31200, 7816,17888, 7824,9696, 7832,26080, + 7848,21984, 7856,13792, 7864,30176, 7880,19936, 7888,11744, 7896,28128, + 7912,24032, 7920,15840, 7928,32224, 7944,17376, 7952,9184, 7960,25568, + 7976,21472, 7984,13280, 7992,29664, 8008,19424, 8016,11232, 8024,27616, + 8040,23520, 8048,15328, 8056,31712, 8072,18400, 8080,10208, 8088,26592, + 8104,22496, 8112,14304, 8120,30688, 8136,20448, 8144,12256, 8152,28640, + 8168,24544, 8176,16352, 8184,32736, 8200,16400, 8216,24592, 8232,20496, + 8240,12304, 8248,28688, 8264,18448, 8272,10256, 8280,26640, 8296,22544, + 8304,14352, 8312,30736, 8328,17424, 8336,9232, 8344,25616, 8360,21520, + 8368,13328, 8376,29712, 8392,19472, 8400,11280, 8408,27664, 8424,23568, + 8432,15376, 8440,31760, 8456,16912, 8464,8720, 8472,25104, 8488,21008, + 8496,12816, 8504,29200, 8520,18960, 8528,10768, 8536,27152, 8552,23056, + 8560,14864, 8568,31248, 8584,17936, 8592,9744, 8600,26128, 8616,22032, + 8624,13840, 8632,30224, 8648,19984, 8656,11792, 8664,28176, 8680,24080, + 8688,15888, 8696,32272, 8712,16656, 8728,24848, 8744,20752, 8752,12560, + 8760,28944, 8776,18704, 8784,10512, 8792,26896, 8808,22800, 8816,14608, + 8824,30992, 8840,17680, 8848,9488, 8856,25872, 8872,21776, 8880,13584, + 8888,29968, 8904,19728, 8912,11536, 8920,27920, 8936,23824, 8944,15632, + 8952,32016, 8968,17168, 8984,25360, 9000,21264, 9008,13072, 9016,29456, + 9032,19216, 9040,11024, 9048,27408, 9064,23312, 9072,15120, 9080,31504, + 9096,18192, 9104,10000, 9112,26384, 9128,22288, 9136,14096, 9144,30480, + 9160,20240, 9168,12048, 9176,28432, 9192,24336, 9200,16144, 9208,32528, + 9224,16528, 9240,24720, 9256,20624, 9264,12432, 9272,28816, 9288,18576, + 9296,10384, 9304,26768, 9320,22672, 9328,14480, 9336,30864, 9352,17552, + 9368,25744, 9384,21648, 9392,13456, 9400,29840, 9416,19600, 9424,11408, + 9432,27792, 9448,23696, 9456,15504, 9464,31888, 9480,17040, 9496,25232, + 9512,21136, 9520,12944, 9528,29328, 9544,19088, 9552,10896, 9560,27280, + 9576,23184, 9584,14992, 9592,31376, 9608,18064, 9616,9872, 9624,26256, + 9640,22160, 9648,13968, 9656,30352, 9672,20112, 9680,11920, 9688,28304, + 9704,24208, 9712,16016, 9720,32400, 9736,16784, 9752,24976, 9768,20880, + 9776,12688, 9784,29072, 9800,18832, 9808,10640, 9816,27024, 9832,22928, + 9840,14736, 9848,31120, 9864,17808, 9880,26000, 9896,21904, 9904,13712, + 9912,30096, 9928,19856, 9936,11664, 9944,28048, 9960,23952, 9968,15760, + 9976,32144, 9992,17296, 10008,25488, 10024,21392, 10032,13200, 10040,29584, + 10056,19344, 10064,11152, 10072,27536, 10088,23440, 10096,15248, 10104,31632, + 10120,18320, 10136,26512, 10152,22416, 10160,14224, 10168,30608, 10184,20368, + 10192,12176, 10200,28560, 10216,24464, 10224,16272, 10232,32656, 10248,16464, + 10264,24656, 10280,20560, 10288,12368, 10296,28752, 10312,18512, 10328,26704, + 10344,22608, 10352,14416, 10360,30800, 10376,17488, 10392,25680, 10408,21584, + 10416,13392, 10424,29776, 10440,19536, 10448,11344, 10456,27728, 10472,23632, + 10480,15440, 10488,31824, 10504,16976, 10520,25168, 10536,21072, 10544,12880, + 10552,29264, 10568,19024, 10576,10832, 10584,27216, 10600,23120, 10608,14928, + 10616,31312, 10632,18000, 10648,26192, 10664,22096, 10672,13904, 10680,30288, + 10696,20048, 10704,11856, 10712,28240, 10728,24144, 10736,15952, 10744,32336, + 10760,16720, 10776,24912, 10792,20816, 10800,12624, 10808,29008, 10824,18768, + 10840,26960, 10856,22864, 10864,14672, 10872,31056, 10888,17744, 10904,25936, + 10920,21840, 10928,13648, 10936,30032, 10952,19792, 10960,11600, 10968,27984, + 10984,23888, 10992,15696, 11000,32080, 11016,17232, 11032,25424, 11048,21328, + 11056,13136, 11064,29520, 11080,19280, 11096,27472, 11112,23376, 11120,15184, + 11128,31568, 11144,18256, 11160,26448, 11176,22352, 11184,14160, 11192,30544, + 11208,20304, 11216,12112, 11224,28496, 11240,24400, 11248,16208, 11256,32592, + 11272,16592, 11288,24784, 11304,20688, 11312,12496, 11320,28880, 11336,18640, + 11352,26832, 11368,22736, 11376,14544, 11384,30928, 11400,17616, 11416,25808, + 11432,21712, 11440,13520, 11448,29904, 11464,19664, 11480,27856, 11496,23760, + 11504,15568, 11512,31952, 11528,17104, 11544,25296, 11560,21200, 11568,13008, + 11576,29392, 11592,19152, 11608,27344, 11624,23248, 11632,15056, 11640,31440, + 11656,18128, 11672,26320, 11688,22224, 11696,14032, 11704,30416, 11720,20176, + 11728,11984, 11736,28368, 11752,24272, 11760,16080, 11768,32464, 11784,16848, + 11800,25040, 11816,20944, 11824,12752, 11832,29136, 11848,18896, 11864,27088, + 11880,22992, 11888,14800, 11896,31184, 11912,17872, 11928,26064, 11944,21968, + 11952,13776, 11960,30160, 11976,19920, 11992,28112, 12008,24016, 12016,15824, + 12024,32208, 12040,17360, 12056,25552, 12072,21456, 12080,13264, 12088,29648, + 12104,19408, 12120,27600, 12136,23504, 12144,15312, 12152,31696, 12168,18384, + 12184,26576, 12200,22480, 12208,14288, 12216,30672, 12232,20432, 12248,28624, + 12264,24528, 12272,16336, 12280,32720, 12296,16432, 12312,24624, 12328,20528, + 12344,28720, 12360,18480, 12376,26672, 12392,22576, 12400,14384, 12408,30768, + 12424,17456, 12440,25648, 12456,21552, 12464,13360, 12472,29744, 12488,19504, + 12504,27696, 12520,23600, 12528,15408, 12536,31792, 12552,16944, 12568,25136, + 12584,21040, 12592,12848, 12600,29232, 12616,18992, 12632,27184, 12648,23088, + 12656,14896, 12664,31280, 12680,17968, 12696,26160, 12712,22064, 12720,13872, + 12728,30256, 12744,20016, 12760,28208, 12776,24112, 12784,15920, 12792,32304, + 12808,16688, 12824,24880, 12840,20784, 12856,28976, 12872,18736, 12888,26928, + 12904,22832, 12912,14640, 12920,31024, 12936,17712, 12952,25904, 12968,21808, + 12976,13616, 12984,30000, 13000,19760, 13016,27952, 13032,23856, 13040,15664, + 13048,32048, 13064,17200, 13080,25392, 13096,21296, 13112,29488, 13128,19248, + 13144,27440, 13160,23344, 13168,15152, 13176,31536, 13192,18224, 13208,26416, + 13224,22320, 13232,14128, 13240,30512, 13256,20272, 13272,28464, 13288,24368, + 13296,16176, 13304,32560, 13320,16560, 13336,24752, 13352,20656, 13368,28848, + 13384,18608, 13400,26800, 13416,22704, 13424,14512, 13432,30896, 13448,17584, + 13464,25776, 13480,21680, 13496,29872, 13512,19632, 13528,27824, 13544,23728, + 13552,15536, 13560,31920, 13576,17072, 13592,25264, 13608,21168, 13624,29360, + 13640,19120, 13656,27312, 13672,23216, 13680,15024, 13688,31408, 13704,18096, + 13720,26288, 13736,22192, 13744,14000, 13752,30384, 13768,20144, 13784,28336, + 13800,24240, 13808,16048, 13816,32432, 13832,16816, 13848,25008, 13864,20912, + 13880,29104, 13896,18864, 13912,27056, 13928,22960, 13936,14768, 13944,31152, + 13960,17840, 13976,26032, 13992,21936, 14008,30128, 14024,19888, 14040,28080, + 14056,23984, 14064,15792, 14072,32176, 14088,17328, 14104,25520, 14120,21424, + 14136,29616, 14152,19376, 14168,27568, 14184,23472, 14192,15280, 14200,31664, + 14216,18352, 14232,26544, 14248,22448, 14264,30640, 14280,20400, 14296,28592, + 14312,24496, 14320,16304, 14328,32688, 14344,16496, 14360,24688, 14376,20592, + 14392,28784, 14408,18544, 14424,26736, 14440,22640, 14456,30832, 14472,17520, + 14488,25712, 14504,21616, 14520,29808, 14536,19568, 14552,27760, 14568,23664, + 14576,15472, 14584,31856, 14600,17008, 14616,25200, 14632,21104, 14648,29296, + 14664,19056, 14680,27248, 14696,23152, 14704,14960, 14712,31344, 14728,18032, + 14744,26224, 14760,22128, 14776,30320, 14792,20080, 14808,28272, 14824,24176, + 14832,15984, 14840,32368, 14856,16752, 14872,24944, 14888,20848, 14904,29040, + 14920,18800, 14936,26992, 14952,22896, 14968,31088, 14984,17776, 15000,25968, + 15016,21872, 15032,30064, 15048,19824, 15064,28016, 15080,23920, 15088,15728, + 15096,32112, 15112,17264, 15128,25456, 15144,21360, 15160,29552, 15176,19312, + 15192,27504, 15208,23408, 15224,31600, 15240,18288, 15256,26480, 15272,22384, + 15288,30576, 15304,20336, 15320,28528, 15336,24432, 15344,16240, 15352,32624, + 15368,16624, 15384,24816, 15400,20720, 15416,28912, 15432,18672, 15448,26864, + 15464,22768, 15480,30960, 15496,17648, 15512,25840, 15528,21744, 15544,29936, + 15560,19696, 15576,27888, 15592,23792, 15608,31984, 15624,17136, 15640,25328, + 15656,21232, 15672,29424, 15688,19184, 15704,27376, 15720,23280, 15736,31472, + 15752,18160, 15768,26352, 15784,22256, 15800,30448, 15816,20208, 15832,28400, + 15848,24304, 15856,16112, 15864,32496, 15880,16880, 15896,25072, 15912,20976, + 15928,29168, 15944,18928, 15960,27120, 15976,23024, 15992,31216, 16008,17904, + 16024,26096, 16040,22000, 16056,30192, 16072,19952, 16088,28144, 16104,24048, + 16120,32240, 16136,17392, 16152,25584, 16168,21488, 16184,29680, 16200,19440, + 16216,27632, 16232,23536, 16248,31728, 16264,18416, 16280,26608, 16296,22512, + 16312,30704, 16328,20464, 16344,28656, 16360,24560, 16376,32752, 16408,24584, + 16424,20488, 16440,28680, 16456,18440, 16472,26632, 16488,22536, 16504,30728, + 16520,17416, 16536,25608, 16552,21512, 16568,29704, 16584,19464, 16600,27656, + 16616,23560, 16632,31752, 16648,16904, 16664,25096, 16680,21000, 16696,29192, + 16712,18952, 16728,27144, 16744,23048, 16760,31240, 16776,17928, 16792,26120, + 16808,22024, 16824,30216, 16840,19976, 16856,28168, 16872,24072, 16888,32264, + 16920,24840, 16936,20744, 16952,28936, 16968,18696, 16984,26888, 17000,22792, + 17016,30984, 17032,17672, 17048,25864, 17064,21768, 17080,29960, 17096,19720, + 17112,27912, 17128,23816, 17144,32008, 17176,25352, 17192,21256, 17208,29448, + 17224,19208, 17240,27400, 17256,23304, 17272,31496, 17288,18184, 17304,26376, + 17320,22280, 17336,30472, 17352,20232, 17368,28424, 17384,24328, 17400,32520, + 17432,24712, 17448,20616, 17464,28808, 17480,18568, 17496,26760, 17512,22664, + 17528,30856, 17560,25736, 17576,21640, 17592,29832, 17608,19592, 17624,27784, + 17640,23688, 17656,31880, 17688,25224, 17704,21128, 17720,29320, 17736,19080, + 17752,27272, 17768,23176, 17784,31368, 17800,18056, 17816,26248, 17832,22152, + 17848,30344, 17864,20104, 17880,28296, 17896,24200, 17912,32392, 17944,24968, + 17960,20872, 17976,29064, 17992,18824, 18008,27016, 18024,22920, 18040,31112, + 18072,25992, 18088,21896, 18104,30088, 18120,19848, 18136,28040, 18152,23944, + 18168,32136, 18200,25480, 18216,21384, 18232,29576, 18248,19336, 18264,27528, + 18280,23432, 18296,31624, 18328,26504, 18344,22408, 18360,30600, 18376,20360, + 18392,28552, 18408,24456, 18424,32648, 18456,24648, 18472,20552, 18488,28744, + 18520,26696, 18536,22600, 18552,30792, 18584,25672, 18600,21576, 18616,29768, + 18632,19528, 18648,27720, 18664,23624, 18680,31816, 18712,25160, 18728,21064, + 18744,29256, 18760,19016, 18776,27208, 18792,23112, 18808,31304, 18840,26184, + 18856,22088, 18872,30280, 18888,20040, 18904,28232, 18920,24136, 18936,32328, + 18968,24904, 18984,20808, 19000,29000, 19032,26952, 19048,22856, 19064,31048, + 19096,25928, 19112,21832, 19128,30024, 19144,19784, 19160,27976, 19176,23880, + 19192,32072, 19224,25416, 19240,21320, 19256,29512, 19288,27464, 19304,23368, + 19320,31560, 19352,26440, 19368,22344, 19384,30536, 19400,20296, 19416,28488, + 19432,24392, 19448,32584, 19480,24776, 19496,20680, 19512,28872, 19544,26824, + 19560,22728, 19576,30920, 19608,25800, 19624,21704, 19640,29896, 19672,27848, + 19688,23752, 19704,31944, 19736,25288, 19752,21192, 19768,29384, 19800,27336, + 19816,23240, 19832,31432, 19864,26312, 19880,22216, 19896,30408, 19912,20168, + 19928,28360, 19944,24264, 19960,32456, 19992,25032, 20008,20936, 20024,29128, + 20056,27080, 20072,22984, 20088,31176, 20120,26056, 20136,21960, 20152,30152, + 20184,28104, 20200,24008, 20216,32200, 20248,25544, 20264,21448, 20280,29640, + 20312,27592, 20328,23496, 20344,31688, 20376,26568, 20392,22472, 20408,30664, + 20440,28616, 20456,24520, 20472,32712, 20504,24616, 20536,28712, 20568,26664, + 20584,22568, 20600,30760, 20632,25640, 20648,21544, 20664,29736, 20696,27688, + 20712,23592, 20728,31784, 20760,25128, 20776,21032, 20792,29224, 20824,27176, + 20840,23080, 20856,31272, 20888,26152, 20904,22056, 20920,30248, 20952,28200, + 20968,24104, 20984,32296, 21016,24872, 21048,28968, 21080,26920, 21096,22824, + 21112,31016, 21144,25896, 21160,21800, 21176,29992, 21208,27944, 21224,23848, + 21240,32040, 21272,25384, 21304,29480, 21336,27432, 21352,23336, 21368,31528, + 21400,26408, 21416,22312, 21432,30504, 21464,28456, 21480,24360, 21496,32552, + 21528,24744, 21560,28840, 21592,26792, 21608,22696, 21624,30888, 21656,25768, + 21688,29864, 21720,27816, 21736,23720, 21752,31912, 21784,25256, 21816,29352, + 21848,27304, 21864,23208, 21880,31400, 21912,26280, 21928,22184, 21944,30376, + 21976,28328, 21992,24232, 22008,32424, 22040,25000, 22072,29096, 22104,27048, + 22120,22952, 22136,31144, 22168,26024, 22200,30120, 22232,28072, 22248,23976, + 22264,32168, 22296,25512, 22328,29608, 22360,27560, 22376,23464, 22392,31656, + 22424,26536, 22456,30632, 22488,28584, 22504,24488, 22520,32680, 22552,24680, + 22584,28776, 22616,26728, 22648,30824, 22680,25704, 22712,29800, 22744,27752, + 22760,23656, 22776,31848, 22808,25192, 22840,29288, 22872,27240, 22888,23144, + 22904,31336, 22936,26216, 22968,30312, 23000,28264, 23016,24168, 23032,32360, + 23064,24936, 23096,29032, 23128,26984, 23160,31080, 23192,25960, 23224,30056, + 23256,28008, 23272,23912, 23288,32104, 23320,25448, 23352,29544, 23384,27496, + 23416,31592, 23448,26472, 23480,30568, 23512,28520, 23528,24424, 23544,32616, + 23576,24808, 23608,28904, 23640,26856, 23672,30952, 23704,25832, 23736,29928, + 23768,27880, 23800,31976, 23832,25320, 23864,29416, 23896,27368, 23928,31464, + 23960,26344, 23992,30440, 24024,28392, 24040,24296, 24056,32488, 24088,25064, + 24120,29160, 24152,27112, 24184,31208, 24216,26088, 24248,30184, 24280,28136, + 24312,32232, 24344,25576, 24376,29672, 24408,27624, 24440,31720, 24472,26600, + 24504,30696, 24536,28648, 24568,32744, 24632,28696, 24664,26648, 24696,30744, + 24728,25624, 24760,29720, 24792,27672, 24824,31768, 24856,25112, 24888,29208, + 24920,27160, 24952,31256, 24984,26136, 25016,30232, 25048,28184, 25080,32280, + 25144,28952, 25176,26904, 25208,31000, 25240,25880, 25272,29976, 25304,27928, + 25336,32024, 25400,29464, 25432,27416, 25464,31512, 25496,26392, 25528,30488, + 25560,28440, 25592,32536, 25656,28824, 25688,26776, 25720,30872, 25784,29848, + 25816,27800, 25848,31896, 25912,29336, 25944,27288, 25976,31384, 26008,26264, + 26040,30360, 26072,28312, 26104,32408, 26168,29080, 26200,27032, 26232,31128, + 26296,30104, 26328,28056, 26360,32152, 26424,29592, 26456,27544, 26488,31640, + 26552,30616, 26584,28568, 26616,32664, 26680,28760, 26744,30808, 26808,29784, + 26840,27736, 26872,31832, 26936,29272, 26968,27224, 27000,31320, 27064,30296, + 27096,28248, 27128,32344, 27192,29016, 27256,31064, 27320,30040, 27352,27992, + 27384,32088, 27448,29528, 27512,31576, 27576,30552, 27608,28504, 27640,32600, + 27704,28888, 27768,30936, 27832,29912, 27896,31960, 27960,29400, 28024,31448, + 28088,30424, 28120,28376, 28152,32472, 28216,29144, 28280,31192, 28344,30168, + 28408,32216, 28472,29656, 28536,31704, 28600,30680, 28664,32728, 28792,30776, + 28856,29752, 28920,31800, 28984,29240, 29048,31288, 29112,30264, 29176,32312, + 29304,31032, 29368,30008, 29432,32056, 29560,31544, 29624,30520, 29688,32568, + 29816,30904, 29944,31928, 30072,31416, 30136,30392, 30200,32440, 30328,31160, + 30456,32184, 30584,31672, 30712,32696, 30968,31864, 31096,31352, 31224,32376, + 31480,32120, 31736,32632, 32248,32504 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32) +/** + @par + Example code for Double Precision Floating-point RFFT Twiddle factors Generation: + @par +
TW = exp(pi/2*i-2*pi*i*[0:L/2-1]/L).' 
+ @par + Real and Imag values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_rfft_32[32] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, //0.19509, 0.98079 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, //0.38268, 0.92388 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, //0.55557, 0.83147 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, //0.70711, 0.70711 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, //0.83147, 0.55557 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, //0.92388, 0.38268 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, //0.98079, 0.19509 + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, //0.98079,-0.19509 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, //0.92388,-0.38268 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, //0.83147,-0.55557 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, //0.70711,-0.70711 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, //0.55557,-0.83147 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, //0.38268,-0.92388 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, //0.19509,-0.98079 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64) +const uint64_t twiddleCoefF64_rfft_64[64] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, //0.098017, 0.99518' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, //0.098017, -0.99518' +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128) +const uint64_t twiddleCoefF64_rfft_128[128] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, //0.049068, 0.9988' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, //0.098017, 0.99518' + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068' + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017' + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, //0.098017, -0.99518' + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, //0.049068, -0.9988' +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256) +const uint64_t twiddleCoefF64_rfft_256[256] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, //0.024541, 0.9997 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, //0.049068, 0.9988 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, //0.073565, 0.99729 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, //0.098017, 0.99518 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997,-0.024541 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729,-0.073565 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, //0.098017, -0.99518 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, //0.073565, -0.99729 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, //0.049068, -0.9988' + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, //0.024541, -0.9997 + + +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512) +const uint64_t twiddleCoefF64_rfft_512[512] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0x3f8921d1fcdec784, 0x3fefff62169b92db, //0.012272, 0.99992' + 0x3f992155f7a3667e, 0x3feffd886084cd0d, //0.024541, 0.9997' + 0x3fa2d865759455cd, 0x3feffa72effef75d, //0.036807, 0.99932' + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, //0.049068, 0.9988' + 0x3faf656e79f820e0, 0x3feff095658e71ad, //0.061321, 0.99812' + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, //0.073565, 0.99729' + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, //0.085797, 0.99631' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, //0.098017, 0.99518' + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391' + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248' + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909' + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918' + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873' + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528' + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832' + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757' + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294' + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003' + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698' + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378' + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331' + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953' + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561' + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154' + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734' + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299' + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911' + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421' + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917' + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399' + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867' + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322' + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607' + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009' + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397' + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773' + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136' + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485' + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459' + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758' + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046' + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321' + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584' + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835' + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517' + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721' + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914' + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095' + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265' + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425' + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838' + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954' + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806' + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156' + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242' + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317' + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486' + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523' + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551' + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957' + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858' + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581' + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532' + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535' + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459' + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141' + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354' + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929' + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054' + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961' + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862' + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756' + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643' + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524' + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132' + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599' + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842' + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689' + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531' + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368' + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852' + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671' + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487' + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298' + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106' + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191' + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304' + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096' + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886' + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673' + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458' + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241' + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797' + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565' + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321' + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068' + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807' + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541' + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272' + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992,-0.012272' + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997,-0.024541' + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932,-0.036807' + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068' + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812,-0.061321' + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729,-0.073565' + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631,-0.085797' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017' + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022' + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241' + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458' + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673' + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886' + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096' + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711' + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191' + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106' + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298' + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487' + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671' + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201' + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368' + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531' + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689' + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842' + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599' + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399' + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524' + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643' + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756' + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862' + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961' + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218' + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929' + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354' + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141' + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459' + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535' + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573' + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581' + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858' + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957' + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551' + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523' + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383' + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317' + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242' + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156' + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806' + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954' + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573' + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425' + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265' + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095' + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914' + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721' + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074' + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835' + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584' + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321' + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046' + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758' + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822' + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485' + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136' + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773' + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397' + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009' + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764' + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322' + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867' + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399' + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917' + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421' + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851' + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299' + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734' + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154' + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561' + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953' + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043' + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378' + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698' + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003' + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294' + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757' + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311' + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528' + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873' + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918' + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909' + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248' + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, //0.098017, -0.99518' + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, //0.085797, -0.99631' + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, //0.073565, -0.99729' + 0x3faf656e79f820e0, 0xbfeff095658e71ad, //0.061321, -0.99812' + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, //0.049068, -0.9988' + 0x3fa2d865759455cd, 0xbfeffa72effef75d, //0.036807, -0.99932' + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, //0.024541, -0.9997' + 0x3f8921d1fcdec784, 0xbfefff62169b92db, //0.012272, -0.99992' + + +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024) +const uint64_t twiddleCoefF64_rfft_1024[1024] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, //0.0061359, 0.99998' + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992' + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983' + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997' + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953' + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932' + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908' + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988' + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848' + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812' + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772' + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729' + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682' + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631' + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518' + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456' + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391' + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321' + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248' + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171' + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909' + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006' + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918' + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826' + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873' + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631' + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528' + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421' + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311' + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957' + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832' + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703' + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757' + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434' + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294' + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715' + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003' + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852' + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698' + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539' + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378' + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212' + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043' + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514' + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331' + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144' + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953' + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759' + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561' + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359' + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154' + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946' + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734' + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518' + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299' + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077' + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851' + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151' + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911' + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668' + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421' + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171' + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917' + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066' + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399' + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135' + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867' + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597' + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322' + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045' + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764' + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901' + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607' + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309' + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009' + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705' + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397' + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087' + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773' + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456' + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136' + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812' + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485' + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155' + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822' + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805' + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459' + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211' + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758' + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404' + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046' + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685' + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321' + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954' + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584' + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211' + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835' + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456' + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074' + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691' + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517' + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612' + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721' + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319' + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914' + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506' + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095' + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682' + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265' + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846' + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425' + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72' + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573' + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275' + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838' + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397' + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954' + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508' + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806' + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609' + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156' + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667' + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242' + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781' + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317' + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851' + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383' + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964' + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486' + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006' + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523' + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038' + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551' + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062' + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957' + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076' + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858' + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081' + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581' + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078' + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573' + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046' + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532' + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017' + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535' + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298' + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459' + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936' + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141' + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883' + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354' + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823' + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929' + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755' + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218' + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598' + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054' + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508' + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961' + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412' + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862' + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309' + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756' + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422' + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643' + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084' + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524' + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962' + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399' + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701' + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132' + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561' + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599' + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416' + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842' + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266' + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689' + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111' + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531' + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195' + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368' + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785' + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201' + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441' + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852' + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262' + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671' + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079' + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487' + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893' + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298' + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702' + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106' + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508' + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191' + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311' + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711' + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907' + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304' + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177' + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096' + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491' + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886' + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528' + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673' + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066' + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458' + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285' + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241' + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632' + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022' + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909' + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797' + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682' + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565' + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444' + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321' + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195' + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068' + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938' + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807' + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675' + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541' + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407' + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272' + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359' + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359' + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272' + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407' + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541' + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675' + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807' + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938' + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068' + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195' + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321' + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444' + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565' + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682' + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797' + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017' + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412' + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022' + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632' + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241' + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285' + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458' + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066' + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673' + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528' + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886' + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491' + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096' + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177' + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304' + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011' + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711' + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311' + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191' + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508' + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106' + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702' + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298' + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893' + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487' + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079' + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671' + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262' + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852' + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615' + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201' + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785' + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368' + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195' + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531' + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111' + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689' + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266' + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842' + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416' + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599' + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561' + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132' + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835' + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399' + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962' + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524' + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084' + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643' + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422' + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756' + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309' + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862' + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412' + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961' + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508' + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054' + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768' + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218' + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755' + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929' + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823' + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354' + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883' + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141' + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936' + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459' + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298' + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535' + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017' + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532' + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066' + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573' + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078' + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581' + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081' + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858' + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076' + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957' + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062' + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551' + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038' + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523' + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006' + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486' + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912' + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383' + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851' + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317' + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781' + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242' + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667' + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156' + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609' + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806' + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508' + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954' + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397' + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838' + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143' + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573' + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72' + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425' + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846' + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265' + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682' + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095' + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506' + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914' + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319' + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721' + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612' + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517' + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689' + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074' + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456' + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835' + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211' + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584' + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954' + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321' + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685' + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046' + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404' + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758' + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211' + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459' + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486' + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822' + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155' + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485' + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812' + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136' + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456' + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773' + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087' + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397' + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705' + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009' + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309' + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607' + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848' + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764' + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045' + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322' + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597' + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867' + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135' + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399' + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066' + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917' + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171' + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421' + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668' + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911' + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621' + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851' + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077' + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299' + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518' + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734' + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946' + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154' + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359' + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561' + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759' + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953' + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144' + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331' + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587' + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043' + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212' + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378' + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539' + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698' + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852' + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003' + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715' + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294' + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434' + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757' + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703' + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832' + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196' + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311' + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421' + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528' + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631' + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873' + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826' + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918' + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006' + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909' + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171' + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248' + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321' + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391' + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518' + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577' + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631' + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682' + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729' + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772' + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812' + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848' + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988' + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908' + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932' + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953' + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997' + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983' + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992' + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, //0.0061359, -0.99998' +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048) +const uint64_t twiddleCoefF64_rfft_2048[2048] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0x3f6921f8becca4ba, 0x3feffff621621d02, // 0.003068, 1 + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, //0.0061359, 0.99998 + 0x3f82d96b0e509703, 0x3fefffa72c978c4f, //0.0092038, 0.99996 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x3f8f6a296ab997ca, 0x3fefff0943c53bd1, // 0.015339, 0.99988 + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983 + 0x3f95fd4d21fab226, 0x3feffe1c6870cb77, // 0.021474, 0.99977 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f9c454f4ce53b1c, 0x3feffce09ce2a679, // 0.027608, 0.99962 + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953 + 0x3fa14685db42c17e, 0x3feffb55e425fdae, // 0.033741, 0.99943 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3fa46a396ff86179, 0x3feff97c4208c014, // 0.039873, 0.9992 + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908 + 0x3fa78dbaa5874685, 0x3feff753bb1b9164, // 0.046003, 0.99894 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3faab101bd5f8317, 0x3feff4dc54b1bed3, // 0.052132, 0.99864 + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848 + 0x3fadd406f9808ec8, 0x3feff21614e131ed, // 0.058258, 0.9983 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fb07b614e463064, 0x3fefef0102826191, // 0.064383, 0.99793 + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772 + 0x3fb20c9674ed444c, 0x3fefeb9d2530410f, // 0.070505, 0.99751 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fb39d9f12c5a299, 0x3fefe7ea85482d60, // 0.076624, 0.99706 + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682 + 0x3fb52e774a4d4d0a, 0x3fefe3e92be9d886, // 0.08274, 0.99657 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb6bf1b3e79b129, 0x3fefdf9922f73307, // 0.088854, 0.99604 + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577 + 0x3fb84f8712c130a0, 0x3fefdafa7514538c, // 0.094963, 0.99548 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // 0.10107, 0.99488 + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456 + 0x3fbb6fa6ec38f64c, 0x3fefd0d158d86087, // 0.10717, 0.99424 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fbcff533b307dc1, 0x3fefcb4703914354, // 0.11327, 0.99356 + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321 + 0x3fbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // 0.11937, 0.99285 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // 0.12545, 0.9921 + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171 + 0x3fc0d64dbcb26786, 0x3fefb8d18d66adb7, // 0.13154, 0.99131 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fc19d8940be24e7, 0x3fefb20dc681d54d, // 0.13762, 0.99049 + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006 + 0x3fc264994dfd340a, 0x3fefaafbcb0cfddc, // 0.1437, 0.98962 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc32b7bf94516a7, 0x3fefa39bac7a1791, // 0.14976, 0.98872 + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826 + 0x3fc3f22f57db4893, 0x3fef9bed7cfbde29, // 0.15583, 0.98778 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc4b8b17f79fa88, 0x3fef93f14f85ac08, // 0.16189, 0.98681 + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631 + 0x3fc57f008654cbde, 0x3fef8ba737cb4b78, // 0.16794, 0.9858 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc6451a831d830d, 0x3fef830f4a40c60c, // 0.17398, 0.98475 + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421 + 0x3fc70afd8d08c4ff, 0x3fef7a299c1a322a, // 0.18002, 0.98366 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // 0.18606, 0.98254 + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196 + 0x3fc8961727c41804, 0x3fef677556883cee, // 0.19208, 0.98138 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc95b49e9b62af9, 0x3fef5da6ed43685d, // 0.1981, 0.98018 + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957 + 0x3fca203e1b1831da, 0x3fef538b1faf2d07, // 0.20411, 0.97895 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fcae4f1d5f3b9ab, 0x3fef492206bcabb4, // 0.21011, 0.97768 + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703 + 0x3fcba96334f15dad, 0x3fef3e6bbc1bbc65, // 0.21611, 0.97637 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcc6d90535d74dc, 0x3fef33685a3aaef0, // 0.22209, 0.97503 + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434 + 0x3fcd31774d2cbdee, 0x3fef2817fc4609ce, // 0.22807, 0.97364 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcdf5163f01099a, 0x3fef1c7abe284708, // 0.23404, 0.97223 + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715 + 0x3fceb86b462de348, 0x3fef1090bc898f5f, // 0.24, 0.97077 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fcf7b7480bd3801, 0x3fef045a14cf738c, // 0.24596, 0.96928 + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852 + 0x3fd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // 0.2519, 0.96775 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fd0804e05eb661e, 0x3feeeb074c50a544, // 0.25783, 0.96619 + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539 + 0x3fd0e15b4e1749cd, 0x3feeddeb6a078651, // 0.26375, 0.96459 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd1423eefc69378, 0x3feed0835e999009, // 0.26967, 0.96295 + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212 + 0x3fd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // 0.27557, 0.96128 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd2038583d727bd, 0x3feeb4cf515b8811, // 0.28146, 0.95957 + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587 + 0x3fd263e6995554ba, 0x3feea68393e65800, // 0.28735, 0.95783 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd2c41a4e954520, 0x3fee97ec36016b30, // 0.29322, 0.95605 + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514 + 0x3fd3241fb638baaf, 0x3fee89095bad6025, // 0.29908, 0.95423 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd383f5e353b6aa, 0x3fee79db29a5165a, // 0.30493, 0.95238 + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144 + 0x3fd3e39be96ec271, 0x3fee6a61c55d53a7, // 0.31077, 0.95049 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd44310dc8936f0, 0x3fee5a9d550467d3, // 0.31659, 0.94856 + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759 + 0x3fd4a253d11b82f3, 0x3fee4a8dff81ce5e, // 0.32241, 0.9466 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd50163dc197047, 0x3fee3a33ec75ce85, // 0.32821, 0.9446 + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359 + 0x3fd5604012f467b4, 0x3fee298f4439197a, // 0.334, 0.94257 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd5bee78b9db3b6, 0x3fee18a02fdc66d9, // 0.33978, 0.94051 + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946 + 0x3fd61d595c88c203, 0x3fee0766d9280f54, // 0.34554, 0.9384 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd67b949cad63ca, 0x3fedf5e36a9ba59c, // 0.35129, 0.93627 + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518 + 0x3fd6d998638a0cb5, 0x3fede4160f6d8d81, // 0.35703, 0.93409 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd73763c9261092, 0x3fedd1fef38a915a, // 0.36276, 0.93188 + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077 + 0x3fd794f5e613dfae, 0x3fedbf9e4395759a, // 0.36847, 0.92964 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd7f24dd37341e3, 0x3fedacf42ce68ab9, // 0.37416, 0.92736 + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621 + 0x3fd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // 0.37985, 0.92505 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd8ac4b86d5ed44, 0x3fed86c48445a450, // 0.38552, 0.9227 + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151 + 0x3fd908ef81ef7bd1, 0x3fed733f508c0dff, // 0.39117, 0.92032 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd96555b7ab948f, 0x3fed5f7172888a7f, // 0.39681, 0.9179 + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668 + 0x3fd9c17d440df9f2, 0x3fed4b5b1b187524, // 0.40243, 0.91545 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // 0.40804, 0.91296 + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171 + 0x3fda790cd3dbf31a, 0x3fed2255c6e5a4e1, // 0.41364, 0.91044 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fdad473125cdc08, 0x3fed0d672f59d2b9, // 0.41922, 0.90789 + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066 + 0x3fdb2f971db31972, 0x3fecf830e8ce467b, // 0.42478, 0.9053 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdb8a7814fd5693, 0x3fece2b32799a060, // 0.43033, 0.90267 + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135 + 0x3fdbe51517ffc0d9, 0x3fecccee20c2de9f, // 0.43586, 0.90002 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdc3f6d47263129, 0x3fecb6e20a00da99, // 0.44137, 0.89732 + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597 + 0x3fdc997fc3865388, 0x3feca08f19b9c449, // 0.44687, 0.8946 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdcf34baee1cd21, 0x3fec89f587029c13, // 0.45235, 0.89184 + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045 + 0x3fdd4cd02ba8609c, 0x3fec7315899eaad7, // 0.45781, 0.88905 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdda60c5cfa10d8, 0x3fec5bef59fef85a, // 0.46326, 0.88622 + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848 + 0x3fddfeff66a941de, 0x3fec44833141c004, // 0.46869, 0.88336 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fde57a86d3cd824, 0x3fec2cd14931e3f1, // 0.4741, 0.88047 + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901 + 0x3fdeb00695f25620, 0x3fec14d9dc465e58, // 0.47949, 0.87755 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fdf081906bff7fd, 0x3febfc9d25a1b147, // 0.48487, 0.87459 + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309 + 0x3fdf5fdee656cda3, 0x3febe41b611154c1, // 0.49023, 0.8716 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdfb7575c24d2de, 0x3febcb54cb0d2327, // 0.49557, 0.86857 + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705 + 0x3fe00740c82b82e0, 0x3febb249a0b6c40d, // 0.50089, 0.86551 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fe032ae55edbd95, 0x3feb98fa1fd9155e, // 0.50619, 0.86242 + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087 + 0x3fe05df3ec31b8b6, 0x3feb7f6686e792ea, // 0.51147, 0.8593 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe089112032b08c, 0x3feb658f14fdbc47, // 0.51673, 0.85615 + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456 + 0x3fe0b405878f85ec, 0x3feb4b7409de7925, // 0.52198, 0.85296 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // 0.5272, 0.84974 + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812 + 0x3fe1097248d0a956, 0x3feb16742a4ca2f5, // 0.5324, 0.84649 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe133e9cfee254e, 0x3feafb8fd89f57b6, // 0.53759, 0.84321 + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155 + 0x3fe15e36e4dbe2bc, 0x3feae068f345ecef, // 0.54275, 0.83989 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe188591f3a46e5, 0x3feac4ffbd3efac8, // 0.54789, 0.83655 + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486 + 0x3fe1b250171373be, 0x3feaa9547a2cb98e, // 0.55302, 0.83317 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe1dc1b64dc4872, 0x3fea8d676e545ad2, // 0.55812, 0.82976 + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805 + 0x3fe205baa17560d6, 0x3fea7138de9d60f5, // 0.5632, 0.82632 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe22f2d662c13e1, 0x3fea54c91090f524, // 0.56826, 0.82285 + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211 + 0x3fe258734cbb7110, 0x3fea38184a593bc6, // 0.5733, 0.81935 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe2818bef4d3cba, 0x3fea1b26d2c0a75e, // 0.57831, 0.81581 + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404 + 0x3fe2aa76e87aeb58, 0x3fe9fdf4f13149de, // 0.58331, 0.81225 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe2d333d34e9bb7, 0x3fe9e082edb42472, // 0.58828, 0.80866 + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685 + 0x3fe2fbc24b441015, 0x3fe9c2d110f075c3, // 0.59323, 0.80503 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe32421ec49a620, 0x3fe9a4dfa42b06b2, // 0.59816, 0.80138 + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954 + 0x3fe34c5252c14de1, 0x3fe986aef1457594, // 0.60307, 0.79769 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe374531b817f8d, 0x3fe9683f42bd7fe1, // 0.60795, 0.79398 + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211 + 0x3fe39c23e3d63029, 0x3fe94990e3ac4a6c, // 0.61281, 0.79023 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe3c3c44981c517, 0x3fe92aa41fc5a815, // 0.61765, 0.78646 + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456 + 0x3fe3eb33eabe0680, 0x3fe90b7943575efe, // 0.62246, 0.78265 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe41272663d108c, 0x3fe8ec109b486c49, // 0.62725, 0.77882 + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689 + 0x3fe4397f5b2a4380, 0x3fe8cc6a75184655, // 0.63202, 0.77495 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe4605a692b32a2, 0x3fe8ac871ede1d88, // 0.63676, 0.77106 + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691 + 0x3fe48703306091fe, 0x3fe88c66e7481ba1, // 0.64148, 0.76714 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe4ad79516722f0, 0x3fe86c0a1d9aa195, // 0.64618, 0.76319 + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612 + 0x3fe4d3bc6d589f80, 0x3fe84b7111af83f9, // 0.65085, 0.75921 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe4f9cc25cca486, 0x3fe82a9c13f545ff, // 0.65549, 0.7552 + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319 + 0x3fe51fa81cd99aa6, 0x3fe8098b756e52fa, // 0.66011, 0.75117 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe5454ff5159dfb, 0x3fe7e83f87b03686, // 0.66471, 0.7471 + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506 + 0x3fe56ac35197649e, 0x3fe7c6b89ce2d333, // 0.66928, 0.74301 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe59001d5f723df, 0x3fe7a4f707bf97d2, // 0.67383, 0.73889 + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682 + 0x3fe5b50b264f7448, 0x3fe782fb1b90b35b, // 0.67835, 0.73474 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe5d9dee73e345c, 0x3fe760c52c304764, // 0.68285, 0.73056 + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846 + 0x3fe5fe7cbde56a0f, 0x3fe73e558e079942, // 0.68732, 0.72636 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe622e44fec22ff, 0x3fe71bac960e41bf, // 0.69176, 0.72213 + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72 + 0x3fe64715437f535b, 0x3fe6f8ca99c95b75, // 0.69618, 0.71787 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe66b0f3f52b386, 0x3fe6d5afef4aafcc, // 0.70057, 0.71358 + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143 + 0x3fe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // 0.70493, 0.70927 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // 0.70927, 0.70493 + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275 + 0x3fe6d5afef4aafcc, 0x3fe66b0f3f52b386, // 0.71358, 0.70057 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6f8ca99c95b75, 0x3fe64715437f535b, // 0.71787, 0.69618 + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397 + 0x3fe71bac960e41bf, 0x3fe622e44fec22ff, // 0.72213, 0.69176 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe73e558e079942, 0x3fe5fe7cbde56a0f, // 0.72636, 0.68732 + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508 + 0x3fe760c52c304764, 0x3fe5d9dee73e345c, // 0.73056, 0.68285 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe782fb1b90b35b, 0x3fe5b50b264f7448, // 0.73474, 0.67835 + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609 + 0x3fe7a4f707bf97d2, 0x3fe59001d5f723df, // 0.73889, 0.67383 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe7c6b89ce2d333, 0x3fe56ac35197649e, // 0.74301, 0.66928 + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667 + 0x3fe7e83f87b03686, 0x3fe5454ff5159dfb, // 0.7471, 0.66471 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe8098b756e52fa, 0x3fe51fa81cd99aa6, // 0.75117, 0.66011 + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781 + 0x3fe82a9c13f545ff, 0x3fe4f9cc25cca486, // 0.7552, 0.65549 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe84b7111af83f9, 0x3fe4d3bc6d589f80, // 0.75921, 0.65085 + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851 + 0x3fe86c0a1d9aa195, 0x3fe4ad79516722f0, // 0.76319, 0.64618 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe88c66e7481ba1, 0x3fe48703306091fe, // 0.76714, 0.64148 + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912 + 0x3fe8ac871ede1d88, 0x3fe4605a692b32a2, // 0.77106, 0.63676 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe8cc6a75184655, 0x3fe4397f5b2a4380, // 0.77495, 0.63202 + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964 + 0x3fe8ec109b486c49, 0x3fe41272663d108c, // 0.77882, 0.62725 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe90b7943575efe, 0x3fe3eb33eabe0680, // 0.78265, 0.62246 + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006 + 0x3fe92aa41fc5a815, 0x3fe3c3c44981c517, // 0.78646, 0.61765 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe94990e3ac4a6c, 0x3fe39c23e3d63029, // 0.79023, 0.61281 + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038 + 0x3fe9683f42bd7fe1, 0x3fe374531b817f8d, // 0.79398, 0.60795 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe986aef1457594, 0x3fe34c5252c14de1, // 0.79769, 0.60307 + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062 + 0x3fe9a4dfa42b06b2, 0x3fe32421ec49a620, // 0.80138, 0.59816 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe9c2d110f075c3, 0x3fe2fbc24b441015, // 0.80503, 0.59323 + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076 + 0x3fe9e082edb42472, 0x3fe2d333d34e9bb7, // 0.80866, 0.58828 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9fdf4f13149de, 0x3fe2aa76e87aeb58, // 0.81225, 0.58331 + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081 + 0x3fea1b26d2c0a75e, 0x3fe2818bef4d3cba, // 0.81581, 0.57831 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea38184a593bc6, 0x3fe258734cbb7110, // 0.81935, 0.5733 + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078 + 0x3fea54c91090f524, 0x3fe22f2d662c13e1, // 0.82285, 0.56826 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea7138de9d60f5, 0x3fe205baa17560d6, // 0.82632, 0.5632 + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066 + 0x3fea8d676e545ad2, 0x3fe1dc1b64dc4872, // 0.82976, 0.55812 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3feaa9547a2cb98e, 0x3fe1b250171373be, // 0.83317, 0.55302 + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046 + 0x3feac4ffbd3efac8, 0x3fe188591f3a46e5, // 0.83655, 0.54789 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3feae068f345ecef, 0x3fe15e36e4dbe2bc, // 0.83989, 0.54275 + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017 + 0x3feafb8fd89f57b6, 0x3fe133e9cfee254e, // 0.84321, 0.53759 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feb16742a4ca2f5, 0x3fe1097248d0a956, // 0.84649, 0.5324 + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298 + 0x3feb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // 0.84974, 0.5272 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb4b7409de7925, 0x3fe0b405878f85ec, // 0.85296, 0.52198 + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936 + 0x3feb658f14fdbc47, 0x3fe089112032b08c, // 0.85615, 0.51673 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb7f6686e792ea, 0x3fe05df3ec31b8b6, // 0.8593, 0.51147 + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883 + 0x3feb98fa1fd9155e, 0x3fe032ae55edbd95, // 0.86242, 0.50619 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3febb249a0b6c40d, 0x3fe00740c82b82e0, // 0.86551, 0.50089 + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823 + 0x3febcb54cb0d2327, 0x3fdfb7575c24d2de, // 0.86857, 0.49557 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3febe41b611154c1, 0x3fdf5fdee656cda3, // 0.8716, 0.49023 + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755 + 0x3febfc9d25a1b147, 0x3fdf081906bff7fd, // 0.87459, 0.48487 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3fec14d9dc465e58, 0x3fdeb00695f25620, // 0.87755, 0.47949 + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768 + 0x3fec2cd14931e3f1, 0x3fde57a86d3cd824, // 0.88047, 0.4741 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec44833141c004, 0x3fddfeff66a941de, // 0.88336, 0.46869 + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598 + 0x3fec5bef59fef85a, 0x3fdda60c5cfa10d8, // 0.88622, 0.46326 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec7315899eaad7, 0x3fdd4cd02ba8609c, // 0.88905, 0.45781 + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508 + 0x3fec89f587029c13, 0x3fdcf34baee1cd21, // 0.89184, 0.45235 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3feca08f19b9c449, 0x3fdc997fc3865388, // 0.8946, 0.44687 + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412 + 0x3fecb6e20a00da99, 0x3fdc3f6d47263129, // 0.89732, 0.44137 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fecccee20c2de9f, 0x3fdbe51517ffc0d9, // 0.90002, 0.43586 + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309 + 0x3fece2b32799a060, 0x3fdb8a7814fd5693, // 0.90267, 0.43033 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fecf830e8ce467b, 0x3fdb2f971db31972, // 0.9053, 0.42478 + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422 + 0x3fed0d672f59d2b9, 0x3fdad473125cdc08, // 0.90789, 0.41922 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3fed2255c6e5a4e1, 0x3fda790cd3dbf31a, // 0.91044, 0.41364 + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084 + 0x3fed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // 0.91296, 0.40804 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed4b5b1b187524, 0x3fd9c17d440df9f2, // 0.91545, 0.40243 + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962 + 0x3fed5f7172888a7f, 0x3fd96555b7ab948f, // 0.9179, 0.39681 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed733f508c0dff, 0x3fd908ef81ef7bd1, // 0.92032, 0.39117 + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835 + 0x3fed86c48445a450, 0x3fd8ac4b86d5ed44, // 0.9227, 0.38552 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // 0.92505, 0.37985 + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701 + 0x3fedacf42ce68ab9, 0x3fd7f24dd37341e3, // 0.92736, 0.37416 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3fedbf9e4395759a, 0x3fd794f5e613dfae, // 0.92964, 0.36847 + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561 + 0x3fedd1fef38a915a, 0x3fd73763c9261092, // 0.93188, 0.36276 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fede4160f6d8d81, 0x3fd6d998638a0cb5, // 0.93409, 0.35703 + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416 + 0x3fedf5e36a9ba59c, 0x3fd67b949cad63ca, // 0.93627, 0.35129 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3fee0766d9280f54, 0x3fd61d595c88c203, // 0.9384, 0.34554 + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266 + 0x3fee18a02fdc66d9, 0x3fd5bee78b9db3b6, // 0.94051, 0.33978 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee298f4439197a, 0x3fd5604012f467b4, // 0.94257, 0.334 + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111 + 0x3fee3a33ec75ce85, 0x3fd50163dc197047, // 0.9446, 0.32821 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee4a8dff81ce5e, 0x3fd4a253d11b82f3, // 0.9466, 0.32241 + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195 + 0x3fee5a9d550467d3, 0x3fd44310dc8936f0, // 0.94856, 0.31659 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee6a61c55d53a7, 0x3fd3e39be96ec271, // 0.95049, 0.31077 + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785 + 0x3fee79db29a5165a, 0x3fd383f5e353b6aa, // 0.95238, 0.30493 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee89095bad6025, 0x3fd3241fb638baaf, // 0.95423, 0.29908 + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615 + 0x3fee97ec36016b30, 0x3fd2c41a4e954520, // 0.95605, 0.29322 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3feea68393e65800, 0x3fd263e6995554ba, // 0.95783, 0.28735 + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441 + 0x3feeb4cf515b8811, 0x3fd2038583d727bd, // 0.95957, 0.28146 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3feec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // 0.96128, 0.27557 + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262 + 0x3feed0835e999009, 0x3fd1423eefc69378, // 0.96295, 0.26967 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feeddeb6a078651, 0x3fd0e15b4e1749cd, // 0.96459, 0.26375 + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079 + 0x3feeeb074c50a544, 0x3fd0804e05eb661e, // 0.96619, 0.25783 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // 0.96775, 0.2519 + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893 + 0x3fef045a14cf738c, 0x3fcf7b7480bd3801, // 0.96928, 0.24596 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3fef1090bc898f5f, 0x3fceb86b462de348, // 0.97077, 0.24 + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702 + 0x3fef1c7abe284708, 0x3fcdf5163f01099a, // 0.97223, 0.23404 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef2817fc4609ce, 0x3fcd31774d2cbdee, // 0.97364, 0.22807 + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508 + 0x3fef33685a3aaef0, 0x3fcc6d90535d74dc, // 0.97503, 0.22209 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef3e6bbc1bbc65, 0x3fcba96334f15dad, // 0.97637, 0.21611 + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311 + 0x3fef492206bcabb4, 0x3fcae4f1d5f3b9ab, // 0.97768, 0.21011 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef538b1faf2d07, 0x3fca203e1b1831da, // 0.97895, 0.20411 + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011 + 0x3fef5da6ed43685d, 0x3fc95b49e9b62af9, // 0.98018, 0.1981 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef677556883cee, 0x3fc8961727c41804, // 0.98138, 0.19208 + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907 + 0x3fef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // 0.98254, 0.18606 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef7a299c1a322a, 0x3fc70afd8d08c4ff, // 0.98366, 0.18002 + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177 + 0x3fef830f4a40c60c, 0x3fc6451a831d830d, // 0.98475, 0.17398 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef8ba737cb4b78, 0x3fc57f008654cbde, // 0.9858, 0.16794 + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491 + 0x3fef93f14f85ac08, 0x3fc4b8b17f79fa88, // 0.98681, 0.16189 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef9bed7cfbde29, 0x3fc3f22f57db4893, // 0.98778, 0.15583 + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528 + 0x3fefa39bac7a1791, 0x3fc32b7bf94516a7, // 0.98872, 0.14976 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fefaafbcb0cfddc, 0x3fc264994dfd340a, // 0.98962, 0.1437 + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066 + 0x3fefb20dc681d54d, 0x3fc19d8940be24e7, // 0.99049, 0.13762 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefb8d18d66adb7, 0x3fc0d64dbcb26786, // 0.99131, 0.13154 + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285 + 0x3fefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // 0.9921, 0.12545 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // 0.99285, 0.11937 + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632 + 0x3fefcb4703914354, 0x3fbcff533b307dc1, // 0.99356, 0.11327 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefd0d158d86087, 0x3fbb6fa6ec38f64c, // 0.99424, 0.10717 + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412 + 0x3fefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // 0.99488, 0.10107 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefdafa7514538c, 0x3fb84f8712c130a0, // 0.99548, 0.094963 + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909 + 0x3fefdf9922f73307, 0x3fb6bf1b3e79b129, // 0.99604, 0.088854 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefe3e92be9d886, 0x3fb52e774a4d4d0a, // 0.99657, 0.08274 + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682 + 0x3fefe7ea85482d60, 0x3fb39d9f12c5a299, // 0.99706, 0.076624 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefeb9d2530410f, 0x3fb20c9674ed444c, // 0.99751, 0.070505 + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444 + 0x3fefef0102826191, 0x3fb07b614e463064, // 0.99793, 0.064383 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3feff21614e131ed, 0x3fadd406f9808ec8, // 0.9983, 0.058258 + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195 + 0x3feff4dc54b1bed3, 0x3faab101bd5f8317, // 0.99864, 0.052132 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff753bb1b9164, 0x3fa78dbaa5874685, // 0.99894, 0.046003 + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938 + 0x3feff97c4208c014, 0x3fa46a396ff86179, // 0.9992, 0.039873 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feffb55e425fdae, 0x3fa14685db42c17e, // 0.99943, 0.033741 + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675 + 0x3feffce09ce2a679, 0x3f9c454f4ce53b1c, // 0.99962, 0.027608 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffe1c6870cb77, 0x3f95fd4d21fab226, // 0.99977, 0.021474 + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407 + 0x3fefff0943c53bd1, 0x3f8f6a296ab997ca, // 0.99988, 0.015339 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3fefffa72c978c4f, 0x3f82d96b0e509703, // 0.99996, 0.0092038 + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359 + 0x3feffff621621d02, 0x3f6921f8becca4ba, // 1, 0.003068 + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffff621621d02, 0xbf6921f8becca4ba, // 1, -0.003068 + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359 + 0x3fefffa72c978c4f, 0xbf82d96b0e509703, // 0.99996,-0.0092038 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272 + 0x3fefff0943c53bd1, 0xbf8f6a296ab997ca, // 0.99988, -0.015339 + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407 + 0x3feffe1c6870cb77, 0xbf95fd4d21fab226, // 0.99977, -0.021474 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541 + 0x3feffce09ce2a679, 0xbf9c454f4ce53b1c, // 0.99962, -0.027608 + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675 + 0x3feffb55e425fdae, 0xbfa14685db42c17e, // 0.99943, -0.033741 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807 + 0x3feff97c4208c014, 0xbfa46a396ff86179, // 0.9992, -0.039873 + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938 + 0x3feff753bb1b9164, 0xbfa78dbaa5874685, // 0.99894, -0.046003 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068 + 0x3feff4dc54b1bed3, 0xbfaab101bd5f8317, // 0.99864, -0.052132 + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195 + 0x3feff21614e131ed, 0xbfadd406f9808ec8, // 0.9983, -0.058258 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321 + 0x3fefef0102826191, 0xbfb07b614e463064, // 0.99793, -0.064383 + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444 + 0x3fefeb9d2530410f, 0xbfb20c9674ed444c, // 0.99751, -0.070505 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565 + 0x3fefe7ea85482d60, 0xbfb39d9f12c5a299, // 0.99706, -0.076624 + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682 + 0x3fefe3e92be9d886, 0xbfb52e774a4d4d0a, // 0.99657, -0.08274 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797 + 0x3fefdf9922f73307, 0xbfb6bf1b3e79b129, // 0.99604, -0.088854 + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909 + 0x3fefdafa7514538c, 0xbfb84f8712c130a0, // 0.99548, -0.094963 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017 + 0x3fefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // 0.99488, -0.10107 + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412 + 0x3fefd0d158d86087, 0xbfbb6fa6ec38f64c, // 0.99424, -0.10717 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefcb4703914354, 0xbfbcff533b307dc1, // 0.99356, -0.11327 + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632 + 0x3fefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // 0.99285, -0.11937 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // 0.9921, -0.12545 + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285 + 0x3fefb8d18d66adb7, 0xbfc0d64dbcb26786, // 0.99131, -0.13154 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefb20dc681d54d, 0xbfc19d8940be24e7, // 0.99049, -0.13762 + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066 + 0x3fefaafbcb0cfddc, 0xbfc264994dfd340a, // 0.98962, -0.1437 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefa39bac7a1791, 0xbfc32b7bf94516a7, // 0.98872, -0.14976 + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528 + 0x3fef9bed7cfbde29, 0xbfc3f22f57db4893, // 0.98778, -0.15583 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fef93f14f85ac08, 0xbfc4b8b17f79fa88, // 0.98681, -0.16189 + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491 + 0x3fef8ba737cb4b78, 0xbfc57f008654cbde, // 0.9858, -0.16794 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef830f4a40c60c, 0xbfc6451a831d830d, // 0.98475, -0.17398 + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177 + 0x3fef7a299c1a322a, 0xbfc70afd8d08c4ff, // 0.98366, -0.18002 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // 0.98254, -0.18606 + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907 + 0x3fef677556883cee, 0xbfc8961727c41804, // 0.98138, -0.19208 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef5da6ed43685d, 0xbfc95b49e9b62af9, // 0.98018, -0.1981 + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011 + 0x3fef538b1faf2d07, 0xbfca203e1b1831da, // 0.97895, -0.20411 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef492206bcabb4, 0xbfcae4f1d5f3b9ab, // 0.97768, -0.21011 + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311 + 0x3fef3e6bbc1bbc65, 0xbfcba96334f15dad, // 0.97637, -0.21611 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef33685a3aaef0, 0xbfcc6d90535d74dc, // 0.97503, -0.22209 + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508 + 0x3fef2817fc4609ce, 0xbfcd31774d2cbdee, // 0.97364, -0.22807 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef1c7abe284708, 0xbfcdf5163f01099a, // 0.97223, -0.23404 + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702 + 0x3fef1090bc898f5f, 0xbfceb86b462de348, // 0.97077, -0.24 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef045a14cf738c, 0xbfcf7b7480bd3801, // 0.96928, -0.24596 + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893 + 0x3feef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // 0.96775, -0.2519 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3feeeb074c50a544, 0xbfd0804e05eb661e, // 0.96619, -0.25783 + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079 + 0x3feeddeb6a078651, 0xbfd0e15b4e1749cd, // 0.96459, -0.26375 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feed0835e999009, 0xbfd1423eefc69378, // 0.96295, -0.26967 + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262 + 0x3feec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // 0.96128, -0.27557 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feeb4cf515b8811, 0xbfd2038583d727bd, // 0.95957, -0.28146 + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441 + 0x3feea68393e65800, 0xbfd263e6995554ba, // 0.95783, -0.28735 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3fee97ec36016b30, 0xbfd2c41a4e954520, // 0.95605, -0.29322 + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615 + 0x3fee89095bad6025, 0xbfd3241fb638baaf, // 0.95423, -0.29908 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee79db29a5165a, 0xbfd383f5e353b6aa, // 0.95238, -0.30493 + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785 + 0x3fee6a61c55d53a7, 0xbfd3e39be96ec271, // 0.95049, -0.31077 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee5a9d550467d3, 0xbfd44310dc8936f0, // 0.94856, -0.31659 + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195 + 0x3fee4a8dff81ce5e, 0xbfd4a253d11b82f3, // 0.9466, -0.32241 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee3a33ec75ce85, 0xbfd50163dc197047, // 0.9446, -0.32821 + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111 + 0x3fee298f4439197a, 0xbfd5604012f467b4, // 0.94257, -0.334 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee18a02fdc66d9, 0xbfd5bee78b9db3b6, // 0.94051, -0.33978 + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266 + 0x3fee0766d9280f54, 0xbfd61d595c88c203, // 0.9384, -0.34554 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fedf5e36a9ba59c, 0xbfd67b949cad63ca, // 0.93627, -0.35129 + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416 + 0x3fede4160f6d8d81, 0xbfd6d998638a0cb5, // 0.93409, -0.35703 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fedd1fef38a915a, 0xbfd73763c9261092, // 0.93188, -0.36276 + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561 + 0x3fedbf9e4395759a, 0xbfd794f5e613dfae, // 0.92964, -0.36847 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3fedacf42ce68ab9, 0xbfd7f24dd37341e3, // 0.92736, -0.37416 + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701 + 0x3fed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // 0.92505, -0.37985 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fed86c48445a450, 0xbfd8ac4b86d5ed44, // 0.9227, -0.38552 + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835 + 0x3fed733f508c0dff, 0xbfd908ef81ef7bd1, // 0.92032, -0.39117 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed5f7172888a7f, 0xbfd96555b7ab948f, // 0.9179, -0.39681 + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962 + 0x3fed4b5b1b187524, 0xbfd9c17d440df9f2, // 0.91545, -0.40243 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // 0.91296, -0.40804 + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084 + 0x3fed2255c6e5a4e1, 0xbfda790cd3dbf31a, // 0.91044, -0.41364 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed0d672f59d2b9, 0xbfdad473125cdc08, // 0.90789, -0.41922 + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422 + 0x3fecf830e8ce467b, 0xbfdb2f971db31972, // 0.9053, -0.42478 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fece2b32799a060, 0xbfdb8a7814fd5693, // 0.90267, -0.43033 + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309 + 0x3fecccee20c2de9f, 0xbfdbe51517ffc0d9, // 0.90002, -0.43586 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3fecb6e20a00da99, 0xbfdc3f6d47263129, // 0.89732, -0.44137 + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412 + 0x3feca08f19b9c449, 0xbfdc997fc3865388, // 0.8946, -0.44687 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fec89f587029c13, 0xbfdcf34baee1cd21, // 0.89184, -0.45235 + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508 + 0x3fec7315899eaad7, 0xbfdd4cd02ba8609c, // 0.88905, -0.45781 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec5bef59fef85a, 0xbfdda60c5cfa10d8, // 0.88622, -0.46326 + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598 + 0x3fec44833141c004, 0xbfddfeff66a941de, // 0.88336, -0.46869 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec2cd14931e3f1, 0xbfde57a86d3cd824, // 0.88047, -0.4741 + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768 + 0x3fec14d9dc465e58, 0xbfdeb00695f25620, // 0.87755, -0.47949 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3febfc9d25a1b147, 0xbfdf081906bff7fd, // 0.87459, -0.48487 + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755 + 0x3febe41b611154c1, 0xbfdf5fdee656cda3, // 0.8716, -0.49023 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3febcb54cb0d2327, 0xbfdfb7575c24d2de, // 0.86857, -0.49557 + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823 + 0x3febb249a0b6c40d, 0xbfe00740c82b82e0, // 0.86551, -0.50089 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3feb98fa1fd9155e, 0xbfe032ae55edbd95, // 0.86242, -0.50619 + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883 + 0x3feb7f6686e792ea, 0xbfe05df3ec31b8b6, // 0.8593, -0.51147 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb658f14fdbc47, 0xbfe089112032b08c, // 0.85615, -0.51673 + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936 + 0x3feb4b7409de7925, 0xbfe0b405878f85ec, // 0.85296, -0.52198 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // 0.84974, -0.5272 + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298 + 0x3feb16742a4ca2f5, 0xbfe1097248d0a956, // 0.84649, -0.5324 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feafb8fd89f57b6, 0xbfe133e9cfee254e, // 0.84321, -0.53759 + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017 + 0x3feae068f345ecef, 0xbfe15e36e4dbe2bc, // 0.83989, -0.54275 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3feac4ffbd3efac8, 0xbfe188591f3a46e5, // 0.83655, -0.54789 + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046 + 0x3feaa9547a2cb98e, 0xbfe1b250171373be, // 0.83317, -0.55302 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3fea8d676e545ad2, 0xbfe1dc1b64dc4872, // 0.82976, -0.55812 + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066 + 0x3fea7138de9d60f5, 0xbfe205baa17560d6, // 0.82632, -0.5632 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea54c91090f524, 0xbfe22f2d662c13e1, // 0.82285, -0.56826 + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078 + 0x3fea38184a593bc6, 0xbfe258734cbb7110, // 0.81935, -0.5733 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea1b26d2c0a75e, 0xbfe2818bef4d3cba, // 0.81581, -0.57831 + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081 + 0x3fe9fdf4f13149de, 0xbfe2aa76e87aeb58, // 0.81225, -0.58331 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fe9e082edb42472, 0xbfe2d333d34e9bb7, // 0.80866, -0.58828 + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076 + 0x3fe9c2d110f075c3, 0xbfe2fbc24b441015, // 0.80503, -0.59323 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9a4dfa42b06b2, 0xbfe32421ec49a620, // 0.80138, -0.59816 + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062 + 0x3fe986aef1457594, 0xbfe34c5252c14de1, // 0.79769, -0.60307 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe9683f42bd7fe1, 0xbfe374531b817f8d, // 0.79398, -0.60795 + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038 + 0x3fe94990e3ac4a6c, 0xbfe39c23e3d63029, // 0.79023, -0.61281 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe92aa41fc5a815, 0xbfe3c3c44981c517, // 0.78646, -0.61765 + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006 + 0x3fe90b7943575efe, 0xbfe3eb33eabe0680, // 0.78265, -0.62246 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe8ec109b486c49, 0xbfe41272663d108c, // 0.77882, -0.62725 + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964 + 0x3fe8cc6a75184655, 0xbfe4397f5b2a4380, // 0.77495, -0.63202 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8ac871ede1d88, 0xbfe4605a692b32a2, // 0.77106, -0.63676 + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912 + 0x3fe88c66e7481ba1, 0xbfe48703306091fe, // 0.76714, -0.64148 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe86c0a1d9aa195, 0xbfe4ad79516722f0, // 0.76319, -0.64618 + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851 + 0x3fe84b7111af83f9, 0xbfe4d3bc6d589f80, // 0.75921, -0.65085 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe82a9c13f545ff, 0xbfe4f9cc25cca486, // 0.7552, -0.65549 + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781 + 0x3fe8098b756e52fa, 0xbfe51fa81cd99aa6, // 0.75117, -0.66011 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe7e83f87b03686, 0xbfe5454ff5159dfb, // 0.7471, -0.66471 + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667 + 0x3fe7c6b89ce2d333, 0xbfe56ac35197649e, // 0.74301, -0.66928 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7a4f707bf97d2, 0xbfe59001d5f723df, // 0.73889, -0.67383 + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609 + 0x3fe782fb1b90b35b, 0xbfe5b50b264f7448, // 0.73474, -0.67835 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe760c52c304764, 0xbfe5d9dee73e345c, // 0.73056, -0.68285 + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508 + 0x3fe73e558e079942, 0xbfe5fe7cbde56a0f, // 0.72636, -0.68732 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe71bac960e41bf, 0xbfe622e44fec22ff, // 0.72213, -0.69176 + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397 + 0x3fe6f8ca99c95b75, 0xbfe64715437f535b, // 0.71787, -0.69618 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe6d5afef4aafcc, 0xbfe66b0f3f52b386, // 0.71358, -0.70057 + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275 + 0x3fe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // 0.70927, -0.70493 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // 0.70493, -0.70927 + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143 + 0x3fe66b0f3f52b386, 0xbfe6d5afef4aafcc, // 0.70057, -0.71358 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe64715437f535b, 0xbfe6f8ca99c95b75, // 0.69618, -0.71787 + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72 + 0x3fe622e44fec22ff, 0xbfe71bac960e41bf, // 0.69176, -0.72213 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe5fe7cbde56a0f, 0xbfe73e558e079942, // 0.68732, -0.72636 + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846 + 0x3fe5d9dee73e345c, 0xbfe760c52c304764, // 0.68285, -0.73056 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe5b50b264f7448, 0xbfe782fb1b90b35b, // 0.67835, -0.73474 + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682 + 0x3fe59001d5f723df, 0xbfe7a4f707bf97d2, // 0.67383, -0.73889 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe56ac35197649e, 0xbfe7c6b89ce2d333, // 0.66928, -0.74301 + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506 + 0x3fe5454ff5159dfb, 0xbfe7e83f87b03686, // 0.66471, -0.7471 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe51fa81cd99aa6, 0xbfe8098b756e52fa, // 0.66011, -0.75117 + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319 + 0x3fe4f9cc25cca486, 0xbfe82a9c13f545ff, // 0.65549, -0.7552 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe4d3bc6d589f80, 0xbfe84b7111af83f9, // 0.65085, -0.75921 + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612 + 0x3fe4ad79516722f0, 0xbfe86c0a1d9aa195, // 0.64618, -0.76319 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe48703306091fe, 0xbfe88c66e7481ba1, // 0.64148, -0.76714 + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691 + 0x3fe4605a692b32a2, 0xbfe8ac871ede1d88, // 0.63676, -0.77106 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe4397f5b2a4380, 0xbfe8cc6a75184655, // 0.63202, -0.77495 + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689 + 0x3fe41272663d108c, 0xbfe8ec109b486c49, // 0.62725, -0.77882 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe3eb33eabe0680, 0xbfe90b7943575efe, // 0.62246, -0.78265 + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456 + 0x3fe3c3c44981c517, 0xbfe92aa41fc5a815, // 0.61765, -0.78646 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe39c23e3d63029, 0xbfe94990e3ac4a6c, // 0.61281, -0.79023 + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211 + 0x3fe374531b817f8d, 0xbfe9683f42bd7fe1, // 0.60795, -0.79398 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe34c5252c14de1, 0xbfe986aef1457594, // 0.60307, -0.79769 + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954 + 0x3fe32421ec49a620, 0xbfe9a4dfa42b06b2, // 0.59816, -0.80138 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe2fbc24b441015, 0xbfe9c2d110f075c3, // 0.59323, -0.80503 + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685 + 0x3fe2d333d34e9bb7, 0xbfe9e082edb42472, // 0.58828, -0.80866 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe2aa76e87aeb58, 0xbfe9fdf4f13149de, // 0.58331, -0.81225 + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404 + 0x3fe2818bef4d3cba, 0xbfea1b26d2c0a75e, // 0.57831, -0.81581 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe258734cbb7110, 0xbfea38184a593bc6, // 0.5733, -0.81935 + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211 + 0x3fe22f2d662c13e1, 0xbfea54c91090f524, // 0.56826, -0.82285 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe205baa17560d6, 0xbfea7138de9d60f5, // 0.5632, -0.82632 + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805 + 0x3fe1dc1b64dc4872, 0xbfea8d676e545ad2, // 0.55812, -0.82976 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe1b250171373be, 0xbfeaa9547a2cb98e, // 0.55302, -0.83317 + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486 + 0x3fe188591f3a46e5, 0xbfeac4ffbd3efac8, // 0.54789, -0.83655 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe15e36e4dbe2bc, 0xbfeae068f345ecef, // 0.54275, -0.83989 + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155 + 0x3fe133e9cfee254e, 0xbfeafb8fd89f57b6, // 0.53759, -0.84321 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe1097248d0a956, 0xbfeb16742a4ca2f5, // 0.5324, -0.84649 + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812 + 0x3fe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // 0.5272, -0.84974 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe0b405878f85ec, 0xbfeb4b7409de7925, // 0.52198, -0.85296 + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456 + 0x3fe089112032b08c, 0xbfeb658f14fdbc47, // 0.51673, -0.85615 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe05df3ec31b8b6, 0xbfeb7f6686e792ea, // 0.51147, -0.8593 + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087 + 0x3fe032ae55edbd95, 0xbfeb98fa1fd9155e, // 0.50619, -0.86242 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe00740c82b82e0, 0xbfebb249a0b6c40d, // 0.50089, -0.86551 + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705 + 0x3fdfb7575c24d2de, 0xbfebcb54cb0d2327, // 0.49557, -0.86857 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fdf5fdee656cda3, 0xbfebe41b611154c1, // 0.49023, -0.8716 + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309 + 0x3fdf081906bff7fd, 0xbfebfc9d25a1b147, // 0.48487, -0.87459 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdeb00695f25620, 0xbfec14d9dc465e58, // 0.47949, -0.87755 + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901 + 0x3fde57a86d3cd824, 0xbfec2cd14931e3f1, // 0.4741, -0.88047 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fddfeff66a941de, 0xbfec44833141c004, // 0.46869, -0.88336 + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848 + 0x3fdda60c5cfa10d8, 0xbfec5bef59fef85a, // 0.46326, -0.88622 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fdd4cd02ba8609c, 0xbfec7315899eaad7, // 0.45781, -0.88905 + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045 + 0x3fdcf34baee1cd21, 0xbfec89f587029c13, // 0.45235, -0.89184 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdc997fc3865388, 0xbfeca08f19b9c449, // 0.44687, -0.8946 + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597 + 0x3fdc3f6d47263129, 0xbfecb6e20a00da99, // 0.44137, -0.89732 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdbe51517ffc0d9, 0xbfecccee20c2de9f, // 0.43586, -0.90002 + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135 + 0x3fdb8a7814fd5693, 0xbfece2b32799a060, // 0.43033, -0.90267 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdb2f971db31972, 0xbfecf830e8ce467b, // 0.42478, -0.9053 + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066 + 0x3fdad473125cdc08, 0xbfed0d672f59d2b9, // 0.41922, -0.90789 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fda790cd3dbf31a, 0xbfed2255c6e5a4e1, // 0.41364, -0.91044 + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171 + 0x3fda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // 0.40804, -0.91296 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fd9c17d440df9f2, 0xbfed4b5b1b187524, // 0.40243, -0.91545 + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668 + 0x3fd96555b7ab948f, 0xbfed5f7172888a7f, // 0.39681, -0.9179 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd908ef81ef7bd1, 0xbfed733f508c0dff, // 0.39117, -0.92032 + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151 + 0x3fd8ac4b86d5ed44, 0xbfed86c48445a450, // 0.38552, -0.9227 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // 0.37985, -0.92505 + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621 + 0x3fd7f24dd37341e3, 0xbfedacf42ce68ab9, // 0.37416, -0.92736 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd794f5e613dfae, 0xbfedbf9e4395759a, // 0.36847, -0.92964 + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077 + 0x3fd73763c9261092, 0xbfedd1fef38a915a, // 0.36276, -0.93188 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd6d998638a0cb5, 0xbfede4160f6d8d81, // 0.35703, -0.93409 + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518 + 0x3fd67b949cad63ca, 0xbfedf5e36a9ba59c, // 0.35129, -0.93627 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd61d595c88c203, 0xbfee0766d9280f54, // 0.34554, -0.9384 + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946 + 0x3fd5bee78b9db3b6, 0xbfee18a02fdc66d9, // 0.33978, -0.94051 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd5604012f467b4, 0xbfee298f4439197a, // 0.334, -0.94257 + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359 + 0x3fd50163dc197047, 0xbfee3a33ec75ce85, // 0.32821, -0.9446 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd4a253d11b82f3, 0xbfee4a8dff81ce5e, // 0.32241, -0.9466 + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759 + 0x3fd44310dc8936f0, 0xbfee5a9d550467d3, // 0.31659, -0.94856 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd3e39be96ec271, 0xbfee6a61c55d53a7, // 0.31077, -0.95049 + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144 + 0x3fd383f5e353b6aa, 0xbfee79db29a5165a, // 0.30493, -0.95238 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd3241fb638baaf, 0xbfee89095bad6025, // 0.29908, -0.95423 + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514 + 0x3fd2c41a4e954520, 0xbfee97ec36016b30, // 0.29322, -0.95605 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd263e6995554ba, 0xbfeea68393e65800, // 0.28735, -0.95783 + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587 + 0x3fd2038583d727bd, 0xbfeeb4cf515b8811, // 0.28146, -0.95957 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // 0.27557, -0.96128 + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212 + 0x3fd1423eefc69378, 0xbfeed0835e999009, // 0.26967, -0.96295 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd0e15b4e1749cd, 0xbfeeddeb6a078651, // 0.26375, -0.96459 + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539 + 0x3fd0804e05eb661e, 0xbfeeeb074c50a544, // 0.25783, -0.96619 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // 0.2519, -0.96775 + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852 + 0x3fcf7b7480bd3801, 0xbfef045a14cf738c, // 0.24596, -0.96928 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fceb86b462de348, 0xbfef1090bc898f5f, // 0.24, -0.97077 + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715 + 0x3fcdf5163f01099a, 0xbfef1c7abe284708, // 0.23404, -0.97223 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fcd31774d2cbdee, 0xbfef2817fc4609ce, // 0.22807, -0.97364 + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434 + 0x3fcc6d90535d74dc, 0xbfef33685a3aaef0, // 0.22209, -0.97503 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcba96334f15dad, 0xbfef3e6bbc1bbc65, // 0.21611, -0.97637 + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703 + 0x3fcae4f1d5f3b9ab, 0xbfef492206bcabb4, // 0.21011, -0.97768 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fca203e1b1831da, 0xbfef538b1faf2d07, // 0.20411, -0.97895 + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957 + 0x3fc95b49e9b62af9, 0xbfef5da6ed43685d, // 0.1981, -0.98018 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc8961727c41804, 0xbfef677556883cee, // 0.19208, -0.98138 + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196 + 0x3fc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // 0.18606, -0.98254 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc70afd8d08c4ff, 0xbfef7a299c1a322a, // 0.18002, -0.98366 + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421 + 0x3fc6451a831d830d, 0xbfef830f4a40c60c, // 0.17398, -0.98475 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc57f008654cbde, 0xbfef8ba737cb4b78, // 0.16794, -0.9858 + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631 + 0x3fc4b8b17f79fa88, 0xbfef93f14f85ac08, // 0.16189, -0.98681 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc3f22f57db4893, 0xbfef9bed7cfbde29, // 0.15583, -0.98778 + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826 + 0x3fc32b7bf94516a7, 0xbfefa39bac7a1791, // 0.14976, -0.98872 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc264994dfd340a, 0xbfefaafbcb0cfddc, // 0.1437, -0.98962 + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006 + 0x3fc19d8940be24e7, 0xbfefb20dc681d54d, // 0.13762, -0.99049 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc0d64dbcb26786, 0xbfefb8d18d66adb7, // 0.13154, -0.99131 + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171 + 0x3fc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // 0.12545, -0.9921 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // 0.11937, -0.99285 + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321 + 0x3fbcff533b307dc1, 0xbfefcb4703914354, // 0.11327, -0.99356 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbb6fa6ec38f64c, 0xbfefd0d158d86087, // 0.10717, -0.99424 + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456 + 0x3fb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // 0.10107, -0.99488 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fb84f8712c130a0, 0xbfefdafa7514538c, // 0.094963, -0.99548 + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577 + 0x3fb6bf1b3e79b129, 0xbfefdf9922f73307, // 0.088854, -0.99604 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb52e774a4d4d0a, 0xbfefe3e92be9d886, // 0.08274, -0.99657 + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682 + 0x3fb39d9f12c5a299, 0xbfefe7ea85482d60, // 0.076624, -0.99706 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb20c9674ed444c, 0xbfefeb9d2530410f, // 0.070505, -0.99751 + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772 + 0x3fb07b614e463064, 0xbfefef0102826191, // 0.064383, -0.99793 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fadd406f9808ec8, 0xbfeff21614e131ed, // 0.058258, -0.9983 + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848 + 0x3faab101bd5f8317, 0xbfeff4dc54b1bed3, // 0.052132, -0.99864 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3fa78dbaa5874685, 0xbfeff753bb1b9164, // 0.046003, -0.99894 + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908 + 0x3fa46a396ff86179, 0xbfeff97c4208c014, // 0.039873, -0.9992 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa14685db42c17e, 0xbfeffb55e425fdae, // 0.033741, -0.99943 + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953 + 0x3f9c454f4ce53b1c, 0xbfeffce09ce2a679, // 0.027608, -0.99962 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3f95fd4d21fab226, 0xbfeffe1c6870cb77, // 0.021474, -0.99977 + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983 + 0x3f8f6a296ab997ca, 0xbfefff0943c53bd1, // 0.015339, -0.99988 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f82d96b0e509703, 0xbfefffa72c978c4f, //0.0092038, -0.99996 + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, //0.0061359, -0.99998 + 0x3f6921f8becca4ba, 0xbfeffff621621d02, // 0.003068, -1 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096) +const uint64_t twiddleCoefF64_rfft_4096[4096] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0x3f5921faaee6472d, 0x3feffffd88586ee6, // 0.001534, 1 + 0x3f6921f8becca4ba, 0x3feffff621621d02, // 0.003068, 1 + 0x3f72d97822f996bc, 0x3fefffe9cb1e2e8d, //0.0046019, 0.99999 + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, //0.0061359, 0.99998 + 0x3f7f6a65f9a2a3c5, 0x3fefffc250b5daef, //0.0076698, 0.99997 + 0x3f82d96b0e509703, 0x3fefffa72c978c4f, //0.0092038, 0.99996 + 0x3f85fda037ac05e0, 0x3fefff871937ce2f, // 0.010738, 0.99994 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x3f8c45ffe1e48ad9, 0x3fefff3824c88f6f, // 0.013805, 0.9999 + 0x3f8f6a296ab997ca, 0x3fefff0943c53bd1, // 0.015339, 0.99988 + 0x3f9147270dad7132, 0x3feffed57398d2b7, // 0.016873, 0.99986 + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983 + 0x3f946b4381fce81c, 0x3feffe5f05e578db, // 0.01994, 0.9998 + 0x3f95fd4d21fab226, 0x3feffe1c6870cb77, // 0.021474, 0.99977 + 0x3f978f535ddc9f03, 0x3feffdd4dbf78f52, // 0.023008, 0.99974 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f9ab354b1504fca, 0x3feffd36f624500c, // 0.026075, 0.99966 + 0x3f9c454f4ce53b1c, 0x3feffce09ce2a679, // 0.027608, 0.99962 + 0x3f9dd7458c64ab39, 0x3feffc8554cd213a, // 0.029142, 0.99958 + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953 + 0x3fa07d91ff984580, 0x3feffbbff85f9515, // 0.032208, 0.99948 + 0x3fa14685db42c17e, 0x3feffb55e425fdae, // 0.033741, 0.99943 + 0x3fa20f770ceb11c6, 0x3feffae6e1556998, // 0.035274, 0.99938 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3fa3a150f6421afc, 0x3feff9fa10348837, // 0.03834, 0.99926 + 0x3fa46a396ff86179, 0x3feff97c4208c014, // 0.039873, 0.9992 + 0x3fa5331ec3bba0eb, 0x3feff8f9858f058b, // 0.041406, 0.99914 + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908 + 0x3fa6c4df7d7d5b84, 0x3feff7e5420320f9, // 0.044471, 0.99901 + 0x3fa78dbaa5874685, 0x3feff753bb1b9164, // 0.046003, 0.99894 + 0x3fa856922bb513c1, 0x3feff6bd463b444d, // 0.047535, 0.99887 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3fa9e835d6993c87, 0x3feff58192ee0358, // 0.0506, 0.99872 + 0x3faab101bd5f8317, 0x3feff4dc54b1bed3, // 0.052132, 0.99864 + 0x3fab79c986698b78, 0x3feff43228de1b77, // 0.053664, 0.99856 + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848 + 0x3fad0b4c436f91d0, 0x3feff2cf08da7321, // 0.056727, 0.99839 + 0x3fadd406f9808ec8, 0x3feff21614e131ed, // 0.058258, 0.9983 + 0x3fae9cbd15ff5527, 0x3feff15833be1965, // 0.05979, 0.99821 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fb0170d833bf421, 0x3fefefcdaa704562, // 0.062852, 0.99802 + 0x3fb07b614e463064, 0x3fefef0102826191, // 0.064383, 0.99793 + 0x3fb0dfb28ea201e6, 0x3fefee2f6de455ba, // 0.065913, 0.99783 + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772 + 0x3fb1a84d316d4f8a, 0x3fefec7d7f19cffc, // 0.068974, 0.99762 + 0x3fb20c9674ed444c, 0x3fefeb9d2530410f, // 0.070505, 0.99751 + 0x3fb270dcefdfc45b, 0x3fefeab7df1c6005, // 0.072035, 0.9974 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fb339614e41ffa5, 0x3fefe8de8f03d75c, // 0.075094, 0.99718 + 0x3fb39d9f12c5a299, 0x3fefe7ea85482d60, // 0.076624, 0.99706 + 0x3fb401d9d0e3a507, 0x3fefe6f18ff42c84, // 0.078153, 0.99694 + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682 + 0x3fb4ca45fc1ba8b6, 0x3fefe4f0e31d7a4a, // 0.081211, 0.9967 + 0x3fb52e774a4d4d0a, 0x3fefe3e92be9d886, // 0.08274, 0.99657 + 0x3fb592a554489bc8, 0x3fefe2dc89bbff08, // 0.084269, 0.99644 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb65af75dd0f87b, 0x3fefe0b485181be3, // 0.087326, 0.99618 + 0x3fb6bf1b3e79b129, 0x3fefdf9922f73307, // 0.088854, 0.99604 + 0x3fb7233b9d236e71, 0x3fefde78d68653fd, // 0.090381, 0.99591 + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577 + 0x3fb7eb7196b72ee4, 0x3fefdc297f674ba9, // 0.093436, 0.99563 + 0x3fb84f8712c130a0, 0x3fefdafa7514538c, // 0.094963, 0.99548 + 0x3fb8b398cf0c38e0, 0x3fefd9c68127c78c, // 0.09649, 0.99533 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb97bb0caaba56f, 0x3fefd74fdd40abbf, // 0.099544, 0.99503 + 0x3fb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // 0.10107, 0.99488 + 0x3fba43b90e27f3c4, 0x3fefd4c59536fae4, // 0.1026, 0.99472 + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456 + 0x3fbb0bb11e1d5559, 0x3fefd227aa9bd53b, // 0.10565, 0.9944 + 0x3fbb6fa6ec38f64c, 0x3fefd0d158d86087, // 0.10717, 0.99424 + 0x3fbbd3987f31fa0e, 0x3fefcf761f0c77a3, // 0.1087, 0.99407 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fbc9b6eb6165c42, 0x3fefccb0f4323aa3, // 0.11175, 0.99374 + 0x3fbcff533b307dc1, 0x3fefcb4703914354, // 0.11327, 0.99356 + 0x3fbd633347858ce4, 0x3fefc9d82bc2915e, // 0.11479, 0.99339 + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321 + 0x3fbe2ae5b8457f77, 0x3fefc6ebc77f0887, // 0.11784, 0.99303 + 0x3fbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // 0.11937, 0.99285 + 0x3fbef2858d27561b, 0x3fefc3ebc935454c, // 0.12089, 0.99267 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fbfba124b07ad85, 0x3fefc0d832bf043a, // 0.12393, 0.99229 + 0x3fc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // 0.12545, 0.9921 + 0x3fc040c5bb67747e, 0x3fefbdb106021816, // 0.12698, 0.99191 + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171 + 0x3fc0a4784ab8bf1d, 0x3fefba7644f068b5, // 0.13002, 0.99151 + 0x3fc0d64dbcb26786, 0x3fefb8d18d66adb7, // 0.13154, 0.99131 + 0x3fc1082095f820b0, 0x3fefb727f187f1c7, // 0.13306, 0.99111 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fc16bbe5fac5865, 0x3fefb3c60dd2c199, // 0.1361, 0.9907 + 0x3fc19d8940be24e7, 0x3fefb20dc681d54d, // 0.13762, 0.99049 + 0x3fc1cf516a62a077, 0x3fefb0509be6f7db, // 0.13914, 0.99027 + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006 + 0x3fc232d978aed413, 0x3fefacc79de6c44f, // 0.14218, 0.98984 + 0x3fc264994dfd340a, 0x3fefaafbcb0cfddc, // 0.1437, 0.98962 + 0x3fc296564d2b953e, 0x3fefa92b1600657c, // 0.14521, 0.9894 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc2f9c7aa7a72af, 0x3fefa57b066e2754, // 0.14825, 0.98895 + 0x3fc32b7bf94516a7, 0x3fefa39bac7a1791, // 0.14976, 0.98872 + 0x3fc35d2d53440db2, 0x3fefa1b7717661d5, // 0.15128, 0.98849 + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826 + 0x3fc3c0870a383ff6, 0x3fef9de0596b77a3, // 0.15431, 0.98802 + 0x3fc3f22f57db4893, 0x3fef9bed7cfbde29, // 0.15583, 0.98778 + 0x3fc423d4920e4166, 0x3fef99f5c0abd496, // 0.15734, 0.98754 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc48715ad84cdf5, 0x3fef95f7a9a1ec47, // 0.16037, 0.98706 + 0x3fc4b8b17f79fa88, 0x3fef93f14f85ac08, // 0.16189, 0.98681 + 0x3fc4ea4a1f624b61, 0x3fef91e616c43891, // 0.1634, 0.98656 + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631 + 0x3fc54d71aa74ef02, 0x3fef8dc10a95380d, // 0.16643, 0.98605 + 0x3fc57f008654cbde, 0x3fef8ba737cb4b78, // 0.16794, 0.9858 + 0x3fc5b08c1192e381, 0x3fef898887a36c84, // 0.16945, 0.98554 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc61399179a6e94, 0x3fef853c9089595e, // 0.17247, 0.98501 + 0x3fc6451a831d830d, 0x3fef830f4a40c60c, // 0.17398, 0.98475 + 0x3fc676987f7216b8, 0x3fef80dd27ed8204, // 0.17549, 0.98448 + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421 + 0x3fc6d98a0c08c8da, 0x3fef7c6a50826840, // 0.17851, 0.98394 + 0x3fc70afd8d08c4ff, 0x3fef7a299c1a322a, // 0.18002, 0.98366 + 0x3fc73c6d8055fe0a, 0x3fef77e40d068a90, // 0.18153, 0.98339 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc79f429f59e11d, 0x3fef734a60446279, // 0.18455, 0.98282 + 0x3fc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // 0.18606, 0.98254 + 0x3fc802092c1d744b, 0x3fef6e9d4d1262ca, // 0.18756, 0.98225 + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196 + 0x3fc864c0e9b2b6cf, 0x3fef69dcd652f5de, // 0.19057, 0.98167 + 0x3fc8961727c41804, 0x3fef677556883cee, // 0.19208, 0.98138 + 0x3fc8c7699b34ca7e, 0x3fef6508fef47bd5, // 0.19359, 0.98108 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc92a0303c8194f, 0x3fef6021c9f148c2, // 0.19659, 0.98048 + 0x3fc95b49e9b62af9, 0x3fef5da6ed43685d, // 0.1981, 0.98018 + 0x3fc98c8ce69a7aec, 0x3fef5b273a4fa2d9, // 0.1996, 0.97988 + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957 + 0x3fc9ef0706e35a35, 0x3fef56195321c090, // 0.20261, 0.97926 + 0x3fca203e1b1831da, 0x3fef538b1faf2d07, // 0.20411, 0.97895 + 0x3fca517127e3dabc, 0x3fef50f81785c6b9, // 0.20561, 0.97863 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fcab3cb0ce6fe44, 0x3fef4bc38aa5c694, // 0.20861, 0.978 + 0x3fcae4f1d5f3b9ab, 0x3fef492206bcabb4, // 0.21011, 0.97768 + 0x3fcb16147941ca2a, 0x3fef467bafb7bbe0, // 0.21161, 0.97735 + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703 + 0x3fcb784d30536cda, 0x3fef412089fd8adc, // 0.21461, 0.9767 + 0x3fcba96334f15dad, 0x3fef3e6bbc1bbc65, // 0.21611, 0.97637 + 0x3fcbda74f5856330, 0x3fef3bb21cc4fe47, // 0.2176, 0.97604 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcc3c8b8c4b9dd7, 0x3fef36306b67c556, // 0.2206, 0.97536 + 0x3fcc6d90535d74dc, 0x3fef33685a3aaef0, // 0.22209, 0.97503 + 0x3fcc9e90b824a6a9, 0x3fef309b794b719f, // 0.22359, 0.97468 + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434 + 0x3fcd00843c99c5f9, 0x3fef2af349e17507, // 0.22658, 0.97399 + 0x3fcd31774d2cbdee, 0x3fef2817fc4609ce, // 0.22807, 0.97364 + 0x3fcd6265dd3f27e3, 0x3fef2537e0a71f9f, // 0.22957, 0.97329 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcdc4355db40195, 0x3fef1f6941259d7a, // 0.23255, 0.97258 + 0x3fcdf5163f01099a, 0x3fef1c7abe284708, // 0.23404, 0.97223 + 0x3fce25f281a2b684, 0x3fef19876ef1f486, // 0.23553, 0.97187 + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715 + 0x3fce879d0cc0fdaf, 0x3fef13926dad024e, // 0.23851, 0.97114 + 0x3fceb86b462de348, 0x3fef1090bc898f5f, // 0.24, 0.97077 + 0x3fcee934c2d006c7, 0x3fef0d8a410379c5, // 0.24149, 0.9704 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fcf4ab9679c9f5c, 0x3fef076eecade0fa, // 0.24447, 0.96966 + 0x3fcf7b7480bd3801, 0x3fef045a14cf738c, // 0.24596, 0.96928 + 0x3fcfac2abeff57ff, 0x3fef014074708ed3, // 0.24744, 0.9689 + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852 + 0x3fd006c4466e54af, 0x3feefafedc1ba8b7, // 0.25041, 0.96814 + 0x3fd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // 0.2519, 0.96775 + 0x3fd037694a928cac, 0x3feef4aa278b2032, // 0.25338, 0.96737 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fd068044deab002, 0x3feeee425aa6b09a, // 0.25635, 0.96658 + 0x3fd0804e05eb661e, 0x3feeeb074c50a544, // 0.25783, 0.96619 + 0x3fd09895327b465e, 0x3feee7c77961dc9e, // 0.25931, 0.96579 + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539 + 0x3fd0c91bda4f158d, 0x3feee13987bbebdc, // 0.26227, 0.96499 + 0x3fd0e15b4e1749cd, 0x3feeddeb6a078651, // 0.26375, 0.96459 + 0x3fd0f998277733f7, 0x3feeda9889bfe86a, // 0.26523, 0.96418 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd12a09fc0b1b12, 0x3feed3e483849c51, // 0.26819, 0.96337 + 0x3fd1423eefc69378, 0x3feed0835e999009, // 0.26967, 0.96295 + 0x3fd15a713a28b9d9, 0x3feecd1d792c8f10, // 0.27115, 0.96254 + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212 + 0x3fd18acdc3f4873a, 0x3feec6436ee60309, // 0.2741, 0.9617 + 0x3fd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // 0.27557, 0.96128 + 0x3fd1bb1f7b999480, 0x3feebf5668eaf2ef, // 0.27705, 0.96086 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd1eb6643499fbb, 0x3feeb8566b810f2a, // 0.27999, 0.96 + 0x3fd2038583d727bd, 0x3feeb4cf515b8811, // 0.28146, 0.95957 + 0x3fd21ba1fd3d2623, 0x3feeb1437af9bb34, // 0.28294, 0.95914 + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587 + 0x3fd24bd28bb37672, 0x3feeaa1d9bb20af3, // 0.28588, 0.95827 + 0x3fd263e6995554ba, 0x3feea68393e65800, // 0.28735, 0.95783 + 0x3fd27bf7d0f2c346, 0x3feea2e4d212c000, // 0.28882, 0.95738 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd2ac11af483572, 0x3fee9b99229046f8, // 0.29175, 0.95649 + 0x3fd2c41a4e954520, 0x3fee97ec36016b30, // 0.29322, 0.95605 + 0x3fd2dc200907fe51, 0x3fee943a91aab4b4, // 0.29469, 0.95559 + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514 + 0x3fd30c22c08d6a13, 0x3fee8cc923edc388, // 0.29762, 0.95469 + 0x3fd3241fb638baaf, 0x3fee89095bad6025, // 0.29908, 0.95423 + 0x3fd33c19b83af207, 0x3fee8544ddf0d075, // 0.30054, 0.95377 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd36c04d27a4edf, 0x3fee7dadc456d850, // 0.30347, 0.95284 + 0x3fd383f5e353b6aa, 0x3fee79db29a5165a, // 0.30493, 0.95238 + 0x3fd39be3f1bc8aef, 0x3fee7603dbce74e9, // 0.30639, 0.95191 + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144 + 0x3fd3cbb6f87a146e, 0x3fee6e472911da27, // 0.30931, 0.95096 + 0x3fd3e39be96ec271, 0x3fee6a61c55d53a7, // 0.31077, 0.95049 + 0x3fd3fb7dc932cfa4, 0x3fee6677b0e6d31e, // 0.31222, 0.95001 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd42b38466e2928, 0x3fee5e95781ebf1c, // 0.31514, 0.94905 + 0x3fd44310dc8936f0, 0x3fee5a9d550467d3, // 0.31659, 0.94856 + 0x3fd45ae652bb2800, 0x3fee56a083968eb1, // 0.31805, 0.94807 + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759 + 0x3fd48a87d0b07fd7, 0x3fee4e98d836c0af, // 0.32096, 0.94709 + 0x3fd4a253d11b82f3, 0x3fee4a8dff81ce5e, // 0.32241, 0.9466 + 0x3fd4ba1ca2eca31c, 0x3fee467e7af35f23, // 0.32386, 0.94611 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd4e9a4ac15d520, 0x3fee3e5170cbfc46, // 0.32676, 0.94511 + 0x3fd50163dc197047, 0x3fee3a33ec75ce85, // 0.32821, 0.9446 + 0x3fd5191fceda3c35, 0x3fee3611becbaf69, // 0.32966, 0.9441 + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359 + 0x3fd5488dedeff3be, 0x3fee2dbf6a0911d9, // 0.33255, 0.94308 + 0x3fd5604012f467b4, 0x3fee298f4439197a, // 0.334, 0.94257 + 0x3fd577eeec151e47, 0x3fee255a77a63bb8, // 0.33545, 0.94206 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd5a742ac0ff78d, 0x3fee1ce2ecd0c0d8, // 0.33833, 0.94103 + 0x3fd5bee78b9db3b6, 0x3fee18a02fdc66d9, // 0.33978, 0.94051 + 0x3fd5d68910aee686, 0x3fee1458cec1ad83, // 0.34122, 0.93998 + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946 + 0x3fd605c1fcc88f63, 0x3fee0bbc22bd8349, // 0.3441, 0.93893 + 0x3fd61d595c88c203, 0x3fee0766d9280f54, // 0.34554, 0.9384 + 0x3fd634ed533be58e, 0x3fee030cee1435b8, // 0.34698, 0.93787 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd6640af6f03d9e, 0x3fedfa4b3621271d, // 0.34986, 0.9368 + 0x3fd67b949cad63ca, 0x3fedf5e36a9ba59c, // 0.35129, 0.93627 + 0x3fd6931acad55f51, 0x3fedf177004b2534, // 0.35273, 0.93573 + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518 + 0x3fd6c21cb1e39771, 0x3fede890520465ce, // 0.3556, 0.93464 + 0x3fd6d998638a0cb5, 0x3fede4160f6d8d81, // 0.35703, 0.93409 + 0x3fd6f1108f1bc9c5, 0x3feddf9730ca837b, // 0.35846, 0.93354 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd71ff6458782ec, 0x3fedd68ba2267a25, // 0.36133, 0.93244 + 0x3fd73763c9261092, 0x3fedd1fef38a915a, // 0.36276, 0.93188 + 0x3fd74ecdb8390a3e, 0x3fedcd6dabaca3a5, // 0.36418, 0.93133 + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077 + 0x3fd77d96ca4b73a6, 0x3fedc43d52fcb453, // 0.36704, 0.93021 + 0x3fd794f5e613dfae, 0x3fedbf9e4395759a, // 0.36847, 0.92964 + 0x3fd7ac515ee2b172, 0x3fedbafa9dc1b78d, // 0.36989, 0.92907 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd7dafd592ba621, 0x3fedb1a591b20c38, // 0.37274, 0.92794 + 0x3fd7f24dd37341e3, 0x3fedacf42ce68ab9, // 0.37416, 0.92736 + 0x3fd8099a9c5c362d, 0x3feda83e348f613b, // 0.37559, 0.92679 + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621 + 0x3fd838290bb359c8, 0x3fed9ec48c26b1f3, // 0.37843, 0.92563 + 0x3fd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // 0.37985, 0.92505 + 0x3fd866a88a792ea0, 0x3fed95389e50429b, // 0.38127, 0.92447 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd89518fbff098e, 0x3fed8b9a70ef9cb4, // 0.3841, 0.92329 + 0x3fd8ac4b86d5ed44, 0x3fed86c48445a450, // 0.38552, 0.9227 + 0x3fd8c37a439f884f, 0x3fed81ea09f38b63, // 0.38693, 0.92211 + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151 + 0x3fd8f1cc44bea329, 0x3fed78276f5617c6, // 0.38976, 0.92092 + 0x3fd908ef81ef7bd1, 0x3fed733f508c0dff, // 0.39117, 0.92032 + 0x3fd9200ee2c9be97, 0x3fed6e52a71c8547, // 0.39258, 0.91972 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd94e420137bce3, 0x3fed646bb7574de5, // 0.3954, 0.91851 + 0x3fd96555b7ab948f, 0x3fed5f7172888a7f, // 0.39681, 0.9179 + 0x3fd97c6583890fc2, 0x3fed5a72a6221e73, // 0.39822, 0.91729 + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668 + 0x3fd9aa794d47c9ee, 0x3fed506779a3d2d9, // 0.40103, 0.91606 + 0x3fd9c17d440df9f2, 0x3fed4b5b1b187524, // 0.40243, 0.91545 + 0x3fd9d87d4207b0ab, 0x3fed464a380e7242, // 0.40384, 0.91483 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fda067145664d57, 0x3fed3c1ae79f2b4e, // 0.40664, 0.91359 + 0x3fda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // 0.40804, 0.91296 + 0x3fda34553b0afee5, 0x3fed31d98e9e503a, // 0.40944, 0.91234 + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171 + 0x3fda622906a70b63, 0x3fed2786335f52fc, // 0.41224, 0.91107 + 0x3fda790cd3dbf31a, 0x3fed2255c6e5a4e1, // 0.41364, 0.91044 + 0x3fda8fec8bf5b166, 0x3fed1d20dc40c15c, // 0.41503, 0.90981 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fdabd9faebc3980, 0x3fed12a98fac410c, // 0.41782, 0.90853 + 0x3fdad473125cdc08, 0x3fed0d672f59d2b9, // 0.41922, 0.90789 + 0x3fdaeb4252ca07ab, 0x3fed082054168bac, // 0.42061, 0.90724 + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066 + 0x3fdb18d45bf8aca6, 0x3fecfd852fff6ad4, // 0.42339, 0.90595 + 0x3fdb2f971db31972, 0x3fecf830e8ce467b, // 0.42478, 0.9053 + 0x3fdb4655ae2bf757, 0x3fecf2d829f1b40e, // 0.42617, 0.90464 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdb73c62d520624, 0x3fece819488344ce, // 0.42894, 0.90333 + 0x3fdb8a7814fd5693, 0x3fece2b32799a060, // 0.43033, 0.90267 + 0x3fdba125bd63583e, 0x3fecdd489254fe65, // 0.43171, 0.90201 + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135 + 0x3fdbce744262deee, 0x3fecd2660e12c1e6, // 0.43448, 0.90068 + 0x3fdbe51517ffc0d9, 0x3fecccee20c2de9f, // 0.43586, 0.90002 + 0x3fdbfbb1a05e0edc, 0x3fecc771c2736c09, // 0.43724, 0.89935 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdc28ddbb6cf145, 0x3fecbc6bb638d10b, // 0.43999, 0.898 + 0x3fdc3f6d47263129, 0x3fecb6e20a00da99, // 0.44137, 0.89732 + 0x3fdc55f877b23537, 0x3fecb153f02fb87d, // 0.44275, 0.89665 + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597 + 0x3fdc8301b95b40c2, 0x3feca62a772fd919, // 0.4455, 0.89528 + 0x3fdc997fc3865388, 0x3feca08f19b9c449, // 0.44687, 0.8946 + 0x3fdcaff964a0421d, 0x3fec9aef521bd480, // 0.44824, 0.89391 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdcdcdf5dc440ce, 0x3fec8fa287e13305, // 0.45098, 0.89253 + 0x3fdcf34baee1cd21, 0x3fec89f587029c13, // 0.45235, 0.89184 + 0x3fdd09b389152ec1, 0x3fec84441f785f61, // 0.45372, 0.89115 + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045 + 0x3fdd3675caebf962, 0x3fec78d41fe4a267, // 0.45645, 0.88975 + 0x3fdd4cd02ba8609c, 0x3fec7315899eaad7, // 0.45781, 0.88905 + 0x3fdd632607ac9aa9, 0x3fec6d5290341eb2, // 0.45918, 0.88835 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdd8fc423c62a25, 0x3fec61bf777fcc48, // 0.4619, 0.88693 + 0x3fdda60c5cfa10d8, 0x3fec5bef59fef85a, // 0.46326, 0.88622 + 0x3fddbc5003b2edf8, 0x3fec561adceb743e, // 0.46462, 0.88551 + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848 + 0x3fdde8c98bf86bd6, 0x3fec4a64c7a5ac4c, // 0.46733, 0.88408 + 0x3fddfeff66a941de, 0x3fec44833141c004, // 0.46869, 0.88336 + 0x3fde1530a12779f4, 0x3fec3e9d3ee7d262, // 0.47004, 0.88264 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fde418527dc4ffa, 0x3fec32c449f60831, // 0.47275, 0.8812 + 0x3fde57a86d3cd824, 0x3fec2cd14931e3f1, // 0.4741, 0.88047 + 0x3fde6dc704be97e2, 0x3fec26d9f01f2eaf, // 0.47545, 0.87974 + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901 + 0x3fde99f61c817eda, 0x3fec1ade38bce19b, // 0.47815, 0.87828 + 0x3fdeb00695f25620, 0x3fec14d9dc465e58, // 0.47949, 0.87755 + 0x3fdec61253e3c61b, 0x3fec0ed12b3372e9, // 0.48084, 0.87681 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fdef21b8fafd3b5, 0x3fec02b2cef1e641, // 0.48353, 0.87533 + 0x3fdf081906bff7fd, 0x3febfc9d25a1b147, // 0.48487, 0.87459 + 0x3fdf1e11b4bbc35c, 0x3febf6832b71ec5b, // 0.48621, 0.87384 + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309 + 0x3fdf49f4a7e97729, 0x3febea424837de6d, // 0.48889, 0.87235 + 0x3fdf5fdee656cda3, 0x3febe41b611154c1, // 0.49023, 0.8716 + 0x3fdf75c44e26a852, 0x3febddf02cd2b983, // 0.49156, 0.87084 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdfa1808c6cf7e0, 0x3febd18ce0dc19d6, // 0.49423, 0.86933 + 0x3fdfb7575c24d2de, 0x3febcb54cb0d2327, // 0.49557, 0.86857 + 0x3fdfcd2947c1ff57, 0x3febc5186bf8361d, // 0.4969, 0.86781 + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705 + 0x3fdff8be6537615e, 0x3febb892d5d5dad5, // 0.49956, 0.86628 + 0x3fe00740c82b82e0, 0x3febb249a0b6c40d, // 0.50089, 0.86551 + 0x3fe0121fe4f56d2c, 0x3febabfc262e6586, // 0.50221, 0.86474 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fe027d6ad83287e, 0x3feb9f5464c5bffc, // 0.50486, 0.8632 + 0x3fe032ae55edbd95, 0x3feb98fa1fd9155e, // 0.50619, 0.86242 + 0x3fe03d837edff370, 0x3feb929b996a5b7f, // 0.50751, 0.86165 + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087 + 0x3fe053264bad0483, 0x3feb85d1cbf52c02, // 0.51015, 0.86009 + 0x3fe05df3ec31b8b6, 0x3feb7f6686e792ea, // 0.51147, 0.8593 + 0x3fe068bf0691c028, 0x3feb78f70449a34b, // 0.51279, 0.85852 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe07e4da23bc102, 0x3feb6c0b4a55ac17, // 0.51542, 0.85694 + 0x3fe089112032b08c, 0x3feb658f14fdbc47, // 0.51673, 0.85615 + 0x3fe093d2115ee018, 0x3feb5f0ea611a532, // 0.51804, 0.85535 + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456 + 0x3fe0a94c46b53d0b, 0x3feb52011f805c92, // 0.52067, 0.85376 + 0x3fe0b405878f85ec, 0x3feb4b7409de7925, // 0.52198, 0.85296 + 0x3fe0bebc34ff4646, 0x3feb44e2beaf0a61, // 0.52328, 0.85216 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe0d421cf03c12b, 0x3feb37b38bb54c09, // 0.5259, 0.85055 + 0x3fe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // 0.5272, 0.84974 + 0x3fe0e97d078fd23b, 0x3feb2a738eb51f33, // 0.5285, 0.84893 + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812 + 0x3fe0fecdd1770537, 0x3feb1d22cfdadcc6, // 0.5311, 0.84731 + 0x3fe1097248d0a956, 0x3feb16742a4ca2f5, // 0.5324, 0.84649 + 0x3fe114141f935545, 0x3feb0fc1575d33db, // 0.5337, 0.84567 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe1294fe4c5350a, 0x3feb024f2d7d24a9, // 0.53629, 0.84403 + 0x3fe133e9cfee254e, 0x3feafb8fd89f57b6, // 0.53759, 0.84321 + 0x3fe13e8113f396c1, 0x3feaf4cc5a85fb73, // 0.53888, 0.84238 + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155 + 0x3fe153a7a00bf453, 0x3feae738e6cd4b67, // 0.54146, 0.84073 + 0x3fe15e36e4dbe2bc, 0x3feae068f345ecef, // 0.54275, 0.83989 + 0x3fe168c37c025764, 0x3fead994dab2e979, // 0.54404, 0.83906 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe17dd49ad16161, 0x3feacbe03ea0e73b, // 0.54661, 0.83739 + 0x3fe188591f3a46e5, 0x3feac4ffbd3efac8, // 0.54789, 0.83655 + 0x3fe192daef7a5386, 0x3feabe1b1b0b8dac, // 0.54918, 0.83571 + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486 + 0x3fe1a7d66d0516e6, 0x3feab045787157ff, // 0.55174, 0.83402 + 0x3fe1b250171373be, 0x3feaa9547a2cb98e, // 0.55302, 0.83317 + 0x3fe1bcc706804467, 0x3feaa25f5f5aee60, // 0.55429, 0.83232 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe1d1acaf012cc2, 0x3fea9468d85b20ae, // 0.55685, 0.83062 + 0x3fe1dc1b64dc4872, 0x3fea8d676e545ad2, // 0.55812, 0.82976 + 0x3fe1e68759a3e074, 0x3fea8661ec0ee133, // 0.55939, 0.8289 + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805 + 0x3fe1fb56f98b37b8, 0x3fea784aa31d3f55, // 0.56193, 0.82718 + 0x3fe205baa17560d6, 0x3fea7138de9d60f5, // 0.5632, 0.82632 + 0x3fe2101b81e0da78, 0x3fea6a230637623b, // 0.56447, 0.82546 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe224d4e5d5482e, 0x3fea5beb1e188375, // 0.567, 0.82372 + 0x3fe22f2d662c13e1, 0x3fea54c91090f524, // 0.56826, 0.82285 + 0x3fe23983189fdfd5, 0x3fea4da2f385e997, // 0.56952, 0.82198 + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211 + 0x3fe24e260d7ee7c9, 0x3fea3f4a8f4ee2d2, // 0.57204, 0.82023 + 0x3fe258734cbb7110, 0x3fea38184a593bc6, // 0.5733, 0.81935 + 0x3fe262bdb7b795a2, 0x3fea30e1fa4cbf81, // 0.57455, 0.81847 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe2774a0a961612, 0x3fea22693d62ccb9, // 0.57706, 0.8167 + 0x3fe2818bef4d3cba, 0x3fea1b26d2c0a75e, // 0.57831, 0.81581 + 0x3fe28bcaf96d94ba, 0x3fea13e0617e4ec7, // 0.57956, 0.81493 + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404 + 0x3fe2a040779843fb, 0x3fea05476f967bb5, // 0.58206, 0.81314 + 0x3fe2aa76e87aeb58, 0x3fe9fdf4f13149de, // 0.58331, 0.81225 + 0x3fe2b4aa787764c4, 0x3fe9f69e70ac75bc, // 0.58455, 0.81135 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe2c908ef734e57, 0x3fe9e7e56dcb45bd, // 0.58704, 0.80956 + 0x3fe2d333d34e9bb7, 0x3fe9e082edb42472, // 0.58828, 0.80866 + 0x3fe2dd5bcffb7616, 0x3fe9d91c7007d5a6, // 0.58952, 0.80775 + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685 + 0x3fe2f1a30d86773a, 0x3fe9ca438080eadb, // 0.592, 0.80594 + 0x3fe2fbc24b441015, 0x3fe9c2d110f075c3, // 0.59323, 0.80503 + 0x3fe305de9b921a94, 0x3fe9bb5aa85f2098, // 0.59447, 0.80412 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe31a0e6da35e44, 0x3fe9ac61f0d4e247, // 0.59693, 0.80229 + 0x3fe32421ec49a620, 0x3fe9a4dfa42b06b2, // 0.59816, 0.80138 + 0x3fe32e3277467d6b, 0x3fe99d59631e65d5, // 0.59939, 0.80046 + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954 + 0x3fe3424aac0ef7d6, 0x3fe98e410881a600, // 0.60184, 0.79861 + 0x3fe34c5252c14de1, 0x3fe986aef1457594, // 0.60307, 0.79769 + 0x3fe35656ff9799ae, 0x3fe97f18ea4e5c9e, // 0.60429, 0.79676 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe36a576582831b, 0x3fe96fe111ddfce0, // 0.60673, 0.79491 + 0x3fe374531b817f8d, 0x3fe9683f42bd7fe1, // 0.60795, 0.79398 + 0x3fe37e4bd1792fe2, 0x3fe960998893ad8c, // 0.60917, 0.79304 + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211 + 0x3fe39234372c7f04, 0x3fe9514257dc4335, // 0.6116, 0.79117 + 0x3fe39c23e3d63029, 0x3fe94990e3ac4a6c, // 0.61281, 0.79023 + 0x3fe3a6108a54ba58, 0x3fe941db892e3a65, // 0.61402, 0.78929 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe3b9e0beb19e18, 0x3fe932652609b1cf, // 0.61644, 0.7874 + 0x3fe3c3c44981c517, 0x3fe92aa41fc5a815, // 0.61765, 0.78646 + 0x3fe3cda4c80a6076, 0x3fe922df37f8646a, // 0.61885, 0.78551 + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456 + 0x3fe3e15c9a2db922, 0x3fe91349c88da398, // 0.62126, 0.7836 + 0x3fe3eb33eabe0680, 0x3fe90b7943575efe, // 0.62246, 0.78265 + 0x3fe3f50828f1e8d2, 0x3fe903a4e1665133, // 0.62366, 0.78169 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe408a76834c0c0, 0x3fe8f3f08c28d9ac, // 0.62606, 0.77978 + 0x3fe41272663d108c, 0x3fe8ec109b486c49, // 0.62725, 0.77882 + 0x3fe41c3a4bdbaa26, 0x3fe8e42cd2852e0a, // 0.62845, 0.77785 + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689 + 0x3fe42fc0c7d3adbb, 0x3fe8d459be34bdfa, // 0.63083, 0.77592 + 0x3fe4397f5b2a4380, 0x3fe8cc6a75184655, // 0.63202, 0.77495 + 0x3fe4433ad0117b1d, 0x3fe8c47758fa71cb, // 0.63321, 0.77398 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe456a858917046, 0x3fe8b485aca2a468, // 0.63558, 0.77204 + 0x3fe4605a692b32a2, 0x3fe8ac871ede1d88, // 0.63676, 0.77106 + 0x3fe46a095557a0f1, 0x3fe8a484c3031d50, // 0.63794, 0.77008 + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691 + 0x3fe47d5dba6fde01, 0x3fe89474a5fb0a84, // 0.6403, 0.76812 + 0x3fe48703306091fe, 0x3fe88c66e7481ba1, // 0.64148, 0.76714 + 0x3fe490a57bedbcdf, 0x3fe884555f72fa6b, // 0.64266, 0.76615 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe4a3e08dec9ed6, 0x3fe87426f95cd5bd, // 0.645, 0.76418 + 0x3fe4ad79516722f0, 0x3fe86c0a1d9aa195, // 0.64618, 0.76319 + 0x3fe4b70ee48fb869, 0x3fe863e97db3d95a, // 0.64735, 0.7622 + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612 + 0x3fe4ca30740218a3, 0x3fe8539cf67c9029, // 0.64968, 0.76021 + 0x3fe4d3bc6d589f80, 0x3fe84b7111af83f9, // 0.65085, 0.75921 + 0x3fe4dd453076b064, 0x3fe843416dc4cce2, // 0.65201, 0.75821 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe4f04d0e2859aa, 0x3fe832d6eda3a3e0, // 0.65433, 0.75621 + 0x3fe4f9cc25cca486, 0x3fe82a9c13f545ff, // 0.65549, 0.7552 + 0x3fe503480159ded2, 0x3fe8225d803964e5, // 0.65665, 0.75419 + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319 + 0x3fe51635fe5601d7, 0x3fe811d52faf94dc, // 0.65896, 0.75218 + 0x3fe51fa81cd99aa6, 0x3fe8098b756e52fa, // 0.66011, 0.75117 + 0x3fe52916f96f8388, 0x3fe8013e0638e795, // 0.66127, 0.75015 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe53beae7012abe, 0x3fe7f0980e113978, // 0.66356, 0.74812 + 0x3fe5454ff5159dfb, 0x3fe7e83f87b03686, // 0.66471, 0.7471 + 0x3fe54eb1bb6dcb8f, 0x3fe7dfe3517d8937, // 0.66586, 0.74608 + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506 + 0x3fe5616b6b204e6e, 0x3fe7cf1fdacbf179, // 0.66814, 0.74403 + 0x3fe56ac35197649e, 0x3fe7c6b89ce2d333, // 0.66928, 0.74301 + 0x3fe57417ea8bb75c, 0x3fe7be4db453a27c, // 0.67042, 0.74198 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe586b72e2b2cfd, 0x3fe7ad6ce874dbb6, // 0.67269, 0.73992 + 0x3fe59001d5f723df, 0x3fe7a4f707bf97d2, // 0.67383, 0.73889 + 0x3fe599492a81ffbc, 0x3fe79c7d8198e56e, // 0.67496, 0.73785 + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682 + 0x3fe5abcdd41bb0d8, 0x3fe78b7f8a320a52, // 0.67722, 0.73578 + 0x3fe5b50b264f7448, 0x3fe782fb1b90b35b, // 0.67835, 0.73474 + 0x3fe5be451f8bf980, 0x3fe77a730cbb9100, // 0.67948, 0.7337 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe5d0af016ed1d4, 0x3fe7695813b9b594, // 0.68172, 0.73161 + 0x3fe5d9dee73e345c, 0x3fe760c52c304764, // 0.68285, 0.73056 + 0x3fe5e30b6e6877f3, 0x3fe7582ea9b9a329, // 0.68397, 0.72951 + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846 + 0x3fe5f55a5b2576f8, 0x3fe746f6d9516d59, // 0.6862, 0.72741 + 0x3fe5fe7cbde56a0f, 0x3fe73e558e079942, // 0.68732, 0.72636 + 0x3fe6079bbc5aadfa, 0x3fe735b0ad2009b2, // 0.68843, 0.7253 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe619cf86c55702, 0x3fe7245c2fcd492a, // 0.69065, 0.72319 + 0x3fe622e44fec22ff, 0x3fe71bac960e41bf, // 0.69176, 0.72213 + 0x3fe62bf5af2b0dfd, 0x3fe712f96c09d18d, // 0.69287, 0.72107 + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72 + 0x3fe63e0e2a59d7aa, 0x3fe701886c8f16e6, // 0.69508, 0.71894 + 0x3fe64715437f535b, 0x3fe6f8ca99c95b75, // 0.69618, 0.71787 + 0x3fe65018ed28287f, 0x3fe6f0093c1f54de, // 0.69728, 0.7168 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe66215ec74eb91, 0x3fe6de7be585881d, // 0.69947, 0.71466 + 0x3fe66b0f3f52b386, 0x3fe6d5afef4aafcc, // 0.70057, 0.71358 + 0x3fe674051d27896c, 0x3fe6cce07395679f, // 0.70166, 0.71251 + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143 + 0x3fe685e6742feeef, 0x3fe6bb36f12b5e06, // 0.70385, 0.71035 + 0x3fe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // 0.70493, 0.70927 + 0x3fe697b9e686941c, 0x3fe6a97f692c82ea, // 0.70602, 0.70819 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe6a97f692c82ea, 0x3fe697b9e686941c, // 0.70819, 0.70602 + 0x3fe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // 0.70927, 0.70493 + 0x3fe6bb36f12b5e06, 0x3fe685e6742feeef, // 0.71035, 0.70385 + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275 + 0x3fe6cce07395679f, 0x3fe674051d27896c, // 0.71251, 0.70166 + 0x3fe6d5afef4aafcc, 0x3fe66b0f3f52b386, // 0.71358, 0.70057 + 0x3fe6de7be585881d, 0x3fe66215ec74eb91, // 0.71466, 0.69947 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6f0093c1f54de, 0x3fe65018ed28287f, // 0.7168, 0.69728 + 0x3fe6f8ca99c95b75, 0x3fe64715437f535b, // 0.71787, 0.69618 + 0x3fe701886c8f16e6, 0x3fe63e0e2a59d7aa, // 0.71894, 0.69508 + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397 + 0x3fe712f96c09d18d, 0x3fe62bf5af2b0dfd, // 0.72107, 0.69287 + 0x3fe71bac960e41bf, 0x3fe622e44fec22ff, // 0.72213, 0.69176 + 0x3fe7245c2fcd492a, 0x3fe619cf86c55702, // 0.72319, 0.69065 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe735b0ad2009b2, 0x3fe6079bbc5aadfa, // 0.7253, 0.68843 + 0x3fe73e558e079942, 0x3fe5fe7cbde56a0f, // 0.72636, 0.68732 + 0x3fe746f6d9516d59, 0x3fe5f55a5b2576f8, // 0.72741, 0.6862 + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508 + 0x3fe7582ea9b9a329, 0x3fe5e30b6e6877f3, // 0.72951, 0.68397 + 0x3fe760c52c304764, 0x3fe5d9dee73e345c, // 0.73056, 0.68285 + 0x3fe7695813b9b594, 0x3fe5d0af016ed1d4, // 0.73161, 0.68172 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe77a730cbb9100, 0x3fe5be451f8bf980, // 0.7337, 0.67948 + 0x3fe782fb1b90b35b, 0x3fe5b50b264f7448, // 0.73474, 0.67835 + 0x3fe78b7f8a320a52, 0x3fe5abcdd41bb0d8, // 0.73578, 0.67722 + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609 + 0x3fe79c7d8198e56e, 0x3fe599492a81ffbc, // 0.73785, 0.67496 + 0x3fe7a4f707bf97d2, 0x3fe59001d5f723df, // 0.73889, 0.67383 + 0x3fe7ad6ce874dbb6, 0x3fe586b72e2b2cfd, // 0.73992, 0.67269 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe7be4db453a27c, 0x3fe57417ea8bb75c, // 0.74198, 0.67042 + 0x3fe7c6b89ce2d333, 0x3fe56ac35197649e, // 0.74301, 0.66928 + 0x3fe7cf1fdacbf179, 0x3fe5616b6b204e6e, // 0.74403, 0.66814 + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667 + 0x3fe7dfe3517d8937, 0x3fe54eb1bb6dcb8f, // 0.74608, 0.66586 + 0x3fe7e83f87b03686, 0x3fe5454ff5159dfb, // 0.7471, 0.66471 + 0x3fe7f0980e113978, 0x3fe53beae7012abe, // 0.74812, 0.66356 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe8013e0638e795, 0x3fe52916f96f8388, // 0.75015, 0.66127 + 0x3fe8098b756e52fa, 0x3fe51fa81cd99aa6, // 0.75117, 0.66011 + 0x3fe811d52faf94dc, 0x3fe51635fe5601d7, // 0.75218, 0.65896 + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781 + 0x3fe8225d803964e5, 0x3fe503480159ded2, // 0.75419, 0.65665 + 0x3fe82a9c13f545ff, 0x3fe4f9cc25cca486, // 0.7552, 0.65549 + 0x3fe832d6eda3a3e0, 0x3fe4f04d0e2859aa, // 0.75621, 0.65433 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe843416dc4cce2, 0x3fe4dd453076b064, // 0.75821, 0.65201 + 0x3fe84b7111af83f9, 0x3fe4d3bc6d589f80, // 0.75921, 0.65085 + 0x3fe8539cf67c9029, 0x3fe4ca30740218a3, // 0.76021, 0.64968 + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851 + 0x3fe863e97db3d95a, 0x3fe4b70ee48fb869, // 0.7622, 0.64735 + 0x3fe86c0a1d9aa195, 0x3fe4ad79516722f0, // 0.76319, 0.64618 + 0x3fe87426f95cd5bd, 0x3fe4a3e08dec9ed6, // 0.76418, 0.645 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe884555f72fa6b, 0x3fe490a57bedbcdf, // 0.76615, 0.64266 + 0x3fe88c66e7481ba1, 0x3fe48703306091fe, // 0.76714, 0.64148 + 0x3fe89474a5fb0a84, 0x3fe47d5dba6fde01, // 0.76812, 0.6403 + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912 + 0x3fe8a484c3031d50, 0x3fe46a095557a0f1, // 0.77008, 0.63794 + 0x3fe8ac871ede1d88, 0x3fe4605a692b32a2, // 0.77106, 0.63676 + 0x3fe8b485aca2a468, 0x3fe456a858917046, // 0.77204, 0.63558 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe8c47758fa71cb, 0x3fe4433ad0117b1d, // 0.77398, 0.63321 + 0x3fe8cc6a75184655, 0x3fe4397f5b2a4380, // 0.77495, 0.63202 + 0x3fe8d459be34bdfa, 0x3fe42fc0c7d3adbb, // 0.77592, 0.63083 + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964 + 0x3fe8e42cd2852e0a, 0x3fe41c3a4bdbaa26, // 0.77785, 0.62845 + 0x3fe8ec109b486c49, 0x3fe41272663d108c, // 0.77882, 0.62725 + 0x3fe8f3f08c28d9ac, 0x3fe408a76834c0c0, // 0.77978, 0.62606 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe903a4e1665133, 0x3fe3f50828f1e8d2, // 0.78169, 0.62366 + 0x3fe90b7943575efe, 0x3fe3eb33eabe0680, // 0.78265, 0.62246 + 0x3fe91349c88da398, 0x3fe3e15c9a2db922, // 0.7836, 0.62126 + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006 + 0x3fe922df37f8646a, 0x3fe3cda4c80a6076, // 0.78551, 0.61885 + 0x3fe92aa41fc5a815, 0x3fe3c3c44981c517, // 0.78646, 0.61765 + 0x3fe932652609b1cf, 0x3fe3b9e0beb19e18, // 0.7874, 0.61644 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe941db892e3a65, 0x3fe3a6108a54ba58, // 0.78929, 0.61402 + 0x3fe94990e3ac4a6c, 0x3fe39c23e3d63029, // 0.79023, 0.61281 + 0x3fe9514257dc4335, 0x3fe39234372c7f04, // 0.79117, 0.6116 + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038 + 0x3fe960998893ad8c, 0x3fe37e4bd1792fe2, // 0.79304, 0.60917 + 0x3fe9683f42bd7fe1, 0x3fe374531b817f8d, // 0.79398, 0.60795 + 0x3fe96fe111ddfce0, 0x3fe36a576582831b, // 0.79491, 0.60673 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe97f18ea4e5c9e, 0x3fe35656ff9799ae, // 0.79676, 0.60429 + 0x3fe986aef1457594, 0x3fe34c5252c14de1, // 0.79769, 0.60307 + 0x3fe98e410881a600, 0x3fe3424aac0ef7d6, // 0.79861, 0.60184 + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062 + 0x3fe99d59631e65d5, 0x3fe32e3277467d6b, // 0.80046, 0.59939 + 0x3fe9a4dfa42b06b2, 0x3fe32421ec49a620, // 0.80138, 0.59816 + 0x3fe9ac61f0d4e247, 0x3fe31a0e6da35e44, // 0.80229, 0.59693 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe9bb5aa85f2098, 0x3fe305de9b921a94, // 0.80412, 0.59447 + 0x3fe9c2d110f075c3, 0x3fe2fbc24b441015, // 0.80503, 0.59323 + 0x3fe9ca438080eadb, 0x3fe2f1a30d86773a, // 0.80594, 0.592 + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076 + 0x3fe9d91c7007d5a6, 0x3fe2dd5bcffb7616, // 0.80775, 0.58952 + 0x3fe9e082edb42472, 0x3fe2d333d34e9bb7, // 0.80866, 0.58828 + 0x3fe9e7e56dcb45bd, 0x3fe2c908ef734e57, // 0.80956, 0.58704 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9f69e70ac75bc, 0x3fe2b4aa787764c4, // 0.81135, 0.58455 + 0x3fe9fdf4f13149de, 0x3fe2aa76e87aeb58, // 0.81225, 0.58331 + 0x3fea05476f967bb5, 0x3fe2a040779843fb, // 0.81314, 0.58206 + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081 + 0x3fea13e0617e4ec7, 0x3fe28bcaf96d94ba, // 0.81493, 0.57956 + 0x3fea1b26d2c0a75e, 0x3fe2818bef4d3cba, // 0.81581, 0.57831 + 0x3fea22693d62ccb9, 0x3fe2774a0a961612, // 0.8167, 0.57706 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea30e1fa4cbf81, 0x3fe262bdb7b795a2, // 0.81847, 0.57455 + 0x3fea38184a593bc6, 0x3fe258734cbb7110, // 0.81935, 0.5733 + 0x3fea3f4a8f4ee2d2, 0x3fe24e260d7ee7c9, // 0.82023, 0.57204 + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078 + 0x3fea4da2f385e997, 0x3fe23983189fdfd5, // 0.82198, 0.56952 + 0x3fea54c91090f524, 0x3fe22f2d662c13e1, // 0.82285, 0.56826 + 0x3fea5beb1e188375, 0x3fe224d4e5d5482e, // 0.82372, 0.567 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea6a230637623b, 0x3fe2101b81e0da78, // 0.82546, 0.56447 + 0x3fea7138de9d60f5, 0x3fe205baa17560d6, // 0.82632, 0.5632 + 0x3fea784aa31d3f55, 0x3fe1fb56f98b37b8, // 0.82718, 0.56193 + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066 + 0x3fea8661ec0ee133, 0x3fe1e68759a3e074, // 0.8289, 0.55939 + 0x3fea8d676e545ad2, 0x3fe1dc1b64dc4872, // 0.82976, 0.55812 + 0x3fea9468d85b20ae, 0x3fe1d1acaf012cc2, // 0.83062, 0.55685 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3feaa25f5f5aee60, 0x3fe1bcc706804467, // 0.83232, 0.55429 + 0x3feaa9547a2cb98e, 0x3fe1b250171373be, // 0.83317, 0.55302 + 0x3feab045787157ff, 0x3fe1a7d66d0516e6, // 0.83402, 0.55174 + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046 + 0x3feabe1b1b0b8dac, 0x3fe192daef7a5386, // 0.83571, 0.54918 + 0x3feac4ffbd3efac8, 0x3fe188591f3a46e5, // 0.83655, 0.54789 + 0x3feacbe03ea0e73b, 0x3fe17dd49ad16161, // 0.83739, 0.54661 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3fead994dab2e979, 0x3fe168c37c025764, // 0.83906, 0.54404 + 0x3feae068f345ecef, 0x3fe15e36e4dbe2bc, // 0.83989, 0.54275 + 0x3feae738e6cd4b67, 0x3fe153a7a00bf453, // 0.84073, 0.54146 + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017 + 0x3feaf4cc5a85fb73, 0x3fe13e8113f396c1, // 0.84238, 0.53888 + 0x3feafb8fd89f57b6, 0x3fe133e9cfee254e, // 0.84321, 0.53759 + 0x3feb024f2d7d24a9, 0x3fe1294fe4c5350a, // 0.84403, 0.53629 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feb0fc1575d33db, 0x3fe114141f935545, // 0.84567, 0.5337 + 0x3feb16742a4ca2f5, 0x3fe1097248d0a956, // 0.84649, 0.5324 + 0x3feb1d22cfdadcc6, 0x3fe0fecdd1770537, // 0.84731, 0.5311 + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298 + 0x3feb2a738eb51f33, 0x3fe0e97d078fd23b, // 0.84893, 0.5285 + 0x3feb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // 0.84974, 0.5272 + 0x3feb37b38bb54c09, 0x3fe0d421cf03c12b, // 0.85055, 0.5259 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb44e2beaf0a61, 0x3fe0bebc34ff4646, // 0.85216, 0.52328 + 0x3feb4b7409de7925, 0x3fe0b405878f85ec, // 0.85296, 0.52198 + 0x3feb52011f805c92, 0x3fe0a94c46b53d0b, // 0.85376, 0.52067 + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936 + 0x3feb5f0ea611a532, 0x3fe093d2115ee018, // 0.85535, 0.51804 + 0x3feb658f14fdbc47, 0x3fe089112032b08c, // 0.85615, 0.51673 + 0x3feb6c0b4a55ac17, 0x3fe07e4da23bc102, // 0.85694, 0.51542 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb78f70449a34b, 0x3fe068bf0691c028, // 0.85852, 0.51279 + 0x3feb7f6686e792ea, 0x3fe05df3ec31b8b6, // 0.8593, 0.51147 + 0x3feb85d1cbf52c02, 0x3fe053264bad0483, // 0.86009, 0.51015 + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883 + 0x3feb929b996a5b7f, 0x3fe03d837edff370, // 0.86165, 0.50751 + 0x3feb98fa1fd9155e, 0x3fe032ae55edbd95, // 0.86242, 0.50619 + 0x3feb9f5464c5bffc, 0x3fe027d6ad83287e, // 0.8632, 0.50486 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3febabfc262e6586, 0x3fe0121fe4f56d2c, // 0.86474, 0.50221 + 0x3febb249a0b6c40d, 0x3fe00740c82b82e0, // 0.86551, 0.50089 + 0x3febb892d5d5dad5, 0x3fdff8be6537615e, // 0.86628, 0.49956 + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823 + 0x3febc5186bf8361d, 0x3fdfcd2947c1ff57, // 0.86781, 0.4969 + 0x3febcb54cb0d2327, 0x3fdfb7575c24d2de, // 0.86857, 0.49557 + 0x3febd18ce0dc19d6, 0x3fdfa1808c6cf7e0, // 0.86933, 0.49423 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3febddf02cd2b983, 0x3fdf75c44e26a852, // 0.87084, 0.49156 + 0x3febe41b611154c1, 0x3fdf5fdee656cda3, // 0.8716, 0.49023 + 0x3febea424837de6d, 0x3fdf49f4a7e97729, // 0.87235, 0.48889 + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755 + 0x3febf6832b71ec5b, 0x3fdf1e11b4bbc35c, // 0.87384, 0.48621 + 0x3febfc9d25a1b147, 0x3fdf081906bff7fd, // 0.87459, 0.48487 + 0x3fec02b2cef1e641, 0x3fdef21b8fafd3b5, // 0.87533, 0.48353 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3fec0ed12b3372e9, 0x3fdec61253e3c61b, // 0.87681, 0.48084 + 0x3fec14d9dc465e58, 0x3fdeb00695f25620, // 0.87755, 0.47949 + 0x3fec1ade38bce19b, 0x3fde99f61c817eda, // 0.87828, 0.47815 + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768 + 0x3fec26d9f01f2eaf, 0x3fde6dc704be97e2, // 0.87974, 0.47545 + 0x3fec2cd14931e3f1, 0x3fde57a86d3cd824, // 0.88047, 0.4741 + 0x3fec32c449f60831, 0x3fde418527dc4ffa, // 0.8812, 0.47275 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec3e9d3ee7d262, 0x3fde1530a12779f4, // 0.88264, 0.47004 + 0x3fec44833141c004, 0x3fddfeff66a941de, // 0.88336, 0.46869 + 0x3fec4a64c7a5ac4c, 0x3fdde8c98bf86bd6, // 0.88408, 0.46733 + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598 + 0x3fec561adceb743e, 0x3fddbc5003b2edf8, // 0.88551, 0.46462 + 0x3fec5bef59fef85a, 0x3fdda60c5cfa10d8, // 0.88622, 0.46326 + 0x3fec61bf777fcc48, 0x3fdd8fc423c62a25, // 0.88693, 0.4619 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec6d5290341eb2, 0x3fdd632607ac9aa9, // 0.88835, 0.45918 + 0x3fec7315899eaad7, 0x3fdd4cd02ba8609c, // 0.88905, 0.45781 + 0x3fec78d41fe4a267, 0x3fdd3675caebf962, // 0.88975, 0.45645 + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508 + 0x3fec84441f785f61, 0x3fdd09b389152ec1, // 0.89115, 0.45372 + 0x3fec89f587029c13, 0x3fdcf34baee1cd21, // 0.89184, 0.45235 + 0x3fec8fa287e13305, 0x3fdcdcdf5dc440ce, // 0.89253, 0.45098 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec9aef521bd480, 0x3fdcaff964a0421d, // 0.89391, 0.44824 + 0x3feca08f19b9c449, 0x3fdc997fc3865388, // 0.8946, 0.44687 + 0x3feca62a772fd919, 0x3fdc8301b95b40c2, // 0.89528, 0.4455 + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412 + 0x3fecb153f02fb87d, 0x3fdc55f877b23537, // 0.89665, 0.44275 + 0x3fecb6e20a00da99, 0x3fdc3f6d47263129, // 0.89732, 0.44137 + 0x3fecbc6bb638d10b, 0x3fdc28ddbb6cf145, // 0.898, 0.43999 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fecc771c2736c09, 0x3fdbfbb1a05e0edc, // 0.89935, 0.43724 + 0x3fecccee20c2de9f, 0x3fdbe51517ffc0d9, // 0.90002, 0.43586 + 0x3fecd2660e12c1e6, 0x3fdbce744262deee, // 0.90068, 0.43448 + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309 + 0x3fecdd489254fe65, 0x3fdba125bd63583e, // 0.90201, 0.43171 + 0x3fece2b32799a060, 0x3fdb8a7814fd5693, // 0.90267, 0.43033 + 0x3fece819488344ce, 0x3fdb73c62d520624, // 0.90333, 0.42894 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fecf2d829f1b40e, 0x3fdb4655ae2bf757, // 0.90464, 0.42617 + 0x3fecf830e8ce467b, 0x3fdb2f971db31972, // 0.9053, 0.42478 + 0x3fecfd852fff6ad4, 0x3fdb18d45bf8aca6, // 0.90595, 0.42339 + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422 + 0x3fed082054168bac, 0x3fdaeb4252ca07ab, // 0.90724, 0.42061 + 0x3fed0d672f59d2b9, 0x3fdad473125cdc08, // 0.90789, 0.41922 + 0x3fed12a98fac410c, 0x3fdabd9faebc3980, // 0.90853, 0.41782 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3fed1d20dc40c15c, 0x3fda8fec8bf5b166, // 0.90981, 0.41503 + 0x3fed2255c6e5a4e1, 0x3fda790cd3dbf31a, // 0.91044, 0.41364 + 0x3fed2786335f52fc, 0x3fda622906a70b63, // 0.91107, 0.41224 + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084 + 0x3fed31d98e9e503a, 0x3fda34553b0afee5, // 0.91234, 0.40944 + 0x3fed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // 0.91296, 0.40804 + 0x3fed3c1ae79f2b4e, 0x3fda067145664d57, // 0.91359, 0.40664 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed464a380e7242, 0x3fd9d87d4207b0ab, // 0.91483, 0.40384 + 0x3fed4b5b1b187524, 0x3fd9c17d440df9f2, // 0.91545, 0.40243 + 0x3fed506779a3d2d9, 0x3fd9aa794d47c9ee, // 0.91606, 0.40103 + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962 + 0x3fed5a72a6221e73, 0x3fd97c6583890fc2, // 0.91729, 0.39822 + 0x3fed5f7172888a7f, 0x3fd96555b7ab948f, // 0.9179, 0.39681 + 0x3fed646bb7574de5, 0x3fd94e420137bce3, // 0.91851, 0.3954 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed6e52a71c8547, 0x3fd9200ee2c9be97, // 0.91972, 0.39258 + 0x3fed733f508c0dff, 0x3fd908ef81ef7bd1, // 0.92032, 0.39117 + 0x3fed78276f5617c6, 0x3fd8f1cc44bea329, // 0.92092, 0.38976 + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835 + 0x3fed81ea09f38b63, 0x3fd8c37a439f884f, // 0.92211, 0.38693 + 0x3fed86c48445a450, 0x3fd8ac4b86d5ed44, // 0.9227, 0.38552 + 0x3fed8b9a70ef9cb4, 0x3fd89518fbff098e, // 0.92329, 0.3841 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed95389e50429b, 0x3fd866a88a792ea0, // 0.92447, 0.38127 + 0x3fed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // 0.92505, 0.37985 + 0x3fed9ec48c26b1f3, 0x3fd838290bb359c8, // 0.92563, 0.37843 + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701 + 0x3feda83e348f613b, 0x3fd8099a9c5c362d, // 0.92679, 0.37559 + 0x3fedacf42ce68ab9, 0x3fd7f24dd37341e3, // 0.92736, 0.37416 + 0x3fedb1a591b20c38, 0x3fd7dafd592ba621, // 0.92794, 0.37274 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3fedbafa9dc1b78d, 0x3fd7ac515ee2b172, // 0.92907, 0.36989 + 0x3fedbf9e4395759a, 0x3fd794f5e613dfae, // 0.92964, 0.36847 + 0x3fedc43d52fcb453, 0x3fd77d96ca4b73a6, // 0.93021, 0.36704 + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561 + 0x3fedcd6dabaca3a5, 0x3fd74ecdb8390a3e, // 0.93133, 0.36418 + 0x3fedd1fef38a915a, 0x3fd73763c9261092, // 0.93188, 0.36276 + 0x3fedd68ba2267a25, 0x3fd71ff6458782ec, // 0.93244, 0.36133 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3feddf9730ca837b, 0x3fd6f1108f1bc9c5, // 0.93354, 0.35846 + 0x3fede4160f6d8d81, 0x3fd6d998638a0cb5, // 0.93409, 0.35703 + 0x3fede890520465ce, 0x3fd6c21cb1e39771, // 0.93464, 0.3556 + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416 + 0x3fedf177004b2534, 0x3fd6931acad55f51, // 0.93573, 0.35273 + 0x3fedf5e36a9ba59c, 0x3fd67b949cad63ca, // 0.93627, 0.35129 + 0x3fedfa4b3621271d, 0x3fd6640af6f03d9e, // 0.9368, 0.34986 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3fee030cee1435b8, 0x3fd634ed533be58e, // 0.93787, 0.34698 + 0x3fee0766d9280f54, 0x3fd61d595c88c203, // 0.9384, 0.34554 + 0x3fee0bbc22bd8349, 0x3fd605c1fcc88f63, // 0.93893, 0.3441 + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266 + 0x3fee1458cec1ad83, 0x3fd5d68910aee686, // 0.93998, 0.34122 + 0x3fee18a02fdc66d9, 0x3fd5bee78b9db3b6, // 0.94051, 0.33978 + 0x3fee1ce2ecd0c0d8, 0x3fd5a742ac0ff78d, // 0.94103, 0.33833 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee255a77a63bb8, 0x3fd577eeec151e47, // 0.94206, 0.33545 + 0x3fee298f4439197a, 0x3fd5604012f467b4, // 0.94257, 0.334 + 0x3fee2dbf6a0911d9, 0x3fd5488dedeff3be, // 0.94308, 0.33255 + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111 + 0x3fee3611becbaf69, 0x3fd5191fceda3c35, // 0.9441, 0.32966 + 0x3fee3a33ec75ce85, 0x3fd50163dc197047, // 0.9446, 0.32821 + 0x3fee3e5170cbfc46, 0x3fd4e9a4ac15d520, // 0.94511, 0.32676 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee467e7af35f23, 0x3fd4ba1ca2eca31c, // 0.94611, 0.32386 + 0x3fee4a8dff81ce5e, 0x3fd4a253d11b82f3, // 0.9466, 0.32241 + 0x3fee4e98d836c0af, 0x3fd48a87d0b07fd7, // 0.94709, 0.32096 + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195 + 0x3fee56a083968eb1, 0x3fd45ae652bb2800, // 0.94807, 0.31805 + 0x3fee5a9d550467d3, 0x3fd44310dc8936f0, // 0.94856, 0.31659 + 0x3fee5e95781ebf1c, 0x3fd42b38466e2928, // 0.94905, 0.31514 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee6677b0e6d31e, 0x3fd3fb7dc932cfa4, // 0.95001, 0.31222 + 0x3fee6a61c55d53a7, 0x3fd3e39be96ec271, // 0.95049, 0.31077 + 0x3fee6e472911da27, 0x3fd3cbb6f87a146e, // 0.95096, 0.30931 + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785 + 0x3fee7603dbce74e9, 0x3fd39be3f1bc8aef, // 0.95191, 0.30639 + 0x3fee79db29a5165a, 0x3fd383f5e353b6aa, // 0.95238, 0.30493 + 0x3fee7dadc456d850, 0x3fd36c04d27a4edf, // 0.95284, 0.30347 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee8544ddf0d075, 0x3fd33c19b83af207, // 0.95377, 0.30054 + 0x3fee89095bad6025, 0x3fd3241fb638baaf, // 0.95423, 0.29908 + 0x3fee8cc923edc388, 0x3fd30c22c08d6a13, // 0.95469, 0.29762 + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615 + 0x3fee943a91aab4b4, 0x3fd2dc200907fe51, // 0.95559, 0.29469 + 0x3fee97ec36016b30, 0x3fd2c41a4e954520, // 0.95605, 0.29322 + 0x3fee9b99229046f8, 0x3fd2ac11af483572, // 0.95649, 0.29175 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3feea2e4d212c000, 0x3fd27bf7d0f2c346, // 0.95738, 0.28882 + 0x3feea68393e65800, 0x3fd263e6995554ba, // 0.95783, 0.28735 + 0x3feeaa1d9bb20af3, 0x3fd24bd28bb37672, // 0.95827, 0.28588 + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441 + 0x3feeb1437af9bb34, 0x3fd21ba1fd3d2623, // 0.95914, 0.28294 + 0x3feeb4cf515b8811, 0x3fd2038583d727bd, // 0.95957, 0.28146 + 0x3feeb8566b810f2a, 0x3fd1eb6643499fbb, // 0.96, 0.27999 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3feebf5668eaf2ef, 0x3fd1bb1f7b999480, // 0.96086, 0.27705 + 0x3feec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // 0.96128, 0.27557 + 0x3feec6436ee60309, 0x3fd18acdc3f4873a, // 0.9617, 0.2741 + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262 + 0x3feecd1d792c8f10, 0x3fd15a713a28b9d9, // 0.96254, 0.27115 + 0x3feed0835e999009, 0x3fd1423eefc69378, // 0.96295, 0.26967 + 0x3feed3e483849c51, 0x3fd12a09fc0b1b12, // 0.96337, 0.26819 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feeda9889bfe86a, 0x3fd0f998277733f7, // 0.96418, 0.26523 + 0x3feeddeb6a078651, 0x3fd0e15b4e1749cd, // 0.96459, 0.26375 + 0x3feee13987bbebdc, 0x3fd0c91bda4f158d, // 0.96499, 0.26227 + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079 + 0x3feee7c77961dc9e, 0x3fd09895327b465e, // 0.96579, 0.25931 + 0x3feeeb074c50a544, 0x3fd0804e05eb661e, // 0.96619, 0.25783 + 0x3feeee425aa6b09a, 0x3fd068044deab002, // 0.96658, 0.25635 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feef4aa278b2032, 0x3fd037694a928cac, // 0.96737, 0.25338 + 0x3feef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // 0.96775, 0.2519 + 0x3feefafedc1ba8b7, 0x3fd006c4466e54af, // 0.96814, 0.25041 + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893 + 0x3fef014074708ed3, 0x3fcfac2abeff57ff, // 0.9689, 0.24744 + 0x3fef045a14cf738c, 0x3fcf7b7480bd3801, // 0.96928, 0.24596 + 0x3fef076eecade0fa, 0x3fcf4ab9679c9f5c, // 0.96966, 0.24447 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3fef0d8a410379c5, 0x3fcee934c2d006c7, // 0.9704, 0.24149 + 0x3fef1090bc898f5f, 0x3fceb86b462de348, // 0.97077, 0.24 + 0x3fef13926dad024e, 0x3fce879d0cc0fdaf, // 0.97114, 0.23851 + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702 + 0x3fef19876ef1f486, 0x3fce25f281a2b684, // 0.97187, 0.23553 + 0x3fef1c7abe284708, 0x3fcdf5163f01099a, // 0.97223, 0.23404 + 0x3fef1f6941259d7a, 0x3fcdc4355db40195, // 0.97258, 0.23255 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef2537e0a71f9f, 0x3fcd6265dd3f27e3, // 0.97329, 0.22957 + 0x3fef2817fc4609ce, 0x3fcd31774d2cbdee, // 0.97364, 0.22807 + 0x3fef2af349e17507, 0x3fcd00843c99c5f9, // 0.97399, 0.22658 + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508 + 0x3fef309b794b719f, 0x3fcc9e90b824a6a9, // 0.97468, 0.22359 + 0x3fef33685a3aaef0, 0x3fcc6d90535d74dc, // 0.97503, 0.22209 + 0x3fef36306b67c556, 0x3fcc3c8b8c4b9dd7, // 0.97536, 0.2206 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef3bb21cc4fe47, 0x3fcbda74f5856330, // 0.97604, 0.2176 + 0x3fef3e6bbc1bbc65, 0x3fcba96334f15dad, // 0.97637, 0.21611 + 0x3fef412089fd8adc, 0x3fcb784d30536cda, // 0.9767, 0.21461 + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311 + 0x3fef467bafb7bbe0, 0x3fcb16147941ca2a, // 0.97735, 0.21161 + 0x3fef492206bcabb4, 0x3fcae4f1d5f3b9ab, // 0.97768, 0.21011 + 0x3fef4bc38aa5c694, 0x3fcab3cb0ce6fe44, // 0.978, 0.20861 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef50f81785c6b9, 0x3fca517127e3dabc, // 0.97863, 0.20561 + 0x3fef538b1faf2d07, 0x3fca203e1b1831da, // 0.97895, 0.20411 + 0x3fef56195321c090, 0x3fc9ef0706e35a35, // 0.97926, 0.20261 + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011 + 0x3fef5b273a4fa2d9, 0x3fc98c8ce69a7aec, // 0.97988, 0.1996 + 0x3fef5da6ed43685d, 0x3fc95b49e9b62af9, // 0.98018, 0.1981 + 0x3fef6021c9f148c2, 0x3fc92a0303c8194f, // 0.98048, 0.19659 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef6508fef47bd5, 0x3fc8c7699b34ca7e, // 0.98108, 0.19359 + 0x3fef677556883cee, 0x3fc8961727c41804, // 0.98138, 0.19208 + 0x3fef69dcd652f5de, 0x3fc864c0e9b2b6cf, // 0.98167, 0.19057 + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907 + 0x3fef6e9d4d1262ca, 0x3fc802092c1d744b, // 0.98225, 0.18756 + 0x3fef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // 0.98254, 0.18606 + 0x3fef734a60446279, 0x3fc79f429f59e11d, // 0.98282, 0.18455 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef77e40d068a90, 0x3fc73c6d8055fe0a, // 0.98339, 0.18153 + 0x3fef7a299c1a322a, 0x3fc70afd8d08c4ff, // 0.98366, 0.18002 + 0x3fef7c6a50826840, 0x3fc6d98a0c08c8da, // 0.98394, 0.17851 + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177 + 0x3fef80dd27ed8204, 0x3fc676987f7216b8, // 0.98448, 0.17549 + 0x3fef830f4a40c60c, 0x3fc6451a831d830d, // 0.98475, 0.17398 + 0x3fef853c9089595e, 0x3fc61399179a6e94, // 0.98501, 0.17247 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef898887a36c84, 0x3fc5b08c1192e381, // 0.98554, 0.16945 + 0x3fef8ba737cb4b78, 0x3fc57f008654cbde, // 0.9858, 0.16794 + 0x3fef8dc10a95380d, 0x3fc54d71aa74ef02, // 0.98605, 0.16643 + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491 + 0x3fef91e616c43891, 0x3fc4ea4a1f624b61, // 0.98656, 0.1634 + 0x3fef93f14f85ac08, 0x3fc4b8b17f79fa88, // 0.98681, 0.16189 + 0x3fef95f7a9a1ec47, 0x3fc48715ad84cdf5, // 0.98706, 0.16037 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef99f5c0abd496, 0x3fc423d4920e4166, // 0.98754, 0.15734 + 0x3fef9bed7cfbde29, 0x3fc3f22f57db4893, // 0.98778, 0.15583 + 0x3fef9de0596b77a3, 0x3fc3c0870a383ff6, // 0.98802, 0.15431 + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528 + 0x3fefa1b7717661d5, 0x3fc35d2d53440db2, // 0.98849, 0.15128 + 0x3fefa39bac7a1791, 0x3fc32b7bf94516a7, // 0.98872, 0.14976 + 0x3fefa57b066e2754, 0x3fc2f9c7aa7a72af, // 0.98895, 0.14825 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fefa92b1600657c, 0x3fc296564d2b953e, // 0.9894, 0.14521 + 0x3fefaafbcb0cfddc, 0x3fc264994dfd340a, // 0.98962, 0.1437 + 0x3fefacc79de6c44f, 0x3fc232d978aed413, // 0.98984, 0.14218 + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066 + 0x3fefb0509be6f7db, 0x3fc1cf516a62a077, // 0.99027, 0.13914 + 0x3fefb20dc681d54d, 0x3fc19d8940be24e7, // 0.99049, 0.13762 + 0x3fefb3c60dd2c199, 0x3fc16bbe5fac5865, // 0.9907, 0.1361 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefb727f187f1c7, 0x3fc1082095f820b0, // 0.99111, 0.13306 + 0x3fefb8d18d66adb7, 0x3fc0d64dbcb26786, // 0.99131, 0.13154 + 0x3fefba7644f068b5, 0x3fc0a4784ab8bf1d, // 0.99151, 0.13002 + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285 + 0x3fefbdb106021816, 0x3fc040c5bb67747e, // 0.99191, 0.12698 + 0x3fefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // 0.9921, 0.12545 + 0x3fefc0d832bf043a, 0x3fbfba124b07ad85, // 0.99229, 0.12393 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefc3ebc935454c, 0x3fbef2858d27561b, // 0.99267, 0.12089 + 0x3fefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // 0.99285, 0.11937 + 0x3fefc6ebc77f0887, 0x3fbe2ae5b8457f77, // 0.99303, 0.11784 + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632 + 0x3fefc9d82bc2915e, 0x3fbd633347858ce4, // 0.99339, 0.11479 + 0x3fefcb4703914354, 0x3fbcff533b307dc1, // 0.99356, 0.11327 + 0x3fefccb0f4323aa3, 0x3fbc9b6eb6165c42, // 0.99374, 0.11175 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefcf761f0c77a3, 0x3fbbd3987f31fa0e, // 0.99407, 0.1087 + 0x3fefd0d158d86087, 0x3fbb6fa6ec38f64c, // 0.99424, 0.10717 + 0x3fefd227aa9bd53b, 0x3fbb0bb11e1d5559, // 0.9944, 0.10565 + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412 + 0x3fefd4c59536fae4, 0x3fba43b90e27f3c4, // 0.99472, 0.1026 + 0x3fefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // 0.99488, 0.10107 + 0x3fefd74fdd40abbf, 0x3fb97bb0caaba56f, // 0.99503, 0.099544 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefd9c68127c78c, 0x3fb8b398cf0c38e0, // 0.99533, 0.09649 + 0x3fefdafa7514538c, 0x3fb84f8712c130a0, // 0.99548, 0.094963 + 0x3fefdc297f674ba9, 0x3fb7eb7196b72ee4, // 0.99563, 0.093436 + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909 + 0x3fefde78d68653fd, 0x3fb7233b9d236e71, // 0.99591, 0.090381 + 0x3fefdf9922f73307, 0x3fb6bf1b3e79b129, // 0.99604, 0.088854 + 0x3fefe0b485181be3, 0x3fb65af75dd0f87b, // 0.99618, 0.087326 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefe2dc89bbff08, 0x3fb592a554489bc8, // 0.99644, 0.084269 + 0x3fefe3e92be9d886, 0x3fb52e774a4d4d0a, // 0.99657, 0.08274 + 0x3fefe4f0e31d7a4a, 0x3fb4ca45fc1ba8b6, // 0.9967, 0.081211 + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682 + 0x3fefe6f18ff42c84, 0x3fb401d9d0e3a507, // 0.99694, 0.078153 + 0x3fefe7ea85482d60, 0x3fb39d9f12c5a299, // 0.99706, 0.076624 + 0x3fefe8de8f03d75c, 0x3fb339614e41ffa5, // 0.99718, 0.075094 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefeab7df1c6005, 0x3fb270dcefdfc45b, // 0.9974, 0.072035 + 0x3fefeb9d2530410f, 0x3fb20c9674ed444c, // 0.99751, 0.070505 + 0x3fefec7d7f19cffc, 0x3fb1a84d316d4f8a, // 0.99762, 0.068974 + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444 + 0x3fefee2f6de455ba, 0x3fb0dfb28ea201e6, // 0.99783, 0.065913 + 0x3fefef0102826191, 0x3fb07b614e463064, // 0.99793, 0.064383 + 0x3fefefcdaa704562, 0x3fb0170d833bf421, // 0.99802, 0.062852 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3feff15833be1965, 0x3fae9cbd15ff5527, // 0.99821, 0.05979 + 0x3feff21614e131ed, 0x3fadd406f9808ec8, // 0.9983, 0.058258 + 0x3feff2cf08da7321, 0x3fad0b4c436f91d0, // 0.99839, 0.056727 + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195 + 0x3feff43228de1b77, 0x3fab79c986698b78, // 0.99856, 0.053664 + 0x3feff4dc54b1bed3, 0x3faab101bd5f8317, // 0.99864, 0.052132 + 0x3feff58192ee0358, 0x3fa9e835d6993c87, // 0.99872, 0.0506 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff6bd463b444d, 0x3fa856922bb513c1, // 0.99887, 0.047535 + 0x3feff753bb1b9164, 0x3fa78dbaa5874685, // 0.99894, 0.046003 + 0x3feff7e5420320f9, 0x3fa6c4df7d7d5b84, // 0.99901, 0.044471 + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938 + 0x3feff8f9858f058b, 0x3fa5331ec3bba0eb, // 0.99914, 0.041406 + 0x3feff97c4208c014, 0x3fa46a396ff86179, // 0.9992, 0.039873 + 0x3feff9fa10348837, 0x3fa3a150f6421afc, // 0.99926, 0.03834 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feffae6e1556998, 0x3fa20f770ceb11c6, // 0.99938, 0.035274 + 0x3feffb55e425fdae, 0x3fa14685db42c17e, // 0.99943, 0.033741 + 0x3feffbbff85f9515, 0x3fa07d91ff984580, // 0.99948, 0.032208 + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675 + 0x3feffc8554cd213a, 0x3f9dd7458c64ab39, // 0.99958, 0.029142 + 0x3feffce09ce2a679, 0x3f9c454f4ce53b1c, // 0.99962, 0.027608 + 0x3feffd36f624500c, 0x3f9ab354b1504fca, // 0.99966, 0.026075 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffdd4dbf78f52, 0x3f978f535ddc9f03, // 0.99974, 0.023008 + 0x3feffe1c6870cb77, 0x3f95fd4d21fab226, // 0.99977, 0.021474 + 0x3feffe5f05e578db, 0x3f946b4381fce81c, // 0.9998, 0.01994 + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407 + 0x3feffed57398d2b7, 0x3f9147270dad7132, // 0.99986, 0.016873 + 0x3fefff0943c53bd1, 0x3f8f6a296ab997ca, // 0.99988, 0.015339 + 0x3fefff3824c88f6f, 0x3f8c45ffe1e48ad9, // 0.9999, 0.013805 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3fefff871937ce2f, 0x3f85fda037ac05e0, // 0.99994, 0.010738 + 0x3fefffa72c978c4f, 0x3f82d96b0e509703, // 0.99996, 0.0092038 + 0x3fefffc250b5daef, 0x3f7f6a65f9a2a3c5, // 0.99997, 0.0076698 + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359 + 0x3fefffe9cb1e2e8d, 0x3f72d97822f996bc, // 0.99999, 0.0046019 + 0x3feffff621621d02, 0x3f6921f8becca4ba, // 1, 0.003068 + 0x3feffffd88586ee6, 0x3f5921faaee6472d, // 1, 0.001534 + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffffd88586ee6, 0xbf5921faaee6472d, // 1, -0.001534 + 0x3feffff621621d02, 0xbf6921f8becca4ba, // 1, -0.003068 + 0x3fefffe9cb1e2e8d, 0xbf72d97822f996bc, // 0.99999,-0.0046019 + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359 + 0x3fefffc250b5daef, 0xbf7f6a65f9a2a3c5, // 0.99997,-0.0076698 + 0x3fefffa72c978c4f, 0xbf82d96b0e509703, // 0.99996,-0.0092038 + 0x3fefff871937ce2f, 0xbf85fda037ac05e0, // 0.99994, -0.010738 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272 + 0x3fefff3824c88f6f, 0xbf8c45ffe1e48ad9, // 0.9999, -0.013805 + 0x3fefff0943c53bd1, 0xbf8f6a296ab997ca, // 0.99988, -0.015339 + 0x3feffed57398d2b7, 0xbf9147270dad7132, // 0.99986, -0.016873 + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407 + 0x3feffe5f05e578db, 0xbf946b4381fce81c, // 0.9998, -0.01994 + 0x3feffe1c6870cb77, 0xbf95fd4d21fab226, // 0.99977, -0.021474 + 0x3feffdd4dbf78f52, 0xbf978f535ddc9f03, // 0.99974, -0.023008 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541 + 0x3feffd36f624500c, 0xbf9ab354b1504fca, // 0.99966, -0.026075 + 0x3feffce09ce2a679, 0xbf9c454f4ce53b1c, // 0.99962, -0.027608 + 0x3feffc8554cd213a, 0xbf9dd7458c64ab39, // 0.99958, -0.029142 + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675 + 0x3feffbbff85f9515, 0xbfa07d91ff984580, // 0.99948, -0.032208 + 0x3feffb55e425fdae, 0xbfa14685db42c17e, // 0.99943, -0.033741 + 0x3feffae6e1556998, 0xbfa20f770ceb11c6, // 0.99938, -0.035274 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807 + 0x3feff9fa10348837, 0xbfa3a150f6421afc, // 0.99926, -0.03834 + 0x3feff97c4208c014, 0xbfa46a396ff86179, // 0.9992, -0.039873 + 0x3feff8f9858f058b, 0xbfa5331ec3bba0eb, // 0.99914, -0.041406 + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938 + 0x3feff7e5420320f9, 0xbfa6c4df7d7d5b84, // 0.99901, -0.044471 + 0x3feff753bb1b9164, 0xbfa78dbaa5874685, // 0.99894, -0.046003 + 0x3feff6bd463b444d, 0xbfa856922bb513c1, // 0.99887, -0.047535 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068 + 0x3feff58192ee0358, 0xbfa9e835d6993c87, // 0.99872, -0.0506 + 0x3feff4dc54b1bed3, 0xbfaab101bd5f8317, // 0.99864, -0.052132 + 0x3feff43228de1b77, 0xbfab79c986698b78, // 0.99856, -0.053664 + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195 + 0x3feff2cf08da7321, 0xbfad0b4c436f91d0, // 0.99839, -0.056727 + 0x3feff21614e131ed, 0xbfadd406f9808ec8, // 0.9983, -0.058258 + 0x3feff15833be1965, 0xbfae9cbd15ff5527, // 0.99821, -0.05979 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321 + 0x3fefefcdaa704562, 0xbfb0170d833bf421, // 0.99802, -0.062852 + 0x3fefef0102826191, 0xbfb07b614e463064, // 0.99793, -0.064383 + 0x3fefee2f6de455ba, 0xbfb0dfb28ea201e6, // 0.99783, -0.065913 + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444 + 0x3fefec7d7f19cffc, 0xbfb1a84d316d4f8a, // 0.99762, -0.068974 + 0x3fefeb9d2530410f, 0xbfb20c9674ed444c, // 0.99751, -0.070505 + 0x3fefeab7df1c6005, 0xbfb270dcefdfc45b, // 0.9974, -0.072035 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565 + 0x3fefe8de8f03d75c, 0xbfb339614e41ffa5, // 0.99718, -0.075094 + 0x3fefe7ea85482d60, 0xbfb39d9f12c5a299, // 0.99706, -0.076624 + 0x3fefe6f18ff42c84, 0xbfb401d9d0e3a507, // 0.99694, -0.078153 + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682 + 0x3fefe4f0e31d7a4a, 0xbfb4ca45fc1ba8b6, // 0.9967, -0.081211 + 0x3fefe3e92be9d886, 0xbfb52e774a4d4d0a, // 0.99657, -0.08274 + 0x3fefe2dc89bbff08, 0xbfb592a554489bc8, // 0.99644, -0.084269 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797 + 0x3fefe0b485181be3, 0xbfb65af75dd0f87b, // 0.99618, -0.087326 + 0x3fefdf9922f73307, 0xbfb6bf1b3e79b129, // 0.99604, -0.088854 + 0x3fefde78d68653fd, 0xbfb7233b9d236e71, // 0.99591, -0.090381 + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909 + 0x3fefdc297f674ba9, 0xbfb7eb7196b72ee4, // 0.99563, -0.093436 + 0x3fefdafa7514538c, 0xbfb84f8712c130a0, // 0.99548, -0.094963 + 0x3fefd9c68127c78c, 0xbfb8b398cf0c38e0, // 0.99533, -0.09649 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017 + 0x3fefd74fdd40abbf, 0xbfb97bb0caaba56f, // 0.99503, -0.099544 + 0x3fefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // 0.99488, -0.10107 + 0x3fefd4c59536fae4, 0xbfba43b90e27f3c4, // 0.99472, -0.1026 + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412 + 0x3fefd227aa9bd53b, 0xbfbb0bb11e1d5559, // 0.9944, -0.10565 + 0x3fefd0d158d86087, 0xbfbb6fa6ec38f64c, // 0.99424, -0.10717 + 0x3fefcf761f0c77a3, 0xbfbbd3987f31fa0e, // 0.99407, -0.1087 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefccb0f4323aa3, 0xbfbc9b6eb6165c42, // 0.99374, -0.11175 + 0x3fefcb4703914354, 0xbfbcff533b307dc1, // 0.99356, -0.11327 + 0x3fefc9d82bc2915e, 0xbfbd633347858ce4, // 0.99339, -0.11479 + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632 + 0x3fefc6ebc77f0887, 0xbfbe2ae5b8457f77, // 0.99303, -0.11784 + 0x3fefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // 0.99285, -0.11937 + 0x3fefc3ebc935454c, 0xbfbef2858d27561b, // 0.99267, -0.12089 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefc0d832bf043a, 0xbfbfba124b07ad85, // 0.99229, -0.12393 + 0x3fefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // 0.9921, -0.12545 + 0x3fefbdb106021816, 0xbfc040c5bb67747e, // 0.99191, -0.12698 + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285 + 0x3fefba7644f068b5, 0xbfc0a4784ab8bf1d, // 0.99151, -0.13002 + 0x3fefb8d18d66adb7, 0xbfc0d64dbcb26786, // 0.99131, -0.13154 + 0x3fefb727f187f1c7, 0xbfc1082095f820b0, // 0.99111, -0.13306 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefb3c60dd2c199, 0xbfc16bbe5fac5865, // 0.9907, -0.1361 + 0x3fefb20dc681d54d, 0xbfc19d8940be24e7, // 0.99049, -0.13762 + 0x3fefb0509be6f7db, 0xbfc1cf516a62a077, // 0.99027, -0.13914 + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066 + 0x3fefacc79de6c44f, 0xbfc232d978aed413, // 0.98984, -0.14218 + 0x3fefaafbcb0cfddc, 0xbfc264994dfd340a, // 0.98962, -0.1437 + 0x3fefa92b1600657c, 0xbfc296564d2b953e, // 0.9894, -0.14521 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefa57b066e2754, 0xbfc2f9c7aa7a72af, // 0.98895, -0.14825 + 0x3fefa39bac7a1791, 0xbfc32b7bf94516a7, // 0.98872, -0.14976 + 0x3fefa1b7717661d5, 0xbfc35d2d53440db2, // 0.98849, -0.15128 + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528 + 0x3fef9de0596b77a3, 0xbfc3c0870a383ff6, // 0.98802, -0.15431 + 0x3fef9bed7cfbde29, 0xbfc3f22f57db4893, // 0.98778, -0.15583 + 0x3fef99f5c0abd496, 0xbfc423d4920e4166, // 0.98754, -0.15734 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fef95f7a9a1ec47, 0xbfc48715ad84cdf5, // 0.98706, -0.16037 + 0x3fef93f14f85ac08, 0xbfc4b8b17f79fa88, // 0.98681, -0.16189 + 0x3fef91e616c43891, 0xbfc4ea4a1f624b61, // 0.98656, -0.1634 + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491 + 0x3fef8dc10a95380d, 0xbfc54d71aa74ef02, // 0.98605, -0.16643 + 0x3fef8ba737cb4b78, 0xbfc57f008654cbde, // 0.9858, -0.16794 + 0x3fef898887a36c84, 0xbfc5b08c1192e381, // 0.98554, -0.16945 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef853c9089595e, 0xbfc61399179a6e94, // 0.98501, -0.17247 + 0x3fef830f4a40c60c, 0xbfc6451a831d830d, // 0.98475, -0.17398 + 0x3fef80dd27ed8204, 0xbfc676987f7216b8, // 0.98448, -0.17549 + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177 + 0x3fef7c6a50826840, 0xbfc6d98a0c08c8da, // 0.98394, -0.17851 + 0x3fef7a299c1a322a, 0xbfc70afd8d08c4ff, // 0.98366, -0.18002 + 0x3fef77e40d068a90, 0xbfc73c6d8055fe0a, // 0.98339, -0.18153 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef734a60446279, 0xbfc79f429f59e11d, // 0.98282, -0.18455 + 0x3fef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // 0.98254, -0.18606 + 0x3fef6e9d4d1262ca, 0xbfc802092c1d744b, // 0.98225, -0.18756 + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907 + 0x3fef69dcd652f5de, 0xbfc864c0e9b2b6cf, // 0.98167, -0.19057 + 0x3fef677556883cee, 0xbfc8961727c41804, // 0.98138, -0.19208 + 0x3fef6508fef47bd5, 0xbfc8c7699b34ca7e, // 0.98108, -0.19359 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef6021c9f148c2, 0xbfc92a0303c8194f, // 0.98048, -0.19659 + 0x3fef5da6ed43685d, 0xbfc95b49e9b62af9, // 0.98018, -0.1981 + 0x3fef5b273a4fa2d9, 0xbfc98c8ce69a7aec, // 0.97988, -0.1996 + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011 + 0x3fef56195321c090, 0xbfc9ef0706e35a35, // 0.97926, -0.20261 + 0x3fef538b1faf2d07, 0xbfca203e1b1831da, // 0.97895, -0.20411 + 0x3fef50f81785c6b9, 0xbfca517127e3dabc, // 0.97863, -0.20561 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef4bc38aa5c694, 0xbfcab3cb0ce6fe44, // 0.978, -0.20861 + 0x3fef492206bcabb4, 0xbfcae4f1d5f3b9ab, // 0.97768, -0.21011 + 0x3fef467bafb7bbe0, 0xbfcb16147941ca2a, // 0.97735, -0.21161 + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311 + 0x3fef412089fd8adc, 0xbfcb784d30536cda, // 0.9767, -0.21461 + 0x3fef3e6bbc1bbc65, 0xbfcba96334f15dad, // 0.97637, -0.21611 + 0x3fef3bb21cc4fe47, 0xbfcbda74f5856330, // 0.97604, -0.2176 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef36306b67c556, 0xbfcc3c8b8c4b9dd7, // 0.97536, -0.2206 + 0x3fef33685a3aaef0, 0xbfcc6d90535d74dc, // 0.97503, -0.22209 + 0x3fef309b794b719f, 0xbfcc9e90b824a6a9, // 0.97468, -0.22359 + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508 + 0x3fef2af349e17507, 0xbfcd00843c99c5f9, // 0.97399, -0.22658 + 0x3fef2817fc4609ce, 0xbfcd31774d2cbdee, // 0.97364, -0.22807 + 0x3fef2537e0a71f9f, 0xbfcd6265dd3f27e3, // 0.97329, -0.22957 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef1f6941259d7a, 0xbfcdc4355db40195, // 0.97258, -0.23255 + 0x3fef1c7abe284708, 0xbfcdf5163f01099a, // 0.97223, -0.23404 + 0x3fef19876ef1f486, 0xbfce25f281a2b684, // 0.97187, -0.23553 + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702 + 0x3fef13926dad024e, 0xbfce879d0cc0fdaf, // 0.97114, -0.23851 + 0x3fef1090bc898f5f, 0xbfceb86b462de348, // 0.97077, -0.24 + 0x3fef0d8a410379c5, 0xbfcee934c2d006c7, // 0.9704, -0.24149 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef076eecade0fa, 0xbfcf4ab9679c9f5c, // 0.96966, -0.24447 + 0x3fef045a14cf738c, 0xbfcf7b7480bd3801, // 0.96928, -0.24596 + 0x3fef014074708ed3, 0xbfcfac2abeff57ff, // 0.9689, -0.24744 + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893 + 0x3feefafedc1ba8b7, 0xbfd006c4466e54af, // 0.96814, -0.25041 + 0x3feef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // 0.96775, -0.2519 + 0x3feef4aa278b2032, 0xbfd037694a928cac, // 0.96737, -0.25338 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3feeee425aa6b09a, 0xbfd068044deab002, // 0.96658, -0.25635 + 0x3feeeb074c50a544, 0xbfd0804e05eb661e, // 0.96619, -0.25783 + 0x3feee7c77961dc9e, 0xbfd09895327b465e, // 0.96579, -0.25931 + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079 + 0x3feee13987bbebdc, 0xbfd0c91bda4f158d, // 0.96499, -0.26227 + 0x3feeddeb6a078651, 0xbfd0e15b4e1749cd, // 0.96459, -0.26375 + 0x3feeda9889bfe86a, 0xbfd0f998277733f7, // 0.96418, -0.26523 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feed3e483849c51, 0xbfd12a09fc0b1b12, // 0.96337, -0.26819 + 0x3feed0835e999009, 0xbfd1423eefc69378, // 0.96295, -0.26967 + 0x3feecd1d792c8f10, 0xbfd15a713a28b9d9, // 0.96254, -0.27115 + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262 + 0x3feec6436ee60309, 0xbfd18acdc3f4873a, // 0.9617, -0.2741 + 0x3feec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // 0.96128, -0.27557 + 0x3feebf5668eaf2ef, 0xbfd1bb1f7b999480, // 0.96086, -0.27705 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feeb8566b810f2a, 0xbfd1eb6643499fbb, // 0.96, -0.27999 + 0x3feeb4cf515b8811, 0xbfd2038583d727bd, // 0.95957, -0.28146 + 0x3feeb1437af9bb34, 0xbfd21ba1fd3d2623, // 0.95914, -0.28294 + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441 + 0x3feeaa1d9bb20af3, 0xbfd24bd28bb37672, // 0.95827, -0.28588 + 0x3feea68393e65800, 0xbfd263e6995554ba, // 0.95783, -0.28735 + 0x3feea2e4d212c000, 0xbfd27bf7d0f2c346, // 0.95738, -0.28882 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3fee9b99229046f8, 0xbfd2ac11af483572, // 0.95649, -0.29175 + 0x3fee97ec36016b30, 0xbfd2c41a4e954520, // 0.95605, -0.29322 + 0x3fee943a91aab4b4, 0xbfd2dc200907fe51, // 0.95559, -0.29469 + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615 + 0x3fee8cc923edc388, 0xbfd30c22c08d6a13, // 0.95469, -0.29762 + 0x3fee89095bad6025, 0xbfd3241fb638baaf, // 0.95423, -0.29908 + 0x3fee8544ddf0d075, 0xbfd33c19b83af207, // 0.95377, -0.30054 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee7dadc456d850, 0xbfd36c04d27a4edf, // 0.95284, -0.30347 + 0x3fee79db29a5165a, 0xbfd383f5e353b6aa, // 0.95238, -0.30493 + 0x3fee7603dbce74e9, 0xbfd39be3f1bc8aef, // 0.95191, -0.30639 + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785 + 0x3fee6e472911da27, 0xbfd3cbb6f87a146e, // 0.95096, -0.30931 + 0x3fee6a61c55d53a7, 0xbfd3e39be96ec271, // 0.95049, -0.31077 + 0x3fee6677b0e6d31e, 0xbfd3fb7dc932cfa4, // 0.95001, -0.31222 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee5e95781ebf1c, 0xbfd42b38466e2928, // 0.94905, -0.31514 + 0x3fee5a9d550467d3, 0xbfd44310dc8936f0, // 0.94856, -0.31659 + 0x3fee56a083968eb1, 0xbfd45ae652bb2800, // 0.94807, -0.31805 + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195 + 0x3fee4e98d836c0af, 0xbfd48a87d0b07fd7, // 0.94709, -0.32096 + 0x3fee4a8dff81ce5e, 0xbfd4a253d11b82f3, // 0.9466, -0.32241 + 0x3fee467e7af35f23, 0xbfd4ba1ca2eca31c, // 0.94611, -0.32386 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee3e5170cbfc46, 0xbfd4e9a4ac15d520, // 0.94511, -0.32676 + 0x3fee3a33ec75ce85, 0xbfd50163dc197047, // 0.9446, -0.32821 + 0x3fee3611becbaf69, 0xbfd5191fceda3c35, // 0.9441, -0.32966 + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111 + 0x3fee2dbf6a0911d9, 0xbfd5488dedeff3be, // 0.94308, -0.33255 + 0x3fee298f4439197a, 0xbfd5604012f467b4, // 0.94257, -0.334 + 0x3fee255a77a63bb8, 0xbfd577eeec151e47, // 0.94206, -0.33545 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee1ce2ecd0c0d8, 0xbfd5a742ac0ff78d, // 0.94103, -0.33833 + 0x3fee18a02fdc66d9, 0xbfd5bee78b9db3b6, // 0.94051, -0.33978 + 0x3fee1458cec1ad83, 0xbfd5d68910aee686, // 0.93998, -0.34122 + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266 + 0x3fee0bbc22bd8349, 0xbfd605c1fcc88f63, // 0.93893, -0.3441 + 0x3fee0766d9280f54, 0xbfd61d595c88c203, // 0.9384, -0.34554 + 0x3fee030cee1435b8, 0xbfd634ed533be58e, // 0.93787, -0.34698 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fedfa4b3621271d, 0xbfd6640af6f03d9e, // 0.9368, -0.34986 + 0x3fedf5e36a9ba59c, 0xbfd67b949cad63ca, // 0.93627, -0.35129 + 0x3fedf177004b2534, 0xbfd6931acad55f51, // 0.93573, -0.35273 + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416 + 0x3fede890520465ce, 0xbfd6c21cb1e39771, // 0.93464, -0.3556 + 0x3fede4160f6d8d81, 0xbfd6d998638a0cb5, // 0.93409, -0.35703 + 0x3feddf9730ca837b, 0xbfd6f1108f1bc9c5, // 0.93354, -0.35846 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fedd68ba2267a25, 0xbfd71ff6458782ec, // 0.93244, -0.36133 + 0x3fedd1fef38a915a, 0xbfd73763c9261092, // 0.93188, -0.36276 + 0x3fedcd6dabaca3a5, 0xbfd74ecdb8390a3e, // 0.93133, -0.36418 + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561 + 0x3fedc43d52fcb453, 0xbfd77d96ca4b73a6, // 0.93021, -0.36704 + 0x3fedbf9e4395759a, 0xbfd794f5e613dfae, // 0.92964, -0.36847 + 0x3fedbafa9dc1b78d, 0xbfd7ac515ee2b172, // 0.92907, -0.36989 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3fedb1a591b20c38, 0xbfd7dafd592ba621, // 0.92794, -0.37274 + 0x3fedacf42ce68ab9, 0xbfd7f24dd37341e3, // 0.92736, -0.37416 + 0x3feda83e348f613b, 0xbfd8099a9c5c362d, // 0.92679, -0.37559 + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701 + 0x3fed9ec48c26b1f3, 0xbfd838290bb359c8, // 0.92563, -0.37843 + 0x3fed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // 0.92505, -0.37985 + 0x3fed95389e50429b, 0xbfd866a88a792ea0, // 0.92447, -0.38127 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fed8b9a70ef9cb4, 0xbfd89518fbff098e, // 0.92329, -0.3841 + 0x3fed86c48445a450, 0xbfd8ac4b86d5ed44, // 0.9227, -0.38552 + 0x3fed81ea09f38b63, 0xbfd8c37a439f884f, // 0.92211, -0.38693 + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835 + 0x3fed78276f5617c6, 0xbfd8f1cc44bea329, // 0.92092, -0.38976 + 0x3fed733f508c0dff, 0xbfd908ef81ef7bd1, // 0.92032, -0.39117 + 0x3fed6e52a71c8547, 0xbfd9200ee2c9be97, // 0.91972, -0.39258 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed646bb7574de5, 0xbfd94e420137bce3, // 0.91851, -0.3954 + 0x3fed5f7172888a7f, 0xbfd96555b7ab948f, // 0.9179, -0.39681 + 0x3fed5a72a6221e73, 0xbfd97c6583890fc2, // 0.91729, -0.39822 + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962 + 0x3fed506779a3d2d9, 0xbfd9aa794d47c9ee, // 0.91606, -0.40103 + 0x3fed4b5b1b187524, 0xbfd9c17d440df9f2, // 0.91545, -0.40243 + 0x3fed464a380e7242, 0xbfd9d87d4207b0ab, // 0.91483, -0.40384 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed3c1ae79f2b4e, 0xbfda067145664d57, // 0.91359, -0.40664 + 0x3fed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // 0.91296, -0.40804 + 0x3fed31d98e9e503a, 0xbfda34553b0afee5, // 0.91234, -0.40944 + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084 + 0x3fed2786335f52fc, 0xbfda622906a70b63, // 0.91107, -0.41224 + 0x3fed2255c6e5a4e1, 0xbfda790cd3dbf31a, // 0.91044, -0.41364 + 0x3fed1d20dc40c15c, 0xbfda8fec8bf5b166, // 0.90981, -0.41503 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed12a98fac410c, 0xbfdabd9faebc3980, // 0.90853, -0.41782 + 0x3fed0d672f59d2b9, 0xbfdad473125cdc08, // 0.90789, -0.41922 + 0x3fed082054168bac, 0xbfdaeb4252ca07ab, // 0.90724, -0.42061 + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422 + 0x3fecfd852fff6ad4, 0xbfdb18d45bf8aca6, // 0.90595, -0.42339 + 0x3fecf830e8ce467b, 0xbfdb2f971db31972, // 0.9053, -0.42478 + 0x3fecf2d829f1b40e, 0xbfdb4655ae2bf757, // 0.90464, -0.42617 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fece819488344ce, 0xbfdb73c62d520624, // 0.90333, -0.42894 + 0x3fece2b32799a060, 0xbfdb8a7814fd5693, // 0.90267, -0.43033 + 0x3fecdd489254fe65, 0xbfdba125bd63583e, // 0.90201, -0.43171 + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309 + 0x3fecd2660e12c1e6, 0xbfdbce744262deee, // 0.90068, -0.43448 + 0x3fecccee20c2de9f, 0xbfdbe51517ffc0d9, // 0.90002, -0.43586 + 0x3fecc771c2736c09, 0xbfdbfbb1a05e0edc, // 0.89935, -0.43724 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3fecbc6bb638d10b, 0xbfdc28ddbb6cf145, // 0.898, -0.43999 + 0x3fecb6e20a00da99, 0xbfdc3f6d47263129, // 0.89732, -0.44137 + 0x3fecb153f02fb87d, 0xbfdc55f877b23537, // 0.89665, -0.44275 + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412 + 0x3feca62a772fd919, 0xbfdc8301b95b40c2, // 0.89528, -0.4455 + 0x3feca08f19b9c449, 0xbfdc997fc3865388, // 0.8946, -0.44687 + 0x3fec9aef521bd480, 0xbfdcaff964a0421d, // 0.89391, -0.44824 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fec8fa287e13305, 0xbfdcdcdf5dc440ce, // 0.89253, -0.45098 + 0x3fec89f587029c13, 0xbfdcf34baee1cd21, // 0.89184, -0.45235 + 0x3fec84441f785f61, 0xbfdd09b389152ec1, // 0.89115, -0.45372 + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508 + 0x3fec78d41fe4a267, 0xbfdd3675caebf962, // 0.88975, -0.45645 + 0x3fec7315899eaad7, 0xbfdd4cd02ba8609c, // 0.88905, -0.45781 + 0x3fec6d5290341eb2, 0xbfdd632607ac9aa9, // 0.88835, -0.45918 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec61bf777fcc48, 0xbfdd8fc423c62a25, // 0.88693, -0.4619 + 0x3fec5bef59fef85a, 0xbfdda60c5cfa10d8, // 0.88622, -0.46326 + 0x3fec561adceb743e, 0xbfddbc5003b2edf8, // 0.88551, -0.46462 + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598 + 0x3fec4a64c7a5ac4c, 0xbfdde8c98bf86bd6, // 0.88408, -0.46733 + 0x3fec44833141c004, 0xbfddfeff66a941de, // 0.88336, -0.46869 + 0x3fec3e9d3ee7d262, 0xbfde1530a12779f4, // 0.88264, -0.47004 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec32c449f60831, 0xbfde418527dc4ffa, // 0.8812, -0.47275 + 0x3fec2cd14931e3f1, 0xbfde57a86d3cd824, // 0.88047, -0.4741 + 0x3fec26d9f01f2eaf, 0xbfde6dc704be97e2, // 0.87974, -0.47545 + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768 + 0x3fec1ade38bce19b, 0xbfde99f61c817eda, // 0.87828, -0.47815 + 0x3fec14d9dc465e58, 0xbfdeb00695f25620, // 0.87755, -0.47949 + 0x3fec0ed12b3372e9, 0xbfdec61253e3c61b, // 0.87681, -0.48084 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3fec02b2cef1e641, 0xbfdef21b8fafd3b5, // 0.87533, -0.48353 + 0x3febfc9d25a1b147, 0xbfdf081906bff7fd, // 0.87459, -0.48487 + 0x3febf6832b71ec5b, 0xbfdf1e11b4bbc35c, // 0.87384, -0.48621 + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755 + 0x3febea424837de6d, 0xbfdf49f4a7e97729, // 0.87235, -0.48889 + 0x3febe41b611154c1, 0xbfdf5fdee656cda3, // 0.8716, -0.49023 + 0x3febddf02cd2b983, 0xbfdf75c44e26a852, // 0.87084, -0.49156 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3febd18ce0dc19d6, 0xbfdfa1808c6cf7e0, // 0.86933, -0.49423 + 0x3febcb54cb0d2327, 0xbfdfb7575c24d2de, // 0.86857, -0.49557 + 0x3febc5186bf8361d, 0xbfdfcd2947c1ff57, // 0.86781, -0.4969 + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823 + 0x3febb892d5d5dad5, 0xbfdff8be6537615e, // 0.86628, -0.49956 + 0x3febb249a0b6c40d, 0xbfe00740c82b82e0, // 0.86551, -0.50089 + 0x3febabfc262e6586, 0xbfe0121fe4f56d2c, // 0.86474, -0.50221 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3feb9f5464c5bffc, 0xbfe027d6ad83287e, // 0.8632, -0.50486 + 0x3feb98fa1fd9155e, 0xbfe032ae55edbd95, // 0.86242, -0.50619 + 0x3feb929b996a5b7f, 0xbfe03d837edff370, // 0.86165, -0.50751 + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883 + 0x3feb85d1cbf52c02, 0xbfe053264bad0483, // 0.86009, -0.51015 + 0x3feb7f6686e792ea, 0xbfe05df3ec31b8b6, // 0.8593, -0.51147 + 0x3feb78f70449a34b, 0xbfe068bf0691c028, // 0.85852, -0.51279 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb6c0b4a55ac17, 0xbfe07e4da23bc102, // 0.85694, -0.51542 + 0x3feb658f14fdbc47, 0xbfe089112032b08c, // 0.85615, -0.51673 + 0x3feb5f0ea611a532, 0xbfe093d2115ee018, // 0.85535, -0.51804 + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936 + 0x3feb52011f805c92, 0xbfe0a94c46b53d0b, // 0.85376, -0.52067 + 0x3feb4b7409de7925, 0xbfe0b405878f85ec, // 0.85296, -0.52198 + 0x3feb44e2beaf0a61, 0xbfe0bebc34ff4646, // 0.85216, -0.52328 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb37b38bb54c09, 0xbfe0d421cf03c12b, // 0.85055, -0.5259 + 0x3feb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // 0.84974, -0.5272 + 0x3feb2a738eb51f33, 0xbfe0e97d078fd23b, // 0.84893, -0.5285 + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298 + 0x3feb1d22cfdadcc6, 0xbfe0fecdd1770537, // 0.84731, -0.5311 + 0x3feb16742a4ca2f5, 0xbfe1097248d0a956, // 0.84649, -0.5324 + 0x3feb0fc1575d33db, 0xbfe114141f935545, // 0.84567, -0.5337 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb024f2d7d24a9, 0xbfe1294fe4c5350a, // 0.84403, -0.53629 + 0x3feafb8fd89f57b6, 0xbfe133e9cfee254e, // 0.84321, -0.53759 + 0x3feaf4cc5a85fb73, 0xbfe13e8113f396c1, // 0.84238, -0.53888 + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017 + 0x3feae738e6cd4b67, 0xbfe153a7a00bf453, // 0.84073, -0.54146 + 0x3feae068f345ecef, 0xbfe15e36e4dbe2bc, // 0.83989, -0.54275 + 0x3fead994dab2e979, 0xbfe168c37c025764, // 0.83906, -0.54404 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3feacbe03ea0e73b, 0xbfe17dd49ad16161, // 0.83739, -0.54661 + 0x3feac4ffbd3efac8, 0xbfe188591f3a46e5, // 0.83655, -0.54789 + 0x3feabe1b1b0b8dac, 0xbfe192daef7a5386, // 0.83571, -0.54918 + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046 + 0x3feab045787157ff, 0xbfe1a7d66d0516e6, // 0.83402, -0.55174 + 0x3feaa9547a2cb98e, 0xbfe1b250171373be, // 0.83317, -0.55302 + 0x3feaa25f5f5aee60, 0xbfe1bcc706804467, // 0.83232, -0.55429 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3fea9468d85b20ae, 0xbfe1d1acaf012cc2, // 0.83062, -0.55685 + 0x3fea8d676e545ad2, 0xbfe1dc1b64dc4872, // 0.82976, -0.55812 + 0x3fea8661ec0ee133, 0xbfe1e68759a3e074, // 0.8289, -0.55939 + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066 + 0x3fea784aa31d3f55, 0xbfe1fb56f98b37b8, // 0.82718, -0.56193 + 0x3fea7138de9d60f5, 0xbfe205baa17560d6, // 0.82632, -0.5632 + 0x3fea6a230637623b, 0xbfe2101b81e0da78, // 0.82546, -0.56447 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea5beb1e188375, 0xbfe224d4e5d5482e, // 0.82372, -0.567 + 0x3fea54c91090f524, 0xbfe22f2d662c13e1, // 0.82285, -0.56826 + 0x3fea4da2f385e997, 0xbfe23983189fdfd5, // 0.82198, -0.56952 + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078 + 0x3fea3f4a8f4ee2d2, 0xbfe24e260d7ee7c9, // 0.82023, -0.57204 + 0x3fea38184a593bc6, 0xbfe258734cbb7110, // 0.81935, -0.5733 + 0x3fea30e1fa4cbf81, 0xbfe262bdb7b795a2, // 0.81847, -0.57455 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea22693d62ccb9, 0xbfe2774a0a961612, // 0.8167, -0.57706 + 0x3fea1b26d2c0a75e, 0xbfe2818bef4d3cba, // 0.81581, -0.57831 + 0x3fea13e0617e4ec7, 0xbfe28bcaf96d94ba, // 0.81493, -0.57956 + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081 + 0x3fea05476f967bb5, 0xbfe2a040779843fb, // 0.81314, -0.58206 + 0x3fe9fdf4f13149de, 0xbfe2aa76e87aeb58, // 0.81225, -0.58331 + 0x3fe9f69e70ac75bc, 0xbfe2b4aa787764c4, // 0.81135, -0.58455 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fe9e7e56dcb45bd, 0xbfe2c908ef734e57, // 0.80956, -0.58704 + 0x3fe9e082edb42472, 0xbfe2d333d34e9bb7, // 0.80866, -0.58828 + 0x3fe9d91c7007d5a6, 0xbfe2dd5bcffb7616, // 0.80775, -0.58952 + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076 + 0x3fe9ca438080eadb, 0xbfe2f1a30d86773a, // 0.80594, -0.592 + 0x3fe9c2d110f075c3, 0xbfe2fbc24b441015, // 0.80503, -0.59323 + 0x3fe9bb5aa85f2098, 0xbfe305de9b921a94, // 0.80412, -0.59447 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9ac61f0d4e247, 0xbfe31a0e6da35e44, // 0.80229, -0.59693 + 0x3fe9a4dfa42b06b2, 0xbfe32421ec49a620, // 0.80138, -0.59816 + 0x3fe99d59631e65d5, 0xbfe32e3277467d6b, // 0.80046, -0.59939 + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062 + 0x3fe98e410881a600, 0xbfe3424aac0ef7d6, // 0.79861, -0.60184 + 0x3fe986aef1457594, 0xbfe34c5252c14de1, // 0.79769, -0.60307 + 0x3fe97f18ea4e5c9e, 0xbfe35656ff9799ae, // 0.79676, -0.60429 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe96fe111ddfce0, 0xbfe36a576582831b, // 0.79491, -0.60673 + 0x3fe9683f42bd7fe1, 0xbfe374531b817f8d, // 0.79398, -0.60795 + 0x3fe960998893ad8c, 0xbfe37e4bd1792fe2, // 0.79304, -0.60917 + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038 + 0x3fe9514257dc4335, 0xbfe39234372c7f04, // 0.79117, -0.6116 + 0x3fe94990e3ac4a6c, 0xbfe39c23e3d63029, // 0.79023, -0.61281 + 0x3fe941db892e3a65, 0xbfe3a6108a54ba58, // 0.78929, -0.61402 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe932652609b1cf, 0xbfe3b9e0beb19e18, // 0.7874, -0.61644 + 0x3fe92aa41fc5a815, 0xbfe3c3c44981c517, // 0.78646, -0.61765 + 0x3fe922df37f8646a, 0xbfe3cda4c80a6076, // 0.78551, -0.61885 + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006 + 0x3fe91349c88da398, 0xbfe3e15c9a2db922, // 0.7836, -0.62126 + 0x3fe90b7943575efe, 0xbfe3eb33eabe0680, // 0.78265, -0.62246 + 0x3fe903a4e1665133, 0xbfe3f50828f1e8d2, // 0.78169, -0.62366 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe8f3f08c28d9ac, 0xbfe408a76834c0c0, // 0.77978, -0.62606 + 0x3fe8ec109b486c49, 0xbfe41272663d108c, // 0.77882, -0.62725 + 0x3fe8e42cd2852e0a, 0xbfe41c3a4bdbaa26, // 0.77785, -0.62845 + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964 + 0x3fe8d459be34bdfa, 0xbfe42fc0c7d3adbb, // 0.77592, -0.63083 + 0x3fe8cc6a75184655, 0xbfe4397f5b2a4380, // 0.77495, -0.63202 + 0x3fe8c47758fa71cb, 0xbfe4433ad0117b1d, // 0.77398, -0.63321 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8b485aca2a468, 0xbfe456a858917046, // 0.77204, -0.63558 + 0x3fe8ac871ede1d88, 0xbfe4605a692b32a2, // 0.77106, -0.63676 + 0x3fe8a484c3031d50, 0xbfe46a095557a0f1, // 0.77008, -0.63794 + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912 + 0x3fe89474a5fb0a84, 0xbfe47d5dba6fde01, // 0.76812, -0.6403 + 0x3fe88c66e7481ba1, 0xbfe48703306091fe, // 0.76714, -0.64148 + 0x3fe884555f72fa6b, 0xbfe490a57bedbcdf, // 0.76615, -0.64266 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe87426f95cd5bd, 0xbfe4a3e08dec9ed6, // 0.76418, -0.645 + 0x3fe86c0a1d9aa195, 0xbfe4ad79516722f0, // 0.76319, -0.64618 + 0x3fe863e97db3d95a, 0xbfe4b70ee48fb869, // 0.7622, -0.64735 + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851 + 0x3fe8539cf67c9029, 0xbfe4ca30740218a3, // 0.76021, -0.64968 + 0x3fe84b7111af83f9, 0xbfe4d3bc6d589f80, // 0.75921, -0.65085 + 0x3fe843416dc4cce2, 0xbfe4dd453076b064, // 0.75821, -0.65201 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe832d6eda3a3e0, 0xbfe4f04d0e2859aa, // 0.75621, -0.65433 + 0x3fe82a9c13f545ff, 0xbfe4f9cc25cca486, // 0.7552, -0.65549 + 0x3fe8225d803964e5, 0xbfe503480159ded2, // 0.75419, -0.65665 + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781 + 0x3fe811d52faf94dc, 0xbfe51635fe5601d7, // 0.75218, -0.65896 + 0x3fe8098b756e52fa, 0xbfe51fa81cd99aa6, // 0.75117, -0.66011 + 0x3fe8013e0638e795, 0xbfe52916f96f8388, // 0.75015, -0.66127 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe7f0980e113978, 0xbfe53beae7012abe, // 0.74812, -0.66356 + 0x3fe7e83f87b03686, 0xbfe5454ff5159dfb, // 0.7471, -0.66471 + 0x3fe7dfe3517d8937, 0xbfe54eb1bb6dcb8f, // 0.74608, -0.66586 + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667 + 0x3fe7cf1fdacbf179, 0xbfe5616b6b204e6e, // 0.74403, -0.66814 + 0x3fe7c6b89ce2d333, 0xbfe56ac35197649e, // 0.74301, -0.66928 + 0x3fe7be4db453a27c, 0xbfe57417ea8bb75c, // 0.74198, -0.67042 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7ad6ce874dbb6, 0xbfe586b72e2b2cfd, // 0.73992, -0.67269 + 0x3fe7a4f707bf97d2, 0xbfe59001d5f723df, // 0.73889, -0.67383 + 0x3fe79c7d8198e56e, 0xbfe599492a81ffbc, // 0.73785, -0.67496 + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609 + 0x3fe78b7f8a320a52, 0xbfe5abcdd41bb0d8, // 0.73578, -0.67722 + 0x3fe782fb1b90b35b, 0xbfe5b50b264f7448, // 0.73474, -0.67835 + 0x3fe77a730cbb9100, 0xbfe5be451f8bf980, // 0.7337, -0.67948 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe7695813b9b594, 0xbfe5d0af016ed1d4, // 0.73161, -0.68172 + 0x3fe760c52c304764, 0xbfe5d9dee73e345c, // 0.73056, -0.68285 + 0x3fe7582ea9b9a329, 0xbfe5e30b6e6877f3, // 0.72951, -0.68397 + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508 + 0x3fe746f6d9516d59, 0xbfe5f55a5b2576f8, // 0.72741, -0.6862 + 0x3fe73e558e079942, 0xbfe5fe7cbde56a0f, // 0.72636, -0.68732 + 0x3fe735b0ad2009b2, 0xbfe6079bbc5aadfa, // 0.7253, -0.68843 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe7245c2fcd492a, 0xbfe619cf86c55702, // 0.72319, -0.69065 + 0x3fe71bac960e41bf, 0xbfe622e44fec22ff, // 0.72213, -0.69176 + 0x3fe712f96c09d18d, 0xbfe62bf5af2b0dfd, // 0.72107, -0.69287 + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397 + 0x3fe701886c8f16e6, 0xbfe63e0e2a59d7aa, // 0.71894, -0.69508 + 0x3fe6f8ca99c95b75, 0xbfe64715437f535b, // 0.71787, -0.69618 + 0x3fe6f0093c1f54de, 0xbfe65018ed28287f, // 0.7168, -0.69728 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe6de7be585881d, 0xbfe66215ec74eb91, // 0.71466, -0.69947 + 0x3fe6d5afef4aafcc, 0xbfe66b0f3f52b386, // 0.71358, -0.70057 + 0x3fe6cce07395679f, 0xbfe674051d27896c, // 0.71251, -0.70166 + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275 + 0x3fe6bb36f12b5e06, 0xbfe685e6742feeef, // 0.71035, -0.70385 + 0x3fe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // 0.70927, -0.70493 + 0x3fe6a97f692c82ea, 0xbfe697b9e686941c, // 0.70819, -0.70602 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe697b9e686941c, 0xbfe6a97f692c82ea, // 0.70602, -0.70819 + 0x3fe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // 0.70493, -0.70927 + 0x3fe685e6742feeef, 0xbfe6bb36f12b5e06, // 0.70385, -0.71035 + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143 + 0x3fe674051d27896c, 0xbfe6cce07395679f, // 0.70166, -0.71251 + 0x3fe66b0f3f52b386, 0xbfe6d5afef4aafcc, // 0.70057, -0.71358 + 0x3fe66215ec74eb91, 0xbfe6de7be585881d, // 0.69947, -0.71466 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe65018ed28287f, 0xbfe6f0093c1f54de, // 0.69728, -0.7168 + 0x3fe64715437f535b, 0xbfe6f8ca99c95b75, // 0.69618, -0.71787 + 0x3fe63e0e2a59d7aa, 0xbfe701886c8f16e6, // 0.69508, -0.71894 + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72 + 0x3fe62bf5af2b0dfd, 0xbfe712f96c09d18d, // 0.69287, -0.72107 + 0x3fe622e44fec22ff, 0xbfe71bac960e41bf, // 0.69176, -0.72213 + 0x3fe619cf86c55702, 0xbfe7245c2fcd492a, // 0.69065, -0.72319 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe6079bbc5aadfa, 0xbfe735b0ad2009b2, // 0.68843, -0.7253 + 0x3fe5fe7cbde56a0f, 0xbfe73e558e079942, // 0.68732, -0.72636 + 0x3fe5f55a5b2576f8, 0xbfe746f6d9516d59, // 0.6862, -0.72741 + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846 + 0x3fe5e30b6e6877f3, 0xbfe7582ea9b9a329, // 0.68397, -0.72951 + 0x3fe5d9dee73e345c, 0xbfe760c52c304764, // 0.68285, -0.73056 + 0x3fe5d0af016ed1d4, 0xbfe7695813b9b594, // 0.68172, -0.73161 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe5be451f8bf980, 0xbfe77a730cbb9100, // 0.67948, -0.7337 + 0x3fe5b50b264f7448, 0xbfe782fb1b90b35b, // 0.67835, -0.73474 + 0x3fe5abcdd41bb0d8, 0xbfe78b7f8a320a52, // 0.67722, -0.73578 + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682 + 0x3fe599492a81ffbc, 0xbfe79c7d8198e56e, // 0.67496, -0.73785 + 0x3fe59001d5f723df, 0xbfe7a4f707bf97d2, // 0.67383, -0.73889 + 0x3fe586b72e2b2cfd, 0xbfe7ad6ce874dbb6, // 0.67269, -0.73992 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe57417ea8bb75c, 0xbfe7be4db453a27c, // 0.67042, -0.74198 + 0x3fe56ac35197649e, 0xbfe7c6b89ce2d333, // 0.66928, -0.74301 + 0x3fe5616b6b204e6e, 0xbfe7cf1fdacbf179, // 0.66814, -0.74403 + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506 + 0x3fe54eb1bb6dcb8f, 0xbfe7dfe3517d8937, // 0.66586, -0.74608 + 0x3fe5454ff5159dfb, 0xbfe7e83f87b03686, // 0.66471, -0.7471 + 0x3fe53beae7012abe, 0xbfe7f0980e113978, // 0.66356, -0.74812 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe52916f96f8388, 0xbfe8013e0638e795, // 0.66127, -0.75015 + 0x3fe51fa81cd99aa6, 0xbfe8098b756e52fa, // 0.66011, -0.75117 + 0x3fe51635fe5601d7, 0xbfe811d52faf94dc, // 0.65896, -0.75218 + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319 + 0x3fe503480159ded2, 0xbfe8225d803964e5, // 0.65665, -0.75419 + 0x3fe4f9cc25cca486, 0xbfe82a9c13f545ff, // 0.65549, -0.7552 + 0x3fe4f04d0e2859aa, 0xbfe832d6eda3a3e0, // 0.65433, -0.75621 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe4dd453076b064, 0xbfe843416dc4cce2, // 0.65201, -0.75821 + 0x3fe4d3bc6d589f80, 0xbfe84b7111af83f9, // 0.65085, -0.75921 + 0x3fe4ca30740218a3, 0xbfe8539cf67c9029, // 0.64968, -0.76021 + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612 + 0x3fe4b70ee48fb869, 0xbfe863e97db3d95a, // 0.64735, -0.7622 + 0x3fe4ad79516722f0, 0xbfe86c0a1d9aa195, // 0.64618, -0.76319 + 0x3fe4a3e08dec9ed6, 0xbfe87426f95cd5bd, // 0.645, -0.76418 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe490a57bedbcdf, 0xbfe884555f72fa6b, // 0.64266, -0.76615 + 0x3fe48703306091fe, 0xbfe88c66e7481ba1, // 0.64148, -0.76714 + 0x3fe47d5dba6fde01, 0xbfe89474a5fb0a84, // 0.6403, -0.76812 + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691 + 0x3fe46a095557a0f1, 0xbfe8a484c3031d50, // 0.63794, -0.77008 + 0x3fe4605a692b32a2, 0xbfe8ac871ede1d88, // 0.63676, -0.77106 + 0x3fe456a858917046, 0xbfe8b485aca2a468, // 0.63558, -0.77204 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe4433ad0117b1d, 0xbfe8c47758fa71cb, // 0.63321, -0.77398 + 0x3fe4397f5b2a4380, 0xbfe8cc6a75184655, // 0.63202, -0.77495 + 0x3fe42fc0c7d3adbb, 0xbfe8d459be34bdfa, // 0.63083, -0.77592 + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689 + 0x3fe41c3a4bdbaa26, 0xbfe8e42cd2852e0a, // 0.62845, -0.77785 + 0x3fe41272663d108c, 0xbfe8ec109b486c49, // 0.62725, -0.77882 + 0x3fe408a76834c0c0, 0xbfe8f3f08c28d9ac, // 0.62606, -0.77978 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe3f50828f1e8d2, 0xbfe903a4e1665133, // 0.62366, -0.78169 + 0x3fe3eb33eabe0680, 0xbfe90b7943575efe, // 0.62246, -0.78265 + 0x3fe3e15c9a2db922, 0xbfe91349c88da398, // 0.62126, -0.7836 + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456 + 0x3fe3cda4c80a6076, 0xbfe922df37f8646a, // 0.61885, -0.78551 + 0x3fe3c3c44981c517, 0xbfe92aa41fc5a815, // 0.61765, -0.78646 + 0x3fe3b9e0beb19e18, 0xbfe932652609b1cf, // 0.61644, -0.7874 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe3a6108a54ba58, 0xbfe941db892e3a65, // 0.61402, -0.78929 + 0x3fe39c23e3d63029, 0xbfe94990e3ac4a6c, // 0.61281, -0.79023 + 0x3fe39234372c7f04, 0xbfe9514257dc4335, // 0.6116, -0.79117 + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211 + 0x3fe37e4bd1792fe2, 0xbfe960998893ad8c, // 0.60917, -0.79304 + 0x3fe374531b817f8d, 0xbfe9683f42bd7fe1, // 0.60795, -0.79398 + 0x3fe36a576582831b, 0xbfe96fe111ddfce0, // 0.60673, -0.79491 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe35656ff9799ae, 0xbfe97f18ea4e5c9e, // 0.60429, -0.79676 + 0x3fe34c5252c14de1, 0xbfe986aef1457594, // 0.60307, -0.79769 + 0x3fe3424aac0ef7d6, 0xbfe98e410881a600, // 0.60184, -0.79861 + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954 + 0x3fe32e3277467d6b, 0xbfe99d59631e65d5, // 0.59939, -0.80046 + 0x3fe32421ec49a620, 0xbfe9a4dfa42b06b2, // 0.59816, -0.80138 + 0x3fe31a0e6da35e44, 0xbfe9ac61f0d4e247, // 0.59693, -0.80229 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe305de9b921a94, 0xbfe9bb5aa85f2098, // 0.59447, -0.80412 + 0x3fe2fbc24b441015, 0xbfe9c2d110f075c3, // 0.59323, -0.80503 + 0x3fe2f1a30d86773a, 0xbfe9ca438080eadb, // 0.592, -0.80594 + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685 + 0x3fe2dd5bcffb7616, 0xbfe9d91c7007d5a6, // 0.58952, -0.80775 + 0x3fe2d333d34e9bb7, 0xbfe9e082edb42472, // 0.58828, -0.80866 + 0x3fe2c908ef734e57, 0xbfe9e7e56dcb45bd, // 0.58704, -0.80956 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe2b4aa787764c4, 0xbfe9f69e70ac75bc, // 0.58455, -0.81135 + 0x3fe2aa76e87aeb58, 0xbfe9fdf4f13149de, // 0.58331, -0.81225 + 0x3fe2a040779843fb, 0xbfea05476f967bb5, // 0.58206, -0.81314 + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404 + 0x3fe28bcaf96d94ba, 0xbfea13e0617e4ec7, // 0.57956, -0.81493 + 0x3fe2818bef4d3cba, 0xbfea1b26d2c0a75e, // 0.57831, -0.81581 + 0x3fe2774a0a961612, 0xbfea22693d62ccb9, // 0.57706, -0.8167 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe262bdb7b795a2, 0xbfea30e1fa4cbf81, // 0.57455, -0.81847 + 0x3fe258734cbb7110, 0xbfea38184a593bc6, // 0.5733, -0.81935 + 0x3fe24e260d7ee7c9, 0xbfea3f4a8f4ee2d2, // 0.57204, -0.82023 + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211 + 0x3fe23983189fdfd5, 0xbfea4da2f385e997, // 0.56952, -0.82198 + 0x3fe22f2d662c13e1, 0xbfea54c91090f524, // 0.56826, -0.82285 + 0x3fe224d4e5d5482e, 0xbfea5beb1e188375, // 0.567, -0.82372 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe2101b81e0da78, 0xbfea6a230637623b, // 0.56447, -0.82546 + 0x3fe205baa17560d6, 0xbfea7138de9d60f5, // 0.5632, -0.82632 + 0x3fe1fb56f98b37b8, 0xbfea784aa31d3f55, // 0.56193, -0.82718 + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805 + 0x3fe1e68759a3e074, 0xbfea8661ec0ee133, // 0.55939, -0.8289 + 0x3fe1dc1b64dc4872, 0xbfea8d676e545ad2, // 0.55812, -0.82976 + 0x3fe1d1acaf012cc2, 0xbfea9468d85b20ae, // 0.55685, -0.83062 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe1bcc706804467, 0xbfeaa25f5f5aee60, // 0.55429, -0.83232 + 0x3fe1b250171373be, 0xbfeaa9547a2cb98e, // 0.55302, -0.83317 + 0x3fe1a7d66d0516e6, 0xbfeab045787157ff, // 0.55174, -0.83402 + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486 + 0x3fe192daef7a5386, 0xbfeabe1b1b0b8dac, // 0.54918, -0.83571 + 0x3fe188591f3a46e5, 0xbfeac4ffbd3efac8, // 0.54789, -0.83655 + 0x3fe17dd49ad16161, 0xbfeacbe03ea0e73b, // 0.54661, -0.83739 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe168c37c025764, 0xbfead994dab2e979, // 0.54404, -0.83906 + 0x3fe15e36e4dbe2bc, 0xbfeae068f345ecef, // 0.54275, -0.83989 + 0x3fe153a7a00bf453, 0xbfeae738e6cd4b67, // 0.54146, -0.84073 + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155 + 0x3fe13e8113f396c1, 0xbfeaf4cc5a85fb73, // 0.53888, -0.84238 + 0x3fe133e9cfee254e, 0xbfeafb8fd89f57b6, // 0.53759, -0.84321 + 0x3fe1294fe4c5350a, 0xbfeb024f2d7d24a9, // 0.53629, -0.84403 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe114141f935545, 0xbfeb0fc1575d33db, // 0.5337, -0.84567 + 0x3fe1097248d0a956, 0xbfeb16742a4ca2f5, // 0.5324, -0.84649 + 0x3fe0fecdd1770537, 0xbfeb1d22cfdadcc6, // 0.5311, -0.84731 + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812 + 0x3fe0e97d078fd23b, 0xbfeb2a738eb51f33, // 0.5285, -0.84893 + 0x3fe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // 0.5272, -0.84974 + 0x3fe0d421cf03c12b, 0xbfeb37b38bb54c09, // 0.5259, -0.85055 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe0bebc34ff4646, 0xbfeb44e2beaf0a61, // 0.52328, -0.85216 + 0x3fe0b405878f85ec, 0xbfeb4b7409de7925, // 0.52198, -0.85296 + 0x3fe0a94c46b53d0b, 0xbfeb52011f805c92, // 0.52067, -0.85376 + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456 + 0x3fe093d2115ee018, 0xbfeb5f0ea611a532, // 0.51804, -0.85535 + 0x3fe089112032b08c, 0xbfeb658f14fdbc47, // 0.51673, -0.85615 + 0x3fe07e4da23bc102, 0xbfeb6c0b4a55ac17, // 0.51542, -0.85694 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe068bf0691c028, 0xbfeb78f70449a34b, // 0.51279, -0.85852 + 0x3fe05df3ec31b8b6, 0xbfeb7f6686e792ea, // 0.51147, -0.8593 + 0x3fe053264bad0483, 0xbfeb85d1cbf52c02, // 0.51015, -0.86009 + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087 + 0x3fe03d837edff370, 0xbfeb929b996a5b7f, // 0.50751, -0.86165 + 0x3fe032ae55edbd95, 0xbfeb98fa1fd9155e, // 0.50619, -0.86242 + 0x3fe027d6ad83287e, 0xbfeb9f5464c5bffc, // 0.50486, -0.8632 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe0121fe4f56d2c, 0xbfebabfc262e6586, // 0.50221, -0.86474 + 0x3fe00740c82b82e0, 0xbfebb249a0b6c40d, // 0.50089, -0.86551 + 0x3fdff8be6537615e, 0xbfebb892d5d5dad5, // 0.49956, -0.86628 + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705 + 0x3fdfcd2947c1ff57, 0xbfebc5186bf8361d, // 0.4969, -0.86781 + 0x3fdfb7575c24d2de, 0xbfebcb54cb0d2327, // 0.49557, -0.86857 + 0x3fdfa1808c6cf7e0, 0xbfebd18ce0dc19d6, // 0.49423, -0.86933 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fdf75c44e26a852, 0xbfebddf02cd2b983, // 0.49156, -0.87084 + 0x3fdf5fdee656cda3, 0xbfebe41b611154c1, // 0.49023, -0.8716 + 0x3fdf49f4a7e97729, 0xbfebea424837de6d, // 0.48889, -0.87235 + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309 + 0x3fdf1e11b4bbc35c, 0xbfebf6832b71ec5b, // 0.48621, -0.87384 + 0x3fdf081906bff7fd, 0xbfebfc9d25a1b147, // 0.48487, -0.87459 + 0x3fdef21b8fafd3b5, 0xbfec02b2cef1e641, // 0.48353, -0.87533 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdec61253e3c61b, 0xbfec0ed12b3372e9, // 0.48084, -0.87681 + 0x3fdeb00695f25620, 0xbfec14d9dc465e58, // 0.47949, -0.87755 + 0x3fde99f61c817eda, 0xbfec1ade38bce19b, // 0.47815, -0.87828 + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901 + 0x3fde6dc704be97e2, 0xbfec26d9f01f2eaf, // 0.47545, -0.87974 + 0x3fde57a86d3cd824, 0xbfec2cd14931e3f1, // 0.4741, -0.88047 + 0x3fde418527dc4ffa, 0xbfec32c449f60831, // 0.47275, -0.8812 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fde1530a12779f4, 0xbfec3e9d3ee7d262, // 0.47004, -0.88264 + 0x3fddfeff66a941de, 0xbfec44833141c004, // 0.46869, -0.88336 + 0x3fdde8c98bf86bd6, 0xbfec4a64c7a5ac4c, // 0.46733, -0.88408 + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848 + 0x3fddbc5003b2edf8, 0xbfec561adceb743e, // 0.46462, -0.88551 + 0x3fdda60c5cfa10d8, 0xbfec5bef59fef85a, // 0.46326, -0.88622 + 0x3fdd8fc423c62a25, 0xbfec61bf777fcc48, // 0.4619, -0.88693 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fdd632607ac9aa9, 0xbfec6d5290341eb2, // 0.45918, -0.88835 + 0x3fdd4cd02ba8609c, 0xbfec7315899eaad7, // 0.45781, -0.88905 + 0x3fdd3675caebf962, 0xbfec78d41fe4a267, // 0.45645, -0.88975 + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045 + 0x3fdd09b389152ec1, 0xbfec84441f785f61, // 0.45372, -0.89115 + 0x3fdcf34baee1cd21, 0xbfec89f587029c13, // 0.45235, -0.89184 + 0x3fdcdcdf5dc440ce, 0xbfec8fa287e13305, // 0.45098, -0.89253 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdcaff964a0421d, 0xbfec9aef521bd480, // 0.44824, -0.89391 + 0x3fdc997fc3865388, 0xbfeca08f19b9c449, // 0.44687, -0.8946 + 0x3fdc8301b95b40c2, 0xbfeca62a772fd919, // 0.4455, -0.89528 + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597 + 0x3fdc55f877b23537, 0xbfecb153f02fb87d, // 0.44275, -0.89665 + 0x3fdc3f6d47263129, 0xbfecb6e20a00da99, // 0.44137, -0.89732 + 0x3fdc28ddbb6cf145, 0xbfecbc6bb638d10b, // 0.43999, -0.898 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdbfbb1a05e0edc, 0xbfecc771c2736c09, // 0.43724, -0.89935 + 0x3fdbe51517ffc0d9, 0xbfecccee20c2de9f, // 0.43586, -0.90002 + 0x3fdbce744262deee, 0xbfecd2660e12c1e6, // 0.43448, -0.90068 + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135 + 0x3fdba125bd63583e, 0xbfecdd489254fe65, // 0.43171, -0.90201 + 0x3fdb8a7814fd5693, 0xbfece2b32799a060, // 0.43033, -0.90267 + 0x3fdb73c62d520624, 0xbfece819488344ce, // 0.42894, -0.90333 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdb4655ae2bf757, 0xbfecf2d829f1b40e, // 0.42617, -0.90464 + 0x3fdb2f971db31972, 0xbfecf830e8ce467b, // 0.42478, -0.9053 + 0x3fdb18d45bf8aca6, 0xbfecfd852fff6ad4, // 0.42339, -0.90595 + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066 + 0x3fdaeb4252ca07ab, 0xbfed082054168bac, // 0.42061, -0.90724 + 0x3fdad473125cdc08, 0xbfed0d672f59d2b9, // 0.41922, -0.90789 + 0x3fdabd9faebc3980, 0xbfed12a98fac410c, // 0.41782, -0.90853 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fda8fec8bf5b166, 0xbfed1d20dc40c15c, // 0.41503, -0.90981 + 0x3fda790cd3dbf31a, 0xbfed2255c6e5a4e1, // 0.41364, -0.91044 + 0x3fda622906a70b63, 0xbfed2786335f52fc, // 0.41224, -0.91107 + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171 + 0x3fda34553b0afee5, 0xbfed31d98e9e503a, // 0.40944, -0.91234 + 0x3fda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // 0.40804, -0.91296 + 0x3fda067145664d57, 0xbfed3c1ae79f2b4e, // 0.40664, -0.91359 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fd9d87d4207b0ab, 0xbfed464a380e7242, // 0.40384, -0.91483 + 0x3fd9c17d440df9f2, 0xbfed4b5b1b187524, // 0.40243, -0.91545 + 0x3fd9aa794d47c9ee, 0xbfed506779a3d2d9, // 0.40103, -0.91606 + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668 + 0x3fd97c6583890fc2, 0xbfed5a72a6221e73, // 0.39822, -0.91729 + 0x3fd96555b7ab948f, 0xbfed5f7172888a7f, // 0.39681, -0.9179 + 0x3fd94e420137bce3, 0xbfed646bb7574de5, // 0.3954, -0.91851 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd9200ee2c9be97, 0xbfed6e52a71c8547, // 0.39258, -0.91972 + 0x3fd908ef81ef7bd1, 0xbfed733f508c0dff, // 0.39117, -0.92032 + 0x3fd8f1cc44bea329, 0xbfed78276f5617c6, // 0.38976, -0.92092 + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151 + 0x3fd8c37a439f884f, 0xbfed81ea09f38b63, // 0.38693, -0.92211 + 0x3fd8ac4b86d5ed44, 0xbfed86c48445a450, // 0.38552, -0.9227 + 0x3fd89518fbff098e, 0xbfed8b9a70ef9cb4, // 0.3841, -0.92329 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd866a88a792ea0, 0xbfed95389e50429b, // 0.38127, -0.92447 + 0x3fd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // 0.37985, -0.92505 + 0x3fd838290bb359c8, 0xbfed9ec48c26b1f3, // 0.37843, -0.92563 + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621 + 0x3fd8099a9c5c362d, 0xbfeda83e348f613b, // 0.37559, -0.92679 + 0x3fd7f24dd37341e3, 0xbfedacf42ce68ab9, // 0.37416, -0.92736 + 0x3fd7dafd592ba621, 0xbfedb1a591b20c38, // 0.37274, -0.92794 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd7ac515ee2b172, 0xbfedbafa9dc1b78d, // 0.36989, -0.92907 + 0x3fd794f5e613dfae, 0xbfedbf9e4395759a, // 0.36847, -0.92964 + 0x3fd77d96ca4b73a6, 0xbfedc43d52fcb453, // 0.36704, -0.93021 + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077 + 0x3fd74ecdb8390a3e, 0xbfedcd6dabaca3a5, // 0.36418, -0.93133 + 0x3fd73763c9261092, 0xbfedd1fef38a915a, // 0.36276, -0.93188 + 0x3fd71ff6458782ec, 0xbfedd68ba2267a25, // 0.36133, -0.93244 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd6f1108f1bc9c5, 0xbfeddf9730ca837b, // 0.35846, -0.93354 + 0x3fd6d998638a0cb5, 0xbfede4160f6d8d81, // 0.35703, -0.93409 + 0x3fd6c21cb1e39771, 0xbfede890520465ce, // 0.3556, -0.93464 + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518 + 0x3fd6931acad55f51, 0xbfedf177004b2534, // 0.35273, -0.93573 + 0x3fd67b949cad63ca, 0xbfedf5e36a9ba59c, // 0.35129, -0.93627 + 0x3fd6640af6f03d9e, 0xbfedfa4b3621271d, // 0.34986, -0.9368 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd634ed533be58e, 0xbfee030cee1435b8, // 0.34698, -0.93787 + 0x3fd61d595c88c203, 0xbfee0766d9280f54, // 0.34554, -0.9384 + 0x3fd605c1fcc88f63, 0xbfee0bbc22bd8349, // 0.3441, -0.93893 + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946 + 0x3fd5d68910aee686, 0xbfee1458cec1ad83, // 0.34122, -0.93998 + 0x3fd5bee78b9db3b6, 0xbfee18a02fdc66d9, // 0.33978, -0.94051 + 0x3fd5a742ac0ff78d, 0xbfee1ce2ecd0c0d8, // 0.33833, -0.94103 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd577eeec151e47, 0xbfee255a77a63bb8, // 0.33545, -0.94206 + 0x3fd5604012f467b4, 0xbfee298f4439197a, // 0.334, -0.94257 + 0x3fd5488dedeff3be, 0xbfee2dbf6a0911d9, // 0.33255, -0.94308 + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359 + 0x3fd5191fceda3c35, 0xbfee3611becbaf69, // 0.32966, -0.9441 + 0x3fd50163dc197047, 0xbfee3a33ec75ce85, // 0.32821, -0.9446 + 0x3fd4e9a4ac15d520, 0xbfee3e5170cbfc46, // 0.32676, -0.94511 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd4ba1ca2eca31c, 0xbfee467e7af35f23, // 0.32386, -0.94611 + 0x3fd4a253d11b82f3, 0xbfee4a8dff81ce5e, // 0.32241, -0.9466 + 0x3fd48a87d0b07fd7, 0xbfee4e98d836c0af, // 0.32096, -0.94709 + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759 + 0x3fd45ae652bb2800, 0xbfee56a083968eb1, // 0.31805, -0.94807 + 0x3fd44310dc8936f0, 0xbfee5a9d550467d3, // 0.31659, -0.94856 + 0x3fd42b38466e2928, 0xbfee5e95781ebf1c, // 0.31514, -0.94905 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd3fb7dc932cfa4, 0xbfee6677b0e6d31e, // 0.31222, -0.95001 + 0x3fd3e39be96ec271, 0xbfee6a61c55d53a7, // 0.31077, -0.95049 + 0x3fd3cbb6f87a146e, 0xbfee6e472911da27, // 0.30931, -0.95096 + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144 + 0x3fd39be3f1bc8aef, 0xbfee7603dbce74e9, // 0.30639, -0.95191 + 0x3fd383f5e353b6aa, 0xbfee79db29a5165a, // 0.30493, -0.95238 + 0x3fd36c04d27a4edf, 0xbfee7dadc456d850, // 0.30347, -0.95284 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd33c19b83af207, 0xbfee8544ddf0d075, // 0.30054, -0.95377 + 0x3fd3241fb638baaf, 0xbfee89095bad6025, // 0.29908, -0.95423 + 0x3fd30c22c08d6a13, 0xbfee8cc923edc388, // 0.29762, -0.95469 + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514 + 0x3fd2dc200907fe51, 0xbfee943a91aab4b4, // 0.29469, -0.95559 + 0x3fd2c41a4e954520, 0xbfee97ec36016b30, // 0.29322, -0.95605 + 0x3fd2ac11af483572, 0xbfee9b99229046f8, // 0.29175, -0.95649 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd27bf7d0f2c346, 0xbfeea2e4d212c000, // 0.28882, -0.95738 + 0x3fd263e6995554ba, 0xbfeea68393e65800, // 0.28735, -0.95783 + 0x3fd24bd28bb37672, 0xbfeeaa1d9bb20af3, // 0.28588, -0.95827 + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587 + 0x3fd21ba1fd3d2623, 0xbfeeb1437af9bb34, // 0.28294, -0.95914 + 0x3fd2038583d727bd, 0xbfeeb4cf515b8811, // 0.28146, -0.95957 + 0x3fd1eb6643499fbb, 0xbfeeb8566b810f2a, // 0.27999, -0.96 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd1bb1f7b999480, 0xbfeebf5668eaf2ef, // 0.27705, -0.96086 + 0x3fd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // 0.27557, -0.96128 + 0x3fd18acdc3f4873a, 0xbfeec6436ee60309, // 0.2741, -0.9617 + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212 + 0x3fd15a713a28b9d9, 0xbfeecd1d792c8f10, // 0.27115, -0.96254 + 0x3fd1423eefc69378, 0xbfeed0835e999009, // 0.26967, -0.96295 + 0x3fd12a09fc0b1b12, 0xbfeed3e483849c51, // 0.26819, -0.96337 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd0f998277733f7, 0xbfeeda9889bfe86a, // 0.26523, -0.96418 + 0x3fd0e15b4e1749cd, 0xbfeeddeb6a078651, // 0.26375, -0.96459 + 0x3fd0c91bda4f158d, 0xbfeee13987bbebdc, // 0.26227, -0.96499 + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539 + 0x3fd09895327b465e, 0xbfeee7c77961dc9e, // 0.25931, -0.96579 + 0x3fd0804e05eb661e, 0xbfeeeb074c50a544, // 0.25783, -0.96619 + 0x3fd068044deab002, 0xbfeeee425aa6b09a, // 0.25635, -0.96658 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd037694a928cac, 0xbfeef4aa278b2032, // 0.25338, -0.96737 + 0x3fd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // 0.2519, -0.96775 + 0x3fd006c4466e54af, 0xbfeefafedc1ba8b7, // 0.25041, -0.96814 + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852 + 0x3fcfac2abeff57ff, 0xbfef014074708ed3, // 0.24744, -0.9689 + 0x3fcf7b7480bd3801, 0xbfef045a14cf738c, // 0.24596, -0.96928 + 0x3fcf4ab9679c9f5c, 0xbfef076eecade0fa, // 0.24447, -0.96966 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fcee934c2d006c7, 0xbfef0d8a410379c5, // 0.24149, -0.9704 + 0x3fceb86b462de348, 0xbfef1090bc898f5f, // 0.24, -0.97077 + 0x3fce879d0cc0fdaf, 0xbfef13926dad024e, // 0.23851, -0.97114 + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715 + 0x3fce25f281a2b684, 0xbfef19876ef1f486, // 0.23553, -0.97187 + 0x3fcdf5163f01099a, 0xbfef1c7abe284708, // 0.23404, -0.97223 + 0x3fcdc4355db40195, 0xbfef1f6941259d7a, // 0.23255, -0.97258 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fcd6265dd3f27e3, 0xbfef2537e0a71f9f, // 0.22957, -0.97329 + 0x3fcd31774d2cbdee, 0xbfef2817fc4609ce, // 0.22807, -0.97364 + 0x3fcd00843c99c5f9, 0xbfef2af349e17507, // 0.22658, -0.97399 + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434 + 0x3fcc9e90b824a6a9, 0xbfef309b794b719f, // 0.22359, -0.97468 + 0x3fcc6d90535d74dc, 0xbfef33685a3aaef0, // 0.22209, -0.97503 + 0x3fcc3c8b8c4b9dd7, 0xbfef36306b67c556, // 0.2206, -0.97536 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcbda74f5856330, 0xbfef3bb21cc4fe47, // 0.2176, -0.97604 + 0x3fcba96334f15dad, 0xbfef3e6bbc1bbc65, // 0.21611, -0.97637 + 0x3fcb784d30536cda, 0xbfef412089fd8adc, // 0.21461, -0.9767 + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703 + 0x3fcb16147941ca2a, 0xbfef467bafb7bbe0, // 0.21161, -0.97735 + 0x3fcae4f1d5f3b9ab, 0xbfef492206bcabb4, // 0.21011, -0.97768 + 0x3fcab3cb0ce6fe44, 0xbfef4bc38aa5c694, // 0.20861, -0.978 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fca517127e3dabc, 0xbfef50f81785c6b9, // 0.20561, -0.97863 + 0x3fca203e1b1831da, 0xbfef538b1faf2d07, // 0.20411, -0.97895 + 0x3fc9ef0706e35a35, 0xbfef56195321c090, // 0.20261, -0.97926 + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957 + 0x3fc98c8ce69a7aec, 0xbfef5b273a4fa2d9, // 0.1996, -0.97988 + 0x3fc95b49e9b62af9, 0xbfef5da6ed43685d, // 0.1981, -0.98018 + 0x3fc92a0303c8194f, 0xbfef6021c9f148c2, // 0.19659, -0.98048 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc8c7699b34ca7e, 0xbfef6508fef47bd5, // 0.19359, -0.98108 + 0x3fc8961727c41804, 0xbfef677556883cee, // 0.19208, -0.98138 + 0x3fc864c0e9b2b6cf, 0xbfef69dcd652f5de, // 0.19057, -0.98167 + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196 + 0x3fc802092c1d744b, 0xbfef6e9d4d1262ca, // 0.18756, -0.98225 + 0x3fc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // 0.18606, -0.98254 + 0x3fc79f429f59e11d, 0xbfef734a60446279, // 0.18455, -0.98282 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc73c6d8055fe0a, 0xbfef77e40d068a90, // 0.18153, -0.98339 + 0x3fc70afd8d08c4ff, 0xbfef7a299c1a322a, // 0.18002, -0.98366 + 0x3fc6d98a0c08c8da, 0xbfef7c6a50826840, // 0.17851, -0.98394 + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421 + 0x3fc676987f7216b8, 0xbfef80dd27ed8204, // 0.17549, -0.98448 + 0x3fc6451a831d830d, 0xbfef830f4a40c60c, // 0.17398, -0.98475 + 0x3fc61399179a6e94, 0xbfef853c9089595e, // 0.17247, -0.98501 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc5b08c1192e381, 0xbfef898887a36c84, // 0.16945, -0.98554 + 0x3fc57f008654cbde, 0xbfef8ba737cb4b78, // 0.16794, -0.9858 + 0x3fc54d71aa74ef02, 0xbfef8dc10a95380d, // 0.16643, -0.98605 + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631 + 0x3fc4ea4a1f624b61, 0xbfef91e616c43891, // 0.1634, -0.98656 + 0x3fc4b8b17f79fa88, 0xbfef93f14f85ac08, // 0.16189, -0.98681 + 0x3fc48715ad84cdf5, 0xbfef95f7a9a1ec47, // 0.16037, -0.98706 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc423d4920e4166, 0xbfef99f5c0abd496, // 0.15734, -0.98754 + 0x3fc3f22f57db4893, 0xbfef9bed7cfbde29, // 0.15583, -0.98778 + 0x3fc3c0870a383ff6, 0xbfef9de0596b77a3, // 0.15431, -0.98802 + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826 + 0x3fc35d2d53440db2, 0xbfefa1b7717661d5, // 0.15128, -0.98849 + 0x3fc32b7bf94516a7, 0xbfefa39bac7a1791, // 0.14976, -0.98872 + 0x3fc2f9c7aa7a72af, 0xbfefa57b066e2754, // 0.14825, -0.98895 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc296564d2b953e, 0xbfefa92b1600657c, // 0.14521, -0.9894 + 0x3fc264994dfd340a, 0xbfefaafbcb0cfddc, // 0.1437, -0.98962 + 0x3fc232d978aed413, 0xbfefacc79de6c44f, // 0.14218, -0.98984 + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006 + 0x3fc1cf516a62a077, 0xbfefb0509be6f7db, // 0.13914, -0.99027 + 0x3fc19d8940be24e7, 0xbfefb20dc681d54d, // 0.13762, -0.99049 + 0x3fc16bbe5fac5865, 0xbfefb3c60dd2c199, // 0.1361, -0.9907 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc1082095f820b0, 0xbfefb727f187f1c7, // 0.13306, -0.99111 + 0x3fc0d64dbcb26786, 0xbfefb8d18d66adb7, // 0.13154, -0.99131 + 0x3fc0a4784ab8bf1d, 0xbfefba7644f068b5, // 0.13002, -0.99151 + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171 + 0x3fc040c5bb67747e, 0xbfefbdb106021816, // 0.12698, -0.99191 + 0x3fc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // 0.12545, -0.9921 + 0x3fbfba124b07ad85, 0xbfefc0d832bf043a, // 0.12393, -0.99229 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fbef2858d27561b, 0xbfefc3ebc935454c, // 0.12089, -0.99267 + 0x3fbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // 0.11937, -0.99285 + 0x3fbe2ae5b8457f77, 0xbfefc6ebc77f0887, // 0.11784, -0.99303 + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321 + 0x3fbd633347858ce4, 0xbfefc9d82bc2915e, // 0.11479, -0.99339 + 0x3fbcff533b307dc1, 0xbfefcb4703914354, // 0.11327, -0.99356 + 0x3fbc9b6eb6165c42, 0xbfefccb0f4323aa3, // 0.11175, -0.99374 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbbd3987f31fa0e, 0xbfefcf761f0c77a3, // 0.1087, -0.99407 + 0x3fbb6fa6ec38f64c, 0xbfefd0d158d86087, // 0.10717, -0.99424 + 0x3fbb0bb11e1d5559, 0xbfefd227aa9bd53b, // 0.10565, -0.9944 + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456 + 0x3fba43b90e27f3c4, 0xbfefd4c59536fae4, // 0.1026, -0.99472 + 0x3fb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // 0.10107, -0.99488 + 0x3fb97bb0caaba56f, 0xbfefd74fdd40abbf, // 0.099544, -0.99503 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fb8b398cf0c38e0, 0xbfefd9c68127c78c, // 0.09649, -0.99533 + 0x3fb84f8712c130a0, 0xbfefdafa7514538c, // 0.094963, -0.99548 + 0x3fb7eb7196b72ee4, 0xbfefdc297f674ba9, // 0.093436, -0.99563 + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577 + 0x3fb7233b9d236e71, 0xbfefde78d68653fd, // 0.090381, -0.99591 + 0x3fb6bf1b3e79b129, 0xbfefdf9922f73307, // 0.088854, -0.99604 + 0x3fb65af75dd0f87b, 0xbfefe0b485181be3, // 0.087326, -0.99618 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb592a554489bc8, 0xbfefe2dc89bbff08, // 0.084269, -0.99644 + 0x3fb52e774a4d4d0a, 0xbfefe3e92be9d886, // 0.08274, -0.99657 + 0x3fb4ca45fc1ba8b6, 0xbfefe4f0e31d7a4a, // 0.081211, -0.9967 + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682 + 0x3fb401d9d0e3a507, 0xbfefe6f18ff42c84, // 0.078153, -0.99694 + 0x3fb39d9f12c5a299, 0xbfefe7ea85482d60, // 0.076624, -0.99706 + 0x3fb339614e41ffa5, 0xbfefe8de8f03d75c, // 0.075094, -0.99718 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb270dcefdfc45b, 0xbfefeab7df1c6005, // 0.072035, -0.9974 + 0x3fb20c9674ed444c, 0xbfefeb9d2530410f, // 0.070505, -0.99751 + 0x3fb1a84d316d4f8a, 0xbfefec7d7f19cffc, // 0.068974, -0.99762 + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772 + 0x3fb0dfb28ea201e6, 0xbfefee2f6de455ba, // 0.065913, -0.99783 + 0x3fb07b614e463064, 0xbfefef0102826191, // 0.064383, -0.99793 + 0x3fb0170d833bf421, 0xbfefefcdaa704562, // 0.062852, -0.99802 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fae9cbd15ff5527, 0xbfeff15833be1965, // 0.05979, -0.99821 + 0x3fadd406f9808ec8, 0xbfeff21614e131ed, // 0.058258, -0.9983 + 0x3fad0b4c436f91d0, 0xbfeff2cf08da7321, // 0.056727, -0.99839 + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848 + 0x3fab79c986698b78, 0xbfeff43228de1b77, // 0.053664, -0.99856 + 0x3faab101bd5f8317, 0xbfeff4dc54b1bed3, // 0.052132, -0.99864 + 0x3fa9e835d6993c87, 0xbfeff58192ee0358, // 0.0506, -0.99872 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3fa856922bb513c1, 0xbfeff6bd463b444d, // 0.047535, -0.99887 + 0x3fa78dbaa5874685, 0xbfeff753bb1b9164, // 0.046003, -0.99894 + 0x3fa6c4df7d7d5b84, 0xbfeff7e5420320f9, // 0.044471, -0.99901 + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908 + 0x3fa5331ec3bba0eb, 0xbfeff8f9858f058b, // 0.041406, -0.99914 + 0x3fa46a396ff86179, 0xbfeff97c4208c014, // 0.039873, -0.9992 + 0x3fa3a150f6421afc, 0xbfeff9fa10348837, // 0.03834, -0.99926 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa20f770ceb11c6, 0xbfeffae6e1556998, // 0.035274, -0.99938 + 0x3fa14685db42c17e, 0xbfeffb55e425fdae, // 0.033741, -0.99943 + 0x3fa07d91ff984580, 0xbfeffbbff85f9515, // 0.032208, -0.99948 + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953 + 0x3f9dd7458c64ab39, 0xbfeffc8554cd213a, // 0.029142, -0.99958 + 0x3f9c454f4ce53b1c, 0xbfeffce09ce2a679, // 0.027608, -0.99962 + 0x3f9ab354b1504fca, 0xbfeffd36f624500c, // 0.026075, -0.99966 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3f978f535ddc9f03, 0xbfeffdd4dbf78f52, // 0.023008, -0.99974 + 0x3f95fd4d21fab226, 0xbfeffe1c6870cb77, // 0.021474, -0.99977 + 0x3f946b4381fce81c, 0xbfeffe5f05e578db, // 0.01994, -0.9998 + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983 + 0x3f9147270dad7132, 0xbfeffed57398d2b7, // 0.016873, -0.99986 + 0x3f8f6a296ab997ca, 0xbfefff0943c53bd1, // 0.015339, -0.99988 + 0x3f8c45ffe1e48ad9, 0xbfefff3824c88f6f, // 0.013805, -0.9999 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f85fda037ac05e0, 0xbfefff871937ce2f, // 0.010738, -0.99994 + 0x3f82d96b0e509703, 0xbfefffa72c978c4f, //0.0092038, -0.99996 + 0x3f7f6a65f9a2a3c5, 0xbfefffc250b5daef, //0.0076698, -0.99997 + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, //0.0061359, -0.99998 + 0x3f72d97822f996bc, 0xbfefffe9cb1e2e8d, //0.0046019, -0.99999 + 0x3f6921f8becca4ba, 0xbfeffff621621d02, // 0.003068, -1 + 0x3f5921faaee6472d, 0xbfeffffd88586ee6, // 0.001534, -1 +}; + +#endif + + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32) +/** + @par + Example code for Floating-point RFFT Twiddle factors Generation: + @par +
TW = exp(pi/2*i-2*pi*i*[0:L/2-1]/L).' 
+ @par + Real and Imag values are in interleaved fashion +*/ +const float32_t twiddleCoef_rfft_32[32] = { + 0.000000000f, 1.000000000f, + 0.195090322f, 0.980785280f, + 0.382683432f, 0.923879533f, + 0.555570233f, 0.831469612f, + 0.707106781f, 0.707106781f, + 0.831469612f, 0.555570233f, + 0.923879533f, 0.382683432f, + 0.980785280f, 0.195090322f, + 1.000000000f, 0.000000000f, + 0.980785280f, -0.195090322f, + 0.923879533f, -0.382683432f, + 0.831469612f, -0.555570233f, + 0.707106781f, -0.707106781f, + 0.555570233f, -0.831469612f, + 0.382683432f, -0.923879533f, + 0.195090322f, -0.980785280f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64) +const float32_t twiddleCoef_rfft_64[64] = { + 0.000000000000000f, 1.000000000000000f, + 0.098017140329561f, 0.995184726672197f, + 0.195090322016128f, 0.980785280403230f, + 0.290284677254462f, 0.956940335732209f, + 0.382683432365090f, 0.923879532511287f, + 0.471396736825998f, 0.881921264348355f, + 0.555570233019602f, 0.831469612302545f, + 0.634393284163645f, 0.773010453362737f, + 0.707106781186547f, 0.707106781186548f, + 0.773010453362737f, 0.634393284163645f, + 0.831469612302545f, 0.555570233019602f, + 0.881921264348355f, 0.471396736825998f, + 0.923879532511287f, 0.382683432365090f, + 0.956940335732209f, 0.290284677254462f, + 0.980785280403230f, 0.195090322016128f, + 0.995184726672197f, 0.098017140329561f, + 1.000000000000000f, 0.000000000000000f, + 0.995184726672197f, -0.098017140329561f, + 0.980785280403230f, -0.195090322016128f, + 0.956940335732209f, -0.290284677254462f, + 0.923879532511287f, -0.382683432365090f, + 0.881921264348355f, -0.471396736825998f, + 0.831469612302545f, -0.555570233019602f, + 0.773010453362737f, -0.634393284163645f, + 0.707106781186548f, -0.707106781186547f, + 0.634393284163645f, -0.773010453362737f, + 0.555570233019602f, -0.831469612302545f, + 0.471396736825998f, -0.881921264348355f, + 0.382683432365090f, -0.923879532511287f, + 0.290284677254462f, -0.956940335732209f, + 0.195090322016129f, -0.980785280403230f, + 0.098017140329561f, -0.995184726672197f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128) +const float32_t twiddleCoef_rfft_128[128] = { + 0.000000000f, 1.000000000f, + 0.049067674f, 0.998795456f, + 0.098017140f, 0.995184727f, + 0.146730474f, 0.989176510f, + 0.195090322f, 0.980785280f, + 0.242980180f, 0.970031253f, + 0.290284677f, 0.956940336f, + 0.336889853f, 0.941544065f, + 0.382683432f, 0.923879533f, + 0.427555093f, 0.903989293f, + 0.471396737f, 0.881921264f, + 0.514102744f, 0.857728610f, + 0.555570233f, 0.831469612f, + 0.595699304f, 0.803207531f, + 0.634393284f, 0.773010453f, + 0.671558955f, 0.740951125f, + 0.707106781f, 0.707106781f, + 0.740951125f, 0.671558955f, + 0.773010453f, 0.634393284f, + 0.803207531f, 0.595699304f, + 0.831469612f, 0.555570233f, + 0.857728610f, 0.514102744f, + 0.881921264f, 0.471396737f, + 0.903989293f, 0.427555093f, + 0.923879533f, 0.382683432f, + 0.941544065f, 0.336889853f, + 0.956940336f, 0.290284677f, + 0.970031253f, 0.242980180f, + 0.980785280f, 0.195090322f, + 0.989176510f, 0.146730474f, + 0.995184727f, 0.098017140f, + 0.998795456f, 0.049067674f, + 1.000000000f, 0.000000000f, + 0.998795456f, -0.049067674f, + 0.995184727f, -0.098017140f, + 0.989176510f, -0.146730474f, + 0.980785280f, -0.195090322f, + 0.970031253f, -0.242980180f, + 0.956940336f, -0.290284677f, + 0.941544065f, -0.336889853f, + 0.923879533f, -0.382683432f, + 0.903989293f, -0.427555093f, + 0.881921264f, -0.471396737f, + 0.857728610f, -0.514102744f, + 0.831469612f, -0.555570233f, + 0.803207531f, -0.595699304f, + 0.773010453f, -0.634393284f, + 0.740951125f, -0.671558955f, + 0.707106781f, -0.707106781f, + 0.671558955f, -0.740951125f, + 0.634393284f, -0.773010453f, + 0.595699304f, -0.803207531f, + 0.555570233f, -0.831469612f, + 0.514102744f, -0.857728610f, + 0.471396737f, -0.881921264f, + 0.427555093f, -0.903989293f, + 0.382683432f, -0.923879533f, + 0.336889853f, -0.941544065f, + 0.290284677f, -0.956940336f, + 0.242980180f, -0.970031253f, + 0.195090322f, -0.980785280f, + 0.146730474f, -0.989176510f, + 0.098017140f, -0.995184727f, + 0.049067674f, -0.998795456f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256) +const float32_t twiddleCoef_rfft_256[256] = { + 0.000000000f, 1.000000000f, + 0.024541229f, 0.999698819f, + 0.049067674f, 0.998795456f, + 0.073564564f, 0.997290457f, + 0.098017140f, 0.995184727f, + 0.122410675f, 0.992479535f, + 0.146730474f, 0.989176510f, + 0.170961889f, 0.985277642f, + 0.195090322f, 0.980785280f, + 0.219101240f, 0.975702130f, + 0.242980180f, 0.970031253f, + 0.266712757f, 0.963776066f, + 0.290284677f, 0.956940336f, + 0.313681740f, 0.949528181f, + 0.336889853f, 0.941544065f, + 0.359895037f, 0.932992799f, + 0.382683432f, 0.923879533f, + 0.405241314f, 0.914209756f, + 0.427555093f, 0.903989293f, + 0.449611330f, 0.893224301f, + 0.471396737f, 0.881921264f, + 0.492898192f, 0.870086991f, + 0.514102744f, 0.857728610f, + 0.534997620f, 0.844853565f, + 0.555570233f, 0.831469612f, + 0.575808191f, 0.817584813f, + 0.595699304f, 0.803207531f, + 0.615231591f, 0.788346428f, + 0.634393284f, 0.773010453f, + 0.653172843f, 0.757208847f, + 0.671558955f, 0.740951125f, + 0.689540545f, 0.724247083f, + 0.707106781f, 0.707106781f, + 0.724247083f, 0.689540545f, + 0.740951125f, 0.671558955f, + 0.757208847f, 0.653172843f, + 0.773010453f, 0.634393284f, + 0.788346428f, 0.615231591f, + 0.803207531f, 0.595699304f, + 0.817584813f, 0.575808191f, + 0.831469612f, 0.555570233f, + 0.844853565f, 0.534997620f, + 0.857728610f, 0.514102744f, + 0.870086991f, 0.492898192f, + 0.881921264f, 0.471396737f, + 0.893224301f, 0.449611330f, + 0.903989293f, 0.427555093f, + 0.914209756f, 0.405241314f, + 0.923879533f, 0.382683432f, + 0.932992799f, 0.359895037f, + 0.941544065f, 0.336889853f, + 0.949528181f, 0.313681740f, + 0.956940336f, 0.290284677f, + 0.963776066f, 0.266712757f, + 0.970031253f, 0.242980180f, + 0.975702130f, 0.219101240f, + 0.980785280f, 0.195090322f, + 0.985277642f, 0.170961889f, + 0.989176510f, 0.146730474f, + 0.992479535f, 0.122410675f, + 0.995184727f, 0.098017140f, + 0.997290457f, 0.073564564f, + 0.998795456f, 0.049067674f, + 0.999698819f, 0.024541229f, + 1.000000000f, 0.000000000f, + 0.999698819f, -0.024541229f, + 0.998795456f, -0.049067674f, + 0.997290457f, -0.073564564f, + 0.995184727f, -0.098017140f, + 0.992479535f, -0.122410675f, + 0.989176510f, -0.146730474f, + 0.985277642f, -0.170961889f, + 0.980785280f, -0.195090322f, + 0.975702130f, -0.219101240f, + 0.970031253f, -0.242980180f, + 0.963776066f, -0.266712757f, + 0.956940336f, -0.290284677f, + 0.949528181f, -0.313681740f, + 0.941544065f, -0.336889853f, + 0.932992799f, -0.359895037f, + 0.923879533f, -0.382683432f, + 0.914209756f, -0.405241314f, + 0.903989293f, -0.427555093f, + 0.893224301f, -0.449611330f, + 0.881921264f, -0.471396737f, + 0.870086991f, -0.492898192f, + 0.857728610f, -0.514102744f, + 0.844853565f, -0.534997620f, + 0.831469612f, -0.555570233f, + 0.817584813f, -0.575808191f, + 0.803207531f, -0.595699304f, + 0.788346428f, -0.615231591f, + 0.773010453f, -0.634393284f, + 0.757208847f, -0.653172843f, + 0.740951125f, -0.671558955f, + 0.724247083f, -0.689540545f, + 0.707106781f, -0.707106781f, + 0.689540545f, -0.724247083f, + 0.671558955f, -0.740951125f, + 0.653172843f, -0.757208847f, + 0.634393284f, -0.773010453f, + 0.615231591f, -0.788346428f, + 0.595699304f, -0.803207531f, + 0.575808191f, -0.817584813f, + 0.555570233f, -0.831469612f, + 0.534997620f, -0.844853565f, + 0.514102744f, -0.857728610f, + 0.492898192f, -0.870086991f, + 0.471396737f, -0.881921264f, + 0.449611330f, -0.893224301f, + 0.427555093f, -0.903989293f, + 0.405241314f, -0.914209756f, + 0.382683432f, -0.923879533f, + 0.359895037f, -0.932992799f, + 0.336889853f, -0.941544065f, + 0.313681740f, -0.949528181f, + 0.290284677f, -0.956940336f, + 0.266712757f, -0.963776066f, + 0.242980180f, -0.970031253f, + 0.219101240f, -0.975702130f, + 0.195090322f, -0.980785280f, + 0.170961889f, -0.985277642f, + 0.146730474f, -0.989176510f, + 0.122410675f, -0.992479535f, + 0.098017140f, -0.995184727f, + 0.073564564f, -0.997290457f, + 0.049067674f, -0.998795456f, + 0.024541229f, -0.999698819f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512) +const float32_t twiddleCoef_rfft_512[512] = { + 0.000000000f, 1.000000000f, + 0.012271538f, 0.999924702f, + 0.024541229f, 0.999698819f, + 0.036807223f, 0.999322385f, + 0.049067674f, 0.998795456f, + 0.061320736f, 0.998118113f, + 0.073564564f, 0.997290457f, + 0.085797312f, 0.996312612f, + 0.098017140f, 0.995184727f, + 0.110222207f, 0.993906970f, + 0.122410675f, 0.992479535f, + 0.134580709f, 0.990902635f, + 0.146730474f, 0.989176510f, + 0.158858143f, 0.987301418f, + 0.170961889f, 0.985277642f, + 0.183039888f, 0.983105487f, + 0.195090322f, 0.980785280f, + 0.207111376f, 0.978317371f, + 0.219101240f, 0.975702130f, + 0.231058108f, 0.972939952f, + 0.242980180f, 0.970031253f, + 0.254865660f, 0.966976471f, + 0.266712757f, 0.963776066f, + 0.278519689f, 0.960430519f, + 0.290284677f, 0.956940336f, + 0.302005949f, 0.953306040f, + 0.313681740f, 0.949528181f, + 0.325310292f, 0.945607325f, + 0.336889853f, 0.941544065f, + 0.348418680f, 0.937339012f, + 0.359895037f, 0.932992799f, + 0.371317194f, 0.928506080f, + 0.382683432f, 0.923879533f, + 0.393992040f, 0.919113852f, + 0.405241314f, 0.914209756f, + 0.416429560f, 0.909167983f, + 0.427555093f, 0.903989293f, + 0.438616239f, 0.898674466f, + 0.449611330f, 0.893224301f, + 0.460538711f, 0.887639620f, + 0.471396737f, 0.881921264f, + 0.482183772f, 0.876070094f, + 0.492898192f, 0.870086991f, + 0.503538384f, 0.863972856f, + 0.514102744f, 0.857728610f, + 0.524589683f, 0.851355193f, + 0.534997620f, 0.844853565f, + 0.545324988f, 0.838224706f, + 0.555570233f, 0.831469612f, + 0.565731811f, 0.824589303f, + 0.575808191f, 0.817584813f, + 0.585797857f, 0.810457198f, + 0.595699304f, 0.803207531f, + 0.605511041f, 0.795836905f, + 0.615231591f, 0.788346428f, + 0.624859488f, 0.780737229f, + 0.634393284f, 0.773010453f, + 0.643831543f, 0.765167266f, + 0.653172843f, 0.757208847f, + 0.662415778f, 0.749136395f, + 0.671558955f, 0.740951125f, + 0.680600998f, 0.732654272f, + 0.689540545f, 0.724247083f, + 0.698376249f, 0.715730825f, + 0.707106781f, 0.707106781f, + 0.715730825f, 0.698376249f, + 0.724247083f, 0.689540545f, + 0.732654272f, 0.680600998f, + 0.740951125f, 0.671558955f, + 0.749136395f, 0.662415778f, + 0.757208847f, 0.653172843f, + 0.765167266f, 0.643831543f, + 0.773010453f, 0.634393284f, + 0.780737229f, 0.624859488f, + 0.788346428f, 0.615231591f, + 0.795836905f, 0.605511041f, + 0.803207531f, 0.595699304f, + 0.810457198f, 0.585797857f, + 0.817584813f, 0.575808191f, + 0.824589303f, 0.565731811f, + 0.831469612f, 0.555570233f, + 0.838224706f, 0.545324988f, + 0.844853565f, 0.534997620f, + 0.851355193f, 0.524589683f, + 0.857728610f, 0.514102744f, + 0.863972856f, 0.503538384f, + 0.870086991f, 0.492898192f, + 0.876070094f, 0.482183772f, + 0.881921264f, 0.471396737f, + 0.887639620f, 0.460538711f, + 0.893224301f, 0.449611330f, + 0.898674466f, 0.438616239f, + 0.903989293f, 0.427555093f, + 0.909167983f, 0.416429560f, + 0.914209756f, 0.405241314f, + 0.919113852f, 0.393992040f, + 0.923879533f, 0.382683432f, + 0.928506080f, 0.371317194f, + 0.932992799f, 0.359895037f, + 0.937339012f, 0.348418680f, + 0.941544065f, 0.336889853f, + 0.945607325f, 0.325310292f, + 0.949528181f, 0.313681740f, + 0.953306040f, 0.302005949f, + 0.956940336f, 0.290284677f, + 0.960430519f, 0.278519689f, + 0.963776066f, 0.266712757f, + 0.966976471f, 0.254865660f, + 0.970031253f, 0.242980180f, + 0.972939952f, 0.231058108f, + 0.975702130f, 0.219101240f, + 0.978317371f, 0.207111376f, + 0.980785280f, 0.195090322f, + 0.983105487f, 0.183039888f, + 0.985277642f, 0.170961889f, + 0.987301418f, 0.158858143f, + 0.989176510f, 0.146730474f, + 0.990902635f, 0.134580709f, + 0.992479535f, 0.122410675f, + 0.993906970f, 0.110222207f, + 0.995184727f, 0.098017140f, + 0.996312612f, 0.085797312f, + 0.997290457f, 0.073564564f, + 0.998118113f, 0.061320736f, + 0.998795456f, 0.049067674f, + 0.999322385f, 0.036807223f, + 0.999698819f, 0.024541229f, + 0.999924702f, 0.012271538f, + 1.000000000f, 0.000000000f, + 0.999924702f, -0.012271538f, + 0.999698819f, -0.024541229f, + 0.999322385f, -0.036807223f, + 0.998795456f, -0.049067674f, + 0.998118113f, -0.061320736f, + 0.997290457f, -0.073564564f, + 0.996312612f, -0.085797312f, + 0.995184727f, -0.098017140f, + 0.993906970f, -0.110222207f, + 0.992479535f, -0.122410675f, + 0.990902635f, -0.134580709f, + 0.989176510f, -0.146730474f, + 0.987301418f, -0.158858143f, + 0.985277642f, -0.170961889f, + 0.983105487f, -0.183039888f, + 0.980785280f, -0.195090322f, + 0.978317371f, -0.207111376f, + 0.975702130f, -0.219101240f, + 0.972939952f, -0.231058108f, + 0.970031253f, -0.242980180f, + 0.966976471f, -0.254865660f, + 0.963776066f, -0.266712757f, + 0.960430519f, -0.278519689f, + 0.956940336f, -0.290284677f, + 0.953306040f, -0.302005949f, + 0.949528181f, -0.313681740f, + 0.945607325f, -0.325310292f, + 0.941544065f, -0.336889853f, + 0.937339012f, -0.348418680f, + 0.932992799f, -0.359895037f, + 0.928506080f, -0.371317194f, + 0.923879533f, -0.382683432f, + 0.919113852f, -0.393992040f, + 0.914209756f, -0.405241314f, + 0.909167983f, -0.416429560f, + 0.903989293f, -0.427555093f, + 0.898674466f, -0.438616239f, + 0.893224301f, -0.449611330f, + 0.887639620f, -0.460538711f, + 0.881921264f, -0.471396737f, + 0.876070094f, -0.482183772f, + 0.870086991f, -0.492898192f, + 0.863972856f, -0.503538384f, + 0.857728610f, -0.514102744f, + 0.851355193f, -0.524589683f, + 0.844853565f, -0.534997620f, + 0.838224706f, -0.545324988f, + 0.831469612f, -0.555570233f, + 0.824589303f, -0.565731811f, + 0.817584813f, -0.575808191f, + 0.810457198f, -0.585797857f, + 0.803207531f, -0.595699304f, + 0.795836905f, -0.605511041f, + 0.788346428f, -0.615231591f, + 0.780737229f, -0.624859488f, + 0.773010453f, -0.634393284f, + 0.765167266f, -0.643831543f, + 0.757208847f, -0.653172843f, + 0.749136395f, -0.662415778f, + 0.740951125f, -0.671558955f, + 0.732654272f, -0.680600998f, + 0.724247083f, -0.689540545f, + 0.715730825f, -0.698376249f, + 0.707106781f, -0.707106781f, + 0.698376249f, -0.715730825f, + 0.689540545f, -0.724247083f, + 0.680600998f, -0.732654272f, + 0.671558955f, -0.740951125f, + 0.662415778f, -0.749136395f, + 0.653172843f, -0.757208847f, + 0.643831543f, -0.765167266f, + 0.634393284f, -0.773010453f, + 0.624859488f, -0.780737229f, + 0.615231591f, -0.788346428f, + 0.605511041f, -0.795836905f, + 0.595699304f, -0.803207531f, + 0.585797857f, -0.810457198f, + 0.575808191f, -0.817584813f, + 0.565731811f, -0.824589303f, + 0.555570233f, -0.831469612f, + 0.545324988f, -0.838224706f, + 0.534997620f, -0.844853565f, + 0.524589683f, -0.851355193f, + 0.514102744f, -0.857728610f, + 0.503538384f, -0.863972856f, + 0.492898192f, -0.870086991f, + 0.482183772f, -0.876070094f, + 0.471396737f, -0.881921264f, + 0.460538711f, -0.887639620f, + 0.449611330f, -0.893224301f, + 0.438616239f, -0.898674466f, + 0.427555093f, -0.903989293f, + 0.416429560f, -0.909167983f, + 0.405241314f, -0.914209756f, + 0.393992040f, -0.919113852f, + 0.382683432f, -0.923879533f, + 0.371317194f, -0.928506080f, + 0.359895037f, -0.932992799f, + 0.348418680f, -0.937339012f, + 0.336889853f, -0.941544065f, + 0.325310292f, -0.945607325f, + 0.313681740f, -0.949528181f, + 0.302005949f, -0.953306040f, + 0.290284677f, -0.956940336f, + 0.278519689f, -0.960430519f, + 0.266712757f, -0.963776066f, + 0.254865660f, -0.966976471f, + 0.242980180f, -0.970031253f, + 0.231058108f, -0.972939952f, + 0.219101240f, -0.975702130f, + 0.207111376f, -0.978317371f, + 0.195090322f, -0.980785280f, + 0.183039888f, -0.983105487f, + 0.170961889f, -0.985277642f, + 0.158858143f, -0.987301418f, + 0.146730474f, -0.989176510f, + 0.134580709f, -0.990902635f, + 0.122410675f, -0.992479535f, + 0.110222207f, -0.993906970f, + 0.098017140f, -0.995184727f, + 0.085797312f, -0.996312612f, + 0.073564564f, -0.997290457f, + 0.061320736f, -0.998118113f, + 0.049067674f, -0.998795456f, + 0.036807223f, -0.999322385f, + 0.024541229f, -0.999698819f, + 0.012271538f, -0.999924702f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024) +const float32_t twiddleCoef_rfft_1024[1024] = { + 0.000000000f, 1.000000000f, + 0.006135885f, 0.999981175f, + 0.012271538f, 0.999924702f, + 0.018406730f, 0.999830582f, + 0.024541229f, 0.999698819f, + 0.030674803f, 0.999529418f, + 0.036807223f, 0.999322385f, + 0.042938257f, 0.999077728f, + 0.049067674f, 0.998795456f, + 0.055195244f, 0.998475581f, + 0.061320736f, 0.998118113f, + 0.067443920f, 0.997723067f, + 0.073564564f, 0.997290457f, + 0.079682438f, 0.996820299f, + 0.085797312f, 0.996312612f, + 0.091908956f, 0.995767414f, + 0.098017140f, 0.995184727f, + 0.104121634f, 0.994564571f, + 0.110222207f, 0.993906970f, + 0.116318631f, 0.993211949f, + 0.122410675f, 0.992479535f, + 0.128498111f, 0.991709754f, + 0.134580709f, 0.990902635f, + 0.140658239f, 0.990058210f, + 0.146730474f, 0.989176510f, + 0.152797185f, 0.988257568f, + 0.158858143f, 0.987301418f, + 0.164913120f, 0.986308097f, + 0.170961889f, 0.985277642f, + 0.177004220f, 0.984210092f, + 0.183039888f, 0.983105487f, + 0.189068664f, 0.981963869f, + 0.195090322f, 0.980785280f, + 0.201104635f, 0.979569766f, + 0.207111376f, 0.978317371f, + 0.213110320f, 0.977028143f, + 0.219101240f, 0.975702130f, + 0.225083911f, 0.974339383f, + 0.231058108f, 0.972939952f, + 0.237023606f, 0.971503891f, + 0.242980180f, 0.970031253f, + 0.248927606f, 0.968522094f, + 0.254865660f, 0.966976471f, + 0.260794118f, 0.965394442f, + 0.266712757f, 0.963776066f, + 0.272621355f, 0.962121404f, + 0.278519689f, 0.960430519f, + 0.284407537f, 0.958703475f, + 0.290284677f, 0.956940336f, + 0.296150888f, 0.955141168f, + 0.302005949f, 0.953306040f, + 0.307849640f, 0.951435021f, + 0.313681740f, 0.949528181f, + 0.319502031f, 0.947585591f, + 0.325310292f, 0.945607325f, + 0.331106306f, 0.943593458f, + 0.336889853f, 0.941544065f, + 0.342660717f, 0.939459224f, + 0.348418680f, 0.937339012f, + 0.354163525f, 0.935183510f, + 0.359895037f, 0.932992799f, + 0.365612998f, 0.930766961f, + 0.371317194f, 0.928506080f, + 0.377007410f, 0.926210242f, + 0.382683432f, 0.923879533f, + 0.388345047f, 0.921514039f, + 0.393992040f, 0.919113852f, + 0.399624200f, 0.916679060f, + 0.405241314f, 0.914209756f, + 0.410843171f, 0.911706032f, + 0.416429560f, 0.909167983f, + 0.422000271f, 0.906595705f, + 0.427555093f, 0.903989293f, + 0.433093819f, 0.901348847f, + 0.438616239f, 0.898674466f, + 0.444122145f, 0.895966250f, + 0.449611330f, 0.893224301f, + 0.455083587f, 0.890448723f, + 0.460538711f, 0.887639620f, + 0.465976496f, 0.884797098f, + 0.471396737f, 0.881921264f, + 0.476799230f, 0.879012226f, + 0.482183772f, 0.876070094f, + 0.487550160f, 0.873094978f, + 0.492898192f, 0.870086991f, + 0.498227667f, 0.867046246f, + 0.503538384f, 0.863972856f, + 0.508830143f, 0.860866939f, + 0.514102744f, 0.857728610f, + 0.519355990f, 0.854557988f, + 0.524589683f, 0.851355193f, + 0.529803625f, 0.848120345f, + 0.534997620f, 0.844853565f, + 0.540171473f, 0.841554977f, + 0.545324988f, 0.838224706f, + 0.550457973f, 0.834862875f, + 0.555570233f, 0.831469612f, + 0.560661576f, 0.828045045f, + 0.565731811f, 0.824589303f, + 0.570780746f, 0.821102515f, + 0.575808191f, 0.817584813f, + 0.580813958f, 0.814036330f, + 0.585797857f, 0.810457198f, + 0.590759702f, 0.806847554f, + 0.595699304f, 0.803207531f, + 0.600616479f, 0.799537269f, + 0.605511041f, 0.795836905f, + 0.610382806f, 0.792106577f, + 0.615231591f, 0.788346428f, + 0.620057212f, 0.784556597f, + 0.624859488f, 0.780737229f, + 0.629638239f, 0.776888466f, + 0.634393284f, 0.773010453f, + 0.639124445f, 0.769103338f, + 0.643831543f, 0.765167266f, + 0.648514401f, 0.761202385f, + 0.653172843f, 0.757208847f, + 0.657806693f, 0.753186799f, + 0.662415778f, 0.749136395f, + 0.666999922f, 0.745057785f, + 0.671558955f, 0.740951125f, + 0.676092704f, 0.736816569f, + 0.680600998f, 0.732654272f, + 0.685083668f, 0.728464390f, + 0.689540545f, 0.724247083f, + 0.693971461f, 0.720002508f, + 0.698376249f, 0.715730825f, + 0.702754744f, 0.711432196f, + 0.707106781f, 0.707106781f, + 0.711432196f, 0.702754744f, + 0.715730825f, 0.698376249f, + 0.720002508f, 0.693971461f, + 0.724247083f, 0.689540545f, + 0.728464390f, 0.685083668f, + 0.732654272f, 0.680600998f, + 0.736816569f, 0.676092704f, + 0.740951125f, 0.671558955f, + 0.745057785f, 0.666999922f, + 0.749136395f, 0.662415778f, + 0.753186799f, 0.657806693f, + 0.757208847f, 0.653172843f, + 0.761202385f, 0.648514401f, + 0.765167266f, 0.643831543f, + 0.769103338f, 0.639124445f, + 0.773010453f, 0.634393284f, + 0.776888466f, 0.629638239f, + 0.780737229f, 0.624859488f, + 0.784556597f, 0.620057212f, + 0.788346428f, 0.615231591f, + 0.792106577f, 0.610382806f, + 0.795836905f, 0.605511041f, + 0.799537269f, 0.600616479f, + 0.803207531f, 0.595699304f, + 0.806847554f, 0.590759702f, + 0.810457198f, 0.585797857f, + 0.814036330f, 0.580813958f, + 0.817584813f, 0.575808191f, + 0.821102515f, 0.570780746f, + 0.824589303f, 0.565731811f, + 0.828045045f, 0.560661576f, + 0.831469612f, 0.555570233f, + 0.834862875f, 0.550457973f, + 0.838224706f, 0.545324988f, + 0.841554977f, 0.540171473f, + 0.844853565f, 0.534997620f, + 0.848120345f, 0.529803625f, + 0.851355193f, 0.524589683f, + 0.854557988f, 0.519355990f, + 0.857728610f, 0.514102744f, + 0.860866939f, 0.508830143f, + 0.863972856f, 0.503538384f, + 0.867046246f, 0.498227667f, + 0.870086991f, 0.492898192f, + 0.873094978f, 0.487550160f, + 0.876070094f, 0.482183772f, + 0.879012226f, 0.476799230f, + 0.881921264f, 0.471396737f, + 0.884797098f, 0.465976496f, + 0.887639620f, 0.460538711f, + 0.890448723f, 0.455083587f, + 0.893224301f, 0.449611330f, + 0.895966250f, 0.444122145f, + 0.898674466f, 0.438616239f, + 0.901348847f, 0.433093819f, + 0.903989293f, 0.427555093f, + 0.906595705f, 0.422000271f, + 0.909167983f, 0.416429560f, + 0.911706032f, 0.410843171f, + 0.914209756f, 0.405241314f, + 0.916679060f, 0.399624200f, + 0.919113852f, 0.393992040f, + 0.921514039f, 0.388345047f, + 0.923879533f, 0.382683432f, + 0.926210242f, 0.377007410f, + 0.928506080f, 0.371317194f, + 0.930766961f, 0.365612998f, + 0.932992799f, 0.359895037f, + 0.935183510f, 0.354163525f, + 0.937339012f, 0.348418680f, + 0.939459224f, 0.342660717f, + 0.941544065f, 0.336889853f, + 0.943593458f, 0.331106306f, + 0.945607325f, 0.325310292f, + 0.947585591f, 0.319502031f, + 0.949528181f, 0.313681740f, + 0.951435021f, 0.307849640f, + 0.953306040f, 0.302005949f, + 0.955141168f, 0.296150888f, + 0.956940336f, 0.290284677f, + 0.958703475f, 0.284407537f, + 0.960430519f, 0.278519689f, + 0.962121404f, 0.272621355f, + 0.963776066f, 0.266712757f, + 0.965394442f, 0.260794118f, + 0.966976471f, 0.254865660f, + 0.968522094f, 0.248927606f, + 0.970031253f, 0.242980180f, + 0.971503891f, 0.237023606f, + 0.972939952f, 0.231058108f, + 0.974339383f, 0.225083911f, + 0.975702130f, 0.219101240f, + 0.977028143f, 0.213110320f, + 0.978317371f, 0.207111376f, + 0.979569766f, 0.201104635f, + 0.980785280f, 0.195090322f, + 0.981963869f, 0.189068664f, + 0.983105487f, 0.183039888f, + 0.984210092f, 0.177004220f, + 0.985277642f, 0.170961889f, + 0.986308097f, 0.164913120f, + 0.987301418f, 0.158858143f, + 0.988257568f, 0.152797185f, + 0.989176510f, 0.146730474f, + 0.990058210f, 0.140658239f, + 0.990902635f, 0.134580709f, + 0.991709754f, 0.128498111f, + 0.992479535f, 0.122410675f, + 0.993211949f, 0.116318631f, + 0.993906970f, 0.110222207f, + 0.994564571f, 0.104121634f, + 0.995184727f, 0.098017140f, + 0.995767414f, 0.091908956f, + 0.996312612f, 0.085797312f, + 0.996820299f, 0.079682438f, + 0.997290457f, 0.073564564f, + 0.997723067f, 0.067443920f, + 0.998118113f, 0.061320736f, + 0.998475581f, 0.055195244f, + 0.998795456f, 0.049067674f, + 0.999077728f, 0.042938257f, + 0.999322385f, 0.036807223f, + 0.999529418f, 0.030674803f, + 0.999698819f, 0.024541229f, + 0.999830582f, 0.018406730f, + 0.999924702f, 0.012271538f, + 0.999981175f, 0.006135885f, + 1.000000000f, 0.000000000f, + 0.999981175f, -0.006135885f, + 0.999924702f, -0.012271538f, + 0.999830582f, -0.018406730f, + 0.999698819f, -0.024541229f, + 0.999529418f, -0.030674803f, + 0.999322385f, -0.036807223f, + 0.999077728f, -0.042938257f, + 0.998795456f, -0.049067674f, + 0.998475581f, -0.055195244f, + 0.998118113f, -0.061320736f, + 0.997723067f, -0.067443920f, + 0.997290457f, -0.073564564f, + 0.996820299f, -0.079682438f, + 0.996312612f, -0.085797312f, + 0.995767414f, -0.091908956f, + 0.995184727f, -0.098017140f, + 0.994564571f, -0.104121634f, + 0.993906970f, -0.110222207f, + 0.993211949f, -0.116318631f, + 0.992479535f, -0.122410675f, + 0.991709754f, -0.128498111f, + 0.990902635f, -0.134580709f, + 0.990058210f, -0.140658239f, + 0.989176510f, -0.146730474f, + 0.988257568f, -0.152797185f, + 0.987301418f, -0.158858143f, + 0.986308097f, -0.164913120f, + 0.985277642f, -0.170961889f, + 0.984210092f, -0.177004220f, + 0.983105487f, -0.183039888f, + 0.981963869f, -0.189068664f, + 0.980785280f, -0.195090322f, + 0.979569766f, -0.201104635f, + 0.978317371f, -0.207111376f, + 0.977028143f, -0.213110320f, + 0.975702130f, -0.219101240f, + 0.974339383f, -0.225083911f, + 0.972939952f, -0.231058108f, + 0.971503891f, -0.237023606f, + 0.970031253f, -0.242980180f, + 0.968522094f, -0.248927606f, + 0.966976471f, -0.254865660f, + 0.965394442f, -0.260794118f, + 0.963776066f, -0.266712757f, + 0.962121404f, -0.272621355f, + 0.960430519f, -0.278519689f, + 0.958703475f, -0.284407537f, + 0.956940336f, -0.290284677f, + 0.955141168f, -0.296150888f, + 0.953306040f, -0.302005949f, + 0.951435021f, -0.307849640f, + 0.949528181f, -0.313681740f, + 0.947585591f, -0.319502031f, + 0.945607325f, -0.325310292f, + 0.943593458f, -0.331106306f, + 0.941544065f, -0.336889853f, + 0.939459224f, -0.342660717f, + 0.937339012f, -0.348418680f, + 0.935183510f, -0.354163525f, + 0.932992799f, -0.359895037f, + 0.930766961f, -0.365612998f, + 0.928506080f, -0.371317194f, + 0.926210242f, -0.377007410f, + 0.923879533f, -0.382683432f, + 0.921514039f, -0.388345047f, + 0.919113852f, -0.393992040f, + 0.916679060f, -0.399624200f, + 0.914209756f, -0.405241314f, + 0.911706032f, -0.410843171f, + 0.909167983f, -0.416429560f, + 0.906595705f, -0.422000271f, + 0.903989293f, -0.427555093f, + 0.901348847f, -0.433093819f, + 0.898674466f, -0.438616239f, + 0.895966250f, -0.444122145f, + 0.893224301f, -0.449611330f, + 0.890448723f, -0.455083587f, + 0.887639620f, -0.460538711f, + 0.884797098f, -0.465976496f, + 0.881921264f, -0.471396737f, + 0.879012226f, -0.476799230f, + 0.876070094f, -0.482183772f, + 0.873094978f, -0.487550160f, + 0.870086991f, -0.492898192f, + 0.867046246f, -0.498227667f, + 0.863972856f, -0.503538384f, + 0.860866939f, -0.508830143f, + 0.857728610f, -0.514102744f, + 0.854557988f, -0.519355990f, + 0.851355193f, -0.524589683f, + 0.848120345f, -0.529803625f, + 0.844853565f, -0.534997620f, + 0.841554977f, -0.540171473f, + 0.838224706f, -0.545324988f, + 0.834862875f, -0.550457973f, + 0.831469612f, -0.555570233f, + 0.828045045f, -0.560661576f, + 0.824589303f, -0.565731811f, + 0.821102515f, -0.570780746f, + 0.817584813f, -0.575808191f, + 0.814036330f, -0.580813958f, + 0.810457198f, -0.585797857f, + 0.806847554f, -0.590759702f, + 0.803207531f, -0.595699304f, + 0.799537269f, -0.600616479f, + 0.795836905f, -0.605511041f, + 0.792106577f, -0.610382806f, + 0.788346428f, -0.615231591f, + 0.784556597f, -0.620057212f, + 0.780737229f, -0.624859488f, + 0.776888466f, -0.629638239f, + 0.773010453f, -0.634393284f, + 0.769103338f, -0.639124445f, + 0.765167266f, -0.643831543f, + 0.761202385f, -0.648514401f, + 0.757208847f, -0.653172843f, + 0.753186799f, -0.657806693f, + 0.749136395f, -0.662415778f, + 0.745057785f, -0.666999922f, + 0.740951125f, -0.671558955f, + 0.736816569f, -0.676092704f, + 0.732654272f, -0.680600998f, + 0.728464390f, -0.685083668f, + 0.724247083f, -0.689540545f, + 0.720002508f, -0.693971461f, + 0.715730825f, -0.698376249f, + 0.711432196f, -0.702754744f, + 0.707106781f, -0.707106781f, + 0.702754744f, -0.711432196f, + 0.698376249f, -0.715730825f, + 0.693971461f, -0.720002508f, + 0.689540545f, -0.724247083f, + 0.685083668f, -0.728464390f, + 0.680600998f, -0.732654272f, + 0.676092704f, -0.736816569f, + 0.671558955f, -0.740951125f, + 0.666999922f, -0.745057785f, + 0.662415778f, -0.749136395f, + 0.657806693f, -0.753186799f, + 0.653172843f, -0.757208847f, + 0.648514401f, -0.761202385f, + 0.643831543f, -0.765167266f, + 0.639124445f, -0.769103338f, + 0.634393284f, -0.773010453f, + 0.629638239f, -0.776888466f, + 0.624859488f, -0.780737229f, + 0.620057212f, -0.784556597f, + 0.615231591f, -0.788346428f, + 0.610382806f, -0.792106577f, + 0.605511041f, -0.795836905f, + 0.600616479f, -0.799537269f, + 0.595699304f, -0.803207531f, + 0.590759702f, -0.806847554f, + 0.585797857f, -0.810457198f, + 0.580813958f, -0.814036330f, + 0.575808191f, -0.817584813f, + 0.570780746f, -0.821102515f, + 0.565731811f, -0.824589303f, + 0.560661576f, -0.828045045f, + 0.555570233f, -0.831469612f, + 0.550457973f, -0.834862875f, + 0.545324988f, -0.838224706f, + 0.540171473f, -0.841554977f, + 0.534997620f, -0.844853565f, + 0.529803625f, -0.848120345f, + 0.524589683f, -0.851355193f, + 0.519355990f, -0.854557988f, + 0.514102744f, -0.857728610f, + 0.508830143f, -0.860866939f, + 0.503538384f, -0.863972856f, + 0.498227667f, -0.867046246f, + 0.492898192f, -0.870086991f, + 0.487550160f, -0.873094978f, + 0.482183772f, -0.876070094f, + 0.476799230f, -0.879012226f, + 0.471396737f, -0.881921264f, + 0.465976496f, -0.884797098f, + 0.460538711f, -0.887639620f, + 0.455083587f, -0.890448723f, + 0.449611330f, -0.893224301f, + 0.444122145f, -0.895966250f, + 0.438616239f, -0.898674466f, + 0.433093819f, -0.901348847f, + 0.427555093f, -0.903989293f, + 0.422000271f, -0.906595705f, + 0.416429560f, -0.909167983f, + 0.410843171f, -0.911706032f, + 0.405241314f, -0.914209756f, + 0.399624200f, -0.916679060f, + 0.393992040f, -0.919113852f, + 0.388345047f, -0.921514039f, + 0.382683432f, -0.923879533f, + 0.377007410f, -0.926210242f, + 0.371317194f, -0.928506080f, + 0.365612998f, -0.930766961f, + 0.359895037f, -0.932992799f, + 0.354163525f, -0.935183510f, + 0.348418680f, -0.937339012f, + 0.342660717f, -0.939459224f, + 0.336889853f, -0.941544065f, + 0.331106306f, -0.943593458f, + 0.325310292f, -0.945607325f, + 0.319502031f, -0.947585591f, + 0.313681740f, -0.949528181f, + 0.307849640f, -0.951435021f, + 0.302005949f, -0.953306040f, + 0.296150888f, -0.955141168f, + 0.290284677f, -0.956940336f, + 0.284407537f, -0.958703475f, + 0.278519689f, -0.960430519f, + 0.272621355f, -0.962121404f, + 0.266712757f, -0.963776066f, + 0.260794118f, -0.965394442f, + 0.254865660f, -0.966976471f, + 0.248927606f, -0.968522094f, + 0.242980180f, -0.970031253f, + 0.237023606f, -0.971503891f, + 0.231058108f, -0.972939952f, + 0.225083911f, -0.974339383f, + 0.219101240f, -0.975702130f, + 0.213110320f, -0.977028143f, + 0.207111376f, -0.978317371f, + 0.201104635f, -0.979569766f, + 0.195090322f, -0.980785280f, + 0.189068664f, -0.981963869f, + 0.183039888f, -0.983105487f, + 0.177004220f, -0.984210092f, + 0.170961889f, -0.985277642f, + 0.164913120f, -0.986308097f, + 0.158858143f, -0.987301418f, + 0.152797185f, -0.988257568f, + 0.146730474f, -0.989176510f, + 0.140658239f, -0.990058210f, + 0.134580709f, -0.990902635f, + 0.128498111f, -0.991709754f, + 0.122410675f, -0.992479535f, + 0.116318631f, -0.993211949f, + 0.110222207f, -0.993906970f, + 0.104121634f, -0.994564571f, + 0.098017140f, -0.995184727f, + 0.091908956f, -0.995767414f, + 0.085797312f, -0.996312612f, + 0.079682438f, -0.996820299f, + 0.073564564f, -0.997290457f, + 0.067443920f, -0.997723067f, + 0.061320736f, -0.998118113f, + 0.055195244f, -0.998475581f, + 0.049067674f, -0.998795456f, + 0.042938257f, -0.999077728f, + 0.036807223f, -0.999322385f, + 0.030674803f, -0.999529418f, + 0.024541229f, -0.999698819f, + 0.018406730f, -0.999830582f, + 0.012271538f, -0.999924702f, + 0.006135885f, -0.999981175f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048) +const float32_t twiddleCoef_rfft_2048[2048] = { + 0.000000000f, 1.000000000f, + 0.003067957f, 0.999995294f, + 0.006135885f, 0.999981175f, + 0.009203755f, 0.999957645f, + 0.012271538f, 0.999924702f, + 0.015339206f, 0.999882347f, + 0.018406730f, 0.999830582f, + 0.021474080f, 0.999769405f, + 0.024541229f, 0.999698819f, + 0.027608146f, 0.999618822f, + 0.030674803f, 0.999529418f, + 0.033741172f, 0.999430605f, + 0.036807223f, 0.999322385f, + 0.039872928f, 0.999204759f, + 0.042938257f, 0.999077728f, + 0.046003182f, 0.998941293f, + 0.049067674f, 0.998795456f, + 0.052131705f, 0.998640218f, + 0.055195244f, 0.998475581f, + 0.058258265f, 0.998301545f, + 0.061320736f, 0.998118113f, + 0.064382631f, 0.997925286f, + 0.067443920f, 0.997723067f, + 0.070504573f, 0.997511456f, + 0.073564564f, 0.997290457f, + 0.076623861f, 0.997060070f, + 0.079682438f, 0.996820299f, + 0.082740265f, 0.996571146f, + 0.085797312f, 0.996312612f, + 0.088853553f, 0.996044701f, + 0.091908956f, 0.995767414f, + 0.094963495f, 0.995480755f, + 0.098017140f, 0.995184727f, + 0.101069863f, 0.994879331f, + 0.104121634f, 0.994564571f, + 0.107172425f, 0.994240449f, + 0.110222207f, 0.993906970f, + 0.113270952f, 0.993564136f, + 0.116318631f, 0.993211949f, + 0.119365215f, 0.992850414f, + 0.122410675f, 0.992479535f, + 0.125454983f, 0.992099313f, + 0.128498111f, 0.991709754f, + 0.131540029f, 0.991310860f, + 0.134580709f, 0.990902635f, + 0.137620122f, 0.990485084f, + 0.140658239f, 0.990058210f, + 0.143695033f, 0.989622017f, + 0.146730474f, 0.989176510f, + 0.149764535f, 0.988721692f, + 0.152797185f, 0.988257568f, + 0.155828398f, 0.987784142f, + 0.158858143f, 0.987301418f, + 0.161886394f, 0.986809402f, + 0.164913120f, 0.986308097f, + 0.167938295f, 0.985797509f, + 0.170961889f, 0.985277642f, + 0.173983873f, 0.984748502f, + 0.177004220f, 0.984210092f, + 0.180022901f, 0.983662419f, + 0.183039888f, 0.983105487f, + 0.186055152f, 0.982539302f, + 0.189068664f, 0.981963869f, + 0.192080397f, 0.981379193f, + 0.195090322f, 0.980785280f, + 0.198098411f, 0.980182136f, + 0.201104635f, 0.979569766f, + 0.204108966f, 0.978948175f, + 0.207111376f, 0.978317371f, + 0.210111837f, 0.977677358f, + 0.213110320f, 0.977028143f, + 0.216106797f, 0.976369731f, + 0.219101240f, 0.975702130f, + 0.222093621f, 0.975025345f, + 0.225083911f, 0.974339383f, + 0.228072083f, 0.973644250f, + 0.231058108f, 0.972939952f, + 0.234041959f, 0.972226497f, + 0.237023606f, 0.971503891f, + 0.240003022f, 0.970772141f, + 0.242980180f, 0.970031253f, + 0.245955050f, 0.969281235f, + 0.248927606f, 0.968522094f, + 0.251897818f, 0.967753837f, + 0.254865660f, 0.966976471f, + 0.257831102f, 0.966190003f, + 0.260794118f, 0.965394442f, + 0.263754679f, 0.964589793f, + 0.266712757f, 0.963776066f, + 0.269668326f, 0.962953267f, + 0.272621355f, 0.962121404f, + 0.275571819f, 0.961280486f, + 0.278519689f, 0.960430519f, + 0.281464938f, 0.959571513f, + 0.284407537f, 0.958703475f, + 0.287347460f, 0.957826413f, + 0.290284677f, 0.956940336f, + 0.293219163f, 0.956045251f, + 0.296150888f, 0.955141168f, + 0.299079826f, 0.954228095f, + 0.302005949f, 0.953306040f, + 0.304929230f, 0.952375013f, + 0.307849640f, 0.951435021f, + 0.310767153f, 0.950486074f, + 0.313681740f, 0.949528181f, + 0.316593376f, 0.948561350f, + 0.319502031f, 0.947585591f, + 0.322407679f, 0.946600913f, + 0.325310292f, 0.945607325f, + 0.328209844f, 0.944604837f, + 0.331106306f, 0.943593458f, + 0.333999651f, 0.942573198f, + 0.336889853f, 0.941544065f, + 0.339776884f, 0.940506071f, + 0.342660717f, 0.939459224f, + 0.345541325f, 0.938403534f, + 0.348418680f, 0.937339012f, + 0.351292756f, 0.936265667f, + 0.354163525f, 0.935183510f, + 0.357030961f, 0.934092550f, + 0.359895037f, 0.932992799f, + 0.362755724f, 0.931884266f, + 0.365612998f, 0.930766961f, + 0.368466830f, 0.929640896f, + 0.371317194f, 0.928506080f, + 0.374164063f, 0.927362526f, + 0.377007410f, 0.926210242f, + 0.379847209f, 0.925049241f, + 0.382683432f, 0.923879533f, + 0.385516054f, 0.922701128f, + 0.388345047f, 0.921514039f, + 0.391170384f, 0.920318277f, + 0.393992040f, 0.919113852f, + 0.396809987f, 0.917900776f, + 0.399624200f, 0.916679060f, + 0.402434651f, 0.915448716f, + 0.405241314f, 0.914209756f, + 0.408044163f, 0.912962190f, + 0.410843171f, 0.911706032f, + 0.413638312f, 0.910441292f, + 0.416429560f, 0.909167983f, + 0.419216888f, 0.907886116f, + 0.422000271f, 0.906595705f, + 0.424779681f, 0.905296759f, + 0.427555093f, 0.903989293f, + 0.430326481f, 0.902673318f, + 0.433093819f, 0.901348847f, + 0.435857080f, 0.900015892f, + 0.438616239f, 0.898674466f, + 0.441371269f, 0.897324581f, + 0.444122145f, 0.895966250f, + 0.446868840f, 0.894599486f, + 0.449611330f, 0.893224301f, + 0.452349587f, 0.891840709f, + 0.455083587f, 0.890448723f, + 0.457813304f, 0.889048356f, + 0.460538711f, 0.887639620f, + 0.463259784f, 0.886222530f, + 0.465976496f, 0.884797098f, + 0.468688822f, 0.883363339f, + 0.471396737f, 0.881921264f, + 0.474100215f, 0.880470889f, + 0.476799230f, 0.879012226f, + 0.479493758f, 0.877545290f, + 0.482183772f, 0.876070094f, + 0.484869248f, 0.874586652f, + 0.487550160f, 0.873094978f, + 0.490226483f, 0.871595087f, + 0.492898192f, 0.870086991f, + 0.495565262f, 0.868570706f, + 0.498227667f, 0.867046246f, + 0.500885383f, 0.865513624f, + 0.503538384f, 0.863972856f, + 0.506186645f, 0.862423956f, + 0.508830143f, 0.860866939f, + 0.511468850f, 0.859301818f, + 0.514102744f, 0.857728610f, + 0.516731799f, 0.856147328f, + 0.519355990f, 0.854557988f, + 0.521975293f, 0.852960605f, + 0.524589683f, 0.851355193f, + 0.527199135f, 0.849741768f, + 0.529803625f, 0.848120345f, + 0.532403128f, 0.846490939f, + 0.534997620f, 0.844853565f, + 0.537587076f, 0.843208240f, + 0.540171473f, 0.841554977f, + 0.542750785f, 0.839893794f, + 0.545324988f, 0.838224706f, + 0.547894059f, 0.836547727f, + 0.550457973f, 0.834862875f, + 0.553016706f, 0.833170165f, + 0.555570233f, 0.831469612f, + 0.558118531f, 0.829761234f, + 0.560661576f, 0.828045045f, + 0.563199344f, 0.826321063f, + 0.565731811f, 0.824589303f, + 0.568258953f, 0.822849781f, + 0.570780746f, 0.821102515f, + 0.573297167f, 0.819347520f, + 0.575808191f, 0.817584813f, + 0.578313796f, 0.815814411f, + 0.580813958f, 0.814036330f, + 0.583308653f, 0.812250587f, + 0.585797857f, 0.810457198f, + 0.588281548f, 0.808656182f, + 0.590759702f, 0.806847554f, + 0.593232295f, 0.805031331f, + 0.595699304f, 0.803207531f, + 0.598160707f, 0.801376172f, + 0.600616479f, 0.799537269f, + 0.603066599f, 0.797690841f, + 0.605511041f, 0.795836905f, + 0.607949785f, 0.793975478f, + 0.610382806f, 0.792106577f, + 0.612810082f, 0.790230221f, + 0.615231591f, 0.788346428f, + 0.617647308f, 0.786455214f, + 0.620057212f, 0.784556597f, + 0.622461279f, 0.782650596f, + 0.624859488f, 0.780737229f, + 0.627251815f, 0.778816512f, + 0.629638239f, 0.776888466f, + 0.632018736f, 0.774953107f, + 0.634393284f, 0.773010453f, + 0.636761861f, 0.771060524f, + 0.639124445f, 0.769103338f, + 0.641481013f, 0.767138912f, + 0.643831543f, 0.765167266f, + 0.646176013f, 0.763188417f, + 0.648514401f, 0.761202385f, + 0.650846685f, 0.759209189f, + 0.653172843f, 0.757208847f, + 0.655492853f, 0.755201377f, + 0.657806693f, 0.753186799f, + 0.660114342f, 0.751165132f, + 0.662415778f, 0.749136395f, + 0.664710978f, 0.747100606f, + 0.666999922f, 0.745057785f, + 0.669282588f, 0.743007952f, + 0.671558955f, 0.740951125f, + 0.673829000f, 0.738887324f, + 0.676092704f, 0.736816569f, + 0.678350043f, 0.734738878f, + 0.680600998f, 0.732654272f, + 0.682845546f, 0.730562769f, + 0.685083668f, 0.728464390f, + 0.687315341f, 0.726359155f, + 0.689540545f, 0.724247083f, + 0.691759258f, 0.722128194f, + 0.693971461f, 0.720002508f, + 0.696177131f, 0.717870045f, + 0.698376249f, 0.715730825f, + 0.700568794f, 0.713584869f, + 0.702754744f, 0.711432196f, + 0.704934080f, 0.709272826f, + 0.707106781f, 0.707106781f, + 0.709272826f, 0.704934080f, + 0.711432196f, 0.702754744f, + 0.713584869f, 0.700568794f, + 0.715730825f, 0.698376249f, + 0.717870045f, 0.696177131f, + 0.720002508f, 0.693971461f, + 0.722128194f, 0.691759258f, + 0.724247083f, 0.689540545f, + 0.726359155f, 0.687315341f, + 0.728464390f, 0.685083668f, + 0.730562769f, 0.682845546f, + 0.732654272f, 0.680600998f, + 0.734738878f, 0.678350043f, + 0.736816569f, 0.676092704f, + 0.738887324f, 0.673829000f, + 0.740951125f, 0.671558955f, + 0.743007952f, 0.669282588f, + 0.745057785f, 0.666999922f, + 0.747100606f, 0.664710978f, + 0.749136395f, 0.662415778f, + 0.751165132f, 0.660114342f, + 0.753186799f, 0.657806693f, + 0.755201377f, 0.655492853f, + 0.757208847f, 0.653172843f, + 0.759209189f, 0.650846685f, + 0.761202385f, 0.648514401f, + 0.763188417f, 0.646176013f, + 0.765167266f, 0.643831543f, + 0.767138912f, 0.641481013f, + 0.769103338f, 0.639124445f, + 0.771060524f, 0.636761861f, + 0.773010453f, 0.634393284f, + 0.774953107f, 0.632018736f, + 0.776888466f, 0.629638239f, + 0.778816512f, 0.627251815f, + 0.780737229f, 0.624859488f, + 0.782650596f, 0.622461279f, + 0.784556597f, 0.620057212f, + 0.786455214f, 0.617647308f, + 0.788346428f, 0.615231591f, + 0.790230221f, 0.612810082f, + 0.792106577f, 0.610382806f, + 0.793975478f, 0.607949785f, + 0.795836905f, 0.605511041f, + 0.797690841f, 0.603066599f, + 0.799537269f, 0.600616479f, + 0.801376172f, 0.598160707f, + 0.803207531f, 0.595699304f, + 0.805031331f, 0.593232295f, + 0.806847554f, 0.590759702f, + 0.808656182f, 0.588281548f, + 0.810457198f, 0.585797857f, + 0.812250587f, 0.583308653f, + 0.814036330f, 0.580813958f, + 0.815814411f, 0.578313796f, + 0.817584813f, 0.575808191f, + 0.819347520f, 0.573297167f, + 0.821102515f, 0.570780746f, + 0.822849781f, 0.568258953f, + 0.824589303f, 0.565731811f, + 0.826321063f, 0.563199344f, + 0.828045045f, 0.560661576f, + 0.829761234f, 0.558118531f, + 0.831469612f, 0.555570233f, + 0.833170165f, 0.553016706f, + 0.834862875f, 0.550457973f, + 0.836547727f, 0.547894059f, + 0.838224706f, 0.545324988f, + 0.839893794f, 0.542750785f, + 0.841554977f, 0.540171473f, + 0.843208240f, 0.537587076f, + 0.844853565f, 0.534997620f, + 0.846490939f, 0.532403128f, + 0.848120345f, 0.529803625f, + 0.849741768f, 0.527199135f, + 0.851355193f, 0.524589683f, + 0.852960605f, 0.521975293f, + 0.854557988f, 0.519355990f, + 0.856147328f, 0.516731799f, + 0.857728610f, 0.514102744f, + 0.859301818f, 0.511468850f, + 0.860866939f, 0.508830143f, + 0.862423956f, 0.506186645f, + 0.863972856f, 0.503538384f, + 0.865513624f, 0.500885383f, + 0.867046246f, 0.498227667f, + 0.868570706f, 0.495565262f, + 0.870086991f, 0.492898192f, + 0.871595087f, 0.490226483f, + 0.873094978f, 0.487550160f, + 0.874586652f, 0.484869248f, + 0.876070094f, 0.482183772f, + 0.877545290f, 0.479493758f, + 0.879012226f, 0.476799230f, + 0.880470889f, 0.474100215f, + 0.881921264f, 0.471396737f, + 0.883363339f, 0.468688822f, + 0.884797098f, 0.465976496f, + 0.886222530f, 0.463259784f, + 0.887639620f, 0.460538711f, + 0.889048356f, 0.457813304f, + 0.890448723f, 0.455083587f, + 0.891840709f, 0.452349587f, + 0.893224301f, 0.449611330f, + 0.894599486f, 0.446868840f, + 0.895966250f, 0.444122145f, + 0.897324581f, 0.441371269f, + 0.898674466f, 0.438616239f, + 0.900015892f, 0.435857080f, + 0.901348847f, 0.433093819f, + 0.902673318f, 0.430326481f, + 0.903989293f, 0.427555093f, + 0.905296759f, 0.424779681f, + 0.906595705f, 0.422000271f, + 0.907886116f, 0.419216888f, + 0.909167983f, 0.416429560f, + 0.910441292f, 0.413638312f, + 0.911706032f, 0.410843171f, + 0.912962190f, 0.408044163f, + 0.914209756f, 0.405241314f, + 0.915448716f, 0.402434651f, + 0.916679060f, 0.399624200f, + 0.917900776f, 0.396809987f, + 0.919113852f, 0.393992040f, + 0.920318277f, 0.391170384f, + 0.921514039f, 0.388345047f, + 0.922701128f, 0.385516054f, + 0.923879533f, 0.382683432f, + 0.925049241f, 0.379847209f, + 0.926210242f, 0.377007410f, + 0.927362526f, 0.374164063f, + 0.928506080f, 0.371317194f, + 0.929640896f, 0.368466830f, + 0.930766961f, 0.365612998f, + 0.931884266f, 0.362755724f, + 0.932992799f, 0.359895037f, + 0.934092550f, 0.357030961f, + 0.935183510f, 0.354163525f, + 0.936265667f, 0.351292756f, + 0.937339012f, 0.348418680f, + 0.938403534f, 0.345541325f, + 0.939459224f, 0.342660717f, + 0.940506071f, 0.339776884f, + 0.941544065f, 0.336889853f, + 0.942573198f, 0.333999651f, + 0.943593458f, 0.331106306f, + 0.944604837f, 0.328209844f, + 0.945607325f, 0.325310292f, + 0.946600913f, 0.322407679f, + 0.947585591f, 0.319502031f, + 0.948561350f, 0.316593376f, + 0.949528181f, 0.313681740f, + 0.950486074f, 0.310767153f, + 0.951435021f, 0.307849640f, + 0.952375013f, 0.304929230f, + 0.953306040f, 0.302005949f, + 0.954228095f, 0.299079826f, + 0.955141168f, 0.296150888f, + 0.956045251f, 0.293219163f, + 0.956940336f, 0.290284677f, + 0.957826413f, 0.287347460f, + 0.958703475f, 0.284407537f, + 0.959571513f, 0.281464938f, + 0.960430519f, 0.278519689f, + 0.961280486f, 0.275571819f, + 0.962121404f, 0.272621355f, + 0.962953267f, 0.269668326f, + 0.963776066f, 0.266712757f, + 0.964589793f, 0.263754679f, + 0.965394442f, 0.260794118f, + 0.966190003f, 0.257831102f, + 0.966976471f, 0.254865660f, + 0.967753837f, 0.251897818f, + 0.968522094f, 0.248927606f, + 0.969281235f, 0.245955050f, + 0.970031253f, 0.242980180f, + 0.970772141f, 0.240003022f, + 0.971503891f, 0.237023606f, + 0.972226497f, 0.234041959f, + 0.972939952f, 0.231058108f, + 0.973644250f, 0.228072083f, + 0.974339383f, 0.225083911f, + 0.975025345f, 0.222093621f, + 0.975702130f, 0.219101240f, + 0.976369731f, 0.216106797f, + 0.977028143f, 0.213110320f, + 0.977677358f, 0.210111837f, + 0.978317371f, 0.207111376f, + 0.978948175f, 0.204108966f, + 0.979569766f, 0.201104635f, + 0.980182136f, 0.198098411f, + 0.980785280f, 0.195090322f, + 0.981379193f, 0.192080397f, + 0.981963869f, 0.189068664f, + 0.982539302f, 0.186055152f, + 0.983105487f, 0.183039888f, + 0.983662419f, 0.180022901f, + 0.984210092f, 0.177004220f, + 0.984748502f, 0.173983873f, + 0.985277642f, 0.170961889f, + 0.985797509f, 0.167938295f, + 0.986308097f, 0.164913120f, + 0.986809402f, 0.161886394f, + 0.987301418f, 0.158858143f, + 0.987784142f, 0.155828398f, + 0.988257568f, 0.152797185f, + 0.988721692f, 0.149764535f, + 0.989176510f, 0.146730474f, + 0.989622017f, 0.143695033f, + 0.990058210f, 0.140658239f, + 0.990485084f, 0.137620122f, + 0.990902635f, 0.134580709f, + 0.991310860f, 0.131540029f, + 0.991709754f, 0.128498111f, + 0.992099313f, 0.125454983f, + 0.992479535f, 0.122410675f, + 0.992850414f, 0.119365215f, + 0.993211949f, 0.116318631f, + 0.993564136f, 0.113270952f, + 0.993906970f, 0.110222207f, + 0.994240449f, 0.107172425f, + 0.994564571f, 0.104121634f, + 0.994879331f, 0.101069863f, + 0.995184727f, 0.098017140f, + 0.995480755f, 0.094963495f, + 0.995767414f, 0.091908956f, + 0.996044701f, 0.088853553f, + 0.996312612f, 0.085797312f, + 0.996571146f, 0.082740265f, + 0.996820299f, 0.079682438f, + 0.997060070f, 0.076623861f, + 0.997290457f, 0.073564564f, + 0.997511456f, 0.070504573f, + 0.997723067f, 0.067443920f, + 0.997925286f, 0.064382631f, + 0.998118113f, 0.061320736f, + 0.998301545f, 0.058258265f, + 0.998475581f, 0.055195244f, + 0.998640218f, 0.052131705f, + 0.998795456f, 0.049067674f, + 0.998941293f, 0.046003182f, + 0.999077728f, 0.042938257f, + 0.999204759f, 0.039872928f, + 0.999322385f, 0.036807223f, + 0.999430605f, 0.033741172f, + 0.999529418f, 0.030674803f, + 0.999618822f, 0.027608146f, + 0.999698819f, 0.024541229f, + 0.999769405f, 0.021474080f, + 0.999830582f, 0.018406730f, + 0.999882347f, 0.015339206f, + 0.999924702f, 0.012271538f, + 0.999957645f, 0.009203755f, + 0.999981175f, 0.006135885f, + 0.999995294f, 0.003067957f, + 1.000000000f, 0.000000000f, + 0.999995294f, -0.003067957f, + 0.999981175f, -0.006135885f, + 0.999957645f, -0.009203755f, + 0.999924702f, -0.012271538f, + 0.999882347f, -0.015339206f, + 0.999830582f, -0.018406730f, + 0.999769405f, -0.021474080f, + 0.999698819f, -0.024541229f, + 0.999618822f, -0.027608146f, + 0.999529418f, -0.030674803f, + 0.999430605f, -0.033741172f, + 0.999322385f, -0.036807223f, + 0.999204759f, -0.039872928f, + 0.999077728f, -0.042938257f, + 0.998941293f, -0.046003182f, + 0.998795456f, -0.049067674f, + 0.998640218f, -0.052131705f, + 0.998475581f, -0.055195244f, + 0.998301545f, -0.058258265f, + 0.998118113f, -0.061320736f, + 0.997925286f, -0.064382631f, + 0.997723067f, -0.067443920f, + 0.997511456f, -0.070504573f, + 0.997290457f, -0.073564564f, + 0.997060070f, -0.076623861f, + 0.996820299f, -0.079682438f, + 0.996571146f, -0.082740265f, + 0.996312612f, -0.085797312f, + 0.996044701f, -0.088853553f, + 0.995767414f, -0.091908956f, + 0.995480755f, -0.094963495f, + 0.995184727f, -0.098017140f, + 0.994879331f, -0.101069863f, + 0.994564571f, -0.104121634f, + 0.994240449f, -0.107172425f, + 0.993906970f, -0.110222207f, + 0.993564136f, -0.113270952f, + 0.993211949f, -0.116318631f, + 0.992850414f, -0.119365215f, + 0.992479535f, -0.122410675f, + 0.992099313f, -0.125454983f, + 0.991709754f, -0.128498111f, + 0.991310860f, -0.131540029f, + 0.990902635f, -0.134580709f, + 0.990485084f, -0.137620122f, + 0.990058210f, -0.140658239f, + 0.989622017f, -0.143695033f, + 0.989176510f, -0.146730474f, + 0.988721692f, -0.149764535f, + 0.988257568f, -0.152797185f, + 0.987784142f, -0.155828398f, + 0.987301418f, -0.158858143f, + 0.986809402f, -0.161886394f, + 0.986308097f, -0.164913120f, + 0.985797509f, -0.167938295f, + 0.985277642f, -0.170961889f, + 0.984748502f, -0.173983873f, + 0.984210092f, -0.177004220f, + 0.983662419f, -0.180022901f, + 0.983105487f, -0.183039888f, + 0.982539302f, -0.186055152f, + 0.981963869f, -0.189068664f, + 0.981379193f, -0.192080397f, + 0.980785280f, -0.195090322f, + 0.980182136f, -0.198098411f, + 0.979569766f, -0.201104635f, + 0.978948175f, -0.204108966f, + 0.978317371f, -0.207111376f, + 0.977677358f, -0.210111837f, + 0.977028143f, -0.213110320f, + 0.976369731f, -0.216106797f, + 0.975702130f, -0.219101240f, + 0.975025345f, -0.222093621f, + 0.974339383f, -0.225083911f, + 0.973644250f, -0.228072083f, + 0.972939952f, -0.231058108f, + 0.972226497f, -0.234041959f, + 0.971503891f, -0.237023606f, + 0.970772141f, -0.240003022f, + 0.970031253f, -0.242980180f, + 0.969281235f, -0.245955050f, + 0.968522094f, -0.248927606f, + 0.967753837f, -0.251897818f, + 0.966976471f, -0.254865660f, + 0.966190003f, -0.257831102f, + 0.965394442f, -0.260794118f, + 0.964589793f, -0.263754679f, + 0.963776066f, -0.266712757f, + 0.962953267f, -0.269668326f, + 0.962121404f, -0.272621355f, + 0.961280486f, -0.275571819f, + 0.960430519f, -0.278519689f, + 0.959571513f, -0.281464938f, + 0.958703475f, -0.284407537f, + 0.957826413f, -0.287347460f, + 0.956940336f, -0.290284677f, + 0.956045251f, -0.293219163f, + 0.955141168f, -0.296150888f, + 0.954228095f, -0.299079826f, + 0.953306040f, -0.302005949f, + 0.952375013f, -0.304929230f, + 0.951435021f, -0.307849640f, + 0.950486074f, -0.310767153f, + 0.949528181f, -0.313681740f, + 0.948561350f, -0.316593376f, + 0.947585591f, -0.319502031f, + 0.946600913f, -0.322407679f, + 0.945607325f, -0.325310292f, + 0.944604837f, -0.328209844f, + 0.943593458f, -0.331106306f, + 0.942573198f, -0.333999651f, + 0.941544065f, -0.336889853f, + 0.940506071f, -0.339776884f, + 0.939459224f, -0.342660717f, + 0.938403534f, -0.345541325f, + 0.937339012f, -0.348418680f, + 0.936265667f, -0.351292756f, + 0.935183510f, -0.354163525f, + 0.934092550f, -0.357030961f, + 0.932992799f, -0.359895037f, + 0.931884266f, -0.362755724f, + 0.930766961f, -0.365612998f, + 0.929640896f, -0.368466830f, + 0.928506080f, -0.371317194f, + 0.927362526f, -0.374164063f, + 0.926210242f, -0.377007410f, + 0.925049241f, -0.379847209f, + 0.923879533f, -0.382683432f, + 0.922701128f, -0.385516054f, + 0.921514039f, -0.388345047f, + 0.920318277f, -0.391170384f, + 0.919113852f, -0.393992040f, + 0.917900776f, -0.396809987f, + 0.916679060f, -0.399624200f, + 0.915448716f, -0.402434651f, + 0.914209756f, -0.405241314f, + 0.912962190f, -0.408044163f, + 0.911706032f, -0.410843171f, + 0.910441292f, -0.413638312f, + 0.909167983f, -0.416429560f, + 0.907886116f, -0.419216888f, + 0.906595705f, -0.422000271f, + 0.905296759f, -0.424779681f, + 0.903989293f, -0.427555093f, + 0.902673318f, -0.430326481f, + 0.901348847f, -0.433093819f, + 0.900015892f, -0.435857080f, + 0.898674466f, -0.438616239f, + 0.897324581f, -0.441371269f, + 0.895966250f, -0.444122145f, + 0.894599486f, -0.446868840f, + 0.893224301f, -0.449611330f, + 0.891840709f, -0.452349587f, + 0.890448723f, -0.455083587f, + 0.889048356f, -0.457813304f, + 0.887639620f, -0.460538711f, + 0.886222530f, -0.463259784f, + 0.884797098f, -0.465976496f, + 0.883363339f, -0.468688822f, + 0.881921264f, -0.471396737f, + 0.880470889f, -0.474100215f, + 0.879012226f, -0.476799230f, + 0.877545290f, -0.479493758f, + 0.876070094f, -0.482183772f, + 0.874586652f, -0.484869248f, + 0.873094978f, -0.487550160f, + 0.871595087f, -0.490226483f, + 0.870086991f, -0.492898192f, + 0.868570706f, -0.495565262f, + 0.867046246f, -0.498227667f, + 0.865513624f, -0.500885383f, + 0.863972856f, -0.503538384f, + 0.862423956f, -0.506186645f, + 0.860866939f, -0.508830143f, + 0.859301818f, -0.511468850f, + 0.857728610f, -0.514102744f, + 0.856147328f, -0.516731799f, + 0.854557988f, -0.519355990f, + 0.852960605f, -0.521975293f, + 0.851355193f, -0.524589683f, + 0.849741768f, -0.527199135f, + 0.848120345f, -0.529803625f, + 0.846490939f, -0.532403128f, + 0.844853565f, -0.534997620f, + 0.843208240f, -0.537587076f, + 0.841554977f, -0.540171473f, + 0.839893794f, -0.542750785f, + 0.838224706f, -0.545324988f, + 0.836547727f, -0.547894059f, + 0.834862875f, -0.550457973f, + 0.833170165f, -0.553016706f, + 0.831469612f, -0.555570233f, + 0.829761234f, -0.558118531f, + 0.828045045f, -0.560661576f, + 0.826321063f, -0.563199344f, + 0.824589303f, -0.565731811f, + 0.822849781f, -0.568258953f, + 0.821102515f, -0.570780746f, + 0.819347520f, -0.573297167f, + 0.817584813f, -0.575808191f, + 0.815814411f, -0.578313796f, + 0.814036330f, -0.580813958f, + 0.812250587f, -0.583308653f, + 0.810457198f, -0.585797857f, + 0.808656182f, -0.588281548f, + 0.806847554f, -0.590759702f, + 0.805031331f, -0.593232295f, + 0.803207531f, -0.595699304f, + 0.801376172f, -0.598160707f, + 0.799537269f, -0.600616479f, + 0.797690841f, -0.603066599f, + 0.795836905f, -0.605511041f, + 0.793975478f, -0.607949785f, + 0.792106577f, -0.610382806f, + 0.790230221f, -0.612810082f, + 0.788346428f, -0.615231591f, + 0.786455214f, -0.617647308f, + 0.784556597f, -0.620057212f, + 0.782650596f, -0.622461279f, + 0.780737229f, -0.624859488f, + 0.778816512f, -0.627251815f, + 0.776888466f, -0.629638239f, + 0.774953107f, -0.632018736f, + 0.773010453f, -0.634393284f, + 0.771060524f, -0.636761861f, + 0.769103338f, -0.639124445f, + 0.767138912f, -0.641481013f, + 0.765167266f, -0.643831543f, + 0.763188417f, -0.646176013f, + 0.761202385f, -0.648514401f, + 0.759209189f, -0.650846685f, + 0.757208847f, -0.653172843f, + 0.755201377f, -0.655492853f, + 0.753186799f, -0.657806693f, + 0.751165132f, -0.660114342f, + 0.749136395f, -0.662415778f, + 0.747100606f, -0.664710978f, + 0.745057785f, -0.666999922f, + 0.743007952f, -0.669282588f, + 0.740951125f, -0.671558955f, + 0.738887324f, -0.673829000f, + 0.736816569f, -0.676092704f, + 0.734738878f, -0.678350043f, + 0.732654272f, -0.680600998f, + 0.730562769f, -0.682845546f, + 0.728464390f, -0.685083668f, + 0.726359155f, -0.687315341f, + 0.724247083f, -0.689540545f, + 0.722128194f, -0.691759258f, + 0.720002508f, -0.693971461f, + 0.717870045f, -0.696177131f, + 0.715730825f, -0.698376249f, + 0.713584869f, -0.700568794f, + 0.711432196f, -0.702754744f, + 0.709272826f, -0.704934080f, + 0.707106781f, -0.707106781f, + 0.704934080f, -0.709272826f, + 0.702754744f, -0.711432196f, + 0.700568794f, -0.713584869f, + 0.698376249f, -0.715730825f, + 0.696177131f, -0.717870045f, + 0.693971461f, -0.720002508f, + 0.691759258f, -0.722128194f, + 0.689540545f, -0.724247083f, + 0.687315341f, -0.726359155f, + 0.685083668f, -0.728464390f, + 0.682845546f, -0.730562769f, + 0.680600998f, -0.732654272f, + 0.678350043f, -0.734738878f, + 0.676092704f, -0.736816569f, + 0.673829000f, -0.738887324f, + 0.671558955f, -0.740951125f, + 0.669282588f, -0.743007952f, + 0.666999922f, -0.745057785f, + 0.664710978f, -0.747100606f, + 0.662415778f, -0.749136395f, + 0.660114342f, -0.751165132f, + 0.657806693f, -0.753186799f, + 0.655492853f, -0.755201377f, + 0.653172843f, -0.757208847f, + 0.650846685f, -0.759209189f, + 0.648514401f, -0.761202385f, + 0.646176013f, -0.763188417f, + 0.643831543f, -0.765167266f, + 0.641481013f, -0.767138912f, + 0.639124445f, -0.769103338f, + 0.636761861f, -0.771060524f, + 0.634393284f, -0.773010453f, + 0.632018736f, -0.774953107f, + 0.629638239f, -0.776888466f, + 0.627251815f, -0.778816512f, + 0.624859488f, -0.780737229f, + 0.622461279f, -0.782650596f, + 0.620057212f, -0.784556597f, + 0.617647308f, -0.786455214f, + 0.615231591f, -0.788346428f, + 0.612810082f, -0.790230221f, + 0.610382806f, -0.792106577f, + 0.607949785f, -0.793975478f, + 0.605511041f, -0.795836905f, + 0.603066599f, -0.797690841f, + 0.600616479f, -0.799537269f, + 0.598160707f, -0.801376172f, + 0.595699304f, -0.803207531f, + 0.593232295f, -0.805031331f, + 0.590759702f, -0.806847554f, + 0.588281548f, -0.808656182f, + 0.585797857f, -0.810457198f, + 0.583308653f, -0.812250587f, + 0.580813958f, -0.814036330f, + 0.578313796f, -0.815814411f, + 0.575808191f, -0.817584813f, + 0.573297167f, -0.819347520f, + 0.570780746f, -0.821102515f, + 0.568258953f, -0.822849781f, + 0.565731811f, -0.824589303f, + 0.563199344f, -0.826321063f, + 0.560661576f, -0.828045045f, + 0.558118531f, -0.829761234f, + 0.555570233f, -0.831469612f, + 0.553016706f, -0.833170165f, + 0.550457973f, -0.834862875f, + 0.547894059f, -0.836547727f, + 0.545324988f, -0.838224706f, + 0.542750785f, -0.839893794f, + 0.540171473f, -0.841554977f, + 0.537587076f, -0.843208240f, + 0.534997620f, -0.844853565f, + 0.532403128f, -0.846490939f, + 0.529803625f, -0.848120345f, + 0.527199135f, -0.849741768f, + 0.524589683f, -0.851355193f, + 0.521975293f, -0.852960605f, + 0.519355990f, -0.854557988f, + 0.516731799f, -0.856147328f, + 0.514102744f, -0.857728610f, + 0.511468850f, -0.859301818f, + 0.508830143f, -0.860866939f, + 0.506186645f, -0.862423956f, + 0.503538384f, -0.863972856f, + 0.500885383f, -0.865513624f, + 0.498227667f, -0.867046246f, + 0.495565262f, -0.868570706f, + 0.492898192f, -0.870086991f, + 0.490226483f, -0.871595087f, + 0.487550160f, -0.873094978f, + 0.484869248f, -0.874586652f, + 0.482183772f, -0.876070094f, + 0.479493758f, -0.877545290f, + 0.476799230f, -0.879012226f, + 0.474100215f, -0.880470889f, + 0.471396737f, -0.881921264f, + 0.468688822f, -0.883363339f, + 0.465976496f, -0.884797098f, + 0.463259784f, -0.886222530f, + 0.460538711f, -0.887639620f, + 0.457813304f, -0.889048356f, + 0.455083587f, -0.890448723f, + 0.452349587f, -0.891840709f, + 0.449611330f, -0.893224301f, + 0.446868840f, -0.894599486f, + 0.444122145f, -0.895966250f, + 0.441371269f, -0.897324581f, + 0.438616239f, -0.898674466f, + 0.435857080f, -0.900015892f, + 0.433093819f, -0.901348847f, + 0.430326481f, -0.902673318f, + 0.427555093f, -0.903989293f, + 0.424779681f, -0.905296759f, + 0.422000271f, -0.906595705f, + 0.419216888f, -0.907886116f, + 0.416429560f, -0.909167983f, + 0.413638312f, -0.910441292f, + 0.410843171f, -0.911706032f, + 0.408044163f, -0.912962190f, + 0.405241314f, -0.914209756f, + 0.402434651f, -0.915448716f, + 0.399624200f, -0.916679060f, + 0.396809987f, -0.917900776f, + 0.393992040f, -0.919113852f, + 0.391170384f, -0.920318277f, + 0.388345047f, -0.921514039f, + 0.385516054f, -0.922701128f, + 0.382683432f, -0.923879533f, + 0.379847209f, -0.925049241f, + 0.377007410f, -0.926210242f, + 0.374164063f, -0.927362526f, + 0.371317194f, -0.928506080f, + 0.368466830f, -0.929640896f, + 0.365612998f, -0.930766961f, + 0.362755724f, -0.931884266f, + 0.359895037f, -0.932992799f, + 0.357030961f, -0.934092550f, + 0.354163525f, -0.935183510f, + 0.351292756f, -0.936265667f, + 0.348418680f, -0.937339012f, + 0.345541325f, -0.938403534f, + 0.342660717f, -0.939459224f, + 0.339776884f, -0.940506071f, + 0.336889853f, -0.941544065f, + 0.333999651f, -0.942573198f, + 0.331106306f, -0.943593458f, + 0.328209844f, -0.944604837f, + 0.325310292f, -0.945607325f, + 0.322407679f, -0.946600913f, + 0.319502031f, -0.947585591f, + 0.316593376f, -0.948561350f, + 0.313681740f, -0.949528181f, + 0.310767153f, -0.950486074f, + 0.307849640f, -0.951435021f, + 0.304929230f, -0.952375013f, + 0.302005949f, -0.953306040f, + 0.299079826f, -0.954228095f, + 0.296150888f, -0.955141168f, + 0.293219163f, -0.956045251f, + 0.290284677f, -0.956940336f, + 0.287347460f, -0.957826413f, + 0.284407537f, -0.958703475f, + 0.281464938f, -0.959571513f, + 0.278519689f, -0.960430519f, + 0.275571819f, -0.961280486f, + 0.272621355f, -0.962121404f, + 0.269668326f, -0.962953267f, + 0.266712757f, -0.963776066f, + 0.263754679f, -0.964589793f, + 0.260794118f, -0.965394442f, + 0.257831102f, -0.966190003f, + 0.254865660f, -0.966976471f, + 0.251897818f, -0.967753837f, + 0.248927606f, -0.968522094f, + 0.245955050f, -0.969281235f, + 0.242980180f, -0.970031253f, + 0.240003022f, -0.970772141f, + 0.237023606f, -0.971503891f, + 0.234041959f, -0.972226497f, + 0.231058108f, -0.972939952f, + 0.228072083f, -0.973644250f, + 0.225083911f, -0.974339383f, + 0.222093621f, -0.975025345f, + 0.219101240f, -0.975702130f, + 0.216106797f, -0.976369731f, + 0.213110320f, -0.977028143f, + 0.210111837f, -0.977677358f, + 0.207111376f, -0.978317371f, + 0.204108966f, -0.978948175f, + 0.201104635f, -0.979569766f, + 0.198098411f, -0.980182136f, + 0.195090322f, -0.980785280f, + 0.192080397f, -0.981379193f, + 0.189068664f, -0.981963869f, + 0.186055152f, -0.982539302f, + 0.183039888f, -0.983105487f, + 0.180022901f, -0.983662419f, + 0.177004220f, -0.984210092f, + 0.173983873f, -0.984748502f, + 0.170961889f, -0.985277642f, + 0.167938295f, -0.985797509f, + 0.164913120f, -0.986308097f, + 0.161886394f, -0.986809402f, + 0.158858143f, -0.987301418f, + 0.155828398f, -0.987784142f, + 0.152797185f, -0.988257568f, + 0.149764535f, -0.988721692f, + 0.146730474f, -0.989176510f, + 0.143695033f, -0.989622017f, + 0.140658239f, -0.990058210f, + 0.137620122f, -0.990485084f, + 0.134580709f, -0.990902635f, + 0.131540029f, -0.991310860f, + 0.128498111f, -0.991709754f, + 0.125454983f, -0.992099313f, + 0.122410675f, -0.992479535f, + 0.119365215f, -0.992850414f, + 0.116318631f, -0.993211949f, + 0.113270952f, -0.993564136f, + 0.110222207f, -0.993906970f, + 0.107172425f, -0.994240449f, + 0.104121634f, -0.994564571f, + 0.101069863f, -0.994879331f, + 0.098017140f, -0.995184727f, + 0.094963495f, -0.995480755f, + 0.091908956f, -0.995767414f, + 0.088853553f, -0.996044701f, + 0.085797312f, -0.996312612f, + 0.082740265f, -0.996571146f, + 0.079682438f, -0.996820299f, + 0.076623861f, -0.997060070f, + 0.073564564f, -0.997290457f, + 0.070504573f, -0.997511456f, + 0.067443920f, -0.997723067f, + 0.064382631f, -0.997925286f, + 0.061320736f, -0.998118113f, + 0.058258265f, -0.998301545f, + 0.055195244f, -0.998475581f, + 0.052131705f, -0.998640218f, + 0.049067674f, -0.998795456f, + 0.046003182f, -0.998941293f, + 0.042938257f, -0.999077728f, + 0.039872928f, -0.999204759f, + 0.036807223f, -0.999322385f, + 0.033741172f, -0.999430605f, + 0.030674803f, -0.999529418f, + 0.027608146f, -0.999618822f, + 0.024541229f, -0.999698819f, + 0.021474080f, -0.999769405f, + 0.018406730f, -0.999830582f, + 0.015339206f, -0.999882347f, + 0.012271538f, -0.999924702f, + 0.009203755f, -0.999957645f, + 0.006135885f, -0.999981175f, + 0.003067957f, -0.999995294f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096) +const float32_t twiddleCoef_rfft_4096[4096] = { + 0.000000000f, 1.000000000f, + 0.001533980f, 0.999998823f, + 0.003067957f, 0.999995294f, + 0.004601926f, 0.999989411f, + 0.006135885f, 0.999981175f, + 0.007669829f, 0.999970586f, + 0.009203755f, 0.999957645f, + 0.010737659f, 0.999942350f, + 0.012271538f, 0.999924702f, + 0.013805389f, 0.999904701f, + 0.015339206f, 0.999882347f, + 0.016872988f, 0.999857641f, + 0.018406730f, 0.999830582f, + 0.019940429f, 0.999801170f, + 0.021474080f, 0.999769405f, + 0.023007681f, 0.999735288f, + 0.024541229f, 0.999698819f, + 0.026074718f, 0.999659997f, + 0.027608146f, 0.999618822f, + 0.029141509f, 0.999575296f, + 0.030674803f, 0.999529418f, + 0.032208025f, 0.999481187f, + 0.033741172f, 0.999430605f, + 0.035274239f, 0.999377670f, + 0.036807223f, 0.999322385f, + 0.038340120f, 0.999264747f, + 0.039872928f, 0.999204759f, + 0.041405641f, 0.999142419f, + 0.042938257f, 0.999077728f, + 0.044470772f, 0.999010686f, + 0.046003182f, 0.998941293f, + 0.047535484f, 0.998869550f, + 0.049067674f, 0.998795456f, + 0.050599749f, 0.998719012f, + 0.052131705f, 0.998640218f, + 0.053663538f, 0.998559074f, + 0.055195244f, 0.998475581f, + 0.056726821f, 0.998389737f, + 0.058258265f, 0.998301545f, + 0.059789571f, 0.998211003f, + 0.061320736f, 0.998118113f, + 0.062851758f, 0.998022874f, + 0.064382631f, 0.997925286f, + 0.065913353f, 0.997825350f, + 0.067443920f, 0.997723067f, + 0.068974328f, 0.997618435f, + 0.070504573f, 0.997511456f, + 0.072034653f, 0.997402130f, + 0.073564564f, 0.997290457f, + 0.075094301f, 0.997176437f, + 0.076623861f, 0.997060070f, + 0.078153242f, 0.996941358f, + 0.079682438f, 0.996820299f, + 0.081211447f, 0.996696895f, + 0.082740265f, 0.996571146f, + 0.084268888f, 0.996443051f, + 0.085797312f, 0.996312612f, + 0.087325535f, 0.996179829f, + 0.088853553f, 0.996044701f, + 0.090381361f, 0.995907229f, + 0.091908956f, 0.995767414f, + 0.093436336f, 0.995625256f, + 0.094963495f, 0.995480755f, + 0.096490431f, 0.995333912f, + 0.098017140f, 0.995184727f, + 0.099543619f, 0.995033199f, + 0.101069863f, 0.994879331f, + 0.102595869f, 0.994723121f, + 0.104121634f, 0.994564571f, + 0.105647154f, 0.994403680f, + 0.107172425f, 0.994240449f, + 0.108697444f, 0.994074879f, + 0.110222207f, 0.993906970f, + 0.111746711f, 0.993736722f, + 0.113270952f, 0.993564136f, + 0.114794927f, 0.993389211f, + 0.116318631f, 0.993211949f, + 0.117842062f, 0.993032350f, + 0.119365215f, 0.992850414f, + 0.120888087f, 0.992666142f, + 0.122410675f, 0.992479535f, + 0.123932975f, 0.992290591f, + 0.125454983f, 0.992099313f, + 0.126976696f, 0.991905700f, + 0.128498111f, 0.991709754f, + 0.130019223f, 0.991511473f, + 0.131540029f, 0.991310860f, + 0.133060525f, 0.991107914f, + 0.134580709f, 0.990902635f, + 0.136100575f, 0.990695025f, + 0.137620122f, 0.990485084f, + 0.139139344f, 0.990272812f, + 0.140658239f, 0.990058210f, + 0.142176804f, 0.989841278f, + 0.143695033f, 0.989622017f, + 0.145212925f, 0.989400428f, + 0.146730474f, 0.989176510f, + 0.148247679f, 0.988950265f, + 0.149764535f, 0.988721692f, + 0.151281038f, 0.988490793f, + 0.152797185f, 0.988257568f, + 0.154312973f, 0.988022017f, + 0.155828398f, 0.987784142f, + 0.157343456f, 0.987543942f, + 0.158858143f, 0.987301418f, + 0.160372457f, 0.987056571f, + 0.161886394f, 0.986809402f, + 0.163399949f, 0.986559910f, + 0.164913120f, 0.986308097f, + 0.166425904f, 0.986053963f, + 0.167938295f, 0.985797509f, + 0.169450291f, 0.985538735f, + 0.170961889f, 0.985277642f, + 0.172473084f, 0.985014231f, + 0.173983873f, 0.984748502f, + 0.175494253f, 0.984480455f, + 0.177004220f, 0.984210092f, + 0.178513771f, 0.983937413f, + 0.180022901f, 0.983662419f, + 0.181531608f, 0.983385110f, + 0.183039888f, 0.983105487f, + 0.184547737f, 0.982823551f, + 0.186055152f, 0.982539302f, + 0.187562129f, 0.982252741f, + 0.189068664f, 0.981963869f, + 0.190574755f, 0.981672686f, + 0.192080397f, 0.981379193f, + 0.193585587f, 0.981083391f, + 0.195090322f, 0.980785280f, + 0.196594598f, 0.980484862f, + 0.198098411f, 0.980182136f, + 0.199601758f, 0.979877104f, + 0.201104635f, 0.979569766f, + 0.202607039f, 0.979260123f, + 0.204108966f, 0.978948175f, + 0.205610413f, 0.978633924f, + 0.207111376f, 0.978317371f, + 0.208611852f, 0.977998515f, + 0.210111837f, 0.977677358f, + 0.211611327f, 0.977353900f, + 0.213110320f, 0.977028143f, + 0.214608811f, 0.976700086f, + 0.216106797f, 0.976369731f, + 0.217604275f, 0.976037079f, + 0.219101240f, 0.975702130f, + 0.220597690f, 0.975364885f, + 0.222093621f, 0.975025345f, + 0.223589029f, 0.974683511f, + 0.225083911f, 0.974339383f, + 0.226578264f, 0.973992962f, + 0.228072083f, 0.973644250f, + 0.229565366f, 0.973293246f, + 0.231058108f, 0.972939952f, + 0.232550307f, 0.972584369f, + 0.234041959f, 0.972226497f, + 0.235533059f, 0.971866337f, + 0.237023606f, 0.971503891f, + 0.238513595f, 0.971139158f, + 0.240003022f, 0.970772141f, + 0.241491885f, 0.970402839f, + 0.242980180f, 0.970031253f, + 0.244467903f, 0.969657385f, + 0.245955050f, 0.969281235f, + 0.247441619f, 0.968902805f, + 0.248927606f, 0.968522094f, + 0.250413007f, 0.968139105f, + 0.251897818f, 0.967753837f, + 0.253382037f, 0.967366292f, + 0.254865660f, 0.966976471f, + 0.256348682f, 0.966584374f, + 0.257831102f, 0.966190003f, + 0.259312915f, 0.965793359f, + 0.260794118f, 0.965394442f, + 0.262274707f, 0.964993253f, + 0.263754679f, 0.964589793f, + 0.265234030f, 0.964184064f, + 0.266712757f, 0.963776066f, + 0.268190857f, 0.963365800f, + 0.269668326f, 0.962953267f, + 0.271145160f, 0.962538468f, + 0.272621355f, 0.962121404f, + 0.274096910f, 0.961702077f, + 0.275571819f, 0.961280486f, + 0.277046080f, 0.960856633f, + 0.278519689f, 0.960430519f, + 0.279992643f, 0.960002146f, + 0.281464938f, 0.959571513f, + 0.282936570f, 0.959138622f, + 0.284407537f, 0.958703475f, + 0.285877835f, 0.958266071f, + 0.287347460f, 0.957826413f, + 0.288816408f, 0.957384501f, + 0.290284677f, 0.956940336f, + 0.291752263f, 0.956493919f, + 0.293219163f, 0.956045251f, + 0.294685372f, 0.955594334f, + 0.296150888f, 0.955141168f, + 0.297615707f, 0.954685755f, + 0.299079826f, 0.954228095f, + 0.300543241f, 0.953768190f, + 0.302005949f, 0.953306040f, + 0.303467947f, 0.952841648f, + 0.304929230f, 0.952375013f, + 0.306389795f, 0.951906137f, + 0.307849640f, 0.951435021f, + 0.309308760f, 0.950961666f, + 0.310767153f, 0.950486074f, + 0.312224814f, 0.950008245f, + 0.313681740f, 0.949528181f, + 0.315137929f, 0.949045882f, + 0.316593376f, 0.948561350f, + 0.318048077f, 0.948074586f, + 0.319502031f, 0.947585591f, + 0.320955232f, 0.947094366f, + 0.322407679f, 0.946600913f, + 0.323859367f, 0.946105232f, + 0.325310292f, 0.945607325f, + 0.326760452f, 0.945107193f, + 0.328209844f, 0.944604837f, + 0.329658463f, 0.944100258f, + 0.331106306f, 0.943593458f, + 0.332553370f, 0.943084437f, + 0.333999651f, 0.942573198f, + 0.335445147f, 0.942059740f, + 0.336889853f, 0.941544065f, + 0.338333767f, 0.941026175f, + 0.339776884f, 0.940506071f, + 0.341219202f, 0.939983753f, + 0.342660717f, 0.939459224f, + 0.344101426f, 0.938932484f, + 0.345541325f, 0.938403534f, + 0.346980411f, 0.937872376f, + 0.348418680f, 0.937339012f, + 0.349856130f, 0.936803442f, + 0.351292756f, 0.936265667f, + 0.352728556f, 0.935725689f, + 0.354163525f, 0.935183510f, + 0.355597662f, 0.934639130f, + 0.357030961f, 0.934092550f, + 0.358463421f, 0.933543773f, + 0.359895037f, 0.932992799f, + 0.361325806f, 0.932439629f, + 0.362755724f, 0.931884266f, + 0.364184790f, 0.931326709f, + 0.365612998f, 0.930766961f, + 0.367040346f, 0.930205023f, + 0.368466830f, 0.929640896f, + 0.369892447f, 0.929074581f, + 0.371317194f, 0.928506080f, + 0.372741067f, 0.927935395f, + 0.374164063f, 0.927362526f, + 0.375586178f, 0.926787474f, + 0.377007410f, 0.926210242f, + 0.378427755f, 0.925630831f, + 0.379847209f, 0.925049241f, + 0.381265769f, 0.924465474f, + 0.382683432f, 0.923879533f, + 0.384100195f, 0.923291417f, + 0.385516054f, 0.922701128f, + 0.386931006f, 0.922108669f, + 0.388345047f, 0.921514039f, + 0.389758174f, 0.920917242f, + 0.391170384f, 0.920318277f, + 0.392581674f, 0.919717146f, + 0.393992040f, 0.919113852f, + 0.395401479f, 0.918508394f, + 0.396809987f, 0.917900776f, + 0.398217562f, 0.917290997f, + 0.399624200f, 0.916679060f, + 0.401029897f, 0.916064966f, + 0.402434651f, 0.915448716f, + 0.403838458f, 0.914830312f, + 0.405241314f, 0.914209756f, + 0.406643217f, 0.913587048f, + 0.408044163f, 0.912962190f, + 0.409444149f, 0.912335185f, + 0.410843171f, 0.911706032f, + 0.412241227f, 0.911074734f, + 0.413638312f, 0.910441292f, + 0.415034424f, 0.909805708f, + 0.416429560f, 0.909167983f, + 0.417823716f, 0.908528119f, + 0.419216888f, 0.907886116f, + 0.420609074f, 0.907241978f, + 0.422000271f, 0.906595705f, + 0.423390474f, 0.905947298f, + 0.424779681f, 0.905296759f, + 0.426167889f, 0.904644091f, + 0.427555093f, 0.903989293f, + 0.428941292f, 0.903332368f, + 0.430326481f, 0.902673318f, + 0.431710658f, 0.902012144f, + 0.433093819f, 0.901348847f, + 0.434475961f, 0.900683429f, + 0.435857080f, 0.900015892f, + 0.437237174f, 0.899346237f, + 0.438616239f, 0.898674466f, + 0.439994271f, 0.898000580f, + 0.441371269f, 0.897324581f, + 0.442747228f, 0.896646470f, + 0.444122145f, 0.895966250f, + 0.445496017f, 0.895283921f, + 0.446868840f, 0.894599486f, + 0.448240612f, 0.893912945f, + 0.449611330f, 0.893224301f, + 0.450980989f, 0.892533555f, + 0.452349587f, 0.891840709f, + 0.453717121f, 0.891145765f, + 0.455083587f, 0.890448723f, + 0.456448982f, 0.889749586f, + 0.457813304f, 0.889048356f, + 0.459176548f, 0.888345033f, + 0.460538711f, 0.887639620f, + 0.461899791f, 0.886932119f, + 0.463259784f, 0.886222530f, + 0.464618686f, 0.885510856f, + 0.465976496f, 0.884797098f, + 0.467333209f, 0.884081259f, + 0.468688822f, 0.883363339f, + 0.470043332f, 0.882643340f, + 0.471396737f, 0.881921264f, + 0.472749032f, 0.881197113f, + 0.474100215f, 0.880470889f, + 0.475450282f, 0.879742593f, + 0.476799230f, 0.879012226f, + 0.478147056f, 0.878279792f, + 0.479493758f, 0.877545290f, + 0.480839331f, 0.876808724f, + 0.482183772f, 0.876070094f, + 0.483527079f, 0.875329403f, + 0.484869248f, 0.874586652f, + 0.486210276f, 0.873841843f, + 0.487550160f, 0.873094978f, + 0.488888897f, 0.872346059f, + 0.490226483f, 0.871595087f, + 0.491562916f, 0.870842063f, + 0.492898192f, 0.870086991f, + 0.494232309f, 0.869329871f, + 0.495565262f, 0.868570706f, + 0.496897049f, 0.867809497f, + 0.498227667f, 0.867046246f, + 0.499557113f, 0.866280954f, + 0.500885383f, 0.865513624f, + 0.502212474f, 0.864744258f, + 0.503538384f, 0.863972856f, + 0.504863109f, 0.863199422f, + 0.506186645f, 0.862423956f, + 0.507508991f, 0.861646461f, + 0.508830143f, 0.860866939f, + 0.510150097f, 0.860085390f, + 0.511468850f, 0.859301818f, + 0.512786401f, 0.858516224f, + 0.514102744f, 0.857728610f, + 0.515417878f, 0.856938977f, + 0.516731799f, 0.856147328f, + 0.518044504f, 0.855353665f, + 0.519355990f, 0.854557988f, + 0.520666254f, 0.853760301f, + 0.521975293f, 0.852960605f, + 0.523283103f, 0.852158902f, + 0.524589683f, 0.851355193f, + 0.525895027f, 0.850549481f, + 0.527199135f, 0.849741768f, + 0.528502002f, 0.848932055f, + 0.529803625f, 0.848120345f, + 0.531104001f, 0.847306639f, + 0.532403128f, 0.846490939f, + 0.533701002f, 0.845673247f, + 0.534997620f, 0.844853565f, + 0.536292979f, 0.844031895f, + 0.537587076f, 0.843208240f, + 0.538879909f, 0.842382600f, + 0.540171473f, 0.841554977f, + 0.541461766f, 0.840725375f, + 0.542750785f, 0.839893794f, + 0.544038527f, 0.839060237f, + 0.545324988f, 0.838224706f, + 0.546610167f, 0.837387202f, + 0.547894059f, 0.836547727f, + 0.549176662f, 0.835706284f, + 0.550457973f, 0.834862875f, + 0.551737988f, 0.834017501f, + 0.553016706f, 0.833170165f, + 0.554294121f, 0.832320868f, + 0.555570233f, 0.831469612f, + 0.556845037f, 0.830616400f, + 0.558118531f, 0.829761234f, + 0.559390712f, 0.828904115f, + 0.560661576f, 0.828045045f, + 0.561931121f, 0.827184027f, + 0.563199344f, 0.826321063f, + 0.564466242f, 0.825456154f, + 0.565731811f, 0.824589303f, + 0.566996049f, 0.823720511f, + 0.568258953f, 0.822849781f, + 0.569520519f, 0.821977115f, + 0.570780746f, 0.821102515f, + 0.572039629f, 0.820225983f, + 0.573297167f, 0.819347520f, + 0.574553355f, 0.818467130f, + 0.575808191f, 0.817584813f, + 0.577061673f, 0.816700573f, + 0.578313796f, 0.815814411f, + 0.579564559f, 0.814926329f, + 0.580813958f, 0.814036330f, + 0.582061990f, 0.813144415f, + 0.583308653f, 0.812250587f, + 0.584553943f, 0.811354847f, + 0.585797857f, 0.810457198f, + 0.587040394f, 0.809557642f, + 0.588281548f, 0.808656182f, + 0.589521319f, 0.807752818f, + 0.590759702f, 0.806847554f, + 0.591996695f, 0.805940391f, + 0.593232295f, 0.805031331f, + 0.594466499f, 0.804120377f, + 0.595699304f, 0.803207531f, + 0.596930708f, 0.802292796f, + 0.598160707f, 0.801376172f, + 0.599389298f, 0.800457662f, + 0.600616479f, 0.799537269f, + 0.601842247f, 0.798614995f, + 0.603066599f, 0.797690841f, + 0.604289531f, 0.796764810f, + 0.605511041f, 0.795836905f, + 0.606731127f, 0.794907126f, + 0.607949785f, 0.793975478f, + 0.609167012f, 0.793041960f, + 0.610382806f, 0.792106577f, + 0.611597164f, 0.791169330f, + 0.612810082f, 0.790230221f, + 0.614021559f, 0.789289253f, + 0.615231591f, 0.788346428f, + 0.616440175f, 0.787401747f, + 0.617647308f, 0.786455214f, + 0.618852988f, 0.785506830f, + 0.620057212f, 0.784556597f, + 0.621259977f, 0.783604519f, + 0.622461279f, 0.782650596f, + 0.623661118f, 0.781694832f, + 0.624859488f, 0.780737229f, + 0.626056388f, 0.779777788f, + 0.627251815f, 0.778816512f, + 0.628445767f, 0.777853404f, + 0.629638239f, 0.776888466f, + 0.630829230f, 0.775921699f, + 0.632018736f, 0.774953107f, + 0.633206755f, 0.773982691f, + 0.634393284f, 0.773010453f, + 0.635578320f, 0.772036397f, + 0.636761861f, 0.771060524f, + 0.637943904f, 0.770082837f, + 0.639124445f, 0.769103338f, + 0.640303482f, 0.768122029f, + 0.641481013f, 0.767138912f, + 0.642657034f, 0.766153990f, + 0.643831543f, 0.765167266f, + 0.645004537f, 0.764178741f, + 0.646176013f, 0.763188417f, + 0.647345969f, 0.762196298f, + 0.648514401f, 0.761202385f, + 0.649681307f, 0.760206682f, + 0.650846685f, 0.759209189f, + 0.652010531f, 0.758209910f, + 0.653172843f, 0.757208847f, + 0.654333618f, 0.756206001f, + 0.655492853f, 0.755201377f, + 0.656650546f, 0.754194975f, + 0.657806693f, 0.753186799f, + 0.658961293f, 0.752176850f, + 0.660114342f, 0.751165132f, + 0.661265838f, 0.750151646f, + 0.662415778f, 0.749136395f, + 0.663564159f, 0.748119380f, + 0.664710978f, 0.747100606f, + 0.665856234f, 0.746080074f, + 0.666999922f, 0.745057785f, + 0.668142041f, 0.744033744f, + 0.669282588f, 0.743007952f, + 0.670421560f, 0.741980412f, + 0.671558955f, 0.740951125f, + 0.672694769f, 0.739920095f, + 0.673829000f, 0.738887324f, + 0.674961646f, 0.737852815f, + 0.676092704f, 0.736816569f, + 0.677222170f, 0.735778589f, + 0.678350043f, 0.734738878f, + 0.679476320f, 0.733697438f, + 0.680600998f, 0.732654272f, + 0.681724074f, 0.731609381f, + 0.682845546f, 0.730562769f, + 0.683965412f, 0.729514438f, + 0.685083668f, 0.728464390f, + 0.686200312f, 0.727412629f, + 0.687315341f, 0.726359155f, + 0.688428753f, 0.725303972f, + 0.689540545f, 0.724247083f, + 0.690650714f, 0.723188489f, + 0.691759258f, 0.722128194f, + 0.692866175f, 0.721066199f, + 0.693971461f, 0.720002508f, + 0.695075114f, 0.718937122f, + 0.696177131f, 0.717870045f, + 0.697277511f, 0.716801279f, + 0.698376249f, 0.715730825f, + 0.699473345f, 0.714658688f, + 0.700568794f, 0.713584869f, + 0.701662595f, 0.712509371f, + 0.702754744f, 0.711432196f, + 0.703845241f, 0.710353347f, + 0.704934080f, 0.709272826f, + 0.706021261f, 0.708190637f, + 0.707106781f, 0.707106781f, + 0.708190637f, 0.706021261f, + 0.709272826f, 0.704934080f, + 0.710353347f, 0.703845241f, + 0.711432196f, 0.702754744f, + 0.712509371f, 0.701662595f, + 0.713584869f, 0.700568794f, + 0.714658688f, 0.699473345f, + 0.715730825f, 0.698376249f, + 0.716801279f, 0.697277511f, + 0.717870045f, 0.696177131f, + 0.718937122f, 0.695075114f, + 0.720002508f, 0.693971461f, + 0.721066199f, 0.692866175f, + 0.722128194f, 0.691759258f, + 0.723188489f, 0.690650714f, + 0.724247083f, 0.689540545f, + 0.725303972f, 0.688428753f, + 0.726359155f, 0.687315341f, + 0.727412629f, 0.686200312f, + 0.728464390f, 0.685083668f, + 0.729514438f, 0.683965412f, + 0.730562769f, 0.682845546f, + 0.731609381f, 0.681724074f, + 0.732654272f, 0.680600998f, + 0.733697438f, 0.679476320f, + 0.734738878f, 0.678350043f, + 0.735778589f, 0.677222170f, + 0.736816569f, 0.676092704f, + 0.737852815f, 0.674961646f, + 0.738887324f, 0.673829000f, + 0.739920095f, 0.672694769f, + 0.740951125f, 0.671558955f, + 0.741980412f, 0.670421560f, + 0.743007952f, 0.669282588f, + 0.744033744f, 0.668142041f, + 0.745057785f, 0.666999922f, + 0.746080074f, 0.665856234f, + 0.747100606f, 0.664710978f, + 0.748119380f, 0.663564159f, + 0.749136395f, 0.662415778f, + 0.750151646f, 0.661265838f, + 0.751165132f, 0.660114342f, + 0.752176850f, 0.658961293f, + 0.753186799f, 0.657806693f, + 0.754194975f, 0.656650546f, + 0.755201377f, 0.655492853f, + 0.756206001f, 0.654333618f, + 0.757208847f, 0.653172843f, + 0.758209910f, 0.652010531f, + 0.759209189f, 0.650846685f, + 0.760206682f, 0.649681307f, + 0.761202385f, 0.648514401f, + 0.762196298f, 0.647345969f, + 0.763188417f, 0.646176013f, + 0.764178741f, 0.645004537f, + 0.765167266f, 0.643831543f, + 0.766153990f, 0.642657034f, + 0.767138912f, 0.641481013f, + 0.768122029f, 0.640303482f, + 0.769103338f, 0.639124445f, + 0.770082837f, 0.637943904f, + 0.771060524f, 0.636761861f, + 0.772036397f, 0.635578320f, + 0.773010453f, 0.634393284f, + 0.773982691f, 0.633206755f, + 0.774953107f, 0.632018736f, + 0.775921699f, 0.630829230f, + 0.776888466f, 0.629638239f, + 0.777853404f, 0.628445767f, + 0.778816512f, 0.627251815f, + 0.779777788f, 0.626056388f, + 0.780737229f, 0.624859488f, + 0.781694832f, 0.623661118f, + 0.782650596f, 0.622461279f, + 0.783604519f, 0.621259977f, + 0.784556597f, 0.620057212f, + 0.785506830f, 0.618852988f, + 0.786455214f, 0.617647308f, + 0.787401747f, 0.616440175f, + 0.788346428f, 0.615231591f, + 0.789289253f, 0.614021559f, + 0.790230221f, 0.612810082f, + 0.791169330f, 0.611597164f, + 0.792106577f, 0.610382806f, + 0.793041960f, 0.609167012f, + 0.793975478f, 0.607949785f, + 0.794907126f, 0.606731127f, + 0.795836905f, 0.605511041f, + 0.796764810f, 0.604289531f, + 0.797690841f, 0.603066599f, + 0.798614995f, 0.601842247f, + 0.799537269f, 0.600616479f, + 0.800457662f, 0.599389298f, + 0.801376172f, 0.598160707f, + 0.802292796f, 0.596930708f, + 0.803207531f, 0.595699304f, + 0.804120377f, 0.594466499f, + 0.805031331f, 0.593232295f, + 0.805940391f, 0.591996695f, + 0.806847554f, 0.590759702f, + 0.807752818f, 0.589521319f, + 0.808656182f, 0.588281548f, + 0.809557642f, 0.587040394f, + 0.810457198f, 0.585797857f, + 0.811354847f, 0.584553943f, + 0.812250587f, 0.583308653f, + 0.813144415f, 0.582061990f, + 0.814036330f, 0.580813958f, + 0.814926329f, 0.579564559f, + 0.815814411f, 0.578313796f, + 0.816700573f, 0.577061673f, + 0.817584813f, 0.575808191f, + 0.818467130f, 0.574553355f, + 0.819347520f, 0.573297167f, + 0.820225983f, 0.572039629f, + 0.821102515f, 0.570780746f, + 0.821977115f, 0.569520519f, + 0.822849781f, 0.568258953f, + 0.823720511f, 0.566996049f, + 0.824589303f, 0.565731811f, + 0.825456154f, 0.564466242f, + 0.826321063f, 0.563199344f, + 0.827184027f, 0.561931121f, + 0.828045045f, 0.560661576f, + 0.828904115f, 0.559390712f, + 0.829761234f, 0.558118531f, + 0.830616400f, 0.556845037f, + 0.831469612f, 0.555570233f, + 0.832320868f, 0.554294121f, + 0.833170165f, 0.553016706f, + 0.834017501f, 0.551737988f, + 0.834862875f, 0.550457973f, + 0.835706284f, 0.549176662f, + 0.836547727f, 0.547894059f, + 0.837387202f, 0.546610167f, + 0.838224706f, 0.545324988f, + 0.839060237f, 0.544038527f, + 0.839893794f, 0.542750785f, + 0.840725375f, 0.541461766f, + 0.841554977f, 0.540171473f, + 0.842382600f, 0.538879909f, + 0.843208240f, 0.537587076f, + 0.844031895f, 0.536292979f, + 0.844853565f, 0.534997620f, + 0.845673247f, 0.533701002f, + 0.846490939f, 0.532403128f, + 0.847306639f, 0.531104001f, + 0.848120345f, 0.529803625f, + 0.848932055f, 0.528502002f, + 0.849741768f, 0.527199135f, + 0.850549481f, 0.525895027f, + 0.851355193f, 0.524589683f, + 0.852158902f, 0.523283103f, + 0.852960605f, 0.521975293f, + 0.853760301f, 0.520666254f, + 0.854557988f, 0.519355990f, + 0.855353665f, 0.518044504f, + 0.856147328f, 0.516731799f, + 0.856938977f, 0.515417878f, + 0.857728610f, 0.514102744f, + 0.858516224f, 0.512786401f, + 0.859301818f, 0.511468850f, + 0.860085390f, 0.510150097f, + 0.860866939f, 0.508830143f, + 0.861646461f, 0.507508991f, + 0.862423956f, 0.506186645f, + 0.863199422f, 0.504863109f, + 0.863972856f, 0.503538384f, + 0.864744258f, 0.502212474f, + 0.865513624f, 0.500885383f, + 0.866280954f, 0.499557113f, + 0.867046246f, 0.498227667f, + 0.867809497f, 0.496897049f, + 0.868570706f, 0.495565262f, + 0.869329871f, 0.494232309f, + 0.870086991f, 0.492898192f, + 0.870842063f, 0.491562916f, + 0.871595087f, 0.490226483f, + 0.872346059f, 0.488888897f, + 0.873094978f, 0.487550160f, + 0.873841843f, 0.486210276f, + 0.874586652f, 0.484869248f, + 0.875329403f, 0.483527079f, + 0.876070094f, 0.482183772f, + 0.876808724f, 0.480839331f, + 0.877545290f, 0.479493758f, + 0.878279792f, 0.478147056f, + 0.879012226f, 0.476799230f, + 0.879742593f, 0.475450282f, + 0.880470889f, 0.474100215f, + 0.881197113f, 0.472749032f, + 0.881921264f, 0.471396737f, + 0.882643340f, 0.470043332f, + 0.883363339f, 0.468688822f, + 0.884081259f, 0.467333209f, + 0.884797098f, 0.465976496f, + 0.885510856f, 0.464618686f, + 0.886222530f, 0.463259784f, + 0.886932119f, 0.461899791f, + 0.887639620f, 0.460538711f, + 0.888345033f, 0.459176548f, + 0.889048356f, 0.457813304f, + 0.889749586f, 0.456448982f, + 0.890448723f, 0.455083587f, + 0.891145765f, 0.453717121f, + 0.891840709f, 0.452349587f, + 0.892533555f, 0.450980989f, + 0.893224301f, 0.449611330f, + 0.893912945f, 0.448240612f, + 0.894599486f, 0.446868840f, + 0.895283921f, 0.445496017f, + 0.895966250f, 0.444122145f, + 0.896646470f, 0.442747228f, + 0.897324581f, 0.441371269f, + 0.898000580f, 0.439994271f, + 0.898674466f, 0.438616239f, + 0.899346237f, 0.437237174f, + 0.900015892f, 0.435857080f, + 0.900683429f, 0.434475961f, + 0.901348847f, 0.433093819f, + 0.902012144f, 0.431710658f, + 0.902673318f, 0.430326481f, + 0.903332368f, 0.428941292f, + 0.903989293f, 0.427555093f, + 0.904644091f, 0.426167889f, + 0.905296759f, 0.424779681f, + 0.905947298f, 0.423390474f, + 0.906595705f, 0.422000271f, + 0.907241978f, 0.420609074f, + 0.907886116f, 0.419216888f, + 0.908528119f, 0.417823716f, + 0.909167983f, 0.416429560f, + 0.909805708f, 0.415034424f, + 0.910441292f, 0.413638312f, + 0.911074734f, 0.412241227f, + 0.911706032f, 0.410843171f, + 0.912335185f, 0.409444149f, + 0.912962190f, 0.408044163f, + 0.913587048f, 0.406643217f, + 0.914209756f, 0.405241314f, + 0.914830312f, 0.403838458f, + 0.915448716f, 0.402434651f, + 0.916064966f, 0.401029897f, + 0.916679060f, 0.399624200f, + 0.917290997f, 0.398217562f, + 0.917900776f, 0.396809987f, + 0.918508394f, 0.395401479f, + 0.919113852f, 0.393992040f, + 0.919717146f, 0.392581674f, + 0.920318277f, 0.391170384f, + 0.920917242f, 0.389758174f, + 0.921514039f, 0.388345047f, + 0.922108669f, 0.386931006f, + 0.922701128f, 0.385516054f, + 0.923291417f, 0.384100195f, + 0.923879533f, 0.382683432f, + 0.924465474f, 0.381265769f, + 0.925049241f, 0.379847209f, + 0.925630831f, 0.378427755f, + 0.926210242f, 0.377007410f, + 0.926787474f, 0.375586178f, + 0.927362526f, 0.374164063f, + 0.927935395f, 0.372741067f, + 0.928506080f, 0.371317194f, + 0.929074581f, 0.369892447f, + 0.929640896f, 0.368466830f, + 0.930205023f, 0.367040346f, + 0.930766961f, 0.365612998f, + 0.931326709f, 0.364184790f, + 0.931884266f, 0.362755724f, + 0.932439629f, 0.361325806f, + 0.932992799f, 0.359895037f, + 0.933543773f, 0.358463421f, + 0.934092550f, 0.357030961f, + 0.934639130f, 0.355597662f, + 0.935183510f, 0.354163525f, + 0.935725689f, 0.352728556f, + 0.936265667f, 0.351292756f, + 0.936803442f, 0.349856130f, + 0.937339012f, 0.348418680f, + 0.937872376f, 0.346980411f, + 0.938403534f, 0.345541325f, + 0.938932484f, 0.344101426f, + 0.939459224f, 0.342660717f, + 0.939983753f, 0.341219202f, + 0.940506071f, 0.339776884f, + 0.941026175f, 0.338333767f, + 0.941544065f, 0.336889853f, + 0.942059740f, 0.335445147f, + 0.942573198f, 0.333999651f, + 0.943084437f, 0.332553370f, + 0.943593458f, 0.331106306f, + 0.944100258f, 0.329658463f, + 0.944604837f, 0.328209844f, + 0.945107193f, 0.326760452f, + 0.945607325f, 0.325310292f, + 0.946105232f, 0.323859367f, + 0.946600913f, 0.322407679f, + 0.947094366f, 0.320955232f, + 0.947585591f, 0.319502031f, + 0.948074586f, 0.318048077f, + 0.948561350f, 0.316593376f, + 0.949045882f, 0.315137929f, + 0.949528181f, 0.313681740f, + 0.950008245f, 0.312224814f, + 0.950486074f, 0.310767153f, + 0.950961666f, 0.309308760f, + 0.951435021f, 0.307849640f, + 0.951906137f, 0.306389795f, + 0.952375013f, 0.304929230f, + 0.952841648f, 0.303467947f, + 0.953306040f, 0.302005949f, + 0.953768190f, 0.300543241f, + 0.954228095f, 0.299079826f, + 0.954685755f, 0.297615707f, + 0.955141168f, 0.296150888f, + 0.955594334f, 0.294685372f, + 0.956045251f, 0.293219163f, + 0.956493919f, 0.291752263f, + 0.956940336f, 0.290284677f, + 0.957384501f, 0.288816408f, + 0.957826413f, 0.287347460f, + 0.958266071f, 0.285877835f, + 0.958703475f, 0.284407537f, + 0.959138622f, 0.282936570f, + 0.959571513f, 0.281464938f, + 0.960002146f, 0.279992643f, + 0.960430519f, 0.278519689f, + 0.960856633f, 0.277046080f, + 0.961280486f, 0.275571819f, + 0.961702077f, 0.274096910f, + 0.962121404f, 0.272621355f, + 0.962538468f, 0.271145160f, + 0.962953267f, 0.269668326f, + 0.963365800f, 0.268190857f, + 0.963776066f, 0.266712757f, + 0.964184064f, 0.265234030f, + 0.964589793f, 0.263754679f, + 0.964993253f, 0.262274707f, + 0.965394442f, 0.260794118f, + 0.965793359f, 0.259312915f, + 0.966190003f, 0.257831102f, + 0.966584374f, 0.256348682f, + 0.966976471f, 0.254865660f, + 0.967366292f, 0.253382037f, + 0.967753837f, 0.251897818f, + 0.968139105f, 0.250413007f, + 0.968522094f, 0.248927606f, + 0.968902805f, 0.247441619f, + 0.969281235f, 0.245955050f, + 0.969657385f, 0.244467903f, + 0.970031253f, 0.242980180f, + 0.970402839f, 0.241491885f, + 0.970772141f, 0.240003022f, + 0.971139158f, 0.238513595f, + 0.971503891f, 0.237023606f, + 0.971866337f, 0.235533059f, + 0.972226497f, 0.234041959f, + 0.972584369f, 0.232550307f, + 0.972939952f, 0.231058108f, + 0.973293246f, 0.229565366f, + 0.973644250f, 0.228072083f, + 0.973992962f, 0.226578264f, + 0.974339383f, 0.225083911f, + 0.974683511f, 0.223589029f, + 0.975025345f, 0.222093621f, + 0.975364885f, 0.220597690f, + 0.975702130f, 0.219101240f, + 0.976037079f, 0.217604275f, + 0.976369731f, 0.216106797f, + 0.976700086f, 0.214608811f, + 0.977028143f, 0.213110320f, + 0.977353900f, 0.211611327f, + 0.977677358f, 0.210111837f, + 0.977998515f, 0.208611852f, + 0.978317371f, 0.207111376f, + 0.978633924f, 0.205610413f, + 0.978948175f, 0.204108966f, + 0.979260123f, 0.202607039f, + 0.979569766f, 0.201104635f, + 0.979877104f, 0.199601758f, + 0.980182136f, 0.198098411f, + 0.980484862f, 0.196594598f, + 0.980785280f, 0.195090322f, + 0.981083391f, 0.193585587f, + 0.981379193f, 0.192080397f, + 0.981672686f, 0.190574755f, + 0.981963869f, 0.189068664f, + 0.982252741f, 0.187562129f, + 0.982539302f, 0.186055152f, + 0.982823551f, 0.184547737f, + 0.983105487f, 0.183039888f, + 0.983385110f, 0.181531608f, + 0.983662419f, 0.180022901f, + 0.983937413f, 0.178513771f, + 0.984210092f, 0.177004220f, + 0.984480455f, 0.175494253f, + 0.984748502f, 0.173983873f, + 0.985014231f, 0.172473084f, + 0.985277642f, 0.170961889f, + 0.985538735f, 0.169450291f, + 0.985797509f, 0.167938295f, + 0.986053963f, 0.166425904f, + 0.986308097f, 0.164913120f, + 0.986559910f, 0.163399949f, + 0.986809402f, 0.161886394f, + 0.987056571f, 0.160372457f, + 0.987301418f, 0.158858143f, + 0.987543942f, 0.157343456f, + 0.987784142f, 0.155828398f, + 0.988022017f, 0.154312973f, + 0.988257568f, 0.152797185f, + 0.988490793f, 0.151281038f, + 0.988721692f, 0.149764535f, + 0.988950265f, 0.148247679f, + 0.989176510f, 0.146730474f, + 0.989400428f, 0.145212925f, + 0.989622017f, 0.143695033f, + 0.989841278f, 0.142176804f, + 0.990058210f, 0.140658239f, + 0.990272812f, 0.139139344f, + 0.990485084f, 0.137620122f, + 0.990695025f, 0.136100575f, + 0.990902635f, 0.134580709f, + 0.991107914f, 0.133060525f, + 0.991310860f, 0.131540029f, + 0.991511473f, 0.130019223f, + 0.991709754f, 0.128498111f, + 0.991905700f, 0.126976696f, + 0.992099313f, 0.125454983f, + 0.992290591f, 0.123932975f, + 0.992479535f, 0.122410675f, + 0.992666142f, 0.120888087f, + 0.992850414f, 0.119365215f, + 0.993032350f, 0.117842062f, + 0.993211949f, 0.116318631f, + 0.993389211f, 0.114794927f, + 0.993564136f, 0.113270952f, + 0.993736722f, 0.111746711f, + 0.993906970f, 0.110222207f, + 0.994074879f, 0.108697444f, + 0.994240449f, 0.107172425f, + 0.994403680f, 0.105647154f, + 0.994564571f, 0.104121634f, + 0.994723121f, 0.102595869f, + 0.994879331f, 0.101069863f, + 0.995033199f, 0.099543619f, + 0.995184727f, 0.098017140f, + 0.995333912f, 0.096490431f, + 0.995480755f, 0.094963495f, + 0.995625256f, 0.093436336f, + 0.995767414f, 0.091908956f, + 0.995907229f, 0.090381361f, + 0.996044701f, 0.088853553f, + 0.996179829f, 0.087325535f, + 0.996312612f, 0.085797312f, + 0.996443051f, 0.084268888f, + 0.996571146f, 0.082740265f, + 0.996696895f, 0.081211447f, + 0.996820299f, 0.079682438f, + 0.996941358f, 0.078153242f, + 0.997060070f, 0.076623861f, + 0.997176437f, 0.075094301f, + 0.997290457f, 0.073564564f, + 0.997402130f, 0.072034653f, + 0.997511456f, 0.070504573f, + 0.997618435f, 0.068974328f, + 0.997723067f, 0.067443920f, + 0.997825350f, 0.065913353f, + 0.997925286f, 0.064382631f, + 0.998022874f, 0.062851758f, + 0.998118113f, 0.061320736f, + 0.998211003f, 0.059789571f, + 0.998301545f, 0.058258265f, + 0.998389737f, 0.056726821f, + 0.998475581f, 0.055195244f, + 0.998559074f, 0.053663538f, + 0.998640218f, 0.052131705f, + 0.998719012f, 0.050599749f, + 0.998795456f, 0.049067674f, + 0.998869550f, 0.047535484f, + 0.998941293f, 0.046003182f, + 0.999010686f, 0.044470772f, + 0.999077728f, 0.042938257f, + 0.999142419f, 0.041405641f, + 0.999204759f, 0.039872928f, + 0.999264747f, 0.038340120f, + 0.999322385f, 0.036807223f, + 0.999377670f, 0.035274239f, + 0.999430605f, 0.033741172f, + 0.999481187f, 0.032208025f, + 0.999529418f, 0.030674803f, + 0.999575296f, 0.029141509f, + 0.999618822f, 0.027608146f, + 0.999659997f, 0.026074718f, + 0.999698819f, 0.024541229f, + 0.999735288f, 0.023007681f, + 0.999769405f, 0.021474080f, + 0.999801170f, 0.019940429f, + 0.999830582f, 0.018406730f, + 0.999857641f, 0.016872988f, + 0.999882347f, 0.015339206f, + 0.999904701f, 0.013805389f, + 0.999924702f, 0.012271538f, + 0.999942350f, 0.010737659f, + 0.999957645f, 0.009203755f, + 0.999970586f, 0.007669829f, + 0.999981175f, 0.006135885f, + 0.999989411f, 0.004601926f, + 0.999995294f, 0.003067957f, + 0.999998823f, 0.001533980f, + 1.000000000f, 0.000000000f, + 0.999998823f, -0.001533980f, + 0.999995294f, -0.003067957f, + 0.999989411f, -0.004601926f, + 0.999981175f, -0.006135885f, + 0.999970586f, -0.007669829f, + 0.999957645f, -0.009203755f, + 0.999942350f, -0.010737659f, + 0.999924702f, -0.012271538f, + 0.999904701f, -0.013805389f, + 0.999882347f, -0.015339206f, + 0.999857641f, -0.016872988f, + 0.999830582f, -0.018406730f, + 0.999801170f, -0.019940429f, + 0.999769405f, -0.021474080f, + 0.999735288f, -0.023007681f, + 0.999698819f, -0.024541229f, + 0.999659997f, -0.026074718f, + 0.999618822f, -0.027608146f, + 0.999575296f, -0.029141509f, + 0.999529418f, -0.030674803f, + 0.999481187f, -0.032208025f, + 0.999430605f, -0.033741172f, + 0.999377670f, -0.035274239f, + 0.999322385f, -0.036807223f, + 0.999264747f, -0.038340120f, + 0.999204759f, -0.039872928f, + 0.999142419f, -0.041405641f, + 0.999077728f, -0.042938257f, + 0.999010686f, -0.044470772f, + 0.998941293f, -0.046003182f, + 0.998869550f, -0.047535484f, + 0.998795456f, -0.049067674f, + 0.998719012f, -0.050599749f, + 0.998640218f, -0.052131705f, + 0.998559074f, -0.053663538f, + 0.998475581f, -0.055195244f, + 0.998389737f, -0.056726821f, + 0.998301545f, -0.058258265f, + 0.998211003f, -0.059789571f, + 0.998118113f, -0.061320736f, + 0.998022874f, -0.062851758f, + 0.997925286f, -0.064382631f, + 0.997825350f, -0.065913353f, + 0.997723067f, -0.067443920f, + 0.997618435f, -0.068974328f, + 0.997511456f, -0.070504573f, + 0.997402130f, -0.072034653f, + 0.997290457f, -0.073564564f, + 0.997176437f, -0.075094301f, + 0.997060070f, -0.076623861f, + 0.996941358f, -0.078153242f, + 0.996820299f, -0.079682438f, + 0.996696895f, -0.081211447f, + 0.996571146f, -0.082740265f, + 0.996443051f, -0.084268888f, + 0.996312612f, -0.085797312f, + 0.996179829f, -0.087325535f, + 0.996044701f, -0.088853553f, + 0.995907229f, -0.090381361f, + 0.995767414f, -0.091908956f, + 0.995625256f, -0.093436336f, + 0.995480755f, -0.094963495f, + 0.995333912f, -0.096490431f, + 0.995184727f, -0.098017140f, + 0.995033199f, -0.099543619f, + 0.994879331f, -0.101069863f, + 0.994723121f, -0.102595869f, + 0.994564571f, -0.104121634f, + 0.994403680f, -0.105647154f, + 0.994240449f, -0.107172425f, + 0.994074879f, -0.108697444f, + 0.993906970f, -0.110222207f, + 0.993736722f, -0.111746711f, + 0.993564136f, -0.113270952f, + 0.993389211f, -0.114794927f, + 0.993211949f, -0.116318631f, + 0.993032350f, -0.117842062f, + 0.992850414f, -0.119365215f, + 0.992666142f, -0.120888087f, + 0.992479535f, -0.122410675f, + 0.992290591f, -0.123932975f, + 0.992099313f, -0.125454983f, + 0.991905700f, -0.126976696f, + 0.991709754f, -0.128498111f, + 0.991511473f, -0.130019223f, + 0.991310860f, -0.131540029f, + 0.991107914f, -0.133060525f, + 0.990902635f, -0.134580709f, + 0.990695025f, -0.136100575f, + 0.990485084f, -0.137620122f, + 0.990272812f, -0.139139344f, + 0.990058210f, -0.140658239f, + 0.989841278f, -0.142176804f, + 0.989622017f, -0.143695033f, + 0.989400428f, -0.145212925f, + 0.989176510f, -0.146730474f, + 0.988950265f, -0.148247679f, + 0.988721692f, -0.149764535f, + 0.988490793f, -0.151281038f, + 0.988257568f, -0.152797185f, + 0.988022017f, -0.154312973f, + 0.987784142f, -0.155828398f, + 0.987543942f, -0.157343456f, + 0.987301418f, -0.158858143f, + 0.987056571f, -0.160372457f, + 0.986809402f, -0.161886394f, + 0.986559910f, -0.163399949f, + 0.986308097f, -0.164913120f, + 0.986053963f, -0.166425904f, + 0.985797509f, -0.167938295f, + 0.985538735f, -0.169450291f, + 0.985277642f, -0.170961889f, + 0.985014231f, -0.172473084f, + 0.984748502f, -0.173983873f, + 0.984480455f, -0.175494253f, + 0.984210092f, -0.177004220f, + 0.983937413f, -0.178513771f, + 0.983662419f, -0.180022901f, + 0.983385110f, -0.181531608f, + 0.983105487f, -0.183039888f, + 0.982823551f, -0.184547737f, + 0.982539302f, -0.186055152f, + 0.982252741f, -0.187562129f, + 0.981963869f, -0.189068664f, + 0.981672686f, -0.190574755f, + 0.981379193f, -0.192080397f, + 0.981083391f, -0.193585587f, + 0.980785280f, -0.195090322f, + 0.980484862f, -0.196594598f, + 0.980182136f, -0.198098411f, + 0.979877104f, -0.199601758f, + 0.979569766f, -0.201104635f, + 0.979260123f, -0.202607039f, + 0.978948175f, -0.204108966f, + 0.978633924f, -0.205610413f, + 0.978317371f, -0.207111376f, + 0.977998515f, -0.208611852f, + 0.977677358f, -0.210111837f, + 0.977353900f, -0.211611327f, + 0.977028143f, -0.213110320f, + 0.976700086f, -0.214608811f, + 0.976369731f, -0.216106797f, + 0.976037079f, -0.217604275f, + 0.975702130f, -0.219101240f, + 0.975364885f, -0.220597690f, + 0.975025345f, -0.222093621f, + 0.974683511f, -0.223589029f, + 0.974339383f, -0.225083911f, + 0.973992962f, -0.226578264f, + 0.973644250f, -0.228072083f, + 0.973293246f, -0.229565366f, + 0.972939952f, -0.231058108f, + 0.972584369f, -0.232550307f, + 0.972226497f, -0.234041959f, + 0.971866337f, -0.235533059f, + 0.971503891f, -0.237023606f, + 0.971139158f, -0.238513595f, + 0.970772141f, -0.240003022f, + 0.970402839f, -0.241491885f, + 0.970031253f, -0.242980180f, + 0.969657385f, -0.244467903f, + 0.969281235f, -0.245955050f, + 0.968902805f, -0.247441619f, + 0.968522094f, -0.248927606f, + 0.968139105f, -0.250413007f, + 0.967753837f, -0.251897818f, + 0.967366292f, -0.253382037f, + 0.966976471f, -0.254865660f, + 0.966584374f, -0.256348682f, + 0.966190003f, -0.257831102f, + 0.965793359f, -0.259312915f, + 0.965394442f, -0.260794118f, + 0.964993253f, -0.262274707f, + 0.964589793f, -0.263754679f, + 0.964184064f, -0.265234030f, + 0.963776066f, -0.266712757f, + 0.963365800f, -0.268190857f, + 0.962953267f, -0.269668326f, + 0.962538468f, -0.271145160f, + 0.962121404f, -0.272621355f, + 0.961702077f, -0.274096910f, + 0.961280486f, -0.275571819f, + 0.960856633f, -0.277046080f, + 0.960430519f, -0.278519689f, + 0.960002146f, -0.279992643f, + 0.959571513f, -0.281464938f, + 0.959138622f, -0.282936570f, + 0.958703475f, -0.284407537f, + 0.958266071f, -0.285877835f, + 0.957826413f, -0.287347460f, + 0.957384501f, -0.288816408f, + 0.956940336f, -0.290284677f, + 0.956493919f, -0.291752263f, + 0.956045251f, -0.293219163f, + 0.955594334f, -0.294685372f, + 0.955141168f, -0.296150888f, + 0.954685755f, -0.297615707f, + 0.954228095f, -0.299079826f, + 0.953768190f, -0.300543241f, + 0.953306040f, -0.302005949f, + 0.952841648f, -0.303467947f, + 0.952375013f, -0.304929230f, + 0.951906137f, -0.306389795f, + 0.951435021f, -0.307849640f, + 0.950961666f, -0.309308760f, + 0.950486074f, -0.310767153f, + 0.950008245f, -0.312224814f, + 0.949528181f, -0.313681740f, + 0.949045882f, -0.315137929f, + 0.948561350f, -0.316593376f, + 0.948074586f, -0.318048077f, + 0.947585591f, -0.319502031f, + 0.947094366f, -0.320955232f, + 0.946600913f, -0.322407679f, + 0.946105232f, -0.323859367f, + 0.945607325f, -0.325310292f, + 0.945107193f, -0.326760452f, + 0.944604837f, -0.328209844f, + 0.944100258f, -0.329658463f, + 0.943593458f, -0.331106306f, + 0.943084437f, -0.332553370f, + 0.942573198f, -0.333999651f, + 0.942059740f, -0.335445147f, + 0.941544065f, -0.336889853f, + 0.941026175f, -0.338333767f, + 0.940506071f, -0.339776884f, + 0.939983753f, -0.341219202f, + 0.939459224f, -0.342660717f, + 0.938932484f, -0.344101426f, + 0.938403534f, -0.345541325f, + 0.937872376f, -0.346980411f, + 0.937339012f, -0.348418680f, + 0.936803442f, -0.349856130f, + 0.936265667f, -0.351292756f, + 0.935725689f, -0.352728556f, + 0.935183510f, -0.354163525f, + 0.934639130f, -0.355597662f, + 0.934092550f, -0.357030961f, + 0.933543773f, -0.358463421f, + 0.932992799f, -0.359895037f, + 0.932439629f, -0.361325806f, + 0.931884266f, -0.362755724f, + 0.931326709f, -0.364184790f, + 0.930766961f, -0.365612998f, + 0.930205023f, -0.367040346f, + 0.929640896f, -0.368466830f, + 0.929074581f, -0.369892447f, + 0.928506080f, -0.371317194f, + 0.927935395f, -0.372741067f, + 0.927362526f, -0.374164063f, + 0.926787474f, -0.375586178f, + 0.926210242f, -0.377007410f, + 0.925630831f, -0.378427755f, + 0.925049241f, -0.379847209f, + 0.924465474f, -0.381265769f, + 0.923879533f, -0.382683432f, + 0.923291417f, -0.384100195f, + 0.922701128f, -0.385516054f, + 0.922108669f, -0.386931006f, + 0.921514039f, -0.388345047f, + 0.920917242f, -0.389758174f, + 0.920318277f, -0.391170384f, + 0.919717146f, -0.392581674f, + 0.919113852f, -0.393992040f, + 0.918508394f, -0.395401479f, + 0.917900776f, -0.396809987f, + 0.917290997f, -0.398217562f, + 0.916679060f, -0.399624200f, + 0.916064966f, -0.401029897f, + 0.915448716f, -0.402434651f, + 0.914830312f, -0.403838458f, + 0.914209756f, -0.405241314f, + 0.913587048f, -0.406643217f, + 0.912962190f, -0.408044163f, + 0.912335185f, -0.409444149f, + 0.911706032f, -0.410843171f, + 0.911074734f, -0.412241227f, + 0.910441292f, -0.413638312f, + 0.909805708f, -0.415034424f, + 0.909167983f, -0.416429560f, + 0.908528119f, -0.417823716f, + 0.907886116f, -0.419216888f, + 0.907241978f, -0.420609074f, + 0.906595705f, -0.422000271f, + 0.905947298f, -0.423390474f, + 0.905296759f, -0.424779681f, + 0.904644091f, -0.426167889f, + 0.903989293f, -0.427555093f, + 0.903332368f, -0.428941292f, + 0.902673318f, -0.430326481f, + 0.902012144f, -0.431710658f, + 0.901348847f, -0.433093819f, + 0.900683429f, -0.434475961f, + 0.900015892f, -0.435857080f, + 0.899346237f, -0.437237174f, + 0.898674466f, -0.438616239f, + 0.898000580f, -0.439994271f, + 0.897324581f, -0.441371269f, + 0.896646470f, -0.442747228f, + 0.895966250f, -0.444122145f, + 0.895283921f, -0.445496017f, + 0.894599486f, -0.446868840f, + 0.893912945f, -0.448240612f, + 0.893224301f, -0.449611330f, + 0.892533555f, -0.450980989f, + 0.891840709f, -0.452349587f, + 0.891145765f, -0.453717121f, + 0.890448723f, -0.455083587f, + 0.889749586f, -0.456448982f, + 0.889048356f, -0.457813304f, + 0.888345033f, -0.459176548f, + 0.887639620f, -0.460538711f, + 0.886932119f, -0.461899791f, + 0.886222530f, -0.463259784f, + 0.885510856f, -0.464618686f, + 0.884797098f, -0.465976496f, + 0.884081259f, -0.467333209f, + 0.883363339f, -0.468688822f, + 0.882643340f, -0.470043332f, + 0.881921264f, -0.471396737f, + 0.881197113f, -0.472749032f, + 0.880470889f, -0.474100215f, + 0.879742593f, -0.475450282f, + 0.879012226f, -0.476799230f, + 0.878279792f, -0.478147056f, + 0.877545290f, -0.479493758f, + 0.876808724f, -0.480839331f, + 0.876070094f, -0.482183772f, + 0.875329403f, -0.483527079f, + 0.874586652f, -0.484869248f, + 0.873841843f, -0.486210276f, + 0.873094978f, -0.487550160f, + 0.872346059f, -0.488888897f, + 0.871595087f, -0.490226483f, + 0.870842063f, -0.491562916f, + 0.870086991f, -0.492898192f, + 0.869329871f, -0.494232309f, + 0.868570706f, -0.495565262f, + 0.867809497f, -0.496897049f, + 0.867046246f, -0.498227667f, + 0.866280954f, -0.499557113f, + 0.865513624f, -0.500885383f, + 0.864744258f, -0.502212474f, + 0.863972856f, -0.503538384f, + 0.863199422f, -0.504863109f, + 0.862423956f, -0.506186645f, + 0.861646461f, -0.507508991f, + 0.860866939f, -0.508830143f, + 0.860085390f, -0.510150097f, + 0.859301818f, -0.511468850f, + 0.858516224f, -0.512786401f, + 0.857728610f, -0.514102744f, + 0.856938977f, -0.515417878f, + 0.856147328f, -0.516731799f, + 0.855353665f, -0.518044504f, + 0.854557988f, -0.519355990f, + 0.853760301f, -0.520666254f, + 0.852960605f, -0.521975293f, + 0.852158902f, -0.523283103f, + 0.851355193f, -0.524589683f, + 0.850549481f, -0.525895027f, + 0.849741768f, -0.527199135f, + 0.848932055f, -0.528502002f, + 0.848120345f, -0.529803625f, + 0.847306639f, -0.531104001f, + 0.846490939f, -0.532403128f, + 0.845673247f, -0.533701002f, + 0.844853565f, -0.534997620f, + 0.844031895f, -0.536292979f, + 0.843208240f, -0.537587076f, + 0.842382600f, -0.538879909f, + 0.841554977f, -0.540171473f, + 0.840725375f, -0.541461766f, + 0.839893794f, -0.542750785f, + 0.839060237f, -0.544038527f, + 0.838224706f, -0.545324988f, + 0.837387202f, -0.546610167f, + 0.836547727f, -0.547894059f, + 0.835706284f, -0.549176662f, + 0.834862875f, -0.550457973f, + 0.834017501f, -0.551737988f, + 0.833170165f, -0.553016706f, + 0.832320868f, -0.554294121f, + 0.831469612f, -0.555570233f, + 0.830616400f, -0.556845037f, + 0.829761234f, -0.558118531f, + 0.828904115f, -0.559390712f, + 0.828045045f, -0.560661576f, + 0.827184027f, -0.561931121f, + 0.826321063f, -0.563199344f, + 0.825456154f, -0.564466242f, + 0.824589303f, -0.565731811f, + 0.823720511f, -0.566996049f, + 0.822849781f, -0.568258953f, + 0.821977115f, -0.569520519f, + 0.821102515f, -0.570780746f, + 0.820225983f, -0.572039629f, + 0.819347520f, -0.573297167f, + 0.818467130f, -0.574553355f, + 0.817584813f, -0.575808191f, + 0.816700573f, -0.577061673f, + 0.815814411f, -0.578313796f, + 0.814926329f, -0.579564559f, + 0.814036330f, -0.580813958f, + 0.813144415f, -0.582061990f, + 0.812250587f, -0.583308653f, + 0.811354847f, -0.584553943f, + 0.810457198f, -0.585797857f, + 0.809557642f, -0.587040394f, + 0.808656182f, -0.588281548f, + 0.807752818f, -0.589521319f, + 0.806847554f, -0.590759702f, + 0.805940391f, -0.591996695f, + 0.805031331f, -0.593232295f, + 0.804120377f, -0.594466499f, + 0.803207531f, -0.595699304f, + 0.802292796f, -0.596930708f, + 0.801376172f, -0.598160707f, + 0.800457662f, -0.599389298f, + 0.799537269f, -0.600616479f, + 0.798614995f, -0.601842247f, + 0.797690841f, -0.603066599f, + 0.796764810f, -0.604289531f, + 0.795836905f, -0.605511041f, + 0.794907126f, -0.606731127f, + 0.793975478f, -0.607949785f, + 0.793041960f, -0.609167012f, + 0.792106577f, -0.610382806f, + 0.791169330f, -0.611597164f, + 0.790230221f, -0.612810082f, + 0.789289253f, -0.614021559f, + 0.788346428f, -0.615231591f, + 0.787401747f, -0.616440175f, + 0.786455214f, -0.617647308f, + 0.785506830f, -0.618852988f, + 0.784556597f, -0.620057212f, + 0.783604519f, -0.621259977f, + 0.782650596f, -0.622461279f, + 0.781694832f, -0.623661118f, + 0.780737229f, -0.624859488f, + 0.779777788f, -0.626056388f, + 0.778816512f, -0.627251815f, + 0.777853404f, -0.628445767f, + 0.776888466f, -0.629638239f, + 0.775921699f, -0.630829230f, + 0.774953107f, -0.632018736f, + 0.773982691f, -0.633206755f, + 0.773010453f, -0.634393284f, + 0.772036397f, -0.635578320f, + 0.771060524f, -0.636761861f, + 0.770082837f, -0.637943904f, + 0.769103338f, -0.639124445f, + 0.768122029f, -0.640303482f, + 0.767138912f, -0.641481013f, + 0.766153990f, -0.642657034f, + 0.765167266f, -0.643831543f, + 0.764178741f, -0.645004537f, + 0.763188417f, -0.646176013f, + 0.762196298f, -0.647345969f, + 0.761202385f, -0.648514401f, + 0.760206682f, -0.649681307f, + 0.759209189f, -0.650846685f, + 0.758209910f, -0.652010531f, + 0.757208847f, -0.653172843f, + 0.756206001f, -0.654333618f, + 0.755201377f, -0.655492853f, + 0.754194975f, -0.656650546f, + 0.753186799f, -0.657806693f, + 0.752176850f, -0.658961293f, + 0.751165132f, -0.660114342f, + 0.750151646f, -0.661265838f, + 0.749136395f, -0.662415778f, + 0.748119380f, -0.663564159f, + 0.747100606f, -0.664710978f, + 0.746080074f, -0.665856234f, + 0.745057785f, -0.666999922f, + 0.744033744f, -0.668142041f, + 0.743007952f, -0.669282588f, + 0.741980412f, -0.670421560f, + 0.740951125f, -0.671558955f, + 0.739920095f, -0.672694769f, + 0.738887324f, -0.673829000f, + 0.737852815f, -0.674961646f, + 0.736816569f, -0.676092704f, + 0.735778589f, -0.677222170f, + 0.734738878f, -0.678350043f, + 0.733697438f, -0.679476320f, + 0.732654272f, -0.680600998f, + 0.731609381f, -0.681724074f, + 0.730562769f, -0.682845546f, + 0.729514438f, -0.683965412f, + 0.728464390f, -0.685083668f, + 0.727412629f, -0.686200312f, + 0.726359155f, -0.687315341f, + 0.725303972f, -0.688428753f, + 0.724247083f, -0.689540545f, + 0.723188489f, -0.690650714f, + 0.722128194f, -0.691759258f, + 0.721066199f, -0.692866175f, + 0.720002508f, -0.693971461f, + 0.718937122f, -0.695075114f, + 0.717870045f, -0.696177131f, + 0.716801279f, -0.697277511f, + 0.715730825f, -0.698376249f, + 0.714658688f, -0.699473345f, + 0.713584869f, -0.700568794f, + 0.712509371f, -0.701662595f, + 0.711432196f, -0.702754744f, + 0.710353347f, -0.703845241f, + 0.709272826f, -0.704934080f, + 0.708190637f, -0.706021261f, + 0.707106781f, -0.707106781f, + 0.706021261f, -0.708190637f, + 0.704934080f, -0.709272826f, + 0.703845241f, -0.710353347f, + 0.702754744f, -0.711432196f, + 0.701662595f, -0.712509371f, + 0.700568794f, -0.713584869f, + 0.699473345f, -0.714658688f, + 0.698376249f, -0.715730825f, + 0.697277511f, -0.716801279f, + 0.696177131f, -0.717870045f, + 0.695075114f, -0.718937122f, + 0.693971461f, -0.720002508f, + 0.692866175f, -0.721066199f, + 0.691759258f, -0.722128194f, + 0.690650714f, -0.723188489f, + 0.689540545f, -0.724247083f, + 0.688428753f, -0.725303972f, + 0.687315341f, -0.726359155f, + 0.686200312f, -0.727412629f, + 0.685083668f, -0.728464390f, + 0.683965412f, -0.729514438f, + 0.682845546f, -0.730562769f, + 0.681724074f, -0.731609381f, + 0.680600998f, -0.732654272f, + 0.679476320f, -0.733697438f, + 0.678350043f, -0.734738878f, + 0.677222170f, -0.735778589f, + 0.676092704f, -0.736816569f, + 0.674961646f, -0.737852815f, + 0.673829000f, -0.738887324f, + 0.672694769f, -0.739920095f, + 0.671558955f, -0.740951125f, + 0.670421560f, -0.741980412f, + 0.669282588f, -0.743007952f, + 0.668142041f, -0.744033744f, + 0.666999922f, -0.745057785f, + 0.665856234f, -0.746080074f, + 0.664710978f, -0.747100606f, + 0.663564159f, -0.748119380f, + 0.662415778f, -0.749136395f, + 0.661265838f, -0.750151646f, + 0.660114342f, -0.751165132f, + 0.658961293f, -0.752176850f, + 0.657806693f, -0.753186799f, + 0.656650546f, -0.754194975f, + 0.655492853f, -0.755201377f, + 0.654333618f, -0.756206001f, + 0.653172843f, -0.757208847f, + 0.652010531f, -0.758209910f, + 0.650846685f, -0.759209189f, + 0.649681307f, -0.760206682f, + 0.648514401f, -0.761202385f, + 0.647345969f, -0.762196298f, + 0.646176013f, -0.763188417f, + 0.645004537f, -0.764178741f, + 0.643831543f, -0.765167266f, + 0.642657034f, -0.766153990f, + 0.641481013f, -0.767138912f, + 0.640303482f, -0.768122029f, + 0.639124445f, -0.769103338f, + 0.637943904f, -0.770082837f, + 0.636761861f, -0.771060524f, + 0.635578320f, -0.772036397f, + 0.634393284f, -0.773010453f, + 0.633206755f, -0.773982691f, + 0.632018736f, -0.774953107f, + 0.630829230f, -0.775921699f, + 0.629638239f, -0.776888466f, + 0.628445767f, -0.777853404f, + 0.627251815f, -0.778816512f, + 0.626056388f, -0.779777788f, + 0.624859488f, -0.780737229f, + 0.623661118f, -0.781694832f, + 0.622461279f, -0.782650596f, + 0.621259977f, -0.783604519f, + 0.620057212f, -0.784556597f, + 0.618852988f, -0.785506830f, + 0.617647308f, -0.786455214f, + 0.616440175f, -0.787401747f, + 0.615231591f, -0.788346428f, + 0.614021559f, -0.789289253f, + 0.612810082f, -0.790230221f, + 0.611597164f, -0.791169330f, + 0.610382806f, -0.792106577f, + 0.609167012f, -0.793041960f, + 0.607949785f, -0.793975478f, + 0.606731127f, -0.794907126f, + 0.605511041f, -0.795836905f, + 0.604289531f, -0.796764810f, + 0.603066599f, -0.797690841f, + 0.601842247f, -0.798614995f, + 0.600616479f, -0.799537269f, + 0.599389298f, -0.800457662f, + 0.598160707f, -0.801376172f, + 0.596930708f, -0.802292796f, + 0.595699304f, -0.803207531f, + 0.594466499f, -0.804120377f, + 0.593232295f, -0.805031331f, + 0.591996695f, -0.805940391f, + 0.590759702f, -0.806847554f, + 0.589521319f, -0.807752818f, + 0.588281548f, -0.808656182f, + 0.587040394f, -0.809557642f, + 0.585797857f, -0.810457198f, + 0.584553943f, -0.811354847f, + 0.583308653f, -0.812250587f, + 0.582061990f, -0.813144415f, + 0.580813958f, -0.814036330f, + 0.579564559f, -0.814926329f, + 0.578313796f, -0.815814411f, + 0.577061673f, -0.816700573f, + 0.575808191f, -0.817584813f, + 0.574553355f, -0.818467130f, + 0.573297167f, -0.819347520f, + 0.572039629f, -0.820225983f, + 0.570780746f, -0.821102515f, + 0.569520519f, -0.821977115f, + 0.568258953f, -0.822849781f, + 0.566996049f, -0.823720511f, + 0.565731811f, -0.824589303f, + 0.564466242f, -0.825456154f, + 0.563199344f, -0.826321063f, + 0.561931121f, -0.827184027f, + 0.560661576f, -0.828045045f, + 0.559390712f, -0.828904115f, + 0.558118531f, -0.829761234f, + 0.556845037f, -0.830616400f, + 0.555570233f, -0.831469612f, + 0.554294121f, -0.832320868f, + 0.553016706f, -0.833170165f, + 0.551737988f, -0.834017501f, + 0.550457973f, -0.834862875f, + 0.549176662f, -0.835706284f, + 0.547894059f, -0.836547727f, + 0.546610167f, -0.837387202f, + 0.545324988f, -0.838224706f, + 0.544038527f, -0.839060237f, + 0.542750785f, -0.839893794f, + 0.541461766f, -0.840725375f, + 0.540171473f, -0.841554977f, + 0.538879909f, -0.842382600f, + 0.537587076f, -0.843208240f, + 0.536292979f, -0.844031895f, + 0.534997620f, -0.844853565f, + 0.533701002f, -0.845673247f, + 0.532403128f, -0.846490939f, + 0.531104001f, -0.847306639f, + 0.529803625f, -0.848120345f, + 0.528502002f, -0.848932055f, + 0.527199135f, -0.849741768f, + 0.525895027f, -0.850549481f, + 0.524589683f, -0.851355193f, + 0.523283103f, -0.852158902f, + 0.521975293f, -0.852960605f, + 0.520666254f, -0.853760301f, + 0.519355990f, -0.854557988f, + 0.518044504f, -0.855353665f, + 0.516731799f, -0.856147328f, + 0.515417878f, -0.856938977f, + 0.514102744f, -0.857728610f, + 0.512786401f, -0.858516224f, + 0.511468850f, -0.859301818f, + 0.510150097f, -0.860085390f, + 0.508830143f, -0.860866939f, + 0.507508991f, -0.861646461f, + 0.506186645f, -0.862423956f, + 0.504863109f, -0.863199422f, + 0.503538384f, -0.863972856f, + 0.502212474f, -0.864744258f, + 0.500885383f, -0.865513624f, + 0.499557113f, -0.866280954f, + 0.498227667f, -0.867046246f, + 0.496897049f, -0.867809497f, + 0.495565262f, -0.868570706f, + 0.494232309f, -0.869329871f, + 0.492898192f, -0.870086991f, + 0.491562916f, -0.870842063f, + 0.490226483f, -0.871595087f, + 0.488888897f, -0.872346059f, + 0.487550160f, -0.873094978f, + 0.486210276f, -0.873841843f, + 0.484869248f, -0.874586652f, + 0.483527079f, -0.875329403f, + 0.482183772f, -0.876070094f, + 0.480839331f, -0.876808724f, + 0.479493758f, -0.877545290f, + 0.478147056f, -0.878279792f, + 0.476799230f, -0.879012226f, + 0.475450282f, -0.879742593f, + 0.474100215f, -0.880470889f, + 0.472749032f, -0.881197113f, + 0.471396737f, -0.881921264f, + 0.470043332f, -0.882643340f, + 0.468688822f, -0.883363339f, + 0.467333209f, -0.884081259f, + 0.465976496f, -0.884797098f, + 0.464618686f, -0.885510856f, + 0.463259784f, -0.886222530f, + 0.461899791f, -0.886932119f, + 0.460538711f, -0.887639620f, + 0.459176548f, -0.888345033f, + 0.457813304f, -0.889048356f, + 0.456448982f, -0.889749586f, + 0.455083587f, -0.890448723f, + 0.453717121f, -0.891145765f, + 0.452349587f, -0.891840709f, + 0.450980989f, -0.892533555f, + 0.449611330f, -0.893224301f, + 0.448240612f, -0.893912945f, + 0.446868840f, -0.894599486f, + 0.445496017f, -0.895283921f, + 0.444122145f, -0.895966250f, + 0.442747228f, -0.896646470f, + 0.441371269f, -0.897324581f, + 0.439994271f, -0.898000580f, + 0.438616239f, -0.898674466f, + 0.437237174f, -0.899346237f, + 0.435857080f, -0.900015892f, + 0.434475961f, -0.900683429f, + 0.433093819f, -0.901348847f, + 0.431710658f, -0.902012144f, + 0.430326481f, -0.902673318f, + 0.428941292f, -0.903332368f, + 0.427555093f, -0.903989293f, + 0.426167889f, -0.904644091f, + 0.424779681f, -0.905296759f, + 0.423390474f, -0.905947298f, + 0.422000271f, -0.906595705f, + 0.420609074f, -0.907241978f, + 0.419216888f, -0.907886116f, + 0.417823716f, -0.908528119f, + 0.416429560f, -0.909167983f, + 0.415034424f, -0.909805708f, + 0.413638312f, -0.910441292f, + 0.412241227f, -0.911074734f, + 0.410843171f, -0.911706032f, + 0.409444149f, -0.912335185f, + 0.408044163f, -0.912962190f, + 0.406643217f, -0.913587048f, + 0.405241314f, -0.914209756f, + 0.403838458f, -0.914830312f, + 0.402434651f, -0.915448716f, + 0.401029897f, -0.916064966f, + 0.399624200f, -0.916679060f, + 0.398217562f, -0.917290997f, + 0.396809987f, -0.917900776f, + 0.395401479f, -0.918508394f, + 0.393992040f, -0.919113852f, + 0.392581674f, -0.919717146f, + 0.391170384f, -0.920318277f, + 0.389758174f, -0.920917242f, + 0.388345047f, -0.921514039f, + 0.386931006f, -0.922108669f, + 0.385516054f, -0.922701128f, + 0.384100195f, -0.923291417f, + 0.382683432f, -0.923879533f, + 0.381265769f, -0.924465474f, + 0.379847209f, -0.925049241f, + 0.378427755f, -0.925630831f, + 0.377007410f, -0.926210242f, + 0.375586178f, -0.926787474f, + 0.374164063f, -0.927362526f, + 0.372741067f, -0.927935395f, + 0.371317194f, -0.928506080f, + 0.369892447f, -0.929074581f, + 0.368466830f, -0.929640896f, + 0.367040346f, -0.930205023f, + 0.365612998f, -0.930766961f, + 0.364184790f, -0.931326709f, + 0.362755724f, -0.931884266f, + 0.361325806f, -0.932439629f, + 0.359895037f, -0.932992799f, + 0.358463421f, -0.933543773f, + 0.357030961f, -0.934092550f, + 0.355597662f, -0.934639130f, + 0.354163525f, -0.935183510f, + 0.352728556f, -0.935725689f, + 0.351292756f, -0.936265667f, + 0.349856130f, -0.936803442f, + 0.348418680f, -0.937339012f, + 0.346980411f, -0.937872376f, + 0.345541325f, -0.938403534f, + 0.344101426f, -0.938932484f, + 0.342660717f, -0.939459224f, + 0.341219202f, -0.939983753f, + 0.339776884f, -0.940506071f, + 0.338333767f, -0.941026175f, + 0.336889853f, -0.941544065f, + 0.335445147f, -0.942059740f, + 0.333999651f, -0.942573198f, + 0.332553370f, -0.943084437f, + 0.331106306f, -0.943593458f, + 0.329658463f, -0.944100258f, + 0.328209844f, -0.944604837f, + 0.326760452f, -0.945107193f, + 0.325310292f, -0.945607325f, + 0.323859367f, -0.946105232f, + 0.322407679f, -0.946600913f, + 0.320955232f, -0.947094366f, + 0.319502031f, -0.947585591f, + 0.318048077f, -0.948074586f, + 0.316593376f, -0.948561350f, + 0.315137929f, -0.949045882f, + 0.313681740f, -0.949528181f, + 0.312224814f, -0.950008245f, + 0.310767153f, -0.950486074f, + 0.309308760f, -0.950961666f, + 0.307849640f, -0.951435021f, + 0.306389795f, -0.951906137f, + 0.304929230f, -0.952375013f, + 0.303467947f, -0.952841648f, + 0.302005949f, -0.953306040f, + 0.300543241f, -0.953768190f, + 0.299079826f, -0.954228095f, + 0.297615707f, -0.954685755f, + 0.296150888f, -0.955141168f, + 0.294685372f, -0.955594334f, + 0.293219163f, -0.956045251f, + 0.291752263f, -0.956493919f, + 0.290284677f, -0.956940336f, + 0.288816408f, -0.957384501f, + 0.287347460f, -0.957826413f, + 0.285877835f, -0.958266071f, + 0.284407537f, -0.958703475f, + 0.282936570f, -0.959138622f, + 0.281464938f, -0.959571513f, + 0.279992643f, -0.960002146f, + 0.278519689f, -0.960430519f, + 0.277046080f, -0.960856633f, + 0.275571819f, -0.961280486f, + 0.274096910f, -0.961702077f, + 0.272621355f, -0.962121404f, + 0.271145160f, -0.962538468f, + 0.269668326f, -0.962953267f, + 0.268190857f, -0.963365800f, + 0.266712757f, -0.963776066f, + 0.265234030f, -0.964184064f, + 0.263754679f, -0.964589793f, + 0.262274707f, -0.964993253f, + 0.260794118f, -0.965394442f, + 0.259312915f, -0.965793359f, + 0.257831102f, -0.966190003f, + 0.256348682f, -0.966584374f, + 0.254865660f, -0.966976471f, + 0.253382037f, -0.967366292f, + 0.251897818f, -0.967753837f, + 0.250413007f, -0.968139105f, + 0.248927606f, -0.968522094f, + 0.247441619f, -0.968902805f, + 0.245955050f, -0.969281235f, + 0.244467903f, -0.969657385f, + 0.242980180f, -0.970031253f, + 0.241491885f, -0.970402839f, + 0.240003022f, -0.970772141f, + 0.238513595f, -0.971139158f, + 0.237023606f, -0.971503891f, + 0.235533059f, -0.971866337f, + 0.234041959f, -0.972226497f, + 0.232550307f, -0.972584369f, + 0.231058108f, -0.972939952f, + 0.229565366f, -0.973293246f, + 0.228072083f, -0.973644250f, + 0.226578264f, -0.973992962f, + 0.225083911f, -0.974339383f, + 0.223589029f, -0.974683511f, + 0.222093621f, -0.975025345f, + 0.220597690f, -0.975364885f, + 0.219101240f, -0.975702130f, + 0.217604275f, -0.976037079f, + 0.216106797f, -0.976369731f, + 0.214608811f, -0.976700086f, + 0.213110320f, -0.977028143f, + 0.211611327f, -0.977353900f, + 0.210111837f, -0.977677358f, + 0.208611852f, -0.977998515f, + 0.207111376f, -0.978317371f, + 0.205610413f, -0.978633924f, + 0.204108966f, -0.978948175f, + 0.202607039f, -0.979260123f, + 0.201104635f, -0.979569766f, + 0.199601758f, -0.979877104f, + 0.198098411f, -0.980182136f, + 0.196594598f, -0.980484862f, + 0.195090322f, -0.980785280f, + 0.193585587f, -0.981083391f, + 0.192080397f, -0.981379193f, + 0.190574755f, -0.981672686f, + 0.189068664f, -0.981963869f, + 0.187562129f, -0.982252741f, + 0.186055152f, -0.982539302f, + 0.184547737f, -0.982823551f, + 0.183039888f, -0.983105487f, + 0.181531608f, -0.983385110f, + 0.180022901f, -0.983662419f, + 0.178513771f, -0.983937413f, + 0.177004220f, -0.984210092f, + 0.175494253f, -0.984480455f, + 0.173983873f, -0.984748502f, + 0.172473084f, -0.985014231f, + 0.170961889f, -0.985277642f, + 0.169450291f, -0.985538735f, + 0.167938295f, -0.985797509f, + 0.166425904f, -0.986053963f, + 0.164913120f, -0.986308097f, + 0.163399949f, -0.986559910f, + 0.161886394f, -0.986809402f, + 0.160372457f, -0.987056571f, + 0.158858143f, -0.987301418f, + 0.157343456f, -0.987543942f, + 0.155828398f, -0.987784142f, + 0.154312973f, -0.988022017f, + 0.152797185f, -0.988257568f, + 0.151281038f, -0.988490793f, + 0.149764535f, -0.988721692f, + 0.148247679f, -0.988950265f, + 0.146730474f, -0.989176510f, + 0.145212925f, -0.989400428f, + 0.143695033f, -0.989622017f, + 0.142176804f, -0.989841278f, + 0.140658239f, -0.990058210f, + 0.139139344f, -0.990272812f, + 0.137620122f, -0.990485084f, + 0.136100575f, -0.990695025f, + 0.134580709f, -0.990902635f, + 0.133060525f, -0.991107914f, + 0.131540029f, -0.991310860f, + 0.130019223f, -0.991511473f, + 0.128498111f, -0.991709754f, + 0.126976696f, -0.991905700f, + 0.125454983f, -0.992099313f, + 0.123932975f, -0.992290591f, + 0.122410675f, -0.992479535f, + 0.120888087f, -0.992666142f, + 0.119365215f, -0.992850414f, + 0.117842062f, -0.993032350f, + 0.116318631f, -0.993211949f, + 0.114794927f, -0.993389211f, + 0.113270952f, -0.993564136f, + 0.111746711f, -0.993736722f, + 0.110222207f, -0.993906970f, + 0.108697444f, -0.994074879f, + 0.107172425f, -0.994240449f, + 0.105647154f, -0.994403680f, + 0.104121634f, -0.994564571f, + 0.102595869f, -0.994723121f, + 0.101069863f, -0.994879331f, + 0.099543619f, -0.995033199f, + 0.098017140f, -0.995184727f, + 0.096490431f, -0.995333912f, + 0.094963495f, -0.995480755f, + 0.093436336f, -0.995625256f, + 0.091908956f, -0.995767414f, + 0.090381361f, -0.995907229f, + 0.088853553f, -0.996044701f, + 0.087325535f, -0.996179829f, + 0.085797312f, -0.996312612f, + 0.084268888f, -0.996443051f, + 0.082740265f, -0.996571146f, + 0.081211447f, -0.996696895f, + 0.079682438f, -0.996820299f, + 0.078153242f, -0.996941358f, + 0.076623861f, -0.997060070f, + 0.075094301f, -0.997176437f, + 0.073564564f, -0.997290457f, + 0.072034653f, -0.997402130f, + 0.070504573f, -0.997511456f, + 0.068974328f, -0.997618435f, + 0.067443920f, -0.997723067f, + 0.065913353f, -0.997825350f, + 0.064382631f, -0.997925286f, + 0.062851758f, -0.998022874f, + 0.061320736f, -0.998118113f, + 0.059789571f, -0.998211003f, + 0.058258265f, -0.998301545f, + 0.056726821f, -0.998389737f, + 0.055195244f, -0.998475581f, + 0.053663538f, -0.998559074f, + 0.052131705f, -0.998640218f, + 0.050599749f, -0.998719012f, + 0.049067674f, -0.998795456f, + 0.047535484f, -0.998869550f, + 0.046003182f, -0.998941293f, + 0.044470772f, -0.999010686f, + 0.042938257f, -0.999077728f, + 0.041405641f, -0.999142419f, + 0.039872928f, -0.999204759f, + 0.038340120f, -0.999264747f, + 0.036807223f, -0.999322385f, + 0.035274239f, -0.999377670f, + 0.033741172f, -0.999430605f, + 0.032208025f, -0.999481187f, + 0.030674803f, -0.999529418f, + 0.029141509f, -0.999575296f, + 0.027608146f, -0.999618822f, + 0.026074718f, -0.999659997f, + 0.024541229f, -0.999698819f, + 0.023007681f, -0.999735288f, + 0.021474080f, -0.999769405f, + 0.019940429f, -0.999801170f, + 0.018406730f, -0.999830582f, + 0.016872988f, -0.999857641f, + 0.015339206f, -0.999882347f, + 0.013805389f, -0.999904701f, + 0.012271538f, -0.999924702f, + 0.010737659f, -0.999942350f, + 0.009203755f, -0.999957645f, + 0.007669829f, -0.999970586f, + 0.006135885f, -0.999981175f, + 0.004601926f, -0.999989411f, + 0.003067957f, -0.999995294f, + 0.001533980f, -0.999998823f +}; + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALL_TABLES) */ + +/** + @ingroup RealFFT + */ + +/** + @addtogroup RealFFT_Table Real FFT Tables + @{ + */ + +/** + @par + Generation of realCoefA array: + @par + n = 4096 +
for (i = 0; i < n; i++)
+  {
+     pATable[2 * i]     = 0.5 * ( 1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+     pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32) +const float32_t realCoefA[8192] = { + 0.500000000000000f, -0.500000000000000f, 0.499616503715515f, -0.499999850988388f, + 0.499233007431030f, -0.499999403953552f, 0.498849511146545f, -0.499998688697815f, + 0.498466014862061f, -0.499997645616531f, 0.498082518577576f, -0.499996334314346f, + 0.497699022293091f, -0.499994695186615f, 0.497315555810928f, -0.499992787837982f, + 0.496932059526443f, -0.499990582466125f, 0.496548563241959f, -0.499988079071045f, + 0.496165096759796f, -0.499985307455063f, 0.495781600475311f, -0.499982208013535f, + 0.495398133993149f, -0.499978810548782f, 0.495014637708664f, -0.499975144863129f, + 0.494631171226501f, -0.499971181154251f, 0.494247704744339f, -0.499966919422150f, + 0.493864238262177f, -0.499962359666824f, 0.493480771780014f, -0.499957501888275f, + 0.493097305297852f, -0.499952346086502f, 0.492713838815689f, -0.499946922063828f, + 0.492330402135849f, -0.499941170215607f, 0.491946935653687f, -0.499935150146484f, + 0.491563498973846f, -0.499928832054138f, 0.491180062294006f, -0.499922215938568f, + 0.490796625614166f, -0.499915301799774f, 0.490413218736649f, -0.499908089637756f, + 0.490029782056808f, -0.499900579452515f, 0.489646375179291f, -0.499892801046371f, + 0.489262968301773f, -0.499884694814682f, 0.488879561424255f, -0.499876320362091f, + 0.488496154546738f, -0.499867647886276f, 0.488112777471542f, -0.499858677387238f, + 0.487729400396347f, -0.499849408864975f, 0.487346023321152f, -0.499839842319489f, + 0.486962646245956f, -0.499830007553101f, 0.486579269170761f, -0.499819844961166f, + 0.486195921897888f, -0.499809414148331f, 0.485812574625015f, -0.499798685312271f, + 0.485429257154465f, -0.499787658452988f, 0.485045909881592f, -0.499776333570480f, + 0.484662592411041f, -0.499764710664749f, 0.484279274940491f, -0.499752789735794f, + 0.483895987272263f, -0.499740600585938f, 0.483512699604034f, -0.499728083610535f, + 0.483129411935806f, -0.499715298414230f, 0.482746154069901f, -0.499702215194702f, + 0.482362866401672f, -0.499688833951950f, 0.481979638338089f, -0.499675154685974f, + 0.481596380472183f, -0.499661177396774f, 0.481213152408600f, -0.499646931886673f, + 0.480829954147339f, -0.499632388353348f, 0.480446726083755f, -0.499617516994476f, + 0.480063527822495f, -0.499602377414703f, 0.479680359363556f, -0.499586939811707f, + 0.479297190904617f, -0.499571204185486f, 0.478914022445679f, -0.499555170536041f, + 0.478530883789063f, -0.499538868665695f, 0.478147745132446f, -0.499522238969803f, + 0.477764606475830f, -0.499505341053009f, 0.477381497621536f, -0.499488145112991f, + 0.476998418569565f, -0.499470651149750f, 0.476615339517593f, -0.499452859163284f, + 0.476232260465622f, -0.499434769153595f, 0.475849211215973f, -0.499416410923004f, + 0.475466161966324f, -0.499397724866867f, 0.475083142518997f, -0.499378770589828f, + 0.474700123071671f, -0.499359518289566f, 0.474317133426666f, -0.499339967966080f, + 0.473934143781662f, -0.499320119619370f, 0.473551183938980f, -0.499299973249435f, + 0.473168224096298f, -0.499279528856277f, 0.472785294055939f, -0.499258816242218f, + 0.472402364015579f, -0.499237775802612f, 0.472019463777542f, -0.499216467142105f, + 0.471636593341827f, -0.499194860458374f, 0.471253722906113f, -0.499172955751419f, + 0.470870882272720f, -0.499150782823563f, 0.470488041639328f, -0.499128282070160f, + 0.470105201005936f, -0.499105513095856f, 0.469722419977188f, -0.499082416296005f, + 0.469339638948441f, -0.499059051275253f, 0.468956857919693f, -0.499035388231277f, + 0.468574106693268f, -0.499011427164078f, 0.468191385269165f, -0.498987197875977f, + 0.467808693647385f, -0.498962640762329f, 0.467426002025604f, -0.498937815427780f, + 0.467043310403824f, -0.498912662267685f, 0.466660678386688f, -0.498887240886688f, + 0.466278046369553f, -0.498861521482468f, 0.465895414352417f, -0.498835533857346f, + 0.465512841939926f, -0.498809218406677f, 0.465130269527435f, -0.498782604932785f, + 0.464747726917267f, -0.498755723237991f, 0.464365184307098f, -0.498728543519974f, + 0.463982671499252f, -0.498701065778732f, 0.463600188493729f, -0.498673290014267f, + 0.463217705488205f, -0.498645216226578f, 0.462835282087326f, -0.498616874217987f, + 0.462452858686447f, -0.498588204383850f, 0.462070435285568f, -0.498559266328812f, + 0.461688071489334f, -0.498530030250549f, 0.461305707693100f, -0.498500496149063f, + 0.460923373699188f, -0.498470664024353f, 0.460541069507599f, -0.498440563678741f, + 0.460158795118332f, -0.498410135507584f, 0.459776520729065f, -0.498379439115524f, + 0.459394276142120f, -0.498348444700241f, 0.459012061357498f, -0.498317152261734f, + 0.458629876375198f, -0.498285561800003f, 0.458247691392899f, -0.498253703117371f, + 0.457865566015244f, -0.498221516609192f, 0.457483440637589f, -0.498189061880112f, + 0.457101345062256f, -0.498156309127808f, 0.456719279289246f, -0.498123258352280f, + 0.456337243318558f, -0.498089909553528f, 0.455955207347870f, -0.498056292533875f, + 0.455573230981827f, -0.498022347688675f, 0.455191254615784f, -0.497988134622574f, + 0.454809308052063f, -0.497953623533249f, 0.454427421092987f, -0.497918814420700f, + 0.454045534133911f, -0.497883707284927f, 0.453663676977158f, -0.497848302125931f, + 0.453281819820404f, -0.497812628746033f, 0.452900022268295f, -0.497776657342911f, + 0.452518254518509f, -0.497740387916565f, 0.452136516571045f, -0.497703820466995f, + 0.451754778623581f, -0.497666954994202f, 0.451373100280762f, -0.497629791498184f, + 0.450991421937943f, -0.497592359781265f, 0.450609803199768f, -0.497554630041122f, + 0.450228184461594f, -0.497516602277756f, 0.449846625328064f, -0.497478276491165f, + 0.449465066194534f, -0.497439652681351f, 0.449083566665649f, -0.497400760650635f, + 0.448702067136765f, -0.497361570596695f, 0.448320597410202f, -0.497322082519531f, + 0.447939187288284f, -0.497282296419144f, 0.447557777166367f, -0.497242212295532f, + 0.447176426649094f, -0.497201830148697f, 0.446795076131821f, -0.497161179780960f, + 0.446413785219193f, -0.497120231389999f, 0.446032524108887f, -0.497078984975815f, + 0.445651292800903f, -0.497037440538406f, 0.445270061492920f, -0.496995598077774f, + 0.444888889789581f, -0.496953487396240f, 0.444507747888565f, -0.496911078691483f, + 0.444126635789871f, -0.496868371963501f, 0.443745553493500f, -0.496825367212296f, + 0.443364530801773f, -0.496782064437866f, 0.442983508110046f, -0.496738493442535f, + 0.442602545022964f, -0.496694594621658f, 0.442221581935883f, -0.496650427579880f, + 0.441840678453445f, -0.496605962514877f, 0.441459804773331f, -0.496561229228973f, + 0.441078960895538f, -0.496516168117523f, 0.440698176622391f, -0.496470838785172f, + 0.440317392349243f, -0.496425211429596f, 0.439936667680740f, -0.496379286050797f, + 0.439555943012238f, -0.496333062648773f, 0.439175277948380f, -0.496286571025848f, + 0.438794672489166f, -0.496239781379700f, 0.438414067029953f, -0.496192663908005f, + 0.438033521175385f, -0.496145308017731f, 0.437653005123138f, -0.496097624301910f, + 0.437272518873215f, -0.496049642562866f, 0.436892062425613f, -0.496001392602921f, + 0.436511665582657f, -0.495952844619751f, 0.436131268739700f, -0.495903998613358f, + 0.435750931501389f, -0.495854884386063f, 0.435370653867722f, -0.495805442333221f, + 0.434990376234055f, -0.495755732059479f, 0.434610158205032f, -0.495705723762512f, + 0.434229999780655f, -0.495655417442322f, 0.433849841356277f, -0.495604842901230f, + 0.433469742536545f, -0.495553970336914f, 0.433089673519135f, -0.495502769947052f, + 0.432709634304047f, -0.495451331138611f, 0.432329654693604f, -0.495399564504623f, + 0.431949704885483f, -0.495347499847412f, 0.431569814682007f, -0.495295166969299f, + 0.431189924478531f, -0.495242536067963f, 0.430810123682022f, -0.495189607143402f, + 0.430430322885513f, -0.495136409997940f, 0.430050581693649f, -0.495082914829254f, + 0.429670870304108f, -0.495029091835022f, 0.429291218519211f, -0.494975030422211f, + 0.428911596536636f, -0.494920641183853f, 0.428532034158707f, -0.494865983724594f, + 0.428152471780777f, -0.494810998439789f, 0.427772998809814f, -0.494755744934082f, + 0.427393525838852f, -0.494700223207474f, 0.427014142274857f, -0.494644373655319f, + 0.426634758710861f, -0.494588255882263f, 0.426255434751511f, -0.494531840085983f, + 0.425876170396805f, -0.494475126266479f, 0.425496935844421f, -0.494418144226074f, + 0.425117731094360f, -0.494360834360123f, 0.424738585948944f, -0.494303256273270f, + 0.424359470605850f, -0.494245409965515f, 0.423980414867401f, -0.494187235832214f, + 0.423601418733597f, -0.494128793478012f, 0.423222452402115f, -0.494070053100586f, + 0.422843515872955f, -0.494011014699936f, 0.422464638948441f, -0.493951678276062f, + 0.422085791826248f, -0.493892073631287f, 0.421707004308701f, -0.493832170963287f, + 0.421328276395798f, -0.493771970272064f, 0.420949578285217f, -0.493711471557617f, + 0.420570939779282f, -0.493650704622269f, 0.420192331075668f, -0.493589639663696f, + 0.419813781976700f, -0.493528276681900f, 0.419435262680054f, -0.493466645479202f, + 0.419056802988052f, -0.493404686450958f, 0.418678402900696f, -0.493342459201813f, + 0.418300032615662f, -0.493279963731766f, 0.417921721935272f, -0.493217140436172f, + 0.417543441057205f, -0.493154048919678f, 0.417165219783783f, -0.493090659379959f, + 0.416787058115005f, -0.493026971817017f, 0.416408926248550f, -0.492963016033173f, + 0.416030853986740f, -0.492898762226105f, 0.415652841329575f, -0.492834210395813f, + 0.415274858474731f, -0.492769360542297f, 0.414896935224533f, -0.492704242467880f, + 0.414519041776657f, -0.492638826370239f, 0.414141237735748f, -0.492573112249374f, + 0.413763463497162f, -0.492507129907608f, 0.413385748863220f, -0.492440819740295f, + 0.413008064031601f, -0.492374241352081f, 0.412630438804626f, -0.492307394742966f, + 0.412252873182297f, -0.492240220308304f, 0.411875367164612f, -0.492172777652740f, + 0.411497890949249f, -0.492105036973953f, 0.411120474338531f, -0.492037028074265f, + 0.410743117332459f, -0.491968721151352f, 0.410365819931030f, -0.491900116205215f, + 0.409988552331924f, -0.491831213235855f, 0.409611344337463f, -0.491762012243271f, + 0.409234195947647f, -0.491692543029785f, 0.408857107162476f, -0.491622805595398f, + 0.408480048179626f, -0.491552740335464f, 0.408103078603745f, -0.491482406854630f, + 0.407726138830185f, -0.491411775350571f, 0.407349258661270f, -0.491340845823288f, + 0.406972438097000f, -0.491269648075104f, 0.406595647335052f, -0.491198152303696f, + 0.406218945980072f, -0.491126358509064f, 0.405842274427414f, -0.491054296493530f, + 0.405465662479401f, -0.490981936454773f, 0.405089110136032f, -0.490909278392792f, + 0.404712617397308f, -0.490836352109909f, 0.404336184263229f, -0.490763127803802f, + 0.403959810733795f, -0.490689605474472f, 0.403583467006683f, -0.490615785121918f, + 0.403207212686539f, -0.490541696548462f, 0.402830988168716f, -0.490467309951782f, + 0.402454853057861f, -0.490392625331879f, 0.402078747749329f, -0.490317672491074f, + 0.401702702045441f, -0.490242421627045f, 0.401326715946198f, -0.490166902542114f, + 0.400950789451599f, -0.490091055631638f, 0.400574922561646f, -0.490014940500259f, + 0.400199115276337f, -0.489938557147980f, 0.399823367595673f, -0.489861875772476f, + 0.399447679519653f, -0.489784896373749f, 0.399072051048279f, -0.489707618951797f, + 0.398696482181549f, -0.489630073308945f, 0.398320972919464f, -0.489552229642868f, + 0.397945523262024f, -0.489474087953568f, 0.397570133209229f, -0.489395678043365f, + 0.397194802761078f, -0.489316970109940f, 0.396819531917572f, -0.489237964153290f, + 0.396444320678711f, -0.489158689975739f, 0.396069169044495f, -0.489079117774963f, + 0.395694077014923f, -0.488999247550964f, 0.395319044589996f, -0.488919109106064f, + 0.394944071769714f, -0.488838672637939f, 0.394569188356400f, -0.488757967948914f, + 0.394194334745407f, -0.488676935434341f, 0.393819570541382f, -0.488595664501190f, + 0.393444836139679f, -0.488514065742493f, 0.393070191144943f, -0.488432198762894f, + 0.392695605754852f, -0.488350033760071f, 0.392321079969406f, -0.488267600536346f, + 0.391946613788605f, -0.488184869289398f, 0.391572207212448f, -0.488101840019226f, + 0.391197860240936f, -0.488018542528152f, 0.390823602676392f, -0.487934947013855f, + 0.390449374914169f, -0.487851053476334f, 0.390075236558914f, -0.487766891717911f, + 0.389701157808304f, -0.487682431936264f, 0.389327138662338f, -0.487597703933716f, + 0.388953179121017f, -0.487512677907944f, 0.388579308986664f, -0.487427353858948f, + 0.388205498456955f, -0.487341761589050f, 0.387831717729568f, -0.487255871295929f, + 0.387458056211472f, -0.487169682979584f, 0.387084424495697f, -0.487083226442337f, + 0.386710882186890f, -0.486996471881866f, 0.386337369680405f, -0.486909449100494f, + 0.385963946580887f, -0.486822128295898f, 0.385590612888336f, -0.486734509468079f, + 0.385217308998108f, -0.486646622419357f, 0.384844094514847f, -0.486558437347412f, + 0.384470939636230f, -0.486469984054565f, 0.384097874164581f, -0.486381232738495f, + 0.383724838495255f, -0.486292183399200f, 0.383351892232895f, -0.486202865839005f, + 0.382979035377502f, -0.486113250255585f, 0.382606208324432f, -0.486023366451263f, + 0.382233470678329f, -0.485933154821396f, 0.381860792636871f, -0.485842704772949f, + 0.381488204002380f, -0.485751956701279f, 0.381115674972534f, -0.485660910606384f, + 0.380743205547333f, -0.485569566488266f, 0.380370795726776f, -0.485477954149246f, + 0.379998475313187f, -0.485386073589325f, 0.379626244306564f, -0.485293895006180f, + 0.379254043102264f, -0.485201418399811f, 0.378881961107254f, -0.485108673572540f, + 0.378509908914566f, -0.485015630722046f, 0.378137946128845f, -0.484922289848328f, + 0.377766042947769f, -0.484828680753708f, 0.377394229173660f, -0.484734803438187f, + 0.377022475004196f, -0.484640628099442f, 0.376650810241699f, -0.484546154737473f, + 0.376279205083847f, -0.484451413154602f, 0.375907659530640f, -0.484356373548508f, + 0.375536203384399f, -0.484261035919189f, 0.375164806842804f, -0.484165430068970f, + 0.374793499708176f, -0.484069555997849f, 0.374422252178192f, -0.483973383903503f, + 0.374051094055176f, -0.483876913785934f, 0.373679995536804f, -0.483780175447464f, + 0.373308986425400f, -0.483683139085770f, 0.372938036918640f, -0.483585834503174f, + 0.372567176818848f, -0.483488231897354f, 0.372196376323700f, -0.483390361070633f, + 0.371825665235519f, -0.483292192220688f, 0.371455013751984f, -0.483193725347519f, + 0.371084451675415f, -0.483094990253448f, 0.370713949203491f, -0.482995986938477f, + 0.370343536138535f, -0.482896685600281f, 0.369973212480545f, -0.482797086238861f, + 0.369602948427200f, -0.482697218656540f, 0.369232743978500f, -0.482597053050995f, + 0.368862658739090f, -0.482496619224548f, 0.368492603302002f, -0.482395917177200f, + 0.368122667074203f, -0.482294887304306f, 0.367752790451050f, -0.482193619012833f, + 0.367382973432541f, -0.482092022895813f, 0.367013275623322f, -0.481990188360214f, + 0.366643607616425f, -0.481888025999069f, 0.366274058818817f, -0.481785595417023f, + 0.365904569625854f, -0.481682896614075f, 0.365535169839859f, -0.481579899787903f, + 0.365165829658508f, -0.481476634740829f, 0.364796578884125f, -0.481373071670532f, + 0.364427417516708f, -0.481269240379334f, 0.364058345556259f, -0.481165111064911f, + 0.363689333200455f, -0.481060713529587f, 0.363320380449295f, -0.480956017971039f, + 0.362951546907425f, -0.480851024389267f, 0.362582772970200f, -0.480745792388916f, + 0.362214088439941f, -0.480640232563019f, 0.361845493316650f, -0.480534434318542f, + 0.361476957798004f, -0.480428308248520f, 0.361108511686325f, -0.480321943759918f, + 0.360740154981613f, -0.480215251445770f, 0.360371887683868f, -0.480108320713043f, + 0.360003679990768f, -0.480001062154770f, 0.359635561704636f, -0.479893565177917f, + 0.359267532825470f, -0.479785770177841f, 0.358899593353271f, -0.479677677154541f, + 0.358531713485718f, -0.479569315910339f, 0.358163923025131f, -0.479460656642914f, + 0.357796221971512f, -0.479351729154587f, 0.357428610324860f, -0.479242533445358f, + 0.357061088085175f, -0.479133039712906f, 0.356693625450134f, -0.479023247957230f, + 0.356326282024384f, -0.478913217782974f, 0.355958998203278f, -0.478802859783173f, + 0.355591803789139f, -0.478692263364792f, 0.355224698781967f, -0.478581339120865f, + 0.354857653379440f, -0.478470176458359f, 0.354490727186203f, -0.478358715772629f, + 0.354123860597610f, -0.478246957063675f, 0.353757113218308f, -0.478134930133820f, + 0.353390425443649f, -0.478022634983063f, 0.353023827075958f, -0.477910041809082f, + 0.352657318115234f, -0.477797180414200f, 0.352290898561478f, -0.477684020996094f, + 0.351924568414688f, -0.477570593357086f, 0.351558297872543f, -0.477456867694855f, + 0.351192146539688f, -0.477342873811722f, 0.350826084613800f, -0.477228611707687f, + 0.350460082292557f, -0.477114051580429f, 0.350094199180603f, -0.476999223232269f, + 0.349728375673294f, -0.476884096860886f, 0.349362671375275f, -0.476768702268600f, + 0.348997026681900f, -0.476653009653091f, 0.348631471395493f, -0.476537048816681f, + 0.348266035318375f, -0.476420819759369f, 0.347900658845901f, -0.476304292678833f, + 0.347535371780396f, -0.476187497377396f, 0.347170203924179f, -0.476070433855057f, + 0.346805095672607f, -0.475953072309494f, 0.346440106630325f, -0.475835442543030f, + 0.346075177192688f, -0.475717514753342f, 0.345710366964340f, -0.475599318742752f, + 0.345345616340637f, -0.475480824708939f, 0.344980984926224f, -0.475362062454224f, + 0.344616413116455f, -0.475243031978607f, 0.344251960515976f, -0.475123733282089f, + 0.343887597322464f, -0.475004136562347f, 0.343523323535919f, -0.474884241819382f, + 0.343159139156342f, -0.474764078855515f, 0.342795044183731f, -0.474643647670746f, + 0.342431038618088f, -0.474522948265076f, 0.342067122459412f, -0.474401950836182f, + 0.341703325510025f, -0.474280685186386f, 0.341339588165283f, -0.474159121513367f, + 0.340975970029831f, -0.474037289619446f, 0.340612411499023f, -0.473915189504623f, + 0.340248972177505f, -0.473792791366577f, 0.339885622262955f, -0.473670125007629f, + 0.339522391557693f, -0.473547190427780f, 0.339159220457077f, -0.473423957824707f, + 0.338796168565750f, -0.473300457000732f, 0.338433176279068f, -0.473176687955856f, + 0.338070303201675f, -0.473052620887756f, 0.337707549333572f, -0.472928285598755f, + 0.337344855070114f, -0.472803652286530f, 0.336982280015945f, -0.472678780555725f, + 0.336619764566422f, -0.472553610801697f, 0.336257368326187f, -0.472428143024445f, + 0.335895091295242f, -0.472302407026291f, 0.335532873868942f, -0.472176402807236f, + 0.335170775651932f, -0.472050130367279f, 0.334808766841888f, -0.471923559904099f, + 0.334446847438812f, -0.471796721220016f, 0.334085017442703f, -0.471669614315033f, + 0.333723306655884f, -0.471542209386826f, 0.333361685276031f, -0.471414536237717f, + 0.333000183105469f, -0.471286594867706f, 0.332638740539551f, -0.471158385276794f, + 0.332277417182922f, -0.471029877662659f, 0.331916213035584f, -0.470901101827621f, + 0.331555068492889f, -0.470772027969360f, 0.331194043159485f, -0.470642685890198f, + 0.330833107233047f, -0.470513075590134f, 0.330472290515900f, -0.470383197069168f, + 0.330111563205719f, -0.470253020524979f, 0.329750925302505f, -0.470122605562210f, + 0.329390406608582f, -0.469991862773895f, 0.329029977321625f, -0.469860881567001f, + 0.328669637441635f, -0.469729602336884f, 0.328309416770935f, -0.469598054885864f, + 0.327949285507202f, -0.469466239213943f, 0.327589273452759f, -0.469334155321121f, + 0.327229350805283f, -0.469201773405075f, 0.326869517564774f, -0.469069123268127f, + 0.326509803533554f, -0.468936175107956f, 0.326150178909302f, -0.468802988529205f, + 0.325790673494339f, -0.468669503927231f, 0.325431257486343f, -0.468535751104355f, + 0.325071930885315f, -0.468401730060577f, 0.324712723493576f, -0.468267410993576f, + 0.324353635311127f, -0.468132823705673f, 0.323994606733322f, -0.467997968196869f, + 0.323635727167130f, -0.467862844467163f, 0.323276937007904f, -0.467727422714233f, + 0.322918236255646f, -0.467591762542725f, 0.322559654712677f, -0.467455804347992f, + 0.322201162576675f, -0.467319577932358f, 0.321842789649963f, -0.467183053493500f, + 0.321484506130219f, -0.467046260833740f, 0.321126341819763f, -0.466909229755402f, + 0.320768296718597f, -0.466771900653839f, 0.320410341024399f, -0.466634273529053f, + 0.320052474737167f, -0.466496407985687f, 0.319694727659225f, -0.466358244419098f, + 0.319337099790573f, -0.466219812631607f, 0.318979561328888f, -0.466081112623215f, + 0.318622142076492f, -0.465942144393921f, 0.318264812231064f, -0.465802878141403f, + 0.317907601594925f, -0.465663343667984f, 0.317550510168076f, -0.465523540973663f, + 0.317193508148193f, -0.465383470058441f, 0.316836595535278f, -0.465243130922318f, + 0.316479831933975f, -0.465102523565292f, 0.316123157739639f, -0.464961618185043f, + 0.315766572952271f, -0.464820444583893f, 0.315410137176514f, -0.464679002761841f, + 0.315053790807724f, -0.464537292718887f, 0.314697533845901f, -0.464395314455032f, + 0.314341396093369f, -0.464253038167953f, 0.313985377550125f, -0.464110493659973f, + 0.313629478216171f, -0.463967710733414f, 0.313273668289185f, -0.463824629783630f, + 0.312917977571487f, -0.463681250810623f, 0.312562376260757f, -0.463537633419037f, + 0.312206923961639f, -0.463393747806549f, 0.311851561069489f, -0.463249564170837f, + 0.311496287584305f, -0.463105112314224f, 0.311141163110733f, -0.462960392236710f, + 0.310786128044128f, -0.462815403938293f, 0.310431212186813f, -0.462670147418976f, + 0.310076385736465f, -0.462524622678757f, 0.309721708297729f, -0.462378799915314f, + 0.309367120265961f, -0.462232738733292f, 0.309012651443481f, -0.462086379528046f, + 0.308658272027969f, -0.461939752101898f, 0.308304041624069f, -0.461792886257172f, + 0.307949900627136f, -0.461645722389221f, 0.307595878839493f, -0.461498260498047f, + 0.307241976261139f, -0.461350560188293f, 0.306888192892075f, -0.461202591657639f, + 0.306534498929977f, -0.461054325103760f, 0.306180924177170f, -0.460905820131302f, + 0.305827468633652f, -0.460757017135620f, 0.305474132299423f, -0.460607945919037f, + 0.305120915174484f, -0.460458606481552f, 0.304767817258835f, -0.460309028625488f, + 0.304414808750153f, -0.460159152746201f, 0.304061919450760f, -0.460008978843689f, + 0.303709149360657f, -0.459858566522598f, 0.303356528282166f, -0.459707885980606f, + 0.303003966808319f, -0.459556937217712f, 0.302651554346085f, -0.459405690431595f, + 0.302299261093140f, -0.459254205226898f, 0.301947087049484f, -0.459102421998978f, + 0.301595002412796f, -0.458950400352478f, 0.301243066787720f, -0.458798080682755f, + 0.300891220569611f, -0.458645492792130f, 0.300539493560791f, -0.458492636680603f, + 0.300187885761261f, -0.458339542150497f, 0.299836426973343f, -0.458186149597168f, + 0.299485057592392f, -0.458032488822937f, 0.299133807420731f, -0.457878559827805f, + 0.298782676458359f, -0.457724362611771f, 0.298431664705276f, -0.457569897174835f, + 0.298080772161484f, -0.457415163516998f, 0.297729998826981f, -0.457260161638260f, + 0.297379344701767f, -0.457104891538620f, 0.297028809785843f, -0.456949323415756f, + 0.296678394079208f, -0.456793516874313f, 0.296328097581863f, -0.456637442111969f, + 0.295977920293808f, -0.456481099128723f, 0.295627862215042f, -0.456324487924576f, + 0.295277923345566f, -0.456167578697205f, 0.294928103685379f, -0.456010431051254f, + 0.294578403234482f, -0.455853015184402f, 0.294228851795197f, -0.455695331096649f, + 0.293879389762878f, -0.455537378787994f, 0.293530046939850f, -0.455379128456116f, + 0.293180853128433f, -0.455220639705658f, 0.292831748723984f, -0.455061882734299f, + 0.292482793331146f, -0.454902857542038f, 0.292133957147598f, -0.454743564128876f, + 0.291785210371017f, -0.454584002494812f, 0.291436612606049f, -0.454424172639847f, + 0.291088134050369f, -0.454264044761658f, 0.290739774703979f, -0.454103678464890f, + 0.290391564369202f, -0.453943043947220f, 0.290043443441391f, -0.453782171010971f, + 0.289695471525192f, -0.453621000051498f, 0.289347589015961f, -0.453459560871124f, + 0.288999855518341f, -0.453297853469849f, 0.288652241230011f, -0.453135877847672f, + 0.288304775953293f, -0.452973634004593f, 0.287957400083542f, -0.452811151742935f, + 0.287610173225403f, -0.452648371458054f, 0.287263035774231f, -0.452485352754593f, + 0.286916047334671f, -0.452322036027908f, 0.286569178104401f, -0.452158480882645f, + 0.286222457885742f, -0.451994657516479f, 0.285875827074051f, -0.451830536127090f, + 0.285529345273972f, -0.451666176319122f, 0.285182982683182f, -0.451501548290253f, + 0.284836769104004f, -0.451336652040482f, 0.284490644931793f, -0.451171487569809f, + 0.284144669771194f, -0.451006084680557f, 0.283798813819885f, -0.450840383768082f, + 0.283453077077866f, -0.450674414634705f, 0.283107489347458f, -0.450508207082748f, + 0.282762020826340f, -0.450341701507568f, 0.282416671514511f, -0.450174957513809f, + 0.282071471214294f, -0.450007945299149f, 0.281726360321045f, -0.449840664863586f, + 0.281381398439407f, -0.449673116207123f, 0.281036585569382f, -0.449505299329758f, + 0.280691891908646f, -0.449337244033813f, 0.280347317457199f, -0.449168890714645f, + 0.280002862215042f, -0.449000298976898f, 0.279658555984497f, -0.448831409215927f, + 0.279314368963242f, -0.448662281036377f, 0.278970301151276f, -0.448492884635925f, + 0.278626382350922f, -0.448323249816895f, 0.278282582759857f, -0.448153316974640f, + 0.277938932180405f, -0.447983115911484f, 0.277595400810242f, -0.447812676429749f, + 0.277251988649368f, -0.447641968727112f, 0.276908725500107f, -0.447470992803574f, + 0.276565581560135f, -0.447299748659134f, 0.276222556829453f, -0.447128236293793f, + 0.275879681110382f, -0.446956485509872f, 0.275536954402924f, -0.446784436702728f, + 0.275194346904755f, -0.446612149477005f, 0.274851858615875f, -0.446439594030380f, + 0.274509519338608f, -0.446266770362854f, 0.274167299270630f, -0.446093708276749f, + 0.273825198411942f, -0.445920348167419f, 0.273483246564865f, -0.445746749639511f, + 0.273141443729401f, -0.445572882890701f, 0.272799760103226f, -0.445398747920990f, + 0.272458195686340f, -0.445224374532700f, 0.272116780281067f, -0.445049703121185f, + 0.271775513887405f, -0.444874793291092f, 0.271434366703033f, -0.444699615240097f, + 0.271093338727951f, -0.444524168968201f, 0.270752459764481f, -0.444348484277725f, + 0.270411729812622f, -0.444172531366348f, 0.270071119070053f, -0.443996280431747f, + 0.269730657339096f, -0.443819820880890f, 0.269390314817429f, -0.443643063306808f, + 0.269050091505051f, -0.443466067314148f, 0.268710047006607f, -0.443288803100586f, + 0.268370121717453f, -0.443111270666122f, 0.268030315637589f, -0.442933470010757f, + 0.267690658569336f, -0.442755430936813f, 0.267351150512695f, -0.442577123641968f, + 0.267011761665344f, -0.442398548126221f, 0.266672492027283f, -0.442219734191895f, + 0.266333401203156f, -0.442040622234344f, 0.265994429588318f, -0.441861271858215f, + 0.265655577182770f, -0.441681683063507f, 0.265316903591156f, -0.441501796245575f, + 0.264978319406509f, -0.441321671009064f, 0.264639914035797f, -0.441141277551651f, + 0.264301627874374f, -0.440960645675659f, 0.263963490724564f, -0.440779715776443f, + 0.263625472784042f, -0.440598547458649f, 0.263287603855133f, -0.440417140722275f, + 0.262949883937836f, -0.440235435962677f, 0.262612313032150f, -0.440053492784500f, + 0.262274861335754f, -0.439871311187744f, 0.261937558650970f, -0.439688831567764f, + 0.261600375175476f, -0.439506113529205f, 0.261263370513916f, -0.439323127269745f, + 0.260926485061646f, -0.439139902591705f, 0.260589718818665f, -0.438956409692764f, + 0.260253131389618f, -0.438772648572922f, 0.259916663169861f, -0.438588619232178f, + 0.259580343961716f, -0.438404351472855f, 0.259244143962860f, -0.438219845294952f, + 0.258908122777939f, -0.438035041093826f, 0.258572220802307f, -0.437849998474121f, + 0.258236467838287f, -0.437664687633514f, 0.257900834083557f, -0.437479138374329f, + 0.257565379142761f, -0.437293320894241f, 0.257230043411255f, -0.437107264995575f, + 0.256894856691360f, -0.436920911073685f, 0.256559818983078f, -0.436734348535538f, + 0.256224930286407f, -0.436547487974167f, 0.255890160799026f, -0.436360388994217f, + 0.255555540323257f, -0.436173021793365f, 0.255221068859100f, -0.435985416173935f, + 0.254886746406555f, -0.435797542333603f, 0.254552572965622f, -0.435609430074692f, + 0.254218548536301f, -0.435421019792557f, 0.253884643316269f, -0.435232400894165f, + 0.253550916910172f, -0.435043483972549f, 0.253217309713364f, -0.434854328632355f, + 0.252883851528168f, -0.434664934873581f, 0.252550542354584f, -0.434475272893906f, + 0.252217382192612f, -0.434285342693329f, 0.251884341239929f, -0.434095174074173f, + 0.251551479101181f, -0.433904737234116f, 0.251218736171722f, -0.433714061975479f, + 0.250886172056198f, -0.433523118495941f, 0.250553727149963f, -0.433331936597824f, + 0.250221431255341f, -0.433140486478806f, 0.249889299273491f, -0.432948768138886f, + 0.249557301402092f, -0.432756811380386f, 0.249225467443466f, -0.432564586400986f, + 0.248893767595291f, -0.432372123003006f, 0.248562216758728f, -0.432179391384125f, + 0.248230814933777f, -0.431986421346664f, 0.247899547219276f, -0.431793183088303f, + 0.247568443417549f, -0.431599706411362f, 0.247237488627434f, -0.431405961513519f, + 0.246906682848930f, -0.431211978197098f, 0.246576011180878f, -0.431017726659775f, + 0.246245503425598f, -0.430823236703873f, 0.245915144681931f, -0.430628478527069f, + 0.245584934949875f, -0.430433481931686f, 0.245254859328270f, -0.430238217115402f, + 0.244924947619438f, -0.430042684078217f, 0.244595184922218f, -0.429846942424774f, + 0.244265571236610f, -0.429650902748108f, 0.243936106562614f, -0.429454624652863f, + 0.243606805801392f, -0.429258108139038f, 0.243277639150620f, -0.429061323404312f, + 0.242948621511459f, -0.428864300251007f, 0.242619767785072f, -0.428667008876801f, + 0.242291063070297f, -0.428469479084015f, 0.241962507367134f, -0.428271710872650f, + 0.241634100675583f, -0.428073674440384f, 0.241305842995644f, -0.427875369787216f, + 0.240977749228477f, -0.427676826715469f, 0.240649804472923f, -0.427478045225143f, + 0.240322008728981f, -0.427278995513916f, 0.239994361996651f, -0.427079707384110f, + 0.239666879177094f, -0.426880151033401f, 0.239339530467987f, -0.426680356264114f, + 0.239012360572815f, -0.426480293273926f, 0.238685324788094f, -0.426279991865158f, + 0.238358452916145f, -0.426079452037811f, 0.238031730055809f, -0.425878643989563f, + 0.237705156207085f, -0.425677597522736f, 0.237378746271133f, -0.425476282835007f, + 0.237052485346794f, -0.425274729728699f, 0.236726388335228f, -0.425072938203812f, + 0.236400425434113f, -0.424870878458023f, 0.236074641346931f, -0.424668580293655f, + 0.235749006271362f, -0.424466013908386f, 0.235423520207405f, -0.424263238906860f, + 0.235098183155060f, -0.424060165882111f, 0.234773010015488f, -0.423856884241104f, + 0.234448000788689f, -0.423653304576874f, 0.234123140573502f, -0.423449516296387f, + 0.233798429369926f, -0.423245459794998f, 0.233473882079124f, -0.423041164875031f, + 0.233149498701096f, -0.422836631536484f, 0.232825264334679f, -0.422631829977036f, + 0.232501193881035f, -0.422426789999008f, 0.232177272439003f, -0.422221481800079f, + 0.231853514909744f, -0.422015935182571f, 0.231529906392097f, -0.421810150146484f, + 0.231206461787224f, -0.421604126691818f, 0.230883181095123f, -0.421397835016251f, + 0.230560049414635f, -0.421191304922104f, 0.230237081646919f, -0.420984506607056f, + 0.229914262890816f, -0.420777499675751f, 0.229591608047485f, -0.420570224523544f, + 0.229269117116928f, -0.420362681150436f, 0.228946775197983f, -0.420154929161072f, + 0.228624612092972f, -0.419946908950806f, 0.228302597999573f, -0.419738620519638f, + 0.227980732917786f, -0.419530123472214f, 0.227659046649933f, -0.419321358203888f, + 0.227337509393692f, -0.419112354516983f, 0.227016136050224f, -0.418903112411499f, + 0.226694911718369f, -0.418693602085114f, 0.226373866200447f, -0.418483853340149f, + 0.226052969694138f, -0.418273866176605f, 0.225732237100601f, -0.418063640594482f, + 0.225411668419838f, -0.417853146791458f, 0.225091263651848f, -0.417642414569855f, + 0.224771007895470f, -0.417431443929672f, 0.224450930953026f, -0.417220205068588f, + 0.224131003022194f, -0.417008757591248f, 0.223811239004135f, -0.416797041893005f, + 0.223491653800011f, -0.416585087776184f, 0.223172217607498f, -0.416372895240784f, + 0.222852945327759f, -0.416160434484482f, 0.222533836960793f, -0.415947735309601f, + 0.222214877605438f, -0.415734797716141f, 0.221896097064018f, -0.415521621704102f, + 0.221577480435371f, -0.415308207273483f, 0.221259027719498f, -0.415094524621964f, + 0.220940738916397f, -0.414880603551865f, 0.220622614026070f, -0.414666473865509f, + 0.220304638147354f, -0.414452046155930f, 0.219986841082573f, -0.414237409830093f, + 0.219669207930565f, -0.414022535085678f, 0.219351738691330f, -0.413807392120361f, + 0.219034433364868f, -0.413592010736465f, 0.218717306852341f, -0.413376390933990f, + 0.218400329351425f, -0.413160532712936f, 0.218083515763283f, -0.412944436073303f, + 0.217766880989075f, -0.412728071212769f, 0.217450410127640f, -0.412511497735977f, + 0.217134088277817f, -0.412294656038284f, 0.216817945241928f, -0.412077575922012f, + 0.216501981019974f, -0.411860257387161f, 0.216186165809631f, -0.411642700433731f, + 0.215870529413223f, -0.411424905061722f, 0.215555042028427f, -0.411206841468811f, + 0.215239733457565f, -0.410988569259644f, 0.214924603700638f, -0.410770028829575f, + 0.214609622955322f, -0.410551249980927f, 0.214294821023941f, -0.410332232713699f, + 0.213980183005333f, -0.410112977027893f, 0.213665723800659f, -0.409893482923508f, + 0.213351413607597f, -0.409673750400543f, 0.213037282228470f, -0.409453779459000f, + 0.212723329663277f, -0.409233570098877f, 0.212409526109695f, -0.409013092517853f, + 0.212095901370049f, -0.408792406320572f, 0.211782455444336f, -0.408571451902390f, + 0.211469158530235f, -0.408350288867950f, 0.211156040430069f, -0.408128857612610f, + 0.210843101143837f, -0.407907217741013f, 0.210530325770378f, -0.407685309648514f, + 0.210217714309692f, -0.407463163137436f, 0.209905281662941f, -0.407240778207779f, + 0.209593027830124f, -0.407018154859543f, 0.209280923008919f, -0.406795293092728f, + 0.208969011902809f, -0.406572192907333f, 0.208657249808311f, -0.406348884105682f, + 0.208345666527748f, -0.406125307083130f, 0.208034262061119f, -0.405901491641998f, + 0.207723021507263f, -0.405677437782288f, 0.207411959767342f, -0.405453115701675f, + 0.207101076841354f, -0.405228585004807f, 0.206790357828140f, -0.405003815889359f, + 0.206479802727699f, -0.404778808355331f, 0.206169426441193f, -0.404553562402725f, + 0.205859228968620f, -0.404328078031540f, 0.205549195408821f, -0.404102355241776f, + 0.205239340662956f, -0.403876423835754f, 0.204929664731026f, -0.403650224208832f, + 0.204620152711868f, -0.403423786163330f, 0.204310819506645f, -0.403197109699249f, + 0.204001650214195f, -0.402970194816589f, 0.203692659735680f, -0.402743041515350f, + 0.203383848071098f, -0.402515679597855f, 0.203075215220451f, -0.402288049459457f, + 0.202766746282578f, -0.402060180902481f, 0.202458456158638f, -0.401832103729248f, + 0.202150344848633f, -0.401603758335114f, 0.201842412352562f, -0.401375204324722f, + 0.201534643769264f, -0.401146411895752f, 0.201227053999901f, -0.400917351245880f, + 0.200919643044472f, -0.400688081979752f, 0.200612410902977f, -0.400458574295044f, + 0.200305357575417f, -0.400228828191757f, 0.199998468160629f, -0.399998843669891f, + 0.199691757559776f, -0.399768620729446f, 0.199385225772858f, -0.399538189172745f, + 0.199078872799873f, -0.399307489395142f, 0.198772698640823f, -0.399076581001282f, + 0.198466703295708f, -0.398845434188843f, 0.198160871863365f, -0.398614019155502f, + 0.197855234146118f, -0.398382395505905f, 0.197549775242805f, -0.398150533437729f, + 0.197244480252266f, -0.397918462753296f, 0.196939364075661f, -0.397686123847961f, + 0.196634441614151f, -0.397453576326370f, 0.196329683065414f, -0.397220760583878f, + 0.196025103330612f, -0.396987736225128f, 0.195720717310905f, -0.396754473447800f, + 0.195416495203972f, -0.396520972251892f, 0.195112451910973f, -0.396287262439728f, + 0.194808602333069f, -0.396053284406662f, 0.194504916667938f, -0.395819097757339f, + 0.194201424717903f, -0.395584672689438f, 0.193898096680641f, -0.395350009202957f, + 0.193594962358475f, -0.395115107297897f, 0.193292006850243f, -0.394879996776581f, + 0.192989215254784f, -0.394644618034363f, 0.192686617374420f, -0.394409030675888f, + 0.192384198307991f, -0.394173204898834f, 0.192081972956657f, -0.393937170505524f, + 0.191779911518097f, -0.393700867891312f, 0.191478043794632f, -0.393464356660843f, + 0.191176339983940f, -0.393227607011795f, 0.190874829888344f, -0.392990618944168f, + 0.190573498606682f, -0.392753422260284f, 0.190272361040115f, -0.392515957355499f, + 0.189971387386322f, -0.392278283834457f, 0.189670607447624f, -0.392040401697159f, + 0.189370006322861f, -0.391802251338959f, 0.189069598913193f, -0.391563892364502f, + 0.188769355416298f, -0.391325294971466f, 0.188469305634499f, -0.391086459159851f, + 0.188169434666634f, -0.390847414731979f, 0.187869757413864f, -0.390608131885529f, + 0.187570258975029f, -0.390368610620499f, 0.187270939350128f, -0.390128880739212f, + 0.186971798539162f, -0.389888882637024f, 0.186672851443291f, -0.389648675918579f, + 0.186374098062515f, -0.389408260583878f, 0.186075508594513f, -0.389167606830597f, + 0.185777112841606f, -0.388926714658737f, 0.185478910803795f, -0.388685584068298f, + 0.185180887579918f, -0.388444244861603f, 0.184883043169975f, -0.388202667236328f, + 0.184585392475128f, -0.387960851192474f, 0.184287920594215f, -0.387718826532364f, + 0.183990627527237f, -0.387476563453674f, 0.183693528175354f, -0.387234061956406f, + 0.183396622538567f, -0.386991351842880f, 0.183099895715714f, -0.386748403310776f, + 0.182803362607956f, -0.386505216360092f, 0.182507008314133f, -0.386261820793152f, + 0.182210832834244f, -0.386018186807632f, 0.181914865970612f, -0.385774344205856f, + 0.181619063019753f, -0.385530263185501f, 0.181323468685150f, -0.385285943746567f, + 0.181028053164482f, -0.385041415691376f, 0.180732816457748f, -0.384796649217606f, + 0.180437773466110f, -0.384551674127579f, 0.180142924189568f, -0.384306460618973f, + 0.179848253726959f, -0.384061008691788f, 0.179553776979446f, -0.383815348148346f, + 0.179259493947029f, -0.383569449186325f, 0.178965389728546f, -0.383323341608047f, + 0.178671479225159f, -0.383076995611191f, 0.178377762436867f, -0.382830440998077f, + 0.178084224462509f, -0.382583618164063f, 0.177790880203247f, -0.382336616516113f, + 0.177497729659081f, -0.382089376449585f, 0.177204772830009f, -0.381841897964478f, + 0.176911994814873f, -0.381594210863113f, 0.176619410514832f, -0.381346285343170f, + 0.176327019929886f, -0.381098151206970f, 0.176034808158875f, -0.380849778652191f, + 0.175742805004120f, -0.380601197481155f, 0.175450980663300f, -0.380352377891541f, + 0.175159350037575f, -0.380103349685669f, 0.174867913126946f, -0.379854083061218f, + 0.174576655030251f, -0.379604607820511f, 0.174285605549812f, -0.379354894161224f, + 0.173994734883308f, -0.379104942083359f, 0.173704057931900f, -0.378854811191559f, + 0.173413574695587f, -0.378604412078857f, 0.173123285174370f, -0.378353834152222f, + 0.172833189368248f, -0.378102988004684f, 0.172543287277222f, -0.377851963043213f, + 0.172253578901291f, -0.377600699663162f, 0.171964049339294f, -0.377349197864532f, + 0.171674728393555f, -0.377097487449646f, 0.171385586261749f, -0.376845568418503f, + 0.171096652746201f, -0.376593410968781f, 0.170807912945747f, -0.376341015100479f, + 0.170519351959229f, -0.376088410615921f, 0.170230999588966f, -0.375835597515106f, + 0.169942826032639f, -0.375582575798035f, 0.169654861092567f, -0.375329315662384f, + 0.169367074966431f, -0.375075817108154f, 0.169079497456551f, -0.374822109937668f, + 0.168792113661766f, -0.374568194150925f, 0.168504923582077f, -0.374314039945602f, + 0.168217927217484f, -0.374059677124023f, 0.167931124567986f, -0.373805105686188f, + 0.167644515633583f, -0.373550295829773f, 0.167358100414276f, -0.373295277357101f, + 0.167071878910065f, -0.373040050268173f, 0.166785866022110f, -0.372784584760666f, + 0.166500031948090f, -0.372528880834579f, 0.166214406490326f, -0.372272998094559f, + 0.165928974747658f, -0.372016876935959f, 0.165643751621246f, -0.371760547161102f, + 0.165358707308769f, -0.371503978967667f, 0.165073871612549f, -0.371247202157974f, + 0.164789214730263f, -0.370990216732025f, 0.164504766464233f, -0.370732992887497f, + 0.164220526814461f, -0.370475560426712f, 0.163936465978622f, -0.370217919349670f, + 0.163652613759041f, -0.369960039854050f, 0.163368955254555f, -0.369701951742172f, + 0.163085505366325f, -0.369443655014038f, 0.162802234292030f, -0.369185149669647f, + 0.162519171833992f, -0.368926405906677f, 0.162236317992210f, -0.368667453527451f, + 0.161953642964363f, -0.368408292531967f, 0.161671176552773f, -0.368148893117905f, + 0.161388918757439f, -0.367889285087585f, 0.161106839776039f, -0.367629468441010f, + 0.160824984312058f, -0.367369443178177f, 0.160543307662010f, -0.367109179496765f, + 0.160261839628220f, -0.366848707199097f, 0.159980565309525f, -0.366588026285172f, + 0.159699499607086f, -0.366327136754990f, 0.159418627619743f, -0.366066008806229f, + 0.159137964248657f, -0.365804702043533f, 0.158857494592667f, -0.365543156862259f, + 0.158577233552933f, -0.365281373262405f, 0.158297166228294f, -0.365019410848618f, + 0.158017292618752f, -0.364757210016251f, 0.157737627625465f, -0.364494800567627f, + 0.157458171248436f, -0.364232182502747f, 0.157178908586502f, -0.363969355821610f, + 0.156899839639664f, -0.363706320524216f, 0.156620979309082f, -0.363443046808243f, + 0.156342327594757f, -0.363179564476013f, 0.156063869595528f, -0.362915903329849f, + 0.155785620212555f, -0.362651973962784f, 0.155507579445839f, -0.362387865781784f, + 0.155229732394218f, -0.362123548984528f, 0.154952079057693f, -0.361858993768692f, + 0.154674649238586f, -0.361594229936600f, 0.154397398233414f, -0.361329287290573f, + 0.154120370745659f, -0.361064106225967f, 0.153843536973000f, -0.360798716545105f, + 0.153566911816597f, -0.360533088445663f, 0.153290495276451f, -0.360267281532288f, + 0.153014272451401f, -0.360001266002655f, 0.152738258242607f, -0.359735012054443f, + 0.152462437748909f, -0.359468549489975f, 0.152186840772629f, -0.359201908111572f, + 0.151911437511444f, -0.358935028314590f, 0.151636242866516f, -0.358667939901352f, + 0.151361241936684f, -0.358400642871857f, 0.151086464524269f, -0.358133137226105f, + 0.150811880826950f, -0.357865422964096f, 0.150537505745888f, -0.357597470283508f, + 0.150263324379921f, -0.357329338788986f, 0.149989366531372f, -0.357060998678207f, + 0.149715602397919f, -0.356792420148849f, 0.149442046880722f, -0.356523662805557f, + 0.149168699979782f, -0.356254696846008f, 0.148895561695099f, -0.355985492467880f, + 0.148622632026672f, -0.355716109275818f, 0.148349896073341f, -0.355446487665176f, + 0.148077383637428f, -0.355176687240601f, 0.147805064916611f, -0.354906648397446f, + 0.147532954812050f, -0.354636400938034f, 0.147261068224907f, -0.354365974664688f, + 0.146989375352860f, -0.354095309972763f, 0.146717891097069f, -0.353824466466904f, + 0.146446615457535f, -0.353553384542465f, 0.146175548434258f, -0.353282123804092f, + 0.145904675126076f, -0.353010624647141f, 0.145634025335312f, -0.352738946676254f, + 0.145363584160805f, -0.352467030286789f, 0.145093351602554f, -0.352194935083389f, + 0.144823327660561f, -0.351922631263733f, 0.144553512334824f, -0.351650089025497f, + 0.144283905625343f, -0.351377367973328f, 0.144014507532120f, -0.351104438304901f, + 0.143745318055153f, -0.350831300020218f, 0.143476337194443f, -0.350557953119278f, + 0.143207564949989f, -0.350284397602081f, 0.142939001321793f, -0.350010633468628f, + 0.142670661211014f, -0.349736660718918f, 0.142402514815331f, -0.349462509155273f, + 0.142134591937065f, -0.349188119173050f, 0.141866862773895f, -0.348913550376892f, + 0.141599357128143f, -0.348638743162155f, 0.141332060098648f, -0.348363757133484f, + 0.141064971685410f, -0.348088562488556f, 0.140798106789589f, -0.347813159227371f, + 0.140531435608864f, -0.347537547349930f, 0.140264987945557f, -0.347261756658554f, + 0.139998748898506f, -0.346985727548599f, 0.139732718467712f, -0.346709519624710f, + 0.139466896653175f, -0.346433073282242f, 0.139201298356056f, -0.346156448125839f, + 0.138935908675194f, -0.345879614353180f, 0.138670727610588f, -0.345602601766586f, + 0.138405755162239f, -0.345325350761414f, 0.138141006231308f, -0.345047920942307f, + 0.137876465916634f, -0.344770282506943f, 0.137612134218216f, -0.344492435455322f, + 0.137348011136055f, -0.344214379787445f, 0.137084111571312f, -0.343936115503311f, + 0.136820420622826f, -0.343657672405243f, 0.136556953191757f, -0.343379020690918f, + 0.136293679475784f, -0.343100160360336f, 0.136030644178391f, -0.342821091413498f, + 0.135767802596092f, -0.342541843652725f, 0.135505184531212f, -0.342262357473373f, + 0.135242775082588f, -0.341982692480087f, 0.134980589151382f, -0.341702848672867f, + 0.134718611836433f, -0.341422766447067f, 0.134456858038902f, -0.341142505407333f, + 0.134195312857628f, -0.340862035751343f, 0.133933976292610f, -0.340581357479095f, + 0.133672863245010f, -0.340300500392914f, 0.133411958813667f, -0.340019434690475f, + 0.133151277899742f, -0.339738160371780f, 0.132890805602074f, -0.339456677436829f, + 0.132630556821823f, -0.339175015687943f, 0.132370531558990f, -0.338893145322800f, + 0.132110700011253f, -0.338611096143723f, 0.131851106882095f, -0.338328808546066f, + 0.131591722369194f, -0.338046342134476f, 0.131332546472549f, -0.337763696908951f, + 0.131073594093323f, -0.337480813264847f, 0.130814850330353f, -0.337197750806808f, + 0.130556344985962f, -0.336914509534836f, 0.130298033356667f, -0.336631029844284f, + 0.130039945244789f, -0.336347371339798f, 0.129782080650330f, -0.336063534021378f, + 0.129524439573288f, -0.335779488086700f, 0.129267007112503f, -0.335495233535767f, + 0.129009798169136f, -0.335210770368576f, 0.128752797842026f, -0.334926128387451f, + 0.128496021032333f, -0.334641307592392f, 0.128239467740059f, -0.334356248378754f, + 0.127983123064041f, -0.334071010351181f, 0.127727001905441f, -0.333785593509674f, + 0.127471104264259f, -0.333499968051910f, 0.127215430140495f, -0.333214133977890f, + 0.126959964632988f, -0.332928121089935f, 0.126704722642899f, -0.332641899585724f, + 0.126449704170227f, -0.332355499267578f, 0.126194894313812f, -0.332068890333176f, + 0.125940307974815f, -0.331782072782516f, 0.125685945153236f, -0.331495076417923f, + 0.125431805849075f, -0.331207901239395f, 0.125177875161171f, -0.330920487642288f, + 0.124924175441265f, -0.330632925033569f, 0.124670691788197f, -0.330345153808594f, + 0.124417431652546f, -0.330057173967361f, 0.124164395034313f, -0.329769015312195f, + 0.123911574482918f, -0.329480648040771f, 0.123658977448940f, -0.329192101955414f, + 0.123406603932381f, -0.328903347253799f, 0.123154446482658f, -0.328614413738251f, + 0.122902512550354f, -0.328325271606445f, 0.122650802135468f, -0.328035950660706f, + 0.122399315237999f, -0.327746421098709f, 0.122148044407368f, -0.327456712722778f, + 0.121896997094154f, -0.327166795730591f, 0.121646173298359f, -0.326876699924469f, + 0.121395580470562f, -0.326586425304413f, 0.121145196259022f, -0.326295942068100f, + 0.120895043015480f, -0.326005280017853f, 0.120645113289356f, -0.325714409351349f, + 0.120395407080650f, -0.325423330068588f, 0.120145916938782f, -0.325132101774216f, + 0.119896657764912f, -0.324840664863586f, 0.119647622108459f, -0.324549019336700f, + 0.119398809969425f, -0.324257194995880f, 0.119150213897228f, -0.323965191841125f, + 0.118901848793030f, -0.323672980070114f, 0.118653707206249f, -0.323380589485168f, + 0.118405789136887f, -0.323088020086288f, 0.118158094584942f, -0.322795242071152f, + 0.117910631000996f, -0.322502255439758f, 0.117663383483887f, -0.322209119796753f, + 0.117416366934776f, -0.321915775537491f, 0.117169573903084f, -0.321622252464294f, + 0.116923004388809f, -0.321328520774841f, 0.116676658391953f, -0.321034610271454f, + 0.116430543363094f, -0.320740520954132f, 0.116184651851654f, -0.320446223020554f, + 0.115938983857632f, -0.320151746273041f, 0.115693546831608f, -0.319857090711594f, + 0.115448333323002f, -0.319562226533890f, 0.115203343331814f, -0.319267183542252f, + 0.114958584308624f, -0.318971961736679f, 0.114714048802853f, -0.318676531314850f, + 0.114469736814499f, -0.318380922079086f, 0.114225655794144f, -0.318085134029388f, + 0.113981798291206f, -0.317789167165756f, 0.113738171756268f, -0.317492991685867f, + 0.113494776189327f, -0.317196637392044f, 0.113251596689224f, -0.316900104284287f, + 0.113008655607700f, -0.316603392362595f, 0.112765938043594f, -0.316306471824646f, + 0.112523443996906f, -0.316009372472763f, 0.112281180918217f, -0.315712094306946f, + 0.112039148807526f, -0.315414607524872f, 0.111797347664833f, -0.315116971731186f, + 0.111555770039558f, -0.314819127321243f, 0.111314415931702f, -0.314521104097366f, + 0.111073300242424f, -0.314222872257233f, 0.110832408070564f, -0.313924491405487f, + 0.110591746866703f, -0.313625901937485f, 0.110351309180260f, -0.313327133655548f, + 0.110111102461815f, -0.313028186559677f, 0.109871134161949f, -0.312729060649872f, + 0.109631389379501f, -0.312429755926132f, 0.109391868114471f, -0.312130242586136f, + 0.109152585268021f, -0.311830550432205f, 0.108913525938988f, -0.311530679464340f, + 0.108674705028534f, -0.311230629682541f, 0.108436107635498f, -0.310930401086807f, + 0.108197741210461f, -0.310629993677139f, 0.107959605753422f, -0.310329377651215f, + 0.107721701264381f, -0.310028612613678f, 0.107484027743340f, -0.309727638959885f, + 0.107246585190296f, -0.309426486492157f, 0.107009373605251f, -0.309125155210495f, + 0.106772392988205f, -0.308823645114899f, 0.106535643339157f, -0.308521956205368f, + 0.106299124658108f, -0.308220088481903f, 0.106062836945057f, -0.307918041944504f, + 0.105826787650585f, -0.307615786790848f, 0.105590961873531f, -0.307313382625580f, + 0.105355374515057f, -0.307010769844055f, 0.105120018124580f, -0.306708008050919f, + 0.104884892702103f, -0.306405037641525f, 0.104649998247623f, -0.306101888418198f, + 0.104415334761143f, -0.305798590183258f, 0.104180909693241f, -0.305495083332062f, + 0.103946708142757f, -0.305191397666931f, 0.103712752461433f, -0.304887533187866f, + 0.103479020297527f, -0.304583519697189f, 0.103245526552200f, -0.304279297590256f, + 0.103012263774872f, -0.303974896669388f, 0.102779231965542f, -0.303670316934586f, + 0.102546438574791f, -0.303365558385849f, 0.102313876152039f, -0.303060621023178f, + 0.102081544697285f, -0.302755534648895f, 0.101849451661110f, -0.302450239658356f, + 0.101617597043514f, -0.302144765853882f, 0.101385973393917f, -0.301839113235474f, + 0.101154580712318f, -0.301533311605453f, 0.100923426449299f, -0.301227301359177f, + 0.100692503154278f, -0.300921112298965f, 0.100461818277836f, -0.300614774227142f, + 0.100231364369392f, -0.300308227539063f, 0.100001148879528f, -0.300001531839371f, + 0.099771171808243f, -0.299694657325745f, 0.099541425704956f, -0.299387603998184f, + 0.099311910569668f, -0.299080342054367f, 0.099082641303539f, -0.298772931098938f, + 0.098853603005409f, -0.298465341329575f, 0.098624803125858f, -0.298157602548599f, + 0.098396234214306f, -0.297849655151367f, 0.098167903721333f, -0.297541528940201f, + 0.097939811646938f, -0.297233253717422f, 0.097711957991123f, -0.296924799680710f, + 0.097484335303307f, -0.296616137027740f, 0.097256951034069f, -0.296307325363159f, + 0.097029805183411f, -0.295998334884644f, 0.096802897751331f, -0.295689195394516f, + 0.096576221287251f, -0.295379847288132f, 0.096349790692329f, -0.295070350170136f, + 0.096123591065407f, -0.294760644435883f, 0.095897629857063f, -0.294450789690018f, + 0.095671907067299f, -0.294140785932541f, 0.095446422696114f, -0.293830573558807f, + 0.095221176743507f, -0.293520182371140f, 0.094996169209480f, -0.293209642171860f, + 0.094771400094032f, -0.292898923158646f, 0.094546869397163f, -0.292588025331497f, + 0.094322577118874f, -0.292276978492737f, 0.094098523259163f, -0.291965723037720f, + 0.093874707818031f, -0.291654318571091f, 0.093651130795479f, -0.291342735290527f, + 0.093427792191505f, -0.291031002998352f, 0.093204692006111f, -0.290719062089920f, + 0.092981837689877f, -0.290406972169876f, 0.092759214341640f, -0.290094703435898f, + 0.092536836862564f, -0.289782285690308f, 0.092314697802067f, -0.289469659328461f, + 0.092092797160149f, -0.289156883955002f, 0.091871134936810f, -0.288843959569931f, + 0.091649711132050f, -0.288530826568604f, 0.091428533196449f, -0.288217544555664f, + 0.091207593679428f, -0.287904083728790f, 0.090986892580986f, -0.287590473890305f, + 0.090766437351704f, -0.287276685237885f, 0.090546220541000f, -0.286962717771530f, + 0.090326242148876f, -0.286648571491241f, 0.090106502175331f, -0.286334276199341f, + 0.089887008070946f, -0.286019802093506f, 0.089667752385139f, -0.285705178976059f, + 0.089448742568493f, -0.285390377044678f, 0.089229971170425f, -0.285075396299362f, + 0.089011445641518f, -0.284760266542435f, 0.088793158531189f, -0.284444957971573f, + 0.088575109839439f, -0.284129470586777f, 0.088357307016850f, -0.283813834190369f, + 0.088139742612839f, -0.283498018980026f, 0.087922424077988f, -0.283182054758072f, + 0.087705351412296f, -0.282865911722183f, 0.087488517165184f, -0.282549589872360f, + 0.087271921336651f, -0.282233119010925f, 0.087055571377277f, -0.281916469335556f, + 0.086839467287064f, -0.281599670648575f, 0.086623609066010f, -0.281282693147659f, + 0.086407989263535f, -0.280965566635132f, 0.086192607879639f, -0.280648261308670f, + 0.085977479815483f, -0.280330777168274f, 0.085762590169907f, -0.280013144016266f, + 0.085547938942909f, -0.279695361852646f, 0.085333541035652f, -0.279377400875092f, + 0.085119381546974f, -0.279059261083603f, 0.084905467927456f, -0.278740972280502f, + 0.084691800177097f, -0.278422504663467f, 0.084478378295898f, -0.278103888034821f, + 0.084265194833279f, -0.277785122394562f, 0.084052257239819f, -0.277466177940369f, + 0.083839565515518f, -0.277147054672241f, 0.083627119660378f, -0.276827782392502f, + 0.083414919674397f, -0.276508361101151f, 0.083202958106995f, -0.276188760995865f, + 0.082991249859333f, -0.275868982076645f, 0.082779780030251f, -0.275549083948135f, + 0.082568563520908f, -0.275228977203369f, 0.082357585430145f, -0.274908751249313f, + 0.082146860659122f, -0.274588316679001f, 0.081936374306679f, -0.274267762899399f, + 0.081726133823395f, -0.273947030305862f, 0.081516146659851f, -0.273626148700714f, + 0.081306397914886f, -0.273305088281631f, 0.081096902489662f, -0.272983878850937f, + 0.080887645483017f, -0.272662490606308f, 0.080678641796112f, -0.272340953350067f, + 0.080469883978367f, -0.272019267082214f, 0.080261372029781f, -0.271697402000427f, + 0.080053105950356f, -0.271375387907028f, 0.079845085740089f, -0.271053224802017f, + 0.079637311398983f, -0.270730882883072f, 0.079429790377617f, -0.270408391952515f, + 0.079222507774830f, -0.270085722208023f, 0.079015478491783f, -0.269762933254242f, + 0.078808702528477f, -0.269439965486526f, 0.078602164983749f, -0.269116818904877f, + 0.078395880758762f, -0.268793523311615f, 0.078189842402935f, -0.268470078706741f, + 0.077984049916267f, -0.268146485090256f, 0.077778510749340f, -0.267822742462158f, + 0.077573217451572f, -0.267498821020126f, 0.077368170022964f, -0.267174720764160f, + 0.077163375914097f, -0.266850501298904f, 0.076958827674389f, -0.266526103019714f, + 0.076754532754421f, -0.266201555728912f, 0.076550483703613f, -0.265876859426498f, + 0.076346680521965f, -0.265552014112473f, 0.076143130660057f, -0.265226989984512f, + 0.075939826667309f, -0.264901816844940f, 0.075736775994301f, -0.264576494693756f, + 0.075533971190453f, -0.264250993728638f, 0.075331419706345f, -0.263925373554230f, + 0.075129114091396f, -0.263599574565887f, 0.074927061796188f, -0.263273626565933f, + 0.074725262820721f, -0.262947499752045f, 0.074523709714413f, -0.262621253728867f, + 0.074322402477264f, -0.262294828891754f, 0.074121348559856f, -0.261968284845352f, + 0.073920547962189f, -0.261641561985016f, 0.073720000684261f, -0.261314690113068f, + 0.073519699275494f, -0.260987639427185f, 0.073319651186466f, -0.260660469532013f, + 0.073119848966599f, -0.260333120822906f, 0.072920300066471f, -0.260005623102188f, + 0.072721004486084f, -0.259678006172180f, 0.072521962225437f, -0.259350210428238f, + 0.072323165833950f, -0.259022265672684f, 0.072124622762203f, -0.258694142103195f, + 0.071926333010197f, -0.258365899324417f, 0.071728296577930f, -0.258037507534027f, + 0.071530513465405f, -0.257708936929703f, 0.071332976222038f, -0.257380217313766f, + 0.071135692298412f, -0.257051378488541f, 0.070938661694527f, -0.256722360849380f, + 0.070741884410381f, -0.256393194198608f, 0.070545360445976f, -0.256063878536224f, + 0.070349089801311f, -0.255734413862228f, 0.070153072476387f, -0.255404800176620f, + 0.069957308471203f, -0.255075037479401f, 0.069761790335178f, -0.254745125770569f, + 0.069566532969475f, -0.254415065050125f, 0.069371521472931f, -0.254084855318069f, + 0.069176770746708f, -0.253754496574402f, 0.068982265889645f, -0.253423988819122f, + 0.068788021802902f, -0.253093332052231f, 0.068594031035900f, -0.252762526273727f, + 0.068400286138058f, -0.252431541681290f, 0.068206802010536f, -0.252100437879562f, + 0.068013571202755f, -0.251769185066223f, 0.067820593714714f, -0.251437783241272f, + 0.067627869546413f, -0.251106232404709f, 0.067435398697853f, -0.250774532556534f, + 0.067243188619614f, -0.250442683696747f, 0.067051224410534f, -0.250110685825348f, + 0.066859520971775f, -0.249778553843498f, 0.066668070852757f, -0.249446272850037f, + 0.066476874053478f, -0.249113827943802f, 0.066285938024521f, -0.248781248927116f, + 0.066095255315304f, -0.248448520898819f, 0.065904818475246f, -0.248115643858910f, + 0.065714649856091f, -0.247782632708550f, 0.065524727106094f, -0.247449472546577f, + 0.065335065126419f, -0.247116148471832f, 0.065145656466484f, -0.246782705187798f, + 0.064956501126289f, -0.246449097990990f, 0.064767606556416f, -0.246115356683731f, + 0.064578965306282f, -0.245781451463699f, 0.064390584826469f, -0.245447427034378f, + 0.064202457666397f, -0.245113238692284f, 0.064014583826065f, -0.244778916239738f, + 0.063826970756054f, -0.244444444775581f, 0.063639611005783f, -0.244109839200974f, + 0.063452512025833f, -0.243775084614754f, 0.063265666365623f, -0.243440181016922f, + 0.063079081475735f, -0.243105143308640f, 0.062892749905586f, -0.242769956588745f, + 0.062706671655178f, -0.242434620857239f, 0.062520854175091f, -0.242099151015282f, + 0.062335297465324f, -0.241763532161713f, 0.062149997800589f, -0.241427779197693f, + 0.061964951455593f, -0.241091892123222f, 0.061780165880919f, -0.240755841135979f, + 0.061595637351274f, -0.240419670939446f, 0.061411365866661f, -0.240083336830139f, + 0.061227355152369f, -0.239746883511543f, 0.061043601483107f, -0.239410281181335f, + 0.060860104858875f, -0.239073529839516f, 0.060676865279675f, -0.238736644387245f, + 0.060493886470795f, -0.238399609923363f, 0.060311164706945f, -0.238062441349030f, + 0.060128703713417f, -0.237725138664246f, 0.059946499764919f, -0.237387686967850f, + 0.059764556586742f, -0.237050101161003f, 0.059582870453596f, -0.236712381243706f, + 0.059401445090771f, -0.236374512314796f, 0.059220276772976f, -0.236036509275436f, + 0.059039369225502f, -0.235698372125626f, 0.058858718723059f, -0.235360085964203f, + 0.058678328990936f, -0.235021665692329f, 0.058498200029135f, -0.234683111310005f, + 0.058318331837654f, -0.234344407916069f, 0.058138720691204f, -0.234005570411682f, + 0.057959370315075f, -0.233666598796844f, 0.057780280709267f, -0.233327493071556f, + 0.057601451873779f, -0.232988253235817f, 0.057422880083323f, -0.232648864388466f, + 0.057244572788477f, -0.232309341430664f, 0.057066522538662f, -0.231969684362412f, + 0.056888736784458f, -0.231629893183708f, 0.056711208075285f, -0.231289967894554f, + 0.056533940136433f, -0.230949893593788f, 0.056356932967901f, -0.230609700083733f, + 0.056180190294981f, -0.230269357562065f, 0.056003704667091f, -0.229928880929947f, + 0.055827483534813f, -0.229588270187378f, 0.055651523172855f, -0.229247525334358f, + 0.055475823581219f, -0.228906646370888f, 0.055300384759903f, -0.228565633296967f, + 0.055125206708908f, -0.228224486112595f, 0.054950293153524f, -0.227883204817772f, + 0.054775636643171f, -0.227541789412498f, 0.054601248353720f, -0.227200239896774f, + 0.054427117109299f, -0.226858556270599f, 0.054253250360489f, -0.226516738533974f, + 0.054079644382000f, -0.226174786686897f, 0.053906302899122f, -0.225832715630531f, + 0.053733222186565f, -0.225490495562553f, 0.053560405969620f, -0.225148141384125f, + 0.053387850522995f, -0.224805667996407f, 0.053215555846691f, -0.224463045597076f, + 0.053043525665998f, -0.224120303988457f, 0.052871759980917f, -0.223777428269386f, + 0.052700258791447f, -0.223434418439865f, 0.052529018372297f, -0.223091274499893f, + 0.052358038723469f, -0.222748011350632f, 0.052187327295542f, -0.222404599189758f, + 0.052016876637936f, -0.222061067819595f, 0.051846686750650f, -0.221717402338982f, + 0.051676765084267f, -0.221373617649078f, 0.051507104188204f, -0.221029683947563f, + 0.051337707787752f, -0.220685631036758f, 0.051168579608202f, -0.220341444015503f, + 0.050999708473682f, -0.219997137784958f, 0.050831105560064f, -0.219652697443962f, + 0.050662767142057f, -0.219308122992516f, 0.050494693219662f, -0.218963414430618f, + 0.050326880067587f, -0.218618586659431f, 0.050159335136414f, -0.218273624777794f, + 0.049992054700851f, -0.217928543686867f, 0.049825038760900f, -0.217583328485489f, + 0.049658283591270f, -0.217237979173660f, 0.049491796642542f, -0.216892510652542f, + 0.049325577914715f, -0.216546908020973f, 0.049159619957209f, -0.216201186180115f, + 0.048993926495314f, -0.215855330228806f, 0.048828501254320f, -0.215509355068207f, + 0.048663340508938f, -0.215163245797157f, 0.048498444259167f, -0.214817002415657f, + 0.048333816230297f, -0.214470639824867f, 0.048169452697039f, -0.214124158024788f, + 0.048005353659391f, -0.213777542114258f, 0.047841522842646f, -0.213430806994438f, + 0.047677956521511f, -0.213083937764168f, 0.047514654695988f, -0.212736949324608f, + 0.047351621091366f, -0.212389841675758f, 0.047188851982355f, -0.212042599916458f, + 0.047026351094246f, -0.211695238947868f, 0.046864114701748f, -0.211347743868828f, + 0.046702146530151f, -0.211000129580498f, 0.046540446579456f, -0.210652396082878f, + 0.046379011124372f, -0.210304543375969f, 0.046217843890190f, -0.209956556558609f, + 0.046056941151619f, -0.209608450531960f, 0.045896306633949f, -0.209260210394859f, + 0.045735940337181f, -0.208911851048470f, 0.045575842261314f, -0.208563387393951f, + 0.045416008681059f, -0.208214774727821f, 0.045256443321705f, -0.207866057753563f, + 0.045097146183252f, -0.207517206668854f, 0.044938117265701f, -0.207168251276016f, + 0.044779352843761f, -0.206819161772728f, 0.044620860368013f, -0.206469938158989f, + 0.044462632387877f, -0.206120610237122f, 0.044304672628641f, -0.205771163105965f, + 0.044146984815598f, -0.205421581864357f, 0.043989561498165f, -0.205071896314621f, + 0.043832406401634f, -0.204722076654434f, 0.043675523251295f, -0.204372137784958f, + 0.043518904596567f, -0.204022079706192f, 0.043362557888031f, -0.203671902418137f, + 0.043206475675106f, -0.203321605920792f, 0.043050665408373f, -0.202971190214157f, + 0.042895123362541f, -0.202620655298233f, 0.042739849537611f, -0.202270001173019f, + 0.042584843933582f, -0.201919227838516f, 0.042430106550455f, -0.201568335294724f, + 0.042275641113520f, -0.201217323541641f, 0.042121443897486f, -0.200866192579269f, + 0.041967518627644f, -0.200514942407608f, 0.041813857853413f, -0.200163587927818f, + 0.041660469025373f, -0.199812099337578f, 0.041507352143526f, -0.199460506439209f, + 0.041354499757290f, -0.199108779430389f, 0.041201923042536f, -0.198756948113441f, + 0.041049610823393f, -0.198404997587204f, 0.040897574275732f, -0.198052927851677f, + 0.040745802223682f, -0.197700738906860f, 0.040594302117825f, -0.197348430752754f, + 0.040443073958158f, -0.196996018290520f, 0.040292114019394f, -0.196643486618996f, + 0.040141426026821f, -0.196290835738182f, 0.039991009980440f, -0.195938065648079f, + 0.039840862154961f, -0.195585191249847f, 0.039690986275673f, -0.195232197642326f, + 0.039541378617287f, -0.194879084825516f, 0.039392042905092f, -0.194525867700577f, + 0.039242979139090f, -0.194172516465187f, 0.039094187319279f, -0.193819075822830f, + 0.038945667445660f, -0.193465501070023f, 0.038797415792942f, -0.193111822009087f, + 0.038649436086416f, -0.192758023738861f, 0.038501728326082f, -0.192404121160507f, + 0.038354292511940f, -0.192050099372864f, 0.038207128643990f, -0.191695958375931f, + 0.038060232996941f, -0.191341713070869f, 0.037913613021374f, -0.190987363457680f, + 0.037767261266708f, -0.190632879734039f, 0.037621185183525f, -0.190278306603432f, + 0.037475381046534f, -0.189923599362373f, 0.037329845130444f, -0.189568802714348f, + 0.037184584885836f, -0.189213871955872f, 0.037039596587420f, -0.188858851790428f, + 0.036894880235195f, -0.188503712415695f, 0.036750435829163f, -0.188148453831673f, + 0.036606263369322f, -0.187793090939522f, 0.036462362855673f, -0.187437608838081f, + 0.036318738013506f, -0.187082037329674f, 0.036175385117531f, -0.186726331710815f, + 0.036032304167747f, -0.186370536684990f, 0.035889495164156f, -0.186014622449875f, + 0.035746958106756f, -0.185658603906631f, 0.035604696720839f, -0.185302466154099f, + 0.035462711006403f, -0.184946224093437f, 0.035320993512869f, -0.184589877724648f, + 0.035179551690817f, -0.184233412146568f, 0.035038381814957f, -0.183876842260361f, + 0.034897487610579f, -0.183520168066025f, 0.034756865352392f, -0.183163389563560f, + 0.034616518765688f, -0.182806491851807f, 0.034476444125175f, -0.182449504733086f, + 0.034336645156145f, -0.182092398405075f, 0.034197118133307f, -0.181735187768936f, + 0.034057866781950f, -0.181377857923508f, 0.033918887376785f, -0.181020438671112f, + 0.033780183643103f, -0.180662900209427f, 0.033641755580902f, -0.180305257439613f, + 0.033503599464893f, -0.179947525262833f, 0.033365719020367f, -0.179589673876762f, + 0.033228114247322f, -0.179231703281403f, 0.033090781420469f, -0.178873643279076f, + 0.032953724265099f, -0.178515478968620f, 0.032816942781210f, -0.178157210350037f, + 0.032680433243513f, -0.177798837423325f, 0.032544203102589f, -0.177440345287323f, + 0.032408244907856f, -0.177081763744354f, 0.032272562384605f, -0.176723077893257f, + 0.032137155532837f, -0.176364272832870f, 0.032002024352551f, -0.176005378365517f, + 0.031867165118456f, -0.175646379590034f, 0.031732585281134f, -0.175287276506424f, + 0.031598277390003f, -0.174928069114685f, 0.031464248895645f, -0.174568757414818f, + 0.031330492347479f, -0.174209341406822f, 0.031197015196085f, -0.173849821090698f, + 0.031063811853528f, -0.173490211367607f, 0.030930884182453f, -0.173130482435226f, + 0.030798232182860f, -0.172770664095879f, 0.030665857717395f, -0.172410741448402f, + 0.030533758923411f, -0.172050714492798f, 0.030401935800910f, -0.171690583229065f, + 0.030270388349891f, -0.171330362558365f, 0.030139118432999f, -0.170970037579536f, + 0.030008124187589f, -0.170609608292580f, 0.029877405613661f, -0.170249074697495f, + 0.029746964573860f, -0.169888436794281f, 0.029616801068187f, -0.169527709484100f, + 0.029486913233995f, -0.169166877865791f, 0.029357301071286f, -0.168805956840515f, + 0.029227968305349f, -0.168444931507111f, 0.029098909348249f, -0.168083801865578f, + 0.028970129787922f, -0.167722567915916f, 0.028841627761722f, -0.167361244559288f, + 0.028713401407003f, -0.166999831795692f, 0.028585452586412f, -0.166638299822807f, + 0.028457781299949f, -0.166276678442955f, 0.028330387547612f, -0.165914967656136f, + 0.028203271329403f, -0.165553152561188f, 0.028076432645321f, -0.165191248059273f, + 0.027949871495366f, -0.164829224348068f, 0.027823587879539f, -0.164467126131058f, + 0.027697581797838f, -0.164104923605919f, 0.027571853250265f, -0.163742616772652f, + 0.027446404099464f, -0.163380220532417f, 0.027321230620146f, -0.163017734885216f, + 0.027196336537600f, -0.162655144929886f, 0.027071721851826f, -0.162292465567589f, + 0.026947384700179f, -0.161929681897163f, 0.026823325082660f, -0.161566808819771f, + 0.026699542999268f, -0.161203846335411f, 0.026576040312648f, -0.160840779542923f, + 0.026452817022800f, -0.160477623343468f, 0.026329871267080f, -0.160114362835884f, + 0.026207204908133f, -0.159751012921333f, 0.026084816083312f, -0.159387573599815f, + 0.025962706655264f, -0.159024044871330f, 0.025840876623988f, -0.158660411834717f, + 0.025719324126840f, -0.158296689391136f, 0.025598052889109f, -0.157932877540588f, + 0.025477059185505f, -0.157568961381912f, 0.025356344878674f, -0.157204970717430f, + 0.025235909968615f, -0.156840875744820f, 0.025115754455328f, -0.156476691365242f, + 0.024995878338814f, -0.156112402677536f, 0.024876279756427f, -0.155748039484024f, + 0.024756962433457f, -0.155383571982384f, 0.024637924507260f, -0.155019029974937f, + 0.024519165977836f, -0.154654383659363f, 0.024400688707829f, -0.154289647936821f, + 0.024282488971949f, -0.153924822807312f, 0.024164570495486f, -0.153559908270836f, + 0.024046931415796f, -0.153194904327393f, 0.023929571732879f, -0.152829796075821f, + 0.023812493309379f, -0.152464613318443f, 0.023695694282651f, -0.152099341154099f, + 0.023579176515341f, -0.151733979582787f, 0.023462938144803f, -0.151368513703346f, + 0.023346979171038f, -0.151002973318100f, 0.023231301456690f, -0.150637343525887f, + 0.023115905001760f, -0.150271624326706f, 0.023000787943602f, -0.149905815720558f, + 0.022885952144861f, -0.149539917707443f, 0.022771397605538f, -0.149173930287361f, + 0.022657122462988f, -0.148807853460312f, 0.022543128579855f, -0.148441687226295f, + 0.022429415956140f, -0.148075446486473f, 0.022315984591842f, -0.147709101438522f, + 0.022202832624316f, -0.147342681884766f, 0.022089963778853f, -0.146976172924042f, + 0.021977374330163f, -0.146609574556351f, 0.021865066140890f, -0.146242901682854f, + 0.021753041073680f, -0.145876124501228f, 0.021641295403242f, -0.145509272813797f, + 0.021529832854867f, -0.145142331719399f, 0.021418649703264f, -0.144775316119194f, + 0.021307749673724f, -0.144408211112022f, 0.021197130903602f, -0.144041016697884f, + 0.021086793392897f, -0.143673732876778f, 0.020976737141609f, -0.143306359648705f, + 0.020866964012384f, -0.142938911914825f, 0.020757472142577f, -0.142571389675140f, + 0.020648263394833f, -0.142203763127327f, 0.020539334043860f, -0.141836062073708f, + 0.020430689677596f, -0.141468286514282f, 0.020322324708104f, -0.141100421547890f, + 0.020214242860675f, -0.140732467174530f, 0.020106444135308f, -0.140364438295364f, + 0.019998926669359f, -0.139996320009232f, 0.019891692325473f, -0.139628127217293f, + 0.019784741103649f, -0.139259845018387f, 0.019678071141243f, -0.138891488313675f, + 0.019571684300900f, -0.138523042201996f, 0.019465578719974f, -0.138154521584511f, + 0.019359756261110f, -0.137785911560059f, 0.019254218786955f, -0.137417227029800f, + 0.019148962572217f, -0.137048453092575f, 0.019043987616897f, -0.136679604649544f, + 0.018939297646284f, -0.136310681700706f, 0.018834890797734f, -0.135941669344902f, + 0.018730765208602f, -0.135572582483292f, 0.018626924604177f, -0.135203406214714f, + 0.018523367121816f, -0.134834155440331f, 0.018420090898871f, -0.134464830160141f, + 0.018317099660635f, -0.134095430374146f, 0.018214391544461f, -0.133725941181183f, + 0.018111966550350f, -0.133356377482414f, 0.018009826540947f, -0.132986739277840f, + 0.017907967790961f, -0.132617011666298f, 0.017806394025683f, -0.132247209548950f, + 0.017705103382468f, -0.131877332925797f, 0.017604095861316f, -0.131507381796837f, + 0.017503373324871f, -0.131137356162071f, 0.017402933910489f, -0.130767241120338f, + 0.017302779480815f, -0.130397051572800f, 0.017202908173203f, -0.130026802420616f, + 0.017103319987655f, -0.129656463861465f, 0.017004016786814f, -0.129286035895348f, + 0.016904998570681f, -0.128915548324585f, 0.016806263476610f, -0.128544986248016f, + 0.016707813367248f, -0.128174334764481f, 0.016609646379948f, -0.127803623676300f, + 0.016511764377356f, -0.127432823181152f, 0.016414167359471f, -0.127061963081360f, + 0.016316853463650f, -0.126691013574600f, 0.016219824552536f, -0.126320004463196f, + 0.016123080626130f, -0.125948905944824f, 0.016026621684432f, -0.125577747821808f, + 0.015930447727442f, -0.125206500291824f, 0.015834558755159f, -0.124835193157196f, + 0.015738952904940f, -0.124463804066181f, 0.015643632039428f, -0.124092340469360f, + 0.015548598021269f, -0.123720809817314f, 0.015453847125173f, -0.123349204659462f, + 0.015359382145107f, -0.122977524995804f, 0.015265202149749f, -0.122605770826340f, + 0.015171307139099f, -0.122233949601650f, 0.015077698044479f, -0.121862053871155f, + 0.014984373003244f, -0.121490091085434f, 0.014891333878040f, -0.121118053793907f, + 0.014798580668867f, -0.120745941996574f, 0.014706112444401f, -0.120373763144016f, + 0.014613929204643f, -0.120001509785652f, 0.014522032812238f, -0.119629189372063f, + 0.014430420473218f, -0.119256794452667f, 0.014339094981551f, -0.118884332478046f, + 0.014248054474592f, -0.118511803448200f, 0.014157299883664f, -0.118139199912548f, + 0.014066831208766f, -0.117766529321671f, 0.013976648449898f, -0.117393791675568f, + 0.013886751607060f, -0.117020979523659f, 0.013797140680254f, -0.116648100316525f, + 0.013707815669477f, -0.116275154054165f, 0.013618776574731f, -0.115902140736580f, + 0.013530024327338f, -0.115529052913189f, 0.013441557064652f, -0.115155905485153f, + 0.013353376649320f, -0.114782683551311f, 0.013265483081341f, -0.114409394562244f, + 0.013177875429392f, -0.114036038517952f, 0.013090553693473f, -0.113662622869015f, + 0.013003518804908f, -0.113289132714272f, 0.012916770763695f, -0.112915575504303f, + 0.012830308638513f, -0.112541958689690f, 0.012744133360684f, -0.112168267369270f, + 0.012658244930208f, -0.111794516444206f, 0.012572642415762f, -0.111420698463917f, + 0.012487327679992f, -0.111046813428402f, 0.012402298860252f, -0.110672861337662f, + 0.012317557819188f, -0.110298842191696f, 0.012233102694154f, -0.109924763441086f, + 0.012148935347795f, -0.109550617635250f, 0.012065053917468f, -0.109176412224770f, + 0.011981460265815f, -0.108802139759064f, 0.011898153461516f, -0.108427800238132f, + 0.011815134435892f, -0.108053401112556f, 0.011732402257621f, -0.107678934931755f, + 0.011649956926703f, -0.107304409146309f, 0.011567799374461f, -0.106929816305637f, + 0.011485928669572f, -0.106555156409740f, 0.011404345743358f, -0.106180444359779f, + 0.011323049664497f, -0.105805665254593f, 0.011242041364312f, -0.105430819094181f, + 0.011161320842803f, -0.105055920779705f, 0.011080888099968f, -0.104680955410004f, + 0.011000742204487f, -0.104305922985077f, 0.010920885019004f, -0.103930838406086f, + 0.010841314680874f, -0.103555686771870f, 0.010762032121420f, -0.103180475533009f, + 0.010683037340641f, -0.102805204689503f, 0.010604331269860f, -0.102429874241352f, + 0.010525912046432f, -0.102054484188557f, 0.010447781533003f, -0.101679034531116f, + 0.010369938798249f, -0.101303517818451f, 0.010292383842170f, -0.100927948951721f, + 0.010215117596090f, -0.100552320480347f, 0.010138138197362f, -0.100176624953747f, + 0.010061448439956f, -0.099800877273083f, 0.009985045529902f, -0.099425069987774f, + 0.009908932261169f, -0.099049203097820f, 0.009833106771111f, -0.098673284053802f, + 0.009757569059730f, -0.098297297954559f, 0.009682320058346f, -0.097921259701252f, + 0.009607359766960f, -0.097545161843300f, 0.009532688185573f, -0.097169004380703f, + 0.009458304382861f, -0.096792794764042f, 0.009384209290147f, -0.096416525542736f, + 0.009310402907431f, -0.096040196716785f, 0.009236886166036f, -0.095663815736771f, + 0.009163657203317f, -0.095287375152111f, 0.009090716950595f, -0.094910882413387f, + 0.009018065407872f, -0.094534330070019f, 0.008945702575147f, -0.094157725572586f, + 0.008873629383743f, -0.093781061470509f, 0.008801844902337f, -0.093404345214367f, + 0.008730349130929f, -0.093027576804161f, 0.008659142069519f, -0.092650748789310f, + 0.008588224649429f, -0.092273868620396f, 0.008517595939338f, -0.091896936297417f, + 0.008447255939245f, -0.091519944369793f, 0.008377205580473f, -0.091142900288105f, + 0.008307444863021f, -0.090765804052353f, 0.008237972855568f, -0.090388655662537f, + 0.008168790489435f, -0.090011447668076f, 0.008099896833301f, -0.089634194970131f, + 0.008031292818487f, -0.089256882667542f, 0.007962978444993f, -0.088879525661469f, + 0.007894953712821f, -0.088502109050751f, 0.007827218621969f, -0.088124647736549f, + 0.007759772241116f, -0.087747126817703f, 0.007692615967244f, -0.087369553744793f, + 0.007625748869032f, -0.086991935968399f, 0.007559171877801f, -0.086614266037941f, + 0.007492884527892f, -0.086236543953419f, 0.007426886819303f, -0.085858769714832f, + 0.007361178752035f, -0.085480943322182f, 0.007295760791749f, -0.085103072226048f, + 0.007230632472783f, -0.084725148975849f, 0.007165793795139f, -0.084347173571587f, + 0.007101245224476f, -0.083969146013260f, 0.007036986760795f, -0.083591073751450f, + 0.006973018404096f, -0.083212949335575f, 0.006909339688718f, -0.082834780216217f, + 0.006845951545984f, -0.082456558942795f, 0.006782853044569f, -0.082078292965889f, + 0.006720044650137f, -0.081699974834919f, 0.006657526828349f, -0.081321612000465f, + 0.006595299113542f, -0.080943197011948f, 0.006533361505717f, -0.080564737319946f, + 0.006471714470536f, -0.080186225473881f, 0.006410357542336f, -0.079807676374912f, + 0.006349290721118f, -0.079429075121880f, 0.006288514938205f, -0.079050421714783f, + 0.006228029262275f, -0.078671731054783f, 0.006167833693326f, -0.078292988240719f, + 0.006107929162681f, -0.077914200723171f, 0.006048315204680f, -0.077535368502140f, + 0.005988991353661f, -0.077156484127045f, 0.005929958540946f, -0.076777562499046f, + 0.005871216300875f, -0.076398596167564f, 0.005812764633447f, -0.076019577682018f, + 0.005754603538662f, -0.075640521943569f, 0.005696733482182f, -0.075261414051056f, + 0.005639153998345f, -0.074882268905640f, 0.005581865552813f, -0.074503071606159f, + 0.005524867679924f, -0.074123837053776f, 0.005468160845339f, -0.073744557797909f, + 0.005411745049059f, -0.073365233838558f, 0.005355620291084f, -0.072985872626305f, + 0.005299786105752f, -0.072606459259987f, 0.005244242958724f, -0.072227008640766f, + 0.005188991315663f, -0.071847513318062f, 0.005134030245245f, -0.071467980742455f, + 0.005079360678792f, -0.071088403463364f, 0.005024982150644f, -0.070708781480789f, + 0.004970894660801f, -0.070329122245312f, 0.004917098674923f, -0.069949418306351f, + 0.004863593727350f, -0.069569669663906f, 0.004810380283743f, -0.069189883768559f, + 0.004757457878441f, -0.068810060620308f, 0.004704826977104f, -0.068430192768574f, + 0.004652487114072f, -0.068050287663937f, 0.004600439220667f, -0.067670337855816f, + 0.004548682365566f, -0.067290350794792f, 0.004497217014432f, -0.066910326480865f, + 0.004446043167263f, -0.066530264914036f, 0.004395160824060f, -0.066150158643723f, + 0.004344569984823f, -0.065770015120506f, 0.004294271115214f, -0.065389834344387f, + 0.004244263283908f, -0.065009608864784f, 0.004194547422230f, -0.064629353582859f, + 0.004145123064518f, -0.064249053597450f, 0.004095990676433f, -0.063868723809719f, + 0.004047149792314f, -0.063488349318504f, 0.003998600877821f, -0.063107937574387f, + 0.003950343467295f, -0.062727488577366f, 0.003902378026396f, -0.062347009778023f, + 0.003854704322293f, -0.061966486275196f, 0.003807322587818f, -0.061585929244757f, + 0.003760232590139f, -0.061205338686705f, 0.003713434794918f, -0.060824707150459f, + 0.003666928736493f, -0.060444042086601f, 0.003620714880526f, -0.060063343495131f, + 0.003574792761356f, -0.059682607650757f, 0.003529162844643f, -0.059301838278770f, + 0.003483824897557f, -0.058921031653881f, 0.003438779152930f, -0.058540191501379f, + 0.003394025377929f, -0.058159314095974f, 0.003349563805386f, -0.057778406888247f, + 0.003305394435301f, -0.057397462427616f, 0.003261517267674f, -0.057016488164663f, + 0.003217932302505f, -0.056635476648808f, 0.003174639539793f, -0.056254431605339f, + 0.003131638979539f, -0.055873356759548f, 0.003088930854574f, -0.055492244660854f, + 0.003046514932066f, -0.055111102759838f, 0.003004391444847f, -0.054729927331209f, + 0.002962560392916f, -0.054348722100258f, 0.002921021543443f, -0.053967483341694f, + 0.002879775362089f, -0.053586211055517f, 0.002838821383193f, -0.053204908967018f, + 0.002798160072416f, -0.052823577076197f, 0.002757790964097f, -0.052442211657763f, + 0.002717714523897f, -0.052060816437006f, 0.002677930751815f, -0.051679391413927f, + 0.002638439415023f, -0.051297932863235f, 0.002599240746349f, -0.050916448235512f, + 0.002560334512964f, -0.050534930080175f, 0.002521721180528f, -0.050153385847807f, + 0.002483400283381f, -0.049771808087826f, 0.002445372054353f, -0.049390204250813f, + 0.002407636726275f, -0.049008570611477f, 0.002370193833485f, -0.048626907169819f, + 0.002333043841645f, -0.048245213925838f, 0.002296186750755f, -0.047863494604826f, + 0.002259622327983f, -0.047481749206781f, 0.002223350573331f, -0.047099970281124f, + 0.002187371719629f, -0.046718169003725f, 0.002151685766876f, -0.046336337924004f, + 0.002116292715073f, -0.045954477041960f, 0.002081192564219f, -0.045572593808174f, + 0.002046385314316f, -0.045190680772066f, 0.002011870965362f, -0.044808741658926f, + 0.001977649517357f, -0.044426776468754f, 0.001943721086718f, -0.044044785201550f, + 0.001910085673444f, -0.043662767857313f, 0.001876743277535f, -0.043280724436045f, + 0.001843693898991f, -0.042898654937744f, 0.001810937537812f, -0.042516563087702f, + 0.001778474310413f, -0.042134445160627f, 0.001746304216795f, -0.041752301156521f, + 0.001714427140541f, -0.041370131075382f, 0.001682843198068f, -0.040987938642502f, + 0.001651552389376f, -0.040605723857880f, 0.001620554830879f, -0.040223482996225f, + 0.001589850406162f, -0.039841219782829f, 0.001559439115226f, -0.039458930492401f, + 0.001529321074486f, -0.039076622575521f, 0.001499496400356f, -0.038694288581610f, + 0.001469964860007f, -0.038311932235956f, 0.001440726569854f, -0.037929553538561f, + 0.001411781646311f, -0.037547148764133f, 0.001383129972965f, -0.037164725363255f, + 0.001354771666229f, -0.036782283335924f, 0.001326706726104f, -0.036399815231562f, + 0.001298935036175f, -0.036017324775457f, 0.001271456829272f, -0.035634815692902f, + 0.001244271872565f, -0.035252287983894f, 0.001217380515300f, -0.034869734197855f, + 0.001190782408230f, -0.034487165510654f, 0.001164477784187f, -0.034104570746422f, + 0.001138466643170f, -0.033721961081028f, 0.001112748985179f, -0.033339329063892f, + 0.001087324810214f, -0.032956674695015f, 0.001062194118276f, -0.032574005424976f, + 0.001037356909364f, -0.032191313803196f, 0.001012813183479f, -0.031808607280254f, + 0.000988563057035f, -0.031425878405571f, 0.000964606530033f, -0.031043132767081f, + 0.000940943544265f, -0.030660368502140f, 0.000917574157938f, -0.030277585610747f, + 0.000894498312846f, -0.029894785955548f, 0.000871716125403f, -0.029511967673898f, + 0.000849227537401f, -0.029129132628441f, 0.000827032607049f, -0.028746278956532f, + 0.000805131276138f, -0.028363410383463f, 0.000783523661084f, -0.027980525046587f, + 0.000762209703680f, -0.027597622945905f, 0.000741189462133f, -0.027214704081416f, + 0.000720462878235f, -0.026831768453121f, 0.000700030010194f, -0.026448817923665f, + 0.000679890916217f, -0.026065852493048f, 0.000660045538098f, -0.025682870298624f, + 0.000640493875835f, -0.025299875065684f, 0.000621235987637f, -0.024916863068938f, + 0.000602271873504f, -0.024533838033676f, 0.000583601591643f, -0.024150796234608f, + 0.000565225025639f, -0.023767741397023f, 0.000547142291907f, -0.023384673520923f, + 0.000529353390448f, -0.023001590743661f, 0.000511858321261f, -0.022618494927883f, + 0.000494657084346f, -0.022235386073589f, 0.000477749679703f, -0.021852264180779f, + 0.000461136136437f, -0.021469129249454f, 0.000444816454547f, -0.021085981279612f, + 0.000428790634032f, -0.020702820271254f, 0.000413058703998f, -0.020319648087025f, + 0.000397620693548f, -0.019936462864280f, 0.000382476573577f, -0.019553268328309f, + 0.000367626344087f, -0.019170060753822f, 0.000353070063284f, -0.018786842003465f, + 0.000338807702065f, -0.018403612077236f, 0.000324839289533f, -0.018020370975137f, + 0.000311164796585f, -0.017637118697166f, 0.000297784281429f, -0.017253857105970f, + 0.000284697714960f, -0.016870586201549f, 0.000271905126283f, -0.016487304121256f, + 0.000259406515397f, -0.016104012727737f, 0.000247201882303f, -0.015720712020993f, + 0.000235291256104f, -0.015337402001023f, 0.000223674607696f, -0.014954082667828f, + 0.000212351980736f, -0.014570754021406f, 0.000201323360670f, -0.014187417924404f, + 0.000190588747500f, -0.013804072514176f, 0.000180148170330f, -0.013420719653368f, + 0.000170001629158f, -0.013037359341979f, 0.000160149123985f, -0.012653990648687f, + 0.000150590654812f, -0.012270614504814f, 0.000141326236189f, -0.011887230910361f, + 0.000132355868118f, -0.011503840796649f, 0.000123679565149f, -0.011120444163680f, + 0.000115297327284f, -0.010737040080130f, 0.000107209154521f, -0.010353630408645f, + 0.000099415054137f, -0.009970214217901f, 0.000091915040684f, -0.009586792439222f, + 0.000084709099610f, -0.009203365072608f, 0.000077797252743f, -0.008819932118058f, + 0.000071179500083f, -0.008436493575573f, 0.000064855834353f, -0.008053051307797f, + 0.000058826273744f, -0.007669602986425f, 0.000053090810979f, -0.007286150939763f, + 0.000047649456974f, -0.006902694236487f, 0.000042502211727f, -0.006519233807921f, + 0.000037649078877f, -0.006135769188404f, 0.000033090062061f, -0.005752300843596f, + 0.000028825161280f, -0.005368829704821f, 0.000024854381991f, -0.004985354840755f, + 0.000021177724193f, -0.004601877182722f, 0.000017795191525f, -0.004218397196382f, + 0.000014706784896f, -0.003834914416075f, 0.000011912506125f, -0.003451429307461f, + 0.000009412358850f, -0.003067942336202f, 0.000007206342616f, -0.002684453502297f, + 0.000005294459243f, -0.002300963038579f, 0.000003676709639f, -0.001917471294291f, + 0.000002353095169f, -0.001533978385851f, 0.000001323616516f, -0.001150484546088f, + 0.000000588274133f, -0.000766990066040f, 0.000000147068562f, -0.000383495149435f, + 0.000000000000000f, -0.000000000000023f, 0.000000147068562f, 0.000383495149435f, + 0.000000588274133f, 0.000766990066040f, 0.000001323616516f, 0.001150484546088f, + 0.000002353095169f, 0.001533978385851f, 0.000003676709639f, 0.001917471294291f, + 0.000005294459243f, 0.002300963038579f, 0.000007206342616f, 0.002684453502297f, + 0.000009412358850f, 0.003067942336202f, 0.000011912506125f, 0.003451429307461f, + 0.000014706784896f, 0.003834914416075f, 0.000017795191525f, 0.004218397196382f, + 0.000021177724193f, 0.004601877182722f, 0.000024854381991f, 0.004985354840755f, + 0.000028825161280f, 0.005368829704821f, 0.000033090062061f, 0.005752300843596f, + 0.000037649078877f, 0.006135769188404f, 0.000042502211727f, 0.006519233807921f, + 0.000047649456974f, 0.006902694236487f, 0.000053090810979f, 0.007286150939763f, + 0.000058826273744f, 0.007669602986425f, 0.000064855834353f, 0.008053051307797f, + 0.000071179500083f, 0.008436493575573f, 0.000077797252743f, 0.008819932118058f, + 0.000084709099610f, 0.009203365072608f, 0.000091915040684f, 0.009586792439222f, + 0.000099415054137f, 0.009970214217901f, 0.000107209154521f, 0.010353630408645f, + 0.000115297327284f, 0.010737040080130f, 0.000123679565149f, 0.011120444163680f, + 0.000132355868118f, 0.011503840796649f, 0.000141326236189f, 0.011887230910361f, + 0.000150590654812f, 0.012270614504814f, 0.000160149123985f, 0.012653990648687f, + 0.000170001629158f, 0.013037359341979f, 0.000180148170330f, 0.013420719653368f, + 0.000190588747500f, 0.013804072514176f, 0.000201323360670f, 0.014187417924404f, + 0.000212351980736f, 0.014570754021406f, 0.000223674607696f, 0.014954082667828f, + 0.000235291256104f, 0.015337402001023f, 0.000247201882303f, 0.015720712020993f, + 0.000259406515397f, 0.016104012727737f, 0.000271905126283f, 0.016487304121256f, + 0.000284697714960f, 0.016870586201549f, 0.000297784281429f, 0.017253857105970f, + 0.000311164796585f, 0.017637118697166f, 0.000324839289533f, 0.018020370975137f, + 0.000338807702065f, 0.018403612077236f, 0.000353070063284f, 0.018786842003465f, + 0.000367626344087f, 0.019170060753822f, 0.000382476573577f, 0.019553268328309f, + 0.000397620693548f, 0.019936462864280f, 0.000413058703998f, 0.020319648087025f, + 0.000428790634032f, 0.020702820271254f, 0.000444816454547f, 0.021085981279612f, + 0.000461136136437f, 0.021469129249454f, 0.000477749679703f, 0.021852264180779f, + 0.000494657084346f, 0.022235386073589f, 0.000511858321261f, 0.022618494927883f, + 0.000529353390448f, 0.023001590743661f, 0.000547142291907f, 0.023384673520923f, + 0.000565225025639f, 0.023767741397023f, 0.000583601591643f, 0.024150796234608f, + 0.000602271873504f, 0.024533838033676f, 0.000621235987637f, 0.024916863068938f, + 0.000640493875835f, 0.025299875065684f, 0.000660045538098f, 0.025682870298624f, + 0.000679890916217f, 0.026065852493048f, 0.000700030010194f, 0.026448817923665f, + 0.000720462878235f, 0.026831768453121f, 0.000741189462133f, 0.027214704081416f, + 0.000762209703680f, 0.027597622945905f, 0.000783523661084f, 0.027980525046587f, + 0.000805131276138f, 0.028363410383463f, 0.000827032607049f, 0.028746278956532f, + 0.000849227537401f, 0.029129132628441f, 0.000871716125403f, 0.029511967673898f, + 0.000894498312846f, 0.029894785955548f, 0.000917574157938f, 0.030277585610747f, + 0.000940943544265f, 0.030660368502140f, 0.000964606530033f, 0.031043132767081f, + 0.000988563057035f, 0.031425878405571f, 0.001012813183479f, 0.031808607280254f, + 0.001037356909364f, 0.032191313803196f, 0.001062194118276f, 0.032574005424976f, + 0.001087324810214f, 0.032956674695015f, 0.001112748985179f, 0.033339329063892f, + 0.001138466643170f, 0.033721961081028f, 0.001164477784187f, 0.034104570746422f, + 0.001190782408230f, 0.034487165510654f, 0.001217380515300f, 0.034869734197855f, + 0.001244271872565f, 0.035252287983894f, 0.001271456829272f, 0.035634815692902f, + 0.001298935036175f, 0.036017324775457f, 0.001326706726104f, 0.036399815231562f, + 0.001354771666229f, 0.036782283335924f, 0.001383129972965f, 0.037164725363255f, + 0.001411781646311f, 0.037547148764133f, 0.001440726569854f, 0.037929553538561f, + 0.001469964860007f, 0.038311932235956f, 0.001499496400356f, 0.038694288581610f, + 0.001529321074486f, 0.039076622575521f, 0.001559439115226f, 0.039458930492401f, + 0.001589850406162f, 0.039841219782829f, 0.001620554830879f, 0.040223482996225f, + 0.001651552389376f, 0.040605723857880f, 0.001682843198068f, 0.040987938642502f, + 0.001714427140541f, 0.041370131075382f, 0.001746304216795f, 0.041752301156521f, + 0.001778474310413f, 0.042134445160627f, 0.001810937537812f, 0.042516563087702f, + 0.001843693898991f, 0.042898654937744f, 0.001876743277535f, 0.043280724436045f, + 0.001910085673444f, 0.043662767857313f, 0.001943721086718f, 0.044044785201550f, + 0.001977649517357f, 0.044426776468754f, 0.002011870965362f, 0.044808741658926f, + 0.002046385314316f, 0.045190680772066f, 0.002081192564219f, 0.045572593808174f, + 0.002116292715073f, 0.045954477041960f, 0.002151685766876f, 0.046336337924004f, + 0.002187371719629f, 0.046718169003725f, 0.002223350573331f, 0.047099970281124f, + 0.002259622327983f, 0.047481749206781f, 0.002296186750755f, 0.047863494604826f, + 0.002333043841645f, 0.048245213925838f, 0.002370193833485f, 0.048626907169819f, + 0.002407636726275f, 0.049008570611477f, 0.002445372054353f, 0.049390204250813f, + 0.002483400283381f, 0.049771808087826f, 0.002521721180528f, 0.050153385847807f, + 0.002560334512964f, 0.050534930080175f, 0.002599240746349f, 0.050916448235512f, + 0.002638439415023f, 0.051297932863235f, 0.002677930751815f, 0.051679391413927f, + 0.002717714523897f, 0.052060816437006f, 0.002757790964097f, 0.052442211657763f, + 0.002798160072416f, 0.052823577076197f, 0.002838821383193f, 0.053204908967018f, + 0.002879775362089f, 0.053586211055517f, 0.002921021543443f, 0.053967483341694f, + 0.002962560392916f, 0.054348722100258f, 0.003004391444847f, 0.054729927331209f, + 0.003046514932066f, 0.055111102759838f, 0.003088930854574f, 0.055492244660854f, + 0.003131638979539f, 0.055873356759548f, 0.003174639539793f, 0.056254431605339f, + 0.003217932302505f, 0.056635476648808f, 0.003261517267674f, 0.057016488164663f, + 0.003305394435301f, 0.057397462427616f, 0.003349563805386f, 0.057778406888247f, + 0.003394025377929f, 0.058159314095974f, 0.003438779152930f, 0.058540191501379f, + 0.003483824897557f, 0.058921031653881f, 0.003529162844643f, 0.059301838278770f, + 0.003574792761356f, 0.059682607650757f, 0.003620714880526f, 0.060063343495131f, + 0.003666928736493f, 0.060444042086601f, 0.003713434794918f, 0.060824707150459f, + 0.003760232590139f, 0.061205338686705f, 0.003807322587818f, 0.061585929244757f, + 0.003854704322293f, 0.061966486275196f, 0.003902378026396f, 0.062347009778023f, + 0.003950343467295f, 0.062727488577366f, 0.003998600877821f, 0.063107937574387f, + 0.004047149792314f, 0.063488349318504f, 0.004095990676433f, 0.063868723809719f, + 0.004145123064518f, 0.064249053597450f, 0.004194547422230f, 0.064629353582859f, + 0.004244263283908f, 0.065009608864784f, 0.004294271115214f, 0.065389834344387f, + 0.004344569984823f, 0.065770015120506f, 0.004395160824060f, 0.066150158643723f, + 0.004446043167263f, 0.066530264914036f, 0.004497217014432f, 0.066910326480865f, + 0.004548682365566f, 0.067290350794792f, 0.004600439220667f, 0.067670337855816f, + 0.004652487114072f, 0.068050287663937f, 0.004704826977104f, 0.068430192768574f, + 0.004757457878441f, 0.068810060620308f, 0.004810380283743f, 0.069189883768559f, + 0.004863593727350f, 0.069569669663906f, 0.004917098674923f, 0.069949418306351f, + 0.004970894660801f, 0.070329122245312f, 0.005024982150644f, 0.070708781480789f, + 0.005079360678792f, 0.071088403463364f, 0.005134030245245f, 0.071467980742455f, + 0.005188991315663f, 0.071847513318062f, 0.005244242958724f, 0.072227008640766f, + 0.005299786105752f, 0.072606459259987f, 0.005355620291084f, 0.072985872626305f, + 0.005411745049059f, 0.073365233838558f, 0.005468160845339f, 0.073744557797909f, + 0.005524867679924f, 0.074123837053776f, 0.005581865552813f, 0.074503071606159f, + 0.005639153998345f, 0.074882268905640f, 0.005696733482182f, 0.075261414051056f, + 0.005754603538662f, 0.075640521943569f, 0.005812764633447f, 0.076019577682018f, + 0.005871216300875f, 0.076398596167564f, 0.005929958540946f, 0.076777562499046f, + 0.005988991353661f, 0.077156484127045f, 0.006048315204680f, 0.077535368502140f, + 0.006107929162681f, 0.077914200723171f, 0.006167833693326f, 0.078292988240719f, + 0.006228029262275f, 0.078671731054783f, 0.006288514938205f, 0.079050421714783f, + 0.006349290721118f, 0.079429075121880f, 0.006410357542336f, 0.079807676374912f, + 0.006471714470536f, 0.080186225473881f, 0.006533361505717f, 0.080564737319946f, + 0.006595299113542f, 0.080943197011948f, 0.006657526828349f, 0.081321612000465f, + 0.006720044650137f, 0.081699974834919f, 0.006782853044569f, 0.082078292965889f, + 0.006845951545984f, 0.082456558942795f, 0.006909339688718f, 0.082834780216217f, + 0.006973018404096f, 0.083212949335575f, 0.007036986760795f, 0.083591073751450f, + 0.007101245224476f, 0.083969146013260f, 0.007165793795139f, 0.084347173571587f, + 0.007230632472783f, 0.084725148975849f, 0.007295760791749f, 0.085103072226048f, + 0.007361178752035f, 0.085480943322182f, 0.007426886819303f, 0.085858769714832f, + 0.007492884527892f, 0.086236543953419f, 0.007559171877801f, 0.086614266037941f, + 0.007625748869032f, 0.086991935968399f, 0.007692615967244f, 0.087369553744793f, + 0.007759772241116f, 0.087747126817703f, 0.007827218621969f, 0.088124647736549f, + 0.007894953712821f, 0.088502109050751f, 0.007962978444993f, 0.088879525661469f, + 0.008031292818487f, 0.089256882667542f, 0.008099896833301f, 0.089634194970131f, + 0.008168790489435f, 0.090011447668076f, 0.008237972855568f, 0.090388655662537f, + 0.008307444863021f, 0.090765804052353f, 0.008377205580473f, 0.091142900288105f, + 0.008447255939245f, 0.091519944369793f, 0.008517595939338f, 0.091896936297417f, + 0.008588224649429f, 0.092273868620396f, 0.008659142069519f, 0.092650748789310f, + 0.008730349130929f, 0.093027576804161f, 0.008801844902337f, 0.093404345214367f, + 0.008873629383743f, 0.093781061470509f, 0.008945702575147f, 0.094157725572586f, + 0.009018065407872f, 0.094534330070019f, 0.009090716950595f, 0.094910882413387f, + 0.009163657203317f, 0.095287375152111f, 0.009236886166036f, 0.095663815736771f, + 0.009310402907431f, 0.096040196716785f, 0.009384209290147f, 0.096416525542736f, + 0.009458304382861f, 0.096792794764042f, 0.009532688185573f, 0.097169004380703f, + 0.009607359766960f, 0.097545161843300f, 0.009682320058346f, 0.097921259701252f, + 0.009757569059730f, 0.098297297954559f, 0.009833106771111f, 0.098673284053802f, + 0.009908932261169f, 0.099049203097820f, 0.009985045529902f, 0.099425069987774f, + 0.010061448439956f, 0.099800877273083f, 0.010138138197362f, 0.100176624953747f, + 0.010215117596090f, 0.100552320480347f, 0.010292383842170f, 0.100927948951721f, + 0.010369938798249f, 0.101303517818451f, 0.010447781533003f, 0.101679034531116f, + 0.010525912046432f, 0.102054484188557f, 0.010604331269860f, 0.102429874241352f, + 0.010683037340641f, 0.102805204689503f, 0.010762032121420f, 0.103180475533009f, + 0.010841314680874f, 0.103555686771870f, 0.010920885019004f, 0.103930838406086f, + 0.011000742204487f, 0.104305922985077f, 0.011080888099968f, 0.104680955410004f, + 0.011161320842803f, 0.105055920779705f, 0.011242041364312f, 0.105430819094181f, + 0.011323049664497f, 0.105805665254593f, 0.011404345743358f, 0.106180444359779f, + 0.011485928669572f, 0.106555156409740f, 0.011567799374461f, 0.106929816305637f, + 0.011649956926703f, 0.107304409146309f, 0.011732402257621f, 0.107678934931755f, + 0.011815134435892f, 0.108053401112556f, 0.011898153461516f, 0.108427800238132f, + 0.011981460265815f, 0.108802139759064f, 0.012065053917468f, 0.109176412224770f, + 0.012148935347795f, 0.109550617635250f, 0.012233102694154f, 0.109924763441086f, + 0.012317557819188f, 0.110298842191696f, 0.012402298860252f, 0.110672861337662f, + 0.012487327679992f, 0.111046813428402f, 0.012572642415762f, 0.111420698463917f, + 0.012658244930208f, 0.111794516444206f, 0.012744133360684f, 0.112168267369270f, + 0.012830308638513f, 0.112541958689690f, 0.012916770763695f, 0.112915575504303f, + 0.013003518804908f, 0.113289132714272f, 0.013090553693473f, 0.113662622869015f, + 0.013177875429392f, 0.114036038517952f, 0.013265483081341f, 0.114409394562244f, + 0.013353376649320f, 0.114782683551311f, 0.013441557064652f, 0.115155905485153f, + 0.013530024327338f, 0.115529052913189f, 0.013618776574731f, 0.115902140736580f, + 0.013707815669477f, 0.116275154054165f, 0.013797140680254f, 0.116648100316525f, + 0.013886751607060f, 0.117020979523659f, 0.013976648449898f, 0.117393791675568f, + 0.014066831208766f, 0.117766529321671f, 0.014157299883664f, 0.118139199912548f, + 0.014248054474592f, 0.118511803448200f, 0.014339094981551f, 0.118884332478046f, + 0.014430420473218f, 0.119256794452667f, 0.014522032812238f, 0.119629189372063f, + 0.014613929204643f, 0.120001509785652f, 0.014706112444401f, 0.120373763144016f, + 0.014798580668867f, 0.120745941996574f, 0.014891333878040f, 0.121118053793907f, + 0.014984373003244f, 0.121490091085434f, 0.015077698044479f, 0.121862053871155f, + 0.015171307139099f, 0.122233949601650f, 0.015265202149749f, 0.122605770826340f, + 0.015359382145107f, 0.122977524995804f, 0.015453847125173f, 0.123349204659462f, + 0.015548598021269f, 0.123720809817314f, 0.015643632039428f, 0.124092340469360f, + 0.015738952904940f, 0.124463804066181f, 0.015834558755159f, 0.124835193157196f, + 0.015930447727442f, 0.125206500291824f, 0.016026621684432f, 0.125577747821808f, + 0.016123080626130f, 0.125948905944824f, 0.016219824552536f, 0.126320004463196f, + 0.016316853463650f, 0.126691013574600f, 0.016414167359471f, 0.127061963081360f, + 0.016511764377356f, 0.127432823181152f, 0.016609646379948f, 0.127803623676300f, + 0.016707813367248f, 0.128174334764481f, 0.016806263476610f, 0.128544986248016f, + 0.016904998570681f, 0.128915548324585f, 0.017004016786814f, 0.129286035895348f, + 0.017103319987655f, 0.129656463861465f, 0.017202908173203f, 0.130026802420616f, + 0.017302779480815f, 0.130397051572800f, 0.017402933910489f, 0.130767241120338f, + 0.017503373324871f, 0.131137356162071f, 0.017604095861316f, 0.131507381796837f, + 0.017705103382468f, 0.131877332925797f, 0.017806394025683f, 0.132247209548950f, + 0.017907967790961f, 0.132617011666298f, 0.018009826540947f, 0.132986739277840f, + 0.018111966550350f, 0.133356377482414f, 0.018214391544461f, 0.133725941181183f, + 0.018317099660635f, 0.134095430374146f, 0.018420090898871f, 0.134464830160141f, + 0.018523367121816f, 0.134834155440331f, 0.018626924604177f, 0.135203406214714f, + 0.018730765208602f, 0.135572582483292f, 0.018834890797734f, 0.135941669344902f, + 0.018939297646284f, 0.136310681700706f, 0.019043987616897f, 0.136679604649544f, + 0.019148962572217f, 0.137048453092575f, 0.019254218786955f, 0.137417227029800f, + 0.019359756261110f, 0.137785911560059f, 0.019465578719974f, 0.138154521584511f, + 0.019571684300900f, 0.138523042201996f, 0.019678071141243f, 0.138891488313675f, + 0.019784741103649f, 0.139259845018387f, 0.019891692325473f, 0.139628127217293f, + 0.019998926669359f, 0.139996320009232f, 0.020106444135308f, 0.140364438295364f, + 0.020214242860675f, 0.140732467174530f, 0.020322324708104f, 0.141100421547890f, + 0.020430689677596f, 0.141468286514282f, 0.020539334043860f, 0.141836062073708f, + 0.020648263394833f, 0.142203763127327f, 0.020757472142577f, 0.142571389675140f, + 0.020866964012384f, 0.142938911914825f, 0.020976737141609f, 0.143306359648705f, + 0.021086793392897f, 0.143673732876778f, 0.021197130903602f, 0.144041016697884f, + 0.021307749673724f, 0.144408211112022f, 0.021418649703264f, 0.144775316119194f, + 0.021529832854867f, 0.145142331719399f, 0.021641295403242f, 0.145509272813797f, + 0.021753041073680f, 0.145876124501228f, 0.021865066140890f, 0.146242901682854f, + 0.021977374330163f, 0.146609574556351f, 0.022089963778853f, 0.146976172924042f, + 0.022202832624316f, 0.147342681884766f, 0.022315984591842f, 0.147709101438522f, + 0.022429415956140f, 0.148075446486473f, 0.022543128579855f, 0.148441687226295f, + 0.022657122462988f, 0.148807853460312f, 0.022771397605538f, 0.149173930287361f, + 0.022885952144861f, 0.149539917707443f, 0.023000787943602f, 0.149905815720558f, + 0.023115905001760f, 0.150271624326706f, 0.023231301456690f, 0.150637343525887f, + 0.023346979171038f, 0.151002973318100f, 0.023462938144803f, 0.151368513703346f, + 0.023579176515341f, 0.151733979582787f, 0.023695694282651f, 0.152099341154099f, + 0.023812493309379f, 0.152464613318443f, 0.023929571732879f, 0.152829796075821f, + 0.024046931415796f, 0.153194904327393f, 0.024164570495486f, 0.153559908270836f, + 0.024282488971949f, 0.153924822807312f, 0.024400688707829f, 0.154289647936821f, + 0.024519165977836f, 0.154654383659363f, 0.024637924507260f, 0.155019029974937f, + 0.024756962433457f, 0.155383571982384f, 0.024876279756427f, 0.155748039484024f, + 0.024995878338814f, 0.156112402677536f, 0.025115754455328f, 0.156476691365242f, + 0.025235909968615f, 0.156840875744820f, 0.025356344878674f, 0.157204970717430f, + 0.025477059185505f, 0.157568961381912f, 0.025598052889109f, 0.157932877540588f, + 0.025719324126840f, 0.158296689391136f, 0.025840876623988f, 0.158660411834717f, + 0.025962706655264f, 0.159024044871330f, 0.026084816083312f, 0.159387573599815f, + 0.026207204908133f, 0.159751012921333f, 0.026329871267080f, 0.160114362835884f, + 0.026452817022800f, 0.160477623343468f, 0.026576040312648f, 0.160840779542923f, + 0.026699542999268f, 0.161203846335411f, 0.026823325082660f, 0.161566808819771f, + 0.026947384700179f, 0.161929681897163f, 0.027071721851826f, 0.162292465567589f, + 0.027196336537600f, 0.162655144929886f, 0.027321230620146f, 0.163017734885216f, + 0.027446404099464f, 0.163380220532417f, 0.027571853250265f, 0.163742616772652f, + 0.027697581797838f, 0.164104923605919f, 0.027823587879539f, 0.164467126131058f, + 0.027949871495366f, 0.164829224348068f, 0.028076432645321f, 0.165191248059273f, + 0.028203271329403f, 0.165553152561188f, 0.028330387547612f, 0.165914967656136f, + 0.028457781299949f, 0.166276678442955f, 0.028585452586412f, 0.166638299822807f, + 0.028713401407003f, 0.166999831795692f, 0.028841627761722f, 0.167361244559288f, + 0.028970129787922f, 0.167722567915916f, 0.029098909348249f, 0.168083801865578f, + 0.029227968305349f, 0.168444931507111f, 0.029357301071286f, 0.168805956840515f, + 0.029486913233995f, 0.169166877865791f, 0.029616801068187f, 0.169527709484100f, + 0.029746964573860f, 0.169888436794281f, 0.029877405613661f, 0.170249074697495f, + 0.030008124187589f, 0.170609608292580f, 0.030139118432999f, 0.170970037579536f, + 0.030270388349891f, 0.171330362558365f, 0.030401935800910f, 0.171690583229065f, + 0.030533758923411f, 0.172050714492798f, 0.030665857717395f, 0.172410741448402f, + 0.030798232182860f, 0.172770664095879f, 0.030930884182453f, 0.173130482435226f, + 0.031063811853528f, 0.173490211367607f, 0.031197015196085f, 0.173849821090698f, + 0.031330492347479f, 0.174209341406822f, 0.031464248895645f, 0.174568757414818f, + 0.031598277390003f, 0.174928069114685f, 0.031732585281134f, 0.175287276506424f, + 0.031867165118456f, 0.175646379590034f, 0.032002024352551f, 0.176005378365517f, + 0.032137155532837f, 0.176364272832870f, 0.032272562384605f, 0.176723077893257f, + 0.032408244907856f, 0.177081763744354f, 0.032544203102589f, 0.177440345287323f, + 0.032680433243513f, 0.177798837423325f, 0.032816942781210f, 0.178157210350037f, + 0.032953724265099f, 0.178515478968620f, 0.033090781420469f, 0.178873643279076f, + 0.033228114247322f, 0.179231703281403f, 0.033365719020367f, 0.179589673876762f, + 0.033503599464893f, 0.179947525262833f, 0.033641755580902f, 0.180305257439613f, + 0.033780183643103f, 0.180662900209427f, 0.033918887376785f, 0.181020438671112f, + 0.034057866781950f, 0.181377857923508f, 0.034197118133307f, 0.181735187768936f, + 0.034336645156145f, 0.182092398405075f, 0.034476444125175f, 0.182449504733086f, + 0.034616518765688f, 0.182806491851807f, 0.034756865352392f, 0.183163389563560f, + 0.034897487610579f, 0.183520168066025f, 0.035038381814957f, 0.183876842260361f, + 0.035179551690817f, 0.184233412146568f, 0.035320993512869f, 0.184589877724648f, + 0.035462711006403f, 0.184946224093437f, 0.035604696720839f, 0.185302466154099f, + 0.035746958106756f, 0.185658603906631f, 0.035889495164156f, 0.186014622449875f, + 0.036032304167747f, 0.186370536684990f, 0.036175385117531f, 0.186726331710815f, + 0.036318738013506f, 0.187082037329674f, 0.036462362855673f, 0.187437608838081f, + 0.036606263369322f, 0.187793090939522f, 0.036750435829163f, 0.188148453831673f, + 0.036894880235195f, 0.188503712415695f, 0.037039596587420f, 0.188858851790428f, + 0.037184584885836f, 0.189213871955872f, 0.037329845130444f, 0.189568802714348f, + 0.037475381046534f, 0.189923599362373f, 0.037621185183525f, 0.190278306603432f, + 0.037767261266708f, 0.190632879734039f, 0.037913613021374f, 0.190987363457680f, + 0.038060232996941f, 0.191341713070869f, 0.038207128643990f, 0.191695958375931f, + 0.038354292511940f, 0.192050099372864f, 0.038501728326082f, 0.192404121160507f, + 0.038649436086416f, 0.192758023738861f, 0.038797415792942f, 0.193111822009087f, + 0.038945667445660f, 0.193465501070023f, 0.039094187319279f, 0.193819075822830f, + 0.039242979139090f, 0.194172516465187f, 0.039392042905092f, 0.194525867700577f, + 0.039541378617287f, 0.194879084825516f, 0.039690986275673f, 0.195232197642326f, + 0.039840862154961f, 0.195585191249847f, 0.039991009980440f, 0.195938065648079f, + 0.040141426026821f, 0.196290835738182f, 0.040292114019394f, 0.196643486618996f, + 0.040443073958158f, 0.196996018290520f, 0.040594302117825f, 0.197348430752754f, + 0.040745802223682f, 0.197700738906860f, 0.040897574275732f, 0.198052927851677f, + 0.041049610823393f, 0.198404997587204f, 0.041201923042536f, 0.198756948113441f, + 0.041354499757290f, 0.199108779430389f, 0.041507352143526f, 0.199460506439209f, + 0.041660469025373f, 0.199812099337578f, 0.041813857853413f, 0.200163587927818f, + 0.041967518627644f, 0.200514942407608f, 0.042121443897486f, 0.200866192579269f, + 0.042275641113520f, 0.201217323541641f, 0.042430106550455f, 0.201568335294724f, + 0.042584843933582f, 0.201919227838516f, 0.042739849537611f, 0.202270001173019f, + 0.042895123362541f, 0.202620655298233f, 0.043050665408373f, 0.202971190214157f, + 0.043206475675106f, 0.203321605920792f, 0.043362557888031f, 0.203671902418137f, + 0.043518904596567f, 0.204022079706192f, 0.043675523251295f, 0.204372137784958f, + 0.043832406401634f, 0.204722076654434f, 0.043989561498165f, 0.205071896314621f, + 0.044146984815598f, 0.205421581864357f, 0.044304672628641f, 0.205771163105965f, + 0.044462632387877f, 0.206120610237122f, 0.044620860368013f, 0.206469938158989f, + 0.044779352843761f, 0.206819161772728f, 0.044938117265701f, 0.207168251276016f, + 0.045097146183252f, 0.207517206668854f, 0.045256443321705f, 0.207866057753563f, + 0.045416008681059f, 0.208214774727821f, 0.045575842261314f, 0.208563387393951f, + 0.045735940337181f, 0.208911851048470f, 0.045896306633949f, 0.209260210394859f, + 0.046056941151619f, 0.209608450531960f, 0.046217843890190f, 0.209956556558609f, + 0.046379011124372f, 0.210304543375969f, 0.046540446579456f, 0.210652396082878f, + 0.046702146530151f, 0.211000129580498f, 0.046864114701748f, 0.211347743868828f, + 0.047026351094246f, 0.211695238947868f, 0.047188851982355f, 0.212042599916458f, + 0.047351621091366f, 0.212389841675758f, 0.047514654695988f, 0.212736949324608f, + 0.047677956521511f, 0.213083937764168f, 0.047841522842646f, 0.213430806994438f, + 0.048005353659391f, 0.213777542114258f, 0.048169452697039f, 0.214124158024788f, + 0.048333816230297f, 0.214470639824867f, 0.048498444259167f, 0.214817002415657f, + 0.048663340508938f, 0.215163245797157f, 0.048828501254320f, 0.215509355068207f, + 0.048993926495314f, 0.215855330228806f, 0.049159619957209f, 0.216201186180115f, + 0.049325577914715f, 0.216546908020973f, 0.049491796642542f, 0.216892510652542f, + 0.049658283591270f, 0.217237979173660f, 0.049825038760900f, 0.217583328485489f, + 0.049992054700851f, 0.217928543686867f, 0.050159335136414f, 0.218273624777794f, + 0.050326880067587f, 0.218618586659431f, 0.050494693219662f, 0.218963414430618f, + 0.050662767142057f, 0.219308122992516f, 0.050831105560064f, 0.219652697443962f, + 0.050999708473682f, 0.219997137784958f, 0.051168579608202f, 0.220341444015503f, + 0.051337707787752f, 0.220685631036758f, 0.051507104188204f, 0.221029683947563f, + 0.051676765084267f, 0.221373617649078f, 0.051846686750650f, 0.221717402338982f, + 0.052016876637936f, 0.222061067819595f, 0.052187327295542f, 0.222404599189758f, + 0.052358038723469f, 0.222748011350632f, 0.052529018372297f, 0.223091274499893f, + 0.052700258791447f, 0.223434418439865f, 0.052871759980917f, 0.223777428269386f, + 0.053043525665998f, 0.224120303988457f, 0.053215555846691f, 0.224463045597076f, + 0.053387850522995f, 0.224805667996407f, 0.053560405969620f, 0.225148141384125f, + 0.053733222186565f, 0.225490495562553f, 0.053906302899122f, 0.225832715630531f, + 0.054079644382000f, 0.226174786686897f, 0.054253250360489f, 0.226516738533974f, + 0.054427117109299f, 0.226858556270599f, 0.054601248353720f, 0.227200239896774f, + 0.054775636643171f, 0.227541789412498f, 0.054950293153524f, 0.227883204817772f, + 0.055125206708908f, 0.228224486112595f, 0.055300384759903f, 0.228565633296967f, + 0.055475823581219f, 0.228906646370888f, 0.055651523172855f, 0.229247525334358f, + 0.055827483534813f, 0.229588270187378f, 0.056003704667091f, 0.229928880929947f, + 0.056180190294981f, 0.230269357562065f, 0.056356932967901f, 0.230609700083733f, + 0.056533940136433f, 0.230949893593788f, 0.056711208075285f, 0.231289967894554f, + 0.056888736784458f, 0.231629893183708f, 0.057066522538662f, 0.231969684362412f, + 0.057244572788477f, 0.232309341430664f, 0.057422880083323f, 0.232648864388466f, + 0.057601451873779f, 0.232988253235817f, 0.057780280709267f, 0.233327493071556f, + 0.057959370315075f, 0.233666598796844f, 0.058138720691204f, 0.234005570411682f, + 0.058318331837654f, 0.234344407916069f, 0.058498200029135f, 0.234683111310005f, + 0.058678328990936f, 0.235021665692329f, 0.058858718723059f, 0.235360085964203f, + 0.059039369225502f, 0.235698372125626f, 0.059220276772976f, 0.236036509275436f, + 0.059401445090771f, 0.236374512314796f, 0.059582870453596f, 0.236712381243706f, + 0.059764556586742f, 0.237050101161003f, 0.059946499764919f, 0.237387686967850f, + 0.060128703713417f, 0.237725138664246f, 0.060311164706945f, 0.238062441349030f, + 0.060493886470795f, 0.238399609923363f, 0.060676865279675f, 0.238736644387245f, + 0.060860104858875f, 0.239073529839516f, 0.061043601483107f, 0.239410281181335f, + 0.061227355152369f, 0.239746883511543f, 0.061411365866661f, 0.240083336830139f, + 0.061595637351274f, 0.240419670939446f, 0.061780165880919f, 0.240755841135979f, + 0.061964951455593f, 0.241091892123222f, 0.062149997800589f, 0.241427779197693f, + 0.062335297465324f, 0.241763532161713f, 0.062520854175091f, 0.242099151015282f, + 0.062706671655178f, 0.242434620857239f, 0.062892749905586f, 0.242769956588745f, + 0.063079081475735f, 0.243105143308640f, 0.063265666365623f, 0.243440181016922f, + 0.063452512025833f, 0.243775084614754f, 0.063639611005783f, 0.244109839200974f, + 0.063826970756054f, 0.244444444775581f, 0.064014583826065f, 0.244778916239738f, + 0.064202457666397f, 0.245113238692284f, 0.064390584826469f, 0.245447427034378f, + 0.064578965306282f, 0.245781451463699f, 0.064767606556416f, 0.246115356683731f, + 0.064956501126289f, 0.246449097990990f, 0.065145656466484f, 0.246782705187798f, + 0.065335065126419f, 0.247116148471832f, 0.065524727106094f, 0.247449472546577f, + 0.065714649856091f, 0.247782632708550f, 0.065904818475246f, 0.248115643858910f, + 0.066095255315304f, 0.248448520898819f, 0.066285938024521f, 0.248781248927116f, + 0.066476874053478f, 0.249113827943802f, 0.066668070852757f, 0.249446272850037f, + 0.066859520971775f, 0.249778553843498f, 0.067051224410534f, 0.250110685825348f, + 0.067243188619614f, 0.250442683696747f, 0.067435398697853f, 0.250774532556534f, + 0.067627869546413f, 0.251106232404709f, 0.067820593714714f, 0.251437783241272f, + 0.068013571202755f, 0.251769185066223f, 0.068206802010536f, 0.252100437879562f, + 0.068400286138058f, 0.252431541681290f, 0.068594031035900f, 0.252762526273727f, + 0.068788021802902f, 0.253093332052231f, 0.068982265889645f, 0.253423988819122f, + 0.069176770746708f, 0.253754496574402f, 0.069371521472931f, 0.254084855318069f, + 0.069566532969475f, 0.254415065050125f, 0.069761790335178f, 0.254745125770569f, + 0.069957308471203f, 0.255075037479401f, 0.070153072476387f, 0.255404800176620f, + 0.070349089801311f, 0.255734413862228f, 0.070545360445976f, 0.256063878536224f, + 0.070741884410381f, 0.256393194198608f, 0.070938661694527f, 0.256722360849380f, + 0.071135692298412f, 0.257051378488541f, 0.071332976222038f, 0.257380217313766f, + 0.071530513465405f, 0.257708936929703f, 0.071728296577930f, 0.258037507534027f, + 0.071926333010197f, 0.258365899324417f, 0.072124622762203f, 0.258694142103195f, + 0.072323165833950f, 0.259022265672684f, 0.072521962225437f, 0.259350210428238f, + 0.072721004486084f, 0.259678006172180f, 0.072920300066471f, 0.260005623102188f, + 0.073119848966599f, 0.260333120822906f, 0.073319651186466f, 0.260660469532013f, + 0.073519699275494f, 0.260987639427185f, 0.073720000684261f, 0.261314690113068f, + 0.073920547962189f, 0.261641561985016f, 0.074121348559856f, 0.261968284845352f, + 0.074322402477264f, 0.262294828891754f, 0.074523709714413f, 0.262621253728867f, + 0.074725262820721f, 0.262947499752045f, 0.074927061796188f, 0.263273626565933f, + 0.075129114091396f, 0.263599574565887f, 0.075331419706345f, 0.263925373554230f, + 0.075533971190453f, 0.264250993728638f, 0.075736775994301f, 0.264576494693756f, + 0.075939826667309f, 0.264901816844940f, 0.076143130660057f, 0.265226989984512f, + 0.076346680521965f, 0.265552014112473f, 0.076550483703613f, 0.265876859426498f, + 0.076754532754421f, 0.266201555728912f, 0.076958827674389f, 0.266526103019714f, + 0.077163375914097f, 0.266850501298904f, 0.077368170022964f, 0.267174720764160f, + 0.077573217451572f, 0.267498821020126f, 0.077778510749340f, 0.267822742462158f, + 0.077984049916267f, 0.268146485090256f, 0.078189842402935f, 0.268470078706741f, + 0.078395880758762f, 0.268793523311615f, 0.078602164983749f, 0.269116818904877f, + 0.078808702528477f, 0.269439965486526f, 0.079015478491783f, 0.269762933254242f, + 0.079222507774830f, 0.270085722208023f, 0.079429790377617f, 0.270408391952515f, + 0.079637311398983f, 0.270730882883072f, 0.079845085740089f, 0.271053224802017f, + 0.080053105950356f, 0.271375387907028f, 0.080261372029781f, 0.271697402000427f, + 0.080469883978367f, 0.272019267082214f, 0.080678641796112f, 0.272340953350067f, + 0.080887645483017f, 0.272662490606308f, 0.081096902489662f, 0.272983878850937f, + 0.081306397914886f, 0.273305088281631f, 0.081516146659851f, 0.273626148700714f, + 0.081726133823395f, 0.273947030305862f, 0.081936374306679f, 0.274267762899399f, + 0.082146860659122f, 0.274588316679001f, 0.082357585430145f, 0.274908751249313f, + 0.082568563520908f, 0.275228977203369f, 0.082779780030251f, 0.275549083948135f, + 0.082991249859333f, 0.275868982076645f, 0.083202958106995f, 0.276188760995865f, + 0.083414919674397f, 0.276508361101151f, 0.083627119660378f, 0.276827782392502f, + 0.083839565515518f, 0.277147054672241f, 0.084052257239819f, 0.277466177940369f, + 0.084265194833279f, 0.277785122394562f, 0.084478378295898f, 0.278103888034821f, + 0.084691800177097f, 0.278422504663467f, 0.084905467927456f, 0.278740972280502f, + 0.085119381546974f, 0.279059261083603f, 0.085333541035652f, 0.279377400875092f, + 0.085547938942909f, 0.279695361852646f, 0.085762590169907f, 0.280013144016266f, + 0.085977479815483f, 0.280330777168274f, 0.086192607879639f, 0.280648261308670f, + 0.086407989263535f, 0.280965566635132f, 0.086623609066010f, 0.281282693147659f, + 0.086839467287064f, 0.281599670648575f, 0.087055571377277f, 0.281916469335556f, + 0.087271921336651f, 0.282233119010925f, 0.087488517165184f, 0.282549589872360f, + 0.087705351412296f, 0.282865911722183f, 0.087922424077988f, 0.283182054758072f, + 0.088139742612839f, 0.283498018980026f, 0.088357307016850f, 0.283813834190369f, + 0.088575109839439f, 0.284129470586777f, 0.088793158531189f, 0.284444957971573f, + 0.089011445641518f, 0.284760266542435f, 0.089229971170425f, 0.285075396299362f, + 0.089448742568493f, 0.285390377044678f, 0.089667752385139f, 0.285705178976059f, + 0.089887008070946f, 0.286019802093506f, 0.090106502175331f, 0.286334276199341f, + 0.090326242148876f, 0.286648571491241f, 0.090546220541000f, 0.286962717771530f, + 0.090766437351704f, 0.287276685237885f, 0.090986892580986f, 0.287590473890305f, + 0.091207593679428f, 0.287904083728790f, 0.091428533196449f, 0.288217544555664f, + 0.091649711132050f, 0.288530826568604f, 0.091871134936810f, 0.288843959569931f, + 0.092092797160149f, 0.289156883955002f, 0.092314697802067f, 0.289469659328461f, + 0.092536836862564f, 0.289782285690308f, 0.092759214341640f, 0.290094703435898f, + 0.092981837689877f, 0.290406972169876f, 0.093204692006111f, 0.290719062089920f, + 0.093427792191505f, 0.291031002998352f, 0.093651130795479f, 0.291342735290527f, + 0.093874707818031f, 0.291654318571091f, 0.094098523259163f, 0.291965723037720f, + 0.094322577118874f, 0.292276978492737f, 0.094546869397163f, 0.292588025331497f, + 0.094771400094032f, 0.292898923158646f, 0.094996169209480f, 0.293209642171860f, + 0.095221176743507f, 0.293520182371140f, 0.095446422696114f, 0.293830573558807f, + 0.095671907067299f, 0.294140785932541f, 0.095897629857063f, 0.294450789690018f, + 0.096123591065407f, 0.294760644435883f, 0.096349790692329f, 0.295070350170136f, + 0.096576221287251f, 0.295379847288132f, 0.096802897751331f, 0.295689195394516f, + 0.097029805183411f, 0.295998334884644f, 0.097256951034069f, 0.296307325363159f, + 0.097484335303307f, 0.296616137027740f, 0.097711957991123f, 0.296924799680710f, + 0.097939811646938f, 0.297233253717422f, 0.098167903721333f, 0.297541528940201f, + 0.098396234214306f, 0.297849655151367f, 0.098624803125858f, 0.298157602548599f, + 0.098853603005409f, 0.298465341329575f, 0.099082641303539f, 0.298772931098938f, + 0.099311910569668f, 0.299080342054367f, 0.099541425704956f, 0.299387603998184f, + 0.099771171808243f, 0.299694657325745f, 0.100001148879528f, 0.300001531839371f, + 0.100231364369392f, 0.300308227539063f, 0.100461818277836f, 0.300614774227142f, + 0.100692503154278f, 0.300921112298965f, 0.100923426449299f, 0.301227301359177f, + 0.101154580712318f, 0.301533311605453f, 0.101385973393917f, 0.301839113235474f, + 0.101617597043514f, 0.302144765853882f, 0.101849451661110f, 0.302450239658356f, + 0.102081544697285f, 0.302755534648895f, 0.102313876152039f, 0.303060621023178f, + 0.102546438574791f, 0.303365558385849f, 0.102779231965542f, 0.303670316934586f, + 0.103012263774872f, 0.303974896669388f, 0.103245526552200f, 0.304279297590256f, + 0.103479020297527f, 0.304583519697189f, 0.103712752461433f, 0.304887533187866f, + 0.103946708142757f, 0.305191397666931f, 0.104180909693241f, 0.305495083332062f, + 0.104415334761143f, 0.305798590183258f, 0.104649998247623f, 0.306101888418198f, + 0.104884892702103f, 0.306405037641525f, 0.105120018124580f, 0.306708008050919f, + 0.105355374515057f, 0.307010769844055f, 0.105590961873531f, 0.307313382625580f, + 0.105826787650585f, 0.307615786790848f, 0.106062836945057f, 0.307918041944504f, + 0.106299124658108f, 0.308220088481903f, 0.106535643339157f, 0.308521956205368f, + 0.106772392988205f, 0.308823645114899f, 0.107009373605251f, 0.309125155210495f, + 0.107246585190296f, 0.309426486492157f, 0.107484027743340f, 0.309727638959885f, + 0.107721701264381f, 0.310028612613678f, 0.107959605753422f, 0.310329377651215f, + 0.108197741210461f, 0.310629993677139f, 0.108436107635498f, 0.310930401086807f, + 0.108674705028534f, 0.311230629682541f, 0.108913525938988f, 0.311530679464340f, + 0.109152585268021f, 0.311830550432205f, 0.109391868114471f, 0.312130242586136f, + 0.109631389379501f, 0.312429755926132f, 0.109871134161949f, 0.312729060649872f, + 0.110111102461815f, 0.313028186559677f, 0.110351309180260f, 0.313327133655548f, + 0.110591746866703f, 0.313625901937485f, 0.110832408070564f, 0.313924491405487f, + 0.111073300242424f, 0.314222872257233f, 0.111314415931702f, 0.314521104097366f, + 0.111555770039558f, 0.314819127321243f, 0.111797347664833f, 0.315116971731186f, + 0.112039148807526f, 0.315414607524872f, 0.112281180918217f, 0.315712094306946f, + 0.112523443996906f, 0.316009372472763f, 0.112765938043594f, 0.316306471824646f, + 0.113008655607700f, 0.316603392362595f, 0.113251596689224f, 0.316900104284287f, + 0.113494776189327f, 0.317196637392044f, 0.113738171756268f, 0.317492991685867f, + 0.113981798291206f, 0.317789167165756f, 0.114225655794144f, 0.318085134029388f, + 0.114469736814499f, 0.318380922079086f, 0.114714048802853f, 0.318676531314850f, + 0.114958584308624f, 0.318971961736679f, 0.115203343331814f, 0.319267183542252f, + 0.115448333323002f, 0.319562226533890f, 0.115693546831608f, 0.319857090711594f, + 0.115938983857632f, 0.320151746273041f, 0.116184651851654f, 0.320446223020554f, + 0.116430543363094f, 0.320740520954132f, 0.116676658391953f, 0.321034610271454f, + 0.116923004388809f, 0.321328520774841f, 0.117169573903084f, 0.321622252464294f, + 0.117416366934776f, 0.321915775537491f, 0.117663383483887f, 0.322209119796753f, + 0.117910631000996f, 0.322502255439758f, 0.118158094584942f, 0.322795242071152f, + 0.118405789136887f, 0.323088020086288f, 0.118653707206249f, 0.323380589485168f, + 0.118901848793030f, 0.323672980070114f, 0.119150213897228f, 0.323965191841125f, + 0.119398809969425f, 0.324257194995880f, 0.119647622108459f, 0.324549019336700f, + 0.119896657764912f, 0.324840664863586f, 0.120145916938782f, 0.325132101774216f, + 0.120395407080650f, 0.325423330068588f, 0.120645113289356f, 0.325714409351349f, + 0.120895043015480f, 0.326005280017853f, 0.121145196259022f, 0.326295942068100f, + 0.121395580470562f, 0.326586425304413f, 0.121646173298359f, 0.326876699924469f, + 0.121896997094154f, 0.327166795730591f, 0.122148044407368f, 0.327456712722778f, + 0.122399315237999f, 0.327746421098709f, 0.122650802135468f, 0.328035950660706f, + 0.122902512550354f, 0.328325271606445f, 0.123154446482658f, 0.328614413738251f, + 0.123406603932381f, 0.328903347253799f, 0.123658977448940f, 0.329192101955414f, + 0.123911574482918f, 0.329480648040771f, 0.124164395034313f, 0.329769015312195f, + 0.124417431652546f, 0.330057173967361f, 0.124670691788197f, 0.330345153808594f, + 0.124924175441265f, 0.330632925033569f, 0.125177875161171f, 0.330920487642288f, + 0.125431805849075f, 0.331207901239395f, 0.125685945153236f, 0.331495076417923f, + 0.125940307974815f, 0.331782072782516f, 0.126194894313812f, 0.332068890333176f, + 0.126449704170227f, 0.332355499267578f, 0.126704722642899f, 0.332641899585724f, + 0.126959964632988f, 0.332928121089935f, 0.127215430140495f, 0.333214133977890f, + 0.127471104264259f, 0.333499968051910f, 0.127727001905441f, 0.333785593509674f, + 0.127983123064041f, 0.334071010351181f, 0.128239467740059f, 0.334356248378754f, + 0.128496021032333f, 0.334641307592392f, 0.128752797842026f, 0.334926128387451f, + 0.129009798169136f, 0.335210770368576f, 0.129267007112503f, 0.335495233535767f, + 0.129524439573288f, 0.335779488086700f, 0.129782080650330f, 0.336063534021378f, + 0.130039945244789f, 0.336347371339798f, 0.130298033356667f, 0.336631029844284f, + 0.130556344985962f, 0.336914509534836f, 0.130814850330353f, 0.337197750806808f, + 0.131073594093323f, 0.337480813264847f, 0.131332546472549f, 0.337763696908951f, + 0.131591722369194f, 0.338046342134476f, 0.131851106882095f, 0.338328808546066f, + 0.132110700011253f, 0.338611096143723f, 0.132370531558990f, 0.338893145322800f, + 0.132630556821823f, 0.339175015687943f, 0.132890805602074f, 0.339456677436829f, + 0.133151277899742f, 0.339738160371780f, 0.133411958813667f, 0.340019434690475f, + 0.133672863245010f, 0.340300500392914f, 0.133933976292610f, 0.340581357479095f, + 0.134195312857628f, 0.340862035751343f, 0.134456858038902f, 0.341142505407333f, + 0.134718611836433f, 0.341422766447067f, 0.134980589151382f, 0.341702848672867f, + 0.135242775082588f, 0.341982692480087f, 0.135505184531212f, 0.342262357473373f, + 0.135767802596092f, 0.342541843652725f, 0.136030644178391f, 0.342821091413498f, + 0.136293679475784f, 0.343100160360336f, 0.136556953191757f, 0.343379020690918f, + 0.136820420622826f, 0.343657672405243f, 0.137084111571312f, 0.343936115503311f, + 0.137348011136055f, 0.344214379787445f, 0.137612134218216f, 0.344492435455322f, + 0.137876465916634f, 0.344770282506943f, 0.138141006231308f, 0.345047920942307f, + 0.138405755162239f, 0.345325350761414f, 0.138670727610588f, 0.345602601766586f, + 0.138935908675194f, 0.345879614353180f, 0.139201298356056f, 0.346156448125839f, + 0.139466896653175f, 0.346433073282242f, 0.139732718467712f, 0.346709519624710f, + 0.139998748898506f, 0.346985727548599f, 0.140264987945557f, 0.347261756658554f, + 0.140531435608864f, 0.347537547349930f, 0.140798106789589f, 0.347813159227371f, + 0.141064971685410f, 0.348088562488556f, 0.141332060098648f, 0.348363757133484f, + 0.141599357128143f, 0.348638743162155f, 0.141866862773895f, 0.348913550376892f, + 0.142134591937065f, 0.349188119173050f, 0.142402514815331f, 0.349462509155273f, + 0.142670661211014f, 0.349736660718918f, 0.142939001321793f, 0.350010633468628f, + 0.143207564949989f, 0.350284397602081f, 0.143476337194443f, 0.350557953119278f, + 0.143745318055153f, 0.350831300020218f, 0.144014507532120f, 0.351104438304901f, + 0.144283905625343f, 0.351377367973328f, 0.144553512334824f, 0.351650089025497f, + 0.144823327660561f, 0.351922631263733f, 0.145093351602554f, 0.352194935083389f, + 0.145363584160805f, 0.352467030286789f, 0.145634025335312f, 0.352738946676254f, + 0.145904675126076f, 0.353010624647141f, 0.146175548434258f, 0.353282123804092f, + 0.146446615457535f, 0.353553384542465f, 0.146717891097069f, 0.353824466466904f, + 0.146989375352860f, 0.354095309972763f, 0.147261068224907f, 0.354365974664688f, + 0.147532954812050f, 0.354636400938034f, 0.147805064916611f, 0.354906648397446f, + 0.148077383637428f, 0.355176687240601f, 0.148349896073341f, 0.355446487665176f, + 0.148622632026672f, 0.355716109275818f, 0.148895561695099f, 0.355985492467880f, + 0.149168699979782f, 0.356254696846008f, 0.149442046880722f, 0.356523662805557f, + 0.149715602397919f, 0.356792420148849f, 0.149989366531372f, 0.357060998678207f, + 0.150263324379921f, 0.357329338788986f, 0.150537505745888f, 0.357597470283508f, + 0.150811880826950f, 0.357865422964096f, 0.151086464524269f, 0.358133137226105f, + 0.151361241936684f, 0.358400642871857f, 0.151636242866516f, 0.358667939901352f, + 0.151911437511444f, 0.358935028314590f, 0.152186840772629f, 0.359201908111572f, + 0.152462437748909f, 0.359468549489975f, 0.152738258242607f, 0.359735012054443f, + 0.153014272451401f, 0.360001266002655f, 0.153290495276451f, 0.360267281532288f, + 0.153566911816597f, 0.360533088445663f, 0.153843536973000f, 0.360798716545105f, + 0.154120370745659f, 0.361064106225967f, 0.154397398233414f, 0.361329287290573f, + 0.154674649238586f, 0.361594229936600f, 0.154952079057693f, 0.361858993768692f, + 0.155229732394218f, 0.362123548984528f, 0.155507579445839f, 0.362387865781784f, + 0.155785620212555f, 0.362651973962784f, 0.156063869595528f, 0.362915903329849f, + 0.156342327594757f, 0.363179564476013f, 0.156620979309082f, 0.363443046808243f, + 0.156899839639664f, 0.363706320524216f, 0.157178908586502f, 0.363969355821610f, + 0.157458171248436f, 0.364232182502747f, 0.157737627625465f, 0.364494800567627f, + 0.158017292618752f, 0.364757210016251f, 0.158297166228294f, 0.365019410848618f, + 0.158577233552933f, 0.365281373262405f, 0.158857494592667f, 0.365543156862259f, + 0.159137964248657f, 0.365804702043533f, 0.159418627619743f, 0.366066008806229f, + 0.159699499607086f, 0.366327136754990f, 0.159980565309525f, 0.366588026285172f, + 0.160261839628220f, 0.366848707199097f, 0.160543307662010f, 0.367109179496765f, + 0.160824984312058f, 0.367369443178177f, 0.161106839776039f, 0.367629468441010f, + 0.161388918757439f, 0.367889285087585f, 0.161671176552773f, 0.368148893117905f, + 0.161953642964363f, 0.368408292531967f, 0.162236317992210f, 0.368667453527451f, + 0.162519171833992f, 0.368926405906677f, 0.162802234292030f, 0.369185149669647f, + 0.163085505366325f, 0.369443655014038f, 0.163368955254555f, 0.369701951742172f, + 0.163652613759041f, 0.369960039854050f, 0.163936465978622f, 0.370217919349670f, + 0.164220526814461f, 0.370475560426712f, 0.164504766464233f, 0.370732992887497f, + 0.164789214730263f, 0.370990216732025f, 0.165073871612549f, 0.371247202157974f, + 0.165358707308769f, 0.371503978967667f, 0.165643751621246f, 0.371760547161102f, + 0.165928974747658f, 0.372016876935959f, 0.166214406490326f, 0.372272998094559f, + 0.166500031948090f, 0.372528880834579f, 0.166785866022110f, 0.372784584760666f, + 0.167071878910065f, 0.373040050268173f, 0.167358100414276f, 0.373295277357101f, + 0.167644515633583f, 0.373550295829773f, 0.167931124567986f, 0.373805105686188f, + 0.168217927217484f, 0.374059677124023f, 0.168504923582077f, 0.374314039945602f, + 0.168792113661766f, 0.374568194150925f, 0.169079497456551f, 0.374822109937668f, + 0.169367074966431f, 0.375075817108154f, 0.169654861092567f, 0.375329315662384f, + 0.169942826032639f, 0.375582575798035f, 0.170230999588966f, 0.375835597515106f, + 0.170519351959229f, 0.376088410615921f, 0.170807912945747f, 0.376341015100479f, + 0.171096652746201f, 0.376593410968781f, 0.171385586261749f, 0.376845568418503f, + 0.171674728393555f, 0.377097487449646f, 0.171964049339294f, 0.377349197864532f, + 0.172253578901291f, 0.377600699663162f, 0.172543287277222f, 0.377851963043213f, + 0.172833189368248f, 0.378102988004684f, 0.173123285174370f, 0.378353834152222f, + 0.173413574695587f, 0.378604412078857f, 0.173704057931900f, 0.378854811191559f, + 0.173994734883308f, 0.379104942083359f, 0.174285605549812f, 0.379354894161224f, + 0.174576655030251f, 0.379604607820511f, 0.174867913126946f, 0.379854083061218f, + 0.175159350037575f, 0.380103349685669f, 0.175450980663300f, 0.380352377891541f, + 0.175742805004120f, 0.380601197481155f, 0.176034808158875f, 0.380849778652191f, + 0.176327019929886f, 0.381098151206970f, 0.176619410514832f, 0.381346285343170f, + 0.176911994814873f, 0.381594210863113f, 0.177204772830009f, 0.381841897964478f, + 0.177497729659081f, 0.382089376449585f, 0.177790880203247f, 0.382336616516113f, + 0.178084224462509f, 0.382583618164063f, 0.178377762436867f, 0.382830440998077f, + 0.178671479225159f, 0.383076995611191f, 0.178965389728546f, 0.383323341608047f, + 0.179259493947029f, 0.383569449186325f, 0.179553776979446f, 0.383815348148346f, + 0.179848253726959f, 0.384061008691788f, 0.180142924189568f, 0.384306460618973f, + 0.180437773466110f, 0.384551674127579f, 0.180732816457748f, 0.384796649217606f, + 0.181028053164482f, 0.385041415691376f, 0.181323468685150f, 0.385285943746567f, + 0.181619063019753f, 0.385530263185501f, 0.181914865970612f, 0.385774344205856f, + 0.182210832834244f, 0.386018186807632f, 0.182507008314133f, 0.386261820793152f, + 0.182803362607956f, 0.386505216360092f, 0.183099895715714f, 0.386748403310776f, + 0.183396622538567f, 0.386991351842880f, 0.183693528175354f, 0.387234061956406f, + 0.183990627527237f, 0.387476563453674f, 0.184287920594215f, 0.387718826532364f, + 0.184585392475128f, 0.387960851192474f, 0.184883043169975f, 0.388202667236328f, + 0.185180887579918f, 0.388444244861603f, 0.185478910803795f, 0.388685584068298f, + 0.185777112841606f, 0.388926714658737f, 0.186075508594513f, 0.389167606830597f, + 0.186374098062515f, 0.389408260583878f, 0.186672851443291f, 0.389648675918579f, + 0.186971798539162f, 0.389888882637024f, 0.187270939350128f, 0.390128880739212f, + 0.187570258975029f, 0.390368610620499f, 0.187869757413864f, 0.390608131885529f, + 0.188169434666634f, 0.390847414731979f, 0.188469305634499f, 0.391086459159851f, + 0.188769355416298f, 0.391325294971466f, 0.189069598913193f, 0.391563892364502f, + 0.189370006322861f, 0.391802251338959f, 0.189670607447624f, 0.392040401697159f, + 0.189971387386322f, 0.392278283834457f, 0.190272361040115f, 0.392515957355499f, + 0.190573498606682f, 0.392753422260284f, 0.190874829888344f, 0.392990618944168f, + 0.191176339983940f, 0.393227607011795f, 0.191478043794632f, 0.393464356660843f, + 0.191779911518097f, 0.393700867891312f, 0.192081972956657f, 0.393937170505524f, + 0.192384198307991f, 0.394173204898834f, 0.192686617374420f, 0.394409030675888f, + 0.192989215254784f, 0.394644618034363f, 0.193292006850243f, 0.394879996776581f, + 0.193594962358475f, 0.395115107297897f, 0.193898096680641f, 0.395350009202957f, + 0.194201424717903f, 0.395584672689438f, 0.194504916667938f, 0.395819097757339f, + 0.194808602333069f, 0.396053284406662f, 0.195112451910973f, 0.396287262439728f, + 0.195416495203972f, 0.396520972251892f, 0.195720717310905f, 0.396754473447800f, + 0.196025103330612f, 0.396987736225128f, 0.196329683065414f, 0.397220760583878f, + 0.196634441614151f, 0.397453576326370f, 0.196939364075661f, 0.397686123847961f, + 0.197244480252266f, 0.397918462753296f, 0.197549775242805f, 0.398150533437729f, + 0.197855234146118f, 0.398382395505905f, 0.198160871863365f, 0.398614019155502f, + 0.198466703295708f, 0.398845434188843f, 0.198772698640823f, 0.399076581001282f, + 0.199078872799873f, 0.399307489395142f, 0.199385225772858f, 0.399538189172745f, + 0.199691757559776f, 0.399768620729446f, 0.199998468160629f, 0.399998843669891f, + 0.200305357575417f, 0.400228828191757f, 0.200612410902977f, 0.400458574295044f, + 0.200919643044472f, 0.400688081979752f, 0.201227053999901f, 0.400917351245880f, + 0.201534643769264f, 0.401146411895752f, 0.201842412352562f, 0.401375204324722f, + 0.202150344848633f, 0.401603758335114f, 0.202458456158638f, 0.401832103729248f, + 0.202766746282578f, 0.402060180902481f, 0.203075215220451f, 0.402288049459457f, + 0.203383848071098f, 0.402515679597855f, 0.203692659735680f, 0.402743041515350f, + 0.204001650214195f, 0.402970194816589f, 0.204310819506645f, 0.403197109699249f, + 0.204620152711868f, 0.403423786163330f, 0.204929664731026f, 0.403650224208832f, + 0.205239340662956f, 0.403876423835754f, 0.205549195408821f, 0.404102355241776f, + 0.205859228968620f, 0.404328078031540f, 0.206169426441193f, 0.404553562402725f, + 0.206479802727699f, 0.404778808355331f, 0.206790357828140f, 0.405003815889359f, + 0.207101076841354f, 0.405228585004807f, 0.207411959767342f, 0.405453115701675f, + 0.207723021507263f, 0.405677437782288f, 0.208034262061119f, 0.405901491641998f, + 0.208345666527748f, 0.406125307083130f, 0.208657249808311f, 0.406348884105682f, + 0.208969011902809f, 0.406572192907333f, 0.209280923008919f, 0.406795293092728f, + 0.209593027830124f, 0.407018154859543f, 0.209905281662941f, 0.407240778207779f, + 0.210217714309692f, 0.407463163137436f, 0.210530325770378f, 0.407685309648514f, + 0.210843101143837f, 0.407907217741013f, 0.211156040430069f, 0.408128857612610f, + 0.211469158530235f, 0.408350288867950f, 0.211782455444336f, 0.408571451902390f, + 0.212095901370049f, 0.408792406320572f, 0.212409526109695f, 0.409013092517853f, + 0.212723329663277f, 0.409233570098877f, 0.213037282228470f, 0.409453779459000f, + 0.213351413607597f, 0.409673750400543f, 0.213665723800659f, 0.409893482923508f, + 0.213980183005333f, 0.410112977027893f, 0.214294821023941f, 0.410332232713699f, + 0.214609622955322f, 0.410551249980927f, 0.214924603700638f, 0.410770028829575f, + 0.215239733457565f, 0.410988569259644f, 0.215555042028427f, 0.411206841468811f, + 0.215870529413223f, 0.411424905061722f, 0.216186165809631f, 0.411642700433731f, + 0.216501981019974f, 0.411860257387161f, 0.216817945241928f, 0.412077575922012f, + 0.217134088277817f, 0.412294656038284f, 0.217450410127640f, 0.412511497735977f, + 0.217766880989075f, 0.412728071212769f, 0.218083515763283f, 0.412944436073303f, + 0.218400329351425f, 0.413160532712936f, 0.218717306852341f, 0.413376390933990f, + 0.219034433364868f, 0.413592010736465f, 0.219351738691330f, 0.413807392120361f, + 0.219669207930565f, 0.414022535085678f, 0.219986841082573f, 0.414237409830093f, + 0.220304638147354f, 0.414452046155930f, 0.220622614026070f, 0.414666473865509f, + 0.220940738916397f, 0.414880603551865f, 0.221259027719498f, 0.415094524621964f, + 0.221577480435371f, 0.415308207273483f, 0.221896097064018f, 0.415521621704102f, + 0.222214877605438f, 0.415734797716141f, 0.222533836960793f, 0.415947735309601f, + 0.222852945327759f, 0.416160434484482f, 0.223172217607498f, 0.416372895240784f, + 0.223491653800011f, 0.416585087776184f, 0.223811239004135f, 0.416797041893005f, + 0.224131003022194f, 0.417008757591248f, 0.224450930953026f, 0.417220205068588f, + 0.224771007895470f, 0.417431443929672f, 0.225091263651848f, 0.417642414569855f, + 0.225411668419838f, 0.417853146791458f, 0.225732237100601f, 0.418063640594482f, + 0.226052969694138f, 0.418273866176605f, 0.226373866200447f, 0.418483853340149f, + 0.226694911718369f, 0.418693602085114f, 0.227016136050224f, 0.418903112411499f, + 0.227337509393692f, 0.419112354516983f, 0.227659046649933f, 0.419321358203888f, + 0.227980732917786f, 0.419530123472214f, 0.228302597999573f, 0.419738620519638f, + 0.228624612092972f, 0.419946908950806f, 0.228946775197983f, 0.420154929161072f, + 0.229269117116928f, 0.420362681150436f, 0.229591608047485f, 0.420570224523544f, + 0.229914262890816f, 0.420777499675751f, 0.230237081646919f, 0.420984506607056f, + 0.230560049414635f, 0.421191304922104f, 0.230883181095123f, 0.421397835016251f, + 0.231206461787224f, 0.421604126691818f, 0.231529906392097f, 0.421810150146484f, + 0.231853514909744f, 0.422015935182571f, 0.232177272439003f, 0.422221481800079f, + 0.232501193881035f, 0.422426789999008f, 0.232825264334679f, 0.422631829977036f, + 0.233149498701096f, 0.422836631536484f, 0.233473882079124f, 0.423041164875031f, + 0.233798429369926f, 0.423245459794998f, 0.234123140573502f, 0.423449516296387f, + 0.234448000788689f, 0.423653304576874f, 0.234773010015488f, 0.423856884241104f, + 0.235098183155060f, 0.424060165882111f, 0.235423520207405f, 0.424263238906860f, + 0.235749006271362f, 0.424466013908386f, 0.236074641346931f, 0.424668580293655f, + 0.236400425434113f, 0.424870878458023f, 0.236726388335228f, 0.425072938203812f, + 0.237052485346794f, 0.425274729728699f, 0.237378746271133f, 0.425476282835007f, + 0.237705156207085f, 0.425677597522736f, 0.238031730055809f, 0.425878643989563f, + 0.238358452916145f, 0.426079452037811f, 0.238685324788094f, 0.426279991865158f, + 0.239012360572815f, 0.426480293273926f, 0.239339530467987f, 0.426680356264114f, + 0.239666879177094f, 0.426880151033401f, 0.239994361996651f, 0.427079707384110f, + 0.240322008728981f, 0.427278995513916f, 0.240649804472923f, 0.427478045225143f, + 0.240977749228477f, 0.427676826715469f, 0.241305842995644f, 0.427875369787216f, + 0.241634100675583f, 0.428073674440384f, 0.241962507367134f, 0.428271710872650f, + 0.242291063070297f, 0.428469479084015f, 0.242619767785072f, 0.428667008876801f, + 0.242948621511459f, 0.428864300251007f, 0.243277639150620f, 0.429061323404312f, + 0.243606805801392f, 0.429258108139038f, 0.243936106562614f, 0.429454624652863f, + 0.244265571236610f, 0.429650902748108f, 0.244595184922218f, 0.429846942424774f, + 0.244924947619438f, 0.430042684078217f, 0.245254859328270f, 0.430238217115402f, + 0.245584934949875f, 0.430433481931686f, 0.245915144681931f, 0.430628478527069f, + 0.246245503425598f, 0.430823236703873f, 0.246576011180878f, 0.431017726659775f, + 0.246906682848930f, 0.431211978197098f, 0.247237488627434f, 0.431405961513519f, + 0.247568443417549f, 0.431599706411362f, 0.247899547219276f, 0.431793183088303f, + 0.248230814933777f, 0.431986421346664f, 0.248562216758728f, 0.432179391384125f, + 0.248893767595291f, 0.432372123003006f, 0.249225467443466f, 0.432564586400986f, + 0.249557301402092f, 0.432756811380386f, 0.249889299273491f, 0.432948768138886f, + 0.250221431255341f, 0.433140486478806f, 0.250553727149963f, 0.433331936597824f, + 0.250886172056198f, 0.433523118495941f, 0.251218736171722f, 0.433714061975479f, + 0.251551479101181f, 0.433904737234116f, 0.251884341239929f, 0.434095174074173f, + 0.252217382192612f, 0.434285342693329f, 0.252550542354584f, 0.434475272893906f, + 0.252883851528168f, 0.434664934873581f, 0.253217309713364f, 0.434854328632355f, + 0.253550916910172f, 0.435043483972549f, 0.253884643316269f, 0.435232400894165f, + 0.254218548536301f, 0.435421019792557f, 0.254552572965622f, 0.435609430074692f, + 0.254886746406555f, 0.435797542333603f, 0.255221068859100f, 0.435985416173935f, + 0.255555540323257f, 0.436173021793365f, 0.255890160799026f, 0.436360388994217f, + 0.256224930286407f, 0.436547487974167f, 0.256559818983078f, 0.436734348535538f, + 0.256894856691360f, 0.436920911073685f, 0.257230043411255f, 0.437107264995575f, + 0.257565379142761f, 0.437293320894241f, 0.257900834083557f, 0.437479138374329f, + 0.258236467838287f, 0.437664687633514f, 0.258572220802307f, 0.437849998474121f, + 0.258908122777939f, 0.438035041093826f, 0.259244143962860f, 0.438219845294952f, + 0.259580343961716f, 0.438404351472855f, 0.259916663169861f, 0.438588619232178f, + 0.260253131389618f, 0.438772648572922f, 0.260589718818665f, 0.438956409692764f, + 0.260926485061646f, 0.439139902591705f, 0.261263370513916f, 0.439323127269745f, + 0.261600375175476f, 0.439506113529205f, 0.261937558650970f, 0.439688831567764f, + 0.262274861335754f, 0.439871311187744f, 0.262612313032150f, 0.440053492784500f, + 0.262949883937836f, 0.440235435962677f, 0.263287603855133f, 0.440417140722275f, + 0.263625472784042f, 0.440598547458649f, 0.263963490724564f, 0.440779715776443f, + 0.264301627874374f, 0.440960645675659f, 0.264639914035797f, 0.441141277551651f, + 0.264978319406509f, 0.441321671009064f, 0.265316903591156f, 0.441501796245575f, + 0.265655577182770f, 0.441681683063507f, 0.265994429588318f, 0.441861271858215f, + 0.266333401203156f, 0.442040622234344f, 0.266672492027283f, 0.442219734191895f, + 0.267011761665344f, 0.442398548126221f, 0.267351150512695f, 0.442577123641968f, + 0.267690658569336f, 0.442755430936813f, 0.268030315637589f, 0.442933470010757f, + 0.268370121717453f, 0.443111270666122f, 0.268710047006607f, 0.443288803100586f, + 0.269050091505051f, 0.443466067314148f, 0.269390314817429f, 0.443643063306808f, + 0.269730657339096f, 0.443819820880890f, 0.270071119070053f, 0.443996280431747f, + 0.270411729812622f, 0.444172531366348f, 0.270752459764481f, 0.444348484277725f, + 0.271093338727951f, 0.444524168968201f, 0.271434366703033f, 0.444699615240097f, + 0.271775513887405f, 0.444874793291092f, 0.272116780281067f, 0.445049703121185f, + 0.272458195686340f, 0.445224374532700f, 0.272799760103226f, 0.445398747920990f, + 0.273141443729401f, 0.445572882890701f, 0.273483246564865f, 0.445746749639511f, + 0.273825198411942f, 0.445920348167419f, 0.274167299270630f, 0.446093708276749f, + 0.274509519338608f, 0.446266770362854f, 0.274851858615875f, 0.446439594030380f, + 0.275194346904755f, 0.446612149477005f, 0.275536954402924f, 0.446784436702728f, + 0.275879681110382f, 0.446956485509872f, 0.276222556829453f, 0.447128236293793f, + 0.276565581560135f, 0.447299748659134f, 0.276908725500107f, 0.447470992803574f, + 0.277251988649368f, 0.447641968727112f, 0.277595400810242f, 0.447812676429749f, + 0.277938932180405f, 0.447983115911484f, 0.278282582759857f, 0.448153316974640f, + 0.278626382350922f, 0.448323249816895f, 0.278970301151276f, 0.448492884635925f, + 0.279314368963242f, 0.448662281036377f, 0.279658555984497f, 0.448831409215927f, + 0.280002862215042f, 0.449000298976898f, 0.280347317457199f, 0.449168890714645f, + 0.280691891908646f, 0.449337244033813f, 0.281036585569382f, 0.449505299329758f, + 0.281381398439407f, 0.449673116207123f, 0.281726360321045f, 0.449840664863586f, + 0.282071471214294f, 0.450007945299149f, 0.282416671514511f, 0.450174957513809f, + 0.282762020826340f, 0.450341701507568f, 0.283107489347458f, 0.450508207082748f, + 0.283453077077866f, 0.450674414634705f, 0.283798813819885f, 0.450840383768082f, + 0.284144669771194f, 0.451006084680557f, 0.284490644931793f, 0.451171487569809f, + 0.284836769104004f, 0.451336652040482f, 0.285182982683182f, 0.451501548290253f, + 0.285529345273972f, 0.451666176319122f, 0.285875827074051f, 0.451830536127090f, + 0.286222457885742f, 0.451994657516479f, 0.286569178104401f, 0.452158480882645f, + 0.286916047334671f, 0.452322036027908f, 0.287263035774231f, 0.452485352754593f, + 0.287610173225403f, 0.452648371458054f, 0.287957400083542f, 0.452811151742935f, + 0.288304775953293f, 0.452973634004593f, 0.288652241230011f, 0.453135877847672f, + 0.288999855518341f, 0.453297853469849f, 0.289347589015961f, 0.453459560871124f, + 0.289695471525192f, 0.453621000051498f, 0.290043443441391f, 0.453782171010971f, + 0.290391564369202f, 0.453943043947220f, 0.290739774703979f, 0.454103678464890f, + 0.291088134050369f, 0.454264044761658f, 0.291436612606049f, 0.454424172639847f, + 0.291785210371017f, 0.454584002494812f, 0.292133957147598f, 0.454743564128876f, + 0.292482793331146f, 0.454902857542038f, 0.292831748723984f, 0.455061882734299f, + 0.293180853128433f, 0.455220639705658f, 0.293530046939850f, 0.455379128456116f, + 0.293879389762878f, 0.455537378787994f, 0.294228851795197f, 0.455695331096649f, + 0.294578403234482f, 0.455853015184402f, 0.294928103685379f, 0.456010431051254f, + 0.295277923345566f, 0.456167578697205f, 0.295627862215042f, 0.456324487924576f, + 0.295977920293808f, 0.456481099128723f, 0.296328097581863f, 0.456637442111969f, + 0.296678394079208f, 0.456793516874313f, 0.297028809785843f, 0.456949323415756f, + 0.297379344701767f, 0.457104891538620f, 0.297729998826981f, 0.457260161638260f, + 0.298080772161484f, 0.457415163516998f, 0.298431664705276f, 0.457569897174835f, + 0.298782676458359f, 0.457724362611771f, 0.299133807420731f, 0.457878559827805f, + 0.299485057592392f, 0.458032488822937f, 0.299836426973343f, 0.458186149597168f, + 0.300187885761261f, 0.458339542150497f, 0.300539493560791f, 0.458492636680603f, + 0.300891220569611f, 0.458645492792130f, 0.301243066787720f, 0.458798080682755f, + 0.301595002412796f, 0.458950400352478f, 0.301947087049484f, 0.459102421998978f, + 0.302299261093140f, 0.459254205226898f, 0.302651554346085f, 0.459405690431595f, + 0.303003966808319f, 0.459556937217712f, 0.303356528282166f, 0.459707885980606f, + 0.303709149360657f, 0.459858566522598f, 0.304061919450760f, 0.460008978843689f, + 0.304414808750153f, 0.460159152746201f, 0.304767817258835f, 0.460309028625488f, + 0.305120915174484f, 0.460458606481552f, 0.305474132299423f, 0.460607945919037f, + 0.305827468633652f, 0.460757017135620f, 0.306180924177170f, 0.460905820131302f, + 0.306534498929977f, 0.461054325103760f, 0.306888192892075f, 0.461202591657639f, + 0.307241976261139f, 0.461350560188293f, 0.307595878839493f, 0.461498260498047f, + 0.307949900627136f, 0.461645722389221f, 0.308304041624069f, 0.461792886257172f, + 0.308658272027969f, 0.461939752101898f, 0.309012651443481f, 0.462086379528046f, + 0.309367120265961f, 0.462232738733292f, 0.309721708297729f, 0.462378799915314f, + 0.310076385736465f, 0.462524622678757f, 0.310431212186813f, 0.462670147418976f, + 0.310786128044128f, 0.462815403938293f, 0.311141163110733f, 0.462960392236710f, + 0.311496287584305f, 0.463105112314224f, 0.311851561069489f, 0.463249564170837f, + 0.312206923961639f, 0.463393747806549f, 0.312562376260757f, 0.463537633419037f, + 0.312917977571487f, 0.463681250810623f, 0.313273668289185f, 0.463824629783630f, + 0.313629478216171f, 0.463967710733414f, 0.313985377550125f, 0.464110493659973f, + 0.314341396093369f, 0.464253038167953f, 0.314697533845901f, 0.464395314455032f, + 0.315053790807724f, 0.464537292718887f, 0.315410137176514f, 0.464679002761841f, + 0.315766572952271f, 0.464820444583893f, 0.316123157739639f, 0.464961618185043f, + 0.316479831933975f, 0.465102523565292f, 0.316836595535278f, 0.465243130922318f, + 0.317193508148193f, 0.465383470058441f, 0.317550510168076f, 0.465523540973663f, + 0.317907601594925f, 0.465663343667984f, 0.318264812231064f, 0.465802878141403f, + 0.318622142076492f, 0.465942144393921f, 0.318979561328888f, 0.466081112623215f, + 0.319337099790573f, 0.466219812631607f, 0.319694727659225f, 0.466358244419098f, + 0.320052474737167f, 0.466496407985687f, 0.320410341024399f, 0.466634273529053f, + 0.320768296718597f, 0.466771900653839f, 0.321126341819763f, 0.466909229755402f, + 0.321484506130219f, 0.467046260833740f, 0.321842789649963f, 0.467183053493500f, + 0.322201162576675f, 0.467319577932358f, 0.322559654712677f, 0.467455804347992f, + 0.322918236255646f, 0.467591762542725f, 0.323276937007904f, 0.467727422714233f, + 0.323635727167130f, 0.467862844467163f, 0.323994606733322f, 0.467997968196869f, + 0.324353635311127f, 0.468132823705673f, 0.324712723493576f, 0.468267410993576f, + 0.325071930885315f, 0.468401730060577f, 0.325431257486343f, 0.468535751104355f, + 0.325790673494339f, 0.468669503927231f, 0.326150178909302f, 0.468802988529205f, + 0.326509803533554f, 0.468936175107956f, 0.326869517564774f, 0.469069123268127f, + 0.327229350805283f, 0.469201773405075f, 0.327589273452759f, 0.469334155321121f, + 0.327949285507202f, 0.469466239213943f, 0.328309416770935f, 0.469598054885864f, + 0.328669637441635f, 0.469729602336884f, 0.329029977321625f, 0.469860881567001f, + 0.329390406608582f, 0.469991862773895f, 0.329750925302505f, 0.470122605562210f, + 0.330111563205719f, 0.470253020524979f, 0.330472290515900f, 0.470383197069168f, + 0.330833107233047f, 0.470513075590134f, 0.331194043159485f, 0.470642685890198f, + 0.331555068492889f, 0.470772027969360f, 0.331916213035584f, 0.470901101827621f, + 0.332277417182922f, 0.471029877662659f, 0.332638740539551f, 0.471158385276794f, + 0.333000183105469f, 0.471286594867706f, 0.333361685276031f, 0.471414536237717f, + 0.333723306655884f, 0.471542209386826f, 0.334085017442703f, 0.471669614315033f, + 0.334446847438812f, 0.471796721220016f, 0.334808766841888f, 0.471923559904099f, + 0.335170775651932f, 0.472050130367279f, 0.335532873868942f, 0.472176402807236f, + 0.335895091295242f, 0.472302407026291f, 0.336257368326187f, 0.472428143024445f, + 0.336619764566422f, 0.472553610801697f, 0.336982280015945f, 0.472678780555725f, + 0.337344855070114f, 0.472803652286530f, 0.337707549333572f, 0.472928285598755f, + 0.338070303201675f, 0.473052620887756f, 0.338433176279068f, 0.473176687955856f, + 0.338796168565750f, 0.473300457000732f, 0.339159220457077f, 0.473423957824707f, + 0.339522391557693f, 0.473547190427780f, 0.339885622262955f, 0.473670125007629f, + 0.340248972177505f, 0.473792791366577f, 0.340612411499023f, 0.473915189504623f, + 0.340975970029831f, 0.474037289619446f, 0.341339588165283f, 0.474159121513367f, + 0.341703325510025f, 0.474280685186386f, 0.342067122459412f, 0.474401950836182f, + 0.342431038618088f, 0.474522948265076f, 0.342795044183731f, 0.474643647670746f, + 0.343159139156342f, 0.474764078855515f, 0.343523323535919f, 0.474884241819382f, + 0.343887597322464f, 0.475004136562347f, 0.344251960515976f, 0.475123733282089f, + 0.344616413116455f, 0.475243031978607f, 0.344980984926224f, 0.475362062454224f, + 0.345345616340637f, 0.475480824708939f, 0.345710366964340f, 0.475599318742752f, + 0.346075177192688f, 0.475717514753342f, 0.346440106630325f, 0.475835442543030f, + 0.346805095672607f, 0.475953072309494f, 0.347170203924179f, 0.476070433855057f, + 0.347535371780396f, 0.476187497377396f, 0.347900658845901f, 0.476304292678833f, + 0.348266035318375f, 0.476420819759369f, 0.348631471395493f, 0.476537048816681f, + 0.348997026681900f, 0.476653009653091f, 0.349362671375275f, 0.476768702268600f, + 0.349728375673294f, 0.476884096860886f, 0.350094199180603f, 0.476999223232269f, + 0.350460082292557f, 0.477114051580429f, 0.350826084613800f, 0.477228611707687f, + 0.351192146539688f, 0.477342873811722f, 0.351558297872543f, 0.477456867694855f, + 0.351924568414688f, 0.477570593357086f, 0.352290898561478f, 0.477684020996094f, + 0.352657318115234f, 0.477797180414200f, 0.353023827075958f, 0.477910041809082f, + 0.353390425443649f, 0.478022634983063f, 0.353757113218308f, 0.478134930133820f, + 0.354123860597610f, 0.478246957063675f, 0.354490727186203f, 0.478358715772629f, + 0.354857653379440f, 0.478470176458359f, 0.355224698781967f, 0.478581339120865f, + 0.355591803789139f, 0.478692263364792f, 0.355958998203278f, 0.478802859783173f, + 0.356326282024384f, 0.478913217782974f, 0.356693625450134f, 0.479023247957230f, + 0.357061088085175f, 0.479133039712906f, 0.357428610324860f, 0.479242533445358f, + 0.357796221971512f, 0.479351729154587f, 0.358163923025131f, 0.479460656642914f, + 0.358531713485718f, 0.479569315910339f, 0.358899593353271f, 0.479677677154541f, + 0.359267532825470f, 0.479785770177841f, 0.359635561704636f, 0.479893565177917f, + 0.360003679990768f, 0.480001062154770f, 0.360371887683868f, 0.480108320713043f, + 0.360740154981613f, 0.480215251445770f, 0.361108511686325f, 0.480321943759918f, + 0.361476957798004f, 0.480428308248520f, 0.361845493316650f, 0.480534434318542f, + 0.362214088439941f, 0.480640232563019f, 0.362582772970200f, 0.480745792388916f, + 0.362951546907425f, 0.480851024389267f, 0.363320380449295f, 0.480956017971039f, + 0.363689333200455f, 0.481060713529587f, 0.364058345556259f, 0.481165111064911f, + 0.364427417516708f, 0.481269240379334f, 0.364796578884125f, 0.481373071670532f, + 0.365165829658508f, 0.481476634740829f, 0.365535169839859f, 0.481579899787903f, + 0.365904569625854f, 0.481682896614075f, 0.366274058818817f, 0.481785595417023f, + 0.366643607616425f, 0.481888025999069f, 0.367013275623322f, 0.481990188360214f, + 0.367382973432541f, 0.482092022895813f, 0.367752790451050f, 0.482193619012833f, + 0.368122667074203f, 0.482294887304306f, 0.368492603302002f, 0.482395917177200f, + 0.368862658739090f, 0.482496619224548f, 0.369232743978500f, 0.482597053050995f, + 0.369602948427200f, 0.482697218656540f, 0.369973212480545f, 0.482797086238861f, + 0.370343536138535f, 0.482896685600281f, 0.370713949203491f, 0.482995986938477f, + 0.371084451675415f, 0.483094990253448f, 0.371455013751984f, 0.483193725347519f, + 0.371825665235519f, 0.483292192220688f, 0.372196376323700f, 0.483390361070633f, + 0.372567176818848f, 0.483488231897354f, 0.372938036918640f, 0.483585834503174f, + 0.373308986425400f, 0.483683139085770f, 0.373679995536804f, 0.483780175447464f, + 0.374051094055176f, 0.483876913785934f, 0.374422252178192f, 0.483973383903503f, + 0.374793499708176f, 0.484069555997849f, 0.375164806842804f, 0.484165430068970f, + 0.375536203384399f, 0.484261035919189f, 0.375907659530640f, 0.484356373548508f, + 0.376279205083847f, 0.484451413154602f, 0.376650810241699f, 0.484546154737473f, + 0.377022475004196f, 0.484640628099442f, 0.377394229173660f, 0.484734803438187f, + 0.377766042947769f, 0.484828680753708f, 0.378137946128845f, 0.484922289848328f, + 0.378509908914566f, 0.485015630722046f, 0.378881961107254f, 0.485108673572540f, + 0.379254043102264f, 0.485201418399811f, 0.379626244306564f, 0.485293895006180f, + 0.379998475313187f, 0.485386073589325f, 0.380370795726776f, 0.485477954149246f, + 0.380743205547333f, 0.485569566488266f, 0.381115674972534f, 0.485660910606384f, + 0.381488204002380f, 0.485751956701279f, 0.381860792636871f, 0.485842704772949f, + 0.382233470678329f, 0.485933154821396f, 0.382606208324432f, 0.486023366451263f, + 0.382979035377502f, 0.486113250255585f, 0.383351892232895f, 0.486202865839005f, + 0.383724838495255f, 0.486292183399200f, 0.384097874164581f, 0.486381232738495f, + 0.384470939636230f, 0.486469984054565f, 0.384844094514847f, 0.486558437347412f, + 0.385217308998108f, 0.486646622419357f, 0.385590612888336f, 0.486734509468079f, + 0.385963946580887f, 0.486822128295898f, 0.386337369680405f, 0.486909449100494f, + 0.386710882186890f, 0.486996471881866f, 0.387084424495697f, 0.487083226442337f, + 0.387458056211472f, 0.487169682979584f, 0.387831717729568f, 0.487255871295929f, + 0.388205498456955f, 0.487341761589050f, 0.388579308986664f, 0.487427353858948f, + 0.388953179121017f, 0.487512677907944f, 0.389327138662338f, 0.487597703933716f, + 0.389701157808304f, 0.487682431936264f, 0.390075236558914f, 0.487766891717911f, + 0.390449374914169f, 0.487851053476334f, 0.390823602676392f, 0.487934947013855f, + 0.391197860240936f, 0.488018542528152f, 0.391572207212448f, 0.488101840019226f, + 0.391946613788605f, 0.488184869289398f, 0.392321079969406f, 0.488267600536346f, + 0.392695605754852f, 0.488350033760071f, 0.393070191144943f, 0.488432198762894f, + 0.393444836139679f, 0.488514065742493f, 0.393819570541382f, 0.488595664501190f, + 0.394194334745407f, 0.488676935434341f, 0.394569188356400f, 0.488757967948914f, + 0.394944071769714f, 0.488838672637939f, 0.395319044589996f, 0.488919109106064f, + 0.395694077014923f, 0.488999247550964f, 0.396069169044495f, 0.489079117774963f, + 0.396444320678711f, 0.489158689975739f, 0.396819531917572f, 0.489237964153290f, + 0.397194802761078f, 0.489316970109940f, 0.397570133209229f, 0.489395678043365f, + 0.397945523262024f, 0.489474087953568f, 0.398320972919464f, 0.489552229642868f, + 0.398696482181549f, 0.489630073308945f, 0.399072051048279f, 0.489707618951797f, + 0.399447679519653f, 0.489784896373749f, 0.399823367595673f, 0.489861875772476f, + 0.400199115276337f, 0.489938557147980f, 0.400574922561646f, 0.490014940500259f, + 0.400950789451599f, 0.490091055631638f, 0.401326715946198f, 0.490166902542114f, + 0.401702702045441f, 0.490242421627045f, 0.402078747749329f, 0.490317672491074f, + 0.402454853057861f, 0.490392625331879f, 0.402830988168716f, 0.490467309951782f, + 0.403207212686539f, 0.490541696548462f, 0.403583467006683f, 0.490615785121918f, + 0.403959810733795f, 0.490689605474472f, 0.404336184263229f, 0.490763127803802f, + 0.404712617397308f, 0.490836352109909f, 0.405089110136032f, 0.490909278392792f, + 0.405465662479401f, 0.490981936454773f, 0.405842274427414f, 0.491054296493530f, + 0.406218945980072f, 0.491126358509064f, 0.406595647335052f, 0.491198152303696f, + 0.406972438097000f, 0.491269648075104f, 0.407349258661270f, 0.491340845823288f, + 0.407726138830185f, 0.491411775350571f, 0.408103078603745f, 0.491482406854630f, + 0.408480048179626f, 0.491552740335464f, 0.408857107162476f, 0.491622805595398f, + 0.409234195947647f, 0.491692543029785f, 0.409611344337463f, 0.491762012243271f, + 0.409988552331924f, 0.491831213235855f, 0.410365819931030f, 0.491900116205215f, + 0.410743117332459f, 0.491968721151352f, 0.411120474338531f, 0.492037028074265f, + 0.411497890949249f, 0.492105036973953f, 0.411875367164612f, 0.492172777652740f, + 0.412252873182297f, 0.492240220308304f, 0.412630438804626f, 0.492307394742966f, + 0.413008064031601f, 0.492374241352081f, 0.413385748863220f, 0.492440819740295f, + 0.413763463497162f, 0.492507129907608f, 0.414141237735748f, 0.492573112249374f, + 0.414519041776657f, 0.492638826370239f, 0.414896935224533f, 0.492704242467880f, + 0.415274858474731f, 0.492769360542297f, 0.415652841329575f, 0.492834210395813f, + 0.416030853986740f, 0.492898762226105f, 0.416408926248550f, 0.492963016033173f, + 0.416787058115005f, 0.493026971817017f, 0.417165219783783f, 0.493090659379959f, + 0.417543441057205f, 0.493154048919678f, 0.417921721935272f, 0.493217140436172f, + 0.418300032615662f, 0.493279963731766f, 0.418678402900696f, 0.493342459201813f, + 0.419056802988052f, 0.493404686450958f, 0.419435262680054f, 0.493466645479202f, + 0.419813781976700f, 0.493528276681900f, 0.420192331075668f, 0.493589639663696f, + 0.420570939779282f, 0.493650704622269f, 0.420949578285217f, 0.493711471557617f, + 0.421328276395798f, 0.493771970272064f, 0.421707004308701f, 0.493832170963287f, + 0.422085791826248f, 0.493892073631287f, 0.422464638948441f, 0.493951678276062f, + 0.422843515872955f, 0.494011014699936f, 0.423222452402115f, 0.494070053100586f, + 0.423601418733597f, 0.494128793478012f, 0.423980414867401f, 0.494187235832214f, + 0.424359470605850f, 0.494245409965515f, 0.424738585948944f, 0.494303256273270f, + 0.425117731094360f, 0.494360834360123f, 0.425496935844421f, 0.494418144226074f, + 0.425876170396805f, 0.494475126266479f, 0.426255434751511f, 0.494531840085983f, + 0.426634758710861f, 0.494588255882263f, 0.427014142274857f, 0.494644373655319f, + 0.427393525838852f, 0.494700223207474f, 0.427772998809814f, 0.494755744934082f, + 0.428152471780777f, 0.494810998439789f, 0.428532034158707f, 0.494865983724594f, + 0.428911596536636f, 0.494920641183853f, 0.429291218519211f, 0.494975030422211f, + 0.429670870304108f, 0.495029091835022f, 0.430050581693649f, 0.495082914829254f, + 0.430430322885513f, 0.495136409997940f, 0.430810123682022f, 0.495189607143402f, + 0.431189924478531f, 0.495242536067963f, 0.431569814682007f, 0.495295166969299f, + 0.431949704885483f, 0.495347499847412f, 0.432329654693604f, 0.495399564504623f, + 0.432709634304047f, 0.495451331138611f, 0.433089673519135f, 0.495502769947052f, + 0.433469742536545f, 0.495553970336914f, 0.433849841356277f, 0.495604842901230f, + 0.434229999780655f, 0.495655417442322f, 0.434610158205032f, 0.495705723762512f, + 0.434990376234055f, 0.495755732059479f, 0.435370653867722f, 0.495805442333221f, + 0.435750931501389f, 0.495854884386063f, 0.436131268739700f, 0.495903998613358f, + 0.436511665582657f, 0.495952844619751f, 0.436892062425613f, 0.496001392602921f, + 0.437272518873215f, 0.496049642562866f, 0.437653005123138f, 0.496097624301910f, + 0.438033521175385f, 0.496145308017731f, 0.438414067029953f, 0.496192663908005f, + 0.438794672489166f, 0.496239781379700f, 0.439175277948380f, 0.496286571025848f, + 0.439555943012238f, 0.496333062648773f, 0.439936667680740f, 0.496379286050797f, + 0.440317392349243f, 0.496425211429596f, 0.440698176622391f, 0.496470838785172f, + 0.441078960895538f, 0.496516168117523f, 0.441459804773331f, 0.496561229228973f, + 0.441840678453445f, 0.496605962514877f, 0.442221581935883f, 0.496650427579880f, + 0.442602545022964f, 0.496694594621658f, 0.442983508110046f, 0.496738493442535f, + 0.443364530801773f, 0.496782064437866f, 0.443745553493500f, 0.496825367212296f, + 0.444126635789871f, 0.496868371963501f, 0.444507747888565f, 0.496911078691483f, + 0.444888889789581f, 0.496953487396240f, 0.445270061492920f, 0.496995598077774f, + 0.445651292800903f, 0.497037440538406f, 0.446032524108887f, 0.497078984975815f, + 0.446413785219193f, 0.497120231389999f, 0.446795076131821f, 0.497161179780960f, + 0.447176426649094f, 0.497201830148697f, 0.447557777166367f, 0.497242212295532f, + 0.447939187288284f, 0.497282296419144f, 0.448320597410202f, 0.497322082519531f, + 0.448702067136765f, 0.497361570596695f, 0.449083566665649f, 0.497400760650635f, + 0.449465066194534f, 0.497439652681351f, 0.449846625328064f, 0.497478276491165f, + 0.450228184461594f, 0.497516602277756f, 0.450609803199768f, 0.497554630041122f, + 0.450991421937943f, 0.497592359781265f, 0.451373100280762f, 0.497629791498184f, + 0.451754778623581f, 0.497666954994202f, 0.452136516571045f, 0.497703820466995f, + 0.452518254518509f, 0.497740387916565f, 0.452900022268295f, 0.497776657342911f, + 0.453281819820404f, 0.497812628746033f, 0.453663676977158f, 0.497848302125931f, + 0.454045534133911f, 0.497883707284927f, 0.454427421092987f, 0.497918814420700f, + 0.454809308052063f, 0.497953623533249f, 0.455191254615784f, 0.497988134622574f, + 0.455573230981827f, 0.498022347688675f, 0.455955207347870f, 0.498056292533875f, + 0.456337243318558f, 0.498089909553528f, 0.456719279289246f, 0.498123258352280f, + 0.457101345062256f, 0.498156309127808f, 0.457483440637589f, 0.498189061880112f, + 0.457865566015244f, 0.498221516609192f, 0.458247691392899f, 0.498253703117371f, + 0.458629876375198f, 0.498285561800003f, 0.459012061357498f, 0.498317152261734f, + 0.459394276142120f, 0.498348444700241f, 0.459776520729065f, 0.498379439115524f, + 0.460158795118332f, 0.498410135507584f, 0.460541069507599f, 0.498440563678741f, + 0.460923373699188f, 0.498470664024353f, 0.461305707693100f, 0.498500496149063f, + 0.461688071489334f, 0.498530030250549f, 0.462070435285568f, 0.498559266328812f, + 0.462452858686447f, 0.498588204383850f, 0.462835282087326f, 0.498616874217987f, + 0.463217705488205f, 0.498645216226578f, 0.463600188493729f, 0.498673290014267f, + 0.463982671499252f, 0.498701065778732f, 0.464365184307098f, 0.498728543519974f, + 0.464747726917267f, 0.498755723237991f, 0.465130269527435f, 0.498782604932785f, + 0.465512841939926f, 0.498809218406677f, 0.465895414352417f, 0.498835533857346f, + 0.466278046369553f, 0.498861521482468f, 0.466660678386688f, 0.498887240886688f, + 0.467043310403824f, 0.498912662267685f, 0.467426002025604f, 0.498937815427780f, + 0.467808693647385f, 0.498962640762329f, 0.468191385269165f, 0.498987197875977f, + 0.468574106693268f, 0.499011427164078f, 0.468956857919693f, 0.499035388231277f, + 0.469339638948441f, 0.499059051275253f, 0.469722419977188f, 0.499082416296005f, + 0.470105201005936f, 0.499105513095856f, 0.470488041639328f, 0.499128282070160f, + 0.470870882272720f, 0.499150782823563f, 0.471253722906113f, 0.499172955751419f, + 0.471636593341827f, 0.499194860458374f, 0.472019463777542f, 0.499216467142105f, + 0.472402364015579f, 0.499237775802612f, 0.472785294055939f, 0.499258816242218f, + 0.473168224096298f, 0.499279528856277f, 0.473551183938980f, 0.499299973249435f, + 0.473934143781662f, 0.499320119619370f, 0.474317133426666f, 0.499339967966080f, + 0.474700123071671f, 0.499359518289566f, 0.475083142518997f, 0.499378770589828f, + 0.475466161966324f, 0.499397724866867f, 0.475849211215973f, 0.499416410923004f, + 0.476232260465622f, 0.499434769153595f, 0.476615339517593f, 0.499452859163284f, + 0.476998418569565f, 0.499470651149750f, 0.477381497621536f, 0.499488145112991f, + 0.477764606475830f, 0.499505341053009f, 0.478147745132446f, 0.499522238969803f, + 0.478530883789063f, 0.499538868665695f, 0.478914022445679f, 0.499555170536041f, + 0.479297190904617f, 0.499571204185486f, 0.479680359363556f, 0.499586939811707f, + 0.480063527822495f, 0.499602377414703f, 0.480446726083755f, 0.499617516994476f, + 0.480829954147339f, 0.499632388353348f, 0.481213152408600f, 0.499646931886673f, + 0.481596380472183f, 0.499661177396774f, 0.481979638338089f, 0.499675154685974f, + 0.482362866401672f, 0.499688833951950f, 0.482746154069901f, 0.499702215194702f, + 0.483129411935806f, 0.499715298414230f, 0.483512699604034f, 0.499728083610535f, + 0.483895987272263f, 0.499740600585938f, 0.484279274940491f, 0.499752789735794f, + 0.484662592411041f, 0.499764710664749f, 0.485045909881592f, 0.499776333570480f, + 0.485429257154465f, 0.499787658452988f, 0.485812574625015f, 0.499798685312271f, + 0.486195921897888f, 0.499809414148331f, 0.486579269170761f, 0.499819844961166f, + 0.486962646245956f, 0.499830007553101f, 0.487346023321152f, 0.499839842319489f, + 0.487729400396347f, 0.499849408864975f, 0.488112777471542f, 0.499858677387238f, + 0.488496154546738f, 0.499867647886276f, 0.488879561424255f, 0.499876320362091f, + 0.489262968301773f, 0.499884694814682f, 0.489646375179291f, 0.499892801046371f, + 0.490029782056808f, 0.499900579452515f, 0.490413218736649f, 0.499908089637756f, + 0.490796625614166f, 0.499915301799774f, 0.491180062294006f, 0.499922215938568f, + 0.491563498973846f, 0.499928832054138f, 0.491946935653687f, 0.499935150146484f, + 0.492330402135849f, 0.499941170215607f, 0.492713838815689f, 0.499946922063828f, + 0.493097305297852f, 0.499952346086502f, 0.493480771780014f, 0.499957501888275f, + 0.493864238262177f, 0.499962359666824f, 0.494247704744339f, 0.499966919422150f, + 0.494631171226501f, 0.499971181154251f, 0.495014637708664f, 0.499975144863129f, + 0.495398133993149f, 0.499978810548782f, 0.495781600475311f, 0.499982208013535f, + 0.496165096759796f, 0.499985307455063f, 0.496548563241959f, 0.499988079071045f, + 0.496932059526443f, 0.499990582466125f, 0.497315555810928f, 0.499992787837982f, + 0.497699022293091f, 0.499994695186615f, 0.498082518577576f, 0.499996334314346f, + 0.498466014862061f, 0.499997645616531f, 0.498849511146545f, 0.499998688697815f, + 0.499233007431030f, 0.499999403953552f, 0.499616503715515f, 0.499999850988388f, +}; + + +/** + @par + Generation of realCoefB array: + @par + n = 4096 +
for (i = 0; i < n; i++)
+  {
+     pBTable[2 * i]     = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+     pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ */ + +const float32_t realCoefB[8192] = { + 0.500000000000000f, 0.500000000000000f, 0.500383496284485f, 0.499999850988388f, + 0.500766992568970f, 0.499999403953552f, 0.501150488853455f, 0.499998688697815f, + 0.501533985137939f, 0.499997645616531f, 0.501917481422424f, 0.499996334314346f, + 0.502300977706909f, 0.499994695186615f, 0.502684473991394f, 0.499992787837982f, + 0.503067970275879f, 0.499990582466125f, 0.503451406955719f, 0.499988079071045f, + 0.503834903240204f, 0.499985307455063f, 0.504218399524689f, 0.499982208013535f, + 0.504601895809174f, 0.499978810548782f, 0.504985332489014f, 0.499975144863129f, + 0.505368828773499f, 0.499971181154251f, 0.505752325057983f, 0.499966919422150f, + 0.506135761737823f, 0.499962359666824f, 0.506519258022308f, 0.499957501888275f, + 0.506902694702148f, 0.499952346086502f, 0.507286131381989f, 0.499946922063828f, + 0.507669627666473f, 0.499941170215607f, 0.508053064346313f, 0.499935150146484f, + 0.508436501026154f, 0.499928832054138f, 0.508819937705994f, 0.499922215938568f, + 0.509203374385834f, 0.499915301799774f, 0.509586811065674f, 0.499908089637756f, + 0.509970188140869f, 0.499900579452515f, 0.510353624820709f, 0.499892801046371f, + 0.510737061500549f, 0.499884694814682f, 0.511120438575745f, 0.499876320362091f, + 0.511503815650940f, 0.499867647886276f, 0.511887252330780f, 0.499858677387238f, + 0.512270629405975f, 0.499849408864975f, 0.512654006481171f, 0.499839842319489f, + 0.513037383556366f, 0.499830007553101f, 0.513420701026917f, 0.499819844961166f, + 0.513804078102112f, 0.499809414148331f, 0.514187395572662f, 0.499798685312271f, + 0.514570772647858f, 0.499787658452988f, 0.514954090118408f, 0.499776333570480f, + 0.515337407588959f, 0.499764710664749f, 0.515720725059509f, 0.499752789735794f, + 0.516103982925415f, 0.499740600585938f, 0.516487300395966f, 0.499728083610535f, + 0.516870558261871f, 0.499715298414230f, 0.517253875732422f, 0.499702215194702f, + 0.517637133598328f, 0.499688833951950f, 0.518020391464233f, 0.499675154685974f, + 0.518403589725494f, 0.499661177396774f, 0.518786847591400f, 0.499646931886673f, + 0.519170045852661f, 0.499632388353348f, 0.519553244113922f, 0.499617516994476f, + 0.519936442375183f, 0.499602377414703f, 0.520319640636444f, 0.499586939811707f, + 0.520702838897705f, 0.499571204185486f, 0.521085977554321f, 0.499555170536041f, + 0.521469116210938f, 0.499538868665695f, 0.521852254867554f, 0.499522238969803f, + 0.522235393524170f, 0.499505341053009f, 0.522618472576141f, 0.499488145112991f, + 0.523001611232758f, 0.499470651149750f, 0.523384690284729f, 0.499452859163284f, + 0.523767769336700f, 0.499434769153595f, 0.524150788784027f, 0.499416410923004f, + 0.524533808231354f, 0.499397724866867f, 0.524916887283325f, 0.499378770589828f, + 0.525299847126007f, 0.499359518289566f, 0.525682866573334f, 0.499339967966080f, + 0.526065826416016f, 0.499320119619370f, 0.526448845863342f, 0.499299973249435f, + 0.526831746101379f, 0.499279528856277f, 0.527214705944061f, 0.499258816242218f, + 0.527597606182098f, 0.499237775802612f, 0.527980506420136f, 0.499216467142105f, + 0.528363406658173f, 0.499194860458374f, 0.528746306896210f, 0.499172955751419f, + 0.529129147529602f, 0.499150782823563f, 0.529511988162994f, 0.499128282070160f, + 0.529894769191742f, 0.499105513095856f, 0.530277609825134f, 0.499082416296005f, + 0.530660390853882f, 0.499059051275253f, 0.531043112277985f, 0.499035388231277f, + 0.531425893306732f, 0.499011427164078f, 0.531808614730835f, 0.498987197875977f, + 0.532191336154938f, 0.498962640762329f, 0.532573997974396f, 0.498937815427780f, + 0.532956659793854f, 0.498912662267685f, 0.533339321613312f, 0.498887240886688f, + 0.533721983432770f, 0.498861521482468f, 0.534104585647583f, 0.498835533857346f, + 0.534487187862396f, 0.498809218406677f, 0.534869730472565f, 0.498782604932785f, + 0.535252273082733f, 0.498755723237991f, 0.535634815692902f, 0.498728543519974f, + 0.536017298698425f, 0.498701065778732f, 0.536399841308594f, 0.498673290014267f, + 0.536782264709473f, 0.498645216226578f, 0.537164747714996f, 0.498616874217987f, + 0.537547171115875f, 0.498588204383850f, 0.537929534912109f, 0.498559266328812f, + 0.538311958312988f, 0.498530030250549f, 0.538694262504578f, 0.498500496149063f, + 0.539076626300812f, 0.498470664024353f, 0.539458930492401f, 0.498440563678741f, + 0.539841234683990f, 0.498410135507584f, 0.540223479270935f, 0.498379439115524f, + 0.540605723857880f, 0.498348444700241f, 0.540987968444824f, 0.498317152261734f, + 0.541370153427124f, 0.498285561800003f, 0.541752278804779f, 0.498253703117371f, + 0.542134463787079f, 0.498221516609192f, 0.542516589164734f, 0.498189061880112f, + 0.542898654937744f, 0.498156309127808f, 0.543280720710754f, 0.498123258352280f, + 0.543662786483765f, 0.498089909553528f, 0.544044792652130f, 0.498056292533875f, + 0.544426798820496f, 0.498022347688675f, 0.544808745384216f, 0.497988134622574f, + 0.545190691947937f, 0.497953623533249f, 0.545572578907013f, 0.497918814420700f, + 0.545954465866089f, 0.497883707284927f, 0.546336352825165f, 0.497848302125931f, + 0.546718180179596f, 0.497812628746033f, 0.547099947929382f, 0.497776657342911f, + 0.547481775283813f, 0.497740387916565f, 0.547863483428955f, 0.497703820466995f, + 0.548245191574097f, 0.497666954994202f, 0.548626899719238f, 0.497629791498184f, + 0.549008548259735f, 0.497592359781265f, 0.549390196800232f, 0.497554630041122f, + 0.549771785736084f, 0.497516602277756f, 0.550153374671936f, 0.497478276491165f, + 0.550534904003143f, 0.497439652681351f, 0.550916433334351f, 0.497400760650635f, + 0.551297962665558f, 0.497361570596695f, 0.551679372787476f, 0.497322082519531f, + 0.552060842514038f, 0.497282296419144f, 0.552442193031311f, 0.497242212295532f, + 0.552823603153229f, 0.497201830148697f, 0.553204894065857f, 0.497161179780960f, + 0.553586184978485f, 0.497120231389999f, 0.553967475891113f, 0.497078984975815f, + 0.554348707199097f, 0.497037440538406f, 0.554729938507080f, 0.496995598077774f, + 0.555111110210419f, 0.496953487396240f, 0.555492222309113f, 0.496911078691483f, + 0.555873334407806f, 0.496868371963501f, 0.556254446506500f, 0.496825367212296f, + 0.556635499000549f, 0.496782064437866f, 0.557016491889954f, 0.496738493442535f, + 0.557397484779358f, 0.496694594621658f, 0.557778418064117f, 0.496650427579880f, + 0.558159291744232f, 0.496605962514877f, 0.558540165424347f, 0.496561229228973f, + 0.558921039104462f, 0.496516168117523f, 0.559301853179932f, 0.496470838785172f, + 0.559682607650757f, 0.496425211429596f, 0.560063362121582f, 0.496379286050797f, + 0.560444056987762f, 0.496333062648773f, 0.560824692249298f, 0.496286571025848f, + 0.561205327510834f, 0.496239781379700f, 0.561585903167725f, 0.496192663908005f, + 0.561966478824615f, 0.496145308017731f, 0.562346994876862f, 0.496097624301910f, + 0.562727510929108f, 0.496049642562866f, 0.563107967376709f, 0.496001392602921f, + 0.563488364219666f, 0.495952844619751f, 0.563868701457977f, 0.495903998613358f, + 0.564249038696289f, 0.495854884386063f, 0.564629375934601f, 0.495805442333221f, + 0.565009593963623f, 0.495755732059479f, 0.565389811992645f, 0.495705723762512f, + 0.565770030021667f, 0.495655417442322f, 0.566150128841400f, 0.495604842901230f, + 0.566530287265778f, 0.495553970336914f, 0.566910326480865f, 0.495502769947052f, + 0.567290365695953f, 0.495451331138611f, 0.567670345306396f, 0.495399564504623f, + 0.568050265312195f, 0.495347499847412f, 0.568430185317993f, 0.495295166969299f, + 0.568810045719147f, 0.495242536067963f, 0.569189906120300f, 0.495189607143402f, + 0.569569647312164f, 0.495136409997940f, 0.569949388504028f, 0.495082914829254f, + 0.570329129695892f, 0.495029091835022f, 0.570708811283112f, 0.494975030422211f, + 0.571088373661041f, 0.494920641183853f, 0.571467995643616f, 0.494865983724594f, + 0.571847498416901f, 0.494810998439789f, 0.572227001190186f, 0.494755744934082f, + 0.572606444358826f, 0.494700223207474f, 0.572985887527466f, 0.494644373655319f, + 0.573365211486816f, 0.494588255882263f, 0.573744535446167f, 0.494531840085983f, + 0.574123859405518f, 0.494475126266479f, 0.574503064155579f, 0.494418144226074f, + 0.574882268905640f, 0.494360834360123f, 0.575261414051056f, 0.494303256273270f, + 0.575640499591827f, 0.494245409965515f, 0.576019585132599f, 0.494187235832214f, + 0.576398611068726f, 0.494128793478012f, 0.576777577400208f, 0.494070053100586f, + 0.577156484127045f, 0.494011014699936f, 0.577535390853882f, 0.493951678276062f, + 0.577914178371429f, 0.493892073631287f, 0.578292965888977f, 0.493832170963287f, + 0.578671753406525f, 0.493771970272064f, 0.579050421714783f, 0.493711471557617f, + 0.579429090023041f, 0.493650704622269f, 0.579807698726654f, 0.493589639663696f, + 0.580186247825623f, 0.493528276681900f, 0.580564737319946f, 0.493466645479202f, + 0.580943167209625f, 0.493404686450958f, 0.581321597099304f, 0.493342459201813f, + 0.581699967384338f, 0.493279963731766f, 0.582078278064728f, 0.493217140436172f, + 0.582456588745117f, 0.493154048919678f, 0.582834780216217f, 0.493090659379959f, + 0.583212971687317f, 0.493026971817017f, 0.583591103553772f, 0.492963016033173f, + 0.583969175815582f, 0.492898762226105f, 0.584347188472748f, 0.492834210395813f, + 0.584725141525269f, 0.492769360542297f, 0.585103094577789f, 0.492704242467880f, + 0.585480928421021f, 0.492638826370239f, 0.585858762264252f, 0.492573112249374f, + 0.586236536502838f, 0.492507129907608f, 0.586614251136780f, 0.492440819740295f, + 0.586991965770721f, 0.492374241352081f, 0.587369561195374f, 0.492307394742966f, + 0.587747097015381f, 0.492240220308304f, 0.588124632835388f, 0.492172777652740f, + 0.588502109050751f, 0.492105036973953f, 0.588879525661469f, 0.492037028074265f, + 0.589256882667542f, 0.491968721151352f, 0.589634180068970f, 0.491900116205215f, + 0.590011477470398f, 0.491831213235855f, 0.590388655662537f, 0.491762012243271f, + 0.590765833854675f, 0.491692543029785f, 0.591142892837524f, 0.491622805595398f, + 0.591519951820374f, 0.491552740335464f, 0.591896951198578f, 0.491482406854630f, + 0.592273890972137f, 0.491411775350571f, 0.592650771141052f, 0.491340845823288f, + 0.593027591705322f, 0.491269648075104f, 0.593404352664948f, 0.491198152303696f, + 0.593781054019928f, 0.491126358509064f, 0.594157755374908f, 0.491054296493530f, + 0.594534337520599f, 0.490981936454773f, 0.594910860061646f, 0.490909278392792f, + 0.595287382602692f, 0.490836352109909f, 0.595663845539093f, 0.490763127803802f, + 0.596040189266205f, 0.490689605474472f, 0.596416532993317f, 0.490615785121918f, + 0.596792817115784f, 0.490541696548462f, 0.597168982028961f, 0.490467309951782f, + 0.597545146942139f, 0.490392625331879f, 0.597921252250671f, 0.490317672491074f, + 0.598297297954559f, 0.490242421627045f, 0.598673284053802f, 0.490166902542114f, + 0.599049210548401f, 0.490091055631638f, 0.599425077438354f, 0.490014940500259f, + 0.599800884723663f, 0.489938557147980f, 0.600176632404327f, 0.489861875772476f, + 0.600552320480347f, 0.489784896373749f, 0.600927948951721f, 0.489707618951797f, + 0.601303517818451f, 0.489630073308945f, 0.601679027080536f, 0.489552229642868f, + 0.602054476737976f, 0.489474087953568f, 0.602429866790771f, 0.489395678043365f, + 0.602805197238922f, 0.489316970109940f, 0.603180468082428f, 0.489237964153290f, + 0.603555679321289f, 0.489158689975739f, 0.603930830955505f, 0.489079117774963f, + 0.604305922985077f, 0.488999247550964f, 0.604680955410004f, 0.488919109106064f, + 0.605055928230286f, 0.488838672637939f, 0.605430841445923f, 0.488757967948914f, + 0.605805635452271f, 0.488676935434341f, 0.606180429458618f, 0.488595664501190f, + 0.606555163860321f, 0.488514065742493f, 0.606929838657379f, 0.488432198762894f, + 0.607304394245148f, 0.488350033760071f, 0.607678949832916f, 0.488267600536346f, + 0.608053386211395f, 0.488184869289398f, 0.608427822589874f, 0.488101840019226f, + 0.608802139759064f, 0.488018542528152f, 0.609176397323608f, 0.487934947013855f, + 0.609550595283508f, 0.487851053476334f, 0.609924793243408f, 0.487766891717911f, + 0.610298871994019f, 0.487682431936264f, 0.610672831535339f, 0.487597703933716f, + 0.611046791076660f, 0.487512677907944f, 0.611420691013336f, 0.487427353858948f, + 0.611794531345367f, 0.487341761589050f, 0.612168252468109f, 0.487255871295929f, + 0.612541973590851f, 0.487169682979584f, 0.612915575504303f, 0.487083226442337f, + 0.613289117813110f, 0.486996471881866f, 0.613662600517273f, 0.486909449100494f, + 0.614036023616791f, 0.486822128295898f, 0.614409387111664f, 0.486734509468079f, + 0.614782691001892f, 0.486646622419357f, 0.615155875682831f, 0.486558437347412f, + 0.615529060363770f, 0.486469984054565f, 0.615902125835419f, 0.486381232738495f, + 0.616275131702423f, 0.486292183399200f, 0.616648077964783f, 0.486202865839005f, + 0.617020964622498f, 0.486113250255585f, 0.617393791675568f, 0.486023366451263f, + 0.617766559123993f, 0.485933154821396f, 0.618139207363129f, 0.485842704772949f, + 0.618511795997620f, 0.485751956701279f, 0.618884325027466f, 0.485660910606384f, + 0.619256794452667f, 0.485569566488266f, 0.619629204273224f, 0.485477954149246f, + 0.620001494884491f, 0.485386073589325f, 0.620373785495758f, 0.485293895006180f, + 0.620745956897736f, 0.485201418399811f, 0.621118068695068f, 0.485108673572540f, + 0.621490061283112f, 0.485015630722046f, 0.621862053871155f, 0.484922289848328f, + 0.622233927249908f, 0.484828680753708f, 0.622605800628662f, 0.484734803438187f, + 0.622977554798126f, 0.484640628099442f, 0.623349189758301f, 0.484546154737473f, + 0.623720824718475f, 0.484451413154602f, 0.624092340469360f, 0.484356373548508f, + 0.624463796615601f, 0.484261035919189f, 0.624835193157196f, 0.484165430068970f, + 0.625206530094147f, 0.484069555997849f, 0.625577747821808f, 0.483973383903503f, + 0.625948905944824f, 0.483876913785934f, 0.626320004463196f, 0.483780175447464f, + 0.626691043376923f, 0.483683139085770f, 0.627061963081360f, 0.483585834503174f, + 0.627432823181152f, 0.483488231897354f, 0.627803623676300f, 0.483390361070633f, + 0.628174364566803f, 0.483292192220688f, 0.628544986248016f, 0.483193725347519f, + 0.628915548324585f, 0.483094990253448f, 0.629286050796509f, 0.482995986938477f, + 0.629656434059143f, 0.482896685600281f, 0.630026817321777f, 0.482797086238861f, + 0.630397081375122f, 0.482697218656540f, 0.630767226219177f, 0.482597053050995f, + 0.631137371063232f, 0.482496619224548f, 0.631507396697998f, 0.482395917177200f, + 0.631877362728119f, 0.482294887304306f, 0.632247209548950f, 0.482193619012833f, + 0.632616996765137f, 0.482092022895813f, 0.632986724376678f, 0.481990188360214f, + 0.633356392383575f, 0.481888025999069f, 0.633725941181183f, 0.481785595417023f, + 0.634095430374146f, 0.481682896614075f, 0.634464859962463f, 0.481579899787903f, + 0.634834170341492f, 0.481476634740829f, 0.635203421115875f, 0.481373071670532f, + 0.635572552680969f, 0.481269240379334f, 0.635941684246063f, 0.481165111064911f, + 0.636310696601868f, 0.481060713529587f, 0.636679589748383f, 0.480956017971039f, + 0.637048482894897f, 0.480851024389267f, 0.637417197227478f, 0.480745792388916f, + 0.637785911560059f, 0.480640232563019f, 0.638154506683350f, 0.480534434318542f, + 0.638523042201996f, 0.480428308248520f, 0.638891458511353f, 0.480321943759918f, + 0.639259815216064f, 0.480215251445770f, 0.639628112316132f, 0.480108320713043f, + 0.639996349811554f, 0.480001062154770f, 0.640364408493042f, 0.479893565177917f, + 0.640732467174530f, 0.479785770177841f, 0.641100406646729f, 0.479677677154541f, + 0.641468286514282f, 0.479569315910339f, 0.641836047172546f, 0.479460656642914f, + 0.642203748226166f, 0.479351729154587f, 0.642571389675140f, 0.479242533445358f, + 0.642938911914825f, 0.479133039712906f, 0.643306374549866f, 0.479023247957230f, + 0.643673717975616f, 0.478913217782974f, 0.644041001796722f, 0.478802859783173f, + 0.644408226013184f, 0.478692263364792f, 0.644775331020355f, 0.478581339120865f, + 0.645142316818237f, 0.478470176458359f, 0.645509302616119f, 0.478358715772629f, + 0.645876109600067f, 0.478246957063675f, 0.646242916584015f, 0.478134930133820f, + 0.646609604358673f, 0.478022634983063f, 0.646976172924042f, 0.477910041809082f, + 0.647342681884766f, 0.477797180414200f, 0.647709131240845f, 0.477684020996094f, + 0.648075461387634f, 0.477570593357086f, 0.648441672325134f, 0.477456867694855f, + 0.648807883262634f, 0.477342873811722f, 0.649173915386200f, 0.477228611707687f, + 0.649539887905121f, 0.477114051580429f, 0.649905800819397f, 0.476999223232269f, + 0.650271594524384f, 0.476884096860886f, 0.650637328624725f, 0.476768702268600f, + 0.651003003120422f, 0.476653009653091f, 0.651368498802185f, 0.476537048816681f, + 0.651733994483948f, 0.476420819759369f, 0.652099311351776f, 0.476304292678833f, + 0.652464628219604f, 0.476187497377396f, 0.652829825878143f, 0.476070433855057f, + 0.653194904327393f, 0.475953072309494f, 0.653559923171997f, 0.475835442543030f, + 0.653924822807312f, 0.475717514753342f, 0.654289662837982f, 0.475599318742752f, + 0.654654383659363f, 0.475480824708939f, 0.655019044876099f, 0.475362062454224f, + 0.655383586883545f, 0.475243031978607f, 0.655748009681702f, 0.475123733282089f, + 0.656112432479858f, 0.475004136562347f, 0.656476676464081f, 0.474884241819382f, + 0.656840860843658f, 0.474764078855515f, 0.657204985618591f, 0.474643647670746f, + 0.657568991184235f, 0.474522948265076f, 0.657932877540588f, 0.474401950836182f, + 0.658296704292297f, 0.474280685186386f, 0.658660411834717f, 0.474159121513367f, + 0.659024059772491f, 0.474037289619446f, 0.659387588500977f, 0.473915189504623f, + 0.659750998020172f, 0.473792791366577f, 0.660114347934723f, 0.473670125007629f, + 0.660477638244629f, 0.473547190427780f, 0.660840749740601f, 0.473423957824707f, + 0.661203861236572f, 0.473300457000732f, 0.661566793918610f, 0.473176687955856f, + 0.661929666996002f, 0.473052620887756f, 0.662292480468750f, 0.472928285598755f, + 0.662655174732208f, 0.472803652286530f, 0.663017749786377f, 0.472678780555725f, + 0.663380205631256f, 0.472553610801697f, 0.663742601871490f, 0.472428143024445f, + 0.664104938507080f, 0.472302407026291f, 0.664467096328735f, 0.472176402807236f, + 0.664829254150391f, 0.472050130367279f, 0.665191233158112f, 0.471923559904099f, + 0.665553152561188f, 0.471796721220016f, 0.665914952754974f, 0.471669614315033f, + 0.666276693344116f, 0.471542209386826f, 0.666638314723969f, 0.471414536237717f, + 0.666999816894531f, 0.471286594867706f, 0.667361259460449f, 0.471158385276794f, + 0.667722582817078f, 0.471029877662659f, 0.668083786964417f, 0.470901101827621f, + 0.668444931507111f, 0.470772027969360f, 0.668805956840515f, 0.470642685890198f, + 0.669166862964630f, 0.470513075590134f, 0.669527709484100f, 0.470383197069168f, + 0.669888436794281f, 0.470253020524979f, 0.670249044895172f, 0.470122605562210f, + 0.670609593391418f, 0.469991862773895f, 0.670970022678375f, 0.469860881567001f, + 0.671330332756042f, 0.469729602336884f, 0.671690583229065f, 0.469598054885864f, + 0.672050714492798f, 0.469466239213943f, 0.672410726547241f, 0.469334155321121f, + 0.672770678997040f, 0.469201773405075f, 0.673130512237549f, 0.469069123268127f, + 0.673490226268768f, 0.468936175107956f, 0.673849821090698f, 0.468802988529205f, + 0.674209356307983f, 0.468669503927231f, 0.674568772315979f, 0.468535751104355f, + 0.674928069114685f, 0.468401730060577f, 0.675287246704102f, 0.468267410993576f, + 0.675646364688873f, 0.468132823705673f, 0.676005363464355f, 0.467997968196869f, + 0.676364302635193f, 0.467862844467163f, 0.676723062992096f, 0.467727422714233f, + 0.677081763744354f, 0.467591762542725f, 0.677440345287323f, 0.467455804347992f, + 0.677798807621002f, 0.467319577932358f, 0.678157210350037f, 0.467183053493500f, + 0.678515493869781f, 0.467046260833740f, 0.678873658180237f, 0.466909229755402f, + 0.679231703281403f, 0.466771900653839f, 0.679589688777924f, 0.466634273529053f, + 0.679947495460510f, 0.466496407985687f, 0.680305242538452f, 0.466358244419098f, + 0.680662930011749f, 0.466219812631607f, 0.681020438671112f, 0.466081112623215f, + 0.681377887725830f, 0.465942144393921f, 0.681735157966614f, 0.465802878141403f, + 0.682092368602753f, 0.465663343667984f, 0.682449519634247f, 0.465523540973663f, + 0.682806491851807f, 0.465383470058441f, 0.683163404464722f, 0.465243130922318f, + 0.683520197868347f, 0.465102523565292f, 0.683876872062683f, 0.464961618185043f, + 0.684233427047729f, 0.464820444583893f, 0.684589862823486f, 0.464679002761841f, + 0.684946238994598f, 0.464537292718887f, 0.685302436351776f, 0.464395314455032f, + 0.685658574104309f, 0.464253038167953f, 0.686014592647552f, 0.464110493659973f, + 0.686370551586151f, 0.463967710733414f, 0.686726331710815f, 0.463824629783630f, + 0.687082052230835f, 0.463681250810623f, 0.687437593936920f, 0.463537633419037f, + 0.687793076038361f, 0.463393747806549f, 0.688148438930511f, 0.463249564170837f, + 0.688503682613373f, 0.463105112314224f, 0.688858866691589f, 0.462960392236710f, + 0.689213871955872f, 0.462815403938293f, 0.689568817615509f, 0.462670147418976f, + 0.689923584461212f, 0.462524622678757f, 0.690278291702271f, 0.462378799915314f, + 0.690632879734039f, 0.462232738733292f, 0.690987348556519f, 0.462086379528046f, + 0.691341698169708f, 0.461939752101898f, 0.691695988178253f, 0.461792886257172f, + 0.692050099372864f, 0.461645722389221f, 0.692404091358185f, 0.461498260498047f, + 0.692758023738861f, 0.461350560188293f, 0.693111836910248f, 0.461202591657639f, + 0.693465530872345f, 0.461054325103760f, 0.693819046020508f, 0.460905820131302f, + 0.694172501564026f, 0.460757017135620f, 0.694525837898254f, 0.460607945919037f, + 0.694879114627838f, 0.460458606481552f, 0.695232212543488f, 0.460309028625488f, + 0.695585191249847f, 0.460159152746201f, 0.695938050746918f, 0.460008978843689f, + 0.696290850639343f, 0.459858566522598f, 0.696643471717834f, 0.459707885980606f, + 0.696996033191681f, 0.459556937217712f, 0.697348415851593f, 0.459405690431595f, + 0.697700738906860f, 0.459254205226898f, 0.698052942752838f, 0.459102421998978f, + 0.698404967784882f, 0.458950400352478f, 0.698756933212280f, 0.458798080682755f, + 0.699108779430389f, 0.458645492792130f, 0.699460506439209f, 0.458492636680603f, + 0.699812114238739f, 0.458339542150497f, 0.700163602828979f, 0.458186149597168f, + 0.700514972209930f, 0.458032488822937f, 0.700866222381592f, 0.457878559827805f, + 0.701217353343964f, 0.457724362611771f, 0.701568365097046f, 0.457569897174835f, + 0.701919257640839f, 0.457415163516998f, 0.702270030975342f, 0.457260161638260f, + 0.702620685100555f, 0.457104891538620f, 0.702971220016479f, 0.456949323415756f, + 0.703321635723114f, 0.456793516874313f, 0.703671932220459f, 0.456637442111969f, + 0.704022109508514f, 0.456481099128723f, 0.704372167587280f, 0.456324487924576f, + 0.704722046852112f, 0.456167578697205f, 0.705071866512299f, 0.456010431051254f, + 0.705421566963196f, 0.455853015184402f, 0.705771148204803f, 0.455695331096649f, + 0.706120610237122f, 0.455537378787994f, 0.706469953060150f, 0.455379128456116f, + 0.706819176673889f, 0.455220639705658f, 0.707168221473694f, 0.455061882734299f, + 0.707517206668854f, 0.454902857542038f, 0.707866072654724f, 0.454743564128876f, + 0.708214759826660f, 0.454584002494812f, 0.708563387393951f, 0.454424172639847f, + 0.708911836147308f, 0.454264044761658f, 0.709260225296021f, 0.454103678464890f, + 0.709608435630798f, 0.453943043947220f, 0.709956526756287f, 0.453782171010971f, + 0.710304558277130f, 0.453621000051498f, 0.710652410984039f, 0.453459560871124f, + 0.711000144481659f, 0.453297853469849f, 0.711347758769989f, 0.453135877847672f, + 0.711695253849030f, 0.452973634004593f, 0.712042629718781f, 0.452811151742935f, + 0.712389826774597f, 0.452648371458054f, 0.712736964225769f, 0.452485352754593f, + 0.713083922863007f, 0.452322036027908f, 0.713430821895599f, 0.452158480882645f, + 0.713777542114258f, 0.451994657516479f, 0.714124143123627f, 0.451830536127090f, + 0.714470624923706f, 0.451666176319122f, 0.714816987514496f, 0.451501548290253f, + 0.715163230895996f, 0.451336652040482f, 0.715509355068207f, 0.451171487569809f, + 0.715855300426483f, 0.451006084680557f, 0.716201186180115f, 0.450840383768082f, + 0.716546893119812f, 0.450674414634705f, 0.716892480850220f, 0.450508207082748f, + 0.717238008975983f, 0.450341701507568f, 0.717583298683167f, 0.450174957513809f, + 0.717928528785706f, 0.450007945299149f, 0.718273639678955f, 0.449840664863586f, + 0.718618571758270f, 0.449673116207123f, 0.718963444232941f, 0.449505299329758f, + 0.719308137893677f, 0.449337244033813f, 0.719652712345123f, 0.449168890714645f, + 0.719997107982636f, 0.449000298976898f, 0.720341444015503f, 0.448831409215927f, + 0.720685660839081f, 0.448662281036377f, 0.721029698848724f, 0.448492884635925f, + 0.721373617649078f, 0.448323249816895f, 0.721717417240143f, 0.448153316974640f, + 0.722061097621918f, 0.447983115911484f, 0.722404599189758f, 0.447812676429749f, + 0.722747981548309f, 0.447641968727112f, 0.723091304302216f, 0.447470992803574f, + 0.723434448242188f, 0.447299748659134f, 0.723777413368225f, 0.447128236293793f, + 0.724120318889618f, 0.446956485509872f, 0.724463045597076f, 0.446784436702728f, + 0.724805653095245f, 0.446612149477005f, 0.725148141384125f, 0.446439594030380f, + 0.725490510463715f, 0.446266770362854f, 0.725832700729370f, 0.446093708276749f, + 0.726174771785736f, 0.445920348167419f, 0.726516723632813f, 0.445746749639511f, + 0.726858556270599f, 0.445572882890701f, 0.727200269699097f, 0.445398747920990f, + 0.727541804313660f, 0.445224374532700f, 0.727883219718933f, 0.445049703121185f, + 0.728224515914917f, 0.444874793291092f, 0.728565633296967f, 0.444699615240097f, + 0.728906631469727f, 0.444524168968201f, 0.729247510433197f, 0.444348484277725f, + 0.729588270187378f, 0.444172531366348f, 0.729928910732269f, 0.443996280431747f, + 0.730269372463226f, 0.443819820880890f, 0.730609714984894f, 0.443643063306808f, + 0.730949878692627f, 0.443466067314148f, 0.731289982795715f, 0.443288803100586f, + 0.731629908084869f, 0.443111270666122f, 0.731969714164734f, 0.442933470010757f, + 0.732309341430664f, 0.442755430936813f, 0.732648849487305f, 0.442577123641968f, + 0.732988238334656f, 0.442398548126221f, 0.733327507972717f, 0.442219734191895f, + 0.733666598796844f, 0.442040622234344f, 0.734005570411682f, 0.441861271858215f, + 0.734344422817230f, 0.441681683063507f, 0.734683096408844f, 0.441501796245575f, + 0.735021650791168f, 0.441321671009064f, 0.735360085964203f, 0.441141277551651f, + 0.735698342323303f, 0.440960645675659f, 0.736036539077759f, 0.440779715776443f, + 0.736374497413635f, 0.440598547458649f, 0.736712396144867f, 0.440417140722275f, + 0.737050116062164f, 0.440235435962677f, 0.737387716770172f, 0.440053492784500f, + 0.737725138664246f, 0.439871311187744f, 0.738062441349030f, 0.439688831567764f, + 0.738399624824524f, 0.439506113529205f, 0.738736629486084f, 0.439323127269745f, + 0.739073514938354f, 0.439139902591705f, 0.739410281181335f, 0.438956409692764f, + 0.739746868610382f, 0.438772648572922f, 0.740083336830139f, 0.438588619232178f, + 0.740419685840607f, 0.438404351472855f, 0.740755856037140f, 0.438219845294952f, + 0.741091907024384f, 0.438035041093826f, 0.741427779197693f, 0.437849998474121f, + 0.741763532161713f, 0.437664687633514f, 0.742099165916443f, 0.437479138374329f, + 0.742434620857239f, 0.437293320894241f, 0.742769956588745f, 0.437107264995575f, + 0.743105113506317f, 0.436920911073685f, 0.743440151214600f, 0.436734348535538f, + 0.743775069713593f, 0.436547487974167f, 0.744109809398651f, 0.436360388994217f, + 0.744444429874420f, 0.436173021793365f, 0.744778931140900f, 0.435985416173935f, + 0.745113253593445f, 0.435797542333603f, 0.745447397232056f, 0.435609430074692f, + 0.745781481266022f, 0.435421019792557f, 0.746115326881409f, 0.435232400894165f, + 0.746449112892151f, 0.435043483972549f, 0.746782720088959f, 0.434854328632355f, + 0.747116148471832f, 0.434664934873581f, 0.747449457645416f, 0.434475272893906f, + 0.747782647609711f, 0.434285342693329f, 0.748115658760071f, 0.434095174074173f, + 0.748448550701141f, 0.433904737234116f, 0.748781263828278f, 0.433714061975479f, + 0.749113857746124f, 0.433523118495941f, 0.749446272850037f, 0.433331936597824f, + 0.749778568744659f, 0.433140486478806f, 0.750110685825348f, 0.432948768138886f, + 0.750442683696747f, 0.432756811380386f, 0.750774562358856f, 0.432564586400986f, + 0.751106262207031f, 0.432372123003006f, 0.751437783241272f, 0.432179391384125f, + 0.751769185066223f, 0.431986421346664f, 0.752100467681885f, 0.431793183088303f, + 0.752431571483612f, 0.431599706411362f, 0.752762496471405f, 0.431405961513519f, + 0.753093302249908f, 0.431211978197098f, 0.753423988819122f, 0.431017726659775f, + 0.753754496574402f, 0.430823236703873f, 0.754084885120392f, 0.430628478527069f, + 0.754415094852448f, 0.430433481931686f, 0.754745125770569f, 0.430238217115402f, + 0.755075037479401f, 0.430042684078217f, 0.755404829978943f, 0.429846942424774f, + 0.755734443664551f, 0.429650902748108f, 0.756063878536224f, 0.429454624652863f, + 0.756393194198608f, 0.429258108139038f, 0.756722390651703f, 0.429061323404312f, + 0.757051348686218f, 0.428864300251007f, 0.757380247116089f, 0.428667008876801f, + 0.757708966732025f, 0.428469479084015f, 0.758037507534027f, 0.428271710872650f, + 0.758365929126740f, 0.428073674440384f, 0.758694171905518f, 0.427875369787216f, + 0.759022235870361f, 0.427676826715469f, 0.759350180625916f, 0.427478045225143f, + 0.759678006172180f, 0.427278995513916f, 0.760005652904511f, 0.427079707384110f, + 0.760333120822906f, 0.426880151033401f, 0.760660469532013f, 0.426680356264114f, + 0.760987639427185f, 0.426480293273926f, 0.761314690113068f, 0.426279991865158f, + 0.761641561985016f, 0.426079452037811f, 0.761968255043030f, 0.425878643989563f, + 0.762294828891754f, 0.425677597522736f, 0.762621283531189f, 0.425476282835007f, + 0.762947499752045f, 0.425274729728699f, 0.763273596763611f, 0.425072938203812f, + 0.763599574565887f, 0.424870878458023f, 0.763925373554230f, 0.424668580293655f, + 0.764250993728638f, 0.424466013908386f, 0.764576494693756f, 0.424263238906860f, + 0.764901816844940f, 0.424060165882111f, 0.765226960182190f, 0.423856884241104f, + 0.765551984310150f, 0.423653304576874f, 0.765876889228821f, 0.423449516296387f, + 0.766201555728912f, 0.423245459794998f, 0.766526103019714f, 0.423041164875031f, + 0.766850471496582f, 0.422836631536484f, 0.767174720764160f, 0.422631829977036f, + 0.767498791217804f, 0.422426789999008f, 0.767822742462158f, 0.422221481800079f, + 0.768146514892578f, 0.422015935182571f, 0.768470108509064f, 0.421810150146484f, + 0.768793523311615f, 0.421604126691818f, 0.769116818904877f, 0.421397835016251f, + 0.769439935684204f, 0.421191304922104f, 0.769762933254242f, 0.420984506607056f, + 0.770085752010345f, 0.420777499675751f, 0.770408391952515f, 0.420570224523544f, + 0.770730912685394f, 0.420362681150436f, 0.771053194999695f, 0.420154929161072f, + 0.771375417709351f, 0.419946908950806f, 0.771697402000427f, 0.419738620519638f, + 0.772019267082214f, 0.419530123472214f, 0.772340953350067f, 0.419321358203888f, + 0.772662520408630f, 0.419112354516983f, 0.772983849048615f, 0.418903112411499f, + 0.773305058479309f, 0.418693602085114f, 0.773626148700714f, 0.418483853340149f, + 0.773947000503540f, 0.418273866176605f, 0.774267733097076f, 0.418063640594482f, + 0.774588346481323f, 0.417853146791458f, 0.774908721446991f, 0.417642414569855f, + 0.775228977203369f, 0.417431443929672f, 0.775549054145813f, 0.417220205068588f, + 0.775869011878967f, 0.417008757591248f, 0.776188731193542f, 0.416797041893005f, + 0.776508331298828f, 0.416585087776184f, 0.776827812194824f, 0.416372895240784f, + 0.777147054672241f, 0.416160434484482f, 0.777466177940369f, 0.415947735309601f, + 0.777785122394562f, 0.415734797716141f, 0.778103888034821f, 0.415521621704102f, + 0.778422534465790f, 0.415308207273483f, 0.778741002082825f, 0.415094524621964f, + 0.779059290885925f, 0.414880603551865f, 0.779377400875092f, 0.414666473865509f, + 0.779695332050323f, 0.414452046155930f, 0.780013144016266f, 0.414237409830093f, + 0.780330777168274f, 0.414022535085678f, 0.780648231506348f, 0.413807392120361f, + 0.780965566635132f, 0.413592010736465f, 0.781282722949982f, 0.413376390933990f, + 0.781599700450897f, 0.413160532712936f, 0.781916499137878f, 0.412944436073303f, + 0.782233119010925f, 0.412728071212769f, 0.782549619674683f, 0.412511497735977f, + 0.782865881919861f, 0.412294656038284f, 0.783182024955750f, 0.412077575922012f, + 0.783498048782349f, 0.411860257387161f, 0.783813834190369f, 0.411642700433731f, + 0.784129500389099f, 0.411424905061722f, 0.784444928169250f, 0.411206841468811f, + 0.784760236740112f, 0.410988569259644f, 0.785075426101685f, 0.410770028829575f, + 0.785390377044678f, 0.410551249980927f, 0.785705149173737f, 0.410332232713699f, + 0.786019802093506f, 0.410112977027893f, 0.786334276199341f, 0.409893482923508f, + 0.786648571491241f, 0.409673750400543f, 0.786962687969208f, 0.409453779459000f, + 0.787276685237885f, 0.409233570098877f, 0.787590444087982f, 0.409013092517853f, + 0.787904083728790f, 0.408792406320572f, 0.788217544555664f, 0.408571451902390f, + 0.788530826568604f, 0.408350288867950f, 0.788843929767609f, 0.408128857612610f, + 0.789156913757324f, 0.407907217741013f, 0.789469659328461f, 0.407685309648514f, + 0.789782285690308f, 0.407463163137436f, 0.790094733238220f, 0.407240778207779f, + 0.790407001972198f, 0.407018154859543f, 0.790719091892242f, 0.406795293092728f, + 0.791031002998352f, 0.406572192907333f, 0.791342735290527f, 0.406348884105682f, + 0.791654348373413f, 0.406125307083130f, 0.791965723037720f, 0.405901491641998f, + 0.792276978492737f, 0.405677437782288f, 0.792588055133820f, 0.405453115701675f, + 0.792898952960968f, 0.405228585004807f, 0.793209671974182f, 0.405003815889359f, + 0.793520212173462f, 0.404778808355331f, 0.793830573558807f, 0.404553562402725f, + 0.794140756130219f, 0.404328078031540f, 0.794450819492340f, 0.404102355241776f, + 0.794760644435883f, 0.403876423835754f, 0.795070350170136f, 0.403650224208832f, + 0.795379877090454f, 0.403423786163330f, 0.795689165592194f, 0.403197109699249f, + 0.795998334884644f, 0.402970194816589f, 0.796307325363159f, 0.402743041515350f, + 0.796616137027740f, 0.402515679597855f, 0.796924769878387f, 0.402288049459457f, + 0.797233223915100f, 0.402060180902481f, 0.797541558742523f, 0.401832103729248f, + 0.797849655151367f, 0.401603758335114f, 0.798157572746277f, 0.401375204324722f, + 0.798465371131897f, 0.401146411895752f, 0.798772931098938f, 0.400917351245880f, + 0.799080371856689f, 0.400688081979752f, 0.799387574195862f, 0.400458574295044f, + 0.799694657325745f, 0.400228828191757f, 0.800001561641693f, 0.399998843669891f, + 0.800308227539063f, 0.399768620729446f, 0.800614774227142f, 0.399538189172745f, + 0.800921142101288f, 0.399307489395142f, 0.801227271556854f, 0.399076581001282f, + 0.801533281803131f, 0.398845434188843f, 0.801839113235474f, 0.398614019155502f, + 0.802144765853882f, 0.398382395505905f, 0.802450239658356f, 0.398150533437729f, + 0.802755534648895f, 0.397918462753296f, 0.803060650825500f, 0.397686123847961f, + 0.803365588188171f, 0.397453576326370f, 0.803670346736908f, 0.397220760583878f, + 0.803974866867065f, 0.396987736225128f, 0.804279267787933f, 0.396754473447800f, + 0.804583489894867f, 0.396520972251892f, 0.804887533187866f, 0.396287262439728f, + 0.805191397666931f, 0.396053284406662f, 0.805495083332062f, 0.395819097757339f, + 0.805798590183258f, 0.395584672689438f, 0.806101918220520f, 0.395350009202957f, + 0.806405067443848f, 0.395115107297897f, 0.806707978248596f, 0.394879996776581f, + 0.807010769844055f, 0.394644618034363f, 0.807313382625580f, 0.394409030675888f, + 0.807615816593170f, 0.394173204898834f, 0.807918012142181f, 0.393937170505524f, + 0.808220088481903f, 0.393700867891312f, 0.808521986007690f, 0.393464356660843f, + 0.808823645114899f, 0.393227607011795f, 0.809125185012817f, 0.392990618944168f, + 0.809426486492157f, 0.392753422260284f, 0.809727668762207f, 0.392515957355499f, + 0.810028612613678f, 0.392278283834457f, 0.810329377651215f, 0.392040401697159f, + 0.810629963874817f, 0.391802251338959f, 0.810930430889130f, 0.391563892364502f, + 0.811230659484863f, 0.391325294971466f, 0.811530709266663f, 0.391086459159851f, + 0.811830580234528f, 0.390847414731979f, 0.812130272388458f, 0.390608131885529f, + 0.812429726123810f, 0.390368610620499f, 0.812729060649872f, 0.390128880739212f, + 0.813028216362000f, 0.389888882637024f, 0.813327133655548f, 0.389648675918579f, + 0.813625931739807f, 0.389408260583878f, 0.813924491405487f, 0.389167606830597f, + 0.814222872257233f, 0.388926714658737f, 0.814521074295044f, 0.388685584068298f, + 0.814819097518921f, 0.388444244861603f, 0.815116941928864f, 0.388202667236328f, + 0.815414607524872f, 0.387960851192474f, 0.815712094306946f, 0.387718826532364f, + 0.816009342670441f, 0.387476563453674f, 0.816306471824646f, 0.387234061956406f, + 0.816603362560272f, 0.386991351842880f, 0.816900074481964f, 0.386748403310776f, + 0.817196667194366f, 0.386505216360092f, 0.817493021488190f, 0.386261820793152f, + 0.817789137363434f, 0.386018186807632f, 0.818085134029388f, 0.385774344205856f, + 0.818380951881409f, 0.385530263185501f, 0.818676531314850f, 0.385285943746567f, + 0.818971931934357f, 0.385041415691376f, 0.819267153739929f, 0.384796649217606f, + 0.819562196731567f, 0.384551674127579f, 0.819857060909271f, 0.384306460618973f, + 0.820151746273041f, 0.384061008691788f, 0.820446193218231f, 0.383815348148346f, + 0.820740520954132f, 0.383569449186325f, 0.821034610271454f, 0.383323341608047f, + 0.821328520774841f, 0.383076995611191f, 0.821622252464294f, 0.382830440998077f, + 0.821915745735168f, 0.382583618164063f, 0.822209119796753f, 0.382336616516113f, + 0.822502255439758f, 0.382089376449585f, 0.822795212268829f, 0.381841897964478f, + 0.823087990283966f, 0.381594210863113f, 0.823380589485168f, 0.381346285343170f, + 0.823673009872437f, 0.381098151206970f, 0.823965191841125f, 0.380849778652191f, + 0.824257194995880f, 0.380601197481155f, 0.824549019336700f, 0.380352377891541f, + 0.824840664863586f, 0.380103349685669f, 0.825132071971893f, 0.379854083061218f, + 0.825423359870911f, 0.379604607820511f, 0.825714409351349f, 0.379354894161224f, + 0.826005280017853f, 0.379104942083359f, 0.826295912265778f, 0.378854811191559f, + 0.826586425304413f, 0.378604412078857f, 0.826876699924469f, 0.378353834152222f, + 0.827166795730591f, 0.378102988004684f, 0.827456712722778f, 0.377851963043213f, + 0.827746450901031f, 0.377600699663162f, 0.828035950660706f, 0.377349197864532f, + 0.828325271606445f, 0.377097487449646f, 0.828614413738251f, 0.376845568418503f, + 0.828903317451477f, 0.376593410968781f, 0.829192101955414f, 0.376341015100479f, + 0.829480648040771f, 0.376088410615921f, 0.829769015312195f, 0.375835597515106f, + 0.830057144165039f, 0.375582575798035f, 0.830345153808594f, 0.375329315662384f, + 0.830632925033569f, 0.375075817108154f, 0.830920517444611f, 0.374822109937668f, + 0.831207871437073f, 0.374568194150925f, 0.831495106220245f, 0.374314039945602f, + 0.831782102584839f, 0.374059677124023f, 0.832068860530853f, 0.373805105686188f, + 0.832355499267578f, 0.373550295829773f, 0.832641899585724f, 0.373295277357101f, + 0.832928121089935f, 0.373040050268173f, 0.833214163780212f, 0.372784584760666f, + 0.833499968051910f, 0.372528880834579f, 0.833785593509674f, 0.372272998094559f, + 0.834071040153503f, 0.372016876935959f, 0.834356248378754f, 0.371760547161102f, + 0.834641277790070f, 0.371503978967667f, 0.834926128387451f, 0.371247202157974f, + 0.835210800170898f, 0.370990216732025f, 0.835495233535767f, 0.370732992887497f, + 0.835779488086700f, 0.370475560426712f, 0.836063504219055f, 0.370217919349670f, + 0.836347401142120f, 0.369960039854050f, 0.836631059646606f, 0.369701951742172f, + 0.836914479732513f, 0.369443655014038f, 0.837197780609131f, 0.369185149669647f, + 0.837480843067169f, 0.368926405906677f, 0.837763667106628f, 0.368667453527451f, + 0.838046371936798f, 0.368408292531967f, 0.838328838348389f, 0.368148893117905f, + 0.838611066341400f, 0.367889285087585f, 0.838893175125122f, 0.367629468441010f, + 0.839175045490265f, 0.367369443178177f, 0.839456677436829f, 0.367109179496765f, + 0.839738130569458f, 0.366848707199097f, 0.840019404888153f, 0.366588026285172f, + 0.840300500392914f, 0.366327136754990f, 0.840581357479095f, 0.366066008806229f, + 0.840862035751343f, 0.365804702043533f, 0.841142535209656f, 0.365543156862259f, + 0.841422796249390f, 0.365281373262405f, 0.841702818870544f, 0.365019410848618f, + 0.841982722282410f, 0.364757210016251f, 0.842262387275696f, 0.364494800567627f, + 0.842541813850403f, 0.364232182502747f, 0.842821121215820f, 0.363969355821610f, + 0.843100130558014f, 0.363706320524216f, 0.843379020690918f, 0.363443046808243f, + 0.843657672405243f, 0.363179564476013f, 0.843936145305634f, 0.362915903329849f, + 0.844214379787445f, 0.362651973962784f, 0.844492435455322f, 0.362387865781784f, + 0.844770252704620f, 0.362123548984528f, 0.845047891139984f, 0.361858993768692f, + 0.845325350761414f, 0.361594229936600f, 0.845602571964264f, 0.361329287290573f, + 0.845879614353180f, 0.361064106225967f, 0.846156477928162f, 0.360798716545105f, + 0.846433103084564f, 0.360533088445663f, 0.846709489822388f, 0.360267281532288f, + 0.846985757350922f, 0.360001266002655f, 0.847261726856232f, 0.359735012054443f, + 0.847537577152252f, 0.359468549489975f, 0.847813189029694f, 0.359201908111572f, + 0.848088562488556f, 0.358935028314590f, 0.848363757133484f, 0.358667939901352f, + 0.848638772964478f, 0.358400642871857f, 0.848913550376892f, 0.358133137226105f, + 0.849188148975372f, 0.357865422964096f, 0.849462509155273f, 0.357597470283508f, + 0.849736690521240f, 0.357329338788986f, 0.850010633468628f, 0.357060998678207f, + 0.850284397602081f, 0.356792420148849f, 0.850557923316956f, 0.356523662805557f, + 0.850831270217896f, 0.356254696846008f, 0.851104438304901f, 0.355985492467880f, + 0.851377367973328f, 0.355716109275818f, 0.851650118827820f, 0.355446487665176f, + 0.851922631263733f, 0.355176687240601f, 0.852194905281067f, 0.354906648397446f, + 0.852467060089111f, 0.354636400938034f, 0.852738916873932f, 0.354365974664688f, + 0.853010654449463f, 0.354095309972763f, 0.853282094001770f, 0.353824466466904f, + 0.853553414344788f, 0.353553384542465f, 0.853824436664581f, 0.353282123804092f, + 0.854095339775085f, 0.353010624647141f, 0.854365944862366f, 0.352738946676254f, + 0.854636430740356f, 0.352467030286789f, 0.854906618595123f, 0.352194935083389f, + 0.855176687240601f, 0.351922631263733f, 0.855446517467499f, 0.351650089025497f, + 0.855716109275818f, 0.351377367973328f, 0.855985522270203f, 0.351104438304901f, + 0.856254696846008f, 0.350831300020218f, 0.856523692607880f, 0.350557953119278f, + 0.856792449951172f, 0.350284397602081f, 0.857060968875885f, 0.350010633468628f, + 0.857329368591309f, 0.349736660718918f, 0.857597470283508f, 0.349462509155273f, + 0.857865393161774f, 0.349188119173050f, 0.858133137226105f, 0.348913550376892f, + 0.858400642871857f, 0.348638743162155f, 0.858667910099030f, 0.348363757133484f, + 0.858934998512268f, 0.348088562488556f, 0.859201908111572f, 0.347813159227371f, + 0.859468579292297f, 0.347537547349930f, 0.859735012054443f, 0.347261756658554f, + 0.860001266002655f, 0.346985727548599f, 0.860267281532288f, 0.346709519624710f, + 0.860533118247986f, 0.346433073282242f, 0.860798716545105f, 0.346156448125839f, + 0.861064076423645f, 0.345879614353180f, 0.861329257488251f, 0.345602601766586f, + 0.861594259738922f, 0.345325350761414f, 0.861859023571014f, 0.345047920942307f, + 0.862123548984528f, 0.344770282506943f, 0.862387895584106f, 0.344492435455322f, + 0.862652003765106f, 0.344214379787445f, 0.862915873527527f, 0.343936115503311f, + 0.863179564476013f, 0.343657672405243f, 0.863443076610565f, 0.343379020690918f, + 0.863706290721893f, 0.343100160360336f, 0.863969385623932f, 0.342821091413498f, + 0.864232182502747f, 0.342541843652725f, 0.864494800567627f, 0.342262357473373f, + 0.864757239818573f, 0.341982692480087f, 0.865019381046295f, 0.341702848672867f, + 0.865281403064728f, 0.341422766447067f, 0.865543127059937f, 0.341142505407333f, + 0.865804672241211f, 0.340862035751343f, 0.866066038608551f, 0.340581357479095f, + 0.866327106952667f, 0.340300500392914f, 0.866588056087494f, 0.340019434690475f, + 0.866848707199097f, 0.339738160371780f, 0.867109179496765f, 0.339456677436829f, + 0.867369413375854f, 0.339175015687943f, 0.867629468441010f, 0.338893145322800f, + 0.867889285087585f, 0.338611096143723f, 0.868148922920227f, 0.338328808546066f, + 0.868408262729645f, 0.338046342134476f, 0.868667483329773f, 0.337763696908951f, + 0.868926405906677f, 0.337480813264847f, 0.869185149669647f, 0.337197750806808f, + 0.869443655014038f, 0.336914509534836f, 0.869701981544495f, 0.336631029844284f, + 0.869960069656372f, 0.336347371339798f, 0.870217919349670f, 0.336063534021378f, + 0.870475590229034f, 0.335779488086700f, 0.870733022689819f, 0.335495233535767f, + 0.870990216732025f, 0.335210770368576f, 0.871247172355652f, 0.334926128387451f, + 0.871503949165344f, 0.334641307592392f, 0.871760547161102f, 0.334356248378754f, + 0.872016847133636f, 0.334071010351181f, 0.872272968292236f, 0.333785593509674f, + 0.872528910636902f, 0.333499968051910f, 0.872784554958344f, 0.333214133977890f, + 0.873040020465851f, 0.332928121089935f, 0.873295307159424f, 0.332641899585724f, + 0.873550295829773f, 0.332355499267578f, 0.873805105686188f, 0.332068890333176f, + 0.874059677124023f, 0.331782072782516f, 0.874314069747925f, 0.331495076417923f, + 0.874568223953247f, 0.331207901239395f, 0.874822139739990f, 0.330920487642288f, + 0.875075817108154f, 0.330632925033569f, 0.875329315662384f, 0.330345153808594f, + 0.875582575798035f, 0.330057173967361f, 0.875835597515106f, 0.329769015312195f, + 0.876088440418243f, 0.329480648040771f, 0.876341044902802f, 0.329192101955414f, + 0.876593410968781f, 0.328903347253799f, 0.876845538616180f, 0.328614413738251f, + 0.877097487449646f, 0.328325271606445f, 0.877349197864532f, 0.328035950660706f, + 0.877600669860840f, 0.327746421098709f, 0.877851963043213f, 0.327456712722778f, + 0.878103017807007f, 0.327166795730591f, 0.878353834152222f, 0.326876699924469f, + 0.878604412078857f, 0.326586425304413f, 0.878854811191559f, 0.326295942068100f, + 0.879104971885681f, 0.326005280017853f, 0.879354894161224f, 0.325714409351349f, + 0.879604578018188f, 0.325423330068588f, 0.879854083061218f, 0.325132101774216f, + 0.880103349685669f, 0.324840664863586f, 0.880352377891541f, 0.324549019336700f, + 0.880601167678833f, 0.324257194995880f, 0.880849778652191f, 0.323965191841125f, + 0.881098151206970f, 0.323672980070114f, 0.881346285343170f, 0.323380589485168f, + 0.881594181060791f, 0.323088020086288f, 0.881841897964478f, 0.322795242071152f, + 0.882089376449585f, 0.322502255439758f, 0.882336616516113f, 0.322209119796753f, + 0.882583618164063f, 0.321915775537491f, 0.882830440998077f, 0.321622252464294f, + 0.883076965808868f, 0.321328520774841f, 0.883323311805725f, 0.321034610271454f, + 0.883569478988647f, 0.320740520954132f, 0.883815348148346f, 0.320446223020554f, + 0.884061038494110f, 0.320151746273041f, 0.884306430816650f, 0.319857090711594f, + 0.884551644325256f, 0.319562226533890f, 0.884796679019928f, 0.319267183542252f, + 0.885041415691376f, 0.318971961736679f, 0.885285973548889f, 0.318676531314850f, + 0.885530233383179f, 0.318380922079086f, 0.885774314403534f, 0.318085134029388f, + 0.886018216609955f, 0.317789167165756f, 0.886261820793152f, 0.317492991685867f, + 0.886505246162415f, 0.317196637392044f, 0.886748373508453f, 0.316900104284287f, + 0.886991322040558f, 0.316603392362595f, 0.887234091758728f, 0.316306471824646f, + 0.887476563453674f, 0.316009372472763f, 0.887718796730042f, 0.315712094306946f, + 0.887960851192474f, 0.315414607524872f, 0.888202667236328f, 0.315116971731186f, + 0.888444244861603f, 0.314819127321243f, 0.888685584068298f, 0.314521104097366f, + 0.888926684856415f, 0.314222872257233f, 0.889167606830597f, 0.313924491405487f, + 0.889408230781555f, 0.313625901937485f, 0.889648675918579f, 0.313327133655548f, + 0.889888882637024f, 0.313028186559677f, 0.890128850936890f, 0.312729060649872f, + 0.890368640422821f, 0.312429755926132f, 0.890608131885529f, 0.312130242586136f, + 0.890847444534302f, 0.311830550432205f, 0.891086459159851f, 0.311530679464340f, + 0.891325294971466f, 0.311230629682541f, 0.891563892364502f, 0.310930401086807f, + 0.891802251338959f, 0.310629993677139f, 0.892040371894836f, 0.310329377651215f, + 0.892278313636780f, 0.310028612613678f, 0.892515957355499f, 0.309727638959885f, + 0.892753422260284f, 0.309426486492157f, 0.892990648746490f, 0.309125155210495f, + 0.893227577209473f, 0.308823645114899f, 0.893464326858521f, 0.308521956205368f, + 0.893700897693634f, 0.308220088481903f, 0.893937170505524f, 0.307918041944504f, + 0.894173204898834f, 0.307615786790848f, 0.894409060478210f, 0.307313382625580f, + 0.894644618034363f, 0.307010769844055f, 0.894879996776581f, 0.306708008050919f, + 0.895115137100220f, 0.306405037641525f, 0.895349979400635f, 0.306101888418198f, + 0.895584642887115f, 0.305798590183258f, 0.895819067955017f, 0.305495083332062f, + 0.896053314208984f, 0.305191397666931f, 0.896287262439728f, 0.304887533187866f, + 0.896520972251892f, 0.304583519697189f, 0.896754503250122f, 0.304279297590256f, + 0.896987736225128f, 0.303974896669388f, 0.897220790386200f, 0.303670316934586f, + 0.897453546524048f, 0.303365558385849f, 0.897686123847961f, 0.303060621023178f, + 0.897918462753296f, 0.302755534648895f, 0.898150563240051f, 0.302450239658356f, + 0.898382425308228f, 0.302144765853882f, 0.898614048957825f, 0.301839113235474f, + 0.898845434188843f, 0.301533311605453f, 0.899076581001282f, 0.301227301359177f, + 0.899307489395142f, 0.300921112298965f, 0.899538159370422f, 0.300614774227142f, + 0.899768650531769f, 0.300308227539063f, 0.899998843669891f, 0.300001531839371f, + 0.900228857994080f, 0.299694657325745f, 0.900458574295044f, 0.299387603998184f, + 0.900688111782074f, 0.299080342054367f, 0.900917351245880f, 0.298772931098938f, + 0.901146411895752f, 0.298465341329575f, 0.901375174522400f, 0.298157602548599f, + 0.901603758335114f, 0.297849655151367f, 0.901832103729248f, 0.297541528940201f, + 0.902060210704803f, 0.297233253717422f, 0.902288019657135f, 0.296924799680710f, + 0.902515649795532f, 0.296616137027740f, 0.902743041515350f, 0.296307325363159f, + 0.902970194816589f, 0.295998334884644f, 0.903197109699249f, 0.295689195394516f, + 0.903423786163330f, 0.295379847288132f, 0.903650224208832f, 0.295070350170136f, + 0.903876423835754f, 0.294760644435883f, 0.904102385044098f, 0.294450789690018f, + 0.904328107833862f, 0.294140785932541f, 0.904553592205048f, 0.293830573558807f, + 0.904778838157654f, 0.293520182371140f, 0.905003845691681f, 0.293209642171860f, + 0.905228614807129f, 0.292898923158646f, 0.905453145503998f, 0.292588025331497f, + 0.905677437782288f, 0.292276978492737f, 0.905901491641998f, 0.291965723037720f, + 0.906125307083130f, 0.291654318571091f, 0.906348884105682f, 0.291342735290527f, + 0.906572222709656f, 0.291031002998352f, 0.906795322895050f, 0.290719062089920f, + 0.907018184661865f, 0.290406972169876f, 0.907240808010101f, 0.290094703435898f, + 0.907463192939758f, 0.289782285690308f, 0.907685279846191f, 0.289469659328461f, + 0.907907187938690f, 0.289156883955002f, 0.908128857612610f, 0.288843959569931f, + 0.908350288867950f, 0.288530826568604f, 0.908571481704712f, 0.288217544555664f, + 0.908792436122894f, 0.287904083728790f, 0.909013092517853f, 0.287590473890305f, + 0.909233570098877f, 0.287276685237885f, 0.909453809261322f, 0.286962717771530f, + 0.909673750400543f, 0.286648571491241f, 0.909893512725830f, 0.286334276199341f, + 0.910112977027893f, 0.286019802093506f, 0.910332262516022f, 0.285705178976059f, + 0.910551249980927f, 0.285390377044678f, 0.910769999027252f, 0.285075396299362f, + 0.910988569259644f, 0.284760266542435f, 0.911206841468811f, 0.284444957971573f, + 0.911424875259399f, 0.284129470586777f, 0.911642670631409f, 0.283813834190369f, + 0.911860227584839f, 0.283498018980026f, 0.912077546119690f, 0.283182054758072f, + 0.912294626235962f, 0.282865911722183f, 0.912511467933655f, 0.282549589872360f, + 0.912728071212769f, 0.282233119010925f, 0.912944436073303f, 0.281916469335556f, + 0.913160502910614f, 0.281599670648575f, 0.913376390933990f, 0.281282693147659f, + 0.913592040538788f, 0.280965566635132f, 0.913807392120361f, 0.280648261308670f, + 0.914022505283356f, 0.280330777168274f, 0.914237439632416f, 0.280013144016266f, + 0.914452075958252f, 0.279695361852646f, 0.914666473865509f, 0.279377400875092f, + 0.914880633354187f, 0.279059261083603f, 0.915094554424286f, 0.278740972280502f, + 0.915308177471161f, 0.278422504663467f, 0.915521621704102f, 0.278103888034821f, + 0.915734827518463f, 0.277785122394562f, 0.915947735309601f, 0.277466177940369f, + 0.916160404682159f, 0.277147054672241f, 0.916372895240784f, 0.276827782392502f, + 0.916585087776184f, 0.276508361101151f, 0.916797041893005f, 0.276188760995865f, + 0.917008757591248f, 0.275868982076645f, 0.917220234870911f, 0.275549083948135f, + 0.917431414127350f, 0.275228977203369f, 0.917642414569855f, 0.274908751249313f, + 0.917853116989136f, 0.274588316679001f, 0.918063640594482f, 0.274267762899399f, + 0.918273866176605f, 0.273947030305862f, 0.918483853340149f, 0.273626148700714f, + 0.918693602085114f, 0.273305088281631f, 0.918903112411499f, 0.272983878850937f, + 0.919112324714661f, 0.272662490606308f, 0.919321358203888f, 0.272340953350067f, + 0.919530093669891f, 0.272019267082214f, 0.919738650321960f, 0.271697402000427f, + 0.919946908950806f, 0.271375387907028f, 0.920154929161072f, 0.271053224802017f, + 0.920362710952759f, 0.270730882883072f, 0.920570194721222f, 0.270408391952515f, + 0.920777499675751f, 0.270085722208023f, 0.920984506607056f, 0.269762933254242f, + 0.921191275119781f, 0.269439965486526f, 0.921397805213928f, 0.269116818904877f, + 0.921604096889496f, 0.268793523311615f, 0.921810150146484f, 0.268470078706741f, + 0.922015964984894f, 0.268146485090256f, 0.922221481800079f, 0.267822742462158f, + 0.922426760196686f, 0.267498821020126f, 0.922631800174713f, 0.267174720764160f, + 0.922836601734161f, 0.266850501298904f, 0.923041164875031f, 0.266526103019714f, + 0.923245489597321f, 0.266201555728912f, 0.923449516296387f, 0.265876859426498f, + 0.923653304576874f, 0.265552014112473f, 0.923856854438782f, 0.265226989984512f, + 0.924060165882111f, 0.264901816844940f, 0.924263238906860f, 0.264576494693756f, + 0.924466013908386f, 0.264250993728638f, 0.924668610095978f, 0.263925373554230f, + 0.924870908260345f, 0.263599574565887f, 0.925072908401489f, 0.263273626565933f, + 0.925274729728699f, 0.262947499752045f, 0.925476312637329f, 0.262621253728867f, + 0.925677597522736f, 0.262294828891754f, 0.925878643989563f, 0.261968284845352f, + 0.926079452037811f, 0.261641561985016f, 0.926280021667480f, 0.261314690113068f, + 0.926480293273926f, 0.260987639427185f, 0.926680326461792f, 0.260660469532013f, + 0.926880121231079f, 0.260333120822906f, 0.927079677581787f, 0.260005623102188f, + 0.927278995513916f, 0.259678006172180f, 0.927478015422821f, 0.259350210428238f, + 0.927676856517792f, 0.259022265672684f, 0.927875399589539f, 0.258694142103195f, + 0.928073644638062f, 0.258365899324417f, 0.928271710872650f, 0.258037507534027f, + 0.928469479084015f, 0.257708936929703f, 0.928667008876801f, 0.257380217313766f, + 0.928864300251007f, 0.257051378488541f, 0.929061353206635f, 0.256722360849380f, + 0.929258108139038f, 0.256393194198608f, 0.929454624652863f, 0.256063878536224f, + 0.929650902748108f, 0.255734413862228f, 0.929846942424774f, 0.255404800176620f, + 0.930042684078217f, 0.255075037479401f, 0.930238187313080f, 0.254745125770569f, + 0.930433452129364f, 0.254415065050125f, 0.930628478527069f, 0.254084855318069f, + 0.930823206901550f, 0.253754496574402f, 0.931017756462097f, 0.253423988819122f, + 0.931211948394775f, 0.253093332052231f, 0.931405961513519f, 0.252762526273727f, + 0.931599736213684f, 0.252431541681290f, 0.931793212890625f, 0.252100437879562f, + 0.931986451148987f, 0.251769185066223f, 0.932179391384125f, 0.251437783241272f, + 0.932372152805328f, 0.251106232404709f, 0.932564616203308f, 0.250774532556534f, + 0.932756841182709f, 0.250442683696747f, 0.932948768138886f, 0.250110685825348f, + 0.933140456676483f, 0.249778553843498f, 0.933331906795502f, 0.249446272850037f, + 0.933523118495941f, 0.249113827943802f, 0.933714091777802f, 0.248781248927116f, + 0.933904767036438f, 0.248448520898819f, 0.934095203876495f, 0.248115643858910f, + 0.934285342693329f, 0.247782632708550f, 0.934475243091583f, 0.247449472546577f, + 0.934664964675903f, 0.247116148471832f, 0.934854328632355f, 0.246782705187798f, + 0.935043513774872f, 0.246449097990990f, 0.935232400894165f, 0.246115356683731f, + 0.935421049594879f, 0.245781451463699f, 0.935609400272369f, 0.245447427034378f, + 0.935797572135925f, 0.245113238692284f, 0.935985386371613f, 0.244778916239738f, + 0.936173021793365f, 0.244444444775581f, 0.936360359191895f, 0.244109839200974f, + 0.936547517776489f, 0.243775084614754f, 0.936734318733215f, 0.243440181016922f, + 0.936920940876007f, 0.243105143308640f, 0.937107264995575f, 0.242769956588745f, + 0.937293350696564f, 0.242434620857239f, 0.937479138374329f, 0.242099151015282f, + 0.937664687633514f, 0.241763532161713f, 0.937849998474121f, 0.241427779197693f, + 0.938035070896149f, 0.241091892123222f, 0.938219845294952f, 0.240755841135979f, + 0.938404381275177f, 0.240419670939446f, 0.938588619232178f, 0.240083336830139f, + 0.938772618770599f, 0.239746883511543f, 0.938956379890442f, 0.239410281181335f, + 0.939139902591705f, 0.239073529839516f, 0.939323127269745f, 0.238736644387245f, + 0.939506113529205f, 0.238399609923363f, 0.939688861370087f, 0.238062441349030f, + 0.939871311187744f, 0.237725138664246f, 0.940053522586823f, 0.237387686967850f, + 0.940235435962677f, 0.237050101161003f, 0.940417110919952f, 0.236712381243706f, + 0.940598547458649f, 0.236374512314796f, 0.940779745578766f, 0.236036509275436f, + 0.940960645675659f, 0.235698372125626f, 0.941141307353973f, 0.235360085964203f, + 0.941321671009064f, 0.235021665692329f, 0.941501796245575f, 0.234683111310005f, + 0.941681683063507f, 0.234344407916069f, 0.941861271858215f, 0.234005570411682f, + 0.942040622234344f, 0.233666598796844f, 0.942219734191895f, 0.233327493071556f, + 0.942398548126221f, 0.232988253235817f, 0.942577123641968f, 0.232648864388466f, + 0.942755401134491f, 0.232309341430664f, 0.942933499813080f, 0.231969684362412f, + 0.943111240863800f, 0.231629893183708f, 0.943288803100586f, 0.231289967894554f, + 0.943466067314148f, 0.230949893593788f, 0.943643093109131f, 0.230609700083733f, + 0.943819820880890f, 0.230269357562065f, 0.943996310234070f, 0.229928880929947f, + 0.944172501564026f, 0.229588270187378f, 0.944348454475403f, 0.229247525334358f, + 0.944524168968201f, 0.228906646370888f, 0.944699645042419f, 0.228565633296967f, + 0.944874763488770f, 0.228224486112595f, 0.945049703121185f, 0.227883204817772f, + 0.945224344730377f, 0.227541789412498f, 0.945398747920990f, 0.227200239896774f, + 0.945572853088379f, 0.226858556270599f, 0.945746779441834f, 0.226516738533974f, + 0.945920348167419f, 0.226174786686897f, 0.946093678474426f, 0.225832715630531f, + 0.946266770362854f, 0.225490495562553f, 0.946439623832703f, 0.225148141384125f, + 0.946612179279327f, 0.224805667996407f, 0.946784436702728f, 0.224463045597076f, + 0.946956455707550f, 0.224120303988457f, 0.947128236293793f, 0.223777428269386f, + 0.947299718856812f, 0.223434418439865f, 0.947470963001251f, 0.223091274499893f, + 0.947641968727112f, 0.222748011350632f, 0.947812676429749f, 0.222404599189758f, + 0.947983145713806f, 0.222061067819595f, 0.948153316974640f, 0.221717402338982f, + 0.948323249816895f, 0.221373617649078f, 0.948492884635925f, 0.221029683947563f, + 0.948662281036377f, 0.220685631036758f, 0.948831439018250f, 0.220341444015503f, + 0.949000298976898f, 0.219997137784958f, 0.949168920516968f, 0.219652697443962f, + 0.949337244033813f, 0.219308122992516f, 0.949505329132080f, 0.218963414430618f, + 0.949673116207123f, 0.218618586659431f, 0.949840664863586f, 0.218273624777794f, + 0.950007975101471f, 0.217928543686867f, 0.950174987316132f, 0.217583328485489f, + 0.950341701507568f, 0.217237979173660f, 0.950508177280426f, 0.216892510652542f, + 0.950674414634705f, 0.216546908020973f, 0.950840353965759f, 0.216201186180115f, + 0.951006054878235f, 0.215855330228806f, 0.951171517372131f, 0.215509355068207f, + 0.951336681842804f, 0.215163245797157f, 0.951501548290253f, 0.214817002415657f, + 0.951666176319122f, 0.214470639824867f, 0.951830565929413f, 0.214124158024788f, + 0.951994657516479f, 0.213777542114258f, 0.952158451080322f, 0.213430806994438f, + 0.952322065830231f, 0.213083937764168f, 0.952485322952271f, 0.212736949324608f, + 0.952648401260376f, 0.212389841675758f, 0.952811121940613f, 0.212042599916458f, + 0.952973663806915f, 0.211695238947868f, 0.953135907649994f, 0.211347743868828f, + 0.953297853469849f, 0.211000129580498f, 0.953459560871124f, 0.210652396082878f, + 0.953620970249176f, 0.210304543375969f, 0.953782141208649f, 0.209956556558609f, + 0.953943073749542f, 0.209608450531960f, 0.954103708267212f, 0.209260210394859f, + 0.954264044761658f, 0.208911851048470f, 0.954424142837524f, 0.208563387393951f, + 0.954584002494812f, 0.208214774727821f, 0.954743564128876f, 0.207866057753563f, + 0.954902827739716f, 0.207517206668854f, 0.955061912536621f, 0.207168251276016f, + 0.955220639705658f, 0.206819161772728f, 0.955379128456116f, 0.206469938158989f, + 0.955537378787994f, 0.206120610237122f, 0.955695331096649f, 0.205771163105965f, + 0.955853044986725f, 0.205421581864357f, 0.956010460853577f, 0.205071896314621f, + 0.956167578697205f, 0.204722076654434f, 0.956324458122253f, 0.204372137784958f, + 0.956481099128723f, 0.204022079706192f, 0.956637442111969f, 0.203671902418137f, + 0.956793546676636f, 0.203321605920792f, 0.956949353218079f, 0.202971190214157f, + 0.957104861736298f, 0.202620655298233f, 0.957260131835938f, 0.202270001173019f, + 0.957415163516998f, 0.201919227838516f, 0.957569897174835f, 0.201568335294724f, + 0.957724332809448f, 0.201217323541641f, 0.957878530025482f, 0.200866192579269f, + 0.958032488822937f, 0.200514942407608f, 0.958186149597168f, 0.200163587927818f, + 0.958339512348175f, 0.199812099337578f, 0.958492636680603f, 0.199460506439209f, + 0.958645522594452f, 0.199108779430389f, 0.958798050880432f, 0.198756948113441f, + 0.958950400352478f, 0.198404997587204f, 0.959102451801300f, 0.198052927851677f, + 0.959254205226898f, 0.197700738906860f, 0.959405720233917f, 0.197348430752754f, + 0.959556937217712f, 0.196996018290520f, 0.959707856178284f, 0.196643486618996f, + 0.959858596324921f, 0.196290835738182f, 0.960008978843689f, 0.195938065648079f, + 0.960159122943878f, 0.195585191249847f, 0.960309028625488f, 0.195232197642326f, + 0.960458636283875f, 0.194879084825516f, 0.960607945919037f, 0.194525867700577f, + 0.960757017135620f, 0.194172516465187f, 0.960905790328979f, 0.193819075822830f, + 0.961054325103760f, 0.193465501070023f, 0.961202561855316f, 0.193111822009087f, + 0.961350560188293f, 0.192758023738861f, 0.961498260498047f, 0.192404121160507f, + 0.961645722389221f, 0.192050099372864f, 0.961792886257172f, 0.191695958375931f, + 0.961939752101898f, 0.191341713070869f, 0.962086379528046f, 0.190987363457680f, + 0.962232708930969f, 0.190632879734039f, 0.962378799915314f, 0.190278306603432f, + 0.962524592876434f, 0.189923599362373f, 0.962670147418976f, 0.189568802714348f, + 0.962815403938293f, 0.189213871955872f, 0.962960422039032f, 0.188858851790428f, + 0.963105142116547f, 0.188503712415695f, 0.963249564170837f, 0.188148453831673f, + 0.963393747806549f, 0.187793090939522f, 0.963537633419037f, 0.187437608838081f, + 0.963681280612946f, 0.187082037329674f, 0.963824629783630f, 0.186726331710815f, + 0.963967680931091f, 0.186370536684990f, 0.964110493659973f, 0.186014622449875f, + 0.964253067970276f, 0.185658603906631f, 0.964395284652710f, 0.185302466154099f, + 0.964537262916565f, 0.184946224093437f, 0.964679002761841f, 0.184589877724648f, + 0.964820444583893f, 0.184233412146568f, 0.964961588382721f, 0.183876842260361f, + 0.965102493762970f, 0.183520168066025f, 0.965243160724640f, 0.183163389563560f, + 0.965383470058441f, 0.182806491851807f, 0.965523540973663f, 0.182449504733086f, + 0.965663373470306f, 0.182092398405075f, 0.965802907943726f, 0.181735187768936f, + 0.965942144393921f, 0.181377857923508f, 0.966081082820892f, 0.181020438671112f, + 0.966219842433929f, 0.180662900209427f, 0.966358244419098f, 0.180305257439613f, + 0.966496407985687f, 0.179947525262833f, 0.966634273529053f, 0.179589673876762f, + 0.966771900653839f, 0.179231703281403f, 0.966909229755402f, 0.178873643279076f, + 0.967046260833740f, 0.178515478968620f, 0.967183053493500f, 0.178157210350037f, + 0.967319548130035f, 0.177798837423325f, 0.967455804347992f, 0.177440345287323f, + 0.967591762542725f, 0.177081763744354f, 0.967727422714233f, 0.176723077893257f, + 0.967862844467163f, 0.176364272832870f, 0.967997968196869f, 0.176005378365517f, + 0.968132853507996f, 0.175646379590034f, 0.968267440795898f, 0.175287276506424f, + 0.968401730060577f, 0.174928069114685f, 0.968535780906677f, 0.174568757414818f, + 0.968669533729553f, 0.174209341406822f, 0.968802988529205f, 0.173849821090698f, + 0.968936204910278f, 0.173490211367607f, 0.969069123268127f, 0.173130482435226f, + 0.969201743602753f, 0.172770664095879f, 0.969334125518799f, 0.172410741448402f, + 0.969466269016266f, 0.172050714492798f, 0.969598054885864f, 0.171690583229065f, + 0.969729602336884f, 0.171330362558365f, 0.969860911369324f, 0.170970037579536f, + 0.969991862773895f, 0.170609608292580f, 0.970122575759888f, 0.170249074697495f, + 0.970253050327301f, 0.169888436794281f, 0.970383226871490f, 0.169527709484100f, + 0.970513105392456f, 0.169166877865791f, 0.970642685890198f, 0.168805956840515f, + 0.970772027969360f, 0.168444931507111f, 0.970901072025299f, 0.168083801865578f, + 0.971029877662659f, 0.167722567915916f, 0.971158385276794f, 0.167361244559288f, + 0.971286594867706f, 0.166999831795692f, 0.971414566040039f, 0.166638299822807f, + 0.971542239189148f, 0.166276678442955f, 0.971669614315033f, 0.165914967656136f, + 0.971796751022339f, 0.165553152561188f, 0.971923589706421f, 0.165191248059273f, + 0.972050130367279f, 0.164829224348068f, 0.972176432609558f, 0.164467126131058f, + 0.972302436828613f, 0.164104923605919f, 0.972428143024445f, 0.163742616772652f, + 0.972553610801697f, 0.163380220532417f, 0.972678780555725f, 0.163017734885216f, + 0.972803652286530f, 0.162655144929886f, 0.972928285598755f, 0.162292465567589f, + 0.973052620887756f, 0.161929681897163f, 0.973176658153534f, 0.161566808819771f, + 0.973300457000732f, 0.161203846335411f, 0.973423957824707f, 0.160840779542923f, + 0.973547160625458f, 0.160477623343468f, 0.973670125007629f, 0.160114362835884f, + 0.973792791366577f, 0.159751012921333f, 0.973915159702301f, 0.159387573599815f, + 0.974037289619446f, 0.159024044871330f, 0.974159121513367f, 0.158660411834717f, + 0.974280655384064f, 0.158296689391136f, 0.974401950836182f, 0.157932877540588f, + 0.974522948265076f, 0.157568961381912f, 0.974643647670746f, 0.157204970717430f, + 0.974764108657837f, 0.156840875744820f, 0.974884271621704f, 0.156476691365242f, + 0.975004136562347f, 0.156112402677536f, 0.975123703479767f, 0.155748039484024f, + 0.975243031978607f, 0.155383571982384f, 0.975362062454224f, 0.155019029974937f, + 0.975480854511261f, 0.154654383659363f, 0.975599288940430f, 0.154289647936821f, + 0.975717484951019f, 0.153924822807312f, 0.975835442543030f, 0.153559908270836f, + 0.975953042507172f, 0.153194904327393f, 0.976070404052734f, 0.152829796075821f, + 0.976187527179718f, 0.152464613318443f, 0.976304292678833f, 0.152099341154099f, + 0.976420819759369f, 0.151733979582787f, 0.976537048816681f, 0.151368513703346f, + 0.976653039455414f, 0.151002973318100f, 0.976768672466278f, 0.150637343525887f, + 0.976884067058563f, 0.150271624326706f, 0.976999223232269f, 0.149905815720558f, + 0.977114021778107f, 0.149539917707443f, 0.977228581905365f, 0.149173930287361f, + 0.977342903614044f, 0.148807853460312f, 0.977456867694855f, 0.148441687226295f, + 0.977570593357086f, 0.148075446486473f, 0.977684020996094f, 0.147709101438522f, + 0.977797150611877f, 0.147342681884766f, 0.977910041809082f, 0.146976172924042f, + 0.978022634983063f, 0.146609574556351f, 0.978134930133820f, 0.146242901682854f, + 0.978246986865997f, 0.145876124501228f, 0.978358685970306f, 0.145509272813797f, + 0.978470146656036f, 0.145142331719399f, 0.978581368923187f, 0.144775316119194f, + 0.978692233562469f, 0.144408211112022f, 0.978802859783173f, 0.144041016697884f, + 0.978913187980652f, 0.143673732876778f, 0.979023277759552f, 0.143306359648705f, + 0.979133009910584f, 0.142938911914825f, 0.979242503643036f, 0.142571389675140f, + 0.979351758956909f, 0.142203763127327f, 0.979460656642914f, 0.141836062073708f, + 0.979569315910339f, 0.141468286514282f, 0.979677677154541f, 0.141100421547890f, + 0.979785740375519f, 0.140732467174530f, 0.979893565177917f, 0.140364438295364f, + 0.980001091957092f, 0.139996320009232f, 0.980108320713043f, 0.139628127217293f, + 0.980215251445770f, 0.139259845018387f, 0.980321943759918f, 0.138891488313675f, + 0.980428338050842f, 0.138523042201996f, 0.980534434318542f, 0.138154521584511f, + 0.980640232563019f, 0.137785911560059f, 0.980745792388916f, 0.137417227029800f, + 0.980851054191589f, 0.137048453092575f, 0.980956017971039f, 0.136679604649544f, + 0.981060683727264f, 0.136310681700706f, 0.981165111064911f, 0.135941669344902f, + 0.981269240379334f, 0.135572582483292f, 0.981373071670532f, 0.135203406214714f, + 0.981476604938507f, 0.134834155440331f, 0.981579899787903f, 0.134464830160141f, + 0.981682896614075f, 0.134095430374146f, 0.981785595417023f, 0.133725941181183f, + 0.981888055801392f, 0.133356377482414f, 0.981990158557892f, 0.132986739277840f, + 0.982092022895813f, 0.132617011666298f, 0.982193589210510f, 0.132247209548950f, + 0.982294917106628f, 0.131877332925797f, 0.982395887374878f, 0.131507381796837f, + 0.982496619224548f, 0.131137356162071f, 0.982597053050995f, 0.130767241120338f, + 0.982697248458862f, 0.130397051572800f, 0.982797086238861f, 0.130026802420616f, + 0.982896685600281f, 0.129656463861465f, 0.982995986938477f, 0.129286035895348f, + 0.983094990253448f, 0.128915548324585f, 0.983193755149841f, 0.128544986248016f, + 0.983292162418365f, 0.128174334764481f, 0.983390331268311f, 0.127803623676300f, + 0.983488261699677f, 0.127432823181152f, 0.983585834503174f, 0.127061963081360f, + 0.983683168888092f, 0.126691013574600f, 0.983780145645142f, 0.126320004463196f, + 0.983876943588257f, 0.125948905944824f, 0.983973383903503f, 0.125577747821808f, + 0.984069526195526f, 0.125206500291824f, 0.984165430068970f, 0.124835193157196f, + 0.984261035919189f, 0.124463804066181f, 0.984356343746185f, 0.124092340469360f, + 0.984451413154602f, 0.123720809817314f, 0.984546124935150f, 0.123349204659462f, + 0.984640598297119f, 0.122977524995804f, 0.984734773635864f, 0.122605770826340f, + 0.984828710556030f, 0.122233949601650f, 0.984922289848328f, 0.121862053871155f, + 0.985015630722046f, 0.121490091085434f, 0.985108673572540f, 0.121118053793907f, + 0.985201418399811f, 0.120745941996574f, 0.985293865203857f, 0.120373763144016f, + 0.985386073589325f, 0.120001509785652f, 0.985477983951569f, 0.119629189372063f, + 0.985569596290588f, 0.119256794452667f, 0.985660910606384f, 0.118884332478046f, + 0.985751926898956f, 0.118511803448200f, 0.985842704772949f, 0.118139199912548f, + 0.985933184623718f, 0.117766529321671f, 0.986023366451263f, 0.117393791675568f, + 0.986113250255585f, 0.117020979523659f, 0.986202836036682f, 0.116648100316525f, + 0.986292183399200f, 0.116275154054165f, 0.986381232738495f, 0.115902140736580f, + 0.986469984054565f, 0.115529052913189f, 0.986558437347412f, 0.115155905485153f, + 0.986646652221680f, 0.114782683551311f, 0.986734509468079f, 0.114409394562244f, + 0.986822128295898f, 0.114036038517952f, 0.986909449100494f, 0.113662622869015f, + 0.986996471881866f, 0.113289132714272f, 0.987083256244659f, 0.112915575504303f, + 0.987169682979584f, 0.112541958689690f, 0.987255871295929f, 0.112168267369270f, + 0.987341761589050f, 0.111794516444206f, 0.987427353858948f, 0.111420698463917f, + 0.987512648105621f, 0.111046813428402f, 0.987597703933716f, 0.110672861337662f, + 0.987682461738586f, 0.110298842191696f, 0.987766921520233f, 0.109924763441086f, + 0.987851083278656f, 0.109550617635250f, 0.987934947013855f, 0.109176412224770f, + 0.988018512725830f, 0.108802139759064f, 0.988101840019226f, 0.108427800238132f, + 0.988184869289398f, 0.108053401112556f, 0.988267600536346f, 0.107678934931755f, + 0.988350033760071f, 0.107304409146309f, 0.988432228565216f, 0.106929816305637f, + 0.988514065742493f, 0.106555156409740f, 0.988595664501190f, 0.106180444359779f, + 0.988676965236664f, 0.105805665254593f, 0.988757967948914f, 0.105430819094181f, + 0.988838672637939f, 0.105055920779705f, 0.988919138908386f, 0.104680955410004f, + 0.988999247550964f, 0.104305922985077f, 0.989079117774963f, 0.103930838406086f, + 0.989158689975739f, 0.103555686771870f, 0.989237964153290f, 0.103180475533009f, + 0.989316940307617f, 0.102805204689503f, 0.989395678043365f, 0.102429874241352f, + 0.989474058151245f, 0.102054484188557f, 0.989552199840546f, 0.101679034531116f, + 0.989630043506622f, 0.101303517818451f, 0.989707589149475f, 0.100927948951721f, + 0.989784896373749f, 0.100552320480347f, 0.989861845970154f, 0.100176624953747f, + 0.989938557147980f, 0.099800877273083f, 0.990014970302582f, 0.099425069987774f, + 0.990091085433960f, 0.099049203097820f, 0.990166902542114f, 0.098673284053802f, + 0.990242421627045f, 0.098297297954559f, 0.990317702293396f, 0.097921259701252f, + 0.990392625331879f, 0.097545161843300f, 0.990467309951782f, 0.097169004380703f, + 0.990541696548462f, 0.096792794764042f, 0.990615785121918f, 0.096416525542736f, + 0.990689575672150f, 0.096040196716785f, 0.990763127803802f, 0.095663815736771f, + 0.990836322307587f, 0.095287375152111f, 0.990909278392792f, 0.094910882413387f, + 0.990981936454773f, 0.094534330070019f, 0.991054296493530f, 0.094157725572586f, + 0.991126358509064f, 0.093781061470509f, 0.991198182106018f, 0.093404345214367f, + 0.991269648075104f, 0.093027576804161f, 0.991340875625610f, 0.092650748789310f, + 0.991411805152893f, 0.092273868620396f, 0.991482377052307f, 0.091896936297417f, + 0.991552770137787f, 0.091519944369793f, 0.991622805595398f, 0.091142900288105f, + 0.991692543029785f, 0.090765804052353f, 0.991762042045593f, 0.090388655662537f, + 0.991831183433533f, 0.090011447668076f, 0.991900086402893f, 0.089634194970131f, + 0.991968691349030f, 0.089256882667542f, 0.992036998271942f, 0.088879525661469f, + 0.992105066776276f, 0.088502109050751f, 0.992172777652740f, 0.088124647736549f, + 0.992240250110626f, 0.087747126817703f, 0.992307364940643f, 0.087369553744793f, + 0.992374241352081f, 0.086991935968399f, 0.992440819740295f, 0.086614266037941f, + 0.992507100105286f, 0.086236543953419f, 0.992573142051697f, 0.085858769714832f, + 0.992638826370239f, 0.085480943322182f, 0.992704212665558f, 0.085103072226048f, + 0.992769360542297f, 0.084725148975849f, 0.992834210395813f, 0.084347173571587f, + 0.992898762226105f, 0.083969146013260f, 0.992963016033173f, 0.083591073751450f, + 0.993026971817017f, 0.083212949335575f, 0.993090689182281f, 0.082834780216217f, + 0.993154048919678f, 0.082456558942795f, 0.993217170238495f, 0.082078292965889f, + 0.993279933929443f, 0.081699974834919f, 0.993342459201813f, 0.081321612000465f, + 0.993404686450958f, 0.080943197011948f, 0.993466615676880f, 0.080564737319946f, + 0.993528306484222f, 0.080186225473881f, 0.993589639663696f, 0.079807676374912f, + 0.993650734424591f, 0.079429075121880f, 0.993711471557617f, 0.079050421714783f, + 0.993771970272064f, 0.078671731054783f, 0.993832170963287f, 0.078292988240719f, + 0.993892073631287f, 0.077914200723171f, 0.993951678276062f, 0.077535368502140f, + 0.994010984897614f, 0.077156484127045f, 0.994070053100586f, 0.076777562499046f, + 0.994128763675690f, 0.076398596167564f, 0.994187235832214f, 0.076019577682018f, + 0.994245409965515f, 0.075640521943569f, 0.994303286075592f, 0.075261414051056f, + 0.994360864162445f, 0.074882268905640f, 0.994418144226074f, 0.074503071606159f, + 0.994475126266479f, 0.074123837053776f, 0.994531810283661f, 0.073744557797909f, + 0.994588255882263f, 0.073365233838558f, 0.994644403457642f, 0.072985872626305f, + 0.994700193405151f, 0.072606459259987f, 0.994755744934082f, 0.072227008640766f, + 0.994810998439789f, 0.071847513318062f, 0.994865953922272f, 0.071467980742455f, + 0.994920611381531f, 0.071088403463364f, 0.994975030422211f, 0.070708781480789f, + 0.995029091835022f, 0.070329122245312f, 0.995082914829254f, 0.069949418306351f, + 0.995136380195618f, 0.069569669663906f, 0.995189607143402f, 0.069189883768559f, + 0.995242536067963f, 0.068810060620308f, 0.995295166969299f, 0.068430192768574f, + 0.995347499847412f, 0.068050287663937f, 0.995399534702301f, 0.067670337855816f, + 0.995451331138611f, 0.067290350794792f, 0.995502769947052f, 0.066910326480865f, + 0.995553970336914f, 0.066530264914036f, 0.995604813098907f, 0.066150158643723f, + 0.995655417442322f, 0.065770015120506f, 0.995705723762512f, 0.065389834344387f, + 0.995755732059479f, 0.065009608864784f, 0.995805442333221f, 0.064629353582859f, + 0.995854854583740f, 0.064249053597450f, 0.995904028415680f, 0.063868723809719f, + 0.995952844619751f, 0.063488349318504f, 0.996001422405243f, 0.063107937574387f, + 0.996049642562866f, 0.062727488577366f, 0.996097624301910f, 0.062347009778023f, + 0.996145308017731f, 0.061966486275196f, 0.996192693710327f, 0.061585929244757f, + 0.996239781379700f, 0.061205338686705f, 0.996286571025848f, 0.060824707150459f, + 0.996333062648773f, 0.060444042086601f, 0.996379256248474f, 0.060063343495131f, + 0.996425211429596f, 0.059682607650757f, 0.996470808982849f, 0.059301838278770f, + 0.996516168117523f, 0.058921031653881f, 0.996561229228973f, 0.058540191501379f, + 0.996605992317200f, 0.058159314095974f, 0.996650457382202f, 0.057778406888247f, + 0.996694624423981f, 0.057397462427616f, 0.996738493442535f, 0.057016488164663f, + 0.996782064437866f, 0.056635476648808f, 0.996825337409973f, 0.056254431605339f, + 0.996868371963501f, 0.055873356759548f, 0.996911048889160f, 0.055492244660854f, + 0.996953487396240f, 0.055111102759838f, 0.996995627880096f, 0.054729927331209f, + 0.997037410736084f, 0.054348722100258f, 0.997078955173492f, 0.053967483341694f, + 0.997120201587677f, 0.053586211055517f, 0.997161149978638f, 0.053204908967018f, + 0.997201859951019f, 0.052823577076197f, 0.997242212295532f, 0.052442211657763f, + 0.997282266616821f, 0.052060816437006f, 0.997322082519531f, 0.051679391413927f, + 0.997361540794373f, 0.051297932863235f, 0.997400760650635f, 0.050916448235512f, + 0.997439682483673f, 0.050534930080175f, 0.997478306293488f, 0.050153385847807f, + 0.997516572475433f, 0.049771808087826f, 0.997554600238800f, 0.049390204250813f, + 0.997592389583588f, 0.049008570611477f, 0.997629821300507f, 0.048626907169819f, + 0.997666954994202f, 0.048245213925838f, 0.997703790664673f, 0.047863494604826f, + 0.997740387916565f, 0.047481749206781f, 0.997776627540588f, 0.047099970281124f, + 0.997812628746033f, 0.046718169003725f, 0.997848331928253f, 0.046336337924004f, + 0.997883677482605f, 0.045954477041960f, 0.997918784618378f, 0.045572593808174f, + 0.997953593730927f, 0.045190680772066f, 0.997988104820251f, 0.044808741658926f, + 0.998022377490997f, 0.044426776468754f, 0.998056292533875f, 0.044044785201550f, + 0.998089909553528f, 0.043662767857313f, 0.998123228549957f, 0.043280724436045f, + 0.998156309127808f, 0.042898654937744f, 0.998189091682434f, 0.042516563087702f, + 0.998221516609192f, 0.042134445160627f, 0.998253703117371f, 0.041752301156521f, + 0.998285591602325f, 0.041370131075382f, 0.998317182064056f, 0.040987938642502f, + 0.998348474502563f, 0.040605723857880f, 0.998379468917847f, 0.040223482996225f, + 0.998410165309906f, 0.039841219782829f, 0.998440563678741f, 0.039458930492401f, + 0.998470664024353f, 0.039076622575521f, 0.998500525951386f, 0.038694288581610f, + 0.998530030250549f, 0.038311932235956f, 0.998559296131134f, 0.037929553538561f, + 0.998588204383850f, 0.037547148764133f, 0.998616874217987f, 0.037164725363255f, + 0.998645246028900f, 0.036782283335924f, 0.998673319816589f, 0.036399815231562f, + 0.998701035976410f, 0.036017324775457f, 0.998728513717651f, 0.035634815692902f, + 0.998755753040314f, 0.035252287983894f, 0.998782634735107f, 0.034869734197855f, + 0.998809218406677f, 0.034487165510654f, 0.998835504055023f, 0.034104570746422f, + 0.998861551284790f, 0.033721961081028f, 0.998887240886688f, 0.033339329063892f, + 0.998912692070007f, 0.032956674695015f, 0.998937785625458f, 0.032574005424976f, + 0.998962640762329f, 0.032191313803196f, 0.998987197875977f, 0.031808607280254f, + 0.999011456966400f, 0.031425878405571f, 0.999035418033600f, 0.031043132767081f, + 0.999059081077576f, 0.030660368502140f, 0.999082446098328f, 0.030277585610747f, + 0.999105513095856f, 0.029894785955548f, 0.999128282070160f, 0.029511967673898f, + 0.999150753021240f, 0.029129132628441f, 0.999172985553741f, 0.028746278956532f, + 0.999194860458374f, 0.028363410383463f, 0.999216496944427f, 0.027980525046587f, + 0.999237775802612f, 0.027597622945905f, 0.999258816242218f, 0.027214704081416f, + 0.999279558658600f, 0.026831768453121f, 0.999299943447113f, 0.026448817923665f, + 0.999320089817047f, 0.026065852493048f, 0.999339938163757f, 0.025682870298624f, + 0.999359488487244f, 0.025299875065684f, 0.999378740787506f, 0.024916863068938f, + 0.999397754669189f, 0.024533838033676f, 0.999416410923004f, 0.024150796234608f, + 0.999434769153595f, 0.023767741397023f, 0.999452829360962f, 0.023384673520923f, + 0.999470651149750f, 0.023001590743661f, 0.999488115310669f, 0.022618494927883f, + 0.999505341053009f, 0.022235386073589f, 0.999522268772125f, 0.021852264180779f, + 0.999538838863373f, 0.021469129249454f, 0.999555170536041f, 0.021085981279612f, + 0.999571204185486f, 0.020702820271254f, 0.999586939811707f, 0.020319648087025f, + 0.999602377414703f, 0.019936462864280f, 0.999617516994476f, 0.019553268328309f, + 0.999632358551025f, 0.019170060753822f, 0.999646902084351f, 0.018786842003465f, + 0.999661207199097f, 0.018403612077236f, 0.999675154685974f, 0.018020370975137f, + 0.999688863754272f, 0.017637118697166f, 0.999702215194702f, 0.017253857105970f, + 0.999715328216553f, 0.016870586201549f, 0.999728083610535f, 0.016487304121256f, + 0.999740600585938f, 0.016104012727737f, 0.999752819538116f, 0.015720712020993f, + 0.999764680862427f, 0.015337402001023f, 0.999776303768158f, 0.014954082667828f, + 0.999787628650665f, 0.014570754021406f, 0.999798655509949f, 0.014187417924404f, + 0.999809384346008f, 0.013804072514176f, 0.999819874763489f, 0.013420719653368f, + 0.999830007553101f, 0.013037359341979f, 0.999839842319489f, 0.012653990648687f, + 0.999849438667297f, 0.012270614504814f, 0.999858677387238f, 0.011887230910361f, + 0.999867618083954f, 0.011503840796649f, 0.999876320362091f, 0.011120444163680f, + 0.999884724617004f, 0.010737040080130f, 0.999892771244049f, 0.010353630408645f, + 0.999900579452515f, 0.009970214217901f, 0.999908089637756f, 0.009586792439222f, + 0.999915301799774f, 0.009203365072608f, 0.999922215938568f, 0.008819932118058f, + 0.999928832054138f, 0.008436493575573f, 0.999935150146484f, 0.008053051307797f, + 0.999941170215607f, 0.007669602986425f, 0.999946892261505f, 0.007286150939763f, + 0.999952375888824f, 0.006902694236487f, 0.999957501888275f, 0.006519233807921f, + 0.999962329864502f, 0.006135769188404f, 0.999966919422150f, 0.005752300843596f, + 0.999971151351929f, 0.005368829704821f, 0.999975144863129f, 0.004985354840755f, + 0.999978840351105f, 0.004601877182722f, 0.999982178211212f, 0.004218397196382f, + 0.999985277652740f, 0.003834914416075f, 0.999988079071045f, 0.003451429307461f, + 0.999990582466125f, 0.003067942336202f, 0.999992787837982f, 0.002684453502297f, + 0.999994695186615f, 0.002300963038579f, 0.999996304512024f, 0.001917471294291f, + 0.999997675418854f, 0.001533978385851f, 0.999998688697815f, 0.001150484546088f, + 0.999999403953552f, 0.000766990066040f, 0.999999880790710f, 0.000383495149435f, + 1.000000000000000f, 0.000000000000023f, 0.999999880790710f, -0.000383495149435f, + 0.999999403953552f, -0.000766990066040f, 0.999998688697815f, -0.001150484546088f, + 0.999997675418854f, -0.001533978385851f, 0.999996304512024f, -0.001917471294291f, + 0.999994695186615f, -0.002300963038579f, 0.999992787837982f, -0.002684453502297f, + 0.999990582466125f, -0.003067942336202f, 0.999988079071045f, -0.003451429307461f, + 0.999985277652740f, -0.003834914416075f, 0.999982178211212f, -0.004218397196382f, + 0.999978840351105f, -0.004601877182722f, 0.999975144863129f, -0.004985354840755f, + 0.999971151351929f, -0.005368829704821f, 0.999966919422150f, -0.005752300843596f, + 0.999962329864502f, -0.006135769188404f, 0.999957501888275f, -0.006519233807921f, + 0.999952375888824f, -0.006902694236487f, 0.999946892261505f, -0.007286150939763f, + 0.999941170215607f, -0.007669602986425f, 0.999935150146484f, -0.008053051307797f, + 0.999928832054138f, -0.008436493575573f, 0.999922215938568f, -0.008819932118058f, + 0.999915301799774f, -0.009203365072608f, 0.999908089637756f, -0.009586792439222f, + 0.999900579452515f, -0.009970214217901f, 0.999892771244049f, -0.010353630408645f, + 0.999884724617004f, -0.010737040080130f, 0.999876320362091f, -0.011120444163680f, + 0.999867618083954f, -0.011503840796649f, 0.999858677387238f, -0.011887230910361f, + 0.999849438667297f, -0.012270614504814f, 0.999839842319489f, -0.012653990648687f, + 0.999830007553101f, -0.013037359341979f, 0.999819874763489f, -0.013420719653368f, + 0.999809384346008f, -0.013804072514176f, 0.999798655509949f, -0.014187417924404f, + 0.999787628650665f, -0.014570754021406f, 0.999776303768158f, -0.014954082667828f, + 0.999764680862427f, -0.015337402001023f, 0.999752819538116f, -0.015720712020993f, + 0.999740600585938f, -0.016104012727737f, 0.999728083610535f, -0.016487304121256f, + 0.999715328216553f, -0.016870586201549f, 0.999702215194702f, -0.017253857105970f, + 0.999688863754272f, -0.017637118697166f, 0.999675154685974f, -0.018020370975137f, + 0.999661207199097f, -0.018403612077236f, 0.999646902084351f, -0.018786842003465f, + 0.999632358551025f, -0.019170060753822f, 0.999617516994476f, -0.019553268328309f, + 0.999602377414703f, -0.019936462864280f, 0.999586939811707f, -0.020319648087025f, + 0.999571204185486f, -0.020702820271254f, 0.999555170536041f, -0.021085981279612f, + 0.999538838863373f, -0.021469129249454f, 0.999522268772125f, -0.021852264180779f, + 0.999505341053009f, -0.022235386073589f, 0.999488115310669f, -0.022618494927883f, + 0.999470651149750f, -0.023001590743661f, 0.999452829360962f, -0.023384673520923f, + 0.999434769153595f, -0.023767741397023f, 0.999416410923004f, -0.024150796234608f, + 0.999397754669189f, -0.024533838033676f, 0.999378740787506f, -0.024916863068938f, + 0.999359488487244f, -0.025299875065684f, 0.999339938163757f, -0.025682870298624f, + 0.999320089817047f, -0.026065852493048f, 0.999299943447113f, -0.026448817923665f, + 0.999279558658600f, -0.026831768453121f, 0.999258816242218f, -0.027214704081416f, + 0.999237775802612f, -0.027597622945905f, 0.999216496944427f, -0.027980525046587f, + 0.999194860458374f, -0.028363410383463f, 0.999172985553741f, -0.028746278956532f, + 0.999150753021240f, -0.029129132628441f, 0.999128282070160f, -0.029511967673898f, + 0.999105513095856f, -0.029894785955548f, 0.999082446098328f, -0.030277585610747f, + 0.999059081077576f, -0.030660368502140f, 0.999035418033600f, -0.031043132767081f, + 0.999011456966400f, -0.031425878405571f, 0.998987197875977f, -0.031808607280254f, + 0.998962640762329f, -0.032191313803196f, 0.998937785625458f, -0.032574005424976f, + 0.998912692070007f, -0.032956674695015f, 0.998887240886688f, -0.033339329063892f, + 0.998861551284790f, -0.033721961081028f, 0.998835504055023f, -0.034104570746422f, + 0.998809218406677f, -0.034487165510654f, 0.998782634735107f, -0.034869734197855f, + 0.998755753040314f, -0.035252287983894f, 0.998728513717651f, -0.035634815692902f, + 0.998701035976410f, -0.036017324775457f, 0.998673319816589f, -0.036399815231562f, + 0.998645246028900f, -0.036782283335924f, 0.998616874217987f, -0.037164725363255f, + 0.998588204383850f, -0.037547148764133f, 0.998559296131134f, -0.037929553538561f, + 0.998530030250549f, -0.038311932235956f, 0.998500525951386f, -0.038694288581610f, + 0.998470664024353f, -0.039076622575521f, 0.998440563678741f, -0.039458930492401f, + 0.998410165309906f, -0.039841219782829f, 0.998379468917847f, -0.040223482996225f, + 0.998348474502563f, -0.040605723857880f, 0.998317182064056f, -0.040987938642502f, + 0.998285591602325f, -0.041370131075382f, 0.998253703117371f, -0.041752301156521f, + 0.998221516609192f, -0.042134445160627f, 0.998189091682434f, -0.042516563087702f, + 0.998156309127808f, -0.042898654937744f, 0.998123228549957f, -0.043280724436045f, + 0.998089909553528f, -0.043662767857313f, 0.998056292533875f, -0.044044785201550f, + 0.998022377490997f, -0.044426776468754f, 0.997988104820251f, -0.044808741658926f, + 0.997953593730927f, -0.045190680772066f, 0.997918784618378f, -0.045572593808174f, + 0.997883677482605f, -0.045954477041960f, 0.997848331928253f, -0.046336337924004f, + 0.997812628746033f, -0.046718169003725f, 0.997776627540588f, -0.047099970281124f, + 0.997740387916565f, -0.047481749206781f, 0.997703790664673f, -0.047863494604826f, + 0.997666954994202f, -0.048245213925838f, 0.997629821300507f, -0.048626907169819f, + 0.997592389583588f, -0.049008570611477f, 0.997554600238800f, -0.049390204250813f, + 0.997516572475433f, -0.049771808087826f, 0.997478306293488f, -0.050153385847807f, + 0.997439682483673f, -0.050534930080175f, 0.997400760650635f, -0.050916448235512f, + 0.997361540794373f, -0.051297932863235f, 0.997322082519531f, -0.051679391413927f, + 0.997282266616821f, -0.052060816437006f, 0.997242212295532f, -0.052442211657763f, + 0.997201859951019f, -0.052823577076197f, 0.997161149978638f, -0.053204908967018f, + 0.997120201587677f, -0.053586211055517f, 0.997078955173492f, -0.053967483341694f, + 0.997037410736084f, -0.054348722100258f, 0.996995627880096f, -0.054729927331209f, + 0.996953487396240f, -0.055111102759838f, 0.996911048889160f, -0.055492244660854f, + 0.996868371963501f, -0.055873356759548f, 0.996825337409973f, -0.056254431605339f, + 0.996782064437866f, -0.056635476648808f, 0.996738493442535f, -0.057016488164663f, + 0.996694624423981f, -0.057397462427616f, 0.996650457382202f, -0.057778406888247f, + 0.996605992317200f, -0.058159314095974f, 0.996561229228973f, -0.058540191501379f, + 0.996516168117523f, -0.058921031653881f, 0.996470808982849f, -0.059301838278770f, + 0.996425211429596f, -0.059682607650757f, 0.996379256248474f, -0.060063343495131f, + 0.996333062648773f, -0.060444042086601f, 0.996286571025848f, -0.060824707150459f, + 0.996239781379700f, -0.061205338686705f, 0.996192693710327f, -0.061585929244757f, + 0.996145308017731f, -0.061966486275196f, 0.996097624301910f, -0.062347009778023f, + 0.996049642562866f, -0.062727488577366f, 0.996001422405243f, -0.063107937574387f, + 0.995952844619751f, -0.063488349318504f, 0.995904028415680f, -0.063868723809719f, + 0.995854854583740f, -0.064249053597450f, 0.995805442333221f, -0.064629353582859f, + 0.995755732059479f, -0.065009608864784f, 0.995705723762512f, -0.065389834344387f, + 0.995655417442322f, -0.065770015120506f, 0.995604813098907f, -0.066150158643723f, + 0.995553970336914f, -0.066530264914036f, 0.995502769947052f, -0.066910326480865f, + 0.995451331138611f, -0.067290350794792f, 0.995399534702301f, -0.067670337855816f, + 0.995347499847412f, -0.068050287663937f, 0.995295166969299f, -0.068430192768574f, + 0.995242536067963f, -0.068810060620308f, 0.995189607143402f, -0.069189883768559f, + 0.995136380195618f, -0.069569669663906f, 0.995082914829254f, -0.069949418306351f, + 0.995029091835022f, -0.070329122245312f, 0.994975030422211f, -0.070708781480789f, + 0.994920611381531f, -0.071088403463364f, 0.994865953922272f, -0.071467980742455f, + 0.994810998439789f, -0.071847513318062f, 0.994755744934082f, -0.072227008640766f, + 0.994700193405151f, -0.072606459259987f, 0.994644403457642f, -0.072985872626305f, + 0.994588255882263f, -0.073365233838558f, 0.994531810283661f, -0.073744557797909f, + 0.994475126266479f, -0.074123837053776f, 0.994418144226074f, -0.074503071606159f, + 0.994360864162445f, -0.074882268905640f, 0.994303286075592f, -0.075261414051056f, + 0.994245409965515f, -0.075640521943569f, 0.994187235832214f, -0.076019577682018f, + 0.994128763675690f, -0.076398596167564f, 0.994070053100586f, -0.076777562499046f, + 0.994010984897614f, -0.077156484127045f, 0.993951678276062f, -0.077535368502140f, + 0.993892073631287f, -0.077914200723171f, 0.993832170963287f, -0.078292988240719f, + 0.993771970272064f, -0.078671731054783f, 0.993711471557617f, -0.079050421714783f, + 0.993650734424591f, -0.079429075121880f, 0.993589639663696f, -0.079807676374912f, + 0.993528306484222f, -0.080186225473881f, 0.993466615676880f, -0.080564737319946f, + 0.993404686450958f, -0.080943197011948f, 0.993342459201813f, -0.081321612000465f, + 0.993279933929443f, -0.081699974834919f, 0.993217170238495f, -0.082078292965889f, + 0.993154048919678f, -0.082456558942795f, 0.993090689182281f, -0.082834780216217f, + 0.993026971817017f, -0.083212949335575f, 0.992963016033173f, -0.083591073751450f, + 0.992898762226105f, -0.083969146013260f, 0.992834210395813f, -0.084347173571587f, + 0.992769360542297f, -0.084725148975849f, 0.992704212665558f, -0.085103072226048f, + 0.992638826370239f, -0.085480943322182f, 0.992573142051697f, -0.085858769714832f, + 0.992507100105286f, -0.086236543953419f, 0.992440819740295f, -0.086614266037941f, + 0.992374241352081f, -0.086991935968399f, 0.992307364940643f, -0.087369553744793f, + 0.992240250110626f, -0.087747126817703f, 0.992172777652740f, -0.088124647736549f, + 0.992105066776276f, -0.088502109050751f, 0.992036998271942f, -0.088879525661469f, + 0.991968691349030f, -0.089256882667542f, 0.991900086402893f, -0.089634194970131f, + 0.991831183433533f, -0.090011447668076f, 0.991762042045593f, -0.090388655662537f, + 0.991692543029785f, -0.090765804052353f, 0.991622805595398f, -0.091142900288105f, + 0.991552770137787f, -0.091519944369793f, 0.991482377052307f, -0.091896936297417f, + 0.991411805152893f, -0.092273868620396f, 0.991340875625610f, -0.092650748789310f, + 0.991269648075104f, -0.093027576804161f, 0.991198182106018f, -0.093404345214367f, + 0.991126358509064f, -0.093781061470509f, 0.991054296493530f, -0.094157725572586f, + 0.990981936454773f, -0.094534330070019f, 0.990909278392792f, -0.094910882413387f, + 0.990836322307587f, -0.095287375152111f, 0.990763127803802f, -0.095663815736771f, + 0.990689575672150f, -0.096040196716785f, 0.990615785121918f, -0.096416525542736f, + 0.990541696548462f, -0.096792794764042f, 0.990467309951782f, -0.097169004380703f, + 0.990392625331879f, -0.097545161843300f, 0.990317702293396f, -0.097921259701252f, + 0.990242421627045f, -0.098297297954559f, 0.990166902542114f, -0.098673284053802f, + 0.990091085433960f, -0.099049203097820f, 0.990014970302582f, -0.099425069987774f, + 0.989938557147980f, -0.099800877273083f, 0.989861845970154f, -0.100176624953747f, + 0.989784896373749f, -0.100552320480347f, 0.989707589149475f, -0.100927948951721f, + 0.989630043506622f, -0.101303517818451f, 0.989552199840546f, -0.101679034531116f, + 0.989474058151245f, -0.102054484188557f, 0.989395678043365f, -0.102429874241352f, + 0.989316940307617f, -0.102805204689503f, 0.989237964153290f, -0.103180475533009f, + 0.989158689975739f, -0.103555686771870f, 0.989079117774963f, -0.103930838406086f, + 0.988999247550964f, -0.104305922985077f, 0.988919138908386f, -0.104680955410004f, + 0.988838672637939f, -0.105055920779705f, 0.988757967948914f, -0.105430819094181f, + 0.988676965236664f, -0.105805665254593f, 0.988595664501190f, -0.106180444359779f, + 0.988514065742493f, -0.106555156409740f, 0.988432228565216f, -0.106929816305637f, + 0.988350033760071f, -0.107304409146309f, 0.988267600536346f, -0.107678934931755f, + 0.988184869289398f, -0.108053401112556f, 0.988101840019226f, -0.108427800238132f, + 0.988018512725830f, -0.108802139759064f, 0.987934947013855f, -0.109176412224770f, + 0.987851083278656f, -0.109550617635250f, 0.987766921520233f, -0.109924763441086f, + 0.987682461738586f, -0.110298842191696f, 0.987597703933716f, -0.110672861337662f, + 0.987512648105621f, -0.111046813428402f, 0.987427353858948f, -0.111420698463917f, + 0.987341761589050f, -0.111794516444206f, 0.987255871295929f, -0.112168267369270f, + 0.987169682979584f, -0.112541958689690f, 0.987083256244659f, -0.112915575504303f, + 0.986996471881866f, -0.113289132714272f, 0.986909449100494f, -0.113662622869015f, + 0.986822128295898f, -0.114036038517952f, 0.986734509468079f, -0.114409394562244f, + 0.986646652221680f, -0.114782683551311f, 0.986558437347412f, -0.115155905485153f, + 0.986469984054565f, -0.115529052913189f, 0.986381232738495f, -0.115902140736580f, + 0.986292183399200f, -0.116275154054165f, 0.986202836036682f, -0.116648100316525f, + 0.986113250255585f, -0.117020979523659f, 0.986023366451263f, -0.117393791675568f, + 0.985933184623718f, -0.117766529321671f, 0.985842704772949f, -0.118139199912548f, + 0.985751926898956f, -0.118511803448200f, 0.985660910606384f, -0.118884332478046f, + 0.985569596290588f, -0.119256794452667f, 0.985477983951569f, -0.119629189372063f, + 0.985386073589325f, -0.120001509785652f, 0.985293865203857f, -0.120373763144016f, + 0.985201418399811f, -0.120745941996574f, 0.985108673572540f, -0.121118053793907f, + 0.985015630722046f, -0.121490091085434f, 0.984922289848328f, -0.121862053871155f, + 0.984828710556030f, -0.122233949601650f, 0.984734773635864f, -0.122605770826340f, + 0.984640598297119f, -0.122977524995804f, 0.984546124935150f, -0.123349204659462f, + 0.984451413154602f, -0.123720809817314f, 0.984356343746185f, -0.124092340469360f, + 0.984261035919189f, -0.124463804066181f, 0.984165430068970f, -0.124835193157196f, + 0.984069526195526f, -0.125206500291824f, 0.983973383903503f, -0.125577747821808f, + 0.983876943588257f, -0.125948905944824f, 0.983780145645142f, -0.126320004463196f, + 0.983683168888092f, -0.126691013574600f, 0.983585834503174f, -0.127061963081360f, + 0.983488261699677f, -0.127432823181152f, 0.983390331268311f, -0.127803623676300f, + 0.983292162418365f, -0.128174334764481f, 0.983193755149841f, -0.128544986248016f, + 0.983094990253448f, -0.128915548324585f, 0.982995986938477f, -0.129286035895348f, + 0.982896685600281f, -0.129656463861465f, 0.982797086238861f, -0.130026802420616f, + 0.982697248458862f, -0.130397051572800f, 0.982597053050995f, -0.130767241120338f, + 0.982496619224548f, -0.131137356162071f, 0.982395887374878f, -0.131507381796837f, + 0.982294917106628f, -0.131877332925797f, 0.982193589210510f, -0.132247209548950f, + 0.982092022895813f, -0.132617011666298f, 0.981990158557892f, -0.132986739277840f, + 0.981888055801392f, -0.133356377482414f, 0.981785595417023f, -0.133725941181183f, + 0.981682896614075f, -0.134095430374146f, 0.981579899787903f, -0.134464830160141f, + 0.981476604938507f, -0.134834155440331f, 0.981373071670532f, -0.135203406214714f, + 0.981269240379334f, -0.135572582483292f, 0.981165111064911f, -0.135941669344902f, + 0.981060683727264f, -0.136310681700706f, 0.980956017971039f, -0.136679604649544f, + 0.980851054191589f, -0.137048453092575f, 0.980745792388916f, -0.137417227029800f, + 0.980640232563019f, -0.137785911560059f, 0.980534434318542f, -0.138154521584511f, + 0.980428338050842f, -0.138523042201996f, 0.980321943759918f, -0.138891488313675f, + 0.980215251445770f, -0.139259845018387f, 0.980108320713043f, -0.139628127217293f, + 0.980001091957092f, -0.139996320009232f, 0.979893565177917f, -0.140364438295364f, + 0.979785740375519f, -0.140732467174530f, 0.979677677154541f, -0.141100421547890f, + 0.979569315910339f, -0.141468286514282f, 0.979460656642914f, -0.141836062073708f, + 0.979351758956909f, -0.142203763127327f, 0.979242503643036f, -0.142571389675140f, + 0.979133009910584f, -0.142938911914825f, 0.979023277759552f, -0.143306359648705f, + 0.978913187980652f, -0.143673732876778f, 0.978802859783173f, -0.144041016697884f, + 0.978692233562469f, -0.144408211112022f, 0.978581368923187f, -0.144775316119194f, + 0.978470146656036f, -0.145142331719399f, 0.978358685970306f, -0.145509272813797f, + 0.978246986865997f, -0.145876124501228f, 0.978134930133820f, -0.146242901682854f, + 0.978022634983063f, -0.146609574556351f, 0.977910041809082f, -0.146976172924042f, + 0.977797150611877f, -0.147342681884766f, 0.977684020996094f, -0.147709101438522f, + 0.977570593357086f, -0.148075446486473f, 0.977456867694855f, -0.148441687226295f, + 0.977342903614044f, -0.148807853460312f, 0.977228581905365f, -0.149173930287361f, + 0.977114021778107f, -0.149539917707443f, 0.976999223232269f, -0.149905815720558f, + 0.976884067058563f, -0.150271624326706f, 0.976768672466278f, -0.150637343525887f, + 0.976653039455414f, -0.151002973318100f, 0.976537048816681f, -0.151368513703346f, + 0.976420819759369f, -0.151733979582787f, 0.976304292678833f, -0.152099341154099f, + 0.976187527179718f, -0.152464613318443f, 0.976070404052734f, -0.152829796075821f, + 0.975953042507172f, -0.153194904327393f, 0.975835442543030f, -0.153559908270836f, + 0.975717484951019f, -0.153924822807312f, 0.975599288940430f, -0.154289647936821f, + 0.975480854511261f, -0.154654383659363f, 0.975362062454224f, -0.155019029974937f, + 0.975243031978607f, -0.155383571982384f, 0.975123703479767f, -0.155748039484024f, + 0.975004136562347f, -0.156112402677536f, 0.974884271621704f, -0.156476691365242f, + 0.974764108657837f, -0.156840875744820f, 0.974643647670746f, -0.157204970717430f, + 0.974522948265076f, -0.157568961381912f, 0.974401950836182f, -0.157932877540588f, + 0.974280655384064f, -0.158296689391136f, 0.974159121513367f, -0.158660411834717f, + 0.974037289619446f, -0.159024044871330f, 0.973915159702301f, -0.159387573599815f, + 0.973792791366577f, -0.159751012921333f, 0.973670125007629f, -0.160114362835884f, + 0.973547160625458f, -0.160477623343468f, 0.973423957824707f, -0.160840779542923f, + 0.973300457000732f, -0.161203846335411f, 0.973176658153534f, -0.161566808819771f, + 0.973052620887756f, -0.161929681897163f, 0.972928285598755f, -0.162292465567589f, + 0.972803652286530f, -0.162655144929886f, 0.972678780555725f, -0.163017734885216f, + 0.972553610801697f, -0.163380220532417f, 0.972428143024445f, -0.163742616772652f, + 0.972302436828613f, -0.164104923605919f, 0.972176432609558f, -0.164467126131058f, + 0.972050130367279f, -0.164829224348068f, 0.971923589706421f, -0.165191248059273f, + 0.971796751022339f, -0.165553152561188f, 0.971669614315033f, -0.165914967656136f, + 0.971542239189148f, -0.166276678442955f, 0.971414566040039f, -0.166638299822807f, + 0.971286594867706f, -0.166999831795692f, 0.971158385276794f, -0.167361244559288f, + 0.971029877662659f, -0.167722567915916f, 0.970901072025299f, -0.168083801865578f, + 0.970772027969360f, -0.168444931507111f, 0.970642685890198f, -0.168805956840515f, + 0.970513105392456f, -0.169166877865791f, 0.970383226871490f, -0.169527709484100f, + 0.970253050327301f, -0.169888436794281f, 0.970122575759888f, -0.170249074697495f, + 0.969991862773895f, -0.170609608292580f, 0.969860911369324f, -0.170970037579536f, + 0.969729602336884f, -0.171330362558365f, 0.969598054885864f, -0.171690583229065f, + 0.969466269016266f, -0.172050714492798f, 0.969334125518799f, -0.172410741448402f, + 0.969201743602753f, -0.172770664095879f, 0.969069123268127f, -0.173130482435226f, + 0.968936204910278f, -0.173490211367607f, 0.968802988529205f, -0.173849821090698f, + 0.968669533729553f, -0.174209341406822f, 0.968535780906677f, -0.174568757414818f, + 0.968401730060577f, -0.174928069114685f, 0.968267440795898f, -0.175287276506424f, + 0.968132853507996f, -0.175646379590034f, 0.967997968196869f, -0.176005378365517f, + 0.967862844467163f, -0.176364272832870f, 0.967727422714233f, -0.176723077893257f, + 0.967591762542725f, -0.177081763744354f, 0.967455804347992f, -0.177440345287323f, + 0.967319548130035f, -0.177798837423325f, 0.967183053493500f, -0.178157210350037f, + 0.967046260833740f, -0.178515478968620f, 0.966909229755402f, -0.178873643279076f, + 0.966771900653839f, -0.179231703281403f, 0.966634273529053f, -0.179589673876762f, + 0.966496407985687f, -0.179947525262833f, 0.966358244419098f, -0.180305257439613f, + 0.966219842433929f, -0.180662900209427f, 0.966081082820892f, -0.181020438671112f, + 0.965942144393921f, -0.181377857923508f, 0.965802907943726f, -0.181735187768936f, + 0.965663373470306f, -0.182092398405075f, 0.965523540973663f, -0.182449504733086f, + 0.965383470058441f, -0.182806491851807f, 0.965243160724640f, -0.183163389563560f, + 0.965102493762970f, -0.183520168066025f, 0.964961588382721f, -0.183876842260361f, + 0.964820444583893f, -0.184233412146568f, 0.964679002761841f, -0.184589877724648f, + 0.964537262916565f, -0.184946224093437f, 0.964395284652710f, -0.185302466154099f, + 0.964253067970276f, -0.185658603906631f, 0.964110493659973f, -0.186014622449875f, + 0.963967680931091f, -0.186370536684990f, 0.963824629783630f, -0.186726331710815f, + 0.963681280612946f, -0.187082037329674f, 0.963537633419037f, -0.187437608838081f, + 0.963393747806549f, -0.187793090939522f, 0.963249564170837f, -0.188148453831673f, + 0.963105142116547f, -0.188503712415695f, 0.962960422039032f, -0.188858851790428f, + 0.962815403938293f, -0.189213871955872f, 0.962670147418976f, -0.189568802714348f, + 0.962524592876434f, -0.189923599362373f, 0.962378799915314f, -0.190278306603432f, + 0.962232708930969f, -0.190632879734039f, 0.962086379528046f, -0.190987363457680f, + 0.961939752101898f, -0.191341713070869f, 0.961792886257172f, -0.191695958375931f, + 0.961645722389221f, -0.192050099372864f, 0.961498260498047f, -0.192404121160507f, + 0.961350560188293f, -0.192758023738861f, 0.961202561855316f, -0.193111822009087f, + 0.961054325103760f, -0.193465501070023f, 0.960905790328979f, -0.193819075822830f, + 0.960757017135620f, -0.194172516465187f, 0.960607945919037f, -0.194525867700577f, + 0.960458636283875f, -0.194879084825516f, 0.960309028625488f, -0.195232197642326f, + 0.960159122943878f, -0.195585191249847f, 0.960008978843689f, -0.195938065648079f, + 0.959858596324921f, -0.196290835738182f, 0.959707856178284f, -0.196643486618996f, + 0.959556937217712f, -0.196996018290520f, 0.959405720233917f, -0.197348430752754f, + 0.959254205226898f, -0.197700738906860f, 0.959102451801300f, -0.198052927851677f, + 0.958950400352478f, -0.198404997587204f, 0.958798050880432f, -0.198756948113441f, + 0.958645522594452f, -0.199108779430389f, 0.958492636680603f, -0.199460506439209f, + 0.958339512348175f, -0.199812099337578f, 0.958186149597168f, -0.200163587927818f, + 0.958032488822937f, -0.200514942407608f, 0.957878530025482f, -0.200866192579269f, + 0.957724332809448f, -0.201217323541641f, 0.957569897174835f, -0.201568335294724f, + 0.957415163516998f, -0.201919227838516f, 0.957260131835938f, -0.202270001173019f, + 0.957104861736298f, -0.202620655298233f, 0.956949353218079f, -0.202971190214157f, + 0.956793546676636f, -0.203321605920792f, 0.956637442111969f, -0.203671902418137f, + 0.956481099128723f, -0.204022079706192f, 0.956324458122253f, -0.204372137784958f, + 0.956167578697205f, -0.204722076654434f, 0.956010460853577f, -0.205071896314621f, + 0.955853044986725f, -0.205421581864357f, 0.955695331096649f, -0.205771163105965f, + 0.955537378787994f, -0.206120610237122f, 0.955379128456116f, -0.206469938158989f, + 0.955220639705658f, -0.206819161772728f, 0.955061912536621f, -0.207168251276016f, + 0.954902827739716f, -0.207517206668854f, 0.954743564128876f, -0.207866057753563f, + 0.954584002494812f, -0.208214774727821f, 0.954424142837524f, -0.208563387393951f, + 0.954264044761658f, -0.208911851048470f, 0.954103708267212f, -0.209260210394859f, + 0.953943073749542f, -0.209608450531960f, 0.953782141208649f, -0.209956556558609f, + 0.953620970249176f, -0.210304543375969f, 0.953459560871124f, -0.210652396082878f, + 0.953297853469849f, -0.211000129580498f, 0.953135907649994f, -0.211347743868828f, + 0.952973663806915f, -0.211695238947868f, 0.952811121940613f, -0.212042599916458f, + 0.952648401260376f, -0.212389841675758f, 0.952485322952271f, -0.212736949324608f, + 0.952322065830231f, -0.213083937764168f, 0.952158451080322f, -0.213430806994438f, + 0.951994657516479f, -0.213777542114258f, 0.951830565929413f, -0.214124158024788f, + 0.951666176319122f, -0.214470639824867f, 0.951501548290253f, -0.214817002415657f, + 0.951336681842804f, -0.215163245797157f, 0.951171517372131f, -0.215509355068207f, + 0.951006054878235f, -0.215855330228806f, 0.950840353965759f, -0.216201186180115f, + 0.950674414634705f, -0.216546908020973f, 0.950508177280426f, -0.216892510652542f, + 0.950341701507568f, -0.217237979173660f, 0.950174987316132f, -0.217583328485489f, + 0.950007975101471f, -0.217928543686867f, 0.949840664863586f, -0.218273624777794f, + 0.949673116207123f, -0.218618586659431f, 0.949505329132080f, -0.218963414430618f, + 0.949337244033813f, -0.219308122992516f, 0.949168920516968f, -0.219652697443962f, + 0.949000298976898f, -0.219997137784958f, 0.948831439018250f, -0.220341444015503f, + 0.948662281036377f, -0.220685631036758f, 0.948492884635925f, -0.221029683947563f, + 0.948323249816895f, -0.221373617649078f, 0.948153316974640f, -0.221717402338982f, + 0.947983145713806f, -0.222061067819595f, 0.947812676429749f, -0.222404599189758f, + 0.947641968727112f, -0.222748011350632f, 0.947470963001251f, -0.223091274499893f, + 0.947299718856812f, -0.223434418439865f, 0.947128236293793f, -0.223777428269386f, + 0.946956455707550f, -0.224120303988457f, 0.946784436702728f, -0.224463045597076f, + 0.946612179279327f, -0.224805667996407f, 0.946439623832703f, -0.225148141384125f, + 0.946266770362854f, -0.225490495562553f, 0.946093678474426f, -0.225832715630531f, + 0.945920348167419f, -0.226174786686897f, 0.945746779441834f, -0.226516738533974f, + 0.945572853088379f, -0.226858556270599f, 0.945398747920990f, -0.227200239896774f, + 0.945224344730377f, -0.227541789412498f, 0.945049703121185f, -0.227883204817772f, + 0.944874763488770f, -0.228224486112595f, 0.944699645042419f, -0.228565633296967f, + 0.944524168968201f, -0.228906646370888f, 0.944348454475403f, -0.229247525334358f, + 0.944172501564026f, -0.229588270187378f, 0.943996310234070f, -0.229928880929947f, + 0.943819820880890f, -0.230269357562065f, 0.943643093109131f, -0.230609700083733f, + 0.943466067314148f, -0.230949893593788f, 0.943288803100586f, -0.231289967894554f, + 0.943111240863800f, -0.231629893183708f, 0.942933499813080f, -0.231969684362412f, + 0.942755401134491f, -0.232309341430664f, 0.942577123641968f, -0.232648864388466f, + 0.942398548126221f, -0.232988253235817f, 0.942219734191895f, -0.233327493071556f, + 0.942040622234344f, -0.233666598796844f, 0.941861271858215f, -0.234005570411682f, + 0.941681683063507f, -0.234344407916069f, 0.941501796245575f, -0.234683111310005f, + 0.941321671009064f, -0.235021665692329f, 0.941141307353973f, -0.235360085964203f, + 0.940960645675659f, -0.235698372125626f, 0.940779745578766f, -0.236036509275436f, + 0.940598547458649f, -0.236374512314796f, 0.940417110919952f, -0.236712381243706f, + 0.940235435962677f, -0.237050101161003f, 0.940053522586823f, -0.237387686967850f, + 0.939871311187744f, -0.237725138664246f, 0.939688861370087f, -0.238062441349030f, + 0.939506113529205f, -0.238399609923363f, 0.939323127269745f, -0.238736644387245f, + 0.939139902591705f, -0.239073529839516f, 0.938956379890442f, -0.239410281181335f, + 0.938772618770599f, -0.239746883511543f, 0.938588619232178f, -0.240083336830139f, + 0.938404381275177f, -0.240419670939446f, 0.938219845294952f, -0.240755841135979f, + 0.938035070896149f, -0.241091892123222f, 0.937849998474121f, -0.241427779197693f, + 0.937664687633514f, -0.241763532161713f, 0.937479138374329f, -0.242099151015282f, + 0.937293350696564f, -0.242434620857239f, 0.937107264995575f, -0.242769956588745f, + 0.936920940876007f, -0.243105143308640f, 0.936734318733215f, -0.243440181016922f, + 0.936547517776489f, -0.243775084614754f, 0.936360359191895f, -0.244109839200974f, + 0.936173021793365f, -0.244444444775581f, 0.935985386371613f, -0.244778916239738f, + 0.935797572135925f, -0.245113238692284f, 0.935609400272369f, -0.245447427034378f, + 0.935421049594879f, -0.245781451463699f, 0.935232400894165f, -0.246115356683731f, + 0.935043513774872f, -0.246449097990990f, 0.934854328632355f, -0.246782705187798f, + 0.934664964675903f, -0.247116148471832f, 0.934475243091583f, -0.247449472546577f, + 0.934285342693329f, -0.247782632708550f, 0.934095203876495f, -0.248115643858910f, + 0.933904767036438f, -0.248448520898819f, 0.933714091777802f, -0.248781248927116f, + 0.933523118495941f, -0.249113827943802f, 0.933331906795502f, -0.249446272850037f, + 0.933140456676483f, -0.249778553843498f, 0.932948768138886f, -0.250110685825348f, + 0.932756841182709f, -0.250442683696747f, 0.932564616203308f, -0.250774532556534f, + 0.932372152805328f, -0.251106232404709f, 0.932179391384125f, -0.251437783241272f, + 0.931986451148987f, -0.251769185066223f, 0.931793212890625f, -0.252100437879562f, + 0.931599736213684f, -0.252431541681290f, 0.931405961513519f, -0.252762526273727f, + 0.931211948394775f, -0.253093332052231f, 0.931017756462097f, -0.253423988819122f, + 0.930823206901550f, -0.253754496574402f, 0.930628478527069f, -0.254084855318069f, + 0.930433452129364f, -0.254415065050125f, 0.930238187313080f, -0.254745125770569f, + 0.930042684078217f, -0.255075037479401f, 0.929846942424774f, -0.255404800176620f, + 0.929650902748108f, -0.255734413862228f, 0.929454624652863f, -0.256063878536224f, + 0.929258108139038f, -0.256393194198608f, 0.929061353206635f, -0.256722360849380f, + 0.928864300251007f, -0.257051378488541f, 0.928667008876801f, -0.257380217313766f, + 0.928469479084015f, -0.257708936929703f, 0.928271710872650f, -0.258037507534027f, + 0.928073644638062f, -0.258365899324417f, 0.927875399589539f, -0.258694142103195f, + 0.927676856517792f, -0.259022265672684f, 0.927478015422821f, -0.259350210428238f, + 0.927278995513916f, -0.259678006172180f, 0.927079677581787f, -0.260005623102188f, + 0.926880121231079f, -0.260333120822906f, 0.926680326461792f, -0.260660469532013f, + 0.926480293273926f, -0.260987639427185f, 0.926280021667480f, -0.261314690113068f, + 0.926079452037811f, -0.261641561985016f, 0.925878643989563f, -0.261968284845352f, + 0.925677597522736f, -0.262294828891754f, 0.925476312637329f, -0.262621253728867f, + 0.925274729728699f, -0.262947499752045f, 0.925072908401489f, -0.263273626565933f, + 0.924870908260345f, -0.263599574565887f, 0.924668610095978f, -0.263925373554230f, + 0.924466013908386f, -0.264250993728638f, 0.924263238906860f, -0.264576494693756f, + 0.924060165882111f, -0.264901816844940f, 0.923856854438782f, -0.265226989984512f, + 0.923653304576874f, -0.265552014112473f, 0.923449516296387f, -0.265876859426498f, + 0.923245489597321f, -0.266201555728912f, 0.923041164875031f, -0.266526103019714f, + 0.922836601734161f, -0.266850501298904f, 0.922631800174713f, -0.267174720764160f, + 0.922426760196686f, -0.267498821020126f, 0.922221481800079f, -0.267822742462158f, + 0.922015964984894f, -0.268146485090256f, 0.921810150146484f, -0.268470078706741f, + 0.921604096889496f, -0.268793523311615f, 0.921397805213928f, -0.269116818904877f, + 0.921191275119781f, -0.269439965486526f, 0.920984506607056f, -0.269762933254242f, + 0.920777499675751f, -0.270085722208023f, 0.920570194721222f, -0.270408391952515f, + 0.920362710952759f, -0.270730882883072f, 0.920154929161072f, -0.271053224802017f, + 0.919946908950806f, -0.271375387907028f, 0.919738650321960f, -0.271697402000427f, + 0.919530093669891f, -0.272019267082214f, 0.919321358203888f, -0.272340953350067f, + 0.919112324714661f, -0.272662490606308f, 0.918903112411499f, -0.272983878850937f, + 0.918693602085114f, -0.273305088281631f, 0.918483853340149f, -0.273626148700714f, + 0.918273866176605f, -0.273947030305862f, 0.918063640594482f, -0.274267762899399f, + 0.917853116989136f, -0.274588316679001f, 0.917642414569855f, -0.274908751249313f, + 0.917431414127350f, -0.275228977203369f, 0.917220234870911f, -0.275549083948135f, + 0.917008757591248f, -0.275868982076645f, 0.916797041893005f, -0.276188760995865f, + 0.916585087776184f, -0.276508361101151f, 0.916372895240784f, -0.276827782392502f, + 0.916160404682159f, -0.277147054672241f, 0.915947735309601f, -0.277466177940369f, + 0.915734827518463f, -0.277785122394562f, 0.915521621704102f, -0.278103888034821f, + 0.915308177471161f, -0.278422504663467f, 0.915094554424286f, -0.278740972280502f, + 0.914880633354187f, -0.279059261083603f, 0.914666473865509f, -0.279377400875092f, + 0.914452075958252f, -0.279695361852646f, 0.914237439632416f, -0.280013144016266f, + 0.914022505283356f, -0.280330777168274f, 0.913807392120361f, -0.280648261308670f, + 0.913592040538788f, -0.280965566635132f, 0.913376390933990f, -0.281282693147659f, + 0.913160502910614f, -0.281599670648575f, 0.912944436073303f, -0.281916469335556f, + 0.912728071212769f, -0.282233119010925f, 0.912511467933655f, -0.282549589872360f, + 0.912294626235962f, -0.282865911722183f, 0.912077546119690f, -0.283182054758072f, + 0.911860227584839f, -0.283498018980026f, 0.911642670631409f, -0.283813834190369f, + 0.911424875259399f, -0.284129470586777f, 0.911206841468811f, -0.284444957971573f, + 0.910988569259644f, -0.284760266542435f, 0.910769999027252f, -0.285075396299362f, + 0.910551249980927f, -0.285390377044678f, 0.910332262516022f, -0.285705178976059f, + 0.910112977027893f, -0.286019802093506f, 0.909893512725830f, -0.286334276199341f, + 0.909673750400543f, -0.286648571491241f, 0.909453809261322f, -0.286962717771530f, + 0.909233570098877f, -0.287276685237885f, 0.909013092517853f, -0.287590473890305f, + 0.908792436122894f, -0.287904083728790f, 0.908571481704712f, -0.288217544555664f, + 0.908350288867950f, -0.288530826568604f, 0.908128857612610f, -0.288843959569931f, + 0.907907187938690f, -0.289156883955002f, 0.907685279846191f, -0.289469659328461f, + 0.907463192939758f, -0.289782285690308f, 0.907240808010101f, -0.290094703435898f, + 0.907018184661865f, -0.290406972169876f, 0.906795322895050f, -0.290719062089920f, + 0.906572222709656f, -0.291031002998352f, 0.906348884105682f, -0.291342735290527f, + 0.906125307083130f, -0.291654318571091f, 0.905901491641998f, -0.291965723037720f, + 0.905677437782288f, -0.292276978492737f, 0.905453145503998f, -0.292588025331497f, + 0.905228614807129f, -0.292898923158646f, 0.905003845691681f, -0.293209642171860f, + 0.904778838157654f, -0.293520182371140f, 0.904553592205048f, -0.293830573558807f, + 0.904328107833862f, -0.294140785932541f, 0.904102385044098f, -0.294450789690018f, + 0.903876423835754f, -0.294760644435883f, 0.903650224208832f, -0.295070350170136f, + 0.903423786163330f, -0.295379847288132f, 0.903197109699249f, -0.295689195394516f, + 0.902970194816589f, -0.295998334884644f, 0.902743041515350f, -0.296307325363159f, + 0.902515649795532f, -0.296616137027740f, 0.902288019657135f, -0.296924799680710f, + 0.902060210704803f, -0.297233253717422f, 0.901832103729248f, -0.297541528940201f, + 0.901603758335114f, -0.297849655151367f, 0.901375174522400f, -0.298157602548599f, + 0.901146411895752f, -0.298465341329575f, 0.900917351245880f, -0.298772931098938f, + 0.900688111782074f, -0.299080342054367f, 0.900458574295044f, -0.299387603998184f, + 0.900228857994080f, -0.299694657325745f, 0.899998843669891f, -0.300001531839371f, + 0.899768650531769f, -0.300308227539063f, 0.899538159370422f, -0.300614774227142f, + 0.899307489395142f, -0.300921112298965f, 0.899076581001282f, -0.301227301359177f, + 0.898845434188843f, -0.301533311605453f, 0.898614048957825f, -0.301839113235474f, + 0.898382425308228f, -0.302144765853882f, 0.898150563240051f, -0.302450239658356f, + 0.897918462753296f, -0.302755534648895f, 0.897686123847961f, -0.303060621023178f, + 0.897453546524048f, -0.303365558385849f, 0.897220790386200f, -0.303670316934586f, + 0.896987736225128f, -0.303974896669388f, 0.896754503250122f, -0.304279297590256f, + 0.896520972251892f, -0.304583519697189f, 0.896287262439728f, -0.304887533187866f, + 0.896053314208984f, -0.305191397666931f, 0.895819067955017f, -0.305495083332062f, + 0.895584642887115f, -0.305798590183258f, 0.895349979400635f, -0.306101888418198f, + 0.895115137100220f, -0.306405037641525f, 0.894879996776581f, -0.306708008050919f, + 0.894644618034363f, -0.307010769844055f, 0.894409060478210f, -0.307313382625580f, + 0.894173204898834f, -0.307615786790848f, 0.893937170505524f, -0.307918041944504f, + 0.893700897693634f, -0.308220088481903f, 0.893464326858521f, -0.308521956205368f, + 0.893227577209473f, -0.308823645114899f, 0.892990648746490f, -0.309125155210495f, + 0.892753422260284f, -0.309426486492157f, 0.892515957355499f, -0.309727638959885f, + 0.892278313636780f, -0.310028612613678f, 0.892040371894836f, -0.310329377651215f, + 0.891802251338959f, -0.310629993677139f, 0.891563892364502f, -0.310930401086807f, + 0.891325294971466f, -0.311230629682541f, 0.891086459159851f, -0.311530679464340f, + 0.890847444534302f, -0.311830550432205f, 0.890608131885529f, -0.312130242586136f, + 0.890368640422821f, -0.312429755926132f, 0.890128850936890f, -0.312729060649872f, + 0.889888882637024f, -0.313028186559677f, 0.889648675918579f, -0.313327133655548f, + 0.889408230781555f, -0.313625901937485f, 0.889167606830597f, -0.313924491405487f, + 0.888926684856415f, -0.314222872257233f, 0.888685584068298f, -0.314521104097366f, + 0.888444244861603f, -0.314819127321243f, 0.888202667236328f, -0.315116971731186f, + 0.887960851192474f, -0.315414607524872f, 0.887718796730042f, -0.315712094306946f, + 0.887476563453674f, -0.316009372472763f, 0.887234091758728f, -0.316306471824646f, + 0.886991322040558f, -0.316603392362595f, 0.886748373508453f, -0.316900104284287f, + 0.886505246162415f, -0.317196637392044f, 0.886261820793152f, -0.317492991685867f, + 0.886018216609955f, -0.317789167165756f, 0.885774314403534f, -0.318085134029388f, + 0.885530233383179f, -0.318380922079086f, 0.885285973548889f, -0.318676531314850f, + 0.885041415691376f, -0.318971961736679f, 0.884796679019928f, -0.319267183542252f, + 0.884551644325256f, -0.319562226533890f, 0.884306430816650f, -0.319857090711594f, + 0.884061038494110f, -0.320151746273041f, 0.883815348148346f, -0.320446223020554f, + 0.883569478988647f, -0.320740520954132f, 0.883323311805725f, -0.321034610271454f, + 0.883076965808868f, -0.321328520774841f, 0.882830440998077f, -0.321622252464294f, + 0.882583618164063f, -0.321915775537491f, 0.882336616516113f, -0.322209119796753f, + 0.882089376449585f, -0.322502255439758f, 0.881841897964478f, -0.322795242071152f, + 0.881594181060791f, -0.323088020086288f, 0.881346285343170f, -0.323380589485168f, + 0.881098151206970f, -0.323672980070114f, 0.880849778652191f, -0.323965191841125f, + 0.880601167678833f, -0.324257194995880f, 0.880352377891541f, -0.324549019336700f, + 0.880103349685669f, -0.324840664863586f, 0.879854083061218f, -0.325132101774216f, + 0.879604578018188f, -0.325423330068588f, 0.879354894161224f, -0.325714409351349f, + 0.879104971885681f, -0.326005280017853f, 0.878854811191559f, -0.326295942068100f, + 0.878604412078857f, -0.326586425304413f, 0.878353834152222f, -0.326876699924469f, + 0.878103017807007f, -0.327166795730591f, 0.877851963043213f, -0.327456712722778f, + 0.877600669860840f, -0.327746421098709f, 0.877349197864532f, -0.328035950660706f, + 0.877097487449646f, -0.328325271606445f, 0.876845538616180f, -0.328614413738251f, + 0.876593410968781f, -0.328903347253799f, 0.876341044902802f, -0.329192101955414f, + 0.876088440418243f, -0.329480648040771f, 0.875835597515106f, -0.329769015312195f, + 0.875582575798035f, -0.330057173967361f, 0.875329315662384f, -0.330345153808594f, + 0.875075817108154f, -0.330632925033569f, 0.874822139739990f, -0.330920487642288f, + 0.874568223953247f, -0.331207901239395f, 0.874314069747925f, -0.331495076417923f, + 0.874059677124023f, -0.331782072782516f, 0.873805105686188f, -0.332068890333176f, + 0.873550295829773f, -0.332355499267578f, 0.873295307159424f, -0.332641899585724f, + 0.873040020465851f, -0.332928121089935f, 0.872784554958344f, -0.333214133977890f, + 0.872528910636902f, -0.333499968051910f, 0.872272968292236f, -0.333785593509674f, + 0.872016847133636f, -0.334071010351181f, 0.871760547161102f, -0.334356248378754f, + 0.871503949165344f, -0.334641307592392f, 0.871247172355652f, -0.334926128387451f, + 0.870990216732025f, -0.335210770368576f, 0.870733022689819f, -0.335495233535767f, + 0.870475590229034f, -0.335779488086700f, 0.870217919349670f, -0.336063534021378f, + 0.869960069656372f, -0.336347371339798f, 0.869701981544495f, -0.336631029844284f, + 0.869443655014038f, -0.336914509534836f, 0.869185149669647f, -0.337197750806808f, + 0.868926405906677f, -0.337480813264847f, 0.868667483329773f, -0.337763696908951f, + 0.868408262729645f, -0.338046342134476f, 0.868148922920227f, -0.338328808546066f, + 0.867889285087585f, -0.338611096143723f, 0.867629468441010f, -0.338893145322800f, + 0.867369413375854f, -0.339175015687943f, 0.867109179496765f, -0.339456677436829f, + 0.866848707199097f, -0.339738160371780f, 0.866588056087494f, -0.340019434690475f, + 0.866327106952667f, -0.340300500392914f, 0.866066038608551f, -0.340581357479095f, + 0.865804672241211f, -0.340862035751343f, 0.865543127059937f, -0.341142505407333f, + 0.865281403064728f, -0.341422766447067f, 0.865019381046295f, -0.341702848672867f, + 0.864757239818573f, -0.341982692480087f, 0.864494800567627f, -0.342262357473373f, + 0.864232182502747f, -0.342541843652725f, 0.863969385623932f, -0.342821091413498f, + 0.863706290721893f, -0.343100160360336f, 0.863443076610565f, -0.343379020690918f, + 0.863179564476013f, -0.343657672405243f, 0.862915873527527f, -0.343936115503311f, + 0.862652003765106f, -0.344214379787445f, 0.862387895584106f, -0.344492435455322f, + 0.862123548984528f, -0.344770282506943f, 0.861859023571014f, -0.345047920942307f, + 0.861594259738922f, -0.345325350761414f, 0.861329257488251f, -0.345602601766586f, + 0.861064076423645f, -0.345879614353180f, 0.860798716545105f, -0.346156448125839f, + 0.860533118247986f, -0.346433073282242f, 0.860267281532288f, -0.346709519624710f, + 0.860001266002655f, -0.346985727548599f, 0.859735012054443f, -0.347261756658554f, + 0.859468579292297f, -0.347537547349930f, 0.859201908111572f, -0.347813159227371f, + 0.858934998512268f, -0.348088562488556f, 0.858667910099030f, -0.348363757133484f, + 0.858400642871857f, -0.348638743162155f, 0.858133137226105f, -0.348913550376892f, + 0.857865393161774f, -0.349188119173050f, 0.857597470283508f, -0.349462509155273f, + 0.857329368591309f, -0.349736660718918f, 0.857060968875885f, -0.350010633468628f, + 0.856792449951172f, -0.350284397602081f, 0.856523692607880f, -0.350557953119278f, + 0.856254696846008f, -0.350831300020218f, 0.855985522270203f, -0.351104438304901f, + 0.855716109275818f, -0.351377367973328f, 0.855446517467499f, -0.351650089025497f, + 0.855176687240601f, -0.351922631263733f, 0.854906618595123f, -0.352194935083389f, + 0.854636430740356f, -0.352467030286789f, 0.854365944862366f, -0.352738946676254f, + 0.854095339775085f, -0.353010624647141f, 0.853824436664581f, -0.353282123804092f, + 0.853553414344788f, -0.353553384542465f, 0.853282094001770f, -0.353824466466904f, + 0.853010654449463f, -0.354095309972763f, 0.852738916873932f, -0.354365974664688f, + 0.852467060089111f, -0.354636400938034f, 0.852194905281067f, -0.354906648397446f, + 0.851922631263733f, -0.355176687240601f, 0.851650118827820f, -0.355446487665176f, + 0.851377367973328f, -0.355716109275818f, 0.851104438304901f, -0.355985492467880f, + 0.850831270217896f, -0.356254696846008f, 0.850557923316956f, -0.356523662805557f, + 0.850284397602081f, -0.356792420148849f, 0.850010633468628f, -0.357060998678207f, + 0.849736690521240f, -0.357329338788986f, 0.849462509155273f, -0.357597470283508f, + 0.849188148975372f, -0.357865422964096f, 0.848913550376892f, -0.358133137226105f, + 0.848638772964478f, -0.358400642871857f, 0.848363757133484f, -0.358667939901352f, + 0.848088562488556f, -0.358935028314590f, 0.847813189029694f, -0.359201908111572f, + 0.847537577152252f, -0.359468549489975f, 0.847261726856232f, -0.359735012054443f, + 0.846985757350922f, -0.360001266002655f, 0.846709489822388f, -0.360267281532288f, + 0.846433103084564f, -0.360533088445663f, 0.846156477928162f, -0.360798716545105f, + 0.845879614353180f, -0.361064106225967f, 0.845602571964264f, -0.361329287290573f, + 0.845325350761414f, -0.361594229936600f, 0.845047891139984f, -0.361858993768692f, + 0.844770252704620f, -0.362123548984528f, 0.844492435455322f, -0.362387865781784f, + 0.844214379787445f, -0.362651973962784f, 0.843936145305634f, -0.362915903329849f, + 0.843657672405243f, -0.363179564476013f, 0.843379020690918f, -0.363443046808243f, + 0.843100130558014f, -0.363706320524216f, 0.842821121215820f, -0.363969355821610f, + 0.842541813850403f, -0.364232182502747f, 0.842262387275696f, -0.364494800567627f, + 0.841982722282410f, -0.364757210016251f, 0.841702818870544f, -0.365019410848618f, + 0.841422796249390f, -0.365281373262405f, 0.841142535209656f, -0.365543156862259f, + 0.840862035751343f, -0.365804702043533f, 0.840581357479095f, -0.366066008806229f, + 0.840300500392914f, -0.366327136754990f, 0.840019404888153f, -0.366588026285172f, + 0.839738130569458f, -0.366848707199097f, 0.839456677436829f, -0.367109179496765f, + 0.839175045490265f, -0.367369443178177f, 0.838893175125122f, -0.367629468441010f, + 0.838611066341400f, -0.367889285087585f, 0.838328838348389f, -0.368148893117905f, + 0.838046371936798f, -0.368408292531967f, 0.837763667106628f, -0.368667453527451f, + 0.837480843067169f, -0.368926405906677f, 0.837197780609131f, -0.369185149669647f, + 0.836914479732513f, -0.369443655014038f, 0.836631059646606f, -0.369701951742172f, + 0.836347401142120f, -0.369960039854050f, 0.836063504219055f, -0.370217919349670f, + 0.835779488086700f, -0.370475560426712f, 0.835495233535767f, -0.370732992887497f, + 0.835210800170898f, -0.370990216732025f, 0.834926128387451f, -0.371247202157974f, + 0.834641277790070f, -0.371503978967667f, 0.834356248378754f, -0.371760547161102f, + 0.834071040153503f, -0.372016876935959f, 0.833785593509674f, -0.372272998094559f, + 0.833499968051910f, -0.372528880834579f, 0.833214163780212f, -0.372784584760666f, + 0.832928121089935f, -0.373040050268173f, 0.832641899585724f, -0.373295277357101f, + 0.832355499267578f, -0.373550295829773f, 0.832068860530853f, -0.373805105686188f, + 0.831782102584839f, -0.374059677124023f, 0.831495106220245f, -0.374314039945602f, + 0.831207871437073f, -0.374568194150925f, 0.830920517444611f, -0.374822109937668f, + 0.830632925033569f, -0.375075817108154f, 0.830345153808594f, -0.375329315662384f, + 0.830057144165039f, -0.375582575798035f, 0.829769015312195f, -0.375835597515106f, + 0.829480648040771f, -0.376088410615921f, 0.829192101955414f, -0.376341015100479f, + 0.828903317451477f, -0.376593410968781f, 0.828614413738251f, -0.376845568418503f, + 0.828325271606445f, -0.377097487449646f, 0.828035950660706f, -0.377349197864532f, + 0.827746450901031f, -0.377600699663162f, 0.827456712722778f, -0.377851963043213f, + 0.827166795730591f, -0.378102988004684f, 0.826876699924469f, -0.378353834152222f, + 0.826586425304413f, -0.378604412078857f, 0.826295912265778f, -0.378854811191559f, + 0.826005280017853f, -0.379104942083359f, 0.825714409351349f, -0.379354894161224f, + 0.825423359870911f, -0.379604607820511f, 0.825132071971893f, -0.379854083061218f, + 0.824840664863586f, -0.380103349685669f, 0.824549019336700f, -0.380352377891541f, + 0.824257194995880f, -0.380601197481155f, 0.823965191841125f, -0.380849778652191f, + 0.823673009872437f, -0.381098151206970f, 0.823380589485168f, -0.381346285343170f, + 0.823087990283966f, -0.381594210863113f, 0.822795212268829f, -0.381841897964478f, + 0.822502255439758f, -0.382089376449585f, 0.822209119796753f, -0.382336616516113f, + 0.821915745735168f, -0.382583618164063f, 0.821622252464294f, -0.382830440998077f, + 0.821328520774841f, -0.383076995611191f, 0.821034610271454f, -0.383323341608047f, + 0.820740520954132f, -0.383569449186325f, 0.820446193218231f, -0.383815348148346f, + 0.820151746273041f, -0.384061008691788f, 0.819857060909271f, -0.384306460618973f, + 0.819562196731567f, -0.384551674127579f, 0.819267153739929f, -0.384796649217606f, + 0.818971931934357f, -0.385041415691376f, 0.818676531314850f, -0.385285943746567f, + 0.818380951881409f, -0.385530263185501f, 0.818085134029388f, -0.385774344205856f, + 0.817789137363434f, -0.386018186807632f, 0.817493021488190f, -0.386261820793152f, + 0.817196667194366f, -0.386505216360092f, 0.816900074481964f, -0.386748403310776f, + 0.816603362560272f, -0.386991351842880f, 0.816306471824646f, -0.387234061956406f, + 0.816009342670441f, -0.387476563453674f, 0.815712094306946f, -0.387718826532364f, + 0.815414607524872f, -0.387960851192474f, 0.815116941928864f, -0.388202667236328f, + 0.814819097518921f, -0.388444244861603f, 0.814521074295044f, -0.388685584068298f, + 0.814222872257233f, -0.388926714658737f, 0.813924491405487f, -0.389167606830597f, + 0.813625931739807f, -0.389408260583878f, 0.813327133655548f, -0.389648675918579f, + 0.813028216362000f, -0.389888882637024f, 0.812729060649872f, -0.390128880739212f, + 0.812429726123810f, -0.390368610620499f, 0.812130272388458f, -0.390608131885529f, + 0.811830580234528f, -0.390847414731979f, 0.811530709266663f, -0.391086459159851f, + 0.811230659484863f, -0.391325294971466f, 0.810930430889130f, -0.391563892364502f, + 0.810629963874817f, -0.391802251338959f, 0.810329377651215f, -0.392040401697159f, + 0.810028612613678f, -0.392278283834457f, 0.809727668762207f, -0.392515957355499f, + 0.809426486492157f, -0.392753422260284f, 0.809125185012817f, -0.392990618944168f, + 0.808823645114899f, -0.393227607011795f, 0.808521986007690f, -0.393464356660843f, + 0.808220088481903f, -0.393700867891312f, 0.807918012142181f, -0.393937170505524f, + 0.807615816593170f, -0.394173204898834f, 0.807313382625580f, -0.394409030675888f, + 0.807010769844055f, -0.394644618034363f, 0.806707978248596f, -0.394879996776581f, + 0.806405067443848f, -0.395115107297897f, 0.806101918220520f, -0.395350009202957f, + 0.805798590183258f, -0.395584672689438f, 0.805495083332062f, -0.395819097757339f, + 0.805191397666931f, -0.396053284406662f, 0.804887533187866f, -0.396287262439728f, + 0.804583489894867f, -0.396520972251892f, 0.804279267787933f, -0.396754473447800f, + 0.803974866867065f, -0.396987736225128f, 0.803670346736908f, -0.397220760583878f, + 0.803365588188171f, -0.397453576326370f, 0.803060650825500f, -0.397686123847961f, + 0.802755534648895f, -0.397918462753296f, 0.802450239658356f, -0.398150533437729f, + 0.802144765853882f, -0.398382395505905f, 0.801839113235474f, -0.398614019155502f, + 0.801533281803131f, -0.398845434188843f, 0.801227271556854f, -0.399076581001282f, + 0.800921142101288f, -0.399307489395142f, 0.800614774227142f, -0.399538189172745f, + 0.800308227539063f, -0.399768620729446f, 0.800001561641693f, -0.399998843669891f, + 0.799694657325745f, -0.400228828191757f, 0.799387574195862f, -0.400458574295044f, + 0.799080371856689f, -0.400688081979752f, 0.798772931098938f, -0.400917351245880f, + 0.798465371131897f, -0.401146411895752f, 0.798157572746277f, -0.401375204324722f, + 0.797849655151367f, -0.401603758335114f, 0.797541558742523f, -0.401832103729248f, + 0.797233223915100f, -0.402060180902481f, 0.796924769878387f, -0.402288049459457f, + 0.796616137027740f, -0.402515679597855f, 0.796307325363159f, -0.402743041515350f, + 0.795998334884644f, -0.402970194816589f, 0.795689165592194f, -0.403197109699249f, + 0.795379877090454f, -0.403423786163330f, 0.795070350170136f, -0.403650224208832f, + 0.794760644435883f, -0.403876423835754f, 0.794450819492340f, -0.404102355241776f, + 0.794140756130219f, -0.404328078031540f, 0.793830573558807f, -0.404553562402725f, + 0.793520212173462f, -0.404778808355331f, 0.793209671974182f, -0.405003815889359f, + 0.792898952960968f, -0.405228585004807f, 0.792588055133820f, -0.405453115701675f, + 0.792276978492737f, -0.405677437782288f, 0.791965723037720f, -0.405901491641998f, + 0.791654348373413f, -0.406125307083130f, 0.791342735290527f, -0.406348884105682f, + 0.791031002998352f, -0.406572192907333f, 0.790719091892242f, -0.406795293092728f, + 0.790407001972198f, -0.407018154859543f, 0.790094733238220f, -0.407240778207779f, + 0.789782285690308f, -0.407463163137436f, 0.789469659328461f, -0.407685309648514f, + 0.789156913757324f, -0.407907217741013f, 0.788843929767609f, -0.408128857612610f, + 0.788530826568604f, -0.408350288867950f, 0.788217544555664f, -0.408571451902390f, + 0.787904083728790f, -0.408792406320572f, 0.787590444087982f, -0.409013092517853f, + 0.787276685237885f, -0.409233570098877f, 0.786962687969208f, -0.409453779459000f, + 0.786648571491241f, -0.409673750400543f, 0.786334276199341f, -0.409893482923508f, + 0.786019802093506f, -0.410112977027893f, 0.785705149173737f, -0.410332232713699f, + 0.785390377044678f, -0.410551249980927f, 0.785075426101685f, -0.410770028829575f, + 0.784760236740112f, -0.410988569259644f, 0.784444928169250f, -0.411206841468811f, + 0.784129500389099f, -0.411424905061722f, 0.783813834190369f, -0.411642700433731f, + 0.783498048782349f, -0.411860257387161f, 0.783182024955750f, -0.412077575922012f, + 0.782865881919861f, -0.412294656038284f, 0.782549619674683f, -0.412511497735977f, + 0.782233119010925f, -0.412728071212769f, 0.781916499137878f, -0.412944436073303f, + 0.781599700450897f, -0.413160532712936f, 0.781282722949982f, -0.413376390933990f, + 0.780965566635132f, -0.413592010736465f, 0.780648231506348f, -0.413807392120361f, + 0.780330777168274f, -0.414022535085678f, 0.780013144016266f, -0.414237409830093f, + 0.779695332050323f, -0.414452046155930f, 0.779377400875092f, -0.414666473865509f, + 0.779059290885925f, -0.414880603551865f, 0.778741002082825f, -0.415094524621964f, + 0.778422534465790f, -0.415308207273483f, 0.778103888034821f, -0.415521621704102f, + 0.777785122394562f, -0.415734797716141f, 0.777466177940369f, -0.415947735309601f, + 0.777147054672241f, -0.416160434484482f, 0.776827812194824f, -0.416372895240784f, + 0.776508331298828f, -0.416585087776184f, 0.776188731193542f, -0.416797041893005f, + 0.775869011878967f, -0.417008757591248f, 0.775549054145813f, -0.417220205068588f, + 0.775228977203369f, -0.417431443929672f, 0.774908721446991f, -0.417642414569855f, + 0.774588346481323f, -0.417853146791458f, 0.774267733097076f, -0.418063640594482f, + 0.773947000503540f, -0.418273866176605f, 0.773626148700714f, -0.418483853340149f, + 0.773305058479309f, -0.418693602085114f, 0.772983849048615f, -0.418903112411499f, + 0.772662520408630f, -0.419112354516983f, 0.772340953350067f, -0.419321358203888f, + 0.772019267082214f, -0.419530123472214f, 0.771697402000427f, -0.419738620519638f, + 0.771375417709351f, -0.419946908950806f, 0.771053194999695f, -0.420154929161072f, + 0.770730912685394f, -0.420362681150436f, 0.770408391952515f, -0.420570224523544f, + 0.770085752010345f, -0.420777499675751f, 0.769762933254242f, -0.420984506607056f, + 0.769439935684204f, -0.421191304922104f, 0.769116818904877f, -0.421397835016251f, + 0.768793523311615f, -0.421604126691818f, 0.768470108509064f, -0.421810150146484f, + 0.768146514892578f, -0.422015935182571f, 0.767822742462158f, -0.422221481800079f, + 0.767498791217804f, -0.422426789999008f, 0.767174720764160f, -0.422631829977036f, + 0.766850471496582f, -0.422836631536484f, 0.766526103019714f, -0.423041164875031f, + 0.766201555728912f, -0.423245459794998f, 0.765876889228821f, -0.423449516296387f, + 0.765551984310150f, -0.423653304576874f, 0.765226960182190f, -0.423856884241104f, + 0.764901816844940f, -0.424060165882111f, 0.764576494693756f, -0.424263238906860f, + 0.764250993728638f, -0.424466013908386f, 0.763925373554230f, -0.424668580293655f, + 0.763599574565887f, -0.424870878458023f, 0.763273596763611f, -0.425072938203812f, + 0.762947499752045f, -0.425274729728699f, 0.762621283531189f, -0.425476282835007f, + 0.762294828891754f, -0.425677597522736f, 0.761968255043030f, -0.425878643989563f, + 0.761641561985016f, -0.426079452037811f, 0.761314690113068f, -0.426279991865158f, + 0.760987639427185f, -0.426480293273926f, 0.760660469532013f, -0.426680356264114f, + 0.760333120822906f, -0.426880151033401f, 0.760005652904511f, -0.427079707384110f, + 0.759678006172180f, -0.427278995513916f, 0.759350180625916f, -0.427478045225143f, + 0.759022235870361f, -0.427676826715469f, 0.758694171905518f, -0.427875369787216f, + 0.758365929126740f, -0.428073674440384f, 0.758037507534027f, -0.428271710872650f, + 0.757708966732025f, -0.428469479084015f, 0.757380247116089f, -0.428667008876801f, + 0.757051348686218f, -0.428864300251007f, 0.756722390651703f, -0.429061323404312f, + 0.756393194198608f, -0.429258108139038f, 0.756063878536224f, -0.429454624652863f, + 0.755734443664551f, -0.429650902748108f, 0.755404829978943f, -0.429846942424774f, + 0.755075037479401f, -0.430042684078217f, 0.754745125770569f, -0.430238217115402f, + 0.754415094852448f, -0.430433481931686f, 0.754084885120392f, -0.430628478527069f, + 0.753754496574402f, -0.430823236703873f, 0.753423988819122f, -0.431017726659775f, + 0.753093302249908f, -0.431211978197098f, 0.752762496471405f, -0.431405961513519f, + 0.752431571483612f, -0.431599706411362f, 0.752100467681885f, -0.431793183088303f, + 0.751769185066223f, -0.431986421346664f, 0.751437783241272f, -0.432179391384125f, + 0.751106262207031f, -0.432372123003006f, 0.750774562358856f, -0.432564586400986f, + 0.750442683696747f, -0.432756811380386f, 0.750110685825348f, -0.432948768138886f, + 0.749778568744659f, -0.433140486478806f, 0.749446272850037f, -0.433331936597824f, + 0.749113857746124f, -0.433523118495941f, 0.748781263828278f, -0.433714061975479f, + 0.748448550701141f, -0.433904737234116f, 0.748115658760071f, -0.434095174074173f, + 0.747782647609711f, -0.434285342693329f, 0.747449457645416f, -0.434475272893906f, + 0.747116148471832f, -0.434664934873581f, 0.746782720088959f, -0.434854328632355f, + 0.746449112892151f, -0.435043483972549f, 0.746115326881409f, -0.435232400894165f, + 0.745781481266022f, -0.435421019792557f, 0.745447397232056f, -0.435609430074692f, + 0.745113253593445f, -0.435797542333603f, 0.744778931140900f, -0.435985416173935f, + 0.744444429874420f, -0.436173021793365f, 0.744109809398651f, -0.436360388994217f, + 0.743775069713593f, -0.436547487974167f, 0.743440151214600f, -0.436734348535538f, + 0.743105113506317f, -0.436920911073685f, 0.742769956588745f, -0.437107264995575f, + 0.742434620857239f, -0.437293320894241f, 0.742099165916443f, -0.437479138374329f, + 0.741763532161713f, -0.437664687633514f, 0.741427779197693f, -0.437849998474121f, + 0.741091907024384f, -0.438035041093826f, 0.740755856037140f, -0.438219845294952f, + 0.740419685840607f, -0.438404351472855f, 0.740083336830139f, -0.438588619232178f, + 0.739746868610382f, -0.438772648572922f, 0.739410281181335f, -0.438956409692764f, + 0.739073514938354f, -0.439139902591705f, 0.738736629486084f, -0.439323127269745f, + 0.738399624824524f, -0.439506113529205f, 0.738062441349030f, -0.439688831567764f, + 0.737725138664246f, -0.439871311187744f, 0.737387716770172f, -0.440053492784500f, + 0.737050116062164f, -0.440235435962677f, 0.736712396144867f, -0.440417140722275f, + 0.736374497413635f, -0.440598547458649f, 0.736036539077759f, -0.440779715776443f, + 0.735698342323303f, -0.440960645675659f, 0.735360085964203f, -0.441141277551651f, + 0.735021650791168f, -0.441321671009064f, 0.734683096408844f, -0.441501796245575f, + 0.734344422817230f, -0.441681683063507f, 0.734005570411682f, -0.441861271858215f, + 0.733666598796844f, -0.442040622234344f, 0.733327507972717f, -0.442219734191895f, + 0.732988238334656f, -0.442398548126221f, 0.732648849487305f, -0.442577123641968f, + 0.732309341430664f, -0.442755430936813f, 0.731969714164734f, -0.442933470010757f, + 0.731629908084869f, -0.443111270666122f, 0.731289982795715f, -0.443288803100586f, + 0.730949878692627f, -0.443466067314148f, 0.730609714984894f, -0.443643063306808f, + 0.730269372463226f, -0.443819820880890f, 0.729928910732269f, -0.443996280431747f, + 0.729588270187378f, -0.444172531366348f, 0.729247510433197f, -0.444348484277725f, + 0.728906631469727f, -0.444524168968201f, 0.728565633296967f, -0.444699615240097f, + 0.728224515914917f, -0.444874793291092f, 0.727883219718933f, -0.445049703121185f, + 0.727541804313660f, -0.445224374532700f, 0.727200269699097f, -0.445398747920990f, + 0.726858556270599f, -0.445572882890701f, 0.726516723632813f, -0.445746749639511f, + 0.726174771785736f, -0.445920348167419f, 0.725832700729370f, -0.446093708276749f, + 0.725490510463715f, -0.446266770362854f, 0.725148141384125f, -0.446439594030380f, + 0.724805653095245f, -0.446612149477005f, 0.724463045597076f, -0.446784436702728f, + 0.724120318889618f, -0.446956485509872f, 0.723777413368225f, -0.447128236293793f, + 0.723434448242188f, -0.447299748659134f, 0.723091304302216f, -0.447470992803574f, + 0.722747981548309f, -0.447641968727112f, 0.722404599189758f, -0.447812676429749f, + 0.722061097621918f, -0.447983115911484f, 0.721717417240143f, -0.448153316974640f, + 0.721373617649078f, -0.448323249816895f, 0.721029698848724f, -0.448492884635925f, + 0.720685660839081f, -0.448662281036377f, 0.720341444015503f, -0.448831409215927f, + 0.719997107982636f, -0.449000298976898f, 0.719652712345123f, -0.449168890714645f, + 0.719308137893677f, -0.449337244033813f, 0.718963444232941f, -0.449505299329758f, + 0.718618571758270f, -0.449673116207123f, 0.718273639678955f, -0.449840664863586f, + 0.717928528785706f, -0.450007945299149f, 0.717583298683167f, -0.450174957513809f, + 0.717238008975983f, -0.450341701507568f, 0.716892480850220f, -0.450508207082748f, + 0.716546893119812f, -0.450674414634705f, 0.716201186180115f, -0.450840383768082f, + 0.715855300426483f, -0.451006084680557f, 0.715509355068207f, -0.451171487569809f, + 0.715163230895996f, -0.451336652040482f, 0.714816987514496f, -0.451501548290253f, + 0.714470624923706f, -0.451666176319122f, 0.714124143123627f, -0.451830536127090f, + 0.713777542114258f, -0.451994657516479f, 0.713430821895599f, -0.452158480882645f, + 0.713083922863007f, -0.452322036027908f, 0.712736964225769f, -0.452485352754593f, + 0.712389826774597f, -0.452648371458054f, 0.712042629718781f, -0.452811151742935f, + 0.711695253849030f, -0.452973634004593f, 0.711347758769989f, -0.453135877847672f, + 0.711000144481659f, -0.453297853469849f, 0.710652410984039f, -0.453459560871124f, + 0.710304558277130f, -0.453621000051498f, 0.709956526756287f, -0.453782171010971f, + 0.709608435630798f, -0.453943043947220f, 0.709260225296021f, -0.454103678464890f, + 0.708911836147308f, -0.454264044761658f, 0.708563387393951f, -0.454424172639847f, + 0.708214759826660f, -0.454584002494812f, 0.707866072654724f, -0.454743564128876f, + 0.707517206668854f, -0.454902857542038f, 0.707168221473694f, -0.455061882734299f, + 0.706819176673889f, -0.455220639705658f, 0.706469953060150f, -0.455379128456116f, + 0.706120610237122f, -0.455537378787994f, 0.705771148204803f, -0.455695331096649f, + 0.705421566963196f, -0.455853015184402f, 0.705071866512299f, -0.456010431051254f, + 0.704722046852112f, -0.456167578697205f, 0.704372167587280f, -0.456324487924576f, + 0.704022109508514f, -0.456481099128723f, 0.703671932220459f, -0.456637442111969f, + 0.703321635723114f, -0.456793516874313f, 0.702971220016479f, -0.456949323415756f, + 0.702620685100555f, -0.457104891538620f, 0.702270030975342f, -0.457260161638260f, + 0.701919257640839f, -0.457415163516998f, 0.701568365097046f, -0.457569897174835f, + 0.701217353343964f, -0.457724362611771f, 0.700866222381592f, -0.457878559827805f, + 0.700514972209930f, -0.458032488822937f, 0.700163602828979f, -0.458186149597168f, + 0.699812114238739f, -0.458339542150497f, 0.699460506439209f, -0.458492636680603f, + 0.699108779430389f, -0.458645492792130f, 0.698756933212280f, -0.458798080682755f, + 0.698404967784882f, -0.458950400352478f, 0.698052942752838f, -0.459102421998978f, + 0.697700738906860f, -0.459254205226898f, 0.697348415851593f, -0.459405690431595f, + 0.696996033191681f, -0.459556937217712f, 0.696643471717834f, -0.459707885980606f, + 0.696290850639343f, -0.459858566522598f, 0.695938050746918f, -0.460008978843689f, + 0.695585191249847f, -0.460159152746201f, 0.695232212543488f, -0.460309028625488f, + 0.694879114627838f, -0.460458606481552f, 0.694525837898254f, -0.460607945919037f, + 0.694172501564026f, -0.460757017135620f, 0.693819046020508f, -0.460905820131302f, + 0.693465530872345f, -0.461054325103760f, 0.693111836910248f, -0.461202591657639f, + 0.692758023738861f, -0.461350560188293f, 0.692404091358185f, -0.461498260498047f, + 0.692050099372864f, -0.461645722389221f, 0.691695988178253f, -0.461792886257172f, + 0.691341698169708f, -0.461939752101898f, 0.690987348556519f, -0.462086379528046f, + 0.690632879734039f, -0.462232738733292f, 0.690278291702271f, -0.462378799915314f, + 0.689923584461212f, -0.462524622678757f, 0.689568817615509f, -0.462670147418976f, + 0.689213871955872f, -0.462815403938293f, 0.688858866691589f, -0.462960392236710f, + 0.688503682613373f, -0.463105112314224f, 0.688148438930511f, -0.463249564170837f, + 0.687793076038361f, -0.463393747806549f, 0.687437593936920f, -0.463537633419037f, + 0.687082052230835f, -0.463681250810623f, 0.686726331710815f, -0.463824629783630f, + 0.686370551586151f, -0.463967710733414f, 0.686014592647552f, -0.464110493659973f, + 0.685658574104309f, -0.464253038167953f, 0.685302436351776f, -0.464395314455032f, + 0.684946238994598f, -0.464537292718887f, 0.684589862823486f, -0.464679002761841f, + 0.684233427047729f, -0.464820444583893f, 0.683876872062683f, -0.464961618185043f, + 0.683520197868347f, -0.465102523565292f, 0.683163404464722f, -0.465243130922318f, + 0.682806491851807f, -0.465383470058441f, 0.682449519634247f, -0.465523540973663f, + 0.682092368602753f, -0.465663343667984f, 0.681735157966614f, -0.465802878141403f, + 0.681377887725830f, -0.465942144393921f, 0.681020438671112f, -0.466081112623215f, + 0.680662930011749f, -0.466219812631607f, 0.680305242538452f, -0.466358244419098f, + 0.679947495460510f, -0.466496407985687f, 0.679589688777924f, -0.466634273529053f, + 0.679231703281403f, -0.466771900653839f, 0.678873658180237f, -0.466909229755402f, + 0.678515493869781f, -0.467046260833740f, 0.678157210350037f, -0.467183053493500f, + 0.677798807621002f, -0.467319577932358f, 0.677440345287323f, -0.467455804347992f, + 0.677081763744354f, -0.467591762542725f, 0.676723062992096f, -0.467727422714233f, + 0.676364302635193f, -0.467862844467163f, 0.676005363464355f, -0.467997968196869f, + 0.675646364688873f, -0.468132823705673f, 0.675287246704102f, -0.468267410993576f, + 0.674928069114685f, -0.468401730060577f, 0.674568772315979f, -0.468535751104355f, + 0.674209356307983f, -0.468669503927231f, 0.673849821090698f, -0.468802988529205f, + 0.673490226268768f, -0.468936175107956f, 0.673130512237549f, -0.469069123268127f, + 0.672770678997040f, -0.469201773405075f, 0.672410726547241f, -0.469334155321121f, + 0.672050714492798f, -0.469466239213943f, 0.671690583229065f, -0.469598054885864f, + 0.671330332756042f, -0.469729602336884f, 0.670970022678375f, -0.469860881567001f, + 0.670609593391418f, -0.469991862773895f, 0.670249044895172f, -0.470122605562210f, + 0.669888436794281f, -0.470253020524979f, 0.669527709484100f, -0.470383197069168f, + 0.669166862964630f, -0.470513075590134f, 0.668805956840515f, -0.470642685890198f, + 0.668444931507111f, -0.470772027969360f, 0.668083786964417f, -0.470901101827621f, + 0.667722582817078f, -0.471029877662659f, 0.667361259460449f, -0.471158385276794f, + 0.666999816894531f, -0.471286594867706f, 0.666638314723969f, -0.471414536237717f, + 0.666276693344116f, -0.471542209386826f, 0.665914952754974f, -0.471669614315033f, + 0.665553152561188f, -0.471796721220016f, 0.665191233158112f, -0.471923559904099f, + 0.664829254150391f, -0.472050130367279f, 0.664467096328735f, -0.472176402807236f, + 0.664104938507080f, -0.472302407026291f, 0.663742601871490f, -0.472428143024445f, + 0.663380205631256f, -0.472553610801697f, 0.663017749786377f, -0.472678780555725f, + 0.662655174732208f, -0.472803652286530f, 0.662292480468750f, -0.472928285598755f, + 0.661929666996002f, -0.473052620887756f, 0.661566793918610f, -0.473176687955856f, + 0.661203861236572f, -0.473300457000732f, 0.660840749740601f, -0.473423957824707f, + 0.660477638244629f, -0.473547190427780f, 0.660114347934723f, -0.473670125007629f, + 0.659750998020172f, -0.473792791366577f, 0.659387588500977f, -0.473915189504623f, + 0.659024059772491f, -0.474037289619446f, 0.658660411834717f, -0.474159121513367f, + 0.658296704292297f, -0.474280685186386f, 0.657932877540588f, -0.474401950836182f, + 0.657568991184235f, -0.474522948265076f, 0.657204985618591f, -0.474643647670746f, + 0.656840860843658f, -0.474764078855515f, 0.656476676464081f, -0.474884241819382f, + 0.656112432479858f, -0.475004136562347f, 0.655748009681702f, -0.475123733282089f, + 0.655383586883545f, -0.475243031978607f, 0.655019044876099f, -0.475362062454224f, + 0.654654383659363f, -0.475480824708939f, 0.654289662837982f, -0.475599318742752f, + 0.653924822807312f, -0.475717514753342f, 0.653559923171997f, -0.475835442543030f, + 0.653194904327393f, -0.475953072309494f, 0.652829825878143f, -0.476070433855057f, + 0.652464628219604f, -0.476187497377396f, 0.652099311351776f, -0.476304292678833f, + 0.651733994483948f, -0.476420819759369f, 0.651368498802185f, -0.476537048816681f, + 0.651003003120422f, -0.476653009653091f, 0.650637328624725f, -0.476768702268600f, + 0.650271594524384f, -0.476884096860886f, 0.649905800819397f, -0.476999223232269f, + 0.649539887905121f, -0.477114051580429f, 0.649173915386200f, -0.477228611707687f, + 0.648807883262634f, -0.477342873811722f, 0.648441672325134f, -0.477456867694855f, + 0.648075461387634f, -0.477570593357086f, 0.647709131240845f, -0.477684020996094f, + 0.647342681884766f, -0.477797180414200f, 0.646976172924042f, -0.477910041809082f, + 0.646609604358673f, -0.478022634983063f, 0.646242916584015f, -0.478134930133820f, + 0.645876109600067f, -0.478246957063675f, 0.645509302616119f, -0.478358715772629f, + 0.645142316818237f, -0.478470176458359f, 0.644775331020355f, -0.478581339120865f, + 0.644408226013184f, -0.478692263364792f, 0.644041001796722f, -0.478802859783173f, + 0.643673717975616f, -0.478913217782974f, 0.643306374549866f, -0.479023247957230f, + 0.642938911914825f, -0.479133039712906f, 0.642571389675140f, -0.479242533445358f, + 0.642203748226166f, -0.479351729154587f, 0.641836047172546f, -0.479460656642914f, + 0.641468286514282f, -0.479569315910339f, 0.641100406646729f, -0.479677677154541f, + 0.640732467174530f, -0.479785770177841f, 0.640364408493042f, -0.479893565177917f, + 0.639996349811554f, -0.480001062154770f, 0.639628112316132f, -0.480108320713043f, + 0.639259815216064f, -0.480215251445770f, 0.638891458511353f, -0.480321943759918f, + 0.638523042201996f, -0.480428308248520f, 0.638154506683350f, -0.480534434318542f, + 0.637785911560059f, -0.480640232563019f, 0.637417197227478f, -0.480745792388916f, + 0.637048482894897f, -0.480851024389267f, 0.636679589748383f, -0.480956017971039f, + 0.636310696601868f, -0.481060713529587f, 0.635941684246063f, -0.481165111064911f, + 0.635572552680969f, -0.481269240379334f, 0.635203421115875f, -0.481373071670532f, + 0.634834170341492f, -0.481476634740829f, 0.634464859962463f, -0.481579899787903f, + 0.634095430374146f, -0.481682896614075f, 0.633725941181183f, -0.481785595417023f, + 0.633356392383575f, -0.481888025999069f, 0.632986724376678f, -0.481990188360214f, + 0.632616996765137f, -0.482092022895813f, 0.632247209548950f, -0.482193619012833f, + 0.631877362728119f, -0.482294887304306f, 0.631507396697998f, -0.482395917177200f, + 0.631137371063232f, -0.482496619224548f, 0.630767226219177f, -0.482597053050995f, + 0.630397081375122f, -0.482697218656540f, 0.630026817321777f, -0.482797086238861f, + 0.629656434059143f, -0.482896685600281f, 0.629286050796509f, -0.482995986938477f, + 0.628915548324585f, -0.483094990253448f, 0.628544986248016f, -0.483193725347519f, + 0.628174364566803f, -0.483292192220688f, 0.627803623676300f, -0.483390361070633f, + 0.627432823181152f, -0.483488231897354f, 0.627061963081360f, -0.483585834503174f, + 0.626691043376923f, -0.483683139085770f, 0.626320004463196f, -0.483780175447464f, + 0.625948905944824f, -0.483876913785934f, 0.625577747821808f, -0.483973383903503f, + 0.625206530094147f, -0.484069555997849f, 0.624835193157196f, -0.484165430068970f, + 0.624463796615601f, -0.484261035919189f, 0.624092340469360f, -0.484356373548508f, + 0.623720824718475f, -0.484451413154602f, 0.623349189758301f, -0.484546154737473f, + 0.622977554798126f, -0.484640628099442f, 0.622605800628662f, -0.484734803438187f, + 0.622233927249908f, -0.484828680753708f, 0.621862053871155f, -0.484922289848328f, + 0.621490061283112f, -0.485015630722046f, 0.621118068695068f, -0.485108673572540f, + 0.620745956897736f, -0.485201418399811f, 0.620373785495758f, -0.485293895006180f, + 0.620001494884491f, -0.485386073589325f, 0.619629204273224f, -0.485477954149246f, + 0.619256794452667f, -0.485569566488266f, 0.618884325027466f, -0.485660910606384f, + 0.618511795997620f, -0.485751956701279f, 0.618139207363129f, -0.485842704772949f, + 0.617766559123993f, -0.485933154821396f, 0.617393791675568f, -0.486023366451263f, + 0.617020964622498f, -0.486113250255585f, 0.616648077964783f, -0.486202865839005f, + 0.616275131702423f, -0.486292183399200f, 0.615902125835419f, -0.486381232738495f, + 0.615529060363770f, -0.486469984054565f, 0.615155875682831f, -0.486558437347412f, + 0.614782691001892f, -0.486646622419357f, 0.614409387111664f, -0.486734509468079f, + 0.614036023616791f, -0.486822128295898f, 0.613662600517273f, -0.486909449100494f, + 0.613289117813110f, -0.486996471881866f, 0.612915575504303f, -0.487083226442337f, + 0.612541973590851f, -0.487169682979584f, 0.612168252468109f, -0.487255871295929f, + 0.611794531345367f, -0.487341761589050f, 0.611420691013336f, -0.487427353858948f, + 0.611046791076660f, -0.487512677907944f, 0.610672831535339f, -0.487597703933716f, + 0.610298871994019f, -0.487682431936264f, 0.609924793243408f, -0.487766891717911f, + 0.609550595283508f, -0.487851053476334f, 0.609176397323608f, -0.487934947013855f, + 0.608802139759064f, -0.488018542528152f, 0.608427822589874f, -0.488101840019226f, + 0.608053386211395f, -0.488184869289398f, 0.607678949832916f, -0.488267600536346f, + 0.607304394245148f, -0.488350033760071f, 0.606929838657379f, -0.488432198762894f, + 0.606555163860321f, -0.488514065742493f, 0.606180429458618f, -0.488595664501190f, + 0.605805635452271f, -0.488676935434341f, 0.605430841445923f, -0.488757967948914f, + 0.605055928230286f, -0.488838672637939f, 0.604680955410004f, -0.488919109106064f, + 0.604305922985077f, -0.488999247550964f, 0.603930830955505f, -0.489079117774963f, + 0.603555679321289f, -0.489158689975739f, 0.603180468082428f, -0.489237964153290f, + 0.602805197238922f, -0.489316970109940f, 0.602429866790771f, -0.489395678043365f, + 0.602054476737976f, -0.489474087953568f, 0.601679027080536f, -0.489552229642868f, + 0.601303517818451f, -0.489630073308945f, 0.600927948951721f, -0.489707618951797f, + 0.600552320480347f, -0.489784896373749f, 0.600176632404327f, -0.489861875772476f, + 0.599800884723663f, -0.489938557147980f, 0.599425077438354f, -0.490014940500259f, + 0.599049210548401f, -0.490091055631638f, 0.598673284053802f, -0.490166902542114f, + 0.598297297954559f, -0.490242421627045f, 0.597921252250671f, -0.490317672491074f, + 0.597545146942139f, -0.490392625331879f, 0.597168982028961f, -0.490467309951782f, + 0.596792817115784f, -0.490541696548462f, 0.596416532993317f, -0.490615785121918f, + 0.596040189266205f, -0.490689605474472f, 0.595663845539093f, -0.490763127803802f, + 0.595287382602692f, -0.490836352109909f, 0.594910860061646f, -0.490909278392792f, + 0.594534337520599f, -0.490981936454773f, 0.594157755374908f, -0.491054296493530f, + 0.593781054019928f, -0.491126358509064f, 0.593404352664948f, -0.491198152303696f, + 0.593027591705322f, -0.491269648075104f, 0.592650771141052f, -0.491340845823288f, + 0.592273890972137f, -0.491411775350571f, 0.591896951198578f, -0.491482406854630f, + 0.591519951820374f, -0.491552740335464f, 0.591142892837524f, -0.491622805595398f, + 0.590765833854675f, -0.491692543029785f, 0.590388655662537f, -0.491762012243271f, + 0.590011477470398f, -0.491831213235855f, 0.589634180068970f, -0.491900116205215f, + 0.589256882667542f, -0.491968721151352f, 0.588879525661469f, -0.492037028074265f, + 0.588502109050751f, -0.492105036973953f, 0.588124632835388f, -0.492172777652740f, + 0.587747097015381f, -0.492240220308304f, 0.587369561195374f, -0.492307394742966f, + 0.586991965770721f, -0.492374241352081f, 0.586614251136780f, -0.492440819740295f, + 0.586236536502838f, -0.492507129907608f, 0.585858762264252f, -0.492573112249374f, + 0.585480928421021f, -0.492638826370239f, 0.585103094577789f, -0.492704242467880f, + 0.584725141525269f, -0.492769360542297f, 0.584347188472748f, -0.492834210395813f, + 0.583969175815582f, -0.492898762226105f, 0.583591103553772f, -0.492963016033173f, + 0.583212971687317f, -0.493026971817017f, 0.582834780216217f, -0.493090659379959f, + 0.582456588745117f, -0.493154048919678f, 0.582078278064728f, -0.493217140436172f, + 0.581699967384338f, -0.493279963731766f, 0.581321597099304f, -0.493342459201813f, + 0.580943167209625f, -0.493404686450958f, 0.580564737319946f, -0.493466645479202f, + 0.580186247825623f, -0.493528276681900f, 0.579807698726654f, -0.493589639663696f, + 0.579429090023041f, -0.493650704622269f, 0.579050421714783f, -0.493711471557617f, + 0.578671753406525f, -0.493771970272064f, 0.578292965888977f, -0.493832170963287f, + 0.577914178371429f, -0.493892073631287f, 0.577535390853882f, -0.493951678276062f, + 0.577156484127045f, -0.494011014699936f, 0.576777577400208f, -0.494070053100586f, + 0.576398611068726f, -0.494128793478012f, 0.576019585132599f, -0.494187235832214f, + 0.575640499591827f, -0.494245409965515f, 0.575261414051056f, -0.494303256273270f, + 0.574882268905640f, -0.494360834360123f, 0.574503064155579f, -0.494418144226074f, + 0.574123859405518f, -0.494475126266479f, 0.573744535446167f, -0.494531840085983f, + 0.573365211486816f, -0.494588255882263f, 0.572985887527466f, -0.494644373655319f, + 0.572606444358826f, -0.494700223207474f, 0.572227001190186f, -0.494755744934082f, + 0.571847498416901f, -0.494810998439789f, 0.571467995643616f, -0.494865983724594f, + 0.571088373661041f, -0.494920641183853f, 0.570708811283112f, -0.494975030422211f, + 0.570329129695892f, -0.495029091835022f, 0.569949388504028f, -0.495082914829254f, + 0.569569647312164f, -0.495136409997940f, 0.569189906120300f, -0.495189607143402f, + 0.568810045719147f, -0.495242536067963f, 0.568430185317993f, -0.495295166969299f, + 0.568050265312195f, -0.495347499847412f, 0.567670345306396f, -0.495399564504623f, + 0.567290365695953f, -0.495451331138611f, 0.566910326480865f, -0.495502769947052f, + 0.566530287265778f, -0.495553970336914f, 0.566150128841400f, -0.495604842901230f, + 0.565770030021667f, -0.495655417442322f, 0.565389811992645f, -0.495705723762512f, + 0.565009593963623f, -0.495755732059479f, 0.564629375934601f, -0.495805442333221f, + 0.564249038696289f, -0.495854884386063f, 0.563868701457977f, -0.495903998613358f, + 0.563488364219666f, -0.495952844619751f, 0.563107967376709f, -0.496001392602921f, + 0.562727510929108f, -0.496049642562866f, 0.562346994876862f, -0.496097624301910f, + 0.561966478824615f, -0.496145308017731f, 0.561585903167725f, -0.496192663908005f, + 0.561205327510834f, -0.496239781379700f, 0.560824692249298f, -0.496286571025848f, + 0.560444056987762f, -0.496333062648773f, 0.560063362121582f, -0.496379286050797f, + 0.559682607650757f, -0.496425211429596f, 0.559301853179932f, -0.496470838785172f, + 0.558921039104462f, -0.496516168117523f, 0.558540165424347f, -0.496561229228973f, + 0.558159291744232f, -0.496605962514877f, 0.557778418064117f, -0.496650427579880f, + 0.557397484779358f, -0.496694594621658f, 0.557016491889954f, -0.496738493442535f, + 0.556635499000549f, -0.496782064437866f, 0.556254446506500f, -0.496825367212296f, + 0.555873334407806f, -0.496868371963501f, 0.555492222309113f, -0.496911078691483f, + 0.555111110210419f, -0.496953487396240f, 0.554729938507080f, -0.496995598077774f, + 0.554348707199097f, -0.497037440538406f, 0.553967475891113f, -0.497078984975815f, + 0.553586184978485f, -0.497120231389999f, 0.553204894065857f, -0.497161179780960f, + 0.552823603153229f, -0.497201830148697f, 0.552442193031311f, -0.497242212295532f, + 0.552060842514038f, -0.497282296419144f, 0.551679372787476f, -0.497322082519531f, + 0.551297962665558f, -0.497361570596695f, 0.550916433334351f, -0.497400760650635f, + 0.550534904003143f, -0.497439652681351f, 0.550153374671936f, -0.497478276491165f, + 0.549771785736084f, -0.497516602277756f, 0.549390196800232f, -0.497554630041122f, + 0.549008548259735f, -0.497592359781265f, 0.548626899719238f, -0.497629791498184f, + 0.548245191574097f, -0.497666954994202f, 0.547863483428955f, -0.497703820466995f, + 0.547481775283813f, -0.497740387916565f, 0.547099947929382f, -0.497776657342911f, + 0.546718180179596f, -0.497812628746033f, 0.546336352825165f, -0.497848302125931f, + 0.545954465866089f, -0.497883707284927f, 0.545572578907013f, -0.497918814420700f, + 0.545190691947937f, -0.497953623533249f, 0.544808745384216f, -0.497988134622574f, + 0.544426798820496f, -0.498022347688675f, 0.544044792652130f, -0.498056292533875f, + 0.543662786483765f, -0.498089909553528f, 0.543280720710754f, -0.498123258352280f, + 0.542898654937744f, -0.498156309127808f, 0.542516589164734f, -0.498189061880112f, + 0.542134463787079f, -0.498221516609192f, 0.541752278804779f, -0.498253703117371f, + 0.541370153427124f, -0.498285561800003f, 0.540987968444824f, -0.498317152261734f, + 0.540605723857880f, -0.498348444700241f, 0.540223479270935f, -0.498379439115524f, + 0.539841234683990f, -0.498410135507584f, 0.539458930492401f, -0.498440563678741f, + 0.539076626300812f, -0.498470664024353f, 0.538694262504578f, -0.498500496149063f, + 0.538311958312988f, -0.498530030250549f, 0.537929534912109f, -0.498559266328812f, + 0.537547171115875f, -0.498588204383850f, 0.537164747714996f, -0.498616874217987f, + 0.536782264709473f, -0.498645216226578f, 0.536399841308594f, -0.498673290014267f, + 0.536017298698425f, -0.498701065778732f, 0.535634815692902f, -0.498728543519974f, + 0.535252273082733f, -0.498755723237991f, 0.534869730472565f, -0.498782604932785f, + 0.534487187862396f, -0.498809218406677f, 0.534104585647583f, -0.498835533857346f, + 0.533721983432770f, -0.498861521482468f, 0.533339321613312f, -0.498887240886688f, + 0.532956659793854f, -0.498912662267685f, 0.532573997974396f, -0.498937815427780f, + 0.532191336154938f, -0.498962640762329f, 0.531808614730835f, -0.498987197875977f, + 0.531425893306732f, -0.499011427164078f, 0.531043112277985f, -0.499035388231277f, + 0.530660390853882f, -0.499059051275253f, 0.530277609825134f, -0.499082416296005f, + 0.529894769191742f, -0.499105513095856f, 0.529511988162994f, -0.499128282070160f, + 0.529129147529602f, -0.499150782823563f, 0.528746306896210f, -0.499172955751419f, + 0.528363406658173f, -0.499194860458374f, 0.527980506420136f, -0.499216467142105f, + 0.527597606182098f, -0.499237775802612f, 0.527214705944061f, -0.499258816242218f, + 0.526831746101379f, -0.499279528856277f, 0.526448845863342f, -0.499299973249435f, + 0.526065826416016f, -0.499320119619370f, 0.525682866573334f, -0.499339967966080f, + 0.525299847126007f, -0.499359518289566f, 0.524916887283325f, -0.499378770589828f, + 0.524533808231354f, -0.499397724866867f, 0.524150788784027f, -0.499416410923004f, + 0.523767769336700f, -0.499434769153595f, 0.523384690284729f, -0.499452859163284f, + 0.523001611232758f, -0.499470651149750f, 0.522618472576141f, -0.499488145112991f, + 0.522235393524170f, -0.499505341053009f, 0.521852254867554f, -0.499522238969803f, + 0.521469116210938f, -0.499538868665695f, 0.521085977554321f, -0.499555170536041f, + 0.520702838897705f, -0.499571204185486f, 0.520319640636444f, -0.499586939811707f, + 0.519936442375183f, -0.499602377414703f, 0.519553244113922f, -0.499617516994476f, + 0.519170045852661f, -0.499632388353348f, 0.518786847591400f, -0.499646931886673f, + 0.518403589725494f, -0.499661177396774f, 0.518020391464233f, -0.499675154685974f, + 0.517637133598328f, -0.499688833951950f, 0.517253875732422f, -0.499702215194702f, + 0.516870558261871f, -0.499715298414230f, 0.516487300395966f, -0.499728083610535f, + 0.516103982925415f, -0.499740600585938f, 0.515720725059509f, -0.499752789735794f, + 0.515337407588959f, -0.499764710664749f, 0.514954090118408f, -0.499776333570480f, + 0.514570772647858f, -0.499787658452988f, 0.514187395572662f, -0.499798685312271f, + 0.513804078102112f, -0.499809414148331f, 0.513420701026917f, -0.499819844961166f, + 0.513037383556366f, -0.499830007553101f, 0.512654006481171f, -0.499839842319489f, + 0.512270629405975f, -0.499849408864975f, 0.511887252330780f, -0.499858677387238f, + 0.511503815650940f, -0.499867647886276f, 0.511120438575745f, -0.499876320362091f, + 0.510737061500549f, -0.499884694814682f, 0.510353624820709f, -0.499892801046371f, + 0.509970188140869f, -0.499900579452515f, 0.509586811065674f, -0.499908089637756f, + 0.509203374385834f, -0.499915301799774f, 0.508819937705994f, -0.499922215938568f, + 0.508436501026154f, -0.499928832054138f, 0.508053064346313f, -0.499935150146484f, + 0.507669627666473f, -0.499941170215607f, 0.507286131381989f, -0.499946922063828f, + 0.506902694702148f, -0.499952346086502f, 0.506519258022308f, -0.499957501888275f, + 0.506135761737823f, -0.499962359666824f, 0.505752325057983f, -0.499966919422150f, + 0.505368828773499f, -0.499971181154251f, 0.504985332489014f, -0.499975144863129f, + 0.504601895809174f, -0.499978810548782f, 0.504218399524689f, -0.499982208013535f, + 0.503834903240204f, -0.499985307455063f, 0.503451406955719f, -0.499988079071045f, + 0.503067970275879f, -0.499990582466125f, 0.502684473991394f, -0.499992787837982f, + 0.502300977706909f, -0.499994695186615f, 0.501917481422424f, -0.499996334314346f, + 0.501533985137939f, -0.499997645616531f, 0.501150488853455f, -0.499998688697815f, + 0.500766992568970f, -0.499999403953552f, 0.500383496284485f, -0.499999850988388f, +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31) +/** + @par + Generation fixed-point realCoefAQ31 array in Q31 format: + @par + n = 4096 +
for (i = 0; i < n; i++)
+  {
+     pATable[2 * i]     = 0.5 * ( 1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+     pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ @par + Convert to fixed point Q31 format + round(pATable[i] * pow(2, 31)) +*/ +const q31_t realCoefAQ31[8192] = { + (q31_t)0x40000000, (q31_t)0xc0000000, (q31_t)0x3ff36f02, (q31_t)0xc000013c, + (q31_t)0x3fe6de05, (q31_t)0xc00004ef, (q31_t)0x3fda4d09, (q31_t)0xc0000b1a, + (q31_t)0x3fcdbc0f, (q31_t)0xc00013bd, (q31_t)0x3fc12b16, (q31_t)0xc0001ed8, + (q31_t)0x3fb49a1f, (q31_t)0xc0002c6a, (q31_t)0x3fa8092c, (q31_t)0xc0003c74, + (q31_t)0x3f9b783c, (q31_t)0xc0004ef5, (q31_t)0x3f8ee750, (q31_t)0xc00063ee, + (q31_t)0x3f825668, (q31_t)0xc0007b5f, (q31_t)0x3f75c585, (q31_t)0xc0009547, + (q31_t)0x3f6934a8, (q31_t)0xc000b1a7, (q31_t)0x3f5ca3d0, (q31_t)0xc000d07e, + (q31_t)0x3f5012fe, (q31_t)0xc000f1ce, (q31_t)0x3f438234, (q31_t)0xc0011594, + (q31_t)0x3f36f170, (q31_t)0xc0013bd3, (q31_t)0x3f2a60b4, (q31_t)0xc0016489, + (q31_t)0x3f1dd001, (q31_t)0xc0018fb6, (q31_t)0x3f113f56, (q31_t)0xc001bd5c, + (q31_t)0x3f04aeb5, (q31_t)0xc001ed78, (q31_t)0x3ef81e1d, (q31_t)0xc002200d, + (q31_t)0x3eeb8d8f, (q31_t)0xc0025519, (q31_t)0x3edefd0c, (q31_t)0xc0028c9c, + (q31_t)0x3ed26c94, (q31_t)0xc002c697, (q31_t)0x3ec5dc28, (q31_t)0xc003030a, + (q31_t)0x3eb94bc8, (q31_t)0xc00341f4, (q31_t)0x3eacbb74, (q31_t)0xc0038356, + (q31_t)0x3ea02b2e, (q31_t)0xc003c72f, (q31_t)0x3e939af5, (q31_t)0xc0040d80, + (q31_t)0x3e870aca, (q31_t)0xc0045648, (q31_t)0x3e7a7aae, (q31_t)0xc004a188, + (q31_t)0x3e6deaa1, (q31_t)0xc004ef3f, (q31_t)0x3e615aa3, (q31_t)0xc0053f6e, + (q31_t)0x3e54cab5, (q31_t)0xc0059214, (q31_t)0x3e483ad8, (q31_t)0xc005e731, + (q31_t)0x3e3bab0b, (q31_t)0xc0063ec6, (q31_t)0x3e2f1b50, (q31_t)0xc00698d3, + (q31_t)0x3e228ba7, (q31_t)0xc006f556, (q31_t)0x3e15fc11, (q31_t)0xc0075452, + (q31_t)0x3e096c8d, (q31_t)0xc007b5c4, (q31_t)0x3dfcdd1d, (q31_t)0xc00819ae, + (q31_t)0x3df04dc0, (q31_t)0xc008800f, (q31_t)0x3de3be78, (q31_t)0xc008e8e8, + (q31_t)0x3dd72f45, (q31_t)0xc0095438, (q31_t)0x3dcaa027, (q31_t)0xc009c1ff, + (q31_t)0x3dbe111e, (q31_t)0xc00a323d, (q31_t)0x3db1822c, (q31_t)0xc00aa4f3, + (q31_t)0x3da4f351, (q31_t)0xc00b1a20, (q31_t)0x3d98648d, (q31_t)0xc00b91c4, + (q31_t)0x3d8bd5e1, (q31_t)0xc00c0be0, (q31_t)0x3d7f474d, (q31_t)0xc00c8872, + (q31_t)0x3d72b8d2, (q31_t)0xc00d077c, (q31_t)0x3d662a70, (q31_t)0xc00d88fd, + (q31_t)0x3d599c28, (q31_t)0xc00e0cf5, (q31_t)0x3d4d0df9, (q31_t)0xc00e9364, + (q31_t)0x3d407fe6, (q31_t)0xc00f1c4a, (q31_t)0x3d33f1ed, (q31_t)0xc00fa7a8, + (q31_t)0x3d276410, (q31_t)0xc010357c, (q31_t)0x3d1ad650, (q31_t)0xc010c5c7, + (q31_t)0x3d0e48ab, (q31_t)0xc011588a, (q31_t)0x3d01bb24, (q31_t)0xc011edc3, + (q31_t)0x3cf52dbb, (q31_t)0xc0128574, (q31_t)0x3ce8a06f, (q31_t)0xc0131f9b, + (q31_t)0x3cdc1342, (q31_t)0xc013bc39, (q31_t)0x3ccf8634, (q31_t)0xc0145b4e, + (q31_t)0x3cc2f945, (q31_t)0xc014fcda, (q31_t)0x3cb66c77, (q31_t)0xc015a0dd, + (q31_t)0x3ca9dfc8, (q31_t)0xc0164757, (q31_t)0x3c9d533b, (q31_t)0xc016f047, + (q31_t)0x3c90c6cf, (q31_t)0xc0179bae, (q31_t)0x3c843a85, (q31_t)0xc018498c, + (q31_t)0x3c77ae5e, (q31_t)0xc018f9e1, (q31_t)0x3c6b2259, (q31_t)0xc019acac, + (q31_t)0x3c5e9678, (q31_t)0xc01a61ee, (q31_t)0x3c520aba, (q31_t)0xc01b19a7, + (q31_t)0x3c457f21, (q31_t)0xc01bd3d6, (q31_t)0x3c38f3ac, (q31_t)0xc01c907c, + (q31_t)0x3c2c685d, (q31_t)0xc01d4f99, (q31_t)0x3c1fdd34, (q31_t)0xc01e112b, + (q31_t)0x3c135231, (q31_t)0xc01ed535, (q31_t)0x3c06c754, (q31_t)0xc01f9bb5, + (q31_t)0x3bfa3c9f, (q31_t)0xc02064ab, (q31_t)0x3bedb212, (q31_t)0xc0213018, + (q31_t)0x3be127ac, (q31_t)0xc021fdfb, (q31_t)0x3bd49d70, (q31_t)0xc022ce54, + (q31_t)0x3bc8135c, (q31_t)0xc023a124, (q31_t)0x3bbb8973, (q31_t)0xc024766a, + (q31_t)0x3baeffb3, (q31_t)0xc0254e27, (q31_t)0x3ba2761e, (q31_t)0xc0262859, + (q31_t)0x3b95ecb4, (q31_t)0xc0270502, (q31_t)0x3b896375, (q31_t)0xc027e421, + (q31_t)0x3b7cda63, (q31_t)0xc028c5b6, (q31_t)0x3b70517d, (q31_t)0xc029a9c1, + (q31_t)0x3b63c8c4, (q31_t)0xc02a9042, (q31_t)0x3b574039, (q31_t)0xc02b7939, + (q31_t)0x3b4ab7db, (q31_t)0xc02c64a6, (q31_t)0x3b3e2fac, (q31_t)0xc02d5289, + (q31_t)0x3b31a7ac, (q31_t)0xc02e42e2, (q31_t)0x3b251fdc, (q31_t)0xc02f35b1, + (q31_t)0x3b18983b, (q31_t)0xc0302af5, (q31_t)0x3b0c10cb, (q31_t)0xc03122b0, + (q31_t)0x3aff898c, (q31_t)0xc0321ce0, (q31_t)0x3af3027e, (q31_t)0xc0331986, + (q31_t)0x3ae67ba2, (q31_t)0xc03418a2, (q31_t)0x3ad9f4f8, (q31_t)0xc0351a33, + (q31_t)0x3acd6e81, (q31_t)0xc0361e3a, (q31_t)0x3ac0e83d, (q31_t)0xc03724b6, + (q31_t)0x3ab4622d, (q31_t)0xc0382da8, (q31_t)0x3aa7dc52, (q31_t)0xc0393910, + (q31_t)0x3a9b56ab, (q31_t)0xc03a46ed, (q31_t)0x3a8ed139, (q31_t)0xc03b573f, + (q31_t)0x3a824bfd, (q31_t)0xc03c6a07, (q31_t)0x3a75c6f8, (q31_t)0xc03d7f44, + (q31_t)0x3a694229, (q31_t)0xc03e96f6, (q31_t)0x3a5cbd91, (q31_t)0xc03fb11d, + (q31_t)0x3a503930, (q31_t)0xc040cdba, (q31_t)0x3a43b508, (q31_t)0xc041eccc, + (q31_t)0x3a373119, (q31_t)0xc0430e53, (q31_t)0x3a2aad62, (q31_t)0xc044324f, + (q31_t)0x3a1e29e5, (q31_t)0xc04558c0, (q31_t)0x3a11a6a3, (q31_t)0xc04681a6, + (q31_t)0x3a05239a, (q31_t)0xc047ad01, (q31_t)0x39f8a0cd, (q31_t)0xc048dad1, + (q31_t)0x39ec1e3b, (q31_t)0xc04a0b16, (q31_t)0x39df9be6, (q31_t)0xc04b3dcf, + (q31_t)0x39d319cc, (q31_t)0xc04c72fe, (q31_t)0x39c697f0, (q31_t)0xc04daaa1, + (q31_t)0x39ba1651, (q31_t)0xc04ee4b8, (q31_t)0x39ad94f0, (q31_t)0xc0502145, + (q31_t)0x39a113cd, (q31_t)0xc0516045, (q31_t)0x399492ea, (q31_t)0xc052a1bb, + (q31_t)0x39881245, (q31_t)0xc053e5a5, (q31_t)0x397b91e1, (q31_t)0xc0552c03, + (q31_t)0x396f11bc, (q31_t)0xc05674d6, (q31_t)0x396291d9, (q31_t)0xc057c01d, + (q31_t)0x39561237, (q31_t)0xc0590dd8, (q31_t)0x394992d7, (q31_t)0xc05a5e07, + (q31_t)0x393d13b8, (q31_t)0xc05bb0ab, (q31_t)0x393094dd, (q31_t)0xc05d05c3, + (q31_t)0x39241645, (q31_t)0xc05e5d4e, (q31_t)0x391797f0, (q31_t)0xc05fb74e, + (q31_t)0x390b19e0, (q31_t)0xc06113c2, (q31_t)0x38fe9c15, (q31_t)0xc06272aa, + (q31_t)0x38f21e8e, (q31_t)0xc063d405, (q31_t)0x38e5a14d, (q31_t)0xc06537d4, + (q31_t)0x38d92452, (q31_t)0xc0669e18, (q31_t)0x38cca79e, (q31_t)0xc06806ce, + (q31_t)0x38c02b31, (q31_t)0xc06971f9, (q31_t)0x38b3af0c, (q31_t)0xc06adf97, + (q31_t)0x38a7332e, (q31_t)0xc06c4fa8, (q31_t)0x389ab799, (q31_t)0xc06dc22e, + (q31_t)0x388e3c4d, (q31_t)0xc06f3726, (q31_t)0x3881c14b, (q31_t)0xc070ae92, + (q31_t)0x38754692, (q31_t)0xc0722871, (q31_t)0x3868cc24, (q31_t)0xc073a4c3, + (q31_t)0x385c5201, (q31_t)0xc0752389, (q31_t)0x384fd829, (q31_t)0xc076a4c2, + (q31_t)0x38435e9d, (q31_t)0xc078286e, (q31_t)0x3836e55d, (q31_t)0xc079ae8c, + (q31_t)0x382a6c6a, (q31_t)0xc07b371e, (q31_t)0x381df3c5, (q31_t)0xc07cc223, + (q31_t)0x38117b6d, (q31_t)0xc07e4f9b, (q31_t)0x38050364, (q31_t)0xc07fdf85, + (q31_t)0x37f88ba9, (q31_t)0xc08171e2, (q31_t)0x37ec143e, (q31_t)0xc08306b2, + (q31_t)0x37df9d22, (q31_t)0xc0849df4, (q31_t)0x37d32657, (q31_t)0xc08637a9, + (q31_t)0x37c6afdc, (q31_t)0xc087d3d0, (q31_t)0x37ba39b3, (q31_t)0xc089726a, + (q31_t)0x37adc3db, (q31_t)0xc08b1376, (q31_t)0x37a14e55, (q31_t)0xc08cb6f5, + (q31_t)0x3794d922, (q31_t)0xc08e5ce5, (q31_t)0x37886442, (q31_t)0xc0900548, + (q31_t)0x377befb5, (q31_t)0xc091b01d, (q31_t)0x376f7b7d, (q31_t)0xc0935d64, + (q31_t)0x37630799, (q31_t)0xc0950d1d, (q31_t)0x3756940a, (q31_t)0xc096bf48, + (q31_t)0x374a20d0, (q31_t)0xc09873e4, (q31_t)0x373daded, (q31_t)0xc09a2af3, + (q31_t)0x37313b60, (q31_t)0xc09be473, (q31_t)0x3724c92a, (q31_t)0xc09da065, + (q31_t)0x3718574b, (q31_t)0xc09f5ec8, (q31_t)0x370be5c4, (q31_t)0xc0a11f9d, + (q31_t)0x36ff7496, (q31_t)0xc0a2e2e3, (q31_t)0x36f303c0, (q31_t)0xc0a4a89b, + (q31_t)0x36e69344, (q31_t)0xc0a670c4, (q31_t)0x36da2321, (q31_t)0xc0a83b5e, + (q31_t)0x36cdb359, (q31_t)0xc0aa086a, (q31_t)0x36c143ec, (q31_t)0xc0abd7e6, + (q31_t)0x36b4d4d9, (q31_t)0xc0ada9d4, (q31_t)0x36a86623, (q31_t)0xc0af7e33, + (q31_t)0x369bf7c9, (q31_t)0xc0b15502, (q31_t)0x368f89cb, (q31_t)0xc0b32e42, + (q31_t)0x36831c2b, (q31_t)0xc0b509f3, (q31_t)0x3676aee8, (q31_t)0xc0b6e815, + (q31_t)0x366a4203, (q31_t)0xc0b8c8a7, (q31_t)0x365dd57d, (q31_t)0xc0baabaa, + (q31_t)0x36516956, (q31_t)0xc0bc911d, (q31_t)0x3644fd8f, (q31_t)0xc0be7901, + (q31_t)0x36389228, (q31_t)0xc0c06355, (q31_t)0x362c2721, (q31_t)0xc0c25019, + (q31_t)0x361fbc7b, (q31_t)0xc0c43f4d, (q31_t)0x36135237, (q31_t)0xc0c630f2, + (q31_t)0x3606e854, (q31_t)0xc0c82506, (q31_t)0x35fa7ed4, (q31_t)0xc0ca1b8a, + (q31_t)0x35ee15b7, (q31_t)0xc0cc147f, (q31_t)0x35e1acfd, (q31_t)0xc0ce0fe3, + (q31_t)0x35d544a7, (q31_t)0xc0d00db6, (q31_t)0x35c8dcb6, (q31_t)0xc0d20dfa, + (q31_t)0x35bc7529, (q31_t)0xc0d410ad, (q31_t)0x35b00e02, (q31_t)0xc0d615cf, + (q31_t)0x35a3a740, (q31_t)0xc0d81d61, (q31_t)0x359740e5, (q31_t)0xc0da2762, + (q31_t)0x358adaf0, (q31_t)0xc0dc33d2, (q31_t)0x357e7563, (q31_t)0xc0de42b2, + (q31_t)0x3572103d, (q31_t)0xc0e05401, (q31_t)0x3565ab80, (q31_t)0xc0e267be, + (q31_t)0x3559472b, (q31_t)0xc0e47deb, (q31_t)0x354ce33f, (q31_t)0xc0e69686, + (q31_t)0x35407fbd, (q31_t)0xc0e8b190, (q31_t)0x35341ca5, (q31_t)0xc0eacf09, + (q31_t)0x3527b9f7, (q31_t)0xc0eceef1, (q31_t)0x351b57b5, (q31_t)0xc0ef1147, + (q31_t)0x350ef5de, (q31_t)0xc0f1360b, (q31_t)0x35029473, (q31_t)0xc0f35d3e, + (q31_t)0x34f63374, (q31_t)0xc0f586df, (q31_t)0x34e9d2e3, (q31_t)0xc0f7b2ee, + (q31_t)0x34dd72be, (q31_t)0xc0f9e16b, (q31_t)0x34d11308, (q31_t)0xc0fc1257, + (q31_t)0x34c4b3c0, (q31_t)0xc0fe45b0, (q31_t)0x34b854e7, (q31_t)0xc1007b77, + (q31_t)0x34abf67e, (q31_t)0xc102b3ac, (q31_t)0x349f9884, (q31_t)0xc104ee4f, + (q31_t)0x34933afa, (q31_t)0xc1072b5f, (q31_t)0x3486dde1, (q31_t)0xc1096add, + (q31_t)0x347a8139, (q31_t)0xc10bacc8, (q31_t)0x346e2504, (q31_t)0xc10df120, + (q31_t)0x3461c940, (q31_t)0xc11037e6, (q31_t)0x34556def, (q31_t)0xc1128119, + (q31_t)0x34491311, (q31_t)0xc114ccb9, (q31_t)0x343cb8a7, (q31_t)0xc1171ac6, + (q31_t)0x34305eb0, (q31_t)0xc1196b3f, (q31_t)0x3424052f, (q31_t)0xc11bbe26, + (q31_t)0x3417ac22, (q31_t)0xc11e1379, (q31_t)0x340b538b, (q31_t)0xc1206b39, + (q31_t)0x33fefb6a, (q31_t)0xc122c566, (q31_t)0x33f2a3bf, (q31_t)0xc12521ff, + (q31_t)0x33e64c8c, (q31_t)0xc1278104, (q31_t)0x33d9f5cf, (q31_t)0xc129e276, + (q31_t)0x33cd9f8b, (q31_t)0xc12c4653, (q31_t)0x33c149bf, (q31_t)0xc12eac9d, + (q31_t)0x33b4f46c, (q31_t)0xc1311553, (q31_t)0x33a89f92, (q31_t)0xc1338075, + (q31_t)0x339c4b32, (q31_t)0xc135ee02, (q31_t)0x338ff74d, (q31_t)0xc1385dfb, + (q31_t)0x3383a3e2, (q31_t)0xc13ad060, (q31_t)0x337750f2, (q31_t)0xc13d4530, + (q31_t)0x336afe7e, (q31_t)0xc13fbc6c, (q31_t)0x335eac86, (q31_t)0xc1423613, + (q31_t)0x33525b0b, (q31_t)0xc144b225, (q31_t)0x33460a0d, (q31_t)0xc14730a3, + (q31_t)0x3339b98d, (q31_t)0xc149b18b, (q31_t)0x332d698a, (q31_t)0xc14c34df, + (q31_t)0x33211a07, (q31_t)0xc14eba9d, (q31_t)0x3314cb02, (q31_t)0xc15142c6, + (q31_t)0x33087c7d, (q31_t)0xc153cd5a, (q31_t)0x32fc2e77, (q31_t)0xc1565a58, + (q31_t)0x32efe0f2, (q31_t)0xc158e9c1, (q31_t)0x32e393ef, (q31_t)0xc15b7b94, + (q31_t)0x32d7476c, (q31_t)0xc15e0fd1, (q31_t)0x32cafb6b, (q31_t)0xc160a678, + (q31_t)0x32beafed, (q31_t)0xc1633f8a, (q31_t)0x32b264f2, (q31_t)0xc165db05, + (q31_t)0x32a61a7a, (q31_t)0xc16878eb, (q31_t)0x3299d085, (q31_t)0xc16b193a, + (q31_t)0x328d8715, (q31_t)0xc16dbbf3, (q31_t)0x32813e2a, (q31_t)0xc1706115, + (q31_t)0x3274f5c3, (q31_t)0xc17308a1, (q31_t)0x3268ade3, (q31_t)0xc175b296, + (q31_t)0x325c6688, (q31_t)0xc1785ef4, (q31_t)0x32501fb5, (q31_t)0xc17b0dbb, + (q31_t)0x3243d968, (q31_t)0xc17dbeec, (q31_t)0x323793a3, (q31_t)0xc1807285, + (q31_t)0x322b4e66, (q31_t)0xc1832888, (q31_t)0x321f09b1, (q31_t)0xc185e0f3, + (q31_t)0x3212c585, (q31_t)0xc1889bc6, (q31_t)0x320681e3, (q31_t)0xc18b5903, + (q31_t)0x31fa3ecb, (q31_t)0xc18e18a7, (q31_t)0x31edfc3d, (q31_t)0xc190dab4, + (q31_t)0x31e1ba3a, (q31_t)0xc1939f29, (q31_t)0x31d578c2, (q31_t)0xc1966606, + (q31_t)0x31c937d6, (q31_t)0xc1992f4c, (q31_t)0x31bcf777, (q31_t)0xc19bfaf9, + (q31_t)0x31b0b7a4, (q31_t)0xc19ec90d, (q31_t)0x31a4785e, (q31_t)0xc1a1998a, + (q31_t)0x319839a6, (q31_t)0xc1a46c6e, (q31_t)0x318bfb7d, (q31_t)0xc1a741b9, + (q31_t)0x317fbde2, (q31_t)0xc1aa196c, (q31_t)0x317380d6, (q31_t)0xc1acf386, + (q31_t)0x31674459, (q31_t)0xc1afd007, (q31_t)0x315b086d, (q31_t)0xc1b2aef0, + (q31_t)0x314ecd11, (q31_t)0xc1b5903f, (q31_t)0x31429247, (q31_t)0xc1b873f5, + (q31_t)0x3136580d, (q31_t)0xc1bb5a11, (q31_t)0x312a1e66, (q31_t)0xc1be4294, + (q31_t)0x311de551, (q31_t)0xc1c12d7e, (q31_t)0x3111accf, (q31_t)0xc1c41ace, + (q31_t)0x310574e0, (q31_t)0xc1c70a84, (q31_t)0x30f93d86, (q31_t)0xc1c9fca0, + (q31_t)0x30ed06bf, (q31_t)0xc1ccf122, (q31_t)0x30e0d08d, (q31_t)0xc1cfe80a, + (q31_t)0x30d49af1, (q31_t)0xc1d2e158, (q31_t)0x30c865ea, (q31_t)0xc1d5dd0c, + (q31_t)0x30bc317a, (q31_t)0xc1d8db25, (q31_t)0x30affda0, (q31_t)0xc1dbdba3, + (q31_t)0x30a3ca5d, (q31_t)0xc1dede87, (q31_t)0x309797b2, (q31_t)0xc1e1e3d0, + (q31_t)0x308b659f, (q31_t)0xc1e4eb7e, (q31_t)0x307f3424, (q31_t)0xc1e7f591, + (q31_t)0x30730342, (q31_t)0xc1eb0209, (q31_t)0x3066d2fa, (q31_t)0xc1ee10e5, + (q31_t)0x305aa34c, (q31_t)0xc1f12227, (q31_t)0x304e7438, (q31_t)0xc1f435cc, + (q31_t)0x304245c0, (q31_t)0xc1f74bd6, (q31_t)0x303617e2, (q31_t)0xc1fa6445, + (q31_t)0x3029eaa1, (q31_t)0xc1fd7f17, (q31_t)0x301dbdfb, (q31_t)0xc2009c4e, + (q31_t)0x301191f3, (q31_t)0xc203bbe8, (q31_t)0x30056687, (q31_t)0xc206dde6, + (q31_t)0x2ff93bba, (q31_t)0xc20a0248, (q31_t)0x2fed118a, (q31_t)0xc20d290d, + (q31_t)0x2fe0e7f9, (q31_t)0xc2105236, (q31_t)0x2fd4bf08, (q31_t)0xc2137dc2, + (q31_t)0x2fc896b5, (q31_t)0xc216abb1, (q31_t)0x2fbc6f03, (q31_t)0xc219dc03, + (q31_t)0x2fb047f2, (q31_t)0xc21d0eb8, (q31_t)0x2fa42181, (q31_t)0xc22043d0, + (q31_t)0x2f97fbb2, (q31_t)0xc2237b4b, (q31_t)0x2f8bd685, (q31_t)0xc226b528, + (q31_t)0x2f7fb1fa, (q31_t)0xc229f167, (q31_t)0x2f738e12, (q31_t)0xc22d3009, + (q31_t)0x2f676ace, (q31_t)0xc230710d, (q31_t)0x2f5b482d, (q31_t)0xc233b473, + (q31_t)0x2f4f2630, (q31_t)0xc236fa3b, (q31_t)0x2f4304d8, (q31_t)0xc23a4265, + (q31_t)0x2f36e426, (q31_t)0xc23d8cf1, (q31_t)0x2f2ac419, (q31_t)0xc240d9de, + (q31_t)0x2f1ea4b2, (q31_t)0xc244292c, (q31_t)0x2f1285f2, (q31_t)0xc2477adc, + (q31_t)0x2f0667d9, (q31_t)0xc24aceed, (q31_t)0x2efa4a67, (q31_t)0xc24e255e, + (q31_t)0x2eee2d9d, (q31_t)0xc2517e31, (q31_t)0x2ee2117c, (q31_t)0xc254d965, + (q31_t)0x2ed5f604, (q31_t)0xc25836f9, (q31_t)0x2ec9db35, (q31_t)0xc25b96ee, + (q31_t)0x2ebdc110, (q31_t)0xc25ef943, (q31_t)0x2eb1a796, (q31_t)0xc2625df8, + (q31_t)0x2ea58ec6, (q31_t)0xc265c50e, (q31_t)0x2e9976a1, (q31_t)0xc2692e83, + (q31_t)0x2e8d5f29, (q31_t)0xc26c9a58, (q31_t)0x2e81485c, (q31_t)0xc270088e, + (q31_t)0x2e75323c, (q31_t)0xc2737922, (q31_t)0x2e691cc9, (q31_t)0xc276ec16, + (q31_t)0x2e5d0804, (q31_t)0xc27a616a, (q31_t)0x2e50f3ed, (q31_t)0xc27dd91c, + (q31_t)0x2e44e084, (q31_t)0xc281532e, (q31_t)0x2e38cdcb, (q31_t)0xc284cf9f, + (q31_t)0x2e2cbbc1, (q31_t)0xc2884e6e, (q31_t)0x2e20aa67, (q31_t)0xc28bcf9c, + (q31_t)0x2e1499bd, (q31_t)0xc28f5329, (q31_t)0x2e0889c4, (q31_t)0xc292d914, + (q31_t)0x2dfc7a7c, (q31_t)0xc296615d, (q31_t)0x2df06be6, (q31_t)0xc299ec05, + (q31_t)0x2de45e03, (q31_t)0xc29d790a, (q31_t)0x2dd850d2, (q31_t)0xc2a1086d, + (q31_t)0x2dcc4454, (q31_t)0xc2a49a2e, (q31_t)0x2dc0388a, (q31_t)0xc2a82e4d, + (q31_t)0x2db42d74, (q31_t)0xc2abc4c9, (q31_t)0x2da82313, (q31_t)0xc2af5da2, + (q31_t)0x2d9c1967, (q31_t)0xc2b2f8d8, (q31_t)0x2d901070, (q31_t)0xc2b6966c, + (q31_t)0x2d84082f, (q31_t)0xc2ba365c, (q31_t)0x2d7800a5, (q31_t)0xc2bdd8a9, + (q31_t)0x2d6bf9d1, (q31_t)0xc2c17d52, (q31_t)0x2d5ff3b5, (q31_t)0xc2c52459, + (q31_t)0x2d53ee51, (q31_t)0xc2c8cdbb, (q31_t)0x2d47e9a5, (q31_t)0xc2cc7979, + (q31_t)0x2d3be5b1, (q31_t)0xc2d02794, (q31_t)0x2d2fe277, (q31_t)0xc2d3d80a, + (q31_t)0x2d23dff7, (q31_t)0xc2d78add, (q31_t)0x2d17de31, (q31_t)0xc2db400a, + (q31_t)0x2d0bdd25, (q31_t)0xc2def794, (q31_t)0x2cffdcd4, (q31_t)0xc2e2b178, + (q31_t)0x2cf3dd3f, (q31_t)0xc2e66db8, (q31_t)0x2ce7de66, (q31_t)0xc2ea2c53, + (q31_t)0x2cdbe04a, (q31_t)0xc2eded49, (q31_t)0x2ccfe2ea, (q31_t)0xc2f1b099, + (q31_t)0x2cc3e648, (q31_t)0xc2f57644, (q31_t)0x2cb7ea63, (q31_t)0xc2f93e4a, + (q31_t)0x2cabef3d, (q31_t)0xc2fd08a9, (q31_t)0x2c9ff4d6, (q31_t)0xc300d563, + (q31_t)0x2c93fb2e, (q31_t)0xc304a477, (q31_t)0x2c880245, (q31_t)0xc30875e5, + (q31_t)0x2c7c0a1d, (q31_t)0xc30c49ad, (q31_t)0x2c7012b5, (q31_t)0xc3101fce, + (q31_t)0x2c641c0e, (q31_t)0xc313f848, (q31_t)0x2c582629, (q31_t)0xc317d31c, + (q31_t)0x2c4c3106, (q31_t)0xc31bb049, (q31_t)0x2c403ca5, (q31_t)0xc31f8fcf, + (q31_t)0x2c344908, (q31_t)0xc32371ae, (q31_t)0x2c28562d, (q31_t)0xc32755e5, + (q31_t)0x2c1c6417, (q31_t)0xc32b3c75, (q31_t)0x2c1072c4, (q31_t)0xc32f255e, + (q31_t)0x2c048237, (q31_t)0xc333109e, (q31_t)0x2bf8926f, (q31_t)0xc336fe37, + (q31_t)0x2beca36c, (q31_t)0xc33aee27, (q31_t)0x2be0b52f, (q31_t)0xc33ee070, + (q31_t)0x2bd4c7ba, (q31_t)0xc342d510, (q31_t)0x2bc8db0b, (q31_t)0xc346cc07, + (q31_t)0x2bbcef23, (q31_t)0xc34ac556, (q31_t)0x2bb10404, (q31_t)0xc34ec0fc, + (q31_t)0x2ba519ad, (q31_t)0xc352bef9, (q31_t)0x2b99301f, (q31_t)0xc356bf4d, + (q31_t)0x2b8d475b, (q31_t)0xc35ac1f7, (q31_t)0x2b815f60, (q31_t)0xc35ec6f8, + (q31_t)0x2b75782f, (q31_t)0xc362ce50, (q31_t)0x2b6991ca, (q31_t)0xc366d7fd, + (q31_t)0x2b5dac2f, (q31_t)0xc36ae401, (q31_t)0x2b51c760, (q31_t)0xc36ef25b, + (q31_t)0x2b45e35d, (q31_t)0xc373030a, (q31_t)0x2b3a0027, (q31_t)0xc377160f, + (q31_t)0x2b2e1dbe, (q31_t)0xc37b2b6a, (q31_t)0x2b223c22, (q31_t)0xc37f4319, + (q31_t)0x2b165b54, (q31_t)0xc3835d1e, (q31_t)0x2b0a7b54, (q31_t)0xc3877978, + (q31_t)0x2afe9c24, (q31_t)0xc38b9827, (q31_t)0x2af2bdc3, (q31_t)0xc38fb92a, + (q31_t)0x2ae6e031, (q31_t)0xc393dc82, (q31_t)0x2adb0370, (q31_t)0xc398022f, + (q31_t)0x2acf277f, (q31_t)0xc39c2a2f, (q31_t)0x2ac34c60, (q31_t)0xc3a05484, + (q31_t)0x2ab77212, (q31_t)0xc3a4812c, (q31_t)0x2aab9896, (q31_t)0xc3a8b028, + (q31_t)0x2a9fbfed, (q31_t)0xc3ace178, (q31_t)0x2a93e817, (q31_t)0xc3b1151b, + (q31_t)0x2a881114, (q31_t)0xc3b54b11, (q31_t)0x2a7c3ae5, (q31_t)0xc3b9835a, + (q31_t)0x2a70658a, (q31_t)0xc3bdbdf6, (q31_t)0x2a649105, (q31_t)0xc3c1fae5, + (q31_t)0x2a58bd54, (q31_t)0xc3c63a26, (q31_t)0x2a4cea79, (q31_t)0xc3ca7bba, + (q31_t)0x2a411874, (q31_t)0xc3cebfa0, (q31_t)0x2a354746, (q31_t)0xc3d305d8, + (q31_t)0x2a2976ef, (q31_t)0xc3d74e62, (q31_t)0x2a1da770, (q31_t)0xc3db993e, + (q31_t)0x2a11d8c8, (q31_t)0xc3dfe66c, (q31_t)0x2a060af9, (q31_t)0xc3e435ea, + (q31_t)0x29fa3e03, (q31_t)0xc3e887bb, (q31_t)0x29ee71e6, (q31_t)0xc3ecdbdc, + (q31_t)0x29e2a6a3, (q31_t)0xc3f1324e, (q31_t)0x29d6dc3b, (q31_t)0xc3f58b10, + (q31_t)0x29cb12ad, (q31_t)0xc3f9e624, (q31_t)0x29bf49fa, (q31_t)0xc3fe4388, + (q31_t)0x29b38223, (q31_t)0xc402a33c, (q31_t)0x29a7bb28, (q31_t)0xc4070540, + (q31_t)0x299bf509, (q31_t)0xc40b6994, (q31_t)0x29902fc7, (q31_t)0xc40fd037, + (q31_t)0x29846b63, (q31_t)0xc414392b, (q31_t)0x2978a7dd, (q31_t)0xc418a46d, + (q31_t)0x296ce535, (q31_t)0xc41d11ff, (q31_t)0x2961236c, (q31_t)0xc42181e0, + (q31_t)0x29556282, (q31_t)0xc425f410, (q31_t)0x2949a278, (q31_t)0xc42a688f, + (q31_t)0x293de34e, (q31_t)0xc42edf5c, (q31_t)0x29322505, (q31_t)0xc4335877, + (q31_t)0x2926679c, (q31_t)0xc437d3e1, (q31_t)0x291aab16, (q31_t)0xc43c5199, + (q31_t)0x290eef71, (q31_t)0xc440d19e, (q31_t)0x290334af, (q31_t)0xc44553f2, + (q31_t)0x28f77acf, (q31_t)0xc449d892, (q31_t)0x28ebc1d3, (q31_t)0xc44e5f80, + (q31_t)0x28e009ba, (q31_t)0xc452e8bc, (q31_t)0x28d45286, (q31_t)0xc4577444, + (q31_t)0x28c89c37, (q31_t)0xc45c0219, (q31_t)0x28bce6cd, (q31_t)0xc460923b, + (q31_t)0x28b13248, (q31_t)0xc46524a9, (q31_t)0x28a57ea9, (q31_t)0xc469b963, + (q31_t)0x2899cbf1, (q31_t)0xc46e5069, (q31_t)0x288e1a20, (q31_t)0xc472e9bc, + (q31_t)0x28826936, (q31_t)0xc477855a, (q31_t)0x2876b934, (q31_t)0xc47c2344, + (q31_t)0x286b0a1a, (q31_t)0xc480c379, (q31_t)0x285f5be9, (q31_t)0xc48565f9, + (q31_t)0x2853aea1, (q31_t)0xc48a0ac4, (q31_t)0x28480243, (q31_t)0xc48eb1db, + (q31_t)0x283c56cf, (q31_t)0xc4935b3c, (q31_t)0x2830ac45, (q31_t)0xc49806e7, + (q31_t)0x282502a7, (q31_t)0xc49cb4dd, (q31_t)0x281959f4, (q31_t)0xc4a1651c, + (q31_t)0x280db22d, (q31_t)0xc4a617a6, (q31_t)0x28020b52, (q31_t)0xc4aacc7a, + (q31_t)0x27f66564, (q31_t)0xc4af8397, (q31_t)0x27eac063, (q31_t)0xc4b43cfd, + (q31_t)0x27df1c50, (q31_t)0xc4b8f8ad, (q31_t)0x27d3792b, (q31_t)0xc4bdb6a6, + (q31_t)0x27c7d6f4, (q31_t)0xc4c276e8, (q31_t)0x27bc35ad, (q31_t)0xc4c73972, + (q31_t)0x27b09555, (q31_t)0xc4cbfe45, (q31_t)0x27a4f5ed, (q31_t)0xc4d0c560, + (q31_t)0x27995776, (q31_t)0xc4d58ec3, (q31_t)0x278db9ef, (q31_t)0xc4da5a6f, + (q31_t)0x27821d59, (q31_t)0xc4df2862, (q31_t)0x277681b6, (q31_t)0xc4e3f89c, + (q31_t)0x276ae704, (q31_t)0xc4e8cb1e, (q31_t)0x275f4d45, (q31_t)0xc4ed9fe7, + (q31_t)0x2753b479, (q31_t)0xc4f276f7, (q31_t)0x27481ca1, (q31_t)0xc4f7504e, + (q31_t)0x273c85bc, (q31_t)0xc4fc2bec, (q31_t)0x2730efcc, (q31_t)0xc50109d0, + (q31_t)0x27255ad1, (q31_t)0xc505e9fb, (q31_t)0x2719c6cb, (q31_t)0xc50acc6b, + (q31_t)0x270e33bb, (q31_t)0xc50fb121, (q31_t)0x2702a1a1, (q31_t)0xc514981d, + (q31_t)0x26f7107e, (q31_t)0xc519815f, (q31_t)0x26eb8052, (q31_t)0xc51e6ce6, + (q31_t)0x26dff11d, (q31_t)0xc5235ab2, (q31_t)0x26d462e1, (q31_t)0xc5284ac3, + (q31_t)0x26c8d59c, (q31_t)0xc52d3d18, (q31_t)0x26bd4951, (q31_t)0xc53231b3, + (q31_t)0x26b1bdff, (q31_t)0xc5372891, (q31_t)0x26a633a6, (q31_t)0xc53c21b4, + (q31_t)0x269aaa48, (q31_t)0xc5411d1b, (q31_t)0x268f21e5, (q31_t)0xc5461ac6, + (q31_t)0x26839a7c, (q31_t)0xc54b1ab4, (q31_t)0x26781410, (q31_t)0xc5501ce5, + (q31_t)0x266c8e9f, (q31_t)0xc555215a, (q31_t)0x26610a2a, (q31_t)0xc55a2812, + (q31_t)0x265586b3, (q31_t)0xc55f310d, (q31_t)0x264a0438, (q31_t)0xc5643c4a, + (q31_t)0x263e82bc, (q31_t)0xc56949ca, (q31_t)0x2633023e, (q31_t)0xc56e598c, + (q31_t)0x262782be, (q31_t)0xc5736b90, (q31_t)0x261c043d, (q31_t)0xc5787fd6, + (q31_t)0x261086bc, (q31_t)0xc57d965d, (q31_t)0x26050a3b, (q31_t)0xc582af26, + (q31_t)0x25f98ebb, (q31_t)0xc587ca31, (q31_t)0x25ee143b, (q31_t)0xc58ce77c, + (q31_t)0x25e29abc, (q31_t)0xc5920708, (q31_t)0x25d72240, (q31_t)0xc59728d5, + (q31_t)0x25cbaac5, (q31_t)0xc59c4ce3, (q31_t)0x25c0344d, (q31_t)0xc5a17330, + (q31_t)0x25b4bed8, (q31_t)0xc5a69bbe, (q31_t)0x25a94a67, (q31_t)0xc5abc68c, + (q31_t)0x259dd6f9, (q31_t)0xc5b0f399, (q31_t)0x25926490, (q31_t)0xc5b622e6, + (q31_t)0x2586f32c, (q31_t)0xc5bb5472, (q31_t)0x257b82cd, (q31_t)0xc5c0883d, + (q31_t)0x25701374, (q31_t)0xc5c5be47, (q31_t)0x2564a521, (q31_t)0xc5caf690, + (q31_t)0x255937d5, (q31_t)0xc5d03118, (q31_t)0x254dcb8f, (q31_t)0xc5d56ddd, + (q31_t)0x25426051, (q31_t)0xc5daace1, (q31_t)0x2536f61b, (q31_t)0xc5dfee22, + (q31_t)0x252b8cee, (q31_t)0xc5e531a1, (q31_t)0x252024c9, (q31_t)0xc5ea775e, + (q31_t)0x2514bdad, (q31_t)0xc5efbf58, (q31_t)0x2509579b, (q31_t)0xc5f5098f, + (q31_t)0x24fdf294, (q31_t)0xc5fa5603, (q31_t)0x24f28e96, (q31_t)0xc5ffa4b3, + (q31_t)0x24e72ba4, (q31_t)0xc604f5a0, (q31_t)0x24dbc9bd, (q31_t)0xc60a48c9, + (q31_t)0x24d068e2, (q31_t)0xc60f9e2e, (q31_t)0x24c50914, (q31_t)0xc614f5cf, + (q31_t)0x24b9aa52, (q31_t)0xc61a4fac, (q31_t)0x24ae4c9d, (q31_t)0xc61fabc4, + (q31_t)0x24a2eff6, (q31_t)0xc6250a18, (q31_t)0x2497945d, (q31_t)0xc62a6aa6, + (q31_t)0x248c39d3, (q31_t)0xc62fcd6f, (q31_t)0x2480e057, (q31_t)0xc6353273, + (q31_t)0x247587eb, (q31_t)0xc63a99b1, (q31_t)0x246a308f, (q31_t)0xc6400329, + (q31_t)0x245eda43, (q31_t)0xc6456edb, (q31_t)0x24538507, (q31_t)0xc64adcc7, + (q31_t)0x244830dd, (q31_t)0xc6504ced, (q31_t)0x243cddc4, (q31_t)0xc655bf4c, + (q31_t)0x24318bbe, (q31_t)0xc65b33e4, (q31_t)0x24263ac9, (q31_t)0xc660aab5, + (q31_t)0x241aeae8, (q31_t)0xc66623be, (q31_t)0x240f9c1a, (q31_t)0xc66b9f01, + (q31_t)0x24044e60, (q31_t)0xc6711c7b, (q31_t)0x23f901ba, (q31_t)0xc6769c2e, + (q31_t)0x23edb628, (q31_t)0xc67c1e18, (q31_t)0x23e26bac, (q31_t)0xc681a23a, + (q31_t)0x23d72245, (q31_t)0xc6872894, (q31_t)0x23cbd9f4, (q31_t)0xc68cb124, + (q31_t)0x23c092b9, (q31_t)0xc6923bec, (q31_t)0x23b54c95, (q31_t)0xc697c8eb, + (q31_t)0x23aa0788, (q31_t)0xc69d5820, (q31_t)0x239ec393, (q31_t)0xc6a2e98b, + (q31_t)0x239380b6, (q31_t)0xc6a87d2d, (q31_t)0x23883ef2, (q31_t)0xc6ae1304, + (q31_t)0x237cfe47, (q31_t)0xc6b3ab12, (q31_t)0x2371beb5, (q31_t)0xc6b94554, + (q31_t)0x2366803c, (q31_t)0xc6bee1cd, (q31_t)0x235b42df, (q31_t)0xc6c4807a, + (q31_t)0x2350069b, (q31_t)0xc6ca215c, (q31_t)0x2344cb73, (q31_t)0xc6cfc472, + (q31_t)0x23399167, (q31_t)0xc6d569be, (q31_t)0x232e5876, (q31_t)0xc6db113d, + (q31_t)0x232320a2, (q31_t)0xc6e0baf0, (q31_t)0x2317e9eb, (q31_t)0xc6e666d7, + (q31_t)0x230cb451, (q31_t)0xc6ec14f2, (q31_t)0x23017fd5, (q31_t)0xc6f1c540, + (q31_t)0x22f64c77, (q31_t)0xc6f777c1, (q31_t)0x22eb1a37, (q31_t)0xc6fd2c75, + (q31_t)0x22dfe917, (q31_t)0xc702e35c, (q31_t)0x22d4b916, (q31_t)0xc7089c75, + (q31_t)0x22c98a35, (q31_t)0xc70e57c0, (q31_t)0x22be5c74, (q31_t)0xc714153e, + (q31_t)0x22b32fd4, (q31_t)0xc719d4ed, (q31_t)0x22a80456, (q31_t)0xc71f96ce, + (q31_t)0x229cd9f8, (q31_t)0xc7255ae0, (q31_t)0x2291b0bd, (q31_t)0xc72b2123, + (q31_t)0x228688a4, (q31_t)0xc730e997, (q31_t)0x227b61af, (q31_t)0xc736b43c, + (q31_t)0x22703bdc, (q31_t)0xc73c8111, (q31_t)0x2265172e, (q31_t)0xc7425016, + (q31_t)0x2259f3a3, (q31_t)0xc748214c, (q31_t)0x224ed13d, (q31_t)0xc74df4b1, + (q31_t)0x2243affc, (q31_t)0xc753ca46, (q31_t)0x22388fe1, (q31_t)0xc759a20a, + (q31_t)0x222d70eb, (q31_t)0xc75f7bfe, (q31_t)0x2222531c, (q31_t)0xc7655820, + (q31_t)0x22173674, (q31_t)0xc76b3671, (q31_t)0x220c1af3, (q31_t)0xc77116f0, + (q31_t)0x22010099, (q31_t)0xc776f99d, (q31_t)0x21f5e768, (q31_t)0xc77cde79, + (q31_t)0x21eacf5f, (q31_t)0xc782c582, (q31_t)0x21dfb87f, (q31_t)0xc788aeb9, + (q31_t)0x21d4a2c8, (q31_t)0xc78e9a1d, (q31_t)0x21c98e3b, (q31_t)0xc79487ae, + (q31_t)0x21be7ad8, (q31_t)0xc79a776c, (q31_t)0x21b368a0, (q31_t)0xc7a06957, + (q31_t)0x21a85793, (q31_t)0xc7a65d6e, (q31_t)0x219d47b1, (q31_t)0xc7ac53b1, + (q31_t)0x219238fb, (q31_t)0xc7b24c20, (q31_t)0x21872b72, (q31_t)0xc7b846ba, + (q31_t)0x217c1f15, (q31_t)0xc7be4381, (q31_t)0x217113e5, (q31_t)0xc7c44272, + (q31_t)0x216609e3, (q31_t)0xc7ca438f, (q31_t)0x215b0110, (q31_t)0xc7d046d6, + (q31_t)0x214ff96a, (q31_t)0xc7d64c47, (q31_t)0x2144f2f3, (q31_t)0xc7dc53e3, + (q31_t)0x2139edac, (q31_t)0xc7e25daa, (q31_t)0x212ee995, (q31_t)0xc7e8699a, + (q31_t)0x2123e6ad, (q31_t)0xc7ee77b3, (q31_t)0x2118e4f6, (q31_t)0xc7f487f6, + (q31_t)0x210de470, (q31_t)0xc7fa9a62, (q31_t)0x2102e51c, (q31_t)0xc800aef7, + (q31_t)0x20f7e6f9, (q31_t)0xc806c5b5, (q31_t)0x20ecea09, (q31_t)0xc80cde9b, + (q31_t)0x20e1ee4b, (q31_t)0xc812f9a9, (q31_t)0x20d6f3c1, (q31_t)0xc81916df, + (q31_t)0x20cbfa6a, (q31_t)0xc81f363d, (q31_t)0x20c10247, (q31_t)0xc82557c3, + (q31_t)0x20b60b58, (q31_t)0xc82b7b70, (q31_t)0x20ab159e, (q31_t)0xc831a143, + (q31_t)0x20a0211a, (q31_t)0xc837c93e, (q31_t)0x20952dcb, (q31_t)0xc83df35f, + (q31_t)0x208a3bb2, (q31_t)0xc8441fa6, (q31_t)0x207f4acf, (q31_t)0xc84a4e14, + (q31_t)0x20745b24, (q31_t)0xc8507ea7, (q31_t)0x20696cb0, (q31_t)0xc856b160, + (q31_t)0x205e7f74, (q31_t)0xc85ce63e, (q31_t)0x2053936f, (q31_t)0xc8631d42, + (q31_t)0x2048a8a4, (q31_t)0xc869566a, (q31_t)0x203dbf11, (q31_t)0xc86f91b7, + (q31_t)0x2032d6b8, (q31_t)0xc875cf28, (q31_t)0x2027ef99, (q31_t)0xc87c0ebd, + (q31_t)0x201d09b4, (q31_t)0xc8825077, (q31_t)0x2012250a, (q31_t)0xc8889454, + (q31_t)0x2007419b, (q31_t)0xc88eda54, (q31_t)0x1ffc5f67, (q31_t)0xc8952278, + (q31_t)0x1ff17e70, (q31_t)0xc89b6cbf, (q31_t)0x1fe69eb4, (q31_t)0xc8a1b928, + (q31_t)0x1fdbc036, (q31_t)0xc8a807b4, (q31_t)0x1fd0e2f5, (q31_t)0xc8ae5862, + (q31_t)0x1fc606f1, (q31_t)0xc8b4ab32, (q31_t)0x1fbb2c2c, (q31_t)0xc8bb0023, + (q31_t)0x1fb052a5, (q31_t)0xc8c15736, (q31_t)0x1fa57a5d, (q31_t)0xc8c7b06b, + (q31_t)0x1f9aa354, (q31_t)0xc8ce0bc0, (q31_t)0x1f8fcd8b, (q31_t)0xc8d46936, + (q31_t)0x1f84f902, (q31_t)0xc8dac8cd, (q31_t)0x1f7a25ba, (q31_t)0xc8e12a84, + (q31_t)0x1f6f53b3, (q31_t)0xc8e78e5b, (q31_t)0x1f6482ed, (q31_t)0xc8edf452, + (q31_t)0x1f59b369, (q31_t)0xc8f45c68, (q31_t)0x1f4ee527, (q31_t)0xc8fac69e, + (q31_t)0x1f441828, (q31_t)0xc90132f2, (q31_t)0x1f394c6b, (q31_t)0xc907a166, + (q31_t)0x1f2e81f3, (q31_t)0xc90e11f7, (q31_t)0x1f23b8be, (q31_t)0xc91484a8, + (q31_t)0x1f18f0ce, (q31_t)0xc91af976, (q31_t)0x1f0e2a22, (q31_t)0xc9217062, + (q31_t)0x1f0364bc, (q31_t)0xc927e96b, (q31_t)0x1ef8a09b, (q31_t)0xc92e6492, + (q31_t)0x1eedddc0, (q31_t)0xc934e1d6, (q31_t)0x1ee31c2b, (q31_t)0xc93b6137, + (q31_t)0x1ed85bdd, (q31_t)0xc941e2b4, (q31_t)0x1ecd9cd7, (q31_t)0xc948664d, + (q31_t)0x1ec2df18, (q31_t)0xc94eec03, (q31_t)0x1eb822a1, (q31_t)0xc95573d4, + (q31_t)0x1ead6773, (q31_t)0xc95bfdc1, (q31_t)0x1ea2ad8d, (q31_t)0xc96289c9, + (q31_t)0x1e97f4f1, (q31_t)0xc96917ec, (q31_t)0x1e8d3d9e, (q31_t)0xc96fa82a, + (q31_t)0x1e828796, (q31_t)0xc9763a83, (q31_t)0x1e77d2d8, (q31_t)0xc97ccef5, + (q31_t)0x1e6d1f65, (q31_t)0xc9836582, (q31_t)0x1e626d3e, (q31_t)0xc989fe29, + (q31_t)0x1e57bc62, (q31_t)0xc99098e9, (q31_t)0x1e4d0cd2, (q31_t)0xc99735c2, + (q31_t)0x1e425e8f, (q31_t)0xc99dd4b4, (q31_t)0x1e37b199, (q31_t)0xc9a475bf, + (q31_t)0x1e2d05f1, (q31_t)0xc9ab18e3, (q31_t)0x1e225b96, (q31_t)0xc9b1be1e, + (q31_t)0x1e17b28a, (q31_t)0xc9b86572, (q31_t)0x1e0d0acc, (q31_t)0xc9bf0edd, + (q31_t)0x1e02645d, (q31_t)0xc9c5ba60, (q31_t)0x1df7bf3e, (q31_t)0xc9cc67fa, + (q31_t)0x1ded1b6e, (q31_t)0xc9d317ab, (q31_t)0x1de278ef, (q31_t)0xc9d9c973, + (q31_t)0x1dd7d7c1, (q31_t)0xc9e07d51, (q31_t)0x1dcd37e4, (q31_t)0xc9e73346, + (q31_t)0x1dc29958, (q31_t)0xc9edeb50, (q31_t)0x1db7fc1e, (q31_t)0xc9f4a570, + (q31_t)0x1dad6036, (q31_t)0xc9fb61a5, (q31_t)0x1da2c5a2, (q31_t)0xca021fef, + (q31_t)0x1d982c60, (q31_t)0xca08e04f, (q31_t)0x1d8d9472, (q31_t)0xca0fa2c3, + (q31_t)0x1d82fdd8, (q31_t)0xca16674b, (q31_t)0x1d786892, (q31_t)0xca1d2de7, + (q31_t)0x1d6dd4a2, (q31_t)0xca23f698, (q31_t)0x1d634206, (q31_t)0xca2ac15b, + (q31_t)0x1d58b0c0, (q31_t)0xca318e32, (q31_t)0x1d4e20d0, (q31_t)0xca385d1d, + (q31_t)0x1d439236, (q31_t)0xca3f2e19, (q31_t)0x1d3904f4, (q31_t)0xca460129, + (q31_t)0x1d2e7908, (q31_t)0xca4cd64b, (q31_t)0x1d23ee74, (q31_t)0xca53ad7e, + (q31_t)0x1d196538, (q31_t)0xca5a86c4, (q31_t)0x1d0edd55, (q31_t)0xca61621b, + (q31_t)0x1d0456ca, (q31_t)0xca683f83, (q31_t)0x1cf9d199, (q31_t)0xca6f1efc, + (q31_t)0x1cef4dc2, (q31_t)0xca760086, (q31_t)0x1ce4cb44, (q31_t)0xca7ce420, + (q31_t)0x1cda4a21, (q31_t)0xca83c9ca, (q31_t)0x1ccfca59, (q31_t)0xca8ab184, + (q31_t)0x1cc54bec, (q31_t)0xca919b4e, (q31_t)0x1cbacedb, (q31_t)0xca988727, + (q31_t)0x1cb05326, (q31_t)0xca9f750f, (q31_t)0x1ca5d8cd, (q31_t)0xcaa66506, + (q31_t)0x1c9b5fd2, (q31_t)0xcaad570c, (q31_t)0x1c90e834, (q31_t)0xcab44b1f, + (q31_t)0x1c8671f3, (q31_t)0xcabb4141, (q31_t)0x1c7bfd11, (q31_t)0xcac23971, + (q31_t)0x1c71898d, (q31_t)0xcac933ae, (q31_t)0x1c671768, (q31_t)0xcad02ff8, + (q31_t)0x1c5ca6a2, (q31_t)0xcad72e4f, (q31_t)0x1c52373c, (q31_t)0xcade2eb3, + (q31_t)0x1c47c936, (q31_t)0xcae53123, (q31_t)0x1c3d5c91, (q31_t)0xcaec35a0, + (q31_t)0x1c32f14d, (q31_t)0xcaf33c28, (q31_t)0x1c28876a, (q31_t)0xcafa44bc, + (q31_t)0x1c1e1ee9, (q31_t)0xcb014f5b, (q31_t)0x1c13b7c9, (q31_t)0xcb085c05, + (q31_t)0x1c09520d, (q31_t)0xcb0f6aba, (q31_t)0x1bfeedb3, (q31_t)0xcb167b79, + (q31_t)0x1bf48abd, (q31_t)0xcb1d8e43, (q31_t)0x1bea292b, (q31_t)0xcb24a316, + (q31_t)0x1bdfc8fc, (q31_t)0xcb2bb9f4, (q31_t)0x1bd56a32, (q31_t)0xcb32d2da, + (q31_t)0x1bcb0cce, (q31_t)0xcb39edca, (q31_t)0x1bc0b0ce, (q31_t)0xcb410ac3, + (q31_t)0x1bb65634, (q31_t)0xcb4829c4, (q31_t)0x1babfd01, (q31_t)0xcb4f4acd, + (q31_t)0x1ba1a534, (q31_t)0xcb566ddf, (q31_t)0x1b974ece, (q31_t)0xcb5d92f8, + (q31_t)0x1b8cf9cf, (q31_t)0xcb64ba19, (q31_t)0x1b82a638, (q31_t)0xcb6be341, + (q31_t)0x1b785409, (q31_t)0xcb730e70, (q31_t)0x1b6e0342, (q31_t)0xcb7a3ba5, + (q31_t)0x1b63b3e5, (q31_t)0xcb816ae1, (q31_t)0x1b5965f1, (q31_t)0xcb889c23, + (q31_t)0x1b4f1967, (q31_t)0xcb8fcf6b, (q31_t)0x1b44ce46, (q31_t)0xcb9704b9, + (q31_t)0x1b3a8491, (q31_t)0xcb9e3c0b, (q31_t)0x1b303c46, (q31_t)0xcba57563, + (q31_t)0x1b25f566, (q31_t)0xcbacb0bf, (q31_t)0x1b1baff2, (q31_t)0xcbb3ee20, + (q31_t)0x1b116beb, (q31_t)0xcbbb2d85, (q31_t)0x1b072950, (q31_t)0xcbc26eee, + (q31_t)0x1afce821, (q31_t)0xcbc9b25a, (q31_t)0x1af2a860, (q31_t)0xcbd0f7ca, + (q31_t)0x1ae86a0d, (q31_t)0xcbd83f3d, (q31_t)0x1ade2d28, (q31_t)0xcbdf88b3, + (q31_t)0x1ad3f1b1, (q31_t)0xcbe6d42b, (q31_t)0x1ac9b7a9, (q31_t)0xcbee21a5, + (q31_t)0x1abf7f11, (q31_t)0xcbf57121, (q31_t)0x1ab547e8, (q31_t)0xcbfcc29f, + (q31_t)0x1aab122f, (q31_t)0xcc04161e, (q31_t)0x1aa0dde7, (q31_t)0xcc0b6b9e, + (q31_t)0x1a96ab0f, (q31_t)0xcc12c31f, (q31_t)0x1a8c79a9, (q31_t)0xcc1a1ca0, + (q31_t)0x1a8249b4, (q31_t)0xcc217822, (q31_t)0x1a781b31, (q31_t)0xcc28d5a3, + (q31_t)0x1a6dee21, (q31_t)0xcc303524, (q31_t)0x1a63c284, (q31_t)0xcc3796a5, + (q31_t)0x1a599859, (q31_t)0xcc3efa25, (q31_t)0x1a4f6fa3, (q31_t)0xcc465fa3, + (q31_t)0x1a454860, (q31_t)0xcc4dc720, (q31_t)0x1a3b2292, (q31_t)0xcc55309b, + (q31_t)0x1a30fe38, (q31_t)0xcc5c9c14, (q31_t)0x1a26db54, (q31_t)0xcc64098b, + (q31_t)0x1a1cb9e5, (q31_t)0xcc6b78ff, (q31_t)0x1a1299ec, (q31_t)0xcc72ea70, + (q31_t)0x1a087b69, (q31_t)0xcc7a5dde, (q31_t)0x19fe5e5e, (q31_t)0xcc81d349, + (q31_t)0x19f442c9, (q31_t)0xcc894aaf, (q31_t)0x19ea28ac, (q31_t)0xcc90c412, + (q31_t)0x19e01006, (q31_t)0xcc983f70, (q31_t)0x19d5f8d9, (q31_t)0xcc9fbcca, + (q31_t)0x19cbe325, (q31_t)0xcca73c1e, (q31_t)0x19c1cee9, (q31_t)0xccaebd6e, + (q31_t)0x19b7bc27, (q31_t)0xccb640b8, (q31_t)0x19adaadf, (q31_t)0xccbdc5fc, + (q31_t)0x19a39b11, (q31_t)0xccc54d3a, (q31_t)0x19998cbe, (q31_t)0xccccd671, + (q31_t)0x198f7fe6, (q31_t)0xccd461a2, (q31_t)0x19857489, (q31_t)0xccdbeecc, + (q31_t)0x197b6aa8, (q31_t)0xcce37def, (q31_t)0x19716243, (q31_t)0xcceb0f0a, + (q31_t)0x19675b5a, (q31_t)0xccf2a21d, (q31_t)0x195d55ef, (q31_t)0xccfa3729, + (q31_t)0x19535201, (q31_t)0xcd01ce2b, (q31_t)0x19494f90, (q31_t)0xcd096725, + (q31_t)0x193f4e9e, (q31_t)0xcd110216, (q31_t)0x19354f2a, (q31_t)0xcd189efe, + (q31_t)0x192b5135, (q31_t)0xcd203ddc, (q31_t)0x192154bf, (q31_t)0xcd27deb0, + (q31_t)0x191759c9, (q31_t)0xcd2f817b, (q31_t)0x190d6053, (q31_t)0xcd37263a, + (q31_t)0x1903685d, (q31_t)0xcd3eccef, (q31_t)0x18f971e8, (q31_t)0xcd467599, + (q31_t)0x18ef7cf4, (q31_t)0xcd4e2037, (q31_t)0x18e58982, (q31_t)0xcd55ccca, + (q31_t)0x18db9792, (q31_t)0xcd5d7b50, (q31_t)0x18d1a724, (q31_t)0xcd652bcb, + (q31_t)0x18c7b838, (q31_t)0xcd6cde39, (q31_t)0x18bdcad0, (q31_t)0xcd74929a, + (q31_t)0x18b3deeb, (q31_t)0xcd7c48ee, (q31_t)0x18a9f48a, (q31_t)0xcd840134, + (q31_t)0x18a00bae, (q31_t)0xcd8bbb6d, (q31_t)0x18962456, (q31_t)0xcd937798, + (q31_t)0x188c3e83, (q31_t)0xcd9b35b4, (q31_t)0x18825a35, (q31_t)0xcda2f5c2, + (q31_t)0x1878776d, (q31_t)0xcdaab7c0, (q31_t)0x186e962b, (q31_t)0xcdb27bb0, + (q31_t)0x1864b670, (q31_t)0xcdba4190, (q31_t)0x185ad83c, (q31_t)0xcdc20960, + (q31_t)0x1850fb8e, (q31_t)0xcdc9d320, (q31_t)0x18472069, (q31_t)0xcdd19ed0, + (q31_t)0x183d46cc, (q31_t)0xcdd96c6f, (q31_t)0x18336eb7, (q31_t)0xcde13bfd, + (q31_t)0x1829982b, (q31_t)0xcde90d79, (q31_t)0x181fc328, (q31_t)0xcdf0e0e4, + (q31_t)0x1815efae, (q31_t)0xcdf8b63d, (q31_t)0x180c1dbf, (q31_t)0xce008d84, + (q31_t)0x18024d59, (q31_t)0xce0866b8, (q31_t)0x17f87e7f, (q31_t)0xce1041d9, + (q31_t)0x17eeb130, (q31_t)0xce181ee8, (q31_t)0x17e4e56c, (q31_t)0xce1ffde2, + (q31_t)0x17db1b34, (q31_t)0xce27dec9, (q31_t)0x17d15288, (q31_t)0xce2fc19c, + (q31_t)0x17c78b68, (q31_t)0xce37a65b, (q31_t)0x17bdc5d6, (q31_t)0xce3f8d05, + (q31_t)0x17b401d1, (q31_t)0xce47759a, (q31_t)0x17aa3f5a, (q31_t)0xce4f6019, + (q31_t)0x17a07e70, (q31_t)0xce574c84, (q31_t)0x1796bf16, (q31_t)0xce5f3ad8, + (q31_t)0x178d014a, (q31_t)0xce672b16, (q31_t)0x1783450d, (q31_t)0xce6f1d3d, + (q31_t)0x17798a60, (q31_t)0xce77114e, (q31_t)0x176fd143, (q31_t)0xce7f0748, + (q31_t)0x176619b6, (q31_t)0xce86ff2a, (q31_t)0x175c63ba, (q31_t)0xce8ef8f4, + (q31_t)0x1752af4f, (q31_t)0xce96f4a7, (q31_t)0x1748fc75, (q31_t)0xce9ef241, + (q31_t)0x173f4b2e, (q31_t)0xcea6f1c2, (q31_t)0x17359b78, (q31_t)0xceaef32b, + (q31_t)0x172bed55, (q31_t)0xceb6f67a, (q31_t)0x172240c5, (q31_t)0xcebefbb0, + (q31_t)0x171895c9, (q31_t)0xcec702cb, (q31_t)0x170eec60, (q31_t)0xcecf0bcd, + (q31_t)0x1705448b, (q31_t)0xced716b4, (q31_t)0x16fb9e4b, (q31_t)0xcedf2380, + (q31_t)0x16f1f99f, (q31_t)0xcee73231, (q31_t)0x16e85689, (q31_t)0xceef42c7, + (q31_t)0x16deb508, (q31_t)0xcef75541, (q31_t)0x16d5151d, (q31_t)0xceff699f, + (q31_t)0x16cb76c9, (q31_t)0xcf077fe1, (q31_t)0x16c1da0b, (q31_t)0xcf0f9805, + (q31_t)0x16b83ee4, (q31_t)0xcf17b20d, (q31_t)0x16aea555, (q31_t)0xcf1fcdf8, + (q31_t)0x16a50d5d, (q31_t)0xcf27ebc5, (q31_t)0x169b76fe, (q31_t)0xcf300b74, + (q31_t)0x1691e237, (q31_t)0xcf382d05, (q31_t)0x16884f09, (q31_t)0xcf405077, + (q31_t)0x167ebd74, (q31_t)0xcf4875ca, (q31_t)0x16752d79, (q31_t)0xcf509cfe, + (q31_t)0x166b9f18, (q31_t)0xcf58c613, (q31_t)0x16621251, (q31_t)0xcf60f108, + (q31_t)0x16588725, (q31_t)0xcf691ddd, (q31_t)0x164efd94, (q31_t)0xcf714c91, + (q31_t)0x1645759f, (q31_t)0xcf797d24, (q31_t)0x163bef46, (q31_t)0xcf81af97, + (q31_t)0x16326a88, (q31_t)0xcf89e3e8, (q31_t)0x1628e767, (q31_t)0xcf921a17, + (q31_t)0x161f65e4, (q31_t)0xcf9a5225, (q31_t)0x1615e5fd, (q31_t)0xcfa28c10, + (q31_t)0x160c67b4, (q31_t)0xcfaac7d8, (q31_t)0x1602eb0a, (q31_t)0xcfb3057d, + (q31_t)0x15f96ffd, (q31_t)0xcfbb4500, (q31_t)0x15eff690, (q31_t)0xcfc3865e, + (q31_t)0x15e67ec1, (q31_t)0xcfcbc999, (q31_t)0x15dd0892, (q31_t)0xcfd40eaf, + (q31_t)0x15d39403, (q31_t)0xcfdc55a1, (q31_t)0x15ca2115, (q31_t)0xcfe49e6d, + (q31_t)0x15c0afc6, (q31_t)0xcfece915, (q31_t)0x15b74019, (q31_t)0xcff53597, + (q31_t)0x15add20d, (q31_t)0xcffd83f4, (q31_t)0x15a465a3, (q31_t)0xd005d42a, + (q31_t)0x159afadb, (q31_t)0xd00e2639, (q31_t)0x159191b5, (q31_t)0xd0167a22, + (q31_t)0x15882a32, (q31_t)0xd01ecfe4, (q31_t)0x157ec452, (q31_t)0xd027277e, + (q31_t)0x15756016, (q31_t)0xd02f80f1, (q31_t)0x156bfd7d, (q31_t)0xd037dc3b, + (q31_t)0x15629c89, (q31_t)0xd040395d, (q31_t)0x15593d3a, (q31_t)0xd0489856, + (q31_t)0x154fdf8f, (q31_t)0xd050f926, (q31_t)0x15468389, (q31_t)0xd0595bcd, + (q31_t)0x153d292a, (q31_t)0xd061c04a, (q31_t)0x1533d070, (q31_t)0xd06a269d, + (q31_t)0x152a795d, (q31_t)0xd0728ec6, (q31_t)0x152123f0, (q31_t)0xd07af8c4, + (q31_t)0x1517d02b, (q31_t)0xd0836497, (q31_t)0x150e7e0d, (q31_t)0xd08bd23f, + (q31_t)0x15052d97, (q31_t)0xd09441bb, (q31_t)0x14fbdec9, (q31_t)0xd09cb30b, + (q31_t)0x14f291a4, (q31_t)0xd0a5262f, (q31_t)0x14e94627, (q31_t)0xd0ad9b26, + (q31_t)0x14dffc54, (q31_t)0xd0b611f1, (q31_t)0x14d6b42b, (q31_t)0xd0be8a8d, + (q31_t)0x14cd6dab, (q31_t)0xd0c704fd, (q31_t)0x14c428d6, (q31_t)0xd0cf813e, + (q31_t)0x14bae5ab, (q31_t)0xd0d7ff51, (q31_t)0x14b1a42c, (q31_t)0xd0e07f36, + (q31_t)0x14a86458, (q31_t)0xd0e900ec, (q31_t)0x149f2630, (q31_t)0xd0f18472, + (q31_t)0x1495e9b3, (q31_t)0xd0fa09c9, (q31_t)0x148caee4, (q31_t)0xd10290f0, + (q31_t)0x148375c1, (q31_t)0xd10b19e7, (q31_t)0x147a3e4b, (q31_t)0xd113a4ad, + (q31_t)0x14710883, (q31_t)0xd11c3142, (q31_t)0x1467d469, (q31_t)0xd124bfa6, + (q31_t)0x145ea1fd, (q31_t)0xd12d4fd9, (q31_t)0x14557140, (q31_t)0xd135e1d9, + (q31_t)0x144c4232, (q31_t)0xd13e75a8, (q31_t)0x144314d3, (q31_t)0xd1470b44, + (q31_t)0x1439e923, (q31_t)0xd14fa2ad, (q31_t)0x1430bf24, (q31_t)0xd1583be2, + (q31_t)0x142796d5, (q31_t)0xd160d6e5, (q31_t)0x141e7037, (q31_t)0xd16973b3, + (q31_t)0x14154b4a, (q31_t)0xd172124d, (q31_t)0x140c280e, (q31_t)0xd17ab2b3, + (q31_t)0x14030684, (q31_t)0xd18354e4, (q31_t)0x13f9e6ad, (q31_t)0xd18bf8e0, + (q31_t)0x13f0c887, (q31_t)0xd1949ea6, (q31_t)0x13e7ac15, (q31_t)0xd19d4636, + (q31_t)0x13de9156, (q31_t)0xd1a5ef90, (q31_t)0x13d5784a, (q31_t)0xd1ae9ab4, + (q31_t)0x13cc60f2, (q31_t)0xd1b747a0, (q31_t)0x13c34b4f, (q31_t)0xd1bff656, + (q31_t)0x13ba3760, (q31_t)0xd1c8a6d4, (q31_t)0x13b12526, (q31_t)0xd1d1591a, + (q31_t)0x13a814a2, (q31_t)0xd1da0d28, (q31_t)0x139f05d3, (q31_t)0xd1e2c2fd, + (q31_t)0x1395f8ba, (q31_t)0xd1eb7a9a, (q31_t)0x138ced57, (q31_t)0xd1f433fd, + (q31_t)0x1383e3ab, (q31_t)0xd1fcef27, (q31_t)0x137adbb6, (q31_t)0xd205ac17, + (q31_t)0x1371d579, (q31_t)0xd20e6acc, (q31_t)0x1368d0f3, (q31_t)0xd2172b48, + (q31_t)0x135fce26, (q31_t)0xd21fed88, (q31_t)0x1356cd11, (q31_t)0xd228b18d, + (q31_t)0x134dcdb4, (q31_t)0xd2317756, (q31_t)0x1344d011, (q31_t)0xd23a3ee4, + (q31_t)0x133bd427, (q31_t)0xd2430835, (q31_t)0x1332d9f7, (q31_t)0xd24bd34a, + (q31_t)0x1329e181, (q31_t)0xd254a021, (q31_t)0x1320eac6, (q31_t)0xd25d6ebc, + (q31_t)0x1317f5c6, (q31_t)0xd2663f19, (q31_t)0x130f0280, (q31_t)0xd26f1138, + (q31_t)0x130610f7, (q31_t)0xd277e518, (q31_t)0x12fd2129, (q31_t)0xd280babb, + (q31_t)0x12f43318, (q31_t)0xd289921e, (q31_t)0x12eb46c3, (q31_t)0xd2926b41, + (q31_t)0x12e25c2b, (q31_t)0xd29b4626, (q31_t)0x12d97350, (q31_t)0xd2a422ca, + (q31_t)0x12d08c33, (q31_t)0xd2ad012e, (q31_t)0x12c7a6d4, (q31_t)0xd2b5e151, + (q31_t)0x12bec333, (q31_t)0xd2bec333, (q31_t)0x12b5e151, (q31_t)0xd2c7a6d4, + (q31_t)0x12ad012e, (q31_t)0xd2d08c33, (q31_t)0x12a422ca, (q31_t)0xd2d97350, + (q31_t)0x129b4626, (q31_t)0xd2e25c2b, (q31_t)0x12926b41, (q31_t)0xd2eb46c3, + (q31_t)0x1289921e, (q31_t)0xd2f43318, (q31_t)0x1280babb, (q31_t)0xd2fd2129, + (q31_t)0x1277e518, (q31_t)0xd30610f7, (q31_t)0x126f1138, (q31_t)0xd30f0280, + (q31_t)0x12663f19, (q31_t)0xd317f5c6, (q31_t)0x125d6ebc, (q31_t)0xd320eac6, + (q31_t)0x1254a021, (q31_t)0xd329e181, (q31_t)0x124bd34a, (q31_t)0xd332d9f7, + (q31_t)0x12430835, (q31_t)0xd33bd427, (q31_t)0x123a3ee4, (q31_t)0xd344d011, + (q31_t)0x12317756, (q31_t)0xd34dcdb4, (q31_t)0x1228b18d, (q31_t)0xd356cd11, + (q31_t)0x121fed88, (q31_t)0xd35fce26, (q31_t)0x12172b48, (q31_t)0xd368d0f3, + (q31_t)0x120e6acc, (q31_t)0xd371d579, (q31_t)0x1205ac17, (q31_t)0xd37adbb6, + (q31_t)0x11fcef27, (q31_t)0xd383e3ab, (q31_t)0x11f433fd, (q31_t)0xd38ced57, + (q31_t)0x11eb7a9a, (q31_t)0xd395f8ba, (q31_t)0x11e2c2fd, (q31_t)0xd39f05d3, + (q31_t)0x11da0d28, (q31_t)0xd3a814a2, (q31_t)0x11d1591a, (q31_t)0xd3b12526, + (q31_t)0x11c8a6d4, (q31_t)0xd3ba3760, (q31_t)0x11bff656, (q31_t)0xd3c34b4f, + (q31_t)0x11b747a0, (q31_t)0xd3cc60f2, (q31_t)0x11ae9ab4, (q31_t)0xd3d5784a, + (q31_t)0x11a5ef90, (q31_t)0xd3de9156, (q31_t)0x119d4636, (q31_t)0xd3e7ac15, + (q31_t)0x11949ea6, (q31_t)0xd3f0c887, (q31_t)0x118bf8e0, (q31_t)0xd3f9e6ad, + (q31_t)0x118354e4, (q31_t)0xd4030684, (q31_t)0x117ab2b3, (q31_t)0xd40c280e, + (q31_t)0x1172124d, (q31_t)0xd4154b4a, (q31_t)0x116973b3, (q31_t)0xd41e7037, + (q31_t)0x1160d6e5, (q31_t)0xd42796d5, (q31_t)0x11583be2, (q31_t)0xd430bf24, + (q31_t)0x114fa2ad, (q31_t)0xd439e923, (q31_t)0x11470b44, (q31_t)0xd44314d3, + (q31_t)0x113e75a8, (q31_t)0xd44c4232, (q31_t)0x1135e1d9, (q31_t)0xd4557140, + (q31_t)0x112d4fd9, (q31_t)0xd45ea1fd, (q31_t)0x1124bfa6, (q31_t)0xd467d469, + (q31_t)0x111c3142, (q31_t)0xd4710883, (q31_t)0x1113a4ad, (q31_t)0xd47a3e4b, + (q31_t)0x110b19e7, (q31_t)0xd48375c1, (q31_t)0x110290f0, (q31_t)0xd48caee4, + (q31_t)0x10fa09c9, (q31_t)0xd495e9b3, (q31_t)0x10f18472, (q31_t)0xd49f2630, + (q31_t)0x10e900ec, (q31_t)0xd4a86458, (q31_t)0x10e07f36, (q31_t)0xd4b1a42c, + (q31_t)0x10d7ff51, (q31_t)0xd4bae5ab, (q31_t)0x10cf813e, (q31_t)0xd4c428d6, + (q31_t)0x10c704fd, (q31_t)0xd4cd6dab, (q31_t)0x10be8a8d, (q31_t)0xd4d6b42b, + (q31_t)0x10b611f1, (q31_t)0xd4dffc54, (q31_t)0x10ad9b26, (q31_t)0xd4e94627, + (q31_t)0x10a5262f, (q31_t)0xd4f291a4, (q31_t)0x109cb30b, (q31_t)0xd4fbdec9, + (q31_t)0x109441bb, (q31_t)0xd5052d97, (q31_t)0x108bd23f, (q31_t)0xd50e7e0d, + (q31_t)0x10836497, (q31_t)0xd517d02b, (q31_t)0x107af8c4, (q31_t)0xd52123f0, + (q31_t)0x10728ec6, (q31_t)0xd52a795d, (q31_t)0x106a269d, (q31_t)0xd533d070, + (q31_t)0x1061c04a, (q31_t)0xd53d292a, (q31_t)0x10595bcd, (q31_t)0xd5468389, + (q31_t)0x1050f926, (q31_t)0xd54fdf8f, (q31_t)0x10489856, (q31_t)0xd5593d3a, + (q31_t)0x1040395d, (q31_t)0xd5629c89, (q31_t)0x1037dc3b, (q31_t)0xd56bfd7d, + (q31_t)0x102f80f1, (q31_t)0xd5756016, (q31_t)0x1027277e, (q31_t)0xd57ec452, + (q31_t)0x101ecfe4, (q31_t)0xd5882a32, (q31_t)0x10167a22, (q31_t)0xd59191b5, + (q31_t)0x100e2639, (q31_t)0xd59afadb, (q31_t)0x1005d42a, (q31_t)0xd5a465a3, + (q31_t)0xffd83f4, (q31_t)0xd5add20d, (q31_t)0xff53597, (q31_t)0xd5b74019, + (q31_t)0xfece915, (q31_t)0xd5c0afc6, (q31_t)0xfe49e6d, (q31_t)0xd5ca2115, + (q31_t)0xfdc55a1, (q31_t)0xd5d39403, (q31_t)0xfd40eaf, (q31_t)0xd5dd0892, + (q31_t)0xfcbc999, (q31_t)0xd5e67ec1, (q31_t)0xfc3865e, (q31_t)0xd5eff690, + (q31_t)0xfbb4500, (q31_t)0xd5f96ffd, (q31_t)0xfb3057d, (q31_t)0xd602eb0a, + (q31_t)0xfaac7d8, (q31_t)0xd60c67b4, (q31_t)0xfa28c10, (q31_t)0xd615e5fd, + (q31_t)0xf9a5225, (q31_t)0xd61f65e4, (q31_t)0xf921a17, (q31_t)0xd628e767, + (q31_t)0xf89e3e8, (q31_t)0xd6326a88, (q31_t)0xf81af97, (q31_t)0xd63bef46, + (q31_t)0xf797d24, (q31_t)0xd645759f, (q31_t)0xf714c91, (q31_t)0xd64efd94, + (q31_t)0xf691ddd, (q31_t)0xd6588725, (q31_t)0xf60f108, (q31_t)0xd6621251, + (q31_t)0xf58c613, (q31_t)0xd66b9f18, (q31_t)0xf509cfe, (q31_t)0xd6752d79, + (q31_t)0xf4875ca, (q31_t)0xd67ebd74, (q31_t)0xf405077, (q31_t)0xd6884f09, + (q31_t)0xf382d05, (q31_t)0xd691e237, (q31_t)0xf300b74, (q31_t)0xd69b76fe, + (q31_t)0xf27ebc5, (q31_t)0xd6a50d5d, (q31_t)0xf1fcdf8, (q31_t)0xd6aea555, + (q31_t)0xf17b20d, (q31_t)0xd6b83ee4, (q31_t)0xf0f9805, (q31_t)0xd6c1da0b, + (q31_t)0xf077fe1, (q31_t)0xd6cb76c9, (q31_t)0xeff699f, (q31_t)0xd6d5151d, + (q31_t)0xef75541, (q31_t)0xd6deb508, (q31_t)0xeef42c7, (q31_t)0xd6e85689, + (q31_t)0xee73231, (q31_t)0xd6f1f99f, (q31_t)0xedf2380, (q31_t)0xd6fb9e4b, + (q31_t)0xed716b4, (q31_t)0xd705448b, (q31_t)0xecf0bcd, (q31_t)0xd70eec60, + (q31_t)0xec702cb, (q31_t)0xd71895c9, (q31_t)0xebefbb0, (q31_t)0xd72240c5, + (q31_t)0xeb6f67a, (q31_t)0xd72bed55, (q31_t)0xeaef32b, (q31_t)0xd7359b78, + (q31_t)0xea6f1c2, (q31_t)0xd73f4b2e, (q31_t)0xe9ef241, (q31_t)0xd748fc75, + (q31_t)0xe96f4a7, (q31_t)0xd752af4f, (q31_t)0xe8ef8f4, (q31_t)0xd75c63ba, + (q31_t)0xe86ff2a, (q31_t)0xd76619b6, (q31_t)0xe7f0748, (q31_t)0xd76fd143, + (q31_t)0xe77114e, (q31_t)0xd7798a60, (q31_t)0xe6f1d3d, (q31_t)0xd783450d, + (q31_t)0xe672b16, (q31_t)0xd78d014a, (q31_t)0xe5f3ad8, (q31_t)0xd796bf16, + (q31_t)0xe574c84, (q31_t)0xd7a07e70, (q31_t)0xe4f6019, (q31_t)0xd7aa3f5a, + (q31_t)0xe47759a, (q31_t)0xd7b401d1, (q31_t)0xe3f8d05, (q31_t)0xd7bdc5d6, + (q31_t)0xe37a65b, (q31_t)0xd7c78b68, (q31_t)0xe2fc19c, (q31_t)0xd7d15288, + (q31_t)0xe27dec9, (q31_t)0xd7db1b34, (q31_t)0xe1ffde2, (q31_t)0xd7e4e56c, + (q31_t)0xe181ee8, (q31_t)0xd7eeb130, (q31_t)0xe1041d9, (q31_t)0xd7f87e7f, + (q31_t)0xe0866b8, (q31_t)0xd8024d59, (q31_t)0xe008d84, (q31_t)0xd80c1dbf, + (q31_t)0xdf8b63d, (q31_t)0xd815efae, (q31_t)0xdf0e0e4, (q31_t)0xd81fc328, + (q31_t)0xde90d79, (q31_t)0xd829982b, (q31_t)0xde13bfd, (q31_t)0xd8336eb7, + (q31_t)0xdd96c6f, (q31_t)0xd83d46cc, (q31_t)0xdd19ed0, (q31_t)0xd8472069, + (q31_t)0xdc9d320, (q31_t)0xd850fb8e, (q31_t)0xdc20960, (q31_t)0xd85ad83c, + (q31_t)0xdba4190, (q31_t)0xd864b670, (q31_t)0xdb27bb0, (q31_t)0xd86e962b, + (q31_t)0xdaab7c0, (q31_t)0xd878776d, (q31_t)0xda2f5c2, (q31_t)0xd8825a35, + (q31_t)0xd9b35b4, (q31_t)0xd88c3e83, (q31_t)0xd937798, (q31_t)0xd8962456, + (q31_t)0xd8bbb6d, (q31_t)0xd8a00bae, (q31_t)0xd840134, (q31_t)0xd8a9f48a, + (q31_t)0xd7c48ee, (q31_t)0xd8b3deeb, (q31_t)0xd74929a, (q31_t)0xd8bdcad0, + (q31_t)0xd6cde39, (q31_t)0xd8c7b838, (q31_t)0xd652bcb, (q31_t)0xd8d1a724, + (q31_t)0xd5d7b50, (q31_t)0xd8db9792, (q31_t)0xd55ccca, (q31_t)0xd8e58982, + (q31_t)0xd4e2037, (q31_t)0xd8ef7cf4, (q31_t)0xd467599, (q31_t)0xd8f971e8, + (q31_t)0xd3eccef, (q31_t)0xd903685d, (q31_t)0xd37263a, (q31_t)0xd90d6053, + (q31_t)0xd2f817b, (q31_t)0xd91759c9, (q31_t)0xd27deb0, (q31_t)0xd92154bf, + (q31_t)0xd203ddc, (q31_t)0xd92b5135, (q31_t)0xd189efe, (q31_t)0xd9354f2a, + (q31_t)0xd110216, (q31_t)0xd93f4e9e, (q31_t)0xd096725, (q31_t)0xd9494f90, + (q31_t)0xd01ce2b, (q31_t)0xd9535201, (q31_t)0xcfa3729, (q31_t)0xd95d55ef, + (q31_t)0xcf2a21d, (q31_t)0xd9675b5a, (q31_t)0xceb0f0a, (q31_t)0xd9716243, + (q31_t)0xce37def, (q31_t)0xd97b6aa8, (q31_t)0xcdbeecc, (q31_t)0xd9857489, + (q31_t)0xcd461a2, (q31_t)0xd98f7fe6, (q31_t)0xcccd671, (q31_t)0xd9998cbe, + (q31_t)0xcc54d3a, (q31_t)0xd9a39b11, (q31_t)0xcbdc5fc, (q31_t)0xd9adaadf, + (q31_t)0xcb640b8, (q31_t)0xd9b7bc27, (q31_t)0xcaebd6e, (q31_t)0xd9c1cee9, + (q31_t)0xca73c1e, (q31_t)0xd9cbe325, (q31_t)0xc9fbcca, (q31_t)0xd9d5f8d9, + (q31_t)0xc983f70, (q31_t)0xd9e01006, (q31_t)0xc90c412, (q31_t)0xd9ea28ac, + (q31_t)0xc894aaf, (q31_t)0xd9f442c9, (q31_t)0xc81d349, (q31_t)0xd9fe5e5e, + (q31_t)0xc7a5dde, (q31_t)0xda087b69, (q31_t)0xc72ea70, (q31_t)0xda1299ec, + (q31_t)0xc6b78ff, (q31_t)0xda1cb9e5, (q31_t)0xc64098b, (q31_t)0xda26db54, + (q31_t)0xc5c9c14, (q31_t)0xda30fe38, (q31_t)0xc55309b, (q31_t)0xda3b2292, + (q31_t)0xc4dc720, (q31_t)0xda454860, (q31_t)0xc465fa3, (q31_t)0xda4f6fa3, + (q31_t)0xc3efa25, (q31_t)0xda599859, (q31_t)0xc3796a5, (q31_t)0xda63c284, + (q31_t)0xc303524, (q31_t)0xda6dee21, (q31_t)0xc28d5a3, (q31_t)0xda781b31, + (q31_t)0xc217822, (q31_t)0xda8249b4, (q31_t)0xc1a1ca0, (q31_t)0xda8c79a9, + (q31_t)0xc12c31f, (q31_t)0xda96ab0f, (q31_t)0xc0b6b9e, (q31_t)0xdaa0dde7, + (q31_t)0xc04161e, (q31_t)0xdaab122f, (q31_t)0xbfcc29f, (q31_t)0xdab547e8, + (q31_t)0xbf57121, (q31_t)0xdabf7f11, (q31_t)0xbee21a5, (q31_t)0xdac9b7a9, + (q31_t)0xbe6d42b, (q31_t)0xdad3f1b1, (q31_t)0xbdf88b3, (q31_t)0xdade2d28, + (q31_t)0xbd83f3d, (q31_t)0xdae86a0d, (q31_t)0xbd0f7ca, (q31_t)0xdaf2a860, + (q31_t)0xbc9b25a, (q31_t)0xdafce821, (q31_t)0xbc26eee, (q31_t)0xdb072950, + (q31_t)0xbbb2d85, (q31_t)0xdb116beb, (q31_t)0xbb3ee20, (q31_t)0xdb1baff2, + (q31_t)0xbacb0bf, (q31_t)0xdb25f566, (q31_t)0xba57563, (q31_t)0xdb303c46, + (q31_t)0xb9e3c0b, (q31_t)0xdb3a8491, (q31_t)0xb9704b9, (q31_t)0xdb44ce46, + (q31_t)0xb8fcf6b, (q31_t)0xdb4f1967, (q31_t)0xb889c23, (q31_t)0xdb5965f1, + (q31_t)0xb816ae1, (q31_t)0xdb63b3e5, (q31_t)0xb7a3ba5, (q31_t)0xdb6e0342, + (q31_t)0xb730e70, (q31_t)0xdb785409, (q31_t)0xb6be341, (q31_t)0xdb82a638, + (q31_t)0xb64ba19, (q31_t)0xdb8cf9cf, (q31_t)0xb5d92f8, (q31_t)0xdb974ece, + (q31_t)0xb566ddf, (q31_t)0xdba1a534, (q31_t)0xb4f4acd, (q31_t)0xdbabfd01, + (q31_t)0xb4829c4, (q31_t)0xdbb65634, (q31_t)0xb410ac3, (q31_t)0xdbc0b0ce, + (q31_t)0xb39edca, (q31_t)0xdbcb0cce, (q31_t)0xb32d2da, (q31_t)0xdbd56a32, + (q31_t)0xb2bb9f4, (q31_t)0xdbdfc8fc, (q31_t)0xb24a316, (q31_t)0xdbea292b, + (q31_t)0xb1d8e43, (q31_t)0xdbf48abd, (q31_t)0xb167b79, (q31_t)0xdbfeedb3, + (q31_t)0xb0f6aba, (q31_t)0xdc09520d, (q31_t)0xb085c05, (q31_t)0xdc13b7c9, + (q31_t)0xb014f5b, (q31_t)0xdc1e1ee9, (q31_t)0xafa44bc, (q31_t)0xdc28876a, + (q31_t)0xaf33c28, (q31_t)0xdc32f14d, (q31_t)0xaec35a0, (q31_t)0xdc3d5c91, + (q31_t)0xae53123, (q31_t)0xdc47c936, (q31_t)0xade2eb3, (q31_t)0xdc52373c, + (q31_t)0xad72e4f, (q31_t)0xdc5ca6a2, (q31_t)0xad02ff8, (q31_t)0xdc671768, + (q31_t)0xac933ae, (q31_t)0xdc71898d, (q31_t)0xac23971, (q31_t)0xdc7bfd11, + (q31_t)0xabb4141, (q31_t)0xdc8671f3, (q31_t)0xab44b1f, (q31_t)0xdc90e834, + (q31_t)0xaad570c, (q31_t)0xdc9b5fd2, (q31_t)0xaa66506, (q31_t)0xdca5d8cd, + (q31_t)0xa9f750f, (q31_t)0xdcb05326, (q31_t)0xa988727, (q31_t)0xdcbacedb, + (q31_t)0xa919b4e, (q31_t)0xdcc54bec, (q31_t)0xa8ab184, (q31_t)0xdccfca59, + (q31_t)0xa83c9ca, (q31_t)0xdcda4a21, (q31_t)0xa7ce420, (q31_t)0xdce4cb44, + (q31_t)0xa760086, (q31_t)0xdcef4dc2, (q31_t)0xa6f1efc, (q31_t)0xdcf9d199, + (q31_t)0xa683f83, (q31_t)0xdd0456ca, (q31_t)0xa61621b, (q31_t)0xdd0edd55, + (q31_t)0xa5a86c4, (q31_t)0xdd196538, (q31_t)0xa53ad7e, (q31_t)0xdd23ee74, + (q31_t)0xa4cd64b, (q31_t)0xdd2e7908, (q31_t)0xa460129, (q31_t)0xdd3904f4, + (q31_t)0xa3f2e19, (q31_t)0xdd439236, (q31_t)0xa385d1d, (q31_t)0xdd4e20d0, + (q31_t)0xa318e32, (q31_t)0xdd58b0c0, (q31_t)0xa2ac15b, (q31_t)0xdd634206, + (q31_t)0xa23f698, (q31_t)0xdd6dd4a2, (q31_t)0xa1d2de7, (q31_t)0xdd786892, + (q31_t)0xa16674b, (q31_t)0xdd82fdd8, (q31_t)0xa0fa2c3, (q31_t)0xdd8d9472, + (q31_t)0xa08e04f, (q31_t)0xdd982c60, (q31_t)0xa021fef, (q31_t)0xdda2c5a2, + (q31_t)0x9fb61a5, (q31_t)0xddad6036, (q31_t)0x9f4a570, (q31_t)0xddb7fc1e, + (q31_t)0x9edeb50, (q31_t)0xddc29958, (q31_t)0x9e73346, (q31_t)0xddcd37e4, + (q31_t)0x9e07d51, (q31_t)0xddd7d7c1, (q31_t)0x9d9c973, (q31_t)0xdde278ef, + (q31_t)0x9d317ab, (q31_t)0xdded1b6e, (q31_t)0x9cc67fa, (q31_t)0xddf7bf3e, + (q31_t)0x9c5ba60, (q31_t)0xde02645d, (q31_t)0x9bf0edd, (q31_t)0xde0d0acc, + (q31_t)0x9b86572, (q31_t)0xde17b28a, (q31_t)0x9b1be1e, (q31_t)0xde225b96, + (q31_t)0x9ab18e3, (q31_t)0xde2d05f1, (q31_t)0x9a475bf, (q31_t)0xde37b199, + (q31_t)0x99dd4b4, (q31_t)0xde425e8f, (q31_t)0x99735c2, (q31_t)0xde4d0cd2, + (q31_t)0x99098e9, (q31_t)0xde57bc62, (q31_t)0x989fe29, (q31_t)0xde626d3e, + (q31_t)0x9836582, (q31_t)0xde6d1f65, (q31_t)0x97ccef5, (q31_t)0xde77d2d8, + (q31_t)0x9763a83, (q31_t)0xde828796, (q31_t)0x96fa82a, (q31_t)0xde8d3d9e, + (q31_t)0x96917ec, (q31_t)0xde97f4f1, (q31_t)0x96289c9, (q31_t)0xdea2ad8d, + (q31_t)0x95bfdc1, (q31_t)0xdead6773, (q31_t)0x95573d4, (q31_t)0xdeb822a1, + (q31_t)0x94eec03, (q31_t)0xdec2df18, (q31_t)0x948664d, (q31_t)0xdecd9cd7, + (q31_t)0x941e2b4, (q31_t)0xded85bdd, (q31_t)0x93b6137, (q31_t)0xdee31c2b, + (q31_t)0x934e1d6, (q31_t)0xdeedddc0, (q31_t)0x92e6492, (q31_t)0xdef8a09b, + (q31_t)0x927e96b, (q31_t)0xdf0364bc, (q31_t)0x9217062, (q31_t)0xdf0e2a22, + (q31_t)0x91af976, (q31_t)0xdf18f0ce, (q31_t)0x91484a8, (q31_t)0xdf23b8be, + (q31_t)0x90e11f7, (q31_t)0xdf2e81f3, (q31_t)0x907a166, (q31_t)0xdf394c6b, + (q31_t)0x90132f2, (q31_t)0xdf441828, (q31_t)0x8fac69e, (q31_t)0xdf4ee527, + (q31_t)0x8f45c68, (q31_t)0xdf59b369, (q31_t)0x8edf452, (q31_t)0xdf6482ed, + (q31_t)0x8e78e5b, (q31_t)0xdf6f53b3, (q31_t)0x8e12a84, (q31_t)0xdf7a25ba, + (q31_t)0x8dac8cd, (q31_t)0xdf84f902, (q31_t)0x8d46936, (q31_t)0xdf8fcd8b, + (q31_t)0x8ce0bc0, (q31_t)0xdf9aa354, (q31_t)0x8c7b06b, (q31_t)0xdfa57a5d, + (q31_t)0x8c15736, (q31_t)0xdfb052a5, (q31_t)0x8bb0023, (q31_t)0xdfbb2c2c, + (q31_t)0x8b4ab32, (q31_t)0xdfc606f1, (q31_t)0x8ae5862, (q31_t)0xdfd0e2f5, + (q31_t)0x8a807b4, (q31_t)0xdfdbc036, (q31_t)0x8a1b928, (q31_t)0xdfe69eb4, + (q31_t)0x89b6cbf, (q31_t)0xdff17e70, (q31_t)0x8952278, (q31_t)0xdffc5f67, + (q31_t)0x88eda54, (q31_t)0xe007419b, (q31_t)0x8889454, (q31_t)0xe012250a, + (q31_t)0x8825077, (q31_t)0xe01d09b4, (q31_t)0x87c0ebd, (q31_t)0xe027ef99, + (q31_t)0x875cf28, (q31_t)0xe032d6b8, (q31_t)0x86f91b7, (q31_t)0xe03dbf11, + (q31_t)0x869566a, (q31_t)0xe048a8a4, (q31_t)0x8631d42, (q31_t)0xe053936f, + (q31_t)0x85ce63e, (q31_t)0xe05e7f74, (q31_t)0x856b160, (q31_t)0xe0696cb0, + (q31_t)0x8507ea7, (q31_t)0xe0745b24, (q31_t)0x84a4e14, (q31_t)0xe07f4acf, + (q31_t)0x8441fa6, (q31_t)0xe08a3bb2, (q31_t)0x83df35f, (q31_t)0xe0952dcb, + (q31_t)0x837c93e, (q31_t)0xe0a0211a, (q31_t)0x831a143, (q31_t)0xe0ab159e, + (q31_t)0x82b7b70, (q31_t)0xe0b60b58, (q31_t)0x82557c3, (q31_t)0xe0c10247, + (q31_t)0x81f363d, (q31_t)0xe0cbfa6a, (q31_t)0x81916df, (q31_t)0xe0d6f3c1, + (q31_t)0x812f9a9, (q31_t)0xe0e1ee4b, (q31_t)0x80cde9b, (q31_t)0xe0ecea09, + (q31_t)0x806c5b5, (q31_t)0xe0f7e6f9, (q31_t)0x800aef7, (q31_t)0xe102e51c, + (q31_t)0x7fa9a62, (q31_t)0xe10de470, (q31_t)0x7f487f6, (q31_t)0xe118e4f6, + (q31_t)0x7ee77b3, (q31_t)0xe123e6ad, (q31_t)0x7e8699a, (q31_t)0xe12ee995, + (q31_t)0x7e25daa, (q31_t)0xe139edac, (q31_t)0x7dc53e3, (q31_t)0xe144f2f3, + (q31_t)0x7d64c47, (q31_t)0xe14ff96a, (q31_t)0x7d046d6, (q31_t)0xe15b0110, + (q31_t)0x7ca438f, (q31_t)0xe16609e3, (q31_t)0x7c44272, (q31_t)0xe17113e5, + (q31_t)0x7be4381, (q31_t)0xe17c1f15, (q31_t)0x7b846ba, (q31_t)0xe1872b72, + (q31_t)0x7b24c20, (q31_t)0xe19238fb, (q31_t)0x7ac53b1, (q31_t)0xe19d47b1, + (q31_t)0x7a65d6e, (q31_t)0xe1a85793, (q31_t)0x7a06957, (q31_t)0xe1b368a0, + (q31_t)0x79a776c, (q31_t)0xe1be7ad8, (q31_t)0x79487ae, (q31_t)0xe1c98e3b, + (q31_t)0x78e9a1d, (q31_t)0xe1d4a2c8, (q31_t)0x788aeb9, (q31_t)0xe1dfb87f, + (q31_t)0x782c582, (q31_t)0xe1eacf5f, (q31_t)0x77cde79, (q31_t)0xe1f5e768, + (q31_t)0x776f99d, (q31_t)0xe2010099, (q31_t)0x77116f0, (q31_t)0xe20c1af3, + (q31_t)0x76b3671, (q31_t)0xe2173674, (q31_t)0x7655820, (q31_t)0xe222531c, + (q31_t)0x75f7bfe, (q31_t)0xe22d70eb, (q31_t)0x759a20a, (q31_t)0xe2388fe1, + (q31_t)0x753ca46, (q31_t)0xe243affc, (q31_t)0x74df4b1, (q31_t)0xe24ed13d, + (q31_t)0x748214c, (q31_t)0xe259f3a3, (q31_t)0x7425016, (q31_t)0xe265172e, + (q31_t)0x73c8111, (q31_t)0xe2703bdc, (q31_t)0x736b43c, (q31_t)0xe27b61af, + (q31_t)0x730e997, (q31_t)0xe28688a4, (q31_t)0x72b2123, (q31_t)0xe291b0bd, + (q31_t)0x7255ae0, (q31_t)0xe29cd9f8, (q31_t)0x71f96ce, (q31_t)0xe2a80456, + (q31_t)0x719d4ed, (q31_t)0xe2b32fd4, (q31_t)0x714153e, (q31_t)0xe2be5c74, + (q31_t)0x70e57c0, (q31_t)0xe2c98a35, (q31_t)0x7089c75, (q31_t)0xe2d4b916, + (q31_t)0x702e35c, (q31_t)0xe2dfe917, (q31_t)0x6fd2c75, (q31_t)0xe2eb1a37, + (q31_t)0x6f777c1, (q31_t)0xe2f64c77, (q31_t)0x6f1c540, (q31_t)0xe3017fd5, + (q31_t)0x6ec14f2, (q31_t)0xe30cb451, (q31_t)0x6e666d7, (q31_t)0xe317e9eb, + (q31_t)0x6e0baf0, (q31_t)0xe32320a2, (q31_t)0x6db113d, (q31_t)0xe32e5876, + (q31_t)0x6d569be, (q31_t)0xe3399167, (q31_t)0x6cfc472, (q31_t)0xe344cb73, + (q31_t)0x6ca215c, (q31_t)0xe350069b, (q31_t)0x6c4807a, (q31_t)0xe35b42df, + (q31_t)0x6bee1cd, (q31_t)0xe366803c, (q31_t)0x6b94554, (q31_t)0xe371beb5, + (q31_t)0x6b3ab12, (q31_t)0xe37cfe47, (q31_t)0x6ae1304, (q31_t)0xe3883ef2, + (q31_t)0x6a87d2d, (q31_t)0xe39380b6, (q31_t)0x6a2e98b, (q31_t)0xe39ec393, + (q31_t)0x69d5820, (q31_t)0xe3aa0788, (q31_t)0x697c8eb, (q31_t)0xe3b54c95, + (q31_t)0x6923bec, (q31_t)0xe3c092b9, (q31_t)0x68cb124, (q31_t)0xe3cbd9f4, + (q31_t)0x6872894, (q31_t)0xe3d72245, (q31_t)0x681a23a, (q31_t)0xe3e26bac, + (q31_t)0x67c1e18, (q31_t)0xe3edb628, (q31_t)0x6769c2e, (q31_t)0xe3f901ba, + (q31_t)0x6711c7b, (q31_t)0xe4044e60, (q31_t)0x66b9f01, (q31_t)0xe40f9c1a, + (q31_t)0x66623be, (q31_t)0xe41aeae8, (q31_t)0x660aab5, (q31_t)0xe4263ac9, + (q31_t)0x65b33e4, (q31_t)0xe4318bbe, (q31_t)0x655bf4c, (q31_t)0xe43cddc4, + (q31_t)0x6504ced, (q31_t)0xe44830dd, (q31_t)0x64adcc7, (q31_t)0xe4538507, + (q31_t)0x6456edb, (q31_t)0xe45eda43, (q31_t)0x6400329, (q31_t)0xe46a308f, + (q31_t)0x63a99b1, (q31_t)0xe47587eb, (q31_t)0x6353273, (q31_t)0xe480e057, + (q31_t)0x62fcd6f, (q31_t)0xe48c39d3, (q31_t)0x62a6aa6, (q31_t)0xe497945d, + (q31_t)0x6250a18, (q31_t)0xe4a2eff6, (q31_t)0x61fabc4, (q31_t)0xe4ae4c9d, + (q31_t)0x61a4fac, (q31_t)0xe4b9aa52, (q31_t)0x614f5cf, (q31_t)0xe4c50914, + (q31_t)0x60f9e2e, (q31_t)0xe4d068e2, (q31_t)0x60a48c9, (q31_t)0xe4dbc9bd, + (q31_t)0x604f5a0, (q31_t)0xe4e72ba4, (q31_t)0x5ffa4b3, (q31_t)0xe4f28e96, + (q31_t)0x5fa5603, (q31_t)0xe4fdf294, (q31_t)0x5f5098f, (q31_t)0xe509579b, + (q31_t)0x5efbf58, (q31_t)0xe514bdad, (q31_t)0x5ea775e, (q31_t)0xe52024c9, + (q31_t)0x5e531a1, (q31_t)0xe52b8cee, (q31_t)0x5dfee22, (q31_t)0xe536f61b, + (q31_t)0x5daace1, (q31_t)0xe5426051, (q31_t)0x5d56ddd, (q31_t)0xe54dcb8f, + (q31_t)0x5d03118, (q31_t)0xe55937d5, (q31_t)0x5caf690, (q31_t)0xe564a521, + (q31_t)0x5c5be47, (q31_t)0xe5701374, (q31_t)0x5c0883d, (q31_t)0xe57b82cd, + (q31_t)0x5bb5472, (q31_t)0xe586f32c, (q31_t)0x5b622e6, (q31_t)0xe5926490, + (q31_t)0x5b0f399, (q31_t)0xe59dd6f9, (q31_t)0x5abc68c, (q31_t)0xe5a94a67, + (q31_t)0x5a69bbe, (q31_t)0xe5b4bed8, (q31_t)0x5a17330, (q31_t)0xe5c0344d, + (q31_t)0x59c4ce3, (q31_t)0xe5cbaac5, (q31_t)0x59728d5, (q31_t)0xe5d72240, + (q31_t)0x5920708, (q31_t)0xe5e29abc, (q31_t)0x58ce77c, (q31_t)0xe5ee143b, + (q31_t)0x587ca31, (q31_t)0xe5f98ebb, (q31_t)0x582af26, (q31_t)0xe6050a3b, + (q31_t)0x57d965d, (q31_t)0xe61086bc, (q31_t)0x5787fd6, (q31_t)0xe61c043d, + (q31_t)0x5736b90, (q31_t)0xe62782be, (q31_t)0x56e598c, (q31_t)0xe633023e, + (q31_t)0x56949ca, (q31_t)0xe63e82bc, (q31_t)0x5643c4a, (q31_t)0xe64a0438, + (q31_t)0x55f310d, (q31_t)0xe65586b3, (q31_t)0x55a2812, (q31_t)0xe6610a2a, + (q31_t)0x555215a, (q31_t)0xe66c8e9f, (q31_t)0x5501ce5, (q31_t)0xe6781410, + (q31_t)0x54b1ab4, (q31_t)0xe6839a7c, (q31_t)0x5461ac6, (q31_t)0xe68f21e5, + (q31_t)0x5411d1b, (q31_t)0xe69aaa48, (q31_t)0x53c21b4, (q31_t)0xe6a633a6, + (q31_t)0x5372891, (q31_t)0xe6b1bdff, (q31_t)0x53231b3, (q31_t)0xe6bd4951, + (q31_t)0x52d3d18, (q31_t)0xe6c8d59c, (q31_t)0x5284ac3, (q31_t)0xe6d462e1, + (q31_t)0x5235ab2, (q31_t)0xe6dff11d, (q31_t)0x51e6ce6, (q31_t)0xe6eb8052, + (q31_t)0x519815f, (q31_t)0xe6f7107e, (q31_t)0x514981d, (q31_t)0xe702a1a1, + (q31_t)0x50fb121, (q31_t)0xe70e33bb, (q31_t)0x50acc6b, (q31_t)0xe719c6cb, + (q31_t)0x505e9fb, (q31_t)0xe7255ad1, (q31_t)0x50109d0, (q31_t)0xe730efcc, + (q31_t)0x4fc2bec, (q31_t)0xe73c85bc, (q31_t)0x4f7504e, (q31_t)0xe7481ca1, + (q31_t)0x4f276f7, (q31_t)0xe753b479, (q31_t)0x4ed9fe7, (q31_t)0xe75f4d45, + (q31_t)0x4e8cb1e, (q31_t)0xe76ae704, (q31_t)0x4e3f89c, (q31_t)0xe77681b6, + (q31_t)0x4df2862, (q31_t)0xe7821d59, (q31_t)0x4da5a6f, (q31_t)0xe78db9ef, + (q31_t)0x4d58ec3, (q31_t)0xe7995776, (q31_t)0x4d0c560, (q31_t)0xe7a4f5ed, + (q31_t)0x4cbfe45, (q31_t)0xe7b09555, (q31_t)0x4c73972, (q31_t)0xe7bc35ad, + (q31_t)0x4c276e8, (q31_t)0xe7c7d6f4, (q31_t)0x4bdb6a6, (q31_t)0xe7d3792b, + (q31_t)0x4b8f8ad, (q31_t)0xe7df1c50, (q31_t)0x4b43cfd, (q31_t)0xe7eac063, + (q31_t)0x4af8397, (q31_t)0xe7f66564, (q31_t)0x4aacc7a, (q31_t)0xe8020b52, + (q31_t)0x4a617a6, (q31_t)0xe80db22d, (q31_t)0x4a1651c, (q31_t)0xe81959f4, + (q31_t)0x49cb4dd, (q31_t)0xe82502a7, (q31_t)0x49806e7, (q31_t)0xe830ac45, + (q31_t)0x4935b3c, (q31_t)0xe83c56cf, (q31_t)0x48eb1db, (q31_t)0xe8480243, + (q31_t)0x48a0ac4, (q31_t)0xe853aea1, (q31_t)0x48565f9, (q31_t)0xe85f5be9, + (q31_t)0x480c379, (q31_t)0xe86b0a1a, (q31_t)0x47c2344, (q31_t)0xe876b934, + (q31_t)0x477855a, (q31_t)0xe8826936, (q31_t)0x472e9bc, (q31_t)0xe88e1a20, + (q31_t)0x46e5069, (q31_t)0xe899cbf1, (q31_t)0x469b963, (q31_t)0xe8a57ea9, + (q31_t)0x46524a9, (q31_t)0xe8b13248, (q31_t)0x460923b, (q31_t)0xe8bce6cd, + (q31_t)0x45c0219, (q31_t)0xe8c89c37, (q31_t)0x4577444, (q31_t)0xe8d45286, + (q31_t)0x452e8bc, (q31_t)0xe8e009ba, (q31_t)0x44e5f80, (q31_t)0xe8ebc1d3, + (q31_t)0x449d892, (q31_t)0xe8f77acf, (q31_t)0x44553f2, (q31_t)0xe90334af, + (q31_t)0x440d19e, (q31_t)0xe90eef71, (q31_t)0x43c5199, (q31_t)0xe91aab16, + (q31_t)0x437d3e1, (q31_t)0xe926679c, (q31_t)0x4335877, (q31_t)0xe9322505, + (q31_t)0x42edf5c, (q31_t)0xe93de34e, (q31_t)0x42a688f, (q31_t)0xe949a278, + (q31_t)0x425f410, (q31_t)0xe9556282, (q31_t)0x42181e0, (q31_t)0xe961236c, + (q31_t)0x41d11ff, (q31_t)0xe96ce535, (q31_t)0x418a46d, (q31_t)0xe978a7dd, + (q31_t)0x414392b, (q31_t)0xe9846b63, (q31_t)0x40fd037, (q31_t)0xe9902fc7, + (q31_t)0x40b6994, (q31_t)0xe99bf509, (q31_t)0x4070540, (q31_t)0xe9a7bb28, + (q31_t)0x402a33c, (q31_t)0xe9b38223, (q31_t)0x3fe4388, (q31_t)0xe9bf49fa, + (q31_t)0x3f9e624, (q31_t)0xe9cb12ad, (q31_t)0x3f58b10, (q31_t)0xe9d6dc3b, + (q31_t)0x3f1324e, (q31_t)0xe9e2a6a3, (q31_t)0x3ecdbdc, (q31_t)0xe9ee71e6, + (q31_t)0x3e887bb, (q31_t)0xe9fa3e03, (q31_t)0x3e435ea, (q31_t)0xea060af9, + (q31_t)0x3dfe66c, (q31_t)0xea11d8c8, (q31_t)0x3db993e, (q31_t)0xea1da770, + (q31_t)0x3d74e62, (q31_t)0xea2976ef, (q31_t)0x3d305d8, (q31_t)0xea354746, + (q31_t)0x3cebfa0, (q31_t)0xea411874, (q31_t)0x3ca7bba, (q31_t)0xea4cea79, + (q31_t)0x3c63a26, (q31_t)0xea58bd54, (q31_t)0x3c1fae5, (q31_t)0xea649105, + (q31_t)0x3bdbdf6, (q31_t)0xea70658a, (q31_t)0x3b9835a, (q31_t)0xea7c3ae5, + (q31_t)0x3b54b11, (q31_t)0xea881114, (q31_t)0x3b1151b, (q31_t)0xea93e817, + (q31_t)0x3ace178, (q31_t)0xea9fbfed, (q31_t)0x3a8b028, (q31_t)0xeaab9896, + (q31_t)0x3a4812c, (q31_t)0xeab77212, (q31_t)0x3a05484, (q31_t)0xeac34c60, + (q31_t)0x39c2a2f, (q31_t)0xeacf277f, (q31_t)0x398022f, (q31_t)0xeadb0370, + (q31_t)0x393dc82, (q31_t)0xeae6e031, (q31_t)0x38fb92a, (q31_t)0xeaf2bdc3, + (q31_t)0x38b9827, (q31_t)0xeafe9c24, (q31_t)0x3877978, (q31_t)0xeb0a7b54, + (q31_t)0x3835d1e, (q31_t)0xeb165b54, (q31_t)0x37f4319, (q31_t)0xeb223c22, + (q31_t)0x37b2b6a, (q31_t)0xeb2e1dbe, (q31_t)0x377160f, (q31_t)0xeb3a0027, + (q31_t)0x373030a, (q31_t)0xeb45e35d, (q31_t)0x36ef25b, (q31_t)0xeb51c760, + (q31_t)0x36ae401, (q31_t)0xeb5dac2f, (q31_t)0x366d7fd, (q31_t)0xeb6991ca, + (q31_t)0x362ce50, (q31_t)0xeb75782f, (q31_t)0x35ec6f8, (q31_t)0xeb815f60, + (q31_t)0x35ac1f7, (q31_t)0xeb8d475b, (q31_t)0x356bf4d, (q31_t)0xeb99301f, + (q31_t)0x352bef9, (q31_t)0xeba519ad, (q31_t)0x34ec0fc, (q31_t)0xebb10404, + (q31_t)0x34ac556, (q31_t)0xebbcef23, (q31_t)0x346cc07, (q31_t)0xebc8db0b, + (q31_t)0x342d510, (q31_t)0xebd4c7ba, (q31_t)0x33ee070, (q31_t)0xebe0b52f, + (q31_t)0x33aee27, (q31_t)0xebeca36c, (q31_t)0x336fe37, (q31_t)0xebf8926f, + (q31_t)0x333109e, (q31_t)0xec048237, (q31_t)0x32f255e, (q31_t)0xec1072c4, + (q31_t)0x32b3c75, (q31_t)0xec1c6417, (q31_t)0x32755e5, (q31_t)0xec28562d, + (q31_t)0x32371ae, (q31_t)0xec344908, (q31_t)0x31f8fcf, (q31_t)0xec403ca5, + (q31_t)0x31bb049, (q31_t)0xec4c3106, (q31_t)0x317d31c, (q31_t)0xec582629, + (q31_t)0x313f848, (q31_t)0xec641c0e, (q31_t)0x3101fce, (q31_t)0xec7012b5, + (q31_t)0x30c49ad, (q31_t)0xec7c0a1d, (q31_t)0x30875e5, (q31_t)0xec880245, + (q31_t)0x304a477, (q31_t)0xec93fb2e, (q31_t)0x300d563, (q31_t)0xec9ff4d6, + (q31_t)0x2fd08a9, (q31_t)0xecabef3d, (q31_t)0x2f93e4a, (q31_t)0xecb7ea63, + (q31_t)0x2f57644, (q31_t)0xecc3e648, (q31_t)0x2f1b099, (q31_t)0xeccfe2ea, + (q31_t)0x2eded49, (q31_t)0xecdbe04a, (q31_t)0x2ea2c53, (q31_t)0xece7de66, + (q31_t)0x2e66db8, (q31_t)0xecf3dd3f, (q31_t)0x2e2b178, (q31_t)0xecffdcd4, + (q31_t)0x2def794, (q31_t)0xed0bdd25, (q31_t)0x2db400a, (q31_t)0xed17de31, + (q31_t)0x2d78add, (q31_t)0xed23dff7, (q31_t)0x2d3d80a, (q31_t)0xed2fe277, + (q31_t)0x2d02794, (q31_t)0xed3be5b1, (q31_t)0x2cc7979, (q31_t)0xed47e9a5, + (q31_t)0x2c8cdbb, (q31_t)0xed53ee51, (q31_t)0x2c52459, (q31_t)0xed5ff3b5, + (q31_t)0x2c17d52, (q31_t)0xed6bf9d1, (q31_t)0x2bdd8a9, (q31_t)0xed7800a5, + (q31_t)0x2ba365c, (q31_t)0xed84082f, (q31_t)0x2b6966c, (q31_t)0xed901070, + (q31_t)0x2b2f8d8, (q31_t)0xed9c1967, (q31_t)0x2af5da2, (q31_t)0xeda82313, + (q31_t)0x2abc4c9, (q31_t)0xedb42d74, (q31_t)0x2a82e4d, (q31_t)0xedc0388a, + (q31_t)0x2a49a2e, (q31_t)0xedcc4454, (q31_t)0x2a1086d, (q31_t)0xedd850d2, + (q31_t)0x29d790a, (q31_t)0xede45e03, (q31_t)0x299ec05, (q31_t)0xedf06be6, + (q31_t)0x296615d, (q31_t)0xedfc7a7c, (q31_t)0x292d914, (q31_t)0xee0889c4, + (q31_t)0x28f5329, (q31_t)0xee1499bd, (q31_t)0x28bcf9c, (q31_t)0xee20aa67, + (q31_t)0x2884e6e, (q31_t)0xee2cbbc1, (q31_t)0x284cf9f, (q31_t)0xee38cdcb, + (q31_t)0x281532e, (q31_t)0xee44e084, (q31_t)0x27dd91c, (q31_t)0xee50f3ed, + (q31_t)0x27a616a, (q31_t)0xee5d0804, (q31_t)0x276ec16, (q31_t)0xee691cc9, + (q31_t)0x2737922, (q31_t)0xee75323c, (q31_t)0x270088e, (q31_t)0xee81485c, + (q31_t)0x26c9a58, (q31_t)0xee8d5f29, (q31_t)0x2692e83, (q31_t)0xee9976a1, + (q31_t)0x265c50e, (q31_t)0xeea58ec6, (q31_t)0x2625df8, (q31_t)0xeeb1a796, + (q31_t)0x25ef943, (q31_t)0xeebdc110, (q31_t)0x25b96ee, (q31_t)0xeec9db35, + (q31_t)0x25836f9, (q31_t)0xeed5f604, (q31_t)0x254d965, (q31_t)0xeee2117c, + (q31_t)0x2517e31, (q31_t)0xeeee2d9d, (q31_t)0x24e255e, (q31_t)0xeefa4a67, + (q31_t)0x24aceed, (q31_t)0xef0667d9, (q31_t)0x2477adc, (q31_t)0xef1285f2, + (q31_t)0x244292c, (q31_t)0xef1ea4b2, (q31_t)0x240d9de, (q31_t)0xef2ac419, + (q31_t)0x23d8cf1, (q31_t)0xef36e426, (q31_t)0x23a4265, (q31_t)0xef4304d8, + (q31_t)0x236fa3b, (q31_t)0xef4f2630, (q31_t)0x233b473, (q31_t)0xef5b482d, + (q31_t)0x230710d, (q31_t)0xef676ace, (q31_t)0x22d3009, (q31_t)0xef738e12, + (q31_t)0x229f167, (q31_t)0xef7fb1fa, (q31_t)0x226b528, (q31_t)0xef8bd685, + (q31_t)0x2237b4b, (q31_t)0xef97fbb2, (q31_t)0x22043d0, (q31_t)0xefa42181, + (q31_t)0x21d0eb8, (q31_t)0xefb047f2, (q31_t)0x219dc03, (q31_t)0xefbc6f03, + (q31_t)0x216abb1, (q31_t)0xefc896b5, (q31_t)0x2137dc2, (q31_t)0xefd4bf08, + (q31_t)0x2105236, (q31_t)0xefe0e7f9, (q31_t)0x20d290d, (q31_t)0xefed118a, + (q31_t)0x20a0248, (q31_t)0xeff93bba, (q31_t)0x206dde6, (q31_t)0xf0056687, + (q31_t)0x203bbe8, (q31_t)0xf01191f3, (q31_t)0x2009c4e, (q31_t)0xf01dbdfb, + (q31_t)0x1fd7f17, (q31_t)0xf029eaa1, (q31_t)0x1fa6445, (q31_t)0xf03617e2, + (q31_t)0x1f74bd6, (q31_t)0xf04245c0, (q31_t)0x1f435cc, (q31_t)0xf04e7438, + (q31_t)0x1f12227, (q31_t)0xf05aa34c, (q31_t)0x1ee10e5, (q31_t)0xf066d2fa, + (q31_t)0x1eb0209, (q31_t)0xf0730342, (q31_t)0x1e7f591, (q31_t)0xf07f3424, + (q31_t)0x1e4eb7e, (q31_t)0xf08b659f, (q31_t)0x1e1e3d0, (q31_t)0xf09797b2, + (q31_t)0x1dede87, (q31_t)0xf0a3ca5d, (q31_t)0x1dbdba3, (q31_t)0xf0affda0, + (q31_t)0x1d8db25, (q31_t)0xf0bc317a, (q31_t)0x1d5dd0c, (q31_t)0xf0c865ea, + (q31_t)0x1d2e158, (q31_t)0xf0d49af1, (q31_t)0x1cfe80a, (q31_t)0xf0e0d08d, + (q31_t)0x1ccf122, (q31_t)0xf0ed06bf, (q31_t)0x1c9fca0, (q31_t)0xf0f93d86, + (q31_t)0x1c70a84, (q31_t)0xf10574e0, (q31_t)0x1c41ace, (q31_t)0xf111accf, + (q31_t)0x1c12d7e, (q31_t)0xf11de551, (q31_t)0x1be4294, (q31_t)0xf12a1e66, + (q31_t)0x1bb5a11, (q31_t)0xf136580d, (q31_t)0x1b873f5, (q31_t)0xf1429247, + (q31_t)0x1b5903f, (q31_t)0xf14ecd11, (q31_t)0x1b2aef0, (q31_t)0xf15b086d, + (q31_t)0x1afd007, (q31_t)0xf1674459, (q31_t)0x1acf386, (q31_t)0xf17380d6, + (q31_t)0x1aa196c, (q31_t)0xf17fbde2, (q31_t)0x1a741b9, (q31_t)0xf18bfb7d, + (q31_t)0x1a46c6e, (q31_t)0xf19839a6, (q31_t)0x1a1998a, (q31_t)0xf1a4785e, + (q31_t)0x19ec90d, (q31_t)0xf1b0b7a4, (q31_t)0x19bfaf9, (q31_t)0xf1bcf777, + (q31_t)0x1992f4c, (q31_t)0xf1c937d6, (q31_t)0x1966606, (q31_t)0xf1d578c2, + (q31_t)0x1939f29, (q31_t)0xf1e1ba3a, (q31_t)0x190dab4, (q31_t)0xf1edfc3d, + (q31_t)0x18e18a7, (q31_t)0xf1fa3ecb, (q31_t)0x18b5903, (q31_t)0xf20681e3, + (q31_t)0x1889bc6, (q31_t)0xf212c585, (q31_t)0x185e0f3, (q31_t)0xf21f09b1, + (q31_t)0x1832888, (q31_t)0xf22b4e66, (q31_t)0x1807285, (q31_t)0xf23793a3, + (q31_t)0x17dbeec, (q31_t)0xf243d968, (q31_t)0x17b0dbb, (q31_t)0xf2501fb5, + (q31_t)0x1785ef4, (q31_t)0xf25c6688, (q31_t)0x175b296, (q31_t)0xf268ade3, + (q31_t)0x17308a1, (q31_t)0xf274f5c3, (q31_t)0x1706115, (q31_t)0xf2813e2a, + (q31_t)0x16dbbf3, (q31_t)0xf28d8715, (q31_t)0x16b193a, (q31_t)0xf299d085, + (q31_t)0x16878eb, (q31_t)0xf2a61a7a, (q31_t)0x165db05, (q31_t)0xf2b264f2, + (q31_t)0x1633f8a, (q31_t)0xf2beafed, (q31_t)0x160a678, (q31_t)0xf2cafb6b, + (q31_t)0x15e0fd1, (q31_t)0xf2d7476c, (q31_t)0x15b7b94, (q31_t)0xf2e393ef, + (q31_t)0x158e9c1, (q31_t)0xf2efe0f2, (q31_t)0x1565a58, (q31_t)0xf2fc2e77, + (q31_t)0x153cd5a, (q31_t)0xf3087c7d, (q31_t)0x15142c6, (q31_t)0xf314cb02, + (q31_t)0x14eba9d, (q31_t)0xf3211a07, (q31_t)0x14c34df, (q31_t)0xf32d698a, + (q31_t)0x149b18b, (q31_t)0xf339b98d, (q31_t)0x14730a3, (q31_t)0xf3460a0d, + (q31_t)0x144b225, (q31_t)0xf3525b0b, (q31_t)0x1423613, (q31_t)0xf35eac86, + (q31_t)0x13fbc6c, (q31_t)0xf36afe7e, (q31_t)0x13d4530, (q31_t)0xf37750f2, + (q31_t)0x13ad060, (q31_t)0xf383a3e2, (q31_t)0x1385dfb, (q31_t)0xf38ff74d, + (q31_t)0x135ee02, (q31_t)0xf39c4b32, (q31_t)0x1338075, (q31_t)0xf3a89f92, + (q31_t)0x1311553, (q31_t)0xf3b4f46c, (q31_t)0x12eac9d, (q31_t)0xf3c149bf, + (q31_t)0x12c4653, (q31_t)0xf3cd9f8b, (q31_t)0x129e276, (q31_t)0xf3d9f5cf, + (q31_t)0x1278104, (q31_t)0xf3e64c8c, (q31_t)0x12521ff, (q31_t)0xf3f2a3bf, + (q31_t)0x122c566, (q31_t)0xf3fefb6a, (q31_t)0x1206b39, (q31_t)0xf40b538b, + (q31_t)0x11e1379, (q31_t)0xf417ac22, (q31_t)0x11bbe26, (q31_t)0xf424052f, + (q31_t)0x1196b3f, (q31_t)0xf4305eb0, (q31_t)0x1171ac6, (q31_t)0xf43cb8a7, + (q31_t)0x114ccb9, (q31_t)0xf4491311, (q31_t)0x1128119, (q31_t)0xf4556def, + (q31_t)0x11037e6, (q31_t)0xf461c940, (q31_t)0x10df120, (q31_t)0xf46e2504, + (q31_t)0x10bacc8, (q31_t)0xf47a8139, (q31_t)0x1096add, (q31_t)0xf486dde1, + (q31_t)0x1072b5f, (q31_t)0xf4933afa, (q31_t)0x104ee4f, (q31_t)0xf49f9884, + (q31_t)0x102b3ac, (q31_t)0xf4abf67e, (q31_t)0x1007b77, (q31_t)0xf4b854e7, + (q31_t)0xfe45b0, (q31_t)0xf4c4b3c0, (q31_t)0xfc1257, (q31_t)0xf4d11308, + (q31_t)0xf9e16b, (q31_t)0xf4dd72be, (q31_t)0xf7b2ee, (q31_t)0xf4e9d2e3, + (q31_t)0xf586df, (q31_t)0xf4f63374, (q31_t)0xf35d3e, (q31_t)0xf5029473, + (q31_t)0xf1360b, (q31_t)0xf50ef5de, (q31_t)0xef1147, (q31_t)0xf51b57b5, + (q31_t)0xeceef1, (q31_t)0xf527b9f7, (q31_t)0xeacf09, (q31_t)0xf5341ca5, + (q31_t)0xe8b190, (q31_t)0xf5407fbd, (q31_t)0xe69686, (q31_t)0xf54ce33f, + (q31_t)0xe47deb, (q31_t)0xf559472b, (q31_t)0xe267be, (q31_t)0xf565ab80, + (q31_t)0xe05401, (q31_t)0xf572103d, (q31_t)0xde42b2, (q31_t)0xf57e7563, + (q31_t)0xdc33d2, (q31_t)0xf58adaf0, (q31_t)0xda2762, (q31_t)0xf59740e5, + (q31_t)0xd81d61, (q31_t)0xf5a3a740, (q31_t)0xd615cf, (q31_t)0xf5b00e02, + (q31_t)0xd410ad, (q31_t)0xf5bc7529, (q31_t)0xd20dfa, (q31_t)0xf5c8dcb6, + (q31_t)0xd00db6, (q31_t)0xf5d544a7, (q31_t)0xce0fe3, (q31_t)0xf5e1acfd, + (q31_t)0xcc147f, (q31_t)0xf5ee15b7, (q31_t)0xca1b8a, (q31_t)0xf5fa7ed4, + (q31_t)0xc82506, (q31_t)0xf606e854, (q31_t)0xc630f2, (q31_t)0xf6135237, + (q31_t)0xc43f4d, (q31_t)0xf61fbc7b, (q31_t)0xc25019, (q31_t)0xf62c2721, + (q31_t)0xc06355, (q31_t)0xf6389228, (q31_t)0xbe7901, (q31_t)0xf644fd8f, + (q31_t)0xbc911d, (q31_t)0xf6516956, (q31_t)0xbaabaa, (q31_t)0xf65dd57d, + (q31_t)0xb8c8a7, (q31_t)0xf66a4203, (q31_t)0xb6e815, (q31_t)0xf676aee8, + (q31_t)0xb509f3, (q31_t)0xf6831c2b, (q31_t)0xb32e42, (q31_t)0xf68f89cb, + (q31_t)0xb15502, (q31_t)0xf69bf7c9, (q31_t)0xaf7e33, (q31_t)0xf6a86623, + (q31_t)0xada9d4, (q31_t)0xf6b4d4d9, (q31_t)0xabd7e6, (q31_t)0xf6c143ec, + (q31_t)0xaa086a, (q31_t)0xf6cdb359, (q31_t)0xa83b5e, (q31_t)0xf6da2321, + (q31_t)0xa670c4, (q31_t)0xf6e69344, (q31_t)0xa4a89b, (q31_t)0xf6f303c0, + (q31_t)0xa2e2e3, (q31_t)0xf6ff7496, (q31_t)0xa11f9d, (q31_t)0xf70be5c4, + (q31_t)0x9f5ec8, (q31_t)0xf718574b, (q31_t)0x9da065, (q31_t)0xf724c92a, + (q31_t)0x9be473, (q31_t)0xf7313b60, (q31_t)0x9a2af3, (q31_t)0xf73daded, + (q31_t)0x9873e4, (q31_t)0xf74a20d0, (q31_t)0x96bf48, (q31_t)0xf756940a, + (q31_t)0x950d1d, (q31_t)0xf7630799, (q31_t)0x935d64, (q31_t)0xf76f7b7d, + (q31_t)0x91b01d, (q31_t)0xf77befb5, (q31_t)0x900548, (q31_t)0xf7886442, + (q31_t)0x8e5ce5, (q31_t)0xf794d922, (q31_t)0x8cb6f5, (q31_t)0xf7a14e55, + (q31_t)0x8b1376, (q31_t)0xf7adc3db, (q31_t)0x89726a, (q31_t)0xf7ba39b3, + (q31_t)0x87d3d0, (q31_t)0xf7c6afdc, (q31_t)0x8637a9, (q31_t)0xf7d32657, + (q31_t)0x849df4, (q31_t)0xf7df9d22, (q31_t)0x8306b2, (q31_t)0xf7ec143e, + (q31_t)0x8171e2, (q31_t)0xf7f88ba9, (q31_t)0x7fdf85, (q31_t)0xf8050364, + (q31_t)0x7e4f9b, (q31_t)0xf8117b6d, (q31_t)0x7cc223, (q31_t)0xf81df3c5, + (q31_t)0x7b371e, (q31_t)0xf82a6c6a, (q31_t)0x79ae8c, (q31_t)0xf836e55d, + (q31_t)0x78286e, (q31_t)0xf8435e9d, (q31_t)0x76a4c2, (q31_t)0xf84fd829, + (q31_t)0x752389, (q31_t)0xf85c5201, (q31_t)0x73a4c3, (q31_t)0xf868cc24, + (q31_t)0x722871, (q31_t)0xf8754692, (q31_t)0x70ae92, (q31_t)0xf881c14b, + (q31_t)0x6f3726, (q31_t)0xf88e3c4d, (q31_t)0x6dc22e, (q31_t)0xf89ab799, + (q31_t)0x6c4fa8, (q31_t)0xf8a7332e, (q31_t)0x6adf97, (q31_t)0xf8b3af0c, + (q31_t)0x6971f9, (q31_t)0xf8c02b31, (q31_t)0x6806ce, (q31_t)0xf8cca79e, + (q31_t)0x669e18, (q31_t)0xf8d92452, (q31_t)0x6537d4, (q31_t)0xf8e5a14d, + (q31_t)0x63d405, (q31_t)0xf8f21e8e, (q31_t)0x6272aa, (q31_t)0xf8fe9c15, + (q31_t)0x6113c2, (q31_t)0xf90b19e0, (q31_t)0x5fb74e, (q31_t)0xf91797f0, + (q31_t)0x5e5d4e, (q31_t)0xf9241645, (q31_t)0x5d05c3, (q31_t)0xf93094dd, + (q31_t)0x5bb0ab, (q31_t)0xf93d13b8, (q31_t)0x5a5e07, (q31_t)0xf94992d7, + (q31_t)0x590dd8, (q31_t)0xf9561237, (q31_t)0x57c01d, (q31_t)0xf96291d9, + (q31_t)0x5674d6, (q31_t)0xf96f11bc, (q31_t)0x552c03, (q31_t)0xf97b91e1, + (q31_t)0x53e5a5, (q31_t)0xf9881245, (q31_t)0x52a1bb, (q31_t)0xf99492ea, + (q31_t)0x516045, (q31_t)0xf9a113cd, (q31_t)0x502145, (q31_t)0xf9ad94f0, + (q31_t)0x4ee4b8, (q31_t)0xf9ba1651, (q31_t)0x4daaa1, (q31_t)0xf9c697f0, + (q31_t)0x4c72fe, (q31_t)0xf9d319cc, (q31_t)0x4b3dcf, (q31_t)0xf9df9be6, + (q31_t)0x4a0b16, (q31_t)0xf9ec1e3b, (q31_t)0x48dad1, (q31_t)0xf9f8a0cd, + (q31_t)0x47ad01, (q31_t)0xfa05239a, (q31_t)0x4681a6, (q31_t)0xfa11a6a3, + (q31_t)0x4558c0, (q31_t)0xfa1e29e5, (q31_t)0x44324f, (q31_t)0xfa2aad62, + (q31_t)0x430e53, (q31_t)0xfa373119, (q31_t)0x41eccc, (q31_t)0xfa43b508, + (q31_t)0x40cdba, (q31_t)0xfa503930, (q31_t)0x3fb11d, (q31_t)0xfa5cbd91, + (q31_t)0x3e96f6, (q31_t)0xfa694229, (q31_t)0x3d7f44, (q31_t)0xfa75c6f8, + (q31_t)0x3c6a07, (q31_t)0xfa824bfd, (q31_t)0x3b573f, (q31_t)0xfa8ed139, + (q31_t)0x3a46ed, (q31_t)0xfa9b56ab, (q31_t)0x393910, (q31_t)0xfaa7dc52, + (q31_t)0x382da8, (q31_t)0xfab4622d, (q31_t)0x3724b6, (q31_t)0xfac0e83d, + (q31_t)0x361e3a, (q31_t)0xfacd6e81, (q31_t)0x351a33, (q31_t)0xfad9f4f8, + (q31_t)0x3418a2, (q31_t)0xfae67ba2, (q31_t)0x331986, (q31_t)0xfaf3027e, + (q31_t)0x321ce0, (q31_t)0xfaff898c, (q31_t)0x3122b0, (q31_t)0xfb0c10cb, + (q31_t)0x302af5, (q31_t)0xfb18983b, (q31_t)0x2f35b1, (q31_t)0xfb251fdc, + (q31_t)0x2e42e2, (q31_t)0xfb31a7ac, (q31_t)0x2d5289, (q31_t)0xfb3e2fac, + (q31_t)0x2c64a6, (q31_t)0xfb4ab7db, (q31_t)0x2b7939, (q31_t)0xfb574039, + (q31_t)0x2a9042, (q31_t)0xfb63c8c4, (q31_t)0x29a9c1, (q31_t)0xfb70517d, + (q31_t)0x28c5b6, (q31_t)0xfb7cda63, (q31_t)0x27e421, (q31_t)0xfb896375, + (q31_t)0x270502, (q31_t)0xfb95ecb4, (q31_t)0x262859, (q31_t)0xfba2761e, + (q31_t)0x254e27, (q31_t)0xfbaeffb3, (q31_t)0x24766a, (q31_t)0xfbbb8973, + (q31_t)0x23a124, (q31_t)0xfbc8135c, (q31_t)0x22ce54, (q31_t)0xfbd49d70, + (q31_t)0x21fdfb, (q31_t)0xfbe127ac, (q31_t)0x213018, (q31_t)0xfbedb212, + (q31_t)0x2064ab, (q31_t)0xfbfa3c9f, (q31_t)0x1f9bb5, (q31_t)0xfc06c754, + (q31_t)0x1ed535, (q31_t)0xfc135231, (q31_t)0x1e112b, (q31_t)0xfc1fdd34, + (q31_t)0x1d4f99, (q31_t)0xfc2c685d, (q31_t)0x1c907c, (q31_t)0xfc38f3ac, + (q31_t)0x1bd3d6, (q31_t)0xfc457f21, (q31_t)0x1b19a7, (q31_t)0xfc520aba, + (q31_t)0x1a61ee, (q31_t)0xfc5e9678, (q31_t)0x19acac, (q31_t)0xfc6b2259, + (q31_t)0x18f9e1, (q31_t)0xfc77ae5e, (q31_t)0x18498c, (q31_t)0xfc843a85, + (q31_t)0x179bae, (q31_t)0xfc90c6cf, (q31_t)0x16f047, (q31_t)0xfc9d533b, + (q31_t)0x164757, (q31_t)0xfca9dfc8, (q31_t)0x15a0dd, (q31_t)0xfcb66c77, + (q31_t)0x14fcda, (q31_t)0xfcc2f945, (q31_t)0x145b4e, (q31_t)0xfccf8634, + (q31_t)0x13bc39, (q31_t)0xfcdc1342, (q31_t)0x131f9b, (q31_t)0xfce8a06f, + (q31_t)0x128574, (q31_t)0xfcf52dbb, (q31_t)0x11edc3, (q31_t)0xfd01bb24, + (q31_t)0x11588a, (q31_t)0xfd0e48ab, (q31_t)0x10c5c7, (q31_t)0xfd1ad650, + (q31_t)0x10357c, (q31_t)0xfd276410, (q31_t)0xfa7a8, (q31_t)0xfd33f1ed, + (q31_t)0xf1c4a, (q31_t)0xfd407fe6, (q31_t)0xe9364, (q31_t)0xfd4d0df9, + (q31_t)0xe0cf5, (q31_t)0xfd599c28, (q31_t)0xd88fd, (q31_t)0xfd662a70, + (q31_t)0xd077c, (q31_t)0xfd72b8d2, (q31_t)0xc8872, (q31_t)0xfd7f474d, + (q31_t)0xc0be0, (q31_t)0xfd8bd5e1, (q31_t)0xb91c4, (q31_t)0xfd98648d, + (q31_t)0xb1a20, (q31_t)0xfda4f351, (q31_t)0xaa4f3, (q31_t)0xfdb1822c, + (q31_t)0xa323d, (q31_t)0xfdbe111e, (q31_t)0x9c1ff, (q31_t)0xfdcaa027, + (q31_t)0x95438, (q31_t)0xfdd72f45, (q31_t)0x8e8e8, (q31_t)0xfde3be78, + (q31_t)0x8800f, (q31_t)0xfdf04dc0, (q31_t)0x819ae, (q31_t)0xfdfcdd1d, + (q31_t)0x7b5c4, (q31_t)0xfe096c8d, (q31_t)0x75452, (q31_t)0xfe15fc11, + (q31_t)0x6f556, (q31_t)0xfe228ba7, (q31_t)0x698d3, (q31_t)0xfe2f1b50, + (q31_t)0x63ec6, (q31_t)0xfe3bab0b, (q31_t)0x5e731, (q31_t)0xfe483ad8, + (q31_t)0x59214, (q31_t)0xfe54cab5, (q31_t)0x53f6e, (q31_t)0xfe615aa3, + (q31_t)0x4ef3f, (q31_t)0xfe6deaa1, (q31_t)0x4a188, (q31_t)0xfe7a7aae, + (q31_t)0x45648, (q31_t)0xfe870aca, (q31_t)0x40d80, (q31_t)0xfe939af5, + (q31_t)0x3c72f, (q31_t)0xfea02b2e, (q31_t)0x38356, (q31_t)0xfeacbb74, + (q31_t)0x341f4, (q31_t)0xfeb94bc8, (q31_t)0x3030a, (q31_t)0xfec5dc28, + (q31_t)0x2c697, (q31_t)0xfed26c94, (q31_t)0x28c9c, (q31_t)0xfedefd0c, + (q31_t)0x25519, (q31_t)0xfeeb8d8f, (q31_t)0x2200d, (q31_t)0xfef81e1d, + (q31_t)0x1ed78, (q31_t)0xff04aeb5, (q31_t)0x1bd5c, (q31_t)0xff113f56, + (q31_t)0x18fb6, (q31_t)0xff1dd001, (q31_t)0x16489, (q31_t)0xff2a60b4, + (q31_t)0x13bd3, (q31_t)0xff36f170, (q31_t)0x11594, (q31_t)0xff438234, + (q31_t)0xf1ce, (q31_t)0xff5012fe, (q31_t)0xd07e, (q31_t)0xff5ca3d0, + (q31_t)0xb1a7, (q31_t)0xff6934a8, (q31_t)0x9547, (q31_t)0xff75c585, + (q31_t)0x7b5f, (q31_t)0xff825668, (q31_t)0x63ee, (q31_t)0xff8ee750, + (q31_t)0x4ef5, (q31_t)0xff9b783c, (q31_t)0x3c74, (q31_t)0xffa8092c, + (q31_t)0x2c6a, (q31_t)0xffb49a1f, (q31_t)0x1ed8, (q31_t)0xffc12b16, + (q31_t)0x13bd, (q31_t)0xffcdbc0f, (q31_t)0xb1a, (q31_t)0xffda4d09, + (q31_t)0x4ef, (q31_t)0xffe6de05, (q31_t)0x13c, (q31_t)0xfff36f02, + (q31_t)0x0, (q31_t)0x0, (q31_t)0x13c, (q31_t)0xc90fe, + (q31_t)0x4ef, (q31_t)0x1921fb, (q31_t)0xb1a, (q31_t)0x25b2f7, + (q31_t)0x13bd, (q31_t)0x3243f1, (q31_t)0x1ed8, (q31_t)0x3ed4ea, + (q31_t)0x2c6a, (q31_t)0x4b65e1, (q31_t)0x3c74, (q31_t)0x57f6d4, + (q31_t)0x4ef5, (q31_t)0x6487c4, (q31_t)0x63ee, (q31_t)0x7118b0, + (q31_t)0x7b5f, (q31_t)0x7da998, (q31_t)0x9547, (q31_t)0x8a3a7b, + (q31_t)0xb1a7, (q31_t)0x96cb58, (q31_t)0xd07e, (q31_t)0xa35c30, + (q31_t)0xf1ce, (q31_t)0xafed02, (q31_t)0x11594, (q31_t)0xbc7dcc, + (q31_t)0x13bd3, (q31_t)0xc90e90, (q31_t)0x16489, (q31_t)0xd59f4c, + (q31_t)0x18fb6, (q31_t)0xe22fff, (q31_t)0x1bd5c, (q31_t)0xeec0aa, + (q31_t)0x1ed78, (q31_t)0xfb514b, (q31_t)0x2200d, (q31_t)0x107e1e3, + (q31_t)0x25519, (q31_t)0x1147271, (q31_t)0x28c9c, (q31_t)0x12102f4, + (q31_t)0x2c697, (q31_t)0x12d936c, (q31_t)0x3030a, (q31_t)0x13a23d8, + (q31_t)0x341f4, (q31_t)0x146b438, (q31_t)0x38356, (q31_t)0x153448c, + (q31_t)0x3c72f, (q31_t)0x15fd4d2, (q31_t)0x40d80, (q31_t)0x16c650b, + (q31_t)0x45648, (q31_t)0x178f536, (q31_t)0x4a188, (q31_t)0x1858552, + (q31_t)0x4ef3f, (q31_t)0x192155f, (q31_t)0x53f6e, (q31_t)0x19ea55d, + (q31_t)0x59214, (q31_t)0x1ab354b, (q31_t)0x5e731, (q31_t)0x1b7c528, + (q31_t)0x63ec6, (q31_t)0x1c454f5, (q31_t)0x698d3, (q31_t)0x1d0e4b0, + (q31_t)0x6f556, (q31_t)0x1dd7459, (q31_t)0x75452, (q31_t)0x1ea03ef, + (q31_t)0x7b5c4, (q31_t)0x1f69373, (q31_t)0x819ae, (q31_t)0x20322e3, + (q31_t)0x8800f, (q31_t)0x20fb240, (q31_t)0x8e8e8, (q31_t)0x21c4188, + (q31_t)0x95438, (q31_t)0x228d0bb, (q31_t)0x9c1ff, (q31_t)0x2355fd9, + (q31_t)0xa323d, (q31_t)0x241eee2, (q31_t)0xaa4f3, (q31_t)0x24e7dd4, + (q31_t)0xb1a20, (q31_t)0x25b0caf, (q31_t)0xb91c4, (q31_t)0x2679b73, + (q31_t)0xc0be0, (q31_t)0x2742a1f, (q31_t)0xc8872, (q31_t)0x280b8b3, + (q31_t)0xd077c, (q31_t)0x28d472e, (q31_t)0xd88fd, (q31_t)0x299d590, + (q31_t)0xe0cf5, (q31_t)0x2a663d8, (q31_t)0xe9364, (q31_t)0x2b2f207, + (q31_t)0xf1c4a, (q31_t)0x2bf801a, (q31_t)0xfa7a8, (q31_t)0x2cc0e13, + (q31_t)0x10357c, (q31_t)0x2d89bf0, (q31_t)0x10c5c7, (q31_t)0x2e529b0, + (q31_t)0x11588a, (q31_t)0x2f1b755, (q31_t)0x11edc3, (q31_t)0x2fe44dc, + (q31_t)0x128574, (q31_t)0x30ad245, (q31_t)0x131f9b, (q31_t)0x3175f91, + (q31_t)0x13bc39, (q31_t)0x323ecbe, (q31_t)0x145b4e, (q31_t)0x33079cc, + (q31_t)0x14fcda, (q31_t)0x33d06bb, (q31_t)0x15a0dd, (q31_t)0x3499389, + (q31_t)0x164757, (q31_t)0x3562038, (q31_t)0x16f047, (q31_t)0x362acc5, + (q31_t)0x179bae, (q31_t)0x36f3931, (q31_t)0x18498c, (q31_t)0x37bc57b, + (q31_t)0x18f9e1, (q31_t)0x38851a2, (q31_t)0x19acac, (q31_t)0x394dda7, + (q31_t)0x1a61ee, (q31_t)0x3a16988, (q31_t)0x1b19a7, (q31_t)0x3adf546, + (q31_t)0x1bd3d6, (q31_t)0x3ba80df, (q31_t)0x1c907c, (q31_t)0x3c70c54, + (q31_t)0x1d4f99, (q31_t)0x3d397a3, (q31_t)0x1e112b, (q31_t)0x3e022cc, + (q31_t)0x1ed535, (q31_t)0x3ecadcf, (q31_t)0x1f9bb5, (q31_t)0x3f938ac, + (q31_t)0x2064ab, (q31_t)0x405c361, (q31_t)0x213018, (q31_t)0x4124dee, + (q31_t)0x21fdfb, (q31_t)0x41ed854, (q31_t)0x22ce54, (q31_t)0x42b6290, + (q31_t)0x23a124, (q31_t)0x437eca4, (q31_t)0x24766a, (q31_t)0x444768d, + (q31_t)0x254e27, (q31_t)0x451004d, (q31_t)0x262859, (q31_t)0x45d89e2, + (q31_t)0x270502, (q31_t)0x46a134c, (q31_t)0x27e421, (q31_t)0x4769c8b, + (q31_t)0x28c5b6, (q31_t)0x483259d, (q31_t)0x29a9c1, (q31_t)0x48fae83, + (q31_t)0x2a9042, (q31_t)0x49c373c, (q31_t)0x2b7939, (q31_t)0x4a8bfc7, + (q31_t)0x2c64a6, (q31_t)0x4b54825, (q31_t)0x2d5289, (q31_t)0x4c1d054, + (q31_t)0x2e42e2, (q31_t)0x4ce5854, (q31_t)0x2f35b1, (q31_t)0x4dae024, + (q31_t)0x302af5, (q31_t)0x4e767c5, (q31_t)0x3122b0, (q31_t)0x4f3ef35, + (q31_t)0x321ce0, (q31_t)0x5007674, (q31_t)0x331986, (q31_t)0x50cfd82, + (q31_t)0x3418a2, (q31_t)0x519845e, (q31_t)0x351a33, (q31_t)0x5260b08, + (q31_t)0x361e3a, (q31_t)0x532917f, (q31_t)0x3724b6, (q31_t)0x53f17c3, + (q31_t)0x382da8, (q31_t)0x54b9dd3, (q31_t)0x393910, (q31_t)0x55823ae, + (q31_t)0x3a46ed, (q31_t)0x564a955, (q31_t)0x3b573f, (q31_t)0x5712ec7, + (q31_t)0x3c6a07, (q31_t)0x57db403, (q31_t)0x3d7f44, (q31_t)0x58a3908, + (q31_t)0x3e96f6, (q31_t)0x596bdd7, (q31_t)0x3fb11d, (q31_t)0x5a3426f, + (q31_t)0x40cdba, (q31_t)0x5afc6d0, (q31_t)0x41eccc, (q31_t)0x5bc4af8, + (q31_t)0x430e53, (q31_t)0x5c8cee7, (q31_t)0x44324f, (q31_t)0x5d5529e, + (q31_t)0x4558c0, (q31_t)0x5e1d61b, (q31_t)0x4681a6, (q31_t)0x5ee595d, + (q31_t)0x47ad01, (q31_t)0x5fadc66, (q31_t)0x48dad1, (q31_t)0x6075f33, + (q31_t)0x4a0b16, (q31_t)0x613e1c5, (q31_t)0x4b3dcf, (q31_t)0x620641a, + (q31_t)0x4c72fe, (q31_t)0x62ce634, (q31_t)0x4daaa1, (q31_t)0x6396810, + (q31_t)0x4ee4b8, (q31_t)0x645e9af, (q31_t)0x502145, (q31_t)0x6526b10, + (q31_t)0x516045, (q31_t)0x65eec33, (q31_t)0x52a1bb, (q31_t)0x66b6d16, + (q31_t)0x53e5a5, (q31_t)0x677edbb, (q31_t)0x552c03, (q31_t)0x6846e1f, + (q31_t)0x5674d6, (q31_t)0x690ee44, (q31_t)0x57c01d, (q31_t)0x69d6e27, + (q31_t)0x590dd8, (q31_t)0x6a9edc9, (q31_t)0x5a5e07, (q31_t)0x6b66d29, + (q31_t)0x5bb0ab, (q31_t)0x6c2ec48, (q31_t)0x5d05c3, (q31_t)0x6cf6b23, + (q31_t)0x5e5d4e, (q31_t)0x6dbe9bb, (q31_t)0x5fb74e, (q31_t)0x6e86810, + (q31_t)0x6113c2, (q31_t)0x6f4e620, (q31_t)0x6272aa, (q31_t)0x70163eb, + (q31_t)0x63d405, (q31_t)0x70de172, (q31_t)0x6537d4, (q31_t)0x71a5eb3, + (q31_t)0x669e18, (q31_t)0x726dbae, (q31_t)0x6806ce, (q31_t)0x7335862, + (q31_t)0x6971f9, (q31_t)0x73fd4cf, (q31_t)0x6adf97, (q31_t)0x74c50f4, + (q31_t)0x6c4fa8, (q31_t)0x758ccd2, (q31_t)0x6dc22e, (q31_t)0x7654867, + (q31_t)0x6f3726, (q31_t)0x771c3b3, (q31_t)0x70ae92, (q31_t)0x77e3eb5, + (q31_t)0x722871, (q31_t)0x78ab96e, (q31_t)0x73a4c3, (q31_t)0x79733dc, + (q31_t)0x752389, (q31_t)0x7a3adff, (q31_t)0x76a4c2, (q31_t)0x7b027d7, + (q31_t)0x78286e, (q31_t)0x7bca163, (q31_t)0x79ae8c, (q31_t)0x7c91aa3, + (q31_t)0x7b371e, (q31_t)0x7d59396, (q31_t)0x7cc223, (q31_t)0x7e20c3b, + (q31_t)0x7e4f9b, (q31_t)0x7ee8493, (q31_t)0x7fdf85, (q31_t)0x7fafc9c, + (q31_t)0x8171e2, (q31_t)0x8077457, (q31_t)0x8306b2, (q31_t)0x813ebc2, + (q31_t)0x849df4, (q31_t)0x82062de, (q31_t)0x8637a9, (q31_t)0x82cd9a9, + (q31_t)0x87d3d0, (q31_t)0x8395024, (q31_t)0x89726a, (q31_t)0x845c64d, + (q31_t)0x8b1376, (q31_t)0x8523c25, (q31_t)0x8cb6f5, (q31_t)0x85eb1ab, + (q31_t)0x8e5ce5, (q31_t)0x86b26de, (q31_t)0x900548, (q31_t)0x8779bbe, + (q31_t)0x91b01d, (q31_t)0x884104b, (q31_t)0x935d64, (q31_t)0x8908483, + (q31_t)0x950d1d, (q31_t)0x89cf867, (q31_t)0x96bf48, (q31_t)0x8a96bf6, + (q31_t)0x9873e4, (q31_t)0x8b5df30, (q31_t)0x9a2af3, (q31_t)0x8c25213, + (q31_t)0x9be473, (q31_t)0x8cec4a0, (q31_t)0x9da065, (q31_t)0x8db36d6, + (q31_t)0x9f5ec8, (q31_t)0x8e7a8b5, (q31_t)0xa11f9d, (q31_t)0x8f41a3c, + (q31_t)0xa2e2e3, (q31_t)0x9008b6a, (q31_t)0xa4a89b, (q31_t)0x90cfc40, + (q31_t)0xa670c4, (q31_t)0x9196cbc, (q31_t)0xa83b5e, (q31_t)0x925dcdf, + (q31_t)0xaa086a, (q31_t)0x9324ca7, (q31_t)0xabd7e6, (q31_t)0x93ebc14, + (q31_t)0xada9d4, (q31_t)0x94b2b27, (q31_t)0xaf7e33, (q31_t)0x95799dd, + (q31_t)0xb15502, (q31_t)0x9640837, (q31_t)0xb32e42, (q31_t)0x9707635, + (q31_t)0xb509f3, (q31_t)0x97ce3d5, (q31_t)0xb6e815, (q31_t)0x9895118, + (q31_t)0xb8c8a7, (q31_t)0x995bdfd, (q31_t)0xbaabaa, (q31_t)0x9a22a83, + (q31_t)0xbc911d, (q31_t)0x9ae96aa, (q31_t)0xbe7901, (q31_t)0x9bb0271, + (q31_t)0xc06355, (q31_t)0x9c76dd8, (q31_t)0xc25019, (q31_t)0x9d3d8df, + (q31_t)0xc43f4d, (q31_t)0x9e04385, (q31_t)0xc630f2, (q31_t)0x9ecadc9, + (q31_t)0xc82506, (q31_t)0x9f917ac, (q31_t)0xca1b8a, (q31_t)0xa05812c, + (q31_t)0xcc147f, (q31_t)0xa11ea49, (q31_t)0xce0fe3, (q31_t)0xa1e5303, + (q31_t)0xd00db6, (q31_t)0xa2abb59, (q31_t)0xd20dfa, (q31_t)0xa37234a, + (q31_t)0xd410ad, (q31_t)0xa438ad7, (q31_t)0xd615cf, (q31_t)0xa4ff1fe, + (q31_t)0xd81d61, (q31_t)0xa5c58c0, (q31_t)0xda2762, (q31_t)0xa68bf1b, + (q31_t)0xdc33d2, (q31_t)0xa752510, (q31_t)0xde42b2, (q31_t)0xa818a9d, + (q31_t)0xe05401, (q31_t)0xa8defc3, (q31_t)0xe267be, (q31_t)0xa9a5480, + (q31_t)0xe47deb, (q31_t)0xaa6b8d5, (q31_t)0xe69686, (q31_t)0xab31cc1, + (q31_t)0xe8b190, (q31_t)0xabf8043, (q31_t)0xeacf09, (q31_t)0xacbe35b, + (q31_t)0xeceef1, (q31_t)0xad84609, (q31_t)0xef1147, (q31_t)0xae4a84b, + (q31_t)0xf1360b, (q31_t)0xaf10a22, (q31_t)0xf35d3e, (q31_t)0xafd6b8d, + (q31_t)0xf586df, (q31_t)0xb09cc8c, (q31_t)0xf7b2ee, (q31_t)0xb162d1d, + (q31_t)0xf9e16b, (q31_t)0xb228d42, (q31_t)0xfc1257, (q31_t)0xb2eecf8, + (q31_t)0xfe45b0, (q31_t)0xb3b4c40, (q31_t)0x1007b77, (q31_t)0xb47ab19, + (q31_t)0x102b3ac, (q31_t)0xb540982, (q31_t)0x104ee4f, (q31_t)0xb60677c, + (q31_t)0x1072b5f, (q31_t)0xb6cc506, (q31_t)0x1096add, (q31_t)0xb79221f, + (q31_t)0x10bacc8, (q31_t)0xb857ec7, (q31_t)0x10df120, (q31_t)0xb91dafc, + (q31_t)0x11037e6, (q31_t)0xb9e36c0, (q31_t)0x1128119, (q31_t)0xbaa9211, + (q31_t)0x114ccb9, (q31_t)0xbb6ecef, (q31_t)0x1171ac6, (q31_t)0xbc34759, + (q31_t)0x1196b3f, (q31_t)0xbcfa150, (q31_t)0x11bbe26, (q31_t)0xbdbfad1, + (q31_t)0x11e1379, (q31_t)0xbe853de, (q31_t)0x1206b39, (q31_t)0xbf4ac75, + (q31_t)0x122c566, (q31_t)0xc010496, (q31_t)0x12521ff, (q31_t)0xc0d5c41, + (q31_t)0x1278104, (q31_t)0xc19b374, (q31_t)0x129e276, (q31_t)0xc260a31, + (q31_t)0x12c4653, (q31_t)0xc326075, (q31_t)0x12eac9d, (q31_t)0xc3eb641, + (q31_t)0x1311553, (q31_t)0xc4b0b94, (q31_t)0x1338075, (q31_t)0xc57606e, + (q31_t)0x135ee02, (q31_t)0xc63b4ce, (q31_t)0x1385dfb, (q31_t)0xc7008b3, + (q31_t)0x13ad060, (q31_t)0xc7c5c1e, (q31_t)0x13d4530, (q31_t)0xc88af0e, + (q31_t)0x13fbc6c, (q31_t)0xc950182, (q31_t)0x1423613, (q31_t)0xca1537a, + (q31_t)0x144b225, (q31_t)0xcada4f5, (q31_t)0x14730a3, (q31_t)0xcb9f5f3, + (q31_t)0x149b18b, (q31_t)0xcc64673, (q31_t)0x14c34df, (q31_t)0xcd29676, + (q31_t)0x14eba9d, (q31_t)0xcdee5f9, (q31_t)0x15142c6, (q31_t)0xceb34fe, + (q31_t)0x153cd5a, (q31_t)0xcf78383, (q31_t)0x1565a58, (q31_t)0xd03d189, + (q31_t)0x158e9c1, (q31_t)0xd101f0e, (q31_t)0x15b7b94, (q31_t)0xd1c6c11, + (q31_t)0x15e0fd1, (q31_t)0xd28b894, (q31_t)0x160a678, (q31_t)0xd350495, + (q31_t)0x1633f8a, (q31_t)0xd415013, (q31_t)0x165db05, (q31_t)0xd4d9b0e, + (q31_t)0x16878eb, (q31_t)0xd59e586, (q31_t)0x16b193a, (q31_t)0xd662f7b, + (q31_t)0x16dbbf3, (q31_t)0xd7278eb, (q31_t)0x1706115, (q31_t)0xd7ec1d6, + (q31_t)0x17308a1, (q31_t)0xd8b0a3d, (q31_t)0x175b296, (q31_t)0xd97521d, + (q31_t)0x1785ef4, (q31_t)0xda39978, (q31_t)0x17b0dbb, (q31_t)0xdafe04b, + (q31_t)0x17dbeec, (q31_t)0xdbc2698, (q31_t)0x1807285, (q31_t)0xdc86c5d, + (q31_t)0x1832888, (q31_t)0xdd4b19a, (q31_t)0x185e0f3, (q31_t)0xde0f64f, + (q31_t)0x1889bc6, (q31_t)0xded3a7b, (q31_t)0x18b5903, (q31_t)0xdf97e1d, + (q31_t)0x18e18a7, (q31_t)0xe05c135, (q31_t)0x190dab4, (q31_t)0xe1203c3, + (q31_t)0x1939f29, (q31_t)0xe1e45c6, (q31_t)0x1966606, (q31_t)0xe2a873e, + (q31_t)0x1992f4c, (q31_t)0xe36c82a, (q31_t)0x19bfaf9, (q31_t)0xe430889, + (q31_t)0x19ec90d, (q31_t)0xe4f485c, (q31_t)0x1a1998a, (q31_t)0xe5b87a2, + (q31_t)0x1a46c6e, (q31_t)0xe67c65a, (q31_t)0x1a741b9, (q31_t)0xe740483, + (q31_t)0x1aa196c, (q31_t)0xe80421e, (q31_t)0x1acf386, (q31_t)0xe8c7f2a, + (q31_t)0x1afd007, (q31_t)0xe98bba7, (q31_t)0x1b2aef0, (q31_t)0xea4f793, + (q31_t)0x1b5903f, (q31_t)0xeb132ef, (q31_t)0x1b873f5, (q31_t)0xebd6db9, + (q31_t)0x1bb5a11, (q31_t)0xec9a7f3, (q31_t)0x1be4294, (q31_t)0xed5e19a, + (q31_t)0x1c12d7e, (q31_t)0xee21aaf, (q31_t)0x1c41ace, (q31_t)0xeee5331, + (q31_t)0x1c70a84, (q31_t)0xefa8b20, (q31_t)0x1c9fca0, (q31_t)0xf06c27a, + (q31_t)0x1ccf122, (q31_t)0xf12f941, (q31_t)0x1cfe80a, (q31_t)0xf1f2f73, + (q31_t)0x1d2e158, (q31_t)0xf2b650f, (q31_t)0x1d5dd0c, (q31_t)0xf379a16, + (q31_t)0x1d8db25, (q31_t)0xf43ce86, (q31_t)0x1dbdba3, (q31_t)0xf500260, + (q31_t)0x1dede87, (q31_t)0xf5c35a3, (q31_t)0x1e1e3d0, (q31_t)0xf68684e, + (q31_t)0x1e4eb7e, (q31_t)0xf749a61, (q31_t)0x1e7f591, (q31_t)0xf80cbdc, + (q31_t)0x1eb0209, (q31_t)0xf8cfcbe, (q31_t)0x1ee10e5, (q31_t)0xf992d06, + (q31_t)0x1f12227, (q31_t)0xfa55cb4, (q31_t)0x1f435cc, (q31_t)0xfb18bc8, + (q31_t)0x1f74bd6, (q31_t)0xfbdba40, (q31_t)0x1fa6445, (q31_t)0xfc9e81e, + (q31_t)0x1fd7f17, (q31_t)0xfd6155f, (q31_t)0x2009c4e, (q31_t)0xfe24205, + (q31_t)0x203bbe8, (q31_t)0xfee6e0d, (q31_t)0x206dde6, (q31_t)0xffa9979, + (q31_t)0x20a0248, (q31_t)0x1006c446, (q31_t)0x20d290d, (q31_t)0x1012ee76, + (q31_t)0x2105236, (q31_t)0x101f1807, (q31_t)0x2137dc2, (q31_t)0x102b40f8, + (q31_t)0x216abb1, (q31_t)0x1037694b, (q31_t)0x219dc03, (q31_t)0x104390fd, + (q31_t)0x21d0eb8, (q31_t)0x104fb80e, (q31_t)0x22043d0, (q31_t)0x105bde7f, + (q31_t)0x2237b4b, (q31_t)0x1068044e, (q31_t)0x226b528, (q31_t)0x1074297b, + (q31_t)0x229f167, (q31_t)0x10804e06, (q31_t)0x22d3009, (q31_t)0x108c71ee, + (q31_t)0x230710d, (q31_t)0x10989532, (q31_t)0x233b473, (q31_t)0x10a4b7d3, + (q31_t)0x236fa3b, (q31_t)0x10b0d9d0, (q31_t)0x23a4265, (q31_t)0x10bcfb28, + (q31_t)0x23d8cf1, (q31_t)0x10c91bda, (q31_t)0x240d9de, (q31_t)0x10d53be7, + (q31_t)0x244292c, (q31_t)0x10e15b4e, (q31_t)0x2477adc, (q31_t)0x10ed7a0e, + (q31_t)0x24aceed, (q31_t)0x10f99827, (q31_t)0x24e255e, (q31_t)0x1105b599, + (q31_t)0x2517e31, (q31_t)0x1111d263, (q31_t)0x254d965, (q31_t)0x111dee84, + (q31_t)0x25836f9, (q31_t)0x112a09fc, (q31_t)0x25b96ee, (q31_t)0x113624cb, + (q31_t)0x25ef943, (q31_t)0x11423ef0, (q31_t)0x2625df8, (q31_t)0x114e586a, + (q31_t)0x265c50e, (q31_t)0x115a713a, (q31_t)0x2692e83, (q31_t)0x1166895f, + (q31_t)0x26c9a58, (q31_t)0x1172a0d7, (q31_t)0x270088e, (q31_t)0x117eb7a4, + (q31_t)0x2737922, (q31_t)0x118acdc4, (q31_t)0x276ec16, (q31_t)0x1196e337, + (q31_t)0x27a616a, (q31_t)0x11a2f7fc, (q31_t)0x27dd91c, (q31_t)0x11af0c13, + (q31_t)0x281532e, (q31_t)0x11bb1f7c, (q31_t)0x284cf9f, (q31_t)0x11c73235, + (q31_t)0x2884e6e, (q31_t)0x11d3443f, (q31_t)0x28bcf9c, (q31_t)0x11df5599, + (q31_t)0x28f5329, (q31_t)0x11eb6643, (q31_t)0x292d914, (q31_t)0x11f7763c, + (q31_t)0x296615d, (q31_t)0x12038584, (q31_t)0x299ec05, (q31_t)0x120f941a, + (q31_t)0x29d790a, (q31_t)0x121ba1fd, (q31_t)0x2a1086d, (q31_t)0x1227af2e, + (q31_t)0x2a49a2e, (q31_t)0x1233bbac, (q31_t)0x2a82e4d, (q31_t)0x123fc776, + (q31_t)0x2abc4c9, (q31_t)0x124bd28c, (q31_t)0x2af5da2, (q31_t)0x1257dced, + (q31_t)0x2b2f8d8, (q31_t)0x1263e699, (q31_t)0x2b6966c, (q31_t)0x126fef90, + (q31_t)0x2ba365c, (q31_t)0x127bf7d1, (q31_t)0x2bdd8a9, (q31_t)0x1287ff5b, + (q31_t)0x2c17d52, (q31_t)0x1294062f, (q31_t)0x2c52459, (q31_t)0x12a00c4b, + (q31_t)0x2c8cdbb, (q31_t)0x12ac11af, (q31_t)0x2cc7979, (q31_t)0x12b8165b, + (q31_t)0x2d02794, (q31_t)0x12c41a4f, (q31_t)0x2d3d80a, (q31_t)0x12d01d89, + (q31_t)0x2d78add, (q31_t)0x12dc2009, (q31_t)0x2db400a, (q31_t)0x12e821cf, + (q31_t)0x2def794, (q31_t)0x12f422db, (q31_t)0x2e2b178, (q31_t)0x1300232c, + (q31_t)0x2e66db8, (q31_t)0x130c22c1, (q31_t)0x2ea2c53, (q31_t)0x1318219a, + (q31_t)0x2eded49, (q31_t)0x13241fb6, (q31_t)0x2f1b099, (q31_t)0x13301d16, + (q31_t)0x2f57644, (q31_t)0x133c19b8, (q31_t)0x2f93e4a, (q31_t)0x1348159d, + (q31_t)0x2fd08a9, (q31_t)0x135410c3, (q31_t)0x300d563, (q31_t)0x13600b2a, + (q31_t)0x304a477, (q31_t)0x136c04d2, (q31_t)0x30875e5, (q31_t)0x1377fdbb, + (q31_t)0x30c49ad, (q31_t)0x1383f5e3, (q31_t)0x3101fce, (q31_t)0x138fed4b, + (q31_t)0x313f848, (q31_t)0x139be3f2, (q31_t)0x317d31c, (q31_t)0x13a7d9d7, + (q31_t)0x31bb049, (q31_t)0x13b3cefa, (q31_t)0x31f8fcf, (q31_t)0x13bfc35b, + (q31_t)0x32371ae, (q31_t)0x13cbb6f8, (q31_t)0x32755e5, (q31_t)0x13d7a9d3, + (q31_t)0x32b3c75, (q31_t)0x13e39be9, (q31_t)0x32f255e, (q31_t)0x13ef8d3c, + (q31_t)0x333109e, (q31_t)0x13fb7dc9, (q31_t)0x336fe37, (q31_t)0x14076d91, + (q31_t)0x33aee27, (q31_t)0x14135c94, (q31_t)0x33ee070, (q31_t)0x141f4ad1, + (q31_t)0x342d510, (q31_t)0x142b3846, (q31_t)0x346cc07, (q31_t)0x143724f5, + (q31_t)0x34ac556, (q31_t)0x144310dd, (q31_t)0x34ec0fc, (q31_t)0x144efbfc, + (q31_t)0x352bef9, (q31_t)0x145ae653, (q31_t)0x356bf4d, (q31_t)0x1466cfe1, + (q31_t)0x35ac1f7, (q31_t)0x1472b8a5, (q31_t)0x35ec6f8, (q31_t)0x147ea0a0, + (q31_t)0x362ce50, (q31_t)0x148a87d1, (q31_t)0x366d7fd, (q31_t)0x14966e36, + (q31_t)0x36ae401, (q31_t)0x14a253d1, (q31_t)0x36ef25b, (q31_t)0x14ae38a0, + (q31_t)0x373030a, (q31_t)0x14ba1ca3, (q31_t)0x377160f, (q31_t)0x14c5ffd9, + (q31_t)0x37b2b6a, (q31_t)0x14d1e242, (q31_t)0x37f4319, (q31_t)0x14ddc3de, + (q31_t)0x3835d1e, (q31_t)0x14e9a4ac, (q31_t)0x3877978, (q31_t)0x14f584ac, + (q31_t)0x38b9827, (q31_t)0x150163dc, (q31_t)0x38fb92a, (q31_t)0x150d423d, + (q31_t)0x393dc82, (q31_t)0x15191fcf, (q31_t)0x398022f, (q31_t)0x1524fc90, + (q31_t)0x39c2a2f, (q31_t)0x1530d881, (q31_t)0x3a05484, (q31_t)0x153cb3a0, + (q31_t)0x3a4812c, (q31_t)0x15488dee, (q31_t)0x3a8b028, (q31_t)0x1554676a, + (q31_t)0x3ace178, (q31_t)0x15604013, (q31_t)0x3b1151b, (q31_t)0x156c17e9, + (q31_t)0x3b54b11, (q31_t)0x1577eeec, (q31_t)0x3b9835a, (q31_t)0x1583c51b, + (q31_t)0x3bdbdf6, (q31_t)0x158f9a76, (q31_t)0x3c1fae5, (q31_t)0x159b6efb, + (q31_t)0x3c63a26, (q31_t)0x15a742ac, (q31_t)0x3ca7bba, (q31_t)0x15b31587, + (q31_t)0x3cebfa0, (q31_t)0x15bee78c, (q31_t)0x3d305d8, (q31_t)0x15cab8ba, + (q31_t)0x3d74e62, (q31_t)0x15d68911, (q31_t)0x3db993e, (q31_t)0x15e25890, + (q31_t)0x3dfe66c, (q31_t)0x15ee2738, (q31_t)0x3e435ea, (q31_t)0x15f9f507, + (q31_t)0x3e887bb, (q31_t)0x1605c1fd, (q31_t)0x3ecdbdc, (q31_t)0x16118e1a, + (q31_t)0x3f1324e, (q31_t)0x161d595d, (q31_t)0x3f58b10, (q31_t)0x162923c5, + (q31_t)0x3f9e624, (q31_t)0x1634ed53, (q31_t)0x3fe4388, (q31_t)0x1640b606, + (q31_t)0x402a33c, (q31_t)0x164c7ddd, (q31_t)0x4070540, (q31_t)0x165844d8, + (q31_t)0x40b6994, (q31_t)0x16640af7, (q31_t)0x40fd037, (q31_t)0x166fd039, + (q31_t)0x414392b, (q31_t)0x167b949d, (q31_t)0x418a46d, (q31_t)0x16875823, + (q31_t)0x41d11ff, (q31_t)0x16931acb, (q31_t)0x42181e0, (q31_t)0x169edc94, + (q31_t)0x425f410, (q31_t)0x16aa9d7e, (q31_t)0x42a688f, (q31_t)0x16b65d88, + (q31_t)0x42edf5c, (q31_t)0x16c21cb2, (q31_t)0x4335877, (q31_t)0x16cddafb, + (q31_t)0x437d3e1, (q31_t)0x16d99864, (q31_t)0x43c5199, (q31_t)0x16e554ea, + (q31_t)0x440d19e, (q31_t)0x16f1108f, (q31_t)0x44553f2, (q31_t)0x16fccb51, + (q31_t)0x449d892, (q31_t)0x17088531, (q31_t)0x44e5f80, (q31_t)0x17143e2d, + (q31_t)0x452e8bc, (q31_t)0x171ff646, (q31_t)0x4577444, (q31_t)0x172bad7a, + (q31_t)0x45c0219, (q31_t)0x173763c9, (q31_t)0x460923b, (q31_t)0x17431933, + (q31_t)0x46524a9, (q31_t)0x174ecdb8, (q31_t)0x469b963, (q31_t)0x175a8157, + (q31_t)0x46e5069, (q31_t)0x1766340f, (q31_t)0x472e9bc, (q31_t)0x1771e5e0, + (q31_t)0x477855a, (q31_t)0x177d96ca, (q31_t)0x47c2344, (q31_t)0x178946cc, + (q31_t)0x480c379, (q31_t)0x1794f5e6, (q31_t)0x48565f9, (q31_t)0x17a0a417, + (q31_t)0x48a0ac4, (q31_t)0x17ac515f, (q31_t)0x48eb1db, (q31_t)0x17b7fdbd, + (q31_t)0x4935b3c, (q31_t)0x17c3a931, (q31_t)0x49806e7, (q31_t)0x17cf53bb, + (q31_t)0x49cb4dd, (q31_t)0x17dafd59, (q31_t)0x4a1651c, (q31_t)0x17e6a60c, + (q31_t)0x4a617a6, (q31_t)0x17f24dd3, (q31_t)0x4aacc7a, (q31_t)0x17fdf4ae, + (q31_t)0x4af8397, (q31_t)0x18099a9c, (q31_t)0x4b43cfd, (q31_t)0x18153f9d, + (q31_t)0x4b8f8ad, (q31_t)0x1820e3b0, (q31_t)0x4bdb6a6, (q31_t)0x182c86d5, + (q31_t)0x4c276e8, (q31_t)0x1838290c, (q31_t)0x4c73972, (q31_t)0x1843ca53, + (q31_t)0x4cbfe45, (q31_t)0x184f6aab, (q31_t)0x4d0c560, (q31_t)0x185b0a13, + (q31_t)0x4d58ec3, (q31_t)0x1866a88a, (q31_t)0x4da5a6f, (q31_t)0x18724611, + (q31_t)0x4df2862, (q31_t)0x187de2a7, (q31_t)0x4e3f89c, (q31_t)0x18897e4a, + (q31_t)0x4e8cb1e, (q31_t)0x189518fc, (q31_t)0x4ed9fe7, (q31_t)0x18a0b2bb, + (q31_t)0x4f276f7, (q31_t)0x18ac4b87, (q31_t)0x4f7504e, (q31_t)0x18b7e35f, + (q31_t)0x4fc2bec, (q31_t)0x18c37a44, (q31_t)0x50109d0, (q31_t)0x18cf1034, + (q31_t)0x505e9fb, (q31_t)0x18daa52f, (q31_t)0x50acc6b, (q31_t)0x18e63935, + (q31_t)0x50fb121, (q31_t)0x18f1cc45, (q31_t)0x514981d, (q31_t)0x18fd5e5f, + (q31_t)0x519815f, (q31_t)0x1908ef82, (q31_t)0x51e6ce6, (q31_t)0x19147fae, + (q31_t)0x5235ab2, (q31_t)0x19200ee3, (q31_t)0x5284ac3, (q31_t)0x192b9d1f, + (q31_t)0x52d3d18, (q31_t)0x19372a64, (q31_t)0x53231b3, (q31_t)0x1942b6af, + (q31_t)0x5372891, (q31_t)0x194e4201, (q31_t)0x53c21b4, (q31_t)0x1959cc5a, + (q31_t)0x5411d1b, (q31_t)0x196555b8, (q31_t)0x5461ac6, (q31_t)0x1970de1b, + (q31_t)0x54b1ab4, (q31_t)0x197c6584, (q31_t)0x5501ce5, (q31_t)0x1987ebf0, + (q31_t)0x555215a, (q31_t)0x19937161, (q31_t)0x55a2812, (q31_t)0x199ef5d6, + (q31_t)0x55f310d, (q31_t)0x19aa794d, (q31_t)0x5643c4a, (q31_t)0x19b5fbc8, + (q31_t)0x56949ca, (q31_t)0x19c17d44, (q31_t)0x56e598c, (q31_t)0x19ccfdc2, + (q31_t)0x5736b90, (q31_t)0x19d87d42, (q31_t)0x5787fd6, (q31_t)0x19e3fbc3, + (q31_t)0x57d965d, (q31_t)0x19ef7944, (q31_t)0x582af26, (q31_t)0x19faf5c5, + (q31_t)0x587ca31, (q31_t)0x1a067145, (q31_t)0x58ce77c, (q31_t)0x1a11ebc5, + (q31_t)0x5920708, (q31_t)0x1a1d6544, (q31_t)0x59728d5, (q31_t)0x1a28ddc0, + (q31_t)0x59c4ce3, (q31_t)0x1a34553b, (q31_t)0x5a17330, (q31_t)0x1a3fcbb3, + (q31_t)0x5a69bbe, (q31_t)0x1a4b4128, (q31_t)0x5abc68c, (q31_t)0x1a56b599, + (q31_t)0x5b0f399, (q31_t)0x1a622907, (q31_t)0x5b622e6, (q31_t)0x1a6d9b70, + (q31_t)0x5bb5472, (q31_t)0x1a790cd4, (q31_t)0x5c0883d, (q31_t)0x1a847d33, + (q31_t)0x5c5be47, (q31_t)0x1a8fec8c, (q31_t)0x5caf690, (q31_t)0x1a9b5adf, + (q31_t)0x5d03118, (q31_t)0x1aa6c82b, (q31_t)0x5d56ddd, (q31_t)0x1ab23471, + (q31_t)0x5daace1, (q31_t)0x1abd9faf, (q31_t)0x5dfee22, (q31_t)0x1ac909e5, + (q31_t)0x5e531a1, (q31_t)0x1ad47312, (q31_t)0x5ea775e, (q31_t)0x1adfdb37, + (q31_t)0x5efbf58, (q31_t)0x1aeb4253, (q31_t)0x5f5098f, (q31_t)0x1af6a865, + (q31_t)0x5fa5603, (q31_t)0x1b020d6c, (q31_t)0x5ffa4b3, (q31_t)0x1b0d716a, + (q31_t)0x604f5a0, (q31_t)0x1b18d45c, (q31_t)0x60a48c9, (q31_t)0x1b243643, + (q31_t)0x60f9e2e, (q31_t)0x1b2f971e, (q31_t)0x614f5cf, (q31_t)0x1b3af6ec, + (q31_t)0x61a4fac, (q31_t)0x1b4655ae, (q31_t)0x61fabc4, (q31_t)0x1b51b363, + (q31_t)0x6250a18, (q31_t)0x1b5d100a, (q31_t)0x62a6aa6, (q31_t)0x1b686ba3, + (q31_t)0x62fcd6f, (q31_t)0x1b73c62d, (q31_t)0x6353273, (q31_t)0x1b7f1fa9, + (q31_t)0x63a99b1, (q31_t)0x1b8a7815, (q31_t)0x6400329, (q31_t)0x1b95cf71, + (q31_t)0x6456edb, (q31_t)0x1ba125bd, (q31_t)0x64adcc7, (q31_t)0x1bac7af9, + (q31_t)0x6504ced, (q31_t)0x1bb7cf23, (q31_t)0x655bf4c, (q31_t)0x1bc3223c, + (q31_t)0x65b33e4, (q31_t)0x1bce7442, (q31_t)0x660aab5, (q31_t)0x1bd9c537, + (q31_t)0x66623be, (q31_t)0x1be51518, (q31_t)0x66b9f01, (q31_t)0x1bf063e6, + (q31_t)0x6711c7b, (q31_t)0x1bfbb1a0, (q31_t)0x6769c2e, (q31_t)0x1c06fe46, + (q31_t)0x67c1e18, (q31_t)0x1c1249d8, (q31_t)0x681a23a, (q31_t)0x1c1d9454, + (q31_t)0x6872894, (q31_t)0x1c28ddbb, (q31_t)0x68cb124, (q31_t)0x1c34260c, + (q31_t)0x6923bec, (q31_t)0x1c3f6d47, (q31_t)0x697c8eb, (q31_t)0x1c4ab36b, + (q31_t)0x69d5820, (q31_t)0x1c55f878, (q31_t)0x6a2e98b, (q31_t)0x1c613c6d, + (q31_t)0x6a87d2d, (q31_t)0x1c6c7f4a, (q31_t)0x6ae1304, (q31_t)0x1c77c10e, + (q31_t)0x6b3ab12, (q31_t)0x1c8301b9, (q31_t)0x6b94554, (q31_t)0x1c8e414b, + (q31_t)0x6bee1cd, (q31_t)0x1c997fc4, (q31_t)0x6c4807a, (q31_t)0x1ca4bd21, + (q31_t)0x6ca215c, (q31_t)0x1caff965, (q31_t)0x6cfc472, (q31_t)0x1cbb348d, + (q31_t)0x6d569be, (q31_t)0x1cc66e99, (q31_t)0x6db113d, (q31_t)0x1cd1a78a, + (q31_t)0x6e0baf0, (q31_t)0x1cdcdf5e, (q31_t)0x6e666d7, (q31_t)0x1ce81615, + (q31_t)0x6ec14f2, (q31_t)0x1cf34baf, (q31_t)0x6f1c540, (q31_t)0x1cfe802b, + (q31_t)0x6f777c1, (q31_t)0x1d09b389, (q31_t)0x6fd2c75, (q31_t)0x1d14e5c9, + (q31_t)0x702e35c, (q31_t)0x1d2016e9, (q31_t)0x7089c75, (q31_t)0x1d2b46ea, + (q31_t)0x70e57c0, (q31_t)0x1d3675cb, (q31_t)0x714153e, (q31_t)0x1d41a38c, + (q31_t)0x719d4ed, (q31_t)0x1d4cd02c, (q31_t)0x71f96ce, (q31_t)0x1d57fbaa, + (q31_t)0x7255ae0, (q31_t)0x1d632608, (q31_t)0x72b2123, (q31_t)0x1d6e4f43, + (q31_t)0x730e997, (q31_t)0x1d79775c, (q31_t)0x736b43c, (q31_t)0x1d849e51, + (q31_t)0x73c8111, (q31_t)0x1d8fc424, (q31_t)0x7425016, (q31_t)0x1d9ae8d2, + (q31_t)0x748214c, (q31_t)0x1da60c5d, (q31_t)0x74df4b1, (q31_t)0x1db12ec3, + (q31_t)0x753ca46, (q31_t)0x1dbc5004, (q31_t)0x759a20a, (q31_t)0x1dc7701f, + (q31_t)0x75f7bfe, (q31_t)0x1dd28f15, (q31_t)0x7655820, (q31_t)0x1dddace4, + (q31_t)0x76b3671, (q31_t)0x1de8c98c, (q31_t)0x77116f0, (q31_t)0x1df3e50d, + (q31_t)0x776f99d, (q31_t)0x1dfeff67, (q31_t)0x77cde79, (q31_t)0x1e0a1898, + (q31_t)0x782c582, (q31_t)0x1e1530a1, (q31_t)0x788aeb9, (q31_t)0x1e204781, + (q31_t)0x78e9a1d, (q31_t)0x1e2b5d38, (q31_t)0x79487ae, (q31_t)0x1e3671c5, + (q31_t)0x79a776c, (q31_t)0x1e418528, (q31_t)0x7a06957, (q31_t)0x1e4c9760, + (q31_t)0x7a65d6e, (q31_t)0x1e57a86d, (q31_t)0x7ac53b1, (q31_t)0x1e62b84f, + (q31_t)0x7b24c20, (q31_t)0x1e6dc705, (q31_t)0x7b846ba, (q31_t)0x1e78d48e, + (q31_t)0x7be4381, (q31_t)0x1e83e0eb, (q31_t)0x7c44272, (q31_t)0x1e8eec1b, + (q31_t)0x7ca438f, (q31_t)0x1e99f61d, (q31_t)0x7d046d6, (q31_t)0x1ea4fef0, + (q31_t)0x7d64c47, (q31_t)0x1eb00696, (q31_t)0x7dc53e3, (q31_t)0x1ebb0d0d, + (q31_t)0x7e25daa, (q31_t)0x1ec61254, (q31_t)0x7e8699a, (q31_t)0x1ed1166b, + (q31_t)0x7ee77b3, (q31_t)0x1edc1953, (q31_t)0x7f487f6, (q31_t)0x1ee71b0a, + (q31_t)0x7fa9a62, (q31_t)0x1ef21b90, (q31_t)0x800aef7, (q31_t)0x1efd1ae4, + (q31_t)0x806c5b5, (q31_t)0x1f081907, (q31_t)0x80cde9b, (q31_t)0x1f1315f7, + (q31_t)0x812f9a9, (q31_t)0x1f1e11b5, (q31_t)0x81916df, (q31_t)0x1f290c3f, + (q31_t)0x81f363d, (q31_t)0x1f340596, (q31_t)0x82557c3, (q31_t)0x1f3efdb9, + (q31_t)0x82b7b70, (q31_t)0x1f49f4a8, (q31_t)0x831a143, (q31_t)0x1f54ea62, + (q31_t)0x837c93e, (q31_t)0x1f5fdee6, (q31_t)0x83df35f, (q31_t)0x1f6ad235, + (q31_t)0x8441fa6, (q31_t)0x1f75c44e, (q31_t)0x84a4e14, (q31_t)0x1f80b531, + (q31_t)0x8507ea7, (q31_t)0x1f8ba4dc, (q31_t)0x856b160, (q31_t)0x1f969350, + (q31_t)0x85ce63e, (q31_t)0x1fa1808c, (q31_t)0x8631d42, (q31_t)0x1fac6c91, + (q31_t)0x869566a, (q31_t)0x1fb7575c, (q31_t)0x86f91b7, (q31_t)0x1fc240ef, + (q31_t)0x875cf28, (q31_t)0x1fcd2948, (q31_t)0x87c0ebd, (q31_t)0x1fd81067, + (q31_t)0x8825077, (q31_t)0x1fe2f64c, (q31_t)0x8889454, (q31_t)0x1feddaf6, + (q31_t)0x88eda54, (q31_t)0x1ff8be65, (q31_t)0x8952278, (q31_t)0x2003a099, + (q31_t)0x89b6cbf, (q31_t)0x200e8190, (q31_t)0x8a1b928, (q31_t)0x2019614c, + (q31_t)0x8a807b4, (q31_t)0x20243fca, (q31_t)0x8ae5862, (q31_t)0x202f1d0b, + (q31_t)0x8b4ab32, (q31_t)0x2039f90f, (q31_t)0x8bb0023, (q31_t)0x2044d3d4, + (q31_t)0x8c15736, (q31_t)0x204fad5b, (q31_t)0x8c7b06b, (q31_t)0x205a85a3, + (q31_t)0x8ce0bc0, (q31_t)0x20655cac, (q31_t)0x8d46936, (q31_t)0x20703275, + (q31_t)0x8dac8cd, (q31_t)0x207b06fe, (q31_t)0x8e12a84, (q31_t)0x2085da46, + (q31_t)0x8e78e5b, (q31_t)0x2090ac4d, (q31_t)0x8edf452, (q31_t)0x209b7d13, + (q31_t)0x8f45c68, (q31_t)0x20a64c97, (q31_t)0x8fac69e, (q31_t)0x20b11ad9, + (q31_t)0x90132f2, (q31_t)0x20bbe7d8, (q31_t)0x907a166, (q31_t)0x20c6b395, + (q31_t)0x90e11f7, (q31_t)0x20d17e0d, (q31_t)0x91484a8, (q31_t)0x20dc4742, + (q31_t)0x91af976, (q31_t)0x20e70f32, (q31_t)0x9217062, (q31_t)0x20f1d5de, + (q31_t)0x927e96b, (q31_t)0x20fc9b44, (q31_t)0x92e6492, (q31_t)0x21075f65, + (q31_t)0x934e1d6, (q31_t)0x21122240, (q31_t)0x93b6137, (q31_t)0x211ce3d5, + (q31_t)0x941e2b4, (q31_t)0x2127a423, (q31_t)0x948664d, (q31_t)0x21326329, + (q31_t)0x94eec03, (q31_t)0x213d20e8, (q31_t)0x95573d4, (q31_t)0x2147dd5f, + (q31_t)0x95bfdc1, (q31_t)0x2152988d, (q31_t)0x96289c9, (q31_t)0x215d5273, + (q31_t)0x96917ec, (q31_t)0x21680b0f, (q31_t)0x96fa82a, (q31_t)0x2172c262, + (q31_t)0x9763a83, (q31_t)0x217d786a, (q31_t)0x97ccef5, (q31_t)0x21882d28, + (q31_t)0x9836582, (q31_t)0x2192e09b, (q31_t)0x989fe29, (q31_t)0x219d92c2, + (q31_t)0x99098e9, (q31_t)0x21a8439e, (q31_t)0x99735c2, (q31_t)0x21b2f32e, + (q31_t)0x99dd4b4, (q31_t)0x21bda171, (q31_t)0x9a475bf, (q31_t)0x21c84e67, + (q31_t)0x9ab18e3, (q31_t)0x21d2fa0f, (q31_t)0x9b1be1e, (q31_t)0x21dda46a, + (q31_t)0x9b86572, (q31_t)0x21e84d76, (q31_t)0x9bf0edd, (q31_t)0x21f2f534, + (q31_t)0x9c5ba60, (q31_t)0x21fd9ba3, (q31_t)0x9cc67fa, (q31_t)0x220840c2, + (q31_t)0x9d317ab, (q31_t)0x2212e492, (q31_t)0x9d9c973, (q31_t)0x221d8711, + (q31_t)0x9e07d51, (q31_t)0x2228283f, (q31_t)0x9e73346, (q31_t)0x2232c81c, + (q31_t)0x9edeb50, (q31_t)0x223d66a8, (q31_t)0x9f4a570, (q31_t)0x224803e2, + (q31_t)0x9fb61a5, (q31_t)0x22529fca, (q31_t)0xa021fef, (q31_t)0x225d3a5e, + (q31_t)0xa08e04f, (q31_t)0x2267d3a0, (q31_t)0xa0fa2c3, (q31_t)0x22726b8e, + (q31_t)0xa16674b, (q31_t)0x227d0228, (q31_t)0xa1d2de7, (q31_t)0x2287976e, + (q31_t)0xa23f698, (q31_t)0x22922b5e, (q31_t)0xa2ac15b, (q31_t)0x229cbdfa, + (q31_t)0xa318e32, (q31_t)0x22a74f40, (q31_t)0xa385d1d, (q31_t)0x22b1df30, + (q31_t)0xa3f2e19, (q31_t)0x22bc6dca, (q31_t)0xa460129, (q31_t)0x22c6fb0c, + (q31_t)0xa4cd64b, (q31_t)0x22d186f8, (q31_t)0xa53ad7e, (q31_t)0x22dc118c, + (q31_t)0xa5a86c4, (q31_t)0x22e69ac8, (q31_t)0xa61621b, (q31_t)0x22f122ab, + (q31_t)0xa683f83, (q31_t)0x22fba936, (q31_t)0xa6f1efc, (q31_t)0x23062e67, + (q31_t)0xa760086, (q31_t)0x2310b23e, (q31_t)0xa7ce420, (q31_t)0x231b34bc, + (q31_t)0xa83c9ca, (q31_t)0x2325b5df, (q31_t)0xa8ab184, (q31_t)0x233035a7, + (q31_t)0xa919b4e, (q31_t)0x233ab414, (q31_t)0xa988727, (q31_t)0x23453125, + (q31_t)0xa9f750f, (q31_t)0x234facda, (q31_t)0xaa66506, (q31_t)0x235a2733, + (q31_t)0xaad570c, (q31_t)0x2364a02e, (q31_t)0xab44b1f, (q31_t)0x236f17cc, + (q31_t)0xabb4141, (q31_t)0x23798e0d, (q31_t)0xac23971, (q31_t)0x238402ef, + (q31_t)0xac933ae, (q31_t)0x238e7673, (q31_t)0xad02ff8, (q31_t)0x2398e898, + (q31_t)0xad72e4f, (q31_t)0x23a3595e, (q31_t)0xade2eb3, (q31_t)0x23adc8c4, + (q31_t)0xae53123, (q31_t)0x23b836ca, (q31_t)0xaec35a0, (q31_t)0x23c2a36f, + (q31_t)0xaf33c28, (q31_t)0x23cd0eb3, (q31_t)0xafa44bc, (q31_t)0x23d77896, + (q31_t)0xb014f5b, (q31_t)0x23e1e117, (q31_t)0xb085c05, (q31_t)0x23ec4837, + (q31_t)0xb0f6aba, (q31_t)0x23f6adf3, (q31_t)0xb167b79, (q31_t)0x2401124d, + (q31_t)0xb1d8e43, (q31_t)0x240b7543, (q31_t)0xb24a316, (q31_t)0x2415d6d5, + (q31_t)0xb2bb9f4, (q31_t)0x24203704, (q31_t)0xb32d2da, (q31_t)0x242a95ce, + (q31_t)0xb39edca, (q31_t)0x2434f332, (q31_t)0xb410ac3, (q31_t)0x243f4f32, + (q31_t)0xb4829c4, (q31_t)0x2449a9cc, (q31_t)0xb4f4acd, (q31_t)0x245402ff, + (q31_t)0xb566ddf, (q31_t)0x245e5acc, (q31_t)0xb5d92f8, (q31_t)0x2468b132, + (q31_t)0xb64ba19, (q31_t)0x24730631, (q31_t)0xb6be341, (q31_t)0x247d59c8, + (q31_t)0xb730e70, (q31_t)0x2487abf7, (q31_t)0xb7a3ba5, (q31_t)0x2491fcbe, + (q31_t)0xb816ae1, (q31_t)0x249c4c1b, (q31_t)0xb889c23, (q31_t)0x24a69a0f, + (q31_t)0xb8fcf6b, (q31_t)0x24b0e699, (q31_t)0xb9704b9, (q31_t)0x24bb31ba, + (q31_t)0xb9e3c0b, (q31_t)0x24c57b6f, (q31_t)0xba57563, (q31_t)0x24cfc3ba, + (q31_t)0xbacb0bf, (q31_t)0x24da0a9a, (q31_t)0xbb3ee20, (q31_t)0x24e4500e, + (q31_t)0xbbb2d85, (q31_t)0x24ee9415, (q31_t)0xbc26eee, (q31_t)0x24f8d6b0, + (q31_t)0xbc9b25a, (q31_t)0x250317df, (q31_t)0xbd0f7ca, (q31_t)0x250d57a0, + (q31_t)0xbd83f3d, (q31_t)0x251795f3, (q31_t)0xbdf88b3, (q31_t)0x2521d2d8, + (q31_t)0xbe6d42b, (q31_t)0x252c0e4f, (q31_t)0xbee21a5, (q31_t)0x25364857, + (q31_t)0xbf57121, (q31_t)0x254080ef, (q31_t)0xbfcc29f, (q31_t)0x254ab818, + (q31_t)0xc04161e, (q31_t)0x2554edd1, (q31_t)0xc0b6b9e, (q31_t)0x255f2219, + (q31_t)0xc12c31f, (q31_t)0x256954f1, (q31_t)0xc1a1ca0, (q31_t)0x25738657, + (q31_t)0xc217822, (q31_t)0x257db64c, (q31_t)0xc28d5a3, (q31_t)0x2587e4cf, + (q31_t)0xc303524, (q31_t)0x259211df, (q31_t)0xc3796a5, (q31_t)0x259c3d7c, + (q31_t)0xc3efa25, (q31_t)0x25a667a7, (q31_t)0xc465fa3, (q31_t)0x25b0905d, + (q31_t)0xc4dc720, (q31_t)0x25bab7a0, (q31_t)0xc55309b, (q31_t)0x25c4dd6e, + (q31_t)0xc5c9c14, (q31_t)0x25cf01c8, (q31_t)0xc64098b, (q31_t)0x25d924ac, + (q31_t)0xc6b78ff, (q31_t)0x25e3461b, (q31_t)0xc72ea70, (q31_t)0x25ed6614, + (q31_t)0xc7a5dde, (q31_t)0x25f78497, (q31_t)0xc81d349, (q31_t)0x2601a1a2, + (q31_t)0xc894aaf, (q31_t)0x260bbd37, (q31_t)0xc90c412, (q31_t)0x2615d754, + (q31_t)0xc983f70, (q31_t)0x261feffa, (q31_t)0xc9fbcca, (q31_t)0x262a0727, + (q31_t)0xca73c1e, (q31_t)0x26341cdb, (q31_t)0xcaebd6e, (q31_t)0x263e3117, + (q31_t)0xcb640b8, (q31_t)0x264843d9, (q31_t)0xcbdc5fc, (q31_t)0x26525521, + (q31_t)0xcc54d3a, (q31_t)0x265c64ef, (q31_t)0xcccd671, (q31_t)0x26667342, + (q31_t)0xcd461a2, (q31_t)0x2670801a, (q31_t)0xcdbeecc, (q31_t)0x267a8b77, + (q31_t)0xce37def, (q31_t)0x26849558, (q31_t)0xceb0f0a, (q31_t)0x268e9dbd, + (q31_t)0xcf2a21d, (q31_t)0x2698a4a6, (q31_t)0xcfa3729, (q31_t)0x26a2aa11, + (q31_t)0xd01ce2b, (q31_t)0x26acadff, (q31_t)0xd096725, (q31_t)0x26b6b070, + (q31_t)0xd110216, (q31_t)0x26c0b162, (q31_t)0xd189efe, (q31_t)0x26cab0d6, + (q31_t)0xd203ddc, (q31_t)0x26d4aecb, (q31_t)0xd27deb0, (q31_t)0x26deab41, + (q31_t)0xd2f817b, (q31_t)0x26e8a637, (q31_t)0xd37263a, (q31_t)0x26f29fad, + (q31_t)0xd3eccef, (q31_t)0x26fc97a3, (q31_t)0xd467599, (q31_t)0x27068e18, + (q31_t)0xd4e2037, (q31_t)0x2710830c, (q31_t)0xd55ccca, (q31_t)0x271a767e, + (q31_t)0xd5d7b50, (q31_t)0x2724686e, (q31_t)0xd652bcb, (q31_t)0x272e58dc, + (q31_t)0xd6cde39, (q31_t)0x273847c8, (q31_t)0xd74929a, (q31_t)0x27423530, + (q31_t)0xd7c48ee, (q31_t)0x274c2115, (q31_t)0xd840134, (q31_t)0x27560b76, + (q31_t)0xd8bbb6d, (q31_t)0x275ff452, (q31_t)0xd937798, (q31_t)0x2769dbaa, + (q31_t)0xd9b35b4, (q31_t)0x2773c17d, (q31_t)0xda2f5c2, (q31_t)0x277da5cb, + (q31_t)0xdaab7c0, (q31_t)0x27878893, (q31_t)0xdb27bb0, (q31_t)0x279169d5, + (q31_t)0xdba4190, (q31_t)0x279b4990, (q31_t)0xdc20960, (q31_t)0x27a527c4, + (q31_t)0xdc9d320, (q31_t)0x27af0472, (q31_t)0xdd19ed0, (q31_t)0x27b8df97, + (q31_t)0xdd96c6f, (q31_t)0x27c2b934, (q31_t)0xde13bfd, (q31_t)0x27cc9149, + (q31_t)0xde90d79, (q31_t)0x27d667d5, (q31_t)0xdf0e0e4, (q31_t)0x27e03cd8, + (q31_t)0xdf8b63d, (q31_t)0x27ea1052, (q31_t)0xe008d84, (q31_t)0x27f3e241, + (q31_t)0xe0866b8, (q31_t)0x27fdb2a7, (q31_t)0xe1041d9, (q31_t)0x28078181, + (q31_t)0xe181ee8, (q31_t)0x28114ed0, (q31_t)0xe1ffde2, (q31_t)0x281b1a94, + (q31_t)0xe27dec9, (q31_t)0x2824e4cc, (q31_t)0xe2fc19c, (q31_t)0x282ead78, + (q31_t)0xe37a65b, (q31_t)0x28387498, (q31_t)0xe3f8d05, (q31_t)0x28423a2a, + (q31_t)0xe47759a, (q31_t)0x284bfe2f, (q31_t)0xe4f6019, (q31_t)0x2855c0a6, + (q31_t)0xe574c84, (q31_t)0x285f8190, (q31_t)0xe5f3ad8, (q31_t)0x286940ea, + (q31_t)0xe672b16, (q31_t)0x2872feb6, (q31_t)0xe6f1d3d, (q31_t)0x287cbaf3, + (q31_t)0xe77114e, (q31_t)0x288675a0, (q31_t)0xe7f0748, (q31_t)0x28902ebd, + (q31_t)0xe86ff2a, (q31_t)0x2899e64a, (q31_t)0xe8ef8f4, (q31_t)0x28a39c46, + (q31_t)0xe96f4a7, (q31_t)0x28ad50b1, (q31_t)0xe9ef241, (q31_t)0x28b7038b, + (q31_t)0xea6f1c2, (q31_t)0x28c0b4d2, (q31_t)0xeaef32b, (q31_t)0x28ca6488, + (q31_t)0xeb6f67a, (q31_t)0x28d412ab, (q31_t)0xebefbb0, (q31_t)0x28ddbf3b, + (q31_t)0xec702cb, (q31_t)0x28e76a37, (q31_t)0xecf0bcd, (q31_t)0x28f113a0, + (q31_t)0xed716b4, (q31_t)0x28fabb75, (q31_t)0xedf2380, (q31_t)0x290461b5, + (q31_t)0xee73231, (q31_t)0x290e0661, (q31_t)0xeef42c7, (q31_t)0x2917a977, + (q31_t)0xef75541, (q31_t)0x29214af8, (q31_t)0xeff699f, (q31_t)0x292aeae3, + (q31_t)0xf077fe1, (q31_t)0x29348937, (q31_t)0xf0f9805, (q31_t)0x293e25f5, + (q31_t)0xf17b20d, (q31_t)0x2947c11c, (q31_t)0xf1fcdf8, (q31_t)0x29515aab, + (q31_t)0xf27ebc5, (q31_t)0x295af2a3, (q31_t)0xf300b74, (q31_t)0x29648902, + (q31_t)0xf382d05, (q31_t)0x296e1dc9, (q31_t)0xf405077, (q31_t)0x2977b0f7, + (q31_t)0xf4875ca, (q31_t)0x2981428c, (q31_t)0xf509cfe, (q31_t)0x298ad287, + (q31_t)0xf58c613, (q31_t)0x299460e8, (q31_t)0xf60f108, (q31_t)0x299dedaf, + (q31_t)0xf691ddd, (q31_t)0x29a778db, (q31_t)0xf714c91, (q31_t)0x29b1026c, + (q31_t)0xf797d24, (q31_t)0x29ba8a61, (q31_t)0xf81af97, (q31_t)0x29c410ba, + (q31_t)0xf89e3e8, (q31_t)0x29cd9578, (q31_t)0xf921a17, (q31_t)0x29d71899, + (q31_t)0xf9a5225, (q31_t)0x29e09a1c, (q31_t)0xfa28c10, (q31_t)0x29ea1a03, + (q31_t)0xfaac7d8, (q31_t)0x29f3984c, (q31_t)0xfb3057d, (q31_t)0x29fd14f6, + (q31_t)0xfbb4500, (q31_t)0x2a069003, (q31_t)0xfc3865e, (q31_t)0x2a100970, + (q31_t)0xfcbc999, (q31_t)0x2a19813f, (q31_t)0xfd40eaf, (q31_t)0x2a22f76e, + (q31_t)0xfdc55a1, (q31_t)0x2a2c6bfd, (q31_t)0xfe49e6d, (q31_t)0x2a35deeb, + (q31_t)0xfece915, (q31_t)0x2a3f503a, (q31_t)0xff53597, (q31_t)0x2a48bfe7, + (q31_t)0xffd83f4, (q31_t)0x2a522df3, (q31_t)0x1005d42a, (q31_t)0x2a5b9a5d, + (q31_t)0x100e2639, (q31_t)0x2a650525, (q31_t)0x10167a22, (q31_t)0x2a6e6e4b, + (q31_t)0x101ecfe4, (q31_t)0x2a77d5ce, (q31_t)0x1027277e, (q31_t)0x2a813bae, + (q31_t)0x102f80f1, (q31_t)0x2a8a9fea, (q31_t)0x1037dc3b, (q31_t)0x2a940283, + (q31_t)0x1040395d, (q31_t)0x2a9d6377, (q31_t)0x10489856, (q31_t)0x2aa6c2c6, + (q31_t)0x1050f926, (q31_t)0x2ab02071, (q31_t)0x10595bcd, (q31_t)0x2ab97c77, + (q31_t)0x1061c04a, (q31_t)0x2ac2d6d6, (q31_t)0x106a269d, (q31_t)0x2acc2f90, + (q31_t)0x10728ec6, (q31_t)0x2ad586a3, (q31_t)0x107af8c4, (q31_t)0x2adedc10, + (q31_t)0x10836497, (q31_t)0x2ae82fd5, (q31_t)0x108bd23f, (q31_t)0x2af181f3, + (q31_t)0x109441bb, (q31_t)0x2afad269, (q31_t)0x109cb30b, (q31_t)0x2b042137, + (q31_t)0x10a5262f, (q31_t)0x2b0d6e5c, (q31_t)0x10ad9b26, (q31_t)0x2b16b9d9, + (q31_t)0x10b611f1, (q31_t)0x2b2003ac, (q31_t)0x10be8a8d, (q31_t)0x2b294bd5, + (q31_t)0x10c704fd, (q31_t)0x2b329255, (q31_t)0x10cf813e, (q31_t)0x2b3bd72a, + (q31_t)0x10d7ff51, (q31_t)0x2b451a55, (q31_t)0x10e07f36, (q31_t)0x2b4e5bd4, + (q31_t)0x10e900ec, (q31_t)0x2b579ba8, (q31_t)0x10f18472, (q31_t)0x2b60d9d0, + (q31_t)0x10fa09c9, (q31_t)0x2b6a164d, (q31_t)0x110290f0, (q31_t)0x2b73511c, + (q31_t)0x110b19e7, (q31_t)0x2b7c8a3f, (q31_t)0x1113a4ad, (q31_t)0x2b85c1b5, + (q31_t)0x111c3142, (q31_t)0x2b8ef77d, (q31_t)0x1124bfa6, (q31_t)0x2b982b97, + (q31_t)0x112d4fd9, (q31_t)0x2ba15e03, (q31_t)0x1135e1d9, (q31_t)0x2baa8ec0, + (q31_t)0x113e75a8, (q31_t)0x2bb3bdce, (q31_t)0x11470b44, (q31_t)0x2bbceb2d, + (q31_t)0x114fa2ad, (q31_t)0x2bc616dd, (q31_t)0x11583be2, (q31_t)0x2bcf40dc, + (q31_t)0x1160d6e5, (q31_t)0x2bd8692b, (q31_t)0x116973b3, (q31_t)0x2be18fc9, + (q31_t)0x1172124d, (q31_t)0x2beab4b6, (q31_t)0x117ab2b3, (q31_t)0x2bf3d7f2, + (q31_t)0x118354e4, (q31_t)0x2bfcf97c, (q31_t)0x118bf8e0, (q31_t)0x2c061953, + (q31_t)0x11949ea6, (q31_t)0x2c0f3779, (q31_t)0x119d4636, (q31_t)0x2c1853eb, + (q31_t)0x11a5ef90, (q31_t)0x2c216eaa, (q31_t)0x11ae9ab4, (q31_t)0x2c2a87b6, + (q31_t)0x11b747a0, (q31_t)0x2c339f0e, (q31_t)0x11bff656, (q31_t)0x2c3cb4b1, + (q31_t)0x11c8a6d4, (q31_t)0x2c45c8a0, (q31_t)0x11d1591a, (q31_t)0x2c4edada, + (q31_t)0x11da0d28, (q31_t)0x2c57eb5e, (q31_t)0x11e2c2fd, (q31_t)0x2c60fa2d, + (q31_t)0x11eb7a9a, (q31_t)0x2c6a0746, (q31_t)0x11f433fd, (q31_t)0x2c7312a9, + (q31_t)0x11fcef27, (q31_t)0x2c7c1c55, (q31_t)0x1205ac17, (q31_t)0x2c85244a, + (q31_t)0x120e6acc, (q31_t)0x2c8e2a87, (q31_t)0x12172b48, (q31_t)0x2c972f0d, + (q31_t)0x121fed88, (q31_t)0x2ca031da, (q31_t)0x1228b18d, (q31_t)0x2ca932ef, + (q31_t)0x12317756, (q31_t)0x2cb2324c, (q31_t)0x123a3ee4, (q31_t)0x2cbb2fef, + (q31_t)0x12430835, (q31_t)0x2cc42bd9, (q31_t)0x124bd34a, (q31_t)0x2ccd2609, + (q31_t)0x1254a021, (q31_t)0x2cd61e7f, (q31_t)0x125d6ebc, (q31_t)0x2cdf153a, + (q31_t)0x12663f19, (q31_t)0x2ce80a3a, (q31_t)0x126f1138, (q31_t)0x2cf0fd80, + (q31_t)0x1277e518, (q31_t)0x2cf9ef09, (q31_t)0x1280babb, (q31_t)0x2d02ded7, + (q31_t)0x1289921e, (q31_t)0x2d0bcce8, (q31_t)0x12926b41, (q31_t)0x2d14b93d, + (q31_t)0x129b4626, (q31_t)0x2d1da3d5, (q31_t)0x12a422ca, (q31_t)0x2d268cb0, + (q31_t)0x12ad012e, (q31_t)0x2d2f73cd, (q31_t)0x12b5e151, (q31_t)0x2d38592c, + (q31_t)0x12bec333, (q31_t)0x2d413ccd, (q31_t)0x12c7a6d4, (q31_t)0x2d4a1eaf, + (q31_t)0x12d08c33, (q31_t)0x2d52fed2, (q31_t)0x12d97350, (q31_t)0x2d5bdd36, + (q31_t)0x12e25c2b, (q31_t)0x2d64b9da, (q31_t)0x12eb46c3, (q31_t)0x2d6d94bf, + (q31_t)0x12f43318, (q31_t)0x2d766de2, (q31_t)0x12fd2129, (q31_t)0x2d7f4545, + (q31_t)0x130610f7, (q31_t)0x2d881ae8, (q31_t)0x130f0280, (q31_t)0x2d90eec8, + (q31_t)0x1317f5c6, (q31_t)0x2d99c0e7, (q31_t)0x1320eac6, (q31_t)0x2da29144, + (q31_t)0x1329e181, (q31_t)0x2dab5fdf, (q31_t)0x1332d9f7, (q31_t)0x2db42cb6, + (q31_t)0x133bd427, (q31_t)0x2dbcf7cb, (q31_t)0x1344d011, (q31_t)0x2dc5c11c, + (q31_t)0x134dcdb4, (q31_t)0x2dce88aa, (q31_t)0x1356cd11, (q31_t)0x2dd74e73, + (q31_t)0x135fce26, (q31_t)0x2de01278, (q31_t)0x1368d0f3, (q31_t)0x2de8d4b8, + (q31_t)0x1371d579, (q31_t)0x2df19534, (q31_t)0x137adbb6, (q31_t)0x2dfa53e9, + (q31_t)0x1383e3ab, (q31_t)0x2e0310d9, (q31_t)0x138ced57, (q31_t)0x2e0bcc03, + (q31_t)0x1395f8ba, (q31_t)0x2e148566, (q31_t)0x139f05d3, (q31_t)0x2e1d3d03, + (q31_t)0x13a814a2, (q31_t)0x2e25f2d8, (q31_t)0x13b12526, (q31_t)0x2e2ea6e6, + (q31_t)0x13ba3760, (q31_t)0x2e37592c, (q31_t)0x13c34b4f, (q31_t)0x2e4009aa, + (q31_t)0x13cc60f2, (q31_t)0x2e48b860, (q31_t)0x13d5784a, (q31_t)0x2e51654c, + (q31_t)0x13de9156, (q31_t)0x2e5a1070, (q31_t)0x13e7ac15, (q31_t)0x2e62b9ca, + (q31_t)0x13f0c887, (q31_t)0x2e6b615a, (q31_t)0x13f9e6ad, (q31_t)0x2e740720, + (q31_t)0x14030684, (q31_t)0x2e7cab1c, (q31_t)0x140c280e, (q31_t)0x2e854d4d, + (q31_t)0x14154b4a, (q31_t)0x2e8dedb3, (q31_t)0x141e7037, (q31_t)0x2e968c4d, + (q31_t)0x142796d5, (q31_t)0x2e9f291b, (q31_t)0x1430bf24, (q31_t)0x2ea7c41e, + (q31_t)0x1439e923, (q31_t)0x2eb05d53, (q31_t)0x144314d3, (q31_t)0x2eb8f4bc, + (q31_t)0x144c4232, (q31_t)0x2ec18a58, (q31_t)0x14557140, (q31_t)0x2eca1e27, + (q31_t)0x145ea1fd, (q31_t)0x2ed2b027, (q31_t)0x1467d469, (q31_t)0x2edb405a, + (q31_t)0x14710883, (q31_t)0x2ee3cebe, (q31_t)0x147a3e4b, (q31_t)0x2eec5b53, + (q31_t)0x148375c1, (q31_t)0x2ef4e619, (q31_t)0x148caee4, (q31_t)0x2efd6f10, + (q31_t)0x1495e9b3, (q31_t)0x2f05f637, (q31_t)0x149f2630, (q31_t)0x2f0e7b8e, + (q31_t)0x14a86458, (q31_t)0x2f16ff14, (q31_t)0x14b1a42c, (q31_t)0x2f1f80ca, + (q31_t)0x14bae5ab, (q31_t)0x2f2800af, (q31_t)0x14c428d6, (q31_t)0x2f307ec2, + (q31_t)0x14cd6dab, (q31_t)0x2f38fb03, (q31_t)0x14d6b42b, (q31_t)0x2f417573, + (q31_t)0x14dffc54, (q31_t)0x2f49ee0f, (q31_t)0x14e94627, (q31_t)0x2f5264da, + (q31_t)0x14f291a4, (q31_t)0x2f5ad9d1, (q31_t)0x14fbdec9, (q31_t)0x2f634cf5, + (q31_t)0x15052d97, (q31_t)0x2f6bbe45, (q31_t)0x150e7e0d, (q31_t)0x2f742dc1, + (q31_t)0x1517d02b, (q31_t)0x2f7c9b69, (q31_t)0x152123f0, (q31_t)0x2f85073c, + (q31_t)0x152a795d, (q31_t)0x2f8d713a, (q31_t)0x1533d070, (q31_t)0x2f95d963, + (q31_t)0x153d292a, (q31_t)0x2f9e3fb6, (q31_t)0x15468389, (q31_t)0x2fa6a433, + (q31_t)0x154fdf8f, (q31_t)0x2faf06da, (q31_t)0x15593d3a, (q31_t)0x2fb767aa, + (q31_t)0x15629c89, (q31_t)0x2fbfc6a3, (q31_t)0x156bfd7d, (q31_t)0x2fc823c5, + (q31_t)0x15756016, (q31_t)0x2fd07f0f, (q31_t)0x157ec452, (q31_t)0x2fd8d882, + (q31_t)0x15882a32, (q31_t)0x2fe1301c, (q31_t)0x159191b5, (q31_t)0x2fe985de, + (q31_t)0x159afadb, (q31_t)0x2ff1d9c7, (q31_t)0x15a465a3, (q31_t)0x2ffa2bd6, + (q31_t)0x15add20d, (q31_t)0x30027c0c, (q31_t)0x15b74019, (q31_t)0x300aca69, + (q31_t)0x15c0afc6, (q31_t)0x301316eb, (q31_t)0x15ca2115, (q31_t)0x301b6193, + (q31_t)0x15d39403, (q31_t)0x3023aa5f, (q31_t)0x15dd0892, (q31_t)0x302bf151, + (q31_t)0x15e67ec1, (q31_t)0x30343667, (q31_t)0x15eff690, (q31_t)0x303c79a2, + (q31_t)0x15f96ffd, (q31_t)0x3044bb00, (q31_t)0x1602eb0a, (q31_t)0x304cfa83, + (q31_t)0x160c67b4, (q31_t)0x30553828, (q31_t)0x1615e5fd, (q31_t)0x305d73f0, + (q31_t)0x161f65e4, (q31_t)0x3065addb, (q31_t)0x1628e767, (q31_t)0x306de5e9, + (q31_t)0x16326a88, (q31_t)0x30761c18, (q31_t)0x163bef46, (q31_t)0x307e5069, + (q31_t)0x1645759f, (q31_t)0x308682dc, (q31_t)0x164efd94, (q31_t)0x308eb36f, + (q31_t)0x16588725, (q31_t)0x3096e223, (q31_t)0x16621251, (q31_t)0x309f0ef8, + (q31_t)0x166b9f18, (q31_t)0x30a739ed, (q31_t)0x16752d79, (q31_t)0x30af6302, + (q31_t)0x167ebd74, (q31_t)0x30b78a36, (q31_t)0x16884f09, (q31_t)0x30bfaf89, + (q31_t)0x1691e237, (q31_t)0x30c7d2fb, (q31_t)0x169b76fe, (q31_t)0x30cff48c, + (q31_t)0x16a50d5d, (q31_t)0x30d8143b, (q31_t)0x16aea555, (q31_t)0x30e03208, + (q31_t)0x16b83ee4, (q31_t)0x30e84df3, (q31_t)0x16c1da0b, (q31_t)0x30f067fb, + (q31_t)0x16cb76c9, (q31_t)0x30f8801f, (q31_t)0x16d5151d, (q31_t)0x31009661, + (q31_t)0x16deb508, (q31_t)0x3108aabf, (q31_t)0x16e85689, (q31_t)0x3110bd39, + (q31_t)0x16f1f99f, (q31_t)0x3118cdcf, (q31_t)0x16fb9e4b, (q31_t)0x3120dc80, + (q31_t)0x1705448b, (q31_t)0x3128e94c, (q31_t)0x170eec60, (q31_t)0x3130f433, + (q31_t)0x171895c9, (q31_t)0x3138fd35, (q31_t)0x172240c5, (q31_t)0x31410450, + (q31_t)0x172bed55, (q31_t)0x31490986, (q31_t)0x17359b78, (q31_t)0x31510cd5, + (q31_t)0x173f4b2e, (q31_t)0x31590e3e, (q31_t)0x1748fc75, (q31_t)0x31610dbf, + (q31_t)0x1752af4f, (q31_t)0x31690b59, (q31_t)0x175c63ba, (q31_t)0x3171070c, + (q31_t)0x176619b6, (q31_t)0x317900d6, (q31_t)0x176fd143, (q31_t)0x3180f8b8, + (q31_t)0x17798a60, (q31_t)0x3188eeb2, (q31_t)0x1783450d, (q31_t)0x3190e2c3, + (q31_t)0x178d014a, (q31_t)0x3198d4ea, (q31_t)0x1796bf16, (q31_t)0x31a0c528, + (q31_t)0x17a07e70, (q31_t)0x31a8b37c, (q31_t)0x17aa3f5a, (q31_t)0x31b09fe7, + (q31_t)0x17b401d1, (q31_t)0x31b88a66, (q31_t)0x17bdc5d6, (q31_t)0x31c072fb, + (q31_t)0x17c78b68, (q31_t)0x31c859a5, (q31_t)0x17d15288, (q31_t)0x31d03e64, + (q31_t)0x17db1b34, (q31_t)0x31d82137, (q31_t)0x17e4e56c, (q31_t)0x31e0021e, + (q31_t)0x17eeb130, (q31_t)0x31e7e118, (q31_t)0x17f87e7f, (q31_t)0x31efbe27, + (q31_t)0x18024d59, (q31_t)0x31f79948, (q31_t)0x180c1dbf, (q31_t)0x31ff727c, + (q31_t)0x1815efae, (q31_t)0x320749c3, (q31_t)0x181fc328, (q31_t)0x320f1f1c, + (q31_t)0x1829982b, (q31_t)0x3216f287, (q31_t)0x18336eb7, (q31_t)0x321ec403, + (q31_t)0x183d46cc, (q31_t)0x32269391, (q31_t)0x18472069, (q31_t)0x322e6130, + (q31_t)0x1850fb8e, (q31_t)0x32362ce0, (q31_t)0x185ad83c, (q31_t)0x323df6a0, + (q31_t)0x1864b670, (q31_t)0x3245be70, (q31_t)0x186e962b, (q31_t)0x324d8450, + (q31_t)0x1878776d, (q31_t)0x32554840, (q31_t)0x18825a35, (q31_t)0x325d0a3e, + (q31_t)0x188c3e83, (q31_t)0x3264ca4c, (q31_t)0x18962456, (q31_t)0x326c8868, + (q31_t)0x18a00bae, (q31_t)0x32744493, (q31_t)0x18a9f48a, (q31_t)0x327bfecc, + (q31_t)0x18b3deeb, (q31_t)0x3283b712, (q31_t)0x18bdcad0, (q31_t)0x328b6d66, + (q31_t)0x18c7b838, (q31_t)0x329321c7, (q31_t)0x18d1a724, (q31_t)0x329ad435, + (q31_t)0x18db9792, (q31_t)0x32a284b0, (q31_t)0x18e58982, (q31_t)0x32aa3336, + (q31_t)0x18ef7cf4, (q31_t)0x32b1dfc9, (q31_t)0x18f971e8, (q31_t)0x32b98a67, + (q31_t)0x1903685d, (q31_t)0x32c13311, (q31_t)0x190d6053, (q31_t)0x32c8d9c6, + (q31_t)0x191759c9, (q31_t)0x32d07e85, (q31_t)0x192154bf, (q31_t)0x32d82150, + (q31_t)0x192b5135, (q31_t)0x32dfc224, (q31_t)0x19354f2a, (q31_t)0x32e76102, + (q31_t)0x193f4e9e, (q31_t)0x32eefdea, (q31_t)0x19494f90, (q31_t)0x32f698db, + (q31_t)0x19535201, (q31_t)0x32fe31d5, (q31_t)0x195d55ef, (q31_t)0x3305c8d7, + (q31_t)0x19675b5a, (q31_t)0x330d5de3, (q31_t)0x19716243, (q31_t)0x3314f0f6, + (q31_t)0x197b6aa8, (q31_t)0x331c8211, (q31_t)0x19857489, (q31_t)0x33241134, + (q31_t)0x198f7fe6, (q31_t)0x332b9e5e, (q31_t)0x19998cbe, (q31_t)0x3333298f, + (q31_t)0x19a39b11, (q31_t)0x333ab2c6, (q31_t)0x19adaadf, (q31_t)0x33423a04, + (q31_t)0x19b7bc27, (q31_t)0x3349bf48, (q31_t)0x19c1cee9, (q31_t)0x33514292, + (q31_t)0x19cbe325, (q31_t)0x3358c3e2, (q31_t)0x19d5f8d9, (q31_t)0x33604336, + (q31_t)0x19e01006, (q31_t)0x3367c090, (q31_t)0x19ea28ac, (q31_t)0x336f3bee, + (q31_t)0x19f442c9, (q31_t)0x3376b551, (q31_t)0x19fe5e5e, (q31_t)0x337e2cb7, + (q31_t)0x1a087b69, (q31_t)0x3385a222, (q31_t)0x1a1299ec, (q31_t)0x338d1590, + (q31_t)0x1a1cb9e5, (q31_t)0x33948701, (q31_t)0x1a26db54, (q31_t)0x339bf675, + (q31_t)0x1a30fe38, (q31_t)0x33a363ec, (q31_t)0x1a3b2292, (q31_t)0x33aacf65, + (q31_t)0x1a454860, (q31_t)0x33b238e0, (q31_t)0x1a4f6fa3, (q31_t)0x33b9a05d, + (q31_t)0x1a599859, (q31_t)0x33c105db, (q31_t)0x1a63c284, (q31_t)0x33c8695b, + (q31_t)0x1a6dee21, (q31_t)0x33cfcadc, (q31_t)0x1a781b31, (q31_t)0x33d72a5d, + (q31_t)0x1a8249b4, (q31_t)0x33de87de, (q31_t)0x1a8c79a9, (q31_t)0x33e5e360, + (q31_t)0x1a96ab0f, (q31_t)0x33ed3ce1, (q31_t)0x1aa0dde7, (q31_t)0x33f49462, + (q31_t)0x1aab122f, (q31_t)0x33fbe9e2, (q31_t)0x1ab547e8, (q31_t)0x34033d61, + (q31_t)0x1abf7f11, (q31_t)0x340a8edf, (q31_t)0x1ac9b7a9, (q31_t)0x3411de5b, + (q31_t)0x1ad3f1b1, (q31_t)0x34192bd5, (q31_t)0x1ade2d28, (q31_t)0x3420774d, + (q31_t)0x1ae86a0d, (q31_t)0x3427c0c3, (q31_t)0x1af2a860, (q31_t)0x342f0836, + (q31_t)0x1afce821, (q31_t)0x34364da6, (q31_t)0x1b072950, (q31_t)0x343d9112, + (q31_t)0x1b116beb, (q31_t)0x3444d27b, (q31_t)0x1b1baff2, (q31_t)0x344c11e0, + (q31_t)0x1b25f566, (q31_t)0x34534f41, (q31_t)0x1b303c46, (q31_t)0x345a8a9d, + (q31_t)0x1b3a8491, (q31_t)0x3461c3f5, (q31_t)0x1b44ce46, (q31_t)0x3468fb47, + (q31_t)0x1b4f1967, (q31_t)0x34703095, (q31_t)0x1b5965f1, (q31_t)0x347763dd, + (q31_t)0x1b63b3e5, (q31_t)0x347e951f, (q31_t)0x1b6e0342, (q31_t)0x3485c45b, + (q31_t)0x1b785409, (q31_t)0x348cf190, (q31_t)0x1b82a638, (q31_t)0x34941cbf, + (q31_t)0x1b8cf9cf, (q31_t)0x349b45e7, (q31_t)0x1b974ece, (q31_t)0x34a26d08, + (q31_t)0x1ba1a534, (q31_t)0x34a99221, (q31_t)0x1babfd01, (q31_t)0x34b0b533, + (q31_t)0x1bb65634, (q31_t)0x34b7d63c, (q31_t)0x1bc0b0ce, (q31_t)0x34bef53d, + (q31_t)0x1bcb0cce, (q31_t)0x34c61236, (q31_t)0x1bd56a32, (q31_t)0x34cd2d26, + (q31_t)0x1bdfc8fc, (q31_t)0x34d4460c, (q31_t)0x1bea292b, (q31_t)0x34db5cea, + (q31_t)0x1bf48abd, (q31_t)0x34e271bd, (q31_t)0x1bfeedb3, (q31_t)0x34e98487, + (q31_t)0x1c09520d, (q31_t)0x34f09546, (q31_t)0x1c13b7c9, (q31_t)0x34f7a3fb, + (q31_t)0x1c1e1ee9, (q31_t)0x34feb0a5, (q31_t)0x1c28876a, (q31_t)0x3505bb44, + (q31_t)0x1c32f14d, (q31_t)0x350cc3d8, (q31_t)0x1c3d5c91, (q31_t)0x3513ca60, + (q31_t)0x1c47c936, (q31_t)0x351acedd, (q31_t)0x1c52373c, (q31_t)0x3521d14d, + (q31_t)0x1c5ca6a2, (q31_t)0x3528d1b1, (q31_t)0x1c671768, (q31_t)0x352fd008, + (q31_t)0x1c71898d, (q31_t)0x3536cc52, (q31_t)0x1c7bfd11, (q31_t)0x353dc68f, + (q31_t)0x1c8671f3, (q31_t)0x3544bebf, (q31_t)0x1c90e834, (q31_t)0x354bb4e1, + (q31_t)0x1c9b5fd2, (q31_t)0x3552a8f4, (q31_t)0x1ca5d8cd, (q31_t)0x35599afa, + (q31_t)0x1cb05326, (q31_t)0x35608af1, (q31_t)0x1cbacedb, (q31_t)0x356778d9, + (q31_t)0x1cc54bec, (q31_t)0x356e64b2, (q31_t)0x1ccfca59, (q31_t)0x35754e7c, + (q31_t)0x1cda4a21, (q31_t)0x357c3636, (q31_t)0x1ce4cb44, (q31_t)0x35831be0, + (q31_t)0x1cef4dc2, (q31_t)0x3589ff7a, (q31_t)0x1cf9d199, (q31_t)0x3590e104, + (q31_t)0x1d0456ca, (q31_t)0x3597c07d, (q31_t)0x1d0edd55, (q31_t)0x359e9de5, + (q31_t)0x1d196538, (q31_t)0x35a5793c, (q31_t)0x1d23ee74, (q31_t)0x35ac5282, + (q31_t)0x1d2e7908, (q31_t)0x35b329b5, (q31_t)0x1d3904f4, (q31_t)0x35b9fed7, + (q31_t)0x1d439236, (q31_t)0x35c0d1e7, (q31_t)0x1d4e20d0, (q31_t)0x35c7a2e3, + (q31_t)0x1d58b0c0, (q31_t)0x35ce71ce, (q31_t)0x1d634206, (q31_t)0x35d53ea5, + (q31_t)0x1d6dd4a2, (q31_t)0x35dc0968, (q31_t)0x1d786892, (q31_t)0x35e2d219, + (q31_t)0x1d82fdd8, (q31_t)0x35e998b5, (q31_t)0x1d8d9472, (q31_t)0x35f05d3d, + (q31_t)0x1d982c60, (q31_t)0x35f71fb1, (q31_t)0x1da2c5a2, (q31_t)0x35fde011, + (q31_t)0x1dad6036, (q31_t)0x36049e5b, (q31_t)0x1db7fc1e, (q31_t)0x360b5a90, + (q31_t)0x1dc29958, (q31_t)0x361214b0, (q31_t)0x1dcd37e4, (q31_t)0x3618ccba, + (q31_t)0x1dd7d7c1, (q31_t)0x361f82af, (q31_t)0x1de278ef, (q31_t)0x3626368d, + (q31_t)0x1ded1b6e, (q31_t)0x362ce855, (q31_t)0x1df7bf3e, (q31_t)0x36339806, + (q31_t)0x1e02645d, (q31_t)0x363a45a0, (q31_t)0x1e0d0acc, (q31_t)0x3640f123, + (q31_t)0x1e17b28a, (q31_t)0x36479a8e, (q31_t)0x1e225b96, (q31_t)0x364e41e2, + (q31_t)0x1e2d05f1, (q31_t)0x3654e71d, (q31_t)0x1e37b199, (q31_t)0x365b8a41, + (q31_t)0x1e425e8f, (q31_t)0x36622b4c, (q31_t)0x1e4d0cd2, (q31_t)0x3668ca3e, + (q31_t)0x1e57bc62, (q31_t)0x366f6717, (q31_t)0x1e626d3e, (q31_t)0x367601d7, + (q31_t)0x1e6d1f65, (q31_t)0x367c9a7e, (q31_t)0x1e77d2d8, (q31_t)0x3683310b, + (q31_t)0x1e828796, (q31_t)0x3689c57d, (q31_t)0x1e8d3d9e, (q31_t)0x369057d6, + (q31_t)0x1e97f4f1, (q31_t)0x3696e814, (q31_t)0x1ea2ad8d, (q31_t)0x369d7637, + (q31_t)0x1ead6773, (q31_t)0x36a4023f, (q31_t)0x1eb822a1, (q31_t)0x36aa8c2c, + (q31_t)0x1ec2df18, (q31_t)0x36b113fd, (q31_t)0x1ecd9cd7, (q31_t)0x36b799b3, + (q31_t)0x1ed85bdd, (q31_t)0x36be1d4c, (q31_t)0x1ee31c2b, (q31_t)0x36c49ec9, + (q31_t)0x1eedddc0, (q31_t)0x36cb1e2a, (q31_t)0x1ef8a09b, (q31_t)0x36d19b6e, + (q31_t)0x1f0364bc, (q31_t)0x36d81695, (q31_t)0x1f0e2a22, (q31_t)0x36de8f9e, + (q31_t)0x1f18f0ce, (q31_t)0x36e5068a, (q31_t)0x1f23b8be, (q31_t)0x36eb7b58, + (q31_t)0x1f2e81f3, (q31_t)0x36f1ee09, (q31_t)0x1f394c6b, (q31_t)0x36f85e9a, + (q31_t)0x1f441828, (q31_t)0x36fecd0e, (q31_t)0x1f4ee527, (q31_t)0x37053962, + (q31_t)0x1f59b369, (q31_t)0x370ba398, (q31_t)0x1f6482ed, (q31_t)0x37120bae, + (q31_t)0x1f6f53b3, (q31_t)0x371871a5, (q31_t)0x1f7a25ba, (q31_t)0x371ed57c, + (q31_t)0x1f84f902, (q31_t)0x37253733, (q31_t)0x1f8fcd8b, (q31_t)0x372b96ca, + (q31_t)0x1f9aa354, (q31_t)0x3731f440, (q31_t)0x1fa57a5d, (q31_t)0x37384f95, + (q31_t)0x1fb052a5, (q31_t)0x373ea8ca, (q31_t)0x1fbb2c2c, (q31_t)0x3744ffdd, + (q31_t)0x1fc606f1, (q31_t)0x374b54ce, (q31_t)0x1fd0e2f5, (q31_t)0x3751a79e, + (q31_t)0x1fdbc036, (q31_t)0x3757f84c, (q31_t)0x1fe69eb4, (q31_t)0x375e46d8, + (q31_t)0x1ff17e70, (q31_t)0x37649341, (q31_t)0x1ffc5f67, (q31_t)0x376add88, + (q31_t)0x2007419b, (q31_t)0x377125ac, (q31_t)0x2012250a, (q31_t)0x37776bac, + (q31_t)0x201d09b4, (q31_t)0x377daf89, (q31_t)0x2027ef99, (q31_t)0x3783f143, + (q31_t)0x2032d6b8, (q31_t)0x378a30d8, (q31_t)0x203dbf11, (q31_t)0x37906e49, + (q31_t)0x2048a8a4, (q31_t)0x3796a996, (q31_t)0x2053936f, (q31_t)0x379ce2be, + (q31_t)0x205e7f74, (q31_t)0x37a319c2, (q31_t)0x20696cb0, (q31_t)0x37a94ea0, + (q31_t)0x20745b24, (q31_t)0x37af8159, (q31_t)0x207f4acf, (q31_t)0x37b5b1ec, + (q31_t)0x208a3bb2, (q31_t)0x37bbe05a, (q31_t)0x20952dcb, (q31_t)0x37c20ca1, + (q31_t)0x20a0211a, (q31_t)0x37c836c2, (q31_t)0x20ab159e, (q31_t)0x37ce5ebd, + (q31_t)0x20b60b58, (q31_t)0x37d48490, (q31_t)0x20c10247, (q31_t)0x37daa83d, + (q31_t)0x20cbfa6a, (q31_t)0x37e0c9c3, (q31_t)0x20d6f3c1, (q31_t)0x37e6e921, + (q31_t)0x20e1ee4b, (q31_t)0x37ed0657, (q31_t)0x20ecea09, (q31_t)0x37f32165, + (q31_t)0x20f7e6f9, (q31_t)0x37f93a4b, (q31_t)0x2102e51c, (q31_t)0x37ff5109, + (q31_t)0x210de470, (q31_t)0x3805659e, (q31_t)0x2118e4f6, (q31_t)0x380b780a, + (q31_t)0x2123e6ad, (q31_t)0x3811884d, (q31_t)0x212ee995, (q31_t)0x38179666, + (q31_t)0x2139edac, (q31_t)0x381da256, (q31_t)0x2144f2f3, (q31_t)0x3823ac1d, + (q31_t)0x214ff96a, (q31_t)0x3829b3b9, (q31_t)0x215b0110, (q31_t)0x382fb92a, + (q31_t)0x216609e3, (q31_t)0x3835bc71, (q31_t)0x217113e5, (q31_t)0x383bbd8e, + (q31_t)0x217c1f15, (q31_t)0x3841bc7f, (q31_t)0x21872b72, (q31_t)0x3847b946, + (q31_t)0x219238fb, (q31_t)0x384db3e0, (q31_t)0x219d47b1, (q31_t)0x3853ac4f, + (q31_t)0x21a85793, (q31_t)0x3859a292, (q31_t)0x21b368a0, (q31_t)0x385f96a9, + (q31_t)0x21be7ad8, (q31_t)0x38658894, (q31_t)0x21c98e3b, (q31_t)0x386b7852, + (q31_t)0x21d4a2c8, (q31_t)0x387165e3, (q31_t)0x21dfb87f, (q31_t)0x38775147, + (q31_t)0x21eacf5f, (q31_t)0x387d3a7e, (q31_t)0x21f5e768, (q31_t)0x38832187, + (q31_t)0x22010099, (q31_t)0x38890663, (q31_t)0x220c1af3, (q31_t)0x388ee910, + (q31_t)0x22173674, (q31_t)0x3894c98f, (q31_t)0x2222531c, (q31_t)0x389aa7e0, + (q31_t)0x222d70eb, (q31_t)0x38a08402, (q31_t)0x22388fe1, (q31_t)0x38a65df6, + (q31_t)0x2243affc, (q31_t)0x38ac35ba, (q31_t)0x224ed13d, (q31_t)0x38b20b4f, + (q31_t)0x2259f3a3, (q31_t)0x38b7deb4, (q31_t)0x2265172e, (q31_t)0x38bdafea, + (q31_t)0x22703bdc, (q31_t)0x38c37eef, (q31_t)0x227b61af, (q31_t)0x38c94bc4, + (q31_t)0x228688a4, (q31_t)0x38cf1669, (q31_t)0x2291b0bd, (q31_t)0x38d4dedd, + (q31_t)0x229cd9f8, (q31_t)0x38daa520, (q31_t)0x22a80456, (q31_t)0x38e06932, + (q31_t)0x22b32fd4, (q31_t)0x38e62b13, (q31_t)0x22be5c74, (q31_t)0x38ebeac2, + (q31_t)0x22c98a35, (q31_t)0x38f1a840, (q31_t)0x22d4b916, (q31_t)0x38f7638b, + (q31_t)0x22dfe917, (q31_t)0x38fd1ca4, (q31_t)0x22eb1a37, (q31_t)0x3902d38b, + (q31_t)0x22f64c77, (q31_t)0x3908883f, (q31_t)0x23017fd5, (q31_t)0x390e3ac0, + (q31_t)0x230cb451, (q31_t)0x3913eb0e, (q31_t)0x2317e9eb, (q31_t)0x39199929, + (q31_t)0x232320a2, (q31_t)0x391f4510, (q31_t)0x232e5876, (q31_t)0x3924eec3, + (q31_t)0x23399167, (q31_t)0x392a9642, (q31_t)0x2344cb73, (q31_t)0x39303b8e, + (q31_t)0x2350069b, (q31_t)0x3935dea4, (q31_t)0x235b42df, (q31_t)0x393b7f86, + (q31_t)0x2366803c, (q31_t)0x39411e33, (q31_t)0x2371beb5, (q31_t)0x3946baac, + (q31_t)0x237cfe47, (q31_t)0x394c54ee, (q31_t)0x23883ef2, (q31_t)0x3951ecfc, + (q31_t)0x239380b6, (q31_t)0x395782d3, (q31_t)0x239ec393, (q31_t)0x395d1675, + (q31_t)0x23aa0788, (q31_t)0x3962a7e0, (q31_t)0x23b54c95, (q31_t)0x39683715, + (q31_t)0x23c092b9, (q31_t)0x396dc414, (q31_t)0x23cbd9f4, (q31_t)0x39734edc, + (q31_t)0x23d72245, (q31_t)0x3978d76c, (q31_t)0x23e26bac, (q31_t)0x397e5dc6, + (q31_t)0x23edb628, (q31_t)0x3983e1e8, (q31_t)0x23f901ba, (q31_t)0x398963d2, + (q31_t)0x24044e60, (q31_t)0x398ee385, (q31_t)0x240f9c1a, (q31_t)0x399460ff, + (q31_t)0x241aeae8, (q31_t)0x3999dc42, (q31_t)0x24263ac9, (q31_t)0x399f554b, + (q31_t)0x24318bbe, (q31_t)0x39a4cc1c, (q31_t)0x243cddc4, (q31_t)0x39aa40b4, + (q31_t)0x244830dd, (q31_t)0x39afb313, (q31_t)0x24538507, (q31_t)0x39b52339, + (q31_t)0x245eda43, (q31_t)0x39ba9125, (q31_t)0x246a308f, (q31_t)0x39bffcd7, + (q31_t)0x247587eb, (q31_t)0x39c5664f, (q31_t)0x2480e057, (q31_t)0x39cacd8d, + (q31_t)0x248c39d3, (q31_t)0x39d03291, (q31_t)0x2497945d, (q31_t)0x39d5955a, + (q31_t)0x24a2eff6, (q31_t)0x39daf5e8, (q31_t)0x24ae4c9d, (q31_t)0x39e0543c, + (q31_t)0x24b9aa52, (q31_t)0x39e5b054, (q31_t)0x24c50914, (q31_t)0x39eb0a31, + (q31_t)0x24d068e2, (q31_t)0x39f061d2, (q31_t)0x24dbc9bd, (q31_t)0x39f5b737, + (q31_t)0x24e72ba4, (q31_t)0x39fb0a60, (q31_t)0x24f28e96, (q31_t)0x3a005b4d, + (q31_t)0x24fdf294, (q31_t)0x3a05a9fd, (q31_t)0x2509579b, (q31_t)0x3a0af671, + (q31_t)0x2514bdad, (q31_t)0x3a1040a8, (q31_t)0x252024c9, (q31_t)0x3a1588a2, + (q31_t)0x252b8cee, (q31_t)0x3a1ace5f, (q31_t)0x2536f61b, (q31_t)0x3a2011de, + (q31_t)0x25426051, (q31_t)0x3a25531f, (q31_t)0x254dcb8f, (q31_t)0x3a2a9223, + (q31_t)0x255937d5, (q31_t)0x3a2fcee8, (q31_t)0x2564a521, (q31_t)0x3a350970, + (q31_t)0x25701374, (q31_t)0x3a3a41b9, (q31_t)0x257b82cd, (q31_t)0x3a3f77c3, + (q31_t)0x2586f32c, (q31_t)0x3a44ab8e, (q31_t)0x25926490, (q31_t)0x3a49dd1a, + (q31_t)0x259dd6f9, (q31_t)0x3a4f0c67, (q31_t)0x25a94a67, (q31_t)0x3a543974, + (q31_t)0x25b4bed8, (q31_t)0x3a596442, (q31_t)0x25c0344d, (q31_t)0x3a5e8cd0, + (q31_t)0x25cbaac5, (q31_t)0x3a63b31d, (q31_t)0x25d72240, (q31_t)0x3a68d72b, + (q31_t)0x25e29abc, (q31_t)0x3a6df8f8, (q31_t)0x25ee143b, (q31_t)0x3a731884, + (q31_t)0x25f98ebb, (q31_t)0x3a7835cf, (q31_t)0x26050a3b, (q31_t)0x3a7d50da, + (q31_t)0x261086bc, (q31_t)0x3a8269a3, (q31_t)0x261c043d, (q31_t)0x3a87802a, + (q31_t)0x262782be, (q31_t)0x3a8c9470, (q31_t)0x2633023e, (q31_t)0x3a91a674, + (q31_t)0x263e82bc, (q31_t)0x3a96b636, (q31_t)0x264a0438, (q31_t)0x3a9bc3b6, + (q31_t)0x265586b3, (q31_t)0x3aa0cef3, (q31_t)0x26610a2a, (q31_t)0x3aa5d7ee, + (q31_t)0x266c8e9f, (q31_t)0x3aaadea6, (q31_t)0x26781410, (q31_t)0x3aafe31b, + (q31_t)0x26839a7c, (q31_t)0x3ab4e54c, (q31_t)0x268f21e5, (q31_t)0x3ab9e53a, + (q31_t)0x269aaa48, (q31_t)0x3abee2e5, (q31_t)0x26a633a6, (q31_t)0x3ac3de4c, + (q31_t)0x26b1bdff, (q31_t)0x3ac8d76f, (q31_t)0x26bd4951, (q31_t)0x3acdce4d, + (q31_t)0x26c8d59c, (q31_t)0x3ad2c2e8, (q31_t)0x26d462e1, (q31_t)0x3ad7b53d, + (q31_t)0x26dff11d, (q31_t)0x3adca54e, (q31_t)0x26eb8052, (q31_t)0x3ae1931a, + (q31_t)0x26f7107e, (q31_t)0x3ae67ea1, (q31_t)0x2702a1a1, (q31_t)0x3aeb67e3, + (q31_t)0x270e33bb, (q31_t)0x3af04edf, (q31_t)0x2719c6cb, (q31_t)0x3af53395, + (q31_t)0x27255ad1, (q31_t)0x3afa1605, (q31_t)0x2730efcc, (q31_t)0x3afef630, + (q31_t)0x273c85bc, (q31_t)0x3b03d414, (q31_t)0x27481ca1, (q31_t)0x3b08afb2, + (q31_t)0x2753b479, (q31_t)0x3b0d8909, (q31_t)0x275f4d45, (q31_t)0x3b126019, + (q31_t)0x276ae704, (q31_t)0x3b1734e2, (q31_t)0x277681b6, (q31_t)0x3b1c0764, + (q31_t)0x27821d59, (q31_t)0x3b20d79e, (q31_t)0x278db9ef, (q31_t)0x3b25a591, + (q31_t)0x27995776, (q31_t)0x3b2a713d, (q31_t)0x27a4f5ed, (q31_t)0x3b2f3aa0, + (q31_t)0x27b09555, (q31_t)0x3b3401bb, (q31_t)0x27bc35ad, (q31_t)0x3b38c68e, + (q31_t)0x27c7d6f4, (q31_t)0x3b3d8918, (q31_t)0x27d3792b, (q31_t)0x3b42495a, + (q31_t)0x27df1c50, (q31_t)0x3b470753, (q31_t)0x27eac063, (q31_t)0x3b4bc303, + (q31_t)0x27f66564, (q31_t)0x3b507c69, (q31_t)0x28020b52, (q31_t)0x3b553386, + (q31_t)0x280db22d, (q31_t)0x3b59e85a, (q31_t)0x281959f4, (q31_t)0x3b5e9ae4, + (q31_t)0x282502a7, (q31_t)0x3b634b23, (q31_t)0x2830ac45, (q31_t)0x3b67f919, + (q31_t)0x283c56cf, (q31_t)0x3b6ca4c4, (q31_t)0x28480243, (q31_t)0x3b714e25, + (q31_t)0x2853aea1, (q31_t)0x3b75f53c, (q31_t)0x285f5be9, (q31_t)0x3b7a9a07, + (q31_t)0x286b0a1a, (q31_t)0x3b7f3c87, (q31_t)0x2876b934, (q31_t)0x3b83dcbc, + (q31_t)0x28826936, (q31_t)0x3b887aa6, (q31_t)0x288e1a20, (q31_t)0x3b8d1644, + (q31_t)0x2899cbf1, (q31_t)0x3b91af97, (q31_t)0x28a57ea9, (q31_t)0x3b96469d, + (q31_t)0x28b13248, (q31_t)0x3b9adb57, (q31_t)0x28bce6cd, (q31_t)0x3b9f6dc5, + (q31_t)0x28c89c37, (q31_t)0x3ba3fde7, (q31_t)0x28d45286, (q31_t)0x3ba88bbc, + (q31_t)0x28e009ba, (q31_t)0x3bad1744, (q31_t)0x28ebc1d3, (q31_t)0x3bb1a080, + (q31_t)0x28f77acf, (q31_t)0x3bb6276e, (q31_t)0x290334af, (q31_t)0x3bbaac0e, + (q31_t)0x290eef71, (q31_t)0x3bbf2e62, (q31_t)0x291aab16, (q31_t)0x3bc3ae67, + (q31_t)0x2926679c, (q31_t)0x3bc82c1f, (q31_t)0x29322505, (q31_t)0x3bcca789, + (q31_t)0x293de34e, (q31_t)0x3bd120a4, (q31_t)0x2949a278, (q31_t)0x3bd59771, + (q31_t)0x29556282, (q31_t)0x3bda0bf0, (q31_t)0x2961236c, (q31_t)0x3bde7e20, + (q31_t)0x296ce535, (q31_t)0x3be2ee01, (q31_t)0x2978a7dd, (q31_t)0x3be75b93, + (q31_t)0x29846b63, (q31_t)0x3bebc6d5, (q31_t)0x29902fc7, (q31_t)0x3bf02fc9, + (q31_t)0x299bf509, (q31_t)0x3bf4966c, (q31_t)0x29a7bb28, (q31_t)0x3bf8fac0, + (q31_t)0x29b38223, (q31_t)0x3bfd5cc4, (q31_t)0x29bf49fa, (q31_t)0x3c01bc78, + (q31_t)0x29cb12ad, (q31_t)0x3c0619dc, (q31_t)0x29d6dc3b, (q31_t)0x3c0a74f0, + (q31_t)0x29e2a6a3, (q31_t)0x3c0ecdb2, (q31_t)0x29ee71e6, (q31_t)0x3c132424, + (q31_t)0x29fa3e03, (q31_t)0x3c177845, (q31_t)0x2a060af9, (q31_t)0x3c1bca16, + (q31_t)0x2a11d8c8, (q31_t)0x3c201994, (q31_t)0x2a1da770, (q31_t)0x3c2466c2, + (q31_t)0x2a2976ef, (q31_t)0x3c28b19e, (q31_t)0x2a354746, (q31_t)0x3c2cfa28, + (q31_t)0x2a411874, (q31_t)0x3c314060, (q31_t)0x2a4cea79, (q31_t)0x3c358446, + (q31_t)0x2a58bd54, (q31_t)0x3c39c5da, (q31_t)0x2a649105, (q31_t)0x3c3e051b, + (q31_t)0x2a70658a, (q31_t)0x3c42420a, (q31_t)0x2a7c3ae5, (q31_t)0x3c467ca6, + (q31_t)0x2a881114, (q31_t)0x3c4ab4ef, (q31_t)0x2a93e817, (q31_t)0x3c4eeae5, + (q31_t)0x2a9fbfed, (q31_t)0x3c531e88, (q31_t)0x2aab9896, (q31_t)0x3c574fd8, + (q31_t)0x2ab77212, (q31_t)0x3c5b7ed4, (q31_t)0x2ac34c60, (q31_t)0x3c5fab7c, + (q31_t)0x2acf277f, (q31_t)0x3c63d5d1, (q31_t)0x2adb0370, (q31_t)0x3c67fdd1, + (q31_t)0x2ae6e031, (q31_t)0x3c6c237e, (q31_t)0x2af2bdc3, (q31_t)0x3c7046d6, + (q31_t)0x2afe9c24, (q31_t)0x3c7467d9, (q31_t)0x2b0a7b54, (q31_t)0x3c788688, + (q31_t)0x2b165b54, (q31_t)0x3c7ca2e2, (q31_t)0x2b223c22, (q31_t)0x3c80bce7, + (q31_t)0x2b2e1dbe, (q31_t)0x3c84d496, (q31_t)0x2b3a0027, (q31_t)0x3c88e9f1, + (q31_t)0x2b45e35d, (q31_t)0x3c8cfcf6, (q31_t)0x2b51c760, (q31_t)0x3c910da5, + (q31_t)0x2b5dac2f, (q31_t)0x3c951bff, (q31_t)0x2b6991ca, (q31_t)0x3c992803, + (q31_t)0x2b75782f, (q31_t)0x3c9d31b0, (q31_t)0x2b815f60, (q31_t)0x3ca13908, + (q31_t)0x2b8d475b, (q31_t)0x3ca53e09, (q31_t)0x2b99301f, (q31_t)0x3ca940b3, + (q31_t)0x2ba519ad, (q31_t)0x3cad4107, (q31_t)0x2bb10404, (q31_t)0x3cb13f04, + (q31_t)0x2bbcef23, (q31_t)0x3cb53aaa, (q31_t)0x2bc8db0b, (q31_t)0x3cb933f9, + (q31_t)0x2bd4c7ba, (q31_t)0x3cbd2af0, (q31_t)0x2be0b52f, (q31_t)0x3cc11f90, + (q31_t)0x2beca36c, (q31_t)0x3cc511d9, (q31_t)0x2bf8926f, (q31_t)0x3cc901c9, + (q31_t)0x2c048237, (q31_t)0x3cccef62, (q31_t)0x2c1072c4, (q31_t)0x3cd0daa2, + (q31_t)0x2c1c6417, (q31_t)0x3cd4c38b, (q31_t)0x2c28562d, (q31_t)0x3cd8aa1b, + (q31_t)0x2c344908, (q31_t)0x3cdc8e52, (q31_t)0x2c403ca5, (q31_t)0x3ce07031, + (q31_t)0x2c4c3106, (q31_t)0x3ce44fb7, (q31_t)0x2c582629, (q31_t)0x3ce82ce4, + (q31_t)0x2c641c0e, (q31_t)0x3cec07b8, (q31_t)0x2c7012b5, (q31_t)0x3cefe032, + (q31_t)0x2c7c0a1d, (q31_t)0x3cf3b653, (q31_t)0x2c880245, (q31_t)0x3cf78a1b, + (q31_t)0x2c93fb2e, (q31_t)0x3cfb5b89, (q31_t)0x2c9ff4d6, (q31_t)0x3cff2a9d, + (q31_t)0x2cabef3d, (q31_t)0x3d02f757, (q31_t)0x2cb7ea63, (q31_t)0x3d06c1b6, + (q31_t)0x2cc3e648, (q31_t)0x3d0a89bc, (q31_t)0x2ccfe2ea, (q31_t)0x3d0e4f67, + (q31_t)0x2cdbe04a, (q31_t)0x3d1212b7, (q31_t)0x2ce7de66, (q31_t)0x3d15d3ad, + (q31_t)0x2cf3dd3f, (q31_t)0x3d199248, (q31_t)0x2cffdcd4, (q31_t)0x3d1d4e88, + (q31_t)0x2d0bdd25, (q31_t)0x3d21086c, (q31_t)0x2d17de31, (q31_t)0x3d24bff6, + (q31_t)0x2d23dff7, (q31_t)0x3d287523, (q31_t)0x2d2fe277, (q31_t)0x3d2c27f6, + (q31_t)0x2d3be5b1, (q31_t)0x3d2fd86c, (q31_t)0x2d47e9a5, (q31_t)0x3d338687, + (q31_t)0x2d53ee51, (q31_t)0x3d373245, (q31_t)0x2d5ff3b5, (q31_t)0x3d3adba7, + (q31_t)0x2d6bf9d1, (q31_t)0x3d3e82ae, (q31_t)0x2d7800a5, (q31_t)0x3d422757, + (q31_t)0x2d84082f, (q31_t)0x3d45c9a4, (q31_t)0x2d901070, (q31_t)0x3d496994, + (q31_t)0x2d9c1967, (q31_t)0x3d4d0728, (q31_t)0x2da82313, (q31_t)0x3d50a25e, + (q31_t)0x2db42d74, (q31_t)0x3d543b37, (q31_t)0x2dc0388a, (q31_t)0x3d57d1b3, + (q31_t)0x2dcc4454, (q31_t)0x3d5b65d2, (q31_t)0x2dd850d2, (q31_t)0x3d5ef793, + (q31_t)0x2de45e03, (q31_t)0x3d6286f6, (q31_t)0x2df06be6, (q31_t)0x3d6613fb, + (q31_t)0x2dfc7a7c, (q31_t)0x3d699ea3, (q31_t)0x2e0889c4, (q31_t)0x3d6d26ec, + (q31_t)0x2e1499bd, (q31_t)0x3d70acd7, (q31_t)0x2e20aa67, (q31_t)0x3d743064, + (q31_t)0x2e2cbbc1, (q31_t)0x3d77b192, (q31_t)0x2e38cdcb, (q31_t)0x3d7b3061, + (q31_t)0x2e44e084, (q31_t)0x3d7eacd2, (q31_t)0x2e50f3ed, (q31_t)0x3d8226e4, + (q31_t)0x2e5d0804, (q31_t)0x3d859e96, (q31_t)0x2e691cc9, (q31_t)0x3d8913ea, + (q31_t)0x2e75323c, (q31_t)0x3d8c86de, (q31_t)0x2e81485c, (q31_t)0x3d8ff772, + (q31_t)0x2e8d5f29, (q31_t)0x3d9365a8, (q31_t)0x2e9976a1, (q31_t)0x3d96d17d, + (q31_t)0x2ea58ec6, (q31_t)0x3d9a3af2, (q31_t)0x2eb1a796, (q31_t)0x3d9da208, + (q31_t)0x2ebdc110, (q31_t)0x3da106bd, (q31_t)0x2ec9db35, (q31_t)0x3da46912, + (q31_t)0x2ed5f604, (q31_t)0x3da7c907, (q31_t)0x2ee2117c, (q31_t)0x3dab269b, + (q31_t)0x2eee2d9d, (q31_t)0x3dae81cf, (q31_t)0x2efa4a67, (q31_t)0x3db1daa2, + (q31_t)0x2f0667d9, (q31_t)0x3db53113, (q31_t)0x2f1285f2, (q31_t)0x3db88524, + (q31_t)0x2f1ea4b2, (q31_t)0x3dbbd6d4, (q31_t)0x2f2ac419, (q31_t)0x3dbf2622, + (q31_t)0x2f36e426, (q31_t)0x3dc2730f, (q31_t)0x2f4304d8, (q31_t)0x3dc5bd9b, + (q31_t)0x2f4f2630, (q31_t)0x3dc905c5, (q31_t)0x2f5b482d, (q31_t)0x3dcc4b8d, + (q31_t)0x2f676ace, (q31_t)0x3dcf8ef3, (q31_t)0x2f738e12, (q31_t)0x3dd2cff7, + (q31_t)0x2f7fb1fa, (q31_t)0x3dd60e99, (q31_t)0x2f8bd685, (q31_t)0x3dd94ad8, + (q31_t)0x2f97fbb2, (q31_t)0x3ddc84b5, (q31_t)0x2fa42181, (q31_t)0x3ddfbc30, + (q31_t)0x2fb047f2, (q31_t)0x3de2f148, (q31_t)0x2fbc6f03, (q31_t)0x3de623fd, + (q31_t)0x2fc896b5, (q31_t)0x3de9544f, (q31_t)0x2fd4bf08, (q31_t)0x3dec823e, + (q31_t)0x2fe0e7f9, (q31_t)0x3defadca, (q31_t)0x2fed118a, (q31_t)0x3df2d6f3, + (q31_t)0x2ff93bba, (q31_t)0x3df5fdb8, (q31_t)0x30056687, (q31_t)0x3df9221a, + (q31_t)0x301191f3, (q31_t)0x3dfc4418, (q31_t)0x301dbdfb, (q31_t)0x3dff63b2, + (q31_t)0x3029eaa1, (q31_t)0x3e0280e9, (q31_t)0x303617e2, (q31_t)0x3e059bbb, + (q31_t)0x304245c0, (q31_t)0x3e08b42a, (q31_t)0x304e7438, (q31_t)0x3e0bca34, + (q31_t)0x305aa34c, (q31_t)0x3e0eddd9, (q31_t)0x3066d2fa, (q31_t)0x3e11ef1b, + (q31_t)0x30730342, (q31_t)0x3e14fdf7, (q31_t)0x307f3424, (q31_t)0x3e180a6f, + (q31_t)0x308b659f, (q31_t)0x3e1b1482, (q31_t)0x309797b2, (q31_t)0x3e1e1c30, + (q31_t)0x30a3ca5d, (q31_t)0x3e212179, (q31_t)0x30affda0, (q31_t)0x3e24245d, + (q31_t)0x30bc317a, (q31_t)0x3e2724db, (q31_t)0x30c865ea, (q31_t)0x3e2a22f4, + (q31_t)0x30d49af1, (q31_t)0x3e2d1ea8, (q31_t)0x30e0d08d, (q31_t)0x3e3017f6, + (q31_t)0x30ed06bf, (q31_t)0x3e330ede, (q31_t)0x30f93d86, (q31_t)0x3e360360, + (q31_t)0x310574e0, (q31_t)0x3e38f57c, (q31_t)0x3111accf, (q31_t)0x3e3be532, + (q31_t)0x311de551, (q31_t)0x3e3ed282, (q31_t)0x312a1e66, (q31_t)0x3e41bd6c, + (q31_t)0x3136580d, (q31_t)0x3e44a5ef, (q31_t)0x31429247, (q31_t)0x3e478c0b, + (q31_t)0x314ecd11, (q31_t)0x3e4a6fc1, (q31_t)0x315b086d, (q31_t)0x3e4d5110, + (q31_t)0x31674459, (q31_t)0x3e502ff9, (q31_t)0x317380d6, (q31_t)0x3e530c7a, + (q31_t)0x317fbde2, (q31_t)0x3e55e694, (q31_t)0x318bfb7d, (q31_t)0x3e58be47, + (q31_t)0x319839a6, (q31_t)0x3e5b9392, (q31_t)0x31a4785e, (q31_t)0x3e5e6676, + (q31_t)0x31b0b7a4, (q31_t)0x3e6136f3, (q31_t)0x31bcf777, (q31_t)0x3e640507, + (q31_t)0x31c937d6, (q31_t)0x3e66d0b4, (q31_t)0x31d578c2, (q31_t)0x3e6999fa, + (q31_t)0x31e1ba3a, (q31_t)0x3e6c60d7, (q31_t)0x31edfc3d, (q31_t)0x3e6f254c, + (q31_t)0x31fa3ecb, (q31_t)0x3e71e759, (q31_t)0x320681e3, (q31_t)0x3e74a6fd, + (q31_t)0x3212c585, (q31_t)0x3e77643a, (q31_t)0x321f09b1, (q31_t)0x3e7a1f0d, + (q31_t)0x322b4e66, (q31_t)0x3e7cd778, (q31_t)0x323793a3, (q31_t)0x3e7f8d7b, + (q31_t)0x3243d968, (q31_t)0x3e824114, (q31_t)0x32501fb5, (q31_t)0x3e84f245, + (q31_t)0x325c6688, (q31_t)0x3e87a10c, (q31_t)0x3268ade3, (q31_t)0x3e8a4d6a, + (q31_t)0x3274f5c3, (q31_t)0x3e8cf75f, (q31_t)0x32813e2a, (q31_t)0x3e8f9eeb, + (q31_t)0x328d8715, (q31_t)0x3e92440d, (q31_t)0x3299d085, (q31_t)0x3e94e6c6, + (q31_t)0x32a61a7a, (q31_t)0x3e978715, (q31_t)0x32b264f2, (q31_t)0x3e9a24fb, + (q31_t)0x32beafed, (q31_t)0x3e9cc076, (q31_t)0x32cafb6b, (q31_t)0x3e9f5988, + (q31_t)0x32d7476c, (q31_t)0x3ea1f02f, (q31_t)0x32e393ef, (q31_t)0x3ea4846c, + (q31_t)0x32efe0f2, (q31_t)0x3ea7163f, (q31_t)0x32fc2e77, (q31_t)0x3ea9a5a8, + (q31_t)0x33087c7d, (q31_t)0x3eac32a6, (q31_t)0x3314cb02, (q31_t)0x3eaebd3a, + (q31_t)0x33211a07, (q31_t)0x3eb14563, (q31_t)0x332d698a, (q31_t)0x3eb3cb21, + (q31_t)0x3339b98d, (q31_t)0x3eb64e75, (q31_t)0x33460a0d, (q31_t)0x3eb8cf5d, + (q31_t)0x33525b0b, (q31_t)0x3ebb4ddb, (q31_t)0x335eac86, (q31_t)0x3ebdc9ed, + (q31_t)0x336afe7e, (q31_t)0x3ec04394, (q31_t)0x337750f2, (q31_t)0x3ec2bad0, + (q31_t)0x3383a3e2, (q31_t)0x3ec52fa0, (q31_t)0x338ff74d, (q31_t)0x3ec7a205, + (q31_t)0x339c4b32, (q31_t)0x3eca11fe, (q31_t)0x33a89f92, (q31_t)0x3ecc7f8b, + (q31_t)0x33b4f46c, (q31_t)0x3eceeaad, (q31_t)0x33c149bf, (q31_t)0x3ed15363, + (q31_t)0x33cd9f8b, (q31_t)0x3ed3b9ad, (q31_t)0x33d9f5cf, (q31_t)0x3ed61d8a, + (q31_t)0x33e64c8c, (q31_t)0x3ed87efc, (q31_t)0x33f2a3bf, (q31_t)0x3edade01, + (q31_t)0x33fefb6a, (q31_t)0x3edd3a9a, (q31_t)0x340b538b, (q31_t)0x3edf94c7, + (q31_t)0x3417ac22, (q31_t)0x3ee1ec87, (q31_t)0x3424052f, (q31_t)0x3ee441da, + (q31_t)0x34305eb0, (q31_t)0x3ee694c1, (q31_t)0x343cb8a7, (q31_t)0x3ee8e53a, + (q31_t)0x34491311, (q31_t)0x3eeb3347, (q31_t)0x34556def, (q31_t)0x3eed7ee7, + (q31_t)0x3461c940, (q31_t)0x3eefc81a, (q31_t)0x346e2504, (q31_t)0x3ef20ee0, + (q31_t)0x347a8139, (q31_t)0x3ef45338, (q31_t)0x3486dde1, (q31_t)0x3ef69523, + (q31_t)0x34933afa, (q31_t)0x3ef8d4a1, (q31_t)0x349f9884, (q31_t)0x3efb11b1, + (q31_t)0x34abf67e, (q31_t)0x3efd4c54, (q31_t)0x34b854e7, (q31_t)0x3eff8489, + (q31_t)0x34c4b3c0, (q31_t)0x3f01ba50, (q31_t)0x34d11308, (q31_t)0x3f03eda9, + (q31_t)0x34dd72be, (q31_t)0x3f061e95, (q31_t)0x34e9d2e3, (q31_t)0x3f084d12, + (q31_t)0x34f63374, (q31_t)0x3f0a7921, (q31_t)0x35029473, (q31_t)0x3f0ca2c2, + (q31_t)0x350ef5de, (q31_t)0x3f0ec9f5, (q31_t)0x351b57b5, (q31_t)0x3f10eeb9, + (q31_t)0x3527b9f7, (q31_t)0x3f13110f, (q31_t)0x35341ca5, (q31_t)0x3f1530f7, + (q31_t)0x35407fbd, (q31_t)0x3f174e70, (q31_t)0x354ce33f, (q31_t)0x3f19697a, + (q31_t)0x3559472b, (q31_t)0x3f1b8215, (q31_t)0x3565ab80, (q31_t)0x3f1d9842, + (q31_t)0x3572103d, (q31_t)0x3f1fabff, (q31_t)0x357e7563, (q31_t)0x3f21bd4e, + (q31_t)0x358adaf0, (q31_t)0x3f23cc2e, (q31_t)0x359740e5, (q31_t)0x3f25d89e, + (q31_t)0x35a3a740, (q31_t)0x3f27e29f, (q31_t)0x35b00e02, (q31_t)0x3f29ea31, + (q31_t)0x35bc7529, (q31_t)0x3f2bef53, (q31_t)0x35c8dcb6, (q31_t)0x3f2df206, + (q31_t)0x35d544a7, (q31_t)0x3f2ff24a, (q31_t)0x35e1acfd, (q31_t)0x3f31f01d, + (q31_t)0x35ee15b7, (q31_t)0x3f33eb81, (q31_t)0x35fa7ed4, (q31_t)0x3f35e476, + (q31_t)0x3606e854, (q31_t)0x3f37dafa, (q31_t)0x36135237, (q31_t)0x3f39cf0e, + (q31_t)0x361fbc7b, (q31_t)0x3f3bc0b3, (q31_t)0x362c2721, (q31_t)0x3f3dafe7, + (q31_t)0x36389228, (q31_t)0x3f3f9cab, (q31_t)0x3644fd8f, (q31_t)0x3f4186ff, + (q31_t)0x36516956, (q31_t)0x3f436ee3, (q31_t)0x365dd57d, (q31_t)0x3f455456, + (q31_t)0x366a4203, (q31_t)0x3f473759, (q31_t)0x3676aee8, (q31_t)0x3f4917eb, + (q31_t)0x36831c2b, (q31_t)0x3f4af60d, (q31_t)0x368f89cb, (q31_t)0x3f4cd1be, + (q31_t)0x369bf7c9, (q31_t)0x3f4eaafe, (q31_t)0x36a86623, (q31_t)0x3f5081cd, + (q31_t)0x36b4d4d9, (q31_t)0x3f52562c, (q31_t)0x36c143ec, (q31_t)0x3f54281a, + (q31_t)0x36cdb359, (q31_t)0x3f55f796, (q31_t)0x36da2321, (q31_t)0x3f57c4a2, + (q31_t)0x36e69344, (q31_t)0x3f598f3c, (q31_t)0x36f303c0, (q31_t)0x3f5b5765, + (q31_t)0x36ff7496, (q31_t)0x3f5d1d1d, (q31_t)0x370be5c4, (q31_t)0x3f5ee063, + (q31_t)0x3718574b, (q31_t)0x3f60a138, (q31_t)0x3724c92a, (q31_t)0x3f625f9b, + (q31_t)0x37313b60, (q31_t)0x3f641b8d, (q31_t)0x373daded, (q31_t)0x3f65d50d, + (q31_t)0x374a20d0, (q31_t)0x3f678c1c, (q31_t)0x3756940a, (q31_t)0x3f6940b8, + (q31_t)0x37630799, (q31_t)0x3f6af2e3, (q31_t)0x376f7b7d, (q31_t)0x3f6ca29c, + (q31_t)0x377befb5, (q31_t)0x3f6e4fe3, (q31_t)0x37886442, (q31_t)0x3f6ffab8, + (q31_t)0x3794d922, (q31_t)0x3f71a31b, (q31_t)0x37a14e55, (q31_t)0x3f73490b, + (q31_t)0x37adc3db, (q31_t)0x3f74ec8a, (q31_t)0x37ba39b3, (q31_t)0x3f768d96, + (q31_t)0x37c6afdc, (q31_t)0x3f782c30, (q31_t)0x37d32657, (q31_t)0x3f79c857, + (q31_t)0x37df9d22, (q31_t)0x3f7b620c, (q31_t)0x37ec143e, (q31_t)0x3f7cf94e, + (q31_t)0x37f88ba9, (q31_t)0x3f7e8e1e, (q31_t)0x38050364, (q31_t)0x3f80207b, + (q31_t)0x38117b6d, (q31_t)0x3f81b065, (q31_t)0x381df3c5, (q31_t)0x3f833ddd, + (q31_t)0x382a6c6a, (q31_t)0x3f84c8e2, (q31_t)0x3836e55d, (q31_t)0x3f865174, + (q31_t)0x38435e9d, (q31_t)0x3f87d792, (q31_t)0x384fd829, (q31_t)0x3f895b3e, + (q31_t)0x385c5201, (q31_t)0x3f8adc77, (q31_t)0x3868cc24, (q31_t)0x3f8c5b3d, + (q31_t)0x38754692, (q31_t)0x3f8dd78f, (q31_t)0x3881c14b, (q31_t)0x3f8f516e, + (q31_t)0x388e3c4d, (q31_t)0x3f90c8da, (q31_t)0x389ab799, (q31_t)0x3f923dd2, + (q31_t)0x38a7332e, (q31_t)0x3f93b058, (q31_t)0x38b3af0c, (q31_t)0x3f952069, + (q31_t)0x38c02b31, (q31_t)0x3f968e07, (q31_t)0x38cca79e, (q31_t)0x3f97f932, + (q31_t)0x38d92452, (q31_t)0x3f9961e8, (q31_t)0x38e5a14d, (q31_t)0x3f9ac82c, + (q31_t)0x38f21e8e, (q31_t)0x3f9c2bfb, (q31_t)0x38fe9c15, (q31_t)0x3f9d8d56, + (q31_t)0x390b19e0, (q31_t)0x3f9eec3e, (q31_t)0x391797f0, (q31_t)0x3fa048b2, + (q31_t)0x39241645, (q31_t)0x3fa1a2b2, (q31_t)0x393094dd, (q31_t)0x3fa2fa3d, + (q31_t)0x393d13b8, (q31_t)0x3fa44f55, (q31_t)0x394992d7, (q31_t)0x3fa5a1f9, + (q31_t)0x39561237, (q31_t)0x3fa6f228, (q31_t)0x396291d9, (q31_t)0x3fa83fe3, + (q31_t)0x396f11bc, (q31_t)0x3fa98b2a, (q31_t)0x397b91e1, (q31_t)0x3faad3fd, + (q31_t)0x39881245, (q31_t)0x3fac1a5b, (q31_t)0x399492ea, (q31_t)0x3fad5e45, + (q31_t)0x39a113cd, (q31_t)0x3fae9fbb, (q31_t)0x39ad94f0, (q31_t)0x3fafdebb, + (q31_t)0x39ba1651, (q31_t)0x3fb11b48, (q31_t)0x39c697f0, (q31_t)0x3fb2555f, + (q31_t)0x39d319cc, (q31_t)0x3fb38d02, (q31_t)0x39df9be6, (q31_t)0x3fb4c231, + (q31_t)0x39ec1e3b, (q31_t)0x3fb5f4ea, (q31_t)0x39f8a0cd, (q31_t)0x3fb7252f, + (q31_t)0x3a05239a, (q31_t)0x3fb852ff, (q31_t)0x3a11a6a3, (q31_t)0x3fb97e5a, + (q31_t)0x3a1e29e5, (q31_t)0x3fbaa740, (q31_t)0x3a2aad62, (q31_t)0x3fbbcdb1, + (q31_t)0x3a373119, (q31_t)0x3fbcf1ad, (q31_t)0x3a43b508, (q31_t)0x3fbe1334, + (q31_t)0x3a503930, (q31_t)0x3fbf3246, (q31_t)0x3a5cbd91, (q31_t)0x3fc04ee3, + (q31_t)0x3a694229, (q31_t)0x3fc1690a, (q31_t)0x3a75c6f8, (q31_t)0x3fc280bc, + (q31_t)0x3a824bfd, (q31_t)0x3fc395f9, (q31_t)0x3a8ed139, (q31_t)0x3fc4a8c1, + (q31_t)0x3a9b56ab, (q31_t)0x3fc5b913, (q31_t)0x3aa7dc52, (q31_t)0x3fc6c6f0, + (q31_t)0x3ab4622d, (q31_t)0x3fc7d258, (q31_t)0x3ac0e83d, (q31_t)0x3fc8db4a, + (q31_t)0x3acd6e81, (q31_t)0x3fc9e1c6, (q31_t)0x3ad9f4f8, (q31_t)0x3fcae5cd, + (q31_t)0x3ae67ba2, (q31_t)0x3fcbe75e, (q31_t)0x3af3027e, (q31_t)0x3fcce67a, + (q31_t)0x3aff898c, (q31_t)0x3fcde320, (q31_t)0x3b0c10cb, (q31_t)0x3fcedd50, + (q31_t)0x3b18983b, (q31_t)0x3fcfd50b, (q31_t)0x3b251fdc, (q31_t)0x3fd0ca4f, + (q31_t)0x3b31a7ac, (q31_t)0x3fd1bd1e, (q31_t)0x3b3e2fac, (q31_t)0x3fd2ad77, + (q31_t)0x3b4ab7db, (q31_t)0x3fd39b5a, (q31_t)0x3b574039, (q31_t)0x3fd486c7, + (q31_t)0x3b63c8c4, (q31_t)0x3fd56fbe, (q31_t)0x3b70517d, (q31_t)0x3fd6563f, + (q31_t)0x3b7cda63, (q31_t)0x3fd73a4a, (q31_t)0x3b896375, (q31_t)0x3fd81bdf, + (q31_t)0x3b95ecb4, (q31_t)0x3fd8fafe, (q31_t)0x3ba2761e, (q31_t)0x3fd9d7a7, + (q31_t)0x3baeffb3, (q31_t)0x3fdab1d9, (q31_t)0x3bbb8973, (q31_t)0x3fdb8996, + (q31_t)0x3bc8135c, (q31_t)0x3fdc5edc, (q31_t)0x3bd49d70, (q31_t)0x3fdd31ac, + (q31_t)0x3be127ac, (q31_t)0x3fde0205, (q31_t)0x3bedb212, (q31_t)0x3fdecfe8, + (q31_t)0x3bfa3c9f, (q31_t)0x3fdf9b55, (q31_t)0x3c06c754, (q31_t)0x3fe0644b, + (q31_t)0x3c135231, (q31_t)0x3fe12acb, (q31_t)0x3c1fdd34, (q31_t)0x3fe1eed5, + (q31_t)0x3c2c685d, (q31_t)0x3fe2b067, (q31_t)0x3c38f3ac, (q31_t)0x3fe36f84, + (q31_t)0x3c457f21, (q31_t)0x3fe42c2a, (q31_t)0x3c520aba, (q31_t)0x3fe4e659, + (q31_t)0x3c5e9678, (q31_t)0x3fe59e12, (q31_t)0x3c6b2259, (q31_t)0x3fe65354, + (q31_t)0x3c77ae5e, (q31_t)0x3fe7061f, (q31_t)0x3c843a85, (q31_t)0x3fe7b674, + (q31_t)0x3c90c6cf, (q31_t)0x3fe86452, (q31_t)0x3c9d533b, (q31_t)0x3fe90fb9, + (q31_t)0x3ca9dfc8, (q31_t)0x3fe9b8a9, (q31_t)0x3cb66c77, (q31_t)0x3fea5f23, + (q31_t)0x3cc2f945, (q31_t)0x3feb0326, (q31_t)0x3ccf8634, (q31_t)0x3feba4b2, + (q31_t)0x3cdc1342, (q31_t)0x3fec43c7, (q31_t)0x3ce8a06f, (q31_t)0x3fece065, + (q31_t)0x3cf52dbb, (q31_t)0x3fed7a8c, (q31_t)0x3d01bb24, (q31_t)0x3fee123d, + (q31_t)0x3d0e48ab, (q31_t)0x3feea776, (q31_t)0x3d1ad650, (q31_t)0x3fef3a39, + (q31_t)0x3d276410, (q31_t)0x3fefca84, (q31_t)0x3d33f1ed, (q31_t)0x3ff05858, + (q31_t)0x3d407fe6, (q31_t)0x3ff0e3b6, (q31_t)0x3d4d0df9, (q31_t)0x3ff16c9c, + (q31_t)0x3d599c28, (q31_t)0x3ff1f30b, (q31_t)0x3d662a70, (q31_t)0x3ff27703, + (q31_t)0x3d72b8d2, (q31_t)0x3ff2f884, (q31_t)0x3d7f474d, (q31_t)0x3ff3778e, + (q31_t)0x3d8bd5e1, (q31_t)0x3ff3f420, (q31_t)0x3d98648d, (q31_t)0x3ff46e3c, + (q31_t)0x3da4f351, (q31_t)0x3ff4e5e0, (q31_t)0x3db1822c, (q31_t)0x3ff55b0d, + (q31_t)0x3dbe111e, (q31_t)0x3ff5cdc3, (q31_t)0x3dcaa027, (q31_t)0x3ff63e01, + (q31_t)0x3dd72f45, (q31_t)0x3ff6abc8, (q31_t)0x3de3be78, (q31_t)0x3ff71718, + (q31_t)0x3df04dc0, (q31_t)0x3ff77ff1, (q31_t)0x3dfcdd1d, (q31_t)0x3ff7e652, + (q31_t)0x3e096c8d, (q31_t)0x3ff84a3c, (q31_t)0x3e15fc11, (q31_t)0x3ff8abae, + (q31_t)0x3e228ba7, (q31_t)0x3ff90aaa, (q31_t)0x3e2f1b50, (q31_t)0x3ff9672d, + (q31_t)0x3e3bab0b, (q31_t)0x3ff9c13a, (q31_t)0x3e483ad8, (q31_t)0x3ffa18cf, + (q31_t)0x3e54cab5, (q31_t)0x3ffa6dec, (q31_t)0x3e615aa3, (q31_t)0x3ffac092, + (q31_t)0x3e6deaa1, (q31_t)0x3ffb10c1, (q31_t)0x3e7a7aae, (q31_t)0x3ffb5e78, + (q31_t)0x3e870aca, (q31_t)0x3ffba9b8, (q31_t)0x3e939af5, (q31_t)0x3ffbf280, + (q31_t)0x3ea02b2e, (q31_t)0x3ffc38d1, (q31_t)0x3eacbb74, (q31_t)0x3ffc7caa, + (q31_t)0x3eb94bc8, (q31_t)0x3ffcbe0c, (q31_t)0x3ec5dc28, (q31_t)0x3ffcfcf6, + (q31_t)0x3ed26c94, (q31_t)0x3ffd3969, (q31_t)0x3edefd0c, (q31_t)0x3ffd7364, + (q31_t)0x3eeb8d8f, (q31_t)0x3ffdaae7, (q31_t)0x3ef81e1d, (q31_t)0x3ffddff3, + (q31_t)0x3f04aeb5, (q31_t)0x3ffe1288, (q31_t)0x3f113f56, (q31_t)0x3ffe42a4, + (q31_t)0x3f1dd001, (q31_t)0x3ffe704a, (q31_t)0x3f2a60b4, (q31_t)0x3ffe9b77, + (q31_t)0x3f36f170, (q31_t)0x3ffec42d, (q31_t)0x3f438234, (q31_t)0x3ffeea6c, + (q31_t)0x3f5012fe, (q31_t)0x3fff0e32, (q31_t)0x3f5ca3d0, (q31_t)0x3fff2f82, + (q31_t)0x3f6934a8, (q31_t)0x3fff4e59, (q31_t)0x3f75c585, (q31_t)0x3fff6ab9, + (q31_t)0x3f825668, (q31_t)0x3fff84a1, (q31_t)0x3f8ee750, (q31_t)0x3fff9c12, + (q31_t)0x3f9b783c, (q31_t)0x3fffb10b, (q31_t)0x3fa8092c, (q31_t)0x3fffc38c, + (q31_t)0x3fb49a1f, (q31_t)0x3fffd396, (q31_t)0x3fc12b16, (q31_t)0x3fffe128, + (q31_t)0x3fcdbc0f, (q31_t)0x3fffec43, (q31_t)0x3fda4d09, (q31_t)0x3ffff4e6, + (q31_t)0x3fe6de05, (q31_t)0x3ffffb11, (q31_t)0x3ff36f02, (q31_t)0x3ffffec4, +}; + + +/** + @par + Generation of realCoefBQ31 array: + @par + n = 4096 +
for (i = 0; i < n; i++)
+  {
+     pBTable[2 * i]     = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+     pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  } 
+ @par + Convert to fixed point Q31 format + round(pBTable[i] * pow(2, 31)) + */ + +const q31_t realCoefBQ31[8192] = { + (q31_t)0x40000000, (q31_t)0x40000000, (q31_t)0x400c90fe, (q31_t)0x3ffffec4, + (q31_t)0x401921fb, (q31_t)0x3ffffb11, (q31_t)0x4025b2f7, (q31_t)0x3ffff4e6, + (q31_t)0x403243f1, (q31_t)0x3fffec43, (q31_t)0x403ed4ea, (q31_t)0x3fffe128, + (q31_t)0x404b65e1, (q31_t)0x3fffd396, (q31_t)0x4057f6d4, (q31_t)0x3fffc38c, + (q31_t)0x406487c4, (q31_t)0x3fffb10b, (q31_t)0x407118b0, (q31_t)0x3fff9c12, + (q31_t)0x407da998, (q31_t)0x3fff84a1, (q31_t)0x408a3a7b, (q31_t)0x3fff6ab9, + (q31_t)0x4096cb58, (q31_t)0x3fff4e59, (q31_t)0x40a35c30, (q31_t)0x3fff2f82, + (q31_t)0x40afed02, (q31_t)0x3fff0e32, (q31_t)0x40bc7dcc, (q31_t)0x3ffeea6c, + (q31_t)0x40c90e90, (q31_t)0x3ffec42d, (q31_t)0x40d59f4c, (q31_t)0x3ffe9b77, + (q31_t)0x40e22fff, (q31_t)0x3ffe704a, (q31_t)0x40eec0aa, (q31_t)0x3ffe42a4, + (q31_t)0x40fb514b, (q31_t)0x3ffe1288, (q31_t)0x4107e1e3, (q31_t)0x3ffddff3, + (q31_t)0x41147271, (q31_t)0x3ffdaae7, (q31_t)0x412102f4, (q31_t)0x3ffd7364, + (q31_t)0x412d936c, (q31_t)0x3ffd3969, (q31_t)0x413a23d8, (q31_t)0x3ffcfcf6, + (q31_t)0x4146b438, (q31_t)0x3ffcbe0c, (q31_t)0x4153448c, (q31_t)0x3ffc7caa, + (q31_t)0x415fd4d2, (q31_t)0x3ffc38d1, (q31_t)0x416c650b, (q31_t)0x3ffbf280, + (q31_t)0x4178f536, (q31_t)0x3ffba9b8, (q31_t)0x41858552, (q31_t)0x3ffb5e78, + (q31_t)0x4192155f, (q31_t)0x3ffb10c1, (q31_t)0x419ea55d, (q31_t)0x3ffac092, + (q31_t)0x41ab354b, (q31_t)0x3ffa6dec, (q31_t)0x41b7c528, (q31_t)0x3ffa18cf, + (q31_t)0x41c454f5, (q31_t)0x3ff9c13a, (q31_t)0x41d0e4b0, (q31_t)0x3ff9672d, + (q31_t)0x41dd7459, (q31_t)0x3ff90aaa, (q31_t)0x41ea03ef, (q31_t)0x3ff8abae, + (q31_t)0x41f69373, (q31_t)0x3ff84a3c, (q31_t)0x420322e3, (q31_t)0x3ff7e652, + (q31_t)0x420fb240, (q31_t)0x3ff77ff1, (q31_t)0x421c4188, (q31_t)0x3ff71718, + (q31_t)0x4228d0bb, (q31_t)0x3ff6abc8, (q31_t)0x42355fd9, (q31_t)0x3ff63e01, + (q31_t)0x4241eee2, (q31_t)0x3ff5cdc3, (q31_t)0x424e7dd4, (q31_t)0x3ff55b0d, + (q31_t)0x425b0caf, (q31_t)0x3ff4e5e0, (q31_t)0x42679b73, (q31_t)0x3ff46e3c, + (q31_t)0x42742a1f, (q31_t)0x3ff3f420, (q31_t)0x4280b8b3, (q31_t)0x3ff3778e, + (q31_t)0x428d472e, (q31_t)0x3ff2f884, (q31_t)0x4299d590, (q31_t)0x3ff27703, + (q31_t)0x42a663d8, (q31_t)0x3ff1f30b, (q31_t)0x42b2f207, (q31_t)0x3ff16c9c, + (q31_t)0x42bf801a, (q31_t)0x3ff0e3b6, (q31_t)0x42cc0e13, (q31_t)0x3ff05858, + (q31_t)0x42d89bf0, (q31_t)0x3fefca84, (q31_t)0x42e529b0, (q31_t)0x3fef3a39, + (q31_t)0x42f1b755, (q31_t)0x3feea776, (q31_t)0x42fe44dc, (q31_t)0x3fee123d, + (q31_t)0x430ad245, (q31_t)0x3fed7a8c, (q31_t)0x43175f91, (q31_t)0x3fece065, + (q31_t)0x4323ecbe, (q31_t)0x3fec43c7, (q31_t)0x433079cc, (q31_t)0x3feba4b2, + (q31_t)0x433d06bb, (q31_t)0x3feb0326, (q31_t)0x43499389, (q31_t)0x3fea5f23, + (q31_t)0x43562038, (q31_t)0x3fe9b8a9, (q31_t)0x4362acc5, (q31_t)0x3fe90fb9, + (q31_t)0x436f3931, (q31_t)0x3fe86452, (q31_t)0x437bc57b, (q31_t)0x3fe7b674, + (q31_t)0x438851a2, (q31_t)0x3fe7061f, (q31_t)0x4394dda7, (q31_t)0x3fe65354, + (q31_t)0x43a16988, (q31_t)0x3fe59e12, (q31_t)0x43adf546, (q31_t)0x3fe4e659, + (q31_t)0x43ba80df, (q31_t)0x3fe42c2a, (q31_t)0x43c70c54, (q31_t)0x3fe36f84, + (q31_t)0x43d397a3, (q31_t)0x3fe2b067, (q31_t)0x43e022cc, (q31_t)0x3fe1eed5, + (q31_t)0x43ecadcf, (q31_t)0x3fe12acb, (q31_t)0x43f938ac, (q31_t)0x3fe0644b, + (q31_t)0x4405c361, (q31_t)0x3fdf9b55, (q31_t)0x44124dee, (q31_t)0x3fdecfe8, + (q31_t)0x441ed854, (q31_t)0x3fde0205, (q31_t)0x442b6290, (q31_t)0x3fdd31ac, + (q31_t)0x4437eca4, (q31_t)0x3fdc5edc, (q31_t)0x4444768d, (q31_t)0x3fdb8996, + (q31_t)0x4451004d, (q31_t)0x3fdab1d9, (q31_t)0x445d89e2, (q31_t)0x3fd9d7a7, + (q31_t)0x446a134c, (q31_t)0x3fd8fafe, (q31_t)0x44769c8b, (q31_t)0x3fd81bdf, + (q31_t)0x4483259d, (q31_t)0x3fd73a4a, (q31_t)0x448fae83, (q31_t)0x3fd6563f, + (q31_t)0x449c373c, (q31_t)0x3fd56fbe, (q31_t)0x44a8bfc7, (q31_t)0x3fd486c7, + (q31_t)0x44b54825, (q31_t)0x3fd39b5a, (q31_t)0x44c1d054, (q31_t)0x3fd2ad77, + (q31_t)0x44ce5854, (q31_t)0x3fd1bd1e, (q31_t)0x44dae024, (q31_t)0x3fd0ca4f, + (q31_t)0x44e767c5, (q31_t)0x3fcfd50b, (q31_t)0x44f3ef35, (q31_t)0x3fcedd50, + (q31_t)0x45007674, (q31_t)0x3fcde320, (q31_t)0x450cfd82, (q31_t)0x3fcce67a, + (q31_t)0x4519845e, (q31_t)0x3fcbe75e, (q31_t)0x45260b08, (q31_t)0x3fcae5cd, + (q31_t)0x4532917f, (q31_t)0x3fc9e1c6, (q31_t)0x453f17c3, (q31_t)0x3fc8db4a, + (q31_t)0x454b9dd3, (q31_t)0x3fc7d258, (q31_t)0x455823ae, (q31_t)0x3fc6c6f0, + (q31_t)0x4564a955, (q31_t)0x3fc5b913, (q31_t)0x45712ec7, (q31_t)0x3fc4a8c1, + (q31_t)0x457db403, (q31_t)0x3fc395f9, (q31_t)0x458a3908, (q31_t)0x3fc280bc, + (q31_t)0x4596bdd7, (q31_t)0x3fc1690a, (q31_t)0x45a3426f, (q31_t)0x3fc04ee3, + (q31_t)0x45afc6d0, (q31_t)0x3fbf3246, (q31_t)0x45bc4af8, (q31_t)0x3fbe1334, + (q31_t)0x45c8cee7, (q31_t)0x3fbcf1ad, (q31_t)0x45d5529e, (q31_t)0x3fbbcdb1, + (q31_t)0x45e1d61b, (q31_t)0x3fbaa740, (q31_t)0x45ee595d, (q31_t)0x3fb97e5a, + (q31_t)0x45fadc66, (q31_t)0x3fb852ff, (q31_t)0x46075f33, (q31_t)0x3fb7252f, + (q31_t)0x4613e1c5, (q31_t)0x3fb5f4ea, (q31_t)0x4620641a, (q31_t)0x3fb4c231, + (q31_t)0x462ce634, (q31_t)0x3fb38d02, (q31_t)0x46396810, (q31_t)0x3fb2555f, + (q31_t)0x4645e9af, (q31_t)0x3fb11b48, (q31_t)0x46526b10, (q31_t)0x3fafdebb, + (q31_t)0x465eec33, (q31_t)0x3fae9fbb, (q31_t)0x466b6d16, (q31_t)0x3fad5e45, + (q31_t)0x4677edbb, (q31_t)0x3fac1a5b, (q31_t)0x46846e1f, (q31_t)0x3faad3fd, + (q31_t)0x4690ee44, (q31_t)0x3fa98b2a, (q31_t)0x469d6e27, (q31_t)0x3fa83fe3, + (q31_t)0x46a9edc9, (q31_t)0x3fa6f228, (q31_t)0x46b66d29, (q31_t)0x3fa5a1f9, + (q31_t)0x46c2ec48, (q31_t)0x3fa44f55, (q31_t)0x46cf6b23, (q31_t)0x3fa2fa3d, + (q31_t)0x46dbe9bb, (q31_t)0x3fa1a2b2, (q31_t)0x46e86810, (q31_t)0x3fa048b2, + (q31_t)0x46f4e620, (q31_t)0x3f9eec3e, (q31_t)0x470163eb, (q31_t)0x3f9d8d56, + (q31_t)0x470de172, (q31_t)0x3f9c2bfb, (q31_t)0x471a5eb3, (q31_t)0x3f9ac82c, + (q31_t)0x4726dbae, (q31_t)0x3f9961e8, (q31_t)0x47335862, (q31_t)0x3f97f932, + (q31_t)0x473fd4cf, (q31_t)0x3f968e07, (q31_t)0x474c50f4, (q31_t)0x3f952069, + (q31_t)0x4758ccd2, (q31_t)0x3f93b058, (q31_t)0x47654867, (q31_t)0x3f923dd2, + (q31_t)0x4771c3b3, (q31_t)0x3f90c8da, (q31_t)0x477e3eb5, (q31_t)0x3f8f516e, + (q31_t)0x478ab96e, (q31_t)0x3f8dd78f, (q31_t)0x479733dc, (q31_t)0x3f8c5b3d, + (q31_t)0x47a3adff, (q31_t)0x3f8adc77, (q31_t)0x47b027d7, (q31_t)0x3f895b3e, + (q31_t)0x47bca163, (q31_t)0x3f87d792, (q31_t)0x47c91aa3, (q31_t)0x3f865174, + (q31_t)0x47d59396, (q31_t)0x3f84c8e2, (q31_t)0x47e20c3b, (q31_t)0x3f833ddd, + (q31_t)0x47ee8493, (q31_t)0x3f81b065, (q31_t)0x47fafc9c, (q31_t)0x3f80207b, + (q31_t)0x48077457, (q31_t)0x3f7e8e1e, (q31_t)0x4813ebc2, (q31_t)0x3f7cf94e, + (q31_t)0x482062de, (q31_t)0x3f7b620c, (q31_t)0x482cd9a9, (q31_t)0x3f79c857, + (q31_t)0x48395024, (q31_t)0x3f782c30, (q31_t)0x4845c64d, (q31_t)0x3f768d96, + (q31_t)0x48523c25, (q31_t)0x3f74ec8a, (q31_t)0x485eb1ab, (q31_t)0x3f73490b, + (q31_t)0x486b26de, (q31_t)0x3f71a31b, (q31_t)0x48779bbe, (q31_t)0x3f6ffab8, + (q31_t)0x4884104b, (q31_t)0x3f6e4fe3, (q31_t)0x48908483, (q31_t)0x3f6ca29c, + (q31_t)0x489cf867, (q31_t)0x3f6af2e3, (q31_t)0x48a96bf6, (q31_t)0x3f6940b8, + (q31_t)0x48b5df30, (q31_t)0x3f678c1c, (q31_t)0x48c25213, (q31_t)0x3f65d50d, + (q31_t)0x48cec4a0, (q31_t)0x3f641b8d, (q31_t)0x48db36d6, (q31_t)0x3f625f9b, + (q31_t)0x48e7a8b5, (q31_t)0x3f60a138, (q31_t)0x48f41a3c, (q31_t)0x3f5ee063, + (q31_t)0x49008b6a, (q31_t)0x3f5d1d1d, (q31_t)0x490cfc40, (q31_t)0x3f5b5765, + (q31_t)0x49196cbc, (q31_t)0x3f598f3c, (q31_t)0x4925dcdf, (q31_t)0x3f57c4a2, + (q31_t)0x49324ca7, (q31_t)0x3f55f796, (q31_t)0x493ebc14, (q31_t)0x3f54281a, + (q31_t)0x494b2b27, (q31_t)0x3f52562c, (q31_t)0x495799dd, (q31_t)0x3f5081cd, + (q31_t)0x49640837, (q31_t)0x3f4eaafe, (q31_t)0x49707635, (q31_t)0x3f4cd1be, + (q31_t)0x497ce3d5, (q31_t)0x3f4af60d, (q31_t)0x49895118, (q31_t)0x3f4917eb, + (q31_t)0x4995bdfd, (q31_t)0x3f473759, (q31_t)0x49a22a83, (q31_t)0x3f455456, + (q31_t)0x49ae96aa, (q31_t)0x3f436ee3, (q31_t)0x49bb0271, (q31_t)0x3f4186ff, + (q31_t)0x49c76dd8, (q31_t)0x3f3f9cab, (q31_t)0x49d3d8df, (q31_t)0x3f3dafe7, + (q31_t)0x49e04385, (q31_t)0x3f3bc0b3, (q31_t)0x49ecadc9, (q31_t)0x3f39cf0e, + (q31_t)0x49f917ac, (q31_t)0x3f37dafa, (q31_t)0x4a05812c, (q31_t)0x3f35e476, + (q31_t)0x4a11ea49, (q31_t)0x3f33eb81, (q31_t)0x4a1e5303, (q31_t)0x3f31f01d, + (q31_t)0x4a2abb59, (q31_t)0x3f2ff24a, (q31_t)0x4a37234a, (q31_t)0x3f2df206, + (q31_t)0x4a438ad7, (q31_t)0x3f2bef53, (q31_t)0x4a4ff1fe, (q31_t)0x3f29ea31, + (q31_t)0x4a5c58c0, (q31_t)0x3f27e29f, (q31_t)0x4a68bf1b, (q31_t)0x3f25d89e, + (q31_t)0x4a752510, (q31_t)0x3f23cc2e, (q31_t)0x4a818a9d, (q31_t)0x3f21bd4e, + (q31_t)0x4a8defc3, (q31_t)0x3f1fabff, (q31_t)0x4a9a5480, (q31_t)0x3f1d9842, + (q31_t)0x4aa6b8d5, (q31_t)0x3f1b8215, (q31_t)0x4ab31cc1, (q31_t)0x3f19697a, + (q31_t)0x4abf8043, (q31_t)0x3f174e70, (q31_t)0x4acbe35b, (q31_t)0x3f1530f7, + (q31_t)0x4ad84609, (q31_t)0x3f13110f, (q31_t)0x4ae4a84b, (q31_t)0x3f10eeb9, + (q31_t)0x4af10a22, (q31_t)0x3f0ec9f5, (q31_t)0x4afd6b8d, (q31_t)0x3f0ca2c2, + (q31_t)0x4b09cc8c, (q31_t)0x3f0a7921, (q31_t)0x4b162d1d, (q31_t)0x3f084d12, + (q31_t)0x4b228d42, (q31_t)0x3f061e95, (q31_t)0x4b2eecf8, (q31_t)0x3f03eda9, + (q31_t)0x4b3b4c40, (q31_t)0x3f01ba50, (q31_t)0x4b47ab19, (q31_t)0x3eff8489, + (q31_t)0x4b540982, (q31_t)0x3efd4c54, (q31_t)0x4b60677c, (q31_t)0x3efb11b1, + (q31_t)0x4b6cc506, (q31_t)0x3ef8d4a1, (q31_t)0x4b79221f, (q31_t)0x3ef69523, + (q31_t)0x4b857ec7, (q31_t)0x3ef45338, (q31_t)0x4b91dafc, (q31_t)0x3ef20ee0, + (q31_t)0x4b9e36c0, (q31_t)0x3eefc81a, (q31_t)0x4baa9211, (q31_t)0x3eed7ee7, + (q31_t)0x4bb6ecef, (q31_t)0x3eeb3347, (q31_t)0x4bc34759, (q31_t)0x3ee8e53a, + (q31_t)0x4bcfa150, (q31_t)0x3ee694c1, (q31_t)0x4bdbfad1, (q31_t)0x3ee441da, + (q31_t)0x4be853de, (q31_t)0x3ee1ec87, (q31_t)0x4bf4ac75, (q31_t)0x3edf94c7, + (q31_t)0x4c010496, (q31_t)0x3edd3a9a, (q31_t)0x4c0d5c41, (q31_t)0x3edade01, + (q31_t)0x4c19b374, (q31_t)0x3ed87efc, (q31_t)0x4c260a31, (q31_t)0x3ed61d8a, + (q31_t)0x4c326075, (q31_t)0x3ed3b9ad, (q31_t)0x4c3eb641, (q31_t)0x3ed15363, + (q31_t)0x4c4b0b94, (q31_t)0x3eceeaad, (q31_t)0x4c57606e, (q31_t)0x3ecc7f8b, + (q31_t)0x4c63b4ce, (q31_t)0x3eca11fe, (q31_t)0x4c7008b3, (q31_t)0x3ec7a205, + (q31_t)0x4c7c5c1e, (q31_t)0x3ec52fa0, (q31_t)0x4c88af0e, (q31_t)0x3ec2bad0, + (q31_t)0x4c950182, (q31_t)0x3ec04394, (q31_t)0x4ca1537a, (q31_t)0x3ebdc9ed, + (q31_t)0x4cada4f5, (q31_t)0x3ebb4ddb, (q31_t)0x4cb9f5f3, (q31_t)0x3eb8cf5d, + (q31_t)0x4cc64673, (q31_t)0x3eb64e75, (q31_t)0x4cd29676, (q31_t)0x3eb3cb21, + (q31_t)0x4cdee5f9, (q31_t)0x3eb14563, (q31_t)0x4ceb34fe, (q31_t)0x3eaebd3a, + (q31_t)0x4cf78383, (q31_t)0x3eac32a6, (q31_t)0x4d03d189, (q31_t)0x3ea9a5a8, + (q31_t)0x4d101f0e, (q31_t)0x3ea7163f, (q31_t)0x4d1c6c11, (q31_t)0x3ea4846c, + (q31_t)0x4d28b894, (q31_t)0x3ea1f02f, (q31_t)0x4d350495, (q31_t)0x3e9f5988, + (q31_t)0x4d415013, (q31_t)0x3e9cc076, (q31_t)0x4d4d9b0e, (q31_t)0x3e9a24fb, + (q31_t)0x4d59e586, (q31_t)0x3e978715, (q31_t)0x4d662f7b, (q31_t)0x3e94e6c6, + (q31_t)0x4d7278eb, (q31_t)0x3e92440d, (q31_t)0x4d7ec1d6, (q31_t)0x3e8f9eeb, + (q31_t)0x4d8b0a3d, (q31_t)0x3e8cf75f, (q31_t)0x4d97521d, (q31_t)0x3e8a4d6a, + (q31_t)0x4da39978, (q31_t)0x3e87a10c, (q31_t)0x4dafe04b, (q31_t)0x3e84f245, + (q31_t)0x4dbc2698, (q31_t)0x3e824114, (q31_t)0x4dc86c5d, (q31_t)0x3e7f8d7b, + (q31_t)0x4dd4b19a, (q31_t)0x3e7cd778, (q31_t)0x4de0f64f, (q31_t)0x3e7a1f0d, + (q31_t)0x4ded3a7b, (q31_t)0x3e77643a, (q31_t)0x4df97e1d, (q31_t)0x3e74a6fd, + (q31_t)0x4e05c135, (q31_t)0x3e71e759, (q31_t)0x4e1203c3, (q31_t)0x3e6f254c, + (q31_t)0x4e1e45c6, (q31_t)0x3e6c60d7, (q31_t)0x4e2a873e, (q31_t)0x3e6999fa, + (q31_t)0x4e36c82a, (q31_t)0x3e66d0b4, (q31_t)0x4e430889, (q31_t)0x3e640507, + (q31_t)0x4e4f485c, (q31_t)0x3e6136f3, (q31_t)0x4e5b87a2, (q31_t)0x3e5e6676, + (q31_t)0x4e67c65a, (q31_t)0x3e5b9392, (q31_t)0x4e740483, (q31_t)0x3e58be47, + (q31_t)0x4e80421e, (q31_t)0x3e55e694, (q31_t)0x4e8c7f2a, (q31_t)0x3e530c7a, + (q31_t)0x4e98bba7, (q31_t)0x3e502ff9, (q31_t)0x4ea4f793, (q31_t)0x3e4d5110, + (q31_t)0x4eb132ef, (q31_t)0x3e4a6fc1, (q31_t)0x4ebd6db9, (q31_t)0x3e478c0b, + (q31_t)0x4ec9a7f3, (q31_t)0x3e44a5ef, (q31_t)0x4ed5e19a, (q31_t)0x3e41bd6c, + (q31_t)0x4ee21aaf, (q31_t)0x3e3ed282, (q31_t)0x4eee5331, (q31_t)0x3e3be532, + (q31_t)0x4efa8b20, (q31_t)0x3e38f57c, (q31_t)0x4f06c27a, (q31_t)0x3e360360, + (q31_t)0x4f12f941, (q31_t)0x3e330ede, (q31_t)0x4f1f2f73, (q31_t)0x3e3017f6, + (q31_t)0x4f2b650f, (q31_t)0x3e2d1ea8, (q31_t)0x4f379a16, (q31_t)0x3e2a22f4, + (q31_t)0x4f43ce86, (q31_t)0x3e2724db, (q31_t)0x4f500260, (q31_t)0x3e24245d, + (q31_t)0x4f5c35a3, (q31_t)0x3e212179, (q31_t)0x4f68684e, (q31_t)0x3e1e1c30, + (q31_t)0x4f749a61, (q31_t)0x3e1b1482, (q31_t)0x4f80cbdc, (q31_t)0x3e180a6f, + (q31_t)0x4f8cfcbe, (q31_t)0x3e14fdf7, (q31_t)0x4f992d06, (q31_t)0x3e11ef1b, + (q31_t)0x4fa55cb4, (q31_t)0x3e0eddd9, (q31_t)0x4fb18bc8, (q31_t)0x3e0bca34, + (q31_t)0x4fbdba40, (q31_t)0x3e08b42a, (q31_t)0x4fc9e81e, (q31_t)0x3e059bbb, + (q31_t)0x4fd6155f, (q31_t)0x3e0280e9, (q31_t)0x4fe24205, (q31_t)0x3dff63b2, + (q31_t)0x4fee6e0d, (q31_t)0x3dfc4418, (q31_t)0x4ffa9979, (q31_t)0x3df9221a, + (q31_t)0x5006c446, (q31_t)0x3df5fdb8, (q31_t)0x5012ee76, (q31_t)0x3df2d6f3, + (q31_t)0x501f1807, (q31_t)0x3defadca, (q31_t)0x502b40f8, (q31_t)0x3dec823e, + (q31_t)0x5037694b, (q31_t)0x3de9544f, (q31_t)0x504390fd, (q31_t)0x3de623fd, + (q31_t)0x504fb80e, (q31_t)0x3de2f148, (q31_t)0x505bde7f, (q31_t)0x3ddfbc30, + (q31_t)0x5068044e, (q31_t)0x3ddc84b5, (q31_t)0x5074297b, (q31_t)0x3dd94ad8, + (q31_t)0x50804e06, (q31_t)0x3dd60e99, (q31_t)0x508c71ee, (q31_t)0x3dd2cff7, + (q31_t)0x50989532, (q31_t)0x3dcf8ef3, (q31_t)0x50a4b7d3, (q31_t)0x3dcc4b8d, + (q31_t)0x50b0d9d0, (q31_t)0x3dc905c5, (q31_t)0x50bcfb28, (q31_t)0x3dc5bd9b, + (q31_t)0x50c91bda, (q31_t)0x3dc2730f, (q31_t)0x50d53be7, (q31_t)0x3dbf2622, + (q31_t)0x50e15b4e, (q31_t)0x3dbbd6d4, (q31_t)0x50ed7a0e, (q31_t)0x3db88524, + (q31_t)0x50f99827, (q31_t)0x3db53113, (q31_t)0x5105b599, (q31_t)0x3db1daa2, + (q31_t)0x5111d263, (q31_t)0x3dae81cf, (q31_t)0x511dee84, (q31_t)0x3dab269b, + (q31_t)0x512a09fc, (q31_t)0x3da7c907, (q31_t)0x513624cb, (q31_t)0x3da46912, + (q31_t)0x51423ef0, (q31_t)0x3da106bd, (q31_t)0x514e586a, (q31_t)0x3d9da208, + (q31_t)0x515a713a, (q31_t)0x3d9a3af2, (q31_t)0x5166895f, (q31_t)0x3d96d17d, + (q31_t)0x5172a0d7, (q31_t)0x3d9365a8, (q31_t)0x517eb7a4, (q31_t)0x3d8ff772, + (q31_t)0x518acdc4, (q31_t)0x3d8c86de, (q31_t)0x5196e337, (q31_t)0x3d8913ea, + (q31_t)0x51a2f7fc, (q31_t)0x3d859e96, (q31_t)0x51af0c13, (q31_t)0x3d8226e4, + (q31_t)0x51bb1f7c, (q31_t)0x3d7eacd2, (q31_t)0x51c73235, (q31_t)0x3d7b3061, + (q31_t)0x51d3443f, (q31_t)0x3d77b192, (q31_t)0x51df5599, (q31_t)0x3d743064, + (q31_t)0x51eb6643, (q31_t)0x3d70acd7, (q31_t)0x51f7763c, (q31_t)0x3d6d26ec, + (q31_t)0x52038584, (q31_t)0x3d699ea3, (q31_t)0x520f941a, (q31_t)0x3d6613fb, + (q31_t)0x521ba1fd, (q31_t)0x3d6286f6, (q31_t)0x5227af2e, (q31_t)0x3d5ef793, + (q31_t)0x5233bbac, (q31_t)0x3d5b65d2, (q31_t)0x523fc776, (q31_t)0x3d57d1b3, + (q31_t)0x524bd28c, (q31_t)0x3d543b37, (q31_t)0x5257dced, (q31_t)0x3d50a25e, + (q31_t)0x5263e699, (q31_t)0x3d4d0728, (q31_t)0x526fef90, (q31_t)0x3d496994, + (q31_t)0x527bf7d1, (q31_t)0x3d45c9a4, (q31_t)0x5287ff5b, (q31_t)0x3d422757, + (q31_t)0x5294062f, (q31_t)0x3d3e82ae, (q31_t)0x52a00c4b, (q31_t)0x3d3adba7, + (q31_t)0x52ac11af, (q31_t)0x3d373245, (q31_t)0x52b8165b, (q31_t)0x3d338687, + (q31_t)0x52c41a4f, (q31_t)0x3d2fd86c, (q31_t)0x52d01d89, (q31_t)0x3d2c27f6, + (q31_t)0x52dc2009, (q31_t)0x3d287523, (q31_t)0x52e821cf, (q31_t)0x3d24bff6, + (q31_t)0x52f422db, (q31_t)0x3d21086c, (q31_t)0x5300232c, (q31_t)0x3d1d4e88, + (q31_t)0x530c22c1, (q31_t)0x3d199248, (q31_t)0x5318219a, (q31_t)0x3d15d3ad, + (q31_t)0x53241fb6, (q31_t)0x3d1212b7, (q31_t)0x53301d16, (q31_t)0x3d0e4f67, + (q31_t)0x533c19b8, (q31_t)0x3d0a89bc, (q31_t)0x5348159d, (q31_t)0x3d06c1b6, + (q31_t)0x535410c3, (q31_t)0x3d02f757, (q31_t)0x53600b2a, (q31_t)0x3cff2a9d, + (q31_t)0x536c04d2, (q31_t)0x3cfb5b89, (q31_t)0x5377fdbb, (q31_t)0x3cf78a1b, + (q31_t)0x5383f5e3, (q31_t)0x3cf3b653, (q31_t)0x538fed4b, (q31_t)0x3cefe032, + (q31_t)0x539be3f2, (q31_t)0x3cec07b8, (q31_t)0x53a7d9d7, (q31_t)0x3ce82ce4, + (q31_t)0x53b3cefa, (q31_t)0x3ce44fb7, (q31_t)0x53bfc35b, (q31_t)0x3ce07031, + (q31_t)0x53cbb6f8, (q31_t)0x3cdc8e52, (q31_t)0x53d7a9d3, (q31_t)0x3cd8aa1b, + (q31_t)0x53e39be9, (q31_t)0x3cd4c38b, (q31_t)0x53ef8d3c, (q31_t)0x3cd0daa2, + (q31_t)0x53fb7dc9, (q31_t)0x3cccef62, (q31_t)0x54076d91, (q31_t)0x3cc901c9, + (q31_t)0x54135c94, (q31_t)0x3cc511d9, (q31_t)0x541f4ad1, (q31_t)0x3cc11f90, + (q31_t)0x542b3846, (q31_t)0x3cbd2af0, (q31_t)0x543724f5, (q31_t)0x3cb933f9, + (q31_t)0x544310dd, (q31_t)0x3cb53aaa, (q31_t)0x544efbfc, (q31_t)0x3cb13f04, + (q31_t)0x545ae653, (q31_t)0x3cad4107, (q31_t)0x5466cfe1, (q31_t)0x3ca940b3, + (q31_t)0x5472b8a5, (q31_t)0x3ca53e09, (q31_t)0x547ea0a0, (q31_t)0x3ca13908, + (q31_t)0x548a87d1, (q31_t)0x3c9d31b0, (q31_t)0x54966e36, (q31_t)0x3c992803, + (q31_t)0x54a253d1, (q31_t)0x3c951bff, (q31_t)0x54ae38a0, (q31_t)0x3c910da5, + (q31_t)0x54ba1ca3, (q31_t)0x3c8cfcf6, (q31_t)0x54c5ffd9, (q31_t)0x3c88e9f1, + (q31_t)0x54d1e242, (q31_t)0x3c84d496, (q31_t)0x54ddc3de, (q31_t)0x3c80bce7, + (q31_t)0x54e9a4ac, (q31_t)0x3c7ca2e2, (q31_t)0x54f584ac, (q31_t)0x3c788688, + (q31_t)0x550163dc, (q31_t)0x3c7467d9, (q31_t)0x550d423d, (q31_t)0x3c7046d6, + (q31_t)0x55191fcf, (q31_t)0x3c6c237e, (q31_t)0x5524fc90, (q31_t)0x3c67fdd1, + (q31_t)0x5530d881, (q31_t)0x3c63d5d1, (q31_t)0x553cb3a0, (q31_t)0x3c5fab7c, + (q31_t)0x55488dee, (q31_t)0x3c5b7ed4, (q31_t)0x5554676a, (q31_t)0x3c574fd8, + (q31_t)0x55604013, (q31_t)0x3c531e88, (q31_t)0x556c17e9, (q31_t)0x3c4eeae5, + (q31_t)0x5577eeec, (q31_t)0x3c4ab4ef, (q31_t)0x5583c51b, (q31_t)0x3c467ca6, + (q31_t)0x558f9a76, (q31_t)0x3c42420a, (q31_t)0x559b6efb, (q31_t)0x3c3e051b, + (q31_t)0x55a742ac, (q31_t)0x3c39c5da, (q31_t)0x55b31587, (q31_t)0x3c358446, + (q31_t)0x55bee78c, (q31_t)0x3c314060, (q31_t)0x55cab8ba, (q31_t)0x3c2cfa28, + (q31_t)0x55d68911, (q31_t)0x3c28b19e, (q31_t)0x55e25890, (q31_t)0x3c2466c2, + (q31_t)0x55ee2738, (q31_t)0x3c201994, (q31_t)0x55f9f507, (q31_t)0x3c1bca16, + (q31_t)0x5605c1fd, (q31_t)0x3c177845, (q31_t)0x56118e1a, (q31_t)0x3c132424, + (q31_t)0x561d595d, (q31_t)0x3c0ecdb2, (q31_t)0x562923c5, (q31_t)0x3c0a74f0, + (q31_t)0x5634ed53, (q31_t)0x3c0619dc, (q31_t)0x5640b606, (q31_t)0x3c01bc78, + (q31_t)0x564c7ddd, (q31_t)0x3bfd5cc4, (q31_t)0x565844d8, (q31_t)0x3bf8fac0, + (q31_t)0x56640af7, (q31_t)0x3bf4966c, (q31_t)0x566fd039, (q31_t)0x3bf02fc9, + (q31_t)0x567b949d, (q31_t)0x3bebc6d5, (q31_t)0x56875823, (q31_t)0x3be75b93, + (q31_t)0x56931acb, (q31_t)0x3be2ee01, (q31_t)0x569edc94, (q31_t)0x3bde7e20, + (q31_t)0x56aa9d7e, (q31_t)0x3bda0bf0, (q31_t)0x56b65d88, (q31_t)0x3bd59771, + (q31_t)0x56c21cb2, (q31_t)0x3bd120a4, (q31_t)0x56cddafb, (q31_t)0x3bcca789, + (q31_t)0x56d99864, (q31_t)0x3bc82c1f, (q31_t)0x56e554ea, (q31_t)0x3bc3ae67, + (q31_t)0x56f1108f, (q31_t)0x3bbf2e62, (q31_t)0x56fccb51, (q31_t)0x3bbaac0e, + (q31_t)0x57088531, (q31_t)0x3bb6276e, (q31_t)0x57143e2d, (q31_t)0x3bb1a080, + (q31_t)0x571ff646, (q31_t)0x3bad1744, (q31_t)0x572bad7a, (q31_t)0x3ba88bbc, + (q31_t)0x573763c9, (q31_t)0x3ba3fde7, (q31_t)0x57431933, (q31_t)0x3b9f6dc5, + (q31_t)0x574ecdb8, (q31_t)0x3b9adb57, (q31_t)0x575a8157, (q31_t)0x3b96469d, + (q31_t)0x5766340f, (q31_t)0x3b91af97, (q31_t)0x5771e5e0, (q31_t)0x3b8d1644, + (q31_t)0x577d96ca, (q31_t)0x3b887aa6, (q31_t)0x578946cc, (q31_t)0x3b83dcbc, + (q31_t)0x5794f5e6, (q31_t)0x3b7f3c87, (q31_t)0x57a0a417, (q31_t)0x3b7a9a07, + (q31_t)0x57ac515f, (q31_t)0x3b75f53c, (q31_t)0x57b7fdbd, (q31_t)0x3b714e25, + (q31_t)0x57c3a931, (q31_t)0x3b6ca4c4, (q31_t)0x57cf53bb, (q31_t)0x3b67f919, + (q31_t)0x57dafd59, (q31_t)0x3b634b23, (q31_t)0x57e6a60c, (q31_t)0x3b5e9ae4, + (q31_t)0x57f24dd3, (q31_t)0x3b59e85a, (q31_t)0x57fdf4ae, (q31_t)0x3b553386, + (q31_t)0x58099a9c, (q31_t)0x3b507c69, (q31_t)0x58153f9d, (q31_t)0x3b4bc303, + (q31_t)0x5820e3b0, (q31_t)0x3b470753, (q31_t)0x582c86d5, (q31_t)0x3b42495a, + (q31_t)0x5838290c, (q31_t)0x3b3d8918, (q31_t)0x5843ca53, (q31_t)0x3b38c68e, + (q31_t)0x584f6aab, (q31_t)0x3b3401bb, (q31_t)0x585b0a13, (q31_t)0x3b2f3aa0, + (q31_t)0x5866a88a, (q31_t)0x3b2a713d, (q31_t)0x58724611, (q31_t)0x3b25a591, + (q31_t)0x587de2a7, (q31_t)0x3b20d79e, (q31_t)0x58897e4a, (q31_t)0x3b1c0764, + (q31_t)0x589518fc, (q31_t)0x3b1734e2, (q31_t)0x58a0b2bb, (q31_t)0x3b126019, + (q31_t)0x58ac4b87, (q31_t)0x3b0d8909, (q31_t)0x58b7e35f, (q31_t)0x3b08afb2, + (q31_t)0x58c37a44, (q31_t)0x3b03d414, (q31_t)0x58cf1034, (q31_t)0x3afef630, + (q31_t)0x58daa52f, (q31_t)0x3afa1605, (q31_t)0x58e63935, (q31_t)0x3af53395, + (q31_t)0x58f1cc45, (q31_t)0x3af04edf, (q31_t)0x58fd5e5f, (q31_t)0x3aeb67e3, + (q31_t)0x5908ef82, (q31_t)0x3ae67ea1, (q31_t)0x59147fae, (q31_t)0x3ae1931a, + (q31_t)0x59200ee3, (q31_t)0x3adca54e, (q31_t)0x592b9d1f, (q31_t)0x3ad7b53d, + (q31_t)0x59372a64, (q31_t)0x3ad2c2e8, (q31_t)0x5942b6af, (q31_t)0x3acdce4d, + (q31_t)0x594e4201, (q31_t)0x3ac8d76f, (q31_t)0x5959cc5a, (q31_t)0x3ac3de4c, + (q31_t)0x596555b8, (q31_t)0x3abee2e5, (q31_t)0x5970de1b, (q31_t)0x3ab9e53a, + (q31_t)0x597c6584, (q31_t)0x3ab4e54c, (q31_t)0x5987ebf0, (q31_t)0x3aafe31b, + (q31_t)0x59937161, (q31_t)0x3aaadea6, (q31_t)0x599ef5d6, (q31_t)0x3aa5d7ee, + (q31_t)0x59aa794d, (q31_t)0x3aa0cef3, (q31_t)0x59b5fbc8, (q31_t)0x3a9bc3b6, + (q31_t)0x59c17d44, (q31_t)0x3a96b636, (q31_t)0x59ccfdc2, (q31_t)0x3a91a674, + (q31_t)0x59d87d42, (q31_t)0x3a8c9470, (q31_t)0x59e3fbc3, (q31_t)0x3a87802a, + (q31_t)0x59ef7944, (q31_t)0x3a8269a3, (q31_t)0x59faf5c5, (q31_t)0x3a7d50da, + (q31_t)0x5a067145, (q31_t)0x3a7835cf, (q31_t)0x5a11ebc5, (q31_t)0x3a731884, + (q31_t)0x5a1d6544, (q31_t)0x3a6df8f8, (q31_t)0x5a28ddc0, (q31_t)0x3a68d72b, + (q31_t)0x5a34553b, (q31_t)0x3a63b31d, (q31_t)0x5a3fcbb3, (q31_t)0x3a5e8cd0, + (q31_t)0x5a4b4128, (q31_t)0x3a596442, (q31_t)0x5a56b599, (q31_t)0x3a543974, + (q31_t)0x5a622907, (q31_t)0x3a4f0c67, (q31_t)0x5a6d9b70, (q31_t)0x3a49dd1a, + (q31_t)0x5a790cd4, (q31_t)0x3a44ab8e, (q31_t)0x5a847d33, (q31_t)0x3a3f77c3, + (q31_t)0x5a8fec8c, (q31_t)0x3a3a41b9, (q31_t)0x5a9b5adf, (q31_t)0x3a350970, + (q31_t)0x5aa6c82b, (q31_t)0x3a2fcee8, (q31_t)0x5ab23471, (q31_t)0x3a2a9223, + (q31_t)0x5abd9faf, (q31_t)0x3a25531f, (q31_t)0x5ac909e5, (q31_t)0x3a2011de, + (q31_t)0x5ad47312, (q31_t)0x3a1ace5f, (q31_t)0x5adfdb37, (q31_t)0x3a1588a2, + (q31_t)0x5aeb4253, (q31_t)0x3a1040a8, (q31_t)0x5af6a865, (q31_t)0x3a0af671, + (q31_t)0x5b020d6c, (q31_t)0x3a05a9fd, (q31_t)0x5b0d716a, (q31_t)0x3a005b4d, + (q31_t)0x5b18d45c, (q31_t)0x39fb0a60, (q31_t)0x5b243643, (q31_t)0x39f5b737, + (q31_t)0x5b2f971e, (q31_t)0x39f061d2, (q31_t)0x5b3af6ec, (q31_t)0x39eb0a31, + (q31_t)0x5b4655ae, (q31_t)0x39e5b054, (q31_t)0x5b51b363, (q31_t)0x39e0543c, + (q31_t)0x5b5d100a, (q31_t)0x39daf5e8, (q31_t)0x5b686ba3, (q31_t)0x39d5955a, + (q31_t)0x5b73c62d, (q31_t)0x39d03291, (q31_t)0x5b7f1fa9, (q31_t)0x39cacd8d, + (q31_t)0x5b8a7815, (q31_t)0x39c5664f, (q31_t)0x5b95cf71, (q31_t)0x39bffcd7, + (q31_t)0x5ba125bd, (q31_t)0x39ba9125, (q31_t)0x5bac7af9, (q31_t)0x39b52339, + (q31_t)0x5bb7cf23, (q31_t)0x39afb313, (q31_t)0x5bc3223c, (q31_t)0x39aa40b4, + (q31_t)0x5bce7442, (q31_t)0x39a4cc1c, (q31_t)0x5bd9c537, (q31_t)0x399f554b, + (q31_t)0x5be51518, (q31_t)0x3999dc42, (q31_t)0x5bf063e6, (q31_t)0x399460ff, + (q31_t)0x5bfbb1a0, (q31_t)0x398ee385, (q31_t)0x5c06fe46, (q31_t)0x398963d2, + (q31_t)0x5c1249d8, (q31_t)0x3983e1e8, (q31_t)0x5c1d9454, (q31_t)0x397e5dc6, + (q31_t)0x5c28ddbb, (q31_t)0x3978d76c, (q31_t)0x5c34260c, (q31_t)0x39734edc, + (q31_t)0x5c3f6d47, (q31_t)0x396dc414, (q31_t)0x5c4ab36b, (q31_t)0x39683715, + (q31_t)0x5c55f878, (q31_t)0x3962a7e0, (q31_t)0x5c613c6d, (q31_t)0x395d1675, + (q31_t)0x5c6c7f4a, (q31_t)0x395782d3, (q31_t)0x5c77c10e, (q31_t)0x3951ecfc, + (q31_t)0x5c8301b9, (q31_t)0x394c54ee, (q31_t)0x5c8e414b, (q31_t)0x3946baac, + (q31_t)0x5c997fc4, (q31_t)0x39411e33, (q31_t)0x5ca4bd21, (q31_t)0x393b7f86, + (q31_t)0x5caff965, (q31_t)0x3935dea4, (q31_t)0x5cbb348d, (q31_t)0x39303b8e, + (q31_t)0x5cc66e99, (q31_t)0x392a9642, (q31_t)0x5cd1a78a, (q31_t)0x3924eec3, + (q31_t)0x5cdcdf5e, (q31_t)0x391f4510, (q31_t)0x5ce81615, (q31_t)0x39199929, + (q31_t)0x5cf34baf, (q31_t)0x3913eb0e, (q31_t)0x5cfe802b, (q31_t)0x390e3ac0, + (q31_t)0x5d09b389, (q31_t)0x3908883f, (q31_t)0x5d14e5c9, (q31_t)0x3902d38b, + (q31_t)0x5d2016e9, (q31_t)0x38fd1ca4, (q31_t)0x5d2b46ea, (q31_t)0x38f7638b, + (q31_t)0x5d3675cb, (q31_t)0x38f1a840, (q31_t)0x5d41a38c, (q31_t)0x38ebeac2, + (q31_t)0x5d4cd02c, (q31_t)0x38e62b13, (q31_t)0x5d57fbaa, (q31_t)0x38e06932, + (q31_t)0x5d632608, (q31_t)0x38daa520, (q31_t)0x5d6e4f43, (q31_t)0x38d4dedd, + (q31_t)0x5d79775c, (q31_t)0x38cf1669, (q31_t)0x5d849e51, (q31_t)0x38c94bc4, + (q31_t)0x5d8fc424, (q31_t)0x38c37eef, (q31_t)0x5d9ae8d2, (q31_t)0x38bdafea, + (q31_t)0x5da60c5d, (q31_t)0x38b7deb4, (q31_t)0x5db12ec3, (q31_t)0x38b20b4f, + (q31_t)0x5dbc5004, (q31_t)0x38ac35ba, (q31_t)0x5dc7701f, (q31_t)0x38a65df6, + (q31_t)0x5dd28f15, (q31_t)0x38a08402, (q31_t)0x5dddace4, (q31_t)0x389aa7e0, + (q31_t)0x5de8c98c, (q31_t)0x3894c98f, (q31_t)0x5df3e50d, (q31_t)0x388ee910, + (q31_t)0x5dfeff67, (q31_t)0x38890663, (q31_t)0x5e0a1898, (q31_t)0x38832187, + (q31_t)0x5e1530a1, (q31_t)0x387d3a7e, (q31_t)0x5e204781, (q31_t)0x38775147, + (q31_t)0x5e2b5d38, (q31_t)0x387165e3, (q31_t)0x5e3671c5, (q31_t)0x386b7852, + (q31_t)0x5e418528, (q31_t)0x38658894, (q31_t)0x5e4c9760, (q31_t)0x385f96a9, + (q31_t)0x5e57a86d, (q31_t)0x3859a292, (q31_t)0x5e62b84f, (q31_t)0x3853ac4f, + (q31_t)0x5e6dc705, (q31_t)0x384db3e0, (q31_t)0x5e78d48e, (q31_t)0x3847b946, + (q31_t)0x5e83e0eb, (q31_t)0x3841bc7f, (q31_t)0x5e8eec1b, (q31_t)0x383bbd8e, + (q31_t)0x5e99f61d, (q31_t)0x3835bc71, (q31_t)0x5ea4fef0, (q31_t)0x382fb92a, + (q31_t)0x5eb00696, (q31_t)0x3829b3b9, (q31_t)0x5ebb0d0d, (q31_t)0x3823ac1d, + (q31_t)0x5ec61254, (q31_t)0x381da256, (q31_t)0x5ed1166b, (q31_t)0x38179666, + (q31_t)0x5edc1953, (q31_t)0x3811884d, (q31_t)0x5ee71b0a, (q31_t)0x380b780a, + (q31_t)0x5ef21b90, (q31_t)0x3805659e, (q31_t)0x5efd1ae4, (q31_t)0x37ff5109, + (q31_t)0x5f081907, (q31_t)0x37f93a4b, (q31_t)0x5f1315f7, (q31_t)0x37f32165, + (q31_t)0x5f1e11b5, (q31_t)0x37ed0657, (q31_t)0x5f290c3f, (q31_t)0x37e6e921, + (q31_t)0x5f340596, (q31_t)0x37e0c9c3, (q31_t)0x5f3efdb9, (q31_t)0x37daa83d, + (q31_t)0x5f49f4a8, (q31_t)0x37d48490, (q31_t)0x5f54ea62, (q31_t)0x37ce5ebd, + (q31_t)0x5f5fdee6, (q31_t)0x37c836c2, (q31_t)0x5f6ad235, (q31_t)0x37c20ca1, + (q31_t)0x5f75c44e, (q31_t)0x37bbe05a, (q31_t)0x5f80b531, (q31_t)0x37b5b1ec, + (q31_t)0x5f8ba4dc, (q31_t)0x37af8159, (q31_t)0x5f969350, (q31_t)0x37a94ea0, + (q31_t)0x5fa1808c, (q31_t)0x37a319c2, (q31_t)0x5fac6c91, (q31_t)0x379ce2be, + (q31_t)0x5fb7575c, (q31_t)0x3796a996, (q31_t)0x5fc240ef, (q31_t)0x37906e49, + (q31_t)0x5fcd2948, (q31_t)0x378a30d8, (q31_t)0x5fd81067, (q31_t)0x3783f143, + (q31_t)0x5fe2f64c, (q31_t)0x377daf89, (q31_t)0x5feddaf6, (q31_t)0x37776bac, + (q31_t)0x5ff8be65, (q31_t)0x377125ac, (q31_t)0x6003a099, (q31_t)0x376add88, + (q31_t)0x600e8190, (q31_t)0x37649341, (q31_t)0x6019614c, (q31_t)0x375e46d8, + (q31_t)0x60243fca, (q31_t)0x3757f84c, (q31_t)0x602f1d0b, (q31_t)0x3751a79e, + (q31_t)0x6039f90f, (q31_t)0x374b54ce, (q31_t)0x6044d3d4, (q31_t)0x3744ffdd, + (q31_t)0x604fad5b, (q31_t)0x373ea8ca, (q31_t)0x605a85a3, (q31_t)0x37384f95, + (q31_t)0x60655cac, (q31_t)0x3731f440, (q31_t)0x60703275, (q31_t)0x372b96ca, + (q31_t)0x607b06fe, (q31_t)0x37253733, (q31_t)0x6085da46, (q31_t)0x371ed57c, + (q31_t)0x6090ac4d, (q31_t)0x371871a5, (q31_t)0x609b7d13, (q31_t)0x37120bae, + (q31_t)0x60a64c97, (q31_t)0x370ba398, (q31_t)0x60b11ad9, (q31_t)0x37053962, + (q31_t)0x60bbe7d8, (q31_t)0x36fecd0e, (q31_t)0x60c6b395, (q31_t)0x36f85e9a, + (q31_t)0x60d17e0d, (q31_t)0x36f1ee09, (q31_t)0x60dc4742, (q31_t)0x36eb7b58, + (q31_t)0x60e70f32, (q31_t)0x36e5068a, (q31_t)0x60f1d5de, (q31_t)0x36de8f9e, + (q31_t)0x60fc9b44, (q31_t)0x36d81695, (q31_t)0x61075f65, (q31_t)0x36d19b6e, + (q31_t)0x61122240, (q31_t)0x36cb1e2a, (q31_t)0x611ce3d5, (q31_t)0x36c49ec9, + (q31_t)0x6127a423, (q31_t)0x36be1d4c, (q31_t)0x61326329, (q31_t)0x36b799b3, + (q31_t)0x613d20e8, (q31_t)0x36b113fd, (q31_t)0x6147dd5f, (q31_t)0x36aa8c2c, + (q31_t)0x6152988d, (q31_t)0x36a4023f, (q31_t)0x615d5273, (q31_t)0x369d7637, + (q31_t)0x61680b0f, (q31_t)0x3696e814, (q31_t)0x6172c262, (q31_t)0x369057d6, + (q31_t)0x617d786a, (q31_t)0x3689c57d, (q31_t)0x61882d28, (q31_t)0x3683310b, + (q31_t)0x6192e09b, (q31_t)0x367c9a7e, (q31_t)0x619d92c2, (q31_t)0x367601d7, + (q31_t)0x61a8439e, (q31_t)0x366f6717, (q31_t)0x61b2f32e, (q31_t)0x3668ca3e, + (q31_t)0x61bda171, (q31_t)0x36622b4c, (q31_t)0x61c84e67, (q31_t)0x365b8a41, + (q31_t)0x61d2fa0f, (q31_t)0x3654e71d, (q31_t)0x61dda46a, (q31_t)0x364e41e2, + (q31_t)0x61e84d76, (q31_t)0x36479a8e, (q31_t)0x61f2f534, (q31_t)0x3640f123, + (q31_t)0x61fd9ba3, (q31_t)0x363a45a0, (q31_t)0x620840c2, (q31_t)0x36339806, + (q31_t)0x6212e492, (q31_t)0x362ce855, (q31_t)0x621d8711, (q31_t)0x3626368d, + (q31_t)0x6228283f, (q31_t)0x361f82af, (q31_t)0x6232c81c, (q31_t)0x3618ccba, + (q31_t)0x623d66a8, (q31_t)0x361214b0, (q31_t)0x624803e2, (q31_t)0x360b5a90, + (q31_t)0x62529fca, (q31_t)0x36049e5b, (q31_t)0x625d3a5e, (q31_t)0x35fde011, + (q31_t)0x6267d3a0, (q31_t)0x35f71fb1, (q31_t)0x62726b8e, (q31_t)0x35f05d3d, + (q31_t)0x627d0228, (q31_t)0x35e998b5, (q31_t)0x6287976e, (q31_t)0x35e2d219, + (q31_t)0x62922b5e, (q31_t)0x35dc0968, (q31_t)0x629cbdfa, (q31_t)0x35d53ea5, + (q31_t)0x62a74f40, (q31_t)0x35ce71ce, (q31_t)0x62b1df30, (q31_t)0x35c7a2e3, + (q31_t)0x62bc6dca, (q31_t)0x35c0d1e7, (q31_t)0x62c6fb0c, (q31_t)0x35b9fed7, + (q31_t)0x62d186f8, (q31_t)0x35b329b5, (q31_t)0x62dc118c, (q31_t)0x35ac5282, + (q31_t)0x62e69ac8, (q31_t)0x35a5793c, (q31_t)0x62f122ab, (q31_t)0x359e9de5, + (q31_t)0x62fba936, (q31_t)0x3597c07d, (q31_t)0x63062e67, (q31_t)0x3590e104, + (q31_t)0x6310b23e, (q31_t)0x3589ff7a, (q31_t)0x631b34bc, (q31_t)0x35831be0, + (q31_t)0x6325b5df, (q31_t)0x357c3636, (q31_t)0x633035a7, (q31_t)0x35754e7c, + (q31_t)0x633ab414, (q31_t)0x356e64b2, (q31_t)0x63453125, (q31_t)0x356778d9, + (q31_t)0x634facda, (q31_t)0x35608af1, (q31_t)0x635a2733, (q31_t)0x35599afa, + (q31_t)0x6364a02e, (q31_t)0x3552a8f4, (q31_t)0x636f17cc, (q31_t)0x354bb4e1, + (q31_t)0x63798e0d, (q31_t)0x3544bebf, (q31_t)0x638402ef, (q31_t)0x353dc68f, + (q31_t)0x638e7673, (q31_t)0x3536cc52, (q31_t)0x6398e898, (q31_t)0x352fd008, + (q31_t)0x63a3595e, (q31_t)0x3528d1b1, (q31_t)0x63adc8c4, (q31_t)0x3521d14d, + (q31_t)0x63b836ca, (q31_t)0x351acedd, (q31_t)0x63c2a36f, (q31_t)0x3513ca60, + (q31_t)0x63cd0eb3, (q31_t)0x350cc3d8, (q31_t)0x63d77896, (q31_t)0x3505bb44, + (q31_t)0x63e1e117, (q31_t)0x34feb0a5, (q31_t)0x63ec4837, (q31_t)0x34f7a3fb, + (q31_t)0x63f6adf3, (q31_t)0x34f09546, (q31_t)0x6401124d, (q31_t)0x34e98487, + (q31_t)0x640b7543, (q31_t)0x34e271bd, (q31_t)0x6415d6d5, (q31_t)0x34db5cea, + (q31_t)0x64203704, (q31_t)0x34d4460c, (q31_t)0x642a95ce, (q31_t)0x34cd2d26, + (q31_t)0x6434f332, (q31_t)0x34c61236, (q31_t)0x643f4f32, (q31_t)0x34bef53d, + (q31_t)0x6449a9cc, (q31_t)0x34b7d63c, (q31_t)0x645402ff, (q31_t)0x34b0b533, + (q31_t)0x645e5acc, (q31_t)0x34a99221, (q31_t)0x6468b132, (q31_t)0x34a26d08, + (q31_t)0x64730631, (q31_t)0x349b45e7, (q31_t)0x647d59c8, (q31_t)0x34941cbf, + (q31_t)0x6487abf7, (q31_t)0x348cf190, (q31_t)0x6491fcbe, (q31_t)0x3485c45b, + (q31_t)0x649c4c1b, (q31_t)0x347e951f, (q31_t)0x64a69a0f, (q31_t)0x347763dd, + (q31_t)0x64b0e699, (q31_t)0x34703095, (q31_t)0x64bb31ba, (q31_t)0x3468fb47, + (q31_t)0x64c57b6f, (q31_t)0x3461c3f5, (q31_t)0x64cfc3ba, (q31_t)0x345a8a9d, + (q31_t)0x64da0a9a, (q31_t)0x34534f41, (q31_t)0x64e4500e, (q31_t)0x344c11e0, + (q31_t)0x64ee9415, (q31_t)0x3444d27b, (q31_t)0x64f8d6b0, (q31_t)0x343d9112, + (q31_t)0x650317df, (q31_t)0x34364da6, (q31_t)0x650d57a0, (q31_t)0x342f0836, + (q31_t)0x651795f3, (q31_t)0x3427c0c3, (q31_t)0x6521d2d8, (q31_t)0x3420774d, + (q31_t)0x652c0e4f, (q31_t)0x34192bd5, (q31_t)0x65364857, (q31_t)0x3411de5b, + (q31_t)0x654080ef, (q31_t)0x340a8edf, (q31_t)0x654ab818, (q31_t)0x34033d61, + (q31_t)0x6554edd1, (q31_t)0x33fbe9e2, (q31_t)0x655f2219, (q31_t)0x33f49462, + (q31_t)0x656954f1, (q31_t)0x33ed3ce1, (q31_t)0x65738657, (q31_t)0x33e5e360, + (q31_t)0x657db64c, (q31_t)0x33de87de, (q31_t)0x6587e4cf, (q31_t)0x33d72a5d, + (q31_t)0x659211df, (q31_t)0x33cfcadc, (q31_t)0x659c3d7c, (q31_t)0x33c8695b, + (q31_t)0x65a667a7, (q31_t)0x33c105db, (q31_t)0x65b0905d, (q31_t)0x33b9a05d, + (q31_t)0x65bab7a0, (q31_t)0x33b238e0, (q31_t)0x65c4dd6e, (q31_t)0x33aacf65, + (q31_t)0x65cf01c8, (q31_t)0x33a363ec, (q31_t)0x65d924ac, (q31_t)0x339bf675, + (q31_t)0x65e3461b, (q31_t)0x33948701, (q31_t)0x65ed6614, (q31_t)0x338d1590, + (q31_t)0x65f78497, (q31_t)0x3385a222, (q31_t)0x6601a1a2, (q31_t)0x337e2cb7, + (q31_t)0x660bbd37, (q31_t)0x3376b551, (q31_t)0x6615d754, (q31_t)0x336f3bee, + (q31_t)0x661feffa, (q31_t)0x3367c090, (q31_t)0x662a0727, (q31_t)0x33604336, + (q31_t)0x66341cdb, (q31_t)0x3358c3e2, (q31_t)0x663e3117, (q31_t)0x33514292, + (q31_t)0x664843d9, (q31_t)0x3349bf48, (q31_t)0x66525521, (q31_t)0x33423a04, + (q31_t)0x665c64ef, (q31_t)0x333ab2c6, (q31_t)0x66667342, (q31_t)0x3333298f, + (q31_t)0x6670801a, (q31_t)0x332b9e5e, (q31_t)0x667a8b77, (q31_t)0x33241134, + (q31_t)0x66849558, (q31_t)0x331c8211, (q31_t)0x668e9dbd, (q31_t)0x3314f0f6, + (q31_t)0x6698a4a6, (q31_t)0x330d5de3, (q31_t)0x66a2aa11, (q31_t)0x3305c8d7, + (q31_t)0x66acadff, (q31_t)0x32fe31d5, (q31_t)0x66b6b070, (q31_t)0x32f698db, + (q31_t)0x66c0b162, (q31_t)0x32eefdea, (q31_t)0x66cab0d6, (q31_t)0x32e76102, + (q31_t)0x66d4aecb, (q31_t)0x32dfc224, (q31_t)0x66deab41, (q31_t)0x32d82150, + (q31_t)0x66e8a637, (q31_t)0x32d07e85, (q31_t)0x66f29fad, (q31_t)0x32c8d9c6, + (q31_t)0x66fc97a3, (q31_t)0x32c13311, (q31_t)0x67068e18, (q31_t)0x32b98a67, + (q31_t)0x6710830c, (q31_t)0x32b1dfc9, (q31_t)0x671a767e, (q31_t)0x32aa3336, + (q31_t)0x6724686e, (q31_t)0x32a284b0, (q31_t)0x672e58dc, (q31_t)0x329ad435, + (q31_t)0x673847c8, (q31_t)0x329321c7, (q31_t)0x67423530, (q31_t)0x328b6d66, + (q31_t)0x674c2115, (q31_t)0x3283b712, (q31_t)0x67560b76, (q31_t)0x327bfecc, + (q31_t)0x675ff452, (q31_t)0x32744493, (q31_t)0x6769dbaa, (q31_t)0x326c8868, + (q31_t)0x6773c17d, (q31_t)0x3264ca4c, (q31_t)0x677da5cb, (q31_t)0x325d0a3e, + (q31_t)0x67878893, (q31_t)0x32554840, (q31_t)0x679169d5, (q31_t)0x324d8450, + (q31_t)0x679b4990, (q31_t)0x3245be70, (q31_t)0x67a527c4, (q31_t)0x323df6a0, + (q31_t)0x67af0472, (q31_t)0x32362ce0, (q31_t)0x67b8df97, (q31_t)0x322e6130, + (q31_t)0x67c2b934, (q31_t)0x32269391, (q31_t)0x67cc9149, (q31_t)0x321ec403, + (q31_t)0x67d667d5, (q31_t)0x3216f287, (q31_t)0x67e03cd8, (q31_t)0x320f1f1c, + (q31_t)0x67ea1052, (q31_t)0x320749c3, (q31_t)0x67f3e241, (q31_t)0x31ff727c, + (q31_t)0x67fdb2a7, (q31_t)0x31f79948, (q31_t)0x68078181, (q31_t)0x31efbe27, + (q31_t)0x68114ed0, (q31_t)0x31e7e118, (q31_t)0x681b1a94, (q31_t)0x31e0021e, + (q31_t)0x6824e4cc, (q31_t)0x31d82137, (q31_t)0x682ead78, (q31_t)0x31d03e64, + (q31_t)0x68387498, (q31_t)0x31c859a5, (q31_t)0x68423a2a, (q31_t)0x31c072fb, + (q31_t)0x684bfe2f, (q31_t)0x31b88a66, (q31_t)0x6855c0a6, (q31_t)0x31b09fe7, + (q31_t)0x685f8190, (q31_t)0x31a8b37c, (q31_t)0x686940ea, (q31_t)0x31a0c528, + (q31_t)0x6872feb6, (q31_t)0x3198d4ea, (q31_t)0x687cbaf3, (q31_t)0x3190e2c3, + (q31_t)0x688675a0, (q31_t)0x3188eeb2, (q31_t)0x68902ebd, (q31_t)0x3180f8b8, + (q31_t)0x6899e64a, (q31_t)0x317900d6, (q31_t)0x68a39c46, (q31_t)0x3171070c, + (q31_t)0x68ad50b1, (q31_t)0x31690b59, (q31_t)0x68b7038b, (q31_t)0x31610dbf, + (q31_t)0x68c0b4d2, (q31_t)0x31590e3e, (q31_t)0x68ca6488, (q31_t)0x31510cd5, + (q31_t)0x68d412ab, (q31_t)0x31490986, (q31_t)0x68ddbf3b, (q31_t)0x31410450, + (q31_t)0x68e76a37, (q31_t)0x3138fd35, (q31_t)0x68f113a0, (q31_t)0x3130f433, + (q31_t)0x68fabb75, (q31_t)0x3128e94c, (q31_t)0x690461b5, (q31_t)0x3120dc80, + (q31_t)0x690e0661, (q31_t)0x3118cdcf, (q31_t)0x6917a977, (q31_t)0x3110bd39, + (q31_t)0x69214af8, (q31_t)0x3108aabf, (q31_t)0x692aeae3, (q31_t)0x31009661, + (q31_t)0x69348937, (q31_t)0x30f8801f, (q31_t)0x693e25f5, (q31_t)0x30f067fb, + (q31_t)0x6947c11c, (q31_t)0x30e84df3, (q31_t)0x69515aab, (q31_t)0x30e03208, + (q31_t)0x695af2a3, (q31_t)0x30d8143b, (q31_t)0x69648902, (q31_t)0x30cff48c, + (q31_t)0x696e1dc9, (q31_t)0x30c7d2fb, (q31_t)0x6977b0f7, (q31_t)0x30bfaf89, + (q31_t)0x6981428c, (q31_t)0x30b78a36, (q31_t)0x698ad287, (q31_t)0x30af6302, + (q31_t)0x699460e8, (q31_t)0x30a739ed, (q31_t)0x699dedaf, (q31_t)0x309f0ef8, + (q31_t)0x69a778db, (q31_t)0x3096e223, (q31_t)0x69b1026c, (q31_t)0x308eb36f, + (q31_t)0x69ba8a61, (q31_t)0x308682dc, (q31_t)0x69c410ba, (q31_t)0x307e5069, + (q31_t)0x69cd9578, (q31_t)0x30761c18, (q31_t)0x69d71899, (q31_t)0x306de5e9, + (q31_t)0x69e09a1c, (q31_t)0x3065addb, (q31_t)0x69ea1a03, (q31_t)0x305d73f0, + (q31_t)0x69f3984c, (q31_t)0x30553828, (q31_t)0x69fd14f6, (q31_t)0x304cfa83, + (q31_t)0x6a069003, (q31_t)0x3044bb00, (q31_t)0x6a100970, (q31_t)0x303c79a2, + (q31_t)0x6a19813f, (q31_t)0x30343667, (q31_t)0x6a22f76e, (q31_t)0x302bf151, + (q31_t)0x6a2c6bfd, (q31_t)0x3023aa5f, (q31_t)0x6a35deeb, (q31_t)0x301b6193, + (q31_t)0x6a3f503a, (q31_t)0x301316eb, (q31_t)0x6a48bfe7, (q31_t)0x300aca69, + (q31_t)0x6a522df3, (q31_t)0x30027c0c, (q31_t)0x6a5b9a5d, (q31_t)0x2ffa2bd6, + (q31_t)0x6a650525, (q31_t)0x2ff1d9c7, (q31_t)0x6a6e6e4b, (q31_t)0x2fe985de, + (q31_t)0x6a77d5ce, (q31_t)0x2fe1301c, (q31_t)0x6a813bae, (q31_t)0x2fd8d882, + (q31_t)0x6a8a9fea, (q31_t)0x2fd07f0f, (q31_t)0x6a940283, (q31_t)0x2fc823c5, + (q31_t)0x6a9d6377, (q31_t)0x2fbfc6a3, (q31_t)0x6aa6c2c6, (q31_t)0x2fb767aa, + (q31_t)0x6ab02071, (q31_t)0x2faf06da, (q31_t)0x6ab97c77, (q31_t)0x2fa6a433, + (q31_t)0x6ac2d6d6, (q31_t)0x2f9e3fb6, (q31_t)0x6acc2f90, (q31_t)0x2f95d963, + (q31_t)0x6ad586a3, (q31_t)0x2f8d713a, (q31_t)0x6adedc10, (q31_t)0x2f85073c, + (q31_t)0x6ae82fd5, (q31_t)0x2f7c9b69, (q31_t)0x6af181f3, (q31_t)0x2f742dc1, + (q31_t)0x6afad269, (q31_t)0x2f6bbe45, (q31_t)0x6b042137, (q31_t)0x2f634cf5, + (q31_t)0x6b0d6e5c, (q31_t)0x2f5ad9d1, (q31_t)0x6b16b9d9, (q31_t)0x2f5264da, + (q31_t)0x6b2003ac, (q31_t)0x2f49ee0f, (q31_t)0x6b294bd5, (q31_t)0x2f417573, + (q31_t)0x6b329255, (q31_t)0x2f38fb03, (q31_t)0x6b3bd72a, (q31_t)0x2f307ec2, + (q31_t)0x6b451a55, (q31_t)0x2f2800af, (q31_t)0x6b4e5bd4, (q31_t)0x2f1f80ca, + (q31_t)0x6b579ba8, (q31_t)0x2f16ff14, (q31_t)0x6b60d9d0, (q31_t)0x2f0e7b8e, + (q31_t)0x6b6a164d, (q31_t)0x2f05f637, (q31_t)0x6b73511c, (q31_t)0x2efd6f10, + (q31_t)0x6b7c8a3f, (q31_t)0x2ef4e619, (q31_t)0x6b85c1b5, (q31_t)0x2eec5b53, + (q31_t)0x6b8ef77d, (q31_t)0x2ee3cebe, (q31_t)0x6b982b97, (q31_t)0x2edb405a, + (q31_t)0x6ba15e03, (q31_t)0x2ed2b027, (q31_t)0x6baa8ec0, (q31_t)0x2eca1e27, + (q31_t)0x6bb3bdce, (q31_t)0x2ec18a58, (q31_t)0x6bbceb2d, (q31_t)0x2eb8f4bc, + (q31_t)0x6bc616dd, (q31_t)0x2eb05d53, (q31_t)0x6bcf40dc, (q31_t)0x2ea7c41e, + (q31_t)0x6bd8692b, (q31_t)0x2e9f291b, (q31_t)0x6be18fc9, (q31_t)0x2e968c4d, + (q31_t)0x6beab4b6, (q31_t)0x2e8dedb3, (q31_t)0x6bf3d7f2, (q31_t)0x2e854d4d, + (q31_t)0x6bfcf97c, (q31_t)0x2e7cab1c, (q31_t)0x6c061953, (q31_t)0x2e740720, + (q31_t)0x6c0f3779, (q31_t)0x2e6b615a, (q31_t)0x6c1853eb, (q31_t)0x2e62b9ca, + (q31_t)0x6c216eaa, (q31_t)0x2e5a1070, (q31_t)0x6c2a87b6, (q31_t)0x2e51654c, + (q31_t)0x6c339f0e, (q31_t)0x2e48b860, (q31_t)0x6c3cb4b1, (q31_t)0x2e4009aa, + (q31_t)0x6c45c8a0, (q31_t)0x2e37592c, (q31_t)0x6c4edada, (q31_t)0x2e2ea6e6, + (q31_t)0x6c57eb5e, (q31_t)0x2e25f2d8, (q31_t)0x6c60fa2d, (q31_t)0x2e1d3d03, + (q31_t)0x6c6a0746, (q31_t)0x2e148566, (q31_t)0x6c7312a9, (q31_t)0x2e0bcc03, + (q31_t)0x6c7c1c55, (q31_t)0x2e0310d9, (q31_t)0x6c85244a, (q31_t)0x2dfa53e9, + (q31_t)0x6c8e2a87, (q31_t)0x2df19534, (q31_t)0x6c972f0d, (q31_t)0x2de8d4b8, + (q31_t)0x6ca031da, (q31_t)0x2de01278, (q31_t)0x6ca932ef, (q31_t)0x2dd74e73, + (q31_t)0x6cb2324c, (q31_t)0x2dce88aa, (q31_t)0x6cbb2fef, (q31_t)0x2dc5c11c, + (q31_t)0x6cc42bd9, (q31_t)0x2dbcf7cb, (q31_t)0x6ccd2609, (q31_t)0x2db42cb6, + (q31_t)0x6cd61e7f, (q31_t)0x2dab5fdf, (q31_t)0x6cdf153a, (q31_t)0x2da29144, + (q31_t)0x6ce80a3a, (q31_t)0x2d99c0e7, (q31_t)0x6cf0fd80, (q31_t)0x2d90eec8, + (q31_t)0x6cf9ef09, (q31_t)0x2d881ae8, (q31_t)0x6d02ded7, (q31_t)0x2d7f4545, + (q31_t)0x6d0bcce8, (q31_t)0x2d766de2, (q31_t)0x6d14b93d, (q31_t)0x2d6d94bf, + (q31_t)0x6d1da3d5, (q31_t)0x2d64b9da, (q31_t)0x6d268cb0, (q31_t)0x2d5bdd36, + (q31_t)0x6d2f73cd, (q31_t)0x2d52fed2, (q31_t)0x6d38592c, (q31_t)0x2d4a1eaf, + (q31_t)0x6d413ccd, (q31_t)0x2d413ccd, (q31_t)0x6d4a1eaf, (q31_t)0x2d38592c, + (q31_t)0x6d52fed2, (q31_t)0x2d2f73cd, (q31_t)0x6d5bdd36, (q31_t)0x2d268cb0, + (q31_t)0x6d64b9da, (q31_t)0x2d1da3d5, (q31_t)0x6d6d94bf, (q31_t)0x2d14b93d, + (q31_t)0x6d766de2, (q31_t)0x2d0bcce8, (q31_t)0x6d7f4545, (q31_t)0x2d02ded7, + (q31_t)0x6d881ae8, (q31_t)0x2cf9ef09, (q31_t)0x6d90eec8, (q31_t)0x2cf0fd80, + (q31_t)0x6d99c0e7, (q31_t)0x2ce80a3a, (q31_t)0x6da29144, (q31_t)0x2cdf153a, + (q31_t)0x6dab5fdf, (q31_t)0x2cd61e7f, (q31_t)0x6db42cb6, (q31_t)0x2ccd2609, + (q31_t)0x6dbcf7cb, (q31_t)0x2cc42bd9, (q31_t)0x6dc5c11c, (q31_t)0x2cbb2fef, + (q31_t)0x6dce88aa, (q31_t)0x2cb2324c, (q31_t)0x6dd74e73, (q31_t)0x2ca932ef, + (q31_t)0x6de01278, (q31_t)0x2ca031da, (q31_t)0x6de8d4b8, (q31_t)0x2c972f0d, + (q31_t)0x6df19534, (q31_t)0x2c8e2a87, (q31_t)0x6dfa53e9, (q31_t)0x2c85244a, + (q31_t)0x6e0310d9, (q31_t)0x2c7c1c55, (q31_t)0x6e0bcc03, (q31_t)0x2c7312a9, + (q31_t)0x6e148566, (q31_t)0x2c6a0746, (q31_t)0x6e1d3d03, (q31_t)0x2c60fa2d, + (q31_t)0x6e25f2d8, (q31_t)0x2c57eb5e, (q31_t)0x6e2ea6e6, (q31_t)0x2c4edada, + (q31_t)0x6e37592c, (q31_t)0x2c45c8a0, (q31_t)0x6e4009aa, (q31_t)0x2c3cb4b1, + (q31_t)0x6e48b860, (q31_t)0x2c339f0e, (q31_t)0x6e51654c, (q31_t)0x2c2a87b6, + (q31_t)0x6e5a1070, (q31_t)0x2c216eaa, (q31_t)0x6e62b9ca, (q31_t)0x2c1853eb, + (q31_t)0x6e6b615a, (q31_t)0x2c0f3779, (q31_t)0x6e740720, (q31_t)0x2c061953, + (q31_t)0x6e7cab1c, (q31_t)0x2bfcf97c, (q31_t)0x6e854d4d, (q31_t)0x2bf3d7f2, + (q31_t)0x6e8dedb3, (q31_t)0x2beab4b6, (q31_t)0x6e968c4d, (q31_t)0x2be18fc9, + (q31_t)0x6e9f291b, (q31_t)0x2bd8692b, (q31_t)0x6ea7c41e, (q31_t)0x2bcf40dc, + (q31_t)0x6eb05d53, (q31_t)0x2bc616dd, (q31_t)0x6eb8f4bc, (q31_t)0x2bbceb2d, + (q31_t)0x6ec18a58, (q31_t)0x2bb3bdce, (q31_t)0x6eca1e27, (q31_t)0x2baa8ec0, + (q31_t)0x6ed2b027, (q31_t)0x2ba15e03, (q31_t)0x6edb405a, (q31_t)0x2b982b97, + (q31_t)0x6ee3cebe, (q31_t)0x2b8ef77d, (q31_t)0x6eec5b53, (q31_t)0x2b85c1b5, + (q31_t)0x6ef4e619, (q31_t)0x2b7c8a3f, (q31_t)0x6efd6f10, (q31_t)0x2b73511c, + (q31_t)0x6f05f637, (q31_t)0x2b6a164d, (q31_t)0x6f0e7b8e, (q31_t)0x2b60d9d0, + (q31_t)0x6f16ff14, (q31_t)0x2b579ba8, (q31_t)0x6f1f80ca, (q31_t)0x2b4e5bd4, + (q31_t)0x6f2800af, (q31_t)0x2b451a55, (q31_t)0x6f307ec2, (q31_t)0x2b3bd72a, + (q31_t)0x6f38fb03, (q31_t)0x2b329255, (q31_t)0x6f417573, (q31_t)0x2b294bd5, + (q31_t)0x6f49ee0f, (q31_t)0x2b2003ac, (q31_t)0x6f5264da, (q31_t)0x2b16b9d9, + (q31_t)0x6f5ad9d1, (q31_t)0x2b0d6e5c, (q31_t)0x6f634cf5, (q31_t)0x2b042137, + (q31_t)0x6f6bbe45, (q31_t)0x2afad269, (q31_t)0x6f742dc1, (q31_t)0x2af181f3, + (q31_t)0x6f7c9b69, (q31_t)0x2ae82fd5, (q31_t)0x6f85073c, (q31_t)0x2adedc10, + (q31_t)0x6f8d713a, (q31_t)0x2ad586a3, (q31_t)0x6f95d963, (q31_t)0x2acc2f90, + (q31_t)0x6f9e3fb6, (q31_t)0x2ac2d6d6, (q31_t)0x6fa6a433, (q31_t)0x2ab97c77, + (q31_t)0x6faf06da, (q31_t)0x2ab02071, (q31_t)0x6fb767aa, (q31_t)0x2aa6c2c6, + (q31_t)0x6fbfc6a3, (q31_t)0x2a9d6377, (q31_t)0x6fc823c5, (q31_t)0x2a940283, + (q31_t)0x6fd07f0f, (q31_t)0x2a8a9fea, (q31_t)0x6fd8d882, (q31_t)0x2a813bae, + (q31_t)0x6fe1301c, (q31_t)0x2a77d5ce, (q31_t)0x6fe985de, (q31_t)0x2a6e6e4b, + (q31_t)0x6ff1d9c7, (q31_t)0x2a650525, (q31_t)0x6ffa2bd6, (q31_t)0x2a5b9a5d, + (q31_t)0x70027c0c, (q31_t)0x2a522df3, (q31_t)0x700aca69, (q31_t)0x2a48bfe7, + (q31_t)0x701316eb, (q31_t)0x2a3f503a, (q31_t)0x701b6193, (q31_t)0x2a35deeb, + (q31_t)0x7023aa5f, (q31_t)0x2a2c6bfd, (q31_t)0x702bf151, (q31_t)0x2a22f76e, + (q31_t)0x70343667, (q31_t)0x2a19813f, (q31_t)0x703c79a2, (q31_t)0x2a100970, + (q31_t)0x7044bb00, (q31_t)0x2a069003, (q31_t)0x704cfa83, (q31_t)0x29fd14f6, + (q31_t)0x70553828, (q31_t)0x29f3984c, (q31_t)0x705d73f0, (q31_t)0x29ea1a03, + (q31_t)0x7065addb, (q31_t)0x29e09a1c, (q31_t)0x706de5e9, (q31_t)0x29d71899, + (q31_t)0x70761c18, (q31_t)0x29cd9578, (q31_t)0x707e5069, (q31_t)0x29c410ba, + (q31_t)0x708682dc, (q31_t)0x29ba8a61, (q31_t)0x708eb36f, (q31_t)0x29b1026c, + (q31_t)0x7096e223, (q31_t)0x29a778db, (q31_t)0x709f0ef8, (q31_t)0x299dedaf, + (q31_t)0x70a739ed, (q31_t)0x299460e8, (q31_t)0x70af6302, (q31_t)0x298ad287, + (q31_t)0x70b78a36, (q31_t)0x2981428c, (q31_t)0x70bfaf89, (q31_t)0x2977b0f7, + (q31_t)0x70c7d2fb, (q31_t)0x296e1dc9, (q31_t)0x70cff48c, (q31_t)0x29648902, + (q31_t)0x70d8143b, (q31_t)0x295af2a3, (q31_t)0x70e03208, (q31_t)0x29515aab, + (q31_t)0x70e84df3, (q31_t)0x2947c11c, (q31_t)0x70f067fb, (q31_t)0x293e25f5, + (q31_t)0x70f8801f, (q31_t)0x29348937, (q31_t)0x71009661, (q31_t)0x292aeae3, + (q31_t)0x7108aabf, (q31_t)0x29214af8, (q31_t)0x7110bd39, (q31_t)0x2917a977, + (q31_t)0x7118cdcf, (q31_t)0x290e0661, (q31_t)0x7120dc80, (q31_t)0x290461b5, + (q31_t)0x7128e94c, (q31_t)0x28fabb75, (q31_t)0x7130f433, (q31_t)0x28f113a0, + (q31_t)0x7138fd35, (q31_t)0x28e76a37, (q31_t)0x71410450, (q31_t)0x28ddbf3b, + (q31_t)0x71490986, (q31_t)0x28d412ab, (q31_t)0x71510cd5, (q31_t)0x28ca6488, + (q31_t)0x71590e3e, (q31_t)0x28c0b4d2, (q31_t)0x71610dbf, (q31_t)0x28b7038b, + (q31_t)0x71690b59, (q31_t)0x28ad50b1, (q31_t)0x7171070c, (q31_t)0x28a39c46, + (q31_t)0x717900d6, (q31_t)0x2899e64a, (q31_t)0x7180f8b8, (q31_t)0x28902ebd, + (q31_t)0x7188eeb2, (q31_t)0x288675a0, (q31_t)0x7190e2c3, (q31_t)0x287cbaf3, + (q31_t)0x7198d4ea, (q31_t)0x2872feb6, (q31_t)0x71a0c528, (q31_t)0x286940ea, + (q31_t)0x71a8b37c, (q31_t)0x285f8190, (q31_t)0x71b09fe7, (q31_t)0x2855c0a6, + (q31_t)0x71b88a66, (q31_t)0x284bfe2f, (q31_t)0x71c072fb, (q31_t)0x28423a2a, + (q31_t)0x71c859a5, (q31_t)0x28387498, (q31_t)0x71d03e64, (q31_t)0x282ead78, + (q31_t)0x71d82137, (q31_t)0x2824e4cc, (q31_t)0x71e0021e, (q31_t)0x281b1a94, + (q31_t)0x71e7e118, (q31_t)0x28114ed0, (q31_t)0x71efbe27, (q31_t)0x28078181, + (q31_t)0x71f79948, (q31_t)0x27fdb2a7, (q31_t)0x71ff727c, (q31_t)0x27f3e241, + (q31_t)0x720749c3, (q31_t)0x27ea1052, (q31_t)0x720f1f1c, (q31_t)0x27e03cd8, + (q31_t)0x7216f287, (q31_t)0x27d667d5, (q31_t)0x721ec403, (q31_t)0x27cc9149, + (q31_t)0x72269391, (q31_t)0x27c2b934, (q31_t)0x722e6130, (q31_t)0x27b8df97, + (q31_t)0x72362ce0, (q31_t)0x27af0472, (q31_t)0x723df6a0, (q31_t)0x27a527c4, + (q31_t)0x7245be70, (q31_t)0x279b4990, (q31_t)0x724d8450, (q31_t)0x279169d5, + (q31_t)0x72554840, (q31_t)0x27878893, (q31_t)0x725d0a3e, (q31_t)0x277da5cb, + (q31_t)0x7264ca4c, (q31_t)0x2773c17d, (q31_t)0x726c8868, (q31_t)0x2769dbaa, + (q31_t)0x72744493, (q31_t)0x275ff452, (q31_t)0x727bfecc, (q31_t)0x27560b76, + (q31_t)0x7283b712, (q31_t)0x274c2115, (q31_t)0x728b6d66, (q31_t)0x27423530, + (q31_t)0x729321c7, (q31_t)0x273847c8, (q31_t)0x729ad435, (q31_t)0x272e58dc, + (q31_t)0x72a284b0, (q31_t)0x2724686e, (q31_t)0x72aa3336, (q31_t)0x271a767e, + (q31_t)0x72b1dfc9, (q31_t)0x2710830c, (q31_t)0x72b98a67, (q31_t)0x27068e18, + (q31_t)0x72c13311, (q31_t)0x26fc97a3, (q31_t)0x72c8d9c6, (q31_t)0x26f29fad, + (q31_t)0x72d07e85, (q31_t)0x26e8a637, (q31_t)0x72d82150, (q31_t)0x26deab41, + (q31_t)0x72dfc224, (q31_t)0x26d4aecb, (q31_t)0x72e76102, (q31_t)0x26cab0d6, + (q31_t)0x72eefdea, (q31_t)0x26c0b162, (q31_t)0x72f698db, (q31_t)0x26b6b070, + (q31_t)0x72fe31d5, (q31_t)0x26acadff, (q31_t)0x7305c8d7, (q31_t)0x26a2aa11, + (q31_t)0x730d5de3, (q31_t)0x2698a4a6, (q31_t)0x7314f0f6, (q31_t)0x268e9dbd, + (q31_t)0x731c8211, (q31_t)0x26849558, (q31_t)0x73241134, (q31_t)0x267a8b77, + (q31_t)0x732b9e5e, (q31_t)0x2670801a, (q31_t)0x7333298f, (q31_t)0x26667342, + (q31_t)0x733ab2c6, (q31_t)0x265c64ef, (q31_t)0x73423a04, (q31_t)0x26525521, + (q31_t)0x7349bf48, (q31_t)0x264843d9, (q31_t)0x73514292, (q31_t)0x263e3117, + (q31_t)0x7358c3e2, (q31_t)0x26341cdb, (q31_t)0x73604336, (q31_t)0x262a0727, + (q31_t)0x7367c090, (q31_t)0x261feffa, (q31_t)0x736f3bee, (q31_t)0x2615d754, + (q31_t)0x7376b551, (q31_t)0x260bbd37, (q31_t)0x737e2cb7, (q31_t)0x2601a1a2, + (q31_t)0x7385a222, (q31_t)0x25f78497, (q31_t)0x738d1590, (q31_t)0x25ed6614, + (q31_t)0x73948701, (q31_t)0x25e3461b, (q31_t)0x739bf675, (q31_t)0x25d924ac, + (q31_t)0x73a363ec, (q31_t)0x25cf01c8, (q31_t)0x73aacf65, (q31_t)0x25c4dd6e, + (q31_t)0x73b238e0, (q31_t)0x25bab7a0, (q31_t)0x73b9a05d, (q31_t)0x25b0905d, + (q31_t)0x73c105db, (q31_t)0x25a667a7, (q31_t)0x73c8695b, (q31_t)0x259c3d7c, + (q31_t)0x73cfcadc, (q31_t)0x259211df, (q31_t)0x73d72a5d, (q31_t)0x2587e4cf, + (q31_t)0x73de87de, (q31_t)0x257db64c, (q31_t)0x73e5e360, (q31_t)0x25738657, + (q31_t)0x73ed3ce1, (q31_t)0x256954f1, (q31_t)0x73f49462, (q31_t)0x255f2219, + (q31_t)0x73fbe9e2, (q31_t)0x2554edd1, (q31_t)0x74033d61, (q31_t)0x254ab818, + (q31_t)0x740a8edf, (q31_t)0x254080ef, (q31_t)0x7411de5b, (q31_t)0x25364857, + (q31_t)0x74192bd5, (q31_t)0x252c0e4f, (q31_t)0x7420774d, (q31_t)0x2521d2d8, + (q31_t)0x7427c0c3, (q31_t)0x251795f3, (q31_t)0x742f0836, (q31_t)0x250d57a0, + (q31_t)0x74364da6, (q31_t)0x250317df, (q31_t)0x743d9112, (q31_t)0x24f8d6b0, + (q31_t)0x7444d27b, (q31_t)0x24ee9415, (q31_t)0x744c11e0, (q31_t)0x24e4500e, + (q31_t)0x74534f41, (q31_t)0x24da0a9a, (q31_t)0x745a8a9d, (q31_t)0x24cfc3ba, + (q31_t)0x7461c3f5, (q31_t)0x24c57b6f, (q31_t)0x7468fb47, (q31_t)0x24bb31ba, + (q31_t)0x74703095, (q31_t)0x24b0e699, (q31_t)0x747763dd, (q31_t)0x24a69a0f, + (q31_t)0x747e951f, (q31_t)0x249c4c1b, (q31_t)0x7485c45b, (q31_t)0x2491fcbe, + (q31_t)0x748cf190, (q31_t)0x2487abf7, (q31_t)0x74941cbf, (q31_t)0x247d59c8, + (q31_t)0x749b45e7, (q31_t)0x24730631, (q31_t)0x74a26d08, (q31_t)0x2468b132, + (q31_t)0x74a99221, (q31_t)0x245e5acc, (q31_t)0x74b0b533, (q31_t)0x245402ff, + (q31_t)0x74b7d63c, (q31_t)0x2449a9cc, (q31_t)0x74bef53d, (q31_t)0x243f4f32, + (q31_t)0x74c61236, (q31_t)0x2434f332, (q31_t)0x74cd2d26, (q31_t)0x242a95ce, + (q31_t)0x74d4460c, (q31_t)0x24203704, (q31_t)0x74db5cea, (q31_t)0x2415d6d5, + (q31_t)0x74e271bd, (q31_t)0x240b7543, (q31_t)0x74e98487, (q31_t)0x2401124d, + (q31_t)0x74f09546, (q31_t)0x23f6adf3, (q31_t)0x74f7a3fb, (q31_t)0x23ec4837, + (q31_t)0x74feb0a5, (q31_t)0x23e1e117, (q31_t)0x7505bb44, (q31_t)0x23d77896, + (q31_t)0x750cc3d8, (q31_t)0x23cd0eb3, (q31_t)0x7513ca60, (q31_t)0x23c2a36f, + (q31_t)0x751acedd, (q31_t)0x23b836ca, (q31_t)0x7521d14d, (q31_t)0x23adc8c4, + (q31_t)0x7528d1b1, (q31_t)0x23a3595e, (q31_t)0x752fd008, (q31_t)0x2398e898, + (q31_t)0x7536cc52, (q31_t)0x238e7673, (q31_t)0x753dc68f, (q31_t)0x238402ef, + (q31_t)0x7544bebf, (q31_t)0x23798e0d, (q31_t)0x754bb4e1, (q31_t)0x236f17cc, + (q31_t)0x7552a8f4, (q31_t)0x2364a02e, (q31_t)0x75599afa, (q31_t)0x235a2733, + (q31_t)0x75608af1, (q31_t)0x234facda, (q31_t)0x756778d9, (q31_t)0x23453125, + (q31_t)0x756e64b2, (q31_t)0x233ab414, (q31_t)0x75754e7c, (q31_t)0x233035a7, + (q31_t)0x757c3636, (q31_t)0x2325b5df, (q31_t)0x75831be0, (q31_t)0x231b34bc, + (q31_t)0x7589ff7a, (q31_t)0x2310b23e, (q31_t)0x7590e104, (q31_t)0x23062e67, + (q31_t)0x7597c07d, (q31_t)0x22fba936, (q31_t)0x759e9de5, (q31_t)0x22f122ab, + (q31_t)0x75a5793c, (q31_t)0x22e69ac8, (q31_t)0x75ac5282, (q31_t)0x22dc118c, + (q31_t)0x75b329b5, (q31_t)0x22d186f8, (q31_t)0x75b9fed7, (q31_t)0x22c6fb0c, + (q31_t)0x75c0d1e7, (q31_t)0x22bc6dca, (q31_t)0x75c7a2e3, (q31_t)0x22b1df30, + (q31_t)0x75ce71ce, (q31_t)0x22a74f40, (q31_t)0x75d53ea5, (q31_t)0x229cbdfa, + (q31_t)0x75dc0968, (q31_t)0x22922b5e, (q31_t)0x75e2d219, (q31_t)0x2287976e, + (q31_t)0x75e998b5, (q31_t)0x227d0228, (q31_t)0x75f05d3d, (q31_t)0x22726b8e, + (q31_t)0x75f71fb1, (q31_t)0x2267d3a0, (q31_t)0x75fde011, (q31_t)0x225d3a5e, + (q31_t)0x76049e5b, (q31_t)0x22529fca, (q31_t)0x760b5a90, (q31_t)0x224803e2, + (q31_t)0x761214b0, (q31_t)0x223d66a8, (q31_t)0x7618ccba, (q31_t)0x2232c81c, + (q31_t)0x761f82af, (q31_t)0x2228283f, (q31_t)0x7626368d, (q31_t)0x221d8711, + (q31_t)0x762ce855, (q31_t)0x2212e492, (q31_t)0x76339806, (q31_t)0x220840c2, + (q31_t)0x763a45a0, (q31_t)0x21fd9ba3, (q31_t)0x7640f123, (q31_t)0x21f2f534, + (q31_t)0x76479a8e, (q31_t)0x21e84d76, (q31_t)0x764e41e2, (q31_t)0x21dda46a, + (q31_t)0x7654e71d, (q31_t)0x21d2fa0f, (q31_t)0x765b8a41, (q31_t)0x21c84e67, + (q31_t)0x76622b4c, (q31_t)0x21bda171, (q31_t)0x7668ca3e, (q31_t)0x21b2f32e, + (q31_t)0x766f6717, (q31_t)0x21a8439e, (q31_t)0x767601d7, (q31_t)0x219d92c2, + (q31_t)0x767c9a7e, (q31_t)0x2192e09b, (q31_t)0x7683310b, (q31_t)0x21882d28, + (q31_t)0x7689c57d, (q31_t)0x217d786a, (q31_t)0x769057d6, (q31_t)0x2172c262, + (q31_t)0x7696e814, (q31_t)0x21680b0f, (q31_t)0x769d7637, (q31_t)0x215d5273, + (q31_t)0x76a4023f, (q31_t)0x2152988d, (q31_t)0x76aa8c2c, (q31_t)0x2147dd5f, + (q31_t)0x76b113fd, (q31_t)0x213d20e8, (q31_t)0x76b799b3, (q31_t)0x21326329, + (q31_t)0x76be1d4c, (q31_t)0x2127a423, (q31_t)0x76c49ec9, (q31_t)0x211ce3d5, + (q31_t)0x76cb1e2a, (q31_t)0x21122240, (q31_t)0x76d19b6e, (q31_t)0x21075f65, + (q31_t)0x76d81695, (q31_t)0x20fc9b44, (q31_t)0x76de8f9e, (q31_t)0x20f1d5de, + (q31_t)0x76e5068a, (q31_t)0x20e70f32, (q31_t)0x76eb7b58, (q31_t)0x20dc4742, + (q31_t)0x76f1ee09, (q31_t)0x20d17e0d, (q31_t)0x76f85e9a, (q31_t)0x20c6b395, + (q31_t)0x76fecd0e, (q31_t)0x20bbe7d8, (q31_t)0x77053962, (q31_t)0x20b11ad9, + (q31_t)0x770ba398, (q31_t)0x20a64c97, (q31_t)0x77120bae, (q31_t)0x209b7d13, + (q31_t)0x771871a5, (q31_t)0x2090ac4d, (q31_t)0x771ed57c, (q31_t)0x2085da46, + (q31_t)0x77253733, (q31_t)0x207b06fe, (q31_t)0x772b96ca, (q31_t)0x20703275, + (q31_t)0x7731f440, (q31_t)0x20655cac, (q31_t)0x77384f95, (q31_t)0x205a85a3, + (q31_t)0x773ea8ca, (q31_t)0x204fad5b, (q31_t)0x7744ffdd, (q31_t)0x2044d3d4, + (q31_t)0x774b54ce, (q31_t)0x2039f90f, (q31_t)0x7751a79e, (q31_t)0x202f1d0b, + (q31_t)0x7757f84c, (q31_t)0x20243fca, (q31_t)0x775e46d8, (q31_t)0x2019614c, + (q31_t)0x77649341, (q31_t)0x200e8190, (q31_t)0x776add88, (q31_t)0x2003a099, + (q31_t)0x777125ac, (q31_t)0x1ff8be65, (q31_t)0x77776bac, (q31_t)0x1feddaf6, + (q31_t)0x777daf89, (q31_t)0x1fe2f64c, (q31_t)0x7783f143, (q31_t)0x1fd81067, + (q31_t)0x778a30d8, (q31_t)0x1fcd2948, (q31_t)0x77906e49, (q31_t)0x1fc240ef, + (q31_t)0x7796a996, (q31_t)0x1fb7575c, (q31_t)0x779ce2be, (q31_t)0x1fac6c91, + (q31_t)0x77a319c2, (q31_t)0x1fa1808c, (q31_t)0x77a94ea0, (q31_t)0x1f969350, + (q31_t)0x77af8159, (q31_t)0x1f8ba4dc, (q31_t)0x77b5b1ec, (q31_t)0x1f80b531, + (q31_t)0x77bbe05a, (q31_t)0x1f75c44e, (q31_t)0x77c20ca1, (q31_t)0x1f6ad235, + (q31_t)0x77c836c2, (q31_t)0x1f5fdee6, (q31_t)0x77ce5ebd, (q31_t)0x1f54ea62, + (q31_t)0x77d48490, (q31_t)0x1f49f4a8, (q31_t)0x77daa83d, (q31_t)0x1f3efdb9, + (q31_t)0x77e0c9c3, (q31_t)0x1f340596, (q31_t)0x77e6e921, (q31_t)0x1f290c3f, + (q31_t)0x77ed0657, (q31_t)0x1f1e11b5, (q31_t)0x77f32165, (q31_t)0x1f1315f7, + (q31_t)0x77f93a4b, (q31_t)0x1f081907, (q31_t)0x77ff5109, (q31_t)0x1efd1ae4, + (q31_t)0x7805659e, (q31_t)0x1ef21b90, (q31_t)0x780b780a, (q31_t)0x1ee71b0a, + (q31_t)0x7811884d, (q31_t)0x1edc1953, (q31_t)0x78179666, (q31_t)0x1ed1166b, + (q31_t)0x781da256, (q31_t)0x1ec61254, (q31_t)0x7823ac1d, (q31_t)0x1ebb0d0d, + (q31_t)0x7829b3b9, (q31_t)0x1eb00696, (q31_t)0x782fb92a, (q31_t)0x1ea4fef0, + (q31_t)0x7835bc71, (q31_t)0x1e99f61d, (q31_t)0x783bbd8e, (q31_t)0x1e8eec1b, + (q31_t)0x7841bc7f, (q31_t)0x1e83e0eb, (q31_t)0x7847b946, (q31_t)0x1e78d48e, + (q31_t)0x784db3e0, (q31_t)0x1e6dc705, (q31_t)0x7853ac4f, (q31_t)0x1e62b84f, + (q31_t)0x7859a292, (q31_t)0x1e57a86d, (q31_t)0x785f96a9, (q31_t)0x1e4c9760, + (q31_t)0x78658894, (q31_t)0x1e418528, (q31_t)0x786b7852, (q31_t)0x1e3671c5, + (q31_t)0x787165e3, (q31_t)0x1e2b5d38, (q31_t)0x78775147, (q31_t)0x1e204781, + (q31_t)0x787d3a7e, (q31_t)0x1e1530a1, (q31_t)0x78832187, (q31_t)0x1e0a1898, + (q31_t)0x78890663, (q31_t)0x1dfeff67, (q31_t)0x788ee910, (q31_t)0x1df3e50d, + (q31_t)0x7894c98f, (q31_t)0x1de8c98c, (q31_t)0x789aa7e0, (q31_t)0x1dddace4, + (q31_t)0x78a08402, (q31_t)0x1dd28f15, (q31_t)0x78a65df6, (q31_t)0x1dc7701f, + (q31_t)0x78ac35ba, (q31_t)0x1dbc5004, (q31_t)0x78b20b4f, (q31_t)0x1db12ec3, + (q31_t)0x78b7deb4, (q31_t)0x1da60c5d, (q31_t)0x78bdafea, (q31_t)0x1d9ae8d2, + (q31_t)0x78c37eef, (q31_t)0x1d8fc424, (q31_t)0x78c94bc4, (q31_t)0x1d849e51, + (q31_t)0x78cf1669, (q31_t)0x1d79775c, (q31_t)0x78d4dedd, (q31_t)0x1d6e4f43, + (q31_t)0x78daa520, (q31_t)0x1d632608, (q31_t)0x78e06932, (q31_t)0x1d57fbaa, + (q31_t)0x78e62b13, (q31_t)0x1d4cd02c, (q31_t)0x78ebeac2, (q31_t)0x1d41a38c, + (q31_t)0x78f1a840, (q31_t)0x1d3675cb, (q31_t)0x78f7638b, (q31_t)0x1d2b46ea, + (q31_t)0x78fd1ca4, (q31_t)0x1d2016e9, (q31_t)0x7902d38b, (q31_t)0x1d14e5c9, + (q31_t)0x7908883f, (q31_t)0x1d09b389, (q31_t)0x790e3ac0, (q31_t)0x1cfe802b, + (q31_t)0x7913eb0e, (q31_t)0x1cf34baf, (q31_t)0x79199929, (q31_t)0x1ce81615, + (q31_t)0x791f4510, (q31_t)0x1cdcdf5e, (q31_t)0x7924eec3, (q31_t)0x1cd1a78a, + (q31_t)0x792a9642, (q31_t)0x1cc66e99, (q31_t)0x79303b8e, (q31_t)0x1cbb348d, + (q31_t)0x7935dea4, (q31_t)0x1caff965, (q31_t)0x793b7f86, (q31_t)0x1ca4bd21, + (q31_t)0x79411e33, (q31_t)0x1c997fc4, (q31_t)0x7946baac, (q31_t)0x1c8e414b, + (q31_t)0x794c54ee, (q31_t)0x1c8301b9, (q31_t)0x7951ecfc, (q31_t)0x1c77c10e, + (q31_t)0x795782d3, (q31_t)0x1c6c7f4a, (q31_t)0x795d1675, (q31_t)0x1c613c6d, + (q31_t)0x7962a7e0, (q31_t)0x1c55f878, (q31_t)0x79683715, (q31_t)0x1c4ab36b, + (q31_t)0x796dc414, (q31_t)0x1c3f6d47, (q31_t)0x79734edc, (q31_t)0x1c34260c, + (q31_t)0x7978d76c, (q31_t)0x1c28ddbb, (q31_t)0x797e5dc6, (q31_t)0x1c1d9454, + (q31_t)0x7983e1e8, (q31_t)0x1c1249d8, (q31_t)0x798963d2, (q31_t)0x1c06fe46, + (q31_t)0x798ee385, (q31_t)0x1bfbb1a0, (q31_t)0x799460ff, (q31_t)0x1bf063e6, + (q31_t)0x7999dc42, (q31_t)0x1be51518, (q31_t)0x799f554b, (q31_t)0x1bd9c537, + (q31_t)0x79a4cc1c, (q31_t)0x1bce7442, (q31_t)0x79aa40b4, (q31_t)0x1bc3223c, + (q31_t)0x79afb313, (q31_t)0x1bb7cf23, (q31_t)0x79b52339, (q31_t)0x1bac7af9, + (q31_t)0x79ba9125, (q31_t)0x1ba125bd, (q31_t)0x79bffcd7, (q31_t)0x1b95cf71, + (q31_t)0x79c5664f, (q31_t)0x1b8a7815, (q31_t)0x79cacd8d, (q31_t)0x1b7f1fa9, + (q31_t)0x79d03291, (q31_t)0x1b73c62d, (q31_t)0x79d5955a, (q31_t)0x1b686ba3, + (q31_t)0x79daf5e8, (q31_t)0x1b5d100a, (q31_t)0x79e0543c, (q31_t)0x1b51b363, + (q31_t)0x79e5b054, (q31_t)0x1b4655ae, (q31_t)0x79eb0a31, (q31_t)0x1b3af6ec, + (q31_t)0x79f061d2, (q31_t)0x1b2f971e, (q31_t)0x79f5b737, (q31_t)0x1b243643, + (q31_t)0x79fb0a60, (q31_t)0x1b18d45c, (q31_t)0x7a005b4d, (q31_t)0x1b0d716a, + (q31_t)0x7a05a9fd, (q31_t)0x1b020d6c, (q31_t)0x7a0af671, (q31_t)0x1af6a865, + (q31_t)0x7a1040a8, (q31_t)0x1aeb4253, (q31_t)0x7a1588a2, (q31_t)0x1adfdb37, + (q31_t)0x7a1ace5f, (q31_t)0x1ad47312, (q31_t)0x7a2011de, (q31_t)0x1ac909e5, + (q31_t)0x7a25531f, (q31_t)0x1abd9faf, (q31_t)0x7a2a9223, (q31_t)0x1ab23471, + (q31_t)0x7a2fcee8, (q31_t)0x1aa6c82b, (q31_t)0x7a350970, (q31_t)0x1a9b5adf, + (q31_t)0x7a3a41b9, (q31_t)0x1a8fec8c, (q31_t)0x7a3f77c3, (q31_t)0x1a847d33, + (q31_t)0x7a44ab8e, (q31_t)0x1a790cd4, (q31_t)0x7a49dd1a, (q31_t)0x1a6d9b70, + (q31_t)0x7a4f0c67, (q31_t)0x1a622907, (q31_t)0x7a543974, (q31_t)0x1a56b599, + (q31_t)0x7a596442, (q31_t)0x1a4b4128, (q31_t)0x7a5e8cd0, (q31_t)0x1a3fcbb3, + (q31_t)0x7a63b31d, (q31_t)0x1a34553b, (q31_t)0x7a68d72b, (q31_t)0x1a28ddc0, + (q31_t)0x7a6df8f8, (q31_t)0x1a1d6544, (q31_t)0x7a731884, (q31_t)0x1a11ebc5, + (q31_t)0x7a7835cf, (q31_t)0x1a067145, (q31_t)0x7a7d50da, (q31_t)0x19faf5c5, + (q31_t)0x7a8269a3, (q31_t)0x19ef7944, (q31_t)0x7a87802a, (q31_t)0x19e3fbc3, + (q31_t)0x7a8c9470, (q31_t)0x19d87d42, (q31_t)0x7a91a674, (q31_t)0x19ccfdc2, + (q31_t)0x7a96b636, (q31_t)0x19c17d44, (q31_t)0x7a9bc3b6, (q31_t)0x19b5fbc8, + (q31_t)0x7aa0cef3, (q31_t)0x19aa794d, (q31_t)0x7aa5d7ee, (q31_t)0x199ef5d6, + (q31_t)0x7aaadea6, (q31_t)0x19937161, (q31_t)0x7aafe31b, (q31_t)0x1987ebf0, + (q31_t)0x7ab4e54c, (q31_t)0x197c6584, (q31_t)0x7ab9e53a, (q31_t)0x1970de1b, + (q31_t)0x7abee2e5, (q31_t)0x196555b8, (q31_t)0x7ac3de4c, (q31_t)0x1959cc5a, + (q31_t)0x7ac8d76f, (q31_t)0x194e4201, (q31_t)0x7acdce4d, (q31_t)0x1942b6af, + (q31_t)0x7ad2c2e8, (q31_t)0x19372a64, (q31_t)0x7ad7b53d, (q31_t)0x192b9d1f, + (q31_t)0x7adca54e, (q31_t)0x19200ee3, (q31_t)0x7ae1931a, (q31_t)0x19147fae, + (q31_t)0x7ae67ea1, (q31_t)0x1908ef82, (q31_t)0x7aeb67e3, (q31_t)0x18fd5e5f, + (q31_t)0x7af04edf, (q31_t)0x18f1cc45, (q31_t)0x7af53395, (q31_t)0x18e63935, + (q31_t)0x7afa1605, (q31_t)0x18daa52f, (q31_t)0x7afef630, (q31_t)0x18cf1034, + (q31_t)0x7b03d414, (q31_t)0x18c37a44, (q31_t)0x7b08afb2, (q31_t)0x18b7e35f, + (q31_t)0x7b0d8909, (q31_t)0x18ac4b87, (q31_t)0x7b126019, (q31_t)0x18a0b2bb, + (q31_t)0x7b1734e2, (q31_t)0x189518fc, (q31_t)0x7b1c0764, (q31_t)0x18897e4a, + (q31_t)0x7b20d79e, (q31_t)0x187de2a7, (q31_t)0x7b25a591, (q31_t)0x18724611, + (q31_t)0x7b2a713d, (q31_t)0x1866a88a, (q31_t)0x7b2f3aa0, (q31_t)0x185b0a13, + (q31_t)0x7b3401bb, (q31_t)0x184f6aab, (q31_t)0x7b38c68e, (q31_t)0x1843ca53, + (q31_t)0x7b3d8918, (q31_t)0x1838290c, (q31_t)0x7b42495a, (q31_t)0x182c86d5, + (q31_t)0x7b470753, (q31_t)0x1820e3b0, (q31_t)0x7b4bc303, (q31_t)0x18153f9d, + (q31_t)0x7b507c69, (q31_t)0x18099a9c, (q31_t)0x7b553386, (q31_t)0x17fdf4ae, + (q31_t)0x7b59e85a, (q31_t)0x17f24dd3, (q31_t)0x7b5e9ae4, (q31_t)0x17e6a60c, + (q31_t)0x7b634b23, (q31_t)0x17dafd59, (q31_t)0x7b67f919, (q31_t)0x17cf53bb, + (q31_t)0x7b6ca4c4, (q31_t)0x17c3a931, (q31_t)0x7b714e25, (q31_t)0x17b7fdbd, + (q31_t)0x7b75f53c, (q31_t)0x17ac515f, (q31_t)0x7b7a9a07, (q31_t)0x17a0a417, + (q31_t)0x7b7f3c87, (q31_t)0x1794f5e6, (q31_t)0x7b83dcbc, (q31_t)0x178946cc, + (q31_t)0x7b887aa6, (q31_t)0x177d96ca, (q31_t)0x7b8d1644, (q31_t)0x1771e5e0, + (q31_t)0x7b91af97, (q31_t)0x1766340f, (q31_t)0x7b96469d, (q31_t)0x175a8157, + (q31_t)0x7b9adb57, (q31_t)0x174ecdb8, (q31_t)0x7b9f6dc5, (q31_t)0x17431933, + (q31_t)0x7ba3fde7, (q31_t)0x173763c9, (q31_t)0x7ba88bbc, (q31_t)0x172bad7a, + (q31_t)0x7bad1744, (q31_t)0x171ff646, (q31_t)0x7bb1a080, (q31_t)0x17143e2d, + (q31_t)0x7bb6276e, (q31_t)0x17088531, (q31_t)0x7bbaac0e, (q31_t)0x16fccb51, + (q31_t)0x7bbf2e62, (q31_t)0x16f1108f, (q31_t)0x7bc3ae67, (q31_t)0x16e554ea, + (q31_t)0x7bc82c1f, (q31_t)0x16d99864, (q31_t)0x7bcca789, (q31_t)0x16cddafb, + (q31_t)0x7bd120a4, (q31_t)0x16c21cb2, (q31_t)0x7bd59771, (q31_t)0x16b65d88, + (q31_t)0x7bda0bf0, (q31_t)0x16aa9d7e, (q31_t)0x7bde7e20, (q31_t)0x169edc94, + (q31_t)0x7be2ee01, (q31_t)0x16931acb, (q31_t)0x7be75b93, (q31_t)0x16875823, + (q31_t)0x7bebc6d5, (q31_t)0x167b949d, (q31_t)0x7bf02fc9, (q31_t)0x166fd039, + (q31_t)0x7bf4966c, (q31_t)0x16640af7, (q31_t)0x7bf8fac0, (q31_t)0x165844d8, + (q31_t)0x7bfd5cc4, (q31_t)0x164c7ddd, (q31_t)0x7c01bc78, (q31_t)0x1640b606, + (q31_t)0x7c0619dc, (q31_t)0x1634ed53, (q31_t)0x7c0a74f0, (q31_t)0x162923c5, + (q31_t)0x7c0ecdb2, (q31_t)0x161d595d, (q31_t)0x7c132424, (q31_t)0x16118e1a, + (q31_t)0x7c177845, (q31_t)0x1605c1fd, (q31_t)0x7c1bca16, (q31_t)0x15f9f507, + (q31_t)0x7c201994, (q31_t)0x15ee2738, (q31_t)0x7c2466c2, (q31_t)0x15e25890, + (q31_t)0x7c28b19e, (q31_t)0x15d68911, (q31_t)0x7c2cfa28, (q31_t)0x15cab8ba, + (q31_t)0x7c314060, (q31_t)0x15bee78c, (q31_t)0x7c358446, (q31_t)0x15b31587, + (q31_t)0x7c39c5da, (q31_t)0x15a742ac, (q31_t)0x7c3e051b, (q31_t)0x159b6efb, + (q31_t)0x7c42420a, (q31_t)0x158f9a76, (q31_t)0x7c467ca6, (q31_t)0x1583c51b, + (q31_t)0x7c4ab4ef, (q31_t)0x1577eeec, (q31_t)0x7c4eeae5, (q31_t)0x156c17e9, + (q31_t)0x7c531e88, (q31_t)0x15604013, (q31_t)0x7c574fd8, (q31_t)0x1554676a, + (q31_t)0x7c5b7ed4, (q31_t)0x15488dee, (q31_t)0x7c5fab7c, (q31_t)0x153cb3a0, + (q31_t)0x7c63d5d1, (q31_t)0x1530d881, (q31_t)0x7c67fdd1, (q31_t)0x1524fc90, + (q31_t)0x7c6c237e, (q31_t)0x15191fcf, (q31_t)0x7c7046d6, (q31_t)0x150d423d, + (q31_t)0x7c7467d9, (q31_t)0x150163dc, (q31_t)0x7c788688, (q31_t)0x14f584ac, + (q31_t)0x7c7ca2e2, (q31_t)0x14e9a4ac, (q31_t)0x7c80bce7, (q31_t)0x14ddc3de, + (q31_t)0x7c84d496, (q31_t)0x14d1e242, (q31_t)0x7c88e9f1, (q31_t)0x14c5ffd9, + (q31_t)0x7c8cfcf6, (q31_t)0x14ba1ca3, (q31_t)0x7c910da5, (q31_t)0x14ae38a0, + (q31_t)0x7c951bff, (q31_t)0x14a253d1, (q31_t)0x7c992803, (q31_t)0x14966e36, + (q31_t)0x7c9d31b0, (q31_t)0x148a87d1, (q31_t)0x7ca13908, (q31_t)0x147ea0a0, + (q31_t)0x7ca53e09, (q31_t)0x1472b8a5, (q31_t)0x7ca940b3, (q31_t)0x1466cfe1, + (q31_t)0x7cad4107, (q31_t)0x145ae653, (q31_t)0x7cb13f04, (q31_t)0x144efbfc, + (q31_t)0x7cb53aaa, (q31_t)0x144310dd, (q31_t)0x7cb933f9, (q31_t)0x143724f5, + (q31_t)0x7cbd2af0, (q31_t)0x142b3846, (q31_t)0x7cc11f90, (q31_t)0x141f4ad1, + (q31_t)0x7cc511d9, (q31_t)0x14135c94, (q31_t)0x7cc901c9, (q31_t)0x14076d91, + (q31_t)0x7cccef62, (q31_t)0x13fb7dc9, (q31_t)0x7cd0daa2, (q31_t)0x13ef8d3c, + (q31_t)0x7cd4c38b, (q31_t)0x13e39be9, (q31_t)0x7cd8aa1b, (q31_t)0x13d7a9d3, + (q31_t)0x7cdc8e52, (q31_t)0x13cbb6f8, (q31_t)0x7ce07031, (q31_t)0x13bfc35b, + (q31_t)0x7ce44fb7, (q31_t)0x13b3cefa, (q31_t)0x7ce82ce4, (q31_t)0x13a7d9d7, + (q31_t)0x7cec07b8, (q31_t)0x139be3f2, (q31_t)0x7cefe032, (q31_t)0x138fed4b, + (q31_t)0x7cf3b653, (q31_t)0x1383f5e3, (q31_t)0x7cf78a1b, (q31_t)0x1377fdbb, + (q31_t)0x7cfb5b89, (q31_t)0x136c04d2, (q31_t)0x7cff2a9d, (q31_t)0x13600b2a, + (q31_t)0x7d02f757, (q31_t)0x135410c3, (q31_t)0x7d06c1b6, (q31_t)0x1348159d, + (q31_t)0x7d0a89bc, (q31_t)0x133c19b8, (q31_t)0x7d0e4f67, (q31_t)0x13301d16, + (q31_t)0x7d1212b7, (q31_t)0x13241fb6, (q31_t)0x7d15d3ad, (q31_t)0x1318219a, + (q31_t)0x7d199248, (q31_t)0x130c22c1, (q31_t)0x7d1d4e88, (q31_t)0x1300232c, + (q31_t)0x7d21086c, (q31_t)0x12f422db, (q31_t)0x7d24bff6, (q31_t)0x12e821cf, + (q31_t)0x7d287523, (q31_t)0x12dc2009, (q31_t)0x7d2c27f6, (q31_t)0x12d01d89, + (q31_t)0x7d2fd86c, (q31_t)0x12c41a4f, (q31_t)0x7d338687, (q31_t)0x12b8165b, + (q31_t)0x7d373245, (q31_t)0x12ac11af, (q31_t)0x7d3adba7, (q31_t)0x12a00c4b, + (q31_t)0x7d3e82ae, (q31_t)0x1294062f, (q31_t)0x7d422757, (q31_t)0x1287ff5b, + (q31_t)0x7d45c9a4, (q31_t)0x127bf7d1, (q31_t)0x7d496994, (q31_t)0x126fef90, + (q31_t)0x7d4d0728, (q31_t)0x1263e699, (q31_t)0x7d50a25e, (q31_t)0x1257dced, + (q31_t)0x7d543b37, (q31_t)0x124bd28c, (q31_t)0x7d57d1b3, (q31_t)0x123fc776, + (q31_t)0x7d5b65d2, (q31_t)0x1233bbac, (q31_t)0x7d5ef793, (q31_t)0x1227af2e, + (q31_t)0x7d6286f6, (q31_t)0x121ba1fd, (q31_t)0x7d6613fb, (q31_t)0x120f941a, + (q31_t)0x7d699ea3, (q31_t)0x12038584, (q31_t)0x7d6d26ec, (q31_t)0x11f7763c, + (q31_t)0x7d70acd7, (q31_t)0x11eb6643, (q31_t)0x7d743064, (q31_t)0x11df5599, + (q31_t)0x7d77b192, (q31_t)0x11d3443f, (q31_t)0x7d7b3061, (q31_t)0x11c73235, + (q31_t)0x7d7eacd2, (q31_t)0x11bb1f7c, (q31_t)0x7d8226e4, (q31_t)0x11af0c13, + (q31_t)0x7d859e96, (q31_t)0x11a2f7fc, (q31_t)0x7d8913ea, (q31_t)0x1196e337, + (q31_t)0x7d8c86de, (q31_t)0x118acdc4, (q31_t)0x7d8ff772, (q31_t)0x117eb7a4, + (q31_t)0x7d9365a8, (q31_t)0x1172a0d7, (q31_t)0x7d96d17d, (q31_t)0x1166895f, + (q31_t)0x7d9a3af2, (q31_t)0x115a713a, (q31_t)0x7d9da208, (q31_t)0x114e586a, + (q31_t)0x7da106bd, (q31_t)0x11423ef0, (q31_t)0x7da46912, (q31_t)0x113624cb, + (q31_t)0x7da7c907, (q31_t)0x112a09fc, (q31_t)0x7dab269b, (q31_t)0x111dee84, + (q31_t)0x7dae81cf, (q31_t)0x1111d263, (q31_t)0x7db1daa2, (q31_t)0x1105b599, + (q31_t)0x7db53113, (q31_t)0x10f99827, (q31_t)0x7db88524, (q31_t)0x10ed7a0e, + (q31_t)0x7dbbd6d4, (q31_t)0x10e15b4e, (q31_t)0x7dbf2622, (q31_t)0x10d53be7, + (q31_t)0x7dc2730f, (q31_t)0x10c91bda, (q31_t)0x7dc5bd9b, (q31_t)0x10bcfb28, + (q31_t)0x7dc905c5, (q31_t)0x10b0d9d0, (q31_t)0x7dcc4b8d, (q31_t)0x10a4b7d3, + (q31_t)0x7dcf8ef3, (q31_t)0x10989532, (q31_t)0x7dd2cff7, (q31_t)0x108c71ee, + (q31_t)0x7dd60e99, (q31_t)0x10804e06, (q31_t)0x7dd94ad8, (q31_t)0x1074297b, + (q31_t)0x7ddc84b5, (q31_t)0x1068044e, (q31_t)0x7ddfbc30, (q31_t)0x105bde7f, + (q31_t)0x7de2f148, (q31_t)0x104fb80e, (q31_t)0x7de623fd, (q31_t)0x104390fd, + (q31_t)0x7de9544f, (q31_t)0x1037694b, (q31_t)0x7dec823e, (q31_t)0x102b40f8, + (q31_t)0x7defadca, (q31_t)0x101f1807, (q31_t)0x7df2d6f3, (q31_t)0x1012ee76, + (q31_t)0x7df5fdb8, (q31_t)0x1006c446, (q31_t)0x7df9221a, (q31_t)0xffa9979, + (q31_t)0x7dfc4418, (q31_t)0xfee6e0d, (q31_t)0x7dff63b2, (q31_t)0xfe24205, + (q31_t)0x7e0280e9, (q31_t)0xfd6155f, (q31_t)0x7e059bbb, (q31_t)0xfc9e81e, + (q31_t)0x7e08b42a, (q31_t)0xfbdba40, (q31_t)0x7e0bca34, (q31_t)0xfb18bc8, + (q31_t)0x7e0eddd9, (q31_t)0xfa55cb4, (q31_t)0x7e11ef1b, (q31_t)0xf992d06, + (q31_t)0x7e14fdf7, (q31_t)0xf8cfcbe, (q31_t)0x7e180a6f, (q31_t)0xf80cbdc, + (q31_t)0x7e1b1482, (q31_t)0xf749a61, (q31_t)0x7e1e1c30, (q31_t)0xf68684e, + (q31_t)0x7e212179, (q31_t)0xf5c35a3, (q31_t)0x7e24245d, (q31_t)0xf500260, + (q31_t)0x7e2724db, (q31_t)0xf43ce86, (q31_t)0x7e2a22f4, (q31_t)0xf379a16, + (q31_t)0x7e2d1ea8, (q31_t)0xf2b650f, (q31_t)0x7e3017f6, (q31_t)0xf1f2f73, + (q31_t)0x7e330ede, (q31_t)0xf12f941, (q31_t)0x7e360360, (q31_t)0xf06c27a, + (q31_t)0x7e38f57c, (q31_t)0xefa8b20, (q31_t)0x7e3be532, (q31_t)0xeee5331, + (q31_t)0x7e3ed282, (q31_t)0xee21aaf, (q31_t)0x7e41bd6c, (q31_t)0xed5e19a, + (q31_t)0x7e44a5ef, (q31_t)0xec9a7f3, (q31_t)0x7e478c0b, (q31_t)0xebd6db9, + (q31_t)0x7e4a6fc1, (q31_t)0xeb132ef, (q31_t)0x7e4d5110, (q31_t)0xea4f793, + (q31_t)0x7e502ff9, (q31_t)0xe98bba7, (q31_t)0x7e530c7a, (q31_t)0xe8c7f2a, + (q31_t)0x7e55e694, (q31_t)0xe80421e, (q31_t)0x7e58be47, (q31_t)0xe740483, + (q31_t)0x7e5b9392, (q31_t)0xe67c65a, (q31_t)0x7e5e6676, (q31_t)0xe5b87a2, + (q31_t)0x7e6136f3, (q31_t)0xe4f485c, (q31_t)0x7e640507, (q31_t)0xe430889, + (q31_t)0x7e66d0b4, (q31_t)0xe36c82a, (q31_t)0x7e6999fa, (q31_t)0xe2a873e, + (q31_t)0x7e6c60d7, (q31_t)0xe1e45c6, (q31_t)0x7e6f254c, (q31_t)0xe1203c3, + (q31_t)0x7e71e759, (q31_t)0xe05c135, (q31_t)0x7e74a6fd, (q31_t)0xdf97e1d, + (q31_t)0x7e77643a, (q31_t)0xded3a7b, (q31_t)0x7e7a1f0d, (q31_t)0xde0f64f, + (q31_t)0x7e7cd778, (q31_t)0xdd4b19a, (q31_t)0x7e7f8d7b, (q31_t)0xdc86c5d, + (q31_t)0x7e824114, (q31_t)0xdbc2698, (q31_t)0x7e84f245, (q31_t)0xdafe04b, + (q31_t)0x7e87a10c, (q31_t)0xda39978, (q31_t)0x7e8a4d6a, (q31_t)0xd97521d, + (q31_t)0x7e8cf75f, (q31_t)0xd8b0a3d, (q31_t)0x7e8f9eeb, (q31_t)0xd7ec1d6, + (q31_t)0x7e92440d, (q31_t)0xd7278eb, (q31_t)0x7e94e6c6, (q31_t)0xd662f7b, + (q31_t)0x7e978715, (q31_t)0xd59e586, (q31_t)0x7e9a24fb, (q31_t)0xd4d9b0e, + (q31_t)0x7e9cc076, (q31_t)0xd415013, (q31_t)0x7e9f5988, (q31_t)0xd350495, + (q31_t)0x7ea1f02f, (q31_t)0xd28b894, (q31_t)0x7ea4846c, (q31_t)0xd1c6c11, + (q31_t)0x7ea7163f, (q31_t)0xd101f0e, (q31_t)0x7ea9a5a8, (q31_t)0xd03d189, + (q31_t)0x7eac32a6, (q31_t)0xcf78383, (q31_t)0x7eaebd3a, (q31_t)0xceb34fe, + (q31_t)0x7eb14563, (q31_t)0xcdee5f9, (q31_t)0x7eb3cb21, (q31_t)0xcd29676, + (q31_t)0x7eb64e75, (q31_t)0xcc64673, (q31_t)0x7eb8cf5d, (q31_t)0xcb9f5f3, + (q31_t)0x7ebb4ddb, (q31_t)0xcada4f5, (q31_t)0x7ebdc9ed, (q31_t)0xca1537a, + (q31_t)0x7ec04394, (q31_t)0xc950182, (q31_t)0x7ec2bad0, (q31_t)0xc88af0e, + (q31_t)0x7ec52fa0, (q31_t)0xc7c5c1e, (q31_t)0x7ec7a205, (q31_t)0xc7008b3, + (q31_t)0x7eca11fe, (q31_t)0xc63b4ce, (q31_t)0x7ecc7f8b, (q31_t)0xc57606e, + (q31_t)0x7eceeaad, (q31_t)0xc4b0b94, (q31_t)0x7ed15363, (q31_t)0xc3eb641, + (q31_t)0x7ed3b9ad, (q31_t)0xc326075, (q31_t)0x7ed61d8a, (q31_t)0xc260a31, + (q31_t)0x7ed87efc, (q31_t)0xc19b374, (q31_t)0x7edade01, (q31_t)0xc0d5c41, + (q31_t)0x7edd3a9a, (q31_t)0xc010496, (q31_t)0x7edf94c7, (q31_t)0xbf4ac75, + (q31_t)0x7ee1ec87, (q31_t)0xbe853de, (q31_t)0x7ee441da, (q31_t)0xbdbfad1, + (q31_t)0x7ee694c1, (q31_t)0xbcfa150, (q31_t)0x7ee8e53a, (q31_t)0xbc34759, + (q31_t)0x7eeb3347, (q31_t)0xbb6ecef, (q31_t)0x7eed7ee7, (q31_t)0xbaa9211, + (q31_t)0x7eefc81a, (q31_t)0xb9e36c0, (q31_t)0x7ef20ee0, (q31_t)0xb91dafc, + (q31_t)0x7ef45338, (q31_t)0xb857ec7, (q31_t)0x7ef69523, (q31_t)0xb79221f, + (q31_t)0x7ef8d4a1, (q31_t)0xb6cc506, (q31_t)0x7efb11b1, (q31_t)0xb60677c, + (q31_t)0x7efd4c54, (q31_t)0xb540982, (q31_t)0x7eff8489, (q31_t)0xb47ab19, + (q31_t)0x7f01ba50, (q31_t)0xb3b4c40, (q31_t)0x7f03eda9, (q31_t)0xb2eecf8, + (q31_t)0x7f061e95, (q31_t)0xb228d42, (q31_t)0x7f084d12, (q31_t)0xb162d1d, + (q31_t)0x7f0a7921, (q31_t)0xb09cc8c, (q31_t)0x7f0ca2c2, (q31_t)0xafd6b8d, + (q31_t)0x7f0ec9f5, (q31_t)0xaf10a22, (q31_t)0x7f10eeb9, (q31_t)0xae4a84b, + (q31_t)0x7f13110f, (q31_t)0xad84609, (q31_t)0x7f1530f7, (q31_t)0xacbe35b, + (q31_t)0x7f174e70, (q31_t)0xabf8043, (q31_t)0x7f19697a, (q31_t)0xab31cc1, + (q31_t)0x7f1b8215, (q31_t)0xaa6b8d5, (q31_t)0x7f1d9842, (q31_t)0xa9a5480, + (q31_t)0x7f1fabff, (q31_t)0xa8defc3, (q31_t)0x7f21bd4e, (q31_t)0xa818a9d, + (q31_t)0x7f23cc2e, (q31_t)0xa752510, (q31_t)0x7f25d89e, (q31_t)0xa68bf1b, + (q31_t)0x7f27e29f, (q31_t)0xa5c58c0, (q31_t)0x7f29ea31, (q31_t)0xa4ff1fe, + (q31_t)0x7f2bef53, (q31_t)0xa438ad7, (q31_t)0x7f2df206, (q31_t)0xa37234a, + (q31_t)0x7f2ff24a, (q31_t)0xa2abb59, (q31_t)0x7f31f01d, (q31_t)0xa1e5303, + (q31_t)0x7f33eb81, (q31_t)0xa11ea49, (q31_t)0x7f35e476, (q31_t)0xa05812c, + (q31_t)0x7f37dafa, (q31_t)0x9f917ac, (q31_t)0x7f39cf0e, (q31_t)0x9ecadc9, + (q31_t)0x7f3bc0b3, (q31_t)0x9e04385, (q31_t)0x7f3dafe7, (q31_t)0x9d3d8df, + (q31_t)0x7f3f9cab, (q31_t)0x9c76dd8, (q31_t)0x7f4186ff, (q31_t)0x9bb0271, + (q31_t)0x7f436ee3, (q31_t)0x9ae96aa, (q31_t)0x7f455456, (q31_t)0x9a22a83, + (q31_t)0x7f473759, (q31_t)0x995bdfd, (q31_t)0x7f4917eb, (q31_t)0x9895118, + (q31_t)0x7f4af60d, (q31_t)0x97ce3d5, (q31_t)0x7f4cd1be, (q31_t)0x9707635, + (q31_t)0x7f4eaafe, (q31_t)0x9640837, (q31_t)0x7f5081cd, (q31_t)0x95799dd, + (q31_t)0x7f52562c, (q31_t)0x94b2b27, (q31_t)0x7f54281a, (q31_t)0x93ebc14, + (q31_t)0x7f55f796, (q31_t)0x9324ca7, (q31_t)0x7f57c4a2, (q31_t)0x925dcdf, + (q31_t)0x7f598f3c, (q31_t)0x9196cbc, (q31_t)0x7f5b5765, (q31_t)0x90cfc40, + (q31_t)0x7f5d1d1d, (q31_t)0x9008b6a, (q31_t)0x7f5ee063, (q31_t)0x8f41a3c, + (q31_t)0x7f60a138, (q31_t)0x8e7a8b5, (q31_t)0x7f625f9b, (q31_t)0x8db36d6, + (q31_t)0x7f641b8d, (q31_t)0x8cec4a0, (q31_t)0x7f65d50d, (q31_t)0x8c25213, + (q31_t)0x7f678c1c, (q31_t)0x8b5df30, (q31_t)0x7f6940b8, (q31_t)0x8a96bf6, + (q31_t)0x7f6af2e3, (q31_t)0x89cf867, (q31_t)0x7f6ca29c, (q31_t)0x8908483, + (q31_t)0x7f6e4fe3, (q31_t)0x884104b, (q31_t)0x7f6ffab8, (q31_t)0x8779bbe, + (q31_t)0x7f71a31b, (q31_t)0x86b26de, (q31_t)0x7f73490b, (q31_t)0x85eb1ab, + (q31_t)0x7f74ec8a, (q31_t)0x8523c25, (q31_t)0x7f768d96, (q31_t)0x845c64d, + (q31_t)0x7f782c30, (q31_t)0x8395024, (q31_t)0x7f79c857, (q31_t)0x82cd9a9, + (q31_t)0x7f7b620c, (q31_t)0x82062de, (q31_t)0x7f7cf94e, (q31_t)0x813ebc2, + (q31_t)0x7f7e8e1e, (q31_t)0x8077457, (q31_t)0x7f80207b, (q31_t)0x7fafc9c, + (q31_t)0x7f81b065, (q31_t)0x7ee8493, (q31_t)0x7f833ddd, (q31_t)0x7e20c3b, + (q31_t)0x7f84c8e2, (q31_t)0x7d59396, (q31_t)0x7f865174, (q31_t)0x7c91aa3, + (q31_t)0x7f87d792, (q31_t)0x7bca163, (q31_t)0x7f895b3e, (q31_t)0x7b027d7, + (q31_t)0x7f8adc77, (q31_t)0x7a3adff, (q31_t)0x7f8c5b3d, (q31_t)0x79733dc, + (q31_t)0x7f8dd78f, (q31_t)0x78ab96e, (q31_t)0x7f8f516e, (q31_t)0x77e3eb5, + (q31_t)0x7f90c8da, (q31_t)0x771c3b3, (q31_t)0x7f923dd2, (q31_t)0x7654867, + (q31_t)0x7f93b058, (q31_t)0x758ccd2, (q31_t)0x7f952069, (q31_t)0x74c50f4, + (q31_t)0x7f968e07, (q31_t)0x73fd4cf, (q31_t)0x7f97f932, (q31_t)0x7335862, + (q31_t)0x7f9961e8, (q31_t)0x726dbae, (q31_t)0x7f9ac82c, (q31_t)0x71a5eb3, + (q31_t)0x7f9c2bfb, (q31_t)0x70de172, (q31_t)0x7f9d8d56, (q31_t)0x70163eb, + (q31_t)0x7f9eec3e, (q31_t)0x6f4e620, (q31_t)0x7fa048b2, (q31_t)0x6e86810, + (q31_t)0x7fa1a2b2, (q31_t)0x6dbe9bb, (q31_t)0x7fa2fa3d, (q31_t)0x6cf6b23, + (q31_t)0x7fa44f55, (q31_t)0x6c2ec48, (q31_t)0x7fa5a1f9, (q31_t)0x6b66d29, + (q31_t)0x7fa6f228, (q31_t)0x6a9edc9, (q31_t)0x7fa83fe3, (q31_t)0x69d6e27, + (q31_t)0x7fa98b2a, (q31_t)0x690ee44, (q31_t)0x7faad3fd, (q31_t)0x6846e1f, + (q31_t)0x7fac1a5b, (q31_t)0x677edbb, (q31_t)0x7fad5e45, (q31_t)0x66b6d16, + (q31_t)0x7fae9fbb, (q31_t)0x65eec33, (q31_t)0x7fafdebb, (q31_t)0x6526b10, + (q31_t)0x7fb11b48, (q31_t)0x645e9af, (q31_t)0x7fb2555f, (q31_t)0x6396810, + (q31_t)0x7fb38d02, (q31_t)0x62ce634, (q31_t)0x7fb4c231, (q31_t)0x620641a, + (q31_t)0x7fb5f4ea, (q31_t)0x613e1c5, (q31_t)0x7fb7252f, (q31_t)0x6075f33, + (q31_t)0x7fb852ff, (q31_t)0x5fadc66, (q31_t)0x7fb97e5a, (q31_t)0x5ee595d, + (q31_t)0x7fbaa740, (q31_t)0x5e1d61b, (q31_t)0x7fbbcdb1, (q31_t)0x5d5529e, + (q31_t)0x7fbcf1ad, (q31_t)0x5c8cee7, (q31_t)0x7fbe1334, (q31_t)0x5bc4af8, + (q31_t)0x7fbf3246, (q31_t)0x5afc6d0, (q31_t)0x7fc04ee3, (q31_t)0x5a3426f, + (q31_t)0x7fc1690a, (q31_t)0x596bdd7, (q31_t)0x7fc280bc, (q31_t)0x58a3908, + (q31_t)0x7fc395f9, (q31_t)0x57db403, (q31_t)0x7fc4a8c1, (q31_t)0x5712ec7, + (q31_t)0x7fc5b913, (q31_t)0x564a955, (q31_t)0x7fc6c6f0, (q31_t)0x55823ae, + (q31_t)0x7fc7d258, (q31_t)0x54b9dd3, (q31_t)0x7fc8db4a, (q31_t)0x53f17c3, + (q31_t)0x7fc9e1c6, (q31_t)0x532917f, (q31_t)0x7fcae5cd, (q31_t)0x5260b08, + (q31_t)0x7fcbe75e, (q31_t)0x519845e, (q31_t)0x7fcce67a, (q31_t)0x50cfd82, + (q31_t)0x7fcde320, (q31_t)0x5007674, (q31_t)0x7fcedd50, (q31_t)0x4f3ef35, + (q31_t)0x7fcfd50b, (q31_t)0x4e767c5, (q31_t)0x7fd0ca4f, (q31_t)0x4dae024, + (q31_t)0x7fd1bd1e, (q31_t)0x4ce5854, (q31_t)0x7fd2ad77, (q31_t)0x4c1d054, + (q31_t)0x7fd39b5a, (q31_t)0x4b54825, (q31_t)0x7fd486c7, (q31_t)0x4a8bfc7, + (q31_t)0x7fd56fbe, (q31_t)0x49c373c, (q31_t)0x7fd6563f, (q31_t)0x48fae83, + (q31_t)0x7fd73a4a, (q31_t)0x483259d, (q31_t)0x7fd81bdf, (q31_t)0x4769c8b, + (q31_t)0x7fd8fafe, (q31_t)0x46a134c, (q31_t)0x7fd9d7a7, (q31_t)0x45d89e2, + (q31_t)0x7fdab1d9, (q31_t)0x451004d, (q31_t)0x7fdb8996, (q31_t)0x444768d, + (q31_t)0x7fdc5edc, (q31_t)0x437eca4, (q31_t)0x7fdd31ac, (q31_t)0x42b6290, + (q31_t)0x7fde0205, (q31_t)0x41ed854, (q31_t)0x7fdecfe8, (q31_t)0x4124dee, + (q31_t)0x7fdf9b55, (q31_t)0x405c361, (q31_t)0x7fe0644b, (q31_t)0x3f938ac, + (q31_t)0x7fe12acb, (q31_t)0x3ecadcf, (q31_t)0x7fe1eed5, (q31_t)0x3e022cc, + (q31_t)0x7fe2b067, (q31_t)0x3d397a3, (q31_t)0x7fe36f84, (q31_t)0x3c70c54, + (q31_t)0x7fe42c2a, (q31_t)0x3ba80df, (q31_t)0x7fe4e659, (q31_t)0x3adf546, + (q31_t)0x7fe59e12, (q31_t)0x3a16988, (q31_t)0x7fe65354, (q31_t)0x394dda7, + (q31_t)0x7fe7061f, (q31_t)0x38851a2, (q31_t)0x7fe7b674, (q31_t)0x37bc57b, + (q31_t)0x7fe86452, (q31_t)0x36f3931, (q31_t)0x7fe90fb9, (q31_t)0x362acc5, + (q31_t)0x7fe9b8a9, (q31_t)0x3562038, (q31_t)0x7fea5f23, (q31_t)0x3499389, + (q31_t)0x7feb0326, (q31_t)0x33d06bb, (q31_t)0x7feba4b2, (q31_t)0x33079cc, + (q31_t)0x7fec43c7, (q31_t)0x323ecbe, (q31_t)0x7fece065, (q31_t)0x3175f91, + (q31_t)0x7fed7a8c, (q31_t)0x30ad245, (q31_t)0x7fee123d, (q31_t)0x2fe44dc, + (q31_t)0x7feea776, (q31_t)0x2f1b755, (q31_t)0x7fef3a39, (q31_t)0x2e529b0, + (q31_t)0x7fefca84, (q31_t)0x2d89bf0, (q31_t)0x7ff05858, (q31_t)0x2cc0e13, + (q31_t)0x7ff0e3b6, (q31_t)0x2bf801a, (q31_t)0x7ff16c9c, (q31_t)0x2b2f207, + (q31_t)0x7ff1f30b, (q31_t)0x2a663d8, (q31_t)0x7ff27703, (q31_t)0x299d590, + (q31_t)0x7ff2f884, (q31_t)0x28d472e, (q31_t)0x7ff3778e, (q31_t)0x280b8b3, + (q31_t)0x7ff3f420, (q31_t)0x2742a1f, (q31_t)0x7ff46e3c, (q31_t)0x2679b73, + (q31_t)0x7ff4e5e0, (q31_t)0x25b0caf, (q31_t)0x7ff55b0d, (q31_t)0x24e7dd4, + (q31_t)0x7ff5cdc3, (q31_t)0x241eee2, (q31_t)0x7ff63e01, (q31_t)0x2355fd9, + (q31_t)0x7ff6abc8, (q31_t)0x228d0bb, (q31_t)0x7ff71718, (q31_t)0x21c4188, + (q31_t)0x7ff77ff1, (q31_t)0x20fb240, (q31_t)0x7ff7e652, (q31_t)0x20322e3, + (q31_t)0x7ff84a3c, (q31_t)0x1f69373, (q31_t)0x7ff8abae, (q31_t)0x1ea03ef, + (q31_t)0x7ff90aaa, (q31_t)0x1dd7459, (q31_t)0x7ff9672d, (q31_t)0x1d0e4b0, + (q31_t)0x7ff9c13a, (q31_t)0x1c454f5, (q31_t)0x7ffa18cf, (q31_t)0x1b7c528, + (q31_t)0x7ffa6dec, (q31_t)0x1ab354b, (q31_t)0x7ffac092, (q31_t)0x19ea55d, + (q31_t)0x7ffb10c1, (q31_t)0x192155f, (q31_t)0x7ffb5e78, (q31_t)0x1858552, + (q31_t)0x7ffba9b8, (q31_t)0x178f536, (q31_t)0x7ffbf280, (q31_t)0x16c650b, + (q31_t)0x7ffc38d1, (q31_t)0x15fd4d2, (q31_t)0x7ffc7caa, (q31_t)0x153448c, + (q31_t)0x7ffcbe0c, (q31_t)0x146b438, (q31_t)0x7ffcfcf6, (q31_t)0x13a23d8, + (q31_t)0x7ffd3969, (q31_t)0x12d936c, (q31_t)0x7ffd7364, (q31_t)0x12102f4, + (q31_t)0x7ffdaae7, (q31_t)0x1147271, (q31_t)0x7ffddff3, (q31_t)0x107e1e3, + (q31_t)0x7ffe1288, (q31_t)0xfb514b, (q31_t)0x7ffe42a4, (q31_t)0xeec0aa, + (q31_t)0x7ffe704a, (q31_t)0xe22fff, (q31_t)0x7ffe9b77, (q31_t)0xd59f4c, + (q31_t)0x7ffec42d, (q31_t)0xc90e90, (q31_t)0x7ffeea6c, (q31_t)0xbc7dcc, + (q31_t)0x7fff0e32, (q31_t)0xafed02, (q31_t)0x7fff2f82, (q31_t)0xa35c30, + (q31_t)0x7fff4e59, (q31_t)0x96cb58, (q31_t)0x7fff6ab9, (q31_t)0x8a3a7b, + (q31_t)0x7fff84a1, (q31_t)0x7da998, (q31_t)0x7fff9c12, (q31_t)0x7118b0, + (q31_t)0x7fffb10b, (q31_t)0x6487c4, (q31_t)0x7fffc38c, (q31_t)0x57f6d4, + (q31_t)0x7fffd396, (q31_t)0x4b65e1, (q31_t)0x7fffe128, (q31_t)0x3ed4ea, + (q31_t)0x7fffec43, (q31_t)0x3243f1, (q31_t)0x7ffff4e6, (q31_t)0x25b2f7, + (q31_t)0x7ffffb11, (q31_t)0x1921fb, (q31_t)0x7ffffec4, (q31_t)0xc90fe, + (q31_t)0x7fffffff, (q31_t)0x0, (q31_t)0x7ffffec4, (q31_t)0xfff36f02, + (q31_t)0x7ffffb11, (q31_t)0xffe6de05, (q31_t)0x7ffff4e6, (q31_t)0xffda4d09, + (q31_t)0x7fffec43, (q31_t)0xffcdbc0f, (q31_t)0x7fffe128, (q31_t)0xffc12b16, + (q31_t)0x7fffd396, (q31_t)0xffb49a1f, (q31_t)0x7fffc38c, (q31_t)0xffa8092c, + (q31_t)0x7fffb10b, (q31_t)0xff9b783c, (q31_t)0x7fff9c12, (q31_t)0xff8ee750, + (q31_t)0x7fff84a1, (q31_t)0xff825668, (q31_t)0x7fff6ab9, (q31_t)0xff75c585, + (q31_t)0x7fff4e59, (q31_t)0xff6934a8, (q31_t)0x7fff2f82, (q31_t)0xff5ca3d0, + (q31_t)0x7fff0e32, (q31_t)0xff5012fe, (q31_t)0x7ffeea6c, (q31_t)0xff438234, + (q31_t)0x7ffec42d, (q31_t)0xff36f170, (q31_t)0x7ffe9b77, (q31_t)0xff2a60b4, + (q31_t)0x7ffe704a, (q31_t)0xff1dd001, (q31_t)0x7ffe42a4, (q31_t)0xff113f56, + (q31_t)0x7ffe1288, (q31_t)0xff04aeb5, (q31_t)0x7ffddff3, (q31_t)0xfef81e1d, + (q31_t)0x7ffdaae7, (q31_t)0xfeeb8d8f, (q31_t)0x7ffd7364, (q31_t)0xfedefd0c, + (q31_t)0x7ffd3969, (q31_t)0xfed26c94, (q31_t)0x7ffcfcf6, (q31_t)0xfec5dc28, + (q31_t)0x7ffcbe0c, (q31_t)0xfeb94bc8, (q31_t)0x7ffc7caa, (q31_t)0xfeacbb74, + (q31_t)0x7ffc38d1, (q31_t)0xfea02b2e, (q31_t)0x7ffbf280, (q31_t)0xfe939af5, + (q31_t)0x7ffba9b8, (q31_t)0xfe870aca, (q31_t)0x7ffb5e78, (q31_t)0xfe7a7aae, + (q31_t)0x7ffb10c1, (q31_t)0xfe6deaa1, (q31_t)0x7ffac092, (q31_t)0xfe615aa3, + (q31_t)0x7ffa6dec, (q31_t)0xfe54cab5, (q31_t)0x7ffa18cf, (q31_t)0xfe483ad8, + (q31_t)0x7ff9c13a, (q31_t)0xfe3bab0b, (q31_t)0x7ff9672d, (q31_t)0xfe2f1b50, + (q31_t)0x7ff90aaa, (q31_t)0xfe228ba7, (q31_t)0x7ff8abae, (q31_t)0xfe15fc11, + (q31_t)0x7ff84a3c, (q31_t)0xfe096c8d, (q31_t)0x7ff7e652, (q31_t)0xfdfcdd1d, + (q31_t)0x7ff77ff1, (q31_t)0xfdf04dc0, (q31_t)0x7ff71718, (q31_t)0xfde3be78, + (q31_t)0x7ff6abc8, (q31_t)0xfdd72f45, (q31_t)0x7ff63e01, (q31_t)0xfdcaa027, + (q31_t)0x7ff5cdc3, (q31_t)0xfdbe111e, (q31_t)0x7ff55b0d, (q31_t)0xfdb1822c, + (q31_t)0x7ff4e5e0, (q31_t)0xfda4f351, (q31_t)0x7ff46e3c, (q31_t)0xfd98648d, + (q31_t)0x7ff3f420, (q31_t)0xfd8bd5e1, (q31_t)0x7ff3778e, (q31_t)0xfd7f474d, + (q31_t)0x7ff2f884, (q31_t)0xfd72b8d2, (q31_t)0x7ff27703, (q31_t)0xfd662a70, + (q31_t)0x7ff1f30b, (q31_t)0xfd599c28, (q31_t)0x7ff16c9c, (q31_t)0xfd4d0df9, + (q31_t)0x7ff0e3b6, (q31_t)0xfd407fe6, (q31_t)0x7ff05858, (q31_t)0xfd33f1ed, + (q31_t)0x7fefca84, (q31_t)0xfd276410, (q31_t)0x7fef3a39, (q31_t)0xfd1ad650, + (q31_t)0x7feea776, (q31_t)0xfd0e48ab, (q31_t)0x7fee123d, (q31_t)0xfd01bb24, + (q31_t)0x7fed7a8c, (q31_t)0xfcf52dbb, (q31_t)0x7fece065, (q31_t)0xfce8a06f, + (q31_t)0x7fec43c7, (q31_t)0xfcdc1342, (q31_t)0x7feba4b2, (q31_t)0xfccf8634, + (q31_t)0x7feb0326, (q31_t)0xfcc2f945, (q31_t)0x7fea5f23, (q31_t)0xfcb66c77, + (q31_t)0x7fe9b8a9, (q31_t)0xfca9dfc8, (q31_t)0x7fe90fb9, (q31_t)0xfc9d533b, + (q31_t)0x7fe86452, (q31_t)0xfc90c6cf, (q31_t)0x7fe7b674, (q31_t)0xfc843a85, + (q31_t)0x7fe7061f, (q31_t)0xfc77ae5e, (q31_t)0x7fe65354, (q31_t)0xfc6b2259, + (q31_t)0x7fe59e12, (q31_t)0xfc5e9678, (q31_t)0x7fe4e659, (q31_t)0xfc520aba, + (q31_t)0x7fe42c2a, (q31_t)0xfc457f21, (q31_t)0x7fe36f84, (q31_t)0xfc38f3ac, + (q31_t)0x7fe2b067, (q31_t)0xfc2c685d, (q31_t)0x7fe1eed5, (q31_t)0xfc1fdd34, + (q31_t)0x7fe12acb, (q31_t)0xfc135231, (q31_t)0x7fe0644b, (q31_t)0xfc06c754, + (q31_t)0x7fdf9b55, (q31_t)0xfbfa3c9f, (q31_t)0x7fdecfe8, (q31_t)0xfbedb212, + (q31_t)0x7fde0205, (q31_t)0xfbe127ac, (q31_t)0x7fdd31ac, (q31_t)0xfbd49d70, + (q31_t)0x7fdc5edc, (q31_t)0xfbc8135c, (q31_t)0x7fdb8996, (q31_t)0xfbbb8973, + (q31_t)0x7fdab1d9, (q31_t)0xfbaeffb3, (q31_t)0x7fd9d7a7, (q31_t)0xfba2761e, + (q31_t)0x7fd8fafe, (q31_t)0xfb95ecb4, (q31_t)0x7fd81bdf, (q31_t)0xfb896375, + (q31_t)0x7fd73a4a, (q31_t)0xfb7cda63, (q31_t)0x7fd6563f, (q31_t)0xfb70517d, + (q31_t)0x7fd56fbe, (q31_t)0xfb63c8c4, (q31_t)0x7fd486c7, (q31_t)0xfb574039, + (q31_t)0x7fd39b5a, (q31_t)0xfb4ab7db, (q31_t)0x7fd2ad77, (q31_t)0xfb3e2fac, + (q31_t)0x7fd1bd1e, (q31_t)0xfb31a7ac, (q31_t)0x7fd0ca4f, (q31_t)0xfb251fdc, + (q31_t)0x7fcfd50b, (q31_t)0xfb18983b, (q31_t)0x7fcedd50, (q31_t)0xfb0c10cb, + (q31_t)0x7fcde320, (q31_t)0xfaff898c, (q31_t)0x7fcce67a, (q31_t)0xfaf3027e, + (q31_t)0x7fcbe75e, (q31_t)0xfae67ba2, (q31_t)0x7fcae5cd, (q31_t)0xfad9f4f8, + (q31_t)0x7fc9e1c6, (q31_t)0xfacd6e81, (q31_t)0x7fc8db4a, (q31_t)0xfac0e83d, + (q31_t)0x7fc7d258, (q31_t)0xfab4622d, (q31_t)0x7fc6c6f0, (q31_t)0xfaa7dc52, + (q31_t)0x7fc5b913, (q31_t)0xfa9b56ab, (q31_t)0x7fc4a8c1, (q31_t)0xfa8ed139, + (q31_t)0x7fc395f9, (q31_t)0xfa824bfd, (q31_t)0x7fc280bc, (q31_t)0xfa75c6f8, + (q31_t)0x7fc1690a, (q31_t)0xfa694229, (q31_t)0x7fc04ee3, (q31_t)0xfa5cbd91, + (q31_t)0x7fbf3246, (q31_t)0xfa503930, (q31_t)0x7fbe1334, (q31_t)0xfa43b508, + (q31_t)0x7fbcf1ad, (q31_t)0xfa373119, (q31_t)0x7fbbcdb1, (q31_t)0xfa2aad62, + (q31_t)0x7fbaa740, (q31_t)0xfa1e29e5, (q31_t)0x7fb97e5a, (q31_t)0xfa11a6a3, + (q31_t)0x7fb852ff, (q31_t)0xfa05239a, (q31_t)0x7fb7252f, (q31_t)0xf9f8a0cd, + (q31_t)0x7fb5f4ea, (q31_t)0xf9ec1e3b, (q31_t)0x7fb4c231, (q31_t)0xf9df9be6, + (q31_t)0x7fb38d02, (q31_t)0xf9d319cc, (q31_t)0x7fb2555f, (q31_t)0xf9c697f0, + (q31_t)0x7fb11b48, (q31_t)0xf9ba1651, (q31_t)0x7fafdebb, (q31_t)0xf9ad94f0, + (q31_t)0x7fae9fbb, (q31_t)0xf9a113cd, (q31_t)0x7fad5e45, (q31_t)0xf99492ea, + (q31_t)0x7fac1a5b, (q31_t)0xf9881245, (q31_t)0x7faad3fd, (q31_t)0xf97b91e1, + (q31_t)0x7fa98b2a, (q31_t)0xf96f11bc, (q31_t)0x7fa83fe3, (q31_t)0xf96291d9, + (q31_t)0x7fa6f228, (q31_t)0xf9561237, (q31_t)0x7fa5a1f9, (q31_t)0xf94992d7, + (q31_t)0x7fa44f55, (q31_t)0xf93d13b8, (q31_t)0x7fa2fa3d, (q31_t)0xf93094dd, + (q31_t)0x7fa1a2b2, (q31_t)0xf9241645, (q31_t)0x7fa048b2, (q31_t)0xf91797f0, + (q31_t)0x7f9eec3e, (q31_t)0xf90b19e0, (q31_t)0x7f9d8d56, (q31_t)0xf8fe9c15, + (q31_t)0x7f9c2bfb, (q31_t)0xf8f21e8e, (q31_t)0x7f9ac82c, (q31_t)0xf8e5a14d, + (q31_t)0x7f9961e8, (q31_t)0xf8d92452, (q31_t)0x7f97f932, (q31_t)0xf8cca79e, + (q31_t)0x7f968e07, (q31_t)0xf8c02b31, (q31_t)0x7f952069, (q31_t)0xf8b3af0c, + (q31_t)0x7f93b058, (q31_t)0xf8a7332e, (q31_t)0x7f923dd2, (q31_t)0xf89ab799, + (q31_t)0x7f90c8da, (q31_t)0xf88e3c4d, (q31_t)0x7f8f516e, (q31_t)0xf881c14b, + (q31_t)0x7f8dd78f, (q31_t)0xf8754692, (q31_t)0x7f8c5b3d, (q31_t)0xf868cc24, + (q31_t)0x7f8adc77, (q31_t)0xf85c5201, (q31_t)0x7f895b3e, (q31_t)0xf84fd829, + (q31_t)0x7f87d792, (q31_t)0xf8435e9d, (q31_t)0x7f865174, (q31_t)0xf836e55d, + (q31_t)0x7f84c8e2, (q31_t)0xf82a6c6a, (q31_t)0x7f833ddd, (q31_t)0xf81df3c5, + (q31_t)0x7f81b065, (q31_t)0xf8117b6d, (q31_t)0x7f80207b, (q31_t)0xf8050364, + (q31_t)0x7f7e8e1e, (q31_t)0xf7f88ba9, (q31_t)0x7f7cf94e, (q31_t)0xf7ec143e, + (q31_t)0x7f7b620c, (q31_t)0xf7df9d22, (q31_t)0x7f79c857, (q31_t)0xf7d32657, + (q31_t)0x7f782c30, (q31_t)0xf7c6afdc, (q31_t)0x7f768d96, (q31_t)0xf7ba39b3, + (q31_t)0x7f74ec8a, (q31_t)0xf7adc3db, (q31_t)0x7f73490b, (q31_t)0xf7a14e55, + (q31_t)0x7f71a31b, (q31_t)0xf794d922, (q31_t)0x7f6ffab8, (q31_t)0xf7886442, + (q31_t)0x7f6e4fe3, (q31_t)0xf77befb5, (q31_t)0x7f6ca29c, (q31_t)0xf76f7b7d, + (q31_t)0x7f6af2e3, (q31_t)0xf7630799, (q31_t)0x7f6940b8, (q31_t)0xf756940a, + (q31_t)0x7f678c1c, (q31_t)0xf74a20d0, (q31_t)0x7f65d50d, (q31_t)0xf73daded, + (q31_t)0x7f641b8d, (q31_t)0xf7313b60, (q31_t)0x7f625f9b, (q31_t)0xf724c92a, + (q31_t)0x7f60a138, (q31_t)0xf718574b, (q31_t)0x7f5ee063, (q31_t)0xf70be5c4, + (q31_t)0x7f5d1d1d, (q31_t)0xf6ff7496, (q31_t)0x7f5b5765, (q31_t)0xf6f303c0, + (q31_t)0x7f598f3c, (q31_t)0xf6e69344, (q31_t)0x7f57c4a2, (q31_t)0xf6da2321, + (q31_t)0x7f55f796, (q31_t)0xf6cdb359, (q31_t)0x7f54281a, (q31_t)0xf6c143ec, + (q31_t)0x7f52562c, (q31_t)0xf6b4d4d9, (q31_t)0x7f5081cd, (q31_t)0xf6a86623, + (q31_t)0x7f4eaafe, (q31_t)0xf69bf7c9, (q31_t)0x7f4cd1be, (q31_t)0xf68f89cb, + (q31_t)0x7f4af60d, (q31_t)0xf6831c2b, (q31_t)0x7f4917eb, (q31_t)0xf676aee8, + (q31_t)0x7f473759, (q31_t)0xf66a4203, (q31_t)0x7f455456, (q31_t)0xf65dd57d, + (q31_t)0x7f436ee3, (q31_t)0xf6516956, (q31_t)0x7f4186ff, (q31_t)0xf644fd8f, + (q31_t)0x7f3f9cab, (q31_t)0xf6389228, (q31_t)0x7f3dafe7, (q31_t)0xf62c2721, + (q31_t)0x7f3bc0b3, (q31_t)0xf61fbc7b, (q31_t)0x7f39cf0e, (q31_t)0xf6135237, + (q31_t)0x7f37dafa, (q31_t)0xf606e854, (q31_t)0x7f35e476, (q31_t)0xf5fa7ed4, + (q31_t)0x7f33eb81, (q31_t)0xf5ee15b7, (q31_t)0x7f31f01d, (q31_t)0xf5e1acfd, + (q31_t)0x7f2ff24a, (q31_t)0xf5d544a7, (q31_t)0x7f2df206, (q31_t)0xf5c8dcb6, + (q31_t)0x7f2bef53, (q31_t)0xf5bc7529, (q31_t)0x7f29ea31, (q31_t)0xf5b00e02, + (q31_t)0x7f27e29f, (q31_t)0xf5a3a740, (q31_t)0x7f25d89e, (q31_t)0xf59740e5, + (q31_t)0x7f23cc2e, (q31_t)0xf58adaf0, (q31_t)0x7f21bd4e, (q31_t)0xf57e7563, + (q31_t)0x7f1fabff, (q31_t)0xf572103d, (q31_t)0x7f1d9842, (q31_t)0xf565ab80, + (q31_t)0x7f1b8215, (q31_t)0xf559472b, (q31_t)0x7f19697a, (q31_t)0xf54ce33f, + (q31_t)0x7f174e70, (q31_t)0xf5407fbd, (q31_t)0x7f1530f7, (q31_t)0xf5341ca5, + (q31_t)0x7f13110f, (q31_t)0xf527b9f7, (q31_t)0x7f10eeb9, (q31_t)0xf51b57b5, + (q31_t)0x7f0ec9f5, (q31_t)0xf50ef5de, (q31_t)0x7f0ca2c2, (q31_t)0xf5029473, + (q31_t)0x7f0a7921, (q31_t)0xf4f63374, (q31_t)0x7f084d12, (q31_t)0xf4e9d2e3, + (q31_t)0x7f061e95, (q31_t)0xf4dd72be, (q31_t)0x7f03eda9, (q31_t)0xf4d11308, + (q31_t)0x7f01ba50, (q31_t)0xf4c4b3c0, (q31_t)0x7eff8489, (q31_t)0xf4b854e7, + (q31_t)0x7efd4c54, (q31_t)0xf4abf67e, (q31_t)0x7efb11b1, (q31_t)0xf49f9884, + (q31_t)0x7ef8d4a1, (q31_t)0xf4933afa, (q31_t)0x7ef69523, (q31_t)0xf486dde1, + (q31_t)0x7ef45338, (q31_t)0xf47a8139, (q31_t)0x7ef20ee0, (q31_t)0xf46e2504, + (q31_t)0x7eefc81a, (q31_t)0xf461c940, (q31_t)0x7eed7ee7, (q31_t)0xf4556def, + (q31_t)0x7eeb3347, (q31_t)0xf4491311, (q31_t)0x7ee8e53a, (q31_t)0xf43cb8a7, + (q31_t)0x7ee694c1, (q31_t)0xf4305eb0, (q31_t)0x7ee441da, (q31_t)0xf424052f, + (q31_t)0x7ee1ec87, (q31_t)0xf417ac22, (q31_t)0x7edf94c7, (q31_t)0xf40b538b, + (q31_t)0x7edd3a9a, (q31_t)0xf3fefb6a, (q31_t)0x7edade01, (q31_t)0xf3f2a3bf, + (q31_t)0x7ed87efc, (q31_t)0xf3e64c8c, (q31_t)0x7ed61d8a, (q31_t)0xf3d9f5cf, + (q31_t)0x7ed3b9ad, (q31_t)0xf3cd9f8b, (q31_t)0x7ed15363, (q31_t)0xf3c149bf, + (q31_t)0x7eceeaad, (q31_t)0xf3b4f46c, (q31_t)0x7ecc7f8b, (q31_t)0xf3a89f92, + (q31_t)0x7eca11fe, (q31_t)0xf39c4b32, (q31_t)0x7ec7a205, (q31_t)0xf38ff74d, + (q31_t)0x7ec52fa0, (q31_t)0xf383a3e2, (q31_t)0x7ec2bad0, (q31_t)0xf37750f2, + (q31_t)0x7ec04394, (q31_t)0xf36afe7e, (q31_t)0x7ebdc9ed, (q31_t)0xf35eac86, + (q31_t)0x7ebb4ddb, (q31_t)0xf3525b0b, (q31_t)0x7eb8cf5d, (q31_t)0xf3460a0d, + (q31_t)0x7eb64e75, (q31_t)0xf339b98d, (q31_t)0x7eb3cb21, (q31_t)0xf32d698a, + (q31_t)0x7eb14563, (q31_t)0xf3211a07, (q31_t)0x7eaebd3a, (q31_t)0xf314cb02, + (q31_t)0x7eac32a6, (q31_t)0xf3087c7d, (q31_t)0x7ea9a5a8, (q31_t)0xf2fc2e77, + (q31_t)0x7ea7163f, (q31_t)0xf2efe0f2, (q31_t)0x7ea4846c, (q31_t)0xf2e393ef, + (q31_t)0x7ea1f02f, (q31_t)0xf2d7476c, (q31_t)0x7e9f5988, (q31_t)0xf2cafb6b, + (q31_t)0x7e9cc076, (q31_t)0xf2beafed, (q31_t)0x7e9a24fb, (q31_t)0xf2b264f2, + (q31_t)0x7e978715, (q31_t)0xf2a61a7a, (q31_t)0x7e94e6c6, (q31_t)0xf299d085, + (q31_t)0x7e92440d, (q31_t)0xf28d8715, (q31_t)0x7e8f9eeb, (q31_t)0xf2813e2a, + (q31_t)0x7e8cf75f, (q31_t)0xf274f5c3, (q31_t)0x7e8a4d6a, (q31_t)0xf268ade3, + (q31_t)0x7e87a10c, (q31_t)0xf25c6688, (q31_t)0x7e84f245, (q31_t)0xf2501fb5, + (q31_t)0x7e824114, (q31_t)0xf243d968, (q31_t)0x7e7f8d7b, (q31_t)0xf23793a3, + (q31_t)0x7e7cd778, (q31_t)0xf22b4e66, (q31_t)0x7e7a1f0d, (q31_t)0xf21f09b1, + (q31_t)0x7e77643a, (q31_t)0xf212c585, (q31_t)0x7e74a6fd, (q31_t)0xf20681e3, + (q31_t)0x7e71e759, (q31_t)0xf1fa3ecb, (q31_t)0x7e6f254c, (q31_t)0xf1edfc3d, + (q31_t)0x7e6c60d7, (q31_t)0xf1e1ba3a, (q31_t)0x7e6999fa, (q31_t)0xf1d578c2, + (q31_t)0x7e66d0b4, (q31_t)0xf1c937d6, (q31_t)0x7e640507, (q31_t)0xf1bcf777, + (q31_t)0x7e6136f3, (q31_t)0xf1b0b7a4, (q31_t)0x7e5e6676, (q31_t)0xf1a4785e, + (q31_t)0x7e5b9392, (q31_t)0xf19839a6, (q31_t)0x7e58be47, (q31_t)0xf18bfb7d, + (q31_t)0x7e55e694, (q31_t)0xf17fbde2, (q31_t)0x7e530c7a, (q31_t)0xf17380d6, + (q31_t)0x7e502ff9, (q31_t)0xf1674459, (q31_t)0x7e4d5110, (q31_t)0xf15b086d, + (q31_t)0x7e4a6fc1, (q31_t)0xf14ecd11, (q31_t)0x7e478c0b, (q31_t)0xf1429247, + (q31_t)0x7e44a5ef, (q31_t)0xf136580d, (q31_t)0x7e41bd6c, (q31_t)0xf12a1e66, + (q31_t)0x7e3ed282, (q31_t)0xf11de551, (q31_t)0x7e3be532, (q31_t)0xf111accf, + (q31_t)0x7e38f57c, (q31_t)0xf10574e0, (q31_t)0x7e360360, (q31_t)0xf0f93d86, + (q31_t)0x7e330ede, (q31_t)0xf0ed06bf, (q31_t)0x7e3017f6, (q31_t)0xf0e0d08d, + (q31_t)0x7e2d1ea8, (q31_t)0xf0d49af1, (q31_t)0x7e2a22f4, (q31_t)0xf0c865ea, + (q31_t)0x7e2724db, (q31_t)0xf0bc317a, (q31_t)0x7e24245d, (q31_t)0xf0affda0, + (q31_t)0x7e212179, (q31_t)0xf0a3ca5d, (q31_t)0x7e1e1c30, (q31_t)0xf09797b2, + (q31_t)0x7e1b1482, (q31_t)0xf08b659f, (q31_t)0x7e180a6f, (q31_t)0xf07f3424, + (q31_t)0x7e14fdf7, (q31_t)0xf0730342, (q31_t)0x7e11ef1b, (q31_t)0xf066d2fa, + (q31_t)0x7e0eddd9, (q31_t)0xf05aa34c, (q31_t)0x7e0bca34, (q31_t)0xf04e7438, + (q31_t)0x7e08b42a, (q31_t)0xf04245c0, (q31_t)0x7e059bbb, (q31_t)0xf03617e2, + (q31_t)0x7e0280e9, (q31_t)0xf029eaa1, (q31_t)0x7dff63b2, (q31_t)0xf01dbdfb, + (q31_t)0x7dfc4418, (q31_t)0xf01191f3, (q31_t)0x7df9221a, (q31_t)0xf0056687, + (q31_t)0x7df5fdb8, (q31_t)0xeff93bba, (q31_t)0x7df2d6f3, (q31_t)0xefed118a, + (q31_t)0x7defadca, (q31_t)0xefe0e7f9, (q31_t)0x7dec823e, (q31_t)0xefd4bf08, + (q31_t)0x7de9544f, (q31_t)0xefc896b5, (q31_t)0x7de623fd, (q31_t)0xefbc6f03, + (q31_t)0x7de2f148, (q31_t)0xefb047f2, (q31_t)0x7ddfbc30, (q31_t)0xefa42181, + (q31_t)0x7ddc84b5, (q31_t)0xef97fbb2, (q31_t)0x7dd94ad8, (q31_t)0xef8bd685, + (q31_t)0x7dd60e99, (q31_t)0xef7fb1fa, (q31_t)0x7dd2cff7, (q31_t)0xef738e12, + (q31_t)0x7dcf8ef3, (q31_t)0xef676ace, (q31_t)0x7dcc4b8d, (q31_t)0xef5b482d, + (q31_t)0x7dc905c5, (q31_t)0xef4f2630, (q31_t)0x7dc5bd9b, (q31_t)0xef4304d8, + (q31_t)0x7dc2730f, (q31_t)0xef36e426, (q31_t)0x7dbf2622, (q31_t)0xef2ac419, + (q31_t)0x7dbbd6d4, (q31_t)0xef1ea4b2, (q31_t)0x7db88524, (q31_t)0xef1285f2, + (q31_t)0x7db53113, (q31_t)0xef0667d9, (q31_t)0x7db1daa2, (q31_t)0xeefa4a67, + (q31_t)0x7dae81cf, (q31_t)0xeeee2d9d, (q31_t)0x7dab269b, (q31_t)0xeee2117c, + (q31_t)0x7da7c907, (q31_t)0xeed5f604, (q31_t)0x7da46912, (q31_t)0xeec9db35, + (q31_t)0x7da106bd, (q31_t)0xeebdc110, (q31_t)0x7d9da208, (q31_t)0xeeb1a796, + (q31_t)0x7d9a3af2, (q31_t)0xeea58ec6, (q31_t)0x7d96d17d, (q31_t)0xee9976a1, + (q31_t)0x7d9365a8, (q31_t)0xee8d5f29, (q31_t)0x7d8ff772, (q31_t)0xee81485c, + (q31_t)0x7d8c86de, (q31_t)0xee75323c, (q31_t)0x7d8913ea, (q31_t)0xee691cc9, + (q31_t)0x7d859e96, (q31_t)0xee5d0804, (q31_t)0x7d8226e4, (q31_t)0xee50f3ed, + (q31_t)0x7d7eacd2, (q31_t)0xee44e084, (q31_t)0x7d7b3061, (q31_t)0xee38cdcb, + (q31_t)0x7d77b192, (q31_t)0xee2cbbc1, (q31_t)0x7d743064, (q31_t)0xee20aa67, + (q31_t)0x7d70acd7, (q31_t)0xee1499bd, (q31_t)0x7d6d26ec, (q31_t)0xee0889c4, + (q31_t)0x7d699ea3, (q31_t)0xedfc7a7c, (q31_t)0x7d6613fb, (q31_t)0xedf06be6, + (q31_t)0x7d6286f6, (q31_t)0xede45e03, (q31_t)0x7d5ef793, (q31_t)0xedd850d2, + (q31_t)0x7d5b65d2, (q31_t)0xedcc4454, (q31_t)0x7d57d1b3, (q31_t)0xedc0388a, + (q31_t)0x7d543b37, (q31_t)0xedb42d74, (q31_t)0x7d50a25e, (q31_t)0xeda82313, + (q31_t)0x7d4d0728, (q31_t)0xed9c1967, (q31_t)0x7d496994, (q31_t)0xed901070, + (q31_t)0x7d45c9a4, (q31_t)0xed84082f, (q31_t)0x7d422757, (q31_t)0xed7800a5, + (q31_t)0x7d3e82ae, (q31_t)0xed6bf9d1, (q31_t)0x7d3adba7, (q31_t)0xed5ff3b5, + (q31_t)0x7d373245, (q31_t)0xed53ee51, (q31_t)0x7d338687, (q31_t)0xed47e9a5, + (q31_t)0x7d2fd86c, (q31_t)0xed3be5b1, (q31_t)0x7d2c27f6, (q31_t)0xed2fe277, + (q31_t)0x7d287523, (q31_t)0xed23dff7, (q31_t)0x7d24bff6, (q31_t)0xed17de31, + (q31_t)0x7d21086c, (q31_t)0xed0bdd25, (q31_t)0x7d1d4e88, (q31_t)0xecffdcd4, + (q31_t)0x7d199248, (q31_t)0xecf3dd3f, (q31_t)0x7d15d3ad, (q31_t)0xece7de66, + (q31_t)0x7d1212b7, (q31_t)0xecdbe04a, (q31_t)0x7d0e4f67, (q31_t)0xeccfe2ea, + (q31_t)0x7d0a89bc, (q31_t)0xecc3e648, (q31_t)0x7d06c1b6, (q31_t)0xecb7ea63, + (q31_t)0x7d02f757, (q31_t)0xecabef3d, (q31_t)0x7cff2a9d, (q31_t)0xec9ff4d6, + (q31_t)0x7cfb5b89, (q31_t)0xec93fb2e, (q31_t)0x7cf78a1b, (q31_t)0xec880245, + (q31_t)0x7cf3b653, (q31_t)0xec7c0a1d, (q31_t)0x7cefe032, (q31_t)0xec7012b5, + (q31_t)0x7cec07b8, (q31_t)0xec641c0e, (q31_t)0x7ce82ce4, (q31_t)0xec582629, + (q31_t)0x7ce44fb7, (q31_t)0xec4c3106, (q31_t)0x7ce07031, (q31_t)0xec403ca5, + (q31_t)0x7cdc8e52, (q31_t)0xec344908, (q31_t)0x7cd8aa1b, (q31_t)0xec28562d, + (q31_t)0x7cd4c38b, (q31_t)0xec1c6417, (q31_t)0x7cd0daa2, (q31_t)0xec1072c4, + (q31_t)0x7cccef62, (q31_t)0xec048237, (q31_t)0x7cc901c9, (q31_t)0xebf8926f, + (q31_t)0x7cc511d9, (q31_t)0xebeca36c, (q31_t)0x7cc11f90, (q31_t)0xebe0b52f, + (q31_t)0x7cbd2af0, (q31_t)0xebd4c7ba, (q31_t)0x7cb933f9, (q31_t)0xebc8db0b, + (q31_t)0x7cb53aaa, (q31_t)0xebbcef23, (q31_t)0x7cb13f04, (q31_t)0xebb10404, + (q31_t)0x7cad4107, (q31_t)0xeba519ad, (q31_t)0x7ca940b3, (q31_t)0xeb99301f, + (q31_t)0x7ca53e09, (q31_t)0xeb8d475b, (q31_t)0x7ca13908, (q31_t)0xeb815f60, + (q31_t)0x7c9d31b0, (q31_t)0xeb75782f, (q31_t)0x7c992803, (q31_t)0xeb6991ca, + (q31_t)0x7c951bff, (q31_t)0xeb5dac2f, (q31_t)0x7c910da5, (q31_t)0xeb51c760, + (q31_t)0x7c8cfcf6, (q31_t)0xeb45e35d, (q31_t)0x7c88e9f1, (q31_t)0xeb3a0027, + (q31_t)0x7c84d496, (q31_t)0xeb2e1dbe, (q31_t)0x7c80bce7, (q31_t)0xeb223c22, + (q31_t)0x7c7ca2e2, (q31_t)0xeb165b54, (q31_t)0x7c788688, (q31_t)0xeb0a7b54, + (q31_t)0x7c7467d9, (q31_t)0xeafe9c24, (q31_t)0x7c7046d6, (q31_t)0xeaf2bdc3, + (q31_t)0x7c6c237e, (q31_t)0xeae6e031, (q31_t)0x7c67fdd1, (q31_t)0xeadb0370, + (q31_t)0x7c63d5d1, (q31_t)0xeacf277f, (q31_t)0x7c5fab7c, (q31_t)0xeac34c60, + (q31_t)0x7c5b7ed4, (q31_t)0xeab77212, (q31_t)0x7c574fd8, (q31_t)0xeaab9896, + (q31_t)0x7c531e88, (q31_t)0xea9fbfed, (q31_t)0x7c4eeae5, (q31_t)0xea93e817, + (q31_t)0x7c4ab4ef, (q31_t)0xea881114, (q31_t)0x7c467ca6, (q31_t)0xea7c3ae5, + (q31_t)0x7c42420a, (q31_t)0xea70658a, (q31_t)0x7c3e051b, (q31_t)0xea649105, + (q31_t)0x7c39c5da, (q31_t)0xea58bd54, (q31_t)0x7c358446, (q31_t)0xea4cea79, + (q31_t)0x7c314060, (q31_t)0xea411874, (q31_t)0x7c2cfa28, (q31_t)0xea354746, + (q31_t)0x7c28b19e, (q31_t)0xea2976ef, (q31_t)0x7c2466c2, (q31_t)0xea1da770, + (q31_t)0x7c201994, (q31_t)0xea11d8c8, (q31_t)0x7c1bca16, (q31_t)0xea060af9, + (q31_t)0x7c177845, (q31_t)0xe9fa3e03, (q31_t)0x7c132424, (q31_t)0xe9ee71e6, + (q31_t)0x7c0ecdb2, (q31_t)0xe9e2a6a3, (q31_t)0x7c0a74f0, (q31_t)0xe9d6dc3b, + (q31_t)0x7c0619dc, (q31_t)0xe9cb12ad, (q31_t)0x7c01bc78, (q31_t)0xe9bf49fa, + (q31_t)0x7bfd5cc4, (q31_t)0xe9b38223, (q31_t)0x7bf8fac0, (q31_t)0xe9a7bb28, + (q31_t)0x7bf4966c, (q31_t)0xe99bf509, (q31_t)0x7bf02fc9, (q31_t)0xe9902fc7, + (q31_t)0x7bebc6d5, (q31_t)0xe9846b63, (q31_t)0x7be75b93, (q31_t)0xe978a7dd, + (q31_t)0x7be2ee01, (q31_t)0xe96ce535, (q31_t)0x7bde7e20, (q31_t)0xe961236c, + (q31_t)0x7bda0bf0, (q31_t)0xe9556282, (q31_t)0x7bd59771, (q31_t)0xe949a278, + (q31_t)0x7bd120a4, (q31_t)0xe93de34e, (q31_t)0x7bcca789, (q31_t)0xe9322505, + (q31_t)0x7bc82c1f, (q31_t)0xe926679c, (q31_t)0x7bc3ae67, (q31_t)0xe91aab16, + (q31_t)0x7bbf2e62, (q31_t)0xe90eef71, (q31_t)0x7bbaac0e, (q31_t)0xe90334af, + (q31_t)0x7bb6276e, (q31_t)0xe8f77acf, (q31_t)0x7bb1a080, (q31_t)0xe8ebc1d3, + (q31_t)0x7bad1744, (q31_t)0xe8e009ba, (q31_t)0x7ba88bbc, (q31_t)0xe8d45286, + (q31_t)0x7ba3fde7, (q31_t)0xe8c89c37, (q31_t)0x7b9f6dc5, (q31_t)0xe8bce6cd, + (q31_t)0x7b9adb57, (q31_t)0xe8b13248, (q31_t)0x7b96469d, (q31_t)0xe8a57ea9, + (q31_t)0x7b91af97, (q31_t)0xe899cbf1, (q31_t)0x7b8d1644, (q31_t)0xe88e1a20, + (q31_t)0x7b887aa6, (q31_t)0xe8826936, (q31_t)0x7b83dcbc, (q31_t)0xe876b934, + (q31_t)0x7b7f3c87, (q31_t)0xe86b0a1a, (q31_t)0x7b7a9a07, (q31_t)0xe85f5be9, + (q31_t)0x7b75f53c, (q31_t)0xe853aea1, (q31_t)0x7b714e25, (q31_t)0xe8480243, + (q31_t)0x7b6ca4c4, (q31_t)0xe83c56cf, (q31_t)0x7b67f919, (q31_t)0xe830ac45, + (q31_t)0x7b634b23, (q31_t)0xe82502a7, (q31_t)0x7b5e9ae4, (q31_t)0xe81959f4, + (q31_t)0x7b59e85a, (q31_t)0xe80db22d, (q31_t)0x7b553386, (q31_t)0xe8020b52, + (q31_t)0x7b507c69, (q31_t)0xe7f66564, (q31_t)0x7b4bc303, (q31_t)0xe7eac063, + (q31_t)0x7b470753, (q31_t)0xe7df1c50, (q31_t)0x7b42495a, (q31_t)0xe7d3792b, + (q31_t)0x7b3d8918, (q31_t)0xe7c7d6f4, (q31_t)0x7b38c68e, (q31_t)0xe7bc35ad, + (q31_t)0x7b3401bb, (q31_t)0xe7b09555, (q31_t)0x7b2f3aa0, (q31_t)0xe7a4f5ed, + (q31_t)0x7b2a713d, (q31_t)0xe7995776, (q31_t)0x7b25a591, (q31_t)0xe78db9ef, + (q31_t)0x7b20d79e, (q31_t)0xe7821d59, (q31_t)0x7b1c0764, (q31_t)0xe77681b6, + (q31_t)0x7b1734e2, (q31_t)0xe76ae704, (q31_t)0x7b126019, (q31_t)0xe75f4d45, + (q31_t)0x7b0d8909, (q31_t)0xe753b479, (q31_t)0x7b08afb2, (q31_t)0xe7481ca1, + (q31_t)0x7b03d414, (q31_t)0xe73c85bc, (q31_t)0x7afef630, (q31_t)0xe730efcc, + (q31_t)0x7afa1605, (q31_t)0xe7255ad1, (q31_t)0x7af53395, (q31_t)0xe719c6cb, + (q31_t)0x7af04edf, (q31_t)0xe70e33bb, (q31_t)0x7aeb67e3, (q31_t)0xe702a1a1, + (q31_t)0x7ae67ea1, (q31_t)0xe6f7107e, (q31_t)0x7ae1931a, (q31_t)0xe6eb8052, + (q31_t)0x7adca54e, (q31_t)0xe6dff11d, (q31_t)0x7ad7b53d, (q31_t)0xe6d462e1, + (q31_t)0x7ad2c2e8, (q31_t)0xe6c8d59c, (q31_t)0x7acdce4d, (q31_t)0xe6bd4951, + (q31_t)0x7ac8d76f, (q31_t)0xe6b1bdff, (q31_t)0x7ac3de4c, (q31_t)0xe6a633a6, + (q31_t)0x7abee2e5, (q31_t)0xe69aaa48, (q31_t)0x7ab9e53a, (q31_t)0xe68f21e5, + (q31_t)0x7ab4e54c, (q31_t)0xe6839a7c, (q31_t)0x7aafe31b, (q31_t)0xe6781410, + (q31_t)0x7aaadea6, (q31_t)0xe66c8e9f, (q31_t)0x7aa5d7ee, (q31_t)0xe6610a2a, + (q31_t)0x7aa0cef3, (q31_t)0xe65586b3, (q31_t)0x7a9bc3b6, (q31_t)0xe64a0438, + (q31_t)0x7a96b636, (q31_t)0xe63e82bc, (q31_t)0x7a91a674, (q31_t)0xe633023e, + (q31_t)0x7a8c9470, (q31_t)0xe62782be, (q31_t)0x7a87802a, (q31_t)0xe61c043d, + (q31_t)0x7a8269a3, (q31_t)0xe61086bc, (q31_t)0x7a7d50da, (q31_t)0xe6050a3b, + (q31_t)0x7a7835cf, (q31_t)0xe5f98ebb, (q31_t)0x7a731884, (q31_t)0xe5ee143b, + (q31_t)0x7a6df8f8, (q31_t)0xe5e29abc, (q31_t)0x7a68d72b, (q31_t)0xe5d72240, + (q31_t)0x7a63b31d, (q31_t)0xe5cbaac5, (q31_t)0x7a5e8cd0, (q31_t)0xe5c0344d, + (q31_t)0x7a596442, (q31_t)0xe5b4bed8, (q31_t)0x7a543974, (q31_t)0xe5a94a67, + (q31_t)0x7a4f0c67, (q31_t)0xe59dd6f9, (q31_t)0x7a49dd1a, (q31_t)0xe5926490, + (q31_t)0x7a44ab8e, (q31_t)0xe586f32c, (q31_t)0x7a3f77c3, (q31_t)0xe57b82cd, + (q31_t)0x7a3a41b9, (q31_t)0xe5701374, (q31_t)0x7a350970, (q31_t)0xe564a521, + (q31_t)0x7a2fcee8, (q31_t)0xe55937d5, (q31_t)0x7a2a9223, (q31_t)0xe54dcb8f, + (q31_t)0x7a25531f, (q31_t)0xe5426051, (q31_t)0x7a2011de, (q31_t)0xe536f61b, + (q31_t)0x7a1ace5f, (q31_t)0xe52b8cee, (q31_t)0x7a1588a2, (q31_t)0xe52024c9, + (q31_t)0x7a1040a8, (q31_t)0xe514bdad, (q31_t)0x7a0af671, (q31_t)0xe509579b, + (q31_t)0x7a05a9fd, (q31_t)0xe4fdf294, (q31_t)0x7a005b4d, (q31_t)0xe4f28e96, + (q31_t)0x79fb0a60, (q31_t)0xe4e72ba4, (q31_t)0x79f5b737, (q31_t)0xe4dbc9bd, + (q31_t)0x79f061d2, (q31_t)0xe4d068e2, (q31_t)0x79eb0a31, (q31_t)0xe4c50914, + (q31_t)0x79e5b054, (q31_t)0xe4b9aa52, (q31_t)0x79e0543c, (q31_t)0xe4ae4c9d, + (q31_t)0x79daf5e8, (q31_t)0xe4a2eff6, (q31_t)0x79d5955a, (q31_t)0xe497945d, + (q31_t)0x79d03291, (q31_t)0xe48c39d3, (q31_t)0x79cacd8d, (q31_t)0xe480e057, + (q31_t)0x79c5664f, (q31_t)0xe47587eb, (q31_t)0x79bffcd7, (q31_t)0xe46a308f, + (q31_t)0x79ba9125, (q31_t)0xe45eda43, (q31_t)0x79b52339, (q31_t)0xe4538507, + (q31_t)0x79afb313, (q31_t)0xe44830dd, (q31_t)0x79aa40b4, (q31_t)0xe43cddc4, + (q31_t)0x79a4cc1c, (q31_t)0xe4318bbe, (q31_t)0x799f554b, (q31_t)0xe4263ac9, + (q31_t)0x7999dc42, (q31_t)0xe41aeae8, (q31_t)0x799460ff, (q31_t)0xe40f9c1a, + (q31_t)0x798ee385, (q31_t)0xe4044e60, (q31_t)0x798963d2, (q31_t)0xe3f901ba, + (q31_t)0x7983e1e8, (q31_t)0xe3edb628, (q31_t)0x797e5dc6, (q31_t)0xe3e26bac, + (q31_t)0x7978d76c, (q31_t)0xe3d72245, (q31_t)0x79734edc, (q31_t)0xe3cbd9f4, + (q31_t)0x796dc414, (q31_t)0xe3c092b9, (q31_t)0x79683715, (q31_t)0xe3b54c95, + (q31_t)0x7962a7e0, (q31_t)0xe3aa0788, (q31_t)0x795d1675, (q31_t)0xe39ec393, + (q31_t)0x795782d3, (q31_t)0xe39380b6, (q31_t)0x7951ecfc, (q31_t)0xe3883ef2, + (q31_t)0x794c54ee, (q31_t)0xe37cfe47, (q31_t)0x7946baac, (q31_t)0xe371beb5, + (q31_t)0x79411e33, (q31_t)0xe366803c, (q31_t)0x793b7f86, (q31_t)0xe35b42df, + (q31_t)0x7935dea4, (q31_t)0xe350069b, (q31_t)0x79303b8e, (q31_t)0xe344cb73, + (q31_t)0x792a9642, (q31_t)0xe3399167, (q31_t)0x7924eec3, (q31_t)0xe32e5876, + (q31_t)0x791f4510, (q31_t)0xe32320a2, (q31_t)0x79199929, (q31_t)0xe317e9eb, + (q31_t)0x7913eb0e, (q31_t)0xe30cb451, (q31_t)0x790e3ac0, (q31_t)0xe3017fd5, + (q31_t)0x7908883f, (q31_t)0xe2f64c77, (q31_t)0x7902d38b, (q31_t)0xe2eb1a37, + (q31_t)0x78fd1ca4, (q31_t)0xe2dfe917, (q31_t)0x78f7638b, (q31_t)0xe2d4b916, + (q31_t)0x78f1a840, (q31_t)0xe2c98a35, (q31_t)0x78ebeac2, (q31_t)0xe2be5c74, + (q31_t)0x78e62b13, (q31_t)0xe2b32fd4, (q31_t)0x78e06932, (q31_t)0xe2a80456, + (q31_t)0x78daa520, (q31_t)0xe29cd9f8, (q31_t)0x78d4dedd, (q31_t)0xe291b0bd, + (q31_t)0x78cf1669, (q31_t)0xe28688a4, (q31_t)0x78c94bc4, (q31_t)0xe27b61af, + (q31_t)0x78c37eef, (q31_t)0xe2703bdc, (q31_t)0x78bdafea, (q31_t)0xe265172e, + (q31_t)0x78b7deb4, (q31_t)0xe259f3a3, (q31_t)0x78b20b4f, (q31_t)0xe24ed13d, + (q31_t)0x78ac35ba, (q31_t)0xe243affc, (q31_t)0x78a65df6, (q31_t)0xe2388fe1, + (q31_t)0x78a08402, (q31_t)0xe22d70eb, (q31_t)0x789aa7e0, (q31_t)0xe222531c, + (q31_t)0x7894c98f, (q31_t)0xe2173674, (q31_t)0x788ee910, (q31_t)0xe20c1af3, + (q31_t)0x78890663, (q31_t)0xe2010099, (q31_t)0x78832187, (q31_t)0xe1f5e768, + (q31_t)0x787d3a7e, (q31_t)0xe1eacf5f, (q31_t)0x78775147, (q31_t)0xe1dfb87f, + (q31_t)0x787165e3, (q31_t)0xe1d4a2c8, (q31_t)0x786b7852, (q31_t)0xe1c98e3b, + (q31_t)0x78658894, (q31_t)0xe1be7ad8, (q31_t)0x785f96a9, (q31_t)0xe1b368a0, + (q31_t)0x7859a292, (q31_t)0xe1a85793, (q31_t)0x7853ac4f, (q31_t)0xe19d47b1, + (q31_t)0x784db3e0, (q31_t)0xe19238fb, (q31_t)0x7847b946, (q31_t)0xe1872b72, + (q31_t)0x7841bc7f, (q31_t)0xe17c1f15, (q31_t)0x783bbd8e, (q31_t)0xe17113e5, + (q31_t)0x7835bc71, (q31_t)0xe16609e3, (q31_t)0x782fb92a, (q31_t)0xe15b0110, + (q31_t)0x7829b3b9, (q31_t)0xe14ff96a, (q31_t)0x7823ac1d, (q31_t)0xe144f2f3, + (q31_t)0x781da256, (q31_t)0xe139edac, (q31_t)0x78179666, (q31_t)0xe12ee995, + (q31_t)0x7811884d, (q31_t)0xe123e6ad, (q31_t)0x780b780a, (q31_t)0xe118e4f6, + (q31_t)0x7805659e, (q31_t)0xe10de470, (q31_t)0x77ff5109, (q31_t)0xe102e51c, + (q31_t)0x77f93a4b, (q31_t)0xe0f7e6f9, (q31_t)0x77f32165, (q31_t)0xe0ecea09, + (q31_t)0x77ed0657, (q31_t)0xe0e1ee4b, (q31_t)0x77e6e921, (q31_t)0xe0d6f3c1, + (q31_t)0x77e0c9c3, (q31_t)0xe0cbfa6a, (q31_t)0x77daa83d, (q31_t)0xe0c10247, + (q31_t)0x77d48490, (q31_t)0xe0b60b58, (q31_t)0x77ce5ebd, (q31_t)0xe0ab159e, + (q31_t)0x77c836c2, (q31_t)0xe0a0211a, (q31_t)0x77c20ca1, (q31_t)0xe0952dcb, + (q31_t)0x77bbe05a, (q31_t)0xe08a3bb2, (q31_t)0x77b5b1ec, (q31_t)0xe07f4acf, + (q31_t)0x77af8159, (q31_t)0xe0745b24, (q31_t)0x77a94ea0, (q31_t)0xe0696cb0, + (q31_t)0x77a319c2, (q31_t)0xe05e7f74, (q31_t)0x779ce2be, (q31_t)0xe053936f, + (q31_t)0x7796a996, (q31_t)0xe048a8a4, (q31_t)0x77906e49, (q31_t)0xe03dbf11, + (q31_t)0x778a30d8, (q31_t)0xe032d6b8, (q31_t)0x7783f143, (q31_t)0xe027ef99, + (q31_t)0x777daf89, (q31_t)0xe01d09b4, (q31_t)0x77776bac, (q31_t)0xe012250a, + (q31_t)0x777125ac, (q31_t)0xe007419b, (q31_t)0x776add88, (q31_t)0xdffc5f67, + (q31_t)0x77649341, (q31_t)0xdff17e70, (q31_t)0x775e46d8, (q31_t)0xdfe69eb4, + (q31_t)0x7757f84c, (q31_t)0xdfdbc036, (q31_t)0x7751a79e, (q31_t)0xdfd0e2f5, + (q31_t)0x774b54ce, (q31_t)0xdfc606f1, (q31_t)0x7744ffdd, (q31_t)0xdfbb2c2c, + (q31_t)0x773ea8ca, (q31_t)0xdfb052a5, (q31_t)0x77384f95, (q31_t)0xdfa57a5d, + (q31_t)0x7731f440, (q31_t)0xdf9aa354, (q31_t)0x772b96ca, (q31_t)0xdf8fcd8b, + (q31_t)0x77253733, (q31_t)0xdf84f902, (q31_t)0x771ed57c, (q31_t)0xdf7a25ba, + (q31_t)0x771871a5, (q31_t)0xdf6f53b3, (q31_t)0x77120bae, (q31_t)0xdf6482ed, + (q31_t)0x770ba398, (q31_t)0xdf59b369, (q31_t)0x77053962, (q31_t)0xdf4ee527, + (q31_t)0x76fecd0e, (q31_t)0xdf441828, (q31_t)0x76f85e9a, (q31_t)0xdf394c6b, + (q31_t)0x76f1ee09, (q31_t)0xdf2e81f3, (q31_t)0x76eb7b58, (q31_t)0xdf23b8be, + (q31_t)0x76e5068a, (q31_t)0xdf18f0ce, (q31_t)0x76de8f9e, (q31_t)0xdf0e2a22, + (q31_t)0x76d81695, (q31_t)0xdf0364bc, (q31_t)0x76d19b6e, (q31_t)0xdef8a09b, + (q31_t)0x76cb1e2a, (q31_t)0xdeedddc0, (q31_t)0x76c49ec9, (q31_t)0xdee31c2b, + (q31_t)0x76be1d4c, (q31_t)0xded85bdd, (q31_t)0x76b799b3, (q31_t)0xdecd9cd7, + (q31_t)0x76b113fd, (q31_t)0xdec2df18, (q31_t)0x76aa8c2c, (q31_t)0xdeb822a1, + (q31_t)0x76a4023f, (q31_t)0xdead6773, (q31_t)0x769d7637, (q31_t)0xdea2ad8d, + (q31_t)0x7696e814, (q31_t)0xde97f4f1, (q31_t)0x769057d6, (q31_t)0xde8d3d9e, + (q31_t)0x7689c57d, (q31_t)0xde828796, (q31_t)0x7683310b, (q31_t)0xde77d2d8, + (q31_t)0x767c9a7e, (q31_t)0xde6d1f65, (q31_t)0x767601d7, (q31_t)0xde626d3e, + (q31_t)0x766f6717, (q31_t)0xde57bc62, (q31_t)0x7668ca3e, (q31_t)0xde4d0cd2, + (q31_t)0x76622b4c, (q31_t)0xde425e8f, (q31_t)0x765b8a41, (q31_t)0xde37b199, + (q31_t)0x7654e71d, (q31_t)0xde2d05f1, (q31_t)0x764e41e2, (q31_t)0xde225b96, + (q31_t)0x76479a8e, (q31_t)0xde17b28a, (q31_t)0x7640f123, (q31_t)0xde0d0acc, + (q31_t)0x763a45a0, (q31_t)0xde02645d, (q31_t)0x76339806, (q31_t)0xddf7bf3e, + (q31_t)0x762ce855, (q31_t)0xdded1b6e, (q31_t)0x7626368d, (q31_t)0xdde278ef, + (q31_t)0x761f82af, (q31_t)0xddd7d7c1, (q31_t)0x7618ccba, (q31_t)0xddcd37e4, + (q31_t)0x761214b0, (q31_t)0xddc29958, (q31_t)0x760b5a90, (q31_t)0xddb7fc1e, + (q31_t)0x76049e5b, (q31_t)0xddad6036, (q31_t)0x75fde011, (q31_t)0xdda2c5a2, + (q31_t)0x75f71fb1, (q31_t)0xdd982c60, (q31_t)0x75f05d3d, (q31_t)0xdd8d9472, + (q31_t)0x75e998b5, (q31_t)0xdd82fdd8, (q31_t)0x75e2d219, (q31_t)0xdd786892, + (q31_t)0x75dc0968, (q31_t)0xdd6dd4a2, (q31_t)0x75d53ea5, (q31_t)0xdd634206, + (q31_t)0x75ce71ce, (q31_t)0xdd58b0c0, (q31_t)0x75c7a2e3, (q31_t)0xdd4e20d0, + (q31_t)0x75c0d1e7, (q31_t)0xdd439236, (q31_t)0x75b9fed7, (q31_t)0xdd3904f4, + (q31_t)0x75b329b5, (q31_t)0xdd2e7908, (q31_t)0x75ac5282, (q31_t)0xdd23ee74, + (q31_t)0x75a5793c, (q31_t)0xdd196538, (q31_t)0x759e9de5, (q31_t)0xdd0edd55, + (q31_t)0x7597c07d, (q31_t)0xdd0456ca, (q31_t)0x7590e104, (q31_t)0xdcf9d199, + (q31_t)0x7589ff7a, (q31_t)0xdcef4dc2, (q31_t)0x75831be0, (q31_t)0xdce4cb44, + (q31_t)0x757c3636, (q31_t)0xdcda4a21, (q31_t)0x75754e7c, (q31_t)0xdccfca59, + (q31_t)0x756e64b2, (q31_t)0xdcc54bec, (q31_t)0x756778d9, (q31_t)0xdcbacedb, + (q31_t)0x75608af1, (q31_t)0xdcb05326, (q31_t)0x75599afa, (q31_t)0xdca5d8cd, + (q31_t)0x7552a8f4, (q31_t)0xdc9b5fd2, (q31_t)0x754bb4e1, (q31_t)0xdc90e834, + (q31_t)0x7544bebf, (q31_t)0xdc8671f3, (q31_t)0x753dc68f, (q31_t)0xdc7bfd11, + (q31_t)0x7536cc52, (q31_t)0xdc71898d, (q31_t)0x752fd008, (q31_t)0xdc671768, + (q31_t)0x7528d1b1, (q31_t)0xdc5ca6a2, (q31_t)0x7521d14d, (q31_t)0xdc52373c, + (q31_t)0x751acedd, (q31_t)0xdc47c936, (q31_t)0x7513ca60, (q31_t)0xdc3d5c91, + (q31_t)0x750cc3d8, (q31_t)0xdc32f14d, (q31_t)0x7505bb44, (q31_t)0xdc28876a, + (q31_t)0x74feb0a5, (q31_t)0xdc1e1ee9, (q31_t)0x74f7a3fb, (q31_t)0xdc13b7c9, + (q31_t)0x74f09546, (q31_t)0xdc09520d, (q31_t)0x74e98487, (q31_t)0xdbfeedb3, + (q31_t)0x74e271bd, (q31_t)0xdbf48abd, (q31_t)0x74db5cea, (q31_t)0xdbea292b, + (q31_t)0x74d4460c, (q31_t)0xdbdfc8fc, (q31_t)0x74cd2d26, (q31_t)0xdbd56a32, + (q31_t)0x74c61236, (q31_t)0xdbcb0cce, (q31_t)0x74bef53d, (q31_t)0xdbc0b0ce, + (q31_t)0x74b7d63c, (q31_t)0xdbb65634, (q31_t)0x74b0b533, (q31_t)0xdbabfd01, + (q31_t)0x74a99221, (q31_t)0xdba1a534, (q31_t)0x74a26d08, (q31_t)0xdb974ece, + (q31_t)0x749b45e7, (q31_t)0xdb8cf9cf, (q31_t)0x74941cbf, (q31_t)0xdb82a638, + (q31_t)0x748cf190, (q31_t)0xdb785409, (q31_t)0x7485c45b, (q31_t)0xdb6e0342, + (q31_t)0x747e951f, (q31_t)0xdb63b3e5, (q31_t)0x747763dd, (q31_t)0xdb5965f1, + (q31_t)0x74703095, (q31_t)0xdb4f1967, (q31_t)0x7468fb47, (q31_t)0xdb44ce46, + (q31_t)0x7461c3f5, (q31_t)0xdb3a8491, (q31_t)0x745a8a9d, (q31_t)0xdb303c46, + (q31_t)0x74534f41, (q31_t)0xdb25f566, (q31_t)0x744c11e0, (q31_t)0xdb1baff2, + (q31_t)0x7444d27b, (q31_t)0xdb116beb, (q31_t)0x743d9112, (q31_t)0xdb072950, + (q31_t)0x74364da6, (q31_t)0xdafce821, (q31_t)0x742f0836, (q31_t)0xdaf2a860, + (q31_t)0x7427c0c3, (q31_t)0xdae86a0d, (q31_t)0x7420774d, (q31_t)0xdade2d28, + (q31_t)0x74192bd5, (q31_t)0xdad3f1b1, (q31_t)0x7411de5b, (q31_t)0xdac9b7a9, + (q31_t)0x740a8edf, (q31_t)0xdabf7f11, (q31_t)0x74033d61, (q31_t)0xdab547e8, + (q31_t)0x73fbe9e2, (q31_t)0xdaab122f, (q31_t)0x73f49462, (q31_t)0xdaa0dde7, + (q31_t)0x73ed3ce1, (q31_t)0xda96ab0f, (q31_t)0x73e5e360, (q31_t)0xda8c79a9, + (q31_t)0x73de87de, (q31_t)0xda8249b4, (q31_t)0x73d72a5d, (q31_t)0xda781b31, + (q31_t)0x73cfcadc, (q31_t)0xda6dee21, (q31_t)0x73c8695b, (q31_t)0xda63c284, + (q31_t)0x73c105db, (q31_t)0xda599859, (q31_t)0x73b9a05d, (q31_t)0xda4f6fa3, + (q31_t)0x73b238e0, (q31_t)0xda454860, (q31_t)0x73aacf65, (q31_t)0xda3b2292, + (q31_t)0x73a363ec, (q31_t)0xda30fe38, (q31_t)0x739bf675, (q31_t)0xda26db54, + (q31_t)0x73948701, (q31_t)0xda1cb9e5, (q31_t)0x738d1590, (q31_t)0xda1299ec, + (q31_t)0x7385a222, (q31_t)0xda087b69, (q31_t)0x737e2cb7, (q31_t)0xd9fe5e5e, + (q31_t)0x7376b551, (q31_t)0xd9f442c9, (q31_t)0x736f3bee, (q31_t)0xd9ea28ac, + (q31_t)0x7367c090, (q31_t)0xd9e01006, (q31_t)0x73604336, (q31_t)0xd9d5f8d9, + (q31_t)0x7358c3e2, (q31_t)0xd9cbe325, (q31_t)0x73514292, (q31_t)0xd9c1cee9, + (q31_t)0x7349bf48, (q31_t)0xd9b7bc27, (q31_t)0x73423a04, (q31_t)0xd9adaadf, + (q31_t)0x733ab2c6, (q31_t)0xd9a39b11, (q31_t)0x7333298f, (q31_t)0xd9998cbe, + (q31_t)0x732b9e5e, (q31_t)0xd98f7fe6, (q31_t)0x73241134, (q31_t)0xd9857489, + (q31_t)0x731c8211, (q31_t)0xd97b6aa8, (q31_t)0x7314f0f6, (q31_t)0xd9716243, + (q31_t)0x730d5de3, (q31_t)0xd9675b5a, (q31_t)0x7305c8d7, (q31_t)0xd95d55ef, + (q31_t)0x72fe31d5, (q31_t)0xd9535201, (q31_t)0x72f698db, (q31_t)0xd9494f90, + (q31_t)0x72eefdea, (q31_t)0xd93f4e9e, (q31_t)0x72e76102, (q31_t)0xd9354f2a, + (q31_t)0x72dfc224, (q31_t)0xd92b5135, (q31_t)0x72d82150, (q31_t)0xd92154bf, + (q31_t)0x72d07e85, (q31_t)0xd91759c9, (q31_t)0x72c8d9c6, (q31_t)0xd90d6053, + (q31_t)0x72c13311, (q31_t)0xd903685d, (q31_t)0x72b98a67, (q31_t)0xd8f971e8, + (q31_t)0x72b1dfc9, (q31_t)0xd8ef7cf4, (q31_t)0x72aa3336, (q31_t)0xd8e58982, + (q31_t)0x72a284b0, (q31_t)0xd8db9792, (q31_t)0x729ad435, (q31_t)0xd8d1a724, + (q31_t)0x729321c7, (q31_t)0xd8c7b838, (q31_t)0x728b6d66, (q31_t)0xd8bdcad0, + (q31_t)0x7283b712, (q31_t)0xd8b3deeb, (q31_t)0x727bfecc, (q31_t)0xd8a9f48a, + (q31_t)0x72744493, (q31_t)0xd8a00bae, (q31_t)0x726c8868, (q31_t)0xd8962456, + (q31_t)0x7264ca4c, (q31_t)0xd88c3e83, (q31_t)0x725d0a3e, (q31_t)0xd8825a35, + (q31_t)0x72554840, (q31_t)0xd878776d, (q31_t)0x724d8450, (q31_t)0xd86e962b, + (q31_t)0x7245be70, (q31_t)0xd864b670, (q31_t)0x723df6a0, (q31_t)0xd85ad83c, + (q31_t)0x72362ce0, (q31_t)0xd850fb8e, (q31_t)0x722e6130, (q31_t)0xd8472069, + (q31_t)0x72269391, (q31_t)0xd83d46cc, (q31_t)0x721ec403, (q31_t)0xd8336eb7, + (q31_t)0x7216f287, (q31_t)0xd829982b, (q31_t)0x720f1f1c, (q31_t)0xd81fc328, + (q31_t)0x720749c3, (q31_t)0xd815efae, (q31_t)0x71ff727c, (q31_t)0xd80c1dbf, + (q31_t)0x71f79948, (q31_t)0xd8024d59, (q31_t)0x71efbe27, (q31_t)0xd7f87e7f, + (q31_t)0x71e7e118, (q31_t)0xd7eeb130, (q31_t)0x71e0021e, (q31_t)0xd7e4e56c, + (q31_t)0x71d82137, (q31_t)0xd7db1b34, (q31_t)0x71d03e64, (q31_t)0xd7d15288, + (q31_t)0x71c859a5, (q31_t)0xd7c78b68, (q31_t)0x71c072fb, (q31_t)0xd7bdc5d6, + (q31_t)0x71b88a66, (q31_t)0xd7b401d1, (q31_t)0x71b09fe7, (q31_t)0xd7aa3f5a, + (q31_t)0x71a8b37c, (q31_t)0xd7a07e70, (q31_t)0x71a0c528, (q31_t)0xd796bf16, + (q31_t)0x7198d4ea, (q31_t)0xd78d014a, (q31_t)0x7190e2c3, (q31_t)0xd783450d, + (q31_t)0x7188eeb2, (q31_t)0xd7798a60, (q31_t)0x7180f8b8, (q31_t)0xd76fd143, + (q31_t)0x717900d6, (q31_t)0xd76619b6, (q31_t)0x7171070c, (q31_t)0xd75c63ba, + (q31_t)0x71690b59, (q31_t)0xd752af4f, (q31_t)0x71610dbf, (q31_t)0xd748fc75, + (q31_t)0x71590e3e, (q31_t)0xd73f4b2e, (q31_t)0x71510cd5, (q31_t)0xd7359b78, + (q31_t)0x71490986, (q31_t)0xd72bed55, (q31_t)0x71410450, (q31_t)0xd72240c5, + (q31_t)0x7138fd35, (q31_t)0xd71895c9, (q31_t)0x7130f433, (q31_t)0xd70eec60, + (q31_t)0x7128e94c, (q31_t)0xd705448b, (q31_t)0x7120dc80, (q31_t)0xd6fb9e4b, + (q31_t)0x7118cdcf, (q31_t)0xd6f1f99f, (q31_t)0x7110bd39, (q31_t)0xd6e85689, + (q31_t)0x7108aabf, (q31_t)0xd6deb508, (q31_t)0x71009661, (q31_t)0xd6d5151d, + (q31_t)0x70f8801f, (q31_t)0xd6cb76c9, (q31_t)0x70f067fb, (q31_t)0xd6c1da0b, + (q31_t)0x70e84df3, (q31_t)0xd6b83ee4, (q31_t)0x70e03208, (q31_t)0xd6aea555, + (q31_t)0x70d8143b, (q31_t)0xd6a50d5d, (q31_t)0x70cff48c, (q31_t)0xd69b76fe, + (q31_t)0x70c7d2fb, (q31_t)0xd691e237, (q31_t)0x70bfaf89, (q31_t)0xd6884f09, + (q31_t)0x70b78a36, (q31_t)0xd67ebd74, (q31_t)0x70af6302, (q31_t)0xd6752d79, + (q31_t)0x70a739ed, (q31_t)0xd66b9f18, (q31_t)0x709f0ef8, (q31_t)0xd6621251, + (q31_t)0x7096e223, (q31_t)0xd6588725, (q31_t)0x708eb36f, (q31_t)0xd64efd94, + (q31_t)0x708682dc, (q31_t)0xd645759f, (q31_t)0x707e5069, (q31_t)0xd63bef46, + (q31_t)0x70761c18, (q31_t)0xd6326a88, (q31_t)0x706de5e9, (q31_t)0xd628e767, + (q31_t)0x7065addb, (q31_t)0xd61f65e4, (q31_t)0x705d73f0, (q31_t)0xd615e5fd, + (q31_t)0x70553828, (q31_t)0xd60c67b4, (q31_t)0x704cfa83, (q31_t)0xd602eb0a, + (q31_t)0x7044bb00, (q31_t)0xd5f96ffd, (q31_t)0x703c79a2, (q31_t)0xd5eff690, + (q31_t)0x70343667, (q31_t)0xd5e67ec1, (q31_t)0x702bf151, (q31_t)0xd5dd0892, + (q31_t)0x7023aa5f, (q31_t)0xd5d39403, (q31_t)0x701b6193, (q31_t)0xd5ca2115, + (q31_t)0x701316eb, (q31_t)0xd5c0afc6, (q31_t)0x700aca69, (q31_t)0xd5b74019, + (q31_t)0x70027c0c, (q31_t)0xd5add20d, (q31_t)0x6ffa2bd6, (q31_t)0xd5a465a3, + (q31_t)0x6ff1d9c7, (q31_t)0xd59afadb, (q31_t)0x6fe985de, (q31_t)0xd59191b5, + (q31_t)0x6fe1301c, (q31_t)0xd5882a32, (q31_t)0x6fd8d882, (q31_t)0xd57ec452, + (q31_t)0x6fd07f0f, (q31_t)0xd5756016, (q31_t)0x6fc823c5, (q31_t)0xd56bfd7d, + (q31_t)0x6fbfc6a3, (q31_t)0xd5629c89, (q31_t)0x6fb767aa, (q31_t)0xd5593d3a, + (q31_t)0x6faf06da, (q31_t)0xd54fdf8f, (q31_t)0x6fa6a433, (q31_t)0xd5468389, + (q31_t)0x6f9e3fb6, (q31_t)0xd53d292a, (q31_t)0x6f95d963, (q31_t)0xd533d070, + (q31_t)0x6f8d713a, (q31_t)0xd52a795d, (q31_t)0x6f85073c, (q31_t)0xd52123f0, + (q31_t)0x6f7c9b69, (q31_t)0xd517d02b, (q31_t)0x6f742dc1, (q31_t)0xd50e7e0d, + (q31_t)0x6f6bbe45, (q31_t)0xd5052d97, (q31_t)0x6f634cf5, (q31_t)0xd4fbdec9, + (q31_t)0x6f5ad9d1, (q31_t)0xd4f291a4, (q31_t)0x6f5264da, (q31_t)0xd4e94627, + (q31_t)0x6f49ee0f, (q31_t)0xd4dffc54, (q31_t)0x6f417573, (q31_t)0xd4d6b42b, + (q31_t)0x6f38fb03, (q31_t)0xd4cd6dab, (q31_t)0x6f307ec2, (q31_t)0xd4c428d6, + (q31_t)0x6f2800af, (q31_t)0xd4bae5ab, (q31_t)0x6f1f80ca, (q31_t)0xd4b1a42c, + (q31_t)0x6f16ff14, (q31_t)0xd4a86458, (q31_t)0x6f0e7b8e, (q31_t)0xd49f2630, + (q31_t)0x6f05f637, (q31_t)0xd495e9b3, (q31_t)0x6efd6f10, (q31_t)0xd48caee4, + (q31_t)0x6ef4e619, (q31_t)0xd48375c1, (q31_t)0x6eec5b53, (q31_t)0xd47a3e4b, + (q31_t)0x6ee3cebe, (q31_t)0xd4710883, (q31_t)0x6edb405a, (q31_t)0xd467d469, + (q31_t)0x6ed2b027, (q31_t)0xd45ea1fd, (q31_t)0x6eca1e27, (q31_t)0xd4557140, + (q31_t)0x6ec18a58, (q31_t)0xd44c4232, (q31_t)0x6eb8f4bc, (q31_t)0xd44314d3, + (q31_t)0x6eb05d53, (q31_t)0xd439e923, (q31_t)0x6ea7c41e, (q31_t)0xd430bf24, + (q31_t)0x6e9f291b, (q31_t)0xd42796d5, (q31_t)0x6e968c4d, (q31_t)0xd41e7037, + (q31_t)0x6e8dedb3, (q31_t)0xd4154b4a, (q31_t)0x6e854d4d, (q31_t)0xd40c280e, + (q31_t)0x6e7cab1c, (q31_t)0xd4030684, (q31_t)0x6e740720, (q31_t)0xd3f9e6ad, + (q31_t)0x6e6b615a, (q31_t)0xd3f0c887, (q31_t)0x6e62b9ca, (q31_t)0xd3e7ac15, + (q31_t)0x6e5a1070, (q31_t)0xd3de9156, (q31_t)0x6e51654c, (q31_t)0xd3d5784a, + (q31_t)0x6e48b860, (q31_t)0xd3cc60f2, (q31_t)0x6e4009aa, (q31_t)0xd3c34b4f, + (q31_t)0x6e37592c, (q31_t)0xd3ba3760, (q31_t)0x6e2ea6e6, (q31_t)0xd3b12526, + (q31_t)0x6e25f2d8, (q31_t)0xd3a814a2, (q31_t)0x6e1d3d03, (q31_t)0xd39f05d3, + (q31_t)0x6e148566, (q31_t)0xd395f8ba, (q31_t)0x6e0bcc03, (q31_t)0xd38ced57, + (q31_t)0x6e0310d9, (q31_t)0xd383e3ab, (q31_t)0x6dfa53e9, (q31_t)0xd37adbb6, + (q31_t)0x6df19534, (q31_t)0xd371d579, (q31_t)0x6de8d4b8, (q31_t)0xd368d0f3, + (q31_t)0x6de01278, (q31_t)0xd35fce26, (q31_t)0x6dd74e73, (q31_t)0xd356cd11, + (q31_t)0x6dce88aa, (q31_t)0xd34dcdb4, (q31_t)0x6dc5c11c, (q31_t)0xd344d011, + (q31_t)0x6dbcf7cb, (q31_t)0xd33bd427, (q31_t)0x6db42cb6, (q31_t)0xd332d9f7, + (q31_t)0x6dab5fdf, (q31_t)0xd329e181, (q31_t)0x6da29144, (q31_t)0xd320eac6, + (q31_t)0x6d99c0e7, (q31_t)0xd317f5c6, (q31_t)0x6d90eec8, (q31_t)0xd30f0280, + (q31_t)0x6d881ae8, (q31_t)0xd30610f7, (q31_t)0x6d7f4545, (q31_t)0xd2fd2129, + (q31_t)0x6d766de2, (q31_t)0xd2f43318, (q31_t)0x6d6d94bf, (q31_t)0xd2eb46c3, + (q31_t)0x6d64b9da, (q31_t)0xd2e25c2b, (q31_t)0x6d5bdd36, (q31_t)0xd2d97350, + (q31_t)0x6d52fed2, (q31_t)0xd2d08c33, (q31_t)0x6d4a1eaf, (q31_t)0xd2c7a6d4, + (q31_t)0x6d413ccd, (q31_t)0xd2bec333, (q31_t)0x6d38592c, (q31_t)0xd2b5e151, + (q31_t)0x6d2f73cd, (q31_t)0xd2ad012e, (q31_t)0x6d268cb0, (q31_t)0xd2a422ca, + (q31_t)0x6d1da3d5, (q31_t)0xd29b4626, (q31_t)0x6d14b93d, (q31_t)0xd2926b41, + (q31_t)0x6d0bcce8, (q31_t)0xd289921e, (q31_t)0x6d02ded7, (q31_t)0xd280babb, + (q31_t)0x6cf9ef09, (q31_t)0xd277e518, (q31_t)0x6cf0fd80, (q31_t)0xd26f1138, + (q31_t)0x6ce80a3a, (q31_t)0xd2663f19, (q31_t)0x6cdf153a, (q31_t)0xd25d6ebc, + (q31_t)0x6cd61e7f, (q31_t)0xd254a021, (q31_t)0x6ccd2609, (q31_t)0xd24bd34a, + (q31_t)0x6cc42bd9, (q31_t)0xd2430835, (q31_t)0x6cbb2fef, (q31_t)0xd23a3ee4, + (q31_t)0x6cb2324c, (q31_t)0xd2317756, (q31_t)0x6ca932ef, (q31_t)0xd228b18d, + (q31_t)0x6ca031da, (q31_t)0xd21fed88, (q31_t)0x6c972f0d, (q31_t)0xd2172b48, + (q31_t)0x6c8e2a87, (q31_t)0xd20e6acc, (q31_t)0x6c85244a, (q31_t)0xd205ac17, + (q31_t)0x6c7c1c55, (q31_t)0xd1fcef27, (q31_t)0x6c7312a9, (q31_t)0xd1f433fd, + (q31_t)0x6c6a0746, (q31_t)0xd1eb7a9a, (q31_t)0x6c60fa2d, (q31_t)0xd1e2c2fd, + (q31_t)0x6c57eb5e, (q31_t)0xd1da0d28, (q31_t)0x6c4edada, (q31_t)0xd1d1591a, + (q31_t)0x6c45c8a0, (q31_t)0xd1c8a6d4, (q31_t)0x6c3cb4b1, (q31_t)0xd1bff656, + (q31_t)0x6c339f0e, (q31_t)0xd1b747a0, (q31_t)0x6c2a87b6, (q31_t)0xd1ae9ab4, + (q31_t)0x6c216eaa, (q31_t)0xd1a5ef90, (q31_t)0x6c1853eb, (q31_t)0xd19d4636, + (q31_t)0x6c0f3779, (q31_t)0xd1949ea6, (q31_t)0x6c061953, (q31_t)0xd18bf8e0, + (q31_t)0x6bfcf97c, (q31_t)0xd18354e4, (q31_t)0x6bf3d7f2, (q31_t)0xd17ab2b3, + (q31_t)0x6beab4b6, (q31_t)0xd172124d, (q31_t)0x6be18fc9, (q31_t)0xd16973b3, + (q31_t)0x6bd8692b, (q31_t)0xd160d6e5, (q31_t)0x6bcf40dc, (q31_t)0xd1583be2, + (q31_t)0x6bc616dd, (q31_t)0xd14fa2ad, (q31_t)0x6bbceb2d, (q31_t)0xd1470b44, + (q31_t)0x6bb3bdce, (q31_t)0xd13e75a8, (q31_t)0x6baa8ec0, (q31_t)0xd135e1d9, + (q31_t)0x6ba15e03, (q31_t)0xd12d4fd9, (q31_t)0x6b982b97, (q31_t)0xd124bfa6, + (q31_t)0x6b8ef77d, (q31_t)0xd11c3142, (q31_t)0x6b85c1b5, (q31_t)0xd113a4ad, + (q31_t)0x6b7c8a3f, (q31_t)0xd10b19e7, (q31_t)0x6b73511c, (q31_t)0xd10290f0, + (q31_t)0x6b6a164d, (q31_t)0xd0fa09c9, (q31_t)0x6b60d9d0, (q31_t)0xd0f18472, + (q31_t)0x6b579ba8, (q31_t)0xd0e900ec, (q31_t)0x6b4e5bd4, (q31_t)0xd0e07f36, + (q31_t)0x6b451a55, (q31_t)0xd0d7ff51, (q31_t)0x6b3bd72a, (q31_t)0xd0cf813e, + (q31_t)0x6b329255, (q31_t)0xd0c704fd, (q31_t)0x6b294bd5, (q31_t)0xd0be8a8d, + (q31_t)0x6b2003ac, (q31_t)0xd0b611f1, (q31_t)0x6b16b9d9, (q31_t)0xd0ad9b26, + (q31_t)0x6b0d6e5c, (q31_t)0xd0a5262f, (q31_t)0x6b042137, (q31_t)0xd09cb30b, + (q31_t)0x6afad269, (q31_t)0xd09441bb, (q31_t)0x6af181f3, (q31_t)0xd08bd23f, + (q31_t)0x6ae82fd5, (q31_t)0xd0836497, (q31_t)0x6adedc10, (q31_t)0xd07af8c4, + (q31_t)0x6ad586a3, (q31_t)0xd0728ec6, (q31_t)0x6acc2f90, (q31_t)0xd06a269d, + (q31_t)0x6ac2d6d6, (q31_t)0xd061c04a, (q31_t)0x6ab97c77, (q31_t)0xd0595bcd, + (q31_t)0x6ab02071, (q31_t)0xd050f926, (q31_t)0x6aa6c2c6, (q31_t)0xd0489856, + (q31_t)0x6a9d6377, (q31_t)0xd040395d, (q31_t)0x6a940283, (q31_t)0xd037dc3b, + (q31_t)0x6a8a9fea, (q31_t)0xd02f80f1, (q31_t)0x6a813bae, (q31_t)0xd027277e, + (q31_t)0x6a77d5ce, (q31_t)0xd01ecfe4, (q31_t)0x6a6e6e4b, (q31_t)0xd0167a22, + (q31_t)0x6a650525, (q31_t)0xd00e2639, (q31_t)0x6a5b9a5d, (q31_t)0xd005d42a, + (q31_t)0x6a522df3, (q31_t)0xcffd83f4, (q31_t)0x6a48bfe7, (q31_t)0xcff53597, + (q31_t)0x6a3f503a, (q31_t)0xcfece915, (q31_t)0x6a35deeb, (q31_t)0xcfe49e6d, + (q31_t)0x6a2c6bfd, (q31_t)0xcfdc55a1, (q31_t)0x6a22f76e, (q31_t)0xcfd40eaf, + (q31_t)0x6a19813f, (q31_t)0xcfcbc999, (q31_t)0x6a100970, (q31_t)0xcfc3865e, + (q31_t)0x6a069003, (q31_t)0xcfbb4500, (q31_t)0x69fd14f6, (q31_t)0xcfb3057d, + (q31_t)0x69f3984c, (q31_t)0xcfaac7d8, (q31_t)0x69ea1a03, (q31_t)0xcfa28c10, + (q31_t)0x69e09a1c, (q31_t)0xcf9a5225, (q31_t)0x69d71899, (q31_t)0xcf921a17, + (q31_t)0x69cd9578, (q31_t)0xcf89e3e8, (q31_t)0x69c410ba, (q31_t)0xcf81af97, + (q31_t)0x69ba8a61, (q31_t)0xcf797d24, (q31_t)0x69b1026c, (q31_t)0xcf714c91, + (q31_t)0x69a778db, (q31_t)0xcf691ddd, (q31_t)0x699dedaf, (q31_t)0xcf60f108, + (q31_t)0x699460e8, (q31_t)0xcf58c613, (q31_t)0x698ad287, (q31_t)0xcf509cfe, + (q31_t)0x6981428c, (q31_t)0xcf4875ca, (q31_t)0x6977b0f7, (q31_t)0xcf405077, + (q31_t)0x696e1dc9, (q31_t)0xcf382d05, (q31_t)0x69648902, (q31_t)0xcf300b74, + (q31_t)0x695af2a3, (q31_t)0xcf27ebc5, (q31_t)0x69515aab, (q31_t)0xcf1fcdf8, + (q31_t)0x6947c11c, (q31_t)0xcf17b20d, (q31_t)0x693e25f5, (q31_t)0xcf0f9805, + (q31_t)0x69348937, (q31_t)0xcf077fe1, (q31_t)0x692aeae3, (q31_t)0xceff699f, + (q31_t)0x69214af8, (q31_t)0xcef75541, (q31_t)0x6917a977, (q31_t)0xceef42c7, + (q31_t)0x690e0661, (q31_t)0xcee73231, (q31_t)0x690461b5, (q31_t)0xcedf2380, + (q31_t)0x68fabb75, (q31_t)0xced716b4, (q31_t)0x68f113a0, (q31_t)0xcecf0bcd, + (q31_t)0x68e76a37, (q31_t)0xcec702cb, (q31_t)0x68ddbf3b, (q31_t)0xcebefbb0, + (q31_t)0x68d412ab, (q31_t)0xceb6f67a, (q31_t)0x68ca6488, (q31_t)0xceaef32b, + (q31_t)0x68c0b4d2, (q31_t)0xcea6f1c2, (q31_t)0x68b7038b, (q31_t)0xce9ef241, + (q31_t)0x68ad50b1, (q31_t)0xce96f4a7, (q31_t)0x68a39c46, (q31_t)0xce8ef8f4, + (q31_t)0x6899e64a, (q31_t)0xce86ff2a, (q31_t)0x68902ebd, (q31_t)0xce7f0748, + (q31_t)0x688675a0, (q31_t)0xce77114e, (q31_t)0x687cbaf3, (q31_t)0xce6f1d3d, + (q31_t)0x6872feb6, (q31_t)0xce672b16, (q31_t)0x686940ea, (q31_t)0xce5f3ad8, + (q31_t)0x685f8190, (q31_t)0xce574c84, (q31_t)0x6855c0a6, (q31_t)0xce4f6019, + (q31_t)0x684bfe2f, (q31_t)0xce47759a, (q31_t)0x68423a2a, (q31_t)0xce3f8d05, + (q31_t)0x68387498, (q31_t)0xce37a65b, (q31_t)0x682ead78, (q31_t)0xce2fc19c, + (q31_t)0x6824e4cc, (q31_t)0xce27dec9, (q31_t)0x681b1a94, (q31_t)0xce1ffde2, + (q31_t)0x68114ed0, (q31_t)0xce181ee8, (q31_t)0x68078181, (q31_t)0xce1041d9, + (q31_t)0x67fdb2a7, (q31_t)0xce0866b8, (q31_t)0x67f3e241, (q31_t)0xce008d84, + (q31_t)0x67ea1052, (q31_t)0xcdf8b63d, (q31_t)0x67e03cd8, (q31_t)0xcdf0e0e4, + (q31_t)0x67d667d5, (q31_t)0xcde90d79, (q31_t)0x67cc9149, (q31_t)0xcde13bfd, + (q31_t)0x67c2b934, (q31_t)0xcdd96c6f, (q31_t)0x67b8df97, (q31_t)0xcdd19ed0, + (q31_t)0x67af0472, (q31_t)0xcdc9d320, (q31_t)0x67a527c4, (q31_t)0xcdc20960, + (q31_t)0x679b4990, (q31_t)0xcdba4190, (q31_t)0x679169d5, (q31_t)0xcdb27bb0, + (q31_t)0x67878893, (q31_t)0xcdaab7c0, (q31_t)0x677da5cb, (q31_t)0xcda2f5c2, + (q31_t)0x6773c17d, (q31_t)0xcd9b35b4, (q31_t)0x6769dbaa, (q31_t)0xcd937798, + (q31_t)0x675ff452, (q31_t)0xcd8bbb6d, (q31_t)0x67560b76, (q31_t)0xcd840134, + (q31_t)0x674c2115, (q31_t)0xcd7c48ee, (q31_t)0x67423530, (q31_t)0xcd74929a, + (q31_t)0x673847c8, (q31_t)0xcd6cde39, (q31_t)0x672e58dc, (q31_t)0xcd652bcb, + (q31_t)0x6724686e, (q31_t)0xcd5d7b50, (q31_t)0x671a767e, (q31_t)0xcd55ccca, + (q31_t)0x6710830c, (q31_t)0xcd4e2037, (q31_t)0x67068e18, (q31_t)0xcd467599, + (q31_t)0x66fc97a3, (q31_t)0xcd3eccef, (q31_t)0x66f29fad, (q31_t)0xcd37263a, + (q31_t)0x66e8a637, (q31_t)0xcd2f817b, (q31_t)0x66deab41, (q31_t)0xcd27deb0, + (q31_t)0x66d4aecb, (q31_t)0xcd203ddc, (q31_t)0x66cab0d6, (q31_t)0xcd189efe, + (q31_t)0x66c0b162, (q31_t)0xcd110216, (q31_t)0x66b6b070, (q31_t)0xcd096725, + (q31_t)0x66acadff, (q31_t)0xcd01ce2b, (q31_t)0x66a2aa11, (q31_t)0xccfa3729, + (q31_t)0x6698a4a6, (q31_t)0xccf2a21d, (q31_t)0x668e9dbd, (q31_t)0xcceb0f0a, + (q31_t)0x66849558, (q31_t)0xcce37def, (q31_t)0x667a8b77, (q31_t)0xccdbeecc, + (q31_t)0x6670801a, (q31_t)0xccd461a2, (q31_t)0x66667342, (q31_t)0xccccd671, + (q31_t)0x665c64ef, (q31_t)0xccc54d3a, (q31_t)0x66525521, (q31_t)0xccbdc5fc, + (q31_t)0x664843d9, (q31_t)0xccb640b8, (q31_t)0x663e3117, (q31_t)0xccaebd6e, + (q31_t)0x66341cdb, (q31_t)0xcca73c1e, (q31_t)0x662a0727, (q31_t)0xcc9fbcca, + (q31_t)0x661feffa, (q31_t)0xcc983f70, (q31_t)0x6615d754, (q31_t)0xcc90c412, + (q31_t)0x660bbd37, (q31_t)0xcc894aaf, (q31_t)0x6601a1a2, (q31_t)0xcc81d349, + (q31_t)0x65f78497, (q31_t)0xcc7a5dde, (q31_t)0x65ed6614, (q31_t)0xcc72ea70, + (q31_t)0x65e3461b, (q31_t)0xcc6b78ff, (q31_t)0x65d924ac, (q31_t)0xcc64098b, + (q31_t)0x65cf01c8, (q31_t)0xcc5c9c14, (q31_t)0x65c4dd6e, (q31_t)0xcc55309b, + (q31_t)0x65bab7a0, (q31_t)0xcc4dc720, (q31_t)0x65b0905d, (q31_t)0xcc465fa3, + (q31_t)0x65a667a7, (q31_t)0xcc3efa25, (q31_t)0x659c3d7c, (q31_t)0xcc3796a5, + (q31_t)0x659211df, (q31_t)0xcc303524, (q31_t)0x6587e4cf, (q31_t)0xcc28d5a3, + (q31_t)0x657db64c, (q31_t)0xcc217822, (q31_t)0x65738657, (q31_t)0xcc1a1ca0, + (q31_t)0x656954f1, (q31_t)0xcc12c31f, (q31_t)0x655f2219, (q31_t)0xcc0b6b9e, + (q31_t)0x6554edd1, (q31_t)0xcc04161e, (q31_t)0x654ab818, (q31_t)0xcbfcc29f, + (q31_t)0x654080ef, (q31_t)0xcbf57121, (q31_t)0x65364857, (q31_t)0xcbee21a5, + (q31_t)0x652c0e4f, (q31_t)0xcbe6d42b, (q31_t)0x6521d2d8, (q31_t)0xcbdf88b3, + (q31_t)0x651795f3, (q31_t)0xcbd83f3d, (q31_t)0x650d57a0, (q31_t)0xcbd0f7ca, + (q31_t)0x650317df, (q31_t)0xcbc9b25a, (q31_t)0x64f8d6b0, (q31_t)0xcbc26eee, + (q31_t)0x64ee9415, (q31_t)0xcbbb2d85, (q31_t)0x64e4500e, (q31_t)0xcbb3ee20, + (q31_t)0x64da0a9a, (q31_t)0xcbacb0bf, (q31_t)0x64cfc3ba, (q31_t)0xcba57563, + (q31_t)0x64c57b6f, (q31_t)0xcb9e3c0b, (q31_t)0x64bb31ba, (q31_t)0xcb9704b9, + (q31_t)0x64b0e699, (q31_t)0xcb8fcf6b, (q31_t)0x64a69a0f, (q31_t)0xcb889c23, + (q31_t)0x649c4c1b, (q31_t)0xcb816ae1, (q31_t)0x6491fcbe, (q31_t)0xcb7a3ba5, + (q31_t)0x6487abf7, (q31_t)0xcb730e70, (q31_t)0x647d59c8, (q31_t)0xcb6be341, + (q31_t)0x64730631, (q31_t)0xcb64ba19, (q31_t)0x6468b132, (q31_t)0xcb5d92f8, + (q31_t)0x645e5acc, (q31_t)0xcb566ddf, (q31_t)0x645402ff, (q31_t)0xcb4f4acd, + (q31_t)0x6449a9cc, (q31_t)0xcb4829c4, (q31_t)0x643f4f32, (q31_t)0xcb410ac3, + (q31_t)0x6434f332, (q31_t)0xcb39edca, (q31_t)0x642a95ce, (q31_t)0xcb32d2da, + (q31_t)0x64203704, (q31_t)0xcb2bb9f4, (q31_t)0x6415d6d5, (q31_t)0xcb24a316, + (q31_t)0x640b7543, (q31_t)0xcb1d8e43, (q31_t)0x6401124d, (q31_t)0xcb167b79, + (q31_t)0x63f6adf3, (q31_t)0xcb0f6aba, (q31_t)0x63ec4837, (q31_t)0xcb085c05, + (q31_t)0x63e1e117, (q31_t)0xcb014f5b, (q31_t)0x63d77896, (q31_t)0xcafa44bc, + (q31_t)0x63cd0eb3, (q31_t)0xcaf33c28, (q31_t)0x63c2a36f, (q31_t)0xcaec35a0, + (q31_t)0x63b836ca, (q31_t)0xcae53123, (q31_t)0x63adc8c4, (q31_t)0xcade2eb3, + (q31_t)0x63a3595e, (q31_t)0xcad72e4f, (q31_t)0x6398e898, (q31_t)0xcad02ff8, + (q31_t)0x638e7673, (q31_t)0xcac933ae, (q31_t)0x638402ef, (q31_t)0xcac23971, + (q31_t)0x63798e0d, (q31_t)0xcabb4141, (q31_t)0x636f17cc, (q31_t)0xcab44b1f, + (q31_t)0x6364a02e, (q31_t)0xcaad570c, (q31_t)0x635a2733, (q31_t)0xcaa66506, + (q31_t)0x634facda, (q31_t)0xca9f750f, (q31_t)0x63453125, (q31_t)0xca988727, + (q31_t)0x633ab414, (q31_t)0xca919b4e, (q31_t)0x633035a7, (q31_t)0xca8ab184, + (q31_t)0x6325b5df, (q31_t)0xca83c9ca, (q31_t)0x631b34bc, (q31_t)0xca7ce420, + (q31_t)0x6310b23e, (q31_t)0xca760086, (q31_t)0x63062e67, (q31_t)0xca6f1efc, + (q31_t)0x62fba936, (q31_t)0xca683f83, (q31_t)0x62f122ab, (q31_t)0xca61621b, + (q31_t)0x62e69ac8, (q31_t)0xca5a86c4, (q31_t)0x62dc118c, (q31_t)0xca53ad7e, + (q31_t)0x62d186f8, (q31_t)0xca4cd64b, (q31_t)0x62c6fb0c, (q31_t)0xca460129, + (q31_t)0x62bc6dca, (q31_t)0xca3f2e19, (q31_t)0x62b1df30, (q31_t)0xca385d1d, + (q31_t)0x62a74f40, (q31_t)0xca318e32, (q31_t)0x629cbdfa, (q31_t)0xca2ac15b, + (q31_t)0x62922b5e, (q31_t)0xca23f698, (q31_t)0x6287976e, (q31_t)0xca1d2de7, + (q31_t)0x627d0228, (q31_t)0xca16674b, (q31_t)0x62726b8e, (q31_t)0xca0fa2c3, + (q31_t)0x6267d3a0, (q31_t)0xca08e04f, (q31_t)0x625d3a5e, (q31_t)0xca021fef, + (q31_t)0x62529fca, (q31_t)0xc9fb61a5, (q31_t)0x624803e2, (q31_t)0xc9f4a570, + (q31_t)0x623d66a8, (q31_t)0xc9edeb50, (q31_t)0x6232c81c, (q31_t)0xc9e73346, + (q31_t)0x6228283f, (q31_t)0xc9e07d51, (q31_t)0x621d8711, (q31_t)0xc9d9c973, + (q31_t)0x6212e492, (q31_t)0xc9d317ab, (q31_t)0x620840c2, (q31_t)0xc9cc67fa, + (q31_t)0x61fd9ba3, (q31_t)0xc9c5ba60, (q31_t)0x61f2f534, (q31_t)0xc9bf0edd, + (q31_t)0x61e84d76, (q31_t)0xc9b86572, (q31_t)0x61dda46a, (q31_t)0xc9b1be1e, + (q31_t)0x61d2fa0f, (q31_t)0xc9ab18e3, (q31_t)0x61c84e67, (q31_t)0xc9a475bf, + (q31_t)0x61bda171, (q31_t)0xc99dd4b4, (q31_t)0x61b2f32e, (q31_t)0xc99735c2, + (q31_t)0x61a8439e, (q31_t)0xc99098e9, (q31_t)0x619d92c2, (q31_t)0xc989fe29, + (q31_t)0x6192e09b, (q31_t)0xc9836582, (q31_t)0x61882d28, (q31_t)0xc97ccef5, + (q31_t)0x617d786a, (q31_t)0xc9763a83, (q31_t)0x6172c262, (q31_t)0xc96fa82a, + (q31_t)0x61680b0f, (q31_t)0xc96917ec, (q31_t)0x615d5273, (q31_t)0xc96289c9, + (q31_t)0x6152988d, (q31_t)0xc95bfdc1, (q31_t)0x6147dd5f, (q31_t)0xc95573d4, + (q31_t)0x613d20e8, (q31_t)0xc94eec03, (q31_t)0x61326329, (q31_t)0xc948664d, + (q31_t)0x6127a423, (q31_t)0xc941e2b4, (q31_t)0x611ce3d5, (q31_t)0xc93b6137, + (q31_t)0x61122240, (q31_t)0xc934e1d6, (q31_t)0x61075f65, (q31_t)0xc92e6492, + (q31_t)0x60fc9b44, (q31_t)0xc927e96b, (q31_t)0x60f1d5de, (q31_t)0xc9217062, + (q31_t)0x60e70f32, (q31_t)0xc91af976, (q31_t)0x60dc4742, (q31_t)0xc91484a8, + (q31_t)0x60d17e0d, (q31_t)0xc90e11f7, (q31_t)0x60c6b395, (q31_t)0xc907a166, + (q31_t)0x60bbe7d8, (q31_t)0xc90132f2, (q31_t)0x60b11ad9, (q31_t)0xc8fac69e, + (q31_t)0x60a64c97, (q31_t)0xc8f45c68, (q31_t)0x609b7d13, (q31_t)0xc8edf452, + (q31_t)0x6090ac4d, (q31_t)0xc8e78e5b, (q31_t)0x6085da46, (q31_t)0xc8e12a84, + (q31_t)0x607b06fe, (q31_t)0xc8dac8cd, (q31_t)0x60703275, (q31_t)0xc8d46936, + (q31_t)0x60655cac, (q31_t)0xc8ce0bc0, (q31_t)0x605a85a3, (q31_t)0xc8c7b06b, + (q31_t)0x604fad5b, (q31_t)0xc8c15736, (q31_t)0x6044d3d4, (q31_t)0xc8bb0023, + (q31_t)0x6039f90f, (q31_t)0xc8b4ab32, (q31_t)0x602f1d0b, (q31_t)0xc8ae5862, + (q31_t)0x60243fca, (q31_t)0xc8a807b4, (q31_t)0x6019614c, (q31_t)0xc8a1b928, + (q31_t)0x600e8190, (q31_t)0xc89b6cbf, (q31_t)0x6003a099, (q31_t)0xc8952278, + (q31_t)0x5ff8be65, (q31_t)0xc88eda54, (q31_t)0x5feddaf6, (q31_t)0xc8889454, + (q31_t)0x5fe2f64c, (q31_t)0xc8825077, (q31_t)0x5fd81067, (q31_t)0xc87c0ebd, + (q31_t)0x5fcd2948, (q31_t)0xc875cf28, (q31_t)0x5fc240ef, (q31_t)0xc86f91b7, + (q31_t)0x5fb7575c, (q31_t)0xc869566a, (q31_t)0x5fac6c91, (q31_t)0xc8631d42, + (q31_t)0x5fa1808c, (q31_t)0xc85ce63e, (q31_t)0x5f969350, (q31_t)0xc856b160, + (q31_t)0x5f8ba4dc, (q31_t)0xc8507ea7, (q31_t)0x5f80b531, (q31_t)0xc84a4e14, + (q31_t)0x5f75c44e, (q31_t)0xc8441fa6, (q31_t)0x5f6ad235, (q31_t)0xc83df35f, + (q31_t)0x5f5fdee6, (q31_t)0xc837c93e, (q31_t)0x5f54ea62, (q31_t)0xc831a143, + (q31_t)0x5f49f4a8, (q31_t)0xc82b7b70, (q31_t)0x5f3efdb9, (q31_t)0xc82557c3, + (q31_t)0x5f340596, (q31_t)0xc81f363d, (q31_t)0x5f290c3f, (q31_t)0xc81916df, + (q31_t)0x5f1e11b5, (q31_t)0xc812f9a9, (q31_t)0x5f1315f7, (q31_t)0xc80cde9b, + (q31_t)0x5f081907, (q31_t)0xc806c5b5, (q31_t)0x5efd1ae4, (q31_t)0xc800aef7, + (q31_t)0x5ef21b90, (q31_t)0xc7fa9a62, (q31_t)0x5ee71b0a, (q31_t)0xc7f487f6, + (q31_t)0x5edc1953, (q31_t)0xc7ee77b3, (q31_t)0x5ed1166b, (q31_t)0xc7e8699a, + (q31_t)0x5ec61254, (q31_t)0xc7e25daa, (q31_t)0x5ebb0d0d, (q31_t)0xc7dc53e3, + (q31_t)0x5eb00696, (q31_t)0xc7d64c47, (q31_t)0x5ea4fef0, (q31_t)0xc7d046d6, + (q31_t)0x5e99f61d, (q31_t)0xc7ca438f, (q31_t)0x5e8eec1b, (q31_t)0xc7c44272, + (q31_t)0x5e83e0eb, (q31_t)0xc7be4381, (q31_t)0x5e78d48e, (q31_t)0xc7b846ba, + (q31_t)0x5e6dc705, (q31_t)0xc7b24c20, (q31_t)0x5e62b84f, (q31_t)0xc7ac53b1, + (q31_t)0x5e57a86d, (q31_t)0xc7a65d6e, (q31_t)0x5e4c9760, (q31_t)0xc7a06957, + (q31_t)0x5e418528, (q31_t)0xc79a776c, (q31_t)0x5e3671c5, (q31_t)0xc79487ae, + (q31_t)0x5e2b5d38, (q31_t)0xc78e9a1d, (q31_t)0x5e204781, (q31_t)0xc788aeb9, + (q31_t)0x5e1530a1, (q31_t)0xc782c582, (q31_t)0x5e0a1898, (q31_t)0xc77cde79, + (q31_t)0x5dfeff67, (q31_t)0xc776f99d, (q31_t)0x5df3e50d, (q31_t)0xc77116f0, + (q31_t)0x5de8c98c, (q31_t)0xc76b3671, (q31_t)0x5dddace4, (q31_t)0xc7655820, + (q31_t)0x5dd28f15, (q31_t)0xc75f7bfe, (q31_t)0x5dc7701f, (q31_t)0xc759a20a, + (q31_t)0x5dbc5004, (q31_t)0xc753ca46, (q31_t)0x5db12ec3, (q31_t)0xc74df4b1, + (q31_t)0x5da60c5d, (q31_t)0xc748214c, (q31_t)0x5d9ae8d2, (q31_t)0xc7425016, + (q31_t)0x5d8fc424, (q31_t)0xc73c8111, (q31_t)0x5d849e51, (q31_t)0xc736b43c, + (q31_t)0x5d79775c, (q31_t)0xc730e997, (q31_t)0x5d6e4f43, (q31_t)0xc72b2123, + (q31_t)0x5d632608, (q31_t)0xc7255ae0, (q31_t)0x5d57fbaa, (q31_t)0xc71f96ce, + (q31_t)0x5d4cd02c, (q31_t)0xc719d4ed, (q31_t)0x5d41a38c, (q31_t)0xc714153e, + (q31_t)0x5d3675cb, (q31_t)0xc70e57c0, (q31_t)0x5d2b46ea, (q31_t)0xc7089c75, + (q31_t)0x5d2016e9, (q31_t)0xc702e35c, (q31_t)0x5d14e5c9, (q31_t)0xc6fd2c75, + (q31_t)0x5d09b389, (q31_t)0xc6f777c1, (q31_t)0x5cfe802b, (q31_t)0xc6f1c540, + (q31_t)0x5cf34baf, (q31_t)0xc6ec14f2, (q31_t)0x5ce81615, (q31_t)0xc6e666d7, + (q31_t)0x5cdcdf5e, (q31_t)0xc6e0baf0, (q31_t)0x5cd1a78a, (q31_t)0xc6db113d, + (q31_t)0x5cc66e99, (q31_t)0xc6d569be, (q31_t)0x5cbb348d, (q31_t)0xc6cfc472, + (q31_t)0x5caff965, (q31_t)0xc6ca215c, (q31_t)0x5ca4bd21, (q31_t)0xc6c4807a, + (q31_t)0x5c997fc4, (q31_t)0xc6bee1cd, (q31_t)0x5c8e414b, (q31_t)0xc6b94554, + (q31_t)0x5c8301b9, (q31_t)0xc6b3ab12, (q31_t)0x5c77c10e, (q31_t)0xc6ae1304, + (q31_t)0x5c6c7f4a, (q31_t)0xc6a87d2d, (q31_t)0x5c613c6d, (q31_t)0xc6a2e98b, + (q31_t)0x5c55f878, (q31_t)0xc69d5820, (q31_t)0x5c4ab36b, (q31_t)0xc697c8eb, + (q31_t)0x5c3f6d47, (q31_t)0xc6923bec, (q31_t)0x5c34260c, (q31_t)0xc68cb124, + (q31_t)0x5c28ddbb, (q31_t)0xc6872894, (q31_t)0x5c1d9454, (q31_t)0xc681a23a, + (q31_t)0x5c1249d8, (q31_t)0xc67c1e18, (q31_t)0x5c06fe46, (q31_t)0xc6769c2e, + (q31_t)0x5bfbb1a0, (q31_t)0xc6711c7b, (q31_t)0x5bf063e6, (q31_t)0xc66b9f01, + (q31_t)0x5be51518, (q31_t)0xc66623be, (q31_t)0x5bd9c537, (q31_t)0xc660aab5, + (q31_t)0x5bce7442, (q31_t)0xc65b33e4, (q31_t)0x5bc3223c, (q31_t)0xc655bf4c, + (q31_t)0x5bb7cf23, (q31_t)0xc6504ced, (q31_t)0x5bac7af9, (q31_t)0xc64adcc7, + (q31_t)0x5ba125bd, (q31_t)0xc6456edb, (q31_t)0x5b95cf71, (q31_t)0xc6400329, + (q31_t)0x5b8a7815, (q31_t)0xc63a99b1, (q31_t)0x5b7f1fa9, (q31_t)0xc6353273, + (q31_t)0x5b73c62d, (q31_t)0xc62fcd6f, (q31_t)0x5b686ba3, (q31_t)0xc62a6aa6, + (q31_t)0x5b5d100a, (q31_t)0xc6250a18, (q31_t)0x5b51b363, (q31_t)0xc61fabc4, + (q31_t)0x5b4655ae, (q31_t)0xc61a4fac, (q31_t)0x5b3af6ec, (q31_t)0xc614f5cf, + (q31_t)0x5b2f971e, (q31_t)0xc60f9e2e, (q31_t)0x5b243643, (q31_t)0xc60a48c9, + (q31_t)0x5b18d45c, (q31_t)0xc604f5a0, (q31_t)0x5b0d716a, (q31_t)0xc5ffa4b3, + (q31_t)0x5b020d6c, (q31_t)0xc5fa5603, (q31_t)0x5af6a865, (q31_t)0xc5f5098f, + (q31_t)0x5aeb4253, (q31_t)0xc5efbf58, (q31_t)0x5adfdb37, (q31_t)0xc5ea775e, + (q31_t)0x5ad47312, (q31_t)0xc5e531a1, (q31_t)0x5ac909e5, (q31_t)0xc5dfee22, + (q31_t)0x5abd9faf, (q31_t)0xc5daace1, (q31_t)0x5ab23471, (q31_t)0xc5d56ddd, + (q31_t)0x5aa6c82b, (q31_t)0xc5d03118, (q31_t)0x5a9b5adf, (q31_t)0xc5caf690, + (q31_t)0x5a8fec8c, (q31_t)0xc5c5be47, (q31_t)0x5a847d33, (q31_t)0xc5c0883d, + (q31_t)0x5a790cd4, (q31_t)0xc5bb5472, (q31_t)0x5a6d9b70, (q31_t)0xc5b622e6, + (q31_t)0x5a622907, (q31_t)0xc5b0f399, (q31_t)0x5a56b599, (q31_t)0xc5abc68c, + (q31_t)0x5a4b4128, (q31_t)0xc5a69bbe, (q31_t)0x5a3fcbb3, (q31_t)0xc5a17330, + (q31_t)0x5a34553b, (q31_t)0xc59c4ce3, (q31_t)0x5a28ddc0, (q31_t)0xc59728d5, + (q31_t)0x5a1d6544, (q31_t)0xc5920708, (q31_t)0x5a11ebc5, (q31_t)0xc58ce77c, + (q31_t)0x5a067145, (q31_t)0xc587ca31, (q31_t)0x59faf5c5, (q31_t)0xc582af26, + (q31_t)0x59ef7944, (q31_t)0xc57d965d, (q31_t)0x59e3fbc3, (q31_t)0xc5787fd6, + (q31_t)0x59d87d42, (q31_t)0xc5736b90, (q31_t)0x59ccfdc2, (q31_t)0xc56e598c, + (q31_t)0x59c17d44, (q31_t)0xc56949ca, (q31_t)0x59b5fbc8, (q31_t)0xc5643c4a, + (q31_t)0x59aa794d, (q31_t)0xc55f310d, (q31_t)0x599ef5d6, (q31_t)0xc55a2812, + (q31_t)0x59937161, (q31_t)0xc555215a, (q31_t)0x5987ebf0, (q31_t)0xc5501ce5, + (q31_t)0x597c6584, (q31_t)0xc54b1ab4, (q31_t)0x5970de1b, (q31_t)0xc5461ac6, + (q31_t)0x596555b8, (q31_t)0xc5411d1b, (q31_t)0x5959cc5a, (q31_t)0xc53c21b4, + (q31_t)0x594e4201, (q31_t)0xc5372891, (q31_t)0x5942b6af, (q31_t)0xc53231b3, + (q31_t)0x59372a64, (q31_t)0xc52d3d18, (q31_t)0x592b9d1f, (q31_t)0xc5284ac3, + (q31_t)0x59200ee3, (q31_t)0xc5235ab2, (q31_t)0x59147fae, (q31_t)0xc51e6ce6, + (q31_t)0x5908ef82, (q31_t)0xc519815f, (q31_t)0x58fd5e5f, (q31_t)0xc514981d, + (q31_t)0x58f1cc45, (q31_t)0xc50fb121, (q31_t)0x58e63935, (q31_t)0xc50acc6b, + (q31_t)0x58daa52f, (q31_t)0xc505e9fb, (q31_t)0x58cf1034, (q31_t)0xc50109d0, + (q31_t)0x58c37a44, (q31_t)0xc4fc2bec, (q31_t)0x58b7e35f, (q31_t)0xc4f7504e, + (q31_t)0x58ac4b87, (q31_t)0xc4f276f7, (q31_t)0x58a0b2bb, (q31_t)0xc4ed9fe7, + (q31_t)0x589518fc, (q31_t)0xc4e8cb1e, (q31_t)0x58897e4a, (q31_t)0xc4e3f89c, + (q31_t)0x587de2a7, (q31_t)0xc4df2862, (q31_t)0x58724611, (q31_t)0xc4da5a6f, + (q31_t)0x5866a88a, (q31_t)0xc4d58ec3, (q31_t)0x585b0a13, (q31_t)0xc4d0c560, + (q31_t)0x584f6aab, (q31_t)0xc4cbfe45, (q31_t)0x5843ca53, (q31_t)0xc4c73972, + (q31_t)0x5838290c, (q31_t)0xc4c276e8, (q31_t)0x582c86d5, (q31_t)0xc4bdb6a6, + (q31_t)0x5820e3b0, (q31_t)0xc4b8f8ad, (q31_t)0x58153f9d, (q31_t)0xc4b43cfd, + (q31_t)0x58099a9c, (q31_t)0xc4af8397, (q31_t)0x57fdf4ae, (q31_t)0xc4aacc7a, + (q31_t)0x57f24dd3, (q31_t)0xc4a617a6, (q31_t)0x57e6a60c, (q31_t)0xc4a1651c, + (q31_t)0x57dafd59, (q31_t)0xc49cb4dd, (q31_t)0x57cf53bb, (q31_t)0xc49806e7, + (q31_t)0x57c3a931, (q31_t)0xc4935b3c, (q31_t)0x57b7fdbd, (q31_t)0xc48eb1db, + (q31_t)0x57ac515f, (q31_t)0xc48a0ac4, (q31_t)0x57a0a417, (q31_t)0xc48565f9, + (q31_t)0x5794f5e6, (q31_t)0xc480c379, (q31_t)0x578946cc, (q31_t)0xc47c2344, + (q31_t)0x577d96ca, (q31_t)0xc477855a, (q31_t)0x5771e5e0, (q31_t)0xc472e9bc, + (q31_t)0x5766340f, (q31_t)0xc46e5069, (q31_t)0x575a8157, (q31_t)0xc469b963, + (q31_t)0x574ecdb8, (q31_t)0xc46524a9, (q31_t)0x57431933, (q31_t)0xc460923b, + (q31_t)0x573763c9, (q31_t)0xc45c0219, (q31_t)0x572bad7a, (q31_t)0xc4577444, + (q31_t)0x571ff646, (q31_t)0xc452e8bc, (q31_t)0x57143e2d, (q31_t)0xc44e5f80, + (q31_t)0x57088531, (q31_t)0xc449d892, (q31_t)0x56fccb51, (q31_t)0xc44553f2, + (q31_t)0x56f1108f, (q31_t)0xc440d19e, (q31_t)0x56e554ea, (q31_t)0xc43c5199, + (q31_t)0x56d99864, (q31_t)0xc437d3e1, (q31_t)0x56cddafb, (q31_t)0xc4335877, + (q31_t)0x56c21cb2, (q31_t)0xc42edf5c, (q31_t)0x56b65d88, (q31_t)0xc42a688f, + (q31_t)0x56aa9d7e, (q31_t)0xc425f410, (q31_t)0x569edc94, (q31_t)0xc42181e0, + (q31_t)0x56931acb, (q31_t)0xc41d11ff, (q31_t)0x56875823, (q31_t)0xc418a46d, + (q31_t)0x567b949d, (q31_t)0xc414392b, (q31_t)0x566fd039, (q31_t)0xc40fd037, + (q31_t)0x56640af7, (q31_t)0xc40b6994, (q31_t)0x565844d8, (q31_t)0xc4070540, + (q31_t)0x564c7ddd, (q31_t)0xc402a33c, (q31_t)0x5640b606, (q31_t)0xc3fe4388, + (q31_t)0x5634ed53, (q31_t)0xc3f9e624, (q31_t)0x562923c5, (q31_t)0xc3f58b10, + (q31_t)0x561d595d, (q31_t)0xc3f1324e, (q31_t)0x56118e1a, (q31_t)0xc3ecdbdc, + (q31_t)0x5605c1fd, (q31_t)0xc3e887bb, (q31_t)0x55f9f507, (q31_t)0xc3e435ea, + (q31_t)0x55ee2738, (q31_t)0xc3dfe66c, (q31_t)0x55e25890, (q31_t)0xc3db993e, + (q31_t)0x55d68911, (q31_t)0xc3d74e62, (q31_t)0x55cab8ba, (q31_t)0xc3d305d8, + (q31_t)0x55bee78c, (q31_t)0xc3cebfa0, (q31_t)0x55b31587, (q31_t)0xc3ca7bba, + (q31_t)0x55a742ac, (q31_t)0xc3c63a26, (q31_t)0x559b6efb, (q31_t)0xc3c1fae5, + (q31_t)0x558f9a76, (q31_t)0xc3bdbdf6, (q31_t)0x5583c51b, (q31_t)0xc3b9835a, + (q31_t)0x5577eeec, (q31_t)0xc3b54b11, (q31_t)0x556c17e9, (q31_t)0xc3b1151b, + (q31_t)0x55604013, (q31_t)0xc3ace178, (q31_t)0x5554676a, (q31_t)0xc3a8b028, + (q31_t)0x55488dee, (q31_t)0xc3a4812c, (q31_t)0x553cb3a0, (q31_t)0xc3a05484, + (q31_t)0x5530d881, (q31_t)0xc39c2a2f, (q31_t)0x5524fc90, (q31_t)0xc398022f, + (q31_t)0x55191fcf, (q31_t)0xc393dc82, (q31_t)0x550d423d, (q31_t)0xc38fb92a, + (q31_t)0x550163dc, (q31_t)0xc38b9827, (q31_t)0x54f584ac, (q31_t)0xc3877978, + (q31_t)0x54e9a4ac, (q31_t)0xc3835d1e, (q31_t)0x54ddc3de, (q31_t)0xc37f4319, + (q31_t)0x54d1e242, (q31_t)0xc37b2b6a, (q31_t)0x54c5ffd9, (q31_t)0xc377160f, + (q31_t)0x54ba1ca3, (q31_t)0xc373030a, (q31_t)0x54ae38a0, (q31_t)0xc36ef25b, + (q31_t)0x54a253d1, (q31_t)0xc36ae401, (q31_t)0x54966e36, (q31_t)0xc366d7fd, + (q31_t)0x548a87d1, (q31_t)0xc362ce50, (q31_t)0x547ea0a0, (q31_t)0xc35ec6f8, + (q31_t)0x5472b8a5, (q31_t)0xc35ac1f7, (q31_t)0x5466cfe1, (q31_t)0xc356bf4d, + (q31_t)0x545ae653, (q31_t)0xc352bef9, (q31_t)0x544efbfc, (q31_t)0xc34ec0fc, + (q31_t)0x544310dd, (q31_t)0xc34ac556, (q31_t)0x543724f5, (q31_t)0xc346cc07, + (q31_t)0x542b3846, (q31_t)0xc342d510, (q31_t)0x541f4ad1, (q31_t)0xc33ee070, + (q31_t)0x54135c94, (q31_t)0xc33aee27, (q31_t)0x54076d91, (q31_t)0xc336fe37, + (q31_t)0x53fb7dc9, (q31_t)0xc333109e, (q31_t)0x53ef8d3c, (q31_t)0xc32f255e, + (q31_t)0x53e39be9, (q31_t)0xc32b3c75, (q31_t)0x53d7a9d3, (q31_t)0xc32755e5, + (q31_t)0x53cbb6f8, (q31_t)0xc32371ae, (q31_t)0x53bfc35b, (q31_t)0xc31f8fcf, + (q31_t)0x53b3cefa, (q31_t)0xc31bb049, (q31_t)0x53a7d9d7, (q31_t)0xc317d31c, + (q31_t)0x539be3f2, (q31_t)0xc313f848, (q31_t)0x538fed4b, (q31_t)0xc3101fce, + (q31_t)0x5383f5e3, (q31_t)0xc30c49ad, (q31_t)0x5377fdbb, (q31_t)0xc30875e5, + (q31_t)0x536c04d2, (q31_t)0xc304a477, (q31_t)0x53600b2a, (q31_t)0xc300d563, + (q31_t)0x535410c3, (q31_t)0xc2fd08a9, (q31_t)0x5348159d, (q31_t)0xc2f93e4a, + (q31_t)0x533c19b8, (q31_t)0xc2f57644, (q31_t)0x53301d16, (q31_t)0xc2f1b099, + (q31_t)0x53241fb6, (q31_t)0xc2eded49, (q31_t)0x5318219a, (q31_t)0xc2ea2c53, + (q31_t)0x530c22c1, (q31_t)0xc2e66db8, (q31_t)0x5300232c, (q31_t)0xc2e2b178, + (q31_t)0x52f422db, (q31_t)0xc2def794, (q31_t)0x52e821cf, (q31_t)0xc2db400a, + (q31_t)0x52dc2009, (q31_t)0xc2d78add, (q31_t)0x52d01d89, (q31_t)0xc2d3d80a, + (q31_t)0x52c41a4f, (q31_t)0xc2d02794, (q31_t)0x52b8165b, (q31_t)0xc2cc7979, + (q31_t)0x52ac11af, (q31_t)0xc2c8cdbb, (q31_t)0x52a00c4b, (q31_t)0xc2c52459, + (q31_t)0x5294062f, (q31_t)0xc2c17d52, (q31_t)0x5287ff5b, (q31_t)0xc2bdd8a9, + (q31_t)0x527bf7d1, (q31_t)0xc2ba365c, (q31_t)0x526fef90, (q31_t)0xc2b6966c, + (q31_t)0x5263e699, (q31_t)0xc2b2f8d8, (q31_t)0x5257dced, (q31_t)0xc2af5da2, + (q31_t)0x524bd28c, (q31_t)0xc2abc4c9, (q31_t)0x523fc776, (q31_t)0xc2a82e4d, + (q31_t)0x5233bbac, (q31_t)0xc2a49a2e, (q31_t)0x5227af2e, (q31_t)0xc2a1086d, + (q31_t)0x521ba1fd, (q31_t)0xc29d790a, (q31_t)0x520f941a, (q31_t)0xc299ec05, + (q31_t)0x52038584, (q31_t)0xc296615d, (q31_t)0x51f7763c, (q31_t)0xc292d914, + (q31_t)0x51eb6643, (q31_t)0xc28f5329, (q31_t)0x51df5599, (q31_t)0xc28bcf9c, + (q31_t)0x51d3443f, (q31_t)0xc2884e6e, (q31_t)0x51c73235, (q31_t)0xc284cf9f, + (q31_t)0x51bb1f7c, (q31_t)0xc281532e, (q31_t)0x51af0c13, (q31_t)0xc27dd91c, + (q31_t)0x51a2f7fc, (q31_t)0xc27a616a, (q31_t)0x5196e337, (q31_t)0xc276ec16, + (q31_t)0x518acdc4, (q31_t)0xc2737922, (q31_t)0x517eb7a4, (q31_t)0xc270088e, + (q31_t)0x5172a0d7, (q31_t)0xc26c9a58, (q31_t)0x5166895f, (q31_t)0xc2692e83, + (q31_t)0x515a713a, (q31_t)0xc265c50e, (q31_t)0x514e586a, (q31_t)0xc2625df8, + (q31_t)0x51423ef0, (q31_t)0xc25ef943, (q31_t)0x513624cb, (q31_t)0xc25b96ee, + (q31_t)0x512a09fc, (q31_t)0xc25836f9, (q31_t)0x511dee84, (q31_t)0xc254d965, + (q31_t)0x5111d263, (q31_t)0xc2517e31, (q31_t)0x5105b599, (q31_t)0xc24e255e, + (q31_t)0x50f99827, (q31_t)0xc24aceed, (q31_t)0x50ed7a0e, (q31_t)0xc2477adc, + (q31_t)0x50e15b4e, (q31_t)0xc244292c, (q31_t)0x50d53be7, (q31_t)0xc240d9de, + (q31_t)0x50c91bda, (q31_t)0xc23d8cf1, (q31_t)0x50bcfb28, (q31_t)0xc23a4265, + (q31_t)0x50b0d9d0, (q31_t)0xc236fa3b, (q31_t)0x50a4b7d3, (q31_t)0xc233b473, + (q31_t)0x50989532, (q31_t)0xc230710d, (q31_t)0x508c71ee, (q31_t)0xc22d3009, + (q31_t)0x50804e06, (q31_t)0xc229f167, (q31_t)0x5074297b, (q31_t)0xc226b528, + (q31_t)0x5068044e, (q31_t)0xc2237b4b, (q31_t)0x505bde7f, (q31_t)0xc22043d0, + (q31_t)0x504fb80e, (q31_t)0xc21d0eb8, (q31_t)0x504390fd, (q31_t)0xc219dc03, + (q31_t)0x5037694b, (q31_t)0xc216abb1, (q31_t)0x502b40f8, (q31_t)0xc2137dc2, + (q31_t)0x501f1807, (q31_t)0xc2105236, (q31_t)0x5012ee76, (q31_t)0xc20d290d, + (q31_t)0x5006c446, (q31_t)0xc20a0248, (q31_t)0x4ffa9979, (q31_t)0xc206dde6, + (q31_t)0x4fee6e0d, (q31_t)0xc203bbe8, (q31_t)0x4fe24205, (q31_t)0xc2009c4e, + (q31_t)0x4fd6155f, (q31_t)0xc1fd7f17, (q31_t)0x4fc9e81e, (q31_t)0xc1fa6445, + (q31_t)0x4fbdba40, (q31_t)0xc1f74bd6, (q31_t)0x4fb18bc8, (q31_t)0xc1f435cc, + (q31_t)0x4fa55cb4, (q31_t)0xc1f12227, (q31_t)0x4f992d06, (q31_t)0xc1ee10e5, + (q31_t)0x4f8cfcbe, (q31_t)0xc1eb0209, (q31_t)0x4f80cbdc, (q31_t)0xc1e7f591, + (q31_t)0x4f749a61, (q31_t)0xc1e4eb7e, (q31_t)0x4f68684e, (q31_t)0xc1e1e3d0, + (q31_t)0x4f5c35a3, (q31_t)0xc1dede87, (q31_t)0x4f500260, (q31_t)0xc1dbdba3, + (q31_t)0x4f43ce86, (q31_t)0xc1d8db25, (q31_t)0x4f379a16, (q31_t)0xc1d5dd0c, + (q31_t)0x4f2b650f, (q31_t)0xc1d2e158, (q31_t)0x4f1f2f73, (q31_t)0xc1cfe80a, + (q31_t)0x4f12f941, (q31_t)0xc1ccf122, (q31_t)0x4f06c27a, (q31_t)0xc1c9fca0, + (q31_t)0x4efa8b20, (q31_t)0xc1c70a84, (q31_t)0x4eee5331, (q31_t)0xc1c41ace, + (q31_t)0x4ee21aaf, (q31_t)0xc1c12d7e, (q31_t)0x4ed5e19a, (q31_t)0xc1be4294, + (q31_t)0x4ec9a7f3, (q31_t)0xc1bb5a11, (q31_t)0x4ebd6db9, (q31_t)0xc1b873f5, + (q31_t)0x4eb132ef, (q31_t)0xc1b5903f, (q31_t)0x4ea4f793, (q31_t)0xc1b2aef0, + (q31_t)0x4e98bba7, (q31_t)0xc1afd007, (q31_t)0x4e8c7f2a, (q31_t)0xc1acf386, + (q31_t)0x4e80421e, (q31_t)0xc1aa196c, (q31_t)0x4e740483, (q31_t)0xc1a741b9, + (q31_t)0x4e67c65a, (q31_t)0xc1a46c6e, (q31_t)0x4e5b87a2, (q31_t)0xc1a1998a, + (q31_t)0x4e4f485c, (q31_t)0xc19ec90d, (q31_t)0x4e430889, (q31_t)0xc19bfaf9, + (q31_t)0x4e36c82a, (q31_t)0xc1992f4c, (q31_t)0x4e2a873e, (q31_t)0xc1966606, + (q31_t)0x4e1e45c6, (q31_t)0xc1939f29, (q31_t)0x4e1203c3, (q31_t)0xc190dab4, + (q31_t)0x4e05c135, (q31_t)0xc18e18a7, (q31_t)0x4df97e1d, (q31_t)0xc18b5903, + (q31_t)0x4ded3a7b, (q31_t)0xc1889bc6, (q31_t)0x4de0f64f, (q31_t)0xc185e0f3, + (q31_t)0x4dd4b19a, (q31_t)0xc1832888, (q31_t)0x4dc86c5d, (q31_t)0xc1807285, + (q31_t)0x4dbc2698, (q31_t)0xc17dbeec, (q31_t)0x4dafe04b, (q31_t)0xc17b0dbb, + (q31_t)0x4da39978, (q31_t)0xc1785ef4, (q31_t)0x4d97521d, (q31_t)0xc175b296, + (q31_t)0x4d8b0a3d, (q31_t)0xc17308a1, (q31_t)0x4d7ec1d6, (q31_t)0xc1706115, + (q31_t)0x4d7278eb, (q31_t)0xc16dbbf3, (q31_t)0x4d662f7b, (q31_t)0xc16b193a, + (q31_t)0x4d59e586, (q31_t)0xc16878eb, (q31_t)0x4d4d9b0e, (q31_t)0xc165db05, + (q31_t)0x4d415013, (q31_t)0xc1633f8a, (q31_t)0x4d350495, (q31_t)0xc160a678, + (q31_t)0x4d28b894, (q31_t)0xc15e0fd1, (q31_t)0x4d1c6c11, (q31_t)0xc15b7b94, + (q31_t)0x4d101f0e, (q31_t)0xc158e9c1, (q31_t)0x4d03d189, (q31_t)0xc1565a58, + (q31_t)0x4cf78383, (q31_t)0xc153cd5a, (q31_t)0x4ceb34fe, (q31_t)0xc15142c6, + (q31_t)0x4cdee5f9, (q31_t)0xc14eba9d, (q31_t)0x4cd29676, (q31_t)0xc14c34df, + (q31_t)0x4cc64673, (q31_t)0xc149b18b, (q31_t)0x4cb9f5f3, (q31_t)0xc14730a3, + (q31_t)0x4cada4f5, (q31_t)0xc144b225, (q31_t)0x4ca1537a, (q31_t)0xc1423613, + (q31_t)0x4c950182, (q31_t)0xc13fbc6c, (q31_t)0x4c88af0e, (q31_t)0xc13d4530, + (q31_t)0x4c7c5c1e, (q31_t)0xc13ad060, (q31_t)0x4c7008b3, (q31_t)0xc1385dfb, + (q31_t)0x4c63b4ce, (q31_t)0xc135ee02, (q31_t)0x4c57606e, (q31_t)0xc1338075, + (q31_t)0x4c4b0b94, (q31_t)0xc1311553, (q31_t)0x4c3eb641, (q31_t)0xc12eac9d, + (q31_t)0x4c326075, (q31_t)0xc12c4653, (q31_t)0x4c260a31, (q31_t)0xc129e276, + (q31_t)0x4c19b374, (q31_t)0xc1278104, (q31_t)0x4c0d5c41, (q31_t)0xc12521ff, + (q31_t)0x4c010496, (q31_t)0xc122c566, (q31_t)0x4bf4ac75, (q31_t)0xc1206b39, + (q31_t)0x4be853de, (q31_t)0xc11e1379, (q31_t)0x4bdbfad1, (q31_t)0xc11bbe26, + (q31_t)0x4bcfa150, (q31_t)0xc1196b3f, (q31_t)0x4bc34759, (q31_t)0xc1171ac6, + (q31_t)0x4bb6ecef, (q31_t)0xc114ccb9, (q31_t)0x4baa9211, (q31_t)0xc1128119, + (q31_t)0x4b9e36c0, (q31_t)0xc11037e6, (q31_t)0x4b91dafc, (q31_t)0xc10df120, + (q31_t)0x4b857ec7, (q31_t)0xc10bacc8, (q31_t)0x4b79221f, (q31_t)0xc1096add, + (q31_t)0x4b6cc506, (q31_t)0xc1072b5f, (q31_t)0x4b60677c, (q31_t)0xc104ee4f, + (q31_t)0x4b540982, (q31_t)0xc102b3ac, (q31_t)0x4b47ab19, (q31_t)0xc1007b77, + (q31_t)0x4b3b4c40, (q31_t)0xc0fe45b0, (q31_t)0x4b2eecf8, (q31_t)0xc0fc1257, + (q31_t)0x4b228d42, (q31_t)0xc0f9e16b, (q31_t)0x4b162d1d, (q31_t)0xc0f7b2ee, + (q31_t)0x4b09cc8c, (q31_t)0xc0f586df, (q31_t)0x4afd6b8d, (q31_t)0xc0f35d3e, + (q31_t)0x4af10a22, (q31_t)0xc0f1360b, (q31_t)0x4ae4a84b, (q31_t)0xc0ef1147, + (q31_t)0x4ad84609, (q31_t)0xc0eceef1, (q31_t)0x4acbe35b, (q31_t)0xc0eacf09, + (q31_t)0x4abf8043, (q31_t)0xc0e8b190, (q31_t)0x4ab31cc1, (q31_t)0xc0e69686, + (q31_t)0x4aa6b8d5, (q31_t)0xc0e47deb, (q31_t)0x4a9a5480, (q31_t)0xc0e267be, + (q31_t)0x4a8defc3, (q31_t)0xc0e05401, (q31_t)0x4a818a9d, (q31_t)0xc0de42b2, + (q31_t)0x4a752510, (q31_t)0xc0dc33d2, (q31_t)0x4a68bf1b, (q31_t)0xc0da2762, + (q31_t)0x4a5c58c0, (q31_t)0xc0d81d61, (q31_t)0x4a4ff1fe, (q31_t)0xc0d615cf, + (q31_t)0x4a438ad7, (q31_t)0xc0d410ad, (q31_t)0x4a37234a, (q31_t)0xc0d20dfa, + (q31_t)0x4a2abb59, (q31_t)0xc0d00db6, (q31_t)0x4a1e5303, (q31_t)0xc0ce0fe3, + (q31_t)0x4a11ea49, (q31_t)0xc0cc147f, (q31_t)0x4a05812c, (q31_t)0xc0ca1b8a, + (q31_t)0x49f917ac, (q31_t)0xc0c82506, (q31_t)0x49ecadc9, (q31_t)0xc0c630f2, + (q31_t)0x49e04385, (q31_t)0xc0c43f4d, (q31_t)0x49d3d8df, (q31_t)0xc0c25019, + (q31_t)0x49c76dd8, (q31_t)0xc0c06355, (q31_t)0x49bb0271, (q31_t)0xc0be7901, + (q31_t)0x49ae96aa, (q31_t)0xc0bc911d, (q31_t)0x49a22a83, (q31_t)0xc0baabaa, + (q31_t)0x4995bdfd, (q31_t)0xc0b8c8a7, (q31_t)0x49895118, (q31_t)0xc0b6e815, + (q31_t)0x497ce3d5, (q31_t)0xc0b509f3, (q31_t)0x49707635, (q31_t)0xc0b32e42, + (q31_t)0x49640837, (q31_t)0xc0b15502, (q31_t)0x495799dd, (q31_t)0xc0af7e33, + (q31_t)0x494b2b27, (q31_t)0xc0ada9d4, (q31_t)0x493ebc14, (q31_t)0xc0abd7e6, + (q31_t)0x49324ca7, (q31_t)0xc0aa086a, (q31_t)0x4925dcdf, (q31_t)0xc0a83b5e, + (q31_t)0x49196cbc, (q31_t)0xc0a670c4, (q31_t)0x490cfc40, (q31_t)0xc0a4a89b, + (q31_t)0x49008b6a, (q31_t)0xc0a2e2e3, (q31_t)0x48f41a3c, (q31_t)0xc0a11f9d, + (q31_t)0x48e7a8b5, (q31_t)0xc09f5ec8, (q31_t)0x48db36d6, (q31_t)0xc09da065, + (q31_t)0x48cec4a0, (q31_t)0xc09be473, (q31_t)0x48c25213, (q31_t)0xc09a2af3, + (q31_t)0x48b5df30, (q31_t)0xc09873e4, (q31_t)0x48a96bf6, (q31_t)0xc096bf48, + (q31_t)0x489cf867, (q31_t)0xc0950d1d, (q31_t)0x48908483, (q31_t)0xc0935d64, + (q31_t)0x4884104b, (q31_t)0xc091b01d, (q31_t)0x48779bbe, (q31_t)0xc0900548, + (q31_t)0x486b26de, (q31_t)0xc08e5ce5, (q31_t)0x485eb1ab, (q31_t)0xc08cb6f5, + (q31_t)0x48523c25, (q31_t)0xc08b1376, (q31_t)0x4845c64d, (q31_t)0xc089726a, + (q31_t)0x48395024, (q31_t)0xc087d3d0, (q31_t)0x482cd9a9, (q31_t)0xc08637a9, + (q31_t)0x482062de, (q31_t)0xc0849df4, (q31_t)0x4813ebc2, (q31_t)0xc08306b2, + (q31_t)0x48077457, (q31_t)0xc08171e2, (q31_t)0x47fafc9c, (q31_t)0xc07fdf85, + (q31_t)0x47ee8493, (q31_t)0xc07e4f9b, (q31_t)0x47e20c3b, (q31_t)0xc07cc223, + (q31_t)0x47d59396, (q31_t)0xc07b371e, (q31_t)0x47c91aa3, (q31_t)0xc079ae8c, + (q31_t)0x47bca163, (q31_t)0xc078286e, (q31_t)0x47b027d7, (q31_t)0xc076a4c2, + (q31_t)0x47a3adff, (q31_t)0xc0752389, (q31_t)0x479733dc, (q31_t)0xc073a4c3, + (q31_t)0x478ab96e, (q31_t)0xc0722871, (q31_t)0x477e3eb5, (q31_t)0xc070ae92, + (q31_t)0x4771c3b3, (q31_t)0xc06f3726, (q31_t)0x47654867, (q31_t)0xc06dc22e, + (q31_t)0x4758ccd2, (q31_t)0xc06c4fa8, (q31_t)0x474c50f4, (q31_t)0xc06adf97, + (q31_t)0x473fd4cf, (q31_t)0xc06971f9, (q31_t)0x47335862, (q31_t)0xc06806ce, + (q31_t)0x4726dbae, (q31_t)0xc0669e18, (q31_t)0x471a5eb3, (q31_t)0xc06537d4, + (q31_t)0x470de172, (q31_t)0xc063d405, (q31_t)0x470163eb, (q31_t)0xc06272aa, + (q31_t)0x46f4e620, (q31_t)0xc06113c2, (q31_t)0x46e86810, (q31_t)0xc05fb74e, + (q31_t)0x46dbe9bb, (q31_t)0xc05e5d4e, (q31_t)0x46cf6b23, (q31_t)0xc05d05c3, + (q31_t)0x46c2ec48, (q31_t)0xc05bb0ab, (q31_t)0x46b66d29, (q31_t)0xc05a5e07, + (q31_t)0x46a9edc9, (q31_t)0xc0590dd8, (q31_t)0x469d6e27, (q31_t)0xc057c01d, + (q31_t)0x4690ee44, (q31_t)0xc05674d6, (q31_t)0x46846e1f, (q31_t)0xc0552c03, + (q31_t)0x4677edbb, (q31_t)0xc053e5a5, (q31_t)0x466b6d16, (q31_t)0xc052a1bb, + (q31_t)0x465eec33, (q31_t)0xc0516045, (q31_t)0x46526b10, (q31_t)0xc0502145, + (q31_t)0x4645e9af, (q31_t)0xc04ee4b8, (q31_t)0x46396810, (q31_t)0xc04daaa1, + (q31_t)0x462ce634, (q31_t)0xc04c72fe, (q31_t)0x4620641a, (q31_t)0xc04b3dcf, + (q31_t)0x4613e1c5, (q31_t)0xc04a0b16, (q31_t)0x46075f33, (q31_t)0xc048dad1, + (q31_t)0x45fadc66, (q31_t)0xc047ad01, (q31_t)0x45ee595d, (q31_t)0xc04681a6, + (q31_t)0x45e1d61b, (q31_t)0xc04558c0, (q31_t)0x45d5529e, (q31_t)0xc044324f, + (q31_t)0x45c8cee7, (q31_t)0xc0430e53, (q31_t)0x45bc4af8, (q31_t)0xc041eccc, + (q31_t)0x45afc6d0, (q31_t)0xc040cdba, (q31_t)0x45a3426f, (q31_t)0xc03fb11d, + (q31_t)0x4596bdd7, (q31_t)0xc03e96f6, (q31_t)0x458a3908, (q31_t)0xc03d7f44, + (q31_t)0x457db403, (q31_t)0xc03c6a07, (q31_t)0x45712ec7, (q31_t)0xc03b573f, + (q31_t)0x4564a955, (q31_t)0xc03a46ed, (q31_t)0x455823ae, (q31_t)0xc0393910, + (q31_t)0x454b9dd3, (q31_t)0xc0382da8, (q31_t)0x453f17c3, (q31_t)0xc03724b6, + (q31_t)0x4532917f, (q31_t)0xc0361e3a, (q31_t)0x45260b08, (q31_t)0xc0351a33, + (q31_t)0x4519845e, (q31_t)0xc03418a2, (q31_t)0x450cfd82, (q31_t)0xc0331986, + (q31_t)0x45007674, (q31_t)0xc0321ce0, (q31_t)0x44f3ef35, (q31_t)0xc03122b0, + (q31_t)0x44e767c5, (q31_t)0xc0302af5, (q31_t)0x44dae024, (q31_t)0xc02f35b1, + (q31_t)0x44ce5854, (q31_t)0xc02e42e2, (q31_t)0x44c1d054, (q31_t)0xc02d5289, + (q31_t)0x44b54825, (q31_t)0xc02c64a6, (q31_t)0x44a8bfc7, (q31_t)0xc02b7939, + (q31_t)0x449c373c, (q31_t)0xc02a9042, (q31_t)0x448fae83, (q31_t)0xc029a9c1, + (q31_t)0x4483259d, (q31_t)0xc028c5b6, (q31_t)0x44769c8b, (q31_t)0xc027e421, + (q31_t)0x446a134c, (q31_t)0xc0270502, (q31_t)0x445d89e2, (q31_t)0xc0262859, + (q31_t)0x4451004d, (q31_t)0xc0254e27, (q31_t)0x4444768d, (q31_t)0xc024766a, + (q31_t)0x4437eca4, (q31_t)0xc023a124, (q31_t)0x442b6290, (q31_t)0xc022ce54, + (q31_t)0x441ed854, (q31_t)0xc021fdfb, (q31_t)0x44124dee, (q31_t)0xc0213018, + (q31_t)0x4405c361, (q31_t)0xc02064ab, (q31_t)0x43f938ac, (q31_t)0xc01f9bb5, + (q31_t)0x43ecadcf, (q31_t)0xc01ed535, (q31_t)0x43e022cc, (q31_t)0xc01e112b, + (q31_t)0x43d397a3, (q31_t)0xc01d4f99, (q31_t)0x43c70c54, (q31_t)0xc01c907c, + (q31_t)0x43ba80df, (q31_t)0xc01bd3d6, (q31_t)0x43adf546, (q31_t)0xc01b19a7, + (q31_t)0x43a16988, (q31_t)0xc01a61ee, (q31_t)0x4394dda7, (q31_t)0xc019acac, + (q31_t)0x438851a2, (q31_t)0xc018f9e1, (q31_t)0x437bc57b, (q31_t)0xc018498c, + (q31_t)0x436f3931, (q31_t)0xc0179bae, (q31_t)0x4362acc5, (q31_t)0xc016f047, + (q31_t)0x43562038, (q31_t)0xc0164757, (q31_t)0x43499389, (q31_t)0xc015a0dd, + (q31_t)0x433d06bb, (q31_t)0xc014fcda, (q31_t)0x433079cc, (q31_t)0xc0145b4e, + (q31_t)0x4323ecbe, (q31_t)0xc013bc39, (q31_t)0x43175f91, (q31_t)0xc0131f9b, + (q31_t)0x430ad245, (q31_t)0xc0128574, (q31_t)0x42fe44dc, (q31_t)0xc011edc3, + (q31_t)0x42f1b755, (q31_t)0xc011588a, (q31_t)0x42e529b0, (q31_t)0xc010c5c7, + (q31_t)0x42d89bf0, (q31_t)0xc010357c, (q31_t)0x42cc0e13, (q31_t)0xc00fa7a8, + (q31_t)0x42bf801a, (q31_t)0xc00f1c4a, (q31_t)0x42b2f207, (q31_t)0xc00e9364, + (q31_t)0x42a663d8, (q31_t)0xc00e0cf5, (q31_t)0x4299d590, (q31_t)0xc00d88fd, + (q31_t)0x428d472e, (q31_t)0xc00d077c, (q31_t)0x4280b8b3, (q31_t)0xc00c8872, + (q31_t)0x42742a1f, (q31_t)0xc00c0be0, (q31_t)0x42679b73, (q31_t)0xc00b91c4, + (q31_t)0x425b0caf, (q31_t)0xc00b1a20, (q31_t)0x424e7dd4, (q31_t)0xc00aa4f3, + (q31_t)0x4241eee2, (q31_t)0xc00a323d, (q31_t)0x42355fd9, (q31_t)0xc009c1ff, + (q31_t)0x4228d0bb, (q31_t)0xc0095438, (q31_t)0x421c4188, (q31_t)0xc008e8e8, + (q31_t)0x420fb240, (q31_t)0xc008800f, (q31_t)0x420322e3, (q31_t)0xc00819ae, + (q31_t)0x41f69373, (q31_t)0xc007b5c4, (q31_t)0x41ea03ef, (q31_t)0xc0075452, + (q31_t)0x41dd7459, (q31_t)0xc006f556, (q31_t)0x41d0e4b0, (q31_t)0xc00698d3, + (q31_t)0x41c454f5, (q31_t)0xc0063ec6, (q31_t)0x41b7c528, (q31_t)0xc005e731, + (q31_t)0x41ab354b, (q31_t)0xc0059214, (q31_t)0x419ea55d, (q31_t)0xc0053f6e, + (q31_t)0x4192155f, (q31_t)0xc004ef3f, (q31_t)0x41858552, (q31_t)0xc004a188, + (q31_t)0x4178f536, (q31_t)0xc0045648, (q31_t)0x416c650b, (q31_t)0xc0040d80, + (q31_t)0x415fd4d2, (q31_t)0xc003c72f, (q31_t)0x4153448c, (q31_t)0xc0038356, + (q31_t)0x4146b438, (q31_t)0xc00341f4, (q31_t)0x413a23d8, (q31_t)0xc003030a, + (q31_t)0x412d936c, (q31_t)0xc002c697, (q31_t)0x412102f4, (q31_t)0xc0028c9c, + (q31_t)0x41147271, (q31_t)0xc0025519, (q31_t)0x4107e1e3, (q31_t)0xc002200d, + (q31_t)0x40fb514b, (q31_t)0xc001ed78, (q31_t)0x40eec0aa, (q31_t)0xc001bd5c, + (q31_t)0x40e22fff, (q31_t)0xc0018fb6, (q31_t)0x40d59f4c, (q31_t)0xc0016489, + (q31_t)0x40c90e90, (q31_t)0xc0013bd3, (q31_t)0x40bc7dcc, (q31_t)0xc0011594, + (q31_t)0x40afed02, (q31_t)0xc000f1ce, (q31_t)0x40a35c30, (q31_t)0xc000d07e, + (q31_t)0x4096cb58, (q31_t)0xc000b1a7, (q31_t)0x408a3a7b, (q31_t)0xc0009547, + (q31_t)0x407da998, (q31_t)0xc0007b5f, (q31_t)0x407118b0, (q31_t)0xc00063ee, + (q31_t)0x406487c4, (q31_t)0xc0004ef5, (q31_t)0x4057f6d4, (q31_t)0xc0003c74, + (q31_t)0x404b65e1, (q31_t)0xc0002c6a, (q31_t)0x403ed4ea, (q31_t)0xc0001ed8, + (q31_t)0x403243f1, (q31_t)0xc00013bd, (q31_t)0x4025b2f7, (q31_t)0xc0000b1a, + (q31_t)0x401921fb, (q31_t)0xc00004ef, (q31_t)0x400c90fe, (q31_t)0xc000013c, +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15) +/** + @par + Generation fixed-point realCoefAQ15 array in Q15 format: + @par + n = 4096 +
for (i = 0; i < n; i++)
+  {
+     pATable[2 * i]     = 0.5 * ( 1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+     pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ @par + Convert to fixed point Q15 format + round(pATable[i] * pow(2, 15)) + */ +const q15_t __ALIGNED(4) realCoefAQ15[8192] = { + (q15_t)0x4000, (q15_t)0xc000, (q15_t)0x3ff3, (q15_t)0xc000, (q15_t)0x3fe7, (q15_t)0xc000, (q15_t)0x3fda, (q15_t)0xc000, + (q15_t)0x3fce, (q15_t)0xc000, (q15_t)0x3fc1, (q15_t)0xc000, (q15_t)0x3fb5, (q15_t)0xc000, (q15_t)0x3fa8, (q15_t)0xc000, + (q15_t)0x3f9b, (q15_t)0xc000, (q15_t)0x3f8f, (q15_t)0xc000, (q15_t)0x3f82, (q15_t)0xc000, (q15_t)0x3f76, (q15_t)0xc001, + (q15_t)0x3f69, (q15_t)0xc001, (q15_t)0x3f5d, (q15_t)0xc001, (q15_t)0x3f50, (q15_t)0xc001, (q15_t)0x3f44, (q15_t)0xc001, + (q15_t)0x3f37, (q15_t)0xc001, (q15_t)0x3f2a, (q15_t)0xc001, (q15_t)0x3f1e, (q15_t)0xc002, (q15_t)0x3f11, (q15_t)0xc002, + (q15_t)0x3f05, (q15_t)0xc002, (q15_t)0x3ef8, (q15_t)0xc002, (q15_t)0x3eec, (q15_t)0xc002, (q15_t)0x3edf, (q15_t)0xc003, + (q15_t)0x3ed2, (q15_t)0xc003, (q15_t)0x3ec6, (q15_t)0xc003, (q15_t)0x3eb9, (q15_t)0xc003, (q15_t)0x3ead, (q15_t)0xc004, + (q15_t)0x3ea0, (q15_t)0xc004, (q15_t)0x3e94, (q15_t)0xc004, (q15_t)0x3e87, (q15_t)0xc004, (q15_t)0x3e7a, (q15_t)0xc005, + (q15_t)0x3e6e, (q15_t)0xc005, (q15_t)0x3e61, (q15_t)0xc005, (q15_t)0x3e55, (q15_t)0xc006, (q15_t)0x3e48, (q15_t)0xc006, + (q15_t)0x3e3c, (q15_t)0xc006, (q15_t)0x3e2f, (q15_t)0xc007, (q15_t)0x3e23, (q15_t)0xc007, (q15_t)0x3e16, (q15_t)0xc007, + (q15_t)0x3e09, (q15_t)0xc008, (q15_t)0x3dfd, (q15_t)0xc008, (q15_t)0x3df0, (q15_t)0xc009, (q15_t)0x3de4, (q15_t)0xc009, + (q15_t)0x3dd7, (q15_t)0xc009, (q15_t)0x3dcb, (q15_t)0xc00a, (q15_t)0x3dbe, (q15_t)0xc00a, (q15_t)0x3db2, (q15_t)0xc00b, + (q15_t)0x3da5, (q15_t)0xc00b, (q15_t)0x3d98, (q15_t)0xc00c, (q15_t)0x3d8c, (q15_t)0xc00c, (q15_t)0x3d7f, (q15_t)0xc00d, + (q15_t)0x3d73, (q15_t)0xc00d, (q15_t)0x3d66, (q15_t)0xc00e, (q15_t)0x3d5a, (q15_t)0xc00e, (q15_t)0x3d4d, (q15_t)0xc00f, + (q15_t)0x3d40, (q15_t)0xc00f, (q15_t)0x3d34, (q15_t)0xc010, (q15_t)0x3d27, (q15_t)0xc010, (q15_t)0x3d1b, (q15_t)0xc011, + (q15_t)0x3d0e, (q15_t)0xc011, (q15_t)0x3d02, (q15_t)0xc012, (q15_t)0x3cf5, (q15_t)0xc013, (q15_t)0x3ce9, (q15_t)0xc013, + (q15_t)0x3cdc, (q15_t)0xc014, (q15_t)0x3cd0, (q15_t)0xc014, (q15_t)0x3cc3, (q15_t)0xc015, (q15_t)0x3cb6, (q15_t)0xc016, + (q15_t)0x3caa, (q15_t)0xc016, (q15_t)0x3c9d, (q15_t)0xc017, (q15_t)0x3c91, (q15_t)0xc018, (q15_t)0x3c84, (q15_t)0xc018, + (q15_t)0x3c78, (q15_t)0xc019, (q15_t)0x3c6b, (q15_t)0xc01a, (q15_t)0x3c5f, (q15_t)0xc01a, (q15_t)0x3c52, (q15_t)0xc01b, + (q15_t)0x3c45, (q15_t)0xc01c, (q15_t)0x3c39, (q15_t)0xc01d, (q15_t)0x3c2c, (q15_t)0xc01d, (q15_t)0x3c20, (q15_t)0xc01e, + (q15_t)0x3c13, (q15_t)0xc01f, (q15_t)0x3c07, (q15_t)0xc020, (q15_t)0x3bfa, (q15_t)0xc020, (q15_t)0x3bee, (q15_t)0xc021, + (q15_t)0x3be1, (q15_t)0xc022, (q15_t)0x3bd5, (q15_t)0xc023, (q15_t)0x3bc8, (q15_t)0xc024, (q15_t)0x3bbc, (q15_t)0xc024, + (q15_t)0x3baf, (q15_t)0xc025, (q15_t)0x3ba2, (q15_t)0xc026, (q15_t)0x3b96, (q15_t)0xc027, (q15_t)0x3b89, (q15_t)0xc028, + (q15_t)0x3b7d, (q15_t)0xc029, (q15_t)0x3b70, (q15_t)0xc02a, (q15_t)0x3b64, (q15_t)0xc02b, (q15_t)0x3b57, (q15_t)0xc02b, + (q15_t)0x3b4b, (q15_t)0xc02c, (q15_t)0x3b3e, (q15_t)0xc02d, (q15_t)0x3b32, (q15_t)0xc02e, (q15_t)0x3b25, (q15_t)0xc02f, + (q15_t)0x3b19, (q15_t)0xc030, (q15_t)0x3b0c, (q15_t)0xc031, (q15_t)0x3b00, (q15_t)0xc032, (q15_t)0x3af3, (q15_t)0xc033, + (q15_t)0x3ae6, (q15_t)0xc034, (q15_t)0x3ada, (q15_t)0xc035, (q15_t)0x3acd, (q15_t)0xc036, (q15_t)0x3ac1, (q15_t)0xc037, + (q15_t)0x3ab4, (q15_t)0xc038, (q15_t)0x3aa8, (q15_t)0xc039, (q15_t)0x3a9b, (q15_t)0xc03a, (q15_t)0x3a8f, (q15_t)0xc03b, + (q15_t)0x3a82, (q15_t)0xc03c, (q15_t)0x3a76, (q15_t)0xc03d, (q15_t)0x3a69, (q15_t)0xc03f, (q15_t)0x3a5d, (q15_t)0xc040, + (q15_t)0x3a50, (q15_t)0xc041, (q15_t)0x3a44, (q15_t)0xc042, (q15_t)0x3a37, (q15_t)0xc043, (q15_t)0x3a2b, (q15_t)0xc044, + (q15_t)0x3a1e, (q15_t)0xc045, (q15_t)0x3a12, (q15_t)0xc047, (q15_t)0x3a05, (q15_t)0xc048, (q15_t)0x39f9, (q15_t)0xc049, + (q15_t)0x39ec, (q15_t)0xc04a, (q15_t)0x39e0, (q15_t)0xc04b, (q15_t)0x39d3, (q15_t)0xc04c, (q15_t)0x39c7, (q15_t)0xc04e, + (q15_t)0x39ba, (q15_t)0xc04f, (q15_t)0x39ae, (q15_t)0xc050, (q15_t)0x39a1, (q15_t)0xc051, (q15_t)0x3995, (q15_t)0xc053, + (q15_t)0x3988, (q15_t)0xc054, (q15_t)0x397c, (q15_t)0xc055, (q15_t)0x396f, (q15_t)0xc056, (q15_t)0x3963, (q15_t)0xc058, + (q15_t)0x3956, (q15_t)0xc059, (q15_t)0x394a, (q15_t)0xc05a, (q15_t)0x393d, (q15_t)0xc05c, (q15_t)0x3931, (q15_t)0xc05d, + (q15_t)0x3924, (q15_t)0xc05e, (q15_t)0x3918, (q15_t)0xc060, (q15_t)0x390b, (q15_t)0xc061, (q15_t)0x38ff, (q15_t)0xc062, + (q15_t)0x38f2, (q15_t)0xc064, (q15_t)0x38e6, (q15_t)0xc065, (q15_t)0x38d9, (q15_t)0xc067, (q15_t)0x38cd, (q15_t)0xc068, + (q15_t)0x38c0, (q15_t)0xc069, (q15_t)0x38b4, (q15_t)0xc06b, (q15_t)0x38a7, (q15_t)0xc06c, (q15_t)0x389b, (q15_t)0xc06e, + (q15_t)0x388e, (q15_t)0xc06f, (q15_t)0x3882, (q15_t)0xc071, (q15_t)0x3875, (q15_t)0xc072, (q15_t)0x3869, (q15_t)0xc074, + (q15_t)0x385c, (q15_t)0xc075, (q15_t)0x3850, (q15_t)0xc077, (q15_t)0x3843, (q15_t)0xc078, (q15_t)0x3837, (q15_t)0xc07a, + (q15_t)0x382a, (q15_t)0xc07b, (q15_t)0x381e, (q15_t)0xc07d, (q15_t)0x3811, (q15_t)0xc07e, (q15_t)0x3805, (q15_t)0xc080, + (q15_t)0x37f9, (q15_t)0xc081, (q15_t)0x37ec, (q15_t)0xc083, (q15_t)0x37e0, (q15_t)0xc085, (q15_t)0x37d3, (q15_t)0xc086, + (q15_t)0x37c7, (q15_t)0xc088, (q15_t)0x37ba, (q15_t)0xc089, (q15_t)0x37ae, (q15_t)0xc08b, (q15_t)0x37a1, (q15_t)0xc08d, + (q15_t)0x3795, (q15_t)0xc08e, (q15_t)0x3788, (q15_t)0xc090, (q15_t)0x377c, (q15_t)0xc092, (q15_t)0x376f, (q15_t)0xc093, + (q15_t)0x3763, (q15_t)0xc095, (q15_t)0x3757, (q15_t)0xc097, (q15_t)0x374a, (q15_t)0xc098, (q15_t)0x373e, (q15_t)0xc09a, + (q15_t)0x3731, (q15_t)0xc09c, (q15_t)0x3725, (q15_t)0xc09e, (q15_t)0x3718, (q15_t)0xc09f, (q15_t)0x370c, (q15_t)0xc0a1, + (q15_t)0x36ff, (q15_t)0xc0a3, (q15_t)0x36f3, (q15_t)0xc0a5, (q15_t)0x36e7, (q15_t)0xc0a6, (q15_t)0x36da, (q15_t)0xc0a8, + (q15_t)0x36ce, (q15_t)0xc0aa, (q15_t)0x36c1, (q15_t)0xc0ac, (q15_t)0x36b5, (q15_t)0xc0ae, (q15_t)0x36a8, (q15_t)0xc0af, + (q15_t)0x369c, (q15_t)0xc0b1, (q15_t)0x3690, (q15_t)0xc0b3, (q15_t)0x3683, (q15_t)0xc0b5, (q15_t)0x3677, (q15_t)0xc0b7, + (q15_t)0x366a, (q15_t)0xc0b9, (q15_t)0x365e, (q15_t)0xc0bb, (q15_t)0x3651, (q15_t)0xc0bd, (q15_t)0x3645, (q15_t)0xc0be, + (q15_t)0x3639, (q15_t)0xc0c0, (q15_t)0x362c, (q15_t)0xc0c2, (q15_t)0x3620, (q15_t)0xc0c4, (q15_t)0x3613, (q15_t)0xc0c6, + (q15_t)0x3607, (q15_t)0xc0c8, (q15_t)0x35fa, (q15_t)0xc0ca, (q15_t)0x35ee, (q15_t)0xc0cc, (q15_t)0x35e2, (q15_t)0xc0ce, + (q15_t)0x35d5, (q15_t)0xc0d0, (q15_t)0x35c9, (q15_t)0xc0d2, (q15_t)0x35bc, (q15_t)0xc0d4, (q15_t)0x35b0, (q15_t)0xc0d6, + (q15_t)0x35a4, (q15_t)0xc0d8, (q15_t)0x3597, (q15_t)0xc0da, (q15_t)0x358b, (q15_t)0xc0dc, (q15_t)0x357e, (q15_t)0xc0de, + (q15_t)0x3572, (q15_t)0xc0e0, (q15_t)0x3566, (q15_t)0xc0e2, (q15_t)0x3559, (q15_t)0xc0e4, (q15_t)0x354d, (q15_t)0xc0e7, + (q15_t)0x3540, (q15_t)0xc0e9, (q15_t)0x3534, (q15_t)0xc0eb, (q15_t)0x3528, (q15_t)0xc0ed, (q15_t)0x351b, (q15_t)0xc0ef, + (q15_t)0x350f, (q15_t)0xc0f1, (q15_t)0x3503, (q15_t)0xc0f3, (q15_t)0x34f6, (q15_t)0xc0f6, (q15_t)0x34ea, (q15_t)0xc0f8, + (q15_t)0x34dd, (q15_t)0xc0fa, (q15_t)0x34d1, (q15_t)0xc0fc, (q15_t)0x34c5, (q15_t)0xc0fe, (q15_t)0x34b8, (q15_t)0xc100, + (q15_t)0x34ac, (q15_t)0xc103, (q15_t)0x34a0, (q15_t)0xc105, (q15_t)0x3493, (q15_t)0xc107, (q15_t)0x3487, (q15_t)0xc109, + (q15_t)0x347b, (q15_t)0xc10c, (q15_t)0x346e, (q15_t)0xc10e, (q15_t)0x3462, (q15_t)0xc110, (q15_t)0x3455, (q15_t)0xc113, + (q15_t)0x3449, (q15_t)0xc115, (q15_t)0x343d, (q15_t)0xc117, (q15_t)0x3430, (q15_t)0xc119, (q15_t)0x3424, (q15_t)0xc11c, + (q15_t)0x3418, (q15_t)0xc11e, (q15_t)0x340b, (q15_t)0xc120, (q15_t)0x33ff, (q15_t)0xc123, (q15_t)0x33f3, (q15_t)0xc125, + (q15_t)0x33e6, (q15_t)0xc128, (q15_t)0x33da, (q15_t)0xc12a, (q15_t)0x33ce, (q15_t)0xc12c, (q15_t)0x33c1, (q15_t)0xc12f, + (q15_t)0x33b5, (q15_t)0xc131, (q15_t)0x33a9, (q15_t)0xc134, (q15_t)0x339c, (q15_t)0xc136, (q15_t)0x3390, (q15_t)0xc138, + (q15_t)0x3384, (q15_t)0xc13b, (q15_t)0x3377, (q15_t)0xc13d, (q15_t)0x336b, (q15_t)0xc140, (q15_t)0x335f, (q15_t)0xc142, + (q15_t)0x3352, (q15_t)0xc145, (q15_t)0x3346, (q15_t)0xc147, (q15_t)0x333a, (q15_t)0xc14a, (q15_t)0x332d, (q15_t)0xc14c, + (q15_t)0x3321, (q15_t)0xc14f, (q15_t)0x3315, (q15_t)0xc151, (q15_t)0x3308, (q15_t)0xc154, (q15_t)0x32fc, (q15_t)0xc156, + (q15_t)0x32f0, (q15_t)0xc159, (q15_t)0x32e4, (q15_t)0xc15b, (q15_t)0x32d7, (q15_t)0xc15e, (q15_t)0x32cb, (q15_t)0xc161, + (q15_t)0x32bf, (q15_t)0xc163, (q15_t)0x32b2, (q15_t)0xc166, (q15_t)0x32a6, (q15_t)0xc168, (q15_t)0x329a, (q15_t)0xc16b, + (q15_t)0x328e, (q15_t)0xc16e, (q15_t)0x3281, (q15_t)0xc170, (q15_t)0x3275, (q15_t)0xc173, (q15_t)0x3269, (q15_t)0xc176, + (q15_t)0x325c, (q15_t)0xc178, (q15_t)0x3250, (q15_t)0xc17b, (q15_t)0x3244, (q15_t)0xc17e, (q15_t)0x3238, (q15_t)0xc180, + (q15_t)0x322b, (q15_t)0xc183, (q15_t)0x321f, (q15_t)0xc186, (q15_t)0x3213, (q15_t)0xc189, (q15_t)0x3207, (q15_t)0xc18b, + (q15_t)0x31fa, (q15_t)0xc18e, (q15_t)0x31ee, (q15_t)0xc191, (q15_t)0x31e2, (q15_t)0xc194, (q15_t)0x31d5, (q15_t)0xc196, + (q15_t)0x31c9, (q15_t)0xc199, (q15_t)0x31bd, (q15_t)0xc19c, (q15_t)0x31b1, (q15_t)0xc19f, (q15_t)0x31a4, (q15_t)0xc1a2, + (q15_t)0x3198, (q15_t)0xc1a4, (q15_t)0x318c, (q15_t)0xc1a7, (q15_t)0x3180, (q15_t)0xc1aa, (q15_t)0x3174, (q15_t)0xc1ad, + (q15_t)0x3167, (q15_t)0xc1b0, (q15_t)0x315b, (q15_t)0xc1b3, (q15_t)0x314f, (q15_t)0xc1b6, (q15_t)0x3143, (q15_t)0xc1b8, + (q15_t)0x3136, (q15_t)0xc1bb, (q15_t)0x312a, (q15_t)0xc1be, (q15_t)0x311e, (q15_t)0xc1c1, (q15_t)0x3112, (q15_t)0xc1c4, + (q15_t)0x3105, (q15_t)0xc1c7, (q15_t)0x30f9, (q15_t)0xc1ca, (q15_t)0x30ed, (q15_t)0xc1cd, (q15_t)0x30e1, (q15_t)0xc1d0, + (q15_t)0x30d5, (q15_t)0xc1d3, (q15_t)0x30c8, (q15_t)0xc1d6, (q15_t)0x30bc, (q15_t)0xc1d9, (q15_t)0x30b0, (q15_t)0xc1dc, + (q15_t)0x30a4, (q15_t)0xc1df, (q15_t)0x3098, (q15_t)0xc1e2, (q15_t)0x308b, (q15_t)0xc1e5, (q15_t)0x307f, (q15_t)0xc1e8, + (q15_t)0x3073, (q15_t)0xc1eb, (q15_t)0x3067, (q15_t)0xc1ee, (q15_t)0x305b, (q15_t)0xc1f1, (q15_t)0x304e, (q15_t)0xc1f4, + (q15_t)0x3042, (q15_t)0xc1f7, (q15_t)0x3036, (q15_t)0xc1fa, (q15_t)0x302a, (q15_t)0xc1fd, (q15_t)0x301e, (q15_t)0xc201, + (q15_t)0x3012, (q15_t)0xc204, (q15_t)0x3005, (q15_t)0xc207, (q15_t)0x2ff9, (q15_t)0xc20a, (q15_t)0x2fed, (q15_t)0xc20d, + (q15_t)0x2fe1, (q15_t)0xc210, (q15_t)0x2fd5, (q15_t)0xc213, (q15_t)0x2fc9, (q15_t)0xc217, (q15_t)0x2fbc, (q15_t)0xc21a, + (q15_t)0x2fb0, (q15_t)0xc21d, (q15_t)0x2fa4, (q15_t)0xc220, (q15_t)0x2f98, (q15_t)0xc223, (q15_t)0x2f8c, (q15_t)0xc227, + (q15_t)0x2f80, (q15_t)0xc22a, (q15_t)0x2f74, (q15_t)0xc22d, (q15_t)0x2f67, (q15_t)0xc230, (q15_t)0x2f5b, (q15_t)0xc234, + (q15_t)0x2f4f, (q15_t)0xc237, (q15_t)0x2f43, (q15_t)0xc23a, (q15_t)0x2f37, (q15_t)0xc23e, (q15_t)0x2f2b, (q15_t)0xc241, + (q15_t)0x2f1f, (q15_t)0xc244, (q15_t)0x2f13, (q15_t)0xc247, (q15_t)0x2f06, (q15_t)0xc24b, (q15_t)0x2efa, (q15_t)0xc24e, + (q15_t)0x2eee, (q15_t)0xc251, (q15_t)0x2ee2, (q15_t)0xc255, (q15_t)0x2ed6, (q15_t)0xc258, (q15_t)0x2eca, (q15_t)0xc25c, + (q15_t)0x2ebe, (q15_t)0xc25f, (q15_t)0x2eb2, (q15_t)0xc262, (q15_t)0x2ea6, (q15_t)0xc266, (q15_t)0x2e99, (q15_t)0xc269, + (q15_t)0x2e8d, (q15_t)0xc26d, (q15_t)0x2e81, (q15_t)0xc270, (q15_t)0x2e75, (q15_t)0xc273, (q15_t)0x2e69, (q15_t)0xc277, + (q15_t)0x2e5d, (q15_t)0xc27a, (q15_t)0x2e51, (q15_t)0xc27e, (q15_t)0x2e45, (q15_t)0xc281, (q15_t)0x2e39, (q15_t)0xc285, + (q15_t)0x2e2d, (q15_t)0xc288, (q15_t)0x2e21, (q15_t)0xc28c, (q15_t)0x2e15, (q15_t)0xc28f, (q15_t)0x2e09, (q15_t)0xc293, + (q15_t)0x2dfc, (q15_t)0xc296, (q15_t)0x2df0, (q15_t)0xc29a, (q15_t)0x2de4, (q15_t)0xc29d, (q15_t)0x2dd8, (q15_t)0xc2a1, + (q15_t)0x2dcc, (q15_t)0xc2a5, (q15_t)0x2dc0, (q15_t)0xc2a8, (q15_t)0x2db4, (q15_t)0xc2ac, (q15_t)0x2da8, (q15_t)0xc2af, + (q15_t)0x2d9c, (q15_t)0xc2b3, (q15_t)0x2d90, (q15_t)0xc2b7, (q15_t)0x2d84, (q15_t)0xc2ba, (q15_t)0x2d78, (q15_t)0xc2be, + (q15_t)0x2d6c, (q15_t)0xc2c1, (q15_t)0x2d60, (q15_t)0xc2c5, (q15_t)0x2d54, (q15_t)0xc2c9, (q15_t)0x2d48, (q15_t)0xc2cc, + (q15_t)0x2d3c, (q15_t)0xc2d0, (q15_t)0x2d30, (q15_t)0xc2d4, (q15_t)0x2d24, (q15_t)0xc2d8, (q15_t)0x2d18, (q15_t)0xc2db, + (q15_t)0x2d0c, (q15_t)0xc2df, (q15_t)0x2d00, (q15_t)0xc2e3, (q15_t)0x2cf4, (q15_t)0xc2e6, (q15_t)0x2ce8, (q15_t)0xc2ea, + (q15_t)0x2cdc, (q15_t)0xc2ee, (q15_t)0x2cd0, (q15_t)0xc2f2, (q15_t)0x2cc4, (q15_t)0xc2f5, (q15_t)0x2cb8, (q15_t)0xc2f9, + (q15_t)0x2cac, (q15_t)0xc2fd, (q15_t)0x2ca0, (q15_t)0xc301, (q15_t)0x2c94, (q15_t)0xc305, (q15_t)0x2c88, (q15_t)0xc308, + (q15_t)0x2c7c, (q15_t)0xc30c, (q15_t)0x2c70, (q15_t)0xc310, (q15_t)0x2c64, (q15_t)0xc314, (q15_t)0x2c58, (q15_t)0xc318, + (q15_t)0x2c4c, (q15_t)0xc31c, (q15_t)0x2c40, (q15_t)0xc320, (q15_t)0x2c34, (q15_t)0xc323, (q15_t)0x2c28, (q15_t)0xc327, + (q15_t)0x2c1c, (q15_t)0xc32b, (q15_t)0x2c10, (q15_t)0xc32f, (q15_t)0x2c05, (q15_t)0xc333, (q15_t)0x2bf9, (q15_t)0xc337, + (q15_t)0x2bed, (q15_t)0xc33b, (q15_t)0x2be1, (q15_t)0xc33f, (q15_t)0x2bd5, (q15_t)0xc343, (q15_t)0x2bc9, (q15_t)0xc347, + (q15_t)0x2bbd, (q15_t)0xc34b, (q15_t)0x2bb1, (q15_t)0xc34f, (q15_t)0x2ba5, (q15_t)0xc353, (q15_t)0x2b99, (q15_t)0xc357, + (q15_t)0x2b8d, (q15_t)0xc35b, (q15_t)0x2b81, (q15_t)0xc35f, (q15_t)0x2b75, (q15_t)0xc363, (q15_t)0x2b6a, (q15_t)0xc367, + (q15_t)0x2b5e, (q15_t)0xc36b, (q15_t)0x2b52, (q15_t)0xc36f, (q15_t)0x2b46, (q15_t)0xc373, (q15_t)0x2b3a, (q15_t)0xc377, + (q15_t)0x2b2e, (q15_t)0xc37b, (q15_t)0x2b22, (q15_t)0xc37f, (q15_t)0x2b16, (q15_t)0xc383, (q15_t)0x2b0a, (q15_t)0xc387, + (q15_t)0x2aff, (q15_t)0xc38c, (q15_t)0x2af3, (q15_t)0xc390, (q15_t)0x2ae7, (q15_t)0xc394, (q15_t)0x2adb, (q15_t)0xc398, + (q15_t)0x2acf, (q15_t)0xc39c, (q15_t)0x2ac3, (q15_t)0xc3a0, (q15_t)0x2ab7, (q15_t)0xc3a5, (q15_t)0x2aac, (q15_t)0xc3a9, + (q15_t)0x2aa0, (q15_t)0xc3ad, (q15_t)0x2a94, (q15_t)0xc3b1, (q15_t)0x2a88, (q15_t)0xc3b5, (q15_t)0x2a7c, (q15_t)0xc3ba, + (q15_t)0x2a70, (q15_t)0xc3be, (q15_t)0x2a65, (q15_t)0xc3c2, (q15_t)0x2a59, (q15_t)0xc3c6, (q15_t)0x2a4d, (q15_t)0xc3ca, + (q15_t)0x2a41, (q15_t)0xc3cf, (q15_t)0x2a35, (q15_t)0xc3d3, (q15_t)0x2a29, (q15_t)0xc3d7, (q15_t)0x2a1e, (q15_t)0xc3dc, + (q15_t)0x2a12, (q15_t)0xc3e0, (q15_t)0x2a06, (q15_t)0xc3e4, (q15_t)0x29fa, (q15_t)0xc3e9, (q15_t)0x29ee, (q15_t)0xc3ed, + (q15_t)0x29e3, (q15_t)0xc3f1, (q15_t)0x29d7, (q15_t)0xc3f6, (q15_t)0x29cb, (q15_t)0xc3fa, (q15_t)0x29bf, (q15_t)0xc3fe, + (q15_t)0x29b4, (q15_t)0xc403, (q15_t)0x29a8, (q15_t)0xc407, (q15_t)0x299c, (q15_t)0xc40b, (q15_t)0x2990, (q15_t)0xc410, + (q15_t)0x2984, (q15_t)0xc414, (q15_t)0x2979, (q15_t)0xc419, (q15_t)0x296d, (q15_t)0xc41d, (q15_t)0x2961, (q15_t)0xc422, + (q15_t)0x2955, (q15_t)0xc426, (q15_t)0x294a, (q15_t)0xc42a, (q15_t)0x293e, (q15_t)0xc42f, (q15_t)0x2932, (q15_t)0xc433, + (q15_t)0x2926, (q15_t)0xc438, (q15_t)0x291b, (q15_t)0xc43c, (q15_t)0x290f, (q15_t)0xc441, (q15_t)0x2903, (q15_t)0xc445, + (q15_t)0x28f7, (q15_t)0xc44a, (q15_t)0x28ec, (q15_t)0xc44e, (q15_t)0x28e0, (q15_t)0xc453, (q15_t)0x28d4, (q15_t)0xc457, + (q15_t)0x28c9, (q15_t)0xc45c, (q15_t)0x28bd, (q15_t)0xc461, (q15_t)0x28b1, (q15_t)0xc465, (q15_t)0x28a5, (q15_t)0xc46a, + (q15_t)0x289a, (q15_t)0xc46e, (q15_t)0x288e, (q15_t)0xc473, (q15_t)0x2882, (q15_t)0xc478, (q15_t)0x2877, (q15_t)0xc47c, + (q15_t)0x286b, (q15_t)0xc481, (q15_t)0x285f, (q15_t)0xc485, (q15_t)0x2854, (q15_t)0xc48a, (q15_t)0x2848, (q15_t)0xc48f, + (q15_t)0x283c, (q15_t)0xc493, (q15_t)0x2831, (q15_t)0xc498, (q15_t)0x2825, (q15_t)0xc49d, (q15_t)0x2819, (q15_t)0xc4a1, + (q15_t)0x280e, (q15_t)0xc4a6, (q15_t)0x2802, (q15_t)0xc4ab, (q15_t)0x27f6, (q15_t)0xc4b0, (q15_t)0x27eb, (q15_t)0xc4b4, + (q15_t)0x27df, (q15_t)0xc4b9, (q15_t)0x27d3, (q15_t)0xc4be, (q15_t)0x27c8, (q15_t)0xc4c2, (q15_t)0x27bc, (q15_t)0xc4c7, + (q15_t)0x27b1, (q15_t)0xc4cc, (q15_t)0x27a5, (q15_t)0xc4d1, (q15_t)0x2799, (q15_t)0xc4d6, (q15_t)0x278e, (q15_t)0xc4da, + (q15_t)0x2782, (q15_t)0xc4df, (q15_t)0x2777, (q15_t)0xc4e4, (q15_t)0x276b, (q15_t)0xc4e9, (q15_t)0x275f, (q15_t)0xc4ee, + (q15_t)0x2754, (q15_t)0xc4f2, (q15_t)0x2748, (q15_t)0xc4f7, (q15_t)0x273d, (q15_t)0xc4fc, (q15_t)0x2731, (q15_t)0xc501, + (q15_t)0x2725, (q15_t)0xc506, (q15_t)0x271a, (q15_t)0xc50b, (q15_t)0x270e, (q15_t)0xc510, (q15_t)0x2703, (q15_t)0xc515, + (q15_t)0x26f7, (q15_t)0xc51a, (q15_t)0x26ec, (q15_t)0xc51e, (q15_t)0x26e0, (q15_t)0xc523, (q15_t)0x26d4, (q15_t)0xc528, + (q15_t)0x26c9, (q15_t)0xc52d, (q15_t)0x26bd, (q15_t)0xc532, (q15_t)0x26b2, (q15_t)0xc537, (q15_t)0x26a6, (q15_t)0xc53c, + (q15_t)0x269b, (q15_t)0xc541, (q15_t)0x268f, (q15_t)0xc546, (q15_t)0x2684, (q15_t)0xc54b, (q15_t)0x2678, (q15_t)0xc550, + (q15_t)0x266d, (q15_t)0xc555, (q15_t)0x2661, (q15_t)0xc55a, (q15_t)0x2656, (q15_t)0xc55f, (q15_t)0x264a, (q15_t)0xc564, + (q15_t)0x263f, (q15_t)0xc569, (q15_t)0x2633, (q15_t)0xc56e, (q15_t)0x2628, (q15_t)0xc573, (q15_t)0x261c, (q15_t)0xc578, + (q15_t)0x2611, (q15_t)0xc57e, (q15_t)0x2605, (q15_t)0xc583, (q15_t)0x25fa, (q15_t)0xc588, (q15_t)0x25ee, (q15_t)0xc58d, + (q15_t)0x25e3, (q15_t)0xc592, (q15_t)0x25d7, (q15_t)0xc597, (q15_t)0x25cc, (q15_t)0xc59c, (q15_t)0x25c0, (q15_t)0xc5a1, + (q15_t)0x25b5, (q15_t)0xc5a7, (q15_t)0x25a9, (q15_t)0xc5ac, (q15_t)0x259e, (q15_t)0xc5b1, (q15_t)0x2592, (q15_t)0xc5b6, + (q15_t)0x2587, (q15_t)0xc5bb, (q15_t)0x257c, (q15_t)0xc5c1, (q15_t)0x2570, (q15_t)0xc5c6, (q15_t)0x2565, (q15_t)0xc5cb, + (q15_t)0x2559, (q15_t)0xc5d0, (q15_t)0x254e, (q15_t)0xc5d5, (q15_t)0x2542, (q15_t)0xc5db, (q15_t)0x2537, (q15_t)0xc5e0, + (q15_t)0x252c, (q15_t)0xc5e5, (q15_t)0x2520, (q15_t)0xc5ea, (q15_t)0x2515, (q15_t)0xc5f0, (q15_t)0x2509, (q15_t)0xc5f5, + (q15_t)0x24fe, (q15_t)0xc5fa, (q15_t)0x24f3, (q15_t)0xc600, (q15_t)0x24e7, (q15_t)0xc605, (q15_t)0x24dc, (q15_t)0xc60a, + (q15_t)0x24d0, (q15_t)0xc610, (q15_t)0x24c5, (q15_t)0xc615, (q15_t)0x24ba, (q15_t)0xc61a, (q15_t)0x24ae, (q15_t)0xc620, + (q15_t)0x24a3, (q15_t)0xc625, (q15_t)0x2498, (q15_t)0xc62a, (q15_t)0x248c, (q15_t)0xc630, (q15_t)0x2481, (q15_t)0xc635, + (q15_t)0x2476, (q15_t)0xc63b, (q15_t)0x246a, (q15_t)0xc640, (q15_t)0x245f, (q15_t)0xc645, (q15_t)0x2454, (q15_t)0xc64b, + (q15_t)0x2448, (q15_t)0xc650, (q15_t)0x243d, (q15_t)0xc656, (q15_t)0x2432, (q15_t)0xc65b, (q15_t)0x2426, (q15_t)0xc661, + (q15_t)0x241b, (q15_t)0xc666, (q15_t)0x2410, (q15_t)0xc66c, (q15_t)0x2404, (q15_t)0xc671, (q15_t)0x23f9, (q15_t)0xc677, + (q15_t)0x23ee, (q15_t)0xc67c, (q15_t)0x23e2, (q15_t)0xc682, (q15_t)0x23d7, (q15_t)0xc687, (q15_t)0x23cc, (q15_t)0xc68d, + (q15_t)0x23c1, (q15_t)0xc692, (q15_t)0x23b5, (q15_t)0xc698, (q15_t)0x23aa, (q15_t)0xc69d, (q15_t)0x239f, (q15_t)0xc6a3, + (q15_t)0x2394, (q15_t)0xc6a8, (q15_t)0x2388, (q15_t)0xc6ae, (q15_t)0x237d, (q15_t)0xc6b4, (q15_t)0x2372, (q15_t)0xc6b9, + (q15_t)0x2367, (q15_t)0xc6bf, (q15_t)0x235b, (q15_t)0xc6c5, (q15_t)0x2350, (q15_t)0xc6ca, (q15_t)0x2345, (q15_t)0xc6d0, + (q15_t)0x233a, (q15_t)0xc6d5, (q15_t)0x232e, (q15_t)0xc6db, (q15_t)0x2323, (q15_t)0xc6e1, (q15_t)0x2318, (q15_t)0xc6e6, + (q15_t)0x230d, (q15_t)0xc6ec, (q15_t)0x2301, (q15_t)0xc6f2, (q15_t)0x22f6, (q15_t)0xc6f7, (q15_t)0x22eb, (q15_t)0xc6fd, + (q15_t)0x22e0, (q15_t)0xc703, (q15_t)0x22d5, (q15_t)0xc709, (q15_t)0x22ca, (q15_t)0xc70e, (q15_t)0x22be, (q15_t)0xc714, + (q15_t)0x22b3, (q15_t)0xc71a, (q15_t)0x22a8, (q15_t)0xc720, (q15_t)0x229d, (q15_t)0xc725, (q15_t)0x2292, (q15_t)0xc72b, + (q15_t)0x2287, (q15_t)0xc731, (q15_t)0x227b, (q15_t)0xc737, (q15_t)0x2270, (q15_t)0xc73d, (q15_t)0x2265, (q15_t)0xc742, + (q15_t)0x225a, (q15_t)0xc748, (q15_t)0x224f, (q15_t)0xc74e, (q15_t)0x2244, (q15_t)0xc754, (q15_t)0x2239, (q15_t)0xc75a, + (q15_t)0x222d, (q15_t)0xc75f, (q15_t)0x2222, (q15_t)0xc765, (q15_t)0x2217, (q15_t)0xc76b, (q15_t)0x220c, (q15_t)0xc771, + (q15_t)0x2201, (q15_t)0xc777, (q15_t)0x21f6, (q15_t)0xc77d, (q15_t)0x21eb, (q15_t)0xc783, (q15_t)0x21e0, (q15_t)0xc789, + (q15_t)0x21d5, (q15_t)0xc78f, (q15_t)0x21ca, (q15_t)0xc795, (q15_t)0x21be, (q15_t)0xc79a, (q15_t)0x21b3, (q15_t)0xc7a0, + (q15_t)0x21a8, (q15_t)0xc7a6, (q15_t)0x219d, (q15_t)0xc7ac, (q15_t)0x2192, (q15_t)0xc7b2, (q15_t)0x2187, (q15_t)0xc7b8, + (q15_t)0x217c, (q15_t)0xc7be, (q15_t)0x2171, (q15_t)0xc7c4, (q15_t)0x2166, (q15_t)0xc7ca, (q15_t)0x215b, (q15_t)0xc7d0, + (q15_t)0x2150, (q15_t)0xc7d6, (q15_t)0x2145, (q15_t)0xc7dc, (q15_t)0x213a, (q15_t)0xc7e2, (q15_t)0x212f, (q15_t)0xc7e8, + (q15_t)0x2124, (q15_t)0xc7ee, (q15_t)0x2119, (q15_t)0xc7f5, (q15_t)0x210e, (q15_t)0xc7fb, (q15_t)0x2103, (q15_t)0xc801, + (q15_t)0x20f8, (q15_t)0xc807, (q15_t)0x20ed, (q15_t)0xc80d, (q15_t)0x20e2, (q15_t)0xc813, (q15_t)0x20d7, (q15_t)0xc819, + (q15_t)0x20cc, (q15_t)0xc81f, (q15_t)0x20c1, (q15_t)0xc825, (q15_t)0x20b6, (q15_t)0xc82b, (q15_t)0x20ab, (q15_t)0xc832, + (q15_t)0x20a0, (q15_t)0xc838, (q15_t)0x2095, (q15_t)0xc83e, (q15_t)0x208a, (q15_t)0xc844, (q15_t)0x207f, (q15_t)0xc84a, + (q15_t)0x2074, (q15_t)0xc850, (q15_t)0x2069, (q15_t)0xc857, (q15_t)0x205e, (q15_t)0xc85d, (q15_t)0x2054, (q15_t)0xc863, + (q15_t)0x2049, (q15_t)0xc869, (q15_t)0x203e, (q15_t)0xc870, (q15_t)0x2033, (q15_t)0xc876, (q15_t)0x2028, (q15_t)0xc87c, + (q15_t)0x201d, (q15_t)0xc882, (q15_t)0x2012, (q15_t)0xc889, (q15_t)0x2007, (q15_t)0xc88f, (q15_t)0x1ffc, (q15_t)0xc895, + (q15_t)0x1ff1, (q15_t)0xc89b, (q15_t)0x1fe7, (q15_t)0xc8a2, (q15_t)0x1fdc, (q15_t)0xc8a8, (q15_t)0x1fd1, (q15_t)0xc8ae, + (q15_t)0x1fc6, (q15_t)0xc8b5, (q15_t)0x1fbb, (q15_t)0xc8bb, (q15_t)0x1fb0, (q15_t)0xc8c1, (q15_t)0x1fa5, (q15_t)0xc8c8, + (q15_t)0x1f9b, (q15_t)0xc8ce, (q15_t)0x1f90, (q15_t)0xc8d4, (q15_t)0x1f85, (q15_t)0xc8db, (q15_t)0x1f7a, (q15_t)0xc8e1, + (q15_t)0x1f6f, (q15_t)0xc8e8, (q15_t)0x1f65, (q15_t)0xc8ee, (q15_t)0x1f5a, (q15_t)0xc8f4, (q15_t)0x1f4f, (q15_t)0xc8fb, + (q15_t)0x1f44, (q15_t)0xc901, (q15_t)0x1f39, (q15_t)0xc908, (q15_t)0x1f2f, (q15_t)0xc90e, (q15_t)0x1f24, (q15_t)0xc915, + (q15_t)0x1f19, (q15_t)0xc91b, (q15_t)0x1f0e, (q15_t)0xc921, (q15_t)0x1f03, (q15_t)0xc928, (q15_t)0x1ef9, (q15_t)0xc92e, + (q15_t)0x1eee, (q15_t)0xc935, (q15_t)0x1ee3, (q15_t)0xc93b, (q15_t)0x1ed8, (q15_t)0xc942, (q15_t)0x1ece, (q15_t)0xc948, + (q15_t)0x1ec3, (q15_t)0xc94f, (q15_t)0x1eb8, (q15_t)0xc955, (q15_t)0x1ead, (q15_t)0xc95c, (q15_t)0x1ea3, (q15_t)0xc963, + (q15_t)0x1e98, (q15_t)0xc969, (q15_t)0x1e8d, (q15_t)0xc970, (q15_t)0x1e83, (q15_t)0xc976, (q15_t)0x1e78, (q15_t)0xc97d, + (q15_t)0x1e6d, (q15_t)0xc983, (q15_t)0x1e62, (q15_t)0xc98a, (q15_t)0x1e58, (q15_t)0xc991, (q15_t)0x1e4d, (q15_t)0xc997, + (q15_t)0x1e42, (q15_t)0xc99e, (q15_t)0x1e38, (q15_t)0xc9a4, (q15_t)0x1e2d, (q15_t)0xc9ab, (q15_t)0x1e22, (q15_t)0xc9b2, + (q15_t)0x1e18, (q15_t)0xc9b8, (q15_t)0x1e0d, (q15_t)0xc9bf, (q15_t)0x1e02, (q15_t)0xc9c6, (q15_t)0x1df8, (q15_t)0xc9cc, + (q15_t)0x1ded, (q15_t)0xc9d3, (q15_t)0x1de2, (q15_t)0xc9da, (q15_t)0x1dd8, (q15_t)0xc9e0, (q15_t)0x1dcd, (q15_t)0xc9e7, + (q15_t)0x1dc3, (q15_t)0xc9ee, (q15_t)0x1db8, (q15_t)0xc9f5, (q15_t)0x1dad, (q15_t)0xc9fb, (q15_t)0x1da3, (q15_t)0xca02, + (q15_t)0x1d98, (q15_t)0xca09, (q15_t)0x1d8e, (q15_t)0xca10, (q15_t)0x1d83, (q15_t)0xca16, (q15_t)0x1d78, (q15_t)0xca1d, + (q15_t)0x1d6e, (q15_t)0xca24, (q15_t)0x1d63, (q15_t)0xca2b, (q15_t)0x1d59, (q15_t)0xca32, (q15_t)0x1d4e, (q15_t)0xca38, + (q15_t)0x1d44, (q15_t)0xca3f, (q15_t)0x1d39, (q15_t)0xca46, (q15_t)0x1d2e, (q15_t)0xca4d, (q15_t)0x1d24, (q15_t)0xca54, + (q15_t)0x1d19, (q15_t)0xca5b, (q15_t)0x1d0f, (q15_t)0xca61, (q15_t)0x1d04, (q15_t)0xca68, (q15_t)0x1cfa, (q15_t)0xca6f, + (q15_t)0x1cef, (q15_t)0xca76, (q15_t)0x1ce5, (q15_t)0xca7d, (q15_t)0x1cda, (q15_t)0xca84, (q15_t)0x1cd0, (q15_t)0xca8b, + (q15_t)0x1cc5, (q15_t)0xca92, (q15_t)0x1cbb, (q15_t)0xca99, (q15_t)0x1cb0, (q15_t)0xca9f, (q15_t)0x1ca6, (q15_t)0xcaa6, + (q15_t)0x1c9b, (q15_t)0xcaad, (q15_t)0x1c91, (q15_t)0xcab4, (q15_t)0x1c86, (q15_t)0xcabb, (q15_t)0x1c7c, (q15_t)0xcac2, + (q15_t)0x1c72, (q15_t)0xcac9, (q15_t)0x1c67, (q15_t)0xcad0, (q15_t)0x1c5d, (q15_t)0xcad7, (q15_t)0x1c52, (q15_t)0xcade, + (q15_t)0x1c48, (q15_t)0xcae5, (q15_t)0x1c3d, (q15_t)0xcaec, (q15_t)0x1c33, (q15_t)0xcaf3, (q15_t)0x1c29, (q15_t)0xcafa, + (q15_t)0x1c1e, (q15_t)0xcb01, (q15_t)0x1c14, (q15_t)0xcb08, (q15_t)0x1c09, (q15_t)0xcb0f, (q15_t)0x1bff, (q15_t)0xcb16, + (q15_t)0x1bf5, (q15_t)0xcb1e, (q15_t)0x1bea, (q15_t)0xcb25, (q15_t)0x1be0, (q15_t)0xcb2c, (q15_t)0x1bd5, (q15_t)0xcb33, + (q15_t)0x1bcb, (q15_t)0xcb3a, (q15_t)0x1bc1, (q15_t)0xcb41, (q15_t)0x1bb6, (q15_t)0xcb48, (q15_t)0x1bac, (q15_t)0xcb4f, + (q15_t)0x1ba2, (q15_t)0xcb56, (q15_t)0x1b97, (q15_t)0xcb5e, (q15_t)0x1b8d, (q15_t)0xcb65, (q15_t)0x1b83, (q15_t)0xcb6c, + (q15_t)0x1b78, (q15_t)0xcb73, (q15_t)0x1b6e, (q15_t)0xcb7a, (q15_t)0x1b64, (q15_t)0xcb81, (q15_t)0x1b59, (q15_t)0xcb89, + (q15_t)0x1b4f, (q15_t)0xcb90, (q15_t)0x1b45, (q15_t)0xcb97, (q15_t)0x1b3b, (q15_t)0xcb9e, (q15_t)0x1b30, (q15_t)0xcba5, + (q15_t)0x1b26, (q15_t)0xcbad, (q15_t)0x1b1c, (q15_t)0xcbb4, (q15_t)0x1b11, (q15_t)0xcbbb, (q15_t)0x1b07, (q15_t)0xcbc2, + (q15_t)0x1afd, (q15_t)0xcbca, (q15_t)0x1af3, (q15_t)0xcbd1, (q15_t)0x1ae8, (q15_t)0xcbd8, (q15_t)0x1ade, (q15_t)0xcbe0, + (q15_t)0x1ad4, (q15_t)0xcbe7, (q15_t)0x1aca, (q15_t)0xcbee, (q15_t)0x1abf, (q15_t)0xcbf5, (q15_t)0x1ab5, (q15_t)0xcbfd, + (q15_t)0x1aab, (q15_t)0xcc04, (q15_t)0x1aa1, (q15_t)0xcc0b, (q15_t)0x1a97, (q15_t)0xcc13, (q15_t)0x1a8c, (q15_t)0xcc1a, + (q15_t)0x1a82, (q15_t)0xcc21, (q15_t)0x1a78, (q15_t)0xcc29, (q15_t)0x1a6e, (q15_t)0xcc30, (q15_t)0x1a64, (q15_t)0xcc38, + (q15_t)0x1a5a, (q15_t)0xcc3f, (q15_t)0x1a4f, (q15_t)0xcc46, (q15_t)0x1a45, (q15_t)0xcc4e, (q15_t)0x1a3b, (q15_t)0xcc55, + (q15_t)0x1a31, (q15_t)0xcc5d, (q15_t)0x1a27, (q15_t)0xcc64, (q15_t)0x1a1d, (q15_t)0xcc6b, (q15_t)0x1a13, (q15_t)0xcc73, + (q15_t)0x1a08, (q15_t)0xcc7a, (q15_t)0x19fe, (q15_t)0xcc82, (q15_t)0x19f4, (q15_t)0xcc89, (q15_t)0x19ea, (q15_t)0xcc91, + (q15_t)0x19e0, (q15_t)0xcc98, (q15_t)0x19d6, (q15_t)0xcca0, (q15_t)0x19cc, (q15_t)0xcca7, (q15_t)0x19c2, (q15_t)0xccaf, + (q15_t)0x19b8, (q15_t)0xccb6, (q15_t)0x19ae, (q15_t)0xccbe, (q15_t)0x19a4, (q15_t)0xccc5, (q15_t)0x199a, (q15_t)0xcccd, + (q15_t)0x198f, (q15_t)0xccd4, (q15_t)0x1985, (q15_t)0xccdc, (q15_t)0x197b, (q15_t)0xcce3, (q15_t)0x1971, (q15_t)0xcceb, + (q15_t)0x1967, (q15_t)0xccf3, (q15_t)0x195d, (q15_t)0xccfa, (q15_t)0x1953, (q15_t)0xcd02, (q15_t)0x1949, (q15_t)0xcd09, + (q15_t)0x193f, (q15_t)0xcd11, (q15_t)0x1935, (q15_t)0xcd19, (q15_t)0x192b, (q15_t)0xcd20, (q15_t)0x1921, (q15_t)0xcd28, + (q15_t)0x1917, (q15_t)0xcd30, (q15_t)0x190d, (q15_t)0xcd37, (q15_t)0x1903, (q15_t)0xcd3f, (q15_t)0x18f9, (q15_t)0xcd46, + (q15_t)0x18ef, (q15_t)0xcd4e, (q15_t)0x18e6, (q15_t)0xcd56, (q15_t)0x18dc, (q15_t)0xcd5d, (q15_t)0x18d2, (q15_t)0xcd65, + (q15_t)0x18c8, (q15_t)0xcd6d, (q15_t)0x18be, (q15_t)0xcd75, (q15_t)0x18b4, (q15_t)0xcd7c, (q15_t)0x18aa, (q15_t)0xcd84, + (q15_t)0x18a0, (q15_t)0xcd8c, (q15_t)0x1896, (q15_t)0xcd93, (q15_t)0x188c, (q15_t)0xcd9b, (q15_t)0x1882, (q15_t)0xcda3, + (q15_t)0x1878, (q15_t)0xcdab, (q15_t)0x186f, (q15_t)0xcdb2, (q15_t)0x1865, (q15_t)0xcdba, (q15_t)0x185b, (q15_t)0xcdc2, + (q15_t)0x1851, (q15_t)0xcdca, (q15_t)0x1847, (q15_t)0xcdd2, (q15_t)0x183d, (q15_t)0xcdd9, (q15_t)0x1833, (q15_t)0xcde1, + (q15_t)0x182a, (q15_t)0xcde9, (q15_t)0x1820, (q15_t)0xcdf1, (q15_t)0x1816, (q15_t)0xcdf9, (q15_t)0x180c, (q15_t)0xce01, + (q15_t)0x1802, (q15_t)0xce08, (q15_t)0x17f8, (q15_t)0xce10, (q15_t)0x17ef, (q15_t)0xce18, (q15_t)0x17e5, (q15_t)0xce20, + (q15_t)0x17db, (q15_t)0xce28, (q15_t)0x17d1, (q15_t)0xce30, (q15_t)0x17c8, (q15_t)0xce38, (q15_t)0x17be, (q15_t)0xce40, + (q15_t)0x17b4, (q15_t)0xce47, (q15_t)0x17aa, (q15_t)0xce4f, (q15_t)0x17a0, (q15_t)0xce57, (q15_t)0x1797, (q15_t)0xce5f, + (q15_t)0x178d, (q15_t)0xce67, (q15_t)0x1783, (q15_t)0xce6f, (q15_t)0x177a, (q15_t)0xce77, (q15_t)0x1770, (q15_t)0xce7f, + (q15_t)0x1766, (q15_t)0xce87, (q15_t)0x175c, (q15_t)0xce8f, (q15_t)0x1753, (q15_t)0xce97, (q15_t)0x1749, (q15_t)0xce9f, + (q15_t)0x173f, (q15_t)0xcea7, (q15_t)0x1736, (q15_t)0xceaf, (q15_t)0x172c, (q15_t)0xceb7, (q15_t)0x1722, (q15_t)0xcebf, + (q15_t)0x1719, (q15_t)0xcec7, (q15_t)0x170f, (q15_t)0xcecf, (q15_t)0x1705, (q15_t)0xced7, (q15_t)0x16fc, (q15_t)0xcedf, + (q15_t)0x16f2, (q15_t)0xcee7, (q15_t)0x16e8, (q15_t)0xceef, (q15_t)0x16df, (q15_t)0xcef7, (q15_t)0x16d5, (q15_t)0xceff, + (q15_t)0x16cb, (q15_t)0xcf07, (q15_t)0x16c2, (q15_t)0xcf10, (q15_t)0x16b8, (q15_t)0xcf18, (q15_t)0x16af, (q15_t)0xcf20, + (q15_t)0x16a5, (q15_t)0xcf28, (q15_t)0x169b, (q15_t)0xcf30, (q15_t)0x1692, (q15_t)0xcf38, (q15_t)0x1688, (q15_t)0xcf40, + (q15_t)0x167f, (q15_t)0xcf48, (q15_t)0x1675, (q15_t)0xcf51, (q15_t)0x166c, (q15_t)0xcf59, (q15_t)0x1662, (q15_t)0xcf61, + (q15_t)0x1659, (q15_t)0xcf69, (q15_t)0x164f, (q15_t)0xcf71, (q15_t)0x1645, (q15_t)0xcf79, (q15_t)0x163c, (q15_t)0xcf82, + (q15_t)0x1632, (q15_t)0xcf8a, (q15_t)0x1629, (q15_t)0xcf92, (q15_t)0x161f, (q15_t)0xcf9a, (q15_t)0x1616, (q15_t)0xcfa3, + (q15_t)0x160c, (q15_t)0xcfab, (q15_t)0x1603, (q15_t)0xcfb3, (q15_t)0x15f9, (q15_t)0xcfbb, (q15_t)0x15f0, (q15_t)0xcfc4, + (q15_t)0x15e6, (q15_t)0xcfcc, (q15_t)0x15dd, (q15_t)0xcfd4, (q15_t)0x15d4, (q15_t)0xcfdc, (q15_t)0x15ca, (q15_t)0xcfe5, + (q15_t)0x15c1, (q15_t)0xcfed, (q15_t)0x15b7, (q15_t)0xcff5, (q15_t)0x15ae, (q15_t)0xcffe, (q15_t)0x15a4, (q15_t)0xd006, + (q15_t)0x159b, (q15_t)0xd00e, (q15_t)0x1592, (q15_t)0xd016, (q15_t)0x1588, (q15_t)0xd01f, (q15_t)0x157f, (q15_t)0xd027, + (q15_t)0x1575, (q15_t)0xd030, (q15_t)0x156c, (q15_t)0xd038, (q15_t)0x1563, (q15_t)0xd040, (q15_t)0x1559, (q15_t)0xd049, + (q15_t)0x1550, (q15_t)0xd051, (q15_t)0x1547, (q15_t)0xd059, (q15_t)0x153d, (q15_t)0xd062, (q15_t)0x1534, (q15_t)0xd06a, + (q15_t)0x152a, (q15_t)0xd073, (q15_t)0x1521, (q15_t)0xd07b, (q15_t)0x1518, (q15_t)0xd083, (q15_t)0x150e, (q15_t)0xd08c, + (q15_t)0x1505, (q15_t)0xd094, (q15_t)0x14fc, (q15_t)0xd09d, (q15_t)0x14f3, (q15_t)0xd0a5, (q15_t)0x14e9, (q15_t)0xd0ae, + (q15_t)0x14e0, (q15_t)0xd0b6, (q15_t)0x14d7, (q15_t)0xd0bf, (q15_t)0x14cd, (q15_t)0xd0c7, (q15_t)0x14c4, (q15_t)0xd0d0, + (q15_t)0x14bb, (q15_t)0xd0d8, (q15_t)0x14b2, (q15_t)0xd0e0, (q15_t)0x14a8, (q15_t)0xd0e9, (q15_t)0x149f, (q15_t)0xd0f2, + (q15_t)0x1496, (q15_t)0xd0fa, (q15_t)0x148d, (q15_t)0xd103, (q15_t)0x1483, (q15_t)0xd10b, (q15_t)0x147a, (q15_t)0xd114, + (q15_t)0x1471, (q15_t)0xd11c, (q15_t)0x1468, (q15_t)0xd125, (q15_t)0x145f, (q15_t)0xd12d, (q15_t)0x1455, (q15_t)0xd136, + (q15_t)0x144c, (q15_t)0xd13e, (q15_t)0x1443, (q15_t)0xd147, (q15_t)0x143a, (q15_t)0xd150, (q15_t)0x1431, (q15_t)0xd158, + (q15_t)0x1428, (q15_t)0xd161, (q15_t)0x141e, (q15_t)0xd169, (q15_t)0x1415, (q15_t)0xd172, (q15_t)0x140c, (q15_t)0xd17b, + (q15_t)0x1403, (q15_t)0xd183, (q15_t)0x13fa, (q15_t)0xd18c, (q15_t)0x13f1, (q15_t)0xd195, (q15_t)0x13e8, (q15_t)0xd19d, + (q15_t)0x13df, (q15_t)0xd1a6, (q15_t)0x13d5, (q15_t)0xd1af, (q15_t)0x13cc, (q15_t)0xd1b7, (q15_t)0x13c3, (q15_t)0xd1c0, + (q15_t)0x13ba, (q15_t)0xd1c9, (q15_t)0x13b1, (q15_t)0xd1d1, (q15_t)0x13a8, (q15_t)0xd1da, (q15_t)0x139f, (q15_t)0xd1e3, + (q15_t)0x1396, (q15_t)0xd1eb, (q15_t)0x138d, (q15_t)0xd1f4, (q15_t)0x1384, (q15_t)0xd1fd, (q15_t)0x137b, (q15_t)0xd206, + (q15_t)0x1372, (q15_t)0xd20e, (q15_t)0x1369, (q15_t)0xd217, (q15_t)0x1360, (q15_t)0xd220, (q15_t)0x1357, (q15_t)0xd229, + (q15_t)0x134e, (q15_t)0xd231, (q15_t)0x1345, (q15_t)0xd23a, (q15_t)0x133c, (q15_t)0xd243, (q15_t)0x1333, (q15_t)0xd24c, + (q15_t)0x132a, (q15_t)0xd255, (q15_t)0x1321, (q15_t)0xd25d, (q15_t)0x1318, (q15_t)0xd266, (q15_t)0x130f, (q15_t)0xd26f, + (q15_t)0x1306, (q15_t)0xd278, (q15_t)0x12fd, (q15_t)0xd281, (q15_t)0x12f4, (q15_t)0xd28a, (q15_t)0x12eb, (q15_t)0xd292, + (q15_t)0x12e2, (q15_t)0xd29b, (q15_t)0x12d9, (q15_t)0xd2a4, (q15_t)0x12d1, (q15_t)0xd2ad, (q15_t)0x12c8, (q15_t)0xd2b6, + (q15_t)0x12bf, (q15_t)0xd2bf, (q15_t)0x12b6, (q15_t)0xd2c8, (q15_t)0x12ad, (q15_t)0xd2d1, (q15_t)0x12a4, (q15_t)0xd2d9, + (q15_t)0x129b, (q15_t)0xd2e2, (q15_t)0x1292, (q15_t)0xd2eb, (q15_t)0x128a, (q15_t)0xd2f4, (q15_t)0x1281, (q15_t)0xd2fd, + (q15_t)0x1278, (q15_t)0xd306, (q15_t)0x126f, (q15_t)0xd30f, (q15_t)0x1266, (q15_t)0xd318, (q15_t)0x125d, (q15_t)0xd321, + (q15_t)0x1255, (q15_t)0xd32a, (q15_t)0x124c, (q15_t)0xd333, (q15_t)0x1243, (q15_t)0xd33c, (q15_t)0x123a, (q15_t)0xd345, + (q15_t)0x1231, (q15_t)0xd34e, (q15_t)0x1229, (q15_t)0xd357, (q15_t)0x1220, (q15_t)0xd360, (q15_t)0x1217, (q15_t)0xd369, + (q15_t)0x120e, (q15_t)0xd372, (q15_t)0x1206, (q15_t)0xd37b, (q15_t)0x11fd, (q15_t)0xd384, (q15_t)0x11f4, (q15_t)0xd38d, + (q15_t)0x11eb, (q15_t)0xd396, (q15_t)0x11e3, (q15_t)0xd39f, (q15_t)0x11da, (q15_t)0xd3a8, (q15_t)0x11d1, (q15_t)0xd3b1, + (q15_t)0x11c9, (q15_t)0xd3ba, (q15_t)0x11c0, (q15_t)0xd3c3, (q15_t)0x11b7, (q15_t)0xd3cc, (q15_t)0x11af, (q15_t)0xd3d5, + (q15_t)0x11a6, (q15_t)0xd3df, (q15_t)0x119d, (q15_t)0xd3e8, (q15_t)0x1195, (q15_t)0xd3f1, (q15_t)0x118c, (q15_t)0xd3fa, + (q15_t)0x1183, (q15_t)0xd403, (q15_t)0x117b, (q15_t)0xd40c, (q15_t)0x1172, (q15_t)0xd415, (q15_t)0x1169, (q15_t)0xd41e, + (q15_t)0x1161, (q15_t)0xd428, (q15_t)0x1158, (q15_t)0xd431, (q15_t)0x1150, (q15_t)0xd43a, (q15_t)0x1147, (q15_t)0xd443, + (q15_t)0x113e, (q15_t)0xd44c, (q15_t)0x1136, (q15_t)0xd455, (q15_t)0x112d, (q15_t)0xd45f, (q15_t)0x1125, (q15_t)0xd468, + (q15_t)0x111c, (q15_t)0xd471, (q15_t)0x1114, (q15_t)0xd47a, (q15_t)0x110b, (q15_t)0xd483, (q15_t)0x1103, (q15_t)0xd48d, + (q15_t)0x10fa, (q15_t)0xd496, (q15_t)0x10f2, (q15_t)0xd49f, (q15_t)0x10e9, (q15_t)0xd4a8, (q15_t)0x10e0, (q15_t)0xd4b2, + (q15_t)0x10d8, (q15_t)0xd4bb, (q15_t)0x10d0, (q15_t)0xd4c4, (q15_t)0x10c7, (q15_t)0xd4cd, (q15_t)0x10bf, (q15_t)0xd4d7, + (q15_t)0x10b6, (q15_t)0xd4e0, (q15_t)0x10ae, (q15_t)0xd4e9, (q15_t)0x10a5, (q15_t)0xd4f3, (q15_t)0x109d, (q15_t)0xd4fc, + (q15_t)0x1094, (q15_t)0xd505, (q15_t)0x108c, (q15_t)0xd50e, (q15_t)0x1083, (q15_t)0xd518, (q15_t)0x107b, (q15_t)0xd521, + (q15_t)0x1073, (q15_t)0xd52a, (q15_t)0x106a, (q15_t)0xd534, (q15_t)0x1062, (q15_t)0xd53d, (q15_t)0x1059, (q15_t)0xd547, + (q15_t)0x1051, (q15_t)0xd550, (q15_t)0x1049, (q15_t)0xd559, (q15_t)0x1040, (q15_t)0xd563, (q15_t)0x1038, (q15_t)0xd56c, + (q15_t)0x1030, (q15_t)0xd575, (q15_t)0x1027, (q15_t)0xd57f, (q15_t)0x101f, (q15_t)0xd588, (q15_t)0x1016, (q15_t)0xd592, + (q15_t)0x100e, (q15_t)0xd59b, (q15_t)0x1006, (q15_t)0xd5a4, (q15_t)0xffe, (q15_t)0xd5ae, (q15_t)0xff5, (q15_t)0xd5b7, + (q15_t)0xfed, (q15_t)0xd5c1, (q15_t)0xfe5, (q15_t)0xd5ca, (q15_t)0xfdc, (q15_t)0xd5d4, (q15_t)0xfd4, (q15_t)0xd5dd, + (q15_t)0xfcc, (q15_t)0xd5e6, (q15_t)0xfc4, (q15_t)0xd5f0, (q15_t)0xfbb, (q15_t)0xd5f9, (q15_t)0xfb3, (q15_t)0xd603, + (q15_t)0xfab, (q15_t)0xd60c, (q15_t)0xfa3, (q15_t)0xd616, (q15_t)0xf9a, (q15_t)0xd61f, (q15_t)0xf92, (q15_t)0xd629, + (q15_t)0xf8a, (q15_t)0xd632, (q15_t)0xf82, (q15_t)0xd63c, (q15_t)0xf79, (q15_t)0xd645, (q15_t)0xf71, (q15_t)0xd64f, + (q15_t)0xf69, (q15_t)0xd659, (q15_t)0xf61, (q15_t)0xd662, (q15_t)0xf59, (q15_t)0xd66c, (q15_t)0xf51, (q15_t)0xd675, + (q15_t)0xf48, (q15_t)0xd67f, (q15_t)0xf40, (q15_t)0xd688, (q15_t)0xf38, (q15_t)0xd692, (q15_t)0xf30, (q15_t)0xd69b, + (q15_t)0xf28, (q15_t)0xd6a5, (q15_t)0xf20, (q15_t)0xd6af, (q15_t)0xf18, (q15_t)0xd6b8, (q15_t)0xf10, (q15_t)0xd6c2, + (q15_t)0xf07, (q15_t)0xd6cb, (q15_t)0xeff, (q15_t)0xd6d5, (q15_t)0xef7, (q15_t)0xd6df, (q15_t)0xeef, (q15_t)0xd6e8, + (q15_t)0xee7, (q15_t)0xd6f2, (q15_t)0xedf, (q15_t)0xd6fc, (q15_t)0xed7, (q15_t)0xd705, (q15_t)0xecf, (q15_t)0xd70f, + (q15_t)0xec7, (q15_t)0xd719, (q15_t)0xebf, (q15_t)0xd722, (q15_t)0xeb7, (q15_t)0xd72c, (q15_t)0xeaf, (q15_t)0xd736, + (q15_t)0xea7, (q15_t)0xd73f, (q15_t)0xe9f, (q15_t)0xd749, (q15_t)0xe97, (q15_t)0xd753, (q15_t)0xe8f, (q15_t)0xd75c, + (q15_t)0xe87, (q15_t)0xd766, (q15_t)0xe7f, (q15_t)0xd770, (q15_t)0xe77, (q15_t)0xd77a, (q15_t)0xe6f, (q15_t)0xd783, + (q15_t)0xe67, (q15_t)0xd78d, (q15_t)0xe5f, (q15_t)0xd797, (q15_t)0xe57, (q15_t)0xd7a0, (q15_t)0xe4f, (q15_t)0xd7aa, + (q15_t)0xe47, (q15_t)0xd7b4, (q15_t)0xe40, (q15_t)0xd7be, (q15_t)0xe38, (q15_t)0xd7c8, (q15_t)0xe30, (q15_t)0xd7d1, + (q15_t)0xe28, (q15_t)0xd7db, (q15_t)0xe20, (q15_t)0xd7e5, (q15_t)0xe18, (q15_t)0xd7ef, (q15_t)0xe10, (q15_t)0xd7f8, + (q15_t)0xe08, (q15_t)0xd802, (q15_t)0xe01, (q15_t)0xd80c, (q15_t)0xdf9, (q15_t)0xd816, (q15_t)0xdf1, (q15_t)0xd820, + (q15_t)0xde9, (q15_t)0xd82a, (q15_t)0xde1, (q15_t)0xd833, (q15_t)0xdd9, (q15_t)0xd83d, (q15_t)0xdd2, (q15_t)0xd847, + (q15_t)0xdca, (q15_t)0xd851, (q15_t)0xdc2, (q15_t)0xd85b, (q15_t)0xdba, (q15_t)0xd865, (q15_t)0xdb2, (q15_t)0xd86f, + (q15_t)0xdab, (q15_t)0xd878, (q15_t)0xda3, (q15_t)0xd882, (q15_t)0xd9b, (q15_t)0xd88c, (q15_t)0xd93, (q15_t)0xd896, + (q15_t)0xd8c, (q15_t)0xd8a0, (q15_t)0xd84, (q15_t)0xd8aa, (q15_t)0xd7c, (q15_t)0xd8b4, (q15_t)0xd75, (q15_t)0xd8be, + (q15_t)0xd6d, (q15_t)0xd8c8, (q15_t)0xd65, (q15_t)0xd8d2, (q15_t)0xd5d, (q15_t)0xd8dc, (q15_t)0xd56, (q15_t)0xd8e6, + (q15_t)0xd4e, (q15_t)0xd8ef, (q15_t)0xd46, (q15_t)0xd8f9, (q15_t)0xd3f, (q15_t)0xd903, (q15_t)0xd37, (q15_t)0xd90d, + (q15_t)0xd30, (q15_t)0xd917, (q15_t)0xd28, (q15_t)0xd921, (q15_t)0xd20, (q15_t)0xd92b, (q15_t)0xd19, (q15_t)0xd935, + (q15_t)0xd11, (q15_t)0xd93f, (q15_t)0xd09, (q15_t)0xd949, (q15_t)0xd02, (q15_t)0xd953, (q15_t)0xcfa, (q15_t)0xd95d, + (q15_t)0xcf3, (q15_t)0xd967, (q15_t)0xceb, (q15_t)0xd971, (q15_t)0xce3, (q15_t)0xd97b, (q15_t)0xcdc, (q15_t)0xd985, + (q15_t)0xcd4, (q15_t)0xd98f, (q15_t)0xccd, (q15_t)0xd99a, (q15_t)0xcc5, (q15_t)0xd9a4, (q15_t)0xcbe, (q15_t)0xd9ae, + (q15_t)0xcb6, (q15_t)0xd9b8, (q15_t)0xcaf, (q15_t)0xd9c2, (q15_t)0xca7, (q15_t)0xd9cc, (q15_t)0xca0, (q15_t)0xd9d6, + (q15_t)0xc98, (q15_t)0xd9e0, (q15_t)0xc91, (q15_t)0xd9ea, (q15_t)0xc89, (q15_t)0xd9f4, (q15_t)0xc82, (q15_t)0xd9fe, + (q15_t)0xc7a, (q15_t)0xda08, (q15_t)0xc73, (q15_t)0xda13, (q15_t)0xc6b, (q15_t)0xda1d, (q15_t)0xc64, (q15_t)0xda27, + (q15_t)0xc5d, (q15_t)0xda31, (q15_t)0xc55, (q15_t)0xda3b, (q15_t)0xc4e, (q15_t)0xda45, (q15_t)0xc46, (q15_t)0xda4f, + (q15_t)0xc3f, (q15_t)0xda5a, (q15_t)0xc38, (q15_t)0xda64, (q15_t)0xc30, (q15_t)0xda6e, (q15_t)0xc29, (q15_t)0xda78, + (q15_t)0xc21, (q15_t)0xda82, (q15_t)0xc1a, (q15_t)0xda8c, (q15_t)0xc13, (q15_t)0xda97, (q15_t)0xc0b, (q15_t)0xdaa1, + (q15_t)0xc04, (q15_t)0xdaab, (q15_t)0xbfd, (q15_t)0xdab5, (q15_t)0xbf5, (q15_t)0xdabf, (q15_t)0xbee, (q15_t)0xdaca, + (q15_t)0xbe7, (q15_t)0xdad4, (q15_t)0xbe0, (q15_t)0xdade, (q15_t)0xbd8, (q15_t)0xdae8, (q15_t)0xbd1, (q15_t)0xdaf3, + (q15_t)0xbca, (q15_t)0xdafd, (q15_t)0xbc2, (q15_t)0xdb07, (q15_t)0xbbb, (q15_t)0xdb11, (q15_t)0xbb4, (q15_t)0xdb1c, + (q15_t)0xbad, (q15_t)0xdb26, (q15_t)0xba5, (q15_t)0xdb30, (q15_t)0xb9e, (q15_t)0xdb3b, (q15_t)0xb97, (q15_t)0xdb45, + (q15_t)0xb90, (q15_t)0xdb4f, (q15_t)0xb89, (q15_t)0xdb59, (q15_t)0xb81, (q15_t)0xdb64, (q15_t)0xb7a, (q15_t)0xdb6e, + (q15_t)0xb73, (q15_t)0xdb78, (q15_t)0xb6c, (q15_t)0xdb83, (q15_t)0xb65, (q15_t)0xdb8d, (q15_t)0xb5e, (q15_t)0xdb97, + (q15_t)0xb56, (q15_t)0xdba2, (q15_t)0xb4f, (q15_t)0xdbac, (q15_t)0xb48, (q15_t)0xdbb6, (q15_t)0xb41, (q15_t)0xdbc1, + (q15_t)0xb3a, (q15_t)0xdbcb, (q15_t)0xb33, (q15_t)0xdbd5, (q15_t)0xb2c, (q15_t)0xdbe0, (q15_t)0xb25, (q15_t)0xdbea, + (q15_t)0xb1e, (q15_t)0xdbf5, (q15_t)0xb16, (q15_t)0xdbff, (q15_t)0xb0f, (q15_t)0xdc09, (q15_t)0xb08, (q15_t)0xdc14, + (q15_t)0xb01, (q15_t)0xdc1e, (q15_t)0xafa, (q15_t)0xdc29, (q15_t)0xaf3, (q15_t)0xdc33, (q15_t)0xaec, (q15_t)0xdc3d, + (q15_t)0xae5, (q15_t)0xdc48, (q15_t)0xade, (q15_t)0xdc52, (q15_t)0xad7, (q15_t)0xdc5d, (q15_t)0xad0, (q15_t)0xdc67, + (q15_t)0xac9, (q15_t)0xdc72, (q15_t)0xac2, (q15_t)0xdc7c, (q15_t)0xabb, (q15_t)0xdc86, (q15_t)0xab4, (q15_t)0xdc91, + (q15_t)0xaad, (q15_t)0xdc9b, (q15_t)0xaa6, (q15_t)0xdca6, (q15_t)0xa9f, (q15_t)0xdcb0, (q15_t)0xa99, (q15_t)0xdcbb, + (q15_t)0xa92, (q15_t)0xdcc5, (q15_t)0xa8b, (q15_t)0xdcd0, (q15_t)0xa84, (q15_t)0xdcda, (q15_t)0xa7d, (q15_t)0xdce5, + (q15_t)0xa76, (q15_t)0xdcef, (q15_t)0xa6f, (q15_t)0xdcfa, (q15_t)0xa68, (q15_t)0xdd04, (q15_t)0xa61, (q15_t)0xdd0f, + (q15_t)0xa5b, (q15_t)0xdd19, (q15_t)0xa54, (q15_t)0xdd24, (q15_t)0xa4d, (q15_t)0xdd2e, (q15_t)0xa46, (q15_t)0xdd39, + (q15_t)0xa3f, (q15_t)0xdd44, (q15_t)0xa38, (q15_t)0xdd4e, (q15_t)0xa32, (q15_t)0xdd59, (q15_t)0xa2b, (q15_t)0xdd63, + (q15_t)0xa24, (q15_t)0xdd6e, (q15_t)0xa1d, (q15_t)0xdd78, (q15_t)0xa16, (q15_t)0xdd83, (q15_t)0xa10, (q15_t)0xdd8e, + (q15_t)0xa09, (q15_t)0xdd98, (q15_t)0xa02, (q15_t)0xdda3, (q15_t)0x9fb, (q15_t)0xddad, (q15_t)0x9f5, (q15_t)0xddb8, + (q15_t)0x9ee, (q15_t)0xddc3, (q15_t)0x9e7, (q15_t)0xddcd, (q15_t)0x9e0, (q15_t)0xddd8, (q15_t)0x9da, (q15_t)0xdde2, + (q15_t)0x9d3, (q15_t)0xdded, (q15_t)0x9cc, (q15_t)0xddf8, (q15_t)0x9c6, (q15_t)0xde02, (q15_t)0x9bf, (q15_t)0xde0d, + (q15_t)0x9b8, (q15_t)0xde18, (q15_t)0x9b2, (q15_t)0xde22, (q15_t)0x9ab, (q15_t)0xde2d, (q15_t)0x9a4, (q15_t)0xde38, + (q15_t)0x99e, (q15_t)0xde42, (q15_t)0x997, (q15_t)0xde4d, (q15_t)0x991, (q15_t)0xde58, (q15_t)0x98a, (q15_t)0xde62, + (q15_t)0x983, (q15_t)0xde6d, (q15_t)0x97d, (q15_t)0xde78, (q15_t)0x976, (q15_t)0xde83, (q15_t)0x970, (q15_t)0xde8d, + (q15_t)0x969, (q15_t)0xde98, (q15_t)0x963, (q15_t)0xdea3, (q15_t)0x95c, (q15_t)0xdead, (q15_t)0x955, (q15_t)0xdeb8, + (q15_t)0x94f, (q15_t)0xdec3, (q15_t)0x948, (q15_t)0xdece, (q15_t)0x942, (q15_t)0xded8, (q15_t)0x93b, (q15_t)0xdee3, + (q15_t)0x935, (q15_t)0xdeee, (q15_t)0x92e, (q15_t)0xdef9, (q15_t)0x928, (q15_t)0xdf03, (q15_t)0x921, (q15_t)0xdf0e, + (q15_t)0x91b, (q15_t)0xdf19, (q15_t)0x915, (q15_t)0xdf24, (q15_t)0x90e, (q15_t)0xdf2f, (q15_t)0x908, (q15_t)0xdf39, + (q15_t)0x901, (q15_t)0xdf44, (q15_t)0x8fb, (q15_t)0xdf4f, (q15_t)0x8f4, (q15_t)0xdf5a, (q15_t)0x8ee, (q15_t)0xdf65, + (q15_t)0x8e8, (q15_t)0xdf6f, (q15_t)0x8e1, (q15_t)0xdf7a, (q15_t)0x8db, (q15_t)0xdf85, (q15_t)0x8d4, (q15_t)0xdf90, + (q15_t)0x8ce, (q15_t)0xdf9b, (q15_t)0x8c8, (q15_t)0xdfa5, (q15_t)0x8c1, (q15_t)0xdfb0, (q15_t)0x8bb, (q15_t)0xdfbb, + (q15_t)0x8b5, (q15_t)0xdfc6, (q15_t)0x8ae, (q15_t)0xdfd1, (q15_t)0x8a8, (q15_t)0xdfdc, (q15_t)0x8a2, (q15_t)0xdfe7, + (q15_t)0x89b, (q15_t)0xdff1, (q15_t)0x895, (q15_t)0xdffc, (q15_t)0x88f, (q15_t)0xe007, (q15_t)0x889, (q15_t)0xe012, + (q15_t)0x882, (q15_t)0xe01d, (q15_t)0x87c, (q15_t)0xe028, (q15_t)0x876, (q15_t)0xe033, (q15_t)0x870, (q15_t)0xe03e, + (q15_t)0x869, (q15_t)0xe049, (q15_t)0x863, (q15_t)0xe054, (q15_t)0x85d, (q15_t)0xe05e, (q15_t)0x857, (q15_t)0xe069, + (q15_t)0x850, (q15_t)0xe074, (q15_t)0x84a, (q15_t)0xe07f, (q15_t)0x844, (q15_t)0xe08a, (q15_t)0x83e, (q15_t)0xe095, + (q15_t)0x838, (q15_t)0xe0a0, (q15_t)0x832, (q15_t)0xe0ab, (q15_t)0x82b, (q15_t)0xe0b6, (q15_t)0x825, (q15_t)0xe0c1, + (q15_t)0x81f, (q15_t)0xe0cc, (q15_t)0x819, (q15_t)0xe0d7, (q15_t)0x813, (q15_t)0xe0e2, (q15_t)0x80d, (q15_t)0xe0ed, + (q15_t)0x807, (q15_t)0xe0f8, (q15_t)0x801, (q15_t)0xe103, (q15_t)0x7fb, (q15_t)0xe10e, (q15_t)0x7f5, (q15_t)0xe119, + (q15_t)0x7ee, (q15_t)0xe124, (q15_t)0x7e8, (q15_t)0xe12f, (q15_t)0x7e2, (q15_t)0xe13a, (q15_t)0x7dc, (q15_t)0xe145, + (q15_t)0x7d6, (q15_t)0xe150, (q15_t)0x7d0, (q15_t)0xe15b, (q15_t)0x7ca, (q15_t)0xe166, (q15_t)0x7c4, (q15_t)0xe171, + (q15_t)0x7be, (q15_t)0xe17c, (q15_t)0x7b8, (q15_t)0xe187, (q15_t)0x7b2, (q15_t)0xe192, (q15_t)0x7ac, (q15_t)0xe19d, + (q15_t)0x7a6, (q15_t)0xe1a8, (q15_t)0x7a0, (q15_t)0xe1b3, (q15_t)0x79a, (q15_t)0xe1be, (q15_t)0x795, (q15_t)0xe1ca, + (q15_t)0x78f, (q15_t)0xe1d5, (q15_t)0x789, (q15_t)0xe1e0, (q15_t)0x783, (q15_t)0xe1eb, (q15_t)0x77d, (q15_t)0xe1f6, + (q15_t)0x777, (q15_t)0xe201, (q15_t)0x771, (q15_t)0xe20c, (q15_t)0x76b, (q15_t)0xe217, (q15_t)0x765, (q15_t)0xe222, + (q15_t)0x75f, (q15_t)0xe22d, (q15_t)0x75a, (q15_t)0xe239, (q15_t)0x754, (q15_t)0xe244, (q15_t)0x74e, (q15_t)0xe24f, + (q15_t)0x748, (q15_t)0xe25a, (q15_t)0x742, (q15_t)0xe265, (q15_t)0x73d, (q15_t)0xe270, (q15_t)0x737, (q15_t)0xe27b, + (q15_t)0x731, (q15_t)0xe287, (q15_t)0x72b, (q15_t)0xe292, (q15_t)0x725, (q15_t)0xe29d, (q15_t)0x720, (q15_t)0xe2a8, + (q15_t)0x71a, (q15_t)0xe2b3, (q15_t)0x714, (q15_t)0xe2be, (q15_t)0x70e, (q15_t)0xe2ca, (q15_t)0x709, (q15_t)0xe2d5, + (q15_t)0x703, (q15_t)0xe2e0, (q15_t)0x6fd, (q15_t)0xe2eb, (q15_t)0x6f7, (q15_t)0xe2f6, (q15_t)0x6f2, (q15_t)0xe301, + (q15_t)0x6ec, (q15_t)0xe30d, (q15_t)0x6e6, (q15_t)0xe318, (q15_t)0x6e1, (q15_t)0xe323, (q15_t)0x6db, (q15_t)0xe32e, + (q15_t)0x6d5, (q15_t)0xe33a, (q15_t)0x6d0, (q15_t)0xe345, (q15_t)0x6ca, (q15_t)0xe350, (q15_t)0x6c5, (q15_t)0xe35b, + (q15_t)0x6bf, (q15_t)0xe367, (q15_t)0x6b9, (q15_t)0xe372, (q15_t)0x6b4, (q15_t)0xe37d, (q15_t)0x6ae, (q15_t)0xe388, + (q15_t)0x6a8, (q15_t)0xe394, (q15_t)0x6a3, (q15_t)0xe39f, (q15_t)0x69d, (q15_t)0xe3aa, (q15_t)0x698, (q15_t)0xe3b5, + (q15_t)0x692, (q15_t)0xe3c1, (q15_t)0x68d, (q15_t)0xe3cc, (q15_t)0x687, (q15_t)0xe3d7, (q15_t)0x682, (q15_t)0xe3e2, + (q15_t)0x67c, (q15_t)0xe3ee, (q15_t)0x677, (q15_t)0xe3f9, (q15_t)0x671, (q15_t)0xe404, (q15_t)0x66c, (q15_t)0xe410, + (q15_t)0x666, (q15_t)0xe41b, (q15_t)0x661, (q15_t)0xe426, (q15_t)0x65b, (q15_t)0xe432, (q15_t)0x656, (q15_t)0xe43d, + (q15_t)0x650, (q15_t)0xe448, (q15_t)0x64b, (q15_t)0xe454, (q15_t)0x645, (q15_t)0xe45f, (q15_t)0x640, (q15_t)0xe46a, + (q15_t)0x63b, (q15_t)0xe476, (q15_t)0x635, (q15_t)0xe481, (q15_t)0x630, (q15_t)0xe48c, (q15_t)0x62a, (q15_t)0xe498, + (q15_t)0x625, (q15_t)0xe4a3, (q15_t)0x620, (q15_t)0xe4ae, (q15_t)0x61a, (q15_t)0xe4ba, (q15_t)0x615, (q15_t)0xe4c5, + (q15_t)0x610, (q15_t)0xe4d0, (q15_t)0x60a, (q15_t)0xe4dc, (q15_t)0x605, (q15_t)0xe4e7, (q15_t)0x600, (q15_t)0xe4f3, + (q15_t)0x5fa, (q15_t)0xe4fe, (q15_t)0x5f5, (q15_t)0xe509, (q15_t)0x5f0, (q15_t)0xe515, (q15_t)0x5ea, (q15_t)0xe520, + (q15_t)0x5e5, (q15_t)0xe52c, (q15_t)0x5e0, (q15_t)0xe537, (q15_t)0x5db, (q15_t)0xe542, (q15_t)0x5d5, (q15_t)0xe54e, + (q15_t)0x5d0, (q15_t)0xe559, (q15_t)0x5cb, (q15_t)0xe565, (q15_t)0x5c6, (q15_t)0xe570, (q15_t)0x5c1, (q15_t)0xe57c, + (q15_t)0x5bb, (q15_t)0xe587, (q15_t)0x5b6, (q15_t)0xe592, (q15_t)0x5b1, (q15_t)0xe59e, (q15_t)0x5ac, (q15_t)0xe5a9, + (q15_t)0x5a7, (q15_t)0xe5b5, (q15_t)0x5a1, (q15_t)0xe5c0, (q15_t)0x59c, (q15_t)0xe5cc, (q15_t)0x597, (q15_t)0xe5d7, + (q15_t)0x592, (q15_t)0xe5e3, (q15_t)0x58d, (q15_t)0xe5ee, (q15_t)0x588, (q15_t)0xe5fa, (q15_t)0x583, (q15_t)0xe605, + (q15_t)0x57e, (q15_t)0xe611, (q15_t)0x578, (q15_t)0xe61c, (q15_t)0x573, (q15_t)0xe628, (q15_t)0x56e, (q15_t)0xe633, + (q15_t)0x569, (q15_t)0xe63f, (q15_t)0x564, (q15_t)0xe64a, (q15_t)0x55f, (q15_t)0xe656, (q15_t)0x55a, (q15_t)0xe661, + (q15_t)0x555, (q15_t)0xe66d, (q15_t)0x550, (q15_t)0xe678, (q15_t)0x54b, (q15_t)0xe684, (q15_t)0x546, (q15_t)0xe68f, + (q15_t)0x541, (q15_t)0xe69b, (q15_t)0x53c, (q15_t)0xe6a6, (q15_t)0x537, (q15_t)0xe6b2, (q15_t)0x532, (q15_t)0xe6bd, + (q15_t)0x52d, (q15_t)0xe6c9, (q15_t)0x528, (q15_t)0xe6d4, (q15_t)0x523, (q15_t)0xe6e0, (q15_t)0x51e, (q15_t)0xe6ec, + (q15_t)0x51a, (q15_t)0xe6f7, (q15_t)0x515, (q15_t)0xe703, (q15_t)0x510, (q15_t)0xe70e, (q15_t)0x50b, (q15_t)0xe71a, + (q15_t)0x506, (q15_t)0xe725, (q15_t)0x501, (q15_t)0xe731, (q15_t)0x4fc, (q15_t)0xe73d, (q15_t)0x4f7, (q15_t)0xe748, + (q15_t)0x4f2, (q15_t)0xe754, (q15_t)0x4ee, (q15_t)0xe75f, (q15_t)0x4e9, (q15_t)0xe76b, (q15_t)0x4e4, (q15_t)0xe777, + (q15_t)0x4df, (q15_t)0xe782, (q15_t)0x4da, (q15_t)0xe78e, (q15_t)0x4d6, (q15_t)0xe799, (q15_t)0x4d1, (q15_t)0xe7a5, + (q15_t)0x4cc, (q15_t)0xe7b1, (q15_t)0x4c7, (q15_t)0xe7bc, (q15_t)0x4c2, (q15_t)0xe7c8, (q15_t)0x4be, (q15_t)0xe7d3, + (q15_t)0x4b9, (q15_t)0xe7df, (q15_t)0x4b4, (q15_t)0xe7eb, (q15_t)0x4b0, (q15_t)0xe7f6, (q15_t)0x4ab, (q15_t)0xe802, + (q15_t)0x4a6, (q15_t)0xe80e, (q15_t)0x4a1, (q15_t)0xe819, (q15_t)0x49d, (q15_t)0xe825, (q15_t)0x498, (q15_t)0xe831, + (q15_t)0x493, (q15_t)0xe83c, (q15_t)0x48f, (q15_t)0xe848, (q15_t)0x48a, (q15_t)0xe854, (q15_t)0x485, (q15_t)0xe85f, + (q15_t)0x481, (q15_t)0xe86b, (q15_t)0x47c, (q15_t)0xe877, (q15_t)0x478, (q15_t)0xe882, (q15_t)0x473, (q15_t)0xe88e, + (q15_t)0x46e, (q15_t)0xe89a, (q15_t)0x46a, (q15_t)0xe8a5, (q15_t)0x465, (q15_t)0xe8b1, (q15_t)0x461, (q15_t)0xe8bd, + (q15_t)0x45c, (q15_t)0xe8c9, (q15_t)0x457, (q15_t)0xe8d4, (q15_t)0x453, (q15_t)0xe8e0, (q15_t)0x44e, (q15_t)0xe8ec, + (q15_t)0x44a, (q15_t)0xe8f7, (q15_t)0x445, (q15_t)0xe903, (q15_t)0x441, (q15_t)0xe90f, (q15_t)0x43c, (q15_t)0xe91b, + (q15_t)0x438, (q15_t)0xe926, (q15_t)0x433, (q15_t)0xe932, (q15_t)0x42f, (q15_t)0xe93e, (q15_t)0x42a, (q15_t)0xe94a, + (q15_t)0x426, (q15_t)0xe955, (q15_t)0x422, (q15_t)0xe961, (q15_t)0x41d, (q15_t)0xe96d, (q15_t)0x419, (q15_t)0xe979, + (q15_t)0x414, (q15_t)0xe984, (q15_t)0x410, (q15_t)0xe990, (q15_t)0x40b, (q15_t)0xe99c, (q15_t)0x407, (q15_t)0xe9a8, + (q15_t)0x403, (q15_t)0xe9b4, (q15_t)0x3fe, (q15_t)0xe9bf, (q15_t)0x3fa, (q15_t)0xe9cb, (q15_t)0x3f6, (q15_t)0xe9d7, + (q15_t)0x3f1, (q15_t)0xe9e3, (q15_t)0x3ed, (q15_t)0xe9ee, (q15_t)0x3e9, (q15_t)0xe9fa, (q15_t)0x3e4, (q15_t)0xea06, + (q15_t)0x3e0, (q15_t)0xea12, (q15_t)0x3dc, (q15_t)0xea1e, (q15_t)0x3d7, (q15_t)0xea29, (q15_t)0x3d3, (q15_t)0xea35, + (q15_t)0x3cf, (q15_t)0xea41, (q15_t)0x3ca, (q15_t)0xea4d, (q15_t)0x3c6, (q15_t)0xea59, (q15_t)0x3c2, (q15_t)0xea65, + (q15_t)0x3be, (q15_t)0xea70, (q15_t)0x3ba, (q15_t)0xea7c, (q15_t)0x3b5, (q15_t)0xea88, (q15_t)0x3b1, (q15_t)0xea94, + (q15_t)0x3ad, (q15_t)0xeaa0, (q15_t)0x3a9, (q15_t)0xeaac, (q15_t)0x3a5, (q15_t)0xeab7, (q15_t)0x3a0, (q15_t)0xeac3, + (q15_t)0x39c, (q15_t)0xeacf, (q15_t)0x398, (q15_t)0xeadb, (q15_t)0x394, (q15_t)0xeae7, (q15_t)0x390, (q15_t)0xeaf3, + (q15_t)0x38c, (q15_t)0xeaff, (q15_t)0x387, (q15_t)0xeb0a, (q15_t)0x383, (q15_t)0xeb16, (q15_t)0x37f, (q15_t)0xeb22, + (q15_t)0x37b, (q15_t)0xeb2e, (q15_t)0x377, (q15_t)0xeb3a, (q15_t)0x373, (q15_t)0xeb46, (q15_t)0x36f, (q15_t)0xeb52, + (q15_t)0x36b, (q15_t)0xeb5e, (q15_t)0x367, (q15_t)0xeb6a, (q15_t)0x363, (q15_t)0xeb75, (q15_t)0x35f, (q15_t)0xeb81, + (q15_t)0x35b, (q15_t)0xeb8d, (q15_t)0x357, (q15_t)0xeb99, (q15_t)0x353, (q15_t)0xeba5, (q15_t)0x34f, (q15_t)0xebb1, + (q15_t)0x34b, (q15_t)0xebbd, (q15_t)0x347, (q15_t)0xebc9, (q15_t)0x343, (q15_t)0xebd5, (q15_t)0x33f, (q15_t)0xebe1, + (q15_t)0x33b, (q15_t)0xebed, (q15_t)0x337, (q15_t)0xebf9, (q15_t)0x333, (q15_t)0xec05, (q15_t)0x32f, (q15_t)0xec10, + (q15_t)0x32b, (q15_t)0xec1c, (q15_t)0x327, (q15_t)0xec28, (q15_t)0x323, (q15_t)0xec34, (q15_t)0x320, (q15_t)0xec40, + (q15_t)0x31c, (q15_t)0xec4c, (q15_t)0x318, (q15_t)0xec58, (q15_t)0x314, (q15_t)0xec64, (q15_t)0x310, (q15_t)0xec70, + (q15_t)0x30c, (q15_t)0xec7c, (q15_t)0x308, (q15_t)0xec88, (q15_t)0x305, (q15_t)0xec94, (q15_t)0x301, (q15_t)0xeca0, + (q15_t)0x2fd, (q15_t)0xecac, (q15_t)0x2f9, (q15_t)0xecb8, (q15_t)0x2f5, (q15_t)0xecc4, (q15_t)0x2f2, (q15_t)0xecd0, + (q15_t)0x2ee, (q15_t)0xecdc, (q15_t)0x2ea, (q15_t)0xece8, (q15_t)0x2e6, (q15_t)0xecf4, (q15_t)0x2e3, (q15_t)0xed00, + (q15_t)0x2df, (q15_t)0xed0c, (q15_t)0x2db, (q15_t)0xed18, (q15_t)0x2d8, (q15_t)0xed24, (q15_t)0x2d4, (q15_t)0xed30, + (q15_t)0x2d0, (q15_t)0xed3c, (q15_t)0x2cc, (q15_t)0xed48, (q15_t)0x2c9, (q15_t)0xed54, (q15_t)0x2c5, (q15_t)0xed60, + (q15_t)0x2c1, (q15_t)0xed6c, (q15_t)0x2be, (q15_t)0xed78, (q15_t)0x2ba, (q15_t)0xed84, (q15_t)0x2b7, (q15_t)0xed90, + (q15_t)0x2b3, (q15_t)0xed9c, (q15_t)0x2af, (q15_t)0xeda8, (q15_t)0x2ac, (q15_t)0xedb4, (q15_t)0x2a8, (q15_t)0xedc0, + (q15_t)0x2a5, (q15_t)0xedcc, (q15_t)0x2a1, (q15_t)0xedd8, (q15_t)0x29d, (q15_t)0xede4, (q15_t)0x29a, (q15_t)0xedf0, + (q15_t)0x296, (q15_t)0xedfc, (q15_t)0x293, (q15_t)0xee09, (q15_t)0x28f, (q15_t)0xee15, (q15_t)0x28c, (q15_t)0xee21, + (q15_t)0x288, (q15_t)0xee2d, (q15_t)0x285, (q15_t)0xee39, (q15_t)0x281, (q15_t)0xee45, (q15_t)0x27e, (q15_t)0xee51, + (q15_t)0x27a, (q15_t)0xee5d, (q15_t)0x277, (q15_t)0xee69, (q15_t)0x273, (q15_t)0xee75, (q15_t)0x270, (q15_t)0xee81, + (q15_t)0x26d, (q15_t)0xee8d, (q15_t)0x269, (q15_t)0xee99, (q15_t)0x266, (q15_t)0xeea6, (q15_t)0x262, (q15_t)0xeeb2, + (q15_t)0x25f, (q15_t)0xeebe, (q15_t)0x25c, (q15_t)0xeeca, (q15_t)0x258, (q15_t)0xeed6, (q15_t)0x255, (q15_t)0xeee2, + (q15_t)0x251, (q15_t)0xeeee, (q15_t)0x24e, (q15_t)0xeefa, (q15_t)0x24b, (q15_t)0xef06, (q15_t)0x247, (q15_t)0xef13, + (q15_t)0x244, (q15_t)0xef1f, (q15_t)0x241, (q15_t)0xef2b, (q15_t)0x23e, (q15_t)0xef37, (q15_t)0x23a, (q15_t)0xef43, + (q15_t)0x237, (q15_t)0xef4f, (q15_t)0x234, (q15_t)0xef5b, (q15_t)0x230, (q15_t)0xef67, (q15_t)0x22d, (q15_t)0xef74, + (q15_t)0x22a, (q15_t)0xef80, (q15_t)0x227, (q15_t)0xef8c, (q15_t)0x223, (q15_t)0xef98, (q15_t)0x220, (q15_t)0xefa4, + (q15_t)0x21d, (q15_t)0xefb0, (q15_t)0x21a, (q15_t)0xefbc, (q15_t)0x217, (q15_t)0xefc9, (q15_t)0x213, (q15_t)0xefd5, + (q15_t)0x210, (q15_t)0xefe1, (q15_t)0x20d, (q15_t)0xefed, (q15_t)0x20a, (q15_t)0xeff9, (q15_t)0x207, (q15_t)0xf005, + (q15_t)0x204, (q15_t)0xf012, (q15_t)0x201, (q15_t)0xf01e, (q15_t)0x1fd, (q15_t)0xf02a, (q15_t)0x1fa, (q15_t)0xf036, + (q15_t)0x1f7, (q15_t)0xf042, (q15_t)0x1f4, (q15_t)0xf04e, (q15_t)0x1f1, (q15_t)0xf05b, (q15_t)0x1ee, (q15_t)0xf067, + (q15_t)0x1eb, (q15_t)0xf073, (q15_t)0x1e8, (q15_t)0xf07f, (q15_t)0x1e5, (q15_t)0xf08b, (q15_t)0x1e2, (q15_t)0xf098, + (q15_t)0x1df, (q15_t)0xf0a4, (q15_t)0x1dc, (q15_t)0xf0b0, (q15_t)0x1d9, (q15_t)0xf0bc, (q15_t)0x1d6, (q15_t)0xf0c8, + (q15_t)0x1d3, (q15_t)0xf0d5, (q15_t)0x1d0, (q15_t)0xf0e1, (q15_t)0x1cd, (q15_t)0xf0ed, (q15_t)0x1ca, (q15_t)0xf0f9, + (q15_t)0x1c7, (q15_t)0xf105, (q15_t)0x1c4, (q15_t)0xf112, (q15_t)0x1c1, (q15_t)0xf11e, (q15_t)0x1be, (q15_t)0xf12a, + (q15_t)0x1bb, (q15_t)0xf136, (q15_t)0x1b8, (q15_t)0xf143, (q15_t)0x1b6, (q15_t)0xf14f, (q15_t)0x1b3, (q15_t)0xf15b, + (q15_t)0x1b0, (q15_t)0xf167, (q15_t)0x1ad, (q15_t)0xf174, (q15_t)0x1aa, (q15_t)0xf180, (q15_t)0x1a7, (q15_t)0xf18c, + (q15_t)0x1a4, (q15_t)0xf198, (q15_t)0x1a2, (q15_t)0xf1a4, (q15_t)0x19f, (q15_t)0xf1b1, (q15_t)0x19c, (q15_t)0xf1bd, + (q15_t)0x199, (q15_t)0xf1c9, (q15_t)0x196, (q15_t)0xf1d5, (q15_t)0x194, (q15_t)0xf1e2, (q15_t)0x191, (q15_t)0xf1ee, + (q15_t)0x18e, (q15_t)0xf1fa, (q15_t)0x18b, (q15_t)0xf207, (q15_t)0x189, (q15_t)0xf213, (q15_t)0x186, (q15_t)0xf21f, + (q15_t)0x183, (q15_t)0xf22b, (q15_t)0x180, (q15_t)0xf238, (q15_t)0x17e, (q15_t)0xf244, (q15_t)0x17b, (q15_t)0xf250, + (q15_t)0x178, (q15_t)0xf25c, (q15_t)0x176, (q15_t)0xf269, (q15_t)0x173, (q15_t)0xf275, (q15_t)0x170, (q15_t)0xf281, + (q15_t)0x16e, (q15_t)0xf28e, (q15_t)0x16b, (q15_t)0xf29a, (q15_t)0x168, (q15_t)0xf2a6, (q15_t)0x166, (q15_t)0xf2b2, + (q15_t)0x163, (q15_t)0xf2bf, (q15_t)0x161, (q15_t)0xf2cb, (q15_t)0x15e, (q15_t)0xf2d7, (q15_t)0x15b, (q15_t)0xf2e4, + (q15_t)0x159, (q15_t)0xf2f0, (q15_t)0x156, (q15_t)0xf2fc, (q15_t)0x154, (q15_t)0xf308, (q15_t)0x151, (q15_t)0xf315, + (q15_t)0x14f, (q15_t)0xf321, (q15_t)0x14c, (q15_t)0xf32d, (q15_t)0x14a, (q15_t)0xf33a, (q15_t)0x147, (q15_t)0xf346, + (q15_t)0x145, (q15_t)0xf352, (q15_t)0x142, (q15_t)0xf35f, (q15_t)0x140, (q15_t)0xf36b, (q15_t)0x13d, (q15_t)0xf377, + (q15_t)0x13b, (q15_t)0xf384, (q15_t)0x138, (q15_t)0xf390, (q15_t)0x136, (q15_t)0xf39c, (q15_t)0x134, (q15_t)0xf3a9, + (q15_t)0x131, (q15_t)0xf3b5, (q15_t)0x12f, (q15_t)0xf3c1, (q15_t)0x12c, (q15_t)0xf3ce, (q15_t)0x12a, (q15_t)0xf3da, + (q15_t)0x128, (q15_t)0xf3e6, (q15_t)0x125, (q15_t)0xf3f3, (q15_t)0x123, (q15_t)0xf3ff, (q15_t)0x120, (q15_t)0xf40b, + (q15_t)0x11e, (q15_t)0xf418, (q15_t)0x11c, (q15_t)0xf424, (q15_t)0x119, (q15_t)0xf430, (q15_t)0x117, (q15_t)0xf43d, + (q15_t)0x115, (q15_t)0xf449, (q15_t)0x113, (q15_t)0xf455, (q15_t)0x110, (q15_t)0xf462, (q15_t)0x10e, (q15_t)0xf46e, + (q15_t)0x10c, (q15_t)0xf47b, (q15_t)0x109, (q15_t)0xf487, (q15_t)0x107, (q15_t)0xf493, (q15_t)0x105, (q15_t)0xf4a0, + (q15_t)0x103, (q15_t)0xf4ac, (q15_t)0x100, (q15_t)0xf4b8, (q15_t)0xfe, (q15_t)0xf4c5, (q15_t)0xfc, (q15_t)0xf4d1, + (q15_t)0xfa, (q15_t)0xf4dd, (q15_t)0xf8, (q15_t)0xf4ea, (q15_t)0xf6, (q15_t)0xf4f6, (q15_t)0xf3, (q15_t)0xf503, + (q15_t)0xf1, (q15_t)0xf50f, (q15_t)0xef, (q15_t)0xf51b, (q15_t)0xed, (q15_t)0xf528, (q15_t)0xeb, (q15_t)0xf534, + (q15_t)0xe9, (q15_t)0xf540, (q15_t)0xe7, (q15_t)0xf54d, (q15_t)0xe4, (q15_t)0xf559, (q15_t)0xe2, (q15_t)0xf566, + (q15_t)0xe0, (q15_t)0xf572, (q15_t)0xde, (q15_t)0xf57e, (q15_t)0xdc, (q15_t)0xf58b, (q15_t)0xda, (q15_t)0xf597, + (q15_t)0xd8, (q15_t)0xf5a4, (q15_t)0xd6, (q15_t)0xf5b0, (q15_t)0xd4, (q15_t)0xf5bc, (q15_t)0xd2, (q15_t)0xf5c9, + (q15_t)0xd0, (q15_t)0xf5d5, (q15_t)0xce, (q15_t)0xf5e2, (q15_t)0xcc, (q15_t)0xf5ee, (q15_t)0xca, (q15_t)0xf5fa, + (q15_t)0xc8, (q15_t)0xf607, (q15_t)0xc6, (q15_t)0xf613, (q15_t)0xc4, (q15_t)0xf620, (q15_t)0xc2, (q15_t)0xf62c, + (q15_t)0xc0, (q15_t)0xf639, (q15_t)0xbe, (q15_t)0xf645, (q15_t)0xbd, (q15_t)0xf651, (q15_t)0xbb, (q15_t)0xf65e, + (q15_t)0xb9, (q15_t)0xf66a, (q15_t)0xb7, (q15_t)0xf677, (q15_t)0xb5, (q15_t)0xf683, (q15_t)0xb3, (q15_t)0xf690, + (q15_t)0xb1, (q15_t)0xf69c, (q15_t)0xaf, (q15_t)0xf6a8, (q15_t)0xae, (q15_t)0xf6b5, (q15_t)0xac, (q15_t)0xf6c1, + (q15_t)0xaa, (q15_t)0xf6ce, (q15_t)0xa8, (q15_t)0xf6da, (q15_t)0xa6, (q15_t)0xf6e7, (q15_t)0xa5, (q15_t)0xf6f3, + (q15_t)0xa3, (q15_t)0xf6ff, (q15_t)0xa1, (q15_t)0xf70c, (q15_t)0x9f, (q15_t)0xf718, (q15_t)0x9e, (q15_t)0xf725, + (q15_t)0x9c, (q15_t)0xf731, (q15_t)0x9a, (q15_t)0xf73e, (q15_t)0x98, (q15_t)0xf74a, (q15_t)0x97, (q15_t)0xf757, + (q15_t)0x95, (q15_t)0xf763, (q15_t)0x93, (q15_t)0xf76f, (q15_t)0x92, (q15_t)0xf77c, (q15_t)0x90, (q15_t)0xf788, + (q15_t)0x8e, (q15_t)0xf795, (q15_t)0x8d, (q15_t)0xf7a1, (q15_t)0x8b, (q15_t)0xf7ae, (q15_t)0x89, (q15_t)0xf7ba, + (q15_t)0x88, (q15_t)0xf7c7, (q15_t)0x86, (q15_t)0xf7d3, (q15_t)0x85, (q15_t)0xf7e0, (q15_t)0x83, (q15_t)0xf7ec, + (q15_t)0x81, (q15_t)0xf7f9, (q15_t)0x80, (q15_t)0xf805, (q15_t)0x7e, (q15_t)0xf811, (q15_t)0x7d, (q15_t)0xf81e, + (q15_t)0x7b, (q15_t)0xf82a, (q15_t)0x7a, (q15_t)0xf837, (q15_t)0x78, (q15_t)0xf843, (q15_t)0x77, (q15_t)0xf850, + (q15_t)0x75, (q15_t)0xf85c, (q15_t)0x74, (q15_t)0xf869, (q15_t)0x72, (q15_t)0xf875, (q15_t)0x71, (q15_t)0xf882, + (q15_t)0x6f, (q15_t)0xf88e, (q15_t)0x6e, (q15_t)0xf89b, (q15_t)0x6c, (q15_t)0xf8a7, (q15_t)0x6b, (q15_t)0xf8b4, + (q15_t)0x69, (q15_t)0xf8c0, (q15_t)0x68, (q15_t)0xf8cd, (q15_t)0x67, (q15_t)0xf8d9, (q15_t)0x65, (q15_t)0xf8e6, + (q15_t)0x64, (q15_t)0xf8f2, (q15_t)0x62, (q15_t)0xf8ff, (q15_t)0x61, (q15_t)0xf90b, (q15_t)0x60, (q15_t)0xf918, + (q15_t)0x5e, (q15_t)0xf924, (q15_t)0x5d, (q15_t)0xf931, (q15_t)0x5c, (q15_t)0xf93d, (q15_t)0x5a, (q15_t)0xf94a, + (q15_t)0x59, (q15_t)0xf956, (q15_t)0x58, (q15_t)0xf963, (q15_t)0x56, (q15_t)0xf96f, (q15_t)0x55, (q15_t)0xf97c, + (q15_t)0x54, (q15_t)0xf988, (q15_t)0x53, (q15_t)0xf995, (q15_t)0x51, (q15_t)0xf9a1, (q15_t)0x50, (q15_t)0xf9ae, + (q15_t)0x4f, (q15_t)0xf9ba, (q15_t)0x4e, (q15_t)0xf9c7, (q15_t)0x4c, (q15_t)0xf9d3, (q15_t)0x4b, (q15_t)0xf9e0, + (q15_t)0x4a, (q15_t)0xf9ec, (q15_t)0x49, (q15_t)0xf9f9, (q15_t)0x48, (q15_t)0xfa05, (q15_t)0x47, (q15_t)0xfa12, + (q15_t)0x45, (q15_t)0xfa1e, (q15_t)0x44, (q15_t)0xfa2b, (q15_t)0x43, (q15_t)0xfa37, (q15_t)0x42, (q15_t)0xfa44, + (q15_t)0x41, (q15_t)0xfa50, (q15_t)0x40, (q15_t)0xfa5d, (q15_t)0x3f, (q15_t)0xfa69, (q15_t)0x3d, (q15_t)0xfa76, + (q15_t)0x3c, (q15_t)0xfa82, (q15_t)0x3b, (q15_t)0xfa8f, (q15_t)0x3a, (q15_t)0xfa9b, (q15_t)0x39, (q15_t)0xfaa8, + (q15_t)0x38, (q15_t)0xfab4, (q15_t)0x37, (q15_t)0xfac1, (q15_t)0x36, (q15_t)0xfacd, (q15_t)0x35, (q15_t)0xfada, + (q15_t)0x34, (q15_t)0xfae6, (q15_t)0x33, (q15_t)0xfaf3, (q15_t)0x32, (q15_t)0xfb00, (q15_t)0x31, (q15_t)0xfb0c, + (q15_t)0x30, (q15_t)0xfb19, (q15_t)0x2f, (q15_t)0xfb25, (q15_t)0x2e, (q15_t)0xfb32, (q15_t)0x2d, (q15_t)0xfb3e, + (q15_t)0x2c, (q15_t)0xfb4b, (q15_t)0x2b, (q15_t)0xfb57, (q15_t)0x2b, (q15_t)0xfb64, (q15_t)0x2a, (q15_t)0xfb70, + (q15_t)0x29, (q15_t)0xfb7d, (q15_t)0x28, (q15_t)0xfb89, (q15_t)0x27, (q15_t)0xfb96, (q15_t)0x26, (q15_t)0xfba2, + (q15_t)0x25, (q15_t)0xfbaf, (q15_t)0x24, (q15_t)0xfbbc, (q15_t)0x24, (q15_t)0xfbc8, (q15_t)0x23, (q15_t)0xfbd5, + (q15_t)0x22, (q15_t)0xfbe1, (q15_t)0x21, (q15_t)0xfbee, (q15_t)0x20, (q15_t)0xfbfa, (q15_t)0x20, (q15_t)0xfc07, + (q15_t)0x1f, (q15_t)0xfc13, (q15_t)0x1e, (q15_t)0xfc20, (q15_t)0x1d, (q15_t)0xfc2c, (q15_t)0x1d, (q15_t)0xfc39, + (q15_t)0x1c, (q15_t)0xfc45, (q15_t)0x1b, (q15_t)0xfc52, (q15_t)0x1a, (q15_t)0xfc5f, (q15_t)0x1a, (q15_t)0xfc6b, + (q15_t)0x19, (q15_t)0xfc78, (q15_t)0x18, (q15_t)0xfc84, (q15_t)0x18, (q15_t)0xfc91, (q15_t)0x17, (q15_t)0xfc9d, + (q15_t)0x16, (q15_t)0xfcaa, (q15_t)0x16, (q15_t)0xfcb6, (q15_t)0x15, (q15_t)0xfcc3, (q15_t)0x14, (q15_t)0xfcd0, + (q15_t)0x14, (q15_t)0xfcdc, (q15_t)0x13, (q15_t)0xfce9, (q15_t)0x13, (q15_t)0xfcf5, (q15_t)0x12, (q15_t)0xfd02, + (q15_t)0x11, (q15_t)0xfd0e, (q15_t)0x11, (q15_t)0xfd1b, (q15_t)0x10, (q15_t)0xfd27, (q15_t)0x10, (q15_t)0xfd34, + (q15_t)0xf, (q15_t)0xfd40, (q15_t)0xf, (q15_t)0xfd4d, (q15_t)0xe, (q15_t)0xfd5a, (q15_t)0xe, (q15_t)0xfd66, + (q15_t)0xd, (q15_t)0xfd73, (q15_t)0xd, (q15_t)0xfd7f, (q15_t)0xc, (q15_t)0xfd8c, (q15_t)0xc, (q15_t)0xfd98, + (q15_t)0xb, (q15_t)0xfda5, (q15_t)0xb, (q15_t)0xfdb2, (q15_t)0xa, (q15_t)0xfdbe, (q15_t)0xa, (q15_t)0xfdcb, + (q15_t)0x9, (q15_t)0xfdd7, (q15_t)0x9, (q15_t)0xfde4, (q15_t)0x9, (q15_t)0xfdf0, (q15_t)0x8, (q15_t)0xfdfd, + (q15_t)0x8, (q15_t)0xfe09, (q15_t)0x7, (q15_t)0xfe16, (q15_t)0x7, (q15_t)0xfe23, (q15_t)0x7, (q15_t)0xfe2f, + (q15_t)0x6, (q15_t)0xfe3c, (q15_t)0x6, (q15_t)0xfe48, (q15_t)0x6, (q15_t)0xfe55, (q15_t)0x5, (q15_t)0xfe61, + (q15_t)0x5, (q15_t)0xfe6e, (q15_t)0x5, (q15_t)0xfe7a, (q15_t)0x4, (q15_t)0xfe87, (q15_t)0x4, (q15_t)0xfe94, + (q15_t)0x4, (q15_t)0xfea0, (q15_t)0x4, (q15_t)0xfead, (q15_t)0x3, (q15_t)0xfeb9, (q15_t)0x3, (q15_t)0xfec6, + (q15_t)0x3, (q15_t)0xfed2, (q15_t)0x3, (q15_t)0xfedf, (q15_t)0x2, (q15_t)0xfeec, (q15_t)0x2, (q15_t)0xfef8, + (q15_t)0x2, (q15_t)0xff05, (q15_t)0x2, (q15_t)0xff11, (q15_t)0x2, (q15_t)0xff1e, (q15_t)0x1, (q15_t)0xff2a, + (q15_t)0x1, (q15_t)0xff37, (q15_t)0x1, (q15_t)0xff44, (q15_t)0x1, (q15_t)0xff50, (q15_t)0x1, (q15_t)0xff5d, + (q15_t)0x1, (q15_t)0xff69, (q15_t)0x1, (q15_t)0xff76, (q15_t)0x0, (q15_t)0xff82, (q15_t)0x0, (q15_t)0xff8f, + (q15_t)0x0, (q15_t)0xff9b, (q15_t)0x0, (q15_t)0xffa8, (q15_t)0x0, (q15_t)0xffb5, (q15_t)0x0, (q15_t)0xffc1, + (q15_t)0x0, (q15_t)0xffce, (q15_t)0x0, (q15_t)0xffda, (q15_t)0x0, (q15_t)0xffe7, (q15_t)0x0, (q15_t)0xfff3, + (q15_t)0x0, (q15_t)0x0, (q15_t)0x0, (q15_t)0xd, (q15_t)0x0, (q15_t)0x19, (q15_t)0x0, (q15_t)0x26, + (q15_t)0x0, (q15_t)0x32, (q15_t)0x0, (q15_t)0x3f, (q15_t)0x0, (q15_t)0x4b, (q15_t)0x0, (q15_t)0x58, + (q15_t)0x0, (q15_t)0x65, (q15_t)0x0, (q15_t)0x71, (q15_t)0x0, (q15_t)0x7e, (q15_t)0x1, (q15_t)0x8a, + (q15_t)0x1, (q15_t)0x97, (q15_t)0x1, (q15_t)0xa3, (q15_t)0x1, (q15_t)0xb0, (q15_t)0x1, (q15_t)0xbc, + (q15_t)0x1, (q15_t)0xc9, (q15_t)0x1, (q15_t)0xd6, (q15_t)0x2, (q15_t)0xe2, (q15_t)0x2, (q15_t)0xef, + (q15_t)0x2, (q15_t)0xfb, (q15_t)0x2, (q15_t)0x108, (q15_t)0x2, (q15_t)0x114, (q15_t)0x3, (q15_t)0x121, + (q15_t)0x3, (q15_t)0x12e, (q15_t)0x3, (q15_t)0x13a, (q15_t)0x3, (q15_t)0x147, (q15_t)0x4, (q15_t)0x153, + (q15_t)0x4, (q15_t)0x160, (q15_t)0x4, (q15_t)0x16c, (q15_t)0x4, (q15_t)0x179, (q15_t)0x5, (q15_t)0x186, + (q15_t)0x5, (q15_t)0x192, (q15_t)0x5, (q15_t)0x19f, (q15_t)0x6, (q15_t)0x1ab, (q15_t)0x6, (q15_t)0x1b8, + (q15_t)0x6, (q15_t)0x1c4, (q15_t)0x7, (q15_t)0x1d1, (q15_t)0x7, (q15_t)0x1dd, (q15_t)0x7, (q15_t)0x1ea, + (q15_t)0x8, (q15_t)0x1f7, (q15_t)0x8, (q15_t)0x203, (q15_t)0x9, (q15_t)0x210, (q15_t)0x9, (q15_t)0x21c, + (q15_t)0x9, (q15_t)0x229, (q15_t)0xa, (q15_t)0x235, (q15_t)0xa, (q15_t)0x242, (q15_t)0xb, (q15_t)0x24e, + (q15_t)0xb, (q15_t)0x25b, (q15_t)0xc, (q15_t)0x268, (q15_t)0xc, (q15_t)0x274, (q15_t)0xd, (q15_t)0x281, + (q15_t)0xd, (q15_t)0x28d, (q15_t)0xe, (q15_t)0x29a, (q15_t)0xe, (q15_t)0x2a6, (q15_t)0xf, (q15_t)0x2b3, + (q15_t)0xf, (q15_t)0x2c0, (q15_t)0x10, (q15_t)0x2cc, (q15_t)0x10, (q15_t)0x2d9, (q15_t)0x11, (q15_t)0x2e5, + (q15_t)0x11, (q15_t)0x2f2, (q15_t)0x12, (q15_t)0x2fe, (q15_t)0x13, (q15_t)0x30b, (q15_t)0x13, (q15_t)0x317, + (q15_t)0x14, (q15_t)0x324, (q15_t)0x14, (q15_t)0x330, (q15_t)0x15, (q15_t)0x33d, (q15_t)0x16, (q15_t)0x34a, + (q15_t)0x16, (q15_t)0x356, (q15_t)0x17, (q15_t)0x363, (q15_t)0x18, (q15_t)0x36f, (q15_t)0x18, (q15_t)0x37c, + (q15_t)0x19, (q15_t)0x388, (q15_t)0x1a, (q15_t)0x395, (q15_t)0x1a, (q15_t)0x3a1, (q15_t)0x1b, (q15_t)0x3ae, + (q15_t)0x1c, (q15_t)0x3bb, (q15_t)0x1d, (q15_t)0x3c7, (q15_t)0x1d, (q15_t)0x3d4, (q15_t)0x1e, (q15_t)0x3e0, + (q15_t)0x1f, (q15_t)0x3ed, (q15_t)0x20, (q15_t)0x3f9, (q15_t)0x20, (q15_t)0x406, (q15_t)0x21, (q15_t)0x412, + (q15_t)0x22, (q15_t)0x41f, (q15_t)0x23, (q15_t)0x42b, (q15_t)0x24, (q15_t)0x438, (q15_t)0x24, (q15_t)0x444, + (q15_t)0x25, (q15_t)0x451, (q15_t)0x26, (q15_t)0x45e, (q15_t)0x27, (q15_t)0x46a, (q15_t)0x28, (q15_t)0x477, + (q15_t)0x29, (q15_t)0x483, (q15_t)0x2a, (q15_t)0x490, (q15_t)0x2b, (q15_t)0x49c, (q15_t)0x2b, (q15_t)0x4a9, + (q15_t)0x2c, (q15_t)0x4b5, (q15_t)0x2d, (q15_t)0x4c2, (q15_t)0x2e, (q15_t)0x4ce, (q15_t)0x2f, (q15_t)0x4db, + (q15_t)0x30, (q15_t)0x4e7, (q15_t)0x31, (q15_t)0x4f4, (q15_t)0x32, (q15_t)0x500, (q15_t)0x33, (q15_t)0x50d, + (q15_t)0x34, (q15_t)0x51a, (q15_t)0x35, (q15_t)0x526, (q15_t)0x36, (q15_t)0x533, (q15_t)0x37, (q15_t)0x53f, + (q15_t)0x38, (q15_t)0x54c, (q15_t)0x39, (q15_t)0x558, (q15_t)0x3a, (q15_t)0x565, (q15_t)0x3b, (q15_t)0x571, + (q15_t)0x3c, (q15_t)0x57e, (q15_t)0x3d, (q15_t)0x58a, (q15_t)0x3f, (q15_t)0x597, (q15_t)0x40, (q15_t)0x5a3, + (q15_t)0x41, (q15_t)0x5b0, (q15_t)0x42, (q15_t)0x5bc, (q15_t)0x43, (q15_t)0x5c9, (q15_t)0x44, (q15_t)0x5d5, + (q15_t)0x45, (q15_t)0x5e2, (q15_t)0x47, (q15_t)0x5ee, (q15_t)0x48, (q15_t)0x5fb, (q15_t)0x49, (q15_t)0x607, + (q15_t)0x4a, (q15_t)0x614, (q15_t)0x4b, (q15_t)0x620, (q15_t)0x4c, (q15_t)0x62d, (q15_t)0x4e, (q15_t)0x639, + (q15_t)0x4f, (q15_t)0x646, (q15_t)0x50, (q15_t)0x652, (q15_t)0x51, (q15_t)0x65f, (q15_t)0x53, (q15_t)0x66b, + (q15_t)0x54, (q15_t)0x678, (q15_t)0x55, (q15_t)0x684, (q15_t)0x56, (q15_t)0x691, (q15_t)0x58, (q15_t)0x69d, + (q15_t)0x59, (q15_t)0x6aa, (q15_t)0x5a, (q15_t)0x6b6, (q15_t)0x5c, (q15_t)0x6c3, (q15_t)0x5d, (q15_t)0x6cf, + (q15_t)0x5e, (q15_t)0x6dc, (q15_t)0x60, (q15_t)0x6e8, (q15_t)0x61, (q15_t)0x6f5, (q15_t)0x62, (q15_t)0x701, + (q15_t)0x64, (q15_t)0x70e, (q15_t)0x65, (q15_t)0x71a, (q15_t)0x67, (q15_t)0x727, (q15_t)0x68, (q15_t)0x733, + (q15_t)0x69, (q15_t)0x740, (q15_t)0x6b, (q15_t)0x74c, (q15_t)0x6c, (q15_t)0x759, (q15_t)0x6e, (q15_t)0x765, + (q15_t)0x6f, (q15_t)0x772, (q15_t)0x71, (q15_t)0x77e, (q15_t)0x72, (q15_t)0x78b, (q15_t)0x74, (q15_t)0x797, + (q15_t)0x75, (q15_t)0x7a4, (q15_t)0x77, (q15_t)0x7b0, (q15_t)0x78, (q15_t)0x7bd, (q15_t)0x7a, (q15_t)0x7c9, + (q15_t)0x7b, (q15_t)0x7d6, (q15_t)0x7d, (q15_t)0x7e2, (q15_t)0x7e, (q15_t)0x7ef, (q15_t)0x80, (q15_t)0x7fb, + (q15_t)0x81, (q15_t)0x807, (q15_t)0x83, (q15_t)0x814, (q15_t)0x85, (q15_t)0x820, (q15_t)0x86, (q15_t)0x82d, + (q15_t)0x88, (q15_t)0x839, (q15_t)0x89, (q15_t)0x846, (q15_t)0x8b, (q15_t)0x852, (q15_t)0x8d, (q15_t)0x85f, + (q15_t)0x8e, (q15_t)0x86b, (q15_t)0x90, (q15_t)0x878, (q15_t)0x92, (q15_t)0x884, (q15_t)0x93, (q15_t)0x891, + (q15_t)0x95, (q15_t)0x89d, (q15_t)0x97, (q15_t)0x8a9, (q15_t)0x98, (q15_t)0x8b6, (q15_t)0x9a, (q15_t)0x8c2, + (q15_t)0x9c, (q15_t)0x8cf, (q15_t)0x9e, (q15_t)0x8db, (q15_t)0x9f, (q15_t)0x8e8, (q15_t)0xa1, (q15_t)0x8f4, + (q15_t)0xa3, (q15_t)0x901, (q15_t)0xa5, (q15_t)0x90d, (q15_t)0xa6, (q15_t)0x919, (q15_t)0xa8, (q15_t)0x926, + (q15_t)0xaa, (q15_t)0x932, (q15_t)0xac, (q15_t)0x93f, (q15_t)0xae, (q15_t)0x94b, (q15_t)0xaf, (q15_t)0x958, + (q15_t)0xb1, (q15_t)0x964, (q15_t)0xb3, (q15_t)0x970, (q15_t)0xb5, (q15_t)0x97d, (q15_t)0xb7, (q15_t)0x989, + (q15_t)0xb9, (q15_t)0x996, (q15_t)0xbb, (q15_t)0x9a2, (q15_t)0xbd, (q15_t)0x9af, (q15_t)0xbe, (q15_t)0x9bb, + (q15_t)0xc0, (q15_t)0x9c7, (q15_t)0xc2, (q15_t)0x9d4, (q15_t)0xc4, (q15_t)0x9e0, (q15_t)0xc6, (q15_t)0x9ed, + (q15_t)0xc8, (q15_t)0x9f9, (q15_t)0xca, (q15_t)0xa06, (q15_t)0xcc, (q15_t)0xa12, (q15_t)0xce, (q15_t)0xa1e, + (q15_t)0xd0, (q15_t)0xa2b, (q15_t)0xd2, (q15_t)0xa37, (q15_t)0xd4, (q15_t)0xa44, (q15_t)0xd6, (q15_t)0xa50, + (q15_t)0xd8, (q15_t)0xa5c, (q15_t)0xda, (q15_t)0xa69, (q15_t)0xdc, (q15_t)0xa75, (q15_t)0xde, (q15_t)0xa82, + (q15_t)0xe0, (q15_t)0xa8e, (q15_t)0xe2, (q15_t)0xa9a, (q15_t)0xe4, (q15_t)0xaa7, (q15_t)0xe7, (q15_t)0xab3, + (q15_t)0xe9, (q15_t)0xac0, (q15_t)0xeb, (q15_t)0xacc, (q15_t)0xed, (q15_t)0xad8, (q15_t)0xef, (q15_t)0xae5, + (q15_t)0xf1, (q15_t)0xaf1, (q15_t)0xf3, (q15_t)0xafd, (q15_t)0xf6, (q15_t)0xb0a, (q15_t)0xf8, (q15_t)0xb16, + (q15_t)0xfa, (q15_t)0xb23, (q15_t)0xfc, (q15_t)0xb2f, (q15_t)0xfe, (q15_t)0xb3b, (q15_t)0x100, (q15_t)0xb48, + (q15_t)0x103, (q15_t)0xb54, (q15_t)0x105, (q15_t)0xb60, (q15_t)0x107, (q15_t)0xb6d, (q15_t)0x109, (q15_t)0xb79, + (q15_t)0x10c, (q15_t)0xb85, (q15_t)0x10e, (q15_t)0xb92, (q15_t)0x110, (q15_t)0xb9e, (q15_t)0x113, (q15_t)0xbab, + (q15_t)0x115, (q15_t)0xbb7, (q15_t)0x117, (q15_t)0xbc3, (q15_t)0x119, (q15_t)0xbd0, (q15_t)0x11c, (q15_t)0xbdc, + (q15_t)0x11e, (q15_t)0xbe8, (q15_t)0x120, (q15_t)0xbf5, (q15_t)0x123, (q15_t)0xc01, (q15_t)0x125, (q15_t)0xc0d, + (q15_t)0x128, (q15_t)0xc1a, (q15_t)0x12a, (q15_t)0xc26, (q15_t)0x12c, (q15_t)0xc32, (q15_t)0x12f, (q15_t)0xc3f, + (q15_t)0x131, (q15_t)0xc4b, (q15_t)0x134, (q15_t)0xc57, (q15_t)0x136, (q15_t)0xc64, (q15_t)0x138, (q15_t)0xc70, + (q15_t)0x13b, (q15_t)0xc7c, (q15_t)0x13d, (q15_t)0xc89, (q15_t)0x140, (q15_t)0xc95, (q15_t)0x142, (q15_t)0xca1, + (q15_t)0x145, (q15_t)0xcae, (q15_t)0x147, (q15_t)0xcba, (q15_t)0x14a, (q15_t)0xcc6, (q15_t)0x14c, (q15_t)0xcd3, + (q15_t)0x14f, (q15_t)0xcdf, (q15_t)0x151, (q15_t)0xceb, (q15_t)0x154, (q15_t)0xcf8, (q15_t)0x156, (q15_t)0xd04, + (q15_t)0x159, (q15_t)0xd10, (q15_t)0x15b, (q15_t)0xd1c, (q15_t)0x15e, (q15_t)0xd29, (q15_t)0x161, (q15_t)0xd35, + (q15_t)0x163, (q15_t)0xd41, (q15_t)0x166, (q15_t)0xd4e, (q15_t)0x168, (q15_t)0xd5a, (q15_t)0x16b, (q15_t)0xd66, + (q15_t)0x16e, (q15_t)0xd72, (q15_t)0x170, (q15_t)0xd7f, (q15_t)0x173, (q15_t)0xd8b, (q15_t)0x176, (q15_t)0xd97, + (q15_t)0x178, (q15_t)0xda4, (q15_t)0x17b, (q15_t)0xdb0, (q15_t)0x17e, (q15_t)0xdbc, (q15_t)0x180, (q15_t)0xdc8, + (q15_t)0x183, (q15_t)0xdd5, (q15_t)0x186, (q15_t)0xde1, (q15_t)0x189, (q15_t)0xded, (q15_t)0x18b, (q15_t)0xdf9, + (q15_t)0x18e, (q15_t)0xe06, (q15_t)0x191, (q15_t)0xe12, (q15_t)0x194, (q15_t)0xe1e, (q15_t)0x196, (q15_t)0xe2b, + (q15_t)0x199, (q15_t)0xe37, (q15_t)0x19c, (q15_t)0xe43, (q15_t)0x19f, (q15_t)0xe4f, (q15_t)0x1a2, (q15_t)0xe5c, + (q15_t)0x1a4, (q15_t)0xe68, (q15_t)0x1a7, (q15_t)0xe74, (q15_t)0x1aa, (q15_t)0xe80, (q15_t)0x1ad, (q15_t)0xe8c, + (q15_t)0x1b0, (q15_t)0xe99, (q15_t)0x1b3, (q15_t)0xea5, (q15_t)0x1b6, (q15_t)0xeb1, (q15_t)0x1b8, (q15_t)0xebd, + (q15_t)0x1bb, (q15_t)0xeca, (q15_t)0x1be, (q15_t)0xed6, (q15_t)0x1c1, (q15_t)0xee2, (q15_t)0x1c4, (q15_t)0xeee, + (q15_t)0x1c7, (q15_t)0xefb, (q15_t)0x1ca, (q15_t)0xf07, (q15_t)0x1cd, (q15_t)0xf13, (q15_t)0x1d0, (q15_t)0xf1f, + (q15_t)0x1d3, (q15_t)0xf2b, (q15_t)0x1d6, (q15_t)0xf38, (q15_t)0x1d9, (q15_t)0xf44, (q15_t)0x1dc, (q15_t)0xf50, + (q15_t)0x1df, (q15_t)0xf5c, (q15_t)0x1e2, (q15_t)0xf68, (q15_t)0x1e5, (q15_t)0xf75, (q15_t)0x1e8, (q15_t)0xf81, + (q15_t)0x1eb, (q15_t)0xf8d, (q15_t)0x1ee, (q15_t)0xf99, (q15_t)0x1f1, (q15_t)0xfa5, (q15_t)0x1f4, (q15_t)0xfb2, + (q15_t)0x1f7, (q15_t)0xfbe, (q15_t)0x1fa, (q15_t)0xfca, (q15_t)0x1fd, (q15_t)0xfd6, (q15_t)0x201, (q15_t)0xfe2, + (q15_t)0x204, (q15_t)0xfee, (q15_t)0x207, (q15_t)0xffb, (q15_t)0x20a, (q15_t)0x1007, (q15_t)0x20d, (q15_t)0x1013, + (q15_t)0x210, (q15_t)0x101f, (q15_t)0x213, (q15_t)0x102b, (q15_t)0x217, (q15_t)0x1037, (q15_t)0x21a, (q15_t)0x1044, + (q15_t)0x21d, (q15_t)0x1050, (q15_t)0x220, (q15_t)0x105c, (q15_t)0x223, (q15_t)0x1068, (q15_t)0x227, (q15_t)0x1074, + (q15_t)0x22a, (q15_t)0x1080, (q15_t)0x22d, (q15_t)0x108c, (q15_t)0x230, (q15_t)0x1099, (q15_t)0x234, (q15_t)0x10a5, + (q15_t)0x237, (q15_t)0x10b1, (q15_t)0x23a, (q15_t)0x10bd, (q15_t)0x23e, (q15_t)0x10c9, (q15_t)0x241, (q15_t)0x10d5, + (q15_t)0x244, (q15_t)0x10e1, (q15_t)0x247, (q15_t)0x10ed, (q15_t)0x24b, (q15_t)0x10fa, (q15_t)0x24e, (q15_t)0x1106, + (q15_t)0x251, (q15_t)0x1112, (q15_t)0x255, (q15_t)0x111e, (q15_t)0x258, (q15_t)0x112a, (q15_t)0x25c, (q15_t)0x1136, + (q15_t)0x25f, (q15_t)0x1142, (q15_t)0x262, (q15_t)0x114e, (q15_t)0x266, (q15_t)0x115a, (q15_t)0x269, (q15_t)0x1167, + (q15_t)0x26d, (q15_t)0x1173, (q15_t)0x270, (q15_t)0x117f, (q15_t)0x273, (q15_t)0x118b, (q15_t)0x277, (q15_t)0x1197, + (q15_t)0x27a, (q15_t)0x11a3, (q15_t)0x27e, (q15_t)0x11af, (q15_t)0x281, (q15_t)0x11bb, (q15_t)0x285, (q15_t)0x11c7, + (q15_t)0x288, (q15_t)0x11d3, (q15_t)0x28c, (q15_t)0x11df, (q15_t)0x28f, (q15_t)0x11eb, (q15_t)0x293, (q15_t)0x11f7, + (q15_t)0x296, (q15_t)0x1204, (q15_t)0x29a, (q15_t)0x1210, (q15_t)0x29d, (q15_t)0x121c, (q15_t)0x2a1, (q15_t)0x1228, + (q15_t)0x2a5, (q15_t)0x1234, (q15_t)0x2a8, (q15_t)0x1240, (q15_t)0x2ac, (q15_t)0x124c, (q15_t)0x2af, (q15_t)0x1258, + (q15_t)0x2b3, (q15_t)0x1264, (q15_t)0x2b7, (q15_t)0x1270, (q15_t)0x2ba, (q15_t)0x127c, (q15_t)0x2be, (q15_t)0x1288, + (q15_t)0x2c1, (q15_t)0x1294, (q15_t)0x2c5, (q15_t)0x12a0, (q15_t)0x2c9, (q15_t)0x12ac, (q15_t)0x2cc, (q15_t)0x12b8, + (q15_t)0x2d0, (q15_t)0x12c4, (q15_t)0x2d4, (q15_t)0x12d0, (q15_t)0x2d8, (q15_t)0x12dc, (q15_t)0x2db, (q15_t)0x12e8, + (q15_t)0x2df, (q15_t)0x12f4, (q15_t)0x2e3, (q15_t)0x1300, (q15_t)0x2e6, (q15_t)0x130c, (q15_t)0x2ea, (q15_t)0x1318, + (q15_t)0x2ee, (q15_t)0x1324, (q15_t)0x2f2, (q15_t)0x1330, (q15_t)0x2f5, (q15_t)0x133c, (q15_t)0x2f9, (q15_t)0x1348, + (q15_t)0x2fd, (q15_t)0x1354, (q15_t)0x301, (q15_t)0x1360, (q15_t)0x305, (q15_t)0x136c, (q15_t)0x308, (q15_t)0x1378, + (q15_t)0x30c, (q15_t)0x1384, (q15_t)0x310, (q15_t)0x1390, (q15_t)0x314, (q15_t)0x139c, (q15_t)0x318, (q15_t)0x13a8, + (q15_t)0x31c, (q15_t)0x13b4, (q15_t)0x320, (q15_t)0x13c0, (q15_t)0x323, (q15_t)0x13cc, (q15_t)0x327, (q15_t)0x13d8, + (q15_t)0x32b, (q15_t)0x13e4, (q15_t)0x32f, (q15_t)0x13f0, (q15_t)0x333, (q15_t)0x13fb, (q15_t)0x337, (q15_t)0x1407, + (q15_t)0x33b, (q15_t)0x1413, (q15_t)0x33f, (q15_t)0x141f, (q15_t)0x343, (q15_t)0x142b, (q15_t)0x347, (q15_t)0x1437, + (q15_t)0x34b, (q15_t)0x1443, (q15_t)0x34f, (q15_t)0x144f, (q15_t)0x353, (q15_t)0x145b, (q15_t)0x357, (q15_t)0x1467, + (q15_t)0x35b, (q15_t)0x1473, (q15_t)0x35f, (q15_t)0x147f, (q15_t)0x363, (q15_t)0x148b, (q15_t)0x367, (q15_t)0x1496, + (q15_t)0x36b, (q15_t)0x14a2, (q15_t)0x36f, (q15_t)0x14ae, (q15_t)0x373, (q15_t)0x14ba, (q15_t)0x377, (q15_t)0x14c6, + (q15_t)0x37b, (q15_t)0x14d2, (q15_t)0x37f, (q15_t)0x14de, (q15_t)0x383, (q15_t)0x14ea, (q15_t)0x387, (q15_t)0x14f6, + (q15_t)0x38c, (q15_t)0x1501, (q15_t)0x390, (q15_t)0x150d, (q15_t)0x394, (q15_t)0x1519, (q15_t)0x398, (q15_t)0x1525, + (q15_t)0x39c, (q15_t)0x1531, (q15_t)0x3a0, (q15_t)0x153d, (q15_t)0x3a5, (q15_t)0x1549, (q15_t)0x3a9, (q15_t)0x1554, + (q15_t)0x3ad, (q15_t)0x1560, (q15_t)0x3b1, (q15_t)0x156c, (q15_t)0x3b5, (q15_t)0x1578, (q15_t)0x3ba, (q15_t)0x1584, + (q15_t)0x3be, (q15_t)0x1590, (q15_t)0x3c2, (q15_t)0x159b, (q15_t)0x3c6, (q15_t)0x15a7, (q15_t)0x3ca, (q15_t)0x15b3, + (q15_t)0x3cf, (q15_t)0x15bf, (q15_t)0x3d3, (q15_t)0x15cb, (q15_t)0x3d7, (q15_t)0x15d7, (q15_t)0x3dc, (q15_t)0x15e2, + (q15_t)0x3e0, (q15_t)0x15ee, (q15_t)0x3e4, (q15_t)0x15fa, (q15_t)0x3e9, (q15_t)0x1606, (q15_t)0x3ed, (q15_t)0x1612, + (q15_t)0x3f1, (q15_t)0x161d, (q15_t)0x3f6, (q15_t)0x1629, (q15_t)0x3fa, (q15_t)0x1635, (q15_t)0x3fe, (q15_t)0x1641, + (q15_t)0x403, (q15_t)0x164c, (q15_t)0x407, (q15_t)0x1658, (q15_t)0x40b, (q15_t)0x1664, (q15_t)0x410, (q15_t)0x1670, + (q15_t)0x414, (q15_t)0x167c, (q15_t)0x419, (q15_t)0x1687, (q15_t)0x41d, (q15_t)0x1693, (q15_t)0x422, (q15_t)0x169f, + (q15_t)0x426, (q15_t)0x16ab, (q15_t)0x42a, (q15_t)0x16b6, (q15_t)0x42f, (q15_t)0x16c2, (q15_t)0x433, (q15_t)0x16ce, + (q15_t)0x438, (q15_t)0x16da, (q15_t)0x43c, (q15_t)0x16e5, (q15_t)0x441, (q15_t)0x16f1, (q15_t)0x445, (q15_t)0x16fd, + (q15_t)0x44a, (q15_t)0x1709, (q15_t)0x44e, (q15_t)0x1714, (q15_t)0x453, (q15_t)0x1720, (q15_t)0x457, (q15_t)0x172c, + (q15_t)0x45c, (q15_t)0x1737, (q15_t)0x461, (q15_t)0x1743, (q15_t)0x465, (q15_t)0x174f, (q15_t)0x46a, (q15_t)0x175b, + (q15_t)0x46e, (q15_t)0x1766, (q15_t)0x473, (q15_t)0x1772, (q15_t)0x478, (q15_t)0x177e, (q15_t)0x47c, (q15_t)0x1789, + (q15_t)0x481, (q15_t)0x1795, (q15_t)0x485, (q15_t)0x17a1, (q15_t)0x48a, (q15_t)0x17ac, (q15_t)0x48f, (q15_t)0x17b8, + (q15_t)0x493, (q15_t)0x17c4, (q15_t)0x498, (q15_t)0x17cf, (q15_t)0x49d, (q15_t)0x17db, (q15_t)0x4a1, (q15_t)0x17e7, + (q15_t)0x4a6, (q15_t)0x17f2, (q15_t)0x4ab, (q15_t)0x17fe, (q15_t)0x4b0, (q15_t)0x180a, (q15_t)0x4b4, (q15_t)0x1815, + (q15_t)0x4b9, (q15_t)0x1821, (q15_t)0x4be, (q15_t)0x182d, (q15_t)0x4c2, (q15_t)0x1838, (q15_t)0x4c7, (q15_t)0x1844, + (q15_t)0x4cc, (q15_t)0x184f, (q15_t)0x4d1, (q15_t)0x185b, (q15_t)0x4d6, (q15_t)0x1867, (q15_t)0x4da, (q15_t)0x1872, + (q15_t)0x4df, (q15_t)0x187e, (q15_t)0x4e4, (q15_t)0x1889, (q15_t)0x4e9, (q15_t)0x1895, (q15_t)0x4ee, (q15_t)0x18a1, + (q15_t)0x4f2, (q15_t)0x18ac, (q15_t)0x4f7, (q15_t)0x18b8, (q15_t)0x4fc, (q15_t)0x18c3, (q15_t)0x501, (q15_t)0x18cf, + (q15_t)0x506, (q15_t)0x18db, (q15_t)0x50b, (q15_t)0x18e6, (q15_t)0x510, (q15_t)0x18f2, (q15_t)0x515, (q15_t)0x18fd, + (q15_t)0x51a, (q15_t)0x1909, (q15_t)0x51e, (q15_t)0x1914, (q15_t)0x523, (q15_t)0x1920, (q15_t)0x528, (q15_t)0x192c, + (q15_t)0x52d, (q15_t)0x1937, (q15_t)0x532, (q15_t)0x1943, (q15_t)0x537, (q15_t)0x194e, (q15_t)0x53c, (q15_t)0x195a, + (q15_t)0x541, (q15_t)0x1965, (q15_t)0x546, (q15_t)0x1971, (q15_t)0x54b, (q15_t)0x197c, (q15_t)0x550, (q15_t)0x1988, + (q15_t)0x555, (q15_t)0x1993, (q15_t)0x55a, (q15_t)0x199f, (q15_t)0x55f, (q15_t)0x19aa, (q15_t)0x564, (q15_t)0x19b6, + (q15_t)0x569, (q15_t)0x19c1, (q15_t)0x56e, (q15_t)0x19cd, (q15_t)0x573, (q15_t)0x19d8, (q15_t)0x578, (q15_t)0x19e4, + (q15_t)0x57e, (q15_t)0x19ef, (q15_t)0x583, (q15_t)0x19fb, (q15_t)0x588, (q15_t)0x1a06, (q15_t)0x58d, (q15_t)0x1a12, + (q15_t)0x592, (q15_t)0x1a1d, (q15_t)0x597, (q15_t)0x1a29, (q15_t)0x59c, (q15_t)0x1a34, (q15_t)0x5a1, (q15_t)0x1a40, + (q15_t)0x5a7, (q15_t)0x1a4b, (q15_t)0x5ac, (q15_t)0x1a57, (q15_t)0x5b1, (q15_t)0x1a62, (q15_t)0x5b6, (q15_t)0x1a6e, + (q15_t)0x5bb, (q15_t)0x1a79, (q15_t)0x5c1, (q15_t)0x1a84, (q15_t)0x5c6, (q15_t)0x1a90, (q15_t)0x5cb, (q15_t)0x1a9b, + (q15_t)0x5d0, (q15_t)0x1aa7, (q15_t)0x5d5, (q15_t)0x1ab2, (q15_t)0x5db, (q15_t)0x1abe, (q15_t)0x5e0, (q15_t)0x1ac9, + (q15_t)0x5e5, (q15_t)0x1ad4, (q15_t)0x5ea, (q15_t)0x1ae0, (q15_t)0x5f0, (q15_t)0x1aeb, (q15_t)0x5f5, (q15_t)0x1af7, + (q15_t)0x5fa, (q15_t)0x1b02, (q15_t)0x600, (q15_t)0x1b0d, (q15_t)0x605, (q15_t)0x1b19, (q15_t)0x60a, (q15_t)0x1b24, + (q15_t)0x610, (q15_t)0x1b30, (q15_t)0x615, (q15_t)0x1b3b, (q15_t)0x61a, (q15_t)0x1b46, (q15_t)0x620, (q15_t)0x1b52, + (q15_t)0x625, (q15_t)0x1b5d, (q15_t)0x62a, (q15_t)0x1b68, (q15_t)0x630, (q15_t)0x1b74, (q15_t)0x635, (q15_t)0x1b7f, + (q15_t)0x63b, (q15_t)0x1b8a, (q15_t)0x640, (q15_t)0x1b96, (q15_t)0x645, (q15_t)0x1ba1, (q15_t)0x64b, (q15_t)0x1bac, + (q15_t)0x650, (q15_t)0x1bb8, (q15_t)0x656, (q15_t)0x1bc3, (q15_t)0x65b, (q15_t)0x1bce, (q15_t)0x661, (q15_t)0x1bda, + (q15_t)0x666, (q15_t)0x1be5, (q15_t)0x66c, (q15_t)0x1bf0, (q15_t)0x671, (q15_t)0x1bfc, (q15_t)0x677, (q15_t)0x1c07, + (q15_t)0x67c, (q15_t)0x1c12, (q15_t)0x682, (q15_t)0x1c1e, (q15_t)0x687, (q15_t)0x1c29, (q15_t)0x68d, (q15_t)0x1c34, + (q15_t)0x692, (q15_t)0x1c3f, (q15_t)0x698, (q15_t)0x1c4b, (q15_t)0x69d, (q15_t)0x1c56, (q15_t)0x6a3, (q15_t)0x1c61, + (q15_t)0x6a8, (q15_t)0x1c6c, (q15_t)0x6ae, (q15_t)0x1c78, (q15_t)0x6b4, (q15_t)0x1c83, (q15_t)0x6b9, (q15_t)0x1c8e, + (q15_t)0x6bf, (q15_t)0x1c99, (q15_t)0x6c5, (q15_t)0x1ca5, (q15_t)0x6ca, (q15_t)0x1cb0, (q15_t)0x6d0, (q15_t)0x1cbb, + (q15_t)0x6d5, (q15_t)0x1cc6, (q15_t)0x6db, (q15_t)0x1cd2, (q15_t)0x6e1, (q15_t)0x1cdd, (q15_t)0x6e6, (q15_t)0x1ce8, + (q15_t)0x6ec, (q15_t)0x1cf3, (q15_t)0x6f2, (q15_t)0x1cff, (q15_t)0x6f7, (q15_t)0x1d0a, (q15_t)0x6fd, (q15_t)0x1d15, + (q15_t)0x703, (q15_t)0x1d20, (q15_t)0x709, (q15_t)0x1d2b, (q15_t)0x70e, (q15_t)0x1d36, (q15_t)0x714, (q15_t)0x1d42, + (q15_t)0x71a, (q15_t)0x1d4d, (q15_t)0x720, (q15_t)0x1d58, (q15_t)0x725, (q15_t)0x1d63, (q15_t)0x72b, (q15_t)0x1d6e, + (q15_t)0x731, (q15_t)0x1d79, (q15_t)0x737, (q15_t)0x1d85, (q15_t)0x73d, (q15_t)0x1d90, (q15_t)0x742, (q15_t)0x1d9b, + (q15_t)0x748, (q15_t)0x1da6, (q15_t)0x74e, (q15_t)0x1db1, (q15_t)0x754, (q15_t)0x1dbc, (q15_t)0x75a, (q15_t)0x1dc7, + (q15_t)0x75f, (q15_t)0x1dd3, (q15_t)0x765, (q15_t)0x1dde, (q15_t)0x76b, (q15_t)0x1de9, (q15_t)0x771, (q15_t)0x1df4, + (q15_t)0x777, (q15_t)0x1dff, (q15_t)0x77d, (q15_t)0x1e0a, (q15_t)0x783, (q15_t)0x1e15, (q15_t)0x789, (q15_t)0x1e20, + (q15_t)0x78f, (q15_t)0x1e2b, (q15_t)0x795, (q15_t)0x1e36, (q15_t)0x79a, (q15_t)0x1e42, (q15_t)0x7a0, (q15_t)0x1e4d, + (q15_t)0x7a6, (q15_t)0x1e58, (q15_t)0x7ac, (q15_t)0x1e63, (q15_t)0x7b2, (q15_t)0x1e6e, (q15_t)0x7b8, (q15_t)0x1e79, + (q15_t)0x7be, (q15_t)0x1e84, (q15_t)0x7c4, (q15_t)0x1e8f, (q15_t)0x7ca, (q15_t)0x1e9a, (q15_t)0x7d0, (q15_t)0x1ea5, + (q15_t)0x7d6, (q15_t)0x1eb0, (q15_t)0x7dc, (q15_t)0x1ebb, (q15_t)0x7e2, (q15_t)0x1ec6, (q15_t)0x7e8, (q15_t)0x1ed1, + (q15_t)0x7ee, (q15_t)0x1edc, (q15_t)0x7f5, (q15_t)0x1ee7, (q15_t)0x7fb, (q15_t)0x1ef2, (q15_t)0x801, (q15_t)0x1efd, + (q15_t)0x807, (q15_t)0x1f08, (q15_t)0x80d, (q15_t)0x1f13, (q15_t)0x813, (q15_t)0x1f1e, (q15_t)0x819, (q15_t)0x1f29, + (q15_t)0x81f, (q15_t)0x1f34, (q15_t)0x825, (q15_t)0x1f3f, (q15_t)0x82b, (q15_t)0x1f4a, (q15_t)0x832, (q15_t)0x1f55, + (q15_t)0x838, (q15_t)0x1f60, (q15_t)0x83e, (q15_t)0x1f6b, (q15_t)0x844, (q15_t)0x1f76, (q15_t)0x84a, (q15_t)0x1f81, + (q15_t)0x850, (q15_t)0x1f8c, (q15_t)0x857, (q15_t)0x1f97, (q15_t)0x85d, (q15_t)0x1fa2, (q15_t)0x863, (q15_t)0x1fac, + (q15_t)0x869, (q15_t)0x1fb7, (q15_t)0x870, (q15_t)0x1fc2, (q15_t)0x876, (q15_t)0x1fcd, (q15_t)0x87c, (q15_t)0x1fd8, + (q15_t)0x882, (q15_t)0x1fe3, (q15_t)0x889, (q15_t)0x1fee, (q15_t)0x88f, (q15_t)0x1ff9, (q15_t)0x895, (q15_t)0x2004, + (q15_t)0x89b, (q15_t)0x200f, (q15_t)0x8a2, (q15_t)0x2019, (q15_t)0x8a8, (q15_t)0x2024, (q15_t)0x8ae, (q15_t)0x202f, + (q15_t)0x8b5, (q15_t)0x203a, (q15_t)0x8bb, (q15_t)0x2045, (q15_t)0x8c1, (q15_t)0x2050, (q15_t)0x8c8, (q15_t)0x205b, + (q15_t)0x8ce, (q15_t)0x2065, (q15_t)0x8d4, (q15_t)0x2070, (q15_t)0x8db, (q15_t)0x207b, (q15_t)0x8e1, (q15_t)0x2086, + (q15_t)0x8e8, (q15_t)0x2091, (q15_t)0x8ee, (q15_t)0x209b, (q15_t)0x8f4, (q15_t)0x20a6, (q15_t)0x8fb, (q15_t)0x20b1, + (q15_t)0x901, (q15_t)0x20bc, (q15_t)0x908, (q15_t)0x20c7, (q15_t)0x90e, (q15_t)0x20d1, (q15_t)0x915, (q15_t)0x20dc, + (q15_t)0x91b, (q15_t)0x20e7, (q15_t)0x921, (q15_t)0x20f2, (q15_t)0x928, (q15_t)0x20fd, (q15_t)0x92e, (q15_t)0x2107, + (q15_t)0x935, (q15_t)0x2112, (q15_t)0x93b, (q15_t)0x211d, (q15_t)0x942, (q15_t)0x2128, (q15_t)0x948, (q15_t)0x2132, + (q15_t)0x94f, (q15_t)0x213d, (q15_t)0x955, (q15_t)0x2148, (q15_t)0x95c, (q15_t)0x2153, (q15_t)0x963, (q15_t)0x215d, + (q15_t)0x969, (q15_t)0x2168, (q15_t)0x970, (q15_t)0x2173, (q15_t)0x976, (q15_t)0x217d, (q15_t)0x97d, (q15_t)0x2188, + (q15_t)0x983, (q15_t)0x2193, (q15_t)0x98a, (q15_t)0x219e, (q15_t)0x991, (q15_t)0x21a8, (q15_t)0x997, (q15_t)0x21b3, + (q15_t)0x99e, (q15_t)0x21be, (q15_t)0x9a4, (q15_t)0x21c8, (q15_t)0x9ab, (q15_t)0x21d3, (q15_t)0x9b2, (q15_t)0x21de, + (q15_t)0x9b8, (q15_t)0x21e8, (q15_t)0x9bf, (q15_t)0x21f3, (q15_t)0x9c6, (q15_t)0x21fe, (q15_t)0x9cc, (q15_t)0x2208, + (q15_t)0x9d3, (q15_t)0x2213, (q15_t)0x9da, (q15_t)0x221e, (q15_t)0x9e0, (q15_t)0x2228, (q15_t)0x9e7, (q15_t)0x2233, + (q15_t)0x9ee, (q15_t)0x223d, (q15_t)0x9f5, (q15_t)0x2248, (q15_t)0x9fb, (q15_t)0x2253, (q15_t)0xa02, (q15_t)0x225d, + (q15_t)0xa09, (q15_t)0x2268, (q15_t)0xa10, (q15_t)0x2272, (q15_t)0xa16, (q15_t)0x227d, (q15_t)0xa1d, (q15_t)0x2288, + (q15_t)0xa24, (q15_t)0x2292, (q15_t)0xa2b, (q15_t)0x229d, (q15_t)0xa32, (q15_t)0x22a7, (q15_t)0xa38, (q15_t)0x22b2, + (q15_t)0xa3f, (q15_t)0x22bc, (q15_t)0xa46, (q15_t)0x22c7, (q15_t)0xa4d, (q15_t)0x22d2, (q15_t)0xa54, (q15_t)0x22dc, + (q15_t)0xa5b, (q15_t)0x22e7, (q15_t)0xa61, (q15_t)0x22f1, (q15_t)0xa68, (q15_t)0x22fc, (q15_t)0xa6f, (q15_t)0x2306, + (q15_t)0xa76, (q15_t)0x2311, (q15_t)0xa7d, (q15_t)0x231b, (q15_t)0xa84, (q15_t)0x2326, (q15_t)0xa8b, (q15_t)0x2330, + (q15_t)0xa92, (q15_t)0x233b, (q15_t)0xa99, (q15_t)0x2345, (q15_t)0xa9f, (q15_t)0x2350, (q15_t)0xaa6, (q15_t)0x235a, + (q15_t)0xaad, (q15_t)0x2365, (q15_t)0xab4, (q15_t)0x236f, (q15_t)0xabb, (q15_t)0x237a, (q15_t)0xac2, (q15_t)0x2384, + (q15_t)0xac9, (q15_t)0x238e, (q15_t)0xad0, (q15_t)0x2399, (q15_t)0xad7, (q15_t)0x23a3, (q15_t)0xade, (q15_t)0x23ae, + (q15_t)0xae5, (q15_t)0x23b8, (q15_t)0xaec, (q15_t)0x23c3, (q15_t)0xaf3, (q15_t)0x23cd, (q15_t)0xafa, (q15_t)0x23d7, + (q15_t)0xb01, (q15_t)0x23e2, (q15_t)0xb08, (q15_t)0x23ec, (q15_t)0xb0f, (q15_t)0x23f7, (q15_t)0xb16, (q15_t)0x2401, + (q15_t)0xb1e, (q15_t)0x240b, (q15_t)0xb25, (q15_t)0x2416, (q15_t)0xb2c, (q15_t)0x2420, (q15_t)0xb33, (q15_t)0x242b, + (q15_t)0xb3a, (q15_t)0x2435, (q15_t)0xb41, (q15_t)0x243f, (q15_t)0xb48, (q15_t)0x244a, (q15_t)0xb4f, (q15_t)0x2454, + (q15_t)0xb56, (q15_t)0x245e, (q15_t)0xb5e, (q15_t)0x2469, (q15_t)0xb65, (q15_t)0x2473, (q15_t)0xb6c, (q15_t)0x247d, + (q15_t)0xb73, (q15_t)0x2488, (q15_t)0xb7a, (q15_t)0x2492, (q15_t)0xb81, (q15_t)0x249c, (q15_t)0xb89, (q15_t)0x24a7, + (q15_t)0xb90, (q15_t)0x24b1, (q15_t)0xb97, (q15_t)0x24bb, (q15_t)0xb9e, (q15_t)0x24c5, (q15_t)0xba5, (q15_t)0x24d0, + (q15_t)0xbad, (q15_t)0x24da, (q15_t)0xbb4, (q15_t)0x24e4, (q15_t)0xbbb, (q15_t)0x24ef, (q15_t)0xbc2, (q15_t)0x24f9, + (q15_t)0xbca, (q15_t)0x2503, (q15_t)0xbd1, (q15_t)0x250d, (q15_t)0xbd8, (q15_t)0x2518, (q15_t)0xbe0, (q15_t)0x2522, + (q15_t)0xbe7, (q15_t)0x252c, (q15_t)0xbee, (q15_t)0x2536, (q15_t)0xbf5, (q15_t)0x2541, (q15_t)0xbfd, (q15_t)0x254b, + (q15_t)0xc04, (q15_t)0x2555, (q15_t)0xc0b, (q15_t)0x255f, (q15_t)0xc13, (q15_t)0x2569, (q15_t)0xc1a, (q15_t)0x2574, + (q15_t)0xc21, (q15_t)0x257e, (q15_t)0xc29, (q15_t)0x2588, (q15_t)0xc30, (q15_t)0x2592, (q15_t)0xc38, (q15_t)0x259c, + (q15_t)0xc3f, (q15_t)0x25a6, (q15_t)0xc46, (q15_t)0x25b1, (q15_t)0xc4e, (q15_t)0x25bb, (q15_t)0xc55, (q15_t)0x25c5, + (q15_t)0xc5d, (q15_t)0x25cf, (q15_t)0xc64, (q15_t)0x25d9, (q15_t)0xc6b, (q15_t)0x25e3, (q15_t)0xc73, (q15_t)0x25ed, + (q15_t)0xc7a, (q15_t)0x25f8, (q15_t)0xc82, (q15_t)0x2602, (q15_t)0xc89, (q15_t)0x260c, (q15_t)0xc91, (q15_t)0x2616, + (q15_t)0xc98, (q15_t)0x2620, (q15_t)0xca0, (q15_t)0x262a, (q15_t)0xca7, (q15_t)0x2634, (q15_t)0xcaf, (q15_t)0x263e, + (q15_t)0xcb6, (q15_t)0x2648, (q15_t)0xcbe, (q15_t)0x2652, (q15_t)0xcc5, (q15_t)0x265c, (q15_t)0xccd, (q15_t)0x2666, + (q15_t)0xcd4, (q15_t)0x2671, (q15_t)0xcdc, (q15_t)0x267b, (q15_t)0xce3, (q15_t)0x2685, (q15_t)0xceb, (q15_t)0x268f, + (q15_t)0xcf3, (q15_t)0x2699, (q15_t)0xcfa, (q15_t)0x26a3, (q15_t)0xd02, (q15_t)0x26ad, (q15_t)0xd09, (q15_t)0x26b7, + (q15_t)0xd11, (q15_t)0x26c1, (q15_t)0xd19, (q15_t)0x26cb, (q15_t)0xd20, (q15_t)0x26d5, (q15_t)0xd28, (q15_t)0x26df, + (q15_t)0xd30, (q15_t)0x26e9, (q15_t)0xd37, (q15_t)0x26f3, (q15_t)0xd3f, (q15_t)0x26fd, (q15_t)0xd46, (q15_t)0x2707, + (q15_t)0xd4e, (q15_t)0x2711, (q15_t)0xd56, (q15_t)0x271a, (q15_t)0xd5d, (q15_t)0x2724, (q15_t)0xd65, (q15_t)0x272e, + (q15_t)0xd6d, (q15_t)0x2738, (q15_t)0xd75, (q15_t)0x2742, (q15_t)0xd7c, (q15_t)0x274c, (q15_t)0xd84, (q15_t)0x2756, + (q15_t)0xd8c, (q15_t)0x2760, (q15_t)0xd93, (q15_t)0x276a, (q15_t)0xd9b, (q15_t)0x2774, (q15_t)0xda3, (q15_t)0x277e, + (q15_t)0xdab, (q15_t)0x2788, (q15_t)0xdb2, (q15_t)0x2791, (q15_t)0xdba, (q15_t)0x279b, (q15_t)0xdc2, (q15_t)0x27a5, + (q15_t)0xdca, (q15_t)0x27af, (q15_t)0xdd2, (q15_t)0x27b9, (q15_t)0xdd9, (q15_t)0x27c3, (q15_t)0xde1, (q15_t)0x27cd, + (q15_t)0xde9, (q15_t)0x27d6, (q15_t)0xdf1, (q15_t)0x27e0, (q15_t)0xdf9, (q15_t)0x27ea, (q15_t)0xe01, (q15_t)0x27f4, + (q15_t)0xe08, (q15_t)0x27fe, (q15_t)0xe10, (q15_t)0x2808, (q15_t)0xe18, (q15_t)0x2811, (q15_t)0xe20, (q15_t)0x281b, + (q15_t)0xe28, (q15_t)0x2825, (q15_t)0xe30, (q15_t)0x282f, (q15_t)0xe38, (q15_t)0x2838, (q15_t)0xe40, (q15_t)0x2842, + (q15_t)0xe47, (q15_t)0x284c, (q15_t)0xe4f, (q15_t)0x2856, (q15_t)0xe57, (q15_t)0x2860, (q15_t)0xe5f, (q15_t)0x2869, + (q15_t)0xe67, (q15_t)0x2873, (q15_t)0xe6f, (q15_t)0x287d, (q15_t)0xe77, (q15_t)0x2886, (q15_t)0xe7f, (q15_t)0x2890, + (q15_t)0xe87, (q15_t)0x289a, (q15_t)0xe8f, (q15_t)0x28a4, (q15_t)0xe97, (q15_t)0x28ad, (q15_t)0xe9f, (q15_t)0x28b7, + (q15_t)0xea7, (q15_t)0x28c1, (q15_t)0xeaf, (q15_t)0x28ca, (q15_t)0xeb7, (q15_t)0x28d4, (q15_t)0xebf, (q15_t)0x28de, + (q15_t)0xec7, (q15_t)0x28e7, (q15_t)0xecf, (q15_t)0x28f1, (q15_t)0xed7, (q15_t)0x28fb, (q15_t)0xedf, (q15_t)0x2904, + (q15_t)0xee7, (q15_t)0x290e, (q15_t)0xeef, (q15_t)0x2918, (q15_t)0xef7, (q15_t)0x2921, (q15_t)0xeff, (q15_t)0x292b, + (q15_t)0xf07, (q15_t)0x2935, (q15_t)0xf10, (q15_t)0x293e, (q15_t)0xf18, (q15_t)0x2948, (q15_t)0xf20, (q15_t)0x2951, + (q15_t)0xf28, (q15_t)0x295b, (q15_t)0xf30, (q15_t)0x2965, (q15_t)0xf38, (q15_t)0x296e, (q15_t)0xf40, (q15_t)0x2978, + (q15_t)0xf48, (q15_t)0x2981, (q15_t)0xf51, (q15_t)0x298b, (q15_t)0xf59, (q15_t)0x2994, (q15_t)0xf61, (q15_t)0x299e, + (q15_t)0xf69, (q15_t)0x29a7, (q15_t)0xf71, (q15_t)0x29b1, (q15_t)0xf79, (q15_t)0x29bb, (q15_t)0xf82, (q15_t)0x29c4, + (q15_t)0xf8a, (q15_t)0x29ce, (q15_t)0xf92, (q15_t)0x29d7, (q15_t)0xf9a, (q15_t)0x29e1, (q15_t)0xfa3, (q15_t)0x29ea, + (q15_t)0xfab, (q15_t)0x29f4, (q15_t)0xfb3, (q15_t)0x29fd, (q15_t)0xfbb, (q15_t)0x2a07, (q15_t)0xfc4, (q15_t)0x2a10, + (q15_t)0xfcc, (q15_t)0x2a1a, (q15_t)0xfd4, (q15_t)0x2a23, (q15_t)0xfdc, (q15_t)0x2a2c, (q15_t)0xfe5, (q15_t)0x2a36, + (q15_t)0xfed, (q15_t)0x2a3f, (q15_t)0xff5, (q15_t)0x2a49, (q15_t)0xffe, (q15_t)0x2a52, (q15_t)0x1006, (q15_t)0x2a5c, + (q15_t)0x100e, (q15_t)0x2a65, (q15_t)0x1016, (q15_t)0x2a6e, (q15_t)0x101f, (q15_t)0x2a78, (q15_t)0x1027, (q15_t)0x2a81, + (q15_t)0x1030, (q15_t)0x2a8b, (q15_t)0x1038, (q15_t)0x2a94, (q15_t)0x1040, (q15_t)0x2a9d, (q15_t)0x1049, (q15_t)0x2aa7, + (q15_t)0x1051, (q15_t)0x2ab0, (q15_t)0x1059, (q15_t)0x2ab9, (q15_t)0x1062, (q15_t)0x2ac3, (q15_t)0x106a, (q15_t)0x2acc, + (q15_t)0x1073, (q15_t)0x2ad6, (q15_t)0x107b, (q15_t)0x2adf, (q15_t)0x1083, (q15_t)0x2ae8, (q15_t)0x108c, (q15_t)0x2af2, + (q15_t)0x1094, (q15_t)0x2afb, (q15_t)0x109d, (q15_t)0x2b04, (q15_t)0x10a5, (q15_t)0x2b0d, (q15_t)0x10ae, (q15_t)0x2b17, + (q15_t)0x10b6, (q15_t)0x2b20, (q15_t)0x10bf, (q15_t)0x2b29, (q15_t)0x10c7, (q15_t)0x2b33, (q15_t)0x10d0, (q15_t)0x2b3c, + (q15_t)0x10d8, (q15_t)0x2b45, (q15_t)0x10e0, (q15_t)0x2b4e, (q15_t)0x10e9, (q15_t)0x2b58, (q15_t)0x10f2, (q15_t)0x2b61, + (q15_t)0x10fa, (q15_t)0x2b6a, (q15_t)0x1103, (q15_t)0x2b73, (q15_t)0x110b, (q15_t)0x2b7d, (q15_t)0x1114, (q15_t)0x2b86, + (q15_t)0x111c, (q15_t)0x2b8f, (q15_t)0x1125, (q15_t)0x2b98, (q15_t)0x112d, (q15_t)0x2ba1, (q15_t)0x1136, (q15_t)0x2bab, + (q15_t)0x113e, (q15_t)0x2bb4, (q15_t)0x1147, (q15_t)0x2bbd, (q15_t)0x1150, (q15_t)0x2bc6, (q15_t)0x1158, (q15_t)0x2bcf, + (q15_t)0x1161, (q15_t)0x2bd8, (q15_t)0x1169, (q15_t)0x2be2, (q15_t)0x1172, (q15_t)0x2beb, (q15_t)0x117b, (q15_t)0x2bf4, + (q15_t)0x1183, (q15_t)0x2bfd, (q15_t)0x118c, (q15_t)0x2c06, (q15_t)0x1195, (q15_t)0x2c0f, (q15_t)0x119d, (q15_t)0x2c18, + (q15_t)0x11a6, (q15_t)0x2c21, (q15_t)0x11af, (q15_t)0x2c2b, (q15_t)0x11b7, (q15_t)0x2c34, (q15_t)0x11c0, (q15_t)0x2c3d, + (q15_t)0x11c9, (q15_t)0x2c46, (q15_t)0x11d1, (q15_t)0x2c4f, (q15_t)0x11da, (q15_t)0x2c58, (q15_t)0x11e3, (q15_t)0x2c61, + (q15_t)0x11eb, (q15_t)0x2c6a, (q15_t)0x11f4, (q15_t)0x2c73, (q15_t)0x11fd, (q15_t)0x2c7c, (q15_t)0x1206, (q15_t)0x2c85, + (q15_t)0x120e, (q15_t)0x2c8e, (q15_t)0x1217, (q15_t)0x2c97, (q15_t)0x1220, (q15_t)0x2ca0, (q15_t)0x1229, (q15_t)0x2ca9, + (q15_t)0x1231, (q15_t)0x2cb2, (q15_t)0x123a, (q15_t)0x2cbb, (q15_t)0x1243, (q15_t)0x2cc4, (q15_t)0x124c, (q15_t)0x2ccd, + (q15_t)0x1255, (q15_t)0x2cd6, (q15_t)0x125d, (q15_t)0x2cdf, (q15_t)0x1266, (q15_t)0x2ce8, (q15_t)0x126f, (q15_t)0x2cf1, + (q15_t)0x1278, (q15_t)0x2cfa, (q15_t)0x1281, (q15_t)0x2d03, (q15_t)0x128a, (q15_t)0x2d0c, (q15_t)0x1292, (q15_t)0x2d15, + (q15_t)0x129b, (q15_t)0x2d1e, (q15_t)0x12a4, (q15_t)0x2d27, (q15_t)0x12ad, (q15_t)0x2d2f, (q15_t)0x12b6, (q15_t)0x2d38, + (q15_t)0x12bf, (q15_t)0x2d41, (q15_t)0x12c8, (q15_t)0x2d4a, (q15_t)0x12d1, (q15_t)0x2d53, (q15_t)0x12d9, (q15_t)0x2d5c, + (q15_t)0x12e2, (q15_t)0x2d65, (q15_t)0x12eb, (q15_t)0x2d6e, (q15_t)0x12f4, (q15_t)0x2d76, (q15_t)0x12fd, (q15_t)0x2d7f, + (q15_t)0x1306, (q15_t)0x2d88, (q15_t)0x130f, (q15_t)0x2d91, (q15_t)0x1318, (q15_t)0x2d9a, (q15_t)0x1321, (q15_t)0x2da3, + (q15_t)0x132a, (q15_t)0x2dab, (q15_t)0x1333, (q15_t)0x2db4, (q15_t)0x133c, (q15_t)0x2dbd, (q15_t)0x1345, (q15_t)0x2dc6, + (q15_t)0x134e, (q15_t)0x2dcf, (q15_t)0x1357, (q15_t)0x2dd7, (q15_t)0x1360, (q15_t)0x2de0, (q15_t)0x1369, (q15_t)0x2de9, + (q15_t)0x1372, (q15_t)0x2df2, (q15_t)0x137b, (q15_t)0x2dfa, (q15_t)0x1384, (q15_t)0x2e03, (q15_t)0x138d, (q15_t)0x2e0c, + (q15_t)0x1396, (q15_t)0x2e15, (q15_t)0x139f, (q15_t)0x2e1d, (q15_t)0x13a8, (q15_t)0x2e26, (q15_t)0x13b1, (q15_t)0x2e2f, + (q15_t)0x13ba, (q15_t)0x2e37, (q15_t)0x13c3, (q15_t)0x2e40, (q15_t)0x13cc, (q15_t)0x2e49, (q15_t)0x13d5, (q15_t)0x2e51, + (q15_t)0x13df, (q15_t)0x2e5a, (q15_t)0x13e8, (q15_t)0x2e63, (q15_t)0x13f1, (q15_t)0x2e6b, (q15_t)0x13fa, (q15_t)0x2e74, + (q15_t)0x1403, (q15_t)0x2e7d, (q15_t)0x140c, (q15_t)0x2e85, (q15_t)0x1415, (q15_t)0x2e8e, (q15_t)0x141e, (q15_t)0x2e97, + (q15_t)0x1428, (q15_t)0x2e9f, (q15_t)0x1431, (q15_t)0x2ea8, (q15_t)0x143a, (q15_t)0x2eb0, (q15_t)0x1443, (q15_t)0x2eb9, + (q15_t)0x144c, (q15_t)0x2ec2, (q15_t)0x1455, (q15_t)0x2eca, (q15_t)0x145f, (q15_t)0x2ed3, (q15_t)0x1468, (q15_t)0x2edb, + (q15_t)0x1471, (q15_t)0x2ee4, (q15_t)0x147a, (q15_t)0x2eec, (q15_t)0x1483, (q15_t)0x2ef5, (q15_t)0x148d, (q15_t)0x2efd, + (q15_t)0x1496, (q15_t)0x2f06, (q15_t)0x149f, (q15_t)0x2f0e, (q15_t)0x14a8, (q15_t)0x2f17, (q15_t)0x14b2, (q15_t)0x2f20, + (q15_t)0x14bb, (q15_t)0x2f28, (q15_t)0x14c4, (q15_t)0x2f30, (q15_t)0x14cd, (q15_t)0x2f39, (q15_t)0x14d7, (q15_t)0x2f41, + (q15_t)0x14e0, (q15_t)0x2f4a, (q15_t)0x14e9, (q15_t)0x2f52, (q15_t)0x14f3, (q15_t)0x2f5b, (q15_t)0x14fc, (q15_t)0x2f63, + (q15_t)0x1505, (q15_t)0x2f6c, (q15_t)0x150e, (q15_t)0x2f74, (q15_t)0x1518, (q15_t)0x2f7d, (q15_t)0x1521, (q15_t)0x2f85, + (q15_t)0x152a, (q15_t)0x2f8d, (q15_t)0x1534, (q15_t)0x2f96, (q15_t)0x153d, (q15_t)0x2f9e, (q15_t)0x1547, (q15_t)0x2fa7, + (q15_t)0x1550, (q15_t)0x2faf, (q15_t)0x1559, (q15_t)0x2fb7, (q15_t)0x1563, (q15_t)0x2fc0, (q15_t)0x156c, (q15_t)0x2fc8, + (q15_t)0x1575, (q15_t)0x2fd0, (q15_t)0x157f, (q15_t)0x2fd9, (q15_t)0x1588, (q15_t)0x2fe1, (q15_t)0x1592, (q15_t)0x2fea, + (q15_t)0x159b, (q15_t)0x2ff2, (q15_t)0x15a4, (q15_t)0x2ffa, (q15_t)0x15ae, (q15_t)0x3002, (q15_t)0x15b7, (q15_t)0x300b, + (q15_t)0x15c1, (q15_t)0x3013, (q15_t)0x15ca, (q15_t)0x301b, (q15_t)0x15d4, (q15_t)0x3024, (q15_t)0x15dd, (q15_t)0x302c, + (q15_t)0x15e6, (q15_t)0x3034, (q15_t)0x15f0, (q15_t)0x303c, (q15_t)0x15f9, (q15_t)0x3045, (q15_t)0x1603, (q15_t)0x304d, + (q15_t)0x160c, (q15_t)0x3055, (q15_t)0x1616, (q15_t)0x305d, (q15_t)0x161f, (q15_t)0x3066, (q15_t)0x1629, (q15_t)0x306e, + (q15_t)0x1632, (q15_t)0x3076, (q15_t)0x163c, (q15_t)0x307e, (q15_t)0x1645, (q15_t)0x3087, (q15_t)0x164f, (q15_t)0x308f, + (q15_t)0x1659, (q15_t)0x3097, (q15_t)0x1662, (q15_t)0x309f, (q15_t)0x166c, (q15_t)0x30a7, (q15_t)0x1675, (q15_t)0x30af, + (q15_t)0x167f, (q15_t)0x30b8, (q15_t)0x1688, (q15_t)0x30c0, (q15_t)0x1692, (q15_t)0x30c8, (q15_t)0x169b, (q15_t)0x30d0, + (q15_t)0x16a5, (q15_t)0x30d8, (q15_t)0x16af, (q15_t)0x30e0, (q15_t)0x16b8, (q15_t)0x30e8, (q15_t)0x16c2, (q15_t)0x30f0, + (q15_t)0x16cb, (q15_t)0x30f9, (q15_t)0x16d5, (q15_t)0x3101, (q15_t)0x16df, (q15_t)0x3109, (q15_t)0x16e8, (q15_t)0x3111, + (q15_t)0x16f2, (q15_t)0x3119, (q15_t)0x16fc, (q15_t)0x3121, (q15_t)0x1705, (q15_t)0x3129, (q15_t)0x170f, (q15_t)0x3131, + (q15_t)0x1719, (q15_t)0x3139, (q15_t)0x1722, (q15_t)0x3141, (q15_t)0x172c, (q15_t)0x3149, (q15_t)0x1736, (q15_t)0x3151, + (q15_t)0x173f, (q15_t)0x3159, (q15_t)0x1749, (q15_t)0x3161, (q15_t)0x1753, (q15_t)0x3169, (q15_t)0x175c, (q15_t)0x3171, + (q15_t)0x1766, (q15_t)0x3179, (q15_t)0x1770, (q15_t)0x3181, (q15_t)0x177a, (q15_t)0x3189, (q15_t)0x1783, (q15_t)0x3191, + (q15_t)0x178d, (q15_t)0x3199, (q15_t)0x1797, (q15_t)0x31a1, (q15_t)0x17a0, (q15_t)0x31a9, (q15_t)0x17aa, (q15_t)0x31b1, + (q15_t)0x17b4, (q15_t)0x31b9, (q15_t)0x17be, (q15_t)0x31c0, (q15_t)0x17c8, (q15_t)0x31c8, (q15_t)0x17d1, (q15_t)0x31d0, + (q15_t)0x17db, (q15_t)0x31d8, (q15_t)0x17e5, (q15_t)0x31e0, (q15_t)0x17ef, (q15_t)0x31e8, (q15_t)0x17f8, (q15_t)0x31f0, + (q15_t)0x1802, (q15_t)0x31f8, (q15_t)0x180c, (q15_t)0x31ff, (q15_t)0x1816, (q15_t)0x3207, (q15_t)0x1820, (q15_t)0x320f, + (q15_t)0x182a, (q15_t)0x3217, (q15_t)0x1833, (q15_t)0x321f, (q15_t)0x183d, (q15_t)0x3227, (q15_t)0x1847, (q15_t)0x322e, + (q15_t)0x1851, (q15_t)0x3236, (q15_t)0x185b, (q15_t)0x323e, (q15_t)0x1865, (q15_t)0x3246, (q15_t)0x186f, (q15_t)0x324e, + (q15_t)0x1878, (q15_t)0x3255, (q15_t)0x1882, (q15_t)0x325d, (q15_t)0x188c, (q15_t)0x3265, (q15_t)0x1896, (q15_t)0x326d, + (q15_t)0x18a0, (q15_t)0x3274, (q15_t)0x18aa, (q15_t)0x327c, (q15_t)0x18b4, (q15_t)0x3284, (q15_t)0x18be, (q15_t)0x328b, + (q15_t)0x18c8, (q15_t)0x3293, (q15_t)0x18d2, (q15_t)0x329b, (q15_t)0x18dc, (q15_t)0x32a3, (q15_t)0x18e6, (q15_t)0x32aa, + (q15_t)0x18ef, (q15_t)0x32b2, (q15_t)0x18f9, (q15_t)0x32ba, (q15_t)0x1903, (q15_t)0x32c1, (q15_t)0x190d, (q15_t)0x32c9, + (q15_t)0x1917, (q15_t)0x32d0, (q15_t)0x1921, (q15_t)0x32d8, (q15_t)0x192b, (q15_t)0x32e0, (q15_t)0x1935, (q15_t)0x32e7, + (q15_t)0x193f, (q15_t)0x32ef, (q15_t)0x1949, (q15_t)0x32f7, (q15_t)0x1953, (q15_t)0x32fe, (q15_t)0x195d, (q15_t)0x3306, + (q15_t)0x1967, (q15_t)0x330d, (q15_t)0x1971, (q15_t)0x3315, (q15_t)0x197b, (q15_t)0x331d, (q15_t)0x1985, (q15_t)0x3324, + (q15_t)0x198f, (q15_t)0x332c, (q15_t)0x199a, (q15_t)0x3333, (q15_t)0x19a4, (q15_t)0x333b, (q15_t)0x19ae, (q15_t)0x3342, + (q15_t)0x19b8, (q15_t)0x334a, (q15_t)0x19c2, (q15_t)0x3351, (q15_t)0x19cc, (q15_t)0x3359, (q15_t)0x19d6, (q15_t)0x3360, + (q15_t)0x19e0, (q15_t)0x3368, (q15_t)0x19ea, (q15_t)0x336f, (q15_t)0x19f4, (q15_t)0x3377, (q15_t)0x19fe, (q15_t)0x337e, + (q15_t)0x1a08, (q15_t)0x3386, (q15_t)0x1a13, (q15_t)0x338d, (q15_t)0x1a1d, (q15_t)0x3395, (q15_t)0x1a27, (q15_t)0x339c, + (q15_t)0x1a31, (q15_t)0x33a3, (q15_t)0x1a3b, (q15_t)0x33ab, (q15_t)0x1a45, (q15_t)0x33b2, (q15_t)0x1a4f, (q15_t)0x33ba, + (q15_t)0x1a5a, (q15_t)0x33c1, (q15_t)0x1a64, (q15_t)0x33c8, (q15_t)0x1a6e, (q15_t)0x33d0, (q15_t)0x1a78, (q15_t)0x33d7, + (q15_t)0x1a82, (q15_t)0x33df, (q15_t)0x1a8c, (q15_t)0x33e6, (q15_t)0x1a97, (q15_t)0x33ed, (q15_t)0x1aa1, (q15_t)0x33f5, + (q15_t)0x1aab, (q15_t)0x33fc, (q15_t)0x1ab5, (q15_t)0x3403, (q15_t)0x1abf, (q15_t)0x340b, (q15_t)0x1aca, (q15_t)0x3412, + (q15_t)0x1ad4, (q15_t)0x3419, (q15_t)0x1ade, (q15_t)0x3420, (q15_t)0x1ae8, (q15_t)0x3428, (q15_t)0x1af3, (q15_t)0x342f, + (q15_t)0x1afd, (q15_t)0x3436, (q15_t)0x1b07, (q15_t)0x343e, (q15_t)0x1b11, (q15_t)0x3445, (q15_t)0x1b1c, (q15_t)0x344c, + (q15_t)0x1b26, (q15_t)0x3453, (q15_t)0x1b30, (q15_t)0x345b, (q15_t)0x1b3b, (q15_t)0x3462, (q15_t)0x1b45, (q15_t)0x3469, + (q15_t)0x1b4f, (q15_t)0x3470, (q15_t)0x1b59, (q15_t)0x3477, (q15_t)0x1b64, (q15_t)0x347f, (q15_t)0x1b6e, (q15_t)0x3486, + (q15_t)0x1b78, (q15_t)0x348d, (q15_t)0x1b83, (q15_t)0x3494, (q15_t)0x1b8d, (q15_t)0x349b, (q15_t)0x1b97, (q15_t)0x34a2, + (q15_t)0x1ba2, (q15_t)0x34aa, (q15_t)0x1bac, (q15_t)0x34b1, (q15_t)0x1bb6, (q15_t)0x34b8, (q15_t)0x1bc1, (q15_t)0x34bf, + (q15_t)0x1bcb, (q15_t)0x34c6, (q15_t)0x1bd5, (q15_t)0x34cd, (q15_t)0x1be0, (q15_t)0x34d4, (q15_t)0x1bea, (q15_t)0x34db, + (q15_t)0x1bf5, (q15_t)0x34e2, (q15_t)0x1bff, (q15_t)0x34ea, (q15_t)0x1c09, (q15_t)0x34f1, (q15_t)0x1c14, (q15_t)0x34f8, + (q15_t)0x1c1e, (q15_t)0x34ff, (q15_t)0x1c29, (q15_t)0x3506, (q15_t)0x1c33, (q15_t)0x350d, (q15_t)0x1c3d, (q15_t)0x3514, + (q15_t)0x1c48, (q15_t)0x351b, (q15_t)0x1c52, (q15_t)0x3522, (q15_t)0x1c5d, (q15_t)0x3529, (q15_t)0x1c67, (q15_t)0x3530, + (q15_t)0x1c72, (q15_t)0x3537, (q15_t)0x1c7c, (q15_t)0x353e, (q15_t)0x1c86, (q15_t)0x3545, (q15_t)0x1c91, (q15_t)0x354c, + (q15_t)0x1c9b, (q15_t)0x3553, (q15_t)0x1ca6, (q15_t)0x355a, (q15_t)0x1cb0, (q15_t)0x3561, (q15_t)0x1cbb, (q15_t)0x3567, + (q15_t)0x1cc5, (q15_t)0x356e, (q15_t)0x1cd0, (q15_t)0x3575, (q15_t)0x1cda, (q15_t)0x357c, (q15_t)0x1ce5, (q15_t)0x3583, + (q15_t)0x1cef, (q15_t)0x358a, (q15_t)0x1cfa, (q15_t)0x3591, (q15_t)0x1d04, (q15_t)0x3598, (q15_t)0x1d0f, (q15_t)0x359f, + (q15_t)0x1d19, (q15_t)0x35a5, (q15_t)0x1d24, (q15_t)0x35ac, (q15_t)0x1d2e, (q15_t)0x35b3, (q15_t)0x1d39, (q15_t)0x35ba, + (q15_t)0x1d44, (q15_t)0x35c1, (q15_t)0x1d4e, (q15_t)0x35c8, (q15_t)0x1d59, (q15_t)0x35ce, (q15_t)0x1d63, (q15_t)0x35d5, + (q15_t)0x1d6e, (q15_t)0x35dc, (q15_t)0x1d78, (q15_t)0x35e3, (q15_t)0x1d83, (q15_t)0x35ea, (q15_t)0x1d8e, (q15_t)0x35f0, + (q15_t)0x1d98, (q15_t)0x35f7, (q15_t)0x1da3, (q15_t)0x35fe, (q15_t)0x1dad, (q15_t)0x3605, (q15_t)0x1db8, (q15_t)0x360b, + (q15_t)0x1dc3, (q15_t)0x3612, (q15_t)0x1dcd, (q15_t)0x3619, (q15_t)0x1dd8, (q15_t)0x3620, (q15_t)0x1de2, (q15_t)0x3626, + (q15_t)0x1ded, (q15_t)0x362d, (q15_t)0x1df8, (q15_t)0x3634, (q15_t)0x1e02, (q15_t)0x363a, (q15_t)0x1e0d, (q15_t)0x3641, + (q15_t)0x1e18, (q15_t)0x3648, (q15_t)0x1e22, (q15_t)0x364e, (q15_t)0x1e2d, (q15_t)0x3655, (q15_t)0x1e38, (q15_t)0x365c, + (q15_t)0x1e42, (q15_t)0x3662, (q15_t)0x1e4d, (q15_t)0x3669, (q15_t)0x1e58, (q15_t)0x366f, (q15_t)0x1e62, (q15_t)0x3676, + (q15_t)0x1e6d, (q15_t)0x367d, (q15_t)0x1e78, (q15_t)0x3683, (q15_t)0x1e83, (q15_t)0x368a, (q15_t)0x1e8d, (q15_t)0x3690, + (q15_t)0x1e98, (q15_t)0x3697, (q15_t)0x1ea3, (q15_t)0x369d, (q15_t)0x1ead, (q15_t)0x36a4, (q15_t)0x1eb8, (q15_t)0x36ab, + (q15_t)0x1ec3, (q15_t)0x36b1, (q15_t)0x1ece, (q15_t)0x36b8, (q15_t)0x1ed8, (q15_t)0x36be, (q15_t)0x1ee3, (q15_t)0x36c5, + (q15_t)0x1eee, (q15_t)0x36cb, (q15_t)0x1ef9, (q15_t)0x36d2, (q15_t)0x1f03, (q15_t)0x36d8, (q15_t)0x1f0e, (q15_t)0x36df, + (q15_t)0x1f19, (q15_t)0x36e5, (q15_t)0x1f24, (q15_t)0x36eb, (q15_t)0x1f2f, (q15_t)0x36f2, (q15_t)0x1f39, (q15_t)0x36f8, + (q15_t)0x1f44, (q15_t)0x36ff, (q15_t)0x1f4f, (q15_t)0x3705, (q15_t)0x1f5a, (q15_t)0x370c, (q15_t)0x1f65, (q15_t)0x3712, + (q15_t)0x1f6f, (q15_t)0x3718, (q15_t)0x1f7a, (q15_t)0x371f, (q15_t)0x1f85, (q15_t)0x3725, (q15_t)0x1f90, (q15_t)0x372c, + (q15_t)0x1f9b, (q15_t)0x3732, (q15_t)0x1fa5, (q15_t)0x3738, (q15_t)0x1fb0, (q15_t)0x373f, (q15_t)0x1fbb, (q15_t)0x3745, + (q15_t)0x1fc6, (q15_t)0x374b, (q15_t)0x1fd1, (q15_t)0x3752, (q15_t)0x1fdc, (q15_t)0x3758, (q15_t)0x1fe7, (q15_t)0x375e, + (q15_t)0x1ff1, (q15_t)0x3765, (q15_t)0x1ffc, (q15_t)0x376b, (q15_t)0x2007, (q15_t)0x3771, (q15_t)0x2012, (q15_t)0x3777, + (q15_t)0x201d, (q15_t)0x377e, (q15_t)0x2028, (q15_t)0x3784, (q15_t)0x2033, (q15_t)0x378a, (q15_t)0x203e, (q15_t)0x3790, + (q15_t)0x2049, (q15_t)0x3797, (q15_t)0x2054, (q15_t)0x379d, (q15_t)0x205e, (q15_t)0x37a3, (q15_t)0x2069, (q15_t)0x37a9, + (q15_t)0x2074, (q15_t)0x37b0, (q15_t)0x207f, (q15_t)0x37b6, (q15_t)0x208a, (q15_t)0x37bc, (q15_t)0x2095, (q15_t)0x37c2, + (q15_t)0x20a0, (q15_t)0x37c8, (q15_t)0x20ab, (q15_t)0x37ce, (q15_t)0x20b6, (q15_t)0x37d5, (q15_t)0x20c1, (q15_t)0x37db, + (q15_t)0x20cc, (q15_t)0x37e1, (q15_t)0x20d7, (q15_t)0x37e7, (q15_t)0x20e2, (q15_t)0x37ed, (q15_t)0x20ed, (q15_t)0x37f3, + (q15_t)0x20f8, (q15_t)0x37f9, (q15_t)0x2103, (q15_t)0x37ff, (q15_t)0x210e, (q15_t)0x3805, (q15_t)0x2119, (q15_t)0x380b, + (q15_t)0x2124, (q15_t)0x3812, (q15_t)0x212f, (q15_t)0x3818, (q15_t)0x213a, (q15_t)0x381e, (q15_t)0x2145, (q15_t)0x3824, + (q15_t)0x2150, (q15_t)0x382a, (q15_t)0x215b, (q15_t)0x3830, (q15_t)0x2166, (q15_t)0x3836, (q15_t)0x2171, (q15_t)0x383c, + (q15_t)0x217c, (q15_t)0x3842, (q15_t)0x2187, (q15_t)0x3848, (q15_t)0x2192, (q15_t)0x384e, (q15_t)0x219d, (q15_t)0x3854, + (q15_t)0x21a8, (q15_t)0x385a, (q15_t)0x21b3, (q15_t)0x3860, (q15_t)0x21be, (q15_t)0x3866, (q15_t)0x21ca, (q15_t)0x386b, + (q15_t)0x21d5, (q15_t)0x3871, (q15_t)0x21e0, (q15_t)0x3877, (q15_t)0x21eb, (q15_t)0x387d, (q15_t)0x21f6, (q15_t)0x3883, + (q15_t)0x2201, (q15_t)0x3889, (q15_t)0x220c, (q15_t)0x388f, (q15_t)0x2217, (q15_t)0x3895, (q15_t)0x2222, (q15_t)0x389b, + (q15_t)0x222d, (q15_t)0x38a1, (q15_t)0x2239, (q15_t)0x38a6, (q15_t)0x2244, (q15_t)0x38ac, (q15_t)0x224f, (q15_t)0x38b2, + (q15_t)0x225a, (q15_t)0x38b8, (q15_t)0x2265, (q15_t)0x38be, (q15_t)0x2270, (q15_t)0x38c3, (q15_t)0x227b, (q15_t)0x38c9, + (q15_t)0x2287, (q15_t)0x38cf, (q15_t)0x2292, (q15_t)0x38d5, (q15_t)0x229d, (q15_t)0x38db, (q15_t)0x22a8, (q15_t)0x38e0, + (q15_t)0x22b3, (q15_t)0x38e6, (q15_t)0x22be, (q15_t)0x38ec, (q15_t)0x22ca, (q15_t)0x38f2, (q15_t)0x22d5, (q15_t)0x38f7, + (q15_t)0x22e0, (q15_t)0x38fd, (q15_t)0x22eb, (q15_t)0x3903, (q15_t)0x22f6, (q15_t)0x3909, (q15_t)0x2301, (q15_t)0x390e, + (q15_t)0x230d, (q15_t)0x3914, (q15_t)0x2318, (q15_t)0x391a, (q15_t)0x2323, (q15_t)0x391f, (q15_t)0x232e, (q15_t)0x3925, + (q15_t)0x233a, (q15_t)0x392b, (q15_t)0x2345, (q15_t)0x3930, (q15_t)0x2350, (q15_t)0x3936, (q15_t)0x235b, (q15_t)0x393b, + (q15_t)0x2367, (q15_t)0x3941, (q15_t)0x2372, (q15_t)0x3947, (q15_t)0x237d, (q15_t)0x394c, (q15_t)0x2388, (q15_t)0x3952, + (q15_t)0x2394, (q15_t)0x3958, (q15_t)0x239f, (q15_t)0x395d, (q15_t)0x23aa, (q15_t)0x3963, (q15_t)0x23b5, (q15_t)0x3968, + (q15_t)0x23c1, (q15_t)0x396e, (q15_t)0x23cc, (q15_t)0x3973, (q15_t)0x23d7, (q15_t)0x3979, (q15_t)0x23e2, (q15_t)0x397e, + (q15_t)0x23ee, (q15_t)0x3984, (q15_t)0x23f9, (q15_t)0x3989, (q15_t)0x2404, (q15_t)0x398f, (q15_t)0x2410, (q15_t)0x3994, + (q15_t)0x241b, (q15_t)0x399a, (q15_t)0x2426, (q15_t)0x399f, (q15_t)0x2432, (q15_t)0x39a5, (q15_t)0x243d, (q15_t)0x39aa, + (q15_t)0x2448, (q15_t)0x39b0, (q15_t)0x2454, (q15_t)0x39b5, (q15_t)0x245f, (q15_t)0x39bb, (q15_t)0x246a, (q15_t)0x39c0, + (q15_t)0x2476, (q15_t)0x39c5, (q15_t)0x2481, (q15_t)0x39cb, (q15_t)0x248c, (q15_t)0x39d0, (q15_t)0x2498, (q15_t)0x39d6, + (q15_t)0x24a3, (q15_t)0x39db, (q15_t)0x24ae, (q15_t)0x39e0, (q15_t)0x24ba, (q15_t)0x39e6, (q15_t)0x24c5, (q15_t)0x39eb, + (q15_t)0x24d0, (q15_t)0x39f0, (q15_t)0x24dc, (q15_t)0x39f6, (q15_t)0x24e7, (q15_t)0x39fb, (q15_t)0x24f3, (q15_t)0x3a00, + (q15_t)0x24fe, (q15_t)0x3a06, (q15_t)0x2509, (q15_t)0x3a0b, (q15_t)0x2515, (q15_t)0x3a10, (q15_t)0x2520, (q15_t)0x3a16, + (q15_t)0x252c, (q15_t)0x3a1b, (q15_t)0x2537, (q15_t)0x3a20, (q15_t)0x2542, (q15_t)0x3a25, (q15_t)0x254e, (q15_t)0x3a2b, + (q15_t)0x2559, (q15_t)0x3a30, (q15_t)0x2565, (q15_t)0x3a35, (q15_t)0x2570, (q15_t)0x3a3a, (q15_t)0x257c, (q15_t)0x3a3f, + (q15_t)0x2587, (q15_t)0x3a45, (q15_t)0x2592, (q15_t)0x3a4a, (q15_t)0x259e, (q15_t)0x3a4f, (q15_t)0x25a9, (q15_t)0x3a54, + (q15_t)0x25b5, (q15_t)0x3a59, (q15_t)0x25c0, (q15_t)0x3a5f, (q15_t)0x25cc, (q15_t)0x3a64, (q15_t)0x25d7, (q15_t)0x3a69, + (q15_t)0x25e3, (q15_t)0x3a6e, (q15_t)0x25ee, (q15_t)0x3a73, (q15_t)0x25fa, (q15_t)0x3a78, (q15_t)0x2605, (q15_t)0x3a7d, + (q15_t)0x2611, (q15_t)0x3a82, (q15_t)0x261c, (q15_t)0x3a88, (q15_t)0x2628, (q15_t)0x3a8d, (q15_t)0x2633, (q15_t)0x3a92, + (q15_t)0x263f, (q15_t)0x3a97, (q15_t)0x264a, (q15_t)0x3a9c, (q15_t)0x2656, (q15_t)0x3aa1, (q15_t)0x2661, (q15_t)0x3aa6, + (q15_t)0x266d, (q15_t)0x3aab, (q15_t)0x2678, (q15_t)0x3ab0, (q15_t)0x2684, (q15_t)0x3ab5, (q15_t)0x268f, (q15_t)0x3aba, + (q15_t)0x269b, (q15_t)0x3abf, (q15_t)0x26a6, (q15_t)0x3ac4, (q15_t)0x26b2, (q15_t)0x3ac9, (q15_t)0x26bd, (q15_t)0x3ace, + (q15_t)0x26c9, (q15_t)0x3ad3, (q15_t)0x26d4, (q15_t)0x3ad8, (q15_t)0x26e0, (q15_t)0x3add, (q15_t)0x26ec, (q15_t)0x3ae2, + (q15_t)0x26f7, (q15_t)0x3ae6, (q15_t)0x2703, (q15_t)0x3aeb, (q15_t)0x270e, (q15_t)0x3af0, (q15_t)0x271a, (q15_t)0x3af5, + (q15_t)0x2725, (q15_t)0x3afa, (q15_t)0x2731, (q15_t)0x3aff, (q15_t)0x273d, (q15_t)0x3b04, (q15_t)0x2748, (q15_t)0x3b09, + (q15_t)0x2754, (q15_t)0x3b0e, (q15_t)0x275f, (q15_t)0x3b12, (q15_t)0x276b, (q15_t)0x3b17, (q15_t)0x2777, (q15_t)0x3b1c, + (q15_t)0x2782, (q15_t)0x3b21, (q15_t)0x278e, (q15_t)0x3b26, (q15_t)0x2799, (q15_t)0x3b2a, (q15_t)0x27a5, (q15_t)0x3b2f, + (q15_t)0x27b1, (q15_t)0x3b34, (q15_t)0x27bc, (q15_t)0x3b39, (q15_t)0x27c8, (q15_t)0x3b3e, (q15_t)0x27d3, (q15_t)0x3b42, + (q15_t)0x27df, (q15_t)0x3b47, (q15_t)0x27eb, (q15_t)0x3b4c, (q15_t)0x27f6, (q15_t)0x3b50, (q15_t)0x2802, (q15_t)0x3b55, + (q15_t)0x280e, (q15_t)0x3b5a, (q15_t)0x2819, (q15_t)0x3b5f, (q15_t)0x2825, (q15_t)0x3b63, (q15_t)0x2831, (q15_t)0x3b68, + (q15_t)0x283c, (q15_t)0x3b6d, (q15_t)0x2848, (q15_t)0x3b71, (q15_t)0x2854, (q15_t)0x3b76, (q15_t)0x285f, (q15_t)0x3b7b, + (q15_t)0x286b, (q15_t)0x3b7f, (q15_t)0x2877, (q15_t)0x3b84, (q15_t)0x2882, (q15_t)0x3b88, (q15_t)0x288e, (q15_t)0x3b8d, + (q15_t)0x289a, (q15_t)0x3b92, (q15_t)0x28a5, (q15_t)0x3b96, (q15_t)0x28b1, (q15_t)0x3b9b, (q15_t)0x28bd, (q15_t)0x3b9f, + (q15_t)0x28c9, (q15_t)0x3ba4, (q15_t)0x28d4, (q15_t)0x3ba9, (q15_t)0x28e0, (q15_t)0x3bad, (q15_t)0x28ec, (q15_t)0x3bb2, + (q15_t)0x28f7, (q15_t)0x3bb6, (q15_t)0x2903, (q15_t)0x3bbb, (q15_t)0x290f, (q15_t)0x3bbf, (q15_t)0x291b, (q15_t)0x3bc4, + (q15_t)0x2926, (q15_t)0x3bc8, (q15_t)0x2932, (q15_t)0x3bcd, (q15_t)0x293e, (q15_t)0x3bd1, (q15_t)0x294a, (q15_t)0x3bd6, + (q15_t)0x2955, (q15_t)0x3bda, (q15_t)0x2961, (q15_t)0x3bde, (q15_t)0x296d, (q15_t)0x3be3, (q15_t)0x2979, (q15_t)0x3be7, + (q15_t)0x2984, (q15_t)0x3bec, (q15_t)0x2990, (q15_t)0x3bf0, (q15_t)0x299c, (q15_t)0x3bf5, (q15_t)0x29a8, (q15_t)0x3bf9, + (q15_t)0x29b4, (q15_t)0x3bfd, (q15_t)0x29bf, (q15_t)0x3c02, (q15_t)0x29cb, (q15_t)0x3c06, (q15_t)0x29d7, (q15_t)0x3c0a, + (q15_t)0x29e3, (q15_t)0x3c0f, (q15_t)0x29ee, (q15_t)0x3c13, (q15_t)0x29fa, (q15_t)0x3c17, (q15_t)0x2a06, (q15_t)0x3c1c, + (q15_t)0x2a12, (q15_t)0x3c20, (q15_t)0x2a1e, (q15_t)0x3c24, (q15_t)0x2a29, (q15_t)0x3c29, (q15_t)0x2a35, (q15_t)0x3c2d, + (q15_t)0x2a41, (q15_t)0x3c31, (q15_t)0x2a4d, (q15_t)0x3c36, (q15_t)0x2a59, (q15_t)0x3c3a, (q15_t)0x2a65, (q15_t)0x3c3e, + (q15_t)0x2a70, (q15_t)0x3c42, (q15_t)0x2a7c, (q15_t)0x3c46, (q15_t)0x2a88, (q15_t)0x3c4b, (q15_t)0x2a94, (q15_t)0x3c4f, + (q15_t)0x2aa0, (q15_t)0x3c53, (q15_t)0x2aac, (q15_t)0x3c57, (q15_t)0x2ab7, (q15_t)0x3c5b, (q15_t)0x2ac3, (q15_t)0x3c60, + (q15_t)0x2acf, (q15_t)0x3c64, (q15_t)0x2adb, (q15_t)0x3c68, (q15_t)0x2ae7, (q15_t)0x3c6c, (q15_t)0x2af3, (q15_t)0x3c70, + (q15_t)0x2aff, (q15_t)0x3c74, (q15_t)0x2b0a, (q15_t)0x3c79, (q15_t)0x2b16, (q15_t)0x3c7d, (q15_t)0x2b22, (q15_t)0x3c81, + (q15_t)0x2b2e, (q15_t)0x3c85, (q15_t)0x2b3a, (q15_t)0x3c89, (q15_t)0x2b46, (q15_t)0x3c8d, (q15_t)0x2b52, (q15_t)0x3c91, + (q15_t)0x2b5e, (q15_t)0x3c95, (q15_t)0x2b6a, (q15_t)0x3c99, (q15_t)0x2b75, (q15_t)0x3c9d, (q15_t)0x2b81, (q15_t)0x3ca1, + (q15_t)0x2b8d, (q15_t)0x3ca5, (q15_t)0x2b99, (q15_t)0x3ca9, (q15_t)0x2ba5, (q15_t)0x3cad, (q15_t)0x2bb1, (q15_t)0x3cb1, + (q15_t)0x2bbd, (q15_t)0x3cb5, (q15_t)0x2bc9, (q15_t)0x3cb9, (q15_t)0x2bd5, (q15_t)0x3cbd, (q15_t)0x2be1, (q15_t)0x3cc1, + (q15_t)0x2bed, (q15_t)0x3cc5, (q15_t)0x2bf9, (q15_t)0x3cc9, (q15_t)0x2c05, (q15_t)0x3ccd, (q15_t)0x2c10, (q15_t)0x3cd1, + (q15_t)0x2c1c, (q15_t)0x3cd5, (q15_t)0x2c28, (q15_t)0x3cd9, (q15_t)0x2c34, (q15_t)0x3cdd, (q15_t)0x2c40, (q15_t)0x3ce0, + (q15_t)0x2c4c, (q15_t)0x3ce4, (q15_t)0x2c58, (q15_t)0x3ce8, (q15_t)0x2c64, (q15_t)0x3cec, (q15_t)0x2c70, (q15_t)0x3cf0, + (q15_t)0x2c7c, (q15_t)0x3cf4, (q15_t)0x2c88, (q15_t)0x3cf8, (q15_t)0x2c94, (q15_t)0x3cfb, (q15_t)0x2ca0, (q15_t)0x3cff, + (q15_t)0x2cac, (q15_t)0x3d03, (q15_t)0x2cb8, (q15_t)0x3d07, (q15_t)0x2cc4, (q15_t)0x3d0b, (q15_t)0x2cd0, (q15_t)0x3d0e, + (q15_t)0x2cdc, (q15_t)0x3d12, (q15_t)0x2ce8, (q15_t)0x3d16, (q15_t)0x2cf4, (q15_t)0x3d1a, (q15_t)0x2d00, (q15_t)0x3d1d, + (q15_t)0x2d0c, (q15_t)0x3d21, (q15_t)0x2d18, (q15_t)0x3d25, (q15_t)0x2d24, (q15_t)0x3d28, (q15_t)0x2d30, (q15_t)0x3d2c, + (q15_t)0x2d3c, (q15_t)0x3d30, (q15_t)0x2d48, (q15_t)0x3d34, (q15_t)0x2d54, (q15_t)0x3d37, (q15_t)0x2d60, (q15_t)0x3d3b, + (q15_t)0x2d6c, (q15_t)0x3d3f, (q15_t)0x2d78, (q15_t)0x3d42, (q15_t)0x2d84, (q15_t)0x3d46, (q15_t)0x2d90, (q15_t)0x3d49, + (q15_t)0x2d9c, (q15_t)0x3d4d, (q15_t)0x2da8, (q15_t)0x3d51, (q15_t)0x2db4, (q15_t)0x3d54, (q15_t)0x2dc0, (q15_t)0x3d58, + (q15_t)0x2dcc, (q15_t)0x3d5b, (q15_t)0x2dd8, (q15_t)0x3d5f, (q15_t)0x2de4, (q15_t)0x3d63, (q15_t)0x2df0, (q15_t)0x3d66, + (q15_t)0x2dfc, (q15_t)0x3d6a, (q15_t)0x2e09, (q15_t)0x3d6d, (q15_t)0x2e15, (q15_t)0x3d71, (q15_t)0x2e21, (q15_t)0x3d74, + (q15_t)0x2e2d, (q15_t)0x3d78, (q15_t)0x2e39, (q15_t)0x3d7b, (q15_t)0x2e45, (q15_t)0x3d7f, (q15_t)0x2e51, (q15_t)0x3d82, + (q15_t)0x2e5d, (q15_t)0x3d86, (q15_t)0x2e69, (q15_t)0x3d89, (q15_t)0x2e75, (q15_t)0x3d8d, (q15_t)0x2e81, (q15_t)0x3d90, + (q15_t)0x2e8d, (q15_t)0x3d93, (q15_t)0x2e99, (q15_t)0x3d97, (q15_t)0x2ea6, (q15_t)0x3d9a, (q15_t)0x2eb2, (q15_t)0x3d9e, + (q15_t)0x2ebe, (q15_t)0x3da1, (q15_t)0x2eca, (q15_t)0x3da4, (q15_t)0x2ed6, (q15_t)0x3da8, (q15_t)0x2ee2, (q15_t)0x3dab, + (q15_t)0x2eee, (q15_t)0x3daf, (q15_t)0x2efa, (q15_t)0x3db2, (q15_t)0x2f06, (q15_t)0x3db5, (q15_t)0x2f13, (q15_t)0x3db9, + (q15_t)0x2f1f, (q15_t)0x3dbc, (q15_t)0x2f2b, (q15_t)0x3dbf, (q15_t)0x2f37, (q15_t)0x3dc2, (q15_t)0x2f43, (q15_t)0x3dc6, + (q15_t)0x2f4f, (q15_t)0x3dc9, (q15_t)0x2f5b, (q15_t)0x3dcc, (q15_t)0x2f67, (q15_t)0x3dd0, (q15_t)0x2f74, (q15_t)0x3dd3, + (q15_t)0x2f80, (q15_t)0x3dd6, (q15_t)0x2f8c, (q15_t)0x3dd9, (q15_t)0x2f98, (q15_t)0x3ddd, (q15_t)0x2fa4, (q15_t)0x3de0, + (q15_t)0x2fb0, (q15_t)0x3de3, (q15_t)0x2fbc, (q15_t)0x3de6, (q15_t)0x2fc9, (q15_t)0x3de9, (q15_t)0x2fd5, (q15_t)0x3ded, + (q15_t)0x2fe1, (q15_t)0x3df0, (q15_t)0x2fed, (q15_t)0x3df3, (q15_t)0x2ff9, (q15_t)0x3df6, (q15_t)0x3005, (q15_t)0x3df9, + (q15_t)0x3012, (q15_t)0x3dfc, (q15_t)0x301e, (q15_t)0x3dff, (q15_t)0x302a, (q15_t)0x3e03, (q15_t)0x3036, (q15_t)0x3e06, + (q15_t)0x3042, (q15_t)0x3e09, (q15_t)0x304e, (q15_t)0x3e0c, (q15_t)0x305b, (q15_t)0x3e0f, (q15_t)0x3067, (q15_t)0x3e12, + (q15_t)0x3073, (q15_t)0x3e15, (q15_t)0x307f, (q15_t)0x3e18, (q15_t)0x308b, (q15_t)0x3e1b, (q15_t)0x3098, (q15_t)0x3e1e, + (q15_t)0x30a4, (q15_t)0x3e21, (q15_t)0x30b0, (q15_t)0x3e24, (q15_t)0x30bc, (q15_t)0x3e27, (q15_t)0x30c8, (q15_t)0x3e2a, + (q15_t)0x30d5, (q15_t)0x3e2d, (q15_t)0x30e1, (q15_t)0x3e30, (q15_t)0x30ed, (q15_t)0x3e33, (q15_t)0x30f9, (q15_t)0x3e36, + (q15_t)0x3105, (q15_t)0x3e39, (q15_t)0x3112, (q15_t)0x3e3c, (q15_t)0x311e, (q15_t)0x3e3f, (q15_t)0x312a, (q15_t)0x3e42, + (q15_t)0x3136, (q15_t)0x3e45, (q15_t)0x3143, (q15_t)0x3e48, (q15_t)0x314f, (q15_t)0x3e4a, (q15_t)0x315b, (q15_t)0x3e4d, + (q15_t)0x3167, (q15_t)0x3e50, (q15_t)0x3174, (q15_t)0x3e53, (q15_t)0x3180, (q15_t)0x3e56, (q15_t)0x318c, (q15_t)0x3e59, + (q15_t)0x3198, (q15_t)0x3e5c, (q15_t)0x31a4, (q15_t)0x3e5e, (q15_t)0x31b1, (q15_t)0x3e61, (q15_t)0x31bd, (q15_t)0x3e64, + (q15_t)0x31c9, (q15_t)0x3e67, (q15_t)0x31d5, (q15_t)0x3e6a, (q15_t)0x31e2, (q15_t)0x3e6c, (q15_t)0x31ee, (q15_t)0x3e6f, + (q15_t)0x31fa, (q15_t)0x3e72, (q15_t)0x3207, (q15_t)0x3e75, (q15_t)0x3213, (q15_t)0x3e77, (q15_t)0x321f, (q15_t)0x3e7a, + (q15_t)0x322b, (q15_t)0x3e7d, (q15_t)0x3238, (q15_t)0x3e80, (q15_t)0x3244, (q15_t)0x3e82, (q15_t)0x3250, (q15_t)0x3e85, + (q15_t)0x325c, (q15_t)0x3e88, (q15_t)0x3269, (q15_t)0x3e8a, (q15_t)0x3275, (q15_t)0x3e8d, (q15_t)0x3281, (q15_t)0x3e90, + (q15_t)0x328e, (q15_t)0x3e92, (q15_t)0x329a, (q15_t)0x3e95, (q15_t)0x32a6, (q15_t)0x3e98, (q15_t)0x32b2, (q15_t)0x3e9a, + (q15_t)0x32bf, (q15_t)0x3e9d, (q15_t)0x32cb, (q15_t)0x3e9f, (q15_t)0x32d7, (q15_t)0x3ea2, (q15_t)0x32e4, (q15_t)0x3ea5, + (q15_t)0x32f0, (q15_t)0x3ea7, (q15_t)0x32fc, (q15_t)0x3eaa, (q15_t)0x3308, (q15_t)0x3eac, (q15_t)0x3315, (q15_t)0x3eaf, + (q15_t)0x3321, (q15_t)0x3eb1, (q15_t)0x332d, (q15_t)0x3eb4, (q15_t)0x333a, (q15_t)0x3eb6, (q15_t)0x3346, (q15_t)0x3eb9, + (q15_t)0x3352, (q15_t)0x3ebb, (q15_t)0x335f, (q15_t)0x3ebe, (q15_t)0x336b, (q15_t)0x3ec0, (q15_t)0x3377, (q15_t)0x3ec3, + (q15_t)0x3384, (q15_t)0x3ec5, (q15_t)0x3390, (q15_t)0x3ec8, (q15_t)0x339c, (q15_t)0x3eca, (q15_t)0x33a9, (q15_t)0x3ecc, + (q15_t)0x33b5, (q15_t)0x3ecf, (q15_t)0x33c1, (q15_t)0x3ed1, (q15_t)0x33ce, (q15_t)0x3ed4, (q15_t)0x33da, (q15_t)0x3ed6, + (q15_t)0x33e6, (q15_t)0x3ed8, (q15_t)0x33f3, (q15_t)0x3edb, (q15_t)0x33ff, (q15_t)0x3edd, (q15_t)0x340b, (q15_t)0x3ee0, + (q15_t)0x3418, (q15_t)0x3ee2, (q15_t)0x3424, (q15_t)0x3ee4, (q15_t)0x3430, (q15_t)0x3ee7, (q15_t)0x343d, (q15_t)0x3ee9, + (q15_t)0x3449, (q15_t)0x3eeb, (q15_t)0x3455, (q15_t)0x3eed, (q15_t)0x3462, (q15_t)0x3ef0, (q15_t)0x346e, (q15_t)0x3ef2, + (q15_t)0x347b, (q15_t)0x3ef4, (q15_t)0x3487, (q15_t)0x3ef7, (q15_t)0x3493, (q15_t)0x3ef9, (q15_t)0x34a0, (q15_t)0x3efb, + (q15_t)0x34ac, (q15_t)0x3efd, (q15_t)0x34b8, (q15_t)0x3f00, (q15_t)0x34c5, (q15_t)0x3f02, (q15_t)0x34d1, (q15_t)0x3f04, + (q15_t)0x34dd, (q15_t)0x3f06, (q15_t)0x34ea, (q15_t)0x3f08, (q15_t)0x34f6, (q15_t)0x3f0a, (q15_t)0x3503, (q15_t)0x3f0d, + (q15_t)0x350f, (q15_t)0x3f0f, (q15_t)0x351b, (q15_t)0x3f11, (q15_t)0x3528, (q15_t)0x3f13, (q15_t)0x3534, (q15_t)0x3f15, + (q15_t)0x3540, (q15_t)0x3f17, (q15_t)0x354d, (q15_t)0x3f19, (q15_t)0x3559, (q15_t)0x3f1c, (q15_t)0x3566, (q15_t)0x3f1e, + (q15_t)0x3572, (q15_t)0x3f20, (q15_t)0x357e, (q15_t)0x3f22, (q15_t)0x358b, (q15_t)0x3f24, (q15_t)0x3597, (q15_t)0x3f26, + (q15_t)0x35a4, (q15_t)0x3f28, (q15_t)0x35b0, (q15_t)0x3f2a, (q15_t)0x35bc, (q15_t)0x3f2c, (q15_t)0x35c9, (q15_t)0x3f2e, + (q15_t)0x35d5, (q15_t)0x3f30, (q15_t)0x35e2, (q15_t)0x3f32, (q15_t)0x35ee, (q15_t)0x3f34, (q15_t)0x35fa, (q15_t)0x3f36, + (q15_t)0x3607, (q15_t)0x3f38, (q15_t)0x3613, (q15_t)0x3f3a, (q15_t)0x3620, (q15_t)0x3f3c, (q15_t)0x362c, (q15_t)0x3f3e, + (q15_t)0x3639, (q15_t)0x3f40, (q15_t)0x3645, (q15_t)0x3f42, (q15_t)0x3651, (q15_t)0x3f43, (q15_t)0x365e, (q15_t)0x3f45, + (q15_t)0x366a, (q15_t)0x3f47, (q15_t)0x3677, (q15_t)0x3f49, (q15_t)0x3683, (q15_t)0x3f4b, (q15_t)0x3690, (q15_t)0x3f4d, + (q15_t)0x369c, (q15_t)0x3f4f, (q15_t)0x36a8, (q15_t)0x3f51, (q15_t)0x36b5, (q15_t)0x3f52, (q15_t)0x36c1, (q15_t)0x3f54, + (q15_t)0x36ce, (q15_t)0x3f56, (q15_t)0x36da, (q15_t)0x3f58, (q15_t)0x36e7, (q15_t)0x3f5a, (q15_t)0x36f3, (q15_t)0x3f5b, + (q15_t)0x36ff, (q15_t)0x3f5d, (q15_t)0x370c, (q15_t)0x3f5f, (q15_t)0x3718, (q15_t)0x3f61, (q15_t)0x3725, (q15_t)0x3f62, + (q15_t)0x3731, (q15_t)0x3f64, (q15_t)0x373e, (q15_t)0x3f66, (q15_t)0x374a, (q15_t)0x3f68, (q15_t)0x3757, (q15_t)0x3f69, + (q15_t)0x3763, (q15_t)0x3f6b, (q15_t)0x376f, (q15_t)0x3f6d, (q15_t)0x377c, (q15_t)0x3f6e, (q15_t)0x3788, (q15_t)0x3f70, + (q15_t)0x3795, (q15_t)0x3f72, (q15_t)0x37a1, (q15_t)0x3f73, (q15_t)0x37ae, (q15_t)0x3f75, (q15_t)0x37ba, (q15_t)0x3f77, + (q15_t)0x37c7, (q15_t)0x3f78, (q15_t)0x37d3, (q15_t)0x3f7a, (q15_t)0x37e0, (q15_t)0x3f7b, (q15_t)0x37ec, (q15_t)0x3f7d, + (q15_t)0x37f9, (q15_t)0x3f7f, (q15_t)0x3805, (q15_t)0x3f80, (q15_t)0x3811, (q15_t)0x3f82, (q15_t)0x381e, (q15_t)0x3f83, + (q15_t)0x382a, (q15_t)0x3f85, (q15_t)0x3837, (q15_t)0x3f86, (q15_t)0x3843, (q15_t)0x3f88, (q15_t)0x3850, (q15_t)0x3f89, + (q15_t)0x385c, (q15_t)0x3f8b, (q15_t)0x3869, (q15_t)0x3f8c, (q15_t)0x3875, (q15_t)0x3f8e, (q15_t)0x3882, (q15_t)0x3f8f, + (q15_t)0x388e, (q15_t)0x3f91, (q15_t)0x389b, (q15_t)0x3f92, (q15_t)0x38a7, (q15_t)0x3f94, (q15_t)0x38b4, (q15_t)0x3f95, + (q15_t)0x38c0, (q15_t)0x3f97, (q15_t)0x38cd, (q15_t)0x3f98, (q15_t)0x38d9, (q15_t)0x3f99, (q15_t)0x38e6, (q15_t)0x3f9b, + (q15_t)0x38f2, (q15_t)0x3f9c, (q15_t)0x38ff, (q15_t)0x3f9e, (q15_t)0x390b, (q15_t)0x3f9f, (q15_t)0x3918, (q15_t)0x3fa0, + (q15_t)0x3924, (q15_t)0x3fa2, (q15_t)0x3931, (q15_t)0x3fa3, (q15_t)0x393d, (q15_t)0x3fa4, (q15_t)0x394a, (q15_t)0x3fa6, + (q15_t)0x3956, (q15_t)0x3fa7, (q15_t)0x3963, (q15_t)0x3fa8, (q15_t)0x396f, (q15_t)0x3faa, (q15_t)0x397c, (q15_t)0x3fab, + (q15_t)0x3988, (q15_t)0x3fac, (q15_t)0x3995, (q15_t)0x3fad, (q15_t)0x39a1, (q15_t)0x3faf, (q15_t)0x39ae, (q15_t)0x3fb0, + (q15_t)0x39ba, (q15_t)0x3fb1, (q15_t)0x39c7, (q15_t)0x3fb2, (q15_t)0x39d3, (q15_t)0x3fb4, (q15_t)0x39e0, (q15_t)0x3fb5, + (q15_t)0x39ec, (q15_t)0x3fb6, (q15_t)0x39f9, (q15_t)0x3fb7, (q15_t)0x3a05, (q15_t)0x3fb8, (q15_t)0x3a12, (q15_t)0x3fb9, + (q15_t)0x3a1e, (q15_t)0x3fbb, (q15_t)0x3a2b, (q15_t)0x3fbc, (q15_t)0x3a37, (q15_t)0x3fbd, (q15_t)0x3a44, (q15_t)0x3fbe, + (q15_t)0x3a50, (q15_t)0x3fbf, (q15_t)0x3a5d, (q15_t)0x3fc0, (q15_t)0x3a69, (q15_t)0x3fc1, (q15_t)0x3a76, (q15_t)0x3fc3, + (q15_t)0x3a82, (q15_t)0x3fc4, (q15_t)0x3a8f, (q15_t)0x3fc5, (q15_t)0x3a9b, (q15_t)0x3fc6, (q15_t)0x3aa8, (q15_t)0x3fc7, + (q15_t)0x3ab4, (q15_t)0x3fc8, (q15_t)0x3ac1, (q15_t)0x3fc9, (q15_t)0x3acd, (q15_t)0x3fca, (q15_t)0x3ada, (q15_t)0x3fcb, + (q15_t)0x3ae6, (q15_t)0x3fcc, (q15_t)0x3af3, (q15_t)0x3fcd, (q15_t)0x3b00, (q15_t)0x3fce, (q15_t)0x3b0c, (q15_t)0x3fcf, + (q15_t)0x3b19, (q15_t)0x3fd0, (q15_t)0x3b25, (q15_t)0x3fd1, (q15_t)0x3b32, (q15_t)0x3fd2, (q15_t)0x3b3e, (q15_t)0x3fd3, + (q15_t)0x3b4b, (q15_t)0x3fd4, (q15_t)0x3b57, (q15_t)0x3fd5, (q15_t)0x3b64, (q15_t)0x3fd5, (q15_t)0x3b70, (q15_t)0x3fd6, + (q15_t)0x3b7d, (q15_t)0x3fd7, (q15_t)0x3b89, (q15_t)0x3fd8, (q15_t)0x3b96, (q15_t)0x3fd9, (q15_t)0x3ba2, (q15_t)0x3fda, + (q15_t)0x3baf, (q15_t)0x3fdb, (q15_t)0x3bbc, (q15_t)0x3fdc, (q15_t)0x3bc8, (q15_t)0x3fdc, (q15_t)0x3bd5, (q15_t)0x3fdd, + (q15_t)0x3be1, (q15_t)0x3fde, (q15_t)0x3bee, (q15_t)0x3fdf, (q15_t)0x3bfa, (q15_t)0x3fe0, (q15_t)0x3c07, (q15_t)0x3fe0, + (q15_t)0x3c13, (q15_t)0x3fe1, (q15_t)0x3c20, (q15_t)0x3fe2, (q15_t)0x3c2c, (q15_t)0x3fe3, (q15_t)0x3c39, (q15_t)0x3fe3, + (q15_t)0x3c45, (q15_t)0x3fe4, (q15_t)0x3c52, (q15_t)0x3fe5, (q15_t)0x3c5f, (q15_t)0x3fe6, (q15_t)0x3c6b, (q15_t)0x3fe6, + (q15_t)0x3c78, (q15_t)0x3fe7, (q15_t)0x3c84, (q15_t)0x3fe8, (q15_t)0x3c91, (q15_t)0x3fe8, (q15_t)0x3c9d, (q15_t)0x3fe9, + (q15_t)0x3caa, (q15_t)0x3fea, (q15_t)0x3cb6, (q15_t)0x3fea, (q15_t)0x3cc3, (q15_t)0x3feb, (q15_t)0x3cd0, (q15_t)0x3fec, + (q15_t)0x3cdc, (q15_t)0x3fec, (q15_t)0x3ce9, (q15_t)0x3fed, (q15_t)0x3cf5, (q15_t)0x3fed, (q15_t)0x3d02, (q15_t)0x3fee, + (q15_t)0x3d0e, (q15_t)0x3fef, (q15_t)0x3d1b, (q15_t)0x3fef, (q15_t)0x3d27, (q15_t)0x3ff0, (q15_t)0x3d34, (q15_t)0x3ff0, + (q15_t)0x3d40, (q15_t)0x3ff1, (q15_t)0x3d4d, (q15_t)0x3ff1, (q15_t)0x3d5a, (q15_t)0x3ff2, (q15_t)0x3d66, (q15_t)0x3ff2, + (q15_t)0x3d73, (q15_t)0x3ff3, (q15_t)0x3d7f, (q15_t)0x3ff3, (q15_t)0x3d8c, (q15_t)0x3ff4, (q15_t)0x3d98, (q15_t)0x3ff4, + (q15_t)0x3da5, (q15_t)0x3ff5, (q15_t)0x3db2, (q15_t)0x3ff5, (q15_t)0x3dbe, (q15_t)0x3ff6, (q15_t)0x3dcb, (q15_t)0x3ff6, + (q15_t)0x3dd7, (q15_t)0x3ff7, (q15_t)0x3de4, (q15_t)0x3ff7, (q15_t)0x3df0, (q15_t)0x3ff7, (q15_t)0x3dfd, (q15_t)0x3ff8, + (q15_t)0x3e09, (q15_t)0x3ff8, (q15_t)0x3e16, (q15_t)0x3ff9, (q15_t)0x3e23, (q15_t)0x3ff9, (q15_t)0x3e2f, (q15_t)0x3ff9, + (q15_t)0x3e3c, (q15_t)0x3ffa, (q15_t)0x3e48, (q15_t)0x3ffa, (q15_t)0x3e55, (q15_t)0x3ffa, (q15_t)0x3e61, (q15_t)0x3ffb, + (q15_t)0x3e6e, (q15_t)0x3ffb, (q15_t)0x3e7a, (q15_t)0x3ffb, (q15_t)0x3e87, (q15_t)0x3ffc, (q15_t)0x3e94, (q15_t)0x3ffc, + (q15_t)0x3ea0, (q15_t)0x3ffc, (q15_t)0x3ead, (q15_t)0x3ffc, (q15_t)0x3eb9, (q15_t)0x3ffd, (q15_t)0x3ec6, (q15_t)0x3ffd, + (q15_t)0x3ed2, (q15_t)0x3ffd, (q15_t)0x3edf, (q15_t)0x3ffd, (q15_t)0x3eec, (q15_t)0x3ffe, (q15_t)0x3ef8, (q15_t)0x3ffe, + (q15_t)0x3f05, (q15_t)0x3ffe, (q15_t)0x3f11, (q15_t)0x3ffe, (q15_t)0x3f1e, (q15_t)0x3ffe, (q15_t)0x3f2a, (q15_t)0x3fff, + (q15_t)0x3f37, (q15_t)0x3fff, (q15_t)0x3f44, (q15_t)0x3fff, (q15_t)0x3f50, (q15_t)0x3fff, (q15_t)0x3f5d, (q15_t)0x3fff, + (q15_t)0x3f69, (q15_t)0x3fff, (q15_t)0x3f76, (q15_t)0x3fff, (q15_t)0x3f82, (q15_t)0x4000, (q15_t)0x3f8f, (q15_t)0x4000, + (q15_t)0x3f9b, (q15_t)0x4000, (q15_t)0x3fa8, (q15_t)0x4000, (q15_t)0x3fb5, (q15_t)0x4000, (q15_t)0x3fc1, (q15_t)0x4000, + (q15_t)0x3fce, (q15_t)0x4000, (q15_t)0x3fda, (q15_t)0x4000, (q15_t)0x3fe7, (q15_t)0x4000, (q15_t)0x3ff3, (q15_t)0x4000, +}; + +/** + @par + Generation of real_CoefB array: + @par + n = 4096 +
for (i = 0; i < n; i++)
+  {
+     pBTable[2 * i]     = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+     pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ @par + Convert to fixed point Q15 format + round(pBTable[i] * pow(2, 15)) +*/ +const q15_t __ALIGNED(4) realCoefBQ15[8192] = { + (q15_t)0x4000, (q15_t)0x4000, (q15_t)0x400d, (q15_t)0x4000, (q15_t)0x4019, (q15_t)0x4000, (q15_t)0x4026, (q15_t)0x4000, + (q15_t)0x4032, (q15_t)0x4000, (q15_t)0x403f, (q15_t)0x4000, (q15_t)0x404b, (q15_t)0x4000, (q15_t)0x4058, (q15_t)0x4000, + (q15_t)0x4065, (q15_t)0x4000, (q15_t)0x4071, (q15_t)0x4000, (q15_t)0x407e, (q15_t)0x4000, (q15_t)0x408a, (q15_t)0x3fff, + (q15_t)0x4097, (q15_t)0x3fff, (q15_t)0x40a3, (q15_t)0x3fff, (q15_t)0x40b0, (q15_t)0x3fff, (q15_t)0x40bc, (q15_t)0x3fff, + (q15_t)0x40c9, (q15_t)0x3fff, (q15_t)0x40d6, (q15_t)0x3fff, (q15_t)0x40e2, (q15_t)0x3ffe, (q15_t)0x40ef, (q15_t)0x3ffe, + (q15_t)0x40fb, (q15_t)0x3ffe, (q15_t)0x4108, (q15_t)0x3ffe, (q15_t)0x4114, (q15_t)0x3ffe, (q15_t)0x4121, (q15_t)0x3ffd, + (q15_t)0x412e, (q15_t)0x3ffd, (q15_t)0x413a, (q15_t)0x3ffd, (q15_t)0x4147, (q15_t)0x3ffd, (q15_t)0x4153, (q15_t)0x3ffc, + (q15_t)0x4160, (q15_t)0x3ffc, (q15_t)0x416c, (q15_t)0x3ffc, (q15_t)0x4179, (q15_t)0x3ffc, (q15_t)0x4186, (q15_t)0x3ffb, + (q15_t)0x4192, (q15_t)0x3ffb, (q15_t)0x419f, (q15_t)0x3ffb, (q15_t)0x41ab, (q15_t)0x3ffa, (q15_t)0x41b8, (q15_t)0x3ffa, + (q15_t)0x41c4, (q15_t)0x3ffa, (q15_t)0x41d1, (q15_t)0x3ff9, (q15_t)0x41dd, (q15_t)0x3ff9, (q15_t)0x41ea, (q15_t)0x3ff9, + (q15_t)0x41f7, (q15_t)0x3ff8, (q15_t)0x4203, (q15_t)0x3ff8, (q15_t)0x4210, (q15_t)0x3ff7, (q15_t)0x421c, (q15_t)0x3ff7, + (q15_t)0x4229, (q15_t)0x3ff7, (q15_t)0x4235, (q15_t)0x3ff6, (q15_t)0x4242, (q15_t)0x3ff6, (q15_t)0x424e, (q15_t)0x3ff5, + (q15_t)0x425b, (q15_t)0x3ff5, (q15_t)0x4268, (q15_t)0x3ff4, (q15_t)0x4274, (q15_t)0x3ff4, (q15_t)0x4281, (q15_t)0x3ff3, + (q15_t)0x428d, (q15_t)0x3ff3, (q15_t)0x429a, (q15_t)0x3ff2, (q15_t)0x42a6, (q15_t)0x3ff2, (q15_t)0x42b3, (q15_t)0x3ff1, + (q15_t)0x42c0, (q15_t)0x3ff1, (q15_t)0x42cc, (q15_t)0x3ff0, (q15_t)0x42d9, (q15_t)0x3ff0, (q15_t)0x42e5, (q15_t)0x3fef, + (q15_t)0x42f2, (q15_t)0x3fef, (q15_t)0x42fe, (q15_t)0x3fee, (q15_t)0x430b, (q15_t)0x3fed, (q15_t)0x4317, (q15_t)0x3fed, + (q15_t)0x4324, (q15_t)0x3fec, (q15_t)0x4330, (q15_t)0x3fec, (q15_t)0x433d, (q15_t)0x3feb, (q15_t)0x434a, (q15_t)0x3fea, + (q15_t)0x4356, (q15_t)0x3fea, (q15_t)0x4363, (q15_t)0x3fe9, (q15_t)0x436f, (q15_t)0x3fe8, (q15_t)0x437c, (q15_t)0x3fe8, + (q15_t)0x4388, (q15_t)0x3fe7, (q15_t)0x4395, (q15_t)0x3fe6, (q15_t)0x43a1, (q15_t)0x3fe6, (q15_t)0x43ae, (q15_t)0x3fe5, + (q15_t)0x43bb, (q15_t)0x3fe4, (q15_t)0x43c7, (q15_t)0x3fe3, (q15_t)0x43d4, (q15_t)0x3fe3, (q15_t)0x43e0, (q15_t)0x3fe2, + (q15_t)0x43ed, (q15_t)0x3fe1, (q15_t)0x43f9, (q15_t)0x3fe0, (q15_t)0x4406, (q15_t)0x3fe0, (q15_t)0x4412, (q15_t)0x3fdf, + (q15_t)0x441f, (q15_t)0x3fde, (q15_t)0x442b, (q15_t)0x3fdd, (q15_t)0x4438, (q15_t)0x3fdc, (q15_t)0x4444, (q15_t)0x3fdc, + (q15_t)0x4451, (q15_t)0x3fdb, (q15_t)0x445e, (q15_t)0x3fda, (q15_t)0x446a, (q15_t)0x3fd9, (q15_t)0x4477, (q15_t)0x3fd8, + (q15_t)0x4483, (q15_t)0x3fd7, (q15_t)0x4490, (q15_t)0x3fd6, (q15_t)0x449c, (q15_t)0x3fd5, (q15_t)0x44a9, (q15_t)0x3fd5, + (q15_t)0x44b5, (q15_t)0x3fd4, (q15_t)0x44c2, (q15_t)0x3fd3, (q15_t)0x44ce, (q15_t)0x3fd2, (q15_t)0x44db, (q15_t)0x3fd1, + (q15_t)0x44e7, (q15_t)0x3fd0, (q15_t)0x44f4, (q15_t)0x3fcf, (q15_t)0x4500, (q15_t)0x3fce, (q15_t)0x450d, (q15_t)0x3fcd, + (q15_t)0x451a, (q15_t)0x3fcc, (q15_t)0x4526, (q15_t)0x3fcb, (q15_t)0x4533, (q15_t)0x3fca, (q15_t)0x453f, (q15_t)0x3fc9, + (q15_t)0x454c, (q15_t)0x3fc8, (q15_t)0x4558, (q15_t)0x3fc7, (q15_t)0x4565, (q15_t)0x3fc6, (q15_t)0x4571, (q15_t)0x3fc5, + (q15_t)0x457e, (q15_t)0x3fc4, (q15_t)0x458a, (q15_t)0x3fc3, (q15_t)0x4597, (q15_t)0x3fc1, (q15_t)0x45a3, (q15_t)0x3fc0, + (q15_t)0x45b0, (q15_t)0x3fbf, (q15_t)0x45bc, (q15_t)0x3fbe, (q15_t)0x45c9, (q15_t)0x3fbd, (q15_t)0x45d5, (q15_t)0x3fbc, + (q15_t)0x45e2, (q15_t)0x3fbb, (q15_t)0x45ee, (q15_t)0x3fb9, (q15_t)0x45fb, (q15_t)0x3fb8, (q15_t)0x4607, (q15_t)0x3fb7, + (q15_t)0x4614, (q15_t)0x3fb6, (q15_t)0x4620, (q15_t)0x3fb5, (q15_t)0x462d, (q15_t)0x3fb4, (q15_t)0x4639, (q15_t)0x3fb2, + (q15_t)0x4646, (q15_t)0x3fb1, (q15_t)0x4652, (q15_t)0x3fb0, (q15_t)0x465f, (q15_t)0x3faf, (q15_t)0x466b, (q15_t)0x3fad, + (q15_t)0x4678, (q15_t)0x3fac, (q15_t)0x4684, (q15_t)0x3fab, (q15_t)0x4691, (q15_t)0x3faa, (q15_t)0x469d, (q15_t)0x3fa8, + (q15_t)0x46aa, (q15_t)0x3fa7, (q15_t)0x46b6, (q15_t)0x3fa6, (q15_t)0x46c3, (q15_t)0x3fa4, (q15_t)0x46cf, (q15_t)0x3fa3, + (q15_t)0x46dc, (q15_t)0x3fa2, (q15_t)0x46e8, (q15_t)0x3fa0, (q15_t)0x46f5, (q15_t)0x3f9f, (q15_t)0x4701, (q15_t)0x3f9e, + (q15_t)0x470e, (q15_t)0x3f9c, (q15_t)0x471a, (q15_t)0x3f9b, (q15_t)0x4727, (q15_t)0x3f99, (q15_t)0x4733, (q15_t)0x3f98, + (q15_t)0x4740, (q15_t)0x3f97, (q15_t)0x474c, (q15_t)0x3f95, (q15_t)0x4759, (q15_t)0x3f94, (q15_t)0x4765, (q15_t)0x3f92, + (q15_t)0x4772, (q15_t)0x3f91, (q15_t)0x477e, (q15_t)0x3f8f, (q15_t)0x478b, (q15_t)0x3f8e, (q15_t)0x4797, (q15_t)0x3f8c, + (q15_t)0x47a4, (q15_t)0x3f8b, (q15_t)0x47b0, (q15_t)0x3f89, (q15_t)0x47bd, (q15_t)0x3f88, (q15_t)0x47c9, (q15_t)0x3f86, + (q15_t)0x47d6, (q15_t)0x3f85, (q15_t)0x47e2, (q15_t)0x3f83, (q15_t)0x47ef, (q15_t)0x3f82, (q15_t)0x47fb, (q15_t)0x3f80, + (q15_t)0x4807, (q15_t)0x3f7f, (q15_t)0x4814, (q15_t)0x3f7d, (q15_t)0x4820, (q15_t)0x3f7b, (q15_t)0x482d, (q15_t)0x3f7a, + (q15_t)0x4839, (q15_t)0x3f78, (q15_t)0x4846, (q15_t)0x3f77, (q15_t)0x4852, (q15_t)0x3f75, (q15_t)0x485f, (q15_t)0x3f73, + (q15_t)0x486b, (q15_t)0x3f72, (q15_t)0x4878, (q15_t)0x3f70, (q15_t)0x4884, (q15_t)0x3f6e, (q15_t)0x4891, (q15_t)0x3f6d, + (q15_t)0x489d, (q15_t)0x3f6b, (q15_t)0x48a9, (q15_t)0x3f69, (q15_t)0x48b6, (q15_t)0x3f68, (q15_t)0x48c2, (q15_t)0x3f66, + (q15_t)0x48cf, (q15_t)0x3f64, (q15_t)0x48db, (q15_t)0x3f62, (q15_t)0x48e8, (q15_t)0x3f61, (q15_t)0x48f4, (q15_t)0x3f5f, + (q15_t)0x4901, (q15_t)0x3f5d, (q15_t)0x490d, (q15_t)0x3f5b, (q15_t)0x4919, (q15_t)0x3f5a, (q15_t)0x4926, (q15_t)0x3f58, + (q15_t)0x4932, (q15_t)0x3f56, (q15_t)0x493f, (q15_t)0x3f54, (q15_t)0x494b, (q15_t)0x3f52, (q15_t)0x4958, (q15_t)0x3f51, + (q15_t)0x4964, (q15_t)0x3f4f, (q15_t)0x4970, (q15_t)0x3f4d, (q15_t)0x497d, (q15_t)0x3f4b, (q15_t)0x4989, (q15_t)0x3f49, + (q15_t)0x4996, (q15_t)0x3f47, (q15_t)0x49a2, (q15_t)0x3f45, (q15_t)0x49af, (q15_t)0x3f43, (q15_t)0x49bb, (q15_t)0x3f42, + (q15_t)0x49c7, (q15_t)0x3f40, (q15_t)0x49d4, (q15_t)0x3f3e, (q15_t)0x49e0, (q15_t)0x3f3c, (q15_t)0x49ed, (q15_t)0x3f3a, + (q15_t)0x49f9, (q15_t)0x3f38, (q15_t)0x4a06, (q15_t)0x3f36, (q15_t)0x4a12, (q15_t)0x3f34, (q15_t)0x4a1e, (q15_t)0x3f32, + (q15_t)0x4a2b, (q15_t)0x3f30, (q15_t)0x4a37, (q15_t)0x3f2e, (q15_t)0x4a44, (q15_t)0x3f2c, (q15_t)0x4a50, (q15_t)0x3f2a, + (q15_t)0x4a5c, (q15_t)0x3f28, (q15_t)0x4a69, (q15_t)0x3f26, (q15_t)0x4a75, (q15_t)0x3f24, (q15_t)0x4a82, (q15_t)0x3f22, + (q15_t)0x4a8e, (q15_t)0x3f20, (q15_t)0x4a9a, (q15_t)0x3f1e, (q15_t)0x4aa7, (q15_t)0x3f1c, (q15_t)0x4ab3, (q15_t)0x3f19, + (q15_t)0x4ac0, (q15_t)0x3f17, (q15_t)0x4acc, (q15_t)0x3f15, (q15_t)0x4ad8, (q15_t)0x3f13, (q15_t)0x4ae5, (q15_t)0x3f11, + (q15_t)0x4af1, (q15_t)0x3f0f, (q15_t)0x4afd, (q15_t)0x3f0d, (q15_t)0x4b0a, (q15_t)0x3f0a, (q15_t)0x4b16, (q15_t)0x3f08, + (q15_t)0x4b23, (q15_t)0x3f06, (q15_t)0x4b2f, (q15_t)0x3f04, (q15_t)0x4b3b, (q15_t)0x3f02, (q15_t)0x4b48, (q15_t)0x3f00, + (q15_t)0x4b54, (q15_t)0x3efd, (q15_t)0x4b60, (q15_t)0x3efb, (q15_t)0x4b6d, (q15_t)0x3ef9, (q15_t)0x4b79, (q15_t)0x3ef7, + (q15_t)0x4b85, (q15_t)0x3ef4, (q15_t)0x4b92, (q15_t)0x3ef2, (q15_t)0x4b9e, (q15_t)0x3ef0, (q15_t)0x4bab, (q15_t)0x3eed, + (q15_t)0x4bb7, (q15_t)0x3eeb, (q15_t)0x4bc3, (q15_t)0x3ee9, (q15_t)0x4bd0, (q15_t)0x3ee7, (q15_t)0x4bdc, (q15_t)0x3ee4, + (q15_t)0x4be8, (q15_t)0x3ee2, (q15_t)0x4bf5, (q15_t)0x3ee0, (q15_t)0x4c01, (q15_t)0x3edd, (q15_t)0x4c0d, (q15_t)0x3edb, + (q15_t)0x4c1a, (q15_t)0x3ed8, (q15_t)0x4c26, (q15_t)0x3ed6, (q15_t)0x4c32, (q15_t)0x3ed4, (q15_t)0x4c3f, (q15_t)0x3ed1, + (q15_t)0x4c4b, (q15_t)0x3ecf, (q15_t)0x4c57, (q15_t)0x3ecc, (q15_t)0x4c64, (q15_t)0x3eca, (q15_t)0x4c70, (q15_t)0x3ec8, + (q15_t)0x4c7c, (q15_t)0x3ec5, (q15_t)0x4c89, (q15_t)0x3ec3, (q15_t)0x4c95, (q15_t)0x3ec0, (q15_t)0x4ca1, (q15_t)0x3ebe, + (q15_t)0x4cae, (q15_t)0x3ebb, (q15_t)0x4cba, (q15_t)0x3eb9, (q15_t)0x4cc6, (q15_t)0x3eb6, (q15_t)0x4cd3, (q15_t)0x3eb4, + (q15_t)0x4cdf, (q15_t)0x3eb1, (q15_t)0x4ceb, (q15_t)0x3eaf, (q15_t)0x4cf8, (q15_t)0x3eac, (q15_t)0x4d04, (q15_t)0x3eaa, + (q15_t)0x4d10, (q15_t)0x3ea7, (q15_t)0x4d1c, (q15_t)0x3ea5, (q15_t)0x4d29, (q15_t)0x3ea2, (q15_t)0x4d35, (q15_t)0x3e9f, + (q15_t)0x4d41, (q15_t)0x3e9d, (q15_t)0x4d4e, (q15_t)0x3e9a, (q15_t)0x4d5a, (q15_t)0x3e98, (q15_t)0x4d66, (q15_t)0x3e95, + (q15_t)0x4d72, (q15_t)0x3e92, (q15_t)0x4d7f, (q15_t)0x3e90, (q15_t)0x4d8b, (q15_t)0x3e8d, (q15_t)0x4d97, (q15_t)0x3e8a, + (q15_t)0x4da4, (q15_t)0x3e88, (q15_t)0x4db0, (q15_t)0x3e85, (q15_t)0x4dbc, (q15_t)0x3e82, (q15_t)0x4dc8, (q15_t)0x3e80, + (q15_t)0x4dd5, (q15_t)0x3e7d, (q15_t)0x4de1, (q15_t)0x3e7a, (q15_t)0x4ded, (q15_t)0x3e77, (q15_t)0x4df9, (q15_t)0x3e75, + (q15_t)0x4e06, (q15_t)0x3e72, (q15_t)0x4e12, (q15_t)0x3e6f, (q15_t)0x4e1e, (q15_t)0x3e6c, (q15_t)0x4e2b, (q15_t)0x3e6a, + (q15_t)0x4e37, (q15_t)0x3e67, (q15_t)0x4e43, (q15_t)0x3e64, (q15_t)0x4e4f, (q15_t)0x3e61, (q15_t)0x4e5c, (q15_t)0x3e5e, + (q15_t)0x4e68, (q15_t)0x3e5c, (q15_t)0x4e74, (q15_t)0x3e59, (q15_t)0x4e80, (q15_t)0x3e56, (q15_t)0x4e8c, (q15_t)0x3e53, + (q15_t)0x4e99, (q15_t)0x3e50, (q15_t)0x4ea5, (q15_t)0x3e4d, (q15_t)0x4eb1, (q15_t)0x3e4a, (q15_t)0x4ebd, (q15_t)0x3e48, + (q15_t)0x4eca, (q15_t)0x3e45, (q15_t)0x4ed6, (q15_t)0x3e42, (q15_t)0x4ee2, (q15_t)0x3e3f, (q15_t)0x4eee, (q15_t)0x3e3c, + (q15_t)0x4efb, (q15_t)0x3e39, (q15_t)0x4f07, (q15_t)0x3e36, (q15_t)0x4f13, (q15_t)0x3e33, (q15_t)0x4f1f, (q15_t)0x3e30, + (q15_t)0x4f2b, (q15_t)0x3e2d, (q15_t)0x4f38, (q15_t)0x3e2a, (q15_t)0x4f44, (q15_t)0x3e27, (q15_t)0x4f50, (q15_t)0x3e24, + (q15_t)0x4f5c, (q15_t)0x3e21, (q15_t)0x4f68, (q15_t)0x3e1e, (q15_t)0x4f75, (q15_t)0x3e1b, (q15_t)0x4f81, (q15_t)0x3e18, + (q15_t)0x4f8d, (q15_t)0x3e15, (q15_t)0x4f99, (q15_t)0x3e12, (q15_t)0x4fa5, (q15_t)0x3e0f, (q15_t)0x4fb2, (q15_t)0x3e0c, + (q15_t)0x4fbe, (q15_t)0x3e09, (q15_t)0x4fca, (q15_t)0x3e06, (q15_t)0x4fd6, (q15_t)0x3e03, (q15_t)0x4fe2, (q15_t)0x3dff, + (q15_t)0x4fee, (q15_t)0x3dfc, (q15_t)0x4ffb, (q15_t)0x3df9, (q15_t)0x5007, (q15_t)0x3df6, (q15_t)0x5013, (q15_t)0x3df3, + (q15_t)0x501f, (q15_t)0x3df0, (q15_t)0x502b, (q15_t)0x3ded, (q15_t)0x5037, (q15_t)0x3de9, (q15_t)0x5044, (q15_t)0x3de6, + (q15_t)0x5050, (q15_t)0x3de3, (q15_t)0x505c, (q15_t)0x3de0, (q15_t)0x5068, (q15_t)0x3ddd, (q15_t)0x5074, (q15_t)0x3dd9, + (q15_t)0x5080, (q15_t)0x3dd6, (q15_t)0x508c, (q15_t)0x3dd3, (q15_t)0x5099, (q15_t)0x3dd0, (q15_t)0x50a5, (q15_t)0x3dcc, + (q15_t)0x50b1, (q15_t)0x3dc9, (q15_t)0x50bd, (q15_t)0x3dc6, (q15_t)0x50c9, (q15_t)0x3dc2, (q15_t)0x50d5, (q15_t)0x3dbf, + (q15_t)0x50e1, (q15_t)0x3dbc, (q15_t)0x50ed, (q15_t)0x3db9, (q15_t)0x50fa, (q15_t)0x3db5, (q15_t)0x5106, (q15_t)0x3db2, + (q15_t)0x5112, (q15_t)0x3daf, (q15_t)0x511e, (q15_t)0x3dab, (q15_t)0x512a, (q15_t)0x3da8, (q15_t)0x5136, (q15_t)0x3da4, + (q15_t)0x5142, (q15_t)0x3da1, (q15_t)0x514e, (q15_t)0x3d9e, (q15_t)0x515a, (q15_t)0x3d9a, (q15_t)0x5167, (q15_t)0x3d97, + (q15_t)0x5173, (q15_t)0x3d93, (q15_t)0x517f, (q15_t)0x3d90, (q15_t)0x518b, (q15_t)0x3d8d, (q15_t)0x5197, (q15_t)0x3d89, + (q15_t)0x51a3, (q15_t)0x3d86, (q15_t)0x51af, (q15_t)0x3d82, (q15_t)0x51bb, (q15_t)0x3d7f, (q15_t)0x51c7, (q15_t)0x3d7b, + (q15_t)0x51d3, (q15_t)0x3d78, (q15_t)0x51df, (q15_t)0x3d74, (q15_t)0x51eb, (q15_t)0x3d71, (q15_t)0x51f7, (q15_t)0x3d6d, + (q15_t)0x5204, (q15_t)0x3d6a, (q15_t)0x5210, (q15_t)0x3d66, (q15_t)0x521c, (q15_t)0x3d63, (q15_t)0x5228, (q15_t)0x3d5f, + (q15_t)0x5234, (q15_t)0x3d5b, (q15_t)0x5240, (q15_t)0x3d58, (q15_t)0x524c, (q15_t)0x3d54, (q15_t)0x5258, (q15_t)0x3d51, + (q15_t)0x5264, (q15_t)0x3d4d, (q15_t)0x5270, (q15_t)0x3d49, (q15_t)0x527c, (q15_t)0x3d46, (q15_t)0x5288, (q15_t)0x3d42, + (q15_t)0x5294, (q15_t)0x3d3f, (q15_t)0x52a0, (q15_t)0x3d3b, (q15_t)0x52ac, (q15_t)0x3d37, (q15_t)0x52b8, (q15_t)0x3d34, + (q15_t)0x52c4, (q15_t)0x3d30, (q15_t)0x52d0, (q15_t)0x3d2c, (q15_t)0x52dc, (q15_t)0x3d28, (q15_t)0x52e8, (q15_t)0x3d25, + (q15_t)0x52f4, (q15_t)0x3d21, (q15_t)0x5300, (q15_t)0x3d1d, (q15_t)0x530c, (q15_t)0x3d1a, (q15_t)0x5318, (q15_t)0x3d16, + (q15_t)0x5324, (q15_t)0x3d12, (q15_t)0x5330, (q15_t)0x3d0e, (q15_t)0x533c, (q15_t)0x3d0b, (q15_t)0x5348, (q15_t)0x3d07, + (q15_t)0x5354, (q15_t)0x3d03, (q15_t)0x5360, (q15_t)0x3cff, (q15_t)0x536c, (q15_t)0x3cfb, (q15_t)0x5378, (q15_t)0x3cf8, + (q15_t)0x5384, (q15_t)0x3cf4, (q15_t)0x5390, (q15_t)0x3cf0, (q15_t)0x539c, (q15_t)0x3cec, (q15_t)0x53a8, (q15_t)0x3ce8, + (q15_t)0x53b4, (q15_t)0x3ce4, (q15_t)0x53c0, (q15_t)0x3ce0, (q15_t)0x53cc, (q15_t)0x3cdd, (q15_t)0x53d8, (q15_t)0x3cd9, + (q15_t)0x53e4, (q15_t)0x3cd5, (q15_t)0x53f0, (q15_t)0x3cd1, (q15_t)0x53fb, (q15_t)0x3ccd, (q15_t)0x5407, (q15_t)0x3cc9, + (q15_t)0x5413, (q15_t)0x3cc5, (q15_t)0x541f, (q15_t)0x3cc1, (q15_t)0x542b, (q15_t)0x3cbd, (q15_t)0x5437, (q15_t)0x3cb9, + (q15_t)0x5443, (q15_t)0x3cb5, (q15_t)0x544f, (q15_t)0x3cb1, (q15_t)0x545b, (q15_t)0x3cad, (q15_t)0x5467, (q15_t)0x3ca9, + (q15_t)0x5473, (q15_t)0x3ca5, (q15_t)0x547f, (q15_t)0x3ca1, (q15_t)0x548b, (q15_t)0x3c9d, (q15_t)0x5496, (q15_t)0x3c99, + (q15_t)0x54a2, (q15_t)0x3c95, (q15_t)0x54ae, (q15_t)0x3c91, (q15_t)0x54ba, (q15_t)0x3c8d, (q15_t)0x54c6, (q15_t)0x3c89, + (q15_t)0x54d2, (q15_t)0x3c85, (q15_t)0x54de, (q15_t)0x3c81, (q15_t)0x54ea, (q15_t)0x3c7d, (q15_t)0x54f6, (q15_t)0x3c79, + (q15_t)0x5501, (q15_t)0x3c74, (q15_t)0x550d, (q15_t)0x3c70, (q15_t)0x5519, (q15_t)0x3c6c, (q15_t)0x5525, (q15_t)0x3c68, + (q15_t)0x5531, (q15_t)0x3c64, (q15_t)0x553d, (q15_t)0x3c60, (q15_t)0x5549, (q15_t)0x3c5b, (q15_t)0x5554, (q15_t)0x3c57, + (q15_t)0x5560, (q15_t)0x3c53, (q15_t)0x556c, (q15_t)0x3c4f, (q15_t)0x5578, (q15_t)0x3c4b, (q15_t)0x5584, (q15_t)0x3c46, + (q15_t)0x5590, (q15_t)0x3c42, (q15_t)0x559b, (q15_t)0x3c3e, (q15_t)0x55a7, (q15_t)0x3c3a, (q15_t)0x55b3, (q15_t)0x3c36, + (q15_t)0x55bf, (q15_t)0x3c31, (q15_t)0x55cb, (q15_t)0x3c2d, (q15_t)0x55d7, (q15_t)0x3c29, (q15_t)0x55e2, (q15_t)0x3c24, + (q15_t)0x55ee, (q15_t)0x3c20, (q15_t)0x55fa, (q15_t)0x3c1c, (q15_t)0x5606, (q15_t)0x3c17, (q15_t)0x5612, (q15_t)0x3c13, + (q15_t)0x561d, (q15_t)0x3c0f, (q15_t)0x5629, (q15_t)0x3c0a, (q15_t)0x5635, (q15_t)0x3c06, (q15_t)0x5641, (q15_t)0x3c02, + (q15_t)0x564c, (q15_t)0x3bfd, (q15_t)0x5658, (q15_t)0x3bf9, (q15_t)0x5664, (q15_t)0x3bf5, (q15_t)0x5670, (q15_t)0x3bf0, + (q15_t)0x567c, (q15_t)0x3bec, (q15_t)0x5687, (q15_t)0x3be7, (q15_t)0x5693, (q15_t)0x3be3, (q15_t)0x569f, (q15_t)0x3bde, + (q15_t)0x56ab, (q15_t)0x3bda, (q15_t)0x56b6, (q15_t)0x3bd6, (q15_t)0x56c2, (q15_t)0x3bd1, (q15_t)0x56ce, (q15_t)0x3bcd, + (q15_t)0x56da, (q15_t)0x3bc8, (q15_t)0x56e5, (q15_t)0x3bc4, (q15_t)0x56f1, (q15_t)0x3bbf, (q15_t)0x56fd, (q15_t)0x3bbb, + (q15_t)0x5709, (q15_t)0x3bb6, (q15_t)0x5714, (q15_t)0x3bb2, (q15_t)0x5720, (q15_t)0x3bad, (q15_t)0x572c, (q15_t)0x3ba9, + (q15_t)0x5737, (q15_t)0x3ba4, (q15_t)0x5743, (q15_t)0x3b9f, (q15_t)0x574f, (q15_t)0x3b9b, (q15_t)0x575b, (q15_t)0x3b96, + (q15_t)0x5766, (q15_t)0x3b92, (q15_t)0x5772, (q15_t)0x3b8d, (q15_t)0x577e, (q15_t)0x3b88, (q15_t)0x5789, (q15_t)0x3b84, + (q15_t)0x5795, (q15_t)0x3b7f, (q15_t)0x57a1, (q15_t)0x3b7b, (q15_t)0x57ac, (q15_t)0x3b76, (q15_t)0x57b8, (q15_t)0x3b71, + (q15_t)0x57c4, (q15_t)0x3b6d, (q15_t)0x57cf, (q15_t)0x3b68, (q15_t)0x57db, (q15_t)0x3b63, (q15_t)0x57e7, (q15_t)0x3b5f, + (q15_t)0x57f2, (q15_t)0x3b5a, (q15_t)0x57fe, (q15_t)0x3b55, (q15_t)0x580a, (q15_t)0x3b50, (q15_t)0x5815, (q15_t)0x3b4c, + (q15_t)0x5821, (q15_t)0x3b47, (q15_t)0x582d, (q15_t)0x3b42, (q15_t)0x5838, (q15_t)0x3b3e, (q15_t)0x5844, (q15_t)0x3b39, + (q15_t)0x584f, (q15_t)0x3b34, (q15_t)0x585b, (q15_t)0x3b2f, (q15_t)0x5867, (q15_t)0x3b2a, (q15_t)0x5872, (q15_t)0x3b26, + (q15_t)0x587e, (q15_t)0x3b21, (q15_t)0x5889, (q15_t)0x3b1c, (q15_t)0x5895, (q15_t)0x3b17, (q15_t)0x58a1, (q15_t)0x3b12, + (q15_t)0x58ac, (q15_t)0x3b0e, (q15_t)0x58b8, (q15_t)0x3b09, (q15_t)0x58c3, (q15_t)0x3b04, (q15_t)0x58cf, (q15_t)0x3aff, + (q15_t)0x58db, (q15_t)0x3afa, (q15_t)0x58e6, (q15_t)0x3af5, (q15_t)0x58f2, (q15_t)0x3af0, (q15_t)0x58fd, (q15_t)0x3aeb, + (q15_t)0x5909, (q15_t)0x3ae6, (q15_t)0x5914, (q15_t)0x3ae2, (q15_t)0x5920, (q15_t)0x3add, (q15_t)0x592c, (q15_t)0x3ad8, + (q15_t)0x5937, (q15_t)0x3ad3, (q15_t)0x5943, (q15_t)0x3ace, (q15_t)0x594e, (q15_t)0x3ac9, (q15_t)0x595a, (q15_t)0x3ac4, + (q15_t)0x5965, (q15_t)0x3abf, (q15_t)0x5971, (q15_t)0x3aba, (q15_t)0x597c, (q15_t)0x3ab5, (q15_t)0x5988, (q15_t)0x3ab0, + (q15_t)0x5993, (q15_t)0x3aab, (q15_t)0x599f, (q15_t)0x3aa6, (q15_t)0x59aa, (q15_t)0x3aa1, (q15_t)0x59b6, (q15_t)0x3a9c, + (q15_t)0x59c1, (q15_t)0x3a97, (q15_t)0x59cd, (q15_t)0x3a92, (q15_t)0x59d8, (q15_t)0x3a8d, (q15_t)0x59e4, (q15_t)0x3a88, + (q15_t)0x59ef, (q15_t)0x3a82, (q15_t)0x59fb, (q15_t)0x3a7d, (q15_t)0x5a06, (q15_t)0x3a78, (q15_t)0x5a12, (q15_t)0x3a73, + (q15_t)0x5a1d, (q15_t)0x3a6e, (q15_t)0x5a29, (q15_t)0x3a69, (q15_t)0x5a34, (q15_t)0x3a64, (q15_t)0x5a40, (q15_t)0x3a5f, + (q15_t)0x5a4b, (q15_t)0x3a59, (q15_t)0x5a57, (q15_t)0x3a54, (q15_t)0x5a62, (q15_t)0x3a4f, (q15_t)0x5a6e, (q15_t)0x3a4a, + (q15_t)0x5a79, (q15_t)0x3a45, (q15_t)0x5a84, (q15_t)0x3a3f, (q15_t)0x5a90, (q15_t)0x3a3a, (q15_t)0x5a9b, (q15_t)0x3a35, + (q15_t)0x5aa7, (q15_t)0x3a30, (q15_t)0x5ab2, (q15_t)0x3a2b, (q15_t)0x5abe, (q15_t)0x3a25, (q15_t)0x5ac9, (q15_t)0x3a20, + (q15_t)0x5ad4, (q15_t)0x3a1b, (q15_t)0x5ae0, (q15_t)0x3a16, (q15_t)0x5aeb, (q15_t)0x3a10, (q15_t)0x5af7, (q15_t)0x3a0b, + (q15_t)0x5b02, (q15_t)0x3a06, (q15_t)0x5b0d, (q15_t)0x3a00, (q15_t)0x5b19, (q15_t)0x39fb, (q15_t)0x5b24, (q15_t)0x39f6, + (q15_t)0x5b30, (q15_t)0x39f0, (q15_t)0x5b3b, (q15_t)0x39eb, (q15_t)0x5b46, (q15_t)0x39e6, (q15_t)0x5b52, (q15_t)0x39e0, + (q15_t)0x5b5d, (q15_t)0x39db, (q15_t)0x5b68, (q15_t)0x39d6, (q15_t)0x5b74, (q15_t)0x39d0, (q15_t)0x5b7f, (q15_t)0x39cb, + (q15_t)0x5b8a, (q15_t)0x39c5, (q15_t)0x5b96, (q15_t)0x39c0, (q15_t)0x5ba1, (q15_t)0x39bb, (q15_t)0x5bac, (q15_t)0x39b5, + (q15_t)0x5bb8, (q15_t)0x39b0, (q15_t)0x5bc3, (q15_t)0x39aa, (q15_t)0x5bce, (q15_t)0x39a5, (q15_t)0x5bda, (q15_t)0x399f, + (q15_t)0x5be5, (q15_t)0x399a, (q15_t)0x5bf0, (q15_t)0x3994, (q15_t)0x5bfc, (q15_t)0x398f, (q15_t)0x5c07, (q15_t)0x3989, + (q15_t)0x5c12, (q15_t)0x3984, (q15_t)0x5c1e, (q15_t)0x397e, (q15_t)0x5c29, (q15_t)0x3979, (q15_t)0x5c34, (q15_t)0x3973, + (q15_t)0x5c3f, (q15_t)0x396e, (q15_t)0x5c4b, (q15_t)0x3968, (q15_t)0x5c56, (q15_t)0x3963, (q15_t)0x5c61, (q15_t)0x395d, + (q15_t)0x5c6c, (q15_t)0x3958, (q15_t)0x5c78, (q15_t)0x3952, (q15_t)0x5c83, (q15_t)0x394c, (q15_t)0x5c8e, (q15_t)0x3947, + (q15_t)0x5c99, (q15_t)0x3941, (q15_t)0x5ca5, (q15_t)0x393b, (q15_t)0x5cb0, (q15_t)0x3936, (q15_t)0x5cbb, (q15_t)0x3930, + (q15_t)0x5cc6, (q15_t)0x392b, (q15_t)0x5cd2, (q15_t)0x3925, (q15_t)0x5cdd, (q15_t)0x391f, (q15_t)0x5ce8, (q15_t)0x391a, + (q15_t)0x5cf3, (q15_t)0x3914, (q15_t)0x5cff, (q15_t)0x390e, (q15_t)0x5d0a, (q15_t)0x3909, (q15_t)0x5d15, (q15_t)0x3903, + (q15_t)0x5d20, (q15_t)0x38fd, (q15_t)0x5d2b, (q15_t)0x38f7, (q15_t)0x5d36, (q15_t)0x38f2, (q15_t)0x5d42, (q15_t)0x38ec, + (q15_t)0x5d4d, (q15_t)0x38e6, (q15_t)0x5d58, (q15_t)0x38e0, (q15_t)0x5d63, (q15_t)0x38db, (q15_t)0x5d6e, (q15_t)0x38d5, + (q15_t)0x5d79, (q15_t)0x38cf, (q15_t)0x5d85, (q15_t)0x38c9, (q15_t)0x5d90, (q15_t)0x38c3, (q15_t)0x5d9b, (q15_t)0x38be, + (q15_t)0x5da6, (q15_t)0x38b8, (q15_t)0x5db1, (q15_t)0x38b2, (q15_t)0x5dbc, (q15_t)0x38ac, (q15_t)0x5dc7, (q15_t)0x38a6, + (q15_t)0x5dd3, (q15_t)0x38a1, (q15_t)0x5dde, (q15_t)0x389b, (q15_t)0x5de9, (q15_t)0x3895, (q15_t)0x5df4, (q15_t)0x388f, + (q15_t)0x5dff, (q15_t)0x3889, (q15_t)0x5e0a, (q15_t)0x3883, (q15_t)0x5e15, (q15_t)0x387d, (q15_t)0x5e20, (q15_t)0x3877, + (q15_t)0x5e2b, (q15_t)0x3871, (q15_t)0x5e36, (q15_t)0x386b, (q15_t)0x5e42, (q15_t)0x3866, (q15_t)0x5e4d, (q15_t)0x3860, + (q15_t)0x5e58, (q15_t)0x385a, (q15_t)0x5e63, (q15_t)0x3854, (q15_t)0x5e6e, (q15_t)0x384e, (q15_t)0x5e79, (q15_t)0x3848, + (q15_t)0x5e84, (q15_t)0x3842, (q15_t)0x5e8f, (q15_t)0x383c, (q15_t)0x5e9a, (q15_t)0x3836, (q15_t)0x5ea5, (q15_t)0x3830, + (q15_t)0x5eb0, (q15_t)0x382a, (q15_t)0x5ebb, (q15_t)0x3824, (q15_t)0x5ec6, (q15_t)0x381e, (q15_t)0x5ed1, (q15_t)0x3818, + (q15_t)0x5edc, (q15_t)0x3812, (q15_t)0x5ee7, (q15_t)0x380b, (q15_t)0x5ef2, (q15_t)0x3805, (q15_t)0x5efd, (q15_t)0x37ff, + (q15_t)0x5f08, (q15_t)0x37f9, (q15_t)0x5f13, (q15_t)0x37f3, (q15_t)0x5f1e, (q15_t)0x37ed, (q15_t)0x5f29, (q15_t)0x37e7, + (q15_t)0x5f34, (q15_t)0x37e1, (q15_t)0x5f3f, (q15_t)0x37db, (q15_t)0x5f4a, (q15_t)0x37d5, (q15_t)0x5f55, (q15_t)0x37ce, + (q15_t)0x5f60, (q15_t)0x37c8, (q15_t)0x5f6b, (q15_t)0x37c2, (q15_t)0x5f76, (q15_t)0x37bc, (q15_t)0x5f81, (q15_t)0x37b6, + (q15_t)0x5f8c, (q15_t)0x37b0, (q15_t)0x5f97, (q15_t)0x37a9, (q15_t)0x5fa2, (q15_t)0x37a3, (q15_t)0x5fac, (q15_t)0x379d, + (q15_t)0x5fb7, (q15_t)0x3797, (q15_t)0x5fc2, (q15_t)0x3790, (q15_t)0x5fcd, (q15_t)0x378a, (q15_t)0x5fd8, (q15_t)0x3784, + (q15_t)0x5fe3, (q15_t)0x377e, (q15_t)0x5fee, (q15_t)0x3777, (q15_t)0x5ff9, (q15_t)0x3771, (q15_t)0x6004, (q15_t)0x376b, + (q15_t)0x600f, (q15_t)0x3765, (q15_t)0x6019, (q15_t)0x375e, (q15_t)0x6024, (q15_t)0x3758, (q15_t)0x602f, (q15_t)0x3752, + (q15_t)0x603a, (q15_t)0x374b, (q15_t)0x6045, (q15_t)0x3745, (q15_t)0x6050, (q15_t)0x373f, (q15_t)0x605b, (q15_t)0x3738, + (q15_t)0x6065, (q15_t)0x3732, (q15_t)0x6070, (q15_t)0x372c, (q15_t)0x607b, (q15_t)0x3725, (q15_t)0x6086, (q15_t)0x371f, + (q15_t)0x6091, (q15_t)0x3718, (q15_t)0x609b, (q15_t)0x3712, (q15_t)0x60a6, (q15_t)0x370c, (q15_t)0x60b1, (q15_t)0x3705, + (q15_t)0x60bc, (q15_t)0x36ff, (q15_t)0x60c7, (q15_t)0x36f8, (q15_t)0x60d1, (q15_t)0x36f2, (q15_t)0x60dc, (q15_t)0x36eb, + (q15_t)0x60e7, (q15_t)0x36e5, (q15_t)0x60f2, (q15_t)0x36df, (q15_t)0x60fd, (q15_t)0x36d8, (q15_t)0x6107, (q15_t)0x36d2, + (q15_t)0x6112, (q15_t)0x36cb, (q15_t)0x611d, (q15_t)0x36c5, (q15_t)0x6128, (q15_t)0x36be, (q15_t)0x6132, (q15_t)0x36b8, + (q15_t)0x613d, (q15_t)0x36b1, (q15_t)0x6148, (q15_t)0x36ab, (q15_t)0x6153, (q15_t)0x36a4, (q15_t)0x615d, (q15_t)0x369d, + (q15_t)0x6168, (q15_t)0x3697, (q15_t)0x6173, (q15_t)0x3690, (q15_t)0x617d, (q15_t)0x368a, (q15_t)0x6188, (q15_t)0x3683, + (q15_t)0x6193, (q15_t)0x367d, (q15_t)0x619e, (q15_t)0x3676, (q15_t)0x61a8, (q15_t)0x366f, (q15_t)0x61b3, (q15_t)0x3669, + (q15_t)0x61be, (q15_t)0x3662, (q15_t)0x61c8, (q15_t)0x365c, (q15_t)0x61d3, (q15_t)0x3655, (q15_t)0x61de, (q15_t)0x364e, + (q15_t)0x61e8, (q15_t)0x3648, (q15_t)0x61f3, (q15_t)0x3641, (q15_t)0x61fe, (q15_t)0x363a, (q15_t)0x6208, (q15_t)0x3634, + (q15_t)0x6213, (q15_t)0x362d, (q15_t)0x621e, (q15_t)0x3626, (q15_t)0x6228, (q15_t)0x3620, (q15_t)0x6233, (q15_t)0x3619, + (q15_t)0x623d, (q15_t)0x3612, (q15_t)0x6248, (q15_t)0x360b, (q15_t)0x6253, (q15_t)0x3605, (q15_t)0x625d, (q15_t)0x35fe, + (q15_t)0x6268, (q15_t)0x35f7, (q15_t)0x6272, (q15_t)0x35f0, (q15_t)0x627d, (q15_t)0x35ea, (q15_t)0x6288, (q15_t)0x35e3, + (q15_t)0x6292, (q15_t)0x35dc, (q15_t)0x629d, (q15_t)0x35d5, (q15_t)0x62a7, (q15_t)0x35ce, (q15_t)0x62b2, (q15_t)0x35c8, + (q15_t)0x62bc, (q15_t)0x35c1, (q15_t)0x62c7, (q15_t)0x35ba, (q15_t)0x62d2, (q15_t)0x35b3, (q15_t)0x62dc, (q15_t)0x35ac, + (q15_t)0x62e7, (q15_t)0x35a5, (q15_t)0x62f1, (q15_t)0x359f, (q15_t)0x62fc, (q15_t)0x3598, (q15_t)0x6306, (q15_t)0x3591, + (q15_t)0x6311, (q15_t)0x358a, (q15_t)0x631b, (q15_t)0x3583, (q15_t)0x6326, (q15_t)0x357c, (q15_t)0x6330, (q15_t)0x3575, + (q15_t)0x633b, (q15_t)0x356e, (q15_t)0x6345, (q15_t)0x3567, (q15_t)0x6350, (q15_t)0x3561, (q15_t)0x635a, (q15_t)0x355a, + (q15_t)0x6365, (q15_t)0x3553, (q15_t)0x636f, (q15_t)0x354c, (q15_t)0x637a, (q15_t)0x3545, (q15_t)0x6384, (q15_t)0x353e, + (q15_t)0x638e, (q15_t)0x3537, (q15_t)0x6399, (q15_t)0x3530, (q15_t)0x63a3, (q15_t)0x3529, (q15_t)0x63ae, (q15_t)0x3522, + (q15_t)0x63b8, (q15_t)0x351b, (q15_t)0x63c3, (q15_t)0x3514, (q15_t)0x63cd, (q15_t)0x350d, (q15_t)0x63d7, (q15_t)0x3506, + (q15_t)0x63e2, (q15_t)0x34ff, (q15_t)0x63ec, (q15_t)0x34f8, (q15_t)0x63f7, (q15_t)0x34f1, (q15_t)0x6401, (q15_t)0x34ea, + (q15_t)0x640b, (q15_t)0x34e2, (q15_t)0x6416, (q15_t)0x34db, (q15_t)0x6420, (q15_t)0x34d4, (q15_t)0x642b, (q15_t)0x34cd, + (q15_t)0x6435, (q15_t)0x34c6, (q15_t)0x643f, (q15_t)0x34bf, (q15_t)0x644a, (q15_t)0x34b8, (q15_t)0x6454, (q15_t)0x34b1, + (q15_t)0x645e, (q15_t)0x34aa, (q15_t)0x6469, (q15_t)0x34a2, (q15_t)0x6473, (q15_t)0x349b, (q15_t)0x647d, (q15_t)0x3494, + (q15_t)0x6488, (q15_t)0x348d, (q15_t)0x6492, (q15_t)0x3486, (q15_t)0x649c, (q15_t)0x347f, (q15_t)0x64a7, (q15_t)0x3477, + (q15_t)0x64b1, (q15_t)0x3470, (q15_t)0x64bb, (q15_t)0x3469, (q15_t)0x64c5, (q15_t)0x3462, (q15_t)0x64d0, (q15_t)0x345b, + (q15_t)0x64da, (q15_t)0x3453, (q15_t)0x64e4, (q15_t)0x344c, (q15_t)0x64ef, (q15_t)0x3445, (q15_t)0x64f9, (q15_t)0x343e, + (q15_t)0x6503, (q15_t)0x3436, (q15_t)0x650d, (q15_t)0x342f, (q15_t)0x6518, (q15_t)0x3428, (q15_t)0x6522, (q15_t)0x3420, + (q15_t)0x652c, (q15_t)0x3419, (q15_t)0x6536, (q15_t)0x3412, (q15_t)0x6541, (q15_t)0x340b, (q15_t)0x654b, (q15_t)0x3403, + (q15_t)0x6555, (q15_t)0x33fc, (q15_t)0x655f, (q15_t)0x33f5, (q15_t)0x6569, (q15_t)0x33ed, (q15_t)0x6574, (q15_t)0x33e6, + (q15_t)0x657e, (q15_t)0x33df, (q15_t)0x6588, (q15_t)0x33d7, (q15_t)0x6592, (q15_t)0x33d0, (q15_t)0x659c, (q15_t)0x33c8, + (q15_t)0x65a6, (q15_t)0x33c1, (q15_t)0x65b1, (q15_t)0x33ba, (q15_t)0x65bb, (q15_t)0x33b2, (q15_t)0x65c5, (q15_t)0x33ab, + (q15_t)0x65cf, (q15_t)0x33a3, (q15_t)0x65d9, (q15_t)0x339c, (q15_t)0x65e3, (q15_t)0x3395, (q15_t)0x65ed, (q15_t)0x338d, + (q15_t)0x65f8, (q15_t)0x3386, (q15_t)0x6602, (q15_t)0x337e, (q15_t)0x660c, (q15_t)0x3377, (q15_t)0x6616, (q15_t)0x336f, + (q15_t)0x6620, (q15_t)0x3368, (q15_t)0x662a, (q15_t)0x3360, (q15_t)0x6634, (q15_t)0x3359, (q15_t)0x663e, (q15_t)0x3351, + (q15_t)0x6648, (q15_t)0x334a, (q15_t)0x6652, (q15_t)0x3342, (q15_t)0x665c, (q15_t)0x333b, (q15_t)0x6666, (q15_t)0x3333, + (q15_t)0x6671, (q15_t)0x332c, (q15_t)0x667b, (q15_t)0x3324, (q15_t)0x6685, (q15_t)0x331d, (q15_t)0x668f, (q15_t)0x3315, + (q15_t)0x6699, (q15_t)0x330d, (q15_t)0x66a3, (q15_t)0x3306, (q15_t)0x66ad, (q15_t)0x32fe, (q15_t)0x66b7, (q15_t)0x32f7, + (q15_t)0x66c1, (q15_t)0x32ef, (q15_t)0x66cb, (q15_t)0x32e7, (q15_t)0x66d5, (q15_t)0x32e0, (q15_t)0x66df, (q15_t)0x32d8, + (q15_t)0x66e9, (q15_t)0x32d0, (q15_t)0x66f3, (q15_t)0x32c9, (q15_t)0x66fd, (q15_t)0x32c1, (q15_t)0x6707, (q15_t)0x32ba, + (q15_t)0x6711, (q15_t)0x32b2, (q15_t)0x671a, (q15_t)0x32aa, (q15_t)0x6724, (q15_t)0x32a3, (q15_t)0x672e, (q15_t)0x329b, + (q15_t)0x6738, (q15_t)0x3293, (q15_t)0x6742, (q15_t)0x328b, (q15_t)0x674c, (q15_t)0x3284, (q15_t)0x6756, (q15_t)0x327c, + (q15_t)0x6760, (q15_t)0x3274, (q15_t)0x676a, (q15_t)0x326d, (q15_t)0x6774, (q15_t)0x3265, (q15_t)0x677e, (q15_t)0x325d, + (q15_t)0x6788, (q15_t)0x3255, (q15_t)0x6791, (q15_t)0x324e, (q15_t)0x679b, (q15_t)0x3246, (q15_t)0x67a5, (q15_t)0x323e, + (q15_t)0x67af, (q15_t)0x3236, (q15_t)0x67b9, (q15_t)0x322e, (q15_t)0x67c3, (q15_t)0x3227, (q15_t)0x67cd, (q15_t)0x321f, + (q15_t)0x67d6, (q15_t)0x3217, (q15_t)0x67e0, (q15_t)0x320f, (q15_t)0x67ea, (q15_t)0x3207, (q15_t)0x67f4, (q15_t)0x31ff, + (q15_t)0x67fe, (q15_t)0x31f8, (q15_t)0x6808, (q15_t)0x31f0, (q15_t)0x6811, (q15_t)0x31e8, (q15_t)0x681b, (q15_t)0x31e0, + (q15_t)0x6825, (q15_t)0x31d8, (q15_t)0x682f, (q15_t)0x31d0, (q15_t)0x6838, (q15_t)0x31c8, (q15_t)0x6842, (q15_t)0x31c0, + (q15_t)0x684c, (q15_t)0x31b9, (q15_t)0x6856, (q15_t)0x31b1, (q15_t)0x6860, (q15_t)0x31a9, (q15_t)0x6869, (q15_t)0x31a1, + (q15_t)0x6873, (q15_t)0x3199, (q15_t)0x687d, (q15_t)0x3191, (q15_t)0x6886, (q15_t)0x3189, (q15_t)0x6890, (q15_t)0x3181, + (q15_t)0x689a, (q15_t)0x3179, (q15_t)0x68a4, (q15_t)0x3171, (q15_t)0x68ad, (q15_t)0x3169, (q15_t)0x68b7, (q15_t)0x3161, + (q15_t)0x68c1, (q15_t)0x3159, (q15_t)0x68ca, (q15_t)0x3151, (q15_t)0x68d4, (q15_t)0x3149, (q15_t)0x68de, (q15_t)0x3141, + (q15_t)0x68e7, (q15_t)0x3139, (q15_t)0x68f1, (q15_t)0x3131, (q15_t)0x68fb, (q15_t)0x3129, (q15_t)0x6904, (q15_t)0x3121, + (q15_t)0x690e, (q15_t)0x3119, (q15_t)0x6918, (q15_t)0x3111, (q15_t)0x6921, (q15_t)0x3109, (q15_t)0x692b, (q15_t)0x3101, + (q15_t)0x6935, (q15_t)0x30f9, (q15_t)0x693e, (q15_t)0x30f0, (q15_t)0x6948, (q15_t)0x30e8, (q15_t)0x6951, (q15_t)0x30e0, + (q15_t)0x695b, (q15_t)0x30d8, (q15_t)0x6965, (q15_t)0x30d0, (q15_t)0x696e, (q15_t)0x30c8, (q15_t)0x6978, (q15_t)0x30c0, + (q15_t)0x6981, (q15_t)0x30b8, (q15_t)0x698b, (q15_t)0x30af, (q15_t)0x6994, (q15_t)0x30a7, (q15_t)0x699e, (q15_t)0x309f, + (q15_t)0x69a7, (q15_t)0x3097, (q15_t)0x69b1, (q15_t)0x308f, (q15_t)0x69bb, (q15_t)0x3087, (q15_t)0x69c4, (q15_t)0x307e, + (q15_t)0x69ce, (q15_t)0x3076, (q15_t)0x69d7, (q15_t)0x306e, (q15_t)0x69e1, (q15_t)0x3066, (q15_t)0x69ea, (q15_t)0x305d, + (q15_t)0x69f4, (q15_t)0x3055, (q15_t)0x69fd, (q15_t)0x304d, (q15_t)0x6a07, (q15_t)0x3045, (q15_t)0x6a10, (q15_t)0x303c, + (q15_t)0x6a1a, (q15_t)0x3034, (q15_t)0x6a23, (q15_t)0x302c, (q15_t)0x6a2c, (q15_t)0x3024, (q15_t)0x6a36, (q15_t)0x301b, + (q15_t)0x6a3f, (q15_t)0x3013, (q15_t)0x6a49, (q15_t)0x300b, (q15_t)0x6a52, (q15_t)0x3002, (q15_t)0x6a5c, (q15_t)0x2ffa, + (q15_t)0x6a65, (q15_t)0x2ff2, (q15_t)0x6a6e, (q15_t)0x2fea, (q15_t)0x6a78, (q15_t)0x2fe1, (q15_t)0x6a81, (q15_t)0x2fd9, + (q15_t)0x6a8b, (q15_t)0x2fd0, (q15_t)0x6a94, (q15_t)0x2fc8, (q15_t)0x6a9d, (q15_t)0x2fc0, (q15_t)0x6aa7, (q15_t)0x2fb7, + (q15_t)0x6ab0, (q15_t)0x2faf, (q15_t)0x6ab9, (q15_t)0x2fa7, (q15_t)0x6ac3, (q15_t)0x2f9e, (q15_t)0x6acc, (q15_t)0x2f96, + (q15_t)0x6ad6, (q15_t)0x2f8d, (q15_t)0x6adf, (q15_t)0x2f85, (q15_t)0x6ae8, (q15_t)0x2f7d, (q15_t)0x6af2, (q15_t)0x2f74, + (q15_t)0x6afb, (q15_t)0x2f6c, (q15_t)0x6b04, (q15_t)0x2f63, (q15_t)0x6b0d, (q15_t)0x2f5b, (q15_t)0x6b17, (q15_t)0x2f52, + (q15_t)0x6b20, (q15_t)0x2f4a, (q15_t)0x6b29, (q15_t)0x2f41, (q15_t)0x6b33, (q15_t)0x2f39, (q15_t)0x6b3c, (q15_t)0x2f30, + (q15_t)0x6b45, (q15_t)0x2f28, (q15_t)0x6b4e, (q15_t)0x2f20, (q15_t)0x6b58, (q15_t)0x2f17, (q15_t)0x6b61, (q15_t)0x2f0e, + (q15_t)0x6b6a, (q15_t)0x2f06, (q15_t)0x6b73, (q15_t)0x2efd, (q15_t)0x6b7d, (q15_t)0x2ef5, (q15_t)0x6b86, (q15_t)0x2eec, + (q15_t)0x6b8f, (q15_t)0x2ee4, (q15_t)0x6b98, (q15_t)0x2edb, (q15_t)0x6ba1, (q15_t)0x2ed3, (q15_t)0x6bab, (q15_t)0x2eca, + (q15_t)0x6bb4, (q15_t)0x2ec2, (q15_t)0x6bbd, (q15_t)0x2eb9, (q15_t)0x6bc6, (q15_t)0x2eb0, (q15_t)0x6bcf, (q15_t)0x2ea8, + (q15_t)0x6bd8, (q15_t)0x2e9f, (q15_t)0x6be2, (q15_t)0x2e97, (q15_t)0x6beb, (q15_t)0x2e8e, (q15_t)0x6bf4, (q15_t)0x2e85, + (q15_t)0x6bfd, (q15_t)0x2e7d, (q15_t)0x6c06, (q15_t)0x2e74, (q15_t)0x6c0f, (q15_t)0x2e6b, (q15_t)0x6c18, (q15_t)0x2e63, + (q15_t)0x6c21, (q15_t)0x2e5a, (q15_t)0x6c2b, (q15_t)0x2e51, (q15_t)0x6c34, (q15_t)0x2e49, (q15_t)0x6c3d, (q15_t)0x2e40, + (q15_t)0x6c46, (q15_t)0x2e37, (q15_t)0x6c4f, (q15_t)0x2e2f, (q15_t)0x6c58, (q15_t)0x2e26, (q15_t)0x6c61, (q15_t)0x2e1d, + (q15_t)0x6c6a, (q15_t)0x2e15, (q15_t)0x6c73, (q15_t)0x2e0c, (q15_t)0x6c7c, (q15_t)0x2e03, (q15_t)0x6c85, (q15_t)0x2dfa, + (q15_t)0x6c8e, (q15_t)0x2df2, (q15_t)0x6c97, (q15_t)0x2de9, (q15_t)0x6ca0, (q15_t)0x2de0, (q15_t)0x6ca9, (q15_t)0x2dd7, + (q15_t)0x6cb2, (q15_t)0x2dcf, (q15_t)0x6cbb, (q15_t)0x2dc6, (q15_t)0x6cc4, (q15_t)0x2dbd, (q15_t)0x6ccd, (q15_t)0x2db4, + (q15_t)0x6cd6, (q15_t)0x2dab, (q15_t)0x6cdf, (q15_t)0x2da3, (q15_t)0x6ce8, (q15_t)0x2d9a, (q15_t)0x6cf1, (q15_t)0x2d91, + (q15_t)0x6cfa, (q15_t)0x2d88, (q15_t)0x6d03, (q15_t)0x2d7f, (q15_t)0x6d0c, (q15_t)0x2d76, (q15_t)0x6d15, (q15_t)0x2d6e, + (q15_t)0x6d1e, (q15_t)0x2d65, (q15_t)0x6d27, (q15_t)0x2d5c, (q15_t)0x6d2f, (q15_t)0x2d53, (q15_t)0x6d38, (q15_t)0x2d4a, + (q15_t)0x6d41, (q15_t)0x2d41, (q15_t)0x6d4a, (q15_t)0x2d38, (q15_t)0x6d53, (q15_t)0x2d2f, (q15_t)0x6d5c, (q15_t)0x2d27, + (q15_t)0x6d65, (q15_t)0x2d1e, (q15_t)0x6d6e, (q15_t)0x2d15, (q15_t)0x6d76, (q15_t)0x2d0c, (q15_t)0x6d7f, (q15_t)0x2d03, + (q15_t)0x6d88, (q15_t)0x2cfa, (q15_t)0x6d91, (q15_t)0x2cf1, (q15_t)0x6d9a, (q15_t)0x2ce8, (q15_t)0x6da3, (q15_t)0x2cdf, + (q15_t)0x6dab, (q15_t)0x2cd6, (q15_t)0x6db4, (q15_t)0x2ccd, (q15_t)0x6dbd, (q15_t)0x2cc4, (q15_t)0x6dc6, (q15_t)0x2cbb, + (q15_t)0x6dcf, (q15_t)0x2cb2, (q15_t)0x6dd7, (q15_t)0x2ca9, (q15_t)0x6de0, (q15_t)0x2ca0, (q15_t)0x6de9, (q15_t)0x2c97, + (q15_t)0x6df2, (q15_t)0x2c8e, (q15_t)0x6dfa, (q15_t)0x2c85, (q15_t)0x6e03, (q15_t)0x2c7c, (q15_t)0x6e0c, (q15_t)0x2c73, + (q15_t)0x6e15, (q15_t)0x2c6a, (q15_t)0x6e1d, (q15_t)0x2c61, (q15_t)0x6e26, (q15_t)0x2c58, (q15_t)0x6e2f, (q15_t)0x2c4f, + (q15_t)0x6e37, (q15_t)0x2c46, (q15_t)0x6e40, (q15_t)0x2c3d, (q15_t)0x6e49, (q15_t)0x2c34, (q15_t)0x6e51, (q15_t)0x2c2b, + (q15_t)0x6e5a, (q15_t)0x2c21, (q15_t)0x6e63, (q15_t)0x2c18, (q15_t)0x6e6b, (q15_t)0x2c0f, (q15_t)0x6e74, (q15_t)0x2c06, + (q15_t)0x6e7d, (q15_t)0x2bfd, (q15_t)0x6e85, (q15_t)0x2bf4, (q15_t)0x6e8e, (q15_t)0x2beb, (q15_t)0x6e97, (q15_t)0x2be2, + (q15_t)0x6e9f, (q15_t)0x2bd8, (q15_t)0x6ea8, (q15_t)0x2bcf, (q15_t)0x6eb0, (q15_t)0x2bc6, (q15_t)0x6eb9, (q15_t)0x2bbd, + (q15_t)0x6ec2, (q15_t)0x2bb4, (q15_t)0x6eca, (q15_t)0x2bab, (q15_t)0x6ed3, (q15_t)0x2ba1, (q15_t)0x6edb, (q15_t)0x2b98, + (q15_t)0x6ee4, (q15_t)0x2b8f, (q15_t)0x6eec, (q15_t)0x2b86, (q15_t)0x6ef5, (q15_t)0x2b7d, (q15_t)0x6efd, (q15_t)0x2b73, + (q15_t)0x6f06, (q15_t)0x2b6a, (q15_t)0x6f0e, (q15_t)0x2b61, (q15_t)0x6f17, (q15_t)0x2b58, (q15_t)0x6f20, (q15_t)0x2b4e, + (q15_t)0x6f28, (q15_t)0x2b45, (q15_t)0x6f30, (q15_t)0x2b3c, (q15_t)0x6f39, (q15_t)0x2b33, (q15_t)0x6f41, (q15_t)0x2b29, + (q15_t)0x6f4a, (q15_t)0x2b20, (q15_t)0x6f52, (q15_t)0x2b17, (q15_t)0x6f5b, (q15_t)0x2b0d, (q15_t)0x6f63, (q15_t)0x2b04, + (q15_t)0x6f6c, (q15_t)0x2afb, (q15_t)0x6f74, (q15_t)0x2af2, (q15_t)0x6f7d, (q15_t)0x2ae8, (q15_t)0x6f85, (q15_t)0x2adf, + (q15_t)0x6f8d, (q15_t)0x2ad6, (q15_t)0x6f96, (q15_t)0x2acc, (q15_t)0x6f9e, (q15_t)0x2ac3, (q15_t)0x6fa7, (q15_t)0x2ab9, + (q15_t)0x6faf, (q15_t)0x2ab0, (q15_t)0x6fb7, (q15_t)0x2aa7, (q15_t)0x6fc0, (q15_t)0x2a9d, (q15_t)0x6fc8, (q15_t)0x2a94, + (q15_t)0x6fd0, (q15_t)0x2a8b, (q15_t)0x6fd9, (q15_t)0x2a81, (q15_t)0x6fe1, (q15_t)0x2a78, (q15_t)0x6fea, (q15_t)0x2a6e, + (q15_t)0x6ff2, (q15_t)0x2a65, (q15_t)0x6ffa, (q15_t)0x2a5c, (q15_t)0x7002, (q15_t)0x2a52, (q15_t)0x700b, (q15_t)0x2a49, + (q15_t)0x7013, (q15_t)0x2a3f, (q15_t)0x701b, (q15_t)0x2a36, (q15_t)0x7024, (q15_t)0x2a2c, (q15_t)0x702c, (q15_t)0x2a23, + (q15_t)0x7034, (q15_t)0x2a1a, (q15_t)0x703c, (q15_t)0x2a10, (q15_t)0x7045, (q15_t)0x2a07, (q15_t)0x704d, (q15_t)0x29fd, + (q15_t)0x7055, (q15_t)0x29f4, (q15_t)0x705d, (q15_t)0x29ea, (q15_t)0x7066, (q15_t)0x29e1, (q15_t)0x706e, (q15_t)0x29d7, + (q15_t)0x7076, (q15_t)0x29ce, (q15_t)0x707e, (q15_t)0x29c4, (q15_t)0x7087, (q15_t)0x29bb, (q15_t)0x708f, (q15_t)0x29b1, + (q15_t)0x7097, (q15_t)0x29a7, (q15_t)0x709f, (q15_t)0x299e, (q15_t)0x70a7, (q15_t)0x2994, (q15_t)0x70af, (q15_t)0x298b, + (q15_t)0x70b8, (q15_t)0x2981, (q15_t)0x70c0, (q15_t)0x2978, (q15_t)0x70c8, (q15_t)0x296e, (q15_t)0x70d0, (q15_t)0x2965, + (q15_t)0x70d8, (q15_t)0x295b, (q15_t)0x70e0, (q15_t)0x2951, (q15_t)0x70e8, (q15_t)0x2948, (q15_t)0x70f0, (q15_t)0x293e, + (q15_t)0x70f9, (q15_t)0x2935, (q15_t)0x7101, (q15_t)0x292b, (q15_t)0x7109, (q15_t)0x2921, (q15_t)0x7111, (q15_t)0x2918, + (q15_t)0x7119, (q15_t)0x290e, (q15_t)0x7121, (q15_t)0x2904, (q15_t)0x7129, (q15_t)0x28fb, (q15_t)0x7131, (q15_t)0x28f1, + (q15_t)0x7139, (q15_t)0x28e7, (q15_t)0x7141, (q15_t)0x28de, (q15_t)0x7149, (q15_t)0x28d4, (q15_t)0x7151, (q15_t)0x28ca, + (q15_t)0x7159, (q15_t)0x28c1, (q15_t)0x7161, (q15_t)0x28b7, (q15_t)0x7169, (q15_t)0x28ad, (q15_t)0x7171, (q15_t)0x28a4, + (q15_t)0x7179, (q15_t)0x289a, (q15_t)0x7181, (q15_t)0x2890, (q15_t)0x7189, (q15_t)0x2886, (q15_t)0x7191, (q15_t)0x287d, + (q15_t)0x7199, (q15_t)0x2873, (q15_t)0x71a1, (q15_t)0x2869, (q15_t)0x71a9, (q15_t)0x2860, (q15_t)0x71b1, (q15_t)0x2856, + (q15_t)0x71b9, (q15_t)0x284c, (q15_t)0x71c0, (q15_t)0x2842, (q15_t)0x71c8, (q15_t)0x2838, (q15_t)0x71d0, (q15_t)0x282f, + (q15_t)0x71d8, (q15_t)0x2825, (q15_t)0x71e0, (q15_t)0x281b, (q15_t)0x71e8, (q15_t)0x2811, (q15_t)0x71f0, (q15_t)0x2808, + (q15_t)0x71f8, (q15_t)0x27fe, (q15_t)0x71ff, (q15_t)0x27f4, (q15_t)0x7207, (q15_t)0x27ea, (q15_t)0x720f, (q15_t)0x27e0, + (q15_t)0x7217, (q15_t)0x27d6, (q15_t)0x721f, (q15_t)0x27cd, (q15_t)0x7227, (q15_t)0x27c3, (q15_t)0x722e, (q15_t)0x27b9, + (q15_t)0x7236, (q15_t)0x27af, (q15_t)0x723e, (q15_t)0x27a5, (q15_t)0x7246, (q15_t)0x279b, (q15_t)0x724e, (q15_t)0x2791, + (q15_t)0x7255, (q15_t)0x2788, (q15_t)0x725d, (q15_t)0x277e, (q15_t)0x7265, (q15_t)0x2774, (q15_t)0x726d, (q15_t)0x276a, + (q15_t)0x7274, (q15_t)0x2760, (q15_t)0x727c, (q15_t)0x2756, (q15_t)0x7284, (q15_t)0x274c, (q15_t)0x728b, (q15_t)0x2742, + (q15_t)0x7293, (q15_t)0x2738, (q15_t)0x729b, (q15_t)0x272e, (q15_t)0x72a3, (q15_t)0x2724, (q15_t)0x72aa, (q15_t)0x271a, + (q15_t)0x72b2, (q15_t)0x2711, (q15_t)0x72ba, (q15_t)0x2707, (q15_t)0x72c1, (q15_t)0x26fd, (q15_t)0x72c9, (q15_t)0x26f3, + (q15_t)0x72d0, (q15_t)0x26e9, (q15_t)0x72d8, (q15_t)0x26df, (q15_t)0x72e0, (q15_t)0x26d5, (q15_t)0x72e7, (q15_t)0x26cb, + (q15_t)0x72ef, (q15_t)0x26c1, (q15_t)0x72f7, (q15_t)0x26b7, (q15_t)0x72fe, (q15_t)0x26ad, (q15_t)0x7306, (q15_t)0x26a3, + (q15_t)0x730d, (q15_t)0x2699, (q15_t)0x7315, (q15_t)0x268f, (q15_t)0x731d, (q15_t)0x2685, (q15_t)0x7324, (q15_t)0x267b, + (q15_t)0x732c, (q15_t)0x2671, (q15_t)0x7333, (q15_t)0x2666, (q15_t)0x733b, (q15_t)0x265c, (q15_t)0x7342, (q15_t)0x2652, + (q15_t)0x734a, (q15_t)0x2648, (q15_t)0x7351, (q15_t)0x263e, (q15_t)0x7359, (q15_t)0x2634, (q15_t)0x7360, (q15_t)0x262a, + (q15_t)0x7368, (q15_t)0x2620, (q15_t)0x736f, (q15_t)0x2616, (q15_t)0x7377, (q15_t)0x260c, (q15_t)0x737e, (q15_t)0x2602, + (q15_t)0x7386, (q15_t)0x25f8, (q15_t)0x738d, (q15_t)0x25ed, (q15_t)0x7395, (q15_t)0x25e3, (q15_t)0x739c, (q15_t)0x25d9, + (q15_t)0x73a3, (q15_t)0x25cf, (q15_t)0x73ab, (q15_t)0x25c5, (q15_t)0x73b2, (q15_t)0x25bb, (q15_t)0x73ba, (q15_t)0x25b1, + (q15_t)0x73c1, (q15_t)0x25a6, (q15_t)0x73c8, (q15_t)0x259c, (q15_t)0x73d0, (q15_t)0x2592, (q15_t)0x73d7, (q15_t)0x2588, + (q15_t)0x73df, (q15_t)0x257e, (q15_t)0x73e6, (q15_t)0x2574, (q15_t)0x73ed, (q15_t)0x2569, (q15_t)0x73f5, (q15_t)0x255f, + (q15_t)0x73fc, (q15_t)0x2555, (q15_t)0x7403, (q15_t)0x254b, (q15_t)0x740b, (q15_t)0x2541, (q15_t)0x7412, (q15_t)0x2536, + (q15_t)0x7419, (q15_t)0x252c, (q15_t)0x7420, (q15_t)0x2522, (q15_t)0x7428, (q15_t)0x2518, (q15_t)0x742f, (q15_t)0x250d, + (q15_t)0x7436, (q15_t)0x2503, (q15_t)0x743e, (q15_t)0x24f9, (q15_t)0x7445, (q15_t)0x24ef, (q15_t)0x744c, (q15_t)0x24e4, + (q15_t)0x7453, (q15_t)0x24da, (q15_t)0x745b, (q15_t)0x24d0, (q15_t)0x7462, (q15_t)0x24c5, (q15_t)0x7469, (q15_t)0x24bb, + (q15_t)0x7470, (q15_t)0x24b1, (q15_t)0x7477, (q15_t)0x24a7, (q15_t)0x747f, (q15_t)0x249c, (q15_t)0x7486, (q15_t)0x2492, + (q15_t)0x748d, (q15_t)0x2488, (q15_t)0x7494, (q15_t)0x247d, (q15_t)0x749b, (q15_t)0x2473, (q15_t)0x74a2, (q15_t)0x2469, + (q15_t)0x74aa, (q15_t)0x245e, (q15_t)0x74b1, (q15_t)0x2454, (q15_t)0x74b8, (q15_t)0x244a, (q15_t)0x74bf, (q15_t)0x243f, + (q15_t)0x74c6, (q15_t)0x2435, (q15_t)0x74cd, (q15_t)0x242b, (q15_t)0x74d4, (q15_t)0x2420, (q15_t)0x74db, (q15_t)0x2416, + (q15_t)0x74e2, (q15_t)0x240b, (q15_t)0x74ea, (q15_t)0x2401, (q15_t)0x74f1, (q15_t)0x23f7, (q15_t)0x74f8, (q15_t)0x23ec, + (q15_t)0x74ff, (q15_t)0x23e2, (q15_t)0x7506, (q15_t)0x23d7, (q15_t)0x750d, (q15_t)0x23cd, (q15_t)0x7514, (q15_t)0x23c3, + (q15_t)0x751b, (q15_t)0x23b8, (q15_t)0x7522, (q15_t)0x23ae, (q15_t)0x7529, (q15_t)0x23a3, (q15_t)0x7530, (q15_t)0x2399, + (q15_t)0x7537, (q15_t)0x238e, (q15_t)0x753e, (q15_t)0x2384, (q15_t)0x7545, (q15_t)0x237a, (q15_t)0x754c, (q15_t)0x236f, + (q15_t)0x7553, (q15_t)0x2365, (q15_t)0x755a, (q15_t)0x235a, (q15_t)0x7561, (q15_t)0x2350, (q15_t)0x7567, (q15_t)0x2345, + (q15_t)0x756e, (q15_t)0x233b, (q15_t)0x7575, (q15_t)0x2330, (q15_t)0x757c, (q15_t)0x2326, (q15_t)0x7583, (q15_t)0x231b, + (q15_t)0x758a, (q15_t)0x2311, (q15_t)0x7591, (q15_t)0x2306, (q15_t)0x7598, (q15_t)0x22fc, (q15_t)0x759f, (q15_t)0x22f1, + (q15_t)0x75a5, (q15_t)0x22e7, (q15_t)0x75ac, (q15_t)0x22dc, (q15_t)0x75b3, (q15_t)0x22d2, (q15_t)0x75ba, (q15_t)0x22c7, + (q15_t)0x75c1, (q15_t)0x22bc, (q15_t)0x75c8, (q15_t)0x22b2, (q15_t)0x75ce, (q15_t)0x22a7, (q15_t)0x75d5, (q15_t)0x229d, + (q15_t)0x75dc, (q15_t)0x2292, (q15_t)0x75e3, (q15_t)0x2288, (q15_t)0x75ea, (q15_t)0x227d, (q15_t)0x75f0, (q15_t)0x2272, + (q15_t)0x75f7, (q15_t)0x2268, (q15_t)0x75fe, (q15_t)0x225d, (q15_t)0x7605, (q15_t)0x2253, (q15_t)0x760b, (q15_t)0x2248, + (q15_t)0x7612, (q15_t)0x223d, (q15_t)0x7619, (q15_t)0x2233, (q15_t)0x7620, (q15_t)0x2228, (q15_t)0x7626, (q15_t)0x221e, + (q15_t)0x762d, (q15_t)0x2213, (q15_t)0x7634, (q15_t)0x2208, (q15_t)0x763a, (q15_t)0x21fe, (q15_t)0x7641, (q15_t)0x21f3, + (q15_t)0x7648, (q15_t)0x21e8, (q15_t)0x764e, (q15_t)0x21de, (q15_t)0x7655, (q15_t)0x21d3, (q15_t)0x765c, (q15_t)0x21c8, + (q15_t)0x7662, (q15_t)0x21be, (q15_t)0x7669, (q15_t)0x21b3, (q15_t)0x766f, (q15_t)0x21a8, (q15_t)0x7676, (q15_t)0x219e, + (q15_t)0x767d, (q15_t)0x2193, (q15_t)0x7683, (q15_t)0x2188, (q15_t)0x768a, (q15_t)0x217d, (q15_t)0x7690, (q15_t)0x2173, + (q15_t)0x7697, (q15_t)0x2168, (q15_t)0x769d, (q15_t)0x215d, (q15_t)0x76a4, (q15_t)0x2153, (q15_t)0x76ab, (q15_t)0x2148, + (q15_t)0x76b1, (q15_t)0x213d, (q15_t)0x76b8, (q15_t)0x2132, (q15_t)0x76be, (q15_t)0x2128, (q15_t)0x76c5, (q15_t)0x211d, + (q15_t)0x76cb, (q15_t)0x2112, (q15_t)0x76d2, (q15_t)0x2107, (q15_t)0x76d8, (q15_t)0x20fd, (q15_t)0x76df, (q15_t)0x20f2, + (q15_t)0x76e5, (q15_t)0x20e7, (q15_t)0x76eb, (q15_t)0x20dc, (q15_t)0x76f2, (q15_t)0x20d1, (q15_t)0x76f8, (q15_t)0x20c7, + (q15_t)0x76ff, (q15_t)0x20bc, (q15_t)0x7705, (q15_t)0x20b1, (q15_t)0x770c, (q15_t)0x20a6, (q15_t)0x7712, (q15_t)0x209b, + (q15_t)0x7718, (q15_t)0x2091, (q15_t)0x771f, (q15_t)0x2086, (q15_t)0x7725, (q15_t)0x207b, (q15_t)0x772c, (q15_t)0x2070, + (q15_t)0x7732, (q15_t)0x2065, (q15_t)0x7738, (q15_t)0x205b, (q15_t)0x773f, (q15_t)0x2050, (q15_t)0x7745, (q15_t)0x2045, + (q15_t)0x774b, (q15_t)0x203a, (q15_t)0x7752, (q15_t)0x202f, (q15_t)0x7758, (q15_t)0x2024, (q15_t)0x775e, (q15_t)0x2019, + (q15_t)0x7765, (q15_t)0x200f, (q15_t)0x776b, (q15_t)0x2004, (q15_t)0x7771, (q15_t)0x1ff9, (q15_t)0x7777, (q15_t)0x1fee, + (q15_t)0x777e, (q15_t)0x1fe3, (q15_t)0x7784, (q15_t)0x1fd8, (q15_t)0x778a, (q15_t)0x1fcd, (q15_t)0x7790, (q15_t)0x1fc2, + (q15_t)0x7797, (q15_t)0x1fb7, (q15_t)0x779d, (q15_t)0x1fac, (q15_t)0x77a3, (q15_t)0x1fa2, (q15_t)0x77a9, (q15_t)0x1f97, + (q15_t)0x77b0, (q15_t)0x1f8c, (q15_t)0x77b6, (q15_t)0x1f81, (q15_t)0x77bc, (q15_t)0x1f76, (q15_t)0x77c2, (q15_t)0x1f6b, + (q15_t)0x77c8, (q15_t)0x1f60, (q15_t)0x77ce, (q15_t)0x1f55, (q15_t)0x77d5, (q15_t)0x1f4a, (q15_t)0x77db, (q15_t)0x1f3f, + (q15_t)0x77e1, (q15_t)0x1f34, (q15_t)0x77e7, (q15_t)0x1f29, (q15_t)0x77ed, (q15_t)0x1f1e, (q15_t)0x77f3, (q15_t)0x1f13, + (q15_t)0x77f9, (q15_t)0x1f08, (q15_t)0x77ff, (q15_t)0x1efd, (q15_t)0x7805, (q15_t)0x1ef2, (q15_t)0x780b, (q15_t)0x1ee7, + (q15_t)0x7812, (q15_t)0x1edc, (q15_t)0x7818, (q15_t)0x1ed1, (q15_t)0x781e, (q15_t)0x1ec6, (q15_t)0x7824, (q15_t)0x1ebb, + (q15_t)0x782a, (q15_t)0x1eb0, (q15_t)0x7830, (q15_t)0x1ea5, (q15_t)0x7836, (q15_t)0x1e9a, (q15_t)0x783c, (q15_t)0x1e8f, + (q15_t)0x7842, (q15_t)0x1e84, (q15_t)0x7848, (q15_t)0x1e79, (q15_t)0x784e, (q15_t)0x1e6e, (q15_t)0x7854, (q15_t)0x1e63, + (q15_t)0x785a, (q15_t)0x1e58, (q15_t)0x7860, (q15_t)0x1e4d, (q15_t)0x7866, (q15_t)0x1e42, (q15_t)0x786b, (q15_t)0x1e36, + (q15_t)0x7871, (q15_t)0x1e2b, (q15_t)0x7877, (q15_t)0x1e20, (q15_t)0x787d, (q15_t)0x1e15, (q15_t)0x7883, (q15_t)0x1e0a, + (q15_t)0x7889, (q15_t)0x1dff, (q15_t)0x788f, (q15_t)0x1df4, (q15_t)0x7895, (q15_t)0x1de9, (q15_t)0x789b, (q15_t)0x1dde, + (q15_t)0x78a1, (q15_t)0x1dd3, (q15_t)0x78a6, (q15_t)0x1dc7, (q15_t)0x78ac, (q15_t)0x1dbc, (q15_t)0x78b2, (q15_t)0x1db1, + (q15_t)0x78b8, (q15_t)0x1da6, (q15_t)0x78be, (q15_t)0x1d9b, (q15_t)0x78c3, (q15_t)0x1d90, (q15_t)0x78c9, (q15_t)0x1d85, + (q15_t)0x78cf, (q15_t)0x1d79, (q15_t)0x78d5, (q15_t)0x1d6e, (q15_t)0x78db, (q15_t)0x1d63, (q15_t)0x78e0, (q15_t)0x1d58, + (q15_t)0x78e6, (q15_t)0x1d4d, (q15_t)0x78ec, (q15_t)0x1d42, (q15_t)0x78f2, (q15_t)0x1d36, (q15_t)0x78f7, (q15_t)0x1d2b, + (q15_t)0x78fd, (q15_t)0x1d20, (q15_t)0x7903, (q15_t)0x1d15, (q15_t)0x7909, (q15_t)0x1d0a, (q15_t)0x790e, (q15_t)0x1cff, + (q15_t)0x7914, (q15_t)0x1cf3, (q15_t)0x791a, (q15_t)0x1ce8, (q15_t)0x791f, (q15_t)0x1cdd, (q15_t)0x7925, (q15_t)0x1cd2, + (q15_t)0x792b, (q15_t)0x1cc6, (q15_t)0x7930, (q15_t)0x1cbb, (q15_t)0x7936, (q15_t)0x1cb0, (q15_t)0x793b, (q15_t)0x1ca5, + (q15_t)0x7941, (q15_t)0x1c99, (q15_t)0x7947, (q15_t)0x1c8e, (q15_t)0x794c, (q15_t)0x1c83, (q15_t)0x7952, (q15_t)0x1c78, + (q15_t)0x7958, (q15_t)0x1c6c, (q15_t)0x795d, (q15_t)0x1c61, (q15_t)0x7963, (q15_t)0x1c56, (q15_t)0x7968, (q15_t)0x1c4b, + (q15_t)0x796e, (q15_t)0x1c3f, (q15_t)0x7973, (q15_t)0x1c34, (q15_t)0x7979, (q15_t)0x1c29, (q15_t)0x797e, (q15_t)0x1c1e, + (q15_t)0x7984, (q15_t)0x1c12, (q15_t)0x7989, (q15_t)0x1c07, (q15_t)0x798f, (q15_t)0x1bfc, (q15_t)0x7994, (q15_t)0x1bf0, + (q15_t)0x799a, (q15_t)0x1be5, (q15_t)0x799f, (q15_t)0x1bda, (q15_t)0x79a5, (q15_t)0x1bce, (q15_t)0x79aa, (q15_t)0x1bc3, + (q15_t)0x79b0, (q15_t)0x1bb8, (q15_t)0x79b5, (q15_t)0x1bac, (q15_t)0x79bb, (q15_t)0x1ba1, (q15_t)0x79c0, (q15_t)0x1b96, + (q15_t)0x79c5, (q15_t)0x1b8a, (q15_t)0x79cb, (q15_t)0x1b7f, (q15_t)0x79d0, (q15_t)0x1b74, (q15_t)0x79d6, (q15_t)0x1b68, + (q15_t)0x79db, (q15_t)0x1b5d, (q15_t)0x79e0, (q15_t)0x1b52, (q15_t)0x79e6, (q15_t)0x1b46, (q15_t)0x79eb, (q15_t)0x1b3b, + (q15_t)0x79f0, (q15_t)0x1b30, (q15_t)0x79f6, (q15_t)0x1b24, (q15_t)0x79fb, (q15_t)0x1b19, (q15_t)0x7a00, (q15_t)0x1b0d, + (q15_t)0x7a06, (q15_t)0x1b02, (q15_t)0x7a0b, (q15_t)0x1af7, (q15_t)0x7a10, (q15_t)0x1aeb, (q15_t)0x7a16, (q15_t)0x1ae0, + (q15_t)0x7a1b, (q15_t)0x1ad4, (q15_t)0x7a20, (q15_t)0x1ac9, (q15_t)0x7a25, (q15_t)0x1abe, (q15_t)0x7a2b, (q15_t)0x1ab2, + (q15_t)0x7a30, (q15_t)0x1aa7, (q15_t)0x7a35, (q15_t)0x1a9b, (q15_t)0x7a3a, (q15_t)0x1a90, (q15_t)0x7a3f, (q15_t)0x1a84, + (q15_t)0x7a45, (q15_t)0x1a79, (q15_t)0x7a4a, (q15_t)0x1a6e, (q15_t)0x7a4f, (q15_t)0x1a62, (q15_t)0x7a54, (q15_t)0x1a57, + (q15_t)0x7a59, (q15_t)0x1a4b, (q15_t)0x7a5f, (q15_t)0x1a40, (q15_t)0x7a64, (q15_t)0x1a34, (q15_t)0x7a69, (q15_t)0x1a29, + (q15_t)0x7a6e, (q15_t)0x1a1d, (q15_t)0x7a73, (q15_t)0x1a12, (q15_t)0x7a78, (q15_t)0x1a06, (q15_t)0x7a7d, (q15_t)0x19fb, + (q15_t)0x7a82, (q15_t)0x19ef, (q15_t)0x7a88, (q15_t)0x19e4, (q15_t)0x7a8d, (q15_t)0x19d8, (q15_t)0x7a92, (q15_t)0x19cd, + (q15_t)0x7a97, (q15_t)0x19c1, (q15_t)0x7a9c, (q15_t)0x19b6, (q15_t)0x7aa1, (q15_t)0x19aa, (q15_t)0x7aa6, (q15_t)0x199f, + (q15_t)0x7aab, (q15_t)0x1993, (q15_t)0x7ab0, (q15_t)0x1988, (q15_t)0x7ab5, (q15_t)0x197c, (q15_t)0x7aba, (q15_t)0x1971, + (q15_t)0x7abf, (q15_t)0x1965, (q15_t)0x7ac4, (q15_t)0x195a, (q15_t)0x7ac9, (q15_t)0x194e, (q15_t)0x7ace, (q15_t)0x1943, + (q15_t)0x7ad3, (q15_t)0x1937, (q15_t)0x7ad8, (q15_t)0x192c, (q15_t)0x7add, (q15_t)0x1920, (q15_t)0x7ae2, (q15_t)0x1914, + (q15_t)0x7ae6, (q15_t)0x1909, (q15_t)0x7aeb, (q15_t)0x18fd, (q15_t)0x7af0, (q15_t)0x18f2, (q15_t)0x7af5, (q15_t)0x18e6, + (q15_t)0x7afa, (q15_t)0x18db, (q15_t)0x7aff, (q15_t)0x18cf, (q15_t)0x7b04, (q15_t)0x18c3, (q15_t)0x7b09, (q15_t)0x18b8, + (q15_t)0x7b0e, (q15_t)0x18ac, (q15_t)0x7b12, (q15_t)0x18a1, (q15_t)0x7b17, (q15_t)0x1895, (q15_t)0x7b1c, (q15_t)0x1889, + (q15_t)0x7b21, (q15_t)0x187e, (q15_t)0x7b26, (q15_t)0x1872, (q15_t)0x7b2a, (q15_t)0x1867, (q15_t)0x7b2f, (q15_t)0x185b, + (q15_t)0x7b34, (q15_t)0x184f, (q15_t)0x7b39, (q15_t)0x1844, (q15_t)0x7b3e, (q15_t)0x1838, (q15_t)0x7b42, (q15_t)0x182d, + (q15_t)0x7b47, (q15_t)0x1821, (q15_t)0x7b4c, (q15_t)0x1815, (q15_t)0x7b50, (q15_t)0x180a, (q15_t)0x7b55, (q15_t)0x17fe, + (q15_t)0x7b5a, (q15_t)0x17f2, (q15_t)0x7b5f, (q15_t)0x17e7, (q15_t)0x7b63, (q15_t)0x17db, (q15_t)0x7b68, (q15_t)0x17cf, + (q15_t)0x7b6d, (q15_t)0x17c4, (q15_t)0x7b71, (q15_t)0x17b8, (q15_t)0x7b76, (q15_t)0x17ac, (q15_t)0x7b7b, (q15_t)0x17a1, + (q15_t)0x7b7f, (q15_t)0x1795, (q15_t)0x7b84, (q15_t)0x1789, (q15_t)0x7b88, (q15_t)0x177e, (q15_t)0x7b8d, (q15_t)0x1772, + (q15_t)0x7b92, (q15_t)0x1766, (q15_t)0x7b96, (q15_t)0x175b, (q15_t)0x7b9b, (q15_t)0x174f, (q15_t)0x7b9f, (q15_t)0x1743, + (q15_t)0x7ba4, (q15_t)0x1737, (q15_t)0x7ba9, (q15_t)0x172c, (q15_t)0x7bad, (q15_t)0x1720, (q15_t)0x7bb2, (q15_t)0x1714, + (q15_t)0x7bb6, (q15_t)0x1709, (q15_t)0x7bbb, (q15_t)0x16fd, (q15_t)0x7bbf, (q15_t)0x16f1, (q15_t)0x7bc4, (q15_t)0x16e5, + (q15_t)0x7bc8, (q15_t)0x16da, (q15_t)0x7bcd, (q15_t)0x16ce, (q15_t)0x7bd1, (q15_t)0x16c2, (q15_t)0x7bd6, (q15_t)0x16b6, + (q15_t)0x7bda, (q15_t)0x16ab, (q15_t)0x7bde, (q15_t)0x169f, (q15_t)0x7be3, (q15_t)0x1693, (q15_t)0x7be7, (q15_t)0x1687, + (q15_t)0x7bec, (q15_t)0x167c, (q15_t)0x7bf0, (q15_t)0x1670, (q15_t)0x7bf5, (q15_t)0x1664, (q15_t)0x7bf9, (q15_t)0x1658, + (q15_t)0x7bfd, (q15_t)0x164c, (q15_t)0x7c02, (q15_t)0x1641, (q15_t)0x7c06, (q15_t)0x1635, (q15_t)0x7c0a, (q15_t)0x1629, + (q15_t)0x7c0f, (q15_t)0x161d, (q15_t)0x7c13, (q15_t)0x1612, (q15_t)0x7c17, (q15_t)0x1606, (q15_t)0x7c1c, (q15_t)0x15fa, + (q15_t)0x7c20, (q15_t)0x15ee, (q15_t)0x7c24, (q15_t)0x15e2, (q15_t)0x7c29, (q15_t)0x15d7, (q15_t)0x7c2d, (q15_t)0x15cb, + (q15_t)0x7c31, (q15_t)0x15bf, (q15_t)0x7c36, (q15_t)0x15b3, (q15_t)0x7c3a, (q15_t)0x15a7, (q15_t)0x7c3e, (q15_t)0x159b, + (q15_t)0x7c42, (q15_t)0x1590, (q15_t)0x7c46, (q15_t)0x1584, (q15_t)0x7c4b, (q15_t)0x1578, (q15_t)0x7c4f, (q15_t)0x156c, + (q15_t)0x7c53, (q15_t)0x1560, (q15_t)0x7c57, (q15_t)0x1554, (q15_t)0x7c5b, (q15_t)0x1549, (q15_t)0x7c60, (q15_t)0x153d, + (q15_t)0x7c64, (q15_t)0x1531, (q15_t)0x7c68, (q15_t)0x1525, (q15_t)0x7c6c, (q15_t)0x1519, (q15_t)0x7c70, (q15_t)0x150d, + (q15_t)0x7c74, (q15_t)0x1501, (q15_t)0x7c79, (q15_t)0x14f6, (q15_t)0x7c7d, (q15_t)0x14ea, (q15_t)0x7c81, (q15_t)0x14de, + (q15_t)0x7c85, (q15_t)0x14d2, (q15_t)0x7c89, (q15_t)0x14c6, (q15_t)0x7c8d, (q15_t)0x14ba, (q15_t)0x7c91, (q15_t)0x14ae, + (q15_t)0x7c95, (q15_t)0x14a2, (q15_t)0x7c99, (q15_t)0x1496, (q15_t)0x7c9d, (q15_t)0x148b, (q15_t)0x7ca1, (q15_t)0x147f, + (q15_t)0x7ca5, (q15_t)0x1473, (q15_t)0x7ca9, (q15_t)0x1467, (q15_t)0x7cad, (q15_t)0x145b, (q15_t)0x7cb1, (q15_t)0x144f, + (q15_t)0x7cb5, (q15_t)0x1443, (q15_t)0x7cb9, (q15_t)0x1437, (q15_t)0x7cbd, (q15_t)0x142b, (q15_t)0x7cc1, (q15_t)0x141f, + (q15_t)0x7cc5, (q15_t)0x1413, (q15_t)0x7cc9, (q15_t)0x1407, (q15_t)0x7ccd, (q15_t)0x13fb, (q15_t)0x7cd1, (q15_t)0x13f0, + (q15_t)0x7cd5, (q15_t)0x13e4, (q15_t)0x7cd9, (q15_t)0x13d8, (q15_t)0x7cdd, (q15_t)0x13cc, (q15_t)0x7ce0, (q15_t)0x13c0, + (q15_t)0x7ce4, (q15_t)0x13b4, (q15_t)0x7ce8, (q15_t)0x13a8, (q15_t)0x7cec, (q15_t)0x139c, (q15_t)0x7cf0, (q15_t)0x1390, + (q15_t)0x7cf4, (q15_t)0x1384, (q15_t)0x7cf8, (q15_t)0x1378, (q15_t)0x7cfb, (q15_t)0x136c, (q15_t)0x7cff, (q15_t)0x1360, + (q15_t)0x7d03, (q15_t)0x1354, (q15_t)0x7d07, (q15_t)0x1348, (q15_t)0x7d0b, (q15_t)0x133c, (q15_t)0x7d0e, (q15_t)0x1330, + (q15_t)0x7d12, (q15_t)0x1324, (q15_t)0x7d16, (q15_t)0x1318, (q15_t)0x7d1a, (q15_t)0x130c, (q15_t)0x7d1d, (q15_t)0x1300, + (q15_t)0x7d21, (q15_t)0x12f4, (q15_t)0x7d25, (q15_t)0x12e8, (q15_t)0x7d28, (q15_t)0x12dc, (q15_t)0x7d2c, (q15_t)0x12d0, + (q15_t)0x7d30, (q15_t)0x12c4, (q15_t)0x7d34, (q15_t)0x12b8, (q15_t)0x7d37, (q15_t)0x12ac, (q15_t)0x7d3b, (q15_t)0x12a0, + (q15_t)0x7d3f, (q15_t)0x1294, (q15_t)0x7d42, (q15_t)0x1288, (q15_t)0x7d46, (q15_t)0x127c, (q15_t)0x7d49, (q15_t)0x1270, + (q15_t)0x7d4d, (q15_t)0x1264, (q15_t)0x7d51, (q15_t)0x1258, (q15_t)0x7d54, (q15_t)0x124c, (q15_t)0x7d58, (q15_t)0x1240, + (q15_t)0x7d5b, (q15_t)0x1234, (q15_t)0x7d5f, (q15_t)0x1228, (q15_t)0x7d63, (q15_t)0x121c, (q15_t)0x7d66, (q15_t)0x1210, + (q15_t)0x7d6a, (q15_t)0x1204, (q15_t)0x7d6d, (q15_t)0x11f7, (q15_t)0x7d71, (q15_t)0x11eb, (q15_t)0x7d74, (q15_t)0x11df, + (q15_t)0x7d78, (q15_t)0x11d3, (q15_t)0x7d7b, (q15_t)0x11c7, (q15_t)0x7d7f, (q15_t)0x11bb, (q15_t)0x7d82, (q15_t)0x11af, + (q15_t)0x7d86, (q15_t)0x11a3, (q15_t)0x7d89, (q15_t)0x1197, (q15_t)0x7d8d, (q15_t)0x118b, (q15_t)0x7d90, (q15_t)0x117f, + (q15_t)0x7d93, (q15_t)0x1173, (q15_t)0x7d97, (q15_t)0x1167, (q15_t)0x7d9a, (q15_t)0x115a, (q15_t)0x7d9e, (q15_t)0x114e, + (q15_t)0x7da1, (q15_t)0x1142, (q15_t)0x7da4, (q15_t)0x1136, (q15_t)0x7da8, (q15_t)0x112a, (q15_t)0x7dab, (q15_t)0x111e, + (q15_t)0x7daf, (q15_t)0x1112, (q15_t)0x7db2, (q15_t)0x1106, (q15_t)0x7db5, (q15_t)0x10fa, (q15_t)0x7db9, (q15_t)0x10ed, + (q15_t)0x7dbc, (q15_t)0x10e1, (q15_t)0x7dbf, (q15_t)0x10d5, (q15_t)0x7dc2, (q15_t)0x10c9, (q15_t)0x7dc6, (q15_t)0x10bd, + (q15_t)0x7dc9, (q15_t)0x10b1, (q15_t)0x7dcc, (q15_t)0x10a5, (q15_t)0x7dd0, (q15_t)0x1099, (q15_t)0x7dd3, (q15_t)0x108c, + (q15_t)0x7dd6, (q15_t)0x1080, (q15_t)0x7dd9, (q15_t)0x1074, (q15_t)0x7ddd, (q15_t)0x1068, (q15_t)0x7de0, (q15_t)0x105c, + (q15_t)0x7de3, (q15_t)0x1050, (q15_t)0x7de6, (q15_t)0x1044, (q15_t)0x7de9, (q15_t)0x1037, (q15_t)0x7ded, (q15_t)0x102b, + (q15_t)0x7df0, (q15_t)0x101f, (q15_t)0x7df3, (q15_t)0x1013, (q15_t)0x7df6, (q15_t)0x1007, (q15_t)0x7df9, (q15_t)0xffb, + (q15_t)0x7dfc, (q15_t)0xfee, (q15_t)0x7dff, (q15_t)0xfe2, (q15_t)0x7e03, (q15_t)0xfd6, (q15_t)0x7e06, (q15_t)0xfca, + (q15_t)0x7e09, (q15_t)0xfbe, (q15_t)0x7e0c, (q15_t)0xfb2, (q15_t)0x7e0f, (q15_t)0xfa5, (q15_t)0x7e12, (q15_t)0xf99, + (q15_t)0x7e15, (q15_t)0xf8d, (q15_t)0x7e18, (q15_t)0xf81, (q15_t)0x7e1b, (q15_t)0xf75, (q15_t)0x7e1e, (q15_t)0xf68, + (q15_t)0x7e21, (q15_t)0xf5c, (q15_t)0x7e24, (q15_t)0xf50, (q15_t)0x7e27, (q15_t)0xf44, (q15_t)0x7e2a, (q15_t)0xf38, + (q15_t)0x7e2d, (q15_t)0xf2b, (q15_t)0x7e30, (q15_t)0xf1f, (q15_t)0x7e33, (q15_t)0xf13, (q15_t)0x7e36, (q15_t)0xf07, + (q15_t)0x7e39, (q15_t)0xefb, (q15_t)0x7e3c, (q15_t)0xeee, (q15_t)0x7e3f, (q15_t)0xee2, (q15_t)0x7e42, (q15_t)0xed6, + (q15_t)0x7e45, (q15_t)0xeca, (q15_t)0x7e48, (q15_t)0xebd, (q15_t)0x7e4a, (q15_t)0xeb1, (q15_t)0x7e4d, (q15_t)0xea5, + (q15_t)0x7e50, (q15_t)0xe99, (q15_t)0x7e53, (q15_t)0xe8c, (q15_t)0x7e56, (q15_t)0xe80, (q15_t)0x7e59, (q15_t)0xe74, + (q15_t)0x7e5c, (q15_t)0xe68, (q15_t)0x7e5e, (q15_t)0xe5c, (q15_t)0x7e61, (q15_t)0xe4f, (q15_t)0x7e64, (q15_t)0xe43, + (q15_t)0x7e67, (q15_t)0xe37, (q15_t)0x7e6a, (q15_t)0xe2b, (q15_t)0x7e6c, (q15_t)0xe1e, (q15_t)0x7e6f, (q15_t)0xe12, + (q15_t)0x7e72, (q15_t)0xe06, (q15_t)0x7e75, (q15_t)0xdf9, (q15_t)0x7e77, (q15_t)0xded, (q15_t)0x7e7a, (q15_t)0xde1, + (q15_t)0x7e7d, (q15_t)0xdd5, (q15_t)0x7e80, (q15_t)0xdc8, (q15_t)0x7e82, (q15_t)0xdbc, (q15_t)0x7e85, (q15_t)0xdb0, + (q15_t)0x7e88, (q15_t)0xda4, (q15_t)0x7e8a, (q15_t)0xd97, (q15_t)0x7e8d, (q15_t)0xd8b, (q15_t)0x7e90, (q15_t)0xd7f, + (q15_t)0x7e92, (q15_t)0xd72, (q15_t)0x7e95, (q15_t)0xd66, (q15_t)0x7e98, (q15_t)0xd5a, (q15_t)0x7e9a, (q15_t)0xd4e, + (q15_t)0x7e9d, (q15_t)0xd41, (q15_t)0x7e9f, (q15_t)0xd35, (q15_t)0x7ea2, (q15_t)0xd29, (q15_t)0x7ea5, (q15_t)0xd1c, + (q15_t)0x7ea7, (q15_t)0xd10, (q15_t)0x7eaa, (q15_t)0xd04, (q15_t)0x7eac, (q15_t)0xcf8, (q15_t)0x7eaf, (q15_t)0xceb, + (q15_t)0x7eb1, (q15_t)0xcdf, (q15_t)0x7eb4, (q15_t)0xcd3, (q15_t)0x7eb6, (q15_t)0xcc6, (q15_t)0x7eb9, (q15_t)0xcba, + (q15_t)0x7ebb, (q15_t)0xcae, (q15_t)0x7ebe, (q15_t)0xca1, (q15_t)0x7ec0, (q15_t)0xc95, (q15_t)0x7ec3, (q15_t)0xc89, + (q15_t)0x7ec5, (q15_t)0xc7c, (q15_t)0x7ec8, (q15_t)0xc70, (q15_t)0x7eca, (q15_t)0xc64, (q15_t)0x7ecc, (q15_t)0xc57, + (q15_t)0x7ecf, (q15_t)0xc4b, (q15_t)0x7ed1, (q15_t)0xc3f, (q15_t)0x7ed4, (q15_t)0xc32, (q15_t)0x7ed6, (q15_t)0xc26, + (q15_t)0x7ed8, (q15_t)0xc1a, (q15_t)0x7edb, (q15_t)0xc0d, (q15_t)0x7edd, (q15_t)0xc01, (q15_t)0x7ee0, (q15_t)0xbf5, + (q15_t)0x7ee2, (q15_t)0xbe8, (q15_t)0x7ee4, (q15_t)0xbdc, (q15_t)0x7ee7, (q15_t)0xbd0, (q15_t)0x7ee9, (q15_t)0xbc3, + (q15_t)0x7eeb, (q15_t)0xbb7, (q15_t)0x7eed, (q15_t)0xbab, (q15_t)0x7ef0, (q15_t)0xb9e, (q15_t)0x7ef2, (q15_t)0xb92, + (q15_t)0x7ef4, (q15_t)0xb85, (q15_t)0x7ef7, (q15_t)0xb79, (q15_t)0x7ef9, (q15_t)0xb6d, (q15_t)0x7efb, (q15_t)0xb60, + (q15_t)0x7efd, (q15_t)0xb54, (q15_t)0x7f00, (q15_t)0xb48, (q15_t)0x7f02, (q15_t)0xb3b, (q15_t)0x7f04, (q15_t)0xb2f, + (q15_t)0x7f06, (q15_t)0xb23, (q15_t)0x7f08, (q15_t)0xb16, (q15_t)0x7f0a, (q15_t)0xb0a, (q15_t)0x7f0d, (q15_t)0xafd, + (q15_t)0x7f0f, (q15_t)0xaf1, (q15_t)0x7f11, (q15_t)0xae5, (q15_t)0x7f13, (q15_t)0xad8, (q15_t)0x7f15, (q15_t)0xacc, + (q15_t)0x7f17, (q15_t)0xac0, (q15_t)0x7f19, (q15_t)0xab3, (q15_t)0x7f1c, (q15_t)0xaa7, (q15_t)0x7f1e, (q15_t)0xa9a, + (q15_t)0x7f20, (q15_t)0xa8e, (q15_t)0x7f22, (q15_t)0xa82, (q15_t)0x7f24, (q15_t)0xa75, (q15_t)0x7f26, (q15_t)0xa69, + (q15_t)0x7f28, (q15_t)0xa5c, (q15_t)0x7f2a, (q15_t)0xa50, (q15_t)0x7f2c, (q15_t)0xa44, (q15_t)0x7f2e, (q15_t)0xa37, + (q15_t)0x7f30, (q15_t)0xa2b, (q15_t)0x7f32, (q15_t)0xa1e, (q15_t)0x7f34, (q15_t)0xa12, (q15_t)0x7f36, (q15_t)0xa06, + (q15_t)0x7f38, (q15_t)0x9f9, (q15_t)0x7f3a, (q15_t)0x9ed, (q15_t)0x7f3c, (q15_t)0x9e0, (q15_t)0x7f3e, (q15_t)0x9d4, + (q15_t)0x7f40, (q15_t)0x9c7, (q15_t)0x7f42, (q15_t)0x9bb, (q15_t)0x7f43, (q15_t)0x9af, (q15_t)0x7f45, (q15_t)0x9a2, + (q15_t)0x7f47, (q15_t)0x996, (q15_t)0x7f49, (q15_t)0x989, (q15_t)0x7f4b, (q15_t)0x97d, (q15_t)0x7f4d, (q15_t)0x970, + (q15_t)0x7f4f, (q15_t)0x964, (q15_t)0x7f51, (q15_t)0x958, (q15_t)0x7f52, (q15_t)0x94b, (q15_t)0x7f54, (q15_t)0x93f, + (q15_t)0x7f56, (q15_t)0x932, (q15_t)0x7f58, (q15_t)0x926, (q15_t)0x7f5a, (q15_t)0x919, (q15_t)0x7f5b, (q15_t)0x90d, + (q15_t)0x7f5d, (q15_t)0x901, (q15_t)0x7f5f, (q15_t)0x8f4, (q15_t)0x7f61, (q15_t)0x8e8, (q15_t)0x7f62, (q15_t)0x8db, + (q15_t)0x7f64, (q15_t)0x8cf, (q15_t)0x7f66, (q15_t)0x8c2, (q15_t)0x7f68, (q15_t)0x8b6, (q15_t)0x7f69, (q15_t)0x8a9, + (q15_t)0x7f6b, (q15_t)0x89d, (q15_t)0x7f6d, (q15_t)0x891, (q15_t)0x7f6e, (q15_t)0x884, (q15_t)0x7f70, (q15_t)0x878, + (q15_t)0x7f72, (q15_t)0x86b, (q15_t)0x7f73, (q15_t)0x85f, (q15_t)0x7f75, (q15_t)0x852, (q15_t)0x7f77, (q15_t)0x846, + (q15_t)0x7f78, (q15_t)0x839, (q15_t)0x7f7a, (q15_t)0x82d, (q15_t)0x7f7b, (q15_t)0x820, (q15_t)0x7f7d, (q15_t)0x814, + (q15_t)0x7f7f, (q15_t)0x807, (q15_t)0x7f80, (q15_t)0x7fb, (q15_t)0x7f82, (q15_t)0x7ef, (q15_t)0x7f83, (q15_t)0x7e2, + (q15_t)0x7f85, (q15_t)0x7d6, (q15_t)0x7f86, (q15_t)0x7c9, (q15_t)0x7f88, (q15_t)0x7bd, (q15_t)0x7f89, (q15_t)0x7b0, + (q15_t)0x7f8b, (q15_t)0x7a4, (q15_t)0x7f8c, (q15_t)0x797, (q15_t)0x7f8e, (q15_t)0x78b, (q15_t)0x7f8f, (q15_t)0x77e, + (q15_t)0x7f91, (q15_t)0x772, (q15_t)0x7f92, (q15_t)0x765, (q15_t)0x7f94, (q15_t)0x759, (q15_t)0x7f95, (q15_t)0x74c, + (q15_t)0x7f97, (q15_t)0x740, (q15_t)0x7f98, (q15_t)0x733, (q15_t)0x7f99, (q15_t)0x727, (q15_t)0x7f9b, (q15_t)0x71a, + (q15_t)0x7f9c, (q15_t)0x70e, (q15_t)0x7f9e, (q15_t)0x701, (q15_t)0x7f9f, (q15_t)0x6f5, (q15_t)0x7fa0, (q15_t)0x6e8, + (q15_t)0x7fa2, (q15_t)0x6dc, (q15_t)0x7fa3, (q15_t)0x6cf, (q15_t)0x7fa4, (q15_t)0x6c3, (q15_t)0x7fa6, (q15_t)0x6b6, + (q15_t)0x7fa7, (q15_t)0x6aa, (q15_t)0x7fa8, (q15_t)0x69d, (q15_t)0x7faa, (q15_t)0x691, (q15_t)0x7fab, (q15_t)0x684, + (q15_t)0x7fac, (q15_t)0x678, (q15_t)0x7fad, (q15_t)0x66b, (q15_t)0x7faf, (q15_t)0x65f, (q15_t)0x7fb0, (q15_t)0x652, + (q15_t)0x7fb1, (q15_t)0x646, (q15_t)0x7fb2, (q15_t)0x639, (q15_t)0x7fb4, (q15_t)0x62d, (q15_t)0x7fb5, (q15_t)0x620, + (q15_t)0x7fb6, (q15_t)0x614, (q15_t)0x7fb7, (q15_t)0x607, (q15_t)0x7fb8, (q15_t)0x5fb, (q15_t)0x7fb9, (q15_t)0x5ee, + (q15_t)0x7fbb, (q15_t)0x5e2, (q15_t)0x7fbc, (q15_t)0x5d5, (q15_t)0x7fbd, (q15_t)0x5c9, (q15_t)0x7fbe, (q15_t)0x5bc, + (q15_t)0x7fbf, (q15_t)0x5b0, (q15_t)0x7fc0, (q15_t)0x5a3, (q15_t)0x7fc1, (q15_t)0x597, (q15_t)0x7fc3, (q15_t)0x58a, + (q15_t)0x7fc4, (q15_t)0x57e, (q15_t)0x7fc5, (q15_t)0x571, (q15_t)0x7fc6, (q15_t)0x565, (q15_t)0x7fc7, (q15_t)0x558, + (q15_t)0x7fc8, (q15_t)0x54c, (q15_t)0x7fc9, (q15_t)0x53f, (q15_t)0x7fca, (q15_t)0x533, (q15_t)0x7fcb, (q15_t)0x526, + (q15_t)0x7fcc, (q15_t)0x51a, (q15_t)0x7fcd, (q15_t)0x50d, (q15_t)0x7fce, (q15_t)0x500, (q15_t)0x7fcf, (q15_t)0x4f4, + (q15_t)0x7fd0, (q15_t)0x4e7, (q15_t)0x7fd1, (q15_t)0x4db, (q15_t)0x7fd2, (q15_t)0x4ce, (q15_t)0x7fd3, (q15_t)0x4c2, + (q15_t)0x7fd4, (q15_t)0x4b5, (q15_t)0x7fd5, (q15_t)0x4a9, (q15_t)0x7fd5, (q15_t)0x49c, (q15_t)0x7fd6, (q15_t)0x490, + (q15_t)0x7fd7, (q15_t)0x483, (q15_t)0x7fd8, (q15_t)0x477, (q15_t)0x7fd9, (q15_t)0x46a, (q15_t)0x7fda, (q15_t)0x45e, + (q15_t)0x7fdb, (q15_t)0x451, (q15_t)0x7fdc, (q15_t)0x444, (q15_t)0x7fdc, (q15_t)0x438, (q15_t)0x7fdd, (q15_t)0x42b, + (q15_t)0x7fde, (q15_t)0x41f, (q15_t)0x7fdf, (q15_t)0x412, (q15_t)0x7fe0, (q15_t)0x406, (q15_t)0x7fe0, (q15_t)0x3f9, + (q15_t)0x7fe1, (q15_t)0x3ed, (q15_t)0x7fe2, (q15_t)0x3e0, (q15_t)0x7fe3, (q15_t)0x3d4, (q15_t)0x7fe3, (q15_t)0x3c7, + (q15_t)0x7fe4, (q15_t)0x3bb, (q15_t)0x7fe5, (q15_t)0x3ae, (q15_t)0x7fe6, (q15_t)0x3a1, (q15_t)0x7fe6, (q15_t)0x395, + (q15_t)0x7fe7, (q15_t)0x388, (q15_t)0x7fe8, (q15_t)0x37c, (q15_t)0x7fe8, (q15_t)0x36f, (q15_t)0x7fe9, (q15_t)0x363, + (q15_t)0x7fea, (q15_t)0x356, (q15_t)0x7fea, (q15_t)0x34a, (q15_t)0x7feb, (q15_t)0x33d, (q15_t)0x7fec, (q15_t)0x330, + (q15_t)0x7fec, (q15_t)0x324, (q15_t)0x7fed, (q15_t)0x317, (q15_t)0x7fed, (q15_t)0x30b, (q15_t)0x7fee, (q15_t)0x2fe, + (q15_t)0x7fef, (q15_t)0x2f2, (q15_t)0x7fef, (q15_t)0x2e5, (q15_t)0x7ff0, (q15_t)0x2d9, (q15_t)0x7ff0, (q15_t)0x2cc, + (q15_t)0x7ff1, (q15_t)0x2c0, (q15_t)0x7ff1, (q15_t)0x2b3, (q15_t)0x7ff2, (q15_t)0x2a6, (q15_t)0x7ff2, (q15_t)0x29a, + (q15_t)0x7ff3, (q15_t)0x28d, (q15_t)0x7ff3, (q15_t)0x281, (q15_t)0x7ff4, (q15_t)0x274, (q15_t)0x7ff4, (q15_t)0x268, + (q15_t)0x7ff5, (q15_t)0x25b, (q15_t)0x7ff5, (q15_t)0x24e, (q15_t)0x7ff6, (q15_t)0x242, (q15_t)0x7ff6, (q15_t)0x235, + (q15_t)0x7ff7, (q15_t)0x229, (q15_t)0x7ff7, (q15_t)0x21c, (q15_t)0x7ff7, (q15_t)0x210, (q15_t)0x7ff8, (q15_t)0x203, + (q15_t)0x7ff8, (q15_t)0x1f7, (q15_t)0x7ff9, (q15_t)0x1ea, (q15_t)0x7ff9, (q15_t)0x1dd, (q15_t)0x7ff9, (q15_t)0x1d1, + (q15_t)0x7ffa, (q15_t)0x1c4, (q15_t)0x7ffa, (q15_t)0x1b8, (q15_t)0x7ffa, (q15_t)0x1ab, (q15_t)0x7ffb, (q15_t)0x19f, + (q15_t)0x7ffb, (q15_t)0x192, (q15_t)0x7ffb, (q15_t)0x186, (q15_t)0x7ffc, (q15_t)0x179, (q15_t)0x7ffc, (q15_t)0x16c, + (q15_t)0x7ffc, (q15_t)0x160, (q15_t)0x7ffc, (q15_t)0x153, (q15_t)0x7ffd, (q15_t)0x147, (q15_t)0x7ffd, (q15_t)0x13a, + (q15_t)0x7ffd, (q15_t)0x12e, (q15_t)0x7ffd, (q15_t)0x121, (q15_t)0x7ffe, (q15_t)0x114, (q15_t)0x7ffe, (q15_t)0x108, + (q15_t)0x7ffe, (q15_t)0xfb, (q15_t)0x7ffe, (q15_t)0xef, (q15_t)0x7ffe, (q15_t)0xe2, (q15_t)0x7fff, (q15_t)0xd6, + (q15_t)0x7fff, (q15_t)0xc9, (q15_t)0x7fff, (q15_t)0xbc, (q15_t)0x7fff, (q15_t)0xb0, (q15_t)0x7fff, (q15_t)0xa3, + (q15_t)0x7fff, (q15_t)0x97, (q15_t)0x7fff, (q15_t)0x8a, (q15_t)0x7fff, (q15_t)0x7e, (q15_t)0x7fff, (q15_t)0x71, + (q15_t)0x7fff, (q15_t)0x65, (q15_t)0x7fff, (q15_t)0x58, (q15_t)0x7fff, (q15_t)0x4b, (q15_t)0x7fff, (q15_t)0x3f, + (q15_t)0x7fff, (q15_t)0x32, (q15_t)0x7fff, (q15_t)0x26, (q15_t)0x7fff, (q15_t)0x19, (q15_t)0x7fff, (q15_t)0xd, + (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xfff3, (q15_t)0x7fff, (q15_t)0xffe7, (q15_t)0x7fff, (q15_t)0xffda, + (q15_t)0x7fff, (q15_t)0xffce, (q15_t)0x7fff, (q15_t)0xffc1, (q15_t)0x7fff, (q15_t)0xffb5, (q15_t)0x7fff, (q15_t)0xffa8, + (q15_t)0x7fff, (q15_t)0xff9b, (q15_t)0x7fff, (q15_t)0xff8f, (q15_t)0x7fff, (q15_t)0xff82, (q15_t)0x7fff, (q15_t)0xff76, + (q15_t)0x7fff, (q15_t)0xff69, (q15_t)0x7fff, (q15_t)0xff5d, (q15_t)0x7fff, (q15_t)0xff50, (q15_t)0x7fff, (q15_t)0xff44, + (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7fff, (q15_t)0xff2a, (q15_t)0x7ffe, (q15_t)0xff1e, (q15_t)0x7ffe, (q15_t)0xff11, + (q15_t)0x7ffe, (q15_t)0xff05, (q15_t)0x7ffe, (q15_t)0xfef8, (q15_t)0x7ffe, (q15_t)0xfeec, (q15_t)0x7ffd, (q15_t)0xfedf, + (q15_t)0x7ffd, (q15_t)0xfed2, (q15_t)0x7ffd, (q15_t)0xfec6, (q15_t)0x7ffd, (q15_t)0xfeb9, (q15_t)0x7ffc, (q15_t)0xfead, + (q15_t)0x7ffc, (q15_t)0xfea0, (q15_t)0x7ffc, (q15_t)0xfe94, (q15_t)0x7ffc, (q15_t)0xfe87, (q15_t)0x7ffb, (q15_t)0xfe7a, + (q15_t)0x7ffb, (q15_t)0xfe6e, (q15_t)0x7ffb, (q15_t)0xfe61, (q15_t)0x7ffa, (q15_t)0xfe55, (q15_t)0x7ffa, (q15_t)0xfe48, + (q15_t)0x7ffa, (q15_t)0xfe3c, (q15_t)0x7ff9, (q15_t)0xfe2f, (q15_t)0x7ff9, (q15_t)0xfe23, (q15_t)0x7ff9, (q15_t)0xfe16, + (q15_t)0x7ff8, (q15_t)0xfe09, (q15_t)0x7ff8, (q15_t)0xfdfd, (q15_t)0x7ff7, (q15_t)0xfdf0, (q15_t)0x7ff7, (q15_t)0xfde4, + (q15_t)0x7ff7, (q15_t)0xfdd7, (q15_t)0x7ff6, (q15_t)0xfdcb, (q15_t)0x7ff6, (q15_t)0xfdbe, (q15_t)0x7ff5, (q15_t)0xfdb2, + (q15_t)0x7ff5, (q15_t)0xfda5, (q15_t)0x7ff4, (q15_t)0xfd98, (q15_t)0x7ff4, (q15_t)0xfd8c, (q15_t)0x7ff3, (q15_t)0xfd7f, + (q15_t)0x7ff3, (q15_t)0xfd73, (q15_t)0x7ff2, (q15_t)0xfd66, (q15_t)0x7ff2, (q15_t)0xfd5a, (q15_t)0x7ff1, (q15_t)0xfd4d, + (q15_t)0x7ff1, (q15_t)0xfd40, (q15_t)0x7ff0, (q15_t)0xfd34, (q15_t)0x7ff0, (q15_t)0xfd27, (q15_t)0x7fef, (q15_t)0xfd1b, + (q15_t)0x7fef, (q15_t)0xfd0e, (q15_t)0x7fee, (q15_t)0xfd02, (q15_t)0x7fed, (q15_t)0xfcf5, (q15_t)0x7fed, (q15_t)0xfce9, + (q15_t)0x7fec, (q15_t)0xfcdc, (q15_t)0x7fec, (q15_t)0xfcd0, (q15_t)0x7feb, (q15_t)0xfcc3, (q15_t)0x7fea, (q15_t)0xfcb6, + (q15_t)0x7fea, (q15_t)0xfcaa, (q15_t)0x7fe9, (q15_t)0xfc9d, (q15_t)0x7fe8, (q15_t)0xfc91, (q15_t)0x7fe8, (q15_t)0xfc84, + (q15_t)0x7fe7, (q15_t)0xfc78, (q15_t)0x7fe6, (q15_t)0xfc6b, (q15_t)0x7fe6, (q15_t)0xfc5f, (q15_t)0x7fe5, (q15_t)0xfc52, + (q15_t)0x7fe4, (q15_t)0xfc45, (q15_t)0x7fe3, (q15_t)0xfc39, (q15_t)0x7fe3, (q15_t)0xfc2c, (q15_t)0x7fe2, (q15_t)0xfc20, + (q15_t)0x7fe1, (q15_t)0xfc13, (q15_t)0x7fe0, (q15_t)0xfc07, (q15_t)0x7fe0, (q15_t)0xfbfa, (q15_t)0x7fdf, (q15_t)0xfbee, + (q15_t)0x7fde, (q15_t)0xfbe1, (q15_t)0x7fdd, (q15_t)0xfbd5, (q15_t)0x7fdc, (q15_t)0xfbc8, (q15_t)0x7fdc, (q15_t)0xfbbc, + (q15_t)0x7fdb, (q15_t)0xfbaf, (q15_t)0x7fda, (q15_t)0xfba2, (q15_t)0x7fd9, (q15_t)0xfb96, (q15_t)0x7fd8, (q15_t)0xfb89, + (q15_t)0x7fd7, (q15_t)0xfb7d, (q15_t)0x7fd6, (q15_t)0xfb70, (q15_t)0x7fd5, (q15_t)0xfb64, (q15_t)0x7fd5, (q15_t)0xfb57, + (q15_t)0x7fd4, (q15_t)0xfb4b, (q15_t)0x7fd3, (q15_t)0xfb3e, (q15_t)0x7fd2, (q15_t)0xfb32, (q15_t)0x7fd1, (q15_t)0xfb25, + (q15_t)0x7fd0, (q15_t)0xfb19, (q15_t)0x7fcf, (q15_t)0xfb0c, (q15_t)0x7fce, (q15_t)0xfb00, (q15_t)0x7fcd, (q15_t)0xfaf3, + (q15_t)0x7fcc, (q15_t)0xfae6, (q15_t)0x7fcb, (q15_t)0xfada, (q15_t)0x7fca, (q15_t)0xfacd, (q15_t)0x7fc9, (q15_t)0xfac1, + (q15_t)0x7fc8, (q15_t)0xfab4, (q15_t)0x7fc7, (q15_t)0xfaa8, (q15_t)0x7fc6, (q15_t)0xfa9b, (q15_t)0x7fc5, (q15_t)0xfa8f, + (q15_t)0x7fc4, (q15_t)0xfa82, (q15_t)0x7fc3, (q15_t)0xfa76, (q15_t)0x7fc1, (q15_t)0xfa69, (q15_t)0x7fc0, (q15_t)0xfa5d, + (q15_t)0x7fbf, (q15_t)0xfa50, (q15_t)0x7fbe, (q15_t)0xfa44, (q15_t)0x7fbd, (q15_t)0xfa37, (q15_t)0x7fbc, (q15_t)0xfa2b, + (q15_t)0x7fbb, (q15_t)0xfa1e, (q15_t)0x7fb9, (q15_t)0xfa12, (q15_t)0x7fb8, (q15_t)0xfa05, (q15_t)0x7fb7, (q15_t)0xf9f9, + (q15_t)0x7fb6, (q15_t)0xf9ec, (q15_t)0x7fb5, (q15_t)0xf9e0, (q15_t)0x7fb4, (q15_t)0xf9d3, (q15_t)0x7fb2, (q15_t)0xf9c7, + (q15_t)0x7fb1, (q15_t)0xf9ba, (q15_t)0x7fb0, (q15_t)0xf9ae, (q15_t)0x7faf, (q15_t)0xf9a1, (q15_t)0x7fad, (q15_t)0xf995, + (q15_t)0x7fac, (q15_t)0xf988, (q15_t)0x7fab, (q15_t)0xf97c, (q15_t)0x7faa, (q15_t)0xf96f, (q15_t)0x7fa8, (q15_t)0xf963, + (q15_t)0x7fa7, (q15_t)0xf956, (q15_t)0x7fa6, (q15_t)0xf94a, (q15_t)0x7fa4, (q15_t)0xf93d, (q15_t)0x7fa3, (q15_t)0xf931, + (q15_t)0x7fa2, (q15_t)0xf924, (q15_t)0x7fa0, (q15_t)0xf918, (q15_t)0x7f9f, (q15_t)0xf90b, (q15_t)0x7f9e, (q15_t)0xf8ff, + (q15_t)0x7f9c, (q15_t)0xf8f2, (q15_t)0x7f9b, (q15_t)0xf8e6, (q15_t)0x7f99, (q15_t)0xf8d9, (q15_t)0x7f98, (q15_t)0xf8cd, + (q15_t)0x7f97, (q15_t)0xf8c0, (q15_t)0x7f95, (q15_t)0xf8b4, (q15_t)0x7f94, (q15_t)0xf8a7, (q15_t)0x7f92, (q15_t)0xf89b, + (q15_t)0x7f91, (q15_t)0xf88e, (q15_t)0x7f8f, (q15_t)0xf882, (q15_t)0x7f8e, (q15_t)0xf875, (q15_t)0x7f8c, (q15_t)0xf869, + (q15_t)0x7f8b, (q15_t)0xf85c, (q15_t)0x7f89, (q15_t)0xf850, (q15_t)0x7f88, (q15_t)0xf843, (q15_t)0x7f86, (q15_t)0xf837, + (q15_t)0x7f85, (q15_t)0xf82a, (q15_t)0x7f83, (q15_t)0xf81e, (q15_t)0x7f82, (q15_t)0xf811, (q15_t)0x7f80, (q15_t)0xf805, + (q15_t)0x7f7f, (q15_t)0xf7f9, (q15_t)0x7f7d, (q15_t)0xf7ec, (q15_t)0x7f7b, (q15_t)0xf7e0, (q15_t)0x7f7a, (q15_t)0xf7d3, + (q15_t)0x7f78, (q15_t)0xf7c7, (q15_t)0x7f77, (q15_t)0xf7ba, (q15_t)0x7f75, (q15_t)0xf7ae, (q15_t)0x7f73, (q15_t)0xf7a1, + (q15_t)0x7f72, (q15_t)0xf795, (q15_t)0x7f70, (q15_t)0xf788, (q15_t)0x7f6e, (q15_t)0xf77c, (q15_t)0x7f6d, (q15_t)0xf76f, + (q15_t)0x7f6b, (q15_t)0xf763, (q15_t)0x7f69, (q15_t)0xf757, (q15_t)0x7f68, (q15_t)0xf74a, (q15_t)0x7f66, (q15_t)0xf73e, + (q15_t)0x7f64, (q15_t)0xf731, (q15_t)0x7f62, (q15_t)0xf725, (q15_t)0x7f61, (q15_t)0xf718, (q15_t)0x7f5f, (q15_t)0xf70c, + (q15_t)0x7f5d, (q15_t)0xf6ff, (q15_t)0x7f5b, (q15_t)0xf6f3, (q15_t)0x7f5a, (q15_t)0xf6e7, (q15_t)0x7f58, (q15_t)0xf6da, + (q15_t)0x7f56, (q15_t)0xf6ce, (q15_t)0x7f54, (q15_t)0xf6c1, (q15_t)0x7f52, (q15_t)0xf6b5, (q15_t)0x7f51, (q15_t)0xf6a8, + (q15_t)0x7f4f, (q15_t)0xf69c, (q15_t)0x7f4d, (q15_t)0xf690, (q15_t)0x7f4b, (q15_t)0xf683, (q15_t)0x7f49, (q15_t)0xf677, + (q15_t)0x7f47, (q15_t)0xf66a, (q15_t)0x7f45, (q15_t)0xf65e, (q15_t)0x7f43, (q15_t)0xf651, (q15_t)0x7f42, (q15_t)0xf645, + (q15_t)0x7f40, (q15_t)0xf639, (q15_t)0x7f3e, (q15_t)0xf62c, (q15_t)0x7f3c, (q15_t)0xf620, (q15_t)0x7f3a, (q15_t)0xf613, + (q15_t)0x7f38, (q15_t)0xf607, (q15_t)0x7f36, (q15_t)0xf5fa, (q15_t)0x7f34, (q15_t)0xf5ee, (q15_t)0x7f32, (q15_t)0xf5e2, + (q15_t)0x7f30, (q15_t)0xf5d5, (q15_t)0x7f2e, (q15_t)0xf5c9, (q15_t)0x7f2c, (q15_t)0xf5bc, (q15_t)0x7f2a, (q15_t)0xf5b0, + (q15_t)0x7f28, (q15_t)0xf5a4, (q15_t)0x7f26, (q15_t)0xf597, (q15_t)0x7f24, (q15_t)0xf58b, (q15_t)0x7f22, (q15_t)0xf57e, + (q15_t)0x7f20, (q15_t)0xf572, (q15_t)0x7f1e, (q15_t)0xf566, (q15_t)0x7f1c, (q15_t)0xf559, (q15_t)0x7f19, (q15_t)0xf54d, + (q15_t)0x7f17, (q15_t)0xf540, (q15_t)0x7f15, (q15_t)0xf534, (q15_t)0x7f13, (q15_t)0xf528, (q15_t)0x7f11, (q15_t)0xf51b, + (q15_t)0x7f0f, (q15_t)0xf50f, (q15_t)0x7f0d, (q15_t)0xf503, (q15_t)0x7f0a, (q15_t)0xf4f6, (q15_t)0x7f08, (q15_t)0xf4ea, + (q15_t)0x7f06, (q15_t)0xf4dd, (q15_t)0x7f04, (q15_t)0xf4d1, (q15_t)0x7f02, (q15_t)0xf4c5, (q15_t)0x7f00, (q15_t)0xf4b8, + (q15_t)0x7efd, (q15_t)0xf4ac, (q15_t)0x7efb, (q15_t)0xf4a0, (q15_t)0x7ef9, (q15_t)0xf493, (q15_t)0x7ef7, (q15_t)0xf487, + (q15_t)0x7ef4, (q15_t)0xf47b, (q15_t)0x7ef2, (q15_t)0xf46e, (q15_t)0x7ef0, (q15_t)0xf462, (q15_t)0x7eed, (q15_t)0xf455, + (q15_t)0x7eeb, (q15_t)0xf449, (q15_t)0x7ee9, (q15_t)0xf43d, (q15_t)0x7ee7, (q15_t)0xf430, (q15_t)0x7ee4, (q15_t)0xf424, + (q15_t)0x7ee2, (q15_t)0xf418, (q15_t)0x7ee0, (q15_t)0xf40b, (q15_t)0x7edd, (q15_t)0xf3ff, (q15_t)0x7edb, (q15_t)0xf3f3, + (q15_t)0x7ed8, (q15_t)0xf3e6, (q15_t)0x7ed6, (q15_t)0xf3da, (q15_t)0x7ed4, (q15_t)0xf3ce, (q15_t)0x7ed1, (q15_t)0xf3c1, + (q15_t)0x7ecf, (q15_t)0xf3b5, (q15_t)0x7ecc, (q15_t)0xf3a9, (q15_t)0x7eca, (q15_t)0xf39c, (q15_t)0x7ec8, (q15_t)0xf390, + (q15_t)0x7ec5, (q15_t)0xf384, (q15_t)0x7ec3, (q15_t)0xf377, (q15_t)0x7ec0, (q15_t)0xf36b, (q15_t)0x7ebe, (q15_t)0xf35f, + (q15_t)0x7ebb, (q15_t)0xf352, (q15_t)0x7eb9, (q15_t)0xf346, (q15_t)0x7eb6, (q15_t)0xf33a, (q15_t)0x7eb4, (q15_t)0xf32d, + (q15_t)0x7eb1, (q15_t)0xf321, (q15_t)0x7eaf, (q15_t)0xf315, (q15_t)0x7eac, (q15_t)0xf308, (q15_t)0x7eaa, (q15_t)0xf2fc, + (q15_t)0x7ea7, (q15_t)0xf2f0, (q15_t)0x7ea5, (q15_t)0xf2e4, (q15_t)0x7ea2, (q15_t)0xf2d7, (q15_t)0x7e9f, (q15_t)0xf2cb, + (q15_t)0x7e9d, (q15_t)0xf2bf, (q15_t)0x7e9a, (q15_t)0xf2b2, (q15_t)0x7e98, (q15_t)0xf2a6, (q15_t)0x7e95, (q15_t)0xf29a, + (q15_t)0x7e92, (q15_t)0xf28e, (q15_t)0x7e90, (q15_t)0xf281, (q15_t)0x7e8d, (q15_t)0xf275, (q15_t)0x7e8a, (q15_t)0xf269, + (q15_t)0x7e88, (q15_t)0xf25c, (q15_t)0x7e85, (q15_t)0xf250, (q15_t)0x7e82, (q15_t)0xf244, (q15_t)0x7e80, (q15_t)0xf238, + (q15_t)0x7e7d, (q15_t)0xf22b, (q15_t)0x7e7a, (q15_t)0xf21f, (q15_t)0x7e77, (q15_t)0xf213, (q15_t)0x7e75, (q15_t)0xf207, + (q15_t)0x7e72, (q15_t)0xf1fa, (q15_t)0x7e6f, (q15_t)0xf1ee, (q15_t)0x7e6c, (q15_t)0xf1e2, (q15_t)0x7e6a, (q15_t)0xf1d5, + (q15_t)0x7e67, (q15_t)0xf1c9, (q15_t)0x7e64, (q15_t)0xf1bd, (q15_t)0x7e61, (q15_t)0xf1b1, (q15_t)0x7e5e, (q15_t)0xf1a4, + (q15_t)0x7e5c, (q15_t)0xf198, (q15_t)0x7e59, (q15_t)0xf18c, (q15_t)0x7e56, (q15_t)0xf180, (q15_t)0x7e53, (q15_t)0xf174, + (q15_t)0x7e50, (q15_t)0xf167, (q15_t)0x7e4d, (q15_t)0xf15b, (q15_t)0x7e4a, (q15_t)0xf14f, (q15_t)0x7e48, (q15_t)0xf143, + (q15_t)0x7e45, (q15_t)0xf136, (q15_t)0x7e42, (q15_t)0xf12a, (q15_t)0x7e3f, (q15_t)0xf11e, (q15_t)0x7e3c, (q15_t)0xf112, + (q15_t)0x7e39, (q15_t)0xf105, (q15_t)0x7e36, (q15_t)0xf0f9, (q15_t)0x7e33, (q15_t)0xf0ed, (q15_t)0x7e30, (q15_t)0xf0e1, + (q15_t)0x7e2d, (q15_t)0xf0d5, (q15_t)0x7e2a, (q15_t)0xf0c8, (q15_t)0x7e27, (q15_t)0xf0bc, (q15_t)0x7e24, (q15_t)0xf0b0, + (q15_t)0x7e21, (q15_t)0xf0a4, (q15_t)0x7e1e, (q15_t)0xf098, (q15_t)0x7e1b, (q15_t)0xf08b, (q15_t)0x7e18, (q15_t)0xf07f, + (q15_t)0x7e15, (q15_t)0xf073, (q15_t)0x7e12, (q15_t)0xf067, (q15_t)0x7e0f, (q15_t)0xf05b, (q15_t)0x7e0c, (q15_t)0xf04e, + (q15_t)0x7e09, (q15_t)0xf042, (q15_t)0x7e06, (q15_t)0xf036, (q15_t)0x7e03, (q15_t)0xf02a, (q15_t)0x7dff, (q15_t)0xf01e, + (q15_t)0x7dfc, (q15_t)0xf012, (q15_t)0x7df9, (q15_t)0xf005, (q15_t)0x7df6, (q15_t)0xeff9, (q15_t)0x7df3, (q15_t)0xefed, + (q15_t)0x7df0, (q15_t)0xefe1, (q15_t)0x7ded, (q15_t)0xefd5, (q15_t)0x7de9, (q15_t)0xefc9, (q15_t)0x7de6, (q15_t)0xefbc, + (q15_t)0x7de3, (q15_t)0xefb0, (q15_t)0x7de0, (q15_t)0xefa4, (q15_t)0x7ddd, (q15_t)0xef98, (q15_t)0x7dd9, (q15_t)0xef8c, + (q15_t)0x7dd6, (q15_t)0xef80, (q15_t)0x7dd3, (q15_t)0xef74, (q15_t)0x7dd0, (q15_t)0xef67, (q15_t)0x7dcc, (q15_t)0xef5b, + (q15_t)0x7dc9, (q15_t)0xef4f, (q15_t)0x7dc6, (q15_t)0xef43, (q15_t)0x7dc2, (q15_t)0xef37, (q15_t)0x7dbf, (q15_t)0xef2b, + (q15_t)0x7dbc, (q15_t)0xef1f, (q15_t)0x7db9, (q15_t)0xef13, (q15_t)0x7db5, (q15_t)0xef06, (q15_t)0x7db2, (q15_t)0xeefa, + (q15_t)0x7daf, (q15_t)0xeeee, (q15_t)0x7dab, (q15_t)0xeee2, (q15_t)0x7da8, (q15_t)0xeed6, (q15_t)0x7da4, (q15_t)0xeeca, + (q15_t)0x7da1, (q15_t)0xeebe, (q15_t)0x7d9e, (q15_t)0xeeb2, (q15_t)0x7d9a, (q15_t)0xeea6, (q15_t)0x7d97, (q15_t)0xee99, + (q15_t)0x7d93, (q15_t)0xee8d, (q15_t)0x7d90, (q15_t)0xee81, (q15_t)0x7d8d, (q15_t)0xee75, (q15_t)0x7d89, (q15_t)0xee69, + (q15_t)0x7d86, (q15_t)0xee5d, (q15_t)0x7d82, (q15_t)0xee51, (q15_t)0x7d7f, (q15_t)0xee45, (q15_t)0x7d7b, (q15_t)0xee39, + (q15_t)0x7d78, (q15_t)0xee2d, (q15_t)0x7d74, (q15_t)0xee21, (q15_t)0x7d71, (q15_t)0xee15, (q15_t)0x7d6d, (q15_t)0xee09, + (q15_t)0x7d6a, (q15_t)0xedfc, (q15_t)0x7d66, (q15_t)0xedf0, (q15_t)0x7d63, (q15_t)0xede4, (q15_t)0x7d5f, (q15_t)0xedd8, + (q15_t)0x7d5b, (q15_t)0xedcc, (q15_t)0x7d58, (q15_t)0xedc0, (q15_t)0x7d54, (q15_t)0xedb4, (q15_t)0x7d51, (q15_t)0xeda8, + (q15_t)0x7d4d, (q15_t)0xed9c, (q15_t)0x7d49, (q15_t)0xed90, (q15_t)0x7d46, (q15_t)0xed84, (q15_t)0x7d42, (q15_t)0xed78, + (q15_t)0x7d3f, (q15_t)0xed6c, (q15_t)0x7d3b, (q15_t)0xed60, (q15_t)0x7d37, (q15_t)0xed54, (q15_t)0x7d34, (q15_t)0xed48, + (q15_t)0x7d30, (q15_t)0xed3c, (q15_t)0x7d2c, (q15_t)0xed30, (q15_t)0x7d28, (q15_t)0xed24, (q15_t)0x7d25, (q15_t)0xed18, + (q15_t)0x7d21, (q15_t)0xed0c, (q15_t)0x7d1d, (q15_t)0xed00, (q15_t)0x7d1a, (q15_t)0xecf4, (q15_t)0x7d16, (q15_t)0xece8, + (q15_t)0x7d12, (q15_t)0xecdc, (q15_t)0x7d0e, (q15_t)0xecd0, (q15_t)0x7d0b, (q15_t)0xecc4, (q15_t)0x7d07, (q15_t)0xecb8, + (q15_t)0x7d03, (q15_t)0xecac, (q15_t)0x7cff, (q15_t)0xeca0, (q15_t)0x7cfb, (q15_t)0xec94, (q15_t)0x7cf8, (q15_t)0xec88, + (q15_t)0x7cf4, (q15_t)0xec7c, (q15_t)0x7cf0, (q15_t)0xec70, (q15_t)0x7cec, (q15_t)0xec64, (q15_t)0x7ce8, (q15_t)0xec58, + (q15_t)0x7ce4, (q15_t)0xec4c, (q15_t)0x7ce0, (q15_t)0xec40, (q15_t)0x7cdd, (q15_t)0xec34, (q15_t)0x7cd9, (q15_t)0xec28, + (q15_t)0x7cd5, (q15_t)0xec1c, (q15_t)0x7cd1, (q15_t)0xec10, (q15_t)0x7ccd, (q15_t)0xec05, (q15_t)0x7cc9, (q15_t)0xebf9, + (q15_t)0x7cc5, (q15_t)0xebed, (q15_t)0x7cc1, (q15_t)0xebe1, (q15_t)0x7cbd, (q15_t)0xebd5, (q15_t)0x7cb9, (q15_t)0xebc9, + (q15_t)0x7cb5, (q15_t)0xebbd, (q15_t)0x7cb1, (q15_t)0xebb1, (q15_t)0x7cad, (q15_t)0xeba5, (q15_t)0x7ca9, (q15_t)0xeb99, + (q15_t)0x7ca5, (q15_t)0xeb8d, (q15_t)0x7ca1, (q15_t)0xeb81, (q15_t)0x7c9d, (q15_t)0xeb75, (q15_t)0x7c99, (q15_t)0xeb6a, + (q15_t)0x7c95, (q15_t)0xeb5e, (q15_t)0x7c91, (q15_t)0xeb52, (q15_t)0x7c8d, (q15_t)0xeb46, (q15_t)0x7c89, (q15_t)0xeb3a, + (q15_t)0x7c85, (q15_t)0xeb2e, (q15_t)0x7c81, (q15_t)0xeb22, (q15_t)0x7c7d, (q15_t)0xeb16, (q15_t)0x7c79, (q15_t)0xeb0a, + (q15_t)0x7c74, (q15_t)0xeaff, (q15_t)0x7c70, (q15_t)0xeaf3, (q15_t)0x7c6c, (q15_t)0xeae7, (q15_t)0x7c68, (q15_t)0xeadb, + (q15_t)0x7c64, (q15_t)0xeacf, (q15_t)0x7c60, (q15_t)0xeac3, (q15_t)0x7c5b, (q15_t)0xeab7, (q15_t)0x7c57, (q15_t)0xeaac, + (q15_t)0x7c53, (q15_t)0xeaa0, (q15_t)0x7c4f, (q15_t)0xea94, (q15_t)0x7c4b, (q15_t)0xea88, (q15_t)0x7c46, (q15_t)0xea7c, + (q15_t)0x7c42, (q15_t)0xea70, (q15_t)0x7c3e, (q15_t)0xea65, (q15_t)0x7c3a, (q15_t)0xea59, (q15_t)0x7c36, (q15_t)0xea4d, + (q15_t)0x7c31, (q15_t)0xea41, (q15_t)0x7c2d, (q15_t)0xea35, (q15_t)0x7c29, (q15_t)0xea29, (q15_t)0x7c24, (q15_t)0xea1e, + (q15_t)0x7c20, (q15_t)0xea12, (q15_t)0x7c1c, (q15_t)0xea06, (q15_t)0x7c17, (q15_t)0xe9fa, (q15_t)0x7c13, (q15_t)0xe9ee, + (q15_t)0x7c0f, (q15_t)0xe9e3, (q15_t)0x7c0a, (q15_t)0xe9d7, (q15_t)0x7c06, (q15_t)0xe9cb, (q15_t)0x7c02, (q15_t)0xe9bf, + (q15_t)0x7bfd, (q15_t)0xe9b4, (q15_t)0x7bf9, (q15_t)0xe9a8, (q15_t)0x7bf5, (q15_t)0xe99c, (q15_t)0x7bf0, (q15_t)0xe990, + (q15_t)0x7bec, (q15_t)0xe984, (q15_t)0x7be7, (q15_t)0xe979, (q15_t)0x7be3, (q15_t)0xe96d, (q15_t)0x7bde, (q15_t)0xe961, + (q15_t)0x7bda, (q15_t)0xe955, (q15_t)0x7bd6, (q15_t)0xe94a, (q15_t)0x7bd1, (q15_t)0xe93e, (q15_t)0x7bcd, (q15_t)0xe932, + (q15_t)0x7bc8, (q15_t)0xe926, (q15_t)0x7bc4, (q15_t)0xe91b, (q15_t)0x7bbf, (q15_t)0xe90f, (q15_t)0x7bbb, (q15_t)0xe903, + (q15_t)0x7bb6, (q15_t)0xe8f7, (q15_t)0x7bb2, (q15_t)0xe8ec, (q15_t)0x7bad, (q15_t)0xe8e0, (q15_t)0x7ba9, (q15_t)0xe8d4, + (q15_t)0x7ba4, (q15_t)0xe8c9, (q15_t)0x7b9f, (q15_t)0xe8bd, (q15_t)0x7b9b, (q15_t)0xe8b1, (q15_t)0x7b96, (q15_t)0xe8a5, + (q15_t)0x7b92, (q15_t)0xe89a, (q15_t)0x7b8d, (q15_t)0xe88e, (q15_t)0x7b88, (q15_t)0xe882, (q15_t)0x7b84, (q15_t)0xe877, + (q15_t)0x7b7f, (q15_t)0xe86b, (q15_t)0x7b7b, (q15_t)0xe85f, (q15_t)0x7b76, (q15_t)0xe854, (q15_t)0x7b71, (q15_t)0xe848, + (q15_t)0x7b6d, (q15_t)0xe83c, (q15_t)0x7b68, (q15_t)0xe831, (q15_t)0x7b63, (q15_t)0xe825, (q15_t)0x7b5f, (q15_t)0xe819, + (q15_t)0x7b5a, (q15_t)0xe80e, (q15_t)0x7b55, (q15_t)0xe802, (q15_t)0x7b50, (q15_t)0xe7f6, (q15_t)0x7b4c, (q15_t)0xe7eb, + (q15_t)0x7b47, (q15_t)0xe7df, (q15_t)0x7b42, (q15_t)0xe7d3, (q15_t)0x7b3e, (q15_t)0xe7c8, (q15_t)0x7b39, (q15_t)0xe7bc, + (q15_t)0x7b34, (q15_t)0xe7b1, (q15_t)0x7b2f, (q15_t)0xe7a5, (q15_t)0x7b2a, (q15_t)0xe799, (q15_t)0x7b26, (q15_t)0xe78e, + (q15_t)0x7b21, (q15_t)0xe782, (q15_t)0x7b1c, (q15_t)0xe777, (q15_t)0x7b17, (q15_t)0xe76b, (q15_t)0x7b12, (q15_t)0xe75f, + (q15_t)0x7b0e, (q15_t)0xe754, (q15_t)0x7b09, (q15_t)0xe748, (q15_t)0x7b04, (q15_t)0xe73d, (q15_t)0x7aff, (q15_t)0xe731, + (q15_t)0x7afa, (q15_t)0xe725, (q15_t)0x7af5, (q15_t)0xe71a, (q15_t)0x7af0, (q15_t)0xe70e, (q15_t)0x7aeb, (q15_t)0xe703, + (q15_t)0x7ae6, (q15_t)0xe6f7, (q15_t)0x7ae2, (q15_t)0xe6ec, (q15_t)0x7add, (q15_t)0xe6e0, (q15_t)0x7ad8, (q15_t)0xe6d4, + (q15_t)0x7ad3, (q15_t)0xe6c9, (q15_t)0x7ace, (q15_t)0xe6bd, (q15_t)0x7ac9, (q15_t)0xe6b2, (q15_t)0x7ac4, (q15_t)0xe6a6, + (q15_t)0x7abf, (q15_t)0xe69b, (q15_t)0x7aba, (q15_t)0xe68f, (q15_t)0x7ab5, (q15_t)0xe684, (q15_t)0x7ab0, (q15_t)0xe678, + (q15_t)0x7aab, (q15_t)0xe66d, (q15_t)0x7aa6, (q15_t)0xe661, (q15_t)0x7aa1, (q15_t)0xe656, (q15_t)0x7a9c, (q15_t)0xe64a, + (q15_t)0x7a97, (q15_t)0xe63f, (q15_t)0x7a92, (q15_t)0xe633, (q15_t)0x7a8d, (q15_t)0xe628, (q15_t)0x7a88, (q15_t)0xe61c, + (q15_t)0x7a82, (q15_t)0xe611, (q15_t)0x7a7d, (q15_t)0xe605, (q15_t)0x7a78, (q15_t)0xe5fa, (q15_t)0x7a73, (q15_t)0xe5ee, + (q15_t)0x7a6e, (q15_t)0xe5e3, (q15_t)0x7a69, (q15_t)0xe5d7, (q15_t)0x7a64, (q15_t)0xe5cc, (q15_t)0x7a5f, (q15_t)0xe5c0, + (q15_t)0x7a59, (q15_t)0xe5b5, (q15_t)0x7a54, (q15_t)0xe5a9, (q15_t)0x7a4f, (q15_t)0xe59e, (q15_t)0x7a4a, (q15_t)0xe592, + (q15_t)0x7a45, (q15_t)0xe587, (q15_t)0x7a3f, (q15_t)0xe57c, (q15_t)0x7a3a, (q15_t)0xe570, (q15_t)0x7a35, (q15_t)0xe565, + (q15_t)0x7a30, (q15_t)0xe559, (q15_t)0x7a2b, (q15_t)0xe54e, (q15_t)0x7a25, (q15_t)0xe542, (q15_t)0x7a20, (q15_t)0xe537, + (q15_t)0x7a1b, (q15_t)0xe52c, (q15_t)0x7a16, (q15_t)0xe520, (q15_t)0x7a10, (q15_t)0xe515, (q15_t)0x7a0b, (q15_t)0xe509, + (q15_t)0x7a06, (q15_t)0xe4fe, (q15_t)0x7a00, (q15_t)0xe4f3, (q15_t)0x79fb, (q15_t)0xe4e7, (q15_t)0x79f6, (q15_t)0xe4dc, + (q15_t)0x79f0, (q15_t)0xe4d0, (q15_t)0x79eb, (q15_t)0xe4c5, (q15_t)0x79e6, (q15_t)0xe4ba, (q15_t)0x79e0, (q15_t)0xe4ae, + (q15_t)0x79db, (q15_t)0xe4a3, (q15_t)0x79d6, (q15_t)0xe498, (q15_t)0x79d0, (q15_t)0xe48c, (q15_t)0x79cb, (q15_t)0xe481, + (q15_t)0x79c5, (q15_t)0xe476, (q15_t)0x79c0, (q15_t)0xe46a, (q15_t)0x79bb, (q15_t)0xe45f, (q15_t)0x79b5, (q15_t)0xe454, + (q15_t)0x79b0, (q15_t)0xe448, (q15_t)0x79aa, (q15_t)0xe43d, (q15_t)0x79a5, (q15_t)0xe432, (q15_t)0x799f, (q15_t)0xe426, + (q15_t)0x799a, (q15_t)0xe41b, (q15_t)0x7994, (q15_t)0xe410, (q15_t)0x798f, (q15_t)0xe404, (q15_t)0x7989, (q15_t)0xe3f9, + (q15_t)0x7984, (q15_t)0xe3ee, (q15_t)0x797e, (q15_t)0xe3e2, (q15_t)0x7979, (q15_t)0xe3d7, (q15_t)0x7973, (q15_t)0xe3cc, + (q15_t)0x796e, (q15_t)0xe3c1, (q15_t)0x7968, (q15_t)0xe3b5, (q15_t)0x7963, (q15_t)0xe3aa, (q15_t)0x795d, (q15_t)0xe39f, + (q15_t)0x7958, (q15_t)0xe394, (q15_t)0x7952, (q15_t)0xe388, (q15_t)0x794c, (q15_t)0xe37d, (q15_t)0x7947, (q15_t)0xe372, + (q15_t)0x7941, (q15_t)0xe367, (q15_t)0x793b, (q15_t)0xe35b, (q15_t)0x7936, (q15_t)0xe350, (q15_t)0x7930, (q15_t)0xe345, + (q15_t)0x792b, (q15_t)0xe33a, (q15_t)0x7925, (q15_t)0xe32e, (q15_t)0x791f, (q15_t)0xe323, (q15_t)0x791a, (q15_t)0xe318, + (q15_t)0x7914, (q15_t)0xe30d, (q15_t)0x790e, (q15_t)0xe301, (q15_t)0x7909, (q15_t)0xe2f6, (q15_t)0x7903, (q15_t)0xe2eb, + (q15_t)0x78fd, (q15_t)0xe2e0, (q15_t)0x78f7, (q15_t)0xe2d5, (q15_t)0x78f2, (q15_t)0xe2ca, (q15_t)0x78ec, (q15_t)0xe2be, + (q15_t)0x78e6, (q15_t)0xe2b3, (q15_t)0x78e0, (q15_t)0xe2a8, (q15_t)0x78db, (q15_t)0xe29d, (q15_t)0x78d5, (q15_t)0xe292, + (q15_t)0x78cf, (q15_t)0xe287, (q15_t)0x78c9, (q15_t)0xe27b, (q15_t)0x78c3, (q15_t)0xe270, (q15_t)0x78be, (q15_t)0xe265, + (q15_t)0x78b8, (q15_t)0xe25a, (q15_t)0x78b2, (q15_t)0xe24f, (q15_t)0x78ac, (q15_t)0xe244, (q15_t)0x78a6, (q15_t)0xe239, + (q15_t)0x78a1, (q15_t)0xe22d, (q15_t)0x789b, (q15_t)0xe222, (q15_t)0x7895, (q15_t)0xe217, (q15_t)0x788f, (q15_t)0xe20c, + (q15_t)0x7889, (q15_t)0xe201, (q15_t)0x7883, (q15_t)0xe1f6, (q15_t)0x787d, (q15_t)0xe1eb, (q15_t)0x7877, (q15_t)0xe1e0, + (q15_t)0x7871, (q15_t)0xe1d5, (q15_t)0x786b, (q15_t)0xe1ca, (q15_t)0x7866, (q15_t)0xe1be, (q15_t)0x7860, (q15_t)0xe1b3, + (q15_t)0x785a, (q15_t)0xe1a8, (q15_t)0x7854, (q15_t)0xe19d, (q15_t)0x784e, (q15_t)0xe192, (q15_t)0x7848, (q15_t)0xe187, + (q15_t)0x7842, (q15_t)0xe17c, (q15_t)0x783c, (q15_t)0xe171, (q15_t)0x7836, (q15_t)0xe166, (q15_t)0x7830, (q15_t)0xe15b, + (q15_t)0x782a, (q15_t)0xe150, (q15_t)0x7824, (q15_t)0xe145, (q15_t)0x781e, (q15_t)0xe13a, (q15_t)0x7818, (q15_t)0xe12f, + (q15_t)0x7812, (q15_t)0xe124, (q15_t)0x780b, (q15_t)0xe119, (q15_t)0x7805, (q15_t)0xe10e, (q15_t)0x77ff, (q15_t)0xe103, + (q15_t)0x77f9, (q15_t)0xe0f8, (q15_t)0x77f3, (q15_t)0xe0ed, (q15_t)0x77ed, (q15_t)0xe0e2, (q15_t)0x77e7, (q15_t)0xe0d7, + (q15_t)0x77e1, (q15_t)0xe0cc, (q15_t)0x77db, (q15_t)0xe0c1, (q15_t)0x77d5, (q15_t)0xe0b6, (q15_t)0x77ce, (q15_t)0xe0ab, + (q15_t)0x77c8, (q15_t)0xe0a0, (q15_t)0x77c2, (q15_t)0xe095, (q15_t)0x77bc, (q15_t)0xe08a, (q15_t)0x77b6, (q15_t)0xe07f, + (q15_t)0x77b0, (q15_t)0xe074, (q15_t)0x77a9, (q15_t)0xe069, (q15_t)0x77a3, (q15_t)0xe05e, (q15_t)0x779d, (q15_t)0xe054, + (q15_t)0x7797, (q15_t)0xe049, (q15_t)0x7790, (q15_t)0xe03e, (q15_t)0x778a, (q15_t)0xe033, (q15_t)0x7784, (q15_t)0xe028, + (q15_t)0x777e, (q15_t)0xe01d, (q15_t)0x7777, (q15_t)0xe012, (q15_t)0x7771, (q15_t)0xe007, (q15_t)0x776b, (q15_t)0xdffc, + (q15_t)0x7765, (q15_t)0xdff1, (q15_t)0x775e, (q15_t)0xdfe7, (q15_t)0x7758, (q15_t)0xdfdc, (q15_t)0x7752, (q15_t)0xdfd1, + (q15_t)0x774b, (q15_t)0xdfc6, (q15_t)0x7745, (q15_t)0xdfbb, (q15_t)0x773f, (q15_t)0xdfb0, (q15_t)0x7738, (q15_t)0xdfa5, + (q15_t)0x7732, (q15_t)0xdf9b, (q15_t)0x772c, (q15_t)0xdf90, (q15_t)0x7725, (q15_t)0xdf85, (q15_t)0x771f, (q15_t)0xdf7a, + (q15_t)0x7718, (q15_t)0xdf6f, (q15_t)0x7712, (q15_t)0xdf65, (q15_t)0x770c, (q15_t)0xdf5a, (q15_t)0x7705, (q15_t)0xdf4f, + (q15_t)0x76ff, (q15_t)0xdf44, (q15_t)0x76f8, (q15_t)0xdf39, (q15_t)0x76f2, (q15_t)0xdf2f, (q15_t)0x76eb, (q15_t)0xdf24, + (q15_t)0x76e5, (q15_t)0xdf19, (q15_t)0x76df, (q15_t)0xdf0e, (q15_t)0x76d8, (q15_t)0xdf03, (q15_t)0x76d2, (q15_t)0xdef9, + (q15_t)0x76cb, (q15_t)0xdeee, (q15_t)0x76c5, (q15_t)0xdee3, (q15_t)0x76be, (q15_t)0xded8, (q15_t)0x76b8, (q15_t)0xdece, + (q15_t)0x76b1, (q15_t)0xdec3, (q15_t)0x76ab, (q15_t)0xdeb8, (q15_t)0x76a4, (q15_t)0xdead, (q15_t)0x769d, (q15_t)0xdea3, + (q15_t)0x7697, (q15_t)0xde98, (q15_t)0x7690, (q15_t)0xde8d, (q15_t)0x768a, (q15_t)0xde83, (q15_t)0x7683, (q15_t)0xde78, + (q15_t)0x767d, (q15_t)0xde6d, (q15_t)0x7676, (q15_t)0xde62, (q15_t)0x766f, (q15_t)0xde58, (q15_t)0x7669, (q15_t)0xde4d, + (q15_t)0x7662, (q15_t)0xde42, (q15_t)0x765c, (q15_t)0xde38, (q15_t)0x7655, (q15_t)0xde2d, (q15_t)0x764e, (q15_t)0xde22, + (q15_t)0x7648, (q15_t)0xde18, (q15_t)0x7641, (q15_t)0xde0d, (q15_t)0x763a, (q15_t)0xde02, (q15_t)0x7634, (q15_t)0xddf8, + (q15_t)0x762d, (q15_t)0xdded, (q15_t)0x7626, (q15_t)0xdde2, (q15_t)0x7620, (q15_t)0xddd8, (q15_t)0x7619, (q15_t)0xddcd, + (q15_t)0x7612, (q15_t)0xddc3, (q15_t)0x760b, (q15_t)0xddb8, (q15_t)0x7605, (q15_t)0xddad, (q15_t)0x75fe, (q15_t)0xdda3, + (q15_t)0x75f7, (q15_t)0xdd98, (q15_t)0x75f0, (q15_t)0xdd8e, (q15_t)0x75ea, (q15_t)0xdd83, (q15_t)0x75e3, (q15_t)0xdd78, + (q15_t)0x75dc, (q15_t)0xdd6e, (q15_t)0x75d5, (q15_t)0xdd63, (q15_t)0x75ce, (q15_t)0xdd59, (q15_t)0x75c8, (q15_t)0xdd4e, + (q15_t)0x75c1, (q15_t)0xdd44, (q15_t)0x75ba, (q15_t)0xdd39, (q15_t)0x75b3, (q15_t)0xdd2e, (q15_t)0x75ac, (q15_t)0xdd24, + (q15_t)0x75a5, (q15_t)0xdd19, (q15_t)0x759f, (q15_t)0xdd0f, (q15_t)0x7598, (q15_t)0xdd04, (q15_t)0x7591, (q15_t)0xdcfa, + (q15_t)0x758a, (q15_t)0xdcef, (q15_t)0x7583, (q15_t)0xdce5, (q15_t)0x757c, (q15_t)0xdcda, (q15_t)0x7575, (q15_t)0xdcd0, + (q15_t)0x756e, (q15_t)0xdcc5, (q15_t)0x7567, (q15_t)0xdcbb, (q15_t)0x7561, (q15_t)0xdcb0, (q15_t)0x755a, (q15_t)0xdca6, + (q15_t)0x7553, (q15_t)0xdc9b, (q15_t)0x754c, (q15_t)0xdc91, (q15_t)0x7545, (q15_t)0xdc86, (q15_t)0x753e, (q15_t)0xdc7c, + (q15_t)0x7537, (q15_t)0xdc72, (q15_t)0x7530, (q15_t)0xdc67, (q15_t)0x7529, (q15_t)0xdc5d, (q15_t)0x7522, (q15_t)0xdc52, + (q15_t)0x751b, (q15_t)0xdc48, (q15_t)0x7514, (q15_t)0xdc3d, (q15_t)0x750d, (q15_t)0xdc33, (q15_t)0x7506, (q15_t)0xdc29, + (q15_t)0x74ff, (q15_t)0xdc1e, (q15_t)0x74f8, (q15_t)0xdc14, (q15_t)0x74f1, (q15_t)0xdc09, (q15_t)0x74ea, (q15_t)0xdbff, + (q15_t)0x74e2, (q15_t)0xdbf5, (q15_t)0x74db, (q15_t)0xdbea, (q15_t)0x74d4, (q15_t)0xdbe0, (q15_t)0x74cd, (q15_t)0xdbd5, + (q15_t)0x74c6, (q15_t)0xdbcb, (q15_t)0x74bf, (q15_t)0xdbc1, (q15_t)0x74b8, (q15_t)0xdbb6, (q15_t)0x74b1, (q15_t)0xdbac, + (q15_t)0x74aa, (q15_t)0xdba2, (q15_t)0x74a2, (q15_t)0xdb97, (q15_t)0x749b, (q15_t)0xdb8d, (q15_t)0x7494, (q15_t)0xdb83, + (q15_t)0x748d, (q15_t)0xdb78, (q15_t)0x7486, (q15_t)0xdb6e, (q15_t)0x747f, (q15_t)0xdb64, (q15_t)0x7477, (q15_t)0xdb59, + (q15_t)0x7470, (q15_t)0xdb4f, (q15_t)0x7469, (q15_t)0xdb45, (q15_t)0x7462, (q15_t)0xdb3b, (q15_t)0x745b, (q15_t)0xdb30, + (q15_t)0x7453, (q15_t)0xdb26, (q15_t)0x744c, (q15_t)0xdb1c, (q15_t)0x7445, (q15_t)0xdb11, (q15_t)0x743e, (q15_t)0xdb07, + (q15_t)0x7436, (q15_t)0xdafd, (q15_t)0x742f, (q15_t)0xdaf3, (q15_t)0x7428, (q15_t)0xdae8, (q15_t)0x7420, (q15_t)0xdade, + (q15_t)0x7419, (q15_t)0xdad4, (q15_t)0x7412, (q15_t)0xdaca, (q15_t)0x740b, (q15_t)0xdabf, (q15_t)0x7403, (q15_t)0xdab5, + (q15_t)0x73fc, (q15_t)0xdaab, (q15_t)0x73f5, (q15_t)0xdaa1, (q15_t)0x73ed, (q15_t)0xda97, (q15_t)0x73e6, (q15_t)0xda8c, + (q15_t)0x73df, (q15_t)0xda82, (q15_t)0x73d7, (q15_t)0xda78, (q15_t)0x73d0, (q15_t)0xda6e, (q15_t)0x73c8, (q15_t)0xda64, + (q15_t)0x73c1, (q15_t)0xda5a, (q15_t)0x73ba, (q15_t)0xda4f, (q15_t)0x73b2, (q15_t)0xda45, (q15_t)0x73ab, (q15_t)0xda3b, + (q15_t)0x73a3, (q15_t)0xda31, (q15_t)0x739c, (q15_t)0xda27, (q15_t)0x7395, (q15_t)0xda1d, (q15_t)0x738d, (q15_t)0xda13, + (q15_t)0x7386, (q15_t)0xda08, (q15_t)0x737e, (q15_t)0xd9fe, (q15_t)0x7377, (q15_t)0xd9f4, (q15_t)0x736f, (q15_t)0xd9ea, + (q15_t)0x7368, (q15_t)0xd9e0, (q15_t)0x7360, (q15_t)0xd9d6, (q15_t)0x7359, (q15_t)0xd9cc, (q15_t)0x7351, (q15_t)0xd9c2, + (q15_t)0x734a, (q15_t)0xd9b8, (q15_t)0x7342, (q15_t)0xd9ae, (q15_t)0x733b, (q15_t)0xd9a4, (q15_t)0x7333, (q15_t)0xd99a, + (q15_t)0x732c, (q15_t)0xd98f, (q15_t)0x7324, (q15_t)0xd985, (q15_t)0x731d, (q15_t)0xd97b, (q15_t)0x7315, (q15_t)0xd971, + (q15_t)0x730d, (q15_t)0xd967, (q15_t)0x7306, (q15_t)0xd95d, (q15_t)0x72fe, (q15_t)0xd953, (q15_t)0x72f7, (q15_t)0xd949, + (q15_t)0x72ef, (q15_t)0xd93f, (q15_t)0x72e7, (q15_t)0xd935, (q15_t)0x72e0, (q15_t)0xd92b, (q15_t)0x72d8, (q15_t)0xd921, + (q15_t)0x72d0, (q15_t)0xd917, (q15_t)0x72c9, (q15_t)0xd90d, (q15_t)0x72c1, (q15_t)0xd903, (q15_t)0x72ba, (q15_t)0xd8f9, + (q15_t)0x72b2, (q15_t)0xd8ef, (q15_t)0x72aa, (q15_t)0xd8e6, (q15_t)0x72a3, (q15_t)0xd8dc, (q15_t)0x729b, (q15_t)0xd8d2, + (q15_t)0x7293, (q15_t)0xd8c8, (q15_t)0x728b, (q15_t)0xd8be, (q15_t)0x7284, (q15_t)0xd8b4, (q15_t)0x727c, (q15_t)0xd8aa, + (q15_t)0x7274, (q15_t)0xd8a0, (q15_t)0x726d, (q15_t)0xd896, (q15_t)0x7265, (q15_t)0xd88c, (q15_t)0x725d, (q15_t)0xd882, + (q15_t)0x7255, (q15_t)0xd878, (q15_t)0x724e, (q15_t)0xd86f, (q15_t)0x7246, (q15_t)0xd865, (q15_t)0x723e, (q15_t)0xd85b, + (q15_t)0x7236, (q15_t)0xd851, (q15_t)0x722e, (q15_t)0xd847, (q15_t)0x7227, (q15_t)0xd83d, (q15_t)0x721f, (q15_t)0xd833, + (q15_t)0x7217, (q15_t)0xd82a, (q15_t)0x720f, (q15_t)0xd820, (q15_t)0x7207, (q15_t)0xd816, (q15_t)0x71ff, (q15_t)0xd80c, + (q15_t)0x71f8, (q15_t)0xd802, (q15_t)0x71f0, (q15_t)0xd7f8, (q15_t)0x71e8, (q15_t)0xd7ef, (q15_t)0x71e0, (q15_t)0xd7e5, + (q15_t)0x71d8, (q15_t)0xd7db, (q15_t)0x71d0, (q15_t)0xd7d1, (q15_t)0x71c8, (q15_t)0xd7c8, (q15_t)0x71c0, (q15_t)0xd7be, + (q15_t)0x71b9, (q15_t)0xd7b4, (q15_t)0x71b1, (q15_t)0xd7aa, (q15_t)0x71a9, (q15_t)0xd7a0, (q15_t)0x71a1, (q15_t)0xd797, + (q15_t)0x7199, (q15_t)0xd78d, (q15_t)0x7191, (q15_t)0xd783, (q15_t)0x7189, (q15_t)0xd77a, (q15_t)0x7181, (q15_t)0xd770, + (q15_t)0x7179, (q15_t)0xd766, (q15_t)0x7171, (q15_t)0xd75c, (q15_t)0x7169, (q15_t)0xd753, (q15_t)0x7161, (q15_t)0xd749, + (q15_t)0x7159, (q15_t)0xd73f, (q15_t)0x7151, (q15_t)0xd736, (q15_t)0x7149, (q15_t)0xd72c, (q15_t)0x7141, (q15_t)0xd722, + (q15_t)0x7139, (q15_t)0xd719, (q15_t)0x7131, (q15_t)0xd70f, (q15_t)0x7129, (q15_t)0xd705, (q15_t)0x7121, (q15_t)0xd6fc, + (q15_t)0x7119, (q15_t)0xd6f2, (q15_t)0x7111, (q15_t)0xd6e8, (q15_t)0x7109, (q15_t)0xd6df, (q15_t)0x7101, (q15_t)0xd6d5, + (q15_t)0x70f9, (q15_t)0xd6cb, (q15_t)0x70f0, (q15_t)0xd6c2, (q15_t)0x70e8, (q15_t)0xd6b8, (q15_t)0x70e0, (q15_t)0xd6af, + (q15_t)0x70d8, (q15_t)0xd6a5, (q15_t)0x70d0, (q15_t)0xd69b, (q15_t)0x70c8, (q15_t)0xd692, (q15_t)0x70c0, (q15_t)0xd688, + (q15_t)0x70b8, (q15_t)0xd67f, (q15_t)0x70af, (q15_t)0xd675, (q15_t)0x70a7, (q15_t)0xd66c, (q15_t)0x709f, (q15_t)0xd662, + (q15_t)0x7097, (q15_t)0xd659, (q15_t)0x708f, (q15_t)0xd64f, (q15_t)0x7087, (q15_t)0xd645, (q15_t)0x707e, (q15_t)0xd63c, + (q15_t)0x7076, (q15_t)0xd632, (q15_t)0x706e, (q15_t)0xd629, (q15_t)0x7066, (q15_t)0xd61f, (q15_t)0x705d, (q15_t)0xd616, + (q15_t)0x7055, (q15_t)0xd60c, (q15_t)0x704d, (q15_t)0xd603, (q15_t)0x7045, (q15_t)0xd5f9, (q15_t)0x703c, (q15_t)0xd5f0, + (q15_t)0x7034, (q15_t)0xd5e6, (q15_t)0x702c, (q15_t)0xd5dd, (q15_t)0x7024, (q15_t)0xd5d4, (q15_t)0x701b, (q15_t)0xd5ca, + (q15_t)0x7013, (q15_t)0xd5c1, (q15_t)0x700b, (q15_t)0xd5b7, (q15_t)0x7002, (q15_t)0xd5ae, (q15_t)0x6ffa, (q15_t)0xd5a4, + (q15_t)0x6ff2, (q15_t)0xd59b, (q15_t)0x6fea, (q15_t)0xd592, (q15_t)0x6fe1, (q15_t)0xd588, (q15_t)0x6fd9, (q15_t)0xd57f, + (q15_t)0x6fd0, (q15_t)0xd575, (q15_t)0x6fc8, (q15_t)0xd56c, (q15_t)0x6fc0, (q15_t)0xd563, (q15_t)0x6fb7, (q15_t)0xd559, + (q15_t)0x6faf, (q15_t)0xd550, (q15_t)0x6fa7, (q15_t)0xd547, (q15_t)0x6f9e, (q15_t)0xd53d, (q15_t)0x6f96, (q15_t)0xd534, + (q15_t)0x6f8d, (q15_t)0xd52a, (q15_t)0x6f85, (q15_t)0xd521, (q15_t)0x6f7d, (q15_t)0xd518, (q15_t)0x6f74, (q15_t)0xd50e, + (q15_t)0x6f6c, (q15_t)0xd505, (q15_t)0x6f63, (q15_t)0xd4fc, (q15_t)0x6f5b, (q15_t)0xd4f3, (q15_t)0x6f52, (q15_t)0xd4e9, + (q15_t)0x6f4a, (q15_t)0xd4e0, (q15_t)0x6f41, (q15_t)0xd4d7, (q15_t)0x6f39, (q15_t)0xd4cd, (q15_t)0x6f30, (q15_t)0xd4c4, + (q15_t)0x6f28, (q15_t)0xd4bb, (q15_t)0x6f20, (q15_t)0xd4b2, (q15_t)0x6f17, (q15_t)0xd4a8, (q15_t)0x6f0e, (q15_t)0xd49f, + (q15_t)0x6f06, (q15_t)0xd496, (q15_t)0x6efd, (q15_t)0xd48d, (q15_t)0x6ef5, (q15_t)0xd483, (q15_t)0x6eec, (q15_t)0xd47a, + (q15_t)0x6ee4, (q15_t)0xd471, (q15_t)0x6edb, (q15_t)0xd468, (q15_t)0x6ed3, (q15_t)0xd45f, (q15_t)0x6eca, (q15_t)0xd455, + (q15_t)0x6ec2, (q15_t)0xd44c, (q15_t)0x6eb9, (q15_t)0xd443, (q15_t)0x6eb0, (q15_t)0xd43a, (q15_t)0x6ea8, (q15_t)0xd431, + (q15_t)0x6e9f, (q15_t)0xd428, (q15_t)0x6e97, (q15_t)0xd41e, (q15_t)0x6e8e, (q15_t)0xd415, (q15_t)0x6e85, (q15_t)0xd40c, + (q15_t)0x6e7d, (q15_t)0xd403, (q15_t)0x6e74, (q15_t)0xd3fa, (q15_t)0x6e6b, (q15_t)0xd3f1, (q15_t)0x6e63, (q15_t)0xd3e8, + (q15_t)0x6e5a, (q15_t)0xd3df, (q15_t)0x6e51, (q15_t)0xd3d5, (q15_t)0x6e49, (q15_t)0xd3cc, (q15_t)0x6e40, (q15_t)0xd3c3, + (q15_t)0x6e37, (q15_t)0xd3ba, (q15_t)0x6e2f, (q15_t)0xd3b1, (q15_t)0x6e26, (q15_t)0xd3a8, (q15_t)0x6e1d, (q15_t)0xd39f, + (q15_t)0x6e15, (q15_t)0xd396, (q15_t)0x6e0c, (q15_t)0xd38d, (q15_t)0x6e03, (q15_t)0xd384, (q15_t)0x6dfa, (q15_t)0xd37b, + (q15_t)0x6df2, (q15_t)0xd372, (q15_t)0x6de9, (q15_t)0xd369, (q15_t)0x6de0, (q15_t)0xd360, (q15_t)0x6dd7, (q15_t)0xd357, + (q15_t)0x6dcf, (q15_t)0xd34e, (q15_t)0x6dc6, (q15_t)0xd345, (q15_t)0x6dbd, (q15_t)0xd33c, (q15_t)0x6db4, (q15_t)0xd333, + (q15_t)0x6dab, (q15_t)0xd32a, (q15_t)0x6da3, (q15_t)0xd321, (q15_t)0x6d9a, (q15_t)0xd318, (q15_t)0x6d91, (q15_t)0xd30f, + (q15_t)0x6d88, (q15_t)0xd306, (q15_t)0x6d7f, (q15_t)0xd2fd, (q15_t)0x6d76, (q15_t)0xd2f4, (q15_t)0x6d6e, (q15_t)0xd2eb, + (q15_t)0x6d65, (q15_t)0xd2e2, (q15_t)0x6d5c, (q15_t)0xd2d9, (q15_t)0x6d53, (q15_t)0xd2d1, (q15_t)0x6d4a, (q15_t)0xd2c8, + (q15_t)0x6d41, (q15_t)0xd2bf, (q15_t)0x6d38, (q15_t)0xd2b6, (q15_t)0x6d2f, (q15_t)0xd2ad, (q15_t)0x6d27, (q15_t)0xd2a4, + (q15_t)0x6d1e, (q15_t)0xd29b, (q15_t)0x6d15, (q15_t)0xd292, (q15_t)0x6d0c, (q15_t)0xd28a, (q15_t)0x6d03, (q15_t)0xd281, + (q15_t)0x6cfa, (q15_t)0xd278, (q15_t)0x6cf1, (q15_t)0xd26f, (q15_t)0x6ce8, (q15_t)0xd266, (q15_t)0x6cdf, (q15_t)0xd25d, + (q15_t)0x6cd6, (q15_t)0xd255, (q15_t)0x6ccd, (q15_t)0xd24c, (q15_t)0x6cc4, (q15_t)0xd243, (q15_t)0x6cbb, (q15_t)0xd23a, + (q15_t)0x6cb2, (q15_t)0xd231, (q15_t)0x6ca9, (q15_t)0xd229, (q15_t)0x6ca0, (q15_t)0xd220, (q15_t)0x6c97, (q15_t)0xd217, + (q15_t)0x6c8e, (q15_t)0xd20e, (q15_t)0x6c85, (q15_t)0xd206, (q15_t)0x6c7c, (q15_t)0xd1fd, (q15_t)0x6c73, (q15_t)0xd1f4, + (q15_t)0x6c6a, (q15_t)0xd1eb, (q15_t)0x6c61, (q15_t)0xd1e3, (q15_t)0x6c58, (q15_t)0xd1da, (q15_t)0x6c4f, (q15_t)0xd1d1, + (q15_t)0x6c46, (q15_t)0xd1c9, (q15_t)0x6c3d, (q15_t)0xd1c0, (q15_t)0x6c34, (q15_t)0xd1b7, (q15_t)0x6c2b, (q15_t)0xd1af, + (q15_t)0x6c21, (q15_t)0xd1a6, (q15_t)0x6c18, (q15_t)0xd19d, (q15_t)0x6c0f, (q15_t)0xd195, (q15_t)0x6c06, (q15_t)0xd18c, + (q15_t)0x6bfd, (q15_t)0xd183, (q15_t)0x6bf4, (q15_t)0xd17b, (q15_t)0x6beb, (q15_t)0xd172, (q15_t)0x6be2, (q15_t)0xd169, + (q15_t)0x6bd8, (q15_t)0xd161, (q15_t)0x6bcf, (q15_t)0xd158, (q15_t)0x6bc6, (q15_t)0xd150, (q15_t)0x6bbd, (q15_t)0xd147, + (q15_t)0x6bb4, (q15_t)0xd13e, (q15_t)0x6bab, (q15_t)0xd136, (q15_t)0x6ba1, (q15_t)0xd12d, (q15_t)0x6b98, (q15_t)0xd125, + (q15_t)0x6b8f, (q15_t)0xd11c, (q15_t)0x6b86, (q15_t)0xd114, (q15_t)0x6b7d, (q15_t)0xd10b, (q15_t)0x6b73, (q15_t)0xd103, + (q15_t)0x6b6a, (q15_t)0xd0fa, (q15_t)0x6b61, (q15_t)0xd0f2, (q15_t)0x6b58, (q15_t)0xd0e9, (q15_t)0x6b4e, (q15_t)0xd0e0, + (q15_t)0x6b45, (q15_t)0xd0d8, (q15_t)0x6b3c, (q15_t)0xd0d0, (q15_t)0x6b33, (q15_t)0xd0c7, (q15_t)0x6b29, (q15_t)0xd0bf, + (q15_t)0x6b20, (q15_t)0xd0b6, (q15_t)0x6b17, (q15_t)0xd0ae, (q15_t)0x6b0d, (q15_t)0xd0a5, (q15_t)0x6b04, (q15_t)0xd09d, + (q15_t)0x6afb, (q15_t)0xd094, (q15_t)0x6af2, (q15_t)0xd08c, (q15_t)0x6ae8, (q15_t)0xd083, (q15_t)0x6adf, (q15_t)0xd07b, + (q15_t)0x6ad6, (q15_t)0xd073, (q15_t)0x6acc, (q15_t)0xd06a, (q15_t)0x6ac3, (q15_t)0xd062, (q15_t)0x6ab9, (q15_t)0xd059, + (q15_t)0x6ab0, (q15_t)0xd051, (q15_t)0x6aa7, (q15_t)0xd049, (q15_t)0x6a9d, (q15_t)0xd040, (q15_t)0x6a94, (q15_t)0xd038, + (q15_t)0x6a8b, (q15_t)0xd030, (q15_t)0x6a81, (q15_t)0xd027, (q15_t)0x6a78, (q15_t)0xd01f, (q15_t)0x6a6e, (q15_t)0xd016, + (q15_t)0x6a65, (q15_t)0xd00e, (q15_t)0x6a5c, (q15_t)0xd006, (q15_t)0x6a52, (q15_t)0xcffe, (q15_t)0x6a49, (q15_t)0xcff5, + (q15_t)0x6a3f, (q15_t)0xcfed, (q15_t)0x6a36, (q15_t)0xcfe5, (q15_t)0x6a2c, (q15_t)0xcfdc, (q15_t)0x6a23, (q15_t)0xcfd4, + (q15_t)0x6a1a, (q15_t)0xcfcc, (q15_t)0x6a10, (q15_t)0xcfc4, (q15_t)0x6a07, (q15_t)0xcfbb, (q15_t)0x69fd, (q15_t)0xcfb3, + (q15_t)0x69f4, (q15_t)0xcfab, (q15_t)0x69ea, (q15_t)0xcfa3, (q15_t)0x69e1, (q15_t)0xcf9a, (q15_t)0x69d7, (q15_t)0xcf92, + (q15_t)0x69ce, (q15_t)0xcf8a, (q15_t)0x69c4, (q15_t)0xcf82, (q15_t)0x69bb, (q15_t)0xcf79, (q15_t)0x69b1, (q15_t)0xcf71, + (q15_t)0x69a7, (q15_t)0xcf69, (q15_t)0x699e, (q15_t)0xcf61, (q15_t)0x6994, (q15_t)0xcf59, (q15_t)0x698b, (q15_t)0xcf51, + (q15_t)0x6981, (q15_t)0xcf48, (q15_t)0x6978, (q15_t)0xcf40, (q15_t)0x696e, (q15_t)0xcf38, (q15_t)0x6965, (q15_t)0xcf30, + (q15_t)0x695b, (q15_t)0xcf28, (q15_t)0x6951, (q15_t)0xcf20, (q15_t)0x6948, (q15_t)0xcf18, (q15_t)0x693e, (q15_t)0xcf10, + (q15_t)0x6935, (q15_t)0xcf07, (q15_t)0x692b, (q15_t)0xceff, (q15_t)0x6921, (q15_t)0xcef7, (q15_t)0x6918, (q15_t)0xceef, + (q15_t)0x690e, (q15_t)0xcee7, (q15_t)0x6904, (q15_t)0xcedf, (q15_t)0x68fb, (q15_t)0xced7, (q15_t)0x68f1, (q15_t)0xcecf, + (q15_t)0x68e7, (q15_t)0xcec7, (q15_t)0x68de, (q15_t)0xcebf, (q15_t)0x68d4, (q15_t)0xceb7, (q15_t)0x68ca, (q15_t)0xceaf, + (q15_t)0x68c1, (q15_t)0xcea7, (q15_t)0x68b7, (q15_t)0xce9f, (q15_t)0x68ad, (q15_t)0xce97, (q15_t)0x68a4, (q15_t)0xce8f, + (q15_t)0x689a, (q15_t)0xce87, (q15_t)0x6890, (q15_t)0xce7f, (q15_t)0x6886, (q15_t)0xce77, (q15_t)0x687d, (q15_t)0xce6f, + (q15_t)0x6873, (q15_t)0xce67, (q15_t)0x6869, (q15_t)0xce5f, (q15_t)0x6860, (q15_t)0xce57, (q15_t)0x6856, (q15_t)0xce4f, + (q15_t)0x684c, (q15_t)0xce47, (q15_t)0x6842, (q15_t)0xce40, (q15_t)0x6838, (q15_t)0xce38, (q15_t)0x682f, (q15_t)0xce30, + (q15_t)0x6825, (q15_t)0xce28, (q15_t)0x681b, (q15_t)0xce20, (q15_t)0x6811, (q15_t)0xce18, (q15_t)0x6808, (q15_t)0xce10, + (q15_t)0x67fe, (q15_t)0xce08, (q15_t)0x67f4, (q15_t)0xce01, (q15_t)0x67ea, (q15_t)0xcdf9, (q15_t)0x67e0, (q15_t)0xcdf1, + (q15_t)0x67d6, (q15_t)0xcde9, (q15_t)0x67cd, (q15_t)0xcde1, (q15_t)0x67c3, (q15_t)0xcdd9, (q15_t)0x67b9, (q15_t)0xcdd2, + (q15_t)0x67af, (q15_t)0xcdca, (q15_t)0x67a5, (q15_t)0xcdc2, (q15_t)0x679b, (q15_t)0xcdba, (q15_t)0x6791, (q15_t)0xcdb2, + (q15_t)0x6788, (q15_t)0xcdab, (q15_t)0x677e, (q15_t)0xcda3, (q15_t)0x6774, (q15_t)0xcd9b, (q15_t)0x676a, (q15_t)0xcd93, + (q15_t)0x6760, (q15_t)0xcd8c, (q15_t)0x6756, (q15_t)0xcd84, (q15_t)0x674c, (q15_t)0xcd7c, (q15_t)0x6742, (q15_t)0xcd75, + (q15_t)0x6738, (q15_t)0xcd6d, (q15_t)0x672e, (q15_t)0xcd65, (q15_t)0x6724, (q15_t)0xcd5d, (q15_t)0x671a, (q15_t)0xcd56, + (q15_t)0x6711, (q15_t)0xcd4e, (q15_t)0x6707, (q15_t)0xcd46, (q15_t)0x66fd, (q15_t)0xcd3f, (q15_t)0x66f3, (q15_t)0xcd37, + (q15_t)0x66e9, (q15_t)0xcd30, (q15_t)0x66df, (q15_t)0xcd28, (q15_t)0x66d5, (q15_t)0xcd20, (q15_t)0x66cb, (q15_t)0xcd19, + (q15_t)0x66c1, (q15_t)0xcd11, (q15_t)0x66b7, (q15_t)0xcd09, (q15_t)0x66ad, (q15_t)0xcd02, (q15_t)0x66a3, (q15_t)0xccfa, + (q15_t)0x6699, (q15_t)0xccf3, (q15_t)0x668f, (q15_t)0xcceb, (q15_t)0x6685, (q15_t)0xcce3, (q15_t)0x667b, (q15_t)0xccdc, + (q15_t)0x6671, (q15_t)0xccd4, (q15_t)0x6666, (q15_t)0xcccd, (q15_t)0x665c, (q15_t)0xccc5, (q15_t)0x6652, (q15_t)0xccbe, + (q15_t)0x6648, (q15_t)0xccb6, (q15_t)0x663e, (q15_t)0xccaf, (q15_t)0x6634, (q15_t)0xcca7, (q15_t)0x662a, (q15_t)0xcca0, + (q15_t)0x6620, (q15_t)0xcc98, (q15_t)0x6616, (q15_t)0xcc91, (q15_t)0x660c, (q15_t)0xcc89, (q15_t)0x6602, (q15_t)0xcc82, + (q15_t)0x65f8, (q15_t)0xcc7a, (q15_t)0x65ed, (q15_t)0xcc73, (q15_t)0x65e3, (q15_t)0xcc6b, (q15_t)0x65d9, (q15_t)0xcc64, + (q15_t)0x65cf, (q15_t)0xcc5d, (q15_t)0x65c5, (q15_t)0xcc55, (q15_t)0x65bb, (q15_t)0xcc4e, (q15_t)0x65b1, (q15_t)0xcc46, + (q15_t)0x65a6, (q15_t)0xcc3f, (q15_t)0x659c, (q15_t)0xcc38, (q15_t)0x6592, (q15_t)0xcc30, (q15_t)0x6588, (q15_t)0xcc29, + (q15_t)0x657e, (q15_t)0xcc21, (q15_t)0x6574, (q15_t)0xcc1a, (q15_t)0x6569, (q15_t)0xcc13, (q15_t)0x655f, (q15_t)0xcc0b, + (q15_t)0x6555, (q15_t)0xcc04, (q15_t)0x654b, (q15_t)0xcbfd, (q15_t)0x6541, (q15_t)0xcbf5, (q15_t)0x6536, (q15_t)0xcbee, + (q15_t)0x652c, (q15_t)0xcbe7, (q15_t)0x6522, (q15_t)0xcbe0, (q15_t)0x6518, (q15_t)0xcbd8, (q15_t)0x650d, (q15_t)0xcbd1, + (q15_t)0x6503, (q15_t)0xcbca, (q15_t)0x64f9, (q15_t)0xcbc2, (q15_t)0x64ef, (q15_t)0xcbbb, (q15_t)0x64e4, (q15_t)0xcbb4, + (q15_t)0x64da, (q15_t)0xcbad, (q15_t)0x64d0, (q15_t)0xcba5, (q15_t)0x64c5, (q15_t)0xcb9e, (q15_t)0x64bb, (q15_t)0xcb97, + (q15_t)0x64b1, (q15_t)0xcb90, (q15_t)0x64a7, (q15_t)0xcb89, (q15_t)0x649c, (q15_t)0xcb81, (q15_t)0x6492, (q15_t)0xcb7a, + (q15_t)0x6488, (q15_t)0xcb73, (q15_t)0x647d, (q15_t)0xcb6c, (q15_t)0x6473, (q15_t)0xcb65, (q15_t)0x6469, (q15_t)0xcb5e, + (q15_t)0x645e, (q15_t)0xcb56, (q15_t)0x6454, (q15_t)0xcb4f, (q15_t)0x644a, (q15_t)0xcb48, (q15_t)0x643f, (q15_t)0xcb41, + (q15_t)0x6435, (q15_t)0xcb3a, (q15_t)0x642b, (q15_t)0xcb33, (q15_t)0x6420, (q15_t)0xcb2c, (q15_t)0x6416, (q15_t)0xcb25, + (q15_t)0x640b, (q15_t)0xcb1e, (q15_t)0x6401, (q15_t)0xcb16, (q15_t)0x63f7, (q15_t)0xcb0f, (q15_t)0x63ec, (q15_t)0xcb08, + (q15_t)0x63e2, (q15_t)0xcb01, (q15_t)0x63d7, (q15_t)0xcafa, (q15_t)0x63cd, (q15_t)0xcaf3, (q15_t)0x63c3, (q15_t)0xcaec, + (q15_t)0x63b8, (q15_t)0xcae5, (q15_t)0x63ae, (q15_t)0xcade, (q15_t)0x63a3, (q15_t)0xcad7, (q15_t)0x6399, (q15_t)0xcad0, + (q15_t)0x638e, (q15_t)0xcac9, (q15_t)0x6384, (q15_t)0xcac2, (q15_t)0x637a, (q15_t)0xcabb, (q15_t)0x636f, (q15_t)0xcab4, + (q15_t)0x6365, (q15_t)0xcaad, (q15_t)0x635a, (q15_t)0xcaa6, (q15_t)0x6350, (q15_t)0xca9f, (q15_t)0x6345, (q15_t)0xca99, + (q15_t)0x633b, (q15_t)0xca92, (q15_t)0x6330, (q15_t)0xca8b, (q15_t)0x6326, (q15_t)0xca84, (q15_t)0x631b, (q15_t)0xca7d, + (q15_t)0x6311, (q15_t)0xca76, (q15_t)0x6306, (q15_t)0xca6f, (q15_t)0x62fc, (q15_t)0xca68, (q15_t)0x62f1, (q15_t)0xca61, + (q15_t)0x62e7, (q15_t)0xca5b, (q15_t)0x62dc, (q15_t)0xca54, (q15_t)0x62d2, (q15_t)0xca4d, (q15_t)0x62c7, (q15_t)0xca46, + (q15_t)0x62bc, (q15_t)0xca3f, (q15_t)0x62b2, (q15_t)0xca38, (q15_t)0x62a7, (q15_t)0xca32, (q15_t)0x629d, (q15_t)0xca2b, + (q15_t)0x6292, (q15_t)0xca24, (q15_t)0x6288, (q15_t)0xca1d, (q15_t)0x627d, (q15_t)0xca16, (q15_t)0x6272, (q15_t)0xca10, + (q15_t)0x6268, (q15_t)0xca09, (q15_t)0x625d, (q15_t)0xca02, (q15_t)0x6253, (q15_t)0xc9fb, (q15_t)0x6248, (q15_t)0xc9f5, + (q15_t)0x623d, (q15_t)0xc9ee, (q15_t)0x6233, (q15_t)0xc9e7, (q15_t)0x6228, (q15_t)0xc9e0, (q15_t)0x621e, (q15_t)0xc9da, + (q15_t)0x6213, (q15_t)0xc9d3, (q15_t)0x6208, (q15_t)0xc9cc, (q15_t)0x61fe, (q15_t)0xc9c6, (q15_t)0x61f3, (q15_t)0xc9bf, + (q15_t)0x61e8, (q15_t)0xc9b8, (q15_t)0x61de, (q15_t)0xc9b2, (q15_t)0x61d3, (q15_t)0xc9ab, (q15_t)0x61c8, (q15_t)0xc9a4, + (q15_t)0x61be, (q15_t)0xc99e, (q15_t)0x61b3, (q15_t)0xc997, (q15_t)0x61a8, (q15_t)0xc991, (q15_t)0x619e, (q15_t)0xc98a, + (q15_t)0x6193, (q15_t)0xc983, (q15_t)0x6188, (q15_t)0xc97d, (q15_t)0x617d, (q15_t)0xc976, (q15_t)0x6173, (q15_t)0xc970, + (q15_t)0x6168, (q15_t)0xc969, (q15_t)0x615d, (q15_t)0xc963, (q15_t)0x6153, (q15_t)0xc95c, (q15_t)0x6148, (q15_t)0xc955, + (q15_t)0x613d, (q15_t)0xc94f, (q15_t)0x6132, (q15_t)0xc948, (q15_t)0x6128, (q15_t)0xc942, (q15_t)0x611d, (q15_t)0xc93b, + (q15_t)0x6112, (q15_t)0xc935, (q15_t)0x6107, (q15_t)0xc92e, (q15_t)0x60fd, (q15_t)0xc928, (q15_t)0x60f2, (q15_t)0xc921, + (q15_t)0x60e7, (q15_t)0xc91b, (q15_t)0x60dc, (q15_t)0xc915, (q15_t)0x60d1, (q15_t)0xc90e, (q15_t)0x60c7, (q15_t)0xc908, + (q15_t)0x60bc, (q15_t)0xc901, (q15_t)0x60b1, (q15_t)0xc8fb, (q15_t)0x60a6, (q15_t)0xc8f4, (q15_t)0x609b, (q15_t)0xc8ee, + (q15_t)0x6091, (q15_t)0xc8e8, (q15_t)0x6086, (q15_t)0xc8e1, (q15_t)0x607b, (q15_t)0xc8db, (q15_t)0x6070, (q15_t)0xc8d4, + (q15_t)0x6065, (q15_t)0xc8ce, (q15_t)0x605b, (q15_t)0xc8c8, (q15_t)0x6050, (q15_t)0xc8c1, (q15_t)0x6045, (q15_t)0xc8bb, + (q15_t)0x603a, (q15_t)0xc8b5, (q15_t)0x602f, (q15_t)0xc8ae, (q15_t)0x6024, (q15_t)0xc8a8, (q15_t)0x6019, (q15_t)0xc8a2, + (q15_t)0x600f, (q15_t)0xc89b, (q15_t)0x6004, (q15_t)0xc895, (q15_t)0x5ff9, (q15_t)0xc88f, (q15_t)0x5fee, (q15_t)0xc889, + (q15_t)0x5fe3, (q15_t)0xc882, (q15_t)0x5fd8, (q15_t)0xc87c, (q15_t)0x5fcd, (q15_t)0xc876, (q15_t)0x5fc2, (q15_t)0xc870, + (q15_t)0x5fb7, (q15_t)0xc869, (q15_t)0x5fac, (q15_t)0xc863, (q15_t)0x5fa2, (q15_t)0xc85d, (q15_t)0x5f97, (q15_t)0xc857, + (q15_t)0x5f8c, (q15_t)0xc850, (q15_t)0x5f81, (q15_t)0xc84a, (q15_t)0x5f76, (q15_t)0xc844, (q15_t)0x5f6b, (q15_t)0xc83e, + (q15_t)0x5f60, (q15_t)0xc838, (q15_t)0x5f55, (q15_t)0xc832, (q15_t)0x5f4a, (q15_t)0xc82b, (q15_t)0x5f3f, (q15_t)0xc825, + (q15_t)0x5f34, (q15_t)0xc81f, (q15_t)0x5f29, (q15_t)0xc819, (q15_t)0x5f1e, (q15_t)0xc813, (q15_t)0x5f13, (q15_t)0xc80d, + (q15_t)0x5f08, (q15_t)0xc807, (q15_t)0x5efd, (q15_t)0xc801, (q15_t)0x5ef2, (q15_t)0xc7fb, (q15_t)0x5ee7, (q15_t)0xc7f5, + (q15_t)0x5edc, (q15_t)0xc7ee, (q15_t)0x5ed1, (q15_t)0xc7e8, (q15_t)0x5ec6, (q15_t)0xc7e2, (q15_t)0x5ebb, (q15_t)0xc7dc, + (q15_t)0x5eb0, (q15_t)0xc7d6, (q15_t)0x5ea5, (q15_t)0xc7d0, (q15_t)0x5e9a, (q15_t)0xc7ca, (q15_t)0x5e8f, (q15_t)0xc7c4, + (q15_t)0x5e84, (q15_t)0xc7be, (q15_t)0x5e79, (q15_t)0xc7b8, (q15_t)0x5e6e, (q15_t)0xc7b2, (q15_t)0x5e63, (q15_t)0xc7ac, + (q15_t)0x5e58, (q15_t)0xc7a6, (q15_t)0x5e4d, (q15_t)0xc7a0, (q15_t)0x5e42, (q15_t)0xc79a, (q15_t)0x5e36, (q15_t)0xc795, + (q15_t)0x5e2b, (q15_t)0xc78f, (q15_t)0x5e20, (q15_t)0xc789, (q15_t)0x5e15, (q15_t)0xc783, (q15_t)0x5e0a, (q15_t)0xc77d, + (q15_t)0x5dff, (q15_t)0xc777, (q15_t)0x5df4, (q15_t)0xc771, (q15_t)0x5de9, (q15_t)0xc76b, (q15_t)0x5dde, (q15_t)0xc765, + (q15_t)0x5dd3, (q15_t)0xc75f, (q15_t)0x5dc7, (q15_t)0xc75a, (q15_t)0x5dbc, (q15_t)0xc754, (q15_t)0x5db1, (q15_t)0xc74e, + (q15_t)0x5da6, (q15_t)0xc748, (q15_t)0x5d9b, (q15_t)0xc742, (q15_t)0x5d90, (q15_t)0xc73d, (q15_t)0x5d85, (q15_t)0xc737, + (q15_t)0x5d79, (q15_t)0xc731, (q15_t)0x5d6e, (q15_t)0xc72b, (q15_t)0x5d63, (q15_t)0xc725, (q15_t)0x5d58, (q15_t)0xc720, + (q15_t)0x5d4d, (q15_t)0xc71a, (q15_t)0x5d42, (q15_t)0xc714, (q15_t)0x5d36, (q15_t)0xc70e, (q15_t)0x5d2b, (q15_t)0xc709, + (q15_t)0x5d20, (q15_t)0xc703, (q15_t)0x5d15, (q15_t)0xc6fd, (q15_t)0x5d0a, (q15_t)0xc6f7, (q15_t)0x5cff, (q15_t)0xc6f2, + (q15_t)0x5cf3, (q15_t)0xc6ec, (q15_t)0x5ce8, (q15_t)0xc6e6, (q15_t)0x5cdd, (q15_t)0xc6e1, (q15_t)0x5cd2, (q15_t)0xc6db, + (q15_t)0x5cc6, (q15_t)0xc6d5, (q15_t)0x5cbb, (q15_t)0xc6d0, (q15_t)0x5cb0, (q15_t)0xc6ca, (q15_t)0x5ca5, (q15_t)0xc6c5, + (q15_t)0x5c99, (q15_t)0xc6bf, (q15_t)0x5c8e, (q15_t)0xc6b9, (q15_t)0x5c83, (q15_t)0xc6b4, (q15_t)0x5c78, (q15_t)0xc6ae, + (q15_t)0x5c6c, (q15_t)0xc6a8, (q15_t)0x5c61, (q15_t)0xc6a3, (q15_t)0x5c56, (q15_t)0xc69d, (q15_t)0x5c4b, (q15_t)0xc698, + (q15_t)0x5c3f, (q15_t)0xc692, (q15_t)0x5c34, (q15_t)0xc68d, (q15_t)0x5c29, (q15_t)0xc687, (q15_t)0x5c1e, (q15_t)0xc682, + (q15_t)0x5c12, (q15_t)0xc67c, (q15_t)0x5c07, (q15_t)0xc677, (q15_t)0x5bfc, (q15_t)0xc671, (q15_t)0x5bf0, (q15_t)0xc66c, + (q15_t)0x5be5, (q15_t)0xc666, (q15_t)0x5bda, (q15_t)0xc661, (q15_t)0x5bce, (q15_t)0xc65b, (q15_t)0x5bc3, (q15_t)0xc656, + (q15_t)0x5bb8, (q15_t)0xc650, (q15_t)0x5bac, (q15_t)0xc64b, (q15_t)0x5ba1, (q15_t)0xc645, (q15_t)0x5b96, (q15_t)0xc640, + (q15_t)0x5b8a, (q15_t)0xc63b, (q15_t)0x5b7f, (q15_t)0xc635, (q15_t)0x5b74, (q15_t)0xc630, (q15_t)0x5b68, (q15_t)0xc62a, + (q15_t)0x5b5d, (q15_t)0xc625, (q15_t)0x5b52, (q15_t)0xc620, (q15_t)0x5b46, (q15_t)0xc61a, (q15_t)0x5b3b, (q15_t)0xc615, + (q15_t)0x5b30, (q15_t)0xc610, (q15_t)0x5b24, (q15_t)0xc60a, (q15_t)0x5b19, (q15_t)0xc605, (q15_t)0x5b0d, (q15_t)0xc600, + (q15_t)0x5b02, (q15_t)0xc5fa, (q15_t)0x5af7, (q15_t)0xc5f5, (q15_t)0x5aeb, (q15_t)0xc5f0, (q15_t)0x5ae0, (q15_t)0xc5ea, + (q15_t)0x5ad4, (q15_t)0xc5e5, (q15_t)0x5ac9, (q15_t)0xc5e0, (q15_t)0x5abe, (q15_t)0xc5db, (q15_t)0x5ab2, (q15_t)0xc5d5, + (q15_t)0x5aa7, (q15_t)0xc5d0, (q15_t)0x5a9b, (q15_t)0xc5cb, (q15_t)0x5a90, (q15_t)0xc5c6, (q15_t)0x5a84, (q15_t)0xc5c1, + (q15_t)0x5a79, (q15_t)0xc5bb, (q15_t)0x5a6e, (q15_t)0xc5b6, (q15_t)0x5a62, (q15_t)0xc5b1, (q15_t)0x5a57, (q15_t)0xc5ac, + (q15_t)0x5a4b, (q15_t)0xc5a7, (q15_t)0x5a40, (q15_t)0xc5a1, (q15_t)0x5a34, (q15_t)0xc59c, (q15_t)0x5a29, (q15_t)0xc597, + (q15_t)0x5a1d, (q15_t)0xc592, (q15_t)0x5a12, (q15_t)0xc58d, (q15_t)0x5a06, (q15_t)0xc588, (q15_t)0x59fb, (q15_t)0xc583, + (q15_t)0x59ef, (q15_t)0xc57e, (q15_t)0x59e4, (q15_t)0xc578, (q15_t)0x59d8, (q15_t)0xc573, (q15_t)0x59cd, (q15_t)0xc56e, + (q15_t)0x59c1, (q15_t)0xc569, (q15_t)0x59b6, (q15_t)0xc564, (q15_t)0x59aa, (q15_t)0xc55f, (q15_t)0x599f, (q15_t)0xc55a, + (q15_t)0x5993, (q15_t)0xc555, (q15_t)0x5988, (q15_t)0xc550, (q15_t)0x597c, (q15_t)0xc54b, (q15_t)0x5971, (q15_t)0xc546, + (q15_t)0x5965, (q15_t)0xc541, (q15_t)0x595a, (q15_t)0xc53c, (q15_t)0x594e, (q15_t)0xc537, (q15_t)0x5943, (q15_t)0xc532, + (q15_t)0x5937, (q15_t)0xc52d, (q15_t)0x592c, (q15_t)0xc528, (q15_t)0x5920, (q15_t)0xc523, (q15_t)0x5914, (q15_t)0xc51e, + (q15_t)0x5909, (q15_t)0xc51a, (q15_t)0x58fd, (q15_t)0xc515, (q15_t)0x58f2, (q15_t)0xc510, (q15_t)0x58e6, (q15_t)0xc50b, + (q15_t)0x58db, (q15_t)0xc506, (q15_t)0x58cf, (q15_t)0xc501, (q15_t)0x58c3, (q15_t)0xc4fc, (q15_t)0x58b8, (q15_t)0xc4f7, + (q15_t)0x58ac, (q15_t)0xc4f2, (q15_t)0x58a1, (q15_t)0xc4ee, (q15_t)0x5895, (q15_t)0xc4e9, (q15_t)0x5889, (q15_t)0xc4e4, + (q15_t)0x587e, (q15_t)0xc4df, (q15_t)0x5872, (q15_t)0xc4da, (q15_t)0x5867, (q15_t)0xc4d6, (q15_t)0x585b, (q15_t)0xc4d1, + (q15_t)0x584f, (q15_t)0xc4cc, (q15_t)0x5844, (q15_t)0xc4c7, (q15_t)0x5838, (q15_t)0xc4c2, (q15_t)0x582d, (q15_t)0xc4be, + (q15_t)0x5821, (q15_t)0xc4b9, (q15_t)0x5815, (q15_t)0xc4b4, (q15_t)0x580a, (q15_t)0xc4b0, (q15_t)0x57fe, (q15_t)0xc4ab, + (q15_t)0x57f2, (q15_t)0xc4a6, (q15_t)0x57e7, (q15_t)0xc4a1, (q15_t)0x57db, (q15_t)0xc49d, (q15_t)0x57cf, (q15_t)0xc498, + (q15_t)0x57c4, (q15_t)0xc493, (q15_t)0x57b8, (q15_t)0xc48f, (q15_t)0x57ac, (q15_t)0xc48a, (q15_t)0x57a1, (q15_t)0xc485, + (q15_t)0x5795, (q15_t)0xc481, (q15_t)0x5789, (q15_t)0xc47c, (q15_t)0x577e, (q15_t)0xc478, (q15_t)0x5772, (q15_t)0xc473, + (q15_t)0x5766, (q15_t)0xc46e, (q15_t)0x575b, (q15_t)0xc46a, (q15_t)0x574f, (q15_t)0xc465, (q15_t)0x5743, (q15_t)0xc461, + (q15_t)0x5737, (q15_t)0xc45c, (q15_t)0x572c, (q15_t)0xc457, (q15_t)0x5720, (q15_t)0xc453, (q15_t)0x5714, (q15_t)0xc44e, + (q15_t)0x5709, (q15_t)0xc44a, (q15_t)0x56fd, (q15_t)0xc445, (q15_t)0x56f1, (q15_t)0xc441, (q15_t)0x56e5, (q15_t)0xc43c, + (q15_t)0x56da, (q15_t)0xc438, (q15_t)0x56ce, (q15_t)0xc433, (q15_t)0x56c2, (q15_t)0xc42f, (q15_t)0x56b6, (q15_t)0xc42a, + (q15_t)0x56ab, (q15_t)0xc426, (q15_t)0x569f, (q15_t)0xc422, (q15_t)0x5693, (q15_t)0xc41d, (q15_t)0x5687, (q15_t)0xc419, + (q15_t)0x567c, (q15_t)0xc414, (q15_t)0x5670, (q15_t)0xc410, (q15_t)0x5664, (q15_t)0xc40b, (q15_t)0x5658, (q15_t)0xc407, + (q15_t)0x564c, (q15_t)0xc403, (q15_t)0x5641, (q15_t)0xc3fe, (q15_t)0x5635, (q15_t)0xc3fa, (q15_t)0x5629, (q15_t)0xc3f6, + (q15_t)0x561d, (q15_t)0xc3f1, (q15_t)0x5612, (q15_t)0xc3ed, (q15_t)0x5606, (q15_t)0xc3e9, (q15_t)0x55fa, (q15_t)0xc3e4, + (q15_t)0x55ee, (q15_t)0xc3e0, (q15_t)0x55e2, (q15_t)0xc3dc, (q15_t)0x55d7, (q15_t)0xc3d7, (q15_t)0x55cb, (q15_t)0xc3d3, + (q15_t)0x55bf, (q15_t)0xc3cf, (q15_t)0x55b3, (q15_t)0xc3ca, (q15_t)0x55a7, (q15_t)0xc3c6, (q15_t)0x559b, (q15_t)0xc3c2, + (q15_t)0x5590, (q15_t)0xc3be, (q15_t)0x5584, (q15_t)0xc3ba, (q15_t)0x5578, (q15_t)0xc3b5, (q15_t)0x556c, (q15_t)0xc3b1, + (q15_t)0x5560, (q15_t)0xc3ad, (q15_t)0x5554, (q15_t)0xc3a9, (q15_t)0x5549, (q15_t)0xc3a5, (q15_t)0x553d, (q15_t)0xc3a0, + (q15_t)0x5531, (q15_t)0xc39c, (q15_t)0x5525, (q15_t)0xc398, (q15_t)0x5519, (q15_t)0xc394, (q15_t)0x550d, (q15_t)0xc390, + (q15_t)0x5501, (q15_t)0xc38c, (q15_t)0x54f6, (q15_t)0xc387, (q15_t)0x54ea, (q15_t)0xc383, (q15_t)0x54de, (q15_t)0xc37f, + (q15_t)0x54d2, (q15_t)0xc37b, (q15_t)0x54c6, (q15_t)0xc377, (q15_t)0x54ba, (q15_t)0xc373, (q15_t)0x54ae, (q15_t)0xc36f, + (q15_t)0x54a2, (q15_t)0xc36b, (q15_t)0x5496, (q15_t)0xc367, (q15_t)0x548b, (q15_t)0xc363, (q15_t)0x547f, (q15_t)0xc35f, + (q15_t)0x5473, (q15_t)0xc35b, (q15_t)0x5467, (q15_t)0xc357, (q15_t)0x545b, (q15_t)0xc353, (q15_t)0x544f, (q15_t)0xc34f, + (q15_t)0x5443, (q15_t)0xc34b, (q15_t)0x5437, (q15_t)0xc347, (q15_t)0x542b, (q15_t)0xc343, (q15_t)0x541f, (q15_t)0xc33f, + (q15_t)0x5413, (q15_t)0xc33b, (q15_t)0x5407, (q15_t)0xc337, (q15_t)0x53fb, (q15_t)0xc333, (q15_t)0x53f0, (q15_t)0xc32f, + (q15_t)0x53e4, (q15_t)0xc32b, (q15_t)0x53d8, (q15_t)0xc327, (q15_t)0x53cc, (q15_t)0xc323, (q15_t)0x53c0, (q15_t)0xc320, + (q15_t)0x53b4, (q15_t)0xc31c, (q15_t)0x53a8, (q15_t)0xc318, (q15_t)0x539c, (q15_t)0xc314, (q15_t)0x5390, (q15_t)0xc310, + (q15_t)0x5384, (q15_t)0xc30c, (q15_t)0x5378, (q15_t)0xc308, (q15_t)0x536c, (q15_t)0xc305, (q15_t)0x5360, (q15_t)0xc301, + (q15_t)0x5354, (q15_t)0xc2fd, (q15_t)0x5348, (q15_t)0xc2f9, (q15_t)0x533c, (q15_t)0xc2f5, (q15_t)0x5330, (q15_t)0xc2f2, + (q15_t)0x5324, (q15_t)0xc2ee, (q15_t)0x5318, (q15_t)0xc2ea, (q15_t)0x530c, (q15_t)0xc2e6, (q15_t)0x5300, (q15_t)0xc2e3, + (q15_t)0x52f4, (q15_t)0xc2df, (q15_t)0x52e8, (q15_t)0xc2db, (q15_t)0x52dc, (q15_t)0xc2d8, (q15_t)0x52d0, (q15_t)0xc2d4, + (q15_t)0x52c4, (q15_t)0xc2d0, (q15_t)0x52b8, (q15_t)0xc2cc, (q15_t)0x52ac, (q15_t)0xc2c9, (q15_t)0x52a0, (q15_t)0xc2c5, + (q15_t)0x5294, (q15_t)0xc2c1, (q15_t)0x5288, (q15_t)0xc2be, (q15_t)0x527c, (q15_t)0xc2ba, (q15_t)0x5270, (q15_t)0xc2b7, + (q15_t)0x5264, (q15_t)0xc2b3, (q15_t)0x5258, (q15_t)0xc2af, (q15_t)0x524c, (q15_t)0xc2ac, (q15_t)0x5240, (q15_t)0xc2a8, + (q15_t)0x5234, (q15_t)0xc2a5, (q15_t)0x5228, (q15_t)0xc2a1, (q15_t)0x521c, (q15_t)0xc29d, (q15_t)0x5210, (q15_t)0xc29a, + (q15_t)0x5204, (q15_t)0xc296, (q15_t)0x51f7, (q15_t)0xc293, (q15_t)0x51eb, (q15_t)0xc28f, (q15_t)0x51df, (q15_t)0xc28c, + (q15_t)0x51d3, (q15_t)0xc288, (q15_t)0x51c7, (q15_t)0xc285, (q15_t)0x51bb, (q15_t)0xc281, (q15_t)0x51af, (q15_t)0xc27e, + (q15_t)0x51a3, (q15_t)0xc27a, (q15_t)0x5197, (q15_t)0xc277, (q15_t)0x518b, (q15_t)0xc273, (q15_t)0x517f, (q15_t)0xc270, + (q15_t)0x5173, (q15_t)0xc26d, (q15_t)0x5167, (q15_t)0xc269, (q15_t)0x515a, (q15_t)0xc266, (q15_t)0x514e, (q15_t)0xc262, + (q15_t)0x5142, (q15_t)0xc25f, (q15_t)0x5136, (q15_t)0xc25c, (q15_t)0x512a, (q15_t)0xc258, (q15_t)0x511e, (q15_t)0xc255, + (q15_t)0x5112, (q15_t)0xc251, (q15_t)0x5106, (q15_t)0xc24e, (q15_t)0x50fa, (q15_t)0xc24b, (q15_t)0x50ed, (q15_t)0xc247, + (q15_t)0x50e1, (q15_t)0xc244, (q15_t)0x50d5, (q15_t)0xc241, (q15_t)0x50c9, (q15_t)0xc23e, (q15_t)0x50bd, (q15_t)0xc23a, + (q15_t)0x50b1, (q15_t)0xc237, (q15_t)0x50a5, (q15_t)0xc234, (q15_t)0x5099, (q15_t)0xc230, (q15_t)0x508c, (q15_t)0xc22d, + (q15_t)0x5080, (q15_t)0xc22a, (q15_t)0x5074, (q15_t)0xc227, (q15_t)0x5068, (q15_t)0xc223, (q15_t)0x505c, (q15_t)0xc220, + (q15_t)0x5050, (q15_t)0xc21d, (q15_t)0x5044, (q15_t)0xc21a, (q15_t)0x5037, (q15_t)0xc217, (q15_t)0x502b, (q15_t)0xc213, + (q15_t)0x501f, (q15_t)0xc210, (q15_t)0x5013, (q15_t)0xc20d, (q15_t)0x5007, (q15_t)0xc20a, (q15_t)0x4ffb, (q15_t)0xc207, + (q15_t)0x4fee, (q15_t)0xc204, (q15_t)0x4fe2, (q15_t)0xc201, (q15_t)0x4fd6, (q15_t)0xc1fd, (q15_t)0x4fca, (q15_t)0xc1fa, + (q15_t)0x4fbe, (q15_t)0xc1f7, (q15_t)0x4fb2, (q15_t)0xc1f4, (q15_t)0x4fa5, (q15_t)0xc1f1, (q15_t)0x4f99, (q15_t)0xc1ee, + (q15_t)0x4f8d, (q15_t)0xc1eb, (q15_t)0x4f81, (q15_t)0xc1e8, (q15_t)0x4f75, (q15_t)0xc1e5, (q15_t)0x4f68, (q15_t)0xc1e2, + (q15_t)0x4f5c, (q15_t)0xc1df, (q15_t)0x4f50, (q15_t)0xc1dc, (q15_t)0x4f44, (q15_t)0xc1d9, (q15_t)0x4f38, (q15_t)0xc1d6, + (q15_t)0x4f2b, (q15_t)0xc1d3, (q15_t)0x4f1f, (q15_t)0xc1d0, (q15_t)0x4f13, (q15_t)0xc1cd, (q15_t)0x4f07, (q15_t)0xc1ca, + (q15_t)0x4efb, (q15_t)0xc1c7, (q15_t)0x4eee, (q15_t)0xc1c4, (q15_t)0x4ee2, (q15_t)0xc1c1, (q15_t)0x4ed6, (q15_t)0xc1be, + (q15_t)0x4eca, (q15_t)0xc1bb, (q15_t)0x4ebd, (q15_t)0xc1b8, (q15_t)0x4eb1, (q15_t)0xc1b6, (q15_t)0x4ea5, (q15_t)0xc1b3, + (q15_t)0x4e99, (q15_t)0xc1b0, (q15_t)0x4e8c, (q15_t)0xc1ad, (q15_t)0x4e80, (q15_t)0xc1aa, (q15_t)0x4e74, (q15_t)0xc1a7, + (q15_t)0x4e68, (q15_t)0xc1a4, (q15_t)0x4e5c, (q15_t)0xc1a2, (q15_t)0x4e4f, (q15_t)0xc19f, (q15_t)0x4e43, (q15_t)0xc19c, + (q15_t)0x4e37, (q15_t)0xc199, (q15_t)0x4e2b, (q15_t)0xc196, (q15_t)0x4e1e, (q15_t)0xc194, (q15_t)0x4e12, (q15_t)0xc191, + (q15_t)0x4e06, (q15_t)0xc18e, (q15_t)0x4df9, (q15_t)0xc18b, (q15_t)0x4ded, (q15_t)0xc189, (q15_t)0x4de1, (q15_t)0xc186, + (q15_t)0x4dd5, (q15_t)0xc183, (q15_t)0x4dc8, (q15_t)0xc180, (q15_t)0x4dbc, (q15_t)0xc17e, (q15_t)0x4db0, (q15_t)0xc17b, + (q15_t)0x4da4, (q15_t)0xc178, (q15_t)0x4d97, (q15_t)0xc176, (q15_t)0x4d8b, (q15_t)0xc173, (q15_t)0x4d7f, (q15_t)0xc170, + (q15_t)0x4d72, (q15_t)0xc16e, (q15_t)0x4d66, (q15_t)0xc16b, (q15_t)0x4d5a, (q15_t)0xc168, (q15_t)0x4d4e, (q15_t)0xc166, + (q15_t)0x4d41, (q15_t)0xc163, (q15_t)0x4d35, (q15_t)0xc161, (q15_t)0x4d29, (q15_t)0xc15e, (q15_t)0x4d1c, (q15_t)0xc15b, + (q15_t)0x4d10, (q15_t)0xc159, (q15_t)0x4d04, (q15_t)0xc156, (q15_t)0x4cf8, (q15_t)0xc154, (q15_t)0x4ceb, (q15_t)0xc151, + (q15_t)0x4cdf, (q15_t)0xc14f, (q15_t)0x4cd3, (q15_t)0xc14c, (q15_t)0x4cc6, (q15_t)0xc14a, (q15_t)0x4cba, (q15_t)0xc147, + (q15_t)0x4cae, (q15_t)0xc145, (q15_t)0x4ca1, (q15_t)0xc142, (q15_t)0x4c95, (q15_t)0xc140, (q15_t)0x4c89, (q15_t)0xc13d, + (q15_t)0x4c7c, (q15_t)0xc13b, (q15_t)0x4c70, (q15_t)0xc138, (q15_t)0x4c64, (q15_t)0xc136, (q15_t)0x4c57, (q15_t)0xc134, + (q15_t)0x4c4b, (q15_t)0xc131, (q15_t)0x4c3f, (q15_t)0xc12f, (q15_t)0x4c32, (q15_t)0xc12c, (q15_t)0x4c26, (q15_t)0xc12a, + (q15_t)0x4c1a, (q15_t)0xc128, (q15_t)0x4c0d, (q15_t)0xc125, (q15_t)0x4c01, (q15_t)0xc123, (q15_t)0x4bf5, (q15_t)0xc120, + (q15_t)0x4be8, (q15_t)0xc11e, (q15_t)0x4bdc, (q15_t)0xc11c, (q15_t)0x4bd0, (q15_t)0xc119, (q15_t)0x4bc3, (q15_t)0xc117, + (q15_t)0x4bb7, (q15_t)0xc115, (q15_t)0x4bab, (q15_t)0xc113, (q15_t)0x4b9e, (q15_t)0xc110, (q15_t)0x4b92, (q15_t)0xc10e, + (q15_t)0x4b85, (q15_t)0xc10c, (q15_t)0x4b79, (q15_t)0xc109, (q15_t)0x4b6d, (q15_t)0xc107, (q15_t)0x4b60, (q15_t)0xc105, + (q15_t)0x4b54, (q15_t)0xc103, (q15_t)0x4b48, (q15_t)0xc100, (q15_t)0x4b3b, (q15_t)0xc0fe, (q15_t)0x4b2f, (q15_t)0xc0fc, + (q15_t)0x4b23, (q15_t)0xc0fa, (q15_t)0x4b16, (q15_t)0xc0f8, (q15_t)0x4b0a, (q15_t)0xc0f6, (q15_t)0x4afd, (q15_t)0xc0f3, + (q15_t)0x4af1, (q15_t)0xc0f1, (q15_t)0x4ae5, (q15_t)0xc0ef, (q15_t)0x4ad8, (q15_t)0xc0ed, (q15_t)0x4acc, (q15_t)0xc0eb, + (q15_t)0x4ac0, (q15_t)0xc0e9, (q15_t)0x4ab3, (q15_t)0xc0e7, (q15_t)0x4aa7, (q15_t)0xc0e4, (q15_t)0x4a9a, (q15_t)0xc0e2, + (q15_t)0x4a8e, (q15_t)0xc0e0, (q15_t)0x4a82, (q15_t)0xc0de, (q15_t)0x4a75, (q15_t)0xc0dc, (q15_t)0x4a69, (q15_t)0xc0da, + (q15_t)0x4a5c, (q15_t)0xc0d8, (q15_t)0x4a50, (q15_t)0xc0d6, (q15_t)0x4a44, (q15_t)0xc0d4, (q15_t)0x4a37, (q15_t)0xc0d2, + (q15_t)0x4a2b, (q15_t)0xc0d0, (q15_t)0x4a1e, (q15_t)0xc0ce, (q15_t)0x4a12, (q15_t)0xc0cc, (q15_t)0x4a06, (q15_t)0xc0ca, + (q15_t)0x49f9, (q15_t)0xc0c8, (q15_t)0x49ed, (q15_t)0xc0c6, (q15_t)0x49e0, (q15_t)0xc0c4, (q15_t)0x49d4, (q15_t)0xc0c2, + (q15_t)0x49c7, (q15_t)0xc0c0, (q15_t)0x49bb, (q15_t)0xc0be, (q15_t)0x49af, (q15_t)0xc0bd, (q15_t)0x49a2, (q15_t)0xc0bb, + (q15_t)0x4996, (q15_t)0xc0b9, (q15_t)0x4989, (q15_t)0xc0b7, (q15_t)0x497d, (q15_t)0xc0b5, (q15_t)0x4970, (q15_t)0xc0b3, + (q15_t)0x4964, (q15_t)0xc0b1, (q15_t)0x4958, (q15_t)0xc0af, (q15_t)0x494b, (q15_t)0xc0ae, (q15_t)0x493f, (q15_t)0xc0ac, + (q15_t)0x4932, (q15_t)0xc0aa, (q15_t)0x4926, (q15_t)0xc0a8, (q15_t)0x4919, (q15_t)0xc0a6, (q15_t)0x490d, (q15_t)0xc0a5, + (q15_t)0x4901, (q15_t)0xc0a3, (q15_t)0x48f4, (q15_t)0xc0a1, (q15_t)0x48e8, (q15_t)0xc09f, (q15_t)0x48db, (q15_t)0xc09e, + (q15_t)0x48cf, (q15_t)0xc09c, (q15_t)0x48c2, (q15_t)0xc09a, (q15_t)0x48b6, (q15_t)0xc098, (q15_t)0x48a9, (q15_t)0xc097, + (q15_t)0x489d, (q15_t)0xc095, (q15_t)0x4891, (q15_t)0xc093, (q15_t)0x4884, (q15_t)0xc092, (q15_t)0x4878, (q15_t)0xc090, + (q15_t)0x486b, (q15_t)0xc08e, (q15_t)0x485f, (q15_t)0xc08d, (q15_t)0x4852, (q15_t)0xc08b, (q15_t)0x4846, (q15_t)0xc089, + (q15_t)0x4839, (q15_t)0xc088, (q15_t)0x482d, (q15_t)0xc086, (q15_t)0x4820, (q15_t)0xc085, (q15_t)0x4814, (q15_t)0xc083, + (q15_t)0x4807, (q15_t)0xc081, (q15_t)0x47fb, (q15_t)0xc080, (q15_t)0x47ef, (q15_t)0xc07e, (q15_t)0x47e2, (q15_t)0xc07d, + (q15_t)0x47d6, (q15_t)0xc07b, (q15_t)0x47c9, (q15_t)0xc07a, (q15_t)0x47bd, (q15_t)0xc078, (q15_t)0x47b0, (q15_t)0xc077, + (q15_t)0x47a4, (q15_t)0xc075, (q15_t)0x4797, (q15_t)0xc074, (q15_t)0x478b, (q15_t)0xc072, (q15_t)0x477e, (q15_t)0xc071, + (q15_t)0x4772, (q15_t)0xc06f, (q15_t)0x4765, (q15_t)0xc06e, (q15_t)0x4759, (q15_t)0xc06c, (q15_t)0x474c, (q15_t)0xc06b, + (q15_t)0x4740, (q15_t)0xc069, (q15_t)0x4733, (q15_t)0xc068, (q15_t)0x4727, (q15_t)0xc067, (q15_t)0x471a, (q15_t)0xc065, + (q15_t)0x470e, (q15_t)0xc064, (q15_t)0x4701, (q15_t)0xc062, (q15_t)0x46f5, (q15_t)0xc061, (q15_t)0x46e8, (q15_t)0xc060, + (q15_t)0x46dc, (q15_t)0xc05e, (q15_t)0x46cf, (q15_t)0xc05d, (q15_t)0x46c3, (q15_t)0xc05c, (q15_t)0x46b6, (q15_t)0xc05a, + (q15_t)0x46aa, (q15_t)0xc059, (q15_t)0x469d, (q15_t)0xc058, (q15_t)0x4691, (q15_t)0xc056, (q15_t)0x4684, (q15_t)0xc055, + (q15_t)0x4678, (q15_t)0xc054, (q15_t)0x466b, (q15_t)0xc053, (q15_t)0x465f, (q15_t)0xc051, (q15_t)0x4652, (q15_t)0xc050, + (q15_t)0x4646, (q15_t)0xc04f, (q15_t)0x4639, (q15_t)0xc04e, (q15_t)0x462d, (q15_t)0xc04c, (q15_t)0x4620, (q15_t)0xc04b, + (q15_t)0x4614, (q15_t)0xc04a, (q15_t)0x4607, (q15_t)0xc049, (q15_t)0x45fb, (q15_t)0xc048, (q15_t)0x45ee, (q15_t)0xc047, + (q15_t)0x45e2, (q15_t)0xc045, (q15_t)0x45d5, (q15_t)0xc044, (q15_t)0x45c9, (q15_t)0xc043, (q15_t)0x45bc, (q15_t)0xc042, + (q15_t)0x45b0, (q15_t)0xc041, (q15_t)0x45a3, (q15_t)0xc040, (q15_t)0x4597, (q15_t)0xc03f, (q15_t)0x458a, (q15_t)0xc03d, + (q15_t)0x457e, (q15_t)0xc03c, (q15_t)0x4571, (q15_t)0xc03b, (q15_t)0x4565, (q15_t)0xc03a, (q15_t)0x4558, (q15_t)0xc039, + (q15_t)0x454c, (q15_t)0xc038, (q15_t)0x453f, (q15_t)0xc037, (q15_t)0x4533, (q15_t)0xc036, (q15_t)0x4526, (q15_t)0xc035, + (q15_t)0x451a, (q15_t)0xc034, (q15_t)0x450d, (q15_t)0xc033, (q15_t)0x4500, (q15_t)0xc032, (q15_t)0x44f4, (q15_t)0xc031, + (q15_t)0x44e7, (q15_t)0xc030, (q15_t)0x44db, (q15_t)0xc02f, (q15_t)0x44ce, (q15_t)0xc02e, (q15_t)0x44c2, (q15_t)0xc02d, + (q15_t)0x44b5, (q15_t)0xc02c, (q15_t)0x44a9, (q15_t)0xc02b, (q15_t)0x449c, (q15_t)0xc02b, (q15_t)0x4490, (q15_t)0xc02a, + (q15_t)0x4483, (q15_t)0xc029, (q15_t)0x4477, (q15_t)0xc028, (q15_t)0x446a, (q15_t)0xc027, (q15_t)0x445e, (q15_t)0xc026, + (q15_t)0x4451, (q15_t)0xc025, (q15_t)0x4444, (q15_t)0xc024, (q15_t)0x4438, (q15_t)0xc024, (q15_t)0x442b, (q15_t)0xc023, + (q15_t)0x441f, (q15_t)0xc022, (q15_t)0x4412, (q15_t)0xc021, (q15_t)0x4406, (q15_t)0xc020, (q15_t)0x43f9, (q15_t)0xc020, + (q15_t)0x43ed, (q15_t)0xc01f, (q15_t)0x43e0, (q15_t)0xc01e, (q15_t)0x43d4, (q15_t)0xc01d, (q15_t)0x43c7, (q15_t)0xc01d, + (q15_t)0x43bb, (q15_t)0xc01c, (q15_t)0x43ae, (q15_t)0xc01b, (q15_t)0x43a1, (q15_t)0xc01a, (q15_t)0x4395, (q15_t)0xc01a, + (q15_t)0x4388, (q15_t)0xc019, (q15_t)0x437c, (q15_t)0xc018, (q15_t)0x436f, (q15_t)0xc018, (q15_t)0x4363, (q15_t)0xc017, + (q15_t)0x4356, (q15_t)0xc016, (q15_t)0x434a, (q15_t)0xc016, (q15_t)0x433d, (q15_t)0xc015, (q15_t)0x4330, (q15_t)0xc014, + (q15_t)0x4324, (q15_t)0xc014, (q15_t)0x4317, (q15_t)0xc013, (q15_t)0x430b, (q15_t)0xc013, (q15_t)0x42fe, (q15_t)0xc012, + (q15_t)0x42f2, (q15_t)0xc011, (q15_t)0x42e5, (q15_t)0xc011, (q15_t)0x42d9, (q15_t)0xc010, (q15_t)0x42cc, (q15_t)0xc010, + (q15_t)0x42c0, (q15_t)0xc00f, (q15_t)0x42b3, (q15_t)0xc00f, (q15_t)0x42a6, (q15_t)0xc00e, (q15_t)0x429a, (q15_t)0xc00e, + (q15_t)0x428d, (q15_t)0xc00d, (q15_t)0x4281, (q15_t)0xc00d, (q15_t)0x4274, (q15_t)0xc00c, (q15_t)0x4268, (q15_t)0xc00c, + (q15_t)0x425b, (q15_t)0xc00b, (q15_t)0x424e, (q15_t)0xc00b, (q15_t)0x4242, (q15_t)0xc00a, (q15_t)0x4235, (q15_t)0xc00a, + (q15_t)0x4229, (q15_t)0xc009, (q15_t)0x421c, (q15_t)0xc009, (q15_t)0x4210, (q15_t)0xc009, (q15_t)0x4203, (q15_t)0xc008, + (q15_t)0x41f7, (q15_t)0xc008, (q15_t)0x41ea, (q15_t)0xc007, (q15_t)0x41dd, (q15_t)0xc007, (q15_t)0x41d1, (q15_t)0xc007, + (q15_t)0x41c4, (q15_t)0xc006, (q15_t)0x41b8, (q15_t)0xc006, (q15_t)0x41ab, (q15_t)0xc006, (q15_t)0x419f, (q15_t)0xc005, + (q15_t)0x4192, (q15_t)0xc005, (q15_t)0x4186, (q15_t)0xc005, (q15_t)0x4179, (q15_t)0xc004, (q15_t)0x416c, (q15_t)0xc004, + (q15_t)0x4160, (q15_t)0xc004, (q15_t)0x4153, (q15_t)0xc004, (q15_t)0x4147, (q15_t)0xc003, (q15_t)0x413a, (q15_t)0xc003, + (q15_t)0x412e, (q15_t)0xc003, (q15_t)0x4121, (q15_t)0xc003, (q15_t)0x4114, (q15_t)0xc002, (q15_t)0x4108, (q15_t)0xc002, + (q15_t)0x40fb, (q15_t)0xc002, (q15_t)0x40ef, (q15_t)0xc002, (q15_t)0x40e2, (q15_t)0xc002, (q15_t)0x40d6, (q15_t)0xc001, + (q15_t)0x40c9, (q15_t)0xc001, (q15_t)0x40bc, (q15_t)0xc001, (q15_t)0x40b0, (q15_t)0xc001, (q15_t)0x40a3, (q15_t)0xc001, + (q15_t)0x4097, (q15_t)0xc001, (q15_t)0x408a, (q15_t)0xc001, (q15_t)0x407e, (q15_t)0xc000, (q15_t)0x4071, (q15_t)0xc000, + (q15_t)0x4065, (q15_t)0xc000, (q15_t)0x4058, (q15_t)0xc000, (q15_t)0x404b, (q15_t)0xc000, (q15_t)0x403f, (q15_t)0xc000, + (q15_t)0x4032, (q15_t)0xc000, (q15_t)0x4026, (q15_t)0xc000, (q15_t)0x4019, (q15_t)0xc000, (q15_t)0x400d, (q15_t)0xc000, +}; + +#endif +/** + @} end of RealFFT_Table group + */ + +/** + @ingroup DCT4_IDCT4 + */ + +/** + @addtogroup DCT4_IDCT4_Table DCT Type IV Tables + @{ + */ + +/** + @brief Weights Table + */ + +/** + @par + Weights tables are generated using the formula :
weights[n] = e^(-j*n*pi/(2*N))
+ @par + C command to generate the table +
+  for(i = 0; i< N; i++)
+  {
+    weights[(2*i)]   =  cos (i*c);
+    weights[(2*i)+1] = -sin (i*c);
+  } 
+ @par + where N is the Number of weights to be calculated and c is pi/(2*N) + @par + In the tables below the real and imaginary values are placed alternatively, hence the + array length is 2*N. + */ + + +/** + @par + cosFactor tables are generated using the formula :
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
+ @par + C command to generate the table + @par +
 for(i = 0; i< N; i++)
+  {
+     cos_factors[i]= 2 * cos((2*i+1)*c/2);
+  } 
+ @par + where N is the number of factors to generate and c is pi/(2*N) +*/ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128) + const float32_t Weights_128[256] = { + 1.000000000000000000f, 0.000000000000000000f, 0.999924701839144500f, -0.012271538285719925f, + 0.999698818696204250f, -0.024541228522912288f, 0.999322384588349540f, -0.036807222941358832f, + 0.998795456205172410f, -0.049067674327418015f, 0.998118112900149180f, -0.061320736302208578f, + 0.997290456678690210f, -0.073564563599667426f, 0.996312612182778000f, -0.085797312344439894f, + 0.995184726672196930f, -0.098017140329560604f, 0.993906970002356060f, -0.110222207293883060f, + 0.992479534598709970f, -0.122410675199216200f, 0.990902635427780010f, -0.134580708507126170f, + 0.989176509964781010f, -0.146730474455361750f, 0.987301418157858430f, -0.158858143333861450f, + 0.985277642388941220f, -0.170961888760301220f, 0.983105487431216290f, -0.183039887955140950f, + 0.980785280403230430f, -0.195090322016128250f, 0.978317370719627650f, -0.207111376192218560f, + 0.975702130038528570f, -0.219101240156869800f, 0.972939952205560180f, -0.231058108280671110f, + 0.970031253194543970f, -0.242980179903263870f, 0.966976471044852070f, -0.254865659604514570f, + 0.963776065795439840f, -0.266712757474898370f, 0.960430519415565790f, -0.278519689385053060f, + 0.956940335732208820f, -0.290284677254462330f, 0.953306040354193860f, -0.302005949319228080f, + 0.949528180593036670f, -0.313681740398891520f, 0.945607325380521280f, -0.325310292162262930f, + 0.941544065183020810f, -0.336889853392220050f, 0.937339011912574960f, -0.348418680249434560f, + 0.932992798834738960f, -0.359895036534988110f, 0.928506080473215590f, -0.371317193951837540f, + 0.923879532511286740f, -0.382683432365089780f, 0.919113851690057770f, -0.393992040061048100f, + 0.914209755703530690f, -0.405241314004989860f, 0.909167983090522380f, -0.416429560097637150f, + 0.903989293123443340f, -0.427555093430282080f, 0.898674465693953820f, -0.438616238538527660f, + 0.893224301195515320f, -0.449611329654606540f, 0.887639620402853930f, -0.460538710958240010f, + 0.881921264348355050f, -0.471396736825997640f, 0.876070094195406600f, -0.482183772079122720f, + 0.870086991108711460f, -0.492898192229784040f, 0.863972856121586810f, -0.503538383725717580f, + 0.857728610000272120f, -0.514102744193221660f, 0.851355193105265200f, -0.524589682678468950f, + 0.844853565249707120f, -0.534997619887097150f, 0.838224705554838080f, -0.545324988422046460f, + 0.831469612302545240f, -0.555570233019602180f, 0.824589302785025290f, -0.565731810783613120f, + 0.817584813151583710f, -0.575808191417845340f, 0.810457198252594770f, -0.585797857456438860f, + 0.803207531480644940f, -0.595699304492433360f, 0.795836904608883570f, -0.605511041404325550f, + 0.788346427626606340f, -0.615231590580626820f, 0.780737228572094490f, -0.624859488142386340f, + 0.773010453362736990f, -0.634393284163645490f, 0.765167265622458960f, -0.643831542889791390f, + 0.757208846506484570f, -0.653172842953776760f, 0.749136394523459370f, -0.662415777590171780f, + 0.740951125354959110f, -0.671558954847018330f, 0.732654271672412820f, -0.680600997795453020f, + 0.724247082951467000f, -0.689540544737066830f, 0.715730825283818590f, -0.698376249408972920f, + 0.707106781186547570f, -0.707106781186547460f, 0.698376249408972920f, -0.715730825283818590f, + 0.689540544737066940f, -0.724247082951466890f, 0.680600997795453130f, -0.732654271672412820f, + 0.671558954847018330f, -0.740951125354959110f, 0.662415777590171780f, -0.749136394523459260f, + 0.653172842953776760f, -0.757208846506484460f, 0.643831542889791500f, -0.765167265622458960f, + 0.634393284163645490f, -0.773010453362736990f, 0.624859488142386450f, -0.780737228572094380f, + 0.615231590580626820f, -0.788346427626606230f, 0.605511041404325550f, -0.795836904608883460f, + 0.595699304492433470f, -0.803207531480644830f, 0.585797857456438860f, -0.810457198252594770f, + 0.575808191417845340f, -0.817584813151583710f, 0.565731810783613230f, -0.824589302785025290f, + 0.555570233019602290f, -0.831469612302545240f, 0.545324988422046460f, -0.838224705554837970f, + 0.534997619887097260f, -0.844853565249707010f, 0.524589682678468840f, -0.851355193105265200f, + 0.514102744193221660f, -0.857728610000272120f, 0.503538383725717580f, -0.863972856121586700f, + 0.492898192229784090f, -0.870086991108711350f, 0.482183772079122830f, -0.876070094195406600f, + 0.471396736825997810f, -0.881921264348354940f, 0.460538710958240010f, -0.887639620402853930f, + 0.449611329654606600f, -0.893224301195515320f, 0.438616238538527710f, -0.898674465693953820f, + 0.427555093430282200f, -0.903989293123443340f, 0.416429560097637320f, -0.909167983090522270f, + 0.405241314004989860f, -0.914209755703530690f, 0.393992040061048100f, -0.919113851690057770f, + 0.382683432365089840f, -0.923879532511286740f, 0.371317193951837600f, -0.928506080473215480f, + 0.359895036534988280f, -0.932992798834738850f, 0.348418680249434510f, -0.937339011912574960f, + 0.336889853392220050f, -0.941544065183020810f, 0.325310292162262980f, -0.945607325380521280f, + 0.313681740398891570f, -0.949528180593036670f, 0.302005949319228200f, -0.953306040354193750f, + 0.290284677254462330f, -0.956940335732208940f, 0.278519689385053060f, -0.960430519415565790f, + 0.266712757474898420f, -0.963776065795439840f, 0.254865659604514630f, -0.966976471044852070f, + 0.242980179903263980f, -0.970031253194543970f, 0.231058108280671280f, -0.972939952205560070f, + 0.219101240156869770f, -0.975702130038528570f, 0.207111376192218560f, -0.978317370719627650f, + 0.195090322016128330f, -0.980785280403230430f, 0.183039887955141060f, -0.983105487431216290f, + 0.170961888760301360f, -0.985277642388941220f, 0.158858143333861390f, -0.987301418157858430f, + 0.146730474455361750f, -0.989176509964781010f, 0.134580708507126220f, -0.990902635427780010f, + 0.122410675199216280f, -0.992479534598709970f, 0.110222207293883180f, -0.993906970002356060f, + 0.098017140329560770f, -0.995184726672196820f, 0.085797312344439880f, -0.996312612182778000f, + 0.073564563599667454f, -0.997290456678690210f, 0.061320736302208648f, -0.998118112900149180f, + 0.049067674327418126f, -0.998795456205172410f, 0.036807222941358991f, -0.999322384588349540f, + 0.024541228522912264f, -0.999698818696204250f, 0.012271538285719944f, -0.999924701839144500f +}; + + const float32_t cos_factors_128[128] = { + 0.999981175282601110f, 0.999830581795823400f, 0.999529417501093140f, + 0.999077727752645360f, + 0.998475580573294770f, 0.997723066644191640f, 0.996820299291165670f, + 0.995767414467659820f, + 0.994564570734255420f, 0.993211949234794500f, 0.991709753669099530f, + 0.990058210262297120f, + 0.988257567730749460f, 0.986308097244598670f, 0.984210092386929030f, + 0.981963869109555240f, + 0.979569765685440520f, 0.977028142657754390f, 0.974339382785575860f, + 0.971503890986251780f, + 0.968522094274417380f, 0.965394441697689400f, 0.962121404269041580f, + 0.958703474895871600f, + 0.955141168305770780f, 0.951435020969008340f, 0.947585591017741090f, + 0.943593458161960390f, + 0.939459223602189920f, 0.935183509938947610f, 0.930766961078983710f, + 0.926210242138311380f, + 0.921514039342042010f, 0.916679059921042700f, 0.911706032005429880f, + 0.906595704514915330f, + 0.901348847046022030f, 0.895966249756185220f, 0.890448723244757880f, + 0.884797098430937790f, + 0.879012226428633530f, 0.873094978418290090f, 0.867046245515692650f, + 0.860866938637767310f, + 0.854557988365400530f, 0.848120344803297230f, 0.841554977436898440f, + 0.834862874986380010f, + 0.828045045257755800f, 0.821102514991104650f, 0.814036329705948410f, + 0.806847553543799330f, + 0.799537269107905010f, 0.792106577300212390f, 0.784556597155575240f, + 0.776888465673232440f, + 0.769103337645579700f, 0.761202385484261780f, 0.753186799043612520f, + 0.745057785441466060f, + 0.736816568877369900f, 0.728464390448225200f, 0.720002507961381650f, + 0.711432195745216430f, + 0.702754744457225300f, 0.693971460889654000f, 0.685083667772700360f, + 0.676092703575316030f, + 0.666999922303637470f, 0.657806693297078640f, 0.648514401022112550f, + 0.639124444863775730f, + 0.629638238914927100f, 0.620057211763289210f, 0.610382806276309480f, + 0.600616479383868970f, + 0.590759701858874280f, 0.580813958095764530f, 0.570780745886967370f, + 0.560661576197336030f, + 0.550457972936604810f, 0.540171472729892970f, 0.529803624686294830f, + 0.519355990165589530f, + 0.508830142543106990f, 0.498227666972781870f, 0.487550160148436050f, + 0.476799230063322250f, + 0.465976495767966130f, 0.455083587126343840f, 0.444122144570429260f, + 0.433093818853152010f, + 0.422000270799799790f, 0.410843171057903910f, 0.399624199845646790f, + 0.388345046698826300f, + 0.377007410216418310f, 0.365612997804773960f, 0.354163525420490510f, + 0.342660717311994380f, + 0.331106305759876430f, 0.319502030816015750f, 0.307849640041534980f, + 0.296150888243623960f, + 0.284407537211271820f, 0.272621355449948980f, 0.260794117915275570f, + 0.248927605745720260f, + 0.237023605994367340f, 0.225083911359792780f, 0.213110319916091360f, + 0.201104634842091960f, + 0.189068664149806280f, 0.177004220412148860f, 0.164913120489970090f, + 0.152797185258443410f, + 0.140658239332849240f, 0.128498110793793220f, 0.116318630911904880f, + 0.104121633872054730f, + 0.091908956497132696f, 0.079682437971430126f, 0.067443919563664106f, + 0.055195244349690031f, + 0.042938256934940959f, 0.030674803176636581f, 0.018406729905804820f, + 0.006135884649154515f +}; + + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512) + const float32_t Weights_512[1024] = { + 1.000000000000000000f, 0.000000000000000000f, 0.999995293809576190f, -0.003067956762965976f, + 0.999981175282601110f, -0.006135884649154475f, 0.999957644551963900f, -0.009203754782059819f, + 0.999924701839144500f, -0.012271538285719925f, 0.999882347454212560f, -0.015339206284988100f, + 0.999830581795823400f, -0.018406729905804820f, 0.999769405351215280f, -0.021474080275469508f, + 0.999698818696204250f, -0.024541228522912288f, 0.999618822495178640f, -0.027608145778965740f, + 0.999529417501093140f, -0.030674803176636626f, 0.999430604555461730f, -0.033741171851377580f, + 0.999322384588349540f, -0.036807222941358832f, 0.999204758618363890f, -0.039872927587739811f, + 0.999077727752645360f, -0.042938256934940820f, 0.998941293186856870f, -0.046003182130914623f, + 0.998795456205172410f, -0.049067674327418015f, 0.998640218180265270f, -0.052131704680283324f, + 0.998475580573294770f, -0.055195244349689934f, 0.998301544933892890f, -0.058258264500435752f, + 0.998118112900149180f, -0.061320736302208578f, 0.997925286198596000f, -0.064382630929857465f, + 0.997723066644191640f, -0.067443919563664051f, 0.997511456140303450f, -0.070504573389613856f, + 0.997290456678690210f, -0.073564563599667426f, 0.997060070339482960f, -0.076623861392031492f, + 0.996820299291165670f, -0.079682437971430126f, 0.996571145790554840f, -0.082740264549375692f, + 0.996312612182778000f, -0.085797312344439894f, 0.996044700901251970f, -0.088853552582524600f, + 0.995767414467659820f, -0.091908956497132724f, 0.995480755491926940f, -0.094963495329638992f, + 0.995184726672196930f, -0.098017140329560604f, 0.994879330794805620f, -0.101069862754827820f, + 0.994564570734255420f, -0.104121633872054590f, 0.994240449453187900f, -0.107172424956808840f, + 0.993906970002356060f, -0.110222207293883060f, 0.993564135520595300f, -0.113270952177564350f, + 0.993211949234794500f, -0.116318630911904750f, 0.992850414459865100f, -0.119365214810991350f, + 0.992479534598709970f, -0.122410675199216200f, 0.992099313142191800f, -0.125454983411546230f, + 0.991709753669099530f, -0.128498110793793170f, 0.991310859846115440f, -0.131540028702883120f, + 0.990902635427780010f, -0.134580708507126170f, 0.990485084256457090f, -0.137620121586486040f, + 0.990058210262297120f, -0.140658239332849210f, 0.989622017463200890f, -0.143695033150294470f, + 0.989176509964781010f, -0.146730474455361750f, 0.988721691960323780f, -0.149764534677321510f, + 0.988257567730749460f, -0.152797185258443440f, 0.987784141644572180f, -0.155828397654265230f, + 0.987301418157858430f, -0.158858143333861450f, 0.986809401814185530f, -0.161886393780111830f, + 0.986308097244598670f, -0.164913120489969890f, 0.985797509167567480f, -0.167938294974731170f, + 0.985277642388941220f, -0.170961888760301220f, 0.984748501801904210f, -0.173983873387463820f, + 0.984210092386929030f, -0.177004220412148750f, 0.983662419211730250f, -0.180022901405699510f, + 0.983105487431216290f, -0.183039887955140950f, 0.982539302287441240f, -0.186055151663446630f, + 0.981963869109555240f, -0.189068664149806190f, 0.981379193313754560f, -0.192080397049892440f, + 0.980785280403230430f, -0.195090322016128250f, 0.980182135968117430f, -0.198098410717953560f, + 0.979569765685440520f, -0.201104634842091900f, 0.978948175319062200f, -0.204108966092816870f, + 0.978317370719627650f, -0.207111376192218560f, 0.977677357824509930f, -0.210111836880469610f, + 0.977028142657754390f, -0.213110319916091360f, 0.976369731330021140f, -0.216106797076219520f, + 0.975702130038528570f, -0.219101240156869800f, 0.975025345066994120f, -0.222093620973203510f, + 0.974339382785575860f, -0.225083911359792830f, 0.973644249650811980f, -0.228072083170885730f, + 0.972939952205560180f, -0.231058108280671110f, 0.972226497078936270f, -0.234041958583543430f, + 0.971503890986251780f, -0.237023605994367200f, 0.970772140728950350f, -0.240003022448741500f, + 0.970031253194543970f, -0.242980179903263870f, 0.969281235356548530f, -0.245955050335794590f, + 0.968522094274417380f, -0.248927605745720150f, 0.967753837093475510f, -0.251897818154216970f, + 0.966976471044852070f, -0.254865659604514570f, 0.966190003445412500f, -0.257831102162158990f, + 0.965394441697689400f, -0.260794117915275510f, 0.964589793289812760f, -0.263754678974831350f, + 0.963776065795439840f, -0.266712757474898370f, 0.962953266873683880f, -0.269668325572915090f, + 0.962121404269041580f, -0.272621355449948980f, 0.961280485811320640f, -0.275571819310958140f, + 0.960430519415565790f, -0.278519689385053060f, 0.959571513081984520f, -0.281464937925757940f, + 0.958703474895871600f, -0.284407537211271880f, 0.957826413027532910f, -0.287347459544729510f, + 0.956940335732208820f, -0.290284677254462330f, 0.956045251349996410f, -0.293219162694258630f, + 0.955141168305770780f, -0.296150888243623790f, 0.954228095109105670f, -0.299079826308040480f, + 0.953306040354193860f, -0.302005949319228080f, 0.952375012719765880f, -0.304929229735402370f, + 0.951435020969008340f, -0.307849640041534870f, 0.950486073949481700f, -0.310767152749611470f, + 0.949528180593036670f, -0.313681740398891520f, 0.948561349915730270f, -0.316593375556165850f, + 0.947585591017741090f, -0.319502030816015690f, 0.946600913083283530f, -0.322407678801069850f, + 0.945607325380521280f, -0.325310292162262930f, 0.944604837261480260f, -0.328209843579092500f, + 0.943593458161960390f, -0.331106305759876430f, 0.942573197601446870f, -0.333999651442009380f, + 0.941544065183020810f, -0.336889853392220050f, 0.940506070593268300f, -0.339776884406826850f, + 0.939459223602189920f, -0.342660717311994380f, 0.938403534063108060f, -0.345541324963989090f, + 0.937339011912574960f, -0.348418680249434560f, 0.936265667170278260f, -0.351292756085567090f, + 0.935183509938947610f, -0.354163525420490340f, 0.934092550404258980f, -0.357030961233429980f, + 0.932992798834738960f, -0.359895036534988110f, 0.931884265581668150f, -0.362755724367397230f, + 0.930766961078983710f, -0.365612997804773850f, 0.929640895843181330f, -0.368466829953372320f, + 0.928506080473215590f, -0.371317193951837540f, 0.927362525650401110f, -0.374164062971457930f, + 0.926210242138311380f, -0.377007410216418260f, 0.925049240782677580f, -0.379847208924051160f, + 0.923879532511286740f, -0.382683432365089780f, 0.922701128333878630f, -0.385516053843918850f, + 0.921514039342042010f, -0.388345046698826250f, 0.920318276709110590f, -0.391170384302253870f, + 0.919113851690057770f, -0.393992040061048100f, 0.917900775621390500f, -0.396809987416710310f, + 0.916679059921042700f, -0.399624199845646790f, 0.915448716088267830f, -0.402434650859418430f, + 0.914209755703530690f, -0.405241314004989860f, 0.912962190428398210f, -0.408044162864978690f, + 0.911706032005429880f, -0.410843171057903910f, 0.910441292258067250f, -0.413638312238434500f, + 0.909167983090522380f, -0.416429560097637150f, 0.907886116487666260f, -0.419216888363223910f, + 0.906595704514915330f, -0.422000270799799680f, 0.905296759318118820f, -0.424779681209108810f, + 0.903989293123443340f, -0.427555093430282080f, 0.902673318237258830f, -0.430326481340082610f, + 0.901348847046022030f, -0.433093818853151960f, 0.900015892016160280f, -0.435857079922255470f, + 0.898674465693953820f, -0.438616238538527660f, 0.897324580705418320f, -0.441371268731716670f, + 0.895966249756185220f, -0.444122144570429200f, 0.894599485631382700f, -0.446868840162374160f, + 0.893224301195515320f, -0.449611329654606540f, 0.891840709392342720f, -0.452349587233770890f, + 0.890448723244757880f, -0.455083587126343840f, 0.889048355854664570f, -0.457813303598877170f, + 0.887639620402853930f, -0.460538710958240010f, 0.886222530148880640f, -0.463259783551860150f, + 0.884797098430937790f, -0.465976495767966180f, 0.883363338665731580f, -0.468688822035827900f, + 0.881921264348355050f, -0.471396736825997640f, 0.880470889052160750f, -0.474100214650549970f, + 0.879012226428633530f, -0.476799230063322090f, 0.877545290207261350f, -0.479493757660153010f, + 0.876070094195406600f, -0.482183772079122720f, 0.874586652278176110f, -0.484869248000791060f, + 0.873094978418290090f, -0.487550160148436000f, 0.871595086655950980f, -0.490226483288291160f, + 0.870086991108711460f, -0.492898192229784040f, 0.868570705971340900f, -0.495565261825772540f, + 0.867046245515692650f, -0.498227666972781870f, 0.865513624090569090f, -0.500885382611240710f, + 0.863972856121586810f, -0.503538383725717580f, 0.862423956111040610f, -0.506186645345155230f, + 0.860866938637767310f, -0.508830142543106990f, 0.859301818357008470f, -0.511468850437970300f, + 0.857728610000272120f, -0.514102744193221660f, 0.856147328375194470f, -0.516731799017649870f, + 0.854557988365400530f, -0.519355990165589640f, 0.852960604930363630f, -0.521975292937154390f, + 0.851355193105265200f, -0.524589682678468950f, 0.849741768000852550f, -0.527199134781901280f, + 0.848120344803297230f, -0.529803624686294610f, 0.846490938774052130f, -0.532403127877197900f, + 0.844853565249707120f, -0.534997619887097150f, 0.843208239641845440f, -0.537587076295645390f, + 0.841554977436898440f, -0.540171472729892850f, 0.839893794195999520f, -0.542750784864515890f, + 0.838224705554838080f, -0.545324988422046460f, 0.836547727223512010f, -0.547894059173100190f, + 0.834862874986380010f, -0.550457972936604810f, 0.833170164701913190f, -0.553016705580027470f, + 0.831469612302545240f, -0.555570233019602180f, 0.829761233794523050f, -0.558118531220556100f, + 0.828045045257755800f, -0.560661576197336030f, 0.826321062845663530f, -0.563199344013834090f, + 0.824589302785025290f, -0.565731810783613120f, 0.822849781375826430f, -0.568258952670131490f, + 0.821102514991104650f, -0.570780745886967260f, 0.819347520076796900f, -0.573297166698042200f, + 0.817584813151583710f, -0.575808191417845340f, 0.815814410806733780f, -0.578313796411655590f, + 0.814036329705948410f, -0.580813958095764530f, 0.812250586585203880f, -0.583308652937698290f, + 0.810457198252594770f, -0.585797857456438860f, 0.808656181588174980f, -0.588281548222645220f, + 0.806847553543799330f, -0.590759701858874160f, 0.805031331142963660f, -0.593232295039799800f, + 0.803207531480644940f, -0.595699304492433360f, 0.801376171723140240f, -0.598160706996342270f, + 0.799537269107905010f, -0.600616479383868970f, 0.797690840943391160f, -0.603066598540348160f, + 0.795836904608883570f, -0.605511041404325550f, 0.793975477554337170f, -0.607949784967773630f, + 0.792106577300212390f, -0.610382806276309480f, 0.790230221437310030f, -0.612810082429409710f, + 0.788346427626606340f, -0.615231590580626820f, 0.786455213599085770f, -0.617647307937803870f, + 0.784556597155575240f, -0.620057211763289100f, 0.782650596166575730f, -0.622461279374149970f, + 0.780737228572094490f, -0.624859488142386340f, 0.778816512381475980f, -0.627251815495144080f, + 0.776888465673232440f, -0.629638238914926980f, 0.774953106594873930f, -0.632018735939809060f, + 0.773010453362736990f, -0.634393284163645490f, 0.771060524261813820f, -0.636761861236284200f, + 0.769103337645579700f, -0.639124444863775730f, 0.767138911935820400f, -0.641481012808583160f, + 0.765167265622458960f, -0.643831542889791390f, 0.763188417263381270f, -0.646176012983316280f, + 0.761202385484261780f, -0.648514401022112440f, 0.759209188978388070f, -0.650846684996380880f, + 0.757208846506484570f, -0.653172842953776760f, 0.755201376896536550f, -0.655492852999615350f, + 0.753186799043612520f, -0.657806693297078640f, 0.751165131909686480f, -0.660114342067420480f, + 0.749136394523459370f, -0.662415777590171780f, 0.747100605980180130f, -0.664710978203344790f, + 0.745057785441466060f, -0.666999922303637470f, 0.743007952135121720f, -0.669282588346636010f, + 0.740951125354959110f, -0.671558954847018330f, 0.738887324460615110f, -0.673829000378756040f, + 0.736816568877369900f, -0.676092703575315920f, 0.734738878095963500f, -0.678350043129861470f, + 0.732654271672412820f, -0.680600997795453020f, 0.730562769227827590f, -0.682845546385248080f, + 0.728464390448225200f, -0.685083667772700360f, 0.726359155084346010f, -0.687315340891759050f, + 0.724247082951467000f, -0.689540544737066830f, 0.722128193929215350f, -0.691759258364157750f, + 0.720002507961381650f, -0.693971460889654000f, 0.717870045055731710f, -0.696177131491462990f, + 0.715730825283818590f, -0.698376249408972920f, 0.713584868780793640f, -0.700568793943248340f, + 0.711432195745216430f, -0.702754744457225300f, 0.709272826438865690f, -0.704934080375904880f, + 0.707106781186547570f, -0.707106781186547460f, 0.704934080375904990f, -0.709272826438865580f, + 0.702754744457225300f, -0.711432195745216430f, 0.700568793943248450f, -0.713584868780793520f, + 0.698376249408972920f, -0.715730825283818590f, 0.696177131491462990f, -0.717870045055731710f, + 0.693971460889654000f, -0.720002507961381650f, 0.691759258364157750f, -0.722128193929215350f, + 0.689540544737066940f, -0.724247082951466890f, 0.687315340891759160f, -0.726359155084346010f, + 0.685083667772700360f, -0.728464390448225200f, 0.682845546385248080f, -0.730562769227827590f, + 0.680600997795453130f, -0.732654271672412820f, 0.678350043129861580f, -0.734738878095963390f, + 0.676092703575316030f, -0.736816568877369790f, 0.673829000378756150f, -0.738887324460615110f, + 0.671558954847018330f, -0.740951125354959110f, 0.669282588346636010f, -0.743007952135121720f, + 0.666999922303637470f, -0.745057785441465950f, 0.664710978203344900f, -0.747100605980180130f, + 0.662415777590171780f, -0.749136394523459260f, 0.660114342067420480f, -0.751165131909686370f, + 0.657806693297078640f, -0.753186799043612410f, 0.655492852999615460f, -0.755201376896536550f, + 0.653172842953776760f, -0.757208846506484460f, 0.650846684996380990f, -0.759209188978387960f, + 0.648514401022112550f, -0.761202385484261780f, 0.646176012983316390f, -0.763188417263381270f, + 0.643831542889791500f, -0.765167265622458960f, 0.641481012808583160f, -0.767138911935820400f, + 0.639124444863775730f, -0.769103337645579590f, 0.636761861236284200f, -0.771060524261813710f, + 0.634393284163645490f, -0.773010453362736990f, 0.632018735939809060f, -0.774953106594873820f, + 0.629638238914927100f, -0.776888465673232440f, 0.627251815495144190f, -0.778816512381475870f, + 0.624859488142386450f, -0.780737228572094380f, 0.622461279374150080f, -0.782650596166575730f, + 0.620057211763289210f, -0.784556597155575240f, 0.617647307937803980f, -0.786455213599085770f, + 0.615231590580626820f, -0.788346427626606230f, 0.612810082429409710f, -0.790230221437310030f, + 0.610382806276309480f, -0.792106577300212390f, 0.607949784967773740f, -0.793975477554337170f, + 0.605511041404325550f, -0.795836904608883460f, 0.603066598540348280f, -0.797690840943391040f, + 0.600616479383868970f, -0.799537269107905010f, 0.598160706996342380f, -0.801376171723140130f, + 0.595699304492433470f, -0.803207531480644830f, 0.593232295039799800f, -0.805031331142963660f, + 0.590759701858874280f, -0.806847553543799220f, 0.588281548222645330f, -0.808656181588174980f, + 0.585797857456438860f, -0.810457198252594770f, 0.583308652937698290f, -0.812250586585203880f, + 0.580813958095764530f, -0.814036329705948300f, 0.578313796411655590f, -0.815814410806733780f, + 0.575808191417845340f, -0.817584813151583710f, 0.573297166698042320f, -0.819347520076796900f, + 0.570780745886967370f, -0.821102514991104650f, 0.568258952670131490f, -0.822849781375826320f, + 0.565731810783613230f, -0.824589302785025290f, 0.563199344013834090f, -0.826321062845663420f, + 0.560661576197336030f, -0.828045045257755800f, 0.558118531220556100f, -0.829761233794523050f, + 0.555570233019602290f, -0.831469612302545240f, 0.553016705580027580f, -0.833170164701913190f, + 0.550457972936604810f, -0.834862874986380010f, 0.547894059173100190f, -0.836547727223511890f, + 0.545324988422046460f, -0.838224705554837970f, 0.542750784864516000f, -0.839893794195999410f, + 0.540171472729892970f, -0.841554977436898330f, 0.537587076295645510f, -0.843208239641845440f, + 0.534997619887097260f, -0.844853565249707010f, 0.532403127877198010f, -0.846490938774052020f, + 0.529803624686294830f, -0.848120344803297120f, 0.527199134781901390f, -0.849741768000852440f, + 0.524589682678468840f, -0.851355193105265200f, 0.521975292937154390f, -0.852960604930363630f, + 0.519355990165589530f, -0.854557988365400530f, 0.516731799017649980f, -0.856147328375194470f, + 0.514102744193221660f, -0.857728610000272120f, 0.511468850437970520f, -0.859301818357008360f, + 0.508830142543106990f, -0.860866938637767310f, 0.506186645345155450f, -0.862423956111040500f, + 0.503538383725717580f, -0.863972856121586700f, 0.500885382611240940f, -0.865513624090568980f, + 0.498227666972781870f, -0.867046245515692650f, 0.495565261825772490f, -0.868570705971340900f, + 0.492898192229784090f, -0.870086991108711350f, 0.490226483288291100f, -0.871595086655951090f, + 0.487550160148436050f, -0.873094978418290090f, 0.484869248000791120f, -0.874586652278176110f, + 0.482183772079122830f, -0.876070094195406600f, 0.479493757660153010f, -0.877545290207261240f, + 0.476799230063322250f, -0.879012226428633410f, 0.474100214650550020f, -0.880470889052160750f, + 0.471396736825997810f, -0.881921264348354940f, 0.468688822035827960f, -0.883363338665731580f, + 0.465976495767966130f, -0.884797098430937790f, 0.463259783551860260f, -0.886222530148880640f, + 0.460538710958240010f, -0.887639620402853930f, 0.457813303598877290f, -0.889048355854664570f, + 0.455083587126343840f, -0.890448723244757880f, 0.452349587233771000f, -0.891840709392342720f, + 0.449611329654606600f, -0.893224301195515320f, 0.446868840162374330f, -0.894599485631382580f, + 0.444122144570429260f, -0.895966249756185110f, 0.441371268731716620f, -0.897324580705418320f, + 0.438616238538527710f, -0.898674465693953820f, 0.435857079922255470f, -0.900015892016160280f, + 0.433093818853152010f, -0.901348847046022030f, 0.430326481340082610f, -0.902673318237258830f, + 0.427555093430282200f, -0.903989293123443340f, 0.424779681209108810f, -0.905296759318118820f, + 0.422000270799799790f, -0.906595704514915330f, 0.419216888363223960f, -0.907886116487666150f, + 0.416429560097637320f, -0.909167983090522270f, 0.413638312238434560f, -0.910441292258067140f, + 0.410843171057903910f, -0.911706032005429880f, 0.408044162864978740f, -0.912962190428398100f, + 0.405241314004989860f, -0.914209755703530690f, 0.402434650859418540f, -0.915448716088267830f, + 0.399624199845646790f, -0.916679059921042700f, 0.396809987416710420f, -0.917900775621390390f, + 0.393992040061048100f, -0.919113851690057770f, 0.391170384302253980f, -0.920318276709110480f, + 0.388345046698826300f, -0.921514039342041900f, 0.385516053843919020f, -0.922701128333878520f, + 0.382683432365089840f, -0.923879532511286740f, 0.379847208924051110f, -0.925049240782677580f, + 0.377007410216418310f, -0.926210242138311270f, 0.374164062971457990f, -0.927362525650401110f, + 0.371317193951837600f, -0.928506080473215480f, 0.368466829953372320f, -0.929640895843181330f, + 0.365612997804773960f, -0.930766961078983710f, 0.362755724367397230f, -0.931884265581668150f, + 0.359895036534988280f, -0.932992798834738850f, 0.357030961233430030f, -0.934092550404258870f, + 0.354163525420490510f, -0.935183509938947500f, 0.351292756085567150f, -0.936265667170278260f, + 0.348418680249434510f, -0.937339011912574960f, 0.345541324963989150f, -0.938403534063108060f, + 0.342660717311994380f, -0.939459223602189920f, 0.339776884406826960f, -0.940506070593268300f, + 0.336889853392220050f, -0.941544065183020810f, 0.333999651442009490f, -0.942573197601446870f, + 0.331106305759876430f, -0.943593458161960390f, 0.328209843579092660f, -0.944604837261480260f, + 0.325310292162262980f, -0.945607325380521280f, 0.322407678801070020f, -0.946600913083283530f, + 0.319502030816015750f, -0.947585591017741090f, 0.316593375556165850f, -0.948561349915730270f, + 0.313681740398891570f, -0.949528180593036670f, 0.310767152749611470f, -0.950486073949481700f, + 0.307849640041534980f, -0.951435020969008340f, 0.304929229735402430f, -0.952375012719765880f, + 0.302005949319228200f, -0.953306040354193750f, 0.299079826308040480f, -0.954228095109105670f, + 0.296150888243623960f, -0.955141168305770670f, 0.293219162694258680f, -0.956045251349996410f, + 0.290284677254462330f, -0.956940335732208940f, 0.287347459544729570f, -0.957826413027532910f, + 0.284407537211271820f, -0.958703474895871600f, 0.281464937925758050f, -0.959571513081984520f, + 0.278519689385053060f, -0.960430519415565790f, 0.275571819310958250f, -0.961280485811320640f, + 0.272621355449948980f, -0.962121404269041580f, 0.269668325572915200f, -0.962953266873683880f, + 0.266712757474898420f, -0.963776065795439840f, 0.263754678974831510f, -0.964589793289812650f, + 0.260794117915275570f, -0.965394441697689400f, 0.257831102162158930f, -0.966190003445412620f, + 0.254865659604514630f, -0.966976471044852070f, 0.251897818154216910f, -0.967753837093475510f, + 0.248927605745720260f, -0.968522094274417270f, 0.245955050335794590f, -0.969281235356548530f, + 0.242980179903263980f, -0.970031253194543970f, 0.240003022448741500f, -0.970772140728950350f, + 0.237023605994367340f, -0.971503890986251780f, 0.234041958583543460f, -0.972226497078936270f, + 0.231058108280671280f, -0.972939952205560070f, 0.228072083170885790f, -0.973644249650811870f, + 0.225083911359792780f, -0.974339382785575860f, 0.222093620973203590f, -0.975025345066994120f, + 0.219101240156869770f, -0.975702130038528570f, 0.216106797076219600f, -0.976369731330021140f, + 0.213110319916091360f, -0.977028142657754390f, 0.210111836880469720f, -0.977677357824509930f, + 0.207111376192218560f, -0.978317370719627650f, 0.204108966092817010f, -0.978948175319062200f, + 0.201104634842091960f, -0.979569765685440520f, 0.198098410717953730f, -0.980182135968117320f, + 0.195090322016128330f, -0.980785280403230430f, 0.192080397049892380f, -0.981379193313754560f, + 0.189068664149806280f, -0.981963869109555240f, 0.186055151663446630f, -0.982539302287441240f, + 0.183039887955141060f, -0.983105487431216290f, 0.180022901405699510f, -0.983662419211730250f, + 0.177004220412148860f, -0.984210092386929030f, 0.173983873387463850f, -0.984748501801904210f, + 0.170961888760301360f, -0.985277642388941220f, 0.167938294974731230f, -0.985797509167567370f, + 0.164913120489970090f, -0.986308097244598670f, 0.161886393780111910f, -0.986809401814185420f, + 0.158858143333861390f, -0.987301418157858430f, 0.155828397654265320f, -0.987784141644572180f, + 0.152797185258443410f, -0.988257567730749460f, 0.149764534677321620f, -0.988721691960323780f, + 0.146730474455361750f, -0.989176509964781010f, 0.143695033150294580f, -0.989622017463200780f, + 0.140658239332849240f, -0.990058210262297120f, 0.137620121586486180f, -0.990485084256456980f, + 0.134580708507126220f, -0.990902635427780010f, 0.131540028702883280f, -0.991310859846115440f, + 0.128498110793793220f, -0.991709753669099530f, 0.125454983411546210f, -0.992099313142191800f, + 0.122410675199216280f, -0.992479534598709970f, 0.119365214810991350f, -0.992850414459865100f, + 0.116318630911904880f, -0.993211949234794500f, 0.113270952177564360f, -0.993564135520595300f, + 0.110222207293883180f, -0.993906970002356060f, 0.107172424956808870f, -0.994240449453187900f, + 0.104121633872054730f, -0.994564570734255420f, 0.101069862754827880f, -0.994879330794805620f, + 0.098017140329560770f, -0.995184726672196820f, 0.094963495329639061f, -0.995480755491926940f, + 0.091908956497132696f, -0.995767414467659820f, 0.088853552582524684f, -0.996044700901251970f, + 0.085797312344439880f, -0.996312612182778000f, 0.082740264549375803f, -0.996571145790554840f, + 0.079682437971430126f, -0.996820299291165670f, 0.076623861392031617f, -0.997060070339482960f, + 0.073564563599667454f, -0.997290456678690210f, 0.070504573389614009f, -0.997511456140303450f, + 0.067443919563664106f, -0.997723066644191640f, 0.064382630929857410f, -0.997925286198596000f, + 0.061320736302208648f, -0.998118112900149180f, 0.058258264500435732f, -0.998301544933892890f, + 0.055195244349690031f, -0.998475580573294770f, 0.052131704680283317f, -0.998640218180265270f, + 0.049067674327418126f, -0.998795456205172410f, 0.046003182130914644f, -0.998941293186856870f, + 0.042938256934940959f, -0.999077727752645360f, 0.039872927587739845f, -0.999204758618363890f, + 0.036807222941358991f, -0.999322384588349540f, 0.033741171851377642f, -0.999430604555461730f, + 0.030674803176636581f, -0.999529417501093140f, 0.027608145778965820f, -0.999618822495178640f, + 0.024541228522912264f, -0.999698818696204250f, 0.021474080275469605f, -0.999769405351215280f, + 0.018406729905804820f, -0.999830581795823400f, 0.015339206284988220f, -0.999882347454212560f, + 0.012271538285719944f, -0.999924701839144500f, 0.009203754782059960f, -0.999957644551963900f, + 0.006135884649154515f, -0.999981175282601110f, 0.003067956762966138f, -0.999995293809576190f +}; + + const float32_t cos_factors_512[512] = { + 0.999998823451701880f, 0.999989411081928400f, 0.999970586430974140f, + 0.999942349676023910f, + 0.999904701082852900f, 0.999857641005823860f, 0.999801169887884260f, + 0.999735288260561680f, + 0.999659996743959220f, 0.999575296046749220f, 0.999481186966166950f, + 0.999377670388002850f, + 0.999264747286594420f, 0.999142418724816910f, 0.999010685854073380f, + 0.998869549914283560f, + 0.998719012233872940f, 0.998559074229759310f, 0.998389737407340160f, + 0.998211003360478190f, + 0.998022873771486240f, 0.997825350411111640f, 0.997618435138519550f, + 0.997402129901275300f, + 0.997176436735326190f, 0.996941357764982160f, 0.996696895202896060f, + 0.996443051350042630f, + 0.996179828595696980f, 0.995907229417411720f, 0.995625256380994310f, + 0.995333912140482280f, + 0.995033199438118630f, 0.994723121104325700f, 0.994403680057679100f, + 0.994074879304879370f, + 0.993736721940724600f, 0.993389211148080650f, 0.993032350197851410f, + 0.992666142448948020f, + 0.992290591348257370f, 0.991905700430609330f, 0.991511473318743900f, + 0.991107913723276890f, + 0.990695025442664630f, 0.990272812363169110f, 0.989841278458820530f, + 0.989400427791380380f, + 0.988950264510302990f, 0.988490792852696590f, 0.988022017143283530f, + 0.987543941794359230f, + 0.987056571305750970f, 0.986559910264775410f, 0.986053963346195440f, + 0.985538735312176060f, + 0.985014231012239840f, 0.984480455383220930f, 0.983937413449218920f, + 0.983385110321551180f, + 0.982823551198705240f, 0.982252741366289370f, 0.981672686196983110f, + 0.981083391150486710f, + 0.980484861773469380f, 0.979877103699517640f, 0.979260122649082020f, + 0.978633924429423210f, + 0.977998514934557140f, 0.977353900145199960f, 0.976700086128711840f, + 0.976037079039039020f, + 0.975364885116656980f, 0.974683510688510670f, 0.973992962167955830f, + 0.973293246054698250f, + 0.972584368934732210f, 0.971866337480279400f, 0.971139158449725090f, + 0.970402838687555500f, + 0.969657385124292450f, 0.968902804776428870f, 0.968139104746362440f, + 0.967366292222328510f, + 0.966584374478333120f, 0.965793358874083680f, 0.964993252854920320f, + 0.964184063951745830f, + 0.963365799780954050f, 0.962538468044359160f, 0.961702076529122540f, + 0.960856633107679660f, + 0.960002145737665960f, 0.959138622461841890f, 0.958266071408017670f, + 0.957384500788975860f, + 0.956493918902395100f, 0.955594334130771110f, 0.954685754941338340f, + 0.953768189885990330f, + 0.952841647601198720f, 0.951906136807932350f, 0.950961666311575080f, + 0.950008245001843000f, + 0.949045881852700560f, 0.948074585922276230f, 0.947094366352777220f, + 0.946105232370403450f, + 0.945107193285260610f, 0.944100258491272660f, 0.943084437466093490f, + 0.942059739771017310f, + 0.941026175050889260f, 0.939983753034014050f, 0.938932483532064600f, + 0.937872376439989890f, + 0.936803441735921560f, 0.935725689481080370f, 0.934639129819680780f, + 0.933543772978836170f, + 0.932439629268462360f, 0.931326709081180430f, 0.930205022892219070f, + 0.929074581259315860f, + 0.927935394822617890f, 0.926787474304581750f, 0.925630830509872720f, + 0.924465474325262600f, + 0.923291416719527640f, 0.922108668743345180f, 0.920917241529189520f, + 0.919717146291227360f, + 0.918508394325212250f, 0.917290997008377910f, 0.916064965799331720f, + 0.914830312237946200f, + 0.913587047945250810f, 0.912335184623322750f, 0.911074734055176360f, + 0.909805708104652220f, + 0.908528118716306120f, 0.907241977915295820f, 0.905947297807268460f, + 0.904644090578246240f, + 0.903332368494511820f, 0.902012143902493180f, 0.900683429228646970f, + 0.899346236979341570f, + 0.898000579740739880f, 0.896646470178680150f, 0.895283921038557580f, + 0.893912945145203250f, + 0.892533555402764580f, 0.891145764794583180f, 0.889749586383072780f, + 0.888345033309596350f, + 0.886932118794342190f, 0.885510856136199950f, 0.884081258712634990f, + 0.882643339979562790f, + 0.881197113471222090f, 0.879742592800047410f, 0.878279791656541580f, + 0.876808723809145650f, + 0.875329403104110890f, 0.873841843465366860f, 0.872346058894391540f, + 0.870842063470078980f, + 0.869329871348606840f, 0.867809496763303320f, 0.866280954024512990f, + 0.864744257519462380f, + 0.863199421712124160f, 0.861646461143081300f, 0.860085390429390140f, + 0.858516224264442740f, + 0.856938977417828760f, 0.855353664735196030f, 0.853760301138111410f, + 0.852158901623919830f, + 0.850549481265603480f, 0.848932055211639610f, 0.847306638685858320f, + 0.845673246987299070f, + 0.844031895490066410f, 0.842382599643185850f, 0.840725374970458070f, + 0.839060237070312740f, + 0.837387201615661940f, 0.835706284353752600f, 0.834017501106018130f, + 0.832320867767929680f, + 0.830616400308846310f, 0.828904114771864870f, 0.827184027273669130f, + 0.825456154004377550f, + 0.823720511227391430f, 0.821977115279241550f, 0.820225982569434690f, + 0.818467129580298660f, + 0.816700572866827850f, 0.814926329056526620f, 0.813144414849253590f, + 0.811354847017063730f, + 0.809557642404051260f, 0.807752817926190360f, 0.805940390571176280f, + 0.804120377398265810f, + 0.802292795538115720f, 0.800457662192622820f, 0.798614994634760820f, + 0.796764810208418830f, + 0.794907126328237010f, 0.793041960479443640f, 0.791169330217690200f, + 0.789289253168885650f, + 0.787401747029031430f, 0.785506829564053930f, 0.783604518609638200f, + 0.781694832071059390f, + 0.779777787923014550f, 0.777853404209453150f, 0.775921699043407690f, + 0.773982690606822900f, + 0.772036397150384520f, 0.770082836993347900f, 0.768122028523365420f, + 0.766153990196312920f, + 0.764178740536116670f, 0.762196298134578900f, 0.760206681651202420f, + 0.758209909813015280f, + 0.756206001414394540f, 0.754194975316889170f, 0.752176850449042810f, + 0.750151645806215070f, + 0.748119380450403600f, 0.746080073510063780f, 0.744033744179929290f, + 0.741980411720831070f, + 0.739920095459516200f, 0.737852814788465980f, 0.735778589165713590f, + 0.733697438114660370f, + 0.731609381223892630f, 0.729514438146997010f, 0.727412628602375770f, + 0.725303972373060770f, + 0.723188489306527460f, 0.721066199314508110f, 0.718937122372804490f, + 0.716801278521099540f, + 0.714658687862769090f, 0.712509370564692320f, 0.710353346857062420f, + 0.708190637033195400f, + 0.706021261449339740f, 0.703845240524484940f, 0.701662594740168570f, + 0.699473344640283770f, + 0.697277510830886630f, 0.695075113980000880f, 0.692866174817424740f, + 0.690650714134534720f, + 0.688428752784090550f, 0.686200311680038700f, 0.683965411797315510f, + 0.681724074171649820f, + 0.679476319899365080f, 0.677222170137180450f, 0.674961646102012040f, + 0.672694769070772970f, + 0.670421560380173090f, 0.668142041426518560f, 0.665856233665509720f, + 0.663564158612039880f, + 0.661265837839992270f, 0.658961292982037320f, 0.656650545729429050f, + 0.654333617831800550f, + 0.652010531096959500f, 0.649681307390683190f, 0.647345968636512060f, + 0.645004536815544040f, + 0.642657033966226860f, 0.640303482184151670f, 0.637943903621844170f, + 0.635578320488556230f, + 0.633206755050057190f, 0.630829229628424470f, 0.628445766601832710f, + 0.626056388404343520f, + 0.623661117525694640f, 0.621259976511087660f, 0.618852987960976320f, + 0.616440174530853650f, + 0.614021558931038490f, 0.611597163926462020f, 0.609167012336453210f, + 0.606731127034524480f, + 0.604289530948156070f, 0.601842247058580030f, 0.599389298400564540f, + 0.596930708062196500f, + 0.594466499184664540f, 0.591996694962040990f, 0.589521318641063940f, + 0.587040393520918080f, + 0.584553942953015330f, 0.582061990340775550f, 0.579564559139405740f, + 0.577061672855679550f, + 0.574553355047715760f, 0.572039629324757050f, 0.569520519346947250f, + 0.566996048825108680f, + 0.564466241520519500f, 0.561931121244689470f, 0.559390711859136140f, + 0.556845037275160100f, + 0.554294121453620110f, 0.551737988404707450f, 0.549176662187719770f, + 0.546610166910834860f, + 0.544038526730883930f, 0.541461765853123560f, 0.538879908531008420f, + 0.536292979065963180f, + 0.533701001807152960f, 0.531104001151255000f, 0.528502001542228480f, + 0.525895027471084740f, + 0.523283103475656430f, 0.520666254140367270f, 0.518044504095999340f, + 0.515417878019463150f, + 0.512786400633563070f, 0.510150096706766700f, 0.507508991052970870f, + 0.504863108531267480f, + 0.502212474045710900f, 0.499557112545081890f, 0.496897049022654640f, + 0.494232308515959730f, + 0.491562916106550060f, 0.488888896919763230f, 0.486210276124486530f, + 0.483527078932918740f, + 0.480839330600333900f, 0.478147056424843120f, 0.475450281747155870f, + 0.472749031950342900f, + 0.470043332459595620f, 0.467333208741988530f, 0.464618686306237820f, + 0.461899790702462840f, + 0.459176547521944150f, 0.456448982396883860f, 0.453717121000163930f, + 0.450980989045103810f, + 0.448240612285220000f, 0.445496016513981740f, 0.442747227564570130f, + 0.439994271309633260f, + 0.437237173661044200f, 0.434475960569655710f, 0.431710658025057370f, + 0.428941292055329550f, + 0.426167888726799620f, 0.423390474143796100f, 0.420609074448402510f, + 0.417823715820212380f, + 0.415034424476081630f, 0.412241226669883000f, 0.409444148692257590f, + 0.406643216870369140f, + 0.403838457567654130f, 0.401029897183575790f, 0.398217562153373620f, + 0.395401478947816300f, + 0.392581674072951530f, 0.389758174069856410f, 0.386931005514388690f, + 0.384100195016935040f, + 0.381265769222162490f, 0.378427754808765620f, 0.375586178489217330f, + 0.372741067009515810f, + 0.369892447148934270f, 0.367040345719767240f, 0.364184789567079840f, + 0.361325805568454340f, + 0.358463420633736540f, 0.355597661704783960f, 0.352728555755210730f, + 0.349856129790135030f, + 0.346980410845923680f, 0.344101425989938980f, 0.341219202320282410f, + 0.338333766965541290f, + 0.335445147084531660f, 0.332553369866044220f, 0.329658462528587550f, + 0.326760452320131790f, + 0.323859366517852960f, 0.320955232427875210f, 0.318048077385015060f, + 0.315137928752522440f, + 0.312224813921825050f, 0.309308760312268780f, 0.306389795370861080f, + 0.303467946572011370f, + 0.300543241417273400f, 0.297615707435086310f, 0.294685372180514330f, + 0.291752263234989370f, + 0.288816408206049480f, 0.285877834727080730f, 0.282936570457055390f, + 0.279992643080273380f, + 0.277046080306099950f, 0.274096909868706330f, 0.271145159526808070f, + 0.268190857063403180f, + 0.265234030285511900f, 0.262274707023913590f, 0.259312915132886350f, + 0.256348682489942910f, + 0.253382036995570270f, 0.250413006572965280f, 0.247441619167773440f, + 0.244467902747824210f, + 0.241491885302869300f, 0.238513594844318500f, 0.235533059404975460f, + 0.232550307038775330f, + 0.229565365820518870f, 0.226578263845610110f, 0.223589029229790020f, + 0.220597690108873650f, + 0.217604274638483670f, 0.214608810993786920f, 0.211611327369227610f, + 0.208611851978263460f, + 0.205610413053099320f, 0.202607038844421110f, 0.199601757621131050f, + 0.196594597670080220f, + 0.193585587295803750f, 0.190574754820252800f, 0.187562128582529740f, + 0.184547736938619640f, + 0.181531608261125130f, 0.178513770938997590f, 0.175494253377271400f, + 0.172473083996796030f, + 0.169450291233967930f, 0.166425903540464220f, 0.163399949382973230f, + 0.160372457242928400f, + 0.157343455616238280f, 0.154312973013020240f, 0.151281037957330250f, + 0.148247678986896200f, + 0.145212924652847520f, 0.142176803519448000f, 0.139139344163826280f, + 0.136100575175706200f, + 0.133060525157139180f, 0.130019222722233350f, 0.126976696496885980f, + 0.123932975118512200f, + 0.120888087235777220f, 0.117842061508325020f, 0.114794926606510250f, + 0.111746711211126660f, + 0.108697444013138670f, 0.105647153713410700f, 0.102595869022436280f, + 0.099543618660069444f, + 0.096490431355252607f, 0.093436335845747912f, 0.090381360877865011f, + 0.087325535206192226f, + 0.084268887593324127f, 0.081211446809592386f, 0.078153241632794315f, + 0.075094300847921291f, + 0.072034653246889416f, 0.068974327628266732f, 0.065913352797003930f, + 0.062851757564161420f, + 0.059789570746640007f, 0.056726821166907783f, 0.053663537652730679f, + 0.050599749036899337f, + 0.047535484156959261f, 0.044470771854938744f, 0.041405640977076712f, + 0.038340120373552791f, + 0.035274238898213947f, 0.032208025408304704f, 0.029141508764193740f, + 0.026074717829104040f, + 0.023007681468839410f, 0.019940428551514598f, 0.016872987947281773f, + 0.013805388528060349f, + 0.010737659167264572f, 0.007669828739531077f, 0.004601926120448672f, + 0.001533980186284766f +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048) + const float32_t Weights_2048[4096] = { + 1.000000000000000000f, 0.000000000000000000f, 0.999999705862882230f, -0.000766990318742704f, + 0.999998823451701880f, -0.001533980186284766f, 0.999997352766978210f, -0.002300969151425805f, + 0.999995293809576190f, -0.003067956762965976f, 0.999992646580707190f, -0.003834942569706228f, + 0.999989411081928400f, -0.004601926120448571f, 0.999985587315143200f, -0.005368906963996343f, + 0.999981175282601110f, -0.006135884649154475f, 0.999976174986897610f, -0.006902858724729756f, + 0.999970586430974140f, -0.007669828739531097f, 0.999964409618118280f, -0.008436794242369799f, + 0.999957644551963900f, -0.009203754782059819f, 0.999950291236490480f, -0.009970709907418031f, + 0.999942349676023910f, -0.010737659167264491f, 0.999933819875236000f, -0.011504602110422714f, + 0.999924701839144500f, -0.012271538285719925f, 0.999914995573113470f, -0.013038467241987334f, + 0.999904701082852900f, -0.013805388528060391f, 0.999893818374418490f, -0.014572301692779064f, + 0.999882347454212560f, -0.015339206284988100f, 0.999870288328982950f, -0.016106101853537287f, + 0.999857641005823860f, -0.016872987947281710f, 0.999844405492175240f, -0.017639864115082053f, + 0.999830581795823400f, -0.018406729905804820f, 0.999816169924900410f, -0.019173584868322623f, + 0.999801169887884260f, -0.019940428551514441f, 0.999785581693599210f, -0.020707260504265895f, + 0.999769405351215280f, -0.021474080275469508f, 0.999752640870248840f, -0.022240887414024961f, + 0.999735288260561680f, -0.023007681468839369f, 0.999717347532362190f, -0.023774461988827555f, + 0.999698818696204250f, -0.024541228522912288f, 0.999679701762987930f, -0.025307980620024571f, + 0.999659996743959220f, -0.026074717829103901f, 0.999639703650710200f, -0.026841439699098531f, + 0.999618822495178640f, -0.027608145778965740f, 0.999597353289648380f, -0.028374835617672099f, + 0.999575296046749220f, -0.029141508764193722f, 0.999552650779456990f, -0.029908164767516555f, + 0.999529417501093140f, -0.030674803176636626f, 0.999505596225325310f, -0.031441423540560301f, + 0.999481186966166950f, -0.032208025408304586f, 0.999456189737977340f, -0.032974608328897335f, + 0.999430604555461730f, -0.033741171851377580f, 0.999404431433671300f, -0.034507715524795750f, + 0.999377670388002850f, -0.035274238898213947f, 0.999350321434199440f, -0.036040741520706229f, + 0.999322384588349540f, -0.036807222941358832f, 0.999293859866887790f, -0.037573682709270494f, + 0.999264747286594420f, -0.038340120373552694f, 0.999235046864595850f, -0.039106535483329888f, + 0.999204758618363890f, -0.039872927587739811f, 0.999173882565716380f, -0.040639296235933736f, + 0.999142418724816910f, -0.041405640977076739f, 0.999110367114174890f, -0.042171961360347947f, + 0.999077727752645360f, -0.042938256934940820f, 0.999044500659429290f, -0.043704527250063421f, + 0.999010685854073380f, -0.044470771854938668f, 0.998976283356469820f, -0.045236990298804590f, + 0.998941293186856870f, -0.046003182130914623f, 0.998905715365818290f, -0.046769346900537863f, + 0.998869549914283560f, -0.047535484156959303f, 0.998832796853527990f, -0.048301593449480144f, + 0.998795456205172410f, -0.049067674327418015f, 0.998757527991183340f, -0.049833726340107277f, + 0.998719012233872940f, -0.050599749036899282f, 0.998679908955899090f, -0.051365741967162593f, + 0.998640218180265270f, -0.052131704680283324f, 0.998599939930320370f, -0.052897636725665324f, + 0.998559074229759310f, -0.053663537652730520f, 0.998517621102622210f, -0.054429407010919133f, + 0.998475580573294770f, -0.055195244349689934f, 0.998432952666508440f, -0.055961049218520569f, + 0.998389737407340160f, -0.056726821166907748f, 0.998345934821212370f, -0.057492559744367566f, + 0.998301544933892890f, -0.058258264500435752f, 0.998256567771495180f, -0.059023934984667931f, + 0.998211003360478190f, -0.059789570746639868f, 0.998164851727646240f, -0.060555171335947788f, + 0.998118112900149180f, -0.061320736302208578f, 0.998070786905482340f, -0.062086265195060088f, + 0.998022873771486240f, -0.062851757564161406f, 0.997974373526346990f, -0.063617212959193106f, + 0.997925286198596000f, -0.064382630929857465f, 0.997875611817110150f, -0.065148011025878833f, + 0.997825350411111640f, -0.065913352797003805f, 0.997774502010167820f, -0.066678655793001557f, + 0.997723066644191640f, -0.067443919563664051f, 0.997671044343441000f, -0.068209143658806329f, + 0.997618435138519550f, -0.068974327628266746f, 0.997565239060375750f, -0.069739471021907307f, + 0.997511456140303450f, -0.070504573389613856f, 0.997457086409941910f, -0.071269634281296401f, + 0.997402129901275300f, -0.072034653246889332f, 0.997346586646633230f, -0.072799629836351673f, + 0.997290456678690210f, -0.073564563599667426f, 0.997233740030466280f, -0.074329454086845756f, + 0.997176436735326190f, -0.075094300847921305f, 0.997118546826979980f, -0.075859103432954447f, + 0.997060070339482960f, -0.076623861392031492f, 0.997001007307235290f, -0.077388574275265049f, + 0.996941357764982160f, -0.078153241632794232f, 0.996881121747813850f, -0.078917863014784942f, + 0.996820299291165670f, -0.079682437971430126f, 0.996758890430818000f, -0.080446966052950014f, + 0.996696895202896060f, -0.081211446809592441f, 0.996634313643869900f, -0.081975879791633066f, + 0.996571145790554840f, -0.082740264549375692f, 0.996507391680110820f, -0.083504600633152432f, + 0.996443051350042630f, -0.084268887593324071f, 0.996378124838200210f, -0.085033124980280275f, + 0.996312612182778000f, -0.085797312344439894f, 0.996246513422315520f, -0.086561449236251170f, + 0.996179828595696980f, -0.087325535206192059f, 0.996112557742151130f, -0.088089569804770507f, + 0.996044700901251970f, -0.088853552582524600f, 0.995976258112917790f, -0.089617483090022959f, + 0.995907229417411720f, -0.090381360877864983f, 0.995837614855341610f, -0.091145185496681005f, + 0.995767414467659820f, -0.091908956497132724f, 0.995696628295663520f, -0.092672673429913310f, + 0.995625256380994310f, -0.093436335845747787f, 0.995553298765638470f, -0.094199943295393204f, + 0.995480755491926940f, -0.094963495329638992f, 0.995407626602534900f, -0.095726991499307162f, + 0.995333912140482280f, -0.096490431355252593f, 0.995259612149133390f, -0.097253814448363271f, + 0.995184726672196930f, -0.098017140329560604f, 0.995109255753726110f, -0.098780408549799623f, + 0.995033199438118630f, -0.099543618660069319f, 0.994956557770116380f, -0.100306770211392860f, + 0.994879330794805620f, -0.101069862754827820f, 0.994801518557617110f, -0.101832895841466530f, + 0.994723121104325700f, -0.102595869022436280f, 0.994644138481050710f, -0.103358781848899610f, + 0.994564570734255420f, -0.104121633872054590f, 0.994484417910747600f, -0.104884424643134970f, + 0.994403680057679100f, -0.105647153713410620f, 0.994322357222545810f, -0.106409820634187680f, + 0.994240449453187900f, -0.107172424956808840f, 0.994157956797789730f, -0.107934966232653650f, + 0.994074879304879370f, -0.108697444013138720f, 0.993991217023329380f, -0.109459857849717980f, + 0.993906970002356060f, -0.110222207293883060f, 0.993822138291519660f, -0.110984491897163390f, + 0.993736721940724600f, -0.111746711211126590f, 0.993650721000219120f, -0.112508864787378690f, + 0.993564135520595300f, -0.113270952177564350f, 0.993476965552789190f, -0.114032972933367200f, + 0.993389211148080650f, -0.114794926606510080f, 0.993300872358093280f, -0.115556812748755260f, + 0.993211949234794500f, -0.116318630911904750f, 0.993122441830495580f, -0.117080380647800590f, + 0.993032350197851410f, -0.117842061508324980f, 0.992941674389860470f, -0.118603673045400720f, + 0.992850414459865100f, -0.119365214810991350f, 0.992758570461551140f, -0.120126686357101500f, + 0.992666142448948020f, -0.120888087235777080f, 0.992573130476428810f, -0.121649416999105530f, + 0.992479534598709970f, -0.122410675199216200f, 0.992385354870851670f, -0.123171861388280480f, + 0.992290591348257370f, -0.123932975118512160f, 0.992195244086673920f, -0.124694015942167640f, + 0.992099313142191800f, -0.125454983411546230f, 0.992002798571244520f, -0.126215877078990350f, + 0.991905700430609330f, -0.126976696496885870f, 0.991808018777406430f, -0.127737441217662310f, + 0.991709753669099530f, -0.128498110793793170f, 0.991610905163495370f, -0.129258704777796140f, + 0.991511473318743900f, -0.130019222722233350f, 0.991411458193338540f, -0.130779664179711710f, + 0.991310859846115440f, -0.131540028702883120f, 0.991209678336254060f, -0.132300315844444650f, + 0.991107913723276890f, -0.133060525157139060f, 0.991005566067049370f, -0.133820656193754720f, + 0.990902635427780010f, -0.134580708507126170f, 0.990799121866020370f, -0.135340681650134210f, + 0.990695025442664630f, -0.136100575175706200f, 0.990590346218950150f, -0.136860388636816380f, + 0.990485084256457090f, -0.137620121586486040f, 0.990379239617108160f, -0.138379773577783890f, + 0.990272812363169110f, -0.139139344163826200f, 0.990165802557248400f, -0.139898832897777210f, + 0.990058210262297120f, -0.140658239332849210f, 0.989950035541608990f, -0.141417563022303020f, + 0.989841278458820530f, -0.142176803519448030f, 0.989731939077910570f, -0.142935960377642670f, + 0.989622017463200890f, -0.143695033150294470f, 0.989511513679355190f, -0.144454021390860470f, + 0.989400427791380380f, -0.145212924652847460f, 0.989288759864625170f, -0.145971742489812210f, + 0.989176509964781010f, -0.146730474455361750f, 0.989063678157881540f, -0.147489120103153570f, + 0.988950264510302990f, -0.148247678986896030f, 0.988836269088763540f, -0.149006150660348450f, + 0.988721691960323780f, -0.149764534677321510f, 0.988606533192386450f, -0.150522830591677400f, + 0.988490792852696590f, -0.151281037957330220f, 0.988374471009341280f, -0.152039156328246050f, + 0.988257567730749460f, -0.152797185258443440f, 0.988140083085692570f, -0.153555124301993450f, + 0.988022017143283530f, -0.154312973013020100f, 0.987903369972977790f, -0.155070730945700510f, + 0.987784141644572180f, -0.155828397654265230f, 0.987664332228205710f, -0.156585972692998430f, + 0.987543941794359230f, -0.157343455616238250f, 0.987422970413855410f, -0.158100845978376980f, + 0.987301418157858430f, -0.158858143333861450f, 0.987179285097874340f, -0.159615347237193060f, + 0.987056571305750970f, -0.160372457242928280f, 0.986933276853677710f, -0.161129472905678810f, + 0.986809401814185530f, -0.161886393780111830f, 0.986684946260146690f, -0.162643219420950310f, + 0.986559910264775410f, -0.163399949382973230f, 0.986434293901627180f, -0.164156583221015810f, + 0.986308097244598670f, -0.164913120489969890f, 0.986181320367928270f, -0.165669560744784120f, + 0.986053963346195440f, -0.166425903540464100f, 0.985926026254321130f, -0.167182148432072940f, + 0.985797509167567480f, -0.167938294974731170f, 0.985668412161537550f, -0.168694342723617330f, + 0.985538735312176060f, -0.169450291233967960f, 0.985408478695768420f, -0.170206140061078070f, + 0.985277642388941220f, -0.170961888760301220f, 0.985146226468662230f, -0.171717536887049970f, + 0.985014231012239840f, -0.172473083996795950f, 0.984881656097323700f, -0.173228529645070320f, + 0.984748501801904210f, -0.173983873387463820f, 0.984614768204312600f, -0.174739114779627200f, + 0.984480455383220930f, -0.175494253377271430f, 0.984345563417641900f, -0.176249288736167880f, + 0.984210092386929030f, -0.177004220412148750f, 0.984074042370776450f, -0.177759047961107170f, + 0.983937413449218920f, -0.178513770938997510f, 0.983800205702631600f, -0.179268388901835750f, + 0.983662419211730250f, -0.180022901405699510f, 0.983524054057571260f, -0.180777308006728590f, + 0.983385110321551180f, -0.181531608261124970f, 0.983245588085407070f, -0.182285801725153300f, + 0.983105487431216290f, -0.183039887955140950f, 0.982964808441396440f, -0.183793866507478450f, + 0.982823551198705240f, -0.184547736938619620f, 0.982681715786240860f, -0.185301498805081900f, + 0.982539302287441240f, -0.186055151663446630f, 0.982396310786084690f, -0.186808695070359270f, + 0.982252741366289370f, -0.187562128582529600f, 0.982108594112513610f, -0.188315451756732120f, + 0.981963869109555240f, -0.189068664149806190f, 0.981818566442552500f, -0.189821765318656410f, + 0.981672686196983110f, -0.190574754820252740f, 0.981526228458664770f, -0.191327632211630900f, + 0.981379193313754560f, -0.192080397049892440f, 0.981231580848749730f, -0.192833048892205230f, + 0.981083391150486710f, -0.193585587295803610f, 0.980934624306141640f, -0.194338011817988600f, + 0.980785280403230430f, -0.195090322016128250f, 0.980635359529608120f, -0.195842517447657850f, + 0.980484861773469380f, -0.196594597670080220f, 0.980333787223347960f, -0.197346562240965920f, + 0.980182135968117430f, -0.198098410717953560f, 0.980029908096990090f, -0.198850142658750090f, + 0.979877103699517640f, -0.199601757621130970f, 0.979723722865591170f, -0.200353255162940450f, + 0.979569765685440520f, -0.201104634842091900f, 0.979415232249634780f, -0.201855896216568050f, + 0.979260122649082020f, -0.202607038844421130f, 0.979104436975029250f, -0.203358062283773320f, + 0.978948175319062200f, -0.204108966092816870f, 0.978791337773105670f, -0.204859749829814420f, + 0.978633924429423210f, -0.205610413053099240f, 0.978475935380616830f, -0.206360955321075510f, + 0.978317370719627650f, -0.207111376192218560f, 0.978158230539735050f, -0.207861675225075070f, + 0.977998514934557140f, -0.208611851978263490f, 0.977838223998050430f, -0.209361906010474160f, + 0.977677357824509930f, -0.210111836880469610f, 0.977515916508569280f, -0.210861644147084860f, + 0.977353900145199960f, -0.211611327369227550f, 0.977191308829712280f, -0.212360886105878420f, + 0.977028142657754390f, -0.213110319916091360f, 0.976864401725312640f, -0.213859628358993750f, + 0.976700086128711840f, -0.214608810993786760f, 0.976535195964614470f, -0.215357867379745550f, + 0.976369731330021140f, -0.216106797076219520f, 0.976203692322270560f, -0.216855599642632620f, + 0.976037079039039020f, -0.217604274638483640f, 0.975869891578341030f, -0.218352821623346320f, + 0.975702130038528570f, -0.219101240156869800f, 0.975533794518291360f, -0.219849529798778700f, + 0.975364885116656980f, -0.220597690108873510f, 0.975195401932990370f, -0.221345720647030810f, + 0.975025345066994120f, -0.222093620973203510f, 0.974854714618708430f, -0.222841390647421120f, + 0.974683510688510670f, -0.223589029229789990f, 0.974511733377115720f, -0.224336536280493600f, + 0.974339382785575860f, -0.225083911359792830f, 0.974166459015280320f, -0.225831154028026170f, + 0.973992962167955830f, -0.226578263845610000f, 0.973818892345666100f, -0.227325240373038860f, + 0.973644249650811980f, -0.228072083170885730f, 0.973469034186131070f, -0.228818791799802220f, + 0.973293246054698250f, -0.229565365820518870f, 0.973116885359925130f, -0.230311804793845440f, + 0.972939952205560180f, -0.231058108280671110f, 0.972762446695688570f, -0.231804275841964780f, + 0.972584368934732210f, -0.232550307038775240f, 0.972405719027449770f, -0.233296201432231590f, + 0.972226497078936270f, -0.234041958583543430f, 0.972046703194623500f, -0.234787578054000970f, + 0.971866337480279400f, -0.235533059404975490f, 0.971685400042008540f, -0.236278402197919570f, + 0.971503890986251780f, -0.237023605994367200f, 0.971321810419786160f, -0.237768670355934190f, + 0.971139158449725090f, -0.238513594844318420f, 0.970955935183517970f, -0.239258379021299980f, + 0.970772140728950350f, -0.240003022448741500f, 0.970587775194143630f, -0.240747524688588430f, + 0.970402838687555500f, -0.241491885302869330f, 0.970217331317979160f, -0.242236103853696010f, + 0.970031253194543970f, -0.242980179903263870f, 0.969844604426714830f, -0.243724113013852160f, + 0.969657385124292450f, -0.244467902747824150f, 0.969469595397413060f, -0.245211548667627540f, + 0.969281235356548530f, -0.245955050335794590f, 0.969092305112506210f, -0.246698407314942410f, + 0.968902804776428870f, -0.247441619167773270f, 0.968712734459794780f, -0.248184685457074780f, + 0.968522094274417380f, -0.248927605745720150f, 0.968330884332445190f, -0.249670379596668570f, + 0.968139104746362440f, -0.250413006572965220f, 0.967946755628987800f, -0.251155486237741920f, + 0.967753837093475510f, -0.251897818154216970f, 0.967560349253314360f, -0.252640001885695520f, + 0.967366292222328510f, -0.253382036995570160f, 0.967171666114676640f, -0.254123923047320620f, + 0.966976471044852070f, -0.254865659604514570f, 0.966780707127683270f, -0.255607246230807380f, + 0.966584374478333120f, -0.256348682489942910f, 0.966387473212298900f, -0.257089967945753120f, + 0.966190003445412500f, -0.257831102162158990f, 0.965991965293840570f, + -0.258572084703170340f, + 0.965793358874083680f, -0.259312915132886230f, 0.965594184302976830f, + -0.260053593015495190f, + 0.965394441697689400f, -0.260794117915275510f, 0.965194131175724720f, + -0.261534489396595520f, + 0.964993252854920320f, -0.262274707023913590f, 0.964791806853447900f, + -0.263014770361779000f, + 0.964589793289812760f, -0.263754678974831350f, 0.964387212282854290f, + -0.264494432427801630f, + 0.964184063951745830f, -0.265234030285511790f, 0.963980348415994110f, + -0.265973472112875590f, + 0.963776065795439840f, -0.266712757474898370f, 0.963571216210257320f, + -0.267451885936677620f, + 0.963365799780954050f, -0.268190857063403180f, 0.963159816628371360f, + -0.268929670420357260f, + 0.962953266873683880f, -0.269668325572915090f, 0.962746150638399410f, + -0.270406822086544820f, + 0.962538468044359160f, -0.271145159526808010f, 0.962330219213737400f, + -0.271883337459359720f, + 0.962121404269041580f, -0.272621355449948980f, 0.961912023333112210f, + -0.273359213064418680f, + 0.961702076529122540f, -0.274096909868706380f, 0.961491563980579000f, + -0.274834445428843940f, + 0.961280485811320640f, -0.275571819310958140f, 0.961068842145519350f, + -0.276309031081271080f, + 0.960856633107679660f, -0.277046080306099900f, 0.960643858822638590f, + -0.277782966551857690f, + 0.960430519415565790f, -0.278519689385053060f, 0.960216615011963430f, + -0.279256248372291180f, + 0.960002145737665960f, -0.279992643080273220f, 0.959787111718839900f, + -0.280728873075797190f, + 0.959571513081984520f, -0.281464937925757940f, 0.959355349953930790f, + -0.282200837197147560f, + 0.959138622461841890f, -0.282936570457055390f, 0.958921330733213170f, + -0.283672137272668430f, + 0.958703474895871600f, -0.284407537211271880f, 0.958485055077976100f, + -0.285142769840248670f, + 0.958266071408017670f, -0.285877834727080620f, 0.958046524014818600f, + -0.286612731439347790f, + 0.957826413027532910f, -0.287347459544729510f, 0.957605738575646350f, + -0.288082018611004130f, + 0.957384500788975860f, -0.288816408206049480f, 0.957162699797670210f, + -0.289550627897843030f, + 0.956940335732208820f, -0.290284677254462330f, 0.956717408723403050f, + -0.291018555844085090f, + 0.956493918902395100f, -0.291752263234989260f, 0.956269866400658030f, + -0.292485798995553880f, + 0.956045251349996410f, -0.293219162694258630f, 0.955820073882545420f, + -0.293952353899684660f, + 0.955594334130771110f, -0.294685372180514330f, 0.955368032227470350f, + -0.295418217105532010f, + 0.955141168305770780f, -0.296150888243623790f, 0.954913742499130520f, + -0.296883385163778270f, + 0.954685754941338340f, -0.297615707435086200f, 0.954457205766513490f, + -0.298347854626741400f, + 0.954228095109105670f, -0.299079826308040480f, 0.953998423103894490f, + -0.299811622048383350f, + 0.953768189885990330f, -0.300543241417273450f, 0.953537395590833280f, + -0.301274683984317950f, + 0.953306040354193860f, -0.302005949319228080f, 0.953074124312172200f, + -0.302737036991819140f, + 0.952841647601198720f, -0.303467946572011320f, 0.952608610358033350f, + -0.304198677629829110f, + 0.952375012719765880f, -0.304929229735402370f, 0.952140854823815830f, + -0.305659602458966120f, + 0.951906136807932350f, -0.306389795370860920f, 0.951670858810193860f, + -0.307119808041533100f, + 0.951435020969008340f, -0.307849640041534870f, 0.951198623423113230f, + -0.308579290941525090f, + 0.950961666311575080f, -0.309308760312268730f, 0.950724149773789610f, + -0.310038047724637890f, + 0.950486073949481700f, -0.310767152749611470f, 0.950247438978705230f, + -0.311496074958275910f, + 0.950008245001843000f, -0.312224813921824880f, 0.949768492159606680f, + -0.312953369211560200f, + 0.949528180593036670f, -0.313681740398891520f, 0.949287310443502120f, + -0.314409927055336660f, + 0.949045881852700560f, -0.315137928752522440f, 0.948803894962658490f, + -0.315865745062183960f, + 0.948561349915730270f, -0.316593375556165850f, 0.948318246854599090f, + -0.317320819806421740f, + 0.948074585922276230f, -0.318048077385014950f, 0.947830367262101010f, + -0.318775147864118480f, + 0.947585591017741090f, -0.319502030816015690f, 0.947340257333192050f, + -0.320228725813099860f, + 0.947094366352777220f, -0.320955232427875210f, 0.946847918221148000f, + -0.321681550232956580f, + 0.946600913083283530f, -0.322407678801069850f, 0.946353351084490590f, + -0.323133617705052330f, + 0.946105232370403450f, -0.323859366517852850f, 0.945856557086983910f, + -0.324584924812532150f, + 0.945607325380521280f, -0.325310292162262930f, 0.945357537397632290f, + -0.326035468140330240f, + 0.945107193285260610f, -0.326760452320131730f, 0.944856293190677210f, + -0.327485244275178000f, + 0.944604837261480260f, -0.328209843579092500f, 0.944352825645594750f, + -0.328934249805612200f, + 0.944100258491272660f, -0.329658462528587490f, 0.943847135947092690f, + -0.330382481321982780f, + 0.943593458161960390f, -0.331106305759876430f, 0.943339225285107720f, + -0.331829935416461110f, + 0.943084437466093490f, -0.332553369866044220f, 0.942829094854802710f, + -0.333276608683047930f, + 0.942573197601446870f, -0.333999651442009380f, 0.942316745856563780f, + -0.334722497717581220f, + 0.942059739771017310f, -0.335445147084531600f, 0.941802179495997650f, + -0.336167599117744520f, + 0.941544065183020810f, -0.336889853392220050f, 0.941285396983928660f, + -0.337611909483074620f, + 0.941026175050889260f, -0.338333766965541130f, 0.940766399536396070f, + -0.339055425414969640f, + 0.940506070593268300f, -0.339776884406826850f, 0.940245188374650880f, + -0.340498143516697160f, + 0.939983753034014050f, -0.341219202320282360f, 0.939721764725153340f, + -0.341940060393402190f, + 0.939459223602189920f, -0.342660717311994380f, 0.939196129819569900f, + -0.343381172652115040f, + 0.938932483532064600f, -0.344101425989938810f, 0.938668284894770170f, + -0.344821476901759290f, + 0.938403534063108060f, -0.345541324963989090f, 0.938138231192824360f, + -0.346260969753160010f, + 0.937872376439989890f, -0.346980410845923680f, 0.937605969960999990f, + -0.347699647819051380f, + 0.937339011912574960f, -0.348418680249434560f, 0.937071502451759190f, + -0.349137507714084970f, + 0.936803441735921560f, -0.349856129790134920f, 0.936534829922755500f, + -0.350574546054837510f, + 0.936265667170278260f, -0.351292756085567090f, 0.935995953636831410f, + -0.352010759459819080f, + 0.935725689481080370f, -0.352728555755210730f, 0.935454874862014620f, + -0.353446144549480810f, + 0.935183509938947610f, -0.354163525420490340f, 0.934911594871516090f, + -0.354880697946222790f, + 0.934639129819680780f, -0.355597661704783850f, 0.934366114943725790f, + -0.356314416274402410f, + 0.934092550404258980f, -0.357030961233429980f, 0.933818436362210960f, + -0.357747296160341900f, + 0.933543772978836170f, -0.358463420633736540f, 0.933268560415712050f, + -0.359179334232336500f, + 0.932992798834738960f, -0.359895036534988110f, 0.932716488398140250f, + -0.360610527120662270f, + 0.932439629268462360f, -0.361325805568454280f, 0.932162221608574430f, + -0.362040871457584180f, + 0.931884265581668150f, -0.362755724367397230f, 0.931605761351257830f, + -0.363470363877363760f, + 0.931326709081180430f, -0.364184789567079890f, 0.931047108935595280f, + -0.364899001016267320f, + 0.930766961078983710f, -0.365612997804773850f, 0.930486265676149780f, + -0.366326779512573590f, + 0.930205022892219070f, -0.367040345719767180f, 0.929923232892639670f, + -0.367753696006581980f, + 0.929640895843181330f, -0.368466829953372320f, 0.929358011909935500f, + -0.369179747140620020f, + 0.929074581259315860f, -0.369892447148934100f, 0.928790604058057020f, + -0.370604929559051670f, + 0.928506080473215590f, -0.371317193951837540f, 0.928221010672169440f, + -0.372029239908285010f, + 0.927935394822617890f, -0.372741067009515760f, 0.927649233092581180f, + -0.373452674836780300f, + 0.927362525650401110f, -0.374164062971457930f, 0.927075272664740100f, + -0.374875230995057540f, + 0.926787474304581750f, -0.375586178489217220f, 0.926499130739230510f, + -0.376296905035704790f, + 0.926210242138311380f, -0.377007410216418260f, 0.925920808671770070f, + -0.377717693613385640f, + 0.925630830509872720f, -0.378427754808765560f, 0.925340307823206310f, + -0.379137593384847320f, + 0.925049240782677580f, -0.379847208924051160f, 0.924757629559513910f, + -0.380556601008928520f, + 0.924465474325262600f, -0.381265769222162380f, 0.924172775251791200f, + -0.381974713146567220f, + 0.923879532511286740f, -0.382683432365089780f, 0.923585746276256670f, + -0.383391926460808660f, + 0.923291416719527640f, -0.384100195016935040f, 0.922996544014246250f, + -0.384808237616812880f, + 0.922701128333878630f, -0.385516053843918850f, 0.922405169852209880f, + -0.386223643281862980f, + 0.922108668743345180f, -0.386931005514388580f, 0.921811625181708120f, + -0.387638140125372730f, + 0.921514039342042010f, -0.388345046698826250f, 0.921215911399408730f, + -0.389051724818894380f, + 0.920917241529189520f, -0.389758174069856410f, 0.920618029907083970f, + -0.390464394036126590f, + 0.920318276709110590f, -0.391170384302253870f, 0.920017982111606570f, + -0.391876144452922350f, + 0.919717146291227360f, -0.392581674072951470f, 0.919415769424947070f, + -0.393286972747296400f, + 0.919113851690057770f, -0.393992040061048100f, 0.918811393264170050f, + -0.394696875599433560f, + 0.918508394325212250f, -0.395401478947816350f, 0.918204855051430900f, + -0.396105849691696270f, + 0.917900775621390500f, -0.396809987416710310f, 0.917596156213972950f, + -0.397513891708632330f, + 0.917290997008377910f, -0.398217562153373560f, 0.916985298184123000f, + -0.398920998336982910f, + 0.916679059921042700f, -0.399624199845646790f, 0.916372282399289140f, + -0.400327166265690090f, + 0.916064965799331720f, -0.401029897183575620f, 0.915757110301956720f, + -0.401732392185905010f, + 0.915448716088267830f, -0.402434650859418430f, 0.915139783339685260f, + -0.403136672790995300f, + 0.914830312237946200f, -0.403838457567654070f, 0.914520302965104450f, + -0.404540004776553000f, + 0.914209755703530690f, -0.405241314004989860f, 0.913898670635911680f, + -0.405942384840402510f, + 0.913587047945250810f, -0.406643216870369030f, 0.913274887814867760f, + -0.407343809682607970f, + 0.912962190428398210f, -0.408044162864978690f, 0.912648955969793900f, + -0.408744276005481360f, + 0.912335184623322750f, -0.409444148692257590f, 0.912020876573568340f, + -0.410143780513590240f, + 0.911706032005429880f, -0.410843171057903910f, 0.911390651104122430f, + -0.411542319913765220f, + 0.911074734055176360f, -0.412241226669882890f, 0.910758281044437570f, + -0.412939890915108080f, + 0.910441292258067250f, -0.413638312238434500f, 0.910123767882541680f, + -0.414336490228999100f, + 0.909805708104652220f, -0.415034424476081630f, 0.909487113111505430f, + -0.415732114569105360f, + 0.909167983090522380f, -0.416429560097637150f, 0.908848318229439120f, + -0.417126760651387870f, + 0.908528118716306120f, -0.417823715820212270f, 0.908207384739488700f, + -0.418520425194109700f, + 0.907886116487666260f, -0.419216888363223910f, 0.907564314149832630f, + -0.419913104917843620f, + 0.907241977915295820f, -0.420609074448402510f, 0.906919107973678140f, + -0.421304796545479640f, + 0.906595704514915330f, -0.422000270799799680f, 0.906271767729257660f, + -0.422695496802232950f, + 0.905947297807268460f, -0.423390474143796050f, 0.905622294939825270f, + -0.424085202415651560f, + 0.905296759318118820f, -0.424779681209108810f, 0.904970691133653250f, + -0.425473910115623800f, + 0.904644090578246240f, -0.426167888726799620f, 0.904316957844028320f, + -0.426861616634386430f, + 0.903989293123443340f, -0.427555093430282080f, 0.903661096609247980f, + -0.428248318706531960f, + 0.903332368494511820f, -0.428941292055329490f, 0.903003108972617150f, + -0.429634013069016380f, + 0.902673318237258830f, -0.430326481340082610f, 0.902342996482444200f, + -0.431018696461167030f, + 0.902012143902493180f, -0.431710658025057260f, 0.901680760692037730f, + -0.432402365624690140f, + 0.901348847046022030f, -0.433093818853151960f, 0.901016403159702330f, + -0.433785017303678520f, + 0.900683429228646970f, -0.434475960569655650f, 0.900349925448735600f, + -0.435166648244619260f, + 0.900015892016160280f, -0.435857079922255470f, 0.899681329127423930f, + -0.436547255196401200f, + 0.899346236979341570f, -0.437237173661044090f, 0.899010615769039070f, + -0.437926834910322860f, + 0.898674465693953820f, -0.438616238538527660f, 0.898337786951834310f, + -0.439305384140099950f, + 0.898000579740739880f, -0.439994271309633260f, 0.897662844259040860f, + -0.440682899641872900f, + 0.897324580705418320f, -0.441371268731716670f, 0.896985789278863970f, + -0.442059378174214700f, + 0.896646470178680150f, -0.442747227564570020f, 0.896306623604479550f, + -0.443434816498138480f, + 0.895966249756185220f, -0.444122144570429200f, 0.895625348834030110f, + -0.444809211377104880f, + 0.895283921038557580f, -0.445496016513981740f, 0.894941966570620750f, + -0.446182559577030070f, + 0.894599485631382700f, -0.446868840162374160f, 0.894256478422316040f, + -0.447554857866293010f, + 0.893912945145203250f, -0.448240612285219890f, 0.893568886002135910f, + -0.448926103015743260f, + 0.893224301195515320f, -0.449611329654606540f, 0.892879190928051680f, + -0.450296291798708610f, + 0.892533555402764580f, -0.450980989045103860f, 0.892187394822982480f, + -0.451665420991002490f, + 0.891840709392342720f, -0.452349587233770890f, 0.891493499314791380f, + -0.453033487370931580f, + 0.891145764794583180f, -0.453717121000163870f, 0.890797506036281490f, + -0.454400487719303580f, + 0.890448723244757880f, -0.455083587126343840f, 0.890099416625192320f, + -0.455766418819434640f, + 0.889749586383072780f, -0.456448982396883920f, 0.889399232724195520f, + -0.457131277457156980f, + 0.889048355854664570f, -0.457813303598877170f, 0.888696955980891600f, + -0.458495060420826270f, + 0.888345033309596350f, -0.459176547521944090f, 0.887992588047805560f, + -0.459857764501329540f, + 0.887639620402853930f, -0.460538710958240010f, 0.887286130582383150f, + -0.461219386492092380f, + 0.886932118794342190f, -0.461899790702462730f, 0.886577585246987040f, + -0.462579923189086810f, + 0.886222530148880640f, -0.463259783551860150f, 0.885866953708892790f, + -0.463939371390838520f, + 0.885510856136199950f, -0.464618686306237820f, 0.885154237640285110f, + -0.465297727898434600f, + 0.884797098430937790f, -0.465976495767966180f, 0.884439438718253810f, + -0.466654989515530920f, + 0.884081258712634990f, -0.467333208741988420f, 0.883722558624789660f, + -0.468011153048359830f, + 0.883363338665731580f, -0.468688822035827900f, 0.883003599046780830f, + -0.469366215305737520f, + 0.882643339979562790f, -0.470043332459595620f, 0.882282561676008710f, + -0.470720173099071600f, + 0.881921264348355050f, -0.471396736825997640f, 0.881559448209143780f, + -0.472073023242368660f, + 0.881197113471222090f, -0.472749031950342790f, 0.880834260347742040f, + -0.473424762552241530f, + 0.880470889052160750f, -0.474100214650549970f, 0.880106999798240360f, + -0.474775387847917120f, + 0.879742592800047410f, -0.475450281747155870f, 0.879377668271953290f, + -0.476124895951243580f, + 0.879012226428633530f, -0.476799230063322090f, 0.878646267485068130f, + -0.477473283686698060f, + 0.878279791656541580f, -0.478147056424843010f, 0.877912799158641840f, + -0.478820547881393890f, + 0.877545290207261350f, -0.479493757660153010f, 0.877177265018595940f, + -0.480166685365088390f, + 0.876808723809145650f, -0.480839330600333960f, 0.876439666795713610f, + -0.481511692970189860f, + 0.876070094195406600f, -0.482183772079122720f, 0.875700006225634600f, + -0.482855567531765670f, + 0.875329403104110890f, -0.483527078932918740f, 0.874958285048851650f, + -0.484198305887549030f, + 0.874586652278176110f, -0.484869248000791060f, 0.874214505010706300f, + -0.485539904877946960f, + 0.873841843465366860f, -0.486210276124486420f, 0.873468667861384880f, + -0.486880361346047340f, + 0.873094978418290090f, -0.487550160148436000f, 0.872720775355914300f, + -0.488219672137626790f, + 0.872346058894391540f, -0.488888896919763170f, 0.871970829254157810f, + -0.489557834101157440f, + 0.871595086655950980f, -0.490226483288291160f, 0.871218831320811020f, + -0.490894844087815090f, + 0.870842063470078980f, -0.491562916106549900f, 0.870464783325397670f, + -0.492230698951486020f, + 0.870086991108711460f, -0.492898192229784040f, 0.869708687042265670f, + -0.493565395548774770f, + 0.869329871348606840f, -0.494232308515959670f, 0.868950544250582380f, + -0.494898930739011260f, + 0.868570705971340900f, -0.495565261825772540f, 0.868190356734331310f, + -0.496231301384258250f, + 0.867809496763303320f, -0.496897049022654470f, 0.867428126282306920f, + -0.497562504349319150f, + 0.867046245515692650f, -0.498227666972781870f, 0.866663854688111130f, + -0.498892536501744590f, + 0.866280954024512990f, -0.499557112545081840f, 0.865897543750148820f, + -0.500221394711840680f, + 0.865513624090569090f, -0.500885382611240710f, 0.865129195271623800f, + -0.501549075852675390f, + 0.864744257519462380f, -0.502212474045710790f, 0.864358811060534030f, + -0.502875576800086990f, + 0.863972856121586810f, -0.503538383725717580f, 0.863586392929668100f, + -0.504200894432690340f, + 0.863199421712124160f, -0.504863108531267590f, 0.862811942696600330f, + -0.505525025631885390f, + 0.862423956111040610f, -0.506186645345155230f, 0.862035462183687210f, + -0.506847967281863210f, + 0.861646461143081300f, -0.507508991052970870f, 0.861256953218062170f, + -0.508169716269614600f, + 0.860866938637767310f, -0.508830142543106990f, 0.860476417631632070f, + -0.509490269484936360f, + 0.860085390429390140f, -0.510150096706766810f, 0.859693857261072610f, + -0.510809623820439040f, + 0.859301818357008470f, -0.511468850437970300f, 0.858909273947823900f, + -0.512127776171554690f, + 0.858516224264442740f, -0.512786400633562960f, 0.858122669538086140f, + -0.513444723436543460f, + 0.857728610000272120f, -0.514102744193221660f, 0.857334045882815590f, + -0.514760462516501200f, + 0.856938977417828760f, -0.515417878019462930f, 0.856543404837719960f, + -0.516074990315366630f, + 0.856147328375194470f, -0.516731799017649870f, 0.855750748263253920f, + -0.517388303739929060f, + 0.855353664735196030f, -0.518044504095999340f, 0.854956078024614930f, + -0.518700399699834950f, + 0.854557988365400530f, -0.519355990165589640f, 0.854159395991738850f, + -0.520011275107596040f, + 0.853760301138111410f, -0.520666254140367160f, 0.853360704039295430f, + -0.521320926878595660f, + 0.852960604930363630f, -0.521975292937154390f, 0.852560004046684080f, + -0.522629351931096610f, + 0.852158901623919830f, -0.523283103475656430f, 0.851757297898029120f, + -0.523936547186248600f, + 0.851355193105265200f, -0.524589682678468950f, 0.850952587482175730f, + -0.525242509568094710f, + 0.850549481265603480f, -0.525895027471084630f, 0.850145874692685210f, + -0.526547236003579440f, + 0.849741768000852550f, -0.527199134781901280f, 0.849337161427830780f, + -0.527850723422555230f, + 0.848932055211639610f, -0.528502001542228480f, 0.848526449590592650f, + -0.529152968757790610f, + 0.848120344803297230f, -0.529803624686294610f, 0.847713741088654380f, + -0.530453968944976320f, + 0.847306638685858320f, -0.531104001151255000f, 0.846899037834397240f, + -0.531753720922733320f, + 0.846490938774052130f, -0.532403127877197900f, 0.846082341744897050f, + -0.533052221632619450f, + 0.845673246987299070f, -0.533701001807152960f, 0.845263654741918220f, + -0.534349468019137520f, + 0.844853565249707120f, -0.534997619887097150f, 0.844442978751910660f, + -0.535645457029741090f, + 0.844031895490066410f, -0.536292979065963180f, 0.843620315706004150f, + -0.536940185614842910f, + 0.843208239641845440f, -0.537587076295645390f, 0.842795667540004120f, + -0.538233650727821700f, + 0.842382599643185850f, -0.538879908531008420f, 0.841969036194387680f, + -0.539525849325028890f, + 0.841554977436898440f, -0.540171472729892850f, 0.841140423614298080f, + -0.540816778365796670f, + 0.840725374970458070f, -0.541461765853123440f, 0.840309831749540770f, + -0.542106434812443920f, + 0.839893794195999520f, -0.542750784864515890f, 0.839477262554578550f, + -0.543394815630284800f, + 0.839060237070312740f, -0.544038526730883820f, 0.838642717988527300f, + -0.544681917787634530f, + 0.838224705554838080f, -0.545324988422046460f, 0.837806200015150940f, + -0.545967738255817570f, + 0.837387201615661940f, -0.546610166910834860f, 0.836967710602857020f, + -0.547252274009174090f, + 0.836547727223512010f, -0.547894059173100190f, 0.836127251724692270f, + -0.548535522025067390f, + 0.835706284353752600f, -0.549176662187719660f, 0.835284825358337370f, + -0.549817479283890910f, + 0.834862874986380010f, -0.550457972936604810f, 0.834440433486103190f, + -0.551098142769075430f, + 0.834017501106018130f, -0.551737988404707340f, 0.833594078094925140f, + -0.552377509467096070f, + 0.833170164701913190f, -0.553016705580027470f, 0.832745761176359460f, + -0.553655576367479310f, + 0.832320867767929680f, -0.554294121453620000f, 0.831895484726577590f, + -0.554932340462810370f, + 0.831469612302545240f, -0.555570233019602180f, 0.831043250746362320f, + -0.556207798748739930f, + 0.830616400308846310f, -0.556845037275160100f, 0.830189061241102370f, + -0.557481948223991550f, + 0.829761233794523050f, -0.558118531220556100f, 0.829332918220788250f, + -0.558754785890368310f, + 0.828904114771864870f, -0.559390711859136140f, 0.828474823700007130f, + -0.560026308752760380f, + 0.828045045257755800f, -0.560661576197336030f, 0.827614779697938400f, + -0.561296513819151470f, + 0.827184027273669130f, -0.561931121244689470f, 0.826752788238348520f, + -0.562565398100626560f, + 0.826321062845663530f, -0.563199344013834090f, 0.825888851349586780f, + -0.563832958611378170f, + 0.825456154004377550f, -0.564466241520519500f, 0.825022971064580220f, + -0.565099192368713980f, + 0.824589302785025290f, -0.565731810783613120f, 0.824155149420828570f, + -0.566364096393063840f, + 0.823720511227391430f, -0.566996048825108680f, 0.823285388460400110f, + -0.567627667707986230f, + 0.822849781375826430f, -0.568258952670131490f, 0.822413690229926390f, + -0.568889903340175860f, + 0.821977115279241550f, -0.569520519346947140f, 0.821540056780597610f, + -0.570150800319470300f, + 0.821102514991104650f, -0.570780745886967260f, 0.820664490168157460f, + -0.571410355678857230f, + 0.820225982569434690f, -0.572039629324757050f, 0.819786992452898990f, + -0.572668566454481160f, + 0.819347520076796900f, -0.573297166698042200f, 0.818907565699658950f, + -0.573925429685650750f, + 0.818467129580298660f, -0.574553355047715760f, 0.818026211977813440f, + -0.575180942414845080f, + 0.817584813151583710f, -0.575808191417845340f, 0.817142933361272970f, + -0.576435101687721830f, + 0.816700572866827850f, -0.577061672855679440f, 0.816257731928477390f, + -0.577687904553122800f, + 0.815814410806733780f, -0.578313796411655590f, 0.815370609762391290f, + -0.578939348063081780f, + 0.814926329056526620f, -0.579564559139405630f, 0.814481568950498610f, + -0.580189429272831680f, + 0.814036329705948410f, -0.580813958095764530f, 0.813590611584798510f, + -0.581438145240810170f, + 0.813144414849253590f, -0.582061990340775440f, 0.812697739761799490f, + -0.582685493028668460f, + 0.812250586585203880f, -0.583308652937698290f, 0.811802955582515470f, + -0.583931469701276180f, + 0.811354847017063730f, -0.584553942953015330f, 0.810906261152459670f, + -0.585176072326730410f, + 0.810457198252594770f, -0.585797857456438860f, 0.810007658581641140f, + -0.586419297976360500f, + 0.809557642404051260f, -0.587040393520917970f, 0.809107149984558240f, + -0.587661143724736660f, + 0.808656181588174980f, -0.588281548222645220f, 0.808204737480194720f, + -0.588901606649675720f, + 0.807752817926190360f, -0.589521318641063940f, 0.807300423192014450f, + -0.590140683832248820f, + 0.806847553543799330f, -0.590759701858874160f, 0.806394209247956240f, + -0.591378372356787580f, + 0.805940390571176280f, -0.591996694962040990f, 0.805486097780429230f, + -0.592614669310891130f, + 0.805031331142963660f, -0.593232295039799800f, 0.804576090926307110f, + -0.593849571785433630f, + 0.804120377398265810f, -0.594466499184664430f, 0.803664190826924090f, + -0.595083076874569960f, + 0.803207531480644940f, -0.595699304492433360f, 0.802750399628069160f, + -0.596315181675743710f, + 0.802292795538115720f, -0.596930708062196500f, 0.801834719479981310f, + -0.597545883289693160f, + 0.801376171723140240f, -0.598160706996342270f, 0.800917152537344300f, + -0.598775178820458720f, + 0.800457662192622820f, -0.599389298400564540f, 0.799997700959281910f, + -0.600003065375388940f, + 0.799537269107905010f, -0.600616479383868970f, 0.799076366909352350f, + -0.601229540065148500f, + 0.798614994634760820f, -0.601842247058580030f, 0.798153152555543750f, + -0.602454600003723750f, + 0.797690840943391160f, -0.603066598540348160f, 0.797228060070268810f, + -0.603678242308430370f, + 0.796764810208418830f, -0.604289530948155960f, 0.796301091630359110f, + -0.604900464099919820f, + 0.795836904608883570f, -0.605511041404325550f, 0.795372249417061310f, + -0.606121262502186120f, + 0.794907126328237010f, -0.606731127034524480f, 0.794441535616030590f, + -0.607340634642572930f, + 0.793975477554337170f, -0.607949784967773630f, 0.793508952417326660f, + -0.608558577651779450f, + 0.793041960479443640f, -0.609167012336453210f, 0.792574502015407690f, + -0.609775088663868430f, + 0.792106577300212390f, -0.610382806276309480f, 0.791638186609125880f, + -0.610990164816271660f, + 0.791169330217690200f, -0.611597163926461910f, 0.790700008401721610f, + -0.612203803249797950f, + 0.790230221437310030f, -0.612810082429409710f, 0.789759969600819070f, + -0.613416001108638590f, + 0.789289253168885650f, -0.614021558931038380f, 0.788818072418420280f, + -0.614626755540375050f, + 0.788346427626606340f, -0.615231590580626820f, 0.787874319070900220f, + -0.615836063695985090f, + 0.787401747029031430f, -0.616440174530853650f, 0.786928711779001810f, + -0.617043922729849760f, + 0.786455213599085770f, -0.617647307937803870f, 0.785981252767830150f, + -0.618250329799760250f, + 0.785506829564053930f, -0.618852987960976320f, 0.785031944266848080f, + -0.619455282066924020f, + 0.784556597155575240f, -0.620057211763289100f, 0.784080788509869950f, + -0.620658776695972140f, + 0.783604518609638200f, -0.621259976511087550f, 0.783127787735057310f, + -0.621860810854965360f, + 0.782650596166575730f, -0.622461279374149970f, 0.782172944184913010f, + -0.623061381715401260f, + 0.781694832071059390f, -0.623661117525694530f, 0.781216260106276090f, + -0.624260486452220650f, + 0.780737228572094490f, -0.624859488142386340f, 0.780257737750316590f, + -0.625458122243814360f, + 0.779777787923014550f, -0.626056388404343520f, 0.779297379372530300f, + -0.626654286272029350f, + 0.778816512381475980f, -0.627251815495144080f, 0.778335187232733210f, + -0.627848975722176460f, + 0.777853404209453150f, -0.628445766601832710f, 0.777371163595056310f, + -0.629042187783036000f, + 0.776888465673232440f, -0.629638238914926980f, 0.776405310727940390f, + -0.630233919646864370f, + 0.775921699043407690f, -0.630829229628424470f, 0.775437630904130540f, + -0.631424168509401860f, + 0.774953106594873930f, -0.632018735939809060f, 0.774468126400670860f, + -0.632612931569877410f, + 0.773982690606822900f, -0.633206755050057190f, 0.773496799498899050f, + -0.633800206031017280f, + 0.773010453362736990f, -0.634393284163645490f, 0.772523652484441330f, + -0.634985989099049460f, + 0.772036397150384520f, -0.635578320488556110f, 0.771548687647206300f, + -0.636170277983712170f, + 0.771060524261813820f, -0.636761861236284200f, 0.770571907281380810f, + -0.637353069898259130f, + 0.770082836993347900f, -0.637943903621844060f, 0.769593313685422940f, + -0.638534362059466790f, + 0.769103337645579700f, -0.639124444863775730f, 0.768612909162058380f, + -0.639714151687640450f, + 0.768122028523365420f, -0.640303482184151670f, 0.767630696018273380f, + -0.640892436006621380f, + 0.767138911935820400f, -0.641481012808583160f, 0.766646676565310380f, + -0.642069212243792540f, + 0.766153990196312920f, -0.642657033966226860f, 0.765660853118662500f, + -0.643244477630085850f, + 0.765167265622458960f, -0.643831542889791390f, 0.764673227998067140f, + -0.644418229399988380f, + 0.764178740536116670f, -0.645004536815543930f, 0.763683803527501870f, + -0.645590464791548690f, + 0.763188417263381270f, -0.646176012983316280f, 0.762692582035177980f, + -0.646761181046383920f, + 0.762196298134578900f, -0.647345968636512060f, 0.761699565853535380f, + -0.647930375409685340f, + 0.761202385484261780f, -0.648514401022112440f, 0.760704757319236920f, + -0.649098045130225950f, + 0.760206681651202420f, -0.649681307390683190f, 0.759708158773163440f, + -0.650264187460365850f, + 0.759209188978388070f, -0.650846684996380880f, 0.758709772560407390f, + -0.651428799656059820f, + 0.758209909813015280f, -0.652010531096959500f, 0.757709601030268080f, + -0.652591878976862440f, + 0.757208846506484570f, -0.653172842953776760f, 0.756707646536245670f, + -0.653753422685936060f, + 0.756206001414394540f, -0.654333617831800440f, 0.755703911436035880f, + -0.654913428050056030f, + 0.755201376896536550f, -0.655492852999615350f, 0.754698398091524500f, + -0.656071892339617600f, + 0.754194975316889170f, -0.656650545729428940f, 0.753691108868781210f, + -0.657228812828642540f, + 0.753186799043612520f, -0.657806693297078640f, 0.752682046138055340f, + -0.658384186794785050f, + 0.752176850449042810f, -0.658961292982037320f, 0.751671212273768430f, + -0.659538011519338660f, + 0.751165131909686480f, -0.660114342067420480f, 0.750658609654510700f, + -0.660690284287242300f, + 0.750151645806215070f, -0.661265837839992270f, 0.749644240663033480f, + -0.661841002387086870f, + 0.749136394523459370f, -0.662415777590171780f, 0.748628107686245440f, + -0.662990163111121470f, + 0.748119380450403600f, -0.663564158612039770f, 0.747610213115205150f, + -0.664137763755260010f, + 0.747100605980180130f, -0.664710978203344790f, 0.746590559345117310f, + -0.665283801619087180f, + 0.746080073510063780f, -0.665856233665509720f, 0.745569148775325430f, + -0.666428274005865240f, + 0.745057785441466060f, -0.666999922303637470f, 0.744545983809307370f, + -0.667571178222540310f, + 0.744033744179929290f, -0.668142041426518450f, 0.743521066854669120f, + -0.668712511579747980f, + 0.743007952135121720f, -0.669282588346636010f, 0.742494400323139180f, + -0.669852271391821020f, + 0.741980411720831070f, -0.670421560380173090f, 0.741465986630563290f, + -0.670990454976794220f, + 0.740951125354959110f, -0.671558954847018330f, 0.740435828196898020f, + -0.672127059656411730f, + 0.739920095459516200f, -0.672694769070772860f, 0.739403927446205760f, + -0.673262082756132970f, + 0.738887324460615110f, -0.673829000378756040f, 0.738370286806648620f, + -0.674395521605139050f, + 0.737852814788465980f, -0.674961646102011930f, 0.737334908710482910f, + -0.675527373536338520f, + 0.736816568877369900f, -0.676092703575315920f, 0.736297795594053170f, + -0.676657635886374950f, + 0.735778589165713590f, -0.677222170137180330f, 0.735258949897786840f, + -0.677786305995631500f, + 0.734738878095963500f, -0.678350043129861470f, 0.734218374066188280f, + -0.678913381208238410f, + 0.733697438114660370f, -0.679476319899364970f, 0.733176070547832740f, + -0.680038858872078930f, + 0.732654271672412820f, -0.680600997795453020f, 0.732132041795361290f, + -0.681162736338795430f, + 0.731609381223892630f, -0.681724074171649710f, 0.731086290265474340f, + -0.682285010963795570f, + 0.730562769227827590f, -0.682845546385248080f, 0.730038818418926260f, + -0.683405680106258680f, + 0.729514438146997010f, -0.683965411797315400f, 0.728989628720519420f, + -0.684524741129142300f, + 0.728464390448225200f, -0.685083667772700360f, 0.727938723639098620f, + -0.685642191399187470f, + 0.727412628602375770f, -0.686200311680038590f, 0.726886105647544970f, + -0.686758028286925890f, + 0.726359155084346010f, -0.687315340891759050f, 0.725831777222770370f, + -0.687872249166685550f, + 0.725303972373060770f, -0.688428752784090440f, 0.724775740845711280f, + -0.688984851416597040f, + 0.724247082951467000f, -0.689540544737066830f, 0.723717999001323500f, + -0.690095832418599950f, + 0.723188489306527460f, -0.690650714134534600f, 0.722658554178575610f, + -0.691205189558448450f, + 0.722128193929215350f, -0.691759258364157750f, 0.721597408870443770f, + -0.692312920225718220f, + 0.721066199314508110f, -0.692866174817424630f, 0.720534565573905270f, + -0.693419021813811760f, + 0.720002507961381650f, -0.693971460889654000f, 0.719470026789932990f, + -0.694523491719965520f, + 0.718937122372804490f, -0.695075113980000880f, 0.718403795023489830f, + -0.695626327345254870f, + 0.717870045055731710f, -0.696177131491462990f, 0.717335872783521730f, + -0.696727526094601200f, + 0.716801278521099540f, -0.697277510830886520f, 0.716266262582953120f, + -0.697827085376777290f, + 0.715730825283818590f, -0.698376249408972920f, 0.715194966938680120f, + -0.698925002604414150f, + 0.714658687862769090f, -0.699473344640283770f, 0.714121988371564820f, + -0.700021275194006250f, + 0.713584868780793640f, -0.700568793943248340f, 0.713047329406429340f, + -0.701115900565918660f, + 0.712509370564692320f, -0.701662594740168450f, 0.711970992572050100f, + -0.702208876144391870f, + 0.711432195745216430f, -0.702754744457225300f, 0.710892980401151680f, + -0.703300199357548730f, + 0.710353346857062420f, -0.703845240524484940f, 0.709813295430400840f, + -0.704389867637400410f, + 0.709272826438865690f, -0.704934080375904880f, 0.708731940200400650f, + -0.705477878419852100f, + 0.708190637033195400f, -0.706021261449339740f, 0.707648917255684350f, + -0.706564229144709510f, + 0.707106781186547570f, -0.707106781186547460f, 0.706564229144709620f, + -0.707648917255684350f, + 0.706021261449339740f, -0.708190637033195290f, 0.705477878419852210f, + -0.708731940200400650f, + 0.704934080375904990f, -0.709272826438865580f, 0.704389867637400410f, + -0.709813295430400840f, + 0.703845240524484940f, -0.710353346857062310f, 0.703300199357548730f, + -0.710892980401151680f, + 0.702754744457225300f, -0.711432195745216430f, 0.702208876144391870f, + -0.711970992572049990f, + 0.701662594740168570f, -0.712509370564692320f, 0.701115900565918660f, + -0.713047329406429230f, + 0.700568793943248450f, -0.713584868780793520f, 0.700021275194006360f, + -0.714121988371564710f, + 0.699473344640283770f, -0.714658687862768980f, 0.698925002604414150f, + -0.715194966938680010f, + 0.698376249408972920f, -0.715730825283818590f, 0.697827085376777290f, + -0.716266262582953120f, + 0.697277510830886630f, -0.716801278521099540f, 0.696727526094601200f, + -0.717335872783521730f, + 0.696177131491462990f, -0.717870045055731710f, 0.695626327345254870f, + -0.718403795023489720f, + 0.695075113980000880f, -0.718937122372804380f, 0.694523491719965520f, + -0.719470026789932990f, + 0.693971460889654000f, -0.720002507961381650f, 0.693419021813811880f, + -0.720534565573905270f, + 0.692866174817424740f, -0.721066199314508110f, 0.692312920225718220f, + -0.721597408870443660f, + 0.691759258364157750f, -0.722128193929215350f, 0.691205189558448450f, + -0.722658554178575610f, + 0.690650714134534720f, -0.723188489306527350f, 0.690095832418599950f, + -0.723717999001323390f, + 0.689540544737066940f, -0.724247082951466890f, 0.688984851416597150f, + -0.724775740845711280f, + 0.688428752784090550f, -0.725303972373060660f, 0.687872249166685550f, + -0.725831777222770370f, + 0.687315340891759160f, -0.726359155084346010f, 0.686758028286925890f, + -0.726886105647544970f, + 0.686200311680038700f, -0.727412628602375770f, 0.685642191399187470f, + -0.727938723639098620f, + 0.685083667772700360f, -0.728464390448225200f, 0.684524741129142300f, + -0.728989628720519310f, + 0.683965411797315510f, -0.729514438146996900f, 0.683405680106258790f, + -0.730038818418926150f, + 0.682845546385248080f, -0.730562769227827590f, 0.682285010963795570f, + -0.731086290265474230f, + 0.681724074171649820f, -0.731609381223892520f, 0.681162736338795430f, + -0.732132041795361290f, + 0.680600997795453130f, -0.732654271672412820f, 0.680038858872079040f, + -0.733176070547832740f, + 0.679476319899365080f, -0.733697438114660260f, 0.678913381208238410f, + -0.734218374066188170f, + 0.678350043129861580f, -0.734738878095963390f, 0.677786305995631500f, + -0.735258949897786730f, + 0.677222170137180450f, -0.735778589165713480f, 0.676657635886374950f, + -0.736297795594053060f, + 0.676092703575316030f, -0.736816568877369790f, 0.675527373536338630f, + -0.737334908710482790f, + 0.674961646102012040f, -0.737852814788465980f, 0.674395521605139050f, + -0.738370286806648510f, + 0.673829000378756150f, -0.738887324460615110f, 0.673262082756132970f, + -0.739403927446205760f, + 0.672694769070772970f, -0.739920095459516090f, 0.672127059656411840f, + -0.740435828196898020f, + 0.671558954847018330f, -0.740951125354959110f, 0.670990454976794220f, + -0.741465986630563290f, + 0.670421560380173090f, -0.741980411720830960f, 0.669852271391821130f, + -0.742494400323139180f, + 0.669282588346636010f, -0.743007952135121720f, 0.668712511579748090f, + -0.743521066854669120f, + 0.668142041426518560f, -0.744033744179929180f, 0.667571178222540310f, + -0.744545983809307250f, + 0.666999922303637470f, -0.745057785441465950f, 0.666428274005865350f, + -0.745569148775325430f, + 0.665856233665509720f, -0.746080073510063780f, 0.665283801619087180f, + -0.746590559345117310f, + 0.664710978203344900f, -0.747100605980180130f, 0.664137763755260010f, + -0.747610213115205150f, + 0.663564158612039880f, -0.748119380450403490f, 0.662990163111121470f, + -0.748628107686245330f, + 0.662415777590171780f, -0.749136394523459260f, 0.661841002387086870f, + -0.749644240663033480f, + 0.661265837839992270f, -0.750151645806214960f, 0.660690284287242300f, + -0.750658609654510590f, + 0.660114342067420480f, -0.751165131909686370f, 0.659538011519338770f, + -0.751671212273768430f, + 0.658961292982037320f, -0.752176850449042700f, 0.658384186794785050f, + -0.752682046138055230f, + 0.657806693297078640f, -0.753186799043612410f, 0.657228812828642650f, + -0.753691108868781210f, + 0.656650545729429050f, -0.754194975316889170f, 0.656071892339617710f, + -0.754698398091524390f, + 0.655492852999615460f, -0.755201376896536550f, 0.654913428050056150f, + -0.755703911436035880f, + 0.654333617831800550f, -0.756206001414394540f, 0.653753422685936170f, + -0.756707646536245670f, + 0.653172842953776760f, -0.757208846506484460f, 0.652591878976862550f, + -0.757709601030268080f, + 0.652010531096959500f, -0.758209909813015280f, 0.651428799656059820f, + -0.758709772560407390f, + 0.650846684996380990f, -0.759209188978387960f, 0.650264187460365960f, + -0.759708158773163440f, + 0.649681307390683190f, -0.760206681651202420f, 0.649098045130226060f, + -0.760704757319236920f, + 0.648514401022112550f, -0.761202385484261780f, 0.647930375409685460f, + -0.761699565853535270f, + 0.647345968636512060f, -0.762196298134578900f, 0.646761181046383920f, + -0.762692582035177870f, + 0.646176012983316390f, -0.763188417263381270f, 0.645590464791548800f, + -0.763683803527501870f, + 0.645004536815544040f, -0.764178740536116670f, 0.644418229399988380f, + -0.764673227998067140f, + 0.643831542889791500f, -0.765167265622458960f, 0.643244477630085850f, + -0.765660853118662390f, + 0.642657033966226860f, -0.766153990196312810f, 0.642069212243792540f, + -0.766646676565310380f, + 0.641481012808583160f, -0.767138911935820400f, 0.640892436006621380f, + -0.767630696018273270f, + 0.640303482184151670f, -0.768122028523365310f, 0.639714151687640450f, + -0.768612909162058270f, + 0.639124444863775730f, -0.769103337645579590f, 0.638534362059466790f, + -0.769593313685422940f, + 0.637943903621844170f, -0.770082836993347900f, 0.637353069898259130f, + -0.770571907281380700f, + 0.636761861236284200f, -0.771060524261813710f, 0.636170277983712170f, + -0.771548687647206300f, + 0.635578320488556230f, -0.772036397150384410f, 0.634985989099049460f, + -0.772523652484441330f, + 0.634393284163645490f, -0.773010453362736990f, 0.633800206031017280f, + -0.773496799498899050f, + 0.633206755050057190f, -0.773982690606822790f, 0.632612931569877520f, + -0.774468126400670860f, + 0.632018735939809060f, -0.774953106594873820f, 0.631424168509401860f, + -0.775437630904130430f, + 0.630829229628424470f, -0.775921699043407580f, 0.630233919646864480f, + -0.776405310727940390f, + 0.629638238914927100f, -0.776888465673232440f, 0.629042187783036000f, + -0.777371163595056200f, + 0.628445766601832710f, -0.777853404209453040f, 0.627848975722176570f, + -0.778335187232733090f, + 0.627251815495144190f, -0.778816512381475870f, 0.626654286272029460f, + -0.779297379372530300f, + 0.626056388404343520f, -0.779777787923014440f, 0.625458122243814360f, + -0.780257737750316590f, + 0.624859488142386450f, -0.780737228572094380f, 0.624260486452220650f, + -0.781216260106276090f, + 0.623661117525694640f, -0.781694832071059390f, 0.623061381715401370f, + -0.782172944184912900f, + 0.622461279374150080f, -0.782650596166575730f, 0.621860810854965360f, + -0.783127787735057310f, + 0.621259976511087660f, -0.783604518609638200f, 0.620658776695972140f, + -0.784080788509869950f, + 0.620057211763289210f, -0.784556597155575240f, 0.619455282066924020f, + -0.785031944266848080f, + 0.618852987960976320f, -0.785506829564053930f, 0.618250329799760250f, + -0.785981252767830150f, + 0.617647307937803980f, -0.786455213599085770f, 0.617043922729849760f, + -0.786928711779001700f, + 0.616440174530853650f, -0.787401747029031320f, 0.615836063695985090f, + -0.787874319070900110f, + 0.615231590580626820f, -0.788346427626606230f, 0.614626755540375050f, + -0.788818072418420170f, + 0.614021558931038490f, -0.789289253168885650f, 0.613416001108638590f, + -0.789759969600819070f, + 0.612810082429409710f, -0.790230221437310030f, 0.612203803249798060f, + -0.790700008401721610f, + 0.611597163926462020f, -0.791169330217690090f, 0.610990164816271770f, + -0.791638186609125770f, + 0.610382806276309480f, -0.792106577300212390f, 0.609775088663868430f, + -0.792574502015407580f, + 0.609167012336453210f, -0.793041960479443640f, 0.608558577651779450f, + -0.793508952417326660f, + 0.607949784967773740f, -0.793975477554337170f, 0.607340634642572930f, + -0.794441535616030590f, + 0.606731127034524480f, -0.794907126328237010f, 0.606121262502186230f, + -0.795372249417061190f, + 0.605511041404325550f, -0.795836904608883460f, 0.604900464099919930f, + -0.796301091630359110f, + 0.604289530948156070f, -0.796764810208418720f, 0.603678242308430370f, + -0.797228060070268700f, + 0.603066598540348280f, -0.797690840943391040f, 0.602454600003723860f, + -0.798153152555543750f, + 0.601842247058580030f, -0.798614994634760820f, 0.601229540065148620f, + -0.799076366909352350f, + 0.600616479383868970f, -0.799537269107905010f, 0.600003065375389060f, + -0.799997700959281910f, + 0.599389298400564540f, -0.800457662192622710f, 0.598775178820458720f, + -0.800917152537344300f, + 0.598160706996342380f, -0.801376171723140130f, 0.597545883289693270f, + -0.801834719479981310f, + 0.596930708062196500f, -0.802292795538115720f, 0.596315181675743820f, + -0.802750399628069160f, + 0.595699304492433470f, -0.803207531480644830f, 0.595083076874569960f, + -0.803664190826924090f, + 0.594466499184664540f, -0.804120377398265700f, 0.593849571785433630f, + -0.804576090926307000f, + 0.593232295039799800f, -0.805031331142963660f, 0.592614669310891130f, + -0.805486097780429120f, + 0.591996694962040990f, -0.805940390571176280f, 0.591378372356787580f, + -0.806394209247956240f, + 0.590759701858874280f, -0.806847553543799220f, 0.590140683832248940f, + -0.807300423192014450f, + 0.589521318641063940f, -0.807752817926190360f, 0.588901606649675840f, + -0.808204737480194720f, + 0.588281548222645330f, -0.808656181588174980f, 0.587661143724736770f, + -0.809107149984558130f, + 0.587040393520918080f, -0.809557642404051260f, 0.586419297976360500f, + -0.810007658581641140f, + 0.585797857456438860f, -0.810457198252594770f, 0.585176072326730410f, + -0.810906261152459670f, + 0.584553942953015330f, -0.811354847017063730f, 0.583931469701276300f, + -0.811802955582515360f, + 0.583308652937698290f, -0.812250586585203880f, 0.582685493028668460f, + -0.812697739761799490f, + 0.582061990340775550f, -0.813144414849253590f, 0.581438145240810280f, + -0.813590611584798510f, + 0.580813958095764530f, -0.814036329705948300f, 0.580189429272831680f, + -0.814481568950498610f, + 0.579564559139405740f, -0.814926329056526620f, 0.578939348063081890f, + -0.815370609762391290f, + 0.578313796411655590f, -0.815814410806733780f, 0.577687904553122800f, + -0.816257731928477390f, + 0.577061672855679550f, -0.816700572866827850f, 0.576435101687721830f, + -0.817142933361272970f, + 0.575808191417845340f, -0.817584813151583710f, 0.575180942414845190f, + -0.818026211977813440f, + 0.574553355047715760f, -0.818467129580298660f, 0.573925429685650750f, + -0.818907565699658950f, + 0.573297166698042320f, -0.819347520076796900f, 0.572668566454481160f, + -0.819786992452898990f, + 0.572039629324757050f, -0.820225982569434690f, 0.571410355678857340f, + -0.820664490168157460f, + 0.570780745886967370f, -0.821102514991104650f, 0.570150800319470300f, + -0.821540056780597610f, + 0.569520519346947250f, -0.821977115279241550f, 0.568889903340175970f, + -0.822413690229926390f, + 0.568258952670131490f, -0.822849781375826320f, 0.567627667707986230f, + -0.823285388460400110f, + 0.566996048825108680f, -0.823720511227391320f, 0.566364096393063950f, + -0.824155149420828570f, + 0.565731810783613230f, -0.824589302785025290f, 0.565099192368714090f, + -0.825022971064580220f, + 0.564466241520519500f, -0.825456154004377440f, 0.563832958611378170f, + -0.825888851349586780f, + 0.563199344013834090f, -0.826321062845663420f, 0.562565398100626560f, + -0.826752788238348520f, + 0.561931121244689470f, -0.827184027273669020f, 0.561296513819151470f, + -0.827614779697938400f, + 0.560661576197336030f, -0.828045045257755800f, 0.560026308752760380f, + -0.828474823700007130f, + 0.559390711859136140f, -0.828904114771864870f, 0.558754785890368310f, + -0.829332918220788250f, + 0.558118531220556100f, -0.829761233794523050f, 0.557481948223991660f, + -0.830189061241102370f, + 0.556845037275160100f, -0.830616400308846200f, 0.556207798748739930f, + -0.831043250746362320f, + 0.555570233019602290f, -0.831469612302545240f, 0.554932340462810370f, + -0.831895484726577590f, + 0.554294121453620110f, -0.832320867767929680f, 0.553655576367479310f, + -0.832745761176359460f, + 0.553016705580027580f, -0.833170164701913190f, 0.552377509467096070f, + -0.833594078094925140f, + 0.551737988404707450f, -0.834017501106018130f, 0.551098142769075430f, + -0.834440433486103190f, + 0.550457972936604810f, -0.834862874986380010f, 0.549817479283891020f, + -0.835284825358337370f, + 0.549176662187719770f, -0.835706284353752600f, 0.548535522025067390f, + -0.836127251724692160f, + 0.547894059173100190f, -0.836547727223511890f, 0.547252274009174090f, + -0.836967710602857020f, + 0.546610166910834860f, -0.837387201615661940f, 0.545967738255817680f, + -0.837806200015150940f, + 0.545324988422046460f, -0.838224705554837970f, 0.544681917787634530f, + -0.838642717988527300f, + 0.544038526730883930f, -0.839060237070312630f, 0.543394815630284800f, + -0.839477262554578550f, + 0.542750784864516000f, -0.839893794195999410f, 0.542106434812444030f, + -0.840309831749540770f, + 0.541461765853123560f, -0.840725374970458070f, 0.540816778365796670f, + -0.841140423614298080f, + 0.540171472729892970f, -0.841554977436898330f, 0.539525849325029010f, + -0.841969036194387680f, + 0.538879908531008420f, -0.842382599643185960f, 0.538233650727821700f, + -0.842795667540004120f, + 0.537587076295645510f, -0.843208239641845440f, 0.536940185614843020f, + -0.843620315706004040f, + 0.536292979065963180f, -0.844031895490066410f, 0.535645457029741090f, + -0.844442978751910660f, + 0.534997619887097260f, -0.844853565249707010f, 0.534349468019137520f, + -0.845263654741918220f, + 0.533701001807152960f, -0.845673246987299070f, 0.533052221632619670f, + -0.846082341744896940f, + 0.532403127877198010f, -0.846490938774052020f, 0.531753720922733320f, + -0.846899037834397350f, + 0.531104001151255000f, -0.847306638685858320f, 0.530453968944976320f, + -0.847713741088654270f, + 0.529803624686294830f, -0.848120344803297120f, 0.529152968757790720f, + -0.848526449590592650f, + 0.528502001542228480f, -0.848932055211639610f, 0.527850723422555460f, + -0.849337161427830670f, + 0.527199134781901390f, -0.849741768000852440f, 0.526547236003579330f, + -0.850145874692685210f, + 0.525895027471084740f, -0.850549481265603370f, 0.525242509568094710f, + -0.850952587482175730f, + 0.524589682678468840f, -0.851355193105265200f, 0.523936547186248600f, + -0.851757297898029120f, + 0.523283103475656430f, -0.852158901623919830f, 0.522629351931096720f, + -0.852560004046683970f, + 0.521975292937154390f, -0.852960604930363630f, 0.521320926878595550f, + -0.853360704039295430f, + 0.520666254140367270f, -0.853760301138111300f, 0.520011275107596040f, + -0.854159395991738730f, + 0.519355990165589530f, -0.854557988365400530f, 0.518700399699835170f, + -0.854956078024614820f, + 0.518044504095999340f, -0.855353664735196030f, 0.517388303739929060f, + -0.855750748263253920f, + 0.516731799017649980f, -0.856147328375194470f, 0.516074990315366630f, + -0.856543404837719960f, + 0.515417878019463150f, -0.856938977417828650f, 0.514760462516501200f, + -0.857334045882815590f, + 0.514102744193221660f, -0.857728610000272120f, 0.513444723436543570f, + -0.858122669538086020f, + 0.512786400633563070f, -0.858516224264442740f, 0.512127776171554690f, + -0.858909273947823900f, + 0.511468850437970520f, -0.859301818357008360f, 0.510809623820439040f, + -0.859693857261072610f, + 0.510150096706766700f, -0.860085390429390140f, 0.509490269484936360f, + -0.860476417631632070f, + 0.508830142543106990f, -0.860866938637767310f, 0.508169716269614710f, + -0.861256953218062060f, + 0.507508991052970870f, -0.861646461143081300f, 0.506847967281863320f, + -0.862035462183687210f, + 0.506186645345155450f, -0.862423956111040500f, 0.505525025631885510f, + -0.862811942696600330f, + 0.504863108531267480f, -0.863199421712124160f, 0.504200894432690560f, + -0.863586392929667990f, + 0.503538383725717580f, -0.863972856121586700f, 0.502875576800086880f, + -0.864358811060534030f, + 0.502212474045710900f, -0.864744257519462380f, 0.501549075852675390f, + -0.865129195271623690f, + 0.500885382611240940f, -0.865513624090568980f, 0.500221394711840680f, + -0.865897543750148820f, + 0.499557112545081890f, -0.866280954024512990f, 0.498892536501744750f, + -0.866663854688111020f, + 0.498227666972781870f, -0.867046245515692650f, 0.497562504349319090f, + -0.867428126282306920f, + 0.496897049022654640f, -0.867809496763303210f, 0.496231301384258310f, + -0.868190356734331310f, + 0.495565261825772490f, -0.868570705971340900f, 0.494898930739011310f, + -0.868950544250582380f, + 0.494232308515959730f, -0.869329871348606730f, 0.493565395548774880f, + -0.869708687042265560f, + 0.492898192229784090f, -0.870086991108711350f, 0.492230698951486080f, + -0.870464783325397670f, + 0.491562916106550060f, -0.870842063470078860f, 0.490894844087815140f, + -0.871218831320810900f, + 0.490226483288291100f, -0.871595086655951090f, 0.489557834101157550f, + -0.871970829254157700f, + 0.488888896919763230f, -0.872346058894391540f, 0.488219672137626740f, + -0.872720775355914300f, + 0.487550160148436050f, -0.873094978418290090f, 0.486880361346047400f, + -0.873468667861384880f, + 0.486210276124486530f, -0.873841843465366750f, 0.485539904877947020f, + -0.874214505010706300f, + 0.484869248000791120f, -0.874586652278176110f, 0.484198305887549140f, + -0.874958285048851540f, + 0.483527078932918740f, -0.875329403104110780f, 0.482855567531765670f, + -0.875700006225634600f, + 0.482183772079122830f, -0.876070094195406600f, 0.481511692970189920f, + -0.876439666795713610f, + 0.480839330600333900f, -0.876808723809145760f, 0.480166685365088440f, + -0.877177265018595940f, + 0.479493757660153010f, -0.877545290207261240f, 0.478820547881394050f, + -0.877912799158641730f, + 0.478147056424843120f, -0.878279791656541460f, 0.477473283686698060f, + -0.878646267485068130f, + 0.476799230063322250f, -0.879012226428633410f, 0.476124895951243630f, + -0.879377668271953180f, + 0.475450281747155870f, -0.879742592800047410f, 0.474775387847917230f, + -0.880106999798240360f, + 0.474100214650550020f, -0.880470889052160750f, 0.473424762552241530f, + -0.880834260347742040f, + 0.472749031950342900f, -0.881197113471221980f, 0.472073023242368660f, + -0.881559448209143780f, + 0.471396736825997810f, -0.881921264348354940f, 0.470720173099071710f, + -0.882282561676008600f, + 0.470043332459595620f, -0.882643339979562790f, 0.469366215305737630f, + -0.883003599046780720f, + 0.468688822035827960f, -0.883363338665731580f, 0.468011153048359830f, + -0.883722558624789660f, + 0.467333208741988530f, -0.884081258712634990f, 0.466654989515530970f, + -0.884439438718253700f, + 0.465976495767966130f, -0.884797098430937790f, 0.465297727898434650f, + -0.885154237640285110f, + 0.464618686306237820f, -0.885510856136199950f, 0.463939371390838460f, + -0.885866953708892790f, + 0.463259783551860260f, -0.886222530148880640f, 0.462579923189086810f, + -0.886577585246987040f, + 0.461899790702462840f, -0.886932118794342080f, 0.461219386492092430f, + -0.887286130582383150f, + 0.460538710958240010f, -0.887639620402853930f, 0.459857764501329650f, + -0.887992588047805560f, + 0.459176547521944150f, -0.888345033309596240f, 0.458495060420826220f, + -0.888696955980891710f, + 0.457813303598877290f, -0.889048355854664570f, 0.457131277457156980f, + -0.889399232724195520f, + 0.456448982396883860f, -0.889749586383072890f, 0.455766418819434750f, + -0.890099416625192210f, + 0.455083587126343840f, -0.890448723244757880f, 0.454400487719303750f, + -0.890797506036281490f, + 0.453717121000163930f, -0.891145764794583180f, 0.453033487370931580f, + -0.891493499314791380f, + 0.452349587233771000f, -0.891840709392342720f, 0.451665420991002540f, + -0.892187394822982480f, + 0.450980989045103810f, -0.892533555402764690f, 0.450296291798708730f, + -0.892879190928051680f, + 0.449611329654606600f, -0.893224301195515320f, 0.448926103015743260f, + -0.893568886002136020f, + 0.448240612285220000f, -0.893912945145203250f, 0.447554857866293010f, + -0.894256478422316040f, + 0.446868840162374330f, -0.894599485631382580f, 0.446182559577030120f, + -0.894941966570620750f, + 0.445496016513981740f, -0.895283921038557580f, 0.444809211377105000f, + -0.895625348834030000f, + 0.444122144570429260f, -0.895966249756185110f, 0.443434816498138430f, + -0.896306623604479660f, + 0.442747227564570130f, -0.896646470178680150f, 0.442059378174214760f, + -0.896985789278863970f, + 0.441371268731716620f, -0.897324580705418320f, 0.440682899641873020f, + -0.897662844259040750f, + 0.439994271309633260f, -0.898000579740739880f, 0.439305384140100060f, + -0.898337786951834190f, + 0.438616238538527710f, -0.898674465693953820f, 0.437926834910322860f, + -0.899010615769039070f, + 0.437237173661044200f, -0.899346236979341460f, 0.436547255196401250f, + -0.899681329127423930f, + 0.435857079922255470f, -0.900015892016160280f, 0.435166648244619370f, + -0.900349925448735600f, + 0.434475960569655710f, -0.900683429228646860f, 0.433785017303678520f, + -0.901016403159702330f, + 0.433093818853152010f, -0.901348847046022030f, 0.432402365624690140f, + -0.901680760692037730f, + 0.431710658025057370f, -0.902012143902493070f, 0.431018696461167080f, + -0.902342996482444200f, + 0.430326481340082610f, -0.902673318237258830f, 0.429634013069016500f, + -0.903003108972617040f, + 0.428941292055329550f, -0.903332368494511820f, 0.428248318706531910f, + -0.903661096609247980f, + 0.427555093430282200f, -0.903989293123443340f, 0.426861616634386490f, + -0.904316957844028320f, + 0.426167888726799620f, -0.904644090578246240f, 0.425473910115623910f, + -0.904970691133653250f, + 0.424779681209108810f, -0.905296759318118820f, 0.424085202415651670f, + -0.905622294939825160f, + 0.423390474143796100f, -0.905947297807268460f, 0.422695496802232950f, + -0.906271767729257660f, + 0.422000270799799790f, -0.906595704514915330f, 0.421304796545479700f, + -0.906919107973678030f, + 0.420609074448402510f, -0.907241977915295930f, 0.419913104917843730f, + -0.907564314149832520f, + 0.419216888363223960f, -0.907886116487666150f, 0.418520425194109700f, + -0.908207384739488700f, + 0.417823715820212380f, -0.908528118716306120f, 0.417126760651387870f, + -0.908848318229439120f, + 0.416429560097637320f, -0.909167983090522270f, 0.415732114569105420f, + -0.909487113111505430f, + 0.415034424476081630f, -0.909805708104652220f, 0.414336490228999210f, + -0.910123767882541570f, + 0.413638312238434560f, -0.910441292258067140f, 0.412939890915108020f, + -0.910758281044437570f, + 0.412241226669883000f, -0.911074734055176250f, 0.411542319913765280f, + -0.911390651104122320f, + 0.410843171057903910f, -0.911706032005429880f, 0.410143780513590350f, + -0.912020876573568230f, + 0.409444148692257590f, -0.912335184623322750f, 0.408744276005481520f, + -0.912648955969793900f, + 0.408044162864978740f, -0.912962190428398100f, 0.407343809682607970f, + -0.913274887814867760f, + 0.406643216870369140f, -0.913587047945250810f, 0.405942384840402570f, + -0.913898670635911680f, + 0.405241314004989860f, -0.914209755703530690f, 0.404540004776553110f, + -0.914520302965104450f, + 0.403838457567654130f, -0.914830312237946090f, 0.403136672790995240f, + -0.915139783339685260f, + 0.402434650859418540f, -0.915448716088267830f, 0.401732392185905010f, + -0.915757110301956720f, + 0.401029897183575790f, -0.916064965799331610f, 0.400327166265690150f, + -0.916372282399289140f, + 0.399624199845646790f, -0.916679059921042700f, 0.398920998336983020f, + -0.916985298184122890f, + 0.398217562153373620f, -0.917290997008377910f, 0.397513891708632330f, + -0.917596156213972950f, + 0.396809987416710420f, -0.917900775621390390f, 0.396105849691696320f, + -0.918204855051430900f, + 0.395401478947816300f, -0.918508394325212250f, 0.394696875599433670f, + -0.918811393264169940f, + 0.393992040061048100f, -0.919113851690057770f, 0.393286972747296570f, + -0.919415769424946960f, + 0.392581674072951530f, -0.919717146291227360f, 0.391876144452922350f, + -0.920017982111606570f, + 0.391170384302253980f, -0.920318276709110480f, 0.390464394036126650f, + -0.920618029907083860f, + 0.389758174069856410f, -0.920917241529189520f, 0.389051724818894500f, + -0.921215911399408730f, + 0.388345046698826300f, -0.921514039342041900f, 0.387638140125372680f, + -0.921811625181708120f, + 0.386931005514388690f, -0.922108668743345070f, 0.386223643281862980f, + -0.922405169852209880f, + 0.385516053843919020f, -0.922701128333878520f, 0.384808237616812930f, + -0.922996544014246250f, + 0.384100195016935040f, -0.923291416719527640f, 0.383391926460808770f, + -0.923585746276256560f, + 0.382683432365089840f, -0.923879532511286740f, 0.381974713146567220f, + -0.924172775251791200f, + 0.381265769222162490f, -0.924465474325262600f, 0.380556601008928570f, + -0.924757629559513910f, + 0.379847208924051110f, -0.925049240782677580f, 0.379137593384847430f, + -0.925340307823206200f, + 0.378427754808765620f, -0.925630830509872720f, 0.377717693613385810f, + -0.925920808671769960f, + 0.377007410216418310f, -0.926210242138311270f, 0.376296905035704790f, + -0.926499130739230510f, + 0.375586178489217330f, -0.926787474304581750f, 0.374875230995057600f, + -0.927075272664740100f, + 0.374164062971457990f, -0.927362525650401110f, 0.373452674836780410f, + -0.927649233092581180f, + 0.372741067009515810f, -0.927935394822617890f, 0.372029239908284960f, + -0.928221010672169440f, + 0.371317193951837600f, -0.928506080473215480f, 0.370604929559051670f, + -0.928790604058057020f, + 0.369892447148934270f, -0.929074581259315750f, 0.369179747140620070f, + -0.929358011909935500f, + 0.368466829953372320f, -0.929640895843181330f, 0.367753696006582090f, + -0.929923232892639560f, + 0.367040345719767240f, -0.930205022892219070f, 0.366326779512573590f, + -0.930486265676149780f, + 0.365612997804773960f, -0.930766961078983710f, 0.364899001016267380f, + -0.931047108935595170f, + 0.364184789567079840f, -0.931326709081180430f, 0.363470363877363870f, + -0.931605761351257830f, + 0.362755724367397230f, -0.931884265581668150f, 0.362040871457584350f, + -0.932162221608574320f, + 0.361325805568454340f, -0.932439629268462360f, 0.360610527120662270f, + -0.932716488398140250f, + 0.359895036534988280f, -0.932992798834738850f, 0.359179334232336560f, + -0.933268560415712050f, + 0.358463420633736540f, -0.933543772978836170f, 0.357747296160342010f, + -0.933818436362210960f, + 0.357030961233430030f, -0.934092550404258870f, 0.356314416274402360f, + -0.934366114943725900f, + 0.355597661704783960f, -0.934639129819680780f, 0.354880697946222790f, + -0.934911594871516090f, + 0.354163525420490510f, -0.935183509938947500f, 0.353446144549480870f, + -0.935454874862014620f, + 0.352728555755210730f, -0.935725689481080370f, 0.352010759459819240f, + -0.935995953636831300f, + 0.351292756085567150f, -0.936265667170278260f, 0.350574546054837570f, + -0.936534829922755500f, + 0.349856129790135030f, -0.936803441735921560f, 0.349137507714085030f, + -0.937071502451759190f, + 0.348418680249434510f, -0.937339011912574960f, 0.347699647819051490f, + -0.937605969960999990f, + 0.346980410845923680f, -0.937872376439989890f, 0.346260969753160170f, + -0.938138231192824360f, + 0.345541324963989150f, -0.938403534063108060f, 0.344821476901759290f, + -0.938668284894770170f, + 0.344101425989938980f, -0.938932483532064490f, 0.343381172652115100f, + -0.939196129819569900f, + 0.342660717311994380f, -0.939459223602189920f, 0.341940060393402300f, + -0.939721764725153340f, + 0.341219202320282410f, -0.939983753034013940f, 0.340498143516697100f, + -0.940245188374650880f, + 0.339776884406826960f, -0.940506070593268300f, 0.339055425414969640f, + -0.940766399536396070f, + 0.338333766965541290f, -0.941026175050889260f, 0.337611909483074680f, + -0.941285396983928660f, + 0.336889853392220050f, -0.941544065183020810f, 0.336167599117744690f, + -0.941802179495997650f, + 0.335445147084531660f, -0.942059739771017310f, 0.334722497717581220f, + -0.942316745856563780f, + 0.333999651442009490f, -0.942573197601446870f, 0.333276608683047980f, + -0.942829094854802710f, + 0.332553369866044220f, -0.943084437466093490f, 0.331829935416461220f, + -0.943339225285107720f, + 0.331106305759876430f, -0.943593458161960390f, 0.330382481321982950f, + -0.943847135947092690f, + 0.329658462528587550f, -0.944100258491272660f, 0.328934249805612200f, + -0.944352825645594750f, + 0.328209843579092660f, -0.944604837261480260f, 0.327485244275178060f, + -0.944856293190677210f, + 0.326760452320131790f, -0.945107193285260610f, 0.326035468140330350f, + -0.945357537397632290f, + 0.325310292162262980f, -0.945607325380521280f, 0.324584924812532150f, + -0.945856557086983910f, + 0.323859366517852960f, -0.946105232370403340f, 0.323133617705052330f, + -0.946353351084490590f, + 0.322407678801070020f, -0.946600913083283530f, 0.321681550232956640f, + -0.946847918221148000f, + 0.320955232427875210f, -0.947094366352777220f, 0.320228725813100020f, + -0.947340257333191940f, + 0.319502030816015750f, -0.947585591017741090f, 0.318775147864118480f, + -0.947830367262101010f, + 0.318048077385015060f, -0.948074585922276230f, 0.317320819806421790f, + -0.948318246854599090f, + 0.316593375556165850f, -0.948561349915730270f, 0.315865745062184070f, + -0.948803894962658380f, + 0.315137928752522440f, -0.949045881852700560f, 0.314409927055336820f, + -0.949287310443502010f, + 0.313681740398891570f, -0.949528180593036670f, 0.312953369211560200f, + -0.949768492159606680f, + 0.312224813921825050f, -0.950008245001843000f, 0.311496074958275970f, + -0.950247438978705230f, + 0.310767152749611470f, -0.950486073949481700f, 0.310038047724638000f, + -0.950724149773789610f, + 0.309308760312268780f, -0.950961666311575080f, 0.308579290941525030f, + -0.951198623423113230f, + 0.307849640041534980f, -0.951435020969008340f, 0.307119808041533100f, + -0.951670858810193860f, + 0.306389795370861080f, -0.951906136807932230f, 0.305659602458966230f, + -0.952140854823815830f, + 0.304929229735402430f, -0.952375012719765880f, 0.304198677629829270f, + -0.952608610358033240f, + 0.303467946572011370f, -0.952841647601198720f, 0.302737036991819140f, + -0.953074124312172200f, + 0.302005949319228200f, -0.953306040354193750f, 0.301274683984318000f, + -0.953537395590833280f, + 0.300543241417273400f, -0.953768189885990330f, 0.299811622048383460f, + -0.953998423103894490f, + 0.299079826308040480f, -0.954228095109105670f, 0.298347854626741570f, + -0.954457205766513490f, + 0.297615707435086310f, -0.954685754941338340f, 0.296883385163778270f, + -0.954913742499130520f, + 0.296150888243623960f, -0.955141168305770670f, 0.295418217105532070f, + -0.955368032227470240f, + 0.294685372180514330f, -0.955594334130771110f, 0.293952353899684770f, + -0.955820073882545420f, + 0.293219162694258680f, -0.956045251349996410f, 0.292485798995553830f, + -0.956269866400658140f, + 0.291752263234989370f, -0.956493918902394990f, 0.291018555844085090f, + -0.956717408723403050f, + 0.290284677254462330f, -0.956940335732208940f, 0.289550627897843140f, + -0.957162699797670100f, + 0.288816408206049480f, -0.957384500788975860f, 0.288082018611004300f, + -0.957605738575646240f, + 0.287347459544729570f, -0.957826413027532910f, 0.286612731439347790f, + -0.958046524014818600f, + 0.285877834727080730f, -0.958266071408017670f, 0.285142769840248720f, + -0.958485055077976100f, + 0.284407537211271820f, -0.958703474895871600f, 0.283672137272668550f, + -0.958921330733213060f, + 0.282936570457055390f, -0.959138622461841890f, 0.282200837197147500f, + -0.959355349953930790f, + 0.281464937925758050f, -0.959571513081984520f, 0.280728873075797190f, + -0.959787111718839900f, + 0.279992643080273380f, -0.960002145737665850f, 0.279256248372291240f, + -0.960216615011963430f, + 0.278519689385053060f, -0.960430519415565790f, 0.277782966551857800f, + -0.960643858822638470f, + 0.277046080306099950f, -0.960856633107679660f, 0.276309031081271030f, + -0.961068842145519350f, + 0.275571819310958250f, -0.961280485811320640f, 0.274834445428843940f, + -0.961491563980579000f, + 0.274096909868706330f, -0.961702076529122540f, 0.273359213064418790f, + -0.961912023333112100f, + 0.272621355449948980f, -0.962121404269041580f, 0.271883337459359890f, + -0.962330219213737400f, + 0.271145159526808070f, -0.962538468044359160f, 0.270406822086544820f, + -0.962746150638399410f, + 0.269668325572915200f, -0.962953266873683880f, 0.268929670420357310f, + -0.963159816628371360f, + 0.268190857063403180f, -0.963365799780954050f, 0.267451885936677740f, + -0.963571216210257210f, + 0.266712757474898420f, -0.963776065795439840f, 0.265973472112875530f, + -0.963980348415994110f, + 0.265234030285511900f, -0.964184063951745720f, 0.264494432427801630f, + -0.964387212282854290f, + 0.263754678974831510f, -0.964589793289812650f, 0.263014770361779060f, + -0.964791806853447900f, + 0.262274707023913590f, -0.964993252854920320f, 0.261534489396595630f, + -0.965194131175724720f, + 0.260794117915275570f, -0.965394441697689400f, 0.260053593015495130f, + -0.965594184302976830f, + 0.259312915132886350f, -0.965793358874083570f, 0.258572084703170390f, + -0.965991965293840570f, + 0.257831102162158930f, -0.966190003445412620f, 0.257089967945753230f, + -0.966387473212298790f, + 0.256348682489942910f, -0.966584374478333120f, 0.255607246230807550f, + -0.966780707127683270f, + 0.254865659604514630f, -0.966976471044852070f, 0.254123923047320620f, + -0.967171666114676640f, + 0.253382036995570270f, -0.967366292222328510f, 0.252640001885695580f, + -0.967560349253314360f, + 0.251897818154216910f, -0.967753837093475510f, 0.251155486237742030f, + -0.967946755628987800f, + 0.250413006572965280f, -0.968139104746362330f, 0.249670379596668520f, + -0.968330884332445300f, + 0.248927605745720260f, -0.968522094274417270f, 0.248184685457074780f, + -0.968712734459794780f, + 0.247441619167773440f, -0.968902804776428870f, 0.246698407314942500f, + -0.969092305112506100f, + 0.245955050335794590f, -0.969281235356548530f, 0.245211548667627680f, + -0.969469595397412950f, + 0.244467902747824210f, -0.969657385124292450f, 0.243724113013852130f, + -0.969844604426714830f, + 0.242980179903263980f, -0.970031253194543970f, 0.242236103853696070f, + -0.970217331317979160f, + 0.241491885302869300f, -0.970402838687555500f, 0.240747524688588540f, + -0.970587775194143630f, + 0.240003022448741500f, -0.970772140728950350f, 0.239258379021300120f, + -0.970955935183517970f, + 0.238513594844318500f, -0.971139158449725090f, 0.237768670355934210f, + -0.971321810419786160f, + 0.237023605994367340f, -0.971503890986251780f, 0.236278402197919620f, + -0.971685400042008540f, + 0.235533059404975460f, -0.971866337480279400f, 0.234787578054001080f, + -0.972046703194623500f, + 0.234041958583543460f, -0.972226497078936270f, 0.233296201432231560f, + -0.972405719027449770f, + 0.232550307038775330f, -0.972584368934732210f, 0.231804275841964780f, + -0.972762446695688570f, + 0.231058108280671280f, -0.972939952205560070f, 0.230311804793845530f, + -0.973116885359925130f, + 0.229565365820518870f, -0.973293246054698250f, 0.228818791799802360f, + -0.973469034186130950f, + 0.228072083170885790f, -0.973644249650811870f, 0.227325240373038830f, + -0.973818892345666100f, + 0.226578263845610110f, -0.973992962167955830f, 0.225831154028026200f, + -0.974166459015280320f, + 0.225083911359792780f, -0.974339382785575860f, 0.224336536280493690f, + -0.974511733377115720f, + 0.223589029229790020f, -0.974683510688510670f, 0.222841390647421280f, + -0.974854714618708430f, + 0.222093620973203590f, -0.975025345066994120f, 0.221345720647030810f, + -0.975195401932990370f, + 0.220597690108873650f, -0.975364885116656870f, 0.219849529798778750f, + -0.975533794518291360f, + 0.219101240156869770f, -0.975702130038528570f, 0.218352821623346430f, + -0.975869891578341030f, + 0.217604274638483670f, -0.976037079039039020f, 0.216855599642632570f, + -0.976203692322270560f, + 0.216106797076219600f, -0.976369731330021140f, 0.215357867379745550f, + -0.976535195964614470f, + 0.214608810993786920f, -0.976700086128711840f, 0.213859628358993830f, + -0.976864401725312640f, + 0.213110319916091360f, -0.977028142657754390f, 0.212360886105878580f, + -0.977191308829712280f, + 0.211611327369227610f, -0.977353900145199960f, 0.210861644147084830f, + -0.977515916508569280f, + 0.210111836880469720f, -0.977677357824509930f, 0.209361906010474190f, + -0.977838223998050430f, + 0.208611851978263460f, -0.977998514934557140f, 0.207861675225075150f, + -0.978158230539735050f, + 0.207111376192218560f, -0.978317370719627650f, 0.206360955321075680f, + -0.978475935380616830f, + 0.205610413053099320f, -0.978633924429423100f, 0.204859749829814420f, + -0.978791337773105670f, + 0.204108966092817010f, -0.978948175319062200f, 0.203358062283773370f, + -0.979104436975029250f, + 0.202607038844421110f, -0.979260122649082020f, 0.201855896216568160f, + -0.979415232249634780f, + 0.201104634842091960f, -0.979569765685440520f, 0.200353255162940420f, + -0.979723722865591170f, + 0.199601757621131050f, -0.979877103699517640f, 0.198850142658750120f, + -0.980029908096989980f, + 0.198098410717953730f, -0.980182135968117320f, 0.197346562240966000f, + -0.980333787223347960f, + 0.196594597670080220f, -0.980484861773469380f, 0.195842517447657990f, + -0.980635359529608120f, + 0.195090322016128330f, -0.980785280403230430f, 0.194338011817988600f, + -0.980934624306141640f, + 0.193585587295803750f, -0.981083391150486590f, 0.192833048892205290f, + -0.981231580848749730f, + 0.192080397049892380f, -0.981379193313754560f, 0.191327632211630990f, + -0.981526228458664660f, + 0.190574754820252800f, -0.981672686196983110f, 0.189821765318656580f, + -0.981818566442552500f, + 0.189068664149806280f, -0.981963869109555240f, 0.188315451756732120f, + -0.982108594112513610f, + 0.187562128582529740f, -0.982252741366289370f, 0.186808695070359330f, + -0.982396310786084690f, + 0.186055151663446630f, -0.982539302287441240f, 0.185301498805082040f, + -0.982681715786240860f, + 0.184547736938619640f, -0.982823551198705240f, 0.183793866507478390f, + -0.982964808441396440f, + 0.183039887955141060f, -0.983105487431216290f, 0.182285801725153320f, + -0.983245588085407070f, + 0.181531608261125130f, -0.983385110321551180f, 0.180777308006728670f, + -0.983524054057571260f, + 0.180022901405699510f, -0.983662419211730250f, 0.179268388901835880f, + -0.983800205702631490f, + 0.178513770938997590f, -0.983937413449218920f, 0.177759047961107140f, + -0.984074042370776450f, + 0.177004220412148860f, -0.984210092386929030f, 0.176249288736167940f, + -0.984345563417641900f, + 0.175494253377271400f, -0.984480455383220930f, 0.174739114779627310f, + -0.984614768204312600f, + 0.173983873387463850f, -0.984748501801904210f, 0.173228529645070490f, + -0.984881656097323700f, + 0.172473083996796030f, -0.985014231012239840f, 0.171717536887049970f, + -0.985146226468662230f, + 0.170961888760301360f, -0.985277642388941220f, 0.170206140061078120f, + -0.985408478695768420f, + 0.169450291233967930f, -0.985538735312176060f, 0.168694342723617440f, + -0.985668412161537550f, + 0.167938294974731230f, -0.985797509167567370f, 0.167182148432072880f, + -0.985926026254321130f, + 0.166425903540464220f, -0.986053963346195440f, 0.165669560744784140f, + -0.986181320367928270f, + 0.164913120489970090f, -0.986308097244598670f, 0.164156583221015890f, + -0.986434293901627070f, + 0.163399949382973230f, -0.986559910264775410f, 0.162643219420950450f, + -0.986684946260146690f, + 0.161886393780111910f, -0.986809401814185420f, 0.161129472905678780f, + -0.986933276853677710f, + 0.160372457242928400f, -0.987056571305750970f, 0.159615347237193090f, + -0.987179285097874340f, + 0.158858143333861390f, -0.987301418157858430f, 0.158100845978377090f, + -0.987422970413855410f, + 0.157343455616238280f, -0.987543941794359230f, 0.156585972692998590f, + -0.987664332228205710f, + 0.155828397654265320f, -0.987784141644572180f, 0.155070730945700510f, + -0.987903369972977790f, + 0.154312973013020240f, -0.988022017143283530f, 0.153555124301993500f, + -0.988140083085692570f, + 0.152797185258443410f, -0.988257567730749460f, 0.152039156328246160f, + -0.988374471009341280f, + 0.151281037957330250f, -0.988490792852696590f, 0.150522830591677370f, + -0.988606533192386450f, + 0.149764534677321620f, -0.988721691960323780f, 0.149006150660348470f, + -0.988836269088763540f, + 0.148247678986896200f, -0.988950264510302990f, 0.147489120103153680f, + -0.989063678157881540f, + 0.146730474455361750f, -0.989176509964781010f, 0.145971742489812370f, + -0.989288759864625170f, + 0.145212924652847520f, -0.989400427791380380f, 0.144454021390860440f, + -0.989511513679355190f, + 0.143695033150294580f, -0.989622017463200780f, 0.142935960377642700f, + -0.989731939077910570f, + 0.142176803519448000f, -0.989841278458820530f, 0.141417563022303130f, + -0.989950035541608990f, + 0.140658239332849240f, -0.990058210262297120f, 0.139898832897777380f, + -0.990165802557248400f, + 0.139139344163826280f, -0.990272812363169110f, 0.138379773577783890f, + -0.990379239617108160f, + 0.137620121586486180f, -0.990485084256456980f, 0.136860388636816430f, + -0.990590346218950150f, + 0.136100575175706200f, -0.990695025442664630f, 0.135340681650134330f, + -0.990799121866020370f, + 0.134580708507126220f, -0.990902635427780010f, 0.133820656193754690f, + -0.991005566067049370f, + 0.133060525157139180f, -0.991107913723276780f, 0.132300315844444680f, + -0.991209678336254060f, + 0.131540028702883280f, -0.991310859846115440f, 0.130779664179711790f, + -0.991411458193338540f, + 0.130019222722233350f, -0.991511473318743900f, 0.129258704777796270f, + -0.991610905163495370f, + 0.128498110793793220f, -0.991709753669099530f, 0.127737441217662280f, + -0.991808018777406430f, + 0.126976696496885980f, -0.991905700430609330f, 0.126215877078990400f, + -0.992002798571244520f, + 0.125454983411546210f, -0.992099313142191800f, 0.124694015942167770f, + -0.992195244086673920f, + 0.123932975118512200f, -0.992290591348257370f, 0.123171861388280650f, + -0.992385354870851670f, + 0.122410675199216280f, -0.992479534598709970f, 0.121649416999105540f, + -0.992573130476428810f, + 0.120888087235777220f, -0.992666142448948020f, 0.120126686357101580f, + -0.992758570461551140f, + 0.119365214810991350f, -0.992850414459865100f, 0.118603673045400840f, + -0.992941674389860470f, + 0.117842061508325020f, -0.993032350197851410f, 0.117080380647800550f, + -0.993122441830495580f, + 0.116318630911904880f, -0.993211949234794500f, 0.115556812748755290f, + -0.993300872358093280f, + 0.114794926606510250f, -0.993389211148080650f, 0.114032972933367300f, + -0.993476965552789190f, + 0.113270952177564360f, -0.993564135520595300f, 0.112508864787378830f, + -0.993650721000219120f, + 0.111746711211126660f, -0.993736721940724600f, 0.110984491897163380f, + -0.993822138291519660f, + 0.110222207293883180f, -0.993906970002356060f, 0.109459857849718030f, + -0.993991217023329380f, + 0.108697444013138670f, -0.994074879304879370f, 0.107934966232653760f, + -0.994157956797789730f, + 0.107172424956808870f, -0.994240449453187900f, 0.106409820634187840f, + -0.994322357222545810f, + 0.105647153713410700f, -0.994403680057679100f, 0.104884424643134970f, + -0.994484417910747600f, + 0.104121633872054730f, -0.994564570734255420f, 0.103358781848899700f, + -0.994644138481050710f, + 0.102595869022436280f, -0.994723121104325700f, 0.101832895841466670f, + -0.994801518557617110f, + 0.101069862754827880f, -0.994879330794805620f, 0.100306770211392820f, + -0.994956557770116380f, + 0.099543618660069444f, -0.995033199438118630f, 0.098780408549799664f, + -0.995109255753726110f, + 0.098017140329560770f, -0.995184726672196820f, 0.097253814448363354f, + -0.995259612149133390f, + 0.096490431355252607f, -0.995333912140482280f, 0.095726991499307315f, + -0.995407626602534900f, + 0.094963495329639061f, -0.995480755491926940f, 0.094199943295393190f, + -0.995553298765638470f, + 0.093436335845747912f, -0.995625256380994310f, 0.092672673429913366f, + -0.995696628295663520f, + 0.091908956497132696f, -0.995767414467659820f, 0.091145185496681130f, + -0.995837614855341610f, + 0.090381360877865011f, -0.995907229417411720f, 0.089617483090022917f, + -0.995976258112917790f, + 0.088853552582524684f, -0.996044700901251970f, 0.088089569804770507f, + -0.996112557742151130f, + 0.087325535206192226f, -0.996179828595696870f, 0.086561449236251239f, + -0.996246513422315520f, + 0.085797312344439880f, -0.996312612182778000f, 0.085033124980280414f, + -0.996378124838200210f, + 0.084268887593324127f, -0.996443051350042630f, 0.083504600633152404f, + -0.996507391680110820f, + 0.082740264549375803f, -0.996571145790554840f, 0.081975879791633108f, + -0.996634313643869900f, + 0.081211446809592386f, -0.996696895202896060f, 0.080446966052950097f, + -0.996758890430818000f, + 0.079682437971430126f, -0.996820299291165670f, 0.078917863014785095f, + -0.996881121747813850f, + 0.078153241632794315f, -0.996941357764982160f, 0.077388574275265049f, + -0.997001007307235290f, + 0.076623861392031617f, -0.997060070339482960f, 0.075859103432954503f, + -0.997118546826979980f, + 0.075094300847921291f, -0.997176436735326190f, 0.074329454086845867f, + -0.997233740030466160f, + 0.073564563599667454f, -0.997290456678690210f, 0.072799629836351618f, + -0.997346586646633230f, + 0.072034653246889416f, -0.997402129901275300f, 0.071269634281296415f, + -0.997457086409941910f, + 0.070504573389614009f, -0.997511456140303450f, 0.069739471021907376f, + -0.997565239060375750f, + 0.068974327628266732f, -0.997618435138519550f, 0.068209143658806454f, + -0.997671044343441000f, + 0.067443919563664106f, -0.997723066644191640f, 0.066678655793001543f, + -0.997774502010167820f, + 0.065913352797003930f, -0.997825350411111640f, 0.065148011025878860f, + -0.997875611817110150f, + 0.064382630929857410f, -0.997925286198596000f, 0.063617212959193190f, + -0.997974373526346990f, + 0.062851757564161420f, -0.998022873771486240f, 0.062086265195060247f, + -0.998070786905482340f, + 0.061320736302208648f, -0.998118112900149180f, 0.060555171335947781f, + -0.998164851727646240f, + 0.059789570746640007f, -0.998211003360478190f, 0.059023934984667986f, + -0.998256567771495180f, + 0.058258264500435732f, -0.998301544933892890f, 0.057492559744367684f, + -0.998345934821212370f, + 0.056726821166907783f, -0.998389737407340160f, 0.055961049218520520f, + -0.998432952666508440f, + 0.055195244349690031f, -0.998475580573294770f, 0.054429407010919147f, + -0.998517621102622210f, + 0.053663537652730679f, -0.998559074229759310f, 0.052897636725665401f, + -0.998599939930320370f, + 0.052131704680283317f, -0.998640218180265270f, 0.051365741967162731f, + -0.998679908955899090f, + 0.050599749036899337f, -0.998719012233872940f, 0.049833726340107257f, + -0.998757527991183340f, + 0.049067674327418126f, -0.998795456205172410f, 0.048301593449480172f, + -0.998832796853527990f, + 0.047535484156959261f, -0.998869549914283560f, 0.046769346900537960f, + -0.998905715365818290f, + 0.046003182130914644f, -0.998941293186856870f, 0.045236990298804750f, + -0.998976283356469820f, + 0.044470771854938744f, -0.999010685854073380f, 0.043704527250063421f, + -0.999044500659429290f, + 0.042938256934940959f, -0.999077727752645360f, 0.042171961360348002f, + -0.999110367114174890f, + 0.041405640977076712f, -0.999142418724816910f, 0.040639296235933854f, + -0.999173882565716380f, + 0.039872927587739845f, -0.999204758618363890f, 0.039106535483329839f, + -0.999235046864595850f, + 0.038340120373552791f, -0.999264747286594420f, 0.037573682709270514f, + -0.999293859866887790f, + 0.036807222941358991f, -0.999322384588349540f, 0.036040741520706299f, + -0.999350321434199440f, + 0.035274238898213947f, -0.999377670388002850f, 0.034507715524795889f, + -0.999404431433671300f, + 0.033741171851377642f, -0.999430604555461730f, 0.032974608328897315f, + -0.999456189737977340f, + 0.032208025408304704f, -0.999481186966166950f, 0.031441423540560343f, + -0.999505596225325310f, + 0.030674803176636581f, -0.999529417501093140f, 0.029908164767516655f, + -0.999552650779456990f, + 0.029141508764193740f, -0.999575296046749220f, 0.028374835617672258f, + -0.999597353289648380f, + 0.027608145778965820f, -0.999618822495178640f, 0.026841439699098527f, + -0.999639703650710200f, + 0.026074717829104040f, -0.999659996743959220f, 0.025307980620024630f, + -0.999679701762987930f, + 0.024541228522912264f, -0.999698818696204250f, 0.023774461988827676f, + -0.999717347532362190f, + 0.023007681468839410f, -0.999735288260561680f, 0.022240887414024919f, + -0.999752640870248840f, + 0.021474080275469605f, -0.999769405351215280f, 0.020707260504265912f, + -0.999785581693599210f, + 0.019940428551514598f, -0.999801169887884260f, 0.019173584868322699f, + -0.999816169924900410f, + 0.018406729905804820f, -0.999830581795823400f, 0.017639864115082195f, + -0.999844405492175240f, + 0.016872987947281773f, -0.999857641005823860f, 0.016106101853537263f, + -0.999870288328982950f, + 0.015339206284988220f, -0.999882347454212560f, 0.014572301692779104f, + -0.999893818374418490f, + 0.013805388528060349f, -0.999904701082852900f, 0.013038467241987433f, + -0.999914995573113470f, + 0.012271538285719944f, -0.999924701839144500f, 0.011504602110422875f, + -0.999933819875236000f, + 0.010737659167264572f, -0.999942349676023910f, 0.009970709907418029f, + -0.999950291236490480f, + 0.009203754782059960f, -0.999957644551963900f, 0.008436794242369860f, + -0.999964409618118280f, + 0.007669828739531077f, -0.999970586430974140f, 0.006902858724729877f, + -0.999976174986897610f, + 0.006135884649154515f, -0.999981175282601110f, 0.005368906963996303f, + -0.999985587315143200f, + 0.004601926120448672f, -0.999989411081928400f, 0.003834942569706248f, + -0.999992646580707190f, + 0.003067956762966138f, -0.999995293809576190f, 0.002300969151425887f, + -0.999997352766978210f, + 0.001533980186284766f, -0.999998823451701880f, 0.000766990318742846f, + -0.999999705862882230f +}; + const float32_t cos_factors_2048[2048] = { + 0.999999926465717890f, 0.999999338191525530f, 0.999998161643486980f, + 0.999996396822294350f, + 0.999994043728985820f, 0.999991102364945590f, 0.999987572731904080f, + 0.999983454831937730f, + 0.999978748667468830f, 0.999973454241265940f, 0.999967571556443780f, + 0.999961100616462820f, + 0.999954041425129780f, 0.999946393986597460f, 0.999938158305364590f, + 0.999929334386276070f, + 0.999919922234522750f, 0.999909921855641540f, 0.999899333255515390f, + 0.999888156440373320f, + 0.999876391416790410f, 0.999864038191687680f, 0.999851096772332190f, + 0.999837567166337090f, + 0.999823449381661570f, 0.999808743426610520f, 0.999793449309835270f, + 0.999777567040332940f, + 0.999761096627446610f, 0.999744038080865430f, 0.999726391410624470f, + 0.999708156627104880f, + 0.999689333741033640f, 0.999669922763483760f, 0.999649923705874240f, + 0.999629336579970110f, + 0.999608161397882110f, 0.999586398172067070f, 0.999564046915327740f, + 0.999541107640812940f, + 0.999517580362016990f, 0.999493465092780590f, 0.999468761847290050f, + 0.999443470640077770f, + 0.999417591486021720f, 0.999391124400346050f, 0.999364069398620550f, + 0.999336426496761240f, + 0.999308195711029470f, 0.999279377058032710f, 0.999249970554724420f, + 0.999219976218403530f, + 0.999189394066714920f, 0.999158224117649430f, 0.999126466389543390f, + 0.999094120901079070f, + 0.999061187671284600f, 0.999027666719533690f, 0.998993558065545680f, + 0.998958861729386080f, + 0.998923577731465780f, 0.998887706092541290f, 0.998851246833715180f, + 0.998814199976435390f, + 0.998776565542495610f, 0.998738343554035230f, 0.998699534033539280f, + 0.998660137003838490f, + 0.998620152488108870f, 0.998579580509872500f, 0.998538421092996730f, + 0.998496674261694640f, + 0.998454340040524800f, 0.998411418454391300f, 0.998367909528543820f, + 0.998323813288577560f, + 0.998279129760433200f, 0.998233858970396850f, 0.998188000945100300f, + 0.998141555711520520f, + 0.998094523296980010f, 0.998046903729146840f, 0.997998697036034390f, + 0.997949903246001190f, + 0.997900522387751620f, 0.997850554490335110f, 0.997799999583146470f, + 0.997748857695925690f, + 0.997697128858758500f, 0.997644813102075420f, 0.997591910456652630f, + 0.997538420953611340f, + 0.997484344624417930f, 0.997429681500884180f, 0.997374431615167150f, + 0.997318594999768600f, + 0.997262171687536170f, 0.997205161711661850f, 0.997147565105683480f, + 0.997089381903483400f, + 0.997030612139289450f, 0.996971255847674320f, 0.996911313063555740f, + 0.996850783822196610f, + 0.996789668159204560f, 0.996727966110532490f, 0.996665677712478160f, + 0.996602803001684130f, + 0.996539342015137940f, 0.996475294790172160f, 0.996410661364464100f, + 0.996345441776035900f, + 0.996279636063254650f, 0.996213244264832040f, 0.996146266419824620f, + 0.996078702567633980f, + 0.996010552748005870f, 0.995941817001031350f, 0.995872495367145730f, + 0.995802587887129160f, + 0.995732094602106430f, 0.995661015553546910f, 0.995589350783264600f, + 0.995517100333418110f, + 0.995444264246510340f, 0.995370842565388990f, 0.995296835333246090f, + 0.995222242593618360f, + 0.995147064390386470f, 0.995071300767776170f, 0.994994951770357020f, + 0.994918017443043200f, + 0.994840497831093180f, 0.994762392980109930f, 0.994683702936040250f, + 0.994604427745175660f, + 0.994524567454151740f, 0.994444122109948040f, 0.994363091759888570f, + 0.994281476451641550f, + 0.994199276233218910f, 0.994116491152977070f, 0.994033121259616400f, + 0.993949166602181130f, + 0.993864627230059750f, 0.993779503192984580f, 0.993693794541031790f, + 0.993607501324621610f, + 0.993520623594518090f, 0.993433161401829360f, 0.993345114798006910f, + 0.993256483834846440f, + 0.993167268564487230f, 0.993077469039412300f, 0.992987085312448390f, + 0.992896117436765980f, + 0.992804565465879140f, 0.992712429453645460f, 0.992619709454266140f, + 0.992526405522286100f, + 0.992432517712593660f, 0.992338046080420420f, 0.992242990681341700f, + 0.992147351571276090f, + 0.992051128806485720f, 0.991954322443575950f, 0.991856932539495470f, + 0.991758959151536110f, + 0.991660402337333210f, 0.991561262154865290f, 0.991461538662453790f, + 0.991361231918763460f, + 0.991260341982802440f, 0.991158868913921350f, 0.991056812771814340f, + 0.990954173616518500f, + 0.990850951508413620f, 0.990747146508222710f, 0.990642758677011570f, + 0.990537788076188750f, + 0.990432234767505970f, 0.990326098813057330f, 0.990219380275280000f, + 0.990112079216953770f, + 0.990004195701200910f, 0.989895729791486660f, 0.989786681551618640f, + 0.989677051045747210f, + 0.989566838338365120f, 0.989456043494307710f, 0.989344666578752640f, + 0.989232707657220050f, + 0.989120166795572690f, 0.989007044060015270f, 0.988893339517095130f, + 0.988779053233701520f, + 0.988664185277066230f, 0.988548735714763200f, 0.988432704614708340f, + 0.988316092045159690f, + 0.988198898074717610f, 0.988081122772324070f, 0.987962766207263420f, + 0.987843828449161740f, + 0.987724309567986960f, 0.987604209634049160f, 0.987483528717999710f, + 0.987362266890832400f, + 0.987240424223882250f, 0.987118000788826280f, 0.986994996657682980f, + 0.986871411902812470f, + 0.986747246596916590f, 0.986622500813038480f, 0.986497174624562880f, + 0.986371268105216030f, + 0.986244781329065460f, 0.986117714370520090f, 0.985990067304330140f, + 0.985861840205586980f, + 0.985733033149723490f, 0.985603646212513400f, 0.985473679470071810f, + 0.985343132998854790f, + 0.985212006875659350f, 0.985080301177623800f, 0.984948015982227030f, + 0.984815151367289140f, + 0.984681707410970940f, 0.984547684191773960f, 0.984413081788540700f, + 0.984277900280454370f, + 0.984142139747038570f, 0.984005800268157870f, 0.983868881924017220f, + 0.983731384795162090f, + 0.983593308962478650f, 0.983454654507193270f, 0.983315421510872810f, + 0.983175610055424420f, + 0.983035220223095640f, 0.982894252096474070f, 0.982752705758487830f, + 0.982610581292404750f, + 0.982467878781833170f, 0.982324598310721280f, 0.982180739963357090f, + 0.982036303824369020f, + 0.981891289978725100f, 0.981745698511732990f, 0.981599529509040720f, + 0.981452783056635520f, + 0.981305459240844670f, 0.981157558148334830f, 0.981009079866112630f, + 0.980860024481523870f, + 0.980710392082253970f, 0.980560182756327840f, 0.980409396592109910f, + 0.980258033678303550f, + 0.980106094103951770f, 0.979953577958436740f, 0.979800485331479790f, + 0.979646816313141210f, + 0.979492570993820810f, 0.979337749464256780f, 0.979182351815526930f, + 0.979026378139047580f, + 0.978869828526574120f, 0.978712703070200420f, 0.978555001862359550f, + 0.978396724995823090f, + 0.978237872563701090f, 0.978078444659442380f, 0.977918441376834370f, + 0.977757862810002760f, + 0.977596709053411890f, 0.977434980201864260f, 0.977272676350500860f, + 0.977109797594800880f, + 0.976946344030581670f, 0.976782315753998650f, 0.976617712861545640f, + 0.976452535450054060f, + 0.976286783616693630f, 0.976120457458971910f, 0.975953557074734300f, + 0.975786082562163930f, + 0.975618034019781750f, 0.975449411546446380f, 0.975280215241354220f, + 0.975110445204038890f, + 0.974940101534371830f, 0.974769184332561770f, 0.974597693699155050f, + 0.974425629735034990f, + 0.974252992541422500f, 0.974079782219875680f, 0.973905998872289570f, + 0.973731642600896400f, + 0.973556713508265560f, 0.973381211697303290f, 0.973205137271252800f, + 0.973028490333694210f, + 0.972851270988544180f, 0.972673479340056430f, 0.972495115492821190f, + 0.972316179551765300f, + 0.972136671622152230f, 0.971956591809581720f, 0.971775940219990140f, + 0.971594716959650160f, + 0.971412922135170940f, 0.971230555853497380f, 0.971047618221911100f, + 0.970864109348029470f, + 0.970680029339806130f, 0.970495378305530560f, 0.970310156353828110f, + 0.970124363593660280f, + 0.969938000134323960f, 0.969751066085452140f, 0.969563561557013180f, + 0.969375486659311280f, + 0.969186841502985950f, 0.968997626199012420f, 0.968807840858700970f, + 0.968617485593697540f, + 0.968426560515983190f, 0.968235065737874320f, 0.968043001372022260f, + 0.967850367531413620f, + 0.967657164329369880f, 0.967463391879547550f, 0.967269050295937790f, + 0.967074139692867040f, + 0.966878660184995910f, 0.966682611887320080f, 0.966485994915169840f, + 0.966288809384209690f, + 0.966091055410438830f, 0.965892733110190860f, 0.965693842600133690f, + 0.965494383997269500f, + 0.965294357418934660f, 0.965093762982799590f, 0.964892600806868890f, + 0.964690871009481030f, + 0.964488573709308410f, 0.964285709025357480f, 0.964082277076968140f, + 0.963878277983814200f, + 0.963673711865903230f, 0.963468578843575950f, 0.963262879037507070f, + 0.963056612568704340f, + 0.962849779558509030f, 0.962642380128595710f, 0.962434414400972100f, + 0.962225882497979020f, + 0.962016784542290560f, 0.961807120656913540f, 0.961596890965187860f, + 0.961386095590786250f, + 0.961174734657714080f, 0.960962808290309780f, 0.960750316613243950f, + 0.960537259751520050f, + 0.960323637830473920f, 0.960109450975773940f, 0.959894699313420530f, + 0.959679382969746750f, + 0.959463502071417510f, 0.959247056745430090f, 0.959030047119113660f, + 0.958812473320129310f, + 0.958594335476470220f, 0.958375633716461170f, 0.958156368168758820f, + 0.957936538962351420f, + 0.957716146226558870f, 0.957495190091032570f, 0.957273670685755200f, + 0.957051588141040970f, + 0.956828942587535370f, 0.956605734156215080f, 0.956381962978387730f, + 0.956157629185692140f, + 0.955932732910098280f, 0.955707274283906560f, 0.955481253439748770f, + 0.955254670510586990f, + 0.955027525629714160f, 0.954799818930753720f, 0.954571550547659630f, + 0.954342720614716480f, + 0.954113329266538800f, 0.953883376638071770f, 0.953652862864590500f, + 0.953421788081700310f, + 0.953190152425336670f, 0.952957956031764700f, 0.952725199037579570f, + 0.952491881579706320f, + 0.952258003795399600f, 0.952023565822243570f, 0.951788567798152130f, + 0.951553009861368590f, + 0.951316892150465550f, 0.951080214804345010f, 0.950842977962238160f, + 0.950605181763705340f, + 0.950366826348635780f, 0.950127911857248100f, 0.949888438430089300f, + 0.949648406208035480f, + 0.949407815332291570f, 0.949166665944390700f, 0.948924958186195160f, + 0.948682692199895090f, + 0.948439868128009620f, 0.948196486113385580f, 0.947952546299198670f, + 0.947708048828952100f, + 0.947462993846477700f, 0.947217381495934820f, 0.946971211921810880f, + 0.946724485268921170f, + 0.946477201682408680f, 0.946229361307743820f, 0.945980964290724760f, + 0.945732010777477150f, + 0.945482500914453740f, 0.945232434848435000f, 0.944981812726528150f, + 0.944730634696167800f, + 0.944478900905115550f, 0.944226611501459810f, 0.943973766633615980f, + 0.943720366450326200f, + 0.943466411100659320f, 0.943211900734010620f, 0.942956835500102120f, + 0.942701215548981900f, + 0.942445041031024890f, 0.942188312096931770f, 0.941931028897729620f, + 0.941673191584771360f, + 0.941414800309736340f, 0.941155855224629190f, 0.940896356481780830f, + 0.940636304233847590f, + 0.940375698633811540f, 0.940114539834980280f, 0.939852827990986680f, + 0.939590563255789270f, + 0.939327745783671400f, 0.939064375729241950f, 0.938800453247434770f, + 0.938535978493508560f, + 0.938270951623047190f, 0.938005372791958840f, 0.937739242156476970f, + 0.937472559873159250f, + 0.937205326098887960f, 0.936937540990869900f, 0.936669204706636170f, + 0.936400317404042060f, + 0.936130879241267030f, 0.935860890376814640f, 0.935590350969512370f, + 0.935319261178511610f, + 0.935047621163287430f, 0.934775431083638700f, 0.934502691099687870f, + 0.934229401371880820f, + 0.933955562060986730f, 0.933681173328098410f, 0.933406235334631520f, + 0.933130748242325230f, + 0.932854712213241120f, 0.932578127409764420f, 0.932300993994602760f, + 0.932023312130786490f, + 0.931745081981668720f, 0.931466303710925090f, 0.931186977482553750f, + 0.930907103460875130f, + 0.930626681810531760f, 0.930345712696488470f, 0.930064196284032360f, + 0.929782132738772190f, + 0.929499522226638560f, 0.929216364913884040f, 0.928932660967082820f, + 0.928648410553130520f, + 0.928363613839244370f, 0.928078270992963140f, 0.927792382182146320f, + 0.927505947574975180f, + 0.927218967339951790f, 0.926931441645899130f, 0.926643370661961230f, + 0.926354754557602860f, + 0.926065593502609310f, 0.925775887667086740f, 0.925485637221461490f, + 0.925194842336480530f, + 0.924903503183210910f, 0.924611619933039970f, 0.924319192757675160f, + 0.924026221829143850f, + 0.923732707319793290f, 0.923438649402290370f, 0.923144048249621930f, + 0.922848904035094120f, + 0.922553216932332830f, 0.922256987115283030f, 0.921960214758209220f, + 0.921662900035694730f, + 0.921365043122642340f, 0.921066644194273640f, 0.920767703426128790f, + 0.920468220994067110f, + 0.920168197074266340f, 0.919867631843222950f, 0.919566525477751530f, + 0.919264878154985370f, + 0.918962690052375630f, 0.918659961347691900f, 0.918356692219021720f, + 0.918052882844770380f, + 0.917748533403661250f, 0.917443644074735220f, 0.917138215037350710f, + 0.916832246471183890f, + 0.916525738556228210f, 0.916218691472794220f, 0.915911105401509880f, + 0.915602980523320230f, + 0.915294317019487050f, 0.914985115071589310f, 0.914675374861522390f, + 0.914365096571498560f, + 0.914054280384046570f, 0.913742926482011390f, 0.913431035048554720f, + 0.913118606267154240f, + 0.912805640321603500f, 0.912492137396012650f, 0.912178097674807180f, + 0.911863521342728520f, + 0.911548408584833990f, 0.911232759586496190f, 0.910916574533403360f, + 0.910599853611558930f, + 0.910282597007281760f, 0.909964804907205660f, 0.909646477498279540f, + 0.909327614967767260f, + 0.909008217503247450f, 0.908688285292613360f, 0.908367818524072890f, + 0.908046817386148340f, + 0.907725282067676440f, 0.907403212757808110f, 0.907080609646008450f, + 0.906757472922056550f, + 0.906433802776045460f, 0.906109599398381980f, 0.905784862979786550f, + 0.905459593711293250f, + 0.905133791784249690f, 0.904807457390316540f, 0.904480590721468250f, + 0.904153191969991780f, + 0.903825261328487510f, 0.903496798989868450f, 0.903167805147360720f, + 0.902838279994502830f, + 0.902508223725145940f, 0.902177636533453620f, 0.901846518613901750f, + 0.901514870161278740f, + 0.901182691370684520f, 0.900849982437531450f, 0.900516743557543520f, + 0.900182974926756810f, + 0.899848676741518580f, 0.899513849198487980f, 0.899178492494635330f, + 0.898842606827242370f, + 0.898506192393901950f, 0.898169249392518080f, 0.897831778021305650f, + 0.897493778478790310f, + 0.897155250963808550f, 0.896816195675507300f, 0.896476612813344120f, + 0.896136502577086770f, + 0.895795865166813530f, 0.895454700782912450f, 0.895113009626081760f, + 0.894770791897329550f, + 0.894428047797973800f, 0.894084777529641990f, 0.893740981294271040f, + 0.893396659294107720f, + 0.893051811731707450f, 0.892706438809935390f, 0.892360540731965360f, + 0.892014117701280470f, + 0.891667169921672280f, 0.891319697597241390f, 0.890971700932396860f, + 0.890623180131855930f, + 0.890274135400644600f, 0.889924566944096720f, 0.889574474967854580f, + 0.889223859677868210f, + 0.888872721280395630f, 0.888521059982002260f, 0.888168875989561730f, + 0.887816169510254440f, + 0.887462940751568840f, 0.887109189921300170f, 0.886754917227550840f, + 0.886400122878730600f, + 0.886044807083555600f, 0.885688970051048960f, 0.885332611990540590f, + 0.884975733111666660f, + 0.884618333624369920f, 0.884260413738899190f, 0.883901973665809470f, + 0.883543013615961880f, + 0.883183533800523390f, 0.882823534430966620f, 0.882463015719070150f, + 0.882101977876917580f, + 0.881740421116898320f, 0.881378345651706920f, 0.881015751694342870f, + 0.880652639458111010f, + 0.880289009156621010f, 0.879924861003786860f, 0.879560195213827890f, + 0.879195012001267480f, + 0.878829311580933360f, 0.878463094167957870f, 0.878096359977777130f, + 0.877729109226131570f, + 0.877361342129065140f, 0.876993058902925890f, 0.876624259764365310f, + 0.876254944930338510f, + 0.875885114618103810f, 0.875514769045222850f, 0.875143908429560360f, + 0.874772532989284150f, + 0.874400642942864790f, 0.874028238509075740f, 0.873655319906992630f, + 0.873281887355994210f, + 0.872907941075761080f, 0.872533481286276170f, 0.872158508207824480f, + 0.871783022060993120f, + 0.871407023066670950f, 0.871030511446048260f, 0.870653487420617430f, + 0.870275951212171940f, + 0.869897903042806340f, 0.869519343134916860f, 0.869140271711200560f, + 0.868760688994655310f, + 0.868380595208579800f, 0.867999990576573510f, 0.867618875322536230f, + 0.867237249670668400f, + 0.866855113845470430f, 0.866472468071743050f, 0.866089312574586770f, + 0.865705647579402380f, + 0.865321473311889800f, 0.864936789998049020f, 0.864551597864179340f, + 0.864165897136879300f, + 0.863779688043046720f, 0.863392970809878420f, 0.863005745664870320f, + 0.862618012835816740f, + 0.862229772550811240f, 0.861841025038245330f, 0.861451770526809320f, + 0.861062009245491480f, + 0.860671741423578380f, 0.860280967290654510f, 0.859889687076602290f, + 0.859497901011601730f, + 0.859105609326130450f, 0.858712812250963520f, 0.858319510017173440f, + 0.857925702856129790f, + 0.857531390999499150f, 0.857136574679244980f, 0.856741254127627470f, + 0.856345429577203610f, + 0.855949101260826910f, 0.855552269411646860f, 0.855154934263109620f, + 0.854757096048957220f, + 0.854358755003227440f, 0.853959911360254180f, 0.853560565354666840f, + 0.853160717221390420f, + 0.852760367195645300f, 0.852359515512947090f, 0.851958162409106380f, + 0.851556308120228980f, + 0.851153952882715340f, 0.850751096933260790f, 0.850347740508854980f, + 0.849943883846782210f, + 0.849539527184620890f, 0.849134670760243630f, 0.848729314811817130f, + 0.848323459577801640f, + 0.847917105296951410f, 0.847510252208314330f, 0.847102900551231500f, + 0.846695050565337450f, + 0.846286702490559710f, 0.845877856567119000f, 0.845468513035528830f, + 0.845058672136595470f, + 0.844648334111417820f, 0.844237499201387020f, 0.843826167648186740f, + 0.843414339693792760f, + 0.843002015580472940f, 0.842589195550786710f, 0.842175879847585570f, + 0.841762068714012490f, + 0.841347762393501950f, 0.840932961129779780f, 0.840517665166862550f, + 0.840101874749058400f, + 0.839685590120966110f, 0.839268811527475230f, 0.838851539213765760f, + 0.838433773425308340f, + 0.838015514407863820f, 0.837596762407483040f, 0.837177517670507300f, + 0.836757780443567190f, + 0.836337550973583530f, 0.835916829507766360f, 0.835495616293615350f, + 0.835073911578919410f, + 0.834651715611756440f, 0.834229028640493420f, 0.833805850913786340f, + 0.833382182680579730f, + 0.832958024190106670f, 0.832533375691888680f, 0.832108237435735590f, + 0.831682609671745120f, + 0.831256492650303210f, 0.830829886622083570f, 0.830402791838047550f, + 0.829975208549443950f, + 0.829547137007808910f, 0.829118577464965980f, 0.828689530173025820f, + 0.828259995384385660f, + 0.827829973351729920f, 0.827399464328029470f, 0.826968468566541600f, + 0.826536986320809960f, + 0.826105017844664610f, 0.825672563392221390f, 0.825239623217882250f, + 0.824806197576334330f, + 0.824372286722551250f, 0.823937890911791370f, 0.823503010399598500f, + 0.823067645441801670f, + 0.822631796294514990f, 0.822195463214137170f, 0.821758646457351750f, + 0.821321346281126740f, + 0.820883562942714580f, 0.820445296699652050f, 0.820006547809759680f, + 0.819567316531142230f, + 0.819127603122188240f, 0.818687407841569680f, 0.818246730948242070f, + 0.817805572701444270f, + 0.817363933360698460f, 0.816921813185809480f, 0.816479212436865390f, + 0.816036131374236810f, + 0.815592570258576790f, 0.815148529350820830f, 0.814704008912187080f, + 0.814259009204175270f, + 0.813813530488567190f, 0.813367573027426570f, 0.812921137083098770f, + 0.812474222918210480f, + 0.812026830795669730f, 0.811578960978665890f, 0.811130613730669190f, + 0.810681789315430780f, + 0.810232487996982330f, 0.809782710039636530f, 0.809332455707985950f, + 0.808881725266903610f, + 0.808430518981542720f, 0.807978837117336310f, 0.807526679939997160f, + 0.807074047715517610f, + 0.806620940710169650f, 0.806167359190504420f, 0.805713303423352230f, + 0.805258773675822210f, + 0.804803770215302920f, 0.804348293309460780f, 0.803892343226241260f, + 0.803435920233868120f, + 0.802979024600843250f, 0.802521656595946430f, 0.802063816488235440f, + 0.801605504547046150f, + 0.801146721041991360f, 0.800687466242961610f, 0.800227740420124790f, + 0.799767543843925680f, + 0.799306876785086160f, 0.798845739514604580f, 0.798384132303756380f, + 0.797922055424093000f, + 0.797459509147442460f, 0.796996493745908750f, 0.796533009491872000f, + 0.796069056657987990f, + 0.795604635517188070f, 0.795139746342679590f, 0.794674389407944550f, + 0.794208564986740640f, + 0.793742273353100210f, 0.793275514781330630f, 0.792808289546014120f, + 0.792340597922007170f, + 0.791872440184440470f, 0.791403816608719500f, 0.790934727470523290f, + 0.790465173045804880f, + 0.789995153610791090f, 0.789524669441982190f, 0.789053720816151880f, + 0.788582308010347120f, + 0.788110431301888070f, 0.787638090968367450f, 0.787165287287651010f, + 0.786692020537876790f, + 0.786218290997455660f, 0.785744098945070360f, 0.785269444659675850f, + 0.784794328420499230f, + 0.784318750507038920f, 0.783842711199065230f, 0.783366210776619720f, + 0.782889249520015480f, + 0.782411827709836530f, 0.781933945626937630f, 0.781455603552444590f, + 0.780976801767753750f, + 0.780497540554531910f, 0.780017820194715990f, 0.779537640970513260f, + 0.779057003164400630f, + 0.778575907059125050f, 0.778094352937702790f, 0.777612341083420030f, + 0.777129871779831620f, + 0.776646945310762060f, 0.776163561960304340f, 0.775679722012820650f, + 0.775195425752941420f, + 0.774710673465565550f, 0.774225465435860680f, 0.773739801949261840f, + 0.773253683291472590f, + 0.772767109748463850f, 0.772280081606474320f, 0.771792599152010150f, + 0.771304662671844830f, + 0.770816272453018540f, 0.770327428782838890f, 0.769838131948879840f, + 0.769348382238982280f, + 0.768858179941253270f, 0.768367525344066270f, 0.767876418736060610f, + 0.767384860406141730f, + 0.766892850643480670f, 0.766400389737514230f, 0.765907477977944340f, + 0.765414115654738270f, + 0.764920303058128410f, 0.764426040478612070f, 0.763931328206951090f, + 0.763436166534172010f, + 0.762940555751565720f, 0.762444496150687210f, 0.761947988023355390f, + 0.761451031661653620f, + 0.760953627357928150f, 0.760455775404789260f, 0.759957476095110330f, + 0.759458729722028210f, + 0.758959536578942440f, 0.758459896959515430f, 0.757959811157672300f, + 0.757459279467600720f, + 0.756958302183750490f, 0.756456879600833740f, 0.755955012013824420f, + 0.755452699717958250f, + 0.754949943008732640f, 0.754446742181906440f, 0.753943097533499640f, + 0.753439009359793580f, + 0.752934477957330150f, 0.752429503622912390f, 0.751924086653603550f, + 0.751418227346727470f, + 0.750911925999867890f, 0.750405182910869330f, 0.749897998377835330f, + 0.749390372699129560f, + 0.748882306173375150f, 0.748373799099454560f, 0.747864851776509410f, + 0.747355464503940190f, + 0.746845637581406540f, 0.746335371308826320f, 0.745824665986376090f, + 0.745313521914490520f, + 0.744801939393862630f, 0.744289918725443260f, 0.743777460210440890f, + 0.743264564150321600f, + 0.742751230846809050f, 0.742237460601884000f, 0.741723253717784140f, + 0.741208610497004260f, + 0.740693531242295760f, 0.740178016256666240f, 0.739662065843380010f, + 0.739145680305957510f, + 0.738628859948174840f, 0.738111605074064260f, 0.737593915987913570f, + 0.737075792994265730f, + 0.736557236397919150f, 0.736038246503927350f, 0.735518823617598900f, + 0.734998968044496710f, + 0.734478680090438370f, 0.733957960061495940f, 0.733436808263995710f, + 0.732915225004517780f, + 0.732393210589896040f, 0.731870765327218290f, 0.731347889523825570f, + 0.730824583487312160f, + 0.730300847525525490f, 0.729776681946566090f, 0.729252087058786970f, + 0.728727063170793830f, + 0.728201610591444610f, 0.727675729629849610f, 0.727149420595371020f, + 0.726622683797622850f, + 0.726095519546471000f, 0.725567928152032300f, 0.725039909924675370f, + 0.724511465175019630f, + 0.723982594213935520f, 0.723453297352544380f, 0.722923574902217700f, + 0.722393427174577550f, + 0.721862854481496340f, 0.721331857135096290f, 0.720800435447749190f, + 0.720268589732077190f, + 0.719736320300951030f, 0.719203627467491220f, 0.718670511545067230f, + 0.718136972847297490f, + 0.717603011688049080f, 0.717068628381437480f, 0.716533823241826680f, + 0.715998596583828690f, + 0.715462948722303760f, 0.714926879972359490f, 0.714390390649351390f, + 0.713853481068882470f, + 0.713316151546802610f, 0.712778402399208980f, 0.712240233942445510f, + 0.711701646493102970f, + 0.711162640368018350f, 0.710623215884275020f, 0.710083373359202800f, + 0.709543113110376770f, + 0.709002435455618250f, 0.708461340712994160f, 0.707919829200816310f, + 0.707377901237642100f, + 0.706835557142273860f, 0.706292797233758480f, 0.705749621831387790f, + 0.705206031254697830f, + 0.704662025823468930f, 0.704117605857725430f, 0.703572771677735580f, + 0.703027523604011220f, + 0.702481861957308000f, 0.701935787058624360f, 0.701389299229202230f, + 0.700842398790526230f, + 0.700295086064323780f, 0.699747361372564990f, 0.699199225037462120f, + 0.698650677381469580f, + 0.698101718727283880f, 0.697552349397843270f, 0.697002569716327460f, + 0.696452380006157830f, + 0.695901780590996830f, 0.695350771794747800f, 0.694799353941554900f, + 0.694247527355803310f, + 0.693695292362118350f, 0.693142649285365510f, 0.692589598450650380f, + 0.692036140183318830f, + 0.691482274808955850f, 0.690928002653386280f, 0.690373324042674040f, + 0.689818239303122470f, + 0.689262748761273470f, 0.688706852743907750f, 0.688150551578044830f, + 0.687593845590942170f, + 0.687036735110095660f, 0.686479220463238950f, 0.685921301978343670f, + 0.685362979983618730f, + 0.684804254807510620f, 0.684245126778703080f, 0.683685596226116690f, + 0.683125663478908800f, + 0.682565328866473250f, 0.682004592718440830f, 0.681443455364677990f, + 0.680881917135287340f, + 0.680319978360607200f, 0.679757639371212030f, 0.679194900497911200f, + 0.678631762071749470f, + 0.678068224424006600f, 0.677504287886197430f, 0.676939952790071240f, + 0.676375219467611700f, + 0.675810088251037060f, 0.675244559472799270f, 0.674678633465584540f, + 0.674112310562312360f, + 0.673545591096136100f, 0.672978475400442090f, 0.672410963808849900f, + 0.671843056655211930f, + 0.671274754273613490f, 0.670706056998372160f, 0.670136965164037760f, + 0.669567479105392490f, + 0.668997599157450270f, 0.668427325655456820f, 0.667856658934889440f, + 0.667285599331456480f, + 0.666714147181097670f, 0.666142302819983540f, 0.665570066584515560f, + 0.664997438811325340f, + 0.664424419837275180f, 0.663851009999457340f, 0.663277209635194100f, + 0.662703019082037440f, + 0.662128438677768720f, 0.661553468760399000f, 0.660978109668168060f, + 0.660402361739545030f, + 0.659826225313227430f, 0.659249700728141490f, 0.658672788323441890f, + 0.658095488438511290f, + 0.657517801412960120f, 0.656939727586627110f, 0.656361267299578000f, + 0.655782420892106030f, + 0.655203188704731930f, 0.654623571078202680f, 0.654043568353492640f, + 0.653463180871802330f, + 0.652882408974558960f, 0.652301253003415460f, 0.651719713300251020f, + 0.651137790207170330f, + 0.650555484066503990f, 0.649972795220807530f, 0.649389724012861770f, + 0.648806270785672550f, + 0.648222435882470420f, 0.647638219646710420f, 0.647053622422071650f, + 0.646468644552457890f, + 0.645883286381996440f, 0.645297548255038380f, 0.644711430516158420f, + 0.644124933510154540f, + 0.643538057582047850f, 0.642950803077082080f, 0.642363170340724320f, + 0.641775159718663500f, + 0.641186771556811250f, 0.640598006201301030f, 0.640008863998488440f, + 0.639419345294950700f, + 0.638829450437486400f, 0.638239179773115390f, 0.637648533649078810f, + 0.637057512412838590f, + 0.636466116412077180f, 0.635874345994697720f, 0.635282201508823530f, + 0.634689683302797850f, + 0.634096791725183740f, 0.633503527124764320f, 0.632909889850541860f, + 0.632315880251737680f, + 0.631721498677792370f, 0.631126745478365340f, 0.630531621003334600f, + 0.629936125602796550f, + 0.629340259627065750f, 0.628744023426674790f, 0.628147417352374120f, + 0.627550441755131530f, + 0.626953096986132770f, 0.626355383396779990f, 0.625757301338692900f, + 0.625158851163707730f, + 0.624560033223877320f, 0.623960847871470770f, 0.623361295458973340f, + 0.622761376339086460f, + 0.622161090864726930f, 0.621560439389027270f, 0.620959422265335180f, + 0.620358039847213830f, + 0.619756292488440660f, 0.619154180543008410f, 0.618551704365123860f, + 0.617948864309208260f, + 0.617345660729896940f, 0.616742093982038830f, 0.616138164420696910f, + 0.615533872401147430f, + 0.614929218278879590f, 0.614324202409595950f, 0.613718825149211830f, + 0.613113086853854910f, + 0.612506987879865570f, 0.611900528583796070f, 0.611293709322411010f, + 0.610686530452686280f, + 0.610078992331809620f, 0.609471095317180240f, 0.608862839766408200f, + 0.608254226037314490f, + 0.607645254487930830f, 0.607035925476499760f, 0.606426239361473550f, + 0.605816196501515080f, + 0.605205797255496500f, 0.604595041982500360f, 0.603983931041818020f, + 0.603372464792950370f, + 0.602760643595607220f, 0.602148467809707320f, 0.601535937795377730f, + 0.600923053912954090f, + 0.600309816522980430f, 0.599696225986208310f, 0.599082282663597310f, + 0.598467986916314310f, + 0.597853339105733910f, 0.597238339593437530f, 0.596622988741213330f, + 0.596007286911056530f, + 0.595391234465168730f, 0.594774831765957580f, 0.594158079176036800f, + 0.593540977058226390f, + 0.592923525775551410f, 0.592305725691242400f, 0.591687577168735550f, + 0.591069080571671510f, + 0.590450236263895920f, 0.589831044609458900f, 0.589211505972615070f, + 0.588591620717822890f, + 0.587971389209745120f, 0.587350811813247660f, 0.586729888893400500f, + 0.586108620815476430f, + 0.585487007944951450f, 0.584865050647504490f, 0.584242749289016980f, + 0.583620104235572760f, + 0.582997115853457700f, 0.582373784509160220f, 0.581750110569369760f, + 0.581126094400977620f, + 0.580501736371076600f, 0.579877036846960350f, 0.579251996196123550f, + 0.578626614786261430f, + 0.578000892985269910f, 0.577374831161244880f, 0.576748429682482520f, + 0.576121688917478390f, + 0.575494609234928230f, 0.574867191003726740f, 0.574239434592967890f, + 0.573611340371944610f, + 0.572982908710148680f, 0.572354139977270030f, 0.571725034543197120f, + 0.571095592778016690f, + 0.570465815052012990f, 0.569835701735668110f, 0.569205253199661200f, + 0.568574469814869250f, + 0.567943351952365670f, 0.567311899983420800f, 0.566680114279501710f, + 0.566047995212271560f, + 0.565415543153589770f, 0.564782758475511400f, 0.564149641550287680f, + 0.563516192750364910f, + 0.562882412448384550f, 0.562248301017183150f, 0.561613858829792420f, + 0.560979086259438260f, + 0.560343983679540860f, 0.559708551463714790f, 0.559072789985768480f, + 0.558436699619704100f, + 0.557800280739717100f, 0.557163533720196340f, 0.556526458935723720f, + 0.555889056761073920f, + 0.555251327571214090f, 0.554613271741304040f, 0.553974889646695610f, + 0.553336181662932410f, + 0.552697148165749770f, 0.552057789531074980f, 0.551418106135026060f, + 0.550778098353912230f, + 0.550137766564233630f, 0.549497111142680960f, 0.548856132466135290f, + 0.548214830911667780f, + 0.547573206856539870f, 0.546931260678202190f, 0.546288992754295210f, + 0.545646403462648590f, + 0.545003493181281160f, 0.544360262288400400f, 0.543716711162402390f, + 0.543072840181871850f, + 0.542428649725581360f, 0.541784140172491660f, 0.541139311901750910f, + 0.540494165292695230f, + 0.539848700724847700f, 0.539202918577918240f, 0.538556819231804210f, + 0.537910403066588990f, + 0.537263670462542530f, 0.536616621800121150f, 0.535969257459966710f, + 0.535321577822907010f, + 0.534673583269955510f, 0.534025274182310380f, 0.533376650941355560f, + 0.532727713928658810f, + 0.532078463525973540f, 0.531428900115236910f, 0.530779024078570250f, + 0.530128835798278850f, + 0.529478335656852090f, 0.528827524036961980f, 0.528176401321464370f, + 0.527524967893398200f, + 0.526873224135984700f, 0.526221170432628170f, 0.525568807166914680f, + 0.524916134722612890f, + 0.524263153483673470f, 0.523609863834228030f, 0.522956266158590140f, + 0.522302360841254700f, + 0.521648148266897090f, 0.520993628820373810f, 0.520338802886721960f, + 0.519683670851158520f, + 0.519028233099080970f, 0.518372490016066220f, 0.517716441987871150f, + 0.517060089400432130f, + 0.516403432639863990f, 0.515746472092461380f, 0.515089208144697270f, + 0.514431641183222930f, + 0.513773771594868030f, 0.513115599766640560f, 0.512457126085725800f, + 0.511798350939487000f, + 0.511139274715464390f, 0.510479897801375700f, 0.509820220585115560f, + 0.509160243454754750f, + 0.508499966798540810f, 0.507839391004897940f, 0.507178516462425290f, + 0.506517343559898530f, + 0.505855872686268860f, 0.505194104230662240f, 0.504532038582380380f, + 0.503869676130898950f, + 0.503207017265869030f, 0.502544062377115800f, 0.501880811854638400f, + 0.501217266088609950f, + 0.500553425469377640f, 0.499889290387461380f, 0.499224861233555030f, + 0.498560138398525200f, + 0.497895122273410930f, 0.497229813249424340f, 0.496564211717949340f, + 0.495898318070542240f, + 0.495232132698931350f, 0.494565655995016010f, 0.493898888350867430f, + 0.493231830158728070f, + 0.492564481811010650f, 0.491896843700299240f, 0.491228916219348330f, + 0.490560699761082080f, + 0.489892194718595300f, 0.489223401485152030f, 0.488554320454186230f, + 0.487884952019301210f, + 0.487215296574268820f, 0.486545354513030270f, 0.485875126229695420f, + 0.485204612118541880f, + 0.484533812574016120f, 0.483862727990732320f, 0.483191358763471910f, + 0.482519705287184520f, + 0.481847767956986080f, 0.481175547168160360f, 0.480503043316157670f, + 0.479830256796594250f, + 0.479157188005253310f, 0.478483837338084080f, 0.477810205191201040f, + 0.477136291960884750f, + 0.476462098043581310f, 0.475787623835901120f, 0.475112869734620470f, + 0.474437836136679340f, + 0.473762523439182850f, 0.473086932039400220f, 0.472411062334764100f, + 0.471734914722871430f, + 0.471058489601482610f, 0.470381787368520710f, 0.469704808422072460f, + 0.469027553160387240f, + 0.468350021981876530f, 0.467672215285114710f, 0.466994133468838110f, + 0.466315776931944480f, + 0.465637146073493770f, 0.464958241292706740f, 0.464279062988965760f, + 0.463599611561814120f, + 0.462919887410955130f, 0.462239890936253280f, 0.461559622537733190f, + 0.460879082615578690f, + 0.460198271570134270f, 0.459517189801903590f, 0.458835837711549120f, + 0.458154215699893230f, + 0.457472324167916110f, 0.456790163516757220f, 0.456107734147714220f, + 0.455425036462242420f, + 0.454742070861955450f, 0.454058837748624540f, 0.453375337524177750f, + 0.452691570590700860f, + 0.452007537350436530f, 0.451323238205783520f, 0.450638673559297760f, + 0.449953843813690580f, + 0.449268749371829920f, 0.448583390636739300f, 0.447897768011597360f, + 0.447211881899738260f, + 0.446525732704651400f, 0.445839320829980350f, 0.445152646679523590f, + 0.444465710657234110f, + 0.443778513167218280f, 0.443091054613736990f, 0.442403335401204130f, + 0.441715355934187310f, + 0.441027116617407340f, 0.440338617855737300f, 0.439649860054203420f, + 0.438960843617984430f, + 0.438271568952410480f, 0.437582036462964340f, 0.436892246555280470f, + 0.436202199635143950f, + 0.435511896108492170f, 0.434821336381412350f, 0.434130520860143310f, + 0.433439449951074200f, + 0.432748124060743760f, 0.432056543595841450f, 0.431364708963206440f, + 0.430672620569826860f, + 0.429980278822840570f, 0.429287684129534720f, 0.428594836897344400f, + 0.427901737533854240f, + 0.427208386446796370f, 0.426514784044051520f, 0.425820930733648350f, + 0.425126826923762410f, + 0.424432473022717420f, 0.423737869438983950f, 0.423043016581179100f, + 0.422347914858067000f, + 0.421652564678558380f, 0.420956966451709440f, 0.420261120586723050f, + 0.419565027492946940f, + 0.418868687579875110f, 0.418172101257146430f, 0.417475268934544340f, + 0.416778191021997590f, + 0.416080867929579320f, 0.415383300067506290f, 0.414685487846140010f, + 0.413987431675985510f, + 0.413289131967690960f, 0.412590589132048380f, 0.411891803579992220f, + 0.411192775722600160f, + 0.410493505971092520f, 0.409793994736831200f, 0.409094242431320920f, + 0.408394249466208110f, + 0.407694016253280170f, 0.406993543204466460f, 0.406292830731837470f, + 0.405591879247603870f, + 0.404890689164117750f, 0.404189260893870750f, 0.403487594849495310f, + 0.402785691443763640f, + 0.402083551089587040f, 0.401381174200016790f, 0.400678561188243350f, + 0.399975712467595390f, + 0.399272628451540930f, 0.398569309553686360f, 0.397865756187775750f, + 0.397161968767691720f, + 0.396457947707453960f, 0.395753693421220080f, 0.395049206323284880f, + 0.394344486828079650f, + 0.393639535350172880f, 0.392934352304269600f, 0.392228938105210370f, + 0.391523293167972350f, + 0.390817417907668610f, 0.390111312739546910f, 0.389404978078991100f, + 0.388698414341519250f, + 0.387991621942784910f, 0.387284601298575890f, 0.386577352824813980f, + 0.385869876937555310f, + 0.385162174052989970f, 0.384454244587440870f, 0.383746088957365010f, + 0.383037707579352130f, + 0.382329100870124510f, 0.381620269246537520f, 0.380911213125578130f, + 0.380201932924366050f, + 0.379492429060152740f, 0.378782701950320600f, 0.378072752012383990f, + 0.377362579663988450f, + 0.376652185322909620f, 0.375941569407054420f, 0.375230732334460030f, + 0.374519674523293210f, + 0.373808396391851370f, 0.373096898358560690f, 0.372385180841977360f, + 0.371673244260786630f, + 0.370961089033802040f, 0.370248715579966360f, 0.369536124318350760f, + 0.368823315668153960f, + 0.368110290048703050f, 0.367397047879452820f, 0.366683589579984930f, + 0.365969915570008910f, + 0.365256026269360380f, 0.364541922098002180f, 0.363827603476023610f, + 0.363113070823639530f, + 0.362398324561191310f, 0.361683365109145950f, 0.360968192888095290f, + 0.360252808318756830f, + 0.359537211821973180f, 0.358821403818710860f, 0.358105384730061760f, + 0.357389154977241000f, + 0.356672714981588260f, 0.355956065164567010f, 0.355239205947763370f, + 0.354522137752887430f, + 0.353804861001772160f, 0.353087376116372530f, 0.352369683518766630f, + 0.351651783631154680f, + 0.350933676875858360f, 0.350215363675321740f, 0.349496844452109600f, + 0.348778119628908420f, + 0.348059189628525780f, 0.347340054873889190f, 0.346620715788047320f, + 0.345901172794169100f, + 0.345181426315542610f, 0.344461476775576480f, 0.343741324597798600f, + 0.343020970205855540f, + 0.342300414023513690f, 0.341579656474657210f, 0.340858697983289440f, + 0.340137538973531880f, + 0.339416179869623410f, 0.338694621095921190f, 0.337972863076899830f, + 0.337250906237150650f, + 0.336528751001382350f, 0.335806397794420560f, 0.335083847041206580f, + 0.334361099166798900f, + 0.333638154596370920f, 0.332915013755212650f, 0.332191677068729320f, + 0.331468144962440920f, + 0.330744417861982890f, 0.330020496193105530f, 0.329296380381672800f, + 0.328572070853663690f, + 0.327847568035170960f, 0.327122872352400510f, 0.326397984231672660f, + 0.325672904099419900f, + 0.324947632382188430f, 0.324222169506637130f, 0.323496515899536760f, + 0.322770671987770710f, + 0.322044638198334620f, 0.321318414958334910f, 0.320592002694990330f, + 0.319865401835630610f, + 0.319138612807695900f, 0.318411636038737960f, 0.317684471956418020f, + 0.316957120988508150f, + 0.316229583562890490f, 0.315501860107556040f, 0.314773951050606070f, + 0.314045856820250820f, + 0.313317577844809070f, 0.312589114552708660f, 0.311860467372486130f, + 0.311131636732785270f, + 0.310402623062358880f, 0.309673426790066490f, 0.308944048344875710f, + 0.308214488155861220f, + 0.307484746652204160f, 0.306754824263192780f, 0.306024721418221900f, + 0.305294438546791720f, + 0.304563976078509050f, 0.303833334443086470f, 0.303102514070341060f, + 0.302371515390196130f, + 0.301640338832678880f, 0.300908984827921890f, 0.300177453806162120f, + 0.299445746197739950f, + 0.298713862433100390f, 0.297981802942791920f, 0.297249568157465890f, + 0.296517158507877410f, + 0.295784574424884370f, 0.295051816339446720f, 0.294318884682627570f, + 0.293585779885591310f, + 0.292852502379604810f, 0.292119052596036540f, 0.291385430966355720f, + 0.290651637922133220f, + 0.289917673895040860f, 0.289183539316850310f, 0.288449234619434170f, + 0.287714760234765280f, + 0.286980116594915570f, 0.286245304132057120f, 0.285510323278461380f, + 0.284775174466498300f, + 0.284039858128637360f, 0.283304374697445790f, 0.282568724605589740f, + 0.281832908285833460f, + 0.281096926171038320f, 0.280360778694163810f, 0.279624466288266700f, + 0.278887989386500280f, + 0.278151348422115090f, 0.277414543828458200f, 0.276677576038972420f, + 0.275940445487197320f, + 0.275203152606767370f, 0.274465697831413220f, 0.273728081594960650f, + 0.272990304331329980f, + 0.272252366474536660f, 0.271514268458690810f, 0.270776010717996010f, + 0.270037593686750510f, + 0.269299017799346230f, 0.268560283490267890f, 0.267821391194094320f, + 0.267082341345496350f, + 0.266343134379238180f, 0.265603770730176440f, 0.264864250833259320f, + 0.264124575123527490f, + 0.263384744036113390f, 0.262644758006240100f, 0.261904617469222560f, + 0.261164322860466590f, + 0.260423874615468010f, 0.259683273169813930f, 0.258942518959180580f, + 0.258201612419334870f, + 0.257460553986133210f, 0.256719344095520720f, 0.255977983183532380f, + 0.255236471686291820f, + 0.254494810040010790f, 0.253752998680989940f, 0.253011038045617980f, + 0.252268928570370810f, + 0.251526670691812780f, 0.250784264846594550f, 0.250041711471454650f, + 0.249299011003218300f, + 0.248556163878796620f, 0.247813170535187620f, 0.247070031409475370f, + 0.246326746938829060f, + 0.245583317560504000f, 0.244839743711840750f, 0.244096025830264210f, + 0.243352164353284880f, + 0.242608159718496890f, 0.241864012363579210f, 0.241119722726294730f, + 0.240375291244489500f, + 0.239630718356093560f, 0.238886004499120170f, 0.238141150111664870f, + 0.237396155631906550f, + 0.236651021498106460f, 0.235905748148607370f, 0.235160336021834860f, + 0.234414785556295250f, + 0.233669097190576820f, 0.232923271363349120f, 0.232177308513361770f, + 0.231431209079445730f, + 0.230684973500512310f, 0.229938602215552260f, 0.229192095663636740f, + 0.228445454283916550f, + 0.227698678515621170f, 0.226951768798059980f, 0.226204725570620270f, + 0.225457549272768540f, + 0.224710240344049570f, 0.223962799224085520f, 0.223215226352576960f, + 0.222467522169301990f, + 0.221719687114115240f, 0.220971721626949060f, 0.220223626147812460f, + 0.219475401116790340f, + 0.218727046974044600f, 0.217978564159812290f, 0.217229953114406790f, + 0.216481214278216900f, + 0.215732348091705940f, 0.214983354995412820f, 0.214234235429951100f, + 0.213484989836008080f, + 0.212735618654345870f, 0.211986122325800410f, 0.211236501291280710f, + 0.210486755991769890f, + 0.209736886868323370f, 0.208986894362070070f, 0.208236778914211470f, + 0.207486540966020700f, + 0.206736180958843660f, 0.205985699334098050f, 0.205235096533272380f, + 0.204484372997927180f, + 0.203733529169694010f, 0.202982565490274460f, 0.202231482401441620f, + 0.201480280345037820f, + 0.200728959762976140f, 0.199977521097239290f, 0.199225964789878890f, + 0.198474291283016360f, + 0.197722501018842030f, 0.196970594439614370f, 0.196218571987660850f, + 0.195466434105377090f, + 0.194714181235225990f, 0.193961813819739010f, 0.193209332301514080f, + 0.192456737123216840f, + 0.191704028727579940f, 0.190951207557401860f, 0.190198274055548120f, + 0.189445228664950340f, + 0.188692071828605260f, 0.187938803989575850f, 0.187185425590990440f, + 0.186431937076041640f, + 0.185678338887987790f, 0.184924631470150870f, 0.184170815265917720f, + 0.183416890718739230f, + 0.182662858272129360f, 0.181908718369666160f, 0.181154471454990920f, + 0.180400117971807270f, + 0.179645658363882100f, 0.178891093075044830f, 0.178136422549186320f, + 0.177381647230260200f, + 0.176626767562280960f, 0.175871783989325040f, 0.175116696955530060f, + 0.174361506905093830f, + 0.173606214282275410f, 0.172850819531394200f, 0.172095323096829040f, + 0.171339725423019260f, + 0.170584026954463700f, 0.169828228135719880f, 0.169072329411405180f, + 0.168316331226194910f, + 0.167560234024823590f, 0.166804038252083870f, 0.166047744352825850f, + 0.165291352771957970f, + 0.164534863954446110f, 0.163778278345312690f, 0.163021596389637810f, + 0.162264818532558110f, + 0.161507945219266150f, 0.160750976895011390f, 0.159993914005098350f, + 0.159236756994887850f, + 0.158479506309796100f, 0.157722162395293690f, 0.156964725696906750f, + 0.156207196660216040f, + 0.155449575730855880f, 0.154691863354515400f, 0.153934059976937460f, + 0.153176166043917870f, + 0.152418182001306500f, 0.151660108295005400f, 0.150901945370970040f, + 0.150143693675208330f, + 0.149385353653779810f, 0.148626925752796540f, 0.147868410418422360f, + 0.147109808096871850f, + 0.146351119234411440f, 0.145592344277358450f, 0.144833483672080240f, + 0.144074537864995330f, + 0.143315507302571590f, 0.142556392431327340f, 0.141797193697830530f, + 0.141037911548697770f, + 0.140278546430595420f, 0.139519098790238600f, 0.138759569074390380f, + 0.137999957729862760f, + 0.137240265203515700f, 0.136480491942256310f, 0.135720638393040080f, + 0.134960705002868830f, + 0.134200692218792020f, 0.133440600487905820f, 0.132680430257352130f, + 0.131920181974319760f, + 0.131159856086043410f, 0.130399453039802740f, 0.129638973282923540f, + 0.128878417262776660f, + 0.128117785426777150f, 0.127357078222385570f, 0.126596296097105960f, + 0.125835439498487020f, + 0.125074508874121300f, 0.124313504671644300f, 0.123552427338735370f, + 0.122791277323116900f, + 0.122030055072553410f, 0.121268761034852550f, 0.120507395657864240f, + 0.119745959389479630f, + 0.118984452677632520f, 0.118222875970297250f, 0.117461229715489990f, + 0.116699514361267840f, + 0.115937730355727850f, 0.115175878147008180f, 0.114413958183287050f, + 0.113651970912781920f, + 0.112889916783750470f, 0.112127796244489750f, 0.111365609743335190f, + 0.110603357728661910f, + 0.109841040648882680f, 0.109078658952449240f, 0.108316213087851300f, + 0.107553703503615710f, + 0.106791130648307380f, 0.106028494970528530f, 0.105265796918917650f, + 0.104503036942150550f, + 0.103740215488939480f, 0.102977333008032250f, 0.102214389948213370f, + 0.101451386758302160f, + 0.100688323887153970f, 0.099925201783659226f, 0.099162020896742573f, + 0.098398781675363881f, + 0.097635484568517339f, 0.096872130025230527f, 0.096108718494565468f, + 0.095345250425617742f, + 0.094581726267515473f, 0.093818146469420494f, 0.093054511480527333f, + 0.092290821750062355f, + 0.091527077727284981f, 0.090763279861485704f, 0.089999428601987341f, + 0.089235524398144139f, + 0.088471567699340822f, 0.087707558954993645f, 0.086943498614549489f, + 0.086179387127484922f, + 0.085415224943307277f, 0.084651012511553700f, 0.083886750281790226f, + 0.083122438703613077f, + 0.082358078226646619f, 0.081593669300544638f, 0.080829212374989468f, + 0.080064707899690932f, + 0.079300156324387569f, 0.078535558098845590f, 0.077770913672857989f, + 0.077006223496245585f, + 0.076241488018856149f, 0.075476707690563416f, 0.074711882961268378f, + 0.073947014280897269f, + 0.073182102099402888f, 0.072417146866763538f, 0.071652149032982254f, + 0.070887109048087787f, + 0.070122027362133646f, 0.069356904425197236f, 0.068591740687380900f, + 0.067826536598810966f, + 0.067061292609636836f, 0.066296009170032283f, 0.065530686730193397f, + 0.064765325740339871f, + 0.063999926650714078f, 0.063234489911580136f, 0.062469015973224969f, + 0.061703505285957416f, + 0.060937958300107238f, 0.060172375466026218f, 0.059406757234087247f, + 0.058641104054683348f, + 0.057875416378229017f, 0.057109694655158132f, 0.056343939335925283f, + 0.055578150871004817f, + 0.054812329710889909f, 0.054046476306093640f, 0.053280591107148056f, + 0.052514674564603257f, + 0.051748727129028414f, 0.050982749251010900f, 0.050216741381155325f, + 0.049450703970084824f, + 0.048684637468439020f, 0.047918542326875327f, 0.047152418996068000f, + 0.046386267926707213f, + 0.045620089569500123f, 0.044853884375169933f, 0.044087652794454979f, + 0.043321395278109784f, + 0.042555112276904117f, 0.041788804241622082f, 0.041022471623063397f, + 0.040256114872041358f, + 0.039489734439384118f, 0.038723330775933762f, 0.037956904332545366f, + 0.037190455560088091f, + 0.036423984909444228f, 0.035657492831508264f, 0.034890979777187955f, + 0.034124446197403423f, + 0.033357892543086159f, 0.032591319265180385f, 0.031824726814640963f, + 0.031058115642434700f, + 0.030291486199539423f, 0.029524838936943035f, 0.028758174305644590f, + 0.027991492756653365f, + 0.027224794740987910f, 0.026458080709677145f, 0.025691351113759395f, + 0.024924606404281485f, + 0.024157847032300020f, 0.023391073448879338f, 0.022624286105092803f, + 0.021857485452021874f, + 0.021090671940755180f, 0.020323846022389572f, 0.019557008148029204f, + 0.018790158768784596f, + 0.018023298335773701f, 0.017256427300120978f, 0.016489546112956454f, + 0.015722655225417017f, + 0.014955755088644378f, 0.014188846153786343f, 0.013421928871995907f, + 0.012655003694430301f, + 0.011888071072252072f, 0.011121131456628141f, 0.010354185298728884f, + 0.009587233049729183f, + 0.008820275160807512f, 0.008053312083144991f, 0.007286344267926684f, + 0.006519372166339549f, + 0.005752396229573737f, 0.004985416908821652f, 0.004218434655277024f, + 0.003451449920135975f, + 0.002684463154596083f, 0.001917474809855460f, 0.001150485337113809f, + 0.000383495187571497f +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192) + const float32_t Weights_8192[16384] = { + 1.000000000000000000f, -0.000000000000000000f, 0.999999981616429330f, + -0.000191747597310703f, + 0.999999926465717890f, -0.000383495187571396f, 0.999999834547867670f, + -0.000575242763732066f, + 0.999999705862882230f, -0.000766990318742704f, 0.999999540410766110f, + -0.000958737845553301f, + 0.999999338191525530f, -0.001150485337113849f, 0.999999099205167830f, + -0.001342232786374338f, + 0.999998823451701880f, -0.001533980186284766f, 0.999998510931137790f, + -0.001725727529795126f, + 0.999998161643486980f, -0.001917474809855419f, 0.999997775588762350f, + -0.002109222019415644f, + 0.999997352766978210f, -0.002300969151425805f, 0.999996893178149880f, + -0.002492716198835908f, + 0.999996396822294350f, -0.002684463154595962f, 0.999995863699429940f, + -0.002876210011655979f, + 0.999995293809576190f, -0.003067956762965976f, 0.999994687152754080f, + -0.003259703401475973f, + 0.999994043728985820f, -0.003451449920135994f, 0.999993363538295150f, + -0.003643196311896068f, + 0.999992646580707190f, -0.003834942569706228f, 0.999991892856248010f, + -0.004026688686516512f, + 0.999991102364945590f, -0.004218434655276963f, 0.999990275106828920f, + -0.004410180468937631f, + 0.999989411081928400f, -0.004601926120448571f, 0.999988510290275690f, + -0.004793671602759841f, + 0.999987572731904080f, -0.004985416908821511f, 0.999986598406848000f, + -0.005177162031583651f, + 0.999985587315143200f, -0.005368906963996343f, 0.999984539456826970f, + -0.005560651699009674f, + 0.999983454831937730f, -0.005752396229573736f, 0.999982333440515350f, + -0.005944140548638633f, + 0.999981175282601110f, -0.006135884649154475f, 0.999979980358237650f, + -0.006327628524071378f, + 0.999978748667468830f, -0.006519372166339468f, 0.999977480210339940f, + -0.006711115568908879f, + 0.999976174986897610f, -0.006902858724729756f, 0.999974832997189810f, + -0.007094601626752250f, + 0.999973454241265940f, -0.007286344267926521f, 0.999972038719176730f, + -0.007478086641202744f, + 0.999970586430974140f, -0.007669828739531097f, 0.999969097376711580f, + -0.007861570555861772f, + 0.999967571556443780f, -0.008053312083144972f, 0.999966008970226920f, + -0.008245053314330906f, + 0.999964409618118280f, -0.008436794242369799f, 0.999962773500176930f, + -0.008628534860211886f, + 0.999961100616462820f, -0.008820275160807412f, 0.999959390967037450f, + -0.009012015137106633f, + 0.999957644551963900f, -0.009203754782059819f, 0.999955861371306100f, + -0.009395494088617252f, + 0.999954041425129780f, -0.009587233049729225f, 0.999952184713501780f, + -0.009778971658346044f, + 0.999950291236490480f, -0.009970709907418031f, 0.999948360994165400f, + -0.010162447789895513f, + 0.999946393986597460f, -0.010354185298728842f, 0.999944390213859060f, + -0.010545922426868378f, + 0.999942349676023910f, -0.010737659167264491f, 0.999940272373166960f, + -0.010929395512867571f, + 0.999938158305364590f, -0.011121131456628021f, 0.999936007472694620f, + -0.011312866991496258f, + 0.999933819875236000f, -0.011504602110422714f, 0.999931595513069200f, + -0.011696336806357838f, + 0.999929334386276070f, -0.011888071072252092f, 0.999927036494939640f, + -0.012079804901055957f, + 0.999924701839144500f, -0.012271538285719925f, 0.999922330418976490f, + -0.012463271219194511f, + 0.999919922234522750f, -0.012655003694430242f, 0.999917477285871770f, + -0.012846735704377662f, + 0.999914995573113470f, -0.013038467241987334f, 0.999912477096339240f, + -0.013230198300209835f, + 0.999909921855641540f, -0.013421928871995765f, 0.999907329851114300f, + -0.013613658950295740f, + 0.999904701082852900f, -0.013805388528060391f, 0.999902035550953920f, + -0.013997117598240367f, + 0.999899333255515390f, -0.014188846153786345f, 0.999896594196636680f, + -0.014380574187649006f, + 0.999893818374418490f, -0.014572301692779064f, 0.999891005788962950f, + -0.014764028662127246f, + 0.999888156440373320f, -0.014955755088644296f, 0.999885270328754520f, + -0.015147480965280987f, + 0.999882347454212560f, -0.015339206284988100f, 0.999879387816854930f, + -0.015530931040716447f, + 0.999876391416790410f, -0.015722655225416857f, 0.999873358254129260f, + -0.015914378832040183f, + 0.999870288328982950f, -0.016106101853537287f, 0.999867181641464380f, + -0.016297824282859065f, + 0.999864038191687680f, -0.016489546112956437f, 0.999860857979768540f, + -0.016681267336780332f, + 0.999857641005823860f, -0.016872987947281710f, 0.999854387269971890f, + -0.017064707937411563f, + 0.999851096772332190f, -0.017256427300120877f, 0.999847769513025900f, + -0.017448146028360693f, + 0.999844405492175240f, -0.017639864115082053f, 0.999841004709904000f, + -0.017831581553236039f, + 0.999837567166337090f, -0.018023298335773746f, 0.999834092861600960f, + -0.018215014455646290f, + 0.999830581795823400f, -0.018406729905804820f, 0.999827033969133420f, + -0.018598444679200511f, + 0.999823449381661570f, -0.018790158768784555f, 0.999819828033539420f, + -0.018981872167508178f, + 0.999816169924900410f, -0.019173584868322623f, 0.999812475055878780f, + -0.019365296864179156f, + 0.999808743426610520f, -0.019557008148029083f, 0.999804975037232870f, + -0.019748718712823729f, + 0.999801169887884260f, -0.019940428551514441f, 0.999797327978704690f, + -0.020132137657052594f, + 0.999793449309835270f, -0.020323846022389593f, 0.999789533881418780f, + -0.020515553640476875f, + 0.999785581693599210f, -0.020707260504265895f, 0.999781592746521670f, + -0.020898966606708137f, + 0.999777567040332940f, -0.021090671940755121f, 0.999773504575180990f, + -0.021282376499358387f, + 0.999769405351215280f, -0.021474080275469508f, 0.999765269368586450f, + -0.021665783262040078f, + 0.999761096627446610f, -0.021857485452021735f, 0.999756887127949080f, + -0.022049186838366135f, + 0.999752640870248840f, -0.022240887414024961f, 0.999748357854501780f, + -0.022432587171949934f, + 0.999744038080865430f, -0.022624286105092803f, 0.999739681549498660f, + -0.022815984206405345f, + 0.999735288260561680f, -0.023007681468839369f, 0.999730858214216030f, + -0.023199377885346720f, + 0.999726391410624470f, -0.023391073448879258f, 0.999721887849951310f, + -0.023582768152388894f, + 0.999717347532362190f, -0.023774461988827555f, 0.999712770458023870f, + -0.023966154951147210f, + 0.999708156627104880f, -0.024157847032299864f, 0.999703506039774650f, + -0.024349538225237534f, + 0.999698818696204250f, -0.024541228522912288f, 0.999694094596566000f, + -0.024732917918276223f, + 0.999689333741033640f, -0.024924606404281468f, 0.999684536129782140f, + -0.025116293973880186f, + 0.999679701762987930f, -0.025307980620024571f, 0.999674830640828740f, + -0.025499666335666853f, + 0.999669922763483760f, -0.025691351113759295f, 0.999664978131133310f, + -0.025883034947254198f, + 0.999659996743959220f, -0.026074717829103901f, 0.999654978602144690f, + -0.026266399752260760f, + 0.999649923705874240f, -0.026458080709677187f, 0.999644832055333610f, + -0.026649760694305618f, + 0.999639703650710200f, -0.026841439699098531f, 0.999634538492192300f, + -0.027033117717008431f, + 0.999629336579970110f, -0.027224794740987875f, 0.999624097914234570f, + -0.027416470763989436f, + 0.999618822495178640f, -0.027608145778965740f, 0.999613510322995950f, + -0.027799819778869445f, + 0.999608161397882110f, -0.027991492756653243f, 0.999602775720033530f, + -0.028183164705269874f, + 0.999597353289648380f, -0.028374835617672099f, 0.999591894106925950f, + -0.028566505486812728f, + 0.999586398172067070f, -0.028758174305644615f, 0.999580865485273700f, + -0.028949842067120635f, + 0.999575296046749220f, -0.029141508764193722f, 0.999569689856698580f, + -0.029333174389816835f, + 0.999564046915327740f, -0.029524838936942976f, 0.999558367222844300f, + -0.029716502398525191f, + 0.999552650779456990f, -0.029908164767516555f, 0.999546897585375960f, + -0.030099826036870198f, + 0.999541107640812940f, -0.030291486199539284f, 0.999535280945980540f, + -0.030483145248477009f, + 0.999529417501093140f, -0.030674803176636626f, 0.999523517306366350f, + -0.030866459976971412f, + 0.999517580362016990f, -0.031058115642434700f, 0.999511606668263440f, + -0.031249770165979861f, + 0.999505596225325310f, -0.031441423540560301f, 0.999499549033423640f, + -0.031633075759129478f, + 0.999493465092780590f, -0.031824726814640887f, 0.999487344403620080f, + -0.032016376700048060f, + 0.999481186966166950f, -0.032208025408304586f, 0.999474992780647780f, + -0.032399672932364086f, + 0.999468761847290050f, -0.032591319265180226f, 0.999462494166323160f, + -0.032782964399706724f, + 0.999456189737977340f, -0.032974608328897335f, 0.999449848562484530f, + -0.033166251045705857f, + 0.999443470640077770f, -0.033357892543086139f, 0.999437055970991530f, + -0.033549532813992068f, + 0.999430604555461730f, -0.033741171851377580f, 0.999424116393725640f, + -0.033932809648196664f, + 0.999417591486021720f, -0.034124446197403326f, 0.999411029832589780f, + -0.034316081491951651f, + 0.999404431433671300f, -0.034507715524795750f, 0.999397796289508640f, + -0.034699348288889799f, + 0.999391124400346050f, -0.034890979777188004f, 0.999384415766428560f, + -0.035082609982644619f, + 0.999377670388002850f, -0.035274238898213947f, 0.999370888265317170f, + -0.035465866516850353f, + 0.999364069398620550f, -0.035657492831508222f, 0.999357213788164000f, + -0.035849117835142018f, + 0.999350321434199440f, -0.036040741520706229f, 0.999343392336980220f, + -0.036232363881155395f, + 0.999336426496761240f, -0.036423984909444110f, 0.999329423913798420f, + -0.036615604598527030f, + 0.999322384588349540f, -0.036807222941358832f, 0.999315308520673070f, + -0.036998839930894263f, + 0.999308195711029470f, -0.037190455560088119f, 0.999301046159680070f, + -0.037382069821895229f, + 0.999293859866887790f, -0.037573682709270494f, 0.999286636832916740f, + -0.037765294215168860f, + 0.999279377058032710f, -0.037956904332545310f, 0.999272080542502610f, + -0.038148513054354891f, + 0.999264747286594420f, -0.038340120373552694f, 0.999257377290578060f, + -0.038531726283093870f, + 0.999249970554724420f, -0.038723330775933623f, 0.999242527079305830f, + -0.038914933845027193f, + 0.999235046864595850f, -0.039106535483329888f, 0.999227529910869610f, + -0.039298135683797059f, + 0.999219976218403530f, -0.039489734439384118f, 0.999212385787475290f, + -0.039681331743046527f, + 0.999204758618363890f, -0.039872927587739811f, 0.999197094711349880f, + -0.040064521966419520f, + 0.999189394066714920f, -0.040256114872041282f, 0.999181656684742350f, + -0.040447706297560782f, + 0.999173882565716380f, -0.040639296235933736f, 0.999166071709923000f, + -0.040830884680115948f, + 0.999158224117649430f, -0.041022471623063238f, 0.999150339789184110f, + -0.041214057057731519f, + 0.999142418724816910f, -0.041405640977076739f, 0.999134460924839150f, + -0.041597223374054894f, + 0.999126466389543390f, -0.041788804241622061f, 0.999118435119223490f, + -0.041980383572734356f, + 0.999110367114174890f, -0.042171961360347947f, 0.999102262374694130f, + -0.042363537597419072f, + 0.999094120901079070f, -0.042555112276904020f, 0.999085942693629270f, + -0.042746685391759132f, + 0.999077727752645360f, -0.042938256934940820f, 0.999069476078429330f, + -0.043129826899405546f, + 0.999061187671284600f, -0.043321395278109825f, 0.999052862531515930f, + -0.043512962064010237f, + 0.999044500659429290f, -0.043704527250063421f, 0.999036102055332330f, + -0.043896090829226068f, + 0.999027666719533690f, -0.044087652794454944f, 0.999019194652343460f, + -0.044279213138706849f, + 0.999010685854073380f, -0.044470771854938668f, 0.999002140325035980f, + -0.044662328936107325f, + 0.998993558065545680f, -0.044853884375169815f, 0.998984939075918010f, + -0.045045438165083197f, + 0.998976283356469820f, -0.045236990298804590f, 0.998967590907519300f, + -0.045428540769291155f, + 0.998958861729386080f, -0.045620089569500144f, 0.998950095822391250f, + -0.045811636692388844f, + 0.998941293186856870f, -0.046003182130914623f, 0.998932453823106690f, + -0.046194725878034908f, + 0.998923577731465780f, -0.046386267926707157f, 0.998914664912260440f, + -0.046577808269888943f, + 0.998905715365818290f, -0.046769346900537863f, 0.998896729092468410f, + -0.046960883811611592f, + 0.998887706092541290f, -0.047152418996067869f, 0.998878646366368690f, + -0.047343952446864478f, + 0.998869549914283560f, -0.047535484156959303f, 0.998860416736620520f, + -0.047727014119310254f, + 0.998851246833715180f, -0.047918542326875327f, 0.998842040205904840f, + -0.048110068772612591f, + 0.998832796853527990f, -0.048301593449480144f, 0.998823516776924490f, + -0.048493116350436176f, + 0.998814199976435390f, -0.048684637468438943f, 0.998804846452403420f, + -0.048876156796446760f, + 0.998795456205172410f, -0.049067674327418015f, 0.998786029235087640f, + -0.049259190054311140f, + 0.998776565542495610f, -0.049450703970084664f, 0.998767065127744380f, + -0.049642216067697156f, + 0.998757527991183340f, -0.049833726340107277f, 0.998747954133162860f, + -0.050025234780273729f, + 0.998738343554035230f, -0.050216741381155311f, 0.998728696254153720f, + -0.050408246135710856f, + 0.998719012233872940f, -0.050599749036899282f, 0.998709291493549030f, + -0.050791250077679581f, + 0.998699534033539280f, -0.050982749251010803f, 0.998689739854202620f, + -0.051174246549852080f, + 0.998679908955899090f, -0.051365741967162593f, 0.998670041338990070f, + -0.051557235495901611f, + 0.998660137003838490f, -0.051748727129028456f, 0.998650195950808280f, + -0.051940216859502536f, + 0.998640218180265270f, -0.052131704680283324f, 0.998630203692576050f, + -0.052323190584330347f, + 0.998620152488108870f, -0.052514674564603223f, 0.998610064567233340f, + -0.052706156614061632f, + 0.998599939930320370f, -0.052897636725665324f, 0.998589778577742230f, + -0.053089114892374133f, + 0.998579580509872500f, -0.053280591107147945f, 0.998569345727086110f, + -0.053472065362946727f, + 0.998559074229759310f, -0.053663537652730520f, 0.998548766018269920f, + -0.053855007969459440f, + 0.998538421092996730f, -0.054046476306093660f, 0.998528039454320230f, + -0.054237942655593452f, + 0.998517621102622210f, -0.054429407010919133f, 0.998507166038285490f, + -0.054620869365031105f, + 0.998496674261694640f, -0.054812329710889854f, 0.998486145773235360f, + -0.055003788041455920f, + 0.998475580573294770f, -0.055195244349689934f, 0.998464978662261250f, + -0.055386698628552597f, + 0.998454340040524800f, -0.055578150871004678f, 0.998443664708476340f, + -0.055769601070007030f, + 0.998432952666508440f, -0.055961049218520569f, 0.998422203915015020f, + -0.056152495309506292f, + 0.998411418454391300f, -0.056343939335925290f, 0.998400596285033640f, + -0.056535381290738700f, + 0.998389737407340160f, -0.056726821166907748f, 0.998378841821709990f, + -0.056918258957393740f, + 0.998367909528543820f, -0.057109694655158062f, 0.998356940528243420f, + -0.057301128253162158f, + 0.998345934821212370f, -0.057492559744367566f, 0.998334892407855000f, + -0.057683989121735904f, + 0.998323813288577560f, -0.057875416378228857f, 0.998312697463787260f, + -0.058066841506808194f, + 0.998301544933892890f, -0.058258264500435752f, 0.998290355699304350f, + -0.058449685352073476f, + 0.998279129760433200f, -0.058641104054683341f, 0.998267867117692110f, + -0.058832520601227435f, + 0.998256567771495180f, -0.059023934984667931f, 0.998245231722257880f, + -0.059215347197967061f, + 0.998233858970396850f, -0.059406757234087150f, 0.998222449516330550f, + -0.059598165085990591f, + 0.998211003360478190f, -0.059789570746639868f, 0.998199520503260660f, + -0.059980974208997548f, + 0.998188000945100300f, -0.060172375466026259f, 0.998176444686420530f, + -0.060363774510688743f, + 0.998164851727646240f, -0.060555171335947788f, 0.998153222069203760f, + -0.060746565934766288f, + 0.998141555711520520f, -0.060937958300107203f, 0.998129852655025630f, + -0.061129348424933588f, + 0.998118112900149180f, -0.061320736302208578f, 0.998106336447323050f, + -0.061512121924895378f, + 0.998094523296980010f, -0.061703505285957298f, 0.998082673449554590f, + -0.061894886378357716f, + 0.998070786905482340f, -0.062086265195060088f, 0.998058863665200250f, + -0.062277641729027972f, + 0.998046903729146840f, -0.062469015973224996f, 0.998034907097761770f, + -0.062660387920614874f, + 0.998022873771486240f, -0.062851757564161406f, 0.998010803750762450f, + -0.063043124896828492f, + 0.997998697036034390f, -0.063234489911580066f, 0.997986553627747020f, + -0.063425852601380228f, + 0.997974373526346990f, -0.063617212959193106f, 0.997962156732281950f, + -0.063808570977982898f, + 0.997949903246001190f, -0.063999926650713940f, 0.997937613067955250f, + -0.064191279970350637f, + 0.997925286198596000f, -0.064382630929857465f, 0.997912922638376610f, + -0.064573979522198982f, + 0.997900522387751620f, -0.064765325740339885f, 0.997888085447177110f, + -0.064956669577244872f, + 0.997875611817110150f, -0.065148011025878833f, 0.997863101498009500f, + -0.065339350079206632f, + 0.997850554490335110f, -0.065530686730193327f, 0.997837970794548280f, + -0.065722020971803990f, + 0.997825350411111640f, -0.065913352797003805f, 0.997812693340489280f, + -0.066104682198758077f, + 0.997799999583146470f, -0.066296009170032130f, 0.997787269139549960f, + -0.066487333703791451f, + 0.997774502010167820f, -0.066678655793001557f, 0.997761698195469560f, + -0.066869975430628115f, + 0.997748857695925690f, -0.067061292609636822f, 0.997735980512008620f, + -0.067252607322993499f, + 0.997723066644191640f, -0.067443919563664051f, 0.997710116092949570f, + -0.067635229324614479f, + 0.997697128858758500f, -0.067826536598810869f, 0.997684104942096030f, + -0.068017841379219388f, + 0.997671044343441000f, -0.068209143658806329f, 0.997657947063273710f, + -0.068400443430538013f, + 0.997644813102075420f, -0.068591740687380942f, 0.997631642460329320f, + -0.068783035422301630f, + 0.997618435138519550f, -0.068974327628266746f, 0.997605191137131640f, + -0.069165617298242985f, + 0.997591910456652630f, -0.069356904425197208f, 0.997578593097570800f, + -0.069548189002096306f, + 0.997565239060375750f, -0.069739471021907307f, 0.997551848345558430f, + -0.069930750477597309f, + 0.997538420953611340f, -0.070122027362133521f, 0.997524956885027960f, + -0.070313301668483250f, + 0.997511456140303450f, -0.070504573389613856f, 0.997497918719934210f, + -0.070695842518492855f, + 0.997484344624417930f, -0.070887109048087801f, 0.997470733854253670f, + -0.071078372971366405f, + 0.997457086409941910f, -0.071269634281296401f, 0.997443402291984360f, + -0.071460892970845680f, + 0.997429681500884180f, -0.071652149032982212f, 0.997415924037145960f, + -0.071843402460674027f, + 0.997402129901275300f, -0.072034653246889332f, 0.997388299093779460f, + -0.072225901384596322f, + 0.997374431615167150f, -0.072417146866763413f, 0.997360527465947940f, + -0.072608389686358993f, + 0.997346586646633230f, -0.072799629836351673f, 0.997332609157735470f, + -0.072990867309710036f, + 0.997318594999768600f, -0.073182102099402888f, 0.997304544173247990f, + -0.073373334198399032f, + 0.997290456678690210f, -0.073564563599667426f, 0.997276332516613180f, + -0.073755790296177098f, + 0.997262171687536170f, -0.073947014280897200f, 0.997247974191979860f, + -0.074138235546796979f, + 0.997233740030466280f, -0.074329454086845756f, 0.997219469203518670f, + -0.074520669894013000f, + 0.997205161711661850f, -0.074711882961268211f, 0.997190817555421940f, + -0.074903093281581082f, + 0.997176436735326190f, -0.075094300847921305f, 0.997162019251903290f, + -0.075285505653258769f, + 0.997147565105683480f, -0.075476707690563388f, 0.997133074297198110f, + -0.075667906952805231f, + 0.997118546826979980f, -0.075859103432954447f, 0.997103982695563330f, + -0.076050297123981259f, + 0.997089381903483400f, -0.076241488018856066f, 0.997074744451277310f, + -0.076432676110549283f, + 0.997060070339482960f, -0.076623861392031492f, 0.997045359568640040f, + -0.076815043856273343f, + 0.997030612139289450f, -0.077006223496245640f, 0.997015828051973310f, + -0.077197400304919200f, + 0.997001007307235290f, -0.077388574275265049f, 0.996986149905620180f, + -0.077579745400254224f, + 0.996971255847674320f, -0.077770913672857947f, 0.996956325133945280f, + -0.077962079086047492f, + 0.996941357764982160f, -0.078153241632794232f, 0.996926353741335090f, + -0.078344401306069705f, + 0.996911313063555740f, -0.078535558098845479f, 0.996896235732197210f, + -0.078726712004093299f, + 0.996881121747813850f, -0.078917863014784942f, 0.996865971110961310f, + -0.079109011123892375f, + 0.996850783822196610f, -0.079300156324387597f, 0.996835559882078170f, + -0.079491298609242769f, + 0.996820299291165670f, -0.079682437971430126f, 0.996805002050020430f, + -0.079873574403921996f, + 0.996789668159204560f, -0.080064707899690890f, 0.996774297619282050f, + -0.080255838451709319f, + 0.996758890430818000f, -0.080446966052950014f, 0.996743446594378860f, + -0.080638090696385709f, + 0.996727966110532490f, -0.080829212374989329f, 0.996712448979848010f, + -0.081020331081733857f, + 0.996696895202896060f, -0.081211446809592441f, 0.996681304780248300f, + -0.081402559551538245f, + 0.996665677712478160f, -0.081593669300544652f, 0.996650014000160070f, + -0.081784776049585076f, + 0.996634313643869900f, -0.081975879791633066f, 0.996618576644185070f, + -0.082166980519662314f, + 0.996602803001684130f, -0.082358078226646536f, 0.996586992716946950f, + -0.082549172905559673f, + 0.996571145790554840f, -0.082740264549375692f, 0.996555262223090540f, + -0.082931353151068699f, + 0.996539342015137940f, -0.083122438703612911f, 0.996523385167282450f, + -0.083313521199982685f, + 0.996507391680110820f, -0.083504600633152432f, 0.996491361554210920f, + -0.083695676996096716f, + 0.996475294790172160f, -0.083886750281790226f, 0.996459191388585410f, + -0.084077820483207694f, + 0.996443051350042630f, -0.084268887593324071f, 0.996426874675137240f, + -0.084459951605114325f, + 0.996410661364464100f, -0.084651012511553617f, 0.996394411418619290f, + -0.084842070305617134f, + 0.996378124838200210f, -0.085033124980280275f, 0.996361801623805720f, + -0.085224176528518478f, + 0.996345441776035900f, -0.085415224943307333f, 0.996329045295492380f, + -0.085606270217622529f, + 0.996312612182778000f, -0.085797312344439894f, 0.996296142438496850f, + -0.085988351316735337f, + 0.996279636063254650f, -0.086179387127484894f, 0.996263093057658140f, + -0.086370419769664752f, + 0.996246513422315520f, -0.086561449236251170f, 0.996229897157836500f, + -0.086752475520220543f, + 0.996213244264832040f, -0.086943498614549378f, 0.996196554743914220f, + -0.087134518512214307f, + 0.996179828595696980f, -0.087325535206192059f, 0.996163065820794950f, + -0.087516548689459531f, + 0.996146266419824620f, -0.087707558954993659f, 0.996129430393403740f, + -0.087898565995771588f, + 0.996112557742151130f, -0.088089569804770507f, 0.996095648466687300f, + -0.088280570374967740f, + 0.996078702567633980f, -0.088471567699340767f, 0.996061720045614000f, + -0.088662561770867149f, + 0.996044700901251970f, -0.088853552582524600f, 0.996027645135173610f, + -0.089044540127290892f, + 0.996010552748005870f, -0.089235524398144014f, 0.995993423740377360f, + -0.089426505388061961f, + 0.995976258112917790f, -0.089617483090022959f, 0.995959055866258320f, + -0.089808457497005278f, + 0.995941817001031350f, -0.089999428601987341f, 0.995924541517870800f, + -0.090190396397947695f, + 0.995907229417411720f, -0.090381360877864983f, 0.995889880700290720f, + -0.090572322034717989f, + 0.995872495367145730f, -0.090763279861485621f, 0.995855073418615790f, + -0.090954234351146926f, + 0.995837614855341610f, -0.091145185496681005f, 0.995820119677964910f, + -0.091336133291067184f, + 0.995802587887129160f, -0.091527077727284828f, 0.995785019483478750f, + -0.091718018798313455f, + 0.995767414467659820f, -0.091908956497132724f, 0.995749772840319510f, + -0.092099890816722388f, + 0.995732094602106430f, -0.092290821750062355f, 0.995714379753670610f, + -0.092481749290132600f, + 0.995696628295663520f, -0.092672673429913310f, 0.995678840228737540f, + -0.092863594162384724f, + 0.995661015553546910f, -0.093054511480527249f, 0.995643154270746900f, + -0.093245425377321375f, + 0.995625256380994310f, -0.093436335845747787f, 0.995607321884947050f, + -0.093627242878787195f, + 0.995589350783264600f, -0.093818146469420549f, 0.995571343076607770f, + -0.094009046610628838f, + 0.995553298765638470f, -0.094199943295393204f, 0.995535217851020390f, + -0.094390836516694943f, + 0.995517100333418110f, -0.094581726267515445f, 0.995498946213497770f, + -0.094772612540836243f, + 0.995480755491926940f, -0.094963495329638992f, 0.995462528169374420f, + -0.095154374626905486f, + 0.995444264246510340f, -0.095345250425617617f, 0.995425963724006160f, + -0.095536122718757471f, + 0.995407626602534900f, -0.095726991499307162f, 0.995389252882770690f, + -0.095917856760249040f, + 0.995370842565388990f, -0.096108718494565509f, 0.995352395651066810f, + -0.096299576695239128f, + 0.995333912140482280f, -0.096490431355252593f, 0.995315392034315070f, + -0.096681282467588725f, + 0.995296835333246090f, -0.096872130025230471f, 0.995278242037957670f, + -0.097062974021160917f, + 0.995259612149133390f, -0.097253814448363271f, 0.995240945667458130f, + -0.097444651299820870f, + 0.995222242593618360f, -0.097635484568517200f, 0.995203502928301510f, + -0.097826314247435861f, + 0.995184726672196930f, -0.098017140329560604f, 0.995165913825994620f, + -0.098207962807875276f, + 0.995147064390386470f, -0.098398781675363881f, 0.995128178366065490f, + -0.098589596925010584f, + 0.995109255753726110f, -0.098780408549799623f, 0.995090296554064000f, + -0.098971216542715429f, + 0.995071300767776170f, -0.099162020896742503f, 0.995052268395561050f, + -0.099352821604865540f, + 0.995033199438118630f, -0.099543618660069319f, 0.995014093896149700f, + -0.099734412055338825f, + 0.994994951770357020f, -0.099925201783659073f, 0.994975773061444140f, + -0.100115987838015310f, + 0.994956557770116380f, -0.100306770211392860f, 0.994937305897080070f, + -0.100497548896777200f, + 0.994918017443043200f, -0.100688323887153960f, 0.994898692408714870f, + -0.100879095175508860f, + 0.994879330794805620f, -0.101069862754827820f, 0.994859932602027320f, + -0.101260626618096830f, + 0.994840497831093180f, -0.101451386758302080f, 0.994821026482717860f, + -0.101642143168429830f, + 0.994801518557617110f, -0.101832895841466530f, 0.994781974056508260f, + -0.102023644770398740f, + 0.994762392980109930f, -0.102214389948213210f, 0.994742775329142010f, + -0.102405131367896720f, + 0.994723121104325700f, -0.102595869022436280f, 0.994703430306383860f, + -0.102786602904819040f, + 0.994683702936040250f, -0.102977333008032220f, 0.994663938994020390f, + -0.103168059325063230f, + 0.994644138481050710f, -0.103358781848899610f, 0.994624301397859400f, + -0.103549500572529070f, + 0.994604427745175660f, -0.103740215488939370f, 0.994584517523730340f, + -0.103930926591118510f, + 0.994564570734255420f, -0.104121633872054590f, 0.994544587377484300f, + -0.104312337324735800f, + 0.994524567454151740f, -0.104503036942150570f, 0.994504510964993700f, + -0.104693732717287390f, + 0.994484417910747600f, -0.104884424643134970f, 0.994464288292152390f, + -0.105075112712682040f, + 0.994444122109948040f, -0.105265796918917600f, 0.994423919364875950f, + -0.105456477254830710f, + 0.994403680057679100f, -0.105647153713410620f, 0.994383404189101430f, + -0.105837826287646670f, + 0.994363091759888570f, -0.106028494970528410f, 0.994342742770787270f, + -0.106219159755045480f, + 0.994322357222545810f, -0.106409820634187680f, 0.994301935115913580f, + -0.106600477600944960f, + 0.994281476451641550f, -0.106791130648307390f, 0.994260981230481790f, + -0.106981779769265230f, + 0.994240449453187900f, -0.107172424956808840f, 0.994219881120514960f, + -0.107363066203928760f, + 0.994199276233218910f, -0.107553703503615620f, 0.994178634792057590f, + -0.107744336848860280f, + 0.994157956797789730f, -0.107934966232653650f, 0.994137242251175720f, + -0.108125591647986870f, + 0.994116491152977070f, -0.108316213087851170f, 0.994095703503956930f, + -0.108506830545237920f, + 0.994074879304879370f, -0.108697444013138720f, 0.994054018556510210f, + -0.108888053484545190f, + 0.994033121259616400f, -0.109078658952449240f, 0.994012187414966220f, + -0.109269260409842780f, + 0.993991217023329380f, -0.109459857849717980f, 0.993970210085476920f, + -0.109650451265067100f, + 0.993949166602181130f, -0.109841040648882600f, 0.993928086574215830f, + -0.110031625994157000f, + 0.993906970002356060f, -0.110222207293883060f, 0.993885816887378090f, + -0.110412784541053630f, + 0.993864627230059750f, -0.110603357728661730f, 0.993843401031180180f, + -0.110793926849700560f, + 0.993822138291519660f, -0.110984491897163390f, 0.993800839011860120f, + -0.111175052864043720f, + 0.993779503192984580f, -0.111365609743335160f, 0.993758130835677430f, + -0.111556162528031480f, + 0.993736721940724600f, -0.111746711211126590f, 0.993715276508913230f, + -0.111937255785614570f, + 0.993693794541031790f, -0.112127796244489640f, 0.993672276037870010f, + -0.112318332580746170f, + 0.993650721000219120f, -0.112508864787378690f, 0.993629129428871720f, + -0.112699392857381860f, + 0.993607501324621610f, -0.112889916783750520f, 0.993585836688263950f, + -0.113080436559479620f, + 0.993564135520595300f, -0.113270952177564350f, 0.993542397822413600f, + -0.113461463630999950f, + 0.993520623594518090f, -0.113651970912781870f, 0.993498812837709360f, + -0.113842474015905710f, + 0.993476965552789190f, -0.114032972933367200f, 0.993455081740560960f, + -0.114223467658162260f, + 0.993433161401829360f, -0.114413958183286920f, 0.993411204537400060f, + -0.114604444501737420f, + 0.993389211148080650f, -0.114794926606510080f, 0.993367181234679600f, + -0.114985404490601460f, + 0.993345114798006910f, -0.115175878147008190f, 0.993323011838873950f, + -0.115366347568727140f, + 0.993300872358093280f, -0.115556812748755260f, 0.993278696356479030f, + -0.115747273680089720f, + 0.993256483834846440f, -0.115937730355727780f, 0.993234234794012290f, + -0.116128182768666930f, + 0.993211949234794500f, -0.116318630911904750f, 0.993189627158012620f, + -0.116509074778439040f, + 0.993167268564487230f, -0.116699514361267690f, 0.993144873455040430f, + -0.116889949653388780f, + 0.993122441830495580f, -0.117080380647800590f, 0.993099973691677570f, + -0.117270807337501460f, + 0.993077469039412300f, -0.117461229715489990f, 0.993054927874527320f, + -0.117651647774764860f, + 0.993032350197851410f, -0.117842061508324980f, 0.993009736010214580f, + -0.118032470909169340f, + 0.992987085312448390f, -0.118222875970297170f, 0.992964398105385610f, + -0.118413276684707790f, + 0.992941674389860470f, -0.118603673045400720f, 0.992918914166708300f, + -0.118794065045375640f, + 0.992896117436765980f, -0.118984452677632340f, 0.992873284200871730f, + -0.119174835935170880f, + 0.992850414459865100f, -0.119365214810991350f, 0.992827508214586760f, + -0.119555589298094110f, + 0.992804565465879140f, -0.119745959389479600f, 0.992781586214585570f, + -0.119936325078148470f, + 0.992758570461551140f, -0.120126686357101500f, 0.992735518207621850f, + -0.120317043219339680f, + 0.992712429453645460f, -0.120507395657864130f, 0.992689304200470750f, + -0.120697743665676110f, + 0.992666142448948020f, -0.120888087235777080f, 0.992642944199928820f, + -0.121078426361168640f, + 0.992619709454266140f, -0.121268761034852600f, 0.992596438212814290f, + -0.121459091249830840f, + 0.992573130476428810f, -0.121649416999105530f, 0.992549786245966680f, + -0.121839738275678890f, + 0.992526405522286100f, -0.122030055072553360f, 0.992502988306246950f, + -0.122220367382731540f, + 0.992479534598709970f, -0.122410675199216200f, 0.992456044400537700f, + -0.122600978515010240f, + 0.992432517712593660f, -0.122791277323116770f, 0.992408954535742850f, + -0.122981571616539050f, + 0.992385354870851670f, -0.123171861388280480f, 0.992361718718787870f, + -0.123362146631344680f, + 0.992338046080420420f, -0.123552427338735370f, 0.992314336956619640f, + -0.123742703503456510f, + 0.992290591348257370f, -0.123932975118512160f, 0.992266809256206580f, + -0.124123242176906600f, + 0.992242990681341700f, -0.124313504671644230f, 0.992219135624538450f, + -0.124503762595729660f, + 0.992195244086673920f, -0.124694015942167640f, 0.992171316068626520f, + -0.124884264703963130f, + 0.992147351571276090f, -0.125074508874121170f, 0.992123350595503720f, + -0.125264748445647060f, + 0.992099313142191800f, -0.125454983411546230f, 0.992075239212224070f, + -0.125645213764824290f, + 0.992051128806485720f, -0.125835439498487000f, 0.992026981925863360f, + -0.126025660605540320f, + 0.992002798571244520f, -0.126215877078990350f, 0.991978578743518580f, + -0.126406088911843380f, + 0.991954322443575950f, -0.126596296097105850f, 0.991930029672308480f, + -0.126786498627784410f, + 0.991905700430609330f, -0.126976696496885870f, 0.991881334719373010f, + -0.127166889697417160f, + 0.991856932539495470f, -0.127357078222385400f, 0.991832493891873780f, + -0.127547262064797970f, + 0.991808018777406430f, -0.127737441217662310f, 0.991783507196993490f, + -0.127927615673986080f, + 0.991758959151536110f, -0.128117785426777130f, 0.991734374641936810f, + -0.128307950469043420f, + 0.991709753669099530f, -0.128498110793793170f, 0.991685096233929420f, + -0.128688266394034690f, + 0.991660402337333210f, -0.128878417262776550f, 0.991635671980218740f, + -0.129068563393027410f, + 0.991610905163495370f, -0.129258704777796140f, 0.991586101888073500f, + -0.129448841410091780f, + 0.991561262154865290f, -0.129638973282923560f, 0.991536385964783880f, + -0.129829100389300930f, + 0.991511473318743900f, -0.130019222722233350f, 0.991486524217661480f, + -0.130209340274730630f, + 0.991461538662453790f, -0.130399453039802690f, 0.991436516654039420f, + -0.130589561010459650f, + 0.991411458193338540f, -0.130779664179711710f, 0.991386363281272280f, + -0.130969762540569380f, + 0.991361231918763460f, -0.131159856086043270f, 0.991336064106736140f, + -0.131349944809144190f, + 0.991310859846115440f, -0.131540028702883120f, 0.991285619137828200f, + -0.131730107760271160f, + 0.991260341982802440f, -0.131920181974319790f, 0.991235028381967420f, + -0.132110251338040360f, + 0.991209678336254060f, -0.132300315844444650f, 0.991184291846594180f, + -0.132490375486544550f, + 0.991158868913921350f, -0.132680430257352070f, 0.991133409539170170f, + -0.132870480149879430f, + 0.991107913723276890f, -0.133060525157139060f, 0.991082381467178640f, + -0.133250565272143570f, + 0.991056812771814340f, -0.133440600487905680f, 0.991031207638124130f, + -0.133630630797438340f, + 0.991005566067049370f, -0.133820656193754720f, 0.990979888059532740f, + -0.134010676669868130f, + 0.990954173616518500f, -0.134200692218792020f, 0.990928422738951990f, + -0.134390702833540070f, + 0.990902635427780010f, -0.134580708507126170f, 0.990876811683950700f, + -0.134770709232564350f, + 0.990850951508413620f, -0.134960705002868750f, 0.990825054902119470f, + -0.135150695811053850f, + 0.990799121866020370f, -0.135340681650134210f, 0.990773152401069780f, + -0.135530662513124590f, + 0.990747146508222710f, -0.135720638393039910f, 0.990721104188435180f, + -0.135910609282895330f, + 0.990695025442664630f, -0.136100575175706200f, 0.990668910271870100f, + -0.136290536064487960f, + 0.990642758677011570f, -0.136480491942256280f, 0.990616570659050620f, + -0.136670442802027090f, + 0.990590346218950150f, -0.136860388636816380f, 0.990564085357674370f, + -0.137050329439640410f, + 0.990537788076188750f, -0.137240265203515590f, 0.990511454375460290f, + -0.137430195921458550f, + 0.990485084256457090f, -0.137620121586486040f, 0.990458677720148620f, + -0.137810042191615080f, + 0.990432234767505970f, -0.137999957729862790f, 0.990405755399501260f, + -0.138189868194246560f, + 0.990379239617108160f, -0.138379773577783890f, 0.990352687421301450f, + -0.138569673873492500f, + 0.990326098813057330f, -0.138759569074390350f, 0.990299473793353590f, + -0.138949459173495490f, + 0.990272812363169110f, -0.139139344163826200f, 0.990246114523483990f, + -0.139329224038400980f, + 0.990219380275280000f, -0.139519098790238490f, 0.990192609619540030f, + -0.139708968412357550f, + 0.990165802557248400f, -0.139898832897777210f, 0.990138959089390650f, + -0.140088692239516670f, + 0.990112079216953770f, -0.140278546430595420f, 0.990085162940925970f, + -0.140468395464033000f, + 0.990058210262297120f, -0.140658239332849210f, 0.990031221182058000f, + -0.140848078030064080f, + 0.990004195701200910f, -0.141037911548697710f, 0.989977133820719610f, + -0.141227739881770510f, + 0.989950035541608990f, -0.141417563022303020f, 0.989922900864865450f, + -0.141607380963316020f, + 0.989895729791486660f, -0.141797193697830390f, 0.989868522322471580f, + -0.141987001218867290f, + 0.989841278458820530f, -0.142176803519448030f, 0.989813998201535260f, + -0.142366600592594180f, + 0.989786681551618640f, -0.142556392431327340f, 0.989759328510075200f, + -0.142746179028669460f, + 0.989731939077910570f, -0.142935960377642670f, 0.989704513256131850f, + -0.143125736471269190f, + 0.989677051045747210f, -0.143315507302571500f, 0.989649552447766530f, + -0.143505272864572290f, + 0.989622017463200890f, -0.143695033150294470f, 0.989594446093062460f, + -0.143884788152760980f, + 0.989566838338365120f, -0.144074537864995160f, 0.989539194200123930f, + -0.144264282280020440f, + 0.989511513679355190f, -0.144454021390860470f, 0.989483796777076760f, + -0.144643755190539040f, + 0.989456043494307710f, -0.144833483672080210f, 0.989428253832068230f, + -0.145023206828508220f, + 0.989400427791380380f, -0.145212924652847460f, 0.989372565373267010f, + -0.145402637138122570f, + 0.989344666578752640f, -0.145592344277358340f, 0.989316731408863000f, + -0.145782046063579860f, + 0.989288759864625170f, -0.145971742489812210f, 0.989260751947067640f, + -0.146161433549080900f, + 0.989232707657220050f, -0.146351119234411460f, 0.989204626996113780f, + -0.146540799538829760f, + 0.989176509964781010f, -0.146730474455361750f, 0.989148356564255590f, + -0.146920143977033620f, + 0.989120166795572690f, -0.147109808096871820f, 0.989091940659768800f, + -0.147299466807902850f, + 0.989063678157881540f, -0.147489120103153570f, 0.989035379290950310f, + -0.147678767975650970f, + 0.989007044060015270f, -0.147868410418422220f, 0.988978672466118480f, + -0.148058047424494720f, + 0.988950264510302990f, -0.148247678986896030f, 0.988921820193613190f, + -0.148437305098653970f, + 0.988893339517095130f, -0.148626925752796540f, 0.988864822481795640f, + -0.148816540942351920f, + 0.988836269088763540f, -0.149006150660348450f, 0.988807679339048450f, + -0.149195754899814820f, + 0.988779053233701520f, -0.149385353653779720f, 0.988750390773775360f, + -0.149574946915272230f, + 0.988721691960323780f, -0.149764534677321510f, 0.988692956794401940f, + -0.149954116932956960f, + 0.988664185277066230f, -0.150143693675208190f, 0.988635377409374790f, + -0.150333264897105000f, + 0.988606533192386450f, -0.150522830591677400f, 0.988577652627162020f, + -0.150712390751955610f, + 0.988548735714763200f, -0.150901945370970040f, 0.988519782456253270f, + -0.151091494441751300f, + 0.988490792852696590f, -0.151281037957330220f, 0.988461766905159300f, + -0.151470575910737810f, + 0.988432704614708340f, -0.151660108295005310f, 0.988403605982412390f, + -0.151849635103164180f, + 0.988374471009341280f, -0.152039156328246050f, 0.988345299696566150f, + -0.152228671963282740f, + 0.988316092045159690f, -0.152418182001306330f, 0.988286848056195820f, + -0.152607686435349050f, + 0.988257567730749460f, -0.152797185258443440f, 0.988228251069897420f, + -0.152986678463622040f, + 0.988198898074717610f, -0.153176166043917840f, 0.988169508746289060f, + -0.153365647992363880f, + 0.988140083085692570f, -0.153555124301993450f, 0.988110621094009820f, + -0.153744594965840030f, + 0.988081122772324070f, -0.153934059976937350f, 0.988051588121720110f, + -0.154123519328319360f, + 0.988022017143283530f, -0.154312973013020100f, 0.987992409838101880f, + -0.154502421024073940f, + 0.987962766207263420f, -0.154691863354515430f, 0.987933086251858380f, + -0.154881299997379320f, + 0.987903369972977790f, -0.155070730945700510f, 0.987873617371714200f, + -0.155260156192514240f, + 0.987843828449161740f, -0.155449575730855850f, 0.987814003206415550f, + -0.155638989553760900f, + 0.987784141644572180f, -0.155828397654265230f, 0.987754243764729530f, + -0.156017800025404800f, + 0.987724309567986960f, -0.156207196660215900f, 0.987694339055445130f, + -0.156396587551734880f, + 0.987664332228205710f, -0.156585972692998430f, 0.987634289087372160f, + -0.156775352077043350f, + 0.987604209634049160f, -0.156964725696906780f, 0.987574093869342360f, + -0.157154093545625900f, + 0.987543941794359230f, -0.157343455616238250f, 0.987513753410208420f, + -0.157532811901781530f, + 0.987483528717999710f, -0.157722162395293630f, 0.987453267718844560f, + -0.157911507089812660f, + 0.987422970413855410f, -0.158100845978376980f, 0.987392636804146240f, + -0.158290179054025180f, + 0.987362266890832400f, -0.158479506309795960f, 0.987331860675030430f, + -0.158668827738728310f, + 0.987301418157858430f, -0.158858143333861450f, 0.987270939340435420f, + -0.159047453088234760f, + 0.987240424223882250f, -0.159236756994887850f, 0.987209872809320820f, + -0.159426055046860580f, + 0.987179285097874340f, -0.159615347237193060f, 0.987148661090667570f, + -0.159804633558925440f, + 0.987118000788826280f, -0.159993914005098270f, 0.987087304193477900f, + -0.160183188568752220f, + 0.987056571305750970f, -0.160372457242928280f, 0.987025802126775600f, + -0.160561720020667490f, + 0.986994996657682980f, -0.160750976895011220f, 0.986964154899605650f, + -0.160940227859001080f, + 0.986933276853677710f, -0.161129472905678810f, 0.986902362521034470f, + -0.161318712028086400f, + 0.986871411902812470f, -0.161507945219266120f, 0.986840425000149680f, + -0.161697172472260400f, + 0.986809401814185530f, -0.161886393780111830f, 0.986778342346060430f, + -0.162075609135863330f, + 0.986747246596916590f, -0.162264818532558000f, 0.986716114567897100f, + -0.162454021963239190f, + 0.986684946260146690f, -0.162643219420950310f, 0.986653741674811350f, + -0.162832410898735210f, + 0.986622500813038480f, -0.163021596389637840f, 0.986591223675976400f, + -0.163210775886702380f, + 0.986559910264775410f, -0.163399949382973230f, 0.986528560580586690f, + -0.163589116871495020f, + 0.986497174624562880f, -0.163778278345312670f, 0.986465752397857940f, + -0.163967433797471170f, + 0.986434293901627180f, -0.164156583221015810f, 0.986402799137027220f, + -0.164345726608992190f, + 0.986371268105216030f, -0.164534863954446000f, 0.986339700807353000f, + -0.164723995250423170f, + 0.986308097244598670f, -0.164913120489969890f, 0.986276457418115090f, + -0.165102239666132660f, + 0.986244781329065460f, -0.165291352771958000f, 0.986213068978614490f, + -0.165480459800492780f, + 0.986181320367928270f, -0.165669560744784120f, 0.986149535498173860f, + -0.165858655597879300f, + 0.986117714370520090f, -0.166047744352825790f, 0.986085856986136820f, + -0.166236827002671420f, + 0.986053963346195440f, -0.166425903540464100f, 0.986022033451868560f, + -0.166614973959252090f, + 0.985990067304330140f, -0.166804038252083730f, 0.985958064904755460f, + -0.166993096412007710f, + 0.985926026254321130f, -0.167182148432072940f, 0.985893951354205210f, + -0.167371194305328430f, + 0.985861840205586980f, -0.167560234024823560f, 0.985829692809647050f, + -0.167749267583607890f, + 0.985797509167567480f, -0.167938294974731170f, 0.985765289280531310f, + -0.168127316191243410f, + 0.985733033149723490f, -0.168316331226194830f, 0.985700740776329850f, + -0.168505340072635900f, + 0.985668412161537550f, -0.168694342723617330f, 0.985636047306535420f, + -0.168883339172189980f, + 0.985603646212513400f, -0.169072329411405010f, 0.985571208880662740f, + -0.169261313434313830f, + 0.985538735312176060f, -0.169450291233967960f, 0.985506225508247290f, + -0.169639262803419290f, + 0.985473679470071810f, -0.169828228135719850f, 0.985441097198846210f, + -0.170017187223921950f, + 0.985408478695768420f, -0.170206140061078070f, 0.985375823962037710f, + -0.170395086640240940f, + 0.985343132998854790f, -0.170584026954463590f, 0.985310405807421570f, + -0.170772960996799230f, + 0.985277642388941220f, -0.170961888760301220f, 0.985244842744618540f, + -0.171150810238023280f, + 0.985212006875659350f, -0.171339725423019310f, 0.985179134783271130f, + -0.171528634308343420f, + 0.985146226468662230f, -0.171717536887049970f, 0.985113281933042710f, + -0.171906433152193530f, + 0.985080301177623800f, -0.172095323096829010f, 0.985047284203618200f, + -0.172284206714011370f, + 0.985014231012239840f, -0.172473083996795950f, 0.984981141604703960f, + -0.172661954938238270f, + 0.984948015982227030f, -0.172850819531394080f, 0.984914854146027200f, + -0.173039677769319360f, + 0.984881656097323700f, -0.173228529645070320f, 0.984848421837337010f, + -0.173417375151703470f, + 0.984815151367289140f, -0.173606214282275410f, 0.984781844688403350f, + -0.173795047029843160f, + 0.984748501801904210f, -0.173983873387463820f, 0.984715122709017620f, + -0.174172693348194820f, + 0.984681707410970940f, -0.174361506905093750f, 0.984648255908992630f, + -0.174550314051218510f, + 0.984614768204312600f, -0.174739114779627200f, 0.984581244298162180f, + -0.174927909083378160f, + 0.984547684191773960f, -0.175116696955529920f, 0.984514087886381840f, + -0.175305478389141320f, + 0.984480455383220930f, -0.175494253377271430f, 0.984446786683527920f, + -0.175683021912979490f, + 0.984413081788540700f, -0.175871783989325040f, 0.984379340699498510f, + -0.176060539599367820f, + 0.984345563417641900f, -0.176249288736167880f, 0.984311749944212780f, + -0.176438031392785410f, + 0.984277900280454370f, -0.176626767562280880f, 0.984244014427611110f, + -0.176815497237715000f, + 0.984210092386929030f, -0.177004220412148750f, 0.984176134159655320f, + -0.177192937078643280f, + 0.984142139747038570f, -0.177381647230260040f, 0.984108109150328540f, + -0.177570350860060710f, + 0.984074042370776450f, -0.177759047961107170f, 0.984039939409634970f, + -0.177947738526461560f, + 0.984005800268157870f, -0.178136422549186300f, 0.983971624947600270f, + -0.178325100022344000f, + 0.983937413449218920f, -0.178513770938997510f, 0.983903165774271500f, + -0.178702435292209970f, + 0.983868881924017220f, -0.178891093075044720f, 0.983834561899716630f, + -0.179079744280565390f, + 0.983800205702631600f, -0.179268388901835750f, 0.983765813334025240f, + -0.179457026931919890f, + 0.983731384795162090f, -0.179645658363882160f, 0.983696920087308140f, + -0.179834283190787090f, + 0.983662419211730250f, -0.180022901405699510f, 0.983627882169697210f, + -0.180211513001684450f, + 0.983593308962478650f, -0.180400117971807240f, 0.983558699591345900f, + -0.180588716309133340f, + 0.983524054057571260f, -0.180777308006728590f, 0.983489372362428730f, + -0.180965893057658980f, + 0.983454654507193270f, -0.181154471454990810f, 0.983419900493141540f, + -0.181343043191790540f, + 0.983385110321551180f, -0.181531608261124970f, 0.983350283993701500f, + -0.181720166656061110f, + 0.983315421510872810f, -0.181908718369666160f, 0.983280522874346970f, + -0.182097263395007650f, + 0.983245588085407070f, -0.182285801725153300f, 0.983210617145337640f, + -0.182474333353171120f, + 0.983175610055424420f, -0.182662858272129270f, 0.983140566816954500f, + -0.182851376475096330f, + 0.983105487431216290f, -0.183039887955140950f, 0.983070371899499640f, + -0.183228392705332140f, + 0.983035220223095640f, -0.183416890718739100f, 0.983000032403296590f, + -0.183605381988431270f, + 0.982964808441396440f, -0.183793866507478450f, 0.982929548338690170f, + -0.183982344268950520f, + 0.982894252096474070f, -0.184170815265917720f, 0.982858919716046110f, + -0.184359279491450510f, + 0.982823551198705240f, -0.184547736938619620f, 0.982788146545751970f, + -0.184736187600495950f, + 0.982752705758487830f, -0.184924631470150790f, 0.982717228838215990f, + -0.185113068540655540f, + 0.982681715786240860f, -0.185301498805081900f, 0.982646166603868050f, + -0.185489922256501880f, + 0.982610581292404750f, -0.185678338887987630f, 0.982574959853159240f, + -0.185866748692611660f, + 0.982539302287441240f, -0.186055151663446630f, 0.982503608596561830f, + -0.186243547793565560f, + 0.982467878781833170f, -0.186431937076041610f, 0.982432112844569110f, + -0.186620319503948280f, + 0.982396310786084690f, -0.186808695070359270f, 0.982360472607696210f, + -0.186997063768348540f, + 0.982324598310721280f, -0.187185425590990330f, 0.982288687896478830f, + -0.187373780531359110f, + 0.982252741366289370f, -0.187562128582529600f, 0.982216758721474510f, + -0.187750469737576780f, + 0.982180739963357090f, -0.187938803989575910f, 0.982144685093261580f, + -0.188127131331602420f, + 0.982108594112513610f, -0.188315451756732120f, 0.982072467022440000f, + -0.188503765258040940f, + 0.982036303824369020f, -0.188692071828605230f, 0.982000104519630490f, + -0.188880371461501380f, + 0.981963869109555240f, -0.189068664149806190f, 0.981927597595475540f, + -0.189256949886596750f, + 0.981891289978725100f, -0.189445228664950230f, 0.981854946260638630f, + -0.189633500477944190f, + 0.981818566442552500f, -0.189821765318656410f, 0.981782150525804310f, + -0.190010023180164990f, + 0.981745698511732990f, -0.190198274055548150f, 0.981709210401678800f, + -0.190386517937884470f, + 0.981672686196983110f, -0.190574754820252740f, 0.981636125898989080f, + -0.190762984695732110f, + 0.981599529509040720f, -0.190951207557401800f, 0.981562897028483650f, + -0.191139423398341450f, + 0.981526228458664770f, -0.191327632211630900f, 0.981489523800932130f, + -0.191515833990350210f, + 0.981452783056635520f, -0.191704028727579800f, 0.981416006227125550f, + -0.191892216416400220f, + 0.981379193313754560f, -0.192080397049892440f, 0.981342344317876040f, + -0.192268570621137500f, + 0.981305459240844670f, -0.192456737123216840f, 0.981268538084016710f, + -0.192644896549212100f, + 0.981231580848749730f, -0.192833048892205230f, 0.981194587536402320f, + -0.193021194145278380f, + 0.981157558148334830f, -0.193209332301513960f, 0.981120492685908730f, + -0.193397463353994740f, + 0.981083391150486710f, -0.193585587295803610f, 0.981046253543432780f, + -0.193773704120023820f, + 0.981009079866112630f, -0.193961813819738840f, 0.980971870119892840f, + -0.194149916388032450f, + 0.980934624306141640f, -0.194338011817988600f, 0.980897342426228390f, + -0.194526100102691610f, + 0.980860024481523870f, -0.194714181235225960f, 0.980822670473400100f, + -0.194902255208676520f, + 0.980785280403230430f, -0.195090322016128250f, 0.980747854272389750f, + -0.195278381650666550f, + 0.980710392082253970f, -0.195466434105376980f, 0.980672893834200530f, + -0.195654479373345370f, + 0.980635359529608120f, -0.195842517447657850f, 0.980597789169856850f, + -0.196030548321400790f, + 0.980560182756327840f, -0.196218571987660880f, 0.980522540290404090f, + -0.196406588439524970f, + 0.980484861773469380f, -0.196594597670080220f, 0.980447147206909060f, + -0.196782599672414100f, + 0.980409396592109910f, -0.196970594439614340f, 0.980371609930459800f, + -0.197158581964768880f, + 0.980333787223347960f, -0.197346562240965920f, 0.980295928472165290f, + -0.197534535261294030f, + 0.980258033678303550f, -0.197722501018841920f, 0.980220102843156080f, + -0.197910459506698670f, + 0.980182135968117430f, -0.198098410717953560f, 0.980144133054583590f, + -0.198286354645696220f, + 0.980106094103951770f, -0.198474291283016390f, 0.980068019117620650f, + -0.198662220623004200f, + 0.980029908096990090f, -0.198850142658750090f, 0.979991761043461200f, + -0.199038057383344680f, + 0.979953577958436740f, -0.199225964789878830f, 0.979915358843320480f, + -0.199413864871443770f, + 0.979877103699517640f, -0.199601757621130970f, 0.979838812528434740f, + -0.199789643032032090f, + 0.979800485331479790f, -0.199977521097239150f, 0.979762122110061750f, + -0.200165391809844440f, + 0.979723722865591170f, -0.200353255162940450f, 0.979685287599479930f, + -0.200541111149619980f, + 0.979646816313141210f, -0.200728959762976140f, 0.979608309007989450f, + -0.200916800996102230f, + 0.979569765685440520f, -0.201104634842091900f, 0.979531186346911500f, + -0.201292461294039020f, + 0.979492570993820810f, -0.201480280345037730f, 0.979453919627588210f, + -0.201668091988182530f, + 0.979415232249634780f, -0.201855896216568050f, 0.979376508861383170f, + -0.202043693023289260f, + 0.979337749464256780f, -0.202231482401441450f, 0.979298954059681040f, + -0.202419264344120160f, + 0.979260122649082020f, -0.202607038844421130f, 0.979221255233887700f, + -0.202794805895440440f, + 0.979182351815526930f, -0.202982565490274440f, 0.979143412395430230f, + -0.203170317622019790f, + 0.979104436975029250f, -0.203358062283773320f, 0.979065425555756930f, + -0.203545799468632190f, + 0.979026378139047580f, -0.203733529169693920f, 0.978987294726337050f, + -0.203921251380056120f, + 0.978948175319062200f, -0.204108966092816870f, 0.978909019918661310f, + -0.204296673301074370f, + 0.978869828526574120f, -0.204484372997927240f, 0.978830601144241470f, + -0.204672065176474210f, + 0.978791337773105670f, -0.204859749829814420f, 0.978752038414610340f, + -0.205047426951047250f, + 0.978712703070200420f, -0.205235096533272350f, 0.978673331741322210f, + -0.205422758569589610f, + 0.978633924429423210f, -0.205610413053099240f, 0.978594481135952270f, + -0.205798059976901790f, + 0.978555001862359550f, -0.205985699334097910f, 0.978515486610096910f, + -0.206173331117788710f, + 0.978475935380616830f, -0.206360955321075510f, 0.978436348175373730f, + -0.206548571937059890f, + 0.978396724995823090f, -0.206736180958843690f, 0.978357065843421640f, + -0.206923782379529100f, + 0.978317370719627650f, -0.207111376192218560f, 0.978277639625900530f, + -0.207298962390014750f, + 0.978237872563701090f, -0.207486540966020650f, 0.978198069534491400f, + -0.207674111913339570f, + 0.978158230539735050f, -0.207861675225075070f, 0.978118355580896660f, + -0.208049230894330940f, + 0.978078444659442380f, -0.208236778914211330f, 0.978038497776839600f, + -0.208424319277820600f, + 0.977998514934557140f, -0.208611851978263490f, 0.977958496134064830f, + -0.208799377008644900f, + 0.977918441376834370f, -0.208986894362070070f, 0.977878350664338150f, + -0.209174404031644580f, + 0.977838223998050430f, -0.209361906010474160f, 0.977798061379446360f, + -0.209549400291664940f, + 0.977757862810002760f, -0.209736886868323290f, 0.977717628291197460f, + -0.209924365733555880f, + 0.977677357824509930f, -0.210111836880469610f, 0.977637051411420770f, + -0.210299300302171730f, + 0.977596709053411890f, -0.210486755991769720f, 0.977556330751966460f, + -0.210674203942371440f, + 0.977515916508569280f, -0.210861644147084860f, 0.977475466324706170f, + -0.211049076599018390f, + 0.977434980201864260f, -0.211236501291280710f, 0.977394458141532250f, + -0.211423918216980670f, + 0.977353900145199960f, -0.211611327369227550f, 0.977313306214358750f, + -0.211798728741130840f, + 0.977272676350500860f, -0.211986122325800330f, 0.977232010555120320f, + -0.212173508116346080f, + 0.977191308829712280f, -0.212360886105878420f, 0.977150571175773200f, + -0.212548256287508060f, + 0.977109797594800880f, -0.212735618654345930f, 0.977068988088294450f, + -0.212922973199503180f, + 0.977028142657754390f, -0.213110319916091360f, 0.976987261304682390f, + -0.213297658797222320f, + 0.976946344030581670f, -0.213484989836008050f, 0.976905390836956490f, + -0.213672313025560970f, + 0.976864401725312640f, -0.213859628358993750f, 0.976823376697157240f, + -0.214046935829419360f, + 0.976782315753998650f, -0.214234235429950990f, 0.976741218897346550f, + -0.214421527153702160f, + 0.976700086128711840f, -0.214608810993786760f, 0.976658917449606980f, + -0.214796086943318860f, + 0.976617712861545640f, -0.214983354995412820f, 0.976576472366042610f, + -0.215170615143183390f, + 0.976535195964614470f, -0.215357867379745550f, 0.976493883658778650f, + -0.215545111698214500f, + 0.976452535450054060f, -0.215732348091705880f, 0.976411151339961040f, + -0.215919576553335490f, + 0.976369731330021140f, -0.216106797076219520f, 0.976328275421757260f, + -0.216294009653474340f, + 0.976286783616693630f, -0.216481214278216730f, 0.976245255916355800f, + -0.216668410943563730f, + 0.976203692322270560f, -0.216855599642632620f, 0.976162092835966110f, + -0.217042780368540990f, + 0.976120457458971910f, -0.217229953114406790f, 0.976078786192818850f, + -0.217417117873348190f, + 0.976037079039039020f, -0.217604274638483640f, 0.975995335999165990f, + -0.217791423402931950f, + 0.975953557074734300f, -0.217978564159812200f, 0.975911742267280170f, + -0.218165696902243800f, + 0.975869891578341030f, -0.218352821623346320f, 0.975828005009455660f, + -0.218539938316239770f, + 0.975786082562163930f, -0.218727046974044440f, 0.975744124238007270f, + -0.218914147589880840f, + 0.975702130038528570f, -0.219101240156869800f, 0.975660099965271590f, + -0.219288324668132470f, + 0.975618034019781750f, -0.219475401116790310f, 0.975575932203605720f, + -0.219662469495965050f, + 0.975533794518291360f, -0.219849529798778700f, 0.975491620965388110f, + -0.220036582018353580f, + 0.975449411546446380f, -0.220223626147812380f, 0.975407166263018270f, + -0.220410662180277940f, + 0.975364885116656980f, -0.220597690108873510f, 0.975322568108916930f, + -0.220784709926722610f, + 0.975280215241354220f, -0.220971721626949110f, 0.975237826515525820f, + -0.221158725202677010f, + 0.975195401932990370f, -0.221345720647030810f, 0.975152941495307620f, + -0.221532707953135230f, + 0.975110445204038890f, -0.221719687114115220f, 0.975067913060746470f, + -0.221906658123096100f, + 0.975025345066994120f, -0.222093620973203510f, 0.974982741224347140f, + -0.222280575657563370f, + 0.974940101534371830f, -0.222467522169301880f, 0.974897425998635820f, + -0.222654460501545500f, + 0.974854714618708430f, -0.222841390647421120f, 0.974811967396159830f, + -0.223028312600055820f, + 0.974769184332561770f, -0.223215226352576980f, 0.974726365429487320f, + -0.223402131898112370f, + 0.974683510688510670f, -0.223589029229789990f, 0.974640620111207560f, + -0.223775918340738150f, + 0.974597693699155050f, -0.223962799224085460f, 0.974554731453931230f, + -0.224149671872960870f, + 0.974511733377115720f, -0.224336536280493600f, 0.974468699470289580f, + -0.224523392439813170f, + 0.974425629735034990f, -0.224710240344049430f, 0.974382524172935470f, + -0.224897079986332490f, + 0.974339382785575860f, -0.225083911359792830f, 0.974296205574542440f, + -0.225270734457561160f, + 0.974252992541422500f, -0.225457549272768540f, 0.974209743687805220f, + -0.225644355798546330f, + 0.974166459015280320f, -0.225831154028026170f, 0.974123138525439640f, + -0.226017943954340020f, + 0.974079782219875680f, -0.226204725570620190f, 0.974036390100182610f, + -0.226391498869999240f, + 0.973992962167955830f, -0.226578263845610000f, 0.973949498424792170f, + -0.226765020490585690f, + 0.973905998872289570f, -0.226951768798059810f, 0.973862463512047300f, + -0.227138508761166170f, + 0.973818892345666100f, -0.227325240373038860f, 0.973775285374748110f, + -0.227511963626812280f, + 0.973731642600896400f, -0.227698678515621170f, 0.973687964025715670f, + -0.227885385032600530f, + 0.973644249650811980f, -0.228072083170885730f, 0.973600499477792370f, + -0.228258772923612380f, + 0.973556713508265560f, -0.228445454283916470f, 0.973512891743841370f, + -0.228632127244934230f, + 0.973469034186131070f, -0.228818791799802220f, 0.973425140836747030f, + -0.229005447941657340f, + 0.973381211697303290f, -0.229192095663636770f, 0.973337246769414910f, + -0.229378734958878010f, + 0.973293246054698250f, -0.229565365820518870f, 0.973249209554771230f, + -0.229751988241697490f, + 0.973205137271252800f, -0.229938602215552210f, 0.973161029205763530f, + -0.230125207735221850f, + 0.973116885359925130f, -0.230311804793845440f, 0.973072705735360530f, + -0.230498393384562350f, + 0.973028490333694210f, -0.230684973500512200f, 0.972984239156551740f, + -0.230871545134835020f, + 0.972939952205560180f, -0.231058108280671110f, 0.972895629482347760f, + -0.231244662931161050f, + 0.972851270988544180f, -0.231431209079445750f, 0.972806876725780370f, + -0.231617746718666470f, + 0.972762446695688570f, -0.231804275841964780f, 0.972717980899902250f, + -0.231990796442482440f, + 0.972673479340056430f, -0.232177308513361710f, 0.972628942017787270f, + -0.232363812047745030f, + 0.972584368934732210f, -0.232550307038775240f, 0.972539760092530180f, + -0.232736793479595390f, + 0.972495115492821190f, -0.232923271363348980f, 0.972450435137246830f, + -0.233109740683179690f, + 0.972405719027449770f, -0.233296201432231590f, 0.972360967165074140f, + -0.233482653603649090f, + 0.972316179551765300f, -0.233669097190576820f, 0.972271356189170040f, + -0.233855532186159840f, + 0.972226497078936270f, -0.234041958583543430f, 0.972181602222713440f, + -0.234228376375873210f, + 0.972136671622152230f, -0.234414785556295160f, 0.972091705278904430f, + -0.234601186117955550f, + 0.972046703194623500f, -0.234787578054000970f, 0.972001665370963890f, + -0.234973961357578250f, + 0.971956591809581720f, -0.235160336021834730f, 0.971911482512134000f, + -0.235346702039917840f, + 0.971866337480279400f, -0.235533059404975490f, 0.971821156715677700f, + -0.235719408110155820f, + 0.971775940219990140f, -0.235905748148607370f, 0.971730687994879160f, + -0.236092079513478910f, + 0.971685400042008540f, -0.236278402197919570f, 0.971640076363043390f, + -0.236464716195078780f, + 0.971594716959650160f, -0.236651021498106380f, 0.971549321833496630f, + -0.236837318100152380f, + 0.971503890986251780f, -0.237023605994367200f, 0.971458424419585960f, + -0.237209885173901600f, + 0.971412922135170940f, -0.237396155631906610f, 0.971367384134679490f, + -0.237582417361533570f, + 0.971321810419786160f, -0.237768670355934190f, 0.971276200992166490f, + -0.237954914608260540f, + 0.971230555853497380f, -0.238141150111664840f, 0.971184875005457030f, + -0.238327376859299810f, + 0.971139158449725090f, -0.238513594844318420f, 0.971093406187982460f, + -0.238699804059873980f, + 0.971047618221911100f, -0.238886004499120040f, 0.971001794553194690f, + -0.239072196155210610f, + 0.970955935183517970f, -0.239258379021299980f, 0.970910040114567050f, + -0.239444553090542630f, + 0.970864109348029470f, -0.239630718356093560f, 0.970818142885593870f, + -0.239816874811108000f, + 0.970772140728950350f, -0.240003022448741500f, 0.970726102879790110f, + -0.240189161262149900f, + 0.970680029339806130f, -0.240375291244489450f, 0.970633920110692160f, + -0.240561412388916650f, + 0.970587775194143630f, -0.240747524688588430f, 0.970541594591857070f, + -0.240933628136661910f, + 0.970495378305530560f, -0.241119722726294590f, 0.970449126336863090f, + -0.241305808450644370f, + 0.970402838687555500f, -0.241491885302869330f, 0.970356515359309450f, + -0.241677953276128010f, + 0.970310156353828110f, -0.241864012363579180f, 0.970263761672816140f, + -0.242050062558382070f, + 0.970217331317979160f, -0.242236103853696010f, 0.970170865291024480f, + -0.242422136242680890f, + 0.970124363593660280f, -0.242608159718496810f, 0.970077826227596420f, + -0.242794174274304220f, + 0.970031253194543970f, -0.242980179903263870f, 0.969984644496215240f, + -0.243166176598536900f, + 0.969938000134323960f, -0.243352164353284740f, 0.969891320110585100f, + -0.243538143160669130f, + 0.969844604426714830f, -0.243724113013852160f, 0.969797853084430890f, + -0.243910073905996260f, + 0.969751066085452140f, -0.244096025830264210f, 0.969704243431498860f, + -0.244281968779819030f, + 0.969657385124292450f, -0.244467902747824150f, 0.969610491165555870f, + -0.244653827727443320f, + 0.969563561557013180f, -0.244839743711840670f, 0.969516596300390000f, + -0.245025650694180470f, + 0.969469595397413060f, -0.245211548667627540f, 0.969422558849810320f, + -0.245397437625346960f, + 0.969375486659311280f, -0.245583317560504060f, 0.969328378827646660f, + -0.245769188466264580f, + 0.969281235356548530f, -0.245955050335794590f, 0.969234056247750050f, + -0.246140903162260530f, + 0.969186841502985950f, -0.246326746938829030f, 0.969139591123992280f, + -0.246512581658667210f, + 0.969092305112506210f, -0.246698407314942410f, 0.969044983470266240f, + -0.246884223900822430f, + 0.968997626199012420f, -0.247070031409475250f, 0.968950233300485800f, + -0.247255829834069300f, + 0.968902804776428870f, -0.247441619167773270f, 0.968855340628585580f, + -0.247627399403756280f, + 0.968807840858700970f, -0.247813170535187670f, 0.968760305468521430f, + -0.247998932555237110f, + 0.968712734459794780f, -0.248184685457074780f, 0.968665127834270060f, + -0.248370429233870980f, + 0.968617485593697540f, -0.248556163878796560f, 0.968569807739828930f, + -0.248741889385022480f, + 0.968522094274417380f, -0.248927605745720150f, 0.968474345199216820f, + -0.249113312954061360f, + 0.968426560515983190f, -0.249299011003218190f, 0.968378740226473300f, + -0.249484699886362960f, + 0.968330884332445190f, -0.249670379596668550f, 0.968282992835658660f, + -0.249856050127307990f, + 0.968235065737874320f, -0.250041711471454650f, 0.968187103040854420f, + -0.250227363622282370f, + 0.968139104746362440f, -0.250413006572965220f, 0.968091070856162970f, + -0.250598640316677670f, + 0.968043001372022260f, -0.250784264846594500f, 0.967994896295707670f, + -0.250969880155890720f, + 0.967946755628987800f, -0.251155486237741920f, 0.967898579373632660f, + -0.251341083085323880f, + 0.967850367531413620f, -0.251526670691812610f, 0.967802120104103270f, + -0.251712249050384700f, + 0.967753837093475510f, -0.251897818154216970f, 0.967705518501305480f, + -0.252083377996486450f, + 0.967657164329369880f, -0.252268928570370810f, 0.967608774579446500f, + -0.252454469869047740f, + 0.967560349253314360f, -0.252640001885695520f, 0.967511888352754150f, + -0.252825524613492610f, + 0.967463391879547550f, -0.253011038045617860f, 0.967414859835477480f, + -0.253196542175250560f, + 0.967366292222328510f, -0.253382036995570160f, 0.967317689041886310f, + -0.253567522499756560f, + 0.967269050295937790f, -0.253752998680989990f, 0.967220375986271420f, + -0.253938465532451090f, + 0.967171666114676640f, -0.254123923047320620f, 0.967122920682944360f, + -0.254309371218780000f, + 0.967074139692867040f, -0.254494810040010730f, 0.967025323146238010f, + -0.254680239504194830f, + 0.966976471044852070f, -0.254865659604514570f, 0.966927583390505660f, + -0.255051070334152470f, + 0.966878660184995910f, -0.255236471686291710f, 0.966829701430121810f, + -0.255421863654115460f, + 0.966780707127683270f, -0.255607246230807380f, 0.966731677279481840f, + -0.255792619409551610f, + 0.966682611887320080f, -0.255977983183532430f, 0.966633510953002100f, + -0.256163337545934460f, + 0.966584374478333120f, -0.256348682489942910f, 0.966535202465119700f, + -0.256534018008743040f, + 0.966485994915169840f, -0.256719344095520660f, 0.966436751830292650f, + -0.256904660743461910f, + 0.966387473212298900f, -0.257089967945753120f, 0.966338159063000130f, + -0.257275265695581120f, + 0.966288809384209690f, -0.257460553986133100f, 0.966239424177741890f, + -0.257645832810596390f, + 0.966190003445412500f, -0.257831102162158990f, 0.966140547189038750f, + -0.258016362034009020f, + 0.966091055410438830f, -0.258201612419334870f, 0.966041528111432400f, + -0.258386853311325600f, + 0.965991965293840570f, -0.258572084703170340f, 0.965942366959485540f, + -0.258757306588058680f, + 0.965892733110190860f, -0.258942518959180520f, 0.965843063747781510f, + -0.259127721809726150f, + 0.965793358874083680f, -0.259312915132886230f, 0.965743618490924830f, + -0.259498098921851660f, + 0.965693842600133690f, -0.259683273169813770f, 0.965644031203540590f, + -0.259868437869964270f, + 0.965594184302976830f, -0.260053593015495190f, 0.965544301900275180f, + -0.260238738599598840f, + 0.965494383997269500f, -0.260423874615468010f, 0.965444430595795430f, + -0.260609001056295750f, + 0.965394441697689400f, -0.260794117915275510f, 0.965344417304789370f, + -0.260979225185601070f, + 0.965294357418934660f, -0.261164322860466480f, 0.965244262041965780f, + -0.261349410933066350f, + 0.965194131175724720f, -0.261534489396595520f, 0.965143964822054450f, + -0.261719558244249030f, + 0.965093762982799590f, -0.261904617469222610f, 0.965043525659805890f, + -0.262089667064712040f, + 0.964993252854920320f, -0.262274707023913590f, 0.964942944569991410f, + -0.262459737340023980f, + 0.964892600806868890f, -0.262644758006240040f, 0.964842221567403620f, + -0.262829769015759160f, + 0.964791806853447900f, -0.263014770361779000f, 0.964741356666855340f, + -0.263199762037497560f, + 0.964690871009481030f, -0.263384744036113280f, 0.964640349883180930f, + -0.263569716350824880f, + 0.964589793289812760f, -0.263754678974831350f, 0.964539201231235150f, + -0.263939631901332350f, + 0.964488573709308410f, -0.264124575123527550f, 0.964437910725893910f, + -0.264309508634617110f, + 0.964387212282854290f, -0.264494432427801630f, 0.964336478382053720f, + -0.264679346496281890f, + 0.964285709025357480f, -0.264864250833259260f, 0.964234904214632200f, + -0.265049145431935250f, + 0.964184063951745830f, -0.265234030285511790f, 0.964133188238567640f, + -0.265418905387191260f, + 0.964082277076968140f, -0.265603770730176330f, 0.964031330468819280f, + -0.265788626307669920f, + 0.963980348415994110f, -0.265973472112875590f, 0.963929330920367140f, + -0.266158308138996990f, + 0.963878277983814200f, -0.266343134379238180f, 0.963827189608212340f, + -0.266527950826803690f, + 0.963776065795439840f, -0.266712757474898370f, 0.963724906547376530f, + -0.266897554316727350f, + 0.963673711865903230f, -0.267082341345496300f, 0.963622481752902220f, + -0.267267118554410930f, + 0.963571216210257320f, -0.267451885936677620f, 0.963519915239853140f, + -0.267636643485503090f, + 0.963468578843575950f, -0.267821391194094150f, 0.963417207023313350f, + -0.268006129055658290f, + 0.963365799780954050f, -0.268190857063403180f, 0.963314357118388200f, + -0.268375575210536900f, + 0.963262879037507070f, -0.268560283490267890f, 0.963211365540203480f, + -0.268744981895804980f, + 0.963159816628371360f, -0.268929670420357260f, 0.963108232303906190f, + -0.269114349057134380f, + 0.963056612568704340f, -0.269299017799346120f, 0.963004957424663850f, + -0.269483676640202840f, + 0.962953266873683880f, -0.269668325572915090f, 0.962901540917665000f, + -0.269852964590693860f, + 0.962849779558509030f, -0.270037593686750570f, 0.962797982798119010f, + -0.270222212854296870f, + 0.962746150638399410f, -0.270406822086544820f, 0.962694283081255930f, + -0.270591421376706940f, + 0.962642380128595710f, -0.270776010717996010f, 0.962590441782326890f, + -0.270960590103625170f, + 0.962538468044359160f, -0.271145159526808010f, 0.962486458916603450f, + -0.271329718980758420f, + 0.962434414400972100f, -0.271514268458690700f, 0.962382334499378380f, + -0.271698807953819510f, + 0.962330219213737400f, -0.271883337459359720f, 0.962278068545965090f, + -0.272067856968526920f, + 0.962225882497979020f, -0.272252366474536710f, 0.962173661071697880f, + -0.272436865970605240f, + 0.962121404269041580f, -0.272621355449948980f, 0.962069112091931580f, + -0.272805834905784810f, + 0.962016784542290560f, -0.272990304331329920f, 0.961964421622042320f, + -0.273174763719801930f, + 0.961912023333112210f, -0.273359213064418680f, 0.961859589677426570f, + -0.273543652358398730f, + 0.961807120656913540f, -0.273728081594960540f, 0.961754616273502010f, + -0.273912500767323260f, + 0.961702076529122540f, -0.274096909868706380f, 0.961649501425706820f, + -0.274281308892329660f, + 0.961596890965187860f, -0.274465697831413220f, 0.961544245149499990f, + -0.274650076679177680f, + 0.961491563980579000f, -0.274834445428843940f, 0.961438847460361680f, + -0.275018804073633220f, + 0.961386095590786250f, -0.275203152606767310f, 0.961333308373792270f, + -0.275387491021468140f, + 0.961280485811320640f, -0.275571819310958140f, 0.961227627905313460f, + -0.275756137468460120f, + 0.961174734657714080f, -0.275940445487197150f, 0.961121806070467380f, + -0.276124743360392830f, + 0.961068842145519350f, -0.276309031081271080f, 0.961015842884817230f, + -0.276493308643055990f, + 0.960962808290309780f, -0.276677576038972420f, 0.960909738363946770f, + -0.276861833262245280f, + 0.960856633107679660f, -0.277046080306099900f, 0.960803492523460760f, + -0.277230317163762170f, + 0.960750316613243950f, -0.277414543828458090f, 0.960697105378984450f, + -0.277598760293414290f, + 0.960643858822638590f, -0.277782966551857690f, 0.960590576946164120f, + -0.277967162597015370f, + 0.960537259751520050f, -0.278151348422115090f, 0.960483907240666790f, + -0.278335524020384920f, + 0.960430519415565790f, -0.278519689385053060f, 0.960377096278180130f, + -0.278703844509348490f, + 0.960323637830473920f, -0.278887989386500280f, 0.960270144074412800f, + -0.279072124009737800f, + 0.960216615011963430f, -0.279256248372291180f, 0.960163050645094000f, + -0.279440362467390510f, + 0.960109450975773940f, -0.279624466288266590f, 0.960055816005973890f, + -0.279808559828150390f, + 0.960002145737665960f, -0.279992643080273220f, 0.959948440172823210f, + -0.280176716037866980f, + 0.959894699313420530f, -0.280360778694163810f, 0.959840923161433770f, + -0.280544831042396250f, + 0.959787111718839900f, -0.280728873075797190f, 0.959733264987617680f, + -0.280912904787600000f, + 0.959679382969746750f, -0.281096926171038260f, 0.959625465667208190f, + -0.281280937219346110f, + 0.959571513081984520f, -0.281464937925757940f, 0.959517525216059260f, + -0.281648928283508630f, + 0.959463502071417510f, -0.281832908285833350f, 0.959409443650045550f, + -0.282016877925967640f, + 0.959355349953930790f, -0.282200837197147560f, 0.959301220985062210f, + -0.282384786092609360f, + 0.959247056745430090f, -0.282568724605589740f, 0.959192857237025740f, + -0.282752652729325930f, + 0.959138622461841890f, -0.282936570457055390f, 0.959084352421872730f, + -0.283120477782015820f, + 0.959030047119113660f, -0.283304374697445740f, 0.958975706555561080f, + -0.283488261196583550f, + 0.958921330733213170f, -0.283672137272668430f, 0.958866919654069010f, + -0.283856002918939750f, + 0.958812473320129310f, -0.284039858128637190f, 0.958757991733395710f, + -0.284223702895001040f, + 0.958703474895871600f, -0.284407537211271880f, 0.958648922809561150f, + -0.284591361070690440f, + 0.958594335476470220f, -0.284775174466498300f, 0.958539712898605730f, + -0.284958977391937040f, + 0.958485055077976100f, -0.285142769840248670f, 0.958430362016590930f, + -0.285326551804675870f, + 0.958375633716461170f, -0.285510323278461260f, 0.958320870179598880f, + -0.285694084254848320f, + 0.958266071408017670f, -0.285877834727080620f, 0.958211237403732260f, + -0.286061574688402040f, + 0.958156368168758820f, -0.286245304132057120f, 0.958101463705114730f, + -0.286429023051290700f, + 0.958046524014818600f, -0.286612731439347790f, 0.957991549099890370f, + -0.286796429289474080f, + 0.957936538962351420f, -0.286980116594915570f, 0.957881493604224370f, + -0.287163793348918390f, + 0.957826413027532910f, -0.287347459544729510f, 0.957771297234302320f, + -0.287531115175595930f, + 0.957716146226558870f, -0.287714760234765170f, 0.957660960006330610f, + -0.287898394715485170f, + 0.957605738575646350f, -0.288082018611004130f, 0.957550481936536470f, + -0.288265631914570770f, + 0.957495190091032570f, -0.288449234619434220f, 0.957439863041167680f, + -0.288632826718843830f, + 0.957384500788975860f, -0.288816408206049480f, 0.957329103336492790f, + -0.288999979074301420f, + 0.957273670685755200f, -0.289183539316850200f, 0.957218202838801210f, + -0.289367088926947010f, + 0.957162699797670210f, -0.289550627897843030f, 0.957107161564402790f, + -0.289734156222790250f, + 0.957051588141040970f, -0.289917673895040750f, 0.956995979529628230f, + -0.290101180907847090f, + 0.956940335732208820f, -0.290284677254462330f, 0.956884656750828900f, + -0.290468162928139820f, + 0.956828942587535370f, -0.290651637922133220f, 0.956773193244376930f, + -0.290835102229696830f, + 0.956717408723403050f, -0.291018555844085090f, 0.956661589026665090f, + -0.291201998758552900f, + 0.956605734156215080f, -0.291385430966355660f, 0.956549844114106820f, + -0.291568852460749040f, + 0.956493918902395100f, -0.291752263234989260f, 0.956437958523136180f, + -0.291935663282332780f, + 0.956381962978387730f, -0.292119052596036380f, 0.956325932270208230f, + -0.292302431169357560f, + 0.956269866400658030f, -0.292485798995553880f, 0.956213765371798470f, + -0.292669156067883460f, + 0.956157629185692140f, -0.292852502379604810f, 0.956101457844403040f, + -0.293035837923976810f, + 0.956045251349996410f, -0.293219162694258630f, 0.955989009704538930f, + -0.293402476683710110f, + 0.955932732910098280f, -0.293585779885591200f, 0.955876420968743590f, + -0.293769072293162400f, + 0.955820073882545420f, -0.293952353899684660f, 0.955763691653575440f, + -0.294135624698419030f, + 0.955707274283906560f, -0.294318884682627400f, 0.955650821775613330f, + -0.294502133845571670f, + 0.955594334130771110f, -0.294685372180514330f, 0.955537811351456880f, + -0.294868599680718270f, + 0.955481253439748770f, -0.295051816339446720f, 0.955424660397726330f, + -0.295235022149963220f, + 0.955368032227470350f, -0.295418217105532010f, 0.955311368931062720f, + -0.295601401199417360f, + 0.955254670510586990f, -0.295784574424884260f, 0.955197936968127710f, + -0.295967736775197890f, + 0.955141168305770780f, -0.296150888243623790f, 0.955084364525603410f, + -0.296334028823428190f, + 0.955027525629714160f, -0.296517158507877470f, 0.954970651620192790f, + -0.296700277290238350f, + 0.954913742499130520f, -0.296883385163778270f, 0.954856798268619580f, + -0.297066482121764730f, + 0.954799818930753720f, -0.297249568157465840f, 0.954742804487627940f, + -0.297432643264150030f, + 0.954685754941338340f, -0.297615707435086200f, 0.954628670293982680f, + -0.297798760663543550f, + 0.954571550547659630f, -0.297981802942791810f, 0.954514395704469500f, + -0.298164834266100850f, + 0.954457205766513490f, -0.298347854626741400f, 0.954399980735894490f, + -0.298530864017984120f, + 0.954342720614716480f, -0.298713862433100330f, 0.954285425405084650f, + -0.298896849865361800f, + 0.954228095109105670f, -0.299079826308040480f, 0.954170729728887280f, + -0.299262791754408840f, + 0.954113329266538800f, -0.299445746197739890f, 0.954055893724170660f, + -0.299628689631306790f, + 0.953998423103894490f, -0.299811622048383350f, 0.953940917407823500f, + -0.299994543442243580f, + 0.953883376638071770f, -0.300177453806161950f, 0.953825800796755050f, + -0.300360353133413530f, + 0.953768189885990330f, -0.300543241417273450f, 0.953710543907895670f, + -0.300726118651017500f, + 0.953652862864590500f, -0.300908984827921890f, 0.953595146758195680f, + -0.301091839941263100f, + 0.953537395590833280f, -0.301274683984317950f, 0.953479609364626610f, + -0.301457516950363940f, + 0.953421788081700310f, -0.301640338832678770f, 0.953363931744180330f, + -0.301823149624540650f, + 0.953306040354193860f, -0.302005949319228080f, 0.953248113913869320f, + -0.302188737910019990f, + 0.953190152425336670f, -0.302371515390195970f, 0.953132155890726750f, + -0.302554281753035610f, + 0.953074124312172200f, -0.302737036991819140f, 0.953016057691806530f, + -0.302919781099827310f, + 0.952957956031764700f, -0.303102514070341060f, 0.952899819334182880f, + -0.303285235896641750f, + 0.952841647601198720f, -0.303467946572011320f, 0.952783440834950920f, + -0.303650646089731910f, + 0.952725199037579570f, -0.303833334443086360f, 0.952666922211226170f, + -0.304016011625357570f, + 0.952608610358033350f, -0.304198677629829110f, 0.952550263480144930f, + -0.304381332449784880f, + 0.952491881579706320f, -0.304563976078509100f, 0.952433464658864030f, + -0.304746608509286530f, + 0.952375012719765880f, -0.304929229735402370f, 0.952316525764560940f, + -0.305111839750142110f, + 0.952258003795399600f, -0.305294438546791670f, 0.952199446814433580f, + -0.305477026118637420f, + 0.952140854823815830f, -0.305659602458966120f, 0.952082227825700620f, + -0.305842167561065080f, + 0.952023565822243570f, -0.306024721418221790f, 0.951964868815601380f, + -0.306207264023724220f, + 0.951906136807932350f, -0.306389795370860920f, 0.951847369801395620f, + -0.306572315452920740f, + 0.951788567798152130f, -0.306754824263192780f, 0.951729730800363830f, + -0.306937321794966910f, + 0.951670858810193860f, -0.307119808041533100f, 0.951611951829806850f, + -0.307302282996181790f, + 0.951553009861368590f, -0.307484746652204100f, 0.951494032907046370f, + -0.307667199002891190f, + 0.951435020969008340f, -0.307849640041534870f, 0.951375974049424420f, + -0.308032069761427330f, + 0.951316892150465550f, -0.308214488155861050f, 0.951257775274304000f, + -0.308396895218129190f, + 0.951198623423113230f, -0.308579290941525090f, 0.951139436599068190f, + -0.308761675319342450f, + 0.951080214804345010f, -0.308944048344875710f, 0.951020958041121080f, + -0.309126410011419440f, + 0.950961666311575080f, -0.309308760312268730f, 0.950902339617887060f, + -0.309491099240719100f, + 0.950842977962238160f, -0.309673426790066380f, 0.950783581346811070f, + -0.309855742953607070f, + 0.950724149773789610f, -0.310038047724637890f, 0.950664683245358910f, + -0.310220341096455850f, + 0.950605181763705340f, -0.310402623062358720f, 0.950545645331016600f, + -0.310584893615644450f, + 0.950486073949481700f, -0.310767152749611470f, 0.950426467621290900f, + -0.310949400457558640f, + 0.950366826348635780f, -0.311131636732785270f, 0.950307150133709260f, + -0.311313861568590920f, + 0.950247438978705230f, -0.311496074958275910f, 0.950187692885819280f, + -0.311678276895140550f, + 0.950127911857248100f, -0.311860467372486020f, 0.950068095895189590f, + -0.312042646383613510f, + 0.950008245001843000f, -0.312224813921824880f, 0.949948359179409010f, + -0.312406969980422440f, + 0.949888438430089300f, -0.312589114552708710f, 0.949828482756087110f, + -0.312771247631986770f, + 0.949768492159606680f, -0.312953369211560200f, 0.949708466642853800f, + -0.313135479284732840f, + 0.949648406208035480f, -0.313317577844809010f, 0.949588310857359950f, + -0.313499664885093510f, + 0.949528180593036670f, -0.313681740398891520f, 0.949468015417276550f, + -0.313863804379508500f, + 0.949407815332291570f, -0.314045856820250710f, 0.949347580340295210f, + -0.314227897714424440f, + 0.949287310443502120f, -0.314409927055336660f, 0.949227005644128210f, + -0.314591944836294660f, + 0.949166665944390700f, -0.314773951050606070f, 0.949106291346508260f, + -0.314955945691579140f, + 0.949045881852700560f, -0.315137928752522440f, 0.948985437465188710f, + -0.315319900226744890f, + 0.948924958186195160f, -0.315501860107555990f, 0.948864444017943340f, + -0.315683808388265650f, + 0.948803894962658490f, -0.315865745062183960f, 0.948743311022566480f, + -0.316047670122621860f, + 0.948682692199895090f, -0.316229583562890330f, 0.948622038496872990f, + -0.316411485376300980f, + 0.948561349915730270f, -0.316593375556165850f, 0.948500626458698260f, + -0.316775254095797270f, + 0.948439868128009620f, -0.316957120988508150f, 0.948379074925898120f, + -0.317138976227611780f, + 0.948318246854599090f, -0.317320819806421740f, 0.948257383916349060f, + -0.317502651718252260f, + 0.948196486113385580f, -0.317684471956417970f, 0.948135553447947980f, + -0.317866280514233660f, + 0.948074585922276230f, -0.318048077385014950f, 0.948013583538612200f, + -0.318229862562077530f, + 0.947952546299198670f, -0.318411636038737790f, 0.947891474206279840f, + -0.318593397808312420f, + 0.947830367262101010f, -0.318775147864118480f, 0.947769225468909180f, + -0.318956886199473650f, + 0.947708048828952100f, -0.319138612807695900f, 0.947646837344479300f, + -0.319320327682103610f, + 0.947585591017741090f, -0.319502030816015690f, 0.947524309850989570f, + -0.319683722202751430f, + 0.947462993846477700f, -0.319865401835630500f, 0.947401643006459900f, + -0.320047069707973140f, + 0.947340257333192050f, -0.320228725813099860f, 0.947278836828930880f, + -0.320410370144331820f, + 0.947217381495934820f, -0.320592002694990330f, 0.947155891336463270f, + -0.320773623458397330f, + 0.947094366352777220f, -0.320955232427875210f, 0.947032806547138620f, + -0.321136829596746660f, + 0.946971211921810880f, -0.321318414958334850f, 0.946909582479058760f, + -0.321499988505963510f, + 0.946847918221148000f, -0.321681550232956580f, 0.946786219150346000f, + -0.321863100132638580f, + 0.946724485268921170f, -0.322044638198334510f, 0.946662716579143360f, + -0.322226164423369600f, + 0.946600913083283530f, -0.322407678801069850f, 0.946539074783614100f, + -0.322589181324761330f, + 0.946477201682408680f, -0.322770671987770710f, 0.946415293781942110f, + -0.322952150783425260f, + 0.946353351084490590f, -0.323133617705052330f, 0.946291373592331620f, + -0.323315072745979980f, + 0.946229361307743820f, -0.323496515899536710f, 0.946167314233007370f, + -0.323677947159051240f, + 0.946105232370403450f, -0.323859366517852850f, 0.946043115722214560f, + -0.324040773969271450f, + 0.945980964290724760f, -0.324222169506636960f, 0.945918778078219110f, + -0.324403553123280230f, + 0.945856557086983910f, -0.324584924812532150f, 0.945794301319306970f, + -0.324766284567724220f, + 0.945732010777477150f, -0.324947632382188430f, 0.945669685463784710f, + -0.325128968249257080f, + 0.945607325380521280f, -0.325310292162262930f, 0.945544930529979680f, + -0.325491604114539310f, + 0.945482500914453740f, -0.325672904099419850f, 0.945420036536239070f, + -0.325854192110238580f, + 0.945357537397632290f, -0.326035468140330240f, 0.945295003500931210f, + -0.326216732183029710f, + 0.945232434848435000f, -0.326397984231672490f, 0.945169831442444150f, + -0.326579224279594400f, + 0.945107193285260610f, -0.326760452320131730f, 0.945044520379187070f, + -0.326941668346621420f, + 0.944981812726528150f, -0.327122872352400510f, 0.944919070329589220f, + -0.327304064330806670f, + 0.944856293190677210f, -0.327485244275178000f, 0.944793481312100280f, + -0.327666412178853120f, + 0.944730634696167800f, -0.327847568035170840f, 0.944667753345190490f, + -0.328028711837470680f, + 0.944604837261480260f, -0.328209843579092500f, 0.944541886447350490f, + -0.328390963253376580f, + 0.944478900905115550f, -0.328572070853663740f, 0.944415880637091250f, + -0.328753166373294990f, + 0.944352825645594750f, -0.328934249805612200f, 0.944289735932944410f, + -0.329115321143957250f, + 0.944226611501459810f, -0.329296380381672750f, 0.944163452353461770f, + -0.329477427512101740f, + 0.944100258491272660f, -0.329658462528587490f, 0.944037029917215830f, + -0.329839485424473940f, + 0.943973766633615980f, -0.330020496193105420f, 0.943910468642799150f, + -0.330201494827826570f, + 0.943847135947092690f, -0.330382481321982780f, 0.943783768548825060f, + -0.330563455668919540f, + 0.943720366450326200f, -0.330744417861982890f, 0.943656929653927220f, + -0.330925367894519540f, + 0.943593458161960390f, -0.331106305759876430f, 0.943529951976759480f, + -0.331287231451400820f, + 0.943466411100659320f, -0.331468144962440870f, 0.943402835535996240f, + -0.331649046286344670f, + 0.943339225285107720f, -0.331829935416461110f, 0.943275580350332540f, + -0.332010812346139380f, + 0.943211900734010620f, -0.332191677068729150f, 0.943148186438483420f, + -0.332372529577580620f, + 0.943084437466093490f, -0.332553369866044220f, 0.943020653819184650f, + -0.332734197927471050f, + 0.942956835500102120f, -0.332915013755212650f, 0.942892982511192250f, + -0.333095817342620780f, + 0.942829094854802710f, -0.333276608683047930f, 0.942765172533282510f, + -0.333457387769846850f, + 0.942701215548981900f, -0.333638154596370860f, 0.942637223904252530f, + -0.333818909155973620f, + 0.942573197601446870f, -0.333999651442009380f, 0.942509136642919240f, + -0.334180381447832690f, + 0.942445041031024890f, -0.334361099166798740f, 0.942380910768120470f, + -0.334541804592262900f, + 0.942316745856563780f, -0.334722497717581220f, 0.942252546298714020f, + -0.334903178536110180f, + 0.942188312096931770f, -0.335083847041206580f, 0.942124043253578570f, + -0.335264503226227810f, + 0.942059739771017310f, -0.335445147084531600f, 0.941995401651612550f, + -0.335625778609476290f, + 0.941931028897729620f, -0.335806397794420450f, 0.941866621511735280f, + -0.335987004632723350f, + 0.941802179495997650f, -0.336167599117744520f, 0.941737702852886160f, + -0.336348181242844050f, + 0.941673191584771360f, -0.336528751001382410f, 0.941608645694025250f, + -0.336709308386720580f, + 0.941544065183020810f, -0.336889853392220050f, 0.941479450054132580f, + -0.337070386011242620f, + 0.941414800309736340f, -0.337250906237150590f, 0.941350115952208970f, + -0.337431414063306840f, + 0.941285396983928660f, -0.337611909483074620f, 0.941220643407275180f, + -0.337792392489817460f, + 0.941155855224629190f, -0.337972863076899720f, 0.941091032438372780f, + -0.338153321237685930f, + 0.941026175050889260f, -0.338333766965541130f, 0.940961283064563280f, + -0.338514200253830940f, + 0.940896356481780830f, -0.338694621095921190f, 0.940831395304928870f, + -0.338875029485178450f, + 0.940766399536396070f, -0.339055425414969640f, 0.940701369178571940f, + -0.339235808878661950f, + 0.940636304233847590f, -0.339416179869623360f, 0.940571204704615190f, + -0.339596538381222110f, + 0.940506070593268300f, -0.339776884406826850f, 0.940440901902201750f, + -0.339957217939806880f, + 0.940375698633811540f, -0.340137538973531720f, 0.940310460790495070f, + -0.340317847501371670f, + 0.940245188374650880f, -0.340498143516697160f, 0.940179881388678920f, + -0.340678427012879200f, + 0.940114539834980280f, -0.340858697983289440f, 0.940049163715957370f, + -0.341038956421299720f, + 0.939983753034014050f, -0.341219202320282360f, 0.939918307791555050f, + -0.341399435673610420f, + 0.939852827990986680f, -0.341579656474657160f, 0.939787313634716570f, + -0.341759864716796310f, + 0.939721764725153340f, -0.341940060393402190f, 0.939656181264707180f, + -0.342120243497849530f, + 0.939590563255789270f, -0.342300414023513520f, 0.939524910700812230f, + -0.342480571963769800f, + 0.939459223602189920f, -0.342660717311994380f, 0.939393501962337510f, + -0.342840850061563950f, + 0.939327745783671400f, -0.343020970205855540f, 0.939261955068609210f, + -0.343201077738246540f, + 0.939196129819569900f, -0.343381172652115040f, 0.939130270038973650f, + -0.343561254940839390f, + 0.939064375729241950f, -0.343741324597798490f, 0.938998446892797540f, + -0.343921381616371700f, + 0.938932483532064600f, -0.344101425989938810f, 0.938866485649468060f, + -0.344281457711880180f, + 0.938800453247434770f, -0.344461476775576540f, 0.938734386328392460f, + -0.344641483174408960f, + 0.938668284894770170f, -0.344821476901759290f, 0.938602148948998400f, + -0.345001457951009670f, + 0.938535978493508560f, -0.345181426315542550f, 0.938469773530733800f, + -0.345361381988741220f, + 0.938403534063108060f, -0.345541324963989090f, 0.938337260093066950f, + -0.345721255234670120f, + 0.938270951623047190f, -0.345901172794168990f, 0.938204608655486490f, + -0.346081077635870430f, + 0.938138231192824360f, -0.346260969753160010f, 0.938071819237501270f, + -0.346440849139423520f, + 0.938005372791958840f, -0.346620715788047320f, 0.937938891858640320f, + -0.346800569692418290f, + 0.937872376439989890f, -0.346980410845923680f, 0.937805826538453120f, + -0.347160239241951160f, + 0.937739242156476970f, -0.347340054873889140f, 0.937672623296509470f, + -0.347519857735126110f, + 0.937605969960999990f, -0.347699647819051380f, 0.937539282152399230f, + -0.347879425119054510f, + 0.937472559873159250f, -0.348059189628525610f, 0.937405803125732960f, + -0.348238941340855260f, + 0.937339011912574960f, -0.348418680249434560f, 0.937272186236140950f, + -0.348598406347654930f, + 0.937205326098887960f, -0.348778119628908420f, 0.937138431503274140f, + -0.348957820086587490f, + 0.937071502451759190f, -0.349137507714084970f, 0.937004538946803690f, + -0.349317182504794380f, + 0.936937540990869900f, -0.349496844452109550f, 0.936870508586420960f, + -0.349676493549424760f, + 0.936803441735921560f, -0.349856129790134920f, 0.936736340441837620f, + -0.350035753167635240f, + 0.936669204706636170f, -0.350215363675321580f, 0.936602034532785570f, + -0.350394961306590150f, + 0.936534829922755500f, -0.350574546054837510f, 0.936467590879016990f, + -0.350754117913461060f, + 0.936400317404042060f, -0.350933676875858360f, 0.936333009500304180f, + -0.351113222935427460f, + 0.936265667170278260f, -0.351292756085567090f, 0.936198290416440090f, + -0.351472276319676310f, + 0.936130879241267030f, -0.351651783631154570f, 0.936063433647237540f, + -0.351831278013402030f, + 0.935995953636831410f, -0.352010759459819080f, 0.935928439212529660f, + -0.352190227963806830f, + 0.935860890376814640f, -0.352369683518766630f, 0.935793307132169900f, + -0.352549126118100460f, + 0.935725689481080370f, -0.352728555755210730f, 0.935658037426032040f, + -0.352907972423500250f, + 0.935590350969512370f, -0.353087376116372480f, 0.935522630114009930f, + -0.353266766827231240f, + 0.935454874862014620f, -0.353446144549480810f, 0.935387085216017770f, + -0.353625509276525970f, + 0.935319261178511610f, -0.353804861001772050f, 0.935251402751989920f, + -0.353984199718624770f, + 0.935183509938947610f, -0.354163525420490340f, 0.935115582741880890f, + -0.354342838100775550f, + 0.935047621163287430f, -0.354522137752887430f, 0.934979625205665800f, + -0.354701424370233830f, + 0.934911594871516090f, -0.354880697946222790f, 0.934843530163339540f, + -0.355059958474262860f, + 0.934775431083638700f, -0.355239205947763310f, 0.934707297634917440f, + -0.355418440360133650f, + 0.934639129819680780f, -0.355597661704783850f, 0.934570927640435030f, + -0.355776869975124640f, + 0.934502691099687870f, -0.355956065164566850f, 0.934434420199948050f, + -0.356135247266522130f, + 0.934366114943725790f, -0.356314416274402410f, 0.934297775333532530f, + -0.356493572181620090f, + 0.934229401371880820f, -0.356672714981588260f, 0.934160993061284530f, + -0.356851844667720300f, + 0.934092550404258980f, -0.357030961233429980f, 0.934024073403320390f, + -0.357210064672131960f, + 0.933955562060986730f, -0.357389154977240940f, 0.933887016379776890f, + -0.357568232142172260f, + 0.933818436362210960f, -0.357747296160341900f, 0.933749822010810580f, + -0.357926347025166010f, + 0.933681173328098410f, -0.358105384730061590f, 0.933612490316598540f, + -0.358284409268445850f, + 0.933543772978836170f, -0.358463420633736540f, 0.933475021317337950f, + -0.358642418819351990f, + 0.933406235334631520f, -0.358821403818710860f, 0.933337415033246190f, + -0.359000375625232460f, + 0.933268560415712050f, -0.359179334232336500f, 0.933199671484560730f, + -0.359358279633443130f, + 0.933130748242325230f, -0.359537211821973070f, 0.933061790691539380f, + -0.359716130791347570f, + 0.932992798834738960f, -0.359895036534988110f, 0.932923772674460140f, + -0.360073929046317020f, + 0.932854712213241120f, -0.360252808318756890f, 0.932785617453621100f, + -0.360431674345730700f, + 0.932716488398140250f, -0.360610527120662270f, 0.932647325049340450f, + -0.360789366636975580f, + 0.932578127409764420f, -0.360968192888095230f, 0.932508895481956590f, + -0.361147005867446250f, + 0.932439629268462360f, -0.361325805568454280f, 0.932370328771828460f, + -0.361504591984545260f, + 0.932300993994602760f, -0.361683365109145840f, 0.932231624939334540f, + -0.361862124935682980f, + 0.932162221608574430f, -0.362040871457584180f, 0.932092784004874050f, + -0.362219604668277460f, + 0.932023312130786490f, -0.362398324561191310f, 0.931953805988866010f, + -0.362577031129754760f, + 0.931884265581668150f, -0.362755724367397230f, 0.931814690911749730f, + -0.362934404267548640f, + 0.931745081981668720f, -0.363113070823639470f, 0.931675438793984620f, + -0.363291724029100760f, + 0.931605761351257830f, -0.363470363877363760f, 0.931536049656050300f, + -0.363648990361860550f, + 0.931466303710925090f, -0.363827603476023500f, 0.931396523518446600f, + -0.364006203213285470f, + 0.931326709081180430f, -0.364184789567079890f, 0.931256860401693420f, + -0.364363362530840620f, + 0.931186977482553750f, -0.364541922098002120f, 0.931117060326330790f, + -0.364720468261999280f, + 0.931047108935595280f, -0.364899001016267320f, 0.930977123312918930f, + -0.365077520354242180f, + 0.930907103460875130f, -0.365256026269360320f, 0.930837049382038150f, + -0.365434518755058390f, + 0.930766961078983710f, -0.365612997804773850f, 0.930696838554288860f, + -0.365791463411944570f, + 0.930626681810531760f, -0.365969915570008740f, 0.930556490850291800f, + -0.366148354272405330f, + 0.930486265676149780f, -0.366326779512573590f, 0.930416006290687550f, + -0.366505191283953370f, + 0.930345712696488470f, -0.366683589579984930f, 0.930275384896137150f, + -0.366861974394109060f, + 0.930205022892219070f, -0.367040345719767180f, 0.930134626687321390f, + -0.367218703550400980f, + 0.930064196284032360f, -0.367397047879452710f, 0.929993731684941480f, + -0.367575378700365330f, + 0.929923232892639670f, -0.367753696006581980f, 0.929852699909718750f, + -0.367931999791546450f, + 0.929782132738772190f, -0.368110290048703050f, 0.929711531382394370f, + -0.368288566771496570f, + 0.929640895843181330f, -0.368466829953372320f, 0.929570226123729860f, + -0.368645079587776040f, + 0.929499522226638560f, -0.368823315668153910f, 0.929428784154506800f, + -0.369001538187952780f, + 0.929358011909935500f, -0.369179747140620020f, 0.929287205495526790f, + -0.369357942519603130f, + 0.929216364913884040f, -0.369536124318350650f, 0.929145490167611720f, + -0.369714292530311240f, + 0.929074581259315860f, -0.369892447148934100f, 0.929003638191603360f, + -0.370070588167669080f, + 0.928932660967082820f, -0.370248715579966360f, 0.928861649588363700f, + -0.370426829379276790f, + 0.928790604058057020f, -0.370604929559051670f, 0.928719524378774810f, + -0.370783016112742560f, + 0.928648410553130520f, -0.370961089033801980f, 0.928577262583738850f, + -0.371139148315682570f, + 0.928506080473215590f, -0.371317193951837540f, 0.928434864224177980f, + -0.371495225935720760f, + 0.928363613839244370f, -0.371673244260786520f, 0.928292329321034670f, + -0.371851248920489490f, + 0.928221010672169440f, -0.372029239908285010f, 0.928149657895271150f, + -0.372207217217628840f, + 0.928078270992963140f, -0.372385180841977360f, 0.928006849967869970f, + -0.372563130774787250f, + 0.927935394822617890f, -0.372741067009515760f, 0.927863905559833780f, + -0.372918989539620830f, + 0.927792382182146320f, -0.373096898358560640f, 0.927720824692185200f, + -0.373274793459793970f, + 0.927649233092581180f, -0.373452674836780300f, 0.927577607385966730f, + -0.373630542482979280f, + 0.927505947574975180f, -0.373808396391851210f, 0.927434253662241300f, + -0.373986236556857030f, + 0.927362525650401110f, -0.374164062971457930f, 0.927290763542091720f, + -0.374341875629115920f, + 0.927218967339951790f, -0.374519674523293210f, 0.927147137046620880f, + -0.374697459647452600f, + 0.927075272664740100f, -0.374875230995057540f, 0.927003374196951670f, + -0.375052988559571920f, + 0.926931441645899130f, -0.375230732334459920f, 0.926859475014227160f, + -0.375408462313186590f, + 0.926787474304581750f, -0.375586178489217220f, 0.926715439519610330f, + -0.375763880856017700f, + 0.926643370661961230f, -0.375941569407054420f, 0.926571267734284330f, + -0.376119244135794340f, + 0.926499130739230510f, -0.376296905035704790f, 0.926426959679452210f, + -0.376474552100253770f, + 0.926354754557602860f, -0.376652185322909560f, 0.926282515376337210f, + -0.376829804697141280f, + 0.926210242138311380f, -0.377007410216418260f, 0.926137934846182560f, + -0.377185001874210450f, + 0.926065593502609310f, -0.377362579663988340f, 0.925993218110251480f, + -0.377540143579222940f, + 0.925920808671770070f, -0.377717693613385640f, 0.925848365189827270f, + -0.377895229759948490f, + 0.925775887667086740f, -0.378072752012383990f, 0.925703376106213230f, + -0.378250260364165200f, + 0.925630830509872720f, -0.378427754808765560f, 0.925558250880732740f, + -0.378605235339659120f, + 0.925485637221461490f, -0.378782701950320540f, 0.925412989534729060f, + -0.378960154634224720f, + 0.925340307823206310f, -0.379137593384847320f, 0.925267592089565660f, + -0.379315018195664430f, + 0.925194842336480530f, -0.379492429060152630f, 0.925122058566625880f, + -0.379669825971788940f, + 0.925049240782677580f, -0.379847208924051160f, 0.924976388987313160f, + -0.380024577910417270f, + 0.924903503183210910f, -0.380201932924366050f, 0.924830583373050800f, + -0.380379273959376600f, + 0.924757629559513910f, -0.380556601008928520f, 0.924684641745282420f, + -0.380733914066502140f, + 0.924611619933039970f, -0.380911213125578070f, 0.924538564125471420f, + -0.381088498179637520f, + 0.924465474325262600f, -0.381265769222162380f, 0.924392350535101050f, + -0.381443026246634730f, + 0.924319192757675160f, -0.381620269246537360f, 0.924246000995674890f, + -0.381797498215353640f, + 0.924172775251791200f, -0.381974713146567220f, 0.924099515528716280f, + -0.382151914033662610f, + 0.924026221829143850f, -0.382329100870124510f, 0.923952894155768640f, + -0.382506273649438230f, + 0.923879532511286740f, -0.382683432365089780f, 0.923806136898395410f, + -0.382860577010565420f, + 0.923732707319793290f, -0.383037707579352020f, 0.923659243778179980f, + -0.383214824064937180f, + 0.923585746276256670f, -0.383391926460808660f, 0.923512214816725630f, + -0.383569014760454910f, + 0.923438649402290370f, -0.383746088957365010f, 0.923365050035655720f, + -0.383923149045028390f, + 0.923291416719527640f, -0.384100195016935040f, 0.923217749456613500f, + -0.384277226866575510f, + 0.923144048249621930f, -0.384454244587440820f, 0.923070313101262420f, + -0.384631248173022580f, + 0.922996544014246250f, -0.384808237616812880f, 0.922922740991285680f, + -0.384985212912304200f, + 0.922848904035094120f, -0.385162174052989860f, 0.922775033148386380f, + -0.385339121032363340f, + 0.922701128333878630f, -0.385516053843918850f, 0.922627189594287910f, + -0.385692972481151140f, + 0.922553216932332830f, -0.385869876937555310f, 0.922479210350733210f, + -0.386046767206627170f, + 0.922405169852209880f, -0.386223643281862980f, 0.922331095439485440f, + -0.386400505156759440f, + 0.922256987115283030f, -0.386577352824813920f, 0.922182844882327600f, + -0.386754186279524180f, + 0.922108668743345180f, -0.386931005514388580f, 0.922034458701062820f, + -0.387107810522905990f, + 0.921960214758209220f, -0.387284601298575840f, 0.921885936917513970f, + -0.387461377834897870f, + 0.921811625181708120f, -0.387638140125372730f, 0.921737279553523910f, + -0.387814888163501180f, + 0.921662900035694730f, -0.387991621942784860f, 0.921588486630955490f, + -0.388168341456725740f, + 0.921514039342042010f, -0.388345046698826250f, 0.921439558171691430f, + -0.388521737662589570f, + 0.921365043122642340f, -0.388698414341519190f, 0.921290494197634540f, + -0.388875076729119250f, + 0.921215911399408730f, -0.389051724818894380f, 0.921141294730707270f, + -0.389228358604349730f, + 0.921066644194273640f, -0.389404978078990940f, 0.920991959792852310f, + -0.389581583236324300f, + 0.920917241529189520f, -0.389758174069856410f, 0.920842489406032190f, + -0.389934750573094730f, + 0.920767703426128790f, -0.390111312739546910f, 0.920692883592229120f, + -0.390287860562721190f, + 0.920618029907083970f, -0.390464394036126590f, 0.920543142373445480f, + -0.390640913153272430f, + 0.920468220994067110f, -0.390817417907668500f, 0.920393265771703550f, + -0.390993908292825380f, + 0.920318276709110590f, -0.391170384302253870f, 0.920243253809045370f, + -0.391346845929465560f, + 0.920168197074266340f, -0.391523293167972410f, 0.920093106507533180f, + -0.391699726011286940f, + 0.920017982111606570f, -0.391876144452922350f, 0.919942823889248640f, + -0.392052548486392090f, + 0.919867631843222950f, -0.392228938105210310f, 0.919792405976293860f, + -0.392405313302891690f, + 0.919717146291227360f, -0.392581674072951470f, 0.919641852790790470f, + -0.392758020408905280f, + 0.919566525477751530f, -0.392934352304269490f, 0.919491164354880100f, + -0.393110669752560760f, + 0.919415769424947070f, -0.393286972747296400f, 0.919340340690724340f, + -0.393463261281994330f, + 0.919264878154985370f, -0.393639535350172880f, 0.919189381820504470f, + -0.393815794945351020f, + 0.919113851690057770f, -0.393992040061048100f, 0.919038287766422050f, + -0.394168270690784080f, + 0.918962690052375630f, -0.394344486828079600f, 0.918887058550697970f, + -0.394520688466455600f, + 0.918811393264170050f, -0.394696875599433560f, 0.918735694195573550f, + -0.394873048220535760f, + 0.918659961347691900f, -0.395049206323284770f, 0.918584194723309540f, + -0.395225349901203670f, + 0.918508394325212250f, -0.395401478947816350f, 0.918432560156186910f, + -0.395577593456646840f, + 0.918356692219021720f, -0.395753693421220080f, 0.918280790516506130f, + -0.395929778835061250f, + 0.918204855051430900f, -0.396105849691696270f, 0.918128885826588030f, + -0.396281905984651520f, + 0.918052882844770380f, -0.396457947707453910f, 0.917976846108772730f, + -0.396633974853630830f, + 0.917900775621390500f, -0.396809987416710310f, 0.917824671385420570f, + -0.396985985390220900f, + 0.917748533403661250f, -0.397161968767691610f, 0.917672361678911860f, + -0.397337937542652060f, + 0.917596156213972950f, -0.397513891708632330f, 0.917519917011646260f, + -0.397689831259163180f, + 0.917443644074735220f, -0.397865756187775750f, 0.917367337406043930f, + -0.398041666488001770f, + 0.917290997008377910f, -0.398217562153373560f, 0.917214622884544250f, + -0.398393443177423980f, + 0.917138215037350710f, -0.398569309553686300f, 0.917061773469606820f, + -0.398745161275694430f, + 0.916985298184123000f, -0.398920998336982910f, 0.916908789183710990f, + -0.399096820731086540f, + 0.916832246471183890f, -0.399272628451540990f, 0.916755670049355990f, + -0.399448421491882140f, + 0.916679059921042700f, -0.399624199845646790f, 0.916602416089060790f, + -0.399799963506371980f, + 0.916525738556228210f, -0.399975712467595330f, 0.916449027325364150f, + -0.400151446722855130f, + 0.916372282399289140f, -0.400327166265690090f, 0.916295503780824800f, + -0.400502871089639500f, + 0.916218691472794220f, -0.400678561188243240f, 0.916141845478021350f, + -0.400854236555041650f, + 0.916064965799331720f, -0.401029897183575620f, 0.915988052439551950f, + -0.401205543067386710f, + 0.915911105401509880f, -0.401381174200016790f, 0.915834124688034710f, + -0.401556790575008540f, + 0.915757110301956720f, -0.401732392185905010f, 0.915680062246107650f, + -0.401907979026249700f, + 0.915602980523320230f, -0.402083551089586990f, 0.915525865136428530f, + -0.402259108369461490f, + 0.915448716088267830f, -0.402434650859418430f, 0.915371533381674760f, + -0.402610178553003680f, + 0.915294317019487050f, -0.402785691443763530f, 0.915217067004543860f, + -0.402961189525244900f, + 0.915139783339685260f, -0.403136672790995300f, 0.915062466027752760f, + -0.403312141234562550f, + 0.914985115071589310f, -0.403487594849495310f, 0.914907730474038730f, + -0.403663033629342640f, + 0.914830312237946200f, -0.403838457567654070f, 0.914752860366158220f, + -0.404013866657979890f, + 0.914675374861522390f, -0.404189260893870690f, 0.914597855726887790f, + -0.404364640268877810f, + 0.914520302965104450f, -0.404540004776553000f, 0.914442716579023870f, + -0.404715354410448650f, + 0.914365096571498560f, -0.404890689164117580f, 0.914287442945382440f, + -0.405066009031113340f, + 0.914209755703530690f, -0.405241314004989860f, 0.914132034848799460f, + -0.405416604079301630f, + 0.914054280384046570f, -0.405591879247603870f, 0.913976492312130630f, + -0.405767139503452060f, + 0.913898670635911680f, -0.405942384840402510f, 0.913820815358251100f, + -0.406117615252011840f, + 0.913742926482011390f, -0.406292830731837360f, 0.913665004010056350f, + -0.406468031273437000f, + 0.913587047945250810f, -0.406643216870369030f, 0.913509058290461140f, + -0.406818387516192310f, + 0.913431035048554720f, -0.406993543204466510f, 0.913352978222400250f, + -0.407168683928751550f, + 0.913274887814867760f, -0.407343809682607970f, 0.913196763828828200f, + -0.407518920459596920f, + 0.913118606267154240f, -0.407694016253280110f, 0.913040415132719160f, + -0.407869097057219800f, + 0.912962190428398210f, -0.408044162864978690f, 0.912883932157067200f, + -0.408219213670120100f, + 0.912805640321603500f, -0.408394249466208000f, 0.912727314924885900f, + -0.408569270246806780f, + 0.912648955969793900f, -0.408744276005481360f, 0.912570563459208730f, + -0.408919266735797430f, + 0.912492137396012650f, -0.409094242431320980f, 0.912413677783089020f, + -0.409269203085618590f, + 0.912335184623322750f, -0.409444148692257590f, 0.912256657919599760f, + -0.409619079244805670f, + 0.912178097674807180f, -0.409793994736831150f, 0.912099503891833470f, + -0.409968895161902880f, + 0.912020876573568340f, -0.410143780513590240f, 0.911942215722902570f, + -0.410318650785463260f, + 0.911863521342728520f, -0.410493505971092410f, 0.911784793435939430f, + -0.410668346064048730f, + 0.911706032005429880f, -0.410843171057903910f, 0.911627237054095650f, + -0.411017980946230210f, + 0.911548408584833990f, -0.411192775722600160f, 0.911469546600543020f, + -0.411367555380587220f, + 0.911390651104122430f, -0.411542319913765220f, 0.911311722098472780f, + -0.411717069315708560f, + 0.911232759586496190f, -0.411891803579992170f, 0.911153763571095900f, + -0.412066522700191560f, + 0.911074734055176360f, -0.412241226669882890f, 0.910995671041643140f, + -0.412415915482642730f, + 0.910916574533403360f, -0.412590589132048210f, 0.910837444533365010f, + -0.412765247611677270f, + 0.910758281044437570f, -0.412939890915108080f, 0.910679084069531570f, + -0.413114519035919450f, + 0.910599853611558930f, -0.413289131967690960f, 0.910520589673432750f, + -0.413463729704002410f, + 0.910441292258067250f, -0.413638312238434500f, 0.910361961368377990f, + -0.413812879564568300f, + 0.910282597007281760f, -0.413987431675985400f, 0.910203199177696540f, + -0.414161968566268080f, + 0.910123767882541680f, -0.414336490228999100f, 0.910044303124737500f, + -0.414510996657761750f, + 0.909964804907205660f, -0.414685487846140010f, 0.909885273232869160f, + -0.414859963787718330f, + 0.909805708104652220f, -0.415034424476081630f, 0.909726109525480160f, + -0.415208869904815590f, + 0.909646477498279540f, -0.415383300067506230f, 0.909566812025978330f, + -0.415557714957740410f, + 0.909487113111505430f, -0.415732114569105360f, 0.909407380757791260f, + -0.415906498895188770f, + 0.909327614967767260f, -0.416080867929579210f, 0.909247815744366310f, + -0.416255221665865480f, + 0.909167983090522380f, -0.416429560097637150f, 0.909088117009170580f, + -0.416603883218484350f, + 0.909008217503247450f, -0.416778191021997650f, 0.908928284575690640f, + -0.416952483501768170f, + 0.908848318229439120f, -0.417126760651387870f, 0.908768318467432890f, + -0.417301022464448890f, + 0.908688285292613360f, -0.417475268934544290f, 0.908608218707923190f, + -0.417649500055267410f, + 0.908528118716306120f, -0.417823715820212270f, 0.908447985320707250f, + -0.417997916222973550f, + 0.908367818524072890f, -0.418172101257146320f, 0.908287618329350450f, + -0.418346270916326260f, + 0.908207384739488700f, -0.418520425194109700f, 0.908127117757437600f, + -0.418694564084093560f, + 0.908046817386148340f, -0.418868687579875050f, 0.907966483628573350f, + -0.419042795675052370f, + 0.907886116487666260f, -0.419216888363223910f, 0.907805715966381930f, + -0.419390965637988890f, + 0.907725282067676440f, -0.419565027492946880f, 0.907644814794507200f, + -0.419739073921698180f, + 0.907564314149832630f, -0.419913104917843620f, 0.907483780136612570f, + -0.420087120474984530f, + 0.907403212757808110f, -0.420261120586722880f, 0.907322612016381420f, + -0.420435105246661170f, + 0.907241977915295820f, -0.420609074448402510f, 0.907161310457516250f, + -0.420783028185550520f, + 0.907080609646008450f, -0.420956966451709440f, 0.906999875483739610f, + -0.421130889240483970f, + 0.906919107973678140f, -0.421304796545479640f, 0.906838307118793430f, + -0.421478688360302280f, + 0.906757472922056550f, -0.421652564678558330f, 0.906676605386439460f, + -0.421826425493854910f, + 0.906595704514915330f, -0.422000270799799680f, 0.906514770310458800f, + -0.422174100590000770f, + 0.906433802776045460f, -0.422347914858067050f, 0.906352801914652400f, + -0.422521713597607820f, + 0.906271767729257660f, -0.422695496802232950f, 0.906190700222840650f, + -0.422869264465553060f, + 0.906109599398381980f, -0.423043016581179040f, 0.906028465258863600f, + -0.423216753142722610f, + 0.905947297807268460f, -0.423390474143796050f, 0.905866097046580940f, + -0.423564179578011960f, + 0.905784862979786550f, -0.423737869438983840f, 0.905703595609872010f, + -0.423911543720325580f, + 0.905622294939825270f, -0.424085202415651560f, 0.905540960972635590f, + -0.424258845518576950f, + 0.905459593711293250f, -0.424432473022717420f, 0.905378193158790090f, + -0.424606084921689110f, + 0.905296759318118820f, -0.424779681209108810f, 0.905215292192273590f, + -0.424953261878593890f, + 0.905133791784249690f, -0.425126826923762360f, 0.905052258097043590f, + -0.425300376338232640f, + 0.904970691133653250f, -0.425473910115623800f, 0.904889090897077470f, + -0.425647428249555590f, + 0.904807457390316540f, -0.425820930733648240f, 0.904725790616371930f, + -0.425994417561522400f, + 0.904644090578246240f, -0.426167888726799620f, 0.904562357278943300f, + -0.426341344223101830f, + 0.904480590721468250f, -0.426514784044051520f, 0.904398790908827350f, + -0.426688208183271860f, + 0.904316957844028320f, -0.426861616634386430f, 0.904235091530079750f, + -0.427035009391019680f, + 0.904153191969991780f, -0.427208386446796320f, 0.904071259166775440f, + -0.427381747795341770f, + 0.903989293123443340f, -0.427555093430282080f, 0.903907293843009050f, + -0.427728423345243800f, + 0.903825261328487510f, -0.427901737533854080f, 0.903743195582894620f, + -0.428075035989740730f, + 0.903661096609247980f, -0.428248318706531960f, 0.903578964410566070f, + -0.428421585677856650f, + 0.903496798989868450f, -0.428594836897344400f, 0.903414600350176290f, + -0.428768072358625070f, + 0.903332368494511820f, -0.428941292055329490f, 0.903250103425898400f, + -0.429114495981088750f, + 0.903167805147360720f, -0.429287684129534610f, 0.903085473661924600f, + -0.429460856494299490f, + 0.903003108972617150f, -0.429634013069016380f, 0.902920711082466740f, + -0.429807153847318710f, + 0.902838279994502830f, -0.429980278822840620f, 0.902755815711756120f, + -0.430153387989216870f, + 0.902673318237258830f, -0.430326481340082610f, 0.902590787574043870f, + -0.430499558869073820f, + 0.902508223725145940f, -0.430672620569826800f, 0.902425626693600380f, + -0.430845666435978660f, + 0.902342996482444200f, -0.431018696461167030f, 0.902260333094715540f, + -0.431191710639029950f, + 0.902177636533453620f, -0.431364708963206330f, 0.902094906801698900f, + -0.431537691427335500f, + 0.902012143902493180f, -0.431710658025057260f, 0.901929347838879460f, + -0.431883608750012250f, + 0.901846518613901750f, -0.432056543595841500f, 0.901763656230605730f, + -0.432229462556186720f, + 0.901680760692037730f, -0.432402365624690140f, 0.901597832001245660f, + -0.432575252794994650f, + 0.901514870161278740f, -0.432748124060743700f, 0.901431875175186970f, + -0.432920979415581280f, + 0.901348847046022030f, -0.433093818853151960f, 0.901265785776836580f, + -0.433266642367100940f, + 0.901182691370684520f, -0.433439449951074090f, 0.901099563830620950f, + -0.433612241598717580f, + 0.901016403159702330f, -0.433785017303678520f, 0.900933209360986200f, + -0.433957777059604420f, + 0.900849982437531450f, -0.434130520860143310f, 0.900766722392397860f, + -0.434303248698943990f, + 0.900683429228646970f, -0.434475960569655650f, 0.900600102949340900f, + -0.434648656465928320f, + 0.900516743557543520f, -0.434821336381412290f, 0.900433351056319830f, + -0.434994000309758710f, + 0.900349925448735600f, -0.435166648244619260f, 0.900266466737858480f, + -0.435339280179646070f, + 0.900182974926756810f, -0.435511896108492000f, 0.900099450018500450f, + -0.435684496024810460f, + 0.900015892016160280f, -0.435857079922255470f, 0.899932300922808510f, + -0.436029647794481560f, + 0.899848676741518580f, -0.436202199635143950f, 0.899765019475365140f, + -0.436374735437898340f, + 0.899681329127423930f, -0.436547255196401200f, 0.899597605700772180f, + -0.436719758904309360f, + 0.899513849198487980f, -0.436892246555280360f, 0.899430059623650860f, + -0.437064718142972370f, + 0.899346236979341570f, -0.437237173661044090f, 0.899262381268642000f, + -0.437409613103154790f, + 0.899178492494635330f, -0.437582036462964400f, 0.899094570660405770f, + -0.437754443734133410f, + 0.899010615769039070f, -0.437926834910322860f, 0.898926627823621870f, + -0.438099209985194470f, + 0.898842606827242370f, -0.438271568952410430f, 0.898758552782989440f, + -0.438443911805633690f, + 0.898674465693953820f, -0.438616238538527660f, 0.898590345563227030f, + -0.438788549144756290f, + 0.898506192393901950f, -0.438960843617984320f, 0.898422006189072530f, + -0.439133121951876930f, + 0.898337786951834310f, -0.439305384140099950f, 0.898253534685283570f, + -0.439477630176319800f, + 0.898169249392518080f, -0.439649860054203480f, 0.898084931076636780f, + -0.439822073767418500f, + 0.898000579740739880f, -0.439994271309633260f, 0.897916195387928660f, + -0.440166452674516320f, + 0.897831778021305650f, -0.440338617855737250f, 0.897747327643974690f, + -0.440510766846965940f, + 0.897662844259040860f, -0.440682899641872900f, 0.897578327869610230f, + -0.440855016234129430f, + 0.897493778478790310f, -0.441027116617407230f, 0.897409196089689720f, + -0.441199200785378660f, + 0.897324580705418320f, -0.441371268731716670f, 0.897239932329087160f, + -0.441543320450094870f, + 0.897155250963808550f, -0.441715355934187310f, 0.897070536612695870f, + -0.441887375177668850f, + 0.896985789278863970f, -0.442059378174214700f, 0.896901008965428790f, + -0.442231364917500980f, + 0.896816195675507300f, -0.442403335401204080f, 0.896731349412217880f, + -0.442575289619001170f, + 0.896646470178680150f, -0.442747227564570020f, 0.896561557978014960f, + -0.442919149231588980f, + 0.896476612813344120f, -0.443091054613736880f, 0.896391634687790820f, + -0.443262943704693320f, + 0.896306623604479550f, -0.443434816498138480f, 0.896221579566536030f, + -0.443606672987752970f, + 0.896136502577086770f, -0.443778513167218220f, 0.896051392639260150f, + -0.443950337030216140f, + 0.895966249756185220f, -0.444122144570429200f, 0.895881073930992370f, + -0.444293935781540580f, + 0.895795865166813530f, -0.444465710657234000f, 0.895710623466781320f, + -0.444637469191193790f, + 0.895625348834030110f, -0.444809211377104880f, 0.895540041271694950f, + -0.444980937208652730f, + 0.895454700782912450f, -0.445152646679523640f, 0.895369327370820310f, + -0.445324339783404190f, + 0.895283921038557580f, -0.445496016513981740f, 0.895198481789264200f, + -0.445667676864944300f, + 0.895113009626081760f, -0.445839320829980290f, 0.895027504552152630f, + -0.446010948402778940f, + 0.894941966570620750f, -0.446182559577030070f, 0.894856395684631050f, + -0.446354154346423840f, + 0.894770791897329550f, -0.446525732704651350f, 0.894685155211863980f, + -0.446697294645404090f, + 0.894599485631382700f, -0.446868840162374160f, 0.894513783159035620f, + -0.447040369249254440f, + 0.894428047797973800f, -0.447211881899738320f, 0.894342279551349480f, + -0.447383378107519600f, + 0.894256478422316040f, -0.447554857866293010f, 0.894170644414028270f, + -0.447726321169753580f, + 0.894084777529641990f, -0.447897768011597310f, 0.893998877772314240f, + -0.448069198385520400f, + 0.893912945145203250f, -0.448240612285219890f, 0.893826979651468620f, + -0.448412009704393430f, + 0.893740981294271040f, -0.448583390636739240f, 0.893654950076772540f, + -0.448754755075955970f, + 0.893568886002135910f, -0.448926103015743260f, 0.893482789073525850f, + -0.449097434449801050f, + 0.893396659294107720f, -0.449268749371829920f, 0.893310496667048200f, + -0.449440047775531150f, + 0.893224301195515320f, -0.449611329654606540f, 0.893138072882678320f, + -0.449782595002758690f, + 0.893051811731707450f, -0.449953843813690520f, 0.892965517745774370f, + -0.450125076081105690f, + 0.892879190928051680f, -0.450296291798708610f, 0.892792831281713610f, + -0.450467490960204110f, + 0.892706438809935390f, -0.450638673559297600f, 0.892620013515893150f, + -0.450809839589695280f, + 0.892533555402764580f, -0.450980989045103860f, 0.892447064473728680f, + -0.451152121919230600f, + 0.892360540731965360f, -0.451323238205783520f, 0.892273984180655840f, + -0.451494337898471100f, + 0.892187394822982480f, -0.451665420991002490f, 0.892100772662129060f, + -0.451836487477087490f, + 0.892014117701280470f, -0.452007537350436420f, 0.891927429943622510f, + -0.452178570604760350f, + 0.891840709392342720f, -0.452349587233770890f, 0.891753956050629460f, + -0.452520587231180050f, + 0.891667169921672280f, -0.452691570590700920f, 0.891580351008662290f, + -0.452862537306046750f, + 0.891493499314791380f, -0.453033487370931580f, 0.891406614843252900f, + -0.453204420779070190f, + 0.891319697597241390f, -0.453375337524177750f, 0.891232747579952520f, + -0.453546237599970090f, + 0.891145764794583180f, -0.453717121000163870f, 0.891058749244331590f, + -0.453887987718476050f, + 0.890971700932396860f, -0.454058837748624430f, 0.890884619861979530f, + -0.454229671084327320f, + 0.890797506036281490f, -0.454400487719303580f, 0.890710359458505630f, + -0.454571287647272950f, + 0.890623180131855930f, -0.454742070861955450f, 0.890535968059537830f, + -0.454912837357071940f, + 0.890448723244757880f, -0.455083587126343840f, 0.890361445690723840f, + -0.455254320163493100f, + 0.890274135400644600f, -0.455425036462242360f, 0.890186792377730240f, + -0.455595736016314980f, + 0.890099416625192320f, -0.455766418819434640f, 0.890012008146243260f, + -0.455937084865326030f, + 0.889924566944096720f, -0.456107734147714110f, 0.889837093021967900f, + -0.456278366660324620f, + 0.889749586383072780f, -0.456448982396883920f, 0.889662047030628900f, + -0.456619581351118910f, + 0.889574474967854580f, -0.456790163516757160f, 0.889486870197969900f, + -0.456960728887526980f, + 0.889399232724195520f, -0.457131277457156980f, 0.889311562549753850f, + -0.457301809219376630f, + 0.889223859677868210f, -0.457472324167916060f, 0.889136124111763240f, + -0.457642822296505770f, + 0.889048355854664570f, -0.457813303598877170f, 0.888960554909799310f, + -0.457983768068762120f, + 0.888872721280395630f, -0.458154215699893060f, 0.888784854969682850f, + -0.458324646486003240f, + 0.888696955980891600f, -0.458495060420826270f, 0.888609024317253860f, + -0.458665457498096560f, + 0.888521059982002260f, -0.458835837711549120f, 0.888433062978371320f, + -0.459006201054919630f, + 0.888345033309596350f, -0.459176547521944090f, 0.888256970978913870f, + -0.459346877106359630f, + 0.888168875989561730f, -0.459517189801903480f, 0.888080748344778900f, + -0.459687485602313870f, + 0.887992588047805560f, -0.459857764501329540f, 0.887904395101883240f, + -0.460028026492689650f, + 0.887816169510254440f, -0.460198271570134320f, 0.887727911276163020f, + -0.460368499727404010f, + 0.887639620402853930f, -0.460538710958240010f, 0.887551296893573370f, + -0.460708905256384080f, + 0.887462940751568840f, -0.460879082615578690f, 0.887374551980088850f, + -0.461049243029566900f, + 0.887286130582383150f, -0.461219386492092380f, 0.887197676561702900f, + -0.461389512996899450f, + 0.887109189921300170f, -0.461559622537733080f, 0.887020670664428360f, + -0.461729715108338770f, + 0.886932118794342190f, -0.461899790702462730f, 0.886843534314297410f, + -0.462069849313851750f, + 0.886754917227550840f, -0.462239890936253340f, 0.886666267537361000f, + -0.462409915563415430f, + 0.886577585246987040f, -0.462579923189086810f, 0.886488870359689600f, + -0.462749913807016740f, + 0.886400122878730600f, -0.462919887410955080f, 0.886311342807372780f, + -0.463089843994652530f, + 0.886222530148880640f, -0.463259783551860150f, 0.886133684906519340f, + -0.463429706076329830f, + 0.886044807083555600f, -0.463599611561814010f, 0.885955896683257030f, + -0.463769500002065630f, + 0.885866953708892790f, -0.463939371390838520f, 0.885777978163732940f, + -0.464109225721886950f, + 0.885688970051048960f, -0.464279062988965760f, 0.885599929374113360f, + -0.464448883185830660f, + 0.885510856136199950f, -0.464618686306237820f, 0.885421750340583680f, + -0.464788472343943990f, + 0.885332611990540590f, -0.464958241292706690f, 0.885243441089348270f, + -0.465127993146283950f, + 0.885154237640285110f, -0.465297727898434600f, 0.885065001646630930f, + -0.465467445542917800f, + 0.884975733111666660f, -0.465637146073493660f, 0.884886432038674560f, + -0.465806829483922710f, + 0.884797098430937790f, -0.465976495767966180f, 0.884707732291741040f, + -0.466146144919385890f, + 0.884618333624369920f, -0.466315776931944430f, 0.884528902432111460f, + -0.466485391799404900f, + 0.884439438718253810f, -0.466654989515530920f, 0.884349942486086120f, + -0.466824570074086950f, + 0.884260413738899190f, -0.466994133468838000f, 0.884170852479984500f, + -0.467163679693549770f, + 0.884081258712634990f, -0.467333208741988420f, 0.883991632440144890f, + -0.467502720607920920f, + 0.883901973665809470f, -0.467672215285114770f, 0.883812282392925090f, + -0.467841692767338170f, + 0.883722558624789660f, -0.468011153048359830f, 0.883632802364701870f, + -0.468180596121949290f, + 0.883543013615961880f, -0.468350021981876530f, 0.883453192381870920f, + -0.468519430621912310f, + 0.883363338665731580f, -0.468688822035827900f, 0.883273452470847430f, + -0.468858196217395330f, + 0.883183533800523390f, -0.469027553160387130f, 0.883093582658065370f, + -0.469196892858576580f, + 0.883003599046780830f, -0.469366215305737520f, 0.882913582969978020f, + -0.469535520495644450f, + 0.882823534430966620f, -0.469704808422072460f, 0.882733453433057650f, + -0.469874079078797360f, + 0.882643339979562790f, -0.470043332459595620f, 0.882553194073795510f, + -0.470212568558244170f, + 0.882463015719070150f, -0.470381787368520650f, 0.882372804918702290f, + -0.470550988884203550f, + 0.882282561676008710f, -0.470720173099071600f, 0.882192285994307430f, + -0.470889340006904520f, + 0.882101977876917580f, -0.471058489601482500f, 0.882011637327159590f, + -0.471227621876586340f, + 0.881921264348355050f, -0.471396736825997640f, 0.881830858943826620f, + -0.471565834443498420f, + 0.881740421116898320f, -0.471734914722871430f, 0.881649950870895260f, + -0.471903977657900210f, + 0.881559448209143780f, -0.472073023242368660f, 0.881468913134971440f, + -0.472242051470061490f, + 0.881378345651706920f, -0.472411062334764040f, 0.881287745762680100f, + -0.472580055830262250f, + 0.881197113471222090f, -0.472749031950342790f, 0.881106448780665130f, + -0.472917990688792760f, + 0.881015751694342870f, -0.473086932039400050f, 0.880925022215589880f, + -0.473255855995953320f, + 0.880834260347742040f, -0.473424762552241530f, 0.880743466094136340f, + -0.473593651702054530f, + 0.880652639458111010f, -0.473762523439182850f, 0.880561780443005700f, + -0.473931377757417450f, + 0.880470889052160750f, -0.474100214650549970f, 0.880379965288918150f, + -0.474269034112372980f, + 0.880289009156621010f, -0.474437836136679230f, 0.880198020658613190f, + -0.474606620717262560f, + 0.880106999798240360f, -0.474775387847917120f, 0.880015946578849070f, + -0.474944137522437800f, + 0.879924861003786860f, -0.475112869734620300f, 0.879833743076402940f, + -0.475281584478260740f, + 0.879742592800047410f, -0.475450281747155870f, 0.879651410178071580f, + -0.475618961535103300f, + 0.879560195213827890f, -0.475787623835901120f, 0.879468947910670210f, + -0.475956268643348060f, + 0.879377668271953290f, -0.476124895951243580f, 0.879286356301033250f, + -0.476293505753387690f, + 0.879195012001267480f, -0.476462098043581190f, 0.879103635376014330f, + -0.476630672815625320f, + 0.879012226428633530f, -0.476799230063322090f, 0.878920785162485840f, + -0.476967769780474170f, + 0.878829311580933360f, -0.477136291960884810f, 0.878737805687339390f, + -0.477304796598357890f, + 0.878646267485068130f, -0.477473283686698060f, 0.878554696977485450f, + -0.477641753219710470f, + 0.878463094167957870f, -0.477810205191200990f, 0.878371459059853480f, + -0.477978639594976160f, + 0.878279791656541580f, -0.478147056424843010f, 0.878188091961392250f, + -0.478315455674609480f, + 0.878096359977777130f, -0.478483837338083970f, 0.878004595709069080f, + -0.478652201409075500f, + 0.877912799158641840f, -0.478820547881393890f, 0.877820970329870500f, + -0.478988876748849490f, + 0.877729109226131570f, -0.479157188005253310f, 0.877637215850802230f, + -0.479325481644417070f, + 0.877545290207261350f, -0.479493757660153010f, 0.877453332298888560f, + -0.479662016046274180f, + 0.877361342129065140f, -0.479830256796594190f, 0.877269319701173170f, + -0.479998479904927280f, + 0.877177265018595940f, -0.480166685365088390f, 0.877085178084718420f, + -0.480334873170893020f, + 0.876993058902925890f, -0.480503043316157510f, 0.876900907476605650f, + -0.480671195794698640f, + 0.876808723809145650f, -0.480839330600333960f, 0.876716507903935400f, + -0.481007447726881590f, + 0.876624259764365310f, -0.481175547168160300f, 0.876531979393827100f, + -0.481343628917989710f, + 0.876439666795713610f, -0.481511692970189860f, 0.876347321973419020f, + -0.481679739318581490f, + 0.876254944930338510f, -0.481847767956986030f, 0.876162535669868460f, + -0.482015778879225590f, + 0.876070094195406600f, -0.482183772079122720f, 0.875977620510351770f, + -0.482351747550500980f, + 0.875885114618103810f, -0.482519705287184350f, 0.875792576522063880f, + -0.482687645282997460f, + 0.875700006225634600f, -0.482855567531765670f, 0.875607403732219350f, + -0.483023472027314880f, + 0.875514769045222850f, -0.483191358763471860f, 0.875422102168050940f, + -0.483359227734063810f, + 0.875329403104110890f, -0.483527078932918740f, 0.875236671856810870f, + -0.483694912353865140f, + 0.875143908429560360f, -0.483862727990732270f, 0.875051112825769970f, + -0.484030525837350010f, + 0.874958285048851650f, -0.484198305887549030f, 0.874865425102218320f, + -0.484366068135160420f, + 0.874772532989284150f, -0.484533812574016180f, 0.874679608713464510f, + -0.484701539197948670f, + 0.874586652278176110f, -0.484869248000791060f, 0.874493663686836560f, + -0.485036938976377290f, + 0.874400642942864790f, -0.485204612118541820f, 0.874307590049680950f, + -0.485372267421119770f, + 0.874214505010706300f, -0.485539904877946960f, 0.874121387829363330f, + -0.485707524482859750f, + 0.874028238509075740f, -0.485875126229695250f, 0.873935057053268240f, + -0.486042710112291330f, + 0.873841843465366860f, -0.486210276124486420f, 0.873748597748798870f, + -0.486377824260119440f, + 0.873655319906992630f, -0.486545354513030270f, 0.873562009943377850f, + -0.486712866877059170f, + 0.873468667861384880f, -0.486880361346047340f, 0.873375293664446000f, + -0.487047837913836380f, + 0.873281887355994210f, -0.487215296574268760f, 0.873188448939463790f, + -0.487382737321187360f, + 0.873094978418290090f, -0.487550160148436000f, 0.873001475795909920f, + -0.487717565049858800f, + 0.872907941075761080f, -0.487884952019301040f, 0.872814374261282390f, + -0.488052321050608250f, + 0.872720775355914300f, -0.488219672137626790f, 0.872627144363097960f, + -0.488387005274203530f, + 0.872533481286276170f, -0.488554320454186180f, 0.872439786128892280f, + -0.488721617671423080f, + 0.872346058894391540f, -0.488888896919763170f, 0.872252299586219860f, + -0.489056158193056030f, + 0.872158508207824480f, -0.489223401485151980f, 0.872064684762653860f, + -0.489390626789901920f, + 0.871970829254157810f, -0.489557834101157440f, 0.871876941685786890f, + -0.489725023412770910f, + 0.871783022060993120f, -0.489892194718595190f, 0.871689070383229740f, + -0.490059348012483850f, + 0.871595086655950980f, -0.490226483288291160f, 0.871501070882612530f, + -0.490393600539871970f, + 0.871407023066670950f, -0.490560699761082020f, 0.871312943211584030f, + -0.490727780945777400f, + 0.871218831320811020f, -0.490894844087815090f, 0.871124687397811900f, + -0.491061889181052650f, + 0.871030511446048260f, -0.491228916219348280f, 0.870936303468982760f, + -0.491395925196560780f, + 0.870842063470078980f, -0.491562916106549900f, 0.870747791452801790f, + -0.491729888943175760f, + 0.870653487420617430f, -0.491896843700299290f, 0.870559151376993250f, + -0.492063780371782000f, + 0.870464783325397670f, -0.492230698951486020f, 0.870370383269300270f, + -0.492397599433274380f, + 0.870275951212171940f, -0.492564481811010590f, 0.870181487157484560f, + -0.492731346078558840f, + 0.870086991108711460f, -0.492898192229784040f, 0.869992463069326870f, + -0.493065020258551700f, + 0.869897903042806340f, -0.493231830158727900f, 0.869803311032626650f, + -0.493398621924179770f, + 0.869708687042265670f, -0.493565395548774770f, 0.869614031075202300f, + -0.493732151026381020f, + 0.869519343134916860f, -0.493898888350867480f, 0.869424623224890890f, + -0.494065607516103570f, + 0.869329871348606840f, -0.494232308515959670f, 0.869235087509548370f, + -0.494398991344306650f, + 0.869140271711200560f, -0.494565655995015950f, 0.869045423957049530f, + -0.494732302461959870f, + 0.868950544250582380f, -0.494898930739011260f, 0.868855632595287860f, + -0.495065540820043560f, + 0.868760688994655310f, -0.495232132698931180f, 0.868665713452175690f, + -0.495398706369549020f, + 0.868570705971340900f, -0.495565261825772540f, 0.868475666555644120f, + -0.495731799061477960f, + 0.868380595208579800f, -0.495898318070542190f, 0.868285491933643350f, + -0.496064818846842890f, + 0.868190356734331310f, -0.496231301384258250f, 0.868095189614141670f, + -0.496397765676667160f, + 0.867999990576573510f, -0.496564211717949290f, 0.867904759625126920f, + -0.496730639501984760f, + 0.867809496763303320f, -0.496897049022654470f, 0.867714201994605140f, + -0.497063440273840250f, + 0.867618875322536230f, -0.497229813249424220f, 0.867523516750601460f, + -0.497396167943289280f, + 0.867428126282306920f, -0.497562504349319150f, 0.867332703921159800f, + -0.497728822461397940f, + 0.867237249670668400f, -0.497895122273410870f, 0.867141763534342470f, + -0.498061403779243410f, + 0.867046245515692650f, -0.498227666972781870f, 0.866950695618230900f, + -0.498393911847913210f, + 0.866855113845470430f, -0.498560138398525140f, 0.866759500200925400f, + -0.498726346618505900f, + 0.866663854688111130f, -0.498892536501744590f, 0.866568177310544470f, + -0.499058708042130870f, + 0.866472468071743050f, -0.499224861233555080f, 0.866376726975225830f, + -0.499390996069908170f, + 0.866280954024512990f, -0.499557112545081840f, 0.866185149223125840f, + -0.499723210652968540f, + 0.866089312574586770f, -0.499889290387461330f, 0.865993444082419520f, + -0.500055351742453860f, + 0.865897543750148820f, -0.500221394711840680f, 0.865801611581300760f, + -0.500387419289516580f, + 0.865705647579402380f, -0.500553425469377420f, 0.865609651747981990f, + -0.500719413245319880f, + 0.865513624090569090f, -0.500885382611240710f, 0.865417564610694410f, + -0.501051333561038040f, + 0.865321473311889800f, -0.501217266088609950f, 0.865225350197688200f, + -0.501383180187855770f, + 0.865129195271623800f, -0.501549075852675390f, 0.865033008537231860f, + -0.501714953076969120f, + 0.864936789998049020f, -0.501880811854638290f, 0.864840539657612870f, + -0.502046652179584660f, + 0.864744257519462380f, -0.502212474045710790f, 0.864647943587137480f, + -0.502378277446919760f, + 0.864551597864179340f, -0.502544062377115690f, 0.864455220354130360f, + -0.502709828830202990f, + 0.864358811060534030f, -0.502875576800086990f, 0.864262369986934950f, + -0.503041306280673450f, + 0.864165897136879300f, -0.503207017265868920f, 0.864069392513913790f, + -0.503372709749581040f, + 0.863972856121586810f, -0.503538383725717580f, 0.863876287963447510f, + -0.503704039188187070f, + 0.863779688043046720f, -0.503869676130898950f, 0.863683056363935830f, + -0.504035294547763190f, + 0.863586392929668100f, -0.504200894432690340f, 0.863489697743797140f, + -0.504366475779592040f, + 0.863392970809878420f, -0.504532038582380270f, 0.863296212131468230f, + -0.504697582834967570f, + 0.863199421712124160f, -0.504863108531267590f, 0.863102599555404910f, + -0.505028615665194080f, + 0.863005745664870320f, -0.505194104230662240f, 0.862908860044081400f, + -0.505359574221587280f, + 0.862811942696600330f, -0.505525025631885390f, 0.862714993625990690f, + -0.505690458455473450f, + 0.862618012835816740f, -0.505855872686268860f, 0.862521000329644520f, + -0.506021268318189720f, + 0.862423956111040610f, -0.506186645345155230f, 0.862326880183573060f, + -0.506352003761084800f, + 0.862229772550811240f, -0.506517343559898530f, 0.862132633216325380f, + -0.506682664735517600f, + 0.862035462183687210f, -0.506847967281863210f, 0.861938259456469290f, + -0.507013251192858230f, + 0.861841025038245330f, -0.507178516462425180f, 0.861743758932590700f, + -0.507343763084487920f, + 0.861646461143081300f, -0.507508991052970870f, 0.861549131673294720f, + -0.507674200361798890f, + 0.861451770526809320f, -0.507839391004897720f, 0.861354377707204910f, + -0.508004562976194010f, + 0.861256953218062170f, -0.508169716269614600f, 0.861159497062963350f, + -0.508334850879087360f, + 0.861062009245491480f, -0.508499966798540930f, 0.860964489769231010f, + -0.508665064021904030f, + 0.860866938637767310f, -0.508830142543106990f, 0.860769355854687170f, + -0.508995202356080090f, + 0.860671741423578380f, -0.509160243454754640f, 0.860574095348029980f, + -0.509325265833062480f, + 0.860476417631632070f, -0.509490269484936360f, 0.860378708277976130f, + -0.509655254404309250f, + 0.860280967290654510f, -0.509820220585115450f, 0.860183194673260990f, + -0.509985168021289460f, + 0.860085390429390140f, -0.510150096706766810f, 0.859987554562638200f, + -0.510315006635483240f, + 0.859889687076602290f, -0.510479897801375700f, 0.859791787974880650f, + -0.510644770198381610f, + 0.859693857261072610f, -0.510809623820439040f, 0.859595894938779080f, + -0.510974458661486830f, + 0.859497901011601730f, -0.511139274715464390f, 0.859399875483143450f, + -0.511304071976312000f, + 0.859301818357008470f, -0.511468850437970300f, 0.859203729636801920f, + -0.511633610094381240f, + 0.859105609326130450f, -0.511798350939486890f, 0.859007457428601520f, + -0.511963072967230200f, + 0.858909273947823900f, -0.512127776171554690f, 0.858811058887407610f, + -0.512292460546404870f, + 0.858712812250963520f, -0.512457126085725690f, 0.858614534042104190f, + -0.512621772783462990f, + 0.858516224264442740f, -0.512786400633562960f, 0.858417882921593930f, + -0.512951009629972980f, + 0.858319510017173440f, -0.513115599766640560f, 0.858221105554798250f, + -0.513280171037514220f, + 0.858122669538086140f, -0.513444723436543460f, 0.858024201970656540f, + -0.513609256957677780f, + 0.857925702856129790f, -0.513773771594868030f, 0.857827172198127430f, + -0.513938267342065380f, + 0.857728610000272120f, -0.514102744193221660f, 0.857630016266187620f, + -0.514267202142289710f, + 0.857531390999499150f, -0.514431641183222820f, 0.857432734203832700f, + -0.514596061309975040f, + 0.857334045882815590f, -0.514760462516501200f, 0.857235326040076460f, + -0.514924844796756490f, + 0.857136574679244980f, -0.515089208144697160f, 0.857037791803951680f, + -0.515253552554280180f, + 0.856938977417828760f, -0.515417878019462930f, 0.856840131524509220f, + -0.515582184534203790f, + 0.856741254127627470f, -0.515746472092461380f, 0.856642345230818840f, + -0.515910740688195650f, + 0.856543404837719960f, -0.516074990315366630f, 0.856444432951968590f, + -0.516239220967935510f, + 0.856345429577203610f, -0.516403432639863990f, 0.856246394717065210f, + -0.516567625325114350f, + 0.856147328375194470f, -0.516731799017649870f, 0.856048230555233940f, + -0.516895953711434150f, + 0.855949101260826910f, -0.517060089400431910f, 0.855849940495618240f, + -0.517224206078608310f, + 0.855750748263253920f, -0.517388303739929060f, 0.855651524567380690f, + -0.517552382378360880f, + 0.855552269411646860f, -0.517716441987871150f, 0.855452982799701830f, + -0.517880482562427690f, + 0.855353664735196030f, -0.518044504095999340f, 0.855254315221780970f, + -0.518208506582555460f, + 0.855154934263109620f, -0.518372490016066110f, 0.855055521862835950f, + -0.518536454390502220f, + 0.854956078024614930f, -0.518700399699834950f, 0.854856602752102850f, + -0.518864325938036890f, + 0.854757096048957220f, -0.519028233099080860f, 0.854657557918836460f, + -0.519192121176940250f, + 0.854557988365400530f, -0.519355990165589640f, 0.854458387392310170f, + -0.519519840059003760f, + 0.854358755003227440f, -0.519683670851158410f, 0.854259091201815530f, + -0.519847482536030190f, + 0.854159395991738850f, -0.520011275107596040f, 0.854059669376662780f, + -0.520175048559833760f, + 0.853959911360254180f, -0.520338802886721960f, 0.853860121946180770f, + -0.520502538082239670f, + 0.853760301138111410f, -0.520666254140367160f, 0.853660448939716380f, + -0.520829951055084670f, + 0.853560565354666840f, -0.520993628820373920f, 0.853460650386635320f, + -0.521157287430216610f, + 0.853360704039295430f, -0.521320926878595660f, 0.853260726316321880f, + -0.521484547159494330f, + 0.853160717221390420f, -0.521648148266897090f, 0.853060676758178320f, + -0.521811730194788550f, + 0.852960604930363630f, -0.521975292937154390f, 0.852860501741625750f, + -0.522138836487980760f, + 0.852760367195645300f, -0.522302360841254590f, 0.852660201296103760f, + -0.522465865990963780f, + 0.852560004046684080f, -0.522629351931096610f, 0.852459775451070100f, + -0.522792818655642090f, + 0.852359515512947090f, -0.522956266158590140f, 0.852259224236001090f, + -0.523119694433931250f, + 0.852158901623919830f, -0.523283103475656430f, 0.852058547680391690f, + -0.523446493277757830f, + 0.851958162409106380f, -0.523609863834227920f, 0.851857745813754840f, + -0.523773215139060170f, + 0.851757297898029120f, -0.523936547186248600f, 0.851656818665622370f, + -0.524099859969787700f, + 0.851556308120228980f, -0.524263153483673360f, 0.851455766265544310f, + -0.524426427721901400f, + 0.851355193105265200f, -0.524589682678468950f, 0.851254588643089120f, + -0.524752918347373360f, + 0.851153952882715340f, -0.524916134722613000f, 0.851053285827843790f, + -0.525079331798186780f, + 0.850952587482175730f, -0.525242509568094710f, 0.850851857849413530f, + -0.525405668026336930f, + 0.850751096933260790f, -0.525568807166914680f, 0.850650304737422090f, + -0.525731926983829760f, + 0.850549481265603480f, -0.525895027471084630f, 0.850448626521511760f, + -0.526058108622682760f, + 0.850347740508854980f, -0.526221170432628060f, 0.850246823231342710f, + -0.526384212894925100f, + 0.850145874692685210f, -0.526547236003579440f, 0.850044894896594180f, + -0.526710239752597010f, + 0.849943883846782210f, -0.526873224135984590f, 0.849842841546963320f, + -0.527036189147750080f, + 0.849741768000852550f, -0.527199134781901280f, 0.849640663212165910f, + -0.527362061032447540f, + 0.849539527184620890f, -0.527524967893398200f, 0.849438359921936060f, + -0.527687855358763720f, + 0.849337161427830780f, -0.527850723422555230f, 0.849235931706025960f, + -0.528013572078784630f, + 0.849134670760243630f, -0.528176401321464370f, 0.849033378594206800f, + -0.528339211144607690f, + 0.848932055211639610f, -0.528502001542228480f, 0.848830700616267530f, + -0.528664772508341320f, + 0.848729314811817130f, -0.528827524036961870f, 0.848627897802015860f, + -0.528990256122106040f, + 0.848526449590592650f, -0.529152968757790610f, 0.848424970181277600f, + -0.529315661938033260f, + 0.848323459577801640f, -0.529478335656851980f, 0.848221917783896990f, + -0.529640989908265910f, + 0.848120344803297230f, -0.529803624686294610f, 0.848018740639736810f, + -0.529966239984958620f, + 0.847917105296951410f, -0.530128835798278960f, 0.847815438778677930f, + -0.530291412120277310f, + 0.847713741088654380f, -0.530453968944976320f, 0.847612012230619660f, + -0.530616506266399330f, + 0.847510252208314330f, -0.530779024078570140f, 0.847408461025479730f, + -0.530941522375513620f, + 0.847306638685858320f, -0.531104001151255000f, 0.847204785193194090f, + -0.531266460399820390f, + 0.847102900551231500f, -0.531428900115236800f, 0.847000984763716880f, + -0.531591320291531670f, + 0.846899037834397240f, -0.531753720922733320f, 0.846797059767020910f, + -0.531916102002870650f, + 0.846695050565337450f, -0.532078463525973540f, 0.846593010233097190f, + -0.532240805486072220f, + 0.846490938774052130f, -0.532403127877197900f, 0.846388836191954930f, + -0.532565430693382580f, + 0.846286702490559710f, -0.532727713928658810f, 0.846184537673621560f, + -0.532889977577059800f, + 0.846082341744897050f, -0.533052221632619450f, 0.845980114708143270f, + -0.533214446089372960f, + 0.845877856567119000f, -0.533376650941355330f, 0.845775567325584010f, + -0.533538836182603120f, + 0.845673246987299070f, -0.533701001807152960f, 0.845570895556026270f, + -0.533863147809042650f, + 0.845468513035528830f, -0.534025274182310380f, 0.845366099429570970f, + -0.534187380920995380f, + 0.845263654741918220f, -0.534349468019137520f, 0.845161178976337140f, + -0.534511535470777120f, + 0.845058672136595470f, -0.534673583269955510f, 0.844956134226462210f, + -0.534835611410714560f, + 0.844853565249707120f, -0.534997619887097150f, 0.844750965210101510f, + -0.535159608693146600f, + 0.844648334111417820f, -0.535321577822907120f, 0.844545671957429240f, + -0.535483527270423370f, + 0.844442978751910660f, -0.535645457029741090f, 0.844340254498637590f, + -0.535807367094906390f, + 0.844237499201387020f, -0.535969257459966710f, 0.844134712863936930f, + -0.536131128118969460f, + 0.844031895490066410f, -0.536292979065963180f, 0.843929047083555870f, + -0.536454810294997090f, + 0.843826167648186740f, -0.536616621800121040f, 0.843723257187741660f, + -0.536778413575385920f, + 0.843620315706004150f, -0.536940185614842910f, 0.843517343206759200f, + -0.537101937912544130f, + 0.843414339693792760f, -0.537263670462542530f, 0.843311305170892140f, + -0.537425383258891550f, + 0.843208239641845440f, -0.537587076295645390f, 0.843105143110442160f, + -0.537748749566859360f, + 0.843002015580472940f, -0.537910403066588880f, 0.842898857055729310f, + -0.538072036788890600f, + 0.842795667540004120f, -0.538233650727821700f, 0.842692447037091670f, + -0.538395244877439950f, + 0.842589195550786710f, -0.538556819231804100f, 0.842485913084885630f, + -0.538718373784973560f, + 0.842382599643185850f, -0.538879908531008420f, 0.842279255229485990f, + -0.539041423463969440f, + 0.842175879847585570f, -0.539202918577918240f, 0.842072473501285560f, + -0.539364393866917040f, + 0.841969036194387680f, -0.539525849325028890f, 0.841865567930695340f, + -0.539687284946317570f, + 0.841762068714012490f, -0.539848700724847590f, 0.841658538548144760f, + -0.540010096654684020f, + 0.841554977436898440f, -0.540171472729892850f, 0.841451385384081260f, + -0.540332828944540710f, + 0.841347762393501950f, -0.540494165292695230f, 0.841244108468970580f, + -0.540655481768424150f, + 0.841140423614298080f, -0.540816778365796670f, 0.841036707833296650f, + -0.540978055078882080f, + 0.840932961129779780f, -0.541139311901750800f, 0.840829183507561640f, + -0.541300548828474120f, + 0.840725374970458070f, -0.541461765853123440f, 0.840621535522285690f, + -0.541622962969771530f, + 0.840517665166862550f, -0.541784140172491550f, 0.840413763908007480f, + -0.541945297455357360f, + 0.840309831749540770f, -0.542106434812443920f, 0.840205868695283580f, + -0.542267552237826520f, + 0.840101874749058400f, -0.542428649725581250f, 0.839997849914688840f, + -0.542589727269785270f, + 0.839893794195999520f, -0.542750784864515890f, 0.839789707596816370f, + -0.542911822503851730f, + 0.839685590120966110f, -0.543072840181871740f, 0.839581441772277120f, + -0.543233837892655890f, + 0.839477262554578550f, -0.543394815630284800f, 0.839373052471700690f, + -0.543555773388839540f, + 0.839268811527475230f, -0.543716711162402280f, 0.839164539725734680f, + -0.543877628945055980f, + 0.839060237070312740f, -0.544038526730883820f, 0.838955903565044460f, + -0.544199404513970310f, + 0.838851539213765760f, -0.544360262288400400f, 0.838747144020313920f, + -0.544521100048259600f, + 0.838642717988527300f, -0.544681917787634530f, 0.838538261122245280f, + -0.544842715500612360f, + 0.838433773425308340f, -0.545003493181281160f, 0.838329254901558300f, + -0.545164250823729320f, + 0.838224705554838080f, -0.545324988422046460f, 0.838120125388991500f, + -0.545485705970322530f, + 0.838015514407863820f, -0.545646403462648590f, 0.837910872615301170f, + -0.545807080893116140f, + 0.837806200015150940f, -0.545967738255817570f, 0.837701496611261700f, + -0.546128375544845950f, + 0.837596762407483040f, -0.546288992754295210f, 0.837491997407665890f, + -0.546449589878259650f, + 0.837387201615661940f, -0.546610166910834860f, 0.837282375035324320f, + -0.546770723846116800f, + 0.837177517670507300f, -0.546931260678202190f, 0.837072629525066000f, + -0.547091777401188530f, + 0.836967710602857020f, -0.547252274009174090f, 0.836862760907737920f, + -0.547412750496257930f, + 0.836757780443567190f, -0.547573206856539760f, 0.836652769214204950f, + -0.547733643084120090f, + 0.836547727223512010f, -0.547894059173100190f, 0.836442654475350380f, + -0.548054455117581880f, + 0.836337550973583530f, -0.548214830911667780f, 0.836232416722075600f, + -0.548375186549461600f, + 0.836127251724692270f, -0.548535522025067390f, 0.836022055985299880f, + -0.548695837332590090f, + 0.835916829507766360f, -0.548856132466135290f, 0.835811572295960700f, + -0.549016407419809390f, + 0.835706284353752600f, -0.549176662187719660f, 0.835600965685013410f, + -0.549336896763974010f, + 0.835495616293615350f, -0.549497111142680960f, 0.835390236183431890f, + -0.549657305317949870f, + 0.835284825358337370f, -0.549817479283890910f, 0.835179383822207690f, + -0.549977633034614890f, + 0.835073911578919410f, -0.550137766564233630f, 0.834968408632350450f, + -0.550297879866859190f, + 0.834862874986380010f, -0.550457972936604810f, 0.834757310644888230f, + -0.550618045767584330f, + 0.834651715611756440f, -0.550778098353912120f, 0.834546089890866870f, + -0.550938130689703880f, + 0.834440433486103190f, -0.551098142769075430f, 0.834334746401350080f, + -0.551258134586143590f, + 0.834229028640493420f, -0.551418106135026060f, 0.834123280207420100f, + -0.551578057409841000f, + 0.834017501106018130f, -0.551737988404707340f, 0.833911691340176840f, + -0.551897899113745210f, + 0.833805850913786340f, -0.552057789531074980f, 0.833699979830738290f, + -0.552217659650817930f, + 0.833594078094925140f, -0.552377509467096070f, 0.833488145710240770f, + -0.552537338974032120f, + 0.833382182680579730f, -0.552697148165749770f, 0.833276189009838240f, + -0.552856937036373290f, + 0.833170164701913190f, -0.553016705580027470f, 0.833064109760702890f, + -0.553176453790838350f, + 0.832958024190106670f, -0.553336181662932300f, 0.832851907994025090f, + -0.553495889190436570f, + 0.832745761176359460f, -0.553655576367479310f, 0.832639583741012770f, + -0.553815243188189090f, + 0.832533375691888680f, -0.553974889646695500f, 0.832427137032892280f, + -0.554134515737128910f, + 0.832320867767929680f, -0.554294121453620000f, 0.832214567900907980f, + -0.554453706790300930f, + 0.832108237435735590f, -0.554613271741304040f, 0.832001876376321950f, + -0.554772816300762470f, + 0.831895484726577590f, -0.554932340462810370f, 0.831789062490414400f, + -0.555091844221582420f, + 0.831682609671745120f, -0.555251327571213980f, 0.831576126274483740f, + -0.555410790505841630f, + 0.831469612302545240f, -0.555570233019602180f, 0.831363067759845920f, + -0.555729655106633410f, + 0.831256492650303210f, -0.555889056761073810f, 0.831149886977835540f, + -0.556048437977062600f, + 0.831043250746362320f, -0.556207798748739930f, 0.830936583959804410f, + -0.556367139070246370f, + 0.830829886622083570f, -0.556526458935723610f, 0.830723158737122880f, + -0.556685758339313890f, + 0.830616400308846310f, -0.556845037275160100f, 0.830509611341179070f, + -0.557004295737405950f, + 0.830402791838047550f, -0.557163533720196220f, 0.830295941803379070f, + -0.557322751217676160f, + 0.830189061241102370f, -0.557481948223991550f, 0.830082150155146970f, + -0.557641124733289420f, + 0.829975208549443950f, -0.557800280739716990f, 0.829868236427924840f, + -0.557959416237422960f, + 0.829761233794523050f, -0.558118531220556100f, 0.829654200653172640f, + -0.558277625683266330f, + 0.829547137007808910f, -0.558436699619704100f, 0.829440042862368170f, + -0.558595753024020760f, + 0.829332918220788250f, -0.558754785890368310f, 0.829225763087007570f, + -0.558913798212899770f, + 0.829118577464965980f, -0.559072789985768480f, 0.829011361358604430f, + -0.559231761203128900f, + 0.828904114771864870f, -0.559390711859136140f, 0.828796837708690610f, + -0.559549641947945760f, + 0.828689530173025820f, -0.559708551463714680f, 0.828582192168815790f, + -0.559867440400600210f, + 0.828474823700007130f, -0.560026308752760380f, 0.828367424770547480f, + -0.560185156514354080f, + 0.828259995384385660f, -0.560343983679540860f, 0.828152535545471410f, + -0.560502790242481060f, + 0.828045045257755800f, -0.560661576197336030f, 0.827937524525190870f, + -0.560820341538267430f, + 0.827829973351729920f, -0.560979086259438150f, 0.827722391741327220f, + -0.561137810355011420f, + 0.827614779697938400f, -0.561296513819151470f, 0.827507137225519830f, + -0.561455196646023280f, + 0.827399464328029470f, -0.561613858829792420f, 0.827291761009425810f, + -0.561772500364625340f, + 0.827184027273669130f, -0.561931121244689470f, 0.827076263124720270f, + -0.562089721464152480f, + 0.826968468566541600f, -0.562248301017183150f, 0.826860643603096190f, + -0.562406859897951140f, + 0.826752788238348520f, -0.562565398100626560f, 0.826644902476264320f, + -0.562723915619380400f, + 0.826536986320809960f, -0.562882412448384440f, 0.826429039775953500f, + -0.563040888581811230f, + 0.826321062845663530f, -0.563199344013834090f, 0.826213055533910220f, + -0.563357778738627020f, + 0.826105017844664610f, -0.563516192750364800f, 0.825996949781899080f, + -0.563674586043223070f, + 0.825888851349586780f, -0.563832958611378170f, 0.825780722551702430f, + -0.563991310449006970f, + 0.825672563392221390f, -0.564149641550287680f, 0.825564373875120490f, + -0.564307951909398640f, + 0.825456154004377550f, -0.564466241520519500f, 0.825347903783971380f, + -0.564624510377830120f, + 0.825239623217882250f, -0.564782758475511400f, 0.825131312310091070f, + -0.564940985807745210f, + 0.825022971064580220f, -0.565099192368713980f, 0.824914599485333190f, + -0.565257378152600800f, + 0.824806197576334330f, -0.565415543153589660f, 0.824697765341569470f, + -0.565573687365865330f, + 0.824589302785025290f, -0.565731810783613120f, 0.824480809910689500f, + -0.565889913401019570f, + 0.824372286722551250f, -0.566047995212271450f, 0.824263733224600560f, + -0.566206056211556730f, + 0.824155149420828570f, -0.566364096393063840f, 0.824046535315227760f, + -0.566522115750982100f, + 0.823937890911791370f, -0.566680114279501600f, 0.823829216214513990f, + -0.566838091972813320f, + 0.823720511227391430f, -0.566996048825108680f, 0.823611775954420260f, + -0.567153984830580100f, + 0.823503010399598500f, -0.567311899983420800f, 0.823394214566925080f, + -0.567469794277824510f, + 0.823285388460400110f, -0.567627667707986230f, 0.823176532084024860f, + -0.567785520268101140f, + 0.823067645441801670f, -0.567943351952365560f, 0.822958728537734000f, + -0.568101162754976460f, + 0.822849781375826430f, -0.568258952670131490f, 0.822740803960084420f, + -0.568416721692029280f, + 0.822631796294514990f, -0.568574469814869140f, 0.822522758383125940f, + -0.568732197032851050f, + 0.822413690229926390f, -0.568889903340175860f, 0.822304591838926350f, + -0.569047588731045110f, + 0.822195463214137170f, -0.569205253199661200f, 0.822086304359571090f, + -0.569362896740227220f, + 0.821977115279241550f, -0.569520519346947140f, 0.821867895977163250f, + -0.569678121014025600f, + 0.821758646457351750f, -0.569835701735668000f, 0.821649366723823940f, + -0.569993261506080540f, + 0.821540056780597610f, -0.570150800319470300f, 0.821430716631691870f, + -0.570308318170044900f, + 0.821321346281126740f, -0.570465815052012990f, 0.821211945732923550f, + -0.570623290959583750f, + 0.821102514991104650f, -0.570780745886967260f, 0.820993054059693580f, + -0.570938179828374360f, + 0.820883562942714580f, -0.571095592778016690f, 0.820774041644193650f, + -0.571252984730106660f, + 0.820664490168157460f, -0.571410355678857230f, 0.820554908518633890f, + -0.571567705618482580f, + 0.820445296699652050f, -0.571725034543197120f, 0.820335654715241840f, + -0.571882342447216590f, + 0.820225982569434690f, -0.572039629324757050f, 0.820116280266262820f, + -0.572196895170035580f, + 0.820006547809759680f, -0.572354139977269920f, 0.819896785203959810f, + -0.572511363740678790f, + 0.819786992452898990f, -0.572668566454481160f, 0.819677169560613870f, + -0.572825748112897550f, + 0.819567316531142230f, -0.572982908710148560f, 0.819457433368523280f, + -0.573140048240455950f, + 0.819347520076796900f, -0.573297166698042200f, 0.819237576660004520f, + -0.573454264077130400f, + 0.819127603122188240f, -0.573611340371944610f, 0.819017599467391500f, + -0.573768395576709560f, + 0.818907565699658950f, -0.573925429685650750f, 0.818797501823036010f, + -0.574082442692994470f, + 0.818687407841569680f, -0.574239434592967890f, 0.818577283759307610f, + -0.574396405379798750f, + 0.818467129580298660f, -0.574553355047715760f, 0.818356945308593150f, + -0.574710283590948330f, + 0.818246730948242070f, -0.574867191003726740f, 0.818136486503297730f, + -0.575024077280281710f, + 0.818026211977813440f, -0.575180942414845080f, 0.817915907375843850f, + -0.575337786401649450f, + 0.817805572701444270f, -0.575494609234928120f, 0.817695207958671680f, + -0.575651410908915140f, + 0.817584813151583710f, -0.575808191417845340f, 0.817474388284239240f, + -0.575964950755954220f, + 0.817363933360698460f, -0.576121688917478280f, 0.817253448385022340f, + -0.576278405896654910f, + 0.817142933361272970f, -0.576435101687721830f, 0.817032388293513880f, + -0.576591776284917760f, + 0.816921813185809480f, -0.576748429682482410f, 0.816811208042225290f, + -0.576905061874655960f, + 0.816700572866827850f, -0.577061672855679440f, 0.816589907663684890f, + -0.577218262619794920f, + 0.816479212436865390f, -0.577374831161244880f, 0.816368487190439200f, + -0.577531378474272720f, + 0.816257731928477390f, -0.577687904553122800f, 0.816146946655052270f, + -0.577844409392039850f, + 0.816036131374236810f, -0.578000892985269910f, 0.815925286090105510f, + -0.578157355327059360f, + 0.815814410806733780f, -0.578313796411655590f, 0.815703505528198260f, + -0.578470216233306630f, + 0.815592570258576790f, -0.578626614786261430f, 0.815481605001947770f, + -0.578782992064769690f, + 0.815370609762391290f, -0.578939348063081780f, 0.815259584543988280f, + -0.579095682775449090f, + 0.815148529350820830f, -0.579251996196123550f, 0.815037444186972220f, + -0.579408288319357870f, + 0.814926329056526620f, -0.579564559139405630f, 0.814815183963569440f, + -0.579720808650521450f, + 0.814704008912187080f, -0.579877036846960350f, 0.814592803906467270f, + -0.580033243722978150f, + 0.814481568950498610f, -0.580189429272831680f, 0.814370304048371070f, + -0.580345593490778300f, + 0.814259009204175270f, -0.580501736371076490f, 0.814147684422003360f, + -0.580657857907985300f, + 0.814036329705948410f, -0.580813958095764530f, 0.813924945060104600f, + -0.580970036928674770f, + 0.813813530488567190f, -0.581126094400977620f, 0.813702085995432700f, + -0.581282130506935000f, + 0.813590611584798510f, -0.581438145240810170f, 0.813479107260763220f, + -0.581594138596866930f, + 0.813367573027426570f, -0.581750110569369650f, 0.813256008888889380f, + -0.581906061152583810f, + 0.813144414849253590f, -0.582061990340775440f, 0.813032790912622040f, + -0.582217898128211670f, + 0.812921137083098770f, -0.582373784509160110f, 0.812809453364789270f, + -0.582529649477889320f, + 0.812697739761799490f, -0.582685493028668460f, 0.812585996278237130f, + -0.582841315155767650f, + 0.812474222918210480f, -0.582997115853457700f, 0.812362419685829230f, + -0.583152895116010430f, + 0.812250586585203880f, -0.583308652937698290f, 0.812138723620446480f, + -0.583464389312794320f, + 0.812026830795669730f, -0.583620104235572760f, 0.811914908114987790f, + -0.583775797700308070f, + 0.811802955582515470f, -0.583931469701276180f, 0.811690973202369050f, + -0.584087120232753440f, + 0.811578960978665890f, -0.584242749289016980f, 0.811466918915524250f, + -0.584398356864344600f, + 0.811354847017063730f, -0.584553942953015330f, 0.811242745287404810f, + -0.584709507549308390f, + 0.811130613730669190f, -0.584865050647504490f, 0.811018452350979470f, + -0.585020572241884530f, + 0.810906261152459670f, -0.585176072326730410f, 0.810794040139234730f, + -0.585331550896324940f, + 0.810681789315430780f, -0.585487007944951340f, 0.810569508685174630f, + -0.585642443466894420f, + 0.810457198252594770f, -0.585797857456438860f, 0.810344858021820550f, + -0.585953249907870570f, + 0.810232487996982330f, -0.586108620815476430f, 0.810120088182211600f, + -0.586263970173543590f, + 0.810007658581641140f, -0.586419297976360500f, 0.809895199199404450f, + -0.586574604218216170f, + 0.809782710039636530f, -0.586729888893400390f, 0.809670191106473090f, + -0.586885151996203950f, + 0.809557642404051260f, -0.587040393520917970f, 0.809445063936509170f, + -0.587195613461834800f, + 0.809332455707985950f, -0.587350811813247660f, 0.809219817722621750f, + -0.587505988569450020f, + 0.809107149984558240f, -0.587661143724736660f, 0.808994452497937670f, + -0.587816277273402910f, + 0.808881725266903610f, -0.587971389209745010f, 0.808768968295600850f, + -0.588126479528059850f, + 0.808656181588174980f, -0.588281548222645220f, 0.808543365148773010f, + -0.588436595287799790f, + 0.808430518981542720f, -0.588591620717822890f, 0.808317643090633250f, + -0.588746624507014540f, + 0.808204737480194720f, -0.588901606649675720f, 0.808091802154378370f, + -0.589056567140108460f, + 0.807978837117336310f, -0.589211505972614960f, 0.807865842373222120f, + -0.589366423141498790f, + 0.807752817926190360f, -0.589521318641063940f, 0.807639763780396480f, + -0.589676192465615420f, + 0.807526679939997160f, -0.589831044609458790f, 0.807413566409150190f, + -0.589985875066900920f, + 0.807300423192014450f, -0.590140683832248820f, 0.807187250292749960f, + -0.590295470899810830f, + 0.807074047715517610f, -0.590450236263895810f, 0.806960815464479730f, + -0.590604979918813330f, + 0.806847553543799330f, -0.590759701858874160f, 0.806734261957640860f, + -0.590914402078389520f, + 0.806620940710169650f, -0.591069080571671400f, 0.806507589805552260f, + -0.591223737333032910f, + 0.806394209247956240f, -0.591378372356787580f, 0.806280799041550480f, + -0.591532985637249990f, + 0.806167359190504420f, -0.591687577168735430f, 0.806053889698989060f, + -0.591842146945560140f, + 0.805940390571176280f, -0.591996694962040990f, 0.805826861811239300f, + -0.592151221212495530f, + 0.805713303423352230f, -0.592305725691242290f, 0.805599715411690060f, + -0.592460208392600830f, + 0.805486097780429230f, -0.592614669310891130f, 0.805372450533747060f, + -0.592769108440434070f, + 0.805258773675822210f, -0.592923525775551300f, 0.805145067210834230f, + -0.593077921310565470f, + 0.805031331142963660f, -0.593232295039799800f, 0.804917565476392260f, + -0.593386646957578480f, + 0.804803770215302920f, -0.593540977058226390f, 0.804689945363879500f, + -0.593695285336069190f, + 0.804576090926307110f, -0.593849571785433630f, 0.804462206906771840f, + -0.594003836400646690f, + 0.804348293309460780f, -0.594158079176036800f, 0.804234350138562260f, + -0.594312300105932830f, + 0.804120377398265810f, -0.594466499184664430f, 0.804006375092761520f, + -0.594620676406562240f, + 0.803892343226241260f, -0.594774831765957580f, 0.803778281802897570f, + -0.594928965257182420f, + 0.803664190826924090f, -0.595083076874569960f, 0.803550070302515680f, + -0.595237166612453850f, + 0.803435920233868120f, -0.595391234465168730f, 0.803321740625178580f, + -0.595545280427049790f, + 0.803207531480644940f, -0.595699304492433360f, 0.803093292804466400f, + -0.595853306655656280f, + 0.802979024600843250f, -0.596007286911056530f, 0.802864726873976700f, + -0.596161245252972540f, + 0.802750399628069160f, -0.596315181675743710f, 0.802636042867324150f, + -0.596469096173710360f, + 0.802521656595946430f, -0.596622988741213220f, 0.802407240818141300f, + -0.596776859372594390f, + 0.802292795538115720f, -0.596930708062196500f, 0.802178320760077450f, + -0.597084534804362740f, + 0.802063816488235440f, -0.597238339593437420f, 0.801949282726799770f, + -0.597392122423765710f, + 0.801834719479981310f, -0.597545883289693160f, 0.801720126751992330f, + -0.597699622185566830f, + 0.801605504547046150f, -0.597853339105733910f, 0.801490852869356950f, + -0.598007034044542700f, + 0.801376171723140240f, -0.598160706996342270f, 0.801261461112612540f, + -0.598314357955482600f, + 0.801146721041991360f, -0.598467986916314310f, 0.801031951515495330f, + -0.598621593873188920f, + 0.800917152537344300f, -0.598775178820458720f, 0.800802324111759110f, + -0.598928741752476900f, + 0.800687466242961610f, -0.599082282663597310f, 0.800572578935174860f, + -0.599235801548174570f, + 0.800457662192622820f, -0.599389298400564540f, 0.800342716019530660f, + -0.599542773215123390f, + 0.800227740420124790f, -0.599696225986208310f, 0.800112735398632370f, + -0.599849656708177250f, + 0.799997700959281910f, -0.600003065375388940f, 0.799882637106302810f, + -0.600156451982203240f, + 0.799767543843925680f, -0.600309816522980430f, 0.799652421176382240f, + -0.600463158992081580f, + 0.799537269107905010f, -0.600616479383868970f, 0.799422087642728040f, + -0.600769777692705230f, + 0.799306876785086160f, -0.600923053912954090f, 0.799191636539215210f, + -0.601076308038980160f, + 0.799076366909352350f, -0.601229540065148500f, 0.798961067899735760f, + -0.601382749985825420f, + 0.798845739514604580f, -0.601535937795377730f, 0.798730381758199210f, + -0.601689103488172950f, + 0.798614994634760820f, -0.601842247058580030f, 0.798499578148532120f, + -0.601995368500968020f, + 0.798384132303756380f, -0.602148467809707210f, 0.798268657104678430f, + -0.602301544979168550f, + 0.798153152555543750f, -0.602454600003723750f, 0.798037618660599410f, + -0.602607632877745440f, + 0.797922055424093000f, -0.602760643595607220f, 0.797806462850273570f, + -0.602913632151683030f, + 0.797690840943391160f, -0.603066598540348160f, 0.797575189707696700f, + -0.603219542755978440f, + 0.797459509147442460f, -0.603372464792950260f, 0.797343799266881700f, + -0.603525364645641550f, + 0.797228060070268700f, -0.603678242308430370f, 0.797112291561858920f, + -0.603831097775695880f, + 0.796996493745908750f, -0.603983931041818020f, 0.796880666626675780f, + -0.604136742101177520f, + 0.796764810208418830f, -0.604289530948155960f, 0.796648924495397260f, + -0.604442297577135860f, + 0.796533009491872000f, -0.604595041982500360f, 0.796417065202104980f, + -0.604747764158633410f, + 0.796301091630359110f, -0.604900464099919820f, 0.796185088780898440f, + -0.605053141800745320f, + 0.796069056657987990f, -0.605205797255496500f, 0.795952995265893910f, + -0.605358430458560530f, + 0.795836904608883570f, -0.605511041404325550f, 0.795720784691225090f, + -0.605663630087180380f, + 0.795604635517188070f, -0.605816196501514970f, 0.795488457091042990f, + -0.605968740641719680f, + 0.795372249417061310f, -0.606121262502186120f, 0.795256012499515610f, + -0.606273762077306430f, + 0.795139746342679590f, -0.606426239361473550f, 0.795023450950828050f, + -0.606578694349081290f, + 0.794907126328237010f, -0.606731127034524480f, 0.794790772479183170f, + -0.606883537412198470f, + 0.794674389407944550f, -0.607035925476499650f, 0.794557977118800380f, + -0.607188291221825160f, + 0.794441535616030590f, -0.607340634642572930f, 0.794325064903916520f, + -0.607492955733141550f, + 0.794208564986740640f, -0.607645254487930830f, 0.794092035868785960f, + -0.607797530901341140f, + 0.793975477554337170f, -0.607949784967773630f, 0.793858890047679730f, + -0.608102016681630440f, + 0.793742273353100210f, -0.608254226037314490f, 0.793625627474886300f, + -0.608406413029229150f, + 0.793508952417326660f, -0.608558577651779450f, 0.793392248184711100f, + -0.608710719899370310f, + 0.793275514781330630f, -0.608862839766408200f, 0.793158752211477140f, + -0.609014937247299830f, + 0.793041960479443640f, -0.609167012336453210f, 0.792925139589524260f, + -0.609319065028276820f, + 0.792808289546014120f, -0.609471095317180240f, 0.792691410353209450f, + -0.609623103197573730f, + 0.792574502015407690f, -0.609775088663868430f, 0.792457564536907080f, + -0.609927051710476120f, + 0.792340597922007170f, -0.610078992331809620f, 0.792223602175008310f, + -0.610230910522282620f, + 0.792106577300212390f, -0.610382806276309480f, 0.791989523301921850f, + -0.610534679588305320f, + 0.791872440184440470f, -0.610686530452686280f, 0.791755327952073150f, + -0.610838358863869170f, + 0.791638186609125880f, -0.610990164816271660f, 0.791521016159905220f, + -0.611141948304312570f, + 0.791403816608719500f, -0.611293709322410890f, 0.791286587959877830f, + -0.611445447864987000f, + 0.791169330217690200f, -0.611597163926461910f, 0.791052043386467950f, + -0.611748857501257290f, + 0.790934727470523290f, -0.611900528583796070f, 0.790817382474169770f, + -0.612052177168501470f, + 0.790700008401721610f, -0.612203803249797950f, 0.790582605257494460f, + -0.612355406822110650f, + 0.790465173045804880f, -0.612506987879865570f, 0.790347711770970520f, + -0.612658546417489290f, + 0.790230221437310030f, -0.612810082429409710f, 0.790112702049143300f, + -0.612961595910055170f, + 0.789995153610791090f, -0.613113086853854910f, 0.789877576126575280f, + -0.613264555255239040f, + 0.789759969600819070f, -0.613416001108638590f, 0.789642334037846340f, + -0.613567424408485330f, + 0.789524669441982190f, -0.613718825149211720f, 0.789406975817552930f, + -0.613870203325251330f, + 0.789289253168885650f, -0.614021558931038380f, 0.789171501500308900f, + -0.614172891961007990f, + 0.789053720816151880f, -0.614324202409595950f, 0.788935911120745240f, + -0.614475490271239040f, + 0.788818072418420280f, -0.614626755540375050f, 0.788700204713509660f, + -0.614777998211442080f, + 0.788582308010347120f, -0.614929218278879590f, 0.788464382313267540f, + -0.615080415737127460f, + 0.788346427626606340f, -0.615231590580626820f, 0.788228443954700490f, + -0.615382742803819220f, + 0.788110431301888070f, -0.615533872401147320f, 0.787992389672507950f, + -0.615684979367054570f, + 0.787874319070900220f, -0.615836063695985090f, 0.787756219501406060f, + -0.615987125382383760f, + 0.787638090968367450f, -0.616138164420696910f, 0.787519933476127810f, + -0.616289180805370980f, + 0.787401747029031430f, -0.616440174530853650f, 0.787283531631423620f, + -0.616591145591593110f, + 0.787165287287651010f, -0.616742093982038720f, 0.787047014002060790f, + -0.616893019696640680f, + 0.786928711779001810f, -0.617043922729849760f, 0.786810380622823490f, + -0.617194803076117630f, + 0.786692020537876790f, -0.617345660729896830f, 0.786573631528513230f, + -0.617496495685640910f, + 0.786455213599085770f, -0.617647307937803870f, 0.786336766753948260f, + -0.617798097480841020f, + 0.786218290997455660f, -0.617948864309208150f, 0.786099786333963930f, + -0.618099608417362000f, + 0.785981252767830150f, -0.618250329799760250f, 0.785862690303412600f, + -0.618401028450860980f, + 0.785744098945070360f, -0.618551704365123740f, 0.785625478697163700f, + -0.618702357537008530f, + 0.785506829564053930f, -0.618852987960976320f, 0.785388151550103550f, + -0.619003595631488660f, + 0.785269444659675850f, -0.619154180543008410f, 0.785150708897135560f, + -0.619304742689998690f, + 0.785031944266848080f, -0.619455282066924020f, 0.784913150773180020f, + -0.619605798668249270f, + 0.784794328420499230f, -0.619756292488440660f, 0.784675477213174320f, + -0.619906763521964720f, + 0.784556597155575240f, -0.620057211763289100f, 0.784437688252072830f, + -0.620207637206882430f, + 0.784318750507038920f, -0.620358039847213720f, 0.784199783924846570f, + -0.620508419678753360f, + 0.784080788509869950f, -0.620658776695972140f, 0.783961764266484120f, + -0.620809110893341900f, + 0.783842711199065230f, -0.620959422265335180f, 0.783723629311990470f, + -0.621109710806425630f, + 0.783604518609638200f, -0.621259976511087550f, 0.783485379096387820f, + -0.621410219373796150f, + 0.783366210776619720f, -0.621560439389027160f, 0.783247013654715380f, + -0.621710636551257690f, + 0.783127787735057310f, -0.621860810854965360f, 0.783008533022029110f, + -0.622010962294628600f, + 0.782889249520015480f, -0.622161090864726820f, 0.782769937233402050f, + -0.622311196559740320f, + 0.782650596166575730f, -0.622461279374149970f, 0.782531226323924240f, + -0.622611339302437730f, + 0.782411827709836530f, -0.622761376339086350f, 0.782292400328702400f, + -0.622911390478579460f, + 0.782172944184913010f, -0.623061381715401260f, 0.782053459282860300f, + -0.623211350044037270f, + 0.781933945626937630f, -0.623361295458973230f, 0.781814403221538830f, + -0.623511217954696440f, + 0.781694832071059390f, -0.623661117525694530f, 0.781575232179895550f, + -0.623810994166456130f, + 0.781455603552444590f, -0.623960847871470660f, 0.781335946193104870f, + -0.624110678635228510f, + 0.781216260106276090f, -0.624260486452220650f, 0.781096545296358520f, + -0.624410271316939270f, + 0.780976801767753750f, -0.624560033223877210f, 0.780857029524864580f, + -0.624709772167528100f, + 0.780737228572094490f, -0.624859488142386340f, 0.780617398913848400f, + -0.625009181142947460f, + 0.780497540554531910f, -0.625158851163707620f, 0.780377653498552040f, + -0.625308498199164010f, + 0.780257737750316590f, -0.625458122243814360f, 0.780137793314234610f, + -0.625607723292157410f, + 0.780017820194715990f, -0.625757301338692900f, 0.779897818396172000f, + -0.625906856377921090f, + 0.779777787923014550f, -0.626056388404343520f, 0.779657728779656890f, + -0.626205897412462130f, + 0.779537640970513260f, -0.626355383396779990f, 0.779417524499998900f, + -0.626504846351800810f, + 0.779297379372530300f, -0.626654286272029350f, 0.779177205592524680f, + -0.626803703151971200f, + 0.779057003164400630f, -0.626953096986132660f, 0.778936772092577500f, + -0.627102467769020900f, + 0.778816512381475980f, -0.627251815495144080f, 0.778696224035517530f, + -0.627401140159011050f, + 0.778575907059125050f, -0.627550441755131530f, 0.778455561456721900f, + -0.627699720278016240f, + 0.778335187232733210f, -0.627848975722176460f, 0.778214784391584540f, + -0.627998208082124700f, + 0.778094352937702790f, -0.628147417352374000f, 0.777973892875516100f, + -0.628296603527438320f, + 0.777853404209453150f, -0.628445766601832710f, 0.777732886943944050f, + -0.628594906570072550f, + 0.777612341083420030f, -0.628744023426674680f, 0.777491766632313010f, + -0.628893117166156480f, + 0.777371163595056310f, -0.629042187783036000f, 0.777250531976084070f, + -0.629191235271832290f, + 0.777129871779831620f, -0.629340259627065630f, 0.777009183010735290f, + -0.629489260843256630f, + 0.776888465673232440f, -0.629638238914926980f, 0.776767719771761510f, + -0.629787193836599200f, + 0.776646945310762060f, -0.629936125602796440f, 0.776526142294674430f, + -0.630085034208043180f, + 0.776405310727940390f, -0.630233919646864370f, 0.776284450615002510f, + -0.630382781913785940f, + 0.776163561960304340f, -0.630531621003334600f, 0.776042644768290770f, + -0.630680436910037940f, + 0.775921699043407690f, -0.630829229628424470f, 0.775800724790101650f, + -0.630977999153023550f, + 0.775679722012820650f, -0.631126745478365340f, 0.775558690716013580f, + -0.631275468598980760f, + 0.775437630904130540f, -0.631424168509401860f, 0.775316542581622530f, + -0.631572845204161020f, + 0.775195425752941420f, -0.631721498677792260f, 0.775074280422540450f, + -0.631870128924829850f, + 0.774953106594873930f, -0.632018735939809060f, 0.774831904274396850f, + -0.632167319717265920f, + 0.774710673465565550f, -0.632315880251737570f, 0.774589414172837550f, + -0.632464417537761840f, + 0.774468126400670860f, -0.632612931569877410f, 0.774346810153525130f, + -0.632761422342624000f, + 0.774225465435860680f, -0.632909889850541750f, 0.774104092252139050f, + -0.633058334088172140f, + 0.773982690606822900f, -0.633206755050057190f, 0.773861260504375540f, + -0.633355152730739950f, + 0.773739801949261840f, -0.633503527124764320f, 0.773618314945947460f, + -0.633651878226674900f, + 0.773496799498899050f, -0.633800206031017280f, 0.773375255612584470f, + -0.633948510532337810f, + 0.773253683291472590f, -0.634096791725183740f, 0.773132082540033070f, + -0.634245049604103330f, + 0.773010453362736990f, -0.634393284163645490f, 0.772888795764056220f, + -0.634541495398360020f, + 0.772767109748463850f, -0.634689683302797740f, 0.772645395320433860f, + -0.634837847871509990f, + 0.772523652484441330f, -0.634985989099049460f, 0.772401881244962450f, + -0.635134106979969190f, + 0.772280081606474320f, -0.635282201508823420f, 0.772158253573455240f, + -0.635430272680167160f, + 0.772036397150384520f, -0.635578320488556110f, 0.771914512341742350f, + -0.635726344928547070f, + 0.771792599152010150f, -0.635874345994697720f, 0.771670657585670330f, + -0.636022323681566300f, + 0.771548687647206300f, -0.636170277983712170f, 0.771426689341102590f, + -0.636318208895695460f, + 0.771304662671844830f, -0.636466116412077180f, 0.771182607643919330f, + -0.636614000527419120f, + 0.771060524261813820f, -0.636761861236284200f, 0.770938412530016940f, + -0.636909698533235870f, + 0.770816272453018540f, -0.637057512412838590f, 0.770694104035309140f, + -0.637205302869657600f, + 0.770571907281380810f, -0.637353069898259130f, 0.770449682195725960f, + -0.637500813493210190f, + 0.770327428782838890f, -0.637648533649078810f, 0.770205147047214210f, + -0.637796230360433540f, + 0.770082836993347900f, -0.637943903621844060f, 0.769960498625737230f, + -0.638091553427880820f, + 0.769838131948879840f, -0.638239179773115280f, 0.769715736967275130f, + -0.638386782652119570f, + 0.769593313685422940f, -0.638534362059466790f, 0.769470862107824670f, + -0.638681917989730730f, + 0.769348382238982280f, -0.638829450437486290f, 0.769225874083399260f, + -0.638976959397309140f, + 0.769103337645579700f, -0.639124444863775730f, 0.768980772930028870f, + -0.639271906831463510f, + 0.768858179941253270f, -0.639419345294950700f, 0.768735558683760310f, + -0.639566760248816310f, + 0.768612909162058380f, -0.639714151687640450f, 0.768490231380656860f, + -0.639861519606003900f, + 0.768367525344066270f, -0.640008863998488440f, 0.768244791056798330f, + -0.640156184859676510f, + 0.768122028523365420f, -0.640303482184151670f, 0.767999237748281270f, + -0.640450755966498140f, + 0.767876418736060610f, -0.640598006201301030f, 0.767753571491219030f, + -0.640745232883146440f, + 0.767630696018273380f, -0.640892436006621380f, 0.767507792321741270f, + -0.641039615566313390f, + 0.767384860406141730f, -0.641186771556811250f, 0.767261900275994500f, + -0.641333903972704290f, + 0.767138911935820400f, -0.641481012808583160f, 0.767015895390141480f, + -0.641628098059038750f, + 0.766892850643480670f, -0.641775159718663500f, 0.766769777700361920f, + -0.641922197782050170f, + 0.766646676565310380f, -0.642069212243792540f, 0.766523547242852210f, + -0.642216203098485370f, + 0.766400389737514230f, -0.642363170340724320f, 0.766277204053824710f, + -0.642510113965105710f, + 0.766153990196312920f, -0.642657033966226860f, 0.766030748169509000f, + -0.642803930338685990f, + 0.765907477977944340f, -0.642950803077082080f, 0.765784179626150970f, + -0.643097652176015110f, + 0.765660853118662500f, -0.643244477630085850f, 0.765537498460013070f, + -0.643391279433895850f, + 0.765414115654738270f, -0.643538057582047740f, 0.765290704707374370f, + -0.643684812069144850f, + 0.765167265622458960f, -0.643831542889791390f, 0.765043798404530520f, + -0.643978250038592660f, + 0.764920303058128410f, -0.644124933510154540f, 0.764796779587793460f, + -0.644271593299083790f, + 0.764673227998067140f, -0.644418229399988380f, 0.764549648293492150f, + -0.644564841807476640f, + 0.764426040478612070f, -0.644711430516158310f, 0.764302404557971720f, + -0.644857995520643710f, + 0.764178740536116670f, -0.645004536815543930f, 0.764055048417593970f, + -0.645151054395471160f, + 0.763931328206951090f, -0.645297548255038380f, 0.763807579908737160f, + -0.645444018388859230f, + 0.763683803527501870f, -0.645590464791548690f, 0.763559999067796150f, + -0.645736887457722290f, + 0.763436166534172010f, -0.645883286381996320f, 0.763312305931182380f, + -0.646029661558988330f, + 0.763188417263381270f, -0.646176012983316280f, 0.763064500535323710f, + -0.646322340649599480f, + 0.762940555751565720f, -0.646468644552457780f, 0.762816582916664430f, + -0.646614924686512050f, + 0.762692582035177980f, -0.646761181046383920f, 0.762568553111665380f, + -0.646907413626696020f, + 0.762444496150687210f, -0.647053622422071540f, 0.762320411156804270f, + -0.647199807427135230f, + 0.762196298134578900f, -0.647345968636512060f, 0.762072157088574560f, + -0.647492106044828100f, + 0.761947988023355390f, -0.647638219646710310f, 0.761823790943486960f, + -0.647784309436786440f, + 0.761699565853535380f, -0.647930375409685340f, 0.761575312758068000f, + -0.648076417560036530f, + 0.761451031661653620f, -0.648222435882470420f, 0.761326722568861360f, + -0.648368430371618290f, + 0.761202385484261780f, -0.648514401022112440f, 0.761078020412426560f, + -0.648660347828585840f, + 0.760953627357928150f, -0.648806270785672550f, 0.760829206325340010f, + -0.648952169888007300f, + 0.760704757319236920f, -0.649098045130225950f, 0.760580280344194450f, + -0.649243896506964900f, + 0.760455775404789260f, -0.649389724012861660f, 0.760331242505599030f, + -0.649535527642554730f, + 0.760206681651202420f, -0.649681307390683190f, 0.760082092846179340f, + -0.649827063251887100f, + 0.759957476095110330f, -0.649972795220807530f, 0.759832831402577400f, + -0.650118503292086200f, + 0.759708158773163440f, -0.650264187460365850f, 0.759583458211452010f, + -0.650409847720290310f, + 0.759458729722028210f, -0.650555484066503880f, 0.759333973309477940f, + -0.650701096493652040f, + 0.759209188978388070f, -0.650846684996380880f, 0.759084376733346610f, + -0.650992249569337660f, + 0.758959536578942440f, -0.651137790207170330f, 0.758834668519765660f, + -0.651283306904527740f, + 0.758709772560407390f, -0.651428799656059820f, 0.758584848705459610f, + -0.651574268456416970f, + 0.758459896959515430f, -0.651719713300250910f, 0.758334917327168960f, + -0.651865134182213920f, + 0.758209909813015280f, -0.652010531096959500f, 0.758084874421650730f, + -0.652155904039141590f, + 0.757959811157672300f, -0.652301253003415460f, 0.757834720025678310f, + -0.652446577984436730f, + 0.757709601030268080f, -0.652591878976862440f, 0.757584454176041810f, + -0.652737155975350310f, + 0.757459279467600720f, -0.652882408974558850f, 0.757334076909547130f, + -0.653027637969147530f, + 0.757208846506484570f, -0.653172842953776760f, 0.757083588263017140f, + -0.653318023923107670f, + 0.756958302183750490f, -0.653463180871802330f, 0.756832988273290820f, + -0.653608313794523890f, + 0.756707646536245670f, -0.653753422685936060f, 0.756582276977223470f, + -0.653898507540703780f, + 0.756456879600833740f, -0.654043568353492640f, 0.756331454411686920f, + -0.654188605118969040f, + 0.756206001414394540f, -0.654333617831800440f, 0.756080520613569120f, + -0.654478606486655350f, + 0.755955012013824420f, -0.654623571078202680f, 0.755829475619774760f, + -0.654768511601112600f, + 0.755703911436035880f, -0.654913428050056030f, 0.755578319467224540f, + -0.655058320419704910f, + 0.755452699717958250f, -0.655203188704731820f, 0.755327052192855670f, + -0.655348032899810470f, + 0.755201376896536550f, -0.655492852999615350f, 0.755075673833621620f, + -0.655637648998821820f, + 0.754949943008732640f, -0.655782420892106030f, 0.754824184426492350f, + -0.655927168674145360f, + 0.754698398091524500f, -0.656071892339617600f, 0.754572584008453840f, + -0.656216591883201920f, + 0.754446742181906440f, -0.656361267299578000f, 0.754320872616508820f, + -0.656505918583426550f, + 0.754194975316889170f, -0.656650545729428940f, 0.754069050287676120f, + -0.656795148732268070f, + 0.753943097533499640f, -0.656939727586627110f, 0.753817117058990790f, + -0.657084282287190180f, + 0.753691108868781210f, -0.657228812828642540f, 0.753565072967504300f, + -0.657373319205670210f, + 0.753439009359793580f, -0.657517801412960120f, 0.753312918050284330f, + -0.657662259445200070f, + 0.753186799043612520f, -0.657806693297078640f, 0.753060652344415100f, + -0.657951102963285520f, + 0.752934477957330150f, -0.658095488438511180f, 0.752808275886996950f, + -0.658239849717446870f, + 0.752682046138055340f, -0.658384186794785050f, 0.752555788715146390f, + -0.658528499665218650f, + 0.752429503622912390f, -0.658672788323441890f, 0.752303190865996400f, + -0.658817052764149480f, + 0.752176850449042810f, -0.658961292982037320f, 0.752050482376696360f, + -0.659105508971802090f, + 0.751924086653603550f, -0.659249700728141490f, 0.751797663284411550f, + -0.659393868245753860f, + 0.751671212273768430f, -0.659538011519338660f, 0.751544733626323680f, + -0.659682130543596150f, + 0.751418227346727470f, -0.659826225313227320f, 0.751291693439630870f, + -0.659970295822934540f, + 0.751165131909686480f, -0.660114342067420480f, 0.751038542761547360f, + -0.660258364041389050f, + 0.750911925999867890f, -0.660402361739545030f, 0.750785281629303690f, + -0.660546335156593890f, + 0.750658609654510700f, -0.660690284287242300f, 0.750531910080146410f, + -0.660834209126197610f, + 0.750405182910869330f, -0.660978109668168060f, 0.750278428151338720f, + -0.661121985907862860f, + 0.750151645806215070f, -0.661265837839992270f, 0.750024835880159780f, + -0.661409665459266940f, + 0.749897998377835330f, -0.661553468760398890f, 0.749771133303905100f, + -0.661697247738101010f, + 0.749644240663033480f, -0.661841002387086870f, 0.749517320459886170f, + -0.661984732702070920f, + 0.749390372699129560f, -0.662128438677768720f, 0.749263397385431130f, + -0.662272120308896590f, + 0.749136394523459370f, -0.662415777590171780f, 0.749009364117883880f, + -0.662559410516312290f, + 0.748882306173375150f, -0.662703019082037440f, 0.748755220694604760f, + -0.662846603282066900f, + 0.748628107686245440f, -0.662990163111121470f, 0.748500967152970430f, + -0.663133698563923010f, + 0.748373799099454560f, -0.663277209635194100f, 0.748246603530373420f, + -0.663420696319658280f, + 0.748119380450403600f, -0.663564158612039770f, 0.747992129864222700f, + -0.663707596507064010f, + 0.747864851776509410f, -0.663851009999457340f, 0.747737546191943330f, + -0.663994399083946640f, + 0.747610213115205150f, -0.664137763755260010f, 0.747482852550976570f, + -0.664281104008126230f, + 0.747355464503940190f, -0.664424419837275180f, 0.747228048978779920f, + -0.664567711237437520f, + 0.747100605980180130f, -0.664710978203344790f, 0.746973135512826850f, + -0.664854220729729660f, + 0.746845637581406540f, -0.664997438811325340f, 0.746718112190607130f, + -0.665140632442866140f, + 0.746590559345117310f, -0.665283801619087180f, 0.746462979049626770f, + -0.665426946334724660f, + 0.746335371308826320f, -0.665570066584515450f, 0.746207736127407760f, + -0.665713162363197550f, + 0.746080073510063780f, -0.665856233665509720f, 0.745952383461488290f, + -0.665999280486191500f, + 0.745824665986376090f, -0.666142302819983540f, 0.745696921089422760f, + -0.666285300661627280f, + 0.745569148775325430f, -0.666428274005865240f, 0.745441349048781680f, + -0.666571222847440640f, + 0.745313521914490520f, -0.666714147181097670f, 0.745185667377151640f, + -0.666857047001581220f, + 0.745057785441466060f, -0.666999922303637470f, 0.744929876112135350f, + -0.667142773082013310f, + 0.744801939393862630f, -0.667285599331456370f, 0.744673975291351710f, + -0.667428401046715520f, + 0.744545983809307370f, -0.667571178222540310f, 0.744417964952435620f, + -0.667713930853681030f, + 0.744289918725443260f, -0.667856658934889320f, 0.744161845133038180f, + -0.667999362460917400f, + 0.744033744179929290f, -0.668142041426518450f, 0.743905615870826490f, + -0.668284695826446670f, + 0.743777460210440890f, -0.668427325655456820f, 0.743649277203484060f, + -0.668569930908304970f, + 0.743521066854669120f, -0.668712511579747980f, 0.743392829168709970f, + -0.668855067664543610f, + 0.743264564150321600f, -0.668997599157450270f, 0.743136271804219820f, + -0.669140106053227600f, + 0.743007952135121720f, -0.669282588346636010f, 0.742879605147745200f, + -0.669425046032436910f, + 0.742751230846809050f, -0.669567479105392490f, 0.742622829237033490f, + -0.669709887560265840f, + 0.742494400323139180f, -0.669852271391821020f, 0.742365944109848460f, + -0.669994630594823000f, + 0.742237460601884000f, -0.670136965164037650f, 0.742108949803969910f, + -0.670279275094231800f, + 0.741980411720831070f, -0.670421560380173090f, 0.741851846357193480f, + -0.670563821016630040f, + 0.741723253717784140f, -0.670706056998372160f, 0.741594633807331150f, + -0.670848268320169640f, + 0.741465986630563290f, -0.670990454976794220f, 0.741337312192210660f, + -0.671132616963017740f, + 0.741208610497004260f, -0.671274754273613490f, 0.741079881549676080f, + -0.671416866903355450f, + 0.740951125354959110f, -0.671558954847018330f, 0.740822341917587330f, + -0.671701018099378320f, + 0.740693531242295760f, -0.671843056655211930f, 0.740564693333820250f, + -0.671985070509296900f, + 0.740435828196898020f, -0.672127059656411730f, 0.740306935836266940f, + -0.672269024091335930f, + 0.740178016256666240f, -0.672410963808849790f, 0.740049069462835550f, + -0.672552878803734710f, + 0.739920095459516200f, -0.672694769070772860f, 0.739791094251449950f, + -0.672836634604747300f, + 0.739662065843380010f, -0.672978475400442090f, 0.739533010240050250f, + -0.673120291452642070f, + 0.739403927446205760f, -0.673262082756132970f, 0.739274817466592520f, + -0.673403849305701740f, + 0.739145680305957510f, -0.673545591096136100f, 0.739016515969048720f, + -0.673687308122224330f, + 0.738887324460615110f, -0.673829000378756040f, 0.738758105785406900f, + -0.673970667860521620f, + 0.738628859948174840f, -0.674112310562312360f, 0.738499586953671130f, + -0.674253928478920410f, + 0.738370286806648620f, -0.674395521605139050f, 0.738240959511861310f, + -0.674537089935762000f, + 0.738111605074064260f, -0.674678633465584540f, 0.737982223498013570f, + -0.674820152189402170f, + 0.737852814788465980f, -0.674961646102011930f, 0.737723378950179700f, + -0.675103115198211420f, + 0.737593915987913570f, -0.675244559472799270f, 0.737464425906427580f, + -0.675385978920574840f, + 0.737334908710482910f, -0.675527373536338520f, 0.737205364404841190f, + -0.675668743314891910f, + 0.737075792994265730f, -0.675810088251036940f, 0.736946194483520280f, + -0.675951408339577010f, + 0.736816568877369900f, -0.676092703575315920f, 0.736686916180580460f, + -0.676233973953058950f, + 0.736557236397919150f, -0.676375219467611590f, 0.736427529534153690f, + -0.676516440113781090f, + 0.736297795594053170f, -0.676657635886374950f, 0.736168034582387330f, + -0.676798806780201770f, + 0.736038246503927350f, -0.676939952790071130f, 0.735908431363445190f, + -0.677081073910793530f, + 0.735778589165713590f, -0.677222170137180330f, 0.735648719915506510f, + -0.677363241464043920f, + 0.735518823617598900f, -0.677504287886197430f, 0.735388900276766730f, + -0.677645309398454910f, + 0.735258949897786840f, -0.677786305995631500f, 0.735128972485437180f, + -0.677927277672543020f, + 0.734998968044496710f, -0.678068224424006600f, 0.734868936579745170f, + -0.678209146244839860f, + 0.734738878095963500f, -0.678350043129861470f, 0.734608792597933550f, + -0.678490915073891140f, + 0.734478680090438370f, -0.678631762071749360f, 0.734348540578261600f, + -0.678772584118257690f, + 0.734218374066188280f, -0.678913381208238410f, 0.734088180559004040f, + -0.679054153336514870f, + 0.733957960061495940f, -0.679194900497911200f, 0.733827712578451700f, + -0.679335622687252560f, + 0.733697438114660370f, -0.679476319899364970f, 0.733567136674911360f, + -0.679616992129075560f, + 0.733436808263995710f, -0.679757639371212030f, 0.733306452886705260f, + -0.679898261620603290f, + 0.733176070547832740f, -0.680038858872078930f, 0.733045661252172080f, + -0.680179431120469750f, + 0.732915225004517780f, -0.680319978360607200f, 0.732784761809665790f, + -0.680460500587323880f, + 0.732654271672412820f, -0.680600997795453020f, 0.732523754597556700f, + -0.680741469979829090f, + 0.732393210589896040f, -0.680881917135287230f, 0.732262639654230770f, + -0.681022339256663670f, + 0.732132041795361290f, -0.681162736338795430f, 0.732001417018089630f, + -0.681303108376520530f, + 0.731870765327218290f, -0.681443455364677870f, 0.731740086727550980f, + -0.681583777298107480f, + 0.731609381223892630f, -0.681724074171649710f, 0.731478648821048520f, + -0.681864345980146670f, + 0.731347889523825570f, -0.682004592718440830f, 0.731217103337031270f, + -0.682144814381375640f, + 0.731086290265474340f, -0.682285010963795570f, 0.730955450313964360f, + -0.682425182460546060f, + 0.730824583487312160f, -0.682565328866473250f, 0.730693689790329000f, + -0.682705450176424590f, + 0.730562769227827590f, -0.682845546385248080f, 0.730431821804621520f, + -0.682985617487792740f, + 0.730300847525525490f, -0.683125663478908680f, 0.730169846395354870f, + -0.683265684353446700f, + 0.730038818418926260f, -0.683405680106258680f, 0.729907763601057140f, + -0.683545650732197530f, + 0.729776681946566090f, -0.683685596226116580f, 0.729645573460272480f, + -0.683825516582870720f, + 0.729514438146997010f, -0.683965411797315400f, 0.729383276011561050f, + -0.684105281864307080f, + 0.729252087058786970f, -0.684245126778703080f, 0.729120871293498230f, + -0.684384946535361750f, + 0.728989628720519420f, -0.684524741129142300f, 0.728858359344675800f, + -0.684664510554904960f, + 0.728727063170793830f, -0.684804254807510620f, 0.728595740203700770f, + -0.684943973881821490f, + 0.728464390448225200f, -0.685083667772700360f, 0.728333013909196360f, + -0.685223336475011210f, + 0.728201610591444610f, -0.685362979983618730f, 0.728070180499801210f, + -0.685502598293388550f, + 0.727938723639098620f, -0.685642191399187470f, 0.727807240014169960f, + -0.685781759295883030f, + 0.727675729629849610f, -0.685921301978343560f, 0.727544192490972800f, + -0.686060819441438710f, + 0.727412628602375770f, -0.686200311680038590f, 0.727281037968895870f, + -0.686339778689014520f, + 0.727149420595371020f, -0.686479220463238950f, 0.727017776486640680f, + -0.686618636997584630f, + 0.726886105647544970f, -0.686758028286925890f, 0.726754408082925020f, + -0.686897394326137610f, + 0.726622683797622850f, -0.687036735110095660f, 0.726490932796481910f, + -0.687176050633676820f, + 0.726359155084346010f, -0.687315340891759050f, 0.726227350666060370f, + -0.687454605879221030f, + 0.726095519546471000f, -0.687593845590942170f, 0.725963661730424930f, + -0.687733060021803230f, + 0.725831777222770370f, -0.687872249166685550f, 0.725699866028356120f, + -0.688011413020471640f, + 0.725567928152032300f, -0.688150551578044830f, 0.725435963598649810f, + -0.688289664834289330f, + 0.725303972373060770f, -0.688428752784090440f, 0.725171954480117950f, + -0.688567815422334250f, + 0.725039909924675370f, -0.688706852743907750f, 0.724907838711587820f, + -0.688845864743699020f, + 0.724775740845711280f, -0.688984851416597040f, 0.724643616331902550f, + -0.689123812757491570f, + 0.724511465175019630f, -0.689262748761273470f, 0.724379287379921190f, + -0.689401659422834270f, + 0.724247082951467000f, -0.689540544737066830f, 0.724114851894517850f, + -0.689679404698864800f, + 0.723982594213935520f, -0.689818239303122470f, 0.723850309914582880f, + -0.689957048544735390f, + 0.723717999001323500f, -0.690095832418599950f, 0.723585661479022150f, + -0.690234590919613370f, + 0.723453297352544380f, -0.690373324042674040f, 0.723320906626756970f, + -0.690512031782681060f, + 0.723188489306527460f, -0.690650714134534600f, 0.723056045396724410f, + -0.690789371093135650f, + 0.722923574902217700f, -0.690928002653386160f, 0.722791077827877550f, + -0.691066608810189220f, + 0.722658554178575610f, -0.691205189558448450f, 0.722526003959184540f, + -0.691343744893068710f, + 0.722393427174577550f, -0.691482274808955850f, 0.722260823829629310f, + -0.691620779301016290f, + 0.722128193929215350f, -0.691759258364157750f, 0.721995537478211880f, + -0.691897711993288760f, + 0.721862854481496340f, -0.692036140183318720f, 0.721730144943947160f, + -0.692174542929158140f, + 0.721597408870443770f, -0.692312920225718220f, 0.721464646265866370f, + -0.692451272067911130f, + 0.721331857135096290f, -0.692589598450650380f, 0.721199041483015720f, + -0.692727899368849820f, + 0.721066199314508110f, -0.692866174817424630f, 0.720933330634457530f, + -0.693004424791290870f, + 0.720800435447749190f, -0.693142649285365400f, 0.720667513759269520f, + -0.693280848294566040f, + 0.720534565573905270f, -0.693419021813811760f, 0.720401590896544760f, + -0.693557169838022290f, + 0.720268589732077190f, -0.693695292362118240f, 0.720135562085392420f, + -0.693833389381021350f, + 0.720002507961381650f, -0.693971460889654000f, 0.719869427364936860f, + -0.694109506882939820f, + 0.719736320300951030f, -0.694247527355803310f, 0.719603186774318120f, + -0.694385522303169740f, + 0.719470026789932990f, -0.694523491719965520f, 0.719336840352691740f, + -0.694661435601117820f, + 0.719203627467491220f, -0.694799353941554900f, 0.719070388139229190f, + -0.694937246736205830f, + 0.718937122372804490f, -0.695075113980000880f, 0.718803830173116890f, + -0.695212955667870780f, + 0.718670511545067230f, -0.695350771794747690f, 0.718537166493557370f, + -0.695488562355564440f, + 0.718403795023489830f, -0.695626327345254870f, 0.718270397139768260f, + -0.695764066758753690f, + 0.718136972847297490f, -0.695901780590996830f, 0.718003522150983180f, + -0.696039468836920690f, + 0.717870045055731710f, -0.696177131491462990f, 0.717736541566450950f, + -0.696314768549562090f, + 0.717603011688049080f, -0.696452380006157830f, 0.717469455425435830f, + -0.696589965856190370f, + 0.717335872783521730f, -0.696727526094601200f, 0.717202263767218070f, + -0.696865060716332470f, + 0.717068628381437480f, -0.697002569716327460f, 0.716934966631093130f, + -0.697140053089530420f, + 0.716801278521099540f, -0.697277510830886520f, 0.716667564056371890f, + -0.697414942935341790f, + 0.716533823241826680f, -0.697552349397843160f, 0.716400056082381000f, + -0.697689730213338800f, + 0.716266262582953120f, -0.697827085376777290f, 0.716132442748462330f, + -0.697964414883108670f, + 0.715998596583828690f, -0.698101718727283770f, 0.715864724093973500f, + -0.698238996904254280f, + 0.715730825283818590f, -0.698376249408972920f, 0.715596900158287470f, + -0.698513476236393040f, + 0.715462948722303760f, -0.698650677381469460f, 0.715328970980792620f, + -0.698787852839157670f, + 0.715194966938680120f, -0.698925002604414150f, 0.715060936600893090f, + -0.699062126672196140f, + 0.714926879972359490f, -0.699199225037462120f, 0.714792797058008240f, + -0.699336297695171140f, + 0.714658687862769090f, -0.699473344640283770f, 0.714524552391572860f, + -0.699610365867761040f, + 0.714390390649351390f, -0.699747361372564990f, 0.714256202641037510f, + -0.699884331149658760f, + 0.714121988371564820f, -0.700021275194006250f, 0.713987747845867830f, + -0.700158193500572730f, + 0.713853481068882470f, -0.700295086064323780f, 0.713719188045545240f, + -0.700431952880226420f, + 0.713584868780793640f, -0.700568793943248340f, 0.713450523279566260f, + -0.700705609248358450f, + 0.713316151546802610f, -0.700842398790526120f, 0.713181753587443180f, + -0.700979162564722370f, + 0.713047329406429340f, -0.701115900565918660f, 0.712912879008703480f, + -0.701252612789087460f, + 0.712778402399208980f, -0.701389299229202230f, 0.712643899582890210f, + -0.701525959881237340f, + 0.712509370564692320f, -0.701662594740168450f, 0.712374815349561710f, + -0.701799203800971720f, + 0.712240233942445510f, -0.701935787058624360f, 0.712105626348291890f, + -0.702072344508104630f, + 0.711970992572050100f, -0.702208876144391870f, 0.711836332618670080f, + -0.702345381962465880f, + 0.711701646493102970f, -0.702481861957308000f, 0.711566934200300700f, + -0.702618316123900130f, + 0.711432195745216430f, -0.702754744457225300f, 0.711297431132803970f, + -0.702891146952267400f, + 0.711162640368018350f, -0.703027523604011220f, 0.711027823455815280f, + -0.703163874407442770f, + 0.710892980401151680f, -0.703300199357548730f, 0.710758111208985350f, + -0.703436498449316660f, + 0.710623215884275020f, -0.703572771677735580f, 0.710488294431980470f, + -0.703709019037794810f, + 0.710353346857062420f, -0.703845240524484940f, 0.710218373164482220f, + -0.703981436132797620f, + 0.710083373359202800f, -0.704117605857725310f, 0.709948347446187400f, + -0.704253749694261470f, + 0.709813295430400840f, -0.704389867637400410f, 0.709678217316808580f, + -0.704525959682137380f, + 0.709543113110376770f, -0.704662025823468820f, 0.709407982816072980f, + -0.704798066056391950f, + 0.709272826438865690f, -0.704934080375904880f, 0.709137643983724030f, + -0.705070068777006840f, + 0.709002435455618250f, -0.705206031254697830f, 0.708867200859519820f, + -0.705341967803978840f, + 0.708731940200400650f, -0.705477878419852100f, 0.708596653483234080f, + -0.705613763097320490f, + 0.708461340712994160f, -0.705749621831387790f, 0.708326001894655890f, + -0.705885454617058980f, + 0.708190637033195400f, -0.706021261449339740f, 0.708055246133589500f, + -0.706157042323237060f, + 0.707919829200816310f, -0.706292797233758480f, 0.707784386239854620f, + -0.706428526175912790f, + 0.707648917255684350f, -0.706564229144709510f, 0.707513422253286280f, + -0.706699906135159430f, + 0.707377901237642100f, -0.706835557142273750f, 0.707242354213734710f, + -0.706971182161065360f, + 0.707106781186547570f, -0.707106781186547460f, 0.706971182161065360f, + -0.707242354213734600f, + 0.706835557142273860f, -0.707377901237642100f, 0.706699906135159430f, + -0.707513422253286170f, + 0.706564229144709620f, -0.707648917255684350f, 0.706428526175912790f, + -0.707784386239854620f, + 0.706292797233758480f, -0.707919829200816310f, 0.706157042323237060f, + -0.708055246133589500f, + 0.706021261449339740f, -0.708190637033195290f, 0.705885454617058980f, + -0.708326001894655780f, + 0.705749621831387790f, -0.708461340712994050f, 0.705613763097320490f, + -0.708596653483234080f, + 0.705477878419852210f, -0.708731940200400650f, 0.705341967803978950f, + -0.708867200859519820f, + 0.705206031254697830f, -0.709002435455618250f, 0.705070068777006840f, + -0.709137643983723920f, + 0.704934080375904990f, -0.709272826438865580f, 0.704798066056391950f, + -0.709407982816072980f, + 0.704662025823468930f, -0.709543113110376770f, 0.704525959682137380f, + -0.709678217316808470f, + 0.704389867637400410f, -0.709813295430400840f, 0.704253749694261580f, + -0.709948347446187400f, + 0.704117605857725430f, -0.710083373359202690f, 0.703981436132797730f, + -0.710218373164482220f, + 0.703845240524484940f, -0.710353346857062310f, 0.703709019037794810f, + -0.710488294431980470f, + 0.703572771677735580f, -0.710623215884275020f, 0.703436498449316770f, + -0.710758111208985350f, + 0.703300199357548730f, -0.710892980401151680f, 0.703163874407442770f, + -0.711027823455815280f, + 0.703027523604011220f, -0.711162640368018350f, 0.702891146952267400f, + -0.711297431132803970f, + 0.702754744457225300f, -0.711432195745216430f, 0.702618316123900130f, + -0.711566934200300700f, + 0.702481861957308000f, -0.711701646493102970f, 0.702345381962465880f, + -0.711836332618670080f, + 0.702208876144391870f, -0.711970992572049990f, 0.702072344508104740f, + -0.712105626348291890f, + 0.701935787058624360f, -0.712240233942445510f, 0.701799203800971720f, + -0.712374815349561710f, + 0.701662594740168570f, -0.712509370564692320f, 0.701525959881237450f, + -0.712643899582890210f, + 0.701389299229202230f, -0.712778402399208870f, 0.701252612789087460f, + -0.712912879008703370f, + 0.701115900565918660f, -0.713047329406429230f, 0.700979162564722480f, + -0.713181753587443070f, + 0.700842398790526230f, -0.713316151546802610f, 0.700705609248358450f, + -0.713450523279566150f, + 0.700568793943248450f, -0.713584868780793520f, 0.700431952880226420f, + -0.713719188045545130f, + 0.700295086064323780f, -0.713853481068882470f, 0.700158193500572730f, + -0.713987747845867830f, + 0.700021275194006360f, -0.714121988371564710f, 0.699884331149658760f, + -0.714256202641037400f, + 0.699747361372564990f, -0.714390390649351390f, 0.699610365867761040f, + -0.714524552391572860f, + 0.699473344640283770f, -0.714658687862768980f, 0.699336297695171250f, + -0.714792797058008130f, + 0.699199225037462120f, -0.714926879972359370f, 0.699062126672196140f, + -0.715060936600892980f, + 0.698925002604414150f, -0.715194966938680010f, 0.698787852839157790f, + -0.715328970980792620f, + 0.698650677381469580f, -0.715462948722303650f, 0.698513476236393040f, + -0.715596900158287360f, + 0.698376249408972920f, -0.715730825283818590f, 0.698238996904254390f, + -0.715864724093973390f, + 0.698101718727283880f, -0.715998596583828690f, 0.697964414883108790f, + -0.716132442748462330f, + 0.697827085376777290f, -0.716266262582953120f, 0.697689730213338800f, + -0.716400056082380890f, + 0.697552349397843270f, -0.716533823241826570f, 0.697414942935341790f, + -0.716667564056371890f, + 0.697277510830886630f, -0.716801278521099540f, 0.697140053089530530f, + -0.716934966631093130f, + 0.697002569716327460f, -0.717068628381437480f, 0.696865060716332470f, + -0.717202263767218070f, + 0.696727526094601200f, -0.717335872783521730f, 0.696589965856190370f, + -0.717469455425435830f, + 0.696452380006157830f, -0.717603011688049080f, 0.696314768549562200f, + -0.717736541566450840f, + 0.696177131491462990f, -0.717870045055731710f, 0.696039468836920690f, + -0.718003522150983060f, + 0.695901780590996830f, -0.718136972847297490f, 0.695764066758753800f, + -0.718270397139768260f, + 0.695626327345254870f, -0.718403795023489720f, 0.695488562355564440f, + -0.718537166493557370f, + 0.695350771794747800f, -0.718670511545067230f, 0.695212955667870890f, + -0.718803830173116890f, + 0.695075113980000880f, -0.718937122372804380f, 0.694937246736205940f, + -0.719070388139229190f, + 0.694799353941554900f, -0.719203627467491220f, 0.694661435601117930f, + -0.719336840352691740f, + 0.694523491719965520f, -0.719470026789932990f, 0.694385522303169860f, + -0.719603186774318000f, + 0.694247527355803310f, -0.719736320300951030f, 0.694109506882939820f, + -0.719869427364936860f, + 0.693971460889654000f, -0.720002507961381650f, 0.693833389381021350f, + -0.720135562085392310f, + 0.693695292362118350f, -0.720268589732077080f, 0.693557169838022400f, + -0.720401590896544760f, + 0.693419021813811880f, -0.720534565573905270f, 0.693280848294566150f, + -0.720667513759269410f, + 0.693142649285365510f, -0.720800435447749190f, 0.693004424791290870f, + -0.720933330634457530f, + 0.692866174817424740f, -0.721066199314508110f, 0.692727899368849820f, + -0.721199041483015720f, + 0.692589598450650380f, -0.721331857135096180f, 0.692451272067911240f, + -0.721464646265866370f, + 0.692312920225718220f, -0.721597408870443660f, 0.692174542929158140f, + -0.721730144943947160f, + 0.692036140183318830f, -0.721862854481496340f, 0.691897711993288760f, + -0.721995537478211880f, + 0.691759258364157750f, -0.722128193929215350f, 0.691620779301016400f, + -0.722260823829629310f, + 0.691482274808955850f, -0.722393427174577550f, 0.691343744893068820f, + -0.722526003959184430f, + 0.691205189558448450f, -0.722658554178575610f, 0.691066608810189220f, + -0.722791077827877550f, + 0.690928002653386280f, -0.722923574902217700f, 0.690789371093135760f, + -0.723056045396724410f, + 0.690650714134534720f, -0.723188489306527350f, 0.690512031782681170f, + -0.723320906626756850f, + 0.690373324042674040f, -0.723453297352544380f, 0.690234590919613370f, + -0.723585661479022040f, + 0.690095832418599950f, -0.723717999001323390f, 0.689957048544735390f, + -0.723850309914582880f, + 0.689818239303122470f, -0.723982594213935520f, 0.689679404698864800f, + -0.724114851894517850f, + 0.689540544737066940f, -0.724247082951466890f, 0.689401659422834380f, + -0.724379287379921080f, + 0.689262748761273470f, -0.724511465175019520f, 0.689123812757491680f, + -0.724643616331902550f, + 0.688984851416597150f, -0.724775740845711280f, 0.688845864743699130f, + -0.724907838711587820f, + 0.688706852743907750f, -0.725039909924675370f, 0.688567815422334360f, + -0.725171954480117840f, + 0.688428752784090550f, -0.725303972373060660f, 0.688289664834289440f, + -0.725435963598649810f, + 0.688150551578044830f, -0.725567928152032300f, 0.688011413020471640f, + -0.725699866028356120f, + 0.687872249166685550f, -0.725831777222770370f, 0.687733060021803230f, + -0.725963661730424930f, + 0.687593845590942170f, -0.726095519546470890f, 0.687454605879221030f, + -0.726227350666060260f, + 0.687315340891759160f, -0.726359155084346010f, 0.687176050633676930f, + -0.726490932796481910f, + 0.687036735110095660f, -0.726622683797622850f, 0.686897394326137610f, + -0.726754408082924910f, + 0.686758028286925890f, -0.726886105647544970f, 0.686618636997584740f, + -0.727017776486640680f, + 0.686479220463238950f, -0.727149420595371020f, 0.686339778689014630f, + -0.727281037968895760f, + 0.686200311680038700f, -0.727412628602375770f, 0.686060819441438710f, + -0.727544192490972800f, + 0.685921301978343670f, -0.727675729629849610f, 0.685781759295883030f, + -0.727807240014169960f, + 0.685642191399187470f, -0.727938723639098620f, 0.685502598293388670f, + -0.728070180499801210f, + 0.685362979983618730f, -0.728201610591444500f, 0.685223336475011210f, + -0.728333013909196360f, + 0.685083667772700360f, -0.728464390448225200f, 0.684943973881821490f, + -0.728595740203700770f, + 0.684804254807510620f, -0.728727063170793720f, 0.684664510554904960f, + -0.728858359344675690f, + 0.684524741129142300f, -0.728989628720519310f, 0.684384946535361750f, + -0.729120871293498230f, + 0.684245126778703080f, -0.729252087058786970f, 0.684105281864307080f, + -0.729383276011561050f, + 0.683965411797315510f, -0.729514438146996900f, 0.683825516582870830f, + -0.729645573460272480f, + 0.683685596226116690f, -0.729776681946565970f, 0.683545650732197530f, + -0.729907763601057140f, + 0.683405680106258790f, -0.730038818418926150f, 0.683265684353446700f, + -0.730169846395354870f, + 0.683125663478908800f, -0.730300847525525380f, 0.682985617487792850f, + -0.730431821804621520f, + 0.682845546385248080f, -0.730562769227827590f, 0.682705450176424590f, + -0.730693689790328890f, + 0.682565328866473250f, -0.730824583487312050f, 0.682425182460546060f, + -0.730955450313964360f, + 0.682285010963795570f, -0.731086290265474230f, 0.682144814381375640f, + -0.731217103337031160f, + 0.682004592718440830f, -0.731347889523825460f, 0.681864345980146780f, + -0.731478648821048520f, + 0.681724074171649820f, -0.731609381223892520f, 0.681583777298107480f, + -0.731740086727550980f, + 0.681443455364677990f, -0.731870765327218290f, 0.681303108376520530f, + -0.732001417018089520f, + 0.681162736338795430f, -0.732132041795361290f, 0.681022339256663670f, + -0.732262639654230660f, + 0.680881917135287340f, -0.732393210589896040f, 0.680741469979829090f, + -0.732523754597556590f, + 0.680600997795453130f, -0.732654271672412820f, 0.680460500587323880f, + -0.732784761809665790f, + 0.680319978360607200f, -0.732915225004517780f, 0.680179431120469750f, + -0.733045661252171970f, + 0.680038858872079040f, -0.733176070547832740f, 0.679898261620603290f, + -0.733306452886705260f, + 0.679757639371212030f, -0.733436808263995710f, 0.679616992129075560f, + -0.733567136674911360f, + 0.679476319899365080f, -0.733697438114660260f, 0.679335622687252670f, + -0.733827712578451700f, + 0.679194900497911200f, -0.733957960061495940f, 0.679054153336514870f, + -0.734088180559004040f, + 0.678913381208238410f, -0.734218374066188170f, 0.678772584118257690f, + -0.734348540578261600f, + 0.678631762071749470f, -0.734478680090438370f, 0.678490915073891250f, + -0.734608792597933550f, + 0.678350043129861580f, -0.734738878095963390f, 0.678209146244839860f, + -0.734868936579745060f, + 0.678068224424006600f, -0.734998968044496600f, 0.677927277672543130f, + -0.735128972485437180f, + 0.677786305995631500f, -0.735258949897786730f, 0.677645309398454910f, + -0.735388900276766620f, + 0.677504287886197430f, -0.735518823617598900f, 0.677363241464044030f, + -0.735648719915506400f, + 0.677222170137180450f, -0.735778589165713480f, 0.677081073910793530f, + -0.735908431363445190f, + 0.676939952790071240f, -0.736038246503927350f, 0.676798806780201770f, + -0.736168034582387330f, + 0.676657635886374950f, -0.736297795594053060f, 0.676516440113781090f, + -0.736427529534153690f, + 0.676375219467611700f, -0.736557236397919150f, 0.676233973953058950f, + -0.736686916180580460f, + 0.676092703575316030f, -0.736816568877369790f, 0.675951408339577010f, + -0.736946194483520170f, + 0.675810088251037060f, -0.737075792994265620f, 0.675668743314891910f, + -0.737205364404841190f, + 0.675527373536338630f, -0.737334908710482790f, 0.675385978920574950f, + -0.737464425906427580f, + 0.675244559472799270f, -0.737593915987913460f, 0.675103115198211530f, + -0.737723378950179590f, + 0.674961646102012040f, -0.737852814788465980f, 0.674820152189402280f, + -0.737982223498013570f, + 0.674678633465584540f, -0.738111605074064260f, 0.674537089935762110f, + -0.738240959511861310f, + 0.674395521605139050f, -0.738370286806648510f, 0.674253928478920520f, + -0.738499586953671130f, + 0.674112310562312360f, -0.738628859948174840f, 0.673970667860521620f, + -0.738758105785406900f, + 0.673829000378756150f, -0.738887324460615110f, 0.673687308122224330f, + -0.739016515969048600f, + 0.673545591096136100f, -0.739145680305957400f, 0.673403849305701850f, + -0.739274817466592520f, + 0.673262082756132970f, -0.739403927446205760f, 0.673120291452642070f, + -0.739533010240050250f, + 0.672978475400442090f, -0.739662065843379900f, 0.672836634604747410f, + -0.739791094251449950f, + 0.672694769070772970f, -0.739920095459516090f, 0.672552878803734820f, + -0.740049069462835550f, + 0.672410963808849900f, -0.740178016256666240f, 0.672269024091336040f, + -0.740306935836266940f, + 0.672127059656411840f, -0.740435828196898020f, 0.671985070509296900f, + -0.740564693333820250f, + 0.671843056655211930f, -0.740693531242295640f, 0.671701018099378320f, + -0.740822341917587330f, + 0.671558954847018330f, -0.740951125354959110f, 0.671416866903355450f, + -0.741079881549676080f, + 0.671274754273613490f, -0.741208610497004260f, 0.671132616963017850f, + -0.741337312192210660f, + 0.670990454976794220f, -0.741465986630563290f, 0.670848268320169750f, + -0.741594633807331150f, + 0.670706056998372160f, -0.741723253717784140f, 0.670563821016630040f, + -0.741851846357193480f, + 0.670421560380173090f, -0.741980411720830960f, 0.670279275094231910f, + -0.742108949803969800f, + 0.670136965164037760f, -0.742237460601884000f, 0.669994630594823000f, + -0.742365944109848460f, + 0.669852271391821130f, -0.742494400323139180f, 0.669709887560265840f, + -0.742622829237033380f, + 0.669567479105392490f, -0.742751230846809050f, 0.669425046032436910f, + -0.742879605147745090f, + 0.669282588346636010f, -0.743007952135121720f, 0.669140106053227710f, + -0.743136271804219820f, + 0.668997599157450270f, -0.743264564150321490f, 0.668855067664543610f, + -0.743392829168709970f, + 0.668712511579748090f, -0.743521066854669120f, 0.668569930908305080f, + -0.743649277203484060f, + 0.668427325655456820f, -0.743777460210440780f, 0.668284695826446670f, + -0.743905615870826490f, + 0.668142041426518560f, -0.744033744179929180f, 0.667999362460917510f, + -0.744161845133038070f, + 0.667856658934889440f, -0.744289918725443140f, 0.667713930853681140f, + -0.744417964952435620f, + 0.667571178222540310f, -0.744545983809307250f, 0.667428401046715640f, + -0.744673975291351600f, + 0.667285599331456480f, -0.744801939393862630f, 0.667142773082013310f, + -0.744929876112135350f, + 0.666999922303637470f, -0.745057785441465950f, 0.666857047001581220f, + -0.745185667377151640f, + 0.666714147181097670f, -0.745313521914490410f, 0.666571222847440750f, + -0.745441349048781680f, + 0.666428274005865350f, -0.745569148775325430f, 0.666285300661627390f, + -0.745696921089422760f, + 0.666142302819983540f, -0.745824665986375980f, 0.665999280486191500f, + -0.745952383461488180f, + 0.665856233665509720f, -0.746080073510063780f, 0.665713162363197660f, + -0.746207736127407650f, + 0.665570066584515560f, -0.746335371308826320f, 0.665426946334724660f, + -0.746462979049626770f, + 0.665283801619087180f, -0.746590559345117310f, 0.665140632442866140f, + -0.746718112190607020f, + 0.664997438811325340f, -0.746845637581406540f, 0.664854220729729660f, + -0.746973135512826740f, + 0.664710978203344900f, -0.747100605980180130f, 0.664567711237437520f, + -0.747228048978779920f, + 0.664424419837275180f, -0.747355464503940190f, 0.664281104008126230f, + -0.747482852550976570f, + 0.664137763755260010f, -0.747610213115205150f, 0.663994399083946640f, + -0.747737546191943330f, + 0.663851009999457340f, -0.747864851776509410f, 0.663707596507064120f, + -0.747992129864222700f, + 0.663564158612039880f, -0.748119380450403490f, 0.663420696319658280f, + -0.748246603530373420f, + 0.663277209635194100f, -0.748373799099454560f, 0.663133698563923010f, + -0.748500967152970430f, + 0.662990163111121470f, -0.748628107686245330f, 0.662846603282066900f, + -0.748755220694604760f, + 0.662703019082037440f, -0.748882306173375030f, 0.662559410516312400f, + -0.749009364117883770f, + 0.662415777590171780f, -0.749136394523459260f, 0.662272120308896590f, + -0.749263397385431020f, + 0.662128438677768720f, -0.749390372699129560f, 0.661984732702071030f, + -0.749517320459886170f, + 0.661841002387086870f, -0.749644240663033480f, 0.661697247738101120f, + -0.749771133303904990f, + 0.661553468760399000f, -0.749897998377835220f, 0.661409665459266940f, + -0.750024835880159780f, + 0.661265837839992270f, -0.750151645806214960f, 0.661121985907862970f, + -0.750278428151338610f, + 0.660978109668168060f, -0.750405182910869220f, 0.660834209126197610f, + -0.750531910080146410f, + 0.660690284287242300f, -0.750658609654510590f, 0.660546335156593890f, + -0.750785281629303580f, + 0.660402361739545030f, -0.750911925999867890f, 0.660258364041389050f, + -0.751038542761547250f, + 0.660114342067420480f, -0.751165131909686370f, 0.659970295822934540f, + -0.751291693439630870f, + 0.659826225313227430f, -0.751418227346727360f, 0.659682130543596150f, + -0.751544733626323570f, + 0.659538011519338770f, -0.751671212273768430f, 0.659393868245753970f, + -0.751797663284411440f, + 0.659249700728141490f, -0.751924086653603550f, 0.659105508971802200f, + -0.752050482376696360f, + 0.658961292982037320f, -0.752176850449042700f, 0.658817052764149480f, + -0.752303190865996400f, + 0.658672788323441890f, -0.752429503622912390f, 0.658528499665218760f, + -0.752555788715146390f, + 0.658384186794785050f, -0.752682046138055230f, 0.658239849717446980f, + -0.752808275886996950f, + 0.658095488438511290f, -0.752934477957330150f, 0.657951102963285630f, + -0.753060652344415100f, + 0.657806693297078640f, -0.753186799043612410f, 0.657662259445200070f, + -0.753312918050284330f, + 0.657517801412960120f, -0.753439009359793580f, 0.657373319205670210f, + -0.753565072967504190f, + 0.657228812828642650f, -0.753691108868781210f, 0.657084282287190180f, + -0.753817117058990680f, + 0.656939727586627110f, -0.753943097533499640f, 0.656795148732268070f, + -0.754069050287676120f, + 0.656650545729429050f, -0.754194975316889170f, 0.656505918583426550f, + -0.754320872616508820f, + 0.656361267299578000f, -0.754446742181906330f, 0.656216591883202030f, + -0.754572584008453840f, + 0.656071892339617710f, -0.754698398091524390f, 0.655927168674145360f, + -0.754824184426492240f, + 0.655782420892106030f, -0.754949943008732640f, 0.655637648998821820f, + -0.755075673833621510f, + 0.655492852999615460f, -0.755201376896536550f, 0.655348032899810580f, + -0.755327052192855560f, + 0.655203188704731930f, -0.755452699717958140f, 0.655058320419704910f, + -0.755578319467224540f, + 0.654913428050056150f, -0.755703911436035880f, 0.654768511601112600f, + -0.755829475619774760f, + 0.654623571078202680f, -0.755955012013824310f, 0.654478606486655350f, + -0.756080520613569120f, + 0.654333617831800550f, -0.756206001414394540f, 0.654188605118969040f, + -0.756331454411686920f, + 0.654043568353492640f, -0.756456879600833630f, 0.653898507540703890f, + -0.756582276977223470f, + 0.653753422685936170f, -0.756707646536245670f, 0.653608313794523890f, + -0.756832988273290820f, + 0.653463180871802330f, -0.756958302183750490f, 0.653318023923107670f, + -0.757083588263017140f, + 0.653172842953776760f, -0.757208846506484460f, 0.653027637969147650f, + -0.757334076909547130f, + 0.652882408974558960f, -0.757459279467600720f, 0.652737155975350420f, + -0.757584454176041810f, + 0.652591878976862550f, -0.757709601030268080f, 0.652446577984436840f, + -0.757834720025678310f, + 0.652301253003415460f, -0.757959811157672300f, 0.652155904039141700f, + -0.758084874421650620f, + 0.652010531096959500f, -0.758209909813015280f, 0.651865134182214030f, + -0.758334917327168960f, + 0.651719713300251020f, -0.758459896959515320f, 0.651574268456417080f, + -0.758584848705459500f, + 0.651428799656059820f, -0.758709772560407390f, 0.651283306904527850f, + -0.758834668519765660f, + 0.651137790207170330f, -0.758959536578942440f, 0.650992249569337660f, + -0.759084376733346500f, + 0.650846684996380990f, -0.759209188978387960f, 0.650701096493652040f, + -0.759333973309477940f, + 0.650555484066503990f, -0.759458729722028210f, 0.650409847720290420f, + -0.759583458211452010f, + 0.650264187460365960f, -0.759708158773163440f, 0.650118503292086200f, + -0.759832831402577400f, + 0.649972795220807530f, -0.759957476095110330f, 0.649827063251887100f, + -0.760082092846179220f, + 0.649681307390683190f, -0.760206681651202420f, 0.649535527642554730f, + -0.760331242505599030f, + 0.649389724012861770f, -0.760455775404789260f, 0.649243896506965010f, + -0.760580280344194340f, + 0.649098045130226060f, -0.760704757319236920f, 0.648952169888007410f, + -0.760829206325340010f, + 0.648806270785672550f, -0.760953627357928040f, 0.648660347828585840f, + -0.761078020412426560f, + 0.648514401022112550f, -0.761202385484261780f, 0.648368430371618400f, + -0.761326722568861250f, + 0.648222435882470420f, -0.761451031661653510f, 0.648076417560036530f, + -0.761575312758068000f, + 0.647930375409685460f, -0.761699565853535270f, 0.647784309436786550f, + -0.761823790943486840f, + 0.647638219646710420f, -0.761947988023355390f, 0.647492106044828100f, + -0.762072157088574560f, + 0.647345968636512060f, -0.762196298134578900f, 0.647199807427135230f, + -0.762320411156804160f, + 0.647053622422071650f, -0.762444496150687100f, 0.646907413626696020f, + -0.762568553111665380f, + 0.646761181046383920f, -0.762692582035177870f, 0.646614924686512050f, + -0.762816582916664320f, + 0.646468644552457890f, -0.762940555751565720f, 0.646322340649599590f, + -0.763064500535323710f, + 0.646176012983316390f, -0.763188417263381270f, 0.646029661558988330f, + -0.763312305931182380f, + 0.645883286381996440f, -0.763436166534172010f, 0.645736887457722290f, + -0.763559999067796150f, + 0.645590464791548800f, -0.763683803527501870f, 0.645444018388859230f, + -0.763807579908737160f, + 0.645297548255038380f, -0.763931328206951090f, 0.645151054395471270f, + -0.764055048417593860f, + 0.645004536815544040f, -0.764178740536116670f, 0.644857995520643710f, + -0.764302404557971720f, + 0.644711430516158420f, -0.764426040478612070f, 0.644564841807476750f, + -0.764549648293492150f, + 0.644418229399988380f, -0.764673227998067140f, 0.644271593299083900f, + -0.764796779587793460f, + 0.644124933510154540f, -0.764920303058128410f, 0.643978250038592660f, + -0.765043798404530410f, + 0.643831542889791500f, -0.765167265622458960f, 0.643684812069144960f, + -0.765290704707374260f, + 0.643538057582047850f, -0.765414115654738160f, 0.643391279433895960f, + -0.765537498460013070f, + 0.643244477630085850f, -0.765660853118662390f, 0.643097652176015110f, + -0.765784179626150970f, + 0.642950803077082080f, -0.765907477977944230f, 0.642803930338686100f, + -0.766030748169509000f, + 0.642657033966226860f, -0.766153990196312810f, 0.642510113965105710f, + -0.766277204053824710f, + 0.642363170340724320f, -0.766400389737514120f, 0.642216203098485370f, + -0.766523547242852100f, + 0.642069212243792540f, -0.766646676565310380f, 0.641922197782050170f, + -0.766769777700361920f, + 0.641775159718663500f, -0.766892850643480670f, 0.641628098059038860f, + -0.767015895390141480f, + 0.641481012808583160f, -0.767138911935820400f, 0.641333903972704290f, + -0.767261900275994390f, + 0.641186771556811250f, -0.767384860406141620f, 0.641039615566313390f, + -0.767507792321741270f, + 0.640892436006621380f, -0.767630696018273270f, 0.640745232883146440f, + -0.767753571491219030f, + 0.640598006201301030f, -0.767876418736060610f, 0.640450755966498140f, + -0.767999237748281270f, + 0.640303482184151670f, -0.768122028523365310f, 0.640156184859676620f, + -0.768244791056798220f, + 0.640008863998488440f, -0.768367525344066270f, 0.639861519606004010f, + -0.768490231380656750f, + 0.639714151687640450f, -0.768612909162058270f, 0.639566760248816420f, + -0.768735558683760310f, + 0.639419345294950700f, -0.768858179941253270f, 0.639271906831463510f, + -0.768980772930028870f, + 0.639124444863775730f, -0.769103337645579590f, 0.638976959397309140f, + -0.769225874083399260f, + 0.638829450437486400f, -0.769348382238982280f, 0.638681917989730840f, + -0.769470862107824560f, + 0.638534362059466790f, -0.769593313685422940f, 0.638386782652119680f, + -0.769715736967275020f, + 0.638239179773115390f, -0.769838131948879840f, 0.638091553427880930f, + -0.769960498625737230f, + 0.637943903621844170f, -0.770082836993347900f, 0.637796230360433540f, + -0.770205147047214100f, + 0.637648533649078810f, -0.770327428782838770f, 0.637500813493210310f, + -0.770449682195725960f, + 0.637353069898259130f, -0.770571907281380700f, 0.637205302869657600f, + -0.770694104035309140f, + 0.637057512412838590f, -0.770816272453018430f, 0.636909698533235870f, + -0.770938412530016940f, + 0.636761861236284200f, -0.771060524261813710f, 0.636614000527419230f, + -0.771182607643919220f, + 0.636466116412077180f, -0.771304662671844720f, 0.636318208895695570f, + -0.771426689341102590f, + 0.636170277983712170f, -0.771548687647206300f, 0.636022323681566300f, + -0.771670657585670330f, + 0.635874345994697720f, -0.771792599152010150f, 0.635726344928547180f, + -0.771914512341742350f, + 0.635578320488556230f, -0.772036397150384410f, 0.635430272680167160f, + -0.772158253573455240f, + 0.635282201508823530f, -0.772280081606474320f, 0.635134106979969300f, + -0.772401881244962340f, + 0.634985989099049460f, -0.772523652484441330f, 0.634837847871510100f, + -0.772645395320433860f, + 0.634689683302797850f, -0.772767109748463740f, 0.634541495398360130f, + -0.772888795764056220f, + 0.634393284163645490f, -0.773010453362736990f, 0.634245049604103330f, + -0.773132082540033070f, + 0.634096791725183740f, -0.773253683291472590f, 0.633948510532337810f, + -0.773375255612584470f, + 0.633800206031017280f, -0.773496799498899050f, 0.633651878226674900f, + -0.773618314945947460f, + 0.633503527124764320f, -0.773739801949261840f, 0.633355152730740060f, + -0.773861260504375540f, + 0.633206755050057190f, -0.773982690606822790f, 0.633058334088172250f, + -0.774104092252138940f, + 0.632909889850541860f, -0.774225465435860570f, 0.632761422342624000f, + -0.774346810153525020f, + 0.632612931569877520f, -0.774468126400670860f, 0.632464417537761840f, + -0.774589414172837550f, + 0.632315880251737680f, -0.774710673465565550f, 0.632167319717266030f, + -0.774831904274396850f, + 0.632018735939809060f, -0.774953106594873820f, 0.631870128924829850f, + -0.775074280422540450f, + 0.631721498677792370f, -0.775195425752941310f, 0.631572845204161130f, + -0.775316542581622410f, + 0.631424168509401860f, -0.775437630904130430f, 0.631275468598980870f, + -0.775558690716013580f, + 0.631126745478365340f, -0.775679722012820540f, 0.630977999153023660f, + -0.775800724790101540f, + 0.630829229628424470f, -0.775921699043407580f, 0.630680436910038060f, + -0.776042644768290770f, + 0.630531621003334600f, -0.776163561960304340f, 0.630382781913785940f, + -0.776284450615002400f, + 0.630233919646864480f, -0.776405310727940390f, 0.630085034208043290f, + -0.776526142294674430f, + 0.629936125602796550f, -0.776646945310762060f, 0.629787193836599200f, + -0.776767719771761510f, + 0.629638238914927100f, -0.776888465673232440f, 0.629489260843256740f, + -0.777009183010735290f, + 0.629340259627065750f, -0.777129871779831620f, 0.629191235271832410f, + -0.777250531976084070f, + 0.629042187783036000f, -0.777371163595056200f, 0.628893117166156480f, + -0.777491766632312900f, + 0.628744023426674790f, -0.777612341083419920f, 0.628594906570072660f, + -0.777732886943944050f, + 0.628445766601832710f, -0.777853404209453040f, 0.628296603527438440f, + -0.777973892875515990f, + 0.628147417352374120f, -0.778094352937702790f, 0.627998208082124810f, + -0.778214784391584420f, + 0.627848975722176570f, -0.778335187232733090f, 0.627699720278016240f, + -0.778455561456721900f, + 0.627550441755131530f, -0.778575907059124940f, 0.627401140159011160f, + -0.778696224035517530f, + 0.627251815495144190f, -0.778816512381475870f, 0.627102467769021010f, + -0.778936772092577500f, + 0.626953096986132770f, -0.779057003164400630f, 0.626803703151971310f, + -0.779177205592524680f, + 0.626654286272029460f, -0.779297379372530300f, 0.626504846351800930f, + -0.779417524499998900f, + 0.626355383396779990f, -0.779537640970513150f, 0.626205897412462130f, + -0.779657728779656780f, + 0.626056388404343520f, -0.779777787923014440f, 0.625906856377921210f, + -0.779897818396171890f, + 0.625757301338692900f, -0.780017820194715990f, 0.625607723292157410f, + -0.780137793314234500f, + 0.625458122243814360f, -0.780257737750316590f, 0.625308498199164010f, + -0.780377653498552040f, + 0.625158851163707730f, -0.780497540554531910f, 0.625009181142947460f, + -0.780617398913848290f, + 0.624859488142386450f, -0.780737228572094380f, 0.624709772167528100f, + -0.780857029524864470f, + 0.624560033223877320f, -0.780976801767753750f, 0.624410271316939380f, + -0.781096545296358410f, + 0.624260486452220650f, -0.781216260106276090f, 0.624110678635228510f, + -0.781335946193104870f, + 0.623960847871470770f, -0.781455603552444480f, 0.623810994166456130f, + -0.781575232179895550f, + 0.623661117525694640f, -0.781694832071059390f, 0.623511217954696550f, + -0.781814403221538830f, + 0.623361295458973340f, -0.781933945626937630f, 0.623211350044037270f, + -0.782053459282860300f, + 0.623061381715401370f, -0.782172944184912900f, 0.622911390478579460f, + -0.782292400328702400f, + 0.622761376339086460f, -0.782411827709836420f, 0.622611339302437730f, + -0.782531226323924240f, + 0.622461279374150080f, -0.782650596166575730f, 0.622311196559740320f, + -0.782769937233402050f, + 0.622161090864726930f, -0.782889249520015480f, 0.622010962294628600f, + -0.783008533022029110f, + 0.621860810854965360f, -0.783127787735057310f, 0.621710636551257690f, + -0.783247013654715380f, + 0.621560439389027270f, -0.783366210776619720f, 0.621410219373796150f, + -0.783485379096387820f, + 0.621259976511087660f, -0.783604518609638200f, 0.621109710806425740f, + -0.783723629311990470f, + 0.620959422265335180f, -0.783842711199065230f, 0.620809110893341900f, + -0.783961764266484010f, + 0.620658776695972140f, -0.784080788509869950f, 0.620508419678753360f, + -0.784199783924846570f, + 0.620358039847213830f, -0.784318750507038920f, 0.620207637206882430f, + -0.784437688252072720f, + 0.620057211763289210f, -0.784556597155575240f, 0.619906763521964830f, + -0.784675477213174320f, + 0.619756292488440660f, -0.784794328420499230f, 0.619605798668249390f, + -0.784913150773180020f, + 0.619455282066924020f, -0.785031944266848080f, 0.619304742689998690f, + -0.785150708897135560f, + 0.619154180543008410f, -0.785269444659675850f, 0.619003595631488770f, + -0.785388151550103550f, + 0.618852987960976320f, -0.785506829564053930f, 0.618702357537008640f, + -0.785625478697163700f, + 0.618551704365123860f, -0.785744098945070360f, 0.618401028450860980f, + -0.785862690303412600f, + 0.618250329799760250f, -0.785981252767830150f, 0.618099608417362110f, + -0.786099786333963820f, + 0.617948864309208260f, -0.786218290997455550f, 0.617798097480841140f, + -0.786336766753948260f, + 0.617647307937803980f, -0.786455213599085770f, 0.617496495685640910f, + -0.786573631528513230f, + 0.617345660729896940f, -0.786692020537876680f, 0.617194803076117630f, + -0.786810380622823490f, + 0.617043922729849760f, -0.786928711779001700f, 0.616893019696640790f, + -0.787047014002060790f, + 0.616742093982038830f, -0.787165287287650890f, 0.616591145591593230f, + -0.787283531631423620f, + 0.616440174530853650f, -0.787401747029031320f, 0.616289180805370980f, + -0.787519933476127810f, + 0.616138164420696910f, -0.787638090968367450f, 0.615987125382383870f, + -0.787756219501405950f, + 0.615836063695985090f, -0.787874319070900110f, 0.615684979367054570f, + -0.787992389672507950f, + 0.615533872401147430f, -0.788110431301888070f, 0.615382742803819330f, + -0.788228443954700490f, + 0.615231590580626820f, -0.788346427626606230f, 0.615080415737127460f, + -0.788464382313267430f, + 0.614929218278879590f, -0.788582308010347120f, 0.614777998211442190f, + -0.788700204713509660f, + 0.614626755540375050f, -0.788818072418420170f, 0.614475490271239160f, + -0.788935911120745130f, + 0.614324202409595950f, -0.789053720816151880f, 0.614172891961007990f, + -0.789171501500308790f, + 0.614021558931038490f, -0.789289253168885650f, 0.613870203325251440f, + -0.789406975817552810f, + 0.613718825149211830f, -0.789524669441982190f, 0.613567424408485330f, + -0.789642334037846340f, + 0.613416001108638590f, -0.789759969600819070f, 0.613264555255239150f, + -0.789877576126575280f, + 0.613113086853854910f, -0.789995153610791090f, 0.612961595910055170f, + -0.790112702049143300f, + 0.612810082429409710f, -0.790230221437310030f, 0.612658546417489290f, + -0.790347711770970520f, + 0.612506987879865570f, -0.790465173045804880f, 0.612355406822110760f, + -0.790582605257494460f, + 0.612203803249798060f, -0.790700008401721610f, 0.612052177168501580f, + -0.790817382474169660f, + 0.611900528583796070f, -0.790934727470523290f, 0.611748857501257400f, + -0.791052043386467950f, + 0.611597163926462020f, -0.791169330217690090f, 0.611445447864987110f, + -0.791286587959877720f, + 0.611293709322411010f, -0.791403816608719500f, 0.611141948304312570f, + -0.791521016159905220f, + 0.610990164816271770f, -0.791638186609125770f, 0.610838358863869280f, + -0.791755327952073150f, + 0.610686530452686280f, -0.791872440184440470f, 0.610534679588305320f, + -0.791989523301921850f, + 0.610382806276309480f, -0.792106577300212390f, 0.610230910522282620f, + -0.792223602175008310f, + 0.610078992331809620f, -0.792340597922007060f, 0.609927051710476230f, + -0.792457564536906970f, + 0.609775088663868430f, -0.792574502015407580f, 0.609623103197573730f, + -0.792691410353209450f, + 0.609471095317180240f, -0.792808289546014120f, 0.609319065028276820f, + -0.792925139589524260f, + 0.609167012336453210f, -0.793041960479443640f, 0.609014937247299940f, + -0.793158752211477140f, + 0.608862839766408200f, -0.793275514781330630f, 0.608710719899370420f, + -0.793392248184711100f, + 0.608558577651779450f, -0.793508952417326660f, 0.608406413029229260f, + -0.793625627474886190f, + 0.608254226037314490f, -0.793742273353100100f, 0.608102016681630550f, + -0.793858890047679620f, + 0.607949784967773740f, -0.793975477554337170f, 0.607797530901341140f, + -0.794092035868785960f, + 0.607645254487930830f, -0.794208564986740640f, 0.607492955733141660f, + -0.794325064903916520f, + 0.607340634642572930f, -0.794441535616030590f, 0.607188291221825160f, + -0.794557977118800270f, + 0.607035925476499760f, -0.794674389407944550f, 0.606883537412198580f, + -0.794790772479183170f, + 0.606731127034524480f, -0.794907126328237010f, 0.606578694349081400f, + -0.795023450950828050f, + 0.606426239361473550f, -0.795139746342679590f, 0.606273762077306430f, + -0.795256012499515500f, + 0.606121262502186230f, -0.795372249417061190f, 0.605968740641719790f, + -0.795488457091042990f, + 0.605816196501515080f, -0.795604635517188070f, 0.605663630087180490f, + -0.795720784691225090f, + 0.605511041404325550f, -0.795836904608883460f, 0.605358430458560530f, + -0.795952995265893910f, + 0.605205797255496500f, -0.796069056657987990f, 0.605053141800745430f, + -0.796185088780898440f, + 0.604900464099919930f, -0.796301091630359110f, 0.604747764158633410f, + -0.796417065202104980f, + 0.604595041982500360f, -0.796533009491872000f, 0.604442297577135970f, + -0.796648924495397150f, + 0.604289530948156070f, -0.796764810208418720f, 0.604136742101177630f, + -0.796880666626675780f, + 0.603983931041818020f, -0.796996493745908750f, 0.603831097775695880f, + -0.797112291561858920f, + 0.603678242308430370f, -0.797228060070268700f, 0.603525364645641550f, + -0.797343799266881700f, + 0.603372464792950370f, -0.797459509147442460f, 0.603219542755978440f, + -0.797575189707696590f, + 0.603066598540348280f, -0.797690840943391040f, 0.602913632151683140f, + -0.797806462850273570f, + 0.602760643595607220f, -0.797922055424093000f, 0.602607632877745550f, + -0.798037618660599410f, + 0.602454600003723860f, -0.798153152555543750f, 0.602301544979168550f, + -0.798268657104678310f, + 0.602148467809707320f, -0.798384132303756380f, 0.601995368500968130f, + -0.798499578148532010f, + 0.601842247058580030f, -0.798614994634760820f, 0.601689103488173060f, + -0.798730381758199210f, + 0.601535937795377730f, -0.798845739514604580f, 0.601382749985825420f, + -0.798961067899735760f, + 0.601229540065148620f, -0.799076366909352350f, 0.601076308038980160f, + -0.799191636539215210f, + 0.600923053912954090f, -0.799306876785086160f, 0.600769777692705230f, + -0.799422087642728040f, + 0.600616479383868970f, -0.799537269107905010f, 0.600463158992081690f, + -0.799652421176382130f, + 0.600309816522980430f, -0.799767543843925680f, 0.600156451982203350f, + -0.799882637106302810f, + 0.600003065375389060f, -0.799997700959281910f, 0.599849656708177360f, + -0.800112735398632370f, + 0.599696225986208310f, -0.800227740420124790f, 0.599542773215123390f, + -0.800342716019530660f, + 0.599389298400564540f, -0.800457662192622710f, 0.599235801548174570f, + -0.800572578935174750f, + 0.599082282663597310f, -0.800687466242961500f, 0.598928741752476900f, + -0.800802324111759110f, + 0.598775178820458720f, -0.800917152537344300f, 0.598621593873188920f, + -0.801031951515495330f, + 0.598467986916314310f, -0.801146721041991250f, 0.598314357955482600f, + -0.801261461112612540f, + 0.598160706996342380f, -0.801376171723140130f, 0.598007034044542700f, + -0.801490852869356840f, + 0.597853339105733910f, -0.801605504547046040f, 0.597699622185566830f, + -0.801720126751992330f, + 0.597545883289693270f, -0.801834719479981310f, 0.597392122423765710f, + -0.801949282726799660f, + 0.597238339593437530f, -0.802063816488235440f, 0.597084534804362740f, + -0.802178320760077450f, + 0.596930708062196500f, -0.802292795538115720f, 0.596776859372594500f, + -0.802407240818141300f, + 0.596622988741213330f, -0.802521656595946320f, 0.596469096173710360f, + -0.802636042867324150f, + 0.596315181675743820f, -0.802750399628069160f, 0.596161245252972540f, + -0.802864726873976590f, + 0.596007286911056530f, -0.802979024600843140f, 0.595853306655656390f, + -0.803093292804466400f, + 0.595699304492433470f, -0.803207531480644830f, 0.595545280427049790f, + -0.803321740625178470f, + 0.595391234465168730f, -0.803435920233868120f, 0.595237166612453850f, + -0.803550070302515570f, + 0.595083076874569960f, -0.803664190826924090f, 0.594928965257182420f, + -0.803778281802897570f, + 0.594774831765957580f, -0.803892343226241260f, 0.594620676406562240f, + -0.804006375092761520f, + 0.594466499184664540f, -0.804120377398265700f, 0.594312300105932830f, + -0.804234350138562260f, + 0.594158079176036800f, -0.804348293309460780f, 0.594003836400646690f, + -0.804462206906771840f, + 0.593849571785433630f, -0.804576090926307000f, 0.593695285336069300f, + -0.804689945363879500f, + 0.593540977058226390f, -0.804803770215302810f, 0.593386646957578480f, + -0.804917565476392150f, + 0.593232295039799800f, -0.805031331142963660f, 0.593077921310565580f, + -0.805145067210834120f, + 0.592923525775551410f, -0.805258773675822210f, 0.592769108440434070f, + -0.805372450533747060f, + 0.592614669310891130f, -0.805486097780429120f, 0.592460208392600940f, + -0.805599715411689950f, + 0.592305725691242400f, -0.805713303423352120f, 0.592151221212495640f, + -0.805826861811239300f, + 0.591996694962040990f, -0.805940390571176280f, 0.591842146945560250f, + -0.806053889698988950f, + 0.591687577168735550f, -0.806167359190504310f, 0.591532985637249990f, + -0.806280799041550370f, + 0.591378372356787580f, -0.806394209247956240f, 0.591223737333032910f, + -0.806507589805552260f, + 0.591069080571671510f, -0.806620940710169650f, 0.590914402078389520f, + -0.806734261957640750f, + 0.590759701858874280f, -0.806847553543799220f, 0.590604979918813440f, + -0.806960815464479620f, + 0.590450236263895920f, -0.807074047715517610f, 0.590295470899810940f, + -0.807187250292749850f, + 0.590140683832248940f, -0.807300423192014450f, 0.589985875066900920f, + -0.807413566409150190f, + 0.589831044609458900f, -0.807526679939997160f, 0.589676192465615420f, + -0.807639763780396370f, + 0.589521318641063940f, -0.807752817926190360f, 0.589366423141498790f, + -0.807865842373222120f, + 0.589211505972615070f, -0.807978837117336310f, 0.589056567140108460f, + -0.808091802154378260f, + 0.588901606649675840f, -0.808204737480194720f, 0.588746624507014650f, + -0.808317643090633250f, + 0.588591620717822890f, -0.808430518981542720f, 0.588436595287799900f, + -0.808543365148773010f, + 0.588281548222645330f, -0.808656181588174980f, 0.588126479528059850f, + -0.808768968295600850f, + 0.587971389209745120f, -0.808881725266903610f, 0.587816277273403020f, + -0.808994452497937560f, + 0.587661143724736770f, -0.809107149984558130f, 0.587505988569450020f, + -0.809219817722621750f, + 0.587350811813247660f, -0.809332455707985840f, 0.587195613461834910f, + -0.809445063936509170f, + 0.587040393520918080f, -0.809557642404051260f, 0.586885151996203950f, + -0.809670191106473090f, + 0.586729888893400500f, -0.809782710039636420f, 0.586574604218216280f, + -0.809895199199404450f, + 0.586419297976360500f, -0.810007658581641140f, 0.586263970173543700f, + -0.810120088182211600f, + 0.586108620815476430f, -0.810232487996982330f, 0.585953249907870680f, + -0.810344858021820550f, + 0.585797857456438860f, -0.810457198252594770f, 0.585642443466894420f, + -0.810569508685174630f, + 0.585487007944951450f, -0.810681789315430670f, 0.585331550896324940f, + -0.810794040139234730f, + 0.585176072326730410f, -0.810906261152459670f, 0.585020572241884530f, + -0.811018452350979470f, + 0.584865050647504490f, -0.811130613730669190f, 0.584709507549308500f, + -0.811242745287404810f, + 0.584553942953015330f, -0.811354847017063730f, 0.584398356864344710f, + -0.811466918915524250f, + 0.584242749289016980f, -0.811578960978665890f, 0.584087120232753550f, + -0.811690973202369050f, + 0.583931469701276300f, -0.811802955582515360f, 0.583775797700308070f, + -0.811914908114987680f, + 0.583620104235572760f, -0.812026830795669730f, 0.583464389312794430f, + -0.812138723620446480f, + 0.583308652937698290f, -0.812250586585203880f, 0.583152895116010540f, + -0.812362419685829120f, + 0.582997115853457700f, -0.812474222918210480f, 0.582841315155767650f, + -0.812585996278237020f, + 0.582685493028668460f, -0.812697739761799490f, 0.582529649477889320f, + -0.812809453364789160f, + 0.582373784509160220f, -0.812921137083098770f, 0.582217898128211790f, + -0.813032790912621930f, + 0.582061990340775550f, -0.813144414849253590f, 0.581906061152583920f, + -0.813256008888889380f, + 0.581750110569369760f, -0.813367573027426570f, 0.581594138596866930f, + -0.813479107260763220f, + 0.581438145240810280f, -0.813590611584798510f, 0.581282130506935110f, + -0.813702085995432700f, + 0.581126094400977620f, -0.813813530488567190f, 0.580970036928674880f, + -0.813924945060104490f, + 0.580813958095764530f, -0.814036329705948300f, 0.580657857907985410f, + -0.814147684422003360f, + 0.580501736371076600f, -0.814259009204175270f, 0.580345593490778300f, + -0.814370304048371070f, + 0.580189429272831680f, -0.814481568950498610f, 0.580033243722978150f, + -0.814592803906467270f, + 0.579877036846960350f, -0.814704008912187080f, 0.579720808650521560f, + -0.814815183963569330f, + 0.579564559139405740f, -0.814926329056526620f, 0.579408288319357980f, + -0.815037444186972220f, + 0.579251996196123550f, -0.815148529350820830f, 0.579095682775449210f, + -0.815259584543988280f, + 0.578939348063081890f, -0.815370609762391290f, 0.578782992064769690f, + -0.815481605001947770f, + 0.578626614786261430f, -0.815592570258576680f, 0.578470216233306740f, + -0.815703505528198260f, + 0.578313796411655590f, -0.815814410806733780f, 0.578157355327059360f, + -0.815925286090105390f, + 0.578000892985269910f, -0.816036131374236700f, 0.577844409392039850f, + -0.816146946655052160f, + 0.577687904553122800f, -0.816257731928477390f, 0.577531378474272830f, + -0.816368487190439200f, + 0.577374831161244880f, -0.816479212436865390f, 0.577218262619794920f, + -0.816589907663684890f, + 0.577061672855679550f, -0.816700572866827850f, 0.576905061874655960f, + -0.816811208042225290f, + 0.576748429682482520f, -0.816921813185809480f, 0.576591776284917870f, + -0.817032388293513880f, + 0.576435101687721830f, -0.817142933361272970f, 0.576278405896654910f, + -0.817253448385022230f, + 0.576121688917478390f, -0.817363933360698460f, 0.575964950755954330f, + -0.817474388284239240f, + 0.575808191417845340f, -0.817584813151583710f, 0.575651410908915250f, + -0.817695207958671680f, + 0.575494609234928230f, -0.817805572701444270f, 0.575337786401649560f, + -0.817915907375843740f, + 0.575180942414845190f, -0.818026211977813440f, 0.575024077280281820f, + -0.818136486503297620f, + 0.574867191003726740f, -0.818246730948241960f, 0.574710283590948450f, + -0.818356945308593150f, + 0.574553355047715760f, -0.818467129580298660f, 0.574396405379798750f, + -0.818577283759307490f, + 0.574239434592967890f, -0.818687407841569570f, 0.574082442692994470f, + -0.818797501823036010f, + 0.573925429685650750f, -0.818907565699658950f, 0.573768395576709560f, + -0.819017599467391500f, + 0.573611340371944610f, -0.819127603122188240f, 0.573454264077130400f, + -0.819237576660004520f, + 0.573297166698042320f, -0.819347520076796900f, 0.573140048240456060f, + -0.819457433368523280f, + 0.572982908710148680f, -0.819567316531142230f, 0.572825748112897550f, + -0.819677169560613760f, + 0.572668566454481160f, -0.819786992452898990f, 0.572511363740678790f, + -0.819896785203959810f, + 0.572354139977270030f, -0.820006547809759680f, 0.572196895170035580f, + -0.820116280266262710f, + 0.572039629324757050f, -0.820225982569434690f, 0.571882342447216590f, + -0.820335654715241840f, + 0.571725034543197120f, -0.820445296699652050f, 0.571567705618482580f, + -0.820554908518633890f, + 0.571410355678857340f, -0.820664490168157460f, 0.571252984730106660f, + -0.820774041644193650f, + 0.571095592778016690f, -0.820883562942714580f, 0.570938179828374360f, + -0.820993054059693470f, + 0.570780745886967370f, -0.821102514991104650f, 0.570623290959583860f, + -0.821211945732923550f, + 0.570465815052012990f, -0.821321346281126740f, 0.570308318170045010f, + -0.821430716631691760f, + 0.570150800319470300f, -0.821540056780597610f, 0.569993261506080650f, + -0.821649366723823830f, + 0.569835701735668110f, -0.821758646457351640f, 0.569678121014025710f, + -0.821867895977163140f, + 0.569520519346947250f, -0.821977115279241550f, 0.569362896740227330f, + -0.822086304359571090f, + 0.569205253199661200f, -0.822195463214137170f, 0.569047588731045220f, + -0.822304591838926350f, + 0.568889903340175970f, -0.822413690229926390f, 0.568732197032851160f, + -0.822522758383125940f, + 0.568574469814869250f, -0.822631796294514990f, 0.568416721692029390f, + -0.822740803960084420f, + 0.568258952670131490f, -0.822849781375826320f, 0.568101162754976570f, + -0.822958728537734000f, + 0.567943351952365670f, -0.823067645441801670f, 0.567785520268101250f, + -0.823176532084024860f, + 0.567627667707986230f, -0.823285388460400110f, 0.567469794277824620f, + -0.823394214566925080f, + 0.567311899983420800f, -0.823503010399598390f, 0.567153984830580100f, + -0.823611775954420260f, + 0.566996048825108680f, -0.823720511227391320f, 0.566838091972813320f, + -0.823829216214513990f, + 0.566680114279501710f, -0.823937890911791370f, 0.566522115750982100f, + -0.824046535315227760f, + 0.566364096393063950f, -0.824155149420828570f, 0.566206056211556840f, + -0.824263733224600450f, + 0.566047995212271560f, -0.824372286722551250f, 0.565889913401019570f, + -0.824480809910689500f, + 0.565731810783613230f, -0.824589302785025290f, 0.565573687365865440f, + -0.824697765341569470f, + 0.565415543153589770f, -0.824806197576334330f, 0.565257378152600910f, + -0.824914599485333080f, + 0.565099192368714090f, -0.825022971064580220f, 0.564940985807745320f, + -0.825131312310090960f, + 0.564782758475511400f, -0.825239623217882130f, 0.564624510377830120f, + -0.825347903783971380f, + 0.564466241520519500f, -0.825456154004377440f, 0.564307951909398750f, + -0.825564373875120490f, + 0.564149641550287680f, -0.825672563392221390f, 0.563991310449007080f, + -0.825780722551702430f, + 0.563832958611378170f, -0.825888851349586780f, 0.563674586043223180f, + -0.825996949781898970f, + 0.563516192750364910f, -0.826105017844664610f, 0.563357778738627020f, + -0.826213055533910110f, + 0.563199344013834090f, -0.826321062845663420f, 0.563040888581811230f, + -0.826429039775953390f, + 0.562882412448384550f, -0.826536986320809960f, 0.562723915619380400f, + -0.826644902476264210f, + 0.562565398100626560f, -0.826752788238348520f, 0.562406859897951140f, + -0.826860643603096080f, + 0.562248301017183150f, -0.826968468566541490f, 0.562089721464152480f, + -0.827076263124720270f, + 0.561931121244689470f, -0.827184027273669020f, 0.561772500364625450f, + -0.827291761009425810f, + 0.561613858829792420f, -0.827399464328029350f, 0.561455196646023280f, + -0.827507137225519830f, + 0.561296513819151470f, -0.827614779697938400f, 0.561137810355011530f, + -0.827722391741327220f, + 0.560979086259438260f, -0.827829973351729810f, 0.560820341538267540f, + -0.827937524525190870f, + 0.560661576197336030f, -0.828045045257755800f, 0.560502790242481060f, + -0.828152535545471410f, + 0.560343983679540860f, -0.828259995384385550f, 0.560185156514354080f, + -0.828367424770547480f, + 0.560026308752760380f, -0.828474823700007130f, 0.559867440400600320f, + -0.828582192168815790f, + 0.559708551463714790f, -0.828689530173025710f, 0.559549641947945870f, + -0.828796837708690610f, + 0.559390711859136140f, -0.828904114771864870f, 0.559231761203129010f, + -0.829011361358604430f, + 0.559072789985768480f, -0.829118577464965980f, 0.558913798212899770f, + -0.829225763087007570f, + 0.558754785890368310f, -0.829332918220788250f, 0.558595753024020760f, + -0.829440042862368170f, + 0.558436699619704100f, -0.829547137007808800f, 0.558277625683266330f, + -0.829654200653172640f, + 0.558118531220556100f, -0.829761233794523050f, 0.557959416237422960f, + -0.829868236427924840f, + 0.557800280739717100f, -0.829975208549443840f, 0.557641124733289420f, + -0.830082150155146970f, + 0.557481948223991660f, -0.830189061241102370f, 0.557322751217676160f, + -0.830295941803379070f, + 0.557163533720196340f, -0.830402791838047550f, 0.557004295737406060f, + -0.830509611341179070f, + 0.556845037275160100f, -0.830616400308846200f, 0.556685758339313890f, + -0.830723158737122880f, + 0.556526458935723720f, -0.830829886622083570f, 0.556367139070246490f, + -0.830936583959804410f, + 0.556207798748739930f, -0.831043250746362320f, 0.556048437977062720f, + -0.831149886977835430f, + 0.555889056761073920f, -0.831256492650303210f, 0.555729655106633520f, + -0.831363067759845920f, + 0.555570233019602290f, -0.831469612302545240f, 0.555410790505841740f, + -0.831576126274483630f, + 0.555251327571214090f, -0.831682609671745120f, 0.555091844221582420f, + -0.831789062490414400f, + 0.554932340462810370f, -0.831895484726577590f, 0.554772816300762580f, + -0.832001876376321840f, + 0.554613271741304040f, -0.832108237435735480f, 0.554453706790301040f, + -0.832214567900907980f, + 0.554294121453620110f, -0.832320867767929680f, 0.554134515737128910f, + -0.832427137032892280f, + 0.553974889646695610f, -0.832533375691888680f, 0.553815243188189090f, + -0.832639583741012770f, + 0.553655576367479310f, -0.832745761176359460f, 0.553495889190436570f, + -0.832851907994024980f, + 0.553336181662932410f, -0.832958024190106670f, 0.553176453790838460f, + -0.833064109760702890f, + 0.553016705580027580f, -0.833170164701913190f, 0.552856937036373290f, + -0.833276189009838240f, + 0.552697148165749770f, -0.833382182680579730f, 0.552537338974032120f, + -0.833488145710240770f, + 0.552377509467096070f, -0.833594078094925140f, 0.552217659650817930f, + -0.833699979830738290f, + 0.552057789531074980f, -0.833805850913786340f, 0.551897899113745320f, + -0.833911691340176730f, + 0.551737988404707450f, -0.834017501106018130f, 0.551578057409841000f, + -0.834123280207419990f, + 0.551418106135026060f, -0.834229028640493420f, 0.551258134586143700f, + -0.834334746401350080f, + 0.551098142769075430f, -0.834440433486103190f, 0.550938130689703880f, + -0.834546089890866760f, + 0.550778098353912230f, -0.834651715611756330f, 0.550618045767584330f, + -0.834757310644888230f, + 0.550457972936604810f, -0.834862874986380010f, 0.550297879866859190f, + -0.834968408632350450f, + 0.550137766564233630f, -0.835073911578919300f, 0.549977633034615000f, + -0.835179383822207580f, + 0.549817479283891020f, -0.835284825358337370f, 0.549657305317949980f, + -0.835390236183431780f, + 0.549497111142680960f, -0.835495616293615350f, 0.549336896763974010f, + -0.835600965685013410f, + 0.549176662187719770f, -0.835706284353752600f, 0.549016407419809390f, + -0.835811572295960590f, + 0.548856132466135290f, -0.835916829507766360f, 0.548695837332590090f, + -0.836022055985299880f, + 0.548535522025067390f, -0.836127251724692160f, 0.548375186549461600f, + -0.836232416722075600f, + 0.548214830911667780f, -0.836337550973583530f, 0.548054455117581880f, + -0.836442654475350380f, + 0.547894059173100190f, -0.836547727223511890f, 0.547733643084120200f, + -0.836652769214204950f, + 0.547573206856539870f, -0.836757780443567190f, 0.547412750496257930f, + -0.836862760907737810f, + 0.547252274009174090f, -0.836967710602857020f, 0.547091777401188530f, + -0.837072629525066000f, + 0.546931260678202190f, -0.837177517670507190f, 0.546770723846116800f, + -0.837282375035324320f, + 0.546610166910834860f, -0.837387201615661940f, 0.546449589878259760f, + -0.837491997407665890f, + 0.546288992754295210f, -0.837596762407483040f, 0.546128375544846060f, + -0.837701496611261700f, + 0.545967738255817680f, -0.837806200015150940f, 0.545807080893116140f, + -0.837910872615301060f, + 0.545646403462648590f, -0.838015514407863700f, 0.545485705970322530f, + -0.838120125388991500f, + 0.545324988422046460f, -0.838224705554837970f, 0.545164250823729320f, + -0.838329254901558300f, + 0.545003493181281160f, -0.838433773425308340f, 0.544842715500612470f, + -0.838538261122245170f, + 0.544681917787634530f, -0.838642717988527300f, 0.544521100048259710f, + -0.838747144020313920f, + 0.544360262288400400f, -0.838851539213765760f, 0.544199404513970420f, + -0.838955903565044350f, + 0.544038526730883930f, -0.839060237070312630f, 0.543877628945055980f, + -0.839164539725734570f, + 0.543716711162402390f, -0.839268811527475230f, 0.543555773388839650f, + -0.839373052471700690f, + 0.543394815630284800f, -0.839477262554578550f, 0.543233837892656000f, + -0.839581441772277120f, + 0.543072840181871850f, -0.839685590120966110f, 0.542911822503851730f, + -0.839789707596816260f, + 0.542750784864516000f, -0.839893794195999410f, 0.542589727269785270f, + -0.839997849914688730f, + 0.542428649725581360f, -0.840101874749058400f, 0.542267552237826520f, + -0.840205868695283580f, + 0.542106434812444030f, -0.840309831749540770f, 0.541945297455357470f, + -0.840413763908007480f, + 0.541784140172491660f, -0.840517665166862440f, 0.541622962969771640f, + -0.840621535522285690f, + 0.541461765853123560f, -0.840725374970458070f, 0.541300548828474120f, + -0.840829183507561640f, + 0.541139311901750910f, -0.840932961129779670f, 0.540978055078882190f, + -0.841036707833296650f, + 0.540816778365796670f, -0.841140423614298080f, 0.540655481768424260f, + -0.841244108468970580f, + 0.540494165292695230f, -0.841347762393501950f, 0.540332828944540820f, + -0.841451385384081260f, + 0.540171472729892970f, -0.841554977436898330f, 0.540010096654684020f, + -0.841658538548144760f, + 0.539848700724847700f, -0.841762068714012490f, 0.539687284946317570f, + -0.841865567930695340f, + 0.539525849325029010f, -0.841969036194387680f, 0.539364393866917150f, + -0.842072473501285450f, + 0.539202918577918240f, -0.842175879847585570f, 0.539041423463969550f, + -0.842279255229485880f, + 0.538879908531008420f, -0.842382599643185960f, 0.538718373784973670f, + -0.842485913084885630f, + 0.538556819231804210f, -0.842589195550786600f, 0.538395244877439950f, + -0.842692447037091560f, + 0.538233650727821700f, -0.842795667540004120f, 0.538072036788890600f, + -0.842898857055729310f, + 0.537910403066588990f, -0.843002015580472830f, 0.537748749566859470f, + -0.843105143110442050f, + 0.537587076295645510f, -0.843208239641845440f, 0.537425383258891660f, + -0.843311305170892030f, + 0.537263670462542530f, -0.843414339693792760f, 0.537101937912544240f, + -0.843517343206759080f, + 0.536940185614843020f, -0.843620315706004040f, 0.536778413575385920f, + -0.843723257187741550f, + 0.536616621800121150f, -0.843826167648186740f, 0.536454810294997090f, + -0.843929047083555870f, + 0.536292979065963180f, -0.844031895490066410f, 0.536131128118969350f, + -0.844134712863936930f, + 0.535969257459966710f, -0.844237499201387020f, 0.535807367094906620f, + -0.844340254498637590f, + 0.535645457029741090f, -0.844442978751910660f, 0.535483527270423370f, + -0.844545671957429240f, + 0.535321577822907010f, -0.844648334111417820f, 0.535159608693146720f, + -0.844750965210101510f, + 0.534997619887097260f, -0.844853565249707010f, 0.534835611410714670f, + -0.844956134226462100f, + 0.534673583269955510f, -0.845058672136595470f, 0.534511535470777010f, + -0.845161178976337140f, + 0.534349468019137520f, -0.845263654741918220f, 0.534187380920995600f, + -0.845366099429570970f, + 0.534025274182310380f, -0.845468513035528830f, 0.533863147809042650f, + -0.845570895556026270f, + 0.533701001807152960f, -0.845673246987299070f, 0.533538836182603120f, + -0.845775567325583900f, + 0.533376650941355560f, -0.845877856567118890f, 0.533214446089372960f, + -0.845980114708143270f, + 0.533052221632619670f, -0.846082341744896940f, 0.532889977577059690f, + -0.846184537673621670f, + 0.532727713928658810f, -0.846286702490559710f, 0.532565430693382580f, + -0.846388836191954930f, + 0.532403127877198010f, -0.846490938774052020f, 0.532240805486072330f, + -0.846593010233097190f, + 0.532078463525973540f, -0.846695050565337450f, 0.531916102002870760f, + -0.846797059767020910f, + 0.531753720922733320f, -0.846899037834397350f, 0.531591320291531780f, + -0.847000984763716880f, + 0.531428900115236910f, -0.847102900551231500f, 0.531266460399820390f, + -0.847204785193193980f, + 0.531104001151255000f, -0.847306638685858320f, 0.530941522375513510f, + -0.847408461025479730f, + 0.530779024078570250f, -0.847510252208314330f, 0.530616506266399450f, + -0.847612012230619660f, + 0.530453968944976320f, -0.847713741088654270f, 0.530291412120277420f, + -0.847815438778677930f, + 0.530128835798278850f, -0.847917105296951410f, 0.529966239984958620f, + -0.848018740639736810f, + 0.529803624686294830f, -0.848120344803297120f, 0.529640989908265910f, + -0.848221917783896990f, + 0.529478335656852090f, -0.848323459577801530f, 0.529315661938033140f, + -0.848424970181277600f, + 0.529152968757790720f, -0.848526449590592650f, 0.528990256122106040f, + -0.848627897802015860f, + 0.528827524036961980f, -0.848729314811817010f, 0.528664772508341540f, + -0.848830700616267530f, + 0.528502001542228480f, -0.848932055211639610f, 0.528339211144607690f, + -0.849033378594206690f, + 0.528176401321464370f, -0.849134670760243630f, 0.528013572078784740f, + -0.849235931706025960f, + 0.527850723422555460f, -0.849337161427830670f, 0.527687855358763720f, + -0.849438359921935950f, + 0.527524967893398200f, -0.849539527184620890f, 0.527362061032447430f, + -0.849640663212165910f, + 0.527199134781901390f, -0.849741768000852440f, 0.527036189147750190f, + -0.849842841546963210f, + 0.526873224135984700f, -0.849943883846782210f, 0.526710239752597010f, + -0.850044894896594070f, + 0.526547236003579330f, -0.850145874692685210f, 0.526384212894925210f, + -0.850246823231342710f, + 0.526221170432628170f, -0.850347740508854980f, 0.526058108622682760f, + -0.850448626521511650f, + 0.525895027471084740f, -0.850549481265603370f, 0.525731926983829640f, + -0.850650304737422200f, + 0.525568807166914680f, -0.850751096933260790f, 0.525405668026336810f, + -0.850851857849413640f, + 0.525242509568094710f, -0.850952587482175730f, 0.525079331798186890f, + -0.851053285827843790f, + 0.524916134722612890f, -0.851153952882715340f, 0.524752918347373360f, + -0.851254588643089120f, + 0.524589682678468840f, -0.851355193105265200f, 0.524426427721901510f, + -0.851455766265544310f, + 0.524263153483673470f, -0.851556308120228870f, 0.524099859969787810f, + -0.851656818665622370f, + 0.523936547186248600f, -0.851757297898029120f, 0.523773215139060170f, + -0.851857745813754840f, + 0.523609863834228030f, -0.851958162409106380f, 0.523446493277757940f, + -0.852058547680391580f, + 0.523283103475656430f, -0.852158901623919830f, 0.523119694433931250f, + -0.852259224236001090f, + 0.522956266158590140f, -0.852359515512947090f, 0.522792818655642200f, + -0.852459775451070100f, + 0.522629351931096720f, -0.852560004046683970f, 0.522465865990963900f, + -0.852660201296103760f, + 0.522302360841254700f, -0.852760367195645300f, 0.522138836487980650f, + -0.852860501741625860f, + 0.521975292937154390f, -0.852960604930363630f, 0.521811730194788550f, + -0.853060676758178320f, + 0.521648148266897090f, -0.853160717221390420f, 0.521484547159494550f, + -0.853260726316321770f, + 0.521320926878595550f, -0.853360704039295430f, 0.521157287430216610f, + -0.853460650386635320f, + 0.520993628820373810f, -0.853560565354666840f, 0.520829951055084780f, + -0.853660448939716270f, + 0.520666254140367270f, -0.853760301138111300f, 0.520502538082239790f, + -0.853860121946180660f, + 0.520338802886721960f, -0.853959911360254060f, 0.520175048559833760f, + -0.854059669376662780f, + 0.520011275107596040f, -0.854159395991738730f, 0.519847482536030300f, + -0.854259091201815420f, + 0.519683670851158520f, -0.854358755003227440f, 0.519519840059003870f, + -0.854458387392310060f, + 0.519355990165589530f, -0.854557988365400530f, 0.519192121176940360f, + -0.854657557918836460f, + 0.519028233099080970f, -0.854757096048957110f, 0.518864325938037000f, + -0.854856602752102850f, + 0.518700399699835170f, -0.854956078024614820f, 0.518536454390502110f, + -0.855055521862835950f, + 0.518372490016066220f, -0.855154934263109620f, 0.518208506582555460f, + -0.855254315221781080f, + 0.518044504095999340f, -0.855353664735196030f, 0.517880482562427800f, + -0.855452982799701830f, + 0.517716441987871150f, -0.855552269411646970f, 0.517552382378360990f, + -0.855651524567380690f, + 0.517388303739929060f, -0.855750748263253920f, 0.517224206078608310f, + -0.855849940495618240f, + 0.517060089400432130f, -0.855949101260826790f, 0.516895953711434260f, + -0.856048230555233820f, + 0.516731799017649980f, -0.856147328375194470f, 0.516567625325114350f, + -0.856246394717065210f, + 0.516403432639863990f, -0.856345429577203610f, 0.516239220967935620f, + -0.856444432951968480f, + 0.516074990315366630f, -0.856543404837719960f, 0.515910740688195650f, + -0.856642345230818720f, + 0.515746472092461380f, -0.856741254127627470f, 0.515582184534203790f, + -0.856840131524509220f, + 0.515417878019463150f, -0.856938977417828650f, 0.515253552554280290f, + -0.857037791803951680f, + 0.515089208144697270f, -0.857136574679244870f, 0.514924844796756490f, + -0.857235326040076460f, + 0.514760462516501200f, -0.857334045882815590f, 0.514596061309975040f, + -0.857432734203832700f, + 0.514431641183222930f, -0.857531390999499040f, 0.514267202142289830f, + -0.857630016266187620f, + 0.514102744193221660f, -0.857728610000272120f, 0.513938267342065490f, + -0.857827172198127320f, + 0.513773771594868030f, -0.857925702856129790f, 0.513609256957677900f, + -0.858024201970656540f, + 0.513444723436543570f, -0.858122669538086020f, 0.513280171037514330f, + -0.858221105554798250f, + 0.513115599766640560f, -0.858319510017173440f, 0.512951009629972860f, + -0.858417882921594040f, + 0.512786400633563070f, -0.858516224264442740f, 0.512621772783463100f, + -0.858614534042104080f, + 0.512457126085725800f, -0.858712812250963520f, 0.512292460546404980f, + -0.858811058887407500f, + 0.512127776171554690f, -0.858909273947823900f, 0.511963072967230200f, + -0.859007457428601410f, + 0.511798350939487000f, -0.859105609326130340f, 0.511633610094381350f, + -0.859203729636801920f, + 0.511468850437970520f, -0.859301818357008360f, 0.511304071976311890f, + -0.859399875483143450f, + 0.511139274715464390f, -0.859497901011601620f, 0.510974458661486720f, + -0.859595894938779080f, + 0.510809623820439040f, -0.859693857261072610f, 0.510644770198381730f, + -0.859791787974880540f, + 0.510479897801375700f, -0.859889687076602290f, 0.510315006635483350f, + -0.859987554562638200f, + 0.510150096706766700f, -0.860085390429390140f, 0.509985168021289570f, + -0.860183194673260880f, + 0.509820220585115560f, -0.860280967290654510f, 0.509655254404309250f, + -0.860378708277976130f, + 0.509490269484936360f, -0.860476417631632070f, 0.509325265833062480f, + -0.860574095348029980f, + 0.509160243454754750f, -0.860671741423578380f, 0.508995202356080310f, + -0.860769355854687060f, + 0.508830142543106990f, -0.860866938637767310f, 0.508665064021904260f, + -0.860964489769230900f, + 0.508499966798540810f, -0.861062009245491480f, 0.508334850879087470f, + -0.861159497062963350f, + 0.508169716269614710f, -0.861256953218062060f, 0.508004562976194010f, + -0.861354377707204800f, + 0.507839391004897940f, -0.861451770526809210f, 0.507674200361798890f, + -0.861549131673294720f, + 0.507508991052970870f, -0.861646461143081300f, 0.507343763084487920f, + -0.861743758932590700f, + 0.507178516462425290f, -0.861841025038245330f, 0.507013251192858340f, + -0.861938259456469180f, + 0.506847967281863320f, -0.862035462183687210f, 0.506682664735517600f, + -0.862132633216325380f, + 0.506517343559898530f, -0.862229772550811240f, 0.506352003761084800f, + -0.862326880183573060f, + 0.506186645345155450f, -0.862423956111040500f, 0.506021268318189830f, + -0.862521000329644520f, + 0.505855872686268860f, -0.862618012835816740f, 0.505690458455473340f, + -0.862714993625990690f, + 0.505525025631885510f, -0.862811942696600330f, 0.505359574221587390f, + -0.862908860044081290f, + 0.505194104230662240f, -0.863005745664870210f, 0.505028615665194300f, + -0.863102599555404800f, + 0.504863108531267480f, -0.863199421712124160f, 0.504697582834967680f, + -0.863296212131468230f, + 0.504532038582380380f, -0.863392970809878310f, 0.504366475779592150f, + -0.863489697743797140f, + 0.504200894432690560f, -0.863586392929667990f, 0.504035294547763080f, + -0.863683056363935940f, + 0.503869676130898950f, -0.863779688043046610f, 0.503704039188186960f, + -0.863876287963447510f, + 0.503538383725717580f, -0.863972856121586700f, 0.503372709749581150f, + -0.864069392513913680f, + 0.503207017265869030f, -0.864165897136879300f, 0.503041306280673450f, + -0.864262369986934950f, + 0.502875576800086880f, -0.864358811060534030f, 0.502709828830203100f, + -0.864455220354130250f, + 0.502544062377115800f, -0.864551597864179230f, 0.502378277446919870f, + -0.864647943587137480f, + 0.502212474045710900f, -0.864744257519462380f, 0.502046652179584660f, + -0.864840539657612980f, + 0.501880811854638400f, -0.864936789998049020f, 0.501714953076969230f, + -0.865033008537231750f, + 0.501549075852675390f, -0.865129195271623690f, 0.501383180187855880f, + -0.865225350197688090f, + 0.501217266088609950f, -0.865321473311889800f, 0.501051333561038040f, + -0.865417564610694410f, + 0.500885382611240940f, -0.865513624090568980f, 0.500719413245319880f, + -0.865609651747981880f, + 0.500553425469377640f, -0.865705647579402270f, 0.500387419289516580f, + -0.865801611581300760f, + 0.500221394711840680f, -0.865897543750148820f, 0.500055351742453860f, + -0.865993444082419520f, + 0.499889290387461380f, -0.866089312574586770f, 0.499723210652968710f, + -0.866185149223125730f, + 0.499557112545081890f, -0.866280954024512990f, 0.499390996069908220f, + -0.866376726975225830f, + 0.499224861233555030f, -0.866472468071743050f, 0.499058708042130930f, + -0.866568177310544360f, + 0.498892536501744750f, -0.866663854688111020f, 0.498726346618505960f, + -0.866759500200925290f, + 0.498560138398525200f, -0.866855113845470320f, 0.498393911847913150f, + -0.866950695618231020f, + 0.498227666972781870f, -0.867046245515692650f, 0.498061403779243520f, + -0.867141763534342360f, + 0.497895122273410930f, -0.867237249670668400f, 0.497728822461398100f, + -0.867332703921159690f, + 0.497562504349319090f, -0.867428126282306920f, 0.497396167943289340f, + -0.867523516750601460f, + 0.497229813249424340f, -0.867618875322536230f, 0.497063440273840310f, + -0.867714201994605140f, + 0.496897049022654640f, -0.867809496763303210f, 0.496730639501984710f, + -0.867904759625126920f, + 0.496564211717949340f, -0.867999990576573400f, 0.496397765676667160f, + -0.868095189614141670f, + 0.496231301384258310f, -0.868190356734331310f, 0.496064818846843060f, + -0.868285491933643240f, + 0.495898318070542240f, -0.868380595208579800f, 0.495731799061478020f, + -0.868475666555644120f, + 0.495565261825772490f, -0.868570705971340900f, 0.495398706369549080f, + -0.868665713452175580f, + 0.495232132698931350f, -0.868760688994655190f, 0.495065540820043610f, + -0.868855632595287750f, + 0.494898930739011310f, -0.868950544250582380f, 0.494732302461959820f, + -0.869045423957049530f, + 0.494565655995016010f, -0.869140271711200560f, 0.494398991344306760f, + -0.869235087509548250f, + 0.494232308515959730f, -0.869329871348606730f, 0.494065607516103730f, + -0.869424623224890780f, + 0.493898888350867430f, -0.869519343134916970f, 0.493732151026381070f, + -0.869614031075202300f, + 0.493565395548774880f, -0.869708687042265560f, 0.493398621924179830f, + -0.869803311032626650f, + 0.493231830158728070f, -0.869897903042806340f, 0.493065020258551650f, + -0.869992463069326870f, + 0.492898192229784090f, -0.870086991108711350f, 0.492731346078558840f, + -0.870181487157484560f, + 0.492564481811010650f, -0.870275951212171830f, 0.492397599433274550f, + -0.870370383269300160f, + 0.492230698951486080f, -0.870464783325397670f, 0.492063780371782060f, + -0.870559151376993250f, + 0.491896843700299240f, -0.870653487420617540f, 0.491729888943175820f, + -0.870747791452801790f, + 0.491562916106550060f, -0.870842063470078860f, 0.491395925196560830f, + -0.870936303468982760f, + 0.491228916219348330f, -0.871030511446048260f, 0.491061889181052590f, + -0.871124687397811900f, + 0.490894844087815140f, -0.871218831320810900f, 0.490727780945777570f, + -0.871312943211583920f, + 0.490560699761082080f, -0.871407023066670950f, 0.490393600539872130f, + -0.871501070882612530f, + 0.490226483288291100f, -0.871595086655951090f, 0.490059348012483910f, + -0.871689070383229740f, + 0.489892194718595300f, -0.871783022060993010f, 0.489725023412770970f, + -0.871876941685786890f, + 0.489557834101157550f, -0.871970829254157700f, 0.489390626789901920f, + -0.872064684762653970f, + 0.489223401485152030f, -0.872158508207824480f, 0.489056158193055980f, + -0.872252299586219860f, + 0.488888896919763230f, -0.872346058894391540f, 0.488721617671423250f, + -0.872439786128892280f, + 0.488554320454186230f, -0.872533481286276060f, 0.488387005274203590f, + -0.872627144363097960f, + 0.488219672137626740f, -0.872720775355914300f, 0.488052321050608310f, + -0.872814374261282390f, + 0.487884952019301210f, -0.872907941075760970f, 0.487717565049858860f, + -0.873001475795909920f, + 0.487550160148436050f, -0.873094978418290090f, 0.487382737321187310f, + -0.873188448939463790f, + 0.487215296574268820f, -0.873281887355994210f, 0.487047837913836550f, + -0.873375293664446000f, + 0.486880361346047400f, -0.873468667861384880f, 0.486712866877059340f, + -0.873562009943377740f, + 0.486545354513030270f, -0.873655319906992630f, 0.486377824260119500f, + -0.873748597748798870f, + 0.486210276124486530f, -0.873841843465366750f, 0.486042710112291390f, + -0.873935057053268130f, + 0.485875126229695420f, -0.874028238509075630f, 0.485707524482859750f, + -0.874121387829363330f, + 0.485539904877947020f, -0.874214505010706300f, 0.485372267421119770f, + -0.874307590049680950f, + 0.485204612118541880f, -0.874400642942864790f, 0.485036938976377450f, + -0.874493663686836450f, + 0.484869248000791120f, -0.874586652278176110f, 0.484701539197948730f, + -0.874679608713464510f, + 0.484533812574016120f, -0.874772532989284150f, 0.484366068135160480f, + -0.874865425102218210f, + 0.484198305887549140f, -0.874958285048851540f, 0.484030525837350010f, + -0.875051112825769970f, + 0.483862727990732320f, -0.875143908429560250f, 0.483694912353865080f, + -0.875236671856810870f, + 0.483527078932918740f, -0.875329403104110780f, 0.483359227734063980f, + -0.875422102168050830f, + 0.483191358763471910f, -0.875514769045222740f, 0.483023472027315050f, + -0.875607403732219240f, + 0.482855567531765670f, -0.875700006225634600f, 0.482687645282997510f, + -0.875792576522063880f, + 0.482519705287184520f, -0.875885114618103700f, 0.482351747550501030f, + -0.875977620510351660f, + 0.482183772079122830f, -0.876070094195406600f, 0.482015778879225530f, + -0.876162535669868460f, + 0.481847767956986080f, -0.876254944930338400f, 0.481679739318581490f, + -0.876347321973419020f, + 0.481511692970189920f, -0.876439666795713610f, 0.481343628917989870f, + -0.876531979393827100f, + 0.481175547168160360f, -0.876624259764365310f, 0.481007447726881640f, + -0.876716507903935400f, + 0.480839330600333900f, -0.876808723809145760f, 0.480671195794698690f, + -0.876900907476605650f, + 0.480503043316157670f, -0.876993058902925780f, 0.480334873170893070f, + -0.877085178084718310f, + 0.480166685365088440f, -0.877177265018595940f, 0.479998479904927220f, + -0.877269319701173170f, + 0.479830256796594250f, -0.877361342129065140f, 0.479662016046274340f, + -0.877453332298888560f, + 0.479493757660153060f, -0.877545290207261240f, 0.479325481644417130f, + -0.877637215850802120f, + 0.479157188005253310f, -0.877729109226131570f, 0.478988876748849550f, + -0.877820970329870500f, + 0.478820547881394050f, -0.877912799158641730f, 0.478652201409075550f, + -0.878004595709069080f, + 0.478483837338084080f, -0.878096359977777130f, 0.478315455674609480f, + -0.878188091961392250f, + 0.478147056424843120f, -0.878279791656541460f, 0.477978639594976110f, + -0.878371459059853590f, + 0.477810205191201040f, -0.878463094167957870f, 0.477641753219710590f, + -0.878554696977485340f, + 0.477473283686698060f, -0.878646267485068130f, 0.477304796598358010f, + -0.878737805687339280f, + 0.477136291960884750f, -0.878829311580933360f, 0.476967769780474230f, + -0.878920785162485840f, + 0.476799230063322250f, -0.879012226428633410f, 0.476630672815625380f, + -0.879103635376014330f, + 0.476462098043581310f, -0.879195012001267370f, 0.476293505753387750f, + -0.879286356301033250f, + 0.476124895951243630f, -0.879377668271953180f, 0.475956268643348220f, + -0.879468947910670100f, + 0.475787623835901120f, -0.879560195213827890f, 0.475618961535103410f, + -0.879651410178071470f, + 0.475450281747155870f, -0.879742592800047410f, 0.475281584478260800f, + -0.879833743076402940f, + 0.475112869734620470f, -0.879924861003786860f, 0.474944137522437860f, + -0.880015946578848960f, + 0.474775387847917230f, -0.880106999798240360f, 0.474606620717262560f, + -0.880198020658613190f, + 0.474437836136679340f, -0.880289009156620890f, 0.474269034112372920f, + -0.880379965288918260f, + 0.474100214650550020f, -0.880470889052160750f, 0.473931377757417560f, + -0.880561780443005590f, + 0.473762523439182850f, -0.880652639458111010f, 0.473593651702054640f, + -0.880743466094136230f, + 0.473424762552241530f, -0.880834260347742040f, 0.473255855995953380f, + -0.880925022215589880f, + 0.473086932039400220f, -0.881015751694342760f, 0.472917990688792760f, + -0.881106448780665130f, + 0.472749031950342900f, -0.881197113471221980f, 0.472580055830262250f, + -0.881287745762680100f, + 0.472411062334764100f, -0.881378345651706810f, 0.472242051470061650f, + -0.881468913134971330f, + 0.472073023242368660f, -0.881559448209143780f, 0.471903977657900320f, + -0.881649950870895260f, + 0.471734914722871430f, -0.881740421116898320f, 0.471565834443498480f, + -0.881830858943826620f, + 0.471396736825997810f, -0.881921264348354940f, 0.471227621876586400f, + -0.882011637327159590f, + 0.471058489601482610f, -0.882101977876917580f, 0.470889340006904520f, + -0.882192285994307430f, + 0.470720173099071710f, -0.882282561676008600f, 0.470550988884203490f, + -0.882372804918702290f, + 0.470381787368520710f, -0.882463015719070040f, 0.470212568558244280f, + -0.882553194073795400f, + 0.470043332459595620f, -0.882643339979562790f, 0.469874079078797470f, + -0.882733453433057540f, + 0.469704808422072460f, -0.882823534430966730f, 0.469535520495644510f, + -0.882913582969978020f, + 0.469366215305737630f, -0.883003599046780720f, 0.469196892858576630f, + -0.883093582658065370f, + 0.469027553160387240f, -0.883183533800523280f, 0.468858196217395330f, + -0.883273452470847430f, + 0.468688822035827960f, -0.883363338665731580f, 0.468519430621912420f, + -0.883453192381870920f, + 0.468350021981876530f, -0.883543013615961880f, 0.468180596121949400f, + -0.883632802364701760f, + 0.468011153048359830f, -0.883722558624789660f, 0.467841692767338220f, + -0.883812282392925090f, + 0.467672215285114710f, -0.883901973665809470f, 0.467502720607920920f, + -0.883991632440144890f, + 0.467333208741988530f, -0.884081258712634990f, 0.467163679693549770f, + -0.884170852479984500f, + 0.466994133468838110f, -0.884260413738899080f, 0.466824570074086950f, + -0.884349942486086120f, + 0.466654989515530970f, -0.884439438718253700f, 0.466485391799405010f, + -0.884528902432111350f, + 0.466315776931944480f, -0.884618333624369920f, 0.466146144919386000f, + -0.884707732291740930f, + 0.465976495767966130f, -0.884797098430937790f, 0.465806829483922770f, + -0.884886432038674560f, + 0.465637146073493770f, -0.884975733111666660f, 0.465467445542917800f, + -0.885065001646630930f, + 0.465297727898434650f, -0.885154237640285110f, 0.465127993146283950f, + -0.885243441089348270f, + 0.464958241292706740f, -0.885332611990540590f, 0.464788472343944160f, + -0.885421750340583570f, + 0.464618686306237820f, -0.885510856136199950f, 0.464448883185830770f, + -0.885599929374113360f, + 0.464279062988965760f, -0.885688970051048960f, 0.464109225721887010f, + -0.885777978163732940f, + 0.463939371390838460f, -0.885866953708892790f, 0.463769500002065680f, + -0.885955896683257030f, + 0.463599611561814120f, -0.886044807083555490f, 0.463429706076329880f, + -0.886133684906519340f, + 0.463259783551860260f, -0.886222530148880640f, 0.463089843994652470f, + -0.886311342807372890f, + 0.462919887410955130f, -0.886400122878730490f, 0.462749913807016850f, + -0.886488870359689600f, + 0.462579923189086810f, -0.886577585246987040f, 0.462409915563415540f, + -0.886666267537360890f, + 0.462239890936253280f, -0.886754917227550950f, 0.462069849313851810f, + -0.886843534314297300f, + 0.461899790702462840f, -0.886932118794342080f, 0.461729715108338770f, + -0.887020670664428360f, + 0.461559622537733190f, -0.887109189921300060f, 0.461389512996899450f, + -0.887197676561702900f, + 0.461219386492092430f, -0.887286130582383150f, 0.461049243029567010f, + -0.887374551980088740f, + 0.460879082615578690f, -0.887462940751568840f, 0.460708905256384190f, + -0.887551296893573370f, + 0.460538710958240010f, -0.887639620402853930f, 0.460368499727404070f, + -0.887727911276163020f, + 0.460198271570134270f, -0.887816169510254550f, 0.460028026492689700f, + -0.887904395101883240f, + 0.459857764501329650f, -0.887992588047805560f, 0.459687485602313870f, + -0.888080748344778900f, + 0.459517189801903590f, -0.888168875989561620f, 0.459346877106359570f, + -0.888256970978913870f, + 0.459176547521944150f, -0.888345033309596240f, 0.459006201054919680f, + -0.888433062978371320f, + 0.458835837711549120f, -0.888521059982002260f, 0.458665457498096670f, + -0.888609024317253750f, + 0.458495060420826220f, -0.888696955980891710f, 0.458324646486003300f, + -0.888784854969682850f, + 0.458154215699893230f, -0.888872721280395520f, 0.457983768068762180f, + -0.888960554909799310f, + 0.457813303598877290f, -0.889048355854664570f, 0.457642822296505770f, + -0.889136124111763240f, + 0.457472324167916110f, -0.889223859677868210f, 0.457301809219376800f, + -0.889311562549753850f, + 0.457131277457156980f, -0.889399232724195520f, 0.456960728887527030f, + -0.889486870197969790f, + 0.456790163516757220f, -0.889574474967854580f, 0.456619581351118960f, + -0.889662047030628790f, + 0.456448982396883860f, -0.889749586383072890f, 0.456278366660324670f, + -0.889837093021967900f, + 0.456107734147714220f, -0.889924566944096720f, 0.455937084865326030f, + -0.890012008146243260f, + 0.455766418819434750f, -0.890099416625192210f, 0.455595736016314920f, + -0.890186792377730240f, + 0.455425036462242420f, -0.890274135400644480f, 0.455254320163493210f, + -0.890361445690723730f, + 0.455083587126343840f, -0.890448723244757880f, 0.454912837357072050f, + -0.890535968059537830f, + 0.454742070861955450f, -0.890623180131855930f, 0.454571287647273000f, + -0.890710359458505520f, + 0.454400487719303750f, -0.890797506036281490f, 0.454229671084327320f, + -0.890884619861979530f, + 0.454058837748624540f, -0.890971700932396750f, 0.453887987718476050f, + -0.891058749244331590f, + 0.453717121000163930f, -0.891145764794583180f, 0.453546237599970260f, + -0.891232747579952520f, + 0.453375337524177750f, -0.891319697597241390f, 0.453204420779070300f, + -0.891406614843252900f, + 0.453033487370931580f, -0.891493499314791380f, 0.452862537306046810f, + -0.891580351008662290f, + 0.452691570590700860f, -0.891667169921672390f, 0.452520587231180100f, + -0.891753956050629460f, + 0.452349587233771000f, -0.891840709392342720f, 0.452178570604760410f, + -0.891927429943622510f, + 0.452007537350436530f, -0.892014117701280360f, 0.451836487477087430f, + -0.892100772662129170f, + 0.451665420991002540f, -0.892187394822982480f, 0.451494337898471210f, + -0.892273984180655730f, + 0.451323238205783520f, -0.892360540731965360f, 0.451152121919230710f, + -0.892447064473728680f, + 0.450980989045103810f, -0.892533555402764690f, 0.450809839589695340f, + -0.892620013515893040f, + 0.450638673559297760f, -0.892706438809935280f, 0.450467490960204110f, + -0.892792831281713610f, + 0.450296291798708730f, -0.892879190928051680f, 0.450125076081105750f, + -0.892965517745774260f, + 0.449953843813690580f, -0.893051811731707450f, 0.449782595002758860f, + -0.893138072882678210f, + 0.449611329654606600f, -0.893224301195515320f, 0.449440047775531260f, + -0.893310496667048090f, + 0.449268749371829920f, -0.893396659294107610f, 0.449097434449801100f, + -0.893482789073525850f, + 0.448926103015743260f, -0.893568886002136020f, 0.448754755075956020f, + -0.893654950076772430f, + 0.448583390636739300f, -0.893740981294271040f, 0.448412009704393430f, + -0.893826979651468620f, + 0.448240612285220000f, -0.893912945145203250f, 0.448069198385520340f, + -0.893998877772314240f, + 0.447897768011597310f, -0.894084777529641990f, 0.447726321169753750f, + -0.894170644414028270f, + 0.447554857866293010f, -0.894256478422316040f, 0.447383378107519710f, + -0.894342279551349480f, + 0.447211881899738260f, -0.894428047797973800f, 0.447040369249254500f, + -0.894513783159035620f, + 0.446868840162374330f, -0.894599485631382580f, 0.446697294645404090f, + -0.894685155211863980f, + 0.446525732704651400f, -0.894770791897329550f, 0.446354154346423840f, + -0.894856395684630930f, + 0.446182559577030120f, -0.894941966570620750f, 0.446010948402779110f, + -0.895027504552152630f, + 0.445839320829980350f, -0.895113009626081760f, 0.445667676864944350f, + -0.895198481789264200f, + 0.445496016513981740f, -0.895283921038557580f, 0.445324339783404240f, + -0.895369327370820310f, + 0.445152646679523590f, -0.895454700782912450f, 0.444980937208652780f, + -0.895540041271694840f, + 0.444809211377105000f, -0.895625348834030000f, 0.444637469191193790f, + -0.895710623466781320f, + 0.444465710657234110f, -0.895795865166813420f, 0.444293935781540580f, + -0.895881073930992370f, + 0.444122144570429260f, -0.895966249756185110f, 0.443950337030216250f, + -0.896051392639260040f, + 0.443778513167218220f, -0.896136502577086770f, 0.443606672987753080f, + -0.896221579566535920f, + 0.443434816498138430f, -0.896306623604479660f, 0.443262943704693380f, + -0.896391634687790820f, + 0.443091054613736990f, -0.896476612813344010f, 0.442919149231588980f, + -0.896561557978014960f, + 0.442747227564570130f, -0.896646470178680150f, 0.442575289619001170f, + -0.896731349412217880f, + 0.442403335401204130f, -0.896816195675507190f, 0.442231364917501090f, + -0.896901008965428680f, + 0.442059378174214760f, -0.896985789278863970f, 0.441887375177668960f, + -0.897070536612695870f, + 0.441715355934187310f, -0.897155250963808550f, 0.441543320450094920f, + -0.897239932329087050f, + 0.441371268731716620f, -0.897324580705418320f, 0.441199200785378660f, + -0.897409196089689720f, + 0.441027116617407340f, -0.897493778478790190f, 0.440855016234129430f, + -0.897578327869610230f, + 0.440682899641873020f, -0.897662844259040750f, 0.440510766846965880f, + -0.897747327643974690f, + 0.440338617855737300f, -0.897831778021305650f, 0.440166452674516480f, + -0.897916195387928550f, + 0.439994271309633260f, -0.898000579740739880f, 0.439822073767418610f, + -0.898084931076636780f, + 0.439649860054203420f, -0.898169249392518080f, 0.439477630176319860f, + -0.898253534685283570f, + 0.439305384140100060f, -0.898337786951834190f, 0.439133121951876930f, + -0.898422006189072530f, + 0.438960843617984430f, -0.898506192393901840f, 0.438788549144756290f, + -0.898590345563227030f, + 0.438616238538527710f, -0.898674465693953820f, 0.438443911805633860f, + -0.898758552782989440f, + 0.438271568952410480f, -0.898842606827242260f, 0.438099209985194580f, + -0.898926627823621870f, + 0.437926834910322860f, -0.899010615769039070f, 0.437754443734133470f, + -0.899094570660405770f, + 0.437582036462964340f, -0.899178492494635330f, 0.437409613103154850f, + -0.899262381268642000f, + 0.437237173661044200f, -0.899346236979341460f, 0.437064718142972370f, + -0.899430059623650860f, + 0.436892246555280470f, -0.899513849198487870f, 0.436719758904309310f, + -0.899597605700772180f, + 0.436547255196401250f, -0.899681329127423930f, 0.436374735437898510f, + -0.899765019475365020f, + 0.436202199635143950f, -0.899848676741518580f, 0.436029647794481670f, + -0.899932300922808400f, + 0.435857079922255470f, -0.900015892016160280f, 0.435684496024810520f, + -0.900099450018500340f, + 0.435511896108492170f, -0.900182974926756700f, 0.435339280179646070f, + -0.900266466737858480f, + 0.435166648244619370f, -0.900349925448735600f, 0.434994000309758710f, + -0.900433351056319830f, + 0.434821336381412350f, -0.900516743557543520f, 0.434648656465928430f, + -0.900600102949340790f, + 0.434475960569655710f, -0.900683429228646860f, 0.434303248698944100f, + -0.900766722392397860f, + 0.434130520860143310f, -0.900849982437531450f, 0.433957777059604480f, + -0.900933209360986200f, + 0.433785017303678520f, -0.901016403159702330f, 0.433612241598717640f, + -0.901099563830620950f, + 0.433439449951074200f, -0.901182691370684410f, 0.433266642367100940f, + -0.901265785776836580f, + 0.433093818853152010f, -0.901348847046022030f, 0.432920979415581220f, + -0.901431875175186970f, + 0.432748124060743760f, -0.901514870161278630f, 0.432575252794994810f, + -0.901597832001245660f, + 0.432402365624690140f, -0.901680760692037730f, 0.432229462556186770f, + -0.901763656230605610f, + 0.432056543595841450f, -0.901846518613901860f, 0.431883608750012300f, + -0.901929347838879350f, + 0.431710658025057370f, -0.902012143902493070f, 0.431537691427335500f, + -0.902094906801698900f, + 0.431364708963206440f, -0.902177636533453510f, 0.431191710639030000f, + -0.902260333094715540f, + 0.431018696461167080f, -0.902342996482444200f, 0.430845666435978820f, + -0.902425626693600270f, + 0.430672620569826860f, -0.902508223725145830f, 0.430499558869073930f, + -0.902590787574043870f, + 0.430326481340082610f, -0.902673318237258830f, 0.430153387989216930f, + -0.902755815711756120f, + 0.429980278822840570f, -0.902838279994502830f, 0.429807153847318770f, + -0.902920711082466630f, + 0.429634013069016500f, -0.903003108972617040f, 0.429460856494299490f, + -0.903085473661924600f, + 0.429287684129534720f, -0.903167805147360610f, 0.429114495981088690f, + -0.903250103425898400f, + 0.428941292055329550f, -0.903332368494511820f, 0.428768072358625240f, + -0.903414600350176290f, + 0.428594836897344400f, -0.903496798989868450f, 0.428421585677856760f, + -0.903578964410565950f, + 0.428248318706531910f, -0.903661096609247980f, 0.428075035989740780f, + -0.903743195582894620f, + 0.427901737533854240f, -0.903825261328487390f, 0.427728423345243860f, + -0.903907293843009050f, + 0.427555093430282200f, -0.903989293123443340f, 0.427381747795341770f, + -0.904071259166775440f, + 0.427208386446796370f, -0.904153191969991670f, 0.427035009391019790f, + -0.904235091530079750f, + 0.426861616634386490f, -0.904316957844028320f, 0.426688208183271970f, + -0.904398790908827350f, + 0.426514784044051520f, -0.904480590721468250f, 0.426341344223101880f, + -0.904562357278943190f, + 0.426167888726799620f, -0.904644090578246240f, 0.425994417561522450f, + -0.904725790616371930f, + 0.425820930733648300f, -0.904807457390316540f, 0.425647428249555590f, + -0.904889090897077470f, + 0.425473910115623910f, -0.904970691133653250f, 0.425300376338232590f, + -0.905052258097043590f, + 0.425126826923762410f, -0.905133791784249580f, 0.424953261878594060f, + -0.905215292192273480f, + 0.424779681209108810f, -0.905296759318118820f, 0.424606084921689220f, + -0.905378193158789980f, + 0.424432473022717420f, -0.905459593711293250f, 0.424258845518577010f, + -0.905540960972635480f, + 0.424085202415651670f, -0.905622294939825160f, 0.423911543720325580f, + -0.905703595609872010f, + 0.423737869438983950f, -0.905784862979786440f, 0.423564179578011960f, + -0.905866097046580940f, + 0.423390474143796100f, -0.905947297807268460f, 0.423216753142722780f, + -0.906028465258863490f, + 0.423043016581179100f, -0.906109599398381980f, 0.422869264465553170f, + -0.906190700222840540f, + 0.422695496802232950f, -0.906271767729257660f, 0.422521713597607870f, + -0.906352801914652280f, + 0.422347914858067000f, -0.906433802776045460f, 0.422174100590000820f, + -0.906514770310458800f, + 0.422000270799799790f, -0.906595704514915330f, 0.421826425493854910f, + -0.906676605386439460f, + 0.421652564678558380f, -0.906757472922056550f, 0.421478688360302220f, + -0.906838307118793540f, + 0.421304796545479700f, -0.906919107973678030f, 0.421130889240484140f, + -0.906999875483739610f, + 0.420956966451709440f, -0.907080609646008450f, 0.420783028185550630f, + -0.907161310457516250f, + 0.420609074448402510f, -0.907241977915295930f, 0.420435105246661220f, + -0.907322612016381310f, + 0.420261120586723050f, -0.907403212757808000f, 0.420087120474984590f, + -0.907483780136612570f, + 0.419913104917843730f, -0.907564314149832520f, 0.419739073921698180f, + -0.907644814794507090f, + 0.419565027492946940f, -0.907725282067676330f, 0.419390965637989050f, + -0.907805715966381820f, + 0.419216888363223960f, -0.907886116487666150f, 0.419042795675052480f, + -0.907966483628573240f, + 0.418868687579875110f, -0.908046817386148340f, 0.418694564084093610f, + -0.908127117757437600f, + 0.418520425194109700f, -0.908207384739488700f, 0.418346270916326310f, + -0.908287618329350450f, + 0.418172101257146430f, -0.908367818524072780f, 0.417997916222973550f, + -0.908447985320707250f, + 0.417823715820212380f, -0.908528118716306120f, 0.417649500055267410f, + -0.908608218707923190f, + 0.417475268934544340f, -0.908688285292613360f, 0.417301022464449060f, + -0.908768318467432780f, + 0.417126760651387870f, -0.908848318229439120f, 0.416952483501768280f, + -0.908928284575690640f, + 0.416778191021997590f, -0.909008217503247450f, 0.416603883218484410f, + -0.909088117009170580f, + 0.416429560097637320f, -0.909167983090522270f, 0.416255221665865480f, + -0.909247815744366310f, + 0.416080867929579320f, -0.909327614967767260f, 0.415906498895188770f, + -0.909407380757791260f, + 0.415732114569105420f, -0.909487113111505430f, 0.415557714957740580f, + -0.909566812025978220f, + 0.415383300067506290f, -0.909646477498279540f, 0.415208869904815650f, + -0.909726109525480160f, + 0.415034424476081630f, -0.909805708104652220f, 0.414859963787718390f, + -0.909885273232869160f, + 0.414685487846140010f, -0.909964804907205660f, 0.414510996657761810f, + -0.910044303124737390f, + 0.414336490228999210f, -0.910123767882541570f, 0.414161968566268080f, + -0.910203199177696540f, + 0.413987431675985510f, -0.910282597007281760f, 0.413812879564568300f, + -0.910361961368377990f, + 0.413638312238434560f, -0.910441292258067140f, 0.413463729704002580f, + -0.910520589673432630f, + 0.413289131967690960f, -0.910599853611558930f, 0.413114519035919560f, + -0.910679084069531570f, + 0.412939890915108020f, -0.910758281044437570f, 0.412765247611677320f, + -0.910837444533365010f, + 0.412590589132048380f, -0.910916574533403240f, 0.412415915482642730f, + -0.910995671041643140f, + 0.412241226669883000f, -0.911074734055176250f, 0.412066522700191560f, + -0.911153763571095900f, + 0.411891803579992220f, -0.911232759586496190f, 0.411717069315708670f, + -0.911311722098472670f, + 0.411542319913765280f, -0.911390651104122320f, 0.411367555380587340f, + -0.911469546600543020f, + 0.411192775722600160f, -0.911548408584833990f, 0.411017980946230270f, + -0.911627237054095650f, + 0.410843171057903910f, -0.911706032005429880f, 0.410668346064048780f, + -0.911784793435939430f, + 0.410493505971092520f, -0.911863521342728520f, 0.410318650785463260f, + -0.911942215722902570f, + 0.410143780513590350f, -0.912020876573568230f, 0.409968895161902820f, + -0.912099503891833470f, + 0.409793994736831200f, -0.912178097674807060f, 0.409619079244805840f, + -0.912256657919599650f, + 0.409444148692257590f, -0.912335184623322750f, 0.409269203085618700f, + -0.912413677783089020f, + 0.409094242431320920f, -0.912492137396012650f, 0.408919266735797480f, + -0.912570563459208730f, + 0.408744276005481520f, -0.912648955969793900f, 0.408569270246806780f, + -0.912727314924885900f, + 0.408394249466208110f, -0.912805640321603500f, 0.408219213670120100f, + -0.912883932157067200f, + 0.408044162864978740f, -0.912962190428398100f, 0.407869097057219960f, + -0.913040415132719160f, + 0.407694016253280170f, -0.913118606267154130f, 0.407518920459597030f, + -0.913196763828828200f, + 0.407343809682607970f, -0.913274887814867760f, 0.407168683928751610f, + -0.913352978222400250f, + 0.406993543204466460f, -0.913431035048554720f, 0.406818387516192370f, + -0.913509058290461140f, + 0.406643216870369140f, -0.913587047945250810f, 0.406468031273437000f, + -0.913665004010056350f, + 0.406292830731837470f, -0.913742926482011390f, 0.406117615252011790f, + -0.913820815358251100f, + 0.405942384840402570f, -0.913898670635911680f, 0.405767139503452220f, + -0.913976492312130520f, + 0.405591879247603870f, -0.914054280384046460f, 0.405416604079301750f, + -0.914132034848799460f, + 0.405241314004989860f, -0.914209755703530690f, 0.405066009031113390f, + -0.914287442945382440f, + 0.404890689164117750f, -0.914365096571498450f, 0.404715354410448650f, + -0.914442716579023870f, + 0.404540004776553110f, -0.914520302965104450f, 0.404364640268877810f, + -0.914597855726887790f, + 0.404189260893870750f, -0.914675374861522390f, 0.404013866657980060f, + -0.914752860366158100f, + 0.403838457567654130f, -0.914830312237946090f, 0.403663033629342750f, + -0.914907730474038620f, + 0.403487594849495310f, -0.914985115071589310f, 0.403312141234562660f, + -0.915062466027752760f, + 0.403136672790995240f, -0.915139783339685260f, 0.402961189525244960f, + -0.915217067004543750f, + 0.402785691443763640f, -0.915294317019487050f, 0.402610178553003680f, + -0.915371533381674760f, + 0.402434650859418540f, -0.915448716088267830f, 0.402259108369461440f, + -0.915525865136428530f, + 0.402083551089587040f, -0.915602980523320230f, 0.401907979026249860f, + -0.915680062246107650f, + 0.401732392185905010f, -0.915757110301956720f, 0.401556790575008650f, + -0.915834124688034710f, + 0.401381174200016790f, -0.915911105401509880f, 0.401205543067386760f, + -0.915988052439551840f, + 0.401029897183575790f, -0.916064965799331610f, 0.400854236555041650f, + -0.916141845478021350f, + 0.400678561188243350f, -0.916218691472794110f, 0.400502871089639500f, + -0.916295503780824800f, + 0.400327166265690150f, -0.916372282399289140f, 0.400151446722855300f, + -0.916449027325364040f, + 0.399975712467595390f, -0.916525738556228100f, 0.399799963506372090f, + -0.916602416089060680f, + 0.399624199845646790f, -0.916679059921042700f, 0.399448421491882260f, + -0.916755670049355990f, + 0.399272628451540930f, -0.916832246471183890f, 0.399096820731086600f, + -0.916908789183710990f, + 0.398920998336983020f, -0.916985298184122890f, 0.398745161275694480f, + -0.917061773469606820f, + 0.398569309553686360f, -0.917138215037350710f, 0.398393443177423920f, + -0.917214622884544250f, + 0.398217562153373620f, -0.917290997008377910f, 0.398041666488001930f, + -0.917367337406043810f, + 0.397865756187775750f, -0.917443644074735220f, 0.397689831259163240f, + -0.917519917011646260f, + 0.397513891708632330f, -0.917596156213972950f, 0.397337937542652120f, + -0.917672361678911750f, + 0.397161968767691720f, -0.917748533403661250f, 0.396985985390220900f, + -0.917824671385420570f, + 0.396809987416710420f, -0.917900775621390390f, 0.396633974853630830f, + -0.917976846108772730f, + 0.396457947707453960f, -0.918052882844770380f, 0.396281905984651680f, + -0.918128885826587910f, + 0.396105849691696320f, -0.918204855051430900f, 0.395929778835061360f, + -0.918280790516506130f, + 0.395753693421220080f, -0.918356692219021720f, 0.395577593456646950f, + -0.918432560156186790f, + 0.395401478947816300f, -0.918508394325212250f, 0.395225349901203730f, + -0.918584194723309540f, + 0.395049206323284880f, -0.918659961347691900f, 0.394873048220535760f, + -0.918735694195573550f, + 0.394696875599433670f, -0.918811393264169940f, 0.394520688466455550f, + -0.918887058550697970f, + 0.394344486828079650f, -0.918962690052375630f, 0.394168270690784250f, + -0.919038287766421940f, + 0.393992040061048100f, -0.919113851690057770f, 0.393815794945351130f, + -0.919189381820504470f, + 0.393639535350172880f, -0.919264878154985250f, 0.393463261281994380f, + -0.919340340690724230f, + 0.393286972747296570f, -0.919415769424946960f, 0.393110669752560760f, + -0.919491164354880100f, + 0.392934352304269600f, -0.919566525477751530f, 0.392758020408905280f, + -0.919641852790790470f, + 0.392581674072951530f, -0.919717146291227360f, 0.392405313302891860f, + -0.919792405976293750f, + 0.392228938105210370f, -0.919867631843222950f, 0.392052548486392200f, + -0.919942823889248640f, + 0.391876144452922350f, -0.920017982111606570f, 0.391699726011287050f, + -0.920093106507533070f, + 0.391523293167972350f, -0.920168197074266450f, 0.391346845929465610f, + -0.920243253809045370f, + 0.391170384302253980f, -0.920318276709110480f, 0.390993908292825380f, + -0.920393265771703550f, + 0.390817417907668610f, -0.920468220994067110f, 0.390640913153272370f, + -0.920543142373445480f, + 0.390464394036126650f, -0.920618029907083860f, 0.390287860562721360f, + -0.920692883592229010f, + 0.390111312739546910f, -0.920767703426128790f, 0.389934750573094790f, + -0.920842489406032080f, + 0.389758174069856410f, -0.920917241529189520f, 0.389581583236324360f, + -0.920991959792852310f, + 0.389404978078991100f, -0.921066644194273530f, 0.389228358604349730f, + -0.921141294730707270f, + 0.389051724818894500f, -0.921215911399408730f, 0.388875076729119250f, + -0.921290494197634540f, + 0.388698414341519250f, -0.921365043122642340f, 0.388521737662589740f, + -0.921439558171691320f, + 0.388345046698826300f, -0.921514039342041900f, 0.388168341456725850f, + -0.921588486630955380f, + 0.387991621942784910f, -0.921662900035694730f, 0.387814888163501290f, + -0.921737279553523800f, + 0.387638140125372680f, -0.921811625181708120f, 0.387461377834897920f, + -0.921885936917513970f, + 0.387284601298575890f, -0.921960214758209110f, 0.387107810522905990f, + -0.922034458701062820f, + 0.386931005514388690f, -0.922108668743345070f, 0.386754186279524130f, + -0.922182844882327600f, + 0.386577352824813980f, -0.922256987115283030f, 0.386400505156759610f, + -0.922331095439485330f, + 0.386223643281862980f, -0.922405169852209880f, 0.386046767206627280f, + -0.922479210350733100f, + 0.385869876937555310f, -0.922553216932332830f, 0.385692972481151200f, + -0.922627189594287800f, + 0.385516053843919020f, -0.922701128333878520f, 0.385339121032363340f, + -0.922775033148386380f, + 0.385162174052989970f, -0.922848904035094120f, 0.384985212912304200f, + -0.922922740991285680f, + 0.384808237616812930f, -0.922996544014246250f, 0.384631248173022740f, + -0.923070313101262420f, + 0.384454244587440870f, -0.923144048249621820f, 0.384277226866575620f, + -0.923217749456613500f, + 0.384100195016935040f, -0.923291416719527640f, 0.383923149045028500f, + -0.923365050035655610f, + 0.383746088957365010f, -0.923438649402290370f, 0.383569014760454960f, + -0.923512214816725520f, + 0.383391926460808770f, -0.923585746276256560f, 0.383214824064937180f, + -0.923659243778179980f, + 0.383037707579352130f, -0.923732707319793180f, 0.382860577010565360f, + -0.923806136898395410f, + 0.382683432365089840f, -0.923879532511286740f, 0.382506273649438400f, + -0.923952894155768640f, + 0.382329100870124510f, -0.924026221829143850f, 0.382151914033662720f, + -0.924099515528716280f, + 0.381974713146567220f, -0.924172775251791200f, 0.381797498215353690f, + -0.924246000995674890f, + 0.381620269246537520f, -0.924319192757675160f, 0.381443026246634730f, + -0.924392350535101050f, + 0.381265769222162490f, -0.924465474325262600f, 0.381088498179637520f, + -0.924538564125471420f, + 0.380911213125578130f, -0.924611619933039970f, 0.380733914066502090f, + -0.924684641745282530f, + 0.380556601008928570f, -0.924757629559513910f, 0.380379273959376710f, + -0.924830583373050800f, + 0.380201932924366050f, -0.924903503183210910f, 0.380024577910417380f, + -0.924976388987313050f, + 0.379847208924051110f, -0.925049240782677580f, 0.379669825971789000f, + -0.925122058566625770f, + 0.379492429060152740f, -0.925194842336480420f, 0.379315018195664430f, + -0.925267592089565550f, + 0.379137593384847430f, -0.925340307823206200f, 0.378960154634224720f, + -0.925412989534729060f, + 0.378782701950320600f, -0.925485637221461490f, 0.378605235339659290f, + -0.925558250880732620f, + 0.378427754808765620f, -0.925630830509872720f, 0.378250260364165310f, + -0.925703376106213120f, + 0.378072752012383990f, -0.925775887667086740f, 0.377895229759948550f, + -0.925848365189827270f, + 0.377717693613385810f, -0.925920808671769960f, 0.377540143579222940f, + -0.925993218110251480f, + 0.377362579663988450f, -0.926065593502609310f, 0.377185001874210450f, + -0.926137934846182560f, + 0.377007410216418310f, -0.926210242138311270f, 0.376829804697141220f, + -0.926282515376337210f, + 0.376652185322909620f, -0.926354754557602860f, 0.376474552100253880f, + -0.926426959679452100f, + 0.376296905035704790f, -0.926499130739230510f, 0.376119244135794390f, + -0.926571267734284220f, + 0.375941569407054420f, -0.926643370661961230f, 0.375763880856017750f, + -0.926715439519610330f, + 0.375586178489217330f, -0.926787474304581750f, 0.375408462313186590f, + -0.926859475014227160f, + 0.375230732334460030f, -0.926931441645899130f, 0.375052988559571860f, + -0.927003374196951670f, + 0.374875230995057600f, -0.927075272664740100f, 0.374697459647452770f, + -0.927147137046620880f, + 0.374519674523293210f, -0.927218967339951790f, 0.374341875629116030f, + -0.927290763542091720f, + 0.374164062971457990f, -0.927362525650401110f, 0.373986236556857090f, + -0.927434253662241300f, + 0.373808396391851370f, -0.927505947574975180f, 0.373630542482979280f, + -0.927577607385966730f, + 0.373452674836780410f, -0.927649233092581180f, 0.373274793459794030f, + -0.927720824692185200f, + 0.373096898358560690f, -0.927792382182146320f, 0.372918989539620770f, + -0.927863905559833780f, + 0.372741067009515810f, -0.927935394822617890f, 0.372563130774787370f, + -0.928006849967869970f, + 0.372385180841977360f, -0.928078270992963140f, 0.372207217217628950f, + -0.928149657895271150f, + 0.372029239908284960f, -0.928221010672169440f, 0.371851248920489540f, + -0.928292329321034560f, + 0.371673244260786630f, -0.928363613839244370f, 0.371495225935720760f, + -0.928434864224177980f, + 0.371317193951837600f, -0.928506080473215480f, 0.371139148315682510f, + -0.928577262583738850f, + 0.370961089033802040f, -0.928648410553130520f, 0.370783016112742720f, + -0.928719524378774700f, + 0.370604929559051670f, -0.928790604058057020f, 0.370426829379276900f, + -0.928861649588363700f, + 0.370248715579966360f, -0.928932660967082820f, 0.370070588167669130f, + -0.929003638191603360f, + 0.369892447148934270f, -0.929074581259315750f, 0.369714292530311240f, + -0.929145490167611720f, + 0.369536124318350760f, -0.929216364913883930f, 0.369357942519603190f, + -0.929287205495526790f, + 0.369179747140620070f, -0.929358011909935500f, 0.369001538187952780f, + -0.929428784154506800f, + 0.368823315668153960f, -0.929499522226638560f, 0.368645079587776150f, + -0.929570226123729860f, + 0.368466829953372320f, -0.929640895843181330f, 0.368288566771496680f, + -0.929711531382394370f, + 0.368110290048703050f, -0.929782132738772190f, 0.367931999791546500f, + -0.929852699909718750f, + 0.367753696006582090f, -0.929923232892639560f, 0.367575378700365330f, + -0.929993731684941480f, + 0.367397047879452820f, -0.930064196284032360f, 0.367218703550400930f, + -0.930134626687321390f, + 0.367040345719767240f, -0.930205022892219070f, 0.366861974394109220f, + -0.930275384896137040f, + 0.366683589579984930f, -0.930345712696488470f, 0.366505191283953480f, + -0.930416006290687550f, + 0.366326779512573590f, -0.930486265676149780f, 0.366148354272405390f, + -0.930556490850291800f, + 0.365969915570008910f, -0.930626681810531650f, 0.365791463411944570f, + -0.930696838554288860f, + 0.365612997804773960f, -0.930766961078983710f, 0.365434518755058390f, + -0.930837049382038150f, + 0.365256026269360380f, -0.930907103460875020f, 0.365077520354242180f, + -0.930977123312918930f, + 0.364899001016267380f, -0.931047108935595170f, 0.364720468261999390f, + -0.931117060326330790f, + 0.364541922098002180f, -0.931186977482553750f, 0.364363362530840730f, + -0.931256860401693420f, + 0.364184789567079840f, -0.931326709081180430f, 0.364006203213285530f, + -0.931396523518446600f, + 0.363827603476023610f, -0.931466303710925090f, 0.363648990361860550f, + -0.931536049656050300f, + 0.363470363877363870f, -0.931605761351257830f, 0.363291724029100700f, + -0.931675438793984620f, + 0.363113070823639530f, -0.931745081981668720f, 0.362934404267548750f, + -0.931814690911749620f, + 0.362755724367397230f, -0.931884265581668150f, 0.362577031129754870f, + -0.931953805988865900f, + 0.362398324561191310f, -0.932023312130786490f, 0.362219604668277570f, + -0.932092784004874050f, + 0.362040871457584350f, -0.932162221608574320f, 0.361862124935682980f, + -0.932231624939334540f, + 0.361683365109145950f, -0.932300993994602640f, 0.361504591984545260f, + -0.932370328771828460f, + 0.361325805568454340f, -0.932439629268462360f, 0.361147005867446190f, + -0.932508895481956700f, + 0.360968192888095290f, -0.932578127409764420f, 0.360789366636975690f, + -0.932647325049340340f, + 0.360610527120662270f, -0.932716488398140250f, 0.360431674345730810f, + -0.932785617453620990f, + 0.360252808318756830f, -0.932854712213241230f, 0.360073929046317080f, + -0.932923772674460140f, + 0.359895036534988280f, -0.932992798834738850f, 0.359716130791347570f, + -0.933061790691539380f, + 0.359537211821973180f, -0.933130748242325110f, 0.359358279633443080f, + -0.933199671484560730f, + 0.359179334232336560f, -0.933268560415712050f, 0.359000375625232630f, + -0.933337415033246080f, + 0.358821403818710920f, -0.933406235334631520f, 0.358642418819352100f, + -0.933475021317337950f, + 0.358463420633736540f, -0.933543772978836170f, 0.358284409268445900f, + -0.933612490316598540f, + 0.358105384730061760f, -0.933681173328098300f, 0.357926347025166070f, + -0.933749822010810580f, + 0.357747296160342010f, -0.933818436362210960f, 0.357568232142172260f, + -0.933887016379776890f, + 0.357389154977241000f, -0.933955562060986730f, 0.357210064672131900f, + -0.934024073403320500f, + 0.357030961233430030f, -0.934092550404258870f, 0.356851844667720410f, + -0.934160993061284420f, + 0.356672714981588260f, -0.934229401371880820f, 0.356493572181620200f, + -0.934297775333532530f, + 0.356314416274402360f, -0.934366114943725900f, 0.356135247266522180f, + -0.934434420199948050f, + 0.355956065164567010f, -0.934502691099687870f, 0.355776869975124640f, + -0.934570927640435030f, + 0.355597661704783960f, -0.934639129819680780f, 0.355418440360133590f, + -0.934707297634917440f, + 0.355239205947763370f, -0.934775431083638700f, 0.355059958474263030f, + -0.934843530163339430f, + 0.354880697946222790f, -0.934911594871516090f, 0.354701424370233940f, + -0.934979625205665800f, + 0.354522137752887430f, -0.935047621163287430f, 0.354342838100775600f, + -0.935115582741880890f, + 0.354163525420490510f, -0.935183509938947500f, 0.353984199718624830f, + -0.935251402751989810f, + 0.353804861001772160f, -0.935319261178511500f, 0.353625509276525970f, + -0.935387085216017770f, + 0.353446144549480870f, -0.935454874862014620f, 0.353266766827231180f, + -0.935522630114009930f, + 0.353087376116372530f, -0.935590350969512370f, 0.352907972423500360f, + -0.935658037426032040f, + 0.352728555755210730f, -0.935725689481080370f, 0.352549126118100580f, + -0.935793307132169900f, + 0.352369683518766630f, -0.935860890376814640f, 0.352190227963806890f, + -0.935928439212529660f, + 0.352010759459819240f, -0.935995953636831300f, 0.351831278013402030f, + -0.936063433647237540f, + 0.351651783631154680f, -0.936130879241266920f, 0.351472276319676260f, + -0.936198290416440090f, + 0.351292756085567150f, -0.936265667170278260f, 0.351113222935427630f, + -0.936333009500304180f, + 0.350933676875858360f, -0.936400317404042060f, 0.350754117913461170f, + -0.936467590879016880f, + 0.350574546054837570f, -0.936534829922755500f, 0.350394961306590200f, + -0.936602034532785570f, + 0.350215363675321740f, -0.936669204706636060f, 0.350035753167635300f, + -0.936736340441837620f, + 0.349856129790135030f, -0.936803441735921560f, 0.349676493549424760f, + -0.936870508586420960f, + 0.349496844452109600f, -0.936937540990869900f, 0.349317182504794320f, + -0.937004538946803690f, + 0.349137507714085030f, -0.937071502451759190f, 0.348957820086587600f, + -0.937138431503274140f, + 0.348778119628908420f, -0.937205326098887960f, 0.348598406347655040f, + -0.937272186236140950f, + 0.348418680249434510f, -0.937339011912574960f, 0.348238941340855310f, + -0.937405803125732850f, + 0.348059189628525780f, -0.937472559873159140f, 0.347879425119054510f, + -0.937539282152399230f, + 0.347699647819051490f, -0.937605969960999990f, 0.347519857735126110f, + -0.937672623296509470f, + 0.347340054873889190f, -0.937739242156476970f, 0.347160239241951330f, + -0.937805826538453010f, + 0.346980410845923680f, -0.937872376439989890f, 0.346800569692418400f, + -0.937938891858640210f, + 0.346620715788047320f, -0.938005372791958840f, 0.346440849139423580f, + -0.938071819237501160f, + 0.346260969753160170f, -0.938138231192824360f, 0.346081077635870480f, + -0.938204608655486490f, + 0.345901172794169100f, -0.938270951623047080f, 0.345721255234670120f, + -0.938337260093066950f, + 0.345541324963989150f, -0.938403534063108060f, 0.345361381988741170f, + -0.938469773530733800f, + 0.345181426315542610f, -0.938535978493508560f, 0.345001457951009780f, + -0.938602148948998290f, + 0.344821476901759290f, -0.938668284894770170f, 0.344641483174409070f, + -0.938734386328392460f, + 0.344461476775576480f, -0.938800453247434770f, 0.344281457711880230f, + -0.938866485649468060f, + 0.344101425989938980f, -0.938932483532064490f, 0.343921381616371700f, + -0.938998446892797540f, + 0.343741324597798600f, -0.939064375729241950f, 0.343561254940839330f, + -0.939130270038973650f, + 0.343381172652115100f, -0.939196129819569900f, 0.343201077738246710f, + -0.939261955068609100f, + 0.343020970205855540f, -0.939327745783671400f, 0.342840850061564060f, + -0.939393501962337510f, + 0.342660717311994380f, -0.939459223602189920f, 0.342480571963769850f, + -0.939524910700812120f, + 0.342300414023513690f, -0.939590563255789160f, 0.342120243497849590f, + -0.939656181264707070f, + 0.341940060393402300f, -0.939721764725153340f, 0.341759864716796310f, + -0.939787313634716570f, + 0.341579656474657210f, -0.939852827990986680f, 0.341399435673610360f, + -0.939918307791555050f, + 0.341219202320282410f, -0.939983753034013940f, 0.341038956421299830f, + -0.940049163715957370f, + 0.340858697983289440f, -0.940114539834980280f, 0.340678427012879310f, + -0.940179881388678810f, + 0.340498143516697100f, -0.940245188374650880f, 0.340317847501371730f, + -0.940310460790495070f, + 0.340137538973531880f, -0.940375698633811540f, 0.339957217939806880f, + -0.940440901902201750f, + 0.339776884406826960f, -0.940506070593268300f, 0.339596538381222060f, + -0.940571204704615190f, + 0.339416179869623410f, -0.940636304233847590f, 0.339235808878662120f, + -0.940701369178571940f, + 0.339055425414969640f, -0.940766399536396070f, 0.338875029485178560f, + -0.940831395304928870f, + 0.338694621095921190f, -0.940896356481780830f, 0.338514200253831000f, + -0.940961283064563280f, + 0.338333766965541290f, -0.941026175050889260f, 0.338153321237685990f, + -0.941091032438372780f, + 0.337972863076899830f, -0.941155855224629190f, 0.337792392489817460f, + -0.941220643407275180f, + 0.337611909483074680f, -0.941285396983928660f, 0.337431414063306790f, + -0.941350115952208970f, + 0.337250906237150650f, -0.941414800309736230f, 0.337070386011242730f, + -0.941479450054132580f, + 0.336889853392220050f, -0.941544065183020810f, 0.336709308386720700f, + -0.941608645694025140f, + 0.336528751001382350f, -0.941673191584771360f, 0.336348181242844100f, + -0.941737702852886160f, + 0.336167599117744690f, -0.941802179495997650f, 0.335987004632723350f, + -0.941866621511735280f, + 0.335806397794420560f, -0.941931028897729510f, 0.335625778609476230f, + -0.941995401651612550f, + 0.335445147084531660f, -0.942059739771017310f, 0.335264503226227970f, + -0.942124043253578460f, + 0.335083847041206580f, -0.942188312096931770f, 0.334903178536110290f, + -0.942252546298714020f, + 0.334722497717581220f, -0.942316745856563780f, 0.334541804592262960f, + -0.942380910768120470f, + 0.334361099166798900f, -0.942445041031024890f, 0.334180381447832740f, + -0.942509136642919240f, + 0.333999651442009490f, -0.942573197601446870f, 0.333818909155973620f, + -0.942637223904252530f, + 0.333638154596370920f, -0.942701215548981900f, 0.333457387769846790f, + -0.942765172533282510f, + 0.333276608683047980f, -0.942829094854802710f, 0.333095817342620890f, + -0.942892982511192130f, + 0.332915013755212650f, -0.942956835500102120f, 0.332734197927471160f, + -0.943020653819184650f, + 0.332553369866044220f, -0.943084437466093490f, 0.332372529577580680f, + -0.943148186438483420f, + 0.332191677068729320f, -0.943211900734010620f, 0.332010812346139380f, + -0.943275580350332540f, + 0.331829935416461220f, -0.943339225285107720f, 0.331649046286344620f, + -0.943402835535996240f, + 0.331468144962440920f, -0.943466411100659320f, 0.331287231451400990f, + -0.943529951976759370f, + 0.331106305759876430f, -0.943593458161960390f, 0.330925367894519650f, + -0.943656929653927110f, + 0.330744417861982890f, -0.943720366450326200f, 0.330563455668919590f, + -0.943783768548825060f, + 0.330382481321982950f, -0.943847135947092690f, 0.330201494827826620f, + -0.943910468642799150f, + 0.330020496193105530f, -0.943973766633615980f, 0.329839485424473940f, + -0.944037029917215830f, + 0.329658462528587550f, -0.944100258491272660f, 0.329477427512101680f, + -0.944163452353461770f, + 0.329296380381672800f, -0.944226611501459810f, 0.329115321143957360f, + -0.944289735932944410f, + 0.328934249805612200f, -0.944352825645594750f, 0.328753166373295100f, + -0.944415880637091250f, + 0.328572070853663690f, -0.944478900905115550f, 0.328390963253376630f, + -0.944541886447350380f, + 0.328209843579092660f, -0.944604837261480260f, 0.328028711837470730f, + -0.944667753345190490f, + 0.327847568035170960f, -0.944730634696167800f, 0.327666412178853060f, + -0.944793481312100280f, + 0.327485244275178060f, -0.944856293190677210f, 0.327304064330806830f, + -0.944919070329589220f, + 0.327122872352400510f, -0.944981812726528150f, 0.326941668346621530f, + -0.945044520379187070f, + 0.326760452320131790f, -0.945107193285260610f, 0.326579224279594460f, + -0.945169831442444150f, + 0.326397984231672660f, -0.945232434848434890f, 0.326216732183029770f, + -0.945295003500931100f, + 0.326035468140330350f, -0.945357537397632290f, 0.325854192110238580f, + -0.945420036536239070f, + 0.325672904099419900f, -0.945482500914453740f, 0.325491604114539260f, + -0.945544930529979680f, + 0.325310292162262980f, -0.945607325380521280f, 0.325128968249257190f, + -0.945669685463784710f, + 0.324947632382188430f, -0.945732010777477150f, 0.324766284567724330f, + -0.945794301319306860f, + 0.324584924812532150f, -0.945856557086983910f, 0.324403553123280290f, + -0.945918778078219110f, + 0.324222169506637130f, -0.945980964290724760f, 0.324040773969271450f, + -0.946043115722214560f, + 0.323859366517852960f, -0.946105232370403340f, 0.323677947159051180f, + -0.946167314233007370f, + 0.323496515899536760f, -0.946229361307743820f, 0.323315072745980150f, + -0.946291373592331510f, + 0.323133617705052330f, -0.946353351084490590f, 0.322952150783425370f, + -0.946415293781942110f, + 0.322770671987770710f, -0.946477201682408680f, 0.322589181324761390f, + -0.946539074783614100f, + 0.322407678801070020f, -0.946600913083283530f, 0.322226164423369650f, + -0.946662716579143360f, + 0.322044638198334620f, -0.946724485268921170f, 0.321863100132638580f, + -0.946786219150346000f, + 0.321681550232956640f, -0.946847918221148000f, 0.321499988505963450f, + -0.946909582479058760f, + 0.321318414958334910f, -0.946971211921810880f, 0.321136829596746780f, + -0.947032806547138620f, + 0.320955232427875210f, -0.947094366352777220f, 0.320773623458397440f, + -0.947155891336463270f, + 0.320592002694990330f, -0.947217381495934820f, 0.320410370144331880f, + -0.947278836828930880f, + 0.320228725813100020f, -0.947340257333191940f, 0.320047069707973140f, + -0.947401643006459900f, + 0.319865401835630610f, -0.947462993846477700f, 0.319683722202751370f, + -0.947524309850989570f, + 0.319502030816015750f, -0.947585591017741090f, 0.319320327682103720f, + -0.947646837344479190f, + 0.319138612807695900f, -0.947708048828952100f, 0.318956886199473770f, + -0.947769225468909180f, + 0.318775147864118480f, -0.947830367262101010f, 0.318593397808312470f, + -0.947891474206279730f, + 0.318411636038737960f, -0.947952546299198560f, 0.318229862562077580f, + -0.948013583538612200f, + 0.318048077385015060f, -0.948074585922276230f, 0.317866280514233660f, + -0.948135553447947980f, + 0.317684471956418020f, -0.948196486113385580f, 0.317502651718252260f, + -0.948257383916349060f, + 0.317320819806421790f, -0.948318246854599090f, 0.317138976227611890f, + -0.948379074925898120f, + 0.316957120988508150f, -0.948439868128009620f, 0.316775254095797380f, + -0.948500626458698260f, + 0.316593375556165850f, -0.948561349915730270f, 0.316411485376301090f, + -0.948622038496872990f, + 0.316229583562890490f, -0.948682692199895090f, 0.316047670122621860f, + -0.948743311022566480f, + 0.315865745062184070f, -0.948803894962658380f, 0.315683808388265600f, + -0.948864444017943340f, + 0.315501860107556040f, -0.948924958186195160f, 0.315319900226745050f, + -0.948985437465188710f, + 0.315137928752522440f, -0.949045881852700560f, 0.314955945691579250f, + -0.949106291346508260f, + 0.314773951050606070f, -0.949166665944390700f, 0.314591944836294710f, + -0.949227005644128210f, + 0.314409927055336820f, -0.949287310443502010f, 0.314227897714424500f, + -0.949347580340295210f, + 0.314045856820250820f, -0.949407815332291460f, 0.313863804379508500f, + -0.949468015417276550f, + 0.313681740398891570f, -0.949528180593036670f, 0.313499664885093450f, + -0.949588310857359950f, + 0.313317577844809070f, -0.949648406208035480f, 0.313135479284732950f, + -0.949708466642853800f, + 0.312953369211560200f, -0.949768492159606680f, 0.312771247631986880f, + -0.949828482756087000f, + 0.312589114552708660f, -0.949888438430089300f, 0.312406969980422500f, + -0.949948359179409010f, + 0.312224813921825050f, -0.950008245001843000f, 0.312042646383613510f, + -0.950068095895189590f, + 0.311860467372486130f, -0.950127911857248100f, 0.311678276895140550f, + -0.950187692885819280f, + 0.311496074958275970f, -0.950247438978705230f, 0.311313861568591090f, + -0.950307150133709140f, + 0.311131636732785270f, -0.950366826348635780f, 0.310949400457558760f, + -0.950426467621290900f, + 0.310767152749611470f, -0.950486073949481700f, 0.310584893615644560f, + -0.950545645331016600f, + 0.310402623062358880f, -0.950605181763705230f, 0.310220341096455910f, + -0.950664683245358910f, + 0.310038047724638000f, -0.950724149773789610f, 0.309855742953607130f, + -0.950783581346811070f, + 0.309673426790066490f, -0.950842977962238160f, 0.309491099240719050f, + -0.950902339617887060f, + 0.309308760312268780f, -0.950961666311575080f, 0.309126410011419550f, + -0.951020958041121080f, + 0.308944048344875710f, -0.951080214804345010f, 0.308761675319342570f, + -0.951139436599068190f, + 0.308579290941525030f, -0.951198623423113230f, 0.308396895218129240f, + -0.951257775274304000f, + 0.308214488155861220f, -0.951316892150465550f, 0.308032069761427330f, + -0.951375974049424420f, + 0.307849640041534980f, -0.951435020969008340f, 0.307667199002891190f, + -0.951494032907046370f, + 0.307484746652204160f, -0.951553009861368590f, 0.307302282996181950f, + -0.951611951829806730f, + 0.307119808041533100f, -0.951670858810193860f, 0.306937321794967020f, + -0.951729730800363720f, + 0.306754824263192780f, -0.951788567798152130f, 0.306572315452920800f, + -0.951847369801395620f, + 0.306389795370861080f, -0.951906136807932230f, 0.306207264023724280f, + -0.951964868815601380f, + 0.306024721418221900f, -0.952023565822243570f, 0.305842167561065080f, + -0.952082227825700620f, + 0.305659602458966230f, -0.952140854823815830f, 0.305477026118637360f, + -0.952199446814433580f, + 0.305294438546791720f, -0.952258003795399600f, 0.305111839750142220f, + -0.952316525764560830f, + 0.304929229735402430f, -0.952375012719765880f, 0.304746608509286640f, + -0.952433464658864030f, + 0.304563976078509050f, -0.952491881579706320f, 0.304381332449784940f, + -0.952550263480144930f, + 0.304198677629829270f, -0.952608610358033240f, 0.304016011625357570f, + -0.952666922211226170f, + 0.303833334443086470f, -0.952725199037579570f, 0.303650646089731910f, + -0.952783440834950920f, + 0.303467946572011370f, -0.952841647601198720f, 0.303285235896641910f, + -0.952899819334182880f, + 0.303102514070341060f, -0.952957956031764700f, 0.302919781099827420f, + -0.953016057691806530f, + 0.302737036991819140f, -0.953074124312172200f, 0.302554281753035670f, + -0.953132155890726750f, + 0.302371515390196130f, -0.953190152425336560f, 0.302188737910020040f, + -0.953248113913869320f, + 0.302005949319228200f, -0.953306040354193750f, 0.301823149624540650f, + -0.953363931744180330f, + 0.301640338832678880f, -0.953421788081700310f, 0.301457516950363940f, + -0.953479609364626610f, + 0.301274683984318000f, -0.953537395590833280f, 0.301091839941263210f, + -0.953595146758195680f, + 0.300908984827921890f, -0.953652862864590500f, 0.300726118651017620f, + -0.953710543907895560f, + 0.300543241417273400f, -0.953768189885990330f, 0.300360353133413580f, + -0.953825800796755050f, + 0.300177453806162120f, -0.953883376638071770f, 0.299994543442243580f, + -0.953940917407823500f, + 0.299811622048383460f, -0.953998423103894490f, 0.299628689631306790f, + -0.954055893724170660f, + 0.299445746197739950f, -0.954113329266538800f, 0.299262791754409010f, + -0.954170729728887280f, + 0.299079826308040480f, -0.954228095109105670f, 0.298896849865361910f, + -0.954285425405084650f, + 0.298713862433100390f, -0.954342720614716480f, 0.298530864017984230f, + -0.954399980735894490f, + 0.298347854626741570f, -0.954457205766513490f, 0.298164834266100910f, + -0.954514395704469500f, + 0.297981802942791920f, -0.954571550547659630f, 0.297798760663543550f, + -0.954628670293982680f, + 0.297615707435086310f, -0.954685754941338340f, 0.297432643264150030f, + -0.954742804487627940f, + 0.297249568157465890f, -0.954799818930753720f, 0.297066482121764840f, + -0.954856798268619580f, + 0.296883385163778270f, -0.954913742499130520f, 0.296700277290238460f, + -0.954970651620192790f, + 0.296517158507877410f, -0.955027525629714160f, 0.296334028823428240f, + -0.955084364525603410f, + 0.296150888243623960f, -0.955141168305770670f, 0.295967736775197890f, + -0.955197936968127710f, + 0.295784574424884370f, -0.955254670510586990f, 0.295601401199417360f, + -0.955311368931062720f, + 0.295418217105532070f, -0.955368032227470240f, 0.295235022149963390f, + -0.955424660397726330f, + 0.295051816339446720f, -0.955481253439748770f, 0.294868599680718380f, + -0.955537811351456770f, + 0.294685372180514330f, -0.955594334130771110f, 0.294502133845571720f, + -0.955650821775613220f, + 0.294318884682627570f, -0.955707274283906560f, 0.294135624698419080f, + -0.955763691653575440f, + 0.293952353899684770f, -0.955820073882545420f, 0.293769072293162400f, + -0.955876420968743590f, + 0.293585779885591310f, -0.955932732910098170f, 0.293402476683710060f, + -0.955989009704538930f, + 0.293219162694258680f, -0.956045251349996410f, 0.293035837923976920f, + -0.956101457844403040f, + 0.292852502379604810f, -0.956157629185692140f, 0.292669156067883570f, + -0.956213765371798470f, + 0.292485798995553830f, -0.956269866400658140f, 0.292302431169357610f, + -0.956325932270208230f, + 0.292119052596036540f, -0.956381962978387620f, 0.291935663282332780f, + -0.956437958523136180f, + 0.291752263234989370f, -0.956493918902394990f, 0.291568852460749040f, + -0.956549844114106820f, + 0.291385430966355720f, -0.956605734156215080f, 0.291201998758553020f, + -0.956661589026664980f, + 0.291018555844085090f, -0.956717408723403050f, 0.290835102229696940f, + -0.956773193244376930f, + 0.290651637922133220f, -0.956828942587535370f, 0.290468162928139870f, + -0.956884656750828900f, + 0.290284677254462330f, -0.956940335732208940f, 0.290101180907847140f, + -0.956995979529628230f, + 0.289917673895040860f, -0.957051588141040970f, 0.289734156222790250f, + -0.957107161564402790f, + 0.289550627897843140f, -0.957162699797670100f, 0.289367088926946960f, + -0.957218202838801210f, + 0.289183539316850310f, -0.957273670685755200f, 0.288999979074301530f, + -0.957329103336492790f, + 0.288816408206049480f, -0.957384500788975860f, 0.288632826718843940f, + -0.957439863041167570f, + 0.288449234619434170f, -0.957495190091032570f, 0.288265631914570830f, + -0.957550481936536470f, + 0.288082018611004300f, -0.957605738575646240f, 0.287898394715485170f, + -0.957660960006330610f, + 0.287714760234765280f, -0.957716146226558870f, 0.287531115175595930f, + -0.957771297234302320f, + 0.287347459544729570f, -0.957826413027532910f, 0.287163793348918560f, + -0.957881493604224250f, + 0.286980116594915570f, -0.957936538962351420f, 0.286796429289474190f, + -0.957991549099890370f, + 0.286612731439347790f, -0.958046524014818600f, 0.286429023051290750f, + -0.958101463705114620f, + 0.286245304132057120f, -0.958156368168758820f, 0.286061574688402100f, + -0.958211237403732260f, + 0.285877834727080730f, -0.958266071408017670f, 0.285694084254848320f, + -0.958320870179598880f, + 0.285510323278461380f, -0.958375633716461170f, 0.285326551804675810f, + -0.958430362016591040f, + 0.285142769840248720f, -0.958485055077976100f, 0.284958977391937150f, + -0.958539712898605730f, + 0.284775174466498300f, -0.958594335476470220f, 0.284591361070690550f, + -0.958648922809561040f, + 0.284407537211271820f, -0.958703474895871600f, 0.284223702895001100f, + -0.958757991733395710f, + 0.284039858128637360f, -0.958812473320129200f, 0.283856002918939750f, + -0.958866919654069010f, + 0.283672137272668550f, -0.958921330733213060f, 0.283488261196583550f, + -0.958975706555561080f, + 0.283304374697445790f, -0.959030047119113550f, 0.283120477782015990f, + -0.959084352421872730f, + 0.282936570457055390f, -0.959138622461841890f, 0.282752652729326040f, + -0.959192857237025740f, + 0.282568724605589740f, -0.959247056745430090f, 0.282384786092609420f, + -0.959301220985062210f, + 0.282200837197147500f, -0.959355349953930790f, 0.282016877925967690f, + -0.959409443650045550f, + 0.281832908285833460f, -0.959463502071417510f, 0.281648928283508680f, + -0.959517525216059260f, + 0.281464937925758050f, -0.959571513081984520f, 0.281280937219346110f, + -0.959625465667208300f, + 0.281096926171038320f, -0.959679382969746750f, 0.280912904787600120f, + -0.959733264987617680f, + 0.280728873075797190f, -0.959787111718839900f, 0.280544831042396360f, + -0.959840923161433660f, + 0.280360778694163810f, -0.959894699313420530f, 0.280176716037867040f, + -0.959948440172823210f, + 0.279992643080273380f, -0.960002145737665850f, 0.279808559828150390f, + -0.960055816005973890f, + 0.279624466288266700f, -0.960109450975773940f, 0.279440362467390510f, + -0.960163050645094000f, + 0.279256248372291240f, -0.960216615011963430f, 0.279072124009737970f, + -0.960270144074412800f, + 0.278887989386500280f, -0.960323637830473920f, 0.278703844509348600f, + -0.960377096278180130f, + 0.278519689385053060f, -0.960430519415565790f, 0.278335524020384970f, + -0.960483907240666790f, + 0.278151348422115090f, -0.960537259751520050f, 0.277967162597015430f, + -0.960590576946164120f, + 0.277782966551857800f, -0.960643858822638470f, 0.277598760293414290f, + -0.960697105378984450f, + 0.277414543828458200f, -0.960750316613243950f, 0.277230317163762120f, + -0.960803492523460760f, + 0.277046080306099950f, -0.960856633107679660f, 0.276861833262245390f, + -0.960909738363946770f, + 0.276677576038972420f, -0.960962808290309780f, 0.276493308643056100f, + -0.961015842884817230f, + 0.276309031081271030f, -0.961068842145519350f, 0.276124743360392890f, + -0.961121806070467380f, + 0.275940445487197320f, -0.961174734657714080f, 0.275756137468460120f, + -0.961227627905313460f, + 0.275571819310958250f, -0.961280485811320640f, 0.275387491021468140f, + -0.961333308373792270f, + 0.275203152606767370f, -0.961386095590786250f, 0.275018804073633380f, + -0.961438847460361570f, + 0.274834445428843940f, -0.961491563980579000f, 0.274650076679177790f, + -0.961544245149499990f, + 0.274465697831413220f, -0.961596890965187860f, 0.274281308892329710f, + -0.961649501425706820f, + 0.274096909868706330f, -0.961702076529122540f, 0.273912500767323320f, + -0.961754616273502010f, + 0.273728081594960650f, -0.961807120656913540f, 0.273543652358398730f, + -0.961859589677426570f, + 0.273359213064418790f, -0.961912023333112100f, 0.273174763719801870f, + -0.961964421622042320f, + 0.272990304331329980f, -0.962016784542290560f, 0.272805834905784920f, + -0.962069112091931580f, + 0.272621355449948980f, -0.962121404269041580f, 0.272436865970605350f, + -0.962173661071697770f, + 0.272252366474536660f, -0.962225882497979020f, 0.272067856968526980f, + -0.962278068545965090f, + 0.271883337459359890f, -0.962330219213737400f, 0.271698807953819510f, + -0.962382334499378380f, + 0.271514268458690810f, -0.962434414400971990f, 0.271329718980758420f, + -0.962486458916603450f, + 0.271145159526808070f, -0.962538468044359160f, 0.270960590103625330f, + -0.962590441782326780f, + 0.270776010717996010f, -0.962642380128595710f, 0.270591421376707050f, + -0.962694283081255930f, + 0.270406822086544820f, -0.962746150638399410f, 0.270222212854296930f, + -0.962797982798119010f, + 0.270037593686750510f, -0.962849779558509030f, 0.269852964590693910f, + -0.962901540917665000f, + 0.269668325572915200f, -0.962953266873683880f, 0.269483676640202840f, + -0.963004957424663850f, + 0.269299017799346230f, -0.963056612568704340f, 0.269114349057134330f, + -0.963108232303906190f, + 0.268929670420357310f, -0.963159816628371360f, 0.268744981895805090f, + -0.963211365540203480f, + 0.268560283490267890f, -0.963262879037507070f, 0.268375575210537010f, + -0.963314357118388090f, + 0.268190857063403180f, -0.963365799780954050f, 0.268006129055658350f, + -0.963417207023313350f, + 0.267821391194094320f, -0.963468578843575950f, 0.267636643485503090f, + -0.963519915239853140f, + 0.267451885936677740f, -0.963571216210257210f, 0.267267118554410930f, + -0.963622481752902220f, + 0.267082341345496350f, -0.963673711865903230f, 0.266897554316727510f, + -0.963724906547376410f, + 0.266712757474898420f, -0.963776065795439840f, 0.266527950826803810f, + -0.963827189608212340f, + 0.266343134379238180f, -0.963878277983814200f, 0.266158308138997050f, + -0.963929330920367140f, + 0.265973472112875530f, -0.963980348415994110f, 0.265788626307669970f, + -0.964031330468819280f, + 0.265603770730176440f, -0.964082277076968140f, 0.265418905387191260f, + -0.964133188238567640f, + 0.265234030285511900f, -0.964184063951745720f, 0.265049145431935200f, + -0.964234904214632200f, + 0.264864250833259320f, -0.964285709025357370f, 0.264679346496282050f, + -0.964336478382053720f, + 0.264494432427801630f, -0.964387212282854290f, 0.264309508634617220f, + -0.964437910725893910f, + 0.264124575123527490f, -0.964488573709308410f, 0.263939631901332410f, + -0.964539201231235150f, + 0.263754678974831510f, -0.964589793289812650f, 0.263569716350824880f, + -0.964640349883180930f, + 0.263384744036113390f, -0.964690871009480920f, 0.263199762037497560f, + -0.964741356666855340f, + 0.263014770361779060f, -0.964791806853447900f, 0.262829769015759330f, + -0.964842221567403510f, + 0.262644758006240100f, -0.964892600806868890f, 0.262459737340024090f, + -0.964942944569991410f, + 0.262274707023913590f, -0.964993252854920320f, 0.262089667064712100f, + -0.965043525659805890f, + 0.261904617469222560f, -0.965093762982799590f, 0.261719558244249080f, + -0.965143964822054450f, + 0.261534489396595630f, -0.965194131175724720f, 0.261349410933066350f, + -0.965244262041965780f, + 0.261164322860466590f, -0.965294357418934660f, 0.260979225185601020f, + -0.965344417304789370f, + 0.260794117915275570f, -0.965394441697689400f, 0.260609001056295920f, + -0.965444430595795430f, + 0.260423874615468010f, -0.965494383997269500f, 0.260238738599598950f, + -0.965544301900275070f, + 0.260053593015495130f, -0.965594184302976830f, 0.259868437869964330f, + -0.965644031203540590f, + 0.259683273169813930f, -0.965693842600133690f, 0.259498098921851660f, + -0.965743618490924830f, + 0.259312915132886350f, -0.965793358874083570f, 0.259127721809726150f, + -0.965843063747781510f, + 0.258942518959180580f, -0.965892733110190860f, 0.258757306588058840f, + -0.965942366959485540f, + 0.258572084703170390f, -0.965991965293840570f, 0.258386853311325710f, + -0.966041528111432400f, + 0.258201612419334870f, -0.966091055410438830f, 0.258016362034009070f, + -0.966140547189038750f, + 0.257831102162158930f, -0.966190003445412620f, 0.257645832810596440f, + -0.966239424177741890f, + 0.257460553986133210f, -0.966288809384209580f, 0.257275265695581120f, + -0.966338159063000130f, + 0.257089967945753230f, -0.966387473212298790f, 0.256904660743461850f, + -0.966436751830292650f, + 0.256719344095520720f, -0.966485994915169840f, 0.256534018008743200f, + -0.966535202465119700f, + 0.256348682489942910f, -0.966584374478333120f, 0.256163337545934570f, + -0.966633510953002100f, + 0.255977983183532380f, -0.966682611887320190f, 0.255792619409551670f, + -0.966731677279481840f, + 0.255607246230807550f, -0.966780707127683270f, 0.255421863654115460f, + -0.966829701430121810f, + 0.255236471686291820f, -0.966878660184995910f, 0.255051070334152530f, + -0.966927583390505660f, + 0.254865659604514630f, -0.966976471044852070f, 0.254680239504194990f, + -0.967025323146237900f, + 0.254494810040010790f, -0.967074139692867040f, 0.254309371218780110f, + -0.967122920682944360f, + 0.254123923047320620f, -0.967171666114676640f, 0.253938465532451140f, + -0.967220375986271310f, + 0.253752998680989940f, -0.967269050295937790f, 0.253567522499756610f, + -0.967317689041886310f, + 0.253382036995570270f, -0.967366292222328510f, 0.253196542175250560f, + -0.967414859835477480f, + 0.253011038045617980f, -0.967463391879547440f, 0.252825524613492610f, + -0.967511888352754150f, + 0.252640001885695580f, -0.967560349253314360f, 0.252454469869047900f, + -0.967608774579446380f, + 0.252268928570370810f, -0.967657164329369880f, 0.252083377996486560f, + -0.967705518501305480f, + 0.251897818154216910f, -0.967753837093475510f, 0.251712249050384750f, + -0.967802120104103270f, + 0.251526670691812780f, -0.967850367531413620f, 0.251341083085323880f, + -0.967898579373632660f, + 0.251155486237742030f, -0.967946755628987800f, 0.250969880155890720f, + -0.967994896295707670f, + 0.250784264846594550f, -0.968043001372022260f, 0.250598640316677830f, + -0.968091070856162970f, + 0.250413006572965280f, -0.968139104746362330f, 0.250227363622282540f, + -0.968187103040854420f, + 0.250041711471454650f, -0.968235065737874320f, 0.249856050127308050f, + -0.968282992835658660f, + 0.249670379596668520f, -0.968330884332445300f, 0.249484699886363010f, + -0.968378740226473300f, + 0.249299011003218300f, -0.968426560515983190f, 0.249113312954061360f, + -0.968474345199216820f, + 0.248927605745720260f, -0.968522094274417270f, 0.248741889385022420f, + -0.968569807739828930f, + 0.248556163878796620f, -0.968617485593697540f, 0.248370429233871150f, + -0.968665127834269950f, + 0.248184685457074780f, -0.968712734459794780f, 0.247998932555237220f, + -0.968760305468521430f, + 0.247813170535187620f, -0.968807840858700970f, 0.247627399403756330f, + -0.968855340628585580f, + 0.247441619167773440f, -0.968902804776428870f, 0.247255829834069320f, + -0.968950233300485800f, + 0.247070031409475370f, -0.968997626199012310f, 0.246884223900822430f, + -0.969044983470266240f, + 0.246698407314942500f, -0.969092305112506100f, 0.246512581658667380f, + -0.969139591123992280f, + 0.246326746938829060f, -0.969186841502985950f, 0.246140903162260640f, + -0.969234056247750050f, + 0.245955050335794590f, -0.969281235356548530f, 0.245769188466264670f, + -0.969328378827646660f, + 0.245583317560504000f, -0.969375486659311280f, 0.245397437625346990f, + -0.969422558849810320f, + 0.245211548667627680f, -0.969469595397412950f, 0.245025650694180470f, + -0.969516596300390000f, + 0.244839743711840750f, -0.969563561557013180f, 0.244653827727443320f, + -0.969610491165555870f, + 0.244467902747824210f, -0.969657385124292450f, 0.244281968779819170f, + -0.969704243431498750f, + 0.244096025830264210f, -0.969751066085452140f, 0.243910073905996370f, + -0.969797853084430890f, + 0.243724113013852130f, -0.969844604426714830f, 0.243538143160669180f, + -0.969891320110585100f, + 0.243352164353284880f, -0.969938000134323960f, 0.243166176598536930f, + -0.969984644496215240f, + 0.242980179903263980f, -0.970031253194543970f, 0.242794174274304190f, + -0.970077826227596420f, + 0.242608159718496890f, -0.970124363593660280f, 0.242422136242681050f, + -0.970170865291024360f, + 0.242236103853696040f, -0.970217331317979160f, 0.242050062558382180f, + -0.970263761672816140f, + 0.241864012363579210f, -0.970310156353828110f, 0.241677953276128090f, + -0.970356515359309450f, + 0.241491885302869300f, -0.970402838687555500f, 0.241305808450644390f, + -0.970449126336863090f, + 0.241119722726294730f, -0.970495378305530450f, 0.240933628136661910f, + -0.970541594591857070f, + 0.240747524688588540f, -0.970587775194143630f, 0.240561412388916620f, + -0.970633920110692160f, + 0.240375291244489500f, -0.970680029339806130f, 0.240189161262150040f, + -0.970726102879790110f, + 0.240003022448741500f, -0.970772140728950350f, 0.239816874811108110f, + -0.970818142885593870f, + 0.239630718356093560f, -0.970864109348029470f, 0.239444553090542720f, + -0.970910040114567050f, + 0.239258379021300120f, -0.970955935183517970f, 0.239072196155210660f, + -0.971001794553194690f, + 0.238886004499120170f, -0.971047618221911100f, 0.238699804059873950f, + -0.971093406187982460f, + 0.238513594844318500f, -0.971139158449725090f, 0.238327376859299970f, + -0.971184875005457030f, + 0.238141150111664870f, -0.971230555853497380f, 0.237954914608260650f, + -0.971276200992166490f, + 0.237768670355934210f, -0.971321810419786160f, 0.237582417361533650f, + -0.971367384134679490f, + 0.237396155631906550f, -0.971412922135170940f, 0.237209885173901620f, + -0.971458424419585960f, + 0.237023605994367340f, -0.971503890986251780f, 0.236837318100152380f, + -0.971549321833496630f, + 0.236651021498106460f, -0.971594716959650160f, 0.236464716195078750f, + -0.971640076363043390f, + 0.236278402197919620f, -0.971685400042008540f, 0.236092079513479050f, + -0.971730687994879160f, + 0.235905748148607370f, -0.971775940219990140f, 0.235719408110155930f, + -0.971821156715677700f, + 0.235533059404975460f, -0.971866337480279400f, 0.235346702039917920f, + -0.971911482512134000f, + 0.235160336021834860f, -0.971956591809581600f, 0.234973961357578310f, + -0.972001665370963890f, + 0.234787578054001080f, -0.972046703194623380f, 0.234601186117955550f, + -0.972091705278904430f, + 0.234414785556295250f, -0.972136671622152120f, 0.234228376375873380f, + -0.972181602222713440f, + 0.234041958583543460f, -0.972226497078936270f, 0.233855532186159950f, + -0.972271356189170040f, + 0.233669097190576820f, -0.972316179551765300f, 0.233482653603649170f, + -0.972360967165074140f, + 0.233296201432231560f, -0.972405719027449770f, 0.233109740683179740f, + -0.972450435137246830f, + 0.232923271363349120f, -0.972495115492821190f, 0.232736793479595420f, + -0.972539760092530180f, + 0.232550307038775330f, -0.972584368934732210f, 0.232363812047745010f, + -0.972628942017787270f, + 0.232177308513361770f, -0.972673479340056430f, 0.231990796442482580f, + -0.972717980899902250f, + 0.231804275841964780f, -0.972762446695688570f, 0.231617746718666580f, + -0.972806876725780370f, + 0.231431209079445730f, -0.972851270988544180f, 0.231244662931161110f, + -0.972895629482347760f, + 0.231058108280671280f, -0.972939952205560070f, 0.230871545134835070f, + -0.972984239156551740f, + 0.230684973500512310f, -0.973028490333694100f, 0.230498393384562320f, + -0.973072705735360530f, + 0.230311804793845530f, -0.973116885359925130f, 0.230125207735222020f, + -0.973161029205763530f, + 0.229938602215552260f, -0.973205137271252800f, 0.229751988241697600f, + -0.973249209554771120f, + 0.229565365820518870f, -0.973293246054698250f, 0.229378734958878120f, + -0.973337246769414800f, + 0.229192095663636740f, -0.973381211697303290f, 0.229005447941657390f, + -0.973425140836747030f, + 0.228818791799802360f, -0.973469034186130950f, 0.228632127244934230f, + -0.973512891743841370f, + 0.228445454283916550f, -0.973556713508265560f, 0.228258772923612350f, + -0.973600499477792370f, + 0.228072083170885790f, -0.973644249650811870f, 0.227885385032600700f, + -0.973687964025715670f, + 0.227698678515621170f, -0.973731642600896400f, 0.227511963626812390f, + -0.973775285374748000f, + 0.227325240373038830f, -0.973818892345666100f, 0.227138508761166260f, + -0.973862463512047300f, + 0.226951768798059980f, -0.973905998872289460f, 0.226765020490585720f, + -0.973949498424792170f, + 0.226578263845610110f, -0.973992962167955830f, 0.226391498869999210f, + -0.974036390100182610f, + 0.226204725570620270f, -0.974079782219875680f, 0.226017943954340190f, + -0.974123138525439520f, + 0.225831154028026200f, -0.974166459015280320f, 0.225644355798546440f, + -0.974209743687805110f, + 0.225457549272768540f, -0.974252992541422500f, 0.225270734457561240f, + -0.974296205574542330f, + 0.225083911359792780f, -0.974339382785575860f, 0.224897079986332540f, + -0.974382524172935470f, + 0.224710240344049570f, -0.974425629735034990f, 0.224523392439813170f, + -0.974468699470289580f, + 0.224336536280493690f, -0.974511733377115720f, 0.224149671872960840f, + -0.974554731453931230f, + 0.223962799224085520f, -0.974597693699155050f, 0.223775918340738290f, + -0.974640620111207560f, + 0.223589029229790020f, -0.974683510688510670f, 0.223402131898112480f, + -0.974726365429487320f, + 0.223215226352576960f, -0.974769184332561770f, 0.223028312600055870f, + -0.974811967396159830f, + 0.222841390647421280f, -0.974854714618708430f, 0.222654460501545550f, + -0.974897425998635820f, + 0.222467522169301990f, -0.974940101534371720f, 0.222280575657563370f, + -0.974982741224347140f, + 0.222093620973203590f, -0.975025345066994120f, 0.221906658123096260f, + -0.975067913060746360f, + 0.221719687114115240f, -0.975110445204038890f, 0.221532707953135340f, + -0.975152941495307620f, + 0.221345720647030810f, -0.975195401932990370f, 0.221158725202677100f, + -0.975237826515525820f, + 0.220971721626949060f, -0.975280215241354220f, 0.220784709926722670f, + -0.975322568108916930f, + 0.220597690108873650f, -0.975364885116656870f, 0.220410662180277940f, + -0.975407166263018270f, + 0.220223626147812460f, -0.975449411546446380f, 0.220036582018353550f, + -0.975491620965388110f, + 0.219849529798778750f, -0.975533794518291360f, 0.219662469495965180f, + -0.975575932203605610f, + 0.219475401116790340f, -0.975618034019781750f, 0.219288324668132580f, + -0.975660099965271590f, + 0.219101240156869770f, -0.975702130038528570f, 0.218914147589880900f, + -0.975744124238007270f, + 0.218727046974044600f, -0.975786082562163930f, 0.218539938316239830f, + -0.975828005009455550f, + 0.218352821623346430f, -0.975869891578341030f, 0.218165696902243770f, + -0.975911742267280170f, + 0.217978564159812290f, -0.975953557074734300f, 0.217791423402932120f, + -0.975995335999165880f, + 0.217604274638483670f, -0.976037079039039020f, 0.217417117873348300f, + -0.976078786192818850f, + 0.217229953114406790f, -0.976120457458971910f, 0.217042780368541080f, + -0.976162092835966110f, + 0.216855599642632570f, -0.976203692322270560f, 0.216668410943563790f, + -0.976245255916355800f, + 0.216481214278216900f, -0.976286783616693630f, 0.216294009653474370f, + -0.976328275421757260f, + 0.216106797076219600f, -0.976369731330021140f, 0.215919576553335460f, + -0.976411151339961040f, + 0.215732348091705940f, -0.976452535450054060f, 0.215545111698214660f, + -0.976493883658778540f, + 0.215357867379745550f, -0.976535195964614470f, 0.215170615143183500f, + -0.976576472366042610f, + 0.214983354995412820f, -0.976617712861545640f, 0.214796086943318920f, + -0.976658917449606980f, + 0.214608810993786920f, -0.976700086128711840f, 0.214421527153702190f, + -0.976741218897346550f, + 0.214234235429951100f, -0.976782315753998650f, 0.214046935829419330f, + -0.976823376697157240f, + 0.213859628358993830f, -0.976864401725312640f, 0.213672313025561140f, + -0.976905390836956490f, + 0.213484989836008080f, -0.976946344030581560f, 0.213297658797222430f, + -0.976987261304682390f, + 0.213110319916091360f, -0.977028142657754390f, 0.212922973199503260f, + -0.977068988088294450f, + 0.212735618654345870f, -0.977109797594800880f, 0.212548256287508120f, + -0.977150571175773200f, + 0.212360886105878580f, -0.977191308829712280f, 0.212173508116346080f, + -0.977232010555120320f, + 0.211986122325800410f, -0.977272676350500860f, 0.211798728741130820f, + -0.977313306214358750f, + 0.211611327369227610f, -0.977353900145199960f, 0.211423918216980810f, + -0.977394458141532250f, + 0.211236501291280710f, -0.977434980201864260f, 0.211049076599018500f, + -0.977475466324706050f, + 0.210861644147084830f, -0.977515916508569280f, 0.210674203942371490f, + -0.977556330751966460f, + 0.210486755991769890f, -0.977596709053411780f, 0.210299300302171750f, + -0.977637051411420770f, + 0.210111836880469720f, -0.977677357824509930f, 0.209924365733555860f, + -0.977717628291197570f, + 0.209736886868323370f, -0.977757862810002760f, 0.209549400291665110f, + -0.977798061379446360f, + 0.209361906010474190f, -0.977838223998050430f, 0.209174404031644700f, + -0.977878350664338150f, + 0.208986894362070070f, -0.977918441376834370f, 0.208799377008644980f, + -0.977958496134064830f, + 0.208611851978263460f, -0.977998514934557140f, 0.208424319277820650f, + -0.978038497776839600f, + 0.208236778914211470f, -0.978078444659442380f, 0.208049230894330940f, + -0.978118355580896660f, + 0.207861675225075150f, -0.978158230539735050f, 0.207674111913339540f, + -0.978198069534491400f, + 0.207486540966020700f, -0.978237872563701090f, 0.207298962390014880f, + -0.978277639625900420f, + 0.207111376192218560f, -0.978317370719627650f, 0.206923782379529210f, + -0.978357065843421640f, + 0.206736180958843660f, -0.978396724995823090f, 0.206548571937059940f, + -0.978436348175373730f, + 0.206360955321075680f, -0.978475935380616830f, 0.206173331117788770f, + -0.978515486610096910f, + 0.205985699334098050f, -0.978555001862359550f, 0.205798059976901760f, + -0.978594481135952270f, + 0.205610413053099320f, -0.978633924429423100f, 0.205422758569589780f, + -0.978673331741322210f, + 0.205235096533272380f, -0.978712703070200420f, 0.205047426951047380f, + -0.978752038414610340f, + 0.204859749829814420f, -0.978791337773105670f, 0.204672065176474290f, + -0.978830601144241470f, + 0.204484372997927180f, -0.978869828526574120f, 0.204296673301074430f, + -0.978909019918661310f, + 0.204108966092817010f, -0.978948175319062200f, 0.203921251380056150f, + -0.978987294726337050f, + 0.203733529169694010f, -0.979026378139047580f, 0.203545799468632190f, + -0.979065425555756930f, + 0.203358062283773370f, -0.979104436975029250f, 0.203170317622019920f, + -0.979143412395430230f, + 0.202982565490274460f, -0.979182351815526930f, 0.202794805895440550f, + -0.979221255233887700f, + 0.202607038844421110f, -0.979260122649082020f, 0.202419264344120220f, + -0.979298954059681040f, + 0.202231482401441620f, -0.979337749464256780f, 0.202043693023289280f, + -0.979376508861383170f, + 0.201855896216568160f, -0.979415232249634780f, 0.201668091988182500f, + -0.979453919627588210f, + 0.201480280345037820f, -0.979492570993820700f, 0.201292461294039190f, + -0.979531186346911390f, + 0.201104634842091960f, -0.979569765685440520f, 0.200916800996102370f, + -0.979608309007989450f, + 0.200728959762976140f, -0.979646816313141210f, 0.200541111149620090f, + -0.979685287599479930f, + 0.200353255162940420f, -0.979723722865591170f, 0.200165391809844500f, + -0.979762122110061640f, + 0.199977521097239290f, -0.979800485331479680f, 0.199789643032032120f, + -0.979838812528434740f, + 0.199601757621131050f, -0.979877103699517640f, 0.199413864871443750f, + -0.979915358843320480f, + 0.199225964789878890f, -0.979953577958436740f, 0.199038057383344820f, + -0.979991761043461200f, + 0.198850142658750120f, -0.980029908096989980f, 0.198662220623004320f, + -0.980068019117620650f, + 0.198474291283016360f, -0.980106094103951770f, 0.198286354645696270f, + -0.980144133054583590f, + 0.198098410717953730f, -0.980182135968117320f, 0.197910459506698720f, + -0.980220102843155970f, + 0.197722501018842030f, -0.980258033678303550f, 0.197534535261294000f, + -0.980295928472165290f, + 0.197346562240966000f, -0.980333787223347960f, 0.197158581964769040f, + -0.980371609930459690f, + 0.196970594439614370f, -0.980409396592109910f, 0.196782599672414240f, + -0.980447147206909060f, + 0.196594597670080220f, -0.980484861773469380f, 0.196406588439525050f, + -0.980522540290404090f, + 0.196218571987660850f, -0.980560182756327950f, 0.196030548321400880f, + -0.980597789169856850f, + 0.195842517447657990f, -0.980635359529608120f, 0.195654479373345370f, + -0.980672893834200530f, + 0.195466434105377090f, -0.980710392082253970f, 0.195278381650666520f, + -0.980747854272389750f, + 0.195090322016128330f, -0.980785280403230430f, 0.194902255208676660f, + -0.980822670473399990f, + 0.194714181235225990f, -0.980860024481523870f, 0.194526100102691720f, + -0.980897342426228390f, + 0.194338011817988600f, -0.980934624306141640f, 0.194149916388032530f, + -0.980971870119892840f, + 0.193961813819739010f, -0.981009079866112630f, 0.193773704120023840f, + -0.981046253543432780f, + 0.193585587295803750f, -0.981083391150486590f, 0.193397463353994740f, + -0.981120492685908730f, + 0.193209332301514080f, -0.981157558148334830f, 0.193021194145278320f, + -0.981194587536402320f, + 0.192833048892205290f, -0.981231580848749730f, 0.192644896549212240f, + -0.981268538084016710f, + 0.192456737123216840f, -0.981305459240844670f, 0.192268570621137590f, + -0.981342344317875930f, + 0.192080397049892380f, -0.981379193313754560f, 0.191892216416400310f, + -0.981416006227125550f, + 0.191704028727579940f, -0.981452783056635520f, 0.191515833990350240f, + -0.981489523800932130f, + 0.191327632211630990f, -0.981526228458664660f, 0.191139423398341420f, + -0.981562897028483650f, + 0.190951207557401860f, -0.981599529509040720f, 0.190762984695732250f, + -0.981636125898989080f, + 0.190574754820252800f, -0.981672686196983110f, 0.190386517937884580f, + -0.981709210401678800f, + 0.190198274055548120f, -0.981745698511732990f, 0.190010023180165050f, + -0.981782150525804310f, + 0.189821765318656580f, -0.981818566442552500f, 0.189633500477944220f, + -0.981854946260638630f, + 0.189445228664950340f, -0.981891289978724990f, 0.189256949886596720f, + -0.981927597595475540f, + 0.189068664149806280f, -0.981963869109555240f, 0.188880371461501330f, + -0.982000104519630490f, + 0.188692071828605260f, -0.982036303824369020f, 0.188503765258041080f, + -0.982072467022439890f, + 0.188315451756732120f, -0.982108594112513610f, 0.188127131331602530f, + -0.982144685093261580f, + 0.187938803989575850f, -0.982180739963357200f, 0.187750469737576840f, + -0.982216758721474510f, + 0.187562128582529740f, -0.982252741366289370f, 0.187373780531359110f, + -0.982288687896478830f, + 0.187185425590990440f, -0.982324598310721160f, 0.186997063768348510f, + -0.982360472607696210f, + 0.186808695070359330f, -0.982396310786084690f, 0.186620319503948420f, + -0.982432112844569110f, + 0.186431937076041640f, -0.982467878781833170f, 0.186243547793565670f, + -0.982503608596561720f, + 0.186055151663446630f, -0.982539302287441240f, 0.185866748692611720f, + -0.982574959853159240f, + 0.185678338887987790f, -0.982610581292404750f, 0.185489922256501900f, + -0.982646166603868050f, + 0.185301498805082040f, -0.982681715786240860f, 0.185113068540655510f, + -0.982717228838215990f, + 0.184924631470150870f, -0.982752705758487830f, 0.184736187600495930f, + -0.982788146545751970f, + 0.184547736938619640f, -0.982823551198705240f, 0.184359279491450640f, + -0.982858919716046110f, + 0.184170815265917720f, -0.982894252096474070f, 0.183982344268950600f, + -0.982929548338690060f, + 0.183793866507478390f, -0.982964808441396440f, 0.183605381988431350f, + -0.983000032403296590f, + 0.183416890718739230f, -0.983035220223095640f, 0.183228392705332140f, + -0.983070371899499640f, + 0.183039887955141060f, -0.983105487431216290f, 0.182851376475096310f, + -0.983140566816954500f, + 0.182662858272129360f, -0.983175610055424420f, 0.182474333353171260f, + -0.983210617145337640f, + 0.182285801725153320f, -0.983245588085407070f, 0.182097263395007760f, + -0.983280522874346970f, + 0.181908718369666160f, -0.983315421510872810f, 0.181720166656061170f, + -0.983350283993701500f, + 0.181531608261125130f, -0.983385110321551180f, 0.181343043191790590f, + -0.983419900493141540f, + 0.181154471454990920f, -0.983454654507193270f, 0.180965893057658980f, + -0.983489372362428730f, + 0.180777308006728670f, -0.983524054057571260f, 0.180588716309133280f, + -0.983558699591345900f, + 0.180400117971807270f, -0.983593308962478650f, 0.180211513001684590f, + -0.983627882169697210f, + 0.180022901405699510f, -0.983662419211730250f, 0.179834283190787180f, + -0.983696920087308020f, + 0.179645658363882100f, -0.983731384795162090f, 0.179457026931919950f, + -0.983765813334025240f, + 0.179268388901835880f, -0.983800205702631490f, 0.179079744280565390f, + -0.983834561899716630f, + 0.178891093075044830f, -0.983868881924017220f, 0.178702435292209940f, + -0.983903165774271500f, + 0.178513770938997590f, -0.983937413449218920f, 0.178325100022344140f, + -0.983971624947600270f, + 0.178136422549186320f, -0.984005800268157870f, 0.177947738526461670f, + -0.984039939409634970f, + 0.177759047961107140f, -0.984074042370776450f, 0.177570350860060790f, + -0.984108109150328540f, + 0.177381647230260200f, -0.984142139747038570f, 0.177192937078643310f, + -0.984176134159655320f, + 0.177004220412148860f, -0.984210092386929030f, 0.176815497237715000f, + -0.984244014427611110f, + 0.176626767562280960f, -0.984277900280454370f, 0.176438031392785350f, + -0.984311749944212780f, + 0.176249288736167940f, -0.984345563417641900f, 0.176060539599367960f, + -0.984379340699498510f, + 0.175871783989325040f, -0.984413081788540700f, 0.175683021912979580f, + -0.984446786683527920f, + 0.175494253377271400f, -0.984480455383220930f, 0.175305478389141370f, + -0.984514087886381840f, + 0.175116696955530060f, -0.984547684191773960f, 0.174927909083378160f, + -0.984581244298162180f, + 0.174739114779627310f, -0.984614768204312600f, 0.174550314051218490f, + -0.984648255908992630f, + 0.174361506905093830f, -0.984681707410970940f, 0.174172693348194960f, + -0.984715122709017620f, + 0.173983873387463850f, -0.984748501801904210f, 0.173795047029843270f, + -0.984781844688403350f, + 0.173606214282275410f, -0.984815151367289140f, 0.173417375151703520f, + -0.984848421837337010f, + 0.173228529645070490f, -0.984881656097323700f, 0.173039677769319390f, + -0.984914854146027200f, + 0.172850819531394200f, -0.984948015982227030f, 0.172661954938238270f, + -0.984981141604703960f, + 0.172473083996796030f, -0.985014231012239840f, 0.172284206714011350f, + -0.985047284203618200f, + 0.172095323096829040f, -0.985080301177623800f, 0.171906433152193700f, + -0.985113281933042590f, + 0.171717536887049970f, -0.985146226468662230f, 0.171528634308343500f, + -0.985179134783271020f, + 0.171339725423019260f, -0.985212006875659460f, 0.171150810238023340f, + -0.985244842744618540f, + 0.170961888760301360f, -0.985277642388941220f, 0.170772960996799230f, + -0.985310405807421570f, + 0.170584026954463700f, -0.985343132998854790f, 0.170395086640240920f, + -0.985375823962037710f, + 0.170206140061078120f, -0.985408478695768420f, 0.170017187223922090f, + -0.985441097198846210f, + 0.169828228135719880f, -0.985473679470071810f, 0.169639262803419400f, + -0.985506225508247290f, + 0.169450291233967930f, -0.985538735312176060f, 0.169261313434313890f, + -0.985571208880662740f, + 0.169072329411405180f, -0.985603646212513400f, 0.168883339172190010f, + -0.985636047306535420f, + 0.168694342723617440f, -0.985668412161537550f, 0.168505340072635900f, + -0.985700740776329850f, + 0.168316331226194910f, -0.985733033149723490f, 0.168127316191243350f, + -0.985765289280531310f, + 0.167938294974731230f, -0.985797509167567370f, 0.167749267583608030f, + -0.985829692809647050f, + 0.167560234024823590f, -0.985861840205586980f, 0.167371194305328540f, + -0.985893951354205210f, + 0.167182148432072880f, -0.985926026254321130f, 0.166993096412007770f, + -0.985958064904755460f, + 0.166804038252083870f, -0.985990067304330030f, 0.166614973959252090f, + -0.986022033451868560f, + 0.166425903540464220f, -0.986053963346195440f, 0.166236827002671390f, + -0.986085856986136820f, + 0.166047744352825850f, -0.986117714370520090f, 0.165858655597879430f, + -0.986149535498173860f, + 0.165669560744784140f, -0.986181320367928270f, 0.165480459800492890f, + -0.986213068978614490f, + 0.165291352771957970f, -0.986244781329065460f, 0.165102239666132720f, + -0.986276457418114980f, + 0.164913120489970090f, -0.986308097244598670f, 0.164723995250423190f, + -0.986339700807353000f, + 0.164534863954446110f, -0.986371268105216030f, 0.164345726608992190f, + -0.986402799137027220f, + 0.164156583221015890f, -0.986434293901627070f, 0.163967433797471110f, + -0.986465752397857940f, + 0.163778278345312690f, -0.986497174624562880f, 0.163589116871495160f, + -0.986528560580586690f, + 0.163399949382973230f, -0.986559910264775410f, 0.163210775886702460f, + -0.986591223675976400f, + 0.163021596389637810f, -0.986622500813038480f, 0.162832410898735260f, + -0.986653741674811350f, + 0.162643219420950450f, -0.986684946260146690f, 0.162454021963239190f, + -0.986716114567897100f, + 0.162264818532558110f, -0.986747246596916480f, 0.162075609135863330f, + -0.986778342346060430f, + 0.161886393780111910f, -0.986809401814185420f, 0.161697172472260540f, + -0.986840425000149680f, + 0.161507945219266150f, -0.986871411902812470f, 0.161318712028086540f, + -0.986902362521034470f, + 0.161129472905678780f, -0.986933276853677710f, 0.160940227859001140f, + -0.986964154899605650f, + 0.160750976895011390f, -0.986994996657682870f, 0.160561720020667510f, + -0.987025802126775600f, + 0.160372457242928400f, -0.987056571305750970f, 0.160183188568752240f, + -0.987087304193477900f, + 0.159993914005098350f, -0.987118000788826280f, 0.159804633558925380f, + -0.987148661090667570f, + 0.159615347237193090f, -0.987179285097874340f, 0.159426055046860750f, + -0.987209872809320820f, + 0.159236756994887850f, -0.987240424223882250f, 0.159047453088234840f, + -0.987270939340435420f, + 0.158858143333861390f, -0.987301418157858430f, 0.158668827738728370f, + -0.987331860675030430f, + 0.158479506309796100f, -0.987362266890832400f, 0.158290179054025180f, + -0.987392636804146240f, + 0.158100845978377090f, -0.987422970413855410f, 0.157911507089812640f, + -0.987453267718844560f, + 0.157722162395293690f, -0.987483528717999710f, 0.157532811901781670f, + -0.987513753410208420f, + 0.157343455616238280f, -0.987543941794359230f, 0.157154093545626010f, + -0.987574093869342360f, + 0.156964725696906750f, -0.987604209634049160f, 0.156775352077043430f, + -0.987634289087372160f, + 0.156585972692998590f, -0.987664332228205710f, 0.156396587551734940f, + -0.987694339055445130f, + 0.156207196660216040f, -0.987724309567986960f, 0.156017800025404830f, + -0.987754243764729530f, + 0.155828397654265320f, -0.987784141644572180f, 0.155638989553760850f, + -0.987814003206415550f, + 0.155449575730855880f, -0.987843828449161740f, 0.155260156192514380f, + -0.987873617371714200f, + 0.155070730945700510f, -0.987903369972977790f, 0.154881299997379400f, + -0.987933086251858380f, + 0.154691863354515400f, -0.987962766207263420f, 0.154502421024073990f, + -0.987992409838101880f, + 0.154312973013020240f, -0.988022017143283530f, 0.154123519328319360f, + -0.988051588121720110f, + 0.153934059976937460f, -0.988081122772324070f, 0.153744594965840000f, + -0.988110621094009820f, + 0.153555124301993500f, -0.988140083085692570f, 0.153365647992364020f, + -0.988169508746289060f, + 0.153176166043917870f, -0.988198898074717610f, 0.152986678463622160f, + -0.988228251069897420f, + 0.152797185258443410f, -0.988257567730749460f, 0.152607686435349140f, + -0.988286848056195710f, + 0.152418182001306500f, -0.988316092045159690f, 0.152228671963282770f, + -0.988345299696566150f, + 0.152039156328246160f, -0.988374471009341280f, 0.151849635103164180f, + -0.988403605982412390f, + 0.151660108295005400f, -0.988432704614708340f, 0.151470575910737760f, + -0.988461766905159300f, + 0.151281037957330250f, -0.988490792852696590f, 0.151091494441751430f, + -0.988519782456253270f, + 0.150901945370970040f, -0.988548735714763200f, 0.150712390751955720f, + -0.988577652627162020f, + 0.150522830591677370f, -0.988606533192386450f, 0.150333264897105050f, + -0.988635377409374790f, + 0.150143693675208330f, -0.988664185277066230f, 0.149954116932956990f, + -0.988692956794401940f, + 0.149764534677321620f, -0.988721691960323780f, 0.149574946915272210f, + -0.988750390773775360f, + 0.149385353653779810f, -0.988779053233701520f, 0.149195754899814960f, + -0.988807679339048340f, + 0.149006150660348470f, -0.988836269088763540f, 0.148816540942352030f, + -0.988864822481795640f, + 0.148626925752796540f, -0.988893339517095130f, 0.148437305098654050f, + -0.988921820193613190f, + 0.148247678986896200f, -0.988950264510302990f, 0.148058047424494740f, + -0.988978672466118480f, + 0.147868410418422360f, -0.989007044060015270f, 0.147678767975650970f, + -0.989035379290950310f, + 0.147489120103153680f, -0.989063678157881540f, 0.147299466807902820f, + -0.989091940659768800f, + 0.147109808096871850f, -0.989120166795572690f, 0.146920143977033760f, + -0.989148356564255590f, + 0.146730474455361750f, -0.989176509964781010f, 0.146540799538829870f, + -0.989204626996113780f, + 0.146351119234411440f, -0.989232707657220050f, 0.146161433549080950f, + -0.989260751947067640f, + 0.145971742489812370f, -0.989288759864625170f, 0.145782046063579860f, + -0.989316731408863000f, + 0.145592344277358450f, -0.989344666578752640f, 0.145402637138122540f, + -0.989372565373267010f, + 0.145212924652847520f, -0.989400427791380380f, 0.145023206828508360f, + -0.989428253832068230f, + 0.144833483672080240f, -0.989456043494307710f, 0.144643755190539150f, + -0.989483796777076760f, + 0.144454021390860440f, -0.989511513679355190f, 0.144264282280020530f, + -0.989539194200123930f, + 0.144074537864995330f, -0.989566838338365120f, 0.143884788152761010f, + -0.989594446093062460f, + 0.143695033150294580f, -0.989622017463200780f, 0.143505272864572290f, + -0.989649552447766530f, + 0.143315507302571590f, -0.989677051045747210f, 0.143125736471269140f, + -0.989704513256131850f, + 0.142935960377642700f, -0.989731939077910570f, 0.142746179028669620f, + -0.989759328510075200f, + 0.142556392431327340f, -0.989786681551618640f, 0.142366600592594260f, + -0.989813998201535260f, + 0.142176803519448000f, -0.989841278458820530f, 0.141987001218867340f, + -0.989868522322471580f, + 0.141797193697830530f, -0.989895729791486660f, 0.141607380963316020f, + -0.989922900864865450f, + 0.141417563022303130f, -0.989950035541608990f, 0.141227739881770480f, + -0.989977133820719610f, + 0.141037911548697770f, -0.990004195701200910f, 0.140848078030064220f, + -0.990031221182058000f, + 0.140658239332849240f, -0.990058210262297120f, 0.140468395464033110f, + -0.990085162940925970f, + 0.140278546430595420f, -0.990112079216953770f, 0.140088692239516780f, + -0.990138959089390650f, + 0.139898832897777380f, -0.990165802557248400f, 0.139708968412357580f, + -0.990192609619540030f, + 0.139519098790238600f, -0.990219380275280000f, 0.139329224038400980f, + -0.990246114523483990f, + 0.139139344163826280f, -0.990272812363169110f, 0.138949459173495440f, + -0.990299473793353590f, + 0.138759569074390380f, -0.990326098813057330f, 0.138569673873492640f, + -0.990352687421301340f, + 0.138379773577783890f, -0.990379239617108160f, 0.138189868194246640f, + -0.990405755399501260f, + 0.137999957729862760f, -0.990432234767505970f, 0.137810042191615130f, + -0.990458677720148620f, + 0.137620121586486180f, -0.990485084256456980f, 0.137430195921458550f, + -0.990511454375460290f, + 0.137240265203515700f, -0.990537788076188750f, 0.137050329439640380f, + -0.990564085357674370f, + 0.136860388636816430f, -0.990590346218950150f, 0.136670442802027230f, + -0.990616570659050620f, + 0.136480491942256310f, -0.990642758677011570f, 0.136290536064488070f, + -0.990668910271869980f, + 0.136100575175706200f, -0.990695025442664630f, 0.135910609282895440f, + -0.990721104188435180f, + 0.135720638393040080f, -0.990747146508222710f, 0.135530662513124620f, + -0.990773152401069780f, + 0.135340681650134330f, -0.990799121866020370f, 0.135150695811053850f, + -0.990825054902119470f, + 0.134960705002868830f, -0.990850951508413620f, 0.134770709232564290f, + -0.990876811683950810f, + 0.134580708507126220f, -0.990902635427780010f, 0.134390702833540240f, + -0.990928422738951990f, + 0.134200692218792020f, -0.990954173616518500f, 0.134010676669868210f, + -0.990979888059532740f, + 0.133820656193754690f, -0.991005566067049370f, 0.133630630797438390f, + -0.991031207638124130f, + 0.133440600487905820f, -0.991056812771814340f, 0.133250565272143570f, + -0.991082381467178640f, + 0.133060525157139180f, -0.991107913723276780f, 0.132870480149879400f, + -0.991133409539170170f, + 0.132680430257352130f, -0.991158868913921350f, 0.132490375486544710f, + -0.991184291846594180f, + 0.132300315844444680f, -0.991209678336254060f, 0.132110251338040470f, + -0.991235028381967420f, + 0.131920181974319760f, -0.991260341982802440f, 0.131730107760271280f, + -0.991285619137828200f, + 0.131540028702883280f, -0.991310859846115440f, 0.131349944809144220f, + -0.991336064106736140f, + 0.131159856086043410f, -0.991361231918763460f, 0.130969762540569380f, + -0.991386363281272280f, + 0.130779664179711790f, -0.991411458193338540f, 0.130589561010459600f, + -0.991436516654039420f, + 0.130399453039802740f, -0.991461538662453790f, 0.130209340274730770f, + -0.991486524217661480f, + 0.130019222722233350f, -0.991511473318743900f, 0.129829100389301010f, + -0.991536385964783880f, + 0.129638973282923540f, -0.991561262154865290f, 0.129448841410091830f, + -0.991586101888073500f, + 0.129258704777796270f, -0.991610905163495370f, 0.129068563393027410f, + -0.991635671980218740f, + 0.128878417262776660f, -0.991660402337333210f, 0.128688266394034690f, + -0.991685096233929530f, + 0.128498110793793220f, -0.991709753669099530f, 0.128307950469043590f, + -0.991734374641936810f, + 0.128117785426777150f, -0.991758959151536110f, 0.127927615673986190f, + -0.991783507196993490f, + 0.127737441217662280f, -0.991808018777406430f, 0.127547262064798050f, + -0.991832493891873780f, + 0.127357078222385570f, -0.991856932539495360f, 0.127166889697417180f, + -0.991881334719373010f, + 0.126976696496885980f, -0.991905700430609330f, 0.126786498627784430f, + -0.991930029672308480f, + 0.126596296097105960f, -0.991954322443575950f, 0.126406088911843320f, + -0.991978578743518580f, + 0.126215877078990400f, -0.992002798571244520f, 0.126025660605540460f, + -0.992026981925863360f, + 0.125835439498487020f, -0.992051128806485720f, 0.125645213764824380f, + -0.992075239212224070f, + 0.125454983411546210f, -0.992099313142191800f, 0.125264748445647110f, + -0.992123350595503720f, + 0.125074508874121300f, -0.992147351571276090f, 0.124884264703963150f, + -0.992171316068626520f, + 0.124694015942167770f, -0.992195244086673920f, 0.124503762595729650f, + -0.992219135624538450f, + 0.124313504671644300f, -0.992242990681341700f, 0.124123242176906760f, + -0.992266809256206580f, + 0.123932975118512200f, -0.992290591348257370f, 0.123742703503456630f, + -0.992314336956619640f, + 0.123552427338735370f, -0.992338046080420420f, 0.123362146631344750f, + -0.992361718718787870f, + 0.123171861388280650f, -0.992385354870851670f, 0.122981571616539080f, + -0.992408954535742850f, + 0.122791277323116900f, -0.992432517712593550f, 0.122600978515010240f, + -0.992456044400537700f, + 0.122410675199216280f, -0.992479534598709970f, 0.122220367382731500f, + -0.992502988306246950f, + 0.122030055072553410f, -0.992526405522286100f, 0.121839738275679020f, + -0.992549786245966570f, + 0.121649416999105540f, -0.992573130476428810f, 0.121459091249830950f, + -0.992596438212814290f, + 0.121268761034852550f, -0.992619709454266140f, 0.121078426361168710f, + -0.992642944199928820f, + 0.120888087235777220f, -0.992666142448948020f, 0.120697743665676120f, + -0.992689304200470750f, + 0.120507395657864240f, -0.992712429453645460f, 0.120317043219339670f, + -0.992735518207621850f, + 0.120126686357101580f, -0.992758570461551140f, 0.119936325078148620f, + -0.992781586214585570f, + 0.119745959389479630f, -0.992804565465879140f, 0.119555589298094230f, + -0.992827508214586760f, + 0.119365214810991350f, -0.992850414459865100f, 0.119174835935170960f, + -0.992873284200871730f, + 0.118984452677632520f, -0.992896117436765980f, 0.118794065045375670f, + -0.992918914166708300f, + 0.118603673045400840f, -0.992941674389860470f, 0.118413276684707770f, + -0.992964398105385610f, + 0.118222875970297250f, -0.992987085312448390f, 0.118032470909169300f, + -0.993009736010214580f, + 0.117842061508325020f, -0.993032350197851410f, 0.117651647774765000f, + -0.993054927874527320f, + 0.117461229715489990f, -0.993077469039412300f, 0.117270807337501560f, + -0.993099973691677570f, + 0.117080380647800550f, -0.993122441830495580f, 0.116889949653388850f, + -0.993144873455040430f, + 0.116699514361267840f, -0.993167268564487230f, 0.116509074778439050f, + -0.993189627158012620f, + 0.116318630911904880f, -0.993211949234794500f, 0.116128182768666920f, + -0.993234234794012290f, + 0.115937730355727850f, -0.993256483834846440f, 0.115747273680089870f, + -0.993278696356479030f, + 0.115556812748755290f, -0.993300872358093280f, 0.115366347568727250f, + -0.993323011838873950f, + 0.115175878147008180f, -0.993345114798006910f, 0.114985404490601530f, + -0.993367181234679600f, + 0.114794926606510250f, -0.993389211148080650f, 0.114604444501737460f, + -0.993411204537400060f, + 0.114413958183287050f, -0.993433161401829360f, 0.114223467658162260f, + -0.993455081740560960f, + 0.114032972933367300f, -0.993476965552789190f, 0.113842474015905660f, + -0.993498812837709360f, + 0.113651970912781920f, -0.993520623594518090f, 0.113461463631000080f, + -0.993542397822413600f, + 0.113270952177564360f, -0.993564135520595300f, 0.113080436559479720f, + -0.993585836688263950f, + 0.112889916783750470f, -0.993607501324621610f, 0.112699392857381910f, + -0.993629129428871720f, + 0.112508864787378830f, -0.993650721000219120f, 0.112318332580746190f, + -0.993672276037870010f, + 0.112127796244489750f, -0.993693794541031680f, 0.111937255785614560f, + -0.993715276508913230f, + 0.111746711211126660f, -0.993736721940724600f, 0.111556162528031630f, + -0.993758130835677430f, + 0.111365609743335190f, -0.993779503192984580f, 0.111175052864043830f, + -0.993800839011860120f, + 0.110984491897163380f, -0.993822138291519660f, 0.110793926849700630f, + -0.993843401031180180f, + 0.110603357728661910f, -0.993864627230059750f, 0.110412784541053660f, + -0.993885816887378090f, + 0.110222207293883180f, -0.993906970002356060f, 0.110031625994157000f, + -0.993928086574215830f, + 0.109841040648882680f, -0.993949166602181130f, 0.109650451265067080f, + -0.993970210085476920f, + 0.109459857849718030f, -0.993991217023329380f, 0.109269260409842920f, + -0.994012187414966220f, + 0.109078658952449240f, -0.994033121259616400f, 0.108888053484545310f, + -0.994054018556510210f, + 0.108697444013138670f, -0.994074879304879370f, 0.108506830545237980f, + -0.994095703503956930f, + 0.108316213087851300f, -0.994116491152977070f, 0.108125591647986880f, + -0.994137242251175720f, + 0.107934966232653760f, -0.994157956797789730f, 0.107744336848860260f, + -0.994178634792057590f, + 0.107553703503615710f, -0.994199276233218910f, 0.107363066203928920f, + -0.994219881120514850f, + 0.107172424956808870f, -0.994240449453187900f, 0.106981779769265340f, + -0.994260981230481790f, + 0.106791130648307380f, -0.994281476451641550f, 0.106600477600945030f, + -0.994301935115913580f, + 0.106409820634187840f, -0.994322357222545810f, 0.106219159755045520f, + -0.994342742770787270f, + 0.106028494970528530f, -0.994363091759888570f, 0.105837826287646670f, + -0.994383404189101430f, + 0.105647153713410700f, -0.994403680057679100f, 0.105456477254830660f, + -0.994423919364875950f, + 0.105265796918917650f, -0.994444122109948040f, 0.105075112712682180f, + -0.994464288292152390f, + 0.104884424643134970f, -0.994484417910747600f, 0.104693732717287500f, + -0.994504510964993590f, + 0.104503036942150550f, -0.994524567454151740f, 0.104312337324735870f, + -0.994544587377484300f, + 0.104121633872054730f, -0.994564570734255420f, 0.103930926591118540f, + -0.994584517523730340f, + 0.103740215488939480f, -0.994604427745175660f, 0.103549500572529040f, + -0.994624301397859400f, + 0.103358781848899700f, -0.994644138481050710f, 0.103168059325063390f, + -0.994663938994020280f, + 0.102977333008032250f, -0.994683702936040250f, 0.102786602904819150f, + -0.994703430306383860f, + 0.102595869022436280f, -0.994723121104325700f, 0.102405131367896790f, + -0.994742775329142010f, + 0.102214389948213370f, -0.994762392980109930f, 0.102023644770398800f, + -0.994781974056508260f, + 0.101832895841466670f, -0.994801518557617110f, 0.101642143168429830f, + -0.994821026482717860f, + 0.101451386758302160f, -0.994840497831093180f, 0.101260626618096800f, + -0.994859932602027320f, + 0.101069862754827880f, -0.994879330794805620f, 0.100879095175509010f, + -0.994898692408714870f, + 0.100688323887153970f, -0.994918017443043200f, 0.100497548896777310f, + -0.994937305897080070f, + 0.100306770211392820f, -0.994956557770116380f, 0.100115987838015370f, + -0.994975773061444140f, + 0.099925201783659226f, -0.994994951770357020f, 0.099734412055338839f, + -0.995014093896149700f, + 0.099543618660069444f, -0.995033199438118630f, 0.099352821604865513f, + -0.995052268395561160f, + 0.099162020896742573f, -0.995071300767776170f, 0.098971216542715582f, + -0.995090296554063890f, + 0.098780408549799664f, -0.995109255753726110f, 0.098589596925010708f, + -0.995128178366065490f, + 0.098398781675363881f, -0.995147064390386470f, 0.098207962807875346f, + -0.995165913825994620f, + 0.098017140329560770f, -0.995184726672196820f, 0.097826314247435903f, + -0.995203502928301510f, + 0.097635484568517339f, -0.995222242593618240f, 0.097444651299820870f, + -0.995240945667458130f, + 0.097253814448363354f, -0.995259612149133390f, 0.097062974021160875f, + -0.995278242037957670f, + 0.096872130025230527f, -0.995296835333246090f, 0.096681282467588864f, + -0.995315392034315070f, + 0.096490431355252607f, -0.995333912140482280f, 0.096299576695239225f, + -0.995352395651066810f, + 0.096108718494565468f, -0.995370842565388990f, 0.095917856760249096f, + -0.995389252882770690f, + 0.095726991499307315f, -0.995407626602534900f, 0.095536122718757485f, + -0.995425963724006160f, + 0.095345250425617742f, -0.995444264246510340f, 0.095154374626905472f, + -0.995462528169374420f, + 0.094963495329639061f, -0.995480755491926940f, 0.094772612540836410f, + -0.995498946213497770f, + 0.094581726267515473f, -0.995517100333418110f, 0.094390836516695067f, + -0.995535217851020390f, + 0.094199943295393190f, -0.995553298765638470f, 0.094009046610628907f, + -0.995571343076607770f, + 0.093818146469420494f, -0.995589350783264600f, 0.093627242878787237f, + -0.995607321884947050f, + 0.093436335845747912f, -0.995625256380994310f, 0.093245425377321389f, + -0.995643154270746900f, + 0.093054511480527333f, -0.995661015553546910f, 0.092863594162384697f, + -0.995678840228737540f, + 0.092672673429913366f, -0.995696628295663520f, 0.092481749290132753f, + -0.995714379753670610f, + 0.092290821750062355f, -0.995732094602106430f, 0.092099890816722485f, + -0.995749772840319400f, + 0.091908956497132696f, -0.995767414467659820f, 0.091718018798313525f, + -0.995785019483478750f, + 0.091527077727284981f, -0.995802587887129160f, 0.091336133291067212f, + -0.995820119677964910f, + 0.091145185496681130f, -0.995837614855341610f, 0.090954234351146898f, + -0.995855073418615790f, + 0.090763279861485704f, -0.995872495367145730f, 0.090572322034718156f, + -0.995889880700290720f, + 0.090381360877865011f, -0.995907229417411720f, 0.090190396397947820f, + -0.995924541517870690f, + 0.089999428601987341f, -0.995941817001031350f, 0.089808457497005362f, + -0.995959055866258320f, + 0.089617483090022917f, -0.995976258112917790f, 0.089426505388062016f, + -0.995993423740377360f, + 0.089235524398144139f, -0.996010552748005870f, 0.089044540127290905f, + -0.996027645135173610f, + 0.088853552582524684f, -0.996044700901251970f, 0.088662561770867121f, + -0.996061720045614000f, + 0.088471567699340822f, -0.996078702567633980f, 0.088280570374967879f, + -0.996095648466687300f, + 0.088089569804770507f, -0.996112557742151130f, 0.087898565995771685f, + -0.996129430393403740f, + 0.087707558954993645f, -0.996146266419824620f, 0.087516548689459586f, + -0.996163065820794950f, + 0.087325535206192226f, -0.996179828595696870f, 0.087134518512214321f, + -0.996196554743914220f, + 0.086943498614549489f, -0.996213244264832040f, 0.086752475520220515f, + -0.996229897157836500f, + 0.086561449236251239f, -0.996246513422315520f, 0.086370419769664919f, + -0.996263093057658030f, + 0.086179387127484922f, -0.996279636063254650f, 0.085988351316735448f, + -0.996296142438496850f, + 0.085797312344439880f, -0.996312612182778000f, 0.085606270217622613f, + -0.996329045295492380f, + 0.085415224943307277f, -0.996345441776035900f, 0.085224176528518519f, + -0.996361801623805720f, + 0.085033124980280414f, -0.996378124838200210f, 0.084842070305617148f, + -0.996394411418619290f, + 0.084651012511553700f, -0.996410661364464100f, 0.084459951605114297f, + -0.996426874675137240f, + 0.084268887593324127f, -0.996443051350042630f, 0.084077820483207846f, + -0.996459191388585410f, + 0.083886750281790226f, -0.996475294790172160f, 0.083695676996096827f, + -0.996491361554210920f, + 0.083504600633152404f, -0.996507391680110820f, 0.083313521199982740f, + -0.996523385167282450f, + 0.083122438703613077f, -0.996539342015137940f, 0.082931353151068726f, + -0.996555262223090540f, + 0.082740264549375803f, -0.996571145790554840f, 0.082549172905559659f, + -0.996586992716946950f, + 0.082358078226646619f, -0.996602803001684130f, 0.082166980519662466f, + -0.996618576644185070f, + 0.081975879791633108f, -0.996634313643869900f, 0.081784776049585201f, + -0.996650014000160070f, + 0.081593669300544638f, -0.996665677712478160f, 0.081402559551538328f, + -0.996681304780248300f, + 0.081211446809592386f, -0.996696895202896060f, 0.081020331081733912f, + -0.996712448979848010f, + 0.080829212374989468f, -0.996727966110532490f, 0.080638090696385709f, + -0.996743446594378860f, + 0.080446966052950097f, -0.996758890430818000f, 0.080255838451709291f, + -0.996774297619282050f, + 0.080064707899690932f, -0.996789668159204560f, 0.079873574403922148f, + -0.996805002050020320f, + 0.079682437971430126f, -0.996820299291165670f, 0.079491298609242866f, + -0.996835559882078170f, + 0.079300156324387569f, -0.996850783822196610f, 0.079109011123892431f, + -0.996865971110961310f, + 0.078917863014785095f, -0.996881121747813850f, 0.078726712004093313f, + -0.996896235732197210f, + 0.078535558098845590f, -0.996911313063555740f, 0.078344401306069678f, + -0.996926353741335090f, + 0.078153241632794315f, -0.996941357764982160f, 0.077962079086047645f, + -0.996956325133945280f, + 0.077770913672857989f, -0.996971255847674320f, 0.077579745400254363f, + -0.996986149905620180f, + 0.077388574275265049f, -0.997001007307235290f, 0.077197400304919297f, + -0.997015828051973310f, + 0.077006223496245585f, -0.997030612139289450f, 0.076815043856273399f, + -0.997045359568640040f, + 0.076623861392031617f, -0.997060070339482960f, 0.076432676110549283f, + -0.997074744451277310f, + 0.076241488018856149f, -0.997089381903483400f, 0.076050297123981231f, + -0.997103982695563330f, + 0.075859103432954503f, -0.997118546826979980f, 0.075667906952805383f, + -0.997133074297198110f, + 0.075476707690563416f, -0.997147565105683480f, 0.075285505653258880f, + -0.997162019251903290f, + 0.075094300847921291f, -0.997176436735326190f, 0.074903093281581137f, + -0.997190817555421940f, + 0.074711882961268378f, -0.997205161711661850f, 0.074520669894013014f, + -0.997219469203518670f, + 0.074329454086845867f, -0.997233740030466160f, 0.074138235546796952f, + -0.997247974191979860f, + 0.073947014280897269f, -0.997262171687536170f, 0.073755790296177265f, + -0.997276332516613180f, + 0.073564563599667454f, -0.997290456678690210f, 0.073373334198399157f, + -0.997304544173247990f, + 0.073182102099402888f, -0.997318594999768600f, 0.072990867309710133f, + -0.997332609157735470f, + 0.072799629836351618f, -0.997346586646633230f, 0.072608389686359048f, + -0.997360527465947940f, + 0.072417146866763538f, -0.997374431615167030f, 0.072225901384596336f, + -0.997388299093779460f, + 0.072034653246889416f, -0.997402129901275300f, 0.071843402460674000f, + -0.997415924037145960f, + 0.071652149032982254f, -0.997429681500884180f, 0.071460892970845832f, + -0.997443402291984360f, + 0.071269634281296415f, -0.997457086409941910f, 0.071078372971366502f, + -0.997470733854253670f, + 0.070887109048087787f, -0.997484344624417930f, 0.070695842518492924f, + -0.997497918719934210f, + 0.070504573389614009f, -0.997511456140303450f, 0.070313301668483263f, + -0.997524956885027960f, + 0.070122027362133646f, -0.997538420953611230f, 0.069930750477597295f, + -0.997551848345558430f, + 0.069739471021907376f, -0.997565239060375750f, 0.069548189002096472f, + -0.997578593097570800f, + 0.069356904425197236f, -0.997591910456652630f, 0.069165617298243109f, + -0.997605191137131640f, + 0.068974327628266732f, -0.997618435138519550f, 0.068783035422301728f, + -0.997631642460329320f, + 0.068591740687380900f, -0.997644813102075420f, 0.068400443430538069f, + -0.997657947063273710f, + 0.068209143658806454f, -0.997671044343441000f, 0.068017841379219388f, + -0.997684104942096030f, + 0.067826536598810966f, -0.997697128858758500f, 0.067635229324614451f, + -0.997710116092949570f, + 0.067443919563664106f, -0.997723066644191640f, 0.067252607322993652f, + -0.997735980512008620f, + 0.067061292609636836f, -0.997748857695925690f, 0.066869975430628226f, + -0.997761698195469560f, + 0.066678655793001543f, -0.997774502010167820f, 0.066487333703791507f, + -0.997787269139549960f, + 0.066296009170032283f, -0.997799999583146470f, 0.066104682198758091f, + -0.997812693340489280f, + 0.065913352797003930f, -0.997825350411111640f, 0.065722020971803977f, + -0.997837970794548280f, + 0.065530686730193397f, -0.997850554490335110f, 0.065339350079206798f, + -0.997863101498009500f, + 0.065148011025878860f, -0.997875611817110150f, 0.064956669577245010f, + -0.997888085447177110f, + 0.064765325740339871f, -0.997900522387751620f, 0.064573979522199065f, + -0.997912922638376610f, + 0.064382630929857410f, -0.997925286198596000f, 0.064191279970350679f, + -0.997937613067955250f, + 0.063999926650714078f, -0.997949903246001190f, 0.063808570977982898f, + -0.997962156732281950f, + 0.063617212959193190f, -0.997974373526346990f, 0.063425852601380200f, + -0.997986553627747020f, + 0.063234489911580136f, -0.997998697036034390f, 0.063043124896828631f, + -0.998010803750762450f, + 0.062851757564161420f, -0.998022873771486240f, 0.062660387920614985f, + -0.998034907097761770f, + 0.062469015973224969f, -0.998046903729146840f, 0.062277641729028041f, + -0.998058863665200250f, + 0.062086265195060247f, -0.998070786905482340f, 0.061894886378357744f, + -0.998082673449554590f, + 0.061703505285957416f, -0.998094523296980010f, 0.061512121924895365f, + -0.998106336447323050f, + 0.061320736302208648f, -0.998118112900149180f, 0.061129348424933755f, + -0.998129852655025520f, + 0.060937958300107238f, -0.998141555711520520f, 0.060746565934766412f, + -0.998153222069203650f, + 0.060555171335947781f, -0.998164851727646240f, 0.060363774510688827f, + -0.998176444686420530f, + 0.060172375466026218f, -0.998188000945100300f, 0.059980974208997596f, + -0.998199520503260660f, + 0.059789570746640007f, -0.998211003360478190f, 0.059598165085990598f, + -0.998222449516330550f, + 0.059406757234087247f, -0.998233858970396850f, 0.059215347197967026f, + -0.998245231722257880f, + 0.059023934984667986f, -0.998256567771495180f, 0.058832520601227581f, + -0.998267867117692110f, + 0.058641104054683348f, -0.998279129760433200f, 0.058449685352073573f, + -0.998290355699304350f, + 0.058258264500435732f, -0.998301544933892890f, 0.058066841506808263f, + -0.998312697463787260f, + 0.057875416378229017f, -0.998323813288577560f, 0.057683989121735932f, + -0.998334892407855000f, + 0.057492559744367684f, -0.998345934821212370f, 0.057301128253162144f, + -0.998356940528243420f, + 0.057109694655158132f, -0.998367909528543820f, 0.056918258957393907f, + -0.998378841821709990f, + 0.056726821166907783f, -0.998389737407340160f, 0.056535381290738825f, + -0.998400596285033640f, + 0.056343939335925283f, -0.998411418454391300f, 0.056152495309506383f, + -0.998422203915015020f, + 0.055961049218520520f, -0.998432952666508440f, 0.055769601070007072f, + -0.998443664708476340f, + 0.055578150871004817f, -0.998454340040524800f, 0.055386698628552604f, + -0.998464978662261250f, + 0.055195244349690031f, -0.998475580573294770f, 0.055003788041455885f, + -0.998486145773235360f, + 0.054812329710889909f, -0.998496674261694640f, 0.054620869365031251f, + -0.998507166038285490f, + 0.054429407010919147f, -0.998517621102622210f, 0.054237942655593556f, + -0.998528039454320230f, + 0.054046476306093640f, -0.998538421092996730f, 0.053855007969459509f, + -0.998548766018269920f, + 0.053663537652730679f, -0.998559074229759310f, 0.053472065362946755f, + -0.998569345727086110f, + 0.053280591107148056f, -0.998579580509872500f, 0.053089114892374119f, + -0.998589778577742230f, + 0.052897636725665401f, -0.998599939930320370f, 0.052706156614061798f, + -0.998610064567233340f, + 0.052514674564603257f, -0.998620152488108870f, 0.052323190584330471f, + -0.998630203692576050f, + 0.052131704680283317f, -0.998640218180265270f, 0.051940216859502626f, + -0.998650195950808280f, + 0.051748727129028414f, -0.998660137003838490f, 0.051557235495901653f, + -0.998670041338990070f, + 0.051365741967162731f, -0.998679908955899090f, 0.051174246549852087f, + -0.998689739854202620f, + 0.050982749251010900f, -0.998699534033539280f, 0.050791250077679546f, + -0.998709291493549030f, + 0.050599749036899337f, -0.998719012233872940f, 0.050408246135710995f, + -0.998728696254153720f, + 0.050216741381155325f, -0.998738343554035230f, 0.050025234780273840f, + -0.998747954133162860f, + 0.049833726340107257f, -0.998757527991183340f, 0.049642216067697226f, + -0.998767065127744380f, + 0.049450703970084824f, -0.998776565542495610f, 0.049259190054311168f, + -0.998786029235087640f, + 0.049067674327418126f, -0.998795456205172410f, 0.048876156796446746f, + -0.998804846452403420f, + 0.048684637468439020f, -0.998814199976435390f, 0.048493116350436342f, + -0.998823516776924380f, + 0.048301593449480172f, -0.998832796853527990f, 0.048110068772612716f, + -0.998842040205904840f, + 0.047918542326875327f, -0.998851246833715180f, 0.047727014119310344f, + -0.998860416736620520f, + 0.047535484156959261f, -0.998869549914283560f, 0.047343952446864526f, + -0.998878646366368690f, + 0.047152418996068000f, -0.998887706092541290f, 0.046960883811611599f, + -0.998896729092468410f, + 0.046769346900537960f, -0.998905715365818290f, 0.046577808269888908f, + -0.998914664912260440f, + 0.046386267926707213f, -0.998923577731465780f, 0.046194725878035046f, + -0.998932453823106690f, + 0.046003182130914644f, -0.998941293186856870f, 0.045811636692388955f, + -0.998950095822391250f, + 0.045620089569500123f, -0.998958861729386080f, 0.045428540769291224f, + -0.998967590907519300f, + 0.045236990298804750f, -0.998976283356469820f, 0.045045438165083225f, + -0.998984939075918010f, + 0.044853884375169933f, -0.998993558065545680f, 0.044662328936107311f, + -0.999002140325035980f, + 0.044470771854938744f, -0.999010685854073380f, 0.044279213138707016f, + -0.999019194652343460f, + 0.044087652794454979f, -0.999027666719533690f, 0.043896090829226200f, + -0.999036102055332330f, + 0.043704527250063421f, -0.999044500659429290f, 0.043512962064010327f, + -0.999052862531515930f, + 0.043321395278109784f, -0.999061187671284600f, 0.043129826899405595f, + -0.999069476078429330f, + 0.042938256934940959f, -0.999077727752645360f, 0.042746685391759139f, + -0.999085942693629270f, + 0.042555112276904117f, -0.999094120901079070f, 0.042363537597419038f, + -0.999102262374694130f, + 0.042171961360348002f, -0.999110367114174890f, 0.041980383572734502f, + -0.999118435119223490f, + 0.041788804241622082f, -0.999126466389543390f, 0.041597223374055005f, + -0.999134460924839150f, + 0.041405640977076712f, -0.999142418724816910f, 0.041214057057731589f, + -0.999150339789184110f, + 0.041022471623063397f, -0.999158224117649430f, 0.040830884680115968f, + -0.999166071709923000f, + 0.040639296235933854f, -0.999173882565716380f, 0.040447706297560768f, + -0.999181656684742350f, + 0.040256114872041358f, -0.999189394066714920f, 0.040064521966419686f, + -0.999197094711349880f, + 0.039872927587739845f, -0.999204758618363890f, 0.039681331743046659f, + -0.999212385787475290f, + 0.039489734439384118f, -0.999219976218403530f, 0.039298135683797149f, + -0.999227529910869610f, + 0.039106535483329839f, -0.999235046864595850f, 0.038914933845027241f, + -0.999242527079305830f, + 0.038723330775933762f, -0.999249970554724420f, 0.038531726283093877f, + -0.999257377290578060f, + 0.038340120373552791f, -0.999264747286594420f, 0.038148513054354856f, + -0.999272080542502610f, + 0.037956904332545366f, -0.999279377058032710f, 0.037765294215169005f, + -0.999286636832916740f, + 0.037573682709270514f, -0.999293859866887790f, 0.037382069821895340f, + -0.999301046159680070f, + 0.037190455560088091f, -0.999308195711029470f, 0.036998839930894332f, + -0.999315308520673070f, + 0.036807222941358991f, -0.999322384588349540f, 0.036615604598527057f, + -0.999329423913798420f, + 0.036423984909444228f, -0.999336426496761240f, 0.036232363881155374f, + -0.999343392336980220f, + 0.036040741520706299f, -0.999350321434199440f, 0.035849117835142184f, + -0.999357213788164000f, + 0.035657492831508264f, -0.999364069398620550f, 0.035465866516850478f, + -0.999370888265317060f, + 0.035274238898213947f, -0.999377670388002850f, 0.035082609982644702f, + -0.999384415766428560f, + 0.034890979777187955f, -0.999391124400346050f, 0.034699348288889847f, + -0.999397796289508640f, + 0.034507715524795889f, -0.999404431433671300f, 0.034316081491951658f, + -0.999411029832589780f, + 0.034124446197403423f, -0.999417591486021720f, 0.033932809648196623f, + -0.999424116393725640f, + 0.033741171851377642f, -0.999430604555461730f, 0.033549532813992221f, + -0.999437055970991530f, + 0.033357892543086159f, -0.999443470640077770f, 0.033166251045705968f, + -0.999449848562484530f, + 0.032974608328897315f, -0.999456189737977340f, 0.032782964399706793f, + -0.999462494166323160f, + 0.032591319265180385f, -0.999468761847290050f, 0.032399672932364114f, + -0.999474992780647780f, + 0.032208025408304704f, -0.999481186966166950f, 0.032016376700048046f, + -0.999487344403620080f, + 0.031824726814640963f, -0.999493465092780590f, 0.031633075759129645f, + -0.999499549033423640f, + 0.031441423540560343f, -0.999505596225325310f, 0.031249770165979990f, + -0.999511606668263440f, + 0.031058115642434700f, -0.999517580362016990f, 0.030866459976971503f, + -0.999523517306366350f, + 0.030674803176636581f, -0.999529417501093140f, 0.030483145248477058f, + -0.999535280945980540f, + 0.030291486199539423f, -0.999541107640812940f, 0.030099826036870208f, + -0.999546897585375960f, + 0.029908164767516655f, -0.999552650779456990f, 0.029716502398525156f, + -0.999558367222844300f, + 0.029524838936943035f, -0.999564046915327740f, 0.029333174389816984f, + -0.999569689856698580f, + 0.029141508764193740f, -0.999575296046749220f, 0.028949842067120746f, + -0.999580865485273700f, + 0.028758174305644590f, -0.999586398172067070f, 0.028566505486812797f, + -0.999591894106925950f, + 0.028374835617672258f, -0.999597353289648380f, 0.028183164705269902f, + -0.999602775720033530f, + 0.027991492756653365f, -0.999608161397882110f, 0.027799819778869434f, + -0.999613510322995950f, + 0.027608145778965820f, -0.999618822495178640f, 0.027416470763989606f, + -0.999624097914234570f, + 0.027224794740987910f, -0.999629336579970110f, 0.027033117717008563f, + -0.999634538492192300f, + 0.026841439699098527f, -0.999639703650710200f, 0.026649760694305708f, + -0.999644832055333610f, + 0.026458080709677145f, -0.999649923705874240f, 0.026266399752260809f, + -0.999654978602144690f, + 0.026074717829104040f, -0.999659996743959220f, 0.025883034947254208f, + -0.999664978131133310f, + 0.025691351113759395f, -0.999669922763483760f, 0.025499666335666818f, + -0.999674830640828740f, + 0.025307980620024630f, -0.999679701762987930f, 0.025116293973880335f, + -0.999684536129782140f, + 0.024924606404281485f, -0.999689333741033640f, 0.024732917918276334f, + -0.999694094596566000f, + 0.024541228522912264f, -0.999698818696204250f, 0.024349538225237600f, + -0.999703506039774650f, + 0.024157847032300020f, -0.999708156627104880f, 0.023966154951147241f, + -0.999712770458023870f, + 0.023774461988827676f, -0.999717347532362190f, 0.023582768152388880f, + -0.999721887849951310f, + 0.023391073448879338f, -0.999726391410624470f, 0.023199377885346890f, + -0.999730858214216030f, + 0.023007681468839410f, -0.999735288260561680f, 0.022815984206405477f, + -0.999739681549498660f, + 0.022624286105092803f, -0.999744038080865430f, 0.022432587171950024f, + -0.999748357854501780f, + 0.022240887414024919f, -0.999752640870248840f, 0.022049186838366180f, + -0.999756887127949080f, + 0.021857485452021874f, -0.999761096627446610f, 0.021665783262040089f, + -0.999765269368586450f, + 0.021474080275469605f, -0.999769405351215280f, 0.021282376499358355f, + -0.999773504575180990f, + 0.021090671940755180f, -0.999777567040332940f, 0.020898966606708289f, + -0.999781592746521670f, + 0.020707260504265912f, -0.999785581693599210f, 0.020515553640476986f, + -0.999789533881418780f, + 0.020323846022389572f, -0.999793449309835270f, 0.020132137657052664f, + -0.999797327978704690f, + 0.019940428551514598f, -0.999801169887884260f, 0.019748718712823757f, + -0.999804975037232870f, + 0.019557008148029204f, -0.999808743426610520f, 0.019365296864179146f, + -0.999812475055878780f, + 0.019173584868322699f, -0.999816169924900410f, 0.018981872167508348f, + -0.999819828033539420f, + 0.018790158768784596f, -0.999823449381661570f, 0.018598444679200642f, + -0.999827033969133420f, + 0.018406729905804820f, -0.999830581795823400f, 0.018215014455646376f, + -0.999834092861600960f, + 0.018023298335773701f, -0.999837567166337090f, 0.017831581553236088f, + -0.999841004709904000f, + 0.017639864115082195f, -0.999844405492175240f, 0.017448146028360704f, + -0.999847769513025900f, + 0.017256427300120978f, -0.999851096772332190f, 0.017064707937411529f, + -0.999854387269971890f, + 0.016872987947281773f, -0.999857641005823860f, 0.016681267336780482f, + -0.999860857979768540f, + 0.016489546112956454f, -0.999864038191687680f, 0.016297824282859176f, + -0.999867181641464380f, + 0.016106101853537263f, -0.999870288328982950f, 0.015914378832040249f, + -0.999873358254129260f, + 0.015722655225417017f, -0.999876391416790410f, 0.015530931040716478f, + -0.999879387816854930f, + 0.015339206284988220f, -0.999882347454212560f, 0.015147480965280975f, + -0.999885270328754520f, + 0.014955755088644378f, -0.999888156440373320f, 0.014764028662127416f, + -0.999891005788962950f, + 0.014572301692779104f, -0.999893818374418490f, 0.014380574187649138f, + -0.999896594196636680f, + 0.014188846153786343f, -0.999899333255515390f, 0.013997117598240459f, + -0.999902035550953920f, + 0.013805388528060349f, -0.999904701082852900f, 0.013613658950295789f, + -0.999907329851114300f, + 0.013421928871995907f, -0.999909921855641540f, 0.013230198300209845f, + -0.999912477096339240f, + 0.013038467241987433f, -0.999914995573113470f, 0.012846735704377631f, + -0.999917477285871770f, + 0.012655003694430301f, -0.999919922234522750f, 0.012463271219194662f, + -0.999922330418976490f, + 0.012271538285719944f, -0.999924701839144500f, 0.012079804901056066f, + -0.999927036494939640f, + 0.011888071072252072f, -0.999929334386276070f, 0.011696336806357907f, + -0.999931595513069200f, + 0.011504602110422875f, -0.999933819875236000f, 0.011312866991496287f, + -0.999936007472694620f, + 0.011121131456628141f, -0.999938158305364590f, 0.010929395512867561f, + -0.999940272373166960f, + 0.010737659167264572f, -0.999942349676023910f, 0.010545922426868548f, + -0.999944390213859060f, + 0.010354185298728884f, -0.999946393986597460f, 0.010162447789895645f, + -0.999948360994165400f, + 0.009970709907418029f, -0.999950291236490480f, 0.009778971658346134f, + -0.999952184713501780f, + 0.009587233049729183f, -0.999954041425129780f, 0.009395494088617302f, + -0.999955861371306100f, + 0.009203754782059960f, -0.999957644551963900f, 0.009012015137106642f, + -0.999959390967037450f, + 0.008820275160807512f, -0.999961100616462820f, 0.008628534860211857f, + -0.999962773500176930f, + 0.008436794242369860f, -0.999964409618118280f, 0.008245053314331058f, + -0.999966008970226920f, + 0.008053312083144991f, -0.999967571556443780f, 0.007861570555861883f, + -0.999969097376711580f, + 0.007669828739531077f, -0.999970586430974140f, 0.007478086641202815f, + -0.999972038719176730f, + 0.007286344267926684f, -0.999973454241265940f, 0.007094601626752279f, + -0.999974832997189810f, + 0.006902858724729877f, -0.999976174986897610f, 0.006711115568908869f, + -0.999977480210339940f, + 0.006519372166339549f, -0.999978748667468830f, 0.006327628524071549f, + -0.999979980358237650f, + 0.006135884649154515f, -0.999981175282601110f, 0.005944140548638765f, + -0.999982333440515350f, + 0.005752396229573737f, -0.999983454831937730f, 0.005560651699009764f, + -0.999984539456826970f, + 0.005368906963996303f, -0.999985587315143200f, 0.005177162031583702f, + -0.999986598406848000f, + 0.004985416908821652f, -0.999987572731904080f, 0.004793671602759852f, + -0.999988510290275690f, + 0.004601926120448672f, -0.999989411081928400f, 0.004410180468937601f, + -0.999990275106828920f, + 0.004218434655277024f, -0.999991102364945590f, 0.004026688686516664f, + -0.999991892856248010f, + 0.003834942569706248f, -0.999992646580707190f, 0.003643196311896179f, + -0.999993363538295150f, + 0.003451449920135975f, -0.999994043728985820f, 0.003259703401476044f, + -0.999994687152754080f, + 0.003067956762966138f, -0.999995293809576190f, 0.002876210011656010f, + -0.999995863699429940f, + 0.002684463154596083f, -0.999996396822294350f, 0.002492716198835898f, + -0.999996893178149880f, + 0.002300969151425887f, -0.999997352766978210f, 0.002109222019415816f, + -0.999997775588762350f, + 0.001917474809855460f, -0.999998161643486980f, 0.001725727529795258f, + -0.999998510931137790f, + 0.001533980186284766f, -0.999998823451701880f, 0.001342232786374430f, + -0.999999099205167830f, + 0.001150485337113809f, -0.999999338191525530f, 0.000958737845553352f, + -0.999999540410766110f, + 0.000766990318742846f, -0.999999705862882230f, 0.000575242763732077f, + -0.999999834547867670f, + 0.000383495187571497f, -0.999999926465717890f, 0.000191747597310674f, + -0.999999981616429330f +}; + + const float32_t cos_factors_8192[8192] = { + 1.999999990808214700f, 1.999999917273932200f, 1.999999770205369800f, + 1.999999549602533100f, + 1.999999255465430200f, 1.999998887794072000f, 1.999998446588471700f, + 1.999997931848645600f, + 1.999997343574612800f, 1.999996681766395000f, 1.999995946424016200f, + 1.999995137547503600f, + 1.999994255136887000f, 1.999993299192198700f, 1.999992269713474200f, + 1.999991166700750800f, + 1.999989990154069600f, 1.999988740073473500f, 1.999987416459008600f, + 1.999986019310723500f, + 1.999984548628669600f, 1.999983004412901000f, 1.999981386663474400f, + 1.999979695380449400f, + 1.999977930563888100f, 1.999976092213855400f, 1.999974180330418700f, + 1.999972194913648900f, + 1.999970135963618400f, 1.999968003480403000f, 1.999965797464081200f, + 1.999963517914734100f, + 1.999961164832445800f, 1.999958738217302300f, 1.999956238069392900f, + 1.999953664388809800f, + 1.999951017175647600f, 1.999948296430003500f, 1.999945502151977600f, + 1.999942634341672600f, + 1.999939692999193900f, 1.999936678124649700f, 1.999933589718150700f, + 1.999930427779810900f, + 1.999927192309745900f, 1.999923883308075200f, 1.999920500774920300f, + 1.999917044710405500f, + 1.999913515114657900f, 1.999909911987807200f, 1.999906235329986100f, + 1.999902485141329400f, + 1.999898661421975400f, 1.999894764172064600f, 1.999890793391740000f, + 1.999886749081147800f, + 1.999882631240436700f, 1.999878439869758200f, 1.999874174969266300f, + 1.999869836539117700f, + 1.999865424579472000f, 1.999860939090491600f, 1.999856380072341000f, + 1.999851747525188200f, + 1.999847041449203300f, 1.999842261844559700f, 1.999837408711432600f, + 1.999832482050000900f, + 1.999827481860445300f, 1.999822408142949900f, 1.999817260897701400f, + 1.999812040124888700f, + 1.999806745824704000f, 1.999801377997341800f, 1.999795936642999600f, + 1.999790421761877400f, + 1.999784833354177900f, 1.999779171420106700f, 1.999773435959872000f, + 1.999767626973684400f, + 1.999761744461757700f, 1.999755788424308200f, 1.999749758861554900f, + 1.999743655773719400f, + 1.999737479161026100f, 1.999731229023702200f, 1.999724905361977200f, + 1.999718508176084000f, + 1.999712037466257600f, 1.999705493232735800f, 1.999698875475759600f, + 1.999692184195571900f, + 1.999685419392419000f, 1.999678581066549400f, 1.999671669218214600f, + 1.999664683847668800f, + 1.999657624955168700f, 1.999650492540973900f, 1.999643286605346800f, + 1.999636007148552400f, + 1.999628654170857900f, 1.999621227672533800f, 1.999613727653853500f, + 1.999606154115092500f, + 1.999598507056529000f, 1.999590786478444600f, 1.999582992381123000f, + 1.999575124764850800f, + 1.999567183629917100f, 1.999559168976613900f, 1.999551080805236100f, + 1.999542919116081000f, + 1.999534683909448600f, 1.999526375185641800f, 1.999517992944965800f, + 1.999509537187729200f, + 1.999501007914242600f, 1.999492405124819700f, 1.999483728819776900f, + 1.999474978999432800f, + 1.999466155664109600f, 1.999457258814131500f, 1.999448288449825500f, + 1.999439244571521700f, + 1.999430127179552500f, 1.999420936274252800f, 1.999411671855960900f, + 1.999402333925017300f, + 1.999392922481765500f, 1.999383437526551300f, 1.999373879059723500f, + 1.999364247081633500f, + 1.999354541592635500f, 1.999344762593086500f, 1.999334910083345700f, + 1.999324984063775700f, + 1.999314984534741100f, 1.999304911496609700f, 1.999294764949752100f, + 1.999284544894541100f, + 1.999274251331352400f, 1.999263884260564600f, 1.999253443682558900f, + 1.999242929597719200f, + 1.999232342006432000f, 1.999221680909086400f, 1.999210946306074500f, + 1.999200138197791100f, + 1.999189256584633600f, 1.999178301467001900f, 1.999167272845298900f, + 1.999156170719930100f, + 1.999144995091303600f, 1.999133745959830600f, 1.999122423325924200f, + 1.999111027190001000f, + 1.999099557552479900f, 1.999088014413782800f, 1.999076397774334000f, + 1.999064707634560700f, + 1.999052943994892300f, 1.999041106855761900f, 1.999029196217604100f, + 1.999017212080857400f, + 1.999005154445962200f, 1.998993023313361700f, 1.998980818683502100f, + 1.998968540556831800f, + 1.998956188933802800f, 1.998943763814868800f, 1.998931265200486900f, + 1.998918693091116200f, + 1.998906047487219600f, 1.998893328389261400f, 1.998880535797709700f, + 1.998867669713034500f, + 1.998854730135709400f, 1.998841717066209400f, 1.998828630505013400f, + 1.998815470452602400f, + 1.998802236909460500f, 1.998788929876074100f, 1.998775549352932400f, + 1.998762095340527400f, + 1.998748567839354000f, 1.998734966849909000f, 1.998721292372693100f, + 1.998707544408208700f, + 1.998693722956961500f, 1.998679828019459300f, 1.998665859596213500f, + 1.998651817687737300f, + 1.998637702294547000f, 1.998623513417161700f, 1.998609251056103100f, + 1.998594915211895600f, + 1.998580505885066100f, 1.998566023076144600f, 1.998551466785663400f, + 1.998536837014157900f, + 1.998522133762165900f, 1.998507357030227900f, 1.998492506818887200f, + 1.998477583128690100f, + 1.998462585960185000f, 1.998447515313923400f, 1.998432371190459500f, + 1.998417153590349900f, + 1.998401862514154200f, 1.998386497962434800f, 1.998371059935756300f, + 1.998355548434686400f, + 1.998339963459795400f, 1.998324305011656600f, 1.998308573090845200f, + 1.998292767697940100f, + 1.998276888833522300f, 1.998260936498175400f, 1.998244910692486000f, + 1.998228811417043700f, + 1.998212638672439900f, 1.998196392459269400f, 1.998180072778129600f, + 1.998163679629620500f, + 1.998147213014344900f, 1.998130672932908000f, 1.998114059385918400f, + 1.998097372373986300f, + 1.998080611897725700f, 1.998063777957752600f, 1.998046870554686100f, + 1.998029889689147700f, + 1.998012835361761900f, 1.997995707573155600f, 1.997978506323958600f, + 1.997961231614803200f, + 1.997943883446324800f, 1.997926461819161000f, 1.997908966733952500f, + 1.997891398191342400f, + 1.997873756191977000f, 1.997856040736504500f, 1.997838251825576400f, + 1.997820389459846700f, + 1.997802453639972300f, 1.997784444366612600f, 1.997766361640429800f, + 1.997748205462088500f, + 1.997729975832256600f, 1.997711672751604200f, 1.997693296220804000f, + 1.997674846240532000f, + 1.997656322811466500f, 1.997637725934288300f, 1.997619055609681600f, + 1.997600311838332500f, + 1.997581494620930300f, 1.997562603958166600f, 1.997543639850736200f, + 1.997524602299336500f, + 1.997505491304667000f, 1.997486306867430900f, 1.997467048988333000f, + 1.997447717668082000f, + 1.997428312907388200f, 1.997408834706965000f, 1.997389283067528800f, + 1.997369657989798400f, + 1.997349959474495200f, 1.997330187522343700f, 1.997310342134070800f, + 1.997290423310406100f, + 1.997270431052081900f, 1.997250365359833200f, 1.997230226234397900f, + 1.997210013676516700f, + 1.997189727686932400f, 1.997169368266390900f, 1.997148935415640600f, + 1.997128429135433400f, + 1.997107849426522600f, 1.997087196289665000f, 1.997066469725620200f, + 1.997045669735150000f, + 1.997024796319019300f, 1.997003849477995600f, 1.996982829212848900f, + 1.996961735524351900f, + 1.996940568413280600f, 1.996919327880412900f, 1.996898013926530000f, + 1.996876626552415400f, + 1.996855165758855600f, 1.996833631546639300f, 1.996812023916558800f, + 1.996790342869408000f, + 1.996768588405984300f, 1.996746760527087700f, 1.996724859233520500f, + 1.996702884526087900f, + 1.996680836405598100f, 1.996658714872861800f, 1.996636519928692000f, + 1.996614251573904900f, + 1.996591909809319400f, 1.996569494635756600f, 1.996547006054041100f, + 1.996524444064999400f, + 1.996501808669461000f, 1.996479099868258400f, 1.996456317662226300f, + 1.996433462052202600f, + 1.996410533039027400f, 1.996387530623543900f, 1.996364454806597500f, + 1.996341305589037100f, + 1.996318082971713500f, 1.996294786955480800f, 1.996271417541195300f, + 1.996247974729716200f, + 1.996224458521905600f, 1.996200868918628100f, 1.996177205920750800f, + 1.996153469529144100f, + 1.996129659744680300f, 1.996105776568235100f, 1.996081820000686500f, + 1.996057790042915500f, + 1.996033686695805300f, 1.996009509960242400f, 1.995985259837115500f, + 1.995960936327316300f, + 1.995936539431739000f, 1.995912069151280800f, 1.995887525486841300f, + 1.995862908439323100f, + 1.995838218009630800f, 1.995813454198672700f, 1.995788617007359100f, + 1.995763706436603200f, + 1.995738722487320600f, 1.995713665160430600f, 1.995688534456853800f, + 1.995663330377514400f, + 1.995638052923339300f, 1.995612702095257400f, 1.995587277894201400f, + 1.995561780321105600f, + 1.995536209376907600f, 1.995510565062547800f, 1.995484847378968600f, + 1.995459056327116000f, + 1.995433191907938000f, 1.995407254122385700f, 1.995381242971412600f, + 1.995355158455975200f, + 1.995329000577032800f, 1.995302769335546500f, 1.995276464732481200f, + 1.995250086768804100f, + 1.995223635445484900f, 1.995197110763496000f, 1.995170512723813100f, + 1.995143841327413400f, + 1.995117096575278200f, 1.995090278468390600f, 1.995063387007736600f, + 1.995036422194304700f, + 1.995009384029086800f, 1.994982272513076600f, 1.994955087647271000f, + 1.994927829432669800f, + 1.994900497870274900f, 1.994873092961091200f, 1.994845614706126400f, + 1.994818063106391000f, + 1.994790438162897600f, 1.994762739876662100f, 1.994734968248702800f, + 1.994707123280041100f, + 1.994679204971700100f, 1.994651213324707000f, 1.994623148340090700f, + 1.994595010018883000f, + 1.994566798362118300f, 1.994538513370834200f, 1.994510155046070700f, + 1.994481723388870100f, + 1.994453218400277900f, 1.994424640081342100f, 1.994395988433113700f, + 1.994367263456646100f, + 1.994338465152995000f, 1.994309593523219600f, 1.994280648568381500f, + 1.994251630289544600f, + 1.994222538687776100f, 1.994193373764145500f, 1.994164135519725000f, + 1.994134823955589800f, + 1.994105439072817700f, 1.994075980872488800f, 1.994046449355686200f, + 1.994016844523496000f, + 1.993987166377006600f, 1.993957414917308700f, 1.993927590145496900f, + 1.993897692062667200f, + 1.993867720669919400f, 1.993837675968354700f, 1.993807557959078600f, + 1.993777366643197900f, + 1.993747102021822900f, 1.993716764096066200f, 1.993686352867043200f, + 1.993655868335872300f, + 1.993625310503674100f, 1.993594679371572200f, 1.993563974940692800f, + 1.993533197212164800f, + 1.993502346187119700f, 1.993471421866692200f, 1.993440424252018900f, + 1.993409353344239600f, + 1.993378209144496700f, 1.993346991653935300f, 1.993315700873703200f, + 1.993284336804950900f, + 1.993252899448831400f, 1.993221388806500900f, 1.993189804879117500f, + 1.993158147667842800f, + 1.993126417173840500f, 1.993094613398277400f, 1.993062736342323000f, + 1.993030786007148800f, + 1.992998762393930000f, 1.992966665503844000f, 1.992934495338070800f, + 1.992902251897793000f, + 1.992869935184196300f, 1.992837545198469000f, 1.992805081941801700f, + 1.992772545415388200f, + 1.992739935620424700f, 1.992707252558110200f, 1.992674496229646500f, + 1.992641666636237700f, + 1.992608763779091000f, 1.992575787659416100f, 1.992542738278425300f, + 1.992509615637334100f, + 1.992476419737359900f, 1.992443150579723500f, 1.992409808165648100f, + 1.992376392496359300f, + 1.992342903573086000f, 1.992309341397059600f, 1.992275705969513800f, + 1.992241997291685400f, + 1.992208215364813700f, 1.992174360190140900f, 1.992140431768911500f, + 1.992106430102373400f, + 1.992072355191776300f, 1.992038207038373300f, 1.992003985643419700f, + 1.991969691008174100f, + 1.991935323133897000f, 1.991900882021852200f, 1.991866367673306200f, + 1.991831780089527500f, + 1.991797119271788300f, 1.991762385221362600f, 1.991727577939527600f, + 1.991692697427563300f, + 1.991657743686751700f, 1.991622716718378400f, 1.991587616523731000f, + 1.991552443104099800f, + 1.991517196460778500f, 1.991481876595062800f, 1.991446483508251500f, + 1.991411017201645500f, + 1.991375477676549100f, 1.991339864934268800f, 1.991304178976114100f, + 1.991268419803397200f, + 1.991232587417432600f, 1.991196681819537900f, 1.991160703011033200f, + 1.991124650993241400f, + 1.991088525767488200f, 1.991052327335101300f, 1.991016055697411900f, + 1.990979710855753900f, + 1.990943292811463000f, 1.990906801565878600f, 1.990870237120342400f, + 1.990833599476198800f, + 1.990796888634794400f, 1.990760104597479400f, 1.990723247365606200f, + 1.990686316940529800f, + 1.990649313323608100f, 1.990612236516201300f, 1.990575086519673200f, + 1.990537863335389400f, + 1.990500566964718400f, 1.990463197409031700f, 1.990425754669703100f, + 1.990388238748109100f, + 1.990350649645629600f, 1.990312987363646000f, 1.990275251903543600f, + 1.990237443266709400f, + 1.990199561454533600f, 1.990161606468409300f, 1.990123578309731700f, + 1.990085476979899000f, + 1.990047302480312300f, 1.990009054812374800f, 1.989970733977493000f, + 1.989932339977075900f, + 1.989893872812535000f, 1.989855332485284800f, 1.989816718996742200f, + 1.989778032348326700f, + 1.989739272541461100f, 1.989700439577570400f, 1.989661533458082100f, + 1.989622554184426800f, + 1.989583501758037700f, 1.989544376180350600f, 1.989505177452804100f, + 1.989465905576839600f, + 1.989426560553900500f, 1.989387142385433900f, 1.989347651072888900f, + 1.989308086617717500f, + 1.989268449021374300f, 1.989228738285316900f, 1.989188954411005100f, + 1.989149097399901500f, + 1.989109167253472000f, 1.989069163973184300f, 1.989029087560509700f, + 1.988988938016921000f, + 1.988948715343894900f, 1.988908419542910100f, 1.988868050615448100f, + 1.988827608562993200f, + 1.988787093387032600f, 1.988746505089055600f, 1.988705843670554500f, + 1.988665109133024500f, + 1.988624301477963200f, 1.988583420706871100f, 1.988542466821251000f, + 1.988501439822608900f, + 1.988460339712453200f, 1.988419166492295000f, 1.988377920163648000f, + 1.988336600728029000f, + 1.988295208186956700f, 1.988253742541953800f, 1.988212203794544000f, + 1.988170591946255100f, + 1.988128906998616800f, 1.988087148953161700f, 1.988045317811425700f, + 1.988003413574946000f, + 1.987961436245263800f, 1.987919385823922400f, 1.987877262312467600f, + 1.987835065712448600f, + 1.987792796025416500f, 1.987750453252925500f, 1.987708037396532800f, + 1.987665548457797400f, + 1.987622986438281700f, 1.987580351339550700f, 1.987537643163171700f, + 1.987494861910715100f, + 1.987452007583754100f, 1.987409080183863800f, 1.987366079712622900f, + 1.987323006171612500f, + 1.987279859562415900f, 1.987236639886619700f, 1.987193347145813000f, + 1.987149981341587400f, + 1.987106542475537400f, 1.987063030549260300f, 1.987019445564355700f, + 1.986975787522426100f, + 1.986932056425076800f, 1.986888252273915500f, 1.986844375070552900f, + 1.986800424816602200f, + 1.986756401513679400f, 1.986712305163403000f, 1.986668135767394300f, + 1.986623893327277500f, + 1.986579577844678900f, 1.986535189321228000f, 1.986490727758556800f, + 1.986446193158300400f, + 1.986401585522095600f, 1.986356904851583000f, 1.986312151148405200f, + 1.986267324414207500f, + 1.986222424650638400f, 1.986177451859348200f, 1.986132406041990900f, + 1.986087287200222700f, + 1.986042095335702300f, 1.985996830450091200f, 1.985951492545054100f, + 1.985906081622257300f, + 1.985860597683371000f, 1.985815040730067200f, 1.985769410764020900f, + 1.985723707786909900f, + 1.985677931800414500f, 1.985632082806217900f, 1.985586160806005700f, + 1.985540165801466200f, + 1.985494097794290800f, 1.985447956786173100f, 1.985401742778809500f, + 1.985355455773899500f, + 1.985309095773144500f, 1.985262662778249300f, 1.985216156790921000f, + 1.985169577812869500f, + 1.985122925845807400f, 1.985076200891450000f, 1.985029402951515200f, + 1.984982532027723700f, + 1.984935588121798700f, 1.984888571235466200f, 1.984841481370454900f, + 1.984794318528496200f, + 1.984747082711324100f, 1.984699773920675300f, 1.984652392158289500f, + 1.984604937425908300f, + 1.984557409725276700f, 1.984509809058142300f, 1.984462135426255000f, + 1.984414388831367900f, + 1.984366569275236400f, 1.984318676759618400f, 1.984270711286275200f, + 1.984222672856969800f, + 1.984174561473469200f, 1.984126377137541700f, 1.984078119850959200f, + 1.984029789615495900f, + 1.983981386432928800f, 1.983932910305037400f, 1.983884361233604100f, + 1.983835739220414000f, + 1.983787044267254700f, 1.983738276375916800f, 1.983689435548192900f, + 1.983640521785879200f, + 1.983591535090773800f, 1.983542475464678000f, 1.983493342909395500f, + 1.983444137426732600f, + 1.983394859018498900f, 1.983345507686505900f, 1.983296083432567900f, + 1.983246586258502700f, + 1.983197016166129400f, 1.983147373157271300f, 1.983097657233753100f, + 1.983047868397403100f, + 1.982998006650051400f, 1.982948071993531700f, 1.982898064429679900f, + 1.982847983960334600f, + 1.982797830587336800f, 1.982747604312531200f, 1.982697305137763700f, + 1.982646933064884200f, + 1.982596488095744300f, 1.982545970232199000f, 1.982495379476105800f, + 1.982444715829324600f, + 1.982393979293718200f, 1.982343169871152000f, 1.982292287563494300f, + 1.982241332372615600f, + 1.982190304300389400f, 1.982139203348692200f, 1.982088029519402300f, + 1.982036782814401900f, + 1.981985463235574700f, 1.981934070784807400f, 1.981882605463990200f, + 1.981831067275015000f, + 1.981779456219776600f, 1.981727772300172500f, 1.981676015518103500f, + 1.981624185875472000f, + 1.981572283374183800f, 1.981520308016147200f, 1.981468259803273300f, + 1.981416138737475800f, + 1.981363944820670800f, 1.981311678054777500f, 1.981259338441717400f, + 1.981206925983415300f, + 1.981154440681797800f, 1.981101882538794900f, 1.981049251556338900f, + 1.980996547736364900f, + 1.980943771080810700f, 1.980890921591616600f, 1.980837999270726100f, + 1.980785004120084700f, + 1.980731936141640900f, 1.980678795337345900f, 1.980625581709153600f, + 1.980572295259020600f, + 1.980518935988905700f, 1.980465503900771000f, 1.980411998996581200f, + 1.980358421278303200f, + 1.980304770747907300f, 1.980251047407365600f, 1.980197251258653900f, + 1.980143382303749500f, + 1.980089440544633600f, 1.980035425983289300f, 1.979981338621702200f, + 1.979927178461861500f, + 1.979872945505758000f, 1.979818639755386100f, 1.979764261212742400f, + 1.979709809879825800f, + 1.979655285758638900f, 1.979600688851186100f, 1.979546019159474900f, + 1.979491276685515300f, + 1.979436461431320000f, 1.979381573398904400f, 1.979326612590286400f, + 1.979271579007487100f, + 1.979216472652529900f, 1.979161293527440500f, 1.979106041634248100f, + 1.979050716974983800f, + 1.978995319551682100f, 1.978939849366379700f, 1.978884306421115900f, + 1.978828690717932900f, + 1.978773002258875600f, 1.978717241045991700f, 1.978661407081331100f, + 1.978605500366946700f, + 1.978549520904894000f, 1.978493468697231300f, 1.978437343746019600f, + 1.978381146053322000f, + 1.978324875621205300f, 1.978268532451738200f, 1.978212116546992100f, + 1.978155627909041300f, + 1.978099066539962900f, 1.978042432441836400f, 1.977985725616743900f, + 1.977928946066770600f, + 1.977872093794004200f, 1.977815168800534500f, 1.977758171088455100f, + 1.977701100659861300f, + 1.977643957516851400f, 1.977586741661526500f, 1.977529453095990200f, + 1.977472091822348700f, + 1.977414657842711200f, 1.977357151159189400f, 1.977299571773897700f, + 1.977241919688953000f, + 1.977184194906475000f, 1.977126397428586000f, 1.977068527257411300f, + 1.977010584395078300f, + 1.976952568843717700f, 1.976894480605462500f, 1.976836319682448300f, + 1.976778086076813600f, + 1.976719779790699500f, 1.976661400826249500f, 1.976602949185610500f, + 1.976544424870931400f, + 1.976485827884363800f, 1.976427158228062100f, 1.976368415904183900f, + 1.976309600914888400f, + 1.976250713262338600f, 1.976191752948699200f, 1.976132719976138000f, + 1.976073614346825800f, + 1.976014436062935700f, 1.975955185126643300f, 1.975895861540127200f, + 1.975836465305568400f, + 1.975776996425151000f, 1.975717454901061400f, 1.975657840735488800f, + 1.975598153930624900f, + 1.975538394488664200f, 1.975478562411804100f, 1.975418657702244300f, + 1.975358680362187400f, + 1.975298630393838500f, 1.975238507799405500f, 1.975178312581099100f, + 1.975118044741132300f, + 1.975057704281721000f, 1.974997291205083700f, 1.974936805513442000f, + 1.974876247209019100f, + 1.974815616294042200f, 1.974754912770740200f, 1.974694136641345300f, + 1.974633287908091500f, + 1.974572366573216400f, 1.974511372638960000f, 1.974450306107564900f, + 1.974389166981275900f, + 1.974327955262341400f, 1.974266670953011400f, 1.974205314055540000f, + 1.974143884572182400f, + 1.974082382505197400f, 1.974020807856846400f, 1.973959160629393100f, + 1.973897440825104200f, + 1.973835648446248900f, 1.973773783495099500f, 1.973711845973930000f, + 1.973649835885018100f, + 1.973587753230643400f, 1.973525598013088800f, 1.973463370234639600f, + 1.973401069897583200f, + 1.973338697004211100f, 1.973276251556815600f, 1.973213733557693400f, + 1.973151143009142800f, + 1.973088479913465100f, 1.973025744272964200f, 1.972962936089946800f, + 1.972900055366722000f, + 1.972837102105601900f, 1.972774076308901200f, 1.972710977978936900f, + 1.972647807118029300f, + 1.972584563728500700f, 1.972521247812676600f, 1.972457859372884500f, + 1.972394398411455800f, + 1.972330864930723200f, 1.972267258933022600f, 1.972203580420693000f, + 1.972139829396075200f, + 1.972076005861513700f, 1.972012109819354600f, 1.971948141271947500f, + 1.971884100221644300f, + 1.971819986670799500f, 1.971755800621770400f, 1.971691542076916800f, + 1.971627211038601500f, + 1.971562807509189800f, 1.971498331491049700f, 1.971433782986551400f, + 1.971369161998068400f, + 1.971304468527976800f, 1.971239702578655000f, 1.971174864152484400f, + 1.971109953251848600f, + 1.971044969879134600f, 1.970979914036731500f, 1.970914785727030800f, + 1.970849584952427900f, + 1.970784311715319400f, 1.970718966018105500f, 1.970653547863188600f, + 1.970588057252973900f, + 1.970522494189869800f, 1.970456858676286300f, 1.970391150714636800f, + 1.970325370307337100f, + 1.970259517456806100f, 1.970193592165464700f, 1.970127594435737000f, + 1.970061524270049400f, + 1.969995381670831100f, 1.969929166640514100f, 1.969862879181532700f, + 1.969796519296324300f, + 1.969730086987328900f, 1.969663582256988600f, 1.969597005107748900f, + 1.969530355542057800f, + 1.969463633562365400f, 1.969396839171125200f, 1.969329972370792700f, + 1.969263033163826800f, + 1.969196021552688500f, 1.969128937539841500f, 1.969061781127752400f, + 1.968994552318890300f, + 1.968927251115727200f, 1.968859877520737300f, 1.968792431536398000f, + 1.968724913165188900f, + 1.968657322409592500f, 1.968589659272094000f, 1.968521923755181000f, + 1.968454115861344000f, + 1.968386235593076300f, 1.968318282952873600f, 1.968250257943234200f, + 1.968182160566659000f, + 1.968113990825652200f, 1.968045748722719900f, 1.967977434260371300f, + 1.967909047441118100f, + 1.967840588267474500f, 1.967772056741957900f, 1.967703452867087800f, + 1.967634776645386600f, + 1.967566028079379200f, 1.967497207171593500f, 1.967428313924559600f, + 1.967359348340810700f, + 1.967290310422882700f, 1.967221200173313400f, 1.967152017594644200f, + 1.967082762689418500f, + 1.967013435460182700f, 1.966944035909485600f, 1.966874564039879300f, + 1.966805019853917500f, + 1.966735403354157500f, 1.966665714543159000f, 1.966595953423483800f, + 1.966526119997697100f, + 1.966456214268366600f, 1.966386236238062200f, 1.966316185909357200f, + 1.966246063284826700f, + 1.966175868367049400f, 1.966105601158605600f, 1.966035261662079300f, + 1.965964849880056600f, + 1.965894365815126000f, 1.965823809469879400f, 1.965753180846910900f, + 1.965682479948817100f, + 1.965611706778197700f, 1.965540861337654600f, 1.965469943629792700f, + 1.965398953657219600f, + 1.965327891422544900f, 1.965256756928382100f, 1.965185550177345900f, + 1.965114271172054800f, + 1.965042919915129400f, 1.964971496409193100f, 1.964900000656872000f, + 1.964828432660794500f, + 1.964756792423592200f, 1.964685079947899200f, 1.964613295236352000f, + 1.964541438291590000f, + 1.964469509116255000f, 1.964397507712991800f, 1.964325434084447600f, + 1.964253288233272400f, + 1.964181070162119000f, 1.964108779873642100f, 1.964036417370500300f, + 1.963963982655353400f, + 1.963891475730865400f, 1.963818896599701400f, 1.963746245264530700f, + 1.963673521728023900f, + 1.963600725992855200f, 1.963527858061700600f, 1.963454917937239800f, + 1.963381905622154400f, + 1.963308821119128700f, 1.963235664430850200f, 1.963162435560008100f, + 1.963089134509295300f, + 1.963015761281406800f, 1.962942315879040000f, 1.962868798304895400f, + 1.962795208561676200f, + 1.962721546652088200f, 1.962647812578839400f, 1.962574006344640900f, + 1.962500127952206300f, + 1.962426177404252200f, 1.962352154703497200f, 1.962278059852663000f, + 1.962203892854473800f, + 1.962129653711656800f, 1.962055342426941400f, 1.961980959003059500f, + 1.961906503442746300f, + 1.961831975748739200f, 1.961757375923778700f, 1.961682703970607100f, + 1.961607959891970200f, + 1.961533143690616000f, 1.961458255369295400f, 1.961383294930761700f, + 1.961308262377770900f, + 1.961233157713082200f, 1.961157980939456400f, 1.961082732059657800f, + 1.961007411076453000f, + 1.960932017992611500f, 1.960856552810905200f, 1.960781015534108800f, + 1.960705406164999300f, + 1.960629724706357100f, 1.960553971160964500f, 1.960478145531606700f, + 1.960402247821071900f, + 1.960326278032150200f, 1.960250236167635100f, 1.960174122230322400f, + 1.960097936223010400f, + 1.960021678148500500f, 1.959945348009596500f, 1.959868945809104500f, + 1.959792471549834000f, + 1.959715925234596600f, 1.959639306866206600f, 1.959562616447480900f, + 1.959485853981239600f, + 1.959409019470304700f, 1.959332112917501400f, 1.959255134325657000f, + 1.959178083697602300f, + 1.959100961036169800f, 1.959023766344195200f, 1.958946499624516700f, + 1.958869160879975500f, + 1.958791750113414700f, 1.958714267327680500f, 1.958636712525621900f, + 1.958559085710090500f, + 1.958481386883940100f, 1.958403616050027600f, 1.958325773211212300f, + 1.958247858370356400f, + 1.958169871530324600f, 1.958091812693984400f, 1.958013681864205500f, + 1.957935479043860600f, + 1.957857204235825100f, 1.957778857442976900f, 1.957700438668196700f, + 1.957621947914367500f, + 1.957543385184375300f, 1.957464750481108700f, 1.957386043807458800f, + 1.957307265166319500f, + 1.957228414560587200f, 1.957149491993160900f, 1.957070497466942400f, + 1.956991430984836400f, + 1.956912292549749500f, 1.956833082164591600f, 1.956753799832275300f, + 1.956674445555715000f, + 1.956595019337829000f, 1.956515521181537000f, 1.956435951089762200f, + 1.956356309065430100f, + 1.956276595111468900f, 1.956196809230809500f, 1.956116951426385600f, + 1.956037021701132900f, + 1.955957020057990500f, 1.955876946499899700f, 1.955796801029804800f, + 1.955716583650652000f, + 1.955636294365391300f, 1.955555933176974300f, 1.955475500088355900f, + 1.955394995102493100f, + 1.955314418222346100f, 1.955233769450877200f, 1.955153048791052000f, + 1.955072256245838000f, + 1.954991391818206000f, 1.954910455511129000f, 1.954829447327582900f, + 1.954748367270545900f, + 1.954667215342999600f, 1.954585991547927100f, 1.954504695888315000f, + 1.954423328367152600f, + 1.954341888987431100f, 1.954260377752145000f, 1.954178794664291200f, + 1.954097139726869600f, + 1.954015412942881900f, 1.953933614315333200f, 1.953851743847231100f, + 1.953769801541585400f, + 1.953687787401409400f, 1.953605701429718100f, 1.953523543629529700f, + 1.953441314003864900f, + 1.953359012555747200f, 1.953276639288202400f, 1.953194194204259200f, + 1.953111677306948800f, + 1.953029088599305100f, 1.952946428084364900f, 1.952863695765167100f, + 1.952780891644753500f, + 1.952698015726169100f, 1.952615068012460300f, 1.952532048506677300f, + 1.952448957211872200f, + 1.952365794131100300f, 1.952282559267419100f, 1.952199252623889200f, + 1.952115874203572900f, + 1.952032424009536600f, 1.951948902044847900f, 1.951865308312577900f, + 1.951781642815800100f, + 1.951697905557590700f, 1.951614096541028500f, 1.951530215769194700f, + 1.951446263245173500f, + 1.951362238972051500f, 1.951278142952918200f, 1.951193975190865600f, + 1.951109735688987900f, + 1.951025424450382900f, 1.950941041478150100f, 1.950856586775392200f, + 1.950772060345214300f, + 1.950687462190724200f, 1.950602792315032200f, 1.950518050721251600f, + 1.950433237412498000f, + 1.950348352391889600f, 1.950263395662547700f, 1.950178367227595900f, + 1.950093267090159800f, + 1.950008095253369200f, 1.949922851720355100f, 1.949837536494251700f, + 1.949752149578196000f, + 1.949666690975327100f, 1.949581160688787400f, 1.949495558721721500f, + 1.949409885077276500f, + 1.949324139758602700f, 1.949238322768852800f, 1.949152434111181700f, + 1.949066473788747300f, + 1.948980441804710300f, 1.948894338162233900f, 1.948808162864483600f, + 1.948721915914628100f, + 1.948635597315838200f, 1.948549207071288000f, 1.948462745184153400f, + 1.948376211657613500f, + 1.948289606494849800f, 1.948202929699046800f, 1.948116181273391100f, + 1.948029361221072400f, + 1.947942469545282500f, 1.947855506249216700f, 1.947768471336071700f, + 1.947681364809048100f, + 1.947594186671348000f, 1.947506936926177300f, 1.947419615576743600f, + 1.947332222626257500f, + 1.947244758077932200f, 1.947157221934983500f, 1.947069614200629900f, + 1.946981934878092300f, + 1.946894183970594900f, 1.946806361481363500f, 1.946718467413627300f, + 1.946630501770618000f, + 1.946542464555569800f, 1.946454355771719300f, 1.946366175422306500f, + 1.946277923510573200f, + 1.946189600039764300f, 1.946101205013127000f, 1.946012738433911600f, + 1.945924200305370700f, + 1.945835590630759400f, 1.945746909413335900f, 1.945658156656360700f, + 1.945569332363096700f, + 1.945480436536810100f, 1.945391469180769200f, 1.945302430298244900f, + 1.945213319892511200f, + 1.945124137966844200f, 1.945034884524523100f, 1.944945559568829200f, + 1.944856163103046800f, + 1.944766695130463000f, 1.944677155654366900f, 1.944587544678050900f, + 1.944497862204809900f, + 1.944408108237940700f, 1.944318282780743900f, 1.944228385836521700f, + 1.944138417408579400f, + 1.944048377500225100f, 1.943958266114769200f, 1.943868083255524800f, + 1.943777828925807600f, + 1.943687503128936200f, 1.943597105868231500f, 1.943506637147017300f, + 1.943416096968619400f, + 1.943325485336367300f, 1.943234802253592400f, 1.943144047723628400f, + 1.943053221749812400f, + 1.942962324335484100f, 1.942871355483985200f, 1.942780315198660200f, + 1.942689203482856900f, + 1.942598020339924700f, 1.942506765773216500f, 1.942415439786087300f, + 1.942324042381895000f, + 1.942232573564000000f, 1.942141033335765400f, 1.942049421700556600f, + 1.941957738661741900f, + 1.941865984222692900f, 1.941774158386782200f, 1.941682261157386700f, + 1.941590292537884700f, + 1.941498252531658200f, 1.941406141142090600f, 1.941313958372568900f, + 1.941221704226482500f, + 1.941129378707223000f, 1.941036981818185400f, 1.940944513562766300f, + 1.940851973944365900f, + 1.940759362966386600f, 1.940666680632233200f, 1.940573926945313700f, + 1.940481101909038200f, + 1.940388205526819600f, 1.940295237802073500f, 1.940202198738217900f, + 1.940109088338673600f, + 1.940015906606864300f, 1.939922653546215500f, 1.939829329160156500f, + 1.939735933452118000f, + 1.939642466425534300f, 1.939548928083841800f, 1.939455318430479500f, + 1.939361637468889100f, + 1.939267885202515400f, 1.939174061634805000f, 1.939080166769207700f, + 1.938986200609175600f, + 1.938892163158163700f, 1.938798054419629500f, 1.938703874397032800f, + 1.938609623093837000f, + 1.938515300513506700f, 1.938420906659510600f, 1.938326441535318500f, + 1.938231905144404400f, + 1.938137297490243500f, 1.938042618576314400f, 1.937947868406098500f, + 1.937853046983079300f, + 1.937758154310742900f, 1.937663190392578500f, 1.937568155232077600f, + 1.937473048832734500f, + 1.937377871198045600f, 1.937282622331510500f, 1.937187302236631500f, + 1.937091910916912900f, + 1.936996448375861900f, 1.936900914616988900f, 1.936805309643805800f, + 1.936709633459828200f, + 1.936613886068573500f, 1.936518067473562300f, 1.936422177678317300f, + 1.936326216686364400f, + 1.936230184501231500f, 1.936134081126449800f, 1.936037906565552400f, + 1.935941660822075600f, + 1.935845343899558000f, 1.935748955801540800f, 1.935652496531568000f, + 1.935555966093186300f, + 1.935459364489944500f, 1.935362691725394500f, 1.935265947803090900f, + 1.935169132726590500f, + 1.935072246499453000f, 1.934975289125240500f, 1.934878260607517900f, + 1.934781160949852600f, + 1.934683990155814800f, 1.934586748228977100f, 1.934489435172914900f, + 1.934392050991206300f, + 1.934294595687431300f, 1.934197069265173500f, 1.934099471728018700f, + 1.934001803079554700f, + 1.933904063323373300f, 1.933806252463067500f, 1.933708370502233800f, + 1.933610417444471000f, + 1.933512393293380600f, 1.933414298052566600f, 1.933316131725635800f, + 1.933217894316197300f, + 1.933119585827862900f, 1.933021206264247600f, 1.932922755628968100f, + 1.932824233925644300f, + 1.932725641157898600f, 1.932626977329356100f, 1.932528242443643900f, + 1.932429436504392800f, + 1.932330559515235100f, 1.932231611479806800f, 1.932132592401745400f, + 1.932033502284691700f, + 1.931934341132289100f, 1.931835108948183300f, 1.931735805736022800f, + 1.931636431499459000f, + 1.931536986242145200f, 1.931437469967737900f, 1.931337882679895900f, + 1.931238224382281000f, + 1.931138495078557300f, 1.931038694772391200f, 1.930938823467452500f, + 1.930838881167413100f, + 1.930738867875947400f, 1.930638783596732700f, 1.930538628333448900f, + 1.930438402089778200f, + 1.930338104869405900f, 1.930237736676019500f, 1.930137297513309300f, + 1.930036787384968200f, + 1.929936206294691400f, 1.929835554246177400f, 1.929734831243126600f, + 1.929634037289242400f, + 1.929533172388230700f, 1.929432236543799900f, 1.929331229759661200f, + 1.929230152039528500f, + 1.929129003387117800f, 1.929027783806148300f, 1.928926493300341400f, + 1.928825131873421500f, + 1.928723699529115000f, 1.928622196271151800f, 1.928520622103263400f, + 1.928418977029184600f, + 1.928317261052652700f, 1.928215474177407100f, 1.928113616407190600f, + 1.928011687745748300f, + 1.927909688196827400f, 1.927807617764178300f, 1.927705476451554000f, + 1.927603264262709900f, + 1.927500981201404100f, 1.927398627271397000f, 1.927296202476451900f, + 1.927193706820335100f, + 1.927091140306814500f, 1.926988502939661400f, 1.926885794722649600f, + 1.926783015659555300f, + 1.926680165754157500f, 1.926577245010237400f, 1.926474253431579500f, + 1.926371191021970100f, + 1.926268057785198700f, 1.926164853725057300f, 1.926061578845340600f, + 1.925958233149845000f, + 1.925854816642371000f, 1.925751329326720600f, 1.925647771206698600f, + 1.925544142286112800f, + 1.925440442568773000f, 1.925336672058492300f, 1.925232830759086000f, + 1.925128918674371900f, + 1.925024935808170600f, 1.924920882164305300f, 1.924816757746601800f, + 1.924712562558888100f, + 1.924608296604995800f, 1.924503959888757900f, 1.924399552414010700f, + 1.924295074184593000f, + 1.924190525204346300f, 1.924085905477114400f, 1.923981215006744100f, + 1.923876453797084300f, + 1.923771621851986700f, 1.923666719175306100f, 1.923561745770898900f, + 1.923456701642625200f, + 1.923351586794346900f, 1.923246401229928600f, 1.923141144953238300f, + 1.923035817968145300f, + 1.922930420278522500f, 1.922824951888245000f, 1.922719412801190600f, + 1.922613803021239600f, + 1.922508122552275100f, 1.922402371398182600f, 1.922296549562850100f, + 1.922190657050168800f, + 1.922084693864031700f, 1.921978660008334600f, 1.921872555486976700f, + 1.921766380303858500f, + 1.921660134462884100f, 1.921553817967959900f, 1.921447430822994500f, + 1.921340973031900000f, + 1.921234444598590100f, 1.921127845526981600f, 1.921021175820994100f, + 1.920914435484549100f, + 1.920807624521571700f, 1.920700742935988600f, 1.920593790731729600f, + 1.920486767912727300f, + 1.920379674482916500f, 1.920272510446234400f, 1.920165275806621400f, + 1.920057970568020100f, + 1.919950594734376000f, 1.919843148309637000f, 1.919735631297753400f, + 1.919628043702678300f, + 1.919520385528367300f, 1.919412656778779000f, 1.919304857457874200f, + 1.919196987569616200f, + 1.919089047117971100f, 1.918981036106907700f, 1.918872954540397300f, + 1.918764802422413500f, + 1.918656579756932800f, 1.918548286547934400f, 1.918439922799399800f, + 1.918331488515313300f, + 1.918222983699661600f, 1.918114408356434300f, 1.918005762489623400f, + 1.917897046103223200f, + 1.917788259201231200f, 1.917679401787647100f, 1.917570473866473200f, + 1.917461475441714500f, + 1.917352406517378600f, 1.917243267097475700f, 1.917134057186018300f, + 1.917024776787022100f, + 1.916915425904504700f, 1.916806004542486800f, 1.916696512704991500f, + 1.916586950396044400f, + 1.916477317619674100f, 1.916367614379911100f, 1.916257840680788900f, + 1.916147996526343700f, + 1.916038081920614400f, 1.915928096867641800f, 1.915818041371470000f, + 1.915707915436145200f, + 1.915597719065716700f, 1.915487452264236000f, 1.915377115035757200f, + 1.915266707384337200f, + 1.915156229314035200f, 1.915045680828913400f, 1.914935061933036300f, + 1.914824372630470800f, + 1.914713612925287100f, 1.914602782821557000f, 1.914491882323355700f, + 1.914380911434760500f, + 1.914269870159851700f, 1.914158758502712000f, 1.914047576467426500f, + 1.913936324058083100f, + 1.913825001278772100f, 1.913713608133586600f, 1.913602144626622500f, + 1.913490610761977600f, + 1.913379006543752800f, 1.913267331976051400f, 1.913155587062979500f, + 1.913043771808645700f, + 1.912931886217160900f, 1.912819930292639000f, 1.912707904039196300f, + 1.912595807460951500f, + 1.912483640562026200f, 1.912371403346544400f, 1.912259095818632700f, + 1.912146717982420500f, + 1.912034269842039600f, 1.911921751401624200f, 1.911809162665311500f, + 1.911696503637241100f, + 1.911583774321554700f, 1.911470974722397500f, 1.911358104843916500f, + 1.911245164690262000f, + 1.911132154265586100f, 1.911019073574044200f, 1.910905922619793800f, + 1.910792701406995000f, + 1.910679409939810600f, 1.910566048222406300f, 1.910452616258949900f, + 1.910339114053611900f, + 1.910225541610565800f, 1.910111898933986900f, 1.909998186028053700f, + 1.909884402896947100f, + 1.909770549544850500f, 1.909656625975950200f, 1.909542632194434700f, + 1.909428568204495100f, + 1.909314434010325400f, 1.909200229616121700f, 1.909085955026083200f, + 1.908971610244411600f, + 1.908857195275310800f, 1.908742710122987700f, 1.908628154791651300f, + 1.908513529285513500f, + 1.908398833608789100f, 1.908284067765694900f, 1.908169231760450400f, + 1.908054325597278200f, + 1.907939349280402400f, 1.907824302814050900f, 1.907709186202453600f, + 1.907593999449842800f, + 1.907478742560453600f, 1.907363415538523700f, 1.907248018388293400f, + 1.907132551114005600f, + 1.907017013719905600f, 1.906901406210241200f, 1.906785728589263300f, + 1.906669980861224900f, + 1.906554163030381500f, 1.906438275100991600f, 1.906322317077316300f, + 1.906206288963618700f, + 1.906090190764164700f, 1.905974022483223300f, 1.905857784125065500f, + 1.905741475693964800f, + 1.905625097194197900f, 1.905508648630043700f, 1.905392130005783400f, + 1.905275541325701400f, + 1.905158882594083900f, 1.905042153815220700f, 1.904925354993402900f, + 1.904808486132925300f, + 1.904691547238084800f, 1.904574538313180700f, 1.904457459362515200f, + 1.904340310390393100f, + 1.904223091401121600f, 1.904105802399010300f, 1.903988443388371600f, + 1.903871014373520700f, + 1.903753515358774800f, 1.903635946348454500f, 1.903518307346881800f, + 1.903400598358382600f, + 1.903282819387284200f, 1.903164970437917400f, 1.903047051514615000f, + 1.902929062621712600f, + 1.902811003763547900f, 1.902692874944462300f, 1.902574676168798700f, + 1.902456407440902700f, + 1.902338068765123200f, 1.902219660145810800f, 1.902101181587319000f, + 1.901982633094004200f, + 1.901864014670225000f, 1.901745326320342500f, 1.901626568048721000f, + 1.901507739859726200f, + 1.901388841757727600f, 1.901269873747096600f, 1.901150835832207100f, + 1.901031728017436300f, + 1.900912550307162700f, 1.900793302705768900f, 1.900673985217638900f, + 1.900554597847159400f, + 1.900435140598720500f, 1.900315613476714100f, 1.900196016485534700f, + 1.900076349629579600f, + 1.899956612913248800f, 1.899836806340944300f, 1.899716929917071500f, + 1.899596983646037600f, + 1.899476967532252900f, 1.899356881580129800f, 1.899236725794083600f, + 1.899116500178532200f, + 1.898996204737895900f, 1.898875839476597700f, 1.898755404399062900f, + 1.898634899509719500f, + 1.898514324812998300f, 1.898393680313332600f, 1.898272966015157800f, + 1.898152181922912600f, + 1.898031328041037700f, 1.897910404373976500f, 1.897789410926175000f, + 1.897668347702081900f, + 1.897547214706148300f, 1.897426011942827900f, 1.897304739416577200f, + 1.897183397131854600f, + 1.897061985093121800f, 1.896940503304842800f, 1.896818951771484000f, + 1.896697330497514800f, + 1.896575639487406300f, 1.896453878745633100f, 1.896332048276672100f, + 1.896210148085002400f, + 1.896088178175106200f, 1.895966138551467700f, 1.895844029218574100f, + 1.895721850180915000f, + 1.895599601442982600f, 1.895477283009271400f, 1.895354894884279100f, + 1.895232437072505300f, + 1.895109909578452500f, 1.894987312406625700f, 1.894864645561532100f, + 1.894741909047682500f, + 1.894619102869589100f, 1.894496227031767100f, 1.894373281538734400f, + 1.894250266395011600f, + 1.894127181605121100f, 1.894004027173588700f, 1.893880803104942600f, + 1.893757509403713100f, + 1.893634146074433500f, 1.893510713121639300f, 1.893387210549869000f, + 1.893263638363663400f, + 1.893139996567565900f, 1.893016285166122500f, 1.892892504163881600f, + 1.892768653565394300f, + 1.892644733375214300f, 1.892520743597897700f, 1.892396684238003300f, + 1.892272555300092300f, + 1.892148356788728700f, 1.892024088708479200f, 1.891899751063912200f, + 1.891775343859599400f, + 1.891650867100115300f, 1.891526320790036100f, 1.891401704933941100f, + 1.891277019536412400f, + 1.891152264602033800f, 1.891027440135392600f, 1.890902546141078000f, + 1.890777582623682300f, + 1.890652549587799700f, 1.890527447038027300f, 1.890402274978965100f, + 1.890277033415215200f, + 1.890151722351382200f, 1.890026341792073500f, 1.889900891741899100f, + 1.889775372205471300f, + 1.889649783187405100f, 1.889524124692318200f, 1.889398396724830500f, + 1.889272599289564900f, + 1.889146732391146400f, 1.889020796034202700f, 1.888894790223364600f, + 1.888768714963264400f, + 1.888642570258537700f, 1.888516356113822700f, 1.888390072533759700f, + 1.888263719522991900f, + 1.888137297086165000f, 1.888010805227927000f, 1.887884243952928600f, + 1.887757613265823400f, + 1.887630913171267000f, 1.887504143673917700f, 1.887377304778437000f, + 1.887250396489487800f, + 1.887123418811736500f, 1.886996371749851700f, 1.886869255308504200f, + 1.886742069492368000f, + 1.886614814306119400f, 1.886487489754437300f, 1.886360095842002600f, + 1.886232632573499700f, + 1.886105099953614900f, 1.885977497987037000f, 1.885849826678457800f, + 1.885722086032571200f, + 1.885594276054074300f, 1.885466396747665700f, 1.885338448118047700f, + 1.885210430169924200f, + 1.885082342908002400f, 1.884954186336991400f, 1.884825960461603100f, + 1.884697665286552400f, + 1.884569300816556000f, 1.884440867056333700f, 1.884312364010607600f, + 1.884183791684102400f, + 1.884055150081545200f, 1.883926439207665800f, 1.883797659067196800f, + 1.883668809664872600f, + 1.883539891005431100f, 1.883410903093611900f, 1.883281845934157800f, + 1.883152719531813800f, + 1.883023523891327300f, 1.882894259017448900f, 1.882764924914930700f, + 1.882635521588528400f, + 1.882506049042999700f, 1.882376507283104900f, 1.882246896313606800f, + 1.882117216139270700f, + 1.881987466764865100f, 1.881857648195159900f, 1.881727760434928500f, + 1.881597803488946500f, + 1.881467777361992100f, 1.881337682058845700f, 1.881207517584290600f, + 1.881077283943112900f, + 1.880946981140100500f, 1.880816609180044700f, 1.880686168067738500f, + 1.880555657807977800f, + 1.880425078405561600f, 1.880294429865290600f, 1.880163712191968300f, + 1.880032925390400900f, + 1.879902069465397200f, 1.879771144421768200f, 1.879640150264327600f, + 1.879509086997891900f, + 1.879377954627279700f, 1.879246753157312700f, 1.879115482592814500f, + 1.878984142938611600f, + 1.878852734199532900f, 1.878721256380410100f, 1.878589709486077300f, + 1.878458093521370800f, + 1.878326408491130200f, 1.878194654400196600f, 1.878062831253414900f, + 1.877930939055631100f, + 1.877798977811695200f, 1.877666947526458700f, 1.877534848204775800f, + 1.877402679851504000f, + 1.877270442471502100f, 1.877138136069632400f, 1.877005760650759500f, + 1.876873316219750200f, + 1.876740802781474500f, 1.876608220340804100f, 1.876475568902614000f, + 1.876342848471781200f, + 1.876210059053185600f, 1.876077200651709500f, 1.875944273272237800f, + 1.875811276919657500f, + 1.875678211598858800f, 1.875545077314734000f, 1.875411874072178100f, + 1.875278601876088700f, + 1.875145260731365700f, 1.875011850642911600f, 1.874878371615631900f, + 1.874744823654434000f, + 1.874611206764227800f, 1.874477520949926500f, 1.874343766216444800f, + 1.874209942568701100f, + 1.874076050011615400f, 1.873942088550110400f, 1.873808058189111700f, + 1.873673958933546900f, + 1.873539790788347100f, 1.873405553758444600f, 1.873271247848775400f, + 1.873136873064277000f, + 1.873002429409890600f, 1.872867916890558900f, 1.872733335511227700f, + 1.872598685276845000f, + 1.872463966192361900f, 1.872329178262731200f, 1.872194321492908700f, + 1.872059395887852900f, + 1.871924401452524700f, 1.871789338191887100f, 1.871654206110906500f, + 1.871519005214550700f, + 1.871383735507791100f, 1.871248396995601300f, 1.871112989682956800f, + 1.870977513574836500f, + 1.870841968676221400f, 1.870706354992095000f, 1.870570672527443600f, + 1.870434921287255700f, + 1.870299101276522400f, 1.870163212500237900f, 1.870027254963397800f, + 1.869891228671001200f, + 1.869755133628049600f, 1.869618969839546500f, 1.869482737310498100f, + 1.869346436045913800f, + 1.869210066050804600f, 1.869073627330184700f, 1.868937119889070300f, + 1.868800543732480600f, + 1.868663898865437200f, 1.868527185292963700f, 1.868390403020087100f, + 1.868253552051836200f, + 1.868116632393243000f, 1.867979644049341200f, 1.867842587025167800f, + 1.867705461325761800f, + 1.867568266956164800f, 1.867431003921421500f, 1.867293672226578300f, + 1.867156271876684500f, + 1.867018802876792200f, 1.866881265231955500f, 1.866743658947231300f, + 1.866605984027679000f, + 1.866468240478360600f, 1.866330428304340300f, 1.866192547510685300f, + 1.866054598102465000f, + 1.865916580084751500f, 1.865778493462619100f, 1.865640338241145100f, + 1.865502114425408900f, + 1.865363822020492700f, 1.865225461031480900f, 1.865087031463460900f, + 1.864948533321522300f, + 1.864809966610757400f, 1.864671331336260600f, 1.864532627503129100f, + 1.864393855116463200f, + 1.864255014181364500f, 1.864116104702938000f, 1.863977126686291200f, + 1.863838080136534000f, + 1.863698965058778300f, 1.863559781458139300f, 1.863420529339734100f, + 1.863281208708683000f, + 1.863141819570107900f, 1.863002361929134500f, 1.862862835790889400f, + 1.862723241160503300f, + 1.862583578043108100f, 1.862443846443839300f, 1.862304046367834200f, + 1.862164177820232700f, + 1.862024240806177800f, 1.861884235330814300f, 1.861744161399289600f, + 1.861604019016754200f, + 1.861463808188360500f, 1.861323528919263800f, 1.861183181214621600f, + 1.861042765079594200f, + 1.860902280519344500f, 1.860761727539037300f, 1.860621106143840500f, + 1.860480416338924600f, + 1.860339658129461800f, 1.860198831520627900f, 1.860057936517600700f, + 1.859916973125560000f, + 1.859775941349689000f, 1.859634841195173100f, 1.859493672667199800f, + 1.859352435770959900f, + 1.859211130511645900f, 1.859069756894453400f, 1.858928314924580300f, + 1.858786804607227100f, + 1.858645225947596300f, 1.858503578950893900f, 1.858361863622327400f, + 1.858220079967107600f, + 1.858078227990447300f, 1.857936307697561900f, 1.857794319093669900f, + 1.857652262183991000f, + 1.857510136973749000f, 1.857367943468169100f, 1.857225681672479300f, + 1.857083351591910300f, + 1.856940953231694900f, 1.856798486597069000f, 1.856655951693270600f, + 1.856513348525540300f, + 1.856370677099121100f, 1.856227937419258700f, 1.856085129491201100f, + 1.855942253320199200f, + 1.855799308911506100f, 1.855656296270377300f, 1.855513215402071000f, + 1.855370066311848000f, + 1.855226849004971500f, 1.855083563486706900f, 1.854940209762322700f, + 1.854796787837089500f, + 1.854653297716280400f, 1.854509739405171300f, 1.854366112909040300f, + 1.854222418233168400f, + 1.854078655382838300f, 1.853934824363336200f, 1.853790925179950500f, + 1.853646957837971500f, + 1.853502922342692600f, 1.853358818699409900f, 1.853214646913421200f, + 1.853070406990027500f, + 1.852926098934532200f, 1.852781722752241000f, 1.852637278448462200f, + 1.852492766028506400f, + 1.852348185497687300f, 1.852203536861320600f, 1.852058820124724300f, + 1.851914035293219700f, + 1.851769182372129600f, 1.851624261366780400f, 1.851479272282500000f, + 1.851334215124619300f, + 1.851189089898471800f, 1.851043896609393400f, 1.850898635262721900f, + 1.850753305863798800f, + 1.850607908417967200f, 1.850462442930572900f, 1.850316909406964200f, + 1.850171307852492200f, + 1.850025638272510000f, 1.849879900672373600f, 1.849734095057441200f, + 1.849588221433073700f, + 1.849442279804634600f, 1.849296270177489800f, 1.849150192557007300f, + 1.849004046948558200f, + 1.848857833357515900f, 1.848711551789256300f, 1.848565202249157400f, + 1.848418784742600400f, + 1.848272299274968500f, 1.848125745851647800f, 1.847979124478026100f, + 1.847832435159495000f, + 1.847685677901447200f, 1.847538852709279100f, 1.847391959588388300f, + 1.847244998544176300f, + 1.847097969582046200f, 1.846950872707404000f, 1.846803707925657600f, + 1.846656475242218300f, + 1.846509174662499300f, 1.846361806191916000f, 1.846214369835887500f, + 1.846066865599834000f, + 1.845919293489179000f, 1.845771653509348200f, 1.845623945665770100f, + 1.845476169963875500f, + 1.845328326409097400f, 1.845180415006871800f, 1.845032435762637100f, + 1.844884388681833800f, + 1.844736273769905300f, 1.844588091032297400f, 1.844439840474458200f, + 1.844291522101838800f, + 1.844143135919891900f, 1.843994681934073600f, 1.843846160149842200f, + 1.843697570572658200f, + 1.843548913207985000f, 1.843400188061288000f, 1.843251395138035800f, + 1.843102534443698900f, + 1.842953605983750400f, 1.842804609763666100f, 1.842655545788924000f, + 1.842506414065004900f, + 1.842357214597392100f, 1.842207947391570900f, 1.842058612453029600f, + 1.841909209787258900f, + 1.841759739399751800f, 1.841610201296003800f, 1.841460595481513100f, + 1.841310921961780500f, + 1.841161180742308500f, 1.841011371828603200f, 1.840861495226172600f, + 1.840711550940526700f, + 1.840561538977179200f, 1.840411459341645400f, 1.840261312039443100f, + 1.840111097076092800f, + 1.839960814457117600f, 1.839810464188043100f, 1.839660046274397100f, + 1.839509560721709800f, + 1.839359007535514400f, 1.839208386721346500f, 1.839057698284743500f, + 1.838906942231246100f, + 1.838756118566397200f, 1.838605227295741800f, 1.838454268424828400f, + 1.838303241959206700f, + 1.838152147904429800f, 1.838000986266052900f, 1.837849757049633900f, + 1.837698460260732900f, + 1.837547095904912700f, 1.837395663987738700f, 1.837244164514778600f, + 1.837092597491602100f, + 1.836940962923782700f, 1.836789260816895000f, 1.836637491176516600f, + 1.836485654008228200f, + 1.836333749317611700f, 1.836181777110252900f, 1.836029737391738700f, + 1.835877630167659800f, + 1.835725455443608200f, 1.835573213225179400f, 1.835420903517970500f, + 1.835268526327581900f, + 1.835116081659615700f, 1.834963569519677100f, 1.834810989913373500f, + 1.834658342846314800f, + 1.834505628324113200f, 1.834352846352383700f, 1.834199996936744000f, + 1.834047080082813300f, + 1.833894095796214400f, 1.833741044082571900f, 1.833587924947513100f, + 1.833434738396668000f, + 1.833281484435668400f, 1.833128163070149300f, 1.832974774305747600f, + 1.832821318148103500f, + 1.832667794602858400f, 1.832514203675657600f, 1.832360545372147900f, + 1.832206819697979000f, + 1.832053026658802700f, 1.831899166260273700f, 1.831745238508049300f, + 1.831591243407788300f, + 1.831437180965153100f, 1.831283051185808300f, 1.831128854075420500f, + 1.830974589639659000f, + 1.830820257884196100f, 1.830665858814705600f, 1.830511392436864800f, + 1.830356858756352800f, + 1.830202257778851300f, 1.830047589510044500f, 1.829892853955619200f, + 1.829738051121264600f, + 1.829583181012672400f, 1.829428243635536500f, 1.829273238995553700f, + 1.829118167098423100f, + 1.828963027949846100f, 1.828807821555527000f, 1.828652547921171900f, + 1.828497207052490100f, + 1.828341798955192900f, 1.828186323634994200f, 1.828030781097610400f, + 1.827875171348760400f, + 1.827719494394165500f, 1.827563750239549400f, 1.827407938890638600f, + 1.827252060353161500f, + 1.827096114632849700f, 1.826940101735436500f, 1.826784021666658400f, + 1.826627874432253700f, + 1.826471660037963800f, 1.826315378489531800f, 1.826159029792704400f, + 1.826002613953229500f, + 1.825846130976858100f, 1.825689580869344100f, 1.825532963636443000f, + 1.825376279283913200f, + 1.825219527817515800f, 1.825062709243013800f, 1.824905823566173000f, + 1.824748870792761900f, + 1.824591850928550800f, 1.824434763979313300f, 1.824277609950824700f, + 1.824120388848863300f, + 1.823963100679209600f, 1.823805745447646600f, 1.823648323159960100f, + 1.823490833821937600f, + 1.823333277439369600f, 1.823175654018049300f, 1.823017963563772000f, + 1.822860206082335300f, + 1.822702381579539800f, 1.822544490061187800f, 1.822386531533084900f, + 1.822228506001038800f, + 1.822070413470859600f, 1.821912253948359700f, 1.821754027439354400f, + 1.821595733949661100f, + 1.821437373485099900f, 1.821278946051493100f, 1.821120451654665700f, + 1.820961890300445400f, + 1.820803261994661500f, 1.820644566743146800f, 1.820485804551735800f, + 1.820326975426265600f, + 1.820168079372576300f, 1.820009116396509800f, 1.819850086503910700f, + 1.819690989700625900f, + 1.819531825992505500f, 1.819372595385401000f, 1.819213297885166900f, + 1.819053933497660300f, + 1.818894502228740600f, 1.818735004084269600f, 1.818575439070111200f, + 1.818415807192132600f, + 1.818256108456203000f, 1.818096342868193800f, 1.817936510433979300f, + 1.817776611159436000f, + 1.817616645050443000f, 1.817456612112881900f, 1.817296512352636300f, + 1.817136345775592900f, + 1.816976112387640700f, 1.816815812194670700f, 1.816655445202576700f, + 1.816495011417255300f, + 1.816334510844604700f, 1.816173943490526400f, 1.816013309360923900f, + 1.815852608461703300f, + 1.815691840798773000f, 1.815531006378043900f, 1.815370105205429600f, + 1.815209137286846200f, + 1.815048102628211500f, 1.814887001235446600f, 1.814725833114474700f, + 1.814564598271221300f, + 1.814403296711615000f, 1.814241928441585800f, 1.814080493467067300f, + 1.813918991793994900f, + 1.813757423428306000f, 1.813595788375941700f, 1.813434086642844400f, + 1.813272318234959700f, + 1.813110483158235400f, 1.812948581418621500f, 1.812786613022070700f, + 1.812624577974538000f, + 1.812462476281981200f, 1.812300307950360300f, 1.812138072985637800f, + 1.811975771393778300f, + 1.811813403180749300f, 1.811650968352521000f, 1.811488466915065000f, + 1.811325898874356800f, + 1.811163264236372900f, 1.811000563007093100f, 1.810837795192499400f, + 1.810674960798576600f, + 1.810512059831311400f, 1.810349092296693400f, 1.810186058200714100f, + 1.810022957549368000f, + 1.809859790348652200f, 1.809696556604565300f, 1.809533256323109200f, + 1.809369889510288100f, + 1.809206456172108200f, 1.809042956314578900f, 1.808879389943711200f, + 1.808715757065519200f, + 1.808552057686019200f, 1.808388291811230000f, 1.808224459447172800f, + 1.808060560599871200f, + 1.807896595275351200f, 1.807732563479641300f, 1.807568465218772900f, + 1.807404300498778800f, + 1.807240069325695400f, 1.807075771705560800f, 1.806911407644415700f, + 1.806746977148303300f, + 1.806582480223269500f, 1.806417916875362000f, 1.806253287110631600f, + 1.806088590935131000f, + 1.805923828354915900f, 1.805758999376044100f, 1.805594104004575800f, + 1.805429142246573600f, + 1.805264114108102900f, 1.805099019595231200f, 1.804933858714028700f, + 1.804768631470567500f, + 1.804603337870923000f, 1.804437977921172300f, 1.804272551627395400f, + 1.804107058995674500f, + 1.803941500032094200f, 1.803775874742741500f, 1.803610183133706400f, + 1.803444425211080400f, + 1.803278600980958300f, 1.803112710449436900f, 1.802946753622615400f, + 1.802780730506595700f, + 1.802614641107481900f, 1.802448485431380900f, 1.802282263484401300f, + 1.802115975272655000f, + 1.801949620802255600f, 1.801783200079319900f, 1.801616713109966300f, + 1.801450159900316300f, + 1.801283540456493700f, 1.801116854784624400f, 1.800950102890836800f, + 1.800783284781262200f, + 1.800616400462033800f, 1.800449449939287800f, 1.800282433219162000f, + 1.800115350307797600f, + 1.799948201211337500f, 1.799780985935927300f, 1.799613704487715200f, + 1.799446356872851400f, + 1.799278943097489100f, 1.799111463167783400f, 1.798943917089892000f, + 1.798776304869975200f, + 1.798608626514195800f, 1.798440882028718500f, 1.798273071419711000f, + 1.798105194693343500f, + 1.797937251855787700f, 1.797769242913218800f, 1.797601167871813800f, + 1.797433026737752700f, + 1.797264819517217200f, 1.797096546216391900f, 1.796928206841463800f, + 1.796759801398622100f, + 1.796591329894058800f, 1.796422792333968000f, 1.796254188724546500f, + 1.796085519071992900f, + 1.795916783382509200f, 1.795747981662299200f, 1.795579113917569200f, + 1.795410180154527900f, + 1.795241180379386800f, 1.795072114598359200f, 1.794902982817661500f, + 1.794733785043511900f, + 1.794564521282131300f, 1.794395191539743400f, 1.794225795822573600f, + 1.794056334136850300f, + 1.793886806488804100f, 1.793717212884667900f, 1.793547553330677300f, + 1.793377827833070100f, + 1.793208036398086900f, 1.793038179031970000f, 1.792868255740965000f, + 1.792698266531319400f, + 1.792528211409282900f, 1.792358090381108300f, 1.792187903453050100f, + 1.792017650631366100f, + 1.791847331922315600f, 1.791676947332161000f, 1.791506496867166600f, + 1.791335980533599300f, + 1.791165398337728900f, 1.790994750285827000f, 1.790824036384167900f, + 1.790653256639028100f, + 1.790482411056686800f, 1.790311499643425500f, 1.790140522405528200f, + 1.789969479349281100f, + 1.789798370480973000f, 1.789627195806895200f, 1.789455955333341100f, + 1.789284649066606800f, + 1.789113277012990900f, 1.788941839178794100f, 1.788770335570319700f, + 1.788598766193873600f, + 1.788427131055763600f, 1.788255430162300400f, 1.788083663519796800f, + 1.787911831134568300f, + 1.787739933012932900f, 1.787567969161210300f, 1.787395939585723500f, + 1.787223844292797500f, + 1.787051683288759500f, 1.786879456579939700f, 1.786707164172670200f, + 1.786534806073285700f, + 1.786362382288123400f, 1.786189892823522700f, 1.786017337685825700f, + 1.785844716881376700f, + 1.785672030416522300f, 1.785499278297612000f, 1.785326460530997300f, + 1.785153577123032000f, + 1.784980628080072900f, 1.784807613408478300f, 1.784634533114609800f, + 1.784461387204831400f, + 1.784288175685508700f, 1.784114898563010200f, 1.783941555843707100f, + 1.783768147533972200f, + 1.783594673640181800f, 1.783421134168713800f, 1.783247529125948900f, + 1.783073858518269700f, + 1.782900122352062000f, 1.782726320633713200f, 1.782552453369613800f, + 1.782378520566156200f, + 1.782204522229735600f, 1.782030458366749200f, 1.781856328983596900f, + 1.781682134086680900f, + 1.781507873682406200f, 1.781333547777179200f, 1.781159156377410100f, + 1.780984699489510200f, + 1.780810177119894100f, 1.780635589274978600f, 1.780460935961182300f, + 1.780286217184927000f, + 1.780111432952636600f, 1.779936583270737400f, 1.779761668145658300f, + 1.779586687583830200f, + 1.779411641591686500f, 1.779236530175663600f, 1.779061353342199500f, + 1.778886111097735000f, + 1.778710803448713400f, 1.778535430401580100f, 1.778359991962783000f, + 1.778184488138772900f, + 1.778008918936002000f, 1.777833284360925900f, 1.777657584420002000f, + 1.777481819119690200f, + 1.777305988466453000f, 1.777130092466755200f, 1.776954131127064200f, + 1.776778104453849100f, + 1.776602012453582400f, 1.776425855132738100f, 1.776249632497793200f, + 1.776073344555227000f, + 1.775896991311520800f, 1.775720572773158900f, 1.775544088946627600f, + 1.775367539838415700f, + 1.775190925455014400f, 1.775014245802917200f, 1.774837500888620400f, + 1.774660690718622000f, + 1.774483815299423100f, 1.774306874637527000f, 1.774129868739439100f, + 1.773952797611667100f, + 1.773775661260722100f, 1.773598459693116500f, 1.773421192915365400f, + 1.773243860933986400f, + 1.773066463755499800f, 1.772889001386427800f, 1.772711473833295200f, + 1.772533881102629000f, + 1.772356223200959100f, 1.772178500134817100f, 1.772000711910737700f, + 1.771822858535257600f, + 1.771644940014915700f, 1.771466956356254000f, 1.771288907565816000f, + 1.771110793650148500f, + 1.770932614615799800f, 1.770754370469321400f, 1.770576061217266500f, + 1.770397686866191300f, + 1.770219247422653700f, 1.770040742893215000f, 1.769862173284438000f, + 1.769683538602888000f, + 1.769504838855133100f, 1.769326074047743700f, 1.769147244187292200f, + 1.768968349280353800f, + 1.768789389333506000f, 1.768610364353328600f, 1.768431274346403900f, + 1.768252119319316400f, + 1.768072899278653200f, 1.767893614231003800f, 1.767714264182959500f, + 1.767534849141115100f, + 1.767355369112067100f, 1.767175824102414000f, 1.766996214118757800f, + 1.766816539167701800f, + 1.766636799255852300f, 1.766456994389817600f, 1.766277124576209000f, + 1.766097189821639300f, + 1.765917190132724600f, 1.765737125516083000f, 1.765556995978334800f, + 1.765376801526102700f, + 1.765196542166012100f, 1.765016217904690900f, 1.764835828748768400f, + 1.764655374704877700f, + 1.764474855779653200f, 1.764294271979732100f, 1.764113623311754000f, + 1.763932909782361100f, + 1.763752131398197200f, 1.763571288165909400f, 1.763390380092146400f, + 1.763209407183560200f, + 1.763028369446804500f, 1.762847266888535100f, 1.762666099515411100f, + 1.762484867334093400f, + 1.762303570351245300f, 1.762122208573532600f, 1.761940782007623600f, + 1.761759290660188400f, + 1.761577734537900500f, 1.761396113647435000f, 1.761214427995469100f, + 1.761032677588683800f, + 1.760850862433760700f, 1.760668982537384900f, 1.760487037906243600f, + 1.760305028547026500f, + 1.760122954466425600f, 1.759940815671135100f, 1.759758612167851700f, + 1.759576343963274600f, + 1.759394011064105100f, 1.759211613477047200f, 1.759029151208807400f, + 1.758846624266093800f, + 1.758664032655617500f, 1.758481376384092500f, 1.758298655458233600f, + 1.758115869884759700f, + 1.757933019670390800f, 1.757750104821850000f, 1.757567125345862700f, + 1.757384081249156100f, + 1.757200972538460700f, 1.757017799220508500f, 1.756834561302034400f, + 1.756651258789775800f, + 1.756467891690471700f, 1.756284460010864200f, 1.756100963757697900f, + 1.755917402937718900f, + 1.755733777557676500f, 1.755550087624322000f, 1.755366333144409200f, + 1.755182514124693900f, + 1.754998630571935200f, 1.754814682492893600f, 1.754630669894332600f, + 1.754446592783017500f, + 1.754262451165716300f, 1.754078245049199600f, 1.753893974440240000f, + 1.753709639345612600f, + 1.753525239772095100f, 1.753340775726466700f, 1.753156247215510400f, + 1.752971654246010300f, + 1.752786996824753600f, 1.752602274958529500f, 1.752417488654129700f, + 1.752232637918348200f, + 1.752047722757981600f, 1.751862743179828600f, 1.751677699190690400f, + 1.751492590797370600f, + 1.751307418006674800f, 1.751122180825411800f, 1.750936879260391700f, + 1.750751513318427700f, + 1.750566083006335600f, 1.750380588330932500f, 1.750195029299038900f, + 1.750009405917477100f, + 1.749823718193071800f, 1.749637966132650900f, 1.749452149743043100f, + 1.749266269031080700f, + 1.749080324003598100f, 1.748894314667431800f, 1.748708241029421000f, + 1.748522103096407300f, + 1.748335900875233900f, 1.748149634372747200f, 1.747963303595795500f, + 1.747776908551230000f, + 1.747590449245904000f, 1.747403925686672500f, 1.747217337880393900f, + 1.747030685833928200f, + 1.746843969554138200f, 1.746657189047889200f, 1.746470344322048200f, + 1.746283435383485100f, + 1.746096462239072000f, 1.745909424895683200f, 1.745722323360195900f, + 1.745535157639489100f, + 1.745347927740444200f, 1.745160633669945200f, 1.744973275434878300f, + 1.744785853042132300f, + 1.744598366498598200f, 1.744410815811169300f, 1.744223200986741100f, + 1.744035522032211900f, + 1.743847778954482000f, 1.743659971760454200f, 1.743472100457033700f, + 1.743284165051127700f, + 1.743096165549646400f, 1.742908101959502100f, 1.742719974287608900f, + 1.742531782540884100f, + 1.742343526726246800f, 1.742155206850618800f, 1.741966822920923800f, + 1.741778374944088000f, + 1.741589862927040800f, 1.741401286876712800f, 1.741212646800037300f, + 1.741023942703950200f, + 1.740835174595389600f, 1.740646342481295900f, 1.740457446368612000f, + 1.740268486264283200f, + 1.740079462175256900f, 1.739890374108482600f, 1.739701222070913200f, + 1.739512006069502800f, + 1.739322726111208500f, 1.739133382202989500f, 1.738943974351807600f, + 1.738754502564626700f, + 1.738564966848413100f, 1.738375367210135400f, 1.738185703656765200f, + 1.737995976195275000f, + 1.737806184832640900f, 1.737616329575841300f, 1.737426410431856200f, + 1.737236427407668800f, + 1.737046380510263800f, 1.736856269746629000f, 1.736666095123754000f, + 1.736475856648631400f, + 1.736285554328254900f, 1.736095188169622500f, 1.735904758179732400f, + 1.735714264365586700f, + 1.735523706734189100f, 1.735333085292545900f, 1.735142400047666100f, + 1.734951651006560100f, + 1.734760838176241400f, 1.734569961563725600f, 1.734379021176030600f, + 1.734188017020177100f, + 1.733996949103187500f, 1.733805817432086900f, 1.733614622013902600f, + 1.733423362855664100f, + 1.733232039964403900f, 1.733040653347156300f, 1.732849203010957900f, + 1.732657688962847600f, + 1.732466111209867200f, 1.732274469759060200f, 1.732082764617472800f, + 1.731890995792153600f, + 1.731699163290153100f, 1.731507267118524500f, 1.731315307284323700f, + 1.731123283794607800f, + 1.730931196656437600f, 1.730739045876875200f, 1.730546831462985500f, + 1.730354553421835600f, + 1.730162211760495300f, 1.729969806486036500f, 1.729777337605533000f, + 1.729584805126061400f, + 1.729392209054700900f, 1.729199549398532400f, 1.729006826164639400f, + 1.728814039360108100f, + 1.728621188992026400f, 1.728428275067485100f, 1.728235297593577100f, + 1.728042256577397200f, + 1.727849152026043500f, 1.727655983946615700f, 1.727462752346216000f, + 1.727269457231948900f, + 1.727076098610921500f, 1.726882676490243000f, 1.726689190877025000f, + 1.726495641778381200f, + 1.726302029201427900f, 1.726108353153283900f, 1.725914613641069900f, + 1.725720810671909300f, + 1.725526944252927700f, 1.725333014391252900f, 1.725139021094015200f, + 1.724944964368347000f, + 1.724750844221383500f, 1.724556660660261800f, 1.724362413692121400f, + 1.724168103324104300f, + 1.723973729563354600f, 1.723779292417019200f, 1.723584791892246700f, + 1.723390227996188600f, + 1.723195600735998100f, 1.723000910118831300f, 1.722806156151846400f, + 1.722611338842204000f, + 1.722416458197066900f, 1.722221514223600100f, 1.722026506928971500f, + 1.721831436320350800f, + 1.721636302404910200f, 1.721441105189824000f, 1.721245844682269600f, + 1.721050520889425600f, + 1.720855133818473900f, 1.720659683476597900f, 1.720464169870984200f, + 1.720268593008821100f, + 1.720072952897299100f, 1.719877249543611900f, 1.719681482954954500f, + 1.719485653138524800f, + 1.719289760101522900f, 1.719093803851151400f, 1.718897784394614900f, + 1.718701701739120400f, + 1.718505555891877400f, 1.718309346860097600f, 1.718113074650995200f, + 1.717916739271786500f, + 1.717720340729689700f, 1.717523879031926500f, 1.717327354185719900f, + 1.717130766198295700f, + 1.716934115076881800f, 1.716737400828708400f, 1.716540623461008100f, + 1.716343782981016200f, + 1.716146879395969500f, 1.715949912713108100f, 1.715752882939673300f, + 1.715555790082909900f, + 1.715358634150064000f, 1.715161415148384500f, 1.714964133085122900f, + 1.714766787967532600f, + 1.714569379802868900f, 1.714371908598390800f, 1.714174374361358000f, + 1.713976777099033700f, + 1.713779116818682900f, 1.713581393527573000f, 1.713383607232973600f, + 1.713185757942156800f, + 1.712987845662396800f, 1.712789870400970700f, 1.712591832165157200f, + 1.712393730962237500f, + 1.712195566799495500f, 1.711997339684216700f, 1.711799049623689900f, + 1.711600696625205300f, + 1.711402280696055800f, 1.711203801843536700f, 1.711005260074945200f, + 1.710806655397581600f, + 1.710607987818747700f, 1.710409257345748100f, 1.710210463985889500f, + 1.710011607746480600f, + 1.709812688634833300f, 1.709613706658261100f, 1.709414661824080000f, + 1.709215554139608400f, + 1.709016383612166600f, 1.708817150249077900f, 1.708617854057667300f, + 1.708418495045262300f, + 1.708219073219193300f, 1.708019588586791700f, 1.707820041155392500f, + 1.707620430932332400f, + 1.707420757924950300f, 1.707221022140587900f, 1.707021223586588700f, + 1.706821362270298600f, + 1.706621438199066300f, 1.706421451380242000f, 1.706221401821179200f, + 1.706021289529232800f, + 1.705821114511760300f, 1.705620876776121600f, 1.705420576329679000f, + 1.705220213179796900f, + 1.705019787333842200f, 1.704819298799183700f, 1.704618747583193100f, + 1.704418133693243800f, + 1.704217457136711900f, 1.704016717920976000f, 1.703815916053416300f, + 1.703615051541415900f, + 1.703414124392360000f, 1.703213134613636100f, 1.703012082212634000f, + 1.702810967196746000f, + 1.702609789573366300f, 1.702408549349891500f, 1.702207246533721000f, + 1.702005881132255800f, + 1.701804453152900000f, 1.701602962603059100f, 1.701401409490141300f, + 1.701199793821557300f, + 1.700998115604720000f, 1.700796374847044300f, 1.700594571555948100f, + 1.700392705738850400f, + 1.700190777403173700f, 1.699988786556342300f, 1.699786733205783000f, + 1.699584617358924400f, + 1.699382439023197700f, 1.699180198206036600f, 1.698977894914877100f, + 1.698775529157156700f, + 1.698573100940316400f, 1.698370610271798800f, 1.698168057159048700f, + 1.697965441609513300f, + 1.697762763630642700f, 1.697560023229888200f, 1.697357220414704500f, + 1.697154355192547900f, + 1.696951427570877000f, 1.696748437557152900f, 1.696545385158839200f, + 1.696342270383401200f, + 1.696139093238307400f, 1.695935853731027600f, 1.695732551869034300f, + 1.695529187659802400f, + 1.695325761110809200f, 1.695122272229534000f, 1.694918721023458600f, + 1.694715107500066800f, + 1.694511431666845000f, 1.694307693531282000f, 1.694103893100868100f, + 1.693900030383096900f, + 1.693696105385463800f, 1.693492118115466500f, 1.693288068580604900f, + 1.693083956788381500f, + 1.692879782746300700f, 1.692675546461869900f, 1.692471247942597600f, + 1.692266887195995600f, + 1.692062464229577600f, 1.691857979050859900f, 1.691653431667360600f, + 1.691448822086600400f, + 1.691244150316102000f, 1.691039416363390800f, 1.690834620235994300f, + 1.690629761941442100f, + 1.690424841487266700f, 1.690219858881001800f, 1.690014814130184300f, + 1.689809707242353200f, + 1.689604538225049700f, 1.689399307085817300f, 1.689194013832201500f, + 1.688988658471750600f, + 1.688783241012014700f, 1.688577761460546800f, 1.688372219824901400f, + 1.688166616112636100f, + 1.687960950331309800f, 1.687755222488484600f, 1.687549432591724400f, + 1.687343580648595700f, + 1.687137666666667100f, 1.686931690653509000f, 1.686725652616694900f, + 1.686519552563800400f, + 1.686313390502403000f, 1.686107166440082600f, 1.685900880384421800f, + 1.685694532343004600f, + 1.685488122323418400f, 1.685281650333251900f, 1.685075116380096800f, + 1.684868520471546600f, + 1.684661862615197000f, 1.684455142818646700f, 1.684248361089495800f, + 1.684041517435347400f, + 1.683834611863806100f, 1.683627644382479800f, 1.683420614998977900f, + 1.683213523720911800f, + 1.683006370555896400f, 1.682799155511547600f, 1.682591878595484300f, + 1.682384539815327400f, + 1.682177139178700400f, 1.681969676693228600f, 1.681762152366539600f, + 1.681554566206263900f, + 1.681346918220033800f, 1.681139208415483700f, 1.680931436800250600f, + 1.680723603381973500f, + 1.680515708168294200f, 1.680307751166856300f, 1.680099732385305300f, + 1.679891651831290100f, + 1.679683509512460900f, 1.679475305436470600f, 1.679267039610974300f, + 1.679058712043629300f, + 1.678850322742095200f, 1.678641871714033900f, 1.678433358967109400f, + 1.678224784508988400f, + 1.678016148347339300f, 1.677807450489833300f, 1.677598690944143400f, + 1.677389869717945000f, + 1.677180986818916300f, 1.676972042254736900f, 1.676763036033089600f, + 1.676553968161658600f, + 1.676344838648130600f, 1.676135647500194700f, 1.675926394725542700f, + 1.675717080331867900f, + 1.675507704326866200f, 1.675298266718235900f, 1.675088767513677200f, + 1.674879206720892900f, + 1.674669584347587800f, 1.674459900401469700f, 1.674250154890247300f, + 1.674040347821632800f, + 1.673830479203340000f, 1.673620549043085500f, 1.673410557348587600f, + 1.673200504127567000f, + 1.672990389387746700f, 1.672780213136852300f, 1.672569975382611300f, + 1.672359676132753500f, + 1.672149315395010900f, 1.671938893177118000f, 1.671728409486811500f, + 1.671517864331830000f, + 1.671307257719914800f, 1.671096589658809500f, 1.670885860156259300f, + 1.670675069220012500f, + 1.670464216857819200f, 1.670253303077431800f, 1.670042327886605200f, + 1.669831291293095900f, + 1.669620193304663500f, 1.669409033929069500f, 1.669197813174077200f, + 1.668986531047453000f, + 1.668775187556965000f, 1.668563782710383600f, 1.668352316515481700f, + 1.668140788980034400f, + 1.667929200111818400f, 1.667717549918614100f, 1.667505838408202700f, + 1.667294065588368100f, + 1.667082231466896900f, 1.666870336051577800f, 1.666658379350201000f, + 1.666446361370560000f, + 1.666234282120450100f, 1.666022141607668600f, 1.665809939840015500f, + 1.665597676825292700f, + 1.665385352571304500f, 1.665172967085857700f, 1.664960520376761000f, + 1.664748012451825200f, + 1.664535443318863900f, 1.664322812985692600f, 1.664110121460129000f, + 1.663897368749993400f, + 1.663684554863107800f, 1.663471679807296800f, 1.663258743590387400f, + 1.663045746220208600f, + 1.662832687704591800f, 1.662619568051370500f, 1.662406387268380100f, + 1.662193145363459100f, + 1.661979842344447600f, 1.661766478219188300f, 1.661553052995526000f, + 1.661339566681307600f, + 1.661126019284382200f, 1.660912410812601900f, 1.660698741273819700f, + 1.660485010675892400f, + 1.660271219026677700f, 1.660057366334036300f, 1.659843452605831200f, + 1.659629477849926800f, + 1.659415442074190900f, 1.659201345286492900f, 1.658987187494704200f, + 1.658772968706699000f, + 1.658558688930353400f, 1.658344348173546300f, 1.658129946444157700f, + 1.657915483750071100f, + 1.657700960099171200f, 1.657486375499345900f, 1.657271729958484500f, + 1.657057023484479000f, + 1.656842256085223800f, 1.656627427768615000f, 1.656412538542551200f, + 1.656197588414933600f, + 1.655982577393664700f, 1.655767505486650500f, 1.655552372701798200f, + 1.655337179047017700f, + 1.655121924530220900f, 1.654906609159322500f, 1.654691232942238500f, + 1.654475795886888300f, + 1.654260298001192200f, 1.654044739293073900f, 1.653829119770458900f, + 1.653613439441274500f, + 1.653397698313451300f, 1.653181896394921000f, 1.652966033693617800f, + 1.652750110217479100f, + 1.652534125974443000f, 1.652318080972451400f, 1.652101975219447200f, + 1.651885808723375900f, + 1.651669581492185300f, 1.651453293533826000f, 1.651236944856249600f, + 1.651020535467411200f, + 1.650804065375267400f, 1.650587534587776700f, 1.650370943112901000f, + 1.650154290958603300f, + 1.649937578132849400f, 1.649720804643607400f, 1.649503970498847200f, + 1.649287075706541200f, + 1.649070120274664000f, 1.648853104211192700f, 1.648636027524106100f, + 1.648418890221385400f, + 1.648201692311014300f, 1.647984433800978600f, 1.647767114699266100f, + 1.647549735013867000f, + 1.647332294752774200f, 1.647114793923981600f, 1.646897232535486500f, + 1.646679610595287900f, + 1.646461928111387300f, 1.646244185091788400f, 1.646026381544496400f, + 1.645808517477519700f, + 1.645590592898868600f, 1.645372607816555400f, 1.645154562238594800f, + 1.644936456173004000f, + 1.644718289627801600f, 1.644500062611009300f, 1.644281775130650900f, + 1.644063427194751600f, + 1.643845018811340300f, 1.643626549988446200f, 1.643408020734102600f, + 1.643189431056343700f, + 1.642970780963206800f, 1.642752070462730800f, 1.642533299562957100f, + 1.642314468271929300f, + 1.642095576597693200f, 1.641876624548297000f, 1.641657612131790500f, + 1.641438539356226500f, + 1.641219406229659700f, 1.641000212760146800f, 1.640780958955747200f, + 1.640561644824521700f, + 1.640342270374534500f, 1.640122835613851100f, 1.639903340550539200f, + 1.639683785192669600f, + 1.639464169548314100f, 1.639244493625547900f, 1.639024757432447500f, + 1.638804960977092100f, + 1.638585104267562800f, 1.638365187311943400f, 1.638145210118319400f, + 1.637925172694778800f, + 1.637705075049411800f, 1.637484917190310800f, 1.637264699125570200f, + 1.637044420863286600f, + 1.636824082411559600f, 1.636603683778490100f, 1.636383224972181500f, + 1.636162706000739300f, + 1.635942126872271800f, 1.635721487594888400f, 1.635500788176702100f, + 1.635280028625826900f, + 1.635059208950379700f, 1.634838329158479200f, 1.634617389258246700f, + 1.634396389257805700f, + 1.634175329165281400f, 1.633954208988801700f, 1.633733028736496400f, + 1.633511788416498000f, + 1.633290488036940500f, 1.633069127605960800f, 1.632847707131697600f, + 1.632626226622291700f, + 1.632404686085886300f, 1.632183085530627200f, 1.631961424964661700f, + 1.631739704396139900f, + 1.631517923833213400f, 1.631296083284036900f, 1.631074182756766300f, + 1.630852222259560700f, + 1.630630201800580900f, 1.630408121387990000f, 1.630185981029953000f, + 1.629963780734637400f, + 1.629741520510213000f, 1.629519200364851800f, 1.629296820306727700f, + 1.629074380344017100f, + 1.628851880484898200f, 1.628629320737551700f, 1.628406701110161100f, + 1.628184021610910700f, + 1.627961282247988300f, 1.627738483029583100f, 1.627515623963887000f, + 1.627292705059093700f, + 1.627069726323399500f, 1.626846687765002700f, 1.626623589392103500f, + 1.626400431212904800f, + 1.626177213235611400f, 1.625953935468430500f, 1.625730597919571300f, + 1.625507200597245500f, + 1.625283743509666300f, 1.625060226665050000f, 1.624836650071614500f, + 1.624613013737580000f, + 1.624389317671169500f, 1.624165561880607000f, 1.623941746374119500f, + 1.623717871159936300f, + 1.623493936246288300f, 1.623269941641409400f, 1.623045887353534900f, + 1.622821773390902700f, + 1.622597599761753000f, 1.622373366474327800f, 1.622149073536871800f, + 1.621924720957631300f, + 1.621700308744855200f, 1.621475836906794500f, 1.621251305451702400f, + 1.621026714387834300f, + 1.620802063723447700f, 1.620577353466802700f, 1.620352583626160500f, + 1.620127754209786100f, + 1.619902865225945300f, 1.619677916682906700f, 1.619452908588941300f, + 1.619227840952321800f, + 1.619002713781323200f, 1.618777527084222800f, 1.618552280869300300f, + 1.618326975144837000f, + 1.618101609919117200f, 1.617876185200426600f, 1.617650700997053500f, + 1.617425157317288200f, + 1.617199554169423500f, 1.616973891561754200f, 1.616748169502577200f, + 1.616522388000191500f, + 1.616296547062898500f, 1.616070646699001800f, 1.615844686916807300f, + 1.615618667724622700f, + 1.615392589130757900f, 1.615166451143525300f, 1.614940253771239400f, + 1.614713997022216900f, + 1.614487680904776600f, 1.614261305427239200f, 1.614034870597928400f, + 1.613808376425168900f, + 1.613581822917288900f, 1.613355210082617800f, 1.613128537929487500f, + 1.612901806466232200f, + 1.612675015701188000f, 1.612448165642693400f, 1.612221256299089200f, + 1.611994287678718100f, + 1.611767259789925100f, 1.611540172641057200f, 1.611313026240463800f, + 1.611085820596496600f, + 1.610858555717509200f, 1.610631231611857800f, 1.610403848287899700f, + 1.610176405753995800f, + 1.609948904018508200f, 1.609721343089801600f, 1.609493722976242900f, + 1.609266043686200700f, + 1.609038305228046400f, 1.608810507610153100f, 1.608582650840896200f, + 1.608354734928653800f, + 1.608126759881805400f, 1.607898725708732900f, 1.607670632417820500f, + 1.607442480017454700f, + 1.607214268516024000f, 1.606985997921919000f, 1.606757668243532500f, + 1.606529279489259600f, + 1.606300831667497600f, 1.606072324786645500f, 1.605843758855105300f, + 1.605615133881280700f, + 1.605386449873577300f, 1.605157706840403300f, 1.604928904790168700f, + 1.604700043731286200f, + 1.604471123672170500f, 1.604242144621237800f, 1.604013106586907400f, + 1.603784009577600100f, + 1.603554853601739700f, 1.603325638667751000f, 1.603096364784061900f, + 1.602867031959102100f, + 1.602637640201303400f, 1.602408189519099800f, 1.602178679920927900f, + 1.601949111415226000f, + 1.601719484010434300f, 1.601489797714996000f, 1.601260052537355700f, + 1.601030248485960900f, + 1.600800385569260300f, 1.600570463795705700f, 1.600340483173750400f, + 1.600110443711850300f, + 1.599880345418463100f, 1.599650188302049100f, 1.599419972371070500f, + 1.599189697633991400f, + 1.598959364099278700f, 1.598728971775401000f, 1.598498520670828900f, + 1.598268010794035900f, + 1.598037442153496900f, 1.597806814757689200f, 1.597576128615092200f, + 1.597345383734188000f, + 1.597114580123460100f, 1.596883717791394800f, 1.596652796746479600f, + 1.596421816997205500f, + 1.596190778552064800f, 1.595959681419551800f, 1.595728525608163700f, + 1.595497311126399300f, + 1.595266037982759500f, 1.595034706185747500f, 1.594803315743869000f, + 1.594571866665631700f, + 1.594340358959544800f, 1.594108792634120600f, 1.593877167697873100f, + 1.593645484159318200f, + 1.593413742026974500f, 1.593181941309362400f, 1.592950082015004700f, + 1.592718164152426000f, + 1.592486187730153300f, 1.592254152756715600f, 1.592022059240644400f, + 1.591789907190473100f, + 1.591557696614737100f, 1.591325427521974100f, 1.591093099920724200f, + 1.590860713819529400f, + 1.590628269226933600f, 1.590395766151483400f, 1.590163204601727100f, + 1.589930584586215500f, + 1.589697906113501000f, 1.589465169192139100f, 1.589232373830686400f, + 1.588999520037702300f, + 1.588766607821748200f, 1.588533637191387400f, 1.588300608155185600f, + 1.588067520721711000f, + 1.587834374899533400f, 1.587601170697224600f, 1.587367908123358900f, + 1.587134587186513000f, + 1.586901207895265300f, 1.586667770258196600f, 1.586434274283889500f, + 1.586200719980929200f, + 1.585967107357902700f, 1.585733436423399000f, 1.585499707186010200f, + 1.585265919654329300f, + 1.585032073836952100f, 1.584798169742476400f, 1.584564207379502500f, + 1.584330186756632200f, + 1.584096107882470000f, 1.583861970765622100f, 1.583627775414697000f, + 1.583393521838305700f, + 1.583159210045060900f, 1.582924840043577400f, 1.582690411842472700f, + 1.582455925450365600f, + 1.582221380875877800f, 1.581986778127632700f, 1.581752117214255900f, + 1.581517398144375800f, + 1.581282620926621300f, 1.581047785569625400f, 1.580812892082021900f, + 1.580577940472447200f, + 1.580342930749539800f, 1.580107862921940700f, 1.579872736998292100f, + 1.579637552987239100f, + 1.579402310897428900f, 1.579167010737510600f, 1.578931652516135700f, + 1.578696236241957200f, + 1.578460761923630800f, 1.578225229569814700f, 1.577989639189168100f, + 1.577753990790353500f, + 1.577518284382034800f, 1.577282519972878200f, 1.577046697571552000f, + 1.576810817186727000f, + 1.576574878827075700f, 1.576338882501273000f, 1.576102828217995600f, + 1.575866715985922500f, + 1.575630545813735200f, 1.575394317710116600f, 1.575158031683752300f, + 1.574921687743330300f, + 1.574685285897539800f, 1.574448826155072400f, 1.574212308524622500f, + 1.573975733014886000f, + 1.573739099634561500f, 1.573502408392348600f, 1.573265659296950300f, + 1.573028852357070800f, + 1.572791987581417100f, 1.572555064978698100f, 1.572318084557624800f, + 1.572081046326909900f, + 1.571843950295269000f, 1.571606796471419100f, 1.571369584864080100f, + 1.571132315481973200f, + 1.570894988333822400f, 1.570657603428353300f, 1.570420160774294000f, + 1.570182660380374600f, + 1.569945102255327200f, 1.569707486407886600f, 1.569469812846788500f, + 1.569232081580771900f, + 1.568994292618577400f, 1.568756445968948000f, 1.568518541640628400f, + 1.568280579642366000f, + 1.568042559982909500f, 1.567804482671010500f, 1.567566347715422500f, + 1.567328155124900800f, + 1.567089904908203200f, 1.566851597074089500f, 1.566613231631321500f, + 1.566374808588663300f, + 1.566136327954881000f, 1.565897789738742900f, 1.565659193949019400f, + 1.565420540594482800f, + 1.565181829683907700f, 1.564943061226071100f, 1.564704235229751500f, + 1.564465351703730400f, + 1.564226410656790000f, 1.563987412097716200f, 1.563748356035296000f, + 1.563509242478319000f, + 1.563270071435576500f, 1.563030842915862100f, 1.562791556927971800f, + 1.562552213480703300f, + 1.562312812582856500f, 1.562073354243233700f, 1.561833838470639200f, + 1.561594265273878800f, + 1.561354634661761300f, 1.561114946643096900f, 1.560875201226698900f, + 1.560635398421381400f, + 1.560395538235961800f, 1.560155620679258400f, 1.559915645760092900f, + 1.559675613487288200f, + 1.559435523869669500f, 1.559195376916064700f, 1.558955172635302800f, + 1.558714911036215700f, + 1.558474592127637100f, 1.558234215918402600f, 1.557993782417350400f, + 1.557753291633320500f, + 1.557512743575155000f, 1.557272138251698300f, 1.557031475671796400f, + 1.556790755844298400f, + 1.556549978778054300f, 1.556309144481917300f, 1.556068252964741600f, + 1.555827304235384500f, + 1.555586298302704900f, 1.555345235175563900f, 1.555104114862824600f, + 1.554862937373352500f, + 1.554621702716015000f, 1.554380410899681300f, 1.554139061933223200f, + 1.553897655825514600f, + 1.553656192585431100f, 1.553414672221850700f, 1.553173094743653300f, + 1.552931460159721100f, + 1.552689768478938500f, 1.552448019710191300f, 1.552206213862368500f, + 1.551964350944360100f, + 1.551722430965059000f, 1.551480453933359800f, 1.551238419858159700f, + 1.550996328748356800f, + 1.550754180612852900f, 1.550511975460550500f, 1.550269713300355100f, + 1.550027394141174000f, + 1.549785017991916400f, 1.549542584861493900f, 1.549300094758820000f, + 1.549057547692810600f, + 1.548814943672383300f, 1.548572282706457900f, 1.548329564803956300f, + 1.548086789973802700f, + 1.547843958224923000f, 1.547601069566245900f, 1.547358124006701400f, + 1.547115121555221700f, + 1.546872062220741700f, 1.546628946012197800f, 1.546385772938528600f, + 1.546142543008675300f, + 1.545899256231580300f, 1.545655912616188800f, 1.545412512171447700f, + 1.545169054906306200f, + 1.544925540829715600f, 1.544681969950629300f, 1.544438342278002600f, + 1.544194657820792800f, + 1.543950916587959700f, 1.543707118588464800f, 1.543463263831272000f, + 1.543219352325347200f, + 1.542975384079658300f, 1.542731359103175300f, 1.542487277404870100f, + 1.542243138993717000f, + 1.541998943878692300f, 1.541754692068774600f, 1.541510383572944000f, + 1.541266018400183200f, + 1.541021596559476700f, 1.540777118059811100f, 1.540532582910175500f, + 1.540287991119560600f, + 1.540043342696959100f, 1.539798637651366400f, 1.539553875991779300f, + 1.539309057727197300f, + 1.539064182866621400f, 1.538819251419055100f, 1.538574263393503800f, + 1.538329218798974800f, + 1.538084117644477900f, 1.537838959939025200f, 1.537593745691629500f, + 1.537348474911307300f, + 1.537103147607076200f, 1.536857763787956400f, 1.536612323462969800f, + 1.536366826641140800f, + 1.536121273331495300f, 1.535875663543061700f, 1.535629997284870400f, + 1.535384274565953600f, + 1.535138495395346400f, 1.534892659782085100f, 1.534646767735208000f, + 1.534400819263756400f, + 1.534154814376772700f, 1.533908753083302200f, 1.533662635392391700f, + 1.533416461313090100f, + 1.533170230854448400f, 1.532923944025520200f, 1.532677600835360600f, + 1.532431201293027000f, + 1.532184745407578500f, 1.531938233188077100f, 1.531691664643585900f, + 1.531445039783170500f, + 1.531198358615898800f, 1.530951621150840700f, 1.530704827397067800f, + 1.530457977363654000f, + 1.530211071059675200f, 1.529964108494209700f, 1.529717089676337500f, + 1.529470014615140800f, + 1.529222883319703700f, 1.528975695799112500f, 1.528728452062455600f, + 1.528481152118823700f, + 1.528233795977309400f, 1.527986383647006500f, 1.527738915137012400f, + 1.527491390456425600f, + 1.527243809614346600f, 1.526996172619878900f, 1.526748479482126700f, + 1.526500730210197200f, + 1.526252924813199500f, 1.526005063300244900f, 1.525757145680446200f, + 1.525509171962918800f, + 1.525261142156779900f, 1.525013056271149000f, 1.524764914315147200f, + 1.524516716297898300f, + 1.524268462228527900f, 1.524020152116163200f, 1.523771785969934000f, + 1.523523363798972000f, + 1.523274885612411200f, 1.523026351419387100f, 1.522777761229038100f, + 1.522529115050503600f, + 1.522280412892925900f, 1.522031654765448900f, 1.521782840677218700f, + 1.521533970637383800f, + 1.521285044655094300f, 1.521036062739502300f, 1.520787024899762100f, + 1.520537931145030400f, + 1.520288781484465700f, 1.520039575927228500f, 1.519790314482481100f, + 1.519540997159388300f, + 1.519291623967116600f, 1.519042194914835200f, 1.518792710011714500f, + 1.518543169266927600f, + 1.518293572689648900f, 1.518043920289055900f, 1.517794212074327500f, + 1.517544448054644500f, + 1.517294628239190400f, 1.517044752637150000f, 1.516794821257710500f, + 1.516544834110061600f, + 1.516294791203394200f, 1.516044692546901800f, 1.515794538149779700f, + 1.515544328021225500f, + 1.515294062170438700f, 1.515043740606620800f, 1.514793363338975600f, + 1.514542930376708600f, + 1.514292441729027300f, 1.514041897405141700f, 1.513791297414263800f, + 1.513540641765606800f, + 1.513289930468387300f, 1.513039163531823000f, 1.512788340965133500f, + 1.512537462777541200f, + 1.512286528978270300f, 1.512035539576546600f, 1.511784494581598600f, + 1.511533394002656100f, + 1.511282237848951400f, 1.511031026129719100f, 1.510779758854195400f, + 1.510528436031618900f, + 1.510277057671229400f, 1.510025623782270000f, 1.509774134373984800f, + 1.509522589455620600f, + 1.509270989036425800f, 1.509019333125651200f, 1.508767621732549400f, + 1.508515854866375100f, + 1.508264032536385000f, 1.508012154751837700f, 1.507760221521994700f, + 1.507508232856118200f, + 1.507256188763473200f, 1.507004089253327000f, 1.506751934334948000f, + 1.506499724017607900f, + 1.506247458310579400f, 1.505995137223137500f, 1.505742760764559300f, + 1.505490328944124200f, + 1.505237841771113200f, 1.504985299254809800f, 1.504732701404498900f, + 1.504480048229468000f, + 1.504227339739006500f, 1.503974575942405700f, 1.503721756848958700f, + 1.503468882467961600f, + 1.503215952808711500f, 1.502962967880507600f, 1.502709927692651900f, + 1.502456832254447600f, + 1.502203681575200700f, 1.501950475664218600f, 1.501697214530810700f, + 1.501443898184289200f, + 1.501190526633967600f, 1.500937099889161600f, 1.500683617959188900f, + 1.500430080853369500f, + 1.500176488581024900f, 1.499922841151479600f, 1.499669138574058800f, + 1.499415380858090800f, + 1.499161568012905300f, 1.498907700047834600f, 1.498653776972212600f, + 1.498399798795375000f, + 1.498145765526660300f, 1.497891677175408500f, 1.497637533750961300f, + 1.497383335262663300f, + 1.497129081719860400f, 1.496874773131900800f, 1.496620409508134800f, + 1.496365990857914600f, + 1.496111517190594300f, 1.495856988515530400f, 1.495602404842080800f, + 1.495347766179606400f, + 1.495093072537469100f, 1.494838323925033400f, 1.494583520351665500f, + 1.494328661826734200f, + 1.494073748359609600f, 1.493818779959664300f, 1.493563756636272500f, + 1.493308678398810800f, + 1.493053545256657800f, 1.492798357219194100f, 1.492543114295801900f, + 1.492287816495866200f, + 1.492032463828773200f, 1.491777056303911700f, 1.491521593930672100f, + 1.491266076718446900f, + 1.491010504676631500f, 1.490754877814621800f, 1.490499196141816600f, + 1.490243459667616600f, + 1.489987668401424800f, 1.489731822352645500f, 1.489475921530685900f, + 1.489219965944954300f, + 1.488963955604861500f, 1.488707890519820600f, 1.488451770699245900f, + 1.488195596152554800f, + 1.487939366889165600f, 1.487683082918499300f, 1.487426744249978400f, + 1.487170350893028500f, + 1.486913902857075700f, 1.486657400151549600f, 1.486400842785880100f, + 1.486144230769501000f, + 1.485887564111846500f, 1.485630842822354100f, 1.485374066910462500f, + 1.485117236385612200f, + 1.484860351257246500f, 1.484603411534810300f, 1.484346417227750700f, + 1.484089368345516300f, + 1.483832264897558400f, 1.483575106893329600f, 1.483317894342285100f, + 1.483060627253882000f, + 1.482803305637578900f, 1.482545929502837100f, 1.482288498859119400f, + 1.482031013715890700f, + 1.481773474082618300f, 1.481515879968770900f, 1.481258231383819800f, + 1.481000528337237800f, + 1.480742770838499900f, 1.480484958897083200f, 1.480227092522466500f, + 1.479969171724131200f, + 1.479711196511560100f, 1.479453166894238100f, 1.479195082881652200f, + 1.478936944483291600f, + 1.478678751708647000f, 1.478420504567211900f, 1.478162203068481100f, + 1.477903847221951400f, + 1.477645437037121900f, 1.477386972523493800f, 1.477128453690569800f, + 1.476869880547855300f, + 1.476611253104856700f, 1.476352571371083700f, 1.476093835356046700f, + 1.475835045069259000f, + 1.475576200520235500f, 1.475317301718493300f, 1.475058348673551100f, + 1.474799341394929900f, + 1.474540279892153000f, 1.474281164174744900f, 1.474021994252233000f, + 1.473762770134145800f, + 1.473503491830014300f, 1.473244159349371700f, 1.472984772701752900f, + 1.472725331896694400f, + 1.472465836943735600f, 1.472206287852416900f, 1.471946684632281500f, + 1.471687027292874400f, + 1.471427315843742100f, 1.471167550294433700f, 1.470907730654499800f, + 1.470647856933493300f, + 1.470387929140969200f, 1.470127947286484100f, 1.469867911379596900f, + 1.469607821429868500f, + 1.469347677446861500f, 1.469087479440140300f, 1.468827227419272200f, + 1.468566921393825700f, + 1.468306561373371900f, 1.468046147367482600f, 1.467785679385733300f, + 1.467525157437700200f, + 1.467264581532962100f, 1.467003951681099800f, 1.466743267891695800f, + 1.466482530174334500f, + 1.466221738538602500f, 1.465960892994088800f, 1.465699993550383400f, + 1.465439040217079400f, + 1.465178033003770700f, 1.464916971920054100f, 1.464655856975527900f, + 1.464394688179792900f, + 1.464133465542451200f, 1.463872189073107500f, 1.463610858781367900f, + 1.463349474676840700f, + 1.463088036769136600f, 1.462826545067867700f, 1.462564999582648600f, + 1.462303400323095000f, + 1.462041747298825900f, 1.461780040519460800f, 1.461518279994622200f, + 1.461256465733934400f, + 1.460994597747023600f, 1.460732676043517800f, 1.460470700633046800f, + 1.460208671525243400f, + 1.459946588729741100f, 1.459684452256176300f, 1.459422262114186800f, + 1.459160018313412400f, + 1.458897720863495500f, 1.458635369774079500f, 1.458372965054810700f, + 1.458110506715337000f, + 1.457847994765308200f, 1.457585429214375700f, 1.457322810072193800f, + 1.457060137348418000f, + 1.456797411052706200f, 1.456534631194717800f, 1.456271797784114900f, + 1.456008910830560500f, + 1.455745970343720800f, 1.455482976333263100f, 1.455219928808857200f, + 1.454956827780174100f, + 1.454693673256887600f, 1.454430465248673300f, 1.454167203765208000f, + 1.453903888816171900f, + 1.453640520411245900f, 1.453377098560113100f, 1.453113623272459100f, + 1.452850094557971000f, + 1.452586512426338000f, 1.452322876887251400f, 1.452059187950404100f, + 1.451795445625491300f, + 1.451531649922210200f, 1.451267800850259500f, 1.451003898419340500f, + 1.450739942639155800f, + 1.450475933519410400f, 1.450211871069811300f, 1.449947755300067500f, + 1.449683586219889400f, + 1.449419363838989800f, 1.449155088167083600f, 1.448890759213887100f, + 1.448626376989119400f, + 1.448361941502500900f, 1.448097452763754000f, 1.447832910782603100f, + 1.447568315568775100f, + 1.447303667131997900f, 1.447038965482002200f, 1.446774210628520200f, + 1.446509402581286400f, + 1.446244541350036700f, 1.445979626944509300f, 1.445714659374444500f, + 1.445449638649584500f, + 1.445184564779673500f, 1.444919437774456700f, 1.444654257643682900f, + 1.444389024397101600f, + 1.444123738044464900f, 1.443858398595526400f, 1.443593006060042100f, + 1.443327560447769600f, + 1.443062061768468400f, 1.442796510031900500f, 1.442530905247829200f, + 1.442265247426020200f, + 1.441999536576240800f, 1.441733772708260600f, 1.441467955831850800f, + 1.441202085956784900f, + 1.440936163092837900f, 1.440670187249787600f, 1.440404158437412500f, + 1.440138076665494100f, + 1.439871941943815300f, 1.439605754282161400f, 1.439339513690319100f, + 1.439073220178077400f, + 1.438806873755226900f, 1.438540474431560600f, 1.438274022216873500f, + 1.438007517120961900f, + 1.437740959153624500f, 1.437474348324662100f, 1.437207684643876800f, + 1.436940968121073600f, + 1.436674198766058500f, 1.436407376588640000f, 1.436140501598628400f, + 1.435873573805835900f, + 1.435606593220076600f, 1.435339559851166500f, 1.435072473708924000f, + 1.434805334803169100f, + 1.434538143143723200f, 1.434270898740410700f, 1.434003601603057300f, + 1.433736251741490700f, + 1.433468849165540500f, 1.433201393885038500f, 1.432933885909818000f, + 1.432666325249714700f, + 1.432398711914566200f, 1.432131045914211600f, 1.431863327258492400f, + 1.431595555957251700f, + 1.431327732020334800f, 1.431059855457588600f, 1.430791926278862400f, + 1.430523944494007400f, + 1.430255910112876000f, 1.429987823145323100f, 1.429719683601205800f, + 1.429451491490382900f, + 1.429183246822714800f, 1.428914949608064200f, 1.428646599856295400f, + 1.428378197577275100f, + 1.428109742780871800f, 1.427841235476955400f, 1.427572675675398600f, + 1.427304063386075200f, + 1.427035398618861500f, 1.426766681383635500f, 1.426497911690277000f, + 1.426229089548668200f, + 1.425960214968693000f, 1.425691287960236600f, 1.425422308533187200f, + 1.425153276697434000f, + 1.424884192462868800f, 1.424615055839385300f, 1.424345866836878200f, + 1.424076625465245500f, + 1.423807331734385800f, 1.423537985654200800f, 1.423268587234593400f, + 1.422999136485468600f, + 1.422729633416733200f, 1.422460078038296300f, 1.422190470360068300f, + 1.421920810391962500f, + 1.421651098143893000f, 1.421381333625776600f, 1.421111516847531700f, + 1.420841647819078600f, + 1.420571726550339700f, 1.420301753051239400f, 1.420031727331703800f, + 1.419761649401660500f, + 1.419491519271040000f, 1.419221336949774100f, 1.418951102447796800f, + 1.418680815775043500f, + 1.418410476941452100f, 1.418140085956961900f, 1.417869642831514700f, + 1.417599147575054000f, + 1.417328600197524900f, 1.417058000708874700f, 1.416787349119052600f, + 1.416516645438009600f, + 1.416245889675698900f, 1.415975081842075300f, 1.415704221947095700f, + 1.415433310000718600f, + 1.415162346012905000f, 1.414891329993617200f, 1.414620261952819600f, + 1.414349141900479000f, + 1.414077969846563500f, 1.413806745801043500f, 1.413535469773890700f, + 1.413264141775079300f, + 1.412992761814585400f, 1.412721329902386900f, 1.412449846048463600f, + 1.412178310262796900f, + 1.411906722555370500f, 1.411635082936170100f, 1.411363391415182900f, + 1.411091648002398500f, + 1.410819852707807700f, 1.410548005541404100f, 1.410276106513182400f, + 1.410004155633139500f, + 1.409732152911274500f, 1.409460098357588200f, 1.409187991982083100f, + 1.408915833794763800f, + 1.408643623805636800f, 1.408371362024710500f, 1.408099048461995300f, + 1.407826683127503000f, + 1.407554266031248100f, 1.407281797183246500f, 1.407009276593515800f, + 1.406736704272076400f, + 1.406464080228949600f, 1.406191404474159000f, 1.405918677017730100f, + 1.405645897869690400f, + 1.405373067040069300f, 1.405100184538898000f, 1.404827250376209400f, + 1.404554264562038400f, + 1.404281227106422400f, 1.404008138019399800f, 1.403734997311011600f, + 1.403461804991300100f, + 1.403188561070310100f, 1.402915265558087700f, 1.402641918464681400f, + 1.402368519800141200f, + 1.402095069574519800f, 1.401821567797870300f, 1.401548014480249000f, + 1.401274409631713600f, + 1.401000753262323900f, 1.400727045382141400f, 1.400453286001229800f, + 1.400179475129653700f, + 1.399905612777481200f, 1.399631698954780800f, 1.399357733671623900f, + 1.399083716938083600f, + 1.398809648764234100f, 1.398535529160152400f, 1.398261358135917300f, + 1.397987135701609200f, + 1.397712861867310300f, 1.397438536643105000f, 1.397164160039079200f, + 1.396889732065321300f, + 1.396615252731921100f, 1.396340722048970300f, 1.396066140026562800f, + 1.395791506674794100f, + 1.395516822003761700f, 1.395242086023564800f, 1.394967298744304900f, + 1.394692460176085300f, + 1.394417570329010700f, 1.394142629213188000f, 1.393867636838725900f, + 1.393592593215735600f, + 1.393317498354329300f, 1.393042352264621600f, 1.392767154956728400f, + 1.392491906440768600f, + 1.392216606726861800f, 1.391941255825130100f, 1.391665853745697400f, + 1.391390400498689700f, + 1.391114896094234100f, 1.390839340542460600f, 1.390563733853500200f, + 1.390288076037486500f, + 1.390012367104554600f, 1.389736607064841100f, 1.389460795928485500f, + 1.389184933705628300f, + 1.388909020406412100f, 1.388633056040981600f, 1.388357040619483200f, + 1.388080974152065200f, + 1.387804856648877600f, 1.387528688120072600f, 1.387252468575804100f, + 1.386976198026228100f, + 1.386699876481501900f, 1.386423503951785200f, 1.386147080447239600f, + 1.385870605978028100f, + 1.385594080554316100f, 1.385317504186270900f, 1.385040876884061000f, + 1.384764198657857200f, + 1.384487469517832200f, 1.384210689474160600f, 1.383933858537019100f, + 1.383656976716585600f, + 1.383380044023040400f, 1.383103060466565300f, 1.382826026057344600f, + 1.382548940805563800f, + 1.382271804721410600f, 1.381994617815074400f, 1.381717380096746800f, + 1.381440091576620700f, + 1.381162752264891500f, 1.380885362171756300f, 1.380607921307413400f, + 1.380330429682064000f, + 1.380052887305910400f, 1.379775294189157000f, 1.379497650342010400f, + 1.379219955774678700f, + 1.378942210497371600f, 1.378664414520301500f, 1.378386567853681700f, + 1.378108670507728300f, + 1.377830722492658500f, 1.377552723818691500f, 1.377274674496048700f, + 1.376996574534953300f, + 1.376718423945630000f, 1.376440222738305700f, 1.376161970923209400f, + 1.375883668510570900f, + 1.375605315510623200f, 1.375326911933600200f, 1.375048457789738400f, + 1.374769953089275400f, + 1.374491397842451100f, 1.374212792059507100f, 1.373934135750687100f, + 1.373655428926236400f, + 1.373376671596402400f, 1.373097863771434200f, 1.372819005461582500f, + 1.372540096677100200f, + 1.372261137428242300f, 1.371982127725264800f, 1.371703067578426700f, + 1.371423956997988000f, + 1.371144795994210500f, 1.370865584577358300f, 1.370586322757697500f, + 1.370307010545495500f, + 1.370027647951022100f, 1.369748234984548000f, 1.369468771656347200f, + 1.369189257976694200f, + 1.368909693955866000f, 1.368630079604142000f, 1.368350414931802000f, + 1.368070699949128800f, + 1.367790934666406600f, 1.367511119093921800f, 1.367231253241962200f, + 1.366951337120818000f, + 1.366671370740780500f, 1.366391354112143500f, 1.366111287245202400f, + 1.365831170150254300f, + 1.365551002837598600f, 1.365270785317536100f, 1.364990517600369400f, + 1.364710199696403300f, + 1.364429831615944200f, 1.364149413369300600f, 1.363868944966782900f, + 1.363588426418702600f, + 1.363307857735373900f, 1.363027238927112300f, 1.362746570004235400f, + 1.362465850977062900f, + 1.362185081855915600f, 1.361904262651116900f, 1.361623393372991300f, + 1.361342474031866000f, + 1.361061504638069400f, 1.360780485201932300f, 1.360499415733786400f, + 1.360218296243966200f, + 1.359937126742807300f, 1.359655907240648000f, 1.359374637747827700f, + 1.359093318274687800f, + 1.358811948831571500f, 1.358530529428824400f, 1.358249060076792900f, + 1.357967540785826300f, + 1.357685971566275200f, 1.357404352428492000f, 1.357122683382830900f, + 1.356840964439648200f, + 1.356559195609301700f, 1.356277376902151900f, 1.355995508328559500f, + 1.355713589898888800f, + 1.355431621623504700f, 1.355149603512774400f, 1.354867535577067200f, + 1.354585417826753800f, + 1.354303250272206500f, 1.354021032923800300f, 1.353738765791911100f, + 1.353456448886917200f, + 1.353174082219199100f, 1.352891665799137900f, 1.352609199637117500f, + 1.352326683743523300f, + 1.352044118128742600f, 1.351761502803164900f, 1.351478837777180700f, + 1.351196123061183100f, + 1.350913358665566400f, 1.350630544600727200f, 1.350347680877063800f, + 1.350064767504976400f, + 1.349781804494866600f, 1.349498791857138400f, 1.349215729602197400f, + 1.348932617740450600f, + 1.348649456282307700f, 1.348366245238179500f, 1.348082984618478800f, + 1.347799674433620500f, + 1.347516314694020800f, 1.347232905410098200f, 1.346949446592273100f, + 1.346665938250967100f, + 1.346382380396604000f, 1.346098773039609700f, 1.345815116190411300f, + 1.345531409859438200f, + 1.345247654057121700f, 1.344963848793894200f, 1.344679994080190800f, + 1.344396089926448000f, + 1.344112136343103900f, 1.343828133340598800f, 1.343544080929374800f, + 1.343259979119875600f, + 1.342975827922546600f, 1.342691627347835500f, 1.342407377406191500f, + 1.342123078108065700f, + 1.341838729463910900f, 1.341554331484181600f, 1.341269884179334700f, + 1.340985387559828100f, + 1.340700841636122400f, 1.340416246418678800f, 1.340131601917961900f, + 1.339846908144436600f, + 1.339562165108570700f, 1.339277372820833400f, 1.338992531291695500f, + 1.338707640531629800f, + 1.338422700551110900f, 1.338137711360615200f, 1.337852672970621300f, + 1.337567585391608900f, + 1.337282448634059800f, 1.336997262708457900f, 1.336712027625288600f, + 1.336426743395039000f, + 1.336141410028198500f, 1.335856027535258000f, 1.335570595926709700f, + 1.335285115213048500f, + 1.334999585404770700f, 1.334714006512374400f, 1.334428378546359500f, + 1.334142701517227600f, + 1.333856975435482300f, 1.333571200311629100f, 1.333285376156174700f, + 1.332999502979628700f, + 1.332713580792501500f, 1.332427609605305400f, 1.332141589428554900f, + 1.331855520272766200f, + 1.331569402148457400f, 1.331283235066148100f, 1.330997019036359800f, + 1.330710754069615700f, + 1.330424440176441300f, 1.330138077367363200f, 1.329851665652910500f, + 1.329565205043613800f, + 1.329278695550004700f, 1.328992137182618100f, 1.328705529951989400f, + 1.328418873868656900f, + 1.328132168943159800f, 1.327845415186039000f, 1.327558612607838500f, + 1.327271761219102500f, + 1.326984861030378000f, 1.326697912052213500f, 1.326410914295159400f, + 1.326123867769767500f, + 1.325836772486591800f, 1.325549628456188100f, 1.325262435689113600f, + 1.324975194195928000f, + 1.324687903987191900f, 1.324400565073468300f, 1.324113177465321900f, + 1.323825741173318700f, + 1.323538256208027800f, 1.323250722580018500f, 1.322963140299862500f, + 1.322675509378133900f, + 1.322387829825407700f, 1.322100101652261100f, 1.321812324869273500f, + 1.321524499487024800f, + 1.321236625516098100f, 1.320948702967077400f, 1.320660731850549000f, + 1.320372712177100700f, + 1.320084643957322400f, 1.319796527201805300f, 1.319508361921142500f, + 1.319220148125929100f, + 1.318931885826762000f, 1.318643575034239800f, 1.318355215758962900f, + 1.318066808011533200f, + 1.317778351802554800f, 1.317489847142633300f, 1.317201294042376300f, + 1.316912692512393300f, + 1.316624042563294900f, 1.316335344205694200f, 1.316046597450205800f, + 1.315757802307445900f, + 1.315468958788033000f, 1.315180066902586800f, 1.314891126661728900f, + 1.314602138076083300f, + 1.314313101156274800f, 1.314024015912930600f, 1.313734882356679900f, + 1.313445700498152800f, + 1.313156470347981900f, 1.312867191916801100f, 1.312577865215246900f, + 1.312288490253956900f, + 1.311999067043570200f, 1.311709595594728000f, 1.311420075918073900f, + 1.311130508024252400f, + 1.310840891923910100f, 1.310551227627695400f, 1.310261515146258200f, + 1.309971754490250700f, + 1.309681945670326400f, 1.309392088697140900f, 1.309102183581351200f, + 1.308812230333616500f, + 1.308522228964597500f, 1.308232179484956500f, 1.307942081905358000f, + 1.307651936236467800f, + 1.307361742488954300f, 1.307071500673486800f, 1.306781210800736200f, + 1.306490872881376200f, + 1.306200486926081700f, 1.305910052945529200f, 1.305619570950396800f, + 1.305329040951365100f, + 1.305038462959116100f, 1.304747836984333300f, 1.304457163037702200f, + 1.304166441129910300f, + 1.303875671271646400f, 1.303584853473601200f, 1.303293987746467300f, + 1.303003074100939100f, + 1.302712112547712800f, 1.302421103097485900f, 1.302130045760958100f, + 1.301838940548830600f, + 1.301547787471806900f, 1.301256586540591600f, 1.300965337765891600f, + 1.300674041158414800f, + 1.300382696728871400f, 1.300091304487973800f, 1.299799864446435200f, + 1.299508376614971500f, + 1.299216841004299200f, 1.298925257625137800f, 1.298633626488207500f, + 1.298341947604231300f, + 1.298050220983932900f, 1.297758446638038700f, 1.297466624577275900f, + 1.297174754812374400f, + 1.296882837354065100f, 1.296590872213081200f, 1.296298859400157700f, + 1.296006798926030200f, + 1.295714690801437600f, 1.295422535037119800f, 1.295130331643818500f, + 1.294838080632277000f, + 1.294545782013240900f, 1.294253435797456900f, 1.293961041995673700f, + 1.293668600618642000f, + 1.293376111677113900f, 1.293083575181843500f, 1.292790991143586200f, + 1.292498359573099700f, + 1.292205680481143500f, 1.291912953878477900f, 1.291620179775866400f, + 1.291327358184073200f, + 1.291034489113864100f, 1.290741572576007400f, 1.290448608581273000f, + 1.290155597140431700f, + 1.289862538264257700f, 1.289569431963524900f, 1.289276278249010600f, + 1.288983077131493000f, + 1.288689828621752300f, 1.288396532730570400f, 1.288103189468731400f, + 1.287809798847019800f, + 1.287516360876223500f, 1.287222875567130900f, 1.286929342930532800f, + 1.286635762977221800f, + 1.286342135717991600f, 1.286048461163638000f, 1.285754739324958900f, + 1.285460970212753500f, + 1.285167153837822900f, 1.284873290210969900f, 1.284579379342998700f, + 1.284285421244715900f, + 1.283991415926929400f, 1.283697363400448900f, 1.283403263676086100f, + 1.283109116764654000f, + 1.282814922676967400f, 1.282520681423843000f, 1.282226393016099500f, + 1.281932057464557000f, + 1.281637674780037100f, 1.281343244973363700f, 1.281048768055361900f, + 1.280754244036858900f, + 1.280459672928683500f, 1.280165054741666300f, 1.279870389486639400f, + 1.279575677174437100f, + 1.279280917815894600f, 1.278986111421849900f, 1.278691258003142000f, + 1.278396357570611900f, + 1.278101410135101800f, 1.277806415707456700f, 1.277511374298522200f, + 1.277216285919146500f, + 1.276921150580179200f, 1.276625968292471000f, 1.276330739066875400f, + 1.276035462914247000f, + 1.275740139845442400f, 1.275444769871319600f, 1.275149353002738700f, + 1.274853889250561200f, + 1.274558378625650200f, 1.274262821138871300f, 1.273967216801090900f, + 1.273671565623178100f, + 1.273375867616002300f, 1.273080122790436000f, 1.272784331157352800f, + 1.272488492727628100f, + 1.272192607512139300f, 1.271896675521764900f, 1.271600696767385400f, + 1.271304671259883200f, + 1.271008599010142500f, 1.270712480029048800f, 1.270416314327489800f, + 1.270120101916354600f, + 1.269823842806533800f, 1.269527537008920300f, 1.269231184534408200f, + 1.268934785393893700f, + 1.268638339598274500f, 1.268341847158450200f, 1.268045308085321800f, + 1.267748722389792100f, + 1.267452090082765900f, 1.267155411175149500f, 1.266858685677851000f, + 1.266561913601780100f, + 1.266265094957848000f, 1.265968229756968100f, 1.265671318010055400f, + 1.265374359728026500f, + 1.265077354921799300f, 1.264780303602294200f, 1.264483205780432700f, + 1.264186061467138500f, + 1.263888870673336400f, 1.263591633409954000f, 1.263294349687918800f, + 1.262997019518161700f, + 1.262699642911614600f, 1.262402219879211300f, 1.262104750431887000f, + 1.261807234580578900f, + 1.261509672336225600f, 1.261212063709767900f, 1.260914408712147800f, + 1.260616707354309500f, + 1.260318959647198400f, 1.260021165601761900f, 1.259723325228949000f, + 1.259425438539710300f, + 1.259127505544998600f, 1.258829526255768000f, 1.258531500682973800f, + 1.258233428837574300f, + 1.257935310730528000f, 1.257637146372796400f, 1.257338935775342200f, + 1.257040678949129500f, + 1.256742375905124400f, 1.256444026654294400f, 1.256145631207609400f, + 1.255847189576040100f, + 1.255548701770560000f, 1.255250167802143000f, 1.254951587681765600f, + 1.254652961420405600f, + 1.254354289029042900f, 1.254055570518658500f, 1.253756805900235700f, + 1.253457995184759300f, + 1.253159138383215200f, 1.252860235506592100f, 1.252561286565879300f, + 1.252262291572068900f, + 1.251963250536153500f, 1.251664163469128300f, 1.251365030381989700f, + 1.251065851285736200f, + 1.250766626191367500f, 1.250467355109885500f, 1.250168038052293500f, + 1.249868675029596200f, + 1.249569266052800800f, 1.249269811132915200f, 1.248970310280950200f, + 1.248670763507917100f, + 1.248371170824829300f, 1.248071532242702100f, 1.247771847772552300f, + 1.247472117425398700f, + 1.247172341212261500f, 1.246872519144162300f, 1.246572651232124700f, + 1.246272737487174300f, + 1.245972777920338000f, 1.245672772542644400f, 1.245372721365123600f, + 1.245072624398807900f, + 1.244772481654731000f, 1.244472293143928300f, 1.244172058877436800f, + 1.243871778866295400f, + 1.243571453121544000f, 1.243271081654225400f, 1.242970664475383100f, + 1.242670201596062700f, + 1.242369693027311200f, 1.242069138780177400f, 1.241768538865712000f, + 1.241467893294967200f, + 1.241167202078996800f, 1.240866465228856100f, 1.240565682755603100f, + 1.240264854670295900f, + 1.239963980983995300f, 1.239663061707763700f, 1.239362096852665300f, + 1.239061086429765300f, + 1.238760030450130900f, 1.238458928924831600f, 1.238157781864937400f, + 1.237856589281521000f, + 1.237555351185656500f, 1.237254067588419400f, 1.236952738500886900f, + 1.236651363934138300f, + 1.236349943899254000f, 1.236048478407316500f, 1.235746967469409900f, + 1.235445411096619500f, + 1.235143809300033300f, 1.234842162090739700f, 1.234540469479829900f, + 1.234238731478396000f, + 1.233936948097532400f, 1.233635119348334400f, 1.233333245241899200f, + 1.233031325789326400f, + 1.232729361001716500f, 1.232427350890172000f, 1.232125295465796600f, + 1.231823194739696300f, + 1.231521048722978200f, 1.231218857426751700f, 1.230916620862127400f, + 1.230614339040217800f, + 1.230312011972136500f, 1.230009639668999500f, 1.229707222141924100f, + 1.229404759402029400f, + 1.229102251460436400f, 1.228799698328266700f, 1.228497100016644900f, + 1.228194456536696500f, + 1.227891767899548700f, 1.227589034116330700f, 1.227286255198173100f, + 1.226983431156208200f, + 1.226680562001569900f, 1.226377647745394000f, 1.226074688398817600f, + 1.225771683972980200f, + 1.225468634479021500f, 1.225165539928084300f, 1.224862400331312400f, + 1.224559215699851500f, + 1.224255986044848500f, 1.223952711377453100f, 1.223649391708814700f, + 1.223346027050086400f, + 1.223042617412421600f, 1.222739162806975900f, 1.222435663244906700f, + 1.222132118737372400f, + 1.221828529295533800f, 1.221524894930552800f, 1.221221215653593100f, + 1.220917491475820500f, + 1.220613722408401900f, 1.220309908462505800f, 1.220006049649302800f, + 1.219702145979964600f, + 1.219398197465665400f, 1.219094204117580300f, 1.218790165946886100f, + 1.218486082964761500f, + 1.218181955182386500f, 1.217877782610943700f, 1.217573565261616000f, + 1.217269303145589000f, + 1.216964996274049400f, 1.216660644658185600f, 1.216356248309187600f, + 1.216051807238247800f, + 1.215747321456559300f, 1.215442790975316700f, 1.215138215805717300f, + 1.214833595958959300f, + 1.214528931446242600f, 1.214224222278769100f, 1.213919468467741900f, + 1.213614670024366000f, + 1.213309826959847700f, 1.213004939285395400f, 1.212700007012219100f, + 1.212395030151530300f, + 1.212090008714541600f, 1.211784942712468300f, 1.211479832156526800f, + 1.211174677057934800f, + 1.210869477427912300f, 1.210564233277680500f, 1.210258944618462200f, + 1.209953611461482200f, + 1.209648233817966600f, 1.209342811699143600f, 1.209037345116242400f, + 1.208731834080493800f, + 1.208426278603131200f, 1.208120678695388600f, 1.207815034368502100f, + 1.207509345633709600f, + 1.207203612502250300f, 1.206897834985365000f, 1.206592013094296200f, + 1.206286146840288300f, + 1.205980236234587100f, 1.205674281288440000f, 1.205368282013096200f, + 1.205062238419806200f, + 1.204756150519822300f, 1.204450018324398900f, 1.204143841844791200f, + 1.203837621092256800f, + 1.203531356078054100f, 1.203225046813444000f, 1.202918693309688300f, + 1.202612295578050900f, + 1.202305853629797500f, 1.201999367476194400f, 1.201692837128510700f, + 1.201386262598016500f, + 1.201079643895983700f, 1.200772981033685800f, 1.200466274022397900f, + 1.200159522873396800f, + 1.199852727597960700f, 1.199545888207369700f, 1.199239004712905300f, + 1.198932077125851100f, + 1.198625105457491700f, 1.198318089719113200f, 1.198011029922004400f, + 1.197703926077454200f, + 1.197396778196754700f, 1.197089586291198500f, 1.196782350372080300f, + 1.196475070450696100f, + 1.196167746538343600f, 1.195860378646322700f, 1.195552966785933900f, + 1.195245510968480300f, + 1.194938011205265900f, 1.194630467507596500f, 1.194322879886780000f, + 1.194015248354125100f, + 1.193707572920943000f, 1.193399853598545500f, 1.193092090398246900f, + 1.192784283331362700f, + 1.192476432409210100f, 1.192168537643107900f, 1.191860599044376500f, + 1.191552616624337800f, + 1.191244590394315400f, 1.190936520365635000f, 1.190628406549622900f, + 1.190320248957608100f, + 1.190012047600920200f, 1.189703802490891000f, 1.189395513638853900f, + 1.189087181056143900f, + 1.188778804754097300f, 1.188470384744052100f, 1.188161921037348400f, + 1.187853413645327100f, + 1.187544862579331500f, 1.187236267850706000f, 1.186927629470796900f, + 1.186618947450951600f, + 1.186310221802519900f, 1.186001452536852300f, 1.185692639665301600f, + 1.185383783199222000f, + 1.185074883149969100f, 1.184765939528900500f, 1.184456952347374900f, + 1.184147921616753200f, + 1.183838847348397400f, 1.183529729553671500f, 1.183220568243940300f, + 1.182911363430571200f, + 1.182602115124932900f, 1.182292823338395100f, 1.181983488082330300f, + 1.181674109368111300f, + 1.181364687207113100f, 1.181055221610712400f, 1.180745712590287400f, + 1.180436160157217800f, + 1.180126564322885100f, 1.179816925098671900f, 1.179507242495962900f, + 1.179197516526144600f, + 1.178887747200604300f, 1.178577934530731700f, 1.178268078527917200f, + 1.177958179203553800f, + 1.177648236569035300f, 1.177338250635757700f, 1.177028221415118200f, + 1.176718148918515700f, + 1.176408033157350300f, 1.176097874143024600f, 1.175787671886942000f, + 1.175477426400507700f, + 1.175167137695128900f, 1.174856805782213500f, 1.174546430673171900f, + 1.174236012379415600f, + 1.173925550912357800f, 1.173615046283413200f, 1.173304498503998400f, + 1.172993907585530900f, + 1.172683273539430800f, 1.172372596377118800f, 1.172061876110017700f, + 1.171751112749551900f, + 1.171440306307147200f, 1.171129456794231200f, 1.170818564222232800f, + 1.170507628602582800f, + 1.170196649946713100f, 1.169885628266057900f, 1.169574563572052300f, + 1.169263455876133200f, + 1.168952305189739200f, 1.168641111524310700f, 1.168329874891289400f, + 1.168018595302118000f, + 1.167707272768241800f, 1.167395907301107100f, 1.167084498912162300f, + 1.166773047612856400f, + 1.166461553414641000f, 1.166150016328968600f, 1.165838436367293800f, + 1.165526813541072100f, + 1.165215147861761400f, 1.164903439340820900f, 1.164591687989710500f, + 1.164279893819892800f, + 1.163968056842831700f, 1.163656177069992500f, 1.163344254512841800f, + 1.163032289182848800f, + 1.162720281091483000f, 1.162408230250216100f, 1.162096136670521600f, + 1.161784000363874000f, + 1.161471821341749900f, 1.161159599615627000f, 1.160847335196984800f, + 1.160535028097304600f, + 1.160222678328068700f, 1.159910285900761700f, 1.159597850826869200f, + 1.159285373117878500f, + 1.158972852785278500f, 1.158660289840559800f, 1.158347684295214300f, + 1.158035036160735900f, + 1.157722345448619400f, 1.157409612170361600f, 1.157096836337461000f, + 1.156784017961417500f, + 1.156471157053732300f, 1.156158253625908700f, 1.155845307689450800f, + 1.155532319255865300f, + 1.155219288336659400f, 1.154906214943342700f, 1.154593099087426000f, + 1.154279940780421400f, + 1.153966740033842900f, 1.153653496859206000f, 1.153340211268028000f, + 1.153026883271827300f, + 1.152713512882124400f, 1.152400100110440700f, 1.152086644968299400f, + 1.151773147467225300f, + 1.151459607618745300f, 1.151146025434387000f, 1.150832400925680100f, + 1.150518734104155400f, + 1.150205024981345800f, 1.149891273568785400f, 1.149577479878009800f, + 1.149263643920556800f, + 1.148949765707964600f, 1.148635845251773800f, 1.148321882563526400f, + 1.148007877654766200f, + 1.147693830537038100f, 1.147379741221888500f, 1.147065609720865600f, + 1.146751436045519300f, + 1.146437220207400700f, 1.146122962218062600f, 1.145808662089060000f, + 1.145494319831947800f, + 1.145179935458284100f, 1.144865508979627800f, 1.144551040407539400f, + 1.144236529753581000f, + 1.143921977029316500f, 1.143607382246310600f, 1.143292745416130600f, + 1.142978066550344400f, + 1.142663345660522000f, 1.142348582758234900f, 1.142033777855056000f, + 1.141718930962559500f, + 1.141404042092321500f, 1.141089111255919800f, 1.140774138464933700f, + 1.140459123730943200f, + 1.140144067065530700f, 1.139828968480280300f, 1.139513827986776900f, + 1.139198645596607400f, + 1.138883421321360600f, 1.138568155172625700f, 1.138252847161994400f, + 1.137937497301059600f, + 1.137622105601416000f, 1.137306672074659900f, 1.136991196732388200f, + 1.136675679586200500f, + 1.136360120647697200f, 1.136044519928480800f, 1.135728877440154800f, + 1.135413193194324800f, + 1.135097467202597100f, 1.134781699476580300f, 1.134465890027884300f, + 1.134150038868120500f, + 1.133834146008902100f, 1.133518211461843200f, 1.133202235238559800f, + 1.132886217350669500f, + 1.132570157809791500f, 1.132254056627546300f, 1.131937913815556300f, + 1.131621729385444900f, + 1.131305503348837300f, 1.130989235717360100f, 1.130672926502642100f, + 1.130356575716312500f, + 1.130040183370002900f, 1.129723749475346000f, 1.129407274043976200f, + 1.129090757087529500f, + 1.128774198617643200f, 1.128457598645956600f, 1.128140957184109700f, + 1.127824274243744500f, + 1.127507549836505000f, 1.127190783974035800f, 1.126873976667983800f, + 1.126557127929996800f, + 1.126240237771724700f, 1.125923306204818400f, 1.125606333240930700f, + 1.125289318891715900f, + 1.124972263168829500f, 1.124655166083928800f, 1.124338027648672500f, + 1.124020847874721100f, + 1.123703626773736100f, 1.123386364357381200f, 1.123069060637320600f, + 1.122751715625221400f, + 1.122434329332750800f, 1.122116901771578400f, 1.121799432953375600f, + 1.121481922889814300f, + 1.121164371592568300f, 1.120846779073313400f, 1.120529145343726500f, + 1.120211470415486200f, + 1.119893754300272300f, 1.119575997009766300f, 1.119258198555651300f, + 1.118940358949611900f, + 1.118622478203333800f, 1.118304556328505200f, 1.117986593336814700f, + 1.117668589239953200f, + 1.117350544049612300f, 1.117032457777486200f, 1.116714330435269600f, + 1.116396162034659600f, + 1.116077952587353600f, 1.115759702105052000f, 1.115441410599455500f, + 1.115123078082267000f, + 1.114804704565190500f, 1.114486290059931900f, 1.114167834578198200f, + 1.113849338131698300f, + 1.113530800732142100f, 1.113212222391241500f, 1.112893603120710000f, + 1.112574942932261600f, + 1.112256241837613000f, 1.111937499848481900f, 1.111618716976587700f, + 1.111299893233650600f, + 1.110981028631393700f, 1.110662123181539900f, 1.110343176895814500f, + 1.110024189785944900f, + 1.109705161863658600f, 1.109386093140686000f, 1.109066983628758100f, + 1.108747833339607200f, + 1.108428642284968100f, 1.108109410476576300f, 1.107790137926169200f, + 1.107470824645485600f, + 1.107151470646265300f, 1.106832075940250600f, 1.106512640539184100f, + 1.106193164454811100f, + 1.105873647698877300f, 1.105554090283131100f, 1.105234492219321100f, + 1.104914853519198400f, + 1.104595174194514800f, 1.104275454257024300f, 1.103955693718482200f, + 1.103635892590644900f, + 1.103316050885270600f, 1.102996168614119000f, 1.102676245788951400f, + 1.102356282421530300f, + 1.102036278523620000f, 1.101716234106985700f, 1.101396149183395000f, + 1.101076023764616400f, + 1.100755857862419700f, 1.100435651488577100f, 1.100115404654861100f, + 1.099795117373046200f, + 1.099474789654909100f, 1.099154421512226600f, 1.098834012956778200f, + 1.098513564000344300f, + 1.098193074654706800f, 1.097872544931649100f, 1.097551974842956500f, + 1.097231364400415000f, + 1.096910713615813200f, 1.096590022500939700f, 1.096269291067585700f, + 1.095948519327543800f, + 1.095627707292607700f, 1.095306854974572800f, 1.094985962385235800f, + 1.094665029536395100f, + 1.094344056439850600f, 1.094023043107403200f, 1.093701989550856000f, + 1.093380895782013000f, + 1.093059761812680100f, 1.092738587654664300f, 1.092417373319774200f, + 1.092096118819820200f, + 1.091774824166613600f, 1.091453489371968100f, 1.091132114447697300f, + 1.090810699405617900f, + 1.090489244257547300f, 1.090167749015304300f, 1.089846213690709900f, + 1.089524638295585400f, + 1.089203022841754400f, 1.088881367341041800f, 1.088559671805274100f, + 1.088237936246279100f, + 1.087916160675885800f, 1.087594345105925300f, 1.087272489548229700f, + 1.086950594014632700f, + 1.086628658516969500f, 1.086306683067076900f, 1.085984667676792600f, + 1.085662612357956500f, + 1.085340517122409800f, 1.085018381981994500f, 1.084696206948555300f, + 1.084373992033937000f, + 1.084051737249986900f, 1.083729442608553300f, 1.083407108121486000f, + 1.083084733800636200f, + 1.082762319657857100f, 1.082439865705002500f, 1.082117371953928300f, + 1.081794838416491700f, + 1.081472265104551200f, 1.081149652029967000f, 1.080826999204601100f, + 1.080504306640315500f, + 1.080181574348975500f, 1.079858802342446900f, 1.079535990632596800f, + 1.079213139231294500f, + 1.078890248150409700f, 1.078567317401815100f, 1.078244346997383300f, + 1.077921336948988600f, + 1.077598287268508400f, 1.077275197967819000f, 1.076952069058800400f, + 1.076628900553332700f, + 1.076305692463297900f, 1.075982444800579700f, 1.075659157577062200f, + 1.075335830804633000f, + 1.075012464495178800f, 1.074689058660589700f, 1.074365613312755900f, + 1.074042128463569500f, + 1.073718604124924500f, 1.073395040308715400f, 1.073071437026839500f, + 1.072747794291194300f, + 1.072424112113678600f, 1.072100390506194500f, 1.071776629480643500f, + 1.071452829048929800f, + 1.071128989222958500f, 1.070805110014635900f, 1.070481191435870500f, + 1.070157233498571600f, + 1.069833236214650800f, 1.069509199596019800f, 1.069185123654592600f, + 1.068861008402285200f, + 1.068536853851013600f, 1.068212660012696700f, 1.067888426899253500f, + 1.067564154522606000f, + 1.067239842894676100f, 1.066915492027387600f, 1.066591101932666800f, + 1.066266672622439700f, + 1.065942204108635300f, 1.065617696403183400f, 1.065293149518014500f, + 1.064968563465062100f, + 1.064643938256259400f, 1.064319273903543000f, 1.063994570418849400f, + 1.063669827814116300f, + 1.063345046101285000f, 1.063020225292295300f, 1.062695365399091200f, + 1.062370466433616400f, + 1.062045528407815900f, 1.061720551333637600f, 1.061395535223029500f, + 1.061070480087941800f, + 1.060745385940325500f, 1.060420252792134000f, 1.060095080655320900f, + 1.059769869541841800f, + 1.059444619463654400f, 1.059119330432716700f, 1.058794002460989000f, + 1.058468635560432500f, + 1.058143229743009600f, 1.057817785020685100f, 1.057492301405424500f, + 1.057166778909195000f, + 1.056841217543965200f, 1.056515617321704500f, 1.056189978254385100f, + 1.055864300353978900f, + 1.055538583632461100f, 1.055212828101807200f, 1.054887033773993300f, + 1.054561200660999200f, + 1.054235328774803900f, 1.053909418127389400f, 1.053583468730738200f, + 1.053257480596834700f, + 1.052931453737664600f, 1.052605388165214700f, 1.052279283891473600f, + 1.051953140928431100f, + 1.051626959288079100f, 1.051300738982409800f, 1.050974480023417500f, + 1.050648182423098000f, + 1.050321846193448000f, 1.049995471346466300f, 1.049669057894152800f, + 1.049342605848508200f, + 1.049016115221536000f, 1.048689586025239700f, 1.048363018271625300f, + 1.048036411972699500f, + 1.047709767140470500f, 1.047383083786948700f, 1.047056361924144400f, + 1.046729601564071200f, + 1.046402802718742400f, 1.046075965400174300f, 1.045749089620383200f, + 1.045422175391386800f, + 1.045095222725206200f, 1.044768231633861100f, 1.044441202129375200f, + 1.044114134223771900f, + 1.043787027929076000f, 1.043459883257315400f, 1.043132700220517300f, + 1.042805478830712200f, + 1.042478219099930400f, 1.042150921040204200f, 1.041823584663568200f, + 1.041496209982056600f, + 1.041168797007707000f, 1.040841345752557200f, 1.040513856228645800f, + 1.040186328448014800f, + 1.039858762422705600f, 1.039531158164762400f, 1.039203515686230000f, + 1.038875834999155100f, + 1.038548116115585800f, 1.038220359047570500f, 1.037892563807160800f, + 1.037564730406408200f, + 1.037236858857366600f, 1.036908949172090900f, 1.036581001362636600f, + 1.036253015441062700f, + 1.035924991419427100f, 1.035596929309791300f, 1.035268829124216700f, + 1.034940690874766300f, + 1.034612514573505700f, 1.034284300232500000f, 1.033956047863817500f, + 1.033627757479526700f, + 1.033299429091697700f, 1.032971062712402700f, 1.032642658353714300f, + 1.032314216027707700f, + 1.031985735746457900f, 1.031657217522042900f, 1.031328661366541300f, + 1.031000067292032300f, + 1.030671435310598600f, 1.030342765434322200f, 1.030014057675287900f, + 1.029685312045581100f, + 1.029356528557288300f, 1.029027707222499100f, 1.028698848053302100f, + 1.028369951061789600f, + 1.028041016260053500f, 1.027712043660187600f, 1.027383033274288400f, + 1.027053985114451100f, + 1.026724899192775300f, 1.026395775521359500f, 1.026066614112305600f, + 1.025737414977715200f, + 1.025408178129692000f, 1.025078903580341600f, 1.024749591341769700f, + 1.024420241426085200f, + 1.024090853845396800f, 1.023761428611814600f, 1.023431965737451800f, + 1.023102465234420700f, + 1.022772927114837100f, 1.022443351390816400f, 1.022113738074476300f, + 1.021784087177936000f, + 1.021454398713315600f, 1.021124672692737000f, 1.020794909128323000f, + 1.020465108032198300f, + 1.020135269416488700f, 1.019805393293321100f, 1.019475479674824900f, + 1.019145528573129000f, + 1.018815540000365800f, 1.018485513968667500f, 1.018155450490168000f, + 1.017825349577003300f, + 1.017495211241309800f, 1.017165035495226400f, 1.016834822350892300f, + 1.016504571820448000f, + 1.016174283916036800f, 1.015843958649801600f, 1.015513596033888400f, + 1.015183196080442900f, + 1.014852758801613200f, 1.014522284209548900f, 1.014191772316400000f, + 1.013861223134318900f, + 1.013530636675459100f, 1.013200012951974700f, 1.012869351976022300f, + 1.012538653759758900f, + 1.012207918315344300f, 1.011877145654937400f, 1.011546335790700600f, + 1.011215488734796800f, + 1.010884604499389800f, 1.010553683096645900f, 1.010222724538731600f, + 1.009891728837815700f, + 1.009560696006067900f, 1.009229626055658800f, 1.008898518998761800f, + 1.008567374847549900f, + 1.008236193614199000f, 1.007904975310885300f, 1.007573719949786700f, + 1.007242427543082900f, + 1.006911098102953900f, 1.006579731641582500f, 1.006248328171152100f, + 1.005916887703846500f, + 1.005585410251852700f, 1.005253895827357800f, 1.004922344442551000f, + 1.004590756109621900f, + 1.004259130840762700f, 1.003927468648166100f, 1.003595769544025900f, + 1.003264033540538500f, + 1.002932260649900000f, 1.002600450884309800f, 1.002268604255967200f, + 1.001936720777072400f, + 1.001604800459829000f, 1.001272843316440000f, 1.000940849359111000f, + 1.000608818600048100f, + 1.000276751051459200f, 0.999944646725553720f, 0.999612505634541740f, + 0.999280327790635690f, + 0.998948113206048590f, 0.998615861892994560f, 0.998283573863690270f, + 0.997951249130352380f, + 0.997618887705200020f, 0.997286489600452630f, 0.996954054828332210f, + 0.996621583401061110f, + 0.996289075330862860f, 0.995956530629963810f, 0.995623949310589620f, + 0.995291331384969390f, + 0.994958676865332010f, 0.994625985763907820f, 0.994293258092929790f, + 0.993960493864630480f, + 0.993627693091245660f, 0.993294855785010760f, 0.992961981958163210f, + 0.992629071622942340f, + 0.992296124791587690f, 0.991963141476341460f, 0.991630121689446090f, + 0.991297065443145440f, + 0.990963972749685840f, 0.990630843621313260f, 0.990297678070276800f, + 0.989964476108825210f, + 0.989631237749210020f, 0.989297963003683330f, 0.988964651884498000f, + 0.988631304403909890f, + 0.988297920574174430f, 0.987964500407549910f, 0.987631043916294970f, + 0.987297551112669370f, + 0.986964022008935520f, 0.986630456617355380f, 0.986296854950194260f, + 0.985963217019717120f, + 0.985629542838190490f, 0.985295832417883540f, 0.984962085771065030f, + 0.984628302910006580f, + 0.984294483846980150f, 0.983960628594258810f, 0.983626737164118190f, + 0.983292809568833910f, + 0.982958845820684270f, 0.982624845931947320f, 0.982290809914904140f, + 0.981956737781835790f, + 0.981622629545024770f, 0.981288485216756160f, 0.980954304809314670f, + 0.980620088334987930f, + 0.980285835806063770f, 0.979951547234831130f, 0.979617222633581860f, + 0.979282862014607240f, + 0.978948465390201530f, 0.978614032772659240f, 0.978279564174275860f, + 0.977945059607349900f, + 0.977610519084179290f, 0.977275942617064740f, 0.976941330218307540f, + 0.976606681900209830f, + 0.976271997675076550f, 0.975937277555212310f, 0.975602521552924600f, + 0.975267729680520560f, + 0.974932901950310350f, 0.974598038374604350f, 0.974263138965714040f, + 0.973928203735953460f, + 0.973593232697636530f, 0.973258225863079970f, 0.972923183244600480f, + 0.972588104854516410f, + 0.972252990705148370f, 0.971917840808816710f, 0.971582655177844700f, + 0.971247433824555920f, + 0.970912176761274950f, 0.970576884000329040f, 0.970241555554045230f, + 0.969906191434753320f, + 0.969570791654783330f, 0.969235356226466500f, 0.968899885162136650f, + 0.968564378474127350f, + 0.968228836174775060f, 0.967893258276415700f, 0.967557644791388500f, + 0.967221995732032490f, + 0.966886311110688230f, 0.966550590939698640f, 0.966214835231406500f, + 0.965879043998157160f, + 0.965543217252296420f, 0.965207355006171270f, 0.964871457272131190f, + 0.964535524062525410f, + 0.964199555389706030f, 0.963863551266025300f, 0.963527511703836660f, + 0.963191436715496120f, + 0.962855326313359350f, 0.962519180509785130f, 0.962182999317132030f, + 0.961846782747760140f, + 0.961510530814032040f, 0.961174243528309820f, 0.960837920902958720f, + 0.960501562950343390f, + 0.960165169682831830f, 0.959828741112791590f, 0.959492277252591900f, + 0.959155778114604400f, + 0.958819243711200310f, 0.958482674054753960f, 0.958146069157639560f, + 0.957809429032232760f, + 0.957472753690911670f, 0.957136043146054050f, 0.956799297410040440f, + 0.956462516495251940f, + 0.956125700414070300f, 0.955788849178880300f, 0.955451962802066120f, + 0.955115041296014880f, + 0.954778084673113870f, 0.954441092945751630f, 0.954104066126319150f, + 0.953767004227207060f, + 0.953429907260809120f, 0.953092775239518630f, 0.952755608175731570f, + 0.952418406081844360f, + 0.952081168970254520f, 0.951743896853362140f, 0.951406589743566950f, + 0.951069247653271500f, + 0.950731870594878510f, 0.950394458580791970f, 0.950057011623418380f, + 0.949719529735163940f, + 0.949382012928437600f, 0.949044461215648560f, 0.948706874609207220f, + 0.948369253121526420f, + 0.948031596765018910f, 0.947693905552099870f, 0.947356179495185020f, + 0.947018418606691230f, + 0.946680622899037650f, 0.946342792384643360f, 0.946004927075930090f, + 0.945667026985319680f, + 0.945329092125236190f, 0.944991122508104350f, 0.944653118146349890f, + 0.944315079052401090f, + 0.943977005238685770f, 0.943638896717634900f, 0.943300753501679190f, + 0.942962575603250920f, + 0.942624363034784580f, 0.942286115808714690f, 0.941947833937478270f, + 0.941609517433512730f, + 0.941271166309256450f, 0.940932780577150460f, 0.940594360249635500f, + 0.940255905339155150f, + 0.939917415858152920f, 0.939578891819073720f, 0.939240333234364950f, + 0.938901740116473540f, + 0.938563112477849630f, 0.938224450330942590f, 0.937885753688204820f, + 0.937547022562088990f, + 0.937208256965048840f, 0.936869456909540490f, 0.936530622408019990f, + 0.936191753472946030f, + 0.935852850116777430f, 0.935513912351974450f, 0.935174940190999560f, + 0.934835933646314900f, + 0.934496892730385720f, 0.934157817455677160f, 0.933818707834655590f, + 0.933479563879790030f, + 0.933140385603548840f, 0.932801173018403480f, 0.932461926136825660f, + 0.932122644971287830f, + 0.931783329534265240f, 0.931443979838232900f, 0.931104595895668410f, + 0.930765177719049210f, + 0.930425725320855430f, 0.930086238713567440f, 0.929746717909666790f, + 0.929407162921637610f, + 0.929067573761963250f, 0.928727950443130500f, 0.928388292977625930f, + 0.928048601377937210f, + 0.927708875656554800f, 0.927369115825968480f, 0.927029321898671270f, + 0.926689493887155820f, + 0.926349631803916270f, 0.926009735661449170f, 0.925669805472250860f, + 0.925329841248820340f, + 0.924989843003656610f, 0.924649810749260110f, 0.924309744498133750f, + 0.923969644262779830f, + 0.923629510055703820f, 0.923289341889410480f, 0.922949139776407800f, + 0.922608903729203570f, + 0.922268633760306990f, 0.921928329882229390f, 0.921587992107482210f, + 0.921247620448579440f, + 0.920907214918035070f, 0.920566775528364410f, 0.920226302292085460f, + 0.919885795221715540f, + 0.919545254329774850f, 0.919204679628783720f, 0.918864071131263780f, + 0.918523428849739030f, + 0.918182752796733110f, 0.917842042984772340f, 0.917501299426383480f, + 0.917160522134094160f, + 0.916819711120434700f, 0.916478866397934850f, 0.916137987979127270f, + 0.915797075876544350f, + 0.915456130102721200f, 0.915115150670193110f, 0.914774137591496510f, + 0.914433090879170130f, + 0.914092010545752620f, 0.913750896603785280f, 0.913409749065809520f, + 0.913068567944367970f, + 0.912727353252005710f, 0.912386105001267270f, 0.912044823204700370f, + 0.911703507874852440f, + 0.911362159024272310f, 0.911020776665511290f, 0.910679360811120000f, + 0.910337911473652390f, + 0.909996428665661990f, 0.909654912399703860f, 0.909313362688335290f, + 0.908971779544113350f, + 0.908630162979597760f, 0.908288513007348140f, 0.907946829639926790f, + 0.907605112889895870f, + 0.907263362769819000f, 0.906921579292262250f, 0.906579762469791110f, + 0.906237912314974080f, + 0.905896028840379560f, 0.905554112058577170f, 0.905212161982139160f, + 0.904870178623637170f, + 0.904528161995645670f, 0.904186112110739510f, 0.903844028981494190f, + 0.903501912620488070f, + 0.903159763040298880f, 0.902817580253507450f, 0.902475364272694370f, + 0.902133115110441470f, + 0.901790832779333250f, 0.901448517291953520f, 0.901106168660889110f, + 0.900763786898726380f, + 0.900421372018054500f, 0.900078924031462610f, 0.899736442951541320f, + 0.899393928790883420f, + 0.899051381562081310f, 0.898708801277730340f, 0.898366187950425780f, + 0.898023541592764210f, + 0.897680862217344440f, 0.897338149836764960f, 0.896995404463627350f, + 0.896652626110532870f, + 0.896309814790084090f, 0.895966970514885940f, 0.895624093297543110f, + 0.895281183150662960f, + 0.894938240086852970f, 0.894595264118721810f, 0.894252255258880410f, + 0.893909213519939460f, + 0.893566138914512420f, 0.893223031455212530f, 0.892879891154655380f, + 0.892536718025457090f, + 0.892193512080234670f, 0.891850273331607600f, 0.891507001792195000f, + 0.891163697474618880f, + 0.890820360391500920f, 0.890476990555464480f, 0.890133587979135000f, + 0.889790152675137610f, + 0.889446684656100330f, 0.889103183934650930f, 0.888759650523418650f, + 0.888416084435035060f, + 0.888072485682131150f, 0.887728854277341050f, 0.887385190233298650f, + 0.887041493562639060f, + 0.886697764277999840f, 0.886354002392018110f, 0.886010207917333760f, + 0.885666380866586560f, + 0.885322521252418610f, 0.884978629087472270f, 0.884634704384391180f, + 0.884290747155821230f, + 0.883946757414407980f, 0.883602735172799640f, 0.883258680443644530f, + 0.882914593239592320f, + 0.882570473573294660f, 0.882226321457403320f, 0.881882136904572400f, + 0.881537919927456340f, + 0.881193670538710450f, 0.880849388750992610f, 0.880505074576960370f, + 0.880160728029273920f, + 0.879816349120593590f, 0.879471937863580690f, 0.879127494270899090f, + 0.878783018355212220f, + 0.878438510129186170f, 0.878093969605486800f, 0.877749396796782770f, + 0.877404791715742370f, + 0.877060154375035710f, 0.876715484787334630f, 0.876370782965310900f, + 0.876026048921639160f, + 0.875681282668993700f, 0.875336484220050390f, 0.874991653587487090f, + 0.874646790783981660f, + 0.874301895822214290f, 0.873956968714865500f, 0.873612009474616810f, + 0.873267018114152300f, + 0.872921994646155390f, 0.872576939083312460f, 0.872231851438309840f, + 0.871886731723835020f, + 0.871541579952577750f, 0.871196396137227660f, 0.870851180290476810f, + 0.870505932425017060f, + 0.870160652553543020f, 0.869815340688749220f, 0.869469996843331370f, + 0.869124621029987670f, + 0.868779213261415610f, 0.868433773550315810f, 0.868088301909388680f, + 0.867742798351335720f, + 0.867397262888861100f, 0.867051695534668210f, 0.866706096301463340f, + 0.866360465201952980f, + 0.866014802248844420f, 0.865669107454847490f, 0.865323380832671800f, + 0.864977622395029290f, + 0.864631832154632240f, 0.864286010124194040f, 0.863940156316430170f, + 0.863594270744056040f, + 0.863248353419789670f, 0.862902404356348570f, 0.862556423566453230f, + 0.862210411062823810f, + 0.861864366858181910f, 0.861518290965251340f, 0.861172183396755500f, + 0.860826044165420630f, + 0.860479873283972910f, 0.860133670765139580f, 0.859787436621650360f, + 0.859441170866234390f, + 0.859094873511623840f, 0.858748544570550610f, 0.858402184055747750f, + 0.858055791979950740f, + 0.857709368355894840f, 0.857362913196317630f, 0.857016426513956930f, + 0.856669908321551650f, + 0.856323358631843170f, 0.855976777457572280f, 0.855630164811482460f, + 0.855283520706317080f, + 0.854936845154821930f, 0.854590138169742830f, 0.854243399763827020f, + 0.853896629949823630f, + 0.853549828740481690f, 0.853202996148552880f, 0.852856132186788910f, + 0.852509236867942440f, + 0.852162310204768740f, 0.851815352210022470f, 0.851468362896461110f, + 0.851121342276842110f, + 0.850774290363923820f, 0.850427207170467380f, 0.850080092709233130f, + 0.849732946992984290f, + 0.849385770034483680f, 0.849038561846496730f, 0.848691322441788910f, + 0.848344051833126780f, + 0.847996750033279350f, 0.847649417055015060f, 0.847302052911105160f, + 0.846954657614320980f, + 0.846607231177434640f, 0.846259773613221020f, 0.845912284934454140f, + 0.845564765153910990f, + 0.845217214284368690f, 0.844869632338605130f, 0.844522019329400630f, + 0.844174375269535320f, + 0.843826700171791620f, 0.843478994048952440f, 0.843131256913801420f, + 0.842783488779124570f, + 0.842435689657707650f, 0.842087859562339000f, 0.841739998505806610f, + 0.841392106500900900f, + 0.841044183560412770f, 0.840696229697133760f, 0.840348244923857960f, + 0.840000229253379030f, + 0.839652182698493290f, 0.839304105271996950f, 0.838955996986687550f, + 0.838607857855364740f, + 0.838259687890827830f, 0.837911487105878820f, 0.837563255513319780f, + 0.837214993125953600f, + 0.836866699956585690f, 0.836518376018021260f, 0.836170021323067610f, + 0.835821635884532730f, + 0.835473219715225040f, 0.835124772827955830f, 0.834776295235535540f, + 0.834427786950777460f, + 0.834079247986494690f, 0.833730678355502630f, 0.833382078070616820f, + 0.833033447144653880f, + 0.832684785590432690f, 0.832336093420771970f, 0.831987370648492710f, + 0.831638617286416190f, + 0.831289833347364620f, 0.830941018844162600f, 0.830592173789634240f, + 0.830243298196606360f, + 0.829894392077905720f, 0.829545455446360270f, 0.829196488314800080f, + 0.828847490696055010f, + 0.828498462602957340f, 0.828149404048339590f, 0.827800315045035150f, + 0.827451195605879990f, + 0.827102045743709160f, 0.826752865471360950f, 0.826403654801672770f, + 0.826054413747485010f, + 0.825705142321637720f, 0.825355840536972420f, 0.825006508406332490f, + 0.824657145942561230f, + 0.824307753158504460f, 0.823958330067008030f, 0.823608876680918760f, + 0.823259393013085820f, + 0.822909879076357930f, 0.822560334883586490f, 0.822210760447622980f, + 0.821861155781319800f, + 0.821511520897531660f, 0.821161855809112830f, 0.820812160528920360f, + 0.820462435069811090f, + 0.820112679444643060f, 0.819762893666276530f, 0.819413077747571440f, + 0.819063231701390170f, + 0.818713355540594880f, 0.818363449278050270f, 0.818013512926620940f, + 0.817663546499172720f, + 0.817313550008573640f, 0.816963523467691410f, 0.816613466889396070f, + 0.816263380286557980f, + 0.815913263672048310f, 0.815563117058740630f, 0.815212940459508210f, + 0.814862733887226740f, + 0.814512497354771830f, 0.814162230875020380f, 0.813811934460851430f, + 0.813461608125143560f, + 0.813111251880778150f, 0.812760865740636440f, 0.812410449717600570f, + 0.812060003824555230f, + 0.811709528074384460f, 0.811359022479975040f, 0.811008487054213360f, + 0.810657921809988410f, + 0.810307326760189020f, 0.809956701917705080f, 0.809606047295428950f, + 0.809255362906252440f, + 0.808904648763069890f, 0.808553904878775760f, 0.808203131266265420f, + 0.807852327938436750f, + 0.807501494908186900f, 0.807150632188415760f, 0.806799739792023240f, + 0.806448817731910130f, + 0.806097866020979660f, 0.805746884672134620f, 0.805395873698280360f, + 0.805044833112322000f, + 0.804693762927166100f, 0.804342663155721230f, 0.803991533810895500f, + 0.803640374905599810f, + 0.803289186452744390f, 0.802937968465242240f, 0.802586720956006250f, + 0.802235443937950320f, + 0.801884137423990890f, 0.801532801427043530f, 0.801181435960026780f, + 0.800830041035858750f, + 0.800478616667459010f, 0.800127162867749210f, 0.799775679649650460f, + 0.799424167026086540f, + 0.799072625009981330f, 0.798721053614259490f, 0.798369452851848020f, + 0.798017822735673680f, + 0.797666163278665570f, 0.797314474493752810f, 0.796962756393865600f, + 0.796611008991936490f, + 0.796259232300897350f, 0.795907426333682830f, 0.795555591103226930f, + 0.795203726622466520f, + 0.794851832904338360f, 0.794499909961779990f, 0.794147957807731400f, + 0.793795976455132220f, + 0.793443965916924570f, 0.793091926206050400f, 0.792739857335452710f, + 0.792387759318077150f, + 0.792035632166868230f, 0.791683475894773720f, 0.791331290514740830f, + 0.790979076039718180f, + 0.790626832482656310f, 0.790274559856505520f, 0.789922258174218570f, + 0.789569927448748320f, + 0.789217567693048520f, 0.788865178920075130f, 0.788512761142783790f, + 0.788160314374132590f, + 0.787807838627079260f, 0.787455333914584220f, 0.787102800249607550f, + 0.786750237645110430f, + 0.786397646114056490f, 0.786045025669408700f, 0.785692376324132690f, + 0.785339698091194080f, + 0.784986990983559170f, 0.784634255014197040f, 0.784281490196075850f, + 0.783928696542166680f, + 0.783575874065440270f, 0.783223022778868350f, 0.782870142695425320f, + 0.782517233828084580f, + 0.782164296189822530f, 0.781811329793615120f, 0.781458334652439630f, + 0.781105310779275470f, + 0.780752258187101480f, 0.780399176888899150f, 0.780046066897649550f, + 0.779692928226336290f, + 0.779339760887942880f, 0.778986564895453810f, 0.778633340261856040f, + 0.778280087000135730f, + 0.777926805123281830f, 0.777573494644283050f, 0.777220155576129220f, + 0.776866787931812410f, + 0.776513391724324210f, 0.776159966966658680f, 0.775806513671809860f, + 0.775453031852772920f, + 0.775099521522545020f, 0.774745982694123090f, 0.774392415380506400f, + 0.774038819594694230f, + 0.773685195349686940f, 0.773331542658487140f, 0.772977861534096640f, + 0.772624151989520280f, + 0.772270414037761980f, 0.771916647691828660f, 0.771562852964726710f, + 0.771209029869463940f, + 0.770855178419050050f, 0.770501298626494410f, 0.770147390504808960f, + 0.769793454067005500f, + 0.769439489326096850f, 0.769085496295098040f, 0.768731474987023660f, + 0.768377425414890850f, + 0.768023347591716640f, 0.767669241530518850f, 0.767315107244318060f, + 0.766960944746133740f, + 0.766606754048988260f, 0.766252535165903970f, 0.765898288109903900f, + 0.765544012894013530f, + 0.765189709531257760f, 0.764835378034664170f, 0.764481018417259680f, + 0.764126630692073870f, + 0.763772214872136200f, 0.763417770970477140f, 0.763063299000129260f, + 0.762708798974124800f, + 0.762354270905498450f, 0.761999714807284790f, 0.761645130692519490f, + 0.761290518574240350f, + 0.760935878465484720f, 0.760581210379292380f, 0.760226514328703140f, + 0.759871790326757670f, + 0.759517038386499090f, 0.759162258520969860f, 0.758807450743214760f, + 0.758452615066278920f, + 0.758097751503208020f, 0.757742860067050380f, 0.757387940770853360f, + 0.757032993627667290f, + 0.756678018650541630f, 0.756323015852528700f, 0.755967985246680520f, + 0.755612926846050080f, + 0.755257840663692730f, 0.754902726712663120f, 0.754547585006018600f, + 0.754192415556816380f, + 0.753837218378114460f, 0.753481993482973400f, 0.753126740884452970f, + 0.752771460595615500f, + 0.752416152629523330f, 0.752060816999239660f, 0.751705453717829930f, + 0.751350062798359140f, + 0.750994644253894730f, 0.750639198097504010f, 0.750283724342255320f, + 0.749928223001219310f, + 0.749572694087465850f, 0.749217137614067500f, 0.748861553594096340f, + 0.748505942040627040f, + 0.748150302966733790f, 0.747794636385492150f, 0.747438942309979870f, + 0.747083220753273820f, + 0.746727471728453770f, 0.746371695248599140f, 0.746015891326790470f, + 0.745660059976110400f, + 0.745304201209641030f, 0.744948315040467210f, 0.744592401481673270f, + 0.744236460546344850f, + 0.743880492247569580f, 0.743524496598434670f, 0.743168473612029980f, + 0.742812423301444810f, + 0.742456345679769810f, 0.742100240760097840f, 0.741744108555520860f, + 0.741387949079133860f, + 0.741031762344030790f, 0.740675548363308620f, 0.740319307150063780f, + 0.739963038717393880f, + 0.739606743078398690f, 0.739250420246177380f, 0.738894070233831800f, + 0.738537693054463370f, + 0.738181288721174830f, 0.737824857247070810f, 0.737468398645255490f, + 0.737111912928835710f, + 0.736755400110918000f, 0.736398860204609870f, 0.736042293223021060f, + 0.735685699179260850f, + 0.735329078086440880f, 0.734972429957672760f, 0.734615754806068890f, + 0.734259052644744230f, + 0.733902323486812610f, 0.733545567345390890f, 0.733188784233595240f, + 0.732831974164544150f, + 0.732475137151356370f, 0.732118273207151170f, 0.731761382345050280f, + 0.731404464578174760f, + 0.731047519919648340f, 0.730690548382594280f, 0.730333549980137110f, + 0.729976524725403530f, + 0.729619472631519270f, 0.729262393711613280f, 0.728905287978813600f, + 0.728548155446249730f, + 0.728190996127053180f, 0.727833810034354990f, 0.727476597181288540f, + 0.727119357580987220f, + 0.726762091246585200f, 0.726404798191218950f, 0.726047478428024420f, + 0.725690131970139980f, + 0.725332758830703360f, 0.724975359022855150f, 0.724617932559735390f, + 0.724260479454485130f, + 0.723902999720247850f, 0.723545493370166160f, 0.723187960417385530f, + 0.722830400875050790f, + 0.722472814756308090f, 0.722115202074305680f, 0.721757562842191060f, + 0.721399897073114470f, + 0.721042204780225960f, 0.720684485976676230f, 0.720326740675618530f, + 0.719968968890205230f, + 0.719611170633591480f, 0.719253345918932090f, 0.718895494759382860f, + 0.718537617168101610f, + 0.718179713158245800f, 0.717821782742975370f, 0.717463825935449550f, + 0.717105842748830160f, + 0.716747833196278770f, 0.716389797290958090f, 0.716031735046032900f, + 0.715673646474667140f, + 0.715315531590027700f, 0.714957390405280950f, 0.714599222933594240f, + 0.714241029188137260f, + 0.713882809182079030f, 0.713524562928591010f, 0.713166290440844450f, + 0.712807991732011590f, + 0.712449666815266890f, 0.712091315703784260f, 0.711732938410739810f, + 0.711374534949309800f, + 0.711016105332671340f, 0.710657649574003460f, 0.710299167686484930f, + 0.709940659683296890f, + 0.709582125577619790f, 0.709223565382636760f, 0.708864979111530680f, + 0.708506366777485130f, + 0.708147728393686340f, 0.707789063973319310f, 0.707430373529572170f, + 0.707071657075632460f, + 0.706712914624688770f, 0.706354146189931750f, 0.705995351784551530f, + 0.705636531421740880f, + 0.705277685114692020f, 0.704918812876598410f, 0.704559914720655490f, + 0.704200990660058150f, + 0.703842040708003820f, 0.703483064877689630f, 0.703124063182313690f, + 0.702765035635076310f, + 0.702405982249177160f, 0.702046903037818250f, 0.701687798014201110f, + 0.701328667191529980f, + 0.700969510583008600f, 0.700610328201841660f, 0.700251120061236020f, + 0.699891886174398130f, + 0.699532626554536630f, 0.699173341214860190f, 0.698814030168578240f, + 0.698454693428902320f, + 0.698095331009043640f, 0.697735942922215520f, 0.697376529181631400f, + 0.697017089800505250f, + 0.696657624792053730f, 0.696298134169492380f, 0.695938617946039510f, + 0.695579076134912990f, + 0.695219508749331800f, 0.694859915802517050f, 0.694500297307689140f, + 0.694140653278070950f, + 0.693780983726884790f, 0.693421288667355530f, 0.693061568112707690f, + 0.692701822076166820f, + 0.692342050570960430f, 0.691982253610315510f, 0.691622431207461700f, + 0.691262583375628180f, + 0.690902710128045050f, 0.690542811477944610f, 0.690182887438558710f, + 0.689822938023121220f, + 0.689462963244866330f, 0.689102963117028790f, 0.688742937652845550f, + 0.688382886865552930f, + 0.688022810768389670f, 0.687662709374594510f, 0.687302582697406850f, + 0.686942430750068330f, + 0.686582253545819920f, 0.686222051097905130f, 0.685861823419566700f, + 0.685501570524050140f, + 0.685141292424600310f, 0.684780989134463280f, 0.684420660666887120f, + 0.684060307035119440f, + 0.683699928252410110f, 0.683339524332008840f, 0.682979095287166160f, + 0.682618641131135020f, + 0.682258161877167370f, 0.681897657538517720f, 0.681537128128440470f, + 0.681176573660190910f, + 0.680815994147026320f, 0.680455389602203310f, 0.680094760038981280f, + 0.679734105470619080f, + 0.679373425910376310f, 0.679012721371515250f, 0.678651991867297080f, + 0.678291237410985510f, + 0.677930458015843620f, 0.677569653695137220f, 0.677208824462131490f, + 0.676847970330092700f, + 0.676487091312289350f, 0.676126187421989040f, 0.675765258672461950f, + 0.675404305076978020f, + 0.675043326648808170f, 0.674682323401225250f, 0.674321295347501510f, + 0.673960242500911690f, + 0.673599164874730370f, 0.673238062482232950f, 0.672876935336696900f, + 0.672515783451398950f, + 0.672154606839618470f, 0.671793405514634180f, 0.671432179489727110f, + 0.671070928778178090f, + 0.670709653393269050f, 0.670348353348283690f, 0.669987028656505170f, + 0.669625679331219300f, + 0.669264305385711360f, 0.668902906833267590f, 0.668541483687176590f, + 0.668180035960725840f, + 0.667818563667205600f, 0.667457066819905800f, 0.667095545432117240f, + 0.666733999517132860f, + 0.666372429088244790f, 0.666010834158747840f, 0.665649214741936390f, + 0.665287570851105680f, + 0.664925902499553190f, 0.664564209700575500f, 0.664202492467472090f, + 0.663840750813541210f, + 0.663478984752084110f, 0.663117194296401260f, 0.662755379459794350f, + 0.662393540255567070f, + 0.662031676697022450f, 0.661669788797465960f, 0.661307876570202740f, + 0.660945940028538900f, + 0.660583979185782600f, 0.660221994055241400f, 0.659859984650225110f, + 0.659497950984043510f, + 0.659135893070007080f, 0.658773810921428500f, 0.658411704551619570f, + 0.658049573973894850f, + 0.657687419201568260f, 0.657325240247955020f, 0.656963037126372160f, + 0.656600809850135910f, + 0.656238558432565400f, 0.655876282886978410f, 0.655513983226695960f, + 0.655151659465038060f, + 0.654789311615326050f, 0.654426939690883280f, 0.654064543705032310f, + 0.653702123671098150f, + 0.653339679602405470f, 0.652977211512280050f, 0.652614719414049580f, + 0.652252203321041060f, + 0.651889663246583930f, 0.651527099204007310f, 0.651164511206641320f, + 0.650801899267818060f, + 0.650439263400868990f, 0.650076603619127890f, 0.649713919935928420f, + 0.649351212364604910f, + 0.648988480918494040f, 0.648625725610931460f, 0.648262946455255510f, + 0.647900143464803730f, + 0.647537316652916140f, 0.647174466032932490f, 0.646811591618193350f, + 0.646448693422041360f, + 0.646085771457818310f, 0.645722825738868860f, 0.645359856278536980f, + 0.644996863090167570f, + 0.644633846187107620f, 0.644270805582703550f, 0.643907741290304040f, + 0.643544653323257610f, + 0.643181541694913480f, 0.642818406418622980f, 0.642455247507736860f, + 0.642092064975608220f, + 0.641728858835589830f, 0.641365629101035340f, 0.641002375785300500f, + 0.640639098901740200f, + 0.640275798463712080f, 0.639912474484572560f, 0.639549126977681070f, + 0.639185755956396480f, + 0.638822361434078330f, 0.638458943424088490f, 0.638095501939787920f, + 0.637732036994540290f, + 0.637368548601708660f, 0.637005036774657030f, 0.636641501526751590f, + 0.636277942871357530f, + 0.635914360821842830f, 0.635550755391574910f, 0.635187126593922070f, + 0.634823474442254840f, + 0.634459798949942640f, 0.634096100130357660f, 0.633732377996871770f, + 0.633368632562857470f, + 0.633004863841689520f, 0.632641071846741790f, 0.632277256591390780f, + 0.631913418089012020f, + 0.631549556352983710f, 0.631185671396683470f, 0.630821763233490040f, + 0.630457831876783950f, + 0.630093877339945260f, 0.629729899636356280f, 0.629365898779399080f, + 0.629001874782456500f, + 0.628637827658913300f, 0.628273757422153860f, 0.627909664085564810f, + 0.627545547662532230f, + 0.627181408166443410f, 0.626817245610687520f, 0.626453060008652860f, + 0.626088851373730380f, + 0.625724619719310480f, 0.625360365058784670f, 0.624996087405546350f, + 0.624631786772988030f, + 0.624267463174504880f, 0.623903116623491180f, 0.623538747133343780f, + 0.623174354717459190f, + 0.622809939389234460f, 0.622445501162069090f, 0.622081040049361490f, + 0.621716556064512820f, + 0.621352049220923570f, 0.620987519531995270f, 0.620622967011131400f, + 0.620258391671734690f, + 0.619893793527210410f, 0.619529172590963410f, 0.619164528876399280f, + 0.618799862396925750f, + 0.618435173165949760f, 0.618070461196880800f, 0.617705726503127720f, + 0.617340969098100430f, + 0.616976188995210780f, 0.616611386207870040f, 0.616246560749491690f, + 0.615881712633488340f, + 0.615516841873275490f, 0.615151948482267840f, 0.614787032473881110f, + 0.614422093861533010f, + 0.614057132658640590f, 0.613692148878623000f, 0.613327142534899510f, + 0.612962113640889710f, + 0.612597062210015750f, 0.612231988255698470f, 0.611866891791361560f, + 0.611501772830428060f, + 0.611136631386322020f, 0.610771467472469460f, 0.610406281102295440f, + 0.610041072289227990f, + 0.609675841046694030f, 0.609310587388121830f, 0.608945311326941520f, + 0.608580012876582370f, + 0.608214692050476290f, 0.607849348862054220f, 0.607483983324749510f, + 0.607118595451995420f, + 0.606753185257225550f, 0.606387752753876020f, 0.606022297955381760f, + 0.605656820875180360f, + 0.605291321526709060f, 0.604925799923405670f, 0.604560256078710220f, + 0.604194690006061960f, + 0.603829101718902580f, 0.603463491230673220f, 0.603097858554815790f, + 0.602732203704774650f, + 0.602366526693992930f, 0.602000827535916330f, 0.601635106243990190f, + 0.601269362831660550f, + 0.600903597312375640f, 0.600537809699582810f, 0.600172000006731770f, + 0.599806168247271620f, + 0.599440314434653620f, 0.599074438582328780f, 0.598708540703749010f, + 0.598342620812368000f, + 0.597976678921638860f, 0.597610715045016950f, 0.597244729195957500f, + 0.596878721387916090f, + 0.596512691634350830f, 0.596146639948718640f, 0.595780566344478960f, + 0.595414470835091030f, + 0.595048353434014630f, 0.594682214154711790f, 0.594316053010643270f, + 0.593949870015273000f, + 0.593583665182063740f, 0.593217438524479500f, 0.592851190055986300f, + 0.592484919790049140f, + 0.592118627740135460f, 0.591752313919712170f, 0.591385978342248260f, + 0.591019621021212420f, + 0.590653241970074180f, 0.590286841202305120f, 0.589920418731375800f, + 0.589553974570759530f, + 0.589187508733928890f, 0.588821021234357310f, 0.588454512085520460f, + 0.588087981300892900f, + 0.587721428893951850f, 0.587354854878173850f, 0.586988259267036350f, + 0.586621642074019120f, + 0.586255003312600500f, 0.585888342996261690f, 0.585521661138483250f, + 0.585154957752746730f, + 0.584788232852535560f, 0.584421486451332410f, 0.584054718562622140f, + 0.583687929199888990f, + 0.583321118376619710f, 0.582954286106300290f, 0.582587432402417840f, + 0.582220557278461340f, + 0.581853660747918780f, 0.581486742824280810f, 0.581119803521037650f, + 0.580752842851679940f, + 0.580385860829700780f, 0.580018857468592270f, 0.579651832781848730f, + 0.579284786782964360f, + 0.578917719485433800f, 0.578550630902754050f, 0.578183521048421080f, + 0.577816389935933090f, + 0.577449237578788300f, 0.577082063990485340f, 0.576714869184524860f, + 0.576347653174406840f, + 0.575980415973633590f, 0.575613157595706530f, 0.575245878054129520f, + 0.574878577362406000f, + 0.574511255534040030f, 0.574143912582537940f, 0.573776548521405030f, + 0.573409163364148930f, + 0.573041757124277180f, 0.572674329815297640f, 0.572306881450720390f, + 0.571939412044054740f, + 0.571571921608812320f, 0.571204410158504090f, 0.570836877706642270f, + 0.570469324266740570f, + 0.570101749852312100f, 0.569734154476872480f, 0.569366538153936560f, + 0.568998900897020210f, + 0.568631242719641270f, 0.568263563635316600f, 0.567895863657565500f, + 0.567528142799906490f, + 0.567160401075860410f, 0.566792638498947680f, 0.566424855082689470f, + 0.566057050840608870f, + 0.565689225786228160f, 0.565321379933072190f, 0.564953513294665140f, + 0.564585625884531870f, + 0.564217717716199550f, 0.563849788803194140f, 0.563481839159044150f, + 0.563113868797277870f, + 0.562745877731423820f, 0.562377865975012940f, 0.562009833541575080f, + 0.561641780444642640f, + 0.561273706697747450f, 0.560905612314422150f, 0.560537497308201240f, + 0.560169361692618440f, + 0.559801205481210040f, 0.559433028687510990f, 0.559064831325059240f, + 0.558696613407391630f, + 0.558328374948046320f, 0.557960115960563050f, 0.557591836458480870f, + 0.557223536455341280f, + 0.556855215964685120f, 0.556486875000054000f, 0.556118513574991650f, + 0.555750131703040880f, + 0.555381729397746880f, 0.555013306672654360f, 0.554644863541308600f, + 0.554276400017257090f, + 0.553907916114046440f, 0.553539411845225590f, 0.553170887224342820f, + 0.552802342264947400f, + 0.552433776980590490f, 0.552065191384822350f, 0.551696585491195710f, + 0.551327959313262280f, + 0.550959312864576220f, 0.550590646158691240f, 0.550221959209161620f, + 0.549853252029543830f, + 0.549484524633393480f, 0.549115777034268170f, 0.548747009245725500f, + 0.548378221281323520f, + 0.548009413154622370f, 0.547640584879181100f, 0.547271736468561530f, + 0.546902867936324590f, + 0.546533979296032200f, 0.546165070561248080f, 0.545796141745535150f, + 0.545427192862458780f, + 0.545058223925583670f, 0.544689234948475210f, 0.544320225944701200f, + 0.543951196927828010f, + 0.543582147911424560f, 0.543213078909059120f, 0.542843989934301940f, + 0.542474881000723050f, + 0.542105752121893050f, 0.541736603311384620f, 0.541367434582769480f, + 0.540998245949621760f, + 0.540629037425515050f, 0.540259809024023600f, 0.539890560758723770f, + 0.539521292643190930f, + 0.539152004691002770f, 0.538782696915736770f, 0.538413369330970610f, + 0.538044021950284450f, + 0.537674654787257180f, 0.537305267855470390f, 0.536935861168504670f, + 0.536566434739941920f, + 0.536196988583365510f, 0.535827522712358230f, 0.535458037140505110f, + 0.535088531881390050f, + 0.534719006948599860f, 0.534349462355720230f, 0.533979898116337950f, + 0.533610314244041710f, + 0.533240710752419080f, 0.532871087655060300f, 0.532501444965554960f, + 0.532131782697493170f, + 0.531762100864467290f, 0.531392399480068670f, 0.531022678557890980f, + 0.530652938111527360f, + 0.530283178154571710f, 0.529913398700619820f, 0.529543599763266700f, + 0.529173781356109600f, + 0.528803943492745180f, 0.528434086186771010f, 0.528064209451786560f, + 0.527694313301390160f, + 0.527324397749182720f, 0.526954462808764120f, 0.526584508493736840f, + 0.526214534817702310f, + 0.525844541794263210f, 0.525474529437023890f, 0.525104497759587900f, + 0.524734446775560910f, + 0.524364376498548390f, 0.523994286942156220f, 0.523624178119992400f, + 0.523254050045663940f, + 0.522883902732780290f, 0.522513736194950230f, 0.522143550445783310f, + 0.521773345498891090f, + 0.521403121367884030f, 0.521032878066375100f, 0.520662615607976660f, + 0.520292334006301820f, + 0.519922033274965560f, 0.519551713427582000f, 0.519181374477767470f, + 0.518811016439137520f, + 0.518440639325310040f, 0.518070243149902240f, 0.517699827926532130f, + 0.517329393668819580f, + 0.516958940390383700f, 0.516588468104845820f, 0.516217976825826600f, + 0.515847466566947580f, + 0.515476937341832310f, 0.515106389164103120f, 0.514735822047384990f, + 0.514365236005302040f, + 0.513994631051479240f, 0.513624007199543600f, 0.513253364463121090f, + 0.512882702855839920f, + 0.512512022391327980f, 0.512141323083213470f, 0.511770604945127050f, + 0.511399867990697920f, + 0.511029112233557960f, 0.510658337687338040f, 0.510287544365671140f, + 0.509916732282189920f, + 0.509545901450527690f, 0.509175051884319660f, 0.508804183597200140f, + 0.508433296602805670f, + 0.508062390914772230f, 0.507691466546736580f, 0.507320523512337470f, + 0.506949561825212450f, + 0.506578581499001590f, 0.506207582547344550f, 0.505836564983881190f, + 0.505465528822253710f, + 0.505094474076103310f, 0.504723400759073290f, 0.504352308884806750f, + 0.503981198466947000f, + 0.503610069519139780f, 0.503238922055029400f, 0.502867756088262840f, + 0.502496571632486070f, + 0.502125368701347050f, 0.501754147308493770f, 0.501382907467574190f, + 0.501011649192238950f, + 0.500640372496137020f, 0.500269077392920150f, 0.499897763896239410f, + 0.499526432019746450f, + 0.499155081777094940f, 0.498783713181937540f, 0.498412326247929250f, + 0.498040920988724490f, + 0.497669497417978280f, 0.497298055549347750f, 0.496926595396488870f, + 0.496555116973059980f, + 0.496183620292718900f, 0.495812105369124070f, 0.495440572215935850f, + 0.495069020846813650f, + 0.494697451275419140f, 0.494325863515413130f, 0.493954257580458580f, + 0.493582633484217940f, + 0.493210991240354450f, 0.492839330862533120f, 0.492467652364417970f, + 0.492095955759675460f, + 0.491724241061971320f, 0.491352508284972070f, 0.490980757442346090f, + 0.490608988547760690f, + 0.490237201614885710f, 0.489865396657390210f, 0.489493573688943970f, + 0.489121732723218740f, + 0.488749873773885120f, 0.488377996854616250f, 0.488006101979084450f, + 0.487634189160962910f, + 0.487262258413926560f, 0.486890309751649490f, 0.486518343187807900f, + 0.486146358736077200f, + 0.485774356410135000f, 0.485402336223658360f, 0.485030298190324950f, + 0.484658242323814380f, + 0.484286168637805270f, 0.483914077145978560f, 0.483541967862014480f, + 0.483169840799594130f, + 0.482797695972400300f, 0.482425533394114920f, 0.482053353078422120f, + 0.481681155039005550f, + 0.481308939289549380f, 0.480936705843739820f, 0.480564454715261990f, + 0.480192185917803270f, + 0.479819899465050160f, 0.479447595370691370f, 0.479075273648415010f, + 0.478702934311909910f, + 0.478330577374866780f, 0.477958202850975230f, 0.477585810753927250f, + 0.477213401097414220f, + 0.476840973895128200f, 0.476468529160763100f, 0.476096066908011760f, + 0.475723587150569390f, + 0.475351089902130650f, 0.474978575176390750f, 0.474606042987046840f, + 0.474233493347795020f, + 0.473860926272333670f, 0.473488341774360670f, 0.473115739867574380f, + 0.472743120565675250f, + 0.472370483882362520f, 0.471997829831337810f, 0.471625158426301700f, + 0.471252469680957190f, + 0.470879763609006460f, 0.470507040224152460f, 0.470134299540099940f, + 0.469761541570552780f, + 0.469388766329217000f, 0.469015973829798090f, 0.468643164086002100f, + 0.468270337111537040f, + 0.467897492920109850f, 0.467524631525429830f, 0.467151752941205530f, + 0.466778857181146260f, + 0.466405944258963200f, 0.466033014188366350f, 0.465660066983068220f, + 0.465287102656780530f, + 0.464914121223215740f, 0.464541122696088100f, 0.464168107089110940f, + 0.463795074415999760f, + 0.463422024690469060f, 0.463048957926235630f, 0.462675874137015720f, + 0.462302773336526080f, + 0.461929655538485470f, 0.461556520756611410f, 0.461183369004623920f, + 0.460810200296242310f, + 0.460437014645186440f, 0.460063812065178160f, 0.459690592569938270f, + 0.459317356173189750f, + 0.458944102888655060f, 0.458570832730057170f, 0.458197545711121090f, + 0.457824241845570630f, + 0.457450921147131930f, 0.457077583629530550f, 0.456704229306492570f, + 0.456330858191746010f, + 0.455957470299017840f, 0.455584065642037350f, 0.455210644234532610f, + 0.454837206090234200f, + 0.454463751222871910f, 0.454090279646176210f, 0.453716791373879380f, + 0.453343286419712720f, + 0.452969764797409750f, 0.452596226520703360f, 0.452222671603327130f, + 0.451849100059016350f, + 0.451475511901505420f, 0.451101907144530910f, 0.450728285801828830f, + 0.450354647887135640f, + 0.449980993414189900f, 0.449607322396728900f, 0.449233634848492320f, + 0.448859930783219170f, + 0.448486210214649020f, 0.448112473156523420f, 0.447738719622582710f, + 0.447364949626569590f, + 0.446991163182225700f, 0.446617360303294910f, 0.446243541003520480f, + 0.445869705296646270f, + 0.445495853196417930f, 0.445121984716580210f, 0.444748099870879880f, + 0.444374198673063330f, + 0.444000281136877280f, 0.443626347276070590f, 0.443252397104390790f, + 0.442878430635587910f, + 0.442504447883411090f, 0.442130448861610240f, 0.441756433583937120f, + 0.441382402064142250f, + 0.441008354315978680f, 0.440634290353198510f, 0.440260210189554690f, + 0.439886113838801880f, + 0.439512001314693700f, 0.439137872630986080f, 0.438763727801433690f, + 0.438389566839793740f, + 0.438015389759822630f, 0.437641196575277220f, 0.437266987299916590f, + 0.436892761947498260f, + 0.436518520531782470f, 0.436144263066528480f, 0.435769989565496290f, + 0.435395700042447710f, + 0.435021394511143410f, 0.434647072985346380f, 0.434272735478819010f, + 0.433898382005324050f, + 0.433524012578626440f, 0.433149627212489670f, 0.432775225920679740f, + 0.432400808716961900f, + 0.432026375615101930f, 0.431651926628867530f, 0.431277461772025310f, + 0.430902981058344070f, + 0.430528484501591540f, 0.430153972115537800f, 0.429779443913952170f, + 0.429404899910604490f, + 0.429030340119266550f, 0.428655764553708960f, 0.428281173227704760f, + 0.427906566155026040f, + 0.427531943349445720f, 0.427157304824738350f, 0.426782650594677570f, + 0.426407980673039090f, + 0.426033295073598160f, 0.425658593810130330f, 0.425283876896413280f, + 0.424909144346223290f, + 0.424534396173339160f, 0.424159632391538870f, 0.423784853014600950f, + 0.423410058056305830f, + 0.423035247530432810f, 0.422660421450763490f, 0.422285579831078230f, + 0.421910722685159720f, + 0.421535850026790060f, 0.421160961869751720f, 0.420786058227829220f, + 0.420411139114805770f, + 0.420036204544466940f, 0.419661254530597550f, 0.419286289086983070f, + 0.418911308227410740f, + 0.418536311965666650f, 0.418161300315539220f, 0.417786273290816130f, + 0.417411230905285650f, + 0.417036173172737830f, 0.416661100106961610f, 0.416286011721748230f, + 0.415910908030888200f, + 0.415535789048172620f, 0.415160654787394280f, 0.414785505262345030f, + 0.414410340486818910f, + 0.414035160474608700f, 0.413659965239509710f, 0.413284754795316230f, + 0.412909529155823300f, + 0.412534288334827750f, 0.412159032346125280f, 0.411783761203513790f, + 0.411408474920790520f, + 0.411033173511753220f, 0.410657856990201580f, 0.410282525369933980f, + 0.409907178664751180f, + 0.409531816888453190f, 0.409156440054840590f, 0.408781048177715660f, + 0.408405641270879690f, + 0.408030219348136270f, 0.407654782423288010f, 0.407279330510138260f, + 0.406903863622492260f, + 0.406528381774153900f, 0.406152884978929480f, 0.405777373250624070f, + 0.405401846603045010f, + 0.405026305049998980f, 0.404650748605293040f, 0.404275177282736260f, + 0.403899591096136380f, + 0.403523990059303620f, 0.403148374186047210f, 0.402772743490177110f, + 0.402397097985504990f, + 0.402021437685841480f, 0.401645762604999350f, 0.401270072756790610f, + 0.400894368155027990f, + 0.400518648813525830f, 0.400142914746097480f, 0.399767165966558420f, + 0.399391402488723400f, + 0.399015624326407800f, 0.398639831493428740f, 0.398264024003602220f, + 0.397888201870746420f, + 0.397512365108678430f, 0.397136513731217500f, 0.396760647752182230f, + 0.396384767185391620f, + 0.396008872044666730f, 0.395632962343827170f, 0.395257038096694990f, + 0.394881099317091370f, + 0.394505146018838130f, 0.394129178215758820f, 0.393753195921675850f, + 0.393377199150413860f, + 0.393001187915796750f, 0.392625162231649010f, 0.392249122111796800f, + 0.391873067570065240f, + 0.391496998620281590f, 0.391120915276272410f, 0.390744817551864850f, + 0.390368705460887750f, + 0.389992579017168830f, 0.389616438234538010f, 0.389240283126824070f, + 0.388864113707858060f, + 0.388487929991470140f, 0.388111731991491180f, 0.387735519721753690f, + 0.387359293196089140f, + 0.386983052428331030f, 0.386606797432312350f, 0.386230528221866430f, + 0.385854244810828530f, + 0.385477947213032580f, 0.385101635442314900f, 0.384725309512510880f, + 0.384348969437456610f, + 0.383972615230989860f, 0.383596246906947210f, 0.383219864479167560f, + 0.382843467961488940f, + 0.382467057367749940f, 0.382090632711791060f, 0.381714194007451380f, + 0.381337741268572390f, + 0.380961274508994250f, 0.380584793742559550f, 0.380208298983109930f, + 0.379831790244487540f, + 0.379455267540536490f, 0.379078730885099520f, 0.378702180292021630f, + 0.378325615775147170f, + 0.377949037348320800f, 0.377572445025389230f, 0.377195838820197690f, + 0.376819218746593910f, + 0.376442584818424570f, 0.376065937049537060f, 0.375689275453780500f, + 0.375312600045002780f, + 0.374935910837054080f, 0.374559207843783660f, 0.374182491079041500f, + 0.373805760556679190f, + 0.373429016290547200f, 0.373052258294498230f, 0.372675486582383640f, + 0.372298701168057190f, + 0.371921902065371730f, 0.371545089288180640f, 0.371168262850339210f, + 0.370791422765701320f, + 0.370414569048123140f, 0.370037701711460170f, 0.369660820769568240f, + 0.369283926236305070f, + 0.368907018125527120f, 0.368530096451093140f, 0.368153161226860980f, + 0.367776212466689010f, + 0.367399250184437480f, 0.367022274393965340f, 0.366645285109133750f, + 0.366268282343803150f, + 0.365891266111834370f, 0.365514236427090080f, 0.365137193303431750f, + 0.364760136754723020f, + 0.364383066794826350f, 0.364005983437606320f, 0.363628886696926890f, + 0.363251776586652310f, + 0.362874653120648700f, 0.362497516312780990f, 0.362120366176916230f, + 0.361743202726920790f, + 0.361366025976661450f, 0.360988835940006750f, 0.360611632630824020f, + 0.360234416062982840f, + 0.359857186250351960f, 0.359479943206800550f, 0.359102686946199680f, + 0.358725417482419150f, + 0.358348134829330870f, 0.357970839000806010f, 0.357593530010716310f, + 0.357216207872935120f, + 0.356838872601334680f, 0.356461524209789380f, 0.356084162712172360f, + 0.355706788122359060f, + 0.355329400454223950f, 0.354951999721642100f, 0.354574585938490280f, + 0.354197159118644080f, + 0.353819719275981330f, 0.353442266424378930f, 0.353064800577714280f, + 0.352687321749866610f, + 0.352309829954713830f, 0.351932325206136210f, 0.351554807518012990f, + 0.351177276904224070f, + 0.350799733378650890f, 0.350422176955173910f, 0.350044607647675640f, + 0.349667025470037810f, + 0.349289430436142520f, 0.348911822559873850f, 0.348534201855114360f, + 0.348156568335749040f, + 0.347778922015661520f, 0.347401262908737570f, 0.347023591028862320f, + 0.346645906389921150f, + 0.346268209005801410f, 0.345890498890388980f, 0.345512776057572080f, + 0.345135040521238170f, + 0.344757292295274910f, 0.344379531393571970f, 0.344001757830017680f, + 0.343623971618502560f, + 0.343246172772916250f, 0.342868361307148980f, 0.342490537235092600f, + 0.342112700570637750f, + 0.341734851327677280f, 0.341356989520103240f, 0.340979115161808070f, + 0.340601228266685980f, + 0.340223328848629880f, 0.339845416921535030f, 0.339467492499295200f, + 0.339089555595806560f, + 0.338711606224964210f, 0.338333644400663940f, 0.337955670136803170f, + 0.337577683447278010f, + 0.337199684345986910f, 0.336821672846827290f, 0.336443648963697160f, + 0.336065612710496290f, + 0.335687564101123050f, 0.335309503149478110f, 0.334931429869461230f, + 0.334553344274972690f, + 0.334175246379914470f, 0.333797136198187240f, 0.333419013743693980f, + 0.333040879030336690f, + 0.332662732072017800f, 0.332284572882641680f, 0.331906401476111280f, + 0.331528217866331690f, + 0.331150022067206780f, 0.330771814092642610f, 0.330393593956544440f, + 0.330015361672817750f, + 0.329637117255370090f, 0.329258860718107450f, 0.328880592074938190f, + 0.328502311339769700f, + 0.328124018526509800f, 0.327745713649068180f, 0.327367396721353070f, + 0.326989067757275040f, + 0.326610726770743760f, 0.326232373775669270f, 0.325854008785963320f, + 0.325475631815536570f, + 0.325097242878301660f, 0.324718841988170470f, 0.324340429159055250f, + 0.323962004404870050f, + 0.323583567739527570f, 0.323205119176942720f, 0.322826658731029110f, + 0.322448186415702550f, + 0.322069702244877910f, 0.321691206232470550f, 0.321312698392397570f, + 0.320934178738574720f, + 0.320555647284919980f, 0.320177104045350440f, 0.319798549033783570f, + 0.319419982264138650f, + 0.319041403750333630f, 0.318662813506288670f, 0.318284211545923010f, + 0.317905597883156250f, + 0.317526972531909870f, 0.317148335506103940f, 0.316769686819660780f, + 0.316391026486501690f, + 0.316012354520548600f, 0.315633670935725030f, 0.315254975745953180f, + 0.314876268965157470f, + 0.314497550607261090f, 0.314118820686189180f, 0.313740079215866160f, + 0.313361326210216840f, + 0.312982561683167790f, 0.312603785648644220f, 0.312224998120573420f, + 0.311846199112882030f, + 0.311467388639496860f, 0.311088566714346650f, 0.310709733351358600f, + 0.310330888564462340f, + 0.309952032367586390f, 0.309573164774659850f, 0.309194285799613390f, + 0.308815395456376430f, + 0.308436493758880660f, 0.308057580721056660f, 0.307678656356835560f, + 0.307299720680150270f, + 0.306920773704932260f, 0.306541815445115160f, 0.306162845914631390f, + 0.305783865127415400f, + 0.305404873097400780f, 0.305025869838521590f, 0.304646855364713530f, + 0.304267829689911010f, + 0.303888792828050650f, 0.303509744793068030f, 0.303130685598899270f, + 0.302751615259482190f, + 0.302372533788753170f, 0.301993441200650910f, 0.301614337509113100f, + 0.301235222728077840f, + 0.300856096871485010f, 0.300476959953273060f, 0.300097811987382670f, + 0.299718652987753580f, + 0.299339482968325970f, 0.298960301943041680f, 0.298581109925841300f, + 0.298201906930667390f, + 0.297822692971461410f, 0.297443468062166820f, 0.297064232216726120f, + 0.296684985449082390f, + 0.296305727773180260f, 0.295926459202963120f, 0.295547179752376430f, + 0.295167889435364820f, + 0.294788588265873170f, 0.294409276257848300f, 0.294029953425235520f, + 0.293650619781982260f, + 0.293271275342035120f, 0.292891920119341120f, 0.292512554127848930f, + 0.292133177381505850f, + 0.291753789894261320f, 0.291374391680063520f, 0.290994982752862730f, + 0.290615563126608250f, + 0.290236132815249790f, 0.289856691832738880f, 0.289477240193025510f, + 0.289097777910061970f, + 0.288718304997799550f, 0.288338821470189910f, 0.287959327341186510f, + 0.287579822624741350f, + 0.287200307334808670f, 0.286820781485341620f, 0.286441245090293950f, + 0.286061698163620930f, + 0.285682140719276560f, 0.285302572771216960f, 0.284922994333397350f, + 0.284543405419773240f, + 0.284163806044301910f, 0.283784196220939370f, 0.283404575963643550f, + 0.283024945286371230f, + 0.282645304203081090f, 0.282265652727731130f, 0.281885990874279570f, + 0.281506318656686290f, + 0.281126636088910030f, 0.280746943184911340f, 0.280367239958650150f, + 0.279987526424086530f, + 0.279607802595182420f, 0.279228068485898210f, 0.278848324110196550f, + 0.278468569482039130f, + 0.278088804615388040f, 0.277709029524206950f, 0.277329244222458250f, + 0.276949448724106480f, + 0.276569643043115150f, 0.276189827193448200f, 0.275810001189071290f, + 0.275430165043948570f, + 0.275050318772046500f, 0.274670462387330010f, 0.274290595903766200f, + 0.273910719335321300f, + 0.273530832695961790f, 0.273150935999655950f, 0.272771029260370560f, + 0.272391112492074590f, + 0.272011185708736060f, 0.271631248924323390f, 0.271251302152806570f, + 0.270871345408154380f, + 0.270491378704337540f, 0.270111402055325910f, 0.269731415475089780f, + 0.269351418977600950f, + 0.268971412576829990f, 0.268591396286749500f, 0.268211370121331170f, + 0.267831334094547010f, + 0.267451288220370730f, 0.267071232512774700f, 0.266691166985733360f, + 0.266311091653219700f, + 0.265931006529208920f, 0.265550911627675250f, 0.265170806962593210f, + 0.264790692547939020f, + 0.264410568397687560f, 0.264030434525815760f, 0.263650290946299660f, + 0.263270137673115630f, + 0.262889974720241610f, 0.262509802101654310f, 0.262129619831332370f, + 0.261749427923253670f, + 0.261369226391396310f, 0.260989015249740050f, 0.260608794512263380f, + 0.260228564192946710f, + 0.259848324305769600f, 0.259468074864711960f, 0.259087815883755400f, + 0.258707547376880010f, + 0.258327269358068100f, 0.257946981841300490f, 0.257566684840560170f, + 0.257186378369829110f, + 0.256806062443089680f, 0.256425737074325920f, 0.256045402277520320f, + 0.255665058066657680f, + 0.255284704455721660f, 0.254904341458696390f, 0.254523969089567590f, + 0.254143587362319620f, + 0.253763196290938850f, 0.253382795889410710f, 0.253002386171721110f, + 0.252621967151857420f, + 0.252241538843805680f, 0.251861101261554090f, 0.251480654419089730f, + 0.251100198330400150f, + 0.250719733009474530f, 0.250339258470300590f, 0.249958774726868170f, + 0.249578281793165680f, + 0.249197779683183660f, 0.248817268410911650f, 0.248436747990339490f, + 0.248056218435458720f, + 0.247675679760259450f, 0.247295131978733870f, 0.246914575104873220f, + 0.246534009152669040f, + 0.246153434136114490f, 0.245772850069201410f, 0.245392256965923620f, + 0.245011654840274010f, + 0.244631043706245800f, 0.244250423577833860f, 0.243869794469031620f, + 0.243489156393834590f, + 0.243108509366237320f, 0.242727853400234670f, 0.242347188509823150f, + 0.241966514708997830f, + 0.241585832011755900f, 0.241205140432093070f, 0.240824439984007180f, + 0.240443730681495050f, + 0.240063012538553830f, 0.239682285569182310f, 0.239301549787377890f, + 0.238920805207139960f, + 0.238540051842467020f, 0.238159289707357810f, 0.237778518815812740f, + 0.237397739181830820f, + 0.237016950819413100f, 0.236636153742559610f, 0.236255347965270780f, + 0.235874533501548580f, + 0.235493710365393630f, 0.235112878570808560f, 0.234732038131795020f, + 0.234351189062355030f, + 0.233970331376492150f, 0.233589465088208580f, 0.233208590211508550f, + 0.232827706760394850f, + 0.232446814748872410f, 0.232065914190945020f, 0.231685005100616930f, + 0.231304087491893930f, + 0.230923161378780380f, 0.230542226775282770f, 0.230161283695406500f, + 0.229780332153157300f, + 0.229399372162542610f, 0.229018403737568290f, 0.228637426892242400f, + 0.228256441640571880f, + 0.227875447996564060f, 0.227494445974227850f, 0.227113435587570770f, + 0.226732416850602300f, + 0.226351389777330990f, 0.225970354381765690f, 0.225589310677916880f, + 0.225208258679793520f, + 0.224827198401406690f, 0.224446129856766040f, 0.224065053059883250f, + 0.223683968024768950f, + 0.223302874765434120f, 0.222921773295891380f, 0.222540663630151820f, + 0.222159545782228660f, + 0.221778419766134050f, 0.221397285595880480f, 0.221016143285482050f, + 0.220634992848951380f, + 0.220253834300303180f, 0.219872667653551100f, 0.219491492922709110f, + 0.219110310121792800f, + 0.218729119264816280f, 0.218347920365795780f, 0.217966713438746380f, + 0.217585498497683580f, + 0.217204275556624420f, 0.216823044629584520f, 0.216441805730581500f, + 0.216060558873631570f, + 0.215679304072752960f, 0.215298041341962870f, 0.214916770695278810f, + 0.214535492146719880f, + 0.214154205710303750f, 0.213772911400050090f, 0.213391609229977570f, + 0.213010299214105140f, + 0.212628981366453330f, 0.212247655701041290f, 0.211866322231890090f, + 0.211484980973019880f, + 0.211103631938451000f, 0.210722275142205480f, 0.210340910598303870f, + 0.209959538320768660f, + 0.209578158323621420f, 0.209196770620883960f, 0.208815375226579670f, + 0.208433972154730530f, + 0.208052561419360520f, 0.207671143034492080f, 0.207289717014149830f, + 0.206908283372357230f, + 0.206526842123138070f, 0.206145393280517730f, 0.205763936858520150f, + 0.205382472871171230f, + 0.205001001332495910f, 0.204619522256519300f, 0.204238035657268250f, + 0.203856541548768030f, + 0.203475039945045950f, 0.203093530860128300f, 0.202712014308041620f, + 0.202330490302814110f, + 0.201948958858472420f, 0.201567419989045200f, 0.201185873708560170f, + 0.200804320031045230f, + 0.200422758970529910f, 0.200041190541042220f, 0.199659614756612230f, + 0.199278031631268500f, + 0.198896441179041650f, 0.198514843413961220f, 0.198133238350057030f, + 0.197751626001360480f, + 0.197370006381901520f, 0.196988379505712050f, 0.196606745386822960f, + 0.196225104039265410f, + 0.195843455477072190f, 0.195461799714274460f, 0.195080136764905570f, + 0.194698466642997730f, + 0.194316789362583340f, 0.193935104937696560f, 0.193553413382369890f, + 0.193171714710637930f, + 0.192790008936534220f, 0.192408296074092570f, 0.192026576137348330f, + 0.191644849140335360f, + 0.191263115097089540f, 0.190881374021645320f, 0.190499625928039040f, + 0.190117870830306100f, + 0.189736108742482030f, 0.189354339678604100f, 0.188972563652707950f, + 0.188590780678831250f, + 0.188208990771010640f, 0.187827193943283040f, 0.187445390209686870f, + 0.187063579584259070f, + 0.186681762081038650f, 0.186299937714063470f, 0.185918106497371700f, + 0.185536268445003070f, + 0.185154423570995760f, 0.184772571889390000f, 0.184390713414225000f, + 0.184008848159540110f, + 0.183626976139376310f, 0.183245097367773090f, 0.182863211858771880f, + 0.182481319626412670f, + 0.182099420684737420f, 0.181717515047787020f, 0.181335602729602590f, + 0.180953683744226880f, + 0.180571758105701030f, 0.180189825828068250f, 0.179807886925370670f, + 0.179425941411650660f, + 0.179043989300952110f, 0.178662030607317450f, 0.178280065344791100f, + 0.177898093527416370f, + 0.177516115169236820f, 0.177134130284297610f, 0.176752138886642350f, + 0.176370140990316640f, + 0.175988136609365020f, 0.175606125757832240f, 0.175224108449764660f, + 0.174842084699207030f, + 0.174460054520206240f, 0.174078017926807490f, 0.173695974933058080f, + 0.173313925553004180f, + 0.172931869800692250f, 0.172549807690170230f, 0.172167739235484620f, + 0.171785664450683800f, + 0.171403583349815180f, 0.171021495946926340f, 0.170639402256066410f, + 0.170257302291283000f, + 0.169875196066625710f, 0.169493083596143100f, 0.169110964893883830f, + 0.168728839973898290f, + 0.168346708850235140f, 0.167964571536945220f, 0.167582428048078130f, + 0.167200278397683750f, + 0.166818122599813570f, 0.166435960668517400f, 0.166053792617847200f, + 0.165671618461853270f, + 0.165289438214587970f, 0.164907251890102520f, 0.164525059502448390f, + 0.164142861065678550f, + 0.163760656593844480f, 0.163378446100999640f, 0.162996229601196390f, + 0.162614007108487250f, + 0.162231778636926370f, 0.161849544200566300f, 0.161467303813461580f, + 0.161085057489665670f, + 0.160702805243232240f, 0.160320547088216470f, 0.159938283038672050f, + 0.159556013108654580f, + 0.159173737312218650f, 0.158791455663418930f, 0.158409168176311760f, + 0.158026874864951870f, + 0.157644575743395960f, 0.157262270825699210f, 0.156879960125918730f, + 0.156497643658110590f, + 0.156115321436331000f, 0.155732993474637760f, 0.155350659787087090f, + 0.154968320387737170f, + 0.154585975290645110f, 0.154203624509868190f, 0.153821268059465250f, + 0.153438905953493550f, + 0.153056538206012340f, 0.152674164831079730f, 0.152291785842754070f, + 0.151909401255095250f, + 0.151527011082161540f, 0.151144615338013210f, 0.150762214036709470f, + 0.150379807192309620f, + 0.149997394818874590f, 0.149614976930463660f, 0.149232553541138180f, + 0.148850124664957870f, + 0.148467690315984390f, 0.148085250508278370f, 0.147702805255900570f, + 0.147320354572913260f, + 0.146937898473377210f, 0.146555436971355090f, 0.146172970080908520f, + 0.145790497816099230f, + 0.145408020190990560f, 0.145025537219644170f, 0.144643048916123810f, + 0.144260555294492000f, + 0.143878056368811510f, 0.143495552153146630f, 0.143113042661560050f, + 0.142730527908116440f, + 0.142348007906879320f, 0.141965482671912420f, 0.141582952217280980f, + 0.141200416557048680f, + 0.140817875705281120f, 0.140435329676042390f, 0.140052778483398480f, + 0.139670222141414250f, + 0.139287660664154770f, 0.138905094065686600f, 0.138522522360074780f, + 0.138139945561386200f, + 0.137757363683686740f, 0.137374776741042340f, 0.136992184747520560f, + 0.136609587717187310f, + 0.136226985664110460f, 0.135844378602356760f, 0.135461766545993150f, + 0.135079149509088060f, + 0.134696527505708320f, 0.134313900549922760f, 0.133931268655799020f, + 0.133548631837404950f, + 0.133165990108809860f, 0.132783343484081580f, 0.132400691977289760f, + 0.132018035602502530f, + 0.131635374373789940f, 0.131252708305220960f, 0.130870037410864640f, + 0.130487361704791580f, + 0.130104681201070800f, 0.129721995913773260f, 0.129339305856968730f, + 0.128956611044727220f, + 0.128573911491120210f, 0.128191207210217570f, 0.127808498216091110f, + 0.127425784522811530f, + 0.127043066144449680f, 0.126660343095077900f, 0.126277615388766920f, + 0.125894883039589430f, + 0.125512146061616980f, 0.125129404468921260f, 0.124746658275575490f, + 0.124363907495651240f, + 0.123981152143222060f, 0.123598392232359880f, 0.123215627777138580f, + 0.122832858791630880f, + 0.122450085289909640f, 0.122067307286049230f, 0.121684524794122440f, + 0.121301737828203960f, + 0.120918946402367330f, 0.120536150530686250f, 0.120153350227235940f, + 0.119770545506089950f, + 0.119387736381323830f, 0.119004922867011920f, 0.118622104977228730f, + 0.118239282726050290f, + 0.117856456127550970f, 0.117473625195807100f, 0.117090789944893860f, + 0.116707950388886520f, + 0.116325106541861910f, 0.115942258417895240f, 0.115559406031063570f, + 0.115176549395442460f, + 0.114793688525109290f, 0.114410823434140360f, 0.114027954136612060f, + 0.113645080646602280f, + 0.113262202978187320f, 0.112879321145445350f, 0.112496435162453430f, + 0.112113545043288730f, + 0.111730650802029900f, 0.111347752452754000f, 0.110964850009539970f, + 0.110581943486465610f, + 0.110199032897608850f, 0.109816118257049110f, 0.109433199578864170f, + 0.109050276877133770f, + 0.108667350165936400f, 0.108284419459350770f, 0.107901484771457020f, + 0.107518546116333660f, + 0.107135603508061170f, 0.106752656960718350f, 0.106369706488385940f, + 0.105986752105143480f, + 0.105603793825070680f, 0.105220831662248700f, 0.104837865630757090f, + 0.104454895744677270f, + 0.104071922018089540f, 0.103688944465074300f, 0.103305963099713400f, + 0.102922977936087120f, + 0.102539988988277600f, 0.102156996270365800f, 0.101773999796432830f, + 0.101390999580561250f, + 0.101007995636832020f, 0.100624987979327970f, 0.100241976622130760f, + 0.099858961579322170f, + 0.099475942864985456f, 0.099092920493202258f, 0.098709894478056073f, + 0.098326864833628791f, + 0.097943831574004214f, 0.097560794713264939f, 0.097177754265493674f, + 0.096794710244774623f, + 0.096411662665190329f, 0.096028611540825232f, 0.095645556885762609f, + 0.095262498714085819f, + 0.094879437039879722f, 0.094496371877227495f, 0.094113303240214247f, + 0.093730231142923864f, + 0.093347155599440373f, 0.092964076623849271f, 0.092580994230234359f, + 0.092197908432681386f, + 0.091814819245274432f, 0.091431726682099479f, 0.091048630757241303f, + 0.090665531484784803f, + 0.090282428878816323f, 0.089899322953420582f, 0.089516213722684160f, + 0.089133101200692441f, + 0.088749985401530951f, 0.088366866339286629f, 0.087983744028044805f, + 0.087600618481892656f, + 0.087217489714916191f, 0.086834357741201490f, 0.086451222574836131f, + 0.086068084229906014f, + 0.085684942720498897f, 0.085301798060701386f, 0.084918650264600160f, + 0.084535499346283349f, + 0.084152345319837438f, 0.083769188199350780f, 0.083386027998910095f, + 0.083002864732603973f, + 0.082619698414519799f, 0.082236529058745025f, 0.081853356679368619f, + 0.081470181290477811f, + 0.081087002906161790f, 0.080703821540508452f, 0.080320637207605849f, + 0.079937449921543474f, + 0.079554259696409127f, 0.079171066546292510f, 0.078787870485282088f, + 0.078404671527466441f, + 0.078021469686935602f, 0.077638264977777913f, 0.077255057414083589f, + 0.076871847009941652f, + 0.076488633779441206f, 0.076105417736672773f, 0.075722198895725248f, + 0.075338977270689375f, + 0.074955752875654230f, 0.074572525724710764f, 0.074189295831948693f, + 0.073806063211457842f, + 0.073422827877329483f, 0.073039589843653177f, 0.072656349124520389f, + 0.072273105734021334f, + 0.071889859686246352f, 0.071506610995287156f, 0.071123359675233852f, + 0.070740105740178361f, + 0.070356849204211397f, 0.069973590081423773f, 0.069590328385907715f, + 0.069207064131753759f, + 0.068823797333054326f, 0.068440528003900616f, 0.068057256158383886f, + 0.067673981810596848f, + 0.067290704974630494f, 0.066907425664577733f, 0.066524143894529736f, + 0.066140859678579578f, + 0.065757573030819083f, 0.065374283965340146f, 0.064990992496236119f, + 0.064607698637598646f, + 0.064224402403521202f, 0.063841103808096086f, 0.063457802865415636f, + 0.063074499589573618f, + 0.062691193994662109f, 0.062307886094775049f, 0.061924575904005130f, + 0.061541263436445129f, + 0.061157948706189229f, 0.060774631727329942f, 0.060391312513961619f, + 0.060007991080177375f, + 0.059624667440070382f, 0.059241341607735261f, 0.058858013597264912f, + 0.058474683422754095f, + 0.058091351098295878f, 0.057708016637985186f, 0.057324680055915692f, + 0.056941341366181127f, + 0.056558000582876661f, 0.056174657720095743f, 0.055791312791933681f, + 0.055407965812484541f, + 0.055024616795842439f, 0.054641265756102911f, 0.054257912707359794f, + 0.053874557663708772f, + 0.053491200639244271f, 0.053107841648060788f, 0.052724480704254229f, + 0.052341117821918783f, + 0.051957753015150501f, 0.051574386298044173f, 0.051191017684694640f, + 0.050807647189198162f, + 0.050424274825649297f, 0.050040900608144430f, 0.049657524550778251f, + 0.049274146667647289f, + 0.048890766972846805f, 0.048507385480472134f, 0.048124002204620014f, + 0.047740617159385448f, + 0.047357230358865306f, 0.046973841817155179f, 0.046590451548350717f, + 0.046207059566548990f, + 0.045823665885845313f, 0.045440270520336883f, 0.045056873484119603f, + 0.044673474791289434f, + 0.044290074455943754f, 0.043906672492178188f, 0.043523268914090238f, + 0.043139863735776100f, + 0.042756456971332048f, 0.042373048634855741f, 0.041989638740443119f, + 0.041606227302191955f, + 0.041222814334198304f, 0.040839399850560058f, 0.040455983865373815f, + 0.040072566392736257f, + 0.039689147446745419f, 0.039305727041497644f, 0.038922305191091085f, + 0.038538881909622631f, + 0.038155457211189216f, 0.037772031109889144f, 0.037388603619819022f, + 0.037005174755077273f, + 0.036621744529761024f, 0.036238312957967478f, 0.035854880053795196f, + 0.035471445831341021f, + 0.035088010304703626f, 0.034704573487980395f, 0.034321135395268765f, + 0.033937696040667535f, + 0.033554255438273790f, 0.033170813602186440f, 0.032787370546502645f, + 0.032403926285321405f, + 0.032020480832740429f, 0.031637034202857461f, 0.031253586409771626f, + 0.030870137467580314f, + 0.030486687390382738f, 0.030103236192276818f, 0.029719783887360508f, + 0.029336330489733147f, + 0.028952876013492331f, 0.028569420472737472f, 0.028185963881566689f, + 0.027802506254078142f, + 0.027419047604371360f, 0.027035587946544135f, 0.026652127294696067f, + 0.026268665662925468f, + 0.025885203065330677f, 0.025501739516011413f, 0.025118275029065638f, + 0.024734809618593138f, + 0.024351343298691951f, 0.023967876083461924f, 0.023584407987001611f, + 0.023200939023409587f, + 0.022817469206785804f, 0.022433998551228459f, 0.022050527070837558f, + 0.021667054779711814f, + 0.021283581691949955f, 0.020900107821652084f, 0.020516633182916549f, + 0.020133157789843505f, + 0.019749681656531803f, 0.019366204797080316f, 0.018982727225589285f, + 0.018599248956157190f, + 0.018215770002884327f, 0.017832290379869671f, 0.017448810101212228f, + 0.017065329181012358f, + 0.016681847633368677f, 0.016298365472381587f, 0.015914882712149747f, + 0.015531399366773606f, + 0.015147915450352307f, 0.014764430976985016f, 0.014380945960772247f, + 0.013997460415812761f, + 0.013613974356207112f, 0.013230487796054543f, 0.012847000749454314f, + 0.012463513230507034f, + 0.012080025253311559f, 0.011696536831968529f, 0.011313047980577277f, + 0.010929558713237145f, + 0.010546069044048827f, 0.010162578987111254f, 0.009779088556525145f, + 0.009395597766389905f, + 0.009012106630804949f, 0.008628615163871038f, 0.008245123379687167f, + 0.007861631292354124f, + 0.007478138915970929f, 0.007094646264638386f, 0.006711153352455981f, + 0.006327660193523208f, + 0.005944166801940901f, 0.005560673191808128f, 0.005177179377225743f, + 0.004793685372293270f, + 0.004410191191110246f, 0.004026696847777542f, 0.003643202356394263f, + 0.003259707731061291f, + 0.002876212985878184f, 0.002492718134944503f, 0.002109223192361147f, + 0.001725728172227238f, + 0.001342233088643682f, 0.000958737955710053f, 0.000575242787525925f, + 0.000191747598192208f +}; + #endif + +/** + @brief Weights Table + */ + +/** + @par + Weights tables are generated using the formula :
weights[n] = e^(-j*n*pi/(2*N))
+ @par + C command to generate the table +
+  for(i = 0; i< N; i++)
+  { 
+    weights[(2*i)]   =  cos(i*c);
+    weights[(2*i)+1] = -sin(i*c);
+  } 
+ @par + where N is the Number of weights to be calculated and c is pi/(2*N) + @par + Converted the output to q15 format by multiplying with 2^31 and saturated if required. + @par + In the tables below the real and imaginary values are placed alternatively, hence the + array length is 2*N. + */ + +/** + @par + cosFactor tables are generated using the formula :
 cos_factors[n] = 2 * cos((2n+1)*pi/(4*N)) 
+ @par + C command to generate the table +
+  for (i = 0; i< N; i++)
+  {
+    cos_factors[i] = 2 * cos((2*i+1)*c/2);
+  } 
+ @par + where N is the number of factors to generate and c is pi/(2*N) + @par + Then converted to q15 format by multiplying with 2^31 and saturated if required. +*/ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128) + + const q15_t __ALIGNED(4) WeightsQ15_128[256] = { + (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7fe9, (q15_t)0xfb4a, + (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7f87, (q15_t)0xf505, + (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f09, (q15_t)0xf055, (q15_t)0x7ed5, (q15_t)0xeec7, + (q15_t)0x7e9d, (q15_t)0xed38, (q15_t)0x7e5f, (q15_t)0xebab, (q15_t)0x7e1d, (q15_t)0xea1e, (q15_t)0x7dd6, (q15_t)0xe893, + (q15_t)0x7d8a, (q15_t)0xe708, (q15_t)0x7d39, (q15_t)0xe57e, (q15_t)0x7ce3, (q15_t)0xe3f5, (q15_t)0x7c89, (q15_t)0xe26d, + (q15_t)0x7c29, (q15_t)0xe0e7, (q15_t)0x7bc5, (q15_t)0xdf61, (q15_t)0x7b5d, (q15_t)0xdddd, (q15_t)0x7aef, (q15_t)0xdc5a, + (q15_t)0x7a7d, (q15_t)0xdad8, (q15_t)0x7a05, (q15_t)0xd958, (q15_t)0x798a, (q15_t)0xd7da, (q15_t)0x7909, (q15_t)0xd65d, + (q15_t)0x7884, (q15_t)0xd4e1, (q15_t)0x77fa, (q15_t)0xd368, (q15_t)0x776c, (q15_t)0xd1ef, (q15_t)0x76d9, (q15_t)0xd079, + (q15_t)0x7641, (q15_t)0xcf05, (q15_t)0x75a5, (q15_t)0xcd92, (q15_t)0x7504, (q15_t)0xcc22, (q15_t)0x745f, (q15_t)0xcab3, + (q15_t)0x73b5, (q15_t)0xc946, (q15_t)0x7307, (q15_t)0xc7dc, (q15_t)0x7255, (q15_t)0xc674, (q15_t)0x719e, (q15_t)0xc50e, + (q15_t)0x70e2, (q15_t)0xc3aa, (q15_t)0x7023, (q15_t)0xc248, (q15_t)0x6f5f, (q15_t)0xc0e9, (q15_t)0x6e96, (q15_t)0xbf8d, + (q15_t)0x6dca, (q15_t)0xbe32, (q15_t)0x6cf9, (q15_t)0xbcdb, (q15_t)0x6c24, (q15_t)0xbb86, (q15_t)0x6b4a, (q15_t)0xba33, + (q15_t)0x6a6d, (q15_t)0xb8e4, (q15_t)0x698c, (q15_t)0xb797, (q15_t)0x68a6, (q15_t)0xb64c, (q15_t)0x67bd, (q15_t)0xb505, + (q15_t)0x66cf, (q15_t)0xb3c1, (q15_t)0x65dd, (q15_t)0xb27f, (q15_t)0x64e8, (q15_t)0xb141, (q15_t)0x63ef, (q15_t)0xb005, + (q15_t)0x62f2, (q15_t)0xaecd, (q15_t)0x61f1, (q15_t)0xad97, (q15_t)0x60ec, (q15_t)0xac65, (q15_t)0x5fe3, (q15_t)0xab36, + (q15_t)0x5ed7, (q15_t)0xaa0b, (q15_t)0x5dc7, (q15_t)0xa8e3, (q15_t)0x5cb4, (q15_t)0xa7be, (q15_t)0x5b9d, (q15_t)0xa69c, + (q15_t)0x5a82, (q15_t)0xa57e, (q15_t)0x5964, (q15_t)0xa463, (q15_t)0x5842, (q15_t)0xa34c, (q15_t)0x571d, (q15_t)0xa239, + (q15_t)0x55f5, (q15_t)0xa129, (q15_t)0x54ca, (q15_t)0xa01d, (q15_t)0x539b, (q15_t)0x9f14, (q15_t)0x5269, (q15_t)0x9e0f, + (q15_t)0x5133, (q15_t)0x9d0e, (q15_t)0x4ffb, (q15_t)0x9c11, (q15_t)0x4ebf, (q15_t)0x9b18, (q15_t)0x4d81, (q15_t)0x9a23, + (q15_t)0x4c3f, (q15_t)0x9931, (q15_t)0x4afb, (q15_t)0x9843, (q15_t)0x49b4, (q15_t)0x975a, (q15_t)0x4869, (q15_t)0x9674, + (q15_t)0x471c, (q15_t)0x9593, (q15_t)0x45cd, (q15_t)0x94b6, (q15_t)0x447a, (q15_t)0x93dc, (q15_t)0x4325, (q15_t)0x9307, + (q15_t)0x41ce, (q15_t)0x9236, (q15_t)0x4073, (q15_t)0x916a, (q15_t)0x3f17, (q15_t)0x90a1, (q15_t)0x3db8, (q15_t)0x8fdd, + (q15_t)0x3c56, (q15_t)0x8f1e, (q15_t)0x3af2, (q15_t)0x8e62, (q15_t)0x398c, (q15_t)0x8dab, (q15_t)0x3824, (q15_t)0x8cf9, + (q15_t)0x36ba, (q15_t)0x8c4b, (q15_t)0x354d, (q15_t)0x8ba1, (q15_t)0x33de, (q15_t)0x8afc, (q15_t)0x326e, (q15_t)0x8a5b, + (q15_t)0x30fb, (q15_t)0x89bf, (q15_t)0x2f87, (q15_t)0x8927, (q15_t)0x2e11, (q15_t)0x8894, (q15_t)0x2c98, (q15_t)0x8806, + (q15_t)0x2b1f, (q15_t)0x877c, (q15_t)0x29a3, (q15_t)0x86f7, (q15_t)0x2826, (q15_t)0x8676, (q15_t)0x26a8, (q15_t)0x85fb, + (q15_t)0x2528, (q15_t)0x8583, (q15_t)0x23a6, (q15_t)0x8511, (q15_t)0x2223, (q15_t)0x84a3, (q15_t)0x209f, (q15_t)0x843b, + (q15_t)0x1f19, (q15_t)0x83d7, (q15_t)0x1d93, (q15_t)0x8377, (q15_t)0x1c0b, (q15_t)0x831d, (q15_t)0x1a82, (q15_t)0x82c7, + (q15_t)0x18f8, (q15_t)0x8276, (q15_t)0x176d, (q15_t)0x822a, (q15_t)0x15e2, (q15_t)0x81e3, (q15_t)0x1455, (q15_t)0x81a1, + (q15_t)0x12c8, (q15_t)0x8163, (q15_t)0x1139, (q15_t)0x812b, (q15_t)0xfab, (q15_t)0x80f7, (q15_t)0xe1b, (q15_t)0x80c8, + (q15_t)0xc8b, (q15_t)0x809e, (q15_t)0xafb, (q15_t)0x8079, (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x7d9, (q15_t)0x803e, + (q15_t)0x647, (q15_t)0x8028, (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x324, (q15_t)0x800a, (q15_t)0x192, (q15_t)0x8003 +}; + const q15_t __ALIGNED(4) cos_factorsQ15_128[128] = { + (q15_t)0x7fff, (q15_t)0x7ffa, (q15_t)0x7ff0, (q15_t)0x7fe1, (q15_t)0x7fce, (q15_t)0x7fb5, (q15_t)0x7f97, (q15_t)0x7f75, + (q15_t)0x7f4d, (q15_t)0x7f21, (q15_t)0x7ef0, (q15_t)0x7eba, (q15_t)0x7e7f, (q15_t)0x7e3f, (q15_t)0x7dfa, (q15_t)0x7db0, + (q15_t)0x7d62, (q15_t)0x7d0f, (q15_t)0x7cb7, (q15_t)0x7c5a, (q15_t)0x7bf8, (q15_t)0x7b92, (q15_t)0x7b26, (q15_t)0x7ab6, + (q15_t)0x7a42, (q15_t)0x79c8, (q15_t)0x794a, (q15_t)0x78c7, (q15_t)0x7840, (q15_t)0x77b4, (q15_t)0x7723, (q15_t)0x768e, + (q15_t)0x75f4, (q15_t)0x7555, (q15_t)0x74b2, (q15_t)0x740b, (q15_t)0x735f, (q15_t)0x72af, (q15_t)0x71fa, (q15_t)0x7141, + (q15_t)0x7083, (q15_t)0x6fc1, (q15_t)0x6efb, (q15_t)0x6e30, (q15_t)0x6d62, (q15_t)0x6c8f, (q15_t)0x6bb8, (q15_t)0x6adc, + (q15_t)0x69fd, (q15_t)0x6919, (q15_t)0x6832, (q15_t)0x6746, (q15_t)0x6657, (q15_t)0x6563, (q15_t)0x646c, (q15_t)0x6371, + (q15_t)0x6271, (q15_t)0x616f, (q15_t)0x6068, (q15_t)0x5f5e, (q15_t)0x5e50, (q15_t)0x5d3e, (q15_t)0x5c29, (q15_t)0x5b10, + (q15_t)0x59f3, (q15_t)0x58d4, (q15_t)0x57b0, (q15_t)0x568a, (q15_t)0x5560, (q15_t)0x5433, (q15_t)0x5302, (q15_t)0x51ce, + (q15_t)0x5097, (q15_t)0x4f5e, (q15_t)0x4e21, (q15_t)0x4ce1, (q15_t)0x4b9e, (q15_t)0x4a58, (q15_t)0x490f, (q15_t)0x47c3, + (q15_t)0x4675, (q15_t)0x4524, (q15_t)0x43d0, (q15_t)0x427a, (q15_t)0x4121, (q15_t)0x3fc5, (q15_t)0x3e68, (q15_t)0x3d07, + (q15_t)0x3ba5, (q15_t)0x3a40, (q15_t)0x38d8, (q15_t)0x376f, (q15_t)0x3604, (q15_t)0x3496, (q15_t)0x3326, (q15_t)0x31b5, + (q15_t)0x3041, (q15_t)0x2ecc, (q15_t)0x2d55, (q15_t)0x2bdc, (q15_t)0x2a61, (q15_t)0x28e5, (q15_t)0x2767, (q15_t)0x25e8, + (q15_t)0x2467, (q15_t)0x22e5, (q15_t)0x2161, (q15_t)0x1fdc, (q15_t)0x1e56, (q15_t)0x1ccf, (q15_t)0x1b47, (q15_t)0x19bd, + (q15_t)0x1833, (q15_t)0x16a8, (q15_t)0x151b, (q15_t)0x138e, (q15_t)0x1201, (q15_t)0x1072, (q15_t)0xee3, (q15_t)0xd53, + (q15_t)0xbc3, (q15_t)0xa33, (q15_t)0x8a2, (q15_t)0x710, (q15_t)0x57f, (q15_t)0x3ed, (q15_t)0x25b, (q15_t)0xc9 +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512) + const q15_t __ALIGNED(4) WeightsQ15_512[1024] = { + (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xff9c, (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7ffe, (q15_t)0xfed3, + (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ffc, (q15_t)0xfe0a, (q15_t)0x7ffa, (q15_t)0xfda5, (q15_t)0x7ff8, (q15_t)0xfd41, + (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7ff3, (q15_t)0xfc78, (q15_t)0x7ff0, (q15_t)0xfc13, (q15_t)0x7fed, (q15_t)0xfbaf, + (q15_t)0x7fe9, (q15_t)0xfb4a, (q15_t)0x7fe5, (q15_t)0xfae6, (q15_t)0x7fe1, (q15_t)0xfa81, (q15_t)0x7fdd, (q15_t)0xfa1d, + (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fd3, (q15_t)0xf954, (q15_t)0x7fce, (q15_t)0xf8f0, (q15_t)0x7fc8, (q15_t)0xf88b, + (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fbc, (q15_t)0xf7c3, (q15_t)0x7fb5, (q15_t)0xf75e, (q15_t)0x7fae, (q15_t)0xf6fa, + (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7f9f, (q15_t)0xf632, (q15_t)0x7f97, (q15_t)0xf5cd, (q15_t)0x7f8f, (q15_t)0xf569, + (q15_t)0x7f87, (q15_t)0xf505, (q15_t)0x7f7e, (q15_t)0xf4a1, (q15_t)0x7f75, (q15_t)0xf43d, (q15_t)0x7f6b, (q15_t)0xf3d9, + (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f58, (q15_t)0xf311, (q15_t)0x7f4d, (q15_t)0xf2ad, (q15_t)0x7f43, (q15_t)0xf249, + (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f2d, (q15_t)0xf181, (q15_t)0x7f21, (q15_t)0xf11d, (q15_t)0x7f15, (q15_t)0xf0b9, + (q15_t)0x7f09, (q15_t)0xf055, (q15_t)0x7efd, (q15_t)0xeff2, (q15_t)0x7ef0, (q15_t)0xef8e, (q15_t)0x7ee3, (q15_t)0xef2a, + (q15_t)0x7ed5, (q15_t)0xeec7, (q15_t)0x7ec8, (q15_t)0xee63, (q15_t)0x7eba, (q15_t)0xedff, (q15_t)0x7eab, (q15_t)0xed9c, + (q15_t)0x7e9d, (q15_t)0xed38, (q15_t)0x7e8e, (q15_t)0xecd5, (q15_t)0x7e7f, (q15_t)0xec72, (q15_t)0x7e6f, (q15_t)0xec0e, + (q15_t)0x7e5f, (q15_t)0xebab, (q15_t)0x7e4f, (q15_t)0xeb48, (q15_t)0x7e3f, (q15_t)0xeae5, (q15_t)0x7e2e, (q15_t)0xea81, + (q15_t)0x7e1d, (q15_t)0xea1e, (q15_t)0x7e0c, (q15_t)0xe9bb, (q15_t)0x7dfa, (q15_t)0xe958, (q15_t)0x7de8, (q15_t)0xe8f6, + (q15_t)0x7dd6, (q15_t)0xe893, (q15_t)0x7dc3, (q15_t)0xe830, (q15_t)0x7db0, (q15_t)0xe7cd, (q15_t)0x7d9d, (q15_t)0xe76a, + (q15_t)0x7d8a, (q15_t)0xe708, (q15_t)0x7d76, (q15_t)0xe6a5, (q15_t)0x7d62, (q15_t)0xe643, (q15_t)0x7d4e, (q15_t)0xe5e0, + (q15_t)0x7d39, (q15_t)0xe57e, (q15_t)0x7d24, (q15_t)0xe51c, (q15_t)0x7d0f, (q15_t)0xe4b9, (q15_t)0x7cf9, (q15_t)0xe457, + (q15_t)0x7ce3, (q15_t)0xe3f5, (q15_t)0x7ccd, (q15_t)0xe393, (q15_t)0x7cb7, (q15_t)0xe331, (q15_t)0x7ca0, (q15_t)0xe2cf, + (q15_t)0x7c89, (q15_t)0xe26d, (q15_t)0x7c71, (q15_t)0xe20b, (q15_t)0x7c5a, (q15_t)0xe1aa, (q15_t)0x7c42, (q15_t)0xe148, + (q15_t)0x7c29, (q15_t)0xe0e7, (q15_t)0x7c11, (q15_t)0xe085, (q15_t)0x7bf8, (q15_t)0xe024, (q15_t)0x7bdf, (q15_t)0xdfc2, + (q15_t)0x7bc5, (q15_t)0xdf61, (q15_t)0x7bac, (q15_t)0xdf00, (q15_t)0x7b92, (q15_t)0xde9f, (q15_t)0x7b77, (q15_t)0xde3e, + (q15_t)0x7b5d, (q15_t)0xdddd, (q15_t)0x7b42, (q15_t)0xdd7c, (q15_t)0x7b26, (q15_t)0xdd1b, (q15_t)0x7b0b, (q15_t)0xdcbb, + (q15_t)0x7aef, (q15_t)0xdc5a, (q15_t)0x7ad3, (q15_t)0xdbf9, (q15_t)0x7ab6, (q15_t)0xdb99, (q15_t)0x7a9a, (q15_t)0xdb39, + (q15_t)0x7a7d, (q15_t)0xdad8, (q15_t)0x7a5f, (q15_t)0xda78, (q15_t)0x7a42, (q15_t)0xda18, (q15_t)0x7a24, (q15_t)0xd9b8, + (q15_t)0x7a05, (q15_t)0xd958, (q15_t)0x79e7, (q15_t)0xd8f9, (q15_t)0x79c8, (q15_t)0xd899, (q15_t)0x79a9, (q15_t)0xd839, + (q15_t)0x798a, (q15_t)0xd7da, (q15_t)0x796a, (q15_t)0xd77a, (q15_t)0x794a, (q15_t)0xd71b, (q15_t)0x792a, (q15_t)0xd6bc, + (q15_t)0x7909, (q15_t)0xd65d, (q15_t)0x78e8, (q15_t)0xd5fe, (q15_t)0x78c7, (q15_t)0xd59f, (q15_t)0x78a6, (q15_t)0xd540, + (q15_t)0x7884, (q15_t)0xd4e1, (q15_t)0x7862, (q15_t)0xd483, (q15_t)0x7840, (q15_t)0xd424, (q15_t)0x781d, (q15_t)0xd3c6, + (q15_t)0x77fa, (q15_t)0xd368, (q15_t)0x77d7, (q15_t)0xd309, (q15_t)0x77b4, (q15_t)0xd2ab, (q15_t)0x7790, (q15_t)0xd24d, + (q15_t)0x776c, (q15_t)0xd1ef, (q15_t)0x7747, (q15_t)0xd192, (q15_t)0x7723, (q15_t)0xd134, (q15_t)0x76fe, (q15_t)0xd0d7, + (q15_t)0x76d9, (q15_t)0xd079, (q15_t)0x76b3, (q15_t)0xd01c, (q15_t)0x768e, (q15_t)0xcfbf, (q15_t)0x7668, (q15_t)0xcf62, + (q15_t)0x7641, (q15_t)0xcf05, (q15_t)0x761b, (q15_t)0xcea8, (q15_t)0x75f4, (q15_t)0xce4b, (q15_t)0x75cc, (q15_t)0xcdef, + (q15_t)0x75a5, (q15_t)0xcd92, (q15_t)0x757d, (q15_t)0xcd36, (q15_t)0x7555, (q15_t)0xccda, (q15_t)0x752d, (q15_t)0xcc7e, + (q15_t)0x7504, (q15_t)0xcc22, (q15_t)0x74db, (q15_t)0xcbc6, (q15_t)0x74b2, (q15_t)0xcb6a, (q15_t)0x7489, (q15_t)0xcb0e, + (q15_t)0x745f, (q15_t)0xcab3, (q15_t)0x7435, (q15_t)0xca58, (q15_t)0x740b, (q15_t)0xc9fc, (q15_t)0x73e0, (q15_t)0xc9a1, + (q15_t)0x73b5, (q15_t)0xc946, (q15_t)0x738a, (q15_t)0xc8ec, (q15_t)0x735f, (q15_t)0xc891, (q15_t)0x7333, (q15_t)0xc836, + (q15_t)0x7307, (q15_t)0xc7dc, (q15_t)0x72db, (q15_t)0xc782, (q15_t)0x72af, (q15_t)0xc728, (q15_t)0x7282, (q15_t)0xc6ce, + (q15_t)0x7255, (q15_t)0xc674, (q15_t)0x7227, (q15_t)0xc61a, (q15_t)0x71fa, (q15_t)0xc5c0, (q15_t)0x71cc, (q15_t)0xc567, + (q15_t)0x719e, (q15_t)0xc50e, (q15_t)0x716f, (q15_t)0xc4b4, (q15_t)0x7141, (q15_t)0xc45b, (q15_t)0x7112, (q15_t)0xc403, + (q15_t)0x70e2, (q15_t)0xc3aa, (q15_t)0x70b3, (q15_t)0xc351, (q15_t)0x7083, (q15_t)0xc2f9, (q15_t)0x7053, (q15_t)0xc2a0, + (q15_t)0x7023, (q15_t)0xc248, (q15_t)0x6ff2, (q15_t)0xc1f0, (q15_t)0x6fc1, (q15_t)0xc198, (q15_t)0x6f90, (q15_t)0xc141, + (q15_t)0x6f5f, (q15_t)0xc0e9, (q15_t)0x6f2d, (q15_t)0xc092, (q15_t)0x6efb, (q15_t)0xc03b, (q15_t)0x6ec9, (q15_t)0xbfe3, + (q15_t)0x6e96, (q15_t)0xbf8d, (q15_t)0x6e63, (q15_t)0xbf36, (q15_t)0x6e30, (q15_t)0xbedf, (q15_t)0x6dfd, (q15_t)0xbe89, + (q15_t)0x6dca, (q15_t)0xbe32, (q15_t)0x6d96, (q15_t)0xbddc, (q15_t)0x6d62, (q15_t)0xbd86, (q15_t)0x6d2d, (q15_t)0xbd30, + (q15_t)0x6cf9, (q15_t)0xbcdb, (q15_t)0x6cc4, (q15_t)0xbc85, (q15_t)0x6c8f, (q15_t)0xbc30, (q15_t)0x6c59, (q15_t)0xbbdb, + (q15_t)0x6c24, (q15_t)0xbb86, (q15_t)0x6bee, (q15_t)0xbb31, (q15_t)0x6bb8, (q15_t)0xbadc, (q15_t)0x6b81, (q15_t)0xba88, + (q15_t)0x6b4a, (q15_t)0xba33, (q15_t)0x6b13, (q15_t)0xb9df, (q15_t)0x6adc, (q15_t)0xb98b, (q15_t)0x6aa5, (q15_t)0xb937, + (q15_t)0x6a6d, (q15_t)0xb8e4, (q15_t)0x6a35, (q15_t)0xb890, (q15_t)0x69fd, (q15_t)0xb83d, (q15_t)0x69c4, (q15_t)0xb7ea, + (q15_t)0x698c, (q15_t)0xb797, (q15_t)0x6953, (q15_t)0xb744, (q15_t)0x6919, (q15_t)0xb6f1, (q15_t)0x68e0, (q15_t)0xb69f, + (q15_t)0x68a6, (q15_t)0xb64c, (q15_t)0x686c, (q15_t)0xb5fa, (q15_t)0x6832, (q15_t)0xb5a8, (q15_t)0x67f7, (q15_t)0xb557, + (q15_t)0x67bd, (q15_t)0xb505, (q15_t)0x6782, (q15_t)0xb4b4, (q15_t)0x6746, (q15_t)0xb462, (q15_t)0x670b, (q15_t)0xb411, + (q15_t)0x66cf, (q15_t)0xb3c1, (q15_t)0x6693, (q15_t)0xb370, (q15_t)0x6657, (q15_t)0xb31f, (q15_t)0x661a, (q15_t)0xb2cf, + (q15_t)0x65dd, (q15_t)0xb27f, (q15_t)0x65a0, (q15_t)0xb22f, (q15_t)0x6563, (q15_t)0xb1df, (q15_t)0x6526, (q15_t)0xb190, + (q15_t)0x64e8, (q15_t)0xb141, (q15_t)0x64aa, (q15_t)0xb0f1, (q15_t)0x646c, (q15_t)0xb0a2, (q15_t)0x642d, (q15_t)0xb054, + (q15_t)0x63ef, (q15_t)0xb005, (q15_t)0x63b0, (q15_t)0xafb7, (q15_t)0x6371, (q15_t)0xaf69, (q15_t)0x6331, (q15_t)0xaf1b, + (q15_t)0x62f2, (q15_t)0xaecd, (q15_t)0x62b2, (q15_t)0xae7f, (q15_t)0x6271, (q15_t)0xae32, (q15_t)0x6231, (q15_t)0xade4, + (q15_t)0x61f1, (q15_t)0xad97, (q15_t)0x61b0, (q15_t)0xad4b, (q15_t)0x616f, (q15_t)0xacfe, (q15_t)0x612d, (q15_t)0xacb2, + (q15_t)0x60ec, (q15_t)0xac65, (q15_t)0x60aa, (q15_t)0xac19, (q15_t)0x6068, (q15_t)0xabcd, (q15_t)0x6026, (q15_t)0xab82, + (q15_t)0x5fe3, (q15_t)0xab36, (q15_t)0x5fa0, (q15_t)0xaaeb, (q15_t)0x5f5e, (q15_t)0xaaa0, (q15_t)0x5f1a, (q15_t)0xaa55, + (q15_t)0x5ed7, (q15_t)0xaa0b, (q15_t)0x5e93, (q15_t)0xa9c0, (q15_t)0x5e50, (q15_t)0xa976, (q15_t)0x5e0b, (q15_t)0xa92c, + (q15_t)0x5dc7, (q15_t)0xa8e3, (q15_t)0x5d83, (q15_t)0xa899, (q15_t)0x5d3e, (q15_t)0xa850, (q15_t)0x5cf9, (q15_t)0xa807, + (q15_t)0x5cb4, (q15_t)0xa7be, (q15_t)0x5c6e, (q15_t)0xa775, (q15_t)0x5c29, (q15_t)0xa72c, (q15_t)0x5be3, (q15_t)0xa6e4, + (q15_t)0x5b9d, (q15_t)0xa69c, (q15_t)0x5b56, (q15_t)0xa654, (q15_t)0x5b10, (q15_t)0xa60d, (q15_t)0x5ac9, (q15_t)0xa5c5, + (q15_t)0x5a82, (q15_t)0xa57e, (q15_t)0x5a3b, (q15_t)0xa537, (q15_t)0x59f3, (q15_t)0xa4f0, (q15_t)0x59ac, (q15_t)0xa4aa, + (q15_t)0x5964, (q15_t)0xa463, (q15_t)0x591c, (q15_t)0xa41d, (q15_t)0x58d4, (q15_t)0xa3d7, (q15_t)0x588b, (q15_t)0xa392, + (q15_t)0x5842, (q15_t)0xa34c, (q15_t)0x57f9, (q15_t)0xa307, (q15_t)0x57b0, (q15_t)0xa2c2, (q15_t)0x5767, (q15_t)0xa27d, + (q15_t)0x571d, (q15_t)0xa239, (q15_t)0x56d4, (q15_t)0xa1f5, (q15_t)0x568a, (q15_t)0xa1b0, (q15_t)0x5640, (q15_t)0xa16d, + (q15_t)0x55f5, (q15_t)0xa129, (q15_t)0x55ab, (q15_t)0xa0e6, (q15_t)0x5560, (q15_t)0xa0a2, (q15_t)0x5515, (q15_t)0xa060, + (q15_t)0x54ca, (q15_t)0xa01d, (q15_t)0x547e, (q15_t)0x9fda, (q15_t)0x5433, (q15_t)0x9f98, (q15_t)0x53e7, (q15_t)0x9f56, + (q15_t)0x539b, (q15_t)0x9f14, (q15_t)0x534e, (q15_t)0x9ed3, (q15_t)0x5302, (q15_t)0x9e91, (q15_t)0x52b5, (q15_t)0x9e50, + (q15_t)0x5269, (q15_t)0x9e0f, (q15_t)0x521c, (q15_t)0x9dcf, (q15_t)0x51ce, (q15_t)0x9d8f, (q15_t)0x5181, (q15_t)0x9d4e, + (q15_t)0x5133, (q15_t)0x9d0e, (q15_t)0x50e5, (q15_t)0x9ccf, (q15_t)0x5097, (q15_t)0x9c8f, (q15_t)0x5049, (q15_t)0x9c50, + (q15_t)0x4ffb, (q15_t)0x9c11, (q15_t)0x4fac, (q15_t)0x9bd3, (q15_t)0x4f5e, (q15_t)0x9b94, (q15_t)0x4f0f, (q15_t)0x9b56, + (q15_t)0x4ebf, (q15_t)0x9b18, (q15_t)0x4e70, (q15_t)0x9ada, (q15_t)0x4e21, (q15_t)0x9a9d, (q15_t)0x4dd1, (q15_t)0x9a60, + (q15_t)0x4d81, (q15_t)0x9a23, (q15_t)0x4d31, (q15_t)0x99e6, (q15_t)0x4ce1, (q15_t)0x99a9, (q15_t)0x4c90, (q15_t)0x996d, + (q15_t)0x4c3f, (q15_t)0x9931, (q15_t)0x4bef, (q15_t)0x98f5, (q15_t)0x4b9e, (q15_t)0x98ba, (q15_t)0x4b4c, (q15_t)0x987e, + (q15_t)0x4afb, (q15_t)0x9843, (q15_t)0x4aa9, (q15_t)0x9809, (q15_t)0x4a58, (q15_t)0x97ce, (q15_t)0x4a06, (q15_t)0x9794, + (q15_t)0x49b4, (q15_t)0x975a, (q15_t)0x4961, (q15_t)0x9720, (q15_t)0x490f, (q15_t)0x96e7, (q15_t)0x48bc, (q15_t)0x96ad, + (q15_t)0x4869, (q15_t)0x9674, (q15_t)0x4816, (q15_t)0x963c, (q15_t)0x47c3, (q15_t)0x9603, (q15_t)0x4770, (q15_t)0x95cb, + (q15_t)0x471c, (q15_t)0x9593, (q15_t)0x46c9, (q15_t)0x955b, (q15_t)0x4675, (q15_t)0x9524, (q15_t)0x4621, (q15_t)0x94ed, + (q15_t)0x45cd, (q15_t)0x94b6, (q15_t)0x4578, (q15_t)0x947f, (q15_t)0x4524, (q15_t)0x9448, (q15_t)0x44cf, (q15_t)0x9412, + (q15_t)0x447a, (q15_t)0x93dc, (q15_t)0x4425, (q15_t)0x93a7, (q15_t)0x43d0, (q15_t)0x9371, (q15_t)0x437b, (q15_t)0x933c, + (q15_t)0x4325, (q15_t)0x9307, (q15_t)0x42d0, (q15_t)0x92d3, (q15_t)0x427a, (q15_t)0x929e, (q15_t)0x4224, (q15_t)0x926a, + (q15_t)0x41ce, (q15_t)0x9236, (q15_t)0x4177, (q15_t)0x9203, (q15_t)0x4121, (q15_t)0x91d0, (q15_t)0x40ca, (q15_t)0x919d, + (q15_t)0x4073, (q15_t)0x916a, (q15_t)0x401d, (q15_t)0x9137, (q15_t)0x3fc5, (q15_t)0x9105, (q15_t)0x3f6e, (q15_t)0x90d3, + (q15_t)0x3f17, (q15_t)0x90a1, (q15_t)0x3ebf, (q15_t)0x9070, (q15_t)0x3e68, (q15_t)0x903f, (q15_t)0x3e10, (q15_t)0x900e, + (q15_t)0x3db8, (q15_t)0x8fdd, (q15_t)0x3d60, (q15_t)0x8fad, (q15_t)0x3d07, (q15_t)0x8f7d, (q15_t)0x3caf, (q15_t)0x8f4d, + (q15_t)0x3c56, (q15_t)0x8f1e, (q15_t)0x3bfd, (q15_t)0x8eee, (q15_t)0x3ba5, (q15_t)0x8ebf, (q15_t)0x3b4c, (q15_t)0x8e91, + (q15_t)0x3af2, (q15_t)0x8e62, (q15_t)0x3a99, (q15_t)0x8e34, (q15_t)0x3a40, (q15_t)0x8e06, (q15_t)0x39e6, (q15_t)0x8dd9, + (q15_t)0x398c, (q15_t)0x8dab, (q15_t)0x3932, (q15_t)0x8d7e, (q15_t)0x38d8, (q15_t)0x8d51, (q15_t)0x387e, (q15_t)0x8d25, + (q15_t)0x3824, (q15_t)0x8cf9, (q15_t)0x37ca, (q15_t)0x8ccd, (q15_t)0x376f, (q15_t)0x8ca1, (q15_t)0x3714, (q15_t)0x8c76, + (q15_t)0x36ba, (q15_t)0x8c4b, (q15_t)0x365f, (q15_t)0x8c20, (q15_t)0x3604, (q15_t)0x8bf5, (q15_t)0x35a8, (q15_t)0x8bcb, + (q15_t)0x354d, (q15_t)0x8ba1, (q15_t)0x34f2, (q15_t)0x8b77, (q15_t)0x3496, (q15_t)0x8b4e, (q15_t)0x343a, (q15_t)0x8b25, + (q15_t)0x33de, (q15_t)0x8afc, (q15_t)0x3382, (q15_t)0x8ad3, (q15_t)0x3326, (q15_t)0x8aab, (q15_t)0x32ca, (q15_t)0x8a83, + (q15_t)0x326e, (q15_t)0x8a5b, (q15_t)0x3211, (q15_t)0x8a34, (q15_t)0x31b5, (q15_t)0x8a0c, (q15_t)0x3158, (q15_t)0x89e5, + (q15_t)0x30fb, (q15_t)0x89bf, (q15_t)0x309e, (q15_t)0x8998, (q15_t)0x3041, (q15_t)0x8972, (q15_t)0x2fe4, (q15_t)0x894d, + (q15_t)0x2f87, (q15_t)0x8927, (q15_t)0x2f29, (q15_t)0x8902, (q15_t)0x2ecc, (q15_t)0x88dd, (q15_t)0x2e6e, (q15_t)0x88b9, + (q15_t)0x2e11, (q15_t)0x8894, (q15_t)0x2db3, (q15_t)0x8870, (q15_t)0x2d55, (q15_t)0x884c, (q15_t)0x2cf7, (q15_t)0x8829, + (q15_t)0x2c98, (q15_t)0x8806, (q15_t)0x2c3a, (q15_t)0x87e3, (q15_t)0x2bdc, (q15_t)0x87c0, (q15_t)0x2b7d, (q15_t)0x879e, + (q15_t)0x2b1f, (q15_t)0x877c, (q15_t)0x2ac0, (q15_t)0x875a, (q15_t)0x2a61, (q15_t)0x8739, (q15_t)0x2a02, (q15_t)0x8718, + (q15_t)0x29a3, (q15_t)0x86f7, (q15_t)0x2944, (q15_t)0x86d6, (q15_t)0x28e5, (q15_t)0x86b6, (q15_t)0x2886, (q15_t)0x8696, + (q15_t)0x2826, (q15_t)0x8676, (q15_t)0x27c7, (q15_t)0x8657, (q15_t)0x2767, (q15_t)0x8638, (q15_t)0x2707, (q15_t)0x8619, + (q15_t)0x26a8, (q15_t)0x85fb, (q15_t)0x2648, (q15_t)0x85dc, (q15_t)0x25e8, (q15_t)0x85be, (q15_t)0x2588, (q15_t)0x85a1, + (q15_t)0x2528, (q15_t)0x8583, (q15_t)0x24c7, (q15_t)0x8566, (q15_t)0x2467, (q15_t)0x854a, (q15_t)0x2407, (q15_t)0x852d, + (q15_t)0x23a6, (q15_t)0x8511, (q15_t)0x2345, (q15_t)0x84f5, (q15_t)0x22e5, (q15_t)0x84da, (q15_t)0x2284, (q15_t)0x84be, + (q15_t)0x2223, (q15_t)0x84a3, (q15_t)0x21c2, (q15_t)0x8489, (q15_t)0x2161, (q15_t)0x846e, (q15_t)0x2100, (q15_t)0x8454, + (q15_t)0x209f, (q15_t)0x843b, (q15_t)0x203e, (q15_t)0x8421, (q15_t)0x1fdc, (q15_t)0x8408, (q15_t)0x1f7b, (q15_t)0x83ef, + (q15_t)0x1f19, (q15_t)0x83d7, (q15_t)0x1eb8, (q15_t)0x83be, (q15_t)0x1e56, (q15_t)0x83a6, (q15_t)0x1df5, (q15_t)0x838f, + (q15_t)0x1d93, (q15_t)0x8377, (q15_t)0x1d31, (q15_t)0x8360, (q15_t)0x1ccf, (q15_t)0x8349, (q15_t)0x1c6d, (q15_t)0x8333, + (q15_t)0x1c0b, (q15_t)0x831d, (q15_t)0x1ba9, (q15_t)0x8307, (q15_t)0x1b47, (q15_t)0x82f1, (q15_t)0x1ae4, (q15_t)0x82dc, + (q15_t)0x1a82, (q15_t)0x82c7, (q15_t)0x1a20, (q15_t)0x82b2, (q15_t)0x19bd, (q15_t)0x829e, (q15_t)0x195b, (q15_t)0x828a, + (q15_t)0x18f8, (q15_t)0x8276, (q15_t)0x1896, (q15_t)0x8263, (q15_t)0x1833, (q15_t)0x8250, (q15_t)0x17d0, (q15_t)0x823d, + (q15_t)0x176d, (q15_t)0x822a, (q15_t)0x170a, (q15_t)0x8218, (q15_t)0x16a8, (q15_t)0x8206, (q15_t)0x1645, (q15_t)0x81f4, + (q15_t)0x15e2, (q15_t)0x81e3, (q15_t)0x157f, (q15_t)0x81d2, (q15_t)0x151b, (q15_t)0x81c1, (q15_t)0x14b8, (q15_t)0x81b1, + (q15_t)0x1455, (q15_t)0x81a1, (q15_t)0x13f2, (q15_t)0x8191, (q15_t)0x138e, (q15_t)0x8181, (q15_t)0x132b, (q15_t)0x8172, + (q15_t)0x12c8, (q15_t)0x8163, (q15_t)0x1264, (q15_t)0x8155, (q15_t)0x1201, (q15_t)0x8146, (q15_t)0x119d, (q15_t)0x8138, + (q15_t)0x1139, (q15_t)0x812b, (q15_t)0x10d6, (q15_t)0x811d, (q15_t)0x1072, (q15_t)0x8110, (q15_t)0x100e, (q15_t)0x8103, + (q15_t)0xfab, (q15_t)0x80f7, (q15_t)0xf47, (q15_t)0x80eb, (q15_t)0xee3, (q15_t)0x80df, (q15_t)0xe7f, (q15_t)0x80d3, + (q15_t)0xe1b, (q15_t)0x80c8, (q15_t)0xdb7, (q15_t)0x80bd, (q15_t)0xd53, (q15_t)0x80b3, (q15_t)0xcef, (q15_t)0x80a8, + (q15_t)0xc8b, (q15_t)0x809e, (q15_t)0xc27, (q15_t)0x8095, (q15_t)0xbc3, (q15_t)0x808b, (q15_t)0xb5f, (q15_t)0x8082, + (q15_t)0xafb, (q15_t)0x8079, (q15_t)0xa97, (q15_t)0x8071, (q15_t)0xa33, (q15_t)0x8069, (q15_t)0x9ce, (q15_t)0x8061, + (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x906, (q15_t)0x8052, (q15_t)0x8a2, (q15_t)0x804b, (q15_t)0x83d, (q15_t)0x8044, + (q15_t)0x7d9, (q15_t)0x803e, (q15_t)0x775, (q15_t)0x8038, (q15_t)0x710, (q15_t)0x8032, (q15_t)0x6ac, (q15_t)0x802d, + (q15_t)0x647, (q15_t)0x8028, (q15_t)0x5e3, (q15_t)0x8023, (q15_t)0x57f, (q15_t)0x801f, (q15_t)0x51a, (q15_t)0x801b, + (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x451, (q15_t)0x8013, (q15_t)0x3ed, (q15_t)0x8010, (q15_t)0x388, (q15_t)0x800d, + (q15_t)0x324, (q15_t)0x800a, (q15_t)0x2bf, (q15_t)0x8008, (q15_t)0x25b, (q15_t)0x8006, (q15_t)0x1f6, (q15_t)0x8004, + (q15_t)0x192, (q15_t)0x8003, (q15_t)0x12d, (q15_t)0x8002, (q15_t)0xc9, (q15_t)0x8001, (q15_t)0x64, (q15_t)0x8001 +}; + + const q15_t __ALIGNED(4) cos_factorsQ15_512[512] = { + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7ffe, (q15_t)0x7ffc, (q15_t)0x7ffb, (q15_t)0x7ff9, (q15_t)0x7ff7, + (q15_t)0x7ff4, (q15_t)0x7ff2, (q15_t)0x7fee, (q15_t)0x7feb, (q15_t)0x7fe7, (q15_t)0x7fe3, (q15_t)0x7fdf, (q15_t)0x7fda, + (q15_t)0x7fd6, (q15_t)0x7fd0, (q15_t)0x7fcb, (q15_t)0x7fc5, (q15_t)0x7fbf, (q15_t)0x7fb8, (q15_t)0x7fb1, (q15_t)0x7faa, + (q15_t)0x7fa3, (q15_t)0x7f9b, (q15_t)0x7f93, (q15_t)0x7f8b, (q15_t)0x7f82, (q15_t)0x7f79, (q15_t)0x7f70, (q15_t)0x7f67, + (q15_t)0x7f5d, (q15_t)0x7f53, (q15_t)0x7f48, (q15_t)0x7f3d, (q15_t)0x7f32, (q15_t)0x7f27, (q15_t)0x7f1b, (q15_t)0x7f0f, + (q15_t)0x7f03, (q15_t)0x7ef6, (q15_t)0x7ee9, (q15_t)0x7edc, (q15_t)0x7ecf, (q15_t)0x7ec1, (q15_t)0x7eb3, (q15_t)0x7ea4, + (q15_t)0x7e95, (q15_t)0x7e86, (q15_t)0x7e77, (q15_t)0x7e67, (q15_t)0x7e57, (q15_t)0x7e47, (q15_t)0x7e37, (q15_t)0x7e26, + (q15_t)0x7e14, (q15_t)0x7e03, (q15_t)0x7df1, (q15_t)0x7ddf, (q15_t)0x7dcd, (q15_t)0x7dba, (q15_t)0x7da7, (q15_t)0x7d94, + (q15_t)0x7d80, (q15_t)0x7d6c, (q15_t)0x7d58, (q15_t)0x7d43, (q15_t)0x7d2f, (q15_t)0x7d19, (q15_t)0x7d04, (q15_t)0x7cee, + (q15_t)0x7cd8, (q15_t)0x7cc2, (q15_t)0x7cab, (q15_t)0x7c94, (q15_t)0x7c7d, (q15_t)0x7c66, (q15_t)0x7c4e, (q15_t)0x7c36, + (q15_t)0x7c1d, (q15_t)0x7c05, (q15_t)0x7beb, (q15_t)0x7bd2, (q15_t)0x7bb9, (q15_t)0x7b9f, (q15_t)0x7b84, (q15_t)0x7b6a, + (q15_t)0x7b4f, (q15_t)0x7b34, (q15_t)0x7b19, (q15_t)0x7afd, (q15_t)0x7ae1, (q15_t)0x7ac5, (q15_t)0x7aa8, (q15_t)0x7a8b, + (q15_t)0x7a6e, (q15_t)0x7a50, (q15_t)0x7a33, (q15_t)0x7a15, (q15_t)0x79f6, (q15_t)0x79d8, (q15_t)0x79b9, (q15_t)0x7999, + (q15_t)0x797a, (q15_t)0x795a, (q15_t)0x793a, (q15_t)0x7919, (q15_t)0x78f9, (q15_t)0x78d8, (q15_t)0x78b6, (q15_t)0x7895, + (q15_t)0x7873, (q15_t)0x7851, (q15_t)0x782e, (q15_t)0x780c, (q15_t)0x77e9, (q15_t)0x77c5, (q15_t)0x77a2, (q15_t)0x777e, + (q15_t)0x775a, (q15_t)0x7735, (q15_t)0x7710, (q15_t)0x76eb, (q15_t)0x76c6, (q15_t)0x76a0, (q15_t)0x767b, (q15_t)0x7654, + (q15_t)0x762e, (q15_t)0x7607, (q15_t)0x75e0, (q15_t)0x75b9, (q15_t)0x7591, (q15_t)0x7569, (q15_t)0x7541, (q15_t)0x7519, + (q15_t)0x74f0, (q15_t)0x74c7, (q15_t)0x749e, (q15_t)0x7474, (q15_t)0x744a, (q15_t)0x7420, (q15_t)0x73f6, (q15_t)0x73cb, + (q15_t)0x73a0, (q15_t)0x7375, (q15_t)0x7349, (q15_t)0x731d, (q15_t)0x72f1, (q15_t)0x72c5, (q15_t)0x7298, (q15_t)0x726b, + (q15_t)0x723e, (q15_t)0x7211, (q15_t)0x71e3, (q15_t)0x71b5, (q15_t)0x7186, (q15_t)0x7158, (q15_t)0x7129, (q15_t)0x70fa, + (q15_t)0x70cb, (q15_t)0x709b, (q15_t)0x706b, (q15_t)0x703b, (q15_t)0x700a, (q15_t)0x6fda, (q15_t)0x6fa9, (q15_t)0x6f77, + (q15_t)0x6f46, (q15_t)0x6f14, (q15_t)0x6ee2, (q15_t)0x6eaf, (q15_t)0x6e7d, (q15_t)0x6e4a, (q15_t)0x6e17, (q15_t)0x6de3, + (q15_t)0x6db0, (q15_t)0x6d7c, (q15_t)0x6d48, (q15_t)0x6d13, (q15_t)0x6cde, (q15_t)0x6ca9, (q15_t)0x6c74, (q15_t)0x6c3f, + (q15_t)0x6c09, (q15_t)0x6bd3, (q15_t)0x6b9c, (q15_t)0x6b66, (q15_t)0x6b2f, (q15_t)0x6af8, (q15_t)0x6ac1, (q15_t)0x6a89, + (q15_t)0x6a51, (q15_t)0x6a19, (q15_t)0x69e1, (q15_t)0x69a8, (q15_t)0x696f, (q15_t)0x6936, (q15_t)0x68fd, (q15_t)0x68c3, + (q15_t)0x6889, (q15_t)0x684f, (q15_t)0x6815, (q15_t)0x67da, (q15_t)0x679f, (q15_t)0x6764, (q15_t)0x6729, (q15_t)0x66ed, + (q15_t)0x66b1, (q15_t)0x6675, (q15_t)0x6639, (q15_t)0x65fc, (q15_t)0x65bf, (q15_t)0x6582, (q15_t)0x6545, (q15_t)0x6507, + (q15_t)0x64c9, (q15_t)0x648b, (q15_t)0x644d, (q15_t)0x640e, (q15_t)0x63cf, (q15_t)0x6390, (q15_t)0x6351, (q15_t)0x6311, + (q15_t)0x62d2, (q15_t)0x6292, (q15_t)0x6251, (q15_t)0x6211, (q15_t)0x61d0, (q15_t)0x618f, (q15_t)0x614e, (q15_t)0x610d, + (q15_t)0x60cb, (q15_t)0x6089, (q15_t)0x6047, (q15_t)0x6004, (q15_t)0x5fc2, (q15_t)0x5f7f, (q15_t)0x5f3c, (q15_t)0x5ef9, + (q15_t)0x5eb5, (q15_t)0x5e71, (q15_t)0x5e2d, (q15_t)0x5de9, (q15_t)0x5da5, (q15_t)0x5d60, (q15_t)0x5d1b, (q15_t)0x5cd6, + (q15_t)0x5c91, (q15_t)0x5c4b, (q15_t)0x5c06, (q15_t)0x5bc0, (q15_t)0x5b79, (q15_t)0x5b33, (q15_t)0x5aec, (q15_t)0x5aa5, + (q15_t)0x5a5e, (q15_t)0x5a17, (q15_t)0x59d0, (q15_t)0x5988, (q15_t)0x5940, (q15_t)0x58f8, (q15_t)0x58af, (q15_t)0x5867, + (q15_t)0x581e, (q15_t)0x57d5, (q15_t)0x578c, (q15_t)0x5742, (q15_t)0x56f9, (q15_t)0x56af, (q15_t)0x5665, (q15_t)0x561a, + (q15_t)0x55d0, (q15_t)0x5585, (q15_t)0x553a, (q15_t)0x54ef, (q15_t)0x54a4, (q15_t)0x5458, (q15_t)0x540d, (q15_t)0x53c1, + (q15_t)0x5375, (q15_t)0x5328, (q15_t)0x52dc, (q15_t)0x528f, (q15_t)0x5242, (q15_t)0x51f5, (q15_t)0x51a8, (q15_t)0x515a, + (q15_t)0x510c, (q15_t)0x50bf, (q15_t)0x5070, (q15_t)0x5022, (q15_t)0x4fd4, (q15_t)0x4f85, (q15_t)0x4f36, (q15_t)0x4ee7, + (q15_t)0x4e98, (q15_t)0x4e48, (q15_t)0x4df9, (q15_t)0x4da9, (q15_t)0x4d59, (q15_t)0x4d09, (q15_t)0x4cb8, (q15_t)0x4c68, + (q15_t)0x4c17, (q15_t)0x4bc6, (q15_t)0x4b75, (q15_t)0x4b24, (q15_t)0x4ad2, (q15_t)0x4a81, (q15_t)0x4a2f, (q15_t)0x49dd, + (q15_t)0x498a, (q15_t)0x4938, (q15_t)0x48e6, (q15_t)0x4893, (q15_t)0x4840, (q15_t)0x47ed, (q15_t)0x479a, (q15_t)0x4746, + (q15_t)0x46f3, (q15_t)0x469f, (q15_t)0x464b, (q15_t)0x45f7, (q15_t)0x45a3, (q15_t)0x454e, (q15_t)0x44fa, (q15_t)0x44a5, + (q15_t)0x4450, (q15_t)0x43fb, (q15_t)0x43a5, (q15_t)0x4350, (q15_t)0x42fa, (q15_t)0x42a5, (q15_t)0x424f, (q15_t)0x41f9, + (q15_t)0x41a2, (q15_t)0x414c, (q15_t)0x40f6, (q15_t)0x409f, (q15_t)0x4048, (q15_t)0x3ff1, (q15_t)0x3f9a, (q15_t)0x3f43, + (q15_t)0x3eeb, (q15_t)0x3e93, (q15_t)0x3e3c, (q15_t)0x3de4, (q15_t)0x3d8c, (q15_t)0x3d33, (q15_t)0x3cdb, (q15_t)0x3c83, + (q15_t)0x3c2a, (q15_t)0x3bd1, (q15_t)0x3b78, (q15_t)0x3b1f, (q15_t)0x3ac6, (q15_t)0x3a6c, (q15_t)0x3a13, (q15_t)0x39b9, + (q15_t)0x395f, (q15_t)0x3906, (q15_t)0x38ab, (q15_t)0x3851, (q15_t)0x37f7, (q15_t)0x379c, (q15_t)0x3742, (q15_t)0x36e7, + (q15_t)0x368c, (q15_t)0x3631, (q15_t)0x35d6, (q15_t)0x357b, (q15_t)0x351f, (q15_t)0x34c4, (q15_t)0x3468, (q15_t)0x340c, + (q15_t)0x33b0, (q15_t)0x3354, (q15_t)0x32f8, (q15_t)0x329c, (q15_t)0x3240, (q15_t)0x31e3, (q15_t)0x3186, (q15_t)0x312a, + (q15_t)0x30cd, (q15_t)0x3070, (q15_t)0x3013, (q15_t)0x2fb5, (q15_t)0x2f58, (q15_t)0x2efb, (q15_t)0x2e9d, (q15_t)0x2e3f, + (q15_t)0x2de2, (q15_t)0x2d84, (q15_t)0x2d26, (q15_t)0x2cc8, (q15_t)0x2c69, (q15_t)0x2c0b, (q15_t)0x2bad, (q15_t)0x2b4e, + (q15_t)0x2aef, (q15_t)0x2a91, (q15_t)0x2a32, (q15_t)0x29d3, (q15_t)0x2974, (q15_t)0x2915, (q15_t)0x28b5, (q15_t)0x2856, + (q15_t)0x27f6, (q15_t)0x2797, (q15_t)0x2737, (q15_t)0x26d8, (q15_t)0x2678, (q15_t)0x2618, (q15_t)0x25b8, (q15_t)0x2558, + (q15_t)0x24f7, (q15_t)0x2497, (q15_t)0x2437, (q15_t)0x23d6, (q15_t)0x2376, (q15_t)0x2315, (q15_t)0x22b4, (q15_t)0x2254, + (q15_t)0x21f3, (q15_t)0x2192, (q15_t)0x2131, (q15_t)0x20d0, (q15_t)0x206e, (q15_t)0x200d, (q15_t)0x1fac, (q15_t)0x1f4a, + (q15_t)0x1ee9, (q15_t)0x1e87, (q15_t)0x1e25, (q15_t)0x1dc4, (q15_t)0x1d62, (q15_t)0x1d00, (q15_t)0x1c9e, (q15_t)0x1c3c, + (q15_t)0x1bda, (q15_t)0x1b78, (q15_t)0x1b16, (q15_t)0x1ab3, (q15_t)0x1a51, (q15_t)0x19ef, (q15_t)0x198c, (q15_t)0x192a, + (q15_t)0x18c7, (q15_t)0x1864, (q15_t)0x1802, (q15_t)0x179f, (q15_t)0x173c, (q15_t)0x16d9, (q15_t)0x1676, (q15_t)0x1613, + (q15_t)0x15b0, (q15_t)0x154d, (q15_t)0x14ea, (q15_t)0x1487, (q15_t)0x1423, (q15_t)0x13c0, (q15_t)0x135d, (q15_t)0x12f9, + (q15_t)0x1296, (q15_t)0x1232, (q15_t)0x11cf, (q15_t)0x116b, (q15_t)0x1108, (q15_t)0x10a4, (q15_t)0x1040, (q15_t)0xfdd, + (q15_t)0xf79, (q15_t)0xf15, (q15_t)0xeb1, (q15_t)0xe4d, (q15_t)0xde9, (q15_t)0xd85, (q15_t)0xd21, (q15_t)0xcbd, + (q15_t)0xc59, (q15_t)0xbf5, (q15_t)0xb91, (q15_t)0xb2d, (q15_t)0xac9, (q15_t)0xa65, (q15_t)0xa00, (q15_t)0x99c, + (q15_t)0x938, (q15_t)0x8d4, (q15_t)0x86f, (q15_t)0x80b, (q15_t)0x7a7, (q15_t)0x742, (q15_t)0x6de, (q15_t)0x67a, + (q15_t)0x615, (q15_t)0x5b1, (q15_t)0x54c, (q15_t)0x4e8, (q15_t)0x483, (q15_t)0x41f, (q15_t)0x3ba, (q15_t)0x356, + (q15_t)0x2f1, (q15_t)0x28d, (q15_t)0x228, (q15_t)0x1c4, (q15_t)0x15f, (q15_t)0xfb, (q15_t)0x96, (q15_t)0x32 +}; + + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048) + const q15_t __ALIGNED(4) WeightsQ15_2048[4096] = { + (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xffe7, (q15_t)0x7fff, (q15_t)0xffce, (q15_t)0x7fff, (q15_t)0xffb5, + (q15_t)0x7fff, (q15_t)0xff9c, (q15_t)0x7fff, (q15_t)0xff83, (q15_t)0x7fff, (q15_t)0xff6a, (q15_t)0x7fff, (q15_t)0xff51, + (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7fff, (q15_t)0xff1e, (q15_t)0x7fff, (q15_t)0xff05, (q15_t)0x7ffe, (q15_t)0xfeec, + (q15_t)0x7ffe, (q15_t)0xfed3, (q15_t)0x7ffe, (q15_t)0xfeba, (q15_t)0x7ffe, (q15_t)0xfea1, (q15_t)0x7ffd, (q15_t)0xfe88, + (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ffd, (q15_t)0xfe55, (q15_t)0x7ffc, (q15_t)0xfe3c, (q15_t)0x7ffc, (q15_t)0xfe23, + (q15_t)0x7ffc, (q15_t)0xfe0a, (q15_t)0x7ffb, (q15_t)0xfdf1, (q15_t)0x7ffb, (q15_t)0xfdd8, (q15_t)0x7ffa, (q15_t)0xfdbe, + (q15_t)0x7ffa, (q15_t)0xfda5, (q15_t)0x7ff9, (q15_t)0xfd8c, (q15_t)0x7ff9, (q15_t)0xfd73, (q15_t)0x7ff8, (q15_t)0xfd5a, + (q15_t)0x7ff8, (q15_t)0xfd41, (q15_t)0x7ff7, (q15_t)0xfd28, (q15_t)0x7ff7, (q15_t)0xfd0f, (q15_t)0x7ff6, (q15_t)0xfcf5, + (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7ff5, (q15_t)0xfcc3, (q15_t)0x7ff4, (q15_t)0xfcaa, (q15_t)0x7ff4, (q15_t)0xfc91, + (q15_t)0x7ff3, (q15_t)0xfc78, (q15_t)0x7ff2, (q15_t)0xfc5f, (q15_t)0x7ff2, (q15_t)0xfc46, (q15_t)0x7ff1, (q15_t)0xfc2c, + (q15_t)0x7ff0, (q15_t)0xfc13, (q15_t)0x7fef, (q15_t)0xfbfa, (q15_t)0x7fee, (q15_t)0xfbe1, (q15_t)0x7fee, (q15_t)0xfbc8, + (q15_t)0x7fed, (q15_t)0xfbaf, (q15_t)0x7fec, (q15_t)0xfb96, (q15_t)0x7feb, (q15_t)0xfb7d, (q15_t)0x7fea, (q15_t)0xfb64, + (q15_t)0x7fe9, (q15_t)0xfb4a, (q15_t)0x7fe8, (q15_t)0xfb31, (q15_t)0x7fe7, (q15_t)0xfb18, (q15_t)0x7fe6, (q15_t)0xfaff, + (q15_t)0x7fe5, (q15_t)0xfae6, (q15_t)0x7fe4, (q15_t)0xfacd, (q15_t)0x7fe3, (q15_t)0xfab4, (q15_t)0x7fe2, (q15_t)0xfa9b, + (q15_t)0x7fe1, (q15_t)0xfa81, (q15_t)0x7fe0, (q15_t)0xfa68, (q15_t)0x7fdf, (q15_t)0xfa4f, (q15_t)0x7fde, (q15_t)0xfa36, + (q15_t)0x7fdd, (q15_t)0xfa1d, (q15_t)0x7fdc, (q15_t)0xfa04, (q15_t)0x7fda, (q15_t)0xf9eb, (q15_t)0x7fd9, (q15_t)0xf9d2, + (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fd7, (q15_t)0xf9a0, (q15_t)0x7fd6, (q15_t)0xf986, (q15_t)0x7fd4, (q15_t)0xf96d, + (q15_t)0x7fd3, (q15_t)0xf954, (q15_t)0x7fd2, (q15_t)0xf93b, (q15_t)0x7fd0, (q15_t)0xf922, (q15_t)0x7fcf, (q15_t)0xf909, + (q15_t)0x7fce, (q15_t)0xf8f0, (q15_t)0x7fcc, (q15_t)0xf8d7, (q15_t)0x7fcb, (q15_t)0xf8be, (q15_t)0x7fc9, (q15_t)0xf8a5, + (q15_t)0x7fc8, (q15_t)0xf88b, (q15_t)0x7fc6, (q15_t)0xf872, (q15_t)0x7fc5, (q15_t)0xf859, (q15_t)0x7fc3, (q15_t)0xf840, + (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fc0, (q15_t)0xf80e, (q15_t)0x7fbf, (q15_t)0xf7f5, (q15_t)0x7fbd, (q15_t)0xf7dc, + (q15_t)0x7fbc, (q15_t)0xf7c3, (q15_t)0x7fba, (q15_t)0xf7aa, (q15_t)0x7fb8, (q15_t)0xf791, (q15_t)0x7fb7, (q15_t)0xf778, + (q15_t)0x7fb5, (q15_t)0xf75e, (q15_t)0x7fb3, (q15_t)0xf745, (q15_t)0x7fb1, (q15_t)0xf72c, (q15_t)0x7fb0, (q15_t)0xf713, + (q15_t)0x7fae, (q15_t)0xf6fa, (q15_t)0x7fac, (q15_t)0xf6e1, (q15_t)0x7faa, (q15_t)0xf6c8, (q15_t)0x7fa9, (q15_t)0xf6af, + (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7fa5, (q15_t)0xf67d, (q15_t)0x7fa3, (q15_t)0xf664, (q15_t)0x7fa1, (q15_t)0xf64b, + (q15_t)0x7f9f, (q15_t)0xf632, (q15_t)0x7f9d, (q15_t)0xf619, (q15_t)0x7f9b, (q15_t)0xf600, (q15_t)0x7f99, (q15_t)0xf5e7, + (q15_t)0x7f97, (q15_t)0xf5cd, (q15_t)0x7f95, (q15_t)0xf5b4, (q15_t)0x7f93, (q15_t)0xf59b, (q15_t)0x7f91, (q15_t)0xf582, + (q15_t)0x7f8f, (q15_t)0xf569, (q15_t)0x7f8d, (q15_t)0xf550, (q15_t)0x7f8b, (q15_t)0xf537, (q15_t)0x7f89, (q15_t)0xf51e, + (q15_t)0x7f87, (q15_t)0xf505, (q15_t)0x7f85, (q15_t)0xf4ec, (q15_t)0x7f82, (q15_t)0xf4d3, (q15_t)0x7f80, (q15_t)0xf4ba, + (q15_t)0x7f7e, (q15_t)0xf4a1, (q15_t)0x7f7c, (q15_t)0xf488, (q15_t)0x7f79, (q15_t)0xf46f, (q15_t)0x7f77, (q15_t)0xf456, + (q15_t)0x7f75, (q15_t)0xf43d, (q15_t)0x7f72, (q15_t)0xf424, (q15_t)0x7f70, (q15_t)0xf40b, (q15_t)0x7f6e, (q15_t)0xf3f2, + (q15_t)0x7f6b, (q15_t)0xf3d9, (q15_t)0x7f69, (q15_t)0xf3c0, (q15_t)0x7f67, (q15_t)0xf3a7, (q15_t)0x7f64, (q15_t)0xf38e, + (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f5f, (q15_t)0xf35c, (q15_t)0x7f5d, (q15_t)0xf343, (q15_t)0x7f5a, (q15_t)0xf32a, + (q15_t)0x7f58, (q15_t)0xf311, (q15_t)0x7f55, (q15_t)0xf2f8, (q15_t)0x7f53, (q15_t)0xf2df, (q15_t)0x7f50, (q15_t)0xf2c6, + (q15_t)0x7f4d, (q15_t)0xf2ad, (q15_t)0x7f4b, (q15_t)0xf294, (q15_t)0x7f48, (q15_t)0xf27b, (q15_t)0x7f45, (q15_t)0xf262, + (q15_t)0x7f43, (q15_t)0xf249, (q15_t)0x7f40, (q15_t)0xf230, (q15_t)0x7f3d, (q15_t)0xf217, (q15_t)0x7f3b, (q15_t)0xf1fe, + (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f35, (q15_t)0xf1cc, (q15_t)0x7f32, (q15_t)0xf1b3, (q15_t)0x7f2f, (q15_t)0xf19a, + (q15_t)0x7f2d, (q15_t)0xf181, (q15_t)0x7f2a, (q15_t)0xf168, (q15_t)0x7f27, (q15_t)0xf14f, (q15_t)0x7f24, (q15_t)0xf136, + (q15_t)0x7f21, (q15_t)0xf11d, (q15_t)0x7f1e, (q15_t)0xf104, (q15_t)0x7f1b, (q15_t)0xf0eb, (q15_t)0x7f18, (q15_t)0xf0d2, + (q15_t)0x7f15, (q15_t)0xf0b9, (q15_t)0x7f12, (q15_t)0xf0a0, (q15_t)0x7f0f, (q15_t)0xf087, (q15_t)0x7f0c, (q15_t)0xf06e, + (q15_t)0x7f09, (q15_t)0xf055, (q15_t)0x7f06, (q15_t)0xf03c, (q15_t)0x7f03, (q15_t)0xf023, (q15_t)0x7f00, (q15_t)0xf00b, + (q15_t)0x7efd, (q15_t)0xeff2, (q15_t)0x7ef9, (q15_t)0xefd9, (q15_t)0x7ef6, (q15_t)0xefc0, (q15_t)0x7ef3, (q15_t)0xefa7, + (q15_t)0x7ef0, (q15_t)0xef8e, (q15_t)0x7eed, (q15_t)0xef75, (q15_t)0x7ee9, (q15_t)0xef5c, (q15_t)0x7ee6, (q15_t)0xef43, + (q15_t)0x7ee3, (q15_t)0xef2a, (q15_t)0x7edf, (q15_t)0xef11, (q15_t)0x7edc, (q15_t)0xeef8, (q15_t)0x7ed9, (q15_t)0xeedf, + (q15_t)0x7ed5, (q15_t)0xeec7, (q15_t)0x7ed2, (q15_t)0xeeae, (q15_t)0x7ecf, (q15_t)0xee95, (q15_t)0x7ecb, (q15_t)0xee7c, + (q15_t)0x7ec8, (q15_t)0xee63, (q15_t)0x7ec4, (q15_t)0xee4a, (q15_t)0x7ec1, (q15_t)0xee31, (q15_t)0x7ebd, (q15_t)0xee18, + (q15_t)0x7eba, (q15_t)0xedff, (q15_t)0x7eb6, (q15_t)0xede7, (q15_t)0x7eb3, (q15_t)0xedce, (q15_t)0x7eaf, (q15_t)0xedb5, + (q15_t)0x7eab, (q15_t)0xed9c, (q15_t)0x7ea8, (q15_t)0xed83, (q15_t)0x7ea4, (q15_t)0xed6a, (q15_t)0x7ea1, (q15_t)0xed51, + (q15_t)0x7e9d, (q15_t)0xed38, (q15_t)0x7e99, (q15_t)0xed20, (q15_t)0x7e95, (q15_t)0xed07, (q15_t)0x7e92, (q15_t)0xecee, + (q15_t)0x7e8e, (q15_t)0xecd5, (q15_t)0x7e8a, (q15_t)0xecbc, (q15_t)0x7e86, (q15_t)0xeca3, (q15_t)0x7e83, (q15_t)0xec8a, + (q15_t)0x7e7f, (q15_t)0xec72, (q15_t)0x7e7b, (q15_t)0xec59, (q15_t)0x7e77, (q15_t)0xec40, (q15_t)0x7e73, (q15_t)0xec27, + (q15_t)0x7e6f, (q15_t)0xec0e, (q15_t)0x7e6b, (q15_t)0xebf5, (q15_t)0x7e67, (q15_t)0xebdd, (q15_t)0x7e63, (q15_t)0xebc4, + (q15_t)0x7e5f, (q15_t)0xebab, (q15_t)0x7e5b, (q15_t)0xeb92, (q15_t)0x7e57, (q15_t)0xeb79, (q15_t)0x7e53, (q15_t)0xeb61, + (q15_t)0x7e4f, (q15_t)0xeb48, (q15_t)0x7e4b, (q15_t)0xeb2f, (q15_t)0x7e47, (q15_t)0xeb16, (q15_t)0x7e43, (q15_t)0xeafd, + (q15_t)0x7e3f, (q15_t)0xeae5, (q15_t)0x7e3b, (q15_t)0xeacc, (q15_t)0x7e37, (q15_t)0xeab3, (q15_t)0x7e32, (q15_t)0xea9a, + (q15_t)0x7e2e, (q15_t)0xea81, (q15_t)0x7e2a, (q15_t)0xea69, (q15_t)0x7e26, (q15_t)0xea50, (q15_t)0x7e21, (q15_t)0xea37, + (q15_t)0x7e1d, (q15_t)0xea1e, (q15_t)0x7e19, (q15_t)0xea06, (q15_t)0x7e14, (q15_t)0xe9ed, (q15_t)0x7e10, (q15_t)0xe9d4, + (q15_t)0x7e0c, (q15_t)0xe9bb, (q15_t)0x7e07, (q15_t)0xe9a3, (q15_t)0x7e03, (q15_t)0xe98a, (q15_t)0x7dff, (q15_t)0xe971, + (q15_t)0x7dfa, (q15_t)0xe958, (q15_t)0x7df6, (q15_t)0xe940, (q15_t)0x7df1, (q15_t)0xe927, (q15_t)0x7ded, (q15_t)0xe90e, + (q15_t)0x7de8, (q15_t)0xe8f6, (q15_t)0x7de4, (q15_t)0xe8dd, (q15_t)0x7ddf, (q15_t)0xe8c4, (q15_t)0x7dda, (q15_t)0xe8ab, + (q15_t)0x7dd6, (q15_t)0xe893, (q15_t)0x7dd1, (q15_t)0xe87a, (q15_t)0x7dcd, (q15_t)0xe861, (q15_t)0x7dc8, (q15_t)0xe849, + (q15_t)0x7dc3, (q15_t)0xe830, (q15_t)0x7dbf, (q15_t)0xe817, (q15_t)0x7dba, (q15_t)0xe7fe, (q15_t)0x7db5, (q15_t)0xe7e6, + (q15_t)0x7db0, (q15_t)0xe7cd, (q15_t)0x7dac, (q15_t)0xe7b4, (q15_t)0x7da7, (q15_t)0xe79c, (q15_t)0x7da2, (q15_t)0xe783, + (q15_t)0x7d9d, (q15_t)0xe76a, (q15_t)0x7d98, (q15_t)0xe752, (q15_t)0x7d94, (q15_t)0xe739, (q15_t)0x7d8f, (q15_t)0xe720, + (q15_t)0x7d8a, (q15_t)0xe708, (q15_t)0x7d85, (q15_t)0xe6ef, (q15_t)0x7d80, (q15_t)0xe6d6, (q15_t)0x7d7b, (q15_t)0xe6be, + (q15_t)0x7d76, (q15_t)0xe6a5, (q15_t)0x7d71, (q15_t)0xe68d, (q15_t)0x7d6c, (q15_t)0xe674, (q15_t)0x7d67, (q15_t)0xe65b, + (q15_t)0x7d62, (q15_t)0xe643, (q15_t)0x7d5d, (q15_t)0xe62a, (q15_t)0x7d58, (q15_t)0xe611, (q15_t)0x7d53, (q15_t)0xe5f9, + (q15_t)0x7d4e, (q15_t)0xe5e0, (q15_t)0x7d49, (q15_t)0xe5c8, (q15_t)0x7d43, (q15_t)0xe5af, (q15_t)0x7d3e, (q15_t)0xe596, + (q15_t)0x7d39, (q15_t)0xe57e, (q15_t)0x7d34, (q15_t)0xe565, (q15_t)0x7d2f, (q15_t)0xe54d, (q15_t)0x7d29, (q15_t)0xe534, + (q15_t)0x7d24, (q15_t)0xe51c, (q15_t)0x7d1f, (q15_t)0xe503, (q15_t)0x7d19, (q15_t)0xe4ea, (q15_t)0x7d14, (q15_t)0xe4d2, + (q15_t)0x7d0f, (q15_t)0xe4b9, (q15_t)0x7d09, (q15_t)0xe4a1, (q15_t)0x7d04, (q15_t)0xe488, (q15_t)0x7cff, (q15_t)0xe470, + (q15_t)0x7cf9, (q15_t)0xe457, (q15_t)0x7cf4, (q15_t)0xe43f, (q15_t)0x7cee, (q15_t)0xe426, (q15_t)0x7ce9, (q15_t)0xe40e, + (q15_t)0x7ce3, (q15_t)0xe3f5, (q15_t)0x7cde, (q15_t)0xe3dc, (q15_t)0x7cd8, (q15_t)0xe3c4, (q15_t)0x7cd3, (q15_t)0xe3ab, + (q15_t)0x7ccd, (q15_t)0xe393, (q15_t)0x7cc8, (q15_t)0xe37a, (q15_t)0x7cc2, (q15_t)0xe362, (q15_t)0x7cbc, (q15_t)0xe349, + (q15_t)0x7cb7, (q15_t)0xe331, (q15_t)0x7cb1, (q15_t)0xe318, (q15_t)0x7cab, (q15_t)0xe300, (q15_t)0x7ca6, (q15_t)0xe2e8, + (q15_t)0x7ca0, (q15_t)0xe2cf, (q15_t)0x7c9a, (q15_t)0xe2b7, (q15_t)0x7c94, (q15_t)0xe29e, (q15_t)0x7c8f, (q15_t)0xe286, + (q15_t)0x7c89, (q15_t)0xe26d, (q15_t)0x7c83, (q15_t)0xe255, (q15_t)0x7c7d, (q15_t)0xe23c, (q15_t)0x7c77, (q15_t)0xe224, + (q15_t)0x7c71, (q15_t)0xe20b, (q15_t)0x7c6c, (q15_t)0xe1f3, (q15_t)0x7c66, (q15_t)0xe1db, (q15_t)0x7c60, (q15_t)0xe1c2, + (q15_t)0x7c5a, (q15_t)0xe1aa, (q15_t)0x7c54, (q15_t)0xe191, (q15_t)0x7c4e, (q15_t)0xe179, (q15_t)0x7c48, (q15_t)0xe160, + (q15_t)0x7c42, (q15_t)0xe148, (q15_t)0x7c3c, (q15_t)0xe130, (q15_t)0x7c36, (q15_t)0xe117, (q15_t)0x7c30, (q15_t)0xe0ff, + (q15_t)0x7c29, (q15_t)0xe0e7, (q15_t)0x7c23, (q15_t)0xe0ce, (q15_t)0x7c1d, (q15_t)0xe0b6, (q15_t)0x7c17, (q15_t)0xe09d, + (q15_t)0x7c11, (q15_t)0xe085, (q15_t)0x7c0b, (q15_t)0xe06d, (q15_t)0x7c05, (q15_t)0xe054, (q15_t)0x7bfe, (q15_t)0xe03c, + (q15_t)0x7bf8, (q15_t)0xe024, (q15_t)0x7bf2, (q15_t)0xe00b, (q15_t)0x7beb, (q15_t)0xdff3, (q15_t)0x7be5, (q15_t)0xdfdb, + (q15_t)0x7bdf, (q15_t)0xdfc2, (q15_t)0x7bd9, (q15_t)0xdfaa, (q15_t)0x7bd2, (q15_t)0xdf92, (q15_t)0x7bcc, (q15_t)0xdf79, + (q15_t)0x7bc5, (q15_t)0xdf61, (q15_t)0x7bbf, (q15_t)0xdf49, (q15_t)0x7bb9, (q15_t)0xdf30, (q15_t)0x7bb2, (q15_t)0xdf18, + (q15_t)0x7bac, (q15_t)0xdf00, (q15_t)0x7ba5, (q15_t)0xdee8, (q15_t)0x7b9f, (q15_t)0xdecf, (q15_t)0x7b98, (q15_t)0xdeb7, + (q15_t)0x7b92, (q15_t)0xde9f, (q15_t)0x7b8b, (q15_t)0xde87, (q15_t)0x7b84, (q15_t)0xde6e, (q15_t)0x7b7e, (q15_t)0xde56, + (q15_t)0x7b77, (q15_t)0xde3e, (q15_t)0x7b71, (q15_t)0xde26, (q15_t)0x7b6a, (q15_t)0xde0d, (q15_t)0x7b63, (q15_t)0xddf5, + (q15_t)0x7b5d, (q15_t)0xdddd, (q15_t)0x7b56, (q15_t)0xddc5, (q15_t)0x7b4f, (q15_t)0xddac, (q15_t)0x7b48, (q15_t)0xdd94, + (q15_t)0x7b42, (q15_t)0xdd7c, (q15_t)0x7b3b, (q15_t)0xdd64, (q15_t)0x7b34, (q15_t)0xdd4c, (q15_t)0x7b2d, (q15_t)0xdd33, + (q15_t)0x7b26, (q15_t)0xdd1b, (q15_t)0x7b1f, (q15_t)0xdd03, (q15_t)0x7b19, (q15_t)0xdceb, (q15_t)0x7b12, (q15_t)0xdcd3, + (q15_t)0x7b0b, (q15_t)0xdcbb, (q15_t)0x7b04, (q15_t)0xdca2, (q15_t)0x7afd, (q15_t)0xdc8a, (q15_t)0x7af6, (q15_t)0xdc72, + (q15_t)0x7aef, (q15_t)0xdc5a, (q15_t)0x7ae8, (q15_t)0xdc42, (q15_t)0x7ae1, (q15_t)0xdc2a, (q15_t)0x7ada, (q15_t)0xdc12, + (q15_t)0x7ad3, (q15_t)0xdbf9, (q15_t)0x7acc, (q15_t)0xdbe1, (q15_t)0x7ac5, (q15_t)0xdbc9, (q15_t)0x7abd, (q15_t)0xdbb1, + (q15_t)0x7ab6, (q15_t)0xdb99, (q15_t)0x7aaf, (q15_t)0xdb81, (q15_t)0x7aa8, (q15_t)0xdb69, (q15_t)0x7aa1, (q15_t)0xdb51, + (q15_t)0x7a9a, (q15_t)0xdb39, (q15_t)0x7a92, (q15_t)0xdb21, (q15_t)0x7a8b, (q15_t)0xdb09, (q15_t)0x7a84, (q15_t)0xdaf1, + (q15_t)0x7a7d, (q15_t)0xdad8, (q15_t)0x7a75, (q15_t)0xdac0, (q15_t)0x7a6e, (q15_t)0xdaa8, (q15_t)0x7a67, (q15_t)0xda90, + (q15_t)0x7a5f, (q15_t)0xda78, (q15_t)0x7a58, (q15_t)0xda60, (q15_t)0x7a50, (q15_t)0xda48, (q15_t)0x7a49, (q15_t)0xda30, + (q15_t)0x7a42, (q15_t)0xda18, (q15_t)0x7a3a, (q15_t)0xda00, (q15_t)0x7a33, (q15_t)0xd9e8, (q15_t)0x7a2b, (q15_t)0xd9d0, + (q15_t)0x7a24, (q15_t)0xd9b8, (q15_t)0x7a1c, (q15_t)0xd9a0, (q15_t)0x7a15, (q15_t)0xd988, (q15_t)0x7a0d, (q15_t)0xd970, + (q15_t)0x7a05, (q15_t)0xd958, (q15_t)0x79fe, (q15_t)0xd940, (q15_t)0x79f6, (q15_t)0xd928, (q15_t)0x79ef, (q15_t)0xd911, + (q15_t)0x79e7, (q15_t)0xd8f9, (q15_t)0x79df, (q15_t)0xd8e1, (q15_t)0x79d8, (q15_t)0xd8c9, (q15_t)0x79d0, (q15_t)0xd8b1, + (q15_t)0x79c8, (q15_t)0xd899, (q15_t)0x79c0, (q15_t)0xd881, (q15_t)0x79b9, (q15_t)0xd869, (q15_t)0x79b1, (q15_t)0xd851, + (q15_t)0x79a9, (q15_t)0xd839, (q15_t)0x79a1, (q15_t)0xd821, (q15_t)0x7999, (q15_t)0xd80a, (q15_t)0x7992, (q15_t)0xd7f2, + (q15_t)0x798a, (q15_t)0xd7da, (q15_t)0x7982, (q15_t)0xd7c2, (q15_t)0x797a, (q15_t)0xd7aa, (q15_t)0x7972, (q15_t)0xd792, + (q15_t)0x796a, (q15_t)0xd77a, (q15_t)0x7962, (q15_t)0xd763, (q15_t)0x795a, (q15_t)0xd74b, (q15_t)0x7952, (q15_t)0xd733, + (q15_t)0x794a, (q15_t)0xd71b, (q15_t)0x7942, (q15_t)0xd703, (q15_t)0x793a, (q15_t)0xd6eb, (q15_t)0x7932, (q15_t)0xd6d4, + (q15_t)0x792a, (q15_t)0xd6bc, (q15_t)0x7922, (q15_t)0xd6a4, (q15_t)0x7919, (q15_t)0xd68c, (q15_t)0x7911, (q15_t)0xd675, + (q15_t)0x7909, (q15_t)0xd65d, (q15_t)0x7901, (q15_t)0xd645, (q15_t)0x78f9, (q15_t)0xd62d, (q15_t)0x78f1, (q15_t)0xd615, + (q15_t)0x78e8, (q15_t)0xd5fe, (q15_t)0x78e0, (q15_t)0xd5e6, (q15_t)0x78d8, (q15_t)0xd5ce, (q15_t)0x78cf, (q15_t)0xd5b7, + (q15_t)0x78c7, (q15_t)0xd59f, (q15_t)0x78bf, (q15_t)0xd587, (q15_t)0x78b6, (q15_t)0xd56f, (q15_t)0x78ae, (q15_t)0xd558, + (q15_t)0x78a6, (q15_t)0xd540, (q15_t)0x789d, (q15_t)0xd528, (q15_t)0x7895, (q15_t)0xd511, (q15_t)0x788c, (q15_t)0xd4f9, + (q15_t)0x7884, (q15_t)0xd4e1, (q15_t)0x787c, (q15_t)0xd4ca, (q15_t)0x7873, (q15_t)0xd4b2, (q15_t)0x786b, (q15_t)0xd49a, + (q15_t)0x7862, (q15_t)0xd483, (q15_t)0x7859, (q15_t)0xd46b, (q15_t)0x7851, (q15_t)0xd453, (q15_t)0x7848, (q15_t)0xd43c, + (q15_t)0x7840, (q15_t)0xd424, (q15_t)0x7837, (q15_t)0xd40d, (q15_t)0x782e, (q15_t)0xd3f5, (q15_t)0x7826, (q15_t)0xd3dd, + (q15_t)0x781d, (q15_t)0xd3c6, (q15_t)0x7814, (q15_t)0xd3ae, (q15_t)0x780c, (q15_t)0xd397, (q15_t)0x7803, (q15_t)0xd37f, + (q15_t)0x77fa, (q15_t)0xd368, (q15_t)0x77f1, (q15_t)0xd350, (q15_t)0x77e9, (q15_t)0xd338, (q15_t)0x77e0, (q15_t)0xd321, + (q15_t)0x77d7, (q15_t)0xd309, (q15_t)0x77ce, (q15_t)0xd2f2, (q15_t)0x77c5, (q15_t)0xd2da, (q15_t)0x77bc, (q15_t)0xd2c3, + (q15_t)0x77b4, (q15_t)0xd2ab, (q15_t)0x77ab, (q15_t)0xd294, (q15_t)0x77a2, (q15_t)0xd27c, (q15_t)0x7799, (q15_t)0xd265, + (q15_t)0x7790, (q15_t)0xd24d, (q15_t)0x7787, (q15_t)0xd236, (q15_t)0x777e, (q15_t)0xd21e, (q15_t)0x7775, (q15_t)0xd207, + (q15_t)0x776c, (q15_t)0xd1ef, (q15_t)0x7763, (q15_t)0xd1d8, (q15_t)0x775a, (q15_t)0xd1c1, (q15_t)0x7751, (q15_t)0xd1a9, + (q15_t)0x7747, (q15_t)0xd192, (q15_t)0x773e, (q15_t)0xd17a, (q15_t)0x7735, (q15_t)0xd163, (q15_t)0x772c, (q15_t)0xd14b, + (q15_t)0x7723, (q15_t)0xd134, (q15_t)0x771a, (q15_t)0xd11d, (q15_t)0x7710, (q15_t)0xd105, (q15_t)0x7707, (q15_t)0xd0ee, + (q15_t)0x76fe, (q15_t)0xd0d7, (q15_t)0x76f5, (q15_t)0xd0bf, (q15_t)0x76eb, (q15_t)0xd0a8, (q15_t)0x76e2, (q15_t)0xd091, + (q15_t)0x76d9, (q15_t)0xd079, (q15_t)0x76cf, (q15_t)0xd062, (q15_t)0x76c6, (q15_t)0xd04b, (q15_t)0x76bd, (q15_t)0xd033, + (q15_t)0x76b3, (q15_t)0xd01c, (q15_t)0x76aa, (q15_t)0xd005, (q15_t)0x76a0, (q15_t)0xcfed, (q15_t)0x7697, (q15_t)0xcfd6, + (q15_t)0x768e, (q15_t)0xcfbf, (q15_t)0x7684, (q15_t)0xcfa7, (q15_t)0x767b, (q15_t)0xcf90, (q15_t)0x7671, (q15_t)0xcf79, + (q15_t)0x7668, (q15_t)0xcf62, (q15_t)0x765e, (q15_t)0xcf4a, (q15_t)0x7654, (q15_t)0xcf33, (q15_t)0x764b, (q15_t)0xcf1c, + (q15_t)0x7641, (q15_t)0xcf05, (q15_t)0x7638, (q15_t)0xceee, (q15_t)0x762e, (q15_t)0xced6, (q15_t)0x7624, (q15_t)0xcebf, + (q15_t)0x761b, (q15_t)0xcea8, (q15_t)0x7611, (q15_t)0xce91, (q15_t)0x7607, (q15_t)0xce7a, (q15_t)0x75fd, (q15_t)0xce62, + (q15_t)0x75f4, (q15_t)0xce4b, (q15_t)0x75ea, (q15_t)0xce34, (q15_t)0x75e0, (q15_t)0xce1d, (q15_t)0x75d6, (q15_t)0xce06, + (q15_t)0x75cc, (q15_t)0xcdef, (q15_t)0x75c3, (q15_t)0xcdd8, (q15_t)0x75b9, (q15_t)0xcdc0, (q15_t)0x75af, (q15_t)0xcda9, + (q15_t)0x75a5, (q15_t)0xcd92, (q15_t)0x759b, (q15_t)0xcd7b, (q15_t)0x7591, (q15_t)0xcd64, (q15_t)0x7587, (q15_t)0xcd4d, + (q15_t)0x757d, (q15_t)0xcd36, (q15_t)0x7573, (q15_t)0xcd1f, (q15_t)0x7569, (q15_t)0xcd08, (q15_t)0x755f, (q15_t)0xccf1, + (q15_t)0x7555, (q15_t)0xccda, (q15_t)0x754b, (q15_t)0xccc3, (q15_t)0x7541, (q15_t)0xccac, (q15_t)0x7537, (q15_t)0xcc95, + (q15_t)0x752d, (q15_t)0xcc7e, (q15_t)0x7523, (q15_t)0xcc67, (q15_t)0x7519, (q15_t)0xcc50, (q15_t)0x750f, (q15_t)0xcc39, + (q15_t)0x7504, (q15_t)0xcc22, (q15_t)0x74fa, (q15_t)0xcc0b, (q15_t)0x74f0, (q15_t)0xcbf4, (q15_t)0x74e6, (q15_t)0xcbdd, + (q15_t)0x74db, (q15_t)0xcbc6, (q15_t)0x74d1, (q15_t)0xcbaf, (q15_t)0x74c7, (q15_t)0xcb98, (q15_t)0x74bd, (q15_t)0xcb81, + (q15_t)0x74b2, (q15_t)0xcb6a, (q15_t)0x74a8, (q15_t)0xcb53, (q15_t)0x749e, (q15_t)0xcb3c, (q15_t)0x7493, (q15_t)0xcb25, + (q15_t)0x7489, (q15_t)0xcb0e, (q15_t)0x747e, (q15_t)0xcaf8, (q15_t)0x7474, (q15_t)0xcae1, (q15_t)0x746a, (q15_t)0xcaca, + (q15_t)0x745f, (q15_t)0xcab3, (q15_t)0x7455, (q15_t)0xca9c, (q15_t)0x744a, (q15_t)0xca85, (q15_t)0x7440, (q15_t)0xca6e, + (q15_t)0x7435, (q15_t)0xca58, (q15_t)0x742b, (q15_t)0xca41, (q15_t)0x7420, (q15_t)0xca2a, (q15_t)0x7415, (q15_t)0xca13, + (q15_t)0x740b, (q15_t)0xc9fc, (q15_t)0x7400, (q15_t)0xc9e6, (q15_t)0x73f6, (q15_t)0xc9cf, (q15_t)0x73eb, (q15_t)0xc9b8, + (q15_t)0x73e0, (q15_t)0xc9a1, (q15_t)0x73d6, (q15_t)0xc98b, (q15_t)0x73cb, (q15_t)0xc974, (q15_t)0x73c0, (q15_t)0xc95d, + (q15_t)0x73b5, (q15_t)0xc946, (q15_t)0x73ab, (q15_t)0xc930, (q15_t)0x73a0, (q15_t)0xc919, (q15_t)0x7395, (q15_t)0xc902, + (q15_t)0x738a, (q15_t)0xc8ec, (q15_t)0x737f, (q15_t)0xc8d5, (q15_t)0x7375, (q15_t)0xc8be, (q15_t)0x736a, (q15_t)0xc8a8, + (q15_t)0x735f, (q15_t)0xc891, (q15_t)0x7354, (q15_t)0xc87a, (q15_t)0x7349, (q15_t)0xc864, (q15_t)0x733e, (q15_t)0xc84d, + (q15_t)0x7333, (q15_t)0xc836, (q15_t)0x7328, (q15_t)0xc820, (q15_t)0x731d, (q15_t)0xc809, (q15_t)0x7312, (q15_t)0xc7f3, + (q15_t)0x7307, (q15_t)0xc7dc, (q15_t)0x72fc, (q15_t)0xc7c5, (q15_t)0x72f1, (q15_t)0xc7af, (q15_t)0x72e6, (q15_t)0xc798, + (q15_t)0x72db, (q15_t)0xc782, (q15_t)0x72d0, (q15_t)0xc76b, (q15_t)0x72c5, (q15_t)0xc755, (q15_t)0x72ba, (q15_t)0xc73e, + (q15_t)0x72af, (q15_t)0xc728, (q15_t)0x72a3, (q15_t)0xc711, (q15_t)0x7298, (q15_t)0xc6fa, (q15_t)0x728d, (q15_t)0xc6e4, + (q15_t)0x7282, (q15_t)0xc6ce, (q15_t)0x7276, (q15_t)0xc6b7, (q15_t)0x726b, (q15_t)0xc6a1, (q15_t)0x7260, (q15_t)0xc68a, + (q15_t)0x7255, (q15_t)0xc674, (q15_t)0x7249, (q15_t)0xc65d, (q15_t)0x723e, (q15_t)0xc647, (q15_t)0x7233, (q15_t)0xc630, + (q15_t)0x7227, (q15_t)0xc61a, (q15_t)0x721c, (q15_t)0xc603, (q15_t)0x7211, (q15_t)0xc5ed, (q15_t)0x7205, (q15_t)0xc5d7, + (q15_t)0x71fa, (q15_t)0xc5c0, (q15_t)0x71ee, (q15_t)0xc5aa, (q15_t)0x71e3, (q15_t)0xc594, (q15_t)0x71d7, (q15_t)0xc57d, + (q15_t)0x71cc, (q15_t)0xc567, (q15_t)0x71c0, (q15_t)0xc551, (q15_t)0x71b5, (q15_t)0xc53a, (q15_t)0x71a9, (q15_t)0xc524, + (q15_t)0x719e, (q15_t)0xc50e, (q15_t)0x7192, (q15_t)0xc4f7, (q15_t)0x7186, (q15_t)0xc4e1, (q15_t)0x717b, (q15_t)0xc4cb, + (q15_t)0x716f, (q15_t)0xc4b4, (q15_t)0x7164, (q15_t)0xc49e, (q15_t)0x7158, (q15_t)0xc488, (q15_t)0x714c, (q15_t)0xc472, + (q15_t)0x7141, (q15_t)0xc45b, (q15_t)0x7135, (q15_t)0xc445, (q15_t)0x7129, (q15_t)0xc42f, (q15_t)0x711d, (q15_t)0xc419, + (q15_t)0x7112, (q15_t)0xc403, (q15_t)0x7106, (q15_t)0xc3ec, (q15_t)0x70fa, (q15_t)0xc3d6, (q15_t)0x70ee, (q15_t)0xc3c0, + (q15_t)0x70e2, (q15_t)0xc3aa, (q15_t)0x70d6, (q15_t)0xc394, (q15_t)0x70cb, (q15_t)0xc37d, (q15_t)0x70bf, (q15_t)0xc367, + (q15_t)0x70b3, (q15_t)0xc351, (q15_t)0x70a7, (q15_t)0xc33b, (q15_t)0x709b, (q15_t)0xc325, (q15_t)0x708f, (q15_t)0xc30f, + (q15_t)0x7083, (q15_t)0xc2f9, (q15_t)0x7077, (q15_t)0xc2e3, (q15_t)0x706b, (q15_t)0xc2cd, (q15_t)0x705f, (q15_t)0xc2b7, + (q15_t)0x7053, (q15_t)0xc2a0, (q15_t)0x7047, (q15_t)0xc28a, (q15_t)0x703b, (q15_t)0xc274, (q15_t)0x702f, (q15_t)0xc25e, + (q15_t)0x7023, (q15_t)0xc248, (q15_t)0x7016, (q15_t)0xc232, (q15_t)0x700a, (q15_t)0xc21c, (q15_t)0x6ffe, (q15_t)0xc206, + (q15_t)0x6ff2, (q15_t)0xc1f0, (q15_t)0x6fe6, (q15_t)0xc1da, (q15_t)0x6fda, (q15_t)0xc1c4, (q15_t)0x6fcd, (q15_t)0xc1ae, + (q15_t)0x6fc1, (q15_t)0xc198, (q15_t)0x6fb5, (q15_t)0xc183, (q15_t)0x6fa9, (q15_t)0xc16d, (q15_t)0x6f9c, (q15_t)0xc157, + (q15_t)0x6f90, (q15_t)0xc141, (q15_t)0x6f84, (q15_t)0xc12b, (q15_t)0x6f77, (q15_t)0xc115, (q15_t)0x6f6b, (q15_t)0xc0ff, + (q15_t)0x6f5f, (q15_t)0xc0e9, (q15_t)0x6f52, (q15_t)0xc0d3, (q15_t)0x6f46, (q15_t)0xc0bd, (q15_t)0x6f39, (q15_t)0xc0a8, + (q15_t)0x6f2d, (q15_t)0xc092, (q15_t)0x6f20, (q15_t)0xc07c, (q15_t)0x6f14, (q15_t)0xc066, (q15_t)0x6f07, (q15_t)0xc050, + (q15_t)0x6efb, (q15_t)0xc03b, (q15_t)0x6eee, (q15_t)0xc025, (q15_t)0x6ee2, (q15_t)0xc00f, (q15_t)0x6ed5, (q15_t)0xbff9, + (q15_t)0x6ec9, (q15_t)0xbfe3, (q15_t)0x6ebc, (q15_t)0xbfce, (q15_t)0x6eaf, (q15_t)0xbfb8, (q15_t)0x6ea3, (q15_t)0xbfa2, + (q15_t)0x6e96, (q15_t)0xbf8d, (q15_t)0x6e89, (q15_t)0xbf77, (q15_t)0x6e7d, (q15_t)0xbf61, (q15_t)0x6e70, (q15_t)0xbf4b, + (q15_t)0x6e63, (q15_t)0xbf36, (q15_t)0x6e57, (q15_t)0xbf20, (q15_t)0x6e4a, (q15_t)0xbf0a, (q15_t)0x6e3d, (q15_t)0xbef5, + (q15_t)0x6e30, (q15_t)0xbedf, (q15_t)0x6e24, (q15_t)0xbeca, (q15_t)0x6e17, (q15_t)0xbeb4, (q15_t)0x6e0a, (q15_t)0xbe9e, + (q15_t)0x6dfd, (q15_t)0xbe89, (q15_t)0x6df0, (q15_t)0xbe73, (q15_t)0x6de3, (q15_t)0xbe5e, (q15_t)0x6dd6, (q15_t)0xbe48, + (q15_t)0x6dca, (q15_t)0xbe32, (q15_t)0x6dbd, (q15_t)0xbe1d, (q15_t)0x6db0, (q15_t)0xbe07, (q15_t)0x6da3, (q15_t)0xbdf2, + (q15_t)0x6d96, (q15_t)0xbddc, (q15_t)0x6d89, (q15_t)0xbdc7, (q15_t)0x6d7c, (q15_t)0xbdb1, (q15_t)0x6d6f, (q15_t)0xbd9c, + (q15_t)0x6d62, (q15_t)0xbd86, (q15_t)0x6d55, (q15_t)0xbd71, (q15_t)0x6d48, (q15_t)0xbd5b, (q15_t)0x6d3a, (q15_t)0xbd46, + (q15_t)0x6d2d, (q15_t)0xbd30, (q15_t)0x6d20, (q15_t)0xbd1b, (q15_t)0x6d13, (q15_t)0xbd06, (q15_t)0x6d06, (q15_t)0xbcf0, + (q15_t)0x6cf9, (q15_t)0xbcdb, (q15_t)0x6cec, (q15_t)0xbcc5, (q15_t)0x6cde, (q15_t)0xbcb0, (q15_t)0x6cd1, (q15_t)0xbc9b, + (q15_t)0x6cc4, (q15_t)0xbc85, (q15_t)0x6cb7, (q15_t)0xbc70, (q15_t)0x6ca9, (q15_t)0xbc5b, (q15_t)0x6c9c, (q15_t)0xbc45, + (q15_t)0x6c8f, (q15_t)0xbc30, (q15_t)0x6c81, (q15_t)0xbc1b, (q15_t)0x6c74, (q15_t)0xbc05, (q15_t)0x6c67, (q15_t)0xbbf0, + (q15_t)0x6c59, (q15_t)0xbbdb, (q15_t)0x6c4c, (q15_t)0xbbc5, (q15_t)0x6c3f, (q15_t)0xbbb0, (q15_t)0x6c31, (q15_t)0xbb9b, + (q15_t)0x6c24, (q15_t)0xbb86, (q15_t)0x6c16, (q15_t)0xbb70, (q15_t)0x6c09, (q15_t)0xbb5b, (q15_t)0x6bfb, (q15_t)0xbb46, + (q15_t)0x6bee, (q15_t)0xbb31, (q15_t)0x6be0, (q15_t)0xbb1c, (q15_t)0x6bd3, (q15_t)0xbb06, (q15_t)0x6bc5, (q15_t)0xbaf1, + (q15_t)0x6bb8, (q15_t)0xbadc, (q15_t)0x6baa, (q15_t)0xbac7, (q15_t)0x6b9c, (q15_t)0xbab2, (q15_t)0x6b8f, (q15_t)0xba9d, + (q15_t)0x6b81, (q15_t)0xba88, (q15_t)0x6b73, (q15_t)0xba73, (q15_t)0x6b66, (q15_t)0xba5d, (q15_t)0x6b58, (q15_t)0xba48, + (q15_t)0x6b4a, (q15_t)0xba33, (q15_t)0x6b3d, (q15_t)0xba1e, (q15_t)0x6b2f, (q15_t)0xba09, (q15_t)0x6b21, (q15_t)0xb9f4, + (q15_t)0x6b13, (q15_t)0xb9df, (q15_t)0x6b06, (q15_t)0xb9ca, (q15_t)0x6af8, (q15_t)0xb9b5, (q15_t)0x6aea, (q15_t)0xb9a0, + (q15_t)0x6adc, (q15_t)0xb98b, (q15_t)0x6ace, (q15_t)0xb976, (q15_t)0x6ac1, (q15_t)0xb961, (q15_t)0x6ab3, (q15_t)0xb94c, + (q15_t)0x6aa5, (q15_t)0xb937, (q15_t)0x6a97, (q15_t)0xb922, (q15_t)0x6a89, (q15_t)0xb90d, (q15_t)0x6a7b, (q15_t)0xb8f8, + (q15_t)0x6a6d, (q15_t)0xb8e4, (q15_t)0x6a5f, (q15_t)0xb8cf, (q15_t)0x6a51, (q15_t)0xb8ba, (q15_t)0x6a43, (q15_t)0xb8a5, + (q15_t)0x6a35, (q15_t)0xb890, (q15_t)0x6a27, (q15_t)0xb87b, (q15_t)0x6a19, (q15_t)0xb866, (q15_t)0x6a0b, (q15_t)0xb852, + (q15_t)0x69fd, (q15_t)0xb83d, (q15_t)0x69ef, (q15_t)0xb828, (q15_t)0x69e1, (q15_t)0xb813, (q15_t)0x69d3, (q15_t)0xb7fe, + (q15_t)0x69c4, (q15_t)0xb7ea, (q15_t)0x69b6, (q15_t)0xb7d5, (q15_t)0x69a8, (q15_t)0xb7c0, (q15_t)0x699a, (q15_t)0xb7ab, + (q15_t)0x698c, (q15_t)0xb797, (q15_t)0x697d, (q15_t)0xb782, (q15_t)0x696f, (q15_t)0xb76d, (q15_t)0x6961, (q15_t)0xb758, + (q15_t)0x6953, (q15_t)0xb744, (q15_t)0x6944, (q15_t)0xb72f, (q15_t)0x6936, (q15_t)0xb71a, (q15_t)0x6928, (q15_t)0xb706, + (q15_t)0x6919, (q15_t)0xb6f1, (q15_t)0x690b, (q15_t)0xb6dd, (q15_t)0x68fd, (q15_t)0xb6c8, (q15_t)0x68ee, (q15_t)0xb6b3, + (q15_t)0x68e0, (q15_t)0xb69f, (q15_t)0x68d1, (q15_t)0xb68a, (q15_t)0x68c3, (q15_t)0xb676, (q15_t)0x68b5, (q15_t)0xb661, + (q15_t)0x68a6, (q15_t)0xb64c, (q15_t)0x6898, (q15_t)0xb638, (q15_t)0x6889, (q15_t)0xb623, (q15_t)0x687b, (q15_t)0xb60f, + (q15_t)0x686c, (q15_t)0xb5fa, (q15_t)0x685e, (q15_t)0xb5e6, (q15_t)0x684f, (q15_t)0xb5d1, (q15_t)0x6840, (q15_t)0xb5bd, + (q15_t)0x6832, (q15_t)0xb5a8, (q15_t)0x6823, (q15_t)0xb594, (q15_t)0x6815, (q15_t)0xb57f, (q15_t)0x6806, (q15_t)0xb56b, + (q15_t)0x67f7, (q15_t)0xb557, (q15_t)0x67e9, (q15_t)0xb542, (q15_t)0x67da, (q15_t)0xb52e, (q15_t)0x67cb, (q15_t)0xb519, + (q15_t)0x67bd, (q15_t)0xb505, (q15_t)0x67ae, (q15_t)0xb4f1, (q15_t)0x679f, (q15_t)0xb4dc, (q15_t)0x6790, (q15_t)0xb4c8, + (q15_t)0x6782, (q15_t)0xb4b4, (q15_t)0x6773, (q15_t)0xb49f, (q15_t)0x6764, (q15_t)0xb48b, (q15_t)0x6755, (q15_t)0xb477, + (q15_t)0x6746, (q15_t)0xb462, (q15_t)0x6737, (q15_t)0xb44e, (q15_t)0x6729, (q15_t)0xb43a, (q15_t)0x671a, (q15_t)0xb426, + (q15_t)0x670b, (q15_t)0xb411, (q15_t)0x66fc, (q15_t)0xb3fd, (q15_t)0x66ed, (q15_t)0xb3e9, (q15_t)0x66de, (q15_t)0xb3d5, + (q15_t)0x66cf, (q15_t)0xb3c1, (q15_t)0x66c0, (q15_t)0xb3ac, (q15_t)0x66b1, (q15_t)0xb398, (q15_t)0x66a2, (q15_t)0xb384, + (q15_t)0x6693, (q15_t)0xb370, (q15_t)0x6684, (q15_t)0xb35c, (q15_t)0x6675, (q15_t)0xb348, (q15_t)0x6666, (q15_t)0xb334, + (q15_t)0x6657, (q15_t)0xb31f, (q15_t)0x6648, (q15_t)0xb30b, (q15_t)0x6639, (q15_t)0xb2f7, (q15_t)0x6629, (q15_t)0xb2e3, + (q15_t)0x661a, (q15_t)0xb2cf, (q15_t)0x660b, (q15_t)0xb2bb, (q15_t)0x65fc, (q15_t)0xb2a7, (q15_t)0x65ed, (q15_t)0xb293, + (q15_t)0x65dd, (q15_t)0xb27f, (q15_t)0x65ce, (q15_t)0xb26b, (q15_t)0x65bf, (q15_t)0xb257, (q15_t)0x65b0, (q15_t)0xb243, + (q15_t)0x65a0, (q15_t)0xb22f, (q15_t)0x6591, (q15_t)0xb21b, (q15_t)0x6582, (q15_t)0xb207, (q15_t)0x6573, (q15_t)0xb1f3, + (q15_t)0x6563, (q15_t)0xb1df, (q15_t)0x6554, (q15_t)0xb1cc, (q15_t)0x6545, (q15_t)0xb1b8, (q15_t)0x6535, (q15_t)0xb1a4, + (q15_t)0x6526, (q15_t)0xb190, (q15_t)0x6516, (q15_t)0xb17c, (q15_t)0x6507, (q15_t)0xb168, (q15_t)0x64f7, (q15_t)0xb154, + (q15_t)0x64e8, (q15_t)0xb141, (q15_t)0x64d9, (q15_t)0xb12d, (q15_t)0x64c9, (q15_t)0xb119, (q15_t)0x64ba, (q15_t)0xb105, + (q15_t)0x64aa, (q15_t)0xb0f1, (q15_t)0x649b, (q15_t)0xb0de, (q15_t)0x648b, (q15_t)0xb0ca, (q15_t)0x647b, (q15_t)0xb0b6, + (q15_t)0x646c, (q15_t)0xb0a2, (q15_t)0x645c, (q15_t)0xb08f, (q15_t)0x644d, (q15_t)0xb07b, (q15_t)0x643d, (q15_t)0xb067, + (q15_t)0x642d, (q15_t)0xb054, (q15_t)0x641e, (q15_t)0xb040, (q15_t)0x640e, (q15_t)0xb02c, (q15_t)0x63fe, (q15_t)0xb019, + (q15_t)0x63ef, (q15_t)0xb005, (q15_t)0x63df, (q15_t)0xaff1, (q15_t)0x63cf, (q15_t)0xafde, (q15_t)0x63c0, (q15_t)0xafca, + (q15_t)0x63b0, (q15_t)0xafb7, (q15_t)0x63a0, (q15_t)0xafa3, (q15_t)0x6390, (q15_t)0xaf90, (q15_t)0x6380, (q15_t)0xaf7c, + (q15_t)0x6371, (q15_t)0xaf69, (q15_t)0x6361, (q15_t)0xaf55, (q15_t)0x6351, (q15_t)0xaf41, (q15_t)0x6341, (q15_t)0xaf2e, + (q15_t)0x6331, (q15_t)0xaf1b, (q15_t)0x6321, (q15_t)0xaf07, (q15_t)0x6311, (q15_t)0xaef4, (q15_t)0x6301, (q15_t)0xaee0, + (q15_t)0x62f2, (q15_t)0xaecd, (q15_t)0x62e2, (q15_t)0xaeb9, (q15_t)0x62d2, (q15_t)0xaea6, (q15_t)0x62c2, (q15_t)0xae92, + (q15_t)0x62b2, (q15_t)0xae7f, (q15_t)0x62a2, (q15_t)0xae6c, (q15_t)0x6292, (q15_t)0xae58, (q15_t)0x6282, (q15_t)0xae45, + (q15_t)0x6271, (q15_t)0xae32, (q15_t)0x6261, (q15_t)0xae1e, (q15_t)0x6251, (q15_t)0xae0b, (q15_t)0x6241, (q15_t)0xadf8, + (q15_t)0x6231, (q15_t)0xade4, (q15_t)0x6221, (q15_t)0xadd1, (q15_t)0x6211, (q15_t)0xadbe, (q15_t)0x6201, (q15_t)0xadab, + (q15_t)0x61f1, (q15_t)0xad97, (q15_t)0x61e0, (q15_t)0xad84, (q15_t)0x61d0, (q15_t)0xad71, (q15_t)0x61c0, (q15_t)0xad5e, + (q15_t)0x61b0, (q15_t)0xad4b, (q15_t)0x619f, (q15_t)0xad37, (q15_t)0x618f, (q15_t)0xad24, (q15_t)0x617f, (q15_t)0xad11, + (q15_t)0x616f, (q15_t)0xacfe, (q15_t)0x615e, (q15_t)0xaceb, (q15_t)0x614e, (q15_t)0xacd8, (q15_t)0x613e, (q15_t)0xacc5, + (q15_t)0x612d, (q15_t)0xacb2, (q15_t)0x611d, (q15_t)0xac9e, (q15_t)0x610d, (q15_t)0xac8b, (q15_t)0x60fc, (q15_t)0xac78, + (q15_t)0x60ec, (q15_t)0xac65, (q15_t)0x60db, (q15_t)0xac52, (q15_t)0x60cb, (q15_t)0xac3f, (q15_t)0x60ba, (q15_t)0xac2c, + (q15_t)0x60aa, (q15_t)0xac19, (q15_t)0x6099, (q15_t)0xac06, (q15_t)0x6089, (q15_t)0xabf3, (q15_t)0x6078, (q15_t)0xabe0, + (q15_t)0x6068, (q15_t)0xabcd, (q15_t)0x6057, (q15_t)0xabbb, (q15_t)0x6047, (q15_t)0xaba8, (q15_t)0x6036, (q15_t)0xab95, + (q15_t)0x6026, (q15_t)0xab82, (q15_t)0x6015, (q15_t)0xab6f, (q15_t)0x6004, (q15_t)0xab5c, (q15_t)0x5ff4, (q15_t)0xab49, + (q15_t)0x5fe3, (q15_t)0xab36, (q15_t)0x5fd3, (q15_t)0xab24, (q15_t)0x5fc2, (q15_t)0xab11, (q15_t)0x5fb1, (q15_t)0xaafe, + (q15_t)0x5fa0, (q15_t)0xaaeb, (q15_t)0x5f90, (q15_t)0xaad8, (q15_t)0x5f7f, (q15_t)0xaac6, (q15_t)0x5f6e, (q15_t)0xaab3, + (q15_t)0x5f5e, (q15_t)0xaaa0, (q15_t)0x5f4d, (q15_t)0xaa8e, (q15_t)0x5f3c, (q15_t)0xaa7b, (q15_t)0x5f2b, (q15_t)0xaa68, + (q15_t)0x5f1a, (q15_t)0xaa55, (q15_t)0x5f0a, (q15_t)0xaa43, (q15_t)0x5ef9, (q15_t)0xaa30, (q15_t)0x5ee8, (q15_t)0xaa1d, + (q15_t)0x5ed7, (q15_t)0xaa0b, (q15_t)0x5ec6, (q15_t)0xa9f8, (q15_t)0x5eb5, (q15_t)0xa9e6, (q15_t)0x5ea4, (q15_t)0xa9d3, + (q15_t)0x5e93, (q15_t)0xa9c0, (q15_t)0x5e82, (q15_t)0xa9ae, (q15_t)0x5e71, (q15_t)0xa99b, (q15_t)0x5e60, (q15_t)0xa989, + (q15_t)0x5e50, (q15_t)0xa976, (q15_t)0x5e3f, (q15_t)0xa964, (q15_t)0x5e2d, (q15_t)0xa951, (q15_t)0x5e1c, (q15_t)0xa93f, + (q15_t)0x5e0b, (q15_t)0xa92c, (q15_t)0x5dfa, (q15_t)0xa91a, (q15_t)0x5de9, (q15_t)0xa907, (q15_t)0x5dd8, (q15_t)0xa8f5, + (q15_t)0x5dc7, (q15_t)0xa8e3, (q15_t)0x5db6, (q15_t)0xa8d0, (q15_t)0x5da5, (q15_t)0xa8be, (q15_t)0x5d94, (q15_t)0xa8ab, + (q15_t)0x5d83, (q15_t)0xa899, (q15_t)0x5d71, (q15_t)0xa887, (q15_t)0x5d60, (q15_t)0xa874, (q15_t)0x5d4f, (q15_t)0xa862, + (q15_t)0x5d3e, (q15_t)0xa850, (q15_t)0x5d2d, (q15_t)0xa83d, (q15_t)0x5d1b, (q15_t)0xa82b, (q15_t)0x5d0a, (q15_t)0xa819, + (q15_t)0x5cf9, (q15_t)0xa807, (q15_t)0x5ce8, (q15_t)0xa7f4, (q15_t)0x5cd6, (q15_t)0xa7e2, (q15_t)0x5cc5, (q15_t)0xa7d0, + (q15_t)0x5cb4, (q15_t)0xa7be, (q15_t)0x5ca2, (q15_t)0xa7ab, (q15_t)0x5c91, (q15_t)0xa799, (q15_t)0x5c80, (q15_t)0xa787, + (q15_t)0x5c6e, (q15_t)0xa775, (q15_t)0x5c5d, (q15_t)0xa763, (q15_t)0x5c4b, (q15_t)0xa751, (q15_t)0x5c3a, (q15_t)0xa73f, + (q15_t)0x5c29, (q15_t)0xa72c, (q15_t)0x5c17, (q15_t)0xa71a, (q15_t)0x5c06, (q15_t)0xa708, (q15_t)0x5bf4, (q15_t)0xa6f6, + (q15_t)0x5be3, (q15_t)0xa6e4, (q15_t)0x5bd1, (q15_t)0xa6d2, (q15_t)0x5bc0, (q15_t)0xa6c0, (q15_t)0x5bae, (q15_t)0xa6ae, + (q15_t)0x5b9d, (q15_t)0xa69c, (q15_t)0x5b8b, (q15_t)0xa68a, (q15_t)0x5b79, (q15_t)0xa678, (q15_t)0x5b68, (q15_t)0xa666, + (q15_t)0x5b56, (q15_t)0xa654, (q15_t)0x5b45, (q15_t)0xa642, (q15_t)0x5b33, (q15_t)0xa630, (q15_t)0x5b21, (q15_t)0xa61f, + (q15_t)0x5b10, (q15_t)0xa60d, (q15_t)0x5afe, (q15_t)0xa5fb, (q15_t)0x5aec, (q15_t)0xa5e9, (q15_t)0x5adb, (q15_t)0xa5d7, + (q15_t)0x5ac9, (q15_t)0xa5c5, (q15_t)0x5ab7, (q15_t)0xa5b3, (q15_t)0x5aa5, (q15_t)0xa5a2, (q15_t)0x5a94, (q15_t)0xa590, + (q15_t)0x5a82, (q15_t)0xa57e, (q15_t)0x5a70, (q15_t)0xa56c, (q15_t)0x5a5e, (q15_t)0xa55b, (q15_t)0x5a4d, (q15_t)0xa549, + (q15_t)0x5a3b, (q15_t)0xa537, (q15_t)0x5a29, (q15_t)0xa525, (q15_t)0x5a17, (q15_t)0xa514, (q15_t)0x5a05, (q15_t)0xa502, + (q15_t)0x59f3, (q15_t)0xa4f0, (q15_t)0x59e1, (q15_t)0xa4df, (q15_t)0x59d0, (q15_t)0xa4cd, (q15_t)0x59be, (q15_t)0xa4bb, + (q15_t)0x59ac, (q15_t)0xa4aa, (q15_t)0x599a, (q15_t)0xa498, (q15_t)0x5988, (q15_t)0xa487, (q15_t)0x5976, (q15_t)0xa475, + (q15_t)0x5964, (q15_t)0xa463, (q15_t)0x5952, (q15_t)0xa452, (q15_t)0x5940, (q15_t)0xa440, (q15_t)0x592e, (q15_t)0xa42f, + (q15_t)0x591c, (q15_t)0xa41d, (q15_t)0x590a, (q15_t)0xa40c, (q15_t)0x58f8, (q15_t)0xa3fa, (q15_t)0x58e6, (q15_t)0xa3e9, + (q15_t)0x58d4, (q15_t)0xa3d7, (q15_t)0x58c1, (q15_t)0xa3c6, (q15_t)0x58af, (q15_t)0xa3b5, (q15_t)0x589d, (q15_t)0xa3a3, + (q15_t)0x588b, (q15_t)0xa392, (q15_t)0x5879, (q15_t)0xa380, (q15_t)0x5867, (q15_t)0xa36f, (q15_t)0x5855, (q15_t)0xa35e, + (q15_t)0x5842, (q15_t)0xa34c, (q15_t)0x5830, (q15_t)0xa33b, (q15_t)0x581e, (q15_t)0xa32a, (q15_t)0x580c, (q15_t)0xa318, + (q15_t)0x57f9, (q15_t)0xa307, (q15_t)0x57e7, (q15_t)0xa2f6, (q15_t)0x57d5, (q15_t)0xa2e5, (q15_t)0x57c3, (q15_t)0xa2d3, + (q15_t)0x57b0, (q15_t)0xa2c2, (q15_t)0x579e, (q15_t)0xa2b1, (q15_t)0x578c, (q15_t)0xa2a0, (q15_t)0x5779, (q15_t)0xa28f, + (q15_t)0x5767, (q15_t)0xa27d, (q15_t)0x5755, (q15_t)0xa26c, (q15_t)0x5742, (q15_t)0xa25b, (q15_t)0x5730, (q15_t)0xa24a, + (q15_t)0x571d, (q15_t)0xa239, (q15_t)0x570b, (q15_t)0xa228, (q15_t)0x56f9, (q15_t)0xa217, (q15_t)0x56e6, (q15_t)0xa206, + (q15_t)0x56d4, (q15_t)0xa1f5, (q15_t)0x56c1, (q15_t)0xa1e4, (q15_t)0x56af, (q15_t)0xa1d3, (q15_t)0x569c, (q15_t)0xa1c1, + (q15_t)0x568a, (q15_t)0xa1b0, (q15_t)0x5677, (q15_t)0xa1a0, (q15_t)0x5665, (q15_t)0xa18f, (q15_t)0x5652, (q15_t)0xa17e, + (q15_t)0x5640, (q15_t)0xa16d, (q15_t)0x562d, (q15_t)0xa15c, (q15_t)0x561a, (q15_t)0xa14b, (q15_t)0x5608, (q15_t)0xa13a, + (q15_t)0x55f5, (q15_t)0xa129, (q15_t)0x55e3, (q15_t)0xa118, (q15_t)0x55d0, (q15_t)0xa107, (q15_t)0x55bd, (q15_t)0xa0f6, + (q15_t)0x55ab, (q15_t)0xa0e6, (q15_t)0x5598, (q15_t)0xa0d5, (q15_t)0x5585, (q15_t)0xa0c4, (q15_t)0x5572, (q15_t)0xa0b3, + (q15_t)0x5560, (q15_t)0xa0a2, (q15_t)0x554d, (q15_t)0xa092, (q15_t)0x553a, (q15_t)0xa081, (q15_t)0x5528, (q15_t)0xa070, + (q15_t)0x5515, (q15_t)0xa060, (q15_t)0x5502, (q15_t)0xa04f, (q15_t)0x54ef, (q15_t)0xa03e, (q15_t)0x54dc, (q15_t)0xa02d, + (q15_t)0x54ca, (q15_t)0xa01d, (q15_t)0x54b7, (q15_t)0xa00c, (q15_t)0x54a4, (q15_t)0x9ffc, (q15_t)0x5491, (q15_t)0x9feb, + (q15_t)0x547e, (q15_t)0x9fda, (q15_t)0x546b, (q15_t)0x9fca, (q15_t)0x5458, (q15_t)0x9fb9, (q15_t)0x5445, (q15_t)0x9fa9, + (q15_t)0x5433, (q15_t)0x9f98, (q15_t)0x5420, (q15_t)0x9f88, (q15_t)0x540d, (q15_t)0x9f77, (q15_t)0x53fa, (q15_t)0x9f67, + (q15_t)0x53e7, (q15_t)0x9f56, (q15_t)0x53d4, (q15_t)0x9f46, (q15_t)0x53c1, (q15_t)0x9f35, (q15_t)0x53ae, (q15_t)0x9f25, + (q15_t)0x539b, (q15_t)0x9f14, (q15_t)0x5388, (q15_t)0x9f04, (q15_t)0x5375, (q15_t)0x9ef3, (q15_t)0x5362, (q15_t)0x9ee3, + (q15_t)0x534e, (q15_t)0x9ed3, (q15_t)0x533b, (q15_t)0x9ec2, (q15_t)0x5328, (q15_t)0x9eb2, (q15_t)0x5315, (q15_t)0x9ea2, + (q15_t)0x5302, (q15_t)0x9e91, (q15_t)0x52ef, (q15_t)0x9e81, (q15_t)0x52dc, (q15_t)0x9e71, (q15_t)0x52c9, (q15_t)0x9e61, + (q15_t)0x52b5, (q15_t)0x9e50, (q15_t)0x52a2, (q15_t)0x9e40, (q15_t)0x528f, (q15_t)0x9e30, (q15_t)0x527c, (q15_t)0x9e20, + (q15_t)0x5269, (q15_t)0x9e0f, (q15_t)0x5255, (q15_t)0x9dff, (q15_t)0x5242, (q15_t)0x9def, (q15_t)0x522f, (q15_t)0x9ddf, + (q15_t)0x521c, (q15_t)0x9dcf, (q15_t)0x5208, (q15_t)0x9dbf, (q15_t)0x51f5, (q15_t)0x9daf, (q15_t)0x51e2, (q15_t)0x9d9f, + (q15_t)0x51ce, (q15_t)0x9d8f, (q15_t)0x51bb, (q15_t)0x9d7e, (q15_t)0x51a8, (q15_t)0x9d6e, (q15_t)0x5194, (q15_t)0x9d5e, + (q15_t)0x5181, (q15_t)0x9d4e, (q15_t)0x516e, (q15_t)0x9d3e, (q15_t)0x515a, (q15_t)0x9d2e, (q15_t)0x5147, (q15_t)0x9d1e, + (q15_t)0x5133, (q15_t)0x9d0e, (q15_t)0x5120, (q15_t)0x9cff, (q15_t)0x510c, (q15_t)0x9cef, (q15_t)0x50f9, (q15_t)0x9cdf, + (q15_t)0x50e5, (q15_t)0x9ccf, (q15_t)0x50d2, (q15_t)0x9cbf, (q15_t)0x50bf, (q15_t)0x9caf, (q15_t)0x50ab, (q15_t)0x9c9f, + (q15_t)0x5097, (q15_t)0x9c8f, (q15_t)0x5084, (q15_t)0x9c80, (q15_t)0x5070, (q15_t)0x9c70, (q15_t)0x505d, (q15_t)0x9c60, + (q15_t)0x5049, (q15_t)0x9c50, (q15_t)0x5036, (q15_t)0x9c40, (q15_t)0x5022, (q15_t)0x9c31, (q15_t)0x500f, (q15_t)0x9c21, + (q15_t)0x4ffb, (q15_t)0x9c11, (q15_t)0x4fe7, (q15_t)0x9c02, (q15_t)0x4fd4, (q15_t)0x9bf2, (q15_t)0x4fc0, (q15_t)0x9be2, + (q15_t)0x4fac, (q15_t)0x9bd3, (q15_t)0x4f99, (q15_t)0x9bc3, (q15_t)0x4f85, (q15_t)0x9bb3, (q15_t)0x4f71, (q15_t)0x9ba4, + (q15_t)0x4f5e, (q15_t)0x9b94, (q15_t)0x4f4a, (q15_t)0x9b85, (q15_t)0x4f36, (q15_t)0x9b75, (q15_t)0x4f22, (q15_t)0x9b65, + (q15_t)0x4f0f, (q15_t)0x9b56, (q15_t)0x4efb, (q15_t)0x9b46, (q15_t)0x4ee7, (q15_t)0x9b37, (q15_t)0x4ed3, (q15_t)0x9b27, + (q15_t)0x4ebf, (q15_t)0x9b18, (q15_t)0x4eac, (q15_t)0x9b09, (q15_t)0x4e98, (q15_t)0x9af9, (q15_t)0x4e84, (q15_t)0x9aea, + (q15_t)0x4e70, (q15_t)0x9ada, (q15_t)0x4e5c, (q15_t)0x9acb, (q15_t)0x4e48, (q15_t)0x9abb, (q15_t)0x4e34, (q15_t)0x9aac, + (q15_t)0x4e21, (q15_t)0x9a9d, (q15_t)0x4e0d, (q15_t)0x9a8d, (q15_t)0x4df9, (q15_t)0x9a7e, (q15_t)0x4de5, (q15_t)0x9a6f, + (q15_t)0x4dd1, (q15_t)0x9a60, (q15_t)0x4dbd, (q15_t)0x9a50, (q15_t)0x4da9, (q15_t)0x9a41, (q15_t)0x4d95, (q15_t)0x9a32, + (q15_t)0x4d81, (q15_t)0x9a23, (q15_t)0x4d6d, (q15_t)0x9a13, (q15_t)0x4d59, (q15_t)0x9a04, (q15_t)0x4d45, (q15_t)0x99f5, + (q15_t)0x4d31, (q15_t)0x99e6, (q15_t)0x4d1d, (q15_t)0x99d7, (q15_t)0x4d09, (q15_t)0x99c7, (q15_t)0x4cf5, (q15_t)0x99b8, + (q15_t)0x4ce1, (q15_t)0x99a9, (q15_t)0x4ccc, (q15_t)0x999a, (q15_t)0x4cb8, (q15_t)0x998b, (q15_t)0x4ca4, (q15_t)0x997c, + (q15_t)0x4c90, (q15_t)0x996d, (q15_t)0x4c7c, (q15_t)0x995e, (q15_t)0x4c68, (q15_t)0x994f, (q15_t)0x4c54, (q15_t)0x9940, + (q15_t)0x4c3f, (q15_t)0x9931, (q15_t)0x4c2b, (q15_t)0x9922, (q15_t)0x4c17, (q15_t)0x9913, (q15_t)0x4c03, (q15_t)0x9904, + (q15_t)0x4bef, (q15_t)0x98f5, (q15_t)0x4bda, (q15_t)0x98e6, (q15_t)0x4bc6, (q15_t)0x98d7, (q15_t)0x4bb2, (q15_t)0x98c9, + (q15_t)0x4b9e, (q15_t)0x98ba, (q15_t)0x4b89, (q15_t)0x98ab, (q15_t)0x4b75, (q15_t)0x989c, (q15_t)0x4b61, (q15_t)0x988d, + (q15_t)0x4b4c, (q15_t)0x987e, (q15_t)0x4b38, (q15_t)0x9870, (q15_t)0x4b24, (q15_t)0x9861, (q15_t)0x4b0f, (q15_t)0x9852, + (q15_t)0x4afb, (q15_t)0x9843, (q15_t)0x4ae7, (q15_t)0x9835, (q15_t)0x4ad2, (q15_t)0x9826, (q15_t)0x4abe, (q15_t)0x9817, + (q15_t)0x4aa9, (q15_t)0x9809, (q15_t)0x4a95, (q15_t)0x97fa, (q15_t)0x4a81, (q15_t)0x97eb, (q15_t)0x4a6c, (q15_t)0x97dd, + (q15_t)0x4a58, (q15_t)0x97ce, (q15_t)0x4a43, (q15_t)0x97c0, (q15_t)0x4a2f, (q15_t)0x97b1, (q15_t)0x4a1a, (q15_t)0x97a2, + (q15_t)0x4a06, (q15_t)0x9794, (q15_t)0x49f1, (q15_t)0x9785, (q15_t)0x49dd, (q15_t)0x9777, (q15_t)0x49c8, (q15_t)0x9768, + (q15_t)0x49b4, (q15_t)0x975a, (q15_t)0x499f, (q15_t)0x974b, (q15_t)0x498a, (q15_t)0x973d, (q15_t)0x4976, (q15_t)0x972f, + (q15_t)0x4961, (q15_t)0x9720, (q15_t)0x494d, (q15_t)0x9712, (q15_t)0x4938, (q15_t)0x9703, (q15_t)0x4923, (q15_t)0x96f5, + (q15_t)0x490f, (q15_t)0x96e7, (q15_t)0x48fa, (q15_t)0x96d8, (q15_t)0x48e6, (q15_t)0x96ca, (q15_t)0x48d1, (q15_t)0x96bc, + (q15_t)0x48bc, (q15_t)0x96ad, (q15_t)0x48a8, (q15_t)0x969f, (q15_t)0x4893, (q15_t)0x9691, (q15_t)0x487e, (q15_t)0x9683, + (q15_t)0x4869, (q15_t)0x9674, (q15_t)0x4855, (q15_t)0x9666, (q15_t)0x4840, (q15_t)0x9658, (q15_t)0x482b, (q15_t)0x964a, + (q15_t)0x4816, (q15_t)0x963c, (q15_t)0x4802, (q15_t)0x962d, (q15_t)0x47ed, (q15_t)0x961f, (q15_t)0x47d8, (q15_t)0x9611, + (q15_t)0x47c3, (q15_t)0x9603, (q15_t)0x47ae, (q15_t)0x95f5, (q15_t)0x479a, (q15_t)0x95e7, (q15_t)0x4785, (q15_t)0x95d9, + (q15_t)0x4770, (q15_t)0x95cb, (q15_t)0x475b, (q15_t)0x95bd, (q15_t)0x4746, (q15_t)0x95af, (q15_t)0x4731, (q15_t)0x95a1, + (q15_t)0x471c, (q15_t)0x9593, (q15_t)0x4708, (q15_t)0x9585, (q15_t)0x46f3, (q15_t)0x9577, (q15_t)0x46de, (q15_t)0x9569, + (q15_t)0x46c9, (q15_t)0x955b, (q15_t)0x46b4, (q15_t)0x954d, (q15_t)0x469f, (q15_t)0x953f, (q15_t)0x468a, (q15_t)0x9532, + (q15_t)0x4675, (q15_t)0x9524, (q15_t)0x4660, (q15_t)0x9516, (q15_t)0x464b, (q15_t)0x9508, (q15_t)0x4636, (q15_t)0x94fa, + (q15_t)0x4621, (q15_t)0x94ed, (q15_t)0x460c, (q15_t)0x94df, (q15_t)0x45f7, (q15_t)0x94d1, (q15_t)0x45e2, (q15_t)0x94c3, + (q15_t)0x45cd, (q15_t)0x94b6, (q15_t)0x45b8, (q15_t)0x94a8, (q15_t)0x45a3, (q15_t)0x949a, (q15_t)0x458d, (q15_t)0x948d, + (q15_t)0x4578, (q15_t)0x947f, (q15_t)0x4563, (q15_t)0x9471, (q15_t)0x454e, (q15_t)0x9464, (q15_t)0x4539, (q15_t)0x9456, + (q15_t)0x4524, (q15_t)0x9448, (q15_t)0x450f, (q15_t)0x943b, (q15_t)0x44fa, (q15_t)0x942d, (q15_t)0x44e4, (q15_t)0x9420, + (q15_t)0x44cf, (q15_t)0x9412, (q15_t)0x44ba, (q15_t)0x9405, (q15_t)0x44a5, (q15_t)0x93f7, (q15_t)0x4490, (q15_t)0x93ea, + (q15_t)0x447a, (q15_t)0x93dc, (q15_t)0x4465, (q15_t)0x93cf, (q15_t)0x4450, (q15_t)0x93c1, (q15_t)0x443b, (q15_t)0x93b4, + (q15_t)0x4425, (q15_t)0x93a7, (q15_t)0x4410, (q15_t)0x9399, (q15_t)0x43fb, (q15_t)0x938c, (q15_t)0x43e5, (q15_t)0x937f, + (q15_t)0x43d0, (q15_t)0x9371, (q15_t)0x43bb, (q15_t)0x9364, (q15_t)0x43a5, (q15_t)0x9357, (q15_t)0x4390, (q15_t)0x9349, + (q15_t)0x437b, (q15_t)0x933c, (q15_t)0x4365, (q15_t)0x932f, (q15_t)0x4350, (q15_t)0x9322, (q15_t)0x433b, (q15_t)0x9314, + (q15_t)0x4325, (q15_t)0x9307, (q15_t)0x4310, (q15_t)0x92fa, (q15_t)0x42fa, (q15_t)0x92ed, (q15_t)0x42e5, (q15_t)0x92e0, + (q15_t)0x42d0, (q15_t)0x92d3, (q15_t)0x42ba, (q15_t)0x92c6, (q15_t)0x42a5, (q15_t)0x92b8, (q15_t)0x428f, (q15_t)0x92ab, + (q15_t)0x427a, (q15_t)0x929e, (q15_t)0x4264, (q15_t)0x9291, (q15_t)0x424f, (q15_t)0x9284, (q15_t)0x4239, (q15_t)0x9277, + (q15_t)0x4224, (q15_t)0x926a, (q15_t)0x420e, (q15_t)0x925d, (q15_t)0x41f9, (q15_t)0x9250, (q15_t)0x41e3, (q15_t)0x9243, + (q15_t)0x41ce, (q15_t)0x9236, (q15_t)0x41b8, (q15_t)0x922a, (q15_t)0x41a2, (q15_t)0x921d, (q15_t)0x418d, (q15_t)0x9210, + (q15_t)0x4177, (q15_t)0x9203, (q15_t)0x4162, (q15_t)0x91f6, (q15_t)0x414c, (q15_t)0x91e9, (q15_t)0x4136, (q15_t)0x91dc, + (q15_t)0x4121, (q15_t)0x91d0, (q15_t)0x410b, (q15_t)0x91c3, (q15_t)0x40f6, (q15_t)0x91b6, (q15_t)0x40e0, (q15_t)0x91a9, + (q15_t)0x40ca, (q15_t)0x919d, (q15_t)0x40b5, (q15_t)0x9190, (q15_t)0x409f, (q15_t)0x9183, (q15_t)0x4089, (q15_t)0x9177, + (q15_t)0x4073, (q15_t)0x916a, (q15_t)0x405e, (q15_t)0x915d, (q15_t)0x4048, (q15_t)0x9151, (q15_t)0x4032, (q15_t)0x9144, + (q15_t)0x401d, (q15_t)0x9137, (q15_t)0x4007, (q15_t)0x912b, (q15_t)0x3ff1, (q15_t)0x911e, (q15_t)0x3fdb, (q15_t)0x9112, + (q15_t)0x3fc5, (q15_t)0x9105, (q15_t)0x3fb0, (q15_t)0x90f9, (q15_t)0x3f9a, (q15_t)0x90ec, (q15_t)0x3f84, (q15_t)0x90e0, + (q15_t)0x3f6e, (q15_t)0x90d3, (q15_t)0x3f58, (q15_t)0x90c7, (q15_t)0x3f43, (q15_t)0x90ba, (q15_t)0x3f2d, (q15_t)0x90ae, + (q15_t)0x3f17, (q15_t)0x90a1, (q15_t)0x3f01, (q15_t)0x9095, (q15_t)0x3eeb, (q15_t)0x9089, (q15_t)0x3ed5, (q15_t)0x907c, + (q15_t)0x3ebf, (q15_t)0x9070, (q15_t)0x3ea9, (q15_t)0x9064, (q15_t)0x3e93, (q15_t)0x9057, (q15_t)0x3e7d, (q15_t)0x904b, + (q15_t)0x3e68, (q15_t)0x903f, (q15_t)0x3e52, (q15_t)0x9033, (q15_t)0x3e3c, (q15_t)0x9026, (q15_t)0x3e26, (q15_t)0x901a, + (q15_t)0x3e10, (q15_t)0x900e, (q15_t)0x3dfa, (q15_t)0x9002, (q15_t)0x3de4, (q15_t)0x8ff6, (q15_t)0x3dce, (q15_t)0x8fea, + (q15_t)0x3db8, (q15_t)0x8fdd, (q15_t)0x3da2, (q15_t)0x8fd1, (q15_t)0x3d8c, (q15_t)0x8fc5, (q15_t)0x3d76, (q15_t)0x8fb9, + (q15_t)0x3d60, (q15_t)0x8fad, (q15_t)0x3d49, (q15_t)0x8fa1, (q15_t)0x3d33, (q15_t)0x8f95, (q15_t)0x3d1d, (q15_t)0x8f89, + (q15_t)0x3d07, (q15_t)0x8f7d, (q15_t)0x3cf1, (q15_t)0x8f71, (q15_t)0x3cdb, (q15_t)0x8f65, (q15_t)0x3cc5, (q15_t)0x8f59, + (q15_t)0x3caf, (q15_t)0x8f4d, (q15_t)0x3c99, (q15_t)0x8f41, (q15_t)0x3c83, (q15_t)0x8f35, (q15_t)0x3c6c, (q15_t)0x8f2a, + (q15_t)0x3c56, (q15_t)0x8f1e, (q15_t)0x3c40, (q15_t)0x8f12, (q15_t)0x3c2a, (q15_t)0x8f06, (q15_t)0x3c14, (q15_t)0x8efa, + (q15_t)0x3bfd, (q15_t)0x8eee, (q15_t)0x3be7, (q15_t)0x8ee3, (q15_t)0x3bd1, (q15_t)0x8ed7, (q15_t)0x3bbb, (q15_t)0x8ecb, + (q15_t)0x3ba5, (q15_t)0x8ebf, (q15_t)0x3b8e, (q15_t)0x8eb4, (q15_t)0x3b78, (q15_t)0x8ea8, (q15_t)0x3b62, (q15_t)0x8e9c, + (q15_t)0x3b4c, (q15_t)0x8e91, (q15_t)0x3b35, (q15_t)0x8e85, (q15_t)0x3b1f, (q15_t)0x8e7a, (q15_t)0x3b09, (q15_t)0x8e6e, + (q15_t)0x3af2, (q15_t)0x8e62, (q15_t)0x3adc, (q15_t)0x8e57, (q15_t)0x3ac6, (q15_t)0x8e4b, (q15_t)0x3aaf, (q15_t)0x8e40, + (q15_t)0x3a99, (q15_t)0x8e34, (q15_t)0x3a83, (q15_t)0x8e29, (q15_t)0x3a6c, (q15_t)0x8e1d, (q15_t)0x3a56, (q15_t)0x8e12, + (q15_t)0x3a40, (q15_t)0x8e06, (q15_t)0x3a29, (q15_t)0x8dfb, (q15_t)0x3a13, (q15_t)0x8def, (q15_t)0x39fd, (q15_t)0x8de4, + (q15_t)0x39e6, (q15_t)0x8dd9, (q15_t)0x39d0, (q15_t)0x8dcd, (q15_t)0x39b9, (q15_t)0x8dc2, (q15_t)0x39a3, (q15_t)0x8db7, + (q15_t)0x398c, (q15_t)0x8dab, (q15_t)0x3976, (q15_t)0x8da0, (q15_t)0x395f, (q15_t)0x8d95, (q15_t)0x3949, (q15_t)0x8d8a, + (q15_t)0x3932, (q15_t)0x8d7e, (q15_t)0x391c, (q15_t)0x8d73, (q15_t)0x3906, (q15_t)0x8d68, (q15_t)0x38ef, (q15_t)0x8d5d, + (q15_t)0x38d8, (q15_t)0x8d51, (q15_t)0x38c2, (q15_t)0x8d46, (q15_t)0x38ab, (q15_t)0x8d3b, (q15_t)0x3895, (q15_t)0x8d30, + (q15_t)0x387e, (q15_t)0x8d25, (q15_t)0x3868, (q15_t)0x8d1a, (q15_t)0x3851, (q15_t)0x8d0f, (q15_t)0x383b, (q15_t)0x8d04, + (q15_t)0x3824, (q15_t)0x8cf9, (q15_t)0x380d, (q15_t)0x8cee, (q15_t)0x37f7, (q15_t)0x8ce3, (q15_t)0x37e0, (q15_t)0x8cd8, + (q15_t)0x37ca, (q15_t)0x8ccd, (q15_t)0x37b3, (q15_t)0x8cc2, (q15_t)0x379c, (q15_t)0x8cb7, (q15_t)0x3786, (q15_t)0x8cac, + (q15_t)0x376f, (q15_t)0x8ca1, (q15_t)0x3758, (q15_t)0x8c96, (q15_t)0x3742, (q15_t)0x8c8b, (q15_t)0x372b, (q15_t)0x8c81, + (q15_t)0x3714, (q15_t)0x8c76, (q15_t)0x36fe, (q15_t)0x8c6b, (q15_t)0x36e7, (q15_t)0x8c60, (q15_t)0x36d0, (q15_t)0x8c55, + (q15_t)0x36ba, (q15_t)0x8c4b, (q15_t)0x36a3, (q15_t)0x8c40, (q15_t)0x368c, (q15_t)0x8c35, (q15_t)0x3675, (q15_t)0x8c2a, + (q15_t)0x365f, (q15_t)0x8c20, (q15_t)0x3648, (q15_t)0x8c15, (q15_t)0x3631, (q15_t)0x8c0a, (q15_t)0x361a, (q15_t)0x8c00, + (q15_t)0x3604, (q15_t)0x8bf5, (q15_t)0x35ed, (q15_t)0x8beb, (q15_t)0x35d6, (q15_t)0x8be0, (q15_t)0x35bf, (q15_t)0x8bd5, + (q15_t)0x35a8, (q15_t)0x8bcb, (q15_t)0x3592, (q15_t)0x8bc0, (q15_t)0x357b, (q15_t)0x8bb6, (q15_t)0x3564, (q15_t)0x8bab, + (q15_t)0x354d, (q15_t)0x8ba1, (q15_t)0x3536, (q15_t)0x8b96, (q15_t)0x351f, (q15_t)0x8b8c, (q15_t)0x3508, (q15_t)0x8b82, + (q15_t)0x34f2, (q15_t)0x8b77, (q15_t)0x34db, (q15_t)0x8b6d, (q15_t)0x34c4, (q15_t)0x8b62, (q15_t)0x34ad, (q15_t)0x8b58, + (q15_t)0x3496, (q15_t)0x8b4e, (q15_t)0x347f, (q15_t)0x8b43, (q15_t)0x3468, (q15_t)0x8b39, (q15_t)0x3451, (q15_t)0x8b2f, + (q15_t)0x343a, (q15_t)0x8b25, (q15_t)0x3423, (q15_t)0x8b1a, (q15_t)0x340c, (q15_t)0x8b10, (q15_t)0x33f5, (q15_t)0x8b06, + (q15_t)0x33de, (q15_t)0x8afc, (q15_t)0x33c7, (q15_t)0x8af1, (q15_t)0x33b0, (q15_t)0x8ae7, (q15_t)0x3399, (q15_t)0x8add, + (q15_t)0x3382, (q15_t)0x8ad3, (q15_t)0x336b, (q15_t)0x8ac9, (q15_t)0x3354, (q15_t)0x8abf, (q15_t)0x333d, (q15_t)0x8ab5, + (q15_t)0x3326, (q15_t)0x8aab, (q15_t)0x330f, (q15_t)0x8aa1, (q15_t)0x32f8, (q15_t)0x8a97, (q15_t)0x32e1, (q15_t)0x8a8d, + (q15_t)0x32ca, (q15_t)0x8a83, (q15_t)0x32b3, (q15_t)0x8a79, (q15_t)0x329c, (q15_t)0x8a6f, (q15_t)0x3285, (q15_t)0x8a65, + (q15_t)0x326e, (q15_t)0x8a5b, (q15_t)0x3257, (q15_t)0x8a51, (q15_t)0x3240, (q15_t)0x8a47, (q15_t)0x3228, (q15_t)0x8a3d, + (q15_t)0x3211, (q15_t)0x8a34, (q15_t)0x31fa, (q15_t)0x8a2a, (q15_t)0x31e3, (q15_t)0x8a20, (q15_t)0x31cc, (q15_t)0x8a16, + (q15_t)0x31b5, (q15_t)0x8a0c, (q15_t)0x319e, (q15_t)0x8a03, (q15_t)0x3186, (q15_t)0x89f9, (q15_t)0x316f, (q15_t)0x89ef, + (q15_t)0x3158, (q15_t)0x89e5, (q15_t)0x3141, (q15_t)0x89dc, (q15_t)0x312a, (q15_t)0x89d2, (q15_t)0x3112, (q15_t)0x89c8, + (q15_t)0x30fb, (q15_t)0x89bf, (q15_t)0x30e4, (q15_t)0x89b5, (q15_t)0x30cd, (q15_t)0x89ac, (q15_t)0x30b6, (q15_t)0x89a2, + (q15_t)0x309e, (q15_t)0x8998, (q15_t)0x3087, (q15_t)0x898f, (q15_t)0x3070, (q15_t)0x8985, (q15_t)0x3059, (q15_t)0x897c, + (q15_t)0x3041, (q15_t)0x8972, (q15_t)0x302a, (q15_t)0x8969, (q15_t)0x3013, (q15_t)0x8960, (q15_t)0x2ffb, (q15_t)0x8956, + (q15_t)0x2fe4, (q15_t)0x894d, (q15_t)0x2fcd, (q15_t)0x8943, (q15_t)0x2fb5, (q15_t)0x893a, (q15_t)0x2f9e, (q15_t)0x8931, + (q15_t)0x2f87, (q15_t)0x8927, (q15_t)0x2f6f, (q15_t)0x891e, (q15_t)0x2f58, (q15_t)0x8915, (q15_t)0x2f41, (q15_t)0x890b, + (q15_t)0x2f29, (q15_t)0x8902, (q15_t)0x2f12, (q15_t)0x88f9, (q15_t)0x2efb, (q15_t)0x88f0, (q15_t)0x2ee3, (q15_t)0x88e6, + (q15_t)0x2ecc, (q15_t)0x88dd, (q15_t)0x2eb5, (q15_t)0x88d4, (q15_t)0x2e9d, (q15_t)0x88cb, (q15_t)0x2e86, (q15_t)0x88c2, + (q15_t)0x2e6e, (q15_t)0x88b9, (q15_t)0x2e57, (q15_t)0x88af, (q15_t)0x2e3f, (q15_t)0x88a6, (q15_t)0x2e28, (q15_t)0x889d, + (q15_t)0x2e11, (q15_t)0x8894, (q15_t)0x2df9, (q15_t)0x888b, (q15_t)0x2de2, (q15_t)0x8882, (q15_t)0x2dca, (q15_t)0x8879, + (q15_t)0x2db3, (q15_t)0x8870, (q15_t)0x2d9b, (q15_t)0x8867, (q15_t)0x2d84, (q15_t)0x885e, (q15_t)0x2d6c, (q15_t)0x8855, + (q15_t)0x2d55, (q15_t)0x884c, (q15_t)0x2d3d, (q15_t)0x8844, (q15_t)0x2d26, (q15_t)0x883b, (q15_t)0x2d0e, (q15_t)0x8832, + (q15_t)0x2cf7, (q15_t)0x8829, (q15_t)0x2cdf, (q15_t)0x8820, (q15_t)0x2cc8, (q15_t)0x8817, (q15_t)0x2cb0, (q15_t)0x880f, + (q15_t)0x2c98, (q15_t)0x8806, (q15_t)0x2c81, (q15_t)0x87fd, (q15_t)0x2c69, (q15_t)0x87f4, (q15_t)0x2c52, (q15_t)0x87ec, + (q15_t)0x2c3a, (q15_t)0x87e3, (q15_t)0x2c23, (q15_t)0x87da, (q15_t)0x2c0b, (q15_t)0x87d2, (q15_t)0x2bf3, (q15_t)0x87c9, + (q15_t)0x2bdc, (q15_t)0x87c0, (q15_t)0x2bc4, (q15_t)0x87b8, (q15_t)0x2bad, (q15_t)0x87af, (q15_t)0x2b95, (q15_t)0x87a7, + (q15_t)0x2b7d, (q15_t)0x879e, (q15_t)0x2b66, (q15_t)0x8795, (q15_t)0x2b4e, (q15_t)0x878d, (q15_t)0x2b36, (q15_t)0x8784, + (q15_t)0x2b1f, (q15_t)0x877c, (q15_t)0x2b07, (q15_t)0x8774, (q15_t)0x2aef, (q15_t)0x876b, (q15_t)0x2ad8, (q15_t)0x8763, + (q15_t)0x2ac0, (q15_t)0x875a, (q15_t)0x2aa8, (q15_t)0x8752, (q15_t)0x2a91, (q15_t)0x874a, (q15_t)0x2a79, (q15_t)0x8741, + (q15_t)0x2a61, (q15_t)0x8739, (q15_t)0x2a49, (q15_t)0x8731, (q15_t)0x2a32, (q15_t)0x8728, (q15_t)0x2a1a, (q15_t)0x8720, + (q15_t)0x2a02, (q15_t)0x8718, (q15_t)0x29eb, (q15_t)0x870f, (q15_t)0x29d3, (q15_t)0x8707, (q15_t)0x29bb, (q15_t)0x86ff, + (q15_t)0x29a3, (q15_t)0x86f7, (q15_t)0x298b, (q15_t)0x86ef, (q15_t)0x2974, (q15_t)0x86e7, (q15_t)0x295c, (q15_t)0x86de, + (q15_t)0x2944, (q15_t)0x86d6, (q15_t)0x292c, (q15_t)0x86ce, (q15_t)0x2915, (q15_t)0x86c6, (q15_t)0x28fd, (q15_t)0x86be, + (q15_t)0x28e5, (q15_t)0x86b6, (q15_t)0x28cd, (q15_t)0x86ae, (q15_t)0x28b5, (q15_t)0x86a6, (q15_t)0x289d, (q15_t)0x869e, + (q15_t)0x2886, (q15_t)0x8696, (q15_t)0x286e, (q15_t)0x868e, (q15_t)0x2856, (q15_t)0x8686, (q15_t)0x283e, (q15_t)0x867e, + (q15_t)0x2826, (q15_t)0x8676, (q15_t)0x280e, (q15_t)0x866e, (q15_t)0x27f6, (q15_t)0x8667, (q15_t)0x27df, (q15_t)0x865f, + (q15_t)0x27c7, (q15_t)0x8657, (q15_t)0x27af, (q15_t)0x864f, (q15_t)0x2797, (q15_t)0x8647, (q15_t)0x277f, (q15_t)0x8640, + (q15_t)0x2767, (q15_t)0x8638, (q15_t)0x274f, (q15_t)0x8630, (q15_t)0x2737, (q15_t)0x8628, (q15_t)0x271f, (q15_t)0x8621, + (q15_t)0x2707, (q15_t)0x8619, (q15_t)0x26ef, (q15_t)0x8611, (q15_t)0x26d8, (q15_t)0x860a, (q15_t)0x26c0, (q15_t)0x8602, + (q15_t)0x26a8, (q15_t)0x85fb, (q15_t)0x2690, (q15_t)0x85f3, (q15_t)0x2678, (q15_t)0x85eb, (q15_t)0x2660, (q15_t)0x85e4, + (q15_t)0x2648, (q15_t)0x85dc, (q15_t)0x2630, (q15_t)0x85d5, (q15_t)0x2618, (q15_t)0x85cd, (q15_t)0x2600, (q15_t)0x85c6, + (q15_t)0x25e8, (q15_t)0x85be, (q15_t)0x25d0, (q15_t)0x85b7, (q15_t)0x25b8, (q15_t)0x85b0, (q15_t)0x25a0, (q15_t)0x85a8, + (q15_t)0x2588, (q15_t)0x85a1, (q15_t)0x2570, (q15_t)0x8599, (q15_t)0x2558, (q15_t)0x8592, (q15_t)0x2540, (q15_t)0x858b, + (q15_t)0x2528, (q15_t)0x8583, (q15_t)0x250f, (q15_t)0x857c, (q15_t)0x24f7, (q15_t)0x8575, (q15_t)0x24df, (q15_t)0x856e, + (q15_t)0x24c7, (q15_t)0x8566, (q15_t)0x24af, (q15_t)0x855f, (q15_t)0x2497, (q15_t)0x8558, (q15_t)0x247f, (q15_t)0x8551, + (q15_t)0x2467, (q15_t)0x854a, (q15_t)0x244f, (q15_t)0x8543, (q15_t)0x2437, (q15_t)0x853b, (q15_t)0x241f, (q15_t)0x8534, + (q15_t)0x2407, (q15_t)0x852d, (q15_t)0x23ee, (q15_t)0x8526, (q15_t)0x23d6, (q15_t)0x851f, (q15_t)0x23be, (q15_t)0x8518, + (q15_t)0x23a6, (q15_t)0x8511, (q15_t)0x238e, (q15_t)0x850a, (q15_t)0x2376, (q15_t)0x8503, (q15_t)0x235e, (q15_t)0x84fc, + (q15_t)0x2345, (q15_t)0x84f5, (q15_t)0x232d, (q15_t)0x84ee, (q15_t)0x2315, (q15_t)0x84e7, (q15_t)0x22fd, (q15_t)0x84e1, + (q15_t)0x22e5, (q15_t)0x84da, (q15_t)0x22cd, (q15_t)0x84d3, (q15_t)0x22b4, (q15_t)0x84cc, (q15_t)0x229c, (q15_t)0x84c5, + (q15_t)0x2284, (q15_t)0x84be, (q15_t)0x226c, (q15_t)0x84b8, (q15_t)0x2254, (q15_t)0x84b1, (q15_t)0x223b, (q15_t)0x84aa, + (q15_t)0x2223, (q15_t)0x84a3, (q15_t)0x220b, (q15_t)0x849d, (q15_t)0x21f3, (q15_t)0x8496, (q15_t)0x21da, (q15_t)0x848f, + (q15_t)0x21c2, (q15_t)0x8489, (q15_t)0x21aa, (q15_t)0x8482, (q15_t)0x2192, (q15_t)0x847c, (q15_t)0x2179, (q15_t)0x8475, + (q15_t)0x2161, (q15_t)0x846e, (q15_t)0x2149, (q15_t)0x8468, (q15_t)0x2131, (q15_t)0x8461, (q15_t)0x2118, (q15_t)0x845b, + (q15_t)0x2100, (q15_t)0x8454, (q15_t)0x20e8, (q15_t)0x844e, (q15_t)0x20d0, (q15_t)0x8447, (q15_t)0x20b7, (q15_t)0x8441, + (q15_t)0x209f, (q15_t)0x843b, (q15_t)0x2087, (q15_t)0x8434, (q15_t)0x206e, (q15_t)0x842e, (q15_t)0x2056, (q15_t)0x8427, + (q15_t)0x203e, (q15_t)0x8421, (q15_t)0x2025, (q15_t)0x841b, (q15_t)0x200d, (q15_t)0x8415, (q15_t)0x1ff5, (q15_t)0x840e, + (q15_t)0x1fdc, (q15_t)0x8408, (q15_t)0x1fc4, (q15_t)0x8402, (q15_t)0x1fac, (q15_t)0x83fb, (q15_t)0x1f93, (q15_t)0x83f5, + (q15_t)0x1f7b, (q15_t)0x83ef, (q15_t)0x1f63, (q15_t)0x83e9, (q15_t)0x1f4a, (q15_t)0x83e3, (q15_t)0x1f32, (q15_t)0x83dd, + (q15_t)0x1f19, (q15_t)0x83d7, (q15_t)0x1f01, (q15_t)0x83d0, (q15_t)0x1ee9, (q15_t)0x83ca, (q15_t)0x1ed0, (q15_t)0x83c4, + (q15_t)0x1eb8, (q15_t)0x83be, (q15_t)0x1ea0, (q15_t)0x83b8, (q15_t)0x1e87, (q15_t)0x83b2, (q15_t)0x1e6f, (q15_t)0x83ac, + (q15_t)0x1e56, (q15_t)0x83a6, (q15_t)0x1e3e, (q15_t)0x83a0, (q15_t)0x1e25, (q15_t)0x839a, (q15_t)0x1e0d, (q15_t)0x8394, + (q15_t)0x1df5, (q15_t)0x838f, (q15_t)0x1ddc, (q15_t)0x8389, (q15_t)0x1dc4, (q15_t)0x8383, (q15_t)0x1dab, (q15_t)0x837d, + (q15_t)0x1d93, (q15_t)0x8377, (q15_t)0x1d7a, (q15_t)0x8371, (q15_t)0x1d62, (q15_t)0x836c, (q15_t)0x1d49, (q15_t)0x8366, + (q15_t)0x1d31, (q15_t)0x8360, (q15_t)0x1d18, (q15_t)0x835a, (q15_t)0x1d00, (q15_t)0x8355, (q15_t)0x1ce8, (q15_t)0x834f, + (q15_t)0x1ccf, (q15_t)0x8349, (q15_t)0x1cb7, (q15_t)0x8344, (q15_t)0x1c9e, (q15_t)0x833e, (q15_t)0x1c86, (q15_t)0x8338, + (q15_t)0x1c6d, (q15_t)0x8333, (q15_t)0x1c55, (q15_t)0x832d, (q15_t)0x1c3c, (q15_t)0x8328, (q15_t)0x1c24, (q15_t)0x8322, + (q15_t)0x1c0b, (q15_t)0x831d, (q15_t)0x1bf2, (q15_t)0x8317, (q15_t)0x1bda, (q15_t)0x8312, (q15_t)0x1bc1, (q15_t)0x830c, + (q15_t)0x1ba9, (q15_t)0x8307, (q15_t)0x1b90, (q15_t)0x8301, (q15_t)0x1b78, (q15_t)0x82fc, (q15_t)0x1b5f, (q15_t)0x82f7, + (q15_t)0x1b47, (q15_t)0x82f1, (q15_t)0x1b2e, (q15_t)0x82ec, (q15_t)0x1b16, (q15_t)0x82e7, (q15_t)0x1afd, (q15_t)0x82e1, + (q15_t)0x1ae4, (q15_t)0x82dc, (q15_t)0x1acc, (q15_t)0x82d7, (q15_t)0x1ab3, (q15_t)0x82d1, (q15_t)0x1a9b, (q15_t)0x82cc, + (q15_t)0x1a82, (q15_t)0x82c7, (q15_t)0x1a6a, (q15_t)0x82c2, (q15_t)0x1a51, (q15_t)0x82bd, (q15_t)0x1a38, (q15_t)0x82b7, + (q15_t)0x1a20, (q15_t)0x82b2, (q15_t)0x1a07, (q15_t)0x82ad, (q15_t)0x19ef, (q15_t)0x82a8, (q15_t)0x19d6, (q15_t)0x82a3, + (q15_t)0x19bd, (q15_t)0x829e, (q15_t)0x19a5, (q15_t)0x8299, (q15_t)0x198c, (q15_t)0x8294, (q15_t)0x1973, (q15_t)0x828f, + (q15_t)0x195b, (q15_t)0x828a, (q15_t)0x1942, (q15_t)0x8285, (q15_t)0x192a, (q15_t)0x8280, (q15_t)0x1911, (q15_t)0x827b, + (q15_t)0x18f8, (q15_t)0x8276, (q15_t)0x18e0, (q15_t)0x8271, (q15_t)0x18c7, (q15_t)0x826c, (q15_t)0x18ae, (q15_t)0x8268, + (q15_t)0x1896, (q15_t)0x8263, (q15_t)0x187d, (q15_t)0x825e, (q15_t)0x1864, (q15_t)0x8259, (q15_t)0x184c, (q15_t)0x8254, + (q15_t)0x1833, (q15_t)0x8250, (q15_t)0x181a, (q15_t)0x824b, (q15_t)0x1802, (q15_t)0x8246, (q15_t)0x17e9, (q15_t)0x8241, + (q15_t)0x17d0, (q15_t)0x823d, (q15_t)0x17b7, (q15_t)0x8238, (q15_t)0x179f, (q15_t)0x8233, (q15_t)0x1786, (q15_t)0x822f, + (q15_t)0x176d, (q15_t)0x822a, (q15_t)0x1755, (q15_t)0x8226, (q15_t)0x173c, (q15_t)0x8221, (q15_t)0x1723, (q15_t)0x821c, + (q15_t)0x170a, (q15_t)0x8218, (q15_t)0x16f2, (q15_t)0x8213, (q15_t)0x16d9, (q15_t)0x820f, (q15_t)0x16c0, (q15_t)0x820a, + (q15_t)0x16a8, (q15_t)0x8206, (q15_t)0x168f, (q15_t)0x8201, (q15_t)0x1676, (q15_t)0x81fd, (q15_t)0x165d, (q15_t)0x81f9, + (q15_t)0x1645, (q15_t)0x81f4, (q15_t)0x162c, (q15_t)0x81f0, (q15_t)0x1613, (q15_t)0x81ec, (q15_t)0x15fa, (q15_t)0x81e7, + (q15_t)0x15e2, (q15_t)0x81e3, (q15_t)0x15c9, (q15_t)0x81df, (q15_t)0x15b0, (q15_t)0x81da, (q15_t)0x1597, (q15_t)0x81d6, + (q15_t)0x157f, (q15_t)0x81d2, (q15_t)0x1566, (q15_t)0x81ce, (q15_t)0x154d, (q15_t)0x81c9, (q15_t)0x1534, (q15_t)0x81c5, + (q15_t)0x151b, (q15_t)0x81c1, (q15_t)0x1503, (q15_t)0x81bd, (q15_t)0x14ea, (q15_t)0x81b9, (q15_t)0x14d1, (q15_t)0x81b5, + (q15_t)0x14b8, (q15_t)0x81b1, (q15_t)0x149f, (q15_t)0x81ad, (q15_t)0x1487, (q15_t)0x81a9, (q15_t)0x146e, (q15_t)0x81a5, + (q15_t)0x1455, (q15_t)0x81a1, (q15_t)0x143c, (q15_t)0x819d, (q15_t)0x1423, (q15_t)0x8199, (q15_t)0x140b, (q15_t)0x8195, + (q15_t)0x13f2, (q15_t)0x8191, (q15_t)0x13d9, (q15_t)0x818d, (q15_t)0x13c0, (q15_t)0x8189, (q15_t)0x13a7, (q15_t)0x8185, + (q15_t)0x138e, (q15_t)0x8181, (q15_t)0x1376, (q15_t)0x817d, (q15_t)0x135d, (q15_t)0x817a, (q15_t)0x1344, (q15_t)0x8176, + (q15_t)0x132b, (q15_t)0x8172, (q15_t)0x1312, (q15_t)0x816e, (q15_t)0x12f9, (q15_t)0x816b, (q15_t)0x12e0, (q15_t)0x8167, + (q15_t)0x12c8, (q15_t)0x8163, (q15_t)0x12af, (q15_t)0x815f, (q15_t)0x1296, (q15_t)0x815c, (q15_t)0x127d, (q15_t)0x8158, + (q15_t)0x1264, (q15_t)0x8155, (q15_t)0x124b, (q15_t)0x8151, (q15_t)0x1232, (q15_t)0x814d, (q15_t)0x1219, (q15_t)0x814a, + (q15_t)0x1201, (q15_t)0x8146, (q15_t)0x11e8, (q15_t)0x8143, (q15_t)0x11cf, (q15_t)0x813f, (q15_t)0x11b6, (q15_t)0x813c, + (q15_t)0x119d, (q15_t)0x8138, (q15_t)0x1184, (q15_t)0x8135, (q15_t)0x116b, (q15_t)0x8131, (q15_t)0x1152, (q15_t)0x812e, + (q15_t)0x1139, (q15_t)0x812b, (q15_t)0x1121, (q15_t)0x8127, (q15_t)0x1108, (q15_t)0x8124, (q15_t)0x10ef, (q15_t)0x8121, + (q15_t)0x10d6, (q15_t)0x811d, (q15_t)0x10bd, (q15_t)0x811a, (q15_t)0x10a4, (q15_t)0x8117, (q15_t)0x108b, (q15_t)0x8113, + (q15_t)0x1072, (q15_t)0x8110, (q15_t)0x1059, (q15_t)0x810d, (q15_t)0x1040, (q15_t)0x810a, (q15_t)0x1027, (q15_t)0x8107, + (q15_t)0x100e, (q15_t)0x8103, (q15_t)0xff5, (q15_t)0x8100, (q15_t)0xfdd, (q15_t)0x80fd, (q15_t)0xfc4, (q15_t)0x80fa, + (q15_t)0xfab, (q15_t)0x80f7, (q15_t)0xf92, (q15_t)0x80f4, (q15_t)0xf79, (q15_t)0x80f1, (q15_t)0xf60, (q15_t)0x80ee, + (q15_t)0xf47, (q15_t)0x80eb, (q15_t)0xf2e, (q15_t)0x80e8, (q15_t)0xf15, (q15_t)0x80e5, (q15_t)0xefc, (q15_t)0x80e2, + (q15_t)0xee3, (q15_t)0x80df, (q15_t)0xeca, (q15_t)0x80dc, (q15_t)0xeb1, (q15_t)0x80d9, (q15_t)0xe98, (q15_t)0x80d6, + (q15_t)0xe7f, (q15_t)0x80d3, (q15_t)0xe66, (q15_t)0x80d1, (q15_t)0xe4d, (q15_t)0x80ce, (q15_t)0xe34, (q15_t)0x80cb, + (q15_t)0xe1b, (q15_t)0x80c8, (q15_t)0xe02, (q15_t)0x80c5, (q15_t)0xde9, (q15_t)0x80c3, (q15_t)0xdd0, (q15_t)0x80c0, + (q15_t)0xdb7, (q15_t)0x80bd, (q15_t)0xd9e, (q15_t)0x80bb, (q15_t)0xd85, (q15_t)0x80b8, (q15_t)0xd6c, (q15_t)0x80b5, + (q15_t)0xd53, (q15_t)0x80b3, (q15_t)0xd3a, (q15_t)0x80b0, (q15_t)0xd21, (q15_t)0x80ad, (q15_t)0xd08, (q15_t)0x80ab, + (q15_t)0xcef, (q15_t)0x80a8, (q15_t)0xcd6, (q15_t)0x80a6, (q15_t)0xcbd, (q15_t)0x80a3, (q15_t)0xca4, (q15_t)0x80a1, + (q15_t)0xc8b, (q15_t)0x809e, (q15_t)0xc72, (q15_t)0x809c, (q15_t)0xc59, (q15_t)0x8099, (q15_t)0xc40, (q15_t)0x8097, + (q15_t)0xc27, (q15_t)0x8095, (q15_t)0xc0e, (q15_t)0x8092, (q15_t)0xbf5, (q15_t)0x8090, (q15_t)0xbdc, (q15_t)0x808e, + (q15_t)0xbc3, (q15_t)0x808b, (q15_t)0xbaa, (q15_t)0x8089, (q15_t)0xb91, (q15_t)0x8087, (q15_t)0xb78, (q15_t)0x8084, + (q15_t)0xb5f, (q15_t)0x8082, (q15_t)0xb46, (q15_t)0x8080, (q15_t)0xb2d, (q15_t)0x807e, (q15_t)0xb14, (q15_t)0x807b, + (q15_t)0xafb, (q15_t)0x8079, (q15_t)0xae2, (q15_t)0x8077, (q15_t)0xac9, (q15_t)0x8075, (q15_t)0xab0, (q15_t)0x8073, + (q15_t)0xa97, (q15_t)0x8071, (q15_t)0xa7e, (q15_t)0x806f, (q15_t)0xa65, (q15_t)0x806d, (q15_t)0xa4c, (q15_t)0x806b, + (q15_t)0xa33, (q15_t)0x8069, (q15_t)0xa19, (q15_t)0x8067, (q15_t)0xa00, (q15_t)0x8065, (q15_t)0x9e7, (q15_t)0x8063, + (q15_t)0x9ce, (q15_t)0x8061, (q15_t)0x9b5, (q15_t)0x805f, (q15_t)0x99c, (q15_t)0x805d, (q15_t)0x983, (q15_t)0x805b, + (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x951, (q15_t)0x8057, (q15_t)0x938, (q15_t)0x8056, (q15_t)0x91f, (q15_t)0x8054, + (q15_t)0x906, (q15_t)0x8052, (q15_t)0x8ed, (q15_t)0x8050, (q15_t)0x8d4, (q15_t)0x804f, (q15_t)0x8bb, (q15_t)0x804d, + (q15_t)0x8a2, (q15_t)0x804b, (q15_t)0x888, (q15_t)0x8049, (q15_t)0x86f, (q15_t)0x8048, (q15_t)0x856, (q15_t)0x8046, + (q15_t)0x83d, (q15_t)0x8044, (q15_t)0x824, (q15_t)0x8043, (q15_t)0x80b, (q15_t)0x8041, (q15_t)0x7f2, (q15_t)0x8040, + (q15_t)0x7d9, (q15_t)0x803e, (q15_t)0x7c0, (q15_t)0x803d, (q15_t)0x7a7, (q15_t)0x803b, (q15_t)0x78e, (q15_t)0x803a, + (q15_t)0x775, (q15_t)0x8038, (q15_t)0x75b, (q15_t)0x8037, (q15_t)0x742, (q15_t)0x8035, (q15_t)0x729, (q15_t)0x8034, + (q15_t)0x710, (q15_t)0x8032, (q15_t)0x6f7, (q15_t)0x8031, (q15_t)0x6de, (q15_t)0x8030, (q15_t)0x6c5, (q15_t)0x802e, + (q15_t)0x6ac, (q15_t)0x802d, (q15_t)0x693, (q15_t)0x802c, (q15_t)0x67a, (q15_t)0x802a, (q15_t)0x660, (q15_t)0x8029, + (q15_t)0x647, (q15_t)0x8028, (q15_t)0x62e, (q15_t)0x8027, (q15_t)0x615, (q15_t)0x8026, (q15_t)0x5fc, (q15_t)0x8024, + (q15_t)0x5e3, (q15_t)0x8023, (q15_t)0x5ca, (q15_t)0x8022, (q15_t)0x5b1, (q15_t)0x8021, (q15_t)0x598, (q15_t)0x8020, + (q15_t)0x57f, (q15_t)0x801f, (q15_t)0x565, (q15_t)0x801e, (q15_t)0x54c, (q15_t)0x801d, (q15_t)0x533, (q15_t)0x801c, + (q15_t)0x51a, (q15_t)0x801b, (q15_t)0x501, (q15_t)0x801a, (q15_t)0x4e8, (q15_t)0x8019, (q15_t)0x4cf, (q15_t)0x8018, + (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x49c, (q15_t)0x8016, (q15_t)0x483, (q15_t)0x8015, (q15_t)0x46a, (q15_t)0x8014, + (q15_t)0x451, (q15_t)0x8013, (q15_t)0x438, (q15_t)0x8012, (q15_t)0x41f, (q15_t)0x8012, (q15_t)0x406, (q15_t)0x8011, + (q15_t)0x3ed, (q15_t)0x8010, (q15_t)0x3d4, (q15_t)0x800f, (q15_t)0x3ba, (q15_t)0x800e, (q15_t)0x3a1, (q15_t)0x800e, + (q15_t)0x388, (q15_t)0x800d, (q15_t)0x36f, (q15_t)0x800c, (q15_t)0x356, (q15_t)0x800c, (q15_t)0x33d, (q15_t)0x800b, + (q15_t)0x324, (q15_t)0x800a, (q15_t)0x30b, (q15_t)0x800a, (q15_t)0x2f1, (q15_t)0x8009, (q15_t)0x2d8, (q15_t)0x8009, + (q15_t)0x2bf, (q15_t)0x8008, (q15_t)0x2a6, (q15_t)0x8008, (q15_t)0x28d, (q15_t)0x8007, (q15_t)0x274, (q15_t)0x8007, + (q15_t)0x25b, (q15_t)0x8006, (q15_t)0x242, (q15_t)0x8006, (q15_t)0x228, (q15_t)0x8005, (q15_t)0x20f, (q15_t)0x8005, + (q15_t)0x1f6, (q15_t)0x8004, (q15_t)0x1dd, (q15_t)0x8004, (q15_t)0x1c4, (q15_t)0x8004, (q15_t)0x1ab, (q15_t)0x8003, + (q15_t)0x192, (q15_t)0x8003, (q15_t)0x178, (q15_t)0x8003, (q15_t)0x15f, (q15_t)0x8002, (q15_t)0x146, (q15_t)0x8002, + (q15_t)0x12d, (q15_t)0x8002, (q15_t)0x114, (q15_t)0x8002, (q15_t)0xfb, (q15_t)0x8001, (q15_t)0xe2, (q15_t)0x8001, + (q15_t)0xc9, (q15_t)0x8001, (q15_t)0xaf, (q15_t)0x8001, (q15_t)0x96, (q15_t)0x8001, (q15_t)0x7d, (q15_t)0x8001, + (q15_t)0x64, (q15_t)0x8001, (q15_t)0x4b, (q15_t)0x8001, (q15_t)0x32, (q15_t)0x8001, (q15_t)0x19, (q15_t)0x8001 +}; + const q15_t __ALIGNED(4) cos_factorsQ15_2048[2048] = { + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffd, (q15_t)0x7ffd, + (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffa, + (q15_t)0x7ffa, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff6, + (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff4, (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff2, (q15_t)0x7ff1, (q15_t)0x7ff0, + (q15_t)0x7ff0, (q15_t)0x7fef, (q15_t)0x7fee, (q15_t)0x7fed, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7feb, (q15_t)0x7fea, + (q15_t)0x7fe9, (q15_t)0x7fe8, (q15_t)0x7fe7, (q15_t)0x7fe6, (q15_t)0x7fe5, (q15_t)0x7fe4, (q15_t)0x7fe3, (q15_t)0x7fe2, + (q15_t)0x7fe1, (q15_t)0x7fe0, (q15_t)0x7fdf, (q15_t)0x7fdd, (q15_t)0x7fdc, (q15_t)0x7fdb, (q15_t)0x7fda, (q15_t)0x7fd9, + (q15_t)0x7fd7, (q15_t)0x7fd6, (q15_t)0x7fd5, (q15_t)0x7fd4, (q15_t)0x7fd2, (q15_t)0x7fd1, (q15_t)0x7fd0, (q15_t)0x7fce, + (q15_t)0x7fcd, (q15_t)0x7fcb, (q15_t)0x7fca, (q15_t)0x7fc9, (q15_t)0x7fc7, (q15_t)0x7fc6, (q15_t)0x7fc4, (q15_t)0x7fc3, + (q15_t)0x7fc1, (q15_t)0x7fc0, (q15_t)0x7fbe, (q15_t)0x7fbc, (q15_t)0x7fbb, (q15_t)0x7fb9, (q15_t)0x7fb7, (q15_t)0x7fb6, + (q15_t)0x7fb4, (q15_t)0x7fb2, (q15_t)0x7fb1, (q15_t)0x7faf, (q15_t)0x7fad, (q15_t)0x7fab, (q15_t)0x7fa9, (q15_t)0x7fa8, + (q15_t)0x7fa6, (q15_t)0x7fa4, (q15_t)0x7fa2, (q15_t)0x7fa0, (q15_t)0x7f9e, (q15_t)0x7f9c, (q15_t)0x7f9a, (q15_t)0x7f98, + (q15_t)0x7f96, (q15_t)0x7f94, (q15_t)0x7f92, (q15_t)0x7f90, (q15_t)0x7f8e, (q15_t)0x7f8c, (q15_t)0x7f8a, (q15_t)0x7f88, + (q15_t)0x7f86, (q15_t)0x7f83, (q15_t)0x7f81, (q15_t)0x7f7f, (q15_t)0x7f7d, (q15_t)0x7f7b, (q15_t)0x7f78, (q15_t)0x7f76, + (q15_t)0x7f74, (q15_t)0x7f71, (q15_t)0x7f6f, (q15_t)0x7f6d, (q15_t)0x7f6a, (q15_t)0x7f68, (q15_t)0x7f65, (q15_t)0x7f63, + (q15_t)0x7f60, (q15_t)0x7f5e, (q15_t)0x7f5b, (q15_t)0x7f59, (q15_t)0x7f56, (q15_t)0x7f54, (q15_t)0x7f51, (q15_t)0x7f4f, + (q15_t)0x7f4c, (q15_t)0x7f49, (q15_t)0x7f47, (q15_t)0x7f44, (q15_t)0x7f41, (q15_t)0x7f3f, (q15_t)0x7f3c, (q15_t)0x7f39, + (q15_t)0x7f36, (q15_t)0x7f34, (q15_t)0x7f31, (q15_t)0x7f2e, (q15_t)0x7f2b, (q15_t)0x7f28, (q15_t)0x7f25, (q15_t)0x7f23, + (q15_t)0x7f20, (q15_t)0x7f1d, (q15_t)0x7f1a, (q15_t)0x7f17, (q15_t)0x7f14, (q15_t)0x7f11, (q15_t)0x7f0e, (q15_t)0x7f0b, + (q15_t)0x7f08, (q15_t)0x7f04, (q15_t)0x7f01, (q15_t)0x7efe, (q15_t)0x7efb, (q15_t)0x7ef8, (q15_t)0x7ef5, (q15_t)0x7ef1, + (q15_t)0x7eee, (q15_t)0x7eeb, (q15_t)0x7ee8, (q15_t)0x7ee4, (q15_t)0x7ee1, (q15_t)0x7ede, (q15_t)0x7eda, (q15_t)0x7ed7, + (q15_t)0x7ed4, (q15_t)0x7ed0, (q15_t)0x7ecd, (q15_t)0x7ec9, (q15_t)0x7ec6, (q15_t)0x7ec3, (q15_t)0x7ebf, (q15_t)0x7ebb, + (q15_t)0x7eb8, (q15_t)0x7eb4, (q15_t)0x7eb1, (q15_t)0x7ead, (q15_t)0x7eaa, (q15_t)0x7ea6, (q15_t)0x7ea2, (q15_t)0x7e9f, + (q15_t)0x7e9b, (q15_t)0x7e97, (q15_t)0x7e94, (q15_t)0x7e90, (q15_t)0x7e8c, (q15_t)0x7e88, (q15_t)0x7e84, (q15_t)0x7e81, + (q15_t)0x7e7d, (q15_t)0x7e79, (q15_t)0x7e75, (q15_t)0x7e71, (q15_t)0x7e6d, (q15_t)0x7e69, (q15_t)0x7e65, (q15_t)0x7e61, + (q15_t)0x7e5d, (q15_t)0x7e59, (q15_t)0x7e55, (q15_t)0x7e51, (q15_t)0x7e4d, (q15_t)0x7e49, (q15_t)0x7e45, (q15_t)0x7e41, + (q15_t)0x7e3d, (q15_t)0x7e39, (q15_t)0x7e34, (q15_t)0x7e30, (q15_t)0x7e2c, (q15_t)0x7e28, (q15_t)0x7e24, (q15_t)0x7e1f, + (q15_t)0x7e1b, (q15_t)0x7e17, (q15_t)0x7e12, (q15_t)0x7e0e, (q15_t)0x7e0a, (q15_t)0x7e05, (q15_t)0x7e01, (q15_t)0x7dfc, + (q15_t)0x7df8, (q15_t)0x7df3, (q15_t)0x7def, (q15_t)0x7dea, (q15_t)0x7de6, (q15_t)0x7de1, (q15_t)0x7ddd, (q15_t)0x7dd8, + (q15_t)0x7dd4, (q15_t)0x7dcf, (q15_t)0x7dca, (q15_t)0x7dc6, (q15_t)0x7dc1, (q15_t)0x7dbc, (q15_t)0x7db8, (q15_t)0x7db3, + (q15_t)0x7dae, (q15_t)0x7da9, (q15_t)0x7da5, (q15_t)0x7da0, (q15_t)0x7d9b, (q15_t)0x7d96, (q15_t)0x7d91, (q15_t)0x7d8c, + (q15_t)0x7d87, (q15_t)0x7d82, (q15_t)0x7d7e, (q15_t)0x7d79, (q15_t)0x7d74, (q15_t)0x7d6f, (q15_t)0x7d6a, (q15_t)0x7d65, + (q15_t)0x7d60, (q15_t)0x7d5a, (q15_t)0x7d55, (q15_t)0x7d50, (q15_t)0x7d4b, (q15_t)0x7d46, (q15_t)0x7d41, (q15_t)0x7d3c, + (q15_t)0x7d36, (q15_t)0x7d31, (q15_t)0x7d2c, (q15_t)0x7d27, (q15_t)0x7d21, (q15_t)0x7d1c, (q15_t)0x7d17, (q15_t)0x7d11, + (q15_t)0x7d0c, (q15_t)0x7d07, (q15_t)0x7d01, (q15_t)0x7cfc, (q15_t)0x7cf6, (q15_t)0x7cf1, (q15_t)0x7cec, (q15_t)0x7ce6, + (q15_t)0x7ce1, (q15_t)0x7cdb, (q15_t)0x7cd5, (q15_t)0x7cd0, (q15_t)0x7cca, (q15_t)0x7cc5, (q15_t)0x7cbf, (q15_t)0x7cb9, + (q15_t)0x7cb4, (q15_t)0x7cae, (q15_t)0x7ca8, (q15_t)0x7ca3, (q15_t)0x7c9d, (q15_t)0x7c97, (q15_t)0x7c91, (q15_t)0x7c8c, + (q15_t)0x7c86, (q15_t)0x7c80, (q15_t)0x7c7a, (q15_t)0x7c74, (q15_t)0x7c6e, (q15_t)0x7c69, (q15_t)0x7c63, (q15_t)0x7c5d, + (q15_t)0x7c57, (q15_t)0x7c51, (q15_t)0x7c4b, (q15_t)0x7c45, (q15_t)0x7c3f, (q15_t)0x7c39, (q15_t)0x7c33, (q15_t)0x7c2d, + (q15_t)0x7c26, (q15_t)0x7c20, (q15_t)0x7c1a, (q15_t)0x7c14, (q15_t)0x7c0e, (q15_t)0x7c08, (q15_t)0x7c01, (q15_t)0x7bfb, + (q15_t)0x7bf5, (q15_t)0x7bef, (q15_t)0x7be8, (q15_t)0x7be2, (q15_t)0x7bdc, (q15_t)0x7bd5, (q15_t)0x7bcf, (q15_t)0x7bc9, + (q15_t)0x7bc2, (q15_t)0x7bbc, (q15_t)0x7bb5, (q15_t)0x7baf, (q15_t)0x7ba8, (q15_t)0x7ba2, (q15_t)0x7b9b, (q15_t)0x7b95, + (q15_t)0x7b8e, (q15_t)0x7b88, (q15_t)0x7b81, (q15_t)0x7b7a, (q15_t)0x7b74, (q15_t)0x7b6d, (q15_t)0x7b67, (q15_t)0x7b60, + (q15_t)0x7b59, (q15_t)0x7b52, (q15_t)0x7b4c, (q15_t)0x7b45, (q15_t)0x7b3e, (q15_t)0x7b37, (q15_t)0x7b31, (q15_t)0x7b2a, + (q15_t)0x7b23, (q15_t)0x7b1c, (q15_t)0x7b15, (q15_t)0x7b0e, (q15_t)0x7b07, (q15_t)0x7b00, (q15_t)0x7af9, (q15_t)0x7af2, + (q15_t)0x7aeb, (q15_t)0x7ae4, (q15_t)0x7add, (q15_t)0x7ad6, (q15_t)0x7acf, (q15_t)0x7ac8, (q15_t)0x7ac1, (q15_t)0x7aba, + (q15_t)0x7ab3, (q15_t)0x7aac, (q15_t)0x7aa4, (q15_t)0x7a9d, (q15_t)0x7a96, (q15_t)0x7a8f, (q15_t)0x7a87, (q15_t)0x7a80, + (q15_t)0x7a79, (q15_t)0x7a72, (q15_t)0x7a6a, (q15_t)0x7a63, (q15_t)0x7a5c, (q15_t)0x7a54, (q15_t)0x7a4d, (q15_t)0x7a45, + (q15_t)0x7a3e, (q15_t)0x7a36, (q15_t)0x7a2f, (q15_t)0x7a27, (q15_t)0x7a20, (q15_t)0x7a18, (q15_t)0x7a11, (q15_t)0x7a09, + (q15_t)0x7a02, (q15_t)0x79fa, (q15_t)0x79f2, (q15_t)0x79eb, (q15_t)0x79e3, (q15_t)0x79db, (q15_t)0x79d4, (q15_t)0x79cc, + (q15_t)0x79c4, (q15_t)0x79bc, (q15_t)0x79b5, (q15_t)0x79ad, (q15_t)0x79a5, (q15_t)0x799d, (q15_t)0x7995, (q15_t)0x798e, + (q15_t)0x7986, (q15_t)0x797e, (q15_t)0x7976, (q15_t)0x796e, (q15_t)0x7966, (q15_t)0x795e, (q15_t)0x7956, (q15_t)0x794e, + (q15_t)0x7946, (q15_t)0x793e, (q15_t)0x7936, (q15_t)0x792e, (q15_t)0x7926, (q15_t)0x791e, (q15_t)0x7915, (q15_t)0x790d, + (q15_t)0x7905, (q15_t)0x78fd, (q15_t)0x78f5, (q15_t)0x78ec, (q15_t)0x78e4, (q15_t)0x78dc, (q15_t)0x78d4, (q15_t)0x78cb, + (q15_t)0x78c3, (q15_t)0x78bb, (q15_t)0x78b2, (q15_t)0x78aa, (q15_t)0x78a2, (q15_t)0x7899, (q15_t)0x7891, (q15_t)0x7888, + (q15_t)0x7880, (q15_t)0x7877, (q15_t)0x786f, (q15_t)0x7866, (q15_t)0x785e, (q15_t)0x7855, (q15_t)0x784d, (q15_t)0x7844, + (q15_t)0x783b, (q15_t)0x7833, (q15_t)0x782a, (q15_t)0x7821, (q15_t)0x7819, (q15_t)0x7810, (q15_t)0x7807, (q15_t)0x77ff, + (q15_t)0x77f6, (q15_t)0x77ed, (q15_t)0x77e4, (q15_t)0x77db, (q15_t)0x77d3, (q15_t)0x77ca, (q15_t)0x77c1, (q15_t)0x77b8, + (q15_t)0x77af, (q15_t)0x77a6, (q15_t)0x779d, (q15_t)0x7794, (q15_t)0x778b, (q15_t)0x7782, (q15_t)0x7779, (q15_t)0x7770, + (q15_t)0x7767, (q15_t)0x775e, (q15_t)0x7755, (q15_t)0x774c, (q15_t)0x7743, (q15_t)0x773a, (q15_t)0x7731, (q15_t)0x7727, + (q15_t)0x771e, (q15_t)0x7715, (q15_t)0x770c, (q15_t)0x7703, (q15_t)0x76f9, (q15_t)0x76f0, (q15_t)0x76e7, (q15_t)0x76dd, + (q15_t)0x76d4, (q15_t)0x76cb, (q15_t)0x76c1, (q15_t)0x76b8, (q15_t)0x76af, (q15_t)0x76a5, (q15_t)0x769c, (q15_t)0x7692, + (q15_t)0x7689, (q15_t)0x767f, (q15_t)0x7676, (q15_t)0x766c, (q15_t)0x7663, (q15_t)0x7659, (q15_t)0x7650, (q15_t)0x7646, + (q15_t)0x763c, (q15_t)0x7633, (q15_t)0x7629, (q15_t)0x761f, (q15_t)0x7616, (q15_t)0x760c, (q15_t)0x7602, (q15_t)0x75f9, + (q15_t)0x75ef, (q15_t)0x75e5, (q15_t)0x75db, (q15_t)0x75d1, (q15_t)0x75c8, (q15_t)0x75be, (q15_t)0x75b4, (q15_t)0x75aa, + (q15_t)0x75a0, (q15_t)0x7596, (q15_t)0x758c, (q15_t)0x7582, (q15_t)0x7578, (q15_t)0x756e, (q15_t)0x7564, (q15_t)0x755a, + (q15_t)0x7550, (q15_t)0x7546, (q15_t)0x753c, (q15_t)0x7532, (q15_t)0x7528, (q15_t)0x751e, (q15_t)0x7514, (q15_t)0x7509, + (q15_t)0x74ff, (q15_t)0x74f5, (q15_t)0x74eb, (q15_t)0x74e1, (q15_t)0x74d6, (q15_t)0x74cc, (q15_t)0x74c2, (q15_t)0x74b7, + (q15_t)0x74ad, (q15_t)0x74a3, (q15_t)0x7498, (q15_t)0x748e, (q15_t)0x7484, (q15_t)0x7479, (q15_t)0x746f, (q15_t)0x7464, + (q15_t)0x745a, (q15_t)0x744f, (q15_t)0x7445, (q15_t)0x743a, (q15_t)0x7430, (q15_t)0x7425, (q15_t)0x741b, (q15_t)0x7410, + (q15_t)0x7406, (q15_t)0x73fb, (q15_t)0x73f0, (q15_t)0x73e6, (q15_t)0x73db, (q15_t)0x73d0, (q15_t)0x73c6, (q15_t)0x73bb, + (q15_t)0x73b0, (q15_t)0x73a5, (q15_t)0x739b, (q15_t)0x7390, (q15_t)0x7385, (q15_t)0x737a, (q15_t)0x736f, (q15_t)0x7364, + (q15_t)0x7359, (q15_t)0x734f, (q15_t)0x7344, (q15_t)0x7339, (q15_t)0x732e, (q15_t)0x7323, (q15_t)0x7318, (q15_t)0x730d, + (q15_t)0x7302, (q15_t)0x72f7, (q15_t)0x72ec, (q15_t)0x72e1, (q15_t)0x72d5, (q15_t)0x72ca, (q15_t)0x72bf, (q15_t)0x72b4, + (q15_t)0x72a9, (q15_t)0x729e, (q15_t)0x7293, (q15_t)0x7287, (q15_t)0x727c, (q15_t)0x7271, (q15_t)0x7266, (q15_t)0x725a, + (q15_t)0x724f, (q15_t)0x7244, (q15_t)0x7238, (q15_t)0x722d, (q15_t)0x7222, (q15_t)0x7216, (q15_t)0x720b, (q15_t)0x71ff, + (q15_t)0x71f4, (q15_t)0x71e9, (q15_t)0x71dd, (q15_t)0x71d2, (q15_t)0x71c6, (q15_t)0x71bb, (q15_t)0x71af, (q15_t)0x71a3, + (q15_t)0x7198, (q15_t)0x718c, (q15_t)0x7181, (q15_t)0x7175, (q15_t)0x7169, (q15_t)0x715e, (q15_t)0x7152, (q15_t)0x7146, + (q15_t)0x713b, (q15_t)0x712f, (q15_t)0x7123, (q15_t)0x7117, (q15_t)0x710c, (q15_t)0x7100, (q15_t)0x70f4, (q15_t)0x70e8, + (q15_t)0x70dc, (q15_t)0x70d1, (q15_t)0x70c5, (q15_t)0x70b9, (q15_t)0x70ad, (q15_t)0x70a1, (q15_t)0x7095, (q15_t)0x7089, + (q15_t)0x707d, (q15_t)0x7071, (q15_t)0x7065, (q15_t)0x7059, (q15_t)0x704d, (q15_t)0x7041, (q15_t)0x7035, (q15_t)0x7029, + (q15_t)0x701d, (q15_t)0x7010, (q15_t)0x7004, (q15_t)0x6ff8, (q15_t)0x6fec, (q15_t)0x6fe0, (q15_t)0x6fd3, (q15_t)0x6fc7, + (q15_t)0x6fbb, (q15_t)0x6faf, (q15_t)0x6fa2, (q15_t)0x6f96, (q15_t)0x6f8a, (q15_t)0x6f7d, (q15_t)0x6f71, (q15_t)0x6f65, + (q15_t)0x6f58, (q15_t)0x6f4c, (q15_t)0x6f3f, (q15_t)0x6f33, (q15_t)0x6f27, (q15_t)0x6f1a, (q15_t)0x6f0e, (q15_t)0x6f01, + (q15_t)0x6ef5, (q15_t)0x6ee8, (q15_t)0x6edc, (q15_t)0x6ecf, (q15_t)0x6ec2, (q15_t)0x6eb6, (q15_t)0x6ea9, (q15_t)0x6e9c, + (q15_t)0x6e90, (q15_t)0x6e83, (q15_t)0x6e76, (q15_t)0x6e6a, (q15_t)0x6e5d, (q15_t)0x6e50, (q15_t)0x6e44, (q15_t)0x6e37, + (q15_t)0x6e2a, (q15_t)0x6e1d, (q15_t)0x6e10, (q15_t)0x6e04, (q15_t)0x6df7, (q15_t)0x6dea, (q15_t)0x6ddd, (q15_t)0x6dd0, + (q15_t)0x6dc3, (q15_t)0x6db6, (q15_t)0x6da9, (q15_t)0x6d9c, (q15_t)0x6d8f, (q15_t)0x6d82, (q15_t)0x6d75, (q15_t)0x6d68, + (q15_t)0x6d5b, (q15_t)0x6d4e, (q15_t)0x6d41, (q15_t)0x6d34, (q15_t)0x6d27, (q15_t)0x6d1a, (q15_t)0x6d0c, (q15_t)0x6cff, + (q15_t)0x6cf2, (q15_t)0x6ce5, (q15_t)0x6cd8, (q15_t)0x6cca, (q15_t)0x6cbd, (q15_t)0x6cb0, (q15_t)0x6ca3, (q15_t)0x6c95, + (q15_t)0x6c88, (q15_t)0x6c7b, (q15_t)0x6c6d, (q15_t)0x6c60, (q15_t)0x6c53, (q15_t)0x6c45, (q15_t)0x6c38, (q15_t)0x6c2a, + (q15_t)0x6c1d, (q15_t)0x6c0f, (q15_t)0x6c02, (q15_t)0x6bf5, (q15_t)0x6be7, (q15_t)0x6bd9, (q15_t)0x6bcc, (q15_t)0x6bbe, + (q15_t)0x6bb1, (q15_t)0x6ba3, (q15_t)0x6b96, (q15_t)0x6b88, (q15_t)0x6b7a, (q15_t)0x6b6d, (q15_t)0x6b5f, (q15_t)0x6b51, + (q15_t)0x6b44, (q15_t)0x6b36, (q15_t)0x6b28, (q15_t)0x6b1a, (q15_t)0x6b0d, (q15_t)0x6aff, (q15_t)0x6af1, (q15_t)0x6ae3, + (q15_t)0x6ad5, (q15_t)0x6ac8, (q15_t)0x6aba, (q15_t)0x6aac, (q15_t)0x6a9e, (q15_t)0x6a90, (q15_t)0x6a82, (q15_t)0x6a74, + (q15_t)0x6a66, (q15_t)0x6a58, (q15_t)0x6a4a, (q15_t)0x6a3c, (q15_t)0x6a2e, (q15_t)0x6a20, (q15_t)0x6a12, (q15_t)0x6a04, + (q15_t)0x69f6, (q15_t)0x69e8, (q15_t)0x69da, (q15_t)0x69cb, (q15_t)0x69bd, (q15_t)0x69af, (q15_t)0x69a1, (q15_t)0x6993, + (q15_t)0x6985, (q15_t)0x6976, (q15_t)0x6968, (q15_t)0x695a, (q15_t)0x694b, (q15_t)0x693d, (q15_t)0x692f, (q15_t)0x6921, + (q15_t)0x6912, (q15_t)0x6904, (q15_t)0x68f5, (q15_t)0x68e7, (q15_t)0x68d9, (q15_t)0x68ca, (q15_t)0x68bc, (q15_t)0x68ad, + (q15_t)0x689f, (q15_t)0x6890, (q15_t)0x6882, (q15_t)0x6873, (q15_t)0x6865, (q15_t)0x6856, (q15_t)0x6848, (q15_t)0x6839, + (q15_t)0x682b, (q15_t)0x681c, (q15_t)0x680d, (q15_t)0x67ff, (q15_t)0x67f0, (q15_t)0x67e1, (q15_t)0x67d3, (q15_t)0x67c4, + (q15_t)0x67b5, (q15_t)0x67a6, (q15_t)0x6798, (q15_t)0x6789, (q15_t)0x677a, (q15_t)0x676b, (q15_t)0x675d, (q15_t)0x674e, + (q15_t)0x673f, (q15_t)0x6730, (q15_t)0x6721, (q15_t)0x6712, (q15_t)0x6703, (q15_t)0x66f4, (q15_t)0x66e5, (q15_t)0x66d6, + (q15_t)0x66c8, (q15_t)0x66b9, (q15_t)0x66aa, (q15_t)0x669b, (q15_t)0x668b, (q15_t)0x667c, (q15_t)0x666d, (q15_t)0x665e, + (q15_t)0x664f, (q15_t)0x6640, (q15_t)0x6631, (q15_t)0x6622, (q15_t)0x6613, (q15_t)0x6603, (q15_t)0x65f4, (q15_t)0x65e5, + (q15_t)0x65d6, (q15_t)0x65c7, (q15_t)0x65b7, (q15_t)0x65a8, (q15_t)0x6599, (q15_t)0x658a, (q15_t)0x657a, (q15_t)0x656b, + (q15_t)0x655c, (q15_t)0x654c, (q15_t)0x653d, (q15_t)0x652d, (q15_t)0x651e, (q15_t)0x650f, (q15_t)0x64ff, (q15_t)0x64f0, + (q15_t)0x64e0, (q15_t)0x64d1, (q15_t)0x64c1, (q15_t)0x64b2, (q15_t)0x64a2, (q15_t)0x6493, (q15_t)0x6483, (q15_t)0x6474, + (q15_t)0x6464, (q15_t)0x6454, (q15_t)0x6445, (q15_t)0x6435, (q15_t)0x6426, (q15_t)0x6416, (q15_t)0x6406, (q15_t)0x63f7, + (q15_t)0x63e7, (q15_t)0x63d7, (q15_t)0x63c7, (q15_t)0x63b8, (q15_t)0x63a8, (q15_t)0x6398, (q15_t)0x6388, (q15_t)0x6378, + (q15_t)0x6369, (q15_t)0x6359, (q15_t)0x6349, (q15_t)0x6339, (q15_t)0x6329, (q15_t)0x6319, (q15_t)0x6309, (q15_t)0x62f9, + (q15_t)0x62ea, (q15_t)0x62da, (q15_t)0x62ca, (q15_t)0x62ba, (q15_t)0x62aa, (q15_t)0x629a, (q15_t)0x628a, (q15_t)0x627a, + (q15_t)0x6269, (q15_t)0x6259, (q15_t)0x6249, (q15_t)0x6239, (q15_t)0x6229, (q15_t)0x6219, (q15_t)0x6209, (q15_t)0x61f9, + (q15_t)0x61e8, (q15_t)0x61d8, (q15_t)0x61c8, (q15_t)0x61b8, (q15_t)0x61a8, (q15_t)0x6197, (q15_t)0x6187, (q15_t)0x6177, + (q15_t)0x6166, (q15_t)0x6156, (q15_t)0x6146, (q15_t)0x6135, (q15_t)0x6125, (q15_t)0x6115, (q15_t)0x6104, (q15_t)0x60f4, + (q15_t)0x60e4, (q15_t)0x60d3, (q15_t)0x60c3, (q15_t)0x60b2, (q15_t)0x60a2, (q15_t)0x6091, (q15_t)0x6081, (q15_t)0x6070, + (q15_t)0x6060, (q15_t)0x604f, (q15_t)0x603f, (q15_t)0x602e, (q15_t)0x601d, (q15_t)0x600d, (q15_t)0x5ffc, (q15_t)0x5fec, + (q15_t)0x5fdb, (q15_t)0x5fca, (q15_t)0x5fba, (q15_t)0x5fa9, (q15_t)0x5f98, (q15_t)0x5f87, (q15_t)0x5f77, (q15_t)0x5f66, + (q15_t)0x5f55, (q15_t)0x5f44, (q15_t)0x5f34, (q15_t)0x5f23, (q15_t)0x5f12, (q15_t)0x5f01, (q15_t)0x5ef0, (q15_t)0x5edf, + (q15_t)0x5ecf, (q15_t)0x5ebe, (q15_t)0x5ead, (q15_t)0x5e9c, (q15_t)0x5e8b, (q15_t)0x5e7a, (q15_t)0x5e69, (q15_t)0x5e58, + (q15_t)0x5e47, (q15_t)0x5e36, (q15_t)0x5e25, (q15_t)0x5e14, (q15_t)0x5e03, (q15_t)0x5df2, (q15_t)0x5de1, (q15_t)0x5dd0, + (q15_t)0x5dbf, (q15_t)0x5dad, (q15_t)0x5d9c, (q15_t)0x5d8b, (q15_t)0x5d7a, (q15_t)0x5d69, (q15_t)0x5d58, (q15_t)0x5d46, + (q15_t)0x5d35, (q15_t)0x5d24, (q15_t)0x5d13, (q15_t)0x5d01, (q15_t)0x5cf0, (q15_t)0x5cdf, (q15_t)0x5cce, (q15_t)0x5cbc, + (q15_t)0x5cab, (q15_t)0x5c9a, (q15_t)0x5c88, (q15_t)0x5c77, (q15_t)0x5c66, (q15_t)0x5c54, (q15_t)0x5c43, (q15_t)0x5c31, + (q15_t)0x5c20, (q15_t)0x5c0e, (q15_t)0x5bfd, (q15_t)0x5beb, (q15_t)0x5bda, (q15_t)0x5bc8, (q15_t)0x5bb7, (q15_t)0x5ba5, + (q15_t)0x5b94, (q15_t)0x5b82, (q15_t)0x5b71, (q15_t)0x5b5f, (q15_t)0x5b4d, (q15_t)0x5b3c, (q15_t)0x5b2a, (q15_t)0x5b19, + (q15_t)0x5b07, (q15_t)0x5af5, (q15_t)0x5ae4, (q15_t)0x5ad2, (q15_t)0x5ac0, (q15_t)0x5aae, (q15_t)0x5a9d, (q15_t)0x5a8b, + (q15_t)0x5a79, (q15_t)0x5a67, (q15_t)0x5a56, (q15_t)0x5a44, (q15_t)0x5a32, (q15_t)0x5a20, (q15_t)0x5a0e, (q15_t)0x59fc, + (q15_t)0x59ea, (q15_t)0x59d9, (q15_t)0x59c7, (q15_t)0x59b5, (q15_t)0x59a3, (q15_t)0x5991, (q15_t)0x597f, (q15_t)0x596d, + (q15_t)0x595b, (q15_t)0x5949, (q15_t)0x5937, (q15_t)0x5925, (q15_t)0x5913, (q15_t)0x5901, (q15_t)0x58ef, (q15_t)0x58dd, + (q15_t)0x58cb, (q15_t)0x58b8, (q15_t)0x58a6, (q15_t)0x5894, (q15_t)0x5882, (q15_t)0x5870, (q15_t)0x585e, (q15_t)0x584b, + (q15_t)0x5839, (q15_t)0x5827, (q15_t)0x5815, (q15_t)0x5803, (q15_t)0x57f0, (q15_t)0x57de, (q15_t)0x57cc, (q15_t)0x57b9, + (q15_t)0x57a7, (q15_t)0x5795, (q15_t)0x5783, (q15_t)0x5770, (q15_t)0x575e, (q15_t)0x574b, (q15_t)0x5739, (q15_t)0x5727, + (q15_t)0x5714, (q15_t)0x5702, (q15_t)0x56ef, (q15_t)0x56dd, (q15_t)0x56ca, (q15_t)0x56b8, (q15_t)0x56a5, (q15_t)0x5693, + (q15_t)0x5680, (q15_t)0x566e, (q15_t)0x565b, (q15_t)0x5649, (q15_t)0x5636, (q15_t)0x5624, (q15_t)0x5611, (q15_t)0x55fe, + (q15_t)0x55ec, (q15_t)0x55d9, (q15_t)0x55c7, (q15_t)0x55b4, (q15_t)0x55a1, (q15_t)0x558f, (q15_t)0x557c, (q15_t)0x5569, + (q15_t)0x5556, (q15_t)0x5544, (q15_t)0x5531, (q15_t)0x551e, (q15_t)0x550b, (q15_t)0x54f9, (q15_t)0x54e6, (q15_t)0x54d3, + (q15_t)0x54c0, (q15_t)0x54ad, (q15_t)0x549a, (q15_t)0x5488, (q15_t)0x5475, (q15_t)0x5462, (q15_t)0x544f, (q15_t)0x543c, + (q15_t)0x5429, (q15_t)0x5416, (q15_t)0x5403, (q15_t)0x53f0, (q15_t)0x53dd, (q15_t)0x53ca, (q15_t)0x53b7, (q15_t)0x53a4, + (q15_t)0x5391, (q15_t)0x537e, (q15_t)0x536b, (q15_t)0x5358, (q15_t)0x5345, (q15_t)0x5332, (q15_t)0x531f, (q15_t)0x530c, + (q15_t)0x52f8, (q15_t)0x52e5, (q15_t)0x52d2, (q15_t)0x52bf, (q15_t)0x52ac, (q15_t)0x5299, (q15_t)0x5285, (q15_t)0x5272, + (q15_t)0x525f, (q15_t)0x524c, (q15_t)0x5238, (q15_t)0x5225, (q15_t)0x5212, (q15_t)0x51ff, (q15_t)0x51eb, (q15_t)0x51d8, + (q15_t)0x51c5, (q15_t)0x51b1, (q15_t)0x519e, (q15_t)0x518b, (q15_t)0x5177, (q15_t)0x5164, (q15_t)0x5150, (q15_t)0x513d, + (q15_t)0x512a, (q15_t)0x5116, (q15_t)0x5103, (q15_t)0x50ef, (q15_t)0x50dc, (q15_t)0x50c8, (q15_t)0x50b5, (q15_t)0x50a1, + (q15_t)0x508e, (q15_t)0x507a, (q15_t)0x5067, (q15_t)0x5053, (q15_t)0x503f, (q15_t)0x502c, (q15_t)0x5018, (q15_t)0x5005, + (q15_t)0x4ff1, (q15_t)0x4fdd, (q15_t)0x4fca, (q15_t)0x4fb6, (q15_t)0x4fa2, (q15_t)0x4f8f, (q15_t)0x4f7b, (q15_t)0x4f67, + (q15_t)0x4f54, (q15_t)0x4f40, (q15_t)0x4f2c, (q15_t)0x4f18, (q15_t)0x4f05, (q15_t)0x4ef1, (q15_t)0x4edd, (q15_t)0x4ec9, + (q15_t)0x4eb6, (q15_t)0x4ea2, (q15_t)0x4e8e, (q15_t)0x4e7a, (q15_t)0x4e66, (q15_t)0x4e52, (q15_t)0x4e3e, (q15_t)0x4e2a, + (q15_t)0x4e17, (q15_t)0x4e03, (q15_t)0x4def, (q15_t)0x4ddb, (q15_t)0x4dc7, (q15_t)0x4db3, (q15_t)0x4d9f, (q15_t)0x4d8b, + (q15_t)0x4d77, (q15_t)0x4d63, (q15_t)0x4d4f, (q15_t)0x4d3b, (q15_t)0x4d27, (q15_t)0x4d13, (q15_t)0x4cff, (q15_t)0x4ceb, + (q15_t)0x4cd6, (q15_t)0x4cc2, (q15_t)0x4cae, (q15_t)0x4c9a, (q15_t)0x4c86, (q15_t)0x4c72, (q15_t)0x4c5e, (q15_t)0x4c49, + (q15_t)0x4c35, (q15_t)0x4c21, (q15_t)0x4c0d, (q15_t)0x4bf9, (q15_t)0x4be4, (q15_t)0x4bd0, (q15_t)0x4bbc, (q15_t)0x4ba8, + (q15_t)0x4b93, (q15_t)0x4b7f, (q15_t)0x4b6b, (q15_t)0x4b56, (q15_t)0x4b42, (q15_t)0x4b2e, (q15_t)0x4b19, (q15_t)0x4b05, + (q15_t)0x4af1, (q15_t)0x4adc, (q15_t)0x4ac8, (q15_t)0x4ab4, (q15_t)0x4a9f, (q15_t)0x4a8b, (q15_t)0x4a76, (q15_t)0x4a62, + (q15_t)0x4a4d, (q15_t)0x4a39, (q15_t)0x4a24, (q15_t)0x4a10, (q15_t)0x49fb, (q15_t)0x49e7, (q15_t)0x49d2, (q15_t)0x49be, + (q15_t)0x49a9, (q15_t)0x4995, (q15_t)0x4980, (q15_t)0x496c, (q15_t)0x4957, (q15_t)0x4942, (q15_t)0x492e, (q15_t)0x4919, + (q15_t)0x4905, (q15_t)0x48f0, (q15_t)0x48db, (q15_t)0x48c7, (q15_t)0x48b2, (q15_t)0x489d, (q15_t)0x4888, (q15_t)0x4874, + (q15_t)0x485f, (q15_t)0x484a, (q15_t)0x4836, (q15_t)0x4821, (q15_t)0x480c, (q15_t)0x47f7, (q15_t)0x47e2, (q15_t)0x47ce, + (q15_t)0x47b9, (q15_t)0x47a4, (q15_t)0x478f, (q15_t)0x477a, (q15_t)0x4765, (q15_t)0x4751, (q15_t)0x473c, (q15_t)0x4727, + (q15_t)0x4712, (q15_t)0x46fd, (q15_t)0x46e8, (q15_t)0x46d3, (q15_t)0x46be, (q15_t)0x46a9, (q15_t)0x4694, (q15_t)0x467f, + (q15_t)0x466a, (q15_t)0x4655, (q15_t)0x4640, (q15_t)0x462b, (q15_t)0x4616, (q15_t)0x4601, (q15_t)0x45ec, (q15_t)0x45d7, + (q15_t)0x45c2, (q15_t)0x45ad, (q15_t)0x4598, (q15_t)0x4583, (q15_t)0x456e, (q15_t)0x4559, (q15_t)0x4544, (q15_t)0x452e, + (q15_t)0x4519, (q15_t)0x4504, (q15_t)0x44ef, (q15_t)0x44da, (q15_t)0x44c5, (q15_t)0x44af, (q15_t)0x449a, (q15_t)0x4485, + (q15_t)0x4470, (q15_t)0x445a, (q15_t)0x4445, (q15_t)0x4430, (q15_t)0x441b, (q15_t)0x4405, (q15_t)0x43f0, (q15_t)0x43db, + (q15_t)0x43c5, (q15_t)0x43b0, (q15_t)0x439b, (q15_t)0x4385, (q15_t)0x4370, (q15_t)0x435b, (q15_t)0x4345, (q15_t)0x4330, + (q15_t)0x431b, (q15_t)0x4305, (q15_t)0x42f0, (q15_t)0x42da, (q15_t)0x42c5, (q15_t)0x42af, (q15_t)0x429a, (q15_t)0x4284, + (q15_t)0x426f, (q15_t)0x425a, (q15_t)0x4244, (q15_t)0x422f, (q15_t)0x4219, (q15_t)0x4203, (q15_t)0x41ee, (q15_t)0x41d8, + (q15_t)0x41c3, (q15_t)0x41ad, (q15_t)0x4198, (q15_t)0x4182, (q15_t)0x416d, (q15_t)0x4157, (q15_t)0x4141, (q15_t)0x412c, + (q15_t)0x4116, (q15_t)0x4100, (q15_t)0x40eb, (q15_t)0x40d5, (q15_t)0x40bf, (q15_t)0x40aa, (q15_t)0x4094, (q15_t)0x407e, + (q15_t)0x4069, (q15_t)0x4053, (q15_t)0x403d, (q15_t)0x4027, (q15_t)0x4012, (q15_t)0x3ffc, (q15_t)0x3fe6, (q15_t)0x3fd0, + (q15_t)0x3fbb, (q15_t)0x3fa5, (q15_t)0x3f8f, (q15_t)0x3f79, (q15_t)0x3f63, (q15_t)0x3f4d, (q15_t)0x3f38, (q15_t)0x3f22, + (q15_t)0x3f0c, (q15_t)0x3ef6, (q15_t)0x3ee0, (q15_t)0x3eca, (q15_t)0x3eb4, (q15_t)0x3e9e, (q15_t)0x3e88, (q15_t)0x3e73, + (q15_t)0x3e5d, (q15_t)0x3e47, (q15_t)0x3e31, (q15_t)0x3e1b, (q15_t)0x3e05, (q15_t)0x3def, (q15_t)0x3dd9, (q15_t)0x3dc3, + (q15_t)0x3dad, (q15_t)0x3d97, (q15_t)0x3d81, (q15_t)0x3d6b, (q15_t)0x3d55, (q15_t)0x3d3e, (q15_t)0x3d28, (q15_t)0x3d12, + (q15_t)0x3cfc, (q15_t)0x3ce6, (q15_t)0x3cd0, (q15_t)0x3cba, (q15_t)0x3ca4, (q15_t)0x3c8e, (q15_t)0x3c77, (q15_t)0x3c61, + (q15_t)0x3c4b, (q15_t)0x3c35, (q15_t)0x3c1f, (q15_t)0x3c09, (q15_t)0x3bf2, (q15_t)0x3bdc, (q15_t)0x3bc6, (q15_t)0x3bb0, + (q15_t)0x3b99, (q15_t)0x3b83, (q15_t)0x3b6d, (q15_t)0x3b57, (q15_t)0x3b40, (q15_t)0x3b2a, (q15_t)0x3b14, (q15_t)0x3afe, + (q15_t)0x3ae7, (q15_t)0x3ad1, (q15_t)0x3abb, (q15_t)0x3aa4, (q15_t)0x3a8e, (q15_t)0x3a78, (q15_t)0x3a61, (q15_t)0x3a4b, + (q15_t)0x3a34, (q15_t)0x3a1e, (q15_t)0x3a08, (q15_t)0x39f1, (q15_t)0x39db, (q15_t)0x39c4, (q15_t)0x39ae, (q15_t)0x3998, + (q15_t)0x3981, (q15_t)0x396b, (q15_t)0x3954, (q15_t)0x393e, (q15_t)0x3927, (q15_t)0x3911, (q15_t)0x38fa, (q15_t)0x38e4, + (q15_t)0x38cd, (q15_t)0x38b7, (q15_t)0x38a0, (q15_t)0x388a, (q15_t)0x3873, (q15_t)0x385d, (q15_t)0x3846, (q15_t)0x382f, + (q15_t)0x3819, (q15_t)0x3802, (q15_t)0x37ec, (q15_t)0x37d5, (q15_t)0x37be, (q15_t)0x37a8, (q15_t)0x3791, (q15_t)0x377a, + (q15_t)0x3764, (q15_t)0x374d, (q15_t)0x3736, (q15_t)0x3720, (q15_t)0x3709, (q15_t)0x36f2, (q15_t)0x36dc, (q15_t)0x36c5, + (q15_t)0x36ae, (q15_t)0x3698, (q15_t)0x3681, (q15_t)0x366a, (q15_t)0x3653, (q15_t)0x363d, (q15_t)0x3626, (q15_t)0x360f, + (q15_t)0x35f8, (q15_t)0x35e1, (q15_t)0x35cb, (q15_t)0x35b4, (q15_t)0x359d, (q15_t)0x3586, (q15_t)0x356f, (q15_t)0x3558, + (q15_t)0x3542, (q15_t)0x352b, (q15_t)0x3514, (q15_t)0x34fd, (q15_t)0x34e6, (q15_t)0x34cf, (q15_t)0x34b8, (q15_t)0x34a1, + (q15_t)0x348b, (q15_t)0x3474, (q15_t)0x345d, (q15_t)0x3446, (q15_t)0x342f, (q15_t)0x3418, (q15_t)0x3401, (q15_t)0x33ea, + (q15_t)0x33d3, (q15_t)0x33bc, (q15_t)0x33a5, (q15_t)0x338e, (q15_t)0x3377, (q15_t)0x3360, (q15_t)0x3349, (q15_t)0x3332, + (q15_t)0x331b, (q15_t)0x3304, (q15_t)0x32ed, (q15_t)0x32d6, (q15_t)0x32bf, (q15_t)0x32a8, (q15_t)0x3290, (q15_t)0x3279, + (q15_t)0x3262, (q15_t)0x324b, (q15_t)0x3234, (q15_t)0x321d, (q15_t)0x3206, (q15_t)0x31ef, (q15_t)0x31d8, (q15_t)0x31c0, + (q15_t)0x31a9, (q15_t)0x3192, (q15_t)0x317b, (q15_t)0x3164, (q15_t)0x314c, (q15_t)0x3135, (q15_t)0x311e, (q15_t)0x3107, + (q15_t)0x30f0, (q15_t)0x30d8, (q15_t)0x30c1, (q15_t)0x30aa, (q15_t)0x3093, (q15_t)0x307b, (q15_t)0x3064, (q15_t)0x304d, + (q15_t)0x3036, (q15_t)0x301e, (q15_t)0x3007, (q15_t)0x2ff0, (q15_t)0x2fd8, (q15_t)0x2fc1, (q15_t)0x2faa, (q15_t)0x2f92, + (q15_t)0x2f7b, (q15_t)0x2f64, (q15_t)0x2f4c, (q15_t)0x2f35, (q15_t)0x2f1e, (q15_t)0x2f06, (q15_t)0x2eef, (q15_t)0x2ed8, + (q15_t)0x2ec0, (q15_t)0x2ea9, (q15_t)0x2e91, (q15_t)0x2e7a, (q15_t)0x2e63, (q15_t)0x2e4b, (q15_t)0x2e34, (q15_t)0x2e1c, + (q15_t)0x2e05, (q15_t)0x2ded, (q15_t)0x2dd6, (q15_t)0x2dbe, (q15_t)0x2da7, (q15_t)0x2d8f, (q15_t)0x2d78, (q15_t)0x2d60, + (q15_t)0x2d49, (q15_t)0x2d31, (q15_t)0x2d1a, (q15_t)0x2d02, (q15_t)0x2ceb, (q15_t)0x2cd3, (q15_t)0x2cbc, (q15_t)0x2ca4, + (q15_t)0x2c8d, (q15_t)0x2c75, (q15_t)0x2c5e, (q15_t)0x2c46, (q15_t)0x2c2e, (q15_t)0x2c17, (q15_t)0x2bff, (q15_t)0x2be8, + (q15_t)0x2bd0, (q15_t)0x2bb8, (q15_t)0x2ba1, (q15_t)0x2b89, (q15_t)0x2b71, (q15_t)0x2b5a, (q15_t)0x2b42, (q15_t)0x2b2b, + (q15_t)0x2b13, (q15_t)0x2afb, (q15_t)0x2ae4, (q15_t)0x2acc, (q15_t)0x2ab4, (q15_t)0x2a9c, (q15_t)0x2a85, (q15_t)0x2a6d, + (q15_t)0x2a55, (q15_t)0x2a3e, (q15_t)0x2a26, (q15_t)0x2a0e, (q15_t)0x29f6, (q15_t)0x29df, (q15_t)0x29c7, (q15_t)0x29af, + (q15_t)0x2997, (q15_t)0x2980, (q15_t)0x2968, (q15_t)0x2950, (q15_t)0x2938, (q15_t)0x2920, (q15_t)0x2909, (q15_t)0x28f1, + (q15_t)0x28d9, (q15_t)0x28c1, (q15_t)0x28a9, (q15_t)0x2892, (q15_t)0x287a, (q15_t)0x2862, (q15_t)0x284a, (q15_t)0x2832, + (q15_t)0x281a, (q15_t)0x2802, (q15_t)0x27eb, (q15_t)0x27d3, (q15_t)0x27bb, (q15_t)0x27a3, (q15_t)0x278b, (q15_t)0x2773, + (q15_t)0x275b, (q15_t)0x2743, (q15_t)0x272b, (q15_t)0x2713, (q15_t)0x26fb, (q15_t)0x26e4, (q15_t)0x26cc, (q15_t)0x26b4, + (q15_t)0x269c, (q15_t)0x2684, (q15_t)0x266c, (q15_t)0x2654, (q15_t)0x263c, (q15_t)0x2624, (q15_t)0x260c, (q15_t)0x25f4, + (q15_t)0x25dc, (q15_t)0x25c4, (q15_t)0x25ac, (q15_t)0x2594, (q15_t)0x257c, (q15_t)0x2564, (q15_t)0x254c, (q15_t)0x2534, + (q15_t)0x251c, (q15_t)0x2503, (q15_t)0x24eb, (q15_t)0x24d3, (q15_t)0x24bb, (q15_t)0x24a3, (q15_t)0x248b, (q15_t)0x2473, + (q15_t)0x245b, (q15_t)0x2443, (q15_t)0x242b, (q15_t)0x2413, (q15_t)0x23fa, (q15_t)0x23e2, (q15_t)0x23ca, (q15_t)0x23b2, + (q15_t)0x239a, (q15_t)0x2382, (q15_t)0x236a, (q15_t)0x2352, (q15_t)0x2339, (q15_t)0x2321, (q15_t)0x2309, (q15_t)0x22f1, + (q15_t)0x22d9, (q15_t)0x22c0, (q15_t)0x22a8, (q15_t)0x2290, (q15_t)0x2278, (q15_t)0x2260, (q15_t)0x2247, (q15_t)0x222f, + (q15_t)0x2217, (q15_t)0x21ff, (q15_t)0x21e7, (q15_t)0x21ce, (q15_t)0x21b6, (q15_t)0x219e, (q15_t)0x2186, (q15_t)0x216d, + (q15_t)0x2155, (q15_t)0x213d, (q15_t)0x2125, (q15_t)0x210c, (q15_t)0x20f4, (q15_t)0x20dc, (q15_t)0x20c3, (q15_t)0x20ab, + (q15_t)0x2093, (q15_t)0x207a, (q15_t)0x2062, (q15_t)0x204a, (q15_t)0x2032, (q15_t)0x2019, (q15_t)0x2001, (q15_t)0x1fe9, + (q15_t)0x1fd0, (q15_t)0x1fb8, (q15_t)0x1f9f, (q15_t)0x1f87, (q15_t)0x1f6f, (q15_t)0x1f56, (q15_t)0x1f3e, (q15_t)0x1f26, + (q15_t)0x1f0d, (q15_t)0x1ef5, (q15_t)0x1edd, (q15_t)0x1ec4, (q15_t)0x1eac, (q15_t)0x1e93, (q15_t)0x1e7b, (q15_t)0x1e62, + (q15_t)0x1e4a, (q15_t)0x1e32, (q15_t)0x1e19, (q15_t)0x1e01, (q15_t)0x1de8, (q15_t)0x1dd0, (q15_t)0x1db7, (q15_t)0x1d9f, + (q15_t)0x1d87, (q15_t)0x1d6e, (q15_t)0x1d56, (q15_t)0x1d3d, (q15_t)0x1d25, (q15_t)0x1d0c, (q15_t)0x1cf4, (q15_t)0x1cdb, + (q15_t)0x1cc3, (q15_t)0x1caa, (q15_t)0x1c92, (q15_t)0x1c79, (q15_t)0x1c61, (q15_t)0x1c48, (q15_t)0x1c30, (q15_t)0x1c17, + (q15_t)0x1bff, (q15_t)0x1be6, (q15_t)0x1bce, (q15_t)0x1bb5, (q15_t)0x1b9d, (q15_t)0x1b84, (q15_t)0x1b6c, (q15_t)0x1b53, + (q15_t)0x1b3a, (q15_t)0x1b22, (q15_t)0x1b09, (q15_t)0x1af1, (q15_t)0x1ad8, (q15_t)0x1ac0, (q15_t)0x1aa7, (q15_t)0x1a8e, + (q15_t)0x1a76, (q15_t)0x1a5d, (q15_t)0x1a45, (q15_t)0x1a2c, (q15_t)0x1a13, (q15_t)0x19fb, (q15_t)0x19e2, (q15_t)0x19ca, + (q15_t)0x19b1, (q15_t)0x1998, (q15_t)0x1980, (q15_t)0x1967, (q15_t)0x194e, (q15_t)0x1936, (q15_t)0x191d, (q15_t)0x1905, + (q15_t)0x18ec, (q15_t)0x18d3, (q15_t)0x18bb, (q15_t)0x18a2, (q15_t)0x1889, (q15_t)0x1871, (q15_t)0x1858, (q15_t)0x183f, + (q15_t)0x1827, (q15_t)0x180e, (q15_t)0x17f5, (q15_t)0x17dd, (q15_t)0x17c4, (q15_t)0x17ab, (q15_t)0x1792, (q15_t)0x177a, + (q15_t)0x1761, (q15_t)0x1748, (q15_t)0x1730, (q15_t)0x1717, (q15_t)0x16fe, (q15_t)0x16e5, (q15_t)0x16cd, (q15_t)0x16b4, + (q15_t)0x169b, (q15_t)0x1682, (q15_t)0x166a, (q15_t)0x1651, (q15_t)0x1638, (q15_t)0x161f, (q15_t)0x1607, (q15_t)0x15ee, + (q15_t)0x15d5, (q15_t)0x15bc, (q15_t)0x15a4, (q15_t)0x158b, (q15_t)0x1572, (q15_t)0x1559, (q15_t)0x1541, (q15_t)0x1528, + (q15_t)0x150f, (q15_t)0x14f6, (q15_t)0x14dd, (q15_t)0x14c5, (q15_t)0x14ac, (q15_t)0x1493, (q15_t)0x147a, (q15_t)0x1461, + (q15_t)0x1449, (q15_t)0x1430, (q15_t)0x1417, (q15_t)0x13fe, (q15_t)0x13e5, (q15_t)0x13cc, (q15_t)0x13b4, (q15_t)0x139b, + (q15_t)0x1382, (q15_t)0x1369, (q15_t)0x1350, (q15_t)0x1337, (q15_t)0x131f, (q15_t)0x1306, (q15_t)0x12ed, (q15_t)0x12d4, + (q15_t)0x12bb, (q15_t)0x12a2, (q15_t)0x1289, (q15_t)0x1271, (q15_t)0x1258, (q15_t)0x123f, (q15_t)0x1226, (q15_t)0x120d, + (q15_t)0x11f4, (q15_t)0x11db, (q15_t)0x11c2, (q15_t)0x11a9, (q15_t)0x1191, (q15_t)0x1178, (q15_t)0x115f, (q15_t)0x1146, + (q15_t)0x112d, (q15_t)0x1114, (q15_t)0x10fb, (q15_t)0x10e2, (q15_t)0x10c9, (q15_t)0x10b0, (q15_t)0x1098, (q15_t)0x107f, + (q15_t)0x1066, (q15_t)0x104d, (q15_t)0x1034, (q15_t)0x101b, (q15_t)0x1002, (q15_t)0xfe9, (q15_t)0xfd0, (q15_t)0xfb7, + (q15_t)0xf9e, (q15_t)0xf85, (q15_t)0xf6c, (q15_t)0xf53, (q15_t)0xf3a, (q15_t)0xf21, (q15_t)0xf08, (q15_t)0xef0, + (q15_t)0xed7, (q15_t)0xebe, (q15_t)0xea5, (q15_t)0xe8c, (q15_t)0xe73, (q15_t)0xe5a, (q15_t)0xe41, (q15_t)0xe28, + (q15_t)0xe0f, (q15_t)0xdf6, (q15_t)0xddd, (q15_t)0xdc4, (q15_t)0xdab, (q15_t)0xd92, (q15_t)0xd79, (q15_t)0xd60, + (q15_t)0xd47, (q15_t)0xd2e, (q15_t)0xd15, (q15_t)0xcfc, (q15_t)0xce3, (q15_t)0xcca, (q15_t)0xcb1, (q15_t)0xc98, + (q15_t)0xc7f, (q15_t)0xc66, (q15_t)0xc4d, (q15_t)0xc34, (q15_t)0xc1b, (q15_t)0xc02, (q15_t)0xbe9, (q15_t)0xbd0, + (q15_t)0xbb7, (q15_t)0xb9e, (q15_t)0xb85, (q15_t)0xb6c, (q15_t)0xb53, (q15_t)0xb3a, (q15_t)0xb20, (q15_t)0xb07, + (q15_t)0xaee, (q15_t)0xad5, (q15_t)0xabc, (q15_t)0xaa3, (q15_t)0xa8a, (q15_t)0xa71, (q15_t)0xa58, (q15_t)0xa3f, + (q15_t)0xa26, (q15_t)0xa0d, (q15_t)0x9f4, (q15_t)0x9db, (q15_t)0x9c2, (q15_t)0x9a9, (q15_t)0x990, (q15_t)0x977, + (q15_t)0x95e, (q15_t)0x944, (q15_t)0x92b, (q15_t)0x912, (q15_t)0x8f9, (q15_t)0x8e0, (q15_t)0x8c7, (q15_t)0x8ae, + (q15_t)0x895, (q15_t)0x87c, (q15_t)0x863, (q15_t)0x84a, (q15_t)0x831, (q15_t)0x818, (q15_t)0x7fe, (q15_t)0x7e5, + (q15_t)0x7cc, (q15_t)0x7b3, (q15_t)0x79a, (q15_t)0x781, (q15_t)0x768, (q15_t)0x74f, (q15_t)0x736, (q15_t)0x71d, + (q15_t)0x704, (q15_t)0x6ea, (q15_t)0x6d1, (q15_t)0x6b8, (q15_t)0x69f, (q15_t)0x686, (q15_t)0x66d, (q15_t)0x654, + (q15_t)0x63b, (q15_t)0x622, (q15_t)0x609, (q15_t)0x5ef, (q15_t)0x5d6, (q15_t)0x5bd, (q15_t)0x5a4, (q15_t)0x58b, + (q15_t)0x572, (q15_t)0x559, (q15_t)0x540, (q15_t)0x527, (q15_t)0x50d, (q15_t)0x4f4, (q15_t)0x4db, (q15_t)0x4c2, + (q15_t)0x4a9, (q15_t)0x490, (q15_t)0x477, (q15_t)0x45e, (q15_t)0x445, (q15_t)0x42b, (q15_t)0x412, (q15_t)0x3f9, + (q15_t)0x3e0, (q15_t)0x3c7, (q15_t)0x3ae, (q15_t)0x395, (q15_t)0x37c, (q15_t)0x362, (q15_t)0x349, (q15_t)0x330, + (q15_t)0x317, (q15_t)0x2fe, (q15_t)0x2e5, (q15_t)0x2cc, (q15_t)0x2b3, (q15_t)0x299, (q15_t)0x280, (q15_t)0x267, + (q15_t)0x24e, (q15_t)0x235, (q15_t)0x21c, (q15_t)0x203, (q15_t)0x1ea, (q15_t)0x1d0, (q15_t)0x1b7, (q15_t)0x19e, + (q15_t)0x185, (q15_t)0x16c, (q15_t)0x153, (q15_t)0x13a, (q15_t)0x121, (q15_t)0x107, (q15_t)0xee, (q15_t)0xd5, + (q15_t)0xbc, (q15_t)0xa3, (q15_t)0x8a, (q15_t)0x71, (q15_t)0x57, (q15_t)0x3e, (q15_t)0x25, (q15_t)0xc + +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192) + const q15_t __ALIGNED(4) WeightsQ15_8192[16384] = { + (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xfffa, (q15_t)0x7fff, (q15_t)0xfff4, (q15_t)0x7fff, (q15_t)0xffee, + (q15_t)0x7fff, (q15_t)0xffe7, (q15_t)0x7fff, (q15_t)0xffe1, (q15_t)0x7fff, (q15_t)0xffdb, (q15_t)0x7fff, (q15_t)0xffd5, + (q15_t)0x7fff, (q15_t)0xffce, (q15_t)0x7fff, (q15_t)0xffc8, (q15_t)0x7fff, (q15_t)0xffc2, (q15_t)0x7fff, (q15_t)0xffbb, + (q15_t)0x7fff, (q15_t)0xffb5, (q15_t)0x7fff, (q15_t)0xffaf, (q15_t)0x7fff, (q15_t)0xffa9, (q15_t)0x7fff, (q15_t)0xffa2, + (q15_t)0x7fff, (q15_t)0xff9c, (q15_t)0x7fff, (q15_t)0xff96, (q15_t)0x7fff, (q15_t)0xff8f, (q15_t)0x7fff, (q15_t)0xff89, + (q15_t)0x7fff, (q15_t)0xff83, (q15_t)0x7fff, (q15_t)0xff7d, (q15_t)0x7fff, (q15_t)0xff76, (q15_t)0x7fff, (q15_t)0xff70, + (q15_t)0x7fff, (q15_t)0xff6a, (q15_t)0x7fff, (q15_t)0xff63, (q15_t)0x7fff, (q15_t)0xff5d, (q15_t)0x7fff, (q15_t)0xff57, + (q15_t)0x7fff, (q15_t)0xff51, (q15_t)0x7fff, (q15_t)0xff4a, (q15_t)0x7fff, (q15_t)0xff44, (q15_t)0x7fff, (q15_t)0xff3e, + (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7fff, (q15_t)0xff31, (q15_t)0x7fff, (q15_t)0xff2b, (q15_t)0x7fff, (q15_t)0xff25, + (q15_t)0x7fff, (q15_t)0xff1e, (q15_t)0x7fff, (q15_t)0xff18, (q15_t)0x7fff, (q15_t)0xff12, (q15_t)0x7fff, (q15_t)0xff0b, + (q15_t)0x7fff, (q15_t)0xff05, (q15_t)0x7ffe, (q15_t)0xfeff, (q15_t)0x7ffe, (q15_t)0xfef9, (q15_t)0x7ffe, (q15_t)0xfef2, + (q15_t)0x7ffe, (q15_t)0xfeec, (q15_t)0x7ffe, (q15_t)0xfee6, (q15_t)0x7ffe, (q15_t)0xfedf, (q15_t)0x7ffe, (q15_t)0xfed9, + (q15_t)0x7ffe, (q15_t)0xfed3, (q15_t)0x7ffe, (q15_t)0xfecd, (q15_t)0x7ffe, (q15_t)0xfec6, (q15_t)0x7ffe, (q15_t)0xfec0, + (q15_t)0x7ffe, (q15_t)0xfeba, (q15_t)0x7ffe, (q15_t)0xfeb3, (q15_t)0x7ffe, (q15_t)0xfead, (q15_t)0x7ffe, (q15_t)0xfea7, + (q15_t)0x7ffe, (q15_t)0xfea1, (q15_t)0x7ffe, (q15_t)0xfe9a, (q15_t)0x7ffd, (q15_t)0xfe94, (q15_t)0x7ffd, (q15_t)0xfe8e, + (q15_t)0x7ffd, (q15_t)0xfe88, (q15_t)0x7ffd, (q15_t)0xfe81, (q15_t)0x7ffd, (q15_t)0xfe7b, (q15_t)0x7ffd, (q15_t)0xfe75, + (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ffd, (q15_t)0xfe68, (q15_t)0x7ffd, (q15_t)0xfe62, (q15_t)0x7ffd, (q15_t)0xfe5c, + (q15_t)0x7ffd, (q15_t)0xfe55, (q15_t)0x7ffd, (q15_t)0xfe4f, (q15_t)0x7ffd, (q15_t)0xfe49, (q15_t)0x7ffc, (q15_t)0xfe42, + (q15_t)0x7ffc, (q15_t)0xfe3c, (q15_t)0x7ffc, (q15_t)0xfe36, (q15_t)0x7ffc, (q15_t)0xfe30, (q15_t)0x7ffc, (q15_t)0xfe29, + (q15_t)0x7ffc, (q15_t)0xfe23, (q15_t)0x7ffc, (q15_t)0xfe1d, (q15_t)0x7ffc, (q15_t)0xfe16, (q15_t)0x7ffc, (q15_t)0xfe10, + (q15_t)0x7ffc, (q15_t)0xfe0a, (q15_t)0x7ffc, (q15_t)0xfe04, (q15_t)0x7ffb, (q15_t)0xfdfd, (q15_t)0x7ffb, (q15_t)0xfdf7, + (q15_t)0x7ffb, (q15_t)0xfdf1, (q15_t)0x7ffb, (q15_t)0xfdea, (q15_t)0x7ffb, (q15_t)0xfde4, (q15_t)0x7ffb, (q15_t)0xfdde, + (q15_t)0x7ffb, (q15_t)0xfdd8, (q15_t)0x7ffb, (q15_t)0xfdd1, (q15_t)0x7ffb, (q15_t)0xfdcb, (q15_t)0x7ffb, (q15_t)0xfdc5, + (q15_t)0x7ffa, (q15_t)0xfdbe, (q15_t)0x7ffa, (q15_t)0xfdb8, (q15_t)0x7ffa, (q15_t)0xfdb2, (q15_t)0x7ffa, (q15_t)0xfdac, + (q15_t)0x7ffa, (q15_t)0xfda5, (q15_t)0x7ffa, (q15_t)0xfd9f, (q15_t)0x7ffa, (q15_t)0xfd99, (q15_t)0x7ffa, (q15_t)0xfd93, + (q15_t)0x7ff9, (q15_t)0xfd8c, (q15_t)0x7ff9, (q15_t)0xfd86, (q15_t)0x7ff9, (q15_t)0xfd80, (q15_t)0x7ff9, (q15_t)0xfd79, + (q15_t)0x7ff9, (q15_t)0xfd73, (q15_t)0x7ff9, (q15_t)0xfd6d, (q15_t)0x7ff9, (q15_t)0xfd67, (q15_t)0x7ff9, (q15_t)0xfd60, + (q15_t)0x7ff8, (q15_t)0xfd5a, (q15_t)0x7ff8, (q15_t)0xfd54, (q15_t)0x7ff8, (q15_t)0xfd4d, (q15_t)0x7ff8, (q15_t)0xfd47, + (q15_t)0x7ff8, (q15_t)0xfd41, (q15_t)0x7ff8, (q15_t)0xfd3b, (q15_t)0x7ff8, (q15_t)0xfd34, (q15_t)0x7ff8, (q15_t)0xfd2e, + (q15_t)0x7ff7, (q15_t)0xfd28, (q15_t)0x7ff7, (q15_t)0xfd21, (q15_t)0x7ff7, (q15_t)0xfd1b, (q15_t)0x7ff7, (q15_t)0xfd15, + (q15_t)0x7ff7, (q15_t)0xfd0f, (q15_t)0x7ff7, (q15_t)0xfd08, (q15_t)0x7ff7, (q15_t)0xfd02, (q15_t)0x7ff6, (q15_t)0xfcfc, + (q15_t)0x7ff6, (q15_t)0xfcf5, (q15_t)0x7ff6, (q15_t)0xfcef, (q15_t)0x7ff6, (q15_t)0xfce9, (q15_t)0x7ff6, (q15_t)0xfce3, + (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7ff5, (q15_t)0xfcd6, (q15_t)0x7ff5, (q15_t)0xfcd0, (q15_t)0x7ff5, (q15_t)0xfcc9, + (q15_t)0x7ff5, (q15_t)0xfcc3, (q15_t)0x7ff5, (q15_t)0xfcbd, (q15_t)0x7ff5, (q15_t)0xfcb7, (q15_t)0x7ff5, (q15_t)0xfcb0, + (q15_t)0x7ff4, (q15_t)0xfcaa, (q15_t)0x7ff4, (q15_t)0xfca4, (q15_t)0x7ff4, (q15_t)0xfc9e, (q15_t)0x7ff4, (q15_t)0xfc97, + (q15_t)0x7ff4, (q15_t)0xfc91, (q15_t)0x7ff4, (q15_t)0xfc8b, (q15_t)0x7ff3, (q15_t)0xfc84, (q15_t)0x7ff3, (q15_t)0xfc7e, + (q15_t)0x7ff3, (q15_t)0xfc78, (q15_t)0x7ff3, (q15_t)0xfc72, (q15_t)0x7ff3, (q15_t)0xfc6b, (q15_t)0x7ff2, (q15_t)0xfc65, + (q15_t)0x7ff2, (q15_t)0xfc5f, (q15_t)0x7ff2, (q15_t)0xfc58, (q15_t)0x7ff2, (q15_t)0xfc52, (q15_t)0x7ff2, (q15_t)0xfc4c, + (q15_t)0x7ff2, (q15_t)0xfc46, (q15_t)0x7ff1, (q15_t)0xfc3f, (q15_t)0x7ff1, (q15_t)0xfc39, (q15_t)0x7ff1, (q15_t)0xfc33, + (q15_t)0x7ff1, (q15_t)0xfc2c, (q15_t)0x7ff1, (q15_t)0xfc26, (q15_t)0x7ff0, (q15_t)0xfc20, (q15_t)0x7ff0, (q15_t)0xfc1a, + (q15_t)0x7ff0, (q15_t)0xfc13, (q15_t)0x7ff0, (q15_t)0xfc0d, (q15_t)0x7ff0, (q15_t)0xfc07, (q15_t)0x7fef, (q15_t)0xfc01, + (q15_t)0x7fef, (q15_t)0xfbfa, (q15_t)0x7fef, (q15_t)0xfbf4, (q15_t)0x7fef, (q15_t)0xfbee, (q15_t)0x7fef, (q15_t)0xfbe7, + (q15_t)0x7fee, (q15_t)0xfbe1, (q15_t)0x7fee, (q15_t)0xfbdb, (q15_t)0x7fee, (q15_t)0xfbd5, (q15_t)0x7fee, (q15_t)0xfbce, + (q15_t)0x7fee, (q15_t)0xfbc8, (q15_t)0x7fed, (q15_t)0xfbc2, (q15_t)0x7fed, (q15_t)0xfbbb, (q15_t)0x7fed, (q15_t)0xfbb5, + (q15_t)0x7fed, (q15_t)0xfbaf, (q15_t)0x7fed, (q15_t)0xfba9, (q15_t)0x7fec, (q15_t)0xfba2, (q15_t)0x7fec, (q15_t)0xfb9c, + (q15_t)0x7fec, (q15_t)0xfb96, (q15_t)0x7fec, (q15_t)0xfb8f, (q15_t)0x7fec, (q15_t)0xfb89, (q15_t)0x7feb, (q15_t)0xfb83, + (q15_t)0x7feb, (q15_t)0xfb7d, (q15_t)0x7feb, (q15_t)0xfb76, (q15_t)0x7feb, (q15_t)0xfb70, (q15_t)0x7fea, (q15_t)0xfb6a, + (q15_t)0x7fea, (q15_t)0xfb64, (q15_t)0x7fea, (q15_t)0xfb5d, (q15_t)0x7fea, (q15_t)0xfb57, (q15_t)0x7fea, (q15_t)0xfb51, + (q15_t)0x7fe9, (q15_t)0xfb4a, (q15_t)0x7fe9, (q15_t)0xfb44, (q15_t)0x7fe9, (q15_t)0xfb3e, (q15_t)0x7fe9, (q15_t)0xfb38, + (q15_t)0x7fe8, (q15_t)0xfb31, (q15_t)0x7fe8, (q15_t)0xfb2b, (q15_t)0x7fe8, (q15_t)0xfb25, (q15_t)0x7fe8, (q15_t)0xfb1e, + (q15_t)0x7fe7, (q15_t)0xfb18, (q15_t)0x7fe7, (q15_t)0xfb12, (q15_t)0x7fe7, (q15_t)0xfb0c, (q15_t)0x7fe7, (q15_t)0xfb05, + (q15_t)0x7fe6, (q15_t)0xfaff, (q15_t)0x7fe6, (q15_t)0xfaf9, (q15_t)0x7fe6, (q15_t)0xfaf3, (q15_t)0x7fe6, (q15_t)0xfaec, + (q15_t)0x7fe5, (q15_t)0xfae6, (q15_t)0x7fe5, (q15_t)0xfae0, (q15_t)0x7fe5, (q15_t)0xfad9, (q15_t)0x7fe5, (q15_t)0xfad3, + (q15_t)0x7fe4, (q15_t)0xfacd, (q15_t)0x7fe4, (q15_t)0xfac7, (q15_t)0x7fe4, (q15_t)0xfac0, (q15_t)0x7fe4, (q15_t)0xfaba, + (q15_t)0x7fe3, (q15_t)0xfab4, (q15_t)0x7fe3, (q15_t)0xfaad, (q15_t)0x7fe3, (q15_t)0xfaa7, (q15_t)0x7fe3, (q15_t)0xfaa1, + (q15_t)0x7fe2, (q15_t)0xfa9b, (q15_t)0x7fe2, (q15_t)0xfa94, (q15_t)0x7fe2, (q15_t)0xfa8e, (q15_t)0x7fe2, (q15_t)0xfa88, + (q15_t)0x7fe1, (q15_t)0xfa81, (q15_t)0x7fe1, (q15_t)0xfa7b, (q15_t)0x7fe1, (q15_t)0xfa75, (q15_t)0x7fe0, (q15_t)0xfa6f, + (q15_t)0x7fe0, (q15_t)0xfa68, (q15_t)0x7fe0, (q15_t)0xfa62, (q15_t)0x7fe0, (q15_t)0xfa5c, (q15_t)0x7fdf, (q15_t)0xfa56, + (q15_t)0x7fdf, (q15_t)0xfa4f, (q15_t)0x7fdf, (q15_t)0xfa49, (q15_t)0x7fdf, (q15_t)0xfa43, (q15_t)0x7fde, (q15_t)0xfa3c, + (q15_t)0x7fde, (q15_t)0xfa36, (q15_t)0x7fde, (q15_t)0xfa30, (q15_t)0x7fdd, (q15_t)0xfa2a, (q15_t)0x7fdd, (q15_t)0xfa23, + (q15_t)0x7fdd, (q15_t)0xfa1d, (q15_t)0x7fdd, (q15_t)0xfa17, (q15_t)0x7fdc, (q15_t)0xfa11, (q15_t)0x7fdc, (q15_t)0xfa0a, + (q15_t)0x7fdc, (q15_t)0xfa04, (q15_t)0x7fdb, (q15_t)0xf9fe, (q15_t)0x7fdb, (q15_t)0xf9f7, (q15_t)0x7fdb, (q15_t)0xf9f1, + (q15_t)0x7fda, (q15_t)0xf9eb, (q15_t)0x7fda, (q15_t)0xf9e5, (q15_t)0x7fda, (q15_t)0xf9de, (q15_t)0x7fda, (q15_t)0xf9d8, + (q15_t)0x7fd9, (q15_t)0xf9d2, (q15_t)0x7fd9, (q15_t)0xf9cb, (q15_t)0x7fd9, (q15_t)0xf9c5, (q15_t)0x7fd8, (q15_t)0xf9bf, + (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fd8, (q15_t)0xf9b2, (q15_t)0x7fd7, (q15_t)0xf9ac, (q15_t)0x7fd7, (q15_t)0xf9a6, + (q15_t)0x7fd7, (q15_t)0xf9a0, (q15_t)0x7fd6, (q15_t)0xf999, (q15_t)0x7fd6, (q15_t)0xf993, (q15_t)0x7fd6, (q15_t)0xf98d, + (q15_t)0x7fd6, (q15_t)0xf986, (q15_t)0x7fd5, (q15_t)0xf980, (q15_t)0x7fd5, (q15_t)0xf97a, (q15_t)0x7fd5, (q15_t)0xf974, + (q15_t)0x7fd4, (q15_t)0xf96d, (q15_t)0x7fd4, (q15_t)0xf967, (q15_t)0x7fd4, (q15_t)0xf961, (q15_t)0x7fd3, (q15_t)0xf95b, + (q15_t)0x7fd3, (q15_t)0xf954, (q15_t)0x7fd3, (q15_t)0xf94e, (q15_t)0x7fd2, (q15_t)0xf948, (q15_t)0x7fd2, (q15_t)0xf941, + (q15_t)0x7fd2, (q15_t)0xf93b, (q15_t)0x7fd1, (q15_t)0xf935, (q15_t)0x7fd1, (q15_t)0xf92f, (q15_t)0x7fd1, (q15_t)0xf928, + (q15_t)0x7fd0, (q15_t)0xf922, (q15_t)0x7fd0, (q15_t)0xf91c, (q15_t)0x7fd0, (q15_t)0xf916, (q15_t)0x7fcf, (q15_t)0xf90f, + (q15_t)0x7fcf, (q15_t)0xf909, (q15_t)0x7fcf, (q15_t)0xf903, (q15_t)0x7fce, (q15_t)0xf8fc, (q15_t)0x7fce, (q15_t)0xf8f6, + (q15_t)0x7fce, (q15_t)0xf8f0, (q15_t)0x7fcd, (q15_t)0xf8ea, (q15_t)0x7fcd, (q15_t)0xf8e3, (q15_t)0x7fcd, (q15_t)0xf8dd, + (q15_t)0x7fcc, (q15_t)0xf8d7, (q15_t)0x7fcc, (q15_t)0xf8d0, (q15_t)0x7fcb, (q15_t)0xf8ca, (q15_t)0x7fcb, (q15_t)0xf8c4, + (q15_t)0x7fcb, (q15_t)0xf8be, (q15_t)0x7fca, (q15_t)0xf8b7, (q15_t)0x7fca, (q15_t)0xf8b1, (q15_t)0x7fca, (q15_t)0xf8ab, + (q15_t)0x7fc9, (q15_t)0xf8a5, (q15_t)0x7fc9, (q15_t)0xf89e, (q15_t)0x7fc9, (q15_t)0xf898, (q15_t)0x7fc8, (q15_t)0xf892, + (q15_t)0x7fc8, (q15_t)0xf88b, (q15_t)0x7fc7, (q15_t)0xf885, (q15_t)0x7fc7, (q15_t)0xf87f, (q15_t)0x7fc7, (q15_t)0xf879, + (q15_t)0x7fc6, (q15_t)0xf872, (q15_t)0x7fc6, (q15_t)0xf86c, (q15_t)0x7fc6, (q15_t)0xf866, (q15_t)0x7fc5, (q15_t)0xf860, + (q15_t)0x7fc5, (q15_t)0xf859, (q15_t)0x7fc5, (q15_t)0xf853, (q15_t)0x7fc4, (q15_t)0xf84d, (q15_t)0x7fc4, (q15_t)0xf846, + (q15_t)0x7fc3, (q15_t)0xf840, (q15_t)0x7fc3, (q15_t)0xf83a, (q15_t)0x7fc3, (q15_t)0xf834, (q15_t)0x7fc2, (q15_t)0xf82d, + (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fc1, (q15_t)0xf821, (q15_t)0x7fc1, (q15_t)0xf81b, (q15_t)0x7fc1, (q15_t)0xf814, + (q15_t)0x7fc0, (q15_t)0xf80e, (q15_t)0x7fc0, (q15_t)0xf808, (q15_t)0x7fc0, (q15_t)0xf802, (q15_t)0x7fbf, (q15_t)0xf7fb, + (q15_t)0x7fbf, (q15_t)0xf7f5, (q15_t)0x7fbe, (q15_t)0xf7ef, (q15_t)0x7fbe, (q15_t)0xf7e8, (q15_t)0x7fbe, (q15_t)0xf7e2, + (q15_t)0x7fbd, (q15_t)0xf7dc, (q15_t)0x7fbd, (q15_t)0xf7d6, (q15_t)0x7fbc, (q15_t)0xf7cf, (q15_t)0x7fbc, (q15_t)0xf7c9, + (q15_t)0x7fbc, (q15_t)0xf7c3, (q15_t)0x7fbb, (q15_t)0xf7bd, (q15_t)0x7fbb, (q15_t)0xf7b6, (q15_t)0x7fba, (q15_t)0xf7b0, + (q15_t)0x7fba, (q15_t)0xf7aa, (q15_t)0x7fb9, (q15_t)0xf7a3, (q15_t)0x7fb9, (q15_t)0xf79d, (q15_t)0x7fb9, (q15_t)0xf797, + (q15_t)0x7fb8, (q15_t)0xf791, (q15_t)0x7fb8, (q15_t)0xf78a, (q15_t)0x7fb7, (q15_t)0xf784, (q15_t)0x7fb7, (q15_t)0xf77e, + (q15_t)0x7fb7, (q15_t)0xf778, (q15_t)0x7fb6, (q15_t)0xf771, (q15_t)0x7fb6, (q15_t)0xf76b, (q15_t)0x7fb5, (q15_t)0xf765, + (q15_t)0x7fb5, (q15_t)0xf75e, (q15_t)0x7fb4, (q15_t)0xf758, (q15_t)0x7fb4, (q15_t)0xf752, (q15_t)0x7fb4, (q15_t)0xf74c, + (q15_t)0x7fb3, (q15_t)0xf745, (q15_t)0x7fb3, (q15_t)0xf73f, (q15_t)0x7fb2, (q15_t)0xf739, (q15_t)0x7fb2, (q15_t)0xf733, + (q15_t)0x7fb1, (q15_t)0xf72c, (q15_t)0x7fb1, (q15_t)0xf726, (q15_t)0x7fb1, (q15_t)0xf720, (q15_t)0x7fb0, (q15_t)0xf71a, + (q15_t)0x7fb0, (q15_t)0xf713, (q15_t)0x7faf, (q15_t)0xf70d, (q15_t)0x7faf, (q15_t)0xf707, (q15_t)0x7fae, (q15_t)0xf700, + (q15_t)0x7fae, (q15_t)0xf6fa, (q15_t)0x7fae, (q15_t)0xf6f4, (q15_t)0x7fad, (q15_t)0xf6ee, (q15_t)0x7fad, (q15_t)0xf6e7, + (q15_t)0x7fac, (q15_t)0xf6e1, (q15_t)0x7fac, (q15_t)0xf6db, (q15_t)0x7fab, (q15_t)0xf6d5, (q15_t)0x7fab, (q15_t)0xf6ce, + (q15_t)0x7faa, (q15_t)0xf6c8, (q15_t)0x7faa, (q15_t)0xf6c2, (q15_t)0x7fa9, (q15_t)0xf6bc, (q15_t)0x7fa9, (q15_t)0xf6b5, + (q15_t)0x7fa9, (q15_t)0xf6af, (q15_t)0x7fa8, (q15_t)0xf6a9, (q15_t)0x7fa8, (q15_t)0xf6a2, (q15_t)0x7fa7, (q15_t)0xf69c, + (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7fa6, (q15_t)0xf690, (q15_t)0x7fa6, (q15_t)0xf689, (q15_t)0x7fa5, (q15_t)0xf683, + (q15_t)0x7fa5, (q15_t)0xf67d, (q15_t)0x7fa4, (q15_t)0xf677, (q15_t)0x7fa4, (q15_t)0xf670, (q15_t)0x7fa3, (q15_t)0xf66a, + (q15_t)0x7fa3, (q15_t)0xf664, (q15_t)0x7fa3, (q15_t)0xf65e, (q15_t)0x7fa2, (q15_t)0xf657, (q15_t)0x7fa2, (q15_t)0xf651, + (q15_t)0x7fa1, (q15_t)0xf64b, (q15_t)0x7fa1, (q15_t)0xf644, (q15_t)0x7fa0, (q15_t)0xf63e, (q15_t)0x7fa0, (q15_t)0xf638, + (q15_t)0x7f9f, (q15_t)0xf632, (q15_t)0x7f9f, (q15_t)0xf62b, (q15_t)0x7f9e, (q15_t)0xf625, (q15_t)0x7f9e, (q15_t)0xf61f, + (q15_t)0x7f9d, (q15_t)0xf619, (q15_t)0x7f9d, (q15_t)0xf612, (q15_t)0x7f9c, (q15_t)0xf60c, (q15_t)0x7f9c, (q15_t)0xf606, + (q15_t)0x7f9b, (q15_t)0xf600, (q15_t)0x7f9b, (q15_t)0xf5f9, (q15_t)0x7f9a, (q15_t)0xf5f3, (q15_t)0x7f9a, (q15_t)0xf5ed, + (q15_t)0x7f99, (q15_t)0xf5e7, (q15_t)0x7f99, (q15_t)0xf5e0, (q15_t)0x7f98, (q15_t)0xf5da, (q15_t)0x7f98, (q15_t)0xf5d4, + (q15_t)0x7f97, (q15_t)0xf5cd, (q15_t)0x7f97, (q15_t)0xf5c7, (q15_t)0x7f96, (q15_t)0xf5c1, (q15_t)0x7f96, (q15_t)0xf5bb, + (q15_t)0x7f95, (q15_t)0xf5b4, (q15_t)0x7f95, (q15_t)0xf5ae, (q15_t)0x7f94, (q15_t)0xf5a8, (q15_t)0x7f94, (q15_t)0xf5a2, + (q15_t)0x7f93, (q15_t)0xf59b, (q15_t)0x7f93, (q15_t)0xf595, (q15_t)0x7f92, (q15_t)0xf58f, (q15_t)0x7f92, (q15_t)0xf589, + (q15_t)0x7f91, (q15_t)0xf582, (q15_t)0x7f91, (q15_t)0xf57c, (q15_t)0x7f90, (q15_t)0xf576, (q15_t)0x7f90, (q15_t)0xf570, + (q15_t)0x7f8f, (q15_t)0xf569, (q15_t)0x7f8f, (q15_t)0xf563, (q15_t)0x7f8e, (q15_t)0xf55d, (q15_t)0x7f8e, (q15_t)0xf556, + (q15_t)0x7f8d, (q15_t)0xf550, (q15_t)0x7f8d, (q15_t)0xf54a, (q15_t)0x7f8c, (q15_t)0xf544, (q15_t)0x7f8b, (q15_t)0xf53d, + (q15_t)0x7f8b, (q15_t)0xf537, (q15_t)0x7f8a, (q15_t)0xf531, (q15_t)0x7f8a, (q15_t)0xf52b, (q15_t)0x7f89, (q15_t)0xf524, + (q15_t)0x7f89, (q15_t)0xf51e, (q15_t)0x7f88, (q15_t)0xf518, (q15_t)0x7f88, (q15_t)0xf512, (q15_t)0x7f87, (q15_t)0xf50b, + (q15_t)0x7f87, (q15_t)0xf505, (q15_t)0x7f86, (q15_t)0xf4ff, (q15_t)0x7f86, (q15_t)0xf4f9, (q15_t)0x7f85, (q15_t)0xf4f2, + (q15_t)0x7f85, (q15_t)0xf4ec, (q15_t)0x7f84, (q15_t)0xf4e6, (q15_t)0x7f83, (q15_t)0xf4e0, (q15_t)0x7f83, (q15_t)0xf4d9, + (q15_t)0x7f82, (q15_t)0xf4d3, (q15_t)0x7f82, (q15_t)0xf4cd, (q15_t)0x7f81, (q15_t)0xf4c6, (q15_t)0x7f81, (q15_t)0xf4c0, + (q15_t)0x7f80, (q15_t)0xf4ba, (q15_t)0x7f80, (q15_t)0xf4b4, (q15_t)0x7f7f, (q15_t)0xf4ad, (q15_t)0x7f7e, (q15_t)0xf4a7, + (q15_t)0x7f7e, (q15_t)0xf4a1, (q15_t)0x7f7d, (q15_t)0xf49b, (q15_t)0x7f7d, (q15_t)0xf494, (q15_t)0x7f7c, (q15_t)0xf48e, + (q15_t)0x7f7c, (q15_t)0xf488, (q15_t)0x7f7b, (q15_t)0xf482, (q15_t)0x7f7b, (q15_t)0xf47b, (q15_t)0x7f7a, (q15_t)0xf475, + (q15_t)0x7f79, (q15_t)0xf46f, (q15_t)0x7f79, (q15_t)0xf469, (q15_t)0x7f78, (q15_t)0xf462, (q15_t)0x7f78, (q15_t)0xf45c, + (q15_t)0x7f77, (q15_t)0xf456, (q15_t)0x7f77, (q15_t)0xf450, (q15_t)0x7f76, (q15_t)0xf449, (q15_t)0x7f75, (q15_t)0xf443, + (q15_t)0x7f75, (q15_t)0xf43d, (q15_t)0x7f74, (q15_t)0xf437, (q15_t)0x7f74, (q15_t)0xf430, (q15_t)0x7f73, (q15_t)0xf42a, + (q15_t)0x7f72, (q15_t)0xf424, (q15_t)0x7f72, (q15_t)0xf41e, (q15_t)0x7f71, (q15_t)0xf417, (q15_t)0x7f71, (q15_t)0xf411, + (q15_t)0x7f70, (q15_t)0xf40b, (q15_t)0x7f70, (q15_t)0xf405, (q15_t)0x7f6f, (q15_t)0xf3fe, (q15_t)0x7f6e, (q15_t)0xf3f8, + (q15_t)0x7f6e, (q15_t)0xf3f2, (q15_t)0x7f6d, (q15_t)0xf3ec, (q15_t)0x7f6d, (q15_t)0xf3e5, (q15_t)0x7f6c, (q15_t)0xf3df, + (q15_t)0x7f6b, (q15_t)0xf3d9, (q15_t)0x7f6b, (q15_t)0xf3d2, (q15_t)0x7f6a, (q15_t)0xf3cc, (q15_t)0x7f6a, (q15_t)0xf3c6, + (q15_t)0x7f69, (q15_t)0xf3c0, (q15_t)0x7f68, (q15_t)0xf3b9, (q15_t)0x7f68, (q15_t)0xf3b3, (q15_t)0x7f67, (q15_t)0xf3ad, + (q15_t)0x7f67, (q15_t)0xf3a7, (q15_t)0x7f66, (q15_t)0xf3a0, (q15_t)0x7f65, (q15_t)0xf39a, (q15_t)0x7f65, (q15_t)0xf394, + (q15_t)0x7f64, (q15_t)0xf38e, (q15_t)0x7f64, (q15_t)0xf387, (q15_t)0x7f63, (q15_t)0xf381, (q15_t)0x7f62, (q15_t)0xf37b, + (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f61, (q15_t)0xf36e, (q15_t)0x7f60, (q15_t)0xf368, (q15_t)0x7f60, (q15_t)0xf362, + (q15_t)0x7f5f, (q15_t)0xf35c, (q15_t)0x7f5f, (q15_t)0xf355, (q15_t)0x7f5e, (q15_t)0xf34f, (q15_t)0x7f5d, (q15_t)0xf349, + (q15_t)0x7f5d, (q15_t)0xf343, (q15_t)0x7f5c, (q15_t)0xf33c, (q15_t)0x7f5b, (q15_t)0xf336, (q15_t)0x7f5b, (q15_t)0xf330, + (q15_t)0x7f5a, (q15_t)0xf32a, (q15_t)0x7f5a, (q15_t)0xf323, (q15_t)0x7f59, (q15_t)0xf31d, (q15_t)0x7f58, (q15_t)0xf317, + (q15_t)0x7f58, (q15_t)0xf311, (q15_t)0x7f57, (q15_t)0xf30a, (q15_t)0x7f56, (q15_t)0xf304, (q15_t)0x7f56, (q15_t)0xf2fe, + (q15_t)0x7f55, (q15_t)0xf2f8, (q15_t)0x7f55, (q15_t)0xf2f1, (q15_t)0x7f54, (q15_t)0xf2eb, (q15_t)0x7f53, (q15_t)0xf2e5, + (q15_t)0x7f53, (q15_t)0xf2df, (q15_t)0x7f52, (q15_t)0xf2d8, (q15_t)0x7f51, (q15_t)0xf2d2, (q15_t)0x7f51, (q15_t)0xf2cc, + (q15_t)0x7f50, (q15_t)0xf2c6, (q15_t)0x7f4f, (q15_t)0xf2bf, (q15_t)0x7f4f, (q15_t)0xf2b9, (q15_t)0x7f4e, (q15_t)0xf2b3, + (q15_t)0x7f4d, (q15_t)0xf2ad, (q15_t)0x7f4d, (q15_t)0xf2a6, (q15_t)0x7f4c, (q15_t)0xf2a0, (q15_t)0x7f4b, (q15_t)0xf29a, + (q15_t)0x7f4b, (q15_t)0xf294, (q15_t)0x7f4a, (q15_t)0xf28d, (q15_t)0x7f49, (q15_t)0xf287, (q15_t)0x7f49, (q15_t)0xf281, + (q15_t)0x7f48, (q15_t)0xf27b, (q15_t)0x7f47, (q15_t)0xf274, (q15_t)0x7f47, (q15_t)0xf26e, (q15_t)0x7f46, (q15_t)0xf268, + (q15_t)0x7f45, (q15_t)0xf262, (q15_t)0x7f45, (q15_t)0xf25b, (q15_t)0x7f44, (q15_t)0xf255, (q15_t)0x7f43, (q15_t)0xf24f, + (q15_t)0x7f43, (q15_t)0xf249, (q15_t)0x7f42, (q15_t)0xf242, (q15_t)0x7f41, (q15_t)0xf23c, (q15_t)0x7f41, (q15_t)0xf236, + (q15_t)0x7f40, (q15_t)0xf230, (q15_t)0x7f3f, (q15_t)0xf229, (q15_t)0x7f3f, (q15_t)0xf223, (q15_t)0x7f3e, (q15_t)0xf21d, + (q15_t)0x7f3d, (q15_t)0xf217, (q15_t)0x7f3d, (q15_t)0xf210, (q15_t)0x7f3c, (q15_t)0xf20a, (q15_t)0x7f3b, (q15_t)0xf204, + (q15_t)0x7f3b, (q15_t)0xf1fe, (q15_t)0x7f3a, (q15_t)0xf1f7, (q15_t)0x7f39, (q15_t)0xf1f1, (q15_t)0x7f39, (q15_t)0xf1eb, + (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f37, (q15_t)0xf1de, (q15_t)0x7f36, (q15_t)0xf1d8, (q15_t)0x7f36, (q15_t)0xf1d2, + (q15_t)0x7f35, (q15_t)0xf1cc, (q15_t)0x7f34, (q15_t)0xf1c6, (q15_t)0x7f34, (q15_t)0xf1bf, (q15_t)0x7f33, (q15_t)0xf1b9, + (q15_t)0x7f32, (q15_t)0xf1b3, (q15_t)0x7f32, (q15_t)0xf1ad, (q15_t)0x7f31, (q15_t)0xf1a6, (q15_t)0x7f30, (q15_t)0xf1a0, + (q15_t)0x7f2f, (q15_t)0xf19a, (q15_t)0x7f2f, (q15_t)0xf194, (q15_t)0x7f2e, (q15_t)0xf18d, (q15_t)0x7f2d, (q15_t)0xf187, + (q15_t)0x7f2d, (q15_t)0xf181, (q15_t)0x7f2c, (q15_t)0xf17b, (q15_t)0x7f2b, (q15_t)0xf174, (q15_t)0x7f2a, (q15_t)0xf16e, + (q15_t)0x7f2a, (q15_t)0xf168, (q15_t)0x7f29, (q15_t)0xf162, (q15_t)0x7f28, (q15_t)0xf15b, (q15_t)0x7f28, (q15_t)0xf155, + (q15_t)0x7f27, (q15_t)0xf14f, (q15_t)0x7f26, (q15_t)0xf149, (q15_t)0x7f25, (q15_t)0xf142, (q15_t)0x7f25, (q15_t)0xf13c, + (q15_t)0x7f24, (q15_t)0xf136, (q15_t)0x7f23, (q15_t)0xf130, (q15_t)0x7f23, (q15_t)0xf129, (q15_t)0x7f22, (q15_t)0xf123, + (q15_t)0x7f21, (q15_t)0xf11d, (q15_t)0x7f20, (q15_t)0xf117, (q15_t)0x7f20, (q15_t)0xf110, (q15_t)0x7f1f, (q15_t)0xf10a, + (q15_t)0x7f1e, (q15_t)0xf104, (q15_t)0x7f1d, (q15_t)0xf0fe, (q15_t)0x7f1d, (q15_t)0xf0f8, (q15_t)0x7f1c, (q15_t)0xf0f1, + (q15_t)0x7f1b, (q15_t)0xf0eb, (q15_t)0x7f1a, (q15_t)0xf0e5, (q15_t)0x7f1a, (q15_t)0xf0df, (q15_t)0x7f19, (q15_t)0xf0d8, + (q15_t)0x7f18, (q15_t)0xf0d2, (q15_t)0x7f17, (q15_t)0xf0cc, (q15_t)0x7f17, (q15_t)0xf0c6, (q15_t)0x7f16, (q15_t)0xf0bf, + (q15_t)0x7f15, (q15_t)0xf0b9, (q15_t)0x7f14, (q15_t)0xf0b3, (q15_t)0x7f14, (q15_t)0xf0ad, (q15_t)0x7f13, (q15_t)0xf0a6, + (q15_t)0x7f12, (q15_t)0xf0a0, (q15_t)0x7f11, (q15_t)0xf09a, (q15_t)0x7f11, (q15_t)0xf094, (q15_t)0x7f10, (q15_t)0xf08d, + (q15_t)0x7f0f, (q15_t)0xf087, (q15_t)0x7f0e, (q15_t)0xf081, (q15_t)0x7f0e, (q15_t)0xf07b, (q15_t)0x7f0d, (q15_t)0xf075, + (q15_t)0x7f0c, (q15_t)0xf06e, (q15_t)0x7f0b, (q15_t)0xf068, (q15_t)0x7f0b, (q15_t)0xf062, (q15_t)0x7f0a, (q15_t)0xf05c, + (q15_t)0x7f09, (q15_t)0xf055, (q15_t)0x7f08, (q15_t)0xf04f, (q15_t)0x7f08, (q15_t)0xf049, (q15_t)0x7f07, (q15_t)0xf043, + (q15_t)0x7f06, (q15_t)0xf03c, (q15_t)0x7f05, (q15_t)0xf036, (q15_t)0x7f04, (q15_t)0xf030, (q15_t)0x7f04, (q15_t)0xf02a, + (q15_t)0x7f03, (q15_t)0xf023, (q15_t)0x7f02, (q15_t)0xf01d, (q15_t)0x7f01, (q15_t)0xf017, (q15_t)0x7f01, (q15_t)0xf011, + (q15_t)0x7f00, (q15_t)0xf00b, (q15_t)0x7eff, (q15_t)0xf004, (q15_t)0x7efe, (q15_t)0xeffe, (q15_t)0x7efd, (q15_t)0xeff8, + (q15_t)0x7efd, (q15_t)0xeff2, (q15_t)0x7efc, (q15_t)0xefeb, (q15_t)0x7efb, (q15_t)0xefe5, (q15_t)0x7efa, (q15_t)0xefdf, + (q15_t)0x7ef9, (q15_t)0xefd9, (q15_t)0x7ef9, (q15_t)0xefd2, (q15_t)0x7ef8, (q15_t)0xefcc, (q15_t)0x7ef7, (q15_t)0xefc6, + (q15_t)0x7ef6, (q15_t)0xefc0, (q15_t)0x7ef5, (q15_t)0xefb9, (q15_t)0x7ef5, (q15_t)0xefb3, (q15_t)0x7ef4, (q15_t)0xefad, + (q15_t)0x7ef3, (q15_t)0xefa7, (q15_t)0x7ef2, (q15_t)0xefa1, (q15_t)0x7ef1, (q15_t)0xef9a, (q15_t)0x7ef1, (q15_t)0xef94, + (q15_t)0x7ef0, (q15_t)0xef8e, (q15_t)0x7eef, (q15_t)0xef88, (q15_t)0x7eee, (q15_t)0xef81, (q15_t)0x7eed, (q15_t)0xef7b, + (q15_t)0x7eed, (q15_t)0xef75, (q15_t)0x7eec, (q15_t)0xef6f, (q15_t)0x7eeb, (q15_t)0xef68, (q15_t)0x7eea, (q15_t)0xef62, + (q15_t)0x7ee9, (q15_t)0xef5c, (q15_t)0x7ee9, (q15_t)0xef56, (q15_t)0x7ee8, (q15_t)0xef50, (q15_t)0x7ee7, (q15_t)0xef49, + (q15_t)0x7ee6, (q15_t)0xef43, (q15_t)0x7ee5, (q15_t)0xef3d, (q15_t)0x7ee4, (q15_t)0xef37, (q15_t)0x7ee4, (q15_t)0xef30, + (q15_t)0x7ee3, (q15_t)0xef2a, (q15_t)0x7ee2, (q15_t)0xef24, (q15_t)0x7ee1, (q15_t)0xef1e, (q15_t)0x7ee0, (q15_t)0xef18, + (q15_t)0x7edf, (q15_t)0xef11, (q15_t)0x7edf, (q15_t)0xef0b, (q15_t)0x7ede, (q15_t)0xef05, (q15_t)0x7edd, (q15_t)0xeeff, + (q15_t)0x7edc, (q15_t)0xeef8, (q15_t)0x7edb, (q15_t)0xeef2, (q15_t)0x7eda, (q15_t)0xeeec, (q15_t)0x7eda, (q15_t)0xeee6, + (q15_t)0x7ed9, (q15_t)0xeedf, (q15_t)0x7ed8, (q15_t)0xeed9, (q15_t)0x7ed7, (q15_t)0xeed3, (q15_t)0x7ed6, (q15_t)0xeecd, + (q15_t)0x7ed5, (q15_t)0xeec7, (q15_t)0x7ed5, (q15_t)0xeec0, (q15_t)0x7ed4, (q15_t)0xeeba, (q15_t)0x7ed3, (q15_t)0xeeb4, + (q15_t)0x7ed2, (q15_t)0xeeae, (q15_t)0x7ed1, (q15_t)0xeea7, (q15_t)0x7ed0, (q15_t)0xeea1, (q15_t)0x7ecf, (q15_t)0xee9b, + (q15_t)0x7ecf, (q15_t)0xee95, (q15_t)0x7ece, (q15_t)0xee8f, (q15_t)0x7ecd, (q15_t)0xee88, (q15_t)0x7ecc, (q15_t)0xee82, + (q15_t)0x7ecb, (q15_t)0xee7c, (q15_t)0x7eca, (q15_t)0xee76, (q15_t)0x7ec9, (q15_t)0xee6f, (q15_t)0x7ec9, (q15_t)0xee69, + (q15_t)0x7ec8, (q15_t)0xee63, (q15_t)0x7ec7, (q15_t)0xee5d, (q15_t)0x7ec6, (q15_t)0xee57, (q15_t)0x7ec5, (q15_t)0xee50, + (q15_t)0x7ec4, (q15_t)0xee4a, (q15_t)0x7ec3, (q15_t)0xee44, (q15_t)0x7ec3, (q15_t)0xee3e, (q15_t)0x7ec2, (q15_t)0xee37, + (q15_t)0x7ec1, (q15_t)0xee31, (q15_t)0x7ec0, (q15_t)0xee2b, (q15_t)0x7ebf, (q15_t)0xee25, (q15_t)0x7ebe, (q15_t)0xee1f, + (q15_t)0x7ebd, (q15_t)0xee18, (q15_t)0x7ebc, (q15_t)0xee12, (q15_t)0x7ebb, (q15_t)0xee0c, (q15_t)0x7ebb, (q15_t)0xee06, + (q15_t)0x7eba, (q15_t)0xedff, (q15_t)0x7eb9, (q15_t)0xedf9, (q15_t)0x7eb8, (q15_t)0xedf3, (q15_t)0x7eb7, (q15_t)0xeded, + (q15_t)0x7eb6, (q15_t)0xede7, (q15_t)0x7eb5, (q15_t)0xede0, (q15_t)0x7eb4, (q15_t)0xedda, (q15_t)0x7eb4, (q15_t)0xedd4, + (q15_t)0x7eb3, (q15_t)0xedce, (q15_t)0x7eb2, (q15_t)0xedc7, (q15_t)0x7eb1, (q15_t)0xedc1, (q15_t)0x7eb0, (q15_t)0xedbb, + (q15_t)0x7eaf, (q15_t)0xedb5, (q15_t)0x7eae, (q15_t)0xedaf, (q15_t)0x7ead, (q15_t)0xeda8, (q15_t)0x7eac, (q15_t)0xeda2, + (q15_t)0x7eab, (q15_t)0xed9c, (q15_t)0x7eab, (q15_t)0xed96, (q15_t)0x7eaa, (q15_t)0xed8f, (q15_t)0x7ea9, (q15_t)0xed89, + (q15_t)0x7ea8, (q15_t)0xed83, (q15_t)0x7ea7, (q15_t)0xed7d, (q15_t)0x7ea6, (q15_t)0xed77, (q15_t)0x7ea5, (q15_t)0xed70, + (q15_t)0x7ea4, (q15_t)0xed6a, (q15_t)0x7ea3, (q15_t)0xed64, (q15_t)0x7ea2, (q15_t)0xed5e, (q15_t)0x7ea1, (q15_t)0xed58, + (q15_t)0x7ea1, (q15_t)0xed51, (q15_t)0x7ea0, (q15_t)0xed4b, (q15_t)0x7e9f, (q15_t)0xed45, (q15_t)0x7e9e, (q15_t)0xed3f, + (q15_t)0x7e9d, (q15_t)0xed38, (q15_t)0x7e9c, (q15_t)0xed32, (q15_t)0x7e9b, (q15_t)0xed2c, (q15_t)0x7e9a, (q15_t)0xed26, + (q15_t)0x7e99, (q15_t)0xed20, (q15_t)0x7e98, (q15_t)0xed19, (q15_t)0x7e97, (q15_t)0xed13, (q15_t)0x7e96, (q15_t)0xed0d, + (q15_t)0x7e95, (q15_t)0xed07, (q15_t)0x7e94, (q15_t)0xed01, (q15_t)0x7e94, (q15_t)0xecfa, (q15_t)0x7e93, (q15_t)0xecf4, + (q15_t)0x7e92, (q15_t)0xecee, (q15_t)0x7e91, (q15_t)0xece8, (q15_t)0x7e90, (q15_t)0xece1, (q15_t)0x7e8f, (q15_t)0xecdb, + (q15_t)0x7e8e, (q15_t)0xecd5, (q15_t)0x7e8d, (q15_t)0xeccf, (q15_t)0x7e8c, (q15_t)0xecc9, (q15_t)0x7e8b, (q15_t)0xecc2, + (q15_t)0x7e8a, (q15_t)0xecbc, (q15_t)0x7e89, (q15_t)0xecb6, (q15_t)0x7e88, (q15_t)0xecb0, (q15_t)0x7e87, (q15_t)0xecaa, + (q15_t)0x7e86, (q15_t)0xeca3, (q15_t)0x7e85, (q15_t)0xec9d, (q15_t)0x7e84, (q15_t)0xec97, (q15_t)0x7e84, (q15_t)0xec91, + (q15_t)0x7e83, (q15_t)0xec8a, (q15_t)0x7e82, (q15_t)0xec84, (q15_t)0x7e81, (q15_t)0xec7e, (q15_t)0x7e80, (q15_t)0xec78, + (q15_t)0x7e7f, (q15_t)0xec72, (q15_t)0x7e7e, (q15_t)0xec6b, (q15_t)0x7e7d, (q15_t)0xec65, (q15_t)0x7e7c, (q15_t)0xec5f, + (q15_t)0x7e7b, (q15_t)0xec59, (q15_t)0x7e7a, (q15_t)0xec53, (q15_t)0x7e79, (q15_t)0xec4c, (q15_t)0x7e78, (q15_t)0xec46, + (q15_t)0x7e77, (q15_t)0xec40, (q15_t)0x7e76, (q15_t)0xec3a, (q15_t)0x7e75, (q15_t)0xec34, (q15_t)0x7e74, (q15_t)0xec2d, + (q15_t)0x7e73, (q15_t)0xec27, (q15_t)0x7e72, (q15_t)0xec21, (q15_t)0x7e71, (q15_t)0xec1b, (q15_t)0x7e70, (q15_t)0xec15, + (q15_t)0x7e6f, (q15_t)0xec0e, (q15_t)0x7e6e, (q15_t)0xec08, (q15_t)0x7e6d, (q15_t)0xec02, (q15_t)0x7e6c, (q15_t)0xebfc, + (q15_t)0x7e6b, (q15_t)0xebf5, (q15_t)0x7e6a, (q15_t)0xebef, (q15_t)0x7e69, (q15_t)0xebe9, (q15_t)0x7e68, (q15_t)0xebe3, + (q15_t)0x7e67, (q15_t)0xebdd, (q15_t)0x7e66, (q15_t)0xebd6, (q15_t)0x7e65, (q15_t)0xebd0, (q15_t)0x7e64, (q15_t)0xebca, + (q15_t)0x7e63, (q15_t)0xebc4, (q15_t)0x7e62, (q15_t)0xebbe, (q15_t)0x7e61, (q15_t)0xebb7, (q15_t)0x7e60, (q15_t)0xebb1, + (q15_t)0x7e5f, (q15_t)0xebab, (q15_t)0x7e5e, (q15_t)0xeba5, (q15_t)0x7e5d, (q15_t)0xeb9f, (q15_t)0x7e5c, (q15_t)0xeb98, + (q15_t)0x7e5b, (q15_t)0xeb92, (q15_t)0x7e5a, (q15_t)0xeb8c, (q15_t)0x7e59, (q15_t)0xeb86, (q15_t)0x7e58, (q15_t)0xeb80, + (q15_t)0x7e57, (q15_t)0xeb79, (q15_t)0x7e56, (q15_t)0xeb73, (q15_t)0x7e55, (q15_t)0xeb6d, (q15_t)0x7e54, (q15_t)0xeb67, + (q15_t)0x7e53, (q15_t)0xeb61, (q15_t)0x7e52, (q15_t)0xeb5a, (q15_t)0x7e51, (q15_t)0xeb54, (q15_t)0x7e50, (q15_t)0xeb4e, + (q15_t)0x7e4f, (q15_t)0xeb48, (q15_t)0x7e4e, (q15_t)0xeb42, (q15_t)0x7e4d, (q15_t)0xeb3b, (q15_t)0x7e4c, (q15_t)0xeb35, + (q15_t)0x7e4b, (q15_t)0xeb2f, (q15_t)0x7e4a, (q15_t)0xeb29, (q15_t)0x7e49, (q15_t)0xeb23, (q15_t)0x7e48, (q15_t)0xeb1c, + (q15_t)0x7e47, (q15_t)0xeb16, (q15_t)0x7e46, (q15_t)0xeb10, (q15_t)0x7e45, (q15_t)0xeb0a, (q15_t)0x7e44, (q15_t)0xeb04, + (q15_t)0x7e43, (q15_t)0xeafd, (q15_t)0x7e42, (q15_t)0xeaf7, (q15_t)0x7e41, (q15_t)0xeaf1, (q15_t)0x7e40, (q15_t)0xeaeb, + (q15_t)0x7e3f, (q15_t)0xeae5, (q15_t)0x7e3e, (q15_t)0xeade, (q15_t)0x7e3d, (q15_t)0xead8, (q15_t)0x7e3c, (q15_t)0xead2, + (q15_t)0x7e3b, (q15_t)0xeacc, (q15_t)0x7e3a, (q15_t)0xeac6, (q15_t)0x7e39, (q15_t)0xeabf, (q15_t)0x7e38, (q15_t)0xeab9, + (q15_t)0x7e37, (q15_t)0xeab3, (q15_t)0x7e35, (q15_t)0xeaad, (q15_t)0x7e34, (q15_t)0xeaa7, (q15_t)0x7e33, (q15_t)0xeaa0, + (q15_t)0x7e32, (q15_t)0xea9a, (q15_t)0x7e31, (q15_t)0xea94, (q15_t)0x7e30, (q15_t)0xea8e, (q15_t)0x7e2f, (q15_t)0xea88, + (q15_t)0x7e2e, (q15_t)0xea81, (q15_t)0x7e2d, (q15_t)0xea7b, (q15_t)0x7e2c, (q15_t)0xea75, (q15_t)0x7e2b, (q15_t)0xea6f, + (q15_t)0x7e2a, (q15_t)0xea69, (q15_t)0x7e29, (q15_t)0xea63, (q15_t)0x7e28, (q15_t)0xea5c, (q15_t)0x7e27, (q15_t)0xea56, + (q15_t)0x7e26, (q15_t)0xea50, (q15_t)0x7e25, (q15_t)0xea4a, (q15_t)0x7e24, (q15_t)0xea44, (q15_t)0x7e22, (q15_t)0xea3d, + (q15_t)0x7e21, (q15_t)0xea37, (q15_t)0x7e20, (q15_t)0xea31, (q15_t)0x7e1f, (q15_t)0xea2b, (q15_t)0x7e1e, (q15_t)0xea25, + (q15_t)0x7e1d, (q15_t)0xea1e, (q15_t)0x7e1c, (q15_t)0xea18, (q15_t)0x7e1b, (q15_t)0xea12, (q15_t)0x7e1a, (q15_t)0xea0c, + (q15_t)0x7e19, (q15_t)0xea06, (q15_t)0x7e18, (q15_t)0xe9ff, (q15_t)0x7e17, (q15_t)0xe9f9, (q15_t)0x7e16, (q15_t)0xe9f3, + (q15_t)0x7e14, (q15_t)0xe9ed, (q15_t)0x7e13, (q15_t)0xe9e7, (q15_t)0x7e12, (q15_t)0xe9e1, (q15_t)0x7e11, (q15_t)0xe9da, + (q15_t)0x7e10, (q15_t)0xe9d4, (q15_t)0x7e0f, (q15_t)0xe9ce, (q15_t)0x7e0e, (q15_t)0xe9c8, (q15_t)0x7e0d, (q15_t)0xe9c2, + (q15_t)0x7e0c, (q15_t)0xe9bb, (q15_t)0x7e0b, (q15_t)0xe9b5, (q15_t)0x7e0a, (q15_t)0xe9af, (q15_t)0x7e08, (q15_t)0xe9a9, + (q15_t)0x7e07, (q15_t)0xe9a3, (q15_t)0x7e06, (q15_t)0xe99c, (q15_t)0x7e05, (q15_t)0xe996, (q15_t)0x7e04, (q15_t)0xe990, + (q15_t)0x7e03, (q15_t)0xe98a, (q15_t)0x7e02, (q15_t)0xe984, (q15_t)0x7e01, (q15_t)0xe97e, (q15_t)0x7e00, (q15_t)0xe977, + (q15_t)0x7dff, (q15_t)0xe971, (q15_t)0x7dfd, (q15_t)0xe96b, (q15_t)0x7dfc, (q15_t)0xe965, (q15_t)0x7dfb, (q15_t)0xe95f, + (q15_t)0x7dfa, (q15_t)0xe958, (q15_t)0x7df9, (q15_t)0xe952, (q15_t)0x7df8, (q15_t)0xe94c, (q15_t)0x7df7, (q15_t)0xe946, + (q15_t)0x7df6, (q15_t)0xe940, (q15_t)0x7df5, (q15_t)0xe93a, (q15_t)0x7df3, (q15_t)0xe933, (q15_t)0x7df2, (q15_t)0xe92d, + (q15_t)0x7df1, (q15_t)0xe927, (q15_t)0x7df0, (q15_t)0xe921, (q15_t)0x7def, (q15_t)0xe91b, (q15_t)0x7dee, (q15_t)0xe914, + (q15_t)0x7ded, (q15_t)0xe90e, (q15_t)0x7dec, (q15_t)0xe908, (q15_t)0x7dea, (q15_t)0xe902, (q15_t)0x7de9, (q15_t)0xe8fc, + (q15_t)0x7de8, (q15_t)0xe8f6, (q15_t)0x7de7, (q15_t)0xe8ef, (q15_t)0x7de6, (q15_t)0xe8e9, (q15_t)0x7de5, (q15_t)0xe8e3, + (q15_t)0x7de4, (q15_t)0xe8dd, (q15_t)0x7de2, (q15_t)0xe8d7, (q15_t)0x7de1, (q15_t)0xe8d0, (q15_t)0x7de0, (q15_t)0xe8ca, + (q15_t)0x7ddf, (q15_t)0xe8c4, (q15_t)0x7dde, (q15_t)0xe8be, (q15_t)0x7ddd, (q15_t)0xe8b8, (q15_t)0x7ddc, (q15_t)0xe8b2, + (q15_t)0x7dda, (q15_t)0xe8ab, (q15_t)0x7dd9, (q15_t)0xe8a5, (q15_t)0x7dd8, (q15_t)0xe89f, (q15_t)0x7dd7, (q15_t)0xe899, + (q15_t)0x7dd6, (q15_t)0xe893, (q15_t)0x7dd5, (q15_t)0xe88c, (q15_t)0x7dd4, (q15_t)0xe886, (q15_t)0x7dd2, (q15_t)0xe880, + (q15_t)0x7dd1, (q15_t)0xe87a, (q15_t)0x7dd0, (q15_t)0xe874, (q15_t)0x7dcf, (q15_t)0xe86e, (q15_t)0x7dce, (q15_t)0xe867, + (q15_t)0x7dcd, (q15_t)0xe861, (q15_t)0x7dcc, (q15_t)0xe85b, (q15_t)0x7dca, (q15_t)0xe855, (q15_t)0x7dc9, (q15_t)0xe84f, + (q15_t)0x7dc8, (q15_t)0xe849, (q15_t)0x7dc7, (q15_t)0xe842, (q15_t)0x7dc6, (q15_t)0xe83c, (q15_t)0x7dc5, (q15_t)0xe836, + (q15_t)0x7dc3, (q15_t)0xe830, (q15_t)0x7dc2, (q15_t)0xe82a, (q15_t)0x7dc1, (q15_t)0xe823, (q15_t)0x7dc0, (q15_t)0xe81d, + (q15_t)0x7dbf, (q15_t)0xe817, (q15_t)0x7dbd, (q15_t)0xe811, (q15_t)0x7dbc, (q15_t)0xe80b, (q15_t)0x7dbb, (q15_t)0xe805, + (q15_t)0x7dba, (q15_t)0xe7fe, (q15_t)0x7db9, (q15_t)0xe7f8, (q15_t)0x7db8, (q15_t)0xe7f2, (q15_t)0x7db6, (q15_t)0xe7ec, + (q15_t)0x7db5, (q15_t)0xe7e6, (q15_t)0x7db4, (q15_t)0xe7e0, (q15_t)0x7db3, (q15_t)0xe7d9, (q15_t)0x7db2, (q15_t)0xe7d3, + (q15_t)0x7db0, (q15_t)0xe7cd, (q15_t)0x7daf, (q15_t)0xe7c7, (q15_t)0x7dae, (q15_t)0xe7c1, (q15_t)0x7dad, (q15_t)0xe7bb, + (q15_t)0x7dac, (q15_t)0xe7b4, (q15_t)0x7dab, (q15_t)0xe7ae, (q15_t)0x7da9, (q15_t)0xe7a8, (q15_t)0x7da8, (q15_t)0xe7a2, + (q15_t)0x7da7, (q15_t)0xe79c, (q15_t)0x7da6, (q15_t)0xe796, (q15_t)0x7da5, (q15_t)0xe78f, (q15_t)0x7da3, (q15_t)0xe789, + (q15_t)0x7da2, (q15_t)0xe783, (q15_t)0x7da1, (q15_t)0xe77d, (q15_t)0x7da0, (q15_t)0xe777, (q15_t)0x7d9f, (q15_t)0xe771, + (q15_t)0x7d9d, (q15_t)0xe76a, (q15_t)0x7d9c, (q15_t)0xe764, (q15_t)0x7d9b, (q15_t)0xe75e, (q15_t)0x7d9a, (q15_t)0xe758, + (q15_t)0x7d98, (q15_t)0xe752, (q15_t)0x7d97, (q15_t)0xe74c, (q15_t)0x7d96, (q15_t)0xe745, (q15_t)0x7d95, (q15_t)0xe73f, + (q15_t)0x7d94, (q15_t)0xe739, (q15_t)0x7d92, (q15_t)0xe733, (q15_t)0x7d91, (q15_t)0xe72d, (q15_t)0x7d90, (q15_t)0xe727, + (q15_t)0x7d8f, (q15_t)0xe720, (q15_t)0x7d8e, (q15_t)0xe71a, (q15_t)0x7d8c, (q15_t)0xe714, (q15_t)0x7d8b, (q15_t)0xe70e, + (q15_t)0x7d8a, (q15_t)0xe708, (q15_t)0x7d89, (q15_t)0xe702, (q15_t)0x7d87, (q15_t)0xe6fb, (q15_t)0x7d86, (q15_t)0xe6f5, + (q15_t)0x7d85, (q15_t)0xe6ef, (q15_t)0x7d84, (q15_t)0xe6e9, (q15_t)0x7d82, (q15_t)0xe6e3, (q15_t)0x7d81, (q15_t)0xe6dd, + (q15_t)0x7d80, (q15_t)0xe6d6, (q15_t)0x7d7f, (q15_t)0xe6d0, (q15_t)0x7d7e, (q15_t)0xe6ca, (q15_t)0x7d7c, (q15_t)0xe6c4, + (q15_t)0x7d7b, (q15_t)0xe6be, (q15_t)0x7d7a, (q15_t)0xe6b8, (q15_t)0x7d79, (q15_t)0xe6b2, (q15_t)0x7d77, (q15_t)0xe6ab, + (q15_t)0x7d76, (q15_t)0xe6a5, (q15_t)0x7d75, (q15_t)0xe69f, (q15_t)0x7d74, (q15_t)0xe699, (q15_t)0x7d72, (q15_t)0xe693, + (q15_t)0x7d71, (q15_t)0xe68d, (q15_t)0x7d70, (q15_t)0xe686, (q15_t)0x7d6f, (q15_t)0xe680, (q15_t)0x7d6d, (q15_t)0xe67a, + (q15_t)0x7d6c, (q15_t)0xe674, (q15_t)0x7d6b, (q15_t)0xe66e, (q15_t)0x7d6a, (q15_t)0xe668, (q15_t)0x7d68, (q15_t)0xe661, + (q15_t)0x7d67, (q15_t)0xe65b, (q15_t)0x7d66, (q15_t)0xe655, (q15_t)0x7d65, (q15_t)0xe64f, (q15_t)0x7d63, (q15_t)0xe649, + (q15_t)0x7d62, (q15_t)0xe643, (q15_t)0x7d61, (q15_t)0xe63d, (q15_t)0x7d60, (q15_t)0xe636, (q15_t)0x7d5e, (q15_t)0xe630, + (q15_t)0x7d5d, (q15_t)0xe62a, (q15_t)0x7d5c, (q15_t)0xe624, (q15_t)0x7d5a, (q15_t)0xe61e, (q15_t)0x7d59, (q15_t)0xe618, + (q15_t)0x7d58, (q15_t)0xe611, (q15_t)0x7d57, (q15_t)0xe60b, (q15_t)0x7d55, (q15_t)0xe605, (q15_t)0x7d54, (q15_t)0xe5ff, + (q15_t)0x7d53, (q15_t)0xe5f9, (q15_t)0x7d52, (q15_t)0xe5f3, (q15_t)0x7d50, (q15_t)0xe5ed, (q15_t)0x7d4f, (q15_t)0xe5e6, + (q15_t)0x7d4e, (q15_t)0xe5e0, (q15_t)0x7d4c, (q15_t)0xe5da, (q15_t)0x7d4b, (q15_t)0xe5d4, (q15_t)0x7d4a, (q15_t)0xe5ce, + (q15_t)0x7d49, (q15_t)0xe5c8, (q15_t)0x7d47, (q15_t)0xe5c2, (q15_t)0x7d46, (q15_t)0xe5bb, (q15_t)0x7d45, (q15_t)0xe5b5, + (q15_t)0x7d43, (q15_t)0xe5af, (q15_t)0x7d42, (q15_t)0xe5a9, (q15_t)0x7d41, (q15_t)0xe5a3, (q15_t)0x7d3f, (q15_t)0xe59d, + (q15_t)0x7d3e, (q15_t)0xe596, (q15_t)0x7d3d, (q15_t)0xe590, (q15_t)0x7d3c, (q15_t)0xe58a, (q15_t)0x7d3a, (q15_t)0xe584, + (q15_t)0x7d39, (q15_t)0xe57e, (q15_t)0x7d38, (q15_t)0xe578, (q15_t)0x7d36, (q15_t)0xe572, (q15_t)0x7d35, (q15_t)0xe56b, + (q15_t)0x7d34, (q15_t)0xe565, (q15_t)0x7d32, (q15_t)0xe55f, (q15_t)0x7d31, (q15_t)0xe559, (q15_t)0x7d30, (q15_t)0xe553, + (q15_t)0x7d2f, (q15_t)0xe54d, (q15_t)0x7d2d, (q15_t)0xe547, (q15_t)0x7d2c, (q15_t)0xe540, (q15_t)0x7d2b, (q15_t)0xe53a, + (q15_t)0x7d29, (q15_t)0xe534, (q15_t)0x7d28, (q15_t)0xe52e, (q15_t)0x7d27, (q15_t)0xe528, (q15_t)0x7d25, (q15_t)0xe522, + (q15_t)0x7d24, (q15_t)0xe51c, (q15_t)0x7d23, (q15_t)0xe515, (q15_t)0x7d21, (q15_t)0xe50f, (q15_t)0x7d20, (q15_t)0xe509, + (q15_t)0x7d1f, (q15_t)0xe503, (q15_t)0x7d1d, (q15_t)0xe4fd, (q15_t)0x7d1c, (q15_t)0xe4f7, (q15_t)0x7d1b, (q15_t)0xe4f1, + (q15_t)0x7d19, (q15_t)0xe4ea, (q15_t)0x7d18, (q15_t)0xe4e4, (q15_t)0x7d17, (q15_t)0xe4de, (q15_t)0x7d15, (q15_t)0xe4d8, + (q15_t)0x7d14, (q15_t)0xe4d2, (q15_t)0x7d13, (q15_t)0xe4cc, (q15_t)0x7d11, (q15_t)0xe4c6, (q15_t)0x7d10, (q15_t)0xe4bf, + (q15_t)0x7d0f, (q15_t)0xe4b9, (q15_t)0x7d0d, (q15_t)0xe4b3, (q15_t)0x7d0c, (q15_t)0xe4ad, (q15_t)0x7d0b, (q15_t)0xe4a7, + (q15_t)0x7d09, (q15_t)0xe4a1, (q15_t)0x7d08, (q15_t)0xe49b, (q15_t)0x7d07, (q15_t)0xe494, (q15_t)0x7d05, (q15_t)0xe48e, + (q15_t)0x7d04, (q15_t)0xe488, (q15_t)0x7d03, (q15_t)0xe482, (q15_t)0x7d01, (q15_t)0xe47c, (q15_t)0x7d00, (q15_t)0xe476, + (q15_t)0x7cff, (q15_t)0xe470, (q15_t)0x7cfd, (q15_t)0xe46a, (q15_t)0x7cfc, (q15_t)0xe463, (q15_t)0x7cfb, (q15_t)0xe45d, + (q15_t)0x7cf9, (q15_t)0xe457, (q15_t)0x7cf8, (q15_t)0xe451, (q15_t)0x7cf6, (q15_t)0xe44b, (q15_t)0x7cf5, (q15_t)0xe445, + (q15_t)0x7cf4, (q15_t)0xe43f, (q15_t)0x7cf2, (q15_t)0xe438, (q15_t)0x7cf1, (q15_t)0xe432, (q15_t)0x7cf0, (q15_t)0xe42c, + (q15_t)0x7cee, (q15_t)0xe426, (q15_t)0x7ced, (q15_t)0xe420, (q15_t)0x7cec, (q15_t)0xe41a, (q15_t)0x7cea, (q15_t)0xe414, + (q15_t)0x7ce9, (q15_t)0xe40e, (q15_t)0x7ce7, (q15_t)0xe407, (q15_t)0x7ce6, (q15_t)0xe401, (q15_t)0x7ce5, (q15_t)0xe3fb, + (q15_t)0x7ce3, (q15_t)0xe3f5, (q15_t)0x7ce2, (q15_t)0xe3ef, (q15_t)0x7ce1, (q15_t)0xe3e9, (q15_t)0x7cdf, (q15_t)0xe3e3, + (q15_t)0x7cde, (q15_t)0xe3dc, (q15_t)0x7cdc, (q15_t)0xe3d6, (q15_t)0x7cdb, (q15_t)0xe3d0, (q15_t)0x7cda, (q15_t)0xe3ca, + (q15_t)0x7cd8, (q15_t)0xe3c4, (q15_t)0x7cd7, (q15_t)0xe3be, (q15_t)0x7cd5, (q15_t)0xe3b8, (q15_t)0x7cd4, (q15_t)0xe3b2, + (q15_t)0x7cd3, (q15_t)0xe3ab, (q15_t)0x7cd1, (q15_t)0xe3a5, (q15_t)0x7cd0, (q15_t)0xe39f, (q15_t)0x7ccf, (q15_t)0xe399, + (q15_t)0x7ccd, (q15_t)0xe393, (q15_t)0x7ccc, (q15_t)0xe38d, (q15_t)0x7cca, (q15_t)0xe387, (q15_t)0x7cc9, (q15_t)0xe381, + (q15_t)0x7cc8, (q15_t)0xe37a, (q15_t)0x7cc6, (q15_t)0xe374, (q15_t)0x7cc5, (q15_t)0xe36e, (q15_t)0x7cc3, (q15_t)0xe368, + (q15_t)0x7cc2, (q15_t)0xe362, (q15_t)0x7cc1, (q15_t)0xe35c, (q15_t)0x7cbf, (q15_t)0xe356, (q15_t)0x7cbe, (q15_t)0xe350, + (q15_t)0x7cbc, (q15_t)0xe349, (q15_t)0x7cbb, (q15_t)0xe343, (q15_t)0x7cb9, (q15_t)0xe33d, (q15_t)0x7cb8, (q15_t)0xe337, + (q15_t)0x7cb7, (q15_t)0xe331, (q15_t)0x7cb5, (q15_t)0xe32b, (q15_t)0x7cb4, (q15_t)0xe325, (q15_t)0x7cb2, (q15_t)0xe31f, + (q15_t)0x7cb1, (q15_t)0xe318, (q15_t)0x7cb0, (q15_t)0xe312, (q15_t)0x7cae, (q15_t)0xe30c, (q15_t)0x7cad, (q15_t)0xe306, + (q15_t)0x7cab, (q15_t)0xe300, (q15_t)0x7caa, (q15_t)0xe2fa, (q15_t)0x7ca8, (q15_t)0xe2f4, (q15_t)0x7ca7, (q15_t)0xe2ee, + (q15_t)0x7ca6, (q15_t)0xe2e8, (q15_t)0x7ca4, (q15_t)0xe2e1, (q15_t)0x7ca3, (q15_t)0xe2db, (q15_t)0x7ca1, (q15_t)0xe2d5, + (q15_t)0x7ca0, (q15_t)0xe2cf, (q15_t)0x7c9e, (q15_t)0xe2c9, (q15_t)0x7c9d, (q15_t)0xe2c3, (q15_t)0x7c9c, (q15_t)0xe2bd, + (q15_t)0x7c9a, (q15_t)0xe2b7, (q15_t)0x7c99, (q15_t)0xe2b0, (q15_t)0x7c97, (q15_t)0xe2aa, (q15_t)0x7c96, (q15_t)0xe2a4, + (q15_t)0x7c94, (q15_t)0xe29e, (q15_t)0x7c93, (q15_t)0xe298, (q15_t)0x7c91, (q15_t)0xe292, (q15_t)0x7c90, (q15_t)0xe28c, + (q15_t)0x7c8f, (q15_t)0xe286, (q15_t)0x7c8d, (q15_t)0xe280, (q15_t)0x7c8c, (q15_t)0xe279, (q15_t)0x7c8a, (q15_t)0xe273, + (q15_t)0x7c89, (q15_t)0xe26d, (q15_t)0x7c87, (q15_t)0xe267, (q15_t)0x7c86, (q15_t)0xe261, (q15_t)0x7c84, (q15_t)0xe25b, + (q15_t)0x7c83, (q15_t)0xe255, (q15_t)0x7c82, (q15_t)0xe24f, (q15_t)0x7c80, (q15_t)0xe249, (q15_t)0x7c7f, (q15_t)0xe242, + (q15_t)0x7c7d, (q15_t)0xe23c, (q15_t)0x7c7c, (q15_t)0xe236, (q15_t)0x7c7a, (q15_t)0xe230, (q15_t)0x7c79, (q15_t)0xe22a, + (q15_t)0x7c77, (q15_t)0xe224, (q15_t)0x7c76, (q15_t)0xe21e, (q15_t)0x7c74, (q15_t)0xe218, (q15_t)0x7c73, (q15_t)0xe212, + (q15_t)0x7c71, (q15_t)0xe20b, (q15_t)0x7c70, (q15_t)0xe205, (q15_t)0x7c6e, (q15_t)0xe1ff, (q15_t)0x7c6d, (q15_t)0xe1f9, + (q15_t)0x7c6c, (q15_t)0xe1f3, (q15_t)0x7c6a, (q15_t)0xe1ed, (q15_t)0x7c69, (q15_t)0xe1e7, (q15_t)0x7c67, (q15_t)0xe1e1, + (q15_t)0x7c66, (q15_t)0xe1db, (q15_t)0x7c64, (q15_t)0xe1d4, (q15_t)0x7c63, (q15_t)0xe1ce, (q15_t)0x7c61, (q15_t)0xe1c8, + (q15_t)0x7c60, (q15_t)0xe1c2, (q15_t)0x7c5e, (q15_t)0xe1bc, (q15_t)0x7c5d, (q15_t)0xe1b6, (q15_t)0x7c5b, (q15_t)0xe1b0, + (q15_t)0x7c5a, (q15_t)0xe1aa, (q15_t)0x7c58, (q15_t)0xe1a4, (q15_t)0x7c57, (q15_t)0xe19e, (q15_t)0x7c55, (q15_t)0xe197, + (q15_t)0x7c54, (q15_t)0xe191, (q15_t)0x7c52, (q15_t)0xe18b, (q15_t)0x7c51, (q15_t)0xe185, (q15_t)0x7c4f, (q15_t)0xe17f, + (q15_t)0x7c4e, (q15_t)0xe179, (q15_t)0x7c4c, (q15_t)0xe173, (q15_t)0x7c4b, (q15_t)0xe16d, (q15_t)0x7c49, (q15_t)0xe167, + (q15_t)0x7c48, (q15_t)0xe160, (q15_t)0x7c46, (q15_t)0xe15a, (q15_t)0x7c45, (q15_t)0xe154, (q15_t)0x7c43, (q15_t)0xe14e, + (q15_t)0x7c42, (q15_t)0xe148, (q15_t)0x7c40, (q15_t)0xe142, (q15_t)0x7c3f, (q15_t)0xe13c, (q15_t)0x7c3d, (q15_t)0xe136, + (q15_t)0x7c3c, (q15_t)0xe130, (q15_t)0x7c3a, (q15_t)0xe12a, (q15_t)0x7c39, (q15_t)0xe123, (q15_t)0x7c37, (q15_t)0xe11d, + (q15_t)0x7c36, (q15_t)0xe117, (q15_t)0x7c34, (q15_t)0xe111, (q15_t)0x7c33, (q15_t)0xe10b, (q15_t)0x7c31, (q15_t)0xe105, + (q15_t)0x7c30, (q15_t)0xe0ff, (q15_t)0x7c2e, (q15_t)0xe0f9, (q15_t)0x7c2d, (q15_t)0xe0f3, (q15_t)0x7c2b, (q15_t)0xe0ed, + (q15_t)0x7c29, (q15_t)0xe0e7, (q15_t)0x7c28, (q15_t)0xe0e0, (q15_t)0x7c26, (q15_t)0xe0da, (q15_t)0x7c25, (q15_t)0xe0d4, + (q15_t)0x7c23, (q15_t)0xe0ce, (q15_t)0x7c22, (q15_t)0xe0c8, (q15_t)0x7c20, (q15_t)0xe0c2, (q15_t)0x7c1f, (q15_t)0xe0bc, + (q15_t)0x7c1d, (q15_t)0xe0b6, (q15_t)0x7c1c, (q15_t)0xe0b0, (q15_t)0x7c1a, (q15_t)0xe0aa, (q15_t)0x7c19, (q15_t)0xe0a3, + (q15_t)0x7c17, (q15_t)0xe09d, (q15_t)0x7c16, (q15_t)0xe097, (q15_t)0x7c14, (q15_t)0xe091, (q15_t)0x7c12, (q15_t)0xe08b, + (q15_t)0x7c11, (q15_t)0xe085, (q15_t)0x7c0f, (q15_t)0xe07f, (q15_t)0x7c0e, (q15_t)0xe079, (q15_t)0x7c0c, (q15_t)0xe073, + (q15_t)0x7c0b, (q15_t)0xe06d, (q15_t)0x7c09, (q15_t)0xe067, (q15_t)0x7c08, (q15_t)0xe061, (q15_t)0x7c06, (q15_t)0xe05a, + (q15_t)0x7c05, (q15_t)0xe054, (q15_t)0x7c03, (q15_t)0xe04e, (q15_t)0x7c01, (q15_t)0xe048, (q15_t)0x7c00, (q15_t)0xe042, + (q15_t)0x7bfe, (q15_t)0xe03c, (q15_t)0x7bfd, (q15_t)0xe036, (q15_t)0x7bfb, (q15_t)0xe030, (q15_t)0x7bfa, (q15_t)0xe02a, + (q15_t)0x7bf8, (q15_t)0xe024, (q15_t)0x7bf6, (q15_t)0xe01e, (q15_t)0x7bf5, (q15_t)0xe017, (q15_t)0x7bf3, (q15_t)0xe011, + (q15_t)0x7bf2, (q15_t)0xe00b, (q15_t)0x7bf0, (q15_t)0xe005, (q15_t)0x7bef, (q15_t)0xdfff, (q15_t)0x7bed, (q15_t)0xdff9, + (q15_t)0x7beb, (q15_t)0xdff3, (q15_t)0x7bea, (q15_t)0xdfed, (q15_t)0x7be8, (q15_t)0xdfe7, (q15_t)0x7be7, (q15_t)0xdfe1, + (q15_t)0x7be5, (q15_t)0xdfdb, (q15_t)0x7be4, (q15_t)0xdfd5, (q15_t)0x7be2, (q15_t)0xdfce, (q15_t)0x7be0, (q15_t)0xdfc8, + (q15_t)0x7bdf, (q15_t)0xdfc2, (q15_t)0x7bdd, (q15_t)0xdfbc, (q15_t)0x7bdc, (q15_t)0xdfb6, (q15_t)0x7bda, (q15_t)0xdfb0, + (q15_t)0x7bd9, (q15_t)0xdfaa, (q15_t)0x7bd7, (q15_t)0xdfa4, (q15_t)0x7bd5, (q15_t)0xdf9e, (q15_t)0x7bd4, (q15_t)0xdf98, + (q15_t)0x7bd2, (q15_t)0xdf92, (q15_t)0x7bd1, (q15_t)0xdf8c, (q15_t)0x7bcf, (q15_t)0xdf86, (q15_t)0x7bcd, (q15_t)0xdf7f, + (q15_t)0x7bcc, (q15_t)0xdf79, (q15_t)0x7bca, (q15_t)0xdf73, (q15_t)0x7bc9, (q15_t)0xdf6d, (q15_t)0x7bc7, (q15_t)0xdf67, + (q15_t)0x7bc5, (q15_t)0xdf61, (q15_t)0x7bc4, (q15_t)0xdf5b, (q15_t)0x7bc2, (q15_t)0xdf55, (q15_t)0x7bc1, (q15_t)0xdf4f, + (q15_t)0x7bbf, (q15_t)0xdf49, (q15_t)0x7bbd, (q15_t)0xdf43, (q15_t)0x7bbc, (q15_t)0xdf3d, (q15_t)0x7bba, (q15_t)0xdf37, + (q15_t)0x7bb9, (q15_t)0xdf30, (q15_t)0x7bb7, (q15_t)0xdf2a, (q15_t)0x7bb5, (q15_t)0xdf24, (q15_t)0x7bb4, (q15_t)0xdf1e, + (q15_t)0x7bb2, (q15_t)0xdf18, (q15_t)0x7bb0, (q15_t)0xdf12, (q15_t)0x7baf, (q15_t)0xdf0c, (q15_t)0x7bad, (q15_t)0xdf06, + (q15_t)0x7bac, (q15_t)0xdf00, (q15_t)0x7baa, (q15_t)0xdefa, (q15_t)0x7ba8, (q15_t)0xdef4, (q15_t)0x7ba7, (q15_t)0xdeee, + (q15_t)0x7ba5, (q15_t)0xdee8, (q15_t)0x7ba3, (q15_t)0xdee2, (q15_t)0x7ba2, (q15_t)0xdedb, (q15_t)0x7ba0, (q15_t)0xded5, + (q15_t)0x7b9f, (q15_t)0xdecf, (q15_t)0x7b9d, (q15_t)0xdec9, (q15_t)0x7b9b, (q15_t)0xdec3, (q15_t)0x7b9a, (q15_t)0xdebd, + (q15_t)0x7b98, (q15_t)0xdeb7, (q15_t)0x7b96, (q15_t)0xdeb1, (q15_t)0x7b95, (q15_t)0xdeab, (q15_t)0x7b93, (q15_t)0xdea5, + (q15_t)0x7b92, (q15_t)0xde9f, (q15_t)0x7b90, (q15_t)0xde99, (q15_t)0x7b8e, (q15_t)0xde93, (q15_t)0x7b8d, (q15_t)0xde8d, + (q15_t)0x7b8b, (q15_t)0xde87, (q15_t)0x7b89, (q15_t)0xde80, (q15_t)0x7b88, (q15_t)0xde7a, (q15_t)0x7b86, (q15_t)0xde74, + (q15_t)0x7b84, (q15_t)0xde6e, (q15_t)0x7b83, (q15_t)0xde68, (q15_t)0x7b81, (q15_t)0xde62, (q15_t)0x7b7f, (q15_t)0xde5c, + (q15_t)0x7b7e, (q15_t)0xde56, (q15_t)0x7b7c, (q15_t)0xde50, (q15_t)0x7b7a, (q15_t)0xde4a, (q15_t)0x7b79, (q15_t)0xde44, + (q15_t)0x7b77, (q15_t)0xde3e, (q15_t)0x7b76, (q15_t)0xde38, (q15_t)0x7b74, (q15_t)0xde32, (q15_t)0x7b72, (q15_t)0xde2c, + (q15_t)0x7b71, (q15_t)0xde26, (q15_t)0x7b6f, (q15_t)0xde1f, (q15_t)0x7b6d, (q15_t)0xde19, (q15_t)0x7b6c, (q15_t)0xde13, + (q15_t)0x7b6a, (q15_t)0xde0d, (q15_t)0x7b68, (q15_t)0xde07, (q15_t)0x7b67, (q15_t)0xde01, (q15_t)0x7b65, (q15_t)0xddfb, + (q15_t)0x7b63, (q15_t)0xddf5, (q15_t)0x7b62, (q15_t)0xddef, (q15_t)0x7b60, (q15_t)0xdde9, (q15_t)0x7b5e, (q15_t)0xdde3, + (q15_t)0x7b5d, (q15_t)0xdddd, (q15_t)0x7b5b, (q15_t)0xddd7, (q15_t)0x7b59, (q15_t)0xddd1, (q15_t)0x7b57, (q15_t)0xddcb, + (q15_t)0x7b56, (q15_t)0xddc5, (q15_t)0x7b54, (q15_t)0xddbf, (q15_t)0x7b52, (q15_t)0xddb9, (q15_t)0x7b51, (q15_t)0xddb2, + (q15_t)0x7b4f, (q15_t)0xddac, (q15_t)0x7b4d, (q15_t)0xdda6, (q15_t)0x7b4c, (q15_t)0xdda0, (q15_t)0x7b4a, (q15_t)0xdd9a, + (q15_t)0x7b48, (q15_t)0xdd94, (q15_t)0x7b47, (q15_t)0xdd8e, (q15_t)0x7b45, (q15_t)0xdd88, (q15_t)0x7b43, (q15_t)0xdd82, + (q15_t)0x7b42, (q15_t)0xdd7c, (q15_t)0x7b40, (q15_t)0xdd76, (q15_t)0x7b3e, (q15_t)0xdd70, (q15_t)0x7b3c, (q15_t)0xdd6a, + (q15_t)0x7b3b, (q15_t)0xdd64, (q15_t)0x7b39, (q15_t)0xdd5e, (q15_t)0x7b37, (q15_t)0xdd58, (q15_t)0x7b36, (q15_t)0xdd52, + (q15_t)0x7b34, (q15_t)0xdd4c, (q15_t)0x7b32, (q15_t)0xdd46, (q15_t)0x7b31, (q15_t)0xdd40, (q15_t)0x7b2f, (q15_t)0xdd39, + (q15_t)0x7b2d, (q15_t)0xdd33, (q15_t)0x7b2b, (q15_t)0xdd2d, (q15_t)0x7b2a, (q15_t)0xdd27, (q15_t)0x7b28, (q15_t)0xdd21, + (q15_t)0x7b26, (q15_t)0xdd1b, (q15_t)0x7b25, (q15_t)0xdd15, (q15_t)0x7b23, (q15_t)0xdd0f, (q15_t)0x7b21, (q15_t)0xdd09, + (q15_t)0x7b1f, (q15_t)0xdd03, (q15_t)0x7b1e, (q15_t)0xdcfd, (q15_t)0x7b1c, (q15_t)0xdcf7, (q15_t)0x7b1a, (q15_t)0xdcf1, + (q15_t)0x7b19, (q15_t)0xdceb, (q15_t)0x7b17, (q15_t)0xdce5, (q15_t)0x7b15, (q15_t)0xdcdf, (q15_t)0x7b13, (q15_t)0xdcd9, + (q15_t)0x7b12, (q15_t)0xdcd3, (q15_t)0x7b10, (q15_t)0xdccd, (q15_t)0x7b0e, (q15_t)0xdcc7, (q15_t)0x7b0c, (q15_t)0xdcc1, + (q15_t)0x7b0b, (q15_t)0xdcbb, (q15_t)0x7b09, (q15_t)0xdcb5, (q15_t)0x7b07, (q15_t)0xdcae, (q15_t)0x7b06, (q15_t)0xdca8, + (q15_t)0x7b04, (q15_t)0xdca2, (q15_t)0x7b02, (q15_t)0xdc9c, (q15_t)0x7b00, (q15_t)0xdc96, (q15_t)0x7aff, (q15_t)0xdc90, + (q15_t)0x7afd, (q15_t)0xdc8a, (q15_t)0x7afb, (q15_t)0xdc84, (q15_t)0x7af9, (q15_t)0xdc7e, (q15_t)0x7af8, (q15_t)0xdc78, + (q15_t)0x7af6, (q15_t)0xdc72, (q15_t)0x7af4, (q15_t)0xdc6c, (q15_t)0x7af2, (q15_t)0xdc66, (q15_t)0x7af1, (q15_t)0xdc60, + (q15_t)0x7aef, (q15_t)0xdc5a, (q15_t)0x7aed, (q15_t)0xdc54, (q15_t)0x7aeb, (q15_t)0xdc4e, (q15_t)0x7aea, (q15_t)0xdc48, + (q15_t)0x7ae8, (q15_t)0xdc42, (q15_t)0x7ae6, (q15_t)0xdc3c, (q15_t)0x7ae4, (q15_t)0xdc36, (q15_t)0x7ae3, (q15_t)0xdc30, + (q15_t)0x7ae1, (q15_t)0xdc2a, (q15_t)0x7adf, (q15_t)0xdc24, (q15_t)0x7add, (q15_t)0xdc1e, (q15_t)0x7adc, (q15_t)0xdc18, + (q15_t)0x7ada, (q15_t)0xdc12, (q15_t)0x7ad8, (q15_t)0xdc0c, (q15_t)0x7ad6, (q15_t)0xdc06, (q15_t)0x7ad5, (q15_t)0xdbff, + (q15_t)0x7ad3, (q15_t)0xdbf9, (q15_t)0x7ad1, (q15_t)0xdbf3, (q15_t)0x7acf, (q15_t)0xdbed, (q15_t)0x7acd, (q15_t)0xdbe7, + (q15_t)0x7acc, (q15_t)0xdbe1, (q15_t)0x7aca, (q15_t)0xdbdb, (q15_t)0x7ac8, (q15_t)0xdbd5, (q15_t)0x7ac6, (q15_t)0xdbcf, + (q15_t)0x7ac5, (q15_t)0xdbc9, (q15_t)0x7ac3, (q15_t)0xdbc3, (q15_t)0x7ac1, (q15_t)0xdbbd, (q15_t)0x7abf, (q15_t)0xdbb7, + (q15_t)0x7abd, (q15_t)0xdbb1, (q15_t)0x7abc, (q15_t)0xdbab, (q15_t)0x7aba, (q15_t)0xdba5, (q15_t)0x7ab8, (q15_t)0xdb9f, + (q15_t)0x7ab6, (q15_t)0xdb99, (q15_t)0x7ab5, (q15_t)0xdb93, (q15_t)0x7ab3, (q15_t)0xdb8d, (q15_t)0x7ab1, (q15_t)0xdb87, + (q15_t)0x7aaf, (q15_t)0xdb81, (q15_t)0x7aad, (q15_t)0xdb7b, (q15_t)0x7aac, (q15_t)0xdb75, (q15_t)0x7aaa, (q15_t)0xdb6f, + (q15_t)0x7aa8, (q15_t)0xdb69, (q15_t)0x7aa6, (q15_t)0xdb63, (q15_t)0x7aa4, (q15_t)0xdb5d, (q15_t)0x7aa3, (q15_t)0xdb57, + (q15_t)0x7aa1, (q15_t)0xdb51, (q15_t)0x7a9f, (q15_t)0xdb4b, (q15_t)0x7a9d, (q15_t)0xdb45, (q15_t)0x7a9b, (q15_t)0xdb3f, + (q15_t)0x7a9a, (q15_t)0xdb39, (q15_t)0x7a98, (q15_t)0xdb33, (q15_t)0x7a96, (q15_t)0xdb2d, (q15_t)0x7a94, (q15_t)0xdb27, + (q15_t)0x7a92, (q15_t)0xdb21, (q15_t)0x7a91, (q15_t)0xdb1b, (q15_t)0x7a8f, (q15_t)0xdb15, (q15_t)0x7a8d, (q15_t)0xdb0f, + (q15_t)0x7a8b, (q15_t)0xdb09, (q15_t)0x7a89, (q15_t)0xdb03, (q15_t)0x7a87, (q15_t)0xdafd, (q15_t)0x7a86, (q15_t)0xdaf7, + (q15_t)0x7a84, (q15_t)0xdaf1, (q15_t)0x7a82, (q15_t)0xdaea, (q15_t)0x7a80, (q15_t)0xdae4, (q15_t)0x7a7e, (q15_t)0xdade, + (q15_t)0x7a7d, (q15_t)0xdad8, (q15_t)0x7a7b, (q15_t)0xdad2, (q15_t)0x7a79, (q15_t)0xdacc, (q15_t)0x7a77, (q15_t)0xdac6, + (q15_t)0x7a75, (q15_t)0xdac0, (q15_t)0x7a73, (q15_t)0xdaba, (q15_t)0x7a72, (q15_t)0xdab4, (q15_t)0x7a70, (q15_t)0xdaae, + (q15_t)0x7a6e, (q15_t)0xdaa8, (q15_t)0x7a6c, (q15_t)0xdaa2, (q15_t)0x7a6a, (q15_t)0xda9c, (q15_t)0x7a68, (q15_t)0xda96, + (q15_t)0x7a67, (q15_t)0xda90, (q15_t)0x7a65, (q15_t)0xda8a, (q15_t)0x7a63, (q15_t)0xda84, (q15_t)0x7a61, (q15_t)0xda7e, + (q15_t)0x7a5f, (q15_t)0xda78, (q15_t)0x7a5d, (q15_t)0xda72, (q15_t)0x7a5c, (q15_t)0xda6c, (q15_t)0x7a5a, (q15_t)0xda66, + (q15_t)0x7a58, (q15_t)0xda60, (q15_t)0x7a56, (q15_t)0xda5a, (q15_t)0x7a54, (q15_t)0xda54, (q15_t)0x7a52, (q15_t)0xda4e, + (q15_t)0x7a50, (q15_t)0xda48, (q15_t)0x7a4f, (q15_t)0xda42, (q15_t)0x7a4d, (q15_t)0xda3c, (q15_t)0x7a4b, (q15_t)0xda36, + (q15_t)0x7a49, (q15_t)0xda30, (q15_t)0x7a47, (q15_t)0xda2a, (q15_t)0x7a45, (q15_t)0xda24, (q15_t)0x7a43, (q15_t)0xda1e, + (q15_t)0x7a42, (q15_t)0xda18, (q15_t)0x7a40, (q15_t)0xda12, (q15_t)0x7a3e, (q15_t)0xda0c, (q15_t)0x7a3c, (q15_t)0xda06, + (q15_t)0x7a3a, (q15_t)0xda00, (q15_t)0x7a38, (q15_t)0xd9fa, (q15_t)0x7a36, (q15_t)0xd9f4, (q15_t)0x7a35, (q15_t)0xd9ee, + (q15_t)0x7a33, (q15_t)0xd9e8, (q15_t)0x7a31, (q15_t)0xd9e2, (q15_t)0x7a2f, (q15_t)0xd9dc, (q15_t)0x7a2d, (q15_t)0xd9d6, + (q15_t)0x7a2b, (q15_t)0xd9d0, (q15_t)0x7a29, (q15_t)0xd9ca, (q15_t)0x7a27, (q15_t)0xd9c4, (q15_t)0x7a26, (q15_t)0xd9be, + (q15_t)0x7a24, (q15_t)0xd9b8, (q15_t)0x7a22, (q15_t)0xd9b2, (q15_t)0x7a20, (q15_t)0xd9ac, (q15_t)0x7a1e, (q15_t)0xd9a6, + (q15_t)0x7a1c, (q15_t)0xd9a0, (q15_t)0x7a1a, (q15_t)0xd99a, (q15_t)0x7a18, (q15_t)0xd994, (q15_t)0x7a16, (q15_t)0xd98e, + (q15_t)0x7a15, (q15_t)0xd988, (q15_t)0x7a13, (q15_t)0xd982, (q15_t)0x7a11, (q15_t)0xd97c, (q15_t)0x7a0f, (q15_t)0xd976, + (q15_t)0x7a0d, (q15_t)0xd970, (q15_t)0x7a0b, (q15_t)0xd96a, (q15_t)0x7a09, (q15_t)0xd964, (q15_t)0x7a07, (q15_t)0xd95e, + (q15_t)0x7a05, (q15_t)0xd958, (q15_t)0x7a04, (q15_t)0xd952, (q15_t)0x7a02, (q15_t)0xd94c, (q15_t)0x7a00, (q15_t)0xd946, + (q15_t)0x79fe, (q15_t)0xd940, (q15_t)0x79fc, (q15_t)0xd93a, (q15_t)0x79fa, (q15_t)0xd934, (q15_t)0x79f8, (q15_t)0xd92e, + (q15_t)0x79f6, (q15_t)0xd928, (q15_t)0x79f4, (q15_t)0xd922, (q15_t)0x79f2, (q15_t)0xd91c, (q15_t)0x79f0, (q15_t)0xd917, + (q15_t)0x79ef, (q15_t)0xd911, (q15_t)0x79ed, (q15_t)0xd90b, (q15_t)0x79eb, (q15_t)0xd905, (q15_t)0x79e9, (q15_t)0xd8ff, + (q15_t)0x79e7, (q15_t)0xd8f9, (q15_t)0x79e5, (q15_t)0xd8f3, (q15_t)0x79e3, (q15_t)0xd8ed, (q15_t)0x79e1, (q15_t)0xd8e7, + (q15_t)0x79df, (q15_t)0xd8e1, (q15_t)0x79dd, (q15_t)0xd8db, (q15_t)0x79db, (q15_t)0xd8d5, (q15_t)0x79d9, (q15_t)0xd8cf, + (q15_t)0x79d8, (q15_t)0xd8c9, (q15_t)0x79d6, (q15_t)0xd8c3, (q15_t)0x79d4, (q15_t)0xd8bd, (q15_t)0x79d2, (q15_t)0xd8b7, + (q15_t)0x79d0, (q15_t)0xd8b1, (q15_t)0x79ce, (q15_t)0xd8ab, (q15_t)0x79cc, (q15_t)0xd8a5, (q15_t)0x79ca, (q15_t)0xd89f, + (q15_t)0x79c8, (q15_t)0xd899, (q15_t)0x79c6, (q15_t)0xd893, (q15_t)0x79c4, (q15_t)0xd88d, (q15_t)0x79c2, (q15_t)0xd887, + (q15_t)0x79c0, (q15_t)0xd881, (q15_t)0x79be, (q15_t)0xd87b, (q15_t)0x79bc, (q15_t)0xd875, (q15_t)0x79bb, (q15_t)0xd86f, + (q15_t)0x79b9, (q15_t)0xd869, (q15_t)0x79b7, (q15_t)0xd863, (q15_t)0x79b5, (q15_t)0xd85d, (q15_t)0x79b3, (q15_t)0xd857, + (q15_t)0x79b1, (q15_t)0xd851, (q15_t)0x79af, (q15_t)0xd84b, (q15_t)0x79ad, (q15_t)0xd845, (q15_t)0x79ab, (q15_t)0xd83f, + (q15_t)0x79a9, (q15_t)0xd839, (q15_t)0x79a7, (q15_t)0xd833, (q15_t)0x79a5, (q15_t)0xd82d, (q15_t)0x79a3, (q15_t)0xd827, + (q15_t)0x79a1, (q15_t)0xd821, (q15_t)0x799f, (q15_t)0xd81b, (q15_t)0x799d, (q15_t)0xd815, (q15_t)0x799b, (q15_t)0xd80f, + (q15_t)0x7999, (q15_t)0xd80a, (q15_t)0x7997, (q15_t)0xd804, (q15_t)0x7995, (q15_t)0xd7fe, (q15_t)0x7993, (q15_t)0xd7f8, + (q15_t)0x7992, (q15_t)0xd7f2, (q15_t)0x7990, (q15_t)0xd7ec, (q15_t)0x798e, (q15_t)0xd7e6, (q15_t)0x798c, (q15_t)0xd7e0, + (q15_t)0x798a, (q15_t)0xd7da, (q15_t)0x7988, (q15_t)0xd7d4, (q15_t)0x7986, (q15_t)0xd7ce, (q15_t)0x7984, (q15_t)0xd7c8, + (q15_t)0x7982, (q15_t)0xd7c2, (q15_t)0x7980, (q15_t)0xd7bc, (q15_t)0x797e, (q15_t)0xd7b6, (q15_t)0x797c, (q15_t)0xd7b0, + (q15_t)0x797a, (q15_t)0xd7aa, (q15_t)0x7978, (q15_t)0xd7a4, (q15_t)0x7976, (q15_t)0xd79e, (q15_t)0x7974, (q15_t)0xd798, + (q15_t)0x7972, (q15_t)0xd792, (q15_t)0x7970, (q15_t)0xd78c, (q15_t)0x796e, (q15_t)0xd786, (q15_t)0x796c, (q15_t)0xd780, + (q15_t)0x796a, (q15_t)0xd77a, (q15_t)0x7968, (q15_t)0xd774, (q15_t)0x7966, (q15_t)0xd76e, (q15_t)0x7964, (q15_t)0xd768, + (q15_t)0x7962, (q15_t)0xd763, (q15_t)0x7960, (q15_t)0xd75d, (q15_t)0x795e, (q15_t)0xd757, (q15_t)0x795c, (q15_t)0xd751, + (q15_t)0x795a, (q15_t)0xd74b, (q15_t)0x7958, (q15_t)0xd745, (q15_t)0x7956, (q15_t)0xd73f, (q15_t)0x7954, (q15_t)0xd739, + (q15_t)0x7952, (q15_t)0xd733, (q15_t)0x7950, (q15_t)0xd72d, (q15_t)0x794e, (q15_t)0xd727, (q15_t)0x794c, (q15_t)0xd721, + (q15_t)0x794a, (q15_t)0xd71b, (q15_t)0x7948, (q15_t)0xd715, (q15_t)0x7946, (q15_t)0xd70f, (q15_t)0x7944, (q15_t)0xd709, + (q15_t)0x7942, (q15_t)0xd703, (q15_t)0x7940, (q15_t)0xd6fd, (q15_t)0x793e, (q15_t)0xd6f7, (q15_t)0x793c, (q15_t)0xd6f1, + (q15_t)0x793a, (q15_t)0xd6eb, (q15_t)0x7938, (q15_t)0xd6e5, (q15_t)0x7936, (q15_t)0xd6e0, (q15_t)0x7934, (q15_t)0xd6da, + (q15_t)0x7932, (q15_t)0xd6d4, (q15_t)0x7930, (q15_t)0xd6ce, (q15_t)0x792e, (q15_t)0xd6c8, (q15_t)0x792c, (q15_t)0xd6c2, + (q15_t)0x792a, (q15_t)0xd6bc, (q15_t)0x7928, (q15_t)0xd6b6, (q15_t)0x7926, (q15_t)0xd6b0, (q15_t)0x7924, (q15_t)0xd6aa, + (q15_t)0x7922, (q15_t)0xd6a4, (q15_t)0x7920, (q15_t)0xd69e, (q15_t)0x791e, (q15_t)0xd698, (q15_t)0x791c, (q15_t)0xd692, + (q15_t)0x7919, (q15_t)0xd68c, (q15_t)0x7917, (q15_t)0xd686, (q15_t)0x7915, (q15_t)0xd680, (q15_t)0x7913, (q15_t)0xd67a, + (q15_t)0x7911, (q15_t)0xd675, (q15_t)0x790f, (q15_t)0xd66f, (q15_t)0x790d, (q15_t)0xd669, (q15_t)0x790b, (q15_t)0xd663, + (q15_t)0x7909, (q15_t)0xd65d, (q15_t)0x7907, (q15_t)0xd657, (q15_t)0x7905, (q15_t)0xd651, (q15_t)0x7903, (q15_t)0xd64b, + (q15_t)0x7901, (q15_t)0xd645, (q15_t)0x78ff, (q15_t)0xd63f, (q15_t)0x78fd, (q15_t)0xd639, (q15_t)0x78fb, (q15_t)0xd633, + (q15_t)0x78f9, (q15_t)0xd62d, (q15_t)0x78f7, (q15_t)0xd627, (q15_t)0x78f5, (q15_t)0xd621, (q15_t)0x78f3, (q15_t)0xd61b, + (q15_t)0x78f1, (q15_t)0xd615, (q15_t)0x78ee, (q15_t)0xd610, (q15_t)0x78ec, (q15_t)0xd60a, (q15_t)0x78ea, (q15_t)0xd604, + (q15_t)0x78e8, (q15_t)0xd5fe, (q15_t)0x78e6, (q15_t)0xd5f8, (q15_t)0x78e4, (q15_t)0xd5f2, (q15_t)0x78e2, (q15_t)0xd5ec, + (q15_t)0x78e0, (q15_t)0xd5e6, (q15_t)0x78de, (q15_t)0xd5e0, (q15_t)0x78dc, (q15_t)0xd5da, (q15_t)0x78da, (q15_t)0xd5d4, + (q15_t)0x78d8, (q15_t)0xd5ce, (q15_t)0x78d6, (q15_t)0xd5c8, (q15_t)0x78d4, (q15_t)0xd5c2, (q15_t)0x78d2, (q15_t)0xd5bc, + (q15_t)0x78cf, (q15_t)0xd5b7, (q15_t)0x78cd, (q15_t)0xd5b1, (q15_t)0x78cb, (q15_t)0xd5ab, (q15_t)0x78c9, (q15_t)0xd5a5, + (q15_t)0x78c7, (q15_t)0xd59f, (q15_t)0x78c5, (q15_t)0xd599, (q15_t)0x78c3, (q15_t)0xd593, (q15_t)0x78c1, (q15_t)0xd58d, + (q15_t)0x78bf, (q15_t)0xd587, (q15_t)0x78bd, (q15_t)0xd581, (q15_t)0x78bb, (q15_t)0xd57b, (q15_t)0x78b9, (q15_t)0xd575, + (q15_t)0x78b6, (q15_t)0xd56f, (q15_t)0x78b4, (q15_t)0xd569, (q15_t)0x78b2, (q15_t)0xd564, (q15_t)0x78b0, (q15_t)0xd55e, + (q15_t)0x78ae, (q15_t)0xd558, (q15_t)0x78ac, (q15_t)0xd552, (q15_t)0x78aa, (q15_t)0xd54c, (q15_t)0x78a8, (q15_t)0xd546, + (q15_t)0x78a6, (q15_t)0xd540, (q15_t)0x78a4, (q15_t)0xd53a, (q15_t)0x78a2, (q15_t)0xd534, (q15_t)0x789f, (q15_t)0xd52e, + (q15_t)0x789d, (q15_t)0xd528, (q15_t)0x789b, (q15_t)0xd522, (q15_t)0x7899, (q15_t)0xd51c, (q15_t)0x7897, (q15_t)0xd517, + (q15_t)0x7895, (q15_t)0xd511, (q15_t)0x7893, (q15_t)0xd50b, (q15_t)0x7891, (q15_t)0xd505, (q15_t)0x788f, (q15_t)0xd4ff, + (q15_t)0x788c, (q15_t)0xd4f9, (q15_t)0x788a, (q15_t)0xd4f3, (q15_t)0x7888, (q15_t)0xd4ed, (q15_t)0x7886, (q15_t)0xd4e7, + (q15_t)0x7884, (q15_t)0xd4e1, (q15_t)0x7882, (q15_t)0xd4db, (q15_t)0x7880, (q15_t)0xd4d5, (q15_t)0x787e, (q15_t)0xd4d0, + (q15_t)0x787c, (q15_t)0xd4ca, (q15_t)0x7879, (q15_t)0xd4c4, (q15_t)0x7877, (q15_t)0xd4be, (q15_t)0x7875, (q15_t)0xd4b8, + (q15_t)0x7873, (q15_t)0xd4b2, (q15_t)0x7871, (q15_t)0xd4ac, (q15_t)0x786f, (q15_t)0xd4a6, (q15_t)0x786d, (q15_t)0xd4a0, + (q15_t)0x786b, (q15_t)0xd49a, (q15_t)0x7868, (q15_t)0xd494, (q15_t)0x7866, (q15_t)0xd48f, (q15_t)0x7864, (q15_t)0xd489, + (q15_t)0x7862, (q15_t)0xd483, (q15_t)0x7860, (q15_t)0xd47d, (q15_t)0x785e, (q15_t)0xd477, (q15_t)0x785c, (q15_t)0xd471, + (q15_t)0x7859, (q15_t)0xd46b, (q15_t)0x7857, (q15_t)0xd465, (q15_t)0x7855, (q15_t)0xd45f, (q15_t)0x7853, (q15_t)0xd459, + (q15_t)0x7851, (q15_t)0xd453, (q15_t)0x784f, (q15_t)0xd44e, (q15_t)0x784d, (q15_t)0xd448, (q15_t)0x784a, (q15_t)0xd442, + (q15_t)0x7848, (q15_t)0xd43c, (q15_t)0x7846, (q15_t)0xd436, (q15_t)0x7844, (q15_t)0xd430, (q15_t)0x7842, (q15_t)0xd42a, + (q15_t)0x7840, (q15_t)0xd424, (q15_t)0x783e, (q15_t)0xd41e, (q15_t)0x783b, (q15_t)0xd418, (q15_t)0x7839, (q15_t)0xd412, + (q15_t)0x7837, (q15_t)0xd40d, (q15_t)0x7835, (q15_t)0xd407, (q15_t)0x7833, (q15_t)0xd401, (q15_t)0x7831, (q15_t)0xd3fb, + (q15_t)0x782e, (q15_t)0xd3f5, (q15_t)0x782c, (q15_t)0xd3ef, (q15_t)0x782a, (q15_t)0xd3e9, (q15_t)0x7828, (q15_t)0xd3e3, + (q15_t)0x7826, (q15_t)0xd3dd, (q15_t)0x7824, (q15_t)0xd3d7, (q15_t)0x7821, (q15_t)0xd3d2, (q15_t)0x781f, (q15_t)0xd3cc, + (q15_t)0x781d, (q15_t)0xd3c6, (q15_t)0x781b, (q15_t)0xd3c0, (q15_t)0x7819, (q15_t)0xd3ba, (q15_t)0x7817, (q15_t)0xd3b4, + (q15_t)0x7814, (q15_t)0xd3ae, (q15_t)0x7812, (q15_t)0xd3a8, (q15_t)0x7810, (q15_t)0xd3a2, (q15_t)0x780e, (q15_t)0xd39d, + (q15_t)0x780c, (q15_t)0xd397, (q15_t)0x780a, (q15_t)0xd391, (q15_t)0x7807, (q15_t)0xd38b, (q15_t)0x7805, (q15_t)0xd385, + (q15_t)0x7803, (q15_t)0xd37f, (q15_t)0x7801, (q15_t)0xd379, (q15_t)0x77ff, (q15_t)0xd373, (q15_t)0x77fc, (q15_t)0xd36d, + (q15_t)0x77fa, (q15_t)0xd368, (q15_t)0x77f8, (q15_t)0xd362, (q15_t)0x77f6, (q15_t)0xd35c, (q15_t)0x77f4, (q15_t)0xd356, + (q15_t)0x77f1, (q15_t)0xd350, (q15_t)0x77ef, (q15_t)0xd34a, (q15_t)0x77ed, (q15_t)0xd344, (q15_t)0x77eb, (q15_t)0xd33e, + (q15_t)0x77e9, (q15_t)0xd338, (q15_t)0x77e6, (q15_t)0xd333, (q15_t)0x77e4, (q15_t)0xd32d, (q15_t)0x77e2, (q15_t)0xd327, + (q15_t)0x77e0, (q15_t)0xd321, (q15_t)0x77de, (q15_t)0xd31b, (q15_t)0x77db, (q15_t)0xd315, (q15_t)0x77d9, (q15_t)0xd30f, + (q15_t)0x77d7, (q15_t)0xd309, (q15_t)0x77d5, (q15_t)0xd303, (q15_t)0x77d3, (q15_t)0xd2fe, (q15_t)0x77d0, (q15_t)0xd2f8, + (q15_t)0x77ce, (q15_t)0xd2f2, (q15_t)0x77cc, (q15_t)0xd2ec, (q15_t)0x77ca, (q15_t)0xd2e6, (q15_t)0x77c8, (q15_t)0xd2e0, + (q15_t)0x77c5, (q15_t)0xd2da, (q15_t)0x77c3, (q15_t)0xd2d4, (q15_t)0x77c1, (q15_t)0xd2cf, (q15_t)0x77bf, (q15_t)0xd2c9, + (q15_t)0x77bc, (q15_t)0xd2c3, (q15_t)0x77ba, (q15_t)0xd2bd, (q15_t)0x77b8, (q15_t)0xd2b7, (q15_t)0x77b6, (q15_t)0xd2b1, + (q15_t)0x77b4, (q15_t)0xd2ab, (q15_t)0x77b1, (q15_t)0xd2a5, (q15_t)0x77af, (q15_t)0xd2a0, (q15_t)0x77ad, (q15_t)0xd29a, + (q15_t)0x77ab, (q15_t)0xd294, (q15_t)0x77a8, (q15_t)0xd28e, (q15_t)0x77a6, (q15_t)0xd288, (q15_t)0x77a4, (q15_t)0xd282, + (q15_t)0x77a2, (q15_t)0xd27c, (q15_t)0x77a0, (q15_t)0xd276, (q15_t)0x779d, (q15_t)0xd271, (q15_t)0x779b, (q15_t)0xd26b, + (q15_t)0x7799, (q15_t)0xd265, (q15_t)0x7797, (q15_t)0xd25f, (q15_t)0x7794, (q15_t)0xd259, (q15_t)0x7792, (q15_t)0xd253, + (q15_t)0x7790, (q15_t)0xd24d, (q15_t)0x778e, (q15_t)0xd247, (q15_t)0x778b, (q15_t)0xd242, (q15_t)0x7789, (q15_t)0xd23c, + (q15_t)0x7787, (q15_t)0xd236, (q15_t)0x7785, (q15_t)0xd230, (q15_t)0x7782, (q15_t)0xd22a, (q15_t)0x7780, (q15_t)0xd224, + (q15_t)0x777e, (q15_t)0xd21e, (q15_t)0x777c, (q15_t)0xd219, (q15_t)0x7779, (q15_t)0xd213, (q15_t)0x7777, (q15_t)0xd20d, + (q15_t)0x7775, (q15_t)0xd207, (q15_t)0x7773, (q15_t)0xd201, (q15_t)0x7770, (q15_t)0xd1fb, (q15_t)0x776e, (q15_t)0xd1f5, + (q15_t)0x776c, (q15_t)0xd1ef, (q15_t)0x776a, (q15_t)0xd1ea, (q15_t)0x7767, (q15_t)0xd1e4, (q15_t)0x7765, (q15_t)0xd1de, + (q15_t)0x7763, (q15_t)0xd1d8, (q15_t)0x7760, (q15_t)0xd1d2, (q15_t)0x775e, (q15_t)0xd1cc, (q15_t)0x775c, (q15_t)0xd1c6, + (q15_t)0x775a, (q15_t)0xd1c1, (q15_t)0x7757, (q15_t)0xd1bb, (q15_t)0x7755, (q15_t)0xd1b5, (q15_t)0x7753, (q15_t)0xd1af, + (q15_t)0x7751, (q15_t)0xd1a9, (q15_t)0x774e, (q15_t)0xd1a3, (q15_t)0x774c, (q15_t)0xd19d, (q15_t)0x774a, (q15_t)0xd198, + (q15_t)0x7747, (q15_t)0xd192, (q15_t)0x7745, (q15_t)0xd18c, (q15_t)0x7743, (q15_t)0xd186, (q15_t)0x7741, (q15_t)0xd180, + (q15_t)0x773e, (q15_t)0xd17a, (q15_t)0x773c, (q15_t)0xd174, (q15_t)0x773a, (q15_t)0xd16f, (q15_t)0x7738, (q15_t)0xd169, + (q15_t)0x7735, (q15_t)0xd163, (q15_t)0x7733, (q15_t)0xd15d, (q15_t)0x7731, (q15_t)0xd157, (q15_t)0x772e, (q15_t)0xd151, + (q15_t)0x772c, (q15_t)0xd14b, (q15_t)0x772a, (q15_t)0xd146, (q15_t)0x7727, (q15_t)0xd140, (q15_t)0x7725, (q15_t)0xd13a, + (q15_t)0x7723, (q15_t)0xd134, (q15_t)0x7721, (q15_t)0xd12e, (q15_t)0x771e, (q15_t)0xd128, (q15_t)0x771c, (q15_t)0xd123, + (q15_t)0x771a, (q15_t)0xd11d, (q15_t)0x7717, (q15_t)0xd117, (q15_t)0x7715, (q15_t)0xd111, (q15_t)0x7713, (q15_t)0xd10b, + (q15_t)0x7710, (q15_t)0xd105, (q15_t)0x770e, (q15_t)0xd0ff, (q15_t)0x770c, (q15_t)0xd0fa, (q15_t)0x770a, (q15_t)0xd0f4, + (q15_t)0x7707, (q15_t)0xd0ee, (q15_t)0x7705, (q15_t)0xd0e8, (q15_t)0x7703, (q15_t)0xd0e2, (q15_t)0x7700, (q15_t)0xd0dc, + (q15_t)0x76fe, (q15_t)0xd0d7, (q15_t)0x76fc, (q15_t)0xd0d1, (q15_t)0x76f9, (q15_t)0xd0cb, (q15_t)0x76f7, (q15_t)0xd0c5, + (q15_t)0x76f5, (q15_t)0xd0bf, (q15_t)0x76f2, (q15_t)0xd0b9, (q15_t)0x76f0, (q15_t)0xd0b4, (q15_t)0x76ee, (q15_t)0xd0ae, + (q15_t)0x76eb, (q15_t)0xd0a8, (q15_t)0x76e9, (q15_t)0xd0a2, (q15_t)0x76e7, (q15_t)0xd09c, (q15_t)0x76e4, (q15_t)0xd096, + (q15_t)0x76e2, (q15_t)0xd091, (q15_t)0x76e0, (q15_t)0xd08b, (q15_t)0x76dd, (q15_t)0xd085, (q15_t)0x76db, (q15_t)0xd07f, + (q15_t)0x76d9, (q15_t)0xd079, (q15_t)0x76d6, (q15_t)0xd073, (q15_t)0x76d4, (q15_t)0xd06e, (q15_t)0x76d2, (q15_t)0xd068, + (q15_t)0x76cf, (q15_t)0xd062, (q15_t)0x76cd, (q15_t)0xd05c, (q15_t)0x76cb, (q15_t)0xd056, (q15_t)0x76c8, (q15_t)0xd050, + (q15_t)0x76c6, (q15_t)0xd04b, (q15_t)0x76c4, (q15_t)0xd045, (q15_t)0x76c1, (q15_t)0xd03f, (q15_t)0x76bf, (q15_t)0xd039, + (q15_t)0x76bd, (q15_t)0xd033, (q15_t)0x76ba, (q15_t)0xd02d, (q15_t)0x76b8, (q15_t)0xd028, (q15_t)0x76b6, (q15_t)0xd022, + (q15_t)0x76b3, (q15_t)0xd01c, (q15_t)0x76b1, (q15_t)0xd016, (q15_t)0x76af, (q15_t)0xd010, (q15_t)0x76ac, (q15_t)0xd00a, + (q15_t)0x76aa, (q15_t)0xd005, (q15_t)0x76a8, (q15_t)0xcfff, (q15_t)0x76a5, (q15_t)0xcff9, (q15_t)0x76a3, (q15_t)0xcff3, + (q15_t)0x76a0, (q15_t)0xcfed, (q15_t)0x769e, (q15_t)0xcfe7, (q15_t)0x769c, (q15_t)0xcfe2, (q15_t)0x7699, (q15_t)0xcfdc, + (q15_t)0x7697, (q15_t)0xcfd6, (q15_t)0x7695, (q15_t)0xcfd0, (q15_t)0x7692, (q15_t)0xcfca, (q15_t)0x7690, (q15_t)0xcfc5, + (q15_t)0x768e, (q15_t)0xcfbf, (q15_t)0x768b, (q15_t)0xcfb9, (q15_t)0x7689, (q15_t)0xcfb3, (q15_t)0x7686, (q15_t)0xcfad, + (q15_t)0x7684, (q15_t)0xcfa7, (q15_t)0x7682, (q15_t)0xcfa2, (q15_t)0x767f, (q15_t)0xcf9c, (q15_t)0x767d, (q15_t)0xcf96, + (q15_t)0x767b, (q15_t)0xcf90, (q15_t)0x7678, (q15_t)0xcf8a, (q15_t)0x7676, (q15_t)0xcf85, (q15_t)0x7673, (q15_t)0xcf7f, + (q15_t)0x7671, (q15_t)0xcf79, (q15_t)0x766f, (q15_t)0xcf73, (q15_t)0x766c, (q15_t)0xcf6d, (q15_t)0x766a, (q15_t)0xcf67, + (q15_t)0x7668, (q15_t)0xcf62, (q15_t)0x7665, (q15_t)0xcf5c, (q15_t)0x7663, (q15_t)0xcf56, (q15_t)0x7660, (q15_t)0xcf50, + (q15_t)0x765e, (q15_t)0xcf4a, (q15_t)0x765c, (q15_t)0xcf45, (q15_t)0x7659, (q15_t)0xcf3f, (q15_t)0x7657, (q15_t)0xcf39, + (q15_t)0x7654, (q15_t)0xcf33, (q15_t)0x7652, (q15_t)0xcf2d, (q15_t)0x7650, (q15_t)0xcf28, (q15_t)0x764d, (q15_t)0xcf22, + (q15_t)0x764b, (q15_t)0xcf1c, (q15_t)0x7648, (q15_t)0xcf16, (q15_t)0x7646, (q15_t)0xcf10, (q15_t)0x7644, (q15_t)0xcf0b, + (q15_t)0x7641, (q15_t)0xcf05, (q15_t)0x763f, (q15_t)0xceff, (q15_t)0x763c, (q15_t)0xcef9, (q15_t)0x763a, (q15_t)0xcef3, + (q15_t)0x7638, (q15_t)0xceee, (q15_t)0x7635, (q15_t)0xcee8, (q15_t)0x7633, (q15_t)0xcee2, (q15_t)0x7630, (q15_t)0xcedc, + (q15_t)0x762e, (q15_t)0xced6, (q15_t)0x762b, (q15_t)0xced1, (q15_t)0x7629, (q15_t)0xcecb, (q15_t)0x7627, (q15_t)0xcec5, + (q15_t)0x7624, (q15_t)0xcebf, (q15_t)0x7622, (q15_t)0xceb9, (q15_t)0x761f, (q15_t)0xceb4, (q15_t)0x761d, (q15_t)0xceae, + (q15_t)0x761b, (q15_t)0xcea8, (q15_t)0x7618, (q15_t)0xcea2, (q15_t)0x7616, (q15_t)0xce9c, (q15_t)0x7613, (q15_t)0xce97, + (q15_t)0x7611, (q15_t)0xce91, (q15_t)0x760e, (q15_t)0xce8b, (q15_t)0x760c, (q15_t)0xce85, (q15_t)0x760a, (q15_t)0xce7f, + (q15_t)0x7607, (q15_t)0xce7a, (q15_t)0x7605, (q15_t)0xce74, (q15_t)0x7602, (q15_t)0xce6e, (q15_t)0x7600, (q15_t)0xce68, + (q15_t)0x75fd, (q15_t)0xce62, (q15_t)0x75fb, (q15_t)0xce5d, (q15_t)0x75f9, (q15_t)0xce57, (q15_t)0x75f6, (q15_t)0xce51, + (q15_t)0x75f4, (q15_t)0xce4b, (q15_t)0x75f1, (q15_t)0xce45, (q15_t)0x75ef, (q15_t)0xce40, (q15_t)0x75ec, (q15_t)0xce3a, + (q15_t)0x75ea, (q15_t)0xce34, (q15_t)0x75e7, (q15_t)0xce2e, (q15_t)0x75e5, (q15_t)0xce28, (q15_t)0x75e3, (q15_t)0xce23, + (q15_t)0x75e0, (q15_t)0xce1d, (q15_t)0x75de, (q15_t)0xce17, (q15_t)0x75db, (q15_t)0xce11, (q15_t)0x75d9, (q15_t)0xce0c, + (q15_t)0x75d6, (q15_t)0xce06, (q15_t)0x75d4, (q15_t)0xce00, (q15_t)0x75d1, (q15_t)0xcdfa, (q15_t)0x75cf, (q15_t)0xcdf4, + (q15_t)0x75cc, (q15_t)0xcdef, (q15_t)0x75ca, (q15_t)0xcde9, (q15_t)0x75c8, (q15_t)0xcde3, (q15_t)0x75c5, (q15_t)0xcddd, + (q15_t)0x75c3, (q15_t)0xcdd8, (q15_t)0x75c0, (q15_t)0xcdd2, (q15_t)0x75be, (q15_t)0xcdcc, (q15_t)0x75bb, (q15_t)0xcdc6, + (q15_t)0x75b9, (q15_t)0xcdc0, (q15_t)0x75b6, (q15_t)0xcdbb, (q15_t)0x75b4, (q15_t)0xcdb5, (q15_t)0x75b1, (q15_t)0xcdaf, + (q15_t)0x75af, (q15_t)0xcda9, (q15_t)0x75ac, (q15_t)0xcda3, (q15_t)0x75aa, (q15_t)0xcd9e, (q15_t)0x75a7, (q15_t)0xcd98, + (q15_t)0x75a5, (q15_t)0xcd92, (q15_t)0x75a3, (q15_t)0xcd8c, (q15_t)0x75a0, (q15_t)0xcd87, (q15_t)0x759e, (q15_t)0xcd81, + (q15_t)0x759b, (q15_t)0xcd7b, (q15_t)0x7599, (q15_t)0xcd75, (q15_t)0x7596, (q15_t)0xcd70, (q15_t)0x7594, (q15_t)0xcd6a, + (q15_t)0x7591, (q15_t)0xcd64, (q15_t)0x758f, (q15_t)0xcd5e, (q15_t)0x758c, (q15_t)0xcd58, (q15_t)0x758a, (q15_t)0xcd53, + (q15_t)0x7587, (q15_t)0xcd4d, (q15_t)0x7585, (q15_t)0xcd47, (q15_t)0x7582, (q15_t)0xcd41, (q15_t)0x7580, (q15_t)0xcd3c, + (q15_t)0x757d, (q15_t)0xcd36, (q15_t)0x757b, (q15_t)0xcd30, (q15_t)0x7578, (q15_t)0xcd2a, (q15_t)0x7576, (q15_t)0xcd25, + (q15_t)0x7573, (q15_t)0xcd1f, (q15_t)0x7571, (q15_t)0xcd19, (q15_t)0x756e, (q15_t)0xcd13, (q15_t)0x756c, (q15_t)0xcd0d, + (q15_t)0x7569, (q15_t)0xcd08, (q15_t)0x7567, (q15_t)0xcd02, (q15_t)0x7564, (q15_t)0xccfc, (q15_t)0x7562, (q15_t)0xccf6, + (q15_t)0x755f, (q15_t)0xccf1, (q15_t)0x755d, (q15_t)0xcceb, (q15_t)0x755a, (q15_t)0xcce5, (q15_t)0x7558, (q15_t)0xccdf, + (q15_t)0x7555, (q15_t)0xccda, (q15_t)0x7553, (q15_t)0xccd4, (q15_t)0x7550, (q15_t)0xccce, (q15_t)0x754e, (q15_t)0xccc8, + (q15_t)0x754b, (q15_t)0xccc3, (q15_t)0x7549, (q15_t)0xccbd, (q15_t)0x7546, (q15_t)0xccb7, (q15_t)0x7544, (q15_t)0xccb1, + (q15_t)0x7541, (q15_t)0xccac, (q15_t)0x753f, (q15_t)0xcca6, (q15_t)0x753c, (q15_t)0xcca0, (q15_t)0x753a, (q15_t)0xcc9a, + (q15_t)0x7537, (q15_t)0xcc95, (q15_t)0x7535, (q15_t)0xcc8f, (q15_t)0x7532, (q15_t)0xcc89, (q15_t)0x752f, (q15_t)0xcc83, + (q15_t)0x752d, (q15_t)0xcc7e, (q15_t)0x752a, (q15_t)0xcc78, (q15_t)0x7528, (q15_t)0xcc72, (q15_t)0x7525, (q15_t)0xcc6c, + (q15_t)0x7523, (q15_t)0xcc67, (q15_t)0x7520, (q15_t)0xcc61, (q15_t)0x751e, (q15_t)0xcc5b, (q15_t)0x751b, (q15_t)0xcc55, + (q15_t)0x7519, (q15_t)0xcc50, (q15_t)0x7516, (q15_t)0xcc4a, (q15_t)0x7514, (q15_t)0xcc44, (q15_t)0x7511, (q15_t)0xcc3e, + (q15_t)0x750f, (q15_t)0xcc39, (q15_t)0x750c, (q15_t)0xcc33, (q15_t)0x7509, (q15_t)0xcc2d, (q15_t)0x7507, (q15_t)0xcc27, + (q15_t)0x7504, (q15_t)0xcc22, (q15_t)0x7502, (q15_t)0xcc1c, (q15_t)0x74ff, (q15_t)0xcc16, (q15_t)0x74fd, (q15_t)0xcc10, + (q15_t)0x74fa, (q15_t)0xcc0b, (q15_t)0x74f8, (q15_t)0xcc05, (q15_t)0x74f5, (q15_t)0xcbff, (q15_t)0x74f2, (q15_t)0xcbf9, + (q15_t)0x74f0, (q15_t)0xcbf4, (q15_t)0x74ed, (q15_t)0xcbee, (q15_t)0x74eb, (q15_t)0xcbe8, (q15_t)0x74e8, (q15_t)0xcbe2, + (q15_t)0x74e6, (q15_t)0xcbdd, (q15_t)0x74e3, (q15_t)0xcbd7, (q15_t)0x74e1, (q15_t)0xcbd1, (q15_t)0x74de, (q15_t)0xcbcb, + (q15_t)0x74db, (q15_t)0xcbc6, (q15_t)0x74d9, (q15_t)0xcbc0, (q15_t)0x74d6, (q15_t)0xcbba, (q15_t)0x74d4, (q15_t)0xcbb5, + (q15_t)0x74d1, (q15_t)0xcbaf, (q15_t)0x74cf, (q15_t)0xcba9, (q15_t)0x74cc, (q15_t)0xcba3, (q15_t)0x74c9, (q15_t)0xcb9e, + (q15_t)0x74c7, (q15_t)0xcb98, (q15_t)0x74c4, (q15_t)0xcb92, (q15_t)0x74c2, (q15_t)0xcb8c, (q15_t)0x74bf, (q15_t)0xcb87, + (q15_t)0x74bd, (q15_t)0xcb81, (q15_t)0x74ba, (q15_t)0xcb7b, (q15_t)0x74b7, (q15_t)0xcb75, (q15_t)0x74b5, (q15_t)0xcb70, + (q15_t)0x74b2, (q15_t)0xcb6a, (q15_t)0x74b0, (q15_t)0xcb64, (q15_t)0x74ad, (q15_t)0xcb5f, (q15_t)0x74ab, (q15_t)0xcb59, + (q15_t)0x74a8, (q15_t)0xcb53, (q15_t)0x74a5, (q15_t)0xcb4d, (q15_t)0x74a3, (q15_t)0xcb48, (q15_t)0x74a0, (q15_t)0xcb42, + (q15_t)0x749e, (q15_t)0xcb3c, (q15_t)0x749b, (q15_t)0xcb36, (q15_t)0x7498, (q15_t)0xcb31, (q15_t)0x7496, (q15_t)0xcb2b, + (q15_t)0x7493, (q15_t)0xcb25, (q15_t)0x7491, (q15_t)0xcb20, (q15_t)0x748e, (q15_t)0xcb1a, (q15_t)0x748b, (q15_t)0xcb14, + (q15_t)0x7489, (q15_t)0xcb0e, (q15_t)0x7486, (q15_t)0xcb09, (q15_t)0x7484, (q15_t)0xcb03, (q15_t)0x7481, (q15_t)0xcafd, + (q15_t)0x747e, (q15_t)0xcaf8, (q15_t)0x747c, (q15_t)0xcaf2, (q15_t)0x7479, (q15_t)0xcaec, (q15_t)0x7477, (q15_t)0xcae6, + (q15_t)0x7474, (q15_t)0xcae1, (q15_t)0x7471, (q15_t)0xcadb, (q15_t)0x746f, (q15_t)0xcad5, (q15_t)0x746c, (q15_t)0xcad0, + (q15_t)0x746a, (q15_t)0xcaca, (q15_t)0x7467, (q15_t)0xcac4, (q15_t)0x7464, (q15_t)0xcabe, (q15_t)0x7462, (q15_t)0xcab9, + (q15_t)0x745f, (q15_t)0xcab3, (q15_t)0x745c, (q15_t)0xcaad, (q15_t)0x745a, (q15_t)0xcaa8, (q15_t)0x7457, (q15_t)0xcaa2, + (q15_t)0x7455, (q15_t)0xca9c, (q15_t)0x7452, (q15_t)0xca96, (q15_t)0x744f, (q15_t)0xca91, (q15_t)0x744d, (q15_t)0xca8b, + (q15_t)0x744a, (q15_t)0xca85, (q15_t)0x7448, (q15_t)0xca80, (q15_t)0x7445, (q15_t)0xca7a, (q15_t)0x7442, (q15_t)0xca74, + (q15_t)0x7440, (q15_t)0xca6e, (q15_t)0x743d, (q15_t)0xca69, (q15_t)0x743a, (q15_t)0xca63, (q15_t)0x7438, (q15_t)0xca5d, + (q15_t)0x7435, (q15_t)0xca58, (q15_t)0x7432, (q15_t)0xca52, (q15_t)0x7430, (q15_t)0xca4c, (q15_t)0x742d, (q15_t)0xca46, + (q15_t)0x742b, (q15_t)0xca41, (q15_t)0x7428, (q15_t)0xca3b, (q15_t)0x7425, (q15_t)0xca35, (q15_t)0x7423, (q15_t)0xca30, + (q15_t)0x7420, (q15_t)0xca2a, (q15_t)0x741d, (q15_t)0xca24, (q15_t)0x741b, (q15_t)0xca1f, (q15_t)0x7418, (q15_t)0xca19, + (q15_t)0x7415, (q15_t)0xca13, (q15_t)0x7413, (q15_t)0xca0d, (q15_t)0x7410, (q15_t)0xca08, (q15_t)0x740d, (q15_t)0xca02, + (q15_t)0x740b, (q15_t)0xc9fc, (q15_t)0x7408, (q15_t)0xc9f7, (q15_t)0x7406, (q15_t)0xc9f1, (q15_t)0x7403, (q15_t)0xc9eb, + (q15_t)0x7400, (q15_t)0xc9e6, (q15_t)0x73fe, (q15_t)0xc9e0, (q15_t)0x73fb, (q15_t)0xc9da, (q15_t)0x73f8, (q15_t)0xc9d5, + (q15_t)0x73f6, (q15_t)0xc9cf, (q15_t)0x73f3, (q15_t)0xc9c9, (q15_t)0x73f0, (q15_t)0xc9c3, (q15_t)0x73ee, (q15_t)0xc9be, + (q15_t)0x73eb, (q15_t)0xc9b8, (q15_t)0x73e8, (q15_t)0xc9b2, (q15_t)0x73e6, (q15_t)0xc9ad, (q15_t)0x73e3, (q15_t)0xc9a7, + (q15_t)0x73e0, (q15_t)0xc9a1, (q15_t)0x73de, (q15_t)0xc99c, (q15_t)0x73db, (q15_t)0xc996, (q15_t)0x73d8, (q15_t)0xc990, + (q15_t)0x73d6, (q15_t)0xc98b, (q15_t)0x73d3, (q15_t)0xc985, (q15_t)0x73d0, (q15_t)0xc97f, (q15_t)0x73ce, (q15_t)0xc97a, + (q15_t)0x73cb, (q15_t)0xc974, (q15_t)0x73c8, (q15_t)0xc96e, (q15_t)0x73c6, (q15_t)0xc968, (q15_t)0x73c3, (q15_t)0xc963, + (q15_t)0x73c0, (q15_t)0xc95d, (q15_t)0x73bd, (q15_t)0xc957, (q15_t)0x73bb, (q15_t)0xc952, (q15_t)0x73b8, (q15_t)0xc94c, + (q15_t)0x73b5, (q15_t)0xc946, (q15_t)0x73b3, (q15_t)0xc941, (q15_t)0x73b0, (q15_t)0xc93b, (q15_t)0x73ad, (q15_t)0xc935, + (q15_t)0x73ab, (q15_t)0xc930, (q15_t)0x73a8, (q15_t)0xc92a, (q15_t)0x73a5, (q15_t)0xc924, (q15_t)0x73a3, (q15_t)0xc91f, + (q15_t)0x73a0, (q15_t)0xc919, (q15_t)0x739d, (q15_t)0xc913, (q15_t)0x739b, (q15_t)0xc90e, (q15_t)0x7398, (q15_t)0xc908, + (q15_t)0x7395, (q15_t)0xc902, (q15_t)0x7392, (q15_t)0xc8fd, (q15_t)0x7390, (q15_t)0xc8f7, (q15_t)0x738d, (q15_t)0xc8f1, + (q15_t)0x738a, (q15_t)0xc8ec, (q15_t)0x7388, (q15_t)0xc8e6, (q15_t)0x7385, (q15_t)0xc8e0, (q15_t)0x7382, (q15_t)0xc8db, + (q15_t)0x737f, (q15_t)0xc8d5, (q15_t)0x737d, (q15_t)0xc8cf, (q15_t)0x737a, (q15_t)0xc8ca, (q15_t)0x7377, (q15_t)0xc8c4, + (q15_t)0x7375, (q15_t)0xc8be, (q15_t)0x7372, (q15_t)0xc8b9, (q15_t)0x736f, (q15_t)0xc8b3, (q15_t)0x736c, (q15_t)0xc8ad, + (q15_t)0x736a, (q15_t)0xc8a8, (q15_t)0x7367, (q15_t)0xc8a2, (q15_t)0x7364, (q15_t)0xc89c, (q15_t)0x7362, (q15_t)0xc897, + (q15_t)0x735f, (q15_t)0xc891, (q15_t)0x735c, (q15_t)0xc88b, (q15_t)0x7359, (q15_t)0xc886, (q15_t)0x7357, (q15_t)0xc880, + (q15_t)0x7354, (q15_t)0xc87a, (q15_t)0x7351, (q15_t)0xc875, (q15_t)0x734f, (q15_t)0xc86f, (q15_t)0x734c, (q15_t)0xc869, + (q15_t)0x7349, (q15_t)0xc864, (q15_t)0x7346, (q15_t)0xc85e, (q15_t)0x7344, (q15_t)0xc858, (q15_t)0x7341, (q15_t)0xc853, + (q15_t)0x733e, (q15_t)0xc84d, (q15_t)0x733b, (q15_t)0xc847, (q15_t)0x7339, (q15_t)0xc842, (q15_t)0x7336, (q15_t)0xc83c, + (q15_t)0x7333, (q15_t)0xc836, (q15_t)0x7330, (q15_t)0xc831, (q15_t)0x732e, (q15_t)0xc82b, (q15_t)0x732b, (q15_t)0xc825, + (q15_t)0x7328, (q15_t)0xc820, (q15_t)0x7326, (q15_t)0xc81a, (q15_t)0x7323, (q15_t)0xc814, (q15_t)0x7320, (q15_t)0xc80f, + (q15_t)0x731d, (q15_t)0xc809, (q15_t)0x731b, (q15_t)0xc803, (q15_t)0x7318, (q15_t)0xc7fe, (q15_t)0x7315, (q15_t)0xc7f8, + (q15_t)0x7312, (q15_t)0xc7f3, (q15_t)0x7310, (q15_t)0xc7ed, (q15_t)0x730d, (q15_t)0xc7e7, (q15_t)0x730a, (q15_t)0xc7e2, + (q15_t)0x7307, (q15_t)0xc7dc, (q15_t)0x7305, (q15_t)0xc7d6, (q15_t)0x7302, (q15_t)0xc7d1, (q15_t)0x72ff, (q15_t)0xc7cb, + (q15_t)0x72fc, (q15_t)0xc7c5, (q15_t)0x72f9, (q15_t)0xc7c0, (q15_t)0x72f7, (q15_t)0xc7ba, (q15_t)0x72f4, (q15_t)0xc7b4, + (q15_t)0x72f1, (q15_t)0xc7af, (q15_t)0x72ee, (q15_t)0xc7a9, (q15_t)0x72ec, (q15_t)0xc7a3, (q15_t)0x72e9, (q15_t)0xc79e, + (q15_t)0x72e6, (q15_t)0xc798, (q15_t)0x72e3, (q15_t)0xc793, (q15_t)0x72e1, (q15_t)0xc78d, (q15_t)0x72de, (q15_t)0xc787, + (q15_t)0x72db, (q15_t)0xc782, (q15_t)0x72d8, (q15_t)0xc77c, (q15_t)0x72d5, (q15_t)0xc776, (q15_t)0x72d3, (q15_t)0xc771, + (q15_t)0x72d0, (q15_t)0xc76b, (q15_t)0x72cd, (q15_t)0xc765, (q15_t)0x72ca, (q15_t)0xc760, (q15_t)0x72c8, (q15_t)0xc75a, + (q15_t)0x72c5, (q15_t)0xc755, (q15_t)0x72c2, (q15_t)0xc74f, (q15_t)0x72bf, (q15_t)0xc749, (q15_t)0x72bc, (q15_t)0xc744, + (q15_t)0x72ba, (q15_t)0xc73e, (q15_t)0x72b7, (q15_t)0xc738, (q15_t)0x72b4, (q15_t)0xc733, (q15_t)0x72b1, (q15_t)0xc72d, + (q15_t)0x72af, (q15_t)0xc728, (q15_t)0x72ac, (q15_t)0xc722, (q15_t)0x72a9, (q15_t)0xc71c, (q15_t)0x72a6, (q15_t)0xc717, + (q15_t)0x72a3, (q15_t)0xc711, (q15_t)0x72a1, (q15_t)0xc70b, (q15_t)0x729e, (q15_t)0xc706, (q15_t)0x729b, (q15_t)0xc700, + (q15_t)0x7298, (q15_t)0xc6fa, (q15_t)0x7295, (q15_t)0xc6f5, (q15_t)0x7293, (q15_t)0xc6ef, (q15_t)0x7290, (q15_t)0xc6ea, + (q15_t)0x728d, (q15_t)0xc6e4, (q15_t)0x728a, (q15_t)0xc6de, (q15_t)0x7287, (q15_t)0xc6d9, (q15_t)0x7285, (q15_t)0xc6d3, + (q15_t)0x7282, (q15_t)0xc6ce, (q15_t)0x727f, (q15_t)0xc6c8, (q15_t)0x727c, (q15_t)0xc6c2, (q15_t)0x7279, (q15_t)0xc6bd, + (q15_t)0x7276, (q15_t)0xc6b7, (q15_t)0x7274, (q15_t)0xc6b1, (q15_t)0x7271, (q15_t)0xc6ac, (q15_t)0x726e, (q15_t)0xc6a6, + (q15_t)0x726b, (q15_t)0xc6a1, (q15_t)0x7268, (q15_t)0xc69b, (q15_t)0x7266, (q15_t)0xc695, (q15_t)0x7263, (q15_t)0xc690, + (q15_t)0x7260, (q15_t)0xc68a, (q15_t)0x725d, (q15_t)0xc684, (q15_t)0x725a, (q15_t)0xc67f, (q15_t)0x7257, (q15_t)0xc679, + (q15_t)0x7255, (q15_t)0xc674, (q15_t)0x7252, (q15_t)0xc66e, (q15_t)0x724f, (q15_t)0xc668, (q15_t)0x724c, (q15_t)0xc663, + (q15_t)0x7249, (q15_t)0xc65d, (q15_t)0x7247, (q15_t)0xc658, (q15_t)0x7244, (q15_t)0xc652, (q15_t)0x7241, (q15_t)0xc64c, + (q15_t)0x723e, (q15_t)0xc647, (q15_t)0x723b, (q15_t)0xc641, (q15_t)0x7238, (q15_t)0xc63c, (q15_t)0x7236, (q15_t)0xc636, + (q15_t)0x7233, (q15_t)0xc630, (q15_t)0x7230, (q15_t)0xc62b, (q15_t)0x722d, (q15_t)0xc625, (q15_t)0x722a, (q15_t)0xc620, + (q15_t)0x7227, (q15_t)0xc61a, (q15_t)0x7224, (q15_t)0xc614, (q15_t)0x7222, (q15_t)0xc60f, (q15_t)0x721f, (q15_t)0xc609, + (q15_t)0x721c, (q15_t)0xc603, (q15_t)0x7219, (q15_t)0xc5fe, (q15_t)0x7216, (q15_t)0xc5f8, (q15_t)0x7213, (q15_t)0xc5f3, + (q15_t)0x7211, (q15_t)0xc5ed, (q15_t)0x720e, (q15_t)0xc5e7, (q15_t)0x720b, (q15_t)0xc5e2, (q15_t)0x7208, (q15_t)0xc5dc, + (q15_t)0x7205, (q15_t)0xc5d7, (q15_t)0x7202, (q15_t)0xc5d1, (q15_t)0x71ff, (q15_t)0xc5cc, (q15_t)0x71fd, (q15_t)0xc5c6, + (q15_t)0x71fa, (q15_t)0xc5c0, (q15_t)0x71f7, (q15_t)0xc5bb, (q15_t)0x71f4, (q15_t)0xc5b5, (q15_t)0x71f1, (q15_t)0xc5b0, + (q15_t)0x71ee, (q15_t)0xc5aa, (q15_t)0x71eb, (q15_t)0xc5a4, (q15_t)0x71e9, (q15_t)0xc59f, (q15_t)0x71e6, (q15_t)0xc599, + (q15_t)0x71e3, (q15_t)0xc594, (q15_t)0x71e0, (q15_t)0xc58e, (q15_t)0x71dd, (q15_t)0xc588, (q15_t)0x71da, (q15_t)0xc583, + (q15_t)0x71d7, (q15_t)0xc57d, (q15_t)0x71d4, (q15_t)0xc578, (q15_t)0x71d2, (q15_t)0xc572, (q15_t)0x71cf, (q15_t)0xc56c, + (q15_t)0x71cc, (q15_t)0xc567, (q15_t)0x71c9, (q15_t)0xc561, (q15_t)0x71c6, (q15_t)0xc55c, (q15_t)0x71c3, (q15_t)0xc556, + (q15_t)0x71c0, (q15_t)0xc551, (q15_t)0x71bd, (q15_t)0xc54b, (q15_t)0x71bb, (q15_t)0xc545, (q15_t)0x71b8, (q15_t)0xc540, + (q15_t)0x71b5, (q15_t)0xc53a, (q15_t)0x71b2, (q15_t)0xc535, (q15_t)0x71af, (q15_t)0xc52f, (q15_t)0x71ac, (q15_t)0xc529, + (q15_t)0x71a9, (q15_t)0xc524, (q15_t)0x71a6, (q15_t)0xc51e, (q15_t)0x71a3, (q15_t)0xc519, (q15_t)0x71a1, (q15_t)0xc513, + (q15_t)0x719e, (q15_t)0xc50e, (q15_t)0x719b, (q15_t)0xc508, (q15_t)0x7198, (q15_t)0xc502, (q15_t)0x7195, (q15_t)0xc4fd, + (q15_t)0x7192, (q15_t)0xc4f7, (q15_t)0x718f, (q15_t)0xc4f2, (q15_t)0x718c, (q15_t)0xc4ec, (q15_t)0x7189, (q15_t)0xc4e7, + (q15_t)0x7186, (q15_t)0xc4e1, (q15_t)0x7184, (q15_t)0xc4db, (q15_t)0x7181, (q15_t)0xc4d6, (q15_t)0x717e, (q15_t)0xc4d0, + (q15_t)0x717b, (q15_t)0xc4cb, (q15_t)0x7178, (q15_t)0xc4c5, (q15_t)0x7175, (q15_t)0xc4c0, (q15_t)0x7172, (q15_t)0xc4ba, + (q15_t)0x716f, (q15_t)0xc4b4, (q15_t)0x716c, (q15_t)0xc4af, (q15_t)0x7169, (q15_t)0xc4a9, (q15_t)0x7167, (q15_t)0xc4a4, + (q15_t)0x7164, (q15_t)0xc49e, (q15_t)0x7161, (q15_t)0xc499, (q15_t)0x715e, (q15_t)0xc493, (q15_t)0x715b, (q15_t)0xc48d, + (q15_t)0x7158, (q15_t)0xc488, (q15_t)0x7155, (q15_t)0xc482, (q15_t)0x7152, (q15_t)0xc47d, (q15_t)0x714f, (q15_t)0xc477, + (q15_t)0x714c, (q15_t)0xc472, (q15_t)0x7149, (q15_t)0xc46c, (q15_t)0x7146, (q15_t)0xc467, (q15_t)0x7143, (q15_t)0xc461, + (q15_t)0x7141, (q15_t)0xc45b, (q15_t)0x713e, (q15_t)0xc456, (q15_t)0x713b, (q15_t)0xc450, (q15_t)0x7138, (q15_t)0xc44b, + (q15_t)0x7135, (q15_t)0xc445, (q15_t)0x7132, (q15_t)0xc440, (q15_t)0x712f, (q15_t)0xc43a, (q15_t)0x712c, (q15_t)0xc434, + (q15_t)0x7129, (q15_t)0xc42f, (q15_t)0x7126, (q15_t)0xc429, (q15_t)0x7123, (q15_t)0xc424, (q15_t)0x7120, (q15_t)0xc41e, + (q15_t)0x711d, (q15_t)0xc419, (q15_t)0x711a, (q15_t)0xc413, (q15_t)0x7117, (q15_t)0xc40e, (q15_t)0x7114, (q15_t)0xc408, + (q15_t)0x7112, (q15_t)0xc403, (q15_t)0x710f, (q15_t)0xc3fd, (q15_t)0x710c, (q15_t)0xc3f7, (q15_t)0x7109, (q15_t)0xc3f2, + (q15_t)0x7106, (q15_t)0xc3ec, (q15_t)0x7103, (q15_t)0xc3e7, (q15_t)0x7100, (q15_t)0xc3e1, (q15_t)0x70fd, (q15_t)0xc3dc, + (q15_t)0x70fa, (q15_t)0xc3d6, (q15_t)0x70f7, (q15_t)0xc3d1, (q15_t)0x70f4, (q15_t)0xc3cb, (q15_t)0x70f1, (q15_t)0xc3c5, + (q15_t)0x70ee, (q15_t)0xc3c0, (q15_t)0x70eb, (q15_t)0xc3ba, (q15_t)0x70e8, (q15_t)0xc3b5, (q15_t)0x70e5, (q15_t)0xc3af, + (q15_t)0x70e2, (q15_t)0xc3aa, (q15_t)0x70df, (q15_t)0xc3a4, (q15_t)0x70dc, (q15_t)0xc39f, (q15_t)0x70d9, (q15_t)0xc399, + (q15_t)0x70d6, (q15_t)0xc394, (q15_t)0x70d3, (q15_t)0xc38e, (q15_t)0x70d1, (q15_t)0xc389, (q15_t)0x70ce, (q15_t)0xc383, + (q15_t)0x70cb, (q15_t)0xc37d, (q15_t)0x70c8, (q15_t)0xc378, (q15_t)0x70c5, (q15_t)0xc372, (q15_t)0x70c2, (q15_t)0xc36d, + (q15_t)0x70bf, (q15_t)0xc367, (q15_t)0x70bc, (q15_t)0xc362, (q15_t)0x70b9, (q15_t)0xc35c, (q15_t)0x70b6, (q15_t)0xc357, + (q15_t)0x70b3, (q15_t)0xc351, (q15_t)0x70b0, (q15_t)0xc34c, (q15_t)0x70ad, (q15_t)0xc346, (q15_t)0x70aa, (q15_t)0xc341, + (q15_t)0x70a7, (q15_t)0xc33b, (q15_t)0x70a4, (q15_t)0xc336, (q15_t)0x70a1, (q15_t)0xc330, (q15_t)0x709e, (q15_t)0xc32a, + (q15_t)0x709b, (q15_t)0xc325, (q15_t)0x7098, (q15_t)0xc31f, (q15_t)0x7095, (q15_t)0xc31a, (q15_t)0x7092, (q15_t)0xc314, + (q15_t)0x708f, (q15_t)0xc30f, (q15_t)0x708c, (q15_t)0xc309, (q15_t)0x7089, (q15_t)0xc304, (q15_t)0x7086, (q15_t)0xc2fe, + (q15_t)0x7083, (q15_t)0xc2f9, (q15_t)0x7080, (q15_t)0xc2f3, (q15_t)0x707d, (q15_t)0xc2ee, (q15_t)0x707a, (q15_t)0xc2e8, + (q15_t)0x7077, (q15_t)0xc2e3, (q15_t)0x7074, (q15_t)0xc2dd, (q15_t)0x7071, (q15_t)0xc2d8, (q15_t)0x706e, (q15_t)0xc2d2, + (q15_t)0x706b, (q15_t)0xc2cd, (q15_t)0x7068, (q15_t)0xc2c7, (q15_t)0x7065, (q15_t)0xc2c2, (q15_t)0x7062, (q15_t)0xc2bc, + (q15_t)0x705f, (q15_t)0xc2b7, (q15_t)0x705c, (q15_t)0xc2b1, (q15_t)0x7059, (q15_t)0xc2ab, (q15_t)0x7056, (q15_t)0xc2a6, + (q15_t)0x7053, (q15_t)0xc2a0, (q15_t)0x7050, (q15_t)0xc29b, (q15_t)0x704d, (q15_t)0xc295, (q15_t)0x704a, (q15_t)0xc290, + (q15_t)0x7047, (q15_t)0xc28a, (q15_t)0x7044, (q15_t)0xc285, (q15_t)0x7041, (q15_t)0xc27f, (q15_t)0x703e, (q15_t)0xc27a, + (q15_t)0x703b, (q15_t)0xc274, (q15_t)0x7038, (q15_t)0xc26f, (q15_t)0x7035, (q15_t)0xc269, (q15_t)0x7032, (q15_t)0xc264, + (q15_t)0x702f, (q15_t)0xc25e, (q15_t)0x702c, (q15_t)0xc259, (q15_t)0x7029, (q15_t)0xc253, (q15_t)0x7026, (q15_t)0xc24e, + (q15_t)0x7023, (q15_t)0xc248, (q15_t)0x7020, (q15_t)0xc243, (q15_t)0x701d, (q15_t)0xc23d, (q15_t)0x7019, (q15_t)0xc238, + (q15_t)0x7016, (q15_t)0xc232, (q15_t)0x7013, (q15_t)0xc22d, (q15_t)0x7010, (q15_t)0xc227, (q15_t)0x700d, (q15_t)0xc222, + (q15_t)0x700a, (q15_t)0xc21c, (q15_t)0x7007, (q15_t)0xc217, (q15_t)0x7004, (q15_t)0xc211, (q15_t)0x7001, (q15_t)0xc20c, + (q15_t)0x6ffe, (q15_t)0xc206, (q15_t)0x6ffb, (q15_t)0xc201, (q15_t)0x6ff8, (q15_t)0xc1fb, (q15_t)0x6ff5, (q15_t)0xc1f6, + (q15_t)0x6ff2, (q15_t)0xc1f0, (q15_t)0x6fef, (q15_t)0xc1eb, (q15_t)0x6fec, (q15_t)0xc1e5, (q15_t)0x6fe9, (q15_t)0xc1e0, + (q15_t)0x6fe6, (q15_t)0xc1da, (q15_t)0x6fe3, (q15_t)0xc1d5, (q15_t)0x6fe0, (q15_t)0xc1cf, (q15_t)0x6fdd, (q15_t)0xc1ca, + (q15_t)0x6fda, (q15_t)0xc1c4, (q15_t)0x6fd6, (q15_t)0xc1bf, (q15_t)0x6fd3, (q15_t)0xc1b9, (q15_t)0x6fd0, (q15_t)0xc1b4, + (q15_t)0x6fcd, (q15_t)0xc1ae, (q15_t)0x6fca, (q15_t)0xc1a9, (q15_t)0x6fc7, (q15_t)0xc1a3, (q15_t)0x6fc4, (q15_t)0xc19e, + (q15_t)0x6fc1, (q15_t)0xc198, (q15_t)0x6fbe, (q15_t)0xc193, (q15_t)0x6fbb, (q15_t)0xc18d, (q15_t)0x6fb8, (q15_t)0xc188, + (q15_t)0x6fb5, (q15_t)0xc183, (q15_t)0x6fb2, (q15_t)0xc17d, (q15_t)0x6faf, (q15_t)0xc178, (q15_t)0x6fac, (q15_t)0xc172, + (q15_t)0x6fa9, (q15_t)0xc16d, (q15_t)0x6fa5, (q15_t)0xc167, (q15_t)0x6fa2, (q15_t)0xc162, (q15_t)0x6f9f, (q15_t)0xc15c, + (q15_t)0x6f9c, (q15_t)0xc157, (q15_t)0x6f99, (q15_t)0xc151, (q15_t)0x6f96, (q15_t)0xc14c, (q15_t)0x6f93, (q15_t)0xc146, + (q15_t)0x6f90, (q15_t)0xc141, (q15_t)0x6f8d, (q15_t)0xc13b, (q15_t)0x6f8a, (q15_t)0xc136, (q15_t)0x6f87, (q15_t)0xc130, + (q15_t)0x6f84, (q15_t)0xc12b, (q15_t)0x6f81, (q15_t)0xc125, (q15_t)0x6f7d, (q15_t)0xc120, (q15_t)0x6f7a, (q15_t)0xc11a, + (q15_t)0x6f77, (q15_t)0xc115, (q15_t)0x6f74, (q15_t)0xc10f, (q15_t)0x6f71, (q15_t)0xc10a, (q15_t)0x6f6e, (q15_t)0xc105, + (q15_t)0x6f6b, (q15_t)0xc0ff, (q15_t)0x6f68, (q15_t)0xc0fa, (q15_t)0x6f65, (q15_t)0xc0f4, (q15_t)0x6f62, (q15_t)0xc0ef, + (q15_t)0x6f5f, (q15_t)0xc0e9, (q15_t)0x6f5b, (q15_t)0xc0e4, (q15_t)0x6f58, (q15_t)0xc0de, (q15_t)0x6f55, (q15_t)0xc0d9, + (q15_t)0x6f52, (q15_t)0xc0d3, (q15_t)0x6f4f, (q15_t)0xc0ce, (q15_t)0x6f4c, (q15_t)0xc0c8, (q15_t)0x6f49, (q15_t)0xc0c3, + (q15_t)0x6f46, (q15_t)0xc0bd, (q15_t)0x6f43, (q15_t)0xc0b8, (q15_t)0x6f3f, (q15_t)0xc0b3, (q15_t)0x6f3c, (q15_t)0xc0ad, + (q15_t)0x6f39, (q15_t)0xc0a8, (q15_t)0x6f36, (q15_t)0xc0a2, (q15_t)0x6f33, (q15_t)0xc09d, (q15_t)0x6f30, (q15_t)0xc097, + (q15_t)0x6f2d, (q15_t)0xc092, (q15_t)0x6f2a, (q15_t)0xc08c, (q15_t)0x6f27, (q15_t)0xc087, (q15_t)0x6f23, (q15_t)0xc081, + (q15_t)0x6f20, (q15_t)0xc07c, (q15_t)0x6f1d, (q15_t)0xc077, (q15_t)0x6f1a, (q15_t)0xc071, (q15_t)0x6f17, (q15_t)0xc06c, + (q15_t)0x6f14, (q15_t)0xc066, (q15_t)0x6f11, (q15_t)0xc061, (q15_t)0x6f0e, (q15_t)0xc05b, (q15_t)0x6f0b, (q15_t)0xc056, + (q15_t)0x6f07, (q15_t)0xc050, (q15_t)0x6f04, (q15_t)0xc04b, (q15_t)0x6f01, (q15_t)0xc045, (q15_t)0x6efe, (q15_t)0xc040, + (q15_t)0x6efb, (q15_t)0xc03b, (q15_t)0x6ef8, (q15_t)0xc035, (q15_t)0x6ef5, (q15_t)0xc030, (q15_t)0x6ef1, (q15_t)0xc02a, + (q15_t)0x6eee, (q15_t)0xc025, (q15_t)0x6eeb, (q15_t)0xc01f, (q15_t)0x6ee8, (q15_t)0xc01a, (q15_t)0x6ee5, (q15_t)0xc014, + (q15_t)0x6ee2, (q15_t)0xc00f, (q15_t)0x6edf, (q15_t)0xc00a, (q15_t)0x6edc, (q15_t)0xc004, (q15_t)0x6ed8, (q15_t)0xbfff, + (q15_t)0x6ed5, (q15_t)0xbff9, (q15_t)0x6ed2, (q15_t)0xbff4, (q15_t)0x6ecf, (q15_t)0xbfee, (q15_t)0x6ecc, (q15_t)0xbfe9, + (q15_t)0x6ec9, (q15_t)0xbfe3, (q15_t)0x6ec6, (q15_t)0xbfde, (q15_t)0x6ec2, (q15_t)0xbfd9, (q15_t)0x6ebf, (q15_t)0xbfd3, + (q15_t)0x6ebc, (q15_t)0xbfce, (q15_t)0x6eb9, (q15_t)0xbfc8, (q15_t)0x6eb6, (q15_t)0xbfc3, (q15_t)0x6eb3, (q15_t)0xbfbd, + (q15_t)0x6eaf, (q15_t)0xbfb8, (q15_t)0x6eac, (q15_t)0xbfb3, (q15_t)0x6ea9, (q15_t)0xbfad, (q15_t)0x6ea6, (q15_t)0xbfa8, + (q15_t)0x6ea3, (q15_t)0xbfa2, (q15_t)0x6ea0, (q15_t)0xbf9d, (q15_t)0x6e9c, (q15_t)0xbf97, (q15_t)0x6e99, (q15_t)0xbf92, + (q15_t)0x6e96, (q15_t)0xbf8d, (q15_t)0x6e93, (q15_t)0xbf87, (q15_t)0x6e90, (q15_t)0xbf82, (q15_t)0x6e8d, (q15_t)0xbf7c, + (q15_t)0x6e89, (q15_t)0xbf77, (q15_t)0x6e86, (q15_t)0xbf71, (q15_t)0x6e83, (q15_t)0xbf6c, (q15_t)0x6e80, (q15_t)0xbf67, + (q15_t)0x6e7d, (q15_t)0xbf61, (q15_t)0x6e7a, (q15_t)0xbf5c, (q15_t)0x6e76, (q15_t)0xbf56, (q15_t)0x6e73, (q15_t)0xbf51, + (q15_t)0x6e70, (q15_t)0xbf4b, (q15_t)0x6e6d, (q15_t)0xbf46, (q15_t)0x6e6a, (q15_t)0xbf41, (q15_t)0x6e67, (q15_t)0xbf3b, + (q15_t)0x6e63, (q15_t)0xbf36, (q15_t)0x6e60, (q15_t)0xbf30, (q15_t)0x6e5d, (q15_t)0xbf2b, (q15_t)0x6e5a, (q15_t)0xbf26, + (q15_t)0x6e57, (q15_t)0xbf20, (q15_t)0x6e53, (q15_t)0xbf1b, (q15_t)0x6e50, (q15_t)0xbf15, (q15_t)0x6e4d, (q15_t)0xbf10, + (q15_t)0x6e4a, (q15_t)0xbf0a, (q15_t)0x6e47, (q15_t)0xbf05, (q15_t)0x6e44, (q15_t)0xbf00, (q15_t)0x6e40, (q15_t)0xbefa, + (q15_t)0x6e3d, (q15_t)0xbef5, (q15_t)0x6e3a, (q15_t)0xbeef, (q15_t)0x6e37, (q15_t)0xbeea, (q15_t)0x6e34, (q15_t)0xbee5, + (q15_t)0x6e30, (q15_t)0xbedf, (q15_t)0x6e2d, (q15_t)0xbeda, (q15_t)0x6e2a, (q15_t)0xbed4, (q15_t)0x6e27, (q15_t)0xbecf, + (q15_t)0x6e24, (q15_t)0xbeca, (q15_t)0x6e20, (q15_t)0xbec4, (q15_t)0x6e1d, (q15_t)0xbebf, (q15_t)0x6e1a, (q15_t)0xbeb9, + (q15_t)0x6e17, (q15_t)0xbeb4, (q15_t)0x6e14, (q15_t)0xbeae, (q15_t)0x6e10, (q15_t)0xbea9, (q15_t)0x6e0d, (q15_t)0xbea4, + (q15_t)0x6e0a, (q15_t)0xbe9e, (q15_t)0x6e07, (q15_t)0xbe99, (q15_t)0x6e04, (q15_t)0xbe93, (q15_t)0x6e00, (q15_t)0xbe8e, + (q15_t)0x6dfd, (q15_t)0xbe89, (q15_t)0x6dfa, (q15_t)0xbe83, (q15_t)0x6df7, (q15_t)0xbe7e, (q15_t)0x6df3, (q15_t)0xbe78, + (q15_t)0x6df0, (q15_t)0xbe73, (q15_t)0x6ded, (q15_t)0xbe6e, (q15_t)0x6dea, (q15_t)0xbe68, (q15_t)0x6de7, (q15_t)0xbe63, + (q15_t)0x6de3, (q15_t)0xbe5e, (q15_t)0x6de0, (q15_t)0xbe58, (q15_t)0x6ddd, (q15_t)0xbe53, (q15_t)0x6dda, (q15_t)0xbe4d, + (q15_t)0x6dd6, (q15_t)0xbe48, (q15_t)0x6dd3, (q15_t)0xbe43, (q15_t)0x6dd0, (q15_t)0xbe3d, (q15_t)0x6dcd, (q15_t)0xbe38, + (q15_t)0x6dca, (q15_t)0xbe32, (q15_t)0x6dc6, (q15_t)0xbe2d, (q15_t)0x6dc3, (q15_t)0xbe28, (q15_t)0x6dc0, (q15_t)0xbe22, + (q15_t)0x6dbd, (q15_t)0xbe1d, (q15_t)0x6db9, (q15_t)0xbe17, (q15_t)0x6db6, (q15_t)0xbe12, (q15_t)0x6db3, (q15_t)0xbe0d, + (q15_t)0x6db0, (q15_t)0xbe07, (q15_t)0x6dac, (q15_t)0xbe02, (q15_t)0x6da9, (q15_t)0xbdfd, (q15_t)0x6da6, (q15_t)0xbdf7, + (q15_t)0x6da3, (q15_t)0xbdf2, (q15_t)0x6d9f, (q15_t)0xbdec, (q15_t)0x6d9c, (q15_t)0xbde7, (q15_t)0x6d99, (q15_t)0xbde2, + (q15_t)0x6d96, (q15_t)0xbddc, (q15_t)0x6d92, (q15_t)0xbdd7, (q15_t)0x6d8f, (q15_t)0xbdd1, (q15_t)0x6d8c, (q15_t)0xbdcc, + (q15_t)0x6d89, (q15_t)0xbdc7, (q15_t)0x6d85, (q15_t)0xbdc1, (q15_t)0x6d82, (q15_t)0xbdbc, (q15_t)0x6d7f, (q15_t)0xbdb7, + (q15_t)0x6d7c, (q15_t)0xbdb1, (q15_t)0x6d78, (q15_t)0xbdac, (q15_t)0x6d75, (q15_t)0xbda6, (q15_t)0x6d72, (q15_t)0xbda1, + (q15_t)0x6d6f, (q15_t)0xbd9c, (q15_t)0x6d6b, (q15_t)0xbd96, (q15_t)0x6d68, (q15_t)0xbd91, (q15_t)0x6d65, (q15_t)0xbd8c, + (q15_t)0x6d62, (q15_t)0xbd86, (q15_t)0x6d5e, (q15_t)0xbd81, (q15_t)0x6d5b, (q15_t)0xbd7c, (q15_t)0x6d58, (q15_t)0xbd76, + (q15_t)0x6d55, (q15_t)0xbd71, (q15_t)0x6d51, (q15_t)0xbd6b, (q15_t)0x6d4e, (q15_t)0xbd66, (q15_t)0x6d4b, (q15_t)0xbd61, + (q15_t)0x6d48, (q15_t)0xbd5b, (q15_t)0x6d44, (q15_t)0xbd56, (q15_t)0x6d41, (q15_t)0xbd51, (q15_t)0x6d3e, (q15_t)0xbd4b, + (q15_t)0x6d3a, (q15_t)0xbd46, (q15_t)0x6d37, (q15_t)0xbd40, (q15_t)0x6d34, (q15_t)0xbd3b, (q15_t)0x6d31, (q15_t)0xbd36, + (q15_t)0x6d2d, (q15_t)0xbd30, (q15_t)0x6d2a, (q15_t)0xbd2b, (q15_t)0x6d27, (q15_t)0xbd26, (q15_t)0x6d23, (q15_t)0xbd20, + (q15_t)0x6d20, (q15_t)0xbd1b, (q15_t)0x6d1d, (q15_t)0xbd16, (q15_t)0x6d1a, (q15_t)0xbd10, (q15_t)0x6d16, (q15_t)0xbd0b, + (q15_t)0x6d13, (q15_t)0xbd06, (q15_t)0x6d10, (q15_t)0xbd00, (q15_t)0x6d0c, (q15_t)0xbcfb, (q15_t)0x6d09, (q15_t)0xbcf5, + (q15_t)0x6d06, (q15_t)0xbcf0, (q15_t)0x6d03, (q15_t)0xbceb, (q15_t)0x6cff, (q15_t)0xbce5, (q15_t)0x6cfc, (q15_t)0xbce0, + (q15_t)0x6cf9, (q15_t)0xbcdb, (q15_t)0x6cf5, (q15_t)0xbcd5, (q15_t)0x6cf2, (q15_t)0xbcd0, (q15_t)0x6cef, (q15_t)0xbccb, + (q15_t)0x6cec, (q15_t)0xbcc5, (q15_t)0x6ce8, (q15_t)0xbcc0, (q15_t)0x6ce5, (q15_t)0xbcbb, (q15_t)0x6ce2, (q15_t)0xbcb5, + (q15_t)0x6cde, (q15_t)0xbcb0, (q15_t)0x6cdb, (q15_t)0xbcab, (q15_t)0x6cd8, (q15_t)0xbca5, (q15_t)0x6cd4, (q15_t)0xbca0, + (q15_t)0x6cd1, (q15_t)0xbc9b, (q15_t)0x6cce, (q15_t)0xbc95, (q15_t)0x6cca, (q15_t)0xbc90, (q15_t)0x6cc7, (q15_t)0xbc8b, + (q15_t)0x6cc4, (q15_t)0xbc85, (q15_t)0x6cc1, (q15_t)0xbc80, (q15_t)0x6cbd, (q15_t)0xbc7b, (q15_t)0x6cba, (q15_t)0xbc75, + (q15_t)0x6cb7, (q15_t)0xbc70, (q15_t)0x6cb3, (q15_t)0xbc6b, (q15_t)0x6cb0, (q15_t)0xbc65, (q15_t)0x6cad, (q15_t)0xbc60, + (q15_t)0x6ca9, (q15_t)0xbc5b, (q15_t)0x6ca6, (q15_t)0xbc55, (q15_t)0x6ca3, (q15_t)0xbc50, (q15_t)0x6c9f, (q15_t)0xbc4b, + (q15_t)0x6c9c, (q15_t)0xbc45, (q15_t)0x6c99, (q15_t)0xbc40, (q15_t)0x6c95, (q15_t)0xbc3b, (q15_t)0x6c92, (q15_t)0xbc35, + (q15_t)0x6c8f, (q15_t)0xbc30, (q15_t)0x6c8b, (q15_t)0xbc2b, (q15_t)0x6c88, (q15_t)0xbc25, (q15_t)0x6c85, (q15_t)0xbc20, + (q15_t)0x6c81, (q15_t)0xbc1b, (q15_t)0x6c7e, (q15_t)0xbc15, (q15_t)0x6c7b, (q15_t)0xbc10, (q15_t)0x6c77, (q15_t)0xbc0b, + (q15_t)0x6c74, (q15_t)0xbc05, (q15_t)0x6c71, (q15_t)0xbc00, (q15_t)0x6c6d, (q15_t)0xbbfb, (q15_t)0x6c6a, (q15_t)0xbbf5, + (q15_t)0x6c67, (q15_t)0xbbf0, (q15_t)0x6c63, (q15_t)0xbbeb, (q15_t)0x6c60, (q15_t)0xbbe5, (q15_t)0x6c5d, (q15_t)0xbbe0, + (q15_t)0x6c59, (q15_t)0xbbdb, (q15_t)0x6c56, (q15_t)0xbbd5, (q15_t)0x6c53, (q15_t)0xbbd0, (q15_t)0x6c4f, (q15_t)0xbbcb, + (q15_t)0x6c4c, (q15_t)0xbbc5, (q15_t)0x6c49, (q15_t)0xbbc0, (q15_t)0x6c45, (q15_t)0xbbbb, (q15_t)0x6c42, (q15_t)0xbbb5, + (q15_t)0x6c3f, (q15_t)0xbbb0, (q15_t)0x6c3b, (q15_t)0xbbab, (q15_t)0x6c38, (q15_t)0xbba6, (q15_t)0x6c34, (q15_t)0xbba0, + (q15_t)0x6c31, (q15_t)0xbb9b, (q15_t)0x6c2e, (q15_t)0xbb96, (q15_t)0x6c2a, (q15_t)0xbb90, (q15_t)0x6c27, (q15_t)0xbb8b, + (q15_t)0x6c24, (q15_t)0xbb86, (q15_t)0x6c20, (q15_t)0xbb80, (q15_t)0x6c1d, (q15_t)0xbb7b, (q15_t)0x6c1a, (q15_t)0xbb76, + (q15_t)0x6c16, (q15_t)0xbb70, (q15_t)0x6c13, (q15_t)0xbb6b, (q15_t)0x6c0f, (q15_t)0xbb66, (q15_t)0x6c0c, (q15_t)0xbb61, + (q15_t)0x6c09, (q15_t)0xbb5b, (q15_t)0x6c05, (q15_t)0xbb56, (q15_t)0x6c02, (q15_t)0xbb51, (q15_t)0x6bff, (q15_t)0xbb4b, + (q15_t)0x6bfb, (q15_t)0xbb46, (q15_t)0x6bf8, (q15_t)0xbb41, (q15_t)0x6bf5, (q15_t)0xbb3b, (q15_t)0x6bf1, (q15_t)0xbb36, + (q15_t)0x6bee, (q15_t)0xbb31, (q15_t)0x6bea, (q15_t)0xbb2c, (q15_t)0x6be7, (q15_t)0xbb26, (q15_t)0x6be4, (q15_t)0xbb21, + (q15_t)0x6be0, (q15_t)0xbb1c, (q15_t)0x6bdd, (q15_t)0xbb16, (q15_t)0x6bd9, (q15_t)0xbb11, (q15_t)0x6bd6, (q15_t)0xbb0c, + (q15_t)0x6bd3, (q15_t)0xbb06, (q15_t)0x6bcf, (q15_t)0xbb01, (q15_t)0x6bcc, (q15_t)0xbafc, (q15_t)0x6bc9, (q15_t)0xbaf7, + (q15_t)0x6bc5, (q15_t)0xbaf1, (q15_t)0x6bc2, (q15_t)0xbaec, (q15_t)0x6bbe, (q15_t)0xbae7, (q15_t)0x6bbb, (q15_t)0xbae1, + (q15_t)0x6bb8, (q15_t)0xbadc, (q15_t)0x6bb4, (q15_t)0xbad7, (q15_t)0x6bb1, (q15_t)0xbad2, (q15_t)0x6bad, (q15_t)0xbacc, + (q15_t)0x6baa, (q15_t)0xbac7, (q15_t)0x6ba7, (q15_t)0xbac2, (q15_t)0x6ba3, (q15_t)0xbabc, (q15_t)0x6ba0, (q15_t)0xbab7, + (q15_t)0x6b9c, (q15_t)0xbab2, (q15_t)0x6b99, (q15_t)0xbaad, (q15_t)0x6b96, (q15_t)0xbaa7, (q15_t)0x6b92, (q15_t)0xbaa2, + (q15_t)0x6b8f, (q15_t)0xba9d, (q15_t)0x6b8b, (q15_t)0xba97, (q15_t)0x6b88, (q15_t)0xba92, (q15_t)0x6b85, (q15_t)0xba8d, + (q15_t)0x6b81, (q15_t)0xba88, (q15_t)0x6b7e, (q15_t)0xba82, (q15_t)0x6b7a, (q15_t)0xba7d, (q15_t)0x6b77, (q15_t)0xba78, + (q15_t)0x6b73, (q15_t)0xba73, (q15_t)0x6b70, (q15_t)0xba6d, (q15_t)0x6b6d, (q15_t)0xba68, (q15_t)0x6b69, (q15_t)0xba63, + (q15_t)0x6b66, (q15_t)0xba5d, (q15_t)0x6b62, (q15_t)0xba58, (q15_t)0x6b5f, (q15_t)0xba53, (q15_t)0x6b5c, (q15_t)0xba4e, + (q15_t)0x6b58, (q15_t)0xba48, (q15_t)0x6b55, (q15_t)0xba43, (q15_t)0x6b51, (q15_t)0xba3e, (q15_t)0x6b4e, (q15_t)0xba39, + (q15_t)0x6b4a, (q15_t)0xba33, (q15_t)0x6b47, (q15_t)0xba2e, (q15_t)0x6b44, (q15_t)0xba29, (q15_t)0x6b40, (q15_t)0xba23, + (q15_t)0x6b3d, (q15_t)0xba1e, (q15_t)0x6b39, (q15_t)0xba19, (q15_t)0x6b36, (q15_t)0xba14, (q15_t)0x6b32, (q15_t)0xba0e, + (q15_t)0x6b2f, (q15_t)0xba09, (q15_t)0x6b2c, (q15_t)0xba04, (q15_t)0x6b28, (q15_t)0xb9ff, (q15_t)0x6b25, (q15_t)0xb9f9, + (q15_t)0x6b21, (q15_t)0xb9f4, (q15_t)0x6b1e, (q15_t)0xb9ef, (q15_t)0x6b1a, (q15_t)0xb9ea, (q15_t)0x6b17, (q15_t)0xb9e4, + (q15_t)0x6b13, (q15_t)0xb9df, (q15_t)0x6b10, (q15_t)0xb9da, (q15_t)0x6b0d, (q15_t)0xb9d5, (q15_t)0x6b09, (q15_t)0xb9cf, + (q15_t)0x6b06, (q15_t)0xb9ca, (q15_t)0x6b02, (q15_t)0xb9c5, (q15_t)0x6aff, (q15_t)0xb9c0, (q15_t)0x6afb, (q15_t)0xb9ba, + (q15_t)0x6af8, (q15_t)0xb9b5, (q15_t)0x6af4, (q15_t)0xb9b0, (q15_t)0x6af1, (q15_t)0xb9ab, (q15_t)0x6aee, (q15_t)0xb9a5, + (q15_t)0x6aea, (q15_t)0xb9a0, (q15_t)0x6ae7, (q15_t)0xb99b, (q15_t)0x6ae3, (q15_t)0xb996, (q15_t)0x6ae0, (q15_t)0xb990, + (q15_t)0x6adc, (q15_t)0xb98b, (q15_t)0x6ad9, (q15_t)0xb986, (q15_t)0x6ad5, (q15_t)0xb981, (q15_t)0x6ad2, (q15_t)0xb97b, + (q15_t)0x6ace, (q15_t)0xb976, (q15_t)0x6acb, (q15_t)0xb971, (q15_t)0x6ac8, (q15_t)0xb96c, (q15_t)0x6ac4, (q15_t)0xb966, + (q15_t)0x6ac1, (q15_t)0xb961, (q15_t)0x6abd, (q15_t)0xb95c, (q15_t)0x6aba, (q15_t)0xb957, (q15_t)0x6ab6, (q15_t)0xb951, + (q15_t)0x6ab3, (q15_t)0xb94c, (q15_t)0x6aaf, (q15_t)0xb947, (q15_t)0x6aac, (q15_t)0xb942, (q15_t)0x6aa8, (q15_t)0xb93c, + (q15_t)0x6aa5, (q15_t)0xb937, (q15_t)0x6aa1, (q15_t)0xb932, (q15_t)0x6a9e, (q15_t)0xb92d, (q15_t)0x6a9a, (q15_t)0xb928, + (q15_t)0x6a97, (q15_t)0xb922, (q15_t)0x6a93, (q15_t)0xb91d, (q15_t)0x6a90, (q15_t)0xb918, (q15_t)0x6a8c, (q15_t)0xb913, + (q15_t)0x6a89, (q15_t)0xb90d, (q15_t)0x6a86, (q15_t)0xb908, (q15_t)0x6a82, (q15_t)0xb903, (q15_t)0x6a7f, (q15_t)0xb8fe, + (q15_t)0x6a7b, (q15_t)0xb8f8, (q15_t)0x6a78, (q15_t)0xb8f3, (q15_t)0x6a74, (q15_t)0xb8ee, (q15_t)0x6a71, (q15_t)0xb8e9, + (q15_t)0x6a6d, (q15_t)0xb8e4, (q15_t)0x6a6a, (q15_t)0xb8de, (q15_t)0x6a66, (q15_t)0xb8d9, (q15_t)0x6a63, (q15_t)0xb8d4, + (q15_t)0x6a5f, (q15_t)0xb8cf, (q15_t)0x6a5c, (q15_t)0xb8c9, (q15_t)0x6a58, (q15_t)0xb8c4, (q15_t)0x6a55, (q15_t)0xb8bf, + (q15_t)0x6a51, (q15_t)0xb8ba, (q15_t)0x6a4e, (q15_t)0xb8b5, (q15_t)0x6a4a, (q15_t)0xb8af, (q15_t)0x6a47, (q15_t)0xb8aa, + (q15_t)0x6a43, (q15_t)0xb8a5, (q15_t)0x6a40, (q15_t)0xb8a0, (q15_t)0x6a3c, (q15_t)0xb89b, (q15_t)0x6a39, (q15_t)0xb895, + (q15_t)0x6a35, (q15_t)0xb890, (q15_t)0x6a32, (q15_t)0xb88b, (q15_t)0x6a2e, (q15_t)0xb886, (q15_t)0x6a2b, (q15_t)0xb880, + (q15_t)0x6a27, (q15_t)0xb87b, (q15_t)0x6a24, (q15_t)0xb876, (q15_t)0x6a20, (q15_t)0xb871, (q15_t)0x6a1d, (q15_t)0xb86c, + (q15_t)0x6a19, (q15_t)0xb866, (q15_t)0x6a16, (q15_t)0xb861, (q15_t)0x6a12, (q15_t)0xb85c, (q15_t)0x6a0e, (q15_t)0xb857, + (q15_t)0x6a0b, (q15_t)0xb852, (q15_t)0x6a07, (q15_t)0xb84c, (q15_t)0x6a04, (q15_t)0xb847, (q15_t)0x6a00, (q15_t)0xb842, + (q15_t)0x69fd, (q15_t)0xb83d, (q15_t)0x69f9, (q15_t)0xb838, (q15_t)0x69f6, (q15_t)0xb832, (q15_t)0x69f2, (q15_t)0xb82d, + (q15_t)0x69ef, (q15_t)0xb828, (q15_t)0x69eb, (q15_t)0xb823, (q15_t)0x69e8, (q15_t)0xb81e, (q15_t)0x69e4, (q15_t)0xb818, + (q15_t)0x69e1, (q15_t)0xb813, (q15_t)0x69dd, (q15_t)0xb80e, (q15_t)0x69da, (q15_t)0xb809, (q15_t)0x69d6, (q15_t)0xb804, + (q15_t)0x69d3, (q15_t)0xb7fe, (q15_t)0x69cf, (q15_t)0xb7f9, (q15_t)0x69cb, (q15_t)0xb7f4, (q15_t)0x69c8, (q15_t)0xb7ef, + (q15_t)0x69c4, (q15_t)0xb7ea, (q15_t)0x69c1, (q15_t)0xb7e4, (q15_t)0x69bd, (q15_t)0xb7df, (q15_t)0x69ba, (q15_t)0xb7da, + (q15_t)0x69b6, (q15_t)0xb7d5, (q15_t)0x69b3, (q15_t)0xb7d0, (q15_t)0x69af, (q15_t)0xb7ca, (q15_t)0x69ac, (q15_t)0xb7c5, + (q15_t)0x69a8, (q15_t)0xb7c0, (q15_t)0x69a5, (q15_t)0xb7bb, (q15_t)0x69a1, (q15_t)0xb7b6, (q15_t)0x699d, (q15_t)0xb7b1, + (q15_t)0x699a, (q15_t)0xb7ab, (q15_t)0x6996, (q15_t)0xb7a6, (q15_t)0x6993, (q15_t)0xb7a1, (q15_t)0x698f, (q15_t)0xb79c, + (q15_t)0x698c, (q15_t)0xb797, (q15_t)0x6988, (q15_t)0xb791, (q15_t)0x6985, (q15_t)0xb78c, (q15_t)0x6981, (q15_t)0xb787, + (q15_t)0x697d, (q15_t)0xb782, (q15_t)0x697a, (q15_t)0xb77d, (q15_t)0x6976, (q15_t)0xb778, (q15_t)0x6973, (q15_t)0xb772, + (q15_t)0x696f, (q15_t)0xb76d, (q15_t)0x696c, (q15_t)0xb768, (q15_t)0x6968, (q15_t)0xb763, (q15_t)0x6964, (q15_t)0xb75e, + (q15_t)0x6961, (q15_t)0xb758, (q15_t)0x695d, (q15_t)0xb753, (q15_t)0x695a, (q15_t)0xb74e, (q15_t)0x6956, (q15_t)0xb749, + (q15_t)0x6953, (q15_t)0xb744, (q15_t)0x694f, (q15_t)0xb73f, (q15_t)0x694b, (q15_t)0xb739, (q15_t)0x6948, (q15_t)0xb734, + (q15_t)0x6944, (q15_t)0xb72f, (q15_t)0x6941, (q15_t)0xb72a, (q15_t)0x693d, (q15_t)0xb725, (q15_t)0x693a, (q15_t)0xb720, + (q15_t)0x6936, (q15_t)0xb71a, (q15_t)0x6932, (q15_t)0xb715, (q15_t)0x692f, (q15_t)0xb710, (q15_t)0x692b, (q15_t)0xb70b, + (q15_t)0x6928, (q15_t)0xb706, (q15_t)0x6924, (q15_t)0xb701, (q15_t)0x6921, (q15_t)0xb6fb, (q15_t)0x691d, (q15_t)0xb6f6, + (q15_t)0x6919, (q15_t)0xb6f1, (q15_t)0x6916, (q15_t)0xb6ec, (q15_t)0x6912, (q15_t)0xb6e7, (q15_t)0x690f, (q15_t)0xb6e2, + (q15_t)0x690b, (q15_t)0xb6dd, (q15_t)0x6907, (q15_t)0xb6d7, (q15_t)0x6904, (q15_t)0xb6d2, (q15_t)0x6900, (q15_t)0xb6cd, + (q15_t)0x68fd, (q15_t)0xb6c8, (q15_t)0x68f9, (q15_t)0xb6c3, (q15_t)0x68f5, (q15_t)0xb6be, (q15_t)0x68f2, (q15_t)0xb6b8, + (q15_t)0x68ee, (q15_t)0xb6b3, (q15_t)0x68eb, (q15_t)0xb6ae, (q15_t)0x68e7, (q15_t)0xb6a9, (q15_t)0x68e3, (q15_t)0xb6a4, + (q15_t)0x68e0, (q15_t)0xb69f, (q15_t)0x68dc, (q15_t)0xb69a, (q15_t)0x68d9, (q15_t)0xb694, (q15_t)0x68d5, (q15_t)0xb68f, + (q15_t)0x68d1, (q15_t)0xb68a, (q15_t)0x68ce, (q15_t)0xb685, (q15_t)0x68ca, (q15_t)0xb680, (q15_t)0x68c7, (q15_t)0xb67b, + (q15_t)0x68c3, (q15_t)0xb676, (q15_t)0x68bf, (q15_t)0xb670, (q15_t)0x68bc, (q15_t)0xb66b, (q15_t)0x68b8, (q15_t)0xb666, + (q15_t)0x68b5, (q15_t)0xb661, (q15_t)0x68b1, (q15_t)0xb65c, (q15_t)0x68ad, (q15_t)0xb657, (q15_t)0x68aa, (q15_t)0xb652, + (q15_t)0x68a6, (q15_t)0xb64c, (q15_t)0x68a3, (q15_t)0xb647, (q15_t)0x689f, (q15_t)0xb642, (q15_t)0x689b, (q15_t)0xb63d, + (q15_t)0x6898, (q15_t)0xb638, (q15_t)0x6894, (q15_t)0xb633, (q15_t)0x6890, (q15_t)0xb62e, (q15_t)0x688d, (q15_t)0xb628, + (q15_t)0x6889, (q15_t)0xb623, (q15_t)0x6886, (q15_t)0xb61e, (q15_t)0x6882, (q15_t)0xb619, (q15_t)0x687e, (q15_t)0xb614, + (q15_t)0x687b, (q15_t)0xb60f, (q15_t)0x6877, (q15_t)0xb60a, (q15_t)0x6873, (q15_t)0xb605, (q15_t)0x6870, (q15_t)0xb5ff, + (q15_t)0x686c, (q15_t)0xb5fa, (q15_t)0x6868, (q15_t)0xb5f5, (q15_t)0x6865, (q15_t)0xb5f0, (q15_t)0x6861, (q15_t)0xb5eb, + (q15_t)0x685e, (q15_t)0xb5e6, (q15_t)0x685a, (q15_t)0xb5e1, (q15_t)0x6856, (q15_t)0xb5dc, (q15_t)0x6853, (q15_t)0xb5d6, + (q15_t)0x684f, (q15_t)0xb5d1, (q15_t)0x684b, (q15_t)0xb5cc, (q15_t)0x6848, (q15_t)0xb5c7, (q15_t)0x6844, (q15_t)0xb5c2, + (q15_t)0x6840, (q15_t)0xb5bd, (q15_t)0x683d, (q15_t)0xb5b8, (q15_t)0x6839, (q15_t)0xb5b3, (q15_t)0x6835, (q15_t)0xb5ae, + (q15_t)0x6832, (q15_t)0xb5a8, (q15_t)0x682e, (q15_t)0xb5a3, (q15_t)0x682b, (q15_t)0xb59e, (q15_t)0x6827, (q15_t)0xb599, + (q15_t)0x6823, (q15_t)0xb594, (q15_t)0x6820, (q15_t)0xb58f, (q15_t)0x681c, (q15_t)0xb58a, (q15_t)0x6818, (q15_t)0xb585, + (q15_t)0x6815, (q15_t)0xb57f, (q15_t)0x6811, (q15_t)0xb57a, (q15_t)0x680d, (q15_t)0xb575, (q15_t)0x680a, (q15_t)0xb570, + (q15_t)0x6806, (q15_t)0xb56b, (q15_t)0x6802, (q15_t)0xb566, (q15_t)0x67ff, (q15_t)0xb561, (q15_t)0x67fb, (q15_t)0xb55c, + (q15_t)0x67f7, (q15_t)0xb557, (q15_t)0x67f4, (q15_t)0xb552, (q15_t)0x67f0, (q15_t)0xb54c, (q15_t)0x67ec, (q15_t)0xb547, + (q15_t)0x67e9, (q15_t)0xb542, (q15_t)0x67e5, (q15_t)0xb53d, (q15_t)0x67e1, (q15_t)0xb538, (q15_t)0x67de, (q15_t)0xb533, + (q15_t)0x67da, (q15_t)0xb52e, (q15_t)0x67d6, (q15_t)0xb529, (q15_t)0x67d3, (q15_t)0xb524, (q15_t)0x67cf, (q15_t)0xb51f, + (q15_t)0x67cb, (q15_t)0xb519, (q15_t)0x67c8, (q15_t)0xb514, (q15_t)0x67c4, (q15_t)0xb50f, (q15_t)0x67c0, (q15_t)0xb50a, + (q15_t)0x67bd, (q15_t)0xb505, (q15_t)0x67b9, (q15_t)0xb500, (q15_t)0x67b5, (q15_t)0xb4fb, (q15_t)0x67b2, (q15_t)0xb4f6, + (q15_t)0x67ae, (q15_t)0xb4f1, (q15_t)0x67aa, (q15_t)0xb4ec, (q15_t)0x67a6, (q15_t)0xb4e7, (q15_t)0x67a3, (q15_t)0xb4e1, + (q15_t)0x679f, (q15_t)0xb4dc, (q15_t)0x679b, (q15_t)0xb4d7, (q15_t)0x6798, (q15_t)0xb4d2, (q15_t)0x6794, (q15_t)0xb4cd, + (q15_t)0x6790, (q15_t)0xb4c8, (q15_t)0x678d, (q15_t)0xb4c3, (q15_t)0x6789, (q15_t)0xb4be, (q15_t)0x6785, (q15_t)0xb4b9, + (q15_t)0x6782, (q15_t)0xb4b4, (q15_t)0x677e, (q15_t)0xb4af, (q15_t)0x677a, (q15_t)0xb4aa, (q15_t)0x6776, (q15_t)0xb4a4, + (q15_t)0x6773, (q15_t)0xb49f, (q15_t)0x676f, (q15_t)0xb49a, (q15_t)0x676b, (q15_t)0xb495, (q15_t)0x6768, (q15_t)0xb490, + (q15_t)0x6764, (q15_t)0xb48b, (q15_t)0x6760, (q15_t)0xb486, (q15_t)0x675d, (q15_t)0xb481, (q15_t)0x6759, (q15_t)0xb47c, + (q15_t)0x6755, (q15_t)0xb477, (q15_t)0x6751, (q15_t)0xb472, (q15_t)0x674e, (q15_t)0xb46d, (q15_t)0x674a, (q15_t)0xb468, + (q15_t)0x6746, (q15_t)0xb462, (q15_t)0x6743, (q15_t)0xb45d, (q15_t)0x673f, (q15_t)0xb458, (q15_t)0x673b, (q15_t)0xb453, + (q15_t)0x6737, (q15_t)0xb44e, (q15_t)0x6734, (q15_t)0xb449, (q15_t)0x6730, (q15_t)0xb444, (q15_t)0x672c, (q15_t)0xb43f, + (q15_t)0x6729, (q15_t)0xb43a, (q15_t)0x6725, (q15_t)0xb435, (q15_t)0x6721, (q15_t)0xb430, (q15_t)0x671d, (q15_t)0xb42b, + (q15_t)0x671a, (q15_t)0xb426, (q15_t)0x6716, (q15_t)0xb421, (q15_t)0x6712, (q15_t)0xb41c, (q15_t)0x670e, (q15_t)0xb417, + (q15_t)0x670b, (q15_t)0xb411, (q15_t)0x6707, (q15_t)0xb40c, (q15_t)0x6703, (q15_t)0xb407, (q15_t)0x6700, (q15_t)0xb402, + (q15_t)0x66fc, (q15_t)0xb3fd, (q15_t)0x66f8, (q15_t)0xb3f8, (q15_t)0x66f4, (q15_t)0xb3f3, (q15_t)0x66f1, (q15_t)0xb3ee, + (q15_t)0x66ed, (q15_t)0xb3e9, (q15_t)0x66e9, (q15_t)0xb3e4, (q15_t)0x66e5, (q15_t)0xb3df, (q15_t)0x66e2, (q15_t)0xb3da, + (q15_t)0x66de, (q15_t)0xb3d5, (q15_t)0x66da, (q15_t)0xb3d0, (q15_t)0x66d6, (q15_t)0xb3cb, (q15_t)0x66d3, (q15_t)0xb3c6, + (q15_t)0x66cf, (q15_t)0xb3c1, (q15_t)0x66cb, (q15_t)0xb3bc, (q15_t)0x66c8, (q15_t)0xb3b7, (q15_t)0x66c4, (q15_t)0xb3b1, + (q15_t)0x66c0, (q15_t)0xb3ac, (q15_t)0x66bc, (q15_t)0xb3a7, (q15_t)0x66b9, (q15_t)0xb3a2, (q15_t)0x66b5, (q15_t)0xb39d, + (q15_t)0x66b1, (q15_t)0xb398, (q15_t)0x66ad, (q15_t)0xb393, (q15_t)0x66aa, (q15_t)0xb38e, (q15_t)0x66a6, (q15_t)0xb389, + (q15_t)0x66a2, (q15_t)0xb384, (q15_t)0x669e, (q15_t)0xb37f, (q15_t)0x669b, (q15_t)0xb37a, (q15_t)0x6697, (q15_t)0xb375, + (q15_t)0x6693, (q15_t)0xb370, (q15_t)0x668f, (q15_t)0xb36b, (q15_t)0x668b, (q15_t)0xb366, (q15_t)0x6688, (q15_t)0xb361, + (q15_t)0x6684, (q15_t)0xb35c, (q15_t)0x6680, (q15_t)0xb357, (q15_t)0x667c, (q15_t)0xb352, (q15_t)0x6679, (q15_t)0xb34d, + (q15_t)0x6675, (q15_t)0xb348, (q15_t)0x6671, (q15_t)0xb343, (q15_t)0x666d, (q15_t)0xb33e, (q15_t)0x666a, (q15_t)0xb339, + (q15_t)0x6666, (q15_t)0xb334, (q15_t)0x6662, (q15_t)0xb32f, (q15_t)0x665e, (q15_t)0xb32a, (q15_t)0x665b, (q15_t)0xb325, + (q15_t)0x6657, (q15_t)0xb31f, (q15_t)0x6653, (q15_t)0xb31a, (q15_t)0x664f, (q15_t)0xb315, (q15_t)0x664b, (q15_t)0xb310, + (q15_t)0x6648, (q15_t)0xb30b, (q15_t)0x6644, (q15_t)0xb306, (q15_t)0x6640, (q15_t)0xb301, (q15_t)0x663c, (q15_t)0xb2fc, + (q15_t)0x6639, (q15_t)0xb2f7, (q15_t)0x6635, (q15_t)0xb2f2, (q15_t)0x6631, (q15_t)0xb2ed, (q15_t)0x662d, (q15_t)0xb2e8, + (q15_t)0x6629, (q15_t)0xb2e3, (q15_t)0x6626, (q15_t)0xb2de, (q15_t)0x6622, (q15_t)0xb2d9, (q15_t)0x661e, (q15_t)0xb2d4, + (q15_t)0x661a, (q15_t)0xb2cf, (q15_t)0x6616, (q15_t)0xb2ca, (q15_t)0x6613, (q15_t)0xb2c5, (q15_t)0x660f, (q15_t)0xb2c0, + (q15_t)0x660b, (q15_t)0xb2bb, (q15_t)0x6607, (q15_t)0xb2b6, (q15_t)0x6603, (q15_t)0xb2b1, (q15_t)0x6600, (q15_t)0xb2ac, + (q15_t)0x65fc, (q15_t)0xb2a7, (q15_t)0x65f8, (q15_t)0xb2a2, (q15_t)0x65f4, (q15_t)0xb29d, (q15_t)0x65f0, (q15_t)0xb298, + (q15_t)0x65ed, (q15_t)0xb293, (q15_t)0x65e9, (q15_t)0xb28e, (q15_t)0x65e5, (q15_t)0xb289, (q15_t)0x65e1, (q15_t)0xb284, + (q15_t)0x65dd, (q15_t)0xb27f, (q15_t)0x65da, (q15_t)0xb27a, (q15_t)0x65d6, (q15_t)0xb275, (q15_t)0x65d2, (q15_t)0xb270, + (q15_t)0x65ce, (q15_t)0xb26b, (q15_t)0x65ca, (q15_t)0xb266, (q15_t)0x65c7, (q15_t)0xb261, (q15_t)0x65c3, (q15_t)0xb25c, + (q15_t)0x65bf, (q15_t)0xb257, (q15_t)0x65bb, (q15_t)0xb252, (q15_t)0x65b7, (q15_t)0xb24d, (q15_t)0x65b4, (q15_t)0xb248, + (q15_t)0x65b0, (q15_t)0xb243, (q15_t)0x65ac, (q15_t)0xb23e, (q15_t)0x65a8, (q15_t)0xb239, (q15_t)0x65a4, (q15_t)0xb234, + (q15_t)0x65a0, (q15_t)0xb22f, (q15_t)0x659d, (q15_t)0xb22a, (q15_t)0x6599, (q15_t)0xb225, (q15_t)0x6595, (q15_t)0xb220, + (q15_t)0x6591, (q15_t)0xb21b, (q15_t)0x658d, (q15_t)0xb216, (q15_t)0x658a, (q15_t)0xb211, (q15_t)0x6586, (q15_t)0xb20c, + (q15_t)0x6582, (q15_t)0xb207, (q15_t)0x657e, (q15_t)0xb202, (q15_t)0x657a, (q15_t)0xb1fd, (q15_t)0x6576, (q15_t)0xb1f8, + (q15_t)0x6573, (q15_t)0xb1f3, (q15_t)0x656f, (q15_t)0xb1ee, (q15_t)0x656b, (q15_t)0xb1e9, (q15_t)0x6567, (q15_t)0xb1e4, + (q15_t)0x6563, (q15_t)0xb1df, (q15_t)0x655f, (q15_t)0xb1da, (q15_t)0x655c, (q15_t)0xb1d6, (q15_t)0x6558, (q15_t)0xb1d1, + (q15_t)0x6554, (q15_t)0xb1cc, (q15_t)0x6550, (q15_t)0xb1c7, (q15_t)0x654c, (q15_t)0xb1c2, (q15_t)0x6548, (q15_t)0xb1bd, + (q15_t)0x6545, (q15_t)0xb1b8, (q15_t)0x6541, (q15_t)0xb1b3, (q15_t)0x653d, (q15_t)0xb1ae, (q15_t)0x6539, (q15_t)0xb1a9, + (q15_t)0x6535, (q15_t)0xb1a4, (q15_t)0x6531, (q15_t)0xb19f, (q15_t)0x652d, (q15_t)0xb19a, (q15_t)0x652a, (q15_t)0xb195, + (q15_t)0x6526, (q15_t)0xb190, (q15_t)0x6522, (q15_t)0xb18b, (q15_t)0x651e, (q15_t)0xb186, (q15_t)0x651a, (q15_t)0xb181, + (q15_t)0x6516, (q15_t)0xb17c, (q15_t)0x6513, (q15_t)0xb177, (q15_t)0x650f, (q15_t)0xb172, (q15_t)0x650b, (q15_t)0xb16d, + (q15_t)0x6507, (q15_t)0xb168, (q15_t)0x6503, (q15_t)0xb163, (q15_t)0x64ff, (q15_t)0xb15e, (q15_t)0x64fb, (q15_t)0xb159, + (q15_t)0x64f7, (q15_t)0xb154, (q15_t)0x64f4, (q15_t)0xb14f, (q15_t)0x64f0, (q15_t)0xb14a, (q15_t)0x64ec, (q15_t)0xb146, + (q15_t)0x64e8, (q15_t)0xb141, (q15_t)0x64e4, (q15_t)0xb13c, (q15_t)0x64e0, (q15_t)0xb137, (q15_t)0x64dc, (q15_t)0xb132, + (q15_t)0x64d9, (q15_t)0xb12d, (q15_t)0x64d5, (q15_t)0xb128, (q15_t)0x64d1, (q15_t)0xb123, (q15_t)0x64cd, (q15_t)0xb11e, + (q15_t)0x64c9, (q15_t)0xb119, (q15_t)0x64c5, (q15_t)0xb114, (q15_t)0x64c1, (q15_t)0xb10f, (q15_t)0x64bd, (q15_t)0xb10a, + (q15_t)0x64ba, (q15_t)0xb105, (q15_t)0x64b6, (q15_t)0xb100, (q15_t)0x64b2, (q15_t)0xb0fb, (q15_t)0x64ae, (q15_t)0xb0f6, + (q15_t)0x64aa, (q15_t)0xb0f1, (q15_t)0x64a6, (q15_t)0xb0ec, (q15_t)0x64a2, (q15_t)0xb0e8, (q15_t)0x649e, (q15_t)0xb0e3, + (q15_t)0x649b, (q15_t)0xb0de, (q15_t)0x6497, (q15_t)0xb0d9, (q15_t)0x6493, (q15_t)0xb0d4, (q15_t)0x648f, (q15_t)0xb0cf, + (q15_t)0x648b, (q15_t)0xb0ca, (q15_t)0x6487, (q15_t)0xb0c5, (q15_t)0x6483, (q15_t)0xb0c0, (q15_t)0x647f, (q15_t)0xb0bb, + (q15_t)0x647b, (q15_t)0xb0b6, (q15_t)0x6478, (q15_t)0xb0b1, (q15_t)0x6474, (q15_t)0xb0ac, (q15_t)0x6470, (q15_t)0xb0a7, + (q15_t)0x646c, (q15_t)0xb0a2, (q15_t)0x6468, (q15_t)0xb09e, (q15_t)0x6464, (q15_t)0xb099, (q15_t)0x6460, (q15_t)0xb094, + (q15_t)0x645c, (q15_t)0xb08f, (q15_t)0x6458, (q15_t)0xb08a, (q15_t)0x6454, (q15_t)0xb085, (q15_t)0x6451, (q15_t)0xb080, + (q15_t)0x644d, (q15_t)0xb07b, (q15_t)0x6449, (q15_t)0xb076, (q15_t)0x6445, (q15_t)0xb071, (q15_t)0x6441, (q15_t)0xb06c, + (q15_t)0x643d, (q15_t)0xb067, (q15_t)0x6439, (q15_t)0xb062, (q15_t)0x6435, (q15_t)0xb05e, (q15_t)0x6431, (q15_t)0xb059, + (q15_t)0x642d, (q15_t)0xb054, (q15_t)0x6429, (q15_t)0xb04f, (q15_t)0x6426, (q15_t)0xb04a, (q15_t)0x6422, (q15_t)0xb045, + (q15_t)0x641e, (q15_t)0xb040, (q15_t)0x641a, (q15_t)0xb03b, (q15_t)0x6416, (q15_t)0xb036, (q15_t)0x6412, (q15_t)0xb031, + (q15_t)0x640e, (q15_t)0xb02c, (q15_t)0x640a, (q15_t)0xb027, (q15_t)0x6406, (q15_t)0xb023, (q15_t)0x6402, (q15_t)0xb01e, + (q15_t)0x63fe, (q15_t)0xb019, (q15_t)0x63fa, (q15_t)0xb014, (q15_t)0x63f7, (q15_t)0xb00f, (q15_t)0x63f3, (q15_t)0xb00a, + (q15_t)0x63ef, (q15_t)0xb005, (q15_t)0x63eb, (q15_t)0xb000, (q15_t)0x63e7, (q15_t)0xaffb, (q15_t)0x63e3, (q15_t)0xaff6, + (q15_t)0x63df, (q15_t)0xaff1, (q15_t)0x63db, (q15_t)0xafed, (q15_t)0x63d7, (q15_t)0xafe8, (q15_t)0x63d3, (q15_t)0xafe3, + (q15_t)0x63cf, (q15_t)0xafde, (q15_t)0x63cb, (q15_t)0xafd9, (q15_t)0x63c7, (q15_t)0xafd4, (q15_t)0x63c3, (q15_t)0xafcf, + (q15_t)0x63c0, (q15_t)0xafca, (q15_t)0x63bc, (q15_t)0xafc5, (q15_t)0x63b8, (q15_t)0xafc1, (q15_t)0x63b4, (q15_t)0xafbc, + (q15_t)0x63b0, (q15_t)0xafb7, (q15_t)0x63ac, (q15_t)0xafb2, (q15_t)0x63a8, (q15_t)0xafad, (q15_t)0x63a4, (q15_t)0xafa8, + (q15_t)0x63a0, (q15_t)0xafa3, (q15_t)0x639c, (q15_t)0xaf9e, (q15_t)0x6398, (q15_t)0xaf99, (q15_t)0x6394, (q15_t)0xaf94, + (q15_t)0x6390, (q15_t)0xaf90, (q15_t)0x638c, (q15_t)0xaf8b, (q15_t)0x6388, (q15_t)0xaf86, (q15_t)0x6384, (q15_t)0xaf81, + (q15_t)0x6380, (q15_t)0xaf7c, (q15_t)0x637c, (q15_t)0xaf77, (q15_t)0x6378, (q15_t)0xaf72, (q15_t)0x6375, (q15_t)0xaf6d, + (q15_t)0x6371, (q15_t)0xaf69, (q15_t)0x636d, (q15_t)0xaf64, (q15_t)0x6369, (q15_t)0xaf5f, (q15_t)0x6365, (q15_t)0xaf5a, + (q15_t)0x6361, (q15_t)0xaf55, (q15_t)0x635d, (q15_t)0xaf50, (q15_t)0x6359, (q15_t)0xaf4b, (q15_t)0x6355, (q15_t)0xaf46, + (q15_t)0x6351, (q15_t)0xaf41, (q15_t)0x634d, (q15_t)0xaf3d, (q15_t)0x6349, (q15_t)0xaf38, (q15_t)0x6345, (q15_t)0xaf33, + (q15_t)0x6341, (q15_t)0xaf2e, (q15_t)0x633d, (q15_t)0xaf29, (q15_t)0x6339, (q15_t)0xaf24, (q15_t)0x6335, (q15_t)0xaf1f, + (q15_t)0x6331, (q15_t)0xaf1b, (q15_t)0x632d, (q15_t)0xaf16, (q15_t)0x6329, (q15_t)0xaf11, (q15_t)0x6325, (q15_t)0xaf0c, + (q15_t)0x6321, (q15_t)0xaf07, (q15_t)0x631d, (q15_t)0xaf02, (q15_t)0x6319, (q15_t)0xaefd, (q15_t)0x6315, (q15_t)0xaef8, + (q15_t)0x6311, (q15_t)0xaef4, (q15_t)0x630d, (q15_t)0xaeef, (q15_t)0x6309, (q15_t)0xaeea, (q15_t)0x6305, (q15_t)0xaee5, + (q15_t)0x6301, (q15_t)0xaee0, (q15_t)0x62fd, (q15_t)0xaedb, (q15_t)0x62f9, (q15_t)0xaed6, (q15_t)0x62f5, (q15_t)0xaed2, + (q15_t)0x62f2, (q15_t)0xaecd, (q15_t)0x62ee, (q15_t)0xaec8, (q15_t)0x62ea, (q15_t)0xaec3, (q15_t)0x62e6, (q15_t)0xaebe, + (q15_t)0x62e2, (q15_t)0xaeb9, (q15_t)0x62de, (q15_t)0xaeb4, (q15_t)0x62da, (q15_t)0xaeb0, (q15_t)0x62d6, (q15_t)0xaeab, + (q15_t)0x62d2, (q15_t)0xaea6, (q15_t)0x62ce, (q15_t)0xaea1, (q15_t)0x62ca, (q15_t)0xae9c, (q15_t)0x62c6, (q15_t)0xae97, + (q15_t)0x62c2, (q15_t)0xae92, (q15_t)0x62be, (q15_t)0xae8e, (q15_t)0x62ba, (q15_t)0xae89, (q15_t)0x62b6, (q15_t)0xae84, + (q15_t)0x62b2, (q15_t)0xae7f, (q15_t)0x62ae, (q15_t)0xae7a, (q15_t)0x62aa, (q15_t)0xae75, (q15_t)0x62a6, (q15_t)0xae71, + (q15_t)0x62a2, (q15_t)0xae6c, (q15_t)0x629e, (q15_t)0xae67, (q15_t)0x629a, (q15_t)0xae62, (q15_t)0x6296, (q15_t)0xae5d, + (q15_t)0x6292, (q15_t)0xae58, (q15_t)0x628e, (q15_t)0xae54, (q15_t)0x628a, (q15_t)0xae4f, (q15_t)0x6286, (q15_t)0xae4a, + (q15_t)0x6282, (q15_t)0xae45, (q15_t)0x627e, (q15_t)0xae40, (q15_t)0x627a, (q15_t)0xae3b, (q15_t)0x6275, (q15_t)0xae37, + (q15_t)0x6271, (q15_t)0xae32, (q15_t)0x626d, (q15_t)0xae2d, (q15_t)0x6269, (q15_t)0xae28, (q15_t)0x6265, (q15_t)0xae23, + (q15_t)0x6261, (q15_t)0xae1e, (q15_t)0x625d, (q15_t)0xae1a, (q15_t)0x6259, (q15_t)0xae15, (q15_t)0x6255, (q15_t)0xae10, + (q15_t)0x6251, (q15_t)0xae0b, (q15_t)0x624d, (q15_t)0xae06, (q15_t)0x6249, (q15_t)0xae01, (q15_t)0x6245, (q15_t)0xadfd, + (q15_t)0x6241, (q15_t)0xadf8, (q15_t)0x623d, (q15_t)0xadf3, (q15_t)0x6239, (q15_t)0xadee, (q15_t)0x6235, (q15_t)0xade9, + (q15_t)0x6231, (q15_t)0xade4, (q15_t)0x622d, (q15_t)0xade0, (q15_t)0x6229, (q15_t)0xaddb, (q15_t)0x6225, (q15_t)0xadd6, + (q15_t)0x6221, (q15_t)0xadd1, (q15_t)0x621d, (q15_t)0xadcc, (q15_t)0x6219, (q15_t)0xadc8, (q15_t)0x6215, (q15_t)0xadc3, + (q15_t)0x6211, (q15_t)0xadbe, (q15_t)0x620d, (q15_t)0xadb9, (q15_t)0x6209, (q15_t)0xadb4, (q15_t)0x6205, (q15_t)0xadaf, + (q15_t)0x6201, (q15_t)0xadab, (q15_t)0x61fd, (q15_t)0xada6, (q15_t)0x61f9, (q15_t)0xada1, (q15_t)0x61f5, (q15_t)0xad9c, + (q15_t)0x61f1, (q15_t)0xad97, (q15_t)0x61ec, (q15_t)0xad93, (q15_t)0x61e8, (q15_t)0xad8e, (q15_t)0x61e4, (q15_t)0xad89, + (q15_t)0x61e0, (q15_t)0xad84, (q15_t)0x61dc, (q15_t)0xad7f, (q15_t)0x61d8, (q15_t)0xad7b, (q15_t)0x61d4, (q15_t)0xad76, + (q15_t)0x61d0, (q15_t)0xad71, (q15_t)0x61cc, (q15_t)0xad6c, (q15_t)0x61c8, (q15_t)0xad67, (q15_t)0x61c4, (q15_t)0xad63, + (q15_t)0x61c0, (q15_t)0xad5e, (q15_t)0x61bc, (q15_t)0xad59, (q15_t)0x61b8, (q15_t)0xad54, (q15_t)0x61b4, (q15_t)0xad4f, + (q15_t)0x61b0, (q15_t)0xad4b, (q15_t)0x61ac, (q15_t)0xad46, (q15_t)0x61a8, (q15_t)0xad41, (q15_t)0x61a3, (q15_t)0xad3c, + (q15_t)0x619f, (q15_t)0xad37, (q15_t)0x619b, (q15_t)0xad33, (q15_t)0x6197, (q15_t)0xad2e, (q15_t)0x6193, (q15_t)0xad29, + (q15_t)0x618f, (q15_t)0xad24, (q15_t)0x618b, (q15_t)0xad1f, (q15_t)0x6187, (q15_t)0xad1b, (q15_t)0x6183, (q15_t)0xad16, + (q15_t)0x617f, (q15_t)0xad11, (q15_t)0x617b, (q15_t)0xad0c, (q15_t)0x6177, (q15_t)0xad08, (q15_t)0x6173, (q15_t)0xad03, + (q15_t)0x616f, (q15_t)0xacfe, (q15_t)0x616b, (q15_t)0xacf9, (q15_t)0x6166, (q15_t)0xacf4, (q15_t)0x6162, (q15_t)0xacf0, + (q15_t)0x615e, (q15_t)0xaceb, (q15_t)0x615a, (q15_t)0xace6, (q15_t)0x6156, (q15_t)0xace1, (q15_t)0x6152, (q15_t)0xacdd, + (q15_t)0x614e, (q15_t)0xacd8, (q15_t)0x614a, (q15_t)0xacd3, (q15_t)0x6146, (q15_t)0xacce, (q15_t)0x6142, (q15_t)0xacc9, + (q15_t)0x613e, (q15_t)0xacc5, (q15_t)0x613a, (q15_t)0xacc0, (q15_t)0x6135, (q15_t)0xacbb, (q15_t)0x6131, (q15_t)0xacb6, + (q15_t)0x612d, (q15_t)0xacb2, (q15_t)0x6129, (q15_t)0xacad, (q15_t)0x6125, (q15_t)0xaca8, (q15_t)0x6121, (q15_t)0xaca3, + (q15_t)0x611d, (q15_t)0xac9e, (q15_t)0x6119, (q15_t)0xac9a, (q15_t)0x6115, (q15_t)0xac95, (q15_t)0x6111, (q15_t)0xac90, + (q15_t)0x610d, (q15_t)0xac8b, (q15_t)0x6108, (q15_t)0xac87, (q15_t)0x6104, (q15_t)0xac82, (q15_t)0x6100, (q15_t)0xac7d, + (q15_t)0x60fc, (q15_t)0xac78, (q15_t)0x60f8, (q15_t)0xac74, (q15_t)0x60f4, (q15_t)0xac6f, (q15_t)0x60f0, (q15_t)0xac6a, + (q15_t)0x60ec, (q15_t)0xac65, (q15_t)0x60e8, (q15_t)0xac61, (q15_t)0x60e4, (q15_t)0xac5c, (q15_t)0x60df, (q15_t)0xac57, + (q15_t)0x60db, (q15_t)0xac52, (q15_t)0x60d7, (q15_t)0xac4e, (q15_t)0x60d3, (q15_t)0xac49, (q15_t)0x60cf, (q15_t)0xac44, + (q15_t)0x60cb, (q15_t)0xac3f, (q15_t)0x60c7, (q15_t)0xac3b, (q15_t)0x60c3, (q15_t)0xac36, (q15_t)0x60bf, (q15_t)0xac31, + (q15_t)0x60ba, (q15_t)0xac2c, (q15_t)0x60b6, (q15_t)0xac28, (q15_t)0x60b2, (q15_t)0xac23, (q15_t)0x60ae, (q15_t)0xac1e, + (q15_t)0x60aa, (q15_t)0xac19, (q15_t)0x60a6, (q15_t)0xac15, (q15_t)0x60a2, (q15_t)0xac10, (q15_t)0x609e, (q15_t)0xac0b, + (q15_t)0x6099, (q15_t)0xac06, (q15_t)0x6095, (q15_t)0xac02, (q15_t)0x6091, (q15_t)0xabfd, (q15_t)0x608d, (q15_t)0xabf8, + (q15_t)0x6089, (q15_t)0xabf3, (q15_t)0x6085, (q15_t)0xabef, (q15_t)0x6081, (q15_t)0xabea, (q15_t)0x607d, (q15_t)0xabe5, + (q15_t)0x6078, (q15_t)0xabe0, (q15_t)0x6074, (q15_t)0xabdc, (q15_t)0x6070, (q15_t)0xabd7, (q15_t)0x606c, (q15_t)0xabd2, + (q15_t)0x6068, (q15_t)0xabcd, (q15_t)0x6064, (q15_t)0xabc9, (q15_t)0x6060, (q15_t)0xabc4, (q15_t)0x605c, (q15_t)0xabbf, + (q15_t)0x6057, (q15_t)0xabbb, (q15_t)0x6053, (q15_t)0xabb6, (q15_t)0x604f, (q15_t)0xabb1, (q15_t)0x604b, (q15_t)0xabac, + (q15_t)0x6047, (q15_t)0xaba8, (q15_t)0x6043, (q15_t)0xaba3, (q15_t)0x603f, (q15_t)0xab9e, (q15_t)0x603a, (q15_t)0xab99, + (q15_t)0x6036, (q15_t)0xab95, (q15_t)0x6032, (q15_t)0xab90, (q15_t)0x602e, (q15_t)0xab8b, (q15_t)0x602a, (q15_t)0xab87, + (q15_t)0x6026, (q15_t)0xab82, (q15_t)0x6022, (q15_t)0xab7d, (q15_t)0x601d, (q15_t)0xab78, (q15_t)0x6019, (q15_t)0xab74, + (q15_t)0x6015, (q15_t)0xab6f, (q15_t)0x6011, (q15_t)0xab6a, (q15_t)0x600d, (q15_t)0xab66, (q15_t)0x6009, (q15_t)0xab61, + (q15_t)0x6004, (q15_t)0xab5c, (q15_t)0x6000, (q15_t)0xab57, (q15_t)0x5ffc, (q15_t)0xab53, (q15_t)0x5ff8, (q15_t)0xab4e, + (q15_t)0x5ff4, (q15_t)0xab49, (q15_t)0x5ff0, (q15_t)0xab45, (q15_t)0x5fec, (q15_t)0xab40, (q15_t)0x5fe7, (q15_t)0xab3b, + (q15_t)0x5fe3, (q15_t)0xab36, (q15_t)0x5fdf, (q15_t)0xab32, (q15_t)0x5fdb, (q15_t)0xab2d, (q15_t)0x5fd7, (q15_t)0xab28, + (q15_t)0x5fd3, (q15_t)0xab24, (q15_t)0x5fce, (q15_t)0xab1f, (q15_t)0x5fca, (q15_t)0xab1a, (q15_t)0x5fc6, (q15_t)0xab16, + (q15_t)0x5fc2, (q15_t)0xab11, (q15_t)0x5fbe, (q15_t)0xab0c, (q15_t)0x5fba, (q15_t)0xab07, (q15_t)0x5fb5, (q15_t)0xab03, + (q15_t)0x5fb1, (q15_t)0xaafe, (q15_t)0x5fad, (q15_t)0xaaf9, (q15_t)0x5fa9, (q15_t)0xaaf5, (q15_t)0x5fa5, (q15_t)0xaaf0, + (q15_t)0x5fa0, (q15_t)0xaaeb, (q15_t)0x5f9c, (q15_t)0xaae7, (q15_t)0x5f98, (q15_t)0xaae2, (q15_t)0x5f94, (q15_t)0xaadd, + (q15_t)0x5f90, (q15_t)0xaad8, (q15_t)0x5f8c, (q15_t)0xaad4, (q15_t)0x5f87, (q15_t)0xaacf, (q15_t)0x5f83, (q15_t)0xaaca, + (q15_t)0x5f7f, (q15_t)0xaac6, (q15_t)0x5f7b, (q15_t)0xaac1, (q15_t)0x5f77, (q15_t)0xaabc, (q15_t)0x5f72, (q15_t)0xaab8, + (q15_t)0x5f6e, (q15_t)0xaab3, (q15_t)0x5f6a, (q15_t)0xaaae, (q15_t)0x5f66, (q15_t)0xaaaa, (q15_t)0x5f62, (q15_t)0xaaa5, + (q15_t)0x5f5e, (q15_t)0xaaa0, (q15_t)0x5f59, (q15_t)0xaa9c, (q15_t)0x5f55, (q15_t)0xaa97, (q15_t)0x5f51, (q15_t)0xaa92, + (q15_t)0x5f4d, (q15_t)0xaa8e, (q15_t)0x5f49, (q15_t)0xaa89, (q15_t)0x5f44, (q15_t)0xaa84, (q15_t)0x5f40, (q15_t)0xaa7f, + (q15_t)0x5f3c, (q15_t)0xaa7b, (q15_t)0x5f38, (q15_t)0xaa76, (q15_t)0x5f34, (q15_t)0xaa71, (q15_t)0x5f2f, (q15_t)0xaa6d, + (q15_t)0x5f2b, (q15_t)0xaa68, (q15_t)0x5f27, (q15_t)0xaa63, (q15_t)0x5f23, (q15_t)0xaa5f, (q15_t)0x5f1f, (q15_t)0xaa5a, + (q15_t)0x5f1a, (q15_t)0xaa55, (q15_t)0x5f16, (q15_t)0xaa51, (q15_t)0x5f12, (q15_t)0xaa4c, (q15_t)0x5f0e, (q15_t)0xaa47, + (q15_t)0x5f0a, (q15_t)0xaa43, (q15_t)0x5f05, (q15_t)0xaa3e, (q15_t)0x5f01, (q15_t)0xaa39, (q15_t)0x5efd, (q15_t)0xaa35, + (q15_t)0x5ef9, (q15_t)0xaa30, (q15_t)0x5ef5, (q15_t)0xaa2b, (q15_t)0x5ef0, (q15_t)0xaa27, (q15_t)0x5eec, (q15_t)0xaa22, + (q15_t)0x5ee8, (q15_t)0xaa1d, (q15_t)0x5ee4, (q15_t)0xaa19, (q15_t)0x5edf, (q15_t)0xaa14, (q15_t)0x5edb, (q15_t)0xaa10, + (q15_t)0x5ed7, (q15_t)0xaa0b, (q15_t)0x5ed3, (q15_t)0xaa06, (q15_t)0x5ecf, (q15_t)0xaa02, (q15_t)0x5eca, (q15_t)0xa9fd, + (q15_t)0x5ec6, (q15_t)0xa9f8, (q15_t)0x5ec2, (q15_t)0xa9f4, (q15_t)0x5ebe, (q15_t)0xa9ef, (q15_t)0x5eb9, (q15_t)0xa9ea, + (q15_t)0x5eb5, (q15_t)0xa9e6, (q15_t)0x5eb1, (q15_t)0xa9e1, (q15_t)0x5ead, (q15_t)0xa9dc, (q15_t)0x5ea9, (q15_t)0xa9d8, + (q15_t)0x5ea4, (q15_t)0xa9d3, (q15_t)0x5ea0, (q15_t)0xa9ce, (q15_t)0x5e9c, (q15_t)0xa9ca, (q15_t)0x5e98, (q15_t)0xa9c5, + (q15_t)0x5e93, (q15_t)0xa9c0, (q15_t)0x5e8f, (q15_t)0xa9bc, (q15_t)0x5e8b, (q15_t)0xa9b7, (q15_t)0x5e87, (q15_t)0xa9b3, + (q15_t)0x5e82, (q15_t)0xa9ae, (q15_t)0x5e7e, (q15_t)0xa9a9, (q15_t)0x5e7a, (q15_t)0xa9a5, (q15_t)0x5e76, (q15_t)0xa9a0, + (q15_t)0x5e71, (q15_t)0xa99b, (q15_t)0x5e6d, (q15_t)0xa997, (q15_t)0x5e69, (q15_t)0xa992, (q15_t)0x5e65, (q15_t)0xa98d, + (q15_t)0x5e60, (q15_t)0xa989, (q15_t)0x5e5c, (q15_t)0xa984, (q15_t)0x5e58, (q15_t)0xa980, (q15_t)0x5e54, (q15_t)0xa97b, + (q15_t)0x5e50, (q15_t)0xa976, (q15_t)0x5e4b, (q15_t)0xa972, (q15_t)0x5e47, (q15_t)0xa96d, (q15_t)0x5e43, (q15_t)0xa968, + (q15_t)0x5e3f, (q15_t)0xa964, (q15_t)0x5e3a, (q15_t)0xa95f, (q15_t)0x5e36, (q15_t)0xa95b, (q15_t)0x5e32, (q15_t)0xa956, + (q15_t)0x5e2d, (q15_t)0xa951, (q15_t)0x5e29, (q15_t)0xa94d, (q15_t)0x5e25, (q15_t)0xa948, (q15_t)0x5e21, (q15_t)0xa943, + (q15_t)0x5e1c, (q15_t)0xa93f, (q15_t)0x5e18, (q15_t)0xa93a, (q15_t)0x5e14, (q15_t)0xa936, (q15_t)0x5e10, (q15_t)0xa931, + (q15_t)0x5e0b, (q15_t)0xa92c, (q15_t)0x5e07, (q15_t)0xa928, (q15_t)0x5e03, (q15_t)0xa923, (q15_t)0x5dff, (q15_t)0xa91e, + (q15_t)0x5dfa, (q15_t)0xa91a, (q15_t)0x5df6, (q15_t)0xa915, (q15_t)0x5df2, (q15_t)0xa911, (q15_t)0x5dee, (q15_t)0xa90c, + (q15_t)0x5de9, (q15_t)0xa907, (q15_t)0x5de5, (q15_t)0xa903, (q15_t)0x5de1, (q15_t)0xa8fe, (q15_t)0x5ddc, (q15_t)0xa8fa, + (q15_t)0x5dd8, (q15_t)0xa8f5, (q15_t)0x5dd4, (q15_t)0xa8f0, (q15_t)0x5dd0, (q15_t)0xa8ec, (q15_t)0x5dcb, (q15_t)0xa8e7, + (q15_t)0x5dc7, (q15_t)0xa8e3, (q15_t)0x5dc3, (q15_t)0xa8de, (q15_t)0x5dbf, (q15_t)0xa8d9, (q15_t)0x5dba, (q15_t)0xa8d5, + (q15_t)0x5db6, (q15_t)0xa8d0, (q15_t)0x5db2, (q15_t)0xa8cc, (q15_t)0x5dad, (q15_t)0xa8c7, (q15_t)0x5da9, (q15_t)0xa8c2, + (q15_t)0x5da5, (q15_t)0xa8be, (q15_t)0x5da1, (q15_t)0xa8b9, (q15_t)0x5d9c, (q15_t)0xa8b5, (q15_t)0x5d98, (q15_t)0xa8b0, + (q15_t)0x5d94, (q15_t)0xa8ab, (q15_t)0x5d8f, (q15_t)0xa8a7, (q15_t)0x5d8b, (q15_t)0xa8a2, (q15_t)0x5d87, (q15_t)0xa89e, + (q15_t)0x5d83, (q15_t)0xa899, (q15_t)0x5d7e, (q15_t)0xa894, (q15_t)0x5d7a, (q15_t)0xa890, (q15_t)0x5d76, (q15_t)0xa88b, + (q15_t)0x5d71, (q15_t)0xa887, (q15_t)0x5d6d, (q15_t)0xa882, (q15_t)0x5d69, (q15_t)0xa87d, (q15_t)0x5d65, (q15_t)0xa879, + (q15_t)0x5d60, (q15_t)0xa874, (q15_t)0x5d5c, (q15_t)0xa870, (q15_t)0x5d58, (q15_t)0xa86b, (q15_t)0x5d53, (q15_t)0xa867, + (q15_t)0x5d4f, (q15_t)0xa862, (q15_t)0x5d4b, (q15_t)0xa85d, (q15_t)0x5d46, (q15_t)0xa859, (q15_t)0x5d42, (q15_t)0xa854, + (q15_t)0x5d3e, (q15_t)0xa850, (q15_t)0x5d3a, (q15_t)0xa84b, (q15_t)0x5d35, (q15_t)0xa847, (q15_t)0x5d31, (q15_t)0xa842, + (q15_t)0x5d2d, (q15_t)0xa83d, (q15_t)0x5d28, (q15_t)0xa839, (q15_t)0x5d24, (q15_t)0xa834, (q15_t)0x5d20, (q15_t)0xa830, + (q15_t)0x5d1b, (q15_t)0xa82b, (q15_t)0x5d17, (q15_t)0xa827, (q15_t)0x5d13, (q15_t)0xa822, (q15_t)0x5d0e, (q15_t)0xa81d, + (q15_t)0x5d0a, (q15_t)0xa819, (q15_t)0x5d06, (q15_t)0xa814, (q15_t)0x5d01, (q15_t)0xa810, (q15_t)0x5cfd, (q15_t)0xa80b, + (q15_t)0x5cf9, (q15_t)0xa807, (q15_t)0x5cf5, (q15_t)0xa802, (q15_t)0x5cf0, (q15_t)0xa7fd, (q15_t)0x5cec, (q15_t)0xa7f9, + (q15_t)0x5ce8, (q15_t)0xa7f4, (q15_t)0x5ce3, (q15_t)0xa7f0, (q15_t)0x5cdf, (q15_t)0xa7eb, (q15_t)0x5cdb, (q15_t)0xa7e7, + (q15_t)0x5cd6, (q15_t)0xa7e2, (q15_t)0x5cd2, (q15_t)0xa7de, (q15_t)0x5cce, (q15_t)0xa7d9, (q15_t)0x5cc9, (q15_t)0xa7d4, + (q15_t)0x5cc5, (q15_t)0xa7d0, (q15_t)0x5cc1, (q15_t)0xa7cb, (q15_t)0x5cbc, (q15_t)0xa7c7, (q15_t)0x5cb8, (q15_t)0xa7c2, + (q15_t)0x5cb4, (q15_t)0xa7be, (q15_t)0x5caf, (q15_t)0xa7b9, (q15_t)0x5cab, (q15_t)0xa7b5, (q15_t)0x5ca7, (q15_t)0xa7b0, + (q15_t)0x5ca2, (q15_t)0xa7ab, (q15_t)0x5c9e, (q15_t)0xa7a7, (q15_t)0x5c9a, (q15_t)0xa7a2, (q15_t)0x5c95, (q15_t)0xa79e, + (q15_t)0x5c91, (q15_t)0xa799, (q15_t)0x5c8d, (q15_t)0xa795, (q15_t)0x5c88, (q15_t)0xa790, (q15_t)0x5c84, (q15_t)0xa78c, + (q15_t)0x5c80, (q15_t)0xa787, (q15_t)0x5c7b, (q15_t)0xa783, (q15_t)0x5c77, (q15_t)0xa77e, (q15_t)0x5c73, (q15_t)0xa779, + (q15_t)0x5c6e, (q15_t)0xa775, (q15_t)0x5c6a, (q15_t)0xa770, (q15_t)0x5c66, (q15_t)0xa76c, (q15_t)0x5c61, (q15_t)0xa767, + (q15_t)0x5c5d, (q15_t)0xa763, (q15_t)0x5c58, (q15_t)0xa75e, (q15_t)0x5c54, (q15_t)0xa75a, (q15_t)0x5c50, (q15_t)0xa755, + (q15_t)0x5c4b, (q15_t)0xa751, (q15_t)0x5c47, (q15_t)0xa74c, (q15_t)0x5c43, (q15_t)0xa748, (q15_t)0x5c3e, (q15_t)0xa743, + (q15_t)0x5c3a, (q15_t)0xa73f, (q15_t)0x5c36, (q15_t)0xa73a, (q15_t)0x5c31, (q15_t)0xa735, (q15_t)0x5c2d, (q15_t)0xa731, + (q15_t)0x5c29, (q15_t)0xa72c, (q15_t)0x5c24, (q15_t)0xa728, (q15_t)0x5c20, (q15_t)0xa723, (q15_t)0x5c1b, (q15_t)0xa71f, + (q15_t)0x5c17, (q15_t)0xa71a, (q15_t)0x5c13, (q15_t)0xa716, (q15_t)0x5c0e, (q15_t)0xa711, (q15_t)0x5c0a, (q15_t)0xa70d, + (q15_t)0x5c06, (q15_t)0xa708, (q15_t)0x5c01, (q15_t)0xa704, (q15_t)0x5bfd, (q15_t)0xa6ff, (q15_t)0x5bf9, (q15_t)0xa6fb, + (q15_t)0x5bf4, (q15_t)0xa6f6, (q15_t)0x5bf0, (q15_t)0xa6f2, (q15_t)0x5beb, (q15_t)0xa6ed, (q15_t)0x5be7, (q15_t)0xa6e9, + (q15_t)0x5be3, (q15_t)0xa6e4, (q15_t)0x5bde, (q15_t)0xa6e0, (q15_t)0x5bda, (q15_t)0xa6db, (q15_t)0x5bd6, (q15_t)0xa6d7, + (q15_t)0x5bd1, (q15_t)0xa6d2, (q15_t)0x5bcd, (q15_t)0xa6ce, (q15_t)0x5bc8, (q15_t)0xa6c9, (q15_t)0x5bc4, (q15_t)0xa6c5, + (q15_t)0x5bc0, (q15_t)0xa6c0, (q15_t)0x5bbb, (q15_t)0xa6bc, (q15_t)0x5bb7, (q15_t)0xa6b7, (q15_t)0x5bb2, (q15_t)0xa6b3, + (q15_t)0x5bae, (q15_t)0xa6ae, (q15_t)0x5baa, (q15_t)0xa6aa, (q15_t)0x5ba5, (q15_t)0xa6a5, (q15_t)0x5ba1, (q15_t)0xa6a1, + (q15_t)0x5b9d, (q15_t)0xa69c, (q15_t)0x5b98, (q15_t)0xa698, (q15_t)0x5b94, (q15_t)0xa693, (q15_t)0x5b8f, (q15_t)0xa68f, + (q15_t)0x5b8b, (q15_t)0xa68a, (q15_t)0x5b87, (q15_t)0xa686, (q15_t)0x5b82, (q15_t)0xa681, (q15_t)0x5b7e, (q15_t)0xa67d, + (q15_t)0x5b79, (q15_t)0xa678, (q15_t)0x5b75, (q15_t)0xa674, (q15_t)0x5b71, (q15_t)0xa66f, (q15_t)0x5b6c, (q15_t)0xa66b, + (q15_t)0x5b68, (q15_t)0xa666, (q15_t)0x5b63, (q15_t)0xa662, (q15_t)0x5b5f, (q15_t)0xa65d, (q15_t)0x5b5b, (q15_t)0xa659, + (q15_t)0x5b56, (q15_t)0xa654, (q15_t)0x5b52, (q15_t)0xa650, (q15_t)0x5b4d, (q15_t)0xa64b, (q15_t)0x5b49, (q15_t)0xa647, + (q15_t)0x5b45, (q15_t)0xa642, (q15_t)0x5b40, (q15_t)0xa63e, (q15_t)0x5b3c, (q15_t)0xa639, (q15_t)0x5b37, (q15_t)0xa635, + (q15_t)0x5b33, (q15_t)0xa630, (q15_t)0x5b2f, (q15_t)0xa62c, (q15_t)0x5b2a, (q15_t)0xa627, (q15_t)0x5b26, (q15_t)0xa623, + (q15_t)0x5b21, (q15_t)0xa61f, (q15_t)0x5b1d, (q15_t)0xa61a, (q15_t)0x5b19, (q15_t)0xa616, (q15_t)0x5b14, (q15_t)0xa611, + (q15_t)0x5b10, (q15_t)0xa60d, (q15_t)0x5b0b, (q15_t)0xa608, (q15_t)0x5b07, (q15_t)0xa604, (q15_t)0x5b02, (q15_t)0xa5ff, + (q15_t)0x5afe, (q15_t)0xa5fb, (q15_t)0x5afa, (q15_t)0xa5f6, (q15_t)0x5af5, (q15_t)0xa5f2, (q15_t)0x5af1, (q15_t)0xa5ed, + (q15_t)0x5aec, (q15_t)0xa5e9, (q15_t)0x5ae8, (q15_t)0xa5e4, (q15_t)0x5ae4, (q15_t)0xa5e0, (q15_t)0x5adf, (q15_t)0xa5dc, + (q15_t)0x5adb, (q15_t)0xa5d7, (q15_t)0x5ad6, (q15_t)0xa5d3, (q15_t)0x5ad2, (q15_t)0xa5ce, (q15_t)0x5acd, (q15_t)0xa5ca, + (q15_t)0x5ac9, (q15_t)0xa5c5, (q15_t)0x5ac5, (q15_t)0xa5c1, (q15_t)0x5ac0, (q15_t)0xa5bc, (q15_t)0x5abc, (q15_t)0xa5b8, + (q15_t)0x5ab7, (q15_t)0xa5b3, (q15_t)0x5ab3, (q15_t)0xa5af, (q15_t)0x5aae, (q15_t)0xa5aa, (q15_t)0x5aaa, (q15_t)0xa5a6, + (q15_t)0x5aa5, (q15_t)0xa5a2, (q15_t)0x5aa1, (q15_t)0xa59d, (q15_t)0x5a9d, (q15_t)0xa599, (q15_t)0x5a98, (q15_t)0xa594, + (q15_t)0x5a94, (q15_t)0xa590, (q15_t)0x5a8f, (q15_t)0xa58b, (q15_t)0x5a8b, (q15_t)0xa587, (q15_t)0x5a86, (q15_t)0xa582, + (q15_t)0x5a82, (q15_t)0xa57e, (q15_t)0x5a7e, (q15_t)0xa57a, (q15_t)0x5a79, (q15_t)0xa575, (q15_t)0x5a75, (q15_t)0xa571, + (q15_t)0x5a70, (q15_t)0xa56c, (q15_t)0x5a6c, (q15_t)0xa568, (q15_t)0x5a67, (q15_t)0xa563, (q15_t)0x5a63, (q15_t)0xa55f, + (q15_t)0x5a5e, (q15_t)0xa55b, (q15_t)0x5a5a, (q15_t)0xa556, (q15_t)0x5a56, (q15_t)0xa552, (q15_t)0x5a51, (q15_t)0xa54d, + (q15_t)0x5a4d, (q15_t)0xa549, (q15_t)0x5a48, (q15_t)0xa544, (q15_t)0x5a44, (q15_t)0xa540, (q15_t)0x5a3f, (q15_t)0xa53b, + (q15_t)0x5a3b, (q15_t)0xa537, (q15_t)0x5a36, (q15_t)0xa533, (q15_t)0x5a32, (q15_t)0xa52e, (q15_t)0x5a2d, (q15_t)0xa52a, + (q15_t)0x5a29, (q15_t)0xa525, (q15_t)0x5a24, (q15_t)0xa521, (q15_t)0x5a20, (q15_t)0xa51c, (q15_t)0x5a1c, (q15_t)0xa518, + (q15_t)0x5a17, (q15_t)0xa514, (q15_t)0x5a13, (q15_t)0xa50f, (q15_t)0x5a0e, (q15_t)0xa50b, (q15_t)0x5a0a, (q15_t)0xa506, + (q15_t)0x5a05, (q15_t)0xa502, (q15_t)0x5a01, (q15_t)0xa4fe, (q15_t)0x59fc, (q15_t)0xa4f9, (q15_t)0x59f8, (q15_t)0xa4f5, + (q15_t)0x59f3, (q15_t)0xa4f0, (q15_t)0x59ef, (q15_t)0xa4ec, (q15_t)0x59ea, (q15_t)0xa4e7, (q15_t)0x59e6, (q15_t)0xa4e3, + (q15_t)0x59e1, (q15_t)0xa4df, (q15_t)0x59dd, (q15_t)0xa4da, (q15_t)0x59d9, (q15_t)0xa4d6, (q15_t)0x59d4, (q15_t)0xa4d1, + (q15_t)0x59d0, (q15_t)0xa4cd, (q15_t)0x59cb, (q15_t)0xa4c9, (q15_t)0x59c7, (q15_t)0xa4c4, (q15_t)0x59c2, (q15_t)0xa4c0, + (q15_t)0x59be, (q15_t)0xa4bb, (q15_t)0x59b9, (q15_t)0xa4b7, (q15_t)0x59b5, (q15_t)0xa4b3, (q15_t)0x59b0, (q15_t)0xa4ae, + (q15_t)0x59ac, (q15_t)0xa4aa, (q15_t)0x59a7, (q15_t)0xa4a5, (q15_t)0x59a3, (q15_t)0xa4a1, (q15_t)0x599e, (q15_t)0xa49d, + (q15_t)0x599a, (q15_t)0xa498, (q15_t)0x5995, (q15_t)0xa494, (q15_t)0x5991, (q15_t)0xa48f, (q15_t)0x598c, (q15_t)0xa48b, + (q15_t)0x5988, (q15_t)0xa487, (q15_t)0x5983, (q15_t)0xa482, (q15_t)0x597f, (q15_t)0xa47e, (q15_t)0x597a, (q15_t)0xa479, + (q15_t)0x5976, (q15_t)0xa475, (q15_t)0x5971, (q15_t)0xa471, (q15_t)0x596d, (q15_t)0xa46c, (q15_t)0x5968, (q15_t)0xa468, + (q15_t)0x5964, (q15_t)0xa463, (q15_t)0x595f, (q15_t)0xa45f, (q15_t)0x595b, (q15_t)0xa45b, (q15_t)0x5956, (q15_t)0xa456, + (q15_t)0x5952, (q15_t)0xa452, (q15_t)0x594d, (q15_t)0xa44e, (q15_t)0x5949, (q15_t)0xa449, (q15_t)0x5944, (q15_t)0xa445, + (q15_t)0x5940, (q15_t)0xa440, (q15_t)0x593b, (q15_t)0xa43c, (q15_t)0x5937, (q15_t)0xa438, (q15_t)0x5932, (q15_t)0xa433, + (q15_t)0x592e, (q15_t)0xa42f, (q15_t)0x5929, (q15_t)0xa42a, (q15_t)0x5925, (q15_t)0xa426, (q15_t)0x5920, (q15_t)0xa422, + (q15_t)0x591c, (q15_t)0xa41d, (q15_t)0x5917, (q15_t)0xa419, (q15_t)0x5913, (q15_t)0xa415, (q15_t)0x590e, (q15_t)0xa410, + (q15_t)0x590a, (q15_t)0xa40c, (q15_t)0x5905, (q15_t)0xa407, (q15_t)0x5901, (q15_t)0xa403, (q15_t)0x58fc, (q15_t)0xa3ff, + (q15_t)0x58f8, (q15_t)0xa3fa, (q15_t)0x58f3, (q15_t)0xa3f6, (q15_t)0x58ef, (q15_t)0xa3f2, (q15_t)0x58ea, (q15_t)0xa3ed, + (q15_t)0x58e6, (q15_t)0xa3e9, (q15_t)0x58e1, (q15_t)0xa3e5, (q15_t)0x58dd, (q15_t)0xa3e0, (q15_t)0x58d8, (q15_t)0xa3dc, + (q15_t)0x58d4, (q15_t)0xa3d7, (q15_t)0x58cf, (q15_t)0xa3d3, (q15_t)0x58cb, (q15_t)0xa3cf, (q15_t)0x58c6, (q15_t)0xa3ca, + (q15_t)0x58c1, (q15_t)0xa3c6, (q15_t)0x58bd, (q15_t)0xa3c2, (q15_t)0x58b8, (q15_t)0xa3bd, (q15_t)0x58b4, (q15_t)0xa3b9, + (q15_t)0x58af, (q15_t)0xa3b5, (q15_t)0x58ab, (q15_t)0xa3b0, (q15_t)0x58a6, (q15_t)0xa3ac, (q15_t)0x58a2, (q15_t)0xa3a8, + (q15_t)0x589d, (q15_t)0xa3a3, (q15_t)0x5899, (q15_t)0xa39f, (q15_t)0x5894, (q15_t)0xa39a, (q15_t)0x5890, (q15_t)0xa396, + (q15_t)0x588b, (q15_t)0xa392, (q15_t)0x5887, (q15_t)0xa38d, (q15_t)0x5882, (q15_t)0xa389, (q15_t)0x587d, (q15_t)0xa385, + (q15_t)0x5879, (q15_t)0xa380, (q15_t)0x5874, (q15_t)0xa37c, (q15_t)0x5870, (q15_t)0xa378, (q15_t)0x586b, (q15_t)0xa373, + (q15_t)0x5867, (q15_t)0xa36f, (q15_t)0x5862, (q15_t)0xa36b, (q15_t)0x585e, (q15_t)0xa366, (q15_t)0x5859, (q15_t)0xa362, + (q15_t)0x5855, (q15_t)0xa35e, (q15_t)0x5850, (q15_t)0xa359, (q15_t)0x584b, (q15_t)0xa355, (q15_t)0x5847, (q15_t)0xa351, + (q15_t)0x5842, (q15_t)0xa34c, (q15_t)0x583e, (q15_t)0xa348, (q15_t)0x5839, (q15_t)0xa344, (q15_t)0x5835, (q15_t)0xa33f, + (q15_t)0x5830, (q15_t)0xa33b, (q15_t)0x582c, (q15_t)0xa337, (q15_t)0x5827, (q15_t)0xa332, (q15_t)0x5822, (q15_t)0xa32e, + (q15_t)0x581e, (q15_t)0xa32a, (q15_t)0x5819, (q15_t)0xa325, (q15_t)0x5815, (q15_t)0xa321, (q15_t)0x5810, (q15_t)0xa31d, + (q15_t)0x580c, (q15_t)0xa318, (q15_t)0x5807, (q15_t)0xa314, (q15_t)0x5803, (q15_t)0xa310, (q15_t)0x57fe, (q15_t)0xa30b, + (q15_t)0x57f9, (q15_t)0xa307, (q15_t)0x57f5, (q15_t)0xa303, (q15_t)0x57f0, (q15_t)0xa2ff, (q15_t)0x57ec, (q15_t)0xa2fa, + (q15_t)0x57e7, (q15_t)0xa2f6, (q15_t)0x57e3, (q15_t)0xa2f2, (q15_t)0x57de, (q15_t)0xa2ed, (q15_t)0x57d9, (q15_t)0xa2e9, + (q15_t)0x57d5, (q15_t)0xa2e5, (q15_t)0x57d0, (q15_t)0xa2e0, (q15_t)0x57cc, (q15_t)0xa2dc, (q15_t)0x57c7, (q15_t)0xa2d8, + (q15_t)0x57c3, (q15_t)0xa2d3, (q15_t)0x57be, (q15_t)0xa2cf, (q15_t)0x57b9, (q15_t)0xa2cb, (q15_t)0x57b5, (q15_t)0xa2c6, + (q15_t)0x57b0, (q15_t)0xa2c2, (q15_t)0x57ac, (q15_t)0xa2be, (q15_t)0x57a7, (q15_t)0xa2ba, (q15_t)0x57a3, (q15_t)0xa2b5, + (q15_t)0x579e, (q15_t)0xa2b1, (q15_t)0x5799, (q15_t)0xa2ad, (q15_t)0x5795, (q15_t)0xa2a8, (q15_t)0x5790, (q15_t)0xa2a4, + (q15_t)0x578c, (q15_t)0xa2a0, (q15_t)0x5787, (q15_t)0xa29b, (q15_t)0x5783, (q15_t)0xa297, (q15_t)0x577e, (q15_t)0xa293, + (q15_t)0x5779, (q15_t)0xa28f, (q15_t)0x5775, (q15_t)0xa28a, (q15_t)0x5770, (q15_t)0xa286, (q15_t)0x576c, (q15_t)0xa282, + (q15_t)0x5767, (q15_t)0xa27d, (q15_t)0x5762, (q15_t)0xa279, (q15_t)0x575e, (q15_t)0xa275, (q15_t)0x5759, (q15_t)0xa271, + (q15_t)0x5755, (q15_t)0xa26c, (q15_t)0x5750, (q15_t)0xa268, (q15_t)0x574b, (q15_t)0xa264, (q15_t)0x5747, (q15_t)0xa25f, + (q15_t)0x5742, (q15_t)0xa25b, (q15_t)0x573e, (q15_t)0xa257, (q15_t)0x5739, (q15_t)0xa253, (q15_t)0x5734, (q15_t)0xa24e, + (q15_t)0x5730, (q15_t)0xa24a, (q15_t)0x572b, (q15_t)0xa246, (q15_t)0x5727, (q15_t)0xa241, (q15_t)0x5722, (q15_t)0xa23d, + (q15_t)0x571d, (q15_t)0xa239, (q15_t)0x5719, (q15_t)0xa235, (q15_t)0x5714, (q15_t)0xa230, (q15_t)0x5710, (q15_t)0xa22c, + (q15_t)0x570b, (q15_t)0xa228, (q15_t)0x5706, (q15_t)0xa224, (q15_t)0x5702, (q15_t)0xa21f, (q15_t)0x56fd, (q15_t)0xa21b, + (q15_t)0x56f9, (q15_t)0xa217, (q15_t)0x56f4, (q15_t)0xa212, (q15_t)0x56ef, (q15_t)0xa20e, (q15_t)0x56eb, (q15_t)0xa20a, + (q15_t)0x56e6, (q15_t)0xa206, (q15_t)0x56e2, (q15_t)0xa201, (q15_t)0x56dd, (q15_t)0xa1fd, (q15_t)0x56d8, (q15_t)0xa1f9, + (q15_t)0x56d4, (q15_t)0xa1f5, (q15_t)0x56cf, (q15_t)0xa1f0, (q15_t)0x56ca, (q15_t)0xa1ec, (q15_t)0x56c6, (q15_t)0xa1e8, + (q15_t)0x56c1, (q15_t)0xa1e4, (q15_t)0x56bd, (q15_t)0xa1df, (q15_t)0x56b8, (q15_t)0xa1db, (q15_t)0x56b3, (q15_t)0xa1d7, + (q15_t)0x56af, (q15_t)0xa1d3, (q15_t)0x56aa, (q15_t)0xa1ce, (q15_t)0x56a5, (q15_t)0xa1ca, (q15_t)0x56a1, (q15_t)0xa1c6, + (q15_t)0x569c, (q15_t)0xa1c1, (q15_t)0x5698, (q15_t)0xa1bd, (q15_t)0x5693, (q15_t)0xa1b9, (q15_t)0x568e, (q15_t)0xa1b5, + (q15_t)0x568a, (q15_t)0xa1b0, (q15_t)0x5685, (q15_t)0xa1ac, (q15_t)0x5680, (q15_t)0xa1a8, (q15_t)0x567c, (q15_t)0xa1a4, + (q15_t)0x5677, (q15_t)0xa1a0, (q15_t)0x5673, (q15_t)0xa19b, (q15_t)0x566e, (q15_t)0xa197, (q15_t)0x5669, (q15_t)0xa193, + (q15_t)0x5665, (q15_t)0xa18f, (q15_t)0x5660, (q15_t)0xa18a, (q15_t)0x565b, (q15_t)0xa186, (q15_t)0x5657, (q15_t)0xa182, + (q15_t)0x5652, (q15_t)0xa17e, (q15_t)0x564d, (q15_t)0xa179, (q15_t)0x5649, (q15_t)0xa175, (q15_t)0x5644, (q15_t)0xa171, + (q15_t)0x5640, (q15_t)0xa16d, (q15_t)0x563b, (q15_t)0xa168, (q15_t)0x5636, (q15_t)0xa164, (q15_t)0x5632, (q15_t)0xa160, + (q15_t)0x562d, (q15_t)0xa15c, (q15_t)0x5628, (q15_t)0xa157, (q15_t)0x5624, (q15_t)0xa153, (q15_t)0x561f, (q15_t)0xa14f, + (q15_t)0x561a, (q15_t)0xa14b, (q15_t)0x5616, (q15_t)0xa147, (q15_t)0x5611, (q15_t)0xa142, (q15_t)0x560c, (q15_t)0xa13e, + (q15_t)0x5608, (q15_t)0xa13a, (q15_t)0x5603, (q15_t)0xa136, (q15_t)0x55fe, (q15_t)0xa131, (q15_t)0x55fa, (q15_t)0xa12d, + (q15_t)0x55f5, (q15_t)0xa129, (q15_t)0x55f0, (q15_t)0xa125, (q15_t)0x55ec, (q15_t)0xa121, (q15_t)0x55e7, (q15_t)0xa11c, + (q15_t)0x55e3, (q15_t)0xa118, (q15_t)0x55de, (q15_t)0xa114, (q15_t)0x55d9, (q15_t)0xa110, (q15_t)0x55d5, (q15_t)0xa10b, + (q15_t)0x55d0, (q15_t)0xa107, (q15_t)0x55cb, (q15_t)0xa103, (q15_t)0x55c7, (q15_t)0xa0ff, (q15_t)0x55c2, (q15_t)0xa0fb, + (q15_t)0x55bd, (q15_t)0xa0f6, (q15_t)0x55b9, (q15_t)0xa0f2, (q15_t)0x55b4, (q15_t)0xa0ee, (q15_t)0x55af, (q15_t)0xa0ea, + (q15_t)0x55ab, (q15_t)0xa0e6, (q15_t)0x55a6, (q15_t)0xa0e1, (q15_t)0x55a1, (q15_t)0xa0dd, (q15_t)0x559d, (q15_t)0xa0d9, + (q15_t)0x5598, (q15_t)0xa0d5, (q15_t)0x5593, (q15_t)0xa0d1, (q15_t)0x558f, (q15_t)0xa0cc, (q15_t)0x558a, (q15_t)0xa0c8, + (q15_t)0x5585, (q15_t)0xa0c4, (q15_t)0x5581, (q15_t)0xa0c0, (q15_t)0x557c, (q15_t)0xa0bc, (q15_t)0x5577, (q15_t)0xa0b7, + (q15_t)0x5572, (q15_t)0xa0b3, (q15_t)0x556e, (q15_t)0xa0af, (q15_t)0x5569, (q15_t)0xa0ab, (q15_t)0x5564, (q15_t)0xa0a7, + (q15_t)0x5560, (q15_t)0xa0a2, (q15_t)0x555b, (q15_t)0xa09e, (q15_t)0x5556, (q15_t)0xa09a, (q15_t)0x5552, (q15_t)0xa096, + (q15_t)0x554d, (q15_t)0xa092, (q15_t)0x5548, (q15_t)0xa08e, (q15_t)0x5544, (q15_t)0xa089, (q15_t)0x553f, (q15_t)0xa085, + (q15_t)0x553a, (q15_t)0xa081, (q15_t)0x5536, (q15_t)0xa07d, (q15_t)0x5531, (q15_t)0xa079, (q15_t)0x552c, (q15_t)0xa074, + (q15_t)0x5528, (q15_t)0xa070, (q15_t)0x5523, (q15_t)0xa06c, (q15_t)0x551e, (q15_t)0xa068, (q15_t)0x5519, (q15_t)0xa064, + (q15_t)0x5515, (q15_t)0xa060, (q15_t)0x5510, (q15_t)0xa05b, (q15_t)0x550b, (q15_t)0xa057, (q15_t)0x5507, (q15_t)0xa053, + (q15_t)0x5502, (q15_t)0xa04f, (q15_t)0x54fd, (q15_t)0xa04b, (q15_t)0x54f9, (q15_t)0xa046, (q15_t)0x54f4, (q15_t)0xa042, + (q15_t)0x54ef, (q15_t)0xa03e, (q15_t)0x54ea, (q15_t)0xa03a, (q15_t)0x54e6, (q15_t)0xa036, (q15_t)0x54e1, (q15_t)0xa032, + (q15_t)0x54dc, (q15_t)0xa02d, (q15_t)0x54d8, (q15_t)0xa029, (q15_t)0x54d3, (q15_t)0xa025, (q15_t)0x54ce, (q15_t)0xa021, + (q15_t)0x54ca, (q15_t)0xa01d, (q15_t)0x54c5, (q15_t)0xa019, (q15_t)0x54c0, (q15_t)0xa014, (q15_t)0x54bb, (q15_t)0xa010, + (q15_t)0x54b7, (q15_t)0xa00c, (q15_t)0x54b2, (q15_t)0xa008, (q15_t)0x54ad, (q15_t)0xa004, (q15_t)0x54a9, (q15_t)0xa000, + (q15_t)0x54a4, (q15_t)0x9ffc, (q15_t)0x549f, (q15_t)0x9ff7, (q15_t)0x549a, (q15_t)0x9ff3, (q15_t)0x5496, (q15_t)0x9fef, + (q15_t)0x5491, (q15_t)0x9feb, (q15_t)0x548c, (q15_t)0x9fe7, (q15_t)0x5488, (q15_t)0x9fe3, (q15_t)0x5483, (q15_t)0x9fde, + (q15_t)0x547e, (q15_t)0x9fda, (q15_t)0x5479, (q15_t)0x9fd6, (q15_t)0x5475, (q15_t)0x9fd2, (q15_t)0x5470, (q15_t)0x9fce, + (q15_t)0x546b, (q15_t)0x9fca, (q15_t)0x5467, (q15_t)0x9fc6, (q15_t)0x5462, (q15_t)0x9fc1, (q15_t)0x545d, (q15_t)0x9fbd, + (q15_t)0x5458, (q15_t)0x9fb9, (q15_t)0x5454, (q15_t)0x9fb5, (q15_t)0x544f, (q15_t)0x9fb1, (q15_t)0x544a, (q15_t)0x9fad, + (q15_t)0x5445, (q15_t)0x9fa9, (q15_t)0x5441, (q15_t)0x9fa4, (q15_t)0x543c, (q15_t)0x9fa0, (q15_t)0x5437, (q15_t)0x9f9c, + (q15_t)0x5433, (q15_t)0x9f98, (q15_t)0x542e, (q15_t)0x9f94, (q15_t)0x5429, (q15_t)0x9f90, (q15_t)0x5424, (q15_t)0x9f8c, + (q15_t)0x5420, (q15_t)0x9f88, (q15_t)0x541b, (q15_t)0x9f83, (q15_t)0x5416, (q15_t)0x9f7f, (q15_t)0x5411, (q15_t)0x9f7b, + (q15_t)0x540d, (q15_t)0x9f77, (q15_t)0x5408, (q15_t)0x9f73, (q15_t)0x5403, (q15_t)0x9f6f, (q15_t)0x53fe, (q15_t)0x9f6b, + (q15_t)0x53fa, (q15_t)0x9f67, (q15_t)0x53f5, (q15_t)0x9f62, (q15_t)0x53f0, (q15_t)0x9f5e, (q15_t)0x53eb, (q15_t)0x9f5a, + (q15_t)0x53e7, (q15_t)0x9f56, (q15_t)0x53e2, (q15_t)0x9f52, (q15_t)0x53dd, (q15_t)0x9f4e, (q15_t)0x53d8, (q15_t)0x9f4a, + (q15_t)0x53d4, (q15_t)0x9f46, (q15_t)0x53cf, (q15_t)0x9f41, (q15_t)0x53ca, (q15_t)0x9f3d, (q15_t)0x53c5, (q15_t)0x9f39, + (q15_t)0x53c1, (q15_t)0x9f35, (q15_t)0x53bc, (q15_t)0x9f31, (q15_t)0x53b7, (q15_t)0x9f2d, (q15_t)0x53b2, (q15_t)0x9f29, + (q15_t)0x53ae, (q15_t)0x9f25, (q15_t)0x53a9, (q15_t)0x9f21, (q15_t)0x53a4, (q15_t)0x9f1c, (q15_t)0x539f, (q15_t)0x9f18, + (q15_t)0x539b, (q15_t)0x9f14, (q15_t)0x5396, (q15_t)0x9f10, (q15_t)0x5391, (q15_t)0x9f0c, (q15_t)0x538c, (q15_t)0x9f08, + (q15_t)0x5388, (q15_t)0x9f04, (q15_t)0x5383, (q15_t)0x9f00, (q15_t)0x537e, (q15_t)0x9efc, (q15_t)0x5379, (q15_t)0x9ef8, + (q15_t)0x5375, (q15_t)0x9ef3, (q15_t)0x5370, (q15_t)0x9eef, (q15_t)0x536b, (q15_t)0x9eeb, (q15_t)0x5366, (q15_t)0x9ee7, + (q15_t)0x5362, (q15_t)0x9ee3, (q15_t)0x535d, (q15_t)0x9edf, (q15_t)0x5358, (q15_t)0x9edb, (q15_t)0x5353, (q15_t)0x9ed7, + (q15_t)0x534e, (q15_t)0x9ed3, (q15_t)0x534a, (q15_t)0x9ecf, (q15_t)0x5345, (q15_t)0x9ecb, (q15_t)0x5340, (q15_t)0x9ec6, + (q15_t)0x533b, (q15_t)0x9ec2, (q15_t)0x5337, (q15_t)0x9ebe, (q15_t)0x5332, (q15_t)0x9eba, (q15_t)0x532d, (q15_t)0x9eb6, + (q15_t)0x5328, (q15_t)0x9eb2, (q15_t)0x5323, (q15_t)0x9eae, (q15_t)0x531f, (q15_t)0x9eaa, (q15_t)0x531a, (q15_t)0x9ea6, + (q15_t)0x5315, (q15_t)0x9ea2, (q15_t)0x5310, (q15_t)0x9e9e, (q15_t)0x530c, (q15_t)0x9e9a, (q15_t)0x5307, (q15_t)0x9e95, + (q15_t)0x5302, (q15_t)0x9e91, (q15_t)0x52fd, (q15_t)0x9e8d, (q15_t)0x52f8, (q15_t)0x9e89, (q15_t)0x52f4, (q15_t)0x9e85, + (q15_t)0x52ef, (q15_t)0x9e81, (q15_t)0x52ea, (q15_t)0x9e7d, (q15_t)0x52e5, (q15_t)0x9e79, (q15_t)0x52e1, (q15_t)0x9e75, + (q15_t)0x52dc, (q15_t)0x9e71, (q15_t)0x52d7, (q15_t)0x9e6d, (q15_t)0x52d2, (q15_t)0x9e69, (q15_t)0x52cd, (q15_t)0x9e65, + (q15_t)0x52c9, (q15_t)0x9e61, (q15_t)0x52c4, (q15_t)0x9e5d, (q15_t)0x52bf, (q15_t)0x9e58, (q15_t)0x52ba, (q15_t)0x9e54, + (q15_t)0x52b5, (q15_t)0x9e50, (q15_t)0x52b1, (q15_t)0x9e4c, (q15_t)0x52ac, (q15_t)0x9e48, (q15_t)0x52a7, (q15_t)0x9e44, + (q15_t)0x52a2, (q15_t)0x9e40, (q15_t)0x529d, (q15_t)0x9e3c, (q15_t)0x5299, (q15_t)0x9e38, (q15_t)0x5294, (q15_t)0x9e34, + (q15_t)0x528f, (q15_t)0x9e30, (q15_t)0x528a, (q15_t)0x9e2c, (q15_t)0x5285, (q15_t)0x9e28, (q15_t)0x5281, (q15_t)0x9e24, + (q15_t)0x527c, (q15_t)0x9e20, (q15_t)0x5277, (q15_t)0x9e1c, (q15_t)0x5272, (q15_t)0x9e18, (q15_t)0x526d, (q15_t)0x9e14, + (q15_t)0x5269, (q15_t)0x9e0f, (q15_t)0x5264, (q15_t)0x9e0b, (q15_t)0x525f, (q15_t)0x9e07, (q15_t)0x525a, (q15_t)0x9e03, + (q15_t)0x5255, (q15_t)0x9dff, (q15_t)0x5251, (q15_t)0x9dfb, (q15_t)0x524c, (q15_t)0x9df7, (q15_t)0x5247, (q15_t)0x9df3, + (q15_t)0x5242, (q15_t)0x9def, (q15_t)0x523d, (q15_t)0x9deb, (q15_t)0x5238, (q15_t)0x9de7, (q15_t)0x5234, (q15_t)0x9de3, + (q15_t)0x522f, (q15_t)0x9ddf, (q15_t)0x522a, (q15_t)0x9ddb, (q15_t)0x5225, (q15_t)0x9dd7, (q15_t)0x5220, (q15_t)0x9dd3, + (q15_t)0x521c, (q15_t)0x9dcf, (q15_t)0x5217, (q15_t)0x9dcb, (q15_t)0x5212, (q15_t)0x9dc7, (q15_t)0x520d, (q15_t)0x9dc3, + (q15_t)0x5208, (q15_t)0x9dbf, (q15_t)0x5203, (q15_t)0x9dbb, (q15_t)0x51ff, (q15_t)0x9db7, (q15_t)0x51fa, (q15_t)0x9db3, + (q15_t)0x51f5, (q15_t)0x9daf, (q15_t)0x51f0, (q15_t)0x9dab, (q15_t)0x51eb, (q15_t)0x9da7, (q15_t)0x51e6, (q15_t)0x9da3, + (q15_t)0x51e2, (q15_t)0x9d9f, (q15_t)0x51dd, (q15_t)0x9d9b, (q15_t)0x51d8, (q15_t)0x9d97, (q15_t)0x51d3, (q15_t)0x9d93, + (q15_t)0x51ce, (q15_t)0x9d8f, (q15_t)0x51c9, (q15_t)0x9d8b, (q15_t)0x51c5, (q15_t)0x9d86, (q15_t)0x51c0, (q15_t)0x9d82, + (q15_t)0x51bb, (q15_t)0x9d7e, (q15_t)0x51b6, (q15_t)0x9d7a, (q15_t)0x51b1, (q15_t)0x9d76, (q15_t)0x51ac, (q15_t)0x9d72, + (q15_t)0x51a8, (q15_t)0x9d6e, (q15_t)0x51a3, (q15_t)0x9d6a, (q15_t)0x519e, (q15_t)0x9d66, (q15_t)0x5199, (q15_t)0x9d62, + (q15_t)0x5194, (q15_t)0x9d5e, (q15_t)0x518f, (q15_t)0x9d5a, (q15_t)0x518b, (q15_t)0x9d56, (q15_t)0x5186, (q15_t)0x9d52, + (q15_t)0x5181, (q15_t)0x9d4e, (q15_t)0x517c, (q15_t)0x9d4a, (q15_t)0x5177, (q15_t)0x9d46, (q15_t)0x5172, (q15_t)0x9d42, + (q15_t)0x516e, (q15_t)0x9d3e, (q15_t)0x5169, (q15_t)0x9d3a, (q15_t)0x5164, (q15_t)0x9d36, (q15_t)0x515f, (q15_t)0x9d32, + (q15_t)0x515a, (q15_t)0x9d2e, (q15_t)0x5155, (q15_t)0x9d2a, (q15_t)0x5150, (q15_t)0x9d26, (q15_t)0x514c, (q15_t)0x9d22, + (q15_t)0x5147, (q15_t)0x9d1e, (q15_t)0x5142, (q15_t)0x9d1a, (q15_t)0x513d, (q15_t)0x9d16, (q15_t)0x5138, (q15_t)0x9d12, + (q15_t)0x5133, (q15_t)0x9d0e, (q15_t)0x512e, (q15_t)0x9d0b, (q15_t)0x512a, (q15_t)0x9d07, (q15_t)0x5125, (q15_t)0x9d03, + (q15_t)0x5120, (q15_t)0x9cff, (q15_t)0x511b, (q15_t)0x9cfb, (q15_t)0x5116, (q15_t)0x9cf7, (q15_t)0x5111, (q15_t)0x9cf3, + (q15_t)0x510c, (q15_t)0x9cef, (q15_t)0x5108, (q15_t)0x9ceb, (q15_t)0x5103, (q15_t)0x9ce7, (q15_t)0x50fe, (q15_t)0x9ce3, + (q15_t)0x50f9, (q15_t)0x9cdf, (q15_t)0x50f4, (q15_t)0x9cdb, (q15_t)0x50ef, (q15_t)0x9cd7, (q15_t)0x50ea, (q15_t)0x9cd3, + (q15_t)0x50e5, (q15_t)0x9ccf, (q15_t)0x50e1, (q15_t)0x9ccb, (q15_t)0x50dc, (q15_t)0x9cc7, (q15_t)0x50d7, (q15_t)0x9cc3, + (q15_t)0x50d2, (q15_t)0x9cbf, (q15_t)0x50cd, (q15_t)0x9cbb, (q15_t)0x50c8, (q15_t)0x9cb7, (q15_t)0x50c3, (q15_t)0x9cb3, + (q15_t)0x50bf, (q15_t)0x9caf, (q15_t)0x50ba, (q15_t)0x9cab, (q15_t)0x50b5, (q15_t)0x9ca7, (q15_t)0x50b0, (q15_t)0x9ca3, + (q15_t)0x50ab, (q15_t)0x9c9f, (q15_t)0x50a6, (q15_t)0x9c9b, (q15_t)0x50a1, (q15_t)0x9c97, (q15_t)0x509c, (q15_t)0x9c93, + (q15_t)0x5097, (q15_t)0x9c8f, (q15_t)0x5093, (q15_t)0x9c8b, (q15_t)0x508e, (q15_t)0x9c88, (q15_t)0x5089, (q15_t)0x9c84, + (q15_t)0x5084, (q15_t)0x9c80, (q15_t)0x507f, (q15_t)0x9c7c, (q15_t)0x507a, (q15_t)0x9c78, (q15_t)0x5075, (q15_t)0x9c74, + (q15_t)0x5070, (q15_t)0x9c70, (q15_t)0x506c, (q15_t)0x9c6c, (q15_t)0x5067, (q15_t)0x9c68, (q15_t)0x5062, (q15_t)0x9c64, + (q15_t)0x505d, (q15_t)0x9c60, (q15_t)0x5058, (q15_t)0x9c5c, (q15_t)0x5053, (q15_t)0x9c58, (q15_t)0x504e, (q15_t)0x9c54, + (q15_t)0x5049, (q15_t)0x9c50, (q15_t)0x5044, (q15_t)0x9c4c, (q15_t)0x503f, (q15_t)0x9c48, (q15_t)0x503b, (q15_t)0x9c44, + (q15_t)0x5036, (q15_t)0x9c40, (q15_t)0x5031, (q15_t)0x9c3d, (q15_t)0x502c, (q15_t)0x9c39, (q15_t)0x5027, (q15_t)0x9c35, + (q15_t)0x5022, (q15_t)0x9c31, (q15_t)0x501d, (q15_t)0x9c2d, (q15_t)0x5018, (q15_t)0x9c29, (q15_t)0x5013, (q15_t)0x9c25, + (q15_t)0x500f, (q15_t)0x9c21, (q15_t)0x500a, (q15_t)0x9c1d, (q15_t)0x5005, (q15_t)0x9c19, (q15_t)0x5000, (q15_t)0x9c15, + (q15_t)0x4ffb, (q15_t)0x9c11, (q15_t)0x4ff6, (q15_t)0x9c0d, (q15_t)0x4ff1, (q15_t)0x9c09, (q15_t)0x4fec, (q15_t)0x9c06, + (q15_t)0x4fe7, (q15_t)0x9c02, (q15_t)0x4fe2, (q15_t)0x9bfe, (q15_t)0x4fdd, (q15_t)0x9bfa, (q15_t)0x4fd9, (q15_t)0x9bf6, + (q15_t)0x4fd4, (q15_t)0x9bf2, (q15_t)0x4fcf, (q15_t)0x9bee, (q15_t)0x4fca, (q15_t)0x9bea, (q15_t)0x4fc5, (q15_t)0x9be6, + (q15_t)0x4fc0, (q15_t)0x9be2, (q15_t)0x4fbb, (q15_t)0x9bde, (q15_t)0x4fb6, (q15_t)0x9bda, (q15_t)0x4fb1, (q15_t)0x9bd7, + (q15_t)0x4fac, (q15_t)0x9bd3, (q15_t)0x4fa7, (q15_t)0x9bcf, (q15_t)0x4fa2, (q15_t)0x9bcb, (q15_t)0x4f9e, (q15_t)0x9bc7, + (q15_t)0x4f99, (q15_t)0x9bc3, (q15_t)0x4f94, (q15_t)0x9bbf, (q15_t)0x4f8f, (q15_t)0x9bbb, (q15_t)0x4f8a, (q15_t)0x9bb7, + (q15_t)0x4f85, (q15_t)0x9bb3, (q15_t)0x4f80, (q15_t)0x9baf, (q15_t)0x4f7b, (q15_t)0x9bac, (q15_t)0x4f76, (q15_t)0x9ba8, + (q15_t)0x4f71, (q15_t)0x9ba4, (q15_t)0x4f6c, (q15_t)0x9ba0, (q15_t)0x4f67, (q15_t)0x9b9c, (q15_t)0x4f62, (q15_t)0x9b98, + (q15_t)0x4f5e, (q15_t)0x9b94, (q15_t)0x4f59, (q15_t)0x9b90, (q15_t)0x4f54, (q15_t)0x9b8c, (q15_t)0x4f4f, (q15_t)0x9b88, + (q15_t)0x4f4a, (q15_t)0x9b85, (q15_t)0x4f45, (q15_t)0x9b81, (q15_t)0x4f40, (q15_t)0x9b7d, (q15_t)0x4f3b, (q15_t)0x9b79, + (q15_t)0x4f36, (q15_t)0x9b75, (q15_t)0x4f31, (q15_t)0x9b71, (q15_t)0x4f2c, (q15_t)0x9b6d, (q15_t)0x4f27, (q15_t)0x9b69, + (q15_t)0x4f22, (q15_t)0x9b65, (q15_t)0x4f1d, (q15_t)0x9b62, (q15_t)0x4f18, (q15_t)0x9b5e, (q15_t)0x4f14, (q15_t)0x9b5a, + (q15_t)0x4f0f, (q15_t)0x9b56, (q15_t)0x4f0a, (q15_t)0x9b52, (q15_t)0x4f05, (q15_t)0x9b4e, (q15_t)0x4f00, (q15_t)0x9b4a, + (q15_t)0x4efb, (q15_t)0x9b46, (q15_t)0x4ef6, (q15_t)0x9b43, (q15_t)0x4ef1, (q15_t)0x9b3f, (q15_t)0x4eec, (q15_t)0x9b3b, + (q15_t)0x4ee7, (q15_t)0x9b37, (q15_t)0x4ee2, (q15_t)0x9b33, (q15_t)0x4edd, (q15_t)0x9b2f, (q15_t)0x4ed8, (q15_t)0x9b2b, + (q15_t)0x4ed3, (q15_t)0x9b27, (q15_t)0x4ece, (q15_t)0x9b24, (q15_t)0x4ec9, (q15_t)0x9b20, (q15_t)0x4ec4, (q15_t)0x9b1c, + (q15_t)0x4ebf, (q15_t)0x9b18, (q15_t)0x4eba, (q15_t)0x9b14, (q15_t)0x4eb6, (q15_t)0x9b10, (q15_t)0x4eb1, (q15_t)0x9b0c, + (q15_t)0x4eac, (q15_t)0x9b09, (q15_t)0x4ea7, (q15_t)0x9b05, (q15_t)0x4ea2, (q15_t)0x9b01, (q15_t)0x4e9d, (q15_t)0x9afd, + (q15_t)0x4e98, (q15_t)0x9af9, (q15_t)0x4e93, (q15_t)0x9af5, (q15_t)0x4e8e, (q15_t)0x9af1, (q15_t)0x4e89, (q15_t)0x9aed, + (q15_t)0x4e84, (q15_t)0x9aea, (q15_t)0x4e7f, (q15_t)0x9ae6, (q15_t)0x4e7a, (q15_t)0x9ae2, (q15_t)0x4e75, (q15_t)0x9ade, + (q15_t)0x4e70, (q15_t)0x9ada, (q15_t)0x4e6b, (q15_t)0x9ad6, (q15_t)0x4e66, (q15_t)0x9ad3, (q15_t)0x4e61, (q15_t)0x9acf, + (q15_t)0x4e5c, (q15_t)0x9acb, (q15_t)0x4e57, (q15_t)0x9ac7, (q15_t)0x4e52, (q15_t)0x9ac3, (q15_t)0x4e4d, (q15_t)0x9abf, + (q15_t)0x4e48, (q15_t)0x9abb, (q15_t)0x4e43, (q15_t)0x9ab8, (q15_t)0x4e3e, (q15_t)0x9ab4, (q15_t)0x4e39, (q15_t)0x9ab0, + (q15_t)0x4e34, (q15_t)0x9aac, (q15_t)0x4e2f, (q15_t)0x9aa8, (q15_t)0x4e2a, (q15_t)0x9aa4, (q15_t)0x4e26, (q15_t)0x9aa1, + (q15_t)0x4e21, (q15_t)0x9a9d, (q15_t)0x4e1c, (q15_t)0x9a99, (q15_t)0x4e17, (q15_t)0x9a95, (q15_t)0x4e12, (q15_t)0x9a91, + (q15_t)0x4e0d, (q15_t)0x9a8d, (q15_t)0x4e08, (q15_t)0x9a8a, (q15_t)0x4e03, (q15_t)0x9a86, (q15_t)0x4dfe, (q15_t)0x9a82, + (q15_t)0x4df9, (q15_t)0x9a7e, (q15_t)0x4df4, (q15_t)0x9a7a, (q15_t)0x4def, (q15_t)0x9a76, (q15_t)0x4dea, (q15_t)0x9a73, + (q15_t)0x4de5, (q15_t)0x9a6f, (q15_t)0x4de0, (q15_t)0x9a6b, (q15_t)0x4ddb, (q15_t)0x9a67, (q15_t)0x4dd6, (q15_t)0x9a63, + (q15_t)0x4dd1, (q15_t)0x9a60, (q15_t)0x4dcc, (q15_t)0x9a5c, (q15_t)0x4dc7, (q15_t)0x9a58, (q15_t)0x4dc2, (q15_t)0x9a54, + (q15_t)0x4dbd, (q15_t)0x9a50, (q15_t)0x4db8, (q15_t)0x9a4c, (q15_t)0x4db3, (q15_t)0x9a49, (q15_t)0x4dae, (q15_t)0x9a45, + (q15_t)0x4da9, (q15_t)0x9a41, (q15_t)0x4da4, (q15_t)0x9a3d, (q15_t)0x4d9f, (q15_t)0x9a39, (q15_t)0x4d9a, (q15_t)0x9a36, + (q15_t)0x4d95, (q15_t)0x9a32, (q15_t)0x4d90, (q15_t)0x9a2e, (q15_t)0x4d8b, (q15_t)0x9a2a, (q15_t)0x4d86, (q15_t)0x9a26, + (q15_t)0x4d81, (q15_t)0x9a23, (q15_t)0x4d7c, (q15_t)0x9a1f, (q15_t)0x4d77, (q15_t)0x9a1b, (q15_t)0x4d72, (q15_t)0x9a17, + (q15_t)0x4d6d, (q15_t)0x9a13, (q15_t)0x4d68, (q15_t)0x9a10, (q15_t)0x4d63, (q15_t)0x9a0c, (q15_t)0x4d5e, (q15_t)0x9a08, + (q15_t)0x4d59, (q15_t)0x9a04, (q15_t)0x4d54, (q15_t)0x9a00, (q15_t)0x4d4f, (q15_t)0x99fd, (q15_t)0x4d4a, (q15_t)0x99f9, + (q15_t)0x4d45, (q15_t)0x99f5, (q15_t)0x4d40, (q15_t)0x99f1, (q15_t)0x4d3b, (q15_t)0x99ed, (q15_t)0x4d36, (q15_t)0x99ea, + (q15_t)0x4d31, (q15_t)0x99e6, (q15_t)0x4d2c, (q15_t)0x99e2, (q15_t)0x4d27, (q15_t)0x99de, (q15_t)0x4d22, (q15_t)0x99da, + (q15_t)0x4d1d, (q15_t)0x99d7, (q15_t)0x4d18, (q15_t)0x99d3, (q15_t)0x4d13, (q15_t)0x99cf, (q15_t)0x4d0e, (q15_t)0x99cb, + (q15_t)0x4d09, (q15_t)0x99c7, (q15_t)0x4d04, (q15_t)0x99c4, (q15_t)0x4cff, (q15_t)0x99c0, (q15_t)0x4cfa, (q15_t)0x99bc, + (q15_t)0x4cf5, (q15_t)0x99b8, (q15_t)0x4cf0, (q15_t)0x99b5, (q15_t)0x4ceb, (q15_t)0x99b1, (q15_t)0x4ce6, (q15_t)0x99ad, + (q15_t)0x4ce1, (q15_t)0x99a9, (q15_t)0x4cdb, (q15_t)0x99a5, (q15_t)0x4cd6, (q15_t)0x99a2, (q15_t)0x4cd1, (q15_t)0x999e, + (q15_t)0x4ccc, (q15_t)0x999a, (q15_t)0x4cc7, (q15_t)0x9996, (q15_t)0x4cc2, (q15_t)0x9993, (q15_t)0x4cbd, (q15_t)0x998f, + (q15_t)0x4cb8, (q15_t)0x998b, (q15_t)0x4cb3, (q15_t)0x9987, (q15_t)0x4cae, (q15_t)0x9984, (q15_t)0x4ca9, (q15_t)0x9980, + (q15_t)0x4ca4, (q15_t)0x997c, (q15_t)0x4c9f, (q15_t)0x9978, (q15_t)0x4c9a, (q15_t)0x9975, (q15_t)0x4c95, (q15_t)0x9971, + (q15_t)0x4c90, (q15_t)0x996d, (q15_t)0x4c8b, (q15_t)0x9969, (q15_t)0x4c86, (q15_t)0x9965, (q15_t)0x4c81, (q15_t)0x9962, + (q15_t)0x4c7c, (q15_t)0x995e, (q15_t)0x4c77, (q15_t)0x995a, (q15_t)0x4c72, (q15_t)0x9956, (q15_t)0x4c6d, (q15_t)0x9953, + (q15_t)0x4c68, (q15_t)0x994f, (q15_t)0x4c63, (q15_t)0x994b, (q15_t)0x4c5e, (q15_t)0x9947, (q15_t)0x4c59, (q15_t)0x9944, + (q15_t)0x4c54, (q15_t)0x9940, (q15_t)0x4c4f, (q15_t)0x993c, (q15_t)0x4c49, (q15_t)0x9938, (q15_t)0x4c44, (q15_t)0x9935, + (q15_t)0x4c3f, (q15_t)0x9931, (q15_t)0x4c3a, (q15_t)0x992d, (q15_t)0x4c35, (q15_t)0x992a, (q15_t)0x4c30, (q15_t)0x9926, + (q15_t)0x4c2b, (q15_t)0x9922, (q15_t)0x4c26, (q15_t)0x991e, (q15_t)0x4c21, (q15_t)0x991b, (q15_t)0x4c1c, (q15_t)0x9917, + (q15_t)0x4c17, (q15_t)0x9913, (q15_t)0x4c12, (q15_t)0x990f, (q15_t)0x4c0d, (q15_t)0x990c, (q15_t)0x4c08, (q15_t)0x9908, + (q15_t)0x4c03, (q15_t)0x9904, (q15_t)0x4bfe, (q15_t)0x9900, (q15_t)0x4bf9, (q15_t)0x98fd, (q15_t)0x4bf4, (q15_t)0x98f9, + (q15_t)0x4bef, (q15_t)0x98f5, (q15_t)0x4be9, (q15_t)0x98f2, (q15_t)0x4be4, (q15_t)0x98ee, (q15_t)0x4bdf, (q15_t)0x98ea, + (q15_t)0x4bda, (q15_t)0x98e6, (q15_t)0x4bd5, (q15_t)0x98e3, (q15_t)0x4bd0, (q15_t)0x98df, (q15_t)0x4bcb, (q15_t)0x98db, + (q15_t)0x4bc6, (q15_t)0x98d7, (q15_t)0x4bc1, (q15_t)0x98d4, (q15_t)0x4bbc, (q15_t)0x98d0, (q15_t)0x4bb7, (q15_t)0x98cc, + (q15_t)0x4bb2, (q15_t)0x98c9, (q15_t)0x4bad, (q15_t)0x98c5, (q15_t)0x4ba8, (q15_t)0x98c1, (q15_t)0x4ba3, (q15_t)0x98bd, + (q15_t)0x4b9e, (q15_t)0x98ba, (q15_t)0x4b98, (q15_t)0x98b6, (q15_t)0x4b93, (q15_t)0x98b2, (q15_t)0x4b8e, (q15_t)0x98af, + (q15_t)0x4b89, (q15_t)0x98ab, (q15_t)0x4b84, (q15_t)0x98a7, (q15_t)0x4b7f, (q15_t)0x98a3, (q15_t)0x4b7a, (q15_t)0x98a0, + (q15_t)0x4b75, (q15_t)0x989c, (q15_t)0x4b70, (q15_t)0x9898, (q15_t)0x4b6b, (q15_t)0x9895, (q15_t)0x4b66, (q15_t)0x9891, + (q15_t)0x4b61, (q15_t)0x988d, (q15_t)0x4b5c, (q15_t)0x988a, (q15_t)0x4b56, (q15_t)0x9886, (q15_t)0x4b51, (q15_t)0x9882, + (q15_t)0x4b4c, (q15_t)0x987e, (q15_t)0x4b47, (q15_t)0x987b, (q15_t)0x4b42, (q15_t)0x9877, (q15_t)0x4b3d, (q15_t)0x9873, + (q15_t)0x4b38, (q15_t)0x9870, (q15_t)0x4b33, (q15_t)0x986c, (q15_t)0x4b2e, (q15_t)0x9868, (q15_t)0x4b29, (q15_t)0x9865, + (q15_t)0x4b24, (q15_t)0x9861, (q15_t)0x4b1f, (q15_t)0x985d, (q15_t)0x4b19, (q15_t)0x985a, (q15_t)0x4b14, (q15_t)0x9856, + (q15_t)0x4b0f, (q15_t)0x9852, (q15_t)0x4b0a, (q15_t)0x984e, (q15_t)0x4b05, (q15_t)0x984b, (q15_t)0x4b00, (q15_t)0x9847, + (q15_t)0x4afb, (q15_t)0x9843, (q15_t)0x4af6, (q15_t)0x9840, (q15_t)0x4af1, (q15_t)0x983c, (q15_t)0x4aec, (q15_t)0x9838, + (q15_t)0x4ae7, (q15_t)0x9835, (q15_t)0x4ae1, (q15_t)0x9831, (q15_t)0x4adc, (q15_t)0x982d, (q15_t)0x4ad7, (q15_t)0x982a, + (q15_t)0x4ad2, (q15_t)0x9826, (q15_t)0x4acd, (q15_t)0x9822, (q15_t)0x4ac8, (q15_t)0x981f, (q15_t)0x4ac3, (q15_t)0x981b, + (q15_t)0x4abe, (q15_t)0x9817, (q15_t)0x4ab9, (q15_t)0x9814, (q15_t)0x4ab4, (q15_t)0x9810, (q15_t)0x4aae, (q15_t)0x980c, + (q15_t)0x4aa9, (q15_t)0x9809, (q15_t)0x4aa4, (q15_t)0x9805, (q15_t)0x4a9f, (q15_t)0x9801, (q15_t)0x4a9a, (q15_t)0x97fe, + (q15_t)0x4a95, (q15_t)0x97fa, (q15_t)0x4a90, (q15_t)0x97f6, (q15_t)0x4a8b, (q15_t)0x97f3, (q15_t)0x4a86, (q15_t)0x97ef, + (q15_t)0x4a81, (q15_t)0x97eb, (q15_t)0x4a7b, (q15_t)0x97e8, (q15_t)0x4a76, (q15_t)0x97e4, (q15_t)0x4a71, (q15_t)0x97e0, + (q15_t)0x4a6c, (q15_t)0x97dd, (q15_t)0x4a67, (q15_t)0x97d9, (q15_t)0x4a62, (q15_t)0x97d5, (q15_t)0x4a5d, (q15_t)0x97d2, + (q15_t)0x4a58, (q15_t)0x97ce, (q15_t)0x4a52, (q15_t)0x97cb, (q15_t)0x4a4d, (q15_t)0x97c7, (q15_t)0x4a48, (q15_t)0x97c3, + (q15_t)0x4a43, (q15_t)0x97c0, (q15_t)0x4a3e, (q15_t)0x97bc, (q15_t)0x4a39, (q15_t)0x97b8, (q15_t)0x4a34, (q15_t)0x97b5, + (q15_t)0x4a2f, (q15_t)0x97b1, (q15_t)0x4a2a, (q15_t)0x97ad, (q15_t)0x4a24, (q15_t)0x97aa, (q15_t)0x4a1f, (q15_t)0x97a6, + (q15_t)0x4a1a, (q15_t)0x97a2, (q15_t)0x4a15, (q15_t)0x979f, (q15_t)0x4a10, (q15_t)0x979b, (q15_t)0x4a0b, (q15_t)0x9798, + (q15_t)0x4a06, (q15_t)0x9794, (q15_t)0x4a01, (q15_t)0x9790, (q15_t)0x49fb, (q15_t)0x978d, (q15_t)0x49f6, (q15_t)0x9789, + (q15_t)0x49f1, (q15_t)0x9785, (q15_t)0x49ec, (q15_t)0x9782, (q15_t)0x49e7, (q15_t)0x977e, (q15_t)0x49e2, (q15_t)0x977a, + (q15_t)0x49dd, (q15_t)0x9777, (q15_t)0x49d8, (q15_t)0x9773, (q15_t)0x49d2, (q15_t)0x9770, (q15_t)0x49cd, (q15_t)0x976c, + (q15_t)0x49c8, (q15_t)0x9768, (q15_t)0x49c3, (q15_t)0x9765, (q15_t)0x49be, (q15_t)0x9761, (q15_t)0x49b9, (q15_t)0x975d, + (q15_t)0x49b4, (q15_t)0x975a, (q15_t)0x49ae, (q15_t)0x9756, (q15_t)0x49a9, (q15_t)0x9753, (q15_t)0x49a4, (q15_t)0x974f, + (q15_t)0x499f, (q15_t)0x974b, (q15_t)0x499a, (q15_t)0x9748, (q15_t)0x4995, (q15_t)0x9744, (q15_t)0x4990, (q15_t)0x9741, + (q15_t)0x498a, (q15_t)0x973d, (q15_t)0x4985, (q15_t)0x9739, (q15_t)0x4980, (q15_t)0x9736, (q15_t)0x497b, (q15_t)0x9732, + (q15_t)0x4976, (q15_t)0x972f, (q15_t)0x4971, (q15_t)0x972b, (q15_t)0x496c, (q15_t)0x9727, (q15_t)0x4966, (q15_t)0x9724, + (q15_t)0x4961, (q15_t)0x9720, (q15_t)0x495c, (q15_t)0x971d, (q15_t)0x4957, (q15_t)0x9719, (q15_t)0x4952, (q15_t)0x9715, + (q15_t)0x494d, (q15_t)0x9712, (q15_t)0x4948, (q15_t)0x970e, (q15_t)0x4942, (q15_t)0x970b, (q15_t)0x493d, (q15_t)0x9707, + (q15_t)0x4938, (q15_t)0x9703, (q15_t)0x4933, (q15_t)0x9700, (q15_t)0x492e, (q15_t)0x96fc, (q15_t)0x4929, (q15_t)0x96f9, + (q15_t)0x4923, (q15_t)0x96f5, (q15_t)0x491e, (q15_t)0x96f1, (q15_t)0x4919, (q15_t)0x96ee, (q15_t)0x4914, (q15_t)0x96ea, + (q15_t)0x490f, (q15_t)0x96e7, (q15_t)0x490a, (q15_t)0x96e3, (q15_t)0x4905, (q15_t)0x96df, (q15_t)0x48ff, (q15_t)0x96dc, + (q15_t)0x48fa, (q15_t)0x96d8, (q15_t)0x48f5, (q15_t)0x96d5, (q15_t)0x48f0, (q15_t)0x96d1, (q15_t)0x48eb, (q15_t)0x96ce, + (q15_t)0x48e6, (q15_t)0x96ca, (q15_t)0x48e0, (q15_t)0x96c6, (q15_t)0x48db, (q15_t)0x96c3, (q15_t)0x48d6, (q15_t)0x96bf, + (q15_t)0x48d1, (q15_t)0x96bc, (q15_t)0x48cc, (q15_t)0x96b8, (q15_t)0x48c7, (q15_t)0x96b5, (q15_t)0x48c1, (q15_t)0x96b1, + (q15_t)0x48bc, (q15_t)0x96ad, (q15_t)0x48b7, (q15_t)0x96aa, (q15_t)0x48b2, (q15_t)0x96a6, (q15_t)0x48ad, (q15_t)0x96a3, + (q15_t)0x48a8, (q15_t)0x969f, (q15_t)0x48a2, (q15_t)0x969c, (q15_t)0x489d, (q15_t)0x9698, (q15_t)0x4898, (q15_t)0x9694, + (q15_t)0x4893, (q15_t)0x9691, (q15_t)0x488e, (q15_t)0x968d, (q15_t)0x4888, (q15_t)0x968a, (q15_t)0x4883, (q15_t)0x9686, + (q15_t)0x487e, (q15_t)0x9683, (q15_t)0x4879, (q15_t)0x967f, (q15_t)0x4874, (q15_t)0x967b, (q15_t)0x486f, (q15_t)0x9678, + (q15_t)0x4869, (q15_t)0x9674, (q15_t)0x4864, (q15_t)0x9671, (q15_t)0x485f, (q15_t)0x966d, (q15_t)0x485a, (q15_t)0x966a, + (q15_t)0x4855, (q15_t)0x9666, (q15_t)0x484f, (q15_t)0x9663, (q15_t)0x484a, (q15_t)0x965f, (q15_t)0x4845, (q15_t)0x965b, + (q15_t)0x4840, (q15_t)0x9658, (q15_t)0x483b, (q15_t)0x9654, (q15_t)0x4836, (q15_t)0x9651, (q15_t)0x4830, (q15_t)0x964d, + (q15_t)0x482b, (q15_t)0x964a, (q15_t)0x4826, (q15_t)0x9646, (q15_t)0x4821, (q15_t)0x9643, (q15_t)0x481c, (q15_t)0x963f, + (q15_t)0x4816, (q15_t)0x963c, (q15_t)0x4811, (q15_t)0x9638, (q15_t)0x480c, (q15_t)0x9635, (q15_t)0x4807, (q15_t)0x9631, + (q15_t)0x4802, (q15_t)0x962d, (q15_t)0x47fc, (q15_t)0x962a, (q15_t)0x47f7, (q15_t)0x9626, (q15_t)0x47f2, (q15_t)0x9623, + (q15_t)0x47ed, (q15_t)0x961f, (q15_t)0x47e8, (q15_t)0x961c, (q15_t)0x47e2, (q15_t)0x9618, (q15_t)0x47dd, (q15_t)0x9615, + (q15_t)0x47d8, (q15_t)0x9611, (q15_t)0x47d3, (q15_t)0x960e, (q15_t)0x47ce, (q15_t)0x960a, (q15_t)0x47c8, (q15_t)0x9607, + (q15_t)0x47c3, (q15_t)0x9603, (q15_t)0x47be, (q15_t)0x9600, (q15_t)0x47b9, (q15_t)0x95fc, (q15_t)0x47b4, (q15_t)0x95f9, + (q15_t)0x47ae, (q15_t)0x95f5, (q15_t)0x47a9, (q15_t)0x95f2, (q15_t)0x47a4, (q15_t)0x95ee, (q15_t)0x479f, (q15_t)0x95ea, + (q15_t)0x479a, (q15_t)0x95e7, (q15_t)0x4794, (q15_t)0x95e3, (q15_t)0x478f, (q15_t)0x95e0, (q15_t)0x478a, (q15_t)0x95dc, + (q15_t)0x4785, (q15_t)0x95d9, (q15_t)0x4780, (q15_t)0x95d5, (q15_t)0x477a, (q15_t)0x95d2, (q15_t)0x4775, (q15_t)0x95ce, + (q15_t)0x4770, (q15_t)0x95cb, (q15_t)0x476b, (q15_t)0x95c7, (q15_t)0x4765, (q15_t)0x95c4, (q15_t)0x4760, (q15_t)0x95c0, + (q15_t)0x475b, (q15_t)0x95bd, (q15_t)0x4756, (q15_t)0x95b9, (q15_t)0x4751, (q15_t)0x95b6, (q15_t)0x474b, (q15_t)0x95b2, + (q15_t)0x4746, (q15_t)0x95af, (q15_t)0x4741, (q15_t)0x95ab, (q15_t)0x473c, (q15_t)0x95a8, (q15_t)0x4737, (q15_t)0x95a4, + (q15_t)0x4731, (q15_t)0x95a1, (q15_t)0x472c, (q15_t)0x959d, (q15_t)0x4727, (q15_t)0x959a, (q15_t)0x4722, (q15_t)0x9596, + (q15_t)0x471c, (q15_t)0x9593, (q15_t)0x4717, (q15_t)0x958f, (q15_t)0x4712, (q15_t)0x958c, (q15_t)0x470d, (q15_t)0x9588, + (q15_t)0x4708, (q15_t)0x9585, (q15_t)0x4702, (q15_t)0x9581, (q15_t)0x46fd, (q15_t)0x957e, (q15_t)0x46f8, (q15_t)0x957a, + (q15_t)0x46f3, (q15_t)0x9577, (q15_t)0x46ed, (q15_t)0x9574, (q15_t)0x46e8, (q15_t)0x9570, (q15_t)0x46e3, (q15_t)0x956d, + (q15_t)0x46de, (q15_t)0x9569, (q15_t)0x46d8, (q15_t)0x9566, (q15_t)0x46d3, (q15_t)0x9562, (q15_t)0x46ce, (q15_t)0x955f, + (q15_t)0x46c9, (q15_t)0x955b, (q15_t)0x46c4, (q15_t)0x9558, (q15_t)0x46be, (q15_t)0x9554, (q15_t)0x46b9, (q15_t)0x9551, + (q15_t)0x46b4, (q15_t)0x954d, (q15_t)0x46af, (q15_t)0x954a, (q15_t)0x46a9, (q15_t)0x9546, (q15_t)0x46a4, (q15_t)0x9543, + (q15_t)0x469f, (q15_t)0x953f, (q15_t)0x469a, (q15_t)0x953c, (q15_t)0x4694, (q15_t)0x9538, (q15_t)0x468f, (q15_t)0x9535, + (q15_t)0x468a, (q15_t)0x9532, (q15_t)0x4685, (q15_t)0x952e, (q15_t)0x467f, (q15_t)0x952b, (q15_t)0x467a, (q15_t)0x9527, + (q15_t)0x4675, (q15_t)0x9524, (q15_t)0x4670, (q15_t)0x9520, (q15_t)0x466a, (q15_t)0x951d, (q15_t)0x4665, (q15_t)0x9519, + (q15_t)0x4660, (q15_t)0x9516, (q15_t)0x465b, (q15_t)0x9512, (q15_t)0x4655, (q15_t)0x950f, (q15_t)0x4650, (q15_t)0x950c, + (q15_t)0x464b, (q15_t)0x9508, (q15_t)0x4646, (q15_t)0x9505, (q15_t)0x4640, (q15_t)0x9501, (q15_t)0x463b, (q15_t)0x94fe, + (q15_t)0x4636, (q15_t)0x94fa, (q15_t)0x4631, (q15_t)0x94f7, (q15_t)0x462b, (q15_t)0x94f3, (q15_t)0x4626, (q15_t)0x94f0, + (q15_t)0x4621, (q15_t)0x94ed, (q15_t)0x461c, (q15_t)0x94e9, (q15_t)0x4616, (q15_t)0x94e6, (q15_t)0x4611, (q15_t)0x94e2, + (q15_t)0x460c, (q15_t)0x94df, (q15_t)0x4607, (q15_t)0x94db, (q15_t)0x4601, (q15_t)0x94d8, (q15_t)0x45fc, (q15_t)0x94d4, + (q15_t)0x45f7, (q15_t)0x94d1, (q15_t)0x45f2, (q15_t)0x94ce, (q15_t)0x45ec, (q15_t)0x94ca, (q15_t)0x45e7, (q15_t)0x94c7, + (q15_t)0x45e2, (q15_t)0x94c3, (q15_t)0x45dd, (q15_t)0x94c0, (q15_t)0x45d7, (q15_t)0x94bc, (q15_t)0x45d2, (q15_t)0x94b9, + (q15_t)0x45cd, (q15_t)0x94b6, (q15_t)0x45c7, (q15_t)0x94b2, (q15_t)0x45c2, (q15_t)0x94af, (q15_t)0x45bd, (q15_t)0x94ab, + (q15_t)0x45b8, (q15_t)0x94a8, (q15_t)0x45b2, (q15_t)0x94a4, (q15_t)0x45ad, (q15_t)0x94a1, (q15_t)0x45a8, (q15_t)0x949e, + (q15_t)0x45a3, (q15_t)0x949a, (q15_t)0x459d, (q15_t)0x9497, (q15_t)0x4598, (q15_t)0x9493, (q15_t)0x4593, (q15_t)0x9490, + (q15_t)0x458d, (q15_t)0x948d, (q15_t)0x4588, (q15_t)0x9489, (q15_t)0x4583, (q15_t)0x9486, (q15_t)0x457e, (q15_t)0x9482, + (q15_t)0x4578, (q15_t)0x947f, (q15_t)0x4573, (q15_t)0x947b, (q15_t)0x456e, (q15_t)0x9478, (q15_t)0x4569, (q15_t)0x9475, + (q15_t)0x4563, (q15_t)0x9471, (q15_t)0x455e, (q15_t)0x946e, (q15_t)0x4559, (q15_t)0x946a, (q15_t)0x4553, (q15_t)0x9467, + (q15_t)0x454e, (q15_t)0x9464, (q15_t)0x4549, (q15_t)0x9460, (q15_t)0x4544, (q15_t)0x945d, (q15_t)0x453e, (q15_t)0x9459, + (q15_t)0x4539, (q15_t)0x9456, (q15_t)0x4534, (q15_t)0x9453, (q15_t)0x452e, (q15_t)0x944f, (q15_t)0x4529, (q15_t)0x944c, + (q15_t)0x4524, (q15_t)0x9448, (q15_t)0x451f, (q15_t)0x9445, (q15_t)0x4519, (q15_t)0x9442, (q15_t)0x4514, (q15_t)0x943e, + (q15_t)0x450f, (q15_t)0x943b, (q15_t)0x4509, (q15_t)0x9437, (q15_t)0x4504, (q15_t)0x9434, (q15_t)0x44ff, (q15_t)0x9431, + (q15_t)0x44fa, (q15_t)0x942d, (q15_t)0x44f4, (q15_t)0x942a, (q15_t)0x44ef, (q15_t)0x9427, (q15_t)0x44ea, (q15_t)0x9423, + (q15_t)0x44e4, (q15_t)0x9420, (q15_t)0x44df, (q15_t)0x941c, (q15_t)0x44da, (q15_t)0x9419, (q15_t)0x44d4, (q15_t)0x9416, + (q15_t)0x44cf, (q15_t)0x9412, (q15_t)0x44ca, (q15_t)0x940f, (q15_t)0x44c5, (q15_t)0x940b, (q15_t)0x44bf, (q15_t)0x9408, + (q15_t)0x44ba, (q15_t)0x9405, (q15_t)0x44b5, (q15_t)0x9401, (q15_t)0x44af, (q15_t)0x93fe, (q15_t)0x44aa, (q15_t)0x93fb, + (q15_t)0x44a5, (q15_t)0x93f7, (q15_t)0x449f, (q15_t)0x93f4, (q15_t)0x449a, (q15_t)0x93f1, (q15_t)0x4495, (q15_t)0x93ed, + (q15_t)0x4490, (q15_t)0x93ea, (q15_t)0x448a, (q15_t)0x93e6, (q15_t)0x4485, (q15_t)0x93e3, (q15_t)0x4480, (q15_t)0x93e0, + (q15_t)0x447a, (q15_t)0x93dc, (q15_t)0x4475, (q15_t)0x93d9, (q15_t)0x4470, (q15_t)0x93d6, (q15_t)0x446a, (q15_t)0x93d2, + (q15_t)0x4465, (q15_t)0x93cf, (q15_t)0x4460, (q15_t)0x93cc, (q15_t)0x445a, (q15_t)0x93c8, (q15_t)0x4455, (q15_t)0x93c5, + (q15_t)0x4450, (q15_t)0x93c1, (q15_t)0x444b, (q15_t)0x93be, (q15_t)0x4445, (q15_t)0x93bb, (q15_t)0x4440, (q15_t)0x93b7, + (q15_t)0x443b, (q15_t)0x93b4, (q15_t)0x4435, (q15_t)0x93b1, (q15_t)0x4430, (q15_t)0x93ad, (q15_t)0x442b, (q15_t)0x93aa, + (q15_t)0x4425, (q15_t)0x93a7, (q15_t)0x4420, (q15_t)0x93a3, (q15_t)0x441b, (q15_t)0x93a0, (q15_t)0x4415, (q15_t)0x939d, + (q15_t)0x4410, (q15_t)0x9399, (q15_t)0x440b, (q15_t)0x9396, (q15_t)0x4405, (q15_t)0x9393, (q15_t)0x4400, (q15_t)0x938f, + (q15_t)0x43fb, (q15_t)0x938c, (q15_t)0x43f5, (q15_t)0x9389, (q15_t)0x43f0, (q15_t)0x9385, (q15_t)0x43eb, (q15_t)0x9382, + (q15_t)0x43e5, (q15_t)0x937f, (q15_t)0x43e0, (q15_t)0x937b, (q15_t)0x43db, (q15_t)0x9378, (q15_t)0x43d5, (q15_t)0x9375, + (q15_t)0x43d0, (q15_t)0x9371, (q15_t)0x43cb, (q15_t)0x936e, (q15_t)0x43c5, (q15_t)0x936b, (q15_t)0x43c0, (q15_t)0x9367, + (q15_t)0x43bb, (q15_t)0x9364, (q15_t)0x43b5, (q15_t)0x9361, (q15_t)0x43b0, (q15_t)0x935d, (q15_t)0x43ab, (q15_t)0x935a, + (q15_t)0x43a5, (q15_t)0x9357, (q15_t)0x43a0, (q15_t)0x9353, (q15_t)0x439b, (q15_t)0x9350, (q15_t)0x4395, (q15_t)0x934d, + (q15_t)0x4390, (q15_t)0x9349, (q15_t)0x438b, (q15_t)0x9346, (q15_t)0x4385, (q15_t)0x9343, (q15_t)0x4380, (q15_t)0x933f, + (q15_t)0x437b, (q15_t)0x933c, (q15_t)0x4375, (q15_t)0x9339, (q15_t)0x4370, (q15_t)0x9336, (q15_t)0x436b, (q15_t)0x9332, + (q15_t)0x4365, (q15_t)0x932f, (q15_t)0x4360, (q15_t)0x932c, (q15_t)0x435b, (q15_t)0x9328, (q15_t)0x4355, (q15_t)0x9325, + (q15_t)0x4350, (q15_t)0x9322, (q15_t)0x434b, (q15_t)0x931e, (q15_t)0x4345, (q15_t)0x931b, (q15_t)0x4340, (q15_t)0x9318, + (q15_t)0x433b, (q15_t)0x9314, (q15_t)0x4335, (q15_t)0x9311, (q15_t)0x4330, (q15_t)0x930e, (q15_t)0x432b, (q15_t)0x930b, + (q15_t)0x4325, (q15_t)0x9307, (q15_t)0x4320, (q15_t)0x9304, (q15_t)0x431b, (q15_t)0x9301, (q15_t)0x4315, (q15_t)0x92fd, + (q15_t)0x4310, (q15_t)0x92fa, (q15_t)0x430b, (q15_t)0x92f7, (q15_t)0x4305, (q15_t)0x92f4, (q15_t)0x4300, (q15_t)0x92f0, + (q15_t)0x42fa, (q15_t)0x92ed, (q15_t)0x42f5, (q15_t)0x92ea, (q15_t)0x42f0, (q15_t)0x92e6, (q15_t)0x42ea, (q15_t)0x92e3, + (q15_t)0x42e5, (q15_t)0x92e0, (q15_t)0x42e0, (q15_t)0x92dd, (q15_t)0x42da, (q15_t)0x92d9, (q15_t)0x42d5, (q15_t)0x92d6, + (q15_t)0x42d0, (q15_t)0x92d3, (q15_t)0x42ca, (q15_t)0x92cf, (q15_t)0x42c5, (q15_t)0x92cc, (q15_t)0x42c0, (q15_t)0x92c9, + (q15_t)0x42ba, (q15_t)0x92c6, (q15_t)0x42b5, (q15_t)0x92c2, (q15_t)0x42af, (q15_t)0x92bf, (q15_t)0x42aa, (q15_t)0x92bc, + (q15_t)0x42a5, (q15_t)0x92b8, (q15_t)0x429f, (q15_t)0x92b5, (q15_t)0x429a, (q15_t)0x92b2, (q15_t)0x4295, (q15_t)0x92af, + (q15_t)0x428f, (q15_t)0x92ab, (q15_t)0x428a, (q15_t)0x92a8, (q15_t)0x4284, (q15_t)0x92a5, (q15_t)0x427f, (q15_t)0x92a2, + (q15_t)0x427a, (q15_t)0x929e, (q15_t)0x4274, (q15_t)0x929b, (q15_t)0x426f, (q15_t)0x9298, (q15_t)0x426a, (q15_t)0x9295, + (q15_t)0x4264, (q15_t)0x9291, (q15_t)0x425f, (q15_t)0x928e, (q15_t)0x425a, (q15_t)0x928b, (q15_t)0x4254, (q15_t)0x9288, + (q15_t)0x424f, (q15_t)0x9284, (q15_t)0x4249, (q15_t)0x9281, (q15_t)0x4244, (q15_t)0x927e, (q15_t)0x423f, (q15_t)0x927b, + (q15_t)0x4239, (q15_t)0x9277, (q15_t)0x4234, (q15_t)0x9274, (q15_t)0x422f, (q15_t)0x9271, (q15_t)0x4229, (q15_t)0x926e, + (q15_t)0x4224, (q15_t)0x926a, (q15_t)0x421e, (q15_t)0x9267, (q15_t)0x4219, (q15_t)0x9264, (q15_t)0x4214, (q15_t)0x9261, + (q15_t)0x420e, (q15_t)0x925d, (q15_t)0x4209, (q15_t)0x925a, (q15_t)0x4203, (q15_t)0x9257, (q15_t)0x41fe, (q15_t)0x9254, + (q15_t)0x41f9, (q15_t)0x9250, (q15_t)0x41f3, (q15_t)0x924d, (q15_t)0x41ee, (q15_t)0x924a, (q15_t)0x41e9, (q15_t)0x9247, + (q15_t)0x41e3, (q15_t)0x9243, (q15_t)0x41de, (q15_t)0x9240, (q15_t)0x41d8, (q15_t)0x923d, (q15_t)0x41d3, (q15_t)0x923a, + (q15_t)0x41ce, (q15_t)0x9236, (q15_t)0x41c8, (q15_t)0x9233, (q15_t)0x41c3, (q15_t)0x9230, (q15_t)0x41bd, (q15_t)0x922d, + (q15_t)0x41b8, (q15_t)0x922a, (q15_t)0x41b3, (q15_t)0x9226, (q15_t)0x41ad, (q15_t)0x9223, (q15_t)0x41a8, (q15_t)0x9220, + (q15_t)0x41a2, (q15_t)0x921d, (q15_t)0x419d, (q15_t)0x9219, (q15_t)0x4198, (q15_t)0x9216, (q15_t)0x4192, (q15_t)0x9213, + (q15_t)0x418d, (q15_t)0x9210, (q15_t)0x4188, (q15_t)0x920d, (q15_t)0x4182, (q15_t)0x9209, (q15_t)0x417d, (q15_t)0x9206, + (q15_t)0x4177, (q15_t)0x9203, (q15_t)0x4172, (q15_t)0x9200, (q15_t)0x416d, (q15_t)0x91fc, (q15_t)0x4167, (q15_t)0x91f9, + (q15_t)0x4162, (q15_t)0x91f6, (q15_t)0x415c, (q15_t)0x91f3, (q15_t)0x4157, (q15_t)0x91f0, (q15_t)0x4152, (q15_t)0x91ec, + (q15_t)0x414c, (q15_t)0x91e9, (q15_t)0x4147, (q15_t)0x91e6, (q15_t)0x4141, (q15_t)0x91e3, (q15_t)0x413c, (q15_t)0x91e0, + (q15_t)0x4136, (q15_t)0x91dc, (q15_t)0x4131, (q15_t)0x91d9, (q15_t)0x412c, (q15_t)0x91d6, (q15_t)0x4126, (q15_t)0x91d3, + (q15_t)0x4121, (q15_t)0x91d0, (q15_t)0x411b, (q15_t)0x91cc, (q15_t)0x4116, (q15_t)0x91c9, (q15_t)0x4111, (q15_t)0x91c6, + (q15_t)0x410b, (q15_t)0x91c3, (q15_t)0x4106, (q15_t)0x91c0, (q15_t)0x4100, (q15_t)0x91bc, (q15_t)0x40fb, (q15_t)0x91b9, + (q15_t)0x40f6, (q15_t)0x91b6, (q15_t)0x40f0, (q15_t)0x91b3, (q15_t)0x40eb, (q15_t)0x91b0, (q15_t)0x40e5, (q15_t)0x91ad, + (q15_t)0x40e0, (q15_t)0x91a9, (q15_t)0x40da, (q15_t)0x91a6, (q15_t)0x40d5, (q15_t)0x91a3, (q15_t)0x40d0, (q15_t)0x91a0, + (q15_t)0x40ca, (q15_t)0x919d, (q15_t)0x40c5, (q15_t)0x9199, (q15_t)0x40bf, (q15_t)0x9196, (q15_t)0x40ba, (q15_t)0x9193, + (q15_t)0x40b5, (q15_t)0x9190, (q15_t)0x40af, (q15_t)0x918d, (q15_t)0x40aa, (q15_t)0x918a, (q15_t)0x40a4, (q15_t)0x9186, + (q15_t)0x409f, (q15_t)0x9183, (q15_t)0x4099, (q15_t)0x9180, (q15_t)0x4094, (q15_t)0x917d, (q15_t)0x408f, (q15_t)0x917a, + (q15_t)0x4089, (q15_t)0x9177, (q15_t)0x4084, (q15_t)0x9173, (q15_t)0x407e, (q15_t)0x9170, (q15_t)0x4079, (q15_t)0x916d, + (q15_t)0x4073, (q15_t)0x916a, (q15_t)0x406e, (q15_t)0x9167, (q15_t)0x4069, (q15_t)0x9164, (q15_t)0x4063, (q15_t)0x9160, + (q15_t)0x405e, (q15_t)0x915d, (q15_t)0x4058, (q15_t)0x915a, (q15_t)0x4053, (q15_t)0x9157, (q15_t)0x404d, (q15_t)0x9154, + (q15_t)0x4048, (q15_t)0x9151, (q15_t)0x4043, (q15_t)0x914d, (q15_t)0x403d, (q15_t)0x914a, (q15_t)0x4038, (q15_t)0x9147, + (q15_t)0x4032, (q15_t)0x9144, (q15_t)0x402d, (q15_t)0x9141, (q15_t)0x4027, (q15_t)0x913e, (q15_t)0x4022, (q15_t)0x913a, + (q15_t)0x401d, (q15_t)0x9137, (q15_t)0x4017, (q15_t)0x9134, (q15_t)0x4012, (q15_t)0x9131, (q15_t)0x400c, (q15_t)0x912e, + (q15_t)0x4007, (q15_t)0x912b, (q15_t)0x4001, (q15_t)0x9128, (q15_t)0x3ffc, (q15_t)0x9124, (q15_t)0x3ff6, (q15_t)0x9121, + (q15_t)0x3ff1, (q15_t)0x911e, (q15_t)0x3fec, (q15_t)0x911b, (q15_t)0x3fe6, (q15_t)0x9118, (q15_t)0x3fe1, (q15_t)0x9115, + (q15_t)0x3fdb, (q15_t)0x9112, (q15_t)0x3fd6, (q15_t)0x910f, (q15_t)0x3fd0, (q15_t)0x910b, (q15_t)0x3fcb, (q15_t)0x9108, + (q15_t)0x3fc5, (q15_t)0x9105, (q15_t)0x3fc0, (q15_t)0x9102, (q15_t)0x3fbb, (q15_t)0x90ff, (q15_t)0x3fb5, (q15_t)0x90fc, + (q15_t)0x3fb0, (q15_t)0x90f9, (q15_t)0x3faa, (q15_t)0x90f5, (q15_t)0x3fa5, (q15_t)0x90f2, (q15_t)0x3f9f, (q15_t)0x90ef, + (q15_t)0x3f9a, (q15_t)0x90ec, (q15_t)0x3f94, (q15_t)0x90e9, (q15_t)0x3f8f, (q15_t)0x90e6, (q15_t)0x3f89, (q15_t)0x90e3, + (q15_t)0x3f84, (q15_t)0x90e0, (q15_t)0x3f7f, (q15_t)0x90dd, (q15_t)0x3f79, (q15_t)0x90d9, (q15_t)0x3f74, (q15_t)0x90d6, + (q15_t)0x3f6e, (q15_t)0x90d3, (q15_t)0x3f69, (q15_t)0x90d0, (q15_t)0x3f63, (q15_t)0x90cd, (q15_t)0x3f5e, (q15_t)0x90ca, + (q15_t)0x3f58, (q15_t)0x90c7, (q15_t)0x3f53, (q15_t)0x90c4, (q15_t)0x3f4d, (q15_t)0x90c1, (q15_t)0x3f48, (q15_t)0x90bd, + (q15_t)0x3f43, (q15_t)0x90ba, (q15_t)0x3f3d, (q15_t)0x90b7, (q15_t)0x3f38, (q15_t)0x90b4, (q15_t)0x3f32, (q15_t)0x90b1, + (q15_t)0x3f2d, (q15_t)0x90ae, (q15_t)0x3f27, (q15_t)0x90ab, (q15_t)0x3f22, (q15_t)0x90a8, (q15_t)0x3f1c, (q15_t)0x90a5, + (q15_t)0x3f17, (q15_t)0x90a1, (q15_t)0x3f11, (q15_t)0x909e, (q15_t)0x3f0c, (q15_t)0x909b, (q15_t)0x3f06, (q15_t)0x9098, + (q15_t)0x3f01, (q15_t)0x9095, (q15_t)0x3efb, (q15_t)0x9092, (q15_t)0x3ef6, (q15_t)0x908f, (q15_t)0x3ef1, (q15_t)0x908c, + (q15_t)0x3eeb, (q15_t)0x9089, (q15_t)0x3ee6, (q15_t)0x9086, (q15_t)0x3ee0, (q15_t)0x9083, (q15_t)0x3edb, (q15_t)0x907f, + (q15_t)0x3ed5, (q15_t)0x907c, (q15_t)0x3ed0, (q15_t)0x9079, (q15_t)0x3eca, (q15_t)0x9076, (q15_t)0x3ec5, (q15_t)0x9073, + (q15_t)0x3ebf, (q15_t)0x9070, (q15_t)0x3eba, (q15_t)0x906d, (q15_t)0x3eb4, (q15_t)0x906a, (q15_t)0x3eaf, (q15_t)0x9067, + (q15_t)0x3ea9, (q15_t)0x9064, (q15_t)0x3ea4, (q15_t)0x9061, (q15_t)0x3e9e, (q15_t)0x905e, (q15_t)0x3e99, (q15_t)0x905b, + (q15_t)0x3e93, (q15_t)0x9057, (q15_t)0x3e8e, (q15_t)0x9054, (q15_t)0x3e88, (q15_t)0x9051, (q15_t)0x3e83, (q15_t)0x904e, + (q15_t)0x3e7d, (q15_t)0x904b, (q15_t)0x3e78, (q15_t)0x9048, (q15_t)0x3e73, (q15_t)0x9045, (q15_t)0x3e6d, (q15_t)0x9042, + (q15_t)0x3e68, (q15_t)0x903f, (q15_t)0x3e62, (q15_t)0x903c, (q15_t)0x3e5d, (q15_t)0x9039, (q15_t)0x3e57, (q15_t)0x9036, + (q15_t)0x3e52, (q15_t)0x9033, (q15_t)0x3e4c, (q15_t)0x9030, (q15_t)0x3e47, (q15_t)0x902d, (q15_t)0x3e41, (q15_t)0x902a, + (q15_t)0x3e3c, (q15_t)0x9026, (q15_t)0x3e36, (q15_t)0x9023, (q15_t)0x3e31, (q15_t)0x9020, (q15_t)0x3e2b, (q15_t)0x901d, + (q15_t)0x3e26, (q15_t)0x901a, (q15_t)0x3e20, (q15_t)0x9017, (q15_t)0x3e1b, (q15_t)0x9014, (q15_t)0x3e15, (q15_t)0x9011, + (q15_t)0x3e10, (q15_t)0x900e, (q15_t)0x3e0a, (q15_t)0x900b, (q15_t)0x3e05, (q15_t)0x9008, (q15_t)0x3dff, (q15_t)0x9005, + (q15_t)0x3dfa, (q15_t)0x9002, (q15_t)0x3df4, (q15_t)0x8fff, (q15_t)0x3def, (q15_t)0x8ffc, (q15_t)0x3de9, (q15_t)0x8ff9, + (q15_t)0x3de4, (q15_t)0x8ff6, (q15_t)0x3dde, (q15_t)0x8ff3, (q15_t)0x3dd9, (q15_t)0x8ff0, (q15_t)0x3dd3, (q15_t)0x8fed, + (q15_t)0x3dce, (q15_t)0x8fea, (q15_t)0x3dc8, (q15_t)0x8fe7, (q15_t)0x3dc3, (q15_t)0x8fe3, (q15_t)0x3dbd, (q15_t)0x8fe0, + (q15_t)0x3db8, (q15_t)0x8fdd, (q15_t)0x3db2, (q15_t)0x8fda, (q15_t)0x3dad, (q15_t)0x8fd7, (q15_t)0x3da7, (q15_t)0x8fd4, + (q15_t)0x3da2, (q15_t)0x8fd1, (q15_t)0x3d9c, (q15_t)0x8fce, (q15_t)0x3d97, (q15_t)0x8fcb, (q15_t)0x3d91, (q15_t)0x8fc8, + (q15_t)0x3d8c, (q15_t)0x8fc5, (q15_t)0x3d86, (q15_t)0x8fc2, (q15_t)0x3d81, (q15_t)0x8fbf, (q15_t)0x3d7b, (q15_t)0x8fbc, + (q15_t)0x3d76, (q15_t)0x8fb9, (q15_t)0x3d70, (q15_t)0x8fb6, (q15_t)0x3d6b, (q15_t)0x8fb3, (q15_t)0x3d65, (q15_t)0x8fb0, + (q15_t)0x3d60, (q15_t)0x8fad, (q15_t)0x3d5a, (q15_t)0x8faa, (q15_t)0x3d55, (q15_t)0x8fa7, (q15_t)0x3d4f, (q15_t)0x8fa4, + (q15_t)0x3d49, (q15_t)0x8fa1, (q15_t)0x3d44, (q15_t)0x8f9e, (q15_t)0x3d3e, (q15_t)0x8f9b, (q15_t)0x3d39, (q15_t)0x8f98, + (q15_t)0x3d33, (q15_t)0x8f95, (q15_t)0x3d2e, (q15_t)0x8f92, (q15_t)0x3d28, (q15_t)0x8f8f, (q15_t)0x3d23, (q15_t)0x8f8c, + (q15_t)0x3d1d, (q15_t)0x8f89, (q15_t)0x3d18, (q15_t)0x8f86, (q15_t)0x3d12, (q15_t)0x8f83, (q15_t)0x3d0d, (q15_t)0x8f80, + (q15_t)0x3d07, (q15_t)0x8f7d, (q15_t)0x3d02, (q15_t)0x8f7a, (q15_t)0x3cfc, (q15_t)0x8f77, (q15_t)0x3cf7, (q15_t)0x8f74, + (q15_t)0x3cf1, (q15_t)0x8f71, (q15_t)0x3cec, (q15_t)0x8f6e, (q15_t)0x3ce6, (q15_t)0x8f6b, (q15_t)0x3ce1, (q15_t)0x8f68, + (q15_t)0x3cdb, (q15_t)0x8f65, (q15_t)0x3cd6, (q15_t)0x8f62, (q15_t)0x3cd0, (q15_t)0x8f5f, (q15_t)0x3cca, (q15_t)0x8f5c, + (q15_t)0x3cc5, (q15_t)0x8f59, (q15_t)0x3cbf, (q15_t)0x8f56, (q15_t)0x3cba, (q15_t)0x8f53, (q15_t)0x3cb4, (q15_t)0x8f50, + (q15_t)0x3caf, (q15_t)0x8f4d, (q15_t)0x3ca9, (q15_t)0x8f4a, (q15_t)0x3ca4, (q15_t)0x8f47, (q15_t)0x3c9e, (q15_t)0x8f44, + (q15_t)0x3c99, (q15_t)0x8f41, (q15_t)0x3c93, (q15_t)0x8f3e, (q15_t)0x3c8e, (q15_t)0x8f3b, (q15_t)0x3c88, (q15_t)0x8f38, + (q15_t)0x3c83, (q15_t)0x8f35, (q15_t)0x3c7d, (q15_t)0x8f32, (q15_t)0x3c77, (q15_t)0x8f2f, (q15_t)0x3c72, (q15_t)0x8f2d, + (q15_t)0x3c6c, (q15_t)0x8f2a, (q15_t)0x3c67, (q15_t)0x8f27, (q15_t)0x3c61, (q15_t)0x8f24, (q15_t)0x3c5c, (q15_t)0x8f21, + (q15_t)0x3c56, (q15_t)0x8f1e, (q15_t)0x3c51, (q15_t)0x8f1b, (q15_t)0x3c4b, (q15_t)0x8f18, (q15_t)0x3c46, (q15_t)0x8f15, + (q15_t)0x3c40, (q15_t)0x8f12, (q15_t)0x3c3b, (q15_t)0x8f0f, (q15_t)0x3c35, (q15_t)0x8f0c, (q15_t)0x3c2f, (q15_t)0x8f09, + (q15_t)0x3c2a, (q15_t)0x8f06, (q15_t)0x3c24, (q15_t)0x8f03, (q15_t)0x3c1f, (q15_t)0x8f00, (q15_t)0x3c19, (q15_t)0x8efd, + (q15_t)0x3c14, (q15_t)0x8efa, (q15_t)0x3c0e, (q15_t)0x8ef7, (q15_t)0x3c09, (q15_t)0x8ef4, (q15_t)0x3c03, (q15_t)0x8ef1, + (q15_t)0x3bfd, (q15_t)0x8eee, (q15_t)0x3bf8, (q15_t)0x8eec, (q15_t)0x3bf2, (q15_t)0x8ee9, (q15_t)0x3bed, (q15_t)0x8ee6, + (q15_t)0x3be7, (q15_t)0x8ee3, (q15_t)0x3be2, (q15_t)0x8ee0, (q15_t)0x3bdc, (q15_t)0x8edd, (q15_t)0x3bd7, (q15_t)0x8eda, + (q15_t)0x3bd1, (q15_t)0x8ed7, (q15_t)0x3bcc, (q15_t)0x8ed4, (q15_t)0x3bc6, (q15_t)0x8ed1, (q15_t)0x3bc0, (q15_t)0x8ece, + (q15_t)0x3bbb, (q15_t)0x8ecb, (q15_t)0x3bb5, (q15_t)0x8ec8, (q15_t)0x3bb0, (q15_t)0x8ec5, (q15_t)0x3baa, (q15_t)0x8ec2, + (q15_t)0x3ba5, (q15_t)0x8ebf, (q15_t)0x3b9f, (q15_t)0x8ebd, (q15_t)0x3b99, (q15_t)0x8eba, (q15_t)0x3b94, (q15_t)0x8eb7, + (q15_t)0x3b8e, (q15_t)0x8eb4, (q15_t)0x3b89, (q15_t)0x8eb1, (q15_t)0x3b83, (q15_t)0x8eae, (q15_t)0x3b7e, (q15_t)0x8eab, + (q15_t)0x3b78, (q15_t)0x8ea8, (q15_t)0x3b73, (q15_t)0x8ea5, (q15_t)0x3b6d, (q15_t)0x8ea2, (q15_t)0x3b67, (q15_t)0x8e9f, + (q15_t)0x3b62, (q15_t)0x8e9c, (q15_t)0x3b5c, (q15_t)0x8e99, (q15_t)0x3b57, (q15_t)0x8e97, (q15_t)0x3b51, (q15_t)0x8e94, + (q15_t)0x3b4c, (q15_t)0x8e91, (q15_t)0x3b46, (q15_t)0x8e8e, (q15_t)0x3b40, (q15_t)0x8e8b, (q15_t)0x3b3b, (q15_t)0x8e88, + (q15_t)0x3b35, (q15_t)0x8e85, (q15_t)0x3b30, (q15_t)0x8e82, (q15_t)0x3b2a, (q15_t)0x8e7f, (q15_t)0x3b25, (q15_t)0x8e7c, + (q15_t)0x3b1f, (q15_t)0x8e7a, (q15_t)0x3b19, (q15_t)0x8e77, (q15_t)0x3b14, (q15_t)0x8e74, (q15_t)0x3b0e, (q15_t)0x8e71, + (q15_t)0x3b09, (q15_t)0x8e6e, (q15_t)0x3b03, (q15_t)0x8e6b, (q15_t)0x3afe, (q15_t)0x8e68, (q15_t)0x3af8, (q15_t)0x8e65, + (q15_t)0x3af2, (q15_t)0x8e62, (q15_t)0x3aed, (q15_t)0x8e5f, (q15_t)0x3ae7, (q15_t)0x8e5d, (q15_t)0x3ae2, (q15_t)0x8e5a, + (q15_t)0x3adc, (q15_t)0x8e57, (q15_t)0x3ad7, (q15_t)0x8e54, (q15_t)0x3ad1, (q15_t)0x8e51, (q15_t)0x3acb, (q15_t)0x8e4e, + (q15_t)0x3ac6, (q15_t)0x8e4b, (q15_t)0x3ac0, (q15_t)0x8e48, (q15_t)0x3abb, (q15_t)0x8e45, (q15_t)0x3ab5, (q15_t)0x8e43, + (q15_t)0x3aaf, (q15_t)0x8e40, (q15_t)0x3aaa, (q15_t)0x8e3d, (q15_t)0x3aa4, (q15_t)0x8e3a, (q15_t)0x3a9f, (q15_t)0x8e37, + (q15_t)0x3a99, (q15_t)0x8e34, (q15_t)0x3a94, (q15_t)0x8e31, (q15_t)0x3a8e, (q15_t)0x8e2e, (q15_t)0x3a88, (q15_t)0x8e2c, + (q15_t)0x3a83, (q15_t)0x8e29, (q15_t)0x3a7d, (q15_t)0x8e26, (q15_t)0x3a78, (q15_t)0x8e23, (q15_t)0x3a72, (q15_t)0x8e20, + (q15_t)0x3a6c, (q15_t)0x8e1d, (q15_t)0x3a67, (q15_t)0x8e1a, (q15_t)0x3a61, (q15_t)0x8e17, (q15_t)0x3a5c, (q15_t)0x8e15, + (q15_t)0x3a56, (q15_t)0x8e12, (q15_t)0x3a50, (q15_t)0x8e0f, (q15_t)0x3a4b, (q15_t)0x8e0c, (q15_t)0x3a45, (q15_t)0x8e09, + (q15_t)0x3a40, (q15_t)0x8e06, (q15_t)0x3a3a, (q15_t)0x8e03, (q15_t)0x3a34, (q15_t)0x8e01, (q15_t)0x3a2f, (q15_t)0x8dfe, + (q15_t)0x3a29, (q15_t)0x8dfb, (q15_t)0x3a24, (q15_t)0x8df8, (q15_t)0x3a1e, (q15_t)0x8df5, (q15_t)0x3a19, (q15_t)0x8df2, + (q15_t)0x3a13, (q15_t)0x8def, (q15_t)0x3a0d, (q15_t)0x8ded, (q15_t)0x3a08, (q15_t)0x8dea, (q15_t)0x3a02, (q15_t)0x8de7, + (q15_t)0x39fd, (q15_t)0x8de4, (q15_t)0x39f7, (q15_t)0x8de1, (q15_t)0x39f1, (q15_t)0x8dde, (q15_t)0x39ec, (q15_t)0x8ddc, + (q15_t)0x39e6, (q15_t)0x8dd9, (q15_t)0x39e0, (q15_t)0x8dd6, (q15_t)0x39db, (q15_t)0x8dd3, (q15_t)0x39d5, (q15_t)0x8dd0, + (q15_t)0x39d0, (q15_t)0x8dcd, (q15_t)0x39ca, (q15_t)0x8dca, (q15_t)0x39c4, (q15_t)0x8dc8, (q15_t)0x39bf, (q15_t)0x8dc5, + (q15_t)0x39b9, (q15_t)0x8dc2, (q15_t)0x39b4, (q15_t)0x8dbf, (q15_t)0x39ae, (q15_t)0x8dbc, (q15_t)0x39a8, (q15_t)0x8db9, + (q15_t)0x39a3, (q15_t)0x8db7, (q15_t)0x399d, (q15_t)0x8db4, (q15_t)0x3998, (q15_t)0x8db1, (q15_t)0x3992, (q15_t)0x8dae, + (q15_t)0x398c, (q15_t)0x8dab, (q15_t)0x3987, (q15_t)0x8da9, (q15_t)0x3981, (q15_t)0x8da6, (q15_t)0x397c, (q15_t)0x8da3, + (q15_t)0x3976, (q15_t)0x8da0, (q15_t)0x3970, (q15_t)0x8d9d, (q15_t)0x396b, (q15_t)0x8d9a, (q15_t)0x3965, (q15_t)0x8d98, + (q15_t)0x395f, (q15_t)0x8d95, (q15_t)0x395a, (q15_t)0x8d92, (q15_t)0x3954, (q15_t)0x8d8f, (q15_t)0x394f, (q15_t)0x8d8c, + (q15_t)0x3949, (q15_t)0x8d8a, (q15_t)0x3943, (q15_t)0x8d87, (q15_t)0x393e, (q15_t)0x8d84, (q15_t)0x3938, (q15_t)0x8d81, + (q15_t)0x3932, (q15_t)0x8d7e, (q15_t)0x392d, (q15_t)0x8d7b, (q15_t)0x3927, (q15_t)0x8d79, (q15_t)0x3922, (q15_t)0x8d76, + (q15_t)0x391c, (q15_t)0x8d73, (q15_t)0x3916, (q15_t)0x8d70, (q15_t)0x3911, (q15_t)0x8d6d, (q15_t)0x390b, (q15_t)0x8d6b, + (q15_t)0x3906, (q15_t)0x8d68, (q15_t)0x3900, (q15_t)0x8d65, (q15_t)0x38fa, (q15_t)0x8d62, (q15_t)0x38f5, (q15_t)0x8d5f, + (q15_t)0x38ef, (q15_t)0x8d5d, (q15_t)0x38e9, (q15_t)0x8d5a, (q15_t)0x38e4, (q15_t)0x8d57, (q15_t)0x38de, (q15_t)0x8d54, + (q15_t)0x38d8, (q15_t)0x8d51, (q15_t)0x38d3, (q15_t)0x8d4f, (q15_t)0x38cd, (q15_t)0x8d4c, (q15_t)0x38c8, (q15_t)0x8d49, + (q15_t)0x38c2, (q15_t)0x8d46, (q15_t)0x38bc, (q15_t)0x8d44, (q15_t)0x38b7, (q15_t)0x8d41, (q15_t)0x38b1, (q15_t)0x8d3e, + (q15_t)0x38ab, (q15_t)0x8d3b, (q15_t)0x38a6, (q15_t)0x8d38, (q15_t)0x38a0, (q15_t)0x8d36, (q15_t)0x389b, (q15_t)0x8d33, + (q15_t)0x3895, (q15_t)0x8d30, (q15_t)0x388f, (q15_t)0x8d2d, (q15_t)0x388a, (q15_t)0x8d2b, (q15_t)0x3884, (q15_t)0x8d28, + (q15_t)0x387e, (q15_t)0x8d25, (q15_t)0x3879, (q15_t)0x8d22, (q15_t)0x3873, (q15_t)0x8d1f, (q15_t)0x386d, (q15_t)0x8d1d, + (q15_t)0x3868, (q15_t)0x8d1a, (q15_t)0x3862, (q15_t)0x8d17, (q15_t)0x385d, (q15_t)0x8d14, (q15_t)0x3857, (q15_t)0x8d12, + (q15_t)0x3851, (q15_t)0x8d0f, (q15_t)0x384c, (q15_t)0x8d0c, (q15_t)0x3846, (q15_t)0x8d09, (q15_t)0x3840, (q15_t)0x8d07, + (q15_t)0x383b, (q15_t)0x8d04, (q15_t)0x3835, (q15_t)0x8d01, (q15_t)0x382f, (q15_t)0x8cfe, (q15_t)0x382a, (q15_t)0x8cfb, + (q15_t)0x3824, (q15_t)0x8cf9, (q15_t)0x381e, (q15_t)0x8cf6, (q15_t)0x3819, (q15_t)0x8cf3, (q15_t)0x3813, (q15_t)0x8cf0, + (q15_t)0x380d, (q15_t)0x8cee, (q15_t)0x3808, (q15_t)0x8ceb, (q15_t)0x3802, (q15_t)0x8ce8, (q15_t)0x37fd, (q15_t)0x8ce5, + (q15_t)0x37f7, (q15_t)0x8ce3, (q15_t)0x37f1, (q15_t)0x8ce0, (q15_t)0x37ec, (q15_t)0x8cdd, (q15_t)0x37e6, (q15_t)0x8cda, + (q15_t)0x37e0, (q15_t)0x8cd8, (q15_t)0x37db, (q15_t)0x8cd5, (q15_t)0x37d5, (q15_t)0x8cd2, (q15_t)0x37cf, (q15_t)0x8cd0, + (q15_t)0x37ca, (q15_t)0x8ccd, (q15_t)0x37c4, (q15_t)0x8cca, (q15_t)0x37be, (q15_t)0x8cc7, (q15_t)0x37b9, (q15_t)0x8cc5, + (q15_t)0x37b3, (q15_t)0x8cc2, (q15_t)0x37ad, (q15_t)0x8cbf, (q15_t)0x37a8, (q15_t)0x8cbc, (q15_t)0x37a2, (q15_t)0x8cba, + (q15_t)0x379c, (q15_t)0x8cb7, (q15_t)0x3797, (q15_t)0x8cb4, (q15_t)0x3791, (q15_t)0x8cb1, (q15_t)0x378b, (q15_t)0x8caf, + (q15_t)0x3786, (q15_t)0x8cac, (q15_t)0x3780, (q15_t)0x8ca9, (q15_t)0x377a, (q15_t)0x8ca7, (q15_t)0x3775, (q15_t)0x8ca4, + (q15_t)0x376f, (q15_t)0x8ca1, (q15_t)0x3769, (q15_t)0x8c9e, (q15_t)0x3764, (q15_t)0x8c9c, (q15_t)0x375e, (q15_t)0x8c99, + (q15_t)0x3758, (q15_t)0x8c96, (q15_t)0x3753, (q15_t)0x8c94, (q15_t)0x374d, (q15_t)0x8c91, (q15_t)0x3747, (q15_t)0x8c8e, + (q15_t)0x3742, (q15_t)0x8c8b, (q15_t)0x373c, (q15_t)0x8c89, (q15_t)0x3736, (q15_t)0x8c86, (q15_t)0x3731, (q15_t)0x8c83, + (q15_t)0x372b, (q15_t)0x8c81, (q15_t)0x3725, (q15_t)0x8c7e, (q15_t)0x3720, (q15_t)0x8c7b, (q15_t)0x371a, (q15_t)0x8c78, + (q15_t)0x3714, (q15_t)0x8c76, (q15_t)0x370f, (q15_t)0x8c73, (q15_t)0x3709, (q15_t)0x8c70, (q15_t)0x3703, (q15_t)0x8c6e, + (q15_t)0x36fe, (q15_t)0x8c6b, (q15_t)0x36f8, (q15_t)0x8c68, (q15_t)0x36f2, (q15_t)0x8c65, (q15_t)0x36ed, (q15_t)0x8c63, + (q15_t)0x36e7, (q15_t)0x8c60, (q15_t)0x36e1, (q15_t)0x8c5d, (q15_t)0x36dc, (q15_t)0x8c5b, (q15_t)0x36d6, (q15_t)0x8c58, + (q15_t)0x36d0, (q15_t)0x8c55, (q15_t)0x36cb, (q15_t)0x8c53, (q15_t)0x36c5, (q15_t)0x8c50, (q15_t)0x36bf, (q15_t)0x8c4d, + (q15_t)0x36ba, (q15_t)0x8c4b, (q15_t)0x36b4, (q15_t)0x8c48, (q15_t)0x36ae, (q15_t)0x8c45, (q15_t)0x36a9, (q15_t)0x8c43, + (q15_t)0x36a3, (q15_t)0x8c40, (q15_t)0x369d, (q15_t)0x8c3d, (q15_t)0x3698, (q15_t)0x8c3a, (q15_t)0x3692, (q15_t)0x8c38, + (q15_t)0x368c, (q15_t)0x8c35, (q15_t)0x3686, (q15_t)0x8c32, (q15_t)0x3681, (q15_t)0x8c30, (q15_t)0x367b, (q15_t)0x8c2d, + (q15_t)0x3675, (q15_t)0x8c2a, (q15_t)0x3670, (q15_t)0x8c28, (q15_t)0x366a, (q15_t)0x8c25, (q15_t)0x3664, (q15_t)0x8c22, + (q15_t)0x365f, (q15_t)0x8c20, (q15_t)0x3659, (q15_t)0x8c1d, (q15_t)0x3653, (q15_t)0x8c1a, (q15_t)0x364e, (q15_t)0x8c18, + (q15_t)0x3648, (q15_t)0x8c15, (q15_t)0x3642, (q15_t)0x8c12, (q15_t)0x363d, (q15_t)0x8c10, (q15_t)0x3637, (q15_t)0x8c0d, + (q15_t)0x3631, (q15_t)0x8c0a, (q15_t)0x362b, (q15_t)0x8c08, (q15_t)0x3626, (q15_t)0x8c05, (q15_t)0x3620, (q15_t)0x8c02, + (q15_t)0x361a, (q15_t)0x8c00, (q15_t)0x3615, (q15_t)0x8bfd, (q15_t)0x360f, (q15_t)0x8bfa, (q15_t)0x3609, (q15_t)0x8bf8, + (q15_t)0x3604, (q15_t)0x8bf5, (q15_t)0x35fe, (q15_t)0x8bf3, (q15_t)0x35f8, (q15_t)0x8bf0, (q15_t)0x35f3, (q15_t)0x8bed, + (q15_t)0x35ed, (q15_t)0x8beb, (q15_t)0x35e7, (q15_t)0x8be8, (q15_t)0x35e1, (q15_t)0x8be5, (q15_t)0x35dc, (q15_t)0x8be3, + (q15_t)0x35d6, (q15_t)0x8be0, (q15_t)0x35d0, (q15_t)0x8bdd, (q15_t)0x35cb, (q15_t)0x8bdb, (q15_t)0x35c5, (q15_t)0x8bd8, + (q15_t)0x35bf, (q15_t)0x8bd5, (q15_t)0x35ba, (q15_t)0x8bd3, (q15_t)0x35b4, (q15_t)0x8bd0, (q15_t)0x35ae, (q15_t)0x8bce, + (q15_t)0x35a8, (q15_t)0x8bcb, (q15_t)0x35a3, (q15_t)0x8bc8, (q15_t)0x359d, (q15_t)0x8bc6, (q15_t)0x3597, (q15_t)0x8bc3, + (q15_t)0x3592, (q15_t)0x8bc0, (q15_t)0x358c, (q15_t)0x8bbe, (q15_t)0x3586, (q15_t)0x8bbb, (q15_t)0x3580, (q15_t)0x8bb8, + (q15_t)0x357b, (q15_t)0x8bb6, (q15_t)0x3575, (q15_t)0x8bb3, (q15_t)0x356f, (q15_t)0x8bb1, (q15_t)0x356a, (q15_t)0x8bae, + (q15_t)0x3564, (q15_t)0x8bab, (q15_t)0x355e, (q15_t)0x8ba9, (q15_t)0x3558, (q15_t)0x8ba6, (q15_t)0x3553, (q15_t)0x8ba4, + (q15_t)0x354d, (q15_t)0x8ba1, (q15_t)0x3547, (q15_t)0x8b9e, (q15_t)0x3542, (q15_t)0x8b9c, (q15_t)0x353c, (q15_t)0x8b99, + (q15_t)0x3536, (q15_t)0x8b96, (q15_t)0x3530, (q15_t)0x8b94, (q15_t)0x352b, (q15_t)0x8b91, (q15_t)0x3525, (q15_t)0x8b8f, + (q15_t)0x351f, (q15_t)0x8b8c, (q15_t)0x351a, (q15_t)0x8b89, (q15_t)0x3514, (q15_t)0x8b87, (q15_t)0x350e, (q15_t)0x8b84, + (q15_t)0x3508, (q15_t)0x8b82, (q15_t)0x3503, (q15_t)0x8b7f, (q15_t)0x34fd, (q15_t)0x8b7c, (q15_t)0x34f7, (q15_t)0x8b7a, + (q15_t)0x34f2, (q15_t)0x8b77, (q15_t)0x34ec, (q15_t)0x8b75, (q15_t)0x34e6, (q15_t)0x8b72, (q15_t)0x34e0, (q15_t)0x8b6f, + (q15_t)0x34db, (q15_t)0x8b6d, (q15_t)0x34d5, (q15_t)0x8b6a, (q15_t)0x34cf, (q15_t)0x8b68, (q15_t)0x34ca, (q15_t)0x8b65, + (q15_t)0x34c4, (q15_t)0x8b62, (q15_t)0x34be, (q15_t)0x8b60, (q15_t)0x34b8, (q15_t)0x8b5d, (q15_t)0x34b3, (q15_t)0x8b5b, + (q15_t)0x34ad, (q15_t)0x8b58, (q15_t)0x34a7, (q15_t)0x8b55, (q15_t)0x34a1, (q15_t)0x8b53, (q15_t)0x349c, (q15_t)0x8b50, + (q15_t)0x3496, (q15_t)0x8b4e, (q15_t)0x3490, (q15_t)0x8b4b, (q15_t)0x348b, (q15_t)0x8b49, (q15_t)0x3485, (q15_t)0x8b46, + (q15_t)0x347f, (q15_t)0x8b43, (q15_t)0x3479, (q15_t)0x8b41, (q15_t)0x3474, (q15_t)0x8b3e, (q15_t)0x346e, (q15_t)0x8b3c, + (q15_t)0x3468, (q15_t)0x8b39, (q15_t)0x3462, (q15_t)0x8b37, (q15_t)0x345d, (q15_t)0x8b34, (q15_t)0x3457, (q15_t)0x8b31, + (q15_t)0x3451, (q15_t)0x8b2f, (q15_t)0x344b, (q15_t)0x8b2c, (q15_t)0x3446, (q15_t)0x8b2a, (q15_t)0x3440, (q15_t)0x8b27, + (q15_t)0x343a, (q15_t)0x8b25, (q15_t)0x3435, (q15_t)0x8b22, (q15_t)0x342f, (q15_t)0x8b1f, (q15_t)0x3429, (q15_t)0x8b1d, + (q15_t)0x3423, (q15_t)0x8b1a, (q15_t)0x341e, (q15_t)0x8b18, (q15_t)0x3418, (q15_t)0x8b15, (q15_t)0x3412, (q15_t)0x8b13, + (q15_t)0x340c, (q15_t)0x8b10, (q15_t)0x3407, (q15_t)0x8b0e, (q15_t)0x3401, (q15_t)0x8b0b, (q15_t)0x33fb, (q15_t)0x8b08, + (q15_t)0x33f5, (q15_t)0x8b06, (q15_t)0x33f0, (q15_t)0x8b03, (q15_t)0x33ea, (q15_t)0x8b01, (q15_t)0x33e4, (q15_t)0x8afe, + (q15_t)0x33de, (q15_t)0x8afc, (q15_t)0x33d9, (q15_t)0x8af9, (q15_t)0x33d3, (q15_t)0x8af7, (q15_t)0x33cd, (q15_t)0x8af4, + (q15_t)0x33c7, (q15_t)0x8af1, (q15_t)0x33c2, (q15_t)0x8aef, (q15_t)0x33bc, (q15_t)0x8aec, (q15_t)0x33b6, (q15_t)0x8aea, + (q15_t)0x33b0, (q15_t)0x8ae7, (q15_t)0x33ab, (q15_t)0x8ae5, (q15_t)0x33a5, (q15_t)0x8ae2, (q15_t)0x339f, (q15_t)0x8ae0, + (q15_t)0x3399, (q15_t)0x8add, (q15_t)0x3394, (q15_t)0x8adb, (q15_t)0x338e, (q15_t)0x8ad8, (q15_t)0x3388, (q15_t)0x8ad6, + (q15_t)0x3382, (q15_t)0x8ad3, (q15_t)0x337d, (q15_t)0x8ad1, (q15_t)0x3377, (q15_t)0x8ace, (q15_t)0x3371, (q15_t)0x8acb, + (q15_t)0x336b, (q15_t)0x8ac9, (q15_t)0x3366, (q15_t)0x8ac6, (q15_t)0x3360, (q15_t)0x8ac4, (q15_t)0x335a, (q15_t)0x8ac1, + (q15_t)0x3354, (q15_t)0x8abf, (q15_t)0x334f, (q15_t)0x8abc, (q15_t)0x3349, (q15_t)0x8aba, (q15_t)0x3343, (q15_t)0x8ab7, + (q15_t)0x333d, (q15_t)0x8ab5, (q15_t)0x3338, (q15_t)0x8ab2, (q15_t)0x3332, (q15_t)0x8ab0, (q15_t)0x332c, (q15_t)0x8aad, + (q15_t)0x3326, (q15_t)0x8aab, (q15_t)0x3321, (q15_t)0x8aa8, (q15_t)0x331b, (q15_t)0x8aa6, (q15_t)0x3315, (q15_t)0x8aa3, + (q15_t)0x330f, (q15_t)0x8aa1, (q15_t)0x330a, (q15_t)0x8a9e, (q15_t)0x3304, (q15_t)0x8a9c, (q15_t)0x32fe, (q15_t)0x8a99, + (q15_t)0x32f8, (q15_t)0x8a97, (q15_t)0x32f3, (q15_t)0x8a94, (q15_t)0x32ed, (q15_t)0x8a92, (q15_t)0x32e7, (q15_t)0x8a8f, + (q15_t)0x32e1, (q15_t)0x8a8d, (q15_t)0x32db, (q15_t)0x8a8a, (q15_t)0x32d6, (q15_t)0x8a88, (q15_t)0x32d0, (q15_t)0x8a85, + (q15_t)0x32ca, (q15_t)0x8a83, (q15_t)0x32c4, (q15_t)0x8a80, (q15_t)0x32bf, (q15_t)0x8a7e, (q15_t)0x32b9, (q15_t)0x8a7b, + (q15_t)0x32b3, (q15_t)0x8a79, (q15_t)0x32ad, (q15_t)0x8a76, (q15_t)0x32a8, (q15_t)0x8a74, (q15_t)0x32a2, (q15_t)0x8a71, + (q15_t)0x329c, (q15_t)0x8a6f, (q15_t)0x3296, (q15_t)0x8a6c, (q15_t)0x3290, (q15_t)0x8a6a, (q15_t)0x328b, (q15_t)0x8a67, + (q15_t)0x3285, (q15_t)0x8a65, (q15_t)0x327f, (q15_t)0x8a62, (q15_t)0x3279, (q15_t)0x8a60, (q15_t)0x3274, (q15_t)0x8a5d, + (q15_t)0x326e, (q15_t)0x8a5b, (q15_t)0x3268, (q15_t)0x8a59, (q15_t)0x3262, (q15_t)0x8a56, (q15_t)0x325d, (q15_t)0x8a54, + (q15_t)0x3257, (q15_t)0x8a51, (q15_t)0x3251, (q15_t)0x8a4f, (q15_t)0x324b, (q15_t)0x8a4c, (q15_t)0x3245, (q15_t)0x8a4a, + (q15_t)0x3240, (q15_t)0x8a47, (q15_t)0x323a, (q15_t)0x8a45, (q15_t)0x3234, (q15_t)0x8a42, (q15_t)0x322e, (q15_t)0x8a40, + (q15_t)0x3228, (q15_t)0x8a3d, (q15_t)0x3223, (q15_t)0x8a3b, (q15_t)0x321d, (q15_t)0x8a38, (q15_t)0x3217, (q15_t)0x8a36, + (q15_t)0x3211, (q15_t)0x8a34, (q15_t)0x320c, (q15_t)0x8a31, (q15_t)0x3206, (q15_t)0x8a2f, (q15_t)0x3200, (q15_t)0x8a2c, + (q15_t)0x31fa, (q15_t)0x8a2a, (q15_t)0x31f4, (q15_t)0x8a27, (q15_t)0x31ef, (q15_t)0x8a25, (q15_t)0x31e9, (q15_t)0x8a22, + (q15_t)0x31e3, (q15_t)0x8a20, (q15_t)0x31dd, (q15_t)0x8a1d, (q15_t)0x31d8, (q15_t)0x8a1b, (q15_t)0x31d2, (q15_t)0x8a19, + (q15_t)0x31cc, (q15_t)0x8a16, (q15_t)0x31c6, (q15_t)0x8a14, (q15_t)0x31c0, (q15_t)0x8a11, (q15_t)0x31bb, (q15_t)0x8a0f, + (q15_t)0x31b5, (q15_t)0x8a0c, (q15_t)0x31af, (q15_t)0x8a0a, (q15_t)0x31a9, (q15_t)0x8a07, (q15_t)0x31a3, (q15_t)0x8a05, + (q15_t)0x319e, (q15_t)0x8a03, (q15_t)0x3198, (q15_t)0x8a00, (q15_t)0x3192, (q15_t)0x89fe, (q15_t)0x318c, (q15_t)0x89fb, + (q15_t)0x3186, (q15_t)0x89f9, (q15_t)0x3181, (q15_t)0x89f6, (q15_t)0x317b, (q15_t)0x89f4, (q15_t)0x3175, (q15_t)0x89f2, + (q15_t)0x316f, (q15_t)0x89ef, (q15_t)0x3169, (q15_t)0x89ed, (q15_t)0x3164, (q15_t)0x89ea, (q15_t)0x315e, (q15_t)0x89e8, + (q15_t)0x3158, (q15_t)0x89e5, (q15_t)0x3152, (q15_t)0x89e3, (q15_t)0x314c, (q15_t)0x89e1, (q15_t)0x3147, (q15_t)0x89de, + (q15_t)0x3141, (q15_t)0x89dc, (q15_t)0x313b, (q15_t)0x89d9, (q15_t)0x3135, (q15_t)0x89d7, (q15_t)0x312f, (q15_t)0x89d5, + (q15_t)0x312a, (q15_t)0x89d2, (q15_t)0x3124, (q15_t)0x89d0, (q15_t)0x311e, (q15_t)0x89cd, (q15_t)0x3118, (q15_t)0x89cb, + (q15_t)0x3112, (q15_t)0x89c8, (q15_t)0x310d, (q15_t)0x89c6, (q15_t)0x3107, (q15_t)0x89c4, (q15_t)0x3101, (q15_t)0x89c1, + (q15_t)0x30fb, (q15_t)0x89bf, (q15_t)0x30f5, (q15_t)0x89bc, (q15_t)0x30f0, (q15_t)0x89ba, (q15_t)0x30ea, (q15_t)0x89b8, + (q15_t)0x30e4, (q15_t)0x89b5, (q15_t)0x30de, (q15_t)0x89b3, (q15_t)0x30d8, (q15_t)0x89b0, (q15_t)0x30d3, (q15_t)0x89ae, + (q15_t)0x30cd, (q15_t)0x89ac, (q15_t)0x30c7, (q15_t)0x89a9, (q15_t)0x30c1, (q15_t)0x89a7, (q15_t)0x30bb, (q15_t)0x89a4, + (q15_t)0x30b6, (q15_t)0x89a2, (q15_t)0x30b0, (q15_t)0x89a0, (q15_t)0x30aa, (q15_t)0x899d, (q15_t)0x30a4, (q15_t)0x899b, + (q15_t)0x309e, (q15_t)0x8998, (q15_t)0x3099, (q15_t)0x8996, (q15_t)0x3093, (q15_t)0x8994, (q15_t)0x308d, (q15_t)0x8991, + (q15_t)0x3087, (q15_t)0x898f, (q15_t)0x3081, (q15_t)0x898d, (q15_t)0x307b, (q15_t)0x898a, (q15_t)0x3076, (q15_t)0x8988, + (q15_t)0x3070, (q15_t)0x8985, (q15_t)0x306a, (q15_t)0x8983, (q15_t)0x3064, (q15_t)0x8981, (q15_t)0x305e, (q15_t)0x897e, + (q15_t)0x3059, (q15_t)0x897c, (q15_t)0x3053, (q15_t)0x897a, (q15_t)0x304d, (q15_t)0x8977, (q15_t)0x3047, (q15_t)0x8975, + (q15_t)0x3041, (q15_t)0x8972, (q15_t)0x303b, (q15_t)0x8970, (q15_t)0x3036, (q15_t)0x896e, (q15_t)0x3030, (q15_t)0x896b, + (q15_t)0x302a, (q15_t)0x8969, (q15_t)0x3024, (q15_t)0x8967, (q15_t)0x301e, (q15_t)0x8964, (q15_t)0x3019, (q15_t)0x8962, + (q15_t)0x3013, (q15_t)0x8960, (q15_t)0x300d, (q15_t)0x895d, (q15_t)0x3007, (q15_t)0x895b, (q15_t)0x3001, (q15_t)0x8958, + (q15_t)0x2ffb, (q15_t)0x8956, (q15_t)0x2ff6, (q15_t)0x8954, (q15_t)0x2ff0, (q15_t)0x8951, (q15_t)0x2fea, (q15_t)0x894f, + (q15_t)0x2fe4, (q15_t)0x894d, (q15_t)0x2fde, (q15_t)0x894a, (q15_t)0x2fd8, (q15_t)0x8948, (q15_t)0x2fd3, (q15_t)0x8946, + (q15_t)0x2fcd, (q15_t)0x8943, (q15_t)0x2fc7, (q15_t)0x8941, (q15_t)0x2fc1, (q15_t)0x893f, (q15_t)0x2fbb, (q15_t)0x893c, + (q15_t)0x2fb5, (q15_t)0x893a, (q15_t)0x2fb0, (q15_t)0x8938, (q15_t)0x2faa, (q15_t)0x8935, (q15_t)0x2fa4, (q15_t)0x8933, + (q15_t)0x2f9e, (q15_t)0x8931, (q15_t)0x2f98, (q15_t)0x892e, (q15_t)0x2f92, (q15_t)0x892c, (q15_t)0x2f8d, (q15_t)0x892a, + (q15_t)0x2f87, (q15_t)0x8927, (q15_t)0x2f81, (q15_t)0x8925, (q15_t)0x2f7b, (q15_t)0x8923, (q15_t)0x2f75, (q15_t)0x8920, + (q15_t)0x2f6f, (q15_t)0x891e, (q15_t)0x2f6a, (q15_t)0x891c, (q15_t)0x2f64, (q15_t)0x8919, (q15_t)0x2f5e, (q15_t)0x8917, + (q15_t)0x2f58, (q15_t)0x8915, (q15_t)0x2f52, (q15_t)0x8912, (q15_t)0x2f4c, (q15_t)0x8910, (q15_t)0x2f47, (q15_t)0x890e, + (q15_t)0x2f41, (q15_t)0x890b, (q15_t)0x2f3b, (q15_t)0x8909, (q15_t)0x2f35, (q15_t)0x8907, (q15_t)0x2f2f, (q15_t)0x8904, + (q15_t)0x2f29, (q15_t)0x8902, (q15_t)0x2f24, (q15_t)0x8900, (q15_t)0x2f1e, (q15_t)0x88fd, (q15_t)0x2f18, (q15_t)0x88fb, + (q15_t)0x2f12, (q15_t)0x88f9, (q15_t)0x2f0c, (q15_t)0x88f6, (q15_t)0x2f06, (q15_t)0x88f4, (q15_t)0x2f01, (q15_t)0x88f2, + (q15_t)0x2efb, (q15_t)0x88f0, (q15_t)0x2ef5, (q15_t)0x88ed, (q15_t)0x2eef, (q15_t)0x88eb, (q15_t)0x2ee9, (q15_t)0x88e9, + (q15_t)0x2ee3, (q15_t)0x88e6, (q15_t)0x2edd, (q15_t)0x88e4, (q15_t)0x2ed8, (q15_t)0x88e2, (q15_t)0x2ed2, (q15_t)0x88df, + (q15_t)0x2ecc, (q15_t)0x88dd, (q15_t)0x2ec6, (q15_t)0x88db, (q15_t)0x2ec0, (q15_t)0x88d9, (q15_t)0x2eba, (q15_t)0x88d6, + (q15_t)0x2eb5, (q15_t)0x88d4, (q15_t)0x2eaf, (q15_t)0x88d2, (q15_t)0x2ea9, (q15_t)0x88cf, (q15_t)0x2ea3, (q15_t)0x88cd, + (q15_t)0x2e9d, (q15_t)0x88cb, (q15_t)0x2e97, (q15_t)0x88c8, (q15_t)0x2e91, (q15_t)0x88c6, (q15_t)0x2e8c, (q15_t)0x88c4, + (q15_t)0x2e86, (q15_t)0x88c2, (q15_t)0x2e80, (q15_t)0x88bf, (q15_t)0x2e7a, (q15_t)0x88bd, (q15_t)0x2e74, (q15_t)0x88bb, + (q15_t)0x2e6e, (q15_t)0x88b9, (q15_t)0x2e68, (q15_t)0x88b6, (q15_t)0x2e63, (q15_t)0x88b4, (q15_t)0x2e5d, (q15_t)0x88b2, + (q15_t)0x2e57, (q15_t)0x88af, (q15_t)0x2e51, (q15_t)0x88ad, (q15_t)0x2e4b, (q15_t)0x88ab, (q15_t)0x2e45, (q15_t)0x88a9, + (q15_t)0x2e3f, (q15_t)0x88a6, (q15_t)0x2e3a, (q15_t)0x88a4, (q15_t)0x2e34, (q15_t)0x88a2, (q15_t)0x2e2e, (q15_t)0x88a0, + (q15_t)0x2e28, (q15_t)0x889d, (q15_t)0x2e22, (q15_t)0x889b, (q15_t)0x2e1c, (q15_t)0x8899, (q15_t)0x2e16, (q15_t)0x8896, + (q15_t)0x2e11, (q15_t)0x8894, (q15_t)0x2e0b, (q15_t)0x8892, (q15_t)0x2e05, (q15_t)0x8890, (q15_t)0x2dff, (q15_t)0x888d, + (q15_t)0x2df9, (q15_t)0x888b, (q15_t)0x2df3, (q15_t)0x8889, (q15_t)0x2ded, (q15_t)0x8887, (q15_t)0x2de7, (q15_t)0x8884, + (q15_t)0x2de2, (q15_t)0x8882, (q15_t)0x2ddc, (q15_t)0x8880, (q15_t)0x2dd6, (q15_t)0x887e, (q15_t)0x2dd0, (q15_t)0x887b, + (q15_t)0x2dca, (q15_t)0x8879, (q15_t)0x2dc4, (q15_t)0x8877, (q15_t)0x2dbe, (q15_t)0x8875, (q15_t)0x2db9, (q15_t)0x8872, + (q15_t)0x2db3, (q15_t)0x8870, (q15_t)0x2dad, (q15_t)0x886e, (q15_t)0x2da7, (q15_t)0x886c, (q15_t)0x2da1, (q15_t)0x8869, + (q15_t)0x2d9b, (q15_t)0x8867, (q15_t)0x2d95, (q15_t)0x8865, (q15_t)0x2d8f, (q15_t)0x8863, (q15_t)0x2d8a, (q15_t)0x8860, + (q15_t)0x2d84, (q15_t)0x885e, (q15_t)0x2d7e, (q15_t)0x885c, (q15_t)0x2d78, (q15_t)0x885a, (q15_t)0x2d72, (q15_t)0x8858, + (q15_t)0x2d6c, (q15_t)0x8855, (q15_t)0x2d66, (q15_t)0x8853, (q15_t)0x2d60, (q15_t)0x8851, (q15_t)0x2d5b, (q15_t)0x884f, + (q15_t)0x2d55, (q15_t)0x884c, (q15_t)0x2d4f, (q15_t)0x884a, (q15_t)0x2d49, (q15_t)0x8848, (q15_t)0x2d43, (q15_t)0x8846, + (q15_t)0x2d3d, (q15_t)0x8844, (q15_t)0x2d37, (q15_t)0x8841, (q15_t)0x2d31, (q15_t)0x883f, (q15_t)0x2d2c, (q15_t)0x883d, + (q15_t)0x2d26, (q15_t)0x883b, (q15_t)0x2d20, (q15_t)0x8838, (q15_t)0x2d1a, (q15_t)0x8836, (q15_t)0x2d14, (q15_t)0x8834, + (q15_t)0x2d0e, (q15_t)0x8832, (q15_t)0x2d08, (q15_t)0x8830, (q15_t)0x2d02, (q15_t)0x882d, (q15_t)0x2cfd, (q15_t)0x882b, + (q15_t)0x2cf7, (q15_t)0x8829, (q15_t)0x2cf1, (q15_t)0x8827, (q15_t)0x2ceb, (q15_t)0x8825, (q15_t)0x2ce5, (q15_t)0x8822, + (q15_t)0x2cdf, (q15_t)0x8820, (q15_t)0x2cd9, (q15_t)0x881e, (q15_t)0x2cd3, (q15_t)0x881c, (q15_t)0x2ccd, (q15_t)0x881a, + (q15_t)0x2cc8, (q15_t)0x8817, (q15_t)0x2cc2, (q15_t)0x8815, (q15_t)0x2cbc, (q15_t)0x8813, (q15_t)0x2cb6, (q15_t)0x8811, + (q15_t)0x2cb0, (q15_t)0x880f, (q15_t)0x2caa, (q15_t)0x880c, (q15_t)0x2ca4, (q15_t)0x880a, (q15_t)0x2c9e, (q15_t)0x8808, + (q15_t)0x2c98, (q15_t)0x8806, (q15_t)0x2c93, (q15_t)0x8804, (q15_t)0x2c8d, (q15_t)0x8801, (q15_t)0x2c87, (q15_t)0x87ff, + (q15_t)0x2c81, (q15_t)0x87fd, (q15_t)0x2c7b, (q15_t)0x87fb, (q15_t)0x2c75, (q15_t)0x87f9, (q15_t)0x2c6f, (q15_t)0x87f6, + (q15_t)0x2c69, (q15_t)0x87f4, (q15_t)0x2c63, (q15_t)0x87f2, (q15_t)0x2c5e, (q15_t)0x87f0, (q15_t)0x2c58, (q15_t)0x87ee, + (q15_t)0x2c52, (q15_t)0x87ec, (q15_t)0x2c4c, (q15_t)0x87e9, (q15_t)0x2c46, (q15_t)0x87e7, (q15_t)0x2c40, (q15_t)0x87e5, + (q15_t)0x2c3a, (q15_t)0x87e3, (q15_t)0x2c34, (q15_t)0x87e1, (q15_t)0x2c2e, (q15_t)0x87df, (q15_t)0x2c29, (q15_t)0x87dc, + (q15_t)0x2c23, (q15_t)0x87da, (q15_t)0x2c1d, (q15_t)0x87d8, (q15_t)0x2c17, (q15_t)0x87d6, (q15_t)0x2c11, (q15_t)0x87d4, + (q15_t)0x2c0b, (q15_t)0x87d2, (q15_t)0x2c05, (q15_t)0x87cf, (q15_t)0x2bff, (q15_t)0x87cd, (q15_t)0x2bf9, (q15_t)0x87cb, + (q15_t)0x2bf3, (q15_t)0x87c9, (q15_t)0x2bee, (q15_t)0x87c7, (q15_t)0x2be8, (q15_t)0x87c5, (q15_t)0x2be2, (q15_t)0x87c2, + (q15_t)0x2bdc, (q15_t)0x87c0, (q15_t)0x2bd6, (q15_t)0x87be, (q15_t)0x2bd0, (q15_t)0x87bc, (q15_t)0x2bca, (q15_t)0x87ba, + (q15_t)0x2bc4, (q15_t)0x87b8, (q15_t)0x2bbe, (q15_t)0x87b6, (q15_t)0x2bb8, (q15_t)0x87b3, (q15_t)0x2bb2, (q15_t)0x87b1, + (q15_t)0x2bad, (q15_t)0x87af, (q15_t)0x2ba7, (q15_t)0x87ad, (q15_t)0x2ba1, (q15_t)0x87ab, (q15_t)0x2b9b, (q15_t)0x87a9, + (q15_t)0x2b95, (q15_t)0x87a7, (q15_t)0x2b8f, (q15_t)0x87a4, (q15_t)0x2b89, (q15_t)0x87a2, (q15_t)0x2b83, (q15_t)0x87a0, + (q15_t)0x2b7d, (q15_t)0x879e, (q15_t)0x2b77, (q15_t)0x879c, (q15_t)0x2b71, (q15_t)0x879a, (q15_t)0x2b6c, (q15_t)0x8798, + (q15_t)0x2b66, (q15_t)0x8795, (q15_t)0x2b60, (q15_t)0x8793, (q15_t)0x2b5a, (q15_t)0x8791, (q15_t)0x2b54, (q15_t)0x878f, + (q15_t)0x2b4e, (q15_t)0x878d, (q15_t)0x2b48, (q15_t)0x878b, (q15_t)0x2b42, (q15_t)0x8789, (q15_t)0x2b3c, (q15_t)0x8787, + (q15_t)0x2b36, (q15_t)0x8784, (q15_t)0x2b30, (q15_t)0x8782, (q15_t)0x2b2b, (q15_t)0x8780, (q15_t)0x2b25, (q15_t)0x877e, + (q15_t)0x2b1f, (q15_t)0x877c, (q15_t)0x2b19, (q15_t)0x877a, (q15_t)0x2b13, (q15_t)0x8778, (q15_t)0x2b0d, (q15_t)0x8776, + (q15_t)0x2b07, (q15_t)0x8774, (q15_t)0x2b01, (q15_t)0x8771, (q15_t)0x2afb, (q15_t)0x876f, (q15_t)0x2af5, (q15_t)0x876d, + (q15_t)0x2aef, (q15_t)0x876b, (q15_t)0x2ae9, (q15_t)0x8769, (q15_t)0x2ae4, (q15_t)0x8767, (q15_t)0x2ade, (q15_t)0x8765, + (q15_t)0x2ad8, (q15_t)0x8763, (q15_t)0x2ad2, (q15_t)0x8761, (q15_t)0x2acc, (q15_t)0x875e, (q15_t)0x2ac6, (q15_t)0x875c, + (q15_t)0x2ac0, (q15_t)0x875a, (q15_t)0x2aba, (q15_t)0x8758, (q15_t)0x2ab4, (q15_t)0x8756, (q15_t)0x2aae, (q15_t)0x8754, + (q15_t)0x2aa8, (q15_t)0x8752, (q15_t)0x2aa2, (q15_t)0x8750, (q15_t)0x2a9c, (q15_t)0x874e, (q15_t)0x2a97, (q15_t)0x874c, + (q15_t)0x2a91, (q15_t)0x874a, (q15_t)0x2a8b, (q15_t)0x8747, (q15_t)0x2a85, (q15_t)0x8745, (q15_t)0x2a7f, (q15_t)0x8743, + (q15_t)0x2a79, (q15_t)0x8741, (q15_t)0x2a73, (q15_t)0x873f, (q15_t)0x2a6d, (q15_t)0x873d, (q15_t)0x2a67, (q15_t)0x873b, + (q15_t)0x2a61, (q15_t)0x8739, (q15_t)0x2a5b, (q15_t)0x8737, (q15_t)0x2a55, (q15_t)0x8735, (q15_t)0x2a4f, (q15_t)0x8733, + (q15_t)0x2a49, (q15_t)0x8731, (q15_t)0x2a44, (q15_t)0x872e, (q15_t)0x2a3e, (q15_t)0x872c, (q15_t)0x2a38, (q15_t)0x872a, + (q15_t)0x2a32, (q15_t)0x8728, (q15_t)0x2a2c, (q15_t)0x8726, (q15_t)0x2a26, (q15_t)0x8724, (q15_t)0x2a20, (q15_t)0x8722, + (q15_t)0x2a1a, (q15_t)0x8720, (q15_t)0x2a14, (q15_t)0x871e, (q15_t)0x2a0e, (q15_t)0x871c, (q15_t)0x2a08, (q15_t)0x871a, + (q15_t)0x2a02, (q15_t)0x8718, (q15_t)0x29fc, (q15_t)0x8716, (q15_t)0x29f6, (q15_t)0x8714, (q15_t)0x29f0, (q15_t)0x8712, + (q15_t)0x29eb, (q15_t)0x870f, (q15_t)0x29e5, (q15_t)0x870d, (q15_t)0x29df, (q15_t)0x870b, (q15_t)0x29d9, (q15_t)0x8709, + (q15_t)0x29d3, (q15_t)0x8707, (q15_t)0x29cd, (q15_t)0x8705, (q15_t)0x29c7, (q15_t)0x8703, (q15_t)0x29c1, (q15_t)0x8701, + (q15_t)0x29bb, (q15_t)0x86ff, (q15_t)0x29b5, (q15_t)0x86fd, (q15_t)0x29af, (q15_t)0x86fb, (q15_t)0x29a9, (q15_t)0x86f9, + (q15_t)0x29a3, (q15_t)0x86f7, (q15_t)0x299d, (q15_t)0x86f5, (q15_t)0x2997, (q15_t)0x86f3, (q15_t)0x2991, (q15_t)0x86f1, + (q15_t)0x298b, (q15_t)0x86ef, (q15_t)0x2986, (q15_t)0x86ed, (q15_t)0x2980, (q15_t)0x86eb, (q15_t)0x297a, (q15_t)0x86e9, + (q15_t)0x2974, (q15_t)0x86e7, (q15_t)0x296e, (q15_t)0x86e4, (q15_t)0x2968, (q15_t)0x86e2, (q15_t)0x2962, (q15_t)0x86e0, + (q15_t)0x295c, (q15_t)0x86de, (q15_t)0x2956, (q15_t)0x86dc, (q15_t)0x2950, (q15_t)0x86da, (q15_t)0x294a, (q15_t)0x86d8, + (q15_t)0x2944, (q15_t)0x86d6, (q15_t)0x293e, (q15_t)0x86d4, (q15_t)0x2938, (q15_t)0x86d2, (q15_t)0x2932, (q15_t)0x86d0, + (q15_t)0x292c, (q15_t)0x86ce, (q15_t)0x2926, (q15_t)0x86cc, (q15_t)0x2920, (q15_t)0x86ca, (q15_t)0x291b, (q15_t)0x86c8, + (q15_t)0x2915, (q15_t)0x86c6, (q15_t)0x290f, (q15_t)0x86c4, (q15_t)0x2909, (q15_t)0x86c2, (q15_t)0x2903, (q15_t)0x86c0, + (q15_t)0x28fd, (q15_t)0x86be, (q15_t)0x28f7, (q15_t)0x86bc, (q15_t)0x28f1, (q15_t)0x86ba, (q15_t)0x28eb, (q15_t)0x86b8, + (q15_t)0x28e5, (q15_t)0x86b6, (q15_t)0x28df, (q15_t)0x86b4, (q15_t)0x28d9, (q15_t)0x86b2, (q15_t)0x28d3, (q15_t)0x86b0, + (q15_t)0x28cd, (q15_t)0x86ae, (q15_t)0x28c7, (q15_t)0x86ac, (q15_t)0x28c1, (q15_t)0x86aa, (q15_t)0x28bb, (q15_t)0x86a8, + (q15_t)0x28b5, (q15_t)0x86a6, (q15_t)0x28af, (q15_t)0x86a4, (q15_t)0x28a9, (q15_t)0x86a2, (q15_t)0x28a3, (q15_t)0x86a0, + (q15_t)0x289d, (q15_t)0x869e, (q15_t)0x2898, (q15_t)0x869c, (q15_t)0x2892, (q15_t)0x869a, (q15_t)0x288c, (q15_t)0x8698, + (q15_t)0x2886, (q15_t)0x8696, (q15_t)0x2880, (q15_t)0x8694, (q15_t)0x287a, (q15_t)0x8692, (q15_t)0x2874, (q15_t)0x8690, + (q15_t)0x286e, (q15_t)0x868e, (q15_t)0x2868, (q15_t)0x868c, (q15_t)0x2862, (q15_t)0x868a, (q15_t)0x285c, (q15_t)0x8688, + (q15_t)0x2856, (q15_t)0x8686, (q15_t)0x2850, (q15_t)0x8684, (q15_t)0x284a, (q15_t)0x8682, (q15_t)0x2844, (q15_t)0x8680, + (q15_t)0x283e, (q15_t)0x867e, (q15_t)0x2838, (q15_t)0x867c, (q15_t)0x2832, (q15_t)0x867a, (q15_t)0x282c, (q15_t)0x8678, + (q15_t)0x2826, (q15_t)0x8676, (q15_t)0x2820, (q15_t)0x8674, (q15_t)0x281a, (q15_t)0x8672, (q15_t)0x2814, (q15_t)0x8670, + (q15_t)0x280e, (q15_t)0x866e, (q15_t)0x2808, (q15_t)0x866d, (q15_t)0x2802, (q15_t)0x866b, (q15_t)0x27fc, (q15_t)0x8669, + (q15_t)0x27f6, (q15_t)0x8667, (q15_t)0x27f1, (q15_t)0x8665, (q15_t)0x27eb, (q15_t)0x8663, (q15_t)0x27e5, (q15_t)0x8661, + (q15_t)0x27df, (q15_t)0x865f, (q15_t)0x27d9, (q15_t)0x865d, (q15_t)0x27d3, (q15_t)0x865b, (q15_t)0x27cd, (q15_t)0x8659, + (q15_t)0x27c7, (q15_t)0x8657, (q15_t)0x27c1, (q15_t)0x8655, (q15_t)0x27bb, (q15_t)0x8653, (q15_t)0x27b5, (q15_t)0x8651, + (q15_t)0x27af, (q15_t)0x864f, (q15_t)0x27a9, (q15_t)0x864d, (q15_t)0x27a3, (q15_t)0x864b, (q15_t)0x279d, (q15_t)0x8649, + (q15_t)0x2797, (q15_t)0x8647, (q15_t)0x2791, (q15_t)0x8645, (q15_t)0x278b, (q15_t)0x8644, (q15_t)0x2785, (q15_t)0x8642, + (q15_t)0x277f, (q15_t)0x8640, (q15_t)0x2779, (q15_t)0x863e, (q15_t)0x2773, (q15_t)0x863c, (q15_t)0x276d, (q15_t)0x863a, + (q15_t)0x2767, (q15_t)0x8638, (q15_t)0x2761, (q15_t)0x8636, (q15_t)0x275b, (q15_t)0x8634, (q15_t)0x2755, (q15_t)0x8632, + (q15_t)0x274f, (q15_t)0x8630, (q15_t)0x2749, (q15_t)0x862e, (q15_t)0x2743, (q15_t)0x862c, (q15_t)0x273d, (q15_t)0x862a, + (q15_t)0x2737, (q15_t)0x8628, (q15_t)0x2731, (q15_t)0x8627, (q15_t)0x272b, (q15_t)0x8625, (q15_t)0x2725, (q15_t)0x8623, + (q15_t)0x271f, (q15_t)0x8621, (q15_t)0x2719, (q15_t)0x861f, (q15_t)0x2713, (q15_t)0x861d, (q15_t)0x270d, (q15_t)0x861b, + (q15_t)0x2707, (q15_t)0x8619, (q15_t)0x2701, (q15_t)0x8617, (q15_t)0x26fb, (q15_t)0x8615, (q15_t)0x26f5, (q15_t)0x8613, + (q15_t)0x26ef, (q15_t)0x8611, (q15_t)0x26e9, (q15_t)0x8610, (q15_t)0x26e4, (q15_t)0x860e, (q15_t)0x26de, (q15_t)0x860c, + (q15_t)0x26d8, (q15_t)0x860a, (q15_t)0x26d2, (q15_t)0x8608, (q15_t)0x26cc, (q15_t)0x8606, (q15_t)0x26c6, (q15_t)0x8604, + (q15_t)0x26c0, (q15_t)0x8602, (q15_t)0x26ba, (q15_t)0x8600, (q15_t)0x26b4, (q15_t)0x85fe, (q15_t)0x26ae, (q15_t)0x85fc, + (q15_t)0x26a8, (q15_t)0x85fb, (q15_t)0x26a2, (q15_t)0x85f9, (q15_t)0x269c, (q15_t)0x85f7, (q15_t)0x2696, (q15_t)0x85f5, + (q15_t)0x2690, (q15_t)0x85f3, (q15_t)0x268a, (q15_t)0x85f1, (q15_t)0x2684, (q15_t)0x85ef, (q15_t)0x267e, (q15_t)0x85ed, + (q15_t)0x2678, (q15_t)0x85eb, (q15_t)0x2672, (q15_t)0x85ea, (q15_t)0x266c, (q15_t)0x85e8, (q15_t)0x2666, (q15_t)0x85e6, + (q15_t)0x2660, (q15_t)0x85e4, (q15_t)0x265a, (q15_t)0x85e2, (q15_t)0x2654, (q15_t)0x85e0, (q15_t)0x264e, (q15_t)0x85de, + (q15_t)0x2648, (q15_t)0x85dc, (q15_t)0x2642, (q15_t)0x85da, (q15_t)0x263c, (q15_t)0x85d9, (q15_t)0x2636, (q15_t)0x85d7, + (q15_t)0x2630, (q15_t)0x85d5, (q15_t)0x262a, (q15_t)0x85d3, (q15_t)0x2624, (q15_t)0x85d1, (q15_t)0x261e, (q15_t)0x85cf, + (q15_t)0x2618, (q15_t)0x85cd, (q15_t)0x2612, (q15_t)0x85cb, (q15_t)0x260c, (q15_t)0x85ca, (q15_t)0x2606, (q15_t)0x85c8, + (q15_t)0x2600, (q15_t)0x85c6, (q15_t)0x25fa, (q15_t)0x85c4, (q15_t)0x25f4, (q15_t)0x85c2, (q15_t)0x25ee, (q15_t)0x85c0, + (q15_t)0x25e8, (q15_t)0x85be, (q15_t)0x25e2, (q15_t)0x85bd, (q15_t)0x25dc, (q15_t)0x85bb, (q15_t)0x25d6, (q15_t)0x85b9, + (q15_t)0x25d0, (q15_t)0x85b7, (q15_t)0x25ca, (q15_t)0x85b5, (q15_t)0x25c4, (q15_t)0x85b3, (q15_t)0x25be, (q15_t)0x85b1, + (q15_t)0x25b8, (q15_t)0x85b0, (q15_t)0x25b2, (q15_t)0x85ae, (q15_t)0x25ac, (q15_t)0x85ac, (q15_t)0x25a6, (q15_t)0x85aa, + (q15_t)0x25a0, (q15_t)0x85a8, (q15_t)0x259a, (q15_t)0x85a6, (q15_t)0x2594, (q15_t)0x85a4, (q15_t)0x258e, (q15_t)0x85a3, + (q15_t)0x2588, (q15_t)0x85a1, (q15_t)0x2582, (q15_t)0x859f, (q15_t)0x257c, (q15_t)0x859d, (q15_t)0x2576, (q15_t)0x859b, + (q15_t)0x2570, (q15_t)0x8599, (q15_t)0x256a, (q15_t)0x8598, (q15_t)0x2564, (q15_t)0x8596, (q15_t)0x255e, (q15_t)0x8594, + (q15_t)0x2558, (q15_t)0x8592, (q15_t)0x2552, (q15_t)0x8590, (q15_t)0x254c, (q15_t)0x858e, (q15_t)0x2546, (q15_t)0x858d, + (q15_t)0x2540, (q15_t)0x858b, (q15_t)0x253a, (q15_t)0x8589, (q15_t)0x2534, (q15_t)0x8587, (q15_t)0x252e, (q15_t)0x8585, + (q15_t)0x2528, (q15_t)0x8583, (q15_t)0x2522, (q15_t)0x8582, (q15_t)0x251c, (q15_t)0x8580, (q15_t)0x2516, (q15_t)0x857e, + (q15_t)0x250f, (q15_t)0x857c, (q15_t)0x2509, (q15_t)0x857a, (q15_t)0x2503, (q15_t)0x8579, (q15_t)0x24fd, (q15_t)0x8577, + (q15_t)0x24f7, (q15_t)0x8575, (q15_t)0x24f1, (q15_t)0x8573, (q15_t)0x24eb, (q15_t)0x8571, (q15_t)0x24e5, (q15_t)0x856f, + (q15_t)0x24df, (q15_t)0x856e, (q15_t)0x24d9, (q15_t)0x856c, (q15_t)0x24d3, (q15_t)0x856a, (q15_t)0x24cd, (q15_t)0x8568, + (q15_t)0x24c7, (q15_t)0x8566, (q15_t)0x24c1, (q15_t)0x8565, (q15_t)0x24bb, (q15_t)0x8563, (q15_t)0x24b5, (q15_t)0x8561, + (q15_t)0x24af, (q15_t)0x855f, (q15_t)0x24a9, (q15_t)0x855d, (q15_t)0x24a3, (q15_t)0x855c, (q15_t)0x249d, (q15_t)0x855a, + (q15_t)0x2497, (q15_t)0x8558, (q15_t)0x2491, (q15_t)0x8556, (q15_t)0x248b, (q15_t)0x8554, (q15_t)0x2485, (q15_t)0x8553, + (q15_t)0x247f, (q15_t)0x8551, (q15_t)0x2479, (q15_t)0x854f, (q15_t)0x2473, (q15_t)0x854d, (q15_t)0x246d, (q15_t)0x854b, + (q15_t)0x2467, (q15_t)0x854a, (q15_t)0x2461, (q15_t)0x8548, (q15_t)0x245b, (q15_t)0x8546, (q15_t)0x2455, (q15_t)0x8544, + (q15_t)0x244f, (q15_t)0x8543, (q15_t)0x2449, (q15_t)0x8541, (q15_t)0x2443, (q15_t)0x853f, (q15_t)0x243d, (q15_t)0x853d, + (q15_t)0x2437, (q15_t)0x853b, (q15_t)0x2431, (q15_t)0x853a, (q15_t)0x242b, (q15_t)0x8538, (q15_t)0x2425, (q15_t)0x8536, + (q15_t)0x241f, (q15_t)0x8534, (q15_t)0x2419, (q15_t)0x8533, (q15_t)0x2413, (q15_t)0x8531, (q15_t)0x240d, (q15_t)0x852f, + (q15_t)0x2407, (q15_t)0x852d, (q15_t)0x2401, (q15_t)0x852b, (q15_t)0x23fa, (q15_t)0x852a, (q15_t)0x23f4, (q15_t)0x8528, + (q15_t)0x23ee, (q15_t)0x8526, (q15_t)0x23e8, (q15_t)0x8524, (q15_t)0x23e2, (q15_t)0x8523, (q15_t)0x23dc, (q15_t)0x8521, + (q15_t)0x23d6, (q15_t)0x851f, (q15_t)0x23d0, (q15_t)0x851d, (q15_t)0x23ca, (q15_t)0x851c, (q15_t)0x23c4, (q15_t)0x851a, + (q15_t)0x23be, (q15_t)0x8518, (q15_t)0x23b8, (q15_t)0x8516, (q15_t)0x23b2, (q15_t)0x8515, (q15_t)0x23ac, (q15_t)0x8513, + (q15_t)0x23a6, (q15_t)0x8511, (q15_t)0x23a0, (q15_t)0x850f, (q15_t)0x239a, (q15_t)0x850e, (q15_t)0x2394, (q15_t)0x850c, + (q15_t)0x238e, (q15_t)0x850a, (q15_t)0x2388, (q15_t)0x8508, (q15_t)0x2382, (q15_t)0x8507, (q15_t)0x237c, (q15_t)0x8505, + (q15_t)0x2376, (q15_t)0x8503, (q15_t)0x2370, (q15_t)0x8501, (q15_t)0x236a, (q15_t)0x8500, (q15_t)0x2364, (q15_t)0x84fe, + (q15_t)0x235e, (q15_t)0x84fc, (q15_t)0x2358, (q15_t)0x84fa, (q15_t)0x2352, (q15_t)0x84f9, (q15_t)0x234b, (q15_t)0x84f7, + (q15_t)0x2345, (q15_t)0x84f5, (q15_t)0x233f, (q15_t)0x84f4, (q15_t)0x2339, (q15_t)0x84f2, (q15_t)0x2333, (q15_t)0x84f0, + (q15_t)0x232d, (q15_t)0x84ee, (q15_t)0x2327, (q15_t)0x84ed, (q15_t)0x2321, (q15_t)0x84eb, (q15_t)0x231b, (q15_t)0x84e9, + (q15_t)0x2315, (q15_t)0x84e7, (q15_t)0x230f, (q15_t)0x84e6, (q15_t)0x2309, (q15_t)0x84e4, (q15_t)0x2303, (q15_t)0x84e2, + (q15_t)0x22fd, (q15_t)0x84e1, (q15_t)0x22f7, (q15_t)0x84df, (q15_t)0x22f1, (q15_t)0x84dd, (q15_t)0x22eb, (q15_t)0x84db, + (q15_t)0x22e5, (q15_t)0x84da, (q15_t)0x22df, (q15_t)0x84d8, (q15_t)0x22d9, (q15_t)0x84d6, (q15_t)0x22d3, (q15_t)0x84d5, + (q15_t)0x22cd, (q15_t)0x84d3, (q15_t)0x22c7, (q15_t)0x84d1, (q15_t)0x22c0, (q15_t)0x84cf, (q15_t)0x22ba, (q15_t)0x84ce, + (q15_t)0x22b4, (q15_t)0x84cc, (q15_t)0x22ae, (q15_t)0x84ca, (q15_t)0x22a8, (q15_t)0x84c9, (q15_t)0x22a2, (q15_t)0x84c7, + (q15_t)0x229c, (q15_t)0x84c5, (q15_t)0x2296, (q15_t)0x84c4, (q15_t)0x2290, (q15_t)0x84c2, (q15_t)0x228a, (q15_t)0x84c0, + (q15_t)0x2284, (q15_t)0x84be, (q15_t)0x227e, (q15_t)0x84bd, (q15_t)0x2278, (q15_t)0x84bb, (q15_t)0x2272, (q15_t)0x84b9, + (q15_t)0x226c, (q15_t)0x84b8, (q15_t)0x2266, (q15_t)0x84b6, (q15_t)0x2260, (q15_t)0x84b4, (q15_t)0x225a, (q15_t)0x84b3, + (q15_t)0x2254, (q15_t)0x84b1, (q15_t)0x224e, (q15_t)0x84af, (q15_t)0x2247, (q15_t)0x84ae, (q15_t)0x2241, (q15_t)0x84ac, + (q15_t)0x223b, (q15_t)0x84aa, (q15_t)0x2235, (q15_t)0x84a9, (q15_t)0x222f, (q15_t)0x84a7, (q15_t)0x2229, (q15_t)0x84a5, + (q15_t)0x2223, (q15_t)0x84a3, (q15_t)0x221d, (q15_t)0x84a2, (q15_t)0x2217, (q15_t)0x84a0, (q15_t)0x2211, (q15_t)0x849e, + (q15_t)0x220b, (q15_t)0x849d, (q15_t)0x2205, (q15_t)0x849b, (q15_t)0x21ff, (q15_t)0x8499, (q15_t)0x21f9, (q15_t)0x8498, + (q15_t)0x21f3, (q15_t)0x8496, (q15_t)0x21ed, (q15_t)0x8494, (q15_t)0x21e7, (q15_t)0x8493, (q15_t)0x21e1, (q15_t)0x8491, + (q15_t)0x21da, (q15_t)0x848f, (q15_t)0x21d4, (q15_t)0x848e, (q15_t)0x21ce, (q15_t)0x848c, (q15_t)0x21c8, (q15_t)0x848a, + (q15_t)0x21c2, (q15_t)0x8489, (q15_t)0x21bc, (q15_t)0x8487, (q15_t)0x21b6, (q15_t)0x8486, (q15_t)0x21b0, (q15_t)0x8484, + (q15_t)0x21aa, (q15_t)0x8482, (q15_t)0x21a4, (q15_t)0x8481, (q15_t)0x219e, (q15_t)0x847f, (q15_t)0x2198, (q15_t)0x847d, + (q15_t)0x2192, (q15_t)0x847c, (q15_t)0x218c, (q15_t)0x847a, (q15_t)0x2186, (q15_t)0x8478, (q15_t)0x2180, (q15_t)0x8477, + (q15_t)0x2179, (q15_t)0x8475, (q15_t)0x2173, (q15_t)0x8473, (q15_t)0x216d, (q15_t)0x8472, (q15_t)0x2167, (q15_t)0x8470, + (q15_t)0x2161, (q15_t)0x846e, (q15_t)0x215b, (q15_t)0x846d, (q15_t)0x2155, (q15_t)0x846b, (q15_t)0x214f, (q15_t)0x846a, + (q15_t)0x2149, (q15_t)0x8468, (q15_t)0x2143, (q15_t)0x8466, (q15_t)0x213d, (q15_t)0x8465, (q15_t)0x2137, (q15_t)0x8463, + (q15_t)0x2131, (q15_t)0x8461, (q15_t)0x212b, (q15_t)0x8460, (q15_t)0x2125, (q15_t)0x845e, (q15_t)0x211e, (q15_t)0x845d, + (q15_t)0x2118, (q15_t)0x845b, (q15_t)0x2112, (q15_t)0x8459, (q15_t)0x210c, (q15_t)0x8458, (q15_t)0x2106, (q15_t)0x8456, + (q15_t)0x2100, (q15_t)0x8454, (q15_t)0x20fa, (q15_t)0x8453, (q15_t)0x20f4, (q15_t)0x8451, (q15_t)0x20ee, (q15_t)0x8450, + (q15_t)0x20e8, (q15_t)0x844e, (q15_t)0x20e2, (q15_t)0x844c, (q15_t)0x20dc, (q15_t)0x844b, (q15_t)0x20d6, (q15_t)0x8449, + (q15_t)0x20d0, (q15_t)0x8447, (q15_t)0x20c9, (q15_t)0x8446, (q15_t)0x20c3, (q15_t)0x8444, (q15_t)0x20bd, (q15_t)0x8443, + (q15_t)0x20b7, (q15_t)0x8441, (q15_t)0x20b1, (q15_t)0x843f, (q15_t)0x20ab, (q15_t)0x843e, (q15_t)0x20a5, (q15_t)0x843c, + (q15_t)0x209f, (q15_t)0x843b, (q15_t)0x2099, (q15_t)0x8439, (q15_t)0x2093, (q15_t)0x8437, (q15_t)0x208d, (q15_t)0x8436, + (q15_t)0x2087, (q15_t)0x8434, (q15_t)0x2081, (q15_t)0x8433, (q15_t)0x207a, (q15_t)0x8431, (q15_t)0x2074, (q15_t)0x842f, + (q15_t)0x206e, (q15_t)0x842e, (q15_t)0x2068, (q15_t)0x842c, (q15_t)0x2062, (q15_t)0x842b, (q15_t)0x205c, (q15_t)0x8429, + (q15_t)0x2056, (q15_t)0x8427, (q15_t)0x2050, (q15_t)0x8426, (q15_t)0x204a, (q15_t)0x8424, (q15_t)0x2044, (q15_t)0x8423, + (q15_t)0x203e, (q15_t)0x8421, (q15_t)0x2038, (q15_t)0x8420, (q15_t)0x2032, (q15_t)0x841e, (q15_t)0x202b, (q15_t)0x841c, + (q15_t)0x2025, (q15_t)0x841b, (q15_t)0x201f, (q15_t)0x8419, (q15_t)0x2019, (q15_t)0x8418, (q15_t)0x2013, (q15_t)0x8416, + (q15_t)0x200d, (q15_t)0x8415, (q15_t)0x2007, (q15_t)0x8413, (q15_t)0x2001, (q15_t)0x8411, (q15_t)0x1ffb, (q15_t)0x8410, + (q15_t)0x1ff5, (q15_t)0x840e, (q15_t)0x1fef, (q15_t)0x840d, (q15_t)0x1fe9, (q15_t)0x840b, (q15_t)0x1fe2, (q15_t)0x840a, + (q15_t)0x1fdc, (q15_t)0x8408, (q15_t)0x1fd6, (q15_t)0x8406, (q15_t)0x1fd0, (q15_t)0x8405, (q15_t)0x1fca, (q15_t)0x8403, + (q15_t)0x1fc4, (q15_t)0x8402, (q15_t)0x1fbe, (q15_t)0x8400, (q15_t)0x1fb8, (q15_t)0x83ff, (q15_t)0x1fb2, (q15_t)0x83fd, + (q15_t)0x1fac, (q15_t)0x83fb, (q15_t)0x1fa6, (q15_t)0x83fa, (q15_t)0x1f9f, (q15_t)0x83f8, (q15_t)0x1f99, (q15_t)0x83f7, + (q15_t)0x1f93, (q15_t)0x83f5, (q15_t)0x1f8d, (q15_t)0x83f4, (q15_t)0x1f87, (q15_t)0x83f2, (q15_t)0x1f81, (q15_t)0x83f1, + (q15_t)0x1f7b, (q15_t)0x83ef, (q15_t)0x1f75, (q15_t)0x83ee, (q15_t)0x1f6f, (q15_t)0x83ec, (q15_t)0x1f69, (q15_t)0x83ea, + (q15_t)0x1f63, (q15_t)0x83e9, (q15_t)0x1f5d, (q15_t)0x83e7, (q15_t)0x1f56, (q15_t)0x83e6, (q15_t)0x1f50, (q15_t)0x83e4, + (q15_t)0x1f4a, (q15_t)0x83e3, (q15_t)0x1f44, (q15_t)0x83e1, (q15_t)0x1f3e, (q15_t)0x83e0, (q15_t)0x1f38, (q15_t)0x83de, + (q15_t)0x1f32, (q15_t)0x83dd, (q15_t)0x1f2c, (q15_t)0x83db, (q15_t)0x1f26, (q15_t)0x83da, (q15_t)0x1f20, (q15_t)0x83d8, + (q15_t)0x1f19, (q15_t)0x83d7, (q15_t)0x1f13, (q15_t)0x83d5, (q15_t)0x1f0d, (q15_t)0x83d3, (q15_t)0x1f07, (q15_t)0x83d2, + (q15_t)0x1f01, (q15_t)0x83d0, (q15_t)0x1efb, (q15_t)0x83cf, (q15_t)0x1ef5, (q15_t)0x83cd, (q15_t)0x1eef, (q15_t)0x83cc, + (q15_t)0x1ee9, (q15_t)0x83ca, (q15_t)0x1ee3, (q15_t)0x83c9, (q15_t)0x1edd, (q15_t)0x83c7, (q15_t)0x1ed6, (q15_t)0x83c6, + (q15_t)0x1ed0, (q15_t)0x83c4, (q15_t)0x1eca, (q15_t)0x83c3, (q15_t)0x1ec4, (q15_t)0x83c1, (q15_t)0x1ebe, (q15_t)0x83c0, + (q15_t)0x1eb8, (q15_t)0x83be, (q15_t)0x1eb2, (q15_t)0x83bd, (q15_t)0x1eac, (q15_t)0x83bb, (q15_t)0x1ea6, (q15_t)0x83ba, + (q15_t)0x1ea0, (q15_t)0x83b8, (q15_t)0x1e99, (q15_t)0x83b7, (q15_t)0x1e93, (q15_t)0x83b5, (q15_t)0x1e8d, (q15_t)0x83b4, + (q15_t)0x1e87, (q15_t)0x83b2, (q15_t)0x1e81, (q15_t)0x83b1, (q15_t)0x1e7b, (q15_t)0x83af, (q15_t)0x1e75, (q15_t)0x83ae, + (q15_t)0x1e6f, (q15_t)0x83ac, (q15_t)0x1e69, (q15_t)0x83ab, (q15_t)0x1e62, (q15_t)0x83a9, (q15_t)0x1e5c, (q15_t)0x83a8, + (q15_t)0x1e56, (q15_t)0x83a6, (q15_t)0x1e50, (q15_t)0x83a5, (q15_t)0x1e4a, (q15_t)0x83a3, (q15_t)0x1e44, (q15_t)0x83a2, + (q15_t)0x1e3e, (q15_t)0x83a0, (q15_t)0x1e38, (q15_t)0x839f, (q15_t)0x1e32, (q15_t)0x839d, (q15_t)0x1e2c, (q15_t)0x839c, + (q15_t)0x1e25, (q15_t)0x839a, (q15_t)0x1e1f, (q15_t)0x8399, (q15_t)0x1e19, (q15_t)0x8397, (q15_t)0x1e13, (q15_t)0x8396, + (q15_t)0x1e0d, (q15_t)0x8394, (q15_t)0x1e07, (q15_t)0x8393, (q15_t)0x1e01, (q15_t)0x8392, (q15_t)0x1dfb, (q15_t)0x8390, + (q15_t)0x1df5, (q15_t)0x838f, (q15_t)0x1dee, (q15_t)0x838d, (q15_t)0x1de8, (q15_t)0x838c, (q15_t)0x1de2, (q15_t)0x838a, + (q15_t)0x1ddc, (q15_t)0x8389, (q15_t)0x1dd6, (q15_t)0x8387, (q15_t)0x1dd0, (q15_t)0x8386, (q15_t)0x1dca, (q15_t)0x8384, + (q15_t)0x1dc4, (q15_t)0x8383, (q15_t)0x1dbe, (q15_t)0x8381, (q15_t)0x1db7, (q15_t)0x8380, (q15_t)0x1db1, (q15_t)0x837e, + (q15_t)0x1dab, (q15_t)0x837d, (q15_t)0x1da5, (q15_t)0x837c, (q15_t)0x1d9f, (q15_t)0x837a, (q15_t)0x1d99, (q15_t)0x8379, + (q15_t)0x1d93, (q15_t)0x8377, (q15_t)0x1d8d, (q15_t)0x8376, (q15_t)0x1d87, (q15_t)0x8374, (q15_t)0x1d80, (q15_t)0x8373, + (q15_t)0x1d7a, (q15_t)0x8371, (q15_t)0x1d74, (q15_t)0x8370, (q15_t)0x1d6e, (q15_t)0x836f, (q15_t)0x1d68, (q15_t)0x836d, + (q15_t)0x1d62, (q15_t)0x836c, (q15_t)0x1d5c, (q15_t)0x836a, (q15_t)0x1d56, (q15_t)0x8369, (q15_t)0x1d50, (q15_t)0x8367, + (q15_t)0x1d49, (q15_t)0x8366, (q15_t)0x1d43, (q15_t)0x8364, (q15_t)0x1d3d, (q15_t)0x8363, (q15_t)0x1d37, (q15_t)0x8362, + (q15_t)0x1d31, (q15_t)0x8360, (q15_t)0x1d2b, (q15_t)0x835f, (q15_t)0x1d25, (q15_t)0x835d, (q15_t)0x1d1f, (q15_t)0x835c, + (q15_t)0x1d18, (q15_t)0x835a, (q15_t)0x1d12, (q15_t)0x8359, (q15_t)0x1d0c, (q15_t)0x8358, (q15_t)0x1d06, (q15_t)0x8356, + (q15_t)0x1d00, (q15_t)0x8355, (q15_t)0x1cfa, (q15_t)0x8353, (q15_t)0x1cf4, (q15_t)0x8352, (q15_t)0x1cee, (q15_t)0x8350, + (q15_t)0x1ce8, (q15_t)0x834f, (q15_t)0x1ce1, (q15_t)0x834e, (q15_t)0x1cdb, (q15_t)0x834c, (q15_t)0x1cd5, (q15_t)0x834b, + (q15_t)0x1ccf, (q15_t)0x8349, (q15_t)0x1cc9, (q15_t)0x8348, (q15_t)0x1cc3, (q15_t)0x8347, (q15_t)0x1cbd, (q15_t)0x8345, + (q15_t)0x1cb7, (q15_t)0x8344, (q15_t)0x1cb0, (q15_t)0x8342, (q15_t)0x1caa, (q15_t)0x8341, (q15_t)0x1ca4, (q15_t)0x833f, + (q15_t)0x1c9e, (q15_t)0x833e, (q15_t)0x1c98, (q15_t)0x833d, (q15_t)0x1c92, (q15_t)0x833b, (q15_t)0x1c8c, (q15_t)0x833a, + (q15_t)0x1c86, (q15_t)0x8338, (q15_t)0x1c7f, (q15_t)0x8337, (q15_t)0x1c79, (q15_t)0x8336, (q15_t)0x1c73, (q15_t)0x8334, + (q15_t)0x1c6d, (q15_t)0x8333, (q15_t)0x1c67, (q15_t)0x8331, (q15_t)0x1c61, (q15_t)0x8330, (q15_t)0x1c5b, (q15_t)0x832f, + (q15_t)0x1c55, (q15_t)0x832d, (q15_t)0x1c4e, (q15_t)0x832c, (q15_t)0x1c48, (q15_t)0x832b, (q15_t)0x1c42, (q15_t)0x8329, + (q15_t)0x1c3c, (q15_t)0x8328, (q15_t)0x1c36, (q15_t)0x8326, (q15_t)0x1c30, (q15_t)0x8325, (q15_t)0x1c2a, (q15_t)0x8324, + (q15_t)0x1c24, (q15_t)0x8322, (q15_t)0x1c1d, (q15_t)0x8321, (q15_t)0x1c17, (q15_t)0x831f, (q15_t)0x1c11, (q15_t)0x831e, + (q15_t)0x1c0b, (q15_t)0x831d, (q15_t)0x1c05, (q15_t)0x831b, (q15_t)0x1bff, (q15_t)0x831a, (q15_t)0x1bf9, (q15_t)0x8319, + (q15_t)0x1bf2, (q15_t)0x8317, (q15_t)0x1bec, (q15_t)0x8316, (q15_t)0x1be6, (q15_t)0x8314, (q15_t)0x1be0, (q15_t)0x8313, + (q15_t)0x1bda, (q15_t)0x8312, (q15_t)0x1bd4, (q15_t)0x8310, (q15_t)0x1bce, (q15_t)0x830f, (q15_t)0x1bc8, (q15_t)0x830e, + (q15_t)0x1bc1, (q15_t)0x830c, (q15_t)0x1bbb, (q15_t)0x830b, (q15_t)0x1bb5, (q15_t)0x830a, (q15_t)0x1baf, (q15_t)0x8308, + (q15_t)0x1ba9, (q15_t)0x8307, (q15_t)0x1ba3, (q15_t)0x8305, (q15_t)0x1b9d, (q15_t)0x8304, (q15_t)0x1b96, (q15_t)0x8303, + (q15_t)0x1b90, (q15_t)0x8301, (q15_t)0x1b8a, (q15_t)0x8300, (q15_t)0x1b84, (q15_t)0x82ff, (q15_t)0x1b7e, (q15_t)0x82fd, + (q15_t)0x1b78, (q15_t)0x82fc, (q15_t)0x1b72, (q15_t)0x82fb, (q15_t)0x1b6c, (q15_t)0x82f9, (q15_t)0x1b65, (q15_t)0x82f8, + (q15_t)0x1b5f, (q15_t)0x82f7, (q15_t)0x1b59, (q15_t)0x82f5, (q15_t)0x1b53, (q15_t)0x82f4, (q15_t)0x1b4d, (q15_t)0x82f3, + (q15_t)0x1b47, (q15_t)0x82f1, (q15_t)0x1b41, (q15_t)0x82f0, (q15_t)0x1b3a, (q15_t)0x82ef, (q15_t)0x1b34, (q15_t)0x82ed, + (q15_t)0x1b2e, (q15_t)0x82ec, (q15_t)0x1b28, (q15_t)0x82eb, (q15_t)0x1b22, (q15_t)0x82e9, (q15_t)0x1b1c, (q15_t)0x82e8, + (q15_t)0x1b16, (q15_t)0x82e7, (q15_t)0x1b0f, (q15_t)0x82e5, (q15_t)0x1b09, (q15_t)0x82e4, (q15_t)0x1b03, (q15_t)0x82e3, + (q15_t)0x1afd, (q15_t)0x82e1, (q15_t)0x1af7, (q15_t)0x82e0, (q15_t)0x1af1, (q15_t)0x82df, (q15_t)0x1aeb, (q15_t)0x82dd, + (q15_t)0x1ae4, (q15_t)0x82dc, (q15_t)0x1ade, (q15_t)0x82db, (q15_t)0x1ad8, (q15_t)0x82d9, (q15_t)0x1ad2, (q15_t)0x82d8, + (q15_t)0x1acc, (q15_t)0x82d7, (q15_t)0x1ac6, (q15_t)0x82d5, (q15_t)0x1ac0, (q15_t)0x82d4, (q15_t)0x1ab9, (q15_t)0x82d3, + (q15_t)0x1ab3, (q15_t)0x82d1, (q15_t)0x1aad, (q15_t)0x82d0, (q15_t)0x1aa7, (q15_t)0x82cf, (q15_t)0x1aa1, (q15_t)0x82ce, + (q15_t)0x1a9b, (q15_t)0x82cc, (q15_t)0x1a95, (q15_t)0x82cb, (q15_t)0x1a8e, (q15_t)0x82ca, (q15_t)0x1a88, (q15_t)0x82c8, + (q15_t)0x1a82, (q15_t)0x82c7, (q15_t)0x1a7c, (q15_t)0x82c6, (q15_t)0x1a76, (q15_t)0x82c4, (q15_t)0x1a70, (q15_t)0x82c3, + (q15_t)0x1a6a, (q15_t)0x82c2, (q15_t)0x1a63, (q15_t)0x82c1, (q15_t)0x1a5d, (q15_t)0x82bf, (q15_t)0x1a57, (q15_t)0x82be, + (q15_t)0x1a51, (q15_t)0x82bd, (q15_t)0x1a4b, (q15_t)0x82bb, (q15_t)0x1a45, (q15_t)0x82ba, (q15_t)0x1a3e, (q15_t)0x82b9, + (q15_t)0x1a38, (q15_t)0x82b7, (q15_t)0x1a32, (q15_t)0x82b6, (q15_t)0x1a2c, (q15_t)0x82b5, (q15_t)0x1a26, (q15_t)0x82b4, + (q15_t)0x1a20, (q15_t)0x82b2, (q15_t)0x1a1a, (q15_t)0x82b1, (q15_t)0x1a13, (q15_t)0x82b0, (q15_t)0x1a0d, (q15_t)0x82ae, + (q15_t)0x1a07, (q15_t)0x82ad, (q15_t)0x1a01, (q15_t)0x82ac, (q15_t)0x19fb, (q15_t)0x82ab, (q15_t)0x19f5, (q15_t)0x82a9, + (q15_t)0x19ef, (q15_t)0x82a8, (q15_t)0x19e8, (q15_t)0x82a7, (q15_t)0x19e2, (q15_t)0x82a6, (q15_t)0x19dc, (q15_t)0x82a4, + (q15_t)0x19d6, (q15_t)0x82a3, (q15_t)0x19d0, (q15_t)0x82a2, (q15_t)0x19ca, (q15_t)0x82a0, (q15_t)0x19c3, (q15_t)0x829f, + (q15_t)0x19bd, (q15_t)0x829e, (q15_t)0x19b7, (q15_t)0x829d, (q15_t)0x19b1, (q15_t)0x829b, (q15_t)0x19ab, (q15_t)0x829a, + (q15_t)0x19a5, (q15_t)0x8299, (q15_t)0x199f, (q15_t)0x8298, (q15_t)0x1998, (q15_t)0x8296, (q15_t)0x1992, (q15_t)0x8295, + (q15_t)0x198c, (q15_t)0x8294, (q15_t)0x1986, (q15_t)0x8293, (q15_t)0x1980, (q15_t)0x8291, (q15_t)0x197a, (q15_t)0x8290, + (q15_t)0x1973, (q15_t)0x828f, (q15_t)0x196d, (q15_t)0x828e, (q15_t)0x1967, (q15_t)0x828c, (q15_t)0x1961, (q15_t)0x828b, + (q15_t)0x195b, (q15_t)0x828a, (q15_t)0x1955, (q15_t)0x8289, (q15_t)0x194e, (q15_t)0x8287, (q15_t)0x1948, (q15_t)0x8286, + (q15_t)0x1942, (q15_t)0x8285, (q15_t)0x193c, (q15_t)0x8284, (q15_t)0x1936, (q15_t)0x8282, (q15_t)0x1930, (q15_t)0x8281, + (q15_t)0x192a, (q15_t)0x8280, (q15_t)0x1923, (q15_t)0x827f, (q15_t)0x191d, (q15_t)0x827e, (q15_t)0x1917, (q15_t)0x827c, + (q15_t)0x1911, (q15_t)0x827b, (q15_t)0x190b, (q15_t)0x827a, (q15_t)0x1905, (q15_t)0x8279, (q15_t)0x18fe, (q15_t)0x8277, + (q15_t)0x18f8, (q15_t)0x8276, (q15_t)0x18f2, (q15_t)0x8275, (q15_t)0x18ec, (q15_t)0x8274, (q15_t)0x18e6, (q15_t)0x8272, + (q15_t)0x18e0, (q15_t)0x8271, (q15_t)0x18d9, (q15_t)0x8270, (q15_t)0x18d3, (q15_t)0x826f, (q15_t)0x18cd, (q15_t)0x826e, + (q15_t)0x18c7, (q15_t)0x826c, (q15_t)0x18c1, (q15_t)0x826b, (q15_t)0x18bb, (q15_t)0x826a, (q15_t)0x18b4, (q15_t)0x8269, + (q15_t)0x18ae, (q15_t)0x8268, (q15_t)0x18a8, (q15_t)0x8266, (q15_t)0x18a2, (q15_t)0x8265, (q15_t)0x189c, (q15_t)0x8264, + (q15_t)0x1896, (q15_t)0x8263, (q15_t)0x188f, (q15_t)0x8261, (q15_t)0x1889, (q15_t)0x8260, (q15_t)0x1883, (q15_t)0x825f, + (q15_t)0x187d, (q15_t)0x825e, (q15_t)0x1877, (q15_t)0x825d, (q15_t)0x1871, (q15_t)0x825b, (q15_t)0x186a, (q15_t)0x825a, + (q15_t)0x1864, (q15_t)0x8259, (q15_t)0x185e, (q15_t)0x8258, (q15_t)0x1858, (q15_t)0x8257, (q15_t)0x1852, (q15_t)0x8255, + (q15_t)0x184c, (q15_t)0x8254, (q15_t)0x1845, (q15_t)0x8253, (q15_t)0x183f, (q15_t)0x8252, (q15_t)0x1839, (q15_t)0x8251, + (q15_t)0x1833, (q15_t)0x8250, (q15_t)0x182d, (q15_t)0x824e, (q15_t)0x1827, (q15_t)0x824d, (q15_t)0x1820, (q15_t)0x824c, + (q15_t)0x181a, (q15_t)0x824b, (q15_t)0x1814, (q15_t)0x824a, (q15_t)0x180e, (q15_t)0x8248, (q15_t)0x1808, (q15_t)0x8247, + (q15_t)0x1802, (q15_t)0x8246, (q15_t)0x17fb, (q15_t)0x8245, (q15_t)0x17f5, (q15_t)0x8244, (q15_t)0x17ef, (q15_t)0x8243, + (q15_t)0x17e9, (q15_t)0x8241, (q15_t)0x17e3, (q15_t)0x8240, (q15_t)0x17dd, (q15_t)0x823f, (q15_t)0x17d6, (q15_t)0x823e, + (q15_t)0x17d0, (q15_t)0x823d, (q15_t)0x17ca, (q15_t)0x823b, (q15_t)0x17c4, (q15_t)0x823a, (q15_t)0x17be, (q15_t)0x8239, + (q15_t)0x17b7, (q15_t)0x8238, (q15_t)0x17b1, (q15_t)0x8237, (q15_t)0x17ab, (q15_t)0x8236, (q15_t)0x17a5, (q15_t)0x8234, + (q15_t)0x179f, (q15_t)0x8233, (q15_t)0x1799, (q15_t)0x8232, (q15_t)0x1792, (q15_t)0x8231, (q15_t)0x178c, (q15_t)0x8230, + (q15_t)0x1786, (q15_t)0x822f, (q15_t)0x1780, (q15_t)0x822e, (q15_t)0x177a, (q15_t)0x822c, (q15_t)0x1774, (q15_t)0x822b, + (q15_t)0x176d, (q15_t)0x822a, (q15_t)0x1767, (q15_t)0x8229, (q15_t)0x1761, (q15_t)0x8228, (q15_t)0x175b, (q15_t)0x8227, + (q15_t)0x1755, (q15_t)0x8226, (q15_t)0x174e, (q15_t)0x8224, (q15_t)0x1748, (q15_t)0x8223, (q15_t)0x1742, (q15_t)0x8222, + (q15_t)0x173c, (q15_t)0x8221, (q15_t)0x1736, (q15_t)0x8220, (q15_t)0x1730, (q15_t)0x821f, (q15_t)0x1729, (q15_t)0x821e, + (q15_t)0x1723, (q15_t)0x821c, (q15_t)0x171d, (q15_t)0x821b, (q15_t)0x1717, (q15_t)0x821a, (q15_t)0x1711, (q15_t)0x8219, + (q15_t)0x170a, (q15_t)0x8218, (q15_t)0x1704, (q15_t)0x8217, (q15_t)0x16fe, (q15_t)0x8216, (q15_t)0x16f8, (q15_t)0x8214, + (q15_t)0x16f2, (q15_t)0x8213, (q15_t)0x16ec, (q15_t)0x8212, (q15_t)0x16e5, (q15_t)0x8211, (q15_t)0x16df, (q15_t)0x8210, + (q15_t)0x16d9, (q15_t)0x820f, (q15_t)0x16d3, (q15_t)0x820e, (q15_t)0x16cd, (q15_t)0x820d, (q15_t)0x16c6, (q15_t)0x820b, + (q15_t)0x16c0, (q15_t)0x820a, (q15_t)0x16ba, (q15_t)0x8209, (q15_t)0x16b4, (q15_t)0x8208, (q15_t)0x16ae, (q15_t)0x8207, + (q15_t)0x16a8, (q15_t)0x8206, (q15_t)0x16a1, (q15_t)0x8205, (q15_t)0x169b, (q15_t)0x8204, (q15_t)0x1695, (q15_t)0x8203, + (q15_t)0x168f, (q15_t)0x8201, (q15_t)0x1689, (q15_t)0x8200, (q15_t)0x1682, (q15_t)0x81ff, (q15_t)0x167c, (q15_t)0x81fe, + (q15_t)0x1676, (q15_t)0x81fd, (q15_t)0x1670, (q15_t)0x81fc, (q15_t)0x166a, (q15_t)0x81fb, (q15_t)0x1664, (q15_t)0x81fa, + (q15_t)0x165d, (q15_t)0x81f9, (q15_t)0x1657, (q15_t)0x81f8, (q15_t)0x1651, (q15_t)0x81f6, (q15_t)0x164b, (q15_t)0x81f5, + (q15_t)0x1645, (q15_t)0x81f4, (q15_t)0x163e, (q15_t)0x81f3, (q15_t)0x1638, (q15_t)0x81f2, (q15_t)0x1632, (q15_t)0x81f1, + (q15_t)0x162c, (q15_t)0x81f0, (q15_t)0x1626, (q15_t)0x81ef, (q15_t)0x161f, (q15_t)0x81ee, (q15_t)0x1619, (q15_t)0x81ed, + (q15_t)0x1613, (q15_t)0x81ec, (q15_t)0x160d, (q15_t)0x81ea, (q15_t)0x1607, (q15_t)0x81e9, (q15_t)0x1601, (q15_t)0x81e8, + (q15_t)0x15fa, (q15_t)0x81e7, (q15_t)0x15f4, (q15_t)0x81e6, (q15_t)0x15ee, (q15_t)0x81e5, (q15_t)0x15e8, (q15_t)0x81e4, + (q15_t)0x15e2, (q15_t)0x81e3, (q15_t)0x15db, (q15_t)0x81e2, (q15_t)0x15d5, (q15_t)0x81e1, (q15_t)0x15cf, (q15_t)0x81e0, + (q15_t)0x15c9, (q15_t)0x81df, (q15_t)0x15c3, (q15_t)0x81de, (q15_t)0x15bc, (q15_t)0x81dc, (q15_t)0x15b6, (q15_t)0x81db, + (q15_t)0x15b0, (q15_t)0x81da, (q15_t)0x15aa, (q15_t)0x81d9, (q15_t)0x15a4, (q15_t)0x81d8, (q15_t)0x159d, (q15_t)0x81d7, + (q15_t)0x1597, (q15_t)0x81d6, (q15_t)0x1591, (q15_t)0x81d5, (q15_t)0x158b, (q15_t)0x81d4, (q15_t)0x1585, (q15_t)0x81d3, + (q15_t)0x157f, (q15_t)0x81d2, (q15_t)0x1578, (q15_t)0x81d1, (q15_t)0x1572, (q15_t)0x81d0, (q15_t)0x156c, (q15_t)0x81cf, + (q15_t)0x1566, (q15_t)0x81ce, (q15_t)0x1560, (q15_t)0x81cd, (q15_t)0x1559, (q15_t)0x81cc, (q15_t)0x1553, (q15_t)0x81cb, + (q15_t)0x154d, (q15_t)0x81c9, (q15_t)0x1547, (q15_t)0x81c8, (q15_t)0x1541, (q15_t)0x81c7, (q15_t)0x153a, (q15_t)0x81c6, + (q15_t)0x1534, (q15_t)0x81c5, (q15_t)0x152e, (q15_t)0x81c4, (q15_t)0x1528, (q15_t)0x81c3, (q15_t)0x1522, (q15_t)0x81c2, + (q15_t)0x151b, (q15_t)0x81c1, (q15_t)0x1515, (q15_t)0x81c0, (q15_t)0x150f, (q15_t)0x81bf, (q15_t)0x1509, (q15_t)0x81be, + (q15_t)0x1503, (q15_t)0x81bd, (q15_t)0x14fc, (q15_t)0x81bc, (q15_t)0x14f6, (q15_t)0x81bb, (q15_t)0x14f0, (q15_t)0x81ba, + (q15_t)0x14ea, (q15_t)0x81b9, (q15_t)0x14e4, (q15_t)0x81b8, (q15_t)0x14dd, (q15_t)0x81b7, (q15_t)0x14d7, (q15_t)0x81b6, + (q15_t)0x14d1, (q15_t)0x81b5, (q15_t)0x14cb, (q15_t)0x81b4, (q15_t)0x14c5, (q15_t)0x81b3, (q15_t)0x14be, (q15_t)0x81b2, + (q15_t)0x14b8, (q15_t)0x81b1, (q15_t)0x14b2, (q15_t)0x81b0, (q15_t)0x14ac, (q15_t)0x81af, (q15_t)0x14a6, (q15_t)0x81ae, + (q15_t)0x149f, (q15_t)0x81ad, (q15_t)0x1499, (q15_t)0x81ac, (q15_t)0x1493, (q15_t)0x81ab, (q15_t)0x148d, (q15_t)0x81aa, + (q15_t)0x1487, (q15_t)0x81a9, (q15_t)0x1480, (q15_t)0x81a8, (q15_t)0x147a, (q15_t)0x81a7, (q15_t)0x1474, (q15_t)0x81a6, + (q15_t)0x146e, (q15_t)0x81a5, (q15_t)0x1468, (q15_t)0x81a4, (q15_t)0x1461, (q15_t)0x81a3, (q15_t)0x145b, (q15_t)0x81a2, + (q15_t)0x1455, (q15_t)0x81a1, (q15_t)0x144f, (q15_t)0x81a0, (q15_t)0x1449, (q15_t)0x819f, (q15_t)0x1442, (q15_t)0x819e, + (q15_t)0x143c, (q15_t)0x819d, (q15_t)0x1436, (q15_t)0x819c, (q15_t)0x1430, (q15_t)0x819b, (q15_t)0x142a, (q15_t)0x819a, + (q15_t)0x1423, (q15_t)0x8199, (q15_t)0x141d, (q15_t)0x8198, (q15_t)0x1417, (q15_t)0x8197, (q15_t)0x1411, (q15_t)0x8196, + (q15_t)0x140b, (q15_t)0x8195, (q15_t)0x1404, (q15_t)0x8194, (q15_t)0x13fe, (q15_t)0x8193, (q15_t)0x13f8, (q15_t)0x8192, + (q15_t)0x13f2, (q15_t)0x8191, (q15_t)0x13eb, (q15_t)0x8190, (q15_t)0x13e5, (q15_t)0x818f, (q15_t)0x13df, (q15_t)0x818e, + (q15_t)0x13d9, (q15_t)0x818d, (q15_t)0x13d3, (q15_t)0x818c, (q15_t)0x13cc, (q15_t)0x818b, (q15_t)0x13c6, (q15_t)0x818a, + (q15_t)0x13c0, (q15_t)0x8189, (q15_t)0x13ba, (q15_t)0x8188, (q15_t)0x13b4, (q15_t)0x8187, (q15_t)0x13ad, (q15_t)0x8186, + (q15_t)0x13a7, (q15_t)0x8185, (q15_t)0x13a1, (q15_t)0x8184, (q15_t)0x139b, (q15_t)0x8183, (q15_t)0x1395, (q15_t)0x8182, + (q15_t)0x138e, (q15_t)0x8181, (q15_t)0x1388, (q15_t)0x8180, (q15_t)0x1382, (q15_t)0x817f, (q15_t)0x137c, (q15_t)0x817e, + (q15_t)0x1376, (q15_t)0x817d, (q15_t)0x136f, (q15_t)0x817c, (q15_t)0x1369, (q15_t)0x817c, (q15_t)0x1363, (q15_t)0x817b, + (q15_t)0x135d, (q15_t)0x817a, (q15_t)0x1356, (q15_t)0x8179, (q15_t)0x1350, (q15_t)0x8178, (q15_t)0x134a, (q15_t)0x8177, + (q15_t)0x1344, (q15_t)0x8176, (q15_t)0x133e, (q15_t)0x8175, (q15_t)0x1337, (q15_t)0x8174, (q15_t)0x1331, (q15_t)0x8173, + (q15_t)0x132b, (q15_t)0x8172, (q15_t)0x1325, (q15_t)0x8171, (q15_t)0x131f, (q15_t)0x8170, (q15_t)0x1318, (q15_t)0x816f, + (q15_t)0x1312, (q15_t)0x816e, (q15_t)0x130c, (q15_t)0x816d, (q15_t)0x1306, (q15_t)0x816c, (q15_t)0x12ff, (q15_t)0x816c, + (q15_t)0x12f9, (q15_t)0x816b, (q15_t)0x12f3, (q15_t)0x816a, (q15_t)0x12ed, (q15_t)0x8169, (q15_t)0x12e7, (q15_t)0x8168, + (q15_t)0x12e0, (q15_t)0x8167, (q15_t)0x12da, (q15_t)0x8166, (q15_t)0x12d4, (q15_t)0x8165, (q15_t)0x12ce, (q15_t)0x8164, + (q15_t)0x12c8, (q15_t)0x8163, (q15_t)0x12c1, (q15_t)0x8162, (q15_t)0x12bb, (q15_t)0x8161, (q15_t)0x12b5, (q15_t)0x8160, + (q15_t)0x12af, (q15_t)0x815f, (q15_t)0x12a8, (q15_t)0x815f, (q15_t)0x12a2, (q15_t)0x815e, (q15_t)0x129c, (q15_t)0x815d, + (q15_t)0x1296, (q15_t)0x815c, (q15_t)0x1290, (q15_t)0x815b, (q15_t)0x1289, (q15_t)0x815a, (q15_t)0x1283, (q15_t)0x8159, + (q15_t)0x127d, (q15_t)0x8158, (q15_t)0x1277, (q15_t)0x8157, (q15_t)0x1271, (q15_t)0x8156, (q15_t)0x126a, (q15_t)0x8155, + (q15_t)0x1264, (q15_t)0x8155, (q15_t)0x125e, (q15_t)0x8154, (q15_t)0x1258, (q15_t)0x8153, (q15_t)0x1251, (q15_t)0x8152, + (q15_t)0x124b, (q15_t)0x8151, (q15_t)0x1245, (q15_t)0x8150, (q15_t)0x123f, (q15_t)0x814f, (q15_t)0x1239, (q15_t)0x814e, + (q15_t)0x1232, (q15_t)0x814d, (q15_t)0x122c, (q15_t)0x814c, (q15_t)0x1226, (q15_t)0x814c, (q15_t)0x1220, (q15_t)0x814b, + (q15_t)0x1219, (q15_t)0x814a, (q15_t)0x1213, (q15_t)0x8149, (q15_t)0x120d, (q15_t)0x8148, (q15_t)0x1207, (q15_t)0x8147, + (q15_t)0x1201, (q15_t)0x8146, (q15_t)0x11fa, (q15_t)0x8145, (q15_t)0x11f4, (q15_t)0x8145, (q15_t)0x11ee, (q15_t)0x8144, + (q15_t)0x11e8, (q15_t)0x8143, (q15_t)0x11e1, (q15_t)0x8142, (q15_t)0x11db, (q15_t)0x8141, (q15_t)0x11d5, (q15_t)0x8140, + (q15_t)0x11cf, (q15_t)0x813f, (q15_t)0x11c9, (q15_t)0x813e, (q15_t)0x11c2, (q15_t)0x813d, (q15_t)0x11bc, (q15_t)0x813d, + (q15_t)0x11b6, (q15_t)0x813c, (q15_t)0x11b0, (q15_t)0x813b, (q15_t)0x11a9, (q15_t)0x813a, (q15_t)0x11a3, (q15_t)0x8139, + (q15_t)0x119d, (q15_t)0x8138, (q15_t)0x1197, (q15_t)0x8137, (q15_t)0x1191, (q15_t)0x8137, (q15_t)0x118a, (q15_t)0x8136, + (q15_t)0x1184, (q15_t)0x8135, (q15_t)0x117e, (q15_t)0x8134, (q15_t)0x1178, (q15_t)0x8133, (q15_t)0x1171, (q15_t)0x8132, + (q15_t)0x116b, (q15_t)0x8131, (q15_t)0x1165, (q15_t)0x8131, (q15_t)0x115f, (q15_t)0x8130, (q15_t)0x1159, (q15_t)0x812f, + (q15_t)0x1152, (q15_t)0x812e, (q15_t)0x114c, (q15_t)0x812d, (q15_t)0x1146, (q15_t)0x812c, (q15_t)0x1140, (q15_t)0x812b, + (q15_t)0x1139, (q15_t)0x812b, (q15_t)0x1133, (q15_t)0x812a, (q15_t)0x112d, (q15_t)0x8129, (q15_t)0x1127, (q15_t)0x8128, + (q15_t)0x1121, (q15_t)0x8127, (q15_t)0x111a, (q15_t)0x8126, (q15_t)0x1114, (q15_t)0x8126, (q15_t)0x110e, (q15_t)0x8125, + (q15_t)0x1108, (q15_t)0x8124, (q15_t)0x1101, (q15_t)0x8123, (q15_t)0x10fb, (q15_t)0x8122, (q15_t)0x10f5, (q15_t)0x8121, + (q15_t)0x10ef, (q15_t)0x8121, (q15_t)0x10e8, (q15_t)0x8120, (q15_t)0x10e2, (q15_t)0x811f, (q15_t)0x10dc, (q15_t)0x811e, + (q15_t)0x10d6, (q15_t)0x811d, (q15_t)0x10d0, (q15_t)0x811c, (q15_t)0x10c9, (q15_t)0x811c, (q15_t)0x10c3, (q15_t)0x811b, + (q15_t)0x10bd, (q15_t)0x811a, (q15_t)0x10b7, (q15_t)0x8119, (q15_t)0x10b0, (q15_t)0x8118, (q15_t)0x10aa, (q15_t)0x8117, + (q15_t)0x10a4, (q15_t)0x8117, (q15_t)0x109e, (q15_t)0x8116, (q15_t)0x1098, (q15_t)0x8115, (q15_t)0x1091, (q15_t)0x8114, + (q15_t)0x108b, (q15_t)0x8113, (q15_t)0x1085, (q15_t)0x8113, (q15_t)0x107f, (q15_t)0x8112, (q15_t)0x1078, (q15_t)0x8111, + (q15_t)0x1072, (q15_t)0x8110, (q15_t)0x106c, (q15_t)0x810f, (q15_t)0x1066, (q15_t)0x810f, (q15_t)0x105f, (q15_t)0x810e, + (q15_t)0x1059, (q15_t)0x810d, (q15_t)0x1053, (q15_t)0x810c, (q15_t)0x104d, (q15_t)0x810b, (q15_t)0x1047, (q15_t)0x810b, + (q15_t)0x1040, (q15_t)0x810a, (q15_t)0x103a, (q15_t)0x8109, (q15_t)0x1034, (q15_t)0x8108, (q15_t)0x102e, (q15_t)0x8107, + (q15_t)0x1027, (q15_t)0x8107, (q15_t)0x1021, (q15_t)0x8106, (q15_t)0x101b, (q15_t)0x8105, (q15_t)0x1015, (q15_t)0x8104, + (q15_t)0x100e, (q15_t)0x8103, (q15_t)0x1008, (q15_t)0x8103, (q15_t)0x1002, (q15_t)0x8102, (q15_t)0xffc, (q15_t)0x8101, + (q15_t)0xff5, (q15_t)0x8100, (q15_t)0xfef, (q15_t)0x80ff, (q15_t)0xfe9, (q15_t)0x80ff, (q15_t)0xfe3, (q15_t)0x80fe, + (q15_t)0xfdd, (q15_t)0x80fd, (q15_t)0xfd6, (q15_t)0x80fc, (q15_t)0xfd0, (q15_t)0x80fc, (q15_t)0xfca, (q15_t)0x80fb, + (q15_t)0xfc4, (q15_t)0x80fa, (q15_t)0xfbd, (q15_t)0x80f9, (q15_t)0xfb7, (q15_t)0x80f8, (q15_t)0xfb1, (q15_t)0x80f8, + (q15_t)0xfab, (q15_t)0x80f7, (q15_t)0xfa4, (q15_t)0x80f6, (q15_t)0xf9e, (q15_t)0x80f5, (q15_t)0xf98, (q15_t)0x80f5, + (q15_t)0xf92, (q15_t)0x80f4, (q15_t)0xf8b, (q15_t)0x80f3, (q15_t)0xf85, (q15_t)0x80f2, (q15_t)0xf7f, (q15_t)0x80f2, + (q15_t)0xf79, (q15_t)0x80f1, (q15_t)0xf73, (q15_t)0x80f0, (q15_t)0xf6c, (q15_t)0x80ef, (q15_t)0xf66, (q15_t)0x80ef, + (q15_t)0xf60, (q15_t)0x80ee, (q15_t)0xf5a, (q15_t)0x80ed, (q15_t)0xf53, (q15_t)0x80ec, (q15_t)0xf4d, (q15_t)0x80ec, + (q15_t)0xf47, (q15_t)0x80eb, (q15_t)0xf41, (q15_t)0x80ea, (q15_t)0xf3a, (q15_t)0x80e9, (q15_t)0xf34, (q15_t)0x80e9, + (q15_t)0xf2e, (q15_t)0x80e8, (q15_t)0xf28, (q15_t)0x80e7, (q15_t)0xf21, (q15_t)0x80e6, (q15_t)0xf1b, (q15_t)0x80e6, + (q15_t)0xf15, (q15_t)0x80e5, (q15_t)0xf0f, (q15_t)0x80e4, (q15_t)0xf08, (q15_t)0x80e3, (q15_t)0xf02, (q15_t)0x80e3, + (q15_t)0xefc, (q15_t)0x80e2, (q15_t)0xef6, (q15_t)0x80e1, (q15_t)0xef0, (q15_t)0x80e0, (q15_t)0xee9, (q15_t)0x80e0, + (q15_t)0xee3, (q15_t)0x80df, (q15_t)0xedd, (q15_t)0x80de, (q15_t)0xed7, (q15_t)0x80dd, (q15_t)0xed0, (q15_t)0x80dd, + (q15_t)0xeca, (q15_t)0x80dc, (q15_t)0xec4, (q15_t)0x80db, (q15_t)0xebe, (q15_t)0x80db, (q15_t)0xeb7, (q15_t)0x80da, + (q15_t)0xeb1, (q15_t)0x80d9, (q15_t)0xeab, (q15_t)0x80d8, (q15_t)0xea5, (q15_t)0x80d8, (q15_t)0xe9e, (q15_t)0x80d7, + (q15_t)0xe98, (q15_t)0x80d6, (q15_t)0xe92, (q15_t)0x80d6, (q15_t)0xe8c, (q15_t)0x80d5, (q15_t)0xe85, (q15_t)0x80d4, + (q15_t)0xe7f, (q15_t)0x80d3, (q15_t)0xe79, (q15_t)0x80d3, (q15_t)0xe73, (q15_t)0x80d2, (q15_t)0xe6c, (q15_t)0x80d1, + (q15_t)0xe66, (q15_t)0x80d1, (q15_t)0xe60, (q15_t)0x80d0, (q15_t)0xe5a, (q15_t)0x80cf, (q15_t)0xe53, (q15_t)0x80ce, + (q15_t)0xe4d, (q15_t)0x80ce, (q15_t)0xe47, (q15_t)0x80cd, (q15_t)0xe41, (q15_t)0x80cc, (q15_t)0xe3a, (q15_t)0x80cc, + (q15_t)0xe34, (q15_t)0x80cb, (q15_t)0xe2e, (q15_t)0x80ca, (q15_t)0xe28, (q15_t)0x80ca, (q15_t)0xe22, (q15_t)0x80c9, + (q15_t)0xe1b, (q15_t)0x80c8, (q15_t)0xe15, (q15_t)0x80c7, (q15_t)0xe0f, (q15_t)0x80c7, (q15_t)0xe09, (q15_t)0x80c6, + (q15_t)0xe02, (q15_t)0x80c5, (q15_t)0xdfc, (q15_t)0x80c5, (q15_t)0xdf6, (q15_t)0x80c4, (q15_t)0xdf0, (q15_t)0x80c3, + (q15_t)0xde9, (q15_t)0x80c3, (q15_t)0xde3, (q15_t)0x80c2, (q15_t)0xddd, (q15_t)0x80c1, (q15_t)0xdd7, (q15_t)0x80c1, + (q15_t)0xdd0, (q15_t)0x80c0, (q15_t)0xdca, (q15_t)0x80bf, (q15_t)0xdc4, (q15_t)0x80bf, (q15_t)0xdbe, (q15_t)0x80be, + (q15_t)0xdb7, (q15_t)0x80bd, (q15_t)0xdb1, (q15_t)0x80bd, (q15_t)0xdab, (q15_t)0x80bc, (q15_t)0xda5, (q15_t)0x80bb, + (q15_t)0xd9e, (q15_t)0x80bb, (q15_t)0xd98, (q15_t)0x80ba, (q15_t)0xd92, (q15_t)0x80b9, (q15_t)0xd8c, (q15_t)0x80b9, + (q15_t)0xd85, (q15_t)0x80b8, (q15_t)0xd7f, (q15_t)0x80b7, (q15_t)0xd79, (q15_t)0x80b7, (q15_t)0xd73, (q15_t)0x80b6, + (q15_t)0xd6c, (q15_t)0x80b5, (q15_t)0xd66, (q15_t)0x80b5, (q15_t)0xd60, (q15_t)0x80b4, (q15_t)0xd5a, (q15_t)0x80b3, + (q15_t)0xd53, (q15_t)0x80b3, (q15_t)0xd4d, (q15_t)0x80b2, (q15_t)0xd47, (q15_t)0x80b1, (q15_t)0xd41, (q15_t)0x80b1, + (q15_t)0xd3a, (q15_t)0x80b0, (q15_t)0xd34, (q15_t)0x80af, (q15_t)0xd2e, (q15_t)0x80af, (q15_t)0xd28, (q15_t)0x80ae, + (q15_t)0xd21, (q15_t)0x80ad, (q15_t)0xd1b, (q15_t)0x80ad, (q15_t)0xd15, (q15_t)0x80ac, (q15_t)0xd0f, (q15_t)0x80ab, + (q15_t)0xd08, (q15_t)0x80ab, (q15_t)0xd02, (q15_t)0x80aa, (q15_t)0xcfc, (q15_t)0x80aa, (q15_t)0xcf6, (q15_t)0x80a9, + (q15_t)0xcef, (q15_t)0x80a8, (q15_t)0xce9, (q15_t)0x80a8, (q15_t)0xce3, (q15_t)0x80a7, (q15_t)0xcdd, (q15_t)0x80a6, + (q15_t)0xcd6, (q15_t)0x80a6, (q15_t)0xcd0, (q15_t)0x80a5, (q15_t)0xcca, (q15_t)0x80a5, (q15_t)0xcc4, (q15_t)0x80a4, + (q15_t)0xcbd, (q15_t)0x80a3, (q15_t)0xcb7, (q15_t)0x80a3, (q15_t)0xcb1, (q15_t)0x80a2, (q15_t)0xcab, (q15_t)0x80a1, + (q15_t)0xca4, (q15_t)0x80a1, (q15_t)0xc9e, (q15_t)0x80a0, (q15_t)0xc98, (q15_t)0x80a0, (q15_t)0xc92, (q15_t)0x809f, + (q15_t)0xc8b, (q15_t)0x809e, (q15_t)0xc85, (q15_t)0x809e, (q15_t)0xc7f, (q15_t)0x809d, (q15_t)0xc79, (q15_t)0x809c, + (q15_t)0xc72, (q15_t)0x809c, (q15_t)0xc6c, (q15_t)0x809b, (q15_t)0xc66, (q15_t)0x809b, (q15_t)0xc60, (q15_t)0x809a, + (q15_t)0xc59, (q15_t)0x8099, (q15_t)0xc53, (q15_t)0x8099, (q15_t)0xc4d, (q15_t)0x8098, (q15_t)0xc47, (q15_t)0x8098, + (q15_t)0xc40, (q15_t)0x8097, (q15_t)0xc3a, (q15_t)0x8096, (q15_t)0xc34, (q15_t)0x8096, (q15_t)0xc2e, (q15_t)0x8095, + (q15_t)0xc27, (q15_t)0x8095, (q15_t)0xc21, (q15_t)0x8094, (q15_t)0xc1b, (q15_t)0x8093, (q15_t)0xc14, (q15_t)0x8093, + (q15_t)0xc0e, (q15_t)0x8092, (q15_t)0xc08, (q15_t)0x8092, (q15_t)0xc02, (q15_t)0x8091, (q15_t)0xbfb, (q15_t)0x8090, + (q15_t)0xbf5, (q15_t)0x8090, (q15_t)0xbef, (q15_t)0x808f, (q15_t)0xbe9, (q15_t)0x808f, (q15_t)0xbe2, (q15_t)0x808e, + (q15_t)0xbdc, (q15_t)0x808e, (q15_t)0xbd6, (q15_t)0x808d, (q15_t)0xbd0, (q15_t)0x808c, (q15_t)0xbc9, (q15_t)0x808c, + (q15_t)0xbc3, (q15_t)0x808b, (q15_t)0xbbd, (q15_t)0x808b, (q15_t)0xbb7, (q15_t)0x808a, (q15_t)0xbb0, (q15_t)0x8089, + (q15_t)0xbaa, (q15_t)0x8089, (q15_t)0xba4, (q15_t)0x8088, (q15_t)0xb9e, (q15_t)0x8088, (q15_t)0xb97, (q15_t)0x8087, + (q15_t)0xb91, (q15_t)0x8087, (q15_t)0xb8b, (q15_t)0x8086, (q15_t)0xb85, (q15_t)0x8085, (q15_t)0xb7e, (q15_t)0x8085, + (q15_t)0xb78, (q15_t)0x8084, (q15_t)0xb72, (q15_t)0x8084, (q15_t)0xb6c, (q15_t)0x8083, (q15_t)0xb65, (q15_t)0x8083, + (q15_t)0xb5f, (q15_t)0x8082, (q15_t)0xb59, (q15_t)0x8082, (q15_t)0xb53, (q15_t)0x8081, (q15_t)0xb4c, (q15_t)0x8080, + (q15_t)0xb46, (q15_t)0x8080, (q15_t)0xb40, (q15_t)0x807f, (q15_t)0xb3a, (q15_t)0x807f, (q15_t)0xb33, (q15_t)0x807e, + (q15_t)0xb2d, (q15_t)0x807e, (q15_t)0xb27, (q15_t)0x807d, (q15_t)0xb20, (q15_t)0x807d, (q15_t)0xb1a, (q15_t)0x807c, + (q15_t)0xb14, (q15_t)0x807b, (q15_t)0xb0e, (q15_t)0x807b, (q15_t)0xb07, (q15_t)0x807a, (q15_t)0xb01, (q15_t)0x807a, + (q15_t)0xafb, (q15_t)0x8079, (q15_t)0xaf5, (q15_t)0x8079, (q15_t)0xaee, (q15_t)0x8078, (q15_t)0xae8, (q15_t)0x8078, + (q15_t)0xae2, (q15_t)0x8077, (q15_t)0xadc, (q15_t)0x8077, (q15_t)0xad5, (q15_t)0x8076, (q15_t)0xacf, (q15_t)0x8076, + (q15_t)0xac9, (q15_t)0x8075, (q15_t)0xac3, (q15_t)0x8075, (q15_t)0xabc, (q15_t)0x8074, (q15_t)0xab6, (q15_t)0x8073, + (q15_t)0xab0, (q15_t)0x8073, (q15_t)0xaaa, (q15_t)0x8072, (q15_t)0xaa3, (q15_t)0x8072, (q15_t)0xa9d, (q15_t)0x8071, + (q15_t)0xa97, (q15_t)0x8071, (q15_t)0xa90, (q15_t)0x8070, (q15_t)0xa8a, (q15_t)0x8070, (q15_t)0xa84, (q15_t)0x806f, + (q15_t)0xa7e, (q15_t)0x806f, (q15_t)0xa77, (q15_t)0x806e, (q15_t)0xa71, (q15_t)0x806e, (q15_t)0xa6b, (q15_t)0x806d, + (q15_t)0xa65, (q15_t)0x806d, (q15_t)0xa5e, (q15_t)0x806c, (q15_t)0xa58, (q15_t)0x806c, (q15_t)0xa52, (q15_t)0x806b, + (q15_t)0xa4c, (q15_t)0x806b, (q15_t)0xa45, (q15_t)0x806a, (q15_t)0xa3f, (q15_t)0x806a, (q15_t)0xa39, (q15_t)0x8069, + (q15_t)0xa33, (q15_t)0x8069, (q15_t)0xa2c, (q15_t)0x8068, (q15_t)0xa26, (q15_t)0x8068, (q15_t)0xa20, (q15_t)0x8067, + (q15_t)0xa19, (q15_t)0x8067, (q15_t)0xa13, (q15_t)0x8066, (q15_t)0xa0d, (q15_t)0x8066, (q15_t)0xa07, (q15_t)0x8065, + (q15_t)0xa00, (q15_t)0x8065, (q15_t)0x9fa, (q15_t)0x8064, (q15_t)0x9f4, (q15_t)0x8064, (q15_t)0x9ee, (q15_t)0x8063, + (q15_t)0x9e7, (q15_t)0x8063, (q15_t)0x9e1, (q15_t)0x8062, (q15_t)0x9db, (q15_t)0x8062, (q15_t)0x9d5, (q15_t)0x8061, + (q15_t)0x9ce, (q15_t)0x8061, (q15_t)0x9c8, (q15_t)0x8060, (q15_t)0x9c2, (q15_t)0x8060, (q15_t)0x9bc, (q15_t)0x805f, + (q15_t)0x9b5, (q15_t)0x805f, (q15_t)0x9af, (q15_t)0x805e, (q15_t)0x9a9, (q15_t)0x805e, (q15_t)0x9a2, (q15_t)0x805d, + (q15_t)0x99c, (q15_t)0x805d, (q15_t)0x996, (q15_t)0x805d, (q15_t)0x990, (q15_t)0x805c, (q15_t)0x989, (q15_t)0x805c, + (q15_t)0x983, (q15_t)0x805b, (q15_t)0x97d, (q15_t)0x805b, (q15_t)0x977, (q15_t)0x805a, (q15_t)0x970, (q15_t)0x805a, + (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x964, (q15_t)0x8059, (q15_t)0x95e, (q15_t)0x8058, (q15_t)0x957, (q15_t)0x8058, + (q15_t)0x951, (q15_t)0x8057, (q15_t)0x94b, (q15_t)0x8057, (q15_t)0x944, (q15_t)0x8057, (q15_t)0x93e, (q15_t)0x8056, + (q15_t)0x938, (q15_t)0x8056, (q15_t)0x932, (q15_t)0x8055, (q15_t)0x92b, (q15_t)0x8055, (q15_t)0x925, (q15_t)0x8054, + (q15_t)0x91f, (q15_t)0x8054, (q15_t)0x919, (q15_t)0x8053, (q15_t)0x912, (q15_t)0x8053, (q15_t)0x90c, (q15_t)0x8052, + (q15_t)0x906, (q15_t)0x8052, (q15_t)0x900, (q15_t)0x8052, (q15_t)0x8f9, (q15_t)0x8051, (q15_t)0x8f3, (q15_t)0x8051, + (q15_t)0x8ed, (q15_t)0x8050, (q15_t)0x8e6, (q15_t)0x8050, (q15_t)0x8e0, (q15_t)0x804f, (q15_t)0x8da, (q15_t)0x804f, + (q15_t)0x8d4, (q15_t)0x804f, (q15_t)0x8cd, (q15_t)0x804e, (q15_t)0x8c7, (q15_t)0x804e, (q15_t)0x8c1, (q15_t)0x804d, + (q15_t)0x8bb, (q15_t)0x804d, (q15_t)0x8b4, (q15_t)0x804c, (q15_t)0x8ae, (q15_t)0x804c, (q15_t)0x8a8, (q15_t)0x804c, + (q15_t)0x8a2, (q15_t)0x804b, (q15_t)0x89b, (q15_t)0x804b, (q15_t)0x895, (q15_t)0x804a, (q15_t)0x88f, (q15_t)0x804a, + (q15_t)0x888, (q15_t)0x8049, (q15_t)0x882, (q15_t)0x8049, (q15_t)0x87c, (q15_t)0x8049, (q15_t)0x876, (q15_t)0x8048, + (q15_t)0x86f, (q15_t)0x8048, (q15_t)0x869, (q15_t)0x8047, (q15_t)0x863, (q15_t)0x8047, (q15_t)0x85d, (q15_t)0x8047, + (q15_t)0x856, (q15_t)0x8046, (q15_t)0x850, (q15_t)0x8046, (q15_t)0x84a, (q15_t)0x8045, (q15_t)0x843, (q15_t)0x8045, + (q15_t)0x83d, (q15_t)0x8044, (q15_t)0x837, (q15_t)0x8044, (q15_t)0x831, (q15_t)0x8044, (q15_t)0x82a, (q15_t)0x8043, + (q15_t)0x824, (q15_t)0x8043, (q15_t)0x81e, (q15_t)0x8042, (q15_t)0x818, (q15_t)0x8042, (q15_t)0x811, (q15_t)0x8042, + (q15_t)0x80b, (q15_t)0x8041, (q15_t)0x805, (q15_t)0x8041, (q15_t)0x7fe, (q15_t)0x8040, (q15_t)0x7f8, (q15_t)0x8040, + (q15_t)0x7f2, (q15_t)0x8040, (q15_t)0x7ec, (q15_t)0x803f, (q15_t)0x7e5, (q15_t)0x803f, (q15_t)0x7df, (q15_t)0x803f, + (q15_t)0x7d9, (q15_t)0x803e, (q15_t)0x7d3, (q15_t)0x803e, (q15_t)0x7cc, (q15_t)0x803d, (q15_t)0x7c6, (q15_t)0x803d, + (q15_t)0x7c0, (q15_t)0x803d, (q15_t)0x7ba, (q15_t)0x803c, (q15_t)0x7b3, (q15_t)0x803c, (q15_t)0x7ad, (q15_t)0x803b, + (q15_t)0x7a7, (q15_t)0x803b, (q15_t)0x7a0, (q15_t)0x803b, (q15_t)0x79a, (q15_t)0x803a, (q15_t)0x794, (q15_t)0x803a, + (q15_t)0x78e, (q15_t)0x803a, (q15_t)0x787, (q15_t)0x8039, (q15_t)0x781, (q15_t)0x8039, (q15_t)0x77b, (q15_t)0x8039, + (q15_t)0x775, (q15_t)0x8038, (q15_t)0x76e, (q15_t)0x8038, (q15_t)0x768, (q15_t)0x8037, (q15_t)0x762, (q15_t)0x8037, + (q15_t)0x75b, (q15_t)0x8037, (q15_t)0x755, (q15_t)0x8036, (q15_t)0x74f, (q15_t)0x8036, (q15_t)0x749, (q15_t)0x8036, + (q15_t)0x742, (q15_t)0x8035, (q15_t)0x73c, (q15_t)0x8035, (q15_t)0x736, (q15_t)0x8035, (q15_t)0x730, (q15_t)0x8034, + (q15_t)0x729, (q15_t)0x8034, (q15_t)0x723, (q15_t)0x8033, (q15_t)0x71d, (q15_t)0x8033, (q15_t)0x716, (q15_t)0x8033, + (q15_t)0x710, (q15_t)0x8032, (q15_t)0x70a, (q15_t)0x8032, (q15_t)0x704, (q15_t)0x8032, (q15_t)0x6fd, (q15_t)0x8031, + (q15_t)0x6f7, (q15_t)0x8031, (q15_t)0x6f1, (q15_t)0x8031, (q15_t)0x6ea, (q15_t)0x8030, (q15_t)0x6e4, (q15_t)0x8030, + (q15_t)0x6de, (q15_t)0x8030, (q15_t)0x6d8, (q15_t)0x802f, (q15_t)0x6d1, (q15_t)0x802f, (q15_t)0x6cb, (q15_t)0x802f, + (q15_t)0x6c5, (q15_t)0x802e, (q15_t)0x6bf, (q15_t)0x802e, (q15_t)0x6b8, (q15_t)0x802e, (q15_t)0x6b2, (q15_t)0x802d, + (q15_t)0x6ac, (q15_t)0x802d, (q15_t)0x6a5, (q15_t)0x802d, (q15_t)0x69f, (q15_t)0x802c, (q15_t)0x699, (q15_t)0x802c, + (q15_t)0x693, (q15_t)0x802c, (q15_t)0x68c, (q15_t)0x802b, (q15_t)0x686, (q15_t)0x802b, (q15_t)0x680, (q15_t)0x802b, + (q15_t)0x67a, (q15_t)0x802a, (q15_t)0x673, (q15_t)0x802a, (q15_t)0x66d, (q15_t)0x802a, (q15_t)0x667, (q15_t)0x802a, + (q15_t)0x660, (q15_t)0x8029, (q15_t)0x65a, (q15_t)0x8029, (q15_t)0x654, (q15_t)0x8029, (q15_t)0x64e, (q15_t)0x8028, + (q15_t)0x647, (q15_t)0x8028, (q15_t)0x641, (q15_t)0x8028, (q15_t)0x63b, (q15_t)0x8027, (q15_t)0x635, (q15_t)0x8027, + (q15_t)0x62e, (q15_t)0x8027, (q15_t)0x628, (q15_t)0x8026, (q15_t)0x622, (q15_t)0x8026, (q15_t)0x61b, (q15_t)0x8026, + (q15_t)0x615, (q15_t)0x8026, (q15_t)0x60f, (q15_t)0x8025, (q15_t)0x609, (q15_t)0x8025, (q15_t)0x602, (q15_t)0x8025, + (q15_t)0x5fc, (q15_t)0x8024, (q15_t)0x5f6, (q15_t)0x8024, (q15_t)0x5ef, (q15_t)0x8024, (q15_t)0x5e9, (q15_t)0x8023, + (q15_t)0x5e3, (q15_t)0x8023, (q15_t)0x5dd, (q15_t)0x8023, (q15_t)0x5d6, (q15_t)0x8023, (q15_t)0x5d0, (q15_t)0x8022, + (q15_t)0x5ca, (q15_t)0x8022, (q15_t)0x5c4, (q15_t)0x8022, (q15_t)0x5bd, (q15_t)0x8021, (q15_t)0x5b7, (q15_t)0x8021, + (q15_t)0x5b1, (q15_t)0x8021, (q15_t)0x5aa, (q15_t)0x8021, (q15_t)0x5a4, (q15_t)0x8020, (q15_t)0x59e, (q15_t)0x8020, + (q15_t)0x598, (q15_t)0x8020, (q15_t)0x591, (q15_t)0x8020, (q15_t)0x58b, (q15_t)0x801f, (q15_t)0x585, (q15_t)0x801f, + (q15_t)0x57f, (q15_t)0x801f, (q15_t)0x578, (q15_t)0x801e, (q15_t)0x572, (q15_t)0x801e, (q15_t)0x56c, (q15_t)0x801e, + (q15_t)0x565, (q15_t)0x801e, (q15_t)0x55f, (q15_t)0x801d, (q15_t)0x559, (q15_t)0x801d, (q15_t)0x553, (q15_t)0x801d, + (q15_t)0x54c, (q15_t)0x801d, (q15_t)0x546, (q15_t)0x801c, (q15_t)0x540, (q15_t)0x801c, (q15_t)0x539, (q15_t)0x801c, + (q15_t)0x533, (q15_t)0x801c, (q15_t)0x52d, (q15_t)0x801b, (q15_t)0x527, (q15_t)0x801b, (q15_t)0x520, (q15_t)0x801b, + (q15_t)0x51a, (q15_t)0x801b, (q15_t)0x514, (q15_t)0x801a, (q15_t)0x50d, (q15_t)0x801a, (q15_t)0x507, (q15_t)0x801a, + (q15_t)0x501, (q15_t)0x801a, (q15_t)0x4fb, (q15_t)0x8019, (q15_t)0x4f4, (q15_t)0x8019, (q15_t)0x4ee, (q15_t)0x8019, + (q15_t)0x4e8, (q15_t)0x8019, (q15_t)0x4e2, (q15_t)0x8018, (q15_t)0x4db, (q15_t)0x8018, (q15_t)0x4d5, (q15_t)0x8018, + (q15_t)0x4cf, (q15_t)0x8018, (q15_t)0x4c8, (q15_t)0x8017, (q15_t)0x4c2, (q15_t)0x8017, (q15_t)0x4bc, (q15_t)0x8017, + (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x4af, (q15_t)0x8016, (q15_t)0x4a9, (q15_t)0x8016, (q15_t)0x4a3, (q15_t)0x8016, + (q15_t)0x49c, (q15_t)0x8016, (q15_t)0x496, (q15_t)0x8016, (q15_t)0x490, (q15_t)0x8015, (q15_t)0x48a, (q15_t)0x8015, + (q15_t)0x483, (q15_t)0x8015, (q15_t)0x47d, (q15_t)0x8015, (q15_t)0x477, (q15_t)0x8014, (q15_t)0x471, (q15_t)0x8014, + (q15_t)0x46a, (q15_t)0x8014, (q15_t)0x464, (q15_t)0x8014, (q15_t)0x45e, (q15_t)0x8014, (q15_t)0x457, (q15_t)0x8013, + (q15_t)0x451, (q15_t)0x8013, (q15_t)0x44b, (q15_t)0x8013, (q15_t)0x445, (q15_t)0x8013, (q15_t)0x43e, (q15_t)0x8013, + (q15_t)0x438, (q15_t)0x8012, (q15_t)0x432, (q15_t)0x8012, (q15_t)0x42b, (q15_t)0x8012, (q15_t)0x425, (q15_t)0x8012, + (q15_t)0x41f, (q15_t)0x8012, (q15_t)0x419, (q15_t)0x8011, (q15_t)0x412, (q15_t)0x8011, (q15_t)0x40c, (q15_t)0x8011, + (q15_t)0x406, (q15_t)0x8011, (q15_t)0x3ff, (q15_t)0x8011, (q15_t)0x3f9, (q15_t)0x8010, (q15_t)0x3f3, (q15_t)0x8010, + (q15_t)0x3ed, (q15_t)0x8010, (q15_t)0x3e6, (q15_t)0x8010, (q15_t)0x3e0, (q15_t)0x8010, (q15_t)0x3da, (q15_t)0x800f, + (q15_t)0x3d4, (q15_t)0x800f, (q15_t)0x3cd, (q15_t)0x800f, (q15_t)0x3c7, (q15_t)0x800f, (q15_t)0x3c1, (q15_t)0x800f, + (q15_t)0x3ba, (q15_t)0x800e, (q15_t)0x3b4, (q15_t)0x800e, (q15_t)0x3ae, (q15_t)0x800e, (q15_t)0x3a8, (q15_t)0x800e, + (q15_t)0x3a1, (q15_t)0x800e, (q15_t)0x39b, (q15_t)0x800e, (q15_t)0x395, (q15_t)0x800d, (q15_t)0x38e, (q15_t)0x800d, + (q15_t)0x388, (q15_t)0x800d, (q15_t)0x382, (q15_t)0x800d, (q15_t)0x37c, (q15_t)0x800d, (q15_t)0x375, (q15_t)0x800c, + (q15_t)0x36f, (q15_t)0x800c, (q15_t)0x369, (q15_t)0x800c, (q15_t)0x362, (q15_t)0x800c, (q15_t)0x35c, (q15_t)0x800c, + (q15_t)0x356, (q15_t)0x800c, (q15_t)0x350, (q15_t)0x800b, (q15_t)0x349, (q15_t)0x800b, (q15_t)0x343, (q15_t)0x800b, + (q15_t)0x33d, (q15_t)0x800b, (q15_t)0x337, (q15_t)0x800b, (q15_t)0x330, (q15_t)0x800b, (q15_t)0x32a, (q15_t)0x800b, + (q15_t)0x324, (q15_t)0x800a, (q15_t)0x31d, (q15_t)0x800a, (q15_t)0x317, (q15_t)0x800a, (q15_t)0x311, (q15_t)0x800a, + (q15_t)0x30b, (q15_t)0x800a, (q15_t)0x304, (q15_t)0x800a, (q15_t)0x2fe, (q15_t)0x8009, (q15_t)0x2f8, (q15_t)0x8009, + (q15_t)0x2f1, (q15_t)0x8009, (q15_t)0x2eb, (q15_t)0x8009, (q15_t)0x2e5, (q15_t)0x8009, (q15_t)0x2df, (q15_t)0x8009, + (q15_t)0x2d8, (q15_t)0x8009, (q15_t)0x2d2, (q15_t)0x8008, (q15_t)0x2cc, (q15_t)0x8008, (q15_t)0x2c5, (q15_t)0x8008, + (q15_t)0x2bf, (q15_t)0x8008, (q15_t)0x2b9, (q15_t)0x8008, (q15_t)0x2b3, (q15_t)0x8008, (q15_t)0x2ac, (q15_t)0x8008, + (q15_t)0x2a6, (q15_t)0x8008, (q15_t)0x2a0, (q15_t)0x8007, (q15_t)0x299, (q15_t)0x8007, (q15_t)0x293, (q15_t)0x8007, + (q15_t)0x28d, (q15_t)0x8007, (q15_t)0x287, (q15_t)0x8007, (q15_t)0x280, (q15_t)0x8007, (q15_t)0x27a, (q15_t)0x8007, + (q15_t)0x274, (q15_t)0x8007, (q15_t)0x26d, (q15_t)0x8006, (q15_t)0x267, (q15_t)0x8006, (q15_t)0x261, (q15_t)0x8006, + (q15_t)0x25b, (q15_t)0x8006, (q15_t)0x254, (q15_t)0x8006, (q15_t)0x24e, (q15_t)0x8006, (q15_t)0x248, (q15_t)0x8006, + (q15_t)0x242, (q15_t)0x8006, (q15_t)0x23b, (q15_t)0x8005, (q15_t)0x235, (q15_t)0x8005, (q15_t)0x22f, (q15_t)0x8005, + (q15_t)0x228, (q15_t)0x8005, (q15_t)0x222, (q15_t)0x8005, (q15_t)0x21c, (q15_t)0x8005, (q15_t)0x216, (q15_t)0x8005, + (q15_t)0x20f, (q15_t)0x8005, (q15_t)0x209, (q15_t)0x8005, (q15_t)0x203, (q15_t)0x8005, (q15_t)0x1fc, (q15_t)0x8004, + (q15_t)0x1f6, (q15_t)0x8004, (q15_t)0x1f0, (q15_t)0x8004, (q15_t)0x1ea, (q15_t)0x8004, (q15_t)0x1e3, (q15_t)0x8004, + (q15_t)0x1dd, (q15_t)0x8004, (q15_t)0x1d7, (q15_t)0x8004, (q15_t)0x1d0, (q15_t)0x8004, (q15_t)0x1ca, (q15_t)0x8004, + (q15_t)0x1c4, (q15_t)0x8004, (q15_t)0x1be, (q15_t)0x8004, (q15_t)0x1b7, (q15_t)0x8003, (q15_t)0x1b1, (q15_t)0x8003, + (q15_t)0x1ab, (q15_t)0x8003, (q15_t)0x1a4, (q15_t)0x8003, (q15_t)0x19e, (q15_t)0x8003, (q15_t)0x198, (q15_t)0x8003, + (q15_t)0x192, (q15_t)0x8003, (q15_t)0x18b, (q15_t)0x8003, (q15_t)0x185, (q15_t)0x8003, (q15_t)0x17f, (q15_t)0x8003, + (q15_t)0x178, (q15_t)0x8003, (q15_t)0x172, (q15_t)0x8003, (q15_t)0x16c, (q15_t)0x8003, (q15_t)0x166, (q15_t)0x8002, + (q15_t)0x15f, (q15_t)0x8002, (q15_t)0x159, (q15_t)0x8002, (q15_t)0x153, (q15_t)0x8002, (q15_t)0x14d, (q15_t)0x8002, + (q15_t)0x146, (q15_t)0x8002, (q15_t)0x140, (q15_t)0x8002, (q15_t)0x13a, (q15_t)0x8002, (q15_t)0x133, (q15_t)0x8002, + (q15_t)0x12d, (q15_t)0x8002, (q15_t)0x127, (q15_t)0x8002, (q15_t)0x121, (q15_t)0x8002, (q15_t)0x11a, (q15_t)0x8002, + (q15_t)0x114, (q15_t)0x8002, (q15_t)0x10e, (q15_t)0x8002, (q15_t)0x107, (q15_t)0x8002, (q15_t)0x101, (q15_t)0x8002, + (q15_t)0xfb, (q15_t)0x8001, (q15_t)0xf5, (q15_t)0x8001, (q15_t)0xee, (q15_t)0x8001, (q15_t)0xe8, (q15_t)0x8001, + (q15_t)0xe2, (q15_t)0x8001, (q15_t)0xdb, (q15_t)0x8001, (q15_t)0xd5, (q15_t)0x8001, (q15_t)0xcf, (q15_t)0x8001, + (q15_t)0xc9, (q15_t)0x8001, (q15_t)0xc2, (q15_t)0x8001, (q15_t)0xbc, (q15_t)0x8001, (q15_t)0xb6, (q15_t)0x8001, + (q15_t)0xaf, (q15_t)0x8001, (q15_t)0xa9, (q15_t)0x8001, (q15_t)0xa3, (q15_t)0x8001, (q15_t)0x9d, (q15_t)0x8001, + (q15_t)0x96, (q15_t)0x8001, (q15_t)0x90, (q15_t)0x8001, (q15_t)0x8a, (q15_t)0x8001, (q15_t)0x83, (q15_t)0x8001, + (q15_t)0x7d, (q15_t)0x8001, (q15_t)0x77, (q15_t)0x8001, (q15_t)0x71, (q15_t)0x8001, (q15_t)0x6a, (q15_t)0x8001, + (q15_t)0x64, (q15_t)0x8001, (q15_t)0x5e, (q15_t)0x8001, (q15_t)0x57, (q15_t)0x8001, (q15_t)0x51, (q15_t)0x8001, + (q15_t)0x4b, (q15_t)0x8001, (q15_t)0x45, (q15_t)0x8001, (q15_t)0x3e, (q15_t)0x8001, (q15_t)0x38, (q15_t)0x8001, + (q15_t)0x32, (q15_t)0x8001, (q15_t)0x2b, (q15_t)0x8001, (q15_t)0x25, (q15_t)0x8001, (q15_t)0x1f, (q15_t)0x8001, + (q15_t)0x19, (q15_t)0x8001, (q15_t)0x12, (q15_t)0x8001, (q15_t)0xc, (q15_t)0x8001, (q15_t)0x6, (q15_t)0x8001 +}; + + const q15_t __ALIGNED(4) cos_factorsQ15_8192[8192] = { + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, + (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, + (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, + (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffc, + (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, + (q15_t)0x7ffc, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, + (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, + (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, + (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff8, + (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff7, + (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, + (q15_t)0x7ff6, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff4, + (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff3, + (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff2, (q15_t)0x7ff2, (q15_t)0x7ff2, (q15_t)0x7ff2, (q15_t)0x7ff2, + (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff0, (q15_t)0x7ff0, + (q15_t)0x7ff0, (q15_t)0x7ff0, (q15_t)0x7ff0, (q15_t)0x7fef, (q15_t)0x7fef, (q15_t)0x7fef, (q15_t)0x7fef, (q15_t)0x7fef, + (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fed, (q15_t)0x7fed, (q15_t)0x7fed, + (q15_t)0x7fed, (q15_t)0x7fed, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7feb, (q15_t)0x7feb, + (q15_t)0x7feb, (q15_t)0x7feb, (q15_t)0x7feb, (q15_t)0x7fea, (q15_t)0x7fea, (q15_t)0x7fea, (q15_t)0x7fea, (q15_t)0x7fe9, + (q15_t)0x7fe9, (q15_t)0x7fe9, (q15_t)0x7fe9, (q15_t)0x7fe8, (q15_t)0x7fe8, (q15_t)0x7fe8, (q15_t)0x7fe8, (q15_t)0x7fe8, + (q15_t)0x7fe7, (q15_t)0x7fe7, (q15_t)0x7fe7, (q15_t)0x7fe7, (q15_t)0x7fe6, (q15_t)0x7fe6, (q15_t)0x7fe6, (q15_t)0x7fe6, + (q15_t)0x7fe5, (q15_t)0x7fe5, (q15_t)0x7fe5, (q15_t)0x7fe5, (q15_t)0x7fe4, (q15_t)0x7fe4, (q15_t)0x7fe4, (q15_t)0x7fe4, + (q15_t)0x7fe3, (q15_t)0x7fe3, (q15_t)0x7fe3, (q15_t)0x7fe2, (q15_t)0x7fe2, (q15_t)0x7fe2, (q15_t)0x7fe2, (q15_t)0x7fe1, + (q15_t)0x7fe1, (q15_t)0x7fe1, (q15_t)0x7fe1, (q15_t)0x7fe0, (q15_t)0x7fe0, (q15_t)0x7fe0, (q15_t)0x7fdf, (q15_t)0x7fdf, + (q15_t)0x7fdf, (q15_t)0x7fdf, (q15_t)0x7fde, (q15_t)0x7fde, (q15_t)0x7fde, (q15_t)0x7fde, (q15_t)0x7fdd, (q15_t)0x7fdd, + (q15_t)0x7fdd, (q15_t)0x7fdc, (q15_t)0x7fdc, (q15_t)0x7fdc, (q15_t)0x7fdb, (q15_t)0x7fdb, (q15_t)0x7fdb, (q15_t)0x7fdb, + (q15_t)0x7fda, (q15_t)0x7fda, (q15_t)0x7fda, (q15_t)0x7fd9, (q15_t)0x7fd9, (q15_t)0x7fd9, (q15_t)0x7fd8, (q15_t)0x7fd8, + (q15_t)0x7fd8, (q15_t)0x7fd8, (q15_t)0x7fd7, (q15_t)0x7fd7, (q15_t)0x7fd7, (q15_t)0x7fd6, (q15_t)0x7fd6, (q15_t)0x7fd6, + (q15_t)0x7fd5, (q15_t)0x7fd5, (q15_t)0x7fd5, (q15_t)0x7fd4, (q15_t)0x7fd4, (q15_t)0x7fd4, (q15_t)0x7fd3, (q15_t)0x7fd3, + (q15_t)0x7fd3, (q15_t)0x7fd2, (q15_t)0x7fd2, (q15_t)0x7fd2, (q15_t)0x7fd1, (q15_t)0x7fd1, (q15_t)0x7fd1, (q15_t)0x7fd0, + (q15_t)0x7fd0, (q15_t)0x7fd0, (q15_t)0x7fcf, (q15_t)0x7fcf, (q15_t)0x7fcf, (q15_t)0x7fce, (q15_t)0x7fce, (q15_t)0x7fce, + (q15_t)0x7fcd, (q15_t)0x7fcd, (q15_t)0x7fcd, (q15_t)0x7fcc, (q15_t)0x7fcc, (q15_t)0x7fcc, (q15_t)0x7fcb, (q15_t)0x7fcb, + (q15_t)0x7fcb, (q15_t)0x7fca, (q15_t)0x7fca, (q15_t)0x7fc9, (q15_t)0x7fc9, (q15_t)0x7fc9, (q15_t)0x7fc8, (q15_t)0x7fc8, + (q15_t)0x7fc8, (q15_t)0x7fc7, (q15_t)0x7fc7, (q15_t)0x7fc7, (q15_t)0x7fc6, (q15_t)0x7fc6, (q15_t)0x7fc5, (q15_t)0x7fc5, + (q15_t)0x7fc5, (q15_t)0x7fc4, (q15_t)0x7fc4, (q15_t)0x7fc4, (q15_t)0x7fc3, (q15_t)0x7fc3, (q15_t)0x7fc2, (q15_t)0x7fc2, + (q15_t)0x7fc2, (q15_t)0x7fc1, (q15_t)0x7fc1, (q15_t)0x7fc0, (q15_t)0x7fc0, (q15_t)0x7fc0, (q15_t)0x7fbf, (q15_t)0x7fbf, + (q15_t)0x7fbf, (q15_t)0x7fbe, (q15_t)0x7fbe, (q15_t)0x7fbd, (q15_t)0x7fbd, (q15_t)0x7fbd, (q15_t)0x7fbc, (q15_t)0x7fbc, + (q15_t)0x7fbb, (q15_t)0x7fbb, (q15_t)0x7fbb, (q15_t)0x7fba, (q15_t)0x7fba, (q15_t)0x7fb9, (q15_t)0x7fb9, (q15_t)0x7fb8, + (q15_t)0x7fb8, (q15_t)0x7fb8, (q15_t)0x7fb7, (q15_t)0x7fb7, (q15_t)0x7fb6, (q15_t)0x7fb6, (q15_t)0x7fb6, (q15_t)0x7fb5, + (q15_t)0x7fb5, (q15_t)0x7fb4, (q15_t)0x7fb4, (q15_t)0x7fb3, (q15_t)0x7fb3, (q15_t)0x7fb3, (q15_t)0x7fb2, (q15_t)0x7fb2, + (q15_t)0x7fb1, (q15_t)0x7fb1, (q15_t)0x7fb0, (q15_t)0x7fb0, (q15_t)0x7faf, (q15_t)0x7faf, (q15_t)0x7faf, (q15_t)0x7fae, + (q15_t)0x7fae, (q15_t)0x7fad, (q15_t)0x7fad, (q15_t)0x7fac, (q15_t)0x7fac, (q15_t)0x7fac, (q15_t)0x7fab, (q15_t)0x7fab, + (q15_t)0x7faa, (q15_t)0x7faa, (q15_t)0x7fa9, (q15_t)0x7fa9, (q15_t)0x7fa8, (q15_t)0x7fa8, (q15_t)0x7fa7, (q15_t)0x7fa7, + (q15_t)0x7fa6, (q15_t)0x7fa6, (q15_t)0x7fa6, (q15_t)0x7fa5, (q15_t)0x7fa5, (q15_t)0x7fa4, (q15_t)0x7fa4, (q15_t)0x7fa3, + (q15_t)0x7fa3, (q15_t)0x7fa2, (q15_t)0x7fa2, (q15_t)0x7fa1, (q15_t)0x7fa1, (q15_t)0x7fa0, (q15_t)0x7fa0, (q15_t)0x7f9f, + (q15_t)0x7f9f, (q15_t)0x7f9e, (q15_t)0x7f9e, (q15_t)0x7f9d, (q15_t)0x7f9d, (q15_t)0x7f9c, (q15_t)0x7f9c, (q15_t)0x7f9c, + (q15_t)0x7f9b, (q15_t)0x7f9b, (q15_t)0x7f9a, (q15_t)0x7f9a, (q15_t)0x7f99, (q15_t)0x7f99, (q15_t)0x7f98, (q15_t)0x7f98, + (q15_t)0x7f97, (q15_t)0x7f97, (q15_t)0x7f96, (q15_t)0x7f96, (q15_t)0x7f95, (q15_t)0x7f95, (q15_t)0x7f94, (q15_t)0x7f94, + (q15_t)0x7f93, (q15_t)0x7f92, (q15_t)0x7f92, (q15_t)0x7f91, (q15_t)0x7f91, (q15_t)0x7f90, (q15_t)0x7f90, (q15_t)0x7f8f, + (q15_t)0x7f8f, (q15_t)0x7f8e, (q15_t)0x7f8e, (q15_t)0x7f8d, (q15_t)0x7f8d, (q15_t)0x7f8c, (q15_t)0x7f8c, (q15_t)0x7f8b, + (q15_t)0x7f8b, (q15_t)0x7f8a, (q15_t)0x7f8a, (q15_t)0x7f89, (q15_t)0x7f89, (q15_t)0x7f88, (q15_t)0x7f87, (q15_t)0x7f87, + (q15_t)0x7f86, (q15_t)0x7f86, (q15_t)0x7f85, (q15_t)0x7f85, (q15_t)0x7f84, (q15_t)0x7f84, (q15_t)0x7f83, (q15_t)0x7f83, + (q15_t)0x7f82, (q15_t)0x7f81, (q15_t)0x7f81, (q15_t)0x7f80, (q15_t)0x7f80, (q15_t)0x7f7f, (q15_t)0x7f7f, (q15_t)0x7f7e, + (q15_t)0x7f7e, (q15_t)0x7f7d, (q15_t)0x7f7c, (q15_t)0x7f7c, (q15_t)0x7f7b, (q15_t)0x7f7b, (q15_t)0x7f7a, (q15_t)0x7f7a, + (q15_t)0x7f79, (q15_t)0x7f79, (q15_t)0x7f78, (q15_t)0x7f77, (q15_t)0x7f77, (q15_t)0x7f76, (q15_t)0x7f76, (q15_t)0x7f75, + (q15_t)0x7f75, (q15_t)0x7f74, (q15_t)0x7f73, (q15_t)0x7f73, (q15_t)0x7f72, (q15_t)0x7f72, (q15_t)0x7f71, (q15_t)0x7f70, + (q15_t)0x7f70, (q15_t)0x7f6f, (q15_t)0x7f6f, (q15_t)0x7f6e, (q15_t)0x7f6d, (q15_t)0x7f6d, (q15_t)0x7f6c, (q15_t)0x7f6c, + (q15_t)0x7f6b, (q15_t)0x7f6b, (q15_t)0x7f6a, (q15_t)0x7f69, (q15_t)0x7f69, (q15_t)0x7f68, (q15_t)0x7f68, (q15_t)0x7f67, + (q15_t)0x7f66, (q15_t)0x7f66, (q15_t)0x7f65, (q15_t)0x7f64, (q15_t)0x7f64, (q15_t)0x7f63, (q15_t)0x7f63, (q15_t)0x7f62, + (q15_t)0x7f61, (q15_t)0x7f61, (q15_t)0x7f60, (q15_t)0x7f60, (q15_t)0x7f5f, (q15_t)0x7f5e, (q15_t)0x7f5e, (q15_t)0x7f5d, + (q15_t)0x7f5c, (q15_t)0x7f5c, (q15_t)0x7f5b, (q15_t)0x7f5b, (q15_t)0x7f5a, (q15_t)0x7f59, (q15_t)0x7f59, (q15_t)0x7f58, + (q15_t)0x7f57, (q15_t)0x7f57, (q15_t)0x7f56, (q15_t)0x7f55, (q15_t)0x7f55, (q15_t)0x7f54, (q15_t)0x7f54, (q15_t)0x7f53, + (q15_t)0x7f52, (q15_t)0x7f52, (q15_t)0x7f51, (q15_t)0x7f50, (q15_t)0x7f50, (q15_t)0x7f4f, (q15_t)0x7f4e, (q15_t)0x7f4e, + (q15_t)0x7f4d, (q15_t)0x7f4c, (q15_t)0x7f4c, (q15_t)0x7f4b, (q15_t)0x7f4a, (q15_t)0x7f4a, (q15_t)0x7f49, (q15_t)0x7f48, + (q15_t)0x7f48, (q15_t)0x7f47, (q15_t)0x7f46, (q15_t)0x7f46, (q15_t)0x7f45, (q15_t)0x7f44, (q15_t)0x7f44, (q15_t)0x7f43, + (q15_t)0x7f42, (q15_t)0x7f42, (q15_t)0x7f41, (q15_t)0x7f40, (q15_t)0x7f40, (q15_t)0x7f3f, (q15_t)0x7f3e, (q15_t)0x7f3e, + (q15_t)0x7f3d, (q15_t)0x7f3c, (q15_t)0x7f3c, (q15_t)0x7f3b, (q15_t)0x7f3a, (q15_t)0x7f3a, (q15_t)0x7f39, (q15_t)0x7f38, + (q15_t)0x7f37, (q15_t)0x7f37, (q15_t)0x7f36, (q15_t)0x7f35, (q15_t)0x7f35, (q15_t)0x7f34, (q15_t)0x7f33, (q15_t)0x7f33, + (q15_t)0x7f32, (q15_t)0x7f31, (q15_t)0x7f31, (q15_t)0x7f30, (q15_t)0x7f2f, (q15_t)0x7f2e, (q15_t)0x7f2e, (q15_t)0x7f2d, + (q15_t)0x7f2c, (q15_t)0x7f2c, (q15_t)0x7f2b, (q15_t)0x7f2a, (q15_t)0x7f29, (q15_t)0x7f29, (q15_t)0x7f28, (q15_t)0x7f27, + (q15_t)0x7f27, (q15_t)0x7f26, (q15_t)0x7f25, (q15_t)0x7f24, (q15_t)0x7f24, (q15_t)0x7f23, (q15_t)0x7f22, (q15_t)0x7f21, + (q15_t)0x7f21, (q15_t)0x7f20, (q15_t)0x7f1f, (q15_t)0x7f1f, (q15_t)0x7f1e, (q15_t)0x7f1d, (q15_t)0x7f1c, (q15_t)0x7f1c, + (q15_t)0x7f1b, (q15_t)0x7f1a, (q15_t)0x7f19, (q15_t)0x7f19, (q15_t)0x7f18, (q15_t)0x7f17, (q15_t)0x7f16, (q15_t)0x7f16, + (q15_t)0x7f15, (q15_t)0x7f14, (q15_t)0x7f13, (q15_t)0x7f13, (q15_t)0x7f12, (q15_t)0x7f11, (q15_t)0x7f10, (q15_t)0x7f10, + (q15_t)0x7f0f, (q15_t)0x7f0e, (q15_t)0x7f0d, (q15_t)0x7f0d, (q15_t)0x7f0c, (q15_t)0x7f0b, (q15_t)0x7f0a, (q15_t)0x7f09, + (q15_t)0x7f09, (q15_t)0x7f08, (q15_t)0x7f07, (q15_t)0x7f06, (q15_t)0x7f06, (q15_t)0x7f05, (q15_t)0x7f04, (q15_t)0x7f03, + (q15_t)0x7f02, (q15_t)0x7f02, (q15_t)0x7f01, (q15_t)0x7f00, (q15_t)0x7eff, (q15_t)0x7eff, (q15_t)0x7efe, (q15_t)0x7efd, + (q15_t)0x7efc, (q15_t)0x7efb, (q15_t)0x7efb, (q15_t)0x7efa, (q15_t)0x7ef9, (q15_t)0x7ef8, (q15_t)0x7ef7, (q15_t)0x7ef7, + (q15_t)0x7ef6, (q15_t)0x7ef5, (q15_t)0x7ef4, (q15_t)0x7ef3, (q15_t)0x7ef3, (q15_t)0x7ef2, (q15_t)0x7ef1, (q15_t)0x7ef0, + (q15_t)0x7eef, (q15_t)0x7eef, (q15_t)0x7eee, (q15_t)0x7eed, (q15_t)0x7eec, (q15_t)0x7eeb, (q15_t)0x7eeb, (q15_t)0x7eea, + (q15_t)0x7ee9, (q15_t)0x7ee8, (q15_t)0x7ee7, (q15_t)0x7ee6, (q15_t)0x7ee6, (q15_t)0x7ee5, (q15_t)0x7ee4, (q15_t)0x7ee3, + (q15_t)0x7ee2, (q15_t)0x7ee2, (q15_t)0x7ee1, (q15_t)0x7ee0, (q15_t)0x7edf, (q15_t)0x7ede, (q15_t)0x7edd, (q15_t)0x7edd, + (q15_t)0x7edc, (q15_t)0x7edb, (q15_t)0x7eda, (q15_t)0x7ed9, (q15_t)0x7ed8, (q15_t)0x7ed8, (q15_t)0x7ed7, (q15_t)0x7ed6, + (q15_t)0x7ed5, (q15_t)0x7ed4, (q15_t)0x7ed3, (q15_t)0x7ed2, (q15_t)0x7ed2, (q15_t)0x7ed1, (q15_t)0x7ed0, (q15_t)0x7ecf, + (q15_t)0x7ece, (q15_t)0x7ecd, (q15_t)0x7ecc, (q15_t)0x7ecc, (q15_t)0x7ecb, (q15_t)0x7eca, (q15_t)0x7ec9, (q15_t)0x7ec8, + (q15_t)0x7ec7, (q15_t)0x7ec6, (q15_t)0x7ec6, (q15_t)0x7ec5, (q15_t)0x7ec4, (q15_t)0x7ec3, (q15_t)0x7ec2, (q15_t)0x7ec1, + (q15_t)0x7ec0, (q15_t)0x7ebf, (q15_t)0x7ebf, (q15_t)0x7ebe, (q15_t)0x7ebd, (q15_t)0x7ebc, (q15_t)0x7ebb, (q15_t)0x7eba, + (q15_t)0x7eb9, (q15_t)0x7eb8, (q15_t)0x7eb8, (q15_t)0x7eb7, (q15_t)0x7eb6, (q15_t)0x7eb5, (q15_t)0x7eb4, (q15_t)0x7eb3, + (q15_t)0x7eb2, (q15_t)0x7eb1, (q15_t)0x7eb0, (q15_t)0x7eaf, (q15_t)0x7eaf, (q15_t)0x7eae, (q15_t)0x7ead, (q15_t)0x7eac, + (q15_t)0x7eab, (q15_t)0x7eaa, (q15_t)0x7ea9, (q15_t)0x7ea8, (q15_t)0x7ea7, (q15_t)0x7ea6, (q15_t)0x7ea6, (q15_t)0x7ea5, + (q15_t)0x7ea4, (q15_t)0x7ea3, (q15_t)0x7ea2, (q15_t)0x7ea1, (q15_t)0x7ea0, (q15_t)0x7e9f, (q15_t)0x7e9e, (q15_t)0x7e9d, + (q15_t)0x7e9c, (q15_t)0x7e9b, (q15_t)0x7e9b, (q15_t)0x7e9a, (q15_t)0x7e99, (q15_t)0x7e98, (q15_t)0x7e97, (q15_t)0x7e96, + (q15_t)0x7e95, (q15_t)0x7e94, (q15_t)0x7e93, (q15_t)0x7e92, (q15_t)0x7e91, (q15_t)0x7e90, (q15_t)0x7e8f, (q15_t)0x7e8e, + (q15_t)0x7e8d, (q15_t)0x7e8d, (q15_t)0x7e8c, (q15_t)0x7e8b, (q15_t)0x7e8a, (q15_t)0x7e89, (q15_t)0x7e88, (q15_t)0x7e87, + (q15_t)0x7e86, (q15_t)0x7e85, (q15_t)0x7e84, (q15_t)0x7e83, (q15_t)0x7e82, (q15_t)0x7e81, (q15_t)0x7e80, (q15_t)0x7e7f, + (q15_t)0x7e7e, (q15_t)0x7e7d, (q15_t)0x7e7c, (q15_t)0x7e7b, (q15_t)0x7e7a, (q15_t)0x7e79, (q15_t)0x7e78, (q15_t)0x7e77, + (q15_t)0x7e77, (q15_t)0x7e76, (q15_t)0x7e75, (q15_t)0x7e74, (q15_t)0x7e73, (q15_t)0x7e72, (q15_t)0x7e71, (q15_t)0x7e70, + (q15_t)0x7e6f, (q15_t)0x7e6e, (q15_t)0x7e6d, (q15_t)0x7e6c, (q15_t)0x7e6b, (q15_t)0x7e6a, (q15_t)0x7e69, (q15_t)0x7e68, + (q15_t)0x7e67, (q15_t)0x7e66, (q15_t)0x7e65, (q15_t)0x7e64, (q15_t)0x7e63, (q15_t)0x7e62, (q15_t)0x7e61, (q15_t)0x7e60, + (q15_t)0x7e5f, (q15_t)0x7e5e, (q15_t)0x7e5d, (q15_t)0x7e5c, (q15_t)0x7e5b, (q15_t)0x7e5a, (q15_t)0x7e59, (q15_t)0x7e58, + (q15_t)0x7e57, (q15_t)0x7e56, (q15_t)0x7e55, (q15_t)0x7e54, (q15_t)0x7e53, (q15_t)0x7e52, (q15_t)0x7e51, (q15_t)0x7e50, + (q15_t)0x7e4f, (q15_t)0x7e4e, (q15_t)0x7e4d, (q15_t)0x7e4c, (q15_t)0x7e4b, (q15_t)0x7e4a, (q15_t)0x7e49, (q15_t)0x7e48, + (q15_t)0x7e47, (q15_t)0x7e46, (q15_t)0x7e45, (q15_t)0x7e43, (q15_t)0x7e42, (q15_t)0x7e41, (q15_t)0x7e40, (q15_t)0x7e3f, + (q15_t)0x7e3e, (q15_t)0x7e3d, (q15_t)0x7e3c, (q15_t)0x7e3b, (q15_t)0x7e3a, (q15_t)0x7e39, (q15_t)0x7e38, (q15_t)0x7e37, + (q15_t)0x7e36, (q15_t)0x7e35, (q15_t)0x7e34, (q15_t)0x7e33, (q15_t)0x7e32, (q15_t)0x7e31, (q15_t)0x7e30, (q15_t)0x7e2f, + (q15_t)0x7e2e, (q15_t)0x7e2d, (q15_t)0x7e2b, (q15_t)0x7e2a, (q15_t)0x7e29, (q15_t)0x7e28, (q15_t)0x7e27, (q15_t)0x7e26, + (q15_t)0x7e25, (q15_t)0x7e24, (q15_t)0x7e23, (q15_t)0x7e22, (q15_t)0x7e21, (q15_t)0x7e20, (q15_t)0x7e1f, (q15_t)0x7e1e, + (q15_t)0x7e1d, (q15_t)0x7e1b, (q15_t)0x7e1a, (q15_t)0x7e19, (q15_t)0x7e18, (q15_t)0x7e17, (q15_t)0x7e16, (q15_t)0x7e15, + (q15_t)0x7e14, (q15_t)0x7e13, (q15_t)0x7e12, (q15_t)0x7e11, (q15_t)0x7e10, (q15_t)0x7e0e, (q15_t)0x7e0d, (q15_t)0x7e0c, + (q15_t)0x7e0b, (q15_t)0x7e0a, (q15_t)0x7e09, (q15_t)0x7e08, (q15_t)0x7e07, (q15_t)0x7e06, (q15_t)0x7e05, (q15_t)0x7e04, + (q15_t)0x7e02, (q15_t)0x7e01, (q15_t)0x7e00, (q15_t)0x7dff, (q15_t)0x7dfe, (q15_t)0x7dfd, (q15_t)0x7dfc, (q15_t)0x7dfb, + (q15_t)0x7dfa, (q15_t)0x7df8, (q15_t)0x7df7, (q15_t)0x7df6, (q15_t)0x7df5, (q15_t)0x7df4, (q15_t)0x7df3, (q15_t)0x7df2, + (q15_t)0x7df1, (q15_t)0x7def, (q15_t)0x7dee, (q15_t)0x7ded, (q15_t)0x7dec, (q15_t)0x7deb, (q15_t)0x7dea, (q15_t)0x7de9, + (q15_t)0x7de8, (q15_t)0x7de6, (q15_t)0x7de5, (q15_t)0x7de4, (q15_t)0x7de3, (q15_t)0x7de2, (q15_t)0x7de1, (q15_t)0x7de0, + (q15_t)0x7dde, (q15_t)0x7ddd, (q15_t)0x7ddc, (q15_t)0x7ddb, (q15_t)0x7dda, (q15_t)0x7dd9, (q15_t)0x7dd8, (q15_t)0x7dd6, + (q15_t)0x7dd5, (q15_t)0x7dd4, (q15_t)0x7dd3, (q15_t)0x7dd2, (q15_t)0x7dd1, (q15_t)0x7dd0, (q15_t)0x7dce, (q15_t)0x7dcd, + (q15_t)0x7dcc, (q15_t)0x7dcb, (q15_t)0x7dca, (q15_t)0x7dc9, (q15_t)0x7dc7, (q15_t)0x7dc6, (q15_t)0x7dc5, (q15_t)0x7dc4, + (q15_t)0x7dc3, (q15_t)0x7dc2, (q15_t)0x7dc0, (q15_t)0x7dbf, (q15_t)0x7dbe, (q15_t)0x7dbd, (q15_t)0x7dbc, (q15_t)0x7dbb, + (q15_t)0x7db9, (q15_t)0x7db8, (q15_t)0x7db7, (q15_t)0x7db6, (q15_t)0x7db5, (q15_t)0x7db3, (q15_t)0x7db2, (q15_t)0x7db1, + (q15_t)0x7db0, (q15_t)0x7daf, (q15_t)0x7dae, (q15_t)0x7dac, (q15_t)0x7dab, (q15_t)0x7daa, (q15_t)0x7da9, (q15_t)0x7da8, + (q15_t)0x7da6, (q15_t)0x7da5, (q15_t)0x7da4, (q15_t)0x7da3, (q15_t)0x7da2, (q15_t)0x7da0, (q15_t)0x7d9f, (q15_t)0x7d9e, + (q15_t)0x7d9d, (q15_t)0x7d9c, (q15_t)0x7d9a, (q15_t)0x7d99, (q15_t)0x7d98, (q15_t)0x7d97, (q15_t)0x7d95, (q15_t)0x7d94, + (q15_t)0x7d93, (q15_t)0x7d92, (q15_t)0x7d91, (q15_t)0x7d8f, (q15_t)0x7d8e, (q15_t)0x7d8d, (q15_t)0x7d8c, (q15_t)0x7d8a, + (q15_t)0x7d89, (q15_t)0x7d88, (q15_t)0x7d87, (q15_t)0x7d86, (q15_t)0x7d84, (q15_t)0x7d83, (q15_t)0x7d82, (q15_t)0x7d81, + (q15_t)0x7d7f, (q15_t)0x7d7e, (q15_t)0x7d7d, (q15_t)0x7d7c, (q15_t)0x7d7a, (q15_t)0x7d79, (q15_t)0x7d78, (q15_t)0x7d77, + (q15_t)0x7d75, (q15_t)0x7d74, (q15_t)0x7d73, (q15_t)0x7d72, (q15_t)0x7d70, (q15_t)0x7d6f, (q15_t)0x7d6e, (q15_t)0x7d6d, + (q15_t)0x7d6b, (q15_t)0x7d6a, (q15_t)0x7d69, (q15_t)0x7d68, (q15_t)0x7d66, (q15_t)0x7d65, (q15_t)0x7d64, (q15_t)0x7d63, + (q15_t)0x7d61, (q15_t)0x7d60, (q15_t)0x7d5f, (q15_t)0x7d5e, (q15_t)0x7d5c, (q15_t)0x7d5b, (q15_t)0x7d5a, (q15_t)0x7d59, + (q15_t)0x7d57, (q15_t)0x7d56, (q15_t)0x7d55, (q15_t)0x7d53, (q15_t)0x7d52, (q15_t)0x7d51, (q15_t)0x7d50, (q15_t)0x7d4e, + (q15_t)0x7d4d, (q15_t)0x7d4c, (q15_t)0x7d4a, (q15_t)0x7d49, (q15_t)0x7d48, (q15_t)0x7d47, (q15_t)0x7d45, (q15_t)0x7d44, + (q15_t)0x7d43, (q15_t)0x7d41, (q15_t)0x7d40, (q15_t)0x7d3f, (q15_t)0x7d3e, (q15_t)0x7d3c, (q15_t)0x7d3b, (q15_t)0x7d3a, + (q15_t)0x7d38, (q15_t)0x7d37, (q15_t)0x7d36, (q15_t)0x7d34, (q15_t)0x7d33, (q15_t)0x7d32, (q15_t)0x7d31, (q15_t)0x7d2f, + (q15_t)0x7d2e, (q15_t)0x7d2d, (q15_t)0x7d2b, (q15_t)0x7d2a, (q15_t)0x7d29, (q15_t)0x7d27, (q15_t)0x7d26, (q15_t)0x7d25, + (q15_t)0x7d23, (q15_t)0x7d22, (q15_t)0x7d21, (q15_t)0x7d1f, (q15_t)0x7d1e, (q15_t)0x7d1d, (q15_t)0x7d1b, (q15_t)0x7d1a, + (q15_t)0x7d19, (q15_t)0x7d17, (q15_t)0x7d16, (q15_t)0x7d15, (q15_t)0x7d13, (q15_t)0x7d12, (q15_t)0x7d11, (q15_t)0x7d0f, + (q15_t)0x7d0e, (q15_t)0x7d0d, (q15_t)0x7d0b, (q15_t)0x7d0a, (q15_t)0x7d09, (q15_t)0x7d07, (q15_t)0x7d06, (q15_t)0x7d05, + (q15_t)0x7d03, (q15_t)0x7d02, (q15_t)0x7d01, (q15_t)0x7cff, (q15_t)0x7cfe, (q15_t)0x7cfd, (q15_t)0x7cfb, (q15_t)0x7cfa, + (q15_t)0x7cf9, (q15_t)0x7cf7, (q15_t)0x7cf6, (q15_t)0x7cf4, (q15_t)0x7cf3, (q15_t)0x7cf2, (q15_t)0x7cf0, (q15_t)0x7cef, + (q15_t)0x7cee, (q15_t)0x7cec, (q15_t)0x7ceb, (q15_t)0x7ce9, (q15_t)0x7ce8, (q15_t)0x7ce7, (q15_t)0x7ce5, (q15_t)0x7ce4, + (q15_t)0x7ce3, (q15_t)0x7ce1, (q15_t)0x7ce0, (q15_t)0x7cde, (q15_t)0x7cdd, (q15_t)0x7cdc, (q15_t)0x7cda, (q15_t)0x7cd9, + (q15_t)0x7cd8, (q15_t)0x7cd6, (q15_t)0x7cd5, (q15_t)0x7cd3, (q15_t)0x7cd2, (q15_t)0x7cd1, (q15_t)0x7ccf, (q15_t)0x7cce, + (q15_t)0x7ccc, (q15_t)0x7ccb, (q15_t)0x7cca, (q15_t)0x7cc8, (q15_t)0x7cc7, (q15_t)0x7cc5, (q15_t)0x7cc4, (q15_t)0x7cc3, + (q15_t)0x7cc1, (q15_t)0x7cc0, (q15_t)0x7cbe, (q15_t)0x7cbd, (q15_t)0x7cbc, (q15_t)0x7cba, (q15_t)0x7cb9, (q15_t)0x7cb7, + (q15_t)0x7cb6, (q15_t)0x7cb5, (q15_t)0x7cb3, (q15_t)0x7cb2, (q15_t)0x7cb0, (q15_t)0x7caf, (q15_t)0x7cad, (q15_t)0x7cac, + (q15_t)0x7cab, (q15_t)0x7ca9, (q15_t)0x7ca8, (q15_t)0x7ca6, (q15_t)0x7ca5, (q15_t)0x7ca3, (q15_t)0x7ca2, (q15_t)0x7ca1, + (q15_t)0x7c9f, (q15_t)0x7c9e, (q15_t)0x7c9c, (q15_t)0x7c9b, (q15_t)0x7c99, (q15_t)0x7c98, (q15_t)0x7c97, (q15_t)0x7c95, + (q15_t)0x7c94, (q15_t)0x7c92, (q15_t)0x7c91, (q15_t)0x7c8f, (q15_t)0x7c8e, (q15_t)0x7c8c, (q15_t)0x7c8b, (q15_t)0x7c8a, + (q15_t)0x7c88, (q15_t)0x7c87, (q15_t)0x7c85, (q15_t)0x7c84, (q15_t)0x7c82, (q15_t)0x7c81, (q15_t)0x7c7f, (q15_t)0x7c7e, + (q15_t)0x7c7c, (q15_t)0x7c7b, (q15_t)0x7c79, (q15_t)0x7c78, (q15_t)0x7c77, (q15_t)0x7c75, (q15_t)0x7c74, (q15_t)0x7c72, + (q15_t)0x7c71, (q15_t)0x7c6f, (q15_t)0x7c6e, (q15_t)0x7c6c, (q15_t)0x7c6b, (q15_t)0x7c69, (q15_t)0x7c68, (q15_t)0x7c66, + (q15_t)0x7c65, (q15_t)0x7c63, (q15_t)0x7c62, (q15_t)0x7c60, (q15_t)0x7c5f, (q15_t)0x7c5d, (q15_t)0x7c5c, (q15_t)0x7c5a, + (q15_t)0x7c59, (q15_t)0x7c58, (q15_t)0x7c56, (q15_t)0x7c55, (q15_t)0x7c53, (q15_t)0x7c52, (q15_t)0x7c50, (q15_t)0x7c4f, + (q15_t)0x7c4d, (q15_t)0x7c4c, (q15_t)0x7c4a, (q15_t)0x7c49, (q15_t)0x7c47, (q15_t)0x7c46, (q15_t)0x7c44, (q15_t)0x7c43, + (q15_t)0x7c41, (q15_t)0x7c3f, (q15_t)0x7c3e, (q15_t)0x7c3c, (q15_t)0x7c3b, (q15_t)0x7c39, (q15_t)0x7c38, (q15_t)0x7c36, + (q15_t)0x7c35, (q15_t)0x7c33, (q15_t)0x7c32, (q15_t)0x7c30, (q15_t)0x7c2f, (q15_t)0x7c2d, (q15_t)0x7c2c, (q15_t)0x7c2a, + (q15_t)0x7c29, (q15_t)0x7c27, (q15_t)0x7c26, (q15_t)0x7c24, (q15_t)0x7c23, (q15_t)0x7c21, (q15_t)0x7c20, (q15_t)0x7c1e, + (q15_t)0x7c1c, (q15_t)0x7c1b, (q15_t)0x7c19, (q15_t)0x7c18, (q15_t)0x7c16, (q15_t)0x7c15, (q15_t)0x7c13, (q15_t)0x7c12, + (q15_t)0x7c10, (q15_t)0x7c0f, (q15_t)0x7c0d, (q15_t)0x7c0b, (q15_t)0x7c0a, (q15_t)0x7c08, (q15_t)0x7c07, (q15_t)0x7c05, + (q15_t)0x7c04, (q15_t)0x7c02, (q15_t)0x7c01, (q15_t)0x7bff, (q15_t)0x7bfd, (q15_t)0x7bfc, (q15_t)0x7bfa, (q15_t)0x7bf9, + (q15_t)0x7bf7, (q15_t)0x7bf6, (q15_t)0x7bf4, (q15_t)0x7bf3, (q15_t)0x7bf1, (q15_t)0x7bef, (q15_t)0x7bee, (q15_t)0x7bec, + (q15_t)0x7beb, (q15_t)0x7be9, (q15_t)0x7be8, (q15_t)0x7be6, (q15_t)0x7be4, (q15_t)0x7be3, (q15_t)0x7be1, (q15_t)0x7be0, + (q15_t)0x7bde, (q15_t)0x7bdc, (q15_t)0x7bdb, (q15_t)0x7bd9, (q15_t)0x7bd8, (q15_t)0x7bd6, (q15_t)0x7bd5, (q15_t)0x7bd3, + (q15_t)0x7bd1, (q15_t)0x7bd0, (q15_t)0x7bce, (q15_t)0x7bcd, (q15_t)0x7bcb, (q15_t)0x7bc9, (q15_t)0x7bc8, (q15_t)0x7bc6, + (q15_t)0x7bc5, (q15_t)0x7bc3, (q15_t)0x7bc1, (q15_t)0x7bc0, (q15_t)0x7bbe, (q15_t)0x7bbd, (q15_t)0x7bbb, (q15_t)0x7bb9, + (q15_t)0x7bb8, (q15_t)0x7bb6, (q15_t)0x7bb5, (q15_t)0x7bb3, (q15_t)0x7bb1, (q15_t)0x7bb0, (q15_t)0x7bae, (q15_t)0x7bac, + (q15_t)0x7bab, (q15_t)0x7ba9, (q15_t)0x7ba8, (q15_t)0x7ba6, (q15_t)0x7ba4, (q15_t)0x7ba3, (q15_t)0x7ba1, (q15_t)0x7b9f, + (q15_t)0x7b9e, (q15_t)0x7b9c, (q15_t)0x7b9b, (q15_t)0x7b99, (q15_t)0x7b97, (q15_t)0x7b96, (q15_t)0x7b94, (q15_t)0x7b92, + (q15_t)0x7b91, (q15_t)0x7b8f, (q15_t)0x7b8d, (q15_t)0x7b8c, (q15_t)0x7b8a, (q15_t)0x7b89, (q15_t)0x7b87, (q15_t)0x7b85, + (q15_t)0x7b84, (q15_t)0x7b82, (q15_t)0x7b80, (q15_t)0x7b7f, (q15_t)0x7b7d, (q15_t)0x7b7b, (q15_t)0x7b7a, (q15_t)0x7b78, + (q15_t)0x7b76, (q15_t)0x7b75, (q15_t)0x7b73, (q15_t)0x7b71, (q15_t)0x7b70, (q15_t)0x7b6e, (q15_t)0x7b6c, (q15_t)0x7b6b, + (q15_t)0x7b69, (q15_t)0x7b67, (q15_t)0x7b66, (q15_t)0x7b64, (q15_t)0x7b62, (q15_t)0x7b61, (q15_t)0x7b5f, (q15_t)0x7b5d, + (q15_t)0x7b5c, (q15_t)0x7b5a, (q15_t)0x7b58, (q15_t)0x7b57, (q15_t)0x7b55, (q15_t)0x7b53, (q15_t)0x7b52, (q15_t)0x7b50, + (q15_t)0x7b4e, (q15_t)0x7b4d, (q15_t)0x7b4b, (q15_t)0x7b49, (q15_t)0x7b47, (q15_t)0x7b46, (q15_t)0x7b44, (q15_t)0x7b42, + (q15_t)0x7b41, (q15_t)0x7b3f, (q15_t)0x7b3d, (q15_t)0x7b3c, (q15_t)0x7b3a, (q15_t)0x7b38, (q15_t)0x7b37, (q15_t)0x7b35, + (q15_t)0x7b33, (q15_t)0x7b31, (q15_t)0x7b30, (q15_t)0x7b2e, (q15_t)0x7b2c, (q15_t)0x7b2b, (q15_t)0x7b29, (q15_t)0x7b27, + (q15_t)0x7b25, (q15_t)0x7b24, (q15_t)0x7b22, (q15_t)0x7b20, (q15_t)0x7b1f, (q15_t)0x7b1d, (q15_t)0x7b1b, (q15_t)0x7b19, + (q15_t)0x7b18, (q15_t)0x7b16, (q15_t)0x7b14, (q15_t)0x7b13, (q15_t)0x7b11, (q15_t)0x7b0f, (q15_t)0x7b0d, (q15_t)0x7b0c, + (q15_t)0x7b0a, (q15_t)0x7b08, (q15_t)0x7b06, (q15_t)0x7b05, (q15_t)0x7b03, (q15_t)0x7b01, (q15_t)0x7aff, (q15_t)0x7afe, + (q15_t)0x7afc, (q15_t)0x7afa, (q15_t)0x7af8, (q15_t)0x7af7, (q15_t)0x7af5, (q15_t)0x7af3, (q15_t)0x7af2, (q15_t)0x7af0, + (q15_t)0x7aee, (q15_t)0x7aec, (q15_t)0x7aeb, (q15_t)0x7ae9, (q15_t)0x7ae7, (q15_t)0x7ae5, (q15_t)0x7ae3, (q15_t)0x7ae2, + (q15_t)0x7ae0, (q15_t)0x7ade, (q15_t)0x7adc, (q15_t)0x7adb, (q15_t)0x7ad9, (q15_t)0x7ad7, (q15_t)0x7ad5, (q15_t)0x7ad4, + (q15_t)0x7ad2, (q15_t)0x7ad0, (q15_t)0x7ace, (q15_t)0x7acd, (q15_t)0x7acb, (q15_t)0x7ac9, (q15_t)0x7ac7, (q15_t)0x7ac5, + (q15_t)0x7ac4, (q15_t)0x7ac2, (q15_t)0x7ac0, (q15_t)0x7abe, (q15_t)0x7abd, (q15_t)0x7abb, (q15_t)0x7ab9, (q15_t)0x7ab7, + (q15_t)0x7ab5, (q15_t)0x7ab4, (q15_t)0x7ab2, (q15_t)0x7ab0, (q15_t)0x7aae, (q15_t)0x7aac, (q15_t)0x7aab, (q15_t)0x7aa9, + (q15_t)0x7aa7, (q15_t)0x7aa5, (q15_t)0x7aa3, (q15_t)0x7aa2, (q15_t)0x7aa0, (q15_t)0x7a9e, (q15_t)0x7a9c, (q15_t)0x7a9a, + (q15_t)0x7a99, (q15_t)0x7a97, (q15_t)0x7a95, (q15_t)0x7a93, (q15_t)0x7a91, (q15_t)0x7a90, (q15_t)0x7a8e, (q15_t)0x7a8c, + (q15_t)0x7a8a, (q15_t)0x7a88, (q15_t)0x7a87, (q15_t)0x7a85, (q15_t)0x7a83, (q15_t)0x7a81, (q15_t)0x7a7f, (q15_t)0x7a7d, + (q15_t)0x7a7c, (q15_t)0x7a7a, (q15_t)0x7a78, (q15_t)0x7a76, (q15_t)0x7a74, (q15_t)0x7a72, (q15_t)0x7a71, (q15_t)0x7a6f, + (q15_t)0x7a6d, (q15_t)0x7a6b, (q15_t)0x7a69, (q15_t)0x7a67, (q15_t)0x7a66, (q15_t)0x7a64, (q15_t)0x7a62, (q15_t)0x7a60, + (q15_t)0x7a5e, (q15_t)0x7a5c, (q15_t)0x7a5b, (q15_t)0x7a59, (q15_t)0x7a57, (q15_t)0x7a55, (q15_t)0x7a53, (q15_t)0x7a51, + (q15_t)0x7a4f, (q15_t)0x7a4e, (q15_t)0x7a4c, (q15_t)0x7a4a, (q15_t)0x7a48, (q15_t)0x7a46, (q15_t)0x7a44, (q15_t)0x7a42, + (q15_t)0x7a41, (q15_t)0x7a3f, (q15_t)0x7a3d, (q15_t)0x7a3b, (q15_t)0x7a39, (q15_t)0x7a37, (q15_t)0x7a35, (q15_t)0x7a34, + (q15_t)0x7a32, (q15_t)0x7a30, (q15_t)0x7a2e, (q15_t)0x7a2c, (q15_t)0x7a2a, (q15_t)0x7a28, (q15_t)0x7a26, (q15_t)0x7a25, + (q15_t)0x7a23, (q15_t)0x7a21, (q15_t)0x7a1f, (q15_t)0x7a1d, (q15_t)0x7a1b, (q15_t)0x7a19, (q15_t)0x7a17, (q15_t)0x7a16, + (q15_t)0x7a14, (q15_t)0x7a12, (q15_t)0x7a10, (q15_t)0x7a0e, (q15_t)0x7a0c, (q15_t)0x7a0a, (q15_t)0x7a08, (q15_t)0x7a06, + (q15_t)0x7a04, (q15_t)0x7a03, (q15_t)0x7a01, (q15_t)0x79ff, (q15_t)0x79fd, (q15_t)0x79fb, (q15_t)0x79f9, (q15_t)0x79f7, + (q15_t)0x79f5, (q15_t)0x79f3, (q15_t)0x79f1, (q15_t)0x79f0, (q15_t)0x79ee, (q15_t)0x79ec, (q15_t)0x79ea, (q15_t)0x79e8, + (q15_t)0x79e6, (q15_t)0x79e4, (q15_t)0x79e2, (q15_t)0x79e0, (q15_t)0x79de, (q15_t)0x79dc, (q15_t)0x79da, (q15_t)0x79d9, + (q15_t)0x79d7, (q15_t)0x79d5, (q15_t)0x79d3, (q15_t)0x79d1, (q15_t)0x79cf, (q15_t)0x79cd, (q15_t)0x79cb, (q15_t)0x79c9, + (q15_t)0x79c7, (q15_t)0x79c5, (q15_t)0x79c3, (q15_t)0x79c1, (q15_t)0x79bf, (q15_t)0x79bd, (q15_t)0x79bc, (q15_t)0x79ba, + (q15_t)0x79b8, (q15_t)0x79b6, (q15_t)0x79b4, (q15_t)0x79b2, (q15_t)0x79b0, (q15_t)0x79ae, (q15_t)0x79ac, (q15_t)0x79aa, + (q15_t)0x79a8, (q15_t)0x79a6, (q15_t)0x79a4, (q15_t)0x79a2, (q15_t)0x79a0, (q15_t)0x799e, (q15_t)0x799c, (q15_t)0x799a, + (q15_t)0x7998, (q15_t)0x7996, (q15_t)0x7994, (q15_t)0x7992, (q15_t)0x7991, (q15_t)0x798f, (q15_t)0x798d, (q15_t)0x798b, + (q15_t)0x7989, (q15_t)0x7987, (q15_t)0x7985, (q15_t)0x7983, (q15_t)0x7981, (q15_t)0x797f, (q15_t)0x797d, (q15_t)0x797b, + (q15_t)0x7979, (q15_t)0x7977, (q15_t)0x7975, (q15_t)0x7973, (q15_t)0x7971, (q15_t)0x796f, (q15_t)0x796d, (q15_t)0x796b, + (q15_t)0x7969, (q15_t)0x7967, (q15_t)0x7965, (q15_t)0x7963, (q15_t)0x7961, (q15_t)0x795f, (q15_t)0x795d, (q15_t)0x795b, + (q15_t)0x7959, (q15_t)0x7957, (q15_t)0x7955, (q15_t)0x7953, (q15_t)0x7951, (q15_t)0x794f, (q15_t)0x794d, (q15_t)0x794b, + (q15_t)0x7949, (q15_t)0x7947, (q15_t)0x7945, (q15_t)0x7943, (q15_t)0x7941, (q15_t)0x793f, (q15_t)0x793d, (q15_t)0x793b, + (q15_t)0x7939, (q15_t)0x7937, (q15_t)0x7935, (q15_t)0x7933, (q15_t)0x7931, (q15_t)0x792f, (q15_t)0x792d, (q15_t)0x792b, + (q15_t)0x7929, (q15_t)0x7927, (q15_t)0x7925, (q15_t)0x7923, (q15_t)0x7921, (q15_t)0x791f, (q15_t)0x791d, (q15_t)0x791a, + (q15_t)0x7918, (q15_t)0x7916, (q15_t)0x7914, (q15_t)0x7912, (q15_t)0x7910, (q15_t)0x790e, (q15_t)0x790c, (q15_t)0x790a, + (q15_t)0x7908, (q15_t)0x7906, (q15_t)0x7904, (q15_t)0x7902, (q15_t)0x7900, (q15_t)0x78fe, (q15_t)0x78fc, (q15_t)0x78fa, + (q15_t)0x78f8, (q15_t)0x78f6, (q15_t)0x78f4, (q15_t)0x78f2, (q15_t)0x78f0, (q15_t)0x78ed, (q15_t)0x78eb, (q15_t)0x78e9, + (q15_t)0x78e7, (q15_t)0x78e5, (q15_t)0x78e3, (q15_t)0x78e1, (q15_t)0x78df, (q15_t)0x78dd, (q15_t)0x78db, (q15_t)0x78d9, + (q15_t)0x78d7, (q15_t)0x78d5, (q15_t)0x78d3, (q15_t)0x78d1, (q15_t)0x78ce, (q15_t)0x78cc, (q15_t)0x78ca, (q15_t)0x78c8, + (q15_t)0x78c6, (q15_t)0x78c4, (q15_t)0x78c2, (q15_t)0x78c0, (q15_t)0x78be, (q15_t)0x78bc, (q15_t)0x78ba, (q15_t)0x78b8, + (q15_t)0x78b5, (q15_t)0x78b3, (q15_t)0x78b1, (q15_t)0x78af, (q15_t)0x78ad, (q15_t)0x78ab, (q15_t)0x78a9, (q15_t)0x78a7, + (q15_t)0x78a5, (q15_t)0x78a3, (q15_t)0x78a0, (q15_t)0x789e, (q15_t)0x789c, (q15_t)0x789a, (q15_t)0x7898, (q15_t)0x7896, + (q15_t)0x7894, (q15_t)0x7892, (q15_t)0x7890, (q15_t)0x788e, (q15_t)0x788b, (q15_t)0x7889, (q15_t)0x7887, (q15_t)0x7885, + (q15_t)0x7883, (q15_t)0x7881, (q15_t)0x787f, (q15_t)0x787d, (q15_t)0x787a, (q15_t)0x7878, (q15_t)0x7876, (q15_t)0x7874, + (q15_t)0x7872, (q15_t)0x7870, (q15_t)0x786e, (q15_t)0x786c, (q15_t)0x7869, (q15_t)0x7867, (q15_t)0x7865, (q15_t)0x7863, + (q15_t)0x7861, (q15_t)0x785f, (q15_t)0x785d, (q15_t)0x785b, (q15_t)0x7858, (q15_t)0x7856, (q15_t)0x7854, (q15_t)0x7852, + (q15_t)0x7850, (q15_t)0x784e, (q15_t)0x784c, (q15_t)0x7849, (q15_t)0x7847, (q15_t)0x7845, (q15_t)0x7843, (q15_t)0x7841, + (q15_t)0x783f, (q15_t)0x783c, (q15_t)0x783a, (q15_t)0x7838, (q15_t)0x7836, (q15_t)0x7834, (q15_t)0x7832, (q15_t)0x7830, + (q15_t)0x782d, (q15_t)0x782b, (q15_t)0x7829, (q15_t)0x7827, (q15_t)0x7825, (q15_t)0x7823, (q15_t)0x7820, (q15_t)0x781e, + (q15_t)0x781c, (q15_t)0x781a, (q15_t)0x7818, (q15_t)0x7816, (q15_t)0x7813, (q15_t)0x7811, (q15_t)0x780f, (q15_t)0x780d, + (q15_t)0x780b, (q15_t)0x7808, (q15_t)0x7806, (q15_t)0x7804, (q15_t)0x7802, (q15_t)0x7800, (q15_t)0x77fe, (q15_t)0x77fb, + (q15_t)0x77f9, (q15_t)0x77f7, (q15_t)0x77f5, (q15_t)0x77f3, (q15_t)0x77f0, (q15_t)0x77ee, (q15_t)0x77ec, (q15_t)0x77ea, + (q15_t)0x77e8, (q15_t)0x77e5, (q15_t)0x77e3, (q15_t)0x77e1, (q15_t)0x77df, (q15_t)0x77dd, (q15_t)0x77da, (q15_t)0x77d8, + (q15_t)0x77d6, (q15_t)0x77d4, (q15_t)0x77d2, (q15_t)0x77cf, (q15_t)0x77cd, (q15_t)0x77cb, (q15_t)0x77c9, (q15_t)0x77c6, + (q15_t)0x77c4, (q15_t)0x77c2, (q15_t)0x77c0, (q15_t)0x77be, (q15_t)0x77bb, (q15_t)0x77b9, (q15_t)0x77b7, (q15_t)0x77b5, + (q15_t)0x77b2, (q15_t)0x77b0, (q15_t)0x77ae, (q15_t)0x77ac, (q15_t)0x77aa, (q15_t)0x77a7, (q15_t)0x77a5, (q15_t)0x77a3, + (q15_t)0x77a1, (q15_t)0x779e, (q15_t)0x779c, (q15_t)0x779a, (q15_t)0x7798, (q15_t)0x7795, (q15_t)0x7793, (q15_t)0x7791, + (q15_t)0x778f, (q15_t)0x778c, (q15_t)0x778a, (q15_t)0x7788, (q15_t)0x7786, (q15_t)0x7783, (q15_t)0x7781, (q15_t)0x777f, + (q15_t)0x777d, (q15_t)0x777a, (q15_t)0x7778, (q15_t)0x7776, (q15_t)0x7774, (q15_t)0x7771, (q15_t)0x776f, (q15_t)0x776d, + (q15_t)0x776b, (q15_t)0x7768, (q15_t)0x7766, (q15_t)0x7764, (q15_t)0x7762, (q15_t)0x775f, (q15_t)0x775d, (q15_t)0x775b, + (q15_t)0x7759, (q15_t)0x7756, (q15_t)0x7754, (q15_t)0x7752, (q15_t)0x774f, (q15_t)0x774d, (q15_t)0x774b, (q15_t)0x7749, + (q15_t)0x7746, (q15_t)0x7744, (q15_t)0x7742, (q15_t)0x773f, (q15_t)0x773d, (q15_t)0x773b, (q15_t)0x7739, (q15_t)0x7736, + (q15_t)0x7734, (q15_t)0x7732, (q15_t)0x772f, (q15_t)0x772d, (q15_t)0x772b, (q15_t)0x7729, (q15_t)0x7726, (q15_t)0x7724, + (q15_t)0x7722, (q15_t)0x771f, (q15_t)0x771d, (q15_t)0x771b, (q15_t)0x7719, (q15_t)0x7716, (q15_t)0x7714, (q15_t)0x7712, + (q15_t)0x770f, (q15_t)0x770d, (q15_t)0x770b, (q15_t)0x7708, (q15_t)0x7706, (q15_t)0x7704, (q15_t)0x7701, (q15_t)0x76ff, + (q15_t)0x76fd, (q15_t)0x76fa, (q15_t)0x76f8, (q15_t)0x76f6, (q15_t)0x76f4, (q15_t)0x76f1, (q15_t)0x76ef, (q15_t)0x76ed, + (q15_t)0x76ea, (q15_t)0x76e8, (q15_t)0x76e6, (q15_t)0x76e3, (q15_t)0x76e1, (q15_t)0x76df, (q15_t)0x76dc, (q15_t)0x76da, + (q15_t)0x76d8, (q15_t)0x76d5, (q15_t)0x76d3, (q15_t)0x76d1, (q15_t)0x76ce, (q15_t)0x76cc, (q15_t)0x76ca, (q15_t)0x76c7, + (q15_t)0x76c5, (q15_t)0x76c3, (q15_t)0x76c0, (q15_t)0x76be, (q15_t)0x76bc, (q15_t)0x76b9, (q15_t)0x76b7, (q15_t)0x76b4, + (q15_t)0x76b2, (q15_t)0x76b0, (q15_t)0x76ad, (q15_t)0x76ab, (q15_t)0x76a9, (q15_t)0x76a6, (q15_t)0x76a4, (q15_t)0x76a2, + (q15_t)0x769f, (q15_t)0x769d, (q15_t)0x769b, (q15_t)0x7698, (q15_t)0x7696, (q15_t)0x7693, (q15_t)0x7691, (q15_t)0x768f, + (q15_t)0x768c, (q15_t)0x768a, (q15_t)0x7688, (q15_t)0x7685, (q15_t)0x7683, (q15_t)0x7681, (q15_t)0x767e, (q15_t)0x767c, + (q15_t)0x7679, (q15_t)0x7677, (q15_t)0x7675, (q15_t)0x7672, (q15_t)0x7670, (q15_t)0x766d, (q15_t)0x766b, (q15_t)0x7669, + (q15_t)0x7666, (q15_t)0x7664, (q15_t)0x7662, (q15_t)0x765f, (q15_t)0x765d, (q15_t)0x765a, (q15_t)0x7658, (q15_t)0x7656, + (q15_t)0x7653, (q15_t)0x7651, (q15_t)0x764e, (q15_t)0x764c, (q15_t)0x764a, (q15_t)0x7647, (q15_t)0x7645, (q15_t)0x7642, + (q15_t)0x7640, (q15_t)0x763e, (q15_t)0x763b, (q15_t)0x7639, (q15_t)0x7636, (q15_t)0x7634, (q15_t)0x7632, (q15_t)0x762f, + (q15_t)0x762d, (q15_t)0x762a, (q15_t)0x7628, (q15_t)0x7625, (q15_t)0x7623, (q15_t)0x7621, (q15_t)0x761e, (q15_t)0x761c, + (q15_t)0x7619, (q15_t)0x7617, (q15_t)0x7615, (q15_t)0x7612, (q15_t)0x7610, (q15_t)0x760d, (q15_t)0x760b, (q15_t)0x7608, + (q15_t)0x7606, (q15_t)0x7604, (q15_t)0x7601, (q15_t)0x75ff, (q15_t)0x75fc, (q15_t)0x75fa, (q15_t)0x75f7, (q15_t)0x75f5, + (q15_t)0x75f2, (q15_t)0x75f0, (q15_t)0x75ee, (q15_t)0x75eb, (q15_t)0x75e9, (q15_t)0x75e6, (q15_t)0x75e4, (q15_t)0x75e1, + (q15_t)0x75df, (q15_t)0x75dc, (q15_t)0x75da, (q15_t)0x75d8, (q15_t)0x75d5, (q15_t)0x75d3, (q15_t)0x75d0, (q15_t)0x75ce, + (q15_t)0x75cb, (q15_t)0x75c9, (q15_t)0x75c6, (q15_t)0x75c4, (q15_t)0x75c1, (q15_t)0x75bf, (q15_t)0x75bc, (q15_t)0x75ba, + (q15_t)0x75b8, (q15_t)0x75b5, (q15_t)0x75b3, (q15_t)0x75b0, (q15_t)0x75ae, (q15_t)0x75ab, (q15_t)0x75a9, (q15_t)0x75a6, + (q15_t)0x75a4, (q15_t)0x75a1, (q15_t)0x759f, (q15_t)0x759c, (q15_t)0x759a, (q15_t)0x7597, (q15_t)0x7595, (q15_t)0x7592, + (q15_t)0x7590, (q15_t)0x758d, (q15_t)0x758b, (q15_t)0x7588, (q15_t)0x7586, (q15_t)0x7584, (q15_t)0x7581, (q15_t)0x757f, + (q15_t)0x757c, (q15_t)0x757a, (q15_t)0x7577, (q15_t)0x7575, (q15_t)0x7572, (q15_t)0x7570, (q15_t)0x756d, (q15_t)0x756b, + (q15_t)0x7568, (q15_t)0x7566, (q15_t)0x7563, (q15_t)0x7561, (q15_t)0x755e, (q15_t)0x755c, (q15_t)0x7559, (q15_t)0x7556, + (q15_t)0x7554, (q15_t)0x7551, (q15_t)0x754f, (q15_t)0x754c, (q15_t)0x754a, (q15_t)0x7547, (q15_t)0x7545, (q15_t)0x7542, + (q15_t)0x7540, (q15_t)0x753d, (q15_t)0x753b, (q15_t)0x7538, (q15_t)0x7536, (q15_t)0x7533, (q15_t)0x7531, (q15_t)0x752e, + (q15_t)0x752c, (q15_t)0x7529, (q15_t)0x7527, (q15_t)0x7524, (q15_t)0x7522, (q15_t)0x751f, (q15_t)0x751c, (q15_t)0x751a, + (q15_t)0x7517, (q15_t)0x7515, (q15_t)0x7512, (q15_t)0x7510, (q15_t)0x750d, (q15_t)0x750b, (q15_t)0x7508, (q15_t)0x7506, + (q15_t)0x7503, (q15_t)0x7501, (q15_t)0x74fe, (q15_t)0x74fb, (q15_t)0x74f9, (q15_t)0x74f6, (q15_t)0x74f4, (q15_t)0x74f1, + (q15_t)0x74ef, (q15_t)0x74ec, (q15_t)0x74ea, (q15_t)0x74e7, (q15_t)0x74e4, (q15_t)0x74e2, (q15_t)0x74df, (q15_t)0x74dd, + (q15_t)0x74da, (q15_t)0x74d8, (q15_t)0x74d5, (q15_t)0x74d2, (q15_t)0x74d0, (q15_t)0x74cd, (q15_t)0x74cb, (q15_t)0x74c8, + (q15_t)0x74c6, (q15_t)0x74c3, (q15_t)0x74c0, (q15_t)0x74be, (q15_t)0x74bb, (q15_t)0x74b9, (q15_t)0x74b6, (q15_t)0x74b4, + (q15_t)0x74b1, (q15_t)0x74ae, (q15_t)0x74ac, (q15_t)0x74a9, (q15_t)0x74a7, (q15_t)0x74a4, (q15_t)0x74a1, (q15_t)0x749f, + (q15_t)0x749c, (q15_t)0x749a, (q15_t)0x7497, (q15_t)0x7495, (q15_t)0x7492, (q15_t)0x748f, (q15_t)0x748d, (q15_t)0x748a, + (q15_t)0x7488, (q15_t)0x7485, (q15_t)0x7482, (q15_t)0x7480, (q15_t)0x747d, (q15_t)0x747b, (q15_t)0x7478, (q15_t)0x7475, + (q15_t)0x7473, (q15_t)0x7470, (q15_t)0x746d, (q15_t)0x746b, (q15_t)0x7468, (q15_t)0x7466, (q15_t)0x7463, (q15_t)0x7460, + (q15_t)0x745e, (q15_t)0x745b, (q15_t)0x7459, (q15_t)0x7456, (q15_t)0x7453, (q15_t)0x7451, (q15_t)0x744e, (q15_t)0x744b, + (q15_t)0x7449, (q15_t)0x7446, (q15_t)0x7444, (q15_t)0x7441, (q15_t)0x743e, (q15_t)0x743c, (q15_t)0x7439, (q15_t)0x7436, + (q15_t)0x7434, (q15_t)0x7431, (q15_t)0x742f, (q15_t)0x742c, (q15_t)0x7429, (q15_t)0x7427, (q15_t)0x7424, (q15_t)0x7421, + (q15_t)0x741f, (q15_t)0x741c, (q15_t)0x7419, (q15_t)0x7417, (q15_t)0x7414, (q15_t)0x7411, (q15_t)0x740f, (q15_t)0x740c, + (q15_t)0x740a, (q15_t)0x7407, (q15_t)0x7404, (q15_t)0x7402, (q15_t)0x73ff, (q15_t)0x73fc, (q15_t)0x73fa, (q15_t)0x73f7, + (q15_t)0x73f4, (q15_t)0x73f2, (q15_t)0x73ef, (q15_t)0x73ec, (q15_t)0x73ea, (q15_t)0x73e7, (q15_t)0x73e4, (q15_t)0x73e2, + (q15_t)0x73df, (q15_t)0x73dc, (q15_t)0x73da, (q15_t)0x73d7, (q15_t)0x73d4, (q15_t)0x73d2, (q15_t)0x73cf, (q15_t)0x73cc, + (q15_t)0x73ca, (q15_t)0x73c7, (q15_t)0x73c4, (q15_t)0x73c1, (q15_t)0x73bf, (q15_t)0x73bc, (q15_t)0x73b9, (q15_t)0x73b7, + (q15_t)0x73b4, (q15_t)0x73b1, (q15_t)0x73af, (q15_t)0x73ac, (q15_t)0x73a9, (q15_t)0x73a7, (q15_t)0x73a4, (q15_t)0x73a1, + (q15_t)0x739f, (q15_t)0x739c, (q15_t)0x7399, (q15_t)0x7396, (q15_t)0x7394, (q15_t)0x7391, (q15_t)0x738e, (q15_t)0x738c, + (q15_t)0x7389, (q15_t)0x7386, (q15_t)0x7384, (q15_t)0x7381, (q15_t)0x737e, (q15_t)0x737b, (q15_t)0x7379, (q15_t)0x7376, + (q15_t)0x7373, (q15_t)0x7371, (q15_t)0x736e, (q15_t)0x736b, (q15_t)0x7368, (q15_t)0x7366, (q15_t)0x7363, (q15_t)0x7360, + (q15_t)0x735e, (q15_t)0x735b, (q15_t)0x7358, (q15_t)0x7355, (q15_t)0x7353, (q15_t)0x7350, (q15_t)0x734d, (q15_t)0x734a, + (q15_t)0x7348, (q15_t)0x7345, (q15_t)0x7342, (q15_t)0x7340, (q15_t)0x733d, (q15_t)0x733a, (q15_t)0x7337, (q15_t)0x7335, + (q15_t)0x7332, (q15_t)0x732f, (q15_t)0x732c, (q15_t)0x732a, (q15_t)0x7327, (q15_t)0x7324, (q15_t)0x7321, (q15_t)0x731f, + (q15_t)0x731c, (q15_t)0x7319, (q15_t)0x7316, (q15_t)0x7314, (q15_t)0x7311, (q15_t)0x730e, (q15_t)0x730b, (q15_t)0x7309, + (q15_t)0x7306, (q15_t)0x7303, (q15_t)0x7300, (q15_t)0x72fe, (q15_t)0x72fb, (q15_t)0x72f8, (q15_t)0x72f5, (q15_t)0x72f3, + (q15_t)0x72f0, (q15_t)0x72ed, (q15_t)0x72ea, (q15_t)0x72e8, (q15_t)0x72e5, (q15_t)0x72e2, (q15_t)0x72df, (q15_t)0x72dc, + (q15_t)0x72da, (q15_t)0x72d7, (q15_t)0x72d4, (q15_t)0x72d1, (q15_t)0x72cf, (q15_t)0x72cc, (q15_t)0x72c9, (q15_t)0x72c6, + (q15_t)0x72c3, (q15_t)0x72c1, (q15_t)0x72be, (q15_t)0x72bb, (q15_t)0x72b8, (q15_t)0x72b5, (q15_t)0x72b3, (q15_t)0x72b0, + (q15_t)0x72ad, (q15_t)0x72aa, (q15_t)0x72a8, (q15_t)0x72a5, (q15_t)0x72a2, (q15_t)0x729f, (q15_t)0x729c, (q15_t)0x729a, + (q15_t)0x7297, (q15_t)0x7294, (q15_t)0x7291, (q15_t)0x728e, (q15_t)0x728c, (q15_t)0x7289, (q15_t)0x7286, (q15_t)0x7283, + (q15_t)0x7280, (q15_t)0x727e, (q15_t)0x727b, (q15_t)0x7278, (q15_t)0x7275, (q15_t)0x7272, (q15_t)0x726f, (q15_t)0x726d, + (q15_t)0x726a, (q15_t)0x7267, (q15_t)0x7264, (q15_t)0x7261, (q15_t)0x725f, (q15_t)0x725c, (q15_t)0x7259, (q15_t)0x7256, + (q15_t)0x7253, (q15_t)0x7250, (q15_t)0x724e, (q15_t)0x724b, (q15_t)0x7248, (q15_t)0x7245, (q15_t)0x7242, (q15_t)0x723f, + (q15_t)0x723d, (q15_t)0x723a, (q15_t)0x7237, (q15_t)0x7234, (q15_t)0x7231, (q15_t)0x722e, (q15_t)0x722c, (q15_t)0x7229, + (q15_t)0x7226, (q15_t)0x7223, (q15_t)0x7220, (q15_t)0x721d, (q15_t)0x721b, (q15_t)0x7218, (q15_t)0x7215, (q15_t)0x7212, + (q15_t)0x720f, (q15_t)0x720c, (q15_t)0x7209, (q15_t)0x7207, (q15_t)0x7204, (q15_t)0x7201, (q15_t)0x71fe, (q15_t)0x71fb, + (q15_t)0x71f8, (q15_t)0x71f5, (q15_t)0x71f3, (q15_t)0x71f0, (q15_t)0x71ed, (q15_t)0x71ea, (q15_t)0x71e7, (q15_t)0x71e4, + (q15_t)0x71e1, (q15_t)0x71df, (q15_t)0x71dc, (q15_t)0x71d9, (q15_t)0x71d6, (q15_t)0x71d3, (q15_t)0x71d0, (q15_t)0x71cd, + (q15_t)0x71ca, (q15_t)0x71c8, (q15_t)0x71c5, (q15_t)0x71c2, (q15_t)0x71bf, (q15_t)0x71bc, (q15_t)0x71b9, (q15_t)0x71b6, + (q15_t)0x71b3, (q15_t)0x71b0, (q15_t)0x71ae, (q15_t)0x71ab, (q15_t)0x71a8, (q15_t)0x71a5, (q15_t)0x71a2, (q15_t)0x719f, + (q15_t)0x719c, (q15_t)0x7199, (q15_t)0x7196, (q15_t)0x7194, (q15_t)0x7191, (q15_t)0x718e, (q15_t)0x718b, (q15_t)0x7188, + (q15_t)0x7185, (q15_t)0x7182, (q15_t)0x717f, (q15_t)0x717c, (q15_t)0x7179, (q15_t)0x7177, (q15_t)0x7174, (q15_t)0x7171, + (q15_t)0x716e, (q15_t)0x716b, (q15_t)0x7168, (q15_t)0x7165, (q15_t)0x7162, (q15_t)0x715f, (q15_t)0x715c, (q15_t)0x7159, + (q15_t)0x7156, (q15_t)0x7154, (q15_t)0x7151, (q15_t)0x714e, (q15_t)0x714b, (q15_t)0x7148, (q15_t)0x7145, (q15_t)0x7142, + (q15_t)0x713f, (q15_t)0x713c, (q15_t)0x7139, (q15_t)0x7136, (q15_t)0x7133, (q15_t)0x7130, (q15_t)0x712d, (q15_t)0x712b, + (q15_t)0x7128, (q15_t)0x7125, (q15_t)0x7122, (q15_t)0x711f, (q15_t)0x711c, (q15_t)0x7119, (q15_t)0x7116, (q15_t)0x7113, + (q15_t)0x7110, (q15_t)0x710d, (q15_t)0x710a, (q15_t)0x7107, (q15_t)0x7104, (q15_t)0x7101, (q15_t)0x70fe, (q15_t)0x70fb, + (q15_t)0x70f8, (q15_t)0x70f6, (q15_t)0x70f3, (q15_t)0x70f0, (q15_t)0x70ed, (q15_t)0x70ea, (q15_t)0x70e7, (q15_t)0x70e4, + (q15_t)0x70e1, (q15_t)0x70de, (q15_t)0x70db, (q15_t)0x70d8, (q15_t)0x70d5, (q15_t)0x70d2, (q15_t)0x70cf, (q15_t)0x70cc, + (q15_t)0x70c9, (q15_t)0x70c6, (q15_t)0x70c3, (q15_t)0x70c0, (q15_t)0x70bd, (q15_t)0x70ba, (q15_t)0x70b7, (q15_t)0x70b4, + (q15_t)0x70b1, (q15_t)0x70ae, (q15_t)0x70ab, (q15_t)0x70a8, (q15_t)0x70a5, (q15_t)0x70a2, (q15_t)0x709f, (q15_t)0x709c, + (q15_t)0x7099, (q15_t)0x7096, (q15_t)0x7093, (q15_t)0x7090, (q15_t)0x708d, (q15_t)0x708a, (q15_t)0x7087, (q15_t)0x7084, + (q15_t)0x7081, (q15_t)0x707e, (q15_t)0x707b, (q15_t)0x7078, (q15_t)0x7075, (q15_t)0x7072, (q15_t)0x706f, (q15_t)0x706c, + (q15_t)0x7069, (q15_t)0x7066, (q15_t)0x7063, (q15_t)0x7060, (q15_t)0x705d, (q15_t)0x705a, (q15_t)0x7057, (q15_t)0x7054, + (q15_t)0x7051, (q15_t)0x704e, (q15_t)0x704b, (q15_t)0x7048, (q15_t)0x7045, (q15_t)0x7042, (q15_t)0x703f, (q15_t)0x703c, + (q15_t)0x7039, (q15_t)0x7036, (q15_t)0x7033, (q15_t)0x7030, (q15_t)0x702d, (q15_t)0x702a, (q15_t)0x7027, (q15_t)0x7024, + (q15_t)0x7021, (q15_t)0x701e, (q15_t)0x701b, (q15_t)0x7018, (q15_t)0x7015, (q15_t)0x7012, (q15_t)0x700f, (q15_t)0x700c, + (q15_t)0x7009, (q15_t)0x7006, (q15_t)0x7003, (q15_t)0x7000, (q15_t)0x6ffd, (q15_t)0x6ffa, (q15_t)0x6ff7, (q15_t)0x6ff3, + (q15_t)0x6ff0, (q15_t)0x6fed, (q15_t)0x6fea, (q15_t)0x6fe7, (q15_t)0x6fe4, (q15_t)0x6fe1, (q15_t)0x6fde, (q15_t)0x6fdb, + (q15_t)0x6fd8, (q15_t)0x6fd5, (q15_t)0x6fd2, (q15_t)0x6fcf, (q15_t)0x6fcc, (q15_t)0x6fc9, (q15_t)0x6fc6, (q15_t)0x6fc3, + (q15_t)0x6fc0, (q15_t)0x6fbc, (q15_t)0x6fb9, (q15_t)0x6fb6, (q15_t)0x6fb3, (q15_t)0x6fb0, (q15_t)0x6fad, (q15_t)0x6faa, + (q15_t)0x6fa7, (q15_t)0x6fa4, (q15_t)0x6fa1, (q15_t)0x6f9e, (q15_t)0x6f9b, (q15_t)0x6f98, (q15_t)0x6f95, (q15_t)0x6f91, + (q15_t)0x6f8e, (q15_t)0x6f8b, (q15_t)0x6f88, (q15_t)0x6f85, (q15_t)0x6f82, (q15_t)0x6f7f, (q15_t)0x6f7c, (q15_t)0x6f79, + (q15_t)0x6f76, (q15_t)0x6f73, (q15_t)0x6f70, (q15_t)0x6f6c, (q15_t)0x6f69, (q15_t)0x6f66, (q15_t)0x6f63, (q15_t)0x6f60, + (q15_t)0x6f5d, (q15_t)0x6f5a, (q15_t)0x6f57, (q15_t)0x6f54, (q15_t)0x6f51, (q15_t)0x6f4d, (q15_t)0x6f4a, (q15_t)0x6f47, + (q15_t)0x6f44, (q15_t)0x6f41, (q15_t)0x6f3e, (q15_t)0x6f3b, (q15_t)0x6f38, (q15_t)0x6f35, (q15_t)0x6f31, (q15_t)0x6f2e, + (q15_t)0x6f2b, (q15_t)0x6f28, (q15_t)0x6f25, (q15_t)0x6f22, (q15_t)0x6f1f, (q15_t)0x6f1c, (q15_t)0x6f19, (q15_t)0x6f15, + (q15_t)0x6f12, (q15_t)0x6f0f, (q15_t)0x6f0c, (q15_t)0x6f09, (q15_t)0x6f06, (q15_t)0x6f03, (q15_t)0x6f00, (q15_t)0x6efc, + (q15_t)0x6ef9, (q15_t)0x6ef6, (q15_t)0x6ef3, (q15_t)0x6ef0, (q15_t)0x6eed, (q15_t)0x6eea, (q15_t)0x6ee7, (q15_t)0x6ee3, + (q15_t)0x6ee0, (q15_t)0x6edd, (q15_t)0x6eda, (q15_t)0x6ed7, (q15_t)0x6ed4, (q15_t)0x6ed1, (q15_t)0x6ecd, (q15_t)0x6eca, + (q15_t)0x6ec7, (q15_t)0x6ec4, (q15_t)0x6ec1, (q15_t)0x6ebe, (q15_t)0x6eba, (q15_t)0x6eb7, (q15_t)0x6eb4, (q15_t)0x6eb1, + (q15_t)0x6eae, (q15_t)0x6eab, (q15_t)0x6ea8, (q15_t)0x6ea4, (q15_t)0x6ea1, (q15_t)0x6e9e, (q15_t)0x6e9b, (q15_t)0x6e98, + (q15_t)0x6e95, (q15_t)0x6e91, (q15_t)0x6e8e, (q15_t)0x6e8b, (q15_t)0x6e88, (q15_t)0x6e85, (q15_t)0x6e82, (q15_t)0x6e7e, + (q15_t)0x6e7b, (q15_t)0x6e78, (q15_t)0x6e75, (q15_t)0x6e72, (q15_t)0x6e6f, (q15_t)0x6e6b, (q15_t)0x6e68, (q15_t)0x6e65, + (q15_t)0x6e62, (q15_t)0x6e5f, (q15_t)0x6e5b, (q15_t)0x6e58, (q15_t)0x6e55, (q15_t)0x6e52, (q15_t)0x6e4f, (q15_t)0x6e4c, + (q15_t)0x6e48, (q15_t)0x6e45, (q15_t)0x6e42, (q15_t)0x6e3f, (q15_t)0x6e3c, (q15_t)0x6e38, (q15_t)0x6e35, (q15_t)0x6e32, + (q15_t)0x6e2f, (q15_t)0x6e2c, (q15_t)0x6e28, (q15_t)0x6e25, (q15_t)0x6e22, (q15_t)0x6e1f, (q15_t)0x6e1c, (q15_t)0x6e18, + (q15_t)0x6e15, (q15_t)0x6e12, (q15_t)0x6e0f, (q15_t)0x6e0c, (q15_t)0x6e08, (q15_t)0x6e05, (q15_t)0x6e02, (q15_t)0x6dff, + (q15_t)0x6dfb, (q15_t)0x6df8, (q15_t)0x6df5, (q15_t)0x6df2, (q15_t)0x6def, (q15_t)0x6deb, (q15_t)0x6de8, (q15_t)0x6de5, + (q15_t)0x6de2, (q15_t)0x6ddf, (q15_t)0x6ddb, (q15_t)0x6dd8, (q15_t)0x6dd5, (q15_t)0x6dd2, (q15_t)0x6dce, (q15_t)0x6dcb, + (q15_t)0x6dc8, (q15_t)0x6dc5, (q15_t)0x6dc1, (q15_t)0x6dbe, (q15_t)0x6dbb, (q15_t)0x6db8, (q15_t)0x6db5, (q15_t)0x6db1, + (q15_t)0x6dae, (q15_t)0x6dab, (q15_t)0x6da8, (q15_t)0x6da4, (q15_t)0x6da1, (q15_t)0x6d9e, (q15_t)0x6d9b, (q15_t)0x6d97, + (q15_t)0x6d94, (q15_t)0x6d91, (q15_t)0x6d8e, (q15_t)0x6d8a, (q15_t)0x6d87, (q15_t)0x6d84, (q15_t)0x6d81, (q15_t)0x6d7d, + (q15_t)0x6d7a, (q15_t)0x6d77, (q15_t)0x6d74, (q15_t)0x6d70, (q15_t)0x6d6d, (q15_t)0x6d6a, (q15_t)0x6d67, (q15_t)0x6d63, + (q15_t)0x6d60, (q15_t)0x6d5d, (q15_t)0x6d59, (q15_t)0x6d56, (q15_t)0x6d53, (q15_t)0x6d50, (q15_t)0x6d4c, (q15_t)0x6d49, + (q15_t)0x6d46, (q15_t)0x6d43, (q15_t)0x6d3f, (q15_t)0x6d3c, (q15_t)0x6d39, (q15_t)0x6d36, (q15_t)0x6d32, (q15_t)0x6d2f, + (q15_t)0x6d2c, (q15_t)0x6d28, (q15_t)0x6d25, (q15_t)0x6d22, (q15_t)0x6d1f, (q15_t)0x6d1b, (q15_t)0x6d18, (q15_t)0x6d15, + (q15_t)0x6d11, (q15_t)0x6d0e, (q15_t)0x6d0b, (q15_t)0x6d08, (q15_t)0x6d04, (q15_t)0x6d01, (q15_t)0x6cfe, (q15_t)0x6cfa, + (q15_t)0x6cf7, (q15_t)0x6cf4, (q15_t)0x6cf0, (q15_t)0x6ced, (q15_t)0x6cea, (q15_t)0x6ce7, (q15_t)0x6ce3, (q15_t)0x6ce0, + (q15_t)0x6cdd, (q15_t)0x6cd9, (q15_t)0x6cd6, (q15_t)0x6cd3, (q15_t)0x6ccf, (q15_t)0x6ccc, (q15_t)0x6cc9, (q15_t)0x6cc5, + (q15_t)0x6cc2, (q15_t)0x6cbf, (q15_t)0x6cbc, (q15_t)0x6cb8, (q15_t)0x6cb5, (q15_t)0x6cb2, (q15_t)0x6cae, (q15_t)0x6cab, + (q15_t)0x6ca8, (q15_t)0x6ca4, (q15_t)0x6ca1, (q15_t)0x6c9e, (q15_t)0x6c9a, (q15_t)0x6c97, (q15_t)0x6c94, (q15_t)0x6c90, + (q15_t)0x6c8d, (q15_t)0x6c8a, (q15_t)0x6c86, (q15_t)0x6c83, (q15_t)0x6c80, (q15_t)0x6c7c, (q15_t)0x6c79, (q15_t)0x6c76, + (q15_t)0x6c72, (q15_t)0x6c6f, (q15_t)0x6c6c, (q15_t)0x6c68, (q15_t)0x6c65, (q15_t)0x6c62, (q15_t)0x6c5e, (q15_t)0x6c5b, + (q15_t)0x6c58, (q15_t)0x6c54, (q15_t)0x6c51, (q15_t)0x6c4e, (q15_t)0x6c4a, (q15_t)0x6c47, (q15_t)0x6c44, (q15_t)0x6c40, + (q15_t)0x6c3d, (q15_t)0x6c39, (q15_t)0x6c36, (q15_t)0x6c33, (q15_t)0x6c2f, (q15_t)0x6c2c, (q15_t)0x6c29, (q15_t)0x6c25, + (q15_t)0x6c22, (q15_t)0x6c1f, (q15_t)0x6c1b, (q15_t)0x6c18, (q15_t)0x6c15, (q15_t)0x6c11, (q15_t)0x6c0e, (q15_t)0x6c0a, + (q15_t)0x6c07, (q15_t)0x6c04, (q15_t)0x6c00, (q15_t)0x6bfd, (q15_t)0x6bfa, (q15_t)0x6bf6, (q15_t)0x6bf3, (q15_t)0x6bef, + (q15_t)0x6bec, (q15_t)0x6be9, (q15_t)0x6be5, (q15_t)0x6be2, (q15_t)0x6bdf, (q15_t)0x6bdb, (q15_t)0x6bd8, (q15_t)0x6bd4, + (q15_t)0x6bd1, (q15_t)0x6bce, (q15_t)0x6bca, (q15_t)0x6bc7, (q15_t)0x6bc3, (q15_t)0x6bc0, (q15_t)0x6bbd, (q15_t)0x6bb9, + (q15_t)0x6bb6, (q15_t)0x6bb2, (q15_t)0x6baf, (q15_t)0x6bac, (q15_t)0x6ba8, (q15_t)0x6ba5, (q15_t)0x6ba1, (q15_t)0x6b9e, + (q15_t)0x6b9b, (q15_t)0x6b97, (q15_t)0x6b94, (q15_t)0x6b90, (q15_t)0x6b8d, (q15_t)0x6b8a, (q15_t)0x6b86, (q15_t)0x6b83, + (q15_t)0x6b7f, (q15_t)0x6b7c, (q15_t)0x6b79, (q15_t)0x6b75, (q15_t)0x6b72, (q15_t)0x6b6e, (q15_t)0x6b6b, (q15_t)0x6b68, + (q15_t)0x6b64, (q15_t)0x6b61, (q15_t)0x6b5d, (q15_t)0x6b5a, (q15_t)0x6b56, (q15_t)0x6b53, (q15_t)0x6b50, (q15_t)0x6b4c, + (q15_t)0x6b49, (q15_t)0x6b45, (q15_t)0x6b42, (q15_t)0x6b3e, (q15_t)0x6b3b, (q15_t)0x6b38, (q15_t)0x6b34, (q15_t)0x6b31, + (q15_t)0x6b2d, (q15_t)0x6b2a, (q15_t)0x6b26, (q15_t)0x6b23, (q15_t)0x6b20, (q15_t)0x6b1c, (q15_t)0x6b19, (q15_t)0x6b15, + (q15_t)0x6b12, (q15_t)0x6b0e, (q15_t)0x6b0b, (q15_t)0x6b07, (q15_t)0x6b04, (q15_t)0x6b01, (q15_t)0x6afd, (q15_t)0x6afa, + (q15_t)0x6af6, (q15_t)0x6af3, (q15_t)0x6aef, (q15_t)0x6aec, (q15_t)0x6ae8, (q15_t)0x6ae5, (q15_t)0x6ae1, (q15_t)0x6ade, + (q15_t)0x6adb, (q15_t)0x6ad7, (q15_t)0x6ad4, (q15_t)0x6ad0, (q15_t)0x6acd, (q15_t)0x6ac9, (q15_t)0x6ac6, (q15_t)0x6ac2, + (q15_t)0x6abf, (q15_t)0x6abb, (q15_t)0x6ab8, (q15_t)0x6ab4, (q15_t)0x6ab1, (q15_t)0x6aae, (q15_t)0x6aaa, (q15_t)0x6aa7, + (q15_t)0x6aa3, (q15_t)0x6aa0, (q15_t)0x6a9c, (q15_t)0x6a99, (q15_t)0x6a95, (q15_t)0x6a92, (q15_t)0x6a8e, (q15_t)0x6a8b, + (q15_t)0x6a87, (q15_t)0x6a84, (q15_t)0x6a80, (q15_t)0x6a7d, (q15_t)0x6a79, (q15_t)0x6a76, (q15_t)0x6a72, (q15_t)0x6a6f, + (q15_t)0x6a6b, (q15_t)0x6a68, (q15_t)0x6a64, (q15_t)0x6a61, (q15_t)0x6a5d, (q15_t)0x6a5a, (q15_t)0x6a56, (q15_t)0x6a53, + (q15_t)0x6a4f, (q15_t)0x6a4c, (q15_t)0x6a48, (q15_t)0x6a45, (q15_t)0x6a41, (q15_t)0x6a3e, (q15_t)0x6a3a, (q15_t)0x6a37, + (q15_t)0x6a33, (q15_t)0x6a30, (q15_t)0x6a2c, (q15_t)0x6a29, (q15_t)0x6a25, (q15_t)0x6a22, (q15_t)0x6a1e, (q15_t)0x6a1b, + (q15_t)0x6a17, (q15_t)0x6a14, (q15_t)0x6a10, (q15_t)0x6a0d, (q15_t)0x6a09, (q15_t)0x6a06, (q15_t)0x6a02, (q15_t)0x69ff, + (q15_t)0x69fb, (q15_t)0x69f8, (q15_t)0x69f4, (q15_t)0x69f1, (q15_t)0x69ed, (q15_t)0x69e9, (q15_t)0x69e6, (q15_t)0x69e2, + (q15_t)0x69df, (q15_t)0x69db, (q15_t)0x69d8, (q15_t)0x69d4, (q15_t)0x69d1, (q15_t)0x69cd, (q15_t)0x69ca, (q15_t)0x69c6, + (q15_t)0x69c3, (q15_t)0x69bf, (q15_t)0x69bc, (q15_t)0x69b8, (q15_t)0x69b4, (q15_t)0x69b1, (q15_t)0x69ad, (q15_t)0x69aa, + (q15_t)0x69a6, (q15_t)0x69a3, (q15_t)0x699f, (q15_t)0x699c, (q15_t)0x6998, (q15_t)0x6995, (q15_t)0x6991, (q15_t)0x698d, + (q15_t)0x698a, (q15_t)0x6986, (q15_t)0x6983, (q15_t)0x697f, (q15_t)0x697c, (q15_t)0x6978, (q15_t)0x6975, (q15_t)0x6971, + (q15_t)0x696d, (q15_t)0x696a, (q15_t)0x6966, (q15_t)0x6963, (q15_t)0x695f, (q15_t)0x695c, (q15_t)0x6958, (q15_t)0x6954, + (q15_t)0x6951, (q15_t)0x694d, (q15_t)0x694a, (q15_t)0x6946, (q15_t)0x6943, (q15_t)0x693f, (q15_t)0x693b, (q15_t)0x6938, + (q15_t)0x6934, (q15_t)0x6931, (q15_t)0x692d, (q15_t)0x692a, (q15_t)0x6926, (q15_t)0x6922, (q15_t)0x691f, (q15_t)0x691b, + (q15_t)0x6918, (q15_t)0x6914, (q15_t)0x6910, (q15_t)0x690d, (q15_t)0x6909, (q15_t)0x6906, (q15_t)0x6902, (q15_t)0x68fe, + (q15_t)0x68fb, (q15_t)0x68f7, (q15_t)0x68f4, (q15_t)0x68f0, (q15_t)0x68ec, (q15_t)0x68e9, (q15_t)0x68e5, (q15_t)0x68e2, + (q15_t)0x68de, (q15_t)0x68da, (q15_t)0x68d7, (q15_t)0x68d3, (q15_t)0x68d0, (q15_t)0x68cc, (q15_t)0x68c8, (q15_t)0x68c5, + (q15_t)0x68c1, (q15_t)0x68be, (q15_t)0x68ba, (q15_t)0x68b6, (q15_t)0x68b3, (q15_t)0x68af, (q15_t)0x68ac, (q15_t)0x68a8, + (q15_t)0x68a4, (q15_t)0x68a1, (q15_t)0x689d, (q15_t)0x6899, (q15_t)0x6896, (q15_t)0x6892, (q15_t)0x688f, (q15_t)0x688b, + (q15_t)0x6887, (q15_t)0x6884, (q15_t)0x6880, (q15_t)0x687c, (q15_t)0x6879, (q15_t)0x6875, (q15_t)0x6872, (q15_t)0x686e, + (q15_t)0x686a, (q15_t)0x6867, (q15_t)0x6863, (q15_t)0x685f, (q15_t)0x685c, (q15_t)0x6858, (q15_t)0x6854, (q15_t)0x6851, + (q15_t)0x684d, (q15_t)0x684a, (q15_t)0x6846, (q15_t)0x6842, (q15_t)0x683f, (q15_t)0x683b, (q15_t)0x6837, (q15_t)0x6834, + (q15_t)0x6830, (q15_t)0x682c, (q15_t)0x6829, (q15_t)0x6825, (q15_t)0x6821, (q15_t)0x681e, (q15_t)0x681a, (q15_t)0x6816, + (q15_t)0x6813, (q15_t)0x680f, (q15_t)0x680b, (q15_t)0x6808, (q15_t)0x6804, (q15_t)0x6800, (q15_t)0x67fd, (q15_t)0x67f9, + (q15_t)0x67f5, (q15_t)0x67f2, (q15_t)0x67ee, (q15_t)0x67ea, (q15_t)0x67e7, (q15_t)0x67e3, (q15_t)0x67df, (q15_t)0x67dc, + (q15_t)0x67d8, (q15_t)0x67d4, (q15_t)0x67d1, (q15_t)0x67cd, (q15_t)0x67c9, (q15_t)0x67c6, (q15_t)0x67c2, (q15_t)0x67be, + (q15_t)0x67bb, (q15_t)0x67b7, (q15_t)0x67b3, (q15_t)0x67b0, (q15_t)0x67ac, (q15_t)0x67a8, (q15_t)0x67a5, (q15_t)0x67a1, + (q15_t)0x679d, (q15_t)0x679a, (q15_t)0x6796, (q15_t)0x6792, (q15_t)0x678e, (q15_t)0x678b, (q15_t)0x6787, (q15_t)0x6783, + (q15_t)0x6780, (q15_t)0x677c, (q15_t)0x6778, (q15_t)0x6775, (q15_t)0x6771, (q15_t)0x676d, (q15_t)0x6769, (q15_t)0x6766, + (q15_t)0x6762, (q15_t)0x675e, (q15_t)0x675b, (q15_t)0x6757, (q15_t)0x6753, (q15_t)0x6750, (q15_t)0x674c, (q15_t)0x6748, + (q15_t)0x6744, (q15_t)0x6741, (q15_t)0x673d, (q15_t)0x6739, (q15_t)0x6736, (q15_t)0x6732, (q15_t)0x672e, (q15_t)0x672a, + (q15_t)0x6727, (q15_t)0x6723, (q15_t)0x671f, (q15_t)0x671c, (q15_t)0x6718, (q15_t)0x6714, (q15_t)0x6710, (q15_t)0x670d, + (q15_t)0x6709, (q15_t)0x6705, (q15_t)0x6701, (q15_t)0x66fe, (q15_t)0x66fa, (q15_t)0x66f6, (q15_t)0x66f3, (q15_t)0x66ef, + (q15_t)0x66eb, (q15_t)0x66e7, (q15_t)0x66e4, (q15_t)0x66e0, (q15_t)0x66dc, (q15_t)0x66d8, (q15_t)0x66d5, (q15_t)0x66d1, + (q15_t)0x66cd, (q15_t)0x66c9, (q15_t)0x66c6, (q15_t)0x66c2, (q15_t)0x66be, (q15_t)0x66ba, (q15_t)0x66b7, (q15_t)0x66b3, + (q15_t)0x66af, (q15_t)0x66ab, (q15_t)0x66a8, (q15_t)0x66a4, (q15_t)0x66a0, (q15_t)0x669c, (q15_t)0x6699, (q15_t)0x6695, + (q15_t)0x6691, (q15_t)0x668d, (q15_t)0x668a, (q15_t)0x6686, (q15_t)0x6682, (q15_t)0x667e, (q15_t)0x667b, (q15_t)0x6677, + (q15_t)0x6673, (q15_t)0x666f, (q15_t)0x666b, (q15_t)0x6668, (q15_t)0x6664, (q15_t)0x6660, (q15_t)0x665c, (q15_t)0x6659, + (q15_t)0x6655, (q15_t)0x6651, (q15_t)0x664d, (q15_t)0x664a, (q15_t)0x6646, (q15_t)0x6642, (q15_t)0x663e, (q15_t)0x663a, + (q15_t)0x6637, (q15_t)0x6633, (q15_t)0x662f, (q15_t)0x662b, (q15_t)0x6627, (q15_t)0x6624, (q15_t)0x6620, (q15_t)0x661c, + (q15_t)0x6618, (q15_t)0x6615, (q15_t)0x6611, (q15_t)0x660d, (q15_t)0x6609, (q15_t)0x6605, (q15_t)0x6602, (q15_t)0x65fe, + (q15_t)0x65fa, (q15_t)0x65f6, (q15_t)0x65f2, (q15_t)0x65ef, (q15_t)0x65eb, (q15_t)0x65e7, (q15_t)0x65e3, (q15_t)0x65df, + (q15_t)0x65dc, (q15_t)0x65d8, (q15_t)0x65d4, (q15_t)0x65d0, (q15_t)0x65cc, (q15_t)0x65c9, (q15_t)0x65c5, (q15_t)0x65c1, + (q15_t)0x65bd, (q15_t)0x65b9, (q15_t)0x65b5, (q15_t)0x65b2, (q15_t)0x65ae, (q15_t)0x65aa, (q15_t)0x65a6, (q15_t)0x65a2, + (q15_t)0x659f, (q15_t)0x659b, (q15_t)0x6597, (q15_t)0x6593, (q15_t)0x658f, (q15_t)0x658b, (q15_t)0x6588, (q15_t)0x6584, + (q15_t)0x6580, (q15_t)0x657c, (q15_t)0x6578, (q15_t)0x6574, (q15_t)0x6571, (q15_t)0x656d, (q15_t)0x6569, (q15_t)0x6565, + (q15_t)0x6561, (q15_t)0x655d, (q15_t)0x655a, (q15_t)0x6556, (q15_t)0x6552, (q15_t)0x654e, (q15_t)0x654a, (q15_t)0x6546, + (q15_t)0x6543, (q15_t)0x653f, (q15_t)0x653b, (q15_t)0x6537, (q15_t)0x6533, (q15_t)0x652f, (q15_t)0x652c, (q15_t)0x6528, + (q15_t)0x6524, (q15_t)0x6520, (q15_t)0x651c, (q15_t)0x6518, (q15_t)0x6514, (q15_t)0x6511, (q15_t)0x650d, (q15_t)0x6509, + (q15_t)0x6505, (q15_t)0x6501, (q15_t)0x64fd, (q15_t)0x64f9, (q15_t)0x64f6, (q15_t)0x64f2, (q15_t)0x64ee, (q15_t)0x64ea, + (q15_t)0x64e6, (q15_t)0x64e2, (q15_t)0x64de, (q15_t)0x64db, (q15_t)0x64d7, (q15_t)0x64d3, (q15_t)0x64cf, (q15_t)0x64cb, + (q15_t)0x64c7, (q15_t)0x64c3, (q15_t)0x64bf, (q15_t)0x64bc, (q15_t)0x64b8, (q15_t)0x64b4, (q15_t)0x64b0, (q15_t)0x64ac, + (q15_t)0x64a8, (q15_t)0x64a4, (q15_t)0x64a0, (q15_t)0x649c, (q15_t)0x6499, (q15_t)0x6495, (q15_t)0x6491, (q15_t)0x648d, + (q15_t)0x6489, (q15_t)0x6485, (q15_t)0x6481, (q15_t)0x647d, (q15_t)0x6479, (q15_t)0x6476, (q15_t)0x6472, (q15_t)0x646e, + (q15_t)0x646a, (q15_t)0x6466, (q15_t)0x6462, (q15_t)0x645e, (q15_t)0x645a, (q15_t)0x6456, (q15_t)0x6453, (q15_t)0x644f, + (q15_t)0x644b, (q15_t)0x6447, (q15_t)0x6443, (q15_t)0x643f, (q15_t)0x643b, (q15_t)0x6437, (q15_t)0x6433, (q15_t)0x642f, + (q15_t)0x642b, (q15_t)0x6428, (q15_t)0x6424, (q15_t)0x6420, (q15_t)0x641c, (q15_t)0x6418, (q15_t)0x6414, (q15_t)0x6410, + (q15_t)0x640c, (q15_t)0x6408, (q15_t)0x6404, (q15_t)0x6400, (q15_t)0x63fc, (q15_t)0x63f9, (q15_t)0x63f5, (q15_t)0x63f1, + (q15_t)0x63ed, (q15_t)0x63e9, (q15_t)0x63e5, (q15_t)0x63e1, (q15_t)0x63dd, (q15_t)0x63d9, (q15_t)0x63d5, (q15_t)0x63d1, + (q15_t)0x63cd, (q15_t)0x63c9, (q15_t)0x63c5, (q15_t)0x63c1, (q15_t)0x63be, (q15_t)0x63ba, (q15_t)0x63b6, (q15_t)0x63b2, + (q15_t)0x63ae, (q15_t)0x63aa, (q15_t)0x63a6, (q15_t)0x63a2, (q15_t)0x639e, (q15_t)0x639a, (q15_t)0x6396, (q15_t)0x6392, + (q15_t)0x638e, (q15_t)0x638a, (q15_t)0x6386, (q15_t)0x6382, (q15_t)0x637e, (q15_t)0x637a, (q15_t)0x6377, (q15_t)0x6373, + (q15_t)0x636f, (q15_t)0x636b, (q15_t)0x6367, (q15_t)0x6363, (q15_t)0x635f, (q15_t)0x635b, (q15_t)0x6357, (q15_t)0x6353, + (q15_t)0x634f, (q15_t)0x634b, (q15_t)0x6347, (q15_t)0x6343, (q15_t)0x633f, (q15_t)0x633b, (q15_t)0x6337, (q15_t)0x6333, + (q15_t)0x632f, (q15_t)0x632b, (q15_t)0x6327, (q15_t)0x6323, (q15_t)0x631f, (q15_t)0x631b, (q15_t)0x6317, (q15_t)0x6313, + (q15_t)0x630f, (q15_t)0x630b, (q15_t)0x6307, (q15_t)0x6303, (q15_t)0x62ff, (q15_t)0x62fb, (q15_t)0x62f7, (q15_t)0x62f3, + (q15_t)0x62f0, (q15_t)0x62ec, (q15_t)0x62e8, (q15_t)0x62e4, (q15_t)0x62e0, (q15_t)0x62dc, (q15_t)0x62d8, (q15_t)0x62d4, + (q15_t)0x62d0, (q15_t)0x62cc, (q15_t)0x62c8, (q15_t)0x62c4, (q15_t)0x62c0, (q15_t)0x62bc, (q15_t)0x62b8, (q15_t)0x62b4, + (q15_t)0x62b0, (q15_t)0x62ac, (q15_t)0x62a8, (q15_t)0x62a4, (q15_t)0x62a0, (q15_t)0x629c, (q15_t)0x6298, (q15_t)0x6294, + (q15_t)0x6290, (q15_t)0x628c, (q15_t)0x6288, (q15_t)0x6284, (q15_t)0x6280, (q15_t)0x627c, (q15_t)0x6278, (q15_t)0x6273, + (q15_t)0x626f, (q15_t)0x626b, (q15_t)0x6267, (q15_t)0x6263, (q15_t)0x625f, (q15_t)0x625b, (q15_t)0x6257, (q15_t)0x6253, + (q15_t)0x624f, (q15_t)0x624b, (q15_t)0x6247, (q15_t)0x6243, (q15_t)0x623f, (q15_t)0x623b, (q15_t)0x6237, (q15_t)0x6233, + (q15_t)0x622f, (q15_t)0x622b, (q15_t)0x6227, (q15_t)0x6223, (q15_t)0x621f, (q15_t)0x621b, (q15_t)0x6217, (q15_t)0x6213, + (q15_t)0x620f, (q15_t)0x620b, (q15_t)0x6207, (q15_t)0x6203, (q15_t)0x61ff, (q15_t)0x61fb, (q15_t)0x61f7, (q15_t)0x61f3, + (q15_t)0x61ee, (q15_t)0x61ea, (q15_t)0x61e6, (q15_t)0x61e2, (q15_t)0x61de, (q15_t)0x61da, (q15_t)0x61d6, (q15_t)0x61d2, + (q15_t)0x61ce, (q15_t)0x61ca, (q15_t)0x61c6, (q15_t)0x61c2, (q15_t)0x61be, (q15_t)0x61ba, (q15_t)0x61b6, (q15_t)0x61b2, + (q15_t)0x61ae, (q15_t)0x61aa, (q15_t)0x61a6, (q15_t)0x61a1, (q15_t)0x619d, (q15_t)0x6199, (q15_t)0x6195, (q15_t)0x6191, + (q15_t)0x618d, (q15_t)0x6189, (q15_t)0x6185, (q15_t)0x6181, (q15_t)0x617d, (q15_t)0x6179, (q15_t)0x6175, (q15_t)0x6171, + (q15_t)0x616d, (q15_t)0x6168, (q15_t)0x6164, (q15_t)0x6160, (q15_t)0x615c, (q15_t)0x6158, (q15_t)0x6154, (q15_t)0x6150, + (q15_t)0x614c, (q15_t)0x6148, (q15_t)0x6144, (q15_t)0x6140, (q15_t)0x613c, (q15_t)0x6137, (q15_t)0x6133, (q15_t)0x612f, + (q15_t)0x612b, (q15_t)0x6127, (q15_t)0x6123, (q15_t)0x611f, (q15_t)0x611b, (q15_t)0x6117, (q15_t)0x6113, (q15_t)0x610f, + (q15_t)0x610a, (q15_t)0x6106, (q15_t)0x6102, (q15_t)0x60fe, (q15_t)0x60fa, (q15_t)0x60f6, (q15_t)0x60f2, (q15_t)0x60ee, + (q15_t)0x60ea, (q15_t)0x60e6, (q15_t)0x60e1, (q15_t)0x60dd, (q15_t)0x60d9, (q15_t)0x60d5, (q15_t)0x60d1, (q15_t)0x60cd, + (q15_t)0x60c9, (q15_t)0x60c5, (q15_t)0x60c1, (q15_t)0x60bc, (q15_t)0x60b8, (q15_t)0x60b4, (q15_t)0x60b0, (q15_t)0x60ac, + (q15_t)0x60a8, (q15_t)0x60a4, (q15_t)0x60a0, (q15_t)0x609c, (q15_t)0x6097, (q15_t)0x6093, (q15_t)0x608f, (q15_t)0x608b, + (q15_t)0x6087, (q15_t)0x6083, (q15_t)0x607f, (q15_t)0x607b, (q15_t)0x6076, (q15_t)0x6072, (q15_t)0x606e, (q15_t)0x606a, + (q15_t)0x6066, (q15_t)0x6062, (q15_t)0x605e, (q15_t)0x6059, (q15_t)0x6055, (q15_t)0x6051, (q15_t)0x604d, (q15_t)0x6049, + (q15_t)0x6045, (q15_t)0x6041, (q15_t)0x603c, (q15_t)0x6038, (q15_t)0x6034, (q15_t)0x6030, (q15_t)0x602c, (q15_t)0x6028, + (q15_t)0x6024, (q15_t)0x601f, (q15_t)0x601b, (q15_t)0x6017, (q15_t)0x6013, (q15_t)0x600f, (q15_t)0x600b, (q15_t)0x6007, + (q15_t)0x6002, (q15_t)0x5ffe, (q15_t)0x5ffa, (q15_t)0x5ff6, (q15_t)0x5ff2, (q15_t)0x5fee, (q15_t)0x5fe9, (q15_t)0x5fe5, + (q15_t)0x5fe1, (q15_t)0x5fdd, (q15_t)0x5fd9, (q15_t)0x5fd5, (q15_t)0x5fd0, (q15_t)0x5fcc, (q15_t)0x5fc8, (q15_t)0x5fc4, + (q15_t)0x5fc0, (q15_t)0x5fbc, (q15_t)0x5fb7, (q15_t)0x5fb3, (q15_t)0x5faf, (q15_t)0x5fab, (q15_t)0x5fa7, (q15_t)0x5fa3, + (q15_t)0x5f9e, (q15_t)0x5f9a, (q15_t)0x5f96, (q15_t)0x5f92, (q15_t)0x5f8e, (q15_t)0x5f8a, (q15_t)0x5f85, (q15_t)0x5f81, + (q15_t)0x5f7d, (q15_t)0x5f79, (q15_t)0x5f75, (q15_t)0x5f70, (q15_t)0x5f6c, (q15_t)0x5f68, (q15_t)0x5f64, (q15_t)0x5f60, + (q15_t)0x5f5b, (q15_t)0x5f57, (q15_t)0x5f53, (q15_t)0x5f4f, (q15_t)0x5f4b, (q15_t)0x5f46, (q15_t)0x5f42, (q15_t)0x5f3e, + (q15_t)0x5f3a, (q15_t)0x5f36, (q15_t)0x5f31, (q15_t)0x5f2d, (q15_t)0x5f29, (q15_t)0x5f25, (q15_t)0x5f21, (q15_t)0x5f1c, + (q15_t)0x5f18, (q15_t)0x5f14, (q15_t)0x5f10, (q15_t)0x5f0c, (q15_t)0x5f07, (q15_t)0x5f03, (q15_t)0x5eff, (q15_t)0x5efb, + (q15_t)0x5ef7, (q15_t)0x5ef2, (q15_t)0x5eee, (q15_t)0x5eea, (q15_t)0x5ee6, (q15_t)0x5ee2, (q15_t)0x5edd, (q15_t)0x5ed9, + (q15_t)0x5ed5, (q15_t)0x5ed1, (q15_t)0x5ecc, (q15_t)0x5ec8, (q15_t)0x5ec4, (q15_t)0x5ec0, (q15_t)0x5ebc, (q15_t)0x5eb7, + (q15_t)0x5eb3, (q15_t)0x5eaf, (q15_t)0x5eab, (q15_t)0x5ea6, (q15_t)0x5ea2, (q15_t)0x5e9e, (q15_t)0x5e9a, (q15_t)0x5e95, + (q15_t)0x5e91, (q15_t)0x5e8d, (q15_t)0x5e89, (q15_t)0x5e85, (q15_t)0x5e80, (q15_t)0x5e7c, (q15_t)0x5e78, (q15_t)0x5e74, + (q15_t)0x5e6f, (q15_t)0x5e6b, (q15_t)0x5e67, (q15_t)0x5e63, (q15_t)0x5e5e, (q15_t)0x5e5a, (q15_t)0x5e56, (q15_t)0x5e52, + (q15_t)0x5e4d, (q15_t)0x5e49, (q15_t)0x5e45, (q15_t)0x5e41, (q15_t)0x5e3c, (q15_t)0x5e38, (q15_t)0x5e34, (q15_t)0x5e30, + (q15_t)0x5e2b, (q15_t)0x5e27, (q15_t)0x5e23, (q15_t)0x5e1f, (q15_t)0x5e1a, (q15_t)0x5e16, (q15_t)0x5e12, (q15_t)0x5e0e, + (q15_t)0x5e09, (q15_t)0x5e05, (q15_t)0x5e01, (q15_t)0x5dfd, (q15_t)0x5df8, (q15_t)0x5df4, (q15_t)0x5df0, (q15_t)0x5deb, + (q15_t)0x5de7, (q15_t)0x5de3, (q15_t)0x5ddf, (q15_t)0x5dda, (q15_t)0x5dd6, (q15_t)0x5dd2, (q15_t)0x5dce, (q15_t)0x5dc9, + (q15_t)0x5dc5, (q15_t)0x5dc1, (q15_t)0x5dbc, (q15_t)0x5db8, (q15_t)0x5db4, (q15_t)0x5db0, (q15_t)0x5dab, (q15_t)0x5da7, + (q15_t)0x5da3, (q15_t)0x5d9e, (q15_t)0x5d9a, (q15_t)0x5d96, (q15_t)0x5d92, (q15_t)0x5d8d, (q15_t)0x5d89, (q15_t)0x5d85, + (q15_t)0x5d80, (q15_t)0x5d7c, (q15_t)0x5d78, (q15_t)0x5d74, (q15_t)0x5d6f, (q15_t)0x5d6b, (q15_t)0x5d67, (q15_t)0x5d62, + (q15_t)0x5d5e, (q15_t)0x5d5a, (q15_t)0x5d55, (q15_t)0x5d51, (q15_t)0x5d4d, (q15_t)0x5d49, (q15_t)0x5d44, (q15_t)0x5d40, + (q15_t)0x5d3c, (q15_t)0x5d37, (q15_t)0x5d33, (q15_t)0x5d2f, (q15_t)0x5d2a, (q15_t)0x5d26, (q15_t)0x5d22, (q15_t)0x5d1e, + (q15_t)0x5d19, (q15_t)0x5d15, (q15_t)0x5d11, (q15_t)0x5d0c, (q15_t)0x5d08, (q15_t)0x5d04, (q15_t)0x5cff, (q15_t)0x5cfb, + (q15_t)0x5cf7, (q15_t)0x5cf2, (q15_t)0x5cee, (q15_t)0x5cea, (q15_t)0x5ce5, (q15_t)0x5ce1, (q15_t)0x5cdd, (q15_t)0x5cd8, + (q15_t)0x5cd4, (q15_t)0x5cd0, (q15_t)0x5ccb, (q15_t)0x5cc7, (q15_t)0x5cc3, (q15_t)0x5cbe, (q15_t)0x5cba, (q15_t)0x5cb6, + (q15_t)0x5cb1, (q15_t)0x5cad, (q15_t)0x5ca9, (q15_t)0x5ca4, (q15_t)0x5ca0, (q15_t)0x5c9c, (q15_t)0x5c97, (q15_t)0x5c93, + (q15_t)0x5c8f, (q15_t)0x5c8a, (q15_t)0x5c86, (q15_t)0x5c82, (q15_t)0x5c7d, (q15_t)0x5c79, (q15_t)0x5c75, (q15_t)0x5c70, + (q15_t)0x5c6c, (q15_t)0x5c68, (q15_t)0x5c63, (q15_t)0x5c5f, (q15_t)0x5c5b, (q15_t)0x5c56, (q15_t)0x5c52, (q15_t)0x5c4e, + (q15_t)0x5c49, (q15_t)0x5c45, (q15_t)0x5c41, (q15_t)0x5c3c, (q15_t)0x5c38, (q15_t)0x5c33, (q15_t)0x5c2f, (q15_t)0x5c2b, + (q15_t)0x5c26, (q15_t)0x5c22, (q15_t)0x5c1e, (q15_t)0x5c19, (q15_t)0x5c15, (q15_t)0x5c11, (q15_t)0x5c0c, (q15_t)0x5c08, + (q15_t)0x5c03, (q15_t)0x5bff, (q15_t)0x5bfb, (q15_t)0x5bf6, (q15_t)0x5bf2, (q15_t)0x5bee, (q15_t)0x5be9, (q15_t)0x5be5, + (q15_t)0x5be0, (q15_t)0x5bdc, (q15_t)0x5bd8, (q15_t)0x5bd3, (q15_t)0x5bcf, (q15_t)0x5bcb, (q15_t)0x5bc6, (q15_t)0x5bc2, + (q15_t)0x5bbd, (q15_t)0x5bb9, (q15_t)0x5bb5, (q15_t)0x5bb0, (q15_t)0x5bac, (q15_t)0x5ba8, (q15_t)0x5ba3, (q15_t)0x5b9f, + (q15_t)0x5b9a, (q15_t)0x5b96, (q15_t)0x5b92, (q15_t)0x5b8d, (q15_t)0x5b89, (q15_t)0x5b84, (q15_t)0x5b80, (q15_t)0x5b7c, + (q15_t)0x5b77, (q15_t)0x5b73, (q15_t)0x5b6e, (q15_t)0x5b6a, (q15_t)0x5b66, (q15_t)0x5b61, (q15_t)0x5b5d, (q15_t)0x5b58, + (q15_t)0x5b54, (q15_t)0x5b50, (q15_t)0x5b4b, (q15_t)0x5b47, (q15_t)0x5b42, (q15_t)0x5b3e, (q15_t)0x5b3a, (q15_t)0x5b35, + (q15_t)0x5b31, (q15_t)0x5b2c, (q15_t)0x5b28, (q15_t)0x5b24, (q15_t)0x5b1f, (q15_t)0x5b1b, (q15_t)0x5b16, (q15_t)0x5b12, + (q15_t)0x5b0e, (q15_t)0x5b09, (q15_t)0x5b05, (q15_t)0x5b00, (q15_t)0x5afc, (q15_t)0x5af7, (q15_t)0x5af3, (q15_t)0x5aef, + (q15_t)0x5aea, (q15_t)0x5ae6, (q15_t)0x5ae1, (q15_t)0x5add, (q15_t)0x5ad8, (q15_t)0x5ad4, (q15_t)0x5ad0, (q15_t)0x5acb, + (q15_t)0x5ac7, (q15_t)0x5ac2, (q15_t)0x5abe, (q15_t)0x5ab9, (q15_t)0x5ab5, (q15_t)0x5ab1, (q15_t)0x5aac, (q15_t)0x5aa8, + (q15_t)0x5aa3, (q15_t)0x5a9f, (q15_t)0x5a9a, (q15_t)0x5a96, (q15_t)0x5a92, (q15_t)0x5a8d, (q15_t)0x5a89, (q15_t)0x5a84, + (q15_t)0x5a80, (q15_t)0x5a7b, (q15_t)0x5a77, (q15_t)0x5a72, (q15_t)0x5a6e, (q15_t)0x5a6a, (q15_t)0x5a65, (q15_t)0x5a61, + (q15_t)0x5a5c, (q15_t)0x5a58, (q15_t)0x5a53, (q15_t)0x5a4f, (q15_t)0x5a4a, (q15_t)0x5a46, (q15_t)0x5a41, (q15_t)0x5a3d, + (q15_t)0x5a39, (q15_t)0x5a34, (q15_t)0x5a30, (q15_t)0x5a2b, (q15_t)0x5a27, (q15_t)0x5a22, (q15_t)0x5a1e, (q15_t)0x5a19, + (q15_t)0x5a15, (q15_t)0x5a10, (q15_t)0x5a0c, (q15_t)0x5a07, (q15_t)0x5a03, (q15_t)0x59ff, (q15_t)0x59fa, (q15_t)0x59f6, + (q15_t)0x59f1, (q15_t)0x59ed, (q15_t)0x59e8, (q15_t)0x59e4, (q15_t)0x59df, (q15_t)0x59db, (q15_t)0x59d6, (q15_t)0x59d2, + (q15_t)0x59cd, (q15_t)0x59c9, (q15_t)0x59c4, (q15_t)0x59c0, (q15_t)0x59bb, (q15_t)0x59b7, (q15_t)0x59b2, (q15_t)0x59ae, + (q15_t)0x59a9, (q15_t)0x59a5, (q15_t)0x59a1, (q15_t)0x599c, (q15_t)0x5998, (q15_t)0x5993, (q15_t)0x598f, (q15_t)0x598a, + (q15_t)0x5986, (q15_t)0x5981, (q15_t)0x597d, (q15_t)0x5978, (q15_t)0x5974, (q15_t)0x596f, (q15_t)0x596b, (q15_t)0x5966, + (q15_t)0x5962, (q15_t)0x595d, (q15_t)0x5959, (q15_t)0x5954, (q15_t)0x5950, (q15_t)0x594b, (q15_t)0x5947, (q15_t)0x5942, + (q15_t)0x593e, (q15_t)0x5939, (q15_t)0x5935, (q15_t)0x5930, (q15_t)0x592c, (q15_t)0x5927, (q15_t)0x5923, (q15_t)0x591e, + (q15_t)0x591a, (q15_t)0x5915, (q15_t)0x5911, (q15_t)0x590c, (q15_t)0x5908, (q15_t)0x5903, (q15_t)0x58fe, (q15_t)0x58fa, + (q15_t)0x58f5, (q15_t)0x58f1, (q15_t)0x58ec, (q15_t)0x58e8, (q15_t)0x58e3, (q15_t)0x58df, (q15_t)0x58da, (q15_t)0x58d6, + (q15_t)0x58d1, (q15_t)0x58cd, (q15_t)0x58c8, (q15_t)0x58c4, (q15_t)0x58bf, (q15_t)0x58bb, (q15_t)0x58b6, (q15_t)0x58b2, + (q15_t)0x58ad, (q15_t)0x58a9, (q15_t)0x58a4, (q15_t)0x589f, (q15_t)0x589b, (q15_t)0x5896, (q15_t)0x5892, (q15_t)0x588d, + (q15_t)0x5889, (q15_t)0x5884, (q15_t)0x5880, (q15_t)0x587b, (q15_t)0x5877, (q15_t)0x5872, (q15_t)0x586e, (q15_t)0x5869, + (q15_t)0x5864, (q15_t)0x5860, (q15_t)0x585b, (q15_t)0x5857, (q15_t)0x5852, (q15_t)0x584e, (q15_t)0x5849, (q15_t)0x5845, + (q15_t)0x5840, (q15_t)0x583c, (q15_t)0x5837, (q15_t)0x5832, (q15_t)0x582e, (q15_t)0x5829, (q15_t)0x5825, (q15_t)0x5820, + (q15_t)0x581c, (q15_t)0x5817, (q15_t)0x5813, (q15_t)0x580e, (q15_t)0x5809, (q15_t)0x5805, (q15_t)0x5800, (q15_t)0x57fc, + (q15_t)0x57f7, (q15_t)0x57f3, (q15_t)0x57ee, (q15_t)0x57e9, (q15_t)0x57e5, (q15_t)0x57e0, (q15_t)0x57dc, (q15_t)0x57d7, + (q15_t)0x57d3, (q15_t)0x57ce, (q15_t)0x57c9, (q15_t)0x57c5, (q15_t)0x57c0, (q15_t)0x57bc, (q15_t)0x57b7, (q15_t)0x57b3, + (q15_t)0x57ae, (q15_t)0x57a9, (q15_t)0x57a5, (q15_t)0x57a0, (q15_t)0x579c, (q15_t)0x5797, (q15_t)0x5793, (q15_t)0x578e, + (q15_t)0x5789, (q15_t)0x5785, (q15_t)0x5780, (q15_t)0x577c, (q15_t)0x5777, (q15_t)0x5772, (q15_t)0x576e, (q15_t)0x5769, + (q15_t)0x5765, (q15_t)0x5760, (q15_t)0x575c, (q15_t)0x5757, (q15_t)0x5752, (q15_t)0x574e, (q15_t)0x5749, (q15_t)0x5745, + (q15_t)0x5740, (q15_t)0x573b, (q15_t)0x5737, (q15_t)0x5732, (q15_t)0x572e, (q15_t)0x5729, (q15_t)0x5724, (q15_t)0x5720, + (q15_t)0x571b, (q15_t)0x5717, (q15_t)0x5712, (q15_t)0x570d, (q15_t)0x5709, (q15_t)0x5704, (q15_t)0x56ff, (q15_t)0x56fb, + (q15_t)0x56f6, (q15_t)0x56f2, (q15_t)0x56ed, (q15_t)0x56e8, (q15_t)0x56e4, (q15_t)0x56df, (q15_t)0x56db, (q15_t)0x56d6, + (q15_t)0x56d1, (q15_t)0x56cd, (q15_t)0x56c8, (q15_t)0x56c4, (q15_t)0x56bf, (q15_t)0x56ba, (q15_t)0x56b6, (q15_t)0x56b1, + (q15_t)0x56ac, (q15_t)0x56a8, (q15_t)0x56a3, (q15_t)0x569f, (q15_t)0x569a, (q15_t)0x5695, (q15_t)0x5691, (q15_t)0x568c, + (q15_t)0x5687, (q15_t)0x5683, (q15_t)0x567e, (q15_t)0x5679, (q15_t)0x5675, (q15_t)0x5670, (q15_t)0x566c, (q15_t)0x5667, + (q15_t)0x5662, (q15_t)0x565e, (q15_t)0x5659, (q15_t)0x5654, (q15_t)0x5650, (q15_t)0x564b, (q15_t)0x5646, (q15_t)0x5642, + (q15_t)0x563d, (q15_t)0x5639, (q15_t)0x5634, (q15_t)0x562f, (q15_t)0x562b, (q15_t)0x5626, (q15_t)0x5621, (q15_t)0x561d, + (q15_t)0x5618, (q15_t)0x5613, (q15_t)0x560f, (q15_t)0x560a, (q15_t)0x5605, (q15_t)0x5601, (q15_t)0x55fc, (q15_t)0x55f7, + (q15_t)0x55f3, (q15_t)0x55ee, (q15_t)0x55ea, (q15_t)0x55e5, (q15_t)0x55e0, (q15_t)0x55dc, (q15_t)0x55d7, (q15_t)0x55d2, + (q15_t)0x55ce, (q15_t)0x55c9, (q15_t)0x55c4, (q15_t)0x55c0, (q15_t)0x55bb, (q15_t)0x55b6, (q15_t)0x55b2, (q15_t)0x55ad, + (q15_t)0x55a8, (q15_t)0x55a4, (q15_t)0x559f, (q15_t)0x559a, (q15_t)0x5596, (q15_t)0x5591, (q15_t)0x558c, (q15_t)0x5588, + (q15_t)0x5583, (q15_t)0x557e, (q15_t)0x5579, (q15_t)0x5575, (q15_t)0x5570, (q15_t)0x556b, (q15_t)0x5567, (q15_t)0x5562, + (q15_t)0x555d, (q15_t)0x5559, (q15_t)0x5554, (q15_t)0x554f, (q15_t)0x554b, (q15_t)0x5546, (q15_t)0x5541, (q15_t)0x553d, + (q15_t)0x5538, (q15_t)0x5533, (q15_t)0x552f, (q15_t)0x552a, (q15_t)0x5525, (q15_t)0x5520, (q15_t)0x551c, (q15_t)0x5517, + (q15_t)0x5512, (q15_t)0x550e, (q15_t)0x5509, (q15_t)0x5504, (q15_t)0x5500, (q15_t)0x54fb, (q15_t)0x54f6, (q15_t)0x54f2, + (q15_t)0x54ed, (q15_t)0x54e8, (q15_t)0x54e3, (q15_t)0x54df, (q15_t)0x54da, (q15_t)0x54d5, (q15_t)0x54d1, (q15_t)0x54cc, + (q15_t)0x54c7, (q15_t)0x54c2, (q15_t)0x54be, (q15_t)0x54b9, (q15_t)0x54b4, (q15_t)0x54b0, (q15_t)0x54ab, (q15_t)0x54a6, + (q15_t)0x54a2, (q15_t)0x549d, (q15_t)0x5498, (q15_t)0x5493, (q15_t)0x548f, (q15_t)0x548a, (q15_t)0x5485, (q15_t)0x5480, + (q15_t)0x547c, (q15_t)0x5477, (q15_t)0x5472, (q15_t)0x546e, (q15_t)0x5469, (q15_t)0x5464, (q15_t)0x545f, (q15_t)0x545b, + (q15_t)0x5456, (q15_t)0x5451, (q15_t)0x544d, (q15_t)0x5448, (q15_t)0x5443, (q15_t)0x543e, (q15_t)0x543a, (q15_t)0x5435, + (q15_t)0x5430, (q15_t)0x542b, (q15_t)0x5427, (q15_t)0x5422, (q15_t)0x541d, (q15_t)0x5418, (q15_t)0x5414, (q15_t)0x540f, + (q15_t)0x540a, (q15_t)0x5406, (q15_t)0x5401, (q15_t)0x53fc, (q15_t)0x53f7, (q15_t)0x53f3, (q15_t)0x53ee, (q15_t)0x53e9, + (q15_t)0x53e4, (q15_t)0x53e0, (q15_t)0x53db, (q15_t)0x53d6, (q15_t)0x53d1, (q15_t)0x53cd, (q15_t)0x53c8, (q15_t)0x53c3, + (q15_t)0x53be, (q15_t)0x53ba, (q15_t)0x53b5, (q15_t)0x53b0, (q15_t)0x53ab, (q15_t)0x53a7, (q15_t)0x53a2, (q15_t)0x539d, + (q15_t)0x5398, (q15_t)0x5394, (q15_t)0x538f, (q15_t)0x538a, (q15_t)0x5385, (q15_t)0x5380, (q15_t)0x537c, (q15_t)0x5377, + (q15_t)0x5372, (q15_t)0x536d, (q15_t)0x5369, (q15_t)0x5364, (q15_t)0x535f, (q15_t)0x535a, (q15_t)0x5356, (q15_t)0x5351, + (q15_t)0x534c, (q15_t)0x5347, (q15_t)0x5343, (q15_t)0x533e, (q15_t)0x5339, (q15_t)0x5334, (q15_t)0x532f, (q15_t)0x532b, + (q15_t)0x5326, (q15_t)0x5321, (q15_t)0x531c, (q15_t)0x5318, (q15_t)0x5313, (q15_t)0x530e, (q15_t)0x5309, (q15_t)0x5304, + (q15_t)0x5300, (q15_t)0x52fb, (q15_t)0x52f6, (q15_t)0x52f1, (q15_t)0x52ec, (q15_t)0x52e8, (q15_t)0x52e3, (q15_t)0x52de, + (q15_t)0x52d9, (q15_t)0x52d5, (q15_t)0x52d0, (q15_t)0x52cb, (q15_t)0x52c6, (q15_t)0x52c1, (q15_t)0x52bd, (q15_t)0x52b8, + (q15_t)0x52b3, (q15_t)0x52ae, (q15_t)0x52a9, (q15_t)0x52a5, (q15_t)0x52a0, (q15_t)0x529b, (q15_t)0x5296, (q15_t)0x5291, + (q15_t)0x528d, (q15_t)0x5288, (q15_t)0x5283, (q15_t)0x527e, (q15_t)0x5279, (q15_t)0x5275, (q15_t)0x5270, (q15_t)0x526b, + (q15_t)0x5266, (q15_t)0x5261, (q15_t)0x525d, (q15_t)0x5258, (q15_t)0x5253, (q15_t)0x524e, (q15_t)0x5249, (q15_t)0x5244, + (q15_t)0x5240, (q15_t)0x523b, (q15_t)0x5236, (q15_t)0x5231, (q15_t)0x522c, (q15_t)0x5228, (q15_t)0x5223, (q15_t)0x521e, + (q15_t)0x5219, (q15_t)0x5214, (q15_t)0x520f, (q15_t)0x520b, (q15_t)0x5206, (q15_t)0x5201, (q15_t)0x51fc, (q15_t)0x51f7, + (q15_t)0x51f3, (q15_t)0x51ee, (q15_t)0x51e9, (q15_t)0x51e4, (q15_t)0x51df, (q15_t)0x51da, (q15_t)0x51d6, (q15_t)0x51d1, + (q15_t)0x51cc, (q15_t)0x51c7, (q15_t)0x51c2, (q15_t)0x51bd, (q15_t)0x51b9, (q15_t)0x51b4, (q15_t)0x51af, (q15_t)0x51aa, + (q15_t)0x51a5, (q15_t)0x51a0, (q15_t)0x519c, (q15_t)0x5197, (q15_t)0x5192, (q15_t)0x518d, (q15_t)0x5188, (q15_t)0x5183, + (q15_t)0x517e, (q15_t)0x517a, (q15_t)0x5175, (q15_t)0x5170, (q15_t)0x516b, (q15_t)0x5166, (q15_t)0x5161, (q15_t)0x515d, + (q15_t)0x5158, (q15_t)0x5153, (q15_t)0x514e, (q15_t)0x5149, (q15_t)0x5144, (q15_t)0x513f, (q15_t)0x513b, (q15_t)0x5136, + (q15_t)0x5131, (q15_t)0x512c, (q15_t)0x5127, (q15_t)0x5122, (q15_t)0x511d, (q15_t)0x5119, (q15_t)0x5114, (q15_t)0x510f, + (q15_t)0x510a, (q15_t)0x5105, (q15_t)0x5100, (q15_t)0x50fb, (q15_t)0x50f7, (q15_t)0x50f2, (q15_t)0x50ed, (q15_t)0x50e8, + (q15_t)0x50e3, (q15_t)0x50de, (q15_t)0x50d9, (q15_t)0x50d4, (q15_t)0x50d0, (q15_t)0x50cb, (q15_t)0x50c6, (q15_t)0x50c1, + (q15_t)0x50bc, (q15_t)0x50b7, (q15_t)0x50b2, (q15_t)0x50ad, (q15_t)0x50a9, (q15_t)0x50a4, (q15_t)0x509f, (q15_t)0x509a, + (q15_t)0x5095, (q15_t)0x5090, (q15_t)0x508b, (q15_t)0x5086, (q15_t)0x5082, (q15_t)0x507d, (q15_t)0x5078, (q15_t)0x5073, + (q15_t)0x506e, (q15_t)0x5069, (q15_t)0x5064, (q15_t)0x505f, (q15_t)0x505a, (q15_t)0x5056, (q15_t)0x5051, (q15_t)0x504c, + (q15_t)0x5047, (q15_t)0x5042, (q15_t)0x503d, (q15_t)0x5038, (q15_t)0x5033, (q15_t)0x502e, (q15_t)0x5029, (q15_t)0x5025, + (q15_t)0x5020, (q15_t)0x501b, (q15_t)0x5016, (q15_t)0x5011, (q15_t)0x500c, (q15_t)0x5007, (q15_t)0x5002, (q15_t)0x4ffd, + (q15_t)0x4ff8, (q15_t)0x4ff4, (q15_t)0x4fef, (q15_t)0x4fea, (q15_t)0x4fe5, (q15_t)0x4fe0, (q15_t)0x4fdb, (q15_t)0x4fd6, + (q15_t)0x4fd1, (q15_t)0x4fcc, (q15_t)0x4fc7, (q15_t)0x4fc2, (q15_t)0x4fbe, (q15_t)0x4fb9, (q15_t)0x4fb4, (q15_t)0x4faf, + (q15_t)0x4faa, (q15_t)0x4fa5, (q15_t)0x4fa0, (q15_t)0x4f9b, (q15_t)0x4f96, (q15_t)0x4f91, (q15_t)0x4f8c, (q15_t)0x4f87, + (q15_t)0x4f82, (q15_t)0x4f7e, (q15_t)0x4f79, (q15_t)0x4f74, (q15_t)0x4f6f, (q15_t)0x4f6a, (q15_t)0x4f65, (q15_t)0x4f60, + (q15_t)0x4f5b, (q15_t)0x4f56, (q15_t)0x4f51, (q15_t)0x4f4c, (q15_t)0x4f47, (q15_t)0x4f42, (q15_t)0x4f3d, (q15_t)0x4f39, + (q15_t)0x4f34, (q15_t)0x4f2f, (q15_t)0x4f2a, (q15_t)0x4f25, (q15_t)0x4f20, (q15_t)0x4f1b, (q15_t)0x4f16, (q15_t)0x4f11, + (q15_t)0x4f0c, (q15_t)0x4f07, (q15_t)0x4f02, (q15_t)0x4efd, (q15_t)0x4ef8, (q15_t)0x4ef3, (q15_t)0x4eee, (q15_t)0x4ee9, + (q15_t)0x4ee5, (q15_t)0x4ee0, (q15_t)0x4edb, (q15_t)0x4ed6, (q15_t)0x4ed1, (q15_t)0x4ecc, (q15_t)0x4ec7, (q15_t)0x4ec2, + (q15_t)0x4ebd, (q15_t)0x4eb8, (q15_t)0x4eb3, (q15_t)0x4eae, (q15_t)0x4ea9, (q15_t)0x4ea4, (q15_t)0x4e9f, (q15_t)0x4e9a, + (q15_t)0x4e95, (q15_t)0x4e90, (q15_t)0x4e8b, (q15_t)0x4e86, (q15_t)0x4e81, (q15_t)0x4e7c, (q15_t)0x4e78, (q15_t)0x4e73, + (q15_t)0x4e6e, (q15_t)0x4e69, (q15_t)0x4e64, (q15_t)0x4e5f, (q15_t)0x4e5a, (q15_t)0x4e55, (q15_t)0x4e50, (q15_t)0x4e4b, + (q15_t)0x4e46, (q15_t)0x4e41, (q15_t)0x4e3c, (q15_t)0x4e37, (q15_t)0x4e32, (q15_t)0x4e2d, (q15_t)0x4e28, (q15_t)0x4e23, + (q15_t)0x4e1e, (q15_t)0x4e19, (q15_t)0x4e14, (q15_t)0x4e0f, (q15_t)0x4e0a, (q15_t)0x4e05, (q15_t)0x4e00, (q15_t)0x4dfb, + (q15_t)0x4df6, (q15_t)0x4df1, (q15_t)0x4dec, (q15_t)0x4de7, (q15_t)0x4de2, (q15_t)0x4ddd, (q15_t)0x4dd8, (q15_t)0x4dd3, + (q15_t)0x4dce, (q15_t)0x4dc9, (q15_t)0x4dc4, (q15_t)0x4dbf, (q15_t)0x4dba, (q15_t)0x4db5, (q15_t)0x4db0, (q15_t)0x4dab, + (q15_t)0x4da6, (q15_t)0x4da1, (q15_t)0x4d9c, (q15_t)0x4d97, (q15_t)0x4d92, (q15_t)0x4d8d, (q15_t)0x4d88, (q15_t)0x4d83, + (q15_t)0x4d7e, (q15_t)0x4d79, (q15_t)0x4d74, (q15_t)0x4d6f, (q15_t)0x4d6a, (q15_t)0x4d65, (q15_t)0x4d60, (q15_t)0x4d5b, + (q15_t)0x4d56, (q15_t)0x4d51, (q15_t)0x4d4c, (q15_t)0x4d47, (q15_t)0x4d42, (q15_t)0x4d3d, (q15_t)0x4d38, (q15_t)0x4d33, + (q15_t)0x4d2e, (q15_t)0x4d29, (q15_t)0x4d24, (q15_t)0x4d1f, (q15_t)0x4d1a, (q15_t)0x4d15, (q15_t)0x4d10, (q15_t)0x4d0b, + (q15_t)0x4d06, (q15_t)0x4d01, (q15_t)0x4cfc, (q15_t)0x4cf7, (q15_t)0x4cf2, (q15_t)0x4ced, (q15_t)0x4ce8, (q15_t)0x4ce3, + (q15_t)0x4cde, (q15_t)0x4cd9, (q15_t)0x4cd4, (q15_t)0x4ccf, (q15_t)0x4cca, (q15_t)0x4cc5, (q15_t)0x4cc0, (q15_t)0x4cbb, + (q15_t)0x4cb6, (q15_t)0x4cb1, (q15_t)0x4cac, (q15_t)0x4ca7, (q15_t)0x4ca2, (q15_t)0x4c9d, (q15_t)0x4c98, (q15_t)0x4c93, + (q15_t)0x4c8e, (q15_t)0x4c88, (q15_t)0x4c83, (q15_t)0x4c7e, (q15_t)0x4c79, (q15_t)0x4c74, (q15_t)0x4c6f, (q15_t)0x4c6a, + (q15_t)0x4c65, (q15_t)0x4c60, (q15_t)0x4c5b, (q15_t)0x4c56, (q15_t)0x4c51, (q15_t)0x4c4c, (q15_t)0x4c47, (q15_t)0x4c42, + (q15_t)0x4c3d, (q15_t)0x4c38, (q15_t)0x4c33, (q15_t)0x4c2e, (q15_t)0x4c29, (q15_t)0x4c24, (q15_t)0x4c1f, (q15_t)0x4c1a, + (q15_t)0x4c14, (q15_t)0x4c0f, (q15_t)0x4c0a, (q15_t)0x4c05, (q15_t)0x4c00, (q15_t)0x4bfb, (q15_t)0x4bf6, (q15_t)0x4bf1, + (q15_t)0x4bec, (q15_t)0x4be7, (q15_t)0x4be2, (q15_t)0x4bdd, (q15_t)0x4bd8, (q15_t)0x4bd3, (q15_t)0x4bce, (q15_t)0x4bc9, + (q15_t)0x4bc4, (q15_t)0x4bbe, (q15_t)0x4bb9, (q15_t)0x4bb4, (q15_t)0x4baf, (q15_t)0x4baa, (q15_t)0x4ba5, (q15_t)0x4ba0, + (q15_t)0x4b9b, (q15_t)0x4b96, (q15_t)0x4b91, (q15_t)0x4b8c, (q15_t)0x4b87, (q15_t)0x4b82, (q15_t)0x4b7d, (q15_t)0x4b77, + (q15_t)0x4b72, (q15_t)0x4b6d, (q15_t)0x4b68, (q15_t)0x4b63, (q15_t)0x4b5e, (q15_t)0x4b59, (q15_t)0x4b54, (q15_t)0x4b4f, + (q15_t)0x4b4a, (q15_t)0x4b45, (q15_t)0x4b40, (q15_t)0x4b3b, (q15_t)0x4b35, (q15_t)0x4b30, (q15_t)0x4b2b, (q15_t)0x4b26, + (q15_t)0x4b21, (q15_t)0x4b1c, (q15_t)0x4b17, (q15_t)0x4b12, (q15_t)0x4b0d, (q15_t)0x4b08, (q15_t)0x4b03, (q15_t)0x4afd, + (q15_t)0x4af8, (q15_t)0x4af3, (q15_t)0x4aee, (q15_t)0x4ae9, (q15_t)0x4ae4, (q15_t)0x4adf, (q15_t)0x4ada, (q15_t)0x4ad5, + (q15_t)0x4ad0, (q15_t)0x4acb, (q15_t)0x4ac5, (q15_t)0x4ac0, (q15_t)0x4abb, (q15_t)0x4ab6, (q15_t)0x4ab1, (q15_t)0x4aac, + (q15_t)0x4aa7, (q15_t)0x4aa2, (q15_t)0x4a9d, (q15_t)0x4a97, (q15_t)0x4a92, (q15_t)0x4a8d, (q15_t)0x4a88, (q15_t)0x4a83, + (q15_t)0x4a7e, (q15_t)0x4a79, (q15_t)0x4a74, (q15_t)0x4a6f, (q15_t)0x4a6a, (q15_t)0x4a64, (q15_t)0x4a5f, (q15_t)0x4a5a, + (q15_t)0x4a55, (q15_t)0x4a50, (q15_t)0x4a4b, (q15_t)0x4a46, (q15_t)0x4a41, (q15_t)0x4a3b, (q15_t)0x4a36, (q15_t)0x4a31, + (q15_t)0x4a2c, (q15_t)0x4a27, (q15_t)0x4a22, (q15_t)0x4a1d, (q15_t)0x4a18, (q15_t)0x4a12, (q15_t)0x4a0d, (q15_t)0x4a08, + (q15_t)0x4a03, (q15_t)0x49fe, (q15_t)0x49f9, (q15_t)0x49f4, (q15_t)0x49ef, (q15_t)0x49e9, (q15_t)0x49e4, (q15_t)0x49df, + (q15_t)0x49da, (q15_t)0x49d5, (q15_t)0x49d0, (q15_t)0x49cb, (q15_t)0x49c6, (q15_t)0x49c0, (q15_t)0x49bb, (q15_t)0x49b6, + (q15_t)0x49b1, (q15_t)0x49ac, (q15_t)0x49a7, (q15_t)0x49a2, (q15_t)0x499c, (q15_t)0x4997, (q15_t)0x4992, (q15_t)0x498d, + (q15_t)0x4988, (q15_t)0x4983, (q15_t)0x497e, (q15_t)0x4978, (q15_t)0x4973, (q15_t)0x496e, (q15_t)0x4969, (q15_t)0x4964, + (q15_t)0x495f, (q15_t)0x495a, (q15_t)0x4954, (q15_t)0x494f, (q15_t)0x494a, (q15_t)0x4945, (q15_t)0x4940, (q15_t)0x493b, + (q15_t)0x4936, (q15_t)0x4930, (q15_t)0x492b, (q15_t)0x4926, (q15_t)0x4921, (q15_t)0x491c, (q15_t)0x4917, (q15_t)0x4911, + (q15_t)0x490c, (q15_t)0x4907, (q15_t)0x4902, (q15_t)0x48fd, (q15_t)0x48f8, (q15_t)0x48f2, (q15_t)0x48ed, (q15_t)0x48e8, + (q15_t)0x48e3, (q15_t)0x48de, (q15_t)0x48d9, (q15_t)0x48d3, (q15_t)0x48ce, (q15_t)0x48c9, (q15_t)0x48c4, (q15_t)0x48bf, + (q15_t)0x48ba, (q15_t)0x48b4, (q15_t)0x48af, (q15_t)0x48aa, (q15_t)0x48a5, (q15_t)0x48a0, (q15_t)0x489b, (q15_t)0x4895, + (q15_t)0x4890, (q15_t)0x488b, (q15_t)0x4886, (q15_t)0x4881, (q15_t)0x487c, (q15_t)0x4876, (q15_t)0x4871, (q15_t)0x486c, + (q15_t)0x4867, (q15_t)0x4862, (q15_t)0x485c, (q15_t)0x4857, (q15_t)0x4852, (q15_t)0x484d, (q15_t)0x4848, (q15_t)0x4843, + (q15_t)0x483d, (q15_t)0x4838, (q15_t)0x4833, (q15_t)0x482e, (q15_t)0x4829, (q15_t)0x4823, (q15_t)0x481e, (q15_t)0x4819, + (q15_t)0x4814, (q15_t)0x480f, (q15_t)0x4809, (q15_t)0x4804, (q15_t)0x47ff, (q15_t)0x47fa, (q15_t)0x47f5, (q15_t)0x47ef, + (q15_t)0x47ea, (q15_t)0x47e5, (q15_t)0x47e0, (q15_t)0x47db, (q15_t)0x47d5, (q15_t)0x47d0, (q15_t)0x47cb, (q15_t)0x47c6, + (q15_t)0x47c1, (q15_t)0x47bb, (q15_t)0x47b6, (q15_t)0x47b1, (q15_t)0x47ac, (q15_t)0x47a7, (q15_t)0x47a1, (q15_t)0x479c, + (q15_t)0x4797, (q15_t)0x4792, (q15_t)0x478d, (q15_t)0x4787, (q15_t)0x4782, (q15_t)0x477d, (q15_t)0x4778, (q15_t)0x4773, + (q15_t)0x476d, (q15_t)0x4768, (q15_t)0x4763, (q15_t)0x475e, (q15_t)0x4758, (q15_t)0x4753, (q15_t)0x474e, (q15_t)0x4749, + (q15_t)0x4744, (q15_t)0x473e, (q15_t)0x4739, (q15_t)0x4734, (q15_t)0x472f, (q15_t)0x4729, (q15_t)0x4724, (q15_t)0x471f, + (q15_t)0x471a, (q15_t)0x4715, (q15_t)0x470f, (q15_t)0x470a, (q15_t)0x4705, (q15_t)0x4700, (q15_t)0x46fa, (q15_t)0x46f5, + (q15_t)0x46f0, (q15_t)0x46eb, (q15_t)0x46e6, (q15_t)0x46e0, (q15_t)0x46db, (q15_t)0x46d6, (q15_t)0x46d1, (q15_t)0x46cb, + (q15_t)0x46c6, (q15_t)0x46c1, (q15_t)0x46bc, (q15_t)0x46b6, (q15_t)0x46b1, (q15_t)0x46ac, (q15_t)0x46a7, (q15_t)0x46a1, + (q15_t)0x469c, (q15_t)0x4697, (q15_t)0x4692, (q15_t)0x468d, (q15_t)0x4687, (q15_t)0x4682, (q15_t)0x467d, (q15_t)0x4678, + (q15_t)0x4672, (q15_t)0x466d, (q15_t)0x4668, (q15_t)0x4663, (q15_t)0x465d, (q15_t)0x4658, (q15_t)0x4653, (q15_t)0x464e, + (q15_t)0x4648, (q15_t)0x4643, (q15_t)0x463e, (q15_t)0x4639, (q15_t)0x4633, (q15_t)0x462e, (q15_t)0x4629, (q15_t)0x4624, + (q15_t)0x461e, (q15_t)0x4619, (q15_t)0x4614, (q15_t)0x460e, (q15_t)0x4609, (q15_t)0x4604, (q15_t)0x45ff, (q15_t)0x45f9, + (q15_t)0x45f4, (q15_t)0x45ef, (q15_t)0x45ea, (q15_t)0x45e4, (q15_t)0x45df, (q15_t)0x45da, (q15_t)0x45d5, (q15_t)0x45cf, + (q15_t)0x45ca, (q15_t)0x45c5, (q15_t)0x45c0, (q15_t)0x45ba, (q15_t)0x45b5, (q15_t)0x45b0, (q15_t)0x45aa, (q15_t)0x45a5, + (q15_t)0x45a0, (q15_t)0x459b, (q15_t)0x4595, (q15_t)0x4590, (q15_t)0x458b, (q15_t)0x4586, (q15_t)0x4580, (q15_t)0x457b, + (q15_t)0x4576, (q15_t)0x4570, (q15_t)0x456b, (q15_t)0x4566, (q15_t)0x4561, (q15_t)0x455b, (q15_t)0x4556, (q15_t)0x4551, + (q15_t)0x454b, (q15_t)0x4546, (q15_t)0x4541, (q15_t)0x453c, (q15_t)0x4536, (q15_t)0x4531, (q15_t)0x452c, (q15_t)0x4526, + (q15_t)0x4521, (q15_t)0x451c, (q15_t)0x4517, (q15_t)0x4511, (q15_t)0x450c, (q15_t)0x4507, (q15_t)0x4501, (q15_t)0x44fc, + (q15_t)0x44f7, (q15_t)0x44f2, (q15_t)0x44ec, (q15_t)0x44e7, (q15_t)0x44e2, (q15_t)0x44dc, (q15_t)0x44d7, (q15_t)0x44d2, + (q15_t)0x44cd, (q15_t)0x44c7, (q15_t)0x44c2, (q15_t)0x44bd, (q15_t)0x44b7, (q15_t)0x44b2, (q15_t)0x44ad, (q15_t)0x44a7, + (q15_t)0x44a2, (q15_t)0x449d, (q15_t)0x4497, (q15_t)0x4492, (q15_t)0x448d, (q15_t)0x4488, (q15_t)0x4482, (q15_t)0x447d, + (q15_t)0x4478, (q15_t)0x4472, (q15_t)0x446d, (q15_t)0x4468, (q15_t)0x4462, (q15_t)0x445d, (q15_t)0x4458, (q15_t)0x4452, + (q15_t)0x444d, (q15_t)0x4448, (q15_t)0x4443, (q15_t)0x443d, (q15_t)0x4438, (q15_t)0x4433, (q15_t)0x442d, (q15_t)0x4428, + (q15_t)0x4423, (q15_t)0x441d, (q15_t)0x4418, (q15_t)0x4413, (q15_t)0x440d, (q15_t)0x4408, (q15_t)0x4403, (q15_t)0x43fd, + (q15_t)0x43f8, (q15_t)0x43f3, (q15_t)0x43ed, (q15_t)0x43e8, (q15_t)0x43e3, (q15_t)0x43dd, (q15_t)0x43d8, (q15_t)0x43d3, + (q15_t)0x43cd, (q15_t)0x43c8, (q15_t)0x43c3, (q15_t)0x43bd, (q15_t)0x43b8, (q15_t)0x43b3, (q15_t)0x43ad, (q15_t)0x43a8, + (q15_t)0x43a3, (q15_t)0x439d, (q15_t)0x4398, (q15_t)0x4393, (q15_t)0x438d, (q15_t)0x4388, (q15_t)0x4383, (q15_t)0x437d, + (q15_t)0x4378, (q15_t)0x4373, (q15_t)0x436d, (q15_t)0x4368, (q15_t)0x4363, (q15_t)0x435d, (q15_t)0x4358, (q15_t)0x4353, + (q15_t)0x434d, (q15_t)0x4348, (q15_t)0x4343, (q15_t)0x433d, (q15_t)0x4338, (q15_t)0x4333, (q15_t)0x432d, (q15_t)0x4328, + (q15_t)0x4323, (q15_t)0x431d, (q15_t)0x4318, (q15_t)0x4313, (q15_t)0x430d, (q15_t)0x4308, (q15_t)0x4302, (q15_t)0x42fd, + (q15_t)0x42f8, (q15_t)0x42f2, (q15_t)0x42ed, (q15_t)0x42e8, (q15_t)0x42e2, (q15_t)0x42dd, (q15_t)0x42d8, (q15_t)0x42d2, + (q15_t)0x42cd, (q15_t)0x42c8, (q15_t)0x42c2, (q15_t)0x42bd, (q15_t)0x42b7, (q15_t)0x42b2, (q15_t)0x42ad, (q15_t)0x42a7, + (q15_t)0x42a2, (q15_t)0x429d, (q15_t)0x4297, (q15_t)0x4292, (q15_t)0x428d, (q15_t)0x4287, (q15_t)0x4282, (q15_t)0x427c, + (q15_t)0x4277, (q15_t)0x4272, (q15_t)0x426c, (q15_t)0x4267, (q15_t)0x4262, (q15_t)0x425c, (q15_t)0x4257, (q15_t)0x4251, + (q15_t)0x424c, (q15_t)0x4247, (q15_t)0x4241, (q15_t)0x423c, (q15_t)0x4237, (q15_t)0x4231, (q15_t)0x422c, (q15_t)0x4226, + (q15_t)0x4221, (q15_t)0x421c, (q15_t)0x4216, (q15_t)0x4211, (q15_t)0x420c, (q15_t)0x4206, (q15_t)0x4201, (q15_t)0x41fb, + (q15_t)0x41f6, (q15_t)0x41f1, (q15_t)0x41eb, (q15_t)0x41e6, (q15_t)0x41e0, (q15_t)0x41db, (q15_t)0x41d6, (q15_t)0x41d0, + (q15_t)0x41cb, (q15_t)0x41c6, (q15_t)0x41c0, (q15_t)0x41bb, (q15_t)0x41b5, (q15_t)0x41b0, (q15_t)0x41ab, (q15_t)0x41a5, + (q15_t)0x41a0, (q15_t)0x419a, (q15_t)0x4195, (q15_t)0x4190, (q15_t)0x418a, (q15_t)0x4185, (q15_t)0x417f, (q15_t)0x417a, + (q15_t)0x4175, (q15_t)0x416f, (q15_t)0x416a, (q15_t)0x4164, (q15_t)0x415f, (q15_t)0x415a, (q15_t)0x4154, (q15_t)0x414f, + (q15_t)0x4149, (q15_t)0x4144, (q15_t)0x413f, (q15_t)0x4139, (q15_t)0x4134, (q15_t)0x412e, (q15_t)0x4129, (q15_t)0x4124, + (q15_t)0x411e, (q15_t)0x4119, (q15_t)0x4113, (q15_t)0x410e, (q15_t)0x4108, (q15_t)0x4103, (q15_t)0x40fe, (q15_t)0x40f8, + (q15_t)0x40f3, (q15_t)0x40ed, (q15_t)0x40e8, (q15_t)0x40e3, (q15_t)0x40dd, (q15_t)0x40d8, (q15_t)0x40d2, (q15_t)0x40cd, + (q15_t)0x40c8, (q15_t)0x40c2, (q15_t)0x40bd, (q15_t)0x40b7, (q15_t)0x40b2, (q15_t)0x40ac, (q15_t)0x40a7, (q15_t)0x40a2, + (q15_t)0x409c, (q15_t)0x4097, (q15_t)0x4091, (q15_t)0x408c, (q15_t)0x4086, (q15_t)0x4081, (q15_t)0x407c, (q15_t)0x4076, + (q15_t)0x4071, (q15_t)0x406b, (q15_t)0x4066, (q15_t)0x4060, (q15_t)0x405b, (q15_t)0x4056, (q15_t)0x4050, (q15_t)0x404b, + (q15_t)0x4045, (q15_t)0x4040, (q15_t)0x403a, (q15_t)0x4035, (q15_t)0x4030, (q15_t)0x402a, (q15_t)0x4025, (q15_t)0x401f, + (q15_t)0x401a, (q15_t)0x4014, (q15_t)0x400f, (q15_t)0x4009, (q15_t)0x4004, (q15_t)0x3fff, (q15_t)0x3ff9, (q15_t)0x3ff4, + (q15_t)0x3fee, (q15_t)0x3fe9, (q15_t)0x3fe3, (q15_t)0x3fde, (q15_t)0x3fd8, (q15_t)0x3fd3, (q15_t)0x3fce, (q15_t)0x3fc8, + (q15_t)0x3fc3, (q15_t)0x3fbd, (q15_t)0x3fb8, (q15_t)0x3fb2, (q15_t)0x3fad, (q15_t)0x3fa7, (q15_t)0x3fa2, (q15_t)0x3f9d, + (q15_t)0x3f97, (q15_t)0x3f92, (q15_t)0x3f8c, (q15_t)0x3f87, (q15_t)0x3f81, (q15_t)0x3f7c, (q15_t)0x3f76, (q15_t)0x3f71, + (q15_t)0x3f6b, (q15_t)0x3f66, (q15_t)0x3f61, (q15_t)0x3f5b, (q15_t)0x3f56, (q15_t)0x3f50, (q15_t)0x3f4b, (q15_t)0x3f45, + (q15_t)0x3f40, (q15_t)0x3f3a, (q15_t)0x3f35, (q15_t)0x3f2f, (q15_t)0x3f2a, (q15_t)0x3f24, (q15_t)0x3f1f, (q15_t)0x3f1a, + (q15_t)0x3f14, (q15_t)0x3f0f, (q15_t)0x3f09, (q15_t)0x3f04, (q15_t)0x3efe, (q15_t)0x3ef9, (q15_t)0x3ef3, (q15_t)0x3eee, + (q15_t)0x3ee8, (q15_t)0x3ee3, (q15_t)0x3edd, (q15_t)0x3ed8, (q15_t)0x3ed2, (q15_t)0x3ecd, (q15_t)0x3ec7, (q15_t)0x3ec2, + (q15_t)0x3ebd, (q15_t)0x3eb7, (q15_t)0x3eb2, (q15_t)0x3eac, (q15_t)0x3ea7, (q15_t)0x3ea1, (q15_t)0x3e9c, (q15_t)0x3e96, + (q15_t)0x3e91, (q15_t)0x3e8b, (q15_t)0x3e86, (q15_t)0x3e80, (q15_t)0x3e7b, (q15_t)0x3e75, (q15_t)0x3e70, (q15_t)0x3e6a, + (q15_t)0x3e65, (q15_t)0x3e5f, (q15_t)0x3e5a, (q15_t)0x3e54, (q15_t)0x3e4f, (q15_t)0x3e49, (q15_t)0x3e44, (q15_t)0x3e3e, + (q15_t)0x3e39, (q15_t)0x3e33, (q15_t)0x3e2e, (q15_t)0x3e28, (q15_t)0x3e23, (q15_t)0x3e1d, (q15_t)0x3e18, (q15_t)0x3e12, + (q15_t)0x3e0d, (q15_t)0x3e07, (q15_t)0x3e02, (q15_t)0x3dfc, (q15_t)0x3df7, (q15_t)0x3df1, (q15_t)0x3dec, (q15_t)0x3de6, + (q15_t)0x3de1, (q15_t)0x3ddb, (q15_t)0x3dd6, (q15_t)0x3dd0, (q15_t)0x3dcb, (q15_t)0x3dc5, (q15_t)0x3dc0, (q15_t)0x3dba, + (q15_t)0x3db5, (q15_t)0x3daf, (q15_t)0x3daa, (q15_t)0x3da4, (q15_t)0x3d9f, (q15_t)0x3d99, (q15_t)0x3d94, (q15_t)0x3d8e, + (q15_t)0x3d89, (q15_t)0x3d83, (q15_t)0x3d7e, (q15_t)0x3d78, (q15_t)0x3d73, (q15_t)0x3d6d, (q15_t)0x3d68, (q15_t)0x3d62, + (q15_t)0x3d5d, (q15_t)0x3d57, (q15_t)0x3d52, (q15_t)0x3d4c, (q15_t)0x3d47, (q15_t)0x3d41, (q15_t)0x3d3c, (q15_t)0x3d36, + (q15_t)0x3d31, (q15_t)0x3d2b, (q15_t)0x3d26, (q15_t)0x3d20, (q15_t)0x3d1b, (q15_t)0x3d15, (q15_t)0x3d10, (q15_t)0x3d0a, + (q15_t)0x3d04, (q15_t)0x3cff, (q15_t)0x3cf9, (q15_t)0x3cf4, (q15_t)0x3cee, (q15_t)0x3ce9, (q15_t)0x3ce3, (q15_t)0x3cde, + (q15_t)0x3cd8, (q15_t)0x3cd3, (q15_t)0x3ccd, (q15_t)0x3cc8, (q15_t)0x3cc2, (q15_t)0x3cbd, (q15_t)0x3cb7, (q15_t)0x3cb2, + (q15_t)0x3cac, (q15_t)0x3ca7, (q15_t)0x3ca1, (q15_t)0x3c9b, (q15_t)0x3c96, (q15_t)0x3c90, (q15_t)0x3c8b, (q15_t)0x3c85, + (q15_t)0x3c80, (q15_t)0x3c7a, (q15_t)0x3c75, (q15_t)0x3c6f, (q15_t)0x3c6a, (q15_t)0x3c64, (q15_t)0x3c5f, (q15_t)0x3c59, + (q15_t)0x3c53, (q15_t)0x3c4e, (q15_t)0x3c48, (q15_t)0x3c43, (q15_t)0x3c3d, (q15_t)0x3c38, (q15_t)0x3c32, (q15_t)0x3c2d, + (q15_t)0x3c27, (q15_t)0x3c22, (q15_t)0x3c1c, (q15_t)0x3c16, (q15_t)0x3c11, (q15_t)0x3c0b, (q15_t)0x3c06, (q15_t)0x3c00, + (q15_t)0x3bfb, (q15_t)0x3bf5, (q15_t)0x3bf0, (q15_t)0x3bea, (q15_t)0x3be5, (q15_t)0x3bdf, (q15_t)0x3bd9, (q15_t)0x3bd4, + (q15_t)0x3bce, (q15_t)0x3bc9, (q15_t)0x3bc3, (q15_t)0x3bbe, (q15_t)0x3bb8, (q15_t)0x3bb3, (q15_t)0x3bad, (q15_t)0x3ba7, + (q15_t)0x3ba2, (q15_t)0x3b9c, (q15_t)0x3b97, (q15_t)0x3b91, (q15_t)0x3b8c, (q15_t)0x3b86, (q15_t)0x3b80, (q15_t)0x3b7b, + (q15_t)0x3b75, (q15_t)0x3b70, (q15_t)0x3b6a, (q15_t)0x3b65, (q15_t)0x3b5f, (q15_t)0x3b5a, (q15_t)0x3b54, (q15_t)0x3b4e, + (q15_t)0x3b49, (q15_t)0x3b43, (q15_t)0x3b3e, (q15_t)0x3b38, (q15_t)0x3b33, (q15_t)0x3b2d, (q15_t)0x3b27, (q15_t)0x3b22, + (q15_t)0x3b1c, (q15_t)0x3b17, (q15_t)0x3b11, (q15_t)0x3b0c, (q15_t)0x3b06, (q15_t)0x3b00, (q15_t)0x3afb, (q15_t)0x3af5, + (q15_t)0x3af0, (q15_t)0x3aea, (q15_t)0x3ae4, (q15_t)0x3adf, (q15_t)0x3ad9, (q15_t)0x3ad4, (q15_t)0x3ace, (q15_t)0x3ac9, + (q15_t)0x3ac3, (q15_t)0x3abd, (q15_t)0x3ab8, (q15_t)0x3ab2, (q15_t)0x3aad, (q15_t)0x3aa7, (q15_t)0x3aa2, (q15_t)0x3a9c, + (q15_t)0x3a96, (q15_t)0x3a91, (q15_t)0x3a8b, (q15_t)0x3a86, (q15_t)0x3a80, (q15_t)0x3a7a, (q15_t)0x3a75, (q15_t)0x3a6f, + (q15_t)0x3a6a, (q15_t)0x3a64, (q15_t)0x3a5e, (q15_t)0x3a59, (q15_t)0x3a53, (q15_t)0x3a4e, (q15_t)0x3a48, (q15_t)0x3a42, + (q15_t)0x3a3d, (q15_t)0x3a37, (q15_t)0x3a32, (q15_t)0x3a2c, (q15_t)0x3a26, (q15_t)0x3a21, (q15_t)0x3a1b, (q15_t)0x3a16, + (q15_t)0x3a10, (q15_t)0x3a0b, (q15_t)0x3a05, (q15_t)0x39ff, (q15_t)0x39fa, (q15_t)0x39f4, (q15_t)0x39ee, (q15_t)0x39e9, + (q15_t)0x39e3, (q15_t)0x39de, (q15_t)0x39d8, (q15_t)0x39d2, (q15_t)0x39cd, (q15_t)0x39c7, (q15_t)0x39c2, (q15_t)0x39bc, + (q15_t)0x39b6, (q15_t)0x39b1, (q15_t)0x39ab, (q15_t)0x39a6, (q15_t)0x39a0, (q15_t)0x399a, (q15_t)0x3995, (q15_t)0x398f, + (q15_t)0x398a, (q15_t)0x3984, (q15_t)0x397e, (q15_t)0x3979, (q15_t)0x3973, (q15_t)0x396d, (q15_t)0x3968, (q15_t)0x3962, + (q15_t)0x395d, (q15_t)0x3957, (q15_t)0x3951, (q15_t)0x394c, (q15_t)0x3946, (q15_t)0x3941, (q15_t)0x393b, (q15_t)0x3935, + (q15_t)0x3930, (q15_t)0x392a, (q15_t)0x3924, (q15_t)0x391f, (q15_t)0x3919, (q15_t)0x3914, (q15_t)0x390e, (q15_t)0x3908, + (q15_t)0x3903, (q15_t)0x38fd, (q15_t)0x38f7, (q15_t)0x38f2, (q15_t)0x38ec, (q15_t)0x38e7, (q15_t)0x38e1, (q15_t)0x38db, + (q15_t)0x38d6, (q15_t)0x38d0, (q15_t)0x38ca, (q15_t)0x38c5, (q15_t)0x38bf, (q15_t)0x38ba, (q15_t)0x38b4, (q15_t)0x38ae, + (q15_t)0x38a9, (q15_t)0x38a3, (q15_t)0x389d, (q15_t)0x3898, (q15_t)0x3892, (q15_t)0x388c, (q15_t)0x3887, (q15_t)0x3881, + (q15_t)0x387c, (q15_t)0x3876, (q15_t)0x3870, (q15_t)0x386b, (q15_t)0x3865, (q15_t)0x385f, (q15_t)0x385a, (q15_t)0x3854, + (q15_t)0x384e, (q15_t)0x3849, (q15_t)0x3843, (q15_t)0x383d, (q15_t)0x3838, (q15_t)0x3832, (q15_t)0x382d, (q15_t)0x3827, + (q15_t)0x3821, (q15_t)0x381c, (q15_t)0x3816, (q15_t)0x3810, (q15_t)0x380b, (q15_t)0x3805, (q15_t)0x37ff, (q15_t)0x37fa, + (q15_t)0x37f4, (q15_t)0x37ee, (q15_t)0x37e9, (q15_t)0x37e3, (q15_t)0x37dd, (q15_t)0x37d8, (q15_t)0x37d2, (q15_t)0x37cc, + (q15_t)0x37c7, (q15_t)0x37c1, (q15_t)0x37bc, (q15_t)0x37b6, (q15_t)0x37b0, (q15_t)0x37ab, (q15_t)0x37a5, (q15_t)0x379f, + (q15_t)0x379a, (q15_t)0x3794, (q15_t)0x378e, (q15_t)0x3789, (q15_t)0x3783, (q15_t)0x377d, (q15_t)0x3778, (q15_t)0x3772, + (q15_t)0x376c, (q15_t)0x3767, (q15_t)0x3761, (q15_t)0x375b, (q15_t)0x3756, (q15_t)0x3750, (q15_t)0x374a, (q15_t)0x3745, + (q15_t)0x373f, (q15_t)0x3739, (q15_t)0x3734, (q15_t)0x372e, (q15_t)0x3728, (q15_t)0x3723, (q15_t)0x371d, (q15_t)0x3717, + (q15_t)0x3712, (q15_t)0x370c, (q15_t)0x3706, (q15_t)0x3701, (q15_t)0x36fb, (q15_t)0x36f5, (q15_t)0x36f0, (q15_t)0x36ea, + (q15_t)0x36e4, (q15_t)0x36df, (q15_t)0x36d9, (q15_t)0x36d3, (q15_t)0x36ce, (q15_t)0x36c8, (q15_t)0x36c2, (q15_t)0x36bc, + (q15_t)0x36b7, (q15_t)0x36b1, (q15_t)0x36ab, (q15_t)0x36a6, (q15_t)0x36a0, (q15_t)0x369a, (q15_t)0x3695, (q15_t)0x368f, + (q15_t)0x3689, (q15_t)0x3684, (q15_t)0x367e, (q15_t)0x3678, (q15_t)0x3673, (q15_t)0x366d, (q15_t)0x3667, (q15_t)0x3662, + (q15_t)0x365c, (q15_t)0x3656, (q15_t)0x3650, (q15_t)0x364b, (q15_t)0x3645, (q15_t)0x363f, (q15_t)0x363a, (q15_t)0x3634, + (q15_t)0x362e, (q15_t)0x3629, (q15_t)0x3623, (q15_t)0x361d, (q15_t)0x3618, (q15_t)0x3612, (q15_t)0x360c, (q15_t)0x3606, + (q15_t)0x3601, (q15_t)0x35fb, (q15_t)0x35f5, (q15_t)0x35f0, (q15_t)0x35ea, (q15_t)0x35e4, (q15_t)0x35df, (q15_t)0x35d9, + (q15_t)0x35d3, (q15_t)0x35cd, (q15_t)0x35c8, (q15_t)0x35c2, (q15_t)0x35bc, (q15_t)0x35b7, (q15_t)0x35b1, (q15_t)0x35ab, + (q15_t)0x35a6, (q15_t)0x35a0, (q15_t)0x359a, (q15_t)0x3594, (q15_t)0x358f, (q15_t)0x3589, (q15_t)0x3583, (q15_t)0x357e, + (q15_t)0x3578, (q15_t)0x3572, (q15_t)0x356c, (q15_t)0x3567, (q15_t)0x3561, (q15_t)0x355b, (q15_t)0x3556, (q15_t)0x3550, + (q15_t)0x354a, (q15_t)0x3544, (q15_t)0x353f, (q15_t)0x3539, (q15_t)0x3533, (q15_t)0x352e, (q15_t)0x3528, (q15_t)0x3522, + (q15_t)0x351c, (q15_t)0x3517, (q15_t)0x3511, (q15_t)0x350b, (q15_t)0x3506, (q15_t)0x3500, (q15_t)0x34fa, (q15_t)0x34f4, + (q15_t)0x34ef, (q15_t)0x34e9, (q15_t)0x34e3, (q15_t)0x34de, (q15_t)0x34d8, (q15_t)0x34d2, (q15_t)0x34cc, (q15_t)0x34c7, + (q15_t)0x34c1, (q15_t)0x34bb, (q15_t)0x34b6, (q15_t)0x34b0, (q15_t)0x34aa, (q15_t)0x34a4, (q15_t)0x349f, (q15_t)0x3499, + (q15_t)0x3493, (q15_t)0x348d, (q15_t)0x3488, (q15_t)0x3482, (q15_t)0x347c, (q15_t)0x3476, (q15_t)0x3471, (q15_t)0x346b, + (q15_t)0x3465, (q15_t)0x3460, (q15_t)0x345a, (q15_t)0x3454, (q15_t)0x344e, (q15_t)0x3449, (q15_t)0x3443, (q15_t)0x343d, + (q15_t)0x3437, (q15_t)0x3432, (q15_t)0x342c, (q15_t)0x3426, (q15_t)0x3420, (q15_t)0x341b, (q15_t)0x3415, (q15_t)0x340f, + (q15_t)0x340a, (q15_t)0x3404, (q15_t)0x33fe, (q15_t)0x33f8, (q15_t)0x33f3, (q15_t)0x33ed, (q15_t)0x33e7, (q15_t)0x33e1, + (q15_t)0x33dc, (q15_t)0x33d6, (q15_t)0x33d0, (q15_t)0x33ca, (q15_t)0x33c5, (q15_t)0x33bf, (q15_t)0x33b9, (q15_t)0x33b3, + (q15_t)0x33ae, (q15_t)0x33a8, (q15_t)0x33a2, (q15_t)0x339c, (q15_t)0x3397, (q15_t)0x3391, (q15_t)0x338b, (q15_t)0x3385, + (q15_t)0x3380, (q15_t)0x337a, (q15_t)0x3374, (q15_t)0x336e, (q15_t)0x3369, (q15_t)0x3363, (q15_t)0x335d, (q15_t)0x3357, + (q15_t)0x3352, (q15_t)0x334c, (q15_t)0x3346, (q15_t)0x3340, (q15_t)0x333b, (q15_t)0x3335, (q15_t)0x332f, (q15_t)0x3329, + (q15_t)0x3324, (q15_t)0x331e, (q15_t)0x3318, (q15_t)0x3312, (q15_t)0x330c, (q15_t)0x3307, (q15_t)0x3301, (q15_t)0x32fb, + (q15_t)0x32f5, (q15_t)0x32f0, (q15_t)0x32ea, (q15_t)0x32e4, (q15_t)0x32de, (q15_t)0x32d9, (q15_t)0x32d3, (q15_t)0x32cd, + (q15_t)0x32c7, (q15_t)0x32c2, (q15_t)0x32bc, (q15_t)0x32b6, (q15_t)0x32b0, (q15_t)0x32aa, (q15_t)0x32a5, (q15_t)0x329f, + (q15_t)0x3299, (q15_t)0x3293, (q15_t)0x328e, (q15_t)0x3288, (q15_t)0x3282, (q15_t)0x327c, (q15_t)0x3276, (q15_t)0x3271, + (q15_t)0x326b, (q15_t)0x3265, (q15_t)0x325f, (q15_t)0x325a, (q15_t)0x3254, (q15_t)0x324e, (q15_t)0x3248, (q15_t)0x3243, + (q15_t)0x323d, (q15_t)0x3237, (q15_t)0x3231, (q15_t)0x322b, (q15_t)0x3226, (q15_t)0x3220, (q15_t)0x321a, (q15_t)0x3214, + (q15_t)0x320e, (q15_t)0x3209, (q15_t)0x3203, (q15_t)0x31fd, (q15_t)0x31f7, (q15_t)0x31f2, (q15_t)0x31ec, (q15_t)0x31e6, + (q15_t)0x31e0, (q15_t)0x31da, (q15_t)0x31d5, (q15_t)0x31cf, (q15_t)0x31c9, (q15_t)0x31c3, (q15_t)0x31bd, (q15_t)0x31b8, + (q15_t)0x31b2, (q15_t)0x31ac, (q15_t)0x31a6, (q15_t)0x31a1, (q15_t)0x319b, (q15_t)0x3195, (q15_t)0x318f, (q15_t)0x3189, + (q15_t)0x3184, (q15_t)0x317e, (q15_t)0x3178, (q15_t)0x3172, (q15_t)0x316c, (q15_t)0x3167, (q15_t)0x3161, (q15_t)0x315b, + (q15_t)0x3155, (q15_t)0x314f, (q15_t)0x314a, (q15_t)0x3144, (q15_t)0x313e, (q15_t)0x3138, (q15_t)0x3132, (q15_t)0x312d, + (q15_t)0x3127, (q15_t)0x3121, (q15_t)0x311b, (q15_t)0x3115, (q15_t)0x3110, (q15_t)0x310a, (q15_t)0x3104, (q15_t)0x30fe, + (q15_t)0x30f8, (q15_t)0x30f3, (q15_t)0x30ed, (q15_t)0x30e7, (q15_t)0x30e1, (q15_t)0x30db, (q15_t)0x30d6, (q15_t)0x30d0, + (q15_t)0x30ca, (q15_t)0x30c4, (q15_t)0x30be, (q15_t)0x30b8, (q15_t)0x30b3, (q15_t)0x30ad, (q15_t)0x30a7, (q15_t)0x30a1, + (q15_t)0x309b, (q15_t)0x3096, (q15_t)0x3090, (q15_t)0x308a, (q15_t)0x3084, (q15_t)0x307e, (q15_t)0x3079, (q15_t)0x3073, + (q15_t)0x306d, (q15_t)0x3067, (q15_t)0x3061, (q15_t)0x305b, (q15_t)0x3056, (q15_t)0x3050, (q15_t)0x304a, (q15_t)0x3044, + (q15_t)0x303e, (q15_t)0x3039, (q15_t)0x3033, (q15_t)0x302d, (q15_t)0x3027, (q15_t)0x3021, (q15_t)0x301b, (q15_t)0x3016, + (q15_t)0x3010, (q15_t)0x300a, (q15_t)0x3004, (q15_t)0x2ffe, (q15_t)0x2ff8, (q15_t)0x2ff3, (q15_t)0x2fed, (q15_t)0x2fe7, + (q15_t)0x2fe1, (q15_t)0x2fdb, (q15_t)0x2fd6, (q15_t)0x2fd0, (q15_t)0x2fca, (q15_t)0x2fc4, (q15_t)0x2fbe, (q15_t)0x2fb8, + (q15_t)0x2fb3, (q15_t)0x2fad, (q15_t)0x2fa7, (q15_t)0x2fa1, (q15_t)0x2f9b, (q15_t)0x2f95, (q15_t)0x2f90, (q15_t)0x2f8a, + (q15_t)0x2f84, (q15_t)0x2f7e, (q15_t)0x2f78, (q15_t)0x2f72, (q15_t)0x2f6d, (q15_t)0x2f67, (q15_t)0x2f61, (q15_t)0x2f5b, + (q15_t)0x2f55, (q15_t)0x2f4f, (q15_t)0x2f4a, (q15_t)0x2f44, (q15_t)0x2f3e, (q15_t)0x2f38, (q15_t)0x2f32, (q15_t)0x2f2c, + (q15_t)0x2f27, (q15_t)0x2f21, (q15_t)0x2f1b, (q15_t)0x2f15, (q15_t)0x2f0f, (q15_t)0x2f09, (q15_t)0x2f03, (q15_t)0x2efe, + (q15_t)0x2ef8, (q15_t)0x2ef2, (q15_t)0x2eec, (q15_t)0x2ee6, (q15_t)0x2ee0, (q15_t)0x2edb, (q15_t)0x2ed5, (q15_t)0x2ecf, + (q15_t)0x2ec9, (q15_t)0x2ec3, (q15_t)0x2ebd, (q15_t)0x2eb7, (q15_t)0x2eb2, (q15_t)0x2eac, (q15_t)0x2ea6, (q15_t)0x2ea0, + (q15_t)0x2e9a, (q15_t)0x2e94, (q15_t)0x2e8e, (q15_t)0x2e89, (q15_t)0x2e83, (q15_t)0x2e7d, (q15_t)0x2e77, (q15_t)0x2e71, + (q15_t)0x2e6b, (q15_t)0x2e65, (q15_t)0x2e60, (q15_t)0x2e5a, (q15_t)0x2e54, (q15_t)0x2e4e, (q15_t)0x2e48, (q15_t)0x2e42, + (q15_t)0x2e3c, (q15_t)0x2e37, (q15_t)0x2e31, (q15_t)0x2e2b, (q15_t)0x2e25, (q15_t)0x2e1f, (q15_t)0x2e19, (q15_t)0x2e13, + (q15_t)0x2e0e, (q15_t)0x2e08, (q15_t)0x2e02, (q15_t)0x2dfc, (q15_t)0x2df6, (q15_t)0x2df0, (q15_t)0x2dea, (q15_t)0x2de5, + (q15_t)0x2ddf, (q15_t)0x2dd9, (q15_t)0x2dd3, (q15_t)0x2dcd, (q15_t)0x2dc7, (q15_t)0x2dc1, (q15_t)0x2dbb, (q15_t)0x2db6, + (q15_t)0x2db0, (q15_t)0x2daa, (q15_t)0x2da4, (q15_t)0x2d9e, (q15_t)0x2d98, (q15_t)0x2d92, (q15_t)0x2d8d, (q15_t)0x2d87, + (q15_t)0x2d81, (q15_t)0x2d7b, (q15_t)0x2d75, (q15_t)0x2d6f, (q15_t)0x2d69, (q15_t)0x2d63, (q15_t)0x2d5e, (q15_t)0x2d58, + (q15_t)0x2d52, (q15_t)0x2d4c, (q15_t)0x2d46, (q15_t)0x2d40, (q15_t)0x2d3a, (q15_t)0x2d34, (q15_t)0x2d2f, (q15_t)0x2d29, + (q15_t)0x2d23, (q15_t)0x2d1d, (q15_t)0x2d17, (q15_t)0x2d11, (q15_t)0x2d0b, (q15_t)0x2d05, (q15_t)0x2cff, (q15_t)0x2cfa, + (q15_t)0x2cf4, (q15_t)0x2cee, (q15_t)0x2ce8, (q15_t)0x2ce2, (q15_t)0x2cdc, (q15_t)0x2cd6, (q15_t)0x2cd0, (q15_t)0x2ccb, + (q15_t)0x2cc5, (q15_t)0x2cbf, (q15_t)0x2cb9, (q15_t)0x2cb3, (q15_t)0x2cad, (q15_t)0x2ca7, (q15_t)0x2ca1, (q15_t)0x2c9b, + (q15_t)0x2c96, (q15_t)0x2c90, (q15_t)0x2c8a, (q15_t)0x2c84, (q15_t)0x2c7e, (q15_t)0x2c78, (q15_t)0x2c72, (q15_t)0x2c6c, + (q15_t)0x2c66, (q15_t)0x2c61, (q15_t)0x2c5b, (q15_t)0x2c55, (q15_t)0x2c4f, (q15_t)0x2c49, (q15_t)0x2c43, (q15_t)0x2c3d, + (q15_t)0x2c37, (q15_t)0x2c31, (q15_t)0x2c2b, (q15_t)0x2c26, (q15_t)0x2c20, (q15_t)0x2c1a, (q15_t)0x2c14, (q15_t)0x2c0e, + (q15_t)0x2c08, (q15_t)0x2c02, (q15_t)0x2bfc, (q15_t)0x2bf6, (q15_t)0x2bf0, (q15_t)0x2beb, (q15_t)0x2be5, (q15_t)0x2bdf, + (q15_t)0x2bd9, (q15_t)0x2bd3, (q15_t)0x2bcd, (q15_t)0x2bc7, (q15_t)0x2bc1, (q15_t)0x2bbb, (q15_t)0x2bb5, (q15_t)0x2bb0, + (q15_t)0x2baa, (q15_t)0x2ba4, (q15_t)0x2b9e, (q15_t)0x2b98, (q15_t)0x2b92, (q15_t)0x2b8c, (q15_t)0x2b86, (q15_t)0x2b80, + (q15_t)0x2b7a, (q15_t)0x2b74, (q15_t)0x2b6f, (q15_t)0x2b69, (q15_t)0x2b63, (q15_t)0x2b5d, (q15_t)0x2b57, (q15_t)0x2b51, + (q15_t)0x2b4b, (q15_t)0x2b45, (q15_t)0x2b3f, (q15_t)0x2b39, (q15_t)0x2b33, (q15_t)0x2b2d, (q15_t)0x2b28, (q15_t)0x2b22, + (q15_t)0x2b1c, (q15_t)0x2b16, (q15_t)0x2b10, (q15_t)0x2b0a, (q15_t)0x2b04, (q15_t)0x2afe, (q15_t)0x2af8, (q15_t)0x2af2, + (q15_t)0x2aec, (q15_t)0x2ae6, (q15_t)0x2ae1, (q15_t)0x2adb, (q15_t)0x2ad5, (q15_t)0x2acf, (q15_t)0x2ac9, (q15_t)0x2ac3, + (q15_t)0x2abd, (q15_t)0x2ab7, (q15_t)0x2ab1, (q15_t)0x2aab, (q15_t)0x2aa5, (q15_t)0x2a9f, (q15_t)0x2a99, (q15_t)0x2a94, + (q15_t)0x2a8e, (q15_t)0x2a88, (q15_t)0x2a82, (q15_t)0x2a7c, (q15_t)0x2a76, (q15_t)0x2a70, (q15_t)0x2a6a, (q15_t)0x2a64, + (q15_t)0x2a5e, (q15_t)0x2a58, (q15_t)0x2a52, (q15_t)0x2a4c, (q15_t)0x2a47, (q15_t)0x2a41, (q15_t)0x2a3b, (q15_t)0x2a35, + (q15_t)0x2a2f, (q15_t)0x2a29, (q15_t)0x2a23, (q15_t)0x2a1d, (q15_t)0x2a17, (q15_t)0x2a11, (q15_t)0x2a0b, (q15_t)0x2a05, + (q15_t)0x29ff, (q15_t)0x29f9, (q15_t)0x29f3, (q15_t)0x29ee, (q15_t)0x29e8, (q15_t)0x29e2, (q15_t)0x29dc, (q15_t)0x29d6, + (q15_t)0x29d0, (q15_t)0x29ca, (q15_t)0x29c4, (q15_t)0x29be, (q15_t)0x29b8, (q15_t)0x29b2, (q15_t)0x29ac, (q15_t)0x29a6, + (q15_t)0x29a0, (q15_t)0x299a, (q15_t)0x2994, (q15_t)0x298e, (q15_t)0x2989, (q15_t)0x2983, (q15_t)0x297d, (q15_t)0x2977, + (q15_t)0x2971, (q15_t)0x296b, (q15_t)0x2965, (q15_t)0x295f, (q15_t)0x2959, (q15_t)0x2953, (q15_t)0x294d, (q15_t)0x2947, + (q15_t)0x2941, (q15_t)0x293b, (q15_t)0x2935, (q15_t)0x292f, (q15_t)0x2929, (q15_t)0x2923, (q15_t)0x291d, (q15_t)0x2918, + (q15_t)0x2912, (q15_t)0x290c, (q15_t)0x2906, (q15_t)0x2900, (q15_t)0x28fa, (q15_t)0x28f4, (q15_t)0x28ee, (q15_t)0x28e8, + (q15_t)0x28e2, (q15_t)0x28dc, (q15_t)0x28d6, (q15_t)0x28d0, (q15_t)0x28ca, (q15_t)0x28c4, (q15_t)0x28be, (q15_t)0x28b8, + (q15_t)0x28b2, (q15_t)0x28ac, (q15_t)0x28a6, (q15_t)0x28a0, (q15_t)0x289a, (q15_t)0x2895, (q15_t)0x288f, (q15_t)0x2889, + (q15_t)0x2883, (q15_t)0x287d, (q15_t)0x2877, (q15_t)0x2871, (q15_t)0x286b, (q15_t)0x2865, (q15_t)0x285f, (q15_t)0x2859, + (q15_t)0x2853, (q15_t)0x284d, (q15_t)0x2847, (q15_t)0x2841, (q15_t)0x283b, (q15_t)0x2835, (q15_t)0x282f, (q15_t)0x2829, + (q15_t)0x2823, (q15_t)0x281d, (q15_t)0x2817, (q15_t)0x2811, (q15_t)0x280b, (q15_t)0x2805, (q15_t)0x27ff, (q15_t)0x27f9, + (q15_t)0x27f3, (q15_t)0x27ee, (q15_t)0x27e8, (q15_t)0x27e2, (q15_t)0x27dc, (q15_t)0x27d6, (q15_t)0x27d0, (q15_t)0x27ca, + (q15_t)0x27c4, (q15_t)0x27be, (q15_t)0x27b8, (q15_t)0x27b2, (q15_t)0x27ac, (q15_t)0x27a6, (q15_t)0x27a0, (q15_t)0x279a, + (q15_t)0x2794, (q15_t)0x278e, (q15_t)0x2788, (q15_t)0x2782, (q15_t)0x277c, (q15_t)0x2776, (q15_t)0x2770, (q15_t)0x276a, + (q15_t)0x2764, (q15_t)0x275e, (q15_t)0x2758, (q15_t)0x2752, (q15_t)0x274c, (q15_t)0x2746, (q15_t)0x2740, (q15_t)0x273a, + (q15_t)0x2734, (q15_t)0x272e, (q15_t)0x2728, (q15_t)0x2722, (q15_t)0x271c, (q15_t)0x2716, (q15_t)0x2710, (q15_t)0x270a, + (q15_t)0x2704, (q15_t)0x26fe, (q15_t)0x26f8, (q15_t)0x26f2, (q15_t)0x26ec, (q15_t)0x26e7, (q15_t)0x26e1, (q15_t)0x26db, + (q15_t)0x26d5, (q15_t)0x26cf, (q15_t)0x26c9, (q15_t)0x26c3, (q15_t)0x26bd, (q15_t)0x26b7, (q15_t)0x26b1, (q15_t)0x26ab, + (q15_t)0x26a5, (q15_t)0x269f, (q15_t)0x2699, (q15_t)0x2693, (q15_t)0x268d, (q15_t)0x2687, (q15_t)0x2681, (q15_t)0x267b, + (q15_t)0x2675, (q15_t)0x266f, (q15_t)0x2669, (q15_t)0x2663, (q15_t)0x265d, (q15_t)0x2657, (q15_t)0x2651, (q15_t)0x264b, + (q15_t)0x2645, (q15_t)0x263f, (q15_t)0x2639, (q15_t)0x2633, (q15_t)0x262d, (q15_t)0x2627, (q15_t)0x2621, (q15_t)0x261b, + (q15_t)0x2615, (q15_t)0x260f, (q15_t)0x2609, (q15_t)0x2603, (q15_t)0x25fd, (q15_t)0x25f7, (q15_t)0x25f1, (q15_t)0x25eb, + (q15_t)0x25e5, (q15_t)0x25df, (q15_t)0x25d9, (q15_t)0x25d3, (q15_t)0x25cd, (q15_t)0x25c7, (q15_t)0x25c1, (q15_t)0x25bb, + (q15_t)0x25b5, (q15_t)0x25af, (q15_t)0x25a9, (q15_t)0x25a3, (q15_t)0x259d, (q15_t)0x2597, (q15_t)0x2591, (q15_t)0x258b, + (q15_t)0x2585, (q15_t)0x257f, (q15_t)0x2579, (q15_t)0x2573, (q15_t)0x256d, (q15_t)0x2567, (q15_t)0x2561, (q15_t)0x255b, + (q15_t)0x2555, (q15_t)0x254f, (q15_t)0x2549, (q15_t)0x2543, (q15_t)0x253d, (q15_t)0x2537, (q15_t)0x2531, (q15_t)0x252b, + (q15_t)0x2525, (q15_t)0x251f, (q15_t)0x2519, (q15_t)0x2513, (q15_t)0x250c, (q15_t)0x2506, (q15_t)0x2500, (q15_t)0x24fa, + (q15_t)0x24f4, (q15_t)0x24ee, (q15_t)0x24e8, (q15_t)0x24e2, (q15_t)0x24dc, (q15_t)0x24d6, (q15_t)0x24d0, (q15_t)0x24ca, + (q15_t)0x24c4, (q15_t)0x24be, (q15_t)0x24b8, (q15_t)0x24b2, (q15_t)0x24ac, (q15_t)0x24a6, (q15_t)0x24a0, (q15_t)0x249a, + (q15_t)0x2494, (q15_t)0x248e, (q15_t)0x2488, (q15_t)0x2482, (q15_t)0x247c, (q15_t)0x2476, (q15_t)0x2470, (q15_t)0x246a, + (q15_t)0x2464, (q15_t)0x245e, (q15_t)0x2458, (q15_t)0x2452, (q15_t)0x244c, (q15_t)0x2446, (q15_t)0x2440, (q15_t)0x243a, + (q15_t)0x2434, (q15_t)0x242e, (q15_t)0x2428, (q15_t)0x2422, (q15_t)0x241c, (q15_t)0x2416, (q15_t)0x2410, (q15_t)0x240a, + (q15_t)0x2404, (q15_t)0x23fd, (q15_t)0x23f7, (q15_t)0x23f1, (q15_t)0x23eb, (q15_t)0x23e5, (q15_t)0x23df, (q15_t)0x23d9, + (q15_t)0x23d3, (q15_t)0x23cd, (q15_t)0x23c7, (q15_t)0x23c1, (q15_t)0x23bb, (q15_t)0x23b5, (q15_t)0x23af, (q15_t)0x23a9, + (q15_t)0x23a3, (q15_t)0x239d, (q15_t)0x2397, (q15_t)0x2391, (q15_t)0x238b, (q15_t)0x2385, (q15_t)0x237f, (q15_t)0x2379, + (q15_t)0x2373, (q15_t)0x236d, (q15_t)0x2367, (q15_t)0x2361, (q15_t)0x235b, (q15_t)0x2355, (q15_t)0x234e, (q15_t)0x2348, + (q15_t)0x2342, (q15_t)0x233c, (q15_t)0x2336, (q15_t)0x2330, (q15_t)0x232a, (q15_t)0x2324, (q15_t)0x231e, (q15_t)0x2318, + (q15_t)0x2312, (q15_t)0x230c, (q15_t)0x2306, (q15_t)0x2300, (q15_t)0x22fa, (q15_t)0x22f4, (q15_t)0x22ee, (q15_t)0x22e8, + (q15_t)0x22e2, (q15_t)0x22dc, (q15_t)0x22d6, (q15_t)0x22d0, (q15_t)0x22ca, (q15_t)0x22c4, (q15_t)0x22bd, (q15_t)0x22b7, + (q15_t)0x22b1, (q15_t)0x22ab, (q15_t)0x22a5, (q15_t)0x229f, (q15_t)0x2299, (q15_t)0x2293, (q15_t)0x228d, (q15_t)0x2287, + (q15_t)0x2281, (q15_t)0x227b, (q15_t)0x2275, (q15_t)0x226f, (q15_t)0x2269, (q15_t)0x2263, (q15_t)0x225d, (q15_t)0x2257, + (q15_t)0x2251, (q15_t)0x224a, (q15_t)0x2244, (q15_t)0x223e, (q15_t)0x2238, (q15_t)0x2232, (q15_t)0x222c, (q15_t)0x2226, + (q15_t)0x2220, (q15_t)0x221a, (q15_t)0x2214, (q15_t)0x220e, (q15_t)0x2208, (q15_t)0x2202, (q15_t)0x21fc, (q15_t)0x21f6, + (q15_t)0x21f0, (q15_t)0x21ea, (q15_t)0x21e4, (q15_t)0x21dd, (q15_t)0x21d7, (q15_t)0x21d1, (q15_t)0x21cb, (q15_t)0x21c5, + (q15_t)0x21bf, (q15_t)0x21b9, (q15_t)0x21b3, (q15_t)0x21ad, (q15_t)0x21a7, (q15_t)0x21a1, (q15_t)0x219b, (q15_t)0x2195, + (q15_t)0x218f, (q15_t)0x2189, (q15_t)0x2183, (q15_t)0x217c, (q15_t)0x2176, (q15_t)0x2170, (q15_t)0x216a, (q15_t)0x2164, + (q15_t)0x215e, (q15_t)0x2158, (q15_t)0x2152, (q15_t)0x214c, (q15_t)0x2146, (q15_t)0x2140, (q15_t)0x213a, (q15_t)0x2134, + (q15_t)0x212e, (q15_t)0x2128, (q15_t)0x2121, (q15_t)0x211b, (q15_t)0x2115, (q15_t)0x210f, (q15_t)0x2109, (q15_t)0x2103, + (q15_t)0x20fd, (q15_t)0x20f7, (q15_t)0x20f1, (q15_t)0x20eb, (q15_t)0x20e5, (q15_t)0x20df, (q15_t)0x20d9, (q15_t)0x20d3, + (q15_t)0x20cc, (q15_t)0x20c6, (q15_t)0x20c0, (q15_t)0x20ba, (q15_t)0x20b4, (q15_t)0x20ae, (q15_t)0x20a8, (q15_t)0x20a2, + (q15_t)0x209c, (q15_t)0x2096, (q15_t)0x2090, (q15_t)0x208a, (q15_t)0x2084, (q15_t)0x207e, (q15_t)0x2077, (q15_t)0x2071, + (q15_t)0x206b, (q15_t)0x2065, (q15_t)0x205f, (q15_t)0x2059, (q15_t)0x2053, (q15_t)0x204d, (q15_t)0x2047, (q15_t)0x2041, + (q15_t)0x203b, (q15_t)0x2035, (q15_t)0x202e, (q15_t)0x2028, (q15_t)0x2022, (q15_t)0x201c, (q15_t)0x2016, (q15_t)0x2010, + (q15_t)0x200a, (q15_t)0x2004, (q15_t)0x1ffe, (q15_t)0x1ff8, (q15_t)0x1ff2, (q15_t)0x1fec, (q15_t)0x1fe5, (q15_t)0x1fdf, + (q15_t)0x1fd9, (q15_t)0x1fd3, (q15_t)0x1fcd, (q15_t)0x1fc7, (q15_t)0x1fc1, (q15_t)0x1fbb, (q15_t)0x1fb5, (q15_t)0x1faf, + (q15_t)0x1fa9, (q15_t)0x1fa3, (q15_t)0x1f9c, (q15_t)0x1f96, (q15_t)0x1f90, (q15_t)0x1f8a, (q15_t)0x1f84, (q15_t)0x1f7e, + (q15_t)0x1f78, (q15_t)0x1f72, (q15_t)0x1f6c, (q15_t)0x1f66, (q15_t)0x1f60, (q15_t)0x1f59, (q15_t)0x1f53, (q15_t)0x1f4d, + (q15_t)0x1f47, (q15_t)0x1f41, (q15_t)0x1f3b, (q15_t)0x1f35, (q15_t)0x1f2f, (q15_t)0x1f29, (q15_t)0x1f23, (q15_t)0x1f1d, + (q15_t)0x1f16, (q15_t)0x1f10, (q15_t)0x1f0a, (q15_t)0x1f04, (q15_t)0x1efe, (q15_t)0x1ef8, (q15_t)0x1ef2, (q15_t)0x1eec, + (q15_t)0x1ee6, (q15_t)0x1ee0, (q15_t)0x1ed9, (q15_t)0x1ed3, (q15_t)0x1ecd, (q15_t)0x1ec7, (q15_t)0x1ec1, (q15_t)0x1ebb, + (q15_t)0x1eb5, (q15_t)0x1eaf, (q15_t)0x1ea9, (q15_t)0x1ea3, (q15_t)0x1e9c, (q15_t)0x1e96, (q15_t)0x1e90, (q15_t)0x1e8a, + (q15_t)0x1e84, (q15_t)0x1e7e, (q15_t)0x1e78, (q15_t)0x1e72, (q15_t)0x1e6c, (q15_t)0x1e66, (q15_t)0x1e5f, (q15_t)0x1e59, + (q15_t)0x1e53, (q15_t)0x1e4d, (q15_t)0x1e47, (q15_t)0x1e41, (q15_t)0x1e3b, (q15_t)0x1e35, (q15_t)0x1e2f, (q15_t)0x1e29, + (q15_t)0x1e22, (q15_t)0x1e1c, (q15_t)0x1e16, (q15_t)0x1e10, (q15_t)0x1e0a, (q15_t)0x1e04, (q15_t)0x1dfe, (q15_t)0x1df8, + (q15_t)0x1df2, (q15_t)0x1deb, (q15_t)0x1de5, (q15_t)0x1ddf, (q15_t)0x1dd9, (q15_t)0x1dd3, (q15_t)0x1dcd, (q15_t)0x1dc7, + (q15_t)0x1dc1, (q15_t)0x1dbb, (q15_t)0x1db4, (q15_t)0x1dae, (q15_t)0x1da8, (q15_t)0x1da2, (q15_t)0x1d9c, (q15_t)0x1d96, + (q15_t)0x1d90, (q15_t)0x1d8a, (q15_t)0x1d84, (q15_t)0x1d7d, (q15_t)0x1d77, (q15_t)0x1d71, (q15_t)0x1d6b, (q15_t)0x1d65, + (q15_t)0x1d5f, (q15_t)0x1d59, (q15_t)0x1d53, (q15_t)0x1d4c, (q15_t)0x1d46, (q15_t)0x1d40, (q15_t)0x1d3a, (q15_t)0x1d34, + (q15_t)0x1d2e, (q15_t)0x1d28, (q15_t)0x1d22, (q15_t)0x1d1c, (q15_t)0x1d15, (q15_t)0x1d0f, (q15_t)0x1d09, (q15_t)0x1d03, + (q15_t)0x1cfd, (q15_t)0x1cf7, (q15_t)0x1cf1, (q15_t)0x1ceb, (q15_t)0x1ce4, (q15_t)0x1cde, (q15_t)0x1cd8, (q15_t)0x1cd2, + (q15_t)0x1ccc, (q15_t)0x1cc6, (q15_t)0x1cc0, (q15_t)0x1cba, (q15_t)0x1cb3, (q15_t)0x1cad, (q15_t)0x1ca7, (q15_t)0x1ca1, + (q15_t)0x1c9b, (q15_t)0x1c95, (q15_t)0x1c8f, (q15_t)0x1c89, (q15_t)0x1c83, (q15_t)0x1c7c, (q15_t)0x1c76, (q15_t)0x1c70, + (q15_t)0x1c6a, (q15_t)0x1c64, (q15_t)0x1c5e, (q15_t)0x1c58, (q15_t)0x1c51, (q15_t)0x1c4b, (q15_t)0x1c45, (q15_t)0x1c3f, + (q15_t)0x1c39, (q15_t)0x1c33, (q15_t)0x1c2d, (q15_t)0x1c27, (q15_t)0x1c20, (q15_t)0x1c1a, (q15_t)0x1c14, (q15_t)0x1c0e, + (q15_t)0x1c08, (q15_t)0x1c02, (q15_t)0x1bfc, (q15_t)0x1bf6, (q15_t)0x1bef, (q15_t)0x1be9, (q15_t)0x1be3, (q15_t)0x1bdd, + (q15_t)0x1bd7, (q15_t)0x1bd1, (q15_t)0x1bcb, (q15_t)0x1bc4, (q15_t)0x1bbe, (q15_t)0x1bb8, (q15_t)0x1bb2, (q15_t)0x1bac, + (q15_t)0x1ba6, (q15_t)0x1ba0, (q15_t)0x1b9a, (q15_t)0x1b93, (q15_t)0x1b8d, (q15_t)0x1b87, (q15_t)0x1b81, (q15_t)0x1b7b, + (q15_t)0x1b75, (q15_t)0x1b6f, (q15_t)0x1b68, (q15_t)0x1b62, (q15_t)0x1b5c, (q15_t)0x1b56, (q15_t)0x1b50, (q15_t)0x1b4a, + (q15_t)0x1b44, (q15_t)0x1b3d, (q15_t)0x1b37, (q15_t)0x1b31, (q15_t)0x1b2b, (q15_t)0x1b25, (q15_t)0x1b1f, (q15_t)0x1b19, + (q15_t)0x1b13, (q15_t)0x1b0c, (q15_t)0x1b06, (q15_t)0x1b00, (q15_t)0x1afa, (q15_t)0x1af4, (q15_t)0x1aee, (q15_t)0x1ae8, + (q15_t)0x1ae1, (q15_t)0x1adb, (q15_t)0x1ad5, (q15_t)0x1acf, (q15_t)0x1ac9, (q15_t)0x1ac3, (q15_t)0x1abd, (q15_t)0x1ab6, + (q15_t)0x1ab0, (q15_t)0x1aaa, (q15_t)0x1aa4, (q15_t)0x1a9e, (q15_t)0x1a98, (q15_t)0x1a91, (q15_t)0x1a8b, (q15_t)0x1a85, + (q15_t)0x1a7f, (q15_t)0x1a79, (q15_t)0x1a73, (q15_t)0x1a6d, (q15_t)0x1a66, (q15_t)0x1a60, (q15_t)0x1a5a, (q15_t)0x1a54, + (q15_t)0x1a4e, (q15_t)0x1a48, (q15_t)0x1a42, (q15_t)0x1a3b, (q15_t)0x1a35, (q15_t)0x1a2f, (q15_t)0x1a29, (q15_t)0x1a23, + (q15_t)0x1a1d, (q15_t)0x1a17, (q15_t)0x1a10, (q15_t)0x1a0a, (q15_t)0x1a04, (q15_t)0x19fe, (q15_t)0x19f8, (q15_t)0x19f2, + (q15_t)0x19eb, (q15_t)0x19e5, (q15_t)0x19df, (q15_t)0x19d9, (q15_t)0x19d3, (q15_t)0x19cd, (q15_t)0x19c7, (q15_t)0x19c0, + (q15_t)0x19ba, (q15_t)0x19b4, (q15_t)0x19ae, (q15_t)0x19a8, (q15_t)0x19a2, (q15_t)0x199b, (q15_t)0x1995, (q15_t)0x198f, + (q15_t)0x1989, (q15_t)0x1983, (q15_t)0x197d, (q15_t)0x1977, (q15_t)0x1970, (q15_t)0x196a, (q15_t)0x1964, (q15_t)0x195e, + (q15_t)0x1958, (q15_t)0x1952, (q15_t)0x194b, (q15_t)0x1945, (q15_t)0x193f, (q15_t)0x1939, (q15_t)0x1933, (q15_t)0x192d, + (q15_t)0x1926, (q15_t)0x1920, (q15_t)0x191a, (q15_t)0x1914, (q15_t)0x190e, (q15_t)0x1908, (q15_t)0x1901, (q15_t)0x18fb, + (q15_t)0x18f5, (q15_t)0x18ef, (q15_t)0x18e9, (q15_t)0x18e3, (q15_t)0x18dc, (q15_t)0x18d6, (q15_t)0x18d0, (q15_t)0x18ca, + (q15_t)0x18c4, (q15_t)0x18be, (q15_t)0x18b8, (q15_t)0x18b1, (q15_t)0x18ab, (q15_t)0x18a5, (q15_t)0x189f, (q15_t)0x1899, + (q15_t)0x1893, (q15_t)0x188c, (q15_t)0x1886, (q15_t)0x1880, (q15_t)0x187a, (q15_t)0x1874, (q15_t)0x186e, (q15_t)0x1867, + (q15_t)0x1861, (q15_t)0x185b, (q15_t)0x1855, (q15_t)0x184f, (q15_t)0x1848, (q15_t)0x1842, (q15_t)0x183c, (q15_t)0x1836, + (q15_t)0x1830, (q15_t)0x182a, (q15_t)0x1823, (q15_t)0x181d, (q15_t)0x1817, (q15_t)0x1811, (q15_t)0x180b, (q15_t)0x1805, + (q15_t)0x17fe, (q15_t)0x17f8, (q15_t)0x17f2, (q15_t)0x17ec, (q15_t)0x17e6, (q15_t)0x17e0, (q15_t)0x17d9, (q15_t)0x17d3, + (q15_t)0x17cd, (q15_t)0x17c7, (q15_t)0x17c1, (q15_t)0x17bb, (q15_t)0x17b4, (q15_t)0x17ae, (q15_t)0x17a8, (q15_t)0x17a2, + (q15_t)0x179c, (q15_t)0x1795, (q15_t)0x178f, (q15_t)0x1789, (q15_t)0x1783, (q15_t)0x177d, (q15_t)0x1777, (q15_t)0x1770, + (q15_t)0x176a, (q15_t)0x1764, (q15_t)0x175e, (q15_t)0x1758, (q15_t)0x1752, (q15_t)0x174b, (q15_t)0x1745, (q15_t)0x173f, + (q15_t)0x1739, (q15_t)0x1733, (q15_t)0x172c, (q15_t)0x1726, (q15_t)0x1720, (q15_t)0x171a, (q15_t)0x1714, (q15_t)0x170e, + (q15_t)0x1707, (q15_t)0x1701, (q15_t)0x16fb, (q15_t)0x16f5, (q15_t)0x16ef, (q15_t)0x16e8, (q15_t)0x16e2, (q15_t)0x16dc, + (q15_t)0x16d6, (q15_t)0x16d0, (q15_t)0x16ca, (q15_t)0x16c3, (q15_t)0x16bd, (q15_t)0x16b7, (q15_t)0x16b1, (q15_t)0x16ab, + (q15_t)0x16a4, (q15_t)0x169e, (q15_t)0x1698, (q15_t)0x1692, (q15_t)0x168c, (q15_t)0x1686, (q15_t)0x167f, (q15_t)0x1679, + (q15_t)0x1673, (q15_t)0x166d, (q15_t)0x1667, (q15_t)0x1660, (q15_t)0x165a, (q15_t)0x1654, (q15_t)0x164e, (q15_t)0x1648, + (q15_t)0x1642, (q15_t)0x163b, (q15_t)0x1635, (q15_t)0x162f, (q15_t)0x1629, (q15_t)0x1623, (q15_t)0x161c, (q15_t)0x1616, + (q15_t)0x1610, (q15_t)0x160a, (q15_t)0x1604, (q15_t)0x15fd, (q15_t)0x15f7, (q15_t)0x15f1, (q15_t)0x15eb, (q15_t)0x15e5, + (q15_t)0x15de, (q15_t)0x15d8, (q15_t)0x15d2, (q15_t)0x15cc, (q15_t)0x15c6, (q15_t)0x15c0, (q15_t)0x15b9, (q15_t)0x15b3, + (q15_t)0x15ad, (q15_t)0x15a7, (q15_t)0x15a1, (q15_t)0x159a, (q15_t)0x1594, (q15_t)0x158e, (q15_t)0x1588, (q15_t)0x1582, + (q15_t)0x157b, (q15_t)0x1575, (q15_t)0x156f, (q15_t)0x1569, (q15_t)0x1563, (q15_t)0x155c, (q15_t)0x1556, (q15_t)0x1550, + (q15_t)0x154a, (q15_t)0x1544, (q15_t)0x153d, (q15_t)0x1537, (q15_t)0x1531, (q15_t)0x152b, (q15_t)0x1525, (q15_t)0x151e, + (q15_t)0x1518, (q15_t)0x1512, (q15_t)0x150c, (q15_t)0x1506, (q15_t)0x14ff, (q15_t)0x14f9, (q15_t)0x14f3, (q15_t)0x14ed, + (q15_t)0x14e7, (q15_t)0x14e0, (q15_t)0x14da, (q15_t)0x14d4, (q15_t)0x14ce, (q15_t)0x14c8, (q15_t)0x14c1, (q15_t)0x14bb, + (q15_t)0x14b5, (q15_t)0x14af, (q15_t)0x14a9, (q15_t)0x14a2, (q15_t)0x149c, (q15_t)0x1496, (q15_t)0x1490, (q15_t)0x148a, + (q15_t)0x1483, (q15_t)0x147d, (q15_t)0x1477, (q15_t)0x1471, (q15_t)0x146b, (q15_t)0x1464, (q15_t)0x145e, (q15_t)0x1458, + (q15_t)0x1452, (q15_t)0x144c, (q15_t)0x1445, (q15_t)0x143f, (q15_t)0x1439, (q15_t)0x1433, (q15_t)0x142d, (q15_t)0x1426, + (q15_t)0x1420, (q15_t)0x141a, (q15_t)0x1414, (q15_t)0x140e, (q15_t)0x1407, (q15_t)0x1401, (q15_t)0x13fb, (q15_t)0x13f5, + (q15_t)0x13ef, (q15_t)0x13e8, (q15_t)0x13e2, (q15_t)0x13dc, (q15_t)0x13d6, (q15_t)0x13d0, (q15_t)0x13c9, (q15_t)0x13c3, + (q15_t)0x13bd, (q15_t)0x13b7, (q15_t)0x13b1, (q15_t)0x13aa, (q15_t)0x13a4, (q15_t)0x139e, (q15_t)0x1398, (q15_t)0x1391, + (q15_t)0x138b, (q15_t)0x1385, (q15_t)0x137f, (q15_t)0x1379, (q15_t)0x1372, (q15_t)0x136c, (q15_t)0x1366, (q15_t)0x1360, + (q15_t)0x135a, (q15_t)0x1353, (q15_t)0x134d, (q15_t)0x1347, (q15_t)0x1341, (q15_t)0x133b, (q15_t)0x1334, (q15_t)0x132e, + (q15_t)0x1328, (q15_t)0x1322, (q15_t)0x131b, (q15_t)0x1315, (q15_t)0x130f, (q15_t)0x1309, (q15_t)0x1303, (q15_t)0x12fc, + (q15_t)0x12f6, (q15_t)0x12f0, (q15_t)0x12ea, (q15_t)0x12e4, (q15_t)0x12dd, (q15_t)0x12d7, (q15_t)0x12d1, (q15_t)0x12cb, + (q15_t)0x12c4, (q15_t)0x12be, (q15_t)0x12b8, (q15_t)0x12b2, (q15_t)0x12ac, (q15_t)0x12a5, (q15_t)0x129f, (q15_t)0x1299, + (q15_t)0x1293, (q15_t)0x128d, (q15_t)0x1286, (q15_t)0x1280, (q15_t)0x127a, (q15_t)0x1274, (q15_t)0x126d, (q15_t)0x1267, + (q15_t)0x1261, (q15_t)0x125b, (q15_t)0x1255, (q15_t)0x124e, (q15_t)0x1248, (q15_t)0x1242, (q15_t)0x123c, (q15_t)0x1235, + (q15_t)0x122f, (q15_t)0x1229, (q15_t)0x1223, (q15_t)0x121d, (q15_t)0x1216, (q15_t)0x1210, (q15_t)0x120a, (q15_t)0x1204, + (q15_t)0x11fd, (q15_t)0x11f7, (q15_t)0x11f1, (q15_t)0x11eb, (q15_t)0x11e5, (q15_t)0x11de, (q15_t)0x11d8, (q15_t)0x11d2, + (q15_t)0x11cc, (q15_t)0x11c5, (q15_t)0x11bf, (q15_t)0x11b9, (q15_t)0x11b3, (q15_t)0x11ad, (q15_t)0x11a6, (q15_t)0x11a0, + (q15_t)0x119a, (q15_t)0x1194, (q15_t)0x118d, (q15_t)0x1187, (q15_t)0x1181, (q15_t)0x117b, (q15_t)0x1175, (q15_t)0x116e, + (q15_t)0x1168, (q15_t)0x1162, (q15_t)0x115c, (q15_t)0x1155, (q15_t)0x114f, (q15_t)0x1149, (q15_t)0x1143, (q15_t)0x113d, + (q15_t)0x1136, (q15_t)0x1130, (q15_t)0x112a, (q15_t)0x1124, (q15_t)0x111d, (q15_t)0x1117, (q15_t)0x1111, (q15_t)0x110b, + (q15_t)0x1105, (q15_t)0x10fe, (q15_t)0x10f8, (q15_t)0x10f2, (q15_t)0x10ec, (q15_t)0x10e5, (q15_t)0x10df, (q15_t)0x10d9, + (q15_t)0x10d3, (q15_t)0x10cc, (q15_t)0x10c6, (q15_t)0x10c0, (q15_t)0x10ba, (q15_t)0x10b4, (q15_t)0x10ad, (q15_t)0x10a7, + (q15_t)0x10a1, (q15_t)0x109b, (q15_t)0x1094, (q15_t)0x108e, (q15_t)0x1088, (q15_t)0x1082, (q15_t)0x107b, (q15_t)0x1075, + (q15_t)0x106f, (q15_t)0x1069, (q15_t)0x1063, (q15_t)0x105c, (q15_t)0x1056, (q15_t)0x1050, (q15_t)0x104a, (q15_t)0x1043, + (q15_t)0x103d, (q15_t)0x1037, (q15_t)0x1031, (q15_t)0x102a, (q15_t)0x1024, (q15_t)0x101e, (q15_t)0x1018, (q15_t)0x1012, + (q15_t)0x100b, (q15_t)0x1005, (q15_t)0xfff, (q15_t)0xff9, (q15_t)0xff2, (q15_t)0xfec, (q15_t)0xfe6, (q15_t)0xfe0, + (q15_t)0xfd9, (q15_t)0xfd3, (q15_t)0xfcd, (q15_t)0xfc7, (q15_t)0xfc0, (q15_t)0xfba, (q15_t)0xfb4, (q15_t)0xfae, + (q15_t)0xfa8, (q15_t)0xfa1, (q15_t)0xf9b, (q15_t)0xf95, (q15_t)0xf8f, (q15_t)0xf88, (q15_t)0xf82, (q15_t)0xf7c, + (q15_t)0xf76, (q15_t)0xf6f, (q15_t)0xf69, (q15_t)0xf63, (q15_t)0xf5d, (q15_t)0xf56, (q15_t)0xf50, (q15_t)0xf4a, + (q15_t)0xf44, (q15_t)0xf3e, (q15_t)0xf37, (q15_t)0xf31, (q15_t)0xf2b, (q15_t)0xf25, (q15_t)0xf1e, (q15_t)0xf18, + (q15_t)0xf12, (q15_t)0xf0c, (q15_t)0xf05, (q15_t)0xeff, (q15_t)0xef9, (q15_t)0xef3, (q15_t)0xeec, (q15_t)0xee6, + (q15_t)0xee0, (q15_t)0xeda, (q15_t)0xed3, (q15_t)0xecd, (q15_t)0xec7, (q15_t)0xec1, (q15_t)0xeba, (q15_t)0xeb4, + (q15_t)0xeae, (q15_t)0xea8, (q15_t)0xea1, (q15_t)0xe9b, (q15_t)0xe95, (q15_t)0xe8f, (q15_t)0xe89, (q15_t)0xe82, + (q15_t)0xe7c, (q15_t)0xe76, (q15_t)0xe70, (q15_t)0xe69, (q15_t)0xe63, (q15_t)0xe5d, (q15_t)0xe57, (q15_t)0xe50, + (q15_t)0xe4a, (q15_t)0xe44, (q15_t)0xe3e, (q15_t)0xe37, (q15_t)0xe31, (q15_t)0xe2b, (q15_t)0xe25, (q15_t)0xe1e, + (q15_t)0xe18, (q15_t)0xe12, (q15_t)0xe0c, (q15_t)0xe05, (q15_t)0xdff, (q15_t)0xdf9, (q15_t)0xdf3, (q15_t)0xdec, + (q15_t)0xde6, (q15_t)0xde0, (q15_t)0xdda, (q15_t)0xdd3, (q15_t)0xdcd, (q15_t)0xdc7, (q15_t)0xdc1, (q15_t)0xdba, + (q15_t)0xdb4, (q15_t)0xdae, (q15_t)0xda8, (q15_t)0xda1, (q15_t)0xd9b, (q15_t)0xd95, (q15_t)0xd8f, (q15_t)0xd88, + (q15_t)0xd82, (q15_t)0xd7c, (q15_t)0xd76, (q15_t)0xd6f, (q15_t)0xd69, (q15_t)0xd63, (q15_t)0xd5d, (q15_t)0xd56, + (q15_t)0xd50, (q15_t)0xd4a, (q15_t)0xd44, (q15_t)0xd3d, (q15_t)0xd37, (q15_t)0xd31, (q15_t)0xd2b, (q15_t)0xd24, + (q15_t)0xd1e, (q15_t)0xd18, (q15_t)0xd12, (q15_t)0xd0b, (q15_t)0xd05, (q15_t)0xcff, (q15_t)0xcf9, (q15_t)0xcf2, + (q15_t)0xcec, (q15_t)0xce6, (q15_t)0xce0, (q15_t)0xcd9, (q15_t)0xcd3, (q15_t)0xccd, (q15_t)0xcc7, (q15_t)0xcc0, + (q15_t)0xcba, (q15_t)0xcb4, (q15_t)0xcae, (q15_t)0xca7, (q15_t)0xca1, (q15_t)0xc9b, (q15_t)0xc95, (q15_t)0xc8e, + (q15_t)0xc88, (q15_t)0xc82, (q15_t)0xc7c, (q15_t)0xc75, (q15_t)0xc6f, (q15_t)0xc69, (q15_t)0xc63, (q15_t)0xc5c, + (q15_t)0xc56, (q15_t)0xc50, (q15_t)0xc4a, (q15_t)0xc43, (q15_t)0xc3d, (q15_t)0xc37, (q15_t)0xc31, (q15_t)0xc2a, + (q15_t)0xc24, (q15_t)0xc1e, (q15_t)0xc18, (q15_t)0xc11, (q15_t)0xc0b, (q15_t)0xc05, (q15_t)0xbff, (q15_t)0xbf8, + (q15_t)0xbf2, (q15_t)0xbec, (q15_t)0xbe6, (q15_t)0xbdf, (q15_t)0xbd9, (q15_t)0xbd3, (q15_t)0xbcd, (q15_t)0xbc6, + (q15_t)0xbc0, (q15_t)0xbba, (q15_t)0xbb4, (q15_t)0xbad, (q15_t)0xba7, (q15_t)0xba1, (q15_t)0xb9b, (q15_t)0xb94, + (q15_t)0xb8e, (q15_t)0xb88, (q15_t)0xb81, (q15_t)0xb7b, (q15_t)0xb75, (q15_t)0xb6f, (q15_t)0xb68, (q15_t)0xb62, + (q15_t)0xb5c, (q15_t)0xb56, (q15_t)0xb4f, (q15_t)0xb49, (q15_t)0xb43, (q15_t)0xb3d, (q15_t)0xb36, (q15_t)0xb30, + (q15_t)0xb2a, (q15_t)0xb24, (q15_t)0xb1d, (q15_t)0xb17, (q15_t)0xb11, (q15_t)0xb0b, (q15_t)0xb04, (q15_t)0xafe, + (q15_t)0xaf8, (q15_t)0xaf2, (q15_t)0xaeb, (q15_t)0xae5, (q15_t)0xadf, (q15_t)0xad8, (q15_t)0xad2, (q15_t)0xacc, + (q15_t)0xac6, (q15_t)0xabf, (q15_t)0xab9, (q15_t)0xab3, (q15_t)0xaad, (q15_t)0xaa6, (q15_t)0xaa0, (q15_t)0xa9a, + (q15_t)0xa94, (q15_t)0xa8d, (q15_t)0xa87, (q15_t)0xa81, (q15_t)0xa7b, (q15_t)0xa74, (q15_t)0xa6e, (q15_t)0xa68, + (q15_t)0xa62, (q15_t)0xa5b, (q15_t)0xa55, (q15_t)0xa4f, (q15_t)0xa48, (q15_t)0xa42, (q15_t)0xa3c, (q15_t)0xa36, + (q15_t)0xa2f, (q15_t)0xa29, (q15_t)0xa23, (q15_t)0xa1d, (q15_t)0xa16, (q15_t)0xa10, (q15_t)0xa0a, (q15_t)0xa04, + (q15_t)0x9fd, (q15_t)0x9f7, (q15_t)0x9f1, (q15_t)0x9eb, (q15_t)0x9e4, (q15_t)0x9de, (q15_t)0x9d8, (q15_t)0x9d1, + (q15_t)0x9cb, (q15_t)0x9c5, (q15_t)0x9bf, (q15_t)0x9b8, (q15_t)0x9b2, (q15_t)0x9ac, (q15_t)0x9a6, (q15_t)0x99f, + (q15_t)0x999, (q15_t)0x993, (q15_t)0x98d, (q15_t)0x986, (q15_t)0x980, (q15_t)0x97a, (q15_t)0x973, (q15_t)0x96d, + (q15_t)0x967, (q15_t)0x961, (q15_t)0x95a, (q15_t)0x954, (q15_t)0x94e, (q15_t)0x948, (q15_t)0x941, (q15_t)0x93b, + (q15_t)0x935, (q15_t)0x92f, (q15_t)0x928, (q15_t)0x922, (q15_t)0x91c, (q15_t)0x915, (q15_t)0x90f, (q15_t)0x909, + (q15_t)0x903, (q15_t)0x8fc, (q15_t)0x8f6, (q15_t)0x8f0, (q15_t)0x8ea, (q15_t)0x8e3, (q15_t)0x8dd, (q15_t)0x8d7, + (q15_t)0x8d1, (q15_t)0x8ca, (q15_t)0x8c4, (q15_t)0x8be, (q15_t)0x8b7, (q15_t)0x8b1, (q15_t)0x8ab, (q15_t)0x8a5, + (q15_t)0x89e, (q15_t)0x898, (q15_t)0x892, (q15_t)0x88c, (q15_t)0x885, (q15_t)0x87f, (q15_t)0x879, (q15_t)0x872, + (q15_t)0x86c, (q15_t)0x866, (q15_t)0x860, (q15_t)0x859, (q15_t)0x853, (q15_t)0x84d, (q15_t)0x847, (q15_t)0x840, + (q15_t)0x83a, (q15_t)0x834, (q15_t)0x82e, (q15_t)0x827, (q15_t)0x821, (q15_t)0x81b, (q15_t)0x814, (q15_t)0x80e, + (q15_t)0x808, (q15_t)0x802, (q15_t)0x7fb, (q15_t)0x7f5, (q15_t)0x7ef, (q15_t)0x7e9, (q15_t)0x7e2, (q15_t)0x7dc, + (q15_t)0x7d6, (q15_t)0x7cf, (q15_t)0x7c9, (q15_t)0x7c3, (q15_t)0x7bd, (q15_t)0x7b6, (q15_t)0x7b0, (q15_t)0x7aa, + (q15_t)0x7a4, (q15_t)0x79d, (q15_t)0x797, (q15_t)0x791, (q15_t)0x78a, (q15_t)0x784, (q15_t)0x77e, (q15_t)0x778, + (q15_t)0x771, (q15_t)0x76b, (q15_t)0x765, (q15_t)0x75f, (q15_t)0x758, (q15_t)0x752, (q15_t)0x74c, (q15_t)0x745, + (q15_t)0x73f, (q15_t)0x739, (q15_t)0x733, (q15_t)0x72c, (q15_t)0x726, (q15_t)0x720, (q15_t)0x71a, (q15_t)0x713, + (q15_t)0x70d, (q15_t)0x707, (q15_t)0x700, (q15_t)0x6fa, (q15_t)0x6f4, (q15_t)0x6ee, (q15_t)0x6e7, (q15_t)0x6e1, + (q15_t)0x6db, (q15_t)0x6d5, (q15_t)0x6ce, (q15_t)0x6c8, (q15_t)0x6c2, (q15_t)0x6bb, (q15_t)0x6b5, (q15_t)0x6af, + (q15_t)0x6a9, (q15_t)0x6a2, (q15_t)0x69c, (q15_t)0x696, (q15_t)0x690, (q15_t)0x689, (q15_t)0x683, (q15_t)0x67d, + (q15_t)0x676, (q15_t)0x670, (q15_t)0x66a, (q15_t)0x664, (q15_t)0x65d, (q15_t)0x657, (q15_t)0x651, (q15_t)0x64a, + (q15_t)0x644, (q15_t)0x63e, (q15_t)0x638, (q15_t)0x631, (q15_t)0x62b, (q15_t)0x625, (q15_t)0x61f, (q15_t)0x618, + (q15_t)0x612, (q15_t)0x60c, (q15_t)0x605, (q15_t)0x5ff, (q15_t)0x5f9, (q15_t)0x5f3, (q15_t)0x5ec, (q15_t)0x5e6, + (q15_t)0x5e0, (q15_t)0x5da, (q15_t)0x5d3, (q15_t)0x5cd, (q15_t)0x5c7, (q15_t)0x5c0, (q15_t)0x5ba, (q15_t)0x5b4, + (q15_t)0x5ae, (q15_t)0x5a7, (q15_t)0x5a1, (q15_t)0x59b, (q15_t)0x594, (q15_t)0x58e, (q15_t)0x588, (q15_t)0x582, + (q15_t)0x57b, (q15_t)0x575, (q15_t)0x56f, (q15_t)0x569, (q15_t)0x562, (q15_t)0x55c, (q15_t)0x556, (q15_t)0x54f, + (q15_t)0x549, (q15_t)0x543, (q15_t)0x53d, (q15_t)0x536, (q15_t)0x530, (q15_t)0x52a, (q15_t)0x523, (q15_t)0x51d, + (q15_t)0x517, (q15_t)0x511, (q15_t)0x50a, (q15_t)0x504, (q15_t)0x4fe, (q15_t)0x4f8, (q15_t)0x4f1, (q15_t)0x4eb, + (q15_t)0x4e5, (q15_t)0x4de, (q15_t)0x4d8, (q15_t)0x4d2, (q15_t)0x4cc, (q15_t)0x4c5, (q15_t)0x4bf, (q15_t)0x4b9, + (q15_t)0x4b2, (q15_t)0x4ac, (q15_t)0x4a6, (q15_t)0x4a0, (q15_t)0x499, (q15_t)0x493, (q15_t)0x48d, (q15_t)0x487, + (q15_t)0x480, (q15_t)0x47a, (q15_t)0x474, (q15_t)0x46d, (q15_t)0x467, (q15_t)0x461, (q15_t)0x45b, (q15_t)0x454, + (q15_t)0x44e, (q15_t)0x448, (q15_t)0x441, (q15_t)0x43b, (q15_t)0x435, (q15_t)0x42f, (q15_t)0x428, (q15_t)0x422, + (q15_t)0x41c, (q15_t)0x415, (q15_t)0x40f, (q15_t)0x409, (q15_t)0x403, (q15_t)0x3fc, (q15_t)0x3f6, (q15_t)0x3f0, + (q15_t)0x3ea, (q15_t)0x3e3, (q15_t)0x3dd, (q15_t)0x3d7, (q15_t)0x3d0, (q15_t)0x3ca, (q15_t)0x3c4, (q15_t)0x3be, + (q15_t)0x3b7, (q15_t)0x3b1, (q15_t)0x3ab, (q15_t)0x3a4, (q15_t)0x39e, (q15_t)0x398, (q15_t)0x392, (q15_t)0x38b, + (q15_t)0x385, (q15_t)0x37f, (q15_t)0x378, (q15_t)0x372, (q15_t)0x36c, (q15_t)0x366, (q15_t)0x35f, (q15_t)0x359, + (q15_t)0x353, (q15_t)0x34c, (q15_t)0x346, (q15_t)0x340, (q15_t)0x33a, (q15_t)0x333, (q15_t)0x32d, (q15_t)0x327, + (q15_t)0x321, (q15_t)0x31a, (q15_t)0x314, (q15_t)0x30e, (q15_t)0x307, (q15_t)0x301, (q15_t)0x2fb, (q15_t)0x2f5, + (q15_t)0x2ee, (q15_t)0x2e8, (q15_t)0x2e2, (q15_t)0x2db, (q15_t)0x2d5, (q15_t)0x2cf, (q15_t)0x2c9, (q15_t)0x2c2, + (q15_t)0x2bc, (q15_t)0x2b6, (q15_t)0x2af, (q15_t)0x2a9, (q15_t)0x2a3, (q15_t)0x29d, (q15_t)0x296, (q15_t)0x290, + (q15_t)0x28a, (q15_t)0x283, (q15_t)0x27d, (q15_t)0x277, (q15_t)0x271, (q15_t)0x26a, (q15_t)0x264, (q15_t)0x25e, + (q15_t)0x258, (q15_t)0x251, (q15_t)0x24b, (q15_t)0x245, (q15_t)0x23e, (q15_t)0x238, (q15_t)0x232, (q15_t)0x22c, + (q15_t)0x225, (q15_t)0x21f, (q15_t)0x219, (q15_t)0x212, (q15_t)0x20c, (q15_t)0x206, (q15_t)0x200, (q15_t)0x1f9, + (q15_t)0x1f3, (q15_t)0x1ed, (q15_t)0x1e6, (q15_t)0x1e0, (q15_t)0x1da, (q15_t)0x1d4, (q15_t)0x1cd, (q15_t)0x1c7, + (q15_t)0x1c1, (q15_t)0x1ba, (q15_t)0x1b4, (q15_t)0x1ae, (q15_t)0x1a8, (q15_t)0x1a1, (q15_t)0x19b, (q15_t)0x195, + (q15_t)0x18e, (q15_t)0x188, (q15_t)0x182, (q15_t)0x17c, (q15_t)0x175, (q15_t)0x16f, (q15_t)0x169, (q15_t)0x162, + (q15_t)0x15c, (q15_t)0x156, (q15_t)0x150, (q15_t)0x149, (q15_t)0x143, (q15_t)0x13d, (q15_t)0x137, (q15_t)0x130, + (q15_t)0x12a, (q15_t)0x124, (q15_t)0x11d, (q15_t)0x117, (q15_t)0x111, (q15_t)0x10b, (q15_t)0x104, (q15_t)0xfe, + (q15_t)0xf8, (q15_t)0xf1, (q15_t)0xeb, (q15_t)0xe5, (q15_t)0xdf, (q15_t)0xd8, (q15_t)0xd2, (q15_t)0xcc, + (q15_t)0xc5, (q15_t)0xbf, (q15_t)0xb9, (q15_t)0xb3, (q15_t)0xac, (q15_t)0xa6, (q15_t)0xa0, (q15_t)0x99, + (q15_t)0x93, (q15_t)0x8d, (q15_t)0x87, (q15_t)0x80, (q15_t)0x7a, (q15_t)0x74, (q15_t)0x6d, (q15_t)0x67, + (q15_t)0x61, (q15_t)0x5b, (q15_t)0x54, (q15_t)0x4e, (q15_t)0x48, (q15_t)0x41, (q15_t)0x3b, (q15_t)0x35, + (q15_t)0x2f, (q15_t)0x28, (q15_t)0x22, (q15_t)0x1c, (q15_t)0x15, (q15_t)0xf, (q15_t)0x9, (q15_t)0x3 +}; + #endif + +/** + @par + Weights tables are generated using the formula :
weights[n] = e^(-j*n*pi/(2*N))
+ @par + C command to generate the table +
+  for (i = 0; i< N; i++)
+  {
+    weights[(2*i)]   =  cos(i*c);
+    weights[(2*i)+1] = -sin(i*c);
+  } 
+ @par + where N is the Number of weights to be calculated and c is pi/(2*N) + @par + Convert the output to q31 format by multiplying with 2^31 and saturated if required. + @par + In the tables below the real and imaginary values are placed alternatively, hence the + array length is 2*N. + */ + +/** + @par + cosFactor tables are generated using the formula :
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
+ @par + C command to generate the table +
+  for (i = 0; i< N; i++)
+  {
+    cos_factors[i] = 2 * cos((2*i+1)*c/2);
+  } 
+ @par + where N is the number of factors to generate and c is pi/(2*N) + @par + Then converted to q31 format by multiplying with 2^31 and saturated if required. +*/ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128) + const q31_t WeightsQ31_128[256] = { + (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3, + (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fc25596, (q31_t)0xf826a462, (q31_t)0x7fa736b4, (q31_t)0xf6956fb7, (q31_t)0x7f872bf3, (q31_t)0xf50497fb, + (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7ed5e5c6, (q31_t)0xeec60f31, + (q31_t)0x7e9d55fc, (q31_t)0xed37ef91, (q31_t)0x7e5fe493, (q31_t)0xebaa894f, (q31_t)0x7e1d93ea, (q31_t)0xea1debbb, (q31_t)0x7dd6668f, (q31_t)0xe8922622, + (q31_t)0x7d8a5f40, (q31_t)0xe70747c4, (q31_t)0x7d3980ec, (q31_t)0xe57d5fda, (q31_t)0x7ce3ceb2, (q31_t)0xe3f47d96, (q31_t)0x7c894bde, (q31_t)0xe26cb01b, + (q31_t)0x7c29fbee, (q31_t)0xe0e60685, (q31_t)0x7bc5e290, (q31_t)0xdf608fe4, (q31_t)0x7b5d039e, (q31_t)0xdddc5b3b, (q31_t)0x7aef6323, (q31_t)0xdc597781, + (q31_t)0x7a7d055b, (q31_t)0xdad7f3a2, (q31_t)0x7a05eead, (q31_t)0xd957de7a, (q31_t)0x798a23b1, (q31_t)0xd7d946d8, (q31_t)0x7909a92d, (q31_t)0xd65c3b7b, + (q31_t)0x78848414, (q31_t)0xd4e0cb15, (q31_t)0x77fab989, (q31_t)0xd3670446, (q31_t)0x776c4edb, (q31_t)0xd1eef59e, (q31_t)0x76d94989, (q31_t)0xd078ad9e, + (q31_t)0x7641af3d, (q31_t)0xcf043ab3, (q31_t)0x75a585cf, (q31_t)0xcd91ab39, (q31_t)0x7504d345, (q31_t)0xcc210d79, (q31_t)0x745f9dd1, (q31_t)0xcab26fa9, + (q31_t)0x73b5ebd1, (q31_t)0xc945dfec, (q31_t)0x7307c3d0, (q31_t)0xc7db6c50, (q31_t)0x72552c85, (q31_t)0xc67322ce, (q31_t)0x719e2cd2, (q31_t)0xc50d1149, + (q31_t)0x70e2cbc6, (q31_t)0xc3a94590, (q31_t)0x7023109a, (q31_t)0xc247cd5a, (q31_t)0x6f5f02b2, (q31_t)0xc0e8b648, (q31_t)0x6e96a99d, (q31_t)0xbf8c0de3, + (q31_t)0x6dca0d14, (q31_t)0xbe31e19b, (q31_t)0x6cf934fc, (q31_t)0xbcda3ecb, (q31_t)0x6c242960, (q31_t)0xbb8532b0, (q31_t)0x6b4af279, (q31_t)0xba32ca71, + (q31_t)0x6a6d98a4, (q31_t)0xb8e31319, (q31_t)0x698c246c, (q31_t)0xb796199b, (q31_t)0x68a69e81, (q31_t)0xb64beacd, (q31_t)0x67bd0fbd, (q31_t)0xb5049368, + (q31_t)0x66cf8120, (q31_t)0xb3c0200c, (q31_t)0x65ddfbd3, (q31_t)0xb27e9d3c, (q31_t)0x64e88926, (q31_t)0xb140175b, (q31_t)0x63ef3290, (q31_t)0xb0049ab3, + (q31_t)0x62f201ac, (q31_t)0xaecc336c, (q31_t)0x61f1003f, (q31_t)0xad96ed92, (q31_t)0x60ec3830, (q31_t)0xac64d510, (q31_t)0x5fe3b38d, (q31_t)0xab35f5b5, + (q31_t)0x5ed77c8a, (q31_t)0xaa0a5b2e, (q31_t)0x5dc79d7c, (q31_t)0xa8e21106, (q31_t)0x5cb420e0, (q31_t)0xa7bd22ac, (q31_t)0x5b9d1154, (q31_t)0xa69b9b68, + (q31_t)0x5a82799a, (q31_t)0xa57d8666, (q31_t)0x59646498, (q31_t)0xa462eeac, (q31_t)0x5842dd54, (q31_t)0xa34bdf20, (q31_t)0x571deefa, (q31_t)0xa2386284, + (q31_t)0x55f5a4d2, (q31_t)0xa1288376, (q31_t)0x54ca0a4b, (q31_t)0xa01c4c73, (q31_t)0x539b2af0, (q31_t)0x9f13c7d0, (q31_t)0x5269126e, (q31_t)0x9e0effc1, + (q31_t)0x5133cc94, (q31_t)0x9d0dfe54, (q31_t)0x4ffb654d, (q31_t)0x9c10cd70, (q31_t)0x4ebfe8a5, (q31_t)0x9b1776da, (q31_t)0x4d8162c4, (q31_t)0x9a22042d, + (q31_t)0x4c3fdff4, (q31_t)0x99307ee0, (q31_t)0x4afb6c98, (q31_t)0x9842f043, (q31_t)0x49b41533, (q31_t)0x9759617f, (q31_t)0x4869e665, (q31_t)0x9673db94, + (q31_t)0x471cece7, (q31_t)0x9592675c, (q31_t)0x45cd358f, (q31_t)0x94b50d87, (q31_t)0x447acd50, (q31_t)0x93dbd6a0, (q31_t)0x4325c135, (q31_t)0x9306cb04, + (q31_t)0x41ce1e65, (q31_t)0x9235f2ec, (q31_t)0x4073f21d, (q31_t)0x91695663, (q31_t)0x3f1749b8, (q31_t)0x90a0fd4e, (q31_t)0x3db832a6, (q31_t)0x8fdcef66, + (q31_t)0x3c56ba70, (q31_t)0x8f1d343a, (q31_t)0x3af2eeb7, (q31_t)0x8e61d32e, (q31_t)0x398cdd32, (q31_t)0x8daad37b, (q31_t)0x382493b0, (q31_t)0x8cf83c30, + (q31_t)0x36ba2014, (q31_t)0x8c4a142f, (q31_t)0x354d9057, (q31_t)0x8ba0622f, (q31_t)0x33def287, (q31_t)0x8afb2cbb, (q31_t)0x326e54c7, (q31_t)0x8a5a7a31, + (q31_t)0x30fbc54d, (q31_t)0x89be50c3, (q31_t)0x2f875262, (q31_t)0x8926b677, (q31_t)0x2e110a62, (q31_t)0x8893b125, (q31_t)0x2c98fbba, (q31_t)0x88054677, + (q31_t)0x2b1f34eb, (q31_t)0x877b7bec, (q31_t)0x29a3c485, (q31_t)0x86f656d3, (q31_t)0x2826b928, (q31_t)0x8675dc4f, (q31_t)0x26a82186, (q31_t)0x85fa1153, + (q31_t)0x25280c5e, (q31_t)0x8582faa5, (q31_t)0x23a6887f, (q31_t)0x85109cdd, (q31_t)0x2223a4c5, (q31_t)0x84a2fc62, (q31_t)0x209f701c, (q31_t)0x843a1d70, + (q31_t)0x1f19f97b, (q31_t)0x83d60412, (q31_t)0x1d934fe5, (q31_t)0x8376b422, (q31_t)0x1c0b826a, (q31_t)0x831c314e, (q31_t)0x1a82a026, (q31_t)0x82c67f14, + (q31_t)0x18f8b83c, (q31_t)0x8275a0c0, (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x145576b1, (q31_t)0x81a01b6d, + (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0x0fab272b, (q31_t)0x80f66e3c, (q31_t)0x0e1bc2e4, (q31_t)0x80c7a80a, + (q31_t)0x0c8bd35e, (q31_t)0x809dc971, (q31_t)0x0afb6805, (q31_t)0x8078d40d, (q31_t)0x096a9049, (q31_t)0x8058c94c, (q31_t)0x07d95b9e, (q31_t)0x803daa6a, + (q31_t)0x0647d97c, (q31_t)0x80277872, (q31_t)0x04b6195d, (q31_t)0x80163440, (q31_t)0x03242abf, (q31_t)0x8009de7e, (q31_t)0x01921d20, (q31_t)0x800277a6 +}; + const q31_t cos_factorsQ31_128[128] = { + (q31_t)0x7fff6216, (q31_t)0x7ffa72d1, (q31_t)0x7ff09478, (q31_t)0x7fe1c76b, (q31_t)0x7fce0c3e, (q31_t)0x7fb563b3, + (q31_t)0x7f97cebd, (q31_t)0x7f754e80, + (q31_t)0x7f4de451, (q31_t)0x7f2191b4, (q31_t)0x7ef05860, (q31_t)0x7eba3a39, (q31_t)0x7e7f3957, (q31_t)0x7e3f57ff, + (q31_t)0x7dfa98a8, (q31_t)0x7db0fdf8, + (q31_t)0x7d628ac6, (q31_t)0x7d0f4218, (q31_t)0x7cb72724, (q31_t)0x7c5a3d50, (q31_t)0x7bf88830, (q31_t)0x7b920b89, + (q31_t)0x7b26cb4f, (q31_t)0x7ab6cba4, + (q31_t)0x7a4210d8, (q31_t)0x79c89f6e, (q31_t)0x794a7c12, (q31_t)0x78c7aba2, (q31_t)0x78403329, (q31_t)0x77b417df, + (q31_t)0x77235f2d, (q31_t)0x768e0ea6, + (q31_t)0x75f42c0b, (q31_t)0x7555bd4c, (q31_t)0x74b2c884, (q31_t)0x740b53fb, (q31_t)0x735f6626, (q31_t)0x72af05a7, + (q31_t)0x71fa3949, (q31_t)0x71410805, + (q31_t)0x708378ff, (q31_t)0x6fc19385, (q31_t)0x6efb5f12, (q31_t)0x6e30e34a, (q31_t)0x6d6227fa, (q31_t)0x6c8f351c, + (q31_t)0x6bb812d1, (q31_t)0x6adcc964, + (q31_t)0x69fd614a, (q31_t)0x6919e320, (q31_t)0x683257ab, (q31_t)0x6746c7d8, (q31_t)0x66573cbb, (q31_t)0x6563bf92, + (q31_t)0x646c59bf, (q31_t)0x637114cc, + (q31_t)0x6271fa69, (q31_t)0x616f146c, (q31_t)0x60686ccf, (q31_t)0x5f5e0db3, (q31_t)0x5e50015d, (q31_t)0x5d3e5237, + (q31_t)0x5c290acc, (q31_t)0x5b1035cf, + (q31_t)0x59f3de12, (q31_t)0x58d40e8c, (q31_t)0x57b0d256, (q31_t)0x568a34a9, (q31_t)0x556040e2, (q31_t)0x5433027d, + (q31_t)0x53028518, (q31_t)0x51ced46e, + (q31_t)0x5097fc5e, (q31_t)0x4f5e08e3, (q31_t)0x4e210617, (q31_t)0x4ce10034, (q31_t)0x4b9e0390, (q31_t)0x4a581c9e, + (q31_t)0x490f57ee, (q31_t)0x47c3c22f, + (q31_t)0x46756828, (q31_t)0x452456bd, (q31_t)0x43d09aed, (q31_t)0x427a41d0, (q31_t)0x4121589b, (q31_t)0x3fc5ec98, + (q31_t)0x3e680b2c, (q31_t)0x3d07c1d6, + (q31_t)0x3ba51e29, (q31_t)0x3a402dd2, (q31_t)0x38d8fe93, (q31_t)0x376f9e46, (q31_t)0x36041ad9, (q31_t)0x34968250, + (q31_t)0x3326e2c3, (q31_t)0x31b54a5e, + (q31_t)0x3041c761, (q31_t)0x2ecc681e, (q31_t)0x2d553afc, (q31_t)0x2bdc4e6f, (q31_t)0x2a61b101, (q31_t)0x28e5714b, + (q31_t)0x27679df4, (q31_t)0x25e845b6, + (q31_t)0x24677758, (q31_t)0x22e541af, (q31_t)0x2161b3a0, (q31_t)0x1fdcdc1b, (q31_t)0x1e56ca1e, (q31_t)0x1ccf8cb3, + (q31_t)0x1b4732ef, (q31_t)0x19bdcbf3, + (q31_t)0x183366e9, (q31_t)0x16a81305, (q31_t)0x151bdf86, (q31_t)0x138edbb1, (q31_t)0x120116d5, (q31_t)0x1072a048, + (q31_t)0xee38766, (q31_t)0xd53db92, + (q31_t)0xbc3ac35, (q31_t)0xa3308bd, (q31_t)0x8a2009a, (q31_t)0x710a345, (q31_t)0x57f0035, (q31_t)0x3ed26e6, (q31_t)0x25b26d7, + (q31_t)0xc90f88 +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512) + const q31_t WeightsQ31_512[1024] = { + (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7fffd886, (q31_t)0xff9b781d, (q31_t)0x7fff6216, (q31_t)0xff36f078, (q31_t)0x7ffe9cb2, (q31_t)0xfed2694f, + (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ffc250f, (q31_t)0xfe095d69, (q31_t)0x7ffa72d1, (q31_t)0xfda4d929, (q31_t)0x7ff871a2, (q31_t)0xfd40565c, + (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7ff38274, (q31_t)0xfc775616, (q31_t)0x7ff09478, (q31_t)0xfc12d91a, (q31_t)0x7fed5791, (q31_t)0xfbae5e89, + (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3, (q31_t)0x7fe5f108, (q31_t)0xfae571a4, (q31_t)0x7fe1c76b, (q31_t)0xfa80ffcb, (q31_t)0x7fdd4eec, (q31_t)0xfa1c9157, + (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fd37153, (q31_t)0xf953bf91, (q31_t)0x7fce0c3e, (q31_t)0xf8ef5cbb, (q31_t)0x7fc85854, (q31_t)0xf88afe42, + (q31_t)0x7fc25596, (q31_t)0xf826a462, (q31_t)0x7fbc040a, (q31_t)0xf7c24f59, (q31_t)0x7fb563b3, (q31_t)0xf75dff66, (q31_t)0x7fae7495, (q31_t)0xf6f9b4c6, + (q31_t)0x7fa736b4, (q31_t)0xf6956fb7, (q31_t)0x7f9faa15, (q31_t)0xf6313077, (q31_t)0x7f97cebd, (q31_t)0xf5ccf743, (q31_t)0x7f8fa4b0, (q31_t)0xf568c45b, + (q31_t)0x7f872bf3, (q31_t)0xf50497fb, (q31_t)0x7f7e648c, (q31_t)0xf4a07261, (q31_t)0x7f754e80, (q31_t)0xf43c53cb, (q31_t)0x7f6be9d4, (q31_t)0xf3d83c77, + (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f5834b7, (q31_t)0xf310248a, (q31_t)0x7f4de451, (q31_t)0xf2ac246e, (q31_t)0x7f434563, (q31_t)0xf2482c8a, + (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f2d1c0e, (q31_t)0xf1805662, (q31_t)0x7f2191b4, (q31_t)0xf11c789a, (q31_t)0x7f15b8ee, (q31_t)0xf0b8a401, + (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7efd1c3c, (q31_t)0xeff11753, (q31_t)0x7ef05860, (q31_t)0xef8d5fb8, (q31_t)0x7ee34636, (q31_t)0xef29b243, + (q31_t)0x7ed5e5c6, (q31_t)0xeec60f31, (q31_t)0x7ec8371a, (q31_t)0xee6276bf, (q31_t)0x7eba3a39, (q31_t)0xedfee92b, (q31_t)0x7eabef2c, (q31_t)0xed9b66b2, + (q31_t)0x7e9d55fc, (q31_t)0xed37ef91, (q31_t)0x7e8e6eb2, (q31_t)0xecd48407, (q31_t)0x7e7f3957, (q31_t)0xec71244f, (q31_t)0x7e6fb5f4, (q31_t)0xec0dd0a8, + (q31_t)0x7e5fe493, (q31_t)0xebaa894f, (q31_t)0x7e4fc53e, (q31_t)0xeb474e81, (q31_t)0x7e3f57ff, (q31_t)0xeae4207a, (q31_t)0x7e2e9cdf, (q31_t)0xea80ff7a, + (q31_t)0x7e1d93ea, (q31_t)0xea1debbb, (q31_t)0x7e0c3d29, (q31_t)0xe9bae57d, (q31_t)0x7dfa98a8, (q31_t)0xe957ecfb, (q31_t)0x7de8a670, (q31_t)0xe8f50273, + (q31_t)0x7dd6668f, (q31_t)0xe8922622, (q31_t)0x7dc3d90d, (q31_t)0xe82f5844, (q31_t)0x7db0fdf8, (q31_t)0xe7cc9917, (q31_t)0x7d9dd55a, (q31_t)0xe769e8d8, + (q31_t)0x7d8a5f40, (q31_t)0xe70747c4, (q31_t)0x7d769bb5, (q31_t)0xe6a4b616, (q31_t)0x7d628ac6, (q31_t)0xe642340d, (q31_t)0x7d4e2c7f, (q31_t)0xe5dfc1e5, + (q31_t)0x7d3980ec, (q31_t)0xe57d5fda, (q31_t)0x7d24881b, (q31_t)0xe51b0e2a, (q31_t)0x7d0f4218, (q31_t)0xe4b8cd11, (q31_t)0x7cf9aef0, (q31_t)0xe4569ccb, + (q31_t)0x7ce3ceb2, (q31_t)0xe3f47d96, (q31_t)0x7ccda169, (q31_t)0xe3926fad, (q31_t)0x7cb72724, (q31_t)0xe330734d, (q31_t)0x7ca05ff1, (q31_t)0xe2ce88b3, + (q31_t)0x7c894bde, (q31_t)0xe26cb01b, (q31_t)0x7c71eaf9, (q31_t)0xe20ae9c1, (q31_t)0x7c5a3d50, (q31_t)0xe1a935e2, (q31_t)0x7c4242f2, (q31_t)0xe14794ba, + (q31_t)0x7c29fbee, (q31_t)0xe0e60685, (q31_t)0x7c116853, (q31_t)0xe0848b7f, (q31_t)0x7bf88830, (q31_t)0xe02323e5, (q31_t)0x7bdf5b94, (q31_t)0xdfc1cff3, + (q31_t)0x7bc5e290, (q31_t)0xdf608fe4, (q31_t)0x7bac1d31, (q31_t)0xdeff63f4, (q31_t)0x7b920b89, (q31_t)0xde9e4c60, (q31_t)0x7b77ada8, (q31_t)0xde3d4964, + (q31_t)0x7b5d039e, (q31_t)0xdddc5b3b, (q31_t)0x7b420d7a, (q31_t)0xdd7b8220, (q31_t)0x7b26cb4f, (q31_t)0xdd1abe51, (q31_t)0x7b0b3d2c, (q31_t)0xdcba1008, + (q31_t)0x7aef6323, (q31_t)0xdc597781, (q31_t)0x7ad33d45, (q31_t)0xdbf8f4f8, (q31_t)0x7ab6cba4, (q31_t)0xdb9888a8, (q31_t)0x7a9a0e50, (q31_t)0xdb3832cd, + (q31_t)0x7a7d055b, (q31_t)0xdad7f3a2, (q31_t)0x7a5fb0d8, (q31_t)0xda77cb63, (q31_t)0x7a4210d8, (q31_t)0xda17ba4a, (q31_t)0x7a24256f, (q31_t)0xd9b7c094, + (q31_t)0x7a05eead, (q31_t)0xd957de7a, (q31_t)0x79e76ca7, (q31_t)0xd8f81439, (q31_t)0x79c89f6e, (q31_t)0xd898620c, (q31_t)0x79a98715, (q31_t)0xd838c82d, + (q31_t)0x798a23b1, (q31_t)0xd7d946d8, (q31_t)0x796a7554, (q31_t)0xd779de47, (q31_t)0x794a7c12, (q31_t)0xd71a8eb5, (q31_t)0x792a37fe, (q31_t)0xd6bb585e, + (q31_t)0x7909a92d, (q31_t)0xd65c3b7b, (q31_t)0x78e8cfb2, (q31_t)0xd5fd3848, (q31_t)0x78c7aba2, (q31_t)0xd59e4eff, (q31_t)0x78a63d11, (q31_t)0xd53f7fda, + (q31_t)0x78848414, (q31_t)0xd4e0cb15, (q31_t)0x786280bf, (q31_t)0xd48230e9, (q31_t)0x78403329, (q31_t)0xd423b191, (q31_t)0x781d9b65, (q31_t)0xd3c54d47, + (q31_t)0x77fab989, (q31_t)0xd3670446, (q31_t)0x77d78daa, (q31_t)0xd308d6c7, (q31_t)0x77b417df, (q31_t)0xd2aac504, (q31_t)0x7790583e, (q31_t)0xd24ccf39, + (q31_t)0x776c4edb, (q31_t)0xd1eef59e, (q31_t)0x7747fbce, (q31_t)0xd191386e, (q31_t)0x77235f2d, (q31_t)0xd13397e2, (q31_t)0x76fe790e, (q31_t)0xd0d61434, + (q31_t)0x76d94989, (q31_t)0xd078ad9e, (q31_t)0x76b3d0b4, (q31_t)0xd01b6459, (q31_t)0x768e0ea6, (q31_t)0xcfbe389f, (q31_t)0x76680376, (q31_t)0xcf612aaa, + (q31_t)0x7641af3d, (q31_t)0xcf043ab3, (q31_t)0x761b1211, (q31_t)0xcea768f2, (q31_t)0x75f42c0b, (q31_t)0xce4ab5a2, (q31_t)0x75ccfd42, (q31_t)0xcdee20fc, + (q31_t)0x75a585cf, (q31_t)0xcd91ab39, (q31_t)0x757dc5ca, (q31_t)0xcd355491, (q31_t)0x7555bd4c, (q31_t)0xccd91d3d, (q31_t)0x752d6c6c, (q31_t)0xcc7d0578, + (q31_t)0x7504d345, (q31_t)0xcc210d79, (q31_t)0x74dbf1ef, (q31_t)0xcbc53579, (q31_t)0x74b2c884, (q31_t)0xcb697db0, (q31_t)0x7489571c, (q31_t)0xcb0de658, + (q31_t)0x745f9dd1, (q31_t)0xcab26fa9, (q31_t)0x74359cbd, (q31_t)0xca5719db, (q31_t)0x740b53fb, (q31_t)0xc9fbe527, (q31_t)0x73e0c3a3, (q31_t)0xc9a0d1c5, + (q31_t)0x73b5ebd1, (q31_t)0xc945dfec, (q31_t)0x738acc9e, (q31_t)0xc8eb0fd6, (q31_t)0x735f6626, (q31_t)0xc89061ba, (q31_t)0x7333b883, (q31_t)0xc835d5d0, + (q31_t)0x7307c3d0, (q31_t)0xc7db6c50, (q31_t)0x72db8828, (q31_t)0xc7812572, (q31_t)0x72af05a7, (q31_t)0xc727016d, (q31_t)0x72823c67, (q31_t)0xc6cd0079, + (q31_t)0x72552c85, (q31_t)0xc67322ce, (q31_t)0x7227d61c, (q31_t)0xc61968a2, (q31_t)0x71fa3949, (q31_t)0xc5bfd22e, (q31_t)0x71cc5626, (q31_t)0xc5665fa9, + (q31_t)0x719e2cd2, (q31_t)0xc50d1149, (q31_t)0x716fbd68, (q31_t)0xc4b3e746, (q31_t)0x71410805, (q31_t)0xc45ae1d7, (q31_t)0x71120cc5, (q31_t)0xc4020133, + (q31_t)0x70e2cbc6, (q31_t)0xc3a94590, (q31_t)0x70b34525, (q31_t)0xc350af26, (q31_t)0x708378ff, (q31_t)0xc2f83e2a, (q31_t)0x70536771, (q31_t)0xc29ff2d4, + (q31_t)0x7023109a, (q31_t)0xc247cd5a, (q31_t)0x6ff27497, (q31_t)0xc1efcdf3, (q31_t)0x6fc19385, (q31_t)0xc197f4d4, (q31_t)0x6f906d84, (q31_t)0xc1404233, + (q31_t)0x6f5f02b2, (q31_t)0xc0e8b648, (q31_t)0x6f2d532c, (q31_t)0xc0915148, (q31_t)0x6efb5f12, (q31_t)0xc03a1368, (q31_t)0x6ec92683, (q31_t)0xbfe2fcdf, + (q31_t)0x6e96a99d, (q31_t)0xbf8c0de3, (q31_t)0x6e63e87f, (q31_t)0xbf3546a8, (q31_t)0x6e30e34a, (q31_t)0xbedea765, (q31_t)0x6dfd9a1c, (q31_t)0xbe88304f, + (q31_t)0x6dca0d14, (q31_t)0xbe31e19b, (q31_t)0x6d963c54, (q31_t)0xbddbbb7f, (q31_t)0x6d6227fa, (q31_t)0xbd85be30, (q31_t)0x6d2dd027, (q31_t)0xbd2fe9e2, + (q31_t)0x6cf934fc, (q31_t)0xbcda3ecb, (q31_t)0x6cc45698, (q31_t)0xbc84bd1f, (q31_t)0x6c8f351c, (q31_t)0xbc2f6513, (q31_t)0x6c59d0a9, (q31_t)0xbbda36dd, + (q31_t)0x6c242960, (q31_t)0xbb8532b0, (q31_t)0x6bee3f62, (q31_t)0xbb3058c0, (q31_t)0x6bb812d1, (q31_t)0xbadba943, (q31_t)0x6b81a3cd, (q31_t)0xba87246d, + (q31_t)0x6b4af279, (q31_t)0xba32ca71, (q31_t)0x6b13fef5, (q31_t)0xb9de9b83, (q31_t)0x6adcc964, (q31_t)0xb98a97d8, (q31_t)0x6aa551e9, (q31_t)0xb936bfa4, + (q31_t)0x6a6d98a4, (q31_t)0xb8e31319, (q31_t)0x6a359db9, (q31_t)0xb88f926d, (q31_t)0x69fd614a, (q31_t)0xb83c3dd1, (q31_t)0x69c4e37a, (q31_t)0xb7e9157a, + (q31_t)0x698c246c, (q31_t)0xb796199b, (q31_t)0x69532442, (q31_t)0xb7434a67, (q31_t)0x6919e320, (q31_t)0xb6f0a812, (q31_t)0x68e06129, (q31_t)0xb69e32cd, + (q31_t)0x68a69e81, (q31_t)0xb64beacd, (q31_t)0x686c9b4b, (q31_t)0xb5f9d043, (q31_t)0x683257ab, (q31_t)0xb5a7e362, (q31_t)0x67f7d3c5, (q31_t)0xb556245e, + (q31_t)0x67bd0fbd, (q31_t)0xb5049368, (q31_t)0x67820bb7, (q31_t)0xb4b330b3, (q31_t)0x6746c7d8, (q31_t)0xb461fc70, (q31_t)0x670b4444, (q31_t)0xb410f6d3, + (q31_t)0x66cf8120, (q31_t)0xb3c0200c, (q31_t)0x66937e91, (q31_t)0xb36f784f, (q31_t)0x66573cbb, (q31_t)0xb31effcc, (q31_t)0x661abbc5, (q31_t)0xb2ceb6b5, + (q31_t)0x65ddfbd3, (q31_t)0xb27e9d3c, (q31_t)0x65a0fd0b, (q31_t)0xb22eb392, (q31_t)0x6563bf92, (q31_t)0xb1def9e9, (q31_t)0x6526438f, (q31_t)0xb18f7071, + (q31_t)0x64e88926, (q31_t)0xb140175b, (q31_t)0x64aa907f, (q31_t)0xb0f0eeda, (q31_t)0x646c59bf, (q31_t)0xb0a1f71d, (q31_t)0x642de50d, (q31_t)0xb0533055, + (q31_t)0x63ef3290, (q31_t)0xb0049ab3, (q31_t)0x63b0426d, (q31_t)0xafb63667, (q31_t)0x637114cc, (q31_t)0xaf6803a2, (q31_t)0x6331a9d4, (q31_t)0xaf1a0293, + (q31_t)0x62f201ac, (q31_t)0xaecc336c, (q31_t)0x62b21c7b, (q31_t)0xae7e965b, (q31_t)0x6271fa69, (q31_t)0xae312b92, (q31_t)0x62319b9d, (q31_t)0xade3f33e, + (q31_t)0x61f1003f, (q31_t)0xad96ed92, (q31_t)0x61b02876, (q31_t)0xad4a1aba, (q31_t)0x616f146c, (q31_t)0xacfd7ae8, (q31_t)0x612dc447, (q31_t)0xacb10e4b, + (q31_t)0x60ec3830, (q31_t)0xac64d510, (q31_t)0x60aa7050, (q31_t)0xac18cf69, (q31_t)0x60686ccf, (q31_t)0xabccfd83, (q31_t)0x60262dd6, (q31_t)0xab815f8d, + (q31_t)0x5fe3b38d, (q31_t)0xab35f5b5, (q31_t)0x5fa0fe1f, (q31_t)0xaaeac02c, (q31_t)0x5f5e0db3, (q31_t)0xaa9fbf1e, (q31_t)0x5f1ae274, (q31_t)0xaa54f2ba, + (q31_t)0x5ed77c8a, (q31_t)0xaa0a5b2e, (q31_t)0x5e93dc1f, (q31_t)0xa9bff8a8, (q31_t)0x5e50015d, (q31_t)0xa975cb57, (q31_t)0x5e0bec6e, (q31_t)0xa92bd367, + (q31_t)0x5dc79d7c, (q31_t)0xa8e21106, (q31_t)0x5d8314b1, (q31_t)0xa8988463, (q31_t)0x5d3e5237, (q31_t)0xa84f2daa, (q31_t)0x5cf95638, (q31_t)0xa8060d08, + (q31_t)0x5cb420e0, (q31_t)0xa7bd22ac, (q31_t)0x5c6eb258, (q31_t)0xa7746ec0, (q31_t)0x5c290acc, (q31_t)0xa72bf174, (q31_t)0x5be32a67, (q31_t)0xa6e3aaf2, + (q31_t)0x5b9d1154, (q31_t)0xa69b9b68, (q31_t)0x5b56bfbd, (q31_t)0xa653c303, (q31_t)0x5b1035cf, (q31_t)0xa60c21ee, (q31_t)0x5ac973b5, (q31_t)0xa5c4b855, + (q31_t)0x5a82799a, (q31_t)0xa57d8666, (q31_t)0x5a3b47ab, (q31_t)0xa5368c4b, (q31_t)0x59f3de12, (q31_t)0xa4efca31, (q31_t)0x59ac3cfd, (q31_t)0xa4a94043, + (q31_t)0x59646498, (q31_t)0xa462eeac, (q31_t)0x591c550e, (q31_t)0xa41cd599, (q31_t)0x58d40e8c, (q31_t)0xa3d6f534, (q31_t)0x588b9140, (q31_t)0xa3914da8, + (q31_t)0x5842dd54, (q31_t)0xa34bdf20, (q31_t)0x57f9f2f8, (q31_t)0xa306a9c8, (q31_t)0x57b0d256, (q31_t)0xa2c1adc9, (q31_t)0x57677b9d, (q31_t)0xa27ceb4f, + (q31_t)0x571deefa, (q31_t)0xa2386284, (q31_t)0x56d42c99, (q31_t)0xa1f41392, (q31_t)0x568a34a9, (q31_t)0xa1affea3, (q31_t)0x56400758, (q31_t)0xa16c23e1, + (q31_t)0x55f5a4d2, (q31_t)0xa1288376, (q31_t)0x55ab0d46, (q31_t)0xa0e51d8c, (q31_t)0x556040e2, (q31_t)0xa0a1f24d, (q31_t)0x55153fd4, (q31_t)0xa05f01e1, + (q31_t)0x54ca0a4b, (q31_t)0xa01c4c73, (q31_t)0x547ea073, (q31_t)0x9fd9d22a, (q31_t)0x5433027d, (q31_t)0x9f979331, (q31_t)0x53e73097, (q31_t)0x9f558fb0, + (q31_t)0x539b2af0, (q31_t)0x9f13c7d0, (q31_t)0x534ef1b5, (q31_t)0x9ed23bb9, (q31_t)0x53028518, (q31_t)0x9e90eb94, (q31_t)0x52b5e546, (q31_t)0x9e4fd78a, + (q31_t)0x5269126e, (q31_t)0x9e0effc1, (q31_t)0x521c0cc2, (q31_t)0x9dce6463, (q31_t)0x51ced46e, (q31_t)0x9d8e0597, (q31_t)0x518169a5, (q31_t)0x9d4de385, + (q31_t)0x5133cc94, (q31_t)0x9d0dfe54, (q31_t)0x50e5fd6d, (q31_t)0x9cce562c, (q31_t)0x5097fc5e, (q31_t)0x9c8eeb34, (q31_t)0x5049c999, (q31_t)0x9c4fbd93, + (q31_t)0x4ffb654d, (q31_t)0x9c10cd70, (q31_t)0x4faccfab, (q31_t)0x9bd21af3, (q31_t)0x4f5e08e3, (q31_t)0x9b93a641, (q31_t)0x4f0f1126, (q31_t)0x9b556f81, + (q31_t)0x4ebfe8a5, (q31_t)0x9b1776da, (q31_t)0x4e708f8f, (q31_t)0x9ad9bc71, (q31_t)0x4e210617, (q31_t)0x9a9c406e, (q31_t)0x4dd14c6e, (q31_t)0x9a5f02f5, + (q31_t)0x4d8162c4, (q31_t)0x9a22042d, (q31_t)0x4d31494b, (q31_t)0x99e5443b, (q31_t)0x4ce10034, (q31_t)0x99a8c345, (q31_t)0x4c9087b1, (q31_t)0x996c816f, + (q31_t)0x4c3fdff4, (q31_t)0x99307ee0, (q31_t)0x4bef092d, (q31_t)0x98f4bbbc, (q31_t)0x4b9e0390, (q31_t)0x98b93828, (q31_t)0x4b4ccf4d, (q31_t)0x987df449, + (q31_t)0x4afb6c98, (q31_t)0x9842f043, (q31_t)0x4aa9dba2, (q31_t)0x98082c3b, (q31_t)0x4a581c9e, (q31_t)0x97cda855, (q31_t)0x4a062fbd, (q31_t)0x979364b5, + (q31_t)0x49b41533, (q31_t)0x9759617f, (q31_t)0x4961cd33, (q31_t)0x971f9ed7, (q31_t)0x490f57ee, (q31_t)0x96e61ce0, (q31_t)0x48bcb599, (q31_t)0x96acdbbe, + (q31_t)0x4869e665, (q31_t)0x9673db94, (q31_t)0x4816ea86, (q31_t)0x963b1c86, (q31_t)0x47c3c22f, (q31_t)0x96029eb6, (q31_t)0x47706d93, (q31_t)0x95ca6247, + (q31_t)0x471cece7, (q31_t)0x9592675c, (q31_t)0x46c9405c, (q31_t)0x955aae17, (q31_t)0x46756828, (q31_t)0x9523369c, (q31_t)0x4621647d, (q31_t)0x94ec010b, + (q31_t)0x45cd358f, (q31_t)0x94b50d87, (q31_t)0x4578db93, (q31_t)0x947e5c33, (q31_t)0x452456bd, (q31_t)0x9447ed2f, (q31_t)0x44cfa740, (q31_t)0x9411c09e, + (q31_t)0x447acd50, (q31_t)0x93dbd6a0, (q31_t)0x4425c923, (q31_t)0x93a62f57, (q31_t)0x43d09aed, (q31_t)0x9370cae4, (q31_t)0x437b42e1, (q31_t)0x933ba968, + (q31_t)0x4325c135, (q31_t)0x9306cb04, (q31_t)0x42d0161e, (q31_t)0x92d22fd9, (q31_t)0x427a41d0, (q31_t)0x929dd806, (q31_t)0x42244481, (q31_t)0x9269c3ac, + (q31_t)0x41ce1e65, (q31_t)0x9235f2ec, (q31_t)0x4177cfb1, (q31_t)0x920265e4, (q31_t)0x4121589b, (q31_t)0x91cf1cb6, (q31_t)0x40cab958, (q31_t)0x919c1781, + (q31_t)0x4073f21d, (q31_t)0x91695663, (q31_t)0x401d0321, (q31_t)0x9136d97d, (q31_t)0x3fc5ec98, (q31_t)0x9104a0ee, (q31_t)0x3f6eaeb8, (q31_t)0x90d2acd4, + (q31_t)0x3f1749b8, (q31_t)0x90a0fd4e, (q31_t)0x3ebfbdcd, (q31_t)0x906f927c, (q31_t)0x3e680b2c, (q31_t)0x903e6c7b, (q31_t)0x3e10320d, (q31_t)0x900d8b69, + (q31_t)0x3db832a6, (q31_t)0x8fdcef66, (q31_t)0x3d600d2c, (q31_t)0x8fac988f, (q31_t)0x3d07c1d6, (q31_t)0x8f7c8701, (q31_t)0x3caf50da, (q31_t)0x8f4cbadb, + (q31_t)0x3c56ba70, (q31_t)0x8f1d343a, (q31_t)0x3bfdfecd, (q31_t)0x8eedf33b, (q31_t)0x3ba51e29, (q31_t)0x8ebef7fb, (q31_t)0x3b4c18ba, (q31_t)0x8e904298, + (q31_t)0x3af2eeb7, (q31_t)0x8e61d32e, (q31_t)0x3a99a057, (q31_t)0x8e33a9da, (q31_t)0x3a402dd2, (q31_t)0x8e05c6b7, (q31_t)0x39e6975e, (q31_t)0x8dd829e4, + (q31_t)0x398cdd32, (q31_t)0x8daad37b, (q31_t)0x3932ff87, (q31_t)0x8d7dc399, (q31_t)0x38d8fe93, (q31_t)0x8d50fa59, (q31_t)0x387eda8e, (q31_t)0x8d2477d8, + (q31_t)0x382493b0, (q31_t)0x8cf83c30, (q31_t)0x37ca2a30, (q31_t)0x8ccc477d, (q31_t)0x376f9e46, (q31_t)0x8ca099da, (q31_t)0x3714f02a, (q31_t)0x8c753362, + (q31_t)0x36ba2014, (q31_t)0x8c4a142f, (q31_t)0x365f2e3b, (q31_t)0x8c1f3c5d, (q31_t)0x36041ad9, (q31_t)0x8bf4ac05, (q31_t)0x35a8e625, (q31_t)0x8bca6343, + (q31_t)0x354d9057, (q31_t)0x8ba0622f, (q31_t)0x34f219a8, (q31_t)0x8b76a8e4, (q31_t)0x34968250, (q31_t)0x8b4d377c, (q31_t)0x343aca87, (q31_t)0x8b240e11, + (q31_t)0x33def287, (q31_t)0x8afb2cbb, (q31_t)0x3382fa88, (q31_t)0x8ad29394, (q31_t)0x3326e2c3, (q31_t)0x8aaa42b4, (q31_t)0x32caab6f, (q31_t)0x8a823a36, + (q31_t)0x326e54c7, (q31_t)0x8a5a7a31, (q31_t)0x3211df04, (q31_t)0x8a3302be, (q31_t)0x31b54a5e, (q31_t)0x8a0bd3f5, (q31_t)0x3158970e, (q31_t)0x89e4edef, + (q31_t)0x30fbc54d, (q31_t)0x89be50c3, (q31_t)0x309ed556, (q31_t)0x8997fc8a, (q31_t)0x3041c761, (q31_t)0x8971f15a, (q31_t)0x2fe49ba7, (q31_t)0x894c2f4c, + (q31_t)0x2f875262, (q31_t)0x8926b677, (q31_t)0x2f29ebcc, (q31_t)0x890186f2, (q31_t)0x2ecc681e, (q31_t)0x88dca0d3, (q31_t)0x2e6ec792, (q31_t)0x88b80432, + (q31_t)0x2e110a62, (q31_t)0x8893b125, (q31_t)0x2db330c7, (q31_t)0x886fa7c2, (q31_t)0x2d553afc, (q31_t)0x884be821, (q31_t)0x2cf72939, (q31_t)0x88287256, + (q31_t)0x2c98fbba, (q31_t)0x88054677, (q31_t)0x2c3ab2b9, (q31_t)0x87e2649b, (q31_t)0x2bdc4e6f, (q31_t)0x87bfccd7, (q31_t)0x2b7dcf17, (q31_t)0x879d7f41, + (q31_t)0x2b1f34eb, (q31_t)0x877b7bec, (q31_t)0x2ac08026, (q31_t)0x8759c2ef, (q31_t)0x2a61b101, (q31_t)0x8738545e, (q31_t)0x2a02c7b8, (q31_t)0x8717304e, + (q31_t)0x29a3c485, (q31_t)0x86f656d3, (q31_t)0x2944a7a2, (q31_t)0x86d5c802, (q31_t)0x28e5714b, (q31_t)0x86b583ee, (q31_t)0x288621b9, (q31_t)0x86958aac, + (q31_t)0x2826b928, (q31_t)0x8675dc4f, (q31_t)0x27c737d3, (q31_t)0x865678eb, (q31_t)0x27679df4, (q31_t)0x86376092, (q31_t)0x2707ebc7, (q31_t)0x86189359, + (q31_t)0x26a82186, (q31_t)0x85fa1153, (q31_t)0x26483f6c, (q31_t)0x85dbda91, (q31_t)0x25e845b6, (q31_t)0x85bdef28, (q31_t)0x2588349d, (q31_t)0x85a04f28, + (q31_t)0x25280c5e, (q31_t)0x8582faa5, (q31_t)0x24c7cd33, (q31_t)0x8565f1b0, (q31_t)0x24677758, (q31_t)0x8549345c, (q31_t)0x24070b08, (q31_t)0x852cc2bb, + (q31_t)0x23a6887f, (q31_t)0x85109cdd, (q31_t)0x2345eff8, (q31_t)0x84f4c2d4, (q31_t)0x22e541af, (q31_t)0x84d934b1, (q31_t)0x22847de0, (q31_t)0x84bdf286, + (q31_t)0x2223a4c5, (q31_t)0x84a2fc62, (q31_t)0x21c2b69c, (q31_t)0x84885258, (q31_t)0x2161b3a0, (q31_t)0x846df477, (q31_t)0x21009c0c, (q31_t)0x8453e2cf, + (q31_t)0x209f701c, (q31_t)0x843a1d70, (q31_t)0x203e300d, (q31_t)0x8420a46c, (q31_t)0x1fdcdc1b, (q31_t)0x840777d0, (q31_t)0x1f7b7481, (q31_t)0x83ee97ad, + (q31_t)0x1f19f97b, (q31_t)0x83d60412, (q31_t)0x1eb86b46, (q31_t)0x83bdbd0e, (q31_t)0x1e56ca1e, (q31_t)0x83a5c2b0, (q31_t)0x1df5163f, (q31_t)0x838e1507, + (q31_t)0x1d934fe5, (q31_t)0x8376b422, (q31_t)0x1d31774d, (q31_t)0x835fa00f, (q31_t)0x1ccf8cb3, (q31_t)0x8348d8dc, (q31_t)0x1c6d9053, (q31_t)0x83325e97, + (q31_t)0x1c0b826a, (q31_t)0x831c314e, (q31_t)0x1ba96335, (q31_t)0x83065110, (q31_t)0x1b4732ef, (q31_t)0x82f0bde8, (q31_t)0x1ae4f1d6, (q31_t)0x82db77e5, + (q31_t)0x1a82a026, (q31_t)0x82c67f14, (q31_t)0x1a203e1b, (q31_t)0x82b1d381, (q31_t)0x19bdcbf3, (q31_t)0x829d753a, (q31_t)0x195b49ea, (q31_t)0x8289644b, + (q31_t)0x18f8b83c, (q31_t)0x8275a0c0, (q31_t)0x18961728, (q31_t)0x82622aa6, (q31_t)0x183366e9, (q31_t)0x824f0208, (q31_t)0x17d0a7bc, (q31_t)0x823c26f3, + (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x170afd8d, (q31_t)0x82175990, (q31_t)0x16a81305, (q31_t)0x82056758, (q31_t)0x16451a83, (q31_t)0x81f3c2d7, + (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x157f0086, (q31_t)0x81d16321, (q31_t)0x151bdf86, (q31_t)0x81c0a801, (q31_t)0x14b8b17f, (q31_t)0x81b03ac2, + (q31_t)0x145576b1, (q31_t)0x81a01b6d, (q31_t)0x13f22f58, (q31_t)0x81904a0c, (q31_t)0x138edbb1, (q31_t)0x8180c6a9, (q31_t)0x132b7bf9, (q31_t)0x8171914e, + (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x1264994e, (q31_t)0x815410d4, (q31_t)0x120116d5, (q31_t)0x8145c5c7, (q31_t)0x119d8941, (q31_t)0x8137c8e6, + (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0x10d64dbd, (q31_t)0x811cb9ca, (q31_t)0x1072a048, (q31_t)0x810fa7a0, (q31_t)0x100ee8ad, (q31_t)0x8102e3c4, + (q31_t)0x0fab272b, (q31_t)0x80f66e3c, (q31_t)0x0f475bff, (q31_t)0x80ea4712, (q31_t)0x0ee38766, (q31_t)0x80de6e4c, (q31_t)0x0e7fa99e, (q31_t)0x80d2e3f2, + (q31_t)0x0e1bc2e4, (q31_t)0x80c7a80a, (q31_t)0x0db7d376, (q31_t)0x80bcba9d, (q31_t)0x0d53db92, (q31_t)0x80b21baf, (q31_t)0x0cefdb76, (q31_t)0x80a7cb49, + (q31_t)0x0c8bd35e, (q31_t)0x809dc971, (q31_t)0x0c27c389, (q31_t)0x8094162c, (q31_t)0x0bc3ac35, (q31_t)0x808ab180, (q31_t)0x0b5f8d9f, (q31_t)0x80819b74, + (q31_t)0x0afb6805, (q31_t)0x8078d40d, (q31_t)0x0a973ba5, (q31_t)0x80705b50, (q31_t)0x0a3308bd, (q31_t)0x80683143, (q31_t)0x09cecf89, (q31_t)0x806055eb, + (q31_t)0x096a9049, (q31_t)0x8058c94c, (q31_t)0x09064b3a, (q31_t)0x80518b6b, (q31_t)0x08a2009a, (q31_t)0x804a9c4d, (q31_t)0x083db0a7, (q31_t)0x8043fbf6, + (q31_t)0x07d95b9e, (q31_t)0x803daa6a, (q31_t)0x077501be, (q31_t)0x8037a7ac, (q31_t)0x0710a345, (q31_t)0x8031f3c2, (q31_t)0x06ac406f, (q31_t)0x802c8ead, + (q31_t)0x0647d97c, (q31_t)0x80277872, (q31_t)0x05e36ea9, (q31_t)0x8022b114, (q31_t)0x057f0035, (q31_t)0x801e3895, (q31_t)0x051a8e5c, (q31_t)0x801a0ef8, + (q31_t)0x04b6195d, (q31_t)0x80163440, (q31_t)0x0451a177, (q31_t)0x8012a86f, (q31_t)0x03ed26e6, (q31_t)0x800f6b88, (q31_t)0x0388a9ea, (q31_t)0x800c7d8c, + (q31_t)0x03242abf, (q31_t)0x8009de7e, (q31_t)0x02bfa9a4, (q31_t)0x80078e5e, (q31_t)0x025b26d7, (q31_t)0x80058d2f, (q31_t)0x01f6a297, (q31_t)0x8003daf1, + (q31_t)0x01921d20, (q31_t)0x800277a6, (q31_t)0x012d96b1, (q31_t)0x8001634e, (q31_t)0x00c90f88, (q31_t)0x80009dea, (q31_t)0x006487e3, (q31_t)0x8000277a +}; + const q31_t cos_factorsQ31_512[512] = { + (q31_t)0x7ffff621, (q31_t)0x7fffa72c, (q31_t)0x7fff0943, (q31_t)0x7ffe1c65, (q31_t)0x7ffce093, (q31_t)0x7ffb55ce, + (q31_t)0x7ff97c18, (q31_t)0x7ff75370, + (q31_t)0x7ff4dbd9, (q31_t)0x7ff21553, (q31_t)0x7feeffe1, (q31_t)0x7feb9b85, (q31_t)0x7fe7e841, (q31_t)0x7fe3e616, + (q31_t)0x7fdf9508, (q31_t)0x7fdaf519, + (q31_t)0x7fd6064c, (q31_t)0x7fd0c8a3, (q31_t)0x7fcb3c23, (q31_t)0x7fc560cf, (q31_t)0x7fbf36aa, (q31_t)0x7fb8bdb8, + (q31_t)0x7fb1f5fc, (q31_t)0x7faadf7c, + (q31_t)0x7fa37a3c, (q31_t)0x7f9bc640, (q31_t)0x7f93c38c, (q31_t)0x7f8b7227, (q31_t)0x7f82d214, (q31_t)0x7f79e35a, + (q31_t)0x7f70a5fe, (q31_t)0x7f671a05, + (q31_t)0x7f5d3f75, (q31_t)0x7f531655, (q31_t)0x7f489eaa, (q31_t)0x7f3dd87c, (q31_t)0x7f32c3d1, (q31_t)0x7f2760af, + (q31_t)0x7f1baf1e, (q31_t)0x7f0faf25, + (q31_t)0x7f0360cb, (q31_t)0x7ef6c418, (q31_t)0x7ee9d914, (q31_t)0x7edc9fc6, (q31_t)0x7ecf1837, (q31_t)0x7ec14270, + (q31_t)0x7eb31e78, (q31_t)0x7ea4ac58, + (q31_t)0x7e95ec1a, (q31_t)0x7e86ddc6, (q31_t)0x7e778166, (q31_t)0x7e67d703, (q31_t)0x7e57dea7, (q31_t)0x7e47985b, + (q31_t)0x7e37042a, (q31_t)0x7e26221f, + (q31_t)0x7e14f242, (q31_t)0x7e0374a0, (q31_t)0x7df1a942, (q31_t)0x7ddf9034, (q31_t)0x7dcd2981, (q31_t)0x7dba7534, + (q31_t)0x7da77359, (q31_t)0x7d9423fc, + (q31_t)0x7d808728, (q31_t)0x7d6c9ce9, (q31_t)0x7d58654d, (q31_t)0x7d43e05e, (q31_t)0x7d2f0e2b, (q31_t)0x7d19eebf, + (q31_t)0x7d048228, (q31_t)0x7ceec873, + (q31_t)0x7cd8c1ae, (q31_t)0x7cc26de5, (q31_t)0x7cabcd28, (q31_t)0x7c94df83, (q31_t)0x7c7da505, (q31_t)0x7c661dbc, + (q31_t)0x7c4e49b7, (q31_t)0x7c362904, + (q31_t)0x7c1dbbb3, (q31_t)0x7c0501d2, (q31_t)0x7bebfb70, (q31_t)0x7bd2a89e, (q31_t)0x7bb9096b, (q31_t)0x7b9f1de6, + (q31_t)0x7b84e61f, (q31_t)0x7b6a6227, + (q31_t)0x7b4f920e, (q31_t)0x7b3475e5, (q31_t)0x7b190dbc, (q31_t)0x7afd59a4, (q31_t)0x7ae159ae, (q31_t)0x7ac50dec, + (q31_t)0x7aa8766f, (q31_t)0x7a8b9348, + (q31_t)0x7a6e648a, (q31_t)0x7a50ea47, (q31_t)0x7a332490, (q31_t)0x7a151378, (q31_t)0x79f6b711, (q31_t)0x79d80f6f, + (q31_t)0x79b91ca4, (q31_t)0x7999dec4, + (q31_t)0x797a55e0, (q31_t)0x795a820e, (q31_t)0x793a6361, (q31_t)0x7919f9ec, (q31_t)0x78f945c3, (q31_t)0x78d846fb, + (q31_t)0x78b6fda8, (q31_t)0x789569df, + (q31_t)0x78738bb3, (q31_t)0x7851633b, (q31_t)0x782ef08b, (q31_t)0x780c33b8, (q31_t)0x77e92cd9, (q31_t)0x77c5dc01, + (q31_t)0x77a24148, (q31_t)0x777e5cc3, + (q31_t)0x775a2e89, (q31_t)0x7735b6af, (q31_t)0x7710f54c, (q31_t)0x76ebea77, (q31_t)0x76c69647, (q31_t)0x76a0f8d2, + (q31_t)0x767b1231, (q31_t)0x7654e279, + (q31_t)0x762e69c4, (q31_t)0x7607a828, (q31_t)0x75e09dbd, (q31_t)0x75b94a9c, (q31_t)0x7591aedd, (q31_t)0x7569ca99, + (q31_t)0x75419de7, (q31_t)0x751928e0, + (q31_t)0x74f06b9e, (q31_t)0x74c7663a, (q31_t)0x749e18cd, (q31_t)0x74748371, (q31_t)0x744aa63f, (q31_t)0x74208150, + (q31_t)0x73f614c0, (q31_t)0x73cb60a8, + (q31_t)0x73a06522, (q31_t)0x73752249, (q31_t)0x73499838, (q31_t)0x731dc70a, (q31_t)0x72f1aed9, (q31_t)0x72c54fc1, + (q31_t)0x7298a9dd, (q31_t)0x726bbd48, + (q31_t)0x723e8a20, (q31_t)0x7211107e, (q31_t)0x71e35080, (q31_t)0x71b54a41, (q31_t)0x7186fdde, (q31_t)0x71586b74, + (q31_t)0x7129931f, (q31_t)0x70fa74fc, + (q31_t)0x70cb1128, (q31_t)0x709b67c0, (q31_t)0x706b78e3, (q31_t)0x703b44ad, (q31_t)0x700acb3c, (q31_t)0x6fda0cae, + (q31_t)0x6fa90921, (q31_t)0x6f77c0b3, + (q31_t)0x6f463383, (q31_t)0x6f1461b0, (q31_t)0x6ee24b57, (q31_t)0x6eaff099, (q31_t)0x6e7d5193, (q31_t)0x6e4a6e66, + (q31_t)0x6e174730, (q31_t)0x6de3dc11, + (q31_t)0x6db02d29, (q31_t)0x6d7c3a98, (q31_t)0x6d48047e, (q31_t)0x6d138afb, (q31_t)0x6cdece2f, (q31_t)0x6ca9ce3b, + (q31_t)0x6c748b3f, (q31_t)0x6c3f055d, + (q31_t)0x6c093cb6, (q31_t)0x6bd3316a, (q31_t)0x6b9ce39b, (q31_t)0x6b66536b, (q31_t)0x6b2f80fb, (q31_t)0x6af86c6c, + (q31_t)0x6ac115e2, (q31_t)0x6a897d7d, + (q31_t)0x6a51a361, (q31_t)0x6a1987b0, (q31_t)0x69e12a8c, (q31_t)0x69a88c19, (q31_t)0x696fac78, (q31_t)0x69368bce, + (q31_t)0x68fd2a3d, (q31_t)0x68c387e9, + (q31_t)0x6889a4f6, (q31_t)0x684f8186, (q31_t)0x68151dbe, (q31_t)0x67da79c3, (q31_t)0x679f95b7, (q31_t)0x676471c0, + (q31_t)0x67290e02, (q31_t)0x66ed6aa1, + (q31_t)0x66b187c3, (q31_t)0x6675658c, (q31_t)0x66390422, (q31_t)0x65fc63a9, (q31_t)0x65bf8447, (q31_t)0x65826622, + (q31_t)0x6545095f, (q31_t)0x65076e25, + (q31_t)0x64c99498, (q31_t)0x648b7ce0, (q31_t)0x644d2722, (q31_t)0x640e9386, (q31_t)0x63cfc231, (q31_t)0x6390b34a, + (q31_t)0x635166f9, (q31_t)0x6311dd64, + (q31_t)0x62d216b3, (q31_t)0x6292130c, (q31_t)0x6251d298, (q31_t)0x6211557e, (q31_t)0x61d09be5, (q31_t)0x618fa5f7, + (q31_t)0x614e73da, (q31_t)0x610d05b7, + (q31_t)0x60cb5bb7, (q31_t)0x60897601, (q31_t)0x604754bf, (q31_t)0x6004f819, (q31_t)0x5fc26038, (q31_t)0x5f7f8d46, + (q31_t)0x5f3c7f6b, (q31_t)0x5ef936d1, + (q31_t)0x5eb5b3a2, (q31_t)0x5e71f606, (q31_t)0x5e2dfe29, (q31_t)0x5de9cc33, (q31_t)0x5da5604f, (q31_t)0x5d60baa7, + (q31_t)0x5d1bdb65, (q31_t)0x5cd6c2b5, + (q31_t)0x5c9170bf, (q31_t)0x5c4be5b0, (q31_t)0x5c0621b2, (q31_t)0x5bc024f0, (q31_t)0x5b79ef96, (q31_t)0x5b3381ce, + (q31_t)0x5aecdbc5, (q31_t)0x5aa5fda5, + (q31_t)0x5a5ee79a, (q31_t)0x5a1799d1, (q31_t)0x59d01475, (q31_t)0x598857b2, (q31_t)0x594063b5, (q31_t)0x58f838a9, + (q31_t)0x58afd6bd, (q31_t)0x58673e1b, + (q31_t)0x581e6ef1, (q31_t)0x57d5696d, (q31_t)0x578c2dba, (q31_t)0x5742bc06, (q31_t)0x56f9147e, (q31_t)0x56af3750, + (q31_t)0x566524aa, (q31_t)0x561adcb9, + (q31_t)0x55d05faa, (q31_t)0x5585adad, (q31_t)0x553ac6ee, (q31_t)0x54efab9c, (q31_t)0x54a45be6, (q31_t)0x5458d7f9, + (q31_t)0x540d2005, (q31_t)0x53c13439, + (q31_t)0x537514c2, (q31_t)0x5328c1d0, (q31_t)0x52dc3b92, (q31_t)0x528f8238, (q31_t)0x524295f0, (q31_t)0x51f576ea, + (q31_t)0x51a82555, (q31_t)0x515aa162, + (q31_t)0x510ceb40, (q31_t)0x50bf031f, (q31_t)0x5070e92f, (q31_t)0x50229da1, (q31_t)0x4fd420a4, (q31_t)0x4f857269, + (q31_t)0x4f369320, (q31_t)0x4ee782fb, + (q31_t)0x4e984229, (q31_t)0x4e48d0dd, (q31_t)0x4df92f46, (q31_t)0x4da95d96, (q31_t)0x4d595bfe, (q31_t)0x4d092ab0, + (q31_t)0x4cb8c9dd, (q31_t)0x4c6839b7, + (q31_t)0x4c177a6e, (q31_t)0x4bc68c36, (q31_t)0x4b756f40, (q31_t)0x4b2423be, (q31_t)0x4ad2a9e2, (q31_t)0x4a8101de, + (q31_t)0x4a2f2be6, (q31_t)0x49dd282a, + (q31_t)0x498af6df, (q31_t)0x49389836, (q31_t)0x48e60c62, (q31_t)0x48935397, (q31_t)0x48406e08, (q31_t)0x47ed5be6, + (q31_t)0x479a1d67, (q31_t)0x4746b2bc, + (q31_t)0x46f31c1a, (q31_t)0x469f59b4, (q31_t)0x464b6bbe, (q31_t)0x45f7526b, (q31_t)0x45a30df0, (q31_t)0x454e9e80, + (q31_t)0x44fa0450, (q31_t)0x44a53f93, + (q31_t)0x4450507e, (q31_t)0x43fb3746, (q31_t)0x43a5f41e, (q31_t)0x4350873c, (q31_t)0x42faf0d4, (q31_t)0x42a5311b, + (q31_t)0x424f4845, (q31_t)0x41f93689, + (q31_t)0x41a2fc1a, (q31_t)0x414c992f, (q31_t)0x40f60dfb, (q31_t)0x409f5ab6, (q31_t)0x40487f94, (q31_t)0x3ff17cca, + (q31_t)0x3f9a5290, (q31_t)0x3f430119, + (q31_t)0x3eeb889c, (q31_t)0x3e93e950, (q31_t)0x3e3c2369, (q31_t)0x3de4371f, (q31_t)0x3d8c24a8, (q31_t)0x3d33ec39, + (q31_t)0x3cdb8e09, (q31_t)0x3c830a50, + (q31_t)0x3c2a6142, (q31_t)0x3bd19318, (q31_t)0x3b78a007, (q31_t)0x3b1f8848, (q31_t)0x3ac64c0f, (q31_t)0x3a6ceb96, + (q31_t)0x3a136712, (q31_t)0x39b9bebc, + (q31_t)0x395ff2c9, (q31_t)0x39060373, (q31_t)0x38abf0ef, (q31_t)0x3851bb77, (q31_t)0x37f76341, (q31_t)0x379ce885, + (q31_t)0x37424b7b, (q31_t)0x36e78c5b, + (q31_t)0x368cab5c, (q31_t)0x3631a8b8, (q31_t)0x35d684a6, (q31_t)0x357b3f5d, (q31_t)0x351fd918, (q31_t)0x34c4520d, + (q31_t)0x3468aa76, (q31_t)0x340ce28b, + (q31_t)0x33b0fa84, (q31_t)0x3354f29b, (q31_t)0x32f8cb07, (q31_t)0x329c8402, (q31_t)0x32401dc6, (q31_t)0x31e39889, + (q31_t)0x3186f487, (q31_t)0x312a31f8, + (q31_t)0x30cd5115, (q31_t)0x30705217, (q31_t)0x30133539, (q31_t)0x2fb5fab2, (q31_t)0x2f58a2be, (q31_t)0x2efb2d95, + (q31_t)0x2e9d9b70, (q31_t)0x2e3fec8b, + (q31_t)0x2de2211e, (q31_t)0x2d843964, (q31_t)0x2d263596, (q31_t)0x2cc815ee, (q31_t)0x2c69daa6, (q31_t)0x2c0b83fa, + (q31_t)0x2bad1221, (q31_t)0x2b4e8558, + (q31_t)0x2aefddd8, (q31_t)0x2a911bdc, (q31_t)0x2a323f9e, (q31_t)0x29d34958, (q31_t)0x29743946, (q31_t)0x29150fa1, + (q31_t)0x28b5cca5, (q31_t)0x2856708d, + (q31_t)0x27f6fb92, (q31_t)0x27976df1, (q31_t)0x2737c7e3, (q31_t)0x26d809a5, (q31_t)0x26783370, (q31_t)0x26184581, + (q31_t)0x25b84012, (q31_t)0x2558235f, + (q31_t)0x24f7efa2, (q31_t)0x2497a517, (q31_t)0x243743fa, (q31_t)0x23d6cc87, (q31_t)0x23763ef7, (q31_t)0x23159b88, + (q31_t)0x22b4e274, (q31_t)0x225413f8, + (q31_t)0x21f3304f, (q31_t)0x219237b5, (q31_t)0x21312a65, (q31_t)0x20d0089c, (q31_t)0x206ed295, (q31_t)0x200d888d, + (q31_t)0x1fac2abf, (q31_t)0x1f4ab968, + (q31_t)0x1ee934c3, (q31_t)0x1e879d0d, (q31_t)0x1e25f282, (q31_t)0x1dc4355e, (q31_t)0x1d6265dd, (q31_t)0x1d00843d, + (q31_t)0x1c9e90b8, (q31_t)0x1c3c8b8c, + (q31_t)0x1bda74f6, (q31_t)0x1b784d30, (q31_t)0x1b161479, (q31_t)0x1ab3cb0d, (q31_t)0x1a517128, (q31_t)0x19ef0707, + (q31_t)0x198c8ce7, (q31_t)0x192a0304, + (q31_t)0x18c7699b, (q31_t)0x1864c0ea, (q31_t)0x1802092c, (q31_t)0x179f429f, (q31_t)0x173c6d80, (q31_t)0x16d98a0c, + (q31_t)0x1676987f, (q31_t)0x16139918, + (q31_t)0x15b08c12, (q31_t)0x154d71aa, (q31_t)0x14ea4a1f, (q31_t)0x148715ae, (q31_t)0x1423d492, (q31_t)0x13c0870a, + (q31_t)0x135d2d53, (q31_t)0x12f9c7aa, + (q31_t)0x1296564d, (q31_t)0x1232d979, (q31_t)0x11cf516a, (q31_t)0x116bbe60, (q31_t)0x11082096, (q31_t)0x10a4784b, + (q31_t)0x1040c5bb, (q31_t)0xfdd0926, + (q31_t)0xf7942c7, (q31_t)0xf1572dc, (q31_t)0xeb199a4, (q31_t)0xe4db75b, (q31_t)0xde9cc40, (q31_t)0xd85d88f, (q31_t)0xd21dc87, + (q31_t)0xcbdd865, + (q31_t)0xc59cc68, (q31_t)0xbf5b8cb, (q31_t)0xb919dcf, (q31_t)0xb2d7baf, (q31_t)0xac952aa, (q31_t)0xa6522fe, (q31_t)0xa00ece8, + (q31_t)0x99cb0a7, + (q31_t)0x9386e78, (q31_t)0x8d42699, (q31_t)0x86fd947, (q31_t)0x80b86c2, (q31_t)0x7a72f45, (q31_t)0x742d311, (q31_t)0x6de7262, + (q31_t)0x67a0d76, + (q31_t)0x615a48b, (q31_t)0x5b137df, (q31_t)0x54cc7b1, (q31_t)0x4e8543e, (q31_t)0x483ddc3, (q31_t)0x41f6480, (q31_t)0x3bae8b2, + (q31_t)0x3566a96, + (q31_t)0x2f1ea6c, (q31_t)0x28d6870, (q31_t)0x228e4e2, (q31_t)0x1c45ffe, (q31_t)0x15fda03, (q31_t)0xfb5330, (q31_t)0x96cbc1, + (q31_t)0x3243f5 +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048) + const q31_t WeightsQ31_2048[4096] = { + (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7ffffd88, (q31_t)0xffe6de05, (q31_t)0x7ffff621, (q31_t)0xffcdbc0b, (q31_t)0x7fffe9cb, (q31_t)0xffb49a12, + (q31_t)0x7fffd886, (q31_t)0xff9b781d, (q31_t)0x7fffc251, (q31_t)0xff82562c, (q31_t)0x7fffa72c, (q31_t)0xff69343f, (q31_t)0x7fff8719, (q31_t)0xff501258, + (q31_t)0x7fff6216, (q31_t)0xff36f078, (q31_t)0x7fff3824, (q31_t)0xff1dcea0, (q31_t)0x7fff0943, (q31_t)0xff04acd0, (q31_t)0x7ffed572, (q31_t)0xfeeb8b0a, + (q31_t)0x7ffe9cb2, (q31_t)0xfed2694f, (q31_t)0x7ffe5f03, (q31_t)0xfeb947a0, (q31_t)0x7ffe1c65, (q31_t)0xfea025fd, (q31_t)0x7ffdd4d7, (q31_t)0xfe870467, + (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ffd36ee, (q31_t)0xfe54c169, (q31_t)0x7ffce093, (q31_t)0xfe3ba002, (q31_t)0x7ffc8549, (q31_t)0xfe227eac, + (q31_t)0x7ffc250f, (q31_t)0xfe095d69, (q31_t)0x7ffbbfe6, (q31_t)0xfdf03c3a, (q31_t)0x7ffb55ce, (q31_t)0xfdd71b1e, (q31_t)0x7ffae6c7, (q31_t)0xfdbdfa18, + (q31_t)0x7ffa72d1, (q31_t)0xfda4d929, (q31_t)0x7ff9f9ec, (q31_t)0xfd8bb850, (q31_t)0x7ff97c18, (q31_t)0xfd729790, (q31_t)0x7ff8f954, (q31_t)0xfd5976e9, + (q31_t)0x7ff871a2, (q31_t)0xfd40565c, (q31_t)0x7ff7e500, (q31_t)0xfd2735ea, (q31_t)0x7ff75370, (q31_t)0xfd0e1594, (q31_t)0x7ff6bcf0, (q31_t)0xfcf4f55c, + (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7ff58125, (q31_t)0xfcc2b545, (q31_t)0x7ff4dbd9, (q31_t)0xfca9956a, (q31_t)0x7ff4319d, (q31_t)0xfc9075af, + (q31_t)0x7ff38274, (q31_t)0xfc775616, (q31_t)0x7ff2ce5b, (q31_t)0xfc5e36a0, (q31_t)0x7ff21553, (q31_t)0xfc45174e, (q31_t)0x7ff1575d, (q31_t)0xfc2bf821, + (q31_t)0x7ff09478, (q31_t)0xfc12d91a, (q31_t)0x7fefcca4, (q31_t)0xfbf9ba39, (q31_t)0x7feeffe1, (q31_t)0xfbe09b80, (q31_t)0x7fee2e30, (q31_t)0xfbc77cf0, + (q31_t)0x7fed5791, (q31_t)0xfbae5e89, (q31_t)0x7fec7c02, (q31_t)0xfb95404d, (q31_t)0x7feb9b85, (q31_t)0xfb7c223d, (q31_t)0x7feab61a, (q31_t)0xfb630459, + (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3, (q31_t)0x7fe8dc78, (q31_t)0xfb30c91b, (q31_t)0x7fe7e841, (q31_t)0xfb17abc2, (q31_t)0x7fe6ef1c, (q31_t)0xfafe8e9b, + (q31_t)0x7fe5f108, (q31_t)0xfae571a4, (q31_t)0x7fe4ee06, (q31_t)0xfacc54e0, (q31_t)0x7fe3e616, (q31_t)0xfab3384f, (q31_t)0x7fe2d938, (q31_t)0xfa9a1bf3, + (q31_t)0x7fe1c76b, (q31_t)0xfa80ffcb, (q31_t)0x7fe0b0b1, (q31_t)0xfa67e3da, (q31_t)0x7fdf9508, (q31_t)0xfa4ec821, (q31_t)0x7fde7471, (q31_t)0xfa35ac9f, + (q31_t)0x7fdd4eec, (q31_t)0xfa1c9157, (q31_t)0x7fdc247a, (q31_t)0xfa037648, (q31_t)0x7fdaf519, (q31_t)0xf9ea5b75, (q31_t)0x7fd9c0ca, (q31_t)0xf9d140de, + (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fd74964, (q31_t)0xf99f0c68, (q31_t)0x7fd6064c, (q31_t)0xf985f28a, (q31_t)0x7fd4be46, (q31_t)0xf96cd8ed, + (q31_t)0x7fd37153, (q31_t)0xf953bf91, (q31_t)0x7fd21f72, (q31_t)0xf93aa676, (q31_t)0x7fd0c8a3, (q31_t)0xf9218d9e, (q31_t)0x7fcf6ce8, (q31_t)0xf908750a, + (q31_t)0x7fce0c3e, (q31_t)0xf8ef5cbb, (q31_t)0x7fcca6a7, (q31_t)0xf8d644b2, (q31_t)0x7fcb3c23, (q31_t)0xf8bd2cef, (q31_t)0x7fc9ccb2, (q31_t)0xf8a41574, + (q31_t)0x7fc85854, (q31_t)0xf88afe42, (q31_t)0x7fc6df08, (q31_t)0xf871e759, (q31_t)0x7fc560cf, (q31_t)0xf858d0bb, (q31_t)0x7fc3dda9, (q31_t)0xf83fba68, + (q31_t)0x7fc25596, (q31_t)0xf826a462, (q31_t)0x7fc0c896, (q31_t)0xf80d8ea9, (q31_t)0x7fbf36aa, (q31_t)0xf7f4793e, (q31_t)0x7fbd9fd0, (q31_t)0xf7db6423, + (q31_t)0x7fbc040a, (q31_t)0xf7c24f59, (q31_t)0x7fba6357, (q31_t)0xf7a93ae0, (q31_t)0x7fb8bdb8, (q31_t)0xf79026b9, (q31_t)0x7fb7132b, (q31_t)0xf77712e5, + (q31_t)0x7fb563b3, (q31_t)0xf75dff66, (q31_t)0x7fb3af4e, (q31_t)0xf744ec3b, (q31_t)0x7fb1f5fc, (q31_t)0xf72bd967, (q31_t)0x7fb037bf, (q31_t)0xf712c6ea, + (q31_t)0x7fae7495, (q31_t)0xf6f9b4c6, (q31_t)0x7facac7f, (q31_t)0xf6e0a2fa, (q31_t)0x7faadf7c, (q31_t)0xf6c79188, (q31_t)0x7fa90d8e, (q31_t)0xf6ae8071, + (q31_t)0x7fa736b4, (q31_t)0xf6956fb7, (q31_t)0x7fa55aee, (q31_t)0xf67c5f59, (q31_t)0x7fa37a3c, (q31_t)0xf6634f59, (q31_t)0x7fa1949e, (q31_t)0xf64a3fb8, + (q31_t)0x7f9faa15, (q31_t)0xf6313077, (q31_t)0x7f9dbaa0, (q31_t)0xf6182196, (q31_t)0x7f9bc640, (q31_t)0xf5ff1318, (q31_t)0x7f99ccf4, (q31_t)0xf5e604fc, + (q31_t)0x7f97cebd, (q31_t)0xf5ccf743, (q31_t)0x7f95cb9a, (q31_t)0xf5b3e9f0, (q31_t)0x7f93c38c, (q31_t)0xf59add02, (q31_t)0x7f91b694, (q31_t)0xf581d07b, + (q31_t)0x7f8fa4b0, (q31_t)0xf568c45b, (q31_t)0x7f8d8de1, (q31_t)0xf54fb8a4, (q31_t)0x7f8b7227, (q31_t)0xf536ad56, (q31_t)0x7f895182, (q31_t)0xf51da273, + (q31_t)0x7f872bf3, (q31_t)0xf50497fb, (q31_t)0x7f850179, (q31_t)0xf4eb8def, (q31_t)0x7f82d214, (q31_t)0xf4d28451, (q31_t)0x7f809dc5, (q31_t)0xf4b97b21, + (q31_t)0x7f7e648c, (q31_t)0xf4a07261, (q31_t)0x7f7c2668, (q31_t)0xf4876a10, (q31_t)0x7f79e35a, (q31_t)0xf46e6231, (q31_t)0x7f779b62, (q31_t)0xf4555ac5, + (q31_t)0x7f754e80, (q31_t)0xf43c53cb, (q31_t)0x7f72fcb4, (q31_t)0xf4234d45, (q31_t)0x7f70a5fe, (q31_t)0xf40a4735, (q31_t)0x7f6e4a5e, (q31_t)0xf3f1419a, + (q31_t)0x7f6be9d4, (q31_t)0xf3d83c77, (q31_t)0x7f698461, (q31_t)0xf3bf37cb, (q31_t)0x7f671a05, (q31_t)0xf3a63398, (q31_t)0x7f64aabf, (q31_t)0xf38d2fe0, + (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f5fbd77, (q31_t)0xf35b29e0, (q31_t)0x7f5d3f75, (q31_t)0xf342279b, (q31_t)0x7f5abc8a, (q31_t)0xf32925d3, + (q31_t)0x7f5834b7, (q31_t)0xf310248a, (q31_t)0x7f55a7fa, (q31_t)0xf2f723c1, (q31_t)0x7f531655, (q31_t)0xf2de2379, (q31_t)0x7f507fc7, (q31_t)0xf2c523b2, + (q31_t)0x7f4de451, (q31_t)0xf2ac246e, (q31_t)0x7f4b43f2, (q31_t)0xf29325ad, (q31_t)0x7f489eaa, (q31_t)0xf27a2771, (q31_t)0x7f45f47b, (q31_t)0xf26129ba, + (q31_t)0x7f434563, (q31_t)0xf2482c8a, (q31_t)0x7f409164, (q31_t)0xf22f2fe1, (q31_t)0x7f3dd87c, (q31_t)0xf21633c0, (q31_t)0x7f3b1aad, (q31_t)0xf1fd3829, + (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f359057, (q31_t)0xf1cb429a, (q31_t)0x7f32c3d1, (q31_t)0xf1b248a5, (q31_t)0x7f2ff263, (q31_t)0xf1994f3d, + (q31_t)0x7f2d1c0e, (q31_t)0xf1805662, (q31_t)0x7f2a40d2, (q31_t)0xf1675e17, (q31_t)0x7f2760af, (q31_t)0xf14e665c, (q31_t)0x7f247ba5, (q31_t)0xf1356f32, + (q31_t)0x7f2191b4, (q31_t)0xf11c789a, (q31_t)0x7f1ea2dc, (q31_t)0xf1038295, (q31_t)0x7f1baf1e, (q31_t)0xf0ea8d24, (q31_t)0x7f18b679, (q31_t)0xf0d19848, + (q31_t)0x7f15b8ee, (q31_t)0xf0b8a401, (q31_t)0x7f12b67c, (q31_t)0xf09fb051, (q31_t)0x7f0faf25, (q31_t)0xf086bd39, (q31_t)0x7f0ca2e7, (q31_t)0xf06dcaba, + (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7f067bba, (q31_t)0xf03be78a, (q31_t)0x7f0360cb, (q31_t)0xf022f6da, (q31_t)0x7f0040f6, (q31_t)0xf00a06c8, + (q31_t)0x7efd1c3c, (q31_t)0xeff11753, (q31_t)0x7ef9f29d, (q31_t)0xefd8287c, (q31_t)0x7ef6c418, (q31_t)0xefbf3a45, (q31_t)0x7ef390ae, (q31_t)0xefa64cae, + (q31_t)0x7ef05860, (q31_t)0xef8d5fb8, (q31_t)0x7eed1b2c, (q31_t)0xef747365, (q31_t)0x7ee9d914, (q31_t)0xef5b87b5, (q31_t)0x7ee69217, (q31_t)0xef429caa, + (q31_t)0x7ee34636, (q31_t)0xef29b243, (q31_t)0x7edff570, (q31_t)0xef10c883, (q31_t)0x7edc9fc6, (q31_t)0xeef7df6a, (q31_t)0x7ed94538, (q31_t)0xeedef6f9, + (q31_t)0x7ed5e5c6, (q31_t)0xeec60f31, (q31_t)0x7ed28171, (q31_t)0xeead2813, (q31_t)0x7ecf1837, (q31_t)0xee9441a0, (q31_t)0x7ecbaa1a, (q31_t)0xee7b5bd9, + (q31_t)0x7ec8371a, (q31_t)0xee6276bf, (q31_t)0x7ec4bf36, (q31_t)0xee499253, (q31_t)0x7ec14270, (q31_t)0xee30ae96, (q31_t)0x7ebdc0c6, (q31_t)0xee17cb88, + (q31_t)0x7eba3a39, (q31_t)0xedfee92b, (q31_t)0x7eb6aeca, (q31_t)0xede60780, (q31_t)0x7eb31e78, (q31_t)0xedcd2687, (q31_t)0x7eaf8943, (q31_t)0xedb44642, + (q31_t)0x7eabef2c, (q31_t)0xed9b66b2, (q31_t)0x7ea85033, (q31_t)0xed8287d7, (q31_t)0x7ea4ac58, (q31_t)0xed69a9b3, (q31_t)0x7ea1039b, (q31_t)0xed50cc46, + (q31_t)0x7e9d55fc, (q31_t)0xed37ef91, (q31_t)0x7e99a37c, (q31_t)0xed1f1396, (q31_t)0x7e95ec1a, (q31_t)0xed063856, (q31_t)0x7e922fd6, (q31_t)0xeced5dd0, + (q31_t)0x7e8e6eb2, (q31_t)0xecd48407, (q31_t)0x7e8aa8ac, (q31_t)0xecbbaafb, (q31_t)0x7e86ddc6, (q31_t)0xeca2d2ad, (q31_t)0x7e830dff, (q31_t)0xec89fb1e, + (q31_t)0x7e7f3957, (q31_t)0xec71244f, (q31_t)0x7e7b5fce, (q31_t)0xec584e41, (q31_t)0x7e778166, (q31_t)0xec3f78f6, (q31_t)0x7e739e1d, (q31_t)0xec26a46d, + (q31_t)0x7e6fb5f4, (q31_t)0xec0dd0a8, (q31_t)0x7e6bc8eb, (q31_t)0xebf4fda8, (q31_t)0x7e67d703, (q31_t)0xebdc2b6e, (q31_t)0x7e63e03b, (q31_t)0xebc359fb, + (q31_t)0x7e5fe493, (q31_t)0xebaa894f, (q31_t)0x7e5be40c, (q31_t)0xeb91b96c, (q31_t)0x7e57dea7, (q31_t)0xeb78ea52, (q31_t)0x7e53d462, (q31_t)0xeb601c04, + (q31_t)0x7e4fc53e, (q31_t)0xeb474e81, (q31_t)0x7e4bb13c, (q31_t)0xeb2e81ca, (q31_t)0x7e47985b, (q31_t)0xeb15b5e1, (q31_t)0x7e437a9c, (q31_t)0xeafceac6, + (q31_t)0x7e3f57ff, (q31_t)0xeae4207a, (q31_t)0x7e3b3083, (q31_t)0xeacb56ff, (q31_t)0x7e37042a, (q31_t)0xeab28e56, (q31_t)0x7e32d2f4, (q31_t)0xea99c67e, + (q31_t)0x7e2e9cdf, (q31_t)0xea80ff7a, (q31_t)0x7e2a61ed, (q31_t)0xea683949, (q31_t)0x7e26221f, (q31_t)0xea4f73ee, (q31_t)0x7e21dd73, (q31_t)0xea36af69, + (q31_t)0x7e1d93ea, (q31_t)0xea1debbb, (q31_t)0x7e194584, (q31_t)0xea0528e5, (q31_t)0x7e14f242, (q31_t)0xe9ec66e8, (q31_t)0x7e109a24, (q31_t)0xe9d3a5c5, + (q31_t)0x7e0c3d29, (q31_t)0xe9bae57d, (q31_t)0x7e07db52, (q31_t)0xe9a22610, (q31_t)0x7e0374a0, (q31_t)0xe9896781, (q31_t)0x7dff0911, (q31_t)0xe970a9ce, + (q31_t)0x7dfa98a8, (q31_t)0xe957ecfb, (q31_t)0x7df62362, (q31_t)0xe93f3107, (q31_t)0x7df1a942, (q31_t)0xe92675f4, (q31_t)0x7ded2a47, (q31_t)0xe90dbbc2, + (q31_t)0x7de8a670, (q31_t)0xe8f50273, (q31_t)0x7de41dc0, (q31_t)0xe8dc4a07, (q31_t)0x7ddf9034, (q31_t)0xe8c39280, (q31_t)0x7ddafdce, (q31_t)0xe8aadbde, + (q31_t)0x7dd6668f, (q31_t)0xe8922622, (q31_t)0x7dd1ca75, (q31_t)0xe879714d, (q31_t)0x7dcd2981, (q31_t)0xe860bd61, (q31_t)0x7dc883b4, (q31_t)0xe8480a5d, + (q31_t)0x7dc3d90d, (q31_t)0xe82f5844, (q31_t)0x7dbf298d, (q31_t)0xe816a716, (q31_t)0x7dba7534, (q31_t)0xe7fdf6d4, (q31_t)0x7db5bc02, (q31_t)0xe7e5477f, + (q31_t)0x7db0fdf8, (q31_t)0xe7cc9917, (q31_t)0x7dac3b15, (q31_t)0xe7b3eb9f, (q31_t)0x7da77359, (q31_t)0xe79b3f16, (q31_t)0x7da2a6c6, (q31_t)0xe782937e, + (q31_t)0x7d9dd55a, (q31_t)0xe769e8d8, (q31_t)0x7d98ff17, (q31_t)0xe7513f25, (q31_t)0x7d9423fc, (q31_t)0xe7389665, (q31_t)0x7d8f4409, (q31_t)0xe71fee99, + (q31_t)0x7d8a5f40, (q31_t)0xe70747c4, (q31_t)0x7d85759f, (q31_t)0xe6eea1e4, (q31_t)0x7d808728, (q31_t)0xe6d5fcfc, (q31_t)0x7d7b93da, (q31_t)0xe6bd590d, + (q31_t)0x7d769bb5, (q31_t)0xe6a4b616, (q31_t)0x7d719eba, (q31_t)0xe68c141a, (q31_t)0x7d6c9ce9, (q31_t)0xe6737319, (q31_t)0x7d679642, (q31_t)0xe65ad315, + (q31_t)0x7d628ac6, (q31_t)0xe642340d, (q31_t)0x7d5d7a74, (q31_t)0xe6299604, (q31_t)0x7d58654d, (q31_t)0xe610f8f9, (q31_t)0x7d534b50, (q31_t)0xe5f85cef, + (q31_t)0x7d4e2c7f, (q31_t)0xe5dfc1e5, (q31_t)0x7d4908d9, (q31_t)0xe5c727dd, (q31_t)0x7d43e05e, (q31_t)0xe5ae8ed8, (q31_t)0x7d3eb30f, (q31_t)0xe595f6d7, + (q31_t)0x7d3980ec, (q31_t)0xe57d5fda, (q31_t)0x7d3449f5, (q31_t)0xe564c9e3, (q31_t)0x7d2f0e2b, (q31_t)0xe54c34f3, (q31_t)0x7d29cd8c, (q31_t)0xe533a10a, + (q31_t)0x7d24881b, (q31_t)0xe51b0e2a, (q31_t)0x7d1f3dd6, (q31_t)0xe5027c53, (q31_t)0x7d19eebf, (q31_t)0xe4e9eb87, (q31_t)0x7d149ad5, (q31_t)0xe4d15bc6, + (q31_t)0x7d0f4218, (q31_t)0xe4b8cd11, (q31_t)0x7d09e489, (q31_t)0xe4a03f69, (q31_t)0x7d048228, (q31_t)0xe487b2d0, (q31_t)0x7cff1af5, (q31_t)0xe46f2745, + (q31_t)0x7cf9aef0, (q31_t)0xe4569ccb, (q31_t)0x7cf43e1a, (q31_t)0xe43e1362, (q31_t)0x7ceec873, (q31_t)0xe4258b0a, (q31_t)0x7ce94dfb, (q31_t)0xe40d03c6, + (q31_t)0x7ce3ceb2, (q31_t)0xe3f47d96, (q31_t)0x7cde4a98, (q31_t)0xe3dbf87a, (q31_t)0x7cd8c1ae, (q31_t)0xe3c37474, (q31_t)0x7cd333f3, (q31_t)0xe3aaf184, + (q31_t)0x7ccda169, (q31_t)0xe3926fad, (q31_t)0x7cc80a0f, (q31_t)0xe379eeed, (q31_t)0x7cc26de5, (q31_t)0xe3616f48, (q31_t)0x7cbcccec, (q31_t)0xe348f0bd, + (q31_t)0x7cb72724, (q31_t)0xe330734d, (q31_t)0x7cb17c8d, (q31_t)0xe317f6fa, (q31_t)0x7cabcd28, (q31_t)0xe2ff7bc3, (q31_t)0x7ca618f3, (q31_t)0xe2e701ac, + (q31_t)0x7ca05ff1, (q31_t)0xe2ce88b3, (q31_t)0x7c9aa221, (q31_t)0xe2b610da, (q31_t)0x7c94df83, (q31_t)0xe29d9a23, (q31_t)0x7c8f1817, (q31_t)0xe285248d, + (q31_t)0x7c894bde, (q31_t)0xe26cb01b, (q31_t)0x7c837ad8, (q31_t)0xe2543ccc, (q31_t)0x7c7da505, (q31_t)0xe23bcaa2, (q31_t)0x7c77ca65, (q31_t)0xe223599e, + (q31_t)0x7c71eaf9, (q31_t)0xe20ae9c1, (q31_t)0x7c6c06c0, (q31_t)0xe1f27b0b, (q31_t)0x7c661dbc, (q31_t)0xe1da0d7e, (q31_t)0x7c602fec, (q31_t)0xe1c1a11b, + (q31_t)0x7c5a3d50, (q31_t)0xe1a935e2, (q31_t)0x7c5445e9, (q31_t)0xe190cbd4, (q31_t)0x7c4e49b7, (q31_t)0xe17862f3, (q31_t)0x7c4848ba, (q31_t)0xe15ffb3f, + (q31_t)0x7c4242f2, (q31_t)0xe14794ba, (q31_t)0x7c3c3860, (q31_t)0xe12f2f63, (q31_t)0x7c362904, (q31_t)0xe116cb3d, (q31_t)0x7c3014de, (q31_t)0xe0fe6848, + (q31_t)0x7c29fbee, (q31_t)0xe0e60685, (q31_t)0x7c23de35, (q31_t)0xe0cda5f5, (q31_t)0x7c1dbbb3, (q31_t)0xe0b54698, (q31_t)0x7c179467, (q31_t)0xe09ce871, + (q31_t)0x7c116853, (q31_t)0xe0848b7f, (q31_t)0x7c0b3777, (q31_t)0xe06c2fc4, (q31_t)0x7c0501d2, (q31_t)0xe053d541, (q31_t)0x7bfec765, (q31_t)0xe03b7bf6, + (q31_t)0x7bf88830, (q31_t)0xe02323e5, (q31_t)0x7bf24434, (q31_t)0xe00acd0e, (q31_t)0x7bebfb70, (q31_t)0xdff27773, (q31_t)0x7be5ade6, (q31_t)0xdfda2314, + (q31_t)0x7bdf5b94, (q31_t)0xdfc1cff3, (q31_t)0x7bd9047c, (q31_t)0xdfa97e0f, (q31_t)0x7bd2a89e, (q31_t)0xdf912d6b, (q31_t)0x7bcc47fa, (q31_t)0xdf78de07, + (q31_t)0x7bc5e290, (q31_t)0xdf608fe4, (q31_t)0x7bbf7860, (q31_t)0xdf484302, (q31_t)0x7bb9096b, (q31_t)0xdf2ff764, (q31_t)0x7bb295b0, (q31_t)0xdf17ad0a, + (q31_t)0x7bac1d31, (q31_t)0xdeff63f4, (q31_t)0x7ba59fee, (q31_t)0xdee71c24, (q31_t)0x7b9f1de6, (q31_t)0xdeced59b, (q31_t)0x7b989719, (q31_t)0xdeb69059, + (q31_t)0x7b920b89, (q31_t)0xde9e4c60, (q31_t)0x7b8b7b36, (q31_t)0xde8609b1, (q31_t)0x7b84e61f, (q31_t)0xde6dc84b, (q31_t)0x7b7e4c45, (q31_t)0xde558831, + (q31_t)0x7b77ada8, (q31_t)0xde3d4964, (q31_t)0x7b710a49, (q31_t)0xde250be3, (q31_t)0x7b6a6227, (q31_t)0xde0ccfb1, (q31_t)0x7b63b543, (q31_t)0xddf494ce, + (q31_t)0x7b5d039e, (q31_t)0xdddc5b3b, (q31_t)0x7b564d36, (q31_t)0xddc422f8, (q31_t)0x7b4f920e, (q31_t)0xddabec08, (q31_t)0x7b48d225, (q31_t)0xdd93b66a, + (q31_t)0x7b420d7a, (q31_t)0xdd7b8220, (q31_t)0x7b3b4410, (q31_t)0xdd634f2b, (q31_t)0x7b3475e5, (q31_t)0xdd4b1d8c, (q31_t)0x7b2da2fa, (q31_t)0xdd32ed43, + (q31_t)0x7b26cb4f, (q31_t)0xdd1abe51, (q31_t)0x7b1feee5, (q31_t)0xdd0290b8, (q31_t)0x7b190dbc, (q31_t)0xdcea6478, (q31_t)0x7b1227d3, (q31_t)0xdcd23993, + (q31_t)0x7b0b3d2c, (q31_t)0xdcba1008, (q31_t)0x7b044dc7, (q31_t)0xdca1e7da, (q31_t)0x7afd59a4, (q31_t)0xdc89c109, (q31_t)0x7af660c2, (q31_t)0xdc719b96, + (q31_t)0x7aef6323, (q31_t)0xdc597781, (q31_t)0x7ae860c7, (q31_t)0xdc4154cd, (q31_t)0x7ae159ae, (q31_t)0xdc293379, (q31_t)0x7ada4dd8, (q31_t)0xdc111388, + (q31_t)0x7ad33d45, (q31_t)0xdbf8f4f8, (q31_t)0x7acc27f7, (q31_t)0xdbe0d7cd, (q31_t)0x7ac50dec, (q31_t)0xdbc8bc06, (q31_t)0x7abdef25, (q31_t)0xdbb0a1a4, + (q31_t)0x7ab6cba4, (q31_t)0xdb9888a8, (q31_t)0x7aafa367, (q31_t)0xdb807114, (q31_t)0x7aa8766f, (q31_t)0xdb685ae9, (q31_t)0x7aa144bc, (q31_t)0xdb504626, + (q31_t)0x7a9a0e50, (q31_t)0xdb3832cd, (q31_t)0x7a92d329, (q31_t)0xdb2020e0, (q31_t)0x7a8b9348, (q31_t)0xdb08105e, (q31_t)0x7a844eae, (q31_t)0xdaf00149, + (q31_t)0x7a7d055b, (q31_t)0xdad7f3a2, (q31_t)0x7a75b74f, (q31_t)0xdabfe76a, (q31_t)0x7a6e648a, (q31_t)0xdaa7dca1, (q31_t)0x7a670d0d, (q31_t)0xda8fd349, + (q31_t)0x7a5fb0d8, (q31_t)0xda77cb63, (q31_t)0x7a584feb, (q31_t)0xda5fc4ef, (q31_t)0x7a50ea47, (q31_t)0xda47bfee, (q31_t)0x7a497feb, (q31_t)0xda2fbc61, + (q31_t)0x7a4210d8, (q31_t)0xda17ba4a, (q31_t)0x7a3a9d0f, (q31_t)0xd9ffb9a9, (q31_t)0x7a332490, (q31_t)0xd9e7ba7f, (q31_t)0x7a2ba75a, (q31_t)0xd9cfbccd, + (q31_t)0x7a24256f, (q31_t)0xd9b7c094, (q31_t)0x7a1c9ece, (q31_t)0xd99fc5d4, (q31_t)0x7a151378, (q31_t)0xd987cc90, (q31_t)0x7a0d836d, (q31_t)0xd96fd4c7, + (q31_t)0x7a05eead, (q31_t)0xd957de7a, (q31_t)0x79fe5539, (q31_t)0xd93fe9ab, (q31_t)0x79f6b711, (q31_t)0xd927f65b, (q31_t)0x79ef1436, (q31_t)0xd910048a, + (q31_t)0x79e76ca7, (q31_t)0xd8f81439, (q31_t)0x79dfc064, (q31_t)0xd8e0256a, (q31_t)0x79d80f6f, (q31_t)0xd8c8381d, (q31_t)0x79d059c8, (q31_t)0xd8b04c52, + (q31_t)0x79c89f6e, (q31_t)0xd898620c, (q31_t)0x79c0e062, (q31_t)0xd880794b, (q31_t)0x79b91ca4, (q31_t)0xd868920f, (q31_t)0x79b15435, (q31_t)0xd850ac5a, + (q31_t)0x79a98715, (q31_t)0xd838c82d, (q31_t)0x79a1b545, (q31_t)0xd820e589, (q31_t)0x7999dec4, (q31_t)0xd809046e, (q31_t)0x79920392, (q31_t)0xd7f124dd, + (q31_t)0x798a23b1, (q31_t)0xd7d946d8, (q31_t)0x79823f20, (q31_t)0xd7c16a5f, (q31_t)0x797a55e0, (q31_t)0xd7a98f73, (q31_t)0x797267f2, (q31_t)0xd791b616, + (q31_t)0x796a7554, (q31_t)0xd779de47, (q31_t)0x79627e08, (q31_t)0xd7620808, (q31_t)0x795a820e, (q31_t)0xd74a335b, (q31_t)0x79528167, (q31_t)0xd732603f, + (q31_t)0x794a7c12, (q31_t)0xd71a8eb5, (q31_t)0x79427210, (q31_t)0xd702bec0, (q31_t)0x793a6361, (q31_t)0xd6eaf05f, (q31_t)0x79325006, (q31_t)0xd6d32393, + (q31_t)0x792a37fe, (q31_t)0xd6bb585e, (q31_t)0x79221b4b, (q31_t)0xd6a38ec0, (q31_t)0x7919f9ec, (q31_t)0xd68bc6ba, (q31_t)0x7911d3e2, (q31_t)0xd674004e, + (q31_t)0x7909a92d, (q31_t)0xd65c3b7b, (q31_t)0x790179cd, (q31_t)0xd6447844, (q31_t)0x78f945c3, (q31_t)0xd62cb6a8, (q31_t)0x78f10d0f, (q31_t)0xd614f6a9, + (q31_t)0x78e8cfb2, (q31_t)0xd5fd3848, (q31_t)0x78e08dab, (q31_t)0xd5e57b85, (q31_t)0x78d846fb, (q31_t)0xd5cdc062, (q31_t)0x78cffba3, (q31_t)0xd5b606e0, + (q31_t)0x78c7aba2, (q31_t)0xd59e4eff, (q31_t)0x78bf56f9, (q31_t)0xd58698c0, (q31_t)0x78b6fda8, (q31_t)0xd56ee424, (q31_t)0x78ae9fb0, (q31_t)0xd557312d, + (q31_t)0x78a63d11, (q31_t)0xd53f7fda, (q31_t)0x789dd5cb, (q31_t)0xd527d02e, (q31_t)0x789569df, (q31_t)0xd5102228, (q31_t)0x788cf94c, (q31_t)0xd4f875ca, + (q31_t)0x78848414, (q31_t)0xd4e0cb15, (q31_t)0x787c0a36, (q31_t)0xd4c92209, (q31_t)0x78738bb3, (q31_t)0xd4b17aa8, (q31_t)0x786b088c, (q31_t)0xd499d4f2, + (q31_t)0x786280bf, (q31_t)0xd48230e9, (q31_t)0x7859f44f, (q31_t)0xd46a8e8d, (q31_t)0x7851633b, (q31_t)0xd452eddf, (q31_t)0x7848cd83, (q31_t)0xd43b4ee0, + (q31_t)0x78403329, (q31_t)0xd423b191, (q31_t)0x7837942b, (q31_t)0xd40c15f3, (q31_t)0x782ef08b, (q31_t)0xd3f47c06, (q31_t)0x78264849, (q31_t)0xd3dce3cd, + (q31_t)0x781d9b65, (q31_t)0xd3c54d47, (q31_t)0x7814e9df, (q31_t)0xd3adb876, (q31_t)0x780c33b8, (q31_t)0xd396255a, (q31_t)0x780378f1, (q31_t)0xd37e93f4, + (q31_t)0x77fab989, (q31_t)0xd3670446, (q31_t)0x77f1f581, (q31_t)0xd34f764f, (q31_t)0x77e92cd9, (q31_t)0xd337ea12, (q31_t)0x77e05f91, (q31_t)0xd3205f8f, + (q31_t)0x77d78daa, (q31_t)0xd308d6c7, (q31_t)0x77ceb725, (q31_t)0xd2f14fba, (q31_t)0x77c5dc01, (q31_t)0xd2d9ca6a, (q31_t)0x77bcfc3f, (q31_t)0xd2c246d8, + (q31_t)0x77b417df, (q31_t)0xd2aac504, (q31_t)0x77ab2ee2, (q31_t)0xd29344f0, (q31_t)0x77a24148, (q31_t)0xd27bc69c, (q31_t)0x77994f11, (q31_t)0xd2644a0a, + (q31_t)0x7790583e, (q31_t)0xd24ccf39, (q31_t)0x77875cce, (q31_t)0xd235562b, (q31_t)0x777e5cc3, (q31_t)0xd21ddee2, (q31_t)0x7775581d, (q31_t)0xd206695d, + (q31_t)0x776c4edb, (q31_t)0xd1eef59e, (q31_t)0x776340ff, (q31_t)0xd1d783a6, (q31_t)0x775a2e89, (q31_t)0xd1c01375, (q31_t)0x77511778, (q31_t)0xd1a8a50d, + (q31_t)0x7747fbce, (q31_t)0xd191386e, (q31_t)0x773edb8b, (q31_t)0xd179cd99, (q31_t)0x7735b6af, (q31_t)0xd1626490, (q31_t)0x772c8d3a, (q31_t)0xd14afd52, + (q31_t)0x77235f2d, (q31_t)0xd13397e2, (q31_t)0x771a2c88, (q31_t)0xd11c343f, (q31_t)0x7710f54c, (q31_t)0xd104d26b, (q31_t)0x7707b979, (q31_t)0xd0ed7267, + (q31_t)0x76fe790e, (q31_t)0xd0d61434, (q31_t)0x76f5340e, (q31_t)0xd0beb7d2, (q31_t)0x76ebea77, (q31_t)0xd0a75d42, (q31_t)0x76e29c4b, (q31_t)0xd0900486, + (q31_t)0x76d94989, (q31_t)0xd078ad9e, (q31_t)0x76cff232, (q31_t)0xd061588b, (q31_t)0x76c69647, (q31_t)0xd04a054e, (q31_t)0x76bd35c7, (q31_t)0xd032b3e7, + (q31_t)0x76b3d0b4, (q31_t)0xd01b6459, (q31_t)0x76aa670d, (q31_t)0xd00416a3, (q31_t)0x76a0f8d2, (q31_t)0xcfeccac7, (q31_t)0x76978605, (q31_t)0xcfd580c6, + (q31_t)0x768e0ea6, (q31_t)0xcfbe389f, (q31_t)0x768492b4, (q31_t)0xcfa6f255, (q31_t)0x767b1231, (q31_t)0xcf8fade9, (q31_t)0x76718d1c, (q31_t)0xcf786b5a, + (q31_t)0x76680376, (q31_t)0xcf612aaa, (q31_t)0x765e7540, (q31_t)0xcf49ebda, (q31_t)0x7654e279, (q31_t)0xcf32aeeb, (q31_t)0x764b4b23, (q31_t)0xcf1b73de, + (q31_t)0x7641af3d, (q31_t)0xcf043ab3, (q31_t)0x76380ec8, (q31_t)0xceed036b, (q31_t)0x762e69c4, (q31_t)0xced5ce08, (q31_t)0x7624c031, (q31_t)0xcebe9a8a, + (q31_t)0x761b1211, (q31_t)0xcea768f2, (q31_t)0x76115f63, (q31_t)0xce903942, (q31_t)0x7607a828, (q31_t)0xce790b79, (q31_t)0x75fdec60, (q31_t)0xce61df99, + (q31_t)0x75f42c0b, (q31_t)0xce4ab5a2, (q31_t)0x75ea672a, (q31_t)0xce338d97, (q31_t)0x75e09dbd, (q31_t)0xce1c6777, (q31_t)0x75d6cfc5, (q31_t)0xce054343, + (q31_t)0x75ccfd42, (q31_t)0xcdee20fc, (q31_t)0x75c32634, (q31_t)0xcdd700a4, (q31_t)0x75b94a9c, (q31_t)0xcdbfe23a, (q31_t)0x75af6a7b, (q31_t)0xcda8c5c1, + (q31_t)0x75a585cf, (q31_t)0xcd91ab39, (q31_t)0x759b9c9b, (q31_t)0xcd7a92a2, (q31_t)0x7591aedd, (q31_t)0xcd637bfe, (q31_t)0x7587bc98, (q31_t)0xcd4c674d, + (q31_t)0x757dc5ca, (q31_t)0xcd355491, (q31_t)0x7573ca75, (q31_t)0xcd1e43ca, (q31_t)0x7569ca99, (q31_t)0xcd0734f9, (q31_t)0x755fc635, (q31_t)0xccf0281f, + (q31_t)0x7555bd4c, (q31_t)0xccd91d3d, (q31_t)0x754bafdc, (q31_t)0xccc21455, (q31_t)0x75419de7, (q31_t)0xccab0d65, (q31_t)0x7537876c, (q31_t)0xcc940871, + (q31_t)0x752d6c6c, (q31_t)0xcc7d0578, (q31_t)0x75234ce8, (q31_t)0xcc66047b, (q31_t)0x751928e0, (q31_t)0xcc4f057c, (q31_t)0x750f0054, (q31_t)0xcc38087b, + (q31_t)0x7504d345, (q31_t)0xcc210d79, (q31_t)0x74faa1b3, (q31_t)0xcc0a1477, (q31_t)0x74f06b9e, (q31_t)0xcbf31d75, (q31_t)0x74e63108, (q31_t)0xcbdc2876, + (q31_t)0x74dbf1ef, (q31_t)0xcbc53579, (q31_t)0x74d1ae55, (q31_t)0xcbae447f, (q31_t)0x74c7663a, (q31_t)0xcb97558a, (q31_t)0x74bd199f, (q31_t)0xcb80689a, + (q31_t)0x74b2c884, (q31_t)0xcb697db0, (q31_t)0x74a872e8, (q31_t)0xcb5294ce, (q31_t)0x749e18cd, (q31_t)0xcb3badf3, (q31_t)0x7493ba34, (q31_t)0xcb24c921, + (q31_t)0x7489571c, (q31_t)0xcb0de658, (q31_t)0x747eef85, (q31_t)0xcaf7059a, (q31_t)0x74748371, (q31_t)0xcae026e8, (q31_t)0x746a12df, (q31_t)0xcac94a42, + (q31_t)0x745f9dd1, (q31_t)0xcab26fa9, (q31_t)0x74552446, (q31_t)0xca9b971e, (q31_t)0x744aa63f, (q31_t)0xca84c0a3, (q31_t)0x744023bc, (q31_t)0xca6dec37, + (q31_t)0x74359cbd, (q31_t)0xca5719db, (q31_t)0x742b1144, (q31_t)0xca404992, (q31_t)0x74208150, (q31_t)0xca297b5a, (q31_t)0x7415ece2, (q31_t)0xca12af37, + (q31_t)0x740b53fb, (q31_t)0xc9fbe527, (q31_t)0x7400b69a, (q31_t)0xc9e51d2d, (q31_t)0x73f614c0, (q31_t)0xc9ce5748, (q31_t)0x73eb6e6e, (q31_t)0xc9b7937a, + (q31_t)0x73e0c3a3, (q31_t)0xc9a0d1c5, (q31_t)0x73d61461, (q31_t)0xc98a1227, (q31_t)0x73cb60a8, (q31_t)0xc97354a4, (q31_t)0x73c0a878, (q31_t)0xc95c993a, + (q31_t)0x73b5ebd1, (q31_t)0xc945dfec, (q31_t)0x73ab2ab4, (q31_t)0xc92f28ba, (q31_t)0x73a06522, (q31_t)0xc91873a5, (q31_t)0x73959b1b, (q31_t)0xc901c0ae, + (q31_t)0x738acc9e, (q31_t)0xc8eb0fd6, (q31_t)0x737ff9ae, (q31_t)0xc8d4611d, (q31_t)0x73752249, (q31_t)0xc8bdb485, (q31_t)0x736a4671, (q31_t)0xc8a70a0e, + (q31_t)0x735f6626, (q31_t)0xc89061ba, (q31_t)0x73548168, (q31_t)0xc879bb89, (q31_t)0x73499838, (q31_t)0xc863177b, (q31_t)0x733eaa96, (q31_t)0xc84c7593, + (q31_t)0x7333b883, (q31_t)0xc835d5d0, (q31_t)0x7328c1ff, (q31_t)0xc81f3834, (q31_t)0x731dc70a, (q31_t)0xc8089cbf, (q31_t)0x7312c7a5, (q31_t)0xc7f20373, + (q31_t)0x7307c3d0, (q31_t)0xc7db6c50, (q31_t)0x72fcbb8c, (q31_t)0xc7c4d757, (q31_t)0x72f1aed9, (q31_t)0xc7ae4489, (q31_t)0x72e69db7, (q31_t)0xc797b3e7, + (q31_t)0x72db8828, (q31_t)0xc7812572, (q31_t)0x72d06e2b, (q31_t)0xc76a992a, (q31_t)0x72c54fc1, (q31_t)0xc7540f11, (q31_t)0x72ba2cea, (q31_t)0xc73d8727, + (q31_t)0x72af05a7, (q31_t)0xc727016d, (q31_t)0x72a3d9f7, (q31_t)0xc7107de4, (q31_t)0x7298a9dd, (q31_t)0xc6f9fc8d, (q31_t)0x728d7557, (q31_t)0xc6e37d69, + (q31_t)0x72823c67, (q31_t)0xc6cd0079, (q31_t)0x7276ff0d, (q31_t)0xc6b685bd, (q31_t)0x726bbd48, (q31_t)0xc6a00d37, (q31_t)0x7260771b, (q31_t)0xc68996e7, + (q31_t)0x72552c85, (q31_t)0xc67322ce, (q31_t)0x7249dd86, (q31_t)0xc65cb0ed, (q31_t)0x723e8a20, (q31_t)0xc6464144, (q31_t)0x72333251, (q31_t)0xc62fd3d6, + (q31_t)0x7227d61c, (q31_t)0xc61968a2, (q31_t)0x721c7580, (q31_t)0xc602ffaa, (q31_t)0x7211107e, (q31_t)0xc5ec98ee, (q31_t)0x7205a716, (q31_t)0xc5d6346f, + (q31_t)0x71fa3949, (q31_t)0xc5bfd22e, (q31_t)0x71eec716, (q31_t)0xc5a9722c, (q31_t)0x71e35080, (q31_t)0xc593146a, (q31_t)0x71d7d585, (q31_t)0xc57cb8e9, + (q31_t)0x71cc5626, (q31_t)0xc5665fa9, (q31_t)0x71c0d265, (q31_t)0xc55008ab, (q31_t)0x71b54a41, (q31_t)0xc539b3f1, (q31_t)0x71a9bdba, (q31_t)0xc523617a, + (q31_t)0x719e2cd2, (q31_t)0xc50d1149, (q31_t)0x71929789, (q31_t)0xc4f6c35d, (q31_t)0x7186fdde, (q31_t)0xc4e077b8, (q31_t)0x717b5fd3, (q31_t)0xc4ca2e5b, + (q31_t)0x716fbd68, (q31_t)0xc4b3e746, (q31_t)0x7164169d, (q31_t)0xc49da27a, (q31_t)0x71586b74, (q31_t)0xc4875ff9, (q31_t)0x714cbbeb, (q31_t)0xc4711fc2, + (q31_t)0x71410805, (q31_t)0xc45ae1d7, (q31_t)0x71354fc0, (q31_t)0xc444a639, (q31_t)0x7129931f, (q31_t)0xc42e6ce8, (q31_t)0x711dd220, (q31_t)0xc41835e6, + (q31_t)0x71120cc5, (q31_t)0xc4020133, (q31_t)0x7106430e, (q31_t)0xc3ebced0, (q31_t)0x70fa74fc, (q31_t)0xc3d59ebe, (q31_t)0x70eea28e, (q31_t)0xc3bf70fd, + (q31_t)0x70e2cbc6, (q31_t)0xc3a94590, (q31_t)0x70d6f0a4, (q31_t)0xc3931c76, (q31_t)0x70cb1128, (q31_t)0xc37cf5b0, (q31_t)0x70bf2d53, (q31_t)0xc366d140, + (q31_t)0x70b34525, (q31_t)0xc350af26, (q31_t)0x70a7589f, (q31_t)0xc33a8f62, (q31_t)0x709b67c0, (q31_t)0xc32471f7, (q31_t)0x708f728b, (q31_t)0xc30e56e4, + (q31_t)0x708378ff, (q31_t)0xc2f83e2a, (q31_t)0x70777b1c, (q31_t)0xc2e227cb, (q31_t)0x706b78e3, (q31_t)0xc2cc13c7, (q31_t)0x705f7255, (q31_t)0xc2b6021f, + (q31_t)0x70536771, (q31_t)0xc29ff2d4, (q31_t)0x70475839, (q31_t)0xc289e5e7, (q31_t)0x703b44ad, (q31_t)0xc273db58, (q31_t)0x702f2ccd, (q31_t)0xc25dd329, + (q31_t)0x7023109a, (q31_t)0xc247cd5a, (q31_t)0x7016f014, (q31_t)0xc231c9ec, (q31_t)0x700acb3c, (q31_t)0xc21bc8e1, (q31_t)0x6ffea212, (q31_t)0xc205ca38, + (q31_t)0x6ff27497, (q31_t)0xc1efcdf3, (q31_t)0x6fe642ca, (q31_t)0xc1d9d412, (q31_t)0x6fda0cae, (q31_t)0xc1c3dc97, (q31_t)0x6fcdd241, (q31_t)0xc1ade781, + (q31_t)0x6fc19385, (q31_t)0xc197f4d4, (q31_t)0x6fb5507a, (q31_t)0xc182048d, (q31_t)0x6fa90921, (q31_t)0xc16c16b0, (q31_t)0x6f9cbd79, (q31_t)0xc1562b3d, + (q31_t)0x6f906d84, (q31_t)0xc1404233, (q31_t)0x6f841942, (q31_t)0xc12a5b95, (q31_t)0x6f77c0b3, (q31_t)0xc1147764, (q31_t)0x6f6b63d8, (q31_t)0xc0fe959f, + (q31_t)0x6f5f02b2, (q31_t)0xc0e8b648, (q31_t)0x6f529d40, (q31_t)0xc0d2d960, (q31_t)0x6f463383, (q31_t)0xc0bcfee7, (q31_t)0x6f39c57d, (q31_t)0xc0a726df, + (q31_t)0x6f2d532c, (q31_t)0xc0915148, (q31_t)0x6f20dc92, (q31_t)0xc07b7e23, (q31_t)0x6f1461b0, (q31_t)0xc065ad70, (q31_t)0x6f07e285, (q31_t)0xc04fdf32, + (q31_t)0x6efb5f12, (q31_t)0xc03a1368, (q31_t)0x6eeed758, (q31_t)0xc0244a14, (q31_t)0x6ee24b57, (q31_t)0xc00e8336, (q31_t)0x6ed5bb10, (q31_t)0xbff8bece, + (q31_t)0x6ec92683, (q31_t)0xbfe2fcdf, (q31_t)0x6ebc8db0, (q31_t)0xbfcd3d69, (q31_t)0x6eaff099, (q31_t)0xbfb7806c, (q31_t)0x6ea34f3d, (q31_t)0xbfa1c5ea, + (q31_t)0x6e96a99d, (q31_t)0xbf8c0de3, (q31_t)0x6e89ffb9, (q31_t)0xbf765858, (q31_t)0x6e7d5193, (q31_t)0xbf60a54a, (q31_t)0x6e709f2a, (q31_t)0xbf4af4ba, + (q31_t)0x6e63e87f, (q31_t)0xbf3546a8, (q31_t)0x6e572d93, (q31_t)0xbf1f9b16, (q31_t)0x6e4a6e66, (q31_t)0xbf09f205, (q31_t)0x6e3daaf8, (q31_t)0xbef44b74, + (q31_t)0x6e30e34a, (q31_t)0xbedea765, (q31_t)0x6e24175c, (q31_t)0xbec905d9, (q31_t)0x6e174730, (q31_t)0xbeb366d1, (q31_t)0x6e0a72c5, (q31_t)0xbe9dca4e, + (q31_t)0x6dfd9a1c, (q31_t)0xbe88304f, (q31_t)0x6df0bd35, (q31_t)0xbe7298d7, (q31_t)0x6de3dc11, (q31_t)0xbe5d03e6, (q31_t)0x6dd6f6b1, (q31_t)0xbe47717c, + (q31_t)0x6dca0d14, (q31_t)0xbe31e19b, (q31_t)0x6dbd1f3c, (q31_t)0xbe1c5444, (q31_t)0x6db02d29, (q31_t)0xbe06c977, (q31_t)0x6da336dc, (q31_t)0xbdf14135, + (q31_t)0x6d963c54, (q31_t)0xbddbbb7f, (q31_t)0x6d893d93, (q31_t)0xbdc63856, (q31_t)0x6d7c3a98, (q31_t)0xbdb0b7bb, (q31_t)0x6d6f3365, (q31_t)0xbd9b39ad, + (q31_t)0x6d6227fa, (q31_t)0xbd85be30, (q31_t)0x6d551858, (q31_t)0xbd704542, (q31_t)0x6d48047e, (q31_t)0xbd5acee5, (q31_t)0x6d3aec6e, (q31_t)0xbd455b1a, + (q31_t)0x6d2dd027, (q31_t)0xbd2fe9e2, (q31_t)0x6d20afac, (q31_t)0xbd1a7b3d, (q31_t)0x6d138afb, (q31_t)0xbd050f2c, (q31_t)0x6d066215, (q31_t)0xbcefa5b0, + (q31_t)0x6cf934fc, (q31_t)0xbcda3ecb, (q31_t)0x6cec03af, (q31_t)0xbcc4da7b, (q31_t)0x6cdece2f, (q31_t)0xbcaf78c4, (q31_t)0x6cd1947c, (q31_t)0xbc9a19a5, + (q31_t)0x6cc45698, (q31_t)0xbc84bd1f, (q31_t)0x6cb71482, (q31_t)0xbc6f6333, (q31_t)0x6ca9ce3b, (q31_t)0xbc5a0be2, (q31_t)0x6c9c83c3, (q31_t)0xbc44b72c, + (q31_t)0x6c8f351c, (q31_t)0xbc2f6513, (q31_t)0x6c81e245, (q31_t)0xbc1a1598, (q31_t)0x6c748b3f, (q31_t)0xbc04c8ba, (q31_t)0x6c67300b, (q31_t)0xbbef7e7c, + (q31_t)0x6c59d0a9, (q31_t)0xbbda36dd, (q31_t)0x6c4c6d1a, (q31_t)0xbbc4f1df, (q31_t)0x6c3f055d, (q31_t)0xbbafaf82, (q31_t)0x6c319975, (q31_t)0xbb9a6fc7, + (q31_t)0x6c242960, (q31_t)0xbb8532b0, (q31_t)0x6c16b521, (q31_t)0xbb6ff83c, (q31_t)0x6c093cb6, (q31_t)0xbb5ac06d, (q31_t)0x6bfbc021, (q31_t)0xbb458b43, + (q31_t)0x6bee3f62, (q31_t)0xbb3058c0, (q31_t)0x6be0ba7b, (q31_t)0xbb1b28e4, (q31_t)0x6bd3316a, (q31_t)0xbb05fbb0, (q31_t)0x6bc5a431, (q31_t)0xbaf0d125, + (q31_t)0x6bb812d1, (q31_t)0xbadba943, (q31_t)0x6baa7d49, (q31_t)0xbac6840c, (q31_t)0x6b9ce39b, (q31_t)0xbab16180, (q31_t)0x6b8f45c7, (q31_t)0xba9c41a0, + (q31_t)0x6b81a3cd, (q31_t)0xba87246d, (q31_t)0x6b73fdae, (q31_t)0xba7209e7, (q31_t)0x6b66536b, (q31_t)0xba5cf210, (q31_t)0x6b58a503, (q31_t)0xba47dce8, + (q31_t)0x6b4af279, (q31_t)0xba32ca71, (q31_t)0x6b3d3bcb, (q31_t)0xba1dbaaa, (q31_t)0x6b2f80fb, (q31_t)0xba08ad95, (q31_t)0x6b21c208, (q31_t)0xb9f3a332, + (q31_t)0x6b13fef5, (q31_t)0xb9de9b83, (q31_t)0x6b0637c1, (q31_t)0xb9c99688, (q31_t)0x6af86c6c, (q31_t)0xb9b49442, (q31_t)0x6aea9cf8, (q31_t)0xb99f94b2, + (q31_t)0x6adcc964, (q31_t)0xb98a97d8, (q31_t)0x6acef1b2, (q31_t)0xb9759db6, (q31_t)0x6ac115e2, (q31_t)0xb960a64c, (q31_t)0x6ab335f4, (q31_t)0xb94bb19b, + (q31_t)0x6aa551e9, (q31_t)0xb936bfa4, (q31_t)0x6a9769c1, (q31_t)0xb921d067, (q31_t)0x6a897d7d, (q31_t)0xb90ce3e6, (q31_t)0x6a7b8d1e, (q31_t)0xb8f7fa21, + (q31_t)0x6a6d98a4, (q31_t)0xb8e31319, (q31_t)0x6a5fa010, (q31_t)0xb8ce2ecf, (q31_t)0x6a51a361, (q31_t)0xb8b94d44, (q31_t)0x6a43a29a, (q31_t)0xb8a46e78, + (q31_t)0x6a359db9, (q31_t)0xb88f926d, (q31_t)0x6a2794c1, (q31_t)0xb87ab922, (q31_t)0x6a1987b0, (q31_t)0xb865e299, (q31_t)0x6a0b7689, (q31_t)0xb8510ed4, + (q31_t)0x69fd614a, (q31_t)0xb83c3dd1, (q31_t)0x69ef47f6, (q31_t)0xb8276f93, (q31_t)0x69e12a8c, (q31_t)0xb812a41a, (q31_t)0x69d3090e, (q31_t)0xb7fddb67, + (q31_t)0x69c4e37a, (q31_t)0xb7e9157a, (q31_t)0x69b6b9d3, (q31_t)0xb7d45255, (q31_t)0x69a88c19, (q31_t)0xb7bf91f8, (q31_t)0x699a5a4c, (q31_t)0xb7aad465, + (q31_t)0x698c246c, (q31_t)0xb796199b, (q31_t)0x697dea7b, (q31_t)0xb781619c, (q31_t)0x696fac78, (q31_t)0xb76cac69, (q31_t)0x69616a65, (q31_t)0xb757fa01, + (q31_t)0x69532442, (q31_t)0xb7434a67, (q31_t)0x6944da10, (q31_t)0xb72e9d9b, (q31_t)0x69368bce, (q31_t)0xb719f39e, (q31_t)0x6928397e, (q31_t)0xb7054c6f, + (q31_t)0x6919e320, (q31_t)0xb6f0a812, (q31_t)0x690b88b5, (q31_t)0xb6dc0685, (q31_t)0x68fd2a3d, (q31_t)0xb6c767ca, (q31_t)0x68eec7b9, (q31_t)0xb6b2cbe2, + (q31_t)0x68e06129, (q31_t)0xb69e32cd, (q31_t)0x68d1f68f, (q31_t)0xb6899c8d, (q31_t)0x68c387e9, (q31_t)0xb6750921, (q31_t)0x68b5153a, (q31_t)0xb660788c, + (q31_t)0x68a69e81, (q31_t)0xb64beacd, (q31_t)0x689823bf, (q31_t)0xb6375fe5, (q31_t)0x6889a4f6, (q31_t)0xb622d7d6, (q31_t)0x687b2224, (q31_t)0xb60e529f, + (q31_t)0x686c9b4b, (q31_t)0xb5f9d043, (q31_t)0x685e106c, (q31_t)0xb5e550c1, (q31_t)0x684f8186, (q31_t)0xb5d0d41a, (q31_t)0x6840ee9b, (q31_t)0xb5bc5a50, + (q31_t)0x683257ab, (q31_t)0xb5a7e362, (q31_t)0x6823bcb7, (q31_t)0xb5936f53, (q31_t)0x68151dbe, (q31_t)0xb57efe22, (q31_t)0x68067ac3, (q31_t)0xb56a8fd0, + (q31_t)0x67f7d3c5, (q31_t)0xb556245e, (q31_t)0x67e928c5, (q31_t)0xb541bbcd, (q31_t)0x67da79c3, (q31_t)0xb52d561e, (q31_t)0x67cbc6c0, (q31_t)0xb518f351, + (q31_t)0x67bd0fbd, (q31_t)0xb5049368, (q31_t)0x67ae54ba, (q31_t)0xb4f03663, (q31_t)0x679f95b7, (q31_t)0xb4dbdc42, (q31_t)0x6790d2b6, (q31_t)0xb4c78507, + (q31_t)0x67820bb7, (q31_t)0xb4b330b3, (q31_t)0x677340ba, (q31_t)0xb49edf45, (q31_t)0x676471c0, (q31_t)0xb48a90c0, (q31_t)0x67559eca, (q31_t)0xb4764523, + (q31_t)0x6746c7d8, (q31_t)0xb461fc70, (q31_t)0x6737ecea, (q31_t)0xb44db6a8, (q31_t)0x67290e02, (q31_t)0xb43973ca, (q31_t)0x671a2b20, (q31_t)0xb42533d8, + (q31_t)0x670b4444, (q31_t)0xb410f6d3, (q31_t)0x66fc596f, (q31_t)0xb3fcbcbb, (q31_t)0x66ed6aa1, (q31_t)0xb3e88592, (q31_t)0x66de77dc, (q31_t)0xb3d45157, + (q31_t)0x66cf8120, (q31_t)0xb3c0200c, (q31_t)0x66c0866d, (q31_t)0xb3abf1b2, (q31_t)0x66b187c3, (q31_t)0xb397c649, (q31_t)0x66a28524, (q31_t)0xb3839dd3, + (q31_t)0x66937e91, (q31_t)0xb36f784f, (q31_t)0x66847408, (q31_t)0xb35b55bf, (q31_t)0x6675658c, (q31_t)0xb3473623, (q31_t)0x6666531d, (q31_t)0xb333197c, + (q31_t)0x66573cbb, (q31_t)0xb31effcc, (q31_t)0x66482267, (q31_t)0xb30ae912, (q31_t)0x66390422, (q31_t)0xb2f6d550, (q31_t)0x6629e1ec, (q31_t)0xb2e2c486, + (q31_t)0x661abbc5, (q31_t)0xb2ceb6b5, (q31_t)0x660b91af, (q31_t)0xb2baabde, (q31_t)0x65fc63a9, (q31_t)0xb2a6a402, (q31_t)0x65ed31b5, (q31_t)0xb2929f21, + (q31_t)0x65ddfbd3, (q31_t)0xb27e9d3c, (q31_t)0x65cec204, (q31_t)0xb26a9e54, (q31_t)0x65bf8447, (q31_t)0xb256a26a, (q31_t)0x65b0429f, (q31_t)0xb242a97e, + (q31_t)0x65a0fd0b, (q31_t)0xb22eb392, (q31_t)0x6591b38c, (q31_t)0xb21ac0a6, (q31_t)0x65826622, (q31_t)0xb206d0ba, (q31_t)0x657314cf, (q31_t)0xb1f2e3d0, + (q31_t)0x6563bf92, (q31_t)0xb1def9e9, (q31_t)0x6554666d, (q31_t)0xb1cb1304, (q31_t)0x6545095f, (q31_t)0xb1b72f23, (q31_t)0x6535a86b, (q31_t)0xb1a34e47, + (q31_t)0x6526438f, (q31_t)0xb18f7071, (q31_t)0x6516dacd, (q31_t)0xb17b95a0, (q31_t)0x65076e25, (q31_t)0xb167bdd7, (q31_t)0x64f7fd98, (q31_t)0xb153e915, + (q31_t)0x64e88926, (q31_t)0xb140175b, (q31_t)0x64d910d1, (q31_t)0xb12c48ab, (q31_t)0x64c99498, (q31_t)0xb1187d05, (q31_t)0x64ba147d, (q31_t)0xb104b46a, + (q31_t)0x64aa907f, (q31_t)0xb0f0eeda, (q31_t)0x649b08a0, (q31_t)0xb0dd2c56, (q31_t)0x648b7ce0, (q31_t)0xb0c96ce0, (q31_t)0x647bed3f, (q31_t)0xb0b5b077, + (q31_t)0x646c59bf, (q31_t)0xb0a1f71d, (q31_t)0x645cc260, (q31_t)0xb08e40d2, (q31_t)0x644d2722, (q31_t)0xb07a8d97, (q31_t)0x643d8806, (q31_t)0xb066dd6d, + (q31_t)0x642de50d, (q31_t)0xb0533055, (q31_t)0x641e3e38, (q31_t)0xb03f864f, (q31_t)0x640e9386, (q31_t)0xb02bdf5c, (q31_t)0x63fee4f8, (q31_t)0xb0183b7d, + (q31_t)0x63ef3290, (q31_t)0xb0049ab3, (q31_t)0x63df7c4d, (q31_t)0xaff0fcfe, (q31_t)0x63cfc231, (q31_t)0xafdd625f, (q31_t)0x63c0043b, (q31_t)0xafc9cad7, + (q31_t)0x63b0426d, (q31_t)0xafb63667, (q31_t)0x63a07cc7, (q31_t)0xafa2a50f, (q31_t)0x6390b34a, (q31_t)0xaf8f16d1, (q31_t)0x6380e5f6, (q31_t)0xaf7b8bac, + (q31_t)0x637114cc, (q31_t)0xaf6803a2, (q31_t)0x63613fcd, (q31_t)0xaf547eb3, (q31_t)0x635166f9, (q31_t)0xaf40fce1, (q31_t)0x63418a50, (q31_t)0xaf2d7e2b, + (q31_t)0x6331a9d4, (q31_t)0xaf1a0293, (q31_t)0x6321c585, (q31_t)0xaf068a1a, (q31_t)0x6311dd64, (q31_t)0xaef314c0, (q31_t)0x6301f171, (q31_t)0xaedfa285, + (q31_t)0x62f201ac, (q31_t)0xaecc336c, (q31_t)0x62e20e17, (q31_t)0xaeb8c774, (q31_t)0x62d216b3, (q31_t)0xaea55e9e, (q31_t)0x62c21b7e, (q31_t)0xae91f8eb, + (q31_t)0x62b21c7b, (q31_t)0xae7e965b, (q31_t)0x62a219aa, (q31_t)0xae6b36f0, (q31_t)0x6292130c, (q31_t)0xae57daab, (q31_t)0x628208a1, (q31_t)0xae44818b, + (q31_t)0x6271fa69, (q31_t)0xae312b92, (q31_t)0x6261e866, (q31_t)0xae1dd8c0, (q31_t)0x6251d298, (q31_t)0xae0a8916, (q31_t)0x6241b8ff, (q31_t)0xadf73c96, + (q31_t)0x62319b9d, (q31_t)0xade3f33e, (q31_t)0x62217a72, (q31_t)0xadd0ad12, (q31_t)0x6211557e, (q31_t)0xadbd6a10, (q31_t)0x62012cc2, (q31_t)0xadaa2a3b, + (q31_t)0x61f1003f, (q31_t)0xad96ed92, (q31_t)0x61e0cff5, (q31_t)0xad83b416, (q31_t)0x61d09be5, (q31_t)0xad707dc8, (q31_t)0x61c06410, (q31_t)0xad5d4aaa, + (q31_t)0x61b02876, (q31_t)0xad4a1aba, (q31_t)0x619fe918, (q31_t)0xad36edfc, (q31_t)0x618fa5f7, (q31_t)0xad23c46e, (q31_t)0x617f5f12, (q31_t)0xad109e12, + (q31_t)0x616f146c, (q31_t)0xacfd7ae8, (q31_t)0x615ec603, (q31_t)0xacea5af2, (q31_t)0x614e73da, (q31_t)0xacd73e30, (q31_t)0x613e1df0, (q31_t)0xacc424a3, + (q31_t)0x612dc447, (q31_t)0xacb10e4b, (q31_t)0x611d66de, (q31_t)0xac9dfb29, (q31_t)0x610d05b7, (q31_t)0xac8aeb3e, (q31_t)0x60fca0d2, (q31_t)0xac77de8b, + (q31_t)0x60ec3830, (q31_t)0xac64d510, (q31_t)0x60dbcbd1, (q31_t)0xac51cecf, (q31_t)0x60cb5bb7, (q31_t)0xac3ecbc7, (q31_t)0x60bae7e1, (q31_t)0xac2bcbfa, + (q31_t)0x60aa7050, (q31_t)0xac18cf69, (q31_t)0x6099f505, (q31_t)0xac05d613, (q31_t)0x60897601, (q31_t)0xabf2dffb, (q31_t)0x6078f344, (q31_t)0xabdfed1f, + (q31_t)0x60686ccf, (q31_t)0xabccfd83, (q31_t)0x6057e2a2, (q31_t)0xabba1125, (q31_t)0x604754bf, (q31_t)0xaba72807, (q31_t)0x6036c325, (q31_t)0xab944229, + (q31_t)0x60262dd6, (q31_t)0xab815f8d, (q31_t)0x601594d1, (q31_t)0xab6e8032, (q31_t)0x6004f819, (q31_t)0xab5ba41a, (q31_t)0x5ff457ad, (q31_t)0xab48cb46, + (q31_t)0x5fe3b38d, (q31_t)0xab35f5b5, (q31_t)0x5fd30bbc, (q31_t)0xab23236a, (q31_t)0x5fc26038, (q31_t)0xab105464, (q31_t)0x5fb1b104, (q31_t)0xaafd88a4, + (q31_t)0x5fa0fe1f, (q31_t)0xaaeac02c, (q31_t)0x5f90478a, (q31_t)0xaad7fafb, (q31_t)0x5f7f8d46, (q31_t)0xaac53912, (q31_t)0x5f6ecf53, (q31_t)0xaab27a73, + (q31_t)0x5f5e0db3, (q31_t)0xaa9fbf1e, (q31_t)0x5f4d4865, (q31_t)0xaa8d0713, (q31_t)0x5f3c7f6b, (q31_t)0xaa7a5253, (q31_t)0x5f2bb2c5, (q31_t)0xaa67a0e0, + (q31_t)0x5f1ae274, (q31_t)0xaa54f2ba, (q31_t)0x5f0a0e77, (q31_t)0xaa4247e1, (q31_t)0x5ef936d1, (q31_t)0xaa2fa056, (q31_t)0x5ee85b82, (q31_t)0xaa1cfc1a, + (q31_t)0x5ed77c8a, (q31_t)0xaa0a5b2e, (q31_t)0x5ec699e9, (q31_t)0xa9f7bd92, (q31_t)0x5eb5b3a2, (q31_t)0xa9e52347, (q31_t)0x5ea4c9b3, (q31_t)0xa9d28c4e, + (q31_t)0x5e93dc1f, (q31_t)0xa9bff8a8, (q31_t)0x5e82eae5, (q31_t)0xa9ad6855, (q31_t)0x5e71f606, (q31_t)0xa99adb56, (q31_t)0x5e60fd84, (q31_t)0xa98851ac, + (q31_t)0x5e50015d, (q31_t)0xa975cb57, (q31_t)0x5e3f0194, (q31_t)0xa9634858, (q31_t)0x5e2dfe29, (q31_t)0xa950c8b0, (q31_t)0x5e1cf71c, (q31_t)0xa93e4c5f, + (q31_t)0x5e0bec6e, (q31_t)0xa92bd367, (q31_t)0x5dfade20, (q31_t)0xa9195dc7, (q31_t)0x5de9cc33, (q31_t)0xa906eb82, (q31_t)0x5dd8b6a7, (q31_t)0xa8f47c97, + (q31_t)0x5dc79d7c, (q31_t)0xa8e21106, (q31_t)0x5db680b4, (q31_t)0xa8cfa8d2, (q31_t)0x5da5604f, (q31_t)0xa8bd43fa, (q31_t)0x5d943c4e, (q31_t)0xa8aae280, + (q31_t)0x5d8314b1, (q31_t)0xa8988463, (q31_t)0x5d71e979, (q31_t)0xa88629a5, (q31_t)0x5d60baa7, (q31_t)0xa873d246, (q31_t)0x5d4f883b, (q31_t)0xa8617e48, + (q31_t)0x5d3e5237, (q31_t)0xa84f2daa, (q31_t)0x5d2d189a, (q31_t)0xa83ce06e, (q31_t)0x5d1bdb65, (q31_t)0xa82a9693, (q31_t)0x5d0a9a9a, (q31_t)0xa818501c, + (q31_t)0x5cf95638, (q31_t)0xa8060d08, (q31_t)0x5ce80e41, (q31_t)0xa7f3cd59, (q31_t)0x5cd6c2b5, (q31_t)0xa7e1910f, (q31_t)0x5cc57394, (q31_t)0xa7cf582a, + (q31_t)0x5cb420e0, (q31_t)0xa7bd22ac, (q31_t)0x5ca2ca99, (q31_t)0xa7aaf094, (q31_t)0x5c9170bf, (q31_t)0xa798c1e5, (q31_t)0x5c801354, (q31_t)0xa786969e, + (q31_t)0x5c6eb258, (q31_t)0xa7746ec0, (q31_t)0x5c5d4dcc, (q31_t)0xa7624a4d, (q31_t)0x5c4be5b0, (q31_t)0xa7502943, (q31_t)0x5c3a7a05, (q31_t)0xa73e0ba5, + (q31_t)0x5c290acc, (q31_t)0xa72bf174, (q31_t)0x5c179806, (q31_t)0xa719daae, (q31_t)0x5c0621b2, (q31_t)0xa707c757, (q31_t)0x5bf4a7d2, (q31_t)0xa6f5b76d, + (q31_t)0x5be32a67, (q31_t)0xa6e3aaf2, (q31_t)0x5bd1a971, (q31_t)0xa6d1a1e7, (q31_t)0x5bc024f0, (q31_t)0xa6bf9c4b, (q31_t)0x5bae9ce7, (q31_t)0xa6ad9a21, + (q31_t)0x5b9d1154, (q31_t)0xa69b9b68, (q31_t)0x5b8b8239, (q31_t)0xa689a022, (q31_t)0x5b79ef96, (q31_t)0xa677a84e, (q31_t)0x5b68596d, (q31_t)0xa665b3ee, + (q31_t)0x5b56bfbd, (q31_t)0xa653c303, (q31_t)0x5b452288, (q31_t)0xa641d58c, (q31_t)0x5b3381ce, (q31_t)0xa62feb8b, (q31_t)0x5b21dd90, (q31_t)0xa61e0501, + (q31_t)0x5b1035cf, (q31_t)0xa60c21ee, (q31_t)0x5afe8a8b, (q31_t)0xa5fa4252, (q31_t)0x5aecdbc5, (q31_t)0xa5e8662f, (q31_t)0x5adb297d, (q31_t)0xa5d68d85, + (q31_t)0x5ac973b5, (q31_t)0xa5c4b855, (q31_t)0x5ab7ba6c, (q31_t)0xa5b2e6a0, (q31_t)0x5aa5fda5, (q31_t)0xa5a11866, (q31_t)0x5a943d5e, (q31_t)0xa58f4da8, + (q31_t)0x5a82799a, (q31_t)0xa57d8666, (q31_t)0x5a70b258, (q31_t)0xa56bc2a2, (q31_t)0x5a5ee79a, (q31_t)0xa55a025b, (q31_t)0x5a4d1960, (q31_t)0xa5484594, + (q31_t)0x5a3b47ab, (q31_t)0xa5368c4b, (q31_t)0x5a29727b, (q31_t)0xa524d683, (q31_t)0x5a1799d1, (q31_t)0xa513243b, (q31_t)0x5a05bdae, (q31_t)0xa5017575, + (q31_t)0x59f3de12, (q31_t)0xa4efca31, (q31_t)0x59e1faff, (q31_t)0xa4de2270, (q31_t)0x59d01475, (q31_t)0xa4cc7e32, (q31_t)0x59be2a74, (q31_t)0xa4badd78, + (q31_t)0x59ac3cfd, (q31_t)0xa4a94043, (q31_t)0x599a4c12, (q31_t)0xa497a693, (q31_t)0x598857b2, (q31_t)0xa486106a, (q31_t)0x59765fde, (q31_t)0xa4747dc7, + (q31_t)0x59646498, (q31_t)0xa462eeac, (q31_t)0x595265df, (q31_t)0xa4516319, (q31_t)0x594063b5, (q31_t)0xa43fdb10, (q31_t)0x592e5e19, (q31_t)0xa42e568f, + (q31_t)0x591c550e, (q31_t)0xa41cd599, (q31_t)0x590a4893, (q31_t)0xa40b582e, (q31_t)0x58f838a9, (q31_t)0xa3f9de4e, (q31_t)0x58e62552, (q31_t)0xa3e867fa, + (q31_t)0x58d40e8c, (q31_t)0xa3d6f534, (q31_t)0x58c1f45b, (q31_t)0xa3c585fb, (q31_t)0x58afd6bd, (q31_t)0xa3b41a50, (q31_t)0x589db5b3, (q31_t)0xa3a2b234, + (q31_t)0x588b9140, (q31_t)0xa3914da8, (q31_t)0x58796962, (q31_t)0xa37fecac, (q31_t)0x58673e1b, (q31_t)0xa36e8f41, (q31_t)0x58550f6c, (q31_t)0xa35d3567, + (q31_t)0x5842dd54, (q31_t)0xa34bdf20, (q31_t)0x5830a7d6, (q31_t)0xa33a8c6c, (q31_t)0x581e6ef1, (q31_t)0xa3293d4b, (q31_t)0x580c32a7, (q31_t)0xa317f1bf, + (q31_t)0x57f9f2f8, (q31_t)0xa306a9c8, (q31_t)0x57e7afe4, (q31_t)0xa2f56566, (q31_t)0x57d5696d, (q31_t)0xa2e4249b, (q31_t)0x57c31f92, (q31_t)0xa2d2e766, + (q31_t)0x57b0d256, (q31_t)0xa2c1adc9, (q31_t)0x579e81b8, (q31_t)0xa2b077c5, (q31_t)0x578c2dba, (q31_t)0xa29f4559, (q31_t)0x5779d65b, (q31_t)0xa28e1687, + (q31_t)0x57677b9d, (q31_t)0xa27ceb4f, (q31_t)0x57551d80, (q31_t)0xa26bc3b2, (q31_t)0x5742bc06, (q31_t)0xa25a9fb1, (q31_t)0x5730572e, (q31_t)0xa2497f4c, + (q31_t)0x571deefa, (q31_t)0xa2386284, (q31_t)0x570b8369, (q31_t)0xa2274959, (q31_t)0x56f9147e, (q31_t)0xa21633cd, (q31_t)0x56e6a239, (q31_t)0xa20521e0, + (q31_t)0x56d42c99, (q31_t)0xa1f41392, (q31_t)0x56c1b3a1, (q31_t)0xa1e308e4, (q31_t)0x56af3750, (q31_t)0xa1d201d7, (q31_t)0x569cb7a8, (q31_t)0xa1c0fe6c, + (q31_t)0x568a34a9, (q31_t)0xa1affea3, (q31_t)0x5677ae54, (q31_t)0xa19f027c, (q31_t)0x566524aa, (q31_t)0xa18e09fa, (q31_t)0x565297ab, (q31_t)0xa17d151b, + (q31_t)0x56400758, (q31_t)0xa16c23e1, (q31_t)0x562d73b2, (q31_t)0xa15b364d, (q31_t)0x561adcb9, (q31_t)0xa14a4c5e, (q31_t)0x5608426e, (q31_t)0xa1396617, + (q31_t)0x55f5a4d2, (q31_t)0xa1288376, (q31_t)0x55e303e6, (q31_t)0xa117a47e, (q31_t)0x55d05faa, (q31_t)0xa106c92f, (q31_t)0x55bdb81f, (q31_t)0xa0f5f189, + (q31_t)0x55ab0d46, (q31_t)0xa0e51d8c, (q31_t)0x55985f20, (q31_t)0xa0d44d3b, (q31_t)0x5585adad, (q31_t)0xa0c38095, (q31_t)0x5572f8ed, (q31_t)0xa0b2b79b, + (q31_t)0x556040e2, (q31_t)0xa0a1f24d, (q31_t)0x554d858d, (q31_t)0xa09130ad, (q31_t)0x553ac6ee, (q31_t)0xa08072ba, (q31_t)0x55280505, (q31_t)0xa06fb876, + (q31_t)0x55153fd4, (q31_t)0xa05f01e1, (q31_t)0x5502775c, (q31_t)0xa04e4efc, (q31_t)0x54efab9c, (q31_t)0xa03d9fc8, (q31_t)0x54dcdc96, (q31_t)0xa02cf444, + (q31_t)0x54ca0a4b, (q31_t)0xa01c4c73, (q31_t)0x54b734ba, (q31_t)0xa00ba853, (q31_t)0x54a45be6, (q31_t)0x9ffb07e7, (q31_t)0x54917fce, (q31_t)0x9fea6b2f, + (q31_t)0x547ea073, (q31_t)0x9fd9d22a, (q31_t)0x546bbdd7, (q31_t)0x9fc93cdb, (q31_t)0x5458d7f9, (q31_t)0x9fb8ab41, (q31_t)0x5445eedb, (q31_t)0x9fa81d5e, + (q31_t)0x5433027d, (q31_t)0x9f979331, (q31_t)0x542012e1, (q31_t)0x9f870cbc, (q31_t)0x540d2005, (q31_t)0x9f7689ff, (q31_t)0x53fa29ed, (q31_t)0x9f660afb, + (q31_t)0x53e73097, (q31_t)0x9f558fb0, (q31_t)0x53d43406, (q31_t)0x9f45181f, (q31_t)0x53c13439, (q31_t)0x9f34a449, (q31_t)0x53ae3131, (q31_t)0x9f24342f, + (q31_t)0x539b2af0, (q31_t)0x9f13c7d0, (q31_t)0x53882175, (q31_t)0x9f035f2e, (q31_t)0x537514c2, (q31_t)0x9ef2fa49, (q31_t)0x536204d7, (q31_t)0x9ee29922, + (q31_t)0x534ef1b5, (q31_t)0x9ed23bb9, (q31_t)0x533bdb5d, (q31_t)0x9ec1e210, (q31_t)0x5328c1d0, (q31_t)0x9eb18c26, (q31_t)0x5315a50e, (q31_t)0x9ea139fd, + (q31_t)0x53028518, (q31_t)0x9e90eb94, (q31_t)0x52ef61ee, (q31_t)0x9e80a0ee, (q31_t)0x52dc3b92, (q31_t)0x9e705a09, (q31_t)0x52c91204, (q31_t)0x9e6016e8, + (q31_t)0x52b5e546, (q31_t)0x9e4fd78a, (q31_t)0x52a2b556, (q31_t)0x9e3f9bf0, (q31_t)0x528f8238, (q31_t)0x9e2f641b, (q31_t)0x527c4bea, (q31_t)0x9e1f300b, + (q31_t)0x5269126e, (q31_t)0x9e0effc1, (q31_t)0x5255d5c5, (q31_t)0x9dfed33e, (q31_t)0x524295f0, (q31_t)0x9deeaa82, (q31_t)0x522f52ee, (q31_t)0x9dde858e, + (q31_t)0x521c0cc2, (q31_t)0x9dce6463, (q31_t)0x5208c36a, (q31_t)0x9dbe4701, (q31_t)0x51f576ea, (q31_t)0x9dae2d68, (q31_t)0x51e22740, (q31_t)0x9d9e179a, + (q31_t)0x51ced46e, (q31_t)0x9d8e0597, (q31_t)0x51bb7e75, (q31_t)0x9d7df75f, (q31_t)0x51a82555, (q31_t)0x9d6decf4, (q31_t)0x5194c910, (q31_t)0x9d5de656, + (q31_t)0x518169a5, (q31_t)0x9d4de385, (q31_t)0x516e0715, (q31_t)0x9d3de482, (q31_t)0x515aa162, (q31_t)0x9d2de94d, (q31_t)0x5147388c, (q31_t)0x9d1df1e9, + (q31_t)0x5133cc94, (q31_t)0x9d0dfe54, (q31_t)0x51205d7b, (q31_t)0x9cfe0e8f, (q31_t)0x510ceb40, (q31_t)0x9cee229c, (q31_t)0x50f975e6, (q31_t)0x9cde3a7b, + (q31_t)0x50e5fd6d, (q31_t)0x9cce562c, (q31_t)0x50d281d5, (q31_t)0x9cbe75b0, (q31_t)0x50bf031f, (q31_t)0x9cae9907, (q31_t)0x50ab814d, (q31_t)0x9c9ec033, + (q31_t)0x5097fc5e, (q31_t)0x9c8eeb34, (q31_t)0x50847454, (q31_t)0x9c7f1a0a, (q31_t)0x5070e92f, (q31_t)0x9c6f4cb6, (q31_t)0x505d5af1, (q31_t)0x9c5f8339, + (q31_t)0x5049c999, (q31_t)0x9c4fbd93, (q31_t)0x50363529, (q31_t)0x9c3ffbc5, (q31_t)0x50229da1, (q31_t)0x9c303dcf, (q31_t)0x500f0302, (q31_t)0x9c2083b3, + (q31_t)0x4ffb654d, (q31_t)0x9c10cd70, (q31_t)0x4fe7c483, (q31_t)0x9c011b08, (q31_t)0x4fd420a4, (q31_t)0x9bf16c7a, (q31_t)0x4fc079b1, (q31_t)0x9be1c1c8, + (q31_t)0x4faccfab, (q31_t)0x9bd21af3, (q31_t)0x4f992293, (q31_t)0x9bc277fa, (q31_t)0x4f857269, (q31_t)0x9bb2d8de, (q31_t)0x4f71bf2e, (q31_t)0x9ba33da0, + (q31_t)0x4f5e08e3, (q31_t)0x9b93a641, (q31_t)0x4f4a4f89, (q31_t)0x9b8412c1, (q31_t)0x4f369320, (q31_t)0x9b748320, (q31_t)0x4f22d3aa, (q31_t)0x9b64f760, + (q31_t)0x4f0f1126, (q31_t)0x9b556f81, (q31_t)0x4efb4b96, (q31_t)0x9b45eb83, (q31_t)0x4ee782fb, (q31_t)0x9b366b68, (q31_t)0x4ed3b755, (q31_t)0x9b26ef2f, + (q31_t)0x4ebfe8a5, (q31_t)0x9b1776da, (q31_t)0x4eac16eb, (q31_t)0x9b080268, (q31_t)0x4e984229, (q31_t)0x9af891db, (q31_t)0x4e846a60, (q31_t)0x9ae92533, + (q31_t)0x4e708f8f, (q31_t)0x9ad9bc71, (q31_t)0x4e5cb1b9, (q31_t)0x9aca5795, (q31_t)0x4e48d0dd, (q31_t)0x9abaf6a1, (q31_t)0x4e34ecfc, (q31_t)0x9aab9993, + (q31_t)0x4e210617, (q31_t)0x9a9c406e, (q31_t)0x4e0d1c30, (q31_t)0x9a8ceb31, (q31_t)0x4df92f46, (q31_t)0x9a7d99de, (q31_t)0x4de53f5a, (q31_t)0x9a6e4c74, + (q31_t)0x4dd14c6e, (q31_t)0x9a5f02f5, (q31_t)0x4dbd5682, (q31_t)0x9a4fbd61, (q31_t)0x4da95d96, (q31_t)0x9a407bb9, (q31_t)0x4d9561ac, (q31_t)0x9a313dfc, + (q31_t)0x4d8162c4, (q31_t)0x9a22042d, (q31_t)0x4d6d60df, (q31_t)0x9a12ce4b, (q31_t)0x4d595bfe, (q31_t)0x9a039c57, (q31_t)0x4d455422, (q31_t)0x99f46e51, + (q31_t)0x4d31494b, (q31_t)0x99e5443b, (q31_t)0x4d1d3b7a, (q31_t)0x99d61e14, (q31_t)0x4d092ab0, (q31_t)0x99c6fbde, (q31_t)0x4cf516ee, (q31_t)0x99b7dd99, + (q31_t)0x4ce10034, (q31_t)0x99a8c345, (q31_t)0x4ccce684, (q31_t)0x9999ace3, (q31_t)0x4cb8c9dd, (q31_t)0x998a9a74, (q31_t)0x4ca4aa41, (q31_t)0x997b8bf8, + (q31_t)0x4c9087b1, (q31_t)0x996c816f, (q31_t)0x4c7c622d, (q31_t)0x995d7adc, (q31_t)0x4c6839b7, (q31_t)0x994e783d, (q31_t)0x4c540e4e, (q31_t)0x993f7993, + (q31_t)0x4c3fdff4, (q31_t)0x99307ee0, (q31_t)0x4c2baea9, (q31_t)0x99218824, (q31_t)0x4c177a6e, (q31_t)0x9912955f, (q31_t)0x4c034345, (q31_t)0x9903a691, + (q31_t)0x4bef092d, (q31_t)0x98f4bbbc, (q31_t)0x4bdacc28, (q31_t)0x98e5d4e0, (q31_t)0x4bc68c36, (q31_t)0x98d6f1fe, (q31_t)0x4bb24958, (q31_t)0x98c81316, + (q31_t)0x4b9e0390, (q31_t)0x98b93828, (q31_t)0x4b89badd, (q31_t)0x98aa6136, (q31_t)0x4b756f40, (q31_t)0x989b8e40, (q31_t)0x4b6120bb, (q31_t)0x988cbf46, + (q31_t)0x4b4ccf4d, (q31_t)0x987df449, (q31_t)0x4b387af9, (q31_t)0x986f2d4a, (q31_t)0x4b2423be, (q31_t)0x98606a49, (q31_t)0x4b0fc99d, (q31_t)0x9851ab46, + (q31_t)0x4afb6c98, (q31_t)0x9842f043, (q31_t)0x4ae70caf, (q31_t)0x98343940, (q31_t)0x4ad2a9e2, (q31_t)0x9825863d, (q31_t)0x4abe4433, (q31_t)0x9816d73b, + (q31_t)0x4aa9dba2, (q31_t)0x98082c3b, (q31_t)0x4a957030, (q31_t)0x97f9853d, (q31_t)0x4a8101de, (q31_t)0x97eae242, (q31_t)0x4a6c90ad, (q31_t)0x97dc4349, + (q31_t)0x4a581c9e, (q31_t)0x97cda855, (q31_t)0x4a43a5b0, (q31_t)0x97bf1165, (q31_t)0x4a2f2be6, (q31_t)0x97b07e7a, (q31_t)0x4a1aaf3f, (q31_t)0x97a1ef94, + (q31_t)0x4a062fbd, (q31_t)0x979364b5, (q31_t)0x49f1ad61, (q31_t)0x9784dddc, (q31_t)0x49dd282a, (q31_t)0x97765b0a, (q31_t)0x49c8a01b, (q31_t)0x9767dc41, + (q31_t)0x49b41533, (q31_t)0x9759617f, (q31_t)0x499f8774, (q31_t)0x974aeac6, (q31_t)0x498af6df, (q31_t)0x973c7817, (q31_t)0x49766373, (q31_t)0x972e0971, + (q31_t)0x4961cd33, (q31_t)0x971f9ed7, (q31_t)0x494d341e, (q31_t)0x97113847, (q31_t)0x49389836, (q31_t)0x9702d5c3, (q31_t)0x4923f97b, (q31_t)0x96f4774b, + (q31_t)0x490f57ee, (q31_t)0x96e61ce0, (q31_t)0x48fab391, (q31_t)0x96d7c682, (q31_t)0x48e60c62, (q31_t)0x96c97432, (q31_t)0x48d16265, (q31_t)0x96bb25f0, + (q31_t)0x48bcb599, (q31_t)0x96acdbbe, (q31_t)0x48a805ff, (q31_t)0x969e959b, (q31_t)0x48935397, (q31_t)0x96905388, (q31_t)0x487e9e64, (q31_t)0x96821585, + (q31_t)0x4869e665, (q31_t)0x9673db94, (q31_t)0x48552b9b, (q31_t)0x9665a5b4, (q31_t)0x48406e08, (q31_t)0x965773e7, (q31_t)0x482badab, (q31_t)0x9649462d, + (q31_t)0x4816ea86, (q31_t)0x963b1c86, (q31_t)0x48022499, (q31_t)0x962cf6f2, (q31_t)0x47ed5be6, (q31_t)0x961ed574, (q31_t)0x47d8906d, (q31_t)0x9610b80a, + (q31_t)0x47c3c22f, (q31_t)0x96029eb6, (q31_t)0x47aef12c, (q31_t)0x95f48977, (q31_t)0x479a1d67, (q31_t)0x95e67850, (q31_t)0x478546de, (q31_t)0x95d86b3f, + (q31_t)0x47706d93, (q31_t)0x95ca6247, (q31_t)0x475b9188, (q31_t)0x95bc5d66, (q31_t)0x4746b2bc, (q31_t)0x95ae5c9f, (q31_t)0x4731d131, (q31_t)0x95a05ff0, + (q31_t)0x471cece7, (q31_t)0x9592675c, (q31_t)0x470805df, (q31_t)0x958472e2, (q31_t)0x46f31c1a, (q31_t)0x95768283, (q31_t)0x46de2f99, (q31_t)0x9568963f, + (q31_t)0x46c9405c, (q31_t)0x955aae17, (q31_t)0x46b44e65, (q31_t)0x954cca0c, (q31_t)0x469f59b4, (q31_t)0x953eea1e, (q31_t)0x468a624a, (q31_t)0x95310e4e, + (q31_t)0x46756828, (q31_t)0x9523369c, (q31_t)0x46606b4e, (q31_t)0x95156308, (q31_t)0x464b6bbe, (q31_t)0x95079394, (q31_t)0x46366978, (q31_t)0x94f9c83f, + (q31_t)0x4621647d, (q31_t)0x94ec010b, (q31_t)0x460c5cce, (q31_t)0x94de3df8, (q31_t)0x45f7526b, (q31_t)0x94d07f05, (q31_t)0x45e24556, (q31_t)0x94c2c435, + (q31_t)0x45cd358f, (q31_t)0x94b50d87, (q31_t)0x45b82318, (q31_t)0x94a75afd, (q31_t)0x45a30df0, (q31_t)0x9499ac95, (q31_t)0x458df619, (q31_t)0x948c0252, + (q31_t)0x4578db93, (q31_t)0x947e5c33, (q31_t)0x4563be60, (q31_t)0x9470ba39, (q31_t)0x454e9e80, (q31_t)0x94631c65, (q31_t)0x45397bf4, (q31_t)0x945582b7, + (q31_t)0x452456bd, (q31_t)0x9447ed2f, (q31_t)0x450f2edb, (q31_t)0x943a5bcf, (q31_t)0x44fa0450, (q31_t)0x942cce96, (q31_t)0x44e4d71c, (q31_t)0x941f4585, + (q31_t)0x44cfa740, (q31_t)0x9411c09e, (q31_t)0x44ba74bd, (q31_t)0x94043fdf, (q31_t)0x44a53f93, (q31_t)0x93f6c34a, (q31_t)0x449007c4, (q31_t)0x93e94adf, + (q31_t)0x447acd50, (q31_t)0x93dbd6a0, (q31_t)0x44659039, (q31_t)0x93ce668b, (q31_t)0x4450507e, (q31_t)0x93c0faa3, (q31_t)0x443b0e21, (q31_t)0x93b392e6, + (q31_t)0x4425c923, (q31_t)0x93a62f57, (q31_t)0x44108184, (q31_t)0x9398cff5, (q31_t)0x43fb3746, (q31_t)0x938b74c1, (q31_t)0x43e5ea68, (q31_t)0x937e1dbb, + (q31_t)0x43d09aed, (q31_t)0x9370cae4, (q31_t)0x43bb48d4, (q31_t)0x93637c3d, (q31_t)0x43a5f41e, (q31_t)0x935631c5, (q31_t)0x43909ccd, (q31_t)0x9348eb7e, + (q31_t)0x437b42e1, (q31_t)0x933ba968, (q31_t)0x4365e65b, (q31_t)0x932e6b84, (q31_t)0x4350873c, (q31_t)0x932131d1, (q31_t)0x433b2585, (q31_t)0x9313fc51, + (q31_t)0x4325c135, (q31_t)0x9306cb04, (q31_t)0x43105a50, (q31_t)0x92f99deb, (q31_t)0x42faf0d4, (q31_t)0x92ec7505, (q31_t)0x42e584c3, (q31_t)0x92df5054, + (q31_t)0x42d0161e, (q31_t)0x92d22fd9, (q31_t)0x42baa4e6, (q31_t)0x92c51392, (q31_t)0x42a5311b, (q31_t)0x92b7fb82, (q31_t)0x428fbabe, (q31_t)0x92aae7a8, + (q31_t)0x427a41d0, (q31_t)0x929dd806, (q31_t)0x4264c653, (q31_t)0x9290cc9b, (q31_t)0x424f4845, (q31_t)0x9283c568, (q31_t)0x4239c7aa, (q31_t)0x9276c26d, + (q31_t)0x42244481, (q31_t)0x9269c3ac, (q31_t)0x420ebecb, (q31_t)0x925cc924, (q31_t)0x41f93689, (q31_t)0x924fd2d7, (q31_t)0x41e3abbc, (q31_t)0x9242e0c4, + (q31_t)0x41ce1e65, (q31_t)0x9235f2ec, (q31_t)0x41b88e84, (q31_t)0x9229094f, (q31_t)0x41a2fc1a, (q31_t)0x921c23ef, (q31_t)0x418d6729, (q31_t)0x920f42cb, + (q31_t)0x4177cfb1, (q31_t)0x920265e4, (q31_t)0x416235b2, (q31_t)0x91f58d3b, (q31_t)0x414c992f, (q31_t)0x91e8b8d0, (q31_t)0x4136fa27, (q31_t)0x91dbe8a4, + (q31_t)0x4121589b, (q31_t)0x91cf1cb6, (q31_t)0x410bb48c, (q31_t)0x91c25508, (q31_t)0x40f60dfb, (q31_t)0x91b5919a, (q31_t)0x40e064ea, (q31_t)0x91a8d26d, + (q31_t)0x40cab958, (q31_t)0x919c1781, (q31_t)0x40b50b46, (q31_t)0x918f60d6, (q31_t)0x409f5ab6, (q31_t)0x9182ae6d, (q31_t)0x4089a7a8, (q31_t)0x91760047, + (q31_t)0x4073f21d, (q31_t)0x91695663, (q31_t)0x405e3a16, (q31_t)0x915cb0c3, (q31_t)0x40487f94, (q31_t)0x91500f67, (q31_t)0x4032c297, (q31_t)0x91437250, + (q31_t)0x401d0321, (q31_t)0x9136d97d, (q31_t)0x40074132, (q31_t)0x912a44f0, (q31_t)0x3ff17cca, (q31_t)0x911db4a9, (q31_t)0x3fdbb5ec, (q31_t)0x911128a8, + (q31_t)0x3fc5ec98, (q31_t)0x9104a0ee, (q31_t)0x3fb020ce, (q31_t)0x90f81d7b, (q31_t)0x3f9a5290, (q31_t)0x90eb9e50, (q31_t)0x3f8481dd, (q31_t)0x90df236e, + (q31_t)0x3f6eaeb8, (q31_t)0x90d2acd4, (q31_t)0x3f58d921, (q31_t)0x90c63a83, (q31_t)0x3f430119, (q31_t)0x90b9cc7d, (q31_t)0x3f2d26a0, (q31_t)0x90ad62c0, + (q31_t)0x3f1749b8, (q31_t)0x90a0fd4e, (q31_t)0x3f016a61, (q31_t)0x90949c28, (q31_t)0x3eeb889c, (q31_t)0x90883f4d, (q31_t)0x3ed5a46b, (q31_t)0x907be6be, + (q31_t)0x3ebfbdcd, (q31_t)0x906f927c, (q31_t)0x3ea9d4c3, (q31_t)0x90634287, (q31_t)0x3e93e950, (q31_t)0x9056f6df, (q31_t)0x3e7dfb73, (q31_t)0x904aaf86, + (q31_t)0x3e680b2c, (q31_t)0x903e6c7b, (q31_t)0x3e52187f, (q31_t)0x90322dbf, (q31_t)0x3e3c2369, (q31_t)0x9025f352, (q31_t)0x3e262bee, (q31_t)0x9019bd36, + (q31_t)0x3e10320d, (q31_t)0x900d8b69, (q31_t)0x3dfa35c8, (q31_t)0x90015dee, (q31_t)0x3de4371f, (q31_t)0x8ff534c4, (q31_t)0x3dce3614, (q31_t)0x8fe90fec, + (q31_t)0x3db832a6, (q31_t)0x8fdcef66, (q31_t)0x3da22cd7, (q31_t)0x8fd0d333, (q31_t)0x3d8c24a8, (q31_t)0x8fc4bb53, (q31_t)0x3d761a19, (q31_t)0x8fb8a7c7, + (q31_t)0x3d600d2c, (q31_t)0x8fac988f, (q31_t)0x3d49fde1, (q31_t)0x8fa08dab, (q31_t)0x3d33ec39, (q31_t)0x8f94871d, (q31_t)0x3d1dd835, (q31_t)0x8f8884e4, + (q31_t)0x3d07c1d6, (q31_t)0x8f7c8701, (q31_t)0x3cf1a91c, (q31_t)0x8f708d75, (q31_t)0x3cdb8e09, (q31_t)0x8f649840, (q31_t)0x3cc5709e, (q31_t)0x8f58a761, + (q31_t)0x3caf50da, (q31_t)0x8f4cbadb, (q31_t)0x3c992ec0, (q31_t)0x8f40d2ad, (q31_t)0x3c830a50, (q31_t)0x8f34eed8, (q31_t)0x3c6ce38a, (q31_t)0x8f290f5c, + (q31_t)0x3c56ba70, (q31_t)0x8f1d343a, (q31_t)0x3c408f03, (q31_t)0x8f115d72, (q31_t)0x3c2a6142, (q31_t)0x8f058b04, (q31_t)0x3c143130, (q31_t)0x8ef9bcf2, + (q31_t)0x3bfdfecd, (q31_t)0x8eedf33b, (q31_t)0x3be7ca1a, (q31_t)0x8ee22de0, (q31_t)0x3bd19318, (q31_t)0x8ed66ce1, (q31_t)0x3bbb59c7, (q31_t)0x8ecab040, + (q31_t)0x3ba51e29, (q31_t)0x8ebef7fb, (q31_t)0x3b8ee03e, (q31_t)0x8eb34415, (q31_t)0x3b78a007, (q31_t)0x8ea7948c, (q31_t)0x3b625d86, (q31_t)0x8e9be963, + (q31_t)0x3b4c18ba, (q31_t)0x8e904298, (q31_t)0x3b35d1a5, (q31_t)0x8e84a02d, (q31_t)0x3b1f8848, (q31_t)0x8e790222, (q31_t)0x3b093ca3, (q31_t)0x8e6d6877, + (q31_t)0x3af2eeb7, (q31_t)0x8e61d32e, (q31_t)0x3adc9e86, (q31_t)0x8e564246, (q31_t)0x3ac64c0f, (q31_t)0x8e4ab5bf, (q31_t)0x3aaff755, (q31_t)0x8e3f2d9b, + (q31_t)0x3a99a057, (q31_t)0x8e33a9da, (q31_t)0x3a834717, (q31_t)0x8e282a7b, (q31_t)0x3a6ceb96, (q31_t)0x8e1caf80, (q31_t)0x3a568dd4, (q31_t)0x8e1138ea, + (q31_t)0x3a402dd2, (q31_t)0x8e05c6b7, (q31_t)0x3a29cb91, (q31_t)0x8dfa58ea, (q31_t)0x3a136712, (q31_t)0x8deeef82, (q31_t)0x39fd0056, (q31_t)0x8de38a80, + (q31_t)0x39e6975e, (q31_t)0x8dd829e4, (q31_t)0x39d02c2a, (q31_t)0x8dcccdaf, (q31_t)0x39b9bebc, (q31_t)0x8dc175e0, (q31_t)0x39a34f13, (q31_t)0x8db6227a, + (q31_t)0x398cdd32, (q31_t)0x8daad37b, (q31_t)0x39766919, (q31_t)0x8d9f88e5, (q31_t)0x395ff2c9, (q31_t)0x8d9442b8, (q31_t)0x39497a43, (q31_t)0x8d8900f3, + (q31_t)0x3932ff87, (q31_t)0x8d7dc399, (q31_t)0x391c8297, (q31_t)0x8d728aa9, (q31_t)0x39060373, (q31_t)0x8d675623, (q31_t)0x38ef821c, (q31_t)0x8d5c2609, + (q31_t)0x38d8fe93, (q31_t)0x8d50fa59, (q31_t)0x38c278d9, (q31_t)0x8d45d316, (q31_t)0x38abf0ef, (q31_t)0x8d3ab03f, (q31_t)0x389566d6, (q31_t)0x8d2f91d5, + (q31_t)0x387eda8e, (q31_t)0x8d2477d8, (q31_t)0x38684c19, (q31_t)0x8d196249, (q31_t)0x3851bb77, (q31_t)0x8d0e5127, (q31_t)0x383b28a9, (q31_t)0x8d034474, + (q31_t)0x382493b0, (q31_t)0x8cf83c30, (q31_t)0x380dfc8d, (q31_t)0x8ced385b, (q31_t)0x37f76341, (q31_t)0x8ce238f6, (q31_t)0x37e0c7cc, (q31_t)0x8cd73e01, + (q31_t)0x37ca2a30, (q31_t)0x8ccc477d, (q31_t)0x37b38a6d, (q31_t)0x8cc1556a, (q31_t)0x379ce885, (q31_t)0x8cb667c8, (q31_t)0x37864477, (q31_t)0x8cab7e98, + (q31_t)0x376f9e46, (q31_t)0x8ca099da, (q31_t)0x3758f5f2, (q31_t)0x8c95b98f, (q31_t)0x37424b7b, (q31_t)0x8c8addb7, (q31_t)0x372b9ee3, (q31_t)0x8c800652, + (q31_t)0x3714f02a, (q31_t)0x8c753362, (q31_t)0x36fe3f52, (q31_t)0x8c6a64e5, (q31_t)0x36e78c5b, (q31_t)0x8c5f9ade, (q31_t)0x36d0d746, (q31_t)0x8c54d54c, + (q31_t)0x36ba2014, (q31_t)0x8c4a142f, (q31_t)0x36a366c6, (q31_t)0x8c3f5788, (q31_t)0x368cab5c, (q31_t)0x8c349f58, (q31_t)0x3675edd9, (q31_t)0x8c29eb9f, + (q31_t)0x365f2e3b, (q31_t)0x8c1f3c5d, (q31_t)0x36486c86, (q31_t)0x8c149192, (q31_t)0x3631a8b8, (q31_t)0x8c09eb40, (q31_t)0x361ae2d3, (q31_t)0x8bff4966, + (q31_t)0x36041ad9, (q31_t)0x8bf4ac05, (q31_t)0x35ed50c9, (q31_t)0x8bea131e, (q31_t)0x35d684a6, (q31_t)0x8bdf7eb0, (q31_t)0x35bfb66e, (q31_t)0x8bd4eebc, + (q31_t)0x35a8e625, (q31_t)0x8bca6343, (q31_t)0x359213c9, (q31_t)0x8bbfdc44, (q31_t)0x357b3f5d, (q31_t)0x8bb559c1, (q31_t)0x356468e2, (q31_t)0x8baadbba, + (q31_t)0x354d9057, (q31_t)0x8ba0622f, (q31_t)0x3536b5be, (q31_t)0x8b95ed21, (q31_t)0x351fd918, (q31_t)0x8b8b7c8f, (q31_t)0x3508fa66, (q31_t)0x8b81107b, + (q31_t)0x34f219a8, (q31_t)0x8b76a8e4, (q31_t)0x34db36df, (q31_t)0x8b6c45cc, (q31_t)0x34c4520d, (q31_t)0x8b61e733, (q31_t)0x34ad6b32, (q31_t)0x8b578d18, + (q31_t)0x34968250, (q31_t)0x8b4d377c, (q31_t)0x347f9766, (q31_t)0x8b42e661, (q31_t)0x3468aa76, (q31_t)0x8b3899c6, (q31_t)0x3451bb81, (q31_t)0x8b2e51ab, + (q31_t)0x343aca87, (q31_t)0x8b240e11, (q31_t)0x3423d78a, (q31_t)0x8b19cef8, (q31_t)0x340ce28b, (q31_t)0x8b0f9462, (q31_t)0x33f5eb89, (q31_t)0x8b055e4d, + (q31_t)0x33def287, (q31_t)0x8afb2cbb, (q31_t)0x33c7f785, (q31_t)0x8af0ffac, (q31_t)0x33b0fa84, (q31_t)0x8ae6d720, (q31_t)0x3399fb85, (q31_t)0x8adcb318, + (q31_t)0x3382fa88, (q31_t)0x8ad29394, (q31_t)0x336bf78f, (q31_t)0x8ac87894, (q31_t)0x3354f29b, (q31_t)0x8abe6219, (q31_t)0x333debab, (q31_t)0x8ab45024, + (q31_t)0x3326e2c3, (q31_t)0x8aaa42b4, (q31_t)0x330fd7e1, (q31_t)0x8aa039cb, (q31_t)0x32f8cb07, (q31_t)0x8a963567, (q31_t)0x32e1bc36, (q31_t)0x8a8c358b, + (q31_t)0x32caab6f, (q31_t)0x8a823a36, (q31_t)0x32b398b3, (q31_t)0x8a784368, (q31_t)0x329c8402, (q31_t)0x8a6e5123, (q31_t)0x32856d5e, (q31_t)0x8a646365, + (q31_t)0x326e54c7, (q31_t)0x8a5a7a31, (q31_t)0x32573a3f, (q31_t)0x8a509585, (q31_t)0x32401dc6, (q31_t)0x8a46b564, (q31_t)0x3228ff5c, (q31_t)0x8a3cd9cc, + (q31_t)0x3211df04, (q31_t)0x8a3302be, (q31_t)0x31fabcbd, (q31_t)0x8a29303b, (q31_t)0x31e39889, (q31_t)0x8a1f6243, (q31_t)0x31cc7269, (q31_t)0x8a1598d6, + (q31_t)0x31b54a5e, (q31_t)0x8a0bd3f5, (q31_t)0x319e2067, (q31_t)0x8a0213a0, (q31_t)0x3186f487, (q31_t)0x89f857d8, (q31_t)0x316fc6be, (q31_t)0x89eea09d, + (q31_t)0x3158970e, (q31_t)0x89e4edef, (q31_t)0x31416576, (q31_t)0x89db3fcf, (q31_t)0x312a31f8, (q31_t)0x89d1963c, (q31_t)0x3112fc95, (q31_t)0x89c7f138, + (q31_t)0x30fbc54d, (q31_t)0x89be50c3, (q31_t)0x30e48c22, (q31_t)0x89b4b4dd, (q31_t)0x30cd5115, (q31_t)0x89ab1d87, (q31_t)0x30b61426, (q31_t)0x89a18ac0, + (q31_t)0x309ed556, (q31_t)0x8997fc8a, (q31_t)0x308794a6, (q31_t)0x898e72e4, (q31_t)0x30705217, (q31_t)0x8984edcf, (q31_t)0x30590dab, (q31_t)0x897b6d4c, + (q31_t)0x3041c761, (q31_t)0x8971f15a, (q31_t)0x302a7f3a, (q31_t)0x896879fb, (q31_t)0x30133539, (q31_t)0x895f072e, (q31_t)0x2ffbe95d, (q31_t)0x895598f3, + (q31_t)0x2fe49ba7, (q31_t)0x894c2f4c, (q31_t)0x2fcd4c19, (q31_t)0x8942ca39, (q31_t)0x2fb5fab2, (q31_t)0x893969b9, (q31_t)0x2f9ea775, (q31_t)0x89300dce, + (q31_t)0x2f875262, (q31_t)0x8926b677, (q31_t)0x2f6ffb7a, (q31_t)0x891d63b5, (q31_t)0x2f58a2be, (q31_t)0x89141589, (q31_t)0x2f41482e, (q31_t)0x890acbf2, + (q31_t)0x2f29ebcc, (q31_t)0x890186f2, (q31_t)0x2f128d99, (q31_t)0x88f84687, (q31_t)0x2efb2d95, (q31_t)0x88ef0ab4, (q31_t)0x2ee3cbc1, (q31_t)0x88e5d378, + (q31_t)0x2ecc681e, (q31_t)0x88dca0d3, (q31_t)0x2eb502ae, (q31_t)0x88d372c6, (q31_t)0x2e9d9b70, (q31_t)0x88ca4951, (q31_t)0x2e863267, (q31_t)0x88c12475, + (q31_t)0x2e6ec792, (q31_t)0x88b80432, (q31_t)0x2e575af3, (q31_t)0x88aee888, (q31_t)0x2e3fec8b, (q31_t)0x88a5d177, (q31_t)0x2e287c5a, (q31_t)0x889cbf01, + (q31_t)0x2e110a62, (q31_t)0x8893b125, (q31_t)0x2df996a3, (q31_t)0x888aa7e3, (q31_t)0x2de2211e, (q31_t)0x8881a33d, (q31_t)0x2dcaa9d5, (q31_t)0x8878a332, + (q31_t)0x2db330c7, (q31_t)0x886fa7c2, (q31_t)0x2d9bb5f6, (q31_t)0x8866b0ef, (q31_t)0x2d843964, (q31_t)0x885dbeb8, (q31_t)0x2d6cbb10, (q31_t)0x8854d11e, + (q31_t)0x2d553afc, (q31_t)0x884be821, (q31_t)0x2d3db928, (q31_t)0x884303c1, (q31_t)0x2d263596, (q31_t)0x883a23ff, (q31_t)0x2d0eb046, (q31_t)0x883148db, + (q31_t)0x2cf72939, (q31_t)0x88287256, (q31_t)0x2cdfa071, (q31_t)0x881fa06f, (q31_t)0x2cc815ee, (q31_t)0x8816d327, (q31_t)0x2cb089b1, (q31_t)0x880e0a7f, + (q31_t)0x2c98fbba, (q31_t)0x88054677, (q31_t)0x2c816c0c, (q31_t)0x87fc870f, (q31_t)0x2c69daa6, (q31_t)0x87f3cc48, (q31_t)0x2c52478a, (q31_t)0x87eb1621, + (q31_t)0x2c3ab2b9, (q31_t)0x87e2649b, (q31_t)0x2c231c33, (q31_t)0x87d9b7b7, (q31_t)0x2c0b83fa, (q31_t)0x87d10f75, (q31_t)0x2bf3ea0d, (q31_t)0x87c86bd5, + (q31_t)0x2bdc4e6f, (q31_t)0x87bfccd7, (q31_t)0x2bc4b120, (q31_t)0x87b7327d, (q31_t)0x2bad1221, (q31_t)0x87ae9cc5, (q31_t)0x2b957173, (q31_t)0x87a60bb1, + (q31_t)0x2b7dcf17, (q31_t)0x879d7f41, (q31_t)0x2b662b0e, (q31_t)0x8794f774, (q31_t)0x2b4e8558, (q31_t)0x878c744d, (q31_t)0x2b36ddf7, (q31_t)0x8783f5ca, + (q31_t)0x2b1f34eb, (q31_t)0x877b7bec, (q31_t)0x2b078a36, (q31_t)0x877306b4, (q31_t)0x2aefddd8, (q31_t)0x876a9621, (q31_t)0x2ad82fd2, (q31_t)0x87622a35, + (q31_t)0x2ac08026, (q31_t)0x8759c2ef, (q31_t)0x2aa8ced3, (q31_t)0x87516050, (q31_t)0x2a911bdc, (q31_t)0x87490258, (q31_t)0x2a796740, (q31_t)0x8740a907, + (q31_t)0x2a61b101, (q31_t)0x8738545e, (q31_t)0x2a49f920, (q31_t)0x8730045d, (q31_t)0x2a323f9e, (q31_t)0x8727b905, (q31_t)0x2a1a847b, (q31_t)0x871f7255, + (q31_t)0x2a02c7b8, (q31_t)0x8717304e, (q31_t)0x29eb0957, (q31_t)0x870ef2f1, (q31_t)0x29d34958, (q31_t)0x8706ba3d, (q31_t)0x29bb87bc, (q31_t)0x86fe8633, + (q31_t)0x29a3c485, (q31_t)0x86f656d3, (q31_t)0x298bffb2, (q31_t)0x86ee2c1e, (q31_t)0x29743946, (q31_t)0x86e60614, (q31_t)0x295c7140, (q31_t)0x86dde4b5, + (q31_t)0x2944a7a2, (q31_t)0x86d5c802, (q31_t)0x292cdc6d, (q31_t)0x86cdaffa, (q31_t)0x29150fa1, (q31_t)0x86c59c9f, (q31_t)0x28fd4140, (q31_t)0x86bd8df0, + (q31_t)0x28e5714b, (q31_t)0x86b583ee, (q31_t)0x28cd9fc1, (q31_t)0x86ad7e99, (q31_t)0x28b5cca5, (q31_t)0x86a57df2, (q31_t)0x289df7f8, (q31_t)0x869d81f8, + (q31_t)0x288621b9, (q31_t)0x86958aac, (q31_t)0x286e49ea, (q31_t)0x868d980e, (q31_t)0x2856708d, (q31_t)0x8685aa20, (q31_t)0x283e95a1, (q31_t)0x867dc0e0, + (q31_t)0x2826b928, (q31_t)0x8675dc4f, (q31_t)0x280edb23, (q31_t)0x866dfc6e, (q31_t)0x27f6fb92, (q31_t)0x8666213c, (q31_t)0x27df1a77, (q31_t)0x865e4abb, + (q31_t)0x27c737d3, (q31_t)0x865678eb, (q31_t)0x27af53a6, (q31_t)0x864eabcb, (q31_t)0x27976df1, (q31_t)0x8646e35c, (q31_t)0x277f86b5, (q31_t)0x863f1f9e, + (q31_t)0x27679df4, (q31_t)0x86376092, (q31_t)0x274fb3ae, (q31_t)0x862fa638, (q31_t)0x2737c7e3, (q31_t)0x8627f091, (q31_t)0x271fda96, (q31_t)0x86203f9c, + (q31_t)0x2707ebc7, (q31_t)0x86189359, (q31_t)0x26effb76, (q31_t)0x8610ebca, (q31_t)0x26d809a5, (q31_t)0x860948ef, (q31_t)0x26c01655, (q31_t)0x8601aac7, + (q31_t)0x26a82186, (q31_t)0x85fa1153, (q31_t)0x26902b39, (q31_t)0x85f27c93, (q31_t)0x26783370, (q31_t)0x85eaec88, (q31_t)0x26603a2c, (q31_t)0x85e36132, + (q31_t)0x26483f6c, (q31_t)0x85dbda91, (q31_t)0x26304333, (q31_t)0x85d458a6, (q31_t)0x26184581, (q31_t)0x85ccdb70, (q31_t)0x26004657, (q31_t)0x85c562f1, + (q31_t)0x25e845b6, (q31_t)0x85bdef28, (q31_t)0x25d0439f, (q31_t)0x85b68015, (q31_t)0x25b84012, (q31_t)0x85af15b9, (q31_t)0x25a03b11, (q31_t)0x85a7b015, + (q31_t)0x2588349d, (q31_t)0x85a04f28, (q31_t)0x25702cb7, (q31_t)0x8598f2f3, (q31_t)0x2558235f, (q31_t)0x85919b76, (q31_t)0x25401896, (q31_t)0x858a48b1, + (q31_t)0x25280c5e, (q31_t)0x8582faa5, (q31_t)0x250ffeb7, (q31_t)0x857bb152, (q31_t)0x24f7efa2, (q31_t)0x85746cb8, (q31_t)0x24dfdf20, (q31_t)0x856d2cd7, + (q31_t)0x24c7cd33, (q31_t)0x8565f1b0, (q31_t)0x24afb9da, (q31_t)0x855ebb44, (q31_t)0x2497a517, (q31_t)0x85578991, (q31_t)0x247f8eec, (q31_t)0x85505c99, + (q31_t)0x24677758, (q31_t)0x8549345c, (q31_t)0x244f5e5c, (q31_t)0x854210db, (q31_t)0x243743fa, (q31_t)0x853af214, (q31_t)0x241f2833, (q31_t)0x8533d809, + (q31_t)0x24070b08, (q31_t)0x852cc2bb, (q31_t)0x23eeec78, (q31_t)0x8525b228, (q31_t)0x23d6cc87, (q31_t)0x851ea652, (q31_t)0x23beab33, (q31_t)0x85179f39, + (q31_t)0x23a6887f, (q31_t)0x85109cdd, (q31_t)0x238e646a, (q31_t)0x85099f3e, (q31_t)0x23763ef7, (q31_t)0x8502a65c, (q31_t)0x235e1826, (q31_t)0x84fbb239, + (q31_t)0x2345eff8, (q31_t)0x84f4c2d4, (q31_t)0x232dc66d, (q31_t)0x84edd82d, (q31_t)0x23159b88, (q31_t)0x84e6f244, (q31_t)0x22fd6f48, (q31_t)0x84e0111b, + (q31_t)0x22e541af, (q31_t)0x84d934b1, (q31_t)0x22cd12bd, (q31_t)0x84d25d06, (q31_t)0x22b4e274, (q31_t)0x84cb8a1b, (q31_t)0x229cb0d5, (q31_t)0x84c4bbf0, + (q31_t)0x22847de0, (q31_t)0x84bdf286, (q31_t)0x226c4996, (q31_t)0x84b72ddb, (q31_t)0x225413f8, (q31_t)0x84b06df2, (q31_t)0x223bdd08, (q31_t)0x84a9b2ca, + (q31_t)0x2223a4c5, (q31_t)0x84a2fc62, (q31_t)0x220b6b32, (q31_t)0x849c4abd, (q31_t)0x21f3304f, (q31_t)0x84959dd9, (q31_t)0x21daf41d, (q31_t)0x848ef5b7, + (q31_t)0x21c2b69c, (q31_t)0x84885258, (q31_t)0x21aa77cf, (q31_t)0x8481b3bb, (q31_t)0x219237b5, (q31_t)0x847b19e1, (q31_t)0x2179f64f, (q31_t)0x847484ca, + (q31_t)0x2161b3a0, (q31_t)0x846df477, (q31_t)0x21496fa7, (q31_t)0x846768e7, (q31_t)0x21312a65, (q31_t)0x8460e21a, (q31_t)0x2118e3dc, (q31_t)0x845a6012, + (q31_t)0x21009c0c, (q31_t)0x8453e2cf, (q31_t)0x20e852f6, (q31_t)0x844d6a50, (q31_t)0x20d0089c, (q31_t)0x8446f695, (q31_t)0x20b7bcfe, (q31_t)0x844087a0, + (q31_t)0x209f701c, (q31_t)0x843a1d70, (q31_t)0x208721f9, (q31_t)0x8433b806, (q31_t)0x206ed295, (q31_t)0x842d5762, (q31_t)0x205681f1, (q31_t)0x8426fb84, + (q31_t)0x203e300d, (q31_t)0x8420a46c, (q31_t)0x2025dcec, (q31_t)0x841a521a, (q31_t)0x200d888d, (q31_t)0x84140490, (q31_t)0x1ff532f2, (q31_t)0x840dbbcc, + (q31_t)0x1fdcdc1b, (q31_t)0x840777d0, (q31_t)0x1fc4840a, (q31_t)0x8401389b, (q31_t)0x1fac2abf, (q31_t)0x83fafe2e, (q31_t)0x1f93d03c, (q31_t)0x83f4c889, + (q31_t)0x1f7b7481, (q31_t)0x83ee97ad, (q31_t)0x1f63178f, (q31_t)0x83e86b99, (q31_t)0x1f4ab968, (q31_t)0x83e2444d, (q31_t)0x1f325a0b, (q31_t)0x83dc21cb, + (q31_t)0x1f19f97b, (q31_t)0x83d60412, (q31_t)0x1f0197b8, (q31_t)0x83cfeb22, (q31_t)0x1ee934c3, (q31_t)0x83c9d6fc, (q31_t)0x1ed0d09d, (q31_t)0x83c3c7a0, + (q31_t)0x1eb86b46, (q31_t)0x83bdbd0e, (q31_t)0x1ea004c1, (q31_t)0x83b7b746, (q31_t)0x1e879d0d, (q31_t)0x83b1b649, (q31_t)0x1e6f342c, (q31_t)0x83abba17, + (q31_t)0x1e56ca1e, (q31_t)0x83a5c2b0, (q31_t)0x1e3e5ee5, (q31_t)0x839fd014, (q31_t)0x1e25f282, (q31_t)0x8399e244, (q31_t)0x1e0d84f5, (q31_t)0x8393f940, + (q31_t)0x1df5163f, (q31_t)0x838e1507, (q31_t)0x1ddca662, (q31_t)0x8388359b, (q31_t)0x1dc4355e, (q31_t)0x83825afb, (q31_t)0x1dabc334, (q31_t)0x837c8528, + (q31_t)0x1d934fe5, (q31_t)0x8376b422, (q31_t)0x1d7adb73, (q31_t)0x8370e7e9, (q31_t)0x1d6265dd, (q31_t)0x836b207d, (q31_t)0x1d49ef26, (q31_t)0x83655ddf, + (q31_t)0x1d31774d, (q31_t)0x835fa00f, (q31_t)0x1d18fe54, (q31_t)0x8359e70d, (q31_t)0x1d00843d, (q31_t)0x835432d8, (q31_t)0x1ce80906, (q31_t)0x834e8373, + (q31_t)0x1ccf8cb3, (q31_t)0x8348d8dc, (q31_t)0x1cb70f43, (q31_t)0x83433314, (q31_t)0x1c9e90b8, (q31_t)0x833d921b, (q31_t)0x1c861113, (q31_t)0x8337f5f1, + (q31_t)0x1c6d9053, (q31_t)0x83325e97, (q31_t)0x1c550e7c, (q31_t)0x832ccc0d, (q31_t)0x1c3c8b8c, (q31_t)0x83273e52, (q31_t)0x1c240786, (q31_t)0x8321b568, + (q31_t)0x1c0b826a, (q31_t)0x831c314e, (q31_t)0x1bf2fc3a, (q31_t)0x8316b205, (q31_t)0x1bda74f6, (q31_t)0x8311378d, (q31_t)0x1bc1ec9e, (q31_t)0x830bc1e6, + (q31_t)0x1ba96335, (q31_t)0x83065110, (q31_t)0x1b90d8bb, (q31_t)0x8300e50b, (q31_t)0x1b784d30, (q31_t)0x82fb7dd8, (q31_t)0x1b5fc097, (q31_t)0x82f61b77, + (q31_t)0x1b4732ef, (q31_t)0x82f0bde8, (q31_t)0x1b2ea43a, (q31_t)0x82eb652b, (q31_t)0x1b161479, (q31_t)0x82e61141, (q31_t)0x1afd83ad, (q31_t)0x82e0c22a, + (q31_t)0x1ae4f1d6, (q31_t)0x82db77e5, (q31_t)0x1acc5ef6, (q31_t)0x82d63274, (q31_t)0x1ab3cb0d, (q31_t)0x82d0f1d5, (q31_t)0x1a9b361d, (q31_t)0x82cbb60b, + (q31_t)0x1a82a026, (q31_t)0x82c67f14, (q31_t)0x1a6a0929, (q31_t)0x82c14cf1, (q31_t)0x1a517128, (q31_t)0x82bc1fa2, (q31_t)0x1a38d823, (q31_t)0x82b6f727, + (q31_t)0x1a203e1b, (q31_t)0x82b1d381, (q31_t)0x1a07a311, (q31_t)0x82acb4b0, (q31_t)0x19ef0707, (q31_t)0x82a79ab3, (q31_t)0x19d669fc, (q31_t)0x82a2858c, + (q31_t)0x19bdcbf3, (q31_t)0x829d753a, (q31_t)0x19a52ceb, (q31_t)0x829869be, (q31_t)0x198c8ce7, (q31_t)0x82936317, (q31_t)0x1973ebe6, (q31_t)0x828e6146, + (q31_t)0x195b49ea, (q31_t)0x8289644b, (q31_t)0x1942a6f3, (q31_t)0x82846c26, (q31_t)0x192a0304, (q31_t)0x827f78d8, (q31_t)0x19115e1c, (q31_t)0x827a8a61, + (q31_t)0x18f8b83c, (q31_t)0x8275a0c0, (q31_t)0x18e01167, (q31_t)0x8270bbf7, (q31_t)0x18c7699b, (q31_t)0x826bdc04, (q31_t)0x18aec0db, (q31_t)0x826700e9, + (q31_t)0x18961728, (q31_t)0x82622aa6, (q31_t)0x187d6c82, (q31_t)0x825d593a, (q31_t)0x1864c0ea, (q31_t)0x82588ca7, (q31_t)0x184c1461, (q31_t)0x8253c4eb, + (q31_t)0x183366e9, (q31_t)0x824f0208, (q31_t)0x181ab881, (q31_t)0x824a43fe, (q31_t)0x1802092c, (q31_t)0x82458acc, (q31_t)0x17e958ea, (q31_t)0x8240d673, + (q31_t)0x17d0a7bc, (q31_t)0x823c26f3, (q31_t)0x17b7f5a3, (q31_t)0x82377c4c, (q31_t)0x179f429f, (q31_t)0x8232d67f, (q31_t)0x17868eb3, (q31_t)0x822e358b, + (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x17552422, (q31_t)0x82250232, (q31_t)0x173c6d80, (q31_t)0x82206fcc, (q31_t)0x1723b5f9, (q31_t)0x821be240, + (q31_t)0x170afd8d, (q31_t)0x82175990, (q31_t)0x16f2443e, (q31_t)0x8212d5b9, (q31_t)0x16d98a0c, (q31_t)0x820e56be, (q31_t)0x16c0cef9, (q31_t)0x8209dc9e, + (q31_t)0x16a81305, (q31_t)0x82056758, (q31_t)0x168f5632, (q31_t)0x8200f6ef, (q31_t)0x1676987f, (q31_t)0x81fc8b60, (q31_t)0x165dd9f0, (q31_t)0x81f824ae, + (q31_t)0x16451a83, (q31_t)0x81f3c2d7, (q31_t)0x162c5a3b, (q31_t)0x81ef65dc, (q31_t)0x16139918, (q31_t)0x81eb0dbe, (q31_t)0x15fad71b, (q31_t)0x81e6ba7c, + (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x15c95097, (q31_t)0x81de228d, (q31_t)0x15b08c12, (q31_t)0x81d9dde1, (q31_t)0x1597c6b7, (q31_t)0x81d59e13, + (q31_t)0x157f0086, (q31_t)0x81d16321, (q31_t)0x15663982, (q31_t)0x81cd2d0c, (q31_t)0x154d71aa, (q31_t)0x81c8fbd6, (q31_t)0x1534a901, (q31_t)0x81c4cf7d, + (q31_t)0x151bdf86, (q31_t)0x81c0a801, (q31_t)0x1503153a, (q31_t)0x81bc8564, (q31_t)0x14ea4a1f, (q31_t)0x81b867a5, (q31_t)0x14d17e36, (q31_t)0x81b44ec4, + (q31_t)0x14b8b17f, (q31_t)0x81b03ac2, (q31_t)0x149fe3fc, (q31_t)0x81ac2b9e, (q31_t)0x148715ae, (q31_t)0x81a82159, (q31_t)0x146e4694, (q31_t)0x81a41bf4, + (q31_t)0x145576b1, (q31_t)0x81a01b6d, (q31_t)0x143ca605, (q31_t)0x819c1fc5, (q31_t)0x1423d492, (q31_t)0x819828fd, (q31_t)0x140b0258, (q31_t)0x81943715, + (q31_t)0x13f22f58, (q31_t)0x81904a0c, (q31_t)0x13d95b93, (q31_t)0x818c61e3, (q31_t)0x13c0870a, (q31_t)0x81887e9a, (q31_t)0x13a7b1bf, (q31_t)0x8184a032, + (q31_t)0x138edbb1, (q31_t)0x8180c6a9, (q31_t)0x137604e2, (q31_t)0x817cf201, (q31_t)0x135d2d53, (q31_t)0x8179223a, (q31_t)0x13445505, (q31_t)0x81755754, + (q31_t)0x132b7bf9, (q31_t)0x8171914e, (q31_t)0x1312a230, (q31_t)0x816dd02a, (q31_t)0x12f9c7aa, (q31_t)0x816a13e6, (q31_t)0x12e0ec6a, (q31_t)0x81665c84, + (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x12af33ba, (q31_t)0x815efc65, (q31_t)0x1296564d, (q31_t)0x815b53a8, (q31_t)0x127d7829, (q31_t)0x8157afcd, + (q31_t)0x1264994e, (q31_t)0x815410d4, (q31_t)0x124bb9be, (q31_t)0x815076bd, (q31_t)0x1232d979, (q31_t)0x814ce188, (q31_t)0x1219f880, (q31_t)0x81495136, + (q31_t)0x120116d5, (q31_t)0x8145c5c7, (q31_t)0x11e83478, (q31_t)0x81423f3a, (q31_t)0x11cf516a, (q31_t)0x813ebd90, (q31_t)0x11b66dad, (q31_t)0x813b40ca, + (q31_t)0x119d8941, (q31_t)0x8137c8e6, (q31_t)0x1184a427, (q31_t)0x813455e6, (q31_t)0x116bbe60, (q31_t)0x8130e7c9, (q31_t)0x1152d7ed, (q31_t)0x812d7e8f, + (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0x11210907, (q31_t)0x8126bac8, (q31_t)0x11082096, (q31_t)0x8123603a, (q31_t)0x10ef377d, (q31_t)0x81200a90, + (q31_t)0x10d64dbd, (q31_t)0x811cb9ca, (q31_t)0x10bd6356, (q31_t)0x81196de9, (q31_t)0x10a4784b, (q31_t)0x811626ec, (q31_t)0x108b8c9b, (q31_t)0x8112e4d4, + (q31_t)0x1072a048, (q31_t)0x810fa7a0, (q31_t)0x1059b352, (q31_t)0x810c6f52, (q31_t)0x1040c5bb, (q31_t)0x81093be8, (q31_t)0x1027d784, (q31_t)0x81060d63, + (q31_t)0x100ee8ad, (q31_t)0x8102e3c4, (q31_t)0xff5f938, (q31_t)0x80ffbf0a, (q31_t)0xfdd0926, (q31_t)0x80fc9f35, (q31_t)0xfc41876, (q31_t)0x80f98446, + (q31_t)0xfab272b, (q31_t)0x80f66e3c, (q31_t)0xf923546, (q31_t)0x80f35d19, (q31_t)0xf7942c7, (q31_t)0x80f050db, (q31_t)0xf604faf, (q31_t)0x80ed4984, + (q31_t)0xf475bff, (q31_t)0x80ea4712, (q31_t)0xf2e67b8, (q31_t)0x80e74987, (q31_t)0xf1572dc, (q31_t)0x80e450e2, (q31_t)0xefc7d6b, (q31_t)0x80e15d24, + (q31_t)0xee38766, (q31_t)0x80de6e4c, (q31_t)0xeca90ce, (q31_t)0x80db845b, (q31_t)0xeb199a4, (q31_t)0x80d89f51, (q31_t)0xe98a1e9, (q31_t)0x80d5bf2e, + (q31_t)0xe7fa99e, (q31_t)0x80d2e3f2, (q31_t)0xe66b0c3, (q31_t)0x80d00d9d, (q31_t)0xe4db75b, (q31_t)0x80cd3c2f, (q31_t)0xe34bd66, (q31_t)0x80ca6fa9, + (q31_t)0xe1bc2e4, (q31_t)0x80c7a80a, (q31_t)0xe02c7d7, (q31_t)0x80c4e553, (q31_t)0xde9cc40, (q31_t)0x80c22784, (q31_t)0xdd0d01f, (q31_t)0x80bf6e9c, + (q31_t)0xdb7d376, (q31_t)0x80bcba9d, (q31_t)0xd9ed646, (q31_t)0x80ba0b85, (q31_t)0xd85d88f, (q31_t)0x80b76156, (q31_t)0xd6cda53, (q31_t)0x80b4bc0e, + (q31_t)0xd53db92, (q31_t)0x80b21baf, (q31_t)0xd3adc4e, (q31_t)0x80af8039, (q31_t)0xd21dc87, (q31_t)0x80ace9ab, (q31_t)0xd08dc3f, (q31_t)0x80aa5806, + (q31_t)0xcefdb76, (q31_t)0x80a7cb49, (q31_t)0xcd6da2d, (q31_t)0x80a54376, (q31_t)0xcbdd865, (q31_t)0x80a2c08b, (q31_t)0xca4d620, (q31_t)0x80a04289, + (q31_t)0xc8bd35e, (q31_t)0x809dc971, (q31_t)0xc72d020, (q31_t)0x809b5541, (q31_t)0xc59cc68, (q31_t)0x8098e5fb, (q31_t)0xc40c835, (q31_t)0x80967b9f, + (q31_t)0xc27c389, (q31_t)0x8094162c, (q31_t)0xc0ebe66, (q31_t)0x8091b5a2, (q31_t)0xbf5b8cb, (q31_t)0x808f5a02, (q31_t)0xbdcb2bb, (q31_t)0x808d034c, + (q31_t)0xbc3ac35, (q31_t)0x808ab180, (q31_t)0xbaaa53b, (q31_t)0x8088649e, (q31_t)0xb919dcf, (q31_t)0x80861ca6, (q31_t)0xb7895f0, (q31_t)0x8083d998, + (q31_t)0xb5f8d9f, (q31_t)0x80819b74, (q31_t)0xb4684df, (q31_t)0x807f623b, (q31_t)0xb2d7baf, (q31_t)0x807d2dec, (q31_t)0xb147211, (q31_t)0x807afe87, + (q31_t)0xafb6805, (q31_t)0x8078d40d, (q31_t)0xae25d8d, (q31_t)0x8076ae7e, (q31_t)0xac952aa, (q31_t)0x80748dd9, (q31_t)0xab0475c, (q31_t)0x8072721f, + (q31_t)0xa973ba5, (q31_t)0x80705b50, (q31_t)0xa7e2f85, (q31_t)0x806e496c, (q31_t)0xa6522fe, (q31_t)0x806c3c74, (q31_t)0xa4c1610, (q31_t)0x806a3466, + (q31_t)0xa3308bd, (q31_t)0x80683143, (q31_t)0xa19fb04, (q31_t)0x8066330c, (q31_t)0xa00ece8, (q31_t)0x806439c0, (q31_t)0x9e7de6a, (q31_t)0x80624560, + (q31_t)0x9cecf89, (q31_t)0x806055eb, (q31_t)0x9b5c048, (q31_t)0x805e6b62, (q31_t)0x99cb0a7, (q31_t)0x805c85c4, (q31_t)0x983a0a7, (q31_t)0x805aa512, + (q31_t)0x96a9049, (q31_t)0x8058c94c, (q31_t)0x9517f8f, (q31_t)0x8056f272, (q31_t)0x9386e78, (q31_t)0x80552084, (q31_t)0x91f5d06, (q31_t)0x80535381, + (q31_t)0x9064b3a, (q31_t)0x80518b6b, (q31_t)0x8ed3916, (q31_t)0x804fc841, (q31_t)0x8d42699, (q31_t)0x804e0a04, (q31_t)0x8bb13c5, (q31_t)0x804c50b2, + (q31_t)0x8a2009a, (q31_t)0x804a9c4d, (q31_t)0x888ed1b, (q31_t)0x8048ecd5, (q31_t)0x86fd947, (q31_t)0x80474248, (q31_t)0x856c520, (q31_t)0x80459ca9, + (q31_t)0x83db0a7, (q31_t)0x8043fbf6, (q31_t)0x8249bdd, (q31_t)0x80426030, (q31_t)0x80b86c2, (q31_t)0x8040c956, (q31_t)0x7f27157, (q31_t)0x803f376a, + (q31_t)0x7d95b9e, (q31_t)0x803daa6a, (q31_t)0x7c04598, (q31_t)0x803c2257, (q31_t)0x7a72f45, (q31_t)0x803a9f31, (q31_t)0x78e18a7, (q31_t)0x803920f8, + (q31_t)0x77501be, (q31_t)0x8037a7ac, (q31_t)0x75bea8c, (q31_t)0x8036334e, (q31_t)0x742d311, (q31_t)0x8034c3dd, (q31_t)0x729bb4e, (q31_t)0x80335959, + (q31_t)0x710a345, (q31_t)0x8031f3c2, (q31_t)0x6f78af6, (q31_t)0x80309318, (q31_t)0x6de7262, (q31_t)0x802f375d, (q31_t)0x6c5598a, (q31_t)0x802de08e, + (q31_t)0x6ac406f, (q31_t)0x802c8ead, (q31_t)0x6932713, (q31_t)0x802b41ba, (q31_t)0x67a0d76, (q31_t)0x8029f9b4, (q31_t)0x660f398, (q31_t)0x8028b69c, + (q31_t)0x647d97c, (q31_t)0x80277872, (q31_t)0x62ebf22, (q31_t)0x80263f36, (q31_t)0x615a48b, (q31_t)0x80250ae7, (q31_t)0x5fc89b8, (q31_t)0x8023db86, + (q31_t)0x5e36ea9, (q31_t)0x8022b114, (q31_t)0x5ca5361, (q31_t)0x80218b8f, (q31_t)0x5b137df, (q31_t)0x80206af8, (q31_t)0x5981c26, (q31_t)0x801f4f4f, + (q31_t)0x57f0035, (q31_t)0x801e3895, (q31_t)0x565e40d, (q31_t)0x801d26c8, (q31_t)0x54cc7b1, (q31_t)0x801c19ea, (q31_t)0x533ab20, (q31_t)0x801b11fa, + (q31_t)0x51a8e5c, (q31_t)0x801a0ef8, (q31_t)0x5017165, (q31_t)0x801910e4, (q31_t)0x4e8543e, (q31_t)0x801817bf, (q31_t)0x4cf36e5, (q31_t)0x80172388, + (q31_t)0x4b6195d, (q31_t)0x80163440, (q31_t)0x49cfba7, (q31_t)0x801549e6, (q31_t)0x483ddc3, (q31_t)0x8014647b, (q31_t)0x46abfb3, (q31_t)0x801383fe, + (q31_t)0x451a177, (q31_t)0x8012a86f, (q31_t)0x4388310, (q31_t)0x8011d1d0, (q31_t)0x41f6480, (q31_t)0x8011001f, (q31_t)0x40645c7, (q31_t)0x8010335c, + (q31_t)0x3ed26e6, (q31_t)0x800f6b88, (q31_t)0x3d407df, (q31_t)0x800ea8a3, (q31_t)0x3bae8b2, (q31_t)0x800deaad, (q31_t)0x3a1c960, (q31_t)0x800d31a5, + (q31_t)0x388a9ea, (q31_t)0x800c7d8c, (q31_t)0x36f8a51, (q31_t)0x800bce63, (q31_t)0x3566a96, (q31_t)0x800b2427, (q31_t)0x33d4abb, (q31_t)0x800a7edb, + (q31_t)0x3242abf, (q31_t)0x8009de7e, (q31_t)0x30b0aa4, (q31_t)0x80094310, (q31_t)0x2f1ea6c, (q31_t)0x8008ac90, (q31_t)0x2d8ca16, (q31_t)0x80081b00, + (q31_t)0x2bfa9a4, (q31_t)0x80078e5e, (q31_t)0x2a68917, (q31_t)0x800706ac, (q31_t)0x28d6870, (q31_t)0x800683e8, (q31_t)0x27447b0, (q31_t)0x80060614, + (q31_t)0x25b26d7, (q31_t)0x80058d2f, (q31_t)0x24205e8, (q31_t)0x80051939, (q31_t)0x228e4e2, (q31_t)0x8004aa32, (q31_t)0x20fc3c6, (q31_t)0x8004401a, + (q31_t)0x1f6a297, (q31_t)0x8003daf1, (q31_t)0x1dd8154, (q31_t)0x80037ab7, (q31_t)0x1c45ffe, (q31_t)0x80031f6d, (q31_t)0x1ab3e97, (q31_t)0x8002c912, + (q31_t)0x1921d20, (q31_t)0x800277a6, (q31_t)0x178fb99, (q31_t)0x80022b29, (q31_t)0x15fda03, (q31_t)0x8001e39b, (q31_t)0x146b860, (q31_t)0x8001a0fd, + (q31_t)0x12d96b1, (q31_t)0x8001634e, (q31_t)0x11474f6, (q31_t)0x80012a8e, (q31_t)0x0fb5330, (q31_t)0x8000f6bd, (q31_t)0xe23160, (q31_t)0x8000c7dc, + (q31_t)0x0c90f88, (q31_t)0x80009dea, (q31_t)0x0afeda8, (q31_t)0x800078e7, (q31_t)0x096cbc1, (q31_t)0x800058d4, (q31_t)0x7da9d4, (q31_t)0x80003daf, + (q31_t)0x06487e3, (q31_t)0x8000277a, (q31_t)0x04b65ee, (q31_t)0x80001635, (q31_t)0x03243f5, (q31_t)0x800009df, (q31_t)0x1921fb, (q31_t)0x80000278 +}; + const q31_t cos_factorsQ31_2048[2048] = { + (q31_t)0x7fffff62, (q31_t)0x7ffffa73, (q31_t)0x7ffff094, (q31_t)0x7fffe1c6, (q31_t)0x7fffce09, (q31_t)0x7fffb55c, + (q31_t)0x7fff97c1, (q31_t)0x7fff7536, + (q31_t)0x7fff4dbb, (q31_t)0x7fff2151, (q31_t)0x7ffeeff8, (q31_t)0x7ffeb9b0, (q31_t)0x7ffe7e79, (q31_t)0x7ffe3e52, + (q31_t)0x7ffdf93c, (q31_t)0x7ffdaf37, + (q31_t)0x7ffd6042, (q31_t)0x7ffd0c5f, (q31_t)0x7ffcb38c, (q31_t)0x7ffc55ca, (q31_t)0x7ffbf319, (q31_t)0x7ffb8b78, + (q31_t)0x7ffb1ee9, (q31_t)0x7ffaad6a, + (q31_t)0x7ffa36fc, (q31_t)0x7ff9bba0, (q31_t)0x7ff93b54, (q31_t)0x7ff8b619, (q31_t)0x7ff82bef, (q31_t)0x7ff79cd6, + (q31_t)0x7ff708ce, (q31_t)0x7ff66fd7, + (q31_t)0x7ff5d1f1, (q31_t)0x7ff52f1d, (q31_t)0x7ff48759, (q31_t)0x7ff3daa6, (q31_t)0x7ff32905, (q31_t)0x7ff27275, + (q31_t)0x7ff1b6f6, (q31_t)0x7ff0f688, + (q31_t)0x7ff0312c, (q31_t)0x7fef66e1, (q31_t)0x7fee97a7, (q31_t)0x7fedc37e, (q31_t)0x7fecea67, (q31_t)0x7fec0c62, + (q31_t)0x7feb296d, (q31_t)0x7fea418b, + (q31_t)0x7fe954ba, (q31_t)0x7fe862fa, (q31_t)0x7fe76c4c, (q31_t)0x7fe670b0, (q31_t)0x7fe57025, (q31_t)0x7fe46aac, + (q31_t)0x7fe36045, (q31_t)0x7fe250ef, + (q31_t)0x7fe13cac, (q31_t)0x7fe0237a, (q31_t)0x7fdf055a, (q31_t)0x7fdde24d, (q31_t)0x7fdcba51, (q31_t)0x7fdb8d67, + (q31_t)0x7fda5b8f, (q31_t)0x7fd924ca, + (q31_t)0x7fd7e917, (q31_t)0x7fd6a875, (q31_t)0x7fd562e7, (q31_t)0x7fd4186a, (q31_t)0x7fd2c900, (q31_t)0x7fd174a8, + (q31_t)0x7fd01b63, (q31_t)0x7fcebd31, + (q31_t)0x7fcd5a11, (q31_t)0x7fcbf203, (q31_t)0x7fca8508, (q31_t)0x7fc91320, (q31_t)0x7fc79c4b, (q31_t)0x7fc62089, + (q31_t)0x7fc49fda, (q31_t)0x7fc31a3d, + (q31_t)0x7fc18fb4, (q31_t)0x7fc0003e, (q31_t)0x7fbe6bdb, (q31_t)0x7fbcd28b, (q31_t)0x7fbb344e, (q31_t)0x7fb99125, + (q31_t)0x7fb7e90f, (q31_t)0x7fb63c0d, + (q31_t)0x7fb48a1e, (q31_t)0x7fb2d343, (q31_t)0x7fb1177b, (q31_t)0x7faf56c7, (q31_t)0x7fad9127, (q31_t)0x7fabc69b, + (q31_t)0x7fa9f723, (q31_t)0x7fa822bf, + (q31_t)0x7fa6496e, (q31_t)0x7fa46b32, (q31_t)0x7fa2880b, (q31_t)0x7fa09ff7, (q31_t)0x7f9eb2f8, (q31_t)0x7f9cc10d, + (q31_t)0x7f9aca37, (q31_t)0x7f98ce76, + (q31_t)0x7f96cdc9, (q31_t)0x7f94c831, (q31_t)0x7f92bdad, (q31_t)0x7f90ae3f, (q31_t)0x7f8e99e6, (q31_t)0x7f8c80a1, + (q31_t)0x7f8a6272, (q31_t)0x7f883f58, + (q31_t)0x7f861753, (q31_t)0x7f83ea64, (q31_t)0x7f81b88a, (q31_t)0x7f7f81c6, (q31_t)0x7f7d4617, (q31_t)0x7f7b057e, + (q31_t)0x7f78bffb, (q31_t)0x7f76758e, + (q31_t)0x7f742637, (q31_t)0x7f71d1f6, (q31_t)0x7f6f78cb, (q31_t)0x7f6d1ab6, (q31_t)0x7f6ab7b8, (q31_t)0x7f684fd0, + (q31_t)0x7f65e2ff, (q31_t)0x7f637144, + (q31_t)0x7f60faa0, (q31_t)0x7f5e7f13, (q31_t)0x7f5bfe9d, (q31_t)0x7f59793e, (q31_t)0x7f56eef5, (q31_t)0x7f545fc5, + (q31_t)0x7f51cbab, (q31_t)0x7f4f32a9, + (q31_t)0x7f4c94be, (q31_t)0x7f49f1eb, (q31_t)0x7f474a30, (q31_t)0x7f449d8c, (q31_t)0x7f41ec01, (q31_t)0x7f3f358d, + (q31_t)0x7f3c7a31, (q31_t)0x7f39b9ee, + (q31_t)0x7f36f4c3, (q31_t)0x7f342ab1, (q31_t)0x7f315bb7, (q31_t)0x7f2e87d6, (q31_t)0x7f2baf0d, (q31_t)0x7f28d15d, + (q31_t)0x7f25eec7, (q31_t)0x7f230749, + (q31_t)0x7f201ae5, (q31_t)0x7f1d299a, (q31_t)0x7f1a3368, (q31_t)0x7f173850, (q31_t)0x7f143852, (q31_t)0x7f11336d, + (q31_t)0x7f0e29a3, (q31_t)0x7f0b1af2, + (q31_t)0x7f08075c, (q31_t)0x7f04eedf, (q31_t)0x7f01d17d, (q31_t)0x7efeaf36, (q31_t)0x7efb8809, (q31_t)0x7ef85bf7, + (q31_t)0x7ef52b00, (q31_t)0x7ef1f524, + (q31_t)0x7eeeba62, (q31_t)0x7eeb7abc, (q31_t)0x7ee83632, (q31_t)0x7ee4ecc3, (q31_t)0x7ee19e6f, (q31_t)0x7ede4b38, + (q31_t)0x7edaf31c, (q31_t)0x7ed7961c, + (q31_t)0x7ed43438, (q31_t)0x7ed0cd70, (q31_t)0x7ecd61c5, (q31_t)0x7ec9f137, (q31_t)0x7ec67bc5, (q31_t)0x7ec3016f, + (q31_t)0x7ebf8237, (q31_t)0x7ebbfe1c, + (q31_t)0x7eb8751e, (q31_t)0x7eb4e73d, (q31_t)0x7eb1547a, (q31_t)0x7eadbcd4, (q31_t)0x7eaa204c, (q31_t)0x7ea67ee2, + (q31_t)0x7ea2d896, (q31_t)0x7e9f2d68, + (q31_t)0x7e9b7d58, (q31_t)0x7e97c867, (q31_t)0x7e940e94, (q31_t)0x7e904fe0, (q31_t)0x7e8c8c4b, (q31_t)0x7e88c3d5, + (q31_t)0x7e84f67e, (q31_t)0x7e812447, + (q31_t)0x7e7d4d2f, (q31_t)0x7e797136, (q31_t)0x7e75905d, (q31_t)0x7e71aaa4, (q31_t)0x7e6dc00c, (q31_t)0x7e69d093, + (q31_t)0x7e65dc3b, (q31_t)0x7e61e303, + (q31_t)0x7e5de4ec, (q31_t)0x7e59e1f5, (q31_t)0x7e55da20, (q31_t)0x7e51cd6c, (q31_t)0x7e4dbbd9, (q31_t)0x7e49a567, + (q31_t)0x7e458a17, (q31_t)0x7e4169e9, + (q31_t)0x7e3d44dd, (q31_t)0x7e391af3, (q31_t)0x7e34ec2b, (q31_t)0x7e30b885, (q31_t)0x7e2c8002, (q31_t)0x7e2842a2, + (q31_t)0x7e240064, (q31_t)0x7e1fb94a, + (q31_t)0x7e1b6d53, (q31_t)0x7e171c7f, (q31_t)0x7e12c6ce, (q31_t)0x7e0e6c42, (q31_t)0x7e0a0cd9, (q31_t)0x7e05a894, + (q31_t)0x7e013f74, (q31_t)0x7dfcd178, + (q31_t)0x7df85ea0, (q31_t)0x7df3e6ee, (q31_t)0x7def6a60, (q31_t)0x7deae8f7, (q31_t)0x7de662b3, (q31_t)0x7de1d795, + (q31_t)0x7ddd479d, (q31_t)0x7dd8b2ca, + (q31_t)0x7dd4191d, (q31_t)0x7dcf7a96, (q31_t)0x7dcad736, (q31_t)0x7dc62efc, (q31_t)0x7dc181e8, (q31_t)0x7dbccffc, + (q31_t)0x7db81936, (q31_t)0x7db35d98, + (q31_t)0x7dae9d21, (q31_t)0x7da9d7d2, (q31_t)0x7da50dab, (q31_t)0x7da03eab, (q31_t)0x7d9b6ad3, (q31_t)0x7d969224, + (q31_t)0x7d91b49e, (q31_t)0x7d8cd240, + (q31_t)0x7d87eb0a, (q31_t)0x7d82fefe, (q31_t)0x7d7e0e1c, (q31_t)0x7d791862, (q31_t)0x7d741dd2, (q31_t)0x7d6f1e6c, + (q31_t)0x7d6a1a31, (q31_t)0x7d65111f, + (q31_t)0x7d600338, (q31_t)0x7d5af07b, (q31_t)0x7d55d8e9, (q31_t)0x7d50bc82, (q31_t)0x7d4b9b46, (q31_t)0x7d467536, + (q31_t)0x7d414a51, (q31_t)0x7d3c1a98, + (q31_t)0x7d36e60b, (q31_t)0x7d31acaa, (q31_t)0x7d2c6e76, (q31_t)0x7d272b6e, (q31_t)0x7d21e393, (q31_t)0x7d1c96e5, + (q31_t)0x7d174564, (q31_t)0x7d11ef11, + (q31_t)0x7d0c93eb, (q31_t)0x7d0733f3, (q31_t)0x7d01cf29, (q31_t)0x7cfc658d, (q31_t)0x7cf6f720, (q31_t)0x7cf183e1, + (q31_t)0x7cec0bd1, (q31_t)0x7ce68ef0, + (q31_t)0x7ce10d3f, (q31_t)0x7cdb86bd, (q31_t)0x7cd5fb6a, (q31_t)0x7cd06b48, (q31_t)0x7ccad656, (q31_t)0x7cc53c94, + (q31_t)0x7cbf9e03, (q31_t)0x7cb9faa2, + (q31_t)0x7cb45272, (q31_t)0x7caea574, (q31_t)0x7ca8f3a7, (q31_t)0x7ca33d0c, (q31_t)0x7c9d81a3, (q31_t)0x7c97c16b, + (q31_t)0x7c91fc66, (q31_t)0x7c8c3294, + (q31_t)0x7c8663f4, (q31_t)0x7c809088, (q31_t)0x7c7ab84e, (q31_t)0x7c74db48, (q31_t)0x7c6ef976, (q31_t)0x7c6912d7, + (q31_t)0x7c63276d, (q31_t)0x7c5d3737, + (q31_t)0x7c574236, (q31_t)0x7c514869, (q31_t)0x7c4b49d2, (q31_t)0x7c45466f, (q31_t)0x7c3f3e42, (q31_t)0x7c39314b, + (q31_t)0x7c331f8a, (q31_t)0x7c2d08ff, + (q31_t)0x7c26edab, (q31_t)0x7c20cd8d, (q31_t)0x7c1aa8a6, (q31_t)0x7c147ef6, (q31_t)0x7c0e507e, (q31_t)0x7c081d3d, + (q31_t)0x7c01e534, (q31_t)0x7bfba863, + (q31_t)0x7bf566cb, (q31_t)0x7bef206b, (q31_t)0x7be8d544, (q31_t)0x7be28556, (q31_t)0x7bdc30a1, (q31_t)0x7bd5d726, + (q31_t)0x7bcf78e5, (q31_t)0x7bc915dd, + (q31_t)0x7bc2ae10, (q31_t)0x7bbc417e, (q31_t)0x7bb5d026, (q31_t)0x7baf5a09, (q31_t)0x7ba8df28, (q31_t)0x7ba25f82, + (q31_t)0x7b9bdb18, (q31_t)0x7b9551ea, + (q31_t)0x7b8ec3f8, (q31_t)0x7b883143, (q31_t)0x7b8199ca, (q31_t)0x7b7afd8f, (q31_t)0x7b745c91, (q31_t)0x7b6db6d0, + (q31_t)0x7b670c4d, (q31_t)0x7b605d09, + (q31_t)0x7b59a902, (q31_t)0x7b52f03a, (q31_t)0x7b4c32b1, (q31_t)0x7b457068, (q31_t)0x7b3ea95d, (q31_t)0x7b37dd92, + (q31_t)0x7b310d07, (q31_t)0x7b2a37bc, + (q31_t)0x7b235db2, (q31_t)0x7b1c7ee8, (q31_t)0x7b159b5f, (q31_t)0x7b0eb318, (q31_t)0x7b07c612, (q31_t)0x7b00d44d, + (q31_t)0x7af9ddcb, (q31_t)0x7af2e28b, + (q31_t)0x7aebe28d, (q31_t)0x7ae4ddd2, (q31_t)0x7addd45b, (q31_t)0x7ad6c626, (q31_t)0x7acfb336, (q31_t)0x7ac89b89, + (q31_t)0x7ac17f20, (q31_t)0x7aba5dfc, + (q31_t)0x7ab3381d, (q31_t)0x7aac0d82, (q31_t)0x7aa4de2d, (q31_t)0x7a9daa1d, (q31_t)0x7a967153, (q31_t)0x7a8f33d0, + (q31_t)0x7a87f192, (q31_t)0x7a80aa9c, + (q31_t)0x7a795eec, (q31_t)0x7a720e84, (q31_t)0x7a6ab963, (q31_t)0x7a635f8a, (q31_t)0x7a5c00f9, (q31_t)0x7a549db0, + (q31_t)0x7a4d35b0, (q31_t)0x7a45c8f9, + (q31_t)0x7a3e578b, (q31_t)0x7a36e166, (q31_t)0x7a2f668c, (q31_t)0x7a27e6fb, (q31_t)0x7a2062b5, (q31_t)0x7a18d9b9, + (q31_t)0x7a114c09, (q31_t)0x7a09b9a4, + (q31_t)0x7a02228a, (q31_t)0x79fa86bc, (q31_t)0x79f2e63a, (q31_t)0x79eb4105, (q31_t)0x79e3971c, (q31_t)0x79dbe880, + (q31_t)0x79d43532, (q31_t)0x79cc7d31, + (q31_t)0x79c4c07e, (q31_t)0x79bcff19, (q31_t)0x79b53903, (q31_t)0x79ad6e3c, (q31_t)0x79a59ec3, (q31_t)0x799dca9a, + (q31_t)0x7995f1c1, (q31_t)0x798e1438, + (q31_t)0x798631ff, (q31_t)0x797e4b16, (q31_t)0x79765f7f, (q31_t)0x796e6f39, (q31_t)0x79667a44, (q31_t)0x795e80a1, + (q31_t)0x79568250, (q31_t)0x794e7f52, + (q31_t)0x794677a6, (q31_t)0x793e6b4e, (q31_t)0x79365a49, (q31_t)0x792e4497, (q31_t)0x79262a3a, (q31_t)0x791e0b31, + (q31_t)0x7915e77c, (q31_t)0x790dbf1d, + (q31_t)0x79059212, (q31_t)0x78fd605d, (q31_t)0x78f529fe, (q31_t)0x78eceef6, (q31_t)0x78e4af44, (q31_t)0x78dc6ae8, + (q31_t)0x78d421e4, (q31_t)0x78cbd437, + (q31_t)0x78c381e2, (q31_t)0x78bb2ae5, (q31_t)0x78b2cf41, (q31_t)0x78aa6ef5, (q31_t)0x78a20a03, (q31_t)0x7899a06a, + (q31_t)0x7891322a, (q31_t)0x7888bf45, + (q31_t)0x788047ba, (q31_t)0x7877cb89, (q31_t)0x786f4ab4, (q31_t)0x7866c53a, (q31_t)0x785e3b1c, (q31_t)0x7855ac5a, + (q31_t)0x784d18f4, (q31_t)0x784480ea, + (q31_t)0x783be43e, (q31_t)0x783342ef, (q31_t)0x782a9cfe, (q31_t)0x7821f26b, (q31_t)0x78194336, (q31_t)0x78108f60, + (q31_t)0x7807d6e9, (q31_t)0x77ff19d1, + (q31_t)0x77f65819, (q31_t)0x77ed91c0, (q31_t)0x77e4c6c9, (q31_t)0x77dbf732, (q31_t)0x77d322fc, (q31_t)0x77ca4a27, + (q31_t)0x77c16cb4, (q31_t)0x77b88aa3, + (q31_t)0x77afa3f5, (q31_t)0x77a6b8a9, (q31_t)0x779dc8c0, (q31_t)0x7794d43b, (q31_t)0x778bdb19, (q31_t)0x7782dd5c, + (q31_t)0x7779db03, (q31_t)0x7770d40f, + (q31_t)0x7767c880, (q31_t)0x775eb857, (q31_t)0x7755a394, (q31_t)0x774c8a36, (q31_t)0x77436c40, (q31_t)0x773a49b0, + (q31_t)0x77312287, (q31_t)0x7727f6c6, + (q31_t)0x771ec66e, (q31_t)0x7715917d, (q31_t)0x770c57f5, (q31_t)0x770319d6, (q31_t)0x76f9d721, (q31_t)0x76f08fd5, + (q31_t)0x76e743f4, (q31_t)0x76ddf37c, + (q31_t)0x76d49e70, (q31_t)0x76cb44cf, (q31_t)0x76c1e699, (q31_t)0x76b883d0, (q31_t)0x76af1c72, (q31_t)0x76a5b082, + (q31_t)0x769c3ffe, (q31_t)0x7692cae8, + (q31_t)0x7689513f, (q31_t)0x767fd304, (q31_t)0x76765038, (q31_t)0x766cc8db, (q31_t)0x76633ced, (q31_t)0x7659ac6f, + (q31_t)0x76501760, (q31_t)0x76467dc2, + (q31_t)0x763cdf94, (q31_t)0x76333cd8, (q31_t)0x7629958c, (q31_t)0x761fe9b3, (q31_t)0x7616394c, (q31_t)0x760c8457, + (q31_t)0x7602cad5, (q31_t)0x75f90cc7, + (q31_t)0x75ef4a2c, (q31_t)0x75e58305, (q31_t)0x75dbb753, (q31_t)0x75d1e715, (q31_t)0x75c8124d, (q31_t)0x75be38fa, + (q31_t)0x75b45b1d, (q31_t)0x75aa78b6, + (q31_t)0x75a091c6, (q31_t)0x7596a64d, (q31_t)0x758cb64c, (q31_t)0x7582c1c2, (q31_t)0x7578c8b0, (q31_t)0x756ecb18, + (q31_t)0x7564c8f8, (q31_t)0x755ac251, + (q31_t)0x7550b725, (q31_t)0x7546a772, (q31_t)0x753c933a, (q31_t)0x75327a7d, (q31_t)0x75285d3b, (q31_t)0x751e3b75, + (q31_t)0x7514152b, (q31_t)0x7509ea5d, + (q31_t)0x74ffbb0d, (q31_t)0x74f58739, (q31_t)0x74eb4ee3, (q31_t)0x74e1120c, (q31_t)0x74d6d0b2, (q31_t)0x74cc8ad8, + (q31_t)0x74c2407d, (q31_t)0x74b7f1a1, + (q31_t)0x74ad9e46, (q31_t)0x74a3466b, (q31_t)0x7498ea11, (q31_t)0x748e8938, (q31_t)0x748423e0, (q31_t)0x7479ba0b, + (q31_t)0x746f4bb8, (q31_t)0x7464d8e8, + (q31_t)0x745a619b, (q31_t)0x744fe5d2, (q31_t)0x7445658d, (q31_t)0x743ae0cc, (q31_t)0x74305790, (q31_t)0x7425c9da, + (q31_t)0x741b37a9, (q31_t)0x7410a0fe, + (q31_t)0x740605d9, (q31_t)0x73fb663c, (q31_t)0x73f0c226, (q31_t)0x73e61997, (q31_t)0x73db6c91, (q31_t)0x73d0bb13, + (q31_t)0x73c6051f, (q31_t)0x73bb4ab3, + (q31_t)0x73b08bd1, (q31_t)0x73a5c87a, (q31_t)0x739b00ad, (q31_t)0x7390346b, (q31_t)0x738563b5, (q31_t)0x737a8e8a, + (q31_t)0x736fb4ec, (q31_t)0x7364d6da, + (q31_t)0x7359f456, (q31_t)0x734f0d5f, (q31_t)0x734421f6, (q31_t)0x7339321b, (q31_t)0x732e3dcf, (q31_t)0x73234512, + (q31_t)0x731847e5, (q31_t)0x730d4648, + (q31_t)0x7302403c, (q31_t)0x72f735c0, (q31_t)0x72ec26d6, (q31_t)0x72e1137d, (q31_t)0x72d5fbb7, (q31_t)0x72cadf83, + (q31_t)0x72bfbee3, (q31_t)0x72b499d6, + (q31_t)0x72a9705c, (q31_t)0x729e4277, (q31_t)0x72931027, (q31_t)0x7287d96c, (q31_t)0x727c9e47, (q31_t)0x72715eb8, + (q31_t)0x72661abf, (q31_t)0x725ad25d, + (q31_t)0x724f8593, (q31_t)0x72443460, (q31_t)0x7238dec5, (q31_t)0x722d84c4, (q31_t)0x7222265b, (q31_t)0x7216c38c, + (q31_t)0x720b5c57, (q31_t)0x71fff0bc, + (q31_t)0x71f480bc, (q31_t)0x71e90c57, (q31_t)0x71dd938f, (q31_t)0x71d21662, (q31_t)0x71c694d2, (q31_t)0x71bb0edf, + (q31_t)0x71af848a, (q31_t)0x71a3f5d2, + (q31_t)0x719862b9, (q31_t)0x718ccb3f, (q31_t)0x71812f65, (q31_t)0x71758f29, (q31_t)0x7169ea8f, (q31_t)0x715e4194, + (q31_t)0x7152943b, (q31_t)0x7146e284, + (q31_t)0x713b2c6e, (q31_t)0x712f71fb, (q31_t)0x7123b32b, (q31_t)0x7117effe, (q31_t)0x710c2875, (q31_t)0x71005c90, + (q31_t)0x70f48c50, (q31_t)0x70e8b7b5, + (q31_t)0x70dcdec0, (q31_t)0x70d10171, (q31_t)0x70c51fc8, (q31_t)0x70b939c7, (q31_t)0x70ad4f6d, (q31_t)0x70a160ba, + (q31_t)0x70956db1, (q31_t)0x70897650, + (q31_t)0x707d7a98, (q31_t)0x70717a8a, (q31_t)0x70657626, (q31_t)0x70596d6d, (q31_t)0x704d6060, (q31_t)0x70414efd, + (q31_t)0x70353947, (q31_t)0x70291f3e, + (q31_t)0x701d00e1, (q31_t)0x7010de32, (q31_t)0x7004b731, (q31_t)0x6ff88bde, (q31_t)0x6fec5c3b, (q31_t)0x6fe02846, + (q31_t)0x6fd3f001, (q31_t)0x6fc7b36d, + (q31_t)0x6fbb728a, (q31_t)0x6faf2d57, (q31_t)0x6fa2e3d7, (q31_t)0x6f969608, (q31_t)0x6f8a43ed, (q31_t)0x6f7ded84, + (q31_t)0x6f7192cf, (q31_t)0x6f6533ce, + (q31_t)0x6f58d082, (q31_t)0x6f4c68eb, (q31_t)0x6f3ffd09, (q31_t)0x6f338cde, (q31_t)0x6f271868, (q31_t)0x6f1a9faa, + (q31_t)0x6f0e22a3, (q31_t)0x6f01a155, + (q31_t)0x6ef51bbe, (q31_t)0x6ee891e1, (q31_t)0x6edc03bc, (q31_t)0x6ecf7152, (q31_t)0x6ec2daa2, (q31_t)0x6eb63fad, + (q31_t)0x6ea9a073, (q31_t)0x6e9cfcf5, + (q31_t)0x6e905534, (q31_t)0x6e83a92f, (q31_t)0x6e76f8e7, (q31_t)0x6e6a445d, (q31_t)0x6e5d8b91, (q31_t)0x6e50ce84, + (q31_t)0x6e440d37, (q31_t)0x6e3747a9, + (q31_t)0x6e2a7ddb, (q31_t)0x6e1dafce, (q31_t)0x6e10dd82, (q31_t)0x6e0406f8, (q31_t)0x6df72c30, (q31_t)0x6dea4d2b, + (q31_t)0x6ddd69e9, (q31_t)0x6dd0826a, + (q31_t)0x6dc396b0, (q31_t)0x6db6a6ba, (q31_t)0x6da9b28a, (q31_t)0x6d9cba1f, (q31_t)0x6d8fbd7a, (q31_t)0x6d82bc9d, + (q31_t)0x6d75b786, (q31_t)0x6d68ae37, + (q31_t)0x6d5ba0b0, (q31_t)0x6d4e8ef2, (q31_t)0x6d4178fd, (q31_t)0x6d345ed1, (q31_t)0x6d274070, (q31_t)0x6d1a1dda, + (q31_t)0x6d0cf70f, (q31_t)0x6cffcc0f, + (q31_t)0x6cf29cdc, (q31_t)0x6ce56975, (q31_t)0x6cd831dc, (q31_t)0x6ccaf610, (q31_t)0x6cbdb613, (q31_t)0x6cb071e4, + (q31_t)0x6ca32985, (q31_t)0x6c95dcf6, + (q31_t)0x6c888c36, (q31_t)0x6c7b3748, (q31_t)0x6c6dde2b, (q31_t)0x6c6080e0, (q31_t)0x6c531f67, (q31_t)0x6c45b9c1, + (q31_t)0x6c384fef, (q31_t)0x6c2ae1f0, + (q31_t)0x6c1d6fc6, (q31_t)0x6c0ff971, (q31_t)0x6c027ef1, (q31_t)0x6bf50047, (q31_t)0x6be77d74, (q31_t)0x6bd9f677, + (q31_t)0x6bcc6b53, (q31_t)0x6bbedc06, + (q31_t)0x6bb14892, (q31_t)0x6ba3b0f7, (q31_t)0x6b961536, (q31_t)0x6b88754f, (q31_t)0x6b7ad142, (q31_t)0x6b6d2911, + (q31_t)0x6b5f7cbc, (q31_t)0x6b51cc42, + (q31_t)0x6b4417a6, (q31_t)0x6b365ee7, (q31_t)0x6b28a206, (q31_t)0x6b1ae103, (q31_t)0x6b0d1bdf, (q31_t)0x6aff529a, + (q31_t)0x6af18536, (q31_t)0x6ae3b3b2, + (q31_t)0x6ad5de0f, (q31_t)0x6ac8044e, (q31_t)0x6aba266e, (q31_t)0x6aac4472, (q31_t)0x6a9e5e58, (q31_t)0x6a907423, + (q31_t)0x6a8285d1, (q31_t)0x6a749365, + (q31_t)0x6a669cdd, (q31_t)0x6a58a23c, (q31_t)0x6a4aa381, (q31_t)0x6a3ca0ad, (q31_t)0x6a2e99c0, (q31_t)0x6a208ebb, + (q31_t)0x6a127f9f, (q31_t)0x6a046c6c, + (q31_t)0x69f65523, (q31_t)0x69e839c4, (q31_t)0x69da1a50, (q31_t)0x69cbf6c7, (q31_t)0x69bdcf29, (q31_t)0x69afa378, + (q31_t)0x69a173b5, (q31_t)0x69933fde, + (q31_t)0x698507f6, (q31_t)0x6976cbfc, (q31_t)0x69688bf1, (q31_t)0x695a47d6, (q31_t)0x694bffab, (q31_t)0x693db371, + (q31_t)0x692f6328, (q31_t)0x69210ed1, + (q31_t)0x6912b66c, (q31_t)0x690459fb, (q31_t)0x68f5f97d, (q31_t)0x68e794f3, (q31_t)0x68d92c5d, (q31_t)0x68cabfbd, + (q31_t)0x68bc4f13, (q31_t)0x68adda5f, + (q31_t)0x689f61a1, (q31_t)0x6890e4dc, (q31_t)0x6882640e, (q31_t)0x6873df38, (q31_t)0x6865565c, (q31_t)0x6856c979, + (q31_t)0x68483891, (q31_t)0x6839a3a4, + (q31_t)0x682b0ab1, (q31_t)0x681c6dbb, (q31_t)0x680dccc1, (q31_t)0x67ff27c4, (q31_t)0x67f07ec5, (q31_t)0x67e1d1c4, + (q31_t)0x67d320c1, (q31_t)0x67c46bbe, + (q31_t)0x67b5b2bb, (q31_t)0x67a6f5b8, (q31_t)0x679834b6, (q31_t)0x67896fb6, (q31_t)0x677aa6b8, (q31_t)0x676bd9bd, + (q31_t)0x675d08c4, (q31_t)0x674e33d0, + (q31_t)0x673f5ae0, (q31_t)0x67307df5, (q31_t)0x67219d10, (q31_t)0x6712b831, (q31_t)0x6703cf58, (q31_t)0x66f4e287, + (q31_t)0x66e5f1be, (q31_t)0x66d6fcfd, + (q31_t)0x66c80445, (q31_t)0x66b90797, (q31_t)0x66aa06f3, (q31_t)0x669b0259, (q31_t)0x668bf9cb, (q31_t)0x667ced49, + (q31_t)0x666ddcd3, (q31_t)0x665ec86b, + (q31_t)0x664fb010, (q31_t)0x664093c3, (q31_t)0x66317385, (q31_t)0x66224f56, (q31_t)0x66132738, (q31_t)0x6603fb2a, + (q31_t)0x65f4cb2d, (q31_t)0x65e59742, + (q31_t)0x65d65f69, (q31_t)0x65c723a3, (q31_t)0x65b7e3f1, (q31_t)0x65a8a052, (q31_t)0x659958c9, (q31_t)0x658a0d54, + (q31_t)0x657abdf6, (q31_t)0x656b6aae, + (q31_t)0x655c137d, (q31_t)0x654cb863, (q31_t)0x653d5962, (q31_t)0x652df679, (q31_t)0x651e8faa, (q31_t)0x650f24f5, + (q31_t)0x64ffb65b, (q31_t)0x64f043dc, + (q31_t)0x64e0cd78, (q31_t)0x64d15331, (q31_t)0x64c1d507, (q31_t)0x64b252fa, (q31_t)0x64a2cd0c, (q31_t)0x6493433c, + (q31_t)0x6483b58c, (q31_t)0x647423fb, + (q31_t)0x64648e8c, (q31_t)0x6454f53d, (q31_t)0x64455810, (q31_t)0x6435b706, (q31_t)0x6426121e, (q31_t)0x6416695a, + (q31_t)0x6406bcba, (q31_t)0x63f70c3f, + (q31_t)0x63e757ea, (q31_t)0x63d79fba, (q31_t)0x63c7e3b1, (q31_t)0x63b823cf, (q31_t)0x63a86015, (q31_t)0x63989884, + (q31_t)0x6388cd1b, (q31_t)0x6378fddc, + (q31_t)0x63692ac7, (q31_t)0x635953dd, (q31_t)0x6349791f, (q31_t)0x63399a8d, (q31_t)0x6329b827, (q31_t)0x6319d1ef, + (q31_t)0x6309e7e4, (q31_t)0x62f9fa09, + (q31_t)0x62ea085c, (q31_t)0x62da12df, (q31_t)0x62ca1992, (q31_t)0x62ba1c77, (q31_t)0x62aa1b8d, (q31_t)0x629a16d5, + (q31_t)0x628a0e50, (q31_t)0x627a01fe, + (q31_t)0x6269f1e1, (q31_t)0x6259ddf8, (q31_t)0x6249c645, (q31_t)0x6239aac7, (q31_t)0x62298b81, (q31_t)0x62196871, + (q31_t)0x62094199, (q31_t)0x61f916f9, + (q31_t)0x61e8e893, (q31_t)0x61d8b666, (q31_t)0x61c88074, (q31_t)0x61b846bc, (q31_t)0x61a80940, (q31_t)0x6197c800, + (q31_t)0x618782fd, (q31_t)0x61773a37, + (q31_t)0x6166edb0, (q31_t)0x61569d67, (q31_t)0x6146495d, (q31_t)0x6135f193, (q31_t)0x6125960a, (q31_t)0x611536c2, + (q31_t)0x6104d3bc, (q31_t)0x60f46cf9, + (q31_t)0x60e40278, (q31_t)0x60d3943b, (q31_t)0x60c32243, (q31_t)0x60b2ac8f, (q31_t)0x60a23322, (q31_t)0x6091b5fa, + (q31_t)0x60813519, (q31_t)0x6070b080, + (q31_t)0x6060282f, (q31_t)0x604f9c27, (q31_t)0x603f0c69, (q31_t)0x602e78f4, (q31_t)0x601de1ca, (q31_t)0x600d46ec, + (q31_t)0x5ffca859, (q31_t)0x5fec0613, + (q31_t)0x5fdb601b, (q31_t)0x5fcab670, (q31_t)0x5fba0914, (q31_t)0x5fa95807, (q31_t)0x5f98a34a, (q31_t)0x5f87eade, + (q31_t)0x5f772ec2, (q31_t)0x5f666ef9, + (q31_t)0x5f55ab82, (q31_t)0x5f44e45e, (q31_t)0x5f34198e, (q31_t)0x5f234b12, (q31_t)0x5f1278eb, (q31_t)0x5f01a31a, + (q31_t)0x5ef0c99f, (q31_t)0x5edfec7b, + (q31_t)0x5ecf0baf, (q31_t)0x5ebe273b, (q31_t)0x5ead3f1f, (q31_t)0x5e9c535e, (q31_t)0x5e8b63f7, (q31_t)0x5e7a70ea, + (q31_t)0x5e697a39, (q31_t)0x5e587fe5, + (q31_t)0x5e4781ed, (q31_t)0x5e368053, (q31_t)0x5e257b17, (q31_t)0x5e147239, (q31_t)0x5e0365bb, (q31_t)0x5df2559e, + (q31_t)0x5de141e1, (q31_t)0x5dd02a85, + (q31_t)0x5dbf0f8c, (q31_t)0x5dadf0f5, (q31_t)0x5d9ccec2, (q31_t)0x5d8ba8f3, (q31_t)0x5d7a7f88, (q31_t)0x5d695283, + (q31_t)0x5d5821e4, (q31_t)0x5d46edac, + (q31_t)0x5d35b5db, (q31_t)0x5d247a72, (q31_t)0x5d133b72, (q31_t)0x5d01f8dc, (q31_t)0x5cf0b2af, (q31_t)0x5cdf68ed, + (q31_t)0x5cce1b97, (q31_t)0x5cbccaac, + (q31_t)0x5cab762f, (q31_t)0x5c9a1e1e, (q31_t)0x5c88c27c, (q31_t)0x5c776348, (q31_t)0x5c660084, (q31_t)0x5c549a30, + (q31_t)0x5c43304d, (q31_t)0x5c31c2db, + (q31_t)0x5c2051db, (q31_t)0x5c0edd4e, (q31_t)0x5bfd6534, (q31_t)0x5bebe98e, (q31_t)0x5bda6a5d, (q31_t)0x5bc8e7a2, + (q31_t)0x5bb7615d, (q31_t)0x5ba5d78e, + (q31_t)0x5b944a37, (q31_t)0x5b82b958, (q31_t)0x5b7124f2, (q31_t)0x5b5f8d06, (q31_t)0x5b4df193, (q31_t)0x5b3c529c, + (q31_t)0x5b2ab020, (q31_t)0x5b190a20, + (q31_t)0x5b07609d, (q31_t)0x5af5b398, (q31_t)0x5ae40311, (q31_t)0x5ad24f09, (q31_t)0x5ac09781, (q31_t)0x5aaedc78, + (q31_t)0x5a9d1df1, (q31_t)0x5a8b5bec, + (q31_t)0x5a799669, (q31_t)0x5a67cd69, (q31_t)0x5a5600ec, (q31_t)0x5a4430f5, (q31_t)0x5a325d82, (q31_t)0x5a208695, + (q31_t)0x5a0eac2e, (q31_t)0x59fcce4f, + (q31_t)0x59eaecf8, (q31_t)0x59d90829, (q31_t)0x59c71fe3, (q31_t)0x59b53427, (q31_t)0x59a344f6, (q31_t)0x59915250, + (q31_t)0x597f5c36, (q31_t)0x596d62a9, + (q31_t)0x595b65aa, (q31_t)0x59496538, (q31_t)0x59376155, (q31_t)0x59255a02, (q31_t)0x59134f3e, (q31_t)0x5901410c, + (q31_t)0x58ef2f6b, (q31_t)0x58dd1a5d, + (q31_t)0x58cb01e1, (q31_t)0x58b8e5f9, (q31_t)0x58a6c6a5, (q31_t)0x5894a3e7, (q31_t)0x58827dbe, (q31_t)0x5870542c, + (q31_t)0x585e2730, (q31_t)0x584bf6cd, + (q31_t)0x5839c302, (q31_t)0x58278bd1, (q31_t)0x58155139, (q31_t)0x5803133c, (q31_t)0x57f0d1da, (q31_t)0x57de8d15, + (q31_t)0x57cc44ec, (q31_t)0x57b9f960, + (q31_t)0x57a7aa73, (q31_t)0x57955825, (q31_t)0x57830276, (q31_t)0x5770a968, (q31_t)0x575e4cfa, (q31_t)0x574bed2f, + (q31_t)0x57398a05, (q31_t)0x5727237f, + (q31_t)0x5714b99d, (q31_t)0x57024c5f, (q31_t)0x56efdbc7, (q31_t)0x56dd67d4, (q31_t)0x56caf088, (q31_t)0x56b875e4, + (q31_t)0x56a5f7e7, (q31_t)0x56937694, + (q31_t)0x5680f1ea, (q31_t)0x566e69ea, (q31_t)0x565bde95, (q31_t)0x56494fec, (q31_t)0x5636bdef, (q31_t)0x5624289f, + (q31_t)0x56118ffe, (q31_t)0x55fef40a, + (q31_t)0x55ec54c6, (q31_t)0x55d9b232, (q31_t)0x55c70c4f, (q31_t)0x55b4631d, (q31_t)0x55a1b69d, (q31_t)0x558f06d0, + (q31_t)0x557c53b6, (q31_t)0x55699d51, + (q31_t)0x5556e3a1, (q31_t)0x554426a7, (q31_t)0x55316663, (q31_t)0x551ea2d6, (q31_t)0x550bdc01, (q31_t)0x54f911e5, + (q31_t)0x54e64482, (q31_t)0x54d373d9, + (q31_t)0x54c09feb, (q31_t)0x54adc8b8, (q31_t)0x549aee42, (q31_t)0x54881089, (q31_t)0x54752f8d, (q31_t)0x54624b50, + (q31_t)0x544f63d2, (q31_t)0x543c7914, + (q31_t)0x54298b17, (q31_t)0x541699db, (q31_t)0x5403a561, (q31_t)0x53f0adaa, (q31_t)0x53ddb2b6, (q31_t)0x53cab486, + (q31_t)0x53b7b31c, (q31_t)0x53a4ae77, + (q31_t)0x5391a699, (q31_t)0x537e9b82, (q31_t)0x536b8d33, (q31_t)0x53587bad, (q31_t)0x534566f0, (q31_t)0x53324efd, + (q31_t)0x531f33d5, (q31_t)0x530c1579, + (q31_t)0x52f8f3e9, (q31_t)0x52e5cf27, (q31_t)0x52d2a732, (q31_t)0x52bf7c0b, (q31_t)0x52ac4db4, (q31_t)0x52991c2d, + (q31_t)0x5285e777, (q31_t)0x5272af92, + (q31_t)0x525f7480, (q31_t)0x524c3640, (q31_t)0x5238f4d4, (q31_t)0x5225b03d, (q31_t)0x5212687b, (q31_t)0x51ff1d8f, + (q31_t)0x51ebcf7a, (q31_t)0x51d87e3c, + (q31_t)0x51c529d7, (q31_t)0x51b1d24a, (q31_t)0x519e7797, (q31_t)0x518b19bf, (q31_t)0x5177b8c2, (q31_t)0x516454a0, + (q31_t)0x5150ed5c, (q31_t)0x513d82f4, + (q31_t)0x512a156b, (q31_t)0x5116a4c1, (q31_t)0x510330f7, (q31_t)0x50efba0d, (q31_t)0x50dc4005, (q31_t)0x50c8c2de, + (q31_t)0x50b5429a, (q31_t)0x50a1bf39, + (q31_t)0x508e38bd, (q31_t)0x507aaf25, (q31_t)0x50672273, (q31_t)0x505392a8, (q31_t)0x503fffc4, (q31_t)0x502c69c8, + (q31_t)0x5018d0b4, (q31_t)0x5005348a, + (q31_t)0x4ff1954b, (q31_t)0x4fddf2f6, (q31_t)0x4fca4d8d, (q31_t)0x4fb6a510, (q31_t)0x4fa2f981, (q31_t)0x4f8f4ae0, + (q31_t)0x4f7b992d, (q31_t)0x4f67e46a, + (q31_t)0x4f542c98, (q31_t)0x4f4071b6, (q31_t)0x4f2cb3c7, (q31_t)0x4f18f2c9, (q31_t)0x4f052ec0, (q31_t)0x4ef167aa, + (q31_t)0x4edd9d89, (q31_t)0x4ec9d05e, + (q31_t)0x4eb60029, (q31_t)0x4ea22ceb, (q31_t)0x4e8e56a5, (q31_t)0x4e7a7d58, (q31_t)0x4e66a105, (q31_t)0x4e52c1ab, + (q31_t)0x4e3edf4d, (q31_t)0x4e2af9ea, + (q31_t)0x4e171184, (q31_t)0x4e03261b, (q31_t)0x4def37b0, (q31_t)0x4ddb4644, (q31_t)0x4dc751d8, (q31_t)0x4db35a6c, + (q31_t)0x4d9f6001, (q31_t)0x4d8b6298, + (q31_t)0x4d776231, (q31_t)0x4d635ece, (q31_t)0x4d4f5870, (q31_t)0x4d3b4f16, (q31_t)0x4d2742c2, (q31_t)0x4d133374, + (q31_t)0x4cff212e, (q31_t)0x4ceb0bf0, + (q31_t)0x4cd6f3bb, (q31_t)0x4cc2d88f, (q31_t)0x4caeba6e, (q31_t)0x4c9a9958, (q31_t)0x4c86754e, (q31_t)0x4c724e50, + (q31_t)0x4c5e2460, (q31_t)0x4c49f77f, + (q31_t)0x4c35c7ac, (q31_t)0x4c2194e9, (q31_t)0x4c0d5f37, (q31_t)0x4bf92697, (q31_t)0x4be4eb08, (q31_t)0x4bd0ac8d, + (q31_t)0x4bbc6b25, (q31_t)0x4ba826d1, + (q31_t)0x4b93df93, (q31_t)0x4b7f956b, (q31_t)0x4b6b485a, (q31_t)0x4b56f861, (q31_t)0x4b42a580, (q31_t)0x4b2e4fb8, + (q31_t)0x4b19f70a, (q31_t)0x4b059b77, + (q31_t)0x4af13d00, (q31_t)0x4adcdba5, (q31_t)0x4ac87767, (q31_t)0x4ab41046, (q31_t)0x4a9fa645, (q31_t)0x4a8b3963, + (q31_t)0x4a76c9a2, (q31_t)0x4a625701, + (q31_t)0x4a4de182, (q31_t)0x4a396926, (q31_t)0x4a24edee, (q31_t)0x4a106fda, (q31_t)0x49fbeeea, (q31_t)0x49e76b21, + (q31_t)0x49d2e47e, (q31_t)0x49be5b02, + (q31_t)0x49a9ceaf, (q31_t)0x49953f84, (q31_t)0x4980ad84, (q31_t)0x496c18ae, (q31_t)0x49578103, (q31_t)0x4942e684, + (q31_t)0x492e4933, (q31_t)0x4919a90f, + (q31_t)0x4905061a, (q31_t)0x48f06054, (q31_t)0x48dbb7be, (q31_t)0x48c70c59, (q31_t)0x48b25e25, (q31_t)0x489dad25, + (q31_t)0x4888f957, (q31_t)0x487442be, + (q31_t)0x485f8959, (q31_t)0x484acd2a, (q31_t)0x48360e32, (q31_t)0x48214c71, (q31_t)0x480c87e8, (q31_t)0x47f7c099, + (q31_t)0x47e2f682, (q31_t)0x47ce29a7, + (q31_t)0x47b95a06, (q31_t)0x47a487a2, (q31_t)0x478fb27b, (q31_t)0x477ada91, (q31_t)0x4765ffe6, (q31_t)0x4751227a, + (q31_t)0x473c424e, (q31_t)0x47275f63, + (q31_t)0x471279ba, (q31_t)0x46fd9154, (q31_t)0x46e8a631, (q31_t)0x46d3b852, (q31_t)0x46bec7b8, (q31_t)0x46a9d464, + (q31_t)0x4694de56, (q31_t)0x467fe590, + (q31_t)0x466aea12, (q31_t)0x4655ebdd, (q31_t)0x4640eaf2, (q31_t)0x462be751, (q31_t)0x4616e0fc, (q31_t)0x4601d7f3, + (q31_t)0x45eccc37, (q31_t)0x45d7bdc9, + (q31_t)0x45c2acaa, (q31_t)0x45ad98da, (q31_t)0x4598825a, (q31_t)0x4583692c, (q31_t)0x456e4d4f, (q31_t)0x45592ec6, + (q31_t)0x45440d90, (q31_t)0x452ee9ae, + (q31_t)0x4519c321, (q31_t)0x450499eb, (q31_t)0x44ef6e0b, (q31_t)0x44da3f83, (q31_t)0x44c50e53, (q31_t)0x44afda7d, + (q31_t)0x449aa400, (q31_t)0x44856adf, + (q31_t)0x44702f19, (q31_t)0x445af0b0, (q31_t)0x4445afa4, (q31_t)0x44306bf6, (q31_t)0x441b25a8, (q31_t)0x4405dcb9, + (q31_t)0x43f0912b, (q31_t)0x43db42fe, + (q31_t)0x43c5f234, (q31_t)0x43b09ecc, (q31_t)0x439b48c9, (q31_t)0x4385f02a, (q31_t)0x437094f1, (q31_t)0x435b371f, + (q31_t)0x4345d6b3, (q31_t)0x433073b0, + (q31_t)0x431b0e15, (q31_t)0x4305a5e5, (q31_t)0x42f03b1e, (q31_t)0x42dacdc3, (q31_t)0x42c55dd4, (q31_t)0x42afeb53, + (q31_t)0x429a763f, (q31_t)0x4284fe99, + (q31_t)0x426f8463, (q31_t)0x425a079e, (q31_t)0x42448849, (q31_t)0x422f0667, (q31_t)0x421981f7, (q31_t)0x4203fafb, + (q31_t)0x41ee7174, (q31_t)0x41d8e561, + (q31_t)0x41c356c5, (q31_t)0x41adc5a0, (q31_t)0x419831f3, (q31_t)0x41829bbe, (q31_t)0x416d0302, (q31_t)0x415767c1, + (q31_t)0x4141c9fb, (q31_t)0x412c29b1, + (q31_t)0x411686e4, (q31_t)0x4100e194, (q31_t)0x40eb39c3, (q31_t)0x40d58f71, (q31_t)0x40bfe29f, (q31_t)0x40aa334e, + (q31_t)0x4094817f, (q31_t)0x407ecd32, + (q31_t)0x40691669, (q31_t)0x40535d24, (q31_t)0x403da165, (q31_t)0x4027e32b, (q31_t)0x40122278, (q31_t)0x3ffc5f4d, + (q31_t)0x3fe699aa, (q31_t)0x3fd0d191, + (q31_t)0x3fbb0702, (q31_t)0x3fa539fd, (q31_t)0x3f8f6a85, (q31_t)0x3f799899, (q31_t)0x3f63c43b, (q31_t)0x3f4ded6b, + (q31_t)0x3f38142a, (q31_t)0x3f22387a, + (q31_t)0x3f0c5a5a, (q31_t)0x3ef679cc, (q31_t)0x3ee096d1, (q31_t)0x3ecab169, (q31_t)0x3eb4c995, (q31_t)0x3e9edf57, + (q31_t)0x3e88f2ae, (q31_t)0x3e73039d, + (q31_t)0x3e5d1222, (q31_t)0x3e471e41, (q31_t)0x3e3127f9, (q31_t)0x3e1b2f4a, (q31_t)0x3e053437, (q31_t)0x3def36c0, + (q31_t)0x3dd936e6, (q31_t)0x3dc334a9, + (q31_t)0x3dad300b, (q31_t)0x3d97290b, (q31_t)0x3d811fac, (q31_t)0x3d6b13ee, (q31_t)0x3d5505d2, (q31_t)0x3d3ef559, + (q31_t)0x3d28e282, (q31_t)0x3d12cd51, + (q31_t)0x3cfcb5c4, (q31_t)0x3ce69bde, (q31_t)0x3cd07f9f, (q31_t)0x3cba6107, (q31_t)0x3ca44018, (q31_t)0x3c8e1cd3, + (q31_t)0x3c77f737, (q31_t)0x3c61cf48, + (q31_t)0x3c4ba504, (q31_t)0x3c35786d, (q31_t)0x3c1f4983, (q31_t)0x3c091849, (q31_t)0x3bf2e4be, (q31_t)0x3bdcaee3, + (q31_t)0x3bc676b9, (q31_t)0x3bb03c42, + (q31_t)0x3b99ff7d, (q31_t)0x3b83c06c, (q31_t)0x3b6d7f10, (q31_t)0x3b573b69, (q31_t)0x3b40f579, (q31_t)0x3b2aad3f, + (q31_t)0x3b1462be, (q31_t)0x3afe15f6, + (q31_t)0x3ae7c6e7, (q31_t)0x3ad17593, (q31_t)0x3abb21fb, (q31_t)0x3aa4cc1e, (q31_t)0x3a8e7400, (q31_t)0x3a78199f, + (q31_t)0x3a61bcfd, (q31_t)0x3a4b5e1b, + (q31_t)0x3a34fcf9, (q31_t)0x3a1e9999, (q31_t)0x3a0833fc, (q31_t)0x39f1cc21, (q31_t)0x39db620b, (q31_t)0x39c4f5ba, + (q31_t)0x39ae872f, (q31_t)0x3998166a, + (q31_t)0x3981a36d, (q31_t)0x396b2e38, (q31_t)0x3954b6cd, (q31_t)0x393e3d2c, (q31_t)0x3927c155, (q31_t)0x3911434b, + (q31_t)0x38fac30e, (q31_t)0x38e4409e, + (q31_t)0x38cdbbfc, (q31_t)0x38b7352a, (q31_t)0x38a0ac29, (q31_t)0x388a20f8, (q31_t)0x38739399, (q31_t)0x385d040d, + (q31_t)0x38467255, (q31_t)0x382fde72, + (q31_t)0x38194864, (q31_t)0x3802b02c, (q31_t)0x37ec15cb, (q31_t)0x37d57943, (q31_t)0x37beda93, (q31_t)0x37a839be, + (q31_t)0x379196c3, (q31_t)0x377af1a3, + (q31_t)0x37644a60, (q31_t)0x374da0fa, (q31_t)0x3736f573, (q31_t)0x372047ca, (q31_t)0x37099802, (q31_t)0x36f2e61a, + (q31_t)0x36dc3214, (q31_t)0x36c57bf0, + (q31_t)0x36aec3b0, (q31_t)0x36980954, (q31_t)0x36814cde, (q31_t)0x366a8e4d, (q31_t)0x3653cda3, (q31_t)0x363d0ae2, + (q31_t)0x36264609, (q31_t)0x360f7f19, + (q31_t)0x35f8b614, (q31_t)0x35e1eafa, (q31_t)0x35cb1dcc, (q31_t)0x35b44e8c, (q31_t)0x359d7d39, (q31_t)0x3586a9d5, + (q31_t)0x356fd461, (q31_t)0x3558fcde, + (q31_t)0x3542234c, (q31_t)0x352b47ad, (q31_t)0x35146a00, (q31_t)0x34fd8a48, (q31_t)0x34e6a885, (q31_t)0x34cfc4b7, + (q31_t)0x34b8dee1, (q31_t)0x34a1f702, + (q31_t)0x348b0d1c, (q31_t)0x3474212f, (q31_t)0x345d333c, (q31_t)0x34464345, (q31_t)0x342f5149, (q31_t)0x34185d4b, + (q31_t)0x3401674a, (q31_t)0x33ea6f48, + (q31_t)0x33d37546, (q31_t)0x33bc7944, (q31_t)0x33a57b44, (q31_t)0x338e7b46, (q31_t)0x3377794b, (q31_t)0x33607554, + (q31_t)0x33496f62, (q31_t)0x33326776, + (q31_t)0x331b5d91, (q31_t)0x330451b3, (q31_t)0x32ed43de, (q31_t)0x32d63412, (q31_t)0x32bf2250, (q31_t)0x32a80e99, + (q31_t)0x3290f8ef, (q31_t)0x3279e151, + (q31_t)0x3262c7c1, (q31_t)0x324bac40, (q31_t)0x32348ecf, (q31_t)0x321d6f6e, (q31_t)0x32064e1e, (q31_t)0x31ef2ae1, + (q31_t)0x31d805b7, (q31_t)0x31c0dea1, + (q31_t)0x31a9b5a0, (q31_t)0x31928ab4, (q31_t)0x317b5de0, (q31_t)0x31642f23, (q31_t)0x314cfe7f, (q31_t)0x3135cbf4, + (q31_t)0x311e9783, (q31_t)0x3107612e, + (q31_t)0x30f028f4, (q31_t)0x30d8eed8, (q31_t)0x30c1b2da, (q31_t)0x30aa74fa, (q31_t)0x3093353a, (q31_t)0x307bf39b, + (q31_t)0x3064b01d, (q31_t)0x304d6ac1, + (q31_t)0x30362389, (q31_t)0x301eda75, (q31_t)0x30078f86, (q31_t)0x2ff042bd, (q31_t)0x2fd8f41b, (q31_t)0x2fc1a3a0, + (q31_t)0x2faa514f, (q31_t)0x2f92fd26, + (q31_t)0x2f7ba729, (q31_t)0x2f644f56, (q31_t)0x2f4cf5b0, (q31_t)0x2f359a37, (q31_t)0x2f1e3ced, (q31_t)0x2f06ddd1, + (q31_t)0x2eef7ce5, (q31_t)0x2ed81a29, + (q31_t)0x2ec0b5a0, (q31_t)0x2ea94f49, (q31_t)0x2e91e725, (q31_t)0x2e7a7d36, (q31_t)0x2e63117c, (q31_t)0x2e4ba3f8, + (q31_t)0x2e3434ac, (q31_t)0x2e1cc397, + (q31_t)0x2e0550bb, (q31_t)0x2deddc19, (q31_t)0x2dd665b2, (q31_t)0x2dbeed86, (q31_t)0x2da77397, (q31_t)0x2d8ff7e5, + (q31_t)0x2d787a72, (q31_t)0x2d60fb3e, + (q31_t)0x2d497a4a, (q31_t)0x2d31f797, (q31_t)0x2d1a7325, (q31_t)0x2d02ecf7, (q31_t)0x2ceb650d, (q31_t)0x2cd3db67, + (q31_t)0x2cbc5006, (q31_t)0x2ca4c2ed, + (q31_t)0x2c8d341a, (q31_t)0x2c75a390, (q31_t)0x2c5e114f, (q31_t)0x2c467d58, (q31_t)0x2c2ee7ad, (q31_t)0x2c17504d, + (q31_t)0x2bffb73a, (q31_t)0x2be81c74, + (q31_t)0x2bd07ffe, (q31_t)0x2bb8e1d7, (q31_t)0x2ba14200, (q31_t)0x2b89a07b, (q31_t)0x2b71fd48, (q31_t)0x2b5a5868, + (q31_t)0x2b42b1dd, (q31_t)0x2b2b09a6, + (q31_t)0x2b135fc6, (q31_t)0x2afbb43c, (q31_t)0x2ae4070a, (q31_t)0x2acc5831, (q31_t)0x2ab4a7b1, (q31_t)0x2a9cf58c, + (q31_t)0x2a8541c3, (q31_t)0x2a6d8c55, + (q31_t)0x2a55d545, (q31_t)0x2a3e1c93, (q31_t)0x2a266240, (q31_t)0x2a0ea64d, (q31_t)0x29f6e8bb, (q31_t)0x29df298b, + (q31_t)0x29c768be, (q31_t)0x29afa654, + (q31_t)0x2997e24f, (q31_t)0x29801caf, (q31_t)0x29685576, (q31_t)0x29508ca4, (q31_t)0x2938c23a, (q31_t)0x2920f63a, + (q31_t)0x290928a3, (q31_t)0x28f15978, + (q31_t)0x28d988b8, (q31_t)0x28c1b666, (q31_t)0x28a9e281, (q31_t)0x28920d0a, (q31_t)0x287a3604, (q31_t)0x28625d6d, + (q31_t)0x284a8349, (q31_t)0x2832a796, + (q31_t)0x281aca57, (q31_t)0x2802eb8c, (q31_t)0x27eb0b36, (q31_t)0x27d32956, (q31_t)0x27bb45ed, (q31_t)0x27a360fc, + (q31_t)0x278b7a84, (q31_t)0x27739285, + (q31_t)0x275ba901, (q31_t)0x2743bdf9, (q31_t)0x272bd16d, (q31_t)0x2713e35f, (q31_t)0x26fbf3ce, (q31_t)0x26e402bd, + (q31_t)0x26cc102d, (q31_t)0x26b41c1d, + (q31_t)0x269c268f, (q31_t)0x26842f84, (q31_t)0x266c36fe, (q31_t)0x26543cfb, (q31_t)0x263c417f, (q31_t)0x26244489, + (q31_t)0x260c461b, (q31_t)0x25f44635, + (q31_t)0x25dc44d9, (q31_t)0x25c44207, (q31_t)0x25ac3dc0, (q31_t)0x25943806, (q31_t)0x257c30d8, (q31_t)0x25642839, + (q31_t)0x254c1e28, (q31_t)0x253412a8, + (q31_t)0x251c05b8, (q31_t)0x2503f75a, (q31_t)0x24ebe78f, (q31_t)0x24d3d657, (q31_t)0x24bbc3b4, (q31_t)0x24a3afa6, + (q31_t)0x248b9a2f, (q31_t)0x2473834f, + (q31_t)0x245b6b07, (q31_t)0x24435158, (q31_t)0x242b3644, (q31_t)0x241319ca, (q31_t)0x23fafbec, (q31_t)0x23e2dcac, + (q31_t)0x23cabc09, (q31_t)0x23b29a05, + (q31_t)0x239a76a0, (q31_t)0x238251dd, (q31_t)0x236a2bba, (q31_t)0x2352043b, (q31_t)0x2339db5e, (q31_t)0x2321b126, + (q31_t)0x23098593, (q31_t)0x22f158a7, + (q31_t)0x22d92a61, (q31_t)0x22c0fac4, (q31_t)0x22a8c9cf, (q31_t)0x22909785, (q31_t)0x227863e5, (q31_t)0x22602ef1, + (q31_t)0x2247f8aa, (q31_t)0x222fc111, + (q31_t)0x22178826, (q31_t)0x21ff4dea, (q31_t)0x21e71260, (q31_t)0x21ced586, (q31_t)0x21b6975f, (q31_t)0x219e57eb, + (q31_t)0x2186172b, (q31_t)0x216dd521, + (q31_t)0x215591cc, (q31_t)0x213d4d2f, (q31_t)0x21250749, (q31_t)0x210cc01d, (q31_t)0x20f477aa, (q31_t)0x20dc2df2, + (q31_t)0x20c3e2f5, (q31_t)0x20ab96b5, + (q31_t)0x20934933, (q31_t)0x207afa6f, (q31_t)0x2062aa6b, (q31_t)0x204a5927, (q31_t)0x203206a4, (q31_t)0x2019b2e4, + (q31_t)0x20015de7, (q31_t)0x1fe907ae, + (q31_t)0x1fd0b03a, (q31_t)0x1fb8578b, (q31_t)0x1f9ffda4, (q31_t)0x1f87a285, (q31_t)0x1f6f462f, (q31_t)0x1f56e8a2, + (q31_t)0x1f3e89e0, (q31_t)0x1f2629ea, + (q31_t)0x1f0dc8c0, (q31_t)0x1ef56664, (q31_t)0x1edd02d6, (q31_t)0x1ec49e17, (q31_t)0x1eac3829, (q31_t)0x1e93d10c, + (q31_t)0x1e7b68c2, (q31_t)0x1e62ff4a, + (q31_t)0x1e4a94a7, (q31_t)0x1e3228d9, (q31_t)0x1e19bbe0, (q31_t)0x1e014dbf, (q31_t)0x1de8de75, (q31_t)0x1dd06e04, + (q31_t)0x1db7fc6d, (q31_t)0x1d9f89b1, + (q31_t)0x1d8715d0, (q31_t)0x1d6ea0cc, (q31_t)0x1d562aa6, (q31_t)0x1d3db35e, (q31_t)0x1d253af5, (q31_t)0x1d0cc16c, + (q31_t)0x1cf446c5, (q31_t)0x1cdbcb00, + (q31_t)0x1cc34e1f, (q31_t)0x1caad021, (q31_t)0x1c925109, (q31_t)0x1c79d0d6, (q31_t)0x1c614f8b, (q31_t)0x1c48cd27, + (q31_t)0x1c3049ac, (q31_t)0x1c17c51b, + (q31_t)0x1bff3f75, (q31_t)0x1be6b8ba, (q31_t)0x1bce30ec, (q31_t)0x1bb5a80c, (q31_t)0x1b9d1e1a, (q31_t)0x1b849317, + (q31_t)0x1b6c0705, (q31_t)0x1b5379e5, + (q31_t)0x1b3aebb6, (q31_t)0x1b225c7b, (q31_t)0x1b09cc34, (q31_t)0x1af13ae3, (q31_t)0x1ad8a887, (q31_t)0x1ac01522, + (q31_t)0x1aa780b6, (q31_t)0x1a8eeb42, + (q31_t)0x1a7654c8, (q31_t)0x1a5dbd49, (q31_t)0x1a4524c6, (q31_t)0x1a2c8b3f, (q31_t)0x1a13f0b6, (q31_t)0x19fb552c, + (q31_t)0x19e2b8a2, (q31_t)0x19ca1b17, + (q31_t)0x19b17c8f, (q31_t)0x1998dd09, (q31_t)0x19803c86, (q31_t)0x19679b07, (q31_t)0x194ef88e, (q31_t)0x1936551b, + (q31_t)0x191db0af, (q31_t)0x19050b4b, + (q31_t)0x18ec64f0, (q31_t)0x18d3bda0, (q31_t)0x18bb155a, (q31_t)0x18a26c20, (q31_t)0x1889c1f3, (q31_t)0x187116d4, + (q31_t)0x18586ac3, (q31_t)0x183fbdc3, + (q31_t)0x18270fd3, (q31_t)0x180e60f4, (q31_t)0x17f5b129, (q31_t)0x17dd0070, (q31_t)0x17c44ecd, (q31_t)0x17ab9c3e, + (q31_t)0x1792e8c6, (q31_t)0x177a3466, + (q31_t)0x17617f1d, (q31_t)0x1748c8ee, (q31_t)0x173011d9, (q31_t)0x171759df, (q31_t)0x16fea102, (q31_t)0x16e5e741, + (q31_t)0x16cd2c9f, (q31_t)0x16b4711b, + (q31_t)0x169bb4b7, (q31_t)0x1682f774, (q31_t)0x166a3953, (q31_t)0x16517a55, (q31_t)0x1638ba7a, (q31_t)0x161ff9c4, + (q31_t)0x16073834, (q31_t)0x15ee75cb, + (q31_t)0x15d5b288, (q31_t)0x15bcee6f, (q31_t)0x15a4297f, (q31_t)0x158b63b9, (q31_t)0x15729d1f, (q31_t)0x1559d5b1, + (q31_t)0x15410d70, (q31_t)0x1528445d, + (q31_t)0x150f7a7a, (q31_t)0x14f6afc7, (q31_t)0x14dde445, (q31_t)0x14c517f4, (q31_t)0x14ac4ad7, (q31_t)0x14937cee, + (q31_t)0x147aae3a, (q31_t)0x1461debc, + (q31_t)0x14490e74, (q31_t)0x14303d65, (q31_t)0x14176b8e, (q31_t)0x13fe98f1, (q31_t)0x13e5c58e, (q31_t)0x13ccf167, + (q31_t)0x13b41c7d, (q31_t)0x139b46d0, + (q31_t)0x13827062, (q31_t)0x13699933, (q31_t)0x1350c144, (q31_t)0x1337e897, (q31_t)0x131f0f2c, (q31_t)0x13063505, + (q31_t)0x12ed5a21, (q31_t)0x12d47e83, + (q31_t)0x12bba22b, (q31_t)0x12a2c51b, (q31_t)0x1289e752, (q31_t)0x127108d2, (q31_t)0x1258299c, (q31_t)0x123f49b2, + (q31_t)0x12266913, (q31_t)0x120d87c1, + (q31_t)0x11f4a5bd, (q31_t)0x11dbc307, (q31_t)0x11c2dfa2, (q31_t)0x11a9fb8d, (q31_t)0x119116c9, (q31_t)0x11783159, + (q31_t)0x115f4b3c, (q31_t)0x11466473, + (q31_t)0x112d7d00, (q31_t)0x111494e4, (q31_t)0x10fbac1e, (q31_t)0x10e2c2b2, (q31_t)0x10c9d89e, (q31_t)0x10b0ede5, + (q31_t)0x10980287, (q31_t)0x107f1686, + (q31_t)0x106629e1, (q31_t)0x104d3c9b, (q31_t)0x10344eb4, (q31_t)0x101b602d, (q31_t)0x10027107, (q31_t)0xfe98143, + (q31_t)0xfd090e1, (q31_t)0xfb79fe4, + (q31_t)0xf9eae4c, (q31_t)0xf85bc19, (q31_t)0xf6cc94e, (q31_t)0xf53d5ea, (q31_t)0xf3ae1ee, (q31_t)0xf21ed5d, (q31_t)0xf08f836, + (q31_t)0xef0027b, + (q31_t)0xed70c2c, (q31_t)0xebe154b, (q31_t)0xea51dd8, (q31_t)0xe8c25d5, (q31_t)0xe732d42, (q31_t)0xe5a3421, (q31_t)0xe413a72, + (q31_t)0xe284036, + (q31_t)0xe0f456f, (q31_t)0xdf64a1c, (q31_t)0xddd4e40, (q31_t)0xdc451dc, (q31_t)0xdab54ef, (q31_t)0xd92577b, (q31_t)0xd795982, + (q31_t)0xd605b03, + (q31_t)0xd475c00, (q31_t)0xd2e5c7b, (q31_t)0xd155c73, (q31_t)0xcfc5bea, (q31_t)0xce35ae1, (q31_t)0xcca5959, (q31_t)0xcb15752, + (q31_t)0xc9854cf, + (q31_t)0xc7f51cf, (q31_t)0xc664e53, (q31_t)0xc4d4a5d, (q31_t)0xc3445ee, (q31_t)0xc1b4107, (q31_t)0xc023ba7, (q31_t)0xbe935d2, + (q31_t)0xbd02f87, + (q31_t)0xbb728c7, (q31_t)0xb9e2193, (q31_t)0xb8519ed, (q31_t)0xb6c11d5, (q31_t)0xb53094d, (q31_t)0xb3a0055, (q31_t)0xb20f6ee, + (q31_t)0xb07ed19, + (q31_t)0xaeee2d7, (q31_t)0xad5d829, (q31_t)0xabccd11, (q31_t)0xaa3c18e, (q31_t)0xa8ab5a2, (q31_t)0xa71a94f, (q31_t)0xa589c94, + (q31_t)0xa3f8f73, + (q31_t)0xa2681ed, (q31_t)0xa0d7403, (q31_t)0x9f465b5, (q31_t)0x9db5706, (q31_t)0x9c247f5, (q31_t)0x9a93884, (q31_t)0x99028b3, + (q31_t)0x9771884, + (q31_t)0x95e07f8, (q31_t)0x944f70f, (q31_t)0x92be5ca, (q31_t)0x912d42c, (q31_t)0x8f9c233, (q31_t)0x8e0afe2, (q31_t)0x8c79d3a, + (q31_t)0x8ae8a3a, + (q31_t)0x89576e5, (q31_t)0x87c633c, (q31_t)0x8634f3e, (q31_t)0x84a3aee, (q31_t)0x831264c, (q31_t)0x8181159, (q31_t)0x7fefc16, + (q31_t)0x7e5e685, + (q31_t)0x7ccd0a5, (q31_t)0x7b3ba78, (q31_t)0x79aa400, (q31_t)0x7818d3c, (q31_t)0x768762e, (q31_t)0x74f5ed7, (q31_t)0x7364738, + (q31_t)0x71d2f52, + (q31_t)0x7041726, (q31_t)0x6eafeb4, (q31_t)0x6d1e5fe, (q31_t)0x6b8cd05, (q31_t)0x69fb3c9, (q31_t)0x6869a4c, (q31_t)0x66d808f, + (q31_t)0x6546692, + (q31_t)0x63b4c57, (q31_t)0x62231de, (q31_t)0x6091729, (q31_t)0x5effc38, (q31_t)0x5d6e10c, (q31_t)0x5bdc5a7, (q31_t)0x5a4aa09, + (q31_t)0x58b8e34, + (q31_t)0x5727228, (q31_t)0x55955e6, (q31_t)0x540396f, (q31_t)0x5271cc4, (q31_t)0x50dffe7, (q31_t)0x4f4e2d8, (q31_t)0x4dbc597, + (q31_t)0x4c2a827, + (q31_t)0x4a98a88, (q31_t)0x4906cbb, (q31_t)0x4774ec1, (q31_t)0x45e309a, (q31_t)0x4451249, (q31_t)0x42bf3cd, (q31_t)0x412d528, + (q31_t)0x3f9b65b, + (q31_t)0x3e09767, (q31_t)0x3c7784d, (q31_t)0x3ae590d, (q31_t)0x39539a9, (q31_t)0x37c1a22, (q31_t)0x362fa78, (q31_t)0x349daac, + (q31_t)0x330bac1, + (q31_t)0x3179ab5, (q31_t)0x2fe7a8c, (q31_t)0x2e55a44, (q31_t)0x2cc39e1, (q31_t)0x2b31961, (q31_t)0x299f8c7, (q31_t)0x280d813, + (q31_t)0x267b747, + (q31_t)0x24e9662, (q31_t)0x2357567, (q31_t)0x21c5457, (q31_t)0x2033331, (q31_t)0x1ea11f7, (q31_t)0x1d0f0ab, (q31_t)0x1b7cf4d, + (q31_t)0x19eaddd, + (q31_t)0x1858c5e, (q31_t)0x16c6ad0, (q31_t)0x1534934, (q31_t)0x13a278a, (q31_t)0x12105d5, (q31_t)0x107e414, (q31_t)0xeec249, + (q31_t)0xd5a075, + (q31_t)0xbc7e99, (q31_t)0xa35cb5, (q31_t)0x8a3acb, (q31_t)0x7118dc, (q31_t)0x57f6e9, (q31_t)0x3ed4f2, (q31_t)0x25b2f8, + (q31_t)0xc90fe +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192) + const q31_t WeightsQ31_8192[16384] = { + (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7fffffd9, (q31_t)0xfff9b781, (q31_t)0x7fffff62, (q31_t)0xfff36f02, (q31_t)0x7ffffe9d, (q31_t)0xffed2684, + (q31_t)0x7ffffd88, (q31_t)0xffe6de05, (q31_t)0x7ffffc25, (q31_t)0xffe09586, (q31_t)0x7ffffa73, (q31_t)0xffda4d08, (q31_t)0x7ffff872, (q31_t)0xffd40489, + (q31_t)0x7ffff621, (q31_t)0xffcdbc0b, (q31_t)0x7ffff382, (q31_t)0xffc7738c, (q31_t)0x7ffff094, (q31_t)0xffc12b0e, (q31_t)0x7fffed57, (q31_t)0xffbae290, + (q31_t)0x7fffe9cb, (q31_t)0xffb49a12, (q31_t)0x7fffe5f0, (q31_t)0xffae5195, (q31_t)0x7fffe1c6, (q31_t)0xffa80917, (q31_t)0x7fffdd4d, (q31_t)0xffa1c09a, + (q31_t)0x7fffd886, (q31_t)0xff9b781d, (q31_t)0x7fffd36f, (q31_t)0xff952fa0, (q31_t)0x7fffce09, (q31_t)0xff8ee724, (q31_t)0x7fffc854, (q31_t)0xff889ea7, + (q31_t)0x7fffc251, (q31_t)0xff82562c, (q31_t)0x7fffbbfe, (q31_t)0xff7c0db0, (q31_t)0x7fffb55c, (q31_t)0xff75c535, (q31_t)0x7fffae6c, (q31_t)0xff6f7cba, + (q31_t)0x7fffa72c, (q31_t)0xff69343f, (q31_t)0x7fff9f9e, (q31_t)0xff62ebc5, (q31_t)0x7fff97c1, (q31_t)0xff5ca34b, (q31_t)0x7fff8f94, (q31_t)0xff565ad1, + (q31_t)0x7fff8719, (q31_t)0xff501258, (q31_t)0x7fff7e4f, (q31_t)0xff49c9df, (q31_t)0x7fff7536, (q31_t)0xff438167, (q31_t)0x7fff6bcd, (q31_t)0xff3d38ef, + (q31_t)0x7fff6216, (q31_t)0xff36f078, (q31_t)0x7fff5810, (q31_t)0xff30a801, (q31_t)0x7fff4dbb, (q31_t)0xff2a5f8b, (q31_t)0x7fff4317, (q31_t)0xff241715, + (q31_t)0x7fff3824, (q31_t)0xff1dcea0, (q31_t)0x7fff2ce2, (q31_t)0xff17862b, (q31_t)0x7fff2151, (q31_t)0xff113db7, (q31_t)0x7fff1572, (q31_t)0xff0af543, + (q31_t)0x7fff0943, (q31_t)0xff04acd0, (q31_t)0x7ffefcc5, (q31_t)0xfefe645e, (q31_t)0x7ffeeff8, (q31_t)0xfef81bec, (q31_t)0x7ffee2dd, (q31_t)0xfef1d37b, + (q31_t)0x7ffed572, (q31_t)0xfeeb8b0a, (q31_t)0x7ffec7b9, (q31_t)0xfee5429a, (q31_t)0x7ffeb9b0, (q31_t)0xfedefa2b, (q31_t)0x7ffeab59, (q31_t)0xfed8b1bd, + (q31_t)0x7ffe9cb2, (q31_t)0xfed2694f, (q31_t)0x7ffe8dbd, (q31_t)0xfecc20e2, (q31_t)0x7ffe7e79, (q31_t)0xfec5d876, (q31_t)0x7ffe6ee5, (q31_t)0xfebf900a, + (q31_t)0x7ffe5f03, (q31_t)0xfeb947a0, (q31_t)0x7ffe4ed2, (q31_t)0xfeb2ff36, (q31_t)0x7ffe3e52, (q31_t)0xfeacb6cc, (q31_t)0x7ffe2d83, (q31_t)0xfea66e64, + (q31_t)0x7ffe1c65, (q31_t)0xfea025fd, (q31_t)0x7ffe0af8, (q31_t)0xfe99dd96, (q31_t)0x7ffdf93c, (q31_t)0xfe939530, (q31_t)0x7ffde731, (q31_t)0xfe8d4ccb, + (q31_t)0x7ffdd4d7, (q31_t)0xfe870467, (q31_t)0x7ffdc22e, (q31_t)0xfe80bc04, (q31_t)0x7ffdaf37, (q31_t)0xfe7a73a2, (q31_t)0x7ffd9bf0, (q31_t)0xfe742b41, + (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ffd7476, (q31_t)0xfe679a81, (q31_t)0x7ffd6042, (q31_t)0xfe615223, (q31_t)0x7ffd4bc0, (q31_t)0xfe5b09c5, + (q31_t)0x7ffd36ee, (q31_t)0xfe54c169, (q31_t)0x7ffd21ce, (q31_t)0xfe4e790d, (q31_t)0x7ffd0c5f, (q31_t)0xfe4830b3, (q31_t)0x7ffcf6a0, (q31_t)0xfe41e85a, + (q31_t)0x7ffce093, (q31_t)0xfe3ba002, (q31_t)0x7ffcca37, (q31_t)0xfe3557ab, (q31_t)0x7ffcb38c, (q31_t)0xfe2f0f55, (q31_t)0x7ffc9c92, (q31_t)0xfe28c700, + (q31_t)0x7ffc8549, (q31_t)0xfe227eac, (q31_t)0x7ffc6db1, (q31_t)0xfe1c365a, (q31_t)0x7ffc55ca, (q31_t)0xfe15ee09, (q31_t)0x7ffc3d94, (q31_t)0xfe0fa5b8, + (q31_t)0x7ffc250f, (q31_t)0xfe095d69, (q31_t)0x7ffc0c3b, (q31_t)0xfe03151c, (q31_t)0x7ffbf319, (q31_t)0xfdfccccf, (q31_t)0x7ffbd9a7, (q31_t)0xfdf68484, + (q31_t)0x7ffbbfe6, (q31_t)0xfdf03c3a, (q31_t)0x7ffba5d7, (q31_t)0xfde9f3f1, (q31_t)0x7ffb8b78, (q31_t)0xfde3aba9, (q31_t)0x7ffb70cb, (q31_t)0xfddd6363, + (q31_t)0x7ffb55ce, (q31_t)0xfdd71b1e, (q31_t)0x7ffb3a83, (q31_t)0xfdd0d2db, (q31_t)0x7ffb1ee9, (q31_t)0xfdca8a99, (q31_t)0x7ffb0300, (q31_t)0xfdc44258, + (q31_t)0x7ffae6c7, (q31_t)0xfdbdfa18, (q31_t)0x7ffaca40, (q31_t)0xfdb7b1da, (q31_t)0x7ffaad6a, (q31_t)0xfdb1699e, (q31_t)0x7ffa9045, (q31_t)0xfdab2162, + (q31_t)0x7ffa72d1, (q31_t)0xfda4d929, (q31_t)0x7ffa550e, (q31_t)0xfd9e90f0, (q31_t)0x7ffa36fc, (q31_t)0xfd9848b9, (q31_t)0x7ffa189c, (q31_t)0xfd920084, + (q31_t)0x7ff9f9ec, (q31_t)0xfd8bb850, (q31_t)0x7ff9daed, (q31_t)0xfd85701e, (q31_t)0x7ff9bba0, (q31_t)0xfd7f27ed, (q31_t)0x7ff99c03, (q31_t)0xfd78dfbd, + (q31_t)0x7ff97c18, (q31_t)0xfd729790, (q31_t)0x7ff95bdd, (q31_t)0xfd6c4f64, (q31_t)0x7ff93b54, (q31_t)0xfd660739, (q31_t)0x7ff91a7b, (q31_t)0xfd5fbf10, + (q31_t)0x7ff8f954, (q31_t)0xfd5976e9, (q31_t)0x7ff8d7de, (q31_t)0xfd532ec3, (q31_t)0x7ff8b619, (q31_t)0xfd4ce69f, (q31_t)0x7ff89405, (q31_t)0xfd469e7c, + (q31_t)0x7ff871a2, (q31_t)0xfd40565c, (q31_t)0x7ff84ef0, (q31_t)0xfd3a0e3d, (q31_t)0x7ff82bef, (q31_t)0xfd33c61f, (q31_t)0x7ff8089f, (q31_t)0xfd2d7e04, + (q31_t)0x7ff7e500, (q31_t)0xfd2735ea, (q31_t)0x7ff7c113, (q31_t)0xfd20edd2, (q31_t)0x7ff79cd6, (q31_t)0xfd1aa5bc, (q31_t)0x7ff7784a, (q31_t)0xfd145da7, + (q31_t)0x7ff75370, (q31_t)0xfd0e1594, (q31_t)0x7ff72e46, (q31_t)0xfd07cd83, (q31_t)0x7ff708ce, (q31_t)0xfd018574, (q31_t)0x7ff6e307, (q31_t)0xfcfb3d67, + (q31_t)0x7ff6bcf0, (q31_t)0xfcf4f55c, (q31_t)0x7ff6968b, (q31_t)0xfceead52, (q31_t)0x7ff66fd7, (q31_t)0xfce8654b, (q31_t)0x7ff648d4, (q31_t)0xfce21d45, + (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7ff5f9e1, (q31_t)0xfcd58d3f, (q31_t)0x7ff5d1f1, (q31_t)0xfccf453f, (q31_t)0x7ff5a9b2, (q31_t)0xfcc8fd41, + (q31_t)0x7ff58125, (q31_t)0xfcc2b545, (q31_t)0x7ff55848, (q31_t)0xfcbc6d4c, (q31_t)0x7ff52f1d, (q31_t)0xfcb62554, (q31_t)0x7ff505a2, (q31_t)0xfcafdd5e, + (q31_t)0x7ff4dbd9, (q31_t)0xfca9956a, (q31_t)0x7ff4b1c0, (q31_t)0xfca34d78, (q31_t)0x7ff48759, (q31_t)0xfc9d0588, (q31_t)0x7ff45ca3, (q31_t)0xfc96bd9b, + (q31_t)0x7ff4319d, (q31_t)0xfc9075af, (q31_t)0x7ff40649, (q31_t)0xfc8a2dc6, (q31_t)0x7ff3daa6, (q31_t)0xfc83e5de, (q31_t)0x7ff3aeb4, (q31_t)0xfc7d9df9, + (q31_t)0x7ff38274, (q31_t)0xfc775616, (q31_t)0x7ff355e4, (q31_t)0xfc710e36, (q31_t)0x7ff32905, (q31_t)0xfc6ac657, (q31_t)0x7ff2fbd7, (q31_t)0xfc647e7b, + (q31_t)0x7ff2ce5b, (q31_t)0xfc5e36a0, (q31_t)0x7ff2a08f, (q31_t)0xfc57eec9, (q31_t)0x7ff27275, (q31_t)0xfc51a6f3, (q31_t)0x7ff2440b, (q31_t)0xfc4b5f20, + (q31_t)0x7ff21553, (q31_t)0xfc45174e, (q31_t)0x7ff1e64c, (q31_t)0xfc3ecf80, (q31_t)0x7ff1b6f6, (q31_t)0xfc3887b3, (q31_t)0x7ff18751, (q31_t)0xfc323fe9, + (q31_t)0x7ff1575d, (q31_t)0xfc2bf821, (q31_t)0x7ff1271a, (q31_t)0xfc25b05c, (q31_t)0x7ff0f688, (q31_t)0xfc1f6899, (q31_t)0x7ff0c5a7, (q31_t)0xfc1920d8, + (q31_t)0x7ff09478, (q31_t)0xfc12d91a, (q31_t)0x7ff062f9, (q31_t)0xfc0c915e, (q31_t)0x7ff0312c, (q31_t)0xfc0649a5, (q31_t)0x7fefff0f, (q31_t)0xfc0001ee, + (q31_t)0x7fefcca4, (q31_t)0xfbf9ba39, (q31_t)0x7fef99ea, (q31_t)0xfbf37287, (q31_t)0x7fef66e1, (q31_t)0xfbed2ad8, (q31_t)0x7fef3388, (q31_t)0xfbe6e32b, + (q31_t)0x7feeffe1, (q31_t)0xfbe09b80, (q31_t)0x7feecbec, (q31_t)0xfbda53d8, (q31_t)0x7fee97a7, (q31_t)0xfbd40c33, (q31_t)0x7fee6313, (q31_t)0xfbcdc490, + (q31_t)0x7fee2e30, (q31_t)0xfbc77cf0, (q31_t)0x7fedf8ff, (q31_t)0xfbc13552, (q31_t)0x7fedc37e, (q31_t)0xfbbaedb7, (q31_t)0x7fed8daf, (q31_t)0xfbb4a61f, + (q31_t)0x7fed5791, (q31_t)0xfbae5e89, (q31_t)0x7fed2123, (q31_t)0xfba816f6, (q31_t)0x7fecea67, (q31_t)0xfba1cf66, (q31_t)0x7fecb35c, (q31_t)0xfb9b87d8, + (q31_t)0x7fec7c02, (q31_t)0xfb95404d, (q31_t)0x7fec4459, (q31_t)0xfb8ef8c5, (q31_t)0x7fec0c62, (q31_t)0xfb88b13f, (q31_t)0x7febd41b, (q31_t)0xfb8269bd, + (q31_t)0x7feb9b85, (q31_t)0xfb7c223d, (q31_t)0x7feb62a1, (q31_t)0xfb75dac0, (q31_t)0x7feb296d, (q31_t)0xfb6f9345, (q31_t)0x7feaefeb, (q31_t)0xfb694bce, + (q31_t)0x7feab61a, (q31_t)0xfb630459, (q31_t)0x7fea7bfa, (q31_t)0xfb5cbce7, (q31_t)0x7fea418b, (q31_t)0xfb567578, (q31_t)0x7fea06cd, (q31_t)0xfb502e0c, + (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3, (q31_t)0x7fe99064, (q31_t)0xfb439f3c, (q31_t)0x7fe954ba, (q31_t)0xfb3d57d9, (q31_t)0x7fe918c0, (q31_t)0xfb371078, + (q31_t)0x7fe8dc78, (q31_t)0xfb30c91b, (q31_t)0x7fe89fe0, (q31_t)0xfb2a81c0, (q31_t)0x7fe862fa, (q31_t)0xfb243a69, (q31_t)0x7fe825c5, (q31_t)0xfb1df314, + (q31_t)0x7fe7e841, (q31_t)0xfb17abc2, (q31_t)0x7fe7aa6e, (q31_t)0xfb116474, (q31_t)0x7fe76c4c, (q31_t)0xfb0b1d28, (q31_t)0x7fe72ddb, (q31_t)0xfb04d5e0, + (q31_t)0x7fe6ef1c, (q31_t)0xfafe8e9b, (q31_t)0x7fe6b00d, (q31_t)0xfaf84758, (q31_t)0x7fe670b0, (q31_t)0xfaf20019, (q31_t)0x7fe63103, (q31_t)0xfaebb8dd, + (q31_t)0x7fe5f108, (q31_t)0xfae571a4, (q31_t)0x7fe5b0be, (q31_t)0xfadf2a6e, (q31_t)0x7fe57025, (q31_t)0xfad8e33c, (q31_t)0x7fe52f3d, (q31_t)0xfad29c0c, + (q31_t)0x7fe4ee06, (q31_t)0xfacc54e0, (q31_t)0x7fe4ac81, (q31_t)0xfac60db7, (q31_t)0x7fe46aac, (q31_t)0xfabfc691, (q31_t)0x7fe42889, (q31_t)0xfab97f6e, + (q31_t)0x7fe3e616, (q31_t)0xfab3384f, (q31_t)0x7fe3a355, (q31_t)0xfaacf133, (q31_t)0x7fe36045, (q31_t)0xfaa6aa1a, (q31_t)0x7fe31ce6, (q31_t)0xfaa06305, + (q31_t)0x7fe2d938, (q31_t)0xfa9a1bf3, (q31_t)0x7fe2953b, (q31_t)0xfa93d4e4, (q31_t)0x7fe250ef, (q31_t)0xfa8d8dd8, (q31_t)0x7fe20c55, (q31_t)0xfa8746d0, + (q31_t)0x7fe1c76b, (q31_t)0xfa80ffcb, (q31_t)0x7fe18233, (q31_t)0xfa7ab8ca, (q31_t)0x7fe13cac, (q31_t)0xfa7471cc, (q31_t)0x7fe0f6d6, (q31_t)0xfa6e2ad1, + (q31_t)0x7fe0b0b1, (q31_t)0xfa67e3da, (q31_t)0x7fe06a3d, (q31_t)0xfa619ce7, (q31_t)0x7fe0237a, (q31_t)0xfa5b55f7, (q31_t)0x7fdfdc69, (q31_t)0xfa550f0a, + (q31_t)0x7fdf9508, (q31_t)0xfa4ec821, (q31_t)0x7fdf4d59, (q31_t)0xfa48813b, (q31_t)0x7fdf055a, (q31_t)0xfa423a59, (q31_t)0x7fdebd0d, (q31_t)0xfa3bf37a, + (q31_t)0x7fde7471, (q31_t)0xfa35ac9f, (q31_t)0x7fde2b86, (q31_t)0xfa2f65c8, (q31_t)0x7fdde24d, (q31_t)0xfa291ef4, (q31_t)0x7fdd98c4, (q31_t)0xfa22d823, + (q31_t)0x7fdd4eec, (q31_t)0xfa1c9157, (q31_t)0x7fdd04c6, (q31_t)0xfa164a8e, (q31_t)0x7fdcba51, (q31_t)0xfa1003c8, (q31_t)0x7fdc6f8d, (q31_t)0xfa09bd06, + (q31_t)0x7fdc247a, (q31_t)0xfa037648, (q31_t)0x7fdbd918, (q31_t)0xf9fd2f8e, (q31_t)0x7fdb8d67, (q31_t)0xf9f6e8d7, (q31_t)0x7fdb4167, (q31_t)0xf9f0a224, + (q31_t)0x7fdaf519, (q31_t)0xf9ea5b75, (q31_t)0x7fdaa87c, (q31_t)0xf9e414ca, (q31_t)0x7fda5b8f, (q31_t)0xf9ddce22, (q31_t)0x7fda0e54, (q31_t)0xf9d7877e, + (q31_t)0x7fd9c0ca, (q31_t)0xf9d140de, (q31_t)0x7fd972f2, (q31_t)0xf9cafa42, (q31_t)0x7fd924ca, (q31_t)0xf9c4b3a9, (q31_t)0x7fd8d653, (q31_t)0xf9be6d15, + (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fd8387a, (q31_t)0xf9b1dff7, (q31_t)0x7fd7e917, (q31_t)0xf9ab996e, (q31_t)0x7fd79965, (q31_t)0xf9a552e9, + (q31_t)0x7fd74964, (q31_t)0xf99f0c68, (q31_t)0x7fd6f914, (q31_t)0xf998c5ea, (q31_t)0x7fd6a875, (q31_t)0xf9927f71, (q31_t)0x7fd65788, (q31_t)0xf98c38fc, + (q31_t)0x7fd6064c, (q31_t)0xf985f28a, (q31_t)0x7fd5b4c1, (q31_t)0xf97fac1d, (q31_t)0x7fd562e7, (q31_t)0xf97965b4, (q31_t)0x7fd510be, (q31_t)0xf9731f4e, + (q31_t)0x7fd4be46, (q31_t)0xf96cd8ed, (q31_t)0x7fd46b80, (q31_t)0xf9669290, (q31_t)0x7fd4186a, (q31_t)0xf9604c37, (q31_t)0x7fd3c506, (q31_t)0xf95a05e2, + (q31_t)0x7fd37153, (q31_t)0xf953bf91, (q31_t)0x7fd31d51, (q31_t)0xf94d7944, (q31_t)0x7fd2c900, (q31_t)0xf94732fb, (q31_t)0x7fd27460, (q31_t)0xf940ecb7, + (q31_t)0x7fd21f72, (q31_t)0xf93aa676, (q31_t)0x7fd1ca35, (q31_t)0xf934603a, (q31_t)0x7fd174a8, (q31_t)0xf92e1a02, (q31_t)0x7fd11ecd, (q31_t)0xf927d3ce, + (q31_t)0x7fd0c8a3, (q31_t)0xf9218d9e, (q31_t)0x7fd0722b, (q31_t)0xf91b4773, (q31_t)0x7fd01b63, (q31_t)0xf915014c, (q31_t)0x7fcfc44d, (q31_t)0xf90ebb29, + (q31_t)0x7fcf6ce8, (q31_t)0xf908750a, (q31_t)0x7fcf1533, (q31_t)0xf9022ef0, (q31_t)0x7fcebd31, (q31_t)0xf8fbe8da, (q31_t)0x7fce64df, (q31_t)0xf8f5a2c9, + (q31_t)0x7fce0c3e, (q31_t)0xf8ef5cbb, (q31_t)0x7fcdb34f, (q31_t)0xf8e916b2, (q31_t)0x7fcd5a11, (q31_t)0xf8e2d0ae, (q31_t)0x7fcd0083, (q31_t)0xf8dc8aae, + (q31_t)0x7fcca6a7, (q31_t)0xf8d644b2, (q31_t)0x7fcc4c7d, (q31_t)0xf8cffebb, (q31_t)0x7fcbf203, (q31_t)0xf8c9b8c8, (q31_t)0x7fcb973b, (q31_t)0xf8c372d9, + (q31_t)0x7fcb3c23, (q31_t)0xf8bd2cef, (q31_t)0x7fcae0bd, (q31_t)0xf8b6e70a, (q31_t)0x7fca8508, (q31_t)0xf8b0a129, (q31_t)0x7fca2905, (q31_t)0xf8aa5b4c, + (q31_t)0x7fc9ccb2, (q31_t)0xf8a41574, (q31_t)0x7fc97011, (q31_t)0xf89dcfa1, (q31_t)0x7fc91320, (q31_t)0xf89789d2, (q31_t)0x7fc8b5e1, (q31_t)0xf8914407, + (q31_t)0x7fc85854, (q31_t)0xf88afe42, (q31_t)0x7fc7fa77, (q31_t)0xf884b880, (q31_t)0x7fc79c4b, (q31_t)0xf87e72c4, (q31_t)0x7fc73dd1, (q31_t)0xf8782d0c, + (q31_t)0x7fc6df08, (q31_t)0xf871e759, (q31_t)0x7fc67ff0, (q31_t)0xf86ba1aa, (q31_t)0x7fc62089, (q31_t)0xf8655c00, (q31_t)0x7fc5c0d3, (q31_t)0xf85f165b, + (q31_t)0x7fc560cf, (q31_t)0xf858d0bb, (q31_t)0x7fc5007c, (q31_t)0xf8528b1f, (q31_t)0x7fc49fda, (q31_t)0xf84c4588, (q31_t)0x7fc43ee9, (q31_t)0xf845fff5, + (q31_t)0x7fc3dda9, (q31_t)0xf83fba68, (q31_t)0x7fc37c1b, (q31_t)0xf83974df, (q31_t)0x7fc31a3d, (q31_t)0xf8332f5b, (q31_t)0x7fc2b811, (q31_t)0xf82ce9dc, + (q31_t)0x7fc25596, (q31_t)0xf826a462, (q31_t)0x7fc1f2cc, (q31_t)0xf8205eec, (q31_t)0x7fc18fb4, (q31_t)0xf81a197b, (q31_t)0x7fc12c4d, (q31_t)0xf813d410, + (q31_t)0x7fc0c896, (q31_t)0xf80d8ea9, (q31_t)0x7fc06491, (q31_t)0xf8074947, (q31_t)0x7fc0003e, (q31_t)0xf80103ea, (q31_t)0x7fbf9b9b, (q31_t)0xf7fabe92, + (q31_t)0x7fbf36aa, (q31_t)0xf7f4793e, (q31_t)0x7fbed16a, (q31_t)0xf7ee33f0, (q31_t)0x7fbe6bdb, (q31_t)0xf7e7eea7, (q31_t)0x7fbe05fd, (q31_t)0xf7e1a963, + (q31_t)0x7fbd9fd0, (q31_t)0xf7db6423, (q31_t)0x7fbd3955, (q31_t)0xf7d51ee9, (q31_t)0x7fbcd28b, (q31_t)0xf7ced9b4, (q31_t)0x7fbc6b72, (q31_t)0xf7c89484, + (q31_t)0x7fbc040a, (q31_t)0xf7c24f59, (q31_t)0x7fbb9c53, (q31_t)0xf7bc0a33, (q31_t)0x7fbb344e, (q31_t)0xf7b5c512, (q31_t)0x7fbacbfa, (q31_t)0xf7af7ff6, + (q31_t)0x7fba6357, (q31_t)0xf7a93ae0, (q31_t)0x7fb9fa65, (q31_t)0xf7a2f5ce, (q31_t)0x7fb99125, (q31_t)0xf79cb0c2, (q31_t)0x7fb92796, (q31_t)0xf7966bbb, + (q31_t)0x7fb8bdb8, (q31_t)0xf79026b9, (q31_t)0x7fb8538b, (q31_t)0xf789e1bc, (q31_t)0x7fb7e90f, (q31_t)0xf7839cc4, (q31_t)0x7fb77e45, (q31_t)0xf77d57d2, + (q31_t)0x7fb7132b, (q31_t)0xf77712e5, (q31_t)0x7fb6a7c3, (q31_t)0xf770cdfd, (q31_t)0x7fb63c0d, (q31_t)0xf76a891b, (q31_t)0x7fb5d007, (q31_t)0xf764443d, + (q31_t)0x7fb563b3, (q31_t)0xf75dff66, (q31_t)0x7fb4f710, (q31_t)0xf757ba93, (q31_t)0x7fb48a1e, (q31_t)0xf75175c6, (q31_t)0x7fb41cdd, (q31_t)0xf74b30fe, + (q31_t)0x7fb3af4e, (q31_t)0xf744ec3b, (q31_t)0x7fb34170, (q31_t)0xf73ea77e, (q31_t)0x7fb2d343, (q31_t)0xf73862c6, (q31_t)0x7fb264c7, (q31_t)0xf7321e14, + (q31_t)0x7fb1f5fc, (q31_t)0xf72bd967, (q31_t)0x7fb186e3, (q31_t)0xf72594c0, (q31_t)0x7fb1177b, (q31_t)0xf71f501e, (q31_t)0x7fb0a7c4, (q31_t)0xf7190b81, + (q31_t)0x7fb037bf, (q31_t)0xf712c6ea, (q31_t)0x7fafc76a, (q31_t)0xf70c8259, (q31_t)0x7faf56c7, (q31_t)0xf7063dcd, (q31_t)0x7faee5d5, (q31_t)0xf6fff946, + (q31_t)0x7fae7495, (q31_t)0xf6f9b4c6, (q31_t)0x7fae0305, (q31_t)0xf6f3704a, (q31_t)0x7fad9127, (q31_t)0xf6ed2bd4, (q31_t)0x7fad1efa, (q31_t)0xf6e6e764, + (q31_t)0x7facac7f, (q31_t)0xf6e0a2fa, (q31_t)0x7fac39b4, (q31_t)0xf6da5e95, (q31_t)0x7fabc69b, (q31_t)0xf6d41a36, (q31_t)0x7fab5333, (q31_t)0xf6cdd5dc, + (q31_t)0x7faadf7c, (q31_t)0xf6c79188, (q31_t)0x7faa6b77, (q31_t)0xf6c14d3a, (q31_t)0x7fa9f723, (q31_t)0xf6bb08f1, (q31_t)0x7fa98280, (q31_t)0xf6b4c4ae, + (q31_t)0x7fa90d8e, (q31_t)0xf6ae8071, (q31_t)0x7fa8984e, (q31_t)0xf6a83c3a, (q31_t)0x7fa822bf, (q31_t)0xf6a1f808, (q31_t)0x7fa7ace1, (q31_t)0xf69bb3dd, + (q31_t)0x7fa736b4, (q31_t)0xf6956fb7, (q31_t)0x7fa6c039, (q31_t)0xf68f2b96, (q31_t)0x7fa6496e, (q31_t)0xf688e77c, (q31_t)0x7fa5d256, (q31_t)0xf682a367, + (q31_t)0x7fa55aee, (q31_t)0xf67c5f59, (q31_t)0x7fa4e338, (q31_t)0xf6761b50, (q31_t)0x7fa46b32, (q31_t)0xf66fd74d, (q31_t)0x7fa3f2df, (q31_t)0xf6699350, + (q31_t)0x7fa37a3c, (q31_t)0xf6634f59, (q31_t)0x7fa3014b, (q31_t)0xf65d0b68, (q31_t)0x7fa2880b, (q31_t)0xf656c77c, (q31_t)0x7fa20e7c, (q31_t)0xf6508397, + (q31_t)0x7fa1949e, (q31_t)0xf64a3fb8, (q31_t)0x7fa11a72, (q31_t)0xf643fbdf, (q31_t)0x7fa09ff7, (q31_t)0xf63db80b, (q31_t)0x7fa0252e, (q31_t)0xf637743e, + (q31_t)0x7f9faa15, (q31_t)0xf6313077, (q31_t)0x7f9f2eae, (q31_t)0xf62aecb5, (q31_t)0x7f9eb2f8, (q31_t)0xf624a8fa, (q31_t)0x7f9e36f4, (q31_t)0xf61e6545, + (q31_t)0x7f9dbaa0, (q31_t)0xf6182196, (q31_t)0x7f9d3dfe, (q31_t)0xf611dded, (q31_t)0x7f9cc10d, (q31_t)0xf60b9a4b, (q31_t)0x7f9c43ce, (q31_t)0xf60556ae, + (q31_t)0x7f9bc640, (q31_t)0xf5ff1318, (q31_t)0x7f9b4863, (q31_t)0xf5f8cf87, (q31_t)0x7f9aca37, (q31_t)0xf5f28bfd, (q31_t)0x7f9a4bbd, (q31_t)0xf5ec4879, + (q31_t)0x7f99ccf4, (q31_t)0xf5e604fc, (q31_t)0x7f994ddc, (q31_t)0xf5dfc184, (q31_t)0x7f98ce76, (q31_t)0xf5d97e13, (q31_t)0x7f984ec1, (q31_t)0xf5d33aa8, + (q31_t)0x7f97cebd, (q31_t)0xf5ccf743, (q31_t)0x7f974e6a, (q31_t)0xf5c6b3e5, (q31_t)0x7f96cdc9, (q31_t)0xf5c0708d, (q31_t)0x7f964cd9, (q31_t)0xf5ba2d3b, + (q31_t)0x7f95cb9a, (q31_t)0xf5b3e9f0, (q31_t)0x7f954a0d, (q31_t)0xf5ada6ab, (q31_t)0x7f94c831, (q31_t)0xf5a7636c, (q31_t)0x7f944606, (q31_t)0xf5a12034, + (q31_t)0x7f93c38c, (q31_t)0xf59add02, (q31_t)0x7f9340c4, (q31_t)0xf59499d6, (q31_t)0x7f92bdad, (q31_t)0xf58e56b1, (q31_t)0x7f923a48, (q31_t)0xf5881393, + (q31_t)0x7f91b694, (q31_t)0xf581d07b, (q31_t)0x7f913291, (q31_t)0xf57b8d69, (q31_t)0x7f90ae3f, (q31_t)0xf5754a5e, (q31_t)0x7f90299f, (q31_t)0xf56f0759, + (q31_t)0x7f8fa4b0, (q31_t)0xf568c45b, (q31_t)0x7f8f1f72, (q31_t)0xf5628163, (q31_t)0x7f8e99e6, (q31_t)0xf55c3e72, (q31_t)0x7f8e140a, (q31_t)0xf555fb88, + (q31_t)0x7f8d8de1, (q31_t)0xf54fb8a4, (q31_t)0x7f8d0768, (q31_t)0xf54975c6, (q31_t)0x7f8c80a1, (q31_t)0xf54332ef, (q31_t)0x7f8bf98b, (q31_t)0xf53cf01f, + (q31_t)0x7f8b7227, (q31_t)0xf536ad56, (q31_t)0x7f8aea74, (q31_t)0xf5306a93, (q31_t)0x7f8a6272, (q31_t)0xf52a27d7, (q31_t)0x7f89da21, (q31_t)0xf523e521, + (q31_t)0x7f895182, (q31_t)0xf51da273, (q31_t)0x7f88c894, (q31_t)0xf5175fca, (q31_t)0x7f883f58, (q31_t)0xf5111d29, (q31_t)0x7f87b5cd, (q31_t)0xf50ada8f, + (q31_t)0x7f872bf3, (q31_t)0xf50497fb, (q31_t)0x7f86a1ca, (q31_t)0xf4fe556e, (q31_t)0x7f861753, (q31_t)0xf4f812e7, (q31_t)0x7f858c8d, (q31_t)0xf4f1d068, + (q31_t)0x7f850179, (q31_t)0xf4eb8def, (q31_t)0x7f847616, (q31_t)0xf4e54b7d, (q31_t)0x7f83ea64, (q31_t)0xf4df0912, (q31_t)0x7f835e64, (q31_t)0xf4d8c6ae, + (q31_t)0x7f82d214, (q31_t)0xf4d28451, (q31_t)0x7f824577, (q31_t)0xf4cc41fb, (q31_t)0x7f81b88a, (q31_t)0xf4c5ffab, (q31_t)0x7f812b4f, (q31_t)0xf4bfbd63, + (q31_t)0x7f809dc5, (q31_t)0xf4b97b21, (q31_t)0x7f800fed, (q31_t)0xf4b338e7, (q31_t)0x7f7f81c6, (q31_t)0xf4acf6b3, (q31_t)0x7f7ef350, (q31_t)0xf4a6b486, + (q31_t)0x7f7e648c, (q31_t)0xf4a07261, (q31_t)0x7f7dd579, (q31_t)0xf49a3042, (q31_t)0x7f7d4617, (q31_t)0xf493ee2b, (q31_t)0x7f7cb667, (q31_t)0xf48dac1a, + (q31_t)0x7f7c2668, (q31_t)0xf4876a10, (q31_t)0x7f7b961b, (q31_t)0xf481280e, (q31_t)0x7f7b057e, (q31_t)0xf47ae613, (q31_t)0x7f7a7494, (q31_t)0xf474a41f, + (q31_t)0x7f79e35a, (q31_t)0xf46e6231, (q31_t)0x7f7951d2, (q31_t)0xf468204b, (q31_t)0x7f78bffb, (q31_t)0xf461de6d, (q31_t)0x7f782dd6, (q31_t)0xf45b9c95, + (q31_t)0x7f779b62, (q31_t)0xf4555ac5, (q31_t)0x7f77089f, (q31_t)0xf44f18fb, (q31_t)0x7f76758e, (q31_t)0xf448d739, (q31_t)0x7f75e22e, (q31_t)0xf442957e, + (q31_t)0x7f754e80, (q31_t)0xf43c53cb, (q31_t)0x7f74ba83, (q31_t)0xf436121e, (q31_t)0x7f742637, (q31_t)0xf42fd079, (q31_t)0x7f73919d, (q31_t)0xf4298edc, + (q31_t)0x7f72fcb4, (q31_t)0xf4234d45, (q31_t)0x7f72677c, (q31_t)0xf41d0bb6, (q31_t)0x7f71d1f6, (q31_t)0xf416ca2e, (q31_t)0x7f713c21, (q31_t)0xf41088ae, + (q31_t)0x7f70a5fe, (q31_t)0xf40a4735, (q31_t)0x7f700f8c, (q31_t)0xf40405c3, (q31_t)0x7f6f78cb, (q31_t)0xf3fdc459, (q31_t)0x7f6ee1bc, (q31_t)0xf3f782f6, + (q31_t)0x7f6e4a5e, (q31_t)0xf3f1419a, (q31_t)0x7f6db2b1, (q31_t)0xf3eb0046, (q31_t)0x7f6d1ab6, (q31_t)0xf3e4bef9, (q31_t)0x7f6c826d, (q31_t)0xf3de7db4, + (q31_t)0x7f6be9d4, (q31_t)0xf3d83c77, (q31_t)0x7f6b50ed, (q31_t)0xf3d1fb40, (q31_t)0x7f6ab7b8, (q31_t)0xf3cbba12, (q31_t)0x7f6a1e34, (q31_t)0xf3c578eb, + (q31_t)0x7f698461, (q31_t)0xf3bf37cb, (q31_t)0x7f68ea40, (q31_t)0xf3b8f6b3, (q31_t)0x7f684fd0, (q31_t)0xf3b2b5a3, (q31_t)0x7f67b512, (q31_t)0xf3ac749a, + (q31_t)0x7f671a05, (q31_t)0xf3a63398, (q31_t)0x7f667ea9, (q31_t)0xf39ff29f, (q31_t)0x7f65e2ff, (q31_t)0xf399b1ad, (q31_t)0x7f654706, (q31_t)0xf39370c2, + (q31_t)0x7f64aabf, (q31_t)0xf38d2fe0, (q31_t)0x7f640e29, (q31_t)0xf386ef05, (q31_t)0x7f637144, (q31_t)0xf380ae31, (q31_t)0x7f62d411, (q31_t)0xf37a6d66, + (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f6198bf, (q31_t)0xf36debe6, (q31_t)0x7f60faa0, (q31_t)0xf367ab31, (q31_t)0x7f605c33, (q31_t)0xf3616a85, + (q31_t)0x7f5fbd77, (q31_t)0xf35b29e0, (q31_t)0x7f5f1e6c, (q31_t)0xf354e943, (q31_t)0x7f5e7f13, (q31_t)0xf34ea8ae, (q31_t)0x7f5ddf6b, (q31_t)0xf3486820, + (q31_t)0x7f5d3f75, (q31_t)0xf342279b, (q31_t)0x7f5c9f30, (q31_t)0xf33be71d, (q31_t)0x7f5bfe9d, (q31_t)0xf335a6a7, (q31_t)0x7f5b5dbb, (q31_t)0xf32f6639, + (q31_t)0x7f5abc8a, (q31_t)0xf32925d3, (q31_t)0x7f5a1b0b, (q31_t)0xf322e575, (q31_t)0x7f59793e, (q31_t)0xf31ca51f, (q31_t)0x7f58d721, (q31_t)0xf31664d1, + (q31_t)0x7f5834b7, (q31_t)0xf310248a, (q31_t)0x7f5791fd, (q31_t)0xf309e44c, (q31_t)0x7f56eef5, (q31_t)0xf303a416, (q31_t)0x7f564b9f, (q31_t)0xf2fd63e8, + (q31_t)0x7f55a7fa, (q31_t)0xf2f723c1, (q31_t)0x7f550407, (q31_t)0xf2f0e3a3, (q31_t)0x7f545fc5, (q31_t)0xf2eaa38d, (q31_t)0x7f53bb34, (q31_t)0xf2e4637f, + (q31_t)0x7f531655, (q31_t)0xf2de2379, (q31_t)0x7f527127, (q31_t)0xf2d7e37b, (q31_t)0x7f51cbab, (q31_t)0xf2d1a385, (q31_t)0x7f5125e0, (q31_t)0xf2cb6398, + (q31_t)0x7f507fc7, (q31_t)0xf2c523b2, (q31_t)0x7f4fd95f, (q31_t)0xf2bee3d5, (q31_t)0x7f4f32a9, (q31_t)0xf2b8a400, (q31_t)0x7f4e8ba4, (q31_t)0xf2b26433, + (q31_t)0x7f4de451, (q31_t)0xf2ac246e, (q31_t)0x7f4d3caf, (q31_t)0xf2a5e4b1, (q31_t)0x7f4c94be, (q31_t)0xf29fa4fd, (q31_t)0x7f4bec7f, (q31_t)0xf2996551, + (q31_t)0x7f4b43f2, (q31_t)0xf29325ad, (q31_t)0x7f4a9b16, (q31_t)0xf28ce612, (q31_t)0x7f49f1eb, (q31_t)0xf286a67e, (q31_t)0x7f494872, (q31_t)0xf28066f4, + (q31_t)0x7f489eaa, (q31_t)0xf27a2771, (q31_t)0x7f47f494, (q31_t)0xf273e7f7, (q31_t)0x7f474a30, (q31_t)0xf26da885, (q31_t)0x7f469f7d, (q31_t)0xf267691b, + (q31_t)0x7f45f47b, (q31_t)0xf26129ba, (q31_t)0x7f45492b, (q31_t)0xf25aea61, (q31_t)0x7f449d8c, (q31_t)0xf254ab11, (q31_t)0x7f43f19f, (q31_t)0xf24e6bc9, + (q31_t)0x7f434563, (q31_t)0xf2482c8a, (q31_t)0x7f4298d9, (q31_t)0xf241ed53, (q31_t)0x7f41ec01, (q31_t)0xf23bae24, (q31_t)0x7f413ed9, (q31_t)0xf2356efe, + (q31_t)0x7f409164, (q31_t)0xf22f2fe1, (q31_t)0x7f3fe3a0, (q31_t)0xf228f0cc, (q31_t)0x7f3f358d, (q31_t)0xf222b1c0, (q31_t)0x7f3e872c, (q31_t)0xf21c72bc, + (q31_t)0x7f3dd87c, (q31_t)0xf21633c0, (q31_t)0x7f3d297e, (q31_t)0xf20ff4ce, (q31_t)0x7f3c7a31, (q31_t)0xf209b5e4, (q31_t)0x7f3bca96, (q31_t)0xf2037702, + (q31_t)0x7f3b1aad, (q31_t)0xf1fd3829, (q31_t)0x7f3a6a75, (q31_t)0xf1f6f959, (q31_t)0x7f39b9ee, (q31_t)0xf1f0ba91, (q31_t)0x7f390919, (q31_t)0xf1ea7bd2, + (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f37a684, (q31_t)0xf1ddfe6f, (q31_t)0x7f36f4c3, (q31_t)0xf1d7bfca, (q31_t)0x7f3642b4, (q31_t)0xf1d1812e, + (q31_t)0x7f359057, (q31_t)0xf1cb429a, (q31_t)0x7f34ddab, (q31_t)0xf1c50410, (q31_t)0x7f342ab1, (q31_t)0xf1bec58e, (q31_t)0x7f337768, (q31_t)0xf1b88715, + (q31_t)0x7f32c3d1, (q31_t)0xf1b248a5, (q31_t)0x7f320feb, (q31_t)0xf1ac0a3e, (q31_t)0x7f315bb7, (q31_t)0xf1a5cbdf, (q31_t)0x7f30a734, (q31_t)0xf19f8d89, + (q31_t)0x7f2ff263, (q31_t)0xf1994f3d, (q31_t)0x7f2f3d44, (q31_t)0xf19310f9, (q31_t)0x7f2e87d6, (q31_t)0xf18cd2be, (q31_t)0x7f2dd219, (q31_t)0xf186948c, + (q31_t)0x7f2d1c0e, (q31_t)0xf1805662, (q31_t)0x7f2c65b5, (q31_t)0xf17a1842, (q31_t)0x7f2baf0d, (q31_t)0xf173da2b, (q31_t)0x7f2af817, (q31_t)0xf16d9c1d, + (q31_t)0x7f2a40d2, (q31_t)0xf1675e17, (q31_t)0x7f29893f, (q31_t)0xf161201b, (q31_t)0x7f28d15d, (q31_t)0xf15ae228, (q31_t)0x7f28192d, (q31_t)0xf154a43d, + (q31_t)0x7f2760af, (q31_t)0xf14e665c, (q31_t)0x7f26a7e2, (q31_t)0xf1482884, (q31_t)0x7f25eec7, (q31_t)0xf141eab5, (q31_t)0x7f25355d, (q31_t)0xf13bacef, + (q31_t)0x7f247ba5, (q31_t)0xf1356f32, (q31_t)0x7f23c19e, (q31_t)0xf12f317e, (q31_t)0x7f230749, (q31_t)0xf128f3d4, (q31_t)0x7f224ca6, (q31_t)0xf122b632, + (q31_t)0x7f2191b4, (q31_t)0xf11c789a, (q31_t)0x7f20d674, (q31_t)0xf1163b0b, (q31_t)0x7f201ae5, (q31_t)0xf10ffd85, (q31_t)0x7f1f5f08, (q31_t)0xf109c009, + (q31_t)0x7f1ea2dc, (q31_t)0xf1038295, (q31_t)0x7f1de662, (q31_t)0xf0fd452b, (q31_t)0x7f1d299a, (q31_t)0xf0f707ca, (q31_t)0x7f1c6c83, (q31_t)0xf0f0ca72, + (q31_t)0x7f1baf1e, (q31_t)0xf0ea8d24, (q31_t)0x7f1af16a, (q31_t)0xf0e44fdf, (q31_t)0x7f1a3368, (q31_t)0xf0de12a3, (q31_t)0x7f197518, (q31_t)0xf0d7d571, + (q31_t)0x7f18b679, (q31_t)0xf0d19848, (q31_t)0x7f17f78c, (q31_t)0xf0cb5b28, (q31_t)0x7f173850, (q31_t)0xf0c51e12, (q31_t)0x7f1678c6, (q31_t)0xf0bee105, + (q31_t)0x7f15b8ee, (q31_t)0xf0b8a401, (q31_t)0x7f14f8c7, (q31_t)0xf0b26707, (q31_t)0x7f143852, (q31_t)0xf0ac2a16, (q31_t)0x7f13778e, (q31_t)0xf0a5ed2f, + (q31_t)0x7f12b67c, (q31_t)0xf09fb051, (q31_t)0x7f11f51c, (q31_t)0xf099737d, (q31_t)0x7f11336d, (q31_t)0xf09336b2, (q31_t)0x7f107170, (q31_t)0xf08cf9f1, + (q31_t)0x7f0faf25, (q31_t)0xf086bd39, (q31_t)0x7f0eec8b, (q31_t)0xf080808b, (q31_t)0x7f0e29a3, (q31_t)0xf07a43e7, (q31_t)0x7f0d666c, (q31_t)0xf074074c, + (q31_t)0x7f0ca2e7, (q31_t)0xf06dcaba, (q31_t)0x7f0bdf14, (q31_t)0xf0678e32, (q31_t)0x7f0b1af2, (q31_t)0xf06151b4, (q31_t)0x7f0a5682, (q31_t)0xf05b1540, + (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7f08ccb7, (q31_t)0xf04e9c73, (q31_t)0x7f08075c, (q31_t)0xf048601c, (q31_t)0x7f0741b2, (q31_t)0xf04223ce, + (q31_t)0x7f067bba, (q31_t)0xf03be78a, (q31_t)0x7f05b574, (q31_t)0xf035ab4f, (q31_t)0x7f04eedf, (q31_t)0xf02f6f1f, (q31_t)0x7f0427fc, (q31_t)0xf02932f8, + (q31_t)0x7f0360cb, (q31_t)0xf022f6da, (q31_t)0x7f02994b, (q31_t)0xf01cbac7, (q31_t)0x7f01d17d, (q31_t)0xf0167ebd, (q31_t)0x7f010961, (q31_t)0xf01042be, + (q31_t)0x7f0040f6, (q31_t)0xf00a06c8, (q31_t)0x7eff783d, (q31_t)0xf003cadc, (q31_t)0x7efeaf36, (q31_t)0xeffd8ef9, (q31_t)0x7efde5e0, (q31_t)0xeff75321, + (q31_t)0x7efd1c3c, (q31_t)0xeff11753, (q31_t)0x7efc524a, (q31_t)0xefeadb8e, (q31_t)0x7efb8809, (q31_t)0xefe49fd3, (q31_t)0x7efabd7a, (q31_t)0xefde6423, + (q31_t)0x7ef9f29d, (q31_t)0xefd8287c, (q31_t)0x7ef92771, (q31_t)0xefd1ecdf, (q31_t)0x7ef85bf7, (q31_t)0xefcbb14c, (q31_t)0x7ef7902f, (q31_t)0xefc575c3, + (q31_t)0x7ef6c418, (q31_t)0xefbf3a45, (q31_t)0x7ef5f7b3, (q31_t)0xefb8fed0, (q31_t)0x7ef52b00, (q31_t)0xefb2c365, (q31_t)0x7ef45dfe, (q31_t)0xefac8804, + (q31_t)0x7ef390ae, (q31_t)0xefa64cae, (q31_t)0x7ef2c310, (q31_t)0xefa01161, (q31_t)0x7ef1f524, (q31_t)0xef99d61f, (q31_t)0x7ef126e9, (q31_t)0xef939ae6, + (q31_t)0x7ef05860, (q31_t)0xef8d5fb8, (q31_t)0x7eef8988, (q31_t)0xef872494, (q31_t)0x7eeeba62, (q31_t)0xef80e97a, (q31_t)0x7eedeaee, (q31_t)0xef7aae6b, + (q31_t)0x7eed1b2c, (q31_t)0xef747365, (q31_t)0x7eec4b1b, (q31_t)0xef6e386a, (q31_t)0x7eeb7abc, (q31_t)0xef67fd79, (q31_t)0x7eeaaa0f, (q31_t)0xef61c292, + (q31_t)0x7ee9d914, (q31_t)0xef5b87b5, (q31_t)0x7ee907ca, (q31_t)0xef554ce3, (q31_t)0x7ee83632, (q31_t)0xef4f121b, (q31_t)0x7ee7644c, (q31_t)0xef48d75d, + (q31_t)0x7ee69217, (q31_t)0xef429caa, (q31_t)0x7ee5bf94, (q31_t)0xef3c6201, (q31_t)0x7ee4ecc3, (q31_t)0xef362762, (q31_t)0x7ee419a3, (q31_t)0xef2feccd, + (q31_t)0x7ee34636, (q31_t)0xef29b243, (q31_t)0x7ee2727a, (q31_t)0xef2377c4, (q31_t)0x7ee19e6f, (q31_t)0xef1d3d4e, (q31_t)0x7ee0ca17, (q31_t)0xef1702e4, + (q31_t)0x7edff570, (q31_t)0xef10c883, (q31_t)0x7edf207b, (q31_t)0xef0a8e2d, (q31_t)0x7ede4b38, (q31_t)0xef0453e2, (q31_t)0x7edd75a6, (q31_t)0xeefe19a1, + (q31_t)0x7edc9fc6, (q31_t)0xeef7df6a, (q31_t)0x7edbc998, (q31_t)0xeef1a53e, (q31_t)0x7edaf31c, (q31_t)0xeeeb6b1c, (q31_t)0x7eda1c51, (q31_t)0xeee53105, + (q31_t)0x7ed94538, (q31_t)0xeedef6f9, (q31_t)0x7ed86dd1, (q31_t)0xeed8bcf7, (q31_t)0x7ed7961c, (q31_t)0xeed28300, (q31_t)0x7ed6be18, (q31_t)0xeecc4913, + (q31_t)0x7ed5e5c6, (q31_t)0xeec60f31, (q31_t)0x7ed50d26, (q31_t)0xeebfd55a, (q31_t)0x7ed43438, (q31_t)0xeeb99b8d, (q31_t)0x7ed35afb, (q31_t)0xeeb361cb, + (q31_t)0x7ed28171, (q31_t)0xeead2813, (q31_t)0x7ed1a798, (q31_t)0xeea6ee66, (q31_t)0x7ed0cd70, (q31_t)0xeea0b4c4, (q31_t)0x7ecff2fb, (q31_t)0xee9a7b2d, + (q31_t)0x7ecf1837, (q31_t)0xee9441a0, (q31_t)0x7ece3d25, (q31_t)0xee8e081e, (q31_t)0x7ecd61c5, (q31_t)0xee87cea7, (q31_t)0x7ecc8617, (q31_t)0xee81953b, + (q31_t)0x7ecbaa1a, (q31_t)0xee7b5bd9, (q31_t)0x7ecacdd0, (q31_t)0xee752283, (q31_t)0x7ec9f137, (q31_t)0xee6ee937, (q31_t)0x7ec9144f, (q31_t)0xee68aff6, + (q31_t)0x7ec8371a, (q31_t)0xee6276bf, (q31_t)0x7ec75996, (q31_t)0xee5c3d94, (q31_t)0x7ec67bc5, (q31_t)0xee560473, (q31_t)0x7ec59da5, (q31_t)0xee4fcb5e, + (q31_t)0x7ec4bf36, (q31_t)0xee499253, (q31_t)0x7ec3e07a, (q31_t)0xee435953, (q31_t)0x7ec3016f, (q31_t)0xee3d205e, (q31_t)0x7ec22217, (q31_t)0xee36e775, + (q31_t)0x7ec14270, (q31_t)0xee30ae96, (q31_t)0x7ec0627a, (q31_t)0xee2a75c2, (q31_t)0x7ebf8237, (q31_t)0xee243cf9, (q31_t)0x7ebea1a6, (q31_t)0xee1e043b, + (q31_t)0x7ebdc0c6, (q31_t)0xee17cb88, (q31_t)0x7ebcdf98, (q31_t)0xee1192e0, (q31_t)0x7ebbfe1c, (q31_t)0xee0b5a43, (q31_t)0x7ebb1c52, (q31_t)0xee0521b2, + (q31_t)0x7eba3a39, (q31_t)0xedfee92b, (q31_t)0x7eb957d2, (q31_t)0xedf8b0b0, (q31_t)0x7eb8751e, (q31_t)0xedf2783f, (q31_t)0x7eb7921b, (q31_t)0xedec3fda, + (q31_t)0x7eb6aeca, (q31_t)0xede60780, (q31_t)0x7eb5cb2a, (q31_t)0xeddfcf31, (q31_t)0x7eb4e73d, (q31_t)0xedd996ed, (q31_t)0x7eb40301, (q31_t)0xedd35eb5, + (q31_t)0x7eb31e78, (q31_t)0xedcd2687, (q31_t)0x7eb239a0, (q31_t)0xedc6ee65, (q31_t)0x7eb1547a, (q31_t)0xedc0b64e, (q31_t)0x7eb06f05, (q31_t)0xedba7e43, + (q31_t)0x7eaf8943, (q31_t)0xedb44642, (q31_t)0x7eaea333, (q31_t)0xedae0e4d, (q31_t)0x7eadbcd4, (q31_t)0xeda7d664, (q31_t)0x7eacd627, (q31_t)0xeda19e85, + (q31_t)0x7eabef2c, (q31_t)0xed9b66b2, (q31_t)0x7eab07e3, (q31_t)0xed952eea, (q31_t)0x7eaa204c, (q31_t)0xed8ef72e, (q31_t)0x7ea93867, (q31_t)0xed88bf7d, + (q31_t)0x7ea85033, (q31_t)0xed8287d7, (q31_t)0x7ea767b2, (q31_t)0xed7c503d, (q31_t)0x7ea67ee2, (q31_t)0xed7618ae, (q31_t)0x7ea595c4, (q31_t)0xed6fe12b, + (q31_t)0x7ea4ac58, (q31_t)0xed69a9b3, (q31_t)0x7ea3c29e, (q31_t)0xed637246, (q31_t)0x7ea2d896, (q31_t)0xed5d3ae5, (q31_t)0x7ea1ee3f, (q31_t)0xed570390, + (q31_t)0x7ea1039b, (q31_t)0xed50cc46, (q31_t)0x7ea018a8, (q31_t)0xed4a9507, (q31_t)0x7e9f2d68, (q31_t)0xed445dd5, (q31_t)0x7e9e41d9, (q31_t)0xed3e26ad, + (q31_t)0x7e9d55fc, (q31_t)0xed37ef91, (q31_t)0x7e9c69d1, (q31_t)0xed31b881, (q31_t)0x7e9b7d58, (q31_t)0xed2b817d, (q31_t)0x7e9a9091, (q31_t)0xed254a84, + (q31_t)0x7e99a37c, (q31_t)0xed1f1396, (q31_t)0x7e98b618, (q31_t)0xed18dcb5, (q31_t)0x7e97c867, (q31_t)0xed12a5df, (q31_t)0x7e96da67, (q31_t)0xed0c6f14, + (q31_t)0x7e95ec1a, (q31_t)0xed063856, (q31_t)0x7e94fd7e, (q31_t)0xed0001a3, (q31_t)0x7e940e94, (q31_t)0xecf9cafb, (q31_t)0x7e931f5c, (q31_t)0xecf39460, + (q31_t)0x7e922fd6, (q31_t)0xeced5dd0, (q31_t)0x7e914002, (q31_t)0xece7274c, (q31_t)0x7e904fe0, (q31_t)0xece0f0d4, (q31_t)0x7e8f5f70, (q31_t)0xecdaba67, + (q31_t)0x7e8e6eb2, (q31_t)0xecd48407, (q31_t)0x7e8d7da6, (q31_t)0xecce4db2, (q31_t)0x7e8c8c4b, (q31_t)0xecc81769, (q31_t)0x7e8b9aa3, (q31_t)0xecc1e12c, + (q31_t)0x7e8aa8ac, (q31_t)0xecbbaafb, (q31_t)0x7e89b668, (q31_t)0xecb574d5, (q31_t)0x7e88c3d5, (q31_t)0xecaf3ebc, (q31_t)0x7e87d0f5, (q31_t)0xeca908ae, + (q31_t)0x7e86ddc6, (q31_t)0xeca2d2ad, (q31_t)0x7e85ea49, (q31_t)0xec9c9cb7, (q31_t)0x7e84f67e, (q31_t)0xec9666cd, (q31_t)0x7e840265, (q31_t)0xec9030f0, + (q31_t)0x7e830dff, (q31_t)0xec89fb1e, (q31_t)0x7e82194a, (q31_t)0xec83c558, (q31_t)0x7e812447, (q31_t)0xec7d8f9e, (q31_t)0x7e802ef6, (q31_t)0xec7759f1, + (q31_t)0x7e7f3957, (q31_t)0xec71244f, (q31_t)0x7e7e436a, (q31_t)0xec6aeeba, (q31_t)0x7e7d4d2f, (q31_t)0xec64b930, (q31_t)0x7e7c56a5, (q31_t)0xec5e83b3, + (q31_t)0x7e7b5fce, (q31_t)0xec584e41, (q31_t)0x7e7a68a9, (q31_t)0xec5218dc, (q31_t)0x7e797136, (q31_t)0xec4be383, (q31_t)0x7e787975, (q31_t)0xec45ae36, + (q31_t)0x7e778166, (q31_t)0xec3f78f6, (q31_t)0x7e768908, (q31_t)0xec3943c1, (q31_t)0x7e75905d, (q31_t)0xec330e99, (q31_t)0x7e749764, (q31_t)0xec2cd97d, + (q31_t)0x7e739e1d, (q31_t)0xec26a46d, (q31_t)0x7e72a488, (q31_t)0xec206f69, (q31_t)0x7e71aaa4, (q31_t)0xec1a3a72, (q31_t)0x7e70b073, (q31_t)0xec140587, + (q31_t)0x7e6fb5f4, (q31_t)0xec0dd0a8, (q31_t)0x7e6ebb27, (q31_t)0xec079bd6, (q31_t)0x7e6dc00c, (q31_t)0xec01670f, (q31_t)0x7e6cc4a2, (q31_t)0xebfb3256, + (q31_t)0x7e6bc8eb, (q31_t)0xebf4fda8, (q31_t)0x7e6acce6, (q31_t)0xebeec907, (q31_t)0x7e69d093, (q31_t)0xebe89472, (q31_t)0x7e68d3f2, (q31_t)0xebe25fea, + (q31_t)0x7e67d703, (q31_t)0xebdc2b6e, (q31_t)0x7e66d9c6, (q31_t)0xebd5f6fe, (q31_t)0x7e65dc3b, (q31_t)0xebcfc29b, (q31_t)0x7e64de62, (q31_t)0xebc98e45, + (q31_t)0x7e63e03b, (q31_t)0xebc359fb, (q31_t)0x7e62e1c6, (q31_t)0xebbd25bd, (q31_t)0x7e61e303, (q31_t)0xebb6f18c, (q31_t)0x7e60e3f2, (q31_t)0xebb0bd67, + (q31_t)0x7e5fe493, (q31_t)0xebaa894f, (q31_t)0x7e5ee4e6, (q31_t)0xeba45543, (q31_t)0x7e5de4ec, (q31_t)0xeb9e2144, (q31_t)0x7e5ce4a3, (q31_t)0xeb97ed52, + (q31_t)0x7e5be40c, (q31_t)0xeb91b96c, (q31_t)0x7e5ae328, (q31_t)0xeb8b8593, (q31_t)0x7e59e1f5, (q31_t)0xeb8551c6, (q31_t)0x7e58e075, (q31_t)0xeb7f1e06, + (q31_t)0x7e57dea7, (q31_t)0xeb78ea52, (q31_t)0x7e56dc8a, (q31_t)0xeb72b6ac, (q31_t)0x7e55da20, (q31_t)0xeb6c8312, (q31_t)0x7e54d768, (q31_t)0xeb664f84, + (q31_t)0x7e53d462, (q31_t)0xeb601c04, (q31_t)0x7e52d10e, (q31_t)0xeb59e890, (q31_t)0x7e51cd6c, (q31_t)0xeb53b529, (q31_t)0x7e50c97c, (q31_t)0xeb4d81ce, + (q31_t)0x7e4fc53e, (q31_t)0xeb474e81, (q31_t)0x7e4ec0b2, (q31_t)0xeb411b40, (q31_t)0x7e4dbbd9, (q31_t)0xeb3ae80c, (q31_t)0x7e4cb6b1, (q31_t)0xeb34b4e4, + (q31_t)0x7e4bb13c, (q31_t)0xeb2e81ca, (q31_t)0x7e4aab78, (q31_t)0xeb284ebc, (q31_t)0x7e49a567, (q31_t)0xeb221bbb, (q31_t)0x7e489f08, (q31_t)0xeb1be8c8, + (q31_t)0x7e47985b, (q31_t)0xeb15b5e1, (q31_t)0x7e469160, (q31_t)0xeb0f8307, (q31_t)0x7e458a17, (q31_t)0xeb095039, (q31_t)0x7e448281, (q31_t)0xeb031d79, + (q31_t)0x7e437a9c, (q31_t)0xeafceac6, (q31_t)0x7e427269, (q31_t)0xeaf6b81f, (q31_t)0x7e4169e9, (q31_t)0xeaf08586, (q31_t)0x7e40611b, (q31_t)0xeaea52fa, + (q31_t)0x7e3f57ff, (q31_t)0xeae4207a, (q31_t)0x7e3e4e95, (q31_t)0xeaddee08, (q31_t)0x7e3d44dd, (q31_t)0xead7bba3, (q31_t)0x7e3c3ad7, (q31_t)0xead1894b, + (q31_t)0x7e3b3083, (q31_t)0xeacb56ff, (q31_t)0x7e3a25e2, (q31_t)0xeac524c1, (q31_t)0x7e391af3, (q31_t)0xeabef290, (q31_t)0x7e380fb5, (q31_t)0xeab8c06c, + (q31_t)0x7e37042a, (q31_t)0xeab28e56, (q31_t)0x7e35f851, (q31_t)0xeaac5c4c, (q31_t)0x7e34ec2b, (q31_t)0xeaa62a4f, (q31_t)0x7e33dfb6, (q31_t)0xea9ff860, + (q31_t)0x7e32d2f4, (q31_t)0xea99c67e, (q31_t)0x7e31c5e3, (q31_t)0xea9394a9, (q31_t)0x7e30b885, (q31_t)0xea8d62e1, (q31_t)0x7e2faad9, (q31_t)0xea873127, + (q31_t)0x7e2e9cdf, (q31_t)0xea80ff7a, (q31_t)0x7e2d8e97, (q31_t)0xea7acdda, (q31_t)0x7e2c8002, (q31_t)0xea749c47, (q31_t)0x7e2b711f, (q31_t)0xea6e6ac2, + (q31_t)0x7e2a61ed, (q31_t)0xea683949, (q31_t)0x7e29526e, (q31_t)0xea6207df, (q31_t)0x7e2842a2, (q31_t)0xea5bd681, (q31_t)0x7e273287, (q31_t)0xea55a531, + (q31_t)0x7e26221f, (q31_t)0xea4f73ee, (q31_t)0x7e251168, (q31_t)0xea4942b9, (q31_t)0x7e240064, (q31_t)0xea431191, (q31_t)0x7e22ef12, (q31_t)0xea3ce077, + (q31_t)0x7e21dd73, (q31_t)0xea36af69, (q31_t)0x7e20cb85, (q31_t)0xea307e6a, (q31_t)0x7e1fb94a, (q31_t)0xea2a4d78, (q31_t)0x7e1ea6c1, (q31_t)0xea241c93, + (q31_t)0x7e1d93ea, (q31_t)0xea1debbb, (q31_t)0x7e1c80c5, (q31_t)0xea17baf2, (q31_t)0x7e1b6d53, (q31_t)0xea118a35, (q31_t)0x7e1a5992, (q31_t)0xea0b5987, + (q31_t)0x7e194584, (q31_t)0xea0528e5, (q31_t)0x7e183128, (q31_t)0xe9fef852, (q31_t)0x7e171c7f, (q31_t)0xe9f8c7cc, (q31_t)0x7e160787, (q31_t)0xe9f29753, + (q31_t)0x7e14f242, (q31_t)0xe9ec66e8, (q31_t)0x7e13dcaf, (q31_t)0xe9e6368b, (q31_t)0x7e12c6ce, (q31_t)0xe9e0063c, (q31_t)0x7e11b0a0, (q31_t)0xe9d9d5fa, + (q31_t)0x7e109a24, (q31_t)0xe9d3a5c5, (q31_t)0x7e0f835a, (q31_t)0xe9cd759f, (q31_t)0x7e0e6c42, (q31_t)0xe9c74586, (q31_t)0x7e0d54dc, (q31_t)0xe9c1157a, + (q31_t)0x7e0c3d29, (q31_t)0xe9bae57d, (q31_t)0x7e0b2528, (q31_t)0xe9b4b58d, (q31_t)0x7e0a0cd9, (q31_t)0xe9ae85ab, (q31_t)0x7e08f43d, (q31_t)0xe9a855d7, + (q31_t)0x7e07db52, (q31_t)0xe9a22610, (q31_t)0x7e06c21a, (q31_t)0xe99bf658, (q31_t)0x7e05a894, (q31_t)0xe995c6ad, (q31_t)0x7e048ec1, (q31_t)0xe98f9710, + (q31_t)0x7e0374a0, (q31_t)0xe9896781, (q31_t)0x7e025a31, (q31_t)0xe98337ff, (q31_t)0x7e013f74, (q31_t)0xe97d088c, (q31_t)0x7e00246a, (q31_t)0xe976d926, + (q31_t)0x7dff0911, (q31_t)0xe970a9ce, (q31_t)0x7dfded6c, (q31_t)0xe96a7a85, (q31_t)0x7dfcd178, (q31_t)0xe9644b49, (q31_t)0x7dfbb537, (q31_t)0xe95e1c1b, + (q31_t)0x7dfa98a8, (q31_t)0xe957ecfb, (q31_t)0x7df97bcb, (q31_t)0xe951bde9, (q31_t)0x7df85ea0, (q31_t)0xe94b8ee5, (q31_t)0x7df74128, (q31_t)0xe9455fef, + (q31_t)0x7df62362, (q31_t)0xe93f3107, (q31_t)0x7df5054f, (q31_t)0xe939022d, (q31_t)0x7df3e6ee, (q31_t)0xe932d361, (q31_t)0x7df2c83f, (q31_t)0xe92ca4a4, + (q31_t)0x7df1a942, (q31_t)0xe92675f4, (q31_t)0x7df089f8, (q31_t)0xe9204752, (q31_t)0x7def6a60, (q31_t)0xe91a18bf, (q31_t)0x7dee4a7a, (q31_t)0xe913ea39, + (q31_t)0x7ded2a47, (q31_t)0xe90dbbc2, (q31_t)0x7dec09c6, (q31_t)0xe9078d59, (q31_t)0x7deae8f7, (q31_t)0xe9015efe, (q31_t)0x7de9c7da, (q31_t)0xe8fb30b1, + (q31_t)0x7de8a670, (q31_t)0xe8f50273, (q31_t)0x7de784b9, (q31_t)0xe8eed443, (q31_t)0x7de662b3, (q31_t)0xe8e8a621, (q31_t)0x7de54060, (q31_t)0xe8e2780d, + (q31_t)0x7de41dc0, (q31_t)0xe8dc4a07, (q31_t)0x7de2fad1, (q31_t)0xe8d61c10, (q31_t)0x7de1d795, (q31_t)0xe8cfee27, (q31_t)0x7de0b40b, (q31_t)0xe8c9c04c, + (q31_t)0x7ddf9034, (q31_t)0xe8c39280, (q31_t)0x7dde6c0f, (q31_t)0xe8bd64c2, (q31_t)0x7ddd479d, (q31_t)0xe8b73712, (q31_t)0x7ddc22dc, (q31_t)0xe8b10971, + (q31_t)0x7ddafdce, (q31_t)0xe8aadbde, (q31_t)0x7dd9d873, (q31_t)0xe8a4ae59, (q31_t)0x7dd8b2ca, (q31_t)0xe89e80e3, (q31_t)0x7dd78cd3, (q31_t)0xe898537b, + (q31_t)0x7dd6668f, (q31_t)0xe8922622, (q31_t)0x7dd53ffc, (q31_t)0xe88bf8d7, (q31_t)0x7dd4191d, (q31_t)0xe885cb9a, (q31_t)0x7dd2f1f0, (q31_t)0xe87f9e6c, + (q31_t)0x7dd1ca75, (q31_t)0xe879714d, (q31_t)0x7dd0a2ac, (q31_t)0xe873443c, (q31_t)0x7dcf7a96, (q31_t)0xe86d173a, (q31_t)0x7dce5232, (q31_t)0xe866ea46, + (q31_t)0x7dcd2981, (q31_t)0xe860bd61, (q31_t)0x7dcc0082, (q31_t)0xe85a908a, (q31_t)0x7dcad736, (q31_t)0xe85463c2, (q31_t)0x7dc9ad9c, (q31_t)0xe84e3708, + (q31_t)0x7dc883b4, (q31_t)0xe8480a5d, (q31_t)0x7dc7597f, (q31_t)0xe841ddc1, (q31_t)0x7dc62efc, (q31_t)0xe83bb133, (q31_t)0x7dc5042b, (q31_t)0xe83584b4, + (q31_t)0x7dc3d90d, (q31_t)0xe82f5844, (q31_t)0x7dc2ada2, (q31_t)0xe8292be3, (q31_t)0x7dc181e8, (q31_t)0xe822ff90, (q31_t)0x7dc055e2, (q31_t)0xe81cd34b, + (q31_t)0x7dbf298d, (q31_t)0xe816a716, (q31_t)0x7dbdfceb, (q31_t)0xe8107aef, (q31_t)0x7dbccffc, (q31_t)0xe80a4ed7, (q31_t)0x7dbba2bf, (q31_t)0xe80422ce, + (q31_t)0x7dba7534, (q31_t)0xe7fdf6d4, (q31_t)0x7db9475c, (q31_t)0xe7f7cae8, (q31_t)0x7db81936, (q31_t)0xe7f19f0c, (q31_t)0x7db6eac3, (q31_t)0xe7eb733e, + (q31_t)0x7db5bc02, (q31_t)0xe7e5477f, (q31_t)0x7db48cf4, (q31_t)0xe7df1bcf, (q31_t)0x7db35d98, (q31_t)0xe7d8f02d, (q31_t)0x7db22def, (q31_t)0xe7d2c49b, + (q31_t)0x7db0fdf8, (q31_t)0xe7cc9917, (q31_t)0x7dafcdb3, (q31_t)0xe7c66da3, (q31_t)0x7dae9d21, (q31_t)0xe7c0423d, (q31_t)0x7dad6c42, (q31_t)0xe7ba16e7, + (q31_t)0x7dac3b15, (q31_t)0xe7b3eb9f, (q31_t)0x7dab099a, (q31_t)0xe7adc066, (q31_t)0x7da9d7d2, (q31_t)0xe7a7953d, (q31_t)0x7da8a5bc, (q31_t)0xe7a16a22, + (q31_t)0x7da77359, (q31_t)0xe79b3f16, (q31_t)0x7da640a9, (q31_t)0xe795141a, (q31_t)0x7da50dab, (q31_t)0xe78ee92c, (q31_t)0x7da3da5f, (q31_t)0xe788be4e, + (q31_t)0x7da2a6c6, (q31_t)0xe782937e, (q31_t)0x7da172df, (q31_t)0xe77c68be, (q31_t)0x7da03eab, (q31_t)0xe7763e0d, (q31_t)0x7d9f0a29, (q31_t)0xe770136b, + (q31_t)0x7d9dd55a, (q31_t)0xe769e8d8, (q31_t)0x7d9ca03e, (q31_t)0xe763be55, (q31_t)0x7d9b6ad3, (q31_t)0xe75d93e0, (q31_t)0x7d9a351c, (q31_t)0xe757697b, + (q31_t)0x7d98ff17, (q31_t)0xe7513f25, (q31_t)0x7d97c8c4, (q31_t)0xe74b14de, (q31_t)0x7d969224, (q31_t)0xe744eaa6, (q31_t)0x7d955b37, (q31_t)0xe73ec07e, + (q31_t)0x7d9423fc, (q31_t)0xe7389665, (q31_t)0x7d92ec73, (q31_t)0xe7326c5b, (q31_t)0x7d91b49e, (q31_t)0xe72c4260, (q31_t)0x7d907c7a, (q31_t)0xe7261875, + (q31_t)0x7d8f4409, (q31_t)0xe71fee99, (q31_t)0x7d8e0b4b, (q31_t)0xe719c4cd, (q31_t)0x7d8cd240, (q31_t)0xe7139b10, (q31_t)0x7d8b98e6, (q31_t)0xe70d7162, + (q31_t)0x7d8a5f40, (q31_t)0xe70747c4, (q31_t)0x7d89254c, (q31_t)0xe7011e35, (q31_t)0x7d87eb0a, (q31_t)0xe6faf4b5, (q31_t)0x7d86b07c, (q31_t)0xe6f4cb45, + (q31_t)0x7d85759f, (q31_t)0xe6eea1e4, (q31_t)0x7d843a76, (q31_t)0xe6e87893, (q31_t)0x7d82fefe, (q31_t)0xe6e24f51, (q31_t)0x7d81c33a, (q31_t)0xe6dc261f, + (q31_t)0x7d808728, (q31_t)0xe6d5fcfc, (q31_t)0x7d7f4ac8, (q31_t)0xe6cfd3e9, (q31_t)0x7d7e0e1c, (q31_t)0xe6c9aae5, (q31_t)0x7d7cd121, (q31_t)0xe6c381f1, + (q31_t)0x7d7b93da, (q31_t)0xe6bd590d, (q31_t)0x7d7a5645, (q31_t)0xe6b73038, (q31_t)0x7d791862, (q31_t)0xe6b10772, (q31_t)0x7d77da32, (q31_t)0xe6aadebc, + (q31_t)0x7d769bb5, (q31_t)0xe6a4b616, (q31_t)0x7d755cea, (q31_t)0xe69e8d80, (q31_t)0x7d741dd2, (q31_t)0xe69864f9, (q31_t)0x7d72de6d, (q31_t)0xe6923c82, + (q31_t)0x7d719eba, (q31_t)0xe68c141a, (q31_t)0x7d705eba, (q31_t)0xe685ebc2, (q31_t)0x7d6f1e6c, (q31_t)0xe67fc37a, (q31_t)0x7d6dddd2, (q31_t)0xe6799b42, + (q31_t)0x7d6c9ce9, (q31_t)0xe6737319, (q31_t)0x7d6b5bb4, (q31_t)0xe66d4b01, (q31_t)0x7d6a1a31, (q31_t)0xe66722f7, (q31_t)0x7d68d860, (q31_t)0xe660fafe, + (q31_t)0x7d679642, (q31_t)0xe65ad315, (q31_t)0x7d6653d7, (q31_t)0xe654ab3b, (q31_t)0x7d65111f, (q31_t)0xe64e8371, (q31_t)0x7d63ce19, (q31_t)0xe6485bb7, + (q31_t)0x7d628ac6, (q31_t)0xe642340d, (q31_t)0x7d614725, (q31_t)0xe63c0c73, (q31_t)0x7d600338, (q31_t)0xe635e4e9, (q31_t)0x7d5ebefc, (q31_t)0xe62fbd6e, + (q31_t)0x7d5d7a74, (q31_t)0xe6299604, (q31_t)0x7d5c359e, (q31_t)0xe6236ea9, (q31_t)0x7d5af07b, (q31_t)0xe61d475e, (q31_t)0x7d59ab0a, (q31_t)0xe6172024, + (q31_t)0x7d58654d, (q31_t)0xe610f8f9, (q31_t)0x7d571f41, (q31_t)0xe60ad1de, (q31_t)0x7d55d8e9, (q31_t)0xe604aad4, (q31_t)0x7d549243, (q31_t)0xe5fe83d9, + (q31_t)0x7d534b50, (q31_t)0xe5f85cef, (q31_t)0x7d520410, (q31_t)0xe5f23614, (q31_t)0x7d50bc82, (q31_t)0xe5ec0f4a, (q31_t)0x7d4f74a7, (q31_t)0xe5e5e88f, + (q31_t)0x7d4e2c7f, (q31_t)0xe5dfc1e5, (q31_t)0x7d4ce409, (q31_t)0xe5d99b4b, (q31_t)0x7d4b9b46, (q31_t)0xe5d374c1, (q31_t)0x7d4a5236, (q31_t)0xe5cd4e47, + (q31_t)0x7d4908d9, (q31_t)0xe5c727dd, (q31_t)0x7d47bf2e, (q31_t)0xe5c10184, (q31_t)0x7d467536, (q31_t)0xe5badb3a, (q31_t)0x7d452af1, (q31_t)0xe5b4b501, + (q31_t)0x7d43e05e, (q31_t)0xe5ae8ed8, (q31_t)0x7d42957e, (q31_t)0xe5a868bf, (q31_t)0x7d414a51, (q31_t)0xe5a242b7, (q31_t)0x7d3ffed7, (q31_t)0xe59c1cbf, + (q31_t)0x7d3eb30f, (q31_t)0xe595f6d7, (q31_t)0x7d3d66fa, (q31_t)0xe58fd0ff, (q31_t)0x7d3c1a98, (q31_t)0xe589ab38, (q31_t)0x7d3acde9, (q31_t)0xe5838581, + (q31_t)0x7d3980ec, (q31_t)0xe57d5fda, (q31_t)0x7d3833a2, (q31_t)0xe5773a44, (q31_t)0x7d36e60b, (q31_t)0xe57114be, (q31_t)0x7d359827, (q31_t)0xe56aef49, + (q31_t)0x7d3449f5, (q31_t)0xe564c9e3, (q31_t)0x7d32fb76, (q31_t)0xe55ea48f, (q31_t)0x7d31acaa, (q31_t)0xe5587f4a, (q31_t)0x7d305d91, (q31_t)0xe5525a17, + (q31_t)0x7d2f0e2b, (q31_t)0xe54c34f3, (q31_t)0x7d2dbe77, (q31_t)0xe5460fe0, (q31_t)0x7d2c6e76, (q31_t)0xe53feade, (q31_t)0x7d2b1e28, (q31_t)0xe539c5ec, + (q31_t)0x7d29cd8c, (q31_t)0xe533a10a, (q31_t)0x7d287ca4, (q31_t)0xe52d7c39, (q31_t)0x7d272b6e, (q31_t)0xe5275779, (q31_t)0x7d25d9eb, (q31_t)0xe52132c9, + (q31_t)0x7d24881b, (q31_t)0xe51b0e2a, (q31_t)0x7d2335fe, (q31_t)0xe514e99b, (q31_t)0x7d21e393, (q31_t)0xe50ec51d, (q31_t)0x7d2090db, (q31_t)0xe508a0b0, + (q31_t)0x7d1f3dd6, (q31_t)0xe5027c53, (q31_t)0x7d1dea84, (q31_t)0xe4fc5807, (q31_t)0x7d1c96e5, (q31_t)0xe4f633cc, (q31_t)0x7d1b42f9, (q31_t)0xe4f00fa1, + (q31_t)0x7d19eebf, (q31_t)0xe4e9eb87, (q31_t)0x7d189a38, (q31_t)0xe4e3c77d, (q31_t)0x7d174564, (q31_t)0xe4dda385, (q31_t)0x7d15f043, (q31_t)0xe4d77f9d, + (q31_t)0x7d149ad5, (q31_t)0xe4d15bc6, (q31_t)0x7d134519, (q31_t)0xe4cb37ff, (q31_t)0x7d11ef11, (q31_t)0xe4c5144a, (q31_t)0x7d1098bb, (q31_t)0xe4bef0a5, + (q31_t)0x7d0f4218, (q31_t)0xe4b8cd11, (q31_t)0x7d0deb28, (q31_t)0xe4b2a98e, (q31_t)0x7d0c93eb, (q31_t)0xe4ac861b, (q31_t)0x7d0b3c60, (q31_t)0xe4a662ba, + (q31_t)0x7d09e489, (q31_t)0xe4a03f69, (q31_t)0x7d088c64, (q31_t)0xe49a1c29, (q31_t)0x7d0733f3, (q31_t)0xe493f8fb, (q31_t)0x7d05db34, (q31_t)0xe48dd5dd, + (q31_t)0x7d048228, (q31_t)0xe487b2d0, (q31_t)0x7d0328cf, (q31_t)0xe4818fd4, (q31_t)0x7d01cf29, (q31_t)0xe47b6ce9, (q31_t)0x7d007535, (q31_t)0xe4754a0e, + (q31_t)0x7cff1af5, (q31_t)0xe46f2745, (q31_t)0x7cfdc068, (q31_t)0xe469048d, (q31_t)0x7cfc658d, (q31_t)0xe462e1e6, (q31_t)0x7cfb0a65, (q31_t)0xe45cbf50, + (q31_t)0x7cf9aef0, (q31_t)0xe4569ccb, (q31_t)0x7cf8532f, (q31_t)0xe4507a57, (q31_t)0x7cf6f720, (q31_t)0xe44a57f4, (q31_t)0x7cf59ac4, (q31_t)0xe44435a2, + (q31_t)0x7cf43e1a, (q31_t)0xe43e1362, (q31_t)0x7cf2e124, (q31_t)0xe437f132, (q31_t)0x7cf183e1, (q31_t)0xe431cf14, (q31_t)0x7cf02651, (q31_t)0xe42bad07, + (q31_t)0x7ceec873, (q31_t)0xe4258b0a, (q31_t)0x7ced6a49, (q31_t)0xe41f6920, (q31_t)0x7cec0bd1, (q31_t)0xe4194746, (q31_t)0x7ceaad0c, (q31_t)0xe413257d, + (q31_t)0x7ce94dfb, (q31_t)0xe40d03c6, (q31_t)0x7ce7ee9c, (q31_t)0xe406e220, (q31_t)0x7ce68ef0, (q31_t)0xe400c08b, (q31_t)0x7ce52ef7, (q31_t)0xe3fa9f08, + (q31_t)0x7ce3ceb2, (q31_t)0xe3f47d96, (q31_t)0x7ce26e1f, (q31_t)0xe3ee5c35, (q31_t)0x7ce10d3f, (q31_t)0xe3e83ae5, (q31_t)0x7cdfac12, (q31_t)0xe3e219a7, + (q31_t)0x7cde4a98, (q31_t)0xe3dbf87a, (q31_t)0x7cdce8d1, (q31_t)0xe3d5d75e, (q31_t)0x7cdb86bd, (q31_t)0xe3cfb654, (q31_t)0x7cda245c, (q31_t)0xe3c9955b, + (q31_t)0x7cd8c1ae, (q31_t)0xe3c37474, (q31_t)0x7cd75eb3, (q31_t)0xe3bd539e, (q31_t)0x7cd5fb6a, (q31_t)0xe3b732d9, (q31_t)0x7cd497d5, (q31_t)0xe3b11226, + (q31_t)0x7cd333f3, (q31_t)0xe3aaf184, (q31_t)0x7cd1cfc4, (q31_t)0xe3a4d0f4, (q31_t)0x7cd06b48, (q31_t)0xe39eb075, (q31_t)0x7ccf067f, (q31_t)0xe3989008, + (q31_t)0x7ccda169, (q31_t)0xe3926fad, (q31_t)0x7ccc3c06, (q31_t)0xe38c4f63, (q31_t)0x7ccad656, (q31_t)0xe3862f2a, (q31_t)0x7cc97059, (q31_t)0xe3800f03, + (q31_t)0x7cc80a0f, (q31_t)0xe379eeed, (q31_t)0x7cc6a378, (q31_t)0xe373ceea, (q31_t)0x7cc53c94, (q31_t)0xe36daef7, (q31_t)0x7cc3d563, (q31_t)0xe3678f17, + (q31_t)0x7cc26de5, (q31_t)0xe3616f48, (q31_t)0x7cc1061a, (q31_t)0xe35b4f8b, (q31_t)0x7cbf9e03, (q31_t)0xe3552fdf, (q31_t)0x7cbe359e, (q31_t)0xe34f1045, + (q31_t)0x7cbcccec, (q31_t)0xe348f0bd, (q31_t)0x7cbb63ee, (q31_t)0xe342d146, (q31_t)0x7cb9faa2, (q31_t)0xe33cb1e1, (q31_t)0x7cb8910a, (q31_t)0xe336928e, + (q31_t)0x7cb72724, (q31_t)0xe330734d, (q31_t)0x7cb5bcf2, (q31_t)0xe32a541d, (q31_t)0x7cb45272, (q31_t)0xe3243500, (q31_t)0x7cb2e7a6, (q31_t)0xe31e15f4, + (q31_t)0x7cb17c8d, (q31_t)0xe317f6fa, (q31_t)0x7cb01127, (q31_t)0xe311d811, (q31_t)0x7caea574, (q31_t)0xe30bb93b, (q31_t)0x7cad3974, (q31_t)0xe3059a76, + (q31_t)0x7cabcd28, (q31_t)0xe2ff7bc3, (q31_t)0x7caa608e, (q31_t)0xe2f95d23, (q31_t)0x7ca8f3a7, (q31_t)0xe2f33e94, (q31_t)0x7ca78674, (q31_t)0xe2ed2017, + (q31_t)0x7ca618f3, (q31_t)0xe2e701ac, (q31_t)0x7ca4ab26, (q31_t)0xe2e0e352, (q31_t)0x7ca33d0c, (q31_t)0xe2dac50b, (q31_t)0x7ca1cea5, (q31_t)0xe2d4a6d6, + (q31_t)0x7ca05ff1, (q31_t)0xe2ce88b3, (q31_t)0x7c9ef0f0, (q31_t)0xe2c86aa2, (q31_t)0x7c9d81a3, (q31_t)0xe2c24ca2, (q31_t)0x7c9c1208, (q31_t)0xe2bc2eb5, + (q31_t)0x7c9aa221, (q31_t)0xe2b610da, (q31_t)0x7c9931ec, (q31_t)0xe2aff311, (q31_t)0x7c97c16b, (q31_t)0xe2a9d55a, (q31_t)0x7c96509d, (q31_t)0xe2a3b7b5, + (q31_t)0x7c94df83, (q31_t)0xe29d9a23, (q31_t)0x7c936e1b, (q31_t)0xe2977ca2, (q31_t)0x7c91fc66, (q31_t)0xe2915f34, (q31_t)0x7c908a65, (q31_t)0xe28b41d7, + (q31_t)0x7c8f1817, (q31_t)0xe285248d, (q31_t)0x7c8da57c, (q31_t)0xe27f0755, (q31_t)0x7c8c3294, (q31_t)0xe278ea30, (q31_t)0x7c8abf5f, (q31_t)0xe272cd1c, + (q31_t)0x7c894bde, (q31_t)0xe26cb01b, (q31_t)0x7c87d810, (q31_t)0xe266932c, (q31_t)0x7c8663f4, (q31_t)0xe260764f, (q31_t)0x7c84ef8c, (q31_t)0xe25a5984, + (q31_t)0x7c837ad8, (q31_t)0xe2543ccc, (q31_t)0x7c8205d6, (q31_t)0xe24e2026, (q31_t)0x7c809088, (q31_t)0xe2480393, (q31_t)0x7c7f1aed, (q31_t)0xe241e711, + (q31_t)0x7c7da505, (q31_t)0xe23bcaa2, (q31_t)0x7c7c2ed0, (q31_t)0xe235ae46, (q31_t)0x7c7ab84e, (q31_t)0xe22f91fc, (q31_t)0x7c794180, (q31_t)0xe22975c4, + (q31_t)0x7c77ca65, (q31_t)0xe223599e, (q31_t)0x7c7652fd, (q31_t)0xe21d3d8b, (q31_t)0x7c74db48, (q31_t)0xe217218b, (q31_t)0x7c736347, (q31_t)0xe211059d, + (q31_t)0x7c71eaf9, (q31_t)0xe20ae9c1, (q31_t)0x7c70725e, (q31_t)0xe204cdf8, (q31_t)0x7c6ef976, (q31_t)0xe1feb241, (q31_t)0x7c6d8041, (q31_t)0xe1f8969d, + (q31_t)0x7c6c06c0, (q31_t)0xe1f27b0b, (q31_t)0x7c6a8cf2, (q31_t)0xe1ec5f8c, (q31_t)0x7c6912d7, (q31_t)0xe1e64420, (q31_t)0x7c679870, (q31_t)0xe1e028c6, + (q31_t)0x7c661dbc, (q31_t)0xe1da0d7e, (q31_t)0x7c64a2bb, (q31_t)0xe1d3f24a, (q31_t)0x7c63276d, (q31_t)0xe1cdd727, (q31_t)0x7c61abd3, (q31_t)0xe1c7bc18, + (q31_t)0x7c602fec, (q31_t)0xe1c1a11b, (q31_t)0x7c5eb3b8, (q31_t)0xe1bb8631, (q31_t)0x7c5d3737, (q31_t)0xe1b56b59, (q31_t)0x7c5bba6a, (q31_t)0xe1af5094, + (q31_t)0x7c5a3d50, (q31_t)0xe1a935e2, (q31_t)0x7c58bfe9, (q31_t)0xe1a31b42, (q31_t)0x7c574236, (q31_t)0xe19d00b6, (q31_t)0x7c55c436, (q31_t)0xe196e63c, + (q31_t)0x7c5445e9, (q31_t)0xe190cbd4, (q31_t)0x7c52c74f, (q31_t)0xe18ab180, (q31_t)0x7c514869, (q31_t)0xe184973e, (q31_t)0x7c4fc936, (q31_t)0xe17e7d0f, + (q31_t)0x7c4e49b7, (q31_t)0xe17862f3, (q31_t)0x7c4cc9ea, (q31_t)0xe17248ea, (q31_t)0x7c4b49d2, (q31_t)0xe16c2ef4, (q31_t)0x7c49c96c, (q31_t)0xe1661510, + (q31_t)0x7c4848ba, (q31_t)0xe15ffb3f, (q31_t)0x7c46c7bb, (q31_t)0xe159e182, (q31_t)0x7c45466f, (q31_t)0xe153c7d7, (q31_t)0x7c43c4d7, (q31_t)0xe14dae3f, + (q31_t)0x7c4242f2, (q31_t)0xe14794ba, (q31_t)0x7c40c0c1, (q31_t)0xe1417b48, (q31_t)0x7c3f3e42, (q31_t)0xe13b61e9, (q31_t)0x7c3dbb78, (q31_t)0xe135489d, + (q31_t)0x7c3c3860, (q31_t)0xe12f2f63, (q31_t)0x7c3ab4fc, (q31_t)0xe129163d, (q31_t)0x7c39314b, (q31_t)0xe122fd2a, (q31_t)0x7c37ad4e, (q31_t)0xe11ce42a, + (q31_t)0x7c362904, (q31_t)0xe116cb3d, (q31_t)0x7c34a46d, (q31_t)0xe110b263, (q31_t)0x7c331f8a, (q31_t)0xe10a999c, (q31_t)0x7c319a5a, (q31_t)0xe10480e9, + (q31_t)0x7c3014de, (q31_t)0xe0fe6848, (q31_t)0x7c2e8f15, (q31_t)0xe0f84fbb, (q31_t)0x7c2d08ff, (q31_t)0xe0f23740, (q31_t)0x7c2b829d, (q31_t)0xe0ec1ed9, + (q31_t)0x7c29fbee, (q31_t)0xe0e60685, (q31_t)0x7c2874f3, (q31_t)0xe0dfee44, (q31_t)0x7c26edab, (q31_t)0xe0d9d616, (q31_t)0x7c256616, (q31_t)0xe0d3bdfc, + (q31_t)0x7c23de35, (q31_t)0xe0cda5f5, (q31_t)0x7c225607, (q31_t)0xe0c78e01, (q31_t)0x7c20cd8d, (q31_t)0xe0c17620, (q31_t)0x7c1f44c6, (q31_t)0xe0bb5e53, + (q31_t)0x7c1dbbb3, (q31_t)0xe0b54698, (q31_t)0x7c1c3253, (q31_t)0xe0af2ef2, (q31_t)0x7c1aa8a6, (q31_t)0xe0a9175e, (q31_t)0x7c191ead, (q31_t)0xe0a2ffde, + (q31_t)0x7c179467, (q31_t)0xe09ce871, (q31_t)0x7c1609d5, (q31_t)0xe096d117, (q31_t)0x7c147ef6, (q31_t)0xe090b9d1, (q31_t)0x7c12f3cb, (q31_t)0xe08aa29f, + (q31_t)0x7c116853, (q31_t)0xe0848b7f, (q31_t)0x7c0fdc8f, (q31_t)0xe07e7473, (q31_t)0x7c0e507e, (q31_t)0xe0785d7b, (q31_t)0x7c0cc421, (q31_t)0xe0724696, + (q31_t)0x7c0b3777, (q31_t)0xe06c2fc4, (q31_t)0x7c09aa80, (q31_t)0xe0661906, (q31_t)0x7c081d3d, (q31_t)0xe060025c, (q31_t)0x7c068fae, (q31_t)0xe059ebc5, + (q31_t)0x7c0501d2, (q31_t)0xe053d541, (q31_t)0x7c0373a9, (q31_t)0xe04dbed1, (q31_t)0x7c01e534, (q31_t)0xe047a875, (q31_t)0x7c005673, (q31_t)0xe041922c, + (q31_t)0x7bfec765, (q31_t)0xe03b7bf6, (q31_t)0x7bfd380a, (q31_t)0xe03565d5, (q31_t)0x7bfba863, (q31_t)0xe02f4fc6, (q31_t)0x7bfa1870, (q31_t)0xe02939cc, + (q31_t)0x7bf88830, (q31_t)0xe02323e5, (q31_t)0x7bf6f7a4, (q31_t)0xe01d0e12, (q31_t)0x7bf566cb, (q31_t)0xe016f852, (q31_t)0x7bf3d5a6, (q31_t)0xe010e2a7, + (q31_t)0x7bf24434, (q31_t)0xe00acd0e, (q31_t)0x7bf0b276, (q31_t)0xe004b78a, (q31_t)0x7bef206b, (q31_t)0xdffea219, (q31_t)0x7bed8e14, (q31_t)0xdff88cbc, + (q31_t)0x7bebfb70, (q31_t)0xdff27773, (q31_t)0x7bea6880, (q31_t)0xdfec623e, (q31_t)0x7be8d544, (q31_t)0xdfe64d1c, (q31_t)0x7be741bb, (q31_t)0xdfe0380e, + (q31_t)0x7be5ade6, (q31_t)0xdfda2314, (q31_t)0x7be419c4, (q31_t)0xdfd40e2e, (q31_t)0x7be28556, (q31_t)0xdfcdf95c, (q31_t)0x7be0f09b, (q31_t)0xdfc7e49d, + (q31_t)0x7bdf5b94, (q31_t)0xdfc1cff3, (q31_t)0x7bddc641, (q31_t)0xdfbbbb5c, (q31_t)0x7bdc30a1, (q31_t)0xdfb5a6d9, (q31_t)0x7bda9ab5, (q31_t)0xdfaf926a, + (q31_t)0x7bd9047c, (q31_t)0xdfa97e0f, (q31_t)0x7bd76df7, (q31_t)0xdfa369c8, (q31_t)0x7bd5d726, (q31_t)0xdf9d5595, (q31_t)0x7bd44008, (q31_t)0xdf974176, + (q31_t)0x7bd2a89e, (q31_t)0xdf912d6b, (q31_t)0x7bd110e8, (q31_t)0xdf8b1974, (q31_t)0x7bcf78e5, (q31_t)0xdf850591, (q31_t)0x7bcde095, (q31_t)0xdf7ef1c2, + (q31_t)0x7bcc47fa, (q31_t)0xdf78de07, (q31_t)0x7bcaaf12, (q31_t)0xdf72ca60, (q31_t)0x7bc915dd, (q31_t)0xdf6cb6cd, (q31_t)0x7bc77c5d, (q31_t)0xdf66a34e, + (q31_t)0x7bc5e290, (q31_t)0xdf608fe4, (q31_t)0x7bc44876, (q31_t)0xdf5a7c8d, (q31_t)0x7bc2ae10, (q31_t)0xdf54694b, (q31_t)0x7bc1135e, (q31_t)0xdf4e561c, + (q31_t)0x7bbf7860, (q31_t)0xdf484302, (q31_t)0x7bbddd15, (q31_t)0xdf422ffd, (q31_t)0x7bbc417e, (q31_t)0xdf3c1d0b, (q31_t)0x7bbaa59a, (q31_t)0xdf360a2d, + (q31_t)0x7bb9096b, (q31_t)0xdf2ff764, (q31_t)0x7bb76cef, (q31_t)0xdf29e4af, (q31_t)0x7bb5d026, (q31_t)0xdf23d20e, (q31_t)0x7bb43311, (q31_t)0xdf1dbf82, + (q31_t)0x7bb295b0, (q31_t)0xdf17ad0a, (q31_t)0x7bb0f803, (q31_t)0xdf119aa6, (q31_t)0x7baf5a09, (q31_t)0xdf0b8856, (q31_t)0x7badbbc3, (q31_t)0xdf05761b, + (q31_t)0x7bac1d31, (q31_t)0xdeff63f4, (q31_t)0x7baa7e53, (q31_t)0xdef951e2, (q31_t)0x7ba8df28, (q31_t)0xdef33fe3, (q31_t)0x7ba73fb1, (q31_t)0xdeed2dfa, + (q31_t)0x7ba59fee, (q31_t)0xdee71c24, (q31_t)0x7ba3ffde, (q31_t)0xdee10a63, (q31_t)0x7ba25f82, (q31_t)0xdedaf8b7, (q31_t)0x7ba0beda, (q31_t)0xded4e71f, + (q31_t)0x7b9f1de6, (q31_t)0xdeced59b, (q31_t)0x7b9d7ca5, (q31_t)0xdec8c42c, (q31_t)0x7b9bdb18, (q31_t)0xdec2b2d1, (q31_t)0x7b9a393f, (q31_t)0xdebca18b, + (q31_t)0x7b989719, (q31_t)0xdeb69059, (q31_t)0x7b96f4a8, (q31_t)0xdeb07f3c, (q31_t)0x7b9551ea, (q31_t)0xdeaa6e34, (q31_t)0x7b93aee0, (q31_t)0xdea45d40, + (q31_t)0x7b920b89, (q31_t)0xde9e4c60, (q31_t)0x7b9067e7, (q31_t)0xde983b95, (q31_t)0x7b8ec3f8, (q31_t)0xde922adf, (q31_t)0x7b8d1fbd, (q31_t)0xde8c1a3e, + (q31_t)0x7b8b7b36, (q31_t)0xde8609b1, (q31_t)0x7b89d662, (q31_t)0xde7ff938, (q31_t)0x7b883143, (q31_t)0xde79e8d5, (q31_t)0x7b868bd7, (q31_t)0xde73d886, + (q31_t)0x7b84e61f, (q31_t)0xde6dc84b, (q31_t)0x7b83401b, (q31_t)0xde67b826, (q31_t)0x7b8199ca, (q31_t)0xde61a815, (q31_t)0x7b7ff32e, (q31_t)0xde5b9819, + (q31_t)0x7b7e4c45, (q31_t)0xde558831, (q31_t)0x7b7ca510, (q31_t)0xde4f785f, (q31_t)0x7b7afd8f, (q31_t)0xde4968a1, (q31_t)0x7b7955c2, (q31_t)0xde4358f8, + (q31_t)0x7b77ada8, (q31_t)0xde3d4964, (q31_t)0x7b760542, (q31_t)0xde3739e4, (q31_t)0x7b745c91, (q31_t)0xde312a7a, (q31_t)0x7b72b393, (q31_t)0xde2b1b24, + (q31_t)0x7b710a49, (q31_t)0xde250be3, (q31_t)0x7b6f60b2, (q31_t)0xde1efcb7, (q31_t)0x7b6db6d0, (q31_t)0xde18eda0, (q31_t)0x7b6c0ca2, (q31_t)0xde12de9e, + (q31_t)0x7b6a6227, (q31_t)0xde0ccfb1, (q31_t)0x7b68b760, (q31_t)0xde06c0d9, (q31_t)0x7b670c4d, (q31_t)0xde00b216, (q31_t)0x7b6560ee, (q31_t)0xddfaa367, + (q31_t)0x7b63b543, (q31_t)0xddf494ce, (q31_t)0x7b62094c, (q31_t)0xddee8649, (q31_t)0x7b605d09, (q31_t)0xdde877da, (q31_t)0x7b5eb079, (q31_t)0xdde26980, + (q31_t)0x7b5d039e, (q31_t)0xdddc5b3b, (q31_t)0x7b5b5676, (q31_t)0xddd64d0a, (q31_t)0x7b59a902, (q31_t)0xddd03eef, (q31_t)0x7b57fb42, (q31_t)0xddca30e9, + (q31_t)0x7b564d36, (q31_t)0xddc422f8, (q31_t)0x7b549ede, (q31_t)0xddbe151d, (q31_t)0x7b52f03a, (q31_t)0xddb80756, (q31_t)0x7b51414a, (q31_t)0xddb1f9a4, + (q31_t)0x7b4f920e, (q31_t)0xddabec08, (q31_t)0x7b4de286, (q31_t)0xdda5de81, (q31_t)0x7b4c32b1, (q31_t)0xdd9fd10f, (q31_t)0x7b4a8291, (q31_t)0xdd99c3b2, + (q31_t)0x7b48d225, (q31_t)0xdd93b66a, (q31_t)0x7b47216c, (q31_t)0xdd8da938, (q31_t)0x7b457068, (q31_t)0xdd879c1b, (q31_t)0x7b43bf17, (q31_t)0xdd818f13, + (q31_t)0x7b420d7a, (q31_t)0xdd7b8220, (q31_t)0x7b405b92, (q31_t)0xdd757543, (q31_t)0x7b3ea95d, (q31_t)0xdd6f687b, (q31_t)0x7b3cf6dc, (q31_t)0xdd695bc9, + (q31_t)0x7b3b4410, (q31_t)0xdd634f2b, (q31_t)0x7b3990f7, (q31_t)0xdd5d42a3, (q31_t)0x7b37dd92, (q31_t)0xdd573631, (q31_t)0x7b3629e1, (q31_t)0xdd5129d4, + (q31_t)0x7b3475e5, (q31_t)0xdd4b1d8c, (q31_t)0x7b32c19c, (q31_t)0xdd451159, (q31_t)0x7b310d07, (q31_t)0xdd3f053c, (q31_t)0x7b2f5826, (q31_t)0xdd38f935, + (q31_t)0x7b2da2fa, (q31_t)0xdd32ed43, (q31_t)0x7b2bed81, (q31_t)0xdd2ce166, (q31_t)0x7b2a37bc, (q31_t)0xdd26d59f, (q31_t)0x7b2881ac, (q31_t)0xdd20c9ed, + (q31_t)0x7b26cb4f, (q31_t)0xdd1abe51, (q31_t)0x7b2514a6, (q31_t)0xdd14b2ca, (q31_t)0x7b235db2, (q31_t)0xdd0ea759, (q31_t)0x7b21a671, (q31_t)0xdd089bfe, + (q31_t)0x7b1feee5, (q31_t)0xdd0290b8, (q31_t)0x7b1e370d, (q31_t)0xdcfc8588, (q31_t)0x7b1c7ee8, (q31_t)0xdcf67a6d, (q31_t)0x7b1ac678, (q31_t)0xdcf06f68, + (q31_t)0x7b190dbc, (q31_t)0xdcea6478, (q31_t)0x7b1754b3, (q31_t)0xdce4599e, (q31_t)0x7b159b5f, (q31_t)0xdcde4eda, (q31_t)0x7b13e1bf, (q31_t)0xdcd8442b, + (q31_t)0x7b1227d3, (q31_t)0xdcd23993, (q31_t)0x7b106d9b, (q31_t)0xdccc2f0f, (q31_t)0x7b0eb318, (q31_t)0xdcc624a2, (q31_t)0x7b0cf848, (q31_t)0xdcc01a4a, + (q31_t)0x7b0b3d2c, (q31_t)0xdcba1008, (q31_t)0x7b0981c5, (q31_t)0xdcb405dc, (q31_t)0x7b07c612, (q31_t)0xdcadfbc5, (q31_t)0x7b060a12, (q31_t)0xdca7f1c5, + (q31_t)0x7b044dc7, (q31_t)0xdca1e7da, (q31_t)0x7b029130, (q31_t)0xdc9bde05, (q31_t)0x7b00d44d, (q31_t)0xdc95d446, (q31_t)0x7aff171e, (q31_t)0xdc8fca9c, + (q31_t)0x7afd59a4, (q31_t)0xdc89c109, (q31_t)0x7afb9bdd, (q31_t)0xdc83b78b, (q31_t)0x7af9ddcb, (q31_t)0xdc7dae23, (q31_t)0x7af81f6c, (q31_t)0xdc77a4d2, + (q31_t)0x7af660c2, (q31_t)0xdc719b96, (q31_t)0x7af4a1cc, (q31_t)0xdc6b9270, (q31_t)0x7af2e28b, (q31_t)0xdc658960, (q31_t)0x7af122fd, (q31_t)0xdc5f8066, + (q31_t)0x7aef6323, (q31_t)0xdc597781, (q31_t)0x7aeda2fe, (q31_t)0xdc536eb3, (q31_t)0x7aebe28d, (q31_t)0xdc4d65fb, (q31_t)0x7aea21d0, (q31_t)0xdc475d59, + (q31_t)0x7ae860c7, (q31_t)0xdc4154cd, (q31_t)0x7ae69f73, (q31_t)0xdc3b4c57, (q31_t)0x7ae4ddd2, (q31_t)0xdc3543f7, (q31_t)0x7ae31be6, (q31_t)0xdc2f3bad, + (q31_t)0x7ae159ae, (q31_t)0xdc293379, (q31_t)0x7adf972a, (q31_t)0xdc232b5c, (q31_t)0x7addd45b, (q31_t)0xdc1d2354, (q31_t)0x7adc113f, (q31_t)0xdc171b63, + (q31_t)0x7ada4dd8, (q31_t)0xdc111388, (q31_t)0x7ad88a25, (q31_t)0xdc0b0bc2, (q31_t)0x7ad6c626, (q31_t)0xdc050414, (q31_t)0x7ad501dc, (q31_t)0xdbfefc7b, + (q31_t)0x7ad33d45, (q31_t)0xdbf8f4f8, (q31_t)0x7ad17863, (q31_t)0xdbf2ed8c, (q31_t)0x7acfb336, (q31_t)0xdbece636, (q31_t)0x7acdedbc, (q31_t)0xdbe6def6, + (q31_t)0x7acc27f7, (q31_t)0xdbe0d7cd, (q31_t)0x7aca61e6, (q31_t)0xdbdad0b9, (q31_t)0x7ac89b89, (q31_t)0xdbd4c9bc, (q31_t)0x7ac6d4e0, (q31_t)0xdbcec2d6, + (q31_t)0x7ac50dec, (q31_t)0xdbc8bc06, (q31_t)0x7ac346ac, (q31_t)0xdbc2b54c, (q31_t)0x7ac17f20, (q31_t)0xdbbcaea8, (q31_t)0x7abfb749, (q31_t)0xdbb6a81b, + (q31_t)0x7abdef25, (q31_t)0xdbb0a1a4, (q31_t)0x7abc26b7, (q31_t)0xdbaa9b43, (q31_t)0x7aba5dfc, (q31_t)0xdba494f9, (q31_t)0x7ab894f6, (q31_t)0xdb9e8ec6, + (q31_t)0x7ab6cba4, (q31_t)0xdb9888a8, (q31_t)0x7ab50206, (q31_t)0xdb9282a2, (q31_t)0x7ab3381d, (q31_t)0xdb8c7cb1, (q31_t)0x7ab16de7, (q31_t)0xdb8676d8, + (q31_t)0x7aafa367, (q31_t)0xdb807114, (q31_t)0x7aadd89a, (q31_t)0xdb7a6b68, (q31_t)0x7aac0d82, (q31_t)0xdb7465d1, (q31_t)0x7aaa421e, (q31_t)0xdb6e6052, + (q31_t)0x7aa8766f, (q31_t)0xdb685ae9, (q31_t)0x7aa6aa74, (q31_t)0xdb625596, (q31_t)0x7aa4de2d, (q31_t)0xdb5c505a, (q31_t)0x7aa3119a, (q31_t)0xdb564b35, + (q31_t)0x7aa144bc, (q31_t)0xdb504626, (q31_t)0x7a9f7793, (q31_t)0xdb4a412e, (q31_t)0x7a9daa1d, (q31_t)0xdb443c4c, (q31_t)0x7a9bdc5c, (q31_t)0xdb3e3781, + (q31_t)0x7a9a0e50, (q31_t)0xdb3832cd, (q31_t)0x7a983ff7, (q31_t)0xdb322e30, (q31_t)0x7a967153, (q31_t)0xdb2c29a9, (q31_t)0x7a94a264, (q31_t)0xdb262539, + (q31_t)0x7a92d329, (q31_t)0xdb2020e0, (q31_t)0x7a9103a2, (q31_t)0xdb1a1c9d, (q31_t)0x7a8f33d0, (q31_t)0xdb141871, (q31_t)0x7a8d63b2, (q31_t)0xdb0e145c, + (q31_t)0x7a8b9348, (q31_t)0xdb08105e, (q31_t)0x7a89c293, (q31_t)0xdb020c77, (q31_t)0x7a87f192, (q31_t)0xdafc08a6, (q31_t)0x7a862046, (q31_t)0xdaf604ec, + (q31_t)0x7a844eae, (q31_t)0xdaf00149, (q31_t)0x7a827ccb, (q31_t)0xdae9fdbd, (q31_t)0x7a80aa9c, (q31_t)0xdae3fa48, (q31_t)0x7a7ed821, (q31_t)0xdaddf6ea, + (q31_t)0x7a7d055b, (q31_t)0xdad7f3a2, (q31_t)0x7a7b3249, (q31_t)0xdad1f072, (q31_t)0x7a795eec, (q31_t)0xdacbed58, (q31_t)0x7a778b43, (q31_t)0xdac5ea56, + (q31_t)0x7a75b74f, (q31_t)0xdabfe76a, (q31_t)0x7a73e30f, (q31_t)0xdab9e495, (q31_t)0x7a720e84, (q31_t)0xdab3e1d8, (q31_t)0x7a7039ad, (q31_t)0xdaaddf31, + (q31_t)0x7a6e648a, (q31_t)0xdaa7dca1, (q31_t)0x7a6c8f1c, (q31_t)0xdaa1da29, (q31_t)0x7a6ab963, (q31_t)0xda9bd7c7, (q31_t)0x7a68e35e, (q31_t)0xda95d57d, + (q31_t)0x7a670d0d, (q31_t)0xda8fd349, (q31_t)0x7a653671, (q31_t)0xda89d12d, (q31_t)0x7a635f8a, (q31_t)0xda83cf28, (q31_t)0x7a618857, (q31_t)0xda7dcd3a, + (q31_t)0x7a5fb0d8, (q31_t)0xda77cb63, (q31_t)0x7a5dd90e, (q31_t)0xda71c9a3, (q31_t)0x7a5c00f9, (q31_t)0xda6bc7fa, (q31_t)0x7a5a2898, (q31_t)0xda65c669, + (q31_t)0x7a584feb, (q31_t)0xda5fc4ef, (q31_t)0x7a5676f3, (q31_t)0xda59c38c, (q31_t)0x7a549db0, (q31_t)0xda53c240, (q31_t)0x7a52c421, (q31_t)0xda4dc10b, + (q31_t)0x7a50ea47, (q31_t)0xda47bfee, (q31_t)0x7a4f1021, (q31_t)0xda41bee8, (q31_t)0x7a4d35b0, (q31_t)0xda3bbdf9, (q31_t)0x7a4b5af3, (q31_t)0xda35bd22, + (q31_t)0x7a497feb, (q31_t)0xda2fbc61, (q31_t)0x7a47a498, (q31_t)0xda29bbb9, (q31_t)0x7a45c8f9, (q31_t)0xda23bb27, (q31_t)0x7a43ed0e, (q31_t)0xda1dbaad, + (q31_t)0x7a4210d8, (q31_t)0xda17ba4a, (q31_t)0x7a403457, (q31_t)0xda11b9ff, (q31_t)0x7a3e578b, (q31_t)0xda0bb9cb, (q31_t)0x7a3c7a73, (q31_t)0xda05b9ae, + (q31_t)0x7a3a9d0f, (q31_t)0xd9ffb9a9, (q31_t)0x7a38bf60, (q31_t)0xd9f9b9bb, (q31_t)0x7a36e166, (q31_t)0xd9f3b9e5, (q31_t)0x7a350321, (q31_t)0xd9edba26, + (q31_t)0x7a332490, (q31_t)0xd9e7ba7f, (q31_t)0x7a3145b3, (q31_t)0xd9e1baef, (q31_t)0x7a2f668c, (q31_t)0xd9dbbb77, (q31_t)0x7a2d8719, (q31_t)0xd9d5bc16, + (q31_t)0x7a2ba75a, (q31_t)0xd9cfbccd, (q31_t)0x7a29c750, (q31_t)0xd9c9bd9b, (q31_t)0x7a27e6fb, (q31_t)0xd9c3be81, (q31_t)0x7a26065b, (q31_t)0xd9bdbf7e, + (q31_t)0x7a24256f, (q31_t)0xd9b7c094, (q31_t)0x7a224437, (q31_t)0xd9b1c1c0, (q31_t)0x7a2062b5, (q31_t)0xd9abc305, (q31_t)0x7a1e80e7, (q31_t)0xd9a5c461, + (q31_t)0x7a1c9ece, (q31_t)0xd99fc5d4, (q31_t)0x7a1abc69, (q31_t)0xd999c75f, (q31_t)0x7a18d9b9, (q31_t)0xd993c902, (q31_t)0x7a16f6be, (q31_t)0xd98dcabd, + (q31_t)0x7a151378, (q31_t)0xd987cc90, (q31_t)0x7a132fe6, (q31_t)0xd981ce7a, (q31_t)0x7a114c09, (q31_t)0xd97bd07c, (q31_t)0x7a0f67e0, (q31_t)0xd975d295, + (q31_t)0x7a0d836d, (q31_t)0xd96fd4c7, (q31_t)0x7a0b9eae, (q31_t)0xd969d710, (q31_t)0x7a09b9a4, (q31_t)0xd963d971, (q31_t)0x7a07d44e, (q31_t)0xd95ddbea, + (q31_t)0x7a05eead, (q31_t)0xd957de7a, (q31_t)0x7a0408c1, (q31_t)0xd951e123, (q31_t)0x7a02228a, (q31_t)0xd94be3e3, (q31_t)0x7a003c07, (q31_t)0xd945e6bb, + (q31_t)0x79fe5539, (q31_t)0xd93fe9ab, (q31_t)0x79fc6e20, (q31_t)0xd939ecb3, (q31_t)0x79fa86bc, (q31_t)0xd933efd3, (q31_t)0x79f89f0c, (q31_t)0xd92df30b, + (q31_t)0x79f6b711, (q31_t)0xd927f65b, (q31_t)0x79f4cecb, (q31_t)0xd921f9c3, (q31_t)0x79f2e63a, (q31_t)0xd91bfd43, (q31_t)0x79f0fd5d, (q31_t)0xd91600da, + (q31_t)0x79ef1436, (q31_t)0xd910048a, (q31_t)0x79ed2ac3, (q31_t)0xd90a0852, (q31_t)0x79eb4105, (q31_t)0xd9040c32, (q31_t)0x79e956fb, (q31_t)0xd8fe1029, + (q31_t)0x79e76ca7, (q31_t)0xd8f81439, (q31_t)0x79e58207, (q31_t)0xd8f21861, (q31_t)0x79e3971c, (q31_t)0xd8ec1ca1, (q31_t)0x79e1abe6, (q31_t)0xd8e620fa, + (q31_t)0x79dfc064, (q31_t)0xd8e0256a, (q31_t)0x79ddd498, (q31_t)0xd8da29f2, (q31_t)0x79dbe880, (q31_t)0xd8d42e93, (q31_t)0x79d9fc1d, (q31_t)0xd8ce334c, + (q31_t)0x79d80f6f, (q31_t)0xd8c8381d, (q31_t)0x79d62276, (q31_t)0xd8c23d06, (q31_t)0x79d43532, (q31_t)0xd8bc4207, (q31_t)0x79d247a2, (q31_t)0xd8b64720, + (q31_t)0x79d059c8, (q31_t)0xd8b04c52, (q31_t)0x79ce6ba2, (q31_t)0xd8aa519c, (q31_t)0x79cc7d31, (q31_t)0xd8a456ff, (q31_t)0x79ca8e75, (q31_t)0xd89e5c79, + (q31_t)0x79c89f6e, (q31_t)0xd898620c, (q31_t)0x79c6b01b, (q31_t)0xd89267b7, (q31_t)0x79c4c07e, (q31_t)0xd88c6d7b, (q31_t)0x79c2d095, (q31_t)0xd8867356, + (q31_t)0x79c0e062, (q31_t)0xd880794b, (q31_t)0x79beefe3, (q31_t)0xd87a7f57, (q31_t)0x79bcff19, (q31_t)0xd874857c, (q31_t)0x79bb0e04, (q31_t)0xd86e8bb9, + (q31_t)0x79b91ca4, (q31_t)0xd868920f, (q31_t)0x79b72af9, (q31_t)0xd862987d, (q31_t)0x79b53903, (q31_t)0xd85c9f04, (q31_t)0x79b346c2, (q31_t)0xd856a5a3, + (q31_t)0x79b15435, (q31_t)0xd850ac5a, (q31_t)0x79af615e, (q31_t)0xd84ab32a, (q31_t)0x79ad6e3c, (q31_t)0xd844ba13, (q31_t)0x79ab7ace, (q31_t)0xd83ec114, + (q31_t)0x79a98715, (q31_t)0xd838c82d, (q31_t)0x79a79312, (q31_t)0xd832cf5f, (q31_t)0x79a59ec3, (q31_t)0xd82cd6aa, (q31_t)0x79a3aa29, (q31_t)0xd826de0d, + (q31_t)0x79a1b545, (q31_t)0xd820e589, (q31_t)0x799fc015, (q31_t)0xd81aed1d, (q31_t)0x799dca9a, (q31_t)0xd814f4ca, (q31_t)0x799bd4d4, (q31_t)0xd80efc8f, + (q31_t)0x7999dec4, (q31_t)0xd809046e, (q31_t)0x7997e868, (q31_t)0xd8030c64, (q31_t)0x7995f1c1, (q31_t)0xd7fd1474, (q31_t)0x7993facf, (q31_t)0xd7f71c9c, + (q31_t)0x79920392, (q31_t)0xd7f124dd, (q31_t)0x79900c0a, (q31_t)0xd7eb2d37, (q31_t)0x798e1438, (q31_t)0xd7e535a9, (q31_t)0x798c1c1a, (q31_t)0xd7df3e34, + (q31_t)0x798a23b1, (q31_t)0xd7d946d8, (q31_t)0x79882afd, (q31_t)0xd7d34f94, (q31_t)0x798631ff, (q31_t)0xd7cd586a, (q31_t)0x798438b5, (q31_t)0xd7c76158, + (q31_t)0x79823f20, (q31_t)0xd7c16a5f, (q31_t)0x79804541, (q31_t)0xd7bb737f, (q31_t)0x797e4b16, (q31_t)0xd7b57cb7, (q31_t)0x797c50a1, (q31_t)0xd7af8609, + (q31_t)0x797a55e0, (q31_t)0xd7a98f73, (q31_t)0x79785ad5, (q31_t)0xd7a398f6, (q31_t)0x79765f7f, (q31_t)0xd79da293, (q31_t)0x797463de, (q31_t)0xd797ac48, + (q31_t)0x797267f2, (q31_t)0xd791b616, (q31_t)0x79706bbb, (q31_t)0xd78bbffc, (q31_t)0x796e6f39, (q31_t)0xd785c9fc, (q31_t)0x796c726c, (q31_t)0xd77fd415, + (q31_t)0x796a7554, (q31_t)0xd779de47, (q31_t)0x796877f1, (q31_t)0xd773e892, (q31_t)0x79667a44, (q31_t)0xd76df2f6, (q31_t)0x79647c4c, (q31_t)0xd767fd72, + (q31_t)0x79627e08, (q31_t)0xd7620808, (q31_t)0x79607f7a, (q31_t)0xd75c12b7, (q31_t)0x795e80a1, (q31_t)0xd7561d7f, (q31_t)0x795c817d, (q31_t)0xd7502860, + (q31_t)0x795a820e, (q31_t)0xd74a335b, (q31_t)0x79588255, (q31_t)0xd7443e6e, (q31_t)0x79568250, (q31_t)0xd73e499a, (q31_t)0x79548201, (q31_t)0xd73854e0, + (q31_t)0x79528167, (q31_t)0xd732603f, (q31_t)0x79508082, (q31_t)0xd72c6bb6, (q31_t)0x794e7f52, (q31_t)0xd7267748, (q31_t)0x794c7dd7, (q31_t)0xd72082f2, + (q31_t)0x794a7c12, (q31_t)0xd71a8eb5, (q31_t)0x79487a01, (q31_t)0xd7149a92, (q31_t)0x794677a6, (q31_t)0xd70ea688, (q31_t)0x79447500, (q31_t)0xd708b297, + (q31_t)0x79427210, (q31_t)0xd702bec0, (q31_t)0x79406ed4, (q31_t)0xd6fccb01, (q31_t)0x793e6b4e, (q31_t)0xd6f6d75d, (q31_t)0x793c677d, (q31_t)0xd6f0e3d1, + (q31_t)0x793a6361, (q31_t)0xd6eaf05f, (q31_t)0x79385efa, (q31_t)0xd6e4fd06, (q31_t)0x79365a49, (q31_t)0xd6df09c6, (q31_t)0x7934554d, (q31_t)0xd6d916a0, + (q31_t)0x79325006, (q31_t)0xd6d32393, (q31_t)0x79304a74, (q31_t)0xd6cd30a0, (q31_t)0x792e4497, (q31_t)0xd6c73dc6, (q31_t)0x792c3e70, (q31_t)0xd6c14b05, + (q31_t)0x792a37fe, (q31_t)0xd6bb585e, (q31_t)0x79283141, (q31_t)0xd6b565d0, (q31_t)0x79262a3a, (q31_t)0xd6af735c, (q31_t)0x792422e8, (q31_t)0xd6a98101, + (q31_t)0x79221b4b, (q31_t)0xd6a38ec0, (q31_t)0x79201363, (q31_t)0xd69d9c98, (q31_t)0x791e0b31, (q31_t)0xd697aa8a, (q31_t)0x791c02b4, (q31_t)0xd691b895, + (q31_t)0x7919f9ec, (q31_t)0xd68bc6ba, (q31_t)0x7917f0d9, (q31_t)0xd685d4f9, (q31_t)0x7915e77c, (q31_t)0xd67fe351, (q31_t)0x7913ddd4, (q31_t)0xd679f1c2, + (q31_t)0x7911d3e2, (q31_t)0xd674004e, (q31_t)0x790fc9a4, (q31_t)0xd66e0ef2, (q31_t)0x790dbf1d, (q31_t)0xd6681db1, (q31_t)0x790bb44a, (q31_t)0xd6622c89, + (q31_t)0x7909a92d, (q31_t)0xd65c3b7b, (q31_t)0x79079dc5, (q31_t)0xd6564a87, (q31_t)0x79059212, (q31_t)0xd65059ac, (q31_t)0x79038615, (q31_t)0xd64a68eb, + (q31_t)0x790179cd, (q31_t)0xd6447844, (q31_t)0x78ff6d3b, (q31_t)0xd63e87b6, (q31_t)0x78fd605d, (q31_t)0xd6389742, (q31_t)0x78fb5336, (q31_t)0xd632a6e8, + (q31_t)0x78f945c3, (q31_t)0xd62cb6a8, (q31_t)0x78f73806, (q31_t)0xd626c681, (q31_t)0x78f529fe, (q31_t)0xd620d675, (q31_t)0x78f31bac, (q31_t)0xd61ae682, + (q31_t)0x78f10d0f, (q31_t)0xd614f6a9, (q31_t)0x78eefe28, (q31_t)0xd60f06ea, (q31_t)0x78eceef6, (q31_t)0xd6091745, (q31_t)0x78eadf79, (q31_t)0xd60327b9, + (q31_t)0x78e8cfb2, (q31_t)0xd5fd3848, (q31_t)0x78e6bfa0, (q31_t)0xd5f748f0, (q31_t)0x78e4af44, (q31_t)0xd5f159b3, (q31_t)0x78e29e9d, (q31_t)0xd5eb6a8f, + (q31_t)0x78e08dab, (q31_t)0xd5e57b85, (q31_t)0x78de7c6f, (q31_t)0xd5df8c96, (q31_t)0x78dc6ae8, (q31_t)0xd5d99dc0, (q31_t)0x78da5917, (q31_t)0xd5d3af04, + (q31_t)0x78d846fb, (q31_t)0xd5cdc062, (q31_t)0x78d63495, (q31_t)0xd5c7d1db, (q31_t)0x78d421e4, (q31_t)0xd5c1e36d, (q31_t)0x78d20ee9, (q31_t)0xd5bbf519, + (q31_t)0x78cffba3, (q31_t)0xd5b606e0, (q31_t)0x78cde812, (q31_t)0xd5b018c0, (q31_t)0x78cbd437, (q31_t)0xd5aa2abb, (q31_t)0x78c9c012, (q31_t)0xd5a43cd0, + (q31_t)0x78c7aba2, (q31_t)0xd59e4eff, (q31_t)0x78c596e7, (q31_t)0xd5986148, (q31_t)0x78c381e2, (q31_t)0xd59273ab, (q31_t)0x78c16c93, (q31_t)0xd58c8628, + (q31_t)0x78bf56f9, (q31_t)0xd58698c0, (q31_t)0x78bd4114, (q31_t)0xd580ab72, (q31_t)0x78bb2ae5, (q31_t)0xd57abe3d, (q31_t)0x78b9146c, (q31_t)0xd574d124, + (q31_t)0x78b6fda8, (q31_t)0xd56ee424, (q31_t)0x78b4e69a, (q31_t)0xd568f73f, (q31_t)0x78b2cf41, (q31_t)0xd5630a74, (q31_t)0x78b0b79e, (q31_t)0xd55d1dc3, + (q31_t)0x78ae9fb0, (q31_t)0xd557312d, (q31_t)0x78ac8778, (q31_t)0xd55144b0, (q31_t)0x78aa6ef5, (q31_t)0xd54b584f, (q31_t)0x78a85628, (q31_t)0xd5456c07, + (q31_t)0x78a63d11, (q31_t)0xd53f7fda, (q31_t)0x78a423af, (q31_t)0xd53993c7, (q31_t)0x78a20a03, (q31_t)0xd533a7cf, (q31_t)0x789ff00c, (q31_t)0xd52dbbf1, + (q31_t)0x789dd5cb, (q31_t)0xd527d02e, (q31_t)0x789bbb3f, (q31_t)0xd521e484, (q31_t)0x7899a06a, (q31_t)0xd51bf8f6, (q31_t)0x78978549, (q31_t)0xd5160d82, + (q31_t)0x789569df, (q31_t)0xd5102228, (q31_t)0x78934e2a, (q31_t)0xd50a36e9, (q31_t)0x7891322a, (q31_t)0xd5044bc4, (q31_t)0x788f15e0, (q31_t)0xd4fe60ba, + (q31_t)0x788cf94c, (q31_t)0xd4f875ca, (q31_t)0x788adc6e, (q31_t)0xd4f28af5, (q31_t)0x7888bf45, (q31_t)0xd4eca03a, (q31_t)0x7886a1d1, (q31_t)0xd4e6b59a, + (q31_t)0x78848414, (q31_t)0xd4e0cb15, (q31_t)0x7882660c, (q31_t)0xd4dae0aa, (q31_t)0x788047ba, (q31_t)0xd4d4f65a, (q31_t)0x787e291d, (q31_t)0xd4cf0c24, + (q31_t)0x787c0a36, (q31_t)0xd4c92209, (q31_t)0x7879eb05, (q31_t)0xd4c33809, (q31_t)0x7877cb89, (q31_t)0xd4bd4e23, (q31_t)0x7875abc3, (q31_t)0xd4b76458, + (q31_t)0x78738bb3, (q31_t)0xd4b17aa8, (q31_t)0x78716b59, (q31_t)0xd4ab9112, (q31_t)0x786f4ab4, (q31_t)0xd4a5a798, (q31_t)0x786d29c5, (q31_t)0xd49fbe37, + (q31_t)0x786b088c, (q31_t)0xd499d4f2, (q31_t)0x7868e708, (q31_t)0xd493ebc8, (q31_t)0x7866c53a, (q31_t)0xd48e02b8, (q31_t)0x7864a322, (q31_t)0xd48819c3, + (q31_t)0x786280bf, (q31_t)0xd48230e9, (q31_t)0x78605e13, (q31_t)0xd47c4829, (q31_t)0x785e3b1c, (q31_t)0xd4765f85, (q31_t)0x785c17db, (q31_t)0xd47076fb, + (q31_t)0x7859f44f, (q31_t)0xd46a8e8d, (q31_t)0x7857d079, (q31_t)0xd464a639, (q31_t)0x7855ac5a, (q31_t)0xd45ebe00, (q31_t)0x785387ef, (q31_t)0xd458d5e2, + (q31_t)0x7851633b, (q31_t)0xd452eddf, (q31_t)0x784f3e3c, (q31_t)0xd44d05f6, (q31_t)0x784d18f4, (q31_t)0xd4471e29, (q31_t)0x784af361, (q31_t)0xd4413677, + (q31_t)0x7848cd83, (q31_t)0xd43b4ee0, (q31_t)0x7846a75c, (q31_t)0xd4356763, (q31_t)0x784480ea, (q31_t)0xd42f8002, (q31_t)0x78425a2f, (q31_t)0xd42998bc, + (q31_t)0x78403329, (q31_t)0xd423b191, (q31_t)0x783e0bd9, (q31_t)0xd41dca81, (q31_t)0x783be43e, (q31_t)0xd417e38c, (q31_t)0x7839bc5a, (q31_t)0xd411fcb2, + (q31_t)0x7837942b, (q31_t)0xd40c15f3, (q31_t)0x78356bb2, (q31_t)0xd4062f4f, (q31_t)0x783342ef, (q31_t)0xd40048c6, (q31_t)0x783119e2, (q31_t)0xd3fa6259, + (q31_t)0x782ef08b, (q31_t)0xd3f47c06, (q31_t)0x782cc6ea, (q31_t)0xd3ee95cf, (q31_t)0x782a9cfe, (q31_t)0xd3e8afb3, (q31_t)0x782872c8, (q31_t)0xd3e2c9b2, + (q31_t)0x78264849, (q31_t)0xd3dce3cd, (q31_t)0x78241d7f, (q31_t)0xd3d6fe03, (q31_t)0x7821f26b, (q31_t)0xd3d11853, (q31_t)0x781fc70d, (q31_t)0xd3cb32c0, + (q31_t)0x781d9b65, (q31_t)0xd3c54d47, (q31_t)0x781b6f72, (q31_t)0xd3bf67ea, (q31_t)0x78194336, (q31_t)0xd3b982a8, (q31_t)0x781716b0, (q31_t)0xd3b39d81, + (q31_t)0x7814e9df, (q31_t)0xd3adb876, (q31_t)0x7812bcc4, (q31_t)0xd3a7d385, (q31_t)0x78108f60, (q31_t)0xd3a1eeb1, (q31_t)0x780e61b1, (q31_t)0xd39c09f7, + (q31_t)0x780c33b8, (q31_t)0xd396255a, (q31_t)0x780a0575, (q31_t)0xd39040d7, (q31_t)0x7807d6e9, (q31_t)0xd38a5c70, (q31_t)0x7805a812, (q31_t)0xd3847824, + (q31_t)0x780378f1, (q31_t)0xd37e93f4, (q31_t)0x78014986, (q31_t)0xd378afdf, (q31_t)0x77ff19d1, (q31_t)0xd372cbe6, (q31_t)0x77fce9d2, (q31_t)0xd36ce808, + (q31_t)0x77fab989, (q31_t)0xd3670446, (q31_t)0x77f888f6, (q31_t)0xd361209f, (q31_t)0x77f65819, (q31_t)0xd35b3d13, (q31_t)0x77f426f2, (q31_t)0xd35559a4, + (q31_t)0x77f1f581, (q31_t)0xd34f764f, (q31_t)0x77efc3c5, (q31_t)0xd3499317, (q31_t)0x77ed91c0, (q31_t)0xd343affa, (q31_t)0x77eb5f71, (q31_t)0xd33dccf8, + (q31_t)0x77e92cd9, (q31_t)0xd337ea12, (q31_t)0x77e6f9f6, (q31_t)0xd3320748, (q31_t)0x77e4c6c9, (q31_t)0xd32c2499, (q31_t)0x77e29352, (q31_t)0xd3264206, + (q31_t)0x77e05f91, (q31_t)0xd3205f8f, (q31_t)0x77de2b86, (q31_t)0xd31a7d33, (q31_t)0x77dbf732, (q31_t)0xd3149af3, (q31_t)0x77d9c293, (q31_t)0xd30eb8cf, + (q31_t)0x77d78daa, (q31_t)0xd308d6c7, (q31_t)0x77d55878, (q31_t)0xd302f4da, (q31_t)0x77d322fc, (q31_t)0xd2fd1309, (q31_t)0x77d0ed35, (q31_t)0xd2f73154, + (q31_t)0x77ceb725, (q31_t)0xd2f14fba, (q31_t)0x77cc80cb, (q31_t)0xd2eb6e3c, (q31_t)0x77ca4a27, (q31_t)0xd2e58cdb, (q31_t)0x77c81339, (q31_t)0xd2dfab95, + (q31_t)0x77c5dc01, (q31_t)0xd2d9ca6a, (q31_t)0x77c3a47f, (q31_t)0xd2d3e95c, (q31_t)0x77c16cb4, (q31_t)0xd2ce0869, (q31_t)0x77bf349f, (q31_t)0xd2c82793, + (q31_t)0x77bcfc3f, (q31_t)0xd2c246d8, (q31_t)0x77bac396, (q31_t)0xd2bc6639, (q31_t)0x77b88aa3, (q31_t)0xd2b685b6, (q31_t)0x77b65166, (q31_t)0xd2b0a54f, + (q31_t)0x77b417df, (q31_t)0xd2aac504, (q31_t)0x77b1de0f, (q31_t)0xd2a4e4d5, (q31_t)0x77afa3f5, (q31_t)0xd29f04c2, (q31_t)0x77ad6990, (q31_t)0xd29924cb, + (q31_t)0x77ab2ee2, (q31_t)0xd29344f0, (q31_t)0x77a8f3ea, (q31_t)0xd28d6531, (q31_t)0x77a6b8a9, (q31_t)0xd287858e, (q31_t)0x77a47d1d, (q31_t)0xd281a607, + (q31_t)0x77a24148, (q31_t)0xd27bc69c, (q31_t)0x77a00529, (q31_t)0xd275e74d, (q31_t)0x779dc8c0, (q31_t)0xd270081b, (q31_t)0x779b8c0e, (q31_t)0xd26a2904, + (q31_t)0x77994f11, (q31_t)0xd2644a0a, (q31_t)0x779711cb, (q31_t)0xd25e6b2b, (q31_t)0x7794d43b, (q31_t)0xd2588c69, (q31_t)0x77929661, (q31_t)0xd252adc3, + (q31_t)0x7790583e, (q31_t)0xd24ccf39, (q31_t)0x778e19d0, (q31_t)0xd246f0cb, (q31_t)0x778bdb19, (q31_t)0xd241127a, (q31_t)0x77899c19, (q31_t)0xd23b3444, + (q31_t)0x77875cce, (q31_t)0xd235562b, (q31_t)0x77851d3a, (q31_t)0xd22f782f, (q31_t)0x7782dd5c, (q31_t)0xd2299a4e, (q31_t)0x77809d35, (q31_t)0xd223bc8a, + (q31_t)0x777e5cc3, (q31_t)0xd21ddee2, (q31_t)0x777c1c08, (q31_t)0xd2180156, (q31_t)0x7779db03, (q31_t)0xd21223e7, (q31_t)0x777799b5, (q31_t)0xd20c4694, + (q31_t)0x7775581d, (q31_t)0xd206695d, (q31_t)0x7773163b, (q31_t)0xd2008c43, (q31_t)0x7770d40f, (q31_t)0xd1faaf45, (q31_t)0x776e919a, (q31_t)0xd1f4d263, + (q31_t)0x776c4edb, (q31_t)0xd1eef59e, (q31_t)0x776a0bd3, (q31_t)0xd1e918f5, (q31_t)0x7767c880, (q31_t)0xd1e33c69, (q31_t)0x776584e5, (q31_t)0xd1dd5ff9, + (q31_t)0x776340ff, (q31_t)0xd1d783a6, (q31_t)0x7760fcd0, (q31_t)0xd1d1a76f, (q31_t)0x775eb857, (q31_t)0xd1cbcb54, (q31_t)0x775c7395, (q31_t)0xd1c5ef56, + (q31_t)0x775a2e89, (q31_t)0xd1c01375, (q31_t)0x7757e933, (q31_t)0xd1ba37b0, (q31_t)0x7755a394, (q31_t)0xd1b45c08, (q31_t)0x77535dab, (q31_t)0xd1ae807c, + (q31_t)0x77511778, (q31_t)0xd1a8a50d, (q31_t)0x774ed0fc, (q31_t)0xd1a2c9ba, (q31_t)0x774c8a36, (q31_t)0xd19cee84, (q31_t)0x774a4327, (q31_t)0xd197136b, + (q31_t)0x7747fbce, (q31_t)0xd191386e, (q31_t)0x7745b42c, (q31_t)0xd18b5d8e, (q31_t)0x77436c40, (q31_t)0xd18582ca, (q31_t)0x7741240a, (q31_t)0xd17fa823, + (q31_t)0x773edb8b, (q31_t)0xd179cd99, (q31_t)0x773c92c2, (q31_t)0xd173f32c, (q31_t)0x773a49b0, (q31_t)0xd16e18db, (q31_t)0x77380054, (q31_t)0xd1683ea7, + (q31_t)0x7735b6af, (q31_t)0xd1626490, (q31_t)0x77336cc0, (q31_t)0xd15c8a95, (q31_t)0x77312287, (q31_t)0xd156b0b7, (q31_t)0x772ed805, (q31_t)0xd150d6f6, + (q31_t)0x772c8d3a, (q31_t)0xd14afd52, (q31_t)0x772a4225, (q31_t)0xd14523cb, (q31_t)0x7727f6c6, (q31_t)0xd13f4a60, (q31_t)0x7725ab1f, (q31_t)0xd1397113, + (q31_t)0x77235f2d, (q31_t)0xd13397e2, (q31_t)0x772112f2, (q31_t)0xd12dbece, (q31_t)0x771ec66e, (q31_t)0xd127e5d7, (q31_t)0x771c79a0, (q31_t)0xd1220cfc, + (q31_t)0x771a2c88, (q31_t)0xd11c343f, (q31_t)0x7717df27, (q31_t)0xd1165b9f, (q31_t)0x7715917d, (q31_t)0xd110831b, (q31_t)0x77134389, (q31_t)0xd10aaab5, + (q31_t)0x7710f54c, (q31_t)0xd104d26b, (q31_t)0x770ea6c5, (q31_t)0xd0fefa3f, (q31_t)0x770c57f5, (q31_t)0xd0f9222f, (q31_t)0x770a08dc, (q31_t)0xd0f34a3d, + (q31_t)0x7707b979, (q31_t)0xd0ed7267, (q31_t)0x770569cc, (q31_t)0xd0e79aaf, (q31_t)0x770319d6, (q31_t)0xd0e1c313, (q31_t)0x7700c997, (q31_t)0xd0dbeb95, + (q31_t)0x76fe790e, (q31_t)0xd0d61434, (q31_t)0x76fc283c, (q31_t)0xd0d03cf0, (q31_t)0x76f9d721, (q31_t)0xd0ca65c9, (q31_t)0x76f785bc, (q31_t)0xd0c48ebf, + (q31_t)0x76f5340e, (q31_t)0xd0beb7d2, (q31_t)0x76f2e216, (q31_t)0xd0b8e102, (q31_t)0x76f08fd5, (q31_t)0xd0b30a50, (q31_t)0x76ee3d4b, (q31_t)0xd0ad33ba, + (q31_t)0x76ebea77, (q31_t)0xd0a75d42, (q31_t)0x76e9975a, (q31_t)0xd0a186e7, (q31_t)0x76e743f4, (q31_t)0xd09bb0aa, (q31_t)0x76e4f044, (q31_t)0xd095da89, + (q31_t)0x76e29c4b, (q31_t)0xd0900486, (q31_t)0x76e04808, (q31_t)0xd08a2ea0, (q31_t)0x76ddf37c, (q31_t)0xd08458d7, (q31_t)0x76db9ea7, (q31_t)0xd07e832c, + (q31_t)0x76d94989, (q31_t)0xd078ad9e, (q31_t)0x76d6f421, (q31_t)0xd072d82d, (q31_t)0x76d49e70, (q31_t)0xd06d02da, (q31_t)0x76d24876, (q31_t)0xd0672da3, + (q31_t)0x76cff232, (q31_t)0xd061588b, (q31_t)0x76cd9ba5, (q31_t)0xd05b838f, (q31_t)0x76cb44cf, (q31_t)0xd055aeb1, (q31_t)0x76c8edb0, (q31_t)0xd04fd9f1, + (q31_t)0x76c69647, (q31_t)0xd04a054e, (q31_t)0x76c43e95, (q31_t)0xd04430c8, (q31_t)0x76c1e699, (q31_t)0xd03e5c60, (q31_t)0x76bf8e55, (q31_t)0xd0388815, + (q31_t)0x76bd35c7, (q31_t)0xd032b3e7, (q31_t)0x76badcf0, (q31_t)0xd02cdfd8, (q31_t)0x76b883d0, (q31_t)0xd0270be5, (q31_t)0x76b62a66, (q31_t)0xd0213810, + (q31_t)0x76b3d0b4, (q31_t)0xd01b6459, (q31_t)0x76b176b8, (q31_t)0xd01590bf, (q31_t)0x76af1c72, (q31_t)0xd00fbd43, (q31_t)0x76acc1e4, (q31_t)0xd009e9e4, + (q31_t)0x76aa670d, (q31_t)0xd00416a3, (q31_t)0x76a80bec, (q31_t)0xcffe4380, (q31_t)0x76a5b082, (q31_t)0xcff8707a, (q31_t)0x76a354cf, (q31_t)0xcff29d92, + (q31_t)0x76a0f8d2, (q31_t)0xcfeccac7, (q31_t)0x769e9c8d, (q31_t)0xcfe6f81a, (q31_t)0x769c3ffe, (q31_t)0xcfe1258b, (q31_t)0x7699e326, (q31_t)0xcfdb531a, + (q31_t)0x76978605, (q31_t)0xcfd580c6, (q31_t)0x7695289b, (q31_t)0xcfcfae8f, (q31_t)0x7692cae8, (q31_t)0xcfc9dc77, (q31_t)0x76906ceb, (q31_t)0xcfc40a7c, + (q31_t)0x768e0ea6, (q31_t)0xcfbe389f, (q31_t)0x768bb017, (q31_t)0xcfb866e0, (q31_t)0x7689513f, (q31_t)0xcfb2953f, (q31_t)0x7686f21e, (q31_t)0xcfacc3bb, + (q31_t)0x768492b4, (q31_t)0xcfa6f255, (q31_t)0x76823301, (q31_t)0xcfa1210d, (q31_t)0x767fd304, (q31_t)0xcf9b4fe3, (q31_t)0x767d72bf, (q31_t)0xcf957ed7, + (q31_t)0x767b1231, (q31_t)0xcf8fade9, (q31_t)0x7678b159, (q31_t)0xcf89dd18, (q31_t)0x76765038, (q31_t)0xcf840c65, (q31_t)0x7673eecf, (q31_t)0xcf7e3bd1, + (q31_t)0x76718d1c, (q31_t)0xcf786b5a, (q31_t)0x766f2b20, (q31_t)0xcf729b01, (q31_t)0x766cc8db, (q31_t)0xcf6ccac6, (q31_t)0x766a664d, (q31_t)0xcf66faa9, + (q31_t)0x76680376, (q31_t)0xcf612aaa, (q31_t)0x7665a056, (q31_t)0xcf5b5ac9, (q31_t)0x76633ced, (q31_t)0xcf558b06, (q31_t)0x7660d93b, (q31_t)0xcf4fbb61, + (q31_t)0x765e7540, (q31_t)0xcf49ebda, (q31_t)0x765c10fc, (q31_t)0xcf441c71, (q31_t)0x7659ac6f, (q31_t)0xcf3e4d26, (q31_t)0x76574798, (q31_t)0xcf387dfa, + (q31_t)0x7654e279, (q31_t)0xcf32aeeb, (q31_t)0x76527d11, (q31_t)0xcf2cdffa, (q31_t)0x76501760, (q31_t)0xcf271128, (q31_t)0x764db166, (q31_t)0xcf214274, + (q31_t)0x764b4b23, (q31_t)0xcf1b73de, (q31_t)0x7648e497, (q31_t)0xcf15a566, (q31_t)0x76467dc2, (q31_t)0xcf0fd70c, (q31_t)0x764416a4, (q31_t)0xcf0a08d0, + (q31_t)0x7641af3d, (q31_t)0xcf043ab3, (q31_t)0x763f478d, (q31_t)0xcefe6cb3, (q31_t)0x763cdf94, (q31_t)0xcef89ed2, (q31_t)0x763a7752, (q31_t)0xcef2d110, + (q31_t)0x76380ec8, (q31_t)0xceed036b, (q31_t)0x7635a5f4, (q31_t)0xcee735e5, (q31_t)0x76333cd8, (q31_t)0xcee1687d, (q31_t)0x7630d372, (q31_t)0xcedb9b33, + (q31_t)0x762e69c4, (q31_t)0xced5ce08, (q31_t)0x762bffcd, (q31_t)0xced000fb, (q31_t)0x7629958c, (q31_t)0xceca340c, (q31_t)0x76272b03, (q31_t)0xcec4673c, + (q31_t)0x7624c031, (q31_t)0xcebe9a8a, (q31_t)0x76225517, (q31_t)0xceb8cdf7, (q31_t)0x761fe9b3, (q31_t)0xceb30181, (q31_t)0x761d7e06, (q31_t)0xcead352b, + (q31_t)0x761b1211, (q31_t)0xcea768f2, (q31_t)0x7618a5d3, (q31_t)0xcea19cd8, (q31_t)0x7616394c, (q31_t)0xce9bd0dd, (q31_t)0x7613cc7c, (q31_t)0xce960500, + (q31_t)0x76115f63, (q31_t)0xce903942, (q31_t)0x760ef201, (q31_t)0xce8a6da2, (q31_t)0x760c8457, (q31_t)0xce84a220, (q31_t)0x760a1664, (q31_t)0xce7ed6bd, + (q31_t)0x7607a828, (q31_t)0xce790b79, (q31_t)0x760539a3, (q31_t)0xce734053, (q31_t)0x7602cad5, (q31_t)0xce6d754c, (q31_t)0x76005bbf, (q31_t)0xce67aa63, + (q31_t)0x75fdec60, (q31_t)0xce61df99, (q31_t)0x75fb7cb8, (q31_t)0xce5c14ed, (q31_t)0x75f90cc7, (q31_t)0xce564a60, (q31_t)0x75f69c8d, (q31_t)0xce507ff2, + (q31_t)0x75f42c0b, (q31_t)0xce4ab5a2, (q31_t)0x75f1bb40, (q31_t)0xce44eb71, (q31_t)0x75ef4a2c, (q31_t)0xce3f215f, (q31_t)0x75ecd8cf, (q31_t)0xce39576c, + (q31_t)0x75ea672a, (q31_t)0xce338d97, (q31_t)0x75e7f53c, (q31_t)0xce2dc3e1, (q31_t)0x75e58305, (q31_t)0xce27fa49, (q31_t)0x75e31086, (q31_t)0xce2230d0, + (q31_t)0x75e09dbd, (q31_t)0xce1c6777, (q31_t)0x75de2aac, (q31_t)0xce169e3b, (q31_t)0x75dbb753, (q31_t)0xce10d51f, (q31_t)0x75d943b0, (q31_t)0xce0b0c21, + (q31_t)0x75d6cfc5, (q31_t)0xce054343, (q31_t)0x75d45b92, (q31_t)0xcdff7a83, (q31_t)0x75d1e715, (q31_t)0xcdf9b1e2, (q31_t)0x75cf7250, (q31_t)0xcdf3e95f, + (q31_t)0x75ccfd42, (q31_t)0xcdee20fc, (q31_t)0x75ca87ec, (q31_t)0xcde858b8, (q31_t)0x75c8124d, (q31_t)0xcde29092, (q31_t)0x75c59c65, (q31_t)0xcddcc88b, + (q31_t)0x75c32634, (q31_t)0xcdd700a4, (q31_t)0x75c0afbb, (q31_t)0xcdd138db, (q31_t)0x75be38fa, (q31_t)0xcdcb7131, (q31_t)0x75bbc1ef, (q31_t)0xcdc5a9a6, + (q31_t)0x75b94a9c, (q31_t)0xcdbfe23a, (q31_t)0x75b6d301, (q31_t)0xcdba1aee, (q31_t)0x75b45b1d, (q31_t)0xcdb453c0, (q31_t)0x75b1e2f0, (q31_t)0xcdae8cb1, + (q31_t)0x75af6a7b, (q31_t)0xcda8c5c1, (q31_t)0x75acf1bd, (q31_t)0xcda2fef0, (q31_t)0x75aa78b6, (q31_t)0xcd9d383f, (q31_t)0x75a7ff67, (q31_t)0xcd9771ac, + (q31_t)0x75a585cf, (q31_t)0xcd91ab39, (q31_t)0x75a30bef, (q31_t)0xcd8be4e4, (q31_t)0x75a091c6, (q31_t)0xcd861eaf, (q31_t)0x759e1755, (q31_t)0xcd805899, + (q31_t)0x759b9c9b, (q31_t)0xcd7a92a2, (q31_t)0x75992198, (q31_t)0xcd74ccca, (q31_t)0x7596a64d, (q31_t)0xcd6f0711, (q31_t)0x75942ab9, (q31_t)0xcd694178, + (q31_t)0x7591aedd, (q31_t)0xcd637bfe, (q31_t)0x758f32b9, (q31_t)0xcd5db6a3, (q31_t)0x758cb64c, (q31_t)0xcd57f167, (q31_t)0x758a3996, (q31_t)0xcd522c4a, + (q31_t)0x7587bc98, (q31_t)0xcd4c674d, (q31_t)0x75853f51, (q31_t)0xcd46a26f, (q31_t)0x7582c1c2, (q31_t)0xcd40ddb0, (q31_t)0x758043ea, (q31_t)0xcd3b1911, + (q31_t)0x757dc5ca, (q31_t)0xcd355491, (q31_t)0x757b4762, (q31_t)0xcd2f9030, (q31_t)0x7578c8b0, (q31_t)0xcd29cbee, (q31_t)0x757649b7, (q31_t)0xcd2407cc, + (q31_t)0x7573ca75, (q31_t)0xcd1e43ca, (q31_t)0x75714aea, (q31_t)0xcd187fe6, (q31_t)0x756ecb18, (q31_t)0xcd12bc22, (q31_t)0x756c4afc, (q31_t)0xcd0cf87e, + (q31_t)0x7569ca99, (q31_t)0xcd0734f9, (q31_t)0x756749ec, (q31_t)0xcd017193, (q31_t)0x7564c8f8, (q31_t)0xccfbae4d, (q31_t)0x756247bb, (q31_t)0xccf5eb26, + (q31_t)0x755fc635, (q31_t)0xccf0281f, (q31_t)0x755d4467, (q31_t)0xccea6538, (q31_t)0x755ac251, (q31_t)0xcce4a26f, (q31_t)0x75583ff3, (q31_t)0xccdedfc7, + (q31_t)0x7555bd4c, (q31_t)0xccd91d3d, (q31_t)0x75533a5c, (q31_t)0xccd35ad4, (q31_t)0x7550b725, (q31_t)0xcccd988a, (q31_t)0x754e33a4, (q31_t)0xccc7d65f, + (q31_t)0x754bafdc, (q31_t)0xccc21455, (q31_t)0x75492bcb, (q31_t)0xccbc5269, (q31_t)0x7546a772, (q31_t)0xccb6909e, (q31_t)0x754422d0, (q31_t)0xccb0cef2, + (q31_t)0x75419de7, (q31_t)0xccab0d65, (q31_t)0x753f18b4, (q31_t)0xcca54bf9, (q31_t)0x753c933a, (q31_t)0xcc9f8aac, (q31_t)0x753a0d77, (q31_t)0xcc99c97e, + (q31_t)0x7537876c, (q31_t)0xcc940871, (q31_t)0x75350118, (q31_t)0xcc8e4783, (q31_t)0x75327a7d, (q31_t)0xcc8886b5, (q31_t)0x752ff399, (q31_t)0xcc82c607, + (q31_t)0x752d6c6c, (q31_t)0xcc7d0578, (q31_t)0x752ae4f8, (q31_t)0xcc774509, (q31_t)0x75285d3b, (q31_t)0xcc7184ba, (q31_t)0x7525d536, (q31_t)0xcc6bc48b, + (q31_t)0x75234ce8, (q31_t)0xcc66047b, (q31_t)0x7520c453, (q31_t)0xcc60448c, (q31_t)0x751e3b75, (q31_t)0xcc5a84bc, (q31_t)0x751bb24f, (q31_t)0xcc54c50c, + (q31_t)0x751928e0, (q31_t)0xcc4f057c, (q31_t)0x75169f2a, (q31_t)0xcc49460c, (q31_t)0x7514152b, (q31_t)0xcc4386bc, (q31_t)0x75118ae4, (q31_t)0xcc3dc78b, + (q31_t)0x750f0054, (q31_t)0xcc38087b, (q31_t)0x750c757d, (q31_t)0xcc32498a, (q31_t)0x7509ea5d, (q31_t)0xcc2c8aba, (q31_t)0x75075ef5, (q31_t)0xcc26cc09, + (q31_t)0x7504d345, (q31_t)0xcc210d79, (q31_t)0x7502474d, (q31_t)0xcc1b4f08, (q31_t)0x74ffbb0d, (q31_t)0xcc1590b8, (q31_t)0x74fd2e84, (q31_t)0xcc0fd287, + (q31_t)0x74faa1b3, (q31_t)0xcc0a1477, (q31_t)0x74f8149a, (q31_t)0xcc045686, (q31_t)0x74f58739, (q31_t)0xcbfe98b6, (q31_t)0x74f2f990, (q31_t)0xcbf8db05, + (q31_t)0x74f06b9e, (q31_t)0xcbf31d75, (q31_t)0x74eddd65, (q31_t)0xcbed6005, (q31_t)0x74eb4ee3, (q31_t)0xcbe7a2b5, (q31_t)0x74e8c01a, (q31_t)0xcbe1e585, + (q31_t)0x74e63108, (q31_t)0xcbdc2876, (q31_t)0x74e3a1ae, (q31_t)0xcbd66b86, (q31_t)0x74e1120c, (q31_t)0xcbd0aeb7, (q31_t)0x74de8221, (q31_t)0xcbcaf208, + (q31_t)0x74dbf1ef, (q31_t)0xcbc53579, (q31_t)0x74d96175, (q31_t)0xcbbf790a, (q31_t)0x74d6d0b2, (q31_t)0xcbb9bcbb, (q31_t)0x74d43fa8, (q31_t)0xcbb4008d, + (q31_t)0x74d1ae55, (q31_t)0xcbae447f, (q31_t)0x74cf1cbb, (q31_t)0xcba88891, (q31_t)0x74cc8ad8, (q31_t)0xcba2ccc4, (q31_t)0x74c9f8ad, (q31_t)0xcb9d1117, + (q31_t)0x74c7663a, (q31_t)0xcb97558a, (q31_t)0x74c4d380, (q31_t)0xcb919a1d, (q31_t)0x74c2407d, (q31_t)0xcb8bded1, (q31_t)0x74bfad32, (q31_t)0xcb8623a5, + (q31_t)0x74bd199f, (q31_t)0xcb80689a, (q31_t)0x74ba85c4, (q31_t)0xcb7aadaf, (q31_t)0x74b7f1a1, (q31_t)0xcb74f2e4, (q31_t)0x74b55d36, (q31_t)0xcb6f383a, + (q31_t)0x74b2c884, (q31_t)0xcb697db0, (q31_t)0x74b03389, (q31_t)0xcb63c347, (q31_t)0x74ad9e46, (q31_t)0xcb5e08fe, (q31_t)0x74ab08bb, (q31_t)0xcb584ed6, + (q31_t)0x74a872e8, (q31_t)0xcb5294ce, (q31_t)0x74a5dccd, (q31_t)0xcb4cdae6, (q31_t)0x74a3466b, (q31_t)0xcb47211f, (q31_t)0x74a0afc0, (q31_t)0xcb416779, + (q31_t)0x749e18cd, (q31_t)0xcb3badf3, (q31_t)0x749b8193, (q31_t)0xcb35f48d, (q31_t)0x7498ea11, (q31_t)0xcb303b49, (q31_t)0x74965246, (q31_t)0xcb2a8224, + (q31_t)0x7493ba34, (q31_t)0xcb24c921, (q31_t)0x749121da, (q31_t)0xcb1f103e, (q31_t)0x748e8938, (q31_t)0xcb19577b, (q31_t)0x748bf04d, (q31_t)0xcb139ed9, + (q31_t)0x7489571c, (q31_t)0xcb0de658, (q31_t)0x7486bda2, (q31_t)0xcb082df8, (q31_t)0x748423e0, (q31_t)0xcb0275b8, (q31_t)0x748189d7, (q31_t)0xcafcbd99, + (q31_t)0x747eef85, (q31_t)0xcaf7059a, (q31_t)0x747c54ec, (q31_t)0xcaf14dbd, (q31_t)0x7479ba0b, (q31_t)0xcaeb9600, (q31_t)0x74771ee2, (q31_t)0xcae5de64, + (q31_t)0x74748371, (q31_t)0xcae026e8, (q31_t)0x7471e7b8, (q31_t)0xcada6f8d, (q31_t)0x746f4bb8, (q31_t)0xcad4b853, (q31_t)0x746caf70, (q31_t)0xcacf013a, + (q31_t)0x746a12df, (q31_t)0xcac94a42, (q31_t)0x74677608, (q31_t)0xcac3936b, (q31_t)0x7464d8e8, (q31_t)0xcabddcb4, (q31_t)0x74623b80, (q31_t)0xcab8261e, + (q31_t)0x745f9dd1, (q31_t)0xcab26fa9, (q31_t)0x745cffda, (q31_t)0xcaacb955, (q31_t)0x745a619b, (q31_t)0xcaa70322, (q31_t)0x7457c314, (q31_t)0xcaa14d10, + (q31_t)0x74552446, (q31_t)0xca9b971e, (q31_t)0x74528530, (q31_t)0xca95e14e, (q31_t)0x744fe5d2, (q31_t)0xca902b9f, (q31_t)0x744d462c, (q31_t)0xca8a7610, + (q31_t)0x744aa63f, (q31_t)0xca84c0a3, (q31_t)0x7448060a, (q31_t)0xca7f0b56, (q31_t)0x7445658d, (q31_t)0xca79562b, (q31_t)0x7442c4c8, (q31_t)0xca73a120, + (q31_t)0x744023bc, (q31_t)0xca6dec37, (q31_t)0x743d8268, (q31_t)0xca68376e, (q31_t)0x743ae0cc, (q31_t)0xca6282c7, (q31_t)0x74383ee9, (q31_t)0xca5cce40, + (q31_t)0x74359cbd, (q31_t)0xca5719db, (q31_t)0x7432fa4b, (q31_t)0xca516597, (q31_t)0x74305790, (q31_t)0xca4bb174, (q31_t)0x742db48e, (q31_t)0xca45fd72, + (q31_t)0x742b1144, (q31_t)0xca404992, (q31_t)0x74286db3, (q31_t)0xca3a95d2, (q31_t)0x7425c9da, (q31_t)0xca34e234, (q31_t)0x742325b9, (q31_t)0xca2f2eb6, + (q31_t)0x74208150, (q31_t)0xca297b5a, (q31_t)0x741ddca0, (q31_t)0xca23c820, (q31_t)0x741b37a9, (q31_t)0xca1e1506, (q31_t)0x74189269, (q31_t)0xca18620e, + (q31_t)0x7415ece2, (q31_t)0xca12af37, (q31_t)0x74134714, (q31_t)0xca0cfc81, (q31_t)0x7410a0fe, (q31_t)0xca0749ec, (q31_t)0x740dfaa0, (q31_t)0xca019779, + (q31_t)0x740b53fb, (q31_t)0xc9fbe527, (q31_t)0x7408ad0e, (q31_t)0xc9f632f6, (q31_t)0x740605d9, (q31_t)0xc9f080e7, (q31_t)0x74035e5d, (q31_t)0xc9eacef9, + (q31_t)0x7400b69a, (q31_t)0xc9e51d2d, (q31_t)0x73fe0e8f, (q31_t)0xc9df6b81, (q31_t)0x73fb663c, (q31_t)0xc9d9b9f7, (q31_t)0x73f8bda2, (q31_t)0xc9d4088f, + (q31_t)0x73f614c0, (q31_t)0xc9ce5748, (q31_t)0x73f36b97, (q31_t)0xc9c8a622, (q31_t)0x73f0c226, (q31_t)0xc9c2f51e, (q31_t)0x73ee186e, (q31_t)0xc9bd443c, + (q31_t)0x73eb6e6e, (q31_t)0xc9b7937a, (q31_t)0x73e8c426, (q31_t)0xc9b1e2db, (q31_t)0x73e61997, (q31_t)0xc9ac325d, (q31_t)0x73e36ec1, (q31_t)0xc9a68200, + (q31_t)0x73e0c3a3, (q31_t)0xc9a0d1c5, (q31_t)0x73de183e, (q31_t)0xc99b21ab, (q31_t)0x73db6c91, (q31_t)0xc99571b3, (q31_t)0x73d8c09d, (q31_t)0xc98fc1dc, + (q31_t)0x73d61461, (q31_t)0xc98a1227, (q31_t)0x73d367de, (q31_t)0xc9846294, (q31_t)0x73d0bb13, (q31_t)0xc97eb322, (q31_t)0x73ce0e01, (q31_t)0xc97903d2, + (q31_t)0x73cb60a8, (q31_t)0xc97354a4, (q31_t)0x73c8b307, (q31_t)0xc96da597, (q31_t)0x73c6051f, (q31_t)0xc967f6ac, (q31_t)0x73c356ef, (q31_t)0xc96247e2, + (q31_t)0x73c0a878, (q31_t)0xc95c993a, (q31_t)0x73bdf9b9, (q31_t)0xc956eab4, (q31_t)0x73bb4ab3, (q31_t)0xc9513c50, (q31_t)0x73b89b66, (q31_t)0xc94b8e0d, + (q31_t)0x73b5ebd1, (q31_t)0xc945dfec, (q31_t)0x73b33bf5, (q31_t)0xc94031ed, (q31_t)0x73b08bd1, (q31_t)0xc93a8410, (q31_t)0x73addb67, (q31_t)0xc934d654, + (q31_t)0x73ab2ab4, (q31_t)0xc92f28ba, (q31_t)0x73a879bb, (q31_t)0xc9297b42, (q31_t)0x73a5c87a, (q31_t)0xc923cdec, (q31_t)0x73a316f2, (q31_t)0xc91e20b8, + (q31_t)0x73a06522, (q31_t)0xc91873a5, (q31_t)0x739db30b, (q31_t)0xc912c6b5, (q31_t)0x739b00ad, (q31_t)0xc90d19e6, (q31_t)0x73984e07, (q31_t)0xc9076d39, + (q31_t)0x73959b1b, (q31_t)0xc901c0ae, (q31_t)0x7392e7e6, (q31_t)0xc8fc1445, (q31_t)0x7390346b, (q31_t)0xc8f667fe, (q31_t)0x738d80a8, (q31_t)0xc8f0bbd9, + (q31_t)0x738acc9e, (q31_t)0xc8eb0fd6, (q31_t)0x7388184d, (q31_t)0xc8e563f5, (q31_t)0x738563b5, (q31_t)0xc8dfb836, (q31_t)0x7382aed5, (q31_t)0xc8da0c99, + (q31_t)0x737ff9ae, (q31_t)0xc8d4611d, (q31_t)0x737d4440, (q31_t)0xc8ceb5c4, (q31_t)0x737a8e8a, (q31_t)0xc8c90a8d, (q31_t)0x7377d88d, (q31_t)0xc8c35f78, + (q31_t)0x73752249, (q31_t)0xc8bdb485, (q31_t)0x73726bbe, (q31_t)0xc8b809b4, (q31_t)0x736fb4ec, (q31_t)0xc8b25f06, (q31_t)0x736cfdd2, (q31_t)0xc8acb479, + (q31_t)0x736a4671, (q31_t)0xc8a70a0e, (q31_t)0x73678ec9, (q31_t)0xc8a15fc6, (q31_t)0x7364d6da, (q31_t)0xc89bb5a0, (q31_t)0x73621ea4, (q31_t)0xc8960b9c, + (q31_t)0x735f6626, (q31_t)0xc89061ba, (q31_t)0x735cad61, (q31_t)0xc88ab7fa, (q31_t)0x7359f456, (q31_t)0xc8850e5d, (q31_t)0x73573b03, (q31_t)0xc87f64e2, + (q31_t)0x73548168, (q31_t)0xc879bb89, (q31_t)0x7351c787, (q31_t)0xc8741252, (q31_t)0x734f0d5f, (q31_t)0xc86e693d, (q31_t)0x734c52ef, (q31_t)0xc868c04b, + (q31_t)0x73499838, (q31_t)0xc863177b, (q31_t)0x7346dd3a, (q31_t)0xc85d6ece, (q31_t)0x734421f6, (q31_t)0xc857c642, (q31_t)0x7341666a, (q31_t)0xc8521dd9, + (q31_t)0x733eaa96, (q31_t)0xc84c7593, (q31_t)0x733bee7c, (q31_t)0xc846cd6e, (q31_t)0x7339321b, (q31_t)0xc841256d, (q31_t)0x73367572, (q31_t)0xc83b7d8d, + (q31_t)0x7333b883, (q31_t)0xc835d5d0, (q31_t)0x7330fb4d, (q31_t)0xc8302e35, (q31_t)0x732e3dcf, (q31_t)0xc82a86bd, (q31_t)0x732b800a, (q31_t)0xc824df67, + (q31_t)0x7328c1ff, (q31_t)0xc81f3834, (q31_t)0x732603ac, (q31_t)0xc8199123, (q31_t)0x73234512, (q31_t)0xc813ea35, (q31_t)0x73208632, (q31_t)0xc80e4369, + (q31_t)0x731dc70a, (q31_t)0xc8089cbf, (q31_t)0x731b079b, (q31_t)0xc802f638, (q31_t)0x731847e5, (q31_t)0xc7fd4fd4, (q31_t)0x731587e8, (q31_t)0xc7f7a992, + (q31_t)0x7312c7a5, (q31_t)0xc7f20373, (q31_t)0x7310071a, (q31_t)0xc7ec5d76, (q31_t)0x730d4648, (q31_t)0xc7e6b79c, (q31_t)0x730a8530, (q31_t)0xc7e111e5, + (q31_t)0x7307c3d0, (q31_t)0xc7db6c50, (q31_t)0x73050229, (q31_t)0xc7d5c6de, (q31_t)0x7302403c, (q31_t)0xc7d0218e, (q31_t)0x72ff7e07, (q31_t)0xc7ca7c61, + (q31_t)0x72fcbb8c, (q31_t)0xc7c4d757, (q31_t)0x72f9f8c9, (q31_t)0xc7bf3270, (q31_t)0x72f735c0, (q31_t)0xc7b98dab, (q31_t)0x72f47270, (q31_t)0xc7b3e909, + (q31_t)0x72f1aed9, (q31_t)0xc7ae4489, (q31_t)0x72eeeafb, (q31_t)0xc7a8a02c, (q31_t)0x72ec26d6, (q31_t)0xc7a2fbf3, (q31_t)0x72e9626a, (q31_t)0xc79d57db, + (q31_t)0x72e69db7, (q31_t)0xc797b3e7, (q31_t)0x72e3d8be, (q31_t)0xc7921015, (q31_t)0x72e1137d, (q31_t)0xc78c6c67, (q31_t)0x72de4df6, (q31_t)0xc786c8db, + (q31_t)0x72db8828, (q31_t)0xc7812572, (q31_t)0x72d8c213, (q31_t)0xc77b822b, (q31_t)0x72d5fbb7, (q31_t)0xc775df08, (q31_t)0x72d33514, (q31_t)0xc7703c08, + (q31_t)0x72d06e2b, (q31_t)0xc76a992a, (q31_t)0x72cda6fb, (q31_t)0xc764f66f, (q31_t)0x72cadf83, (q31_t)0xc75f53d7, (q31_t)0x72c817c6, (q31_t)0xc759b163, + (q31_t)0x72c54fc1, (q31_t)0xc7540f11, (q31_t)0x72c28775, (q31_t)0xc74e6ce2, (q31_t)0x72bfbee3, (q31_t)0xc748cad6, (q31_t)0x72bcf60a, (q31_t)0xc74328ed, + (q31_t)0x72ba2cea, (q31_t)0xc73d8727, (q31_t)0x72b76383, (q31_t)0xc737e584, (q31_t)0x72b499d6, (q31_t)0xc7324404, (q31_t)0x72b1cfe1, (q31_t)0xc72ca2a7, + (q31_t)0x72af05a7, (q31_t)0xc727016d, (q31_t)0x72ac3b25, (q31_t)0xc7216056, (q31_t)0x72a9705c, (q31_t)0xc71bbf62, (q31_t)0x72a6a54d, (q31_t)0xc7161e92, + (q31_t)0x72a3d9f7, (q31_t)0xc7107de4, (q31_t)0x72a10e5b, (q31_t)0xc70add5a, (q31_t)0x729e4277, (q31_t)0xc7053cf2, (q31_t)0x729b764d, (q31_t)0xc6ff9cae, + (q31_t)0x7298a9dd, (q31_t)0xc6f9fc8d, (q31_t)0x7295dd25, (q31_t)0xc6f45c8f, (q31_t)0x72931027, (q31_t)0xc6eebcb5, (q31_t)0x729042e3, (q31_t)0xc6e91cfd, + (q31_t)0x728d7557, (q31_t)0xc6e37d69, (q31_t)0x728aa785, (q31_t)0xc6ddddf8, (q31_t)0x7287d96c, (q31_t)0xc6d83eab, (q31_t)0x72850b0d, (q31_t)0xc6d29f80, + (q31_t)0x72823c67, (q31_t)0xc6cd0079, (q31_t)0x727f6d7a, (q31_t)0xc6c76195, (q31_t)0x727c9e47, (q31_t)0xc6c1c2d4, (q31_t)0x7279cecd, (q31_t)0xc6bc2437, + (q31_t)0x7276ff0d, (q31_t)0xc6b685bd, (q31_t)0x72742f05, (q31_t)0xc6b0e767, (q31_t)0x72715eb8, (q31_t)0xc6ab4933, (q31_t)0x726e8e23, (q31_t)0xc6a5ab23, + (q31_t)0x726bbd48, (q31_t)0xc6a00d37, (q31_t)0x7268ec27, (q31_t)0xc69a6f6e, (q31_t)0x72661abf, (q31_t)0xc694d1c8, (q31_t)0x72634910, (q31_t)0xc68f3446, + (q31_t)0x7260771b, (q31_t)0xc68996e7, (q31_t)0x725da4df, (q31_t)0xc683f9ab, (q31_t)0x725ad25d, (q31_t)0xc67e5c93, (q31_t)0x7257ff94, (q31_t)0xc678bf9f, + (q31_t)0x72552c85, (q31_t)0xc67322ce, (q31_t)0x7252592f, (q31_t)0xc66d8620, (q31_t)0x724f8593, (q31_t)0xc667e996, (q31_t)0x724cb1b0, (q31_t)0xc6624d30, + (q31_t)0x7249dd86, (q31_t)0xc65cb0ed, (q31_t)0x72470916, (q31_t)0xc65714cd, (q31_t)0x72443460, (q31_t)0xc65178d1, (q31_t)0x72415f63, (q31_t)0xc64bdcf9, + (q31_t)0x723e8a20, (q31_t)0xc6464144, (q31_t)0x723bb496, (q31_t)0xc640a5b3, (q31_t)0x7238dec5, (q31_t)0xc63b0a46, (q31_t)0x723608af, (q31_t)0xc6356efc, + (q31_t)0x72333251, (q31_t)0xc62fd3d6, (q31_t)0x72305bae, (q31_t)0xc62a38d4, (q31_t)0x722d84c4, (q31_t)0xc6249df5, (q31_t)0x722aad93, (q31_t)0xc61f033a, + (q31_t)0x7227d61c, (q31_t)0xc61968a2, (q31_t)0x7224fe5f, (q31_t)0xc613ce2f, (q31_t)0x7222265b, (q31_t)0xc60e33df, (q31_t)0x721f4e11, (q31_t)0xc60899b2, + (q31_t)0x721c7580, (q31_t)0xc602ffaa, (q31_t)0x72199ca9, (q31_t)0xc5fd65c5, (q31_t)0x7216c38c, (q31_t)0xc5f7cc04, (q31_t)0x7213ea28, (q31_t)0xc5f23267, + (q31_t)0x7211107e, (q31_t)0xc5ec98ee, (q31_t)0x720e368d, (q31_t)0xc5e6ff98, (q31_t)0x720b5c57, (q31_t)0xc5e16667, (q31_t)0x720881d9, (q31_t)0xc5dbcd59, + (q31_t)0x7205a716, (q31_t)0xc5d6346f, (q31_t)0x7202cc0c, (q31_t)0xc5d09ba9, (q31_t)0x71fff0bc, (q31_t)0xc5cb0307, (q31_t)0x71fd1525, (q31_t)0xc5c56a89, + (q31_t)0x71fa3949, (q31_t)0xc5bfd22e, (q31_t)0x71f75d25, (q31_t)0xc5ba39f8, (q31_t)0x71f480bc, (q31_t)0xc5b4a1e5, (q31_t)0x71f1a40c, (q31_t)0xc5af09f7, + (q31_t)0x71eec716, (q31_t)0xc5a9722c, (q31_t)0x71ebe9da, (q31_t)0xc5a3da86, (q31_t)0x71e90c57, (q31_t)0xc59e4303, (q31_t)0x71e62e8f, (q31_t)0xc598aba5, + (q31_t)0x71e35080, (q31_t)0xc593146a, (q31_t)0x71e0722a, (q31_t)0xc58d7d54, (q31_t)0x71dd938f, (q31_t)0xc587e661, (q31_t)0x71dab4ad, (q31_t)0xc5824f93, + (q31_t)0x71d7d585, (q31_t)0xc57cb8e9, (q31_t)0x71d4f617, (q31_t)0xc5772263, (q31_t)0x71d21662, (q31_t)0xc5718c00, (q31_t)0x71cf3667, (q31_t)0xc56bf5c2, + (q31_t)0x71cc5626, (q31_t)0xc5665fa9, (q31_t)0x71c9759f, (q31_t)0xc560c9b3, (q31_t)0x71c694d2, (q31_t)0xc55b33e2, (q31_t)0x71c3b3bf, (q31_t)0xc5559e34, + (q31_t)0x71c0d265, (q31_t)0xc55008ab, (q31_t)0x71bdf0c5, (q31_t)0xc54a7346, (q31_t)0x71bb0edf, (q31_t)0xc544de05, (q31_t)0x71b82cb3, (q31_t)0xc53f48e9, + (q31_t)0x71b54a41, (q31_t)0xc539b3f1, (q31_t)0x71b26788, (q31_t)0xc5341f1d, (q31_t)0x71af848a, (q31_t)0xc52e8a6d, (q31_t)0x71aca145, (q31_t)0xc528f5e1, + (q31_t)0x71a9bdba, (q31_t)0xc523617a, (q31_t)0x71a6d9e9, (q31_t)0xc51dcd37, (q31_t)0x71a3f5d2, (q31_t)0xc5183919, (q31_t)0x71a11175, (q31_t)0xc512a51f, + (q31_t)0x719e2cd2, (q31_t)0xc50d1149, (q31_t)0x719b47e9, (q31_t)0xc5077d97, (q31_t)0x719862b9, (q31_t)0xc501ea0a, (q31_t)0x71957d44, (q31_t)0xc4fc56a2, + (q31_t)0x71929789, (q31_t)0xc4f6c35d, (q31_t)0x718fb187, (q31_t)0xc4f1303d, (q31_t)0x718ccb3f, (q31_t)0xc4eb9d42, (q31_t)0x7189e4b2, (q31_t)0xc4e60a6b, + (q31_t)0x7186fdde, (q31_t)0xc4e077b8, (q31_t)0x718416c4, (q31_t)0xc4dae52a, (q31_t)0x71812f65, (q31_t)0xc4d552c1, (q31_t)0x717e47bf, (q31_t)0xc4cfc07c, + (q31_t)0x717b5fd3, (q31_t)0xc4ca2e5b, (q31_t)0x717877a1, (q31_t)0xc4c49c5f, (q31_t)0x71758f29, (q31_t)0xc4bf0a87, (q31_t)0x7172a66c, (q31_t)0xc4b978d4, + (q31_t)0x716fbd68, (q31_t)0xc4b3e746, (q31_t)0x716cd41e, (q31_t)0xc4ae55dc, (q31_t)0x7169ea8f, (q31_t)0xc4a8c497, (q31_t)0x716700b9, (q31_t)0xc4a33376, + (q31_t)0x7164169d, (q31_t)0xc49da27a, (q31_t)0x71612c3c, (q31_t)0xc49811a3, (q31_t)0x715e4194, (q31_t)0xc49280f0, (q31_t)0x715b56a7, (q31_t)0xc48cf062, + (q31_t)0x71586b74, (q31_t)0xc4875ff9, (q31_t)0x71557ffa, (q31_t)0xc481cfb4, (q31_t)0x7152943b, (q31_t)0xc47c3f94, (q31_t)0x714fa836, (q31_t)0xc476af98, + (q31_t)0x714cbbeb, (q31_t)0xc4711fc2, (q31_t)0x7149cf5a, (q31_t)0xc46b9010, (q31_t)0x7146e284, (q31_t)0xc4660083, (q31_t)0x7143f567, (q31_t)0xc460711b, + (q31_t)0x71410805, (q31_t)0xc45ae1d7, (q31_t)0x713e1a5c, (q31_t)0xc45552b8, (q31_t)0x713b2c6e, (q31_t)0xc44fc3be, (q31_t)0x71383e3a, (q31_t)0xc44a34e9, + (q31_t)0x71354fc0, (q31_t)0xc444a639, (q31_t)0x71326101, (q31_t)0xc43f17ad, (q31_t)0x712f71fb, (q31_t)0xc4398947, (q31_t)0x712c82b0, (q31_t)0xc433fb05, + (q31_t)0x7129931f, (q31_t)0xc42e6ce8, (q31_t)0x7126a348, (q31_t)0xc428def0, (q31_t)0x7123b32b, (q31_t)0xc423511d, (q31_t)0x7120c2c8, (q31_t)0xc41dc36f, + (q31_t)0x711dd220, (q31_t)0xc41835e6, (q31_t)0x711ae132, (q31_t)0xc412a882, (q31_t)0x7117effe, (q31_t)0xc40d1b42, (q31_t)0x7114fe84, (q31_t)0xc4078e28, + (q31_t)0x71120cc5, (q31_t)0xc4020133, (q31_t)0x710f1ac0, (q31_t)0xc3fc7462, (q31_t)0x710c2875, (q31_t)0xc3f6e7b7, (q31_t)0x710935e4, (q31_t)0xc3f15b31, + (q31_t)0x7106430e, (q31_t)0xc3ebced0, (q31_t)0x71034ff2, (q31_t)0xc3e64294, (q31_t)0x71005c90, (q31_t)0xc3e0b67d, (q31_t)0x70fd68e9, (q31_t)0xc3db2a8b, + (q31_t)0x70fa74fc, (q31_t)0xc3d59ebe, (q31_t)0x70f780c9, (q31_t)0xc3d01316, (q31_t)0x70f48c50, (q31_t)0xc3ca8793, (q31_t)0x70f19792, (q31_t)0xc3c4fc36, + (q31_t)0x70eea28e, (q31_t)0xc3bf70fd, (q31_t)0x70ebad45, (q31_t)0xc3b9e5ea, (q31_t)0x70e8b7b5, (q31_t)0xc3b45afc, (q31_t)0x70e5c1e1, (q31_t)0xc3aed034, + (q31_t)0x70e2cbc6, (q31_t)0xc3a94590, (q31_t)0x70dfd566, (q31_t)0xc3a3bb12, (q31_t)0x70dcdec0, (q31_t)0xc39e30b8, (q31_t)0x70d9e7d5, (q31_t)0xc398a685, + (q31_t)0x70d6f0a4, (q31_t)0xc3931c76, (q31_t)0x70d3f92d, (q31_t)0xc38d928d, (q31_t)0x70d10171, (q31_t)0xc38808c9, (q31_t)0x70ce096f, (q31_t)0xc3827f2a, + (q31_t)0x70cb1128, (q31_t)0xc37cf5b0, (q31_t)0x70c8189b, (q31_t)0xc3776c5c, (q31_t)0x70c51fc8, (q31_t)0xc371e32d, (q31_t)0x70c226b0, (q31_t)0xc36c5a24, + (q31_t)0x70bf2d53, (q31_t)0xc366d140, (q31_t)0x70bc33b0, (q31_t)0xc3614881, (q31_t)0x70b939c7, (q31_t)0xc35bbfe8, (q31_t)0x70b63f99, (q31_t)0xc3563774, + (q31_t)0x70b34525, (q31_t)0xc350af26, (q31_t)0x70b04a6b, (q31_t)0xc34b26fc, (q31_t)0x70ad4f6d, (q31_t)0xc3459ef9, (q31_t)0x70aa5428, (q31_t)0xc340171b, + (q31_t)0x70a7589f, (q31_t)0xc33a8f62, (q31_t)0x70a45ccf, (q31_t)0xc33507cf, (q31_t)0x70a160ba, (q31_t)0xc32f8061, (q31_t)0x709e6460, (q31_t)0xc329f919, + (q31_t)0x709b67c0, (q31_t)0xc32471f7, (q31_t)0x70986adb, (q31_t)0xc31eeaf9, (q31_t)0x70956db1, (q31_t)0xc3196422, (q31_t)0x70927041, (q31_t)0xc313dd70, + (q31_t)0x708f728b, (q31_t)0xc30e56e4, (q31_t)0x708c7490, (q31_t)0xc308d07d, (q31_t)0x70897650, (q31_t)0xc3034a3c, (q31_t)0x708677ca, (q31_t)0xc2fdc420, + (q31_t)0x708378ff, (q31_t)0xc2f83e2a, (q31_t)0x708079ee, (q31_t)0xc2f2b85a, (q31_t)0x707d7a98, (q31_t)0xc2ed32af, (q31_t)0x707a7afd, (q31_t)0xc2e7ad2a, + (q31_t)0x70777b1c, (q31_t)0xc2e227cb, (q31_t)0x70747af6, (q31_t)0xc2dca291, (q31_t)0x70717a8a, (q31_t)0xc2d71d7e, (q31_t)0x706e79d9, (q31_t)0xc2d1988f, + (q31_t)0x706b78e3, (q31_t)0xc2cc13c7, (q31_t)0x706877a7, (q31_t)0xc2c68f24, (q31_t)0x70657626, (q31_t)0xc2c10aa7, (q31_t)0x70627460, (q31_t)0xc2bb8650, + (q31_t)0x705f7255, (q31_t)0xc2b6021f, (q31_t)0x705c7004, (q31_t)0xc2b07e14, (q31_t)0x70596d6d, (q31_t)0xc2aafa2e, (q31_t)0x70566a92, (q31_t)0xc2a5766e, + (q31_t)0x70536771, (q31_t)0xc29ff2d4, (q31_t)0x7050640b, (q31_t)0xc29a6f60, (q31_t)0x704d6060, (q31_t)0xc294ec12, (q31_t)0x704a5c6f, (q31_t)0xc28f68e9, + (q31_t)0x70475839, (q31_t)0xc289e5e7, (q31_t)0x704453be, (q31_t)0xc284630a, (q31_t)0x70414efd, (q31_t)0xc27ee054, (q31_t)0x703e49f8, (q31_t)0xc2795dc3, + (q31_t)0x703b44ad, (q31_t)0xc273db58, (q31_t)0x70383f1d, (q31_t)0xc26e5913, (q31_t)0x70353947, (q31_t)0xc268d6f5, (q31_t)0x7032332d, (q31_t)0xc26354fc, + (q31_t)0x702f2ccd, (q31_t)0xc25dd329, (q31_t)0x702c2628, (q31_t)0xc258517c, (q31_t)0x70291f3e, (q31_t)0xc252cff5, (q31_t)0x7026180e, (q31_t)0xc24d4e95, + (q31_t)0x7023109a, (q31_t)0xc247cd5a, (q31_t)0x702008e0, (q31_t)0xc2424c46, (q31_t)0x701d00e1, (q31_t)0xc23ccb57, (q31_t)0x7019f89d, (q31_t)0xc2374a8f, + (q31_t)0x7016f014, (q31_t)0xc231c9ec, (q31_t)0x7013e746, (q31_t)0xc22c4970, (q31_t)0x7010de32, (q31_t)0xc226c91a, (q31_t)0x700dd4da, (q31_t)0xc22148ea, + (q31_t)0x700acb3c, (q31_t)0xc21bc8e1, (q31_t)0x7007c159, (q31_t)0xc21648fd, (q31_t)0x7004b731, (q31_t)0xc210c940, (q31_t)0x7001acc4, (q31_t)0xc20b49a9, + (q31_t)0x6ffea212, (q31_t)0xc205ca38, (q31_t)0x6ffb971b, (q31_t)0xc2004aed, (q31_t)0x6ff88bde, (q31_t)0xc1facbc9, (q31_t)0x6ff5805d, (q31_t)0xc1f54cca, + (q31_t)0x6ff27497, (q31_t)0xc1efcdf3, (q31_t)0x6fef688b, (q31_t)0xc1ea4f41, (q31_t)0x6fec5c3b, (q31_t)0xc1e4d0b6, (q31_t)0x6fe94fa5, (q31_t)0xc1df5251, + (q31_t)0x6fe642ca, (q31_t)0xc1d9d412, (q31_t)0x6fe335ab, (q31_t)0xc1d455f9, (q31_t)0x6fe02846, (q31_t)0xc1ced807, (q31_t)0x6fdd1a9c, (q31_t)0xc1c95a3c, + (q31_t)0x6fda0cae, (q31_t)0xc1c3dc97, (q31_t)0x6fd6fe7a, (q31_t)0xc1be5f18, (q31_t)0x6fd3f001, (q31_t)0xc1b8e1bf, (q31_t)0x6fd0e144, (q31_t)0xc1b3648d, + (q31_t)0x6fcdd241, (q31_t)0xc1ade781, (q31_t)0x6fcac2fa, (q31_t)0xc1a86a9c, (q31_t)0x6fc7b36d, (q31_t)0xc1a2edde, (q31_t)0x6fc4a39c, (q31_t)0xc19d7145, + (q31_t)0x6fc19385, (q31_t)0xc197f4d4, (q31_t)0x6fbe832a, (q31_t)0xc1927888, (q31_t)0x6fbb728a, (q31_t)0xc18cfc63, (q31_t)0x6fb861a4, (q31_t)0xc1878065, + (q31_t)0x6fb5507a, (q31_t)0xc182048d, (q31_t)0x6fb23f0b, (q31_t)0xc17c88dc, (q31_t)0x6faf2d57, (q31_t)0xc1770d52, (q31_t)0x6fac1b5f, (q31_t)0xc17191ee, + (q31_t)0x6fa90921, (q31_t)0xc16c16b0, (q31_t)0x6fa5f69e, (q31_t)0xc1669b99, (q31_t)0x6fa2e3d7, (q31_t)0xc16120a9, (q31_t)0x6f9fd0cb, (q31_t)0xc15ba5df, + (q31_t)0x6f9cbd79, (q31_t)0xc1562b3d, (q31_t)0x6f99a9e3, (q31_t)0xc150b0c0, (q31_t)0x6f969608, (q31_t)0xc14b366b, (q31_t)0x6f9381e9, (q31_t)0xc145bc3c, + (q31_t)0x6f906d84, (q31_t)0xc1404233, (q31_t)0x6f8d58db, (q31_t)0xc13ac852, (q31_t)0x6f8a43ed, (q31_t)0xc1354e97, (q31_t)0x6f872eba, (q31_t)0xc12fd503, + (q31_t)0x6f841942, (q31_t)0xc12a5b95, (q31_t)0x6f810386, (q31_t)0xc124e24f, (q31_t)0x6f7ded84, (q31_t)0xc11f692f, (q31_t)0x6f7ad73e, (q31_t)0xc119f036, + (q31_t)0x6f77c0b3, (q31_t)0xc1147764, (q31_t)0x6f74a9e4, (q31_t)0xc10efeb8, (q31_t)0x6f7192cf, (q31_t)0xc1098634, (q31_t)0x6f6e7b76, (q31_t)0xc1040dd6, + (q31_t)0x6f6b63d8, (q31_t)0xc0fe959f, (q31_t)0x6f684bf6, (q31_t)0xc0f91d8f, (q31_t)0x6f6533ce, (q31_t)0xc0f3a5a6, (q31_t)0x6f621b62, (q31_t)0xc0ee2de3, + (q31_t)0x6f5f02b2, (q31_t)0xc0e8b648, (q31_t)0x6f5be9bc, (q31_t)0xc0e33ed4, (q31_t)0x6f58d082, (q31_t)0xc0ddc786, (q31_t)0x6f55b703, (q31_t)0xc0d8505f, + (q31_t)0x6f529d40, (q31_t)0xc0d2d960, (q31_t)0x6f4f8338, (q31_t)0xc0cd6287, (q31_t)0x6f4c68eb, (q31_t)0xc0c7ebd6, (q31_t)0x6f494e5a, (q31_t)0xc0c2754b, + (q31_t)0x6f463383, (q31_t)0xc0bcfee7, (q31_t)0x6f431869, (q31_t)0xc0b788ab, (q31_t)0x6f3ffd09, (q31_t)0xc0b21295, (q31_t)0x6f3ce165, (q31_t)0xc0ac9ca6, + (q31_t)0x6f39c57d, (q31_t)0xc0a726df, (q31_t)0x6f36a94f, (q31_t)0xc0a1b13e, (q31_t)0x6f338cde, (q31_t)0xc09c3bc5, (q31_t)0x6f307027, (q31_t)0xc096c673, + (q31_t)0x6f2d532c, (q31_t)0xc0915148, (q31_t)0x6f2a35ed, (q31_t)0xc08bdc44, (q31_t)0x6f271868, (q31_t)0xc0866767, (q31_t)0x6f23faa0, (q31_t)0xc080f2b1, + (q31_t)0x6f20dc92, (q31_t)0xc07b7e23, (q31_t)0x6f1dbe41, (q31_t)0xc07609bb, (q31_t)0x6f1a9faa, (q31_t)0xc070957b, (q31_t)0x6f1780cf, (q31_t)0xc06b2162, + (q31_t)0x6f1461b0, (q31_t)0xc065ad70, (q31_t)0x6f11424c, (q31_t)0xc06039a6, (q31_t)0x6f0e22a3, (q31_t)0xc05ac603, (q31_t)0x6f0b02b6, (q31_t)0xc0555287, + (q31_t)0x6f07e285, (q31_t)0xc04fdf32, (q31_t)0x6f04c20f, (q31_t)0xc04a6c05, (q31_t)0x6f01a155, (q31_t)0xc044f8fe, (q31_t)0x6efe8056, (q31_t)0xc03f8620, + (q31_t)0x6efb5f12, (q31_t)0xc03a1368, (q31_t)0x6ef83d8a, (q31_t)0xc034a0d8, (q31_t)0x6ef51bbe, (q31_t)0xc02f2e6f, (q31_t)0x6ef1f9ad, (q31_t)0xc029bc2e, + (q31_t)0x6eeed758, (q31_t)0xc0244a14, (q31_t)0x6eebb4bf, (q31_t)0xc01ed821, (q31_t)0x6ee891e1, (q31_t)0xc0196656, (q31_t)0x6ee56ebe, (q31_t)0xc013f4b2, + (q31_t)0x6ee24b57, (q31_t)0xc00e8336, (q31_t)0x6edf27ac, (q31_t)0xc00911e1, (q31_t)0x6edc03bc, (q31_t)0xc003a0b3, (q31_t)0x6ed8df88, (q31_t)0xbffe2fad, + (q31_t)0x6ed5bb10, (q31_t)0xbff8bece, (q31_t)0x6ed29653, (q31_t)0xbff34e17, (q31_t)0x6ecf7152, (q31_t)0xbfeddd88, (q31_t)0x6ecc4c0d, (q31_t)0xbfe86d20, + (q31_t)0x6ec92683, (q31_t)0xbfe2fcdf, (q31_t)0x6ec600b5, (q31_t)0xbfdd8cc6, (q31_t)0x6ec2daa2, (q31_t)0xbfd81cd5, (q31_t)0x6ebfb44b, (q31_t)0xbfd2ad0b, + (q31_t)0x6ebc8db0, (q31_t)0xbfcd3d69, (q31_t)0x6eb966d1, (q31_t)0xbfc7cdee, (q31_t)0x6eb63fad, (q31_t)0xbfc25e9b, (q31_t)0x6eb31845, (q31_t)0xbfbcef70, + (q31_t)0x6eaff099, (q31_t)0xbfb7806c, (q31_t)0x6eacc8a8, (q31_t)0xbfb21190, (q31_t)0x6ea9a073, (q31_t)0xbfaca2dc, (q31_t)0x6ea677fa, (q31_t)0xbfa7344f, + (q31_t)0x6ea34f3d, (q31_t)0xbfa1c5ea, (q31_t)0x6ea0263b, (q31_t)0xbf9c57ac, (q31_t)0x6e9cfcf5, (q31_t)0xbf96e997, (q31_t)0x6e99d36b, (q31_t)0xbf917ba9, + (q31_t)0x6e96a99d, (q31_t)0xbf8c0de3, (q31_t)0x6e937f8a, (q31_t)0xbf86a044, (q31_t)0x6e905534, (q31_t)0xbf8132ce, (q31_t)0x6e8d2a99, (q31_t)0xbf7bc57f, + (q31_t)0x6e89ffb9, (q31_t)0xbf765858, (q31_t)0x6e86d496, (q31_t)0xbf70eb59, (q31_t)0x6e83a92f, (q31_t)0xbf6b7e81, (q31_t)0x6e807d83, (q31_t)0xbf6611d2, + (q31_t)0x6e7d5193, (q31_t)0xbf60a54a, (q31_t)0x6e7a255f, (q31_t)0xbf5b38ea, (q31_t)0x6e76f8e7, (q31_t)0xbf55ccb2, (q31_t)0x6e73cc2b, (q31_t)0xbf5060a2, + (q31_t)0x6e709f2a, (q31_t)0xbf4af4ba, (q31_t)0x6e6d71e6, (q31_t)0xbf4588fa, (q31_t)0x6e6a445d, (q31_t)0xbf401d61, (q31_t)0x6e671690, (q31_t)0xbf3ab1f1, + (q31_t)0x6e63e87f, (q31_t)0xbf3546a8, (q31_t)0x6e60ba2a, (q31_t)0xbf2fdb88, (q31_t)0x6e5d8b91, (q31_t)0xbf2a708f, (q31_t)0x6e5a5cb4, (q31_t)0xbf2505bf, + (q31_t)0x6e572d93, (q31_t)0xbf1f9b16, (q31_t)0x6e53fe2e, (q31_t)0xbf1a3096, (q31_t)0x6e50ce84, (q31_t)0xbf14c63d, (q31_t)0x6e4d9e97, (q31_t)0xbf0f5c0d, + (q31_t)0x6e4a6e66, (q31_t)0xbf09f205, (q31_t)0x6e473df0, (q31_t)0xbf048824, (q31_t)0x6e440d37, (q31_t)0xbeff1e6c, (q31_t)0x6e40dc39, (q31_t)0xbef9b4dc, + (q31_t)0x6e3daaf8, (q31_t)0xbef44b74, (q31_t)0x6e3a7972, (q31_t)0xbeeee234, (q31_t)0x6e3747a9, (q31_t)0xbee9791c, (q31_t)0x6e34159b, (q31_t)0xbee4102d, + (q31_t)0x6e30e34a, (q31_t)0xbedea765, (q31_t)0x6e2db0b4, (q31_t)0xbed93ec6, (q31_t)0x6e2a7ddb, (q31_t)0xbed3d64f, (q31_t)0x6e274abe, (q31_t)0xbece6e00, + (q31_t)0x6e24175c, (q31_t)0xbec905d9, (q31_t)0x6e20e3b7, (q31_t)0xbec39ddb, (q31_t)0x6e1dafce, (q31_t)0xbebe3605, (q31_t)0x6e1a7ba1, (q31_t)0xbeb8ce57, + (q31_t)0x6e174730, (q31_t)0xbeb366d1, (q31_t)0x6e14127b, (q31_t)0xbeadff74, (q31_t)0x6e10dd82, (q31_t)0xbea8983f, (q31_t)0x6e0da845, (q31_t)0xbea33132, + (q31_t)0x6e0a72c5, (q31_t)0xbe9dca4e, (q31_t)0x6e073d00, (q31_t)0xbe986391, (q31_t)0x6e0406f8, (q31_t)0xbe92fcfe, (q31_t)0x6e00d0ac, (q31_t)0xbe8d9692, + (q31_t)0x6dfd9a1c, (q31_t)0xbe88304f, (q31_t)0x6dfa6348, (q31_t)0xbe82ca35, (q31_t)0x6df72c30, (q31_t)0xbe7d6442, (q31_t)0x6df3f4d4, (q31_t)0xbe77fe78, + (q31_t)0x6df0bd35, (q31_t)0xbe7298d7, (q31_t)0x6ded8552, (q31_t)0xbe6d335e, (q31_t)0x6dea4d2b, (q31_t)0xbe67ce0d, (q31_t)0x6de714c0, (q31_t)0xbe6268e5, + (q31_t)0x6de3dc11, (q31_t)0xbe5d03e6, (q31_t)0x6de0a31f, (q31_t)0xbe579f0f, (q31_t)0x6ddd69e9, (q31_t)0xbe523a60, (q31_t)0x6dda306f, (q31_t)0xbe4cd5da, + (q31_t)0x6dd6f6b1, (q31_t)0xbe47717c, (q31_t)0x6dd3bcaf, (q31_t)0xbe420d47, (q31_t)0x6dd0826a, (q31_t)0xbe3ca93b, (q31_t)0x6dcd47e1, (q31_t)0xbe374557, + (q31_t)0x6dca0d14, (q31_t)0xbe31e19b, (q31_t)0x6dc6d204, (q31_t)0xbe2c7e09, (q31_t)0x6dc396b0, (q31_t)0xbe271a9f, (q31_t)0x6dc05b18, (q31_t)0xbe21b75d, + (q31_t)0x6dbd1f3c, (q31_t)0xbe1c5444, (q31_t)0x6db9e31d, (q31_t)0xbe16f154, (q31_t)0x6db6a6ba, (q31_t)0xbe118e8c, (q31_t)0x6db36a14, (q31_t)0xbe0c2bed, + (q31_t)0x6db02d29, (q31_t)0xbe06c977, (q31_t)0x6daceffb, (q31_t)0xbe01672a, (q31_t)0x6da9b28a, (q31_t)0xbdfc0505, (q31_t)0x6da674d5, (q31_t)0xbdf6a309, + (q31_t)0x6da336dc, (q31_t)0xbdf14135, (q31_t)0x6d9ff89f, (q31_t)0xbdebdf8b, (q31_t)0x6d9cba1f, (q31_t)0xbde67e09, (q31_t)0x6d997b5b, (q31_t)0xbde11cb0, + (q31_t)0x6d963c54, (q31_t)0xbddbbb7f, (q31_t)0x6d92fd09, (q31_t)0xbdd65a78, (q31_t)0x6d8fbd7a, (q31_t)0xbdd0f999, (q31_t)0x6d8c7da8, (q31_t)0xbdcb98e3, + (q31_t)0x6d893d93, (q31_t)0xbdc63856, (q31_t)0x6d85fd39, (q31_t)0xbdc0d7f2, (q31_t)0x6d82bc9d, (q31_t)0xbdbb77b7, (q31_t)0x6d7f7bbc, (q31_t)0xbdb617a4, + (q31_t)0x6d7c3a98, (q31_t)0xbdb0b7bb, (q31_t)0x6d78f931, (q31_t)0xbdab57fa, (q31_t)0x6d75b786, (q31_t)0xbda5f862, (q31_t)0x6d727597, (q31_t)0xbda098f3, + (q31_t)0x6d6f3365, (q31_t)0xbd9b39ad, (q31_t)0x6d6bf0f0, (q31_t)0xbd95da91, (q31_t)0x6d68ae37, (q31_t)0xbd907b9d, (q31_t)0x6d656b3a, (q31_t)0xbd8b1cd2, + (q31_t)0x6d6227fa, (q31_t)0xbd85be30, (q31_t)0x6d5ee477, (q31_t)0xbd805fb7, (q31_t)0x6d5ba0b0, (q31_t)0xbd7b0167, (q31_t)0x6d585ca6, (q31_t)0xbd75a340, + (q31_t)0x6d551858, (q31_t)0xbd704542, (q31_t)0x6d51d3c6, (q31_t)0xbd6ae76d, (q31_t)0x6d4e8ef2, (q31_t)0xbd6589c1, (q31_t)0x6d4b49da, (q31_t)0xbd602c3f, + (q31_t)0x6d48047e, (q31_t)0xbd5acee5, (q31_t)0x6d44bedf, (q31_t)0xbd5571b5, (q31_t)0x6d4178fd, (q31_t)0xbd5014ad, (q31_t)0x6d3e32d7, (q31_t)0xbd4ab7cf, + (q31_t)0x6d3aec6e, (q31_t)0xbd455b1a, (q31_t)0x6d37a5c1, (q31_t)0xbd3ffe8e, (q31_t)0x6d345ed1, (q31_t)0xbd3aa22c, (q31_t)0x6d31179e, (q31_t)0xbd3545f2, + (q31_t)0x6d2dd027, (q31_t)0xbd2fe9e2, (q31_t)0x6d2a886e, (q31_t)0xbd2a8dfb, (q31_t)0x6d274070, (q31_t)0xbd25323d, (q31_t)0x6d23f830, (q31_t)0xbd1fd6a8, + (q31_t)0x6d20afac, (q31_t)0xbd1a7b3d, (q31_t)0x6d1d66e4, (q31_t)0xbd151ffb, (q31_t)0x6d1a1dda, (q31_t)0xbd0fc4e2, (q31_t)0x6d16d48c, (q31_t)0xbd0a69f2, + (q31_t)0x6d138afb, (q31_t)0xbd050f2c, (q31_t)0x6d104126, (q31_t)0xbcffb48f, (q31_t)0x6d0cf70f, (q31_t)0xbcfa5a1b, (q31_t)0x6d09acb4, (q31_t)0xbcf4ffd1, + (q31_t)0x6d066215, (q31_t)0xbcefa5b0, (q31_t)0x6d031734, (q31_t)0xbcea4bb9, (q31_t)0x6cffcc0f, (q31_t)0xbce4f1eb, (q31_t)0x6cfc80a7, (q31_t)0xbcdf9846, + (q31_t)0x6cf934fc, (q31_t)0xbcda3ecb, (q31_t)0x6cf5e90d, (q31_t)0xbcd4e579, (q31_t)0x6cf29cdc, (q31_t)0xbccf8c50, (q31_t)0x6cef5067, (q31_t)0xbcca3351, + (q31_t)0x6cec03af, (q31_t)0xbcc4da7b, (q31_t)0x6ce8b6b4, (q31_t)0xbcbf81cf, (q31_t)0x6ce56975, (q31_t)0xbcba294d, (q31_t)0x6ce21bf4, (q31_t)0xbcb4d0f4, + (q31_t)0x6cdece2f, (q31_t)0xbcaf78c4, (q31_t)0x6cdb8027, (q31_t)0xbcaa20be, (q31_t)0x6cd831dc, (q31_t)0xbca4c8e1, (q31_t)0x6cd4e34e, (q31_t)0xbc9f712e, + (q31_t)0x6cd1947c, (q31_t)0xbc9a19a5, (q31_t)0x6cce4568, (q31_t)0xbc94c245, (q31_t)0x6ccaf610, (q31_t)0xbc8f6b0f, (q31_t)0x6cc7a676, (q31_t)0xbc8a1402, + (q31_t)0x6cc45698, (q31_t)0xbc84bd1f, (q31_t)0x6cc10677, (q31_t)0xbc7f6665, (q31_t)0x6cbdb613, (q31_t)0xbc7a0fd6, (q31_t)0x6cba656c, (q31_t)0xbc74b96f, + (q31_t)0x6cb71482, (q31_t)0xbc6f6333, (q31_t)0x6cb3c355, (q31_t)0xbc6a0d20, (q31_t)0x6cb071e4, (q31_t)0xbc64b737, (q31_t)0x6cad2031, (q31_t)0xbc5f6177, + (q31_t)0x6ca9ce3b, (q31_t)0xbc5a0be2, (q31_t)0x6ca67c01, (q31_t)0xbc54b676, (q31_t)0x6ca32985, (q31_t)0xbc4f6134, (q31_t)0x6c9fd6c6, (q31_t)0xbc4a0c1b, + (q31_t)0x6c9c83c3, (q31_t)0xbc44b72c, (q31_t)0x6c99307e, (q31_t)0xbc3f6267, (q31_t)0x6c95dcf6, (q31_t)0xbc3a0dcc, (q31_t)0x6c92892a, (q31_t)0xbc34b95b, + (q31_t)0x6c8f351c, (q31_t)0xbc2f6513, (q31_t)0x6c8be0cb, (q31_t)0xbc2a10f6, (q31_t)0x6c888c36, (q31_t)0xbc24bd02, (q31_t)0x6c85375f, (q31_t)0xbc1f6938, + (q31_t)0x6c81e245, (q31_t)0xbc1a1598, (q31_t)0x6c7e8ce8, (q31_t)0xbc14c221, (q31_t)0x6c7b3748, (q31_t)0xbc0f6ed5, (q31_t)0x6c77e165, (q31_t)0xbc0a1bb3, + (q31_t)0x6c748b3f, (q31_t)0xbc04c8ba, (q31_t)0x6c7134d7, (q31_t)0xbbff75ec, (q31_t)0x6c6dde2b, (q31_t)0xbbfa2347, (q31_t)0x6c6a873d, (q31_t)0xbbf4d0cc, + (q31_t)0x6c67300b, (q31_t)0xbbef7e7c, (q31_t)0x6c63d897, (q31_t)0xbbea2c55, (q31_t)0x6c6080e0, (q31_t)0xbbe4da58, (q31_t)0x6c5d28e6, (q31_t)0xbbdf8885, + (q31_t)0x6c59d0a9, (q31_t)0xbbda36dd, (q31_t)0x6c56782a, (q31_t)0xbbd4e55e, (q31_t)0x6c531f67, (q31_t)0xbbcf940a, (q31_t)0x6c4fc662, (q31_t)0xbbca42df, + (q31_t)0x6c4c6d1a, (q31_t)0xbbc4f1df, (q31_t)0x6c49138f, (q31_t)0xbbbfa108, (q31_t)0x6c45b9c1, (q31_t)0xbbba505c, (q31_t)0x6c425fb1, (q31_t)0xbbb4ffda, + (q31_t)0x6c3f055d, (q31_t)0xbbafaf82, (q31_t)0x6c3baac7, (q31_t)0xbbaa5f54, (q31_t)0x6c384fef, (q31_t)0xbba50f50, (q31_t)0x6c34f4d3, (q31_t)0xbb9fbf77, + (q31_t)0x6c319975, (q31_t)0xbb9a6fc7, (q31_t)0x6c2e3dd4, (q31_t)0xbb952042, (q31_t)0x6c2ae1f0, (q31_t)0xbb8fd0e7, (q31_t)0x6c2785ca, (q31_t)0xbb8a81b6, + (q31_t)0x6c242960, (q31_t)0xbb8532b0, (q31_t)0x6c20ccb4, (q31_t)0xbb7fe3d3, (q31_t)0x6c1d6fc6, (q31_t)0xbb7a9521, (q31_t)0x6c1a1295, (q31_t)0xbb754699, + (q31_t)0x6c16b521, (q31_t)0xbb6ff83c, (q31_t)0x6c13576a, (q31_t)0xbb6aaa09, (q31_t)0x6c0ff971, (q31_t)0xbb655c00, (q31_t)0x6c0c9b35, (q31_t)0xbb600e21, + (q31_t)0x6c093cb6, (q31_t)0xbb5ac06d, (q31_t)0x6c05ddf5, (q31_t)0xbb5572e3, (q31_t)0x6c027ef1, (q31_t)0xbb502583, (q31_t)0x6bff1faa, (q31_t)0xbb4ad84e, + (q31_t)0x6bfbc021, (q31_t)0xbb458b43, (q31_t)0x6bf86055, (q31_t)0xbb403e63, (q31_t)0x6bf50047, (q31_t)0xbb3af1ad, (q31_t)0x6bf19ff6, (q31_t)0xbb35a521, + (q31_t)0x6bee3f62, (q31_t)0xbb3058c0, (q31_t)0x6beade8c, (q31_t)0xbb2b0c8a, (q31_t)0x6be77d74, (q31_t)0xbb25c07d, (q31_t)0x6be41c18, (q31_t)0xbb20749c, + (q31_t)0x6be0ba7b, (q31_t)0xbb1b28e4, (q31_t)0x6bdd589a, (q31_t)0xbb15dd57, (q31_t)0x6bd9f677, (q31_t)0xbb1091f5, (q31_t)0x6bd69412, (q31_t)0xbb0b46bd, + (q31_t)0x6bd3316a, (q31_t)0xbb05fbb0, (q31_t)0x6bcfce80, (q31_t)0xbb00b0ce, (q31_t)0x6bcc6b53, (q31_t)0xbafb6615, (q31_t)0x6bc907e3, (q31_t)0xbaf61b88, + (q31_t)0x6bc5a431, (q31_t)0xbaf0d125, (q31_t)0x6bc2403d, (q31_t)0xbaeb86ed, (q31_t)0x6bbedc06, (q31_t)0xbae63cdf, (q31_t)0x6bbb778d, (q31_t)0xbae0f2fc, + (q31_t)0x6bb812d1, (q31_t)0xbadba943, (q31_t)0x6bb4add3, (q31_t)0xbad65fb5, (q31_t)0x6bb14892, (q31_t)0xbad11652, (q31_t)0x6bade30f, (q31_t)0xbacbcd1a, + (q31_t)0x6baa7d49, (q31_t)0xbac6840c, (q31_t)0x6ba71741, (q31_t)0xbac13b29, (q31_t)0x6ba3b0f7, (q31_t)0xbabbf270, (q31_t)0x6ba04a6a, (q31_t)0xbab6a9e3, + (q31_t)0x6b9ce39b, (q31_t)0xbab16180, (q31_t)0x6b997c8a, (q31_t)0xbaac1948, (q31_t)0x6b961536, (q31_t)0xbaa6d13a, (q31_t)0x6b92ada0, (q31_t)0xbaa18958, + (q31_t)0x6b8f45c7, (q31_t)0xba9c41a0, (q31_t)0x6b8bddac, (q31_t)0xba96fa13, (q31_t)0x6b88754f, (q31_t)0xba91b2b1, (q31_t)0x6b850caf, (q31_t)0xba8c6b79, + (q31_t)0x6b81a3cd, (q31_t)0xba87246d, (q31_t)0x6b7e3aa9, (q31_t)0xba81dd8b, (q31_t)0x6b7ad142, (q31_t)0xba7c96d4, (q31_t)0x6b776799, (q31_t)0xba775048, + (q31_t)0x6b73fdae, (q31_t)0xba7209e7, (q31_t)0x6b709381, (q31_t)0xba6cc3b1, (q31_t)0x6b6d2911, (q31_t)0xba677da6, (q31_t)0x6b69be5f, (q31_t)0xba6237c5, + (q31_t)0x6b66536b, (q31_t)0xba5cf210, (q31_t)0x6b62e834, (q31_t)0xba57ac86, (q31_t)0x6b5f7cbc, (q31_t)0xba526726, (q31_t)0x6b5c1101, (q31_t)0xba4d21f2, + (q31_t)0x6b58a503, (q31_t)0xba47dce8, (q31_t)0x6b5538c4, (q31_t)0xba42980a, (q31_t)0x6b51cc42, (q31_t)0xba3d5356, (q31_t)0x6b4e5f7f, (q31_t)0xba380ece, + (q31_t)0x6b4af279, (q31_t)0xba32ca71, (q31_t)0x6b478530, (q31_t)0xba2d863e, (q31_t)0x6b4417a6, (q31_t)0xba284237, (q31_t)0x6b40a9d9, (q31_t)0xba22fe5b, + (q31_t)0x6b3d3bcb, (q31_t)0xba1dbaaa, (q31_t)0x6b39cd7a, (q31_t)0xba187724, (q31_t)0x6b365ee7, (q31_t)0xba1333c9, (q31_t)0x6b32f012, (q31_t)0xba0df099, + (q31_t)0x6b2f80fb, (q31_t)0xba08ad95, (q31_t)0x6b2c11a1, (q31_t)0xba036abb, (q31_t)0x6b28a206, (q31_t)0xb9fe280d, (q31_t)0x6b253228, (q31_t)0xb9f8e58a, + (q31_t)0x6b21c208, (q31_t)0xb9f3a332, (q31_t)0x6b1e51a7, (q31_t)0xb9ee6106, (q31_t)0x6b1ae103, (q31_t)0xb9e91f04, (q31_t)0x6b17701d, (q31_t)0xb9e3dd2e, + (q31_t)0x6b13fef5, (q31_t)0xb9de9b83, (q31_t)0x6b108d8b, (q31_t)0xb9d95a03, (q31_t)0x6b0d1bdf, (q31_t)0xb9d418af, (q31_t)0x6b09a9f1, (q31_t)0xb9ced786, + (q31_t)0x6b0637c1, (q31_t)0xb9c99688, (q31_t)0x6b02c54f, (q31_t)0xb9c455b6, (q31_t)0x6aff529a, (q31_t)0xb9bf150e, (q31_t)0x6afbdfa4, (q31_t)0xb9b9d493, + (q31_t)0x6af86c6c, (q31_t)0xb9b49442, (q31_t)0x6af4f8f2, (q31_t)0xb9af541d, (q31_t)0x6af18536, (q31_t)0xb9aa1423, (q31_t)0x6aee1138, (q31_t)0xb9a4d455, + (q31_t)0x6aea9cf8, (q31_t)0xb99f94b2, (q31_t)0x6ae72876, (q31_t)0xb99a553a, (q31_t)0x6ae3b3b2, (q31_t)0xb99515ee, (q31_t)0x6ae03eac, (q31_t)0xb98fd6cd, + (q31_t)0x6adcc964, (q31_t)0xb98a97d8, (q31_t)0x6ad953db, (q31_t)0xb985590e, (q31_t)0x6ad5de0f, (q31_t)0xb9801a70, (q31_t)0x6ad26802, (q31_t)0xb97adbfd, + (q31_t)0x6acef1b2, (q31_t)0xb9759db6, (q31_t)0x6acb7b21, (q31_t)0xb9705f9a, (q31_t)0x6ac8044e, (q31_t)0xb96b21aa, (q31_t)0x6ac48d39, (q31_t)0xb965e3e5, + (q31_t)0x6ac115e2, (q31_t)0xb960a64c, (q31_t)0x6abd9e49, (q31_t)0xb95b68de, (q31_t)0x6aba266e, (q31_t)0xb9562b9c, (q31_t)0x6ab6ae52, (q31_t)0xb950ee86, + (q31_t)0x6ab335f4, (q31_t)0xb94bb19b, (q31_t)0x6aafbd54, (q31_t)0xb94674dc, (q31_t)0x6aac4472, (q31_t)0xb9413848, (q31_t)0x6aa8cb4e, (q31_t)0xb93bfbe0, + (q31_t)0x6aa551e9, (q31_t)0xb936bfa4, (q31_t)0x6aa1d841, (q31_t)0xb9318393, (q31_t)0x6a9e5e58, (q31_t)0xb92c47ae, (q31_t)0x6a9ae42e, (q31_t)0xb9270bf5, + (q31_t)0x6a9769c1, (q31_t)0xb921d067, (q31_t)0x6a93ef13, (q31_t)0xb91c9505, (q31_t)0x6a907423, (q31_t)0xb91759cf, (q31_t)0x6a8cf8f1, (q31_t)0xb9121ec5, + (q31_t)0x6a897d7d, (q31_t)0xb90ce3e6, (q31_t)0x6a8601c8, (q31_t)0xb907a933, (q31_t)0x6a8285d1, (q31_t)0xb9026eac, (q31_t)0x6a7f0999, (q31_t)0xb8fd3451, + (q31_t)0x6a7b8d1e, (q31_t)0xb8f7fa21, (q31_t)0x6a781062, (q31_t)0xb8f2c01d, (q31_t)0x6a749365, (q31_t)0xb8ed8646, (q31_t)0x6a711625, (q31_t)0xb8e84c99, + (q31_t)0x6a6d98a4, (q31_t)0xb8e31319, (q31_t)0x6a6a1ae2, (q31_t)0xb8ddd9c5, (q31_t)0x6a669cdd, (q31_t)0xb8d8a09d, (q31_t)0x6a631e97, (q31_t)0xb8d367a0, + (q31_t)0x6a5fa010, (q31_t)0xb8ce2ecf, (q31_t)0x6a5c2147, (q31_t)0xb8c8f62b, (q31_t)0x6a58a23c, (q31_t)0xb8c3bdb2, (q31_t)0x6a5522ef, (q31_t)0xb8be8565, + (q31_t)0x6a51a361, (q31_t)0xb8b94d44, (q31_t)0x6a4e2392, (q31_t)0xb8b4154f, (q31_t)0x6a4aa381, (q31_t)0xb8aedd86, (q31_t)0x6a47232e, (q31_t)0xb8a9a5e9, + (q31_t)0x6a43a29a, (q31_t)0xb8a46e78, (q31_t)0x6a4021c4, (q31_t)0xb89f3733, (q31_t)0x6a3ca0ad, (q31_t)0xb89a001a, (q31_t)0x6a391f54, (q31_t)0xb894c92d, + (q31_t)0x6a359db9, (q31_t)0xb88f926d, (q31_t)0x6a321bdd, (q31_t)0xb88a5bd8, (q31_t)0x6a2e99c0, (q31_t)0xb885256f, (q31_t)0x6a2b1761, (q31_t)0xb87fef33, + (q31_t)0x6a2794c1, (q31_t)0xb87ab922, (q31_t)0x6a2411df, (q31_t)0xb875833e, (q31_t)0x6a208ebb, (q31_t)0xb8704d85, (q31_t)0x6a1d0b57, (q31_t)0xb86b17f9, + (q31_t)0x6a1987b0, (q31_t)0xb865e299, (q31_t)0x6a1603c8, (q31_t)0xb860ad66, (q31_t)0x6a127f9f, (q31_t)0xb85b785e, (q31_t)0x6a0efb35, (q31_t)0xb8564383, + (q31_t)0x6a0b7689, (q31_t)0xb8510ed4, (q31_t)0x6a07f19b, (q31_t)0xb84bda51, (q31_t)0x6a046c6c, (q31_t)0xb846a5fa, (q31_t)0x6a00e6fc, (q31_t)0xb84171cf, + (q31_t)0x69fd614a, (q31_t)0xb83c3dd1, (q31_t)0x69f9db57, (q31_t)0xb83709ff, (q31_t)0x69f65523, (q31_t)0xb831d659, (q31_t)0x69f2cead, (q31_t)0xb82ca2e0, + (q31_t)0x69ef47f6, (q31_t)0xb8276f93, (q31_t)0x69ebc0fe, (q31_t)0xb8223c72, (q31_t)0x69e839c4, (q31_t)0xb81d097e, (q31_t)0x69e4b249, (q31_t)0xb817d6b6, + (q31_t)0x69e12a8c, (q31_t)0xb812a41a, (q31_t)0x69dda28f, (q31_t)0xb80d71aa, (q31_t)0x69da1a50, (q31_t)0xb8083f67, (q31_t)0x69d691cf, (q31_t)0xb8030d51, + (q31_t)0x69d3090e, (q31_t)0xb7fddb67, (q31_t)0x69cf800b, (q31_t)0xb7f8a9a9, (q31_t)0x69cbf6c7, (q31_t)0xb7f37818, (q31_t)0x69c86d41, (q31_t)0xb7ee46b3, + (q31_t)0x69c4e37a, (q31_t)0xb7e9157a, (q31_t)0x69c15973, (q31_t)0xb7e3e46e, (q31_t)0x69bdcf29, (q31_t)0xb7deb38f, (q31_t)0x69ba449f, (q31_t)0xb7d982dc, + (q31_t)0x69b6b9d3, (q31_t)0xb7d45255, (q31_t)0x69b32ec7, (q31_t)0xb7cf21fb, (q31_t)0x69afa378, (q31_t)0xb7c9f1ce, (q31_t)0x69ac17e9, (q31_t)0xb7c4c1cd, + (q31_t)0x69a88c19, (q31_t)0xb7bf91f8, (q31_t)0x69a50007, (q31_t)0xb7ba6251, (q31_t)0x69a173b5, (q31_t)0xb7b532d6, (q31_t)0x699de721, (q31_t)0xb7b00387, + (q31_t)0x699a5a4c, (q31_t)0xb7aad465, (q31_t)0x6996cd35, (q31_t)0xb7a5a570, (q31_t)0x69933fde, (q31_t)0xb7a076a7, (q31_t)0x698fb246, (q31_t)0xb79b480b, + (q31_t)0x698c246c, (q31_t)0xb796199b, (q31_t)0x69889651, (q31_t)0xb790eb58, (q31_t)0x698507f6, (q31_t)0xb78bbd42, (q31_t)0x69817959, (q31_t)0xb7868f59, + (q31_t)0x697dea7b, (q31_t)0xb781619c, (q31_t)0x697a5b5c, (q31_t)0xb77c340c, (q31_t)0x6976cbfc, (q31_t)0xb77706a9, (q31_t)0x69733c5b, (q31_t)0xb771d972, + (q31_t)0x696fac78, (q31_t)0xb76cac69, (q31_t)0x696c1c55, (q31_t)0xb7677f8c, (q31_t)0x69688bf1, (q31_t)0xb76252db, (q31_t)0x6964fb4c, (q31_t)0xb75d2658, + (q31_t)0x69616a65, (q31_t)0xb757fa01, (q31_t)0x695dd93e, (q31_t)0xb752cdd8, (q31_t)0x695a47d6, (q31_t)0xb74da1db, (q31_t)0x6956b62d, (q31_t)0xb748760b, + (q31_t)0x69532442, (q31_t)0xb7434a67, (q31_t)0x694f9217, (q31_t)0xb73e1ef1, (q31_t)0x694bffab, (q31_t)0xb738f3a7, (q31_t)0x69486cfe, (q31_t)0xb733c88b, + (q31_t)0x6944da10, (q31_t)0xb72e9d9b, (q31_t)0x694146e1, (q31_t)0xb72972d8, (q31_t)0x693db371, (q31_t)0xb7244842, (q31_t)0x693a1fc0, (q31_t)0xb71f1dd9, + (q31_t)0x69368bce, (q31_t)0xb719f39e, (q31_t)0x6932f79b, (q31_t)0xb714c98e, (q31_t)0x692f6328, (q31_t)0xb70f9fac, (q31_t)0x692bce73, (q31_t)0xb70a75f7, + (q31_t)0x6928397e, (q31_t)0xb7054c6f, (q31_t)0x6924a448, (q31_t)0xb7002314, (q31_t)0x69210ed1, (q31_t)0xb6faf9e6, (q31_t)0x691d7919, (q31_t)0xb6f5d0e5, + (q31_t)0x6919e320, (q31_t)0xb6f0a812, (q31_t)0x69164ce7, (q31_t)0xb6eb7f6b, (q31_t)0x6912b66c, (q31_t)0xb6e656f1, (q31_t)0x690f1fb1, (q31_t)0xb6e12ea4, + (q31_t)0x690b88b5, (q31_t)0xb6dc0685, (q31_t)0x6907f178, (q31_t)0xb6d6de92, (q31_t)0x690459fb, (q31_t)0xb6d1b6cd, (q31_t)0x6900c23c, (q31_t)0xb6cc8f35, + (q31_t)0x68fd2a3d, (q31_t)0xb6c767ca, (q31_t)0x68f991fd, (q31_t)0xb6c2408c, (q31_t)0x68f5f97d, (q31_t)0xb6bd197c, (q31_t)0x68f260bb, (q31_t)0xb6b7f298, + (q31_t)0x68eec7b9, (q31_t)0xb6b2cbe2, (q31_t)0x68eb2e76, (q31_t)0xb6ada559, (q31_t)0x68e794f3, (q31_t)0xb6a87efd, (q31_t)0x68e3fb2e, (q31_t)0xb6a358ce, + (q31_t)0x68e06129, (q31_t)0xb69e32cd, (q31_t)0x68dcc6e4, (q31_t)0xb6990cf9, (q31_t)0x68d92c5d, (q31_t)0xb693e752, (q31_t)0x68d59196, (q31_t)0xb68ec1d9, + (q31_t)0x68d1f68f, (q31_t)0xb6899c8d, (q31_t)0x68ce5b46, (q31_t)0xb684776e, (q31_t)0x68cabfbd, (q31_t)0xb67f527c, (q31_t)0x68c723f3, (q31_t)0xb67a2db8, + (q31_t)0x68c387e9, (q31_t)0xb6750921, (q31_t)0x68bfeb9e, (q31_t)0xb66fe4b8, (q31_t)0x68bc4f13, (q31_t)0xb66ac07c, (q31_t)0x68b8b247, (q31_t)0xb6659c6d, + (q31_t)0x68b5153a, (q31_t)0xb660788c, (q31_t)0x68b177ed, (q31_t)0xb65b54d8, (q31_t)0x68adda5f, (q31_t)0xb6563151, (q31_t)0x68aa3c90, (q31_t)0xb6510df8, + (q31_t)0x68a69e81, (q31_t)0xb64beacd, (q31_t)0x68a30031, (q31_t)0xb646c7ce, (q31_t)0x689f61a1, (q31_t)0xb641a4fe, (q31_t)0x689bc2d1, (q31_t)0xb63c825b, + (q31_t)0x689823bf, (q31_t)0xb6375fe5, (q31_t)0x6894846e, (q31_t)0xb6323d9d, (q31_t)0x6890e4dc, (q31_t)0xb62d1b82, (q31_t)0x688d4509, (q31_t)0xb627f995, + (q31_t)0x6889a4f6, (q31_t)0xb622d7d6, (q31_t)0x688604a2, (q31_t)0xb61db644, (q31_t)0x6882640e, (q31_t)0xb61894df, (q31_t)0x687ec339, (q31_t)0xb61373a9, + (q31_t)0x687b2224, (q31_t)0xb60e529f, (q31_t)0x687780ce, (q31_t)0xb60931c4, (q31_t)0x6873df38, (q31_t)0xb6041116, (q31_t)0x68703d62, (q31_t)0xb5fef095, + (q31_t)0x686c9b4b, (q31_t)0xb5f9d043, (q31_t)0x6868f8f4, (q31_t)0xb5f4b01e, (q31_t)0x6865565c, (q31_t)0xb5ef9026, (q31_t)0x6861b384, (q31_t)0xb5ea705d, + (q31_t)0x685e106c, (q31_t)0xb5e550c1, (q31_t)0x685a6d13, (q31_t)0xb5e03153, (q31_t)0x6856c979, (q31_t)0xb5db1212, (q31_t)0x685325a0, (q31_t)0xb5d5f2ff, + (q31_t)0x684f8186, (q31_t)0xb5d0d41a, (q31_t)0x684bdd2c, (q31_t)0xb5cbb563, (q31_t)0x68483891, (q31_t)0xb5c696da, (q31_t)0x684493b6, (q31_t)0xb5c1787e, + (q31_t)0x6840ee9b, (q31_t)0xb5bc5a50, (q31_t)0x683d493f, (q31_t)0xb5b73c50, (q31_t)0x6839a3a4, (q31_t)0xb5b21e7e, (q31_t)0x6835fdc7, (q31_t)0xb5ad00d9, + (q31_t)0x683257ab, (q31_t)0xb5a7e362, (q31_t)0x682eb14e, (q31_t)0xb5a2c61a, (q31_t)0x682b0ab1, (q31_t)0xb59da8ff, (q31_t)0x682763d4, (q31_t)0xb5988c12, + (q31_t)0x6823bcb7, (q31_t)0xb5936f53, (q31_t)0x68201559, (q31_t)0xb58e52c2, (q31_t)0x681c6dbb, (q31_t)0xb589365e, (q31_t)0x6818c5dd, (q31_t)0xb5841a29, + (q31_t)0x68151dbe, (q31_t)0xb57efe22, (q31_t)0x68117560, (q31_t)0xb579e248, (q31_t)0x680dccc1, (q31_t)0xb574c69d, (q31_t)0x680a23e2, (q31_t)0xb56fab1f, + (q31_t)0x68067ac3, (q31_t)0xb56a8fd0, (q31_t)0x6802d164, (q31_t)0xb56574ae, (q31_t)0x67ff27c4, (q31_t)0xb56059bb, (q31_t)0x67fb7de5, (q31_t)0xb55b3ef5, + (q31_t)0x67f7d3c5, (q31_t)0xb556245e, (q31_t)0x67f42965, (q31_t)0xb55109f5, (q31_t)0x67f07ec5, (q31_t)0xb54befba, (q31_t)0x67ecd3e5, (q31_t)0xb546d5ac, + (q31_t)0x67e928c5, (q31_t)0xb541bbcd, (q31_t)0x67e57d64, (q31_t)0xb53ca21c, (q31_t)0x67e1d1c4, (q31_t)0xb5378899, (q31_t)0x67de25e3, (q31_t)0xb5326f45, + (q31_t)0x67da79c3, (q31_t)0xb52d561e, (q31_t)0x67d6cd62, (q31_t)0xb5283d26, (q31_t)0x67d320c1, (q31_t)0xb523245b, (q31_t)0x67cf73e1, (q31_t)0xb51e0bbf, + (q31_t)0x67cbc6c0, (q31_t)0xb518f351, (q31_t)0x67c8195f, (q31_t)0xb513db12, (q31_t)0x67c46bbe, (q31_t)0xb50ec300, (q31_t)0x67c0bddd, (q31_t)0xb509ab1d, + (q31_t)0x67bd0fbd, (q31_t)0xb5049368, (q31_t)0x67b9615c, (q31_t)0xb4ff7be1, (q31_t)0x67b5b2bb, (q31_t)0xb4fa6489, (q31_t)0x67b203da, (q31_t)0xb4f54d5f, + (q31_t)0x67ae54ba, (q31_t)0xb4f03663, (q31_t)0x67aaa559, (q31_t)0xb4eb1f95, (q31_t)0x67a6f5b8, (q31_t)0xb4e608f6, (q31_t)0x67a345d8, (q31_t)0xb4e0f285, + (q31_t)0x679f95b7, (q31_t)0xb4dbdc42, (q31_t)0x679be557, (q31_t)0xb4d6c62e, (q31_t)0x679834b6, (q31_t)0xb4d1b048, (q31_t)0x679483d6, (q31_t)0xb4cc9a90, + (q31_t)0x6790d2b6, (q31_t)0xb4c78507, (q31_t)0x678d2156, (q31_t)0xb4c26fad, (q31_t)0x67896fb6, (q31_t)0xb4bd5a80, (q31_t)0x6785bdd6, (q31_t)0xb4b84582, + (q31_t)0x67820bb7, (q31_t)0xb4b330b3, (q31_t)0x677e5957, (q31_t)0xb4ae1c12, (q31_t)0x677aa6b8, (q31_t)0xb4a9079f, (q31_t)0x6776f3d9, (q31_t)0xb4a3f35b, + (q31_t)0x677340ba, (q31_t)0xb49edf45, (q31_t)0x676f8d5b, (q31_t)0xb499cb5e, (q31_t)0x676bd9bd, (q31_t)0xb494b7a6, (q31_t)0x676825de, (q31_t)0xb48fa41c, + (q31_t)0x676471c0, (q31_t)0xb48a90c0, (q31_t)0x6760bd62, (q31_t)0xb4857d93, (q31_t)0x675d08c4, (q31_t)0xb4806a95, (q31_t)0x675953e7, (q31_t)0xb47b57c5, + (q31_t)0x67559eca, (q31_t)0xb4764523, (q31_t)0x6751e96d, (q31_t)0xb47132b1, (q31_t)0x674e33d0, (q31_t)0xb46c206d, (q31_t)0x674a7df4, (q31_t)0xb4670e57, + (q31_t)0x6746c7d8, (q31_t)0xb461fc70, (q31_t)0x6743117c, (q31_t)0xb45ceab8, (q31_t)0x673f5ae0, (q31_t)0xb457d92f, (q31_t)0x673ba405, (q31_t)0xb452c7d4, + (q31_t)0x6737ecea, (q31_t)0xb44db6a8, (q31_t)0x67343590, (q31_t)0xb448a5aa, (q31_t)0x67307df5, (q31_t)0xb44394db, (q31_t)0x672cc61c, (q31_t)0xb43e843b, + (q31_t)0x67290e02, (q31_t)0xb43973ca, (q31_t)0x672555a9, (q31_t)0xb4346387, (q31_t)0x67219d10, (q31_t)0xb42f5373, (q31_t)0x671de438, (q31_t)0xb42a438e, + (q31_t)0x671a2b20, (q31_t)0xb42533d8, (q31_t)0x671671c8, (q31_t)0xb4202451, (q31_t)0x6712b831, (q31_t)0xb41b14f8, (q31_t)0x670efe5a, (q31_t)0xb41605ce, + (q31_t)0x670b4444, (q31_t)0xb410f6d3, (q31_t)0x670789ee, (q31_t)0xb40be807, (q31_t)0x6703cf58, (q31_t)0xb406d969, (q31_t)0x67001483, (q31_t)0xb401cafb, + (q31_t)0x66fc596f, (q31_t)0xb3fcbcbb, (q31_t)0x66f89e1b, (q31_t)0xb3f7aeaa, (q31_t)0x66f4e287, (q31_t)0xb3f2a0c9, (q31_t)0x66f126b4, (q31_t)0xb3ed9316, + (q31_t)0x66ed6aa1, (q31_t)0xb3e88592, (q31_t)0x66e9ae4f, (q31_t)0xb3e3783d, (q31_t)0x66e5f1be, (q31_t)0xb3de6b17, (q31_t)0x66e234ed, (q31_t)0xb3d95e1f, + (q31_t)0x66de77dc, (q31_t)0xb3d45157, (q31_t)0x66daba8c, (q31_t)0xb3cf44be, (q31_t)0x66d6fcfd, (q31_t)0xb3ca3854, (q31_t)0x66d33f2e, (q31_t)0xb3c52c19, + (q31_t)0x66cf8120, (q31_t)0xb3c0200c, (q31_t)0x66cbc2d2, (q31_t)0xb3bb142f, (q31_t)0x66c80445, (q31_t)0xb3b60881, (q31_t)0x66c44579, (q31_t)0xb3b0fd02, + (q31_t)0x66c0866d, (q31_t)0xb3abf1b2, (q31_t)0x66bcc721, (q31_t)0xb3a6e691, (q31_t)0x66b90797, (q31_t)0xb3a1dba0, (q31_t)0x66b547cd, (q31_t)0xb39cd0dd, + (q31_t)0x66b187c3, (q31_t)0xb397c649, (q31_t)0x66adc77b, (q31_t)0xb392bbe5, (q31_t)0x66aa06f3, (q31_t)0xb38db1b0, (q31_t)0x66a6462b, (q31_t)0xb388a7aa, + (q31_t)0x66a28524, (q31_t)0xb3839dd3, (q31_t)0x669ec3de, (q31_t)0xb37e942b, (q31_t)0x669b0259, (q31_t)0xb3798ab2, (q31_t)0x66974095, (q31_t)0xb3748169, + (q31_t)0x66937e91, (q31_t)0xb36f784f, (q31_t)0x668fbc4e, (q31_t)0xb36a6f64, (q31_t)0x668bf9cb, (q31_t)0xb36566a8, (q31_t)0x66883709, (q31_t)0xb3605e1c, + (q31_t)0x66847408, (q31_t)0xb35b55bf, (q31_t)0x6680b0c8, (q31_t)0xb3564d91, (q31_t)0x667ced49, (q31_t)0xb3514592, (q31_t)0x6679298a, (q31_t)0xb34c3dc3, + (q31_t)0x6675658c, (q31_t)0xb3473623, (q31_t)0x6671a14f, (q31_t)0xb3422eb2, (q31_t)0x666ddcd3, (q31_t)0xb33d2771, (q31_t)0x666a1818, (q31_t)0xb338205f, + (q31_t)0x6666531d, (q31_t)0xb333197c, (q31_t)0x66628de4, (q31_t)0xb32e12c9, (q31_t)0x665ec86b, (q31_t)0xb3290c45, (q31_t)0x665b02b3, (q31_t)0xb32405f1, + (q31_t)0x66573cbb, (q31_t)0xb31effcc, (q31_t)0x66537685, (q31_t)0xb319f9d6, (q31_t)0x664fb010, (q31_t)0xb314f410, (q31_t)0x664be95b, (q31_t)0xb30fee79, + (q31_t)0x66482267, (q31_t)0xb30ae912, (q31_t)0x66445b35, (q31_t)0xb305e3da, (q31_t)0x664093c3, (q31_t)0xb300ded2, (q31_t)0x663ccc12, (q31_t)0xb2fbd9f9, + (q31_t)0x66390422, (q31_t)0xb2f6d550, (q31_t)0x66353bf3, (q31_t)0xb2f1d0d6, (q31_t)0x66317385, (q31_t)0xb2eccc8c, (q31_t)0x662daad8, (q31_t)0xb2e7c871, + (q31_t)0x6629e1ec, (q31_t)0xb2e2c486, (q31_t)0x662618c1, (q31_t)0xb2ddc0ca, (q31_t)0x66224f56, (q31_t)0xb2d8bd3e, (q31_t)0x661e85ad, (q31_t)0xb2d3b9e2, + (q31_t)0x661abbc5, (q31_t)0xb2ceb6b5, (q31_t)0x6616f19e, (q31_t)0xb2c9b3b8, (q31_t)0x66132738, (q31_t)0xb2c4b0ea, (q31_t)0x660f5c93, (q31_t)0xb2bfae4c, + (q31_t)0x660b91af, (q31_t)0xb2baabde, (q31_t)0x6607c68c, (q31_t)0xb2b5a99f, (q31_t)0x6603fb2a, (q31_t)0xb2b0a790, (q31_t)0x66002f89, (q31_t)0xb2aba5b1, + (q31_t)0x65fc63a9, (q31_t)0xb2a6a402, (q31_t)0x65f8978b, (q31_t)0xb2a1a282, (q31_t)0x65f4cb2d, (q31_t)0xb29ca132, (q31_t)0x65f0fe91, (q31_t)0xb297a011, + (q31_t)0x65ed31b5, (q31_t)0xb2929f21, (q31_t)0x65e9649b, (q31_t)0xb28d9e60, (q31_t)0x65e59742, (q31_t)0xb2889dcf, (q31_t)0x65e1c9aa, (q31_t)0xb2839d6d, + (q31_t)0x65ddfbd3, (q31_t)0xb27e9d3c, (q31_t)0x65da2dbd, (q31_t)0xb2799d3a, (q31_t)0x65d65f69, (q31_t)0xb2749d68, (q31_t)0x65d290d6, (q31_t)0xb26f9dc6, + (q31_t)0x65cec204, (q31_t)0xb26a9e54, (q31_t)0x65caf2f3, (q31_t)0xb2659f12, (q31_t)0x65c723a3, (q31_t)0xb2609fff, (q31_t)0x65c35415, (q31_t)0xb25ba11d, + (q31_t)0x65bf8447, (q31_t)0xb256a26a, (q31_t)0x65bbb43b, (q31_t)0xb251a3e7, (q31_t)0x65b7e3f1, (q31_t)0xb24ca594, (q31_t)0x65b41367, (q31_t)0xb247a771, + (q31_t)0x65b0429f, (q31_t)0xb242a97e, (q31_t)0x65ac7198, (q31_t)0xb23dabbb, (q31_t)0x65a8a052, (q31_t)0xb238ae28, (q31_t)0x65a4cece, (q31_t)0xb233b0c5, + (q31_t)0x65a0fd0b, (q31_t)0xb22eb392, (q31_t)0x659d2b09, (q31_t)0xb229b68f, (q31_t)0x659958c9, (q31_t)0xb224b9bc, (q31_t)0x6595864a, (q31_t)0xb21fbd19, + (q31_t)0x6591b38c, (q31_t)0xb21ac0a6, (q31_t)0x658de08f, (q31_t)0xb215c463, (q31_t)0x658a0d54, (q31_t)0xb210c850, (q31_t)0x658639db, (q31_t)0xb20bcc6d, + (q31_t)0x65826622, (q31_t)0xb206d0ba, (q31_t)0x657e922b, (q31_t)0xb201d537, (q31_t)0x657abdf6, (q31_t)0xb1fcd9e5, (q31_t)0x6576e982, (q31_t)0xb1f7dec2, + (q31_t)0x657314cf, (q31_t)0xb1f2e3d0, (q31_t)0x656f3fde, (q31_t)0xb1ede90e, (q31_t)0x656b6aae, (q31_t)0xb1e8ee7c, (q31_t)0x6567953f, (q31_t)0xb1e3f41a, + (q31_t)0x6563bf92, (q31_t)0xb1def9e9, (q31_t)0x655fe9a7, (q31_t)0xb1d9ffe7, (q31_t)0x655c137d, (q31_t)0xb1d50616, (q31_t)0x65583d14, (q31_t)0xb1d00c75, + (q31_t)0x6554666d, (q31_t)0xb1cb1304, (q31_t)0x65508f87, (q31_t)0xb1c619c3, (q31_t)0x654cb863, (q31_t)0xb1c120b3, (q31_t)0x6548e101, (q31_t)0xb1bc27d3, + (q31_t)0x6545095f, (q31_t)0xb1b72f23, (q31_t)0x65413180, (q31_t)0xb1b236a4, (q31_t)0x653d5962, (q31_t)0xb1ad3e55, (q31_t)0x65398105, (q31_t)0xb1a84636, + (q31_t)0x6535a86b, (q31_t)0xb1a34e47, (q31_t)0x6531cf91, (q31_t)0xb19e5689, (q31_t)0x652df679, (q31_t)0xb1995efb, (q31_t)0x652a1d23, (q31_t)0xb194679e, + (q31_t)0x6526438f, (q31_t)0xb18f7071, (q31_t)0x652269bc, (q31_t)0xb18a7974, (q31_t)0x651e8faa, (q31_t)0xb18582a8, (q31_t)0x651ab55b, (q31_t)0xb1808c0c, + (q31_t)0x6516dacd, (q31_t)0xb17b95a0, (q31_t)0x65130000, (q31_t)0xb1769f65, (q31_t)0x650f24f5, (q31_t)0xb171a95b, (q31_t)0x650b49ac, (q31_t)0xb16cb380, + (q31_t)0x65076e25, (q31_t)0xb167bdd7, (q31_t)0x6503925f, (q31_t)0xb162c85d, (q31_t)0x64ffb65b, (q31_t)0xb15dd315, (q31_t)0x64fbda18, (q31_t)0xb158ddfd, + (q31_t)0x64f7fd98, (q31_t)0xb153e915, (q31_t)0x64f420d9, (q31_t)0xb14ef45e, (q31_t)0x64f043dc, (q31_t)0xb149ffd7, (q31_t)0x64ec66a0, (q31_t)0xb1450b81, + (q31_t)0x64e88926, (q31_t)0xb140175b, (q31_t)0x64e4ab6e, (q31_t)0xb13b2367, (q31_t)0x64e0cd78, (q31_t)0xb1362fa2, (q31_t)0x64dcef44, (q31_t)0xb1313c0e, + (q31_t)0x64d910d1, (q31_t)0xb12c48ab, (q31_t)0x64d53220, (q31_t)0xb1275579, (q31_t)0x64d15331, (q31_t)0xb1226277, (q31_t)0x64cd7404, (q31_t)0xb11d6fa6, + (q31_t)0x64c99498, (q31_t)0xb1187d05, (q31_t)0x64c5b4ef, (q31_t)0xb1138a95, (q31_t)0x64c1d507, (q31_t)0xb10e9856, (q31_t)0x64bdf4e1, (q31_t)0xb109a648, + (q31_t)0x64ba147d, (q31_t)0xb104b46a, (q31_t)0x64b633da, (q31_t)0xb0ffc2bd, (q31_t)0x64b252fa, (q31_t)0xb0fad140, (q31_t)0x64ae71dc, (q31_t)0xb0f5dff5, + (q31_t)0x64aa907f, (q31_t)0xb0f0eeda, (q31_t)0x64a6aee4, (q31_t)0xb0ebfdf0, (q31_t)0x64a2cd0c, (q31_t)0xb0e70d37, (q31_t)0x649eeaf5, (q31_t)0xb0e21cae, + (q31_t)0x649b08a0, (q31_t)0xb0dd2c56, (q31_t)0x6497260d, (q31_t)0xb0d83c2f, (q31_t)0x6493433c, (q31_t)0xb0d34c39, (q31_t)0x648f602d, (q31_t)0xb0ce5c74, + (q31_t)0x648b7ce0, (q31_t)0xb0c96ce0, (q31_t)0x64879955, (q31_t)0xb0c47d7c, (q31_t)0x6483b58c, (q31_t)0xb0bf8e4a, (q31_t)0x647fd185, (q31_t)0xb0ba9f48, + (q31_t)0x647bed3f, (q31_t)0xb0b5b077, (q31_t)0x647808bc, (q31_t)0xb0b0c1d7, (q31_t)0x647423fb, (q31_t)0xb0abd368, (q31_t)0x64703efc, (q31_t)0xb0a6e52a, + (q31_t)0x646c59bf, (q31_t)0xb0a1f71d, (q31_t)0x64687444, (q31_t)0xb09d0941, (q31_t)0x64648e8c, (q31_t)0xb0981b96, (q31_t)0x6460a895, (q31_t)0xb0932e1b, + (q31_t)0x645cc260, (q31_t)0xb08e40d2, (q31_t)0x6458dbed, (q31_t)0xb08953ba, (q31_t)0x6454f53d, (q31_t)0xb08466d3, (q31_t)0x64510e4e, (q31_t)0xb07f7a1c, + (q31_t)0x644d2722, (q31_t)0xb07a8d97, (q31_t)0x64493fb8, (q31_t)0xb075a143, (q31_t)0x64455810, (q31_t)0xb070b520, (q31_t)0x6441702a, (q31_t)0xb06bc92e, + (q31_t)0x643d8806, (q31_t)0xb066dd6d, (q31_t)0x64399fa5, (q31_t)0xb061f1de, (q31_t)0x6435b706, (q31_t)0xb05d067f, (q31_t)0x6431ce28, (q31_t)0xb0581b51, + (q31_t)0x642de50d, (q31_t)0xb0533055, (q31_t)0x6429fbb5, (q31_t)0xb04e458a, (q31_t)0x6426121e, (q31_t)0xb0495af0, (q31_t)0x6422284a, (q31_t)0xb0447087, + (q31_t)0x641e3e38, (q31_t)0xb03f864f, (q31_t)0x641a53e8, (q31_t)0xb03a9c49, (q31_t)0x6416695a, (q31_t)0xb035b273, (q31_t)0x64127e8f, (q31_t)0xb030c8cf, + (q31_t)0x640e9386, (q31_t)0xb02bdf5c, (q31_t)0x640aa83f, (q31_t)0xb026f61b, (q31_t)0x6406bcba, (q31_t)0xb0220d0a, (q31_t)0x6402d0f8, (q31_t)0xb01d242b, + (q31_t)0x63fee4f8, (q31_t)0xb0183b7d, (q31_t)0x63faf8bb, (q31_t)0xb0135301, (q31_t)0x63f70c3f, (q31_t)0xb00e6ab5, (q31_t)0x63f31f86, (q31_t)0xb009829c, + (q31_t)0x63ef3290, (q31_t)0xb0049ab3, (q31_t)0x63eb455c, (q31_t)0xafffb2fc, (q31_t)0x63e757ea, (q31_t)0xaffacb76, (q31_t)0x63e36a3a, (q31_t)0xaff5e421, + (q31_t)0x63df7c4d, (q31_t)0xaff0fcfe, (q31_t)0x63db8e22, (q31_t)0xafec160c, (q31_t)0x63d79fba, (q31_t)0xafe72f4c, (q31_t)0x63d3b114, (q31_t)0xafe248bd, + (q31_t)0x63cfc231, (q31_t)0xafdd625f, (q31_t)0x63cbd310, (q31_t)0xafd87c33, (q31_t)0x63c7e3b1, (q31_t)0xafd39638, (q31_t)0x63c3f415, (q31_t)0xafceb06f, + (q31_t)0x63c0043b, (q31_t)0xafc9cad7, (q31_t)0x63bc1424, (q31_t)0xafc4e571, (q31_t)0x63b823cf, (q31_t)0xafc0003c, (q31_t)0x63b4333d, (q31_t)0xafbb1b39, + (q31_t)0x63b0426d, (q31_t)0xafb63667, (q31_t)0x63ac5160, (q31_t)0xafb151c7, (q31_t)0x63a86015, (q31_t)0xafac6d58, (q31_t)0x63a46e8d, (q31_t)0xafa7891b, + (q31_t)0x63a07cc7, (q31_t)0xafa2a50f, (q31_t)0x639c8ac4, (q31_t)0xaf9dc135, (q31_t)0x63989884, (q31_t)0xaf98dd8d, (q31_t)0x6394a606, (q31_t)0xaf93fa16, + (q31_t)0x6390b34a, (q31_t)0xaf8f16d1, (q31_t)0x638cc051, (q31_t)0xaf8a33bd, (q31_t)0x6388cd1b, (q31_t)0xaf8550db, (q31_t)0x6384d9a7, (q31_t)0xaf806e2b, + (q31_t)0x6380e5f6, (q31_t)0xaf7b8bac, (q31_t)0x637cf208, (q31_t)0xaf76a95f, (q31_t)0x6378fddc, (q31_t)0xaf71c743, (q31_t)0x63750973, (q31_t)0xaf6ce55a, + (q31_t)0x637114cc, (q31_t)0xaf6803a2, (q31_t)0x636d1fe9, (q31_t)0xaf63221c, (q31_t)0x63692ac7, (q31_t)0xaf5e40c7, (q31_t)0x63653569, (q31_t)0xaf595fa4, + (q31_t)0x63613fcd, (q31_t)0xaf547eb3, (q31_t)0x635d49f4, (q31_t)0xaf4f9df4, (q31_t)0x635953dd, (q31_t)0xaf4abd66, (q31_t)0x63555d8a, (q31_t)0xaf45dd0b, + (q31_t)0x635166f9, (q31_t)0xaf40fce1, (q31_t)0x634d702b, (q31_t)0xaf3c1ce9, (q31_t)0x6349791f, (q31_t)0xaf373d22, (q31_t)0x634581d6, (q31_t)0xaf325d8e, + (q31_t)0x63418a50, (q31_t)0xaf2d7e2b, (q31_t)0x633d928d, (q31_t)0xaf289efa, (q31_t)0x63399a8d, (q31_t)0xaf23bffb, (q31_t)0x6335a24f, (q31_t)0xaf1ee12e, + (q31_t)0x6331a9d4, (q31_t)0xaf1a0293, (q31_t)0x632db11c, (q31_t)0xaf15242a, (q31_t)0x6329b827, (q31_t)0xaf1045f3, (q31_t)0x6325bef5, (q31_t)0xaf0b67ed, + (q31_t)0x6321c585, (q31_t)0xaf068a1a, (q31_t)0x631dcbd9, (q31_t)0xaf01ac78, (q31_t)0x6319d1ef, (q31_t)0xaefccf09, (q31_t)0x6315d7c8, (q31_t)0xaef7f1cb, + (q31_t)0x6311dd64, (q31_t)0xaef314c0, (q31_t)0x630de2c3, (q31_t)0xaeee37e6, (q31_t)0x6309e7e4, (q31_t)0xaee95b3f, (q31_t)0x6305ecc9, (q31_t)0xaee47ec9, + (q31_t)0x6301f171, (q31_t)0xaedfa285, (q31_t)0x62fdf5db, (q31_t)0xaedac674, (q31_t)0x62f9fa09, (q31_t)0xaed5ea95, (q31_t)0x62f5fdf9, (q31_t)0xaed10ee7, + (q31_t)0x62f201ac, (q31_t)0xaecc336c, (q31_t)0x62ee0523, (q31_t)0xaec75823, (q31_t)0x62ea085c, (q31_t)0xaec27d0c, (q31_t)0x62e60b58, (q31_t)0xaebda227, + (q31_t)0x62e20e17, (q31_t)0xaeb8c774, (q31_t)0x62de109a, (q31_t)0xaeb3ecf3, (q31_t)0x62da12df, (q31_t)0xaeaf12a4, (q31_t)0x62d614e7, (q31_t)0xaeaa3888, + (q31_t)0x62d216b3, (q31_t)0xaea55e9e, (q31_t)0x62ce1841, (q31_t)0xaea084e6, (q31_t)0x62ca1992, (q31_t)0xae9bab60, (q31_t)0x62c61aa7, (q31_t)0xae96d20c, + (q31_t)0x62c21b7e, (q31_t)0xae91f8eb, (q31_t)0x62be1c19, (q31_t)0xae8d1ffb, (q31_t)0x62ba1c77, (q31_t)0xae88473e, (q31_t)0x62b61c98, (q31_t)0xae836eb4, + (q31_t)0x62b21c7b, (q31_t)0xae7e965b, (q31_t)0x62ae1c23, (q31_t)0xae79be35, (q31_t)0x62aa1b8d, (q31_t)0xae74e641, (q31_t)0x62a61aba, (q31_t)0xae700e80, + (q31_t)0x62a219aa, (q31_t)0xae6b36f0, (q31_t)0x629e185e, (q31_t)0xae665f93, (q31_t)0x629a16d5, (q31_t)0xae618869, (q31_t)0x6296150f, (q31_t)0xae5cb171, + (q31_t)0x6292130c, (q31_t)0xae57daab, (q31_t)0x628e10cc, (q31_t)0xae530417, (q31_t)0x628a0e50, (q31_t)0xae4e2db6, (q31_t)0x62860b97, (q31_t)0xae495787, + (q31_t)0x628208a1, (q31_t)0xae44818b, (q31_t)0x627e056e, (q31_t)0xae3fabc1, (q31_t)0x627a01fe, (q31_t)0xae3ad629, (q31_t)0x6275fe52, (q31_t)0xae3600c4, + (q31_t)0x6271fa69, (q31_t)0xae312b92, (q31_t)0x626df643, (q31_t)0xae2c5691, (q31_t)0x6269f1e1, (q31_t)0xae2781c4, (q31_t)0x6265ed42, (q31_t)0xae22ad29, + (q31_t)0x6261e866, (q31_t)0xae1dd8c0, (q31_t)0x625de34e, (q31_t)0xae19048a, (q31_t)0x6259ddf8, (q31_t)0xae143086, (q31_t)0x6255d866, (q31_t)0xae0f5cb5, + (q31_t)0x6251d298, (q31_t)0xae0a8916, (q31_t)0x624dcc8d, (q31_t)0xae05b5aa, (q31_t)0x6249c645, (q31_t)0xae00e271, (q31_t)0x6245bfc0, (q31_t)0xadfc0f6a, + (q31_t)0x6241b8ff, (q31_t)0xadf73c96, (q31_t)0x623db202, (q31_t)0xadf269f4, (q31_t)0x6239aac7, (q31_t)0xaded9785, (q31_t)0x6235a351, (q31_t)0xade8c548, + (q31_t)0x62319b9d, (q31_t)0xade3f33e, (q31_t)0x622d93ad, (q31_t)0xaddf2167, (q31_t)0x62298b81, (q31_t)0xadda4fc3, (q31_t)0x62258317, (q31_t)0xadd57e51, + (q31_t)0x62217a72, (q31_t)0xadd0ad12, (q31_t)0x621d7190, (q31_t)0xadcbdc05, (q31_t)0x62196871, (q31_t)0xadc70b2c, (q31_t)0x62155f16, (q31_t)0xadc23a85, + (q31_t)0x6211557e, (q31_t)0xadbd6a10, (q31_t)0x620d4baa, (q31_t)0xadb899cf, (q31_t)0x62094199, (q31_t)0xadb3c9c0, (q31_t)0x6205374c, (q31_t)0xadaef9e4, + (q31_t)0x62012cc2, (q31_t)0xadaa2a3b, (q31_t)0x61fd21fc, (q31_t)0xada55ac4, (q31_t)0x61f916f9, (q31_t)0xada08b80, (q31_t)0x61f50bba, (q31_t)0xad9bbc70, + (q31_t)0x61f1003f, (q31_t)0xad96ed92, (q31_t)0x61ecf487, (q31_t)0xad921ee6, (q31_t)0x61e8e893, (q31_t)0xad8d506e, (q31_t)0x61e4dc62, (q31_t)0xad888229, + (q31_t)0x61e0cff5, (q31_t)0xad83b416, (q31_t)0x61dcc34c, (q31_t)0xad7ee636, (q31_t)0x61d8b666, (q31_t)0xad7a1889, (q31_t)0x61d4a944, (q31_t)0xad754b0f, + (q31_t)0x61d09be5, (q31_t)0xad707dc8, (q31_t)0x61cc8e4b, (q31_t)0xad6bb0b4, (q31_t)0x61c88074, (q31_t)0xad66e3d3, (q31_t)0x61c47260, (q31_t)0xad621725, + (q31_t)0x61c06410, (q31_t)0xad5d4aaa, (q31_t)0x61bc5584, (q31_t)0xad587e61, (q31_t)0x61b846bc, (q31_t)0xad53b24c, (q31_t)0x61b437b7, (q31_t)0xad4ee66a, + (q31_t)0x61b02876, (q31_t)0xad4a1aba, (q31_t)0x61ac18f9, (q31_t)0xad454f3e, (q31_t)0x61a80940, (q31_t)0xad4083f5, (q31_t)0x61a3f94a, (q31_t)0xad3bb8df, + (q31_t)0x619fe918, (q31_t)0xad36edfc, (q31_t)0x619bd8aa, (q31_t)0xad32234b, (q31_t)0x6197c800, (q31_t)0xad2d58ce, (q31_t)0x6193b719, (q31_t)0xad288e85, + (q31_t)0x618fa5f7, (q31_t)0xad23c46e, (q31_t)0x618b9498, (q31_t)0xad1efa8a, (q31_t)0x618782fd, (q31_t)0xad1a30d9, (q31_t)0x61837126, (q31_t)0xad15675c, + (q31_t)0x617f5f12, (q31_t)0xad109e12, (q31_t)0x617b4cc3, (q31_t)0xad0bd4fb, (q31_t)0x61773a37, (q31_t)0xad070c17, (q31_t)0x61732770, (q31_t)0xad024366, + (q31_t)0x616f146c, (q31_t)0xacfd7ae8, (q31_t)0x616b012c, (q31_t)0xacf8b29e, (q31_t)0x6166edb0, (q31_t)0xacf3ea87, (q31_t)0x6162d9f8, (q31_t)0xacef22a3, + (q31_t)0x615ec603, (q31_t)0xacea5af2, (q31_t)0x615ab1d3, (q31_t)0xace59375, (q31_t)0x61569d67, (q31_t)0xace0cc2b, (q31_t)0x615288be, (q31_t)0xacdc0514, + (q31_t)0x614e73da, (q31_t)0xacd73e30, (q31_t)0x614a5eba, (q31_t)0xacd27780, (q31_t)0x6146495d, (q31_t)0xaccdb103, (q31_t)0x614233c5, (q31_t)0xacc8eab9, + (q31_t)0x613e1df0, (q31_t)0xacc424a3, (q31_t)0x613a07e0, (q31_t)0xacbf5ec0, (q31_t)0x6135f193, (q31_t)0xacba9910, (q31_t)0x6131db0b, (q31_t)0xacb5d394, + (q31_t)0x612dc447, (q31_t)0xacb10e4b, (q31_t)0x6129ad46, (q31_t)0xacac4935, (q31_t)0x6125960a, (q31_t)0xaca78453, (q31_t)0x61217e92, (q31_t)0xaca2bfa4, + (q31_t)0x611d66de, (q31_t)0xac9dfb29, (q31_t)0x61194eee, (q31_t)0xac9936e1, (q31_t)0x611536c2, (q31_t)0xac9472cd, (q31_t)0x61111e5b, (q31_t)0xac8faeec, + (q31_t)0x610d05b7, (q31_t)0xac8aeb3e, (q31_t)0x6108ecd8, (q31_t)0xac8627c4, (q31_t)0x6104d3bc, (q31_t)0xac81647e, (q31_t)0x6100ba65, (q31_t)0xac7ca16b, + (q31_t)0x60fca0d2, (q31_t)0xac77de8b, (q31_t)0x60f88703, (q31_t)0xac731bdf, (q31_t)0x60f46cf9, (q31_t)0xac6e5967, (q31_t)0x60f052b2, (q31_t)0xac699722, + (q31_t)0x60ec3830, (q31_t)0xac64d510, (q31_t)0x60e81d72, (q31_t)0xac601333, (q31_t)0x60e40278, (q31_t)0xac5b5189, (q31_t)0x60dfe743, (q31_t)0xac569012, + (q31_t)0x60dbcbd1, (q31_t)0xac51cecf, (q31_t)0x60d7b024, (q31_t)0xac4d0dc0, (q31_t)0x60d3943b, (q31_t)0xac484ce4, (q31_t)0x60cf7817, (q31_t)0xac438c3c, + (q31_t)0x60cb5bb7, (q31_t)0xac3ecbc7, (q31_t)0x60c73f1b, (q31_t)0xac3a0b87, (q31_t)0x60c32243, (q31_t)0xac354b7a, (q31_t)0x60bf0530, (q31_t)0xac308ba0, + (q31_t)0x60bae7e1, (q31_t)0xac2bcbfa, (q31_t)0x60b6ca56, (q31_t)0xac270c88, (q31_t)0x60b2ac8f, (q31_t)0xac224d4a, (q31_t)0x60ae8e8d, (q31_t)0xac1d8e40, + (q31_t)0x60aa7050, (q31_t)0xac18cf69, (q31_t)0x60a651d7, (q31_t)0xac1410c6, (q31_t)0x60a23322, (q31_t)0xac0f5256, (q31_t)0x609e1431, (q31_t)0xac0a941b, + (q31_t)0x6099f505, (q31_t)0xac05d613, (q31_t)0x6095d59d, (q31_t)0xac01183f, (q31_t)0x6091b5fa, (q31_t)0xabfc5a9f, (q31_t)0x608d961b, (q31_t)0xabf79d33, + (q31_t)0x60897601, (q31_t)0xabf2dffb, (q31_t)0x608555ab, (q31_t)0xabee22f6, (q31_t)0x60813519, (q31_t)0xabe96625, (q31_t)0x607d144c, (q31_t)0xabe4a988, + (q31_t)0x6078f344, (q31_t)0xabdfed1f, (q31_t)0x6074d200, (q31_t)0xabdb30ea, (q31_t)0x6070b080, (q31_t)0xabd674e9, (q31_t)0x606c8ec5, (q31_t)0xabd1b91c, + (q31_t)0x60686ccf, (q31_t)0xabccfd83, (q31_t)0x60644a9d, (q31_t)0xabc8421d, (q31_t)0x6060282f, (q31_t)0xabc386ec, (q31_t)0x605c0587, (q31_t)0xabbecbee, + (q31_t)0x6057e2a2, (q31_t)0xabba1125, (q31_t)0x6053bf82, (q31_t)0xabb5568f, (q31_t)0x604f9c27, (q31_t)0xabb09c2e, (q31_t)0x604b7891, (q31_t)0xababe200, + (q31_t)0x604754bf, (q31_t)0xaba72807, (q31_t)0x604330b1, (q31_t)0xaba26e41, (q31_t)0x603f0c69, (q31_t)0xab9db4b0, (q31_t)0x603ae7e5, (q31_t)0xab98fb52, + (q31_t)0x6036c325, (q31_t)0xab944229, (q31_t)0x60329e2a, (q31_t)0xab8f8934, (q31_t)0x602e78f4, (q31_t)0xab8ad073, (q31_t)0x602a5383, (q31_t)0xab8617e6, + (q31_t)0x60262dd6, (q31_t)0xab815f8d, (q31_t)0x602207ee, (q31_t)0xab7ca768, (q31_t)0x601de1ca, (q31_t)0xab77ef77, (q31_t)0x6019bb6b, (q31_t)0xab7337bb, + (q31_t)0x601594d1, (q31_t)0xab6e8032, (q31_t)0x60116dfc, (q31_t)0xab69c8de, (q31_t)0x600d46ec, (q31_t)0xab6511be, (q31_t)0x60091fa0, (q31_t)0xab605ad2, + (q31_t)0x6004f819, (q31_t)0xab5ba41a, (q31_t)0x6000d057, (q31_t)0xab56ed97, (q31_t)0x5ffca859, (q31_t)0xab523748, (q31_t)0x5ff88021, (q31_t)0xab4d812d, + (q31_t)0x5ff457ad, (q31_t)0xab48cb46, (q31_t)0x5ff02efe, (q31_t)0xab441593, (q31_t)0x5fec0613, (q31_t)0xab3f6015, (q31_t)0x5fe7dcee, (q31_t)0xab3aaacb, + (q31_t)0x5fe3b38d, (q31_t)0xab35f5b5, (q31_t)0x5fdf89f2, (q31_t)0xab3140d4, (q31_t)0x5fdb601b, (q31_t)0xab2c8c27, (q31_t)0x5fd73609, (q31_t)0xab27d7ae, + (q31_t)0x5fd30bbc, (q31_t)0xab23236a, (q31_t)0x5fcee133, (q31_t)0xab1e6f5a, (q31_t)0x5fcab670, (q31_t)0xab19bb7e, (q31_t)0x5fc68b72, (q31_t)0xab1507d7, + (q31_t)0x5fc26038, (q31_t)0xab105464, (q31_t)0x5fbe34c4, (q31_t)0xab0ba125, (q31_t)0x5fba0914, (q31_t)0xab06ee1b, (q31_t)0x5fb5dd29, (q31_t)0xab023b46, + (q31_t)0x5fb1b104, (q31_t)0xaafd88a4, (q31_t)0x5fad84a3, (q31_t)0xaaf8d637, (q31_t)0x5fa95807, (q31_t)0xaaf423ff, (q31_t)0x5fa52b31, (q31_t)0xaaef71fb, + (q31_t)0x5fa0fe1f, (q31_t)0xaaeac02c, (q31_t)0x5f9cd0d2, (q31_t)0xaae60e91, (q31_t)0x5f98a34a, (q31_t)0xaae15d2a, (q31_t)0x5f947588, (q31_t)0xaadcabf8, + (q31_t)0x5f90478a, (q31_t)0xaad7fafb, (q31_t)0x5f8c1951, (q31_t)0xaad34a32, (q31_t)0x5f87eade, (q31_t)0xaace999d, (q31_t)0x5f83bc2f, (q31_t)0xaac9e93e, + (q31_t)0x5f7f8d46, (q31_t)0xaac53912, (q31_t)0x5f7b5e22, (q31_t)0xaac0891c, (q31_t)0x5f772ec2, (q31_t)0xaabbd959, (q31_t)0x5f72ff28, (q31_t)0xaab729cc, + (q31_t)0x5f6ecf53, (q31_t)0xaab27a73, (q31_t)0x5f6a9f44, (q31_t)0xaaadcb4f, (q31_t)0x5f666ef9, (q31_t)0xaaa91c5f, (q31_t)0x5f623e73, (q31_t)0xaaa46da4, + (q31_t)0x5f5e0db3, (q31_t)0xaa9fbf1e, (q31_t)0x5f59dcb8, (q31_t)0xaa9b10cc, (q31_t)0x5f55ab82, (q31_t)0xaa9662af, (q31_t)0x5f517a11, (q31_t)0xaa91b4c7, + (q31_t)0x5f4d4865, (q31_t)0xaa8d0713, (q31_t)0x5f49167f, (q31_t)0xaa885994, (q31_t)0x5f44e45e, (q31_t)0xaa83ac4a, (q31_t)0x5f40b202, (q31_t)0xaa7eff34, + (q31_t)0x5f3c7f6b, (q31_t)0xaa7a5253, (q31_t)0x5f384c9a, (q31_t)0xaa75a5a8, (q31_t)0x5f34198e, (q31_t)0xaa70f930, (q31_t)0x5f2fe647, (q31_t)0xaa6c4cee, + (q31_t)0x5f2bb2c5, (q31_t)0xaa67a0e0, (q31_t)0x5f277f09, (q31_t)0xaa62f507, (q31_t)0x5f234b12, (q31_t)0xaa5e4963, (q31_t)0x5f1f16e0, (q31_t)0xaa599df4, + (q31_t)0x5f1ae274, (q31_t)0xaa54f2ba, (q31_t)0x5f16adcc, (q31_t)0xaa5047b4, (q31_t)0x5f1278eb, (q31_t)0xaa4b9ce3, (q31_t)0x5f0e43ce, (q31_t)0xaa46f248, + (q31_t)0x5f0a0e77, (q31_t)0xaa4247e1, (q31_t)0x5f05d8e6, (q31_t)0xaa3d9daf, (q31_t)0x5f01a31a, (q31_t)0xaa38f3b1, (q31_t)0x5efd6d13, (q31_t)0xaa3449e9, + (q31_t)0x5ef936d1, (q31_t)0xaa2fa056, (q31_t)0x5ef50055, (q31_t)0xaa2af6f7, (q31_t)0x5ef0c99f, (q31_t)0xaa264dce, (q31_t)0x5eec92ae, (q31_t)0xaa21a4d9, + (q31_t)0x5ee85b82, (q31_t)0xaa1cfc1a, (q31_t)0x5ee4241c, (q31_t)0xaa18538f, (q31_t)0x5edfec7b, (q31_t)0xaa13ab3a, (q31_t)0x5edbb49f, (q31_t)0xaa0f0319, + (q31_t)0x5ed77c8a, (q31_t)0xaa0a5b2e, (q31_t)0x5ed34439, (q31_t)0xaa05b377, (q31_t)0x5ecf0baf, (q31_t)0xaa010bf6, (q31_t)0x5ecad2e9, (q31_t)0xa9fc64a9, + (q31_t)0x5ec699e9, (q31_t)0xa9f7bd92, (q31_t)0x5ec260af, (q31_t)0xa9f316b0, (q31_t)0x5ebe273b, (q31_t)0xa9ee7002, (q31_t)0x5eb9ed8b, (q31_t)0xa9e9c98a, + (q31_t)0x5eb5b3a2, (q31_t)0xa9e52347, (q31_t)0x5eb1797e, (q31_t)0xa9e07d39, (q31_t)0x5ead3f1f, (q31_t)0xa9dbd761, (q31_t)0x5ea90487, (q31_t)0xa9d731bd, + (q31_t)0x5ea4c9b3, (q31_t)0xa9d28c4e, (q31_t)0x5ea08ea6, (q31_t)0xa9cde715, (q31_t)0x5e9c535e, (q31_t)0xa9c94211, (q31_t)0x5e9817dc, (q31_t)0xa9c49d42, + (q31_t)0x5e93dc1f, (q31_t)0xa9bff8a8, (q31_t)0x5e8fa028, (q31_t)0xa9bb5444, (q31_t)0x5e8b63f7, (q31_t)0xa9b6b014, (q31_t)0x5e87278b, (q31_t)0xa9b20c1a, + (q31_t)0x5e82eae5, (q31_t)0xa9ad6855, (q31_t)0x5e7eae05, (q31_t)0xa9a8c4c5, (q31_t)0x5e7a70ea, (q31_t)0xa9a4216b, (q31_t)0x5e763395, (q31_t)0xa99f7e46, + (q31_t)0x5e71f606, (q31_t)0xa99adb56, (q31_t)0x5e6db83d, (q31_t)0xa996389b, (q31_t)0x5e697a39, (q31_t)0xa9919616, (q31_t)0x5e653bfc, (q31_t)0xa98cf3c6, + (q31_t)0x5e60fd84, (q31_t)0xa98851ac, (q31_t)0x5e5cbed1, (q31_t)0xa983afc6, (q31_t)0x5e587fe5, (q31_t)0xa97f0e16, (q31_t)0x5e5440be, (q31_t)0xa97a6c9c, + (q31_t)0x5e50015d, (q31_t)0xa975cb57, (q31_t)0x5e4bc1c2, (q31_t)0xa9712a47, (q31_t)0x5e4781ed, (q31_t)0xa96c896c, (q31_t)0x5e4341de, (q31_t)0xa967e8c7, + (q31_t)0x5e3f0194, (q31_t)0xa9634858, (q31_t)0x5e3ac110, (q31_t)0xa95ea81d, (q31_t)0x5e368053, (q31_t)0xa95a0819, (q31_t)0x5e323f5b, (q31_t)0xa9556849, + (q31_t)0x5e2dfe29, (q31_t)0xa950c8b0, (q31_t)0x5e29bcbd, (q31_t)0xa94c294b, (q31_t)0x5e257b17, (q31_t)0xa9478a1c, (q31_t)0x5e213936, (q31_t)0xa942eb23, + (q31_t)0x5e1cf71c, (q31_t)0xa93e4c5f, (q31_t)0x5e18b4c8, (q31_t)0xa939add1, (q31_t)0x5e147239, (q31_t)0xa9350f78, (q31_t)0x5e102f71, (q31_t)0xa9307155, + (q31_t)0x5e0bec6e, (q31_t)0xa92bd367, (q31_t)0x5e07a932, (q31_t)0xa92735af, (q31_t)0x5e0365bb, (q31_t)0xa922982c, (q31_t)0x5dff220b, (q31_t)0xa91dfadf, + (q31_t)0x5dfade20, (q31_t)0xa9195dc7, (q31_t)0x5df699fc, (q31_t)0xa914c0e6, (q31_t)0x5df2559e, (q31_t)0xa9102439, (q31_t)0x5dee1105, (q31_t)0xa90b87c3, + (q31_t)0x5de9cc33, (q31_t)0xa906eb82, (q31_t)0x5de58727, (q31_t)0xa9024f76, (q31_t)0x5de141e1, (q31_t)0xa8fdb3a1, (q31_t)0x5ddcfc61, (q31_t)0xa8f91801, + (q31_t)0x5dd8b6a7, (q31_t)0xa8f47c97, (q31_t)0x5dd470b3, (q31_t)0xa8efe162, (q31_t)0x5dd02a85, (q31_t)0xa8eb4663, (q31_t)0x5dcbe41d, (q31_t)0xa8e6ab9a, + (q31_t)0x5dc79d7c, (q31_t)0xa8e21106, (q31_t)0x5dc356a1, (q31_t)0xa8dd76a9, (q31_t)0x5dbf0f8c, (q31_t)0xa8d8dc81, (q31_t)0x5dbac83d, (q31_t)0xa8d4428f, + (q31_t)0x5db680b4, (q31_t)0xa8cfa8d2, (q31_t)0x5db238f1, (q31_t)0xa8cb0f4b, (q31_t)0x5dadf0f5, (q31_t)0xa8c675fb, (q31_t)0x5da9a8bf, (q31_t)0xa8c1dce0, + (q31_t)0x5da5604f, (q31_t)0xa8bd43fa, (q31_t)0x5da117a5, (q31_t)0xa8b8ab4b, (q31_t)0x5d9ccec2, (q31_t)0xa8b412d1, (q31_t)0x5d9885a5, (q31_t)0xa8af7a8e, + (q31_t)0x5d943c4e, (q31_t)0xa8aae280, (q31_t)0x5d8ff2bd, (q31_t)0xa8a64aa8, (q31_t)0x5d8ba8f3, (q31_t)0xa8a1b306, (q31_t)0x5d875eef, (q31_t)0xa89d1b99, + (q31_t)0x5d8314b1, (q31_t)0xa8988463, (q31_t)0x5d7eca39, (q31_t)0xa893ed63, (q31_t)0x5d7a7f88, (q31_t)0xa88f5698, (q31_t)0x5d76349d, (q31_t)0xa88ac004, + (q31_t)0x5d71e979, (q31_t)0xa88629a5, (q31_t)0x5d6d9e1b, (q31_t)0xa881937c, (q31_t)0x5d695283, (q31_t)0xa87cfd8a, (q31_t)0x5d6506b2, (q31_t)0xa87867cd, + (q31_t)0x5d60baa7, (q31_t)0xa873d246, (q31_t)0x5d5c6e62, (q31_t)0xa86f3cf6, (q31_t)0x5d5821e4, (q31_t)0xa86aa7db, (q31_t)0x5d53d52d, (q31_t)0xa86612f6, + (q31_t)0x5d4f883b, (q31_t)0xa8617e48, (q31_t)0x5d4b3b10, (q31_t)0xa85ce9cf, (q31_t)0x5d46edac, (q31_t)0xa858558d, (q31_t)0x5d42a00e, (q31_t)0xa853c180, + (q31_t)0x5d3e5237, (q31_t)0xa84f2daa, (q31_t)0x5d3a0426, (q31_t)0xa84a9a0a, (q31_t)0x5d35b5db, (q31_t)0xa84606a0, (q31_t)0x5d316757, (q31_t)0xa841736c, + (q31_t)0x5d2d189a, (q31_t)0xa83ce06e, (q31_t)0x5d28c9a3, (q31_t)0xa8384da6, (q31_t)0x5d247a72, (q31_t)0xa833bb14, (q31_t)0x5d202b09, (q31_t)0xa82f28b9, + (q31_t)0x5d1bdb65, (q31_t)0xa82a9693, (q31_t)0x5d178b89, (q31_t)0xa82604a4, (q31_t)0x5d133b72, (q31_t)0xa82172eb, (q31_t)0x5d0eeb23, (q31_t)0xa81ce169, + (q31_t)0x5d0a9a9a, (q31_t)0xa818501c, (q31_t)0x5d0649d7, (q31_t)0xa813bf06, (q31_t)0x5d01f8dc, (q31_t)0xa80f2e26, (q31_t)0x5cfda7a7, (q31_t)0xa80a9d7c, + (q31_t)0x5cf95638, (q31_t)0xa8060d08, (q31_t)0x5cf50490, (q31_t)0xa8017ccb, (q31_t)0x5cf0b2af, (q31_t)0xa7fcecc4, (q31_t)0x5cec6095, (q31_t)0xa7f85cf3, + (q31_t)0x5ce80e41, (q31_t)0xa7f3cd59, (q31_t)0x5ce3bbb4, (q31_t)0xa7ef3df5, (q31_t)0x5cdf68ed, (q31_t)0xa7eaaec7, (q31_t)0x5cdb15ed, (q31_t)0xa7e61fd0, + (q31_t)0x5cd6c2b5, (q31_t)0xa7e1910f, (q31_t)0x5cd26f42, (q31_t)0xa7dd0284, (q31_t)0x5cce1b97, (q31_t)0xa7d8742f, (q31_t)0x5cc9c7b2, (q31_t)0xa7d3e611, + (q31_t)0x5cc57394, (q31_t)0xa7cf582a, (q31_t)0x5cc11f3d, (q31_t)0xa7caca79, (q31_t)0x5cbccaac, (q31_t)0xa7c63cfe, (q31_t)0x5cb875e3, (q31_t)0xa7c1afb9, + (q31_t)0x5cb420e0, (q31_t)0xa7bd22ac, (q31_t)0x5cafcba4, (q31_t)0xa7b895d4, (q31_t)0x5cab762f, (q31_t)0xa7b40933, (q31_t)0x5ca72080, (q31_t)0xa7af7cc8, + (q31_t)0x5ca2ca99, (q31_t)0xa7aaf094, (q31_t)0x5c9e7478, (q31_t)0xa7a66497, (q31_t)0x5c9a1e1e, (q31_t)0xa7a1d8d0, (q31_t)0x5c95c78b, (q31_t)0xa79d4d3f, + (q31_t)0x5c9170bf, (q31_t)0xa798c1e5, (q31_t)0x5c8d19ba, (q31_t)0xa79436c1, (q31_t)0x5c88c27c, (q31_t)0xa78fabd4, (q31_t)0x5c846b05, (q31_t)0xa78b211e, + (q31_t)0x5c801354, (q31_t)0xa786969e, (q31_t)0x5c7bbb6b, (q31_t)0xa7820c55, (q31_t)0x5c776348, (q31_t)0xa77d8242, (q31_t)0x5c730aed, (q31_t)0xa778f866, + (q31_t)0x5c6eb258, (q31_t)0xa7746ec0, (q31_t)0x5c6a598b, (q31_t)0xa76fe551, (q31_t)0x5c660084, (q31_t)0xa76b5c19, (q31_t)0x5c61a745, (q31_t)0xa766d317, + (q31_t)0x5c5d4dcc, (q31_t)0xa7624a4d, (q31_t)0x5c58f41a, (q31_t)0xa75dc1b8, (q31_t)0x5c549a30, (q31_t)0xa759395b, (q31_t)0x5c50400d, (q31_t)0xa754b134, + (q31_t)0x5c4be5b0, (q31_t)0xa7502943, (q31_t)0x5c478b1b, (q31_t)0xa74ba18a, (q31_t)0x5c43304d, (q31_t)0xa7471a07, (q31_t)0x5c3ed545, (q31_t)0xa74292bb, + (q31_t)0x5c3a7a05, (q31_t)0xa73e0ba5, (q31_t)0x5c361e8c, (q31_t)0xa73984c7, (q31_t)0x5c31c2db, (q31_t)0xa734fe1f, (q31_t)0x5c2d66f0, (q31_t)0xa73077ae, + (q31_t)0x5c290acc, (q31_t)0xa72bf174, (q31_t)0x5c24ae70, (q31_t)0xa7276b70, (q31_t)0x5c2051db, (q31_t)0xa722e5a3, (q31_t)0x5c1bf50d, (q31_t)0xa71e600d, + (q31_t)0x5c179806, (q31_t)0xa719daae, (q31_t)0x5c133ac6, (q31_t)0xa7155586, (q31_t)0x5c0edd4e, (q31_t)0xa710d095, (q31_t)0x5c0a7f9c, (q31_t)0xa70c4bda, + (q31_t)0x5c0621b2, (q31_t)0xa707c757, (q31_t)0x5c01c38f, (q31_t)0xa703430a, (q31_t)0x5bfd6534, (q31_t)0xa6febef4, (q31_t)0x5bf906a0, (q31_t)0xa6fa3b15, + (q31_t)0x5bf4a7d2, (q31_t)0xa6f5b76d, (q31_t)0x5bf048cd, (q31_t)0xa6f133fc, (q31_t)0x5bebe98e, (q31_t)0xa6ecb0c2, (q31_t)0x5be78a17, (q31_t)0xa6e82dbe, + (q31_t)0x5be32a67, (q31_t)0xa6e3aaf2, (q31_t)0x5bdeca7f, (q31_t)0xa6df285d, (q31_t)0x5bda6a5d, (q31_t)0xa6daa5fe, (q31_t)0x5bd60a03, (q31_t)0xa6d623d7, + (q31_t)0x5bd1a971, (q31_t)0xa6d1a1e7, (q31_t)0x5bcd48a6, (q31_t)0xa6cd202d, (q31_t)0x5bc8e7a2, (q31_t)0xa6c89eab, (q31_t)0x5bc48666, (q31_t)0xa6c41d60, + (q31_t)0x5bc024f0, (q31_t)0xa6bf9c4b, (q31_t)0x5bbbc343, (q31_t)0xa6bb1b6e, (q31_t)0x5bb7615d, (q31_t)0xa6b69ac8, (q31_t)0x5bb2ff3e, (q31_t)0xa6b21a59, + (q31_t)0x5bae9ce7, (q31_t)0xa6ad9a21, (q31_t)0x5baa3a57, (q31_t)0xa6a91a20, (q31_t)0x5ba5d78e, (q31_t)0xa6a49a56, (q31_t)0x5ba1748d, (q31_t)0xa6a01ac4, + (q31_t)0x5b9d1154, (q31_t)0xa69b9b68, (q31_t)0x5b98ade2, (q31_t)0xa6971c44, (q31_t)0x5b944a37, (q31_t)0xa6929d57, (q31_t)0x5b8fe654, (q31_t)0xa68e1ea1, + (q31_t)0x5b8b8239, (q31_t)0xa689a022, (q31_t)0x5b871de5, (q31_t)0xa68521da, (q31_t)0x5b82b958, (q31_t)0xa680a3ca, (q31_t)0x5b7e5493, (q31_t)0xa67c25f0, + (q31_t)0x5b79ef96, (q31_t)0xa677a84e, (q31_t)0x5b758a60, (q31_t)0xa6732ae3, (q31_t)0x5b7124f2, (q31_t)0xa66eadb0, (q31_t)0x5b6cbf4c, (q31_t)0xa66a30b3, + (q31_t)0x5b68596d, (q31_t)0xa665b3ee, (q31_t)0x5b63f355, (q31_t)0xa6613760, (q31_t)0x5b5f8d06, (q31_t)0xa65cbb0a, (q31_t)0x5b5b267e, (q31_t)0xa6583eeb, + (q31_t)0x5b56bfbd, (q31_t)0xa653c303, (q31_t)0x5b5258c4, (q31_t)0xa64f4752, (q31_t)0x5b4df193, (q31_t)0xa64acbd9, (q31_t)0x5b498a2a, (q31_t)0xa6465097, + (q31_t)0x5b452288, (q31_t)0xa641d58c, (q31_t)0x5b40baae, (q31_t)0xa63d5ab9, (q31_t)0x5b3c529c, (q31_t)0xa638e01d, (q31_t)0x5b37ea51, (q31_t)0xa63465b9, + (q31_t)0x5b3381ce, (q31_t)0xa62feb8b, (q31_t)0x5b2f1913, (q31_t)0xa62b7196, (q31_t)0x5b2ab020, (q31_t)0xa626f7d7, (q31_t)0x5b2646f4, (q31_t)0xa6227e50, + (q31_t)0x5b21dd90, (q31_t)0xa61e0501, (q31_t)0x5b1d73f4, (q31_t)0xa6198be9, (q31_t)0x5b190a20, (q31_t)0xa6151308, (q31_t)0x5b14a014, (q31_t)0xa6109a5f, + (q31_t)0x5b1035cf, (q31_t)0xa60c21ee, (q31_t)0x5b0bcb52, (q31_t)0xa607a9b4, (q31_t)0x5b07609d, (q31_t)0xa60331b1, (q31_t)0x5b02f5b0, (q31_t)0xa5feb9e6, + (q31_t)0x5afe8a8b, (q31_t)0xa5fa4252, (q31_t)0x5afa1f2e, (q31_t)0xa5f5caf6, (q31_t)0x5af5b398, (q31_t)0xa5f153d2, (q31_t)0x5af147ca, (q31_t)0xa5ecdce5, + (q31_t)0x5aecdbc5, (q31_t)0xa5e8662f, (q31_t)0x5ae86f87, (q31_t)0xa5e3efb1, (q31_t)0x5ae40311, (q31_t)0xa5df796b, (q31_t)0x5adf9663, (q31_t)0xa5db035c, + (q31_t)0x5adb297d, (q31_t)0xa5d68d85, (q31_t)0x5ad6bc5f, (q31_t)0xa5d217e6, (q31_t)0x5ad24f09, (q31_t)0xa5cda27e, (q31_t)0x5acde17b, (q31_t)0xa5c92d4e, + (q31_t)0x5ac973b5, (q31_t)0xa5c4b855, (q31_t)0x5ac505b7, (q31_t)0xa5c04395, (q31_t)0x5ac09781, (q31_t)0xa5bbcf0b, (q31_t)0x5abc2912, (q31_t)0xa5b75aba, + (q31_t)0x5ab7ba6c, (q31_t)0xa5b2e6a0, (q31_t)0x5ab34b8e, (q31_t)0xa5ae72be, (q31_t)0x5aaedc78, (q31_t)0xa5a9ff14, (q31_t)0x5aaa6d2b, (q31_t)0xa5a58ba1, + (q31_t)0x5aa5fda5, (q31_t)0xa5a11866, (q31_t)0x5aa18de7, (q31_t)0xa59ca563, (q31_t)0x5a9d1df1, (q31_t)0xa5983297, (q31_t)0x5a98adc4, (q31_t)0xa593c004, + (q31_t)0x5a943d5e, (q31_t)0xa58f4da8, (q31_t)0x5a8fccc1, (q31_t)0xa58adb84, (q31_t)0x5a8b5bec, (q31_t)0xa5866997, (q31_t)0x5a86eadf, (q31_t)0xa581f7e3, + (q31_t)0x5a82799a, (q31_t)0xa57d8666, (q31_t)0x5a7e081d, (q31_t)0xa5791521, (q31_t)0x5a799669, (q31_t)0xa574a414, (q31_t)0x5a75247c, (q31_t)0xa570333f, + (q31_t)0x5a70b258, (q31_t)0xa56bc2a2, (q31_t)0x5a6c3ffc, (q31_t)0xa567523c, (q31_t)0x5a67cd69, (q31_t)0xa562e20f, (q31_t)0x5a635a9d, (q31_t)0xa55e7219, + (q31_t)0x5a5ee79a, (q31_t)0xa55a025b, (q31_t)0x5a5a745f, (q31_t)0xa55592d5, (q31_t)0x5a5600ec, (q31_t)0xa5512388, (q31_t)0x5a518d42, (q31_t)0xa54cb472, + (q31_t)0x5a4d1960, (q31_t)0xa5484594, (q31_t)0x5a48a546, (q31_t)0xa543d6ee, (q31_t)0x5a4430f5, (q31_t)0xa53f687f, (q31_t)0x5a3fbc6b, (q31_t)0xa53afa49, + (q31_t)0x5a3b47ab, (q31_t)0xa5368c4b, (q31_t)0x5a36d2b2, (q31_t)0xa5321e85, (q31_t)0x5a325d82, (q31_t)0xa52db0f7, (q31_t)0x5a2de81a, (q31_t)0xa52943a1, + (q31_t)0x5a29727b, (q31_t)0xa524d683, (q31_t)0x5a24fca4, (q31_t)0xa520699d, (q31_t)0x5a208695, (q31_t)0xa51bfcef, (q31_t)0x5a1c104f, (q31_t)0xa5179079, + (q31_t)0x5a1799d1, (q31_t)0xa513243b, (q31_t)0x5a13231b, (q31_t)0xa50eb836, (q31_t)0x5a0eac2e, (q31_t)0xa50a4c68, (q31_t)0x5a0a350a, (q31_t)0xa505e0d2, + (q31_t)0x5a05bdae, (q31_t)0xa5017575, (q31_t)0x5a01461a, (q31_t)0xa4fd0a50, (q31_t)0x59fcce4f, (q31_t)0xa4f89f63, (q31_t)0x59f8564c, (q31_t)0xa4f434ae, + (q31_t)0x59f3de12, (q31_t)0xa4efca31, (q31_t)0x59ef65a1, (q31_t)0xa4eb5fec, (q31_t)0x59eaecf8, (q31_t)0xa4e6f5e0, (q31_t)0x59e67417, (q31_t)0xa4e28c0c, + (q31_t)0x59e1faff, (q31_t)0xa4de2270, (q31_t)0x59dd81b0, (q31_t)0xa4d9b90c, (q31_t)0x59d90829, (q31_t)0xa4d54fe0, (q31_t)0x59d48e6a, (q31_t)0xa4d0e6ed, + (q31_t)0x59d01475, (q31_t)0xa4cc7e32, (q31_t)0x59cb9a47, (q31_t)0xa4c815af, (q31_t)0x59c71fe3, (q31_t)0xa4c3ad64, (q31_t)0x59c2a547, (q31_t)0xa4bf4552, + (q31_t)0x59be2a74, (q31_t)0xa4badd78, (q31_t)0x59b9af69, (q31_t)0xa4b675d6, (q31_t)0x59b53427, (q31_t)0xa4b20e6d, (q31_t)0x59b0b8ae, (q31_t)0xa4ada73c, + (q31_t)0x59ac3cfd, (q31_t)0xa4a94043, (q31_t)0x59a7c115, (q31_t)0xa4a4d982, (q31_t)0x59a344f6, (q31_t)0xa4a072fa, (q31_t)0x599ec8a0, (q31_t)0xa49c0cab, + (q31_t)0x599a4c12, (q31_t)0xa497a693, (q31_t)0x5995cf4d, (q31_t)0xa49340b4, (q31_t)0x59915250, (q31_t)0xa48edb0e, (q31_t)0x598cd51d, (q31_t)0xa48a75a0, + (q31_t)0x598857b2, (q31_t)0xa486106a, (q31_t)0x5983da10, (q31_t)0xa481ab6d, (q31_t)0x597f5c36, (q31_t)0xa47d46a8, (q31_t)0x597ade26, (q31_t)0xa478e21b, + (q31_t)0x59765fde, (q31_t)0xa4747dc7, (q31_t)0x5971e15f, (q31_t)0xa47019ac, (q31_t)0x596d62a9, (q31_t)0xa46bb5c9, (q31_t)0x5968e3bc, (q31_t)0xa467521e, + (q31_t)0x59646498, (q31_t)0xa462eeac, (q31_t)0x595fe53c, (q31_t)0xa45e8b73, (q31_t)0x595b65aa, (q31_t)0xa45a2872, (q31_t)0x5956e5e0, (q31_t)0xa455c5a9, + (q31_t)0x595265df, (q31_t)0xa4516319, (q31_t)0x594de5a7, (q31_t)0xa44d00c2, (q31_t)0x59496538, (q31_t)0xa4489ea3, (q31_t)0x5944e492, (q31_t)0xa4443cbd, + (q31_t)0x594063b5, (q31_t)0xa43fdb10, (q31_t)0x593be2a0, (q31_t)0xa43b799a, (q31_t)0x59376155, (q31_t)0xa437185e, (q31_t)0x5932dfd3, (q31_t)0xa432b75a, + (q31_t)0x592e5e19, (q31_t)0xa42e568f, (q31_t)0x5929dc29, (q31_t)0xa429f5fd, (q31_t)0x59255a02, (q31_t)0xa42595a3, (q31_t)0x5920d7a3, (q31_t)0xa4213581, + (q31_t)0x591c550e, (q31_t)0xa41cd599, (q31_t)0x5917d242, (q31_t)0xa41875e9, (q31_t)0x59134f3e, (q31_t)0xa4141672, (q31_t)0x590ecc04, (q31_t)0xa40fb733, + (q31_t)0x590a4893, (q31_t)0xa40b582e, (q31_t)0x5905c4eb, (q31_t)0xa406f960, (q31_t)0x5901410c, (q31_t)0xa4029acc, (q31_t)0x58fcbcf6, (q31_t)0xa3fe3c71, + (q31_t)0x58f838a9, (q31_t)0xa3f9de4e, (q31_t)0x58f3b426, (q31_t)0xa3f58064, (q31_t)0x58ef2f6b, (q31_t)0xa3f122b2, (q31_t)0x58eaaa7a, (q31_t)0xa3ecc53a, + (q31_t)0x58e62552, (q31_t)0xa3e867fa, (q31_t)0x58e19ff3, (q31_t)0xa3e40af3, (q31_t)0x58dd1a5d, (q31_t)0xa3dfae25, (q31_t)0x58d89490, (q31_t)0xa3db5190, + (q31_t)0x58d40e8c, (q31_t)0xa3d6f534, (q31_t)0x58cf8852, (q31_t)0xa3d29910, (q31_t)0x58cb01e1, (q31_t)0xa3ce3d25, (q31_t)0x58c67b39, (q31_t)0xa3c9e174, + (q31_t)0x58c1f45b, (q31_t)0xa3c585fb, (q31_t)0x58bd6d45, (q31_t)0xa3c12abb, (q31_t)0x58b8e5f9, (q31_t)0xa3bccfb3, (q31_t)0x58b45e76, (q31_t)0xa3b874e5, + (q31_t)0x58afd6bd, (q31_t)0xa3b41a50, (q31_t)0x58ab4ecc, (q31_t)0xa3afbff3, (q31_t)0x58a6c6a5, (q31_t)0xa3ab65d0, (q31_t)0x58a23e48, (q31_t)0xa3a70be6, + (q31_t)0x589db5b3, (q31_t)0xa3a2b234, (q31_t)0x58992ce9, (q31_t)0xa39e58bb, (q31_t)0x5894a3e7, (q31_t)0xa399ff7c, (q31_t)0x58901aaf, (q31_t)0xa395a675, + (q31_t)0x588b9140, (q31_t)0xa3914da8, (q31_t)0x5887079a, (q31_t)0xa38cf513, (q31_t)0x58827dbe, (q31_t)0xa3889cb8, (q31_t)0x587df3ab, (q31_t)0xa3844495, + (q31_t)0x58796962, (q31_t)0xa37fecac, (q31_t)0x5874dee2, (q31_t)0xa37b94fb, (q31_t)0x5870542c, (q31_t)0xa3773d84, (q31_t)0x586bc93f, (q31_t)0xa372e646, + (q31_t)0x58673e1b, (q31_t)0xa36e8f41, (q31_t)0x5862b2c1, (q31_t)0xa36a3875, (q31_t)0x585e2730, (q31_t)0xa365e1e2, (q31_t)0x58599b69, (q31_t)0xa3618b88, + (q31_t)0x58550f6c, (q31_t)0xa35d3567, (q31_t)0x58508338, (q31_t)0xa358df80, (q31_t)0x584bf6cd, (q31_t)0xa35489d1, (q31_t)0x58476a2c, (q31_t)0xa350345c, + (q31_t)0x5842dd54, (q31_t)0xa34bdf20, (q31_t)0x583e5047, (q31_t)0xa3478a1d, (q31_t)0x5839c302, (q31_t)0xa3433554, (q31_t)0x58353587, (q31_t)0xa33ee0c3, + (q31_t)0x5830a7d6, (q31_t)0xa33a8c6c, (q31_t)0x582c19ef, (q31_t)0xa336384e, (q31_t)0x58278bd1, (q31_t)0xa331e469, (q31_t)0x5822fd7c, (q31_t)0xa32d90be, + (q31_t)0x581e6ef1, (q31_t)0xa3293d4b, (q31_t)0x5819e030, (q31_t)0xa324ea13, (q31_t)0x58155139, (q31_t)0xa3209713, (q31_t)0x5810c20b, (q31_t)0xa31c444c, + (q31_t)0x580c32a7, (q31_t)0xa317f1bf, (q31_t)0x5807a30d, (q31_t)0xa3139f6b, (q31_t)0x5803133c, (q31_t)0xa30f4d51, (q31_t)0x57fe8335, (q31_t)0xa30afb70, + (q31_t)0x57f9f2f8, (q31_t)0xa306a9c8, (q31_t)0x57f56284, (q31_t)0xa3025859, (q31_t)0x57f0d1da, (q31_t)0xa2fe0724, (q31_t)0x57ec40fa, (q31_t)0xa2f9b629, + (q31_t)0x57e7afe4, (q31_t)0xa2f56566, (q31_t)0x57e31e97, (q31_t)0xa2f114dd, (q31_t)0x57de8d15, (q31_t)0xa2ecc48e, (q31_t)0x57d9fb5c, (q31_t)0xa2e87477, + (q31_t)0x57d5696d, (q31_t)0xa2e4249b, (q31_t)0x57d0d747, (q31_t)0xa2dfd4f7, (q31_t)0x57cc44ec, (q31_t)0xa2db858e, (q31_t)0x57c7b25a, (q31_t)0xa2d7365d, + (q31_t)0x57c31f92, (q31_t)0xa2d2e766, (q31_t)0x57be8c94, (q31_t)0xa2ce98a9, (q31_t)0x57b9f960, (q31_t)0xa2ca4a25, (q31_t)0x57b565f6, (q31_t)0xa2c5fbda, + (q31_t)0x57b0d256, (q31_t)0xa2c1adc9, (q31_t)0x57ac3e80, (q31_t)0xa2bd5ff2, (q31_t)0x57a7aa73, (q31_t)0xa2b91254, (q31_t)0x57a31631, (q31_t)0xa2b4c4f0, + (q31_t)0x579e81b8, (q31_t)0xa2b077c5, (q31_t)0x5799ed0a, (q31_t)0xa2ac2ad3, (q31_t)0x57955825, (q31_t)0xa2a7de1c, (q31_t)0x5790c30a, (q31_t)0xa2a3919e, + (q31_t)0x578c2dba, (q31_t)0xa29f4559, (q31_t)0x57879833, (q31_t)0xa29af94e, (q31_t)0x57830276, (q31_t)0xa296ad7d, (q31_t)0x577e6c84, (q31_t)0xa29261e5, + (q31_t)0x5779d65b, (q31_t)0xa28e1687, (q31_t)0x57753ffc, (q31_t)0xa289cb63, (q31_t)0x5770a968, (q31_t)0xa2858078, (q31_t)0x576c129d, (q31_t)0xa28135c7, + (q31_t)0x57677b9d, (q31_t)0xa27ceb4f, (q31_t)0x5762e467, (q31_t)0xa278a111, (q31_t)0x575e4cfa, (q31_t)0xa274570d, (q31_t)0x5759b558, (q31_t)0xa2700d43, + (q31_t)0x57551d80, (q31_t)0xa26bc3b2, (q31_t)0x57508572, (q31_t)0xa2677a5b, (q31_t)0x574bed2f, (q31_t)0xa263313e, (q31_t)0x574754b5, (q31_t)0xa25ee85b, + (q31_t)0x5742bc06, (q31_t)0xa25a9fb1, (q31_t)0x573e2320, (q31_t)0xa2565741, (q31_t)0x57398a05, (q31_t)0xa2520f0b, (q31_t)0x5734f0b5, (q31_t)0xa24dc70f, + (q31_t)0x5730572e, (q31_t)0xa2497f4c, (q31_t)0x572bbd71, (q31_t)0xa24537c3, (q31_t)0x5727237f, (q31_t)0xa240f074, (q31_t)0x57228957, (q31_t)0xa23ca95f, + (q31_t)0x571deefa, (q31_t)0xa2386284, (q31_t)0x57195466, (q31_t)0xa2341be3, (q31_t)0x5714b99d, (q31_t)0xa22fd57b, (q31_t)0x57101e9e, (q31_t)0xa22b8f4d, + (q31_t)0x570b8369, (q31_t)0xa2274959, (q31_t)0x5706e7ff, (q31_t)0xa223039f, (q31_t)0x57024c5f, (q31_t)0xa21ebe1f, (q31_t)0x56fdb08a, (q31_t)0xa21a78d9, + (q31_t)0x56f9147e, (q31_t)0xa21633cd, (q31_t)0x56f4783d, (q31_t)0xa211eefb, (q31_t)0x56efdbc7, (q31_t)0xa20daa62, (q31_t)0x56eb3f1a, (q31_t)0xa2096604, + (q31_t)0x56e6a239, (q31_t)0xa20521e0, (q31_t)0x56e20521, (q31_t)0xa200ddf5, (q31_t)0x56dd67d4, (q31_t)0xa1fc9a45, (q31_t)0x56d8ca51, (q31_t)0xa1f856ce, + (q31_t)0x56d42c99, (q31_t)0xa1f41392, (q31_t)0x56cf8eab, (q31_t)0xa1efd08f, (q31_t)0x56caf088, (q31_t)0xa1eb8dc7, (q31_t)0x56c6522f, (q31_t)0xa1e74b38, + (q31_t)0x56c1b3a1, (q31_t)0xa1e308e4, (q31_t)0x56bd14dd, (q31_t)0xa1dec6ca, (q31_t)0x56b875e4, (q31_t)0xa1da84e9, (q31_t)0x56b3d6b5, (q31_t)0xa1d64343, + (q31_t)0x56af3750, (q31_t)0xa1d201d7, (q31_t)0x56aa97b7, (q31_t)0xa1cdc0a5, (q31_t)0x56a5f7e7, (q31_t)0xa1c97fad, (q31_t)0x56a157e3, (q31_t)0xa1c53ef0, + (q31_t)0x569cb7a8, (q31_t)0xa1c0fe6c, (q31_t)0x56981739, (q31_t)0xa1bcbe22, (q31_t)0x56937694, (q31_t)0xa1b87e13, (q31_t)0x568ed5b9, (q31_t)0xa1b43e3e, + (q31_t)0x568a34a9, (q31_t)0xa1affea3, (q31_t)0x56859364, (q31_t)0xa1abbf42, (q31_t)0x5680f1ea, (q31_t)0xa1a7801b, (q31_t)0x567c503a, (q31_t)0xa1a3412f, + (q31_t)0x5677ae54, (q31_t)0xa19f027c, (q31_t)0x56730c3a, (q31_t)0xa19ac404, (q31_t)0x566e69ea, (q31_t)0xa19685c7, (q31_t)0x5669c765, (q31_t)0xa19247c3, + (q31_t)0x566524aa, (q31_t)0xa18e09fa, (q31_t)0x566081ba, (q31_t)0xa189cc6b, (q31_t)0x565bde95, (q31_t)0xa1858f16, (q31_t)0x56573b3b, (q31_t)0xa18151fb, + (q31_t)0x565297ab, (q31_t)0xa17d151b, (q31_t)0x564df3e6, (q31_t)0xa178d875, (q31_t)0x56494fec, (q31_t)0xa1749c09, (q31_t)0x5644abbc, (q31_t)0xa1705fd8, + (q31_t)0x56400758, (q31_t)0xa16c23e1, (q31_t)0x563b62be, (q31_t)0xa167e824, (q31_t)0x5636bdef, (q31_t)0xa163aca2, (q31_t)0x563218eb, (q31_t)0xa15f715a, + (q31_t)0x562d73b2, (q31_t)0xa15b364d, (q31_t)0x5628ce43, (q31_t)0xa156fb79, (q31_t)0x5624289f, (q31_t)0xa152c0e1, (q31_t)0x561f82c7, (q31_t)0xa14e8682, + (q31_t)0x561adcb9, (q31_t)0xa14a4c5e, (q31_t)0x56163676, (q31_t)0xa1461275, (q31_t)0x56118ffe, (q31_t)0xa141d8c5, (q31_t)0x560ce950, (q31_t)0xa13d9f51, + (q31_t)0x5608426e, (q31_t)0xa1396617, (q31_t)0x56039b57, (q31_t)0xa1352d17, (q31_t)0x55fef40a, (q31_t)0xa130f451, (q31_t)0x55fa4c89, (q31_t)0xa12cbbc7, + (q31_t)0x55f5a4d2, (q31_t)0xa1288376, (q31_t)0x55f0fce7, (q31_t)0xa1244b61, (q31_t)0x55ec54c6, (q31_t)0xa1201385, (q31_t)0x55e7ac71, (q31_t)0xa11bdbe4, + (q31_t)0x55e303e6, (q31_t)0xa117a47e, (q31_t)0x55de5b27, (q31_t)0xa1136d52, (q31_t)0x55d9b232, (q31_t)0xa10f3661, (q31_t)0x55d50909, (q31_t)0xa10affab, + (q31_t)0x55d05faa, (q31_t)0xa106c92f, (q31_t)0x55cbb617, (q31_t)0xa10292ed, (q31_t)0x55c70c4f, (q31_t)0xa0fe5ce6, (q31_t)0x55c26251, (q31_t)0xa0fa271a, + (q31_t)0x55bdb81f, (q31_t)0xa0f5f189, (q31_t)0x55b90db8, (q31_t)0xa0f1bc32, (q31_t)0x55b4631d, (q31_t)0xa0ed8715, (q31_t)0x55afb84c, (q31_t)0xa0e95234, + (q31_t)0x55ab0d46, (q31_t)0xa0e51d8c, (q31_t)0x55a6620c, (q31_t)0xa0e0e920, (q31_t)0x55a1b69d, (q31_t)0xa0dcb4ee, (q31_t)0x559d0af9, (q31_t)0xa0d880f7, + (q31_t)0x55985f20, (q31_t)0xa0d44d3b, (q31_t)0x5593b312, (q31_t)0xa0d019b9, (q31_t)0x558f06d0, (q31_t)0xa0cbe672, (q31_t)0x558a5a58, (q31_t)0xa0c7b366, + (q31_t)0x5585adad, (q31_t)0xa0c38095, (q31_t)0x558100cc, (q31_t)0xa0bf4dfe, (q31_t)0x557c53b6, (q31_t)0xa0bb1ba2, (q31_t)0x5577a66c, (q31_t)0xa0b6e981, + (q31_t)0x5572f8ed, (q31_t)0xa0b2b79b, (q31_t)0x556e4b39, (q31_t)0xa0ae85ef, (q31_t)0x55699d51, (q31_t)0xa0aa547e, (q31_t)0x5564ef34, (q31_t)0xa0a62348, + (q31_t)0x556040e2, (q31_t)0xa0a1f24d, (q31_t)0x555b925c, (q31_t)0xa09dc18d, (q31_t)0x5556e3a1, (q31_t)0xa0999107, (q31_t)0x555234b1, (q31_t)0xa09560bc, + (q31_t)0x554d858d, (q31_t)0xa09130ad, (q31_t)0x5548d634, (q31_t)0xa08d00d8, (q31_t)0x554426a7, (q31_t)0xa088d13e, (q31_t)0x553f76e4, (q31_t)0xa084a1de, + (q31_t)0x553ac6ee, (q31_t)0xa08072ba, (q31_t)0x553616c2, (q31_t)0xa07c43d1, (q31_t)0x55316663, (q31_t)0xa0781522, (q31_t)0x552cb5ce, (q31_t)0xa073e6af, + (q31_t)0x55280505, (q31_t)0xa06fb876, (q31_t)0x55235408, (q31_t)0xa06b8a78, (q31_t)0x551ea2d6, (q31_t)0xa0675cb6, (q31_t)0x5519f16f, (q31_t)0xa0632f2e, + (q31_t)0x55153fd4, (q31_t)0xa05f01e1, (q31_t)0x55108e05, (q31_t)0xa05ad4cf, (q31_t)0x550bdc01, (q31_t)0xa056a7f9, (q31_t)0x550729c9, (q31_t)0xa0527b5d, + (q31_t)0x5502775c, (q31_t)0xa04e4efc, (q31_t)0x54fdc4ba, (q31_t)0xa04a22d7, (q31_t)0x54f911e5, (q31_t)0xa045f6ec, (q31_t)0x54f45edb, (q31_t)0xa041cb3c, + (q31_t)0x54efab9c, (q31_t)0xa03d9fc8, (q31_t)0x54eaf829, (q31_t)0xa039748e, (q31_t)0x54e64482, (q31_t)0xa0354990, (q31_t)0x54e190a6, (q31_t)0xa0311ecd, + (q31_t)0x54dcdc96, (q31_t)0xa02cf444, (q31_t)0x54d82852, (q31_t)0xa028c9f7, (q31_t)0x54d373d9, (q31_t)0xa0249fe5, (q31_t)0x54cebf2c, (q31_t)0xa020760e, + (q31_t)0x54ca0a4b, (q31_t)0xa01c4c73, (q31_t)0x54c55535, (q31_t)0xa0182312, (q31_t)0x54c09feb, (q31_t)0xa013f9ed, (q31_t)0x54bbea6d, (q31_t)0xa00fd102, + (q31_t)0x54b734ba, (q31_t)0xa00ba853, (q31_t)0x54b27ed3, (q31_t)0xa0077fdf, (q31_t)0x54adc8b8, (q31_t)0xa00357a7, (q31_t)0x54a91269, (q31_t)0x9fff2fa9, + (q31_t)0x54a45be6, (q31_t)0x9ffb07e7, (q31_t)0x549fa52e, (q31_t)0x9ff6e060, (q31_t)0x549aee42, (q31_t)0x9ff2b914, (q31_t)0x54963722, (q31_t)0x9fee9204, + (q31_t)0x54917fce, (q31_t)0x9fea6b2f, (q31_t)0x548cc845, (q31_t)0x9fe64495, (q31_t)0x54881089, (q31_t)0x9fe21e36, (q31_t)0x54835898, (q31_t)0x9fddf812, + (q31_t)0x547ea073, (q31_t)0x9fd9d22a, (q31_t)0x5479e81a, (q31_t)0x9fd5ac7d, (q31_t)0x54752f8d, (q31_t)0x9fd1870c, (q31_t)0x547076cc, (q31_t)0x9fcd61d6, + (q31_t)0x546bbdd7, (q31_t)0x9fc93cdb, (q31_t)0x546704ae, (q31_t)0x9fc5181b, (q31_t)0x54624b50, (q31_t)0x9fc0f397, (q31_t)0x545d91bf, (q31_t)0x9fbccf4f, + (q31_t)0x5458d7f9, (q31_t)0x9fb8ab41, (q31_t)0x54541e00, (q31_t)0x9fb4876f, (q31_t)0x544f63d2, (q31_t)0x9fb063d9, (q31_t)0x544aa971, (q31_t)0x9fac407e, + (q31_t)0x5445eedb, (q31_t)0x9fa81d5e, (q31_t)0x54413412, (q31_t)0x9fa3fa79, (q31_t)0x543c7914, (q31_t)0x9f9fd7d1, (q31_t)0x5437bde3, (q31_t)0x9f9bb563, + (q31_t)0x5433027d, (q31_t)0x9f979331, (q31_t)0x542e46e4, (q31_t)0x9f93713b, (q31_t)0x54298b17, (q31_t)0x9f8f4f80, (q31_t)0x5424cf16, (q31_t)0x9f8b2e00, + (q31_t)0x542012e1, (q31_t)0x9f870cbc, (q31_t)0x541b5678, (q31_t)0x9f82ebb4, (q31_t)0x541699db, (q31_t)0x9f7ecae7, (q31_t)0x5411dd0a, (q31_t)0x9f7aaa55, + (q31_t)0x540d2005, (q31_t)0x9f7689ff, (q31_t)0x540862cd, (q31_t)0x9f7269e5, (q31_t)0x5403a561, (q31_t)0x9f6e4a06, (q31_t)0x53fee7c1, (q31_t)0x9f6a2a63, + (q31_t)0x53fa29ed, (q31_t)0x9f660afb, (q31_t)0x53f56be5, (q31_t)0x9f61ebcf, (q31_t)0x53f0adaa, (q31_t)0x9f5dccde, (q31_t)0x53ebef3a, (q31_t)0x9f59ae29, + (q31_t)0x53e73097, (q31_t)0x9f558fb0, (q31_t)0x53e271c0, (q31_t)0x9f517173, (q31_t)0x53ddb2b6, (q31_t)0x9f4d5371, (q31_t)0x53d8f378, (q31_t)0x9f4935aa, + (q31_t)0x53d43406, (q31_t)0x9f45181f, (q31_t)0x53cf7460, (q31_t)0x9f40fad0, (q31_t)0x53cab486, (q31_t)0x9f3cddbd, (q31_t)0x53c5f479, (q31_t)0x9f38c0e5, + (q31_t)0x53c13439, (q31_t)0x9f34a449, (q31_t)0x53bc73c4, (q31_t)0x9f3087e9, (q31_t)0x53b7b31c, (q31_t)0x9f2c6bc5, (q31_t)0x53b2f240, (q31_t)0x9f284fdc, + (q31_t)0x53ae3131, (q31_t)0x9f24342f, (q31_t)0x53a96fee, (q31_t)0x9f2018bd, (q31_t)0x53a4ae77, (q31_t)0x9f1bfd88, (q31_t)0x539feccd, (q31_t)0x9f17e28e, + (q31_t)0x539b2af0, (q31_t)0x9f13c7d0, (q31_t)0x539668de, (q31_t)0x9f0fad4e, (q31_t)0x5391a699, (q31_t)0x9f0b9307, (q31_t)0x538ce421, (q31_t)0x9f0778fd, + (q31_t)0x53882175, (q31_t)0x9f035f2e, (q31_t)0x53835e95, (q31_t)0x9eff459b, (q31_t)0x537e9b82, (q31_t)0x9efb2c44, (q31_t)0x5379d83c, (q31_t)0x9ef71328, + (q31_t)0x537514c2, (q31_t)0x9ef2fa49, (q31_t)0x53705114, (q31_t)0x9eeee1a5, (q31_t)0x536b8d33, (q31_t)0x9eeac93e, (q31_t)0x5366c91f, (q31_t)0x9ee6b112, + (q31_t)0x536204d7, (q31_t)0x9ee29922, (q31_t)0x535d405c, (q31_t)0x9ede816e, (q31_t)0x53587bad, (q31_t)0x9eda69f6, (q31_t)0x5353b6cb, (q31_t)0x9ed652ba, + (q31_t)0x534ef1b5, (q31_t)0x9ed23bb9, (q31_t)0x534a2c6c, (q31_t)0x9ece24f5, (q31_t)0x534566f0, (q31_t)0x9eca0e6d, (q31_t)0x5340a140, (q31_t)0x9ec5f820, + (q31_t)0x533bdb5d, (q31_t)0x9ec1e210, (q31_t)0x53371547, (q31_t)0x9ebdcc3b, (q31_t)0x53324efd, (q31_t)0x9eb9b6a3, (q31_t)0x532d8880, (q31_t)0x9eb5a146, + (q31_t)0x5328c1d0, (q31_t)0x9eb18c26, (q31_t)0x5323faec, (q31_t)0x9ead7742, (q31_t)0x531f33d5, (q31_t)0x9ea96299, (q31_t)0x531a6c8b, (q31_t)0x9ea54e2d, + (q31_t)0x5315a50e, (q31_t)0x9ea139fd, (q31_t)0x5310dd5d, (q31_t)0x9e9d2608, (q31_t)0x530c1579, (q31_t)0x9e991250, (q31_t)0x53074d62, (q31_t)0x9e94fed4, + (q31_t)0x53028518, (q31_t)0x9e90eb94, (q31_t)0x52fdbc9a, (q31_t)0x9e8cd890, (q31_t)0x52f8f3e9, (q31_t)0x9e88c5c9, (q31_t)0x52f42b05, (q31_t)0x9e84b33d, + (q31_t)0x52ef61ee, (q31_t)0x9e80a0ee, (q31_t)0x52ea98a4, (q31_t)0x9e7c8eda, (q31_t)0x52e5cf27, (q31_t)0x9e787d03, (q31_t)0x52e10576, (q31_t)0x9e746b68, + (q31_t)0x52dc3b92, (q31_t)0x9e705a09, (q31_t)0x52d7717b, (q31_t)0x9e6c48e7, (q31_t)0x52d2a732, (q31_t)0x9e683800, (q31_t)0x52cddcb5, (q31_t)0x9e642756, + (q31_t)0x52c91204, (q31_t)0x9e6016e8, (q31_t)0x52c44721, (q31_t)0x9e5c06b6, (q31_t)0x52bf7c0b, (q31_t)0x9e57f6c0, (q31_t)0x52bab0c2, (q31_t)0x9e53e707, + (q31_t)0x52b5e546, (q31_t)0x9e4fd78a, (q31_t)0x52b11996, (q31_t)0x9e4bc849, (q31_t)0x52ac4db4, (q31_t)0x9e47b944, (q31_t)0x52a7819f, (q31_t)0x9e43aa7c, + (q31_t)0x52a2b556, (q31_t)0x9e3f9bf0, (q31_t)0x529de8db, (q31_t)0x9e3b8da0, (q31_t)0x52991c2d, (q31_t)0x9e377f8c, (q31_t)0x52944f4c, (q31_t)0x9e3371b5, + (q31_t)0x528f8238, (q31_t)0x9e2f641b, (q31_t)0x528ab4f1, (q31_t)0x9e2b56bc, (q31_t)0x5285e777, (q31_t)0x9e27499a, (q31_t)0x528119ca, (q31_t)0x9e233cb4, + (q31_t)0x527c4bea, (q31_t)0x9e1f300b, (q31_t)0x52777dd7, (q31_t)0x9e1b239e, (q31_t)0x5272af92, (q31_t)0x9e17176d, (q31_t)0x526de11a, (q31_t)0x9e130b79, + (q31_t)0x5269126e, (q31_t)0x9e0effc1, (q31_t)0x52644390, (q31_t)0x9e0af446, (q31_t)0x525f7480, (q31_t)0x9e06e907, (q31_t)0x525aa53c, (q31_t)0x9e02de04, + (q31_t)0x5255d5c5, (q31_t)0x9dfed33e, (q31_t)0x5251061c, (q31_t)0x9dfac8b4, (q31_t)0x524c3640, (q31_t)0x9df6be67, (q31_t)0x52476631, (q31_t)0x9df2b456, + (q31_t)0x524295f0, (q31_t)0x9deeaa82, (q31_t)0x523dc57b, (q31_t)0x9deaa0ea, (q31_t)0x5238f4d4, (q31_t)0x9de6978f, (q31_t)0x523423fb, (q31_t)0x9de28e70, + (q31_t)0x522f52ee, (q31_t)0x9dde858e, (q31_t)0x522a81af, (q31_t)0x9dda7ce9, (q31_t)0x5225b03d, (q31_t)0x9dd6747f, (q31_t)0x5220de99, (q31_t)0x9dd26c53, + (q31_t)0x521c0cc2, (q31_t)0x9dce6463, (q31_t)0x52173ab8, (q31_t)0x9dca5caf, (q31_t)0x5212687b, (q31_t)0x9dc65539, (q31_t)0x520d960c, (q31_t)0x9dc24dfe, + (q31_t)0x5208c36a, (q31_t)0x9dbe4701, (q31_t)0x5203f096, (q31_t)0x9dba4040, (q31_t)0x51ff1d8f, (q31_t)0x9db639bb, (q31_t)0x51fa4a56, (q31_t)0x9db23373, + (q31_t)0x51f576ea, (q31_t)0x9dae2d68, (q31_t)0x51f0a34b, (q31_t)0x9daa279a, (q31_t)0x51ebcf7a, (q31_t)0x9da62208, (q31_t)0x51e6fb76, (q31_t)0x9da21cb2, + (q31_t)0x51e22740, (q31_t)0x9d9e179a, (q31_t)0x51dd52d7, (q31_t)0x9d9a12be, (q31_t)0x51d87e3c, (q31_t)0x9d960e1f, (q31_t)0x51d3a96f, (q31_t)0x9d9209bd, + (q31_t)0x51ced46e, (q31_t)0x9d8e0597, (q31_t)0x51c9ff3c, (q31_t)0x9d8a01ae, (q31_t)0x51c529d7, (q31_t)0x9d85fe02, (q31_t)0x51c0543f, (q31_t)0x9d81fa92, + (q31_t)0x51bb7e75, (q31_t)0x9d7df75f, (q31_t)0x51b6a879, (q31_t)0x9d79f469, (q31_t)0x51b1d24a, (q31_t)0x9d75f1b0, (q31_t)0x51acfbe9, (q31_t)0x9d71ef34, + (q31_t)0x51a82555, (q31_t)0x9d6decf4, (q31_t)0x51a34e8f, (q31_t)0x9d69eaf1, (q31_t)0x519e7797, (q31_t)0x9d65e92b, (q31_t)0x5199a06d, (q31_t)0x9d61e7a2, + (q31_t)0x5194c910, (q31_t)0x9d5de656, (q31_t)0x518ff180, (q31_t)0x9d59e546, (q31_t)0x518b19bf, (q31_t)0x9d55e473, (q31_t)0x518641cb, (q31_t)0x9d51e3dd, + (q31_t)0x518169a5, (q31_t)0x9d4de385, (q31_t)0x517c914c, (q31_t)0x9d49e368, (q31_t)0x5177b8c2, (q31_t)0x9d45e389, (q31_t)0x5172e005, (q31_t)0x9d41e3e7, + (q31_t)0x516e0715, (q31_t)0x9d3de482, (q31_t)0x51692df4, (q31_t)0x9d39e559, (q31_t)0x516454a0, (q31_t)0x9d35e66e, (q31_t)0x515f7b1a, (q31_t)0x9d31e7bf, + (q31_t)0x515aa162, (q31_t)0x9d2de94d, (q31_t)0x5155c778, (q31_t)0x9d29eb19, (q31_t)0x5150ed5c, (q31_t)0x9d25ed21, (q31_t)0x514c130d, (q31_t)0x9d21ef66, + (q31_t)0x5147388c, (q31_t)0x9d1df1e9, (q31_t)0x51425dd9, (q31_t)0x9d19f4a8, (q31_t)0x513d82f4, (q31_t)0x9d15f7a4, (q31_t)0x5138a7dd, (q31_t)0x9d11fadd, + (q31_t)0x5133cc94, (q31_t)0x9d0dfe54, (q31_t)0x512ef119, (q31_t)0x9d0a0207, (q31_t)0x512a156b, (q31_t)0x9d0605f7, (q31_t)0x5125398c, (q31_t)0x9d020a25, + (q31_t)0x51205d7b, (q31_t)0x9cfe0e8f, (q31_t)0x511b8137, (q31_t)0x9cfa1337, (q31_t)0x5116a4c1, (q31_t)0x9cf6181c, (q31_t)0x5111c81a, (q31_t)0x9cf21d3d, + (q31_t)0x510ceb40, (q31_t)0x9cee229c, (q31_t)0x51080e35, (q31_t)0x9cea2838, (q31_t)0x510330f7, (q31_t)0x9ce62e11, (q31_t)0x50fe5388, (q31_t)0x9ce23427, + (q31_t)0x50f975e6, (q31_t)0x9cde3a7b, (q31_t)0x50f49813, (q31_t)0x9cda410b, (q31_t)0x50efba0d, (q31_t)0x9cd647d9, (q31_t)0x50eadbd6, (q31_t)0x9cd24ee4, + (q31_t)0x50e5fd6d, (q31_t)0x9cce562c, (q31_t)0x50e11ed2, (q31_t)0x9cca5db1, (q31_t)0x50dc4005, (q31_t)0x9cc66573, (q31_t)0x50d76106, (q31_t)0x9cc26d73, + (q31_t)0x50d281d5, (q31_t)0x9cbe75b0, (q31_t)0x50cda272, (q31_t)0x9cba7e2a, (q31_t)0x50c8c2de, (q31_t)0x9cb686e1, (q31_t)0x50c3e317, (q31_t)0x9cb28fd5, + (q31_t)0x50bf031f, (q31_t)0x9cae9907, (q31_t)0x50ba22f5, (q31_t)0x9caaa276, (q31_t)0x50b5429a, (q31_t)0x9ca6ac23, (q31_t)0x50b0620c, (q31_t)0x9ca2b60c, + (q31_t)0x50ab814d, (q31_t)0x9c9ec033, (q31_t)0x50a6a05c, (q31_t)0x9c9aca97, (q31_t)0x50a1bf39, (q31_t)0x9c96d539, (q31_t)0x509cdde4, (q31_t)0x9c92e017, + (q31_t)0x5097fc5e, (q31_t)0x9c8eeb34, (q31_t)0x50931aa6, (q31_t)0x9c8af68d, (q31_t)0x508e38bd, (q31_t)0x9c870224, (q31_t)0x508956a1, (q31_t)0x9c830df8, + (q31_t)0x50847454, (q31_t)0x9c7f1a0a, (q31_t)0x507f91d5, (q31_t)0x9c7b2659, (q31_t)0x507aaf25, (q31_t)0x9c7732e5, (q31_t)0x5075cc43, (q31_t)0x9c733faf, + (q31_t)0x5070e92f, (q31_t)0x9c6f4cb6, (q31_t)0x506c05ea, (q31_t)0x9c6b59fa, (q31_t)0x50672273, (q31_t)0x9c67677c, (q31_t)0x50623ecb, (q31_t)0x9c63753c, + (q31_t)0x505d5af1, (q31_t)0x9c5f8339, (q31_t)0x505876e5, (q31_t)0x9c5b9173, (q31_t)0x505392a8, (q31_t)0x9c579feb, (q31_t)0x504eae39, (q31_t)0x9c53aea0, + (q31_t)0x5049c999, (q31_t)0x9c4fbd93, (q31_t)0x5044e4c7, (q31_t)0x9c4bccc3, (q31_t)0x503fffc4, (q31_t)0x9c47dc31, (q31_t)0x503b1a8f, (q31_t)0x9c43ebdc, + (q31_t)0x50363529, (q31_t)0x9c3ffbc5, (q31_t)0x50314f91, (q31_t)0x9c3c0beb, (q31_t)0x502c69c8, (q31_t)0x9c381c4f, (q31_t)0x502783cd, (q31_t)0x9c342cf0, + (q31_t)0x50229da1, (q31_t)0x9c303dcf, (q31_t)0x501db743, (q31_t)0x9c2c4eec, (q31_t)0x5018d0b4, (q31_t)0x9c286046, (q31_t)0x5013e9f4, (q31_t)0x9c2471de, + (q31_t)0x500f0302, (q31_t)0x9c2083b3, (q31_t)0x500a1bdf, (q31_t)0x9c1c95c6, (q31_t)0x5005348a, (q31_t)0x9c18a816, (q31_t)0x50004d04, (q31_t)0x9c14baa4, + (q31_t)0x4ffb654d, (q31_t)0x9c10cd70, (q31_t)0x4ff67d64, (q31_t)0x9c0ce07a, (q31_t)0x4ff1954b, (q31_t)0x9c08f3c1, (q31_t)0x4fecacff, (q31_t)0x9c050745, + (q31_t)0x4fe7c483, (q31_t)0x9c011b08, (q31_t)0x4fe2dbd5, (q31_t)0x9bfd2f08, (q31_t)0x4fddf2f6, (q31_t)0x9bf94346, (q31_t)0x4fd909e5, (q31_t)0x9bf557c1, + (q31_t)0x4fd420a4, (q31_t)0x9bf16c7a, (q31_t)0x4fcf3731, (q31_t)0x9bed8171, (q31_t)0x4fca4d8d, (q31_t)0x9be996a6, (q31_t)0x4fc563b7, (q31_t)0x9be5ac18, + (q31_t)0x4fc079b1, (q31_t)0x9be1c1c8, (q31_t)0x4fbb8f79, (q31_t)0x9bddd7b6, (q31_t)0x4fb6a510, (q31_t)0x9bd9ede2, (q31_t)0x4fb1ba76, (q31_t)0x9bd6044b, + (q31_t)0x4faccfab, (q31_t)0x9bd21af3, (q31_t)0x4fa7e4af, (q31_t)0x9bce31d8, (q31_t)0x4fa2f981, (q31_t)0x9bca48fa, (q31_t)0x4f9e0e22, (q31_t)0x9bc6605b, + (q31_t)0x4f992293, (q31_t)0x9bc277fa, (q31_t)0x4f9436d2, (q31_t)0x9bbe8fd6, (q31_t)0x4f8f4ae0, (q31_t)0x9bbaa7f0, (q31_t)0x4f8a5ebd, (q31_t)0x9bb6c048, + (q31_t)0x4f857269, (q31_t)0x9bb2d8de, (q31_t)0x4f8085e4, (q31_t)0x9baef1b2, (q31_t)0x4f7b992d, (q31_t)0x9bab0ac3, (q31_t)0x4f76ac46, (q31_t)0x9ba72413, + (q31_t)0x4f71bf2e, (q31_t)0x9ba33da0, (q31_t)0x4f6cd1e5, (q31_t)0x9b9f576b, (q31_t)0x4f67e46a, (q31_t)0x9b9b7174, (q31_t)0x4f62f6bf, (q31_t)0x9b978bbc, + (q31_t)0x4f5e08e3, (q31_t)0x9b93a641, (q31_t)0x4f591ad6, (q31_t)0x9b8fc104, (q31_t)0x4f542c98, (q31_t)0x9b8bdc05, (q31_t)0x4f4f3e29, (q31_t)0x9b87f744, + (q31_t)0x4f4a4f89, (q31_t)0x9b8412c1, (q31_t)0x4f4560b8, (q31_t)0x9b802e7b, (q31_t)0x4f4071b6, (q31_t)0x9b7c4a74, (q31_t)0x4f3b8284, (q31_t)0x9b7866ab, + (q31_t)0x4f369320, (q31_t)0x9b748320, (q31_t)0x4f31a38c, (q31_t)0x9b709fd3, (q31_t)0x4f2cb3c7, (q31_t)0x9b6cbcc4, (q31_t)0x4f27c3d1, (q31_t)0x9b68d9f3, + (q31_t)0x4f22d3aa, (q31_t)0x9b64f760, (q31_t)0x4f1de352, (q31_t)0x9b61150b, (q31_t)0x4f18f2c9, (q31_t)0x9b5d32f4, (q31_t)0x4f140210, (q31_t)0x9b59511c, + (q31_t)0x4f0f1126, (q31_t)0x9b556f81, (q31_t)0x4f0a200b, (q31_t)0x9b518e24, (q31_t)0x4f052ec0, (q31_t)0x9b4dad06, (q31_t)0x4f003d43, (q31_t)0x9b49cc26, + (q31_t)0x4efb4b96, (q31_t)0x9b45eb83, (q31_t)0x4ef659b8, (q31_t)0x9b420b1f, (q31_t)0x4ef167aa, (q31_t)0x9b3e2af9, (q31_t)0x4eec756b, (q31_t)0x9b3a4b11, + (q31_t)0x4ee782fb, (q31_t)0x9b366b68, (q31_t)0x4ee2905a, (q31_t)0x9b328bfc, (q31_t)0x4edd9d89, (q31_t)0x9b2eaccf, (q31_t)0x4ed8aa87, (q31_t)0x9b2acde0, + (q31_t)0x4ed3b755, (q31_t)0x9b26ef2f, (q31_t)0x4ecec3f2, (q31_t)0x9b2310bc, (q31_t)0x4ec9d05e, (q31_t)0x9b1f3288, (q31_t)0x4ec4dc99, (q31_t)0x9b1b5492, + (q31_t)0x4ebfe8a5, (q31_t)0x9b1776da, (q31_t)0x4ebaf47f, (q31_t)0x9b139960, (q31_t)0x4eb60029, (q31_t)0x9b0fbc24, (q31_t)0x4eb10ba2, (q31_t)0x9b0bdf27, + (q31_t)0x4eac16eb, (q31_t)0x9b080268, (q31_t)0x4ea72203, (q31_t)0x9b0425e8, (q31_t)0x4ea22ceb, (q31_t)0x9b0049a5, (q31_t)0x4e9d37a3, (q31_t)0x9afc6da1, + (q31_t)0x4e984229, (q31_t)0x9af891db, (q31_t)0x4e934c80, (q31_t)0x9af4b654, (q31_t)0x4e8e56a5, (q31_t)0x9af0db0b, (q31_t)0x4e89609b, (q31_t)0x9aed0000, + (q31_t)0x4e846a60, (q31_t)0x9ae92533, (q31_t)0x4e7f73f4, (q31_t)0x9ae54aa5, (q31_t)0x4e7a7d58, (q31_t)0x9ae17056, (q31_t)0x4e75868c, (q31_t)0x9add9644, + (q31_t)0x4e708f8f, (q31_t)0x9ad9bc71, (q31_t)0x4e6b9862, (q31_t)0x9ad5e2dd, (q31_t)0x4e66a105, (q31_t)0x9ad20987, (q31_t)0x4e61a977, (q31_t)0x9ace306f, + (q31_t)0x4e5cb1b9, (q31_t)0x9aca5795, (q31_t)0x4e57b9ca, (q31_t)0x9ac67efb, (q31_t)0x4e52c1ab, (q31_t)0x9ac2a69e, (q31_t)0x4e4dc95c, (q31_t)0x9abece80, + (q31_t)0x4e48d0dd, (q31_t)0x9abaf6a1, (q31_t)0x4e43d82d, (q31_t)0x9ab71eff, (q31_t)0x4e3edf4d, (q31_t)0x9ab3479d, (q31_t)0x4e39e63d, (q31_t)0x9aaf7079, + (q31_t)0x4e34ecfc, (q31_t)0x9aab9993, (q31_t)0x4e2ff38b, (q31_t)0x9aa7c2ec, (q31_t)0x4e2af9ea, (q31_t)0x9aa3ec83, (q31_t)0x4e260019, (q31_t)0x9aa01659, + (q31_t)0x4e210617, (q31_t)0x9a9c406e, (q31_t)0x4e1c0be6, (q31_t)0x9a986ac1, (q31_t)0x4e171184, (q31_t)0x9a949552, (q31_t)0x4e1216f2, (q31_t)0x9a90c022, + (q31_t)0x4e0d1c30, (q31_t)0x9a8ceb31, (q31_t)0x4e08213e, (q31_t)0x9a89167e, (q31_t)0x4e03261b, (q31_t)0x9a85420a, (q31_t)0x4dfe2ac9, (q31_t)0x9a816dd5, + (q31_t)0x4df92f46, (q31_t)0x9a7d99de, (q31_t)0x4df43393, (q31_t)0x9a79c625, (q31_t)0x4def37b0, (q31_t)0x9a75f2ac, (q31_t)0x4dea3b9d, (q31_t)0x9a721f71, + (q31_t)0x4de53f5a, (q31_t)0x9a6e4c74, (q31_t)0x4de042e7, (q31_t)0x9a6a79b6, (q31_t)0x4ddb4644, (q31_t)0x9a66a737, (q31_t)0x4dd64971, (q31_t)0x9a62d4f7, + (q31_t)0x4dd14c6e, (q31_t)0x9a5f02f5, (q31_t)0x4dcc4f3b, (q31_t)0x9a5b3132, (q31_t)0x4dc751d8, (q31_t)0x9a575fae, (q31_t)0x4dc25445, (q31_t)0x9a538e68, + (q31_t)0x4dbd5682, (q31_t)0x9a4fbd61, (q31_t)0x4db8588f, (q31_t)0x9a4bec99, (q31_t)0x4db35a6c, (q31_t)0x9a481c0f, (q31_t)0x4dae5c19, (q31_t)0x9a444bc5, + (q31_t)0x4da95d96, (q31_t)0x9a407bb9, (q31_t)0x4da45ee3, (q31_t)0x9a3cabeb, (q31_t)0x4d9f6001, (q31_t)0x9a38dc5d, (q31_t)0x4d9a60ee, (q31_t)0x9a350d0d, + (q31_t)0x4d9561ac, (q31_t)0x9a313dfc, (q31_t)0x4d90623a, (q31_t)0x9a2d6f2a, (q31_t)0x4d8b6298, (q31_t)0x9a29a097, (q31_t)0x4d8662c6, (q31_t)0x9a25d243, + (q31_t)0x4d8162c4, (q31_t)0x9a22042d, (q31_t)0x4d7c6293, (q31_t)0x9a1e3656, (q31_t)0x4d776231, (q31_t)0x9a1a68be, (q31_t)0x4d7261a0, (q31_t)0x9a169b65, + (q31_t)0x4d6d60df, (q31_t)0x9a12ce4b, (q31_t)0x4d685fef, (q31_t)0x9a0f016f, (q31_t)0x4d635ece, (q31_t)0x9a0b34d3, (q31_t)0x4d5e5d7e, (q31_t)0x9a076875, + (q31_t)0x4d595bfe, (q31_t)0x9a039c57, (q31_t)0x4d545a4f, (q31_t)0x99ffd077, (q31_t)0x4d4f5870, (q31_t)0x99fc04d6, (q31_t)0x4d4a5661, (q31_t)0x99f83974, + (q31_t)0x4d455422, (q31_t)0x99f46e51, (q31_t)0x4d4051b4, (q31_t)0x99f0a36d, (q31_t)0x4d3b4f16, (q31_t)0x99ecd8c8, (q31_t)0x4d364c48, (q31_t)0x99e90e62, + (q31_t)0x4d31494b, (q31_t)0x99e5443b, (q31_t)0x4d2c461e, (q31_t)0x99e17a53, (q31_t)0x4d2742c2, (q31_t)0x99ddb0aa, (q31_t)0x4d223f36, (q31_t)0x99d9e73f, + (q31_t)0x4d1d3b7a, (q31_t)0x99d61e14, (q31_t)0x4d18378f, (q31_t)0x99d25528, (q31_t)0x4d133374, (q31_t)0x99ce8c7b, (q31_t)0x4d0e2f2a, (q31_t)0x99cac40d, + (q31_t)0x4d092ab0, (q31_t)0x99c6fbde, (q31_t)0x4d042607, (q31_t)0x99c333ee, (q31_t)0x4cff212e, (q31_t)0x99bf6c3d, (q31_t)0x4cfa1c26, (q31_t)0x99bba4cb, + (q31_t)0x4cf516ee, (q31_t)0x99b7dd99, (q31_t)0x4cf01187, (q31_t)0x99b416a5, (q31_t)0x4ceb0bf0, (q31_t)0x99b04ff0, (q31_t)0x4ce6062a, (q31_t)0x99ac897b, + (q31_t)0x4ce10034, (q31_t)0x99a8c345, (q31_t)0x4cdbfa0f, (q31_t)0x99a4fd4d, (q31_t)0x4cd6f3bb, (q31_t)0x99a13795, (q31_t)0x4cd1ed37, (q31_t)0x999d721c, + (q31_t)0x4ccce684, (q31_t)0x9999ace3, (q31_t)0x4cc7dfa1, (q31_t)0x9995e7e8, (q31_t)0x4cc2d88f, (q31_t)0x9992232d, (q31_t)0x4cbdd14e, (q31_t)0x998e5eb1, + (q31_t)0x4cb8c9dd, (q31_t)0x998a9a74, (q31_t)0x4cb3c23d, (q31_t)0x9986d676, (q31_t)0x4caeba6e, (q31_t)0x998312b7, (q31_t)0x4ca9b26f, (q31_t)0x997f4f38, + (q31_t)0x4ca4aa41, (q31_t)0x997b8bf8, (q31_t)0x4c9fa1e4, (q31_t)0x9977c8f7, (q31_t)0x4c9a9958, (q31_t)0x99740635, (q31_t)0x4c95909c, (q31_t)0x997043b2, + (q31_t)0x4c9087b1, (q31_t)0x996c816f, (q31_t)0x4c8b7e97, (q31_t)0x9968bf6b, (q31_t)0x4c86754e, (q31_t)0x9964fda7, (q31_t)0x4c816bd5, (q31_t)0x99613c22, + (q31_t)0x4c7c622d, (q31_t)0x995d7adc, (q31_t)0x4c775856, (q31_t)0x9959b9d5, (q31_t)0x4c724e50, (q31_t)0x9955f90d, (q31_t)0x4c6d441b, (q31_t)0x99523885, + (q31_t)0x4c6839b7, (q31_t)0x994e783d, (q31_t)0x4c632f23, (q31_t)0x994ab833, (q31_t)0x4c5e2460, (q31_t)0x9946f869, (q31_t)0x4c59196f, (q31_t)0x994338df, + (q31_t)0x4c540e4e, (q31_t)0x993f7993, (q31_t)0x4c4f02fe, (q31_t)0x993bba87, (q31_t)0x4c49f77f, (q31_t)0x9937fbbb, (q31_t)0x4c44ebd1, (q31_t)0x99343d2e, + (q31_t)0x4c3fdff4, (q31_t)0x99307ee0, (q31_t)0x4c3ad3e7, (q31_t)0x992cc0d2, (q31_t)0x4c35c7ac, (q31_t)0x99290303, (q31_t)0x4c30bb42, (q31_t)0x99254574, + (q31_t)0x4c2baea9, (q31_t)0x99218824, (q31_t)0x4c26a1e1, (q31_t)0x991dcb13, (q31_t)0x4c2194e9, (q31_t)0x991a0e42, (q31_t)0x4c1c87c3, (q31_t)0x991651b1, + (q31_t)0x4c177a6e, (q31_t)0x9912955f, (q31_t)0x4c126cea, (q31_t)0x990ed94c, (q31_t)0x4c0d5f37, (q31_t)0x990b1d79, (q31_t)0x4c085156, (q31_t)0x990761e5, + (q31_t)0x4c034345, (q31_t)0x9903a691, (q31_t)0x4bfe3505, (q31_t)0x98ffeb7d, (q31_t)0x4bf92697, (q31_t)0x98fc30a8, (q31_t)0x4bf417f9, (q31_t)0x98f87612, + (q31_t)0x4bef092d, (q31_t)0x98f4bbbc, (q31_t)0x4be9fa32, (q31_t)0x98f101a6, (q31_t)0x4be4eb08, (q31_t)0x98ed47cf, (q31_t)0x4bdfdbaf, (q31_t)0x98e98e38, + (q31_t)0x4bdacc28, (q31_t)0x98e5d4e0, (q31_t)0x4bd5bc72, (q31_t)0x98e21bc8, (q31_t)0x4bd0ac8d, (q31_t)0x98de62f0, (q31_t)0x4bcb9c79, (q31_t)0x98daaa57, + (q31_t)0x4bc68c36, (q31_t)0x98d6f1fe, (q31_t)0x4bc17bc5, (q31_t)0x98d339e4, (q31_t)0x4bbc6b25, (q31_t)0x98cf820b, (q31_t)0x4bb75a56, (q31_t)0x98cbca70, + (q31_t)0x4bb24958, (q31_t)0x98c81316, (q31_t)0x4bad382c, (q31_t)0x98c45bfb, (q31_t)0x4ba826d1, (q31_t)0x98c0a520, (q31_t)0x4ba31548, (q31_t)0x98bcee84, + (q31_t)0x4b9e0390, (q31_t)0x98b93828, (q31_t)0x4b98f1a9, (q31_t)0x98b5820c, (q31_t)0x4b93df93, (q31_t)0x98b1cc30, (q31_t)0x4b8ecd4f, (q31_t)0x98ae1693, + (q31_t)0x4b89badd, (q31_t)0x98aa6136, (q31_t)0x4b84a83b, (q31_t)0x98a6ac19, (q31_t)0x4b7f956b, (q31_t)0x98a2f73c, (q31_t)0x4b7a826d, (q31_t)0x989f429e, + (q31_t)0x4b756f40, (q31_t)0x989b8e40, (q31_t)0x4b705be4, (q31_t)0x9897da22, (q31_t)0x4b6b485a, (q31_t)0x98942643, (q31_t)0x4b6634a2, (q31_t)0x989072a5, + (q31_t)0x4b6120bb, (q31_t)0x988cbf46, (q31_t)0x4b5c0ca5, (q31_t)0x98890c27, (q31_t)0x4b56f861, (q31_t)0x98855948, (q31_t)0x4b51e3ee, (q31_t)0x9881a6a9, + (q31_t)0x4b4ccf4d, (q31_t)0x987df449, (q31_t)0x4b47ba7e, (q31_t)0x987a422a, (q31_t)0x4b42a580, (q31_t)0x9876904a, (q31_t)0x4b3d9053, (q31_t)0x9872deaa, + (q31_t)0x4b387af9, (q31_t)0x986f2d4a, (q31_t)0x4b336570, (q31_t)0x986b7c2a, (q31_t)0x4b2e4fb8, (q31_t)0x9867cb4a, (q31_t)0x4b2939d2, (q31_t)0x98641aa9, + (q31_t)0x4b2423be, (q31_t)0x98606a49, (q31_t)0x4b1f0d7b, (q31_t)0x985cba28, (q31_t)0x4b19f70a, (q31_t)0x98590a48, (q31_t)0x4b14e06b, (q31_t)0x98555aa7, + (q31_t)0x4b0fc99d, (q31_t)0x9851ab46, (q31_t)0x4b0ab2a1, (q31_t)0x984dfc26, (q31_t)0x4b059b77, (q31_t)0x984a4d45, (q31_t)0x4b00841f, (q31_t)0x98469ea4, + (q31_t)0x4afb6c98, (q31_t)0x9842f043, (q31_t)0x4af654e3, (q31_t)0x983f4223, (q31_t)0x4af13d00, (q31_t)0x983b9442, (q31_t)0x4aec24ee, (q31_t)0x9837e6a1, + (q31_t)0x4ae70caf, (q31_t)0x98343940, (q31_t)0x4ae1f441, (q31_t)0x98308c1f, (q31_t)0x4adcdba5, (q31_t)0x982cdf3f, (q31_t)0x4ad7c2da, (q31_t)0x9829329e, + (q31_t)0x4ad2a9e2, (q31_t)0x9825863d, (q31_t)0x4acd90bb, (q31_t)0x9821da1d, (q31_t)0x4ac87767, (q31_t)0x981e2e3c, (q31_t)0x4ac35de4, (q31_t)0x981a829c, + (q31_t)0x4abe4433, (q31_t)0x9816d73b, (q31_t)0x4ab92a54, (q31_t)0x98132c1b, (q31_t)0x4ab41046, (q31_t)0x980f813b, (q31_t)0x4aaef60b, (q31_t)0x980bd69b, + (q31_t)0x4aa9dba2, (q31_t)0x98082c3b, (q31_t)0x4aa4c10b, (q31_t)0x9804821b, (q31_t)0x4a9fa645, (q31_t)0x9800d83c, (q31_t)0x4a9a8b52, (q31_t)0x97fd2e9c, + (q31_t)0x4a957030, (q31_t)0x97f9853d, (q31_t)0x4a9054e1, (q31_t)0x97f5dc1e, (q31_t)0x4a8b3963, (q31_t)0x97f2333f, (q31_t)0x4a861db8, (q31_t)0x97ee8aa0, + (q31_t)0x4a8101de, (q31_t)0x97eae242, (q31_t)0x4a7be5d7, (q31_t)0x97e73a23, (q31_t)0x4a76c9a2, (q31_t)0x97e39245, (q31_t)0x4a71ad3e, (q31_t)0x97dfeaa7, + (q31_t)0x4a6c90ad, (q31_t)0x97dc4349, (q31_t)0x4a6773ee, (q31_t)0x97d89c2c, (q31_t)0x4a625701, (q31_t)0x97d4f54f, (q31_t)0x4a5d39e6, (q31_t)0x97d14eb2, + (q31_t)0x4a581c9e, (q31_t)0x97cda855, (q31_t)0x4a52ff27, (q31_t)0x97ca0239, (q31_t)0x4a4de182, (q31_t)0x97c65c5c, (q31_t)0x4a48c3b0, (q31_t)0x97c2b6c1, + (q31_t)0x4a43a5b0, (q31_t)0x97bf1165, (q31_t)0x4a3e8782, (q31_t)0x97bb6c4a, (q31_t)0x4a396926, (q31_t)0x97b7c76f, (q31_t)0x4a344a9d, (q31_t)0x97b422d4, + (q31_t)0x4a2f2be6, (q31_t)0x97b07e7a, (q31_t)0x4a2a0d01, (q31_t)0x97acda60, (q31_t)0x4a24edee, (q31_t)0x97a93687, (q31_t)0x4a1fcead, (q31_t)0x97a592ed, + (q31_t)0x4a1aaf3f, (q31_t)0x97a1ef94, (q31_t)0x4a158fa3, (q31_t)0x979e4c7c, (q31_t)0x4a106fda, (q31_t)0x979aa9a4, (q31_t)0x4a0b4fe2, (q31_t)0x9797070c, + (q31_t)0x4a062fbd, (q31_t)0x979364b5, (q31_t)0x4a010f6b, (q31_t)0x978fc29e, (q31_t)0x49fbeeea, (q31_t)0x978c20c8, (q31_t)0x49f6ce3c, (q31_t)0x97887f32, + (q31_t)0x49f1ad61, (q31_t)0x9784dddc, (q31_t)0x49ec8c57, (q31_t)0x97813cc7, (q31_t)0x49e76b21, (q31_t)0x977d9bf2, (q31_t)0x49e249bc, (q31_t)0x9779fb5e, + (q31_t)0x49dd282a, (q31_t)0x97765b0a, (q31_t)0x49d8066b, (q31_t)0x9772baf7, (q31_t)0x49d2e47e, (q31_t)0x976f1b24, (q31_t)0x49cdc263, (q31_t)0x976b7b92, + (q31_t)0x49c8a01b, (q31_t)0x9767dc41, (q31_t)0x49c37da5, (q31_t)0x97643d2f, (q31_t)0x49be5b02, (q31_t)0x97609e5f, (q31_t)0x49b93832, (q31_t)0x975cffcf, + (q31_t)0x49b41533, (q31_t)0x9759617f, (q31_t)0x49aef208, (q31_t)0x9755c370, (q31_t)0x49a9ceaf, (q31_t)0x975225a1, (q31_t)0x49a4ab28, (q31_t)0x974e8813, + (q31_t)0x499f8774, (q31_t)0x974aeac6, (q31_t)0x499a6393, (q31_t)0x97474db9, (q31_t)0x49953f84, (q31_t)0x9743b0ed, (q31_t)0x49901b48, (q31_t)0x97401462, + (q31_t)0x498af6df, (q31_t)0x973c7817, (q31_t)0x4985d248, (q31_t)0x9738dc0d, (q31_t)0x4980ad84, (q31_t)0x97354043, (q31_t)0x497b8892, (q31_t)0x9731a4ba, + (q31_t)0x49766373, (q31_t)0x972e0971, (q31_t)0x49713e27, (q31_t)0x972a6e6a, (q31_t)0x496c18ae, (q31_t)0x9726d3a3, (q31_t)0x4966f307, (q31_t)0x9723391c, + (q31_t)0x4961cd33, (q31_t)0x971f9ed7, (q31_t)0x495ca732, (q31_t)0x971c04d2, (q31_t)0x49578103, (q31_t)0x97186b0d, (q31_t)0x49525aa7, (q31_t)0x9714d18a, + (q31_t)0x494d341e, (q31_t)0x97113847, (q31_t)0x49480d68, (q31_t)0x970d9f45, (q31_t)0x4942e684, (q31_t)0x970a0683, (q31_t)0x493dbf74, (q31_t)0x97066e03, + (q31_t)0x49389836, (q31_t)0x9702d5c3, (q31_t)0x493370cb, (q31_t)0x96ff3dc4, (q31_t)0x492e4933, (q31_t)0x96fba605, (q31_t)0x4929216e, (q31_t)0x96f80e88, + (q31_t)0x4923f97b, (q31_t)0x96f4774b, (q31_t)0x491ed15c, (q31_t)0x96f0e04f, (q31_t)0x4919a90f, (q31_t)0x96ed4994, (q31_t)0x49148095, (q31_t)0x96e9b319, + (q31_t)0x490f57ee, (q31_t)0x96e61ce0, (q31_t)0x490a2f1b, (q31_t)0x96e286e7, (q31_t)0x4905061a, (q31_t)0x96def12f, (q31_t)0x48ffdcec, (q31_t)0x96db5bb8, + (q31_t)0x48fab391, (q31_t)0x96d7c682, (q31_t)0x48f58a09, (q31_t)0x96d4318d, (q31_t)0x48f06054, (q31_t)0x96d09cd8, (q31_t)0x48eb3672, (q31_t)0x96cd0865, + (q31_t)0x48e60c62, (q31_t)0x96c97432, (q31_t)0x48e0e227, (q31_t)0x96c5e040, (q31_t)0x48dbb7be, (q31_t)0x96c24c8f, (q31_t)0x48d68d28, (q31_t)0x96beb91f, + (q31_t)0x48d16265, (q31_t)0x96bb25f0, (q31_t)0x48cc3775, (q31_t)0x96b79302, (q31_t)0x48c70c59, (q31_t)0x96b40055, (q31_t)0x48c1e10f, (q31_t)0x96b06de9, + (q31_t)0x48bcb599, (q31_t)0x96acdbbe, (q31_t)0x48b789f5, (q31_t)0x96a949d3, (q31_t)0x48b25e25, (q31_t)0x96a5b82a, (q31_t)0x48ad3228, (q31_t)0x96a226c2, + (q31_t)0x48a805ff, (q31_t)0x969e959b, (q31_t)0x48a2d9a8, (q31_t)0x969b04b4, (q31_t)0x489dad25, (q31_t)0x9697740f, (q31_t)0x48988074, (q31_t)0x9693e3ab, + (q31_t)0x48935397, (q31_t)0x96905388, (q31_t)0x488e268e, (q31_t)0x968cc3a5, (q31_t)0x4888f957, (q31_t)0x96893404, (q31_t)0x4883cbf4, (q31_t)0x9685a4a4, + (q31_t)0x487e9e64, (q31_t)0x96821585, (q31_t)0x487970a7, (q31_t)0x967e86a7, (q31_t)0x487442be, (q31_t)0x967af80a, (q31_t)0x486f14a8, (q31_t)0x967769af, + (q31_t)0x4869e665, (q31_t)0x9673db94, (q31_t)0x4864b7f5, (q31_t)0x96704dba, (q31_t)0x485f8959, (q31_t)0x966cc022, (q31_t)0x485a5a90, (q31_t)0x966932cb, + (q31_t)0x48552b9b, (q31_t)0x9665a5b4, (q31_t)0x484ffc79, (q31_t)0x966218df, (q31_t)0x484acd2a, (q31_t)0x965e8c4b, (q31_t)0x48459daf, (q31_t)0x965afff9, + (q31_t)0x48406e08, (q31_t)0x965773e7, (q31_t)0x483b3e33, (q31_t)0x9653e817, (q31_t)0x48360e32, (q31_t)0x96505c88, (q31_t)0x4830de05, (q31_t)0x964cd139, + (q31_t)0x482badab, (q31_t)0x9649462d, (q31_t)0x48267d24, (q31_t)0x9645bb61, (q31_t)0x48214c71, (q31_t)0x964230d7, (q31_t)0x481c1b92, (q31_t)0x963ea68d, + (q31_t)0x4816ea86, (q31_t)0x963b1c86, (q31_t)0x4811b94d, (q31_t)0x963792bf, (q31_t)0x480c87e8, (q31_t)0x96340939, (q31_t)0x48075657, (q31_t)0x96307ff5, + (q31_t)0x48022499, (q31_t)0x962cf6f2, (q31_t)0x47fcf2af, (q31_t)0x96296e31, (q31_t)0x47f7c099, (q31_t)0x9625e5b0, (q31_t)0x47f28e56, (q31_t)0x96225d71, + (q31_t)0x47ed5be6, (q31_t)0x961ed574, (q31_t)0x47e8294a, (q31_t)0x961b4db7, (q31_t)0x47e2f682, (q31_t)0x9617c63c, (q31_t)0x47ddc38e, (q31_t)0x96143f02, + (q31_t)0x47d8906d, (q31_t)0x9610b80a, (q31_t)0x47d35d20, (q31_t)0x960d3153, (q31_t)0x47ce29a7, (q31_t)0x9609aadd, (q31_t)0x47c8f601, (q31_t)0x960624a9, + (q31_t)0x47c3c22f, (q31_t)0x96029eb6, (q31_t)0x47be8e31, (q31_t)0x95ff1904, (q31_t)0x47b95a06, (q31_t)0x95fb9394, (q31_t)0x47b425af, (q31_t)0x95f80e65, + (q31_t)0x47aef12c, (q31_t)0x95f48977, (q31_t)0x47a9bc7d, (q31_t)0x95f104cb, (q31_t)0x47a487a2, (q31_t)0x95ed8061, (q31_t)0x479f529a, (q31_t)0x95e9fc38, + (q31_t)0x479a1d67, (q31_t)0x95e67850, (q31_t)0x4794e807, (q31_t)0x95e2f4a9, (q31_t)0x478fb27b, (q31_t)0x95df7145, (q31_t)0x478a7cc2, (q31_t)0x95dbee21, + (q31_t)0x478546de, (q31_t)0x95d86b3f, (q31_t)0x478010cd, (q31_t)0x95d4e89f, (q31_t)0x477ada91, (q31_t)0x95d16640, (q31_t)0x4775a428, (q31_t)0x95cde423, + (q31_t)0x47706d93, (q31_t)0x95ca6247, (q31_t)0x476b36d3, (q31_t)0x95c6e0ac, (q31_t)0x4765ffe6, (q31_t)0x95c35f53, (q31_t)0x4760c8cd, (q31_t)0x95bfde3c, + (q31_t)0x475b9188, (q31_t)0x95bc5d66, (q31_t)0x47565a17, (q31_t)0x95b8dcd2, (q31_t)0x4751227a, (q31_t)0x95b55c7f, (q31_t)0x474beab1, (q31_t)0x95b1dc6e, + (q31_t)0x4746b2bc, (q31_t)0x95ae5c9f, (q31_t)0x47417a9b, (q31_t)0x95aadd11, (q31_t)0x473c424e, (q31_t)0x95a75dc4, (q31_t)0x473709d5, (q31_t)0x95a3deb9, + (q31_t)0x4731d131, (q31_t)0x95a05ff0, (q31_t)0x472c9860, (q31_t)0x959ce169, (q31_t)0x47275f63, (q31_t)0x95996323, (q31_t)0x4722263b, (q31_t)0x9595e51e, + (q31_t)0x471cece7, (q31_t)0x9592675c, (q31_t)0x4717b367, (q31_t)0x958ee9db, (q31_t)0x471279ba, (q31_t)0x958b6c9b, (q31_t)0x470d3fe3, (q31_t)0x9587ef9e, + (q31_t)0x470805df, (q31_t)0x958472e2, (q31_t)0x4702cbaf, (q31_t)0x9580f667, (q31_t)0x46fd9154, (q31_t)0x957d7a2f, (q31_t)0x46f856cd, (q31_t)0x9579fe38, + (q31_t)0x46f31c1a, (q31_t)0x95768283, (q31_t)0x46ede13b, (q31_t)0x9573070f, (q31_t)0x46e8a631, (q31_t)0x956f8bdd, (q31_t)0x46e36afb, (q31_t)0x956c10ed, + (q31_t)0x46de2f99, (q31_t)0x9568963f, (q31_t)0x46d8f40b, (q31_t)0x95651bd2, (q31_t)0x46d3b852, (q31_t)0x9561a1a8, (q31_t)0x46ce7c6d, (q31_t)0x955e27bf, + (q31_t)0x46c9405c, (q31_t)0x955aae17, (q31_t)0x46c40420, (q31_t)0x955734b2, (q31_t)0x46bec7b8, (q31_t)0x9553bb8e, (q31_t)0x46b98b24, (q31_t)0x955042ac, + (q31_t)0x46b44e65, (q31_t)0x954cca0c, (q31_t)0x46af117a, (q31_t)0x954951ae, (q31_t)0x46a9d464, (q31_t)0x9545d992, (q31_t)0x46a49722, (q31_t)0x954261b7, + (q31_t)0x469f59b4, (q31_t)0x953eea1e, (q31_t)0x469a1c1b, (q31_t)0x953b72c7, (q31_t)0x4694de56, (q31_t)0x9537fbb2, (q31_t)0x468fa066, (q31_t)0x953484df, + (q31_t)0x468a624a, (q31_t)0x95310e4e, (q31_t)0x46852403, (q31_t)0x952d97fe, (q31_t)0x467fe590, (q31_t)0x952a21f1, (q31_t)0x467aa6f2, (q31_t)0x9526ac25, + (q31_t)0x46756828, (q31_t)0x9523369c, (q31_t)0x46702933, (q31_t)0x951fc154, (q31_t)0x466aea12, (q31_t)0x951c4c4e, (q31_t)0x4665aac6, (q31_t)0x9518d78a, + (q31_t)0x46606b4e, (q31_t)0x95156308, (q31_t)0x465b2bab, (q31_t)0x9511eec8, (q31_t)0x4655ebdd, (q31_t)0x950e7aca, (q31_t)0x4650abe3, (q31_t)0x950b070e, + (q31_t)0x464b6bbe, (q31_t)0x95079394, (q31_t)0x46462b6d, (q31_t)0x9504205c, (q31_t)0x4640eaf2, (q31_t)0x9500ad66, (q31_t)0x463baa4a, (q31_t)0x94fd3ab1, + (q31_t)0x46366978, (q31_t)0x94f9c83f, (q31_t)0x4631287a, (q31_t)0x94f6560f, (q31_t)0x462be751, (q31_t)0x94f2e421, (q31_t)0x4626a5fd, (q31_t)0x94ef7275, + (q31_t)0x4621647d, (q31_t)0x94ec010b, (q31_t)0x461c22d2, (q31_t)0x94e88fe3, (q31_t)0x4616e0fc, (q31_t)0x94e51efd, (q31_t)0x46119efa, (q31_t)0x94e1ae59, + (q31_t)0x460c5cce, (q31_t)0x94de3df8, (q31_t)0x46071a76, (q31_t)0x94dacdd8, (q31_t)0x4601d7f3, (q31_t)0x94d75dfa, (q31_t)0x45fc9545, (q31_t)0x94d3ee5f, + (q31_t)0x45f7526b, (q31_t)0x94d07f05, (q31_t)0x45f20f67, (q31_t)0x94cd0fee, (q31_t)0x45eccc37, (q31_t)0x94c9a119, (q31_t)0x45e788dc, (q31_t)0x94c63286, + (q31_t)0x45e24556, (q31_t)0x94c2c435, (q31_t)0x45dd01a5, (q31_t)0x94bf5627, (q31_t)0x45d7bdc9, (q31_t)0x94bbe85a, (q31_t)0x45d279c2, (q31_t)0x94b87ad0, + (q31_t)0x45cd358f, (q31_t)0x94b50d87, (q31_t)0x45c7f132, (q31_t)0x94b1a081, (q31_t)0x45c2acaa, (q31_t)0x94ae33be, (q31_t)0x45bd67f6, (q31_t)0x94aac73c, + (q31_t)0x45b82318, (q31_t)0x94a75afd, (q31_t)0x45b2de0e, (q31_t)0x94a3eeff, (q31_t)0x45ad98da, (q31_t)0x94a08344, (q31_t)0x45a8537a, (q31_t)0x949d17cc, + (q31_t)0x45a30df0, (q31_t)0x9499ac95, (q31_t)0x459dc83b, (q31_t)0x949641a1, (q31_t)0x4598825a, (q31_t)0x9492d6ef, (q31_t)0x45933c4f, (q31_t)0x948f6c7f, + (q31_t)0x458df619, (q31_t)0x948c0252, (q31_t)0x4588afb8, (q31_t)0x94889867, (q31_t)0x4583692c, (q31_t)0x94852ebe, (q31_t)0x457e2275, (q31_t)0x9481c557, + (q31_t)0x4578db93, (q31_t)0x947e5c33, (q31_t)0x45739487, (q31_t)0x947af351, (q31_t)0x456e4d4f, (q31_t)0x94778ab1, (q31_t)0x456905ed, (q31_t)0x94742254, + (q31_t)0x4563be60, (q31_t)0x9470ba39, (q31_t)0x455e76a8, (q31_t)0x946d5260, (q31_t)0x45592ec6, (q31_t)0x9469eaca, (q31_t)0x4553e6b8, (q31_t)0x94668376, + (q31_t)0x454e9e80, (q31_t)0x94631c65, (q31_t)0x4549561d, (q31_t)0x945fb596, (q31_t)0x45440d90, (q31_t)0x945c4f09, (q31_t)0x453ec4d7, (q31_t)0x9458e8bf, + (q31_t)0x45397bf4, (q31_t)0x945582b7, (q31_t)0x453432e6, (q31_t)0x94521cf1, (q31_t)0x452ee9ae, (q31_t)0x944eb76e, (q31_t)0x4529a04b, (q31_t)0x944b522d, + (q31_t)0x452456bd, (q31_t)0x9447ed2f, (q31_t)0x451f0d04, (q31_t)0x94448873, (q31_t)0x4519c321, (q31_t)0x944123fa, (q31_t)0x45147913, (q31_t)0x943dbfc3, + (q31_t)0x450f2edb, (q31_t)0x943a5bcf, (q31_t)0x4509e478, (q31_t)0x9436f81d, (q31_t)0x450499eb, (q31_t)0x943394ad, (q31_t)0x44ff4f32, (q31_t)0x94303180, + (q31_t)0x44fa0450, (q31_t)0x942cce96, (q31_t)0x44f4b943, (q31_t)0x94296bee, (q31_t)0x44ef6e0b, (q31_t)0x94260989, (q31_t)0x44ea22a9, (q31_t)0x9422a766, + (q31_t)0x44e4d71c, (q31_t)0x941f4585, (q31_t)0x44df8b64, (q31_t)0x941be3e8, (q31_t)0x44da3f83, (q31_t)0x9418828c, (q31_t)0x44d4f376, (q31_t)0x94152174, + (q31_t)0x44cfa740, (q31_t)0x9411c09e, (q31_t)0x44ca5adf, (q31_t)0x940e600a, (q31_t)0x44c50e53, (q31_t)0x940affb9, (q31_t)0x44bfc19d, (q31_t)0x94079fab, + (q31_t)0x44ba74bd, (q31_t)0x94043fdf, (q31_t)0x44b527b2, (q31_t)0x9400e056, (q31_t)0x44afda7d, (q31_t)0x93fd810f, (q31_t)0x44aa8d1d, (q31_t)0x93fa220b, + (q31_t)0x44a53f93, (q31_t)0x93f6c34a, (q31_t)0x449ff1df, (q31_t)0x93f364cb, (q31_t)0x449aa400, (q31_t)0x93f0068f, (q31_t)0x449555f7, (q31_t)0x93eca896, + (q31_t)0x449007c4, (q31_t)0x93e94adf, (q31_t)0x448ab967, (q31_t)0x93e5ed6b, (q31_t)0x44856adf, (q31_t)0x93e2903a, (q31_t)0x44801c2d, (q31_t)0x93df334c, + (q31_t)0x447acd50, (q31_t)0x93dbd6a0, (q31_t)0x44757e4a, (q31_t)0x93d87a36, (q31_t)0x44702f19, (q31_t)0x93d51e10, (q31_t)0x446adfbe, (q31_t)0x93d1c22c, + (q31_t)0x44659039, (q31_t)0x93ce668b, (q31_t)0x44604089, (q31_t)0x93cb0b2d, (q31_t)0x445af0b0, (q31_t)0x93c7b011, (q31_t)0x4455a0ac, (q31_t)0x93c45539, + (q31_t)0x4450507e, (q31_t)0x93c0faa3, (q31_t)0x444b0026, (q31_t)0x93bda04f, (q31_t)0x4445afa4, (q31_t)0x93ba463f, (q31_t)0x44405ef8, (q31_t)0x93b6ec71, + (q31_t)0x443b0e21, (q31_t)0x93b392e6, (q31_t)0x4435bd21, (q31_t)0x93b0399e, (q31_t)0x44306bf6, (q31_t)0x93ace099, (q31_t)0x442b1aa2, (q31_t)0x93a987d6, + (q31_t)0x4425c923, (q31_t)0x93a62f57, (q31_t)0x4420777b, (q31_t)0x93a2d71a, (q31_t)0x441b25a8, (q31_t)0x939f7f20, (q31_t)0x4415d3ab, (q31_t)0x939c2769, + (q31_t)0x44108184, (q31_t)0x9398cff5, (q31_t)0x440b2f34, (q31_t)0x939578c3, (q31_t)0x4405dcb9, (q31_t)0x939221d5, (q31_t)0x44008a14, (q31_t)0x938ecb29, + (q31_t)0x43fb3746, (q31_t)0x938b74c1, (q31_t)0x43f5e44d, (q31_t)0x93881e9b, (q31_t)0x43f0912b, (q31_t)0x9384c8b8, (q31_t)0x43eb3ddf, (q31_t)0x93817318, + (q31_t)0x43e5ea68, (q31_t)0x937e1dbb, (q31_t)0x43e096c8, (q31_t)0x937ac8a1, (q31_t)0x43db42fe, (q31_t)0x937773ca, (q31_t)0x43d5ef0a, (q31_t)0x93741f35, + (q31_t)0x43d09aed, (q31_t)0x9370cae4, (q31_t)0x43cb46a5, (q31_t)0x936d76d6, (q31_t)0x43c5f234, (q31_t)0x936a230a, (q31_t)0x43c09d99, (q31_t)0x9366cf82, + (q31_t)0x43bb48d4, (q31_t)0x93637c3d, (q31_t)0x43b5f3e5, (q31_t)0x9360293a, (q31_t)0x43b09ecc, (q31_t)0x935cd67b, (q31_t)0x43ab498a, (q31_t)0x935983ff, + (q31_t)0x43a5f41e, (q31_t)0x935631c5, (q31_t)0x43a09e89, (q31_t)0x9352dfcf, (q31_t)0x439b48c9, (q31_t)0x934f8e1c, (q31_t)0x4395f2e0, (q31_t)0x934c3cab, + (q31_t)0x43909ccd, (q31_t)0x9348eb7e, (q31_t)0x438b4691, (q31_t)0x93459a94, (q31_t)0x4385f02a, (q31_t)0x934249ed, (q31_t)0x4380999b, (q31_t)0x933ef989, + (q31_t)0x437b42e1, (q31_t)0x933ba968, (q31_t)0x4375ebfe, (q31_t)0x9338598a, (q31_t)0x437094f1, (q31_t)0x933509f0, (q31_t)0x436b3dbb, (q31_t)0x9331ba98, + (q31_t)0x4365e65b, (q31_t)0x932e6b84, (q31_t)0x43608ed2, (q31_t)0x932b1cb2, (q31_t)0x435b371f, (q31_t)0x9327ce24, (q31_t)0x4355df42, (q31_t)0x93247fd9, + (q31_t)0x4350873c, (q31_t)0x932131d1, (q31_t)0x434b2f0c, (q31_t)0x931de40c, (q31_t)0x4345d6b3, (q31_t)0x931a968b, (q31_t)0x43407e31, (q31_t)0x9317494c, + (q31_t)0x433b2585, (q31_t)0x9313fc51, (q31_t)0x4335ccaf, (q31_t)0x9310af99, (q31_t)0x433073b0, (q31_t)0x930d6324, (q31_t)0x432b1a87, (q31_t)0x930a16f3, + (q31_t)0x4325c135, (q31_t)0x9306cb04, (q31_t)0x432067ba, (q31_t)0x93037f59, (q31_t)0x431b0e15, (q31_t)0x930033f1, (q31_t)0x4315b447, (q31_t)0x92fce8cc, + (q31_t)0x43105a50, (q31_t)0x92f99deb, (q31_t)0x430b002f, (q31_t)0x92f6534c, (q31_t)0x4305a5e5, (q31_t)0x92f308f1, (q31_t)0x43004b71, (q31_t)0x92efbeda, + (q31_t)0x42faf0d4, (q31_t)0x92ec7505, (q31_t)0x42f5960e, (q31_t)0x92e92b74, (q31_t)0x42f03b1e, (q31_t)0x92e5e226, (q31_t)0x42eae005, (q31_t)0x92e2991c, + (q31_t)0x42e584c3, (q31_t)0x92df5054, (q31_t)0x42e02958, (q31_t)0x92dc07d0, (q31_t)0x42dacdc3, (q31_t)0x92d8bf90, (q31_t)0x42d57205, (q31_t)0x92d57792, + (q31_t)0x42d0161e, (q31_t)0x92d22fd9, (q31_t)0x42caba0e, (q31_t)0x92cee862, (q31_t)0x42c55dd4, (q31_t)0x92cba12f, (q31_t)0x42c00172, (q31_t)0x92c85a3f, + (q31_t)0x42baa4e6, (q31_t)0x92c51392, (q31_t)0x42b54831, (q31_t)0x92c1cd29, (q31_t)0x42afeb53, (q31_t)0x92be8703, (q31_t)0x42aa8e4b, (q31_t)0x92bb4121, + (q31_t)0x42a5311b, (q31_t)0x92b7fb82, (q31_t)0x429fd3c1, (q31_t)0x92b4b626, (q31_t)0x429a763f, (q31_t)0x92b1710e, (q31_t)0x42951893, (q31_t)0x92ae2c3a, + (q31_t)0x428fbabe, (q31_t)0x92aae7a8, (q31_t)0x428a5cc0, (q31_t)0x92a7a35a, (q31_t)0x4284fe99, (q31_t)0x92a45f50, (q31_t)0x427fa049, (q31_t)0x92a11b89, + (q31_t)0x427a41d0, (q31_t)0x929dd806, (q31_t)0x4274e32e, (q31_t)0x929a94c6, (q31_t)0x426f8463, (q31_t)0x929751c9, (q31_t)0x426a256f, (q31_t)0x92940f10, + (q31_t)0x4264c653, (q31_t)0x9290cc9b, (q31_t)0x425f670d, (q31_t)0x928d8a69, (q31_t)0x425a079e, (q31_t)0x928a487a, (q31_t)0x4254a806, (q31_t)0x928706cf, + (q31_t)0x424f4845, (q31_t)0x9283c568, (q31_t)0x4249e85c, (q31_t)0x92808444, (q31_t)0x42448849, (q31_t)0x927d4363, (q31_t)0x423f280e, (q31_t)0x927a02c7, + (q31_t)0x4239c7aa, (q31_t)0x9276c26d, (q31_t)0x4234671d, (q31_t)0x92738258, (q31_t)0x422f0667, (q31_t)0x92704286, (q31_t)0x4229a588, (q31_t)0x926d02f7, + (q31_t)0x42244481, (q31_t)0x9269c3ac, (q31_t)0x421ee350, (q31_t)0x926684a5, (q31_t)0x421981f7, (q31_t)0x926345e1, (q31_t)0x42142075, (q31_t)0x92600761, + (q31_t)0x420ebecb, (q31_t)0x925cc924, (q31_t)0x42095cf7, (q31_t)0x92598b2b, (q31_t)0x4203fafb, (q31_t)0x92564d76, (q31_t)0x41fe98d6, (q31_t)0x92531005, + (q31_t)0x41f93689, (q31_t)0x924fd2d7, (q31_t)0x41f3d413, (q31_t)0x924c95ec, (q31_t)0x41ee7174, (q31_t)0x92495946, (q31_t)0x41e90eac, (q31_t)0x92461ce3, + (q31_t)0x41e3abbc, (q31_t)0x9242e0c4, (q31_t)0x41de48a3, (q31_t)0x923fa4e8, (q31_t)0x41d8e561, (q31_t)0x923c6950, (q31_t)0x41d381f7, (q31_t)0x92392dfc, + (q31_t)0x41ce1e65, (q31_t)0x9235f2ec, (q31_t)0x41c8baa9, (q31_t)0x9232b81f, (q31_t)0x41c356c5, (q31_t)0x922f7d96, (q31_t)0x41bdf2b9, (q31_t)0x922c4351, + (q31_t)0x41b88e84, (q31_t)0x9229094f, (q31_t)0x41b32a26, (q31_t)0x9225cf91, (q31_t)0x41adc5a0, (q31_t)0x92229617, (q31_t)0x41a860f1, (q31_t)0x921f5ce1, + (q31_t)0x41a2fc1a, (q31_t)0x921c23ef, (q31_t)0x419d971b, (q31_t)0x9218eb40, (q31_t)0x419831f3, (q31_t)0x9215b2d5, (q31_t)0x4192cca2, (q31_t)0x92127aae, + (q31_t)0x418d6729, (q31_t)0x920f42cb, (q31_t)0x41880188, (q31_t)0x920c0b2c, (q31_t)0x41829bbe, (q31_t)0x9208d3d0, (q31_t)0x417d35cb, (q31_t)0x92059cb8, + (q31_t)0x4177cfb1, (q31_t)0x920265e4, (q31_t)0x4172696e, (q31_t)0x91ff2f54, (q31_t)0x416d0302, (q31_t)0x91fbf908, (q31_t)0x41679c6f, (q31_t)0x91f8c300, + (q31_t)0x416235b2, (q31_t)0x91f58d3b, (q31_t)0x415ccece, (q31_t)0x91f257bb, (q31_t)0x415767c1, (q31_t)0x91ef227e, (q31_t)0x4152008c, (q31_t)0x91ebed85, + (q31_t)0x414c992f, (q31_t)0x91e8b8d0, (q31_t)0x414731a9, (q31_t)0x91e5845f, (q31_t)0x4141c9fb, (q31_t)0x91e25032, (q31_t)0x413c6225, (q31_t)0x91df1c49, + (q31_t)0x4136fa27, (q31_t)0x91dbe8a4, (q31_t)0x41319200, (q31_t)0x91d8b542, (q31_t)0x412c29b1, (q31_t)0x91d58225, (q31_t)0x4126c13a, (q31_t)0x91d24f4c, + (q31_t)0x4121589b, (q31_t)0x91cf1cb6, (q31_t)0x411befd3, (q31_t)0x91cbea65, (q31_t)0x411686e4, (q31_t)0x91c8b857, (q31_t)0x41111dcc, (q31_t)0x91c5868e, + (q31_t)0x410bb48c, (q31_t)0x91c25508, (q31_t)0x41064b24, (q31_t)0x91bf23c7, (q31_t)0x4100e194, (q31_t)0x91bbf2c9, (q31_t)0x40fb77dc, (q31_t)0x91b8c210, + (q31_t)0x40f60dfb, (q31_t)0x91b5919a, (q31_t)0x40f0a3f3, (q31_t)0x91b26169, (q31_t)0x40eb39c3, (q31_t)0x91af317c, (q31_t)0x40e5cf6a, (q31_t)0x91ac01d2, + (q31_t)0x40e064ea, (q31_t)0x91a8d26d, (q31_t)0x40dafa41, (q31_t)0x91a5a34c, (q31_t)0x40d58f71, (q31_t)0x91a2746f, (q31_t)0x40d02478, (q31_t)0x919f45d6, + (q31_t)0x40cab958, (q31_t)0x919c1781, (q31_t)0x40c54e0f, (q31_t)0x9198e970, (q31_t)0x40bfe29f, (q31_t)0x9195bba3, (q31_t)0x40ba7706, (q31_t)0x91928e1a, + (q31_t)0x40b50b46, (q31_t)0x918f60d6, (q31_t)0x40af9f5e, (q31_t)0x918c33d5, (q31_t)0x40aa334e, (q31_t)0x91890719, (q31_t)0x40a4c716, (q31_t)0x9185daa1, + (q31_t)0x409f5ab6, (q31_t)0x9182ae6d, (q31_t)0x4099ee2e, (q31_t)0x917f827d, (q31_t)0x4094817f, (q31_t)0x917c56d1, (q31_t)0x408f14a7, (q31_t)0x91792b6a, + (q31_t)0x4089a7a8, (q31_t)0x91760047, (q31_t)0x40843a81, (q31_t)0x9172d567, (q31_t)0x407ecd32, (q31_t)0x916faacc, (q31_t)0x40795fbc, (q31_t)0x916c8076, + (q31_t)0x4073f21d, (q31_t)0x91695663, (q31_t)0x406e8457, (q31_t)0x91662c95, (q31_t)0x40691669, (q31_t)0x9163030b, (q31_t)0x4063a854, (q31_t)0x915fd9c5, + (q31_t)0x405e3a16, (q31_t)0x915cb0c3, (q31_t)0x4058cbb1, (q31_t)0x91598806, (q31_t)0x40535d24, (q31_t)0x91565f8d, (q31_t)0x404dee70, (q31_t)0x91533758, + (q31_t)0x40487f94, (q31_t)0x91500f67, (q31_t)0x40431090, (q31_t)0x914ce7bb, (q31_t)0x403da165, (q31_t)0x9149c053, (q31_t)0x40383212, (q31_t)0x9146992f, + (q31_t)0x4032c297, (q31_t)0x91437250, (q31_t)0x402d52f5, (q31_t)0x91404bb5, (q31_t)0x4027e32b, (q31_t)0x913d255e, (q31_t)0x4022733a, (q31_t)0x9139ff4b, + (q31_t)0x401d0321, (q31_t)0x9136d97d, (q31_t)0x401792e0, (q31_t)0x9133b3f3, (q31_t)0x40122278, (q31_t)0x91308eae, (q31_t)0x400cb1e9, (q31_t)0x912d69ad, + (q31_t)0x40074132, (q31_t)0x912a44f0, (q31_t)0x4001d053, (q31_t)0x91272078, (q31_t)0x3ffc5f4d, (q31_t)0x9123fc44, (q31_t)0x3ff6ee1f, (q31_t)0x9120d854, + (q31_t)0x3ff17cca, (q31_t)0x911db4a9, (q31_t)0x3fec0b4e, (q31_t)0x911a9142, (q31_t)0x3fe699aa, (q31_t)0x91176e1f, (q31_t)0x3fe127df, (q31_t)0x91144b41, + (q31_t)0x3fdbb5ec, (q31_t)0x911128a8, (q31_t)0x3fd643d2, (q31_t)0x910e0653, (q31_t)0x3fd0d191, (q31_t)0x910ae442, (q31_t)0x3fcb5f28, (q31_t)0x9107c276, + (q31_t)0x3fc5ec98, (q31_t)0x9104a0ee, (q31_t)0x3fc079e0, (q31_t)0x91017faa, (q31_t)0x3fbb0702, (q31_t)0x90fe5eab, (q31_t)0x3fb593fb, (q31_t)0x90fb3df1, + (q31_t)0x3fb020ce, (q31_t)0x90f81d7b, (q31_t)0x3faaad79, (q31_t)0x90f4fd4a, (q31_t)0x3fa539fd, (q31_t)0x90f1dd5d, (q31_t)0x3f9fc65a, (q31_t)0x90eebdb4, + (q31_t)0x3f9a5290, (q31_t)0x90eb9e50, (q31_t)0x3f94de9e, (q31_t)0x90e87f31, (q31_t)0x3f8f6a85, (q31_t)0x90e56056, (q31_t)0x3f89f645, (q31_t)0x90e241bf, + (q31_t)0x3f8481dd, (q31_t)0x90df236e, (q31_t)0x3f7f0d4f, (q31_t)0x90dc0560, (q31_t)0x3f799899, (q31_t)0x90d8e798, (q31_t)0x3f7423bc, (q31_t)0x90d5ca13, + (q31_t)0x3f6eaeb8, (q31_t)0x90d2acd4, (q31_t)0x3f69398d, (q31_t)0x90cf8fd9, (q31_t)0x3f63c43b, (q31_t)0x90cc7322, (q31_t)0x3f5e4ec2, (q31_t)0x90c956b1, + (q31_t)0x3f58d921, (q31_t)0x90c63a83, (q31_t)0x3f53635a, (q31_t)0x90c31e9b, (q31_t)0x3f4ded6b, (q31_t)0x90c002f7, (q31_t)0x3f487755, (q31_t)0x90bce797, + (q31_t)0x3f430119, (q31_t)0x90b9cc7d, (q31_t)0x3f3d8ab5, (q31_t)0x90b6b1a6, (q31_t)0x3f38142a, (q31_t)0x90b39715, (q31_t)0x3f329d79, (q31_t)0x90b07cc8, + (q31_t)0x3f2d26a0, (q31_t)0x90ad62c0, (q31_t)0x3f27afa1, (q31_t)0x90aa48fd, (q31_t)0x3f22387a, (q31_t)0x90a72f7e, (q31_t)0x3f1cc12c, (q31_t)0x90a41644, + (q31_t)0x3f1749b8, (q31_t)0x90a0fd4e, (q31_t)0x3f11d21d, (q31_t)0x909de49e, (q31_t)0x3f0c5a5a, (q31_t)0x909acc32, (q31_t)0x3f06e271, (q31_t)0x9097b40a, + (q31_t)0x3f016a61, (q31_t)0x90949c28, (q31_t)0x3efbf22a, (q31_t)0x9091848a, (q31_t)0x3ef679cc, (q31_t)0x908e6d31, (q31_t)0x3ef10148, (q31_t)0x908b561c, + (q31_t)0x3eeb889c, (q31_t)0x90883f4d, (q31_t)0x3ee60fca, (q31_t)0x908528c2, (q31_t)0x3ee096d1, (q31_t)0x9082127c, (q31_t)0x3edb1db1, (q31_t)0x907efc7a, + (q31_t)0x3ed5a46b, (q31_t)0x907be6be, (q31_t)0x3ed02afd, (q31_t)0x9078d146, (q31_t)0x3ecab169, (q31_t)0x9075bc13, (q31_t)0x3ec537ae, (q31_t)0x9072a725, + (q31_t)0x3ebfbdcd, (q31_t)0x906f927c, (q31_t)0x3eba43c4, (q31_t)0x906c7e17, (q31_t)0x3eb4c995, (q31_t)0x906969f8, (q31_t)0x3eaf4f40, (q31_t)0x9066561d, + (q31_t)0x3ea9d4c3, (q31_t)0x90634287, (q31_t)0x3ea45a21, (q31_t)0x90602f35, (q31_t)0x3e9edf57, (q31_t)0x905d1c29, (q31_t)0x3e996467, (q31_t)0x905a0962, + (q31_t)0x3e93e950, (q31_t)0x9056f6df, (q31_t)0x3e8e6e12, (q31_t)0x9053e4a1, (q31_t)0x3e88f2ae, (q31_t)0x9050d2a9, (q31_t)0x3e837724, (q31_t)0x904dc0f5, + (q31_t)0x3e7dfb73, (q31_t)0x904aaf86, (q31_t)0x3e787f9b, (q31_t)0x90479e5c, (q31_t)0x3e73039d, (q31_t)0x90448d76, (q31_t)0x3e6d8778, (q31_t)0x90417cd6, + (q31_t)0x3e680b2c, (q31_t)0x903e6c7b, (q31_t)0x3e628ebb, (q31_t)0x903b5c64, (q31_t)0x3e5d1222, (q31_t)0x90384c93, (q31_t)0x3e579564, (q31_t)0x90353d06, + (q31_t)0x3e52187f, (q31_t)0x90322dbf, (q31_t)0x3e4c9b73, (q31_t)0x902f1ebc, (q31_t)0x3e471e41, (q31_t)0x902c0fff, (q31_t)0x3e41a0e8, (q31_t)0x90290186, + (q31_t)0x3e3c2369, (q31_t)0x9025f352, (q31_t)0x3e36a5c4, (q31_t)0x9022e564, (q31_t)0x3e3127f9, (q31_t)0x901fd7ba, (q31_t)0x3e2baa07, (q31_t)0x901cca55, + (q31_t)0x3e262bee, (q31_t)0x9019bd36, (q31_t)0x3e20adaf, (q31_t)0x9016b05b, (q31_t)0x3e1b2f4a, (q31_t)0x9013a3c5, (q31_t)0x3e15b0bf, (q31_t)0x90109775, + (q31_t)0x3e10320d, (q31_t)0x900d8b69, (q31_t)0x3e0ab336, (q31_t)0x900a7fa3, (q31_t)0x3e053437, (q31_t)0x90077422, (q31_t)0x3dffb513, (q31_t)0x900468e5, + (q31_t)0x3dfa35c8, (q31_t)0x90015dee, (q31_t)0x3df4b657, (q31_t)0x8ffe533c, (q31_t)0x3def36c0, (q31_t)0x8ffb48cf, (q31_t)0x3de9b703, (q31_t)0x8ff83ea7, + (q31_t)0x3de4371f, (q31_t)0x8ff534c4, (q31_t)0x3ddeb716, (q31_t)0x8ff22b26, (q31_t)0x3dd936e6, (q31_t)0x8fef21ce, (q31_t)0x3dd3b690, (q31_t)0x8fec18ba, + (q31_t)0x3dce3614, (q31_t)0x8fe90fec, (q31_t)0x3dc8b571, (q31_t)0x8fe60763, (q31_t)0x3dc334a9, (q31_t)0x8fe2ff1f, (q31_t)0x3dbdb3ba, (q31_t)0x8fdff720, + (q31_t)0x3db832a6, (q31_t)0x8fdcef66, (q31_t)0x3db2b16b, (q31_t)0x8fd9e7f2, (q31_t)0x3dad300b, (q31_t)0x8fd6e0c2, (q31_t)0x3da7ae84, (q31_t)0x8fd3d9d8, + (q31_t)0x3da22cd7, (q31_t)0x8fd0d333, (q31_t)0x3d9cab04, (q31_t)0x8fcdccd3, (q31_t)0x3d97290b, (q31_t)0x8fcac6b9, (q31_t)0x3d91a6ed, (q31_t)0x8fc7c0e3, + (q31_t)0x3d8c24a8, (q31_t)0x8fc4bb53, (q31_t)0x3d86a23d, (q31_t)0x8fc1b608, (q31_t)0x3d811fac, (q31_t)0x8fbeb103, (q31_t)0x3d7b9cf6, (q31_t)0x8fbbac42, + (q31_t)0x3d761a19, (q31_t)0x8fb8a7c7, (q31_t)0x3d709717, (q31_t)0x8fb5a391, (q31_t)0x3d6b13ee, (q31_t)0x8fb29fa0, (q31_t)0x3d6590a0, (q31_t)0x8faf9bf5, + (q31_t)0x3d600d2c, (q31_t)0x8fac988f, (q31_t)0x3d5a8992, (q31_t)0x8fa9956e, (q31_t)0x3d5505d2, (q31_t)0x8fa69293, (q31_t)0x3d4f81ec, (q31_t)0x8fa38ffc, + (q31_t)0x3d49fde1, (q31_t)0x8fa08dab, (q31_t)0x3d4479b0, (q31_t)0x8f9d8ba0, (q31_t)0x3d3ef559, (q31_t)0x8f9a89da, (q31_t)0x3d3970dc, (q31_t)0x8f978859, + (q31_t)0x3d33ec39, (q31_t)0x8f94871d, (q31_t)0x3d2e6771, (q31_t)0x8f918627, (q31_t)0x3d28e282, (q31_t)0x8f8e8576, (q31_t)0x3d235d6f, (q31_t)0x8f8b850a, + (q31_t)0x3d1dd835, (q31_t)0x8f8884e4, (q31_t)0x3d1852d6, (q31_t)0x8f858503, (q31_t)0x3d12cd51, (q31_t)0x8f828568, (q31_t)0x3d0d47a6, (q31_t)0x8f7f8612, + (q31_t)0x3d07c1d6, (q31_t)0x8f7c8701, (q31_t)0x3d023be0, (q31_t)0x8f798836, (q31_t)0x3cfcb5c4, (q31_t)0x8f7689b0, (q31_t)0x3cf72f83, (q31_t)0x8f738b70, + (q31_t)0x3cf1a91c, (q31_t)0x8f708d75, (q31_t)0x3cec2290, (q31_t)0x8f6d8fbf, (q31_t)0x3ce69bde, (q31_t)0x8f6a924f, (q31_t)0x3ce11507, (q31_t)0x8f679525, + (q31_t)0x3cdb8e09, (q31_t)0x8f649840, (q31_t)0x3cd606e7, (q31_t)0x8f619ba0, (q31_t)0x3cd07f9f, (q31_t)0x8f5e9f46, (q31_t)0x3ccaf831, (q31_t)0x8f5ba331, + (q31_t)0x3cc5709e, (q31_t)0x8f58a761, (q31_t)0x3cbfe8e5, (q31_t)0x8f55abd8, (q31_t)0x3cba6107, (q31_t)0x8f52b093, (q31_t)0x3cb4d904, (q31_t)0x8f4fb595, + (q31_t)0x3caf50da, (q31_t)0x8f4cbadb, (q31_t)0x3ca9c88c, (q31_t)0x8f49c067, (q31_t)0x3ca44018, (q31_t)0x8f46c639, (q31_t)0x3c9eb77f, (q31_t)0x8f43cc50, + (q31_t)0x3c992ec0, (q31_t)0x8f40d2ad, (q31_t)0x3c93a5dc, (q31_t)0x8f3dd950, (q31_t)0x3c8e1cd3, (q31_t)0x8f3ae038, (q31_t)0x3c8893a4, (q31_t)0x8f37e765, + (q31_t)0x3c830a50, (q31_t)0x8f34eed8, (q31_t)0x3c7d80d6, (q31_t)0x8f31f691, (q31_t)0x3c77f737, (q31_t)0x8f2efe8f, (q31_t)0x3c726d73, (q31_t)0x8f2c06d3, + (q31_t)0x3c6ce38a, (q31_t)0x8f290f5c, (q31_t)0x3c67597b, (q31_t)0x8f26182b, (q31_t)0x3c61cf48, (q31_t)0x8f232140, (q31_t)0x3c5c44ee, (q31_t)0x8f202a9a, + (q31_t)0x3c56ba70, (q31_t)0x8f1d343a, (q31_t)0x3c512fcc, (q31_t)0x8f1a3e1f, (q31_t)0x3c4ba504, (q31_t)0x8f17484b, (q31_t)0x3c461a16, (q31_t)0x8f1452bb, + (q31_t)0x3c408f03, (q31_t)0x8f115d72, (q31_t)0x3c3b03ca, (q31_t)0x8f0e686e, (q31_t)0x3c35786d, (q31_t)0x8f0b73b0, (q31_t)0x3c2fecea, (q31_t)0x8f087f37, + (q31_t)0x3c2a6142, (q31_t)0x8f058b04, (q31_t)0x3c24d575, (q31_t)0x8f029717, (q31_t)0x3c1f4983, (q31_t)0x8effa370, (q31_t)0x3c19bd6c, (q31_t)0x8efcb00e, + (q31_t)0x3c143130, (q31_t)0x8ef9bcf2, (q31_t)0x3c0ea4cf, (q31_t)0x8ef6ca1c, (q31_t)0x3c091849, (q31_t)0x8ef3d78b, (q31_t)0x3c038b9e, (q31_t)0x8ef0e540, + (q31_t)0x3bfdfecd, (q31_t)0x8eedf33b, (q31_t)0x3bf871d8, (q31_t)0x8eeb017c, (q31_t)0x3bf2e4be, (q31_t)0x8ee81002, (q31_t)0x3bed577e, (q31_t)0x8ee51ece, + (q31_t)0x3be7ca1a, (q31_t)0x8ee22de0, (q31_t)0x3be23c91, (q31_t)0x8edf3d38, (q31_t)0x3bdcaee3, (q31_t)0x8edc4cd5, (q31_t)0x3bd72110, (q31_t)0x8ed95cb8, + (q31_t)0x3bd19318, (q31_t)0x8ed66ce1, (q31_t)0x3bcc04fb, (q31_t)0x8ed37d50, (q31_t)0x3bc676b9, (q31_t)0x8ed08e05, (q31_t)0x3bc0e853, (q31_t)0x8ecd9eff, + (q31_t)0x3bbb59c7, (q31_t)0x8ecab040, (q31_t)0x3bb5cb17, (q31_t)0x8ec7c1c6, (q31_t)0x3bb03c42, (q31_t)0x8ec4d392, (q31_t)0x3baaad48, (q31_t)0x8ec1e5a4, + (q31_t)0x3ba51e29, (q31_t)0x8ebef7fb, (q31_t)0x3b9f8ee5, (q31_t)0x8ebc0a99, (q31_t)0x3b99ff7d, (q31_t)0x8eb91d7c, (q31_t)0x3b946ff0, (q31_t)0x8eb630a6, + (q31_t)0x3b8ee03e, (q31_t)0x8eb34415, (q31_t)0x3b895068, (q31_t)0x8eb057ca, (q31_t)0x3b83c06c, (q31_t)0x8ead6bc5, (q31_t)0x3b7e304c, (q31_t)0x8eaa8006, + (q31_t)0x3b78a007, (q31_t)0x8ea7948c, (q31_t)0x3b730f9e, (q31_t)0x8ea4a959, (q31_t)0x3b6d7f10, (q31_t)0x8ea1be6c, (q31_t)0x3b67ee5d, (q31_t)0x8e9ed3c4, + (q31_t)0x3b625d86, (q31_t)0x8e9be963, (q31_t)0x3b5ccc8a, (q31_t)0x8e98ff47, (q31_t)0x3b573b69, (q31_t)0x8e961571, (q31_t)0x3b51aa24, (q31_t)0x8e932be2, + (q31_t)0x3b4c18ba, (q31_t)0x8e904298, (q31_t)0x3b46872c, (q31_t)0x8e8d5994, (q31_t)0x3b40f579, (q31_t)0x8e8a70d7, (q31_t)0x3b3b63a1, (q31_t)0x8e87885f, + (q31_t)0x3b35d1a5, (q31_t)0x8e84a02d, (q31_t)0x3b303f84, (q31_t)0x8e81b841, (q31_t)0x3b2aad3f, (q31_t)0x8e7ed09b, (q31_t)0x3b251ad6, (q31_t)0x8e7be93c, + (q31_t)0x3b1f8848, (q31_t)0x8e790222, (q31_t)0x3b19f595, (q31_t)0x8e761b4e, (q31_t)0x3b1462be, (q31_t)0x8e7334c1, (q31_t)0x3b0ecfc3, (q31_t)0x8e704e79, + (q31_t)0x3b093ca3, (q31_t)0x8e6d6877, (q31_t)0x3b03a95e, (q31_t)0x8e6a82bc, (q31_t)0x3afe15f6, (q31_t)0x8e679d47, (q31_t)0x3af88269, (q31_t)0x8e64b817, + (q31_t)0x3af2eeb7, (q31_t)0x8e61d32e, (q31_t)0x3aed5ae1, (q31_t)0x8e5eee8b, (q31_t)0x3ae7c6e7, (q31_t)0x8e5c0a2e, (q31_t)0x3ae232c9, (q31_t)0x8e592617, + (q31_t)0x3adc9e86, (q31_t)0x8e564246, (q31_t)0x3ad70a1f, (q31_t)0x8e535ebb, (q31_t)0x3ad17593, (q31_t)0x8e507b76, (q31_t)0x3acbe0e3, (q31_t)0x8e4d9878, + (q31_t)0x3ac64c0f, (q31_t)0x8e4ab5bf, (q31_t)0x3ac0b717, (q31_t)0x8e47d34d, (q31_t)0x3abb21fb, (q31_t)0x8e44f121, (q31_t)0x3ab58cba, (q31_t)0x8e420f3b, + (q31_t)0x3aaff755, (q31_t)0x8e3f2d9b, (q31_t)0x3aaa61cc, (q31_t)0x8e3c4c41, (q31_t)0x3aa4cc1e, (q31_t)0x8e396b2e, (q31_t)0x3a9f364d, (q31_t)0x8e368a61, + (q31_t)0x3a99a057, (q31_t)0x8e33a9da, (q31_t)0x3a940a3e, (q31_t)0x8e30c999, (q31_t)0x3a8e7400, (q31_t)0x8e2de99e, (q31_t)0x3a88dd9d, (q31_t)0x8e2b09e9, + (q31_t)0x3a834717, (q31_t)0x8e282a7b, (q31_t)0x3a7db06d, (q31_t)0x8e254b53, (q31_t)0x3a78199f, (q31_t)0x8e226c71, (q31_t)0x3a7282ac, (q31_t)0x8e1f8dd6, + (q31_t)0x3a6ceb96, (q31_t)0x8e1caf80, (q31_t)0x3a67545b, (q31_t)0x8e19d171, (q31_t)0x3a61bcfd, (q31_t)0x8e16f3a9, (q31_t)0x3a5c257a, (q31_t)0x8e141626, + (q31_t)0x3a568dd4, (q31_t)0x8e1138ea, (q31_t)0x3a50f609, (q31_t)0x8e0e5bf4, (q31_t)0x3a4b5e1b, (q31_t)0x8e0b7f44, (q31_t)0x3a45c608, (q31_t)0x8e08a2db, + (q31_t)0x3a402dd2, (q31_t)0x8e05c6b7, (q31_t)0x3a3a9577, (q31_t)0x8e02eadb, (q31_t)0x3a34fcf9, (q31_t)0x8e000f44, (q31_t)0x3a2f6457, (q31_t)0x8dfd33f4, + (q31_t)0x3a29cb91, (q31_t)0x8dfa58ea, (q31_t)0x3a2432a7, (q31_t)0x8df77e27, (q31_t)0x3a1e9999, (q31_t)0x8df4a3a9, (q31_t)0x3a190068, (q31_t)0x8df1c973, + (q31_t)0x3a136712, (q31_t)0x8deeef82, (q31_t)0x3a0dcd99, (q31_t)0x8dec15d8, (q31_t)0x3a0833fc, (q31_t)0x8de93c74, (q31_t)0x3a029a3b, (q31_t)0x8de66357, + (q31_t)0x39fd0056, (q31_t)0x8de38a80, (q31_t)0x39f7664e, (q31_t)0x8de0b1ef, (q31_t)0x39f1cc21, (q31_t)0x8dddd9a5, (q31_t)0x39ec31d1, (q31_t)0x8ddb01a1, + (q31_t)0x39e6975e, (q31_t)0x8dd829e4, (q31_t)0x39e0fcc6, (q31_t)0x8dd5526d, (q31_t)0x39db620b, (q31_t)0x8dd27b3c, (q31_t)0x39d5c72c, (q31_t)0x8dcfa452, + (q31_t)0x39d02c2a, (q31_t)0x8dcccdaf, (q31_t)0x39ca9104, (q31_t)0x8dc9f751, (q31_t)0x39c4f5ba, (q31_t)0x8dc7213b, (q31_t)0x39bf5a4d, (q31_t)0x8dc44b6a, + (q31_t)0x39b9bebc, (q31_t)0x8dc175e0, (q31_t)0x39b42307, (q31_t)0x8dbea09d, (q31_t)0x39ae872f, (q31_t)0x8dbbcba0, (q31_t)0x39a8eb33, (q31_t)0x8db8f6ea, + (q31_t)0x39a34f13, (q31_t)0x8db6227a, (q31_t)0x399db2d0, (q31_t)0x8db34e50, (q31_t)0x3998166a, (q31_t)0x8db07a6d, (q31_t)0x399279e0, (q31_t)0x8dada6d1, + (q31_t)0x398cdd32, (q31_t)0x8daad37b, (q31_t)0x39874061, (q31_t)0x8da8006c, (q31_t)0x3981a36d, (q31_t)0x8da52da3, (q31_t)0x397c0655, (q31_t)0x8da25b21, + (q31_t)0x39766919, (q31_t)0x8d9f88e5, (q31_t)0x3970cbba, (q31_t)0x8d9cb6f0, (q31_t)0x396b2e38, (q31_t)0x8d99e541, (q31_t)0x39659092, (q31_t)0x8d9713d9, + (q31_t)0x395ff2c9, (q31_t)0x8d9442b8, (q31_t)0x395a54dd, (q31_t)0x8d9171dd, (q31_t)0x3954b6cd, (q31_t)0x8d8ea148, (q31_t)0x394f1899, (q31_t)0x8d8bd0fb, + (q31_t)0x39497a43, (q31_t)0x8d8900f3, (q31_t)0x3943dbc9, (q31_t)0x8d863133, (q31_t)0x393e3d2c, (q31_t)0x8d8361b9, (q31_t)0x39389e6b, (q31_t)0x8d809286, + (q31_t)0x3932ff87, (q31_t)0x8d7dc399, (q31_t)0x392d6080, (q31_t)0x8d7af4f3, (q31_t)0x3927c155, (q31_t)0x8d782694, (q31_t)0x39222208, (q31_t)0x8d75587b, + (q31_t)0x391c8297, (q31_t)0x8d728aa9, (q31_t)0x3916e303, (q31_t)0x8d6fbd1d, (q31_t)0x3911434b, (q31_t)0x8d6cefd9, (q31_t)0x390ba371, (q31_t)0x8d6a22db, + (q31_t)0x39060373, (q31_t)0x8d675623, (q31_t)0x39006352, (q31_t)0x8d6489b3, (q31_t)0x38fac30e, (q31_t)0x8d61bd89, (q31_t)0x38f522a6, (q31_t)0x8d5ef1a5, + (q31_t)0x38ef821c, (q31_t)0x8d5c2609, (q31_t)0x38e9e16e, (q31_t)0x8d595ab3, (q31_t)0x38e4409e, (q31_t)0x8d568fa4, (q31_t)0x38de9faa, (q31_t)0x8d53c4db, + (q31_t)0x38d8fe93, (q31_t)0x8d50fa59, (q31_t)0x38d35d59, (q31_t)0x8d4e301f, (q31_t)0x38cdbbfc, (q31_t)0x8d4b662a, (q31_t)0x38c81a7c, (q31_t)0x8d489c7d, + (q31_t)0x38c278d9, (q31_t)0x8d45d316, (q31_t)0x38bcd713, (q31_t)0x8d4309f6, (q31_t)0x38b7352a, (q31_t)0x8d40411d, (q31_t)0x38b1931e, (q31_t)0x8d3d788b, + (q31_t)0x38abf0ef, (q31_t)0x8d3ab03f, (q31_t)0x38a64e9d, (q31_t)0x8d37e83a, (q31_t)0x38a0ac29, (q31_t)0x8d35207d, (q31_t)0x389b0991, (q31_t)0x8d325905, + (q31_t)0x389566d6, (q31_t)0x8d2f91d5, (q31_t)0x388fc3f8, (q31_t)0x8d2ccaec, (q31_t)0x388a20f8, (q31_t)0x8d2a0449, (q31_t)0x38847dd5, (q31_t)0x8d273ded, + (q31_t)0x387eda8e, (q31_t)0x8d2477d8, (q31_t)0x38793725, (q31_t)0x8d21b20a, (q31_t)0x38739399, (q31_t)0x8d1eec83, (q31_t)0x386defeb, (q31_t)0x8d1c2742, + (q31_t)0x38684c19, (q31_t)0x8d196249, (q31_t)0x3862a825, (q31_t)0x8d169d96, (q31_t)0x385d040d, (q31_t)0x8d13d92a, (q31_t)0x38575fd4, (q31_t)0x8d111505, + (q31_t)0x3851bb77, (q31_t)0x8d0e5127, (q31_t)0x384c16f7, (q31_t)0x8d0b8d90, (q31_t)0x38467255, (q31_t)0x8d08ca40, (q31_t)0x3840cd90, (q31_t)0x8d060737, + (q31_t)0x383b28a9, (q31_t)0x8d034474, (q31_t)0x3835839f, (q31_t)0x8d0081f9, (q31_t)0x382fde72, (q31_t)0x8cfdbfc4, (q31_t)0x382a3922, (q31_t)0x8cfafdd7, + (q31_t)0x382493b0, (q31_t)0x8cf83c30, (q31_t)0x381eee1b, (q31_t)0x8cf57ad0, (q31_t)0x38194864, (q31_t)0x8cf2b9b8, (q31_t)0x3813a28a, (q31_t)0x8ceff8e6, + (q31_t)0x380dfc8d, (q31_t)0x8ced385b, (q31_t)0x3808566e, (q31_t)0x8cea7818, (q31_t)0x3802b02c, (q31_t)0x8ce7b81b, (q31_t)0x37fd09c8, (q31_t)0x8ce4f865, + (q31_t)0x37f76341, (q31_t)0x8ce238f6, (q31_t)0x37f1bc97, (q31_t)0x8cdf79ce, (q31_t)0x37ec15cb, (q31_t)0x8cdcbaee, (q31_t)0x37e66edd, (q31_t)0x8cd9fc54, + (q31_t)0x37e0c7cc, (q31_t)0x8cd73e01, (q31_t)0x37db2099, (q31_t)0x8cd47ff6, (q31_t)0x37d57943, (q31_t)0x8cd1c231, (q31_t)0x37cfd1cb, (q31_t)0x8ccf04b3, + (q31_t)0x37ca2a30, (q31_t)0x8ccc477d, (q31_t)0x37c48273, (q31_t)0x8cc98a8e, (q31_t)0x37beda93, (q31_t)0x8cc6cde5, (q31_t)0x37b93292, (q31_t)0x8cc41184, + (q31_t)0x37b38a6d, (q31_t)0x8cc1556a, (q31_t)0x37ade227, (q31_t)0x8cbe9996, (q31_t)0x37a839be, (q31_t)0x8cbbde0a, (q31_t)0x37a29132, (q31_t)0x8cb922c6, + (q31_t)0x379ce885, (q31_t)0x8cb667c8, (q31_t)0x37973fb5, (q31_t)0x8cb3ad11, (q31_t)0x379196c3, (q31_t)0x8cb0f2a1, (q31_t)0x378bedae, (q31_t)0x8cae3879, + (q31_t)0x37864477, (q31_t)0x8cab7e98, (q31_t)0x37809b1e, (q31_t)0x8ca8c4fd, (q31_t)0x377af1a3, (q31_t)0x8ca60baa, (q31_t)0x37754806, (q31_t)0x8ca3529f, + (q31_t)0x376f9e46, (q31_t)0x8ca099da, (q31_t)0x3769f464, (q31_t)0x8c9de15c, (q31_t)0x37644a60, (q31_t)0x8c9b2926, (q31_t)0x375ea03a, (q31_t)0x8c987137, + (q31_t)0x3758f5f2, (q31_t)0x8c95b98f, (q31_t)0x37534b87, (q31_t)0x8c93022e, (q31_t)0x374da0fa, (q31_t)0x8c904b14, (q31_t)0x3747f64c, (q31_t)0x8c8d9442, + (q31_t)0x37424b7b, (q31_t)0x8c8addb7, (q31_t)0x373ca088, (q31_t)0x8c882773, (q31_t)0x3736f573, (q31_t)0x8c857176, (q31_t)0x37314a3c, (q31_t)0x8c82bbc0, + (q31_t)0x372b9ee3, (q31_t)0x8c800652, (q31_t)0x3725f367, (q31_t)0x8c7d512b, (q31_t)0x372047ca, (q31_t)0x8c7a9c4b, (q31_t)0x371a9c0b, (q31_t)0x8c77e7b3, + (q31_t)0x3714f02a, (q31_t)0x8c753362, (q31_t)0x370f4427, (q31_t)0x8c727f58, (q31_t)0x37099802, (q31_t)0x8c6fcb95, (q31_t)0x3703ebbb, (q31_t)0x8c6d181a, + (q31_t)0x36fe3f52, (q31_t)0x8c6a64e5, (q31_t)0x36f892c7, (q31_t)0x8c67b1f9, (q31_t)0x36f2e61a, (q31_t)0x8c64ff53, (q31_t)0x36ed394b, (q31_t)0x8c624cf5, + (q31_t)0x36e78c5b, (q31_t)0x8c5f9ade, (q31_t)0x36e1df48, (q31_t)0x8c5ce90e, (q31_t)0x36dc3214, (q31_t)0x8c5a3786, (q31_t)0x36d684be, (q31_t)0x8c578645, + (q31_t)0x36d0d746, (q31_t)0x8c54d54c, (q31_t)0x36cb29ac, (q31_t)0x8c522499, (q31_t)0x36c57bf0, (q31_t)0x8c4f742f, (q31_t)0x36bfce13, (q31_t)0x8c4cc40b, + (q31_t)0x36ba2014, (q31_t)0x8c4a142f, (q31_t)0x36b471f3, (q31_t)0x8c47649a, (q31_t)0x36aec3b0, (q31_t)0x8c44b54d, (q31_t)0x36a9154c, (q31_t)0x8c420647, + (q31_t)0x36a366c6, (q31_t)0x8c3f5788, (q31_t)0x369db81e, (q31_t)0x8c3ca911, (q31_t)0x36980954, (q31_t)0x8c39fae1, (q31_t)0x36925a69, (q31_t)0x8c374cf9, + (q31_t)0x368cab5c, (q31_t)0x8c349f58, (q31_t)0x3686fc2e, (q31_t)0x8c31f1ff, (q31_t)0x36814cde, (q31_t)0x8c2f44ed, (q31_t)0x367b9d6c, (q31_t)0x8c2c9822, + (q31_t)0x3675edd9, (q31_t)0x8c29eb9f, (q31_t)0x36703e24, (q31_t)0x8c273f63, (q31_t)0x366a8e4d, (q31_t)0x8c24936f, (q31_t)0x3664de55, (q31_t)0x8c21e7c2, + (q31_t)0x365f2e3b, (q31_t)0x8c1f3c5d, (q31_t)0x36597e00, (q31_t)0x8c1c913f, (q31_t)0x3653cda3, (q31_t)0x8c19e669, (q31_t)0x364e1d25, (q31_t)0x8c173bda, + (q31_t)0x36486c86, (q31_t)0x8c149192, (q31_t)0x3642bbc4, (q31_t)0x8c11e792, (q31_t)0x363d0ae2, (q31_t)0x8c0f3dda, (q31_t)0x363759de, (q31_t)0x8c0c9469, + (q31_t)0x3631a8b8, (q31_t)0x8c09eb40, (q31_t)0x362bf771, (q31_t)0x8c07425e, (q31_t)0x36264609, (q31_t)0x8c0499c4, (q31_t)0x3620947f, (q31_t)0x8c01f171, + (q31_t)0x361ae2d3, (q31_t)0x8bff4966, (q31_t)0x36153107, (q31_t)0x8bfca1a3, (q31_t)0x360f7f19, (q31_t)0x8bf9fa27, (q31_t)0x3609cd0a, (q31_t)0x8bf752f2, + (q31_t)0x36041ad9, (q31_t)0x8bf4ac05, (q31_t)0x35fe6887, (q31_t)0x8bf20560, (q31_t)0x35f8b614, (q31_t)0x8bef5f02, (q31_t)0x35f3037f, (q31_t)0x8becb8ec, + (q31_t)0x35ed50c9, (q31_t)0x8bea131e, (q31_t)0x35e79df2, (q31_t)0x8be76d97, (q31_t)0x35e1eafa, (q31_t)0x8be4c857, (q31_t)0x35dc37e0, (q31_t)0x8be22360, + (q31_t)0x35d684a6, (q31_t)0x8bdf7eb0, (q31_t)0x35d0d14a, (q31_t)0x8bdcda47, (q31_t)0x35cb1dcc, (q31_t)0x8bda3626, (q31_t)0x35c56a2e, (q31_t)0x8bd7924d, + (q31_t)0x35bfb66e, (q31_t)0x8bd4eebc, (q31_t)0x35ba028e, (q31_t)0x8bd24b72, (q31_t)0x35b44e8c, (q31_t)0x8bcfa870, (q31_t)0x35ae9a69, (q31_t)0x8bcd05b5, + (q31_t)0x35a8e625, (q31_t)0x8bca6343, (q31_t)0x35a331c0, (q31_t)0x8bc7c117, (q31_t)0x359d7d39, (q31_t)0x8bc51f34, (q31_t)0x3597c892, (q31_t)0x8bc27d98, + (q31_t)0x359213c9, (q31_t)0x8bbfdc44, (q31_t)0x358c5ee0, (q31_t)0x8bbd3b38, (q31_t)0x3586a9d5, (q31_t)0x8bba9a73, (q31_t)0x3580f4aa, (q31_t)0x8bb7f9f6, + (q31_t)0x357b3f5d, (q31_t)0x8bb559c1, (q31_t)0x357589f0, (q31_t)0x8bb2b9d4, (q31_t)0x356fd461, (q31_t)0x8bb01a2e, (q31_t)0x356a1eb2, (q31_t)0x8bad7ad0, + (q31_t)0x356468e2, (q31_t)0x8baadbba, (q31_t)0x355eb2f0, (q31_t)0x8ba83cec, (q31_t)0x3558fcde, (q31_t)0x8ba59e65, (q31_t)0x355346ab, (q31_t)0x8ba30026, + (q31_t)0x354d9057, (q31_t)0x8ba0622f, (q31_t)0x3547d9e2, (q31_t)0x8b9dc480, (q31_t)0x3542234c, (q31_t)0x8b9b2718, (q31_t)0x353c6c95, (q31_t)0x8b9889f8, + (q31_t)0x3536b5be, (q31_t)0x8b95ed21, (q31_t)0x3530fec6, (q31_t)0x8b935090, (q31_t)0x352b47ad, (q31_t)0x8b90b448, (q31_t)0x35259073, (q31_t)0x8b8e1848, + (q31_t)0x351fd918, (q31_t)0x8b8b7c8f, (q31_t)0x351a219c, (q31_t)0x8b88e11e, (q31_t)0x35146a00, (q31_t)0x8b8645f5, (q31_t)0x350eb243, (q31_t)0x8b83ab14, + (q31_t)0x3508fa66, (q31_t)0x8b81107b, (q31_t)0x35034267, (q31_t)0x8b7e7629, (q31_t)0x34fd8a48, (q31_t)0x8b7bdc20, (q31_t)0x34f7d208, (q31_t)0x8b79425e, + (q31_t)0x34f219a8, (q31_t)0x8b76a8e4, (q31_t)0x34ec6127, (q31_t)0x8b740fb3, (q31_t)0x34e6a885, (q31_t)0x8b7176c8, (q31_t)0x34e0efc2, (q31_t)0x8b6ede26, + (q31_t)0x34db36df, (q31_t)0x8b6c45cc, (q31_t)0x34d57ddc, (q31_t)0x8b69adba, (q31_t)0x34cfc4b7, (q31_t)0x8b6715ef, (q31_t)0x34ca0b73, (q31_t)0x8b647e6d, + (q31_t)0x34c4520d, (q31_t)0x8b61e733, (q31_t)0x34be9887, (q31_t)0x8b5f5040, (q31_t)0x34b8dee1, (q31_t)0x8b5cb995, (q31_t)0x34b3251a, (q31_t)0x8b5a2333, + (q31_t)0x34ad6b32, (q31_t)0x8b578d18, (q31_t)0x34a7b12a, (q31_t)0x8b54f745, (q31_t)0x34a1f702, (q31_t)0x8b5261ba, (q31_t)0x349c3cb9, (q31_t)0x8b4fcc77, + (q31_t)0x34968250, (q31_t)0x8b4d377c, (q31_t)0x3490c7c6, (q31_t)0x8b4aa2ca, (q31_t)0x348b0d1c, (q31_t)0x8b480e5f, (q31_t)0x34855251, (q31_t)0x8b457a3c, + (q31_t)0x347f9766, (q31_t)0x8b42e661, (q31_t)0x3479dc5b, (q31_t)0x8b4052ce, (q31_t)0x3474212f, (q31_t)0x8b3dbf83, (q31_t)0x346e65e3, (q31_t)0x8b3b2c80, + (q31_t)0x3468aa76, (q31_t)0x8b3899c6, (q31_t)0x3462eee9, (q31_t)0x8b360753, (q31_t)0x345d333c, (q31_t)0x8b337528, (q31_t)0x3457776f, (q31_t)0x8b30e345, + (q31_t)0x3451bb81, (q31_t)0x8b2e51ab, (q31_t)0x344bff73, (q31_t)0x8b2bc058, (q31_t)0x34464345, (q31_t)0x8b292f4e, (q31_t)0x344086f6, (q31_t)0x8b269e8b, + (q31_t)0x343aca87, (q31_t)0x8b240e11, (q31_t)0x34350df8, (q31_t)0x8b217ddf, (q31_t)0x342f5149, (q31_t)0x8b1eedf4, (q31_t)0x3429947a, (q31_t)0x8b1c5e52, + (q31_t)0x3423d78a, (q31_t)0x8b19cef8, (q31_t)0x341e1a7b, (q31_t)0x8b173fe6, (q31_t)0x34185d4b, (q31_t)0x8b14b11d, (q31_t)0x34129ffb, (q31_t)0x8b12229b, + (q31_t)0x340ce28b, (q31_t)0x8b0f9462, (q31_t)0x340724fb, (q31_t)0x8b0d0670, (q31_t)0x3401674a, (q31_t)0x8b0a78c7, (q31_t)0x33fba97a, (q31_t)0x8b07eb66, + (q31_t)0x33f5eb89, (q31_t)0x8b055e4d, (q31_t)0x33f02d79, (q31_t)0x8b02d17c, (q31_t)0x33ea6f48, (q31_t)0x8b0044f3, (q31_t)0x33e4b0f8, (q31_t)0x8afdb8b3, + (q31_t)0x33def287, (q31_t)0x8afb2cbb, (q31_t)0x33d933f7, (q31_t)0x8af8a10b, (q31_t)0x33d37546, (q31_t)0x8af615a3, (q31_t)0x33cdb676, (q31_t)0x8af38a83, + (q31_t)0x33c7f785, (q31_t)0x8af0ffac, (q31_t)0x33c23875, (q31_t)0x8aee751c, (q31_t)0x33bc7944, (q31_t)0x8aebead5, (q31_t)0x33b6b9f4, (q31_t)0x8ae960d6, + (q31_t)0x33b0fa84, (q31_t)0x8ae6d720, (q31_t)0x33ab3af4, (q31_t)0x8ae44db1, (q31_t)0x33a57b44, (q31_t)0x8ae1c48b, (q31_t)0x339fbb74, (q31_t)0x8adf3bad, + (q31_t)0x3399fb85, (q31_t)0x8adcb318, (q31_t)0x33943b75, (q31_t)0x8ada2aca, (q31_t)0x338e7b46, (q31_t)0x8ad7a2c5, (q31_t)0x3388baf7, (q31_t)0x8ad51b08, + (q31_t)0x3382fa88, (q31_t)0x8ad29394, (q31_t)0x337d39f9, (q31_t)0x8ad00c67, (q31_t)0x3377794b, (q31_t)0x8acd8583, (q31_t)0x3371b87d, (q31_t)0x8acafee8, + (q31_t)0x336bf78f, (q31_t)0x8ac87894, (q31_t)0x33663682, (q31_t)0x8ac5f289, (q31_t)0x33607554, (q31_t)0x8ac36cc6, (q31_t)0x335ab407, (q31_t)0x8ac0e74c, + (q31_t)0x3354f29b, (q31_t)0x8abe6219, (q31_t)0x334f310e, (q31_t)0x8abbdd30, (q31_t)0x33496f62, (q31_t)0x8ab9588e, (q31_t)0x3343ad97, (q31_t)0x8ab6d435, + (q31_t)0x333debab, (q31_t)0x8ab45024, (q31_t)0x333829a1, (q31_t)0x8ab1cc5c, (q31_t)0x33326776, (q31_t)0x8aaf48db, (q31_t)0x332ca52c, (q31_t)0x8aacc5a4, + (q31_t)0x3326e2c3, (q31_t)0x8aaa42b4, (q31_t)0x33212039, (q31_t)0x8aa7c00d, (q31_t)0x331b5d91, (q31_t)0x8aa53daf, (q31_t)0x33159ac8, (q31_t)0x8aa2bb99, + (q31_t)0x330fd7e1, (q31_t)0x8aa039cb, (q31_t)0x330a14da, (q31_t)0x8a9db845, (q31_t)0x330451b3, (q31_t)0x8a9b3708, (q31_t)0x32fe8e6d, (q31_t)0x8a98b614, + (q31_t)0x32f8cb07, (q31_t)0x8a963567, (q31_t)0x32f30782, (q31_t)0x8a93b504, (q31_t)0x32ed43de, (q31_t)0x8a9134e8, (q31_t)0x32e7801a, (q31_t)0x8a8eb516, + (q31_t)0x32e1bc36, (q31_t)0x8a8c358b, (q31_t)0x32dbf834, (q31_t)0x8a89b649, (q31_t)0x32d63412, (q31_t)0x8a873750, (q31_t)0x32d06fd0, (q31_t)0x8a84b89e, + (q31_t)0x32caab6f, (q31_t)0x8a823a36, (q31_t)0x32c4e6ef, (q31_t)0x8a7fbc16, (q31_t)0x32bf2250, (q31_t)0x8a7d3e3e, (q31_t)0x32b95d91, (q31_t)0x8a7ac0af, + (q31_t)0x32b398b3, (q31_t)0x8a784368, (q31_t)0x32add3b6, (q31_t)0x8a75c66a, (q31_t)0x32a80e99, (q31_t)0x8a7349b4, (q31_t)0x32a2495d, (q31_t)0x8a70cd47, + (q31_t)0x329c8402, (q31_t)0x8a6e5123, (q31_t)0x3296be88, (q31_t)0x8a6bd547, (q31_t)0x3290f8ef, (q31_t)0x8a6959b3, (q31_t)0x328b3336, (q31_t)0x8a66de68, + (q31_t)0x32856d5e, (q31_t)0x8a646365, (q31_t)0x327fa767, (q31_t)0x8a61e8ab, (q31_t)0x3279e151, (q31_t)0x8a5f6e3a, (q31_t)0x32741b1c, (q31_t)0x8a5cf411, + (q31_t)0x326e54c7, (q31_t)0x8a5a7a31, (q31_t)0x32688e54, (q31_t)0x8a580099, (q31_t)0x3262c7c1, (q31_t)0x8a55874a, (q31_t)0x325d0110, (q31_t)0x8a530e43, + (q31_t)0x32573a3f, (q31_t)0x8a509585, (q31_t)0x3251734f, (q31_t)0x8a4e1d10, (q31_t)0x324bac40, (q31_t)0x8a4ba4e3, (q31_t)0x3245e512, (q31_t)0x8a492cff, + (q31_t)0x32401dc6, (q31_t)0x8a46b564, (q31_t)0x323a565a, (q31_t)0x8a443e11, (q31_t)0x32348ecf, (q31_t)0x8a41c706, (q31_t)0x322ec725, (q31_t)0x8a3f5045, + (q31_t)0x3228ff5c, (q31_t)0x8a3cd9cc, (q31_t)0x32233775, (q31_t)0x8a3a639b, (q31_t)0x321d6f6e, (q31_t)0x8a37edb3, (q31_t)0x3217a748, (q31_t)0x8a357814, + (q31_t)0x3211df04, (q31_t)0x8a3302be, (q31_t)0x320c16a1, (q31_t)0x8a308db0, (q31_t)0x32064e1e, (q31_t)0x8a2e18eb, (q31_t)0x3200857d, (q31_t)0x8a2ba46e, + (q31_t)0x31fabcbd, (q31_t)0x8a29303b, (q31_t)0x31f4f3df, (q31_t)0x8a26bc50, (q31_t)0x31ef2ae1, (q31_t)0x8a2448ad, (q31_t)0x31e961c5, (q31_t)0x8a21d554, + (q31_t)0x31e39889, (q31_t)0x8a1f6243, (q31_t)0x31ddcf30, (q31_t)0x8a1cef7a, (q31_t)0x31d805b7, (q31_t)0x8a1a7cfb, (q31_t)0x31d23c1f, (q31_t)0x8a180ac4, + (q31_t)0x31cc7269, (q31_t)0x8a1598d6, (q31_t)0x31c6a894, (q31_t)0x8a132731, (q31_t)0x31c0dea1, (q31_t)0x8a10b5d4, (q31_t)0x31bb148f, (q31_t)0x8a0e44c0, + (q31_t)0x31b54a5e, (q31_t)0x8a0bd3f5, (q31_t)0x31af800e, (q31_t)0x8a096373, (q31_t)0x31a9b5a0, (q31_t)0x8a06f339, (q31_t)0x31a3eb13, (q31_t)0x8a048348, + (q31_t)0x319e2067, (q31_t)0x8a0213a0, (q31_t)0x3198559d, (q31_t)0x89ffa441, (q31_t)0x31928ab4, (q31_t)0x89fd352b, (q31_t)0x318cbfad, (q31_t)0x89fac65d, + (q31_t)0x3186f487, (q31_t)0x89f857d8, (q31_t)0x31812943, (q31_t)0x89f5e99c, (q31_t)0x317b5de0, (q31_t)0x89f37ba9, (q31_t)0x3175925e, (q31_t)0x89f10dff, + (q31_t)0x316fc6be, (q31_t)0x89eea09d, (q31_t)0x3169fb00, (q31_t)0x89ec3384, (q31_t)0x31642f23, (q31_t)0x89e9c6b4, (q31_t)0x315e6328, (q31_t)0x89e75a2d, + (q31_t)0x3158970e, (q31_t)0x89e4edef, (q31_t)0x3152cad5, (q31_t)0x89e281fa, (q31_t)0x314cfe7f, (q31_t)0x89e0164d, (q31_t)0x31473209, (q31_t)0x89ddaae9, + (q31_t)0x31416576, (q31_t)0x89db3fcf, (q31_t)0x313b98c4, (q31_t)0x89d8d4fd, (q31_t)0x3135cbf4, (q31_t)0x89d66a74, (q31_t)0x312fff05, (q31_t)0x89d40033, + (q31_t)0x312a31f8, (q31_t)0x89d1963c, (q31_t)0x312464cd, (q31_t)0x89cf2c8e, (q31_t)0x311e9783, (q31_t)0x89ccc328, (q31_t)0x3118ca1b, (q31_t)0x89ca5a0c, + (q31_t)0x3112fc95, (q31_t)0x89c7f138, (q31_t)0x310d2ef0, (q31_t)0x89c588ae, (q31_t)0x3107612e, (q31_t)0x89c3206c, (q31_t)0x3101934d, (q31_t)0x89c0b873, + (q31_t)0x30fbc54d, (q31_t)0x89be50c3, (q31_t)0x30f5f730, (q31_t)0x89bbe95c, (q31_t)0x30f028f4, (q31_t)0x89b9823e, (q31_t)0x30ea5a9a, (q31_t)0x89b71b69, + (q31_t)0x30e48c22, (q31_t)0x89b4b4dd, (q31_t)0x30debd8c, (q31_t)0x89b24e9a, (q31_t)0x30d8eed8, (q31_t)0x89afe8a0, (q31_t)0x30d32006, (q31_t)0x89ad82ef, + (q31_t)0x30cd5115, (q31_t)0x89ab1d87, (q31_t)0x30c78206, (q31_t)0x89a8b868, (q31_t)0x30c1b2da, (q31_t)0x89a65391, (q31_t)0x30bbe38f, (q31_t)0x89a3ef04, + (q31_t)0x30b61426, (q31_t)0x89a18ac0, (q31_t)0x30b0449f, (q31_t)0x899f26c5, (q31_t)0x30aa74fa, (q31_t)0x899cc313, (q31_t)0x30a4a537, (q31_t)0x899a5faa, + (q31_t)0x309ed556, (q31_t)0x8997fc8a, (q31_t)0x30990557, (q31_t)0x899599b3, (q31_t)0x3093353a, (q31_t)0x89933725, (q31_t)0x308d64ff, (q31_t)0x8990d4e0, + (q31_t)0x308794a6, (q31_t)0x898e72e4, (q31_t)0x3081c42f, (q31_t)0x898c1131, (q31_t)0x307bf39b, (q31_t)0x8989afc8, (q31_t)0x307622e8, (q31_t)0x89874ea7, + (q31_t)0x30705217, (q31_t)0x8984edcf, (q31_t)0x306a8129, (q31_t)0x89828d41, (q31_t)0x3064b01d, (q31_t)0x89802cfc, (q31_t)0x305edef3, (q31_t)0x897dccff, + (q31_t)0x30590dab, (q31_t)0x897b6d4c, (q31_t)0x30533c45, (q31_t)0x89790de2, (q31_t)0x304d6ac1, (q31_t)0x8976aec1, (q31_t)0x30479920, (q31_t)0x89744fe9, + (q31_t)0x3041c761, (q31_t)0x8971f15a, (q31_t)0x303bf584, (q31_t)0x896f9315, (q31_t)0x30362389, (q31_t)0x896d3518, (q31_t)0x30305171, (q31_t)0x896ad765, + (q31_t)0x302a7f3a, (q31_t)0x896879fb, (q31_t)0x3024ace6, (q31_t)0x89661cda, (q31_t)0x301eda75, (q31_t)0x8963c002, (q31_t)0x301907e6, (q31_t)0x89616373, + (q31_t)0x30133539, (q31_t)0x895f072e, (q31_t)0x300d626e, (q31_t)0x895cab31, (q31_t)0x30078f86, (q31_t)0x895a4f7e, (q31_t)0x3001bc80, (q31_t)0x8957f414, + (q31_t)0x2ffbe95d, (q31_t)0x895598f3, (q31_t)0x2ff6161c, (q31_t)0x89533e1c, (q31_t)0x2ff042bd, (q31_t)0x8950e38e, (q31_t)0x2fea6f41, (q31_t)0x894e8948, + (q31_t)0x2fe49ba7, (q31_t)0x894c2f4c, (q31_t)0x2fdec7f0, (q31_t)0x8949d59a, (q31_t)0x2fd8f41b, (q31_t)0x89477c30, (q31_t)0x2fd32028, (q31_t)0x89452310, + (q31_t)0x2fcd4c19, (q31_t)0x8942ca39, (q31_t)0x2fc777eb, (q31_t)0x894071ab, (q31_t)0x2fc1a3a0, (q31_t)0x893e1967, (q31_t)0x2fbbcf38, (q31_t)0x893bc16b, + (q31_t)0x2fb5fab2, (q31_t)0x893969b9, (q31_t)0x2fb0260f, (q31_t)0x89371250, (q31_t)0x2faa514f, (q31_t)0x8934bb31, (q31_t)0x2fa47c71, (q31_t)0x8932645b, + (q31_t)0x2f9ea775, (q31_t)0x89300dce, (q31_t)0x2f98d25d, (q31_t)0x892db78a, (q31_t)0x2f92fd26, (q31_t)0x892b6190, (q31_t)0x2f8d27d3, (q31_t)0x89290bdf, + (q31_t)0x2f875262, (q31_t)0x8926b677, (q31_t)0x2f817cd4, (q31_t)0x89246159, (q31_t)0x2f7ba729, (q31_t)0x89220c84, (q31_t)0x2f75d160, (q31_t)0x891fb7f8, + (q31_t)0x2f6ffb7a, (q31_t)0x891d63b5, (q31_t)0x2f6a2577, (q31_t)0x891b0fbc, (q31_t)0x2f644f56, (q31_t)0x8918bc0c, (q31_t)0x2f5e7919, (q31_t)0x891668a6, + (q31_t)0x2f58a2be, (q31_t)0x89141589, (q31_t)0x2f52cc46, (q31_t)0x8911c2b5, (q31_t)0x2f4cf5b0, (q31_t)0x890f702b, (q31_t)0x2f471efe, (q31_t)0x890d1dea, + (q31_t)0x2f41482e, (q31_t)0x890acbf2, (q31_t)0x2f3b7141, (q31_t)0x89087a44, (q31_t)0x2f359a37, (q31_t)0x890628df, (q31_t)0x2f2fc310, (q31_t)0x8903d7c4, + (q31_t)0x2f29ebcc, (q31_t)0x890186f2, (q31_t)0x2f24146b, (q31_t)0x88ff3669, (q31_t)0x2f1e3ced, (q31_t)0x88fce62a, (q31_t)0x2f186551, (q31_t)0x88fa9634, + (q31_t)0x2f128d99, (q31_t)0x88f84687, (q31_t)0x2f0cb5c3, (q31_t)0x88f5f724, (q31_t)0x2f06ddd1, (q31_t)0x88f3a80b, (q31_t)0x2f0105c1, (q31_t)0x88f1593b, + (q31_t)0x2efb2d95, (q31_t)0x88ef0ab4, (q31_t)0x2ef5554b, (q31_t)0x88ecbc77, (q31_t)0x2eef7ce5, (q31_t)0x88ea6e83, (q31_t)0x2ee9a461, (q31_t)0x88e820d9, + (q31_t)0x2ee3cbc1, (q31_t)0x88e5d378, (q31_t)0x2eddf304, (q31_t)0x88e38660, (q31_t)0x2ed81a29, (q31_t)0x88e13992, (q31_t)0x2ed24132, (q31_t)0x88deed0e, + (q31_t)0x2ecc681e, (q31_t)0x88dca0d3, (q31_t)0x2ec68eed, (q31_t)0x88da54e1, (q31_t)0x2ec0b5a0, (q31_t)0x88d8093a, (q31_t)0x2ebadc35, (q31_t)0x88d5bddb, + (q31_t)0x2eb502ae, (q31_t)0x88d372c6, (q31_t)0x2eaf290a, (q31_t)0x88d127fb, (q31_t)0x2ea94f49, (q31_t)0x88cedd79, (q31_t)0x2ea3756b, (q31_t)0x88cc9340, + (q31_t)0x2e9d9b70, (q31_t)0x88ca4951, (q31_t)0x2e97c159, (q31_t)0x88c7ffac, (q31_t)0x2e91e725, (q31_t)0x88c5b650, (q31_t)0x2e8c0cd4, (q31_t)0x88c36d3e, + (q31_t)0x2e863267, (q31_t)0x88c12475, (q31_t)0x2e8057dd, (q31_t)0x88bedbf6, (q31_t)0x2e7a7d36, (q31_t)0x88bc93c0, (q31_t)0x2e74a272, (q31_t)0x88ba4bd4, + (q31_t)0x2e6ec792, (q31_t)0x88b80432, (q31_t)0x2e68ec95, (q31_t)0x88b5bcd9, (q31_t)0x2e63117c, (q31_t)0x88b375ca, (q31_t)0x2e5d3646, (q31_t)0x88b12f04, + (q31_t)0x2e575af3, (q31_t)0x88aee888, (q31_t)0x2e517f84, (q31_t)0x88aca255, (q31_t)0x2e4ba3f8, (q31_t)0x88aa5c6c, (q31_t)0x2e45c850, (q31_t)0x88a816cd, + (q31_t)0x2e3fec8b, (q31_t)0x88a5d177, (q31_t)0x2e3a10aa, (q31_t)0x88a38c6b, (q31_t)0x2e3434ac, (q31_t)0x88a147a9, (q31_t)0x2e2e5891, (q31_t)0x889f0330, + (q31_t)0x2e287c5a, (q31_t)0x889cbf01, (q31_t)0x2e22a007, (q31_t)0x889a7b1b, (q31_t)0x2e1cc397, (q31_t)0x88983780, (q31_t)0x2e16e70b, (q31_t)0x8895f42d, + (q31_t)0x2e110a62, (q31_t)0x8893b125, (q31_t)0x2e0b2d9d, (q31_t)0x88916e66, (q31_t)0x2e0550bb, (q31_t)0x888f2bf1, (q31_t)0x2dff73bd, (q31_t)0x888ce9c5, + (q31_t)0x2df996a3, (q31_t)0x888aa7e3, (q31_t)0x2df3b96c, (q31_t)0x8888664b, (q31_t)0x2deddc19, (q31_t)0x888624fd, (q31_t)0x2de7feaa, (q31_t)0x8883e3f8, + (q31_t)0x2de2211e, (q31_t)0x8881a33d, (q31_t)0x2ddc4376, (q31_t)0x887f62cb, (q31_t)0x2dd665b2, (q31_t)0x887d22a4, (q31_t)0x2dd087d1, (q31_t)0x887ae2c6, + (q31_t)0x2dcaa9d5, (q31_t)0x8878a332, (q31_t)0x2dc4cbbc, (q31_t)0x887663e7, (q31_t)0x2dbeed86, (q31_t)0x887424e7, (q31_t)0x2db90f35, (q31_t)0x8871e630, + (q31_t)0x2db330c7, (q31_t)0x886fa7c2, (q31_t)0x2dad523d, (q31_t)0x886d699f, (q31_t)0x2da77397, (q31_t)0x886b2bc5, (q31_t)0x2da194d5, (q31_t)0x8868ee35, + (q31_t)0x2d9bb5f6, (q31_t)0x8866b0ef, (q31_t)0x2d95d6fc, (q31_t)0x886473f2, (q31_t)0x2d8ff7e5, (q31_t)0x88623740, (q31_t)0x2d8a18b3, (q31_t)0x885ffad7, + (q31_t)0x2d843964, (q31_t)0x885dbeb8, (q31_t)0x2d7e59f9, (q31_t)0x885b82e3, (q31_t)0x2d787a72, (q31_t)0x88594757, (q31_t)0x2d729acf, (q31_t)0x88570c16, + (q31_t)0x2d6cbb10, (q31_t)0x8854d11e, (q31_t)0x2d66db35, (q31_t)0x88529670, (q31_t)0x2d60fb3e, (q31_t)0x88505c0b, (q31_t)0x2d5b1b2b, (q31_t)0x884e21f1, + (q31_t)0x2d553afc, (q31_t)0x884be821, (q31_t)0x2d4f5ab1, (q31_t)0x8849ae9a, (q31_t)0x2d497a4a, (q31_t)0x8847755d, (q31_t)0x2d4399c7, (q31_t)0x88453c6a, + (q31_t)0x2d3db928, (q31_t)0x884303c1, (q31_t)0x2d37d86d, (q31_t)0x8840cb61, (q31_t)0x2d31f797, (q31_t)0x883e934c, (q31_t)0x2d2c16a4, (q31_t)0x883c5b81, + (q31_t)0x2d263596, (q31_t)0x883a23ff, (q31_t)0x2d20546b, (q31_t)0x8837ecc7, (q31_t)0x2d1a7325, (q31_t)0x8835b5d9, (q31_t)0x2d1491c4, (q31_t)0x88337f35, + (q31_t)0x2d0eb046, (q31_t)0x883148db, (q31_t)0x2d08ceac, (q31_t)0x882f12cb, (q31_t)0x2d02ecf7, (q31_t)0x882cdd04, (q31_t)0x2cfd0b26, (q31_t)0x882aa788, + (q31_t)0x2cf72939, (q31_t)0x88287256, (q31_t)0x2cf14731, (q31_t)0x88263d6d, (q31_t)0x2ceb650d, (q31_t)0x882408ce, (q31_t)0x2ce582cd, (q31_t)0x8821d47a, + (q31_t)0x2cdfa071, (q31_t)0x881fa06f, (q31_t)0x2cd9bdfa, (q31_t)0x881d6cae, (q31_t)0x2cd3db67, (q31_t)0x881b3937, (q31_t)0x2ccdf8b8, (q31_t)0x8819060a, + (q31_t)0x2cc815ee, (q31_t)0x8816d327, (q31_t)0x2cc23308, (q31_t)0x8814a08f, (q31_t)0x2cbc5006, (q31_t)0x88126e40, (q31_t)0x2cb66ce9, (q31_t)0x88103c3b, + (q31_t)0x2cb089b1, (q31_t)0x880e0a7f, (q31_t)0x2caaa65c, (q31_t)0x880bd90e, (q31_t)0x2ca4c2ed, (q31_t)0x8809a7e7, (q31_t)0x2c9edf61, (q31_t)0x8807770a, + (q31_t)0x2c98fbba, (q31_t)0x88054677, (q31_t)0x2c9317f8, (q31_t)0x8803162e, (q31_t)0x2c8d341a, (q31_t)0x8800e62f, (q31_t)0x2c875021, (q31_t)0x87feb67a, + (q31_t)0x2c816c0c, (q31_t)0x87fc870f, (q31_t)0x2c7b87dc, (q31_t)0x87fa57ee, (q31_t)0x2c75a390, (q31_t)0x87f82917, (q31_t)0x2c6fbf29, (q31_t)0x87f5fa8b, + (q31_t)0x2c69daa6, (q31_t)0x87f3cc48, (q31_t)0x2c63f609, (q31_t)0x87f19e4f, (q31_t)0x2c5e114f, (q31_t)0x87ef70a0, (q31_t)0x2c582c7b, (q31_t)0x87ed433c, + (q31_t)0x2c52478a, (q31_t)0x87eb1621, (q31_t)0x2c4c627f, (q31_t)0x87e8e950, (q31_t)0x2c467d58, (q31_t)0x87e6bcca, (q31_t)0x2c409816, (q31_t)0x87e4908e, + (q31_t)0x2c3ab2b9, (q31_t)0x87e2649b, (q31_t)0x2c34cd40, (q31_t)0x87e038f3, (q31_t)0x2c2ee7ad, (q31_t)0x87de0d95, (q31_t)0x2c2901fd, (q31_t)0x87dbe281, + (q31_t)0x2c231c33, (q31_t)0x87d9b7b7, (q31_t)0x2c1d364e, (q31_t)0x87d78d38, (q31_t)0x2c17504d, (q31_t)0x87d56302, (q31_t)0x2c116a31, (q31_t)0x87d33916, + (q31_t)0x2c0b83fa, (q31_t)0x87d10f75, (q31_t)0x2c059da7, (q31_t)0x87cee61e, (q31_t)0x2bffb73a, (q31_t)0x87ccbd11, (q31_t)0x2bf9d0b1, (q31_t)0x87ca944e, + (q31_t)0x2bf3ea0d, (q31_t)0x87c86bd5, (q31_t)0x2bee034e, (q31_t)0x87c643a6, (q31_t)0x2be81c74, (q31_t)0x87c41bc2, (q31_t)0x2be2357f, (q31_t)0x87c1f427, + (q31_t)0x2bdc4e6f, (q31_t)0x87bfccd7, (q31_t)0x2bd66744, (q31_t)0x87bda5d1, (q31_t)0x2bd07ffe, (q31_t)0x87bb7f16, (q31_t)0x2bca989d, (q31_t)0x87b958a4, + (q31_t)0x2bc4b120, (q31_t)0x87b7327d, (q31_t)0x2bbec989, (q31_t)0x87b50c9f, (q31_t)0x2bb8e1d7, (q31_t)0x87b2e70c, (q31_t)0x2bb2fa0a, (q31_t)0x87b0c1c4, + (q31_t)0x2bad1221, (q31_t)0x87ae9cc5, (q31_t)0x2ba72a1e, (q31_t)0x87ac7811, (q31_t)0x2ba14200, (q31_t)0x87aa53a6, (q31_t)0x2b9b59c7, (q31_t)0x87a82f87, + (q31_t)0x2b957173, (q31_t)0x87a60bb1, (q31_t)0x2b8f8905, (q31_t)0x87a3e825, (q31_t)0x2b89a07b, (q31_t)0x87a1c4e4, (q31_t)0x2b83b7d7, (q31_t)0x879fa1ed, + (q31_t)0x2b7dcf17, (q31_t)0x879d7f41, (q31_t)0x2b77e63d, (q31_t)0x879b5cde, (q31_t)0x2b71fd48, (q31_t)0x87993ac6, (q31_t)0x2b6c1438, (q31_t)0x879718f8, + (q31_t)0x2b662b0e, (q31_t)0x8794f774, (q31_t)0x2b6041c9, (q31_t)0x8792d63b, (q31_t)0x2b5a5868, (q31_t)0x8790b54c, (q31_t)0x2b546eee, (q31_t)0x878e94a7, + (q31_t)0x2b4e8558, (q31_t)0x878c744d, (q31_t)0x2b489ba8, (q31_t)0x878a543d, (q31_t)0x2b42b1dd, (q31_t)0x87883477, (q31_t)0x2b3cc7f7, (q31_t)0x878614fb, + (q31_t)0x2b36ddf7, (q31_t)0x8783f5ca, (q31_t)0x2b30f3dc, (q31_t)0x8781d6e3, (q31_t)0x2b2b09a6, (q31_t)0x877fb846, (q31_t)0x2b251f56, (q31_t)0x877d99f4, + (q31_t)0x2b1f34eb, (q31_t)0x877b7bec, (q31_t)0x2b194a66, (q31_t)0x87795e2f, (q31_t)0x2b135fc6, (q31_t)0x877740bb, (q31_t)0x2b0d750b, (q31_t)0x87752392, + (q31_t)0x2b078a36, (q31_t)0x877306b4, (q31_t)0x2b019f46, (q31_t)0x8770ea20, (q31_t)0x2afbb43c, (q31_t)0x876ecdd6, (q31_t)0x2af5c917, (q31_t)0x876cb1d6, + (q31_t)0x2aefddd8, (q31_t)0x876a9621, (q31_t)0x2ae9f27e, (q31_t)0x87687ab7, (q31_t)0x2ae4070a, (q31_t)0x87665f96, (q31_t)0x2ade1b7c, (q31_t)0x876444c1, + (q31_t)0x2ad82fd2, (q31_t)0x87622a35, (q31_t)0x2ad2440f, (q31_t)0x87600ff4, (q31_t)0x2acc5831, (q31_t)0x875df5fd, (q31_t)0x2ac66c39, (q31_t)0x875bdc51, + (q31_t)0x2ac08026, (q31_t)0x8759c2ef, (q31_t)0x2aba93f9, (q31_t)0x8757a9d8, (q31_t)0x2ab4a7b1, (q31_t)0x8755910b, (q31_t)0x2aaebb50, (q31_t)0x87537888, + (q31_t)0x2aa8ced3, (q31_t)0x87516050, (q31_t)0x2aa2e23d, (q31_t)0x874f4862, (q31_t)0x2a9cf58c, (q31_t)0x874d30bf, (q31_t)0x2a9708c1, (q31_t)0x874b1966, + (q31_t)0x2a911bdc, (q31_t)0x87490258, (q31_t)0x2a8b2edc, (q31_t)0x8746eb94, (q31_t)0x2a8541c3, (q31_t)0x8744d51b, (q31_t)0x2a7f548e, (q31_t)0x8742beec, + (q31_t)0x2a796740, (q31_t)0x8740a907, (q31_t)0x2a7379d8, (q31_t)0x873e936d, (q31_t)0x2a6d8c55, (q31_t)0x873c7e1e, (q31_t)0x2a679eb8, (q31_t)0x873a6919, + (q31_t)0x2a61b101, (q31_t)0x8738545e, (q31_t)0x2a5bc330, (q31_t)0x87363fee, (q31_t)0x2a55d545, (q31_t)0x87342bc9, (q31_t)0x2a4fe740, (q31_t)0x873217ee, + (q31_t)0x2a49f920, (q31_t)0x8730045d, (q31_t)0x2a440ae7, (q31_t)0x872df117, (q31_t)0x2a3e1c93, (q31_t)0x872bde1c, (q31_t)0x2a382e25, (q31_t)0x8729cb6b, + (q31_t)0x2a323f9e, (q31_t)0x8727b905, (q31_t)0x2a2c50fc, (q31_t)0x8725a6e9, (q31_t)0x2a266240, (q31_t)0x87239518, (q31_t)0x2a20736a, (q31_t)0x87218391, + (q31_t)0x2a1a847b, (q31_t)0x871f7255, (q31_t)0x2a149571, (q31_t)0x871d6163, (q31_t)0x2a0ea64d, (q31_t)0x871b50bc, (q31_t)0x2a08b710, (q31_t)0x87194060, + (q31_t)0x2a02c7b8, (q31_t)0x8717304e, (q31_t)0x29fcd847, (q31_t)0x87152087, (q31_t)0x29f6e8bb, (q31_t)0x8713110a, (q31_t)0x29f0f916, (q31_t)0x871101d8, + (q31_t)0x29eb0957, (q31_t)0x870ef2f1, (q31_t)0x29e5197e, (q31_t)0x870ce454, (q31_t)0x29df298b, (q31_t)0x870ad602, (q31_t)0x29d9397f, (q31_t)0x8708c7fa, + (q31_t)0x29d34958, (q31_t)0x8706ba3d, (q31_t)0x29cd5918, (q31_t)0x8704acca, (q31_t)0x29c768be, (q31_t)0x87029fa3, (q31_t)0x29c1784a, (q31_t)0x870092c5, + (q31_t)0x29bb87bc, (q31_t)0x86fe8633, (q31_t)0x29b59715, (q31_t)0x86fc79eb, (q31_t)0x29afa654, (q31_t)0x86fa6dee, (q31_t)0x29a9b579, (q31_t)0x86f8623b, + (q31_t)0x29a3c485, (q31_t)0x86f656d3, (q31_t)0x299dd377, (q31_t)0x86f44bb6, (q31_t)0x2997e24f, (q31_t)0x86f240e3, (q31_t)0x2991f10e, (q31_t)0x86f0365c, + (q31_t)0x298bffb2, (q31_t)0x86ee2c1e, (q31_t)0x29860e3e, (q31_t)0x86ec222c, (q31_t)0x29801caf, (q31_t)0x86ea1884, (q31_t)0x297a2b07, (q31_t)0x86e80f27, + (q31_t)0x29743946, (q31_t)0x86e60614, (q31_t)0x296e476b, (q31_t)0x86e3fd4c, (q31_t)0x29685576, (q31_t)0x86e1f4cf, (q31_t)0x29626368, (q31_t)0x86dfec9d, + (q31_t)0x295c7140, (q31_t)0x86dde4b5, (q31_t)0x29567eff, (q31_t)0x86dbdd18, (q31_t)0x29508ca4, (q31_t)0x86d9d5c6, (q31_t)0x294a9a30, (q31_t)0x86d7cebf, + (q31_t)0x2944a7a2, (q31_t)0x86d5c802, (q31_t)0x293eb4fb, (q31_t)0x86d3c190, (q31_t)0x2938c23a, (q31_t)0x86d1bb69, (q31_t)0x2932cf60, (q31_t)0x86cfb58c, + (q31_t)0x292cdc6d, (q31_t)0x86cdaffa, (q31_t)0x2926e960, (q31_t)0x86cbaab3, (q31_t)0x2920f63a, (q31_t)0x86c9a5b7, (q31_t)0x291b02fa, (q31_t)0x86c7a106, + (q31_t)0x29150fa1, (q31_t)0x86c59c9f, (q31_t)0x290f1c2f, (q31_t)0x86c39883, (q31_t)0x290928a3, (q31_t)0x86c194b2, (q31_t)0x290334ff, (q31_t)0x86bf912c, + (q31_t)0x28fd4140, (q31_t)0x86bd8df0, (q31_t)0x28f74d69, (q31_t)0x86bb8b00, (q31_t)0x28f15978, (q31_t)0x86b9885a, (q31_t)0x28eb656e, (q31_t)0x86b785ff, + (q31_t)0x28e5714b, (q31_t)0x86b583ee, (q31_t)0x28df7d0e, (q31_t)0x86b38229, (q31_t)0x28d988b8, (q31_t)0x86b180ae, (q31_t)0x28d3944a, (q31_t)0x86af7f7e, + (q31_t)0x28cd9fc1, (q31_t)0x86ad7e99, (q31_t)0x28c7ab20, (q31_t)0x86ab7dff, (q31_t)0x28c1b666, (q31_t)0x86a97db0, (q31_t)0x28bbc192, (q31_t)0x86a77dab, + (q31_t)0x28b5cca5, (q31_t)0x86a57df2, (q31_t)0x28afd7a0, (q31_t)0x86a37e83, (q31_t)0x28a9e281, (q31_t)0x86a17f5f, (q31_t)0x28a3ed49, (q31_t)0x869f8086, + (q31_t)0x289df7f8, (q31_t)0x869d81f8, (q31_t)0x2898028e, (q31_t)0x869b83b4, (q31_t)0x28920d0a, (q31_t)0x869985bc, (q31_t)0x288c176e, (q31_t)0x8697880f, + (q31_t)0x288621b9, (q31_t)0x86958aac, (q31_t)0x28802beb, (q31_t)0x86938d94, (q31_t)0x287a3604, (q31_t)0x869190c7, (q31_t)0x28744004, (q31_t)0x868f9445, + (q31_t)0x286e49ea, (q31_t)0x868d980e, (q31_t)0x286853b8, (q31_t)0x868b9c22, (q31_t)0x28625d6d, (q31_t)0x8689a081, (q31_t)0x285c670a, (q31_t)0x8687a52b, + (q31_t)0x2856708d, (q31_t)0x8685aa20, (q31_t)0x285079f7, (q31_t)0x8683af5f, (q31_t)0x284a8349, (q31_t)0x8681b4ea, (q31_t)0x28448c81, (q31_t)0x867fbabf, + (q31_t)0x283e95a1, (q31_t)0x867dc0e0, (q31_t)0x28389ea8, (q31_t)0x867bc74b, (q31_t)0x2832a796, (q31_t)0x8679ce01, (q31_t)0x282cb06c, (q31_t)0x8677d503, + (q31_t)0x2826b928, (q31_t)0x8675dc4f, (q31_t)0x2820c1cc, (q31_t)0x8673e3e6, (q31_t)0x281aca57, (q31_t)0x8671ebc8, (q31_t)0x2814d2c9, (q31_t)0x866ff3f6, + (q31_t)0x280edb23, (q31_t)0x866dfc6e, (q31_t)0x2808e364, (q31_t)0x866c0531, (q31_t)0x2802eb8c, (q31_t)0x866a0e3f, (q31_t)0x27fcf39c, (q31_t)0x86681798, + (q31_t)0x27f6fb92, (q31_t)0x8666213c, (q31_t)0x27f10371, (q31_t)0x86642b2c, (q31_t)0x27eb0b36, (q31_t)0x86623566, (q31_t)0x27e512e3, (q31_t)0x86603feb, + (q31_t)0x27df1a77, (q31_t)0x865e4abb, (q31_t)0x27d921f3, (q31_t)0x865c55d7, (q31_t)0x27d32956, (q31_t)0x865a613d, (q31_t)0x27cd30a1, (q31_t)0x86586cee, + (q31_t)0x27c737d3, (q31_t)0x865678eb, (q31_t)0x27c13eec, (q31_t)0x86548532, (q31_t)0x27bb45ed, (q31_t)0x865291c4, (q31_t)0x27b54cd6, (q31_t)0x86509ea2, + (q31_t)0x27af53a6, (q31_t)0x864eabcb, (q31_t)0x27a95a5d, (q31_t)0x864cb93e, (q31_t)0x27a360fc, (q31_t)0x864ac6fd, (q31_t)0x279d6783, (q31_t)0x8648d507, + (q31_t)0x27976df1, (q31_t)0x8646e35c, (q31_t)0x27917447, (q31_t)0x8644f1fc, (q31_t)0x278b7a84, (q31_t)0x864300e7, (q31_t)0x278580a9, (q31_t)0x8641101d, + (q31_t)0x277f86b5, (q31_t)0x863f1f9e, (q31_t)0x27798caa, (q31_t)0x863d2f6b, (q31_t)0x27739285, (q31_t)0x863b3f82, (q31_t)0x276d9849, (q31_t)0x86394fe5, + (q31_t)0x27679df4, (q31_t)0x86376092, (q31_t)0x2761a387, (q31_t)0x8635718b, (q31_t)0x275ba901, (q31_t)0x863382cf, (q31_t)0x2755ae64, (q31_t)0x8631945e, + (q31_t)0x274fb3ae, (q31_t)0x862fa638, (q31_t)0x2749b8e0, (q31_t)0x862db85e, (q31_t)0x2743bdf9, (q31_t)0x862bcace, (q31_t)0x273dc2fa, (q31_t)0x8629dd8a, + (q31_t)0x2737c7e3, (q31_t)0x8627f091, (q31_t)0x2731ccb4, (q31_t)0x862603e3, (q31_t)0x272bd16d, (q31_t)0x86241780, (q31_t)0x2725d60e, (q31_t)0x86222b68, + (q31_t)0x271fda96, (q31_t)0x86203f9c, (q31_t)0x2719df06, (q31_t)0x861e541a, (q31_t)0x2713e35f, (q31_t)0x861c68e4, (q31_t)0x270de79f, (q31_t)0x861a7df9, + (q31_t)0x2707ebc7, (q31_t)0x86189359, (q31_t)0x2701efd7, (q31_t)0x8616a905, (q31_t)0x26fbf3ce, (q31_t)0x8614befb, (q31_t)0x26f5f7ae, (q31_t)0x8612d53d, + (q31_t)0x26effb76, (q31_t)0x8610ebca, (q31_t)0x26e9ff26, (q31_t)0x860f02a3, (q31_t)0x26e402bd, (q31_t)0x860d19c6, (q31_t)0x26de063d, (q31_t)0x860b3135, + (q31_t)0x26d809a5, (q31_t)0x860948ef, (q31_t)0x26d20cf5, (q31_t)0x860760f4, (q31_t)0x26cc102d, (q31_t)0x86057944, (q31_t)0x26c6134d, (q31_t)0x860391e0, + (q31_t)0x26c01655, (q31_t)0x8601aac7, (q31_t)0x26ba1945, (q31_t)0x85ffc3f9, (q31_t)0x26b41c1d, (q31_t)0x85fddd76, (q31_t)0x26ae1edd, (q31_t)0x85fbf73f, + (q31_t)0x26a82186, (q31_t)0x85fa1153, (q31_t)0x26a22416, (q31_t)0x85f82bb2, (q31_t)0x269c268f, (q31_t)0x85f6465c, (q31_t)0x269628f0, (q31_t)0x85f46152, + (q31_t)0x26902b39, (q31_t)0x85f27c93, (q31_t)0x268a2d6b, (q31_t)0x85f09820, (q31_t)0x26842f84, (q31_t)0x85eeb3f7, (q31_t)0x267e3186, (q31_t)0x85ecd01a, + (q31_t)0x26783370, (q31_t)0x85eaec88, (q31_t)0x26723543, (q31_t)0x85e90942, (q31_t)0x266c36fe, (q31_t)0x85e72647, (q31_t)0x266638a1, (q31_t)0x85e54397, + (q31_t)0x26603a2c, (q31_t)0x85e36132, (q31_t)0x265a3b9f, (q31_t)0x85e17f19, (q31_t)0x26543cfb, (q31_t)0x85df9d4b, (q31_t)0x264e3e40, (q31_t)0x85ddbbc9, + (q31_t)0x26483f6c, (q31_t)0x85dbda91, (q31_t)0x26424082, (q31_t)0x85d9f9a5, (q31_t)0x263c417f, (q31_t)0x85d81905, (q31_t)0x26364265, (q31_t)0x85d638b0, + (q31_t)0x26304333, (q31_t)0x85d458a6, (q31_t)0x262a43ea, (q31_t)0x85d278e7, (q31_t)0x26244489, (q31_t)0x85d09974, (q31_t)0x261e4511, (q31_t)0x85ceba4d, + (q31_t)0x26184581, (q31_t)0x85ccdb70, (q31_t)0x261245da, (q31_t)0x85cafcdf, (q31_t)0x260c461b, (q31_t)0x85c91e9a, (q31_t)0x26064645, (q31_t)0x85c740a0, + (q31_t)0x26004657, (q31_t)0x85c562f1, (q31_t)0x25fa4652, (q31_t)0x85c3858d, (q31_t)0x25f44635, (q31_t)0x85c1a875, (q31_t)0x25ee4601, (q31_t)0x85bfcba9, + (q31_t)0x25e845b6, (q31_t)0x85bdef28, (q31_t)0x25e24553, (q31_t)0x85bc12f2, (q31_t)0x25dc44d9, (q31_t)0x85ba3707, (q31_t)0x25d64447, (q31_t)0x85b85b68, + (q31_t)0x25d0439f, (q31_t)0x85b68015, (q31_t)0x25ca42de, (q31_t)0x85b4a50d, (q31_t)0x25c44207, (q31_t)0x85b2ca50, (q31_t)0x25be4118, (q31_t)0x85b0efdf, + (q31_t)0x25b84012, (q31_t)0x85af15b9, (q31_t)0x25b23ef5, (q31_t)0x85ad3bdf, (q31_t)0x25ac3dc0, (q31_t)0x85ab6250, (q31_t)0x25a63c74, (q31_t)0x85a9890d, + (q31_t)0x25a03b11, (q31_t)0x85a7b015, (q31_t)0x259a3997, (q31_t)0x85a5d768, (q31_t)0x25943806, (q31_t)0x85a3ff07, (q31_t)0x258e365d, (q31_t)0x85a226f2, + (q31_t)0x2588349d, (q31_t)0x85a04f28, (q31_t)0x258232c6, (q31_t)0x859e77a9, (q31_t)0x257c30d8, (q31_t)0x859ca076, (q31_t)0x25762ed3, (q31_t)0x859ac98f, + (q31_t)0x25702cb7, (q31_t)0x8598f2f3, (q31_t)0x256a2a83, (q31_t)0x85971ca2, (q31_t)0x25642839, (q31_t)0x8595469d, (q31_t)0x255e25d7, (q31_t)0x859370e4, + (q31_t)0x2558235f, (q31_t)0x85919b76, (q31_t)0x255220cf, (q31_t)0x858fc653, (q31_t)0x254c1e28, (q31_t)0x858df17c, (q31_t)0x25461b6b, (q31_t)0x858c1cf1, + (q31_t)0x25401896, (q31_t)0x858a48b1, (q31_t)0x253a15aa, (q31_t)0x858874bd, (q31_t)0x253412a8, (q31_t)0x8586a114, (q31_t)0x252e0f8e, (q31_t)0x8584cdb7, + (q31_t)0x25280c5e, (q31_t)0x8582faa5, (q31_t)0x25220916, (q31_t)0x858127df, (q31_t)0x251c05b8, (q31_t)0x857f5564, (q31_t)0x25160243, (q31_t)0x857d8335, + (q31_t)0x250ffeb7, (q31_t)0x857bb152, (q31_t)0x2509fb14, (q31_t)0x8579dfba, (q31_t)0x2503f75a, (q31_t)0x85780e6e, (q31_t)0x24fdf389, (q31_t)0x85763d6d, + (q31_t)0x24f7efa2, (q31_t)0x85746cb8, (q31_t)0x24f1eba4, (q31_t)0x85729c4e, (q31_t)0x24ebe78f, (q31_t)0x8570cc30, (q31_t)0x24e5e363, (q31_t)0x856efc5e, + (q31_t)0x24dfdf20, (q31_t)0x856d2cd7, (q31_t)0x24d9dac7, (q31_t)0x856b5d9c, (q31_t)0x24d3d657, (q31_t)0x85698ead, (q31_t)0x24cdd1d0, (q31_t)0x8567c009, + (q31_t)0x24c7cd33, (q31_t)0x8565f1b0, (q31_t)0x24c1c87f, (q31_t)0x856423a4, (q31_t)0x24bbc3b4, (q31_t)0x856255e3, (q31_t)0x24b5bed2, (q31_t)0x8560886d, + (q31_t)0x24afb9da, (q31_t)0x855ebb44, (q31_t)0x24a9b4cb, (q31_t)0x855cee66, (q31_t)0x24a3afa6, (q31_t)0x855b21d3, (q31_t)0x249daa6a, (q31_t)0x8559558c, + (q31_t)0x2497a517, (q31_t)0x85578991, (q31_t)0x24919fae, (q31_t)0x8555bde2, (q31_t)0x248b9a2f, (q31_t)0x8553f27e, (q31_t)0x24859498, (q31_t)0x85522766, + (q31_t)0x247f8eec, (q31_t)0x85505c99, (q31_t)0x24798928, (q31_t)0x854e9219, (q31_t)0x2473834f, (q31_t)0x854cc7e3, (q31_t)0x246d7d5e, (q31_t)0x854afdfa, + (q31_t)0x24677758, (q31_t)0x8549345c, (q31_t)0x2461713a, (q31_t)0x85476b0a, (q31_t)0x245b6b07, (q31_t)0x8545a204, (q31_t)0x245564bd, (q31_t)0x8543d949, + (q31_t)0x244f5e5c, (q31_t)0x854210db, (q31_t)0x244957e5, (q31_t)0x854048b7, (q31_t)0x24435158, (q31_t)0x853e80e0, (q31_t)0x243d4ab4, (q31_t)0x853cb954, + (q31_t)0x243743fa, (q31_t)0x853af214, (q31_t)0x24313d2a, (q31_t)0x85392b20, (q31_t)0x242b3644, (q31_t)0x85376477, (q31_t)0x24252f47, (q31_t)0x85359e1a, + (q31_t)0x241f2833, (q31_t)0x8533d809, (q31_t)0x2419210a, (q31_t)0x85321244, (q31_t)0x241319ca, (q31_t)0x85304cca, (q31_t)0x240d1274, (q31_t)0x852e879d, + (q31_t)0x24070b08, (q31_t)0x852cc2bb, (q31_t)0x24010385, (q31_t)0x852afe24, (q31_t)0x23fafbec, (q31_t)0x852939da, (q31_t)0x23f4f43e, (q31_t)0x852775db, + (q31_t)0x23eeec78, (q31_t)0x8525b228, (q31_t)0x23e8e49d, (q31_t)0x8523eec1, (q31_t)0x23e2dcac, (q31_t)0x85222ba5, (q31_t)0x23dcd4a4, (q31_t)0x852068d6, + (q31_t)0x23d6cc87, (q31_t)0x851ea652, (q31_t)0x23d0c453, (q31_t)0x851ce41a, (q31_t)0x23cabc09, (q31_t)0x851b222e, (q31_t)0x23c4b3a9, (q31_t)0x8519608d, + (q31_t)0x23beab33, (q31_t)0x85179f39, (q31_t)0x23b8a2a7, (q31_t)0x8515de30, (q31_t)0x23b29a05, (q31_t)0x85141d73, (q31_t)0x23ac914d, (q31_t)0x85125d02, + (q31_t)0x23a6887f, (q31_t)0x85109cdd, (q31_t)0x23a07f9a, (q31_t)0x850edd03, (q31_t)0x239a76a0, (q31_t)0x850d1d75, (q31_t)0x23946d90, (q31_t)0x850b5e34, + (q31_t)0x238e646a, (q31_t)0x85099f3e, (q31_t)0x23885b2e, (q31_t)0x8507e094, (q31_t)0x238251dd, (q31_t)0x85062235, (q31_t)0x237c4875, (q31_t)0x85046423, + (q31_t)0x23763ef7, (q31_t)0x8502a65c, (q31_t)0x23703564, (q31_t)0x8500e8e2, (q31_t)0x236a2bba, (q31_t)0x84ff2bb3, (q31_t)0x236421fb, (q31_t)0x84fd6ed0, + (q31_t)0x235e1826, (q31_t)0x84fbb239, (q31_t)0x23580e3b, (q31_t)0x84f9f5ee, (q31_t)0x2352043b, (q31_t)0x84f839ee, (q31_t)0x234bfa24, (q31_t)0x84f67e3b, + (q31_t)0x2345eff8, (q31_t)0x84f4c2d4, (q31_t)0x233fe5b6, (q31_t)0x84f307b8, (q31_t)0x2339db5e, (q31_t)0x84f14ce8, (q31_t)0x2333d0f1, (q31_t)0x84ef9265, + (q31_t)0x232dc66d, (q31_t)0x84edd82d, (q31_t)0x2327bbd5, (q31_t)0x84ec1e41, (q31_t)0x2321b126, (q31_t)0x84ea64a1, (q31_t)0x231ba662, (q31_t)0x84e8ab4d, + (q31_t)0x23159b88, (q31_t)0x84e6f244, (q31_t)0x230f9098, (q31_t)0x84e53988, (q31_t)0x23098593, (q31_t)0x84e38118, (q31_t)0x23037a78, (q31_t)0x84e1c8f3, + (q31_t)0x22fd6f48, (q31_t)0x84e0111b, (q31_t)0x22f76402, (q31_t)0x84de598f, (q31_t)0x22f158a7, (q31_t)0x84dca24e, (q31_t)0x22eb4d36, (q31_t)0x84daeb5a, + (q31_t)0x22e541af, (q31_t)0x84d934b1, (q31_t)0x22df3613, (q31_t)0x84d77e54, (q31_t)0x22d92a61, (q31_t)0x84d5c844, (q31_t)0x22d31e9a, (q31_t)0x84d4127f, + (q31_t)0x22cd12bd, (q31_t)0x84d25d06, (q31_t)0x22c706cb, (q31_t)0x84d0a7da, (q31_t)0x22c0fac4, (q31_t)0x84cef2f9, (q31_t)0x22baeea7, (q31_t)0x84cd3e64, + (q31_t)0x22b4e274, (q31_t)0x84cb8a1b, (q31_t)0x22aed62c, (q31_t)0x84c9d61f, (q31_t)0x22a8c9cf, (q31_t)0x84c8226e, (q31_t)0x22a2bd5d, (q31_t)0x84c66f09, + (q31_t)0x229cb0d5, (q31_t)0x84c4bbf0, (q31_t)0x2296a437, (q31_t)0x84c30924, (q31_t)0x22909785, (q31_t)0x84c156a3, (q31_t)0x228a8abd, (q31_t)0x84bfa46e, + (q31_t)0x22847de0, (q31_t)0x84bdf286, (q31_t)0x227e70ed, (q31_t)0x84bc40e9, (q31_t)0x227863e5, (q31_t)0x84ba8f98, (q31_t)0x227256c8, (q31_t)0x84b8de94, + (q31_t)0x226c4996, (q31_t)0x84b72ddb, (q31_t)0x22663c4e, (q31_t)0x84b57d6f, (q31_t)0x22602ef1, (q31_t)0x84b3cd4f, (q31_t)0x225a217f, (q31_t)0x84b21d7a, + (q31_t)0x225413f8, (q31_t)0x84b06df2, (q31_t)0x224e065c, (q31_t)0x84aebeb6, (q31_t)0x2247f8aa, (q31_t)0x84ad0fc6, (q31_t)0x2241eae3, (q31_t)0x84ab6122, + (q31_t)0x223bdd08, (q31_t)0x84a9b2ca, (q31_t)0x2235cf17, (q31_t)0x84a804be, (q31_t)0x222fc111, (q31_t)0x84a656fe, (q31_t)0x2229b2f6, (q31_t)0x84a4a98a, + (q31_t)0x2223a4c5, (q31_t)0x84a2fc62, (q31_t)0x221d9680, (q31_t)0x84a14f87, (q31_t)0x22178826, (q31_t)0x849fa2f7, (q31_t)0x221179b7, (q31_t)0x849df6b4, + (q31_t)0x220b6b32, (q31_t)0x849c4abd, (q31_t)0x22055c99, (q31_t)0x849a9f12, (q31_t)0x21ff4dea, (q31_t)0x8498f3b3, (q31_t)0x21f93f27, (q31_t)0x849748a0, + (q31_t)0x21f3304f, (q31_t)0x84959dd9, (q31_t)0x21ed2162, (q31_t)0x8493f35e, (q31_t)0x21e71260, (q31_t)0x84924930, (q31_t)0x21e10349, (q31_t)0x84909f4e, + (q31_t)0x21daf41d, (q31_t)0x848ef5b7, (q31_t)0x21d4e4dc, (q31_t)0x848d4c6d, (q31_t)0x21ced586, (q31_t)0x848ba36f, (q31_t)0x21c8c61c, (q31_t)0x8489fabe, + (q31_t)0x21c2b69c, (q31_t)0x84885258, (q31_t)0x21bca708, (q31_t)0x8486aa3e, (q31_t)0x21b6975f, (q31_t)0x84850271, (q31_t)0x21b087a1, (q31_t)0x84835af0, + (q31_t)0x21aa77cf, (q31_t)0x8481b3bb, (q31_t)0x21a467e7, (q31_t)0x84800cd2, (q31_t)0x219e57eb, (q31_t)0x847e6636, (q31_t)0x219847da, (q31_t)0x847cbfe5, + (q31_t)0x219237b5, (q31_t)0x847b19e1, (q31_t)0x218c277a, (q31_t)0x84797429, (q31_t)0x2186172b, (q31_t)0x8477cebd, (q31_t)0x218006c8, (q31_t)0x8476299e, + (q31_t)0x2179f64f, (q31_t)0x847484ca, (q31_t)0x2173e5c2, (q31_t)0x8472e043, (q31_t)0x216dd521, (q31_t)0x84713c08, (q31_t)0x2167c46b, (q31_t)0x846f9819, + (q31_t)0x2161b3a0, (q31_t)0x846df477, (q31_t)0x215ba2c0, (q31_t)0x846c5120, (q31_t)0x215591cc, (q31_t)0x846aae16, (q31_t)0x214f80c4, (q31_t)0x84690b58, + (q31_t)0x21496fa7, (q31_t)0x846768e7, (q31_t)0x21435e75, (q31_t)0x8465c6c1, (q31_t)0x213d4d2f, (q31_t)0x846424e8, (q31_t)0x21373bd4, (q31_t)0x8462835b, + (q31_t)0x21312a65, (q31_t)0x8460e21a, (q31_t)0x212b18e1, (q31_t)0x845f4126, (q31_t)0x21250749, (q31_t)0x845da07e, (q31_t)0x211ef59d, (q31_t)0x845c0022, + (q31_t)0x2118e3dc, (q31_t)0x845a6012, (q31_t)0x2112d206, (q31_t)0x8458c04f, (q31_t)0x210cc01d, (q31_t)0x845720d8, (q31_t)0x2106ae1e, (q31_t)0x845581ad, + (q31_t)0x21009c0c, (q31_t)0x8453e2cf, (q31_t)0x20fa89e5, (q31_t)0x8452443d, (q31_t)0x20f477aa, (q31_t)0x8450a5f7, (q31_t)0x20ee655a, (q31_t)0x844f07fd, + (q31_t)0x20e852f6, (q31_t)0x844d6a50, (q31_t)0x20e2407e, (q31_t)0x844bccef, (q31_t)0x20dc2df2, (q31_t)0x844a2fda, (q31_t)0x20d61b51, (q31_t)0x84489311, + (q31_t)0x20d0089c, (q31_t)0x8446f695, (q31_t)0x20c9f5d3, (q31_t)0x84455a66, (q31_t)0x20c3e2f5, (q31_t)0x8443be82, (q31_t)0x20bdd003, (q31_t)0x844222eb, + (q31_t)0x20b7bcfe, (q31_t)0x844087a0, (q31_t)0x20b1a9e4, (q31_t)0x843eeca2, (q31_t)0x20ab96b5, (q31_t)0x843d51f0, (q31_t)0x20a58373, (q31_t)0x843bb78a, + (q31_t)0x209f701c, (q31_t)0x843a1d70, (q31_t)0x20995cb2, (q31_t)0x843883a3, (q31_t)0x20934933, (q31_t)0x8436ea23, (q31_t)0x208d35a0, (q31_t)0x843550ee, + (q31_t)0x208721f9, (q31_t)0x8433b806, (q31_t)0x20810e3e, (q31_t)0x84321f6b, (q31_t)0x207afa6f, (q31_t)0x8430871b, (q31_t)0x2074e68c, (q31_t)0x842eef18, + (q31_t)0x206ed295, (q31_t)0x842d5762, (q31_t)0x2068be8a, (q31_t)0x842bbff8, (q31_t)0x2062aa6b, (q31_t)0x842a28da, (q31_t)0x205c9638, (q31_t)0x84289209, + (q31_t)0x205681f1, (q31_t)0x8426fb84, (q31_t)0x20506d96, (q31_t)0x8425654b, (q31_t)0x204a5927, (q31_t)0x8423cf5f, (q31_t)0x204444a4, (q31_t)0x842239bf, + (q31_t)0x203e300d, (q31_t)0x8420a46c, (q31_t)0x20381b63, (q31_t)0x841f0f65, (q31_t)0x203206a4, (q31_t)0x841d7aaa, (q31_t)0x202bf1d2, (q31_t)0x841be63c, + (q31_t)0x2025dcec, (q31_t)0x841a521a, (q31_t)0x201fc7f2, (q31_t)0x8418be45, (q31_t)0x2019b2e4, (q31_t)0x84172abc, (q31_t)0x20139dc2, (q31_t)0x84159780, + (q31_t)0x200d888d, (q31_t)0x84140490, (q31_t)0x20077344, (q31_t)0x841271ec, (q31_t)0x20015de7, (q31_t)0x8410df95, (q31_t)0x1ffb4876, (q31_t)0x840f4d8a, + (q31_t)0x1ff532f2, (q31_t)0x840dbbcc, (q31_t)0x1fef1d59, (q31_t)0x840c2a5a, (q31_t)0x1fe907ae, (q31_t)0x840a9935, (q31_t)0x1fe2f1ee, (q31_t)0x8409085c, + (q31_t)0x1fdcdc1b, (q31_t)0x840777d0, (q31_t)0x1fd6c634, (q31_t)0x8405e790, (q31_t)0x1fd0b03a, (q31_t)0x8404579d, (q31_t)0x1fca9a2b, (q31_t)0x8402c7f6, + (q31_t)0x1fc4840a, (q31_t)0x8401389b, (q31_t)0x1fbe6dd4, (q31_t)0x83ffa98d, (q31_t)0x1fb8578b, (q31_t)0x83fe1acc, (q31_t)0x1fb2412f, (q31_t)0x83fc8c57, + (q31_t)0x1fac2abf, (q31_t)0x83fafe2e, (q31_t)0x1fa6143b, (q31_t)0x83f97052, (q31_t)0x1f9ffda4, (q31_t)0x83f7e2c3, (q31_t)0x1f99e6fa, (q31_t)0x83f65580, + (q31_t)0x1f93d03c, (q31_t)0x83f4c889, (q31_t)0x1f8db96a, (q31_t)0x83f33bdf, (q31_t)0x1f87a285, (q31_t)0x83f1af82, (q31_t)0x1f818b8d, (q31_t)0x83f02371, + (q31_t)0x1f7b7481, (q31_t)0x83ee97ad, (q31_t)0x1f755d61, (q31_t)0x83ed0c35, (q31_t)0x1f6f462f, (q31_t)0x83eb810a, (q31_t)0x1f692ee9, (q31_t)0x83e9f62b, + (q31_t)0x1f63178f, (q31_t)0x83e86b99, (q31_t)0x1f5d0022, (q31_t)0x83e6e153, (q31_t)0x1f56e8a2, (q31_t)0x83e5575a, (q31_t)0x1f50d10e, (q31_t)0x83e3cdad, + (q31_t)0x1f4ab968, (q31_t)0x83e2444d, (q31_t)0x1f44a1ad, (q31_t)0x83e0bb3a, (q31_t)0x1f3e89e0, (q31_t)0x83df3273, (q31_t)0x1f3871ff, (q31_t)0x83dda9f9, + (q31_t)0x1f325a0b, (q31_t)0x83dc21cb, (q31_t)0x1f2c4204, (q31_t)0x83da99ea, (q31_t)0x1f2629ea, (q31_t)0x83d91255, (q31_t)0x1f2011bc, (q31_t)0x83d78b0d, + (q31_t)0x1f19f97b, (q31_t)0x83d60412, (q31_t)0x1f13e127, (q31_t)0x83d47d63, (q31_t)0x1f0dc8c0, (q31_t)0x83d2f701, (q31_t)0x1f07b045, (q31_t)0x83d170eb, + (q31_t)0x1f0197b8, (q31_t)0x83cfeb22, (q31_t)0x1efb7f17, (q31_t)0x83ce65a6, (q31_t)0x1ef56664, (q31_t)0x83cce076, (q31_t)0x1eef4d9d, (q31_t)0x83cb5b93, + (q31_t)0x1ee934c3, (q31_t)0x83c9d6fc, (q31_t)0x1ee31bd6, (q31_t)0x83c852b2, (q31_t)0x1edd02d6, (q31_t)0x83c6ceb5, (q31_t)0x1ed6e9c3, (q31_t)0x83c54b04, + (q31_t)0x1ed0d09d, (q31_t)0x83c3c7a0, (q31_t)0x1ecab763, (q31_t)0x83c24488, (q31_t)0x1ec49e17, (q31_t)0x83c0c1be, (q31_t)0x1ebe84b8, (q31_t)0x83bf3f3f, + (q31_t)0x1eb86b46, (q31_t)0x83bdbd0e, (q31_t)0x1eb251c1, (q31_t)0x83bc3b29, (q31_t)0x1eac3829, (q31_t)0x83bab991, (q31_t)0x1ea61e7e, (q31_t)0x83b93845, + (q31_t)0x1ea004c1, (q31_t)0x83b7b746, (q31_t)0x1e99eaf0, (q31_t)0x83b63694, (q31_t)0x1e93d10c, (q31_t)0x83b4b62e, (q31_t)0x1e8db716, (q31_t)0x83b33616, + (q31_t)0x1e879d0d, (q31_t)0x83b1b649, (q31_t)0x1e8182f1, (q31_t)0x83b036ca, (q31_t)0x1e7b68c2, (q31_t)0x83aeb797, (q31_t)0x1e754e80, (q31_t)0x83ad38b1, + (q31_t)0x1e6f342c, (q31_t)0x83abba17, (q31_t)0x1e6919c4, (q31_t)0x83aa3bca, (q31_t)0x1e62ff4a, (q31_t)0x83a8bdca, (q31_t)0x1e5ce4be, (q31_t)0x83a74017, + (q31_t)0x1e56ca1e, (q31_t)0x83a5c2b0, (q31_t)0x1e50af6c, (q31_t)0x83a44596, (q31_t)0x1e4a94a7, (q31_t)0x83a2c8c9, (q31_t)0x1e4479cf, (q31_t)0x83a14c48, + (q31_t)0x1e3e5ee5, (q31_t)0x839fd014, (q31_t)0x1e3843e8, (q31_t)0x839e542d, (q31_t)0x1e3228d9, (q31_t)0x839cd893, (q31_t)0x1e2c0db6, (q31_t)0x839b5d45, + (q31_t)0x1e25f282, (q31_t)0x8399e244, (q31_t)0x1e1fd73a, (q31_t)0x83986790, (q31_t)0x1e19bbe0, (q31_t)0x8396ed29, (q31_t)0x1e13a074, (q31_t)0x8395730e, + (q31_t)0x1e0d84f5, (q31_t)0x8393f940, (q31_t)0x1e076963, (q31_t)0x83927fbf, (q31_t)0x1e014dbf, (q31_t)0x8391068a, (q31_t)0x1dfb3208, (q31_t)0x838f8da2, + (q31_t)0x1df5163f, (q31_t)0x838e1507, (q31_t)0x1deefa63, (q31_t)0x838c9cb9, (q31_t)0x1de8de75, (q31_t)0x838b24b8, (q31_t)0x1de2c275, (q31_t)0x8389ad03, + (q31_t)0x1ddca662, (q31_t)0x8388359b, (q31_t)0x1dd68a3c, (q31_t)0x8386be80, (q31_t)0x1dd06e04, (q31_t)0x838547b2, (q31_t)0x1dca51ba, (q31_t)0x8383d130, + (q31_t)0x1dc4355e, (q31_t)0x83825afb, (q31_t)0x1dbe18ef, (q31_t)0x8380e513, (q31_t)0x1db7fc6d, (q31_t)0x837f6f78, (q31_t)0x1db1dfda, (q31_t)0x837dfa2a, + (q31_t)0x1dabc334, (q31_t)0x837c8528, (q31_t)0x1da5a67c, (q31_t)0x837b1074, (q31_t)0x1d9f89b1, (q31_t)0x83799c0c, (q31_t)0x1d996cd4, (q31_t)0x837827f0, + (q31_t)0x1d934fe5, (q31_t)0x8376b422, (q31_t)0x1d8d32e4, (q31_t)0x837540a1, (q31_t)0x1d8715d0, (q31_t)0x8373cd6c, (q31_t)0x1d80f8ab, (q31_t)0x83725a84, + (q31_t)0x1d7adb73, (q31_t)0x8370e7e9, (q31_t)0x1d74be29, (q31_t)0x836f759b, (q31_t)0x1d6ea0cc, (q31_t)0x836e039a, (q31_t)0x1d68835e, (q31_t)0x836c91e5, + (q31_t)0x1d6265dd, (q31_t)0x836b207d, (q31_t)0x1d5c484b, (q31_t)0x8369af63, (q31_t)0x1d562aa6, (q31_t)0x83683e95, (q31_t)0x1d500cef, (q31_t)0x8366ce14, + (q31_t)0x1d49ef26, (q31_t)0x83655ddf, (q31_t)0x1d43d14b, (q31_t)0x8363edf8, (q31_t)0x1d3db35e, (q31_t)0x83627e5d, (q31_t)0x1d37955e, (q31_t)0x83610f10, + (q31_t)0x1d31774d, (q31_t)0x835fa00f, (q31_t)0x1d2b592a, (q31_t)0x835e315b, (q31_t)0x1d253af5, (q31_t)0x835cc2f4, (q31_t)0x1d1f1cae, (q31_t)0x835b54da, + (q31_t)0x1d18fe54, (q31_t)0x8359e70d, (q31_t)0x1d12dfe9, (q31_t)0x8358798c, (q31_t)0x1d0cc16c, (q31_t)0x83570c59, (q31_t)0x1d06a2dd, (q31_t)0x83559f72, + (q31_t)0x1d00843d, (q31_t)0x835432d8, (q31_t)0x1cfa658a, (q31_t)0x8352c68c, (q31_t)0x1cf446c5, (q31_t)0x83515a8c, (q31_t)0x1cee27ef, (q31_t)0x834feed9, + (q31_t)0x1ce80906, (q31_t)0x834e8373, (q31_t)0x1ce1ea0c, (q31_t)0x834d185a, (q31_t)0x1cdbcb00, (q31_t)0x834bad8e, (q31_t)0x1cd5abe3, (q31_t)0x834a430e, + (q31_t)0x1ccf8cb3, (q31_t)0x8348d8dc, (q31_t)0x1cc96d72, (q31_t)0x83476ef6, (q31_t)0x1cc34e1f, (q31_t)0x8346055e, (q31_t)0x1cbd2eba, (q31_t)0x83449c12, + (q31_t)0x1cb70f43, (q31_t)0x83433314, (q31_t)0x1cb0efbb, (q31_t)0x8341ca62, (q31_t)0x1caad021, (q31_t)0x834061fd, (q31_t)0x1ca4b075, (q31_t)0x833ef9e6, + (q31_t)0x1c9e90b8, (q31_t)0x833d921b, (q31_t)0x1c9870e9, (q31_t)0x833c2a9d, (q31_t)0x1c925109, (q31_t)0x833ac36c, (q31_t)0x1c8c3116, (q31_t)0x83395c88, + (q31_t)0x1c861113, (q31_t)0x8337f5f1, (q31_t)0x1c7ff0fd, (q31_t)0x83368fa7, (q31_t)0x1c79d0d6, (q31_t)0x833529aa, (q31_t)0x1c73b09d, (q31_t)0x8333c3fa, + (q31_t)0x1c6d9053, (q31_t)0x83325e97, (q31_t)0x1c676ff8, (q31_t)0x8330f981, (q31_t)0x1c614f8b, (q31_t)0x832f94b8, (q31_t)0x1c5b2f0c, (q31_t)0x832e303c, + (q31_t)0x1c550e7c, (q31_t)0x832ccc0d, (q31_t)0x1c4eedda, (q31_t)0x832b682b, (q31_t)0x1c48cd27, (q31_t)0x832a0496, (q31_t)0x1c42ac62, (q31_t)0x8328a14d, + (q31_t)0x1c3c8b8c, (q31_t)0x83273e52, (q31_t)0x1c366aa5, (q31_t)0x8325dba4, (q31_t)0x1c3049ac, (q31_t)0x83247943, (q31_t)0x1c2a28a2, (q31_t)0x8323172f, + (q31_t)0x1c240786, (q31_t)0x8321b568, (q31_t)0x1c1de659, (q31_t)0x832053ee, (q31_t)0x1c17c51b, (q31_t)0x831ef2c1, (q31_t)0x1c11a3cb, (q31_t)0x831d91e1, + (q31_t)0x1c0b826a, (q31_t)0x831c314e, (q31_t)0x1c0560f8, (q31_t)0x831ad109, (q31_t)0x1bff3f75, (q31_t)0x83197110, (q31_t)0x1bf91de0, (q31_t)0x83181164, + (q31_t)0x1bf2fc3a, (q31_t)0x8316b205, (q31_t)0x1becda83, (q31_t)0x831552f4, (q31_t)0x1be6b8ba, (q31_t)0x8313f42f, (q31_t)0x1be096e0, (q31_t)0x831295b7, + (q31_t)0x1bda74f6, (q31_t)0x8311378d, (q31_t)0x1bd452f9, (q31_t)0x830fd9af, (q31_t)0x1bce30ec, (q31_t)0x830e7c1f, (q31_t)0x1bc80ece, (q31_t)0x830d1edc, + (q31_t)0x1bc1ec9e, (q31_t)0x830bc1e6, (q31_t)0x1bbbca5e, (q31_t)0x830a653c, (q31_t)0x1bb5a80c, (q31_t)0x830908e0, (q31_t)0x1baf85a9, (q31_t)0x8307acd1, + (q31_t)0x1ba96335, (q31_t)0x83065110, (q31_t)0x1ba340b0, (q31_t)0x8304f59b, (q31_t)0x1b9d1e1a, (q31_t)0x83039a73, (q31_t)0x1b96fb73, (q31_t)0x83023f98, + (q31_t)0x1b90d8bb, (q31_t)0x8300e50b, (q31_t)0x1b8ab5f2, (q31_t)0x82ff8acb, (q31_t)0x1b849317, (q31_t)0x82fe30d7, (q31_t)0x1b7e702c, (q31_t)0x82fcd731, + (q31_t)0x1b784d30, (q31_t)0x82fb7dd8, (q31_t)0x1b722a23, (q31_t)0x82fa24cc, (q31_t)0x1b6c0705, (q31_t)0x82f8cc0d, (q31_t)0x1b65e3d7, (q31_t)0x82f7739c, + (q31_t)0x1b5fc097, (q31_t)0x82f61b77, (q31_t)0x1b599d46, (q31_t)0x82f4c3a0, (q31_t)0x1b5379e5, (q31_t)0x82f36c15, (q31_t)0x1b4d5672, (q31_t)0x82f214d8, + (q31_t)0x1b4732ef, (q31_t)0x82f0bde8, (q31_t)0x1b410f5b, (q31_t)0x82ef6745, (q31_t)0x1b3aebb6, (q31_t)0x82ee10ef, (q31_t)0x1b34c801, (q31_t)0x82ecbae7, + (q31_t)0x1b2ea43a, (q31_t)0x82eb652b, (q31_t)0x1b288063, (q31_t)0x82ea0fbd, (q31_t)0x1b225c7b, (q31_t)0x82e8ba9c, (q31_t)0x1b1c3883, (q31_t)0x82e765c8, + (q31_t)0x1b161479, (q31_t)0x82e61141, (q31_t)0x1b0ff05f, (q31_t)0x82e4bd07, (q31_t)0x1b09cc34, (q31_t)0x82e3691b, (q31_t)0x1b03a7f9, (q31_t)0x82e2157c, + (q31_t)0x1afd83ad, (q31_t)0x82e0c22a, (q31_t)0x1af75f50, (q31_t)0x82df6f25, (q31_t)0x1af13ae3, (q31_t)0x82de1c6d, (q31_t)0x1aeb1665, (q31_t)0x82dcca02, + (q31_t)0x1ae4f1d6, (q31_t)0x82db77e5, (q31_t)0x1adecd37, (q31_t)0x82da2615, (q31_t)0x1ad8a887, (q31_t)0x82d8d492, (q31_t)0x1ad283c7, (q31_t)0x82d7835c, + (q31_t)0x1acc5ef6, (q31_t)0x82d63274, (q31_t)0x1ac63a14, (q31_t)0x82d4e1d8, (q31_t)0x1ac01522, (q31_t)0x82d3918a, (q31_t)0x1ab9f020, (q31_t)0x82d24189, + (q31_t)0x1ab3cb0d, (q31_t)0x82d0f1d5, (q31_t)0x1aada5e9, (q31_t)0x82cfa26f, (q31_t)0x1aa780b6, (q31_t)0x82ce5356, (q31_t)0x1aa15b71, (q31_t)0x82cd048a, + (q31_t)0x1a9b361d, (q31_t)0x82cbb60b, (q31_t)0x1a9510b7, (q31_t)0x82ca67d9, (q31_t)0x1a8eeb42, (q31_t)0x82c919f5, (q31_t)0x1a88c5bc, (q31_t)0x82c7cc5e, + (q31_t)0x1a82a026, (q31_t)0x82c67f14, (q31_t)0x1a7c7a7f, (q31_t)0x82c53217, (q31_t)0x1a7654c8, (q31_t)0x82c3e568, (q31_t)0x1a702f01, (q31_t)0x82c29906, + (q31_t)0x1a6a0929, (q31_t)0x82c14cf1, (q31_t)0x1a63e341, (q31_t)0x82c00129, (q31_t)0x1a5dbd49, (q31_t)0x82beb5af, (q31_t)0x1a579741, (q31_t)0x82bd6a82, + (q31_t)0x1a517128, (q31_t)0x82bc1fa2, (q31_t)0x1a4b4aff, (q31_t)0x82bad50f, (q31_t)0x1a4524c6, (q31_t)0x82b98aca, (q31_t)0x1a3efe7c, (q31_t)0x82b840d2, + (q31_t)0x1a38d823, (q31_t)0x82b6f727, (q31_t)0x1a32b1b9, (q31_t)0x82b5adca, (q31_t)0x1a2c8b3f, (q31_t)0x82b464ba, (q31_t)0x1a2664b5, (q31_t)0x82b31bf7, + (q31_t)0x1a203e1b, (q31_t)0x82b1d381, (q31_t)0x1a1a1771, (q31_t)0x82b08b59, (q31_t)0x1a13f0b6, (q31_t)0x82af437e, (q31_t)0x1a0dc9ec, (q31_t)0x82adfbf0, + (q31_t)0x1a07a311, (q31_t)0x82acb4b0, (q31_t)0x1a017c27, (q31_t)0x82ab6dbd, (q31_t)0x19fb552c, (q31_t)0x82aa2717, (q31_t)0x19f52e22, (q31_t)0x82a8e0bf, + (q31_t)0x19ef0707, (q31_t)0x82a79ab3, (q31_t)0x19e8dfdc, (q31_t)0x82a654f6, (q31_t)0x19e2b8a2, (q31_t)0x82a50f85, (q31_t)0x19dc9157, (q31_t)0x82a3ca62, + (q31_t)0x19d669fc, (q31_t)0x82a2858c, (q31_t)0x19d04292, (q31_t)0x82a14104, (q31_t)0x19ca1b17, (q31_t)0x829ffcc8, (q31_t)0x19c3f38d, (q31_t)0x829eb8db, + (q31_t)0x19bdcbf3, (q31_t)0x829d753a, (q31_t)0x19b7a449, (q31_t)0x829c31e7, (q31_t)0x19b17c8f, (q31_t)0x829aeee1, (q31_t)0x19ab54c5, (q31_t)0x8299ac29, + (q31_t)0x19a52ceb, (q31_t)0x829869be, (q31_t)0x199f0502, (q31_t)0x829727a0, (q31_t)0x1998dd09, (q31_t)0x8295e5cf, (q31_t)0x1992b4ff, (q31_t)0x8294a44c, + (q31_t)0x198c8ce7, (q31_t)0x82936317, (q31_t)0x198664be, (q31_t)0x8292222e, (q31_t)0x19803c86, (q31_t)0x8290e194, (q31_t)0x197a143e, (q31_t)0x828fa146, + (q31_t)0x1973ebe6, (q31_t)0x828e6146, (q31_t)0x196dc37e, (q31_t)0x828d2193, (q31_t)0x19679b07, (q31_t)0x828be22e, (q31_t)0x19617280, (q31_t)0x828aa316, + (q31_t)0x195b49ea, (q31_t)0x8289644b, (q31_t)0x19552144, (q31_t)0x828825ce, (q31_t)0x194ef88e, (q31_t)0x8286e79e, (q31_t)0x1948cfc8, (q31_t)0x8285a9bb, + (q31_t)0x1942a6f3, (q31_t)0x82846c26, (q31_t)0x193c7e0f, (q31_t)0x82832edf, (q31_t)0x1936551b, (q31_t)0x8281f1e4, (q31_t)0x19302c17, (q31_t)0x8280b538, + (q31_t)0x192a0304, (q31_t)0x827f78d8, (q31_t)0x1923d9e1, (q31_t)0x827e3cc6, (q31_t)0x191db0af, (q31_t)0x827d0102, (q31_t)0x1917876d, (q31_t)0x827bc58a, + (q31_t)0x19115e1c, (q31_t)0x827a8a61, (q31_t)0x190b34bb, (q31_t)0x82794f84, (q31_t)0x19050b4b, (q31_t)0x827814f6, (q31_t)0x18fee1cb, (q31_t)0x8276dab4, + (q31_t)0x18f8b83c, (q31_t)0x8275a0c0, (q31_t)0x18f28e9e, (q31_t)0x8274671a, (q31_t)0x18ec64f0, (q31_t)0x82732dc0, (q31_t)0x18e63b33, (q31_t)0x8271f4b5, + (q31_t)0x18e01167, (q31_t)0x8270bbf7, (q31_t)0x18d9e78b, (q31_t)0x826f8386, (q31_t)0x18d3bda0, (q31_t)0x826e4b62, (q31_t)0x18cd93a5, (q31_t)0x826d138d, + (q31_t)0x18c7699b, (q31_t)0x826bdc04, (q31_t)0x18c13f82, (q31_t)0x826aa4c9, (q31_t)0x18bb155a, (q31_t)0x82696ddc, (q31_t)0x18b4eb22, (q31_t)0x8268373c, + (q31_t)0x18aec0db, (q31_t)0x826700e9, (q31_t)0x18a89685, (q31_t)0x8265cae4, (q31_t)0x18a26c20, (q31_t)0x8264952d, (q31_t)0x189c41ab, (q31_t)0x82635fc2, + (q31_t)0x18961728, (q31_t)0x82622aa6, (q31_t)0x188fec95, (q31_t)0x8260f5d7, (q31_t)0x1889c1f3, (q31_t)0x825fc155, (q31_t)0x18839742, (q31_t)0x825e8d21, + (q31_t)0x187d6c82, (q31_t)0x825d593a, (q31_t)0x187741b2, (q31_t)0x825c25a1, (q31_t)0x187116d4, (q31_t)0x825af255, (q31_t)0x186aebe6, (q31_t)0x8259bf57, + (q31_t)0x1864c0ea, (q31_t)0x82588ca7, (q31_t)0x185e95de, (q31_t)0x82575a44, (q31_t)0x18586ac3, (q31_t)0x8256282e, (q31_t)0x18523f9a, (q31_t)0x8254f666, + (q31_t)0x184c1461, (q31_t)0x8253c4eb, (q31_t)0x1845e919, (q31_t)0x825293be, (q31_t)0x183fbdc3, (q31_t)0x825162df, (q31_t)0x1839925d, (q31_t)0x8250324d, + (q31_t)0x183366e9, (q31_t)0x824f0208, (q31_t)0x182d3b65, (q31_t)0x824dd211, (q31_t)0x18270fd3, (q31_t)0x824ca268, (q31_t)0x1820e431, (q31_t)0x824b730c, + (q31_t)0x181ab881, (q31_t)0x824a43fe, (q31_t)0x18148cc2, (q31_t)0x8249153d, (q31_t)0x180e60f4, (q31_t)0x8247e6ca, (q31_t)0x18083518, (q31_t)0x8246b8a4, + (q31_t)0x1802092c, (q31_t)0x82458acc, (q31_t)0x17fbdd32, (q31_t)0x82445d41, (q31_t)0x17f5b129, (q31_t)0x82433004, (q31_t)0x17ef8511, (q31_t)0x82420315, + (q31_t)0x17e958ea, (q31_t)0x8240d673, (q31_t)0x17e32cb5, (q31_t)0x823faa1e, (q31_t)0x17dd0070, (q31_t)0x823e7e18, (q31_t)0x17d6d41d, (q31_t)0x823d525e, + (q31_t)0x17d0a7bc, (q31_t)0x823c26f3, (q31_t)0x17ca7b4c, (q31_t)0x823afbd5, (q31_t)0x17c44ecd, (q31_t)0x8239d104, (q31_t)0x17be223f, (q31_t)0x8238a681, + (q31_t)0x17b7f5a3, (q31_t)0x82377c4c, (q31_t)0x17b1c8f8, (q31_t)0x82365264, (q31_t)0x17ab9c3e, (q31_t)0x823528ca, (q31_t)0x17a56f76, (q31_t)0x8233ff7e, + (q31_t)0x179f429f, (q31_t)0x8232d67f, (q31_t)0x179915ba, (q31_t)0x8231adce, (q31_t)0x1792e8c6, (q31_t)0x8230856a, (q31_t)0x178cbbc4, (q31_t)0x822f5d54, + (q31_t)0x17868eb3, (q31_t)0x822e358b, (q31_t)0x17806194, (q31_t)0x822d0e10, (q31_t)0x177a3466, (q31_t)0x822be6e3, (q31_t)0x17740729, (q31_t)0x822ac004, + (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x1767ac85, (q31_t)0x8228732d, (q31_t)0x17617f1d, (q31_t)0x82274d36, (q31_t)0x175b51a7, (q31_t)0x8226278d, + (q31_t)0x17552422, (q31_t)0x82250232, (q31_t)0x174ef68f, (q31_t)0x8223dd24, (q31_t)0x1748c8ee, (q31_t)0x8222b863, (q31_t)0x17429b3e, (q31_t)0x822193f1, + (q31_t)0x173c6d80, (q31_t)0x82206fcc, (q31_t)0x17363fb4, (q31_t)0x821f4bf5, (q31_t)0x173011d9, (q31_t)0x821e286b, (q31_t)0x1729e3f0, (q31_t)0x821d052f, + (q31_t)0x1723b5f9, (q31_t)0x821be240, (q31_t)0x171d87f3, (q31_t)0x821abfa0, (q31_t)0x171759df, (q31_t)0x82199d4d, (q31_t)0x17112bbd, (q31_t)0x82187b47, + (q31_t)0x170afd8d, (q31_t)0x82175990, (q31_t)0x1704cf4f, (q31_t)0x82163826, (q31_t)0x16fea102, (q31_t)0x82151709, (q31_t)0x16f872a7, (q31_t)0x8213f63a, + (q31_t)0x16f2443e, (q31_t)0x8212d5b9, (q31_t)0x16ec15c7, (q31_t)0x8211b586, (q31_t)0x16e5e741, (q31_t)0x821095a0, (q31_t)0x16dfb8ae, (q31_t)0x820f7608, + (q31_t)0x16d98a0c, (q31_t)0x820e56be, (q31_t)0x16d35b5c, (q31_t)0x820d37c1, (q31_t)0x16cd2c9f, (q31_t)0x820c1912, (q31_t)0x16c6fdd3, (q31_t)0x820afab1, + (q31_t)0x16c0cef9, (q31_t)0x8209dc9e, (q31_t)0x16baa011, (q31_t)0x8208bed8, (q31_t)0x16b4711b, (q31_t)0x8207a160, (q31_t)0x16ae4217, (q31_t)0x82068435, + (q31_t)0x16a81305, (q31_t)0x82056758, (q31_t)0x16a1e3e5, (q31_t)0x82044ac9, (q31_t)0x169bb4b7, (q31_t)0x82032e88, (q31_t)0x1695857b, (q31_t)0x82021294, + (q31_t)0x168f5632, (q31_t)0x8200f6ef, (q31_t)0x168926da, (q31_t)0x81ffdb96, (q31_t)0x1682f774, (q31_t)0x81fec08c, (q31_t)0x167cc801, (q31_t)0x81fda5cf, + (q31_t)0x1676987f, (q31_t)0x81fc8b60, (q31_t)0x167068f0, (q31_t)0x81fb713f, (q31_t)0x166a3953, (q31_t)0x81fa576c, (q31_t)0x166409a8, (q31_t)0x81f93de6, + (q31_t)0x165dd9f0, (q31_t)0x81f824ae, (q31_t)0x1657aa29, (q31_t)0x81f70bc3, (q31_t)0x16517a55, (q31_t)0x81f5f327, (q31_t)0x164b4a73, (q31_t)0x81f4dad8, + (q31_t)0x16451a83, (q31_t)0x81f3c2d7, (q31_t)0x163eea86, (q31_t)0x81f2ab24, (q31_t)0x1638ba7a, (q31_t)0x81f193be, (q31_t)0x16328a61, (q31_t)0x81f07ca6, + (q31_t)0x162c5a3b, (q31_t)0x81ef65dc, (q31_t)0x16262a06, (q31_t)0x81ee4f60, (q31_t)0x161ff9c4, (q31_t)0x81ed3932, (q31_t)0x1619c975, (q31_t)0x81ec2351, + (q31_t)0x16139918, (q31_t)0x81eb0dbe, (q31_t)0x160d68ad, (q31_t)0x81e9f879, (q31_t)0x16073834, (q31_t)0x81e8e381, (q31_t)0x160107ae, (q31_t)0x81e7ced8, + (q31_t)0x15fad71b, (q31_t)0x81e6ba7c, (q31_t)0x15f4a679, (q31_t)0x81e5a66e, (q31_t)0x15ee75cb, (q31_t)0x81e492ad, (q31_t)0x15e8450e, (q31_t)0x81e37f3b, + (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x15dbe36d, (q31_t)0x81e1593f, (q31_t)0x15d5b288, (q31_t)0x81e046b6, (q31_t)0x15cf8196, (q31_t)0x81df347b, + (q31_t)0x15c95097, (q31_t)0x81de228d, (q31_t)0x15c31f89, (q31_t)0x81dd10ee, (q31_t)0x15bcee6f, (q31_t)0x81dbff9c, (q31_t)0x15b6bd47, (q31_t)0x81daee98, + (q31_t)0x15b08c12, (q31_t)0x81d9dde1, (q31_t)0x15aa5acf, (q31_t)0x81d8cd79, (q31_t)0x15a4297f, (q31_t)0x81d7bd5e, (q31_t)0x159df821, (q31_t)0x81d6ad92, + (q31_t)0x1597c6b7, (q31_t)0x81d59e13, (q31_t)0x1591953e, (q31_t)0x81d48ee1, (q31_t)0x158b63b9, (q31_t)0x81d37ffe, (q31_t)0x15853226, (q31_t)0x81d27169, + (q31_t)0x157f0086, (q31_t)0x81d16321, (q31_t)0x1578ced9, (q31_t)0x81d05527, (q31_t)0x15729d1f, (q31_t)0x81cf477b, (q31_t)0x156c6b57, (q31_t)0x81ce3a1d, + (q31_t)0x15663982, (q31_t)0x81cd2d0c, (q31_t)0x156007a0, (q31_t)0x81cc204a, (q31_t)0x1559d5b1, (q31_t)0x81cb13d5, (q31_t)0x1553a3b4, (q31_t)0x81ca07af, + (q31_t)0x154d71aa, (q31_t)0x81c8fbd6, (q31_t)0x15473f94, (q31_t)0x81c7f04b, (q31_t)0x15410d70, (q31_t)0x81c6e50d, (q31_t)0x153adb3f, (q31_t)0x81c5da1e, + (q31_t)0x1534a901, (q31_t)0x81c4cf7d, (q31_t)0x152e76b5, (q31_t)0x81c3c529, (q31_t)0x1528445d, (q31_t)0x81c2bb23, (q31_t)0x152211f8, (q31_t)0x81c1b16b, + (q31_t)0x151bdf86, (q31_t)0x81c0a801, (q31_t)0x1515ad06, (q31_t)0x81bf9ee5, (q31_t)0x150f7a7a, (q31_t)0x81be9617, (q31_t)0x150947e1, (q31_t)0x81bd8d97, + (q31_t)0x1503153a, (q31_t)0x81bc8564, (q31_t)0x14fce287, (q31_t)0x81bb7d7f, (q31_t)0x14f6afc7, (q31_t)0x81ba75e9, (q31_t)0x14f07cf9, (q31_t)0x81b96ea0, + (q31_t)0x14ea4a1f, (q31_t)0x81b867a5, (q31_t)0x14e41738, (q31_t)0x81b760f8, (q31_t)0x14dde445, (q31_t)0x81b65a99, (q31_t)0x14d7b144, (q31_t)0x81b55488, + (q31_t)0x14d17e36, (q31_t)0x81b44ec4, (q31_t)0x14cb4b1c, (q31_t)0x81b3494f, (q31_t)0x14c517f4, (q31_t)0x81b24427, (q31_t)0x14bee4c0, (q31_t)0x81b13f4e, + (q31_t)0x14b8b17f, (q31_t)0x81b03ac2, (q31_t)0x14b27e32, (q31_t)0x81af3684, (q31_t)0x14ac4ad7, (q31_t)0x81ae3294, (q31_t)0x14a61770, (q31_t)0x81ad2ef2, + (q31_t)0x149fe3fc, (q31_t)0x81ac2b9e, (q31_t)0x1499b07c, (q31_t)0x81ab2898, (q31_t)0x14937cee, (q31_t)0x81aa25e0, (q31_t)0x148d4954, (q31_t)0x81a92376, + (q31_t)0x148715ae, (q31_t)0x81a82159, (q31_t)0x1480e1fa, (q31_t)0x81a71f8b, (q31_t)0x147aae3a, (q31_t)0x81a61e0b, (q31_t)0x14747a6d, (q31_t)0x81a51cd8, + (q31_t)0x146e4694, (q31_t)0x81a41bf4, (q31_t)0x146812ae, (q31_t)0x81a31b5d, (q31_t)0x1461debc, (q31_t)0x81a21b14, (q31_t)0x145baabd, (q31_t)0x81a11b1a, + (q31_t)0x145576b1, (q31_t)0x81a01b6d, (q31_t)0x144f4299, (q31_t)0x819f1c0e, (q31_t)0x14490e74, (q31_t)0x819e1cfd, (q31_t)0x1442da43, (q31_t)0x819d1e3a, + (q31_t)0x143ca605, (q31_t)0x819c1fc5, (q31_t)0x143671bb, (q31_t)0x819b219e, (q31_t)0x14303d65, (q31_t)0x819a23c5, (q31_t)0x142a0902, (q31_t)0x8199263a, + (q31_t)0x1423d492, (q31_t)0x819828fd, (q31_t)0x141da016, (q31_t)0x81972c0e, (q31_t)0x14176b8e, (q31_t)0x81962f6d, (q31_t)0x141136f9, (q31_t)0x8195331a, + (q31_t)0x140b0258, (q31_t)0x81943715, (q31_t)0x1404cdaa, (q31_t)0x81933b5e, (q31_t)0x13fe98f1, (q31_t)0x81923ff4, (q31_t)0x13f8642a, (q31_t)0x819144d9, + (q31_t)0x13f22f58, (q31_t)0x81904a0c, (q31_t)0x13ebfa79, (q31_t)0x818f4f8d, (q31_t)0x13e5c58e, (q31_t)0x818e555c, (q31_t)0x13df9097, (q31_t)0x818d5b78, + (q31_t)0x13d95b93, (q31_t)0x818c61e3, (q31_t)0x13d32683, (q31_t)0x818b689c, (q31_t)0x13ccf167, (q31_t)0x818a6fa3, (q31_t)0x13c6bc3f, (q31_t)0x818976f8, + (q31_t)0x13c0870a, (q31_t)0x81887e9a, (q31_t)0x13ba51ca, (q31_t)0x8187868b, (q31_t)0x13b41c7d, (q31_t)0x81868eca, (q31_t)0x13ade724, (q31_t)0x81859757, + (q31_t)0x13a7b1bf, (q31_t)0x8184a032, (q31_t)0x13a17c4d, (q31_t)0x8183a95b, (q31_t)0x139b46d0, (q31_t)0x8182b2d1, (q31_t)0x13951146, (q31_t)0x8181bc96, + (q31_t)0x138edbb1, (q31_t)0x8180c6a9, (q31_t)0x1388a60f, (q31_t)0x817fd10a, (q31_t)0x13827062, (q31_t)0x817edbb9, (q31_t)0x137c3aa8, (q31_t)0x817de6b6, + (q31_t)0x137604e2, (q31_t)0x817cf201, (q31_t)0x136fcf10, (q31_t)0x817bfd9b, (q31_t)0x13699933, (q31_t)0x817b0982, (q31_t)0x13636349, (q31_t)0x817a15b7, + (q31_t)0x135d2d53, (q31_t)0x8179223a, (q31_t)0x1356f752, (q31_t)0x81782f0b, (q31_t)0x1350c144, (q31_t)0x81773c2b, (q31_t)0x134a8b2b, (q31_t)0x81764998, + (q31_t)0x13445505, (q31_t)0x81755754, (q31_t)0x133e1ed4, (q31_t)0x8174655d, (q31_t)0x1337e897, (q31_t)0x817373b5, (q31_t)0x1331b24e, (q31_t)0x8172825a, + (q31_t)0x132b7bf9, (q31_t)0x8171914e, (q31_t)0x13254599, (q31_t)0x8170a090, (q31_t)0x131f0f2c, (q31_t)0x816fb020, (q31_t)0x1318d8b4, (q31_t)0x816ebffe, + (q31_t)0x1312a230, (q31_t)0x816dd02a, (q31_t)0x130c6ba0, (q31_t)0x816ce0a4, (q31_t)0x13063505, (q31_t)0x816bf16c, (q31_t)0x12fffe5d, (q31_t)0x816b0282, + (q31_t)0x12f9c7aa, (q31_t)0x816a13e6, (q31_t)0x12f390ec, (q31_t)0x81692599, (q31_t)0x12ed5a21, (q31_t)0x81683799, (q31_t)0x12e7234b, (q31_t)0x816749e8, + (q31_t)0x12e0ec6a, (q31_t)0x81665c84, (q31_t)0x12dab57c, (q31_t)0x81656f6f, (q31_t)0x12d47e83, (q31_t)0x816482a8, (q31_t)0x12ce477f, (q31_t)0x8163962f, + (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x12c1d953, (q31_t)0x8161be27, (q31_t)0x12bba22b, (q31_t)0x8160d298, (q31_t)0x12b56af9, (q31_t)0x815fe758, + (q31_t)0x12af33ba, (q31_t)0x815efc65, (q31_t)0x12a8fc70, (q31_t)0x815e11c1, (q31_t)0x12a2c51b, (q31_t)0x815d276a, (q31_t)0x129c8dba, (q31_t)0x815c3d62, + (q31_t)0x1296564d, (q31_t)0x815b53a8, (q31_t)0x12901ed5, (q31_t)0x815a6a3c, (q31_t)0x1289e752, (q31_t)0x8159811e, (q31_t)0x1283afc3, (q31_t)0x8158984e, + (q31_t)0x127d7829, (q31_t)0x8157afcd, (q31_t)0x12774083, (q31_t)0x8156c799, (q31_t)0x127108d2, (q31_t)0x8155dfb4, (q31_t)0x126ad116, (q31_t)0x8154f81d, + (q31_t)0x1264994e, (q31_t)0x815410d4, (q31_t)0x125e617b, (q31_t)0x815329d9, (q31_t)0x1258299c, (q31_t)0x8152432c, (q31_t)0x1251f1b3, (q31_t)0x81515ccd, + (q31_t)0x124bb9be, (q31_t)0x815076bd, (q31_t)0x124581bd, (q31_t)0x814f90fb, (q31_t)0x123f49b2, (q31_t)0x814eab86, (q31_t)0x1239119b, (q31_t)0x814dc660, + (q31_t)0x1232d979, (q31_t)0x814ce188, (q31_t)0x122ca14b, (q31_t)0x814bfcff, (q31_t)0x12266913, (q31_t)0x814b18c3, (q31_t)0x122030cf, (q31_t)0x814a34d6, + (q31_t)0x1219f880, (q31_t)0x81495136, (q31_t)0x1213c026, (q31_t)0x81486de5, (q31_t)0x120d87c1, (q31_t)0x81478ae2, (q31_t)0x12074f50, (q31_t)0x8146a82e, + (q31_t)0x120116d5, (q31_t)0x8145c5c7, (q31_t)0x11fade4e, (q31_t)0x8144e3ae, (q31_t)0x11f4a5bd, (q31_t)0x814401e4, (q31_t)0x11ee6d20, (q31_t)0x81432068, + (q31_t)0x11e83478, (q31_t)0x81423f3a, (q31_t)0x11e1fbc5, (q31_t)0x81415e5a, (q31_t)0x11dbc307, (q31_t)0x81407dc9, (q31_t)0x11d58a3e, (q31_t)0x813f9d86, + (q31_t)0x11cf516a, (q31_t)0x813ebd90, (q31_t)0x11c9188b, (q31_t)0x813ddde9, (q31_t)0x11c2dfa2, (q31_t)0x813cfe91, (q31_t)0x11bca6ad, (q31_t)0x813c1f86, + (q31_t)0x11b66dad, (q31_t)0x813b40ca, (q31_t)0x11b034a2, (q31_t)0x813a625b, (q31_t)0x11a9fb8d, (q31_t)0x8139843b, (q31_t)0x11a3c26c, (q31_t)0x8138a66a, + (q31_t)0x119d8941, (q31_t)0x8137c8e6, (q31_t)0x1197500a, (q31_t)0x8136ebb1, (q31_t)0x119116c9, (q31_t)0x81360ec9, (q31_t)0x118add7d, (q31_t)0x81353230, + (q31_t)0x1184a427, (q31_t)0x813455e6, (q31_t)0x117e6ac5, (q31_t)0x813379e9, (q31_t)0x11783159, (q31_t)0x81329e3b, (q31_t)0x1171f7e2, (q31_t)0x8131c2db, + (q31_t)0x116bbe60, (q31_t)0x8130e7c9, (q31_t)0x116584d3, (q31_t)0x81300d05, (q31_t)0x115f4b3c, (q31_t)0x812f3290, (q31_t)0x1159119a, (q31_t)0x812e5868, + (q31_t)0x1152d7ed, (q31_t)0x812d7e8f, (q31_t)0x114c9e35, (q31_t)0x812ca505, (q31_t)0x11466473, (q31_t)0x812bcbc8, (q31_t)0x11402aa6, (q31_t)0x812af2da, + (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0x1133b6ed, (q31_t)0x812941e8, (q31_t)0x112d7d00, (q31_t)0x812869e4, (q31_t)0x11274309, (q31_t)0x8127922f, + (q31_t)0x11210907, (q31_t)0x8126bac8, (q31_t)0x111acefb, (q31_t)0x8125e3af, (q31_t)0x111494e4, (q31_t)0x81250ce4, (q31_t)0x110e5ac2, (q31_t)0x81243668, + (q31_t)0x11082096, (q31_t)0x8123603a, (q31_t)0x1101e65f, (q31_t)0x81228a5a, (q31_t)0x10fbac1e, (q31_t)0x8121b4c8, (q31_t)0x10f571d3, (q31_t)0x8120df85, + (q31_t)0x10ef377d, (q31_t)0x81200a90, (q31_t)0x10e8fd1c, (q31_t)0x811f35e9, (q31_t)0x10e2c2b2, (q31_t)0x811e6191, (q31_t)0x10dc883c, (q31_t)0x811d8d86, + (q31_t)0x10d64dbd, (q31_t)0x811cb9ca, (q31_t)0x10d01333, (q31_t)0x811be65d, (q31_t)0x10c9d89e, (q31_t)0x811b133d, (q31_t)0x10c39dff, (q31_t)0x811a406c, + (q31_t)0x10bd6356, (q31_t)0x81196de9, (q31_t)0x10b728a3, (q31_t)0x81189bb4, (q31_t)0x10b0ede5, (q31_t)0x8117c9ce, (q31_t)0x10aab31d, (q31_t)0x8116f836, + (q31_t)0x10a4784b, (q31_t)0x811626ec, (q31_t)0x109e3d6e, (q31_t)0x811555f1, (q31_t)0x10980287, (q31_t)0x81148544, (q31_t)0x1091c796, (q31_t)0x8113b4e5, + (q31_t)0x108b8c9b, (q31_t)0x8112e4d4, (q31_t)0x10855195, (q31_t)0x81121512, (q31_t)0x107f1686, (q31_t)0x8111459e, (q31_t)0x1078db6c, (q31_t)0x81107678, + (q31_t)0x1072a048, (q31_t)0x810fa7a0, (q31_t)0x106c651a, (q31_t)0x810ed917, (q31_t)0x106629e1, (q31_t)0x810e0adc, (q31_t)0x105fee9f, (q31_t)0x810d3cf0, + (q31_t)0x1059b352, (q31_t)0x810c6f52, (q31_t)0x105377fc, (q31_t)0x810ba202, (q31_t)0x104d3c9b, (q31_t)0x810ad500, (q31_t)0x10470130, (q31_t)0x810a084d, + (q31_t)0x1040c5bb, (q31_t)0x81093be8, (q31_t)0x103a8a3d, (q31_t)0x81086fd1, (q31_t)0x10344eb4, (q31_t)0x8107a409, (q31_t)0x102e1321, (q31_t)0x8106d88f, + (q31_t)0x1027d784, (q31_t)0x81060d63, (q31_t)0x10219bdd, (q31_t)0x81054286, (q31_t)0x101b602d, (q31_t)0x810477f7, (q31_t)0x10152472, (q31_t)0x8103adb6, + (q31_t)0x100ee8ad, (q31_t)0x8102e3c4, (q31_t)0x1008acdf, (q31_t)0x81021a20, (q31_t)0x10027107, (q31_t)0x810150ca, (q31_t)0xffc3524, (q31_t)0x810087c3, + (q31_t)0xff5f938, (q31_t)0x80ffbf0a, (q31_t)0xfefbd42, (q31_t)0x80fef69f, (q31_t)0xfe98143, (q31_t)0x80fe2e83, (q31_t)0xfe34539, (q31_t)0x80fd66b5, + (q31_t)0xfdd0926, (q31_t)0x80fc9f35, (q31_t)0xfd6cd08, (q31_t)0x80fbd804, (q31_t)0xfd090e1, (q31_t)0x80fb1121, (q31_t)0xfca54b1, (q31_t)0x80fa4a8c, + (q31_t)0xfc41876, (q31_t)0x80f98446, (q31_t)0xfbddc32, (q31_t)0x80f8be4e, (q31_t)0xfb79fe4, (q31_t)0x80f7f8a4, (q31_t)0xfb1638d, (q31_t)0x80f73349, + (q31_t)0xfab272b, (q31_t)0x80f66e3c, (q31_t)0xfa4eac0, (q31_t)0x80f5a97e, (q31_t)0xf9eae4c, (q31_t)0x80f4e50e, (q31_t)0xf9871ce, (q31_t)0x80f420ec, + (q31_t)0xf923546, (q31_t)0x80f35d19, (q31_t)0xf8bf8b4, (q31_t)0x80f29994, (q31_t)0xf85bc19, (q31_t)0x80f1d65d, (q31_t)0xf7f7f75, (q31_t)0x80f11375, + (q31_t)0xf7942c7, (q31_t)0x80f050db, (q31_t)0xf73060f, (q31_t)0x80ef8e90, (q31_t)0xf6cc94e, (q31_t)0x80eecc93, (q31_t)0xf668c83, (q31_t)0x80ee0ae4, + (q31_t)0xf604faf, (q31_t)0x80ed4984, (q31_t)0xf5a12d1, (q31_t)0x80ec8872, (q31_t)0xf53d5ea, (q31_t)0x80ebc7ae, (q31_t)0xf4d98f9, (q31_t)0x80eb0739, + (q31_t)0xf475bff, (q31_t)0x80ea4712, (q31_t)0xf411efb, (q31_t)0x80e9873a, (q31_t)0xf3ae1ee, (q31_t)0x80e8c7b0, (q31_t)0xf34a4d8, (q31_t)0x80e80874, + (q31_t)0xf2e67b8, (q31_t)0x80e74987, (q31_t)0xf282a8f, (q31_t)0x80e68ae8, (q31_t)0xf21ed5d, (q31_t)0x80e5cc98, (q31_t)0xf1bb021, (q31_t)0x80e50e96, + (q31_t)0xf1572dc, (q31_t)0x80e450e2, (q31_t)0xf0f358e, (q31_t)0x80e3937d, (q31_t)0xf08f836, (q31_t)0x80e2d666, (q31_t)0xf02bad5, (q31_t)0x80e2199e, + (q31_t)0xefc7d6b, (q31_t)0x80e15d24, (q31_t)0xef63ff7, (q31_t)0x80e0a0f8, (q31_t)0xef0027b, (q31_t)0x80dfe51b, (q31_t)0xee9c4f5, (q31_t)0x80df298c, + (q31_t)0xee38766, (q31_t)0x80de6e4c, (q31_t)0xedd49ce, (q31_t)0x80ddb35a, (q31_t)0xed70c2c, (q31_t)0x80dcf8b7, (q31_t)0xed0ce82, (q31_t)0x80dc3e62, + (q31_t)0xeca90ce, (q31_t)0x80db845b, (q31_t)0xec45311, (q31_t)0x80dacaa3, (q31_t)0xebe154b, (q31_t)0x80da1139, (q31_t)0xeb7d77c, (q31_t)0x80d9581e, + (q31_t)0xeb199a4, (q31_t)0x80d89f51, (q31_t)0xeab5bc3, (q31_t)0x80d7e6d3, (q31_t)0xea51dd8, (q31_t)0x80d72ea3, (q31_t)0xe9edfe5, (q31_t)0x80d676c1, + (q31_t)0xe98a1e9, (q31_t)0x80d5bf2e, (q31_t)0xe9263e3, (q31_t)0x80d507e9, (q31_t)0xe8c25d5, (q31_t)0x80d450f3, (q31_t)0xe85e7be, (q31_t)0x80d39a4b, + (q31_t)0xe7fa99e, (q31_t)0x80d2e3f2, (q31_t)0xe796b74, (q31_t)0x80d22de7, (q31_t)0xe732d42, (q31_t)0x80d1782a, (q31_t)0xe6cef07, (q31_t)0x80d0c2bc, + (q31_t)0xe66b0c3, (q31_t)0x80d00d9d, (q31_t)0xe607277, (q31_t)0x80cf58cc, (q31_t)0xe5a3421, (q31_t)0x80cea449, (q31_t)0xe53f5c2, (q31_t)0x80cdf015, + (q31_t)0xe4db75b, (q31_t)0x80cd3c2f, (q31_t)0xe4778eb, (q31_t)0x80cc8898, (q31_t)0xe413a72, (q31_t)0x80cbd54f, (q31_t)0xe3afbf0, (q31_t)0x80cb2255, + (q31_t)0xe34bd66, (q31_t)0x80ca6fa9, (q31_t)0xe2e7ed2, (q31_t)0x80c9bd4c, (q31_t)0xe284036, (q31_t)0x80c90b3d, (q31_t)0xe220191, (q31_t)0x80c8597c, + (q31_t)0xe1bc2e4, (q31_t)0x80c7a80a, (q31_t)0xe15842e, (q31_t)0x80c6f6e7, (q31_t)0xe0f456f, (q31_t)0x80c64612, (q31_t)0xe0906a7, (q31_t)0x80c5958b, + (q31_t)0xe02c7d7, (q31_t)0x80c4e553, (q31_t)0xdfc88fe, (q31_t)0x80c4356a, (q31_t)0xdf64a1c, (q31_t)0x80c385cf, (q31_t)0xdf00b32, (q31_t)0x80c2d682, + (q31_t)0xde9cc40, (q31_t)0x80c22784, (q31_t)0xde38d44, (q31_t)0x80c178d4, (q31_t)0xddd4e40, (q31_t)0x80c0ca73, (q31_t)0xdd70f34, (q31_t)0x80c01c60, + (q31_t)0xdd0d01f, (q31_t)0x80bf6e9c, (q31_t)0xdca9102, (q31_t)0x80bec127, (q31_t)0xdc451dc, (q31_t)0x80be13ff, (q31_t)0xdbe12ad, (q31_t)0x80bd6727, + (q31_t)0xdb7d376, (q31_t)0x80bcba9d, (q31_t)0xdb19437, (q31_t)0x80bc0e61, (q31_t)0xdab54ef, (q31_t)0x80bb6274, (q31_t)0xda5159f, (q31_t)0x80bab6d5, + (q31_t)0xd9ed646, (q31_t)0x80ba0b85, (q31_t)0xd9896e5, (q31_t)0x80b96083, (q31_t)0xd92577b, (q31_t)0x80b8b5d0, (q31_t)0xd8c1809, (q31_t)0x80b80b6c, + (q31_t)0xd85d88f, (q31_t)0x80b76156, (q31_t)0xd7f990c, (q31_t)0x80b6b78e, (q31_t)0xd795982, (q31_t)0x80b60e15, (q31_t)0xd7319ee, (q31_t)0x80b564ea, + (q31_t)0xd6cda53, (q31_t)0x80b4bc0e, (q31_t)0xd669aaf, (q31_t)0x80b41381, (q31_t)0xd605b03, (q31_t)0x80b36b42, (q31_t)0xd5a1b4f, (q31_t)0x80b2c351, + (q31_t)0xd53db92, (q31_t)0x80b21baf, (q31_t)0xd4d9bcd, (q31_t)0x80b1745c, (q31_t)0xd475c00, (q31_t)0x80b0cd57, (q31_t)0xd411c2b, (q31_t)0x80b026a1, + (q31_t)0xd3adc4e, (q31_t)0x80af8039, (q31_t)0xd349c68, (q31_t)0x80aeda20, (q31_t)0xd2e5c7b, (q31_t)0x80ae3455, (q31_t)0xd281c85, (q31_t)0x80ad8ed9, + (q31_t)0xd21dc87, (q31_t)0x80ace9ab, (q31_t)0xd1b9c81, (q31_t)0x80ac44cc, (q31_t)0xd155c73, (q31_t)0x80aba03b, (q31_t)0xd0f1c5d, (q31_t)0x80aafbf9, + (q31_t)0xd08dc3f, (q31_t)0x80aa5806, (q31_t)0xd029c18, (q31_t)0x80a9b461, (q31_t)0xcfc5bea, (q31_t)0x80a9110b, (q31_t)0xcf61bb4, (q31_t)0x80a86e03, + (q31_t)0xcefdb76, (q31_t)0x80a7cb49, (q31_t)0xce99b2f, (q31_t)0x80a728df, (q31_t)0xce35ae1, (q31_t)0x80a686c2, (q31_t)0xcdd1a8b, (q31_t)0x80a5e4f5, + (q31_t)0xcd6da2d, (q31_t)0x80a54376, (q31_t)0xcd099c7, (q31_t)0x80a4a245, (q31_t)0xcca5959, (q31_t)0x80a40163, (q31_t)0xcc418e3, (q31_t)0x80a360d0, + (q31_t)0xcbdd865, (q31_t)0x80a2c08b, (q31_t)0xcb797e0, (q31_t)0x80a22095, (q31_t)0xcb15752, (q31_t)0x80a180ed, (q31_t)0xcab16bd, (q31_t)0x80a0e194, + (q31_t)0xca4d620, (q31_t)0x80a04289, (q31_t)0xc9e957b, (q31_t)0x809fa3cd, (q31_t)0xc9854cf, (q31_t)0x809f0560, (q31_t)0xc92141a, (q31_t)0x809e6741, + (q31_t)0xc8bd35e, (q31_t)0x809dc971, (q31_t)0xc85929a, (q31_t)0x809d2bef, (q31_t)0xc7f51cf, (q31_t)0x809c8ebc, (q31_t)0xc7910fb, (q31_t)0x809bf1d7, + (q31_t)0xc72d020, (q31_t)0x809b5541, (q31_t)0xc6c8f3e, (q31_t)0x809ab8fa, (q31_t)0xc664e53, (q31_t)0x809a1d01, (q31_t)0xc600d61, (q31_t)0x80998157, + (q31_t)0xc59cc68, (q31_t)0x8098e5fb, (q31_t)0xc538b66, (q31_t)0x80984aee, (q31_t)0xc4d4a5d, (q31_t)0x8097b030, (q31_t)0xc47094d, (q31_t)0x809715c0, + (q31_t)0xc40c835, (q31_t)0x80967b9f, (q31_t)0xc3a8715, (q31_t)0x8095e1cc, (q31_t)0xc3445ee, (q31_t)0x80954848, (q31_t)0xc2e04c0, (q31_t)0x8094af13, + (q31_t)0xc27c389, (q31_t)0x8094162c, (q31_t)0xc21824c, (q31_t)0x80937d93, (q31_t)0xc1b4107, (q31_t)0x8092e54a, (q31_t)0xc14ffba, (q31_t)0x80924d4f, + (q31_t)0xc0ebe66, (q31_t)0x8091b5a2, (q31_t)0xc087d0a, (q31_t)0x80911e44, (q31_t)0xc023ba7, (q31_t)0x80908735, (q31_t)0xbfbfa3d, (q31_t)0x808ff074, + (q31_t)0xbf5b8cb, (q31_t)0x808f5a02, (q31_t)0xbef7752, (q31_t)0x808ec3df, (q31_t)0xbe935d2, (q31_t)0x808e2e0a, (q31_t)0xbe2f44a, (q31_t)0x808d9884, + (q31_t)0xbdcb2bb, (q31_t)0x808d034c, (q31_t)0xbd67124, (q31_t)0x808c6e63, (q31_t)0xbd02f87, (q31_t)0x808bd9c9, (q31_t)0xbc9ede2, (q31_t)0x808b457d, + (q31_t)0xbc3ac35, (q31_t)0x808ab180, (q31_t)0xbbd6a82, (q31_t)0x808a1dd2, (q31_t)0xbb728c7, (q31_t)0x80898a72, (q31_t)0xbb0e705, (q31_t)0x8088f761, + (q31_t)0xbaaa53b, (q31_t)0x8088649e, (q31_t)0xba4636b, (q31_t)0x8087d22a, (q31_t)0xb9e2193, (q31_t)0x80874005, (q31_t)0xb97dfb5, (q31_t)0x8086ae2e, + (q31_t)0xb919dcf, (q31_t)0x80861ca6, (q31_t)0xb8b5be1, (q31_t)0x80858b6c, (q31_t)0xb8519ed, (q31_t)0x8084fa82, (q31_t)0xb7ed7f2, (q31_t)0x808469e5, + (q31_t)0xb7895f0, (q31_t)0x8083d998, (q31_t)0xb7253e6, (q31_t)0x80834999, (q31_t)0xb6c11d5, (q31_t)0x8082b9e9, (q31_t)0xb65cfbe, (q31_t)0x80822a87, + (q31_t)0xb5f8d9f, (q31_t)0x80819b74, (q31_t)0xb594b7a, (q31_t)0x80810cb0, (q31_t)0xb53094d, (q31_t)0x80807e3a, (q31_t)0xb4cc719, (q31_t)0x807ff013, + (q31_t)0xb4684df, (q31_t)0x807f623b, (q31_t)0xb40429d, (q31_t)0x807ed4b1, (q31_t)0xb3a0055, (q31_t)0x807e4776, (q31_t)0xb33be05, (q31_t)0x807dba89, + (q31_t)0xb2d7baf, (q31_t)0x807d2dec, (q31_t)0xb273952, (q31_t)0x807ca19c, (q31_t)0xb20f6ee, (q31_t)0x807c159c, (q31_t)0xb1ab483, (q31_t)0x807b89ea, + (q31_t)0xb147211, (q31_t)0x807afe87, (q31_t)0xb0e2f98, (q31_t)0x807a7373, (q31_t)0xb07ed19, (q31_t)0x8079e8ad, (q31_t)0xb01aa92, (q31_t)0x80795e36, + (q31_t)0xafb6805, (q31_t)0x8078d40d, (q31_t)0xaf52571, (q31_t)0x80784a33, (q31_t)0xaeee2d7, (q31_t)0x8077c0a8, (q31_t)0xae8a036, (q31_t)0x8077376c, + (q31_t)0xae25d8d, (q31_t)0x8076ae7e, (q31_t)0xadc1adf, (q31_t)0x807625df, (q31_t)0xad5d829, (q31_t)0x80759d8e, (q31_t)0xacf956d, (q31_t)0x8075158c, + (q31_t)0xac952aa, (q31_t)0x80748dd9, (q31_t)0xac30fe1, (q31_t)0x80740675, (q31_t)0xabccd11, (q31_t)0x80737f5f, (q31_t)0xab68a3a, (q31_t)0x8072f898, + (q31_t)0xab0475c, (q31_t)0x8072721f, (q31_t)0xaaa0478, (q31_t)0x8071ebf6, (q31_t)0xaa3c18e, (q31_t)0x8071661a, (q31_t)0xa9d7e9d, (q31_t)0x8070e08e, + (q31_t)0xa973ba5, (q31_t)0x80705b50, (q31_t)0xa90f8a7, (q31_t)0x806fd661, (q31_t)0xa8ab5a2, (q31_t)0x806f51c1, (q31_t)0xa847297, (q31_t)0x806ecd6f, + (q31_t)0xa7e2f85, (q31_t)0x806e496c, (q31_t)0xa77ec6d, (q31_t)0x806dc5b8, (q31_t)0xa71a94f, (q31_t)0x806d4253, (q31_t)0xa6b662a, (q31_t)0x806cbf3c, + (q31_t)0xa6522fe, (q31_t)0x806c3c74, (q31_t)0xa5edfcc, (q31_t)0x806bb9fa, (q31_t)0xa589c94, (q31_t)0x806b37cf, (q31_t)0xa525955, (q31_t)0x806ab5f3, + (q31_t)0xa4c1610, (q31_t)0x806a3466, (q31_t)0xa45d2c5, (q31_t)0x8069b327, (q31_t)0xa3f8f73, (q31_t)0x80693237, (q31_t)0xa394c1b, (q31_t)0x8068b196, + (q31_t)0xa3308bd, (q31_t)0x80683143, (q31_t)0xa2cc558, (q31_t)0x8067b13f, (q31_t)0xa2681ed, (q31_t)0x8067318a, (q31_t)0xa203e7c, (q31_t)0x8066b224, + (q31_t)0xa19fb04, (q31_t)0x8066330c, (q31_t)0xa13b787, (q31_t)0x8065b443, (q31_t)0xa0d7403, (q31_t)0x806535c9, (q31_t)0xa073079, (q31_t)0x8064b79d, + (q31_t)0xa00ece8, (q31_t)0x806439c0, (q31_t)0x9faa952, (q31_t)0x8063bc32, (q31_t)0x9f465b5, (q31_t)0x80633ef3, (q31_t)0x9ee2213, (q31_t)0x8062c202, + (q31_t)0x9e7de6a, (q31_t)0x80624560, (q31_t)0x9e19abb, (q31_t)0x8061c90c, (q31_t)0x9db5706, (q31_t)0x80614d08, (q31_t)0x9d5134b, (q31_t)0x8060d152, + (q31_t)0x9cecf89, (q31_t)0x806055eb, (q31_t)0x9c88bc2, (q31_t)0x805fdad2, (q31_t)0x9c247f5, (q31_t)0x805f6009, (q31_t)0x9bc0421, (q31_t)0x805ee58e, + (q31_t)0x9b5c048, (q31_t)0x805e6b62, (q31_t)0x9af7c69, (q31_t)0x805df184, (q31_t)0x9a93884, (q31_t)0x805d77f5, (q31_t)0x9a2f498, (q31_t)0x805cfeb5, + (q31_t)0x99cb0a7, (q31_t)0x805c85c4, (q31_t)0x9966cb0, (q31_t)0x805c0d21, (q31_t)0x99028b3, (q31_t)0x805b94ce, (q31_t)0x989e4b0, (q31_t)0x805b1cc8, + (q31_t)0x983a0a7, (q31_t)0x805aa512, (q31_t)0x97d5c99, (q31_t)0x805a2daa, (q31_t)0x9771884, (q31_t)0x8059b692, (q31_t)0x970d46a, (q31_t)0x80593fc7, + (q31_t)0x96a9049, (q31_t)0x8058c94c, (q31_t)0x9644c23, (q31_t)0x8058531f, (q31_t)0x95e07f8, (q31_t)0x8057dd41, (q31_t)0x957c3c6, (q31_t)0x805767b2, + (q31_t)0x9517f8f, (q31_t)0x8056f272, (q31_t)0x94b3b52, (q31_t)0x80567d80, (q31_t)0x944f70f, (q31_t)0x805608dd, (q31_t)0x93eb2c6, (q31_t)0x80559489, + (q31_t)0x9386e78, (q31_t)0x80552084, (q31_t)0x9322a24, (q31_t)0x8054accd, (q31_t)0x92be5ca, (q31_t)0x80543965, (q31_t)0x925a16b, (q31_t)0x8053c64c, + (q31_t)0x91f5d06, (q31_t)0x80535381, (q31_t)0x919189c, (q31_t)0x8052e106, (q31_t)0x912d42c, (q31_t)0x80526ed9, (q31_t)0x90c8fb6, (q31_t)0x8051fcfb, + (q31_t)0x9064b3a, (q31_t)0x80518b6b, (q31_t)0x90006ba, (q31_t)0x80511a2b, (q31_t)0x8f9c233, (q31_t)0x8050a939, (q31_t)0x8f37da7, (q31_t)0x80503896, + (q31_t)0x8ed3916, (q31_t)0x804fc841, (q31_t)0x8e6f47f, (q31_t)0x804f583c, (q31_t)0x8e0afe2, (q31_t)0x804ee885, (q31_t)0x8da6b40, (q31_t)0x804e791d, + (q31_t)0x8d42699, (q31_t)0x804e0a04, (q31_t)0x8cde1ec, (q31_t)0x804d9b39, (q31_t)0x8c79d3a, (q31_t)0x804d2cbd, (q31_t)0x8c15882, (q31_t)0x804cbe90, + (q31_t)0x8bb13c5, (q31_t)0x804c50b2, (q31_t)0x8b4cf02, (q31_t)0x804be323, (q31_t)0x8ae8a3a, (q31_t)0x804b75e2, (q31_t)0x8a8456d, (q31_t)0x804b08f0, + (q31_t)0x8a2009a, (q31_t)0x804a9c4d, (q31_t)0x89bbbc3, (q31_t)0x804a2ff9, (q31_t)0x89576e5, (q31_t)0x8049c3f3, (q31_t)0x88f3203, (q31_t)0x8049583d, + (q31_t)0x888ed1b, (q31_t)0x8048ecd5, (q31_t)0x882a82e, (q31_t)0x804881bb, (q31_t)0x87c633c, (q31_t)0x804816f1, (q31_t)0x8761e44, (q31_t)0x8047ac75, + (q31_t)0x86fd947, (q31_t)0x80474248, (q31_t)0x8699445, (q31_t)0x8046d86a, (q31_t)0x8634f3e, (q31_t)0x80466edb, (q31_t)0x85d0a32, (q31_t)0x8046059b, + (q31_t)0x856c520, (q31_t)0x80459ca9, (q31_t)0x850800a, (q31_t)0x80453406, (q31_t)0x84a3aee, (q31_t)0x8044cbb2, (q31_t)0x843f5cd, (q31_t)0x804463ad, + (q31_t)0x83db0a7, (q31_t)0x8043fbf6, (q31_t)0x8376b7c, (q31_t)0x8043948e, (q31_t)0x831264c, (q31_t)0x80432d75, (q31_t)0x82ae117, (q31_t)0x8042c6ab, + (q31_t)0x8249bdd, (q31_t)0x80426030, (q31_t)0x81e569d, (q31_t)0x8041fa03, (q31_t)0x8181159, (q31_t)0x80419425, (q31_t)0x811cc10, (q31_t)0x80412e96, + (q31_t)0x80b86c2, (q31_t)0x8040c956, (q31_t)0x805416e, (q31_t)0x80406465, (q31_t)0x7fefc16, (q31_t)0x803fffc2, (q31_t)0x7f8b6b9, (q31_t)0x803f9b6f, + (q31_t)0x7f27157, (q31_t)0x803f376a, (q31_t)0x7ec2bf0, (q31_t)0x803ed3b3, (q31_t)0x7e5e685, (q31_t)0x803e704c, (q31_t)0x7dfa114, (q31_t)0x803e0d34, + (q31_t)0x7d95b9e, (q31_t)0x803daa6a, (q31_t)0x7d31624, (q31_t)0x803d47ef, (q31_t)0x7ccd0a5, (q31_t)0x803ce5c3, (q31_t)0x7c68b21, (q31_t)0x803c83e5, + (q31_t)0x7c04598, (q31_t)0x803c2257, (q31_t)0x7ba000b, (q31_t)0x803bc117, (q31_t)0x7b3ba78, (q31_t)0x803b6026, (q31_t)0x7ad74e1, (q31_t)0x803aff84, + (q31_t)0x7a72f45, (q31_t)0x803a9f31, (q31_t)0x7a0e9a5, (q31_t)0x803a3f2d, (q31_t)0x79aa400, (q31_t)0x8039df77, (q31_t)0x7945e56, (q31_t)0x80398010, + (q31_t)0x78e18a7, (q31_t)0x803920f8, (q31_t)0x787d2f4, (q31_t)0x8038c22f, (q31_t)0x7818d3c, (q31_t)0x803863b5, (q31_t)0x77b4780, (q31_t)0x80380589, + (q31_t)0x77501be, (q31_t)0x8037a7ac, (q31_t)0x76ebbf9, (q31_t)0x80374a1f, (q31_t)0x768762e, (q31_t)0x8036ece0, (q31_t)0x762305f, (q31_t)0x80368fef, + (q31_t)0x75bea8c, (q31_t)0x8036334e, (q31_t)0x755a4b4, (q31_t)0x8035d6fb, (q31_t)0x74f5ed7, (q31_t)0x80357af8, (q31_t)0x74918f6, (q31_t)0x80351f43, + (q31_t)0x742d311, (q31_t)0x8034c3dd, (q31_t)0x73c8d27, (q31_t)0x803468c5, (q31_t)0x7364738, (q31_t)0x80340dfd, (q31_t)0x7300145, (q31_t)0x8033b383, + (q31_t)0x729bb4e, (q31_t)0x80335959, (q31_t)0x7237552, (q31_t)0x8032ff7d, (q31_t)0x71d2f52, (q31_t)0x8032a5ef, (q31_t)0x716e94e, (q31_t)0x80324cb1, + (q31_t)0x710a345, (q31_t)0x8031f3c2, (q31_t)0x70a5d37, (q31_t)0x80319b21, (q31_t)0x7041726, (q31_t)0x803142cf, (q31_t)0x6fdd110, (q31_t)0x8030eacd, + (q31_t)0x6f78af6, (q31_t)0x80309318, (q31_t)0x6f144d7, (q31_t)0x80303bb3, (q31_t)0x6eafeb4, (q31_t)0x802fe49d, (q31_t)0x6e4b88d, (q31_t)0x802f8dd5, + (q31_t)0x6de7262, (q31_t)0x802f375d, (q31_t)0x6d82c32, (q31_t)0x802ee133, (q31_t)0x6d1e5fe, (q31_t)0x802e8b58, (q31_t)0x6cb9fc6, (q31_t)0x802e35cb, + (q31_t)0x6c5598a, (q31_t)0x802de08e, (q31_t)0x6bf1349, (q31_t)0x802d8ba0, (q31_t)0x6b8cd05, (q31_t)0x802d3700, (q31_t)0x6b286bc, (q31_t)0x802ce2af, + (q31_t)0x6ac406f, (q31_t)0x802c8ead, (q31_t)0x6a5fa1e, (q31_t)0x802c3afa, (q31_t)0x69fb3c9, (q31_t)0x802be796, (q31_t)0x6996d70, (q31_t)0x802b9480, + (q31_t)0x6932713, (q31_t)0x802b41ba, (q31_t)0x68ce0b2, (q31_t)0x802aef42, (q31_t)0x6869a4c, (q31_t)0x802a9d19, (q31_t)0x68053e3, (q31_t)0x802a4b3f, + (q31_t)0x67a0d76, (q31_t)0x8029f9b4, (q31_t)0x673c704, (q31_t)0x8029a878, (q31_t)0x66d808f, (q31_t)0x8029578b, (q31_t)0x6673a16, (q31_t)0x802906ec, + (q31_t)0x660f398, (q31_t)0x8028b69c, (q31_t)0x65aad17, (q31_t)0x8028669b, (q31_t)0x6546692, (q31_t)0x802816e9, (q31_t)0x64e2009, (q31_t)0x8027c786, + (q31_t)0x647d97c, (q31_t)0x80277872, (q31_t)0x64192eb, (q31_t)0x802729ad, (q31_t)0x63b4c57, (q31_t)0x8026db36, (q31_t)0x63505be, (q31_t)0x80268d0e, + (q31_t)0x62ebf22, (q31_t)0x80263f36, (q31_t)0x6287882, (q31_t)0x8025f1ac, (q31_t)0x62231de, (q31_t)0x8025a471, (q31_t)0x61beb36, (q31_t)0x80255784, + (q31_t)0x615a48b, (q31_t)0x80250ae7, (q31_t)0x60f5ddc, (q31_t)0x8024be99, (q31_t)0x6091729, (q31_t)0x80247299, (q31_t)0x602d072, (q31_t)0x802426e8, + (q31_t)0x5fc89b8, (q31_t)0x8023db86, (q31_t)0x5f642fa, (q31_t)0x80239073, (q31_t)0x5effc38, (q31_t)0x802345af, (q31_t)0x5e9b572, (q31_t)0x8022fb3a, + (q31_t)0x5e36ea9, (q31_t)0x8022b114, (q31_t)0x5dd27dd, (q31_t)0x8022673c, (q31_t)0x5d6e10c, (q31_t)0x80221db3, (q31_t)0x5d09a38, (q31_t)0x8021d47a, + (q31_t)0x5ca5361, (q31_t)0x80218b8f, (q31_t)0x5c40c86, (q31_t)0x802142f3, (q31_t)0x5bdc5a7, (q31_t)0x8020faa6, (q31_t)0x5b77ec5, (q31_t)0x8020b2a7, + (q31_t)0x5b137df, (q31_t)0x80206af8, (q31_t)0x5aaf0f6, (q31_t)0x80202397, (q31_t)0x5a4aa09, (q31_t)0x801fdc86, (q31_t)0x59e6319, (q31_t)0x801f95c3, + (q31_t)0x5981c26, (q31_t)0x801f4f4f, (q31_t)0x591d52f, (q31_t)0x801f092a, (q31_t)0x58b8e34, (q31_t)0x801ec354, (q31_t)0x5854736, (q31_t)0x801e7dcd, + (q31_t)0x57f0035, (q31_t)0x801e3895, (q31_t)0x578b930, (q31_t)0x801df3ab, (q31_t)0x5727228, (q31_t)0x801daf11, (q31_t)0x56c2b1c, (q31_t)0x801d6ac5, + (q31_t)0x565e40d, (q31_t)0x801d26c8, (q31_t)0x55f9cfb, (q31_t)0x801ce31a, (q31_t)0x55955e6, (q31_t)0x801c9fbb, (q31_t)0x5530ecd, (q31_t)0x801c5cab, + (q31_t)0x54cc7b1, (q31_t)0x801c19ea, (q31_t)0x5468092, (q31_t)0x801bd777, (q31_t)0x540396f, (q31_t)0x801b9554, (q31_t)0x539f249, (q31_t)0x801b537f, + (q31_t)0x533ab20, (q31_t)0x801b11fa, (q31_t)0x52d63f4, (q31_t)0x801ad0c3, (q31_t)0x5271cc4, (q31_t)0x801a8fdb, (q31_t)0x520d592, (q31_t)0x801a4f42, + (q31_t)0x51a8e5c, (q31_t)0x801a0ef8, (q31_t)0x5144723, (q31_t)0x8019cefd, (q31_t)0x50dffe7, (q31_t)0x80198f50, (q31_t)0x507b8a8, (q31_t)0x80194ff3, + (q31_t)0x5017165, (q31_t)0x801910e4, (q31_t)0x4fb2a20, (q31_t)0x8018d225, (q31_t)0x4f4e2d8, (q31_t)0x801893b4, (q31_t)0x4ee9b8c, (q31_t)0x80185592, + (q31_t)0x4e8543e, (q31_t)0x801817bf, (q31_t)0x4e20cec, (q31_t)0x8017da3b, (q31_t)0x4dbc597, (q31_t)0x80179d06, (q31_t)0x4d57e40, (q31_t)0x80176020, + (q31_t)0x4cf36e5, (q31_t)0x80172388, (q31_t)0x4c8ef88, (q31_t)0x8016e740, (q31_t)0x4c2a827, (q31_t)0x8016ab46, (q31_t)0x4bc60c4, (q31_t)0x80166f9c, + (q31_t)0x4b6195d, (q31_t)0x80163440, (q31_t)0x4afd1f4, (q31_t)0x8015f933, (q31_t)0x4a98a88, (q31_t)0x8015be75, (q31_t)0x4a34319, (q31_t)0x80158406, + (q31_t)0x49cfba7, (q31_t)0x801549e6, (q31_t)0x496b432, (q31_t)0x80151015, (q31_t)0x4906cbb, (q31_t)0x8014d693, (q31_t)0x48a2540, (q31_t)0x80149d5f, + (q31_t)0x483ddc3, (q31_t)0x8014647b, (q31_t)0x47d9643, (q31_t)0x80142be5, (q31_t)0x4774ec1, (q31_t)0x8013f39e, (q31_t)0x471073b, (q31_t)0x8013bba7, + (q31_t)0x46abfb3, (q31_t)0x801383fe, (q31_t)0x4647828, (q31_t)0x80134ca4, (q31_t)0x45e309a, (q31_t)0x80131599, (q31_t)0x457e90a, (q31_t)0x8012dedd, + (q31_t)0x451a177, (q31_t)0x8012a86f, (q31_t)0x44b59e1, (q31_t)0x80127251, (q31_t)0x4451249, (q31_t)0x80123c82, (q31_t)0x43ecaae, (q31_t)0x80120701, + (q31_t)0x4388310, (q31_t)0x8011d1d0, (q31_t)0x4323b70, (q31_t)0x80119ced, (q31_t)0x42bf3cd, (q31_t)0x80116859, (q31_t)0x425ac28, (q31_t)0x80113414, + (q31_t)0x41f6480, (q31_t)0x8011001f, (q31_t)0x4191cd5, (q31_t)0x8010cc78, (q31_t)0x412d528, (q31_t)0x8010991f, (q31_t)0x40c8d79, (q31_t)0x80106616, + (q31_t)0x40645c7, (q31_t)0x8010335c, (q31_t)0x3fffe12, (q31_t)0x801000f1, (q31_t)0x3f9b65b, (q31_t)0x800fced4, (q31_t)0x3f36ea2, (q31_t)0x800f9d07, + (q31_t)0x3ed26e6, (q31_t)0x800f6b88, (q31_t)0x3e6df28, (q31_t)0x800f3a59, (q31_t)0x3e09767, (q31_t)0x800f0978, (q31_t)0x3da4fa4, (q31_t)0x800ed8e6, + (q31_t)0x3d407df, (q31_t)0x800ea8a3, (q31_t)0x3cdc017, (q31_t)0x800e78af, (q31_t)0x3c7784d, (q31_t)0x800e490a, (q31_t)0x3c13080, (q31_t)0x800e19b4, + (q31_t)0x3bae8b2, (q31_t)0x800deaad, (q31_t)0x3b4a0e0, (q31_t)0x800dbbf5, (q31_t)0x3ae590d, (q31_t)0x800d8d8b, (q31_t)0x3a81137, (q31_t)0x800d5f71, + (q31_t)0x3a1c960, (q31_t)0x800d31a5, (q31_t)0x39b8185, (q31_t)0x800d0429, (q31_t)0x39539a9, (q31_t)0x800cd6fb, (q31_t)0x38ef1ca, (q31_t)0x800caa1c, + (q31_t)0x388a9ea, (q31_t)0x800c7d8c, (q31_t)0x3826207, (q31_t)0x800c514c, (q31_t)0x37c1a22, (q31_t)0x800c255a, (q31_t)0x375d23a, (q31_t)0x800bf9b7, + (q31_t)0x36f8a51, (q31_t)0x800bce63, (q31_t)0x3694265, (q31_t)0x800ba35d, (q31_t)0x362fa78, (q31_t)0x800b78a7, (q31_t)0x35cb288, (q31_t)0x800b4e40, + (q31_t)0x3566a96, (q31_t)0x800b2427, (q31_t)0x35022a2, (q31_t)0x800afa5e, (q31_t)0x349daac, (q31_t)0x800ad0e3, (q31_t)0x34392b4, (q31_t)0x800aa7b8, + (q31_t)0x33d4abb, (q31_t)0x800a7edb, (q31_t)0x33702bf, (q31_t)0x800a564e, (q31_t)0x330bac1, (q31_t)0x800a2e0f, (q31_t)0x32a72c1, (q31_t)0x800a061f, + (q31_t)0x3242abf, (q31_t)0x8009de7e, (q31_t)0x31de2bb, (q31_t)0x8009b72c, (q31_t)0x3179ab5, (q31_t)0x80099029, (q31_t)0x31152ae, (q31_t)0x80096975, + (q31_t)0x30b0aa4, (q31_t)0x80094310, (q31_t)0x304c299, (q31_t)0x80091cf9, (q31_t)0x2fe7a8c, (q31_t)0x8008f732, (q31_t)0x2f8327d, (q31_t)0x8008d1ba, + (q31_t)0x2f1ea6c, (q31_t)0x8008ac90, (q31_t)0x2eba259, (q31_t)0x800887b6, (q31_t)0x2e55a44, (q31_t)0x8008632a, (q31_t)0x2df122e, (q31_t)0x80083eed, + (q31_t)0x2d8ca16, (q31_t)0x80081b00, (q31_t)0x2d281fc, (q31_t)0x8007f761, (q31_t)0x2cc39e1, (q31_t)0x8007d411, (q31_t)0x2c5f1c3, (q31_t)0x8007b110, + (q31_t)0x2bfa9a4, (q31_t)0x80078e5e, (q31_t)0x2b96184, (q31_t)0x80076bfb, (q31_t)0x2b31961, (q31_t)0x800749e7, (q31_t)0x2acd13d, (q31_t)0x80072822, + (q31_t)0x2a68917, (q31_t)0x800706ac, (q31_t)0x2a040f0, (q31_t)0x8006e585, (q31_t)0x299f8c7, (q31_t)0x8006c4ac, (q31_t)0x293b09c, (q31_t)0x8006a423, + (q31_t)0x28d6870, (q31_t)0x800683e8, (q31_t)0x2872043, (q31_t)0x800663fd, (q31_t)0x280d813, (q31_t)0x80064460, (q31_t)0x27a8fe2, (q31_t)0x80062513, + (q31_t)0x27447b0, (q31_t)0x80060614, (q31_t)0x26dff7c, (q31_t)0x8005e764, (q31_t)0x267b747, (q31_t)0x8005c904, (q31_t)0x2616f10, (q31_t)0x8005aaf2, + (q31_t)0x25b26d7, (q31_t)0x80058d2f, (q31_t)0x254de9e, (q31_t)0x80056fbb, (q31_t)0x24e9662, (q31_t)0x80055296, (q31_t)0x2484e26, (q31_t)0x800535c0, + (q31_t)0x24205e8, (q31_t)0x80051939, (q31_t)0x23bbda8, (q31_t)0x8004fd00, (q31_t)0x2357567, (q31_t)0x8004e117, (q31_t)0x22f2d25, (q31_t)0x8004c57d, + (q31_t)0x228e4e2, (q31_t)0x8004aa32, (q31_t)0x2229c9d, (q31_t)0x80048f35, (q31_t)0x21c5457, (q31_t)0x80047488, (q31_t)0x2160c0f, (q31_t)0x80045a29, + (q31_t)0x20fc3c6, (q31_t)0x8004401a, (q31_t)0x2097b7c, (q31_t)0x80042659, (q31_t)0x2033331, (q31_t)0x80040ce7, (q31_t)0x1fceae4, (q31_t)0x8003f3c5, + (q31_t)0x1f6a297, (q31_t)0x8003daf1, (q31_t)0x1f05a48, (q31_t)0x8003c26c, (q31_t)0x1ea11f7, (q31_t)0x8003aa36, (q31_t)0x1e3c9a6, (q31_t)0x8003924f, + (q31_t)0x1dd8154, (q31_t)0x80037ab7, (q31_t)0x1d73900, (q31_t)0x8003636e, (q31_t)0x1d0f0ab, (q31_t)0x80034c74, (q31_t)0x1caa855, (q31_t)0x800335c9, + (q31_t)0x1c45ffe, (q31_t)0x80031f6d, (q31_t)0x1be17a6, (q31_t)0x80030960, (q31_t)0x1b7cf4d, (q31_t)0x8002f3a1, (q31_t)0x1b186f3, (q31_t)0x8002de32, + (q31_t)0x1ab3e97, (q31_t)0x8002c912, (q31_t)0x1a4f63b, (q31_t)0x8002b440, (q31_t)0x19eaddd, (q31_t)0x80029fbe, (q31_t)0x198657f, (q31_t)0x80028b8a, + (q31_t)0x1921d20, (q31_t)0x800277a6, (q31_t)0x18bd4bf, (q31_t)0x80026410, (q31_t)0x1858c5e, (q31_t)0x800250c9, (q31_t)0x17f43fc, (q31_t)0x80023dd2, + (q31_t)0x178fb99, (q31_t)0x80022b29, (q31_t)0x172b335, (q31_t)0x800218cf, (q31_t)0x16c6ad0, (q31_t)0x800206c4, (q31_t)0x166226a, (q31_t)0x8001f508, + (q31_t)0x15fda03, (q31_t)0x8001e39b, (q31_t)0x159919c, (q31_t)0x8001d27d, (q31_t)0x1534934, (q31_t)0x8001c1ae, (q31_t)0x14d00ca, (q31_t)0x8001b12e, + (q31_t)0x146b860, (q31_t)0x8001a0fd, (q31_t)0x1406ff6, (q31_t)0x8001911b, (q31_t)0x13a278a, (q31_t)0x80018187, (q31_t)0x133df1e, (q31_t)0x80017243, + (q31_t)0x12d96b1, (q31_t)0x8001634e, (q31_t)0x1274e43, (q31_t)0x800154a7, (q31_t)0x12105d5, (q31_t)0x80014650, (q31_t)0x11abd66, (q31_t)0x80013847, + (q31_t)0x11474f6, (q31_t)0x80012a8e, (q31_t)0x10e2c85, (q31_t)0x80011d23, (q31_t)0x107e414, (q31_t)0x80011008, (q31_t)0x1019ba2, (q31_t)0x8001033b, + (q31_t)0x0fb5330, (q31_t)0x8000f6bd, (q31_t)0x0f50abd, (q31_t)0x8000ea8e, (q31_t)0x0eec249, (q31_t)0x8000deaf, (q31_t)0x0e879d5, (q31_t)0x8000d31e, + (q31_t)0x0e23160, (q31_t)0x8000c7dc, (q31_t)0x0dbe8eb, (q31_t)0x8000bce9, (q31_t)0x0d5a075, (q31_t)0x8000b245, (q31_t)0x0cf57ff, (q31_t)0x8000a7f0, + (q31_t)0x0c90f88, (q31_t)0x80009dea, (q31_t)0x0c2c711, (q31_t)0x80009433, (q31_t)0x0bc7e99, (q31_t)0x80008aca, (q31_t)0x0b63621, (q31_t)0x800081b1, + (q31_t)0x0afeda8, (q31_t)0x800078e7, (q31_t)0x0a9a52f, (q31_t)0x8000706c, (q31_t)0x0a35cb5, (q31_t)0x8000683f, (q31_t)0x09d143b, (q31_t)0x80006062, + (q31_t)0x096cbc1, (q31_t)0x800058d4, (q31_t)0x0908346, (q31_t)0x80005194, (q31_t)0x08a3acb, (q31_t)0x80004aa4, (q31_t)0x083f250, (q31_t)0x80004402, + (q31_t)0x07da9d4, (q31_t)0x80003daf, (q31_t)0x0776159, (q31_t)0x800037ac, (q31_t)0x07118dc, (q31_t)0x800031f7, (q31_t)0x06ad060, (q31_t)0x80002c91, + (q31_t)0x06487e3, (q31_t)0x8000277a, (q31_t)0x05e3f66, (q31_t)0x800022b3, (q31_t)0x057f6e9, (q31_t)0x80001e3a, (q31_t)0x051ae6b, (q31_t)0x80001a10, + (q31_t)0x04b65ee, (q31_t)0x80001635, (q31_t)0x0451d70, (q31_t)0x800012a9, (q31_t)0x03ed4f2, (q31_t)0x80000f6c, (q31_t)0x0388c74, (q31_t)0x80000c7e, + (q31_t)0x03243f5, (q31_t)0x800009df, (q31_t)0x02bfb77, (q31_t)0x8000078e, (q31_t)0x025b2f8, (q31_t)0x8000058d, (q31_t)0x01f6a7a, (q31_t)0x800003db, + (q31_t)0x01921fb, (q31_t)0x80000278, (q31_t)0x012d97c, (q31_t)0x80000163, (q31_t)0x00c90fe, (q31_t)0x8000009e, (q31_t)0x006487f, (q31_t)0x80000027 +}; + const q31_t cos_factorsQ31_8192[8192] = { + (q31_t)0x7ffffff6, (q31_t)0x7fffffa7, (q31_t)0x7fffff09, (q31_t)0x7ffffe1c, (q31_t)0x7ffffce1, (q31_t)0x7ffffb56, (q31_t)0x7ffff97c, (q31_t)0x7ffff753, + (q31_t)0x7ffff4dc, (q31_t)0x7ffff215, (q31_t)0x7fffef00, (q31_t)0x7fffeb9b, (q31_t)0x7fffe7e8, (q31_t)0x7fffe3e5, (q31_t)0x7fffdf94, (q31_t)0x7fffdaf3, + (q31_t)0x7fffd604, (q31_t)0x7fffd0c6, (q31_t)0x7fffcb39, (q31_t)0x7fffc55c, (q31_t)0x7fffbf31, (q31_t)0x7fffb8b7, (q31_t)0x7fffb1ee, (q31_t)0x7fffaad6, + (q31_t)0x7fffa36f, (q31_t)0x7fff9bb9, (q31_t)0x7fff93b4, (q31_t)0x7fff8b61, (q31_t)0x7fff82be, (q31_t)0x7fff79cc, (q31_t)0x7fff708b, (q31_t)0x7fff66fc, + (q31_t)0x7fff5d1d, (q31_t)0x7fff52ef, (q31_t)0x7fff4873, (q31_t)0x7fff3da8, (q31_t)0x7fff328d, (q31_t)0x7fff2724, (q31_t)0x7fff1b6b, (q31_t)0x7fff0f64, + (q31_t)0x7fff030e, (q31_t)0x7ffef669, (q31_t)0x7ffee975, (q31_t)0x7ffedc31, (q31_t)0x7ffece9f, (q31_t)0x7ffec0be, (q31_t)0x7ffeb28e, (q31_t)0x7ffea40f, + (q31_t)0x7ffe9542, (q31_t)0x7ffe8625, (q31_t)0x7ffe76b9, (q31_t)0x7ffe66fe, (q31_t)0x7ffe56f5, (q31_t)0x7ffe469c, (q31_t)0x7ffe35f4, (q31_t)0x7ffe24fe, + (q31_t)0x7ffe13b8, (q31_t)0x7ffe0224, (q31_t)0x7ffdf040, (q31_t)0x7ffdde0e, (q31_t)0x7ffdcb8d, (q31_t)0x7ffdb8bc, (q31_t)0x7ffda59d, (q31_t)0x7ffd922f, + (q31_t)0x7ffd7e72, (q31_t)0x7ffd6a66, (q31_t)0x7ffd560b, (q31_t)0x7ffd4161, (q31_t)0x7ffd2c68, (q31_t)0x7ffd1720, (q31_t)0x7ffd0189, (q31_t)0x7ffceba4, + (q31_t)0x7ffcd56f, (q31_t)0x7ffcbeeb, (q31_t)0x7ffca819, (q31_t)0x7ffc90f7, (q31_t)0x7ffc7987, (q31_t)0x7ffc61c7, (q31_t)0x7ffc49b9, (q31_t)0x7ffc315b, + (q31_t)0x7ffc18af, (q31_t)0x7ffbffb4, (q31_t)0x7ffbe66a, (q31_t)0x7ffbccd0, (q31_t)0x7ffbb2e8, (q31_t)0x7ffb98b1, (q31_t)0x7ffb7e2b, (q31_t)0x7ffb6356, + (q31_t)0x7ffb4833, (q31_t)0x7ffb2cc0, (q31_t)0x7ffb10fe, (q31_t)0x7ffaf4ed, (q31_t)0x7ffad88e, (q31_t)0x7ffabbdf, (q31_t)0x7ffa9ee2, (q31_t)0x7ffa8195, + (q31_t)0x7ffa63fa, (q31_t)0x7ffa460f, (q31_t)0x7ffa27d6, (q31_t)0x7ffa094e, (q31_t)0x7ff9ea76, (q31_t)0x7ff9cb50, (q31_t)0x7ff9abdb, (q31_t)0x7ff98c17, + (q31_t)0x7ff96c04, (q31_t)0x7ff94ba2, (q31_t)0x7ff92af1, (q31_t)0x7ff909f2, (q31_t)0x7ff8e8a3, (q31_t)0x7ff8c705, (q31_t)0x7ff8a519, (q31_t)0x7ff882dd, + (q31_t)0x7ff86053, (q31_t)0x7ff83d79, (q31_t)0x7ff81a51, (q31_t)0x7ff7f6da, (q31_t)0x7ff7d313, (q31_t)0x7ff7aefe, (q31_t)0x7ff78a9a, (q31_t)0x7ff765e7, + (q31_t)0x7ff740e5, (q31_t)0x7ff71b94, (q31_t)0x7ff6f5f4, (q31_t)0x7ff6d005, (q31_t)0x7ff6a9c8, (q31_t)0x7ff6833b, (q31_t)0x7ff65c5f, (q31_t)0x7ff63535, + (q31_t)0x7ff60dbb, (q31_t)0x7ff5e5f3, (q31_t)0x7ff5bddc, (q31_t)0x7ff59576, (q31_t)0x7ff56cc0, (q31_t)0x7ff543bc, (q31_t)0x7ff51a69, (q31_t)0x7ff4f0c7, + (q31_t)0x7ff4c6d6, (q31_t)0x7ff49c96, (q31_t)0x7ff47208, (q31_t)0x7ff4472a, (q31_t)0x7ff41bfd, (q31_t)0x7ff3f082, (q31_t)0x7ff3c4b7, (q31_t)0x7ff3989e, + (q31_t)0x7ff36c36, (q31_t)0x7ff33f7e, (q31_t)0x7ff31278, (q31_t)0x7ff2e523, (q31_t)0x7ff2b77f, (q31_t)0x7ff2898c, (q31_t)0x7ff25b4a, (q31_t)0x7ff22cb9, + (q31_t)0x7ff1fdd9, (q31_t)0x7ff1ceab, (q31_t)0x7ff19f2d, (q31_t)0x7ff16f61, (q31_t)0x7ff13f45, (q31_t)0x7ff10edb, (q31_t)0x7ff0de22, (q31_t)0x7ff0ad19, + (q31_t)0x7ff07bc2, (q31_t)0x7ff04a1c, (q31_t)0x7ff01827, (q31_t)0x7fefe5e4, (q31_t)0x7fefb351, (q31_t)0x7fef806f, (q31_t)0x7fef4d3e, (q31_t)0x7fef19bf, + (q31_t)0x7feee5f0, (q31_t)0x7feeb1d3, (q31_t)0x7fee7d67, (q31_t)0x7fee48ac, (q31_t)0x7fee13a1, (q31_t)0x7fedde48, (q31_t)0x7feda8a0, (q31_t)0x7fed72aa, + (q31_t)0x7fed3c64, (q31_t)0x7fed05cf, (q31_t)0x7fecceec, (q31_t)0x7fec97b9, (q31_t)0x7fec6038, (q31_t)0x7fec2867, (q31_t)0x7febf048, (q31_t)0x7febb7da, + (q31_t)0x7feb7f1d, (q31_t)0x7feb4611, (q31_t)0x7feb0cb6, (q31_t)0x7fead30c, (q31_t)0x7fea9914, (q31_t)0x7fea5ecc, (q31_t)0x7fea2436, (q31_t)0x7fe9e950, + (q31_t)0x7fe9ae1c, (q31_t)0x7fe97299, (q31_t)0x7fe936c7, (q31_t)0x7fe8faa6, (q31_t)0x7fe8be36, (q31_t)0x7fe88177, (q31_t)0x7fe84469, (q31_t)0x7fe8070d, + (q31_t)0x7fe7c961, (q31_t)0x7fe78b67, (q31_t)0x7fe74d1e, (q31_t)0x7fe70e85, (q31_t)0x7fe6cf9e, (q31_t)0x7fe69068, (q31_t)0x7fe650e3, (q31_t)0x7fe61110, + (q31_t)0x7fe5d0ed, (q31_t)0x7fe5907b, (q31_t)0x7fe54fbb, (q31_t)0x7fe50eac, (q31_t)0x7fe4cd4d, (q31_t)0x7fe48ba0, (q31_t)0x7fe449a4, (q31_t)0x7fe40759, + (q31_t)0x7fe3c4bf, (q31_t)0x7fe381d7, (q31_t)0x7fe33e9f, (q31_t)0x7fe2fb19, (q31_t)0x7fe2b743, (q31_t)0x7fe2731f, (q31_t)0x7fe22eac, (q31_t)0x7fe1e9ea, + (q31_t)0x7fe1a4d9, (q31_t)0x7fe15f79, (q31_t)0x7fe119cb, (q31_t)0x7fe0d3cd, (q31_t)0x7fe08d81, (q31_t)0x7fe046e5, (q31_t)0x7fdffffb, (q31_t)0x7fdfb8c2, + (q31_t)0x7fdf713a, (q31_t)0x7fdf2963, (q31_t)0x7fdee13e, (q31_t)0x7fde98c9, (q31_t)0x7fde5006, (q31_t)0x7fde06f3, (q31_t)0x7fddbd92, (q31_t)0x7fdd73e2, + (q31_t)0x7fdd29e3, (q31_t)0x7fdcdf95, (q31_t)0x7fdc94f9, (q31_t)0x7fdc4a0d, (q31_t)0x7fdbfed3, (q31_t)0x7fdbb349, (q31_t)0x7fdb6771, (q31_t)0x7fdb1b4a, + (q31_t)0x7fdaced4, (q31_t)0x7fda820f, (q31_t)0x7fda34fc, (q31_t)0x7fd9e799, (q31_t)0x7fd999e8, (q31_t)0x7fd94be8, (q31_t)0x7fd8fd98, (q31_t)0x7fd8aefa, + (q31_t)0x7fd8600e, (q31_t)0x7fd810d2, (q31_t)0x7fd7c147, (q31_t)0x7fd7716e, (q31_t)0x7fd72146, (q31_t)0x7fd6d0cf, (q31_t)0x7fd68009, (q31_t)0x7fd62ef4, + (q31_t)0x7fd5dd90, (q31_t)0x7fd58bdd, (q31_t)0x7fd539dc, (q31_t)0x7fd4e78c, (q31_t)0x7fd494ed, (q31_t)0x7fd441ff, (q31_t)0x7fd3eec2, (q31_t)0x7fd39b36, + (q31_t)0x7fd3475c, (q31_t)0x7fd2f332, (q31_t)0x7fd29eba, (q31_t)0x7fd249f3, (q31_t)0x7fd1f4dd, (q31_t)0x7fd19f78, (q31_t)0x7fd149c5, (q31_t)0x7fd0f3c2, + (q31_t)0x7fd09d71, (q31_t)0x7fd046d1, (q31_t)0x7fcfefe2, (q31_t)0x7fcf98a4, (q31_t)0x7fcf4117, (q31_t)0x7fcee93c, (q31_t)0x7fce9112, (q31_t)0x7fce3898, + (q31_t)0x7fcddfd0, (q31_t)0x7fcd86b9, (q31_t)0x7fcd2d54, (q31_t)0x7fccd39f, (q31_t)0x7fcc799c, (q31_t)0x7fcc1f4a, (q31_t)0x7fcbc4a9, (q31_t)0x7fcb69b9, + (q31_t)0x7fcb0e7a, (q31_t)0x7fcab2ed, (q31_t)0x7fca5710, (q31_t)0x7fc9fae5, (q31_t)0x7fc99e6b, (q31_t)0x7fc941a2, (q31_t)0x7fc8e48b, (q31_t)0x7fc88724, + (q31_t)0x7fc8296f, (q31_t)0x7fc7cb6b, (q31_t)0x7fc76d18, (q31_t)0x7fc70e76, (q31_t)0x7fc6af86, (q31_t)0x7fc65046, (q31_t)0x7fc5f0b8, (q31_t)0x7fc590db, + (q31_t)0x7fc530af, (q31_t)0x7fc4d035, (q31_t)0x7fc46f6b, (q31_t)0x7fc40e53, (q31_t)0x7fc3acec, (q31_t)0x7fc34b36, (q31_t)0x7fc2e931, (q31_t)0x7fc286de, + (q31_t)0x7fc2243b, (q31_t)0x7fc1c14a, (q31_t)0x7fc15e0a, (q31_t)0x7fc0fa7b, (q31_t)0x7fc0969e, (q31_t)0x7fc03271, (q31_t)0x7fbfcdf6, (q31_t)0x7fbf692c, + (q31_t)0x7fbf0414, (q31_t)0x7fbe9eac, (q31_t)0x7fbe38f6, (q31_t)0x7fbdd2f0, (q31_t)0x7fbd6c9c, (q31_t)0x7fbd05fa, (q31_t)0x7fbc9f08, (q31_t)0x7fbc37c8, + (q31_t)0x7fbbd039, (q31_t)0x7fbb685b, (q31_t)0x7fbb002e, (q31_t)0x7fba97b2, (q31_t)0x7fba2ee8, (q31_t)0x7fb9c5cf, (q31_t)0x7fb95c67, (q31_t)0x7fb8f2b0, + (q31_t)0x7fb888ab, (q31_t)0x7fb81e57, (q31_t)0x7fb7b3b4, (q31_t)0x7fb748c2, (q31_t)0x7fb6dd81, (q31_t)0x7fb671f2, (q31_t)0x7fb60614, (q31_t)0x7fb599e7, + (q31_t)0x7fb52d6b, (q31_t)0x7fb4c0a1, (q31_t)0x7fb45387, (q31_t)0x7fb3e61f, (q31_t)0x7fb37869, (q31_t)0x7fb30a63, (q31_t)0x7fb29c0f, (q31_t)0x7fb22d6c, + (q31_t)0x7fb1be7a, (q31_t)0x7fb14f39, (q31_t)0x7fb0dfaa, (q31_t)0x7fb06fcb, (q31_t)0x7fafff9e, (q31_t)0x7faf8f23, (q31_t)0x7faf1e58, (q31_t)0x7faead3f, + (q31_t)0x7fae3bd7, (q31_t)0x7fadca20, (q31_t)0x7fad581b, (q31_t)0x7face5c6, (q31_t)0x7fac7323, (q31_t)0x7fac0031, (q31_t)0x7fab8cf1, (q31_t)0x7fab1962, + (q31_t)0x7faaa584, (q31_t)0x7faa3157, (q31_t)0x7fa9bcdb, (q31_t)0x7fa94811, (q31_t)0x7fa8d2f8, (q31_t)0x7fa85d90, (q31_t)0x7fa7e7d9, (q31_t)0x7fa771d4, + (q31_t)0x7fa6fb80, (q31_t)0x7fa684dd, (q31_t)0x7fa60dec, (q31_t)0x7fa596ac, (q31_t)0x7fa51f1d, (q31_t)0x7fa4a73f, (q31_t)0x7fa42f12, (q31_t)0x7fa3b697, + (q31_t)0x7fa33dcd, (q31_t)0x7fa2c4b5, (q31_t)0x7fa24b4d, (q31_t)0x7fa1d197, (q31_t)0x7fa15792, (q31_t)0x7fa0dd3f, (q31_t)0x7fa0629c, (q31_t)0x7f9fe7ab, + (q31_t)0x7f9f6c6b, (q31_t)0x7f9ef0dd, (q31_t)0x7f9e7500, (q31_t)0x7f9df8d4, (q31_t)0x7f9d7c59, (q31_t)0x7f9cff90, (q31_t)0x7f9c8278, (q31_t)0x7f9c0511, + (q31_t)0x7f9b875b, (q31_t)0x7f9b0957, (q31_t)0x7f9a8b04, (q31_t)0x7f9a0c62, (q31_t)0x7f998d72, (q31_t)0x7f990e33, (q31_t)0x7f988ea5, (q31_t)0x7f980ec8, + (q31_t)0x7f978e9d, (q31_t)0x7f970e23, (q31_t)0x7f968d5b, (q31_t)0x7f960c43, (q31_t)0x7f958add, (q31_t)0x7f950929, (q31_t)0x7f948725, (q31_t)0x7f9404d3, + (q31_t)0x7f938232, (q31_t)0x7f92ff43, (q31_t)0x7f927c04, (q31_t)0x7f91f878, (q31_t)0x7f91749c, (q31_t)0x7f90f072, (q31_t)0x7f906bf9, (q31_t)0x7f8fe731, + (q31_t)0x7f8f621b, (q31_t)0x7f8edcb6, (q31_t)0x7f8e5702, (q31_t)0x7f8dd0ff, (q31_t)0x7f8d4aae, (q31_t)0x7f8cc40f, (q31_t)0x7f8c3d20, (q31_t)0x7f8bb5e3, + (q31_t)0x7f8b2e57, (q31_t)0x7f8aa67d, (q31_t)0x7f8a1e54, (q31_t)0x7f8995dc, (q31_t)0x7f890d15, (q31_t)0x7f888400, (q31_t)0x7f87fa9c, (q31_t)0x7f8770ea, + (q31_t)0x7f86e6e9, (q31_t)0x7f865c99, (q31_t)0x7f85d1fa, (q31_t)0x7f85470d, (q31_t)0x7f84bbd1, (q31_t)0x7f843047, (q31_t)0x7f83a46e, (q31_t)0x7f831846, + (q31_t)0x7f828bcf, (q31_t)0x7f81ff0a, (q31_t)0x7f8171f6, (q31_t)0x7f80e494, (q31_t)0x7f8056e3, (q31_t)0x7f7fc8e3, (q31_t)0x7f7f3a95, (q31_t)0x7f7eabf8, + (q31_t)0x7f7e1d0c, (q31_t)0x7f7d8dd2, (q31_t)0x7f7cfe49, (q31_t)0x7f7c6e71, (q31_t)0x7f7bde4b, (q31_t)0x7f7b4dd6, (q31_t)0x7f7abd13, (q31_t)0x7f7a2c01, + (q31_t)0x7f799aa0, (q31_t)0x7f7908f0, (q31_t)0x7f7876f2, (q31_t)0x7f77e4a6, (q31_t)0x7f77520a, (q31_t)0x7f76bf21, (q31_t)0x7f762be8, (q31_t)0x7f759861, + (q31_t)0x7f75048b, (q31_t)0x7f747067, (q31_t)0x7f73dbf4, (q31_t)0x7f734732, (q31_t)0x7f72b222, (q31_t)0x7f721cc3, (q31_t)0x7f718715, (q31_t)0x7f70f119, + (q31_t)0x7f705ace, (q31_t)0x7f6fc435, (q31_t)0x7f6f2d4d, (q31_t)0x7f6e9617, (q31_t)0x7f6dfe91, (q31_t)0x7f6d66be, (q31_t)0x7f6cce9b, (q31_t)0x7f6c362a, + (q31_t)0x7f6b9d6b, (q31_t)0x7f6b045d, (q31_t)0x7f6a6b00, (q31_t)0x7f69d154, (q31_t)0x7f69375a, (q31_t)0x7f689d12, (q31_t)0x7f68027b, (q31_t)0x7f676795, + (q31_t)0x7f66cc61, (q31_t)0x7f6630de, (q31_t)0x7f65950c, (q31_t)0x7f64f8ec, (q31_t)0x7f645c7d, (q31_t)0x7f63bfc0, (q31_t)0x7f6322b4, (q31_t)0x7f62855a, + (q31_t)0x7f61e7b1, (q31_t)0x7f6149b9, (q31_t)0x7f60ab73, (q31_t)0x7f600cdf, (q31_t)0x7f5f6dfb, (q31_t)0x7f5ecec9, (q31_t)0x7f5e2f49, (q31_t)0x7f5d8f7a, + (q31_t)0x7f5cef5c, (q31_t)0x7f5c4ef0, (q31_t)0x7f5bae36, (q31_t)0x7f5b0d2c, (q31_t)0x7f5a6bd5, (q31_t)0x7f59ca2e, (q31_t)0x7f592839, (q31_t)0x7f5885f6, + (q31_t)0x7f57e364, (q31_t)0x7f574083, (q31_t)0x7f569d54, (q31_t)0x7f55f9d6, (q31_t)0x7f55560a, (q31_t)0x7f54b1ef, (q31_t)0x7f540d86, (q31_t)0x7f5368ce, + (q31_t)0x7f52c3c8, (q31_t)0x7f521e73, (q31_t)0x7f5178cf, (q31_t)0x7f50d2dd, (q31_t)0x7f502c9d, (q31_t)0x7f4f860e, (q31_t)0x7f4edf30, (q31_t)0x7f4e3804, + (q31_t)0x7f4d9089, (q31_t)0x7f4ce8c0, (q31_t)0x7f4c40a8, (q31_t)0x7f4b9842, (q31_t)0x7f4aef8d, (q31_t)0x7f4a468a, (q31_t)0x7f499d38, (q31_t)0x7f48f398, + (q31_t)0x7f4849a9, (q31_t)0x7f479f6c, (q31_t)0x7f46f4e0, (q31_t)0x7f464a06, (q31_t)0x7f459edd, (q31_t)0x7f44f365, (q31_t)0x7f44479f, (q31_t)0x7f439b8b, + (q31_t)0x7f42ef28, (q31_t)0x7f424277, (q31_t)0x7f419577, (q31_t)0x7f40e828, (q31_t)0x7f403a8b, (q31_t)0x7f3f8ca0, (q31_t)0x7f3ede66, (q31_t)0x7f3e2fde, + (q31_t)0x7f3d8107, (q31_t)0x7f3cd1e2, (q31_t)0x7f3c226e, (q31_t)0x7f3b72ab, (q31_t)0x7f3ac29b, (q31_t)0x7f3a123b, (q31_t)0x7f39618e, (q31_t)0x7f38b091, + (q31_t)0x7f37ff47, (q31_t)0x7f374dad, (q31_t)0x7f369bc6, (q31_t)0x7f35e990, (q31_t)0x7f35370b, (q31_t)0x7f348438, (q31_t)0x7f33d116, (q31_t)0x7f331da6, + (q31_t)0x7f3269e8, (q31_t)0x7f31b5db, (q31_t)0x7f31017f, (q31_t)0x7f304cd6, (q31_t)0x7f2f97dd, (q31_t)0x7f2ee296, (q31_t)0x7f2e2d01, (q31_t)0x7f2d771e, + (q31_t)0x7f2cc0eb, (q31_t)0x7f2c0a6b, (q31_t)0x7f2b539c, (q31_t)0x7f2a9c7e, (q31_t)0x7f29e512, (q31_t)0x7f292d58, (q31_t)0x7f28754f, (q31_t)0x7f27bcf8, + (q31_t)0x7f270452, (q31_t)0x7f264b5e, (q31_t)0x7f25921c, (q31_t)0x7f24d88b, (q31_t)0x7f241eab, (q31_t)0x7f23647e, (q31_t)0x7f22aa01, (q31_t)0x7f21ef37, + (q31_t)0x7f21341e, (q31_t)0x7f2078b6, (q31_t)0x7f1fbd00, (q31_t)0x7f1f00fc, (q31_t)0x7f1e44a9, (q31_t)0x7f1d8808, (q31_t)0x7f1ccb18, (q31_t)0x7f1c0dda, + (q31_t)0x7f1b504e, (q31_t)0x7f1a9273, (q31_t)0x7f19d44a, (q31_t)0x7f1915d2, (q31_t)0x7f18570c, (q31_t)0x7f1797f8, (q31_t)0x7f16d895, (q31_t)0x7f1618e4, + (q31_t)0x7f1558e4, (q31_t)0x7f149896, (q31_t)0x7f13d7fa, (q31_t)0x7f13170f, (q31_t)0x7f1255d6, (q31_t)0x7f11944f, (q31_t)0x7f10d279, (q31_t)0x7f101054, + (q31_t)0x7f0f4de2, (q31_t)0x7f0e8b21, (q31_t)0x7f0dc811, (q31_t)0x7f0d04b3, (q31_t)0x7f0c4107, (q31_t)0x7f0b7d0d, (q31_t)0x7f0ab8c4, (q31_t)0x7f09f42d, + (q31_t)0x7f092f47, (q31_t)0x7f086a13, (q31_t)0x7f07a491, (q31_t)0x7f06dec0, (q31_t)0x7f0618a1, (q31_t)0x7f055233, (q31_t)0x7f048b78, (q31_t)0x7f03c46d, + (q31_t)0x7f02fd15, (q31_t)0x7f02356e, (q31_t)0x7f016d79, (q31_t)0x7f00a535, (q31_t)0x7effdca4, (q31_t)0x7eff13c3, (q31_t)0x7efe4a95, (q31_t)0x7efd8118, + (q31_t)0x7efcb74d, (q31_t)0x7efbed33, (q31_t)0x7efb22cb, (q31_t)0x7efa5815, (q31_t)0x7ef98d11, (q31_t)0x7ef8c1be, (q31_t)0x7ef7f61d, (q31_t)0x7ef72a2d, + (q31_t)0x7ef65def, (q31_t)0x7ef59163, (q31_t)0x7ef4c489, (q31_t)0x7ef3f760, (q31_t)0x7ef329e9, (q31_t)0x7ef25c24, (q31_t)0x7ef18e10, (q31_t)0x7ef0bfae, + (q31_t)0x7eeff0fe, (q31_t)0x7eef21ff, (q31_t)0x7eee52b2, (q31_t)0x7eed8317, (q31_t)0x7eecb32d, (q31_t)0x7eebe2f6, (q31_t)0x7eeb1270, (q31_t)0x7eea419b, + (q31_t)0x7ee97079, (q31_t)0x7ee89f08, (q31_t)0x7ee7cd49, (q31_t)0x7ee6fb3b, (q31_t)0x7ee628df, (q31_t)0x7ee55635, (q31_t)0x7ee4833d, (q31_t)0x7ee3aff6, + (q31_t)0x7ee2dc61, (q31_t)0x7ee2087e, (q31_t)0x7ee1344d, (q31_t)0x7ee05fcd, (q31_t)0x7edf8aff, (q31_t)0x7edeb5e3, (q31_t)0x7edde079, (q31_t)0x7edd0ac0, + (q31_t)0x7edc34b9, (q31_t)0x7edb5e64, (q31_t)0x7eda87c0, (q31_t)0x7ed9b0ce, (q31_t)0x7ed8d98e, (q31_t)0x7ed80200, (q31_t)0x7ed72a24, (q31_t)0x7ed651f9, + (q31_t)0x7ed57980, (q31_t)0x7ed4a0b9, (q31_t)0x7ed3c7a3, (q31_t)0x7ed2ee40, (q31_t)0x7ed2148e, (q31_t)0x7ed13a8e, (q31_t)0x7ed0603f, (q31_t)0x7ecf85a3, + (q31_t)0x7eceaab8, (q31_t)0x7ecdcf7f, (q31_t)0x7eccf3f8, (q31_t)0x7ecc1822, (q31_t)0x7ecb3bff, (q31_t)0x7eca5f8d, (q31_t)0x7ec982cd, (q31_t)0x7ec8a5bf, + (q31_t)0x7ec7c862, (q31_t)0x7ec6eab7, (q31_t)0x7ec60cbe, (q31_t)0x7ec52e77, (q31_t)0x7ec44fe2, (q31_t)0x7ec370fe, (q31_t)0x7ec291cd, (q31_t)0x7ec1b24d, + (q31_t)0x7ec0d27f, (q31_t)0x7ebff263, (q31_t)0x7ebf11f8, (q31_t)0x7ebe313f, (q31_t)0x7ebd5039, (q31_t)0x7ebc6ee4, (q31_t)0x7ebb8d40, (q31_t)0x7ebaab4f, + (q31_t)0x7eb9c910, (q31_t)0x7eb8e682, (q31_t)0x7eb803a6, (q31_t)0x7eb7207c, (q31_t)0x7eb63d04, (q31_t)0x7eb5593d, (q31_t)0x7eb47529, (q31_t)0x7eb390c6, + (q31_t)0x7eb2ac15, (q31_t)0x7eb1c716, (q31_t)0x7eb0e1c9, (q31_t)0x7eaffc2e, (q31_t)0x7eaf1645, (q31_t)0x7eae300d, (q31_t)0x7ead4987, (q31_t)0x7eac62b3, + (q31_t)0x7eab7b91, (q31_t)0x7eaa9421, (q31_t)0x7ea9ac63, (q31_t)0x7ea8c457, (q31_t)0x7ea7dbfc, (q31_t)0x7ea6f353, (q31_t)0x7ea60a5d, (q31_t)0x7ea52118, + (q31_t)0x7ea43785, (q31_t)0x7ea34da4, (q31_t)0x7ea26374, (q31_t)0x7ea178f7, (q31_t)0x7ea08e2b, (q31_t)0x7e9fa312, (q31_t)0x7e9eb7aa, (q31_t)0x7e9dcbf4, + (q31_t)0x7e9cdff0, (q31_t)0x7e9bf39e, (q31_t)0x7e9b06fe, (q31_t)0x7e9a1a10, (q31_t)0x7e992cd4, (q31_t)0x7e983f49, (q31_t)0x7e975171, (q31_t)0x7e96634a, + (q31_t)0x7e9574d6, (q31_t)0x7e948613, (q31_t)0x7e939702, (q31_t)0x7e92a7a3, (q31_t)0x7e91b7f6, (q31_t)0x7e90c7fb, (q31_t)0x7e8fd7b2, (q31_t)0x7e8ee71b, + (q31_t)0x7e8df636, (q31_t)0x7e8d0502, (q31_t)0x7e8c1381, (q31_t)0x7e8b21b1, (q31_t)0x7e8a2f94, (q31_t)0x7e893d28, (q31_t)0x7e884a6f, (q31_t)0x7e875767, + (q31_t)0x7e866411, (q31_t)0x7e85706d, (q31_t)0x7e847c7c, (q31_t)0x7e83883c, (q31_t)0x7e8293ae, (q31_t)0x7e819ed2, (q31_t)0x7e80a9a8, (q31_t)0x7e7fb430, + (q31_t)0x7e7ebe6a, (q31_t)0x7e7dc856, (q31_t)0x7e7cd1f4, (q31_t)0x7e7bdb44, (q31_t)0x7e7ae446, (q31_t)0x7e79ecf9, (q31_t)0x7e78f55f, (q31_t)0x7e77fd77, + (q31_t)0x7e770541, (q31_t)0x7e760cbd, (q31_t)0x7e7513ea, (q31_t)0x7e741aca, (q31_t)0x7e73215c, (q31_t)0x7e7227a0, (q31_t)0x7e712d96, (q31_t)0x7e70333d, + (q31_t)0x7e6f3897, (q31_t)0x7e6e3da3, (q31_t)0x7e6d4261, (q31_t)0x7e6c46d1, (q31_t)0x7e6b4af2, (q31_t)0x7e6a4ec6, (q31_t)0x7e69524c, (q31_t)0x7e685584, + (q31_t)0x7e67586e, (q31_t)0x7e665b0a, (q31_t)0x7e655d58, (q31_t)0x7e645f58, (q31_t)0x7e63610a, (q31_t)0x7e62626e, (q31_t)0x7e616384, (q31_t)0x7e60644c, + (q31_t)0x7e5f64c7, (q31_t)0x7e5e64f3, (q31_t)0x7e5d64d1, (q31_t)0x7e5c6461, (q31_t)0x7e5b63a4, (q31_t)0x7e5a6298, (q31_t)0x7e59613f, (q31_t)0x7e585f97, + (q31_t)0x7e575da2, (q31_t)0x7e565b5f, (q31_t)0x7e5558ce, (q31_t)0x7e5455ef, (q31_t)0x7e5352c1, (q31_t)0x7e524f46, (q31_t)0x7e514b7e, (q31_t)0x7e504767, + (q31_t)0x7e4f4302, (q31_t)0x7e4e3e4f, (q31_t)0x7e4d394f, (q31_t)0x7e4c3400, (q31_t)0x7e4b2e64, (q31_t)0x7e4a287a, (q31_t)0x7e492241, (q31_t)0x7e481bbb, + (q31_t)0x7e4714e7, (q31_t)0x7e460dc5, (q31_t)0x7e450656, (q31_t)0x7e43fe98, (q31_t)0x7e42f68c, (q31_t)0x7e41ee33, (q31_t)0x7e40e58c, (q31_t)0x7e3fdc97, + (q31_t)0x7e3ed353, (q31_t)0x7e3dc9c3, (q31_t)0x7e3cbfe4, (q31_t)0x7e3bb5b7, (q31_t)0x7e3aab3c, (q31_t)0x7e39a074, (q31_t)0x7e38955e, (q31_t)0x7e3789fa, + (q31_t)0x7e367e48, (q31_t)0x7e357248, (q31_t)0x7e3465fa, (q31_t)0x7e33595e, (q31_t)0x7e324c75, (q31_t)0x7e313f3e, (q31_t)0x7e3031b9, (q31_t)0x7e2f23e6, + (q31_t)0x7e2e15c5, (q31_t)0x7e2d0756, (q31_t)0x7e2bf89a, (q31_t)0x7e2ae990, (q31_t)0x7e29da38, (q31_t)0x7e28ca92, (q31_t)0x7e27ba9e, (q31_t)0x7e26aa5d, + (q31_t)0x7e2599cd, (q31_t)0x7e2488f0, (q31_t)0x7e2377c5, (q31_t)0x7e22664c, (q31_t)0x7e215486, (q31_t)0x7e204271, (q31_t)0x7e1f300f, (q31_t)0x7e1e1d5f, + (q31_t)0x7e1d0a61, (q31_t)0x7e1bf716, (q31_t)0x7e1ae37c, (q31_t)0x7e19cf95, (q31_t)0x7e18bb60, (q31_t)0x7e17a6dd, (q31_t)0x7e16920d, (q31_t)0x7e157cee, + (q31_t)0x7e146782, (q31_t)0x7e1351c9, (q31_t)0x7e123bc1, (q31_t)0x7e11256c, (q31_t)0x7e100ec8, (q31_t)0x7e0ef7d7, (q31_t)0x7e0de099, (q31_t)0x7e0cc90c, + (q31_t)0x7e0bb132, (q31_t)0x7e0a990a, (q31_t)0x7e098095, (q31_t)0x7e0867d1, (q31_t)0x7e074ec0, (q31_t)0x7e063561, (q31_t)0x7e051bb4, (q31_t)0x7e0401ba, + (q31_t)0x7e02e772, (q31_t)0x7e01ccdc, (q31_t)0x7e00b1f9, (q31_t)0x7dff96c7, (q31_t)0x7dfe7b48, (q31_t)0x7dfd5f7b, (q31_t)0x7dfc4361, (q31_t)0x7dfb26f9, + (q31_t)0x7dfa0a43, (q31_t)0x7df8ed3f, (q31_t)0x7df7cfee, (q31_t)0x7df6b24f, (q31_t)0x7df59462, (q31_t)0x7df47628, (q31_t)0x7df357a0, (q31_t)0x7df238ca, + (q31_t)0x7df119a7, (q31_t)0x7deffa35, (q31_t)0x7deeda77, (q31_t)0x7dedba6a, (q31_t)0x7dec9a10, (q31_t)0x7deb7968, (q31_t)0x7dea5872, (q31_t)0x7de9372f, + (q31_t)0x7de8159e, (q31_t)0x7de6f3c0, (q31_t)0x7de5d193, (q31_t)0x7de4af1a, (q31_t)0x7de38c52, (q31_t)0x7de2693d, (q31_t)0x7de145da, (q31_t)0x7de02229, + (q31_t)0x7ddefe2b, (q31_t)0x7dddd9e0, (q31_t)0x7ddcb546, (q31_t)0x7ddb905f, (q31_t)0x7dda6b2a, (q31_t)0x7dd945a8, (q31_t)0x7dd81fd8, (q31_t)0x7dd6f9ba, + (q31_t)0x7dd5d34f, (q31_t)0x7dd4ac96, (q31_t)0x7dd38590, (q31_t)0x7dd25e3c, (q31_t)0x7dd1369a, (q31_t)0x7dd00eab, (q31_t)0x7dcee66e, (q31_t)0x7dcdbde3, + (q31_t)0x7dcc950b, (q31_t)0x7dcb6be6, (q31_t)0x7dca4272, (q31_t)0x7dc918b1, (q31_t)0x7dc7eea3, (q31_t)0x7dc6c447, (q31_t)0x7dc5999d, (q31_t)0x7dc46ea6, + (q31_t)0x7dc34361, (q31_t)0x7dc217cf, (q31_t)0x7dc0ebef, (q31_t)0x7dbfbfc1, (q31_t)0x7dbe9346, (q31_t)0x7dbd667d, (q31_t)0x7dbc3967, (q31_t)0x7dbb0c03, + (q31_t)0x7db9de52, (q31_t)0x7db8b053, (q31_t)0x7db78207, (q31_t)0x7db6536d, (q31_t)0x7db52485, (q31_t)0x7db3f550, (q31_t)0x7db2c5cd, (q31_t)0x7db195fd, + (q31_t)0x7db065df, (q31_t)0x7daf3574, (q31_t)0x7dae04bb, (q31_t)0x7dacd3b5, (q31_t)0x7daba261, (q31_t)0x7daa70c0, (q31_t)0x7da93ed1, (q31_t)0x7da80c95, + (q31_t)0x7da6da0b, (q31_t)0x7da5a733, (q31_t)0x7da4740e, (q31_t)0x7da3409c, (q31_t)0x7da20cdc, (q31_t)0x7da0d8cf, (q31_t)0x7d9fa474, (q31_t)0x7d9e6fcb, + (q31_t)0x7d9d3ad6, (q31_t)0x7d9c0592, (q31_t)0x7d9ad001, (q31_t)0x7d999a23, (q31_t)0x7d9863f7, (q31_t)0x7d972d7e, (q31_t)0x7d95f6b7, (q31_t)0x7d94bfa3, + (q31_t)0x7d938841, (q31_t)0x7d925092, (q31_t)0x7d911896, (q31_t)0x7d8fe04c, (q31_t)0x7d8ea7b4, (q31_t)0x7d8d6ecf, (q31_t)0x7d8c359d, (q31_t)0x7d8afc1d, + (q31_t)0x7d89c250, (q31_t)0x7d888835, (q31_t)0x7d874dcd, (q31_t)0x7d861317, (q31_t)0x7d84d814, (q31_t)0x7d839cc4, (q31_t)0x7d826126, (q31_t)0x7d81253a, + (q31_t)0x7d7fe902, (q31_t)0x7d7eac7c, (q31_t)0x7d7d6fa8, (q31_t)0x7d7c3287, (q31_t)0x7d7af519, (q31_t)0x7d79b75d, (q31_t)0x7d787954, (q31_t)0x7d773afd, + (q31_t)0x7d75fc59, (q31_t)0x7d74bd68, (q31_t)0x7d737e29, (q31_t)0x7d723e9d, (q31_t)0x7d70fec4, (q31_t)0x7d6fbe9d, (q31_t)0x7d6e7e29, (q31_t)0x7d6d3d67, + (q31_t)0x7d6bfc58, (q31_t)0x7d6abafc, (q31_t)0x7d697952, (q31_t)0x7d68375b, (q31_t)0x7d66f517, (q31_t)0x7d65b285, (q31_t)0x7d646fa6, (q31_t)0x7d632c79, + (q31_t)0x7d61e8ff, (q31_t)0x7d60a538, (q31_t)0x7d5f6124, (q31_t)0x7d5e1cc2, (q31_t)0x7d5cd813, (q31_t)0x7d5b9316, (q31_t)0x7d5a4dcc, (q31_t)0x7d590835, + (q31_t)0x7d57c251, (q31_t)0x7d567c1f, (q31_t)0x7d5535a0, (q31_t)0x7d53eed3, (q31_t)0x7d52a7ba, (q31_t)0x7d516053, (q31_t)0x7d50189e, (q31_t)0x7d4ed09d, + (q31_t)0x7d4d884e, (q31_t)0x7d4c3fb1, (q31_t)0x7d4af6c8, (q31_t)0x7d49ad91, (q31_t)0x7d48640d, (q31_t)0x7d471a3c, (q31_t)0x7d45d01d, (q31_t)0x7d4485b1, + (q31_t)0x7d433af8, (q31_t)0x7d41eff1, (q31_t)0x7d40a49e, (q31_t)0x7d3f58fd, (q31_t)0x7d3e0d0e, (q31_t)0x7d3cc0d3, (q31_t)0x7d3b744a, (q31_t)0x7d3a2774, + (q31_t)0x7d38da51, (q31_t)0x7d378ce0, (q31_t)0x7d363f23, (q31_t)0x7d34f118, (q31_t)0x7d33a2bf, (q31_t)0x7d32541a, (q31_t)0x7d310527, (q31_t)0x7d2fb5e7, + (q31_t)0x7d2e665a, (q31_t)0x7d2d1680, (q31_t)0x7d2bc659, (q31_t)0x7d2a75e4, (q31_t)0x7d292522, (q31_t)0x7d27d413, (q31_t)0x7d2682b6, (q31_t)0x7d25310d, + (q31_t)0x7d23df16, (q31_t)0x7d228cd2, (q31_t)0x7d213a41, (q31_t)0x7d1fe762, (q31_t)0x7d1e9437, (q31_t)0x7d1d40be, (q31_t)0x7d1becf8, (q31_t)0x7d1a98e5, + (q31_t)0x7d194485, (q31_t)0x7d17efd8, (q31_t)0x7d169add, (q31_t)0x7d154595, (q31_t)0x7d13f001, (q31_t)0x7d129a1f, (q31_t)0x7d1143ef, (q31_t)0x7d0fed73, + (q31_t)0x7d0e96aa, (q31_t)0x7d0d3f93, (q31_t)0x7d0be82f, (q31_t)0x7d0a907e, (q31_t)0x7d093880, (q31_t)0x7d07e035, (q31_t)0x7d06879d, (q31_t)0x7d052eb8, + (q31_t)0x7d03d585, (q31_t)0x7d027c05, (q31_t)0x7d012239, (q31_t)0x7cffc81f, (q31_t)0x7cfe6db8, (q31_t)0x7cfd1304, (q31_t)0x7cfbb803, (q31_t)0x7cfa5cb4, + (q31_t)0x7cf90119, (q31_t)0x7cf7a531, (q31_t)0x7cf648fb, (q31_t)0x7cf4ec79, (q31_t)0x7cf38fa9, (q31_t)0x7cf2328c, (q31_t)0x7cf0d522, (q31_t)0x7cef776b, + (q31_t)0x7cee1967, (q31_t)0x7cecbb16, (q31_t)0x7ceb5c78, (q31_t)0x7ce9fd8d, (q31_t)0x7ce89e55, (q31_t)0x7ce73ed0, (q31_t)0x7ce5defd, (q31_t)0x7ce47ede, + (q31_t)0x7ce31e72, (q31_t)0x7ce1bdb8, (q31_t)0x7ce05cb2, (q31_t)0x7cdefb5e, (q31_t)0x7cdd99be, (q31_t)0x7cdc37d0, (q31_t)0x7cdad596, (q31_t)0x7cd9730e, + (q31_t)0x7cd8103a, (q31_t)0x7cd6ad18, (q31_t)0x7cd549aa, (q31_t)0x7cd3e5ee, (q31_t)0x7cd281e5, (q31_t)0x7cd11d90, (q31_t)0x7ccfb8ed, (q31_t)0x7cce53fe, + (q31_t)0x7ccceec1, (q31_t)0x7ccb8937, (q31_t)0x7cca2361, (q31_t)0x7cc8bd3d, (q31_t)0x7cc756cd, (q31_t)0x7cc5f010, (q31_t)0x7cc48905, (q31_t)0x7cc321ae, + (q31_t)0x7cc1ba09, (q31_t)0x7cc05218, (q31_t)0x7cbee9da, (q31_t)0x7cbd814f, (q31_t)0x7cbc1877, (q31_t)0x7cbaaf51, (q31_t)0x7cb945df, (q31_t)0x7cb7dc20, + (q31_t)0x7cb67215, (q31_t)0x7cb507bc, (q31_t)0x7cb39d16, (q31_t)0x7cb23223, (q31_t)0x7cb0c6e4, (q31_t)0x7caf5b57, (q31_t)0x7cadef7e, (q31_t)0x7cac8358, + (q31_t)0x7cab16e4, (q31_t)0x7ca9aa24, (q31_t)0x7ca83d17, (q31_t)0x7ca6cfbd, (q31_t)0x7ca56216, (q31_t)0x7ca3f423, (q31_t)0x7ca285e2, (q31_t)0x7ca11755, + (q31_t)0x7c9fa87a, (q31_t)0x7c9e3953, (q31_t)0x7c9cc9df, (q31_t)0x7c9b5a1e, (q31_t)0x7c99ea10, (q31_t)0x7c9879b6, (q31_t)0x7c97090e, (q31_t)0x7c95981a, + (q31_t)0x7c9426d8, (q31_t)0x7c92b54a, (q31_t)0x7c91436f, (q31_t)0x7c8fd148, (q31_t)0x7c8e5ed3, (q31_t)0x7c8cec12, (q31_t)0x7c8b7903, (q31_t)0x7c8a05a8, + (q31_t)0x7c889200, (q31_t)0x7c871e0c, (q31_t)0x7c85a9ca, (q31_t)0x7c84353c, (q31_t)0x7c82c060, (q31_t)0x7c814b39, (q31_t)0x7c7fd5c4, (q31_t)0x7c7e6002, + (q31_t)0x7c7ce9f4, (q31_t)0x7c7b7399, (q31_t)0x7c79fcf1, (q31_t)0x7c7885fc, (q31_t)0x7c770eba, (q31_t)0x7c75972c, (q31_t)0x7c741f51, (q31_t)0x7c72a729, + (q31_t)0x7c712eb5, (q31_t)0x7c6fb5f3, (q31_t)0x7c6e3ce5, (q31_t)0x7c6cc38a, (q31_t)0x7c6b49e3, (q31_t)0x7c69cfee, (q31_t)0x7c6855ad, (q31_t)0x7c66db1f, + (q31_t)0x7c656045, (q31_t)0x7c63e51e, (q31_t)0x7c6269aa, (q31_t)0x7c60ede9, (q31_t)0x7c5f71db, (q31_t)0x7c5df581, (q31_t)0x7c5c78da, (q31_t)0x7c5afbe6, + (q31_t)0x7c597ea6, (q31_t)0x7c580119, (q31_t)0x7c56833f, (q31_t)0x7c550519, (q31_t)0x7c5386a6, (q31_t)0x7c5207e6, (q31_t)0x7c5088d9, (q31_t)0x7c4f0980, + (q31_t)0x7c4d89da, (q31_t)0x7c4c09e8, (q31_t)0x7c4a89a8, (q31_t)0x7c49091c, (q31_t)0x7c478844, (q31_t)0x7c46071f, (q31_t)0x7c4485ad, (q31_t)0x7c4303ee, + (q31_t)0x7c4181e3, (q31_t)0x7c3fff8b, (q31_t)0x7c3e7ce7, (q31_t)0x7c3cf9f5, (q31_t)0x7c3b76b8, (q31_t)0x7c39f32d, (q31_t)0x7c386f56, (q31_t)0x7c36eb33, + (q31_t)0x7c3566c2, (q31_t)0x7c33e205, (q31_t)0x7c325cfc, (q31_t)0x7c30d7a6, (q31_t)0x7c2f5203, (q31_t)0x7c2dcc14, (q31_t)0x7c2c45d8, (q31_t)0x7c2abf4f, + (q31_t)0x7c29387a, (q31_t)0x7c27b158, (q31_t)0x7c2629ea, (q31_t)0x7c24a22f, (q31_t)0x7c231a28, (q31_t)0x7c2191d4, (q31_t)0x7c200933, (q31_t)0x7c1e8046, + (q31_t)0x7c1cf70c, (q31_t)0x7c1b6d86, (q31_t)0x7c19e3b3, (q31_t)0x7c185994, (q31_t)0x7c16cf28, (q31_t)0x7c15446f, (q31_t)0x7c13b96a, (q31_t)0x7c122e19, + (q31_t)0x7c10a27b, (q31_t)0x7c0f1690, (q31_t)0x7c0d8a59, (q31_t)0x7c0bfdd5, (q31_t)0x7c0a7105, (q31_t)0x7c08e3e8, (q31_t)0x7c07567f, (q31_t)0x7c05c8c9, + (q31_t)0x7c043ac7, (q31_t)0x7c02ac78, (q31_t)0x7c011ddd, (q31_t)0x7bff8ef5, (q31_t)0x7bfdffc1, (q31_t)0x7bfc7041, (q31_t)0x7bfae073, (q31_t)0x7bf9505a, + (q31_t)0x7bf7bff4, (q31_t)0x7bf62f41, (q31_t)0x7bf49e42, (q31_t)0x7bf30cf6, (q31_t)0x7bf17b5e, (q31_t)0x7befe97a, (q31_t)0x7bee5749, (q31_t)0x7becc4cc, + (q31_t)0x7beb3202, (q31_t)0x7be99eec, (q31_t)0x7be80b89, (q31_t)0x7be677da, (q31_t)0x7be4e3df, (q31_t)0x7be34f97, (q31_t)0x7be1bb02, (q31_t)0x7be02621, + (q31_t)0x7bde90f4, (q31_t)0x7bdcfb7b, (q31_t)0x7bdb65b5, (q31_t)0x7bd9cfa2, (q31_t)0x7bd83944, (q31_t)0x7bd6a298, (q31_t)0x7bd50ba1, (q31_t)0x7bd3745d, + (q31_t)0x7bd1dccc, (q31_t)0x7bd044f0, (q31_t)0x7bceacc7, (q31_t)0x7bcd1451, (q31_t)0x7bcb7b8f, (q31_t)0x7bc9e281, (q31_t)0x7bc84927, (q31_t)0x7bc6af80, + (q31_t)0x7bc5158c, (q31_t)0x7bc37b4d, (q31_t)0x7bc1e0c1, (q31_t)0x7bc045e9, (q31_t)0x7bbeaac4, (q31_t)0x7bbd0f53, (q31_t)0x7bbb7396, (q31_t)0x7bb9d78c, + (q31_t)0x7bb83b36, (q31_t)0x7bb69e94, (q31_t)0x7bb501a5, (q31_t)0x7bb3646a, (q31_t)0x7bb1c6e3, (q31_t)0x7bb02910, (q31_t)0x7bae8af0, (q31_t)0x7bacec84, + (q31_t)0x7bab4dcc, (q31_t)0x7ba9aec7, (q31_t)0x7ba80f76, (q31_t)0x7ba66fd9, (q31_t)0x7ba4cfef, (q31_t)0x7ba32fba, (q31_t)0x7ba18f38, (q31_t)0x7b9fee69, + (q31_t)0x7b9e4d4f, (q31_t)0x7b9cabe8, (q31_t)0x7b9b0a35, (q31_t)0x7b996836, (q31_t)0x7b97c5ea, (q31_t)0x7b962352, (q31_t)0x7b94806e, (q31_t)0x7b92dd3e, + (q31_t)0x7b9139c2, (q31_t)0x7b8f95f9, (q31_t)0x7b8df1e4, (q31_t)0x7b8c4d83, (q31_t)0x7b8aa8d6, (q31_t)0x7b8903dc, (q31_t)0x7b875e96, (q31_t)0x7b85b904, + (q31_t)0x7b841326, (q31_t)0x7b826cfc, (q31_t)0x7b80c686, (q31_t)0x7b7f1fc3, (q31_t)0x7b7d78b4, (q31_t)0x7b7bd159, (q31_t)0x7b7a29b2, (q31_t)0x7b7881be, + (q31_t)0x7b76d97f, (q31_t)0x7b7530f3, (q31_t)0x7b73881b, (q31_t)0x7b71def7, (q31_t)0x7b703587, (q31_t)0x7b6e8bcb, (q31_t)0x7b6ce1c2, (q31_t)0x7b6b376e, + (q31_t)0x7b698ccd, (q31_t)0x7b67e1e0, (q31_t)0x7b6636a7, (q31_t)0x7b648b22, (q31_t)0x7b62df51, (q31_t)0x7b613334, (q31_t)0x7b5f86ca, (q31_t)0x7b5dda15, + (q31_t)0x7b5c2d13, (q31_t)0x7b5a7fc6, (q31_t)0x7b58d22c, (q31_t)0x7b572446, (q31_t)0x7b557614, (q31_t)0x7b53c796, (q31_t)0x7b5218cc, (q31_t)0x7b5069b6, + (q31_t)0x7b4eba53, (q31_t)0x7b4d0aa5, (q31_t)0x7b4b5aab, (q31_t)0x7b49aa64, (q31_t)0x7b47f9d2, (q31_t)0x7b4648f3, (q31_t)0x7b4497c9, (q31_t)0x7b42e652, + (q31_t)0x7b413490, (q31_t)0x7b3f8281, (q31_t)0x7b3dd026, (q31_t)0x7b3c1d80, (q31_t)0x7b3a6a8d, (q31_t)0x7b38b74e, (q31_t)0x7b3703c3, (q31_t)0x7b354fed, + (q31_t)0x7b339bca, (q31_t)0x7b31e75b, (q31_t)0x7b3032a0, (q31_t)0x7b2e7d9a, (q31_t)0x7b2cc847, (q31_t)0x7b2b12a8, (q31_t)0x7b295cbe, (q31_t)0x7b27a687, + (q31_t)0x7b25f004, (q31_t)0x7b243936, (q31_t)0x7b22821b, (q31_t)0x7b20cab5, (q31_t)0x7b1f1302, (q31_t)0x7b1d5b04, (q31_t)0x7b1ba2b9, (q31_t)0x7b19ea23, + (q31_t)0x7b183141, (q31_t)0x7b167813, (q31_t)0x7b14be99, (q31_t)0x7b1304d3, (q31_t)0x7b114ac1, (q31_t)0x7b0f9063, (q31_t)0x7b0dd5b9, (q31_t)0x7b0c1ac4, + (q31_t)0x7b0a5f82, (q31_t)0x7b08a3f5, (q31_t)0x7b06e81b, (q31_t)0x7b052bf6, (q31_t)0x7b036f85, (q31_t)0x7b01b2c8, (q31_t)0x7afff5bf, (q31_t)0x7afe386a, + (q31_t)0x7afc7aca, (q31_t)0x7afabcdd, (q31_t)0x7af8fea5, (q31_t)0x7af74021, (q31_t)0x7af58151, (q31_t)0x7af3c235, (q31_t)0x7af202cd, (q31_t)0x7af0431a, + (q31_t)0x7aee831a, (q31_t)0x7aecc2cf, (q31_t)0x7aeb0238, (q31_t)0x7ae94155, (q31_t)0x7ae78026, (q31_t)0x7ae5beac, (q31_t)0x7ae3fce6, (q31_t)0x7ae23ad4, + (q31_t)0x7ae07876, (q31_t)0x7adeb5cc, (q31_t)0x7adcf2d6, (q31_t)0x7adb2f95, (q31_t)0x7ad96c08, (q31_t)0x7ad7a82f, (q31_t)0x7ad5e40a, (q31_t)0x7ad41f9a, + (q31_t)0x7ad25ade, (q31_t)0x7ad095d6, (q31_t)0x7aced082, (q31_t)0x7acd0ae3, (q31_t)0x7acb44f8, (q31_t)0x7ac97ec1, (q31_t)0x7ac7b83e, (q31_t)0x7ac5f170, + (q31_t)0x7ac42a55, (q31_t)0x7ac262ef, (q31_t)0x7ac09b3e, (q31_t)0x7abed341, (q31_t)0x7abd0af7, (q31_t)0x7abb4263, (q31_t)0x7ab97982, (q31_t)0x7ab7b056, + (q31_t)0x7ab5e6de, (q31_t)0x7ab41d1b, (q31_t)0x7ab2530b, (q31_t)0x7ab088b0, (q31_t)0x7aaebe0a, (q31_t)0x7aacf318, (q31_t)0x7aab27da, (q31_t)0x7aa95c50, + (q31_t)0x7aa7907b, (q31_t)0x7aa5c45a, (q31_t)0x7aa3f7ed, (q31_t)0x7aa22b35, (q31_t)0x7aa05e31, (q31_t)0x7a9e90e1, (q31_t)0x7a9cc346, (q31_t)0x7a9af55f, + (q31_t)0x7a99272d, (q31_t)0x7a9758af, (q31_t)0x7a9589e5, (q31_t)0x7a93bad0, (q31_t)0x7a91eb6f, (q31_t)0x7a901bc2, (q31_t)0x7a8e4bca, (q31_t)0x7a8c7b87, + (q31_t)0x7a8aaaf7, (q31_t)0x7a88da1c, (q31_t)0x7a8708f6, (q31_t)0x7a853784, (q31_t)0x7a8365c6, (q31_t)0x7a8193bd, (q31_t)0x7a7fc168, (q31_t)0x7a7deec8, + (q31_t)0x7a7c1bdc, (q31_t)0x7a7a48a4, (q31_t)0x7a787521, (q31_t)0x7a76a153, (q31_t)0x7a74cd38, (q31_t)0x7a72f8d3, (q31_t)0x7a712422, (q31_t)0x7a6f4f25, + (q31_t)0x7a6d79dd, (q31_t)0x7a6ba449, (q31_t)0x7a69ce6a, (q31_t)0x7a67f83f, (q31_t)0x7a6621c9, (q31_t)0x7a644b07, (q31_t)0x7a6273fa, (q31_t)0x7a609ca1, + (q31_t)0x7a5ec4fc, (q31_t)0x7a5ced0d, (q31_t)0x7a5b14d1, (q31_t)0x7a593c4b, (q31_t)0x7a576379, (q31_t)0x7a558a5b, (q31_t)0x7a53b0f2, (q31_t)0x7a51d73d, + (q31_t)0x7a4ffd3d, (q31_t)0x7a4e22f2, (q31_t)0x7a4c485b, (q31_t)0x7a4a6d78, (q31_t)0x7a48924b, (q31_t)0x7a46b6d1, (q31_t)0x7a44db0d, (q31_t)0x7a42fefd, + (q31_t)0x7a4122a1, (q31_t)0x7a3f45fa, (q31_t)0x7a3d6908, (q31_t)0x7a3b8bca, (q31_t)0x7a39ae41, (q31_t)0x7a37d06d, (q31_t)0x7a35f24d, (q31_t)0x7a3413e2, + (q31_t)0x7a32352b, (q31_t)0x7a305629, (q31_t)0x7a2e76dc, (q31_t)0x7a2c9743, (q31_t)0x7a2ab75f, (q31_t)0x7a28d72f, (q31_t)0x7a26f6b4, (q31_t)0x7a2515ee, + (q31_t)0x7a2334dd, (q31_t)0x7a215380, (q31_t)0x7a1f71d7, (q31_t)0x7a1d8fe4, (q31_t)0x7a1bada5, (q31_t)0x7a19cb1b, (q31_t)0x7a17e845, (q31_t)0x7a160524, + (q31_t)0x7a1421b8, (q31_t)0x7a123e01, (q31_t)0x7a1059fe, (q31_t)0x7a0e75b0, (q31_t)0x7a0c9117, (q31_t)0x7a0aac32, (q31_t)0x7a08c702, (q31_t)0x7a06e187, + (q31_t)0x7a04fbc1, (q31_t)0x7a0315af, (q31_t)0x7a012f52, (q31_t)0x79ff48aa, (q31_t)0x79fd61b6, (q31_t)0x79fb7a77, (q31_t)0x79f992ed, (q31_t)0x79f7ab18, + (q31_t)0x79f5c2f8, (q31_t)0x79f3da8c, (q31_t)0x79f1f1d5, (q31_t)0x79f008d3, (q31_t)0x79ee1f86, (q31_t)0x79ec35ed, (q31_t)0x79ea4c09, (q31_t)0x79e861da, + (q31_t)0x79e67760, (q31_t)0x79e48c9b, (q31_t)0x79e2a18a, (q31_t)0x79e0b62e, (q31_t)0x79deca87, (q31_t)0x79dcde95, (q31_t)0x79daf258, (q31_t)0x79d905d0, + (q31_t)0x79d718fc, (q31_t)0x79d52bdd, (q31_t)0x79d33e73, (q31_t)0x79d150be, (q31_t)0x79cf62be, (q31_t)0x79cd7473, (q31_t)0x79cb85dc, (q31_t)0x79c996fb, + (q31_t)0x79c7a7ce, (q31_t)0x79c5b856, (q31_t)0x79c3c893, (q31_t)0x79c1d885, (q31_t)0x79bfe82c, (q31_t)0x79bdf788, (q31_t)0x79bc0698, (q31_t)0x79ba155e, + (q31_t)0x79b823d8, (q31_t)0x79b63207, (q31_t)0x79b43fec, (q31_t)0x79b24d85, (q31_t)0x79b05ad3, (q31_t)0x79ae67d6, (q31_t)0x79ac748e, (q31_t)0x79aa80fb, + (q31_t)0x79a88d1d, (q31_t)0x79a698f4, (q31_t)0x79a4a480, (q31_t)0x79a2afc1, (q31_t)0x79a0bab6, (q31_t)0x799ec561, (q31_t)0x799ccfc1, (q31_t)0x799ad9d5, + (q31_t)0x7998e39f, (q31_t)0x7996ed1e, (q31_t)0x7994f651, (q31_t)0x7992ff3a, (q31_t)0x799107d8, (q31_t)0x798f102a, (q31_t)0x798d1832, (q31_t)0x798b1fef, + (q31_t)0x79892761, (q31_t)0x79872e87, (q31_t)0x79853563, (q31_t)0x79833bf4, (q31_t)0x7981423a, (q31_t)0x797f4835, (q31_t)0x797d4de5, (q31_t)0x797b534a, + (q31_t)0x79795864, (q31_t)0x79775d33, (q31_t)0x797561b8, (q31_t)0x797365f1, (q31_t)0x797169df, (q31_t)0x796f6d83, (q31_t)0x796d70dc, (q31_t)0x796b73e9, + (q31_t)0x796976ac, (q31_t)0x79677924, (q31_t)0x79657b51, (q31_t)0x79637d33, (q31_t)0x79617eca, (q31_t)0x795f8017, (q31_t)0x795d8118, (q31_t)0x795b81cf, + (q31_t)0x7959823b, (q31_t)0x7957825c, (q31_t)0x79558232, (q31_t)0x795381bd, (q31_t)0x795180fe, (q31_t)0x794f7ff3, (q31_t)0x794d7e9e, (q31_t)0x794b7cfe, + (q31_t)0x79497b13, (q31_t)0x794778dd, (q31_t)0x7945765d, (q31_t)0x79437391, (q31_t)0x7941707b, (q31_t)0x793f6d1a, (q31_t)0x793d696f, (q31_t)0x793b6578, + (q31_t)0x79396137, (q31_t)0x79375cab, (q31_t)0x793557d4, (q31_t)0x793352b2, (q31_t)0x79314d46, (q31_t)0x792f478f, (q31_t)0x792d418d, (q31_t)0x792b3b40, + (q31_t)0x792934a9, (q31_t)0x79272dc7, (q31_t)0x7925269a, (q31_t)0x79231f22, (q31_t)0x79211760, (q31_t)0x791f0f53, (q31_t)0x791d06fb, (q31_t)0x791afe59, + (q31_t)0x7918f56c, (q31_t)0x7916ec34, (q31_t)0x7914e2b2, (q31_t)0x7912d8e4, (q31_t)0x7910cecc, (q31_t)0x790ec46a, (q31_t)0x790cb9bd, (q31_t)0x790aaec5, + (q31_t)0x7908a382, (q31_t)0x790697f5, (q31_t)0x79048c1d, (q31_t)0x79027ffa, (q31_t)0x7900738d, (q31_t)0x78fe66d5, (q31_t)0x78fc59d3, (q31_t)0x78fa4c86, + (q31_t)0x78f83eee, (q31_t)0x78f6310c, (q31_t)0x78f422df, (q31_t)0x78f21467, (q31_t)0x78f005a5, (q31_t)0x78edf698, (q31_t)0x78ebe741, (q31_t)0x78e9d79f, + (q31_t)0x78e7c7b2, (q31_t)0x78e5b77b, (q31_t)0x78e3a6f9, (q31_t)0x78e1962d, (q31_t)0x78df8516, (q31_t)0x78dd73b5, (q31_t)0x78db6209, (q31_t)0x78d95012, + (q31_t)0x78d73dd1, (q31_t)0x78d52b46, (q31_t)0x78d31870, (q31_t)0x78d1054f, (q31_t)0x78cef1e4, (q31_t)0x78ccde2e, (q31_t)0x78caca2e, (q31_t)0x78c8b5e3, + (q31_t)0x78c6a14e, (q31_t)0x78c48c6e, (q31_t)0x78c27744, (q31_t)0x78c061cf, (q31_t)0x78be4c10, (q31_t)0x78bc3606, (q31_t)0x78ba1fb2, (q31_t)0x78b80913, + (q31_t)0x78b5f22a, (q31_t)0x78b3daf7, (q31_t)0x78b1c379, (q31_t)0x78afabb0, (q31_t)0x78ad939d, (q31_t)0x78ab7b40, (q31_t)0x78a96298, (q31_t)0x78a749a6, + (q31_t)0x78a53069, (q31_t)0x78a316e2, (q31_t)0x78a0fd11, (q31_t)0x789ee2f5, (q31_t)0x789cc88f, (q31_t)0x789aadde, (q31_t)0x789892e3, (q31_t)0x7896779d, + (q31_t)0x78945c0d, (q31_t)0x78924033, (q31_t)0x7890240e, (q31_t)0x788e07a0, (q31_t)0x788beae6, (q31_t)0x7889cde2, (q31_t)0x7887b094, (q31_t)0x788592fc, + (q31_t)0x78837519, (q31_t)0x788156ec, (q31_t)0x787f3875, (q31_t)0x787d19b3, (q31_t)0x787afaa7, (q31_t)0x7878db50, (q31_t)0x7876bbb0, (q31_t)0x78749bc5, + (q31_t)0x78727b8f, (q31_t)0x78705b10, (q31_t)0x786e3a46, (q31_t)0x786c1932, (q31_t)0x7869f7d3, (q31_t)0x7867d62a, (q31_t)0x7865b437, (q31_t)0x786391fa, + (q31_t)0x78616f72, (q31_t)0x785f4ca1, (q31_t)0x785d2984, (q31_t)0x785b061e, (q31_t)0x7858e26e, (q31_t)0x7856be73, (q31_t)0x78549a2e, (q31_t)0x7852759e, + (q31_t)0x785050c5, (q31_t)0x784e2ba1, (q31_t)0x784c0633, (q31_t)0x7849e07b, (q31_t)0x7847ba79, (q31_t)0x7845942c, (q31_t)0x78436d96, (q31_t)0x784146b5, + (q31_t)0x783f1f8a, (q31_t)0x783cf815, (q31_t)0x783ad055, (q31_t)0x7838a84c, (q31_t)0x78367ff8, (q31_t)0x7834575a, (q31_t)0x78322e72, (q31_t)0x78300540, + (q31_t)0x782ddbc4, (q31_t)0x782bb1fd, (q31_t)0x782987ed, (q31_t)0x78275d92, (q31_t)0x782532ed, (q31_t)0x782307fe, (q31_t)0x7820dcc5, (q31_t)0x781eb142, + (q31_t)0x781c8575, (q31_t)0x781a595d, (q31_t)0x78182cfc, (q31_t)0x78160051, (q31_t)0x7813d35b, (q31_t)0x7811a61b, (q31_t)0x780f7892, (q31_t)0x780d4abe, + (q31_t)0x780b1ca0, (q31_t)0x7808ee38, (q31_t)0x7806bf86, (q31_t)0x7804908a, (q31_t)0x78026145, (q31_t)0x780031b5, (q31_t)0x77fe01db, (q31_t)0x77fbd1b6, + (q31_t)0x77f9a148, (q31_t)0x77f77090, (q31_t)0x77f53f8e, (q31_t)0x77f30e42, (q31_t)0x77f0dcac, (q31_t)0x77eeaacc, (q31_t)0x77ec78a2, (q31_t)0x77ea462e, + (q31_t)0x77e81370, (q31_t)0x77e5e068, (q31_t)0x77e3ad17, (q31_t)0x77e1797b, (q31_t)0x77df4595, (q31_t)0x77dd1165, (q31_t)0x77dadcec, (q31_t)0x77d8a828, + (q31_t)0x77d6731a, (q31_t)0x77d43dc3, (q31_t)0x77d20822, (q31_t)0x77cfd236, (q31_t)0x77cd9c01, (q31_t)0x77cb6582, (q31_t)0x77c92eb9, (q31_t)0x77c6f7a6, + (q31_t)0x77c4c04a, (q31_t)0x77c288a3, (q31_t)0x77c050b2, (q31_t)0x77be1878, (q31_t)0x77bbdff4, (q31_t)0x77b9a726, (q31_t)0x77b76e0e, (q31_t)0x77b534ac, + (q31_t)0x77b2fb00, (q31_t)0x77b0c10b, (q31_t)0x77ae86cc, (q31_t)0x77ac4c43, (q31_t)0x77aa1170, (q31_t)0x77a7d653, (q31_t)0x77a59aec, (q31_t)0x77a35f3c, + (q31_t)0x77a12342, (q31_t)0x779ee6fe, (q31_t)0x779caa70, (q31_t)0x779a6d99, (q31_t)0x77983077, (q31_t)0x7795f30c, (q31_t)0x7793b557, (q31_t)0x77917759, + (q31_t)0x778f3910, (q31_t)0x778cfa7e, (q31_t)0x778abba2, (q31_t)0x77887c7d, (q31_t)0x77863d0d, (q31_t)0x7783fd54, (q31_t)0x7781bd52, (q31_t)0x777f7d05, + (q31_t)0x777d3c6f, (q31_t)0x777afb8f, (q31_t)0x7778ba65, (q31_t)0x777678f2, (q31_t)0x77743735, (q31_t)0x7771f52e, (q31_t)0x776fb2de, (q31_t)0x776d7044, + (q31_t)0x776b2d60, (q31_t)0x7768ea33, (q31_t)0x7766a6bc, (q31_t)0x776462fb, (q31_t)0x77621ef1, (q31_t)0x775fda9d, (q31_t)0x775d95ff, (q31_t)0x775b5118, + (q31_t)0x77590be7, (q31_t)0x7756c66c, (q31_t)0x775480a8, (q31_t)0x77523a9b, (q31_t)0x774ff443, (q31_t)0x774dada2, (q31_t)0x774b66b8, (q31_t)0x77491f84, + (q31_t)0x7746d806, (q31_t)0x7744903f, (q31_t)0x7742482e, (q31_t)0x773fffd4, (q31_t)0x773db730, (q31_t)0x773b6e42, (q31_t)0x7739250b, (q31_t)0x7736db8b, + (q31_t)0x773491c0, (q31_t)0x773247ad, (q31_t)0x772ffd50, (q31_t)0x772db2a9, (q31_t)0x772b67b9, (q31_t)0x77291c7f, (q31_t)0x7726d0fc, (q31_t)0x7724852f, + (q31_t)0x77223919, (q31_t)0x771fecb9, (q31_t)0x771da010, (q31_t)0x771b531d, (q31_t)0x771905e1, (q31_t)0x7716b85b, (q31_t)0x77146a8c, (q31_t)0x77121c74, + (q31_t)0x770fce12, (q31_t)0x770d7f66, (q31_t)0x770b3072, (q31_t)0x7708e133, (q31_t)0x770691ab, (q31_t)0x770441da, (q31_t)0x7701f1c0, (q31_t)0x76ffa15c, + (q31_t)0x76fd50ae, (q31_t)0x76faffb8, (q31_t)0x76f8ae78, (q31_t)0x76f65cee, (q31_t)0x76f40b1b, (q31_t)0x76f1b8ff, (q31_t)0x76ef6699, (q31_t)0x76ed13ea, + (q31_t)0x76eac0f2, (q31_t)0x76e86db0, (q31_t)0x76e61a25, (q31_t)0x76e3c650, (q31_t)0x76e17233, (q31_t)0x76df1dcb, (q31_t)0x76dcc91b, (q31_t)0x76da7421, + (q31_t)0x76d81ede, (q31_t)0x76d5c952, (q31_t)0x76d3737c, (q31_t)0x76d11d5d, (q31_t)0x76cec6f5, (q31_t)0x76cc7043, (q31_t)0x76ca1948, (q31_t)0x76c7c204, + (q31_t)0x76c56a77, (q31_t)0x76c312a0, (q31_t)0x76c0ba80, (q31_t)0x76be6217, (q31_t)0x76bc0965, (q31_t)0x76b9b069, (q31_t)0x76b75724, (q31_t)0x76b4fd96, + (q31_t)0x76b2a3bf, (q31_t)0x76b0499e, (q31_t)0x76adef34, (q31_t)0x76ab9481, (q31_t)0x76a93985, (q31_t)0x76a6de40, (q31_t)0x76a482b1, (q31_t)0x76a226da, + (q31_t)0x769fcab9, (q31_t)0x769d6e4f, (q31_t)0x769b119b, (q31_t)0x7698b49f, (q31_t)0x76965759, (q31_t)0x7693f9ca, (q31_t)0x76919bf3, (q31_t)0x768f3dd2, + (q31_t)0x768cdf67, (q31_t)0x768a80b4, (q31_t)0x768821b8, (q31_t)0x7685c272, (q31_t)0x768362e4, (q31_t)0x7681030c, (q31_t)0x767ea2eb, (q31_t)0x767c4281, + (q31_t)0x7679e1ce, (q31_t)0x767780d2, (q31_t)0x76751f8d, (q31_t)0x7672bdfe, (q31_t)0x76705c27, (q31_t)0x766dfa07, (q31_t)0x766b979d, (q31_t)0x766934eb, + (q31_t)0x7666d1ef, (q31_t)0x76646eab, (q31_t)0x76620b1d, (q31_t)0x765fa747, (q31_t)0x765d4327, (q31_t)0x765adebe, (q31_t)0x76587a0d, (q31_t)0x76561512, + (q31_t)0x7653afce, (q31_t)0x76514a42, (q31_t)0x764ee46c, (q31_t)0x764c7e4d, (q31_t)0x764a17e6, (q31_t)0x7647b135, (q31_t)0x76454a3c, (q31_t)0x7642e2f9, + (q31_t)0x76407b6e, (q31_t)0x763e139a, (q31_t)0x763bab7c, (q31_t)0x76394316, (q31_t)0x7636da67, (q31_t)0x7634716f, (q31_t)0x7632082e, (q31_t)0x762f9ea4, + (q31_t)0x762d34d1, (q31_t)0x762acab6, (q31_t)0x76286051, (q31_t)0x7625f5a3, (q31_t)0x76238aad, (q31_t)0x76211f6e, (q31_t)0x761eb3e6, (q31_t)0x761c4815, + (q31_t)0x7619dbfb, (q31_t)0x76176f98, (q31_t)0x761502ed, (q31_t)0x761295f9, (q31_t)0x761028bb, (q31_t)0x760dbb35, (q31_t)0x760b4d67, (q31_t)0x7608df4f, + (q31_t)0x760670ee, (q31_t)0x76040245, (q31_t)0x76019353, (q31_t)0x75ff2418, (q31_t)0x75fcb495, (q31_t)0x75fa44c8, (q31_t)0x75f7d4b3, (q31_t)0x75f56455, + (q31_t)0x75f2f3ae, (q31_t)0x75f082bf, (q31_t)0x75ee1187, (q31_t)0x75eba006, (q31_t)0x75e92e3c, (q31_t)0x75e6bc2a, (q31_t)0x75e449ce, (q31_t)0x75e1d72b, + (q31_t)0x75df643e, (q31_t)0x75dcf109, (q31_t)0x75da7d8b, (q31_t)0x75d809c4, (q31_t)0x75d595b4, (q31_t)0x75d3215c, (q31_t)0x75d0acbc, (q31_t)0x75ce37d2, + (q31_t)0x75cbc2a0, (q31_t)0x75c94d25, (q31_t)0x75c6d762, (q31_t)0x75c46156, (q31_t)0x75c1eb01, (q31_t)0x75bf7464, (q31_t)0x75bcfd7e, (q31_t)0x75ba864f, + (q31_t)0x75b80ed8, (q31_t)0x75b59718, (q31_t)0x75b31f0f, (q31_t)0x75b0a6be, (q31_t)0x75ae2e25, (q31_t)0x75abb542, (q31_t)0x75a93c18, (q31_t)0x75a6c2a4, + (q31_t)0x75a448e8, (q31_t)0x75a1cee4, (q31_t)0x759f5496, (q31_t)0x759cda01, (q31_t)0x759a5f22, (q31_t)0x7597e3fc, (q31_t)0x7595688c, (q31_t)0x7592ecd4, + (q31_t)0x759070d4, (q31_t)0x758df48b, (q31_t)0x758b77fa, (q31_t)0x7588fb20, (q31_t)0x75867dfd, (q31_t)0x75840093, (q31_t)0x758182df, (q31_t)0x757f04e3, + (q31_t)0x757c869f, (q31_t)0x757a0812, (q31_t)0x7577893d, (q31_t)0x75750a1f, (q31_t)0x75728ab9, (q31_t)0x75700b0a, (q31_t)0x756d8b13, (q31_t)0x756b0ad3, + (q31_t)0x75688a4b, (q31_t)0x7566097b, (q31_t)0x75638862, (q31_t)0x75610701, (q31_t)0x755e8557, (q31_t)0x755c0365, (q31_t)0x7559812b, (q31_t)0x7556fea8, + (q31_t)0x75547bdd, (q31_t)0x7551f8c9, (q31_t)0x754f756e, (q31_t)0x754cf1c9, (q31_t)0x754a6ddd, (q31_t)0x7547e9a8, (q31_t)0x7545652a, (q31_t)0x7542e065, + (q31_t)0x75405b57, (q31_t)0x753dd600, (q31_t)0x753b5061, (q31_t)0x7538ca7b, (q31_t)0x7536444b, (q31_t)0x7533bdd4, (q31_t)0x75313714, (q31_t)0x752eb00c, + (q31_t)0x752c28bb, (q31_t)0x7529a122, (q31_t)0x75271941, (q31_t)0x75249118, (q31_t)0x752208a7, (q31_t)0x751f7fed, (q31_t)0x751cf6eb, (q31_t)0x751a6da0, + (q31_t)0x7517e40e, (q31_t)0x75155a33, (q31_t)0x7512d010, (q31_t)0x751045a5, (q31_t)0x750dbaf2, (q31_t)0x750b2ff6, (q31_t)0x7508a4b2, (q31_t)0x75061926, + (q31_t)0x75038d52, (q31_t)0x75010136, (q31_t)0x74fe74d1, (q31_t)0x74fbe825, (q31_t)0x74f95b30, (q31_t)0x74f6cdf3, (q31_t)0x74f4406d, (q31_t)0x74f1b2a0, + (q31_t)0x74ef248b, (q31_t)0x74ec962d, (q31_t)0x74ea0787, (q31_t)0x74e7789a, (q31_t)0x74e4e964, (q31_t)0x74e259e6, (q31_t)0x74dfca20, (q31_t)0x74dd3a11, + (q31_t)0x74daa9bb, (q31_t)0x74d8191d, (q31_t)0x74d58836, (q31_t)0x74d2f708, (q31_t)0x74d06591, (q31_t)0x74cdd3d2, (q31_t)0x74cb41cc, (q31_t)0x74c8af7d, + (q31_t)0x74c61ce6, (q31_t)0x74c38a07, (q31_t)0x74c0f6e0, (q31_t)0x74be6372, (q31_t)0x74bbcfbb, (q31_t)0x74b93bbc, (q31_t)0x74b6a775, (q31_t)0x74b412e6, + (q31_t)0x74b17e0f, (q31_t)0x74aee8f0, (q31_t)0x74ac5389, (q31_t)0x74a9bddb, (q31_t)0x74a727e4, (q31_t)0x74a491a5, (q31_t)0x74a1fb1e, (q31_t)0x749f6450, + (q31_t)0x749ccd39, (q31_t)0x749a35db, (q31_t)0x74979e34, (q31_t)0x74950646, (q31_t)0x74926e10, (q31_t)0x748fd592, (q31_t)0x748d3ccb, (q31_t)0x748aa3be, + (q31_t)0x74880a68, (q31_t)0x748570ca, (q31_t)0x7482d6e4, (q31_t)0x74803cb7, (q31_t)0x747da242, (q31_t)0x747b0784, (q31_t)0x74786c7f, (q31_t)0x7475d132, + (q31_t)0x7473359e, (q31_t)0x747099c1, (q31_t)0x746dfd9d, (q31_t)0x746b6131, (q31_t)0x7468c47c, (q31_t)0x74662781, (q31_t)0x74638a3d, (q31_t)0x7460ecb2, + (q31_t)0x745e4ede, (q31_t)0x745bb0c3, (q31_t)0x74591261, (q31_t)0x745673b6, (q31_t)0x7453d4c4, (q31_t)0x7451358a, (q31_t)0x744e9608, (q31_t)0x744bf63e, + (q31_t)0x7449562d, (q31_t)0x7446b5d4, (q31_t)0x74441533, (q31_t)0x7441744b, (q31_t)0x743ed31b, (q31_t)0x743c31a3, (q31_t)0x74398fe3, (q31_t)0x7436eddc, + (q31_t)0x74344b8d, (q31_t)0x7431a8f6, (q31_t)0x742f0618, (q31_t)0x742c62f2, (q31_t)0x7429bf84, (q31_t)0x74271bcf, (q31_t)0x742477d2, (q31_t)0x7421d38e, + (q31_t)0x741f2f01, (q31_t)0x741c8a2d, (q31_t)0x7419e512, (q31_t)0x74173faf, (q31_t)0x74149a04, (q31_t)0x7411f412, (q31_t)0x740f4dd8, (q31_t)0x740ca756, + (q31_t)0x740a008d, (q31_t)0x7407597d, (q31_t)0x7404b224, (q31_t)0x74020a85, (q31_t)0x73ff629d, (q31_t)0x73fcba6e, (q31_t)0x73fa11f8, (q31_t)0x73f7693a, + (q31_t)0x73f4c034, (q31_t)0x73f216e7, (q31_t)0x73ef6d53, (q31_t)0x73ecc377, (q31_t)0x73ea1953, (q31_t)0x73e76ee8, (q31_t)0x73e4c435, (q31_t)0x73e2193b, + (q31_t)0x73df6df9, (q31_t)0x73dcc270, (q31_t)0x73da16a0, (q31_t)0x73d76a88, (q31_t)0x73d4be28, (q31_t)0x73d21182, (q31_t)0x73cf6493, (q31_t)0x73ccb75d, + (q31_t)0x73ca09e0, (q31_t)0x73c75c1c, (q31_t)0x73c4ae10, (q31_t)0x73c1ffbc, (q31_t)0x73bf5121, (q31_t)0x73bca23f, (q31_t)0x73b9f315, (q31_t)0x73b743a4, + (q31_t)0x73b493ec, (q31_t)0x73b1e3ec, (q31_t)0x73af33a5, (q31_t)0x73ac8316, (q31_t)0x73a9d240, (q31_t)0x73a72123, (q31_t)0x73a46fbf, (q31_t)0x73a1be13, + (q31_t)0x739f0c20, (q31_t)0x739c59e5, (q31_t)0x7399a763, (q31_t)0x7396f49a, (q31_t)0x73944189, (q31_t)0x73918e32, (q31_t)0x738eda93, (q31_t)0x738c26ac, + (q31_t)0x7389727f, (q31_t)0x7386be0a, (q31_t)0x7384094e, (q31_t)0x7381544a, (q31_t)0x737e9f00, (q31_t)0x737be96e, (q31_t)0x73793395, (q31_t)0x73767d74, + (q31_t)0x7373c70d, (q31_t)0x7371105e, (q31_t)0x736e5968, (q31_t)0x736ba22b, (q31_t)0x7368eaa6, (q31_t)0x736632db, (q31_t)0x73637ac8, (q31_t)0x7360c26e, + (q31_t)0x735e09cd, (q31_t)0x735b50e4, (q31_t)0x735897b5, (q31_t)0x7355de3e, (q31_t)0x73532481, (q31_t)0x73506a7c, (q31_t)0x734db030, (q31_t)0x734af59d, + (q31_t)0x73483ac2, (q31_t)0x73457fa1, (q31_t)0x7342c438, (q31_t)0x73400889, (q31_t)0x733d4c92, (q31_t)0x733a9054, (q31_t)0x7337d3d0, (q31_t)0x73351704, + (q31_t)0x733259f1, (q31_t)0x732f9c97, (q31_t)0x732cdef6, (q31_t)0x732a210d, (q31_t)0x732762de, (q31_t)0x7324a468, (q31_t)0x7321e5ab, (q31_t)0x731f26a7, + (q31_t)0x731c675b, (q31_t)0x7319a7c9, (q31_t)0x7316e7f0, (q31_t)0x731427cf, (q31_t)0x73116768, (q31_t)0x730ea6ba, (q31_t)0x730be5c5, (q31_t)0x73092489, + (q31_t)0x73066306, (q31_t)0x7303a13b, (q31_t)0x7300df2a, (q31_t)0x72fe1cd2, (q31_t)0x72fb5a34, (q31_t)0x72f8974e, (q31_t)0x72f5d421, (q31_t)0x72f310ad, + (q31_t)0x72f04cf3, (q31_t)0x72ed88f1, (q31_t)0x72eac4a9, (q31_t)0x72e8001a, (q31_t)0x72e53b44, (q31_t)0x72e27627, (q31_t)0x72dfb0c3, (q31_t)0x72dceb18, + (q31_t)0x72da2526, (q31_t)0x72d75eee, (q31_t)0x72d4986f, (q31_t)0x72d1d1a9, (q31_t)0x72cf0a9c, (q31_t)0x72cc4348, (q31_t)0x72c97bad, (q31_t)0x72c6b3cc, + (q31_t)0x72c3eba4, (q31_t)0x72c12335, (q31_t)0x72be5a7f, (q31_t)0x72bb9183, (q31_t)0x72b8c83f, (q31_t)0x72b5feb5, (q31_t)0x72b334e4, (q31_t)0x72b06acd, + (q31_t)0x72ada06f, (q31_t)0x72aad5c9, (q31_t)0x72a80ade, (q31_t)0x72a53fab, (q31_t)0x72a27432, (q31_t)0x729fa872, (q31_t)0x729cdc6b, (q31_t)0x729a101e, + (q31_t)0x7297438a, (q31_t)0x729476af, (q31_t)0x7291a98e, (q31_t)0x728edc26, (q31_t)0x728c0e77, (q31_t)0x72894082, (q31_t)0x72867245, (q31_t)0x7283a3c3, + (q31_t)0x7280d4f9, (q31_t)0x727e05e9, (q31_t)0x727b3693, (q31_t)0x727866f6, (q31_t)0x72759712, (q31_t)0x7272c6e7, (q31_t)0x726ff676, (q31_t)0x726d25bf, + (q31_t)0x726a54c1, (q31_t)0x7267837c, (q31_t)0x7264b1f0, (q31_t)0x7261e01e, (q31_t)0x725f0e06, (q31_t)0x725c3ba7, (q31_t)0x72596901, (q31_t)0x72569615, + (q31_t)0x7253c2e3, (q31_t)0x7250ef6a, (q31_t)0x724e1baa, (q31_t)0x724b47a4, (q31_t)0x72487357, (q31_t)0x72459ec4, (q31_t)0x7242c9ea, (q31_t)0x723ff4ca, + (q31_t)0x723d1f63, (q31_t)0x723a49b6, (q31_t)0x723773c3, (q31_t)0x72349d89, (q31_t)0x7231c708, (q31_t)0x722ef041, (q31_t)0x722c1934, (q31_t)0x722941e0, + (q31_t)0x72266a46, (q31_t)0x72239266, (q31_t)0x7220ba3f, (q31_t)0x721de1d1, (q31_t)0x721b091d, (q31_t)0x72183023, (q31_t)0x721556e3, (q31_t)0x72127d5c, + (q31_t)0x720fa38e, (q31_t)0x720cc97b, (q31_t)0x7209ef21, (q31_t)0x72071480, (q31_t)0x7204399a, (q31_t)0x72015e6d, (q31_t)0x71fe82f9, (q31_t)0x71fba740, + (q31_t)0x71f8cb40, (q31_t)0x71f5eefa, (q31_t)0x71f3126d, (q31_t)0x71f0359a, (q31_t)0x71ed5881, (q31_t)0x71ea7b22, (q31_t)0x71e79d7c, (q31_t)0x71e4bf90, + (q31_t)0x71e1e15e, (q31_t)0x71df02e5, (q31_t)0x71dc2427, (q31_t)0x71d94522, (q31_t)0x71d665d6, (q31_t)0x71d38645, (q31_t)0x71d0a66d, (q31_t)0x71cdc650, + (q31_t)0x71cae5ec, (q31_t)0x71c80542, (q31_t)0x71c52451, (q31_t)0x71c2431b, (q31_t)0x71bf619e, (q31_t)0x71bc7fdb, (q31_t)0x71b99dd2, (q31_t)0x71b6bb83, + (q31_t)0x71b3d8ed, (q31_t)0x71b0f612, (q31_t)0x71ae12f0, (q31_t)0x71ab2f89, (q31_t)0x71a84bdb, (q31_t)0x71a567e7, (q31_t)0x71a283ad, (q31_t)0x719f9f2c, + (q31_t)0x719cba66, (q31_t)0x7199d55a, (q31_t)0x7196f008, (q31_t)0x71940a6f, (q31_t)0x71912490, (q31_t)0x718e3e6c, (q31_t)0x718b5801, (q31_t)0x71887151, + (q31_t)0x71858a5a, (q31_t)0x7182a31d, (q31_t)0x717fbb9a, (q31_t)0x717cd3d2, (q31_t)0x7179ebc3, (q31_t)0x7177036e, (q31_t)0x71741ad3, (q31_t)0x717131f3, + (q31_t)0x716e48cc, (q31_t)0x716b5f5f, (q31_t)0x716875ad, (q31_t)0x71658bb4, (q31_t)0x7162a175, (q31_t)0x715fb6f1, (q31_t)0x715ccc26, (q31_t)0x7159e116, + (q31_t)0x7156f5c0, (q31_t)0x71540a24, (q31_t)0x71511e42, (q31_t)0x714e321a, (q31_t)0x714b45ac, (q31_t)0x714858f8, (q31_t)0x71456bfe, (q31_t)0x71427ebf, + (q31_t)0x713f9139, (q31_t)0x713ca36e, (q31_t)0x7139b55d, (q31_t)0x7136c706, (q31_t)0x7133d869, (q31_t)0x7130e987, (q31_t)0x712dfa5e, (q31_t)0x712b0af0, + (q31_t)0x71281b3c, (q31_t)0x71252b42, (q31_t)0x71223b02, (q31_t)0x711f4a7d, (q31_t)0x711c59b2, (q31_t)0x711968a1, (q31_t)0x7116774a, (q31_t)0x711385ad, + (q31_t)0x711093cb, (q31_t)0x710da1a3, (q31_t)0x710aaf35, (q31_t)0x7107bc82, (q31_t)0x7104c989, (q31_t)0x7101d64a, (q31_t)0x70fee2c5, (q31_t)0x70fbeefb, + (q31_t)0x70f8faeb, (q31_t)0x70f60695, (q31_t)0x70f311fa, (q31_t)0x70f01d19, (q31_t)0x70ed27f2, (q31_t)0x70ea3286, (q31_t)0x70e73cd4, (q31_t)0x70e446dc, + (q31_t)0x70e1509f, (q31_t)0x70de5a1c, (q31_t)0x70db6353, (q31_t)0x70d86c45, (q31_t)0x70d574f1, (q31_t)0x70d27d58, (q31_t)0x70cf8579, (q31_t)0x70cc8d54, + (q31_t)0x70c994ea, (q31_t)0x70c69c3a, (q31_t)0x70c3a345, (q31_t)0x70c0aa0a, (q31_t)0x70bdb08a, (q31_t)0x70bab6c4, (q31_t)0x70b7bcb8, (q31_t)0x70b4c267, + (q31_t)0x70b1c7d1, (q31_t)0x70aeccf5, (q31_t)0x70abd1d3, (q31_t)0x70a8d66c, (q31_t)0x70a5dac0, (q31_t)0x70a2dece, (q31_t)0x709fe296, (q31_t)0x709ce619, + (q31_t)0x7099e957, (q31_t)0x7096ec4f, (q31_t)0x7093ef01, (q31_t)0x7090f16e, (q31_t)0x708df396, (q31_t)0x708af579, (q31_t)0x7087f715, (q31_t)0x7084f86d, + (q31_t)0x7081f97f, (q31_t)0x707efa4c, (q31_t)0x707bfad3, (q31_t)0x7078fb15, (q31_t)0x7075fb11, (q31_t)0x7072fac9, (q31_t)0x706ffa3a, (q31_t)0x706cf967, + (q31_t)0x7069f84e, (q31_t)0x7066f6f0, (q31_t)0x7063f54c, (q31_t)0x7060f363, (q31_t)0x705df135, (q31_t)0x705aeec1, (q31_t)0x7057ec08, (q31_t)0x7054e90a, + (q31_t)0x7051e5c7, (q31_t)0x704ee23e, (q31_t)0x704bde70, (q31_t)0x7048da5d, (q31_t)0x7045d604, (q31_t)0x7042d166, (q31_t)0x703fcc83, (q31_t)0x703cc75b, + (q31_t)0x7039c1ed, (q31_t)0x7036bc3b, (q31_t)0x7033b643, (q31_t)0x7030b005, (q31_t)0x702da983, (q31_t)0x702aa2bb, (q31_t)0x70279baf, (q31_t)0x7024945d, + (q31_t)0x70218cc6, (q31_t)0x701e84e9, (q31_t)0x701b7cc8, (q31_t)0x70187461, (q31_t)0x70156bb5, (q31_t)0x701262c4, (q31_t)0x700f598e, (q31_t)0x700c5013, + (q31_t)0x70094653, (q31_t)0x70063c4e, (q31_t)0x70033203, (q31_t)0x70002774, (q31_t)0x6ffd1c9f, (q31_t)0x6ffa1185, (q31_t)0x6ff70626, (q31_t)0x6ff3fa82, + (q31_t)0x6ff0ee99, (q31_t)0x6fede26b, (q31_t)0x6fead5f8, (q31_t)0x6fe7c940, (q31_t)0x6fe4bc43, (q31_t)0x6fe1af01, (q31_t)0x6fdea17a, (q31_t)0x6fdb93ae, + (q31_t)0x6fd8859d, (q31_t)0x6fd57746, (q31_t)0x6fd268ab, (q31_t)0x6fcf59cb, (q31_t)0x6fcc4aa6, (q31_t)0x6fc93b3c, (q31_t)0x6fc62b8d, (q31_t)0x6fc31b99, + (q31_t)0x6fc00b60, (q31_t)0x6fbcfae2, (q31_t)0x6fb9ea20, (q31_t)0x6fb6d918, (q31_t)0x6fb3c7cb, (q31_t)0x6fb0b63a, (q31_t)0x6fada464, (q31_t)0x6faa9248, + (q31_t)0x6fa77fe8, (q31_t)0x6fa46d43, (q31_t)0x6fa15a59, (q31_t)0x6f9e472b, (q31_t)0x6f9b33b7, (q31_t)0x6f981fff, (q31_t)0x6f950c01, (q31_t)0x6f91f7bf, + (q31_t)0x6f8ee338, (q31_t)0x6f8bce6c, (q31_t)0x6f88b95c, (q31_t)0x6f85a407, (q31_t)0x6f828e6c, (q31_t)0x6f7f788d, (q31_t)0x6f7c626a, (q31_t)0x6f794c01, + (q31_t)0x6f763554, (q31_t)0x6f731e62, (q31_t)0x6f70072b, (q31_t)0x6f6cefb0, (q31_t)0x6f69d7f0, (q31_t)0x6f66bfeb, (q31_t)0x6f63a7a1, (q31_t)0x6f608f13, + (q31_t)0x6f5d7640, (q31_t)0x6f5a5d28, (q31_t)0x6f5743cb, (q31_t)0x6f542a2a, (q31_t)0x6f511044, (q31_t)0x6f4df61a, (q31_t)0x6f4adbab, (q31_t)0x6f47c0f7, + (q31_t)0x6f44a5ff, (q31_t)0x6f418ac2, (q31_t)0x6f3e6f40, (q31_t)0x6f3b537a, (q31_t)0x6f38376f, (q31_t)0x6f351b1f, (q31_t)0x6f31fe8b, (q31_t)0x6f2ee1b2, + (q31_t)0x6f2bc495, (q31_t)0x6f28a733, (q31_t)0x6f25898d, (q31_t)0x6f226ba2, (q31_t)0x6f1f4d72, (q31_t)0x6f1c2efe, (q31_t)0x6f191045, (q31_t)0x6f15f148, + (q31_t)0x6f12d206, (q31_t)0x6f0fb280, (q31_t)0x6f0c92b6, (q31_t)0x6f0972a6, (q31_t)0x6f065253, (q31_t)0x6f0331ba, (q31_t)0x6f0010de, (q31_t)0x6efcefbd, + (q31_t)0x6ef9ce57, (q31_t)0x6ef6acad, (q31_t)0x6ef38abe, (q31_t)0x6ef0688b, (q31_t)0x6eed4614, (q31_t)0x6eea2358, (q31_t)0x6ee70058, (q31_t)0x6ee3dd13, + (q31_t)0x6ee0b98a, (q31_t)0x6edd95bd, (q31_t)0x6eda71ab, (q31_t)0x6ed74d55, (q31_t)0x6ed428ba, (q31_t)0x6ed103db, (q31_t)0x6ecddeb8, (q31_t)0x6ecab950, + (q31_t)0x6ec793a4, (q31_t)0x6ec46db4, (q31_t)0x6ec1477f, (q31_t)0x6ebe2106, (q31_t)0x6ebafa49, (q31_t)0x6eb7d347, (q31_t)0x6eb4ac02, (q31_t)0x6eb18477, + (q31_t)0x6eae5ca9, (q31_t)0x6eab3496, (q31_t)0x6ea80c3f, (q31_t)0x6ea4e3a4, (q31_t)0x6ea1bac4, (q31_t)0x6e9e91a1, (q31_t)0x6e9b6839, (q31_t)0x6e983e8d, + (q31_t)0x6e95149c, (q31_t)0x6e91ea67, (q31_t)0x6e8ebfef, (q31_t)0x6e8b9532, (q31_t)0x6e886a30, (q31_t)0x6e853eeb, (q31_t)0x6e821361, (q31_t)0x6e7ee794, + (q31_t)0x6e7bbb82, (q31_t)0x6e788f2c, (q31_t)0x6e756291, (q31_t)0x6e7235b3, (q31_t)0x6e6f0890, (q31_t)0x6e6bdb2a, (q31_t)0x6e68ad7f, (q31_t)0x6e657f90, + (q31_t)0x6e62515d, (q31_t)0x6e5f22e6, (q31_t)0x6e5bf42b, (q31_t)0x6e58c52c, (q31_t)0x6e5595e9, (q31_t)0x6e526662, (q31_t)0x6e4f3696, (q31_t)0x6e4c0687, + (q31_t)0x6e48d633, (q31_t)0x6e45a59c, (q31_t)0x6e4274c1, (q31_t)0x6e3f43a1, (q31_t)0x6e3c123e, (q31_t)0x6e38e096, (q31_t)0x6e35aeab, (q31_t)0x6e327c7b, + (q31_t)0x6e2f4a08, (q31_t)0x6e2c1750, (q31_t)0x6e28e455, (q31_t)0x6e25b115, (q31_t)0x6e227d92, (q31_t)0x6e1f49cb, (q31_t)0x6e1c15c0, (q31_t)0x6e18e171, + (q31_t)0x6e15acde, (q31_t)0x6e127807, (q31_t)0x6e0f42ec, (q31_t)0x6e0c0d8e, (q31_t)0x6e08d7eb, (q31_t)0x6e05a205, (q31_t)0x6e026bda, (q31_t)0x6dff356c, + (q31_t)0x6dfbfeba, (q31_t)0x6df8c7c4, (q31_t)0x6df5908b, (q31_t)0x6df2590d, (q31_t)0x6def214c, (q31_t)0x6debe947, (q31_t)0x6de8b0fe, (q31_t)0x6de57871, + (q31_t)0x6de23fa0, (q31_t)0x6ddf068c, (q31_t)0x6ddbcd34, (q31_t)0x6dd89398, (q31_t)0x6dd559b9, (q31_t)0x6dd21f95, (q31_t)0x6dcee52e, (q31_t)0x6dcbaa83, + (q31_t)0x6dc86f95, (q31_t)0x6dc53462, (q31_t)0x6dc1f8ec, (q31_t)0x6dbebd33, (q31_t)0x6dbb8135, (q31_t)0x6db844f4, (q31_t)0x6db5086f, (q31_t)0x6db1cba7, + (q31_t)0x6dae8e9b, (q31_t)0x6dab514b, (q31_t)0x6da813b8, (q31_t)0x6da4d5e1, (q31_t)0x6da197c6, (q31_t)0x6d9e5968, (q31_t)0x6d9b1ac6, (q31_t)0x6d97dbe0, + (q31_t)0x6d949cb7, (q31_t)0x6d915d4a, (q31_t)0x6d8e1d9a, (q31_t)0x6d8adda6, (q31_t)0x6d879d6e, (q31_t)0x6d845cf3, (q31_t)0x6d811c35, (q31_t)0x6d7ddb33, + (q31_t)0x6d7a99ed, (q31_t)0x6d775864, (q31_t)0x6d741697, (q31_t)0x6d70d487, (q31_t)0x6d6d9233, (q31_t)0x6d6a4f9c, (q31_t)0x6d670cc1, (q31_t)0x6d63c9a3, + (q31_t)0x6d608641, (q31_t)0x6d5d429c, (q31_t)0x6d59feb3, (q31_t)0x6d56ba87, (q31_t)0x6d537617, (q31_t)0x6d503164, (q31_t)0x6d4cec6e, (q31_t)0x6d49a734, + (q31_t)0x6d4661b7, (q31_t)0x6d431bf6, (q31_t)0x6d3fd5f2, (q31_t)0x6d3c8fab, (q31_t)0x6d394920, (q31_t)0x6d360252, (q31_t)0x6d32bb40, (q31_t)0x6d2f73eb, + (q31_t)0x6d2c2c53, (q31_t)0x6d28e477, (q31_t)0x6d259c58, (q31_t)0x6d2253f6, (q31_t)0x6d1f0b50, (q31_t)0x6d1bc267, (q31_t)0x6d18793b, (q31_t)0x6d152fcc, + (q31_t)0x6d11e619, (q31_t)0x6d0e9c23, (q31_t)0x6d0b51e9, (q31_t)0x6d08076d, (q31_t)0x6d04bcad, (q31_t)0x6d0171aa, (q31_t)0x6cfe2663, (q31_t)0x6cfadada, + (q31_t)0x6cf78f0d, (q31_t)0x6cf442fd, (q31_t)0x6cf0f6aa, (q31_t)0x6cedaa13, (q31_t)0x6cea5d3a, (q31_t)0x6ce7101d, (q31_t)0x6ce3c2bd, (q31_t)0x6ce0751a, + (q31_t)0x6cdd2733, (q31_t)0x6cd9d90a, (q31_t)0x6cd68a9d, (q31_t)0x6cd33bed, (q31_t)0x6ccfecfa, (q31_t)0x6ccc9dc4, (q31_t)0x6cc94e4b, (q31_t)0x6cc5fe8f, + (q31_t)0x6cc2ae90, (q31_t)0x6cbf5e4d, (q31_t)0x6cbc0dc8, (q31_t)0x6cb8bcff, (q31_t)0x6cb56bf4, (q31_t)0x6cb21aa5, (q31_t)0x6caec913, (q31_t)0x6cab773e, + (q31_t)0x6ca82527, (q31_t)0x6ca4d2cc, (q31_t)0x6ca1802e, (q31_t)0x6c9e2d4d, (q31_t)0x6c9ada29, (q31_t)0x6c9786c2, (q31_t)0x6c943318, (q31_t)0x6c90df2c, + (q31_t)0x6c8d8afc, (q31_t)0x6c8a3689, (q31_t)0x6c86e1d3, (q31_t)0x6c838cdb, (q31_t)0x6c80379f, (q31_t)0x6c7ce220, (q31_t)0x6c798c5f, (q31_t)0x6c76365b, + (q31_t)0x6c72e013, (q31_t)0x6c6f8989, (q31_t)0x6c6c32bc, (q31_t)0x6c68dbac, (q31_t)0x6c658459, (q31_t)0x6c622cc4, (q31_t)0x6c5ed4eb, (q31_t)0x6c5b7cd0, + (q31_t)0x6c582472, (q31_t)0x6c54cbd1, (q31_t)0x6c5172ed, (q31_t)0x6c4e19c6, (q31_t)0x6c4ac05d, (q31_t)0x6c4766b0, (q31_t)0x6c440cc1, (q31_t)0x6c40b28f, + (q31_t)0x6c3d581b, (q31_t)0x6c39fd63, (q31_t)0x6c36a269, (q31_t)0x6c33472c, (q31_t)0x6c2febad, (q31_t)0x6c2c8fea, (q31_t)0x6c2933e5, (q31_t)0x6c25d79d, + (q31_t)0x6c227b13, (q31_t)0x6c1f1e45, (q31_t)0x6c1bc136, (q31_t)0x6c1863e3, (q31_t)0x6c15064e, (q31_t)0x6c11a876, (q31_t)0x6c0e4a5b, (q31_t)0x6c0aebfe, + (q31_t)0x6c078d5e, (q31_t)0x6c042e7b, (q31_t)0x6c00cf56, (q31_t)0x6bfd6fee, (q31_t)0x6bfa1044, (q31_t)0x6bf6b056, (q31_t)0x6bf35027, (q31_t)0x6befefb5, + (q31_t)0x6bec8f00, (q31_t)0x6be92e08, (q31_t)0x6be5ccce, (q31_t)0x6be26b52, (q31_t)0x6bdf0993, (q31_t)0x6bdba791, (q31_t)0x6bd8454d, (q31_t)0x6bd4e2c6, + (q31_t)0x6bd17ffd, (q31_t)0x6bce1cf1, (q31_t)0x6bcab9a3, (q31_t)0x6bc75613, (q31_t)0x6bc3f23f, (q31_t)0x6bc08e2a, (q31_t)0x6bbd29d2, (q31_t)0x6bb9c537, + (q31_t)0x6bb6605a, (q31_t)0x6bb2fb3b, (q31_t)0x6baf95d9, (q31_t)0x6bac3034, (q31_t)0x6ba8ca4e, (q31_t)0x6ba56425, (q31_t)0x6ba1fdb9, (q31_t)0x6b9e970b, + (q31_t)0x6b9b301b, (q31_t)0x6b97c8e8, (q31_t)0x6b946173, (q31_t)0x6b90f9bc, (q31_t)0x6b8d91c2, (q31_t)0x6b8a2986, (q31_t)0x6b86c107, (q31_t)0x6b835846, + (q31_t)0x6b7fef43, (q31_t)0x6b7c85fe, (q31_t)0x6b791c76, (q31_t)0x6b75b2ac, (q31_t)0x6b7248a0, (q31_t)0x6b6ede51, (q31_t)0x6b6b73c0, (q31_t)0x6b6808ed, + (q31_t)0x6b649dd8, (q31_t)0x6b613280, (q31_t)0x6b5dc6e6, (q31_t)0x6b5a5b0a, (q31_t)0x6b56eeec, (q31_t)0x6b53828b, (q31_t)0x6b5015e9, (q31_t)0x6b4ca904, + (q31_t)0x6b493bdd, (q31_t)0x6b45ce73, (q31_t)0x6b4260c8, (q31_t)0x6b3ef2da, (q31_t)0x6b3b84ab, (q31_t)0x6b381639, (q31_t)0x6b34a785, (q31_t)0x6b31388e, + (q31_t)0x6b2dc956, (q31_t)0x6b2a59dc, (q31_t)0x6b26ea1f, (q31_t)0x6b237a21, (q31_t)0x6b2009e0, (q31_t)0x6b1c995d, (q31_t)0x6b192898, (q31_t)0x6b15b791, + (q31_t)0x6b124648, (q31_t)0x6b0ed4bd, (q31_t)0x6b0b62f0, (q31_t)0x6b07f0e1, (q31_t)0x6b047e90, (q31_t)0x6b010bfd, (q31_t)0x6afd9928, (q31_t)0x6afa2610, + (q31_t)0x6af6b2b7, (q31_t)0x6af33f1c, (q31_t)0x6aefcb3f, (q31_t)0x6aec5720, (q31_t)0x6ae8e2bf, (q31_t)0x6ae56e1c, (q31_t)0x6ae1f937, (q31_t)0x6ade8410, + (q31_t)0x6adb0ea8, (q31_t)0x6ad798fd, (q31_t)0x6ad42311, (q31_t)0x6ad0ace2, (q31_t)0x6acd3672, (q31_t)0x6ac9bfc0, (q31_t)0x6ac648cb, (q31_t)0x6ac2d195, + (q31_t)0x6abf5a1e, (q31_t)0x6abbe264, (q31_t)0x6ab86a68, (q31_t)0x6ab4f22b, (q31_t)0x6ab179ac, (q31_t)0x6aae00eb, (q31_t)0x6aaa87e8, (q31_t)0x6aa70ea4, + (q31_t)0x6aa3951d, (q31_t)0x6aa01b55, (q31_t)0x6a9ca14b, (q31_t)0x6a992700, (q31_t)0x6a95ac72, (q31_t)0x6a9231a3, (q31_t)0x6a8eb692, (q31_t)0x6a8b3b3f, + (q31_t)0x6a87bfab, (q31_t)0x6a8443d5, (q31_t)0x6a80c7bd, (q31_t)0x6a7d4b64, (q31_t)0x6a79cec8, (q31_t)0x6a7651ec, (q31_t)0x6a72d4cd, (q31_t)0x6a6f576d, + (q31_t)0x6a6bd9cb, (q31_t)0x6a685be8, (q31_t)0x6a64ddc2, (q31_t)0x6a615f5c, (q31_t)0x6a5de0b3, (q31_t)0x6a5a61c9, (q31_t)0x6a56e29e, (q31_t)0x6a536331, + (q31_t)0x6a4fe382, (q31_t)0x6a4c6391, (q31_t)0x6a48e360, (q31_t)0x6a4562ec, (q31_t)0x6a41e237, (q31_t)0x6a3e6140, (q31_t)0x6a3ae008, (q31_t)0x6a375e8f, + (q31_t)0x6a33dcd4, (q31_t)0x6a305ad7, (q31_t)0x6a2cd899, (q31_t)0x6a295619, (q31_t)0x6a25d358, (q31_t)0x6a225055, (q31_t)0x6a1ecd11, (q31_t)0x6a1b498c, + (q31_t)0x6a17c5c5, (q31_t)0x6a1441bc, (q31_t)0x6a10bd72, (q31_t)0x6a0d38e7, (q31_t)0x6a09b41a, (q31_t)0x6a062f0c, (q31_t)0x6a02a9bc, (q31_t)0x69ff242b, + (q31_t)0x69fb9e59, (q31_t)0x69f81845, (q31_t)0x69f491f0, (q31_t)0x69f10b5a, (q31_t)0x69ed8482, (q31_t)0x69e9fd69, (q31_t)0x69e6760f, (q31_t)0x69e2ee73, + (q31_t)0x69df6696, (q31_t)0x69dbde77, (q31_t)0x69d85618, (q31_t)0x69d4cd77, (q31_t)0x69d14494, (q31_t)0x69cdbb71, (q31_t)0x69ca320c, (q31_t)0x69c6a866, + (q31_t)0x69c31e7f, (q31_t)0x69bf9456, (q31_t)0x69bc09ec, (q31_t)0x69b87f41, (q31_t)0x69b4f455, (q31_t)0x69b16928, (q31_t)0x69adddb9, (q31_t)0x69aa5209, + (q31_t)0x69a6c618, (q31_t)0x69a339e6, (q31_t)0x699fad73, (q31_t)0x699c20be, (q31_t)0x699893c9, (q31_t)0x69950692, (q31_t)0x6991791a, (q31_t)0x698deb61, + (q31_t)0x698a5d67, (q31_t)0x6986cf2c, (q31_t)0x698340af, (q31_t)0x697fb1f2, (q31_t)0x697c22f3, (q31_t)0x697893b4, (q31_t)0x69750433, (q31_t)0x69717472, + (q31_t)0x696de46f, (q31_t)0x696a542b, (q31_t)0x6966c3a6, (q31_t)0x696332e1, (q31_t)0x695fa1da, (q31_t)0x695c1092, (q31_t)0x69587f09, (q31_t)0x6954ed40, + (q31_t)0x69515b35, (q31_t)0x694dc8e9, (q31_t)0x694a365c, (q31_t)0x6946a38f, (q31_t)0x69431080, (q31_t)0x693f7d31, (q31_t)0x693be9a0, (q31_t)0x693855cf, + (q31_t)0x6934c1bd, (q31_t)0x69312d6a, (q31_t)0x692d98d6, (q31_t)0x692a0401, (q31_t)0x69266eeb, (q31_t)0x6922d995, (q31_t)0x691f43fd, (q31_t)0x691bae25, + (q31_t)0x6918180c, (q31_t)0x691481b2, (q31_t)0x6910eb17, (q31_t)0x690d543b, (q31_t)0x6909bd1f, (q31_t)0x690625c2, (q31_t)0x69028e24, (q31_t)0x68fef645, + (q31_t)0x68fb5e25, (q31_t)0x68f7c5c5, (q31_t)0x68f42d24, (q31_t)0x68f09442, (q31_t)0x68ecfb20, (q31_t)0x68e961bd, (q31_t)0x68e5c819, (q31_t)0x68e22e34, + (q31_t)0x68de940f, (q31_t)0x68daf9a9, (q31_t)0x68d75f02, (q31_t)0x68d3c41b, (q31_t)0x68d028f2, (q31_t)0x68cc8d8a, (q31_t)0x68c8f1e0, (q31_t)0x68c555f6, + (q31_t)0x68c1b9cc, (q31_t)0x68be1d61, (q31_t)0x68ba80b5, (q31_t)0x68b6e3c8, (q31_t)0x68b3469b, (q31_t)0x68afa92e, (q31_t)0x68ac0b7f, (q31_t)0x68a86d91, + (q31_t)0x68a4cf61, (q31_t)0x68a130f1, (q31_t)0x689d9241, (q31_t)0x6899f350, (q31_t)0x6896541f, (q31_t)0x6892b4ad, (q31_t)0x688f14fa, (q31_t)0x688b7507, + (q31_t)0x6887d4d4, (q31_t)0x68843460, (q31_t)0x688093ab, (q31_t)0x687cf2b6, (q31_t)0x68795181, (q31_t)0x6875b00b, (q31_t)0x68720e55, (q31_t)0x686e6c5e, + (q31_t)0x686aca27, (q31_t)0x686727b0, (q31_t)0x686384f8, (q31_t)0x685fe200, (q31_t)0x685c3ec7, (q31_t)0x68589b4e, (q31_t)0x6854f795, (q31_t)0x6851539b, + (q31_t)0x684daf61, (q31_t)0x684a0ae6, (q31_t)0x6846662c, (q31_t)0x6842c131, (q31_t)0x683f1bf5, (q31_t)0x683b7679, (q31_t)0x6837d0bd, (q31_t)0x68342ac1, + (q31_t)0x68308485, (q31_t)0x682cde08, (q31_t)0x6829374b, (q31_t)0x6825904d, (q31_t)0x6821e910, (q31_t)0x681e4192, (q31_t)0x681a99d4, (q31_t)0x6816f1d6, + (q31_t)0x68134997, (q31_t)0x680fa118, (q31_t)0x680bf85a, (q31_t)0x68084f5a, (q31_t)0x6804a61b, (q31_t)0x6800fc9c, (q31_t)0x67fd52dc, (q31_t)0x67f9a8dd, + (q31_t)0x67f5fe9d, (q31_t)0x67f2541d, (q31_t)0x67eea95d, (q31_t)0x67eafe5d, (q31_t)0x67e7531c, (q31_t)0x67e3a79c, (q31_t)0x67dffbdc, (q31_t)0x67dc4fdb, + (q31_t)0x67d8a39a, (q31_t)0x67d4f71a, (q31_t)0x67d14a59, (q31_t)0x67cd9d58, (q31_t)0x67c9f017, (q31_t)0x67c64297, (q31_t)0x67c294d6, (q31_t)0x67bee6d5, + (q31_t)0x67bb3894, (q31_t)0x67b78a13, (q31_t)0x67b3db53, (q31_t)0x67b02c52, (q31_t)0x67ac7d11, (q31_t)0x67a8cd91, (q31_t)0x67a51dd0, (q31_t)0x67a16dcf, + (q31_t)0x679dbd8f, (q31_t)0x679a0d0f, (q31_t)0x67965c4e, (q31_t)0x6792ab4e, (q31_t)0x678efa0e, (q31_t)0x678b488e, (q31_t)0x678796ce, (q31_t)0x6783e4cf, + (q31_t)0x6780328f, (q31_t)0x677c8010, (q31_t)0x6778cd50, (q31_t)0x67751a51, (q31_t)0x67716713, (q31_t)0x676db394, (q31_t)0x6769ffd5, (q31_t)0x67664bd7, + (q31_t)0x67629799, (q31_t)0x675ee31b, (q31_t)0x675b2e5e, (q31_t)0x67577960, (q31_t)0x6753c423, (q31_t)0x67500ea7, (q31_t)0x674c58ea, (q31_t)0x6748a2ee, + (q31_t)0x6744ecb2, (q31_t)0x67413636, (q31_t)0x673d7f7b, (q31_t)0x6739c880, (q31_t)0x67361145, (q31_t)0x673259ca, (q31_t)0x672ea210, (q31_t)0x672aea17, + (q31_t)0x672731dd, (q31_t)0x67237964, (q31_t)0x671fc0ac, (q31_t)0x671c07b4, (q31_t)0x67184e7c, (q31_t)0x67149504, (q31_t)0x6710db4d, (q31_t)0x670d2157, + (q31_t)0x67096721, (q31_t)0x6705acab, (q31_t)0x6701f1f6, (q31_t)0x66fe3701, (q31_t)0x66fa7bcd, (q31_t)0x66f6c059, (q31_t)0x66f304a6, (q31_t)0x66ef48b3, + (q31_t)0x66eb8c80, (q31_t)0x66e7d00f, (q31_t)0x66e4135d, (q31_t)0x66e0566c, (q31_t)0x66dc993c, (q31_t)0x66d8dbcd, (q31_t)0x66d51e1d, (q31_t)0x66d1602f, + (q31_t)0x66cda201, (q31_t)0x66c9e393, (q31_t)0x66c624e7, (q31_t)0x66c265fa, (q31_t)0x66bea6cf, (q31_t)0x66bae764, (q31_t)0x66b727ba, (q31_t)0x66b367d0, + (q31_t)0x66afa7a7, (q31_t)0x66abe73f, (q31_t)0x66a82697, (q31_t)0x66a465b0, (q31_t)0x66a0a489, (q31_t)0x669ce324, (q31_t)0x6699217f, (q31_t)0x66955f9b, + (q31_t)0x66919d77, (q31_t)0x668ddb14, (q31_t)0x668a1872, (q31_t)0x66865591, (q31_t)0x66829270, (q31_t)0x667ecf11, (q31_t)0x667b0b72, (q31_t)0x66774793, + (q31_t)0x66738376, (q31_t)0x666fbf19, (q31_t)0x666bfa7d, (q31_t)0x666835a2, (q31_t)0x66647088, (q31_t)0x6660ab2f, (q31_t)0x665ce596, (q31_t)0x66591fbf, + (q31_t)0x665559a8, (q31_t)0x66519352, (q31_t)0x664dccbd, (q31_t)0x664a05e9, (q31_t)0x66463ed6, (q31_t)0x66427784, (q31_t)0x663eaff2, (q31_t)0x663ae822, + (q31_t)0x66372012, (q31_t)0x663357c4, (q31_t)0x662f8f36, (q31_t)0x662bc66a, (q31_t)0x6627fd5e, (q31_t)0x66243413, (q31_t)0x66206a8a, (q31_t)0x661ca0c1, + (q31_t)0x6618d6b9, (q31_t)0x66150c73, (q31_t)0x661141ed, (q31_t)0x660d7729, (q31_t)0x6609ac25, (q31_t)0x6605e0e3, (q31_t)0x66021561, (q31_t)0x65fe49a1, + (q31_t)0x65fa7da2, (q31_t)0x65f6b164, (q31_t)0x65f2e4e7, (q31_t)0x65ef182b, (q31_t)0x65eb4b30, (q31_t)0x65e77df6, (q31_t)0x65e3b07e, (q31_t)0x65dfe2c6, + (q31_t)0x65dc14d0, (q31_t)0x65d8469b, (q31_t)0x65d47827, (q31_t)0x65d0a975, (q31_t)0x65ccda83, (q31_t)0x65c90b53, (q31_t)0x65c53be4, (q31_t)0x65c16c36, + (q31_t)0x65bd9c49, (q31_t)0x65b9cc1e, (q31_t)0x65b5fbb4, (q31_t)0x65b22b0b, (q31_t)0x65ae5a23, (q31_t)0x65aa88fd, (q31_t)0x65a6b798, (q31_t)0x65a2e5f4, + (q31_t)0x659f1412, (q31_t)0x659b41f1, (q31_t)0x65976f91, (q31_t)0x65939cf3, (q31_t)0x658fca15, (q31_t)0x658bf6fa, (q31_t)0x6588239f, (q31_t)0x65845006, + (q31_t)0x65807c2f, (q31_t)0x657ca818, (q31_t)0x6578d3c4, (q31_t)0x6574ff30, (q31_t)0x65712a5e, (q31_t)0x656d554d, (q31_t)0x65697ffe, (q31_t)0x6565aa71, + (q31_t)0x6561d4a4, (q31_t)0x655dfe99, (q31_t)0x655a2850, (q31_t)0x655651c8, (q31_t)0x65527b02, (q31_t)0x654ea3fd, (q31_t)0x654accba, (q31_t)0x6546f538, + (q31_t)0x65431d77, (q31_t)0x653f4579, (q31_t)0x653b6d3b, (q31_t)0x653794c0, (q31_t)0x6533bc06, (q31_t)0x652fe30d, (q31_t)0x652c09d6, (q31_t)0x65283061, + (q31_t)0x652456ad, (q31_t)0x65207cbb, (q31_t)0x651ca28a, (q31_t)0x6518c81b, (q31_t)0x6514ed6e, (q31_t)0x65111283, (q31_t)0x650d3759, (q31_t)0x65095bf0, + (q31_t)0x6505804a, (q31_t)0x6501a465, (q31_t)0x64fdc841, (q31_t)0x64f9ebe0, (q31_t)0x64f60f40, (q31_t)0x64f23262, (q31_t)0x64ee5546, (q31_t)0x64ea77eb, + (q31_t)0x64e69a52, (q31_t)0x64e2bc7b, (q31_t)0x64dede66, (q31_t)0x64db0012, (q31_t)0x64d72180, (q31_t)0x64d342b0, (q31_t)0x64cf63a2, (q31_t)0x64cb8456, + (q31_t)0x64c7a4cb, (q31_t)0x64c3c502, (q31_t)0x64bfe4fc, (q31_t)0x64bc04b6, (q31_t)0x64b82433, (q31_t)0x64b44372, (q31_t)0x64b06273, (q31_t)0x64ac8135, + (q31_t)0x64a89fba, (q31_t)0x64a4be00, (q31_t)0x64a0dc08, (q31_t)0x649cf9d2, (q31_t)0x6499175e, (q31_t)0x649534ac, (q31_t)0x649151bc, (q31_t)0x648d6e8e, + (q31_t)0x64898b22, (q31_t)0x6485a778, (q31_t)0x6481c390, (q31_t)0x647ddf6a, (q31_t)0x6479fb06, (q31_t)0x64761664, (q31_t)0x64723184, (q31_t)0x646e4c66, + (q31_t)0x646a670a, (q31_t)0x64668170, (q31_t)0x64629b98, (q31_t)0x645eb582, (q31_t)0x645acf2e, (q31_t)0x6456e89d, (q31_t)0x645301cd, (q31_t)0x644f1ac0, + (q31_t)0x644b3375, (q31_t)0x64474bec, (q31_t)0x64436425, (q31_t)0x643f7c20, (q31_t)0x643b93dd, (q31_t)0x6437ab5d, (q31_t)0x6433c29f, (q31_t)0x642fd9a3, + (q31_t)0x642bf069, (q31_t)0x642806f1, (q31_t)0x64241d3c, (q31_t)0x64203348, (q31_t)0x641c4917, (q31_t)0x64185ea9, (q31_t)0x641473fc, (q31_t)0x64108912, + (q31_t)0x640c9dea, (q31_t)0x6408b284, (q31_t)0x6404c6e1, (q31_t)0x6400db00, (q31_t)0x63fceee1, (q31_t)0x63f90285, (q31_t)0x63f515eb, (q31_t)0x63f12913, + (q31_t)0x63ed3bfd, (q31_t)0x63e94eaa, (q31_t)0x63e5611a, (q31_t)0x63e1734b, (q31_t)0x63dd853f, (q31_t)0x63d996f6, (q31_t)0x63d5a86f, (q31_t)0x63d1b9aa, + (q31_t)0x63cdcaa8, (q31_t)0x63c9db68, (q31_t)0x63c5ebeb, (q31_t)0x63c1fc30, (q31_t)0x63be0c37, (q31_t)0x63ba1c01, (q31_t)0x63b62b8e, (q31_t)0x63b23add, + (q31_t)0x63ae49ee, (q31_t)0x63aa58c2, (q31_t)0x63a66759, (q31_t)0x63a275b2, (q31_t)0x639e83cd, (q31_t)0x639a91ac, (q31_t)0x63969f4c, (q31_t)0x6392acaf, + (q31_t)0x638eb9d5, (q31_t)0x638ac6be, (q31_t)0x6386d369, (q31_t)0x6382dfd6, (q31_t)0x637eec07, (q31_t)0x637af7fa, (q31_t)0x637703af, (q31_t)0x63730f27, + (q31_t)0x636f1a62, (q31_t)0x636b2560, (q31_t)0x63673020, (q31_t)0x63633aa3, (q31_t)0x635f44e8, (q31_t)0x635b4ef0, (q31_t)0x635758bb, (q31_t)0x63536249, + (q31_t)0x634f6b99, (q31_t)0x634b74ad, (q31_t)0x63477d82, (q31_t)0x6343861b, (q31_t)0x633f8e76, (q31_t)0x633b9695, (q31_t)0x63379e76, (q31_t)0x6333a619, + (q31_t)0x632fad80, (q31_t)0x632bb4a9, (q31_t)0x6327bb96, (q31_t)0x6323c245, (q31_t)0x631fc8b7, (q31_t)0x631bceeb, (q31_t)0x6317d4e3, (q31_t)0x6313da9e, + (q31_t)0x630fe01b, (q31_t)0x630be55b, (q31_t)0x6307ea5e, (q31_t)0x6303ef25, (q31_t)0x62fff3ae, (q31_t)0x62fbf7fa, (q31_t)0x62f7fc08, (q31_t)0x62f3ffda, + (q31_t)0x62f0036f, (q31_t)0x62ec06c7, (q31_t)0x62e809e2, (q31_t)0x62e40cbf, (q31_t)0x62e00f60, (q31_t)0x62dc11c4, (q31_t)0x62d813eb, (q31_t)0x62d415d4, + (q31_t)0x62d01781, (q31_t)0x62cc18f1, (q31_t)0x62c81a24, (q31_t)0x62c41b1a, (q31_t)0x62c01bd3, (q31_t)0x62bc1c4f, (q31_t)0x62b81c8f, (q31_t)0x62b41c91, + (q31_t)0x62b01c57, (q31_t)0x62ac1bdf, (q31_t)0x62a81b2b, (q31_t)0x62a41a3a, (q31_t)0x62a0190c, (q31_t)0x629c17a1, (q31_t)0x629815fa, (q31_t)0x62941415, + (q31_t)0x629011f4, (q31_t)0x628c0f96, (q31_t)0x62880cfb, (q31_t)0x62840a23, (q31_t)0x6280070f, (q31_t)0x627c03be, (q31_t)0x62780030, (q31_t)0x6273fc65, + (q31_t)0x626ff85e, (q31_t)0x626bf41a, (q31_t)0x6267ef99, (q31_t)0x6263eadc, (q31_t)0x625fe5e1, (q31_t)0x625be0ab, (q31_t)0x6257db37, (q31_t)0x6253d587, + (q31_t)0x624fcf9a, (q31_t)0x624bc970, (q31_t)0x6247c30a, (q31_t)0x6243bc68, (q31_t)0x623fb588, (q31_t)0x623bae6c, (q31_t)0x6237a714, (q31_t)0x62339f7e, + (q31_t)0x622f97ad, (q31_t)0x622b8f9e, (q31_t)0x62278754, (q31_t)0x62237ecc, (q31_t)0x621f7608, (q31_t)0x621b6d08, (q31_t)0x621763cb, (q31_t)0x62135a51, + (q31_t)0x620f509b, (q31_t)0x620b46a9, (q31_t)0x62073c7a, (q31_t)0x6203320e, (q31_t)0x61ff2766, (q31_t)0x61fb1c82, (q31_t)0x61f71161, (q31_t)0x61f30604, + (q31_t)0x61eefa6b, (q31_t)0x61eaee95, (q31_t)0x61e6e282, (q31_t)0x61e2d633, (q31_t)0x61dec9a8, (q31_t)0x61dabce0, (q31_t)0x61d6afdd, (q31_t)0x61d2a29c, + (q31_t)0x61ce9520, (q31_t)0x61ca8767, (q31_t)0x61c67971, (q31_t)0x61c26b40, (q31_t)0x61be5cd2, (q31_t)0x61ba4e28, (q31_t)0x61b63f41, (q31_t)0x61b2301e, + (q31_t)0x61ae20bf, (q31_t)0x61aa1124, (q31_t)0x61a6014d, (q31_t)0x61a1f139, (q31_t)0x619de0e9, (q31_t)0x6199d05d, (q31_t)0x6195bf94, (q31_t)0x6191ae90, + (q31_t)0x618d9d4f, (q31_t)0x61898bd2, (q31_t)0x61857a19, (q31_t)0x61816824, (q31_t)0x617d55f2, (q31_t)0x61794385, (q31_t)0x617530db, (q31_t)0x61711df5, + (q31_t)0x616d0ad3, (q31_t)0x6168f775, (q31_t)0x6164e3db, (q31_t)0x6160d005, (q31_t)0x615cbbf3, (q31_t)0x6158a7a4, (q31_t)0x6154931a, (q31_t)0x61507e54, + (q31_t)0x614c6951, (q31_t)0x61485413, (q31_t)0x61443e98, (q31_t)0x614028e2, (q31_t)0x613c12f0, (q31_t)0x6137fcc1, (q31_t)0x6133e657, (q31_t)0x612fcfb0, + (q31_t)0x612bb8ce, (q31_t)0x6127a1b0, (q31_t)0x61238a56, (q31_t)0x611f72c0, (q31_t)0x611b5aee, (q31_t)0x611742e0, (q31_t)0x61132a96, (q31_t)0x610f1210, + (q31_t)0x610af94f, (q31_t)0x6106e051, (q31_t)0x6102c718, (q31_t)0x60feada3, (q31_t)0x60fa93f2, (q31_t)0x60f67a05, (q31_t)0x60f25fdd, (q31_t)0x60ee4579, + (q31_t)0x60ea2ad8, (q31_t)0x60e60ffd, (q31_t)0x60e1f4e5, (q31_t)0x60ddd991, (q31_t)0x60d9be02, (q31_t)0x60d5a237, (q31_t)0x60d18631, (q31_t)0x60cd69ee, + (q31_t)0x60c94d70, (q31_t)0x60c530b6, (q31_t)0x60c113c1, (q31_t)0x60bcf690, (q31_t)0x60b8d923, (q31_t)0x60b4bb7a, (q31_t)0x60b09d96, (q31_t)0x60ac7f76, + (q31_t)0x60a8611b, (q31_t)0x60a44284, (q31_t)0x60a023b1, (q31_t)0x609c04a3, (q31_t)0x6097e559, (q31_t)0x6093c5d3, (q31_t)0x608fa612, (q31_t)0x608b8616, + (q31_t)0x608765dd, (q31_t)0x6083456a, (q31_t)0x607f24ba, (q31_t)0x607b03d0, (q31_t)0x6076e2a9, (q31_t)0x6072c148, (q31_t)0x606e9faa, (q31_t)0x606a7dd2, + (q31_t)0x60665bbd, (q31_t)0x6062396e, (q31_t)0x605e16e2, (q31_t)0x6059f41c, (q31_t)0x6055d11a, (q31_t)0x6051addc, (q31_t)0x604d8a63, (q31_t)0x604966af, + (q31_t)0x604542bf, (q31_t)0x60411e94, (q31_t)0x603cfa2e, (q31_t)0x6038d58c, (q31_t)0x6034b0af, (q31_t)0x60308b97, (q31_t)0x602c6643, (q31_t)0x602840b4, + (q31_t)0x60241ae9, (q31_t)0x601ff4e3, (q31_t)0x601bcea2, (q31_t)0x6017a826, (q31_t)0x6013816e, (q31_t)0x600f5a7b, (q31_t)0x600b334d, (q31_t)0x60070be4, + (q31_t)0x6002e43f, (q31_t)0x5ffebc5f, (q31_t)0x5ffa9444, (q31_t)0x5ff66bee, (q31_t)0x5ff2435d, (q31_t)0x5fee1a90, (q31_t)0x5fe9f188, (q31_t)0x5fe5c845, + (q31_t)0x5fe19ec7, (q31_t)0x5fdd750e, (q31_t)0x5fd94b19, (q31_t)0x5fd520ea, (q31_t)0x5fd0f67f, (q31_t)0x5fcccbd9, (q31_t)0x5fc8a0f8, (q31_t)0x5fc475dc, + (q31_t)0x5fc04a85, (q31_t)0x5fbc1ef3, (q31_t)0x5fb7f326, (q31_t)0x5fb3c71e, (q31_t)0x5faf9adb, (q31_t)0x5fab6e5d, (q31_t)0x5fa741a3, (q31_t)0x5fa314af, + (q31_t)0x5f9ee780, (q31_t)0x5f9aba16, (q31_t)0x5f968c70, (q31_t)0x5f925e90, (q31_t)0x5f8e3075, (q31_t)0x5f8a021f, (q31_t)0x5f85d38e, (q31_t)0x5f81a4c2, + (q31_t)0x5f7d75bb, (q31_t)0x5f794679, (q31_t)0x5f7516fd, (q31_t)0x5f70e745, (q31_t)0x5f6cb753, (q31_t)0x5f688726, (q31_t)0x5f6456be, (q31_t)0x5f60261b, + (q31_t)0x5f5bf53d, (q31_t)0x5f57c424, (q31_t)0x5f5392d1, (q31_t)0x5f4f6143, (q31_t)0x5f4b2f7a, (q31_t)0x5f46fd76, (q31_t)0x5f42cb37, (q31_t)0x5f3e98be, + (q31_t)0x5f3a660a, (q31_t)0x5f36331b, (q31_t)0x5f31fff1, (q31_t)0x5f2dcc8d, (q31_t)0x5f2998ee, (q31_t)0x5f256515, (q31_t)0x5f213100, (q31_t)0x5f1cfcb1, + (q31_t)0x5f18c827, (q31_t)0x5f149363, (q31_t)0x5f105e64, (q31_t)0x5f0c292a, (q31_t)0x5f07f3b6, (q31_t)0x5f03be07, (q31_t)0x5eff881d, (q31_t)0x5efb51f9, + (q31_t)0x5ef71b9b, (q31_t)0x5ef2e501, (q31_t)0x5eeeae2d, (q31_t)0x5eea771f, (q31_t)0x5ee63fd6, (q31_t)0x5ee20853, (q31_t)0x5eddd094, (q31_t)0x5ed9989c, + (q31_t)0x5ed56069, (q31_t)0x5ed127fb, (q31_t)0x5eccef53, (q31_t)0x5ec8b671, (q31_t)0x5ec47d54, (q31_t)0x5ec043fc, (q31_t)0x5ebc0a6a, (q31_t)0x5eb7d09e, + (q31_t)0x5eb39697, (q31_t)0x5eaf5c56, (q31_t)0x5eab21da, (q31_t)0x5ea6e724, (q31_t)0x5ea2ac34, (q31_t)0x5e9e7109, (q31_t)0x5e9a35a4, (q31_t)0x5e95fa05, + (q31_t)0x5e91be2b, (q31_t)0x5e8d8217, (q31_t)0x5e8945c8, (q31_t)0x5e85093f, (q31_t)0x5e80cc7c, (q31_t)0x5e7c8f7f, (q31_t)0x5e785247, (q31_t)0x5e7414d5, + (q31_t)0x5e6fd729, (q31_t)0x5e6b9943, (q31_t)0x5e675b22, (q31_t)0x5e631cc7, (q31_t)0x5e5ede32, (q31_t)0x5e5a9f62, (q31_t)0x5e566059, (q31_t)0x5e522115, + (q31_t)0x5e4de197, (q31_t)0x5e49a1df, (q31_t)0x5e4561ed, (q31_t)0x5e4121c0, (q31_t)0x5e3ce15a, (q31_t)0x5e38a0b9, (q31_t)0x5e345fde, (q31_t)0x5e301ec9, + (q31_t)0x5e2bdd7a, (q31_t)0x5e279bf1, (q31_t)0x5e235a2e, (q31_t)0x5e1f1830, (q31_t)0x5e1ad5f9, (q31_t)0x5e169388, (q31_t)0x5e1250dc, (q31_t)0x5e0e0df7, + (q31_t)0x5e09cad7, (q31_t)0x5e05877e, (q31_t)0x5e0143ea, (q31_t)0x5dfd001d, (q31_t)0x5df8bc15, (q31_t)0x5df477d4, (q31_t)0x5df03359, (q31_t)0x5debeea3, + (q31_t)0x5de7a9b4, (q31_t)0x5de3648b, (q31_t)0x5ddf1f28, (q31_t)0x5ddad98b, (q31_t)0x5dd693b4, (q31_t)0x5dd24da3, (q31_t)0x5dce0759, (q31_t)0x5dc9c0d4, + (q31_t)0x5dc57a16, (q31_t)0x5dc1331d, (q31_t)0x5dbcebeb, (q31_t)0x5db8a480, (q31_t)0x5db45cda, (q31_t)0x5db014fa, (q31_t)0x5dabcce1, (q31_t)0x5da7848e, + (q31_t)0x5da33c01, (q31_t)0x5d9ef33b, (q31_t)0x5d9aaa3a, (q31_t)0x5d966100, (q31_t)0x5d92178d, (q31_t)0x5d8dcddf, (q31_t)0x5d8983f8, (q31_t)0x5d8539d7, + (q31_t)0x5d80ef7c, (q31_t)0x5d7ca4e8, (q31_t)0x5d785a1a, (q31_t)0x5d740f12, (q31_t)0x5d6fc3d1, (q31_t)0x5d6b7856, (q31_t)0x5d672ca2, (q31_t)0x5d62e0b4, + (q31_t)0x5d5e948c, (q31_t)0x5d5a482a, (q31_t)0x5d55fb90, (q31_t)0x5d51aebb, (q31_t)0x5d4d61ad, (q31_t)0x5d491465, (q31_t)0x5d44c6e4, (q31_t)0x5d40792a, + (q31_t)0x5d3c2b35, (q31_t)0x5d37dd08, (q31_t)0x5d338ea0, (q31_t)0x5d2f4000, (q31_t)0x5d2af125, (q31_t)0x5d26a212, (q31_t)0x5d2252c5, (q31_t)0x5d1e033e, + (q31_t)0x5d19b37e, (q31_t)0x5d156385, (q31_t)0x5d111352, (q31_t)0x5d0cc2e5, (q31_t)0x5d087240, (q31_t)0x5d042161, (q31_t)0x5cffd048, (q31_t)0x5cfb7ef7, + (q31_t)0x5cf72d6b, (q31_t)0x5cf2dba7, (q31_t)0x5cee89a9, (q31_t)0x5cea3772, (q31_t)0x5ce5e501, (q31_t)0x5ce19258, (q31_t)0x5cdd3f75, (q31_t)0x5cd8ec58, + (q31_t)0x5cd49903, (q31_t)0x5cd04574, (q31_t)0x5ccbf1ab, (q31_t)0x5cc79daa, (q31_t)0x5cc3496f, (q31_t)0x5cbef4fc, (q31_t)0x5cbaa04f, (q31_t)0x5cb64b68, + (q31_t)0x5cb1f649, (q31_t)0x5cada0f0, (q31_t)0x5ca94b5e, (q31_t)0x5ca4f594, (q31_t)0x5ca09f8f, (q31_t)0x5c9c4952, (q31_t)0x5c97f2dc, (q31_t)0x5c939c2c, + (q31_t)0x5c8f4544, (q31_t)0x5c8aee22, (q31_t)0x5c8696c7, (q31_t)0x5c823f34, (q31_t)0x5c7de767, (q31_t)0x5c798f61, (q31_t)0x5c753722, (q31_t)0x5c70deaa, + (q31_t)0x5c6c85f9, (q31_t)0x5c682d0f, (q31_t)0x5c63d3eb, (q31_t)0x5c5f7a8f, (q31_t)0x5c5b20fa, (q31_t)0x5c56c72c, (q31_t)0x5c526d25, (q31_t)0x5c4e12e5, + (q31_t)0x5c49b86d, (q31_t)0x5c455dbb, (q31_t)0x5c4102d0, (q31_t)0x5c3ca7ad, (q31_t)0x5c384c50, (q31_t)0x5c33f0bb, (q31_t)0x5c2f94ec, (q31_t)0x5c2b38e5, + (q31_t)0x5c26dca5, (q31_t)0x5c22802c, (q31_t)0x5c1e237b, (q31_t)0x5c19c690, (q31_t)0x5c15696d, (q31_t)0x5c110c11, (q31_t)0x5c0cae7c, (q31_t)0x5c0850ae, + (q31_t)0x5c03f2a8, (q31_t)0x5bff9469, (q31_t)0x5bfb35f1, (q31_t)0x5bf6d740, (q31_t)0x5bf27857, (q31_t)0x5bee1935, (q31_t)0x5be9b9da, (q31_t)0x5be55a46, + (q31_t)0x5be0fa7a, (q31_t)0x5bdc9a75, (q31_t)0x5bd83a37, (q31_t)0x5bd3d9c1, (q31_t)0x5bcf7912, (q31_t)0x5bcb182b, (q31_t)0x5bc6b70b, (q31_t)0x5bc255b2, + (q31_t)0x5bbdf421, (q31_t)0x5bb99257, (q31_t)0x5bb53054, (q31_t)0x5bb0ce19, (q31_t)0x5bac6ba6, (q31_t)0x5ba808f9, (q31_t)0x5ba3a615, (q31_t)0x5b9f42f7, + (q31_t)0x5b9adfa2, (q31_t)0x5b967c13, (q31_t)0x5b92184d, (q31_t)0x5b8db44d, (q31_t)0x5b895016, (q31_t)0x5b84eba6, (q31_t)0x5b8086fd, (q31_t)0x5b7c221c, + (q31_t)0x5b77bd02, (q31_t)0x5b7357b0, (q31_t)0x5b6ef226, (q31_t)0x5b6a8c63, (q31_t)0x5b662668, (q31_t)0x5b61c035, (q31_t)0x5b5d59c9, (q31_t)0x5b58f324, + (q31_t)0x5b548c48, (q31_t)0x5b502533, (q31_t)0x5b4bbde6, (q31_t)0x5b475660, (q31_t)0x5b42eea2, (q31_t)0x5b3e86ac, (q31_t)0x5b3a1e7e, (q31_t)0x5b35b617, + (q31_t)0x5b314d78, (q31_t)0x5b2ce4a1, (q31_t)0x5b287b91, (q31_t)0x5b241249, (q31_t)0x5b1fa8c9, (q31_t)0x5b1b3f11, (q31_t)0x5b16d521, (q31_t)0x5b126af8, + (q31_t)0x5b0e0098, (q31_t)0x5b0995ff, (q31_t)0x5b052b2e, (q31_t)0x5b00c025, (q31_t)0x5afc54e3, (q31_t)0x5af7e96a, (q31_t)0x5af37db8, (q31_t)0x5aef11cf, + (q31_t)0x5aeaa5ad, (q31_t)0x5ae63953, (q31_t)0x5ae1ccc1, (q31_t)0x5add5ff7, (q31_t)0x5ad8f2f5, (q31_t)0x5ad485bb, (q31_t)0x5ad01849, (q31_t)0x5acbaa9f, + (q31_t)0x5ac73cbd, (q31_t)0x5ac2cea3, (q31_t)0x5abe6050, (q31_t)0x5ab9f1c6, (q31_t)0x5ab58304, (q31_t)0x5ab1140a, (q31_t)0x5aaca4d8, (q31_t)0x5aa8356f, + (q31_t)0x5aa3c5cd, (q31_t)0x5a9f55f3, (q31_t)0x5a9ae5e2, (q31_t)0x5a967598, (q31_t)0x5a920517, (q31_t)0x5a8d945d, (q31_t)0x5a89236c, (q31_t)0x5a84b243, + (q31_t)0x5a8040e3, (q31_t)0x5a7bcf4a, (q31_t)0x5a775d7a, (q31_t)0x5a72eb71, (q31_t)0x5a6e7931, (q31_t)0x5a6a06ba, (q31_t)0x5a65940a, (q31_t)0x5a612123, + (q31_t)0x5a5cae04, (q31_t)0x5a583aad, (q31_t)0x5a53c71e, (q31_t)0x5a4f5358, (q31_t)0x5a4adf5a, (q31_t)0x5a466b24, (q31_t)0x5a41f6b7, (q31_t)0x5a3d8212, + (q31_t)0x5a390d35, (q31_t)0x5a349821, (q31_t)0x5a3022d5, (q31_t)0x5a2bad51, (q31_t)0x5a273796, (q31_t)0x5a22c1a3, (q31_t)0x5a1e4b79, (q31_t)0x5a19d517, + (q31_t)0x5a155e7d, (q31_t)0x5a10e7ac, (q31_t)0x5a0c70a3, (q31_t)0x5a07f963, (q31_t)0x5a0381eb, (q31_t)0x59ff0a3c, (q31_t)0x59fa9255, (q31_t)0x59f61a36, + (q31_t)0x59f1a1e0, (q31_t)0x59ed2953, (q31_t)0x59e8b08e, (q31_t)0x59e43792, (q31_t)0x59dfbe5e, (q31_t)0x59db44f3, (q31_t)0x59d6cb50, (q31_t)0x59d25176, + (q31_t)0x59cdd765, (q31_t)0x59c95d1c, (q31_t)0x59c4e29c, (q31_t)0x59c067e4, (q31_t)0x59bbecf5, (q31_t)0x59b771cf, (q31_t)0x59b2f671, (q31_t)0x59ae7add, + (q31_t)0x59a9ff10, (q31_t)0x59a5830d, (q31_t)0x59a106d2, (q31_t)0x599c8a60, (q31_t)0x59980db6, (q31_t)0x599390d5, (q31_t)0x598f13bd, (q31_t)0x598a966e, + (q31_t)0x598618e8, (q31_t)0x59819b2a, (q31_t)0x597d1d35, (q31_t)0x59789f09, (q31_t)0x597420a6, (q31_t)0x596fa20b, (q31_t)0x596b233a, (q31_t)0x5966a431, + (q31_t)0x596224f1, (q31_t)0x595da57a, (q31_t)0x595925cc, (q31_t)0x5954a5e6, (q31_t)0x595025ca, (q31_t)0x594ba576, (q31_t)0x594724ec, (q31_t)0x5942a42a, + (q31_t)0x593e2331, (q31_t)0x5939a202, (q31_t)0x5935209b, (q31_t)0x59309efd, (q31_t)0x592c1d28, (q31_t)0x59279b1c, (q31_t)0x592318d9, (q31_t)0x591e9660, + (q31_t)0x591a13af, (q31_t)0x591590c7, (q31_t)0x59110da8, (q31_t)0x590c8a53, (q31_t)0x590806c6, (q31_t)0x59038302, (q31_t)0x58feff08, (q31_t)0x58fa7ad7, + (q31_t)0x58f5f66e, (q31_t)0x58f171cf, (q31_t)0x58ececf9, (q31_t)0x58e867ed, (q31_t)0x58e3e2a9, (q31_t)0x58df5d2e, (q31_t)0x58dad77d, (q31_t)0x58d65195, + (q31_t)0x58d1cb76, (q31_t)0x58cd4520, (q31_t)0x58c8be94, (q31_t)0x58c437d1, (q31_t)0x58bfb0d7, (q31_t)0x58bb29a6, (q31_t)0x58b6a23e, (q31_t)0x58b21aa0, + (q31_t)0x58ad92cb, (q31_t)0x58a90ac0, (q31_t)0x58a4827d, (q31_t)0x589ffa04, (q31_t)0x589b7155, (q31_t)0x5896e86f, (q31_t)0x58925f52, (q31_t)0x588dd5fe, + (q31_t)0x58894c74, (q31_t)0x5884c2b3, (q31_t)0x588038bb, (q31_t)0x587bae8d, (q31_t)0x58772429, (q31_t)0x5872998e, (q31_t)0x586e0ebc, (q31_t)0x586983b4, + (q31_t)0x5864f875, (q31_t)0x58606d00, (q31_t)0x585be154, (q31_t)0x58575571, (q31_t)0x5852c958, (q31_t)0x584e3d09, (q31_t)0x5849b083, (q31_t)0x584523c7, + (q31_t)0x584096d4, (q31_t)0x583c09ab, (q31_t)0x58377c4c, (q31_t)0x5832eeb6, (q31_t)0x582e60e9, (q31_t)0x5829d2e6, (q31_t)0x582544ad, (q31_t)0x5820b63e, + (q31_t)0x581c2798, (q31_t)0x581798bb, (q31_t)0x581309a9, (q31_t)0x580e7a60, (q31_t)0x5809eae1, (q31_t)0x58055b2b, (q31_t)0x5800cb3f, (q31_t)0x57fc3b1d, + (q31_t)0x57f7aac5, (q31_t)0x57f31a36, (q31_t)0x57ee8971, (q31_t)0x57e9f876, (q31_t)0x57e56744, (q31_t)0x57e0d5dd, (q31_t)0x57dc443f, (q31_t)0x57d7b26b, + (q31_t)0x57d32061, (q31_t)0x57ce8e20, (q31_t)0x57c9fbaa, (q31_t)0x57c568fd, (q31_t)0x57c0d61a, (q31_t)0x57bc4301, (q31_t)0x57b7afb2, (q31_t)0x57b31c2d, + (q31_t)0x57ae8872, (q31_t)0x57a9f480, (q31_t)0x57a56059, (q31_t)0x57a0cbfb, (q31_t)0x579c3768, (q31_t)0x5797a29e, (q31_t)0x57930d9e, (q31_t)0x578e7869, + (q31_t)0x5789e2fd, (q31_t)0x57854d5b, (q31_t)0x5780b784, (q31_t)0x577c2176, (q31_t)0x57778b32, (q31_t)0x5772f4b9, (q31_t)0x576e5e09, (q31_t)0x5769c724, + (q31_t)0x57653009, (q31_t)0x576098b7, (q31_t)0x575c0130, (q31_t)0x57576973, (q31_t)0x5752d180, (q31_t)0x574e3957, (q31_t)0x5749a0f9, (q31_t)0x57450864, + (q31_t)0x57406f9a, (q31_t)0x573bd69a, (q31_t)0x57373d64, (q31_t)0x5732a3f8, (q31_t)0x572e0a56, (q31_t)0x5729707f, (q31_t)0x5724d672, (q31_t)0x57203c2f, + (q31_t)0x571ba1b7, (q31_t)0x57170708, (q31_t)0x57126c24, (q31_t)0x570dd10a, (q31_t)0x570935bb, (q31_t)0x57049a36, (q31_t)0x56fffe7b, (q31_t)0x56fb628b, + (q31_t)0x56f6c664, (q31_t)0x56f22a09, (q31_t)0x56ed8d77, (q31_t)0x56e8f0b0, (q31_t)0x56e453b4, (q31_t)0x56dfb681, (q31_t)0x56db1919, (q31_t)0x56d67b7c, + (q31_t)0x56d1dda9, (q31_t)0x56cd3fa1, (q31_t)0x56c8a162, (q31_t)0x56c402ef, (q31_t)0x56bf6446, (q31_t)0x56bac567, (q31_t)0x56b62653, (q31_t)0x56b18709, + (q31_t)0x56ace78a, (q31_t)0x56a847d6, (q31_t)0x56a3a7ec, (q31_t)0x569f07cc, (q31_t)0x569a6777, (q31_t)0x5695c6ed, (q31_t)0x5691262d, (q31_t)0x568c8538, + (q31_t)0x5687e40e, (q31_t)0x568342ae, (q31_t)0x567ea118, (q31_t)0x5679ff4e, (q31_t)0x56755d4e, (q31_t)0x5670bb19, (q31_t)0x566c18ae, (q31_t)0x5667760e, + (q31_t)0x5662d339, (q31_t)0x565e302e, (q31_t)0x56598cee, (q31_t)0x5654e979, (q31_t)0x565045cf, (q31_t)0x564ba1f0, (q31_t)0x5646fddb, (q31_t)0x56425991, + (q31_t)0x563db512, (q31_t)0x5639105d, (q31_t)0x56346b74, (q31_t)0x562fc655, (q31_t)0x562b2101, (q31_t)0x56267b78, (q31_t)0x5621d5ba, (q31_t)0x561d2fc6, + (q31_t)0x5618899e, (q31_t)0x5613e340, (q31_t)0x560f3cae, (q31_t)0x560a95e6, (q31_t)0x5605eee9, (q31_t)0x560147b7, (q31_t)0x55fca050, (q31_t)0x55f7f8b4, + (q31_t)0x55f350e3, (q31_t)0x55eea8dd, (q31_t)0x55ea00a2, (q31_t)0x55e55832, (q31_t)0x55e0af8d, (q31_t)0x55dc06b3, (q31_t)0x55d75da4, (q31_t)0x55d2b460, + (q31_t)0x55ce0ae7, (q31_t)0x55c96139, (q31_t)0x55c4b757, (q31_t)0x55c00d3f, (q31_t)0x55bb62f3, (q31_t)0x55b6b871, (q31_t)0x55b20dbb, (q31_t)0x55ad62d0, + (q31_t)0x55a8b7b0, (q31_t)0x55a40c5b, (q31_t)0x559f60d1, (q31_t)0x559ab513, (q31_t)0x55960920, (q31_t)0x55915cf8, (q31_t)0x558cb09b, (q31_t)0x55880409, + (q31_t)0x55835743, (q31_t)0x557eaa48, (q31_t)0x5579fd18, (q31_t)0x55754fb3, (q31_t)0x5570a21a, (q31_t)0x556bf44c, (q31_t)0x55674649, (q31_t)0x55629812, + (q31_t)0x555de9a6, (q31_t)0x55593b05, (q31_t)0x55548c30, (q31_t)0x554fdd26, (q31_t)0x554b2de7, (q31_t)0x55467e74, (q31_t)0x5541cecc, (q31_t)0x553d1ef0, + (q31_t)0x55386edf, (q31_t)0x5533be99, (q31_t)0x552f0e1f, (q31_t)0x552a5d70, (q31_t)0x5525ac8d, (q31_t)0x5520fb75, (q31_t)0x551c4a29, (q31_t)0x551798a8, + (q31_t)0x5512e6f3, (q31_t)0x550e3509, (q31_t)0x550982eb, (q31_t)0x5504d099, (q31_t)0x55001e12, (q31_t)0x54fb6b56, (q31_t)0x54f6b866, (q31_t)0x54f20542, + (q31_t)0x54ed51e9, (q31_t)0x54e89e5c, (q31_t)0x54e3ea9a, (q31_t)0x54df36a5, (q31_t)0x54da827a, (q31_t)0x54d5ce1c, (q31_t)0x54d11989, (q31_t)0x54cc64c2, + (q31_t)0x54c7afc6, (q31_t)0x54c2fa96, (q31_t)0x54be4532, (q31_t)0x54b98f9a, (q31_t)0x54b4d9cd, (q31_t)0x54b023cc, (q31_t)0x54ab6d97, (q31_t)0x54a6b72e, + (q31_t)0x54a20090, (q31_t)0x549d49bf, (q31_t)0x549892b9, (q31_t)0x5493db7f, (q31_t)0x548f2410, (q31_t)0x548a6c6e, (q31_t)0x5485b497, (q31_t)0x5480fc8c, + (q31_t)0x547c444d, (q31_t)0x54778bda, (q31_t)0x5472d333, (q31_t)0x546e1a58, (q31_t)0x54696149, (q31_t)0x5464a805, (q31_t)0x545fee8e, (q31_t)0x545b34e3, + (q31_t)0x54567b03, (q31_t)0x5451c0f0, (q31_t)0x544d06a8, (q31_t)0x54484c2d, (q31_t)0x5443917d, (q31_t)0x543ed699, (q31_t)0x543a1b82, (q31_t)0x54356037, + (q31_t)0x5430a4b7, (q31_t)0x542be904, (q31_t)0x54272d1d, (q31_t)0x54227102, (q31_t)0x541db4b3, (q31_t)0x5418f830, (q31_t)0x54143b79, (q31_t)0x540f7e8e, + (q31_t)0x540ac170, (q31_t)0x5406041d, (q31_t)0x54014697, (q31_t)0x53fc88dd, (q31_t)0x53f7caef, (q31_t)0x53f30cce, (q31_t)0x53ee4e78, (q31_t)0x53e98fef, + (q31_t)0x53e4d132, (q31_t)0x53e01242, (q31_t)0x53db531d, (q31_t)0x53d693c5, (q31_t)0x53d1d439, (q31_t)0x53cd147a, (q31_t)0x53c85486, (q31_t)0x53c3945f, + (q31_t)0x53bed405, (q31_t)0x53ba1377, (q31_t)0x53b552b5, (q31_t)0x53b091bf, (q31_t)0x53abd096, (q31_t)0x53a70f39, (q31_t)0x53a24da9, (q31_t)0x539d8be5, + (q31_t)0x5398c9ed, (q31_t)0x539407c2, (q31_t)0x538f4564, (q31_t)0x538a82d1, (q31_t)0x5385c00c, (q31_t)0x5380fd12, (q31_t)0x537c39e6, (q31_t)0x53777685, + (q31_t)0x5372b2f2, (q31_t)0x536def2a, (q31_t)0x53692b30, (q31_t)0x53646701, (q31_t)0x535fa2a0, (q31_t)0x535ade0b, (q31_t)0x53561942, (q31_t)0x53515447, + (q31_t)0x534c8f17, (q31_t)0x5347c9b5, (q31_t)0x5343041f, (q31_t)0x533e3e55, (q31_t)0x53397859, (q31_t)0x5334b229, (q31_t)0x532febc5, (q31_t)0x532b252f, + (q31_t)0x53265e65, (q31_t)0x53219767, (q31_t)0x531cd037, (q31_t)0x531808d3, (q31_t)0x5313413c, (q31_t)0x530e7972, (q31_t)0x5309b174, (q31_t)0x5304e943, + (q31_t)0x530020df, (q31_t)0x52fb5848, (q31_t)0x52f68f7e, (q31_t)0x52f1c680, (q31_t)0x52ecfd4f, (q31_t)0x52e833ec, (q31_t)0x52e36a55, (q31_t)0x52dea08a, + (q31_t)0x52d9d68d, (q31_t)0x52d50c5d, (q31_t)0x52d041f9, (q31_t)0x52cb7763, (q31_t)0x52c6ac99, (q31_t)0x52c1e19d, (q31_t)0x52bd166d, (q31_t)0x52b84b0a, + (q31_t)0x52b37f74, (q31_t)0x52aeb3ac, (q31_t)0x52a9e7b0, (q31_t)0x52a51b81, (q31_t)0x52a04f1f, (q31_t)0x529b828a, (q31_t)0x5296b5c3, (q31_t)0x5291e8c8, + (q31_t)0x528d1b9b, (q31_t)0x52884e3a, (q31_t)0x528380a7, (q31_t)0x527eb2e0, (q31_t)0x5279e4e7, (q31_t)0x527516bb, (q31_t)0x5270485c, (q31_t)0x526b79ca, + (q31_t)0x5266ab06, (q31_t)0x5261dc0e, (q31_t)0x525d0ce4, (q31_t)0x52583d87, (q31_t)0x52536df7, (q31_t)0x524e9e34, (q31_t)0x5249ce3f, (q31_t)0x5244fe17, + (q31_t)0x52402dbc, (q31_t)0x523b5d2e, (q31_t)0x52368c6e, (q31_t)0x5231bb7b, (q31_t)0x522cea55, (q31_t)0x522818fc, (q31_t)0x52234771, (q31_t)0x521e75b3, + (q31_t)0x5219a3c3, (q31_t)0x5214d1a0, (q31_t)0x520fff4a, (q31_t)0x520b2cc2, (q31_t)0x52065a07, (q31_t)0x52018719, (q31_t)0x51fcb3f9, (q31_t)0x51f7e0a6, + (q31_t)0x51f30d21, (q31_t)0x51ee3969, (q31_t)0x51e9657e, (q31_t)0x51e49162, (q31_t)0x51dfbd12, (q31_t)0x51dae890, (q31_t)0x51d613dc, (q31_t)0x51d13ef5, + (q31_t)0x51cc69db, (q31_t)0x51c79490, (q31_t)0x51c2bf11, (q31_t)0x51bde960, (q31_t)0x51b9137d, (q31_t)0x51b43d68, (q31_t)0x51af6720, (q31_t)0x51aa90a5, + (q31_t)0x51a5b9f9, (q31_t)0x51a0e31a, (q31_t)0x519c0c08, (q31_t)0x519734c4, (q31_t)0x51925d4e, (q31_t)0x518d85a6, (q31_t)0x5188adcb, (q31_t)0x5183d5be, + (q31_t)0x517efd7f, (q31_t)0x517a250d, (q31_t)0x51754c69, (q31_t)0x51707393, (q31_t)0x516b9a8b, (q31_t)0x5166c150, (q31_t)0x5161e7e4, (q31_t)0x515d0e45, + (q31_t)0x51583473, (q31_t)0x51535a70, (q31_t)0x514e803b, (q31_t)0x5149a5d3, (q31_t)0x5144cb39, (q31_t)0x513ff06d, (q31_t)0x513b156f, (q31_t)0x51363a3f, + (q31_t)0x51315edd, (q31_t)0x512c8348, (q31_t)0x5127a782, (q31_t)0x5122cb8a, (q31_t)0x511def5f, (q31_t)0x51191302, (q31_t)0x51143674, (q31_t)0x510f59b3, + (q31_t)0x510a7cc1, (q31_t)0x51059f9c, (q31_t)0x5100c246, (q31_t)0x50fbe4bd, (q31_t)0x50f70703, (q31_t)0x50f22916, (q31_t)0x50ed4af8, (q31_t)0x50e86ca8, + (q31_t)0x50e38e25, (q31_t)0x50deaf71, (q31_t)0x50d9d08b, (q31_t)0x50d4f173, (q31_t)0x50d0122a, (q31_t)0x50cb32ae, (q31_t)0x50c65301, (q31_t)0x50c17322, + (q31_t)0x50bc9311, (q31_t)0x50b7b2ce, (q31_t)0x50b2d259, (q31_t)0x50adf1b3, (q31_t)0x50a910db, (q31_t)0x50a42fd1, (q31_t)0x509f4e95, (q31_t)0x509a6d28, + (q31_t)0x50958b88, (q31_t)0x5090a9b8, (q31_t)0x508bc7b5, (q31_t)0x5086e581, (q31_t)0x5082031b, (q31_t)0x507d2083, (q31_t)0x50783dba, (q31_t)0x50735abf, + (q31_t)0x506e7793, (q31_t)0x50699435, (q31_t)0x5064b0a5, (q31_t)0x505fcce4, (q31_t)0x505ae8f1, (q31_t)0x505604cd, (q31_t)0x50512077, (q31_t)0x504c3bef, + (q31_t)0x50475736, (q31_t)0x5042724c, (q31_t)0x503d8d30, (q31_t)0x5038a7e2, (q31_t)0x5033c263, (q31_t)0x502edcb2, (q31_t)0x5029f6d1, (q31_t)0x502510bd, + (q31_t)0x50202a78, (q31_t)0x501b4402, (q31_t)0x50165d5a, (q31_t)0x50117681, (q31_t)0x500c8f77, (q31_t)0x5007a83b, (q31_t)0x5002c0cd, (q31_t)0x4ffdd92f, + (q31_t)0x4ff8f15f, (q31_t)0x4ff4095e, (q31_t)0x4fef212b, (q31_t)0x4fea38c7, (q31_t)0x4fe55032, (q31_t)0x4fe0676c, (q31_t)0x4fdb7e74, (q31_t)0x4fd6954b, + (q31_t)0x4fd1abf0, (q31_t)0x4fccc265, (q31_t)0x4fc7d8a8, (q31_t)0x4fc2eeba, (q31_t)0x4fbe049b, (q31_t)0x4fb91a4b, (q31_t)0x4fb42fc9, (q31_t)0x4faf4517, + (q31_t)0x4faa5a33, (q31_t)0x4fa56f1e, (q31_t)0x4fa083d8, (q31_t)0x4f9b9861, (q31_t)0x4f96acb8, (q31_t)0x4f91c0df, (q31_t)0x4f8cd4d4, (q31_t)0x4f87e899, + (q31_t)0x4f82fc2c, (q31_t)0x4f7e0f8f, (q31_t)0x4f7922c0, (q31_t)0x4f7435c0, (q31_t)0x4f6f488f, (q31_t)0x4f6a5b2e, (q31_t)0x4f656d9b, (q31_t)0x4f607fd7, + (q31_t)0x4f5b91e3, (q31_t)0x4f56a3bd, (q31_t)0x4f51b566, (q31_t)0x4f4cc6df, (q31_t)0x4f47d827, (q31_t)0x4f42e93d, (q31_t)0x4f3dfa23, (q31_t)0x4f390ad8, + (q31_t)0x4f341b5c, (q31_t)0x4f2f2baf, (q31_t)0x4f2a3bd2, (q31_t)0x4f254bc3, (q31_t)0x4f205b84, (q31_t)0x4f1b6b14, (q31_t)0x4f167a73, (q31_t)0x4f1189a1, + (q31_t)0x4f0c989f, (q31_t)0x4f07a76b, (q31_t)0x4f02b608, (q31_t)0x4efdc473, (q31_t)0x4ef8d2ad, (q31_t)0x4ef3e0b7, (q31_t)0x4eeeee90, (q31_t)0x4ee9fc39, + (q31_t)0x4ee509b1, (q31_t)0x4ee016f8, (q31_t)0x4edb240e, (q31_t)0x4ed630f4, (q31_t)0x4ed13da9, (q31_t)0x4ecc4a2e, (q31_t)0x4ec75682, (q31_t)0x4ec262a5, + (q31_t)0x4ebd6e98, (q31_t)0x4eb87a5a, (q31_t)0x4eb385ec, (q31_t)0x4eae914d, (q31_t)0x4ea99c7d, (q31_t)0x4ea4a77d, (q31_t)0x4e9fb24d, (q31_t)0x4e9abcec, + (q31_t)0x4e95c75b, (q31_t)0x4e90d199, (q31_t)0x4e8bdba6, (q31_t)0x4e86e583, (q31_t)0x4e81ef30, (q31_t)0x4e7cf8ac, (q31_t)0x4e7801f8, (q31_t)0x4e730b14, + (q31_t)0x4e6e13ff, (q31_t)0x4e691cba, (q31_t)0x4e642544, (q31_t)0x4e5f2d9e, (q31_t)0x4e5a35c7, (q31_t)0x4e553dc1, (q31_t)0x4e50458a, (q31_t)0x4e4b4d22, + (q31_t)0x4e46548b, (q31_t)0x4e415bc3, (q31_t)0x4e3c62cb, (q31_t)0x4e3769a2, (q31_t)0x4e32704a, (q31_t)0x4e2d76c1, (q31_t)0x4e287d08, (q31_t)0x4e23831e, + (q31_t)0x4e1e8905, (q31_t)0x4e198ebb, (q31_t)0x4e149441, (q31_t)0x4e0f9997, (q31_t)0x4e0a9ebd, (q31_t)0x4e05a3b2, (q31_t)0x4e00a878, (q31_t)0x4dfbad0d, + (q31_t)0x4df6b173, (q31_t)0x4df1b5a8, (q31_t)0x4decb9ad, (q31_t)0x4de7bd82, (q31_t)0x4de2c127, (q31_t)0x4dddc49c, (q31_t)0x4dd8c7e1, (q31_t)0x4dd3caf6, + (q31_t)0x4dcecdda, (q31_t)0x4dc9d08f, (q31_t)0x4dc4d314, (q31_t)0x4dbfd569, (q31_t)0x4dbad78e, (q31_t)0x4db5d983, (q31_t)0x4db0db48, (q31_t)0x4dabdcdd, + (q31_t)0x4da6de43, (q31_t)0x4da1df78, (q31_t)0x4d9ce07d, (q31_t)0x4d97e153, (q31_t)0x4d92e1f9, (q31_t)0x4d8de26f, (q31_t)0x4d88e2b5, (q31_t)0x4d83e2cb, + (q31_t)0x4d7ee2b1, (q31_t)0x4d79e268, (q31_t)0x4d74e1ef, (q31_t)0x4d6fe146, (q31_t)0x4d6ae06d, (q31_t)0x4d65df64, (q31_t)0x4d60de2c, (q31_t)0x4d5bdcc4, + (q31_t)0x4d56db2d, (q31_t)0x4d51d965, (q31_t)0x4d4cd76e, (q31_t)0x4d47d547, (q31_t)0x4d42d2f1, (q31_t)0x4d3dd06b, (q31_t)0x4d38cdb5, (q31_t)0x4d33cad0, + (q31_t)0x4d2ec7bb, (q31_t)0x4d29c476, (q31_t)0x4d24c102, (q31_t)0x4d1fbd5e, (q31_t)0x4d1ab98b, (q31_t)0x4d15b588, (q31_t)0x4d10b155, (q31_t)0x4d0bacf3, + (q31_t)0x4d06a862, (q31_t)0x4d01a3a0, (q31_t)0x4cfc9eb0, (q31_t)0x4cf79990, (q31_t)0x4cf29440, (q31_t)0x4ced8ec1, (q31_t)0x4ce88913, (q31_t)0x4ce38335, + (q31_t)0x4cde7d28, (q31_t)0x4cd976eb, (q31_t)0x4cd4707f, (q31_t)0x4ccf69e3, (q31_t)0x4cca6318, (q31_t)0x4cc55c1e, (q31_t)0x4cc054f4, (q31_t)0x4cbb4d9b, + (q31_t)0x4cb64613, (q31_t)0x4cb13e5b, (q31_t)0x4cac3674, (q31_t)0x4ca72e5e, (q31_t)0x4ca22619, (q31_t)0x4c9d1da4, (q31_t)0x4c981500, (q31_t)0x4c930c2d, + (q31_t)0x4c8e032a, (q31_t)0x4c88f9f8, (q31_t)0x4c83f097, (q31_t)0x4c7ee707, (q31_t)0x4c79dd48, (q31_t)0x4c74d359, (q31_t)0x4c6fc93b, (q31_t)0x4c6abeef, + (q31_t)0x4c65b473, (q31_t)0x4c60a9c8, (q31_t)0x4c5b9eed, (q31_t)0x4c5693e4, (q31_t)0x4c5188ac, (q31_t)0x4c4c7d44, (q31_t)0x4c4771ae, (q31_t)0x4c4265e8, + (q31_t)0x4c3d59f3, (q31_t)0x4c384dd0, (q31_t)0x4c33417d, (q31_t)0x4c2e34fb, (q31_t)0x4c29284b, (q31_t)0x4c241b6b, (q31_t)0x4c1f0e5c, (q31_t)0x4c1a011f, + (q31_t)0x4c14f3b2, (q31_t)0x4c0fe617, (q31_t)0x4c0ad84c, (q31_t)0x4c05ca53, (q31_t)0x4c00bc2b, (q31_t)0x4bfbadd4, (q31_t)0x4bf69f4e, (q31_t)0x4bf19099, + (q31_t)0x4bec81b5, (q31_t)0x4be772a3, (q31_t)0x4be26362, (q31_t)0x4bdd53f2, (q31_t)0x4bd84453, (q31_t)0x4bd33485, (q31_t)0x4bce2488, (q31_t)0x4bc9145d, + (q31_t)0x4bc40403, (q31_t)0x4bbef37b, (q31_t)0x4bb9e2c3, (q31_t)0x4bb4d1dd, (q31_t)0x4bafc0c8, (q31_t)0x4baaaf85, (q31_t)0x4ba59e12, (q31_t)0x4ba08c72, + (q31_t)0x4b9b7aa2, (q31_t)0x4b9668a4, (q31_t)0x4b915677, (q31_t)0x4b8c441c, (q31_t)0x4b873192, (q31_t)0x4b821ed9, (q31_t)0x4b7d0bf2, (q31_t)0x4b77f8dc, + (q31_t)0x4b72e598, (q31_t)0x4b6dd225, (q31_t)0x4b68be84, (q31_t)0x4b63aab4, (q31_t)0x4b5e96b6, (q31_t)0x4b598289, (q31_t)0x4b546e2d, (q31_t)0x4b4f59a4, + (q31_t)0x4b4a44eb, (q31_t)0x4b453005, (q31_t)0x4b401aef, (q31_t)0x4b3b05ac, (q31_t)0x4b35f03a, (q31_t)0x4b30da9a, (q31_t)0x4b2bc4cb, (q31_t)0x4b26aece, + (q31_t)0x4b2198a2, (q31_t)0x4b1c8248, (q31_t)0x4b176bc0, (q31_t)0x4b12550a, (q31_t)0x4b0d3e25, (q31_t)0x4b082712, (q31_t)0x4b030fd1, (q31_t)0x4afdf861, + (q31_t)0x4af8e0c3, (q31_t)0x4af3c8f7, (q31_t)0x4aeeb0fd, (q31_t)0x4ae998d4, (q31_t)0x4ae4807d, (q31_t)0x4adf67f8, (q31_t)0x4ada4f45, (q31_t)0x4ad53664, + (q31_t)0x4ad01d54, (q31_t)0x4acb0417, (q31_t)0x4ac5eaab, (q31_t)0x4ac0d111, (q31_t)0x4abbb749, (q31_t)0x4ab69d53, (q31_t)0x4ab1832f, (q31_t)0x4aac68dc, + (q31_t)0x4aa74e5c, (q31_t)0x4aa233ae, (q31_t)0x4a9d18d1, (q31_t)0x4a97fdc7, (q31_t)0x4a92e28e, (q31_t)0x4a8dc728, (q31_t)0x4a88ab93, (q31_t)0x4a838fd1, + (q31_t)0x4a7e73e0, (q31_t)0x4a7957c2, (q31_t)0x4a743b76, (q31_t)0x4a6f1efc, (q31_t)0x4a6a0253, (q31_t)0x4a64e57d, (q31_t)0x4a5fc879, (q31_t)0x4a5aab48, + (q31_t)0x4a558de8, (q31_t)0x4a50705a, (q31_t)0x4a4b529f, (q31_t)0x4a4634b6, (q31_t)0x4a41169f, (q31_t)0x4a3bf85a, (q31_t)0x4a36d9e7, (q31_t)0x4a31bb47, + (q31_t)0x4a2c9c79, (q31_t)0x4a277d7d, (q31_t)0x4a225e53, (q31_t)0x4a1d3efc, (q31_t)0x4a181f77, (q31_t)0x4a12ffc4, (q31_t)0x4a0ddfe4, (q31_t)0x4a08bfd5, + (q31_t)0x4a039f9a, (q31_t)0x49fe7f30, (q31_t)0x49f95e99, (q31_t)0x49f43dd4, (q31_t)0x49ef1ce2, (q31_t)0x49e9fbc2, (q31_t)0x49e4da74, (q31_t)0x49dfb8f9, + (q31_t)0x49da9750, (q31_t)0x49d5757a, (q31_t)0x49d05376, (q31_t)0x49cb3145, (q31_t)0x49c60ee6, (q31_t)0x49c0ec59, (q31_t)0x49bbc9a0, (q31_t)0x49b6a6b8, + (q31_t)0x49b183a3, (q31_t)0x49ac6061, (q31_t)0x49a73cf1, (q31_t)0x49a21954, (q31_t)0x499cf589, (q31_t)0x4997d191, (q31_t)0x4992ad6c, (q31_t)0x498d8919, + (q31_t)0x49886499, (q31_t)0x49833fec, (q31_t)0x497e1b11, (q31_t)0x4978f609, (q31_t)0x4973d0d3, (q31_t)0x496eab70, (q31_t)0x496985e0, (q31_t)0x49646023, + (q31_t)0x495f3a38, (q31_t)0x495a1420, (q31_t)0x4954eddb, (q31_t)0x494fc768, (q31_t)0x494aa0c9, (q31_t)0x494579fc, (q31_t)0x49405302, (q31_t)0x493b2bdb, + (q31_t)0x49360486, (q31_t)0x4930dd05, (q31_t)0x492bb556, (q31_t)0x49268d7a, (q31_t)0x49216571, (q31_t)0x491c3d3b, (q31_t)0x491714d8, (q31_t)0x4911ec47, + (q31_t)0x490cc38a, (q31_t)0x49079aa0, (q31_t)0x49027188, (q31_t)0x48fd4844, (q31_t)0x48f81ed2, (q31_t)0x48f2f534, (q31_t)0x48edcb68, (q31_t)0x48e8a170, + (q31_t)0x48e3774a, (q31_t)0x48de4cf8, (q31_t)0x48d92278, (q31_t)0x48d3f7cc, (q31_t)0x48ceccf3, (q31_t)0x48c9a1ed, (q31_t)0x48c476b9, (q31_t)0x48bf4b59, + (q31_t)0x48ba1fcd, (q31_t)0x48b4f413, (q31_t)0x48afc82c, (q31_t)0x48aa9c19, (q31_t)0x48a56fd9, (q31_t)0x48a0436c, (q31_t)0x489b16d2, (q31_t)0x4895ea0b, + (q31_t)0x4890bd18, (q31_t)0x488b8ff8, (q31_t)0x488662ab, (q31_t)0x48813531, (q31_t)0x487c078b, (q31_t)0x4876d9b8, (q31_t)0x4871abb8, (q31_t)0x486c7d8c, + (q31_t)0x48674f33, (q31_t)0x486220ad, (q31_t)0x485cf1fa, (q31_t)0x4857c31b, (q31_t)0x48529410, (q31_t)0x484d64d7, (q31_t)0x48483572, (q31_t)0x484305e1, + (q31_t)0x483dd623, (q31_t)0x4838a638, (q31_t)0x48337621, (q31_t)0x482e45dd, (q31_t)0x4829156d, (q31_t)0x4823e4d0, (q31_t)0x481eb407, (q31_t)0x48198311, + (q31_t)0x481451ef, (q31_t)0x480f20a0, (q31_t)0x4809ef25, (q31_t)0x4804bd7e, (q31_t)0x47ff8baa, (q31_t)0x47fa59a9, (q31_t)0x47f5277d, (q31_t)0x47eff523, + (q31_t)0x47eac29e, (q31_t)0x47e58fec, (q31_t)0x47e05d0e, (q31_t)0x47db2a03, (q31_t)0x47d5f6cc, (q31_t)0x47d0c369, (q31_t)0x47cb8fd9, (q31_t)0x47c65c1d, + (q31_t)0x47c12835, (q31_t)0x47bbf421, (q31_t)0x47b6bfe0, (q31_t)0x47b18b74, (q31_t)0x47ac56da, (q31_t)0x47a72215, (q31_t)0x47a1ed24, (q31_t)0x479cb806, + (q31_t)0x479782bc, (q31_t)0x47924d46, (q31_t)0x478d17a4, (q31_t)0x4787e1d6, (q31_t)0x4782abdb, (q31_t)0x477d75b5, (q31_t)0x47783f62, (q31_t)0x477308e3, + (q31_t)0x476dd239, (q31_t)0x47689b62, (q31_t)0x4763645f, (q31_t)0x475e2d30, (q31_t)0x4758f5d5, (q31_t)0x4753be4e, (q31_t)0x474e869b, (q31_t)0x47494ebc, + (q31_t)0x474416b1, (q31_t)0x473ede7a, (q31_t)0x4739a617, (q31_t)0x47346d89, (q31_t)0x472f34ce, (q31_t)0x4729fbe7, (q31_t)0x4724c2d5, (q31_t)0x471f8996, + (q31_t)0x471a502c, (q31_t)0x47151696, (q31_t)0x470fdcd4, (q31_t)0x470aa2e6, (q31_t)0x470568cd, (q31_t)0x47002e87, (q31_t)0x46faf416, (q31_t)0x46f5b979, + (q31_t)0x46f07eb0, (q31_t)0x46eb43bc, (q31_t)0x46e6089b, (q31_t)0x46e0cd4f, (q31_t)0x46db91d8, (q31_t)0x46d65634, (q31_t)0x46d11a65, (q31_t)0x46cbde6a, + (q31_t)0x46c6a244, (q31_t)0x46c165f1, (q31_t)0x46bc2974, (q31_t)0x46b6ecca, (q31_t)0x46b1aff5, (q31_t)0x46ac72f4, (q31_t)0x46a735c8, (q31_t)0x46a1f870, + (q31_t)0x469cbaed, (q31_t)0x46977d3e, (q31_t)0x46923f63, (q31_t)0x468d015d, (q31_t)0x4687c32c, (q31_t)0x468284cf, (q31_t)0x467d4646, (q31_t)0x46780792, + (q31_t)0x4672c8b3, (q31_t)0x466d89a8, (q31_t)0x46684a71, (q31_t)0x46630b0f, (q31_t)0x465dcb82, (q31_t)0x46588bc9, (q31_t)0x46534be5, (q31_t)0x464e0bd6, + (q31_t)0x4648cb9b, (q31_t)0x46438b35, (q31_t)0x463e4aa3, (q31_t)0x463909e7, (q31_t)0x4633c8fe, (q31_t)0x462e87eb, (q31_t)0x462946ac, (q31_t)0x46240542, + (q31_t)0x461ec3ad, (q31_t)0x461981ec, (q31_t)0x46144001, (q31_t)0x460efde9, (q31_t)0x4609bba7, (q31_t)0x4604793a, (q31_t)0x45ff36a1, (q31_t)0x45f9f3dd, + (q31_t)0x45f4b0ee, (q31_t)0x45ef6dd4, (q31_t)0x45ea2a8f, (q31_t)0x45e4e71f, (q31_t)0x45dfa383, (q31_t)0x45da5fbc, (q31_t)0x45d51bcb, (q31_t)0x45cfd7ae, + (q31_t)0x45ca9366, (q31_t)0x45c54ef3, (q31_t)0x45c00a55, (q31_t)0x45bac58c, (q31_t)0x45b58098, (q31_t)0x45b03b79, (q31_t)0x45aaf630, (q31_t)0x45a5b0bb, + (q31_t)0x45a06b1b, (q31_t)0x459b2550, (q31_t)0x4595df5a, (q31_t)0x45909939, (q31_t)0x458b52ee, (q31_t)0x45860c77, (q31_t)0x4580c5d6, (q31_t)0x457b7f0a, + (q31_t)0x45763813, (q31_t)0x4570f0f1, (q31_t)0x456ba9a4, (q31_t)0x4566622c, (q31_t)0x45611a8a, (q31_t)0x455bd2bc, (q31_t)0x45568ac4, (q31_t)0x455142a2, + (q31_t)0x454bfa54, (q31_t)0x4546b1dc, (q31_t)0x45416939, (q31_t)0x453c206b, (q31_t)0x4536d773, (q31_t)0x45318e4f, (q31_t)0x452c4502, (q31_t)0x4526fb89, + (q31_t)0x4521b1e6, (q31_t)0x451c6818, (q31_t)0x45171e20, (q31_t)0x4511d3fd, (q31_t)0x450c89af, (q31_t)0x45073f37, (q31_t)0x4501f494, (q31_t)0x44fca9c6, + (q31_t)0x44f75ecf, (q31_t)0x44f213ac, (q31_t)0x44ecc85f, (q31_t)0x44e77ce7, (q31_t)0x44e23145, (q31_t)0x44dce579, (q31_t)0x44d79982, (q31_t)0x44d24d60, + (q31_t)0x44cd0114, (q31_t)0x44c7b49e, (q31_t)0x44c267fd, (q31_t)0x44bd1b32, (q31_t)0x44b7ce3c, (q31_t)0x44b2811c, (q31_t)0x44ad33d2, (q31_t)0x44a7e65d, + (q31_t)0x44a298be, (q31_t)0x449d4af5, (q31_t)0x4497fd01, (q31_t)0x4492aee3, (q31_t)0x448d609b, (q31_t)0x44881228, (q31_t)0x4482c38b, (q31_t)0x447d74c4, + (q31_t)0x447825d2, (q31_t)0x4472d6b7, (q31_t)0x446d8771, (q31_t)0x44683801, (q31_t)0x4462e866, (q31_t)0x445d98a2, (q31_t)0x445848b3, (q31_t)0x4452f89b, + (q31_t)0x444da858, (q31_t)0x444857ea, (q31_t)0x44430753, (q31_t)0x443db692, (q31_t)0x443865a7, (q31_t)0x44331491, (q31_t)0x442dc351, (q31_t)0x442871e8, + (q31_t)0x44232054, (q31_t)0x441dce96, (q31_t)0x44187caf, (q31_t)0x44132a9d, (q31_t)0x440dd861, (q31_t)0x440885fc, (q31_t)0x4403336c, (q31_t)0x43fde0b2, + (q31_t)0x43f88dcf, (q31_t)0x43f33ac1, (q31_t)0x43ede78a, (q31_t)0x43e89429, (q31_t)0x43e3409d, (q31_t)0x43ddece8, (q31_t)0x43d8990a, (q31_t)0x43d34501, + (q31_t)0x43cdf0ce, (q31_t)0x43c89c72, (q31_t)0x43c347eb, (q31_t)0x43bdf33b, (q31_t)0x43b89e62, (q31_t)0x43b3495e, (q31_t)0x43adf431, (q31_t)0x43a89ed9, + (q31_t)0x43a34959, (q31_t)0x439df3ae, (q31_t)0x43989dda, (q31_t)0x439347dc, (q31_t)0x438df1b4, (q31_t)0x43889b63, (q31_t)0x438344e8, (q31_t)0x437dee43, + (q31_t)0x43789775, (q31_t)0x4373407d, (q31_t)0x436de95b, (q31_t)0x43689210, (q31_t)0x43633a9c, (q31_t)0x435de2fd, (q31_t)0x43588b36, (q31_t)0x43533344, + (q31_t)0x434ddb29, (q31_t)0x434882e5, (q31_t)0x43432a77, (q31_t)0x433dd1e0, (q31_t)0x4338791f, (q31_t)0x43332035, (q31_t)0x432dc721, (q31_t)0x43286de4, + (q31_t)0x4323147d, (q31_t)0x431dbaed, (q31_t)0x43186133, (q31_t)0x43130751, (q31_t)0x430dad44, (q31_t)0x4308530f, (q31_t)0x4302f8b0, (q31_t)0x42fd9e28, + (q31_t)0x42f84376, (q31_t)0x42f2e89b, (q31_t)0x42ed8d97, (q31_t)0x42e83269, (q31_t)0x42e2d713, (q31_t)0x42dd7b93, (q31_t)0x42d81fe9, (q31_t)0x42d2c417, + (q31_t)0x42cd681b, (q31_t)0x42c80bf6, (q31_t)0x42c2afa8, (q31_t)0x42bd5331, (q31_t)0x42b7f690, (q31_t)0x42b299c7, (q31_t)0x42ad3cd4, (q31_t)0x42a7dfb8, + (q31_t)0x42a28273, (q31_t)0x429d2505, (q31_t)0x4297c76e, (q31_t)0x429269ae, (q31_t)0x428d0bc4, (q31_t)0x4287adb2, (q31_t)0x42824f76, (q31_t)0x427cf112, + (q31_t)0x42779285, (q31_t)0x427233ce, (q31_t)0x426cd4ef, (q31_t)0x426775e6, (q31_t)0x426216b5, (q31_t)0x425cb75a, (q31_t)0x425757d7, (q31_t)0x4251f82b, + (q31_t)0x424c9856, (q31_t)0x42473858, (q31_t)0x4241d831, (q31_t)0x423c77e1, (q31_t)0x42371769, (q31_t)0x4231b6c7, (q31_t)0x422c55fd, (q31_t)0x4226f50a, + (q31_t)0x422193ee, (q31_t)0x421c32a9, (q31_t)0x4216d13c, (q31_t)0x42116fa5, (q31_t)0x420c0de6, (q31_t)0x4206abfe, (q31_t)0x420149ee, (q31_t)0x41fbe7b5, + (q31_t)0x41f68553, (q31_t)0x41f122c8, (q31_t)0x41ebc015, (q31_t)0x41e65d39, (q31_t)0x41e0fa35, (q31_t)0x41db9707, (q31_t)0x41d633b1, (q31_t)0x41d0d033, + (q31_t)0x41cb6c8c, (q31_t)0x41c608bc, (q31_t)0x41c0a4c4, (q31_t)0x41bb40a3, (q31_t)0x41b5dc5a, (q31_t)0x41b077e8, (q31_t)0x41ab134e, (q31_t)0x41a5ae8b, + (q31_t)0x41a049a0, (q31_t)0x419ae48c, (q31_t)0x41957f4f, (q31_t)0x419019eb, (q31_t)0x418ab45d, (q31_t)0x41854ea8, (q31_t)0x417fe8ca, (q31_t)0x417a82c3, + (q31_t)0x41751c94, (q31_t)0x416fb63d, (q31_t)0x416a4fbd, (q31_t)0x4164e916, (q31_t)0x415f8245, (q31_t)0x415a1b4d, (q31_t)0x4154b42c, (q31_t)0x414f4ce2, + (q31_t)0x4149e571, (q31_t)0x41447dd7, (q31_t)0x413f1615, (q31_t)0x4139ae2b, (q31_t)0x41344618, (q31_t)0x412edddd, (q31_t)0x4129757b, (q31_t)0x41240cef, + (q31_t)0x411ea43c, (q31_t)0x41193b61, (q31_t)0x4113d25d, (q31_t)0x410e6931, (q31_t)0x4108ffdd, (q31_t)0x41039661, (q31_t)0x40fe2cbd, (q31_t)0x40f8c2f1, + (q31_t)0x40f358fc, (q31_t)0x40edeee0, (q31_t)0x40e8849b, (q31_t)0x40e31a2f, (q31_t)0x40ddaf9b, (q31_t)0x40d844de, (q31_t)0x40d2d9f9, (q31_t)0x40cd6eed, + (q31_t)0x40c803b8, (q31_t)0x40c2985c, (q31_t)0x40bd2cd8, (q31_t)0x40b7c12b, (q31_t)0x40b25557, (q31_t)0x40ace95b, (q31_t)0x40a77d37, (q31_t)0x40a210eb, + (q31_t)0x409ca477, (q31_t)0x409737dc, (q31_t)0x4091cb18, (q31_t)0x408c5e2d, (q31_t)0x4086f11a, (q31_t)0x408183df, (q31_t)0x407c167c, (q31_t)0x4076a8f1, + (q31_t)0x40713b3f, (q31_t)0x406bcd65, (q31_t)0x40665f63, (q31_t)0x4060f13a, (q31_t)0x405b82e9, (q31_t)0x40561470, (q31_t)0x4050a5cf, (q31_t)0x404b3707, + (q31_t)0x4045c817, (q31_t)0x404058ff, (q31_t)0x403ae9c0, (q31_t)0x40357a59, (q31_t)0x40300acb, (q31_t)0x402a9b15, (q31_t)0x40252b37, (q31_t)0x401fbb32, + (q31_t)0x401a4b05, (q31_t)0x4014dab1, (q31_t)0x400f6a35, (q31_t)0x4009f992, (q31_t)0x400488c7, (q31_t)0x3fff17d5, (q31_t)0x3ff9a6bb, (q31_t)0x3ff4357a, + (q31_t)0x3feec411, (q31_t)0x3fe95281, (q31_t)0x3fe3e0c9, (q31_t)0x3fde6eeb, (q31_t)0x3fd8fce4, (q31_t)0x3fd38ab6, (q31_t)0x3fce1861, (q31_t)0x3fc8a5e5, + (q31_t)0x3fc33341, (q31_t)0x3fbdc076, (q31_t)0x3fb84d83, (q31_t)0x3fb2da6a, (q31_t)0x3fad6729, (q31_t)0x3fa7f3c0, (q31_t)0x3fa28031, (q31_t)0x3f9d0c7a, + (q31_t)0x3f97989c, (q31_t)0x3f922496, (q31_t)0x3f8cb06a, (q31_t)0x3f873c16, (q31_t)0x3f81c79b, (q31_t)0x3f7c52f9, (q31_t)0x3f76de30, (q31_t)0x3f71693f, + (q31_t)0x3f6bf428, (q31_t)0x3f667ee9, (q31_t)0x3f610983, (q31_t)0x3f5b93f6, (q31_t)0x3f561e42, (q31_t)0x3f50a867, (q31_t)0x3f4b3265, (q31_t)0x3f45bc3c, + (q31_t)0x3f4045ec, (q31_t)0x3f3acf75, (q31_t)0x3f3558d7, (q31_t)0x3f2fe211, (q31_t)0x3f2a6b25, (q31_t)0x3f24f412, (q31_t)0x3f1f7cd8, (q31_t)0x3f1a0577, + (q31_t)0x3f148def, (q31_t)0x3f0f1640, (q31_t)0x3f099e6b, (q31_t)0x3f04266e, (q31_t)0x3efeae4a, (q31_t)0x3ef93600, (q31_t)0x3ef3bd8f, (q31_t)0x3eee44f7, + (q31_t)0x3ee8cc38, (q31_t)0x3ee35352, (q31_t)0x3eddda46, (q31_t)0x3ed86113, (q31_t)0x3ed2e7b9, (q31_t)0x3ecd6e38, (q31_t)0x3ec7f491, (q31_t)0x3ec27ac2, + (q31_t)0x3ebd00cd, (q31_t)0x3eb786b2, (q31_t)0x3eb20c6f, (q31_t)0x3eac9206, (q31_t)0x3ea71777, (q31_t)0x3ea19cc1, (q31_t)0x3e9c21e4, (q31_t)0x3e96a6e0, + (q31_t)0x3e912bb6, (q31_t)0x3e8bb065, (q31_t)0x3e8634ee, (q31_t)0x3e80b950, (q31_t)0x3e7b3d8c, (q31_t)0x3e75c1a1, (q31_t)0x3e70458f, (q31_t)0x3e6ac957, + (q31_t)0x3e654cf8, (q31_t)0x3e5fd073, (q31_t)0x3e5a53c8, (q31_t)0x3e54d6f6, (q31_t)0x3e4f59fe, (q31_t)0x3e49dcdf, (q31_t)0x3e445f99, (q31_t)0x3e3ee22e, + (q31_t)0x3e39649c, (q31_t)0x3e33e6e3, (q31_t)0x3e2e6904, (q31_t)0x3e28eaff, (q31_t)0x3e236cd4, (q31_t)0x3e1dee82, (q31_t)0x3e18700a, (q31_t)0x3e12f16b, + (q31_t)0x3e0d72a6, (q31_t)0x3e07f3bb, (q31_t)0x3e0274aa, (q31_t)0x3dfcf572, (q31_t)0x3df77615, (q31_t)0x3df1f691, (q31_t)0x3dec76e6, (q31_t)0x3de6f716, + (q31_t)0x3de1771f, (q31_t)0x3ddbf703, (q31_t)0x3dd676c0, (q31_t)0x3dd0f656, (q31_t)0x3dcb75c7, (q31_t)0x3dc5f512, (q31_t)0x3dc07436, (q31_t)0x3dbaf335, + (q31_t)0x3db5720d, (q31_t)0x3daff0c0, (q31_t)0x3daa6f4c, (q31_t)0x3da4edb2, (q31_t)0x3d9f6bf2, (q31_t)0x3d99ea0d, (q31_t)0x3d946801, (q31_t)0x3d8ee5cf, + (q31_t)0x3d896377, (q31_t)0x3d83e0f9, (q31_t)0x3d7e5e56, (q31_t)0x3d78db8c, (q31_t)0x3d73589d, (q31_t)0x3d6dd587, (q31_t)0x3d68524c, (q31_t)0x3d62ceeb, + (q31_t)0x3d5d4b64, (q31_t)0x3d57c7b7, (q31_t)0x3d5243e4, (q31_t)0x3d4cbfeb, (q31_t)0x3d473bcd, (q31_t)0x3d41b789, (q31_t)0x3d3c331f, (q31_t)0x3d36ae8f, + (q31_t)0x3d3129da, (q31_t)0x3d2ba4fe, (q31_t)0x3d261ffd, (q31_t)0x3d209ad7, (q31_t)0x3d1b158a, (q31_t)0x3d159018, (q31_t)0x3d100a80, (q31_t)0x3d0a84c3, + (q31_t)0x3d04fee0, (q31_t)0x3cff78d7, (q31_t)0x3cf9f2a9, (q31_t)0x3cf46c55, (q31_t)0x3ceee5db, (q31_t)0x3ce95f3c, (q31_t)0x3ce3d877, (q31_t)0x3cde518d, + (q31_t)0x3cd8ca7d, (q31_t)0x3cd34347, (q31_t)0x3ccdbbed, (q31_t)0x3cc8346c, (q31_t)0x3cc2acc6, (q31_t)0x3cbd24fb, (q31_t)0x3cb79d0a, (q31_t)0x3cb214f4, + (q31_t)0x3cac8cb8, (q31_t)0x3ca70457, (q31_t)0x3ca17bd0, (q31_t)0x3c9bf324, (q31_t)0x3c966a53, (q31_t)0x3c90e15c, (q31_t)0x3c8b5840, (q31_t)0x3c85cefe, + (q31_t)0x3c804598, (q31_t)0x3c7abc0c, (q31_t)0x3c75325a, (q31_t)0x3c6fa883, (q31_t)0x3c6a1e87, (q31_t)0x3c649466, (q31_t)0x3c5f0a20, (q31_t)0x3c597fb4, + (q31_t)0x3c53f523, (q31_t)0x3c4e6a6d, (q31_t)0x3c48df91, (q31_t)0x3c435491, (q31_t)0x3c3dc96b, (q31_t)0x3c383e20, (q31_t)0x3c32b2b0, (q31_t)0x3c2d271b, + (q31_t)0x3c279b61, (q31_t)0x3c220f81, (q31_t)0x3c1c837d, (q31_t)0x3c16f753, (q31_t)0x3c116b04, (q31_t)0x3c0bde91, (q31_t)0x3c0651f8, (q31_t)0x3c00c53a, + (q31_t)0x3bfb3857, (q31_t)0x3bf5ab50, (q31_t)0x3bf01e23, (q31_t)0x3bea90d1, (q31_t)0x3be5035a, (q31_t)0x3bdf75bf, (q31_t)0x3bd9e7fe, (q31_t)0x3bd45a19, + (q31_t)0x3bcecc0e, (q31_t)0x3bc93ddf, (q31_t)0x3bc3af8b, (q31_t)0x3bbe2112, (q31_t)0x3bb89274, (q31_t)0x3bb303b1, (q31_t)0x3bad74c9, (q31_t)0x3ba7e5bd, + (q31_t)0x3ba2568c, (q31_t)0x3b9cc736, (q31_t)0x3b9737bb, (q31_t)0x3b91a81c, (q31_t)0x3b8c1857, (q31_t)0x3b86886e, (q31_t)0x3b80f861, (q31_t)0x3b7b682e, + (q31_t)0x3b75d7d7, (q31_t)0x3b70475c, (q31_t)0x3b6ab6bb, (q31_t)0x3b6525f6, (q31_t)0x3b5f950c, (q31_t)0x3b5a03fe, (q31_t)0x3b5472cb, (q31_t)0x3b4ee173, + (q31_t)0x3b494ff7, (q31_t)0x3b43be57, (q31_t)0x3b3e2c91, (q31_t)0x3b389aa8, (q31_t)0x3b330899, (q31_t)0x3b2d7666, (q31_t)0x3b27e40f, (q31_t)0x3b225193, + (q31_t)0x3b1cbef3, (q31_t)0x3b172c2e, (q31_t)0x3b119945, (q31_t)0x3b0c0637, (q31_t)0x3b067305, (q31_t)0x3b00dfaf, (q31_t)0x3afb4c34, (q31_t)0x3af5b894, + (q31_t)0x3af024d1, (q31_t)0x3aea90e9, (q31_t)0x3ae4fcdc, (q31_t)0x3adf68ac, (q31_t)0x3ad9d457, (q31_t)0x3ad43fdd, (q31_t)0x3aceab40, (q31_t)0x3ac9167e, + (q31_t)0x3ac38198, (q31_t)0x3abdec8d, (q31_t)0x3ab8575f, (q31_t)0x3ab2c20c, (q31_t)0x3aad2c95, (q31_t)0x3aa796fa, (q31_t)0x3aa2013a, (q31_t)0x3a9c6b57, + (q31_t)0x3a96d54f, (q31_t)0x3a913f23, (q31_t)0x3a8ba8d3, (q31_t)0x3a86125f, (q31_t)0x3a807bc7, (q31_t)0x3a7ae50a, (q31_t)0x3a754e2a, (q31_t)0x3a6fb726, + (q31_t)0x3a6a1ffd, (q31_t)0x3a6488b1, (q31_t)0x3a5ef140, (q31_t)0x3a5959ab, (q31_t)0x3a53c1f3, (q31_t)0x3a4e2a16, (q31_t)0x3a489216, (q31_t)0x3a42f9f2, + (q31_t)0x3a3d61a9, (q31_t)0x3a37c93d, (q31_t)0x3a3230ad, (q31_t)0x3a2c97f9, (q31_t)0x3a26ff21, (q31_t)0x3a216625, (q31_t)0x3a1bcd05, (q31_t)0x3a1633c1, + (q31_t)0x3a109a5a, (q31_t)0x3a0b00cf, (q31_t)0x3a056720, (q31_t)0x39ffcd4d, (q31_t)0x39fa3356, (q31_t)0x39f4993c, (q31_t)0x39eefefe, (q31_t)0x39e9649c, + (q31_t)0x39e3ca17, (q31_t)0x39de2f6d, (q31_t)0x39d894a0, (q31_t)0x39d2f9b0, (q31_t)0x39cd5e9b, (q31_t)0x39c7c363, (q31_t)0x39c22808, (q31_t)0x39bc8c89, + (q31_t)0x39b6f0e6, (q31_t)0x39b1551f, (q31_t)0x39abb935, (q31_t)0x39a61d28, (q31_t)0x39a080f6, (q31_t)0x399ae4a2, (q31_t)0x39954829, (q31_t)0x398fab8e, + (q31_t)0x398a0ece, (q31_t)0x398471ec, (q31_t)0x397ed4e5, (q31_t)0x397937bc, (q31_t)0x39739a6e, (q31_t)0x396dfcfe, (q31_t)0x39685f6a, (q31_t)0x3962c1b2, + (q31_t)0x395d23d7, (q31_t)0x395785d9, (q31_t)0x3951e7b8, (q31_t)0x394c4973, (q31_t)0x3946ab0a, (q31_t)0x39410c7f, (q31_t)0x393b6dd0, (q31_t)0x3935cefd, + (q31_t)0x39303008, (q31_t)0x392a90ef, (q31_t)0x3924f1b3, (q31_t)0x391f5254, (q31_t)0x3919b2d1, (q31_t)0x3914132b, (q31_t)0x390e7362, (q31_t)0x3908d376, + (q31_t)0x39033367, (q31_t)0x38fd9334, (q31_t)0x38f7f2de, (q31_t)0x38f25266, (q31_t)0x38ecb1ca, (q31_t)0x38e7110a, (q31_t)0x38e17028, (q31_t)0x38dbcf23, + (q31_t)0x38d62dfb, (q31_t)0x38d08caf, (q31_t)0x38caeb41, (q31_t)0x38c549af, (q31_t)0x38bfa7fb, (q31_t)0x38ba0623, (q31_t)0x38b46429, (q31_t)0x38aec20b, + (q31_t)0x38a91fcb, (q31_t)0x38a37d67, (q31_t)0x389ddae1, (q31_t)0x38983838, (q31_t)0x3892956c, (q31_t)0x388cf27d, (q31_t)0x38874f6b, (q31_t)0x3881ac36, + (q31_t)0x387c08de, (q31_t)0x38766564, (q31_t)0x3870c1c6, (q31_t)0x386b1e06, (q31_t)0x38657a23, (q31_t)0x385fd61d, (q31_t)0x385a31f5, (q31_t)0x38548daa, + (q31_t)0x384ee93b, (q31_t)0x384944ab, (q31_t)0x38439ff7, (q31_t)0x383dfb21, (q31_t)0x38385628, (q31_t)0x3832b10d, (q31_t)0x382d0bce, (q31_t)0x3827666d, + (q31_t)0x3821c0ea, (q31_t)0x381c1b44, (q31_t)0x3816757b, (q31_t)0x3810cf90, (q31_t)0x380b2982, (q31_t)0x38058351, (q31_t)0x37ffdcfe, (q31_t)0x37fa3688, + (q31_t)0x37f48ff0, (q31_t)0x37eee936, (q31_t)0x37e94259, (q31_t)0x37e39b59, (q31_t)0x37ddf437, (q31_t)0x37d84cf2, (q31_t)0x37d2a58b, (q31_t)0x37ccfe02, + (q31_t)0x37c75656, (q31_t)0x37c1ae87, (q31_t)0x37bc0697, (q31_t)0x37b65e84, (q31_t)0x37b0b64e, (q31_t)0x37ab0df6, (q31_t)0x37a5657c, (q31_t)0x379fbce0, + (q31_t)0x379a1421, (q31_t)0x37946b40, (q31_t)0x378ec23d, (q31_t)0x37891917, (q31_t)0x37836fcf, (q31_t)0x377dc665, (q31_t)0x37781cd9, (q31_t)0x3772732a, + (q31_t)0x376cc959, (q31_t)0x37671f66, (q31_t)0x37617551, (q31_t)0x375bcb1a, (q31_t)0x375620c1, (q31_t)0x37507645, (q31_t)0x374acba7, (q31_t)0x374520e7, + (q31_t)0x373f7606, (q31_t)0x3739cb02, (q31_t)0x37341fdc, (q31_t)0x372e7493, (q31_t)0x3728c929, (q31_t)0x37231d9d, (q31_t)0x371d71ef, (q31_t)0x3717c61f, + (q31_t)0x37121a2d, (q31_t)0x370c6e19, (q31_t)0x3706c1e2, (q31_t)0x3701158a, (q31_t)0x36fb6910, (q31_t)0x36f5bc75, (q31_t)0x36f00fb7, (q31_t)0x36ea62d7, + (q31_t)0x36e4b5d6, (q31_t)0x36df08b2, (q31_t)0x36d95b6d, (q31_t)0x36d3ae06, (q31_t)0x36ce007d, (q31_t)0x36c852d2, (q31_t)0x36c2a506, (q31_t)0x36bcf718, + (q31_t)0x36b74908, (q31_t)0x36b19ad6, (q31_t)0x36abec82, (q31_t)0x36a63e0d, (q31_t)0x36a08f76, (q31_t)0x369ae0bd, (q31_t)0x369531e3, (q31_t)0x368f82e7, + (q31_t)0x3689d3c9, (q31_t)0x3684248a, (q31_t)0x367e7529, (q31_t)0x3678c5a7, (q31_t)0x36731602, (q31_t)0x366d663d, (q31_t)0x3667b655, (q31_t)0x3662064c, + (q31_t)0x365c5622, (q31_t)0x3656a5d6, (q31_t)0x3650f569, (q31_t)0x364b44da, (q31_t)0x36459429, (q31_t)0x363fe357, (q31_t)0x363a3264, (q31_t)0x3634814f, + (q31_t)0x362ed019, (q31_t)0x36291ec1, (q31_t)0x36236d48, (q31_t)0x361dbbad, (q31_t)0x361809f1, (q31_t)0x36125814, (q31_t)0x360ca615, (q31_t)0x3606f3f5, + (q31_t)0x360141b4, (q31_t)0x35fb8f52, (q31_t)0x35f5dcce, (q31_t)0x35f02a28, (q31_t)0x35ea7762, (q31_t)0x35e4c47a, (q31_t)0x35df1171, (q31_t)0x35d95e47, + (q31_t)0x35d3aafc, (q31_t)0x35cdf78f, (q31_t)0x35c84401, (q31_t)0x35c29052, (q31_t)0x35bcdc82, (q31_t)0x35b72891, (q31_t)0x35b1747e, (q31_t)0x35abc04b, + (q31_t)0x35a60bf6, (q31_t)0x35a05781, (q31_t)0x359aa2ea, (q31_t)0x3594ee32, (q31_t)0x358f3959, (q31_t)0x3589845f, (q31_t)0x3583cf44, (q31_t)0x357e1a08, + (q31_t)0x357864ab, (q31_t)0x3572af2d, (q31_t)0x356cf98e, (q31_t)0x356743ce, (q31_t)0x35618ded, (q31_t)0x355bd7eb, (q31_t)0x355621c9, (q31_t)0x35506b85, + (q31_t)0x354ab520, (q31_t)0x3544fe9b, (q31_t)0x353f47f5, (q31_t)0x3539912e, (q31_t)0x3533da46, (q31_t)0x352e233d, (q31_t)0x35286c14, (q31_t)0x3522b4c9, + (q31_t)0x351cfd5e, (q31_t)0x351745d2, (q31_t)0x35118e26, (q31_t)0x350bd658, (q31_t)0x35061e6a, (q31_t)0x3500665c, (q31_t)0x34faae2c, (q31_t)0x34f4f5dc, + (q31_t)0x34ef3d6b, (q31_t)0x34e984da, (q31_t)0x34e3cc28, (q31_t)0x34de1355, (q31_t)0x34d85a62, (q31_t)0x34d2a14e, (q31_t)0x34cce819, (q31_t)0x34c72ec4, + (q31_t)0x34c1754e, (q31_t)0x34bbbbb8, (q31_t)0x34b60202, (q31_t)0x34b0482a, (q31_t)0x34aa8e33, (q31_t)0x34a4d41a, (q31_t)0x349f19e2, (q31_t)0x34995f88, + (q31_t)0x3493a50f, (q31_t)0x348dea75, (q31_t)0x34882fba, (q31_t)0x348274e0, (q31_t)0x347cb9e4, (q31_t)0x3476fec9, (q31_t)0x3471438d, (q31_t)0x346b8830, + (q31_t)0x3465ccb4, (q31_t)0x34601117, (q31_t)0x345a5559, (q31_t)0x3454997c, (q31_t)0x344edd7e, (q31_t)0x34492160, (q31_t)0x34436521, (q31_t)0x343da8c3, + (q31_t)0x3437ec44, (q31_t)0x34322fa5, (q31_t)0x342c72e6, (q31_t)0x3426b606, (q31_t)0x3420f907, (q31_t)0x341b3be7, (q31_t)0x34157ea7, (q31_t)0x340fc147, + (q31_t)0x340a03c7, (q31_t)0x34044626, (q31_t)0x33fe8866, (q31_t)0x33f8ca86, (q31_t)0x33f30c85, (q31_t)0x33ed4e65, (q31_t)0x33e79024, (q31_t)0x33e1d1c4, + (q31_t)0x33dc1343, (q31_t)0x33d654a2, (q31_t)0x33d095e2, (q31_t)0x33cad701, (q31_t)0x33c51801, (q31_t)0x33bf58e1, (q31_t)0x33b999a0, (q31_t)0x33b3da40, + (q31_t)0x33ae1ac0, (q31_t)0x33a85b20, (q31_t)0x33a29b60, (q31_t)0x339cdb81, (q31_t)0x33971b81, (q31_t)0x33915b62, (q31_t)0x338b9b22, (q31_t)0x3385dac4, + (q31_t)0x33801a45, (q31_t)0x337a59a6, (q31_t)0x337498e8, (q31_t)0x336ed80a, (q31_t)0x3369170c, (q31_t)0x336355ef, (q31_t)0x335d94b2, (q31_t)0x3357d355, + (q31_t)0x335211d8, (q31_t)0x334c503c, (q31_t)0x33468e80, (q31_t)0x3340cca5, (q31_t)0x333b0aaa, (q31_t)0x3335488f, (q31_t)0x332f8655, (q31_t)0x3329c3fb, + (q31_t)0x33240182, (q31_t)0x331e3ee9, (q31_t)0x33187c31, (q31_t)0x3312b959, (q31_t)0x330cf661, (q31_t)0x3307334a, (q31_t)0x33017014, (q31_t)0x32fbacbe, + (q31_t)0x32f5e948, (q31_t)0x32f025b4, (q31_t)0x32ea61ff, (q31_t)0x32e49e2c, (q31_t)0x32deda39, (q31_t)0x32d91626, (q31_t)0x32d351f5, (q31_t)0x32cd8da4, + (q31_t)0x32c7c933, (q31_t)0x32c204a3, (q31_t)0x32bc3ff4, (q31_t)0x32b67b26, (q31_t)0x32b0b638, (q31_t)0x32aaf12b, (q31_t)0x32a52bff, (q31_t)0x329f66b4, + (q31_t)0x3299a149, (q31_t)0x3293dbbf, (q31_t)0x328e1616, (q31_t)0x3288504e, (q31_t)0x32828a67, (q31_t)0x327cc460, (q31_t)0x3276fe3a, (q31_t)0x327137f6, + (q31_t)0x326b7192, (q31_t)0x3265ab0f, (q31_t)0x325fe46c, (q31_t)0x325a1dab, (q31_t)0x325456cb, (q31_t)0x324e8fcc, (q31_t)0x3248c8ad, (q31_t)0x32430170, + (q31_t)0x323d3a14, (q31_t)0x32377298, (q31_t)0x3231aafe, (q31_t)0x322be345, (q31_t)0x32261b6c, (q31_t)0x32205375, (q31_t)0x321a8b5f, (q31_t)0x3214c32a, + (q31_t)0x320efad6, (q31_t)0x32093263, (q31_t)0x320369d2, (q31_t)0x31fda121, (q31_t)0x31f7d852, (q31_t)0x31f20f64, (q31_t)0x31ec4657, (q31_t)0x31e67d2b, + (q31_t)0x31e0b3e0, (q31_t)0x31daea77, (q31_t)0x31d520ef, (q31_t)0x31cf5748, (q31_t)0x31c98d83, (q31_t)0x31c3c39e, (q31_t)0x31bdf99b, (q31_t)0x31b82f7a, + (q31_t)0x31b2653a, (q31_t)0x31ac9adb, (q31_t)0x31a6d05d, (q31_t)0x31a105c1, (q31_t)0x319b3b06, (q31_t)0x3195702d, (q31_t)0x318fa535, (q31_t)0x3189da1e, + (q31_t)0x31840ee9, (q31_t)0x317e4395, (q31_t)0x31787823, (q31_t)0x3172ac92, (q31_t)0x316ce0e3, (q31_t)0x31671515, (q31_t)0x31614929, (q31_t)0x315b7d1e, + (q31_t)0x3155b0f5, (q31_t)0x314fe4ae, (q31_t)0x314a1848, (q31_t)0x31444bc3, (q31_t)0x313e7f21, (q31_t)0x3138b260, (q31_t)0x3132e580, (q31_t)0x312d1882, + (q31_t)0x31274b66, (q31_t)0x31217e2c, (q31_t)0x311bb0d3, (q31_t)0x3115e35c, (q31_t)0x311015c6, (q31_t)0x310a4813, (q31_t)0x31047a41, (q31_t)0x30feac51, + (q31_t)0x30f8de42, (q31_t)0x30f31016, (q31_t)0x30ed41cb, (q31_t)0x30e77362, (q31_t)0x30e1a4db, (q31_t)0x30dbd636, (q31_t)0x30d60772, (q31_t)0x30d03891, + (q31_t)0x30ca6991, (q31_t)0x30c49a74, (q31_t)0x30becb38, (q31_t)0x30b8fbde, (q31_t)0x30b32c66, (q31_t)0x30ad5cd0, (q31_t)0x30a78d1c, (q31_t)0x30a1bd4a, + (q31_t)0x309bed5a, (q31_t)0x30961d4c, (q31_t)0x30904d20, (q31_t)0x308a7cd6, (q31_t)0x3084ac6e, (q31_t)0x307edbe9, (q31_t)0x30790b45, (q31_t)0x30733a83, + (q31_t)0x306d69a4, (q31_t)0x306798a7, (q31_t)0x3061c78b, (q31_t)0x305bf652, (q31_t)0x305624fb, (q31_t)0x30505387, (q31_t)0x304a81f4, (q31_t)0x3044b044, + (q31_t)0x303ede76, (q31_t)0x30390c8a, (q31_t)0x30333a80, (q31_t)0x302d6859, (q31_t)0x30279614, (q31_t)0x3021c3b1, (q31_t)0x301bf131, (q31_t)0x30161e93, + (q31_t)0x30104bd7, (q31_t)0x300a78fe, (q31_t)0x3004a607, (q31_t)0x2ffed2f2, (q31_t)0x2ff8ffc0, (q31_t)0x2ff32c70, (q31_t)0x2fed5902, (q31_t)0x2fe78577, + (q31_t)0x2fe1b1cf, (q31_t)0x2fdbde09, (q31_t)0x2fd60a25, (q31_t)0x2fd03624, (q31_t)0x2fca6206, (q31_t)0x2fc48dc9, (q31_t)0x2fbeb970, (q31_t)0x2fb8e4f9, + (q31_t)0x2fb31064, (q31_t)0x2fad3bb3, (q31_t)0x2fa766e3, (q31_t)0x2fa191f7, (q31_t)0x2f9bbced, (q31_t)0x2f95e7c5, (q31_t)0x2f901280, (q31_t)0x2f8a3d1e, + (q31_t)0x2f84679f, (q31_t)0x2f7e9202, (q31_t)0x2f78bc48, (q31_t)0x2f72e671, (q31_t)0x2f6d107c, (q31_t)0x2f673a6a, (q31_t)0x2f61643b, (q31_t)0x2f5b8def, + (q31_t)0x2f55b785, (q31_t)0x2f4fe0ff, (q31_t)0x2f4a0a5b, (q31_t)0x2f44339a, (q31_t)0x2f3e5cbb, (q31_t)0x2f3885c0, (q31_t)0x2f32aea8, (q31_t)0x2f2cd772, + (q31_t)0x2f27001f, (q31_t)0x2f2128af, (q31_t)0x2f1b5122, (q31_t)0x2f157979, (q31_t)0x2f0fa1b2, (q31_t)0x2f09c9ce, (q31_t)0x2f03f1cd, (q31_t)0x2efe19ae, + (q31_t)0x2ef84173, (q31_t)0x2ef2691b, (q31_t)0x2eec90a7, (q31_t)0x2ee6b815, (q31_t)0x2ee0df66, (q31_t)0x2edb069a, (q31_t)0x2ed52db1, (q31_t)0x2ecf54ac, + (q31_t)0x2ec97b89, (q31_t)0x2ec3a24a, (q31_t)0x2ebdc8ee, (q31_t)0x2eb7ef75, (q31_t)0x2eb215df, (q31_t)0x2eac3c2d, (q31_t)0x2ea6625d, (q31_t)0x2ea08871, + (q31_t)0x2e9aae68, (q31_t)0x2e94d443, (q31_t)0x2e8efa00, (q31_t)0x2e891fa1, (q31_t)0x2e834525, (q31_t)0x2e7d6a8d, (q31_t)0x2e778fd8, (q31_t)0x2e71b506, + (q31_t)0x2e6bda17, (q31_t)0x2e65ff0c, (q31_t)0x2e6023e5, (q31_t)0x2e5a48a0, (q31_t)0x2e546d3f, (q31_t)0x2e4e91c2, (q31_t)0x2e48b628, (q31_t)0x2e42da71, + (q31_t)0x2e3cfe9e, (q31_t)0x2e3722ae, (q31_t)0x2e3146a2, (q31_t)0x2e2b6a79, (q31_t)0x2e258e34, (q31_t)0x2e1fb1d3, (q31_t)0x2e19d554, (q31_t)0x2e13f8ba, + (q31_t)0x2e0e1c03, (q31_t)0x2e083f30, (q31_t)0x2e026240, (q31_t)0x2dfc8534, (q31_t)0x2df6a80b, (q31_t)0x2df0cac6, (q31_t)0x2deaed65, (q31_t)0x2de50fe8, + (q31_t)0x2ddf324e, (q31_t)0x2dd95498, (q31_t)0x2dd376c5, (q31_t)0x2dcd98d7, (q31_t)0x2dc7bacc, (q31_t)0x2dc1dca4, (q31_t)0x2dbbfe61, (q31_t)0x2db62001, + (q31_t)0x2db04186, (q31_t)0x2daa62ee, (q31_t)0x2da4843a, (q31_t)0x2d9ea569, (q31_t)0x2d98c67d, (q31_t)0x2d92e774, (q31_t)0x2d8d084f, (q31_t)0x2d87290f, + (q31_t)0x2d8149b2, (q31_t)0x2d7b6a39, (q31_t)0x2d758aa4, (q31_t)0x2d6faaf3, (q31_t)0x2d69cb26, (q31_t)0x2d63eb3d, (q31_t)0x2d5e0b38, (q31_t)0x2d582b17, + (q31_t)0x2d524ada, (q31_t)0x2d4c6a81, (q31_t)0x2d468a0c, (q31_t)0x2d40a97b, (q31_t)0x2d3ac8ce, (q31_t)0x2d34e805, (q31_t)0x2d2f0721, (q31_t)0x2d292620, + (q31_t)0x2d234504, (q31_t)0x2d1d63cc, (q31_t)0x2d178278, (q31_t)0x2d11a108, (q31_t)0x2d0bbf7d, (q31_t)0x2d05ddd5, (q31_t)0x2cfffc12, (q31_t)0x2cfa1a33, + (q31_t)0x2cf43839, (q31_t)0x2cee5622, (q31_t)0x2ce873f0, (q31_t)0x2ce291a2, (q31_t)0x2cdcaf39, (q31_t)0x2cd6ccb4, (q31_t)0x2cd0ea13, (q31_t)0x2ccb0756, + (q31_t)0x2cc5247e, (q31_t)0x2cbf418b, (q31_t)0x2cb95e7b, (q31_t)0x2cb37b51, (q31_t)0x2cad980a, (q31_t)0x2ca7b4a8, (q31_t)0x2ca1d12a, (q31_t)0x2c9bed91, + (q31_t)0x2c9609dd, (q31_t)0x2c90260d, (q31_t)0x2c8a4221, (q31_t)0x2c845e1a, (q31_t)0x2c7e79f7, (q31_t)0x2c7895b9, (q31_t)0x2c72b160, (q31_t)0x2c6ccceb, + (q31_t)0x2c66e85b, (q31_t)0x2c6103af, (q31_t)0x2c5b1ee8, (q31_t)0x2c553a06, (q31_t)0x2c4f5508, (q31_t)0x2c496fef, (q31_t)0x2c438abb, (q31_t)0x2c3da56b, + (q31_t)0x2c37c000, (q31_t)0x2c31da7a, (q31_t)0x2c2bf4d8, (q31_t)0x2c260f1c, (q31_t)0x2c202944, (q31_t)0x2c1a4351, (q31_t)0x2c145d42, (q31_t)0x2c0e7719, + (q31_t)0x2c0890d4, (q31_t)0x2c02aa74, (q31_t)0x2bfcc3f9, (q31_t)0x2bf6dd63, (q31_t)0x2bf0f6b1, (q31_t)0x2beb0fe5, (q31_t)0x2be528fd, (q31_t)0x2bdf41fb, + (q31_t)0x2bd95add, (q31_t)0x2bd373a4, (q31_t)0x2bcd8c51, (q31_t)0x2bc7a4e2, (q31_t)0x2bc1bd58, (q31_t)0x2bbbd5b3, (q31_t)0x2bb5edf4, (q31_t)0x2bb00619, + (q31_t)0x2baa1e23, (q31_t)0x2ba43613, (q31_t)0x2b9e4de7, (q31_t)0x2b9865a1, (q31_t)0x2b927d3f, (q31_t)0x2b8c94c3, (q31_t)0x2b86ac2c, (q31_t)0x2b80c37a, + (q31_t)0x2b7adaae, (q31_t)0x2b74f1c6, (q31_t)0x2b6f08c4, (q31_t)0x2b691fa6, (q31_t)0x2b63366f, (q31_t)0x2b5d4d1c, (q31_t)0x2b5763ae, (q31_t)0x2b517a26, + (q31_t)0x2b4b9083, (q31_t)0x2b45a6c6, (q31_t)0x2b3fbced, (q31_t)0x2b39d2fa, (q31_t)0x2b33e8ed, (q31_t)0x2b2dfec5, (q31_t)0x2b281482, (q31_t)0x2b222a24, + (q31_t)0x2b1c3fac, (q31_t)0x2b165519, (q31_t)0x2b106a6c, (q31_t)0x2b0a7fa4, (q31_t)0x2b0494c2, (q31_t)0x2afea9c5, (q31_t)0x2af8bead, (q31_t)0x2af2d37b, + (q31_t)0x2aece82f, (q31_t)0x2ae6fcc8, (q31_t)0x2ae11146, (q31_t)0x2adb25aa, (q31_t)0x2ad539f4, (q31_t)0x2acf4e23, (q31_t)0x2ac96238, (q31_t)0x2ac37633, + (q31_t)0x2abd8a13, (q31_t)0x2ab79dd8, (q31_t)0x2ab1b184, (q31_t)0x2aabc515, (q31_t)0x2aa5d88b, (q31_t)0x2a9febe8, (q31_t)0x2a99ff2a, (q31_t)0x2a941252, + (q31_t)0x2a8e255f, (q31_t)0x2a883853, (q31_t)0x2a824b2c, (q31_t)0x2a7c5deb, (q31_t)0x2a76708f, (q31_t)0x2a70831a, (q31_t)0x2a6a958a, (q31_t)0x2a64a7e0, + (q31_t)0x2a5eba1c, (q31_t)0x2a58cc3e, (q31_t)0x2a52de46, (q31_t)0x2a4cf033, (q31_t)0x2a470207, (q31_t)0x2a4113c0, (q31_t)0x2a3b2560, (q31_t)0x2a3536e5, + (q31_t)0x2a2f4850, (q31_t)0x2a2959a1, (q31_t)0x2a236ad9, (q31_t)0x2a1d7bf6, (q31_t)0x2a178cf9, (q31_t)0x2a119de2, (q31_t)0x2a0baeb2, (q31_t)0x2a05bf67, + (q31_t)0x29ffd003, (q31_t)0x29f9e084, (q31_t)0x29f3f0ec, (q31_t)0x29ee013a, (q31_t)0x29e8116e, (q31_t)0x29e22188, (q31_t)0x29dc3188, (q31_t)0x29d6416f, + (q31_t)0x29d0513b, (q31_t)0x29ca60ee, (q31_t)0x29c47087, (q31_t)0x29be8007, (q31_t)0x29b88f6c, (q31_t)0x29b29eb8, (q31_t)0x29acadea, (q31_t)0x29a6bd02, + (q31_t)0x29a0cc01, (q31_t)0x299adae6, (q31_t)0x2994e9b1, (q31_t)0x298ef863, (q31_t)0x298906fb, (q31_t)0x2983157a, (q31_t)0x297d23df, (q31_t)0x2977322a, + (q31_t)0x2971405b, (q31_t)0x296b4e74, (q31_t)0x29655c72, (q31_t)0x295f6a57, (q31_t)0x29597823, (q31_t)0x295385d5, (q31_t)0x294d936d, (q31_t)0x2947a0ec, + (q31_t)0x2941ae52, (q31_t)0x293bbb9e, (q31_t)0x2935c8d1, (q31_t)0x292fd5ea, (q31_t)0x2929e2ea, (q31_t)0x2923efd0, (q31_t)0x291dfc9d, (q31_t)0x29180951, + (q31_t)0x291215eb, (q31_t)0x290c226c, (q31_t)0x29062ed4, (q31_t)0x29003b23, (q31_t)0x28fa4758, (q31_t)0x28f45374, (q31_t)0x28ee5f76, (q31_t)0x28e86b5f, + (q31_t)0x28e27730, (q31_t)0x28dc82e6, (q31_t)0x28d68e84, (q31_t)0x28d09a09, (q31_t)0x28caa574, (q31_t)0x28c4b0c6, (q31_t)0x28bebbff, (q31_t)0x28b8c71f, + (q31_t)0x28b2d226, (q31_t)0x28acdd13, (q31_t)0x28a6e7e8, (q31_t)0x28a0f2a3, (q31_t)0x289afd46, (q31_t)0x289507cf, (q31_t)0x288f123f, (q31_t)0x28891c97, + (q31_t)0x288326d5, (q31_t)0x287d30fa, (q31_t)0x28773b07, (q31_t)0x287144fa, (q31_t)0x286b4ed5, (q31_t)0x28655896, (q31_t)0x285f623f, (q31_t)0x28596bce, + (q31_t)0x28537545, (q31_t)0x284d7ea3, (q31_t)0x284787e8, (q31_t)0x28419114, (q31_t)0x283b9a28, (q31_t)0x2835a322, (q31_t)0x282fac04, (q31_t)0x2829b4cd, + (q31_t)0x2823bd7d, (q31_t)0x281dc615, (q31_t)0x2817ce93, (q31_t)0x2811d6f9, (q31_t)0x280bdf46, (q31_t)0x2805e77b, (q31_t)0x27ffef97, (q31_t)0x27f9f79a, + (q31_t)0x27f3ff85, (q31_t)0x27ee0756, (q31_t)0x27e80f10, (q31_t)0x27e216b0, (q31_t)0x27dc1e38, (q31_t)0x27d625a8, (q31_t)0x27d02cff, (q31_t)0x27ca343d, + (q31_t)0x27c43b63, (q31_t)0x27be4270, (q31_t)0x27b84965, (q31_t)0x27b25041, (q31_t)0x27ac5705, (q31_t)0x27a65db0, (q31_t)0x27a06443, (q31_t)0x279a6abd, + (q31_t)0x2794711f, (q31_t)0x278e7768, (q31_t)0x27887d99, (q31_t)0x278283b2, (q31_t)0x277c89b3, (q31_t)0x27768f9b, (q31_t)0x2770956a, (q31_t)0x276a9b21, + (q31_t)0x2764a0c0, (q31_t)0x275ea647, (q31_t)0x2758abb6, (q31_t)0x2752b10c, (q31_t)0x274cb64a, (q31_t)0x2746bb6f, (q31_t)0x2740c07d, (q31_t)0x273ac572, + (q31_t)0x2734ca4f, (q31_t)0x272ecf14, (q31_t)0x2728d3c0, (q31_t)0x2722d855, (q31_t)0x271cdcd1, (q31_t)0x2716e136, (q31_t)0x2710e582, (q31_t)0x270ae9b6, + (q31_t)0x2704edd2, (q31_t)0x26fef1d5, (q31_t)0x26f8f5c1, (q31_t)0x26f2f995, (q31_t)0x26ecfd51, (q31_t)0x26e700f5, (q31_t)0x26e10480, (q31_t)0x26db07f4, + (q31_t)0x26d50b50, (q31_t)0x26cf0e94, (q31_t)0x26c911c0, (q31_t)0x26c314d4, (q31_t)0x26bd17d0, (q31_t)0x26b71ab4, (q31_t)0x26b11d80, (q31_t)0x26ab2034, + (q31_t)0x26a522d1, (q31_t)0x269f2556, (q31_t)0x269927c3, (q31_t)0x26932a18, (q31_t)0x268d2c55, (q31_t)0x26872e7b, (q31_t)0x26813088, (q31_t)0x267b327e, + (q31_t)0x2675345d, (q31_t)0x266f3623, (q31_t)0x266937d2, (q31_t)0x26633969, (q31_t)0x265d3ae9, (q31_t)0x26573c50, (q31_t)0x26513da1, (q31_t)0x264b3ed9, + (q31_t)0x26453ffa, (q31_t)0x263f4103, (q31_t)0x263941f5, (q31_t)0x263342cf, (q31_t)0x262d4392, (q31_t)0x2627443d, (q31_t)0x262144d0, (q31_t)0x261b454c, + (q31_t)0x261545b0, (q31_t)0x260f45fd, (q31_t)0x26094633, (q31_t)0x26034651, (q31_t)0x25fd4657, (q31_t)0x25f74646, (q31_t)0x25f1461e, (q31_t)0x25eb45de, + (q31_t)0x25e54587, (q31_t)0x25df4519, (q31_t)0x25d94493, (q31_t)0x25d343f6, (q31_t)0x25cd4341, (q31_t)0x25c74276, (q31_t)0x25c14192, (q31_t)0x25bb4098, + (q31_t)0x25b53f86, (q31_t)0x25af3e5d, (q31_t)0x25a93d1d, (q31_t)0x25a33bc6, (q31_t)0x259d3a57, (q31_t)0x259738d1, (q31_t)0x25913734, (q31_t)0x258b3580, + (q31_t)0x258533b5, (q31_t)0x257f31d2, (q31_t)0x25792fd8, (q31_t)0x25732dc8, (q31_t)0x256d2ba0, (q31_t)0x25672961, (q31_t)0x2561270b, (q31_t)0x255b249e, + (q31_t)0x2555221a, (q31_t)0x254f1f7e, (q31_t)0x25491ccc, (q31_t)0x25431a03, (q31_t)0x253d1723, (q31_t)0x2537142c, (q31_t)0x2531111e, (q31_t)0x252b0df9, + (q31_t)0x25250abd, (q31_t)0x251f076a, (q31_t)0x25190400, (q31_t)0x25130080, (q31_t)0x250cfce8, (q31_t)0x2506f93a, (q31_t)0x2500f574, (q31_t)0x24faf198, + (q31_t)0x24f4eda6, (q31_t)0x24eee99c, (q31_t)0x24e8e57c, (q31_t)0x24e2e144, (q31_t)0x24dcdcf6, (q31_t)0x24d6d892, (q31_t)0x24d0d416, (q31_t)0x24cacf84, + (q31_t)0x24c4cadb, (q31_t)0x24bec61c, (q31_t)0x24b8c146, (q31_t)0x24b2bc59, (q31_t)0x24acb756, (q31_t)0x24a6b23b, (q31_t)0x24a0ad0b, (q31_t)0x249aa7c4, + (q31_t)0x2494a266, (q31_t)0x248e9cf1, (q31_t)0x24889766, (q31_t)0x248291c5, (q31_t)0x247c8c0d, (q31_t)0x2476863e, (q31_t)0x24708059, (q31_t)0x246a7a5e, + (q31_t)0x2464744c, (q31_t)0x245e6e23, (q31_t)0x245867e4, (q31_t)0x2452618f, (q31_t)0x244c5b24, (q31_t)0x244654a1, (q31_t)0x24404e09, (q31_t)0x243a475a, + (q31_t)0x24344095, (q31_t)0x242e39ba, (q31_t)0x242832c8, (q31_t)0x24222bc0, (q31_t)0x241c24a1, (q31_t)0x24161d6d, (q31_t)0x24101622, (q31_t)0x240a0ec1, + (q31_t)0x24040749, (q31_t)0x23fdffbc, (q31_t)0x23f7f818, (q31_t)0x23f1f05e, (q31_t)0x23ebe88e, (q31_t)0x23e5e0a7, (q31_t)0x23dfd8ab, (q31_t)0x23d9d098, + (q31_t)0x23d3c86f, (q31_t)0x23cdc031, (q31_t)0x23c7b7dc, (q31_t)0x23c1af71, (q31_t)0x23bba6f0, (q31_t)0x23b59e59, (q31_t)0x23af95ac, (q31_t)0x23a98ce8, + (q31_t)0x23a3840f, (q31_t)0x239d7b20, (q31_t)0x2397721b, (q31_t)0x23916900, (q31_t)0x238b5fcf, (q31_t)0x23855688, (q31_t)0x237f4d2b, (q31_t)0x237943b9, + (q31_t)0x23733a30, (q31_t)0x236d3092, (q31_t)0x236726dd, (q31_t)0x23611d13, (q31_t)0x235b1333, (q31_t)0x2355093e, (q31_t)0x234eff32, (q31_t)0x2348f511, + (q31_t)0x2342eada, (q31_t)0x233ce08d, (q31_t)0x2336d62a, (q31_t)0x2330cbb2, (q31_t)0x232ac124, (q31_t)0x2324b680, (q31_t)0x231eabc7, (q31_t)0x2318a0f8, + (q31_t)0x23129613, (q31_t)0x230c8b19, (q31_t)0x23068009, (q31_t)0x230074e3, (q31_t)0x22fa69a8, (q31_t)0x22f45e57, (q31_t)0x22ee52f1, (q31_t)0x22e84775, + (q31_t)0x22e23be4, (q31_t)0x22dc303d, (q31_t)0x22d62480, (q31_t)0x22d018ae, (q31_t)0x22ca0cc7, (q31_t)0x22c400ca, (q31_t)0x22bdf4b8, (q31_t)0x22b7e890, + (q31_t)0x22b1dc53, (q31_t)0x22abd001, (q31_t)0x22a5c399, (q31_t)0x229fb71b, (q31_t)0x2299aa89, (q31_t)0x22939de1, (q31_t)0x228d9123, (q31_t)0x22878451, + (q31_t)0x22817769, (q31_t)0x227b6a6c, (q31_t)0x22755d59, (q31_t)0x226f5032, (q31_t)0x226942f5, (q31_t)0x226335a2, (q31_t)0x225d283b, (q31_t)0x22571abe, + (q31_t)0x22510d2d, (q31_t)0x224aff86, (q31_t)0x2244f1c9, (q31_t)0x223ee3f8, (q31_t)0x2238d612, (q31_t)0x2232c816, (q31_t)0x222cba06, (q31_t)0x2226abe0, + (q31_t)0x22209da5, (q31_t)0x221a8f56, (q31_t)0x221480f1, (q31_t)0x220e7277, (q31_t)0x220863e8, (q31_t)0x22025544, (q31_t)0x21fc468b, (q31_t)0x21f637be, + (q31_t)0x21f028db, (q31_t)0x21ea19e3, (q31_t)0x21e40ad7, (q31_t)0x21ddfbb5, (q31_t)0x21d7ec7f, (q31_t)0x21d1dd34, (q31_t)0x21cbcdd3, (q31_t)0x21c5be5e, + (q31_t)0x21bfaed5, (q31_t)0x21b99f36, (q31_t)0x21b38f83, (q31_t)0x21ad7fba, (q31_t)0x21a76fdd, (q31_t)0x21a15fec, (q31_t)0x219b4fe5, (q31_t)0x21953fca, + (q31_t)0x218f2f9a, (q31_t)0x21891f55, (q31_t)0x21830efc, (q31_t)0x217cfe8e, (q31_t)0x2176ee0b, (q31_t)0x2170dd74, (q31_t)0x216accc8, (q31_t)0x2164bc08, + (q31_t)0x215eab33, (q31_t)0x21589a49, (q31_t)0x2152894b, (q31_t)0x214c7838, (q31_t)0x21466710, (q31_t)0x214055d4, (q31_t)0x213a4484, (q31_t)0x2134331f, + (q31_t)0x212e21a6, (q31_t)0x21281018, (q31_t)0x2121fe76, (q31_t)0x211becbf, (q31_t)0x2115daf4, (q31_t)0x210fc914, (q31_t)0x2109b720, (q31_t)0x2103a518, + (q31_t)0x20fd92fb, (q31_t)0x20f780ca, (q31_t)0x20f16e84, (q31_t)0x20eb5c2b, (q31_t)0x20e549bd, (q31_t)0x20df373a, (q31_t)0x20d924a4, (q31_t)0x20d311f9, + (q31_t)0x20ccff3a, (q31_t)0x20c6ec66, (q31_t)0x20c0d97f, (q31_t)0x20bac683, (q31_t)0x20b4b373, (q31_t)0x20aea04f, (q31_t)0x20a88d17, (q31_t)0x20a279ca, + (q31_t)0x209c666a, (q31_t)0x209652f5, (q31_t)0x20903f6c, (q31_t)0x208a2bcf, (q31_t)0x2084181e, (q31_t)0x207e0459, (q31_t)0x2077f080, (q31_t)0x2071dc93, + (q31_t)0x206bc892, (q31_t)0x2065b47d, (q31_t)0x205fa054, (q31_t)0x20598c17, (q31_t)0x205377c6, (q31_t)0x204d6361, (q31_t)0x20474ee8, (q31_t)0x20413a5b, + (q31_t)0x203b25bb, (q31_t)0x20351106, (q31_t)0x202efc3e, (q31_t)0x2028e761, (q31_t)0x2022d271, (q31_t)0x201cbd6d, (q31_t)0x2016a856, (q31_t)0x2010932a, + (q31_t)0x200a7deb, (q31_t)0x20046898, (q31_t)0x1ffe5331, (q31_t)0x1ff83db6, (q31_t)0x1ff22828, (q31_t)0x1fec1286, (q31_t)0x1fe5fcd0, (q31_t)0x1fdfe707, + (q31_t)0x1fd9d12a, (q31_t)0x1fd3bb39, (q31_t)0x1fcda535, (q31_t)0x1fc78f1d, (q31_t)0x1fc178f1, (q31_t)0x1fbb62b2, (q31_t)0x1fb54c60, (q31_t)0x1faf35f9, + (q31_t)0x1fa91f80, (q31_t)0x1fa308f2, (q31_t)0x1f9cf252, (q31_t)0x1f96db9d, (q31_t)0x1f90c4d5, (q31_t)0x1f8aadfa, (q31_t)0x1f84970b, (q31_t)0x1f7e8009, + (q31_t)0x1f7868f4, (q31_t)0x1f7251ca, (q31_t)0x1f6c3a8e, (q31_t)0x1f66233e, (q31_t)0x1f600bdb, (q31_t)0x1f59f465, (q31_t)0x1f53dcdb, (q31_t)0x1f4dc53d, + (q31_t)0x1f47ad8d, (q31_t)0x1f4195c9, (q31_t)0x1f3b7df2, (q31_t)0x1f356608, (q31_t)0x1f2f4e0a, (q31_t)0x1f2935f9, (q31_t)0x1f231dd5, (q31_t)0x1f1d059e, + (q31_t)0x1f16ed54, (q31_t)0x1f10d4f6, (q31_t)0x1f0abc85, (q31_t)0x1f04a401, (q31_t)0x1efe8b6a, (q31_t)0x1ef872c0, (q31_t)0x1ef25a03, (q31_t)0x1eec4132, + (q31_t)0x1ee6284f, (q31_t)0x1ee00f58, (q31_t)0x1ed9f64f, (q31_t)0x1ed3dd32, (q31_t)0x1ecdc402, (q31_t)0x1ec7aac0, (q31_t)0x1ec1916a, (q31_t)0x1ebb7802, + (q31_t)0x1eb55e86, (q31_t)0x1eaf44f8, (q31_t)0x1ea92b56, (q31_t)0x1ea311a2, (q31_t)0x1e9cf7db, (q31_t)0x1e96de01, (q31_t)0x1e90c414, (q31_t)0x1e8aaa14, + (q31_t)0x1e849001, (q31_t)0x1e7e75dc, (q31_t)0x1e785ba3, (q31_t)0x1e724158, (q31_t)0x1e6c26fa, (q31_t)0x1e660c8a, (q31_t)0x1e5ff206, (q31_t)0x1e59d770, + (q31_t)0x1e53bcc7, (q31_t)0x1e4da20c, (q31_t)0x1e47873d, (q31_t)0x1e416c5d, (q31_t)0x1e3b5169, (q31_t)0x1e353663, (q31_t)0x1e2f1b4a, (q31_t)0x1e29001e, + (q31_t)0x1e22e4e0, (q31_t)0x1e1cc990, (q31_t)0x1e16ae2c, (q31_t)0x1e1092b6, (q31_t)0x1e0a772e, (q31_t)0x1e045b93, (q31_t)0x1dfe3fe6, (q31_t)0x1df82426, + (q31_t)0x1df20853, (q31_t)0x1debec6f, (q31_t)0x1de5d077, (q31_t)0x1ddfb46e, (q31_t)0x1dd99851, (q31_t)0x1dd37c23, (q31_t)0x1dcd5fe2, (q31_t)0x1dc7438e, + (q31_t)0x1dc12729, (q31_t)0x1dbb0ab0, (q31_t)0x1db4ee26, (q31_t)0x1daed189, (q31_t)0x1da8b4da, (q31_t)0x1da29819, (q31_t)0x1d9c7b45, (q31_t)0x1d965e5f, + (q31_t)0x1d904167, (q31_t)0x1d8a245c, (q31_t)0x1d840740, (q31_t)0x1d7dea11, (q31_t)0x1d77ccd0, (q31_t)0x1d71af7d, (q31_t)0x1d6b9217, (q31_t)0x1d6574a0, + (q31_t)0x1d5f5716, (q31_t)0x1d59397a, (q31_t)0x1d531bcc, (q31_t)0x1d4cfe0d, (q31_t)0x1d46e03a, (q31_t)0x1d40c256, (q31_t)0x1d3aa460, (q31_t)0x1d348658, + (q31_t)0x1d2e683e, (q31_t)0x1d284a12, (q31_t)0x1d222bd3, (q31_t)0x1d1c0d83, (q31_t)0x1d15ef21, (q31_t)0x1d0fd0ad, (q31_t)0x1d09b227, (q31_t)0x1d03938f, + (q31_t)0x1cfd74e5, (q31_t)0x1cf7562a, (q31_t)0x1cf1375c, (q31_t)0x1ceb187d, (q31_t)0x1ce4f98c, (q31_t)0x1cdeda89, (q31_t)0x1cd8bb74, (q31_t)0x1cd29c4d, + (q31_t)0x1ccc7d15, (q31_t)0x1cc65dca, (q31_t)0x1cc03e6e, (q31_t)0x1cba1f01, (q31_t)0x1cb3ff81, (q31_t)0x1caddff0, (q31_t)0x1ca7c04d, (q31_t)0x1ca1a099, + (q31_t)0x1c9b80d3, (q31_t)0x1c9560fb, (q31_t)0x1c8f4112, (q31_t)0x1c892117, (q31_t)0x1c83010a, (q31_t)0x1c7ce0ec, (q31_t)0x1c76c0bc, (q31_t)0x1c70a07b, + (q31_t)0x1c6a8028, (q31_t)0x1c645fc3, (q31_t)0x1c5e3f4d, (q31_t)0x1c581ec6, (q31_t)0x1c51fe2d, (q31_t)0x1c4bdd83, (q31_t)0x1c45bcc7, (q31_t)0x1c3f9bf9, + (q31_t)0x1c397b1b, (q31_t)0x1c335a2b, (q31_t)0x1c2d3929, (q31_t)0x1c271816, (q31_t)0x1c20f6f2, (q31_t)0x1c1ad5bc, (q31_t)0x1c14b475, (q31_t)0x1c0e931d, + (q31_t)0x1c0871b4, (q31_t)0x1c025039, (q31_t)0x1bfc2ead, (q31_t)0x1bf60d0f, (q31_t)0x1befeb60, (q31_t)0x1be9c9a1, (q31_t)0x1be3a7cf, (q31_t)0x1bdd85ed, + (q31_t)0x1bd763fa, (q31_t)0x1bd141f5, (q31_t)0x1bcb1fdf, (q31_t)0x1bc4fdb8, (q31_t)0x1bbedb80, (q31_t)0x1bb8b937, (q31_t)0x1bb296dc, (q31_t)0x1bac7471, + (q31_t)0x1ba651f5, (q31_t)0x1ba02f67, (q31_t)0x1b9a0cc8, (q31_t)0x1b93ea19, (q31_t)0x1b8dc758, (q31_t)0x1b87a487, (q31_t)0x1b8181a4, (q31_t)0x1b7b5eb0, + (q31_t)0x1b753bac, (q31_t)0x1b6f1897, (q31_t)0x1b68f570, (q31_t)0x1b62d239, (q31_t)0x1b5caef1, (q31_t)0x1b568b98, (q31_t)0x1b50682e, (q31_t)0x1b4a44b3, + (q31_t)0x1b442127, (q31_t)0x1b3dfd8b, (q31_t)0x1b37d9de, (q31_t)0x1b31b620, (q31_t)0x1b2b9251, (q31_t)0x1b256e71, (q31_t)0x1b1f4a81, (q31_t)0x1b192680, + (q31_t)0x1b13026e, (q31_t)0x1b0cde4c, (q31_t)0x1b06ba19, (q31_t)0x1b0095d5, (q31_t)0x1afa7180, (q31_t)0x1af44d1b, (q31_t)0x1aee28a6, (q31_t)0x1ae8041f, + (q31_t)0x1ae1df88, (q31_t)0x1adbbae1, (q31_t)0x1ad59629, (q31_t)0x1acf7160, (q31_t)0x1ac94c87, (q31_t)0x1ac3279d, (q31_t)0x1abd02a3, (q31_t)0x1ab6dd98, + (q31_t)0x1ab0b87d, (q31_t)0x1aaa9352, (q31_t)0x1aa46e16, (q31_t)0x1a9e48c9, (q31_t)0x1a98236c, (q31_t)0x1a91fdff, (q31_t)0x1a8bd881, (q31_t)0x1a85b2f3, + (q31_t)0x1a7f8d54, (q31_t)0x1a7967a6, (q31_t)0x1a7341e6, (q31_t)0x1a6d1c17, (q31_t)0x1a66f637, (q31_t)0x1a60d047, (q31_t)0x1a5aaa47, (q31_t)0x1a548436, + (q31_t)0x1a4e5e15, (q31_t)0x1a4837e4, (q31_t)0x1a4211a3, (q31_t)0x1a3beb52, (q31_t)0x1a35c4f0, (q31_t)0x1a2f9e7e, (q31_t)0x1a2977fc, (q31_t)0x1a23516a, + (q31_t)0x1a1d2ac8, (q31_t)0x1a170416, (q31_t)0x1a10dd53, (q31_t)0x1a0ab681, (q31_t)0x1a048f9e, (q31_t)0x19fe68ac, (q31_t)0x19f841a9, (q31_t)0x19f21a96, + (q31_t)0x19ebf374, (q31_t)0x19e5cc41, (q31_t)0x19dfa4fe, (q31_t)0x19d97dac, (q31_t)0x19d35649, (q31_t)0x19cd2ed7, (q31_t)0x19c70754, (q31_t)0x19c0dfc2, + (q31_t)0x19bab820, (q31_t)0x19b4906e, (q31_t)0x19ae68ac, (q31_t)0x19a840da, (q31_t)0x19a218f9, (q31_t)0x199bf107, (q31_t)0x1995c906, (q31_t)0x198fa0f5, + (q31_t)0x198978d4, (q31_t)0x198350a4, (q31_t)0x197d2864, (q31_t)0x19770014, (q31_t)0x1970d7b4, (q31_t)0x196aaf45, (q31_t)0x196486c6, (q31_t)0x195e5e37, + (q31_t)0x19583599, (q31_t)0x19520ceb, (q31_t)0x194be42d, (q31_t)0x1945bb60, (q31_t)0x193f9283, (q31_t)0x19396997, (q31_t)0x1933409b, (q31_t)0x192d178f, + (q31_t)0x1926ee74, (q31_t)0x1920c54a, (q31_t)0x191a9c10, (q31_t)0x191472c6, (q31_t)0x190e496d, (q31_t)0x19082005, (q31_t)0x1901f68d, (q31_t)0x18fbcd06, + (q31_t)0x18f5a36f, (q31_t)0x18ef79c9, (q31_t)0x18e95014, (q31_t)0x18e3264f, (q31_t)0x18dcfc7b, (q31_t)0x18d6d297, (q31_t)0x18d0a8a4, (q31_t)0x18ca7ea2, + (q31_t)0x18c45491, (q31_t)0x18be2a70, (q31_t)0x18b80040, (q31_t)0x18b1d601, (q31_t)0x18ababb2, (q31_t)0x18a58154, (q31_t)0x189f56e8, (q31_t)0x18992c6b, + (q31_t)0x189301e0, (q31_t)0x188cd746, (q31_t)0x1886ac9c, (q31_t)0x188081e4, (q31_t)0x187a571c, (q31_t)0x18742c45, (q31_t)0x186e015f, (q31_t)0x1867d66a, + (q31_t)0x1861ab66, (q31_t)0x185b8053, (q31_t)0x18555530, (q31_t)0x184f29ff, (q31_t)0x1848febf, (q31_t)0x1842d370, (q31_t)0x183ca812, (q31_t)0x18367ca5, + (q31_t)0x18305129, (q31_t)0x182a259e, (q31_t)0x1823fa04, (q31_t)0x181dce5b, (q31_t)0x1817a2a4, (q31_t)0x181176dd, (q31_t)0x180b4b08, (q31_t)0x18051f24, + (q31_t)0x17fef331, (q31_t)0x17f8c72f, (q31_t)0x17f29b1e, (q31_t)0x17ec6eff, (q31_t)0x17e642d1, (q31_t)0x17e01694, (q31_t)0x17d9ea49, (q31_t)0x17d3bdee, + (q31_t)0x17cd9186, (q31_t)0x17c7650e, (q31_t)0x17c13888, (q31_t)0x17bb0bf3, (q31_t)0x17b4df4f, (q31_t)0x17aeb29d, (q31_t)0x17a885dc, (q31_t)0x17a2590d, + (q31_t)0x179c2c2f, (q31_t)0x1795ff42, (q31_t)0x178fd247, (q31_t)0x1789a53d, (q31_t)0x17837825, (q31_t)0x177d4afe, (q31_t)0x17771dc9, (q31_t)0x1770f086, + (q31_t)0x176ac333, (q31_t)0x176495d3, (q31_t)0x175e6864, (q31_t)0x17583ae7, (q31_t)0x17520d5b, (q31_t)0x174bdfc1, (q31_t)0x1745b218, (q31_t)0x173f8461, + (q31_t)0x1739569c, (q31_t)0x173328c8, (q31_t)0x172cfae6, (q31_t)0x1726ccf6, (q31_t)0x17209ef8, (q31_t)0x171a70eb, (q31_t)0x171442d0, (q31_t)0x170e14a7, + (q31_t)0x1707e670, (q31_t)0x1701b82a, (q31_t)0x16fb89d6, (q31_t)0x16f55b74, (q31_t)0x16ef2d04, (q31_t)0x16e8fe86, (q31_t)0x16e2cff9, (q31_t)0x16dca15f, + (q31_t)0x16d672b6, (q31_t)0x16d043ff, (q31_t)0x16ca153a, (q31_t)0x16c3e667, (q31_t)0x16bdb787, (q31_t)0x16b78898, (q31_t)0x16b1599b, (q31_t)0x16ab2a90, + (q31_t)0x16a4fb77, (q31_t)0x169ecc50, (q31_t)0x16989d1b, (q31_t)0x16926dd8, (q31_t)0x168c3e87, (q31_t)0x16860f29, (q31_t)0x167fdfbc, (q31_t)0x1679b042, + (q31_t)0x167380ba, (q31_t)0x166d5123, (q31_t)0x1667217f, (q31_t)0x1660f1ce, (q31_t)0x165ac20e, (q31_t)0x16549241, (q31_t)0x164e6266, (q31_t)0x1648327d, + (q31_t)0x16420286, (q31_t)0x163bd282, (q31_t)0x1635a270, (q31_t)0x162f7250, (q31_t)0x16294222, (q31_t)0x162311e7, (q31_t)0x161ce19e, (q31_t)0x1616b148, + (q31_t)0x161080e4, (q31_t)0x160a5072, (q31_t)0x16041ff3, (q31_t)0x15fdef66, (q31_t)0x15f7becc, (q31_t)0x15f18e24, (q31_t)0x15eb5d6e, (q31_t)0x15e52cab, + (q31_t)0x15defbdb, (q31_t)0x15d8cafd, (q31_t)0x15d29a11, (q31_t)0x15cc6918, (q31_t)0x15c63812, (q31_t)0x15c006fe, (q31_t)0x15b9d5dd, (q31_t)0x15b3a4ae, + (q31_t)0x15ad7372, (q31_t)0x15a74228, (q31_t)0x15a110d2, (q31_t)0x159adf6e, (q31_t)0x1594adfc, (q31_t)0x158e7c7d, (q31_t)0x15884af1, (q31_t)0x15821958, + (q31_t)0x157be7b1, (q31_t)0x1575b5fe, (q31_t)0x156f843c, (q31_t)0x1569526e, (q31_t)0x15632093, (q31_t)0x155ceeaa, (q31_t)0x1556bcb4, (q31_t)0x15508ab1, + (q31_t)0x154a58a1, (q31_t)0x15442683, (q31_t)0x153df459, (q31_t)0x1537c221, (q31_t)0x15318fdd, (q31_t)0x152b5d8b, (q31_t)0x15252b2c, (q31_t)0x151ef8c0, + (q31_t)0x1518c648, (q31_t)0x151293c2, (q31_t)0x150c612f, (q31_t)0x15062e8f, (q31_t)0x14fffbe2, (q31_t)0x14f9c928, (q31_t)0x14f39662, (q31_t)0x14ed638e, + (q31_t)0x14e730ae, (q31_t)0x14e0fdc0, (q31_t)0x14dacac6, (q31_t)0x14d497bf, (q31_t)0x14ce64ab, (q31_t)0x14c8318a, (q31_t)0x14c1fe5c, (q31_t)0x14bbcb22, + (q31_t)0x14b597da, (q31_t)0x14af6486, (q31_t)0x14a93125, (q31_t)0x14a2fdb8, (q31_t)0x149cca3e, (q31_t)0x149696b7, (q31_t)0x14906323, (q31_t)0x148a2f82, + (q31_t)0x1483fbd5, (q31_t)0x147dc81c, (q31_t)0x14779455, (q31_t)0x14716082, (q31_t)0x146b2ca3, (q31_t)0x1464f8b7, (q31_t)0x145ec4be, (q31_t)0x145890b9, + (q31_t)0x14525ca7, (q31_t)0x144c2888, (q31_t)0x1445f45d, (q31_t)0x143fc026, (q31_t)0x14398be2, (q31_t)0x14335792, (q31_t)0x142d2335, (q31_t)0x1426eecb, + (q31_t)0x1420ba56, (q31_t)0x141a85d3, (q31_t)0x14145145, (q31_t)0x140e1caa, (q31_t)0x1407e803, (q31_t)0x1401b34f, (q31_t)0x13fb7e8f, (q31_t)0x13f549c3, + (q31_t)0x13ef14ea, (q31_t)0x13e8e005, (q31_t)0x13e2ab14, (q31_t)0x13dc7616, (q31_t)0x13d6410d, (q31_t)0x13d00bf7, (q31_t)0x13c9d6d4, (q31_t)0x13c3a1a6, + (q31_t)0x13bd6c6b, (q31_t)0x13b73725, (q31_t)0x13b101d2, (q31_t)0x13aacc73, (q31_t)0x13a49707, (q31_t)0x139e6190, (q31_t)0x13982c0d, (q31_t)0x1391f67d, + (q31_t)0x138bc0e1, (q31_t)0x13858b3a, (q31_t)0x137f5586, (q31_t)0x13791fc6, (q31_t)0x1372e9fb, (q31_t)0x136cb423, (q31_t)0x13667e3f, (q31_t)0x13604850, + (q31_t)0x135a1254, (q31_t)0x1353dc4c, (q31_t)0x134da639, (q31_t)0x1347701a, (q31_t)0x134139ee, (q31_t)0x133b03b7, (q31_t)0x1334cd74, (q31_t)0x132e9725, + (q31_t)0x132860ca, (q31_t)0x13222a64, (q31_t)0x131bf3f2, (q31_t)0x1315bd73, (q31_t)0x130f86ea, (q31_t)0x13095054, (q31_t)0x130319b3, (q31_t)0x12fce305, + (q31_t)0x12f6ac4d, (q31_t)0x12f07588, (q31_t)0x12ea3eb8, (q31_t)0x12e407dc, (q31_t)0x12ddd0f4, (q31_t)0x12d79a01, (q31_t)0x12d16303, (q31_t)0x12cb2bf8, + (q31_t)0x12c4f4e2, (q31_t)0x12bebdc1, (q31_t)0x12b88693, (q31_t)0x12b24f5b, (q31_t)0x12ac1817, (q31_t)0x12a5e0c7, (q31_t)0x129fa96c, (q31_t)0x12997205, + (q31_t)0x12933a93, (q31_t)0x128d0315, (q31_t)0x1286cb8c, (q31_t)0x128093f7, (q31_t)0x127a5c57, (q31_t)0x127424ac, (q31_t)0x126decf5, (q31_t)0x1267b533, + (q31_t)0x12617d66, (q31_t)0x125b458d, (q31_t)0x12550da9, (q31_t)0x124ed5ba, (q31_t)0x12489dbf, (q31_t)0x124265b9, (q31_t)0x123c2da8, (q31_t)0x1235f58b, + (q31_t)0x122fbd63, (q31_t)0x12298530, (q31_t)0x12234cf2, (q31_t)0x121d14a9, (q31_t)0x1216dc54, (q31_t)0x1210a3f5, (q31_t)0x120a6b8a, (q31_t)0x12043314, + (q31_t)0x11fdfa93, (q31_t)0x11f7c207, (q31_t)0x11f18970, (q31_t)0x11eb50cd, (q31_t)0x11e51820, (q31_t)0x11dedf68, (q31_t)0x11d8a6a4, (q31_t)0x11d26dd6, + (q31_t)0x11cc34fc, (q31_t)0x11c5fc18, (q31_t)0x11bfc329, (q31_t)0x11b98a2e, (q31_t)0x11b35129, (q31_t)0x11ad1819, (q31_t)0x11a6defe, (q31_t)0x11a0a5d8, + (q31_t)0x119a6ca7, (q31_t)0x1194336b, (q31_t)0x118dfa25, (q31_t)0x1187c0d3, (q31_t)0x11818777, (q31_t)0x117b4e10, (q31_t)0x1175149e, (q31_t)0x116edb22, + (q31_t)0x1168a19b, (q31_t)0x11626809, (q31_t)0x115c2e6c, (q31_t)0x1155f4c4, (q31_t)0x114fbb12, (q31_t)0x11498156, (q31_t)0x1143478e, (q31_t)0x113d0dbc, + (q31_t)0x1136d3df, (q31_t)0x113099f8, (q31_t)0x112a6006, (q31_t)0x11242609, (q31_t)0x111dec02, (q31_t)0x1117b1f0, (q31_t)0x111177d4, (q31_t)0x110b3dad, + (q31_t)0x1105037c, (q31_t)0x10fec940, (q31_t)0x10f88efa, (q31_t)0x10f254a9, (q31_t)0x10ec1a4e, (q31_t)0x10e5dfe8, (q31_t)0x10dfa578, (q31_t)0x10d96afe, + (q31_t)0x10d33079, (q31_t)0x10ccf5ea, (q31_t)0x10c6bb50, (q31_t)0x10c080ac, (q31_t)0x10ba45fe, (q31_t)0x10b40b45, (q31_t)0x10add082, (q31_t)0x10a795b5, + (q31_t)0x10a15ade, (q31_t)0x109b1ffc, (q31_t)0x1094e510, (q31_t)0x108eaa1a, (q31_t)0x10886f19, (q31_t)0x1082340f, (q31_t)0x107bf8fa, (q31_t)0x1075bddb, + (q31_t)0x106f82b2, (q31_t)0x1069477f, (q31_t)0x10630c41, (q31_t)0x105cd0fa, (q31_t)0x105695a8, (q31_t)0x10505a4d, (q31_t)0x104a1ee7, (q31_t)0x1043e377, + (q31_t)0x103da7fd, (q31_t)0x10376c79, (q31_t)0x103130ec, (q31_t)0x102af554, (q31_t)0x1024b9b2, (q31_t)0x101e7e06, (q31_t)0x10184251, (q31_t)0x10120691, + (q31_t)0x100bcac7, (q31_t)0x10058ef4, (q31_t)0xfff5317, (q31_t)0xff91730, (q31_t)0xff2db3e, (q31_t)0xfec9f44, (q31_t)0xfe6633f, (q31_t)0xfe02730, + (q31_t)0xfd9eb18, (q31_t)0xfd3aef6, (q31_t)0xfcd72ca, (q31_t)0xfc73695, (q31_t)0xfc0fa55, (q31_t)0xfbabe0c, (q31_t)0xfb481ba, (q31_t)0xfae455d, + (q31_t)0xfa808f7, (q31_t)0xfa1cc87, (q31_t)0xf9b900e, (q31_t)0xf95538b, (q31_t)0xf8f16fe, (q31_t)0xf88da68, (q31_t)0xf829dc8, (q31_t)0xf7c611f, + (q31_t)0xf76246c, (q31_t)0xf6fe7af, (q31_t)0xf69aae9, (q31_t)0xf636e1a, (q31_t)0xf5d3141, (q31_t)0xf56f45e, (q31_t)0xf50b773, (q31_t)0xf4a7a7d, + (q31_t)0xf443d7e, (q31_t)0xf3e0076, (q31_t)0xf37c365, (q31_t)0xf318649, (q31_t)0xf2b4925, (q31_t)0xf250bf7, (q31_t)0xf1ecec0, (q31_t)0xf189180, + (q31_t)0xf125436, (q31_t)0xf0c16e3, (q31_t)0xf05d987, (q31_t)0xeff9c21, (q31_t)0xef95eb2, (q31_t)0xef3213a, (q31_t)0xeece3b9, (q31_t)0xee6a62f, + (q31_t)0xee0689b, (q31_t)0xeda2afe, (q31_t)0xed3ed58, (q31_t)0xecdafa9, (q31_t)0xec771f1, (q31_t)0xec1342f, (q31_t)0xebaf665, (q31_t)0xeb4b891, + (q31_t)0xeae7ab4, (q31_t)0xea83ccf, (q31_t)0xea1fee0, (q31_t)0xe9bc0e8, (q31_t)0xe9582e7, (q31_t)0xe8f44dd, (q31_t)0xe8906cb, (q31_t)0xe82c8af, + (q31_t)0xe7c8a8a, (q31_t)0xe764c5c, (q31_t)0xe700e26, (q31_t)0xe69cfe6, (q31_t)0xe63919e, (q31_t)0xe5d534d, (q31_t)0xe5714f3, (q31_t)0xe50d690, + (q31_t)0xe4a9824, (q31_t)0xe4459af, (q31_t)0xe3e1b32, (q31_t)0xe37dcac, (q31_t)0xe319e1d, (q31_t)0xe2b5f85, (q31_t)0xe2520e5, (q31_t)0xe1ee23c, + (q31_t)0xe18a38a, (q31_t)0xe1264cf, (q31_t)0xe0c260c, (q31_t)0xe05e740, (q31_t)0xdffa86b, (q31_t)0xdf9698e, (q31_t)0xdf32aa8, (q31_t)0xdecebba, + (q31_t)0xde6acc3, (q31_t)0xde06dc3, (q31_t)0xdda2ebb, (q31_t)0xdd3efab, (q31_t)0xdcdb091, (q31_t)0xdc77170, (q31_t)0xdc13245, (q31_t)0xdbaf313, + (q31_t)0xdb4b3d7, (q31_t)0xdae7494, (q31_t)0xda83548, (q31_t)0xda1f5f3, (q31_t)0xd9bb696, (q31_t)0xd957731, (q31_t)0xd8f37c3, (q31_t)0xd88f84d, + (q31_t)0xd82b8cf, (q31_t)0xd7c7948, (q31_t)0xd7639b9, (q31_t)0xd6ffa22, (q31_t)0xd69ba82, (q31_t)0xd637ada, (q31_t)0xd5d3b2a, (q31_t)0xd56fb71, + (q31_t)0xd50bbb1, (q31_t)0xd4a7be8, (q31_t)0xd443c17, (q31_t)0xd3dfc3e, (q31_t)0xd37bc5c, (q31_t)0xd317c73, (q31_t)0xd2b3c81, (q31_t)0xd24fc87, + (q31_t)0xd1ebc85, (q31_t)0xd187c7b, (q31_t)0xd123c69, (q31_t)0xd0bfc4f, (q31_t)0xd05bc2d, (q31_t)0xcff7c02, (q31_t)0xcf93bd0, (q31_t)0xcf2fb96, + (q31_t)0xcecbb53, (q31_t)0xce67b09, (q31_t)0xce03ab7, (q31_t)0xcd9fa5d, (q31_t)0xcd3b9fb, (q31_t)0xccd7991, (q31_t)0xcc7391f, (q31_t)0xcc0f8a5, + (q31_t)0xcbab824, (q31_t)0xcb4779a, (q31_t)0xcae3709, (q31_t)0xca7f670, (q31_t)0xca1b5cf, (q31_t)0xc9b7526, (q31_t)0xc953475, (q31_t)0xc8ef3bd, + (q31_t)0xc88b2fd, (q31_t)0xc827235, (q31_t)0xc7c3166, (q31_t)0xc75f08f, (q31_t)0xc6fafb0, (q31_t)0xc696ec9, (q31_t)0xc632ddb, (q31_t)0xc5cece5, + (q31_t)0xc56abe8, (q31_t)0xc506ae3, (q31_t)0xc4a29d6, (q31_t)0xc43e8c2, (q31_t)0xc3da7a6, (q31_t)0xc376683, (q31_t)0xc312558, (q31_t)0xc2ae425, + (q31_t)0xc24a2eb, (q31_t)0xc1e61aa, (q31_t)0xc182061, (q31_t)0xc11df11, (q31_t)0xc0b9db9, (q31_t)0xc055c5a, (q31_t)0xbff1af3, (q31_t)0xbf8d985, + (q31_t)0xbf29810, (q31_t)0xbec5693, (q31_t)0xbe6150f, (q31_t)0xbdfd383, (q31_t)0xbd991f0, (q31_t)0xbd35056, (q31_t)0xbcd0eb5, (q31_t)0xbc6cd0c, + (q31_t)0xbc08b5c, (q31_t)0xbba49a5, (q31_t)0xbb407e7, (q31_t)0xbadc621, (q31_t)0xba78454, (q31_t)0xba14280, (q31_t)0xb9b00a5, (q31_t)0xb94bec2, + (q31_t)0xb8e7cd9, (q31_t)0xb883ae8, (q31_t)0xb81f8f0, (q31_t)0xb7bb6f2, (q31_t)0xb7574ec, (q31_t)0xb6f32df, (q31_t)0xb68f0cb, (q31_t)0xb62aeaf, + (q31_t)0xb5c6c8d, (q31_t)0xb562a64, (q31_t)0xb4fe834, (q31_t)0xb49a5fd, (q31_t)0xb4363bf, (q31_t)0xb3d217a, (q31_t)0xb36df2e, (q31_t)0xb309cdb, + (q31_t)0xb2a5a81, (q31_t)0xb241820, (q31_t)0xb1dd5b9, (q31_t)0xb17934b, (q31_t)0xb1150d5, (q31_t)0xb0b0e59, (q31_t)0xb04cbd6, (q31_t)0xafe894d, + (q31_t)0xaf846bc, (q31_t)0xaf20425, (q31_t)0xaebc187, (q31_t)0xae57ee2, (q31_t)0xadf3c37, (q31_t)0xad8f985, (q31_t)0xad2b6cc, (q31_t)0xacc740c, + (q31_t)0xac63146, (q31_t)0xabfee79, (q31_t)0xab9aba6, (q31_t)0xab368cc, (q31_t)0xaad25eb, (q31_t)0xaa6e304, (q31_t)0xaa0a016, (q31_t)0xa9a5d22, + (q31_t)0xa941a27, (q31_t)0xa8dd725, (q31_t)0xa87941d, (q31_t)0xa81510f, (q31_t)0xa7b0dfa, (q31_t)0xa74cadf, (q31_t)0xa6e87bd, (q31_t)0xa684495, + (q31_t)0xa620166, (q31_t)0xa5bbe31, (q31_t)0xa557af5, (q31_t)0xa4f37b3, (q31_t)0xa48f46b, (q31_t)0xa42b11d, (q31_t)0xa3c6dc8, (q31_t)0xa362a6d, + (q31_t)0xa2fe70b, (q31_t)0xa29a3a3, (q31_t)0xa236035, (q31_t)0xa1d1cc1, (q31_t)0xa16d946, (q31_t)0xa1095c6, (q31_t)0xa0a523f, (q31_t)0xa040eb1, + (q31_t)0x9fdcb1e, (q31_t)0x9f78784, (q31_t)0x9f143e5, (q31_t)0x9eb003f, (q31_t)0x9e4bc93, (q31_t)0x9de78e1, (q31_t)0x9d83529, (q31_t)0x9d1f16b, + (q31_t)0x9cbada7, (q31_t)0x9c569dc, (q31_t)0x9bf260c, (q31_t)0x9b8e236, (q31_t)0x9b29e59, (q31_t)0x9ac5a77, (q31_t)0x9a6168f, (q31_t)0x99fd2a0, + (q31_t)0x9998eac, (q31_t)0x9934ab2, (q31_t)0x98d06b2, (q31_t)0x986c2ac, (q31_t)0x9807ea1, (q31_t)0x97a3a8f, (q31_t)0x973f678, (q31_t)0x96db25a, + (q31_t)0x9676e37, (q31_t)0x9612a0e, (q31_t)0x95ae5e0, (q31_t)0x954a1ab, (q31_t)0x94e5d71, (q31_t)0x9481931, (q31_t)0x941d4eb, (q31_t)0x93b90a0, + (q31_t)0x9354c4f, (q31_t)0x92f07f8, (q31_t)0x928c39b, (q31_t)0x9227f39, (q31_t)0x91c3ad2, (q31_t)0x915f664, (q31_t)0x90fb1f1, (q31_t)0x9096d79, + (q31_t)0x90328fb, (q31_t)0x8fce477, (q31_t)0x8f69fee, (q31_t)0x8f05b5f, (q31_t)0x8ea16cb, (q31_t)0x8e3d231, (q31_t)0x8dd8d92, (q31_t)0x8d748ed, + (q31_t)0x8d10443, (q31_t)0x8cabf93, (q31_t)0x8c47ade, (q31_t)0x8be3624, (q31_t)0x8b7f164, (q31_t)0x8b1ac9f, (q31_t)0x8ab67d4, (q31_t)0x8a52304, + (q31_t)0x89ede2f, (q31_t)0x8989955, (q31_t)0x8925475, (q31_t)0x88c0f90, (q31_t)0x885caa5, (q31_t)0x87f85b5, (q31_t)0x87940c1, (q31_t)0x872fbc6, + (q31_t)0x86cb6c7, (q31_t)0x86671c2, (q31_t)0x8602cb9, (q31_t)0x859e7aa, (q31_t)0x853a296, (q31_t)0x84d5d7d, (q31_t)0x847185e, (q31_t)0x840d33b, + (q31_t)0x83a8e12, (q31_t)0x83448e5, (q31_t)0x82e03b2, (q31_t)0x827be7a, (q31_t)0x821793e, (q31_t)0x81b33fc, (q31_t)0x814eeb5, (q31_t)0x80ea969, + (q31_t)0x8086419, (q31_t)0x8021ec3, (q31_t)0x7fbd968, (q31_t)0x7f59409, (q31_t)0x7ef4ea4, (q31_t)0x7e9093b, (q31_t)0x7e2c3cd, (q31_t)0x7dc7e5a, + (q31_t)0x7d638e2, (q31_t)0x7cff365, (q31_t)0x7c9ade4, (q31_t)0x7c3685d, (q31_t)0x7bd22d2, (q31_t)0x7b6dd42, (q31_t)0x7b097ad, (q31_t)0x7aa5214, + (q31_t)0x7a40c76, (q31_t)0x79dc6d3, (q31_t)0x797812b, (q31_t)0x7913b7f, (q31_t)0x78af5ce, (q31_t)0x784b019, (q31_t)0x77e6a5e, (q31_t)0x77824a0, + (q31_t)0x771dedc, (q31_t)0x76b9914, (q31_t)0x7655347, (q31_t)0x75f0d76, (q31_t)0x758c7a1, (q31_t)0x75281c6, (q31_t)0x74c3be7, (q31_t)0x745f604, + (q31_t)0x73fb01c, (q31_t)0x7396a30, (q31_t)0x733243f, (q31_t)0x72cde4a, (q31_t)0x7269851, (q31_t)0x7205253, (q31_t)0x71a0c50, (q31_t)0x713c64a, + (q31_t)0x70d803f, (q31_t)0x7073a2f, (q31_t)0x700f41b, (q31_t)0x6faae03, (q31_t)0x6f467e7, (q31_t)0x6ee21c6, (q31_t)0x6e7dba1, (q31_t)0x6e19578, + (q31_t)0x6db4f4a, (q31_t)0x6d50919, (q31_t)0x6cec2e3, (q31_t)0x6c87ca9, (q31_t)0x6c2366a, (q31_t)0x6bbf028, (q31_t)0x6b5a9e1, (q31_t)0x6af6396, + (q31_t)0x6a91d47, (q31_t)0x6a2d6f4, (q31_t)0x69c909d, (q31_t)0x6964a42, (q31_t)0x69003e3, (q31_t)0x689bd80, (q31_t)0x6837718, (q31_t)0x67d30ad, + (q31_t)0x676ea3d, (q31_t)0x670a3ca, (q31_t)0x66a5d53, (q31_t)0x66416d8, (q31_t)0x65dd058, (q31_t)0x65789d5, (q31_t)0x651434e, (q31_t)0x64afcc3, + (q31_t)0x644b634, (q31_t)0x63e6fa2, (q31_t)0x638290b, (q31_t)0x631e271, (q31_t)0x62b9bd3, (q31_t)0x6255531, (q31_t)0x61f0e8b, (q31_t)0x618c7e1, + (q31_t)0x6128134, (q31_t)0x60c3a83, (q31_t)0x605f3ce, (q31_t)0x5ffad15, (q31_t)0x5f96659, (q31_t)0x5f31f99, (q31_t)0x5ecd8d6, (q31_t)0x5e6920e, + (q31_t)0x5e04b43, (q31_t)0x5da0475, (q31_t)0x5d3bda3, (q31_t)0x5cd76cd, (q31_t)0x5c72ff4, (q31_t)0x5c0e917, (q31_t)0x5baa237, (q31_t)0x5b45b53, + (q31_t)0x5ae146b, (q31_t)0x5a7cd80, (q31_t)0x5a18692, (q31_t)0x59b3fa0, (q31_t)0x594f8aa, (q31_t)0x58eb1b2, (q31_t)0x5886ab5, (q31_t)0x58223b6, + (q31_t)0x57bdcb3, (q31_t)0x57595ac, (q31_t)0x56f4ea2, (q31_t)0x5690795, (q31_t)0x562c085, (q31_t)0x55c7971, (q31_t)0x556325a, (q31_t)0x54feb3f, + (q31_t)0x549a422, (q31_t)0x5435d01, (q31_t)0x53d15dd, (q31_t)0x536ceb5, (q31_t)0x530878a, (q31_t)0x52a405d, (q31_t)0x523f92c, (q31_t)0x51db1f7, + (q31_t)0x5176ac0, (q31_t)0x5112385, (q31_t)0x50adc48, (q31_t)0x5049507, (q31_t)0x4fe4dc3, (q31_t)0x4f8067c, (q31_t)0x4f1bf32, (q31_t)0x4eb77e5, + (q31_t)0x4e53095, (q31_t)0x4dee942, (q31_t)0x4d8a1ec, (q31_t)0x4d25a93, (q31_t)0x4cc1337, (q31_t)0x4c5cbd8, (q31_t)0x4bf8476, (q31_t)0x4b93d11, + (q31_t)0x4b2f5a9, (q31_t)0x4acae3e, (q31_t)0x4a666d1, (q31_t)0x4a01f60, (q31_t)0x499d7ed, (q31_t)0x4939077, (q31_t)0x48d48fe, (q31_t)0x4870182, + (q31_t)0x480ba04, (q31_t)0x47a7282, (q31_t)0x4742afe, (q31_t)0x46de377, (q31_t)0x4679bee, (q31_t)0x4615461, (q31_t)0x45b0cd2, (q31_t)0x454c541, + (q31_t)0x44e7dac, (q31_t)0x4483615, (q31_t)0x441ee7c, (q31_t)0x43ba6df, (q31_t)0x4355f40, (q31_t)0x42f179f, (q31_t)0x428cffb, (q31_t)0x4228854, + (q31_t)0x41c40ab, (q31_t)0x415f8ff, (q31_t)0x40fb151, (q31_t)0x40969a0, (q31_t)0x40321ed, (q31_t)0x3fcda37, (q31_t)0x3f6927f, (q31_t)0x3f04ac4, + (q31_t)0x3ea0307, (q31_t)0x3e3bb48, (q31_t)0x3dd7386, (q31_t)0x3d72bc2, (q31_t)0x3d0e3fb, (q31_t)0x3ca9c32, (q31_t)0x3c45467, (q31_t)0x3be0c99, + (q31_t)0x3b7c4c9, (q31_t)0x3b17cf7, (q31_t)0x3ab3523, (q31_t)0x3a4ed4c, (q31_t)0x39ea573, (q31_t)0x3985d97, (q31_t)0x39215ba, (q31_t)0x38bcdda, + (q31_t)0x38585f8, (q31_t)0x37f3e14, (q31_t)0x378f62e, (q31_t)0x372ae46, (q31_t)0x36c665b, (q31_t)0x3661e6f, (q31_t)0x35fd680, (q31_t)0x3598e8f, + (q31_t)0x353469c, (q31_t)0x34cfea8, (q31_t)0x346b6b1, (q31_t)0x3406eb8, (q31_t)0x33a26bd, (q31_t)0x333dec0, (q31_t)0x32d96c1, (q31_t)0x3274ec0, + (q31_t)0x32106bd, (q31_t)0x31abeb9, (q31_t)0x31476b2, (q31_t)0x30e2ea9, (q31_t)0x307e69f, (q31_t)0x3019e93, (q31_t)0x2fb5684, (q31_t)0x2f50e74, + (q31_t)0x2eec663, (q31_t)0x2e87e4f, (q31_t)0x2e2363a, (q31_t)0x2dbee22, (q31_t)0x2d5a609, (q31_t)0x2cf5def, (q31_t)0x2c915d2, (q31_t)0x2c2cdb4, + (q31_t)0x2bc8594, (q31_t)0x2b63d73, (q31_t)0x2aff54f, (q31_t)0x2a9ad2a, (q31_t)0x2a36504, (q31_t)0x29d1cdc, (q31_t)0x296d4b2, (q31_t)0x2908c87, + (q31_t)0x28a445a, (q31_t)0x283fc2b, (q31_t)0x27db3fb, (q31_t)0x2776bc9, (q31_t)0x2712396, (q31_t)0x26adb62, (q31_t)0x264932b, (q31_t)0x25e4af4, + (q31_t)0x25802bb, (q31_t)0x251ba80, (q31_t)0x24b7244, (q31_t)0x2452a07, (q31_t)0x23ee1c8, (q31_t)0x2389988, (q31_t)0x2325147, (q31_t)0x22c0904, + (q31_t)0x225c0bf, (q31_t)0x21f787a, (q31_t)0x2193033, (q31_t)0x212e7eb, (q31_t)0x20c9fa1, (q31_t)0x2065757, (q31_t)0x2000f0b, (q31_t)0x1f9c6be, + (q31_t)0x1f37e6f, (q31_t)0x1ed3620, (q31_t)0x1e6edcf, (q31_t)0x1e0a57d, (q31_t)0x1da5d2a, (q31_t)0x1d414d6, (q31_t)0x1cdcc80, (q31_t)0x1c7842a, + (q31_t)0x1c13bd2, (q31_t)0x1baf37a, (q31_t)0x1b4ab20, (q31_t)0x1ae62c5, (q31_t)0x1a81a69, (q31_t)0x1a1d20c, (q31_t)0x19b89ae, (q31_t)0x1954150, + (q31_t)0x18ef8f0, (q31_t)0x188b08f, (q31_t)0x182682d, (q31_t)0x17c1fcb, (q31_t)0x175d767, (q31_t)0x16f8f03, (q31_t)0x169469d, (q31_t)0x162fe37, + (q31_t)0x15cb5d0, (q31_t)0x1566d68, (q31_t)0x15024ff, (q31_t)0x149dc96, (q31_t)0x143942b, (q31_t)0x13d4bc0, (q31_t)0x1370354, (q31_t)0x130bae7, + (q31_t)0x12a727a, (q31_t)0x1242a0c, (q31_t)0x11de19d, (q31_t)0x117992e, (q31_t)0x11150be, (q31_t)0x10b084d, (q31_t)0x104bfdb, (q31_t)0xfe7769, + (q31_t)0xf82ef6, (q31_t)0xf1e683, (q31_t)0xeb9e0f, (q31_t)0xe5559b, (q31_t)0xdf0d26, (q31_t)0xd8c4b0, (q31_t)0xd27c3a, (q31_t)0xcc33c3, + (q31_t)0xc5eb4c, (q31_t)0xbfa2d5, (q31_t)0xb95a5d, (q31_t)0xb311e4, (q31_t)0xacc96b, (q31_t)0xa680f2, (q31_t)0xa03878, (q31_t)0x99effe, + (q31_t)0x93a784, (q31_t)0x8d5f09, (q31_t)0x87168e, (q31_t)0x80ce12, (q31_t)0x7a8597, (q31_t)0x743d1a, (q31_t)0x6df49e, (q31_t)0x67ac21, + (q31_t)0x6163a5, (q31_t)0x5b1b27, (q31_t)0x54d2aa, (q31_t)0x4e8a2c, (q31_t)0x4841af, (q31_t)0x41f931, (q31_t)0x3bb0b3, (q31_t)0x356835, + (q31_t)0x2f1fb6, (q31_t)0x28d738, (q31_t)0x228eb9, (q31_t)0x1c463b, (q31_t)0x15fdbc, (q31_t)0xfb53d, (q31_t)0x96cbe, (q31_t)0x3243f +}; + #endif + +/** + @} end of DCT4_IDCT4_Table group + */ + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15) +/** + @brief Q15 table for reciprocal +*/ +const q15_t __ALIGNED(4) armRecipTableQ15[64] = { + 0x7F03, 0x7D13, 0x7B31, 0x795E, 0x7798, 0x75E0, + 0x7434, 0x7294, 0x70FF, 0x6F76, 0x6DF6, 0x6C82, + 0x6B16, 0x69B5, 0x685C, 0x670C, 0x65C4, 0x6484, + 0x634C, 0x621C, 0x60F3, 0x5FD0, 0x5EB5, 0x5DA0, + 0x5C91, 0x5B88, 0x5A85, 0x5988, 0x5890, 0x579E, + 0x56B0, 0x55C8, 0x54E4, 0x5405, 0x532B, 0x5255, + 0x5183, 0x50B6, 0x4FEC, 0x4F26, 0x4E64, 0x4DA6, + 0x4CEC, 0x4C34, 0x4B81, 0x4AD0, 0x4A23, 0x4978, + 0x48D1, 0x482D, 0x478C, 0x46ED, 0x4651, 0x45B8, + 0x4521, 0x448D, 0x43FC, 0x436C, 0x42DF, 0x4255, + 0x41CC, 0x4146, 0x40C2, 0x4040 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31) + +/** + @brief Q31 table for reciprocal +*/ +const q31_t armRecipTableQ31[64] = { + 0x7F03F03F, 0x7D137420, 0x7B31E739, 0x795E9F94, 0x7798FD29, 0x75E06928, + 0x7434554D, 0x72943B4B, 0x70FF9C40, 0x6F760031, 0x6DF6F593, 0x6C8210E3, + 0x6B16EC3A, 0x69B526F6, 0x685C655F, 0x670C505D, 0x65C4952D, 0x6484E519, + 0x634CF53E, 0x621C7E4F, 0x60F33C61, 0x5FD0EEB3, 0x5EB55785, 0x5DA03BEB, + 0x5C9163A1, 0x5B8898E6, 0x5A85A85A, 0x598860DF, 0x58909373, 0x579E1318, + 0x56B0B4B8, 0x55C84F0B, 0x54E4BA80, 0x5405D124, 0x532B6E8F, 0x52556FD0, + 0x5183B35A, 0x50B618F3, 0x4FEC81A2, 0x4F26CFA2, 0x4E64E64E, 0x4DA6AA1D, + 0x4CEC008B, 0x4C34D010, 0x4B810016, 0x4AD078EF, 0x4A2323C4, 0x4978EA96, + 0x48D1B827, 0x482D77FE, 0x478C1657, 0x46ED801D, 0x4651A2E5, 0x45B86CE2, + 0x4521CCE1, 0x448DB244, 0x43FC0CFA, 0x436CCD78, 0x42DFE4B4, 0x42554426, + 0x41CCDDB6, 0x4146A3C6, 0x40C28923, 0x40408102 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32) +/** + @par + Example code for the generation of the floating-point sine table: +
+  tableSize = 512;
+  for (n = 0; n < (tableSize + 1); n++)
+  {
+ 	sinTable[n] = sin(2*PI*n/tableSize);
+  }
+ @par + where PI value is 3.14159265358979 + */ +const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1] = { + 0.00000000f, 0.01227154f, 0.02454123f, 0.03680722f, 0.04906767f, 0.06132074f, + 0.07356456f, 0.08579731f, 0.09801714f, 0.11022221f, 0.12241068f, 0.13458071f, + 0.14673047f, 0.15885814f, 0.17096189f, 0.18303989f, 0.19509032f, 0.20711138f, + 0.21910124f, 0.23105811f, 0.24298018f, 0.25486566f, 0.26671276f, 0.27851969f, + 0.29028468f, 0.30200595f, 0.31368174f, 0.32531029f, 0.33688985f, 0.34841868f, + 0.35989504f, 0.37131719f, 0.38268343f, 0.39399204f, 0.40524131f, 0.41642956f, + 0.42755509f, 0.43861624f, 0.44961133f, 0.46053871f, 0.47139674f, 0.48218377f, + 0.49289819f, 0.50353838f, 0.51410274f, 0.52458968f, 0.53499762f, 0.54532499f, + 0.55557023f, 0.56573181f, 0.57580819f, 0.58579786f, 0.59569930f, 0.60551104f, + 0.61523159f, 0.62485949f, 0.63439328f, 0.64383154f, 0.65317284f, 0.66241578f, + 0.67155895f, 0.68060100f, 0.68954054f, 0.69837625f, 0.70710678f, 0.71573083f, + 0.72424708f, 0.73265427f, 0.74095113f, 0.74913639f, 0.75720885f, 0.76516727f, + 0.77301045f, 0.78073723f, 0.78834643f, 0.79583690f, 0.80320753f, 0.81045720f, + 0.81758481f, 0.82458930f, 0.83146961f, 0.83822471f, 0.84485357f, 0.85135519f, + 0.85772861f, 0.86397286f, 0.87008699f, 0.87607009f, 0.88192126f, 0.88763962f, + 0.89322430f, 0.89867447f, 0.90398929f, 0.90916798f, 0.91420976f, 0.91911385f, + 0.92387953f, 0.92850608f, 0.93299280f, 0.93733901f, 0.94154407f, 0.94560733f, + 0.94952818f, 0.95330604f, 0.95694034f, 0.96043052f, 0.96377607f, 0.96697647f, + 0.97003125f, 0.97293995f, 0.97570213f, 0.97831737f, 0.98078528f, 0.98310549f, + 0.98527764f, 0.98730142f, 0.98917651f, 0.99090264f, 0.99247953f, 0.99390697f, + 0.99518473f, 0.99631261f, 0.99729046f, 0.99811811f, 0.99879546f, 0.99932238f, + 0.99969882f, 0.99992470f, 1.00000000f, 0.99992470f, 0.99969882f, 0.99932238f, + 0.99879546f, 0.99811811f, 0.99729046f, 0.99631261f, 0.99518473f, 0.99390697f, + 0.99247953f, 0.99090264f, 0.98917651f, 0.98730142f, 0.98527764f, 0.98310549f, + 0.98078528f, 0.97831737f, 0.97570213f, 0.97293995f, 0.97003125f, 0.96697647f, + 0.96377607f, 0.96043052f, 0.95694034f, 0.95330604f, 0.94952818f, 0.94560733f, + 0.94154407f, 0.93733901f, 0.93299280f, 0.92850608f, 0.92387953f, 0.91911385f, + 0.91420976f, 0.90916798f, 0.90398929f, 0.89867447f, 0.89322430f, 0.88763962f, + 0.88192126f, 0.87607009f, 0.87008699f, 0.86397286f, 0.85772861f, 0.85135519f, + 0.84485357f, 0.83822471f, 0.83146961f, 0.82458930f, 0.81758481f, 0.81045720f, + 0.80320753f, 0.79583690f, 0.78834643f, 0.78073723f, 0.77301045f, 0.76516727f, + 0.75720885f, 0.74913639f, 0.74095113f, 0.73265427f, 0.72424708f, 0.71573083f, + 0.70710678f, 0.69837625f, 0.68954054f, 0.68060100f, 0.67155895f, 0.66241578f, + 0.65317284f, 0.64383154f, 0.63439328f, 0.62485949f, 0.61523159f, 0.60551104f, + 0.59569930f, 0.58579786f, 0.57580819f, 0.56573181f, 0.55557023f, 0.54532499f, + 0.53499762f, 0.52458968f, 0.51410274f, 0.50353838f, 0.49289819f, 0.48218377f, + 0.47139674f, 0.46053871f, 0.44961133f, 0.43861624f, 0.42755509f, 0.41642956f, + 0.40524131f, 0.39399204f, 0.38268343f, 0.37131719f, 0.35989504f, 0.34841868f, + 0.33688985f, 0.32531029f, 0.31368174f, 0.30200595f, 0.29028468f, 0.27851969f, + 0.26671276f, 0.25486566f, 0.24298018f, 0.23105811f, 0.21910124f, 0.20711138f, + 0.19509032f, 0.18303989f, 0.17096189f, 0.15885814f, 0.14673047f, 0.13458071f, + 0.12241068f, 0.11022221f, 0.09801714f, 0.08579731f, 0.07356456f, 0.06132074f, + 0.04906767f, 0.03680722f, 0.02454123f, 0.01227154f, 0.00000000f, -0.01227154f, + -0.02454123f, -0.03680722f, -0.04906767f, -0.06132074f, -0.07356456f, + -0.08579731f, -0.09801714f, -0.11022221f, -0.12241068f, -0.13458071f, + -0.14673047f, -0.15885814f, -0.17096189f, -0.18303989f, -0.19509032f, + -0.20711138f, -0.21910124f, -0.23105811f, -0.24298018f, -0.25486566f, + -0.26671276f, -0.27851969f, -0.29028468f, -0.30200595f, -0.31368174f, + -0.32531029f, -0.33688985f, -0.34841868f, -0.35989504f, -0.37131719f, + -0.38268343f, -0.39399204f, -0.40524131f, -0.41642956f, -0.42755509f, + -0.43861624f, -0.44961133f, -0.46053871f, -0.47139674f, -0.48218377f, + -0.49289819f, -0.50353838f, -0.51410274f, -0.52458968f, -0.53499762f, + -0.54532499f, -0.55557023f, -0.56573181f, -0.57580819f, -0.58579786f, + -0.59569930f, -0.60551104f, -0.61523159f, -0.62485949f, -0.63439328f, + -0.64383154f, -0.65317284f, -0.66241578f, -0.67155895f, -0.68060100f, + -0.68954054f, -0.69837625f, -0.70710678f, -0.71573083f, -0.72424708f, + -0.73265427f, -0.74095113f, -0.74913639f, -0.75720885f, -0.76516727f, + -0.77301045f, -0.78073723f, -0.78834643f, -0.79583690f, -0.80320753f, + -0.81045720f, -0.81758481f, -0.82458930f, -0.83146961f, -0.83822471f, + -0.84485357f, -0.85135519f, -0.85772861f, -0.86397286f, -0.87008699f, + -0.87607009f, -0.88192126f, -0.88763962f, -0.89322430f, -0.89867447f, + -0.90398929f, -0.90916798f, -0.91420976f, -0.91911385f, -0.92387953f, + -0.92850608f, -0.93299280f, -0.93733901f, -0.94154407f, -0.94560733f, + -0.94952818f, -0.95330604f, -0.95694034f, -0.96043052f, -0.96377607f, + -0.96697647f, -0.97003125f, -0.97293995f, -0.97570213f, -0.97831737f, + -0.98078528f, -0.98310549f, -0.98527764f, -0.98730142f, -0.98917651f, + -0.99090264f, -0.99247953f, -0.99390697f, -0.99518473f, -0.99631261f, + -0.99729046f, -0.99811811f, -0.99879546f, -0.99932238f, -0.99969882f, + -0.99992470f, -1.00000000f, -0.99992470f, -0.99969882f, -0.99932238f, + -0.99879546f, -0.99811811f, -0.99729046f, -0.99631261f, -0.99518473f, + -0.99390697f, -0.99247953f, -0.99090264f, -0.98917651f, -0.98730142f, + -0.98527764f, -0.98310549f, -0.98078528f, -0.97831737f, -0.97570213f, + -0.97293995f, -0.97003125f, -0.96697647f, -0.96377607f, -0.96043052f, + -0.95694034f, -0.95330604f, -0.94952818f, -0.94560733f, -0.94154407f, + -0.93733901f, -0.93299280f, -0.92850608f, -0.92387953f, -0.91911385f, + -0.91420976f, -0.90916798f, -0.90398929f, -0.89867447f, -0.89322430f, + -0.88763962f, -0.88192126f, -0.87607009f, -0.87008699f, -0.86397286f, + -0.85772861f, -0.85135519f, -0.84485357f, -0.83822471f, -0.83146961f, + -0.82458930f, -0.81758481f, -0.81045720f, -0.80320753f, -0.79583690f, + -0.78834643f, -0.78073723f, -0.77301045f, -0.76516727f, -0.75720885f, + -0.74913639f, -0.74095113f, -0.73265427f, -0.72424708f, -0.71573083f, + -0.70710678f, -0.69837625f, -0.68954054f, -0.68060100f, -0.67155895f, + -0.66241578f, -0.65317284f, -0.64383154f, -0.63439328f, -0.62485949f, + -0.61523159f, -0.60551104f, -0.59569930f, -0.58579786f, -0.57580819f, + -0.56573181f, -0.55557023f, -0.54532499f, -0.53499762f, -0.52458968f, + -0.51410274f, -0.50353838f, -0.49289819f, -0.48218377f, -0.47139674f, + -0.46053871f, -0.44961133f, -0.43861624f, -0.42755509f, -0.41642956f, + -0.40524131f, -0.39399204f, -0.38268343f, -0.37131719f, -0.35989504f, + -0.34841868f, -0.33688985f, -0.32531029f, -0.31368174f, -0.30200595f, + -0.29028468f, -0.27851969f, -0.26671276f, -0.25486566f, -0.24298018f, + -0.23105811f, -0.21910124f, -0.20711138f, -0.19509032f, -0.18303989f, + -0.17096189f, -0.15885814f, -0.14673047f, -0.13458071f, -0.12241068f, + -0.11022221f, -0.09801714f, -0.08579731f, -0.07356456f, -0.06132074f, + -0.04906767f, -0.03680722f, -0.02454123f, -0.01227154f, -0.00000000f +}; +#endif /* defined(ARM_ALL_FAST_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31) +/** + @par + Table values are in Q31 (1.31 fixed-point format) and generation is done in + three steps. First, generate sin values in floating point: +
+  tableSize = 512;
+  for (n = 0; n < (tableSize + 1); n++)
+  {
+ 	sinTable[n] = sin(2*PI*n/tableSize);
+  } 
+ where PI value is 3.14159265358979 + @par + Second, convert floating-point to Q31 (Fixed point): + (sinTable[i] * pow(2, 31)) + @par + Finally, round to the nearest integer value: + sinTable[i] += (sinTable[i] > 0 ? 0.5 : -0.5); + */ +const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1] = { + 0L, 26352928L, 52701887L, 79042909L, 105372028L, 131685278L, 157978697L, + 184248325L, 210490206L, 236700388L, 262874923L, 289009871L, 315101295L, + 341145265L, 367137861L, 393075166L, 418953276L, 444768294L, 470516330L, + 496193509L, 521795963L, 547319836L, 572761285L, 598116479L, 623381598L, + 648552838L, 673626408L, 698598533L, 723465451L, 748223418L, 772868706L, + 797397602L, 821806413L, 846091463L, 870249095L, 894275671L, 918167572L, + 941921200L, 965532978L, 988999351L, 1012316784L, 1035481766L, 1058490808L, + 1081340445L, 1104027237L, 1126547765L, 1148898640L, 1171076495L, 1193077991L, + 1214899813L, 1236538675L, 1257991320L, 1279254516L, 1300325060L, 1321199781L, + 1341875533L, 1362349204L, 1382617710L, 1402678000L, 1422527051L, 1442161874L, + 1461579514L, 1480777044L, 1499751576L, 1518500250L, 1537020244L, 1555308768L, + 1573363068L, 1591180426L, 1608758157L, 1626093616L, 1643184191L, 1660027308L, + 1676620432L, 1692961062L, 1709046739L, 1724875040L, 1740443581L, 1755750017L, + 1770792044L, 1785567396L, 1800073849L, 1814309216L, 1828271356L, 1841958164L, + 1855367581L, 1868497586L, 1881346202L, 1893911494L, 1906191570L, 1918184581L, + 1929888720L, 1941302225L, 1952423377L, 1963250501L, 1973781967L, 1984016189L, + 1993951625L, 2003586779L, 2012920201L, 2021950484L, 2030676269L, 2039096241L, + 2047209133L, 2055013723L, 2062508835L, 2069693342L, 2076566160L, 2083126254L, + 2089372638L, 2095304370L, 2100920556L, 2106220352L, 2111202959L, 2115867626L, + 2120213651L, 2124240380L, 2127947206L, 2131333572L, 2134398966L, 2137142927L, + 2139565043L, 2141664948L, 2143442326L, 2144896910L, 2146028480L, 2146836866L, + 2147321946L, 2147483647L, 2147321946L, 2146836866L, 2146028480L, 2144896910L, + 2143442326L, 2141664948L, 2139565043L, 2137142927L, 2134398966L, 2131333572L, + 2127947206L, 2124240380L, 2120213651L, 2115867626L, 2111202959L, 2106220352L, + 2100920556L, 2095304370L, 2089372638L, 2083126254L, 2076566160L, 2069693342L, + 2062508835L, 2055013723L, 2047209133L, 2039096241L, 2030676269L, 2021950484L, + 2012920201L, 2003586779L, 1993951625L, 1984016189L, 1973781967L, 1963250501L, + 1952423377L, 1941302225L, 1929888720L, 1918184581L, 1906191570L, 1893911494L, + 1881346202L, 1868497586L, 1855367581L, 1841958164L, 1828271356L, 1814309216L, + 1800073849L, 1785567396L, 1770792044L, 1755750017L, 1740443581L, 1724875040L, + 1709046739L, 1692961062L, 1676620432L, 1660027308L, 1643184191L, 1626093616L, + 1608758157L, 1591180426L, 1573363068L, 1555308768L, 1537020244L, 1518500250L, + 1499751576L, 1480777044L, 1461579514L, 1442161874L, 1422527051L, 1402678000L, + 1382617710L, 1362349204L, 1341875533L, 1321199781L, 1300325060L, 1279254516L, + 1257991320L, 1236538675L, 1214899813L, 1193077991L, 1171076495L, 1148898640L, + 1126547765L, 1104027237L, 1081340445L, 1058490808L, 1035481766L, 1012316784L, + 988999351L, 965532978L, 941921200L, 918167572L, 894275671L, 870249095L, + 846091463L, 821806413L, 797397602L, 772868706L, 748223418L, 723465451L, + 698598533L, 673626408L, 648552838L, 623381598L, 598116479L, 572761285L, + 547319836L, 521795963L, 496193509L, 470516330L, 444768294L, 418953276L, + 393075166L, 367137861L, 341145265L, 315101295L, 289009871L, 262874923L, + 236700388L, 210490206L, 184248325L, 157978697L, 131685278L, 105372028L, + 79042909L, 52701887L, 26352928L, 0L, -26352928L, -52701887L, -79042909L, + -105372028L, -131685278L, -157978697L, -184248325L, -210490206L, -236700388L, + -262874923L, -289009871L, -315101295L, -341145265L, -367137861L, -393075166L, + -418953276L, -444768294L, -470516330L, -496193509L, -521795963L, -547319836L, + -572761285L, -598116479L, -623381598L, -648552838L, -673626408L, -698598533L, + -723465451L, -748223418L, -772868706L, -797397602L, -821806413L, -846091463L, + -870249095L, -894275671L, -918167572L, -941921200L, -965532978L, -988999351L, + -1012316784L, -1035481766L, -1058490808L, -1081340445L, -1104027237L, + -1126547765L, -1148898640L, -1171076495L, -1193077991L, -1214899813L, + -1236538675L, -1257991320L, -1279254516L, -1300325060L, -1321199781L, + -1341875533L, -1362349204L, -1382617710L, -1402678000L, -1422527051L, + -1442161874L, -1461579514L, -1480777044L, -1499751576L, -1518500250L, + -1537020244L, -1555308768L, -1573363068L, -1591180426L, -1608758157L, + -1626093616L, -1643184191L, -1660027308L, -1676620432L, -1692961062L, + -1709046739L, -1724875040L, -1740443581L, -1755750017L, -1770792044L, + -1785567396L, -1800073849L, -1814309216L, -1828271356L, -1841958164L, + -1855367581L, -1868497586L, -1881346202L, -1893911494L, -1906191570L, + -1918184581L, -1929888720L, -1941302225L, -1952423377L, -1963250501L, + -1973781967L, -1984016189L, -1993951625L, -2003586779L, -2012920201L, + -2021950484L, -2030676269L, -2039096241L, -2047209133L, -2055013723L, + -2062508835L, -2069693342L, -2076566160L, -2083126254L, -2089372638L, + -2095304370L, -2100920556L, -2106220352L, -2111202959L, -2115867626L, + -2120213651L, -2124240380L, -2127947206L, -2131333572L, -2134398966L, + -2137142927L, -2139565043L, -2141664948L, -2143442326L, -2144896910L, + -2146028480L, -2146836866L, -2147321946L, (q31_t)0x80000000, -2147321946L, + -2146836866L, -2146028480L, -2144896910L, -2143442326L, -2141664948L, + -2139565043L, -2137142927L, -2134398966L, -2131333572L, -2127947206L, + -2124240380L, -2120213651L, -2115867626L, -2111202959L, -2106220352L, + -2100920556L, -2095304370L, -2089372638L, -2083126254L, -2076566160L, + -2069693342L, -2062508835L, -2055013723L, -2047209133L, -2039096241L, + -2030676269L, -2021950484L, -2012920201L, -2003586779L, -1993951625L, + -1984016189L, -1973781967L, -1963250501L, -1952423377L, -1941302225L, + -1929888720L, -1918184581L, -1906191570L, -1893911494L, -1881346202L, + -1868497586L, -1855367581L, -1841958164L, -1828271356L, -1814309216L, + -1800073849L, -1785567396L, -1770792044L, -1755750017L, -1740443581L, + -1724875040L, -1709046739L, -1692961062L, -1676620432L, -1660027308L, + -1643184191L, -1626093616L, -1608758157L, -1591180426L, -1573363068L, + -1555308768L, -1537020244L, -1518500250L, -1499751576L, -1480777044L, + -1461579514L, -1442161874L, -1422527051L, -1402678000L, -1382617710L, + -1362349204L, -1341875533L, -1321199781L, -1300325060L, -1279254516L, + -1257991320L, -1236538675L, -1214899813L, -1193077991L, -1171076495L, + -1148898640L, -1126547765L, -1104027237L, -1081340445L, -1058490808L, + -1035481766L, -1012316784L, -988999351L, -965532978L, -941921200L, + -918167572L, -894275671L, -870249095L, -846091463L, -821806413L, -797397602L, + -772868706L, -748223418L, -723465451L, -698598533L, -673626408L, -648552838L, + -623381598L, -598116479L, -572761285L, -547319836L, -521795963L, -496193509L, + -470516330L, -444768294L, -418953276L, -393075166L, -367137861L, -341145265L, + -315101295L, -289009871L, -262874923L, -236700388L, -210490206L, -184248325L, + -157978697L, -131685278L, -105372028L, -79042909L, -52701887L, -26352928L, 0 +}; + +#endif /* defined(ARM_ALL_FAST_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15) +/** + @par + Table values are in Q15 (1.15 fixed-point format) and generation is done in + three steps. First, generate sin values in floating point: +
+  tableSize = 512;
+  for (n = 0; n < (tableSize + 1); n++)
+  {
+ 	sinTable[n] = sin(2*PI*n/tableSize);
+  } 
+ where PI value is 3.14159265358979 + @par + Second, convert floating-point to Q15 (Fixed point): + (sinTable[i] * pow(2, 15)) + @par + Finally, round to the nearest integer value: + sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5); + */ +const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1] = { + 0, 402, 804, 1206, 1608, 2009, 2411, 2811, 3212, 3612, 4011, 4410, 4808, + 5205, 5602, 5998, 6393, 6787, 7180, 7571, 7962, 8351, 8740, 9127, 9512, + 9896, 10279, 10660, 11039, 11417, 11793, 12167, 12540, 12910, 13279, + 13646, 14010, 14373, 14733, 15091, 15447, 15800, 16151, 16500, 16846, + 17190, 17531, 17869, 18205, 18538, 18868, 19195, 19520, 19841, 20160, + 20475, 20788, 21097, 21403, 21706, 22006, 22302, 22595, 22884, 23170, + 23453, 23732, 24008, 24279, 24548, 24812, 25073, 25330, 25583, 25833, + 26078, 26320, 26557, 26791, 27020, 27246, 27467, 27684, 27897, 28106, + 28311, 28511, 28707, 28899, 29086, 29269, 29448, 29622, 29792, 29957, + 30118, 30274, 30425, 30572, 30715, 30853, 30986, 31114, 31238, 31357, + 31471, 31581, 31686, 31786, 31881, 31972, 32058, 32138, 32214, 32286, + 32352, 32413, 32470, 32522, 32568, 32610, 32647, 32679, 32706, 32729, + 32746, 32758, 32766, 32767, 32766, 32758, 32746, 32729, 32706, 32679, + 32647, 32610, 32568, 32522, 32470, 32413, 32352, 32286, 32214, 32138, + 32058, 31972, 31881, 31786, 31686, 31581, 31471, 31357, 31238, 31114, + 30986, 30853, 30715, 30572, 30425, 30274, 30118, 29957, 29792, 29622, + 29448, 29269, 29086, 28899, 28707, 28511, 28311, 28106, 27897, 27684, + 27467, 27246, 27020, 26791, 26557, 26320, 26078, 25833, 25583, 25330, + 25073, 24812, 24548, 24279, 24008, 23732, 23453, 23170, 22884, 22595, + 22302, 22006, 21706, 21403, 21097, 20788, 20475, 20160, 19841, 19520, + 19195, 18868, 18538, 18205, 17869, 17531, 17190, 16846, 16500, 16151, + 15800, 15447, 15091, 14733, 14373, 14010, 13646, 13279, 12910, 12540, + 12167, 11793, 11417, 11039, 10660, 10279, 9896, 9512, 9127, 8740, 8351, + 7962, 7571, 7180, 6787, 6393, 5998, 5602, 5205, 4808, 4410, 4011, 3612, + 3212, 2811, 2411, 2009, 1608, 1206, 804, 402, 0, -402, -804, -1206, + -1608, -2009, -2411, -2811, -3212, -3612, -4011, -4410, -4808, -5205, + -5602, -5998, -6393, -6787, -7180, -7571, -7962, -8351, -8740, -9127, + -9512, -9896, -10279, -10660, -11039, -11417, -11793, -12167, -12540, + -12910, -13279, -13646, -14010, -14373, -14733, -15091, -15447, -15800, + -16151, -16500, -16846, -17190, -17531, -17869, -18205, -18538, -18868, + -19195, -19520, -19841, -20160, -20475, -20788, -21097, -21403, -21706, + -22006, -22302, -22595, -22884, -23170, -23453, -23732, -24008, -24279, + -24548, -24812, -25073, -25330, -25583, -25833, -26078, -26320, -26557, + -26791, -27020, -27246, -27467, -27684, -27897, -28106, -28311, -28511, + -28707, -28899, -29086, -29269, -29448, -29622, -29792, -29957, -30118, + -30274, -30425, -30572, -30715, -30853, -30986, -31114, -31238, -31357, + -31471, -31581, -31686, -31786, -31881, -31972, -32058, -32138, -32214, + -32286, -32352, -32413, -32470, -32522, -32568, -32610, -32647, -32679, + -32706, -32729, -32746, -32758, -32766, -32768, -32766, -32758, -32746, + -32729, -32706, -32679, -32647, -32610, -32568, -32522, -32470, -32413, + -32352, -32286, -32214, -32138, -32058, -31972, -31881, -31786, -31686, + -31581, -31471, -31357, -31238, -31114, -30986, -30853, -30715, -30572, + -30425, -30274, -30118, -29957, -29792, -29622, -29448, -29269, -29086, + -28899, -28707, -28511, -28311, -28106, -27897, -27684, -27467, -27246, + -27020, -26791, -26557, -26320, -26078, -25833, -25583, -25330, -25073, + -24812, -24548, -24279, -24008, -23732, -23453, -23170, -22884, -22595, + -22302, -22006, -21706, -21403, -21097, -20788, -20475, -20160, -19841, + -19520, -19195, -18868, -18538, -18205, -17869, -17531, -17190, -16846, + -16500, -16151, -15800, -15447, -15091, -14733, -14373, -14010, -13646, + -13279, -12910, -12540, -12167, -11793, -11417, -11039, -10660, -10279, + -9896, -9512, -9127, -8740, -8351, -7962, -7571, -7180, -6787, -6393, + -5998, -5602, -5205, -4808, -4410, -4011, -3612, -3212, -2811, -2411, + -2009, -1608, -1206, -804, -402, 0 +}; +#endif /* defined(ARM_ALL_FAST_TABLES) */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) +const q31_t sqrtTable_Q31[256] = { + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x5ffffffe, 0x7ffffffa, 0x5e88c596, 0x7a39e2ff, + 0x5d2238d8, 0x74dfa6b1, 0x5bcb268e, 0x6fe69562, + 0x5a827998, 0x6b454dba, 0x5947373a, 0x66f39063, + 0x58187bf8, 0x62ea1669, 0x56f578e6, 0x5f226e5f, + 0x55dd714e, 0x5b96df40, 0x54cfb8b0, 0x58424fca, + 0x53cbb102, 0x552031c7, 0x52d0c92c, 0x522c7048, + 0x51de7bb2, 0x4f6360a9, 0x50f44d86, 0x4cc1b594, + 0x5011cd0a, 0x4a4473f6, 0x4f36911a, 0x47e8e962, + 0x4e62384e, 0x45aca3d0, 0x4d946838, 0x438d6a6a, + 0x4cccccca, 0x41893746, 0x4c0b17c0, 0x3f9e31fa, + 0x4b4f0022, 0x3dcaaac3, 0x4a9841ce, 0x3c0d1660, + 0x49e69d14, 0x3a640a53, 0x4939d654, 0x38ce39a6, + 0x4891b5b2, 0x374a720b, 0x47ee06ba, 0x35d7993c, + 0x474e9830, 0x3474aacc, 0x46b33bc0, 0x3320b60c, + 0x461bc5d2, 0x31dadc4f, 0x45880d4c, 0x30a24f3c, + 0x44f7eb6a, 0x2f764f6a, 0x446b3b92, 0x2e562b0b, + 0x43e1db32, 0x2d413cc9, 0x435ba98a, 0x2c36eab0, + 0x42d887a4, 0x2b36a542, 0x42585824, 0x2a3fe69b, + 0x41daff34, 0x295231b0, 0x41606266, 0x286d118d, + 0x40e868a4, 0x279018c3, 0x4072fa10, 0x26bae0c8, + 0x3ffffffe, 0x25ed0979, 0x3f8f64d2, 0x25263894, + 0x3f2113f8, 0x24661958, 0x3eb4f9d8, 0x23ac5c10, + 0x3e4b03ba, 0x22f8b5bb, 0x3de31fc4, 0x224adfba, + 0x3d7d3cee, 0x21a2977a, 0x3d194ae8, 0x20ff9e30, + 0x3cb73a24, 0x2061b89a, 0x3c56fbba, 0x1fc8aebb, + 0x3bf88166, 0x1f344ba6, 0x3b9bbd80, 0x1ea45d4b, + 0x3b40a2f0, 0x1e18b448, 0x3ae7252e, 0x1d9123b9, + 0x3a8f382c, 0x1d0d8113, 0x3a38d062, 0x1c8da3fb, + 0x39e3e2b6, 0x1c116628, 0x39906482, 0x1b98a33c, + 0x393e4b8a, 0x1b2338aa, 0x38ed8df6, 0x1ab1059a, + 0x389e2250, 0x1a41eace, 0x384fff7a, 0x19d5ca89, + 0x38031cb2, 0x196c887b, 0x37b77184, 0x190609a9, + 0x376cf5ce, 0x18a2345b, 0x3723a1ba, 0x1840f00a, + 0x36db6db6, 0x17e22550, 0x36945276, 0x1785bdd2, + 0x364e48f4, 0x172ba43e, 0x36094a64, 0x16d3c42c, + 0x35c55036, 0x167e0a1f, 0x35825414, 0x162a6372, + 0x35404fde, 0x15d8be4d, 0x34ff3dac, 0x1589099d, + 0x34bf17c4, 0x153b3508, 0x347fd89e, 0x14ef30e4, + 0x34417ade, 0x14a4ee2a, 0x3403f956, 0x145c5e76, + 0x33c74f02, 0x141573fa, 0x338b7706, 0x13d02171, + 0x33506cae, 0x138c5a28, 0x33162b6a, 0x134a11e6, + 0x32dcaed0, 0x13093cee, 0x32a3f294, 0x12c9cffa, + 0x326bf292, 0x128bc034, 0x3234aac0, 0x124f0330, + 0x31fe1736, 0x12138ee5, 0x31c83428, 0x11d959b0, + 0x3192fde6, 0x11a05a45, 0x315e70de, 0x116887b5, + 0x312a8994, 0x1131d960, 0x30f744aa, 0x10fc46fd, + 0x30c49ed6, 0x10c7c88b, 0x309294ea, 0x10945653, + 0x306123cc, 0x1061e8e6, 0x30304878, 0x10307919 +}; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE) +const q15_t sqrtTable_Q15[256] = { + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x5fff, 0x7fff, 0x5e88, 0x7a39, + 0x5d22, 0x74df, 0x5bcb, 0x6fe6, + 0x5a82, 0x6b45, 0x5947, 0x66f3, + 0x5818, 0x62ea, 0x56f5, 0x5f22, + 0x55dd, 0x5b96, 0x54cf, 0x5842, + 0x53cb, 0x5520, 0x52d0, 0x522c, + 0x51de, 0x4f63, 0x50f4, 0x4cc1, + 0x5011, 0x4a44, 0x4f36, 0x47e8, + 0x4e62, 0x45ac, 0x4d94, 0x438d, + 0x4ccc, 0x4189, 0x4c0b, 0x3f9e, + 0x4b4f, 0x3dca, 0x4a98, 0x3c0d, + 0x49e6, 0x3a64, 0x4939, 0x38ce, + 0x4891, 0x374a, 0x47ee, 0x35d7, + 0x474e, 0x3474, 0x46b3, 0x3320, + 0x461b, 0x31da, 0x4588, 0x30a2, + 0x44f7, 0x2f76, 0x446b, 0x2e56, + 0x43e1, 0x2d41, 0x435b, 0x2c36, + 0x42d8, 0x2b36, 0x4258, 0x2a3f, + 0x41da, 0x2952, 0x4160, 0x286d, + 0x40e8, 0x2790, 0x4072, 0x26ba, + 0x3fff, 0x25ed, 0x3f8f, 0x2526, + 0x3f21, 0x2466, 0x3eb4, 0x23ac, + 0x3e4b, 0x22f8, 0x3de3, 0x224a, + 0x3d7d, 0x21a2, 0x3d19, 0x20ff, + 0x3cb7, 0x2061, 0x3c56, 0x1fc8, + 0x3bf8, 0x1f34, 0x3b9b, 0x1ea4, + 0x3b40, 0x1e18, 0x3ae7, 0x1d91, + 0x3a8f, 0x1d0d, 0x3a38, 0x1c8d, + 0x39e3, 0x1c11, 0x3990, 0x1b98, + 0x393e, 0x1b23, 0x38ed, 0x1ab1, + 0x389e, 0x1a41, 0x384f, 0x19d5, + 0x3803, 0x196c, 0x37b7, 0x1906, + 0x376c, 0x18a2, 0x3723, 0x1840, + 0x36db, 0x17e2, 0x3694, 0x1785, + 0x364e, 0x172b, 0x3609, 0x16d3, + 0x35c5, 0x167e, 0x3582, 0x162a, + 0x3540, 0x15d8, 0x34ff, 0x1589, + 0x34bf, 0x153b, 0x347f, 0x14ef, + 0x3441, 0x14a4, 0x3403, 0x145c, + 0x33c7, 0x1415, 0x338b, 0x13d0, + 0x3350, 0x138c, 0x3316, 0x134a, + 0x32dc, 0x1309, 0x32a3, 0x12c9, + 0x326b, 0x128b, 0x3234, 0x124f, + 0x31fe, 0x1213, 0x31c8, 0x11d9, + 0x3192, 0x11a0, 0x315e, 0x1168, + 0x312a, 0x1131, 0x30f7, 0x10fc, + 0x30c4, 0x10c7, 0x3092, 0x1094, + 0x3061, 0x1061, 0x3030, 0x1030 +}; + #endif +#endif /* defined(ARM_MATH_MVEI) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q31) +/* +ClearAll[tofix]; +tofix[q_][a_] := With[{r = Round[a*2^q]}, + If[r > (2^q - 1), 2^q - 1, r] + ]; + +(* For q = format, 2^nb is length of the table *) +With[{q = 15, nb = 4, q12quarter = 16^^2000}, + With[{shift = Echo[q - nb]}, + Table[tofix[q][1.0/Sqrt[1.0*i/2^q]/8.0], {i, 2^(q - 2), + 2^q + q12quarter - 1, 2^shift}]] + ] // CopyToClipboard + +*/ +const q31_t sqrt_initial_lut_q31[32]={536870912, 506166750, 480191942, 457845052, 438353264, 421156193, \ +405836263, 392075079, 379625062, 368290407, 357913941, 348367849, \ +339546978, 331363921, 323745341, 316629190, 309962566, 303700050, \ +297802400, 292235509, 286969573, 281978417, 277238947, 272730696, \ +268435456, 264336964, 260420644, 256673389, 253083375, 249639903, \ +246333269, 243154642}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q31) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q15) +const q15_t sqrt_initial_lut_q15[16]={8192, 7327, 6689, 6193, 5793, 5461, 5181, 4940, 4730, 4544, 4379, \ +4230, 4096, 3974, 3862, 3759}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q15) */ + + +#endif /* #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) */ + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) +const float32_t exp_tab[8] = { + (1.f), + (0.0416598916054f), + (0.500000596046f), + (0.0014122662833f), + (1.00000011921f), + (0.00833693705499f), + (0.166665703058f), + (0.000195780929062f), +}; + +const float32_t __logf_lut_f32[8] = { + -2.295614848256274, /*p0*/ + -2.470711633419806, /*p4*/ + -5.686926051100417, /*p2*/ + -0.165253547131978, /*p6*/ + +5.175912446351073, /*p1*/ + +0.844006986174912, /*p5*/ + +4.584458825456749, /*p3*/ + +0.014127821926000 /*p7*/ +}; + +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + +/* haming weight LUT for bytes */ +#define B2(n) n, n + 1, n + 1, n + 2 +#define B4(n) B2(n) , B2(n + 1), B2(n + 1), B2(n + 2) +#define B6(n) B4(n) , B4(n + 1), B4(n + 1), B4(n + 2) + +// Lookup table that store the reverse of each table +const unsigned char hwLUT[256] = { B6(0), B6(1), B6(1), B6(2) }; + +#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables_f16.c new file mode 100644 index 00000000..ef14c84b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables_f16.c @@ -0,0 +1,12586 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables_f16.c + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math_types_f16.h" +/** + @ingroup ComplexFFT + */ + +/** + @addtogroup CFFT_CIFFT Complex FFT Tables + @{ + */ + + +/** + @brief Floating-point Twiddle factors Table Generation +*/ + +/* F16 */ +#if !defined(__CC_ARM) + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include "arm_common_tables_f16.h" + + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_16) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +*
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } 
+* \par +* where N = 16 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_16[32] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.923879533f, (float16_t)-0.382683432f +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_32) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +*
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } 
+* \par +* where N = 32 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_32[64] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.980785280f, (float16_t)-0.195090322f +}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_64) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +*
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } 
+* \par +* where N = 64 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_64[128] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.098017140f, (float16_t)0.995184727f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.290284677f, (float16_t)0.956940336f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.471396737f, (float16_t)0.881921264f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.634393284f, (float16_t)0.773010453f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.773010453f, (float16_t)0.634393284f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.881921264f, (float16_t)0.471396737f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.956940336f, (float16_t)0.290284677f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-0.995184727f, (float16_t)0.098017140f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.995184727f, (float16_t)-0.098017140f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.956940336f, (float16_t)-0.290284677f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.881921264f, (float16_t)-0.471396737f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.773010453f, (float16_t)-0.634393284f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.634393284f, (float16_t)-0.773010453f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.471396737f, (float16_t)-0.881921264f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.290284677f, (float16_t)-0.956940336f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.098017140f, (float16_t)-0.995184727f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.995184727f, (float16_t)-0.098017140f +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_128) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +*
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } 
+* \par +* where N = 128 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ + +const float16_t twiddleCoefF16_128[256] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.049067674f, (float16_t)0.998795456f, + (float16_t)-0.098017140f, (float16_t)0.995184727f, + (float16_t)-0.146730474f, (float16_t)0.989176510f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.242980180f, (float16_t)0.970031253f, + (float16_t)-0.290284677f, (float16_t)0.956940336f, + (float16_t)-0.336889853f, (float16_t)0.941544065f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.427555093f, (float16_t)0.903989293f, + (float16_t)-0.471396737f, (float16_t)0.881921264f, + (float16_t)-0.514102744f, (float16_t)0.857728610f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.595699304f, (float16_t)0.803207531f, + (float16_t)-0.634393284f, (float16_t)0.773010453f, + (float16_t)-0.671558955f, (float16_t)0.740951125f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.740951125f, (float16_t)0.671558955f, + (float16_t)-0.773010453f, (float16_t)0.634393284f, + (float16_t)-0.803207531f, (float16_t)0.595699304f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.857728610f, (float16_t)0.514102744f, + (float16_t)-0.881921264f, (float16_t)0.471396737f, + (float16_t)-0.903989293f, (float16_t)0.427555093f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.941544065f, (float16_t)0.336889853f, + (float16_t)-0.956940336f, (float16_t)0.290284677f, + (float16_t)-0.970031253f, (float16_t)0.242980180f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-0.989176510f, (float16_t)0.146730474f, + (float16_t)-0.995184727f, (float16_t)0.098017140f, + (float16_t)-0.998795456f, (float16_t)0.049067674f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.998795456f, (float16_t)-0.049067674f, + (float16_t)-0.995184727f, (float16_t)-0.098017140f, + (float16_t)-0.989176510f, (float16_t)-0.146730474f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.970031253f, (float16_t)-0.242980180f, + (float16_t)-0.956940336f, (float16_t)-0.290284677f, + (float16_t)-0.941544065f, (float16_t)-0.336889853f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.903989293f, (float16_t)-0.427555093f, + (float16_t)-0.881921264f, (float16_t)-0.471396737f, + (float16_t)-0.857728610f, (float16_t)-0.514102744f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.803207531f, (float16_t)-0.595699304f, + (float16_t)-0.773010453f, (float16_t)-0.634393284f, + (float16_t)-0.740951125f, (float16_t)-0.671558955f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.671558955f, (float16_t)-0.740951125f, + (float16_t)-0.634393284f, (float16_t)-0.773010453f, + (float16_t)-0.595699304f, (float16_t)-0.803207531f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.514102744f, (float16_t)-0.857728610f, + (float16_t)-0.471396737f, (float16_t)-0.881921264f, + (float16_t)-0.427555093f, (float16_t)-0.903989293f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.336889853f, (float16_t)-0.941544065f, + (float16_t)-0.290284677f, (float16_t)-0.956940336f, + (float16_t)-0.242980180f, (float16_t)-0.970031253f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.146730474f, (float16_t)-0.989176510f, + (float16_t)-0.098017140f, (float16_t)-0.995184727f, + (float16_t)-0.049067674f, (float16_t)-0.998795456f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.998795456f, (float16_t)-0.049067674f +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_256) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +*
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } 
+* \par +* where N = 256 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_256[512] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.024541229f, (float16_t)0.999698819f, + (float16_t)-0.049067674f, (float16_t)0.998795456f, + (float16_t)-0.073564564f, (float16_t)0.997290457f, + (float16_t)-0.098017140f, (float16_t)0.995184727f, + (float16_t)-0.122410675f, (float16_t)0.992479535f, + (float16_t)-0.146730474f, (float16_t)0.989176510f, + (float16_t)-0.170961889f, (float16_t)0.985277642f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.219101240f, (float16_t)0.975702130f, + (float16_t)-0.242980180f, (float16_t)0.970031253f, + (float16_t)-0.266712757f, (float16_t)0.963776066f, + (float16_t)-0.290284677f, (float16_t)0.956940336f, + (float16_t)-0.313681740f, (float16_t)0.949528181f, + (float16_t)-0.336889853f, (float16_t)0.941544065f, + (float16_t)-0.359895037f, (float16_t)0.932992799f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.405241314f, (float16_t)0.914209756f, + (float16_t)-0.427555093f, (float16_t)0.903989293f, + (float16_t)-0.449611330f, (float16_t)0.893224301f, + (float16_t)-0.471396737f, (float16_t)0.881921264f, + (float16_t)-0.492898192f, (float16_t)0.870086991f, + (float16_t)-0.514102744f, (float16_t)0.857728610f, + (float16_t)-0.534997620f, (float16_t)0.844853565f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.575808191f, (float16_t)0.817584813f, + (float16_t)-0.595699304f, (float16_t)0.803207531f, + (float16_t)-0.615231591f, (float16_t)0.788346428f, + (float16_t)-0.634393284f, (float16_t)0.773010453f, + (float16_t)-0.653172843f, (float16_t)0.757208847f, + (float16_t)-0.671558955f, (float16_t)0.740951125f, + (float16_t)-0.689540545f, (float16_t)0.724247083f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.724247083f, (float16_t)0.689540545f, + (float16_t)-0.740951125f, (float16_t)0.671558955f, + (float16_t)-0.757208847f, (float16_t)0.653172843f, + (float16_t)-0.773010453f, (float16_t)0.634393284f, + (float16_t)-0.788346428f, (float16_t)0.615231591f, + (float16_t)-0.803207531f, (float16_t)0.595699304f, + (float16_t)-0.817584813f, (float16_t)0.575808191f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.844853565f, (float16_t)0.534997620f, + (float16_t)-0.857728610f, (float16_t)0.514102744f, + (float16_t)-0.870086991f, (float16_t)0.492898192f, + (float16_t)-0.881921264f, (float16_t)0.471396737f, + (float16_t)-0.893224301f, (float16_t)0.449611330f, + (float16_t)-0.903989293f, (float16_t)0.427555093f, + (float16_t)-0.914209756f, (float16_t)0.405241314f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.932992799f, (float16_t)0.359895037f, + (float16_t)-0.941544065f, (float16_t)0.336889853f, + (float16_t)-0.949528181f, (float16_t)0.313681740f, + (float16_t)-0.956940336f, (float16_t)0.290284677f, + (float16_t)-0.963776066f, (float16_t)0.266712757f, + (float16_t)-0.970031253f, (float16_t)0.242980180f, + (float16_t)-0.975702130f, (float16_t)0.219101240f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-0.985277642f, (float16_t)0.170961889f, + (float16_t)-0.989176510f, (float16_t)0.146730474f, + (float16_t)-0.992479535f, (float16_t)0.122410675f, + (float16_t)-0.995184727f, (float16_t)0.098017140f, + (float16_t)-0.997290457f, (float16_t)0.073564564f, + (float16_t)-0.998795456f, (float16_t)0.049067674f, + (float16_t)-0.999698819f, (float16_t)0.024541229f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.999698819f, (float16_t)-0.024541229f, + (float16_t)-0.998795456f, (float16_t)-0.049067674f, + (float16_t)-0.997290457f, (float16_t)-0.073564564f, + (float16_t)-0.995184727f, (float16_t)-0.098017140f, + (float16_t)-0.992479535f, (float16_t)-0.122410675f, + (float16_t)-0.989176510f, (float16_t)-0.146730474f, + (float16_t)-0.985277642f, (float16_t)-0.170961889f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.975702130f, (float16_t)-0.219101240f, + (float16_t)-0.970031253f, (float16_t)-0.242980180f, + (float16_t)-0.963776066f, (float16_t)-0.266712757f, + (float16_t)-0.956940336f, (float16_t)-0.290284677f, + (float16_t)-0.949528181f, (float16_t)-0.313681740f, + (float16_t)-0.941544065f, (float16_t)-0.336889853f, + (float16_t)-0.932992799f, (float16_t)-0.359895037f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.914209756f, (float16_t)-0.405241314f, + (float16_t)-0.903989293f, (float16_t)-0.427555093f, + (float16_t)-0.893224301f, (float16_t)-0.449611330f, + (float16_t)-0.881921264f, (float16_t)-0.471396737f, + (float16_t)-0.870086991f, (float16_t)-0.492898192f, + (float16_t)-0.857728610f, (float16_t)-0.514102744f, + (float16_t)-0.844853565f, (float16_t)-0.534997620f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.817584813f, (float16_t)-0.575808191f, + (float16_t)-0.803207531f, (float16_t)-0.595699304f, + (float16_t)-0.788346428f, (float16_t)-0.615231591f, + (float16_t)-0.773010453f, (float16_t)-0.634393284f, + (float16_t)-0.757208847f, (float16_t)-0.653172843f, + (float16_t)-0.740951125f, (float16_t)-0.671558955f, + (float16_t)-0.724247083f, (float16_t)-0.689540545f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.689540545f, (float16_t)-0.724247083f, + (float16_t)-0.671558955f, (float16_t)-0.740951125f, + (float16_t)-0.653172843f, (float16_t)-0.757208847f, + (float16_t)-0.634393284f, (float16_t)-0.773010453f, + (float16_t)-0.615231591f, (float16_t)-0.788346428f, + (float16_t)-0.595699304f, (float16_t)-0.803207531f, + (float16_t)-0.575808191f, (float16_t)-0.817584813f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.534997620f, (float16_t)-0.844853565f, + (float16_t)-0.514102744f, (float16_t)-0.857728610f, + (float16_t)-0.492898192f, (float16_t)-0.870086991f, + (float16_t)-0.471396737f, (float16_t)-0.881921264f, + (float16_t)-0.449611330f, (float16_t)-0.893224301f, + (float16_t)-0.427555093f, (float16_t)-0.903989293f, + (float16_t)-0.405241314f, (float16_t)-0.914209756f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.359895037f, (float16_t)-0.932992799f, + (float16_t)-0.336889853f, (float16_t)-0.941544065f, + (float16_t)-0.313681740f, (float16_t)-0.949528181f, + (float16_t)-0.290284677f, (float16_t)-0.956940336f, + (float16_t)-0.266712757f, (float16_t)-0.963776066f, + (float16_t)-0.242980180f, (float16_t)-0.970031253f, + (float16_t)-0.219101240f, (float16_t)-0.975702130f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.170961889f, (float16_t)-0.985277642f, + (float16_t)-0.146730474f, (float16_t)-0.989176510f, + (float16_t)-0.122410675f, (float16_t)-0.992479535f, + (float16_t)-0.098017140f, (float16_t)-0.995184727f, + (float16_t)-0.073564564f, (float16_t)-0.997290457f, + (float16_t)-0.049067674f, (float16_t)-0.998795456f, + (float16_t)-0.024541229f, (float16_t)-0.999698819f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.999698819f, (float16_t)-0.024541229f +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_512) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +*
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } 
+* \par +* where N = 512 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_512[1024] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.863972856f, (float16_t)0.503538384f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.851355193f, (float16_t)0.524589683f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.795836905f, (float16_t)0.605511041f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.624859488f, (float16_t)0.780737229f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.605511041f, (float16_t)0.795836905f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.585797857f, (float16_t)0.810457198f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.565731811f, (float16_t)0.824589303f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.545324988f, (float16_t)0.838224706f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.524589683f, (float16_t)0.851355193f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.503538384f, (float16_t)0.863972856f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.482183772f, (float16_t)0.876070094f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.460538711f, (float16_t)0.887639620f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.012271538f, (float16_t)0.999924702f, + (float16_t)-0.024541229f, (float16_t)0.999698819f, + (float16_t)-0.036807223f, (float16_t)0.999322385f, + (float16_t)-0.049067674f, (float16_t)0.998795456f, + (float16_t)-0.061320736f, (float16_t)0.998118113f, + (float16_t)-0.073564564f, (float16_t)0.997290457f, + (float16_t)-0.085797312f, (float16_t)0.996312612f, + (float16_t)-0.098017140f, (float16_t)0.995184727f, + (float16_t)-0.110222207f, (float16_t)0.993906970f, + (float16_t)-0.122410675f, (float16_t)0.992479535f, + (float16_t)-0.134580709f, (float16_t)0.990902635f, + (float16_t)-0.146730474f, (float16_t)0.989176510f, + (float16_t)-0.158858143f, (float16_t)0.987301418f, + (float16_t)-0.170961889f, (float16_t)0.985277642f, + (float16_t)-0.183039888f, (float16_t)0.983105487f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.207111376f, (float16_t)0.978317371f, + (float16_t)-0.219101240f, (float16_t)0.975702130f, + (float16_t)-0.231058108f, (float16_t)0.972939952f, + (float16_t)-0.242980180f, (float16_t)0.970031253f, + (float16_t)-0.254865660f, (float16_t)0.966976471f, + (float16_t)-0.266712757f, (float16_t)0.963776066f, + (float16_t)-0.278519689f, (float16_t)0.960430519f, + (float16_t)-0.290284677f, (float16_t)0.956940336f, + (float16_t)-0.302005949f, (float16_t)0.953306040f, + (float16_t)-0.313681740f, (float16_t)0.949528181f, + (float16_t)-0.325310292f, (float16_t)0.945607325f, + (float16_t)-0.336889853f, (float16_t)0.941544065f, + (float16_t)-0.348418680f, (float16_t)0.937339012f, + (float16_t)-0.359895037f, (float16_t)0.932992799f, + (float16_t)-0.371317194f, (float16_t)0.928506080f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.393992040f, (float16_t)0.919113852f, + (float16_t)-0.405241314f, (float16_t)0.914209756f, + (float16_t)-0.416429560f, (float16_t)0.909167983f, + (float16_t)-0.427555093f, (float16_t)0.903989293f, + (float16_t)-0.438616239f, (float16_t)0.898674466f, + (float16_t)-0.449611330f, (float16_t)0.893224301f, + (float16_t)-0.460538711f, (float16_t)0.887639620f, + (float16_t)-0.471396737f, (float16_t)0.881921264f, + (float16_t)-0.482183772f, (float16_t)0.876070094f, + (float16_t)-0.492898192f, (float16_t)0.870086991f, + (float16_t)-0.503538384f, (float16_t)0.863972856f, + (float16_t)-0.514102744f, (float16_t)0.857728610f, + (float16_t)-0.524589683f, (float16_t)0.851355193f, + (float16_t)-0.534997620f, (float16_t)0.844853565f, + (float16_t)-0.545324988f, (float16_t)0.838224706f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.565731811f, (float16_t)0.824589303f, + (float16_t)-0.575808191f, (float16_t)0.817584813f, + (float16_t)-0.585797857f, (float16_t)0.810457198f, + (float16_t)-0.595699304f, (float16_t)0.803207531f, + (float16_t)-0.605511041f, (float16_t)0.795836905f, + (float16_t)-0.615231591f, (float16_t)0.788346428f, + (float16_t)-0.624859488f, (float16_t)0.780737229f, + (float16_t)-0.634393284f, (float16_t)0.773010453f, + (float16_t)-0.643831543f, (float16_t)0.765167266f, + (float16_t)-0.653172843f, (float16_t)0.757208847f, + (float16_t)-0.662415778f, (float16_t)0.749136395f, + (float16_t)-0.671558955f, (float16_t)0.740951125f, + (float16_t)-0.680600998f, (float16_t)0.732654272f, + (float16_t)-0.689540545f, (float16_t)0.724247083f, + (float16_t)-0.698376249f, (float16_t)0.715730825f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.715730825f, (float16_t)0.698376249f, + (float16_t)-0.724247083f, (float16_t)0.689540545f, + (float16_t)-0.732654272f, (float16_t)0.680600998f, + (float16_t)-0.740951125f, (float16_t)0.671558955f, + (float16_t)-0.749136395f, (float16_t)0.662415778f, + (float16_t)-0.757208847f, (float16_t)0.653172843f, + (float16_t)-0.765167266f, (float16_t)0.643831543f, + (float16_t)-0.773010453f, (float16_t)0.634393284f, + (float16_t)-0.780737229f, (float16_t)0.624859488f, + (float16_t)-0.788346428f, (float16_t)0.615231591f, + (float16_t)-0.795836905f, (float16_t)0.605511041f, + (float16_t)-0.803207531f, (float16_t)0.595699304f, + (float16_t)-0.810457198f, (float16_t)0.585797857f, + (float16_t)-0.817584813f, (float16_t)0.575808191f, + (float16_t)-0.824589303f, (float16_t)0.565731811f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.838224706f, (float16_t)0.545324988f, + (float16_t)-0.844853565f, (float16_t)0.534997620f, + (float16_t)-0.851355193f, (float16_t)0.524589683f, + (float16_t)-0.857728610f, (float16_t)0.514102744f, + (float16_t)-0.863972856f, (float16_t)0.503538384f, + (float16_t)-0.870086991f, (float16_t)0.492898192f, + (float16_t)-0.876070094f, (float16_t)0.482183772f, + (float16_t)-0.881921264f, (float16_t)0.471396737f, + (float16_t)-0.887639620f, (float16_t)0.460538711f, + (float16_t)-0.893224301f, (float16_t)0.449611330f, + (float16_t)-0.898674466f, (float16_t)0.438616239f, + (float16_t)-0.903989293f, (float16_t)0.427555093f, + (float16_t)-0.909167983f, (float16_t)0.416429560f, + (float16_t)-0.914209756f, (float16_t)0.405241314f, + (float16_t)-0.919113852f, (float16_t)0.393992040f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.928506080f, (float16_t)0.371317194f, + (float16_t)-0.932992799f, (float16_t)0.359895037f, + (float16_t)-0.937339012f, (float16_t)0.348418680f, + (float16_t)-0.941544065f, (float16_t)0.336889853f, + (float16_t)-0.945607325f, (float16_t)0.325310292f, + (float16_t)-0.949528181f, (float16_t)0.313681740f, + (float16_t)-0.953306040f, (float16_t)0.302005949f, + (float16_t)-0.956940336f, (float16_t)0.290284677f, + (float16_t)-0.960430519f, (float16_t)0.278519689f, + (float16_t)-0.963776066f, (float16_t)0.266712757f, + (float16_t)-0.966976471f, (float16_t)0.254865660f, + (float16_t)-0.970031253f, (float16_t)0.242980180f, + (float16_t)-0.972939952f, (float16_t)0.231058108f, + (float16_t)-0.975702130f, (float16_t)0.219101240f, + (float16_t)-0.978317371f, (float16_t)0.207111376f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-0.983105487f, (float16_t)0.183039888f, + (float16_t)-0.985277642f, (float16_t)0.170961889f, + (float16_t)-0.987301418f, (float16_t)0.158858143f, + (float16_t)-0.989176510f, (float16_t)0.146730474f, + (float16_t)-0.990902635f, (float16_t)0.134580709f, + (float16_t)-0.992479535f, (float16_t)0.122410675f, + (float16_t)-0.993906970f, (float16_t)0.110222207f, + (float16_t)-0.995184727f, (float16_t)0.098017140f, + (float16_t)-0.996312612f, (float16_t)0.085797312f, + (float16_t)-0.997290457f, (float16_t)0.073564564f, + (float16_t)-0.998118113f, (float16_t)0.061320736f, + (float16_t)-0.998795456f, (float16_t)0.049067674f, + (float16_t)-0.999322385f, (float16_t)0.036807223f, + (float16_t)-0.999698819f, (float16_t)0.024541229f, + (float16_t)-0.999924702f, (float16_t)0.012271538f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.999924702f, (float16_t)-0.012271538f, + (float16_t)-0.999698819f, (float16_t)-0.024541229f, + (float16_t)-0.999322385f, (float16_t)-0.036807223f, + (float16_t)-0.998795456f, (float16_t)-0.049067674f, + (float16_t)-0.998118113f, (float16_t)-0.061320736f, + (float16_t)-0.997290457f, (float16_t)-0.073564564f, + (float16_t)-0.996312612f, (float16_t)-0.085797312f, + (float16_t)-0.995184727f, (float16_t)-0.098017140f, + (float16_t)-0.993906970f, (float16_t)-0.110222207f, + (float16_t)-0.992479535f, (float16_t)-0.122410675f, + (float16_t)-0.990902635f, (float16_t)-0.134580709f, + (float16_t)-0.989176510f, (float16_t)-0.146730474f, + (float16_t)-0.987301418f, (float16_t)-0.158858143f, + (float16_t)-0.985277642f, (float16_t)-0.170961889f, + (float16_t)-0.983105487f, (float16_t)-0.183039888f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.978317371f, (float16_t)-0.207111376f, + (float16_t)-0.975702130f, (float16_t)-0.219101240f, + (float16_t)-0.972939952f, (float16_t)-0.231058108f, + (float16_t)-0.970031253f, (float16_t)-0.242980180f, + (float16_t)-0.966976471f, (float16_t)-0.254865660f, + (float16_t)-0.963776066f, (float16_t)-0.266712757f, + (float16_t)-0.960430519f, (float16_t)-0.278519689f, + (float16_t)-0.956940336f, (float16_t)-0.290284677f, + (float16_t)-0.953306040f, (float16_t)-0.302005949f, + (float16_t)-0.949528181f, (float16_t)-0.313681740f, + (float16_t)-0.945607325f, (float16_t)-0.325310292f, + (float16_t)-0.941544065f, (float16_t)-0.336889853f, + (float16_t)-0.937339012f, (float16_t)-0.348418680f, + (float16_t)-0.932992799f, (float16_t)-0.359895037f, + (float16_t)-0.928506080f, (float16_t)-0.371317194f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.919113852f, (float16_t)-0.393992040f, + (float16_t)-0.914209756f, (float16_t)-0.405241314f, + (float16_t)-0.909167983f, (float16_t)-0.416429560f, + (float16_t)-0.903989293f, (float16_t)-0.427555093f, + (float16_t)-0.898674466f, (float16_t)-0.438616239f, + (float16_t)-0.893224301f, (float16_t)-0.449611330f, + (float16_t)-0.887639620f, (float16_t)-0.460538711f, + (float16_t)-0.881921264f, (float16_t)-0.471396737f, + (float16_t)-0.876070094f, (float16_t)-0.482183772f, + (float16_t)-0.870086991f, (float16_t)-0.492898192f, + (float16_t)-0.863972856f, (float16_t)-0.503538384f, + (float16_t)-0.857728610f, (float16_t)-0.514102744f, + (float16_t)-0.851355193f, (float16_t)-0.524589683f, + (float16_t)-0.844853565f, (float16_t)-0.534997620f, + (float16_t)-0.838224706f, (float16_t)-0.545324988f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.824589303f, (float16_t)-0.565731811f, + (float16_t)-0.817584813f, (float16_t)-0.575808191f, + (float16_t)-0.810457198f, (float16_t)-0.585797857f, + (float16_t)-0.803207531f, (float16_t)-0.595699304f, + (float16_t)-0.795836905f, (float16_t)-0.605511041f, + (float16_t)-0.788346428f, (float16_t)-0.615231591f, + (float16_t)-0.780737229f, (float16_t)-0.624859488f, + (float16_t)-0.773010453f, (float16_t)-0.634393284f, + (float16_t)-0.765167266f, (float16_t)-0.643831543f, + (float16_t)-0.757208847f, (float16_t)-0.653172843f, + (float16_t)-0.749136395f, (float16_t)-0.662415778f, + (float16_t)-0.740951125f, (float16_t)-0.671558955f, + (float16_t)-0.732654272f, (float16_t)-0.680600998f, + (float16_t)-0.724247083f, (float16_t)-0.689540545f, + (float16_t)-0.715730825f, (float16_t)-0.698376249f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.698376249f, (float16_t)-0.715730825f, + (float16_t)-0.689540545f, (float16_t)-0.724247083f, + (float16_t)-0.680600998f, (float16_t)-0.732654272f, + (float16_t)-0.671558955f, (float16_t)-0.740951125f, + (float16_t)-0.662415778f, (float16_t)-0.749136395f, + (float16_t)-0.653172843f, (float16_t)-0.757208847f, + (float16_t)-0.643831543f, (float16_t)-0.765167266f, + (float16_t)-0.634393284f, (float16_t)-0.773010453f, + (float16_t)-0.624859488f, (float16_t)-0.780737229f, + (float16_t)-0.615231591f, (float16_t)-0.788346428f, + (float16_t)-0.605511041f, (float16_t)-0.795836905f, + (float16_t)-0.595699304f, (float16_t)-0.803207531f, + (float16_t)-0.585797857f, (float16_t)-0.810457198f, + (float16_t)-0.575808191f, (float16_t)-0.817584813f, + (float16_t)-0.565731811f, (float16_t)-0.824589303f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.545324988f, (float16_t)-0.838224706f, + (float16_t)-0.534997620f, (float16_t)-0.844853565f, + (float16_t)-0.524589683f, (float16_t)-0.851355193f, + (float16_t)-0.514102744f, (float16_t)-0.857728610f, + (float16_t)-0.503538384f, (float16_t)-0.863972856f, + (float16_t)-0.492898192f, (float16_t)-0.870086991f, + (float16_t)-0.482183772f, (float16_t)-0.876070094f, + (float16_t)-0.471396737f, (float16_t)-0.881921264f, + (float16_t)-0.460538711f, (float16_t)-0.887639620f, + (float16_t)-0.449611330f, (float16_t)-0.893224301f, + (float16_t)-0.438616239f, (float16_t)-0.898674466f, + (float16_t)-0.427555093f, (float16_t)-0.903989293f, + (float16_t)-0.416429560f, (float16_t)-0.909167983f, + (float16_t)-0.405241314f, (float16_t)-0.914209756f, + (float16_t)-0.393992040f, (float16_t)-0.919113852f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.371317194f, (float16_t)-0.928506080f, + (float16_t)-0.359895037f, (float16_t)-0.932992799f, + (float16_t)-0.348418680f, (float16_t)-0.937339012f, + (float16_t)-0.336889853f, (float16_t)-0.941544065f, + (float16_t)-0.325310292f, (float16_t)-0.945607325f, + (float16_t)-0.313681740f, (float16_t)-0.949528181f, + (float16_t)-0.302005949f, (float16_t)-0.953306040f, + (float16_t)-0.290284677f, (float16_t)-0.956940336f, + (float16_t)-0.278519689f, (float16_t)-0.960430519f, + (float16_t)-0.266712757f, (float16_t)-0.963776066f, + (float16_t)-0.254865660f, (float16_t)-0.966976471f, + (float16_t)-0.242980180f, (float16_t)-0.970031253f, + (float16_t)-0.231058108f, (float16_t)-0.972939952f, + (float16_t)-0.219101240f, (float16_t)-0.975702130f, + (float16_t)-0.207111376f, (float16_t)-0.978317371f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.183039888f, (float16_t)-0.983105487f, + (float16_t)-0.170961889f, (float16_t)-0.985277642f, + (float16_t)-0.158858143f, (float16_t)-0.987301418f, + (float16_t)-0.146730474f, (float16_t)-0.989176510f, + (float16_t)-0.134580709f, (float16_t)-0.990902635f, + (float16_t)-0.122410675f, (float16_t)-0.992479535f, + (float16_t)-0.110222207f, (float16_t)-0.993906970f, + (float16_t)-0.098017140f, (float16_t)-0.995184727f, + (float16_t)-0.085797312f, (float16_t)-0.996312612f, + (float16_t)-0.073564564f, (float16_t)-0.997290457f, + (float16_t)-0.061320736f, (float16_t)-0.998118113f, + (float16_t)-0.049067674f, (float16_t)-0.998795456f, + (float16_t)-0.036807223f, (float16_t)-0.999322385f, + (float16_t)-0.024541229f, (float16_t)-0.999698819f, + (float16_t)-0.012271538f, (float16_t)-0.999924702f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.012271538f, (float16_t)-0.999924702f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.371317194f, (float16_t)-0.928506080f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.393992040f, (float16_t)-0.919113852f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.416429560f, (float16_t)-0.909167983f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.438616239f, (float16_t)-0.898674466f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.460538711f, (float16_t)-0.887639620f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.482183772f, (float16_t)-0.876070094f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.503538384f, (float16_t)-0.863972856f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.524589683f, (float16_t)-0.851355193f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.545324988f, (float16_t)-0.838224706f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.565731811f, (float16_t)-0.824589303f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.585797857f, (float16_t)-0.810457198f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.605511041f, (float16_t)-0.795836905f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.624859488f, (float16_t)-0.780737229f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.643831543f, (float16_t)-0.765167266f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.662415778f, (float16_t)-0.749136395f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.680600998f, (float16_t)-0.732654272f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.698376249f, (float16_t)-0.715730825f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.715730825f, (float16_t)-0.698376249f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.732654272f, (float16_t)-0.680600998f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.749136395f, (float16_t)-0.662415778f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.765167266f, (float16_t)-0.643831543f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.780737229f, (float16_t)-0.624859488f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.795836905f, (float16_t)-0.605511041f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.810457198f, (float16_t)-0.585797857f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.824589303f, (float16_t)-0.565731811f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.838224706f, (float16_t)-0.545324988f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.851355193f, (float16_t)-0.524589683f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.863972856f, (float16_t)-0.503538384f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.876070094f, (float16_t)-0.482183772f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.887639620f, (float16_t)-0.460538711f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.898674466f, (float16_t)-0.438616239f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.909167983f, (float16_t)-0.416429560f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.919113852f, (float16_t)-0.393992040f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.928506080f, (float16_t)-0.371317194f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999924702f, (float16_t)-0.012271538f +}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_1024) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +*
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } 
+* \par +* where N = 1024 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_1024[2048] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999981175f, (float16_t)0.006135885f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)0.999830582f, (float16_t)0.018406730f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999529418f, (float16_t)0.030674803f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.999077728f, (float16_t)0.042938257f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.998475581f, (float16_t)0.055195244f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.997723067f, (float16_t)0.067443920f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.996820299f, (float16_t)0.079682438f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.995767414f, (float16_t)0.091908956f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.994564571f, (float16_t)0.104121634f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.993211949f, (float16_t)0.116318631f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.991709754f, (float16_t)0.128498111f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.990058210f, (float16_t)0.140658239f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.988257568f, (float16_t)0.152797185f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.986308097f, (float16_t)0.164913120f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.984210092f, (float16_t)0.177004220f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.981963869f, (float16_t)0.189068664f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.979569766f, (float16_t)0.201104635f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.977028143f, (float16_t)0.213110320f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.974339383f, (float16_t)0.225083911f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.971503891f, (float16_t)0.237023606f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.968522094f, (float16_t)0.248927606f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.965394442f, (float16_t)0.260794118f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.962121404f, (float16_t)0.272621355f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.958703475f, (float16_t)0.284407537f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.955141168f, (float16_t)0.296150888f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.951435021f, (float16_t)0.307849640f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.947585591f, (float16_t)0.319502031f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.943593458f, (float16_t)0.331106306f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.939459224f, (float16_t)0.342660717f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.935183510f, (float16_t)0.354163525f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.930766961f, (float16_t)0.365612998f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.926210242f, (float16_t)0.377007410f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.921514039f, (float16_t)0.388345047f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.916679060f, (float16_t)0.399624200f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.911706032f, (float16_t)0.410843171f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.906595705f, (float16_t)0.422000271f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.901348847f, (float16_t)0.433093819f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.895966250f, (float16_t)0.444122145f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.890448723f, (float16_t)0.455083587f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.884797098f, (float16_t)0.465976496f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.879012226f, (float16_t)0.476799230f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.873094978f, (float16_t)0.487550160f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.867046246f, (float16_t)0.498227667f, + (float16_t)0.863972856f, (float16_t)0.503538384f, + (float16_t)0.860866939f, (float16_t)0.508830143f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.854557988f, (float16_t)0.519355990f, + (float16_t)0.851355193f, (float16_t)0.524589683f, + (float16_t)0.848120345f, (float16_t)0.529803625f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.841554977f, (float16_t)0.540171473f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.834862875f, (float16_t)0.550457973f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.828045045f, (float16_t)0.560661576f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.821102515f, (float16_t)0.570780746f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.814036330f, (float16_t)0.580813958f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.806847554f, (float16_t)0.590759702f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.799537269f, (float16_t)0.600616479f, + (float16_t)0.795836905f, (float16_t)0.605511041f, + (float16_t)0.792106577f, (float16_t)0.610382806f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.784556597f, (float16_t)0.620057212f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.776888466f, (float16_t)0.629638239f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.769103338f, (float16_t)0.639124445f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.761202385f, (float16_t)0.648514401f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.753186799f, (float16_t)0.657806693f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.745057785f, (float16_t)0.666999922f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.736816569f, (float16_t)0.676092704f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.728464390f, (float16_t)0.685083668f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.720002508f, (float16_t)0.693971461f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.711432196f, (float16_t)0.702754744f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.702754744f, (float16_t)0.711432196f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.693971461f, (float16_t)0.720002508f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.685083668f, (float16_t)0.728464390f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.676092704f, (float16_t)0.736816569f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.666999922f, (float16_t)0.745057785f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.657806693f, (float16_t)0.753186799f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.648514401f, (float16_t)0.761202385f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.639124445f, (float16_t)0.769103338f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.629638239f, (float16_t)0.776888466f, + (float16_t)0.624859488f, (float16_t)0.780737229f, + (float16_t)0.620057212f, (float16_t)0.784556597f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.610382806f, (float16_t)0.792106577f, + (float16_t)0.605511041f, (float16_t)0.795836905f, + (float16_t)0.600616479f, (float16_t)0.799537269f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.590759702f, (float16_t)0.806847554f, + (float16_t)0.585797857f, (float16_t)0.810457198f, + (float16_t)0.580813958f, (float16_t)0.814036330f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.570780746f, (float16_t)0.821102515f, + (float16_t)0.565731811f, (float16_t)0.824589303f, + (float16_t)0.560661576f, (float16_t)0.828045045f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.550457973f, (float16_t)0.834862875f, + (float16_t)0.545324988f, (float16_t)0.838224706f, + (float16_t)0.540171473f, (float16_t)0.841554977f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.529803625f, (float16_t)0.848120345f, + (float16_t)0.524589683f, (float16_t)0.851355193f, + (float16_t)0.519355990f, (float16_t)0.854557988f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.508830143f, (float16_t)0.860866939f, + (float16_t)0.503538384f, (float16_t)0.863972856f, + (float16_t)0.498227667f, (float16_t)0.867046246f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.487550160f, (float16_t)0.873094978f, + (float16_t)0.482183772f, (float16_t)0.876070094f, + (float16_t)0.476799230f, (float16_t)0.879012226f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.465976496f, (float16_t)0.884797098f, + (float16_t)0.460538711f, (float16_t)0.887639620f, + (float16_t)0.455083587f, (float16_t)0.890448723f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.444122145f, (float16_t)0.895966250f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.433093819f, (float16_t)0.901348847f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.422000271f, (float16_t)0.906595705f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.410843171f, (float16_t)0.911706032f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.399624200f, (float16_t)0.916679060f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.388345047f, (float16_t)0.921514039f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.377007410f, (float16_t)0.926210242f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.365612998f, (float16_t)0.930766961f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.354163525f, (float16_t)0.935183510f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.342660717f, (float16_t)0.939459224f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.331106306f, (float16_t)0.943593458f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.319502031f, (float16_t)0.947585591f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.307849640f, (float16_t)0.951435021f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.296150888f, (float16_t)0.955141168f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.284407537f, (float16_t)0.958703475f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.272621355f, (float16_t)0.962121404f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.260794118f, (float16_t)0.965394442f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.248927606f, (float16_t)0.968522094f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.237023606f, (float16_t)0.971503891f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.225083911f, (float16_t)0.974339383f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.213110320f, (float16_t)0.977028143f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.201104635f, (float16_t)0.979569766f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.189068664f, (float16_t)0.981963869f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.177004220f, (float16_t)0.984210092f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.164913120f, (float16_t)0.986308097f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.152797185f, (float16_t)0.988257568f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.140658239f, (float16_t)0.990058210f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.128498111f, (float16_t)0.991709754f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.116318631f, (float16_t)0.993211949f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.104121634f, (float16_t)0.994564571f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.091908956f, (float16_t)0.995767414f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.079682438f, (float16_t)0.996820299f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.067443920f, (float16_t)0.997723067f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.055195244f, (float16_t)0.998475581f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.042938257f, (float16_t)0.999077728f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.030674803f, (float16_t)0.999529418f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.018406730f, (float16_t)0.999830582f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.006135885f, (float16_t)0.999981175f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.006135885f, (float16_t)0.999981175f, + (float16_t)-0.012271538f, (float16_t)0.999924702f, + (float16_t)-0.018406730f, (float16_t)0.999830582f, + (float16_t)-0.024541229f, (float16_t)0.999698819f, + (float16_t)-0.030674803f, (float16_t)0.999529418f, + (float16_t)-0.036807223f, (float16_t)0.999322385f, + (float16_t)-0.042938257f, (float16_t)0.999077728f, + (float16_t)-0.049067674f, (float16_t)0.998795456f, + (float16_t)-0.055195244f, (float16_t)0.998475581f, + (float16_t)-0.061320736f, (float16_t)0.998118113f, + (float16_t)-0.067443920f, (float16_t)0.997723067f, + (float16_t)-0.073564564f, (float16_t)0.997290457f, + (float16_t)-0.079682438f, (float16_t)0.996820299f, + (float16_t)-0.085797312f, (float16_t)0.996312612f, + (float16_t)-0.091908956f, (float16_t)0.995767414f, + (float16_t)-0.098017140f, (float16_t)0.995184727f, + (float16_t)-0.104121634f, (float16_t)0.994564571f, + (float16_t)-0.110222207f, (float16_t)0.993906970f, + (float16_t)-0.116318631f, (float16_t)0.993211949f, + (float16_t)-0.122410675f, (float16_t)0.992479535f, + (float16_t)-0.128498111f, (float16_t)0.991709754f, + (float16_t)-0.134580709f, (float16_t)0.990902635f, + (float16_t)-0.140658239f, (float16_t)0.990058210f, + (float16_t)-0.146730474f, (float16_t)0.989176510f, + (float16_t)-0.152797185f, (float16_t)0.988257568f, + (float16_t)-0.158858143f, (float16_t)0.987301418f, + (float16_t)-0.164913120f, (float16_t)0.986308097f, + (float16_t)-0.170961889f, (float16_t)0.985277642f, + (float16_t)-0.177004220f, (float16_t)0.984210092f, + (float16_t)-0.183039888f, (float16_t)0.983105487f, + (float16_t)-0.189068664f, (float16_t)0.981963869f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.201104635f, (float16_t)0.979569766f, + (float16_t)-0.207111376f, (float16_t)0.978317371f, + (float16_t)-0.213110320f, (float16_t)0.977028143f, + (float16_t)-0.219101240f, (float16_t)0.975702130f, + (float16_t)-0.225083911f, (float16_t)0.974339383f, + (float16_t)-0.231058108f, (float16_t)0.972939952f, + (float16_t)-0.237023606f, (float16_t)0.971503891f, + (float16_t)-0.242980180f, (float16_t)0.970031253f, + (float16_t)-0.248927606f, (float16_t)0.968522094f, + (float16_t)-0.254865660f, (float16_t)0.966976471f, + (float16_t)-0.260794118f, (float16_t)0.965394442f, + (float16_t)-0.266712757f, (float16_t)0.963776066f, + (float16_t)-0.272621355f, (float16_t)0.962121404f, + (float16_t)-0.278519689f, (float16_t)0.960430519f, + (float16_t)-0.284407537f, (float16_t)0.958703475f, + (float16_t)-0.290284677f, (float16_t)0.956940336f, + (float16_t)-0.296150888f, (float16_t)0.955141168f, + (float16_t)-0.302005949f, (float16_t)0.953306040f, + (float16_t)-0.307849640f, (float16_t)0.951435021f, + (float16_t)-0.313681740f, (float16_t)0.949528181f, + (float16_t)-0.319502031f, (float16_t)0.947585591f, + (float16_t)-0.325310292f, (float16_t)0.945607325f, + (float16_t)-0.331106306f, (float16_t)0.943593458f, + (float16_t)-0.336889853f, (float16_t)0.941544065f, + (float16_t)-0.342660717f, (float16_t)0.939459224f, + (float16_t)-0.348418680f, (float16_t)0.937339012f, + (float16_t)-0.354163525f, (float16_t)0.935183510f, + (float16_t)-0.359895037f, (float16_t)0.932992799f, + (float16_t)-0.365612998f, (float16_t)0.930766961f, + (float16_t)-0.371317194f, (float16_t)0.928506080f, + (float16_t)-0.377007410f, (float16_t)0.926210242f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.388345047f, (float16_t)0.921514039f, + (float16_t)-0.393992040f, (float16_t)0.919113852f, + (float16_t)-0.399624200f, (float16_t)0.916679060f, + (float16_t)-0.405241314f, (float16_t)0.914209756f, + (float16_t)-0.410843171f, (float16_t)0.911706032f, + (float16_t)-0.416429560f, (float16_t)0.909167983f, + (float16_t)-0.422000271f, (float16_t)0.906595705f, + (float16_t)-0.427555093f, (float16_t)0.903989293f, + (float16_t)-0.433093819f, (float16_t)0.901348847f, + (float16_t)-0.438616239f, (float16_t)0.898674466f, + (float16_t)-0.444122145f, (float16_t)0.895966250f, + (float16_t)-0.449611330f, (float16_t)0.893224301f, + (float16_t)-0.455083587f, (float16_t)0.890448723f, + (float16_t)-0.460538711f, (float16_t)0.887639620f, + (float16_t)-0.465976496f, (float16_t)0.884797098f, + (float16_t)-0.471396737f, (float16_t)0.881921264f, + (float16_t)-0.476799230f, (float16_t)0.879012226f, + (float16_t)-0.482183772f, (float16_t)0.876070094f, + (float16_t)-0.487550160f, (float16_t)0.873094978f, + (float16_t)-0.492898192f, (float16_t)0.870086991f, + (float16_t)-0.498227667f, (float16_t)0.867046246f, + (float16_t)-0.503538384f, (float16_t)0.863972856f, + (float16_t)-0.508830143f, (float16_t)0.860866939f, + (float16_t)-0.514102744f, (float16_t)0.857728610f, + (float16_t)-0.519355990f, (float16_t)0.854557988f, + (float16_t)-0.524589683f, (float16_t)0.851355193f, + (float16_t)-0.529803625f, (float16_t)0.848120345f, + (float16_t)-0.534997620f, (float16_t)0.844853565f, + (float16_t)-0.540171473f, (float16_t)0.841554977f, + (float16_t)-0.545324988f, (float16_t)0.838224706f, + (float16_t)-0.550457973f, (float16_t)0.834862875f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.560661576f, (float16_t)0.828045045f, + (float16_t)-0.565731811f, (float16_t)0.824589303f, + (float16_t)-0.570780746f, (float16_t)0.821102515f, + (float16_t)-0.575808191f, (float16_t)0.817584813f, + (float16_t)-0.580813958f, (float16_t)0.814036330f, + (float16_t)-0.585797857f, (float16_t)0.810457198f, + (float16_t)-0.590759702f, (float16_t)0.806847554f, + (float16_t)-0.595699304f, (float16_t)0.803207531f, + (float16_t)-0.600616479f, (float16_t)0.799537269f, + (float16_t)-0.605511041f, (float16_t)0.795836905f, + (float16_t)-0.610382806f, (float16_t)0.792106577f, + (float16_t)-0.615231591f, (float16_t)0.788346428f, + (float16_t)-0.620057212f, (float16_t)0.784556597f, + (float16_t)-0.624859488f, (float16_t)0.780737229f, + (float16_t)-0.629638239f, (float16_t)0.776888466f, + (float16_t)-0.634393284f, (float16_t)0.773010453f, + (float16_t)-0.639124445f, (float16_t)0.769103338f, + (float16_t)-0.643831543f, (float16_t)0.765167266f, + (float16_t)-0.648514401f, (float16_t)0.761202385f, + (float16_t)-0.653172843f, (float16_t)0.757208847f, + (float16_t)-0.657806693f, (float16_t)0.753186799f, + (float16_t)-0.662415778f, (float16_t)0.749136395f, + (float16_t)-0.666999922f, (float16_t)0.745057785f, + (float16_t)-0.671558955f, (float16_t)0.740951125f, + (float16_t)-0.676092704f, (float16_t)0.736816569f, + (float16_t)-0.680600998f, (float16_t)0.732654272f, + (float16_t)-0.685083668f, (float16_t)0.728464390f, + (float16_t)-0.689540545f, (float16_t)0.724247083f, + (float16_t)-0.693971461f, (float16_t)0.720002508f, + (float16_t)-0.698376249f, (float16_t)0.715730825f, + (float16_t)-0.702754744f, (float16_t)0.711432196f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.711432196f, (float16_t)0.702754744f, + (float16_t)-0.715730825f, (float16_t)0.698376249f, + (float16_t)-0.720002508f, (float16_t)0.693971461f, + (float16_t)-0.724247083f, (float16_t)0.689540545f, + (float16_t)-0.728464390f, (float16_t)0.685083668f, + (float16_t)-0.732654272f, (float16_t)0.680600998f, + (float16_t)-0.736816569f, (float16_t)0.676092704f, + (float16_t)-0.740951125f, (float16_t)0.671558955f, + (float16_t)-0.745057785f, (float16_t)0.666999922f, + (float16_t)-0.749136395f, (float16_t)0.662415778f, + (float16_t)-0.753186799f, (float16_t)0.657806693f, + (float16_t)-0.757208847f, (float16_t)0.653172843f, + (float16_t)-0.761202385f, (float16_t)0.648514401f, + (float16_t)-0.765167266f, (float16_t)0.643831543f, + (float16_t)-0.769103338f, (float16_t)0.639124445f, + (float16_t)-0.773010453f, (float16_t)0.634393284f, + (float16_t)-0.776888466f, (float16_t)0.629638239f, + (float16_t)-0.780737229f, (float16_t)0.624859488f, + (float16_t)-0.784556597f, (float16_t)0.620057212f, + (float16_t)-0.788346428f, (float16_t)0.615231591f, + (float16_t)-0.792106577f, (float16_t)0.610382806f, + (float16_t)-0.795836905f, (float16_t)0.605511041f, + (float16_t)-0.799537269f, (float16_t)0.600616479f, + (float16_t)-0.803207531f, (float16_t)0.595699304f, + (float16_t)-0.806847554f, (float16_t)0.590759702f, + (float16_t)-0.810457198f, (float16_t)0.585797857f, + (float16_t)-0.814036330f, (float16_t)0.580813958f, + (float16_t)-0.817584813f, (float16_t)0.575808191f, + (float16_t)-0.821102515f, (float16_t)0.570780746f, + (float16_t)-0.824589303f, (float16_t)0.565731811f, + (float16_t)-0.828045045f, (float16_t)0.560661576f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.834862875f, (float16_t)0.550457973f, + (float16_t)-0.838224706f, (float16_t)0.545324988f, + (float16_t)-0.841554977f, (float16_t)0.540171473f, + (float16_t)-0.844853565f, (float16_t)0.534997620f, + (float16_t)-0.848120345f, (float16_t)0.529803625f, + (float16_t)-0.851355193f, (float16_t)0.524589683f, + (float16_t)-0.854557988f, (float16_t)0.519355990f, + (float16_t)-0.857728610f, (float16_t)0.514102744f, + (float16_t)-0.860866939f, (float16_t)0.508830143f, + (float16_t)-0.863972856f, (float16_t)0.503538384f, + (float16_t)-0.867046246f, (float16_t)0.498227667f, + (float16_t)-0.870086991f, (float16_t)0.492898192f, + (float16_t)-0.873094978f, (float16_t)0.487550160f, + (float16_t)-0.876070094f, (float16_t)0.482183772f, + (float16_t)-0.879012226f, (float16_t)0.476799230f, + (float16_t)-0.881921264f, (float16_t)0.471396737f, + (float16_t)-0.884797098f, (float16_t)0.465976496f, + (float16_t)-0.887639620f, (float16_t)0.460538711f, + (float16_t)-0.890448723f, (float16_t)0.455083587f, + (float16_t)-0.893224301f, (float16_t)0.449611330f, + (float16_t)-0.895966250f, (float16_t)0.444122145f, + (float16_t)-0.898674466f, (float16_t)0.438616239f, + (float16_t)-0.901348847f, (float16_t)0.433093819f, + (float16_t)-0.903989293f, (float16_t)0.427555093f, + (float16_t)-0.906595705f, (float16_t)0.422000271f, + (float16_t)-0.909167983f, (float16_t)0.416429560f, + (float16_t)-0.911706032f, (float16_t)0.410843171f, + (float16_t)-0.914209756f, (float16_t)0.405241314f, + (float16_t)-0.916679060f, (float16_t)0.399624200f, + (float16_t)-0.919113852f, (float16_t)0.393992040f, + (float16_t)-0.921514039f, (float16_t)0.388345047f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.926210242f, (float16_t)0.377007410f, + (float16_t)-0.928506080f, (float16_t)0.371317194f, + (float16_t)-0.930766961f, (float16_t)0.365612998f, + (float16_t)-0.932992799f, (float16_t)0.359895037f, + (float16_t)-0.935183510f, (float16_t)0.354163525f, + (float16_t)-0.937339012f, (float16_t)0.348418680f, + (float16_t)-0.939459224f, (float16_t)0.342660717f, + (float16_t)-0.941544065f, (float16_t)0.336889853f, + (float16_t)-0.943593458f, (float16_t)0.331106306f, + (float16_t)-0.945607325f, (float16_t)0.325310292f, + (float16_t)-0.947585591f, (float16_t)0.319502031f, + (float16_t)-0.949528181f, (float16_t)0.313681740f, + (float16_t)-0.951435021f, (float16_t)0.307849640f, + (float16_t)-0.953306040f, (float16_t)0.302005949f, + (float16_t)-0.955141168f, (float16_t)0.296150888f, + (float16_t)-0.956940336f, (float16_t)0.290284677f, + (float16_t)-0.958703475f, (float16_t)0.284407537f, + (float16_t)-0.960430519f, (float16_t)0.278519689f, + (float16_t)-0.962121404f, (float16_t)0.272621355f, + (float16_t)-0.963776066f, (float16_t)0.266712757f, + (float16_t)-0.965394442f, (float16_t)0.260794118f, + (float16_t)-0.966976471f, (float16_t)0.254865660f, + (float16_t)-0.968522094f, (float16_t)0.248927606f, + (float16_t)-0.970031253f, (float16_t)0.242980180f, + (float16_t)-0.971503891f, (float16_t)0.237023606f, + (float16_t)-0.972939952f, (float16_t)0.231058108f, + (float16_t)-0.974339383f, (float16_t)0.225083911f, + (float16_t)-0.975702130f, (float16_t)0.219101240f, + (float16_t)-0.977028143f, (float16_t)0.213110320f, + (float16_t)-0.978317371f, (float16_t)0.207111376f, + (float16_t)-0.979569766f, (float16_t)0.201104635f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-0.981963869f, (float16_t)0.189068664f, + (float16_t)-0.983105487f, (float16_t)0.183039888f, + (float16_t)-0.984210092f, (float16_t)0.177004220f, + (float16_t)-0.985277642f, (float16_t)0.170961889f, + (float16_t)-0.986308097f, (float16_t)0.164913120f, + (float16_t)-0.987301418f, (float16_t)0.158858143f, + (float16_t)-0.988257568f, (float16_t)0.152797185f, + (float16_t)-0.989176510f, (float16_t)0.146730474f, + (float16_t)-0.990058210f, (float16_t)0.140658239f, + (float16_t)-0.990902635f, (float16_t)0.134580709f, + (float16_t)-0.991709754f, (float16_t)0.128498111f, + (float16_t)-0.992479535f, (float16_t)0.122410675f, + (float16_t)-0.993211949f, (float16_t)0.116318631f, + (float16_t)-0.993906970f, (float16_t)0.110222207f, + (float16_t)-0.994564571f, (float16_t)0.104121634f, + (float16_t)-0.995184727f, (float16_t)0.098017140f, + (float16_t)-0.995767414f, (float16_t)0.091908956f, + (float16_t)-0.996312612f, (float16_t)0.085797312f, + (float16_t)-0.996820299f, (float16_t)0.079682438f, + (float16_t)-0.997290457f, (float16_t)0.073564564f, + (float16_t)-0.997723067f, (float16_t)0.067443920f, + (float16_t)-0.998118113f, (float16_t)0.061320736f, + (float16_t)-0.998475581f, (float16_t)0.055195244f, + (float16_t)-0.998795456f, (float16_t)0.049067674f, + (float16_t)-0.999077728f, (float16_t)0.042938257f, + (float16_t)-0.999322385f, (float16_t)0.036807223f, + (float16_t)-0.999529418f, (float16_t)0.030674803f, + (float16_t)-0.999698819f, (float16_t)0.024541229f, + (float16_t)-0.999830582f, (float16_t)0.018406730f, + (float16_t)-0.999924702f, (float16_t)0.012271538f, + (float16_t)-0.999981175f, (float16_t)0.006135885f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.999981175f, (float16_t)-0.006135885f, + (float16_t)-0.999924702f, (float16_t)-0.012271538f, + (float16_t)-0.999830582f, (float16_t)-0.018406730f, + (float16_t)-0.999698819f, (float16_t)-0.024541229f, + (float16_t)-0.999529418f, (float16_t)-0.030674803f, + (float16_t)-0.999322385f, (float16_t)-0.036807223f, + (float16_t)-0.999077728f, (float16_t)-0.042938257f, + (float16_t)-0.998795456f, (float16_t)-0.049067674f, + (float16_t)-0.998475581f, (float16_t)-0.055195244f, + (float16_t)-0.998118113f, (float16_t)-0.061320736f, + (float16_t)-0.997723067f, (float16_t)-0.067443920f, + (float16_t)-0.997290457f, (float16_t)-0.073564564f, + (float16_t)-0.996820299f, (float16_t)-0.079682438f, + (float16_t)-0.996312612f, (float16_t)-0.085797312f, + (float16_t)-0.995767414f, (float16_t)-0.091908956f, + (float16_t)-0.995184727f, (float16_t)-0.098017140f, + (float16_t)-0.994564571f, (float16_t)-0.104121634f, + (float16_t)-0.993906970f, (float16_t)-0.110222207f, + (float16_t)-0.993211949f, (float16_t)-0.116318631f, + (float16_t)-0.992479535f, (float16_t)-0.122410675f, + (float16_t)-0.991709754f, (float16_t)-0.128498111f, + (float16_t)-0.990902635f, (float16_t)-0.134580709f, + (float16_t)-0.990058210f, (float16_t)-0.140658239f, + (float16_t)-0.989176510f, (float16_t)-0.146730474f, + (float16_t)-0.988257568f, (float16_t)-0.152797185f, + (float16_t)-0.987301418f, (float16_t)-0.158858143f, + (float16_t)-0.986308097f, (float16_t)-0.164913120f, + (float16_t)-0.985277642f, (float16_t)-0.170961889f, + (float16_t)-0.984210092f, (float16_t)-0.177004220f, + (float16_t)-0.983105487f, (float16_t)-0.183039888f, + (float16_t)-0.981963869f, (float16_t)-0.189068664f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.979569766f, (float16_t)-0.201104635f, + (float16_t)-0.978317371f, (float16_t)-0.207111376f, + (float16_t)-0.977028143f, (float16_t)-0.213110320f, + (float16_t)-0.975702130f, (float16_t)-0.219101240f, + (float16_t)-0.974339383f, (float16_t)-0.225083911f, + (float16_t)-0.972939952f, (float16_t)-0.231058108f, + (float16_t)-0.971503891f, (float16_t)-0.237023606f, + (float16_t)-0.970031253f, (float16_t)-0.242980180f, + (float16_t)-0.968522094f, (float16_t)-0.248927606f, + (float16_t)-0.966976471f, (float16_t)-0.254865660f, + (float16_t)-0.965394442f, (float16_t)-0.260794118f, + (float16_t)-0.963776066f, (float16_t)-0.266712757f, + (float16_t)-0.962121404f, (float16_t)-0.272621355f, + (float16_t)-0.960430519f, (float16_t)-0.278519689f, + (float16_t)-0.958703475f, (float16_t)-0.284407537f, + (float16_t)-0.956940336f, (float16_t)-0.290284677f, + (float16_t)-0.955141168f, (float16_t)-0.296150888f, + (float16_t)-0.953306040f, (float16_t)-0.302005949f, + (float16_t)-0.951435021f, (float16_t)-0.307849640f, + (float16_t)-0.949528181f, (float16_t)-0.313681740f, + (float16_t)-0.947585591f, (float16_t)-0.319502031f, + (float16_t)-0.945607325f, (float16_t)-0.325310292f, + (float16_t)-0.943593458f, (float16_t)-0.331106306f, + (float16_t)-0.941544065f, (float16_t)-0.336889853f, + (float16_t)-0.939459224f, (float16_t)-0.342660717f, + (float16_t)-0.937339012f, (float16_t)-0.348418680f, + (float16_t)-0.935183510f, (float16_t)-0.354163525f, + (float16_t)-0.932992799f, (float16_t)-0.359895037f, + (float16_t)-0.930766961f, (float16_t)-0.365612998f, + (float16_t)-0.928506080f, (float16_t)-0.371317194f, + (float16_t)-0.926210242f, (float16_t)-0.377007410f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.921514039f, (float16_t)-0.388345047f, + (float16_t)-0.919113852f, (float16_t)-0.393992040f, + (float16_t)-0.916679060f, (float16_t)-0.399624200f, + (float16_t)-0.914209756f, (float16_t)-0.405241314f, + (float16_t)-0.911706032f, (float16_t)-0.410843171f, + (float16_t)-0.909167983f, (float16_t)-0.416429560f, + (float16_t)-0.906595705f, (float16_t)-0.422000271f, + (float16_t)-0.903989293f, (float16_t)-0.427555093f, + (float16_t)-0.901348847f, (float16_t)-0.433093819f, + (float16_t)-0.898674466f, (float16_t)-0.438616239f, + (float16_t)-0.895966250f, (float16_t)-0.444122145f, + (float16_t)-0.893224301f, (float16_t)-0.449611330f, + (float16_t)-0.890448723f, (float16_t)-0.455083587f, + (float16_t)-0.887639620f, (float16_t)-0.460538711f, + (float16_t)-0.884797098f, (float16_t)-0.465976496f, + (float16_t)-0.881921264f, (float16_t)-0.471396737f, + (float16_t)-0.879012226f, (float16_t)-0.476799230f, + (float16_t)-0.876070094f, (float16_t)-0.482183772f, + (float16_t)-0.873094978f, (float16_t)-0.487550160f, + (float16_t)-0.870086991f, (float16_t)-0.492898192f, + (float16_t)-0.867046246f, (float16_t)-0.498227667f, + (float16_t)-0.863972856f, (float16_t)-0.503538384f, + (float16_t)-0.860866939f, (float16_t)-0.508830143f, + (float16_t)-0.857728610f, (float16_t)-0.514102744f, + (float16_t)-0.854557988f, (float16_t)-0.519355990f, + (float16_t)-0.851355193f, (float16_t)-0.524589683f, + (float16_t)-0.848120345f, (float16_t)-0.529803625f, + (float16_t)-0.844853565f, (float16_t)-0.534997620f, + (float16_t)-0.841554977f, (float16_t)-0.540171473f, + (float16_t)-0.838224706f, (float16_t)-0.545324988f, + (float16_t)-0.834862875f, (float16_t)-0.550457973f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.828045045f, (float16_t)-0.560661576f, + (float16_t)-0.824589303f, (float16_t)-0.565731811f, + (float16_t)-0.821102515f, (float16_t)-0.570780746f, + (float16_t)-0.817584813f, (float16_t)-0.575808191f, + (float16_t)-0.814036330f, (float16_t)-0.580813958f, + (float16_t)-0.810457198f, (float16_t)-0.585797857f, + (float16_t)-0.806847554f, (float16_t)-0.590759702f, + (float16_t)-0.803207531f, (float16_t)-0.595699304f, + (float16_t)-0.799537269f, (float16_t)-0.600616479f, + (float16_t)-0.795836905f, (float16_t)-0.605511041f, + (float16_t)-0.792106577f, (float16_t)-0.610382806f, + (float16_t)-0.788346428f, (float16_t)-0.615231591f, + (float16_t)-0.784556597f, (float16_t)-0.620057212f, + (float16_t)-0.780737229f, (float16_t)-0.624859488f, + (float16_t)-0.776888466f, (float16_t)-0.629638239f, + (float16_t)-0.773010453f, (float16_t)-0.634393284f, + (float16_t)-0.769103338f, (float16_t)-0.639124445f, + (float16_t)-0.765167266f, (float16_t)-0.643831543f, + (float16_t)-0.761202385f, (float16_t)-0.648514401f, + (float16_t)-0.757208847f, (float16_t)-0.653172843f, + (float16_t)-0.753186799f, (float16_t)-0.657806693f, + (float16_t)-0.749136395f, (float16_t)-0.662415778f, + (float16_t)-0.745057785f, (float16_t)-0.666999922f, + (float16_t)-0.740951125f, (float16_t)-0.671558955f, + (float16_t)-0.736816569f, (float16_t)-0.676092704f, + (float16_t)-0.732654272f, (float16_t)-0.680600998f, + (float16_t)-0.728464390f, (float16_t)-0.685083668f, + (float16_t)-0.724247083f, (float16_t)-0.689540545f, + (float16_t)-0.720002508f, (float16_t)-0.693971461f, + (float16_t)-0.715730825f, (float16_t)-0.698376249f, + (float16_t)-0.711432196f, (float16_t)-0.702754744f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.702754744f, (float16_t)-0.711432196f, + (float16_t)-0.698376249f, (float16_t)-0.715730825f, + (float16_t)-0.693971461f, (float16_t)-0.720002508f, + (float16_t)-0.689540545f, (float16_t)-0.724247083f, + (float16_t)-0.685083668f, (float16_t)-0.728464390f, + (float16_t)-0.680600998f, (float16_t)-0.732654272f, + (float16_t)-0.676092704f, (float16_t)-0.736816569f, + (float16_t)-0.671558955f, (float16_t)-0.740951125f, + (float16_t)-0.666999922f, (float16_t)-0.745057785f, + (float16_t)-0.662415778f, (float16_t)-0.749136395f, + (float16_t)-0.657806693f, (float16_t)-0.753186799f, + (float16_t)-0.653172843f, (float16_t)-0.757208847f, + (float16_t)-0.648514401f, (float16_t)-0.761202385f, + (float16_t)-0.643831543f, (float16_t)-0.765167266f, + (float16_t)-0.639124445f, (float16_t)-0.769103338f, + (float16_t)-0.634393284f, (float16_t)-0.773010453f, + (float16_t)-0.629638239f, (float16_t)-0.776888466f, + (float16_t)-0.624859488f, (float16_t)-0.780737229f, + (float16_t)-0.620057212f, (float16_t)-0.784556597f, + (float16_t)-0.615231591f, (float16_t)-0.788346428f, + (float16_t)-0.610382806f, (float16_t)-0.792106577f, + (float16_t)-0.605511041f, (float16_t)-0.795836905f, + (float16_t)-0.600616479f, (float16_t)-0.799537269f, + (float16_t)-0.595699304f, (float16_t)-0.803207531f, + (float16_t)-0.590759702f, (float16_t)-0.806847554f, + (float16_t)-0.585797857f, (float16_t)-0.810457198f, + (float16_t)-0.580813958f, (float16_t)-0.814036330f, + (float16_t)-0.575808191f, (float16_t)-0.817584813f, + (float16_t)-0.570780746f, (float16_t)-0.821102515f, + (float16_t)-0.565731811f, (float16_t)-0.824589303f, + (float16_t)-0.560661576f, (float16_t)-0.828045045f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.550457973f, (float16_t)-0.834862875f, + (float16_t)-0.545324988f, (float16_t)-0.838224706f, + (float16_t)-0.540171473f, (float16_t)-0.841554977f, + (float16_t)-0.534997620f, (float16_t)-0.844853565f, + (float16_t)-0.529803625f, (float16_t)-0.848120345f, + (float16_t)-0.524589683f, (float16_t)-0.851355193f, + (float16_t)-0.519355990f, (float16_t)-0.854557988f, + (float16_t)-0.514102744f, (float16_t)-0.857728610f, + (float16_t)-0.508830143f, (float16_t)-0.860866939f, + (float16_t)-0.503538384f, (float16_t)-0.863972856f, + (float16_t)-0.498227667f, (float16_t)-0.867046246f, + (float16_t)-0.492898192f, (float16_t)-0.870086991f, + (float16_t)-0.487550160f, (float16_t)-0.873094978f, + (float16_t)-0.482183772f, (float16_t)-0.876070094f, + (float16_t)-0.476799230f, (float16_t)-0.879012226f, + (float16_t)-0.471396737f, (float16_t)-0.881921264f, + (float16_t)-0.465976496f, (float16_t)-0.884797098f, + (float16_t)-0.460538711f, (float16_t)-0.887639620f, + (float16_t)-0.455083587f, (float16_t)-0.890448723f, + (float16_t)-0.449611330f, (float16_t)-0.893224301f, + (float16_t)-0.444122145f, (float16_t)-0.895966250f, + (float16_t)-0.438616239f, (float16_t)-0.898674466f, + (float16_t)-0.433093819f, (float16_t)-0.901348847f, + (float16_t)-0.427555093f, (float16_t)-0.903989293f, + (float16_t)-0.422000271f, (float16_t)-0.906595705f, + (float16_t)-0.416429560f, (float16_t)-0.909167983f, + (float16_t)-0.410843171f, (float16_t)-0.911706032f, + (float16_t)-0.405241314f, (float16_t)-0.914209756f, + (float16_t)-0.399624200f, (float16_t)-0.916679060f, + (float16_t)-0.393992040f, (float16_t)-0.919113852f, + (float16_t)-0.388345047f, (float16_t)-0.921514039f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.377007410f, (float16_t)-0.926210242f, + (float16_t)-0.371317194f, (float16_t)-0.928506080f, + (float16_t)-0.365612998f, (float16_t)-0.930766961f, + (float16_t)-0.359895037f, (float16_t)-0.932992799f, + (float16_t)-0.354163525f, (float16_t)-0.935183510f, + (float16_t)-0.348418680f, (float16_t)-0.937339012f, + (float16_t)-0.342660717f, (float16_t)-0.939459224f, + (float16_t)-0.336889853f, (float16_t)-0.941544065f, + (float16_t)-0.331106306f, (float16_t)-0.943593458f, + (float16_t)-0.325310292f, (float16_t)-0.945607325f, + (float16_t)-0.319502031f, (float16_t)-0.947585591f, + (float16_t)-0.313681740f, (float16_t)-0.949528181f, + (float16_t)-0.307849640f, (float16_t)-0.951435021f, + (float16_t)-0.302005949f, (float16_t)-0.953306040f, + (float16_t)-0.296150888f, (float16_t)-0.955141168f, + (float16_t)-0.290284677f, (float16_t)-0.956940336f, + (float16_t)-0.284407537f, (float16_t)-0.958703475f, + (float16_t)-0.278519689f, (float16_t)-0.960430519f, + (float16_t)-0.272621355f, (float16_t)-0.962121404f, + (float16_t)-0.266712757f, (float16_t)-0.963776066f, + (float16_t)-0.260794118f, (float16_t)-0.965394442f, + (float16_t)-0.254865660f, (float16_t)-0.966976471f, + (float16_t)-0.248927606f, (float16_t)-0.968522094f, + (float16_t)-0.242980180f, (float16_t)-0.970031253f, + (float16_t)-0.237023606f, (float16_t)-0.971503891f, + (float16_t)-0.231058108f, (float16_t)-0.972939952f, + (float16_t)-0.225083911f, (float16_t)-0.974339383f, + (float16_t)-0.219101240f, (float16_t)-0.975702130f, + (float16_t)-0.213110320f, (float16_t)-0.977028143f, + (float16_t)-0.207111376f, (float16_t)-0.978317371f, + (float16_t)-0.201104635f, (float16_t)-0.979569766f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.189068664f, (float16_t)-0.981963869f, + (float16_t)-0.183039888f, (float16_t)-0.983105487f, + (float16_t)-0.177004220f, (float16_t)-0.984210092f, + (float16_t)-0.170961889f, (float16_t)-0.985277642f, + (float16_t)-0.164913120f, (float16_t)-0.986308097f, + (float16_t)-0.158858143f, (float16_t)-0.987301418f, + (float16_t)-0.152797185f, (float16_t)-0.988257568f, + (float16_t)-0.146730474f, (float16_t)-0.989176510f, + (float16_t)-0.140658239f, (float16_t)-0.990058210f, + (float16_t)-0.134580709f, (float16_t)-0.990902635f, + (float16_t)-0.128498111f, (float16_t)-0.991709754f, + (float16_t)-0.122410675f, (float16_t)-0.992479535f, + (float16_t)-0.116318631f, (float16_t)-0.993211949f, + (float16_t)-0.110222207f, (float16_t)-0.993906970f, + (float16_t)-0.104121634f, (float16_t)-0.994564571f, + (float16_t)-0.098017140f, (float16_t)-0.995184727f, + (float16_t)-0.091908956f, (float16_t)-0.995767414f, + (float16_t)-0.085797312f, (float16_t)-0.996312612f, + (float16_t)-0.079682438f, (float16_t)-0.996820299f, + (float16_t)-0.073564564f, (float16_t)-0.997290457f, + (float16_t)-0.067443920f, (float16_t)-0.997723067f, + (float16_t)-0.061320736f, (float16_t)-0.998118113f, + (float16_t)-0.055195244f, (float16_t)-0.998475581f, + (float16_t)-0.049067674f, (float16_t)-0.998795456f, + (float16_t)-0.042938257f, (float16_t)-0.999077728f, + (float16_t)-0.036807223f, (float16_t)-0.999322385f, + (float16_t)-0.030674803f, (float16_t)-0.999529418f, + (float16_t)-0.024541229f, (float16_t)-0.999698819f, + (float16_t)-0.018406730f, (float16_t)-0.999830582f, + (float16_t)-0.012271538f, (float16_t)-0.999924702f, + (float16_t)-0.006135885f, (float16_t)-0.999981175f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.006135885f, (float16_t)-0.999981175f, + (float16_t)0.012271538f, (float16_t)-0.999924702f, + (float16_t)0.018406730f, (float16_t)-0.999830582f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.030674803f, (float16_t)-0.999529418f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.042938257f, (float16_t)-0.999077728f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.055195244f, (float16_t)-0.998475581f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.067443920f, (float16_t)-0.997723067f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.079682438f, (float16_t)-0.996820299f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.091908956f, (float16_t)-0.995767414f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.104121634f, (float16_t)-0.994564571f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.116318631f, (float16_t)-0.993211949f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.128498111f, (float16_t)-0.991709754f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.140658239f, (float16_t)-0.990058210f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.152797185f, (float16_t)-0.988257568f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.164913120f, (float16_t)-0.986308097f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.177004220f, (float16_t)-0.984210092f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.189068664f, (float16_t)-0.981963869f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.201104635f, (float16_t)-0.979569766f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.213110320f, (float16_t)-0.977028143f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.225083911f, (float16_t)-0.974339383f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.237023606f, (float16_t)-0.971503891f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.248927606f, (float16_t)-0.968522094f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.260794118f, (float16_t)-0.965394442f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.272621355f, (float16_t)-0.962121404f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.284407537f, (float16_t)-0.958703475f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.296150888f, (float16_t)-0.955141168f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.307849640f, (float16_t)-0.951435021f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.319502031f, (float16_t)-0.947585591f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.331106306f, (float16_t)-0.943593458f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.342660717f, (float16_t)-0.939459224f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.354163525f, (float16_t)-0.935183510f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.365612998f, (float16_t)-0.930766961f, + (float16_t)0.371317194f, (float16_t)-0.928506080f, + (float16_t)0.377007410f, (float16_t)-0.926210242f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.388345047f, (float16_t)-0.921514039f, + (float16_t)0.393992040f, (float16_t)-0.919113852f, + (float16_t)0.399624200f, (float16_t)-0.916679060f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.410843171f, (float16_t)-0.911706032f, + (float16_t)0.416429560f, (float16_t)-0.909167983f, + (float16_t)0.422000271f, (float16_t)-0.906595705f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.433093819f, (float16_t)-0.901348847f, + (float16_t)0.438616239f, (float16_t)-0.898674466f, + (float16_t)0.444122145f, (float16_t)-0.895966250f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.455083587f, (float16_t)-0.890448723f, + (float16_t)0.460538711f, (float16_t)-0.887639620f, + (float16_t)0.465976496f, (float16_t)-0.884797098f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.476799230f, (float16_t)-0.879012226f, + (float16_t)0.482183772f, (float16_t)-0.876070094f, + (float16_t)0.487550160f, (float16_t)-0.873094978f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.498227667f, (float16_t)-0.867046246f, + (float16_t)0.503538384f, (float16_t)-0.863972856f, + (float16_t)0.508830143f, (float16_t)-0.860866939f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.519355990f, (float16_t)-0.854557988f, + (float16_t)0.524589683f, (float16_t)-0.851355193f, + (float16_t)0.529803625f, (float16_t)-0.848120345f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.540171473f, (float16_t)-0.841554977f, + (float16_t)0.545324988f, (float16_t)-0.838224706f, + (float16_t)0.550457973f, (float16_t)-0.834862875f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.560661576f, (float16_t)-0.828045045f, + (float16_t)0.565731811f, (float16_t)-0.824589303f, + (float16_t)0.570780746f, (float16_t)-0.821102515f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.580813958f, (float16_t)-0.814036330f, + (float16_t)0.585797857f, (float16_t)-0.810457198f, + (float16_t)0.590759702f, (float16_t)-0.806847554f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.600616479f, (float16_t)-0.799537269f, + (float16_t)0.605511041f, (float16_t)-0.795836905f, + (float16_t)0.610382806f, (float16_t)-0.792106577f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.620057212f, (float16_t)-0.784556597f, + (float16_t)0.624859488f, (float16_t)-0.780737229f, + (float16_t)0.629638239f, (float16_t)-0.776888466f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.639124445f, (float16_t)-0.769103338f, + (float16_t)0.643831543f, (float16_t)-0.765167266f, + (float16_t)0.648514401f, (float16_t)-0.761202385f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.657806693f, (float16_t)-0.753186799f, + (float16_t)0.662415778f, (float16_t)-0.749136395f, + (float16_t)0.666999922f, (float16_t)-0.745057785f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.676092704f, (float16_t)-0.736816569f, + (float16_t)0.680600998f, (float16_t)-0.732654272f, + (float16_t)0.685083668f, (float16_t)-0.728464390f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.693971461f, (float16_t)-0.720002508f, + (float16_t)0.698376249f, (float16_t)-0.715730825f, + (float16_t)0.702754744f, (float16_t)-0.711432196f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.711432196f, (float16_t)-0.702754744f, + (float16_t)0.715730825f, (float16_t)-0.698376249f, + (float16_t)0.720002508f, (float16_t)-0.693971461f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.728464390f, (float16_t)-0.685083668f, + (float16_t)0.732654272f, (float16_t)-0.680600998f, + (float16_t)0.736816569f, (float16_t)-0.676092704f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.745057785f, (float16_t)-0.666999922f, + (float16_t)0.749136395f, (float16_t)-0.662415778f, + (float16_t)0.753186799f, (float16_t)-0.657806693f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.761202385f, (float16_t)-0.648514401f, + (float16_t)0.765167266f, (float16_t)-0.643831543f, + (float16_t)0.769103338f, (float16_t)-0.639124445f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.776888466f, (float16_t)-0.629638239f, + (float16_t)0.780737229f, (float16_t)-0.624859488f, + (float16_t)0.784556597f, (float16_t)-0.620057212f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.792106577f, (float16_t)-0.610382806f, + (float16_t)0.795836905f, (float16_t)-0.605511041f, + (float16_t)0.799537269f, (float16_t)-0.600616479f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.806847554f, (float16_t)-0.590759702f, + (float16_t)0.810457198f, (float16_t)-0.585797857f, + (float16_t)0.814036330f, (float16_t)-0.580813958f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.821102515f, (float16_t)-0.570780746f, + (float16_t)0.824589303f, (float16_t)-0.565731811f, + (float16_t)0.828045045f, (float16_t)-0.560661576f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.834862875f, (float16_t)-0.550457973f, + (float16_t)0.838224706f, (float16_t)-0.545324988f, + (float16_t)0.841554977f, (float16_t)-0.540171473f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.848120345f, (float16_t)-0.529803625f, + (float16_t)0.851355193f, (float16_t)-0.524589683f, + (float16_t)0.854557988f, (float16_t)-0.519355990f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.860866939f, (float16_t)-0.508830143f, + (float16_t)0.863972856f, (float16_t)-0.503538384f, + (float16_t)0.867046246f, (float16_t)-0.498227667f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.873094978f, (float16_t)-0.487550160f, + (float16_t)0.876070094f, (float16_t)-0.482183772f, + (float16_t)0.879012226f, (float16_t)-0.476799230f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.884797098f, (float16_t)-0.465976496f, + (float16_t)0.887639620f, (float16_t)-0.460538711f, + (float16_t)0.890448723f, (float16_t)-0.455083587f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.895966250f, (float16_t)-0.444122145f, + (float16_t)0.898674466f, (float16_t)-0.438616239f, + (float16_t)0.901348847f, (float16_t)-0.433093819f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.906595705f, (float16_t)-0.422000271f, + (float16_t)0.909167983f, (float16_t)-0.416429560f, + (float16_t)0.911706032f, (float16_t)-0.410843171f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.916679060f, (float16_t)-0.399624200f, + (float16_t)0.919113852f, (float16_t)-0.393992040f, + (float16_t)0.921514039f, (float16_t)-0.388345047f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.926210242f, (float16_t)-0.377007410f, + (float16_t)0.928506080f, (float16_t)-0.371317194f, + (float16_t)0.930766961f, (float16_t)-0.365612998f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.935183510f, (float16_t)-0.354163525f, + (float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.939459224f, (float16_t)-0.342660717f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.943593458f, (float16_t)-0.331106306f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.947585591f, (float16_t)-0.319502031f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.951435021f, (float16_t)-0.307849640f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.955141168f, (float16_t)-0.296150888f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.958703475f, (float16_t)-0.284407537f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.962121404f, (float16_t)-0.272621355f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.965394442f, (float16_t)-0.260794118f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.968522094f, (float16_t)-0.248927606f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.971503891f, (float16_t)-0.237023606f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.974339383f, (float16_t)-0.225083911f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.977028143f, (float16_t)-0.213110320f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.979569766f, (float16_t)-0.201104635f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.981963869f, (float16_t)-0.189068664f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.984210092f, (float16_t)-0.177004220f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.986308097f, (float16_t)-0.164913120f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.988257568f, (float16_t)-0.152797185f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.990058210f, (float16_t)-0.140658239f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.991709754f, (float16_t)-0.128498111f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.993211949f, (float16_t)-0.116318631f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.994564571f, (float16_t)-0.104121634f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.995767414f, (float16_t)-0.091908956f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.996820299f, (float16_t)-0.079682438f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.997723067f, (float16_t)-0.067443920f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.998475581f, (float16_t)-0.055195244f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.999077728f, (float16_t)-0.042938257f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.999529418f, (float16_t)-0.030674803f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999830582f, (float16_t)-0.018406730f, + (float16_t)0.999924702f, (float16_t)-0.012271538f, + (float16_t)0.999981175f, (float16_t)-0.006135885f +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +*
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } 
+* \par +* where N = 2048 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_2048[4096] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999995294f, (float16_t)0.003067957f, + (float16_t)0.999981175f, (float16_t)0.006135885f, + (float16_t)0.999957645f, (float16_t)0.009203755f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)0.999882347f, (float16_t)0.015339206f, + (float16_t)0.999830582f, (float16_t)0.018406730f, + (float16_t)0.999769405f, (float16_t)0.021474080f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999618822f, (float16_t)0.027608146f, + (float16_t)0.999529418f, (float16_t)0.030674803f, + (float16_t)0.999430605f, (float16_t)0.033741172f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.999204759f, (float16_t)0.039872928f, + (float16_t)0.999077728f, (float16_t)0.042938257f, + (float16_t)0.998941293f, (float16_t)0.046003182f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.998640218f, (float16_t)0.052131705f, + (float16_t)0.998475581f, (float16_t)0.055195244f, + (float16_t)0.998301545f, (float16_t)0.058258265f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.997925286f, (float16_t)0.064382631f, + (float16_t)0.997723067f, (float16_t)0.067443920f, + (float16_t)0.997511456f, (float16_t)0.070504573f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.997060070f, (float16_t)0.076623861f, + (float16_t)0.996820299f, (float16_t)0.079682438f, + (float16_t)0.996571146f, (float16_t)0.082740265f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.996044701f, (float16_t)0.088853553f, + (float16_t)0.995767414f, (float16_t)0.091908956f, + (float16_t)0.995480755f, (float16_t)0.094963495f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.994879331f, (float16_t)0.101069863f, + (float16_t)0.994564571f, (float16_t)0.104121634f, + (float16_t)0.994240449f, (float16_t)0.107172425f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.993564136f, (float16_t)0.113270952f, + (float16_t)0.993211949f, (float16_t)0.116318631f, + (float16_t)0.992850414f, (float16_t)0.119365215f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.992099313f, (float16_t)0.125454983f, + (float16_t)0.991709754f, (float16_t)0.128498111f, + (float16_t)0.991310860f, (float16_t)0.131540029f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.990485084f, (float16_t)0.137620122f, + (float16_t)0.990058210f, (float16_t)0.140658239f, + (float16_t)0.989622017f, (float16_t)0.143695033f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.988721692f, (float16_t)0.149764535f, + (float16_t)0.988257568f, (float16_t)0.152797185f, + (float16_t)0.987784142f, (float16_t)0.155828398f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.986809402f, (float16_t)0.161886394f, + (float16_t)0.986308097f, (float16_t)0.164913120f, + (float16_t)0.985797509f, (float16_t)0.167938295f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.984748502f, (float16_t)0.173983873f, + (float16_t)0.984210092f, (float16_t)0.177004220f, + (float16_t)0.983662419f, (float16_t)0.180022901f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.982539302f, (float16_t)0.186055152f, + (float16_t)0.981963869f, (float16_t)0.189068664f, + (float16_t)0.981379193f, (float16_t)0.192080397f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.980182136f, (float16_t)0.198098411f, + (float16_t)0.979569766f, (float16_t)0.201104635f, + (float16_t)0.978948175f, (float16_t)0.204108966f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.977677358f, (float16_t)0.210111837f, + (float16_t)0.977028143f, (float16_t)0.213110320f, + (float16_t)0.976369731f, (float16_t)0.216106797f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.975025345f, (float16_t)0.222093621f, + (float16_t)0.974339383f, (float16_t)0.225083911f, + (float16_t)0.973644250f, (float16_t)0.228072083f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.972226497f, (float16_t)0.234041959f, + (float16_t)0.971503891f, (float16_t)0.237023606f, + (float16_t)0.970772141f, (float16_t)0.240003022f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.969281235f, (float16_t)0.245955050f, + (float16_t)0.968522094f, (float16_t)0.248927606f, + (float16_t)0.967753837f, (float16_t)0.251897818f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.966190003f, (float16_t)0.257831102f, + (float16_t)0.965394442f, (float16_t)0.260794118f, + (float16_t)0.964589793f, (float16_t)0.263754679f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.962953267f, (float16_t)0.269668326f, + (float16_t)0.962121404f, (float16_t)0.272621355f, + (float16_t)0.961280486f, (float16_t)0.275571819f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.959571513f, (float16_t)0.281464938f, + (float16_t)0.958703475f, (float16_t)0.284407537f, + (float16_t)0.957826413f, (float16_t)0.287347460f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.956045251f, (float16_t)0.293219163f, + (float16_t)0.955141168f, (float16_t)0.296150888f, + (float16_t)0.954228095f, (float16_t)0.299079826f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.952375013f, (float16_t)0.304929230f, + (float16_t)0.951435021f, (float16_t)0.307849640f, + (float16_t)0.950486074f, (float16_t)0.310767153f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.948561350f, (float16_t)0.316593376f, + (float16_t)0.947585591f, (float16_t)0.319502031f, + (float16_t)0.946600913f, (float16_t)0.322407679f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.944604837f, (float16_t)0.328209844f, + (float16_t)0.943593458f, (float16_t)0.331106306f, + (float16_t)0.942573198f, (float16_t)0.333999651f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.940506071f, (float16_t)0.339776884f, + (float16_t)0.939459224f, (float16_t)0.342660717f, + (float16_t)0.938403534f, (float16_t)0.345541325f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.936265667f, (float16_t)0.351292756f, + (float16_t)0.935183510f, (float16_t)0.354163525f, + (float16_t)0.934092550f, (float16_t)0.357030961f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.931884266f, (float16_t)0.362755724f, + (float16_t)0.930766961f, (float16_t)0.365612998f, + (float16_t)0.929640896f, (float16_t)0.368466830f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.927362526f, (float16_t)0.374164063f, + (float16_t)0.926210242f, (float16_t)0.377007410f, + (float16_t)0.925049241f, (float16_t)0.379847209f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.922701128f, (float16_t)0.385516054f, + (float16_t)0.921514039f, (float16_t)0.388345047f, + (float16_t)0.920318277f, (float16_t)0.391170384f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.917900776f, (float16_t)0.396809987f, + (float16_t)0.916679060f, (float16_t)0.399624200f, + (float16_t)0.915448716f, (float16_t)0.402434651f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.912962190f, (float16_t)0.408044163f, + (float16_t)0.911706032f, (float16_t)0.410843171f, + (float16_t)0.910441292f, (float16_t)0.413638312f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.907886116f, (float16_t)0.419216888f, + (float16_t)0.906595705f, (float16_t)0.422000271f, + (float16_t)0.905296759f, (float16_t)0.424779681f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.902673318f, (float16_t)0.430326481f, + (float16_t)0.901348847f, (float16_t)0.433093819f, + (float16_t)0.900015892f, (float16_t)0.435857080f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.897324581f, (float16_t)0.441371269f, + (float16_t)0.895966250f, (float16_t)0.444122145f, + (float16_t)0.894599486f, (float16_t)0.446868840f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.891840709f, (float16_t)0.452349587f, + (float16_t)0.890448723f, (float16_t)0.455083587f, + (float16_t)0.889048356f, (float16_t)0.457813304f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.886222530f, (float16_t)0.463259784f, + (float16_t)0.884797098f, (float16_t)0.465976496f, + (float16_t)0.883363339f, (float16_t)0.468688822f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.880470889f, (float16_t)0.474100215f, + (float16_t)0.879012226f, (float16_t)0.476799230f, + (float16_t)0.877545290f, (float16_t)0.479493758f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.874586652f, (float16_t)0.484869248f, + (float16_t)0.873094978f, (float16_t)0.487550160f, + (float16_t)0.871595087f, (float16_t)0.490226483f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.868570706f, (float16_t)0.495565262f, + (float16_t)0.867046246f, (float16_t)0.498227667f, + (float16_t)0.865513624f, (float16_t)0.500885383f, + (float16_t)0.863972856f, (float16_t)0.503538384f, + (float16_t)0.862423956f, (float16_t)0.506186645f, + (float16_t)0.860866939f, (float16_t)0.508830143f, + (float16_t)0.859301818f, (float16_t)0.511468850f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.856147328f, (float16_t)0.516731799f, + (float16_t)0.854557988f, (float16_t)0.519355990f, + (float16_t)0.852960605f, (float16_t)0.521975293f, + (float16_t)0.851355193f, (float16_t)0.524589683f, + (float16_t)0.849741768f, (float16_t)0.527199135f, + (float16_t)0.848120345f, (float16_t)0.529803625f, + (float16_t)0.846490939f, (float16_t)0.532403128f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.843208240f, (float16_t)0.537587076f, + (float16_t)0.841554977f, (float16_t)0.540171473f, + (float16_t)0.839893794f, (float16_t)0.542750785f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.836547727f, (float16_t)0.547894059f, + (float16_t)0.834862875f, (float16_t)0.550457973f, + (float16_t)0.833170165f, (float16_t)0.553016706f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.829761234f, (float16_t)0.558118531f, + (float16_t)0.828045045f, (float16_t)0.560661576f, + (float16_t)0.826321063f, (float16_t)0.563199344f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.822849781f, (float16_t)0.568258953f, + (float16_t)0.821102515f, (float16_t)0.570780746f, + (float16_t)0.819347520f, (float16_t)0.573297167f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.815814411f, (float16_t)0.578313796f, + (float16_t)0.814036330f, (float16_t)0.580813958f, + (float16_t)0.812250587f, (float16_t)0.583308653f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.808656182f, (float16_t)0.588281548f, + (float16_t)0.806847554f, (float16_t)0.590759702f, + (float16_t)0.805031331f, (float16_t)0.593232295f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.801376172f, (float16_t)0.598160707f, + (float16_t)0.799537269f, (float16_t)0.600616479f, + (float16_t)0.797690841f, (float16_t)0.603066599f, + (float16_t)0.795836905f, (float16_t)0.605511041f, + (float16_t)0.793975478f, (float16_t)0.607949785f, + (float16_t)0.792106577f, (float16_t)0.610382806f, + (float16_t)0.790230221f, (float16_t)0.612810082f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.786455214f, (float16_t)0.617647308f, + (float16_t)0.784556597f, (float16_t)0.620057212f, + (float16_t)0.782650596f, (float16_t)0.622461279f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.778816512f, (float16_t)0.627251815f, + (float16_t)0.776888466f, (float16_t)0.629638239f, + (float16_t)0.774953107f, (float16_t)0.632018736f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.771060524f, (float16_t)0.636761861f, + (float16_t)0.769103338f, (float16_t)0.639124445f, + (float16_t)0.767138912f, (float16_t)0.641481013f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.763188417f, (float16_t)0.646176013f, + (float16_t)0.761202385f, (float16_t)0.648514401f, + (float16_t)0.759209189f, (float16_t)0.650846685f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.755201377f, (float16_t)0.655492853f, + (float16_t)0.753186799f, (float16_t)0.657806693f, + (float16_t)0.751165132f, (float16_t)0.660114342f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.747100606f, (float16_t)0.664710978f, + (float16_t)0.745057785f, (float16_t)0.666999922f, + (float16_t)0.743007952f, (float16_t)0.669282588f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.738887324f, (float16_t)0.673829000f, + (float16_t)0.736816569f, (float16_t)0.676092704f, + (float16_t)0.734738878f, (float16_t)0.678350043f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.730562769f, (float16_t)0.682845546f, + (float16_t)0.728464390f, (float16_t)0.685083668f, + (float16_t)0.726359155f, (float16_t)0.687315341f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.722128194f, (float16_t)0.691759258f, + (float16_t)0.720002508f, (float16_t)0.693971461f, + (float16_t)0.717870045f, (float16_t)0.696177131f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.713584869f, (float16_t)0.700568794f, + (float16_t)0.711432196f, (float16_t)0.702754744f, + (float16_t)0.709272826f, (float16_t)0.704934080f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.704934080f, (float16_t)0.709272826f, + (float16_t)0.702754744f, (float16_t)0.711432196f, + (float16_t)0.700568794f, (float16_t)0.713584869f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.696177131f, (float16_t)0.717870045f, + (float16_t)0.693971461f, (float16_t)0.720002508f, + (float16_t)0.691759258f, (float16_t)0.722128194f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.687315341f, (float16_t)0.726359155f, + (float16_t)0.685083668f, (float16_t)0.728464390f, + (float16_t)0.682845546f, (float16_t)0.730562769f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.678350043f, (float16_t)0.734738878f, + (float16_t)0.676092704f, (float16_t)0.736816569f, + (float16_t)0.673829000f, (float16_t)0.738887324f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.669282588f, (float16_t)0.743007952f, + (float16_t)0.666999922f, (float16_t)0.745057785f, + (float16_t)0.664710978f, (float16_t)0.747100606f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.660114342f, (float16_t)0.751165132f, + (float16_t)0.657806693f, (float16_t)0.753186799f, + (float16_t)0.655492853f, (float16_t)0.755201377f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.650846685f, (float16_t)0.759209189f, + (float16_t)0.648514401f, (float16_t)0.761202385f, + (float16_t)0.646176013f, (float16_t)0.763188417f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.641481013f, (float16_t)0.767138912f, + (float16_t)0.639124445f, (float16_t)0.769103338f, + (float16_t)0.636761861f, (float16_t)0.771060524f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.632018736f, (float16_t)0.774953107f, + (float16_t)0.629638239f, (float16_t)0.776888466f, + (float16_t)0.627251815f, (float16_t)0.778816512f, + (float16_t)0.624859488f, (float16_t)0.780737229f, + (float16_t)0.622461279f, (float16_t)0.782650596f, + (float16_t)0.620057212f, (float16_t)0.784556597f, + (float16_t)0.617647308f, (float16_t)0.786455214f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.612810082f, (float16_t)0.790230221f, + (float16_t)0.610382806f, (float16_t)0.792106577f, + (float16_t)0.607949785f, (float16_t)0.793975478f, + (float16_t)0.605511041f, (float16_t)0.795836905f, + (float16_t)0.603066599f, (float16_t)0.797690841f, + (float16_t)0.600616479f, (float16_t)0.799537269f, + (float16_t)0.598160707f, (float16_t)0.801376172f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.593232295f, (float16_t)0.805031331f, + (float16_t)0.590759702f, (float16_t)0.806847554f, + (float16_t)0.588281548f, (float16_t)0.808656182f, + (float16_t)0.585797857f, (float16_t)0.810457198f, + (float16_t)0.583308653f, (float16_t)0.812250587f, + (float16_t)0.580813958f, (float16_t)0.814036330f, + (float16_t)0.578313796f, (float16_t)0.815814411f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.573297167f, (float16_t)0.819347520f, + (float16_t)0.570780746f, (float16_t)0.821102515f, + (float16_t)0.568258953f, (float16_t)0.822849781f, + (float16_t)0.565731811f, (float16_t)0.824589303f, + (float16_t)0.563199344f, (float16_t)0.826321063f, + (float16_t)0.560661576f, (float16_t)0.828045045f, + (float16_t)0.558118531f, (float16_t)0.829761234f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.553016706f, (float16_t)0.833170165f, + (float16_t)0.550457973f, (float16_t)0.834862875f, + (float16_t)0.547894059f, (float16_t)0.836547727f, + (float16_t)0.545324988f, (float16_t)0.838224706f, + (float16_t)0.542750785f, (float16_t)0.839893794f, + (float16_t)0.540171473f, (float16_t)0.841554977f, + (float16_t)0.537587076f, (float16_t)0.843208240f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.532403128f, (float16_t)0.846490939f, + (float16_t)0.529803625f, (float16_t)0.848120345f, + (float16_t)0.527199135f, (float16_t)0.849741768f, + (float16_t)0.524589683f, (float16_t)0.851355193f, + (float16_t)0.521975293f, (float16_t)0.852960605f, + (float16_t)0.519355990f, (float16_t)0.854557988f, + (float16_t)0.516731799f, (float16_t)0.856147328f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.511468850f, (float16_t)0.859301818f, + (float16_t)0.508830143f, (float16_t)0.860866939f, + (float16_t)0.506186645f, (float16_t)0.862423956f, + (float16_t)0.503538384f, (float16_t)0.863972856f, + (float16_t)0.500885383f, (float16_t)0.865513624f, + (float16_t)0.498227667f, (float16_t)0.867046246f, + (float16_t)0.495565262f, (float16_t)0.868570706f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.490226483f, (float16_t)0.871595087f, + (float16_t)0.487550160f, (float16_t)0.873094978f, + (float16_t)0.484869248f, (float16_t)0.874586652f, + (float16_t)0.482183772f, (float16_t)0.876070094f, + (float16_t)0.479493758f, (float16_t)0.877545290f, + (float16_t)0.476799230f, (float16_t)0.879012226f, + (float16_t)0.474100215f, (float16_t)0.880470889f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.468688822f, (float16_t)0.883363339f, + (float16_t)0.465976496f, (float16_t)0.884797098f, + (float16_t)0.463259784f, (float16_t)0.886222530f, + (float16_t)0.460538711f, (float16_t)0.887639620f, + (float16_t)0.457813304f, (float16_t)0.889048356f, + (float16_t)0.455083587f, (float16_t)0.890448723f, + (float16_t)0.452349587f, (float16_t)0.891840709f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.446868840f, (float16_t)0.894599486f, + (float16_t)0.444122145f, (float16_t)0.895966250f, + (float16_t)0.441371269f, (float16_t)0.897324581f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.435857080f, (float16_t)0.900015892f, + (float16_t)0.433093819f, (float16_t)0.901348847f, + (float16_t)0.430326481f, (float16_t)0.902673318f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.424779681f, (float16_t)0.905296759f, + (float16_t)0.422000271f, (float16_t)0.906595705f, + (float16_t)0.419216888f, (float16_t)0.907886116f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.413638312f, (float16_t)0.910441292f, + (float16_t)0.410843171f, (float16_t)0.911706032f, + (float16_t)0.408044163f, (float16_t)0.912962190f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.402434651f, (float16_t)0.915448716f, + (float16_t)0.399624200f, (float16_t)0.916679060f, + (float16_t)0.396809987f, (float16_t)0.917900776f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.391170384f, (float16_t)0.920318277f, + (float16_t)0.388345047f, (float16_t)0.921514039f, + (float16_t)0.385516054f, (float16_t)0.922701128f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.379847209f, (float16_t)0.925049241f, + (float16_t)0.377007410f, (float16_t)0.926210242f, + (float16_t)0.374164063f, (float16_t)0.927362526f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.368466830f, (float16_t)0.929640896f, + (float16_t)0.365612998f, (float16_t)0.930766961f, + (float16_t)0.362755724f, (float16_t)0.931884266f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.357030961f, (float16_t)0.934092550f, + (float16_t)0.354163525f, (float16_t)0.935183510f, + (float16_t)0.351292756f, (float16_t)0.936265667f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.345541325f, (float16_t)0.938403534f, + (float16_t)0.342660717f, (float16_t)0.939459224f, + (float16_t)0.339776884f, (float16_t)0.940506071f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.333999651f, (float16_t)0.942573198f, + (float16_t)0.331106306f, (float16_t)0.943593458f, + (float16_t)0.328209844f, (float16_t)0.944604837f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.322407679f, (float16_t)0.946600913f, + (float16_t)0.319502031f, (float16_t)0.947585591f, + (float16_t)0.316593376f, (float16_t)0.948561350f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.310767153f, (float16_t)0.950486074f, + (float16_t)0.307849640f, (float16_t)0.951435021f, + (float16_t)0.304929230f, (float16_t)0.952375013f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.299079826f, (float16_t)0.954228095f, + (float16_t)0.296150888f, (float16_t)0.955141168f, + (float16_t)0.293219163f, (float16_t)0.956045251f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.287347460f, (float16_t)0.957826413f, + (float16_t)0.284407537f, (float16_t)0.958703475f, + (float16_t)0.281464938f, (float16_t)0.959571513f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.275571819f, (float16_t)0.961280486f, + (float16_t)0.272621355f, (float16_t)0.962121404f, + (float16_t)0.269668326f, (float16_t)0.962953267f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.263754679f, (float16_t)0.964589793f, + (float16_t)0.260794118f, (float16_t)0.965394442f, + (float16_t)0.257831102f, (float16_t)0.966190003f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.251897818f, (float16_t)0.967753837f, + (float16_t)0.248927606f, (float16_t)0.968522094f, + (float16_t)0.245955050f, (float16_t)0.969281235f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.240003022f, (float16_t)0.970772141f, + (float16_t)0.237023606f, (float16_t)0.971503891f, + (float16_t)0.234041959f, (float16_t)0.972226497f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.228072083f, (float16_t)0.973644250f, + (float16_t)0.225083911f, (float16_t)0.974339383f, + (float16_t)0.222093621f, (float16_t)0.975025345f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.216106797f, (float16_t)0.976369731f, + (float16_t)0.213110320f, (float16_t)0.977028143f, + (float16_t)0.210111837f, (float16_t)0.977677358f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.204108966f, (float16_t)0.978948175f, + (float16_t)0.201104635f, (float16_t)0.979569766f, + (float16_t)0.198098411f, (float16_t)0.980182136f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.192080397f, (float16_t)0.981379193f, + (float16_t)0.189068664f, (float16_t)0.981963869f, + (float16_t)0.186055152f, (float16_t)0.982539302f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.180022901f, (float16_t)0.983662419f, + (float16_t)0.177004220f, (float16_t)0.984210092f, + (float16_t)0.173983873f, (float16_t)0.984748502f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.167938295f, (float16_t)0.985797509f, + (float16_t)0.164913120f, (float16_t)0.986308097f, + (float16_t)0.161886394f, (float16_t)0.986809402f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.155828398f, (float16_t)0.987784142f, + (float16_t)0.152797185f, (float16_t)0.988257568f, + (float16_t)0.149764535f, (float16_t)0.988721692f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.143695033f, (float16_t)0.989622017f, + (float16_t)0.140658239f, (float16_t)0.990058210f, + (float16_t)0.137620122f, (float16_t)0.990485084f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.131540029f, (float16_t)0.991310860f, + (float16_t)0.128498111f, (float16_t)0.991709754f, + (float16_t)0.125454983f, (float16_t)0.992099313f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.119365215f, (float16_t)0.992850414f, + (float16_t)0.116318631f, (float16_t)0.993211949f, + (float16_t)0.113270952f, (float16_t)0.993564136f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.107172425f, (float16_t)0.994240449f, + (float16_t)0.104121634f, (float16_t)0.994564571f, + (float16_t)0.101069863f, (float16_t)0.994879331f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.094963495f, (float16_t)0.995480755f, + (float16_t)0.091908956f, (float16_t)0.995767414f, + (float16_t)0.088853553f, (float16_t)0.996044701f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.082740265f, (float16_t)0.996571146f, + (float16_t)0.079682438f, (float16_t)0.996820299f, + (float16_t)0.076623861f, (float16_t)0.997060070f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.070504573f, (float16_t)0.997511456f, + (float16_t)0.067443920f, (float16_t)0.997723067f, + (float16_t)0.064382631f, (float16_t)0.997925286f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.058258265f, (float16_t)0.998301545f, + (float16_t)0.055195244f, (float16_t)0.998475581f, + (float16_t)0.052131705f, (float16_t)0.998640218f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.046003182f, (float16_t)0.998941293f, + (float16_t)0.042938257f, (float16_t)0.999077728f, + (float16_t)0.039872928f, (float16_t)0.999204759f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.033741172f, (float16_t)0.999430605f, + (float16_t)0.030674803f, (float16_t)0.999529418f, + (float16_t)0.027608146f, (float16_t)0.999618822f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.021474080f, (float16_t)0.999769405f, + (float16_t)0.018406730f, (float16_t)0.999830582f, + (float16_t)0.015339206f, (float16_t)0.999882347f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.009203755f, (float16_t)0.999957645f, + (float16_t)0.006135885f, (float16_t)0.999981175f, + (float16_t)0.003067957f, (float16_t)0.999995294f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.003067957f, (float16_t)0.999995294f, + (float16_t)-0.006135885f, (float16_t)0.999981175f, + (float16_t)-0.009203755f, (float16_t)0.999957645f, + (float16_t)-0.012271538f, (float16_t)0.999924702f, + (float16_t)-0.015339206f, (float16_t)0.999882347f, + (float16_t)-0.018406730f, (float16_t)0.999830582f, + (float16_t)-0.021474080f, (float16_t)0.999769405f, + (float16_t)-0.024541229f, (float16_t)0.999698819f, + (float16_t)-0.027608146f, (float16_t)0.999618822f, + (float16_t)-0.030674803f, (float16_t)0.999529418f, + (float16_t)-0.033741172f, (float16_t)0.999430605f, + (float16_t)-0.036807223f, (float16_t)0.999322385f, + (float16_t)-0.039872928f, (float16_t)0.999204759f, + (float16_t)-0.042938257f, (float16_t)0.999077728f, + (float16_t)-0.046003182f, (float16_t)0.998941293f, + (float16_t)-0.049067674f, (float16_t)0.998795456f, + (float16_t)-0.052131705f, (float16_t)0.998640218f, + (float16_t)-0.055195244f, (float16_t)0.998475581f, + (float16_t)-0.058258265f, (float16_t)0.998301545f, + (float16_t)-0.061320736f, (float16_t)0.998118113f, + (float16_t)-0.064382631f, (float16_t)0.997925286f, + (float16_t)-0.067443920f, (float16_t)0.997723067f, + (float16_t)-0.070504573f, (float16_t)0.997511456f, + (float16_t)-0.073564564f, (float16_t)0.997290457f, + (float16_t)-0.076623861f, (float16_t)0.997060070f, + (float16_t)-0.079682438f, (float16_t)0.996820299f, + (float16_t)-0.082740265f, (float16_t)0.996571146f, + (float16_t)-0.085797312f, (float16_t)0.996312612f, + (float16_t)-0.088853553f, (float16_t)0.996044701f, + (float16_t)-0.091908956f, (float16_t)0.995767414f, + (float16_t)-0.094963495f, (float16_t)0.995480755f, + (float16_t)-0.098017140f, (float16_t)0.995184727f, + (float16_t)-0.101069863f, (float16_t)0.994879331f, + (float16_t)-0.104121634f, (float16_t)0.994564571f, + (float16_t)-0.107172425f, (float16_t)0.994240449f, + (float16_t)-0.110222207f, (float16_t)0.993906970f, + (float16_t)-0.113270952f, (float16_t)0.993564136f, + (float16_t)-0.116318631f, (float16_t)0.993211949f, + (float16_t)-0.119365215f, (float16_t)0.992850414f, + (float16_t)-0.122410675f, (float16_t)0.992479535f, + (float16_t)-0.125454983f, (float16_t)0.992099313f, + (float16_t)-0.128498111f, (float16_t)0.991709754f, + (float16_t)-0.131540029f, (float16_t)0.991310860f, + (float16_t)-0.134580709f, (float16_t)0.990902635f, + (float16_t)-0.137620122f, (float16_t)0.990485084f, + (float16_t)-0.140658239f, (float16_t)0.990058210f, + (float16_t)-0.143695033f, (float16_t)0.989622017f, + (float16_t)-0.146730474f, (float16_t)0.989176510f, + (float16_t)-0.149764535f, (float16_t)0.988721692f, + (float16_t)-0.152797185f, (float16_t)0.988257568f, + (float16_t)-0.155828398f, (float16_t)0.987784142f, + (float16_t)-0.158858143f, (float16_t)0.987301418f, + (float16_t)-0.161886394f, (float16_t)0.986809402f, + (float16_t)-0.164913120f, (float16_t)0.986308097f, + (float16_t)-0.167938295f, (float16_t)0.985797509f, + (float16_t)-0.170961889f, (float16_t)0.985277642f, + (float16_t)-0.173983873f, (float16_t)0.984748502f, + (float16_t)-0.177004220f, (float16_t)0.984210092f, + (float16_t)-0.180022901f, (float16_t)0.983662419f, + (float16_t)-0.183039888f, (float16_t)0.983105487f, + (float16_t)-0.186055152f, (float16_t)0.982539302f, + (float16_t)-0.189068664f, (float16_t)0.981963869f, + (float16_t)-0.192080397f, (float16_t)0.981379193f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.198098411f, (float16_t)0.980182136f, + (float16_t)-0.201104635f, (float16_t)0.979569766f, + (float16_t)-0.204108966f, (float16_t)0.978948175f, + (float16_t)-0.207111376f, (float16_t)0.978317371f, + (float16_t)-0.210111837f, (float16_t)0.977677358f, + (float16_t)-0.213110320f, (float16_t)0.977028143f, + (float16_t)-0.216106797f, (float16_t)0.976369731f, + (float16_t)-0.219101240f, (float16_t)0.975702130f, + (float16_t)-0.222093621f, (float16_t)0.975025345f, + (float16_t)-0.225083911f, (float16_t)0.974339383f, + (float16_t)-0.228072083f, (float16_t)0.973644250f, + (float16_t)-0.231058108f, (float16_t)0.972939952f, + (float16_t)-0.234041959f, (float16_t)0.972226497f, + (float16_t)-0.237023606f, (float16_t)0.971503891f, + (float16_t)-0.240003022f, (float16_t)0.970772141f, + (float16_t)-0.242980180f, (float16_t)0.970031253f, + (float16_t)-0.245955050f, (float16_t)0.969281235f, + (float16_t)-0.248927606f, (float16_t)0.968522094f, + (float16_t)-0.251897818f, (float16_t)0.967753837f, + (float16_t)-0.254865660f, (float16_t)0.966976471f, + (float16_t)-0.257831102f, (float16_t)0.966190003f, + (float16_t)-0.260794118f, (float16_t)0.965394442f, + (float16_t)-0.263754679f, (float16_t)0.964589793f, + (float16_t)-0.266712757f, (float16_t)0.963776066f, + (float16_t)-0.269668326f, (float16_t)0.962953267f, + (float16_t)-0.272621355f, (float16_t)0.962121404f, + (float16_t)-0.275571819f, (float16_t)0.961280486f, + (float16_t)-0.278519689f, (float16_t)0.960430519f, + (float16_t)-0.281464938f, (float16_t)0.959571513f, + (float16_t)-0.284407537f, (float16_t)0.958703475f, + (float16_t)-0.287347460f, (float16_t)0.957826413f, + (float16_t)-0.290284677f, (float16_t)0.956940336f, + (float16_t)-0.293219163f, (float16_t)0.956045251f, + (float16_t)-0.296150888f, (float16_t)0.955141168f, + (float16_t)-0.299079826f, (float16_t)0.954228095f, + (float16_t)-0.302005949f, (float16_t)0.953306040f, + (float16_t)-0.304929230f, (float16_t)0.952375013f, + (float16_t)-0.307849640f, (float16_t)0.951435021f, + (float16_t)-0.310767153f, (float16_t)0.950486074f, + (float16_t)-0.313681740f, (float16_t)0.949528181f, + (float16_t)-0.316593376f, (float16_t)0.948561350f, + (float16_t)-0.319502031f, (float16_t)0.947585591f, + (float16_t)-0.322407679f, (float16_t)0.946600913f, + (float16_t)-0.325310292f, (float16_t)0.945607325f, + (float16_t)-0.328209844f, (float16_t)0.944604837f, + (float16_t)-0.331106306f, (float16_t)0.943593458f, + (float16_t)-0.333999651f, (float16_t)0.942573198f, + (float16_t)-0.336889853f, (float16_t)0.941544065f, + (float16_t)-0.339776884f, (float16_t)0.940506071f, + (float16_t)-0.342660717f, (float16_t)0.939459224f, + (float16_t)-0.345541325f, (float16_t)0.938403534f, + (float16_t)-0.348418680f, (float16_t)0.937339012f, + (float16_t)-0.351292756f, (float16_t)0.936265667f, + (float16_t)-0.354163525f, (float16_t)0.935183510f, + (float16_t)-0.357030961f, (float16_t)0.934092550f, + (float16_t)-0.359895037f, (float16_t)0.932992799f, + (float16_t)-0.362755724f, (float16_t)0.931884266f, + (float16_t)-0.365612998f, (float16_t)0.930766961f, + (float16_t)-0.368466830f, (float16_t)0.929640896f, + (float16_t)-0.371317194f, (float16_t)0.928506080f, + (float16_t)-0.374164063f, (float16_t)0.927362526f, + (float16_t)-0.377007410f, (float16_t)0.926210242f, + (float16_t)-0.379847209f, (float16_t)0.925049241f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.385516054f, (float16_t)0.922701128f, + (float16_t)-0.388345047f, (float16_t)0.921514039f, + (float16_t)-0.391170384f, (float16_t)0.920318277f, + (float16_t)-0.393992040f, (float16_t)0.919113852f, + (float16_t)-0.396809987f, (float16_t)0.917900776f, + (float16_t)-0.399624200f, (float16_t)0.916679060f, + (float16_t)-0.402434651f, (float16_t)0.915448716f, + (float16_t)-0.405241314f, (float16_t)0.914209756f, + (float16_t)-0.408044163f, (float16_t)0.912962190f, + (float16_t)-0.410843171f, (float16_t)0.911706032f, + (float16_t)-0.413638312f, (float16_t)0.910441292f, + (float16_t)-0.416429560f, (float16_t)0.909167983f, + (float16_t)-0.419216888f, (float16_t)0.907886116f, + (float16_t)-0.422000271f, (float16_t)0.906595705f, + (float16_t)-0.424779681f, (float16_t)0.905296759f, + (float16_t)-0.427555093f, (float16_t)0.903989293f, + (float16_t)-0.430326481f, (float16_t)0.902673318f, + (float16_t)-0.433093819f, (float16_t)0.901348847f, + (float16_t)-0.435857080f, (float16_t)0.900015892f, + (float16_t)-0.438616239f, (float16_t)0.898674466f, + (float16_t)-0.441371269f, (float16_t)0.897324581f, + (float16_t)-0.444122145f, (float16_t)0.895966250f, + (float16_t)-0.446868840f, (float16_t)0.894599486f, + (float16_t)-0.449611330f, (float16_t)0.893224301f, + (float16_t)-0.452349587f, (float16_t)0.891840709f, + (float16_t)-0.455083587f, (float16_t)0.890448723f, + (float16_t)-0.457813304f, (float16_t)0.889048356f, + (float16_t)-0.460538711f, (float16_t)0.887639620f, + (float16_t)-0.463259784f, (float16_t)0.886222530f, + (float16_t)-0.465976496f, (float16_t)0.884797098f, + (float16_t)-0.468688822f, (float16_t)0.883363339f, + (float16_t)-0.471396737f, (float16_t)0.881921264f, + (float16_t)-0.474100215f, (float16_t)0.880470889f, + (float16_t)-0.476799230f, (float16_t)0.879012226f, + (float16_t)-0.479493758f, (float16_t)0.877545290f, + (float16_t)-0.482183772f, (float16_t)0.876070094f, + (float16_t)-0.484869248f, (float16_t)0.874586652f, + (float16_t)-0.487550160f, (float16_t)0.873094978f, + (float16_t)-0.490226483f, (float16_t)0.871595087f, + (float16_t)-0.492898192f, (float16_t)0.870086991f, + (float16_t)-0.495565262f, (float16_t)0.868570706f, + (float16_t)-0.498227667f, (float16_t)0.867046246f, + (float16_t)-0.500885383f, (float16_t)0.865513624f, + (float16_t)-0.503538384f, (float16_t)0.863972856f, + (float16_t)-0.506186645f, (float16_t)0.862423956f, + (float16_t)-0.508830143f, (float16_t)0.860866939f, + (float16_t)-0.511468850f, (float16_t)0.859301818f, + (float16_t)-0.514102744f, (float16_t)0.857728610f, + (float16_t)-0.516731799f, (float16_t)0.856147328f, + (float16_t)-0.519355990f, (float16_t)0.854557988f, + (float16_t)-0.521975293f, (float16_t)0.852960605f, + (float16_t)-0.524589683f, (float16_t)0.851355193f, + (float16_t)-0.527199135f, (float16_t)0.849741768f, + (float16_t)-0.529803625f, (float16_t)0.848120345f, + (float16_t)-0.532403128f, (float16_t)0.846490939f, + (float16_t)-0.534997620f, (float16_t)0.844853565f, + (float16_t)-0.537587076f, (float16_t)0.843208240f, + (float16_t)-0.540171473f, (float16_t)0.841554977f, + (float16_t)-0.542750785f, (float16_t)0.839893794f, + (float16_t)-0.545324988f, (float16_t)0.838224706f, + (float16_t)-0.547894059f, (float16_t)0.836547727f, + (float16_t)-0.550457973f, (float16_t)0.834862875f, + (float16_t)-0.553016706f, (float16_t)0.833170165f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.558118531f, (float16_t)0.829761234f, + (float16_t)-0.560661576f, (float16_t)0.828045045f, + (float16_t)-0.563199344f, (float16_t)0.826321063f, + (float16_t)-0.565731811f, (float16_t)0.824589303f, + (float16_t)-0.568258953f, (float16_t)0.822849781f, + (float16_t)-0.570780746f, (float16_t)0.821102515f, + (float16_t)-0.573297167f, (float16_t)0.819347520f, + (float16_t)-0.575808191f, (float16_t)0.817584813f, + (float16_t)-0.578313796f, (float16_t)0.815814411f, + (float16_t)-0.580813958f, (float16_t)0.814036330f, + (float16_t)-0.583308653f, (float16_t)0.812250587f, + (float16_t)-0.585797857f, (float16_t)0.810457198f, + (float16_t)-0.588281548f, (float16_t)0.808656182f, + (float16_t)-0.590759702f, (float16_t)0.806847554f, + (float16_t)-0.593232295f, (float16_t)0.805031331f, + (float16_t)-0.595699304f, (float16_t)0.803207531f, + (float16_t)-0.598160707f, (float16_t)0.801376172f, + (float16_t)-0.600616479f, (float16_t)0.799537269f, + (float16_t)-0.603066599f, (float16_t)0.797690841f, + (float16_t)-0.605511041f, (float16_t)0.795836905f, + (float16_t)-0.607949785f, (float16_t)0.793975478f, + (float16_t)-0.610382806f, (float16_t)0.792106577f, + (float16_t)-0.612810082f, (float16_t)0.790230221f, + (float16_t)-0.615231591f, (float16_t)0.788346428f, + (float16_t)-0.617647308f, (float16_t)0.786455214f, + (float16_t)-0.620057212f, (float16_t)0.784556597f, + (float16_t)-0.622461279f, (float16_t)0.782650596f, + (float16_t)-0.624859488f, (float16_t)0.780737229f, + (float16_t)-0.627251815f, (float16_t)0.778816512f, + (float16_t)-0.629638239f, (float16_t)0.776888466f, + (float16_t)-0.632018736f, (float16_t)0.774953107f, + (float16_t)-0.634393284f, (float16_t)0.773010453f, + (float16_t)-0.636761861f, (float16_t)0.771060524f, + (float16_t)-0.639124445f, (float16_t)0.769103338f, + (float16_t)-0.641481013f, (float16_t)0.767138912f, + (float16_t)-0.643831543f, (float16_t)0.765167266f, + (float16_t)-0.646176013f, (float16_t)0.763188417f, + (float16_t)-0.648514401f, (float16_t)0.761202385f, + (float16_t)-0.650846685f, (float16_t)0.759209189f, + (float16_t)-0.653172843f, (float16_t)0.757208847f, + (float16_t)-0.655492853f, (float16_t)0.755201377f, + (float16_t)-0.657806693f, (float16_t)0.753186799f, + (float16_t)-0.660114342f, (float16_t)0.751165132f, + (float16_t)-0.662415778f, (float16_t)0.749136395f, + (float16_t)-0.664710978f, (float16_t)0.747100606f, + (float16_t)-0.666999922f, (float16_t)0.745057785f, + (float16_t)-0.669282588f, (float16_t)0.743007952f, + (float16_t)-0.671558955f, (float16_t)0.740951125f, + (float16_t)-0.673829000f, (float16_t)0.738887324f, + (float16_t)-0.676092704f, (float16_t)0.736816569f, + (float16_t)-0.678350043f, (float16_t)0.734738878f, + (float16_t)-0.680600998f, (float16_t)0.732654272f, + (float16_t)-0.682845546f, (float16_t)0.730562769f, + (float16_t)-0.685083668f, (float16_t)0.728464390f, + (float16_t)-0.687315341f, (float16_t)0.726359155f, + (float16_t)-0.689540545f, (float16_t)0.724247083f, + (float16_t)-0.691759258f, (float16_t)0.722128194f, + (float16_t)-0.693971461f, (float16_t)0.720002508f, + (float16_t)-0.696177131f, (float16_t)0.717870045f, + (float16_t)-0.698376249f, (float16_t)0.715730825f, + (float16_t)-0.700568794f, (float16_t)0.713584869f, + (float16_t)-0.702754744f, (float16_t)0.711432196f, + (float16_t)-0.704934080f, (float16_t)0.709272826f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.709272826f, (float16_t)0.704934080f, + (float16_t)-0.711432196f, (float16_t)0.702754744f, + (float16_t)-0.713584869f, (float16_t)0.700568794f, + (float16_t)-0.715730825f, (float16_t)0.698376249f, + (float16_t)-0.717870045f, (float16_t)0.696177131f, + (float16_t)-0.720002508f, (float16_t)0.693971461f, + (float16_t)-0.722128194f, (float16_t)0.691759258f, + (float16_t)-0.724247083f, (float16_t)0.689540545f, + (float16_t)-0.726359155f, (float16_t)0.687315341f, + (float16_t)-0.728464390f, (float16_t)0.685083668f, + (float16_t)-0.730562769f, (float16_t)0.682845546f, + (float16_t)-0.732654272f, (float16_t)0.680600998f, + (float16_t)-0.734738878f, (float16_t)0.678350043f, + (float16_t)-0.736816569f, (float16_t)0.676092704f, + (float16_t)-0.738887324f, (float16_t)0.673829000f, + (float16_t)-0.740951125f, (float16_t)0.671558955f, + (float16_t)-0.743007952f, (float16_t)0.669282588f, + (float16_t)-0.745057785f, (float16_t)0.666999922f, + (float16_t)-0.747100606f, (float16_t)0.664710978f, + (float16_t)-0.749136395f, (float16_t)0.662415778f, + (float16_t)-0.751165132f, (float16_t)0.660114342f, + (float16_t)-0.753186799f, (float16_t)0.657806693f, + (float16_t)-0.755201377f, (float16_t)0.655492853f, + (float16_t)-0.757208847f, (float16_t)0.653172843f, + (float16_t)-0.759209189f, (float16_t)0.650846685f, + (float16_t)-0.761202385f, (float16_t)0.648514401f, + (float16_t)-0.763188417f, (float16_t)0.646176013f, + (float16_t)-0.765167266f, (float16_t)0.643831543f, + (float16_t)-0.767138912f, (float16_t)0.641481013f, + (float16_t)-0.769103338f, (float16_t)0.639124445f, + (float16_t)-0.771060524f, (float16_t)0.636761861f, + (float16_t)-0.773010453f, (float16_t)0.634393284f, + (float16_t)-0.774953107f, (float16_t)0.632018736f, + (float16_t)-0.776888466f, (float16_t)0.629638239f, + (float16_t)-0.778816512f, (float16_t)0.627251815f, + (float16_t)-0.780737229f, (float16_t)0.624859488f, + (float16_t)-0.782650596f, (float16_t)0.622461279f, + (float16_t)-0.784556597f, (float16_t)0.620057212f, + (float16_t)-0.786455214f, (float16_t)0.617647308f, + (float16_t)-0.788346428f, (float16_t)0.615231591f, + (float16_t)-0.790230221f, (float16_t)0.612810082f, + (float16_t)-0.792106577f, (float16_t)0.610382806f, + (float16_t)-0.793975478f, (float16_t)0.607949785f, + (float16_t)-0.795836905f, (float16_t)0.605511041f, + (float16_t)-0.797690841f, (float16_t)0.603066599f, + (float16_t)-0.799537269f, (float16_t)0.600616479f, + (float16_t)-0.801376172f, (float16_t)0.598160707f, + (float16_t)-0.803207531f, (float16_t)0.595699304f, + (float16_t)-0.805031331f, (float16_t)0.593232295f, + (float16_t)-0.806847554f, (float16_t)0.590759702f, + (float16_t)-0.808656182f, (float16_t)0.588281548f, + (float16_t)-0.810457198f, (float16_t)0.585797857f, + (float16_t)-0.812250587f, (float16_t)0.583308653f, + (float16_t)-0.814036330f, (float16_t)0.580813958f, + (float16_t)-0.815814411f, (float16_t)0.578313796f, + (float16_t)-0.817584813f, (float16_t)0.575808191f, + (float16_t)-0.819347520f, (float16_t)0.573297167f, + (float16_t)-0.821102515f, (float16_t)0.570780746f, + (float16_t)-0.822849781f, (float16_t)0.568258953f, + (float16_t)-0.824589303f, (float16_t)0.565731811f, + (float16_t)-0.826321063f, (float16_t)0.563199344f, + (float16_t)-0.828045045f, (float16_t)0.560661576f, + (float16_t)-0.829761234f, (float16_t)0.558118531f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.833170165f, (float16_t)0.553016706f, + (float16_t)-0.834862875f, (float16_t)0.550457973f, + (float16_t)-0.836547727f, (float16_t)0.547894059f, + (float16_t)-0.838224706f, (float16_t)0.545324988f, + (float16_t)-0.839893794f, (float16_t)0.542750785f, + (float16_t)-0.841554977f, (float16_t)0.540171473f, + (float16_t)-0.843208240f, (float16_t)0.537587076f, + (float16_t)-0.844853565f, (float16_t)0.534997620f, + (float16_t)-0.846490939f, (float16_t)0.532403128f, + (float16_t)-0.848120345f, (float16_t)0.529803625f, + (float16_t)-0.849741768f, (float16_t)0.527199135f, + (float16_t)-0.851355193f, (float16_t)0.524589683f, + (float16_t)-0.852960605f, (float16_t)0.521975293f, + (float16_t)-0.854557988f, (float16_t)0.519355990f, + (float16_t)-0.856147328f, (float16_t)0.516731799f, + (float16_t)-0.857728610f, (float16_t)0.514102744f, + (float16_t)-0.859301818f, (float16_t)0.511468850f, + (float16_t)-0.860866939f, (float16_t)0.508830143f, + (float16_t)-0.862423956f, (float16_t)0.506186645f, + (float16_t)-0.863972856f, (float16_t)0.503538384f, + (float16_t)-0.865513624f, (float16_t)0.500885383f, + (float16_t)-0.867046246f, (float16_t)0.498227667f, + (float16_t)-0.868570706f, (float16_t)0.495565262f, + (float16_t)-0.870086991f, (float16_t)0.492898192f, + (float16_t)-0.871595087f, (float16_t)0.490226483f, + (float16_t)-0.873094978f, (float16_t)0.487550160f, + (float16_t)-0.874586652f, (float16_t)0.484869248f, + (float16_t)-0.876070094f, (float16_t)0.482183772f, + (float16_t)-0.877545290f, (float16_t)0.479493758f, + (float16_t)-0.879012226f, (float16_t)0.476799230f, + (float16_t)-0.880470889f, (float16_t)0.474100215f, + (float16_t)-0.881921264f, (float16_t)0.471396737f, + (float16_t)-0.883363339f, (float16_t)0.468688822f, + (float16_t)-0.884797098f, (float16_t)0.465976496f, + (float16_t)-0.886222530f, (float16_t)0.463259784f, + (float16_t)-0.887639620f, (float16_t)0.460538711f, + (float16_t)-0.889048356f, (float16_t)0.457813304f, + (float16_t)-0.890448723f, (float16_t)0.455083587f, + (float16_t)-0.891840709f, (float16_t)0.452349587f, + (float16_t)-0.893224301f, (float16_t)0.449611330f, + (float16_t)-0.894599486f, (float16_t)0.446868840f, + (float16_t)-0.895966250f, (float16_t)0.444122145f, + (float16_t)-0.897324581f, (float16_t)0.441371269f, + (float16_t)-0.898674466f, (float16_t)0.438616239f, + (float16_t)-0.900015892f, (float16_t)0.435857080f, + (float16_t)-0.901348847f, (float16_t)0.433093819f, + (float16_t)-0.902673318f, (float16_t)0.430326481f, + (float16_t)-0.903989293f, (float16_t)0.427555093f, + (float16_t)-0.905296759f, (float16_t)0.424779681f, + (float16_t)-0.906595705f, (float16_t)0.422000271f, + (float16_t)-0.907886116f, (float16_t)0.419216888f, + (float16_t)-0.909167983f, (float16_t)0.416429560f, + (float16_t)-0.910441292f, (float16_t)0.413638312f, + (float16_t)-0.911706032f, (float16_t)0.410843171f, + (float16_t)-0.912962190f, (float16_t)0.408044163f, + (float16_t)-0.914209756f, (float16_t)0.405241314f, + (float16_t)-0.915448716f, (float16_t)0.402434651f, + (float16_t)-0.916679060f, (float16_t)0.399624200f, + (float16_t)-0.917900776f, (float16_t)0.396809987f, + (float16_t)-0.919113852f, (float16_t)0.393992040f, + (float16_t)-0.920318277f, (float16_t)0.391170384f, + (float16_t)-0.921514039f, (float16_t)0.388345047f, + (float16_t)-0.922701128f, (float16_t)0.385516054f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.925049241f, (float16_t)0.379847209f, + (float16_t)-0.926210242f, (float16_t)0.377007410f, + (float16_t)-0.927362526f, (float16_t)0.374164063f, + (float16_t)-0.928506080f, (float16_t)0.371317194f, + (float16_t)-0.929640896f, (float16_t)0.368466830f, + (float16_t)-0.930766961f, (float16_t)0.365612998f, + (float16_t)-0.931884266f, (float16_t)0.362755724f, + (float16_t)-0.932992799f, (float16_t)0.359895037f, + (float16_t)-0.934092550f, (float16_t)0.357030961f, + (float16_t)-0.935183510f, (float16_t)0.354163525f, + (float16_t)-0.936265667f, (float16_t)0.351292756f, + (float16_t)-0.937339012f, (float16_t)0.348418680f, + (float16_t)-0.938403534f, (float16_t)0.345541325f, + (float16_t)-0.939459224f, (float16_t)0.342660717f, + (float16_t)-0.940506071f, (float16_t)0.339776884f, + (float16_t)-0.941544065f, (float16_t)0.336889853f, + (float16_t)-0.942573198f, (float16_t)0.333999651f, + (float16_t)-0.943593458f, (float16_t)0.331106306f, + (float16_t)-0.944604837f, (float16_t)0.328209844f, + (float16_t)-0.945607325f, (float16_t)0.325310292f, + (float16_t)-0.946600913f, (float16_t)0.322407679f, + (float16_t)-0.947585591f, (float16_t)0.319502031f, + (float16_t)-0.948561350f, (float16_t)0.316593376f, + (float16_t)-0.949528181f, (float16_t)0.313681740f, + (float16_t)-0.950486074f, (float16_t)0.310767153f, + (float16_t)-0.951435021f, (float16_t)0.307849640f, + (float16_t)-0.952375013f, (float16_t)0.304929230f, + (float16_t)-0.953306040f, (float16_t)0.302005949f, + (float16_t)-0.954228095f, (float16_t)0.299079826f, + (float16_t)-0.955141168f, (float16_t)0.296150888f, + (float16_t)-0.956045251f, (float16_t)0.293219163f, + (float16_t)-0.956940336f, (float16_t)0.290284677f, + (float16_t)-0.957826413f, (float16_t)0.287347460f, + (float16_t)-0.958703475f, (float16_t)0.284407537f, + (float16_t)-0.959571513f, (float16_t)0.281464938f, + (float16_t)-0.960430519f, (float16_t)0.278519689f, + (float16_t)-0.961280486f, (float16_t)0.275571819f, + (float16_t)-0.962121404f, (float16_t)0.272621355f, + (float16_t)-0.962953267f, (float16_t)0.269668326f, + (float16_t)-0.963776066f, (float16_t)0.266712757f, + (float16_t)-0.964589793f, (float16_t)0.263754679f, + (float16_t)-0.965394442f, (float16_t)0.260794118f, + (float16_t)-0.966190003f, (float16_t)0.257831102f, + (float16_t)-0.966976471f, (float16_t)0.254865660f, + (float16_t)-0.967753837f, (float16_t)0.251897818f, + (float16_t)-0.968522094f, (float16_t)0.248927606f, + (float16_t)-0.969281235f, (float16_t)0.245955050f, + (float16_t)-0.970031253f, (float16_t)0.242980180f, + (float16_t)-0.970772141f, (float16_t)0.240003022f, + (float16_t)-0.971503891f, (float16_t)0.237023606f, + (float16_t)-0.972226497f, (float16_t)0.234041959f, + (float16_t)-0.972939952f, (float16_t)0.231058108f, + (float16_t)-0.973644250f, (float16_t)0.228072083f, + (float16_t)-0.974339383f, (float16_t)0.225083911f, + (float16_t)-0.975025345f, (float16_t)0.222093621f, + (float16_t)-0.975702130f, (float16_t)0.219101240f, + (float16_t)-0.976369731f, (float16_t)0.216106797f, + (float16_t)-0.977028143f, (float16_t)0.213110320f, + (float16_t)-0.977677358f, (float16_t)0.210111837f, + (float16_t)-0.978317371f, (float16_t)0.207111376f, + (float16_t)-0.978948175f, (float16_t)0.204108966f, + (float16_t)-0.979569766f, (float16_t)0.201104635f, + (float16_t)-0.980182136f, (float16_t)0.198098411f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-0.981379193f, (float16_t)0.192080397f, + (float16_t)-0.981963869f, (float16_t)0.189068664f, + (float16_t)-0.982539302f, (float16_t)0.186055152f, + (float16_t)-0.983105487f, (float16_t)0.183039888f, + (float16_t)-0.983662419f, (float16_t)0.180022901f, + (float16_t)-0.984210092f, (float16_t)0.177004220f, + (float16_t)-0.984748502f, (float16_t)0.173983873f, + (float16_t)-0.985277642f, (float16_t)0.170961889f, + (float16_t)-0.985797509f, (float16_t)0.167938295f, + (float16_t)-0.986308097f, (float16_t)0.164913120f, + (float16_t)-0.986809402f, (float16_t)0.161886394f, + (float16_t)-0.987301418f, (float16_t)0.158858143f, + (float16_t)-0.987784142f, (float16_t)0.155828398f, + (float16_t)-0.988257568f, (float16_t)0.152797185f, + (float16_t)-0.988721692f, (float16_t)0.149764535f, + (float16_t)-0.989176510f, (float16_t)0.146730474f, + (float16_t)-0.989622017f, (float16_t)0.143695033f, + (float16_t)-0.990058210f, (float16_t)0.140658239f, + (float16_t)-0.990485084f, (float16_t)0.137620122f, + (float16_t)-0.990902635f, (float16_t)0.134580709f, + (float16_t)-0.991310860f, (float16_t)0.131540029f, + (float16_t)-0.991709754f, (float16_t)0.128498111f, + (float16_t)-0.992099313f, (float16_t)0.125454983f, + (float16_t)-0.992479535f, (float16_t)0.122410675f, + (float16_t)-0.992850414f, (float16_t)0.119365215f, + (float16_t)-0.993211949f, (float16_t)0.116318631f, + (float16_t)-0.993564136f, (float16_t)0.113270952f, + (float16_t)-0.993906970f, (float16_t)0.110222207f, + (float16_t)-0.994240449f, (float16_t)0.107172425f, + (float16_t)-0.994564571f, (float16_t)0.104121634f, + (float16_t)-0.994879331f, (float16_t)0.101069863f, + (float16_t)-0.995184727f, (float16_t)0.098017140f, + (float16_t)-0.995480755f, (float16_t)0.094963495f, + (float16_t)-0.995767414f, (float16_t)0.091908956f, + (float16_t)-0.996044701f, (float16_t)0.088853553f, + (float16_t)-0.996312612f, (float16_t)0.085797312f, + (float16_t)-0.996571146f, (float16_t)0.082740265f, + (float16_t)-0.996820299f, (float16_t)0.079682438f, + (float16_t)-0.997060070f, (float16_t)0.076623861f, + (float16_t)-0.997290457f, (float16_t)0.073564564f, + (float16_t)-0.997511456f, (float16_t)0.070504573f, + (float16_t)-0.997723067f, (float16_t)0.067443920f, + (float16_t)-0.997925286f, (float16_t)0.064382631f, + (float16_t)-0.998118113f, (float16_t)0.061320736f, + (float16_t)-0.998301545f, (float16_t)0.058258265f, + (float16_t)-0.998475581f, (float16_t)0.055195244f, + (float16_t)-0.998640218f, (float16_t)0.052131705f, + (float16_t)-0.998795456f, (float16_t)0.049067674f, + (float16_t)-0.998941293f, (float16_t)0.046003182f, + (float16_t)-0.999077728f, (float16_t)0.042938257f, + (float16_t)-0.999204759f, (float16_t)0.039872928f, + (float16_t)-0.999322385f, (float16_t)0.036807223f, + (float16_t)-0.999430605f, (float16_t)0.033741172f, + (float16_t)-0.999529418f, (float16_t)0.030674803f, + (float16_t)-0.999618822f, (float16_t)0.027608146f, + (float16_t)-0.999698819f, (float16_t)0.024541229f, + (float16_t)-0.999769405f, (float16_t)0.021474080f, + (float16_t)-0.999830582f, (float16_t)0.018406730f, + (float16_t)-0.999882347f, (float16_t)0.015339206f, + (float16_t)-0.999924702f, (float16_t)0.012271538f, + (float16_t)-0.999957645f, (float16_t)0.009203755f, + (float16_t)-0.999981175f, (float16_t)0.006135885f, + (float16_t)-0.999995294f, (float16_t)0.003067957f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.999995294f, (float16_t)-0.003067957f, + (float16_t)-0.999981175f, (float16_t)-0.006135885f, + (float16_t)-0.999957645f, (float16_t)-0.009203755f, + (float16_t)-0.999924702f, (float16_t)-0.012271538f, + (float16_t)-0.999882347f, (float16_t)-0.015339206f, + (float16_t)-0.999830582f, (float16_t)-0.018406730f, + (float16_t)-0.999769405f, (float16_t)-0.021474080f, + (float16_t)-0.999698819f, (float16_t)-0.024541229f, + (float16_t)-0.999618822f, (float16_t)-0.027608146f, + (float16_t)-0.999529418f, (float16_t)-0.030674803f, + (float16_t)-0.999430605f, (float16_t)-0.033741172f, + (float16_t)-0.999322385f, (float16_t)-0.036807223f, + (float16_t)-0.999204759f, (float16_t)-0.039872928f, + (float16_t)-0.999077728f, (float16_t)-0.042938257f, + (float16_t)-0.998941293f, (float16_t)-0.046003182f, + (float16_t)-0.998795456f, (float16_t)-0.049067674f, + (float16_t)-0.998640218f, (float16_t)-0.052131705f, + (float16_t)-0.998475581f, (float16_t)-0.055195244f, + (float16_t)-0.998301545f, (float16_t)-0.058258265f, + (float16_t)-0.998118113f, (float16_t)-0.061320736f, + (float16_t)-0.997925286f, (float16_t)-0.064382631f, + (float16_t)-0.997723067f, (float16_t)-0.067443920f, + (float16_t)-0.997511456f, (float16_t)-0.070504573f, + (float16_t)-0.997290457f, (float16_t)-0.073564564f, + (float16_t)-0.997060070f, (float16_t)-0.076623861f, + (float16_t)-0.996820299f, (float16_t)-0.079682438f, + (float16_t)-0.996571146f, (float16_t)-0.082740265f, + (float16_t)-0.996312612f, (float16_t)-0.085797312f, + (float16_t)-0.996044701f, (float16_t)-0.088853553f, + (float16_t)-0.995767414f, (float16_t)-0.091908956f, + (float16_t)-0.995480755f, (float16_t)-0.094963495f, + (float16_t)-0.995184727f, (float16_t)-0.098017140f, + (float16_t)-0.994879331f, (float16_t)-0.101069863f, + (float16_t)-0.994564571f, (float16_t)-0.104121634f, + (float16_t)-0.994240449f, (float16_t)-0.107172425f, + (float16_t)-0.993906970f, (float16_t)-0.110222207f, + (float16_t)-0.993564136f, (float16_t)-0.113270952f, + (float16_t)-0.993211949f, (float16_t)-0.116318631f, + (float16_t)-0.992850414f, (float16_t)-0.119365215f, + (float16_t)-0.992479535f, (float16_t)-0.122410675f, + (float16_t)-0.992099313f, (float16_t)-0.125454983f, + (float16_t)-0.991709754f, (float16_t)-0.128498111f, + (float16_t)-0.991310860f, (float16_t)-0.131540029f, + (float16_t)-0.990902635f, (float16_t)-0.134580709f, + (float16_t)-0.990485084f, (float16_t)-0.137620122f, + (float16_t)-0.990058210f, (float16_t)-0.140658239f, + (float16_t)-0.989622017f, (float16_t)-0.143695033f, + (float16_t)-0.989176510f, (float16_t)-0.146730474f, + (float16_t)-0.988721692f, (float16_t)-0.149764535f, + (float16_t)-0.988257568f, (float16_t)-0.152797185f, + (float16_t)-0.987784142f, (float16_t)-0.155828398f, + (float16_t)-0.987301418f, (float16_t)-0.158858143f, + (float16_t)-0.986809402f, (float16_t)-0.161886394f, + (float16_t)-0.986308097f, (float16_t)-0.164913120f, + (float16_t)-0.985797509f, (float16_t)-0.167938295f, + (float16_t)-0.985277642f, (float16_t)-0.170961889f, + (float16_t)-0.984748502f, (float16_t)-0.173983873f, + (float16_t)-0.984210092f, (float16_t)-0.177004220f, + (float16_t)-0.983662419f, (float16_t)-0.180022901f, + (float16_t)-0.983105487f, (float16_t)-0.183039888f, + (float16_t)-0.982539302f, (float16_t)-0.186055152f, + (float16_t)-0.981963869f, (float16_t)-0.189068664f, + (float16_t)-0.981379193f, (float16_t)-0.192080397f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.980182136f, (float16_t)-0.198098411f, + (float16_t)-0.979569766f, (float16_t)-0.201104635f, + (float16_t)-0.978948175f, (float16_t)-0.204108966f, + (float16_t)-0.978317371f, (float16_t)-0.207111376f, + (float16_t)-0.977677358f, (float16_t)-0.210111837f, + (float16_t)-0.977028143f, (float16_t)-0.213110320f, + (float16_t)-0.976369731f, (float16_t)-0.216106797f, + (float16_t)-0.975702130f, (float16_t)-0.219101240f, + (float16_t)-0.975025345f, (float16_t)-0.222093621f, + (float16_t)-0.974339383f, (float16_t)-0.225083911f, + (float16_t)-0.973644250f, (float16_t)-0.228072083f, + (float16_t)-0.972939952f, (float16_t)-0.231058108f, + (float16_t)-0.972226497f, (float16_t)-0.234041959f, + (float16_t)-0.971503891f, (float16_t)-0.237023606f, + (float16_t)-0.970772141f, (float16_t)-0.240003022f, + (float16_t)-0.970031253f, (float16_t)-0.242980180f, + (float16_t)-0.969281235f, (float16_t)-0.245955050f, + (float16_t)-0.968522094f, (float16_t)-0.248927606f, + (float16_t)-0.967753837f, (float16_t)-0.251897818f, + (float16_t)-0.966976471f, (float16_t)-0.254865660f, + (float16_t)-0.966190003f, (float16_t)-0.257831102f, + (float16_t)-0.965394442f, (float16_t)-0.260794118f, + (float16_t)-0.964589793f, (float16_t)-0.263754679f, + (float16_t)-0.963776066f, (float16_t)-0.266712757f, + (float16_t)-0.962953267f, (float16_t)-0.269668326f, + (float16_t)-0.962121404f, (float16_t)-0.272621355f, + (float16_t)-0.961280486f, (float16_t)-0.275571819f, + (float16_t)-0.960430519f, (float16_t)-0.278519689f, + (float16_t)-0.959571513f, (float16_t)-0.281464938f, + (float16_t)-0.958703475f, (float16_t)-0.284407537f, + (float16_t)-0.957826413f, (float16_t)-0.287347460f, + (float16_t)-0.956940336f, (float16_t)-0.290284677f, + (float16_t)-0.956045251f, (float16_t)-0.293219163f, + (float16_t)-0.955141168f, (float16_t)-0.296150888f, + (float16_t)-0.954228095f, (float16_t)-0.299079826f, + (float16_t)-0.953306040f, (float16_t)-0.302005949f, + (float16_t)-0.952375013f, (float16_t)-0.304929230f, + (float16_t)-0.951435021f, (float16_t)-0.307849640f, + (float16_t)-0.950486074f, (float16_t)-0.310767153f, + (float16_t)-0.949528181f, (float16_t)-0.313681740f, + (float16_t)-0.948561350f, (float16_t)-0.316593376f, + (float16_t)-0.947585591f, (float16_t)-0.319502031f, + (float16_t)-0.946600913f, (float16_t)-0.322407679f, + (float16_t)-0.945607325f, (float16_t)-0.325310292f, + (float16_t)-0.944604837f, (float16_t)-0.328209844f, + (float16_t)-0.943593458f, (float16_t)-0.331106306f, + (float16_t)-0.942573198f, (float16_t)-0.333999651f, + (float16_t)-0.941544065f, (float16_t)-0.336889853f, + (float16_t)-0.940506071f, (float16_t)-0.339776884f, + (float16_t)-0.939459224f, (float16_t)-0.342660717f, + (float16_t)-0.938403534f, (float16_t)-0.345541325f, + (float16_t)-0.937339012f, (float16_t)-0.348418680f, + (float16_t)-0.936265667f, (float16_t)-0.351292756f, + (float16_t)-0.935183510f, (float16_t)-0.354163525f, + (float16_t)-0.934092550f, (float16_t)-0.357030961f, + (float16_t)-0.932992799f, (float16_t)-0.359895037f, + (float16_t)-0.931884266f, (float16_t)-0.362755724f, + (float16_t)-0.930766961f, (float16_t)-0.365612998f, + (float16_t)-0.929640896f, (float16_t)-0.368466830f, + (float16_t)-0.928506080f, (float16_t)-0.371317194f, + (float16_t)-0.927362526f, (float16_t)-0.374164063f, + (float16_t)-0.926210242f, (float16_t)-0.377007410f, + (float16_t)-0.925049241f, (float16_t)-0.379847209f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.922701128f, (float16_t)-0.385516054f, + (float16_t)-0.921514039f, (float16_t)-0.388345047f, + (float16_t)-0.920318277f, (float16_t)-0.391170384f, + (float16_t)-0.919113852f, (float16_t)-0.393992040f, + (float16_t)-0.917900776f, (float16_t)-0.396809987f, + (float16_t)-0.916679060f, (float16_t)-0.399624200f, + (float16_t)-0.915448716f, (float16_t)-0.402434651f, + (float16_t)-0.914209756f, (float16_t)-0.405241314f, + (float16_t)-0.912962190f, (float16_t)-0.408044163f, + (float16_t)-0.911706032f, (float16_t)-0.410843171f, + (float16_t)-0.910441292f, (float16_t)-0.413638312f, + (float16_t)-0.909167983f, (float16_t)-0.416429560f, + (float16_t)-0.907886116f, (float16_t)-0.419216888f, + (float16_t)-0.906595705f, (float16_t)-0.422000271f, + (float16_t)-0.905296759f, (float16_t)-0.424779681f, + (float16_t)-0.903989293f, (float16_t)-0.427555093f, + (float16_t)-0.902673318f, (float16_t)-0.430326481f, + (float16_t)-0.901348847f, (float16_t)-0.433093819f, + (float16_t)-0.900015892f, (float16_t)-0.435857080f, + (float16_t)-0.898674466f, (float16_t)-0.438616239f, + (float16_t)-0.897324581f, (float16_t)-0.441371269f, + (float16_t)-0.895966250f, (float16_t)-0.444122145f, + (float16_t)-0.894599486f, (float16_t)-0.446868840f, + (float16_t)-0.893224301f, (float16_t)-0.449611330f, + (float16_t)-0.891840709f, (float16_t)-0.452349587f, + (float16_t)-0.890448723f, (float16_t)-0.455083587f, + (float16_t)-0.889048356f, (float16_t)-0.457813304f, + (float16_t)-0.887639620f, (float16_t)-0.460538711f, + (float16_t)-0.886222530f, (float16_t)-0.463259784f, + (float16_t)-0.884797098f, (float16_t)-0.465976496f, + (float16_t)-0.883363339f, (float16_t)-0.468688822f, + (float16_t)-0.881921264f, (float16_t)-0.471396737f, + (float16_t)-0.880470889f, (float16_t)-0.474100215f, + (float16_t)-0.879012226f, (float16_t)-0.476799230f, + (float16_t)-0.877545290f, (float16_t)-0.479493758f, + (float16_t)-0.876070094f, (float16_t)-0.482183772f, + (float16_t)-0.874586652f, (float16_t)-0.484869248f, + (float16_t)-0.873094978f, (float16_t)-0.487550160f, + (float16_t)-0.871595087f, (float16_t)-0.490226483f, + (float16_t)-0.870086991f, (float16_t)-0.492898192f, + (float16_t)-0.868570706f, (float16_t)-0.495565262f, + (float16_t)-0.867046246f, (float16_t)-0.498227667f, + (float16_t)-0.865513624f, (float16_t)-0.500885383f, + (float16_t)-0.863972856f, (float16_t)-0.503538384f, + (float16_t)-0.862423956f, (float16_t)-0.506186645f, + (float16_t)-0.860866939f, (float16_t)-0.508830143f, + (float16_t)-0.859301818f, (float16_t)-0.511468850f, + (float16_t)-0.857728610f, (float16_t)-0.514102744f, + (float16_t)-0.856147328f, (float16_t)-0.516731799f, + (float16_t)-0.854557988f, (float16_t)-0.519355990f, + (float16_t)-0.852960605f, (float16_t)-0.521975293f, + (float16_t)-0.851355193f, (float16_t)-0.524589683f, + (float16_t)-0.849741768f, (float16_t)-0.527199135f, + (float16_t)-0.848120345f, (float16_t)-0.529803625f, + (float16_t)-0.846490939f, (float16_t)-0.532403128f, + (float16_t)-0.844853565f, (float16_t)-0.534997620f, + (float16_t)-0.843208240f, (float16_t)-0.537587076f, + (float16_t)-0.841554977f, (float16_t)-0.540171473f, + (float16_t)-0.839893794f, (float16_t)-0.542750785f, + (float16_t)-0.838224706f, (float16_t)-0.545324988f, + (float16_t)-0.836547727f, (float16_t)-0.547894059f, + (float16_t)-0.834862875f, (float16_t)-0.550457973f, + (float16_t)-0.833170165f, (float16_t)-0.553016706f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.829761234f, (float16_t)-0.558118531f, + (float16_t)-0.828045045f, (float16_t)-0.560661576f, + (float16_t)-0.826321063f, (float16_t)-0.563199344f, + (float16_t)-0.824589303f, (float16_t)-0.565731811f, + (float16_t)-0.822849781f, (float16_t)-0.568258953f, + (float16_t)-0.821102515f, (float16_t)-0.570780746f, + (float16_t)-0.819347520f, (float16_t)-0.573297167f, + (float16_t)-0.817584813f, (float16_t)-0.575808191f, + (float16_t)-0.815814411f, (float16_t)-0.578313796f, + (float16_t)-0.814036330f, (float16_t)-0.580813958f, + (float16_t)-0.812250587f, (float16_t)-0.583308653f, + (float16_t)-0.810457198f, (float16_t)-0.585797857f, + (float16_t)-0.808656182f, (float16_t)-0.588281548f, + (float16_t)-0.806847554f, (float16_t)-0.590759702f, + (float16_t)-0.805031331f, (float16_t)-0.593232295f, + (float16_t)-0.803207531f, (float16_t)-0.595699304f, + (float16_t)-0.801376172f, (float16_t)-0.598160707f, + (float16_t)-0.799537269f, (float16_t)-0.600616479f, + (float16_t)-0.797690841f, (float16_t)-0.603066599f, + (float16_t)-0.795836905f, (float16_t)-0.605511041f, + (float16_t)-0.793975478f, (float16_t)-0.607949785f, + (float16_t)-0.792106577f, (float16_t)-0.610382806f, + (float16_t)-0.790230221f, (float16_t)-0.612810082f, + (float16_t)-0.788346428f, (float16_t)-0.615231591f, + (float16_t)-0.786455214f, (float16_t)-0.617647308f, + (float16_t)-0.784556597f, (float16_t)-0.620057212f, + (float16_t)-0.782650596f, (float16_t)-0.622461279f, + (float16_t)-0.780737229f, (float16_t)-0.624859488f, + (float16_t)-0.778816512f, (float16_t)-0.627251815f, + (float16_t)-0.776888466f, (float16_t)-0.629638239f, + (float16_t)-0.774953107f, (float16_t)-0.632018736f, + (float16_t)-0.773010453f, (float16_t)-0.634393284f, + (float16_t)-0.771060524f, (float16_t)-0.636761861f, + (float16_t)-0.769103338f, (float16_t)-0.639124445f, + (float16_t)-0.767138912f, (float16_t)-0.641481013f, + (float16_t)-0.765167266f, (float16_t)-0.643831543f, + (float16_t)-0.763188417f, (float16_t)-0.646176013f, + (float16_t)-0.761202385f, (float16_t)-0.648514401f, + (float16_t)-0.759209189f, (float16_t)-0.650846685f, + (float16_t)-0.757208847f, (float16_t)-0.653172843f, + (float16_t)-0.755201377f, (float16_t)-0.655492853f, + (float16_t)-0.753186799f, (float16_t)-0.657806693f, + (float16_t)-0.751165132f, (float16_t)-0.660114342f, + (float16_t)-0.749136395f, (float16_t)-0.662415778f, + (float16_t)-0.747100606f, (float16_t)-0.664710978f, + (float16_t)-0.745057785f, (float16_t)-0.666999922f, + (float16_t)-0.743007952f, (float16_t)-0.669282588f, + (float16_t)-0.740951125f, (float16_t)-0.671558955f, + (float16_t)-0.738887324f, (float16_t)-0.673829000f, + (float16_t)-0.736816569f, (float16_t)-0.676092704f, + (float16_t)-0.734738878f, (float16_t)-0.678350043f, + (float16_t)-0.732654272f, (float16_t)-0.680600998f, + (float16_t)-0.730562769f, (float16_t)-0.682845546f, + (float16_t)-0.728464390f, (float16_t)-0.685083668f, + (float16_t)-0.726359155f, (float16_t)-0.687315341f, + (float16_t)-0.724247083f, (float16_t)-0.689540545f, + (float16_t)-0.722128194f, (float16_t)-0.691759258f, + (float16_t)-0.720002508f, (float16_t)-0.693971461f, + (float16_t)-0.717870045f, (float16_t)-0.696177131f, + (float16_t)-0.715730825f, (float16_t)-0.698376249f, + (float16_t)-0.713584869f, (float16_t)-0.700568794f, + (float16_t)-0.711432196f, (float16_t)-0.702754744f, + (float16_t)-0.709272826f, (float16_t)-0.704934080f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.704934080f, (float16_t)-0.709272826f, + (float16_t)-0.702754744f, (float16_t)-0.711432196f, + (float16_t)-0.700568794f, (float16_t)-0.713584869f, + (float16_t)-0.698376249f, (float16_t)-0.715730825f, + (float16_t)-0.696177131f, (float16_t)-0.717870045f, + (float16_t)-0.693971461f, (float16_t)-0.720002508f, + (float16_t)-0.691759258f, (float16_t)-0.722128194f, + (float16_t)-0.689540545f, (float16_t)-0.724247083f, + (float16_t)-0.687315341f, (float16_t)-0.726359155f, + (float16_t)-0.685083668f, (float16_t)-0.728464390f, + (float16_t)-0.682845546f, (float16_t)-0.730562769f, + (float16_t)-0.680600998f, (float16_t)-0.732654272f, + (float16_t)-0.678350043f, (float16_t)-0.734738878f, + (float16_t)-0.676092704f, (float16_t)-0.736816569f, + (float16_t)-0.673829000f, (float16_t)-0.738887324f, + (float16_t)-0.671558955f, (float16_t)-0.740951125f, + (float16_t)-0.669282588f, (float16_t)-0.743007952f, + (float16_t)-0.666999922f, (float16_t)-0.745057785f, + (float16_t)-0.664710978f, (float16_t)-0.747100606f, + (float16_t)-0.662415778f, (float16_t)-0.749136395f, + (float16_t)-0.660114342f, (float16_t)-0.751165132f, + (float16_t)-0.657806693f, (float16_t)-0.753186799f, + (float16_t)-0.655492853f, (float16_t)-0.755201377f, + (float16_t)-0.653172843f, (float16_t)-0.757208847f, + (float16_t)-0.650846685f, (float16_t)-0.759209189f, + (float16_t)-0.648514401f, (float16_t)-0.761202385f, + (float16_t)-0.646176013f, (float16_t)-0.763188417f, + (float16_t)-0.643831543f, (float16_t)-0.765167266f, + (float16_t)-0.641481013f, (float16_t)-0.767138912f, + (float16_t)-0.639124445f, (float16_t)-0.769103338f, + (float16_t)-0.636761861f, (float16_t)-0.771060524f, + (float16_t)-0.634393284f, (float16_t)-0.773010453f, + (float16_t)-0.632018736f, (float16_t)-0.774953107f, + (float16_t)-0.629638239f, (float16_t)-0.776888466f, + (float16_t)-0.627251815f, (float16_t)-0.778816512f, + (float16_t)-0.624859488f, (float16_t)-0.780737229f, + (float16_t)-0.622461279f, (float16_t)-0.782650596f, + (float16_t)-0.620057212f, (float16_t)-0.784556597f, + (float16_t)-0.617647308f, (float16_t)-0.786455214f, + (float16_t)-0.615231591f, (float16_t)-0.788346428f, + (float16_t)-0.612810082f, (float16_t)-0.790230221f, + (float16_t)-0.610382806f, (float16_t)-0.792106577f, + (float16_t)-0.607949785f, (float16_t)-0.793975478f, + (float16_t)-0.605511041f, (float16_t)-0.795836905f, + (float16_t)-0.603066599f, (float16_t)-0.797690841f, + (float16_t)-0.600616479f, (float16_t)-0.799537269f, + (float16_t)-0.598160707f, (float16_t)-0.801376172f, + (float16_t)-0.595699304f, (float16_t)-0.803207531f, + (float16_t)-0.593232295f, (float16_t)-0.805031331f, + (float16_t)-0.590759702f, (float16_t)-0.806847554f, + (float16_t)-0.588281548f, (float16_t)-0.808656182f, + (float16_t)-0.585797857f, (float16_t)-0.810457198f, + (float16_t)-0.583308653f, (float16_t)-0.812250587f, + (float16_t)-0.580813958f, (float16_t)-0.814036330f, + (float16_t)-0.578313796f, (float16_t)-0.815814411f, + (float16_t)-0.575808191f, (float16_t)-0.817584813f, + (float16_t)-0.573297167f, (float16_t)-0.819347520f, + (float16_t)-0.570780746f, (float16_t)-0.821102515f, + (float16_t)-0.568258953f, (float16_t)-0.822849781f, + (float16_t)-0.565731811f, (float16_t)-0.824589303f, + (float16_t)-0.563199344f, (float16_t)-0.826321063f, + (float16_t)-0.560661576f, (float16_t)-0.828045045f, + (float16_t)-0.558118531f, (float16_t)-0.829761234f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.553016706f, (float16_t)-0.833170165f, + (float16_t)-0.550457973f, (float16_t)-0.834862875f, + (float16_t)-0.547894059f, (float16_t)-0.836547727f, + (float16_t)-0.545324988f, (float16_t)-0.838224706f, + (float16_t)-0.542750785f, (float16_t)-0.839893794f, + (float16_t)-0.540171473f, (float16_t)-0.841554977f, + (float16_t)-0.537587076f, (float16_t)-0.843208240f, + (float16_t)-0.534997620f, (float16_t)-0.844853565f, + (float16_t)-0.532403128f, (float16_t)-0.846490939f, + (float16_t)-0.529803625f, (float16_t)-0.848120345f, + (float16_t)-0.527199135f, (float16_t)-0.849741768f, + (float16_t)-0.524589683f, (float16_t)-0.851355193f, + (float16_t)-0.521975293f, (float16_t)-0.852960605f, + (float16_t)-0.519355990f, (float16_t)-0.854557988f, + (float16_t)-0.516731799f, (float16_t)-0.856147328f, + (float16_t)-0.514102744f, (float16_t)-0.857728610f, + (float16_t)-0.511468850f, (float16_t)-0.859301818f, + (float16_t)-0.508830143f, (float16_t)-0.860866939f, + (float16_t)-0.506186645f, (float16_t)-0.862423956f, + (float16_t)-0.503538384f, (float16_t)-0.863972856f, + (float16_t)-0.500885383f, (float16_t)-0.865513624f, + (float16_t)-0.498227667f, (float16_t)-0.867046246f, + (float16_t)-0.495565262f, (float16_t)-0.868570706f, + (float16_t)-0.492898192f, (float16_t)-0.870086991f, + (float16_t)-0.490226483f, (float16_t)-0.871595087f, + (float16_t)-0.487550160f, (float16_t)-0.873094978f, + (float16_t)-0.484869248f, (float16_t)-0.874586652f, + (float16_t)-0.482183772f, (float16_t)-0.876070094f, + (float16_t)-0.479493758f, (float16_t)-0.877545290f, + (float16_t)-0.476799230f, (float16_t)-0.879012226f, + (float16_t)-0.474100215f, (float16_t)-0.880470889f, + (float16_t)-0.471396737f, (float16_t)-0.881921264f, + (float16_t)-0.468688822f, (float16_t)-0.883363339f, + (float16_t)-0.465976496f, (float16_t)-0.884797098f, + (float16_t)-0.463259784f, (float16_t)-0.886222530f, + (float16_t)-0.460538711f, (float16_t)-0.887639620f, + (float16_t)-0.457813304f, (float16_t)-0.889048356f, + (float16_t)-0.455083587f, (float16_t)-0.890448723f, + (float16_t)-0.452349587f, (float16_t)-0.891840709f, + (float16_t)-0.449611330f, (float16_t)-0.893224301f, + (float16_t)-0.446868840f, (float16_t)-0.894599486f, + (float16_t)-0.444122145f, (float16_t)-0.895966250f, + (float16_t)-0.441371269f, (float16_t)-0.897324581f, + (float16_t)-0.438616239f, (float16_t)-0.898674466f, + (float16_t)-0.435857080f, (float16_t)-0.900015892f, + (float16_t)-0.433093819f, (float16_t)-0.901348847f, + (float16_t)-0.430326481f, (float16_t)-0.902673318f, + (float16_t)-0.427555093f, (float16_t)-0.903989293f, + (float16_t)-0.424779681f, (float16_t)-0.905296759f, + (float16_t)-0.422000271f, (float16_t)-0.906595705f, + (float16_t)-0.419216888f, (float16_t)-0.907886116f, + (float16_t)-0.416429560f, (float16_t)-0.909167983f, + (float16_t)-0.413638312f, (float16_t)-0.910441292f, + (float16_t)-0.410843171f, (float16_t)-0.911706032f, + (float16_t)-0.408044163f, (float16_t)-0.912962190f, + (float16_t)-0.405241314f, (float16_t)-0.914209756f, + (float16_t)-0.402434651f, (float16_t)-0.915448716f, + (float16_t)-0.399624200f, (float16_t)-0.916679060f, + (float16_t)-0.396809987f, (float16_t)-0.917900776f, + (float16_t)-0.393992040f, (float16_t)-0.919113852f, + (float16_t)-0.391170384f, (float16_t)-0.920318277f, + (float16_t)-0.388345047f, (float16_t)-0.921514039f, + (float16_t)-0.385516054f, (float16_t)-0.922701128f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.379847209f, (float16_t)-0.925049241f, + (float16_t)-0.377007410f, (float16_t)-0.926210242f, + (float16_t)-0.374164063f, (float16_t)-0.927362526f, + (float16_t)-0.371317194f, (float16_t)-0.928506080f, + (float16_t)-0.368466830f, (float16_t)-0.929640896f, + (float16_t)-0.365612998f, (float16_t)-0.930766961f, + (float16_t)-0.362755724f, (float16_t)-0.931884266f, + (float16_t)-0.359895037f, (float16_t)-0.932992799f, + (float16_t)-0.357030961f, (float16_t)-0.934092550f, + (float16_t)-0.354163525f, (float16_t)-0.935183510f, + (float16_t)-0.351292756f, (float16_t)-0.936265667f, + (float16_t)-0.348418680f, (float16_t)-0.937339012f, + (float16_t)-0.345541325f, (float16_t)-0.938403534f, + (float16_t)-0.342660717f, (float16_t)-0.939459224f, + (float16_t)-0.339776884f, (float16_t)-0.940506071f, + (float16_t)-0.336889853f, (float16_t)-0.941544065f, + (float16_t)-0.333999651f, (float16_t)-0.942573198f, + (float16_t)-0.331106306f, (float16_t)-0.943593458f, + (float16_t)-0.328209844f, (float16_t)-0.944604837f, + (float16_t)-0.325310292f, (float16_t)-0.945607325f, + (float16_t)-0.322407679f, (float16_t)-0.946600913f, + (float16_t)-0.319502031f, (float16_t)-0.947585591f, + (float16_t)-0.316593376f, (float16_t)-0.948561350f, + (float16_t)-0.313681740f, (float16_t)-0.949528181f, + (float16_t)-0.310767153f, (float16_t)-0.950486074f, + (float16_t)-0.307849640f, (float16_t)-0.951435021f, + (float16_t)-0.304929230f, (float16_t)-0.952375013f, + (float16_t)-0.302005949f, (float16_t)-0.953306040f, + (float16_t)-0.299079826f, (float16_t)-0.954228095f, + (float16_t)-0.296150888f, (float16_t)-0.955141168f, + (float16_t)-0.293219163f, (float16_t)-0.956045251f, + (float16_t)-0.290284677f, (float16_t)-0.956940336f, + (float16_t)-0.287347460f, (float16_t)-0.957826413f, + (float16_t)-0.284407537f, (float16_t)-0.958703475f, + (float16_t)-0.281464938f, (float16_t)-0.959571513f, + (float16_t)-0.278519689f, (float16_t)-0.960430519f, + (float16_t)-0.275571819f, (float16_t)-0.961280486f, + (float16_t)-0.272621355f, (float16_t)-0.962121404f, + (float16_t)-0.269668326f, (float16_t)-0.962953267f, + (float16_t)-0.266712757f, (float16_t)-0.963776066f, + (float16_t)-0.263754679f, (float16_t)-0.964589793f, + (float16_t)-0.260794118f, (float16_t)-0.965394442f, + (float16_t)-0.257831102f, (float16_t)-0.966190003f, + (float16_t)-0.254865660f, (float16_t)-0.966976471f, + (float16_t)-0.251897818f, (float16_t)-0.967753837f, + (float16_t)-0.248927606f, (float16_t)-0.968522094f, + (float16_t)-0.245955050f, (float16_t)-0.969281235f, + (float16_t)-0.242980180f, (float16_t)-0.970031253f, + (float16_t)-0.240003022f, (float16_t)-0.970772141f, + (float16_t)-0.237023606f, (float16_t)-0.971503891f, + (float16_t)-0.234041959f, (float16_t)-0.972226497f, + (float16_t)-0.231058108f, (float16_t)-0.972939952f, + (float16_t)-0.228072083f, (float16_t)-0.973644250f, + (float16_t)-0.225083911f, (float16_t)-0.974339383f, + (float16_t)-0.222093621f, (float16_t)-0.975025345f, + (float16_t)-0.219101240f, (float16_t)-0.975702130f, + (float16_t)-0.216106797f, (float16_t)-0.976369731f, + (float16_t)-0.213110320f, (float16_t)-0.977028143f, + (float16_t)-0.210111837f, (float16_t)-0.977677358f, + (float16_t)-0.207111376f, (float16_t)-0.978317371f, + (float16_t)-0.204108966f, (float16_t)-0.978948175f, + (float16_t)-0.201104635f, (float16_t)-0.979569766f, + (float16_t)-0.198098411f, (float16_t)-0.980182136f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.192080397f, (float16_t)-0.981379193f, + (float16_t)-0.189068664f, (float16_t)-0.981963869f, + (float16_t)-0.186055152f, (float16_t)-0.982539302f, + (float16_t)-0.183039888f, (float16_t)-0.983105487f, + (float16_t)-0.180022901f, (float16_t)-0.983662419f, + (float16_t)-0.177004220f, (float16_t)-0.984210092f, + (float16_t)-0.173983873f, (float16_t)-0.984748502f, + (float16_t)-0.170961889f, (float16_t)-0.985277642f, + (float16_t)-0.167938295f, (float16_t)-0.985797509f, + (float16_t)-0.164913120f, (float16_t)-0.986308097f, + (float16_t)-0.161886394f, (float16_t)-0.986809402f, + (float16_t)-0.158858143f, (float16_t)-0.987301418f, + (float16_t)-0.155828398f, (float16_t)-0.987784142f, + (float16_t)-0.152797185f, (float16_t)-0.988257568f, + (float16_t)-0.149764535f, (float16_t)-0.988721692f, + (float16_t)-0.146730474f, (float16_t)-0.989176510f, + (float16_t)-0.143695033f, (float16_t)-0.989622017f, + (float16_t)-0.140658239f, (float16_t)-0.990058210f, + (float16_t)-0.137620122f, (float16_t)-0.990485084f, + (float16_t)-0.134580709f, (float16_t)-0.990902635f, + (float16_t)-0.131540029f, (float16_t)-0.991310860f, + (float16_t)-0.128498111f, (float16_t)-0.991709754f, + (float16_t)-0.125454983f, (float16_t)-0.992099313f, + (float16_t)-0.122410675f, (float16_t)-0.992479535f, + (float16_t)-0.119365215f, (float16_t)-0.992850414f, + (float16_t)-0.116318631f, (float16_t)-0.993211949f, + (float16_t)-0.113270952f, (float16_t)-0.993564136f, + (float16_t)-0.110222207f, (float16_t)-0.993906970f, + (float16_t)-0.107172425f, (float16_t)-0.994240449f, + (float16_t)-0.104121634f, (float16_t)-0.994564571f, + (float16_t)-0.101069863f, (float16_t)-0.994879331f, + (float16_t)-0.098017140f, (float16_t)-0.995184727f, + (float16_t)-0.094963495f, (float16_t)-0.995480755f, + (float16_t)-0.091908956f, (float16_t)-0.995767414f, + (float16_t)-0.088853553f, (float16_t)-0.996044701f, + (float16_t)-0.085797312f, (float16_t)-0.996312612f, + (float16_t)-0.082740265f, (float16_t)-0.996571146f, + (float16_t)-0.079682438f, (float16_t)-0.996820299f, + (float16_t)-0.076623861f, (float16_t)-0.997060070f, + (float16_t)-0.073564564f, (float16_t)-0.997290457f, + (float16_t)-0.070504573f, (float16_t)-0.997511456f, + (float16_t)-0.067443920f, (float16_t)-0.997723067f, + (float16_t)-0.064382631f, (float16_t)-0.997925286f, + (float16_t)-0.061320736f, (float16_t)-0.998118113f, + (float16_t)-0.058258265f, (float16_t)-0.998301545f, + (float16_t)-0.055195244f, (float16_t)-0.998475581f, + (float16_t)-0.052131705f, (float16_t)-0.998640218f, + (float16_t)-0.049067674f, (float16_t)-0.998795456f, + (float16_t)-0.046003182f, (float16_t)-0.998941293f, + (float16_t)-0.042938257f, (float16_t)-0.999077728f, + (float16_t)-0.039872928f, (float16_t)-0.999204759f, + (float16_t)-0.036807223f, (float16_t)-0.999322385f, + (float16_t)-0.033741172f, (float16_t)-0.999430605f, + (float16_t)-0.030674803f, (float16_t)-0.999529418f, + (float16_t)-0.027608146f, (float16_t)-0.999618822f, + (float16_t)-0.024541229f, (float16_t)-0.999698819f, + (float16_t)-0.021474080f, (float16_t)-0.999769405f, + (float16_t)-0.018406730f, (float16_t)-0.999830582f, + (float16_t)-0.015339206f, (float16_t)-0.999882347f, + (float16_t)-0.012271538f, (float16_t)-0.999924702f, + (float16_t)-0.009203755f, (float16_t)-0.999957645f, + (float16_t)-0.006135885f, (float16_t)-0.999981175f, + (float16_t)-0.003067957f, (float16_t)-0.999995294f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.003067957f, (float16_t)-0.999995294f, + (float16_t)0.006135885f, (float16_t)-0.999981175f, + (float16_t)0.009203755f, (float16_t)-0.999957645f, + (float16_t)0.012271538f, (float16_t)-0.999924702f, + (float16_t)0.015339206f, (float16_t)-0.999882347f, + (float16_t)0.018406730f, (float16_t)-0.999830582f, + (float16_t)0.021474080f, (float16_t)-0.999769405f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.027608146f, (float16_t)-0.999618822f, + (float16_t)0.030674803f, (float16_t)-0.999529418f, + (float16_t)0.033741172f, (float16_t)-0.999430605f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.039872928f, (float16_t)-0.999204759f, + (float16_t)0.042938257f, (float16_t)-0.999077728f, + (float16_t)0.046003182f, (float16_t)-0.998941293f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.052131705f, (float16_t)-0.998640218f, + (float16_t)0.055195244f, (float16_t)-0.998475581f, + (float16_t)0.058258265f, (float16_t)-0.998301545f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.064382631f, (float16_t)-0.997925286f, + (float16_t)0.067443920f, (float16_t)-0.997723067f, + (float16_t)0.070504573f, (float16_t)-0.997511456f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.076623861f, (float16_t)-0.997060070f, + (float16_t)0.079682438f, (float16_t)-0.996820299f, + (float16_t)0.082740265f, (float16_t)-0.996571146f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.088853553f, (float16_t)-0.996044701f, + (float16_t)0.091908956f, (float16_t)-0.995767414f, + (float16_t)0.094963495f, (float16_t)-0.995480755f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.101069863f, (float16_t)-0.994879331f, + (float16_t)0.104121634f, (float16_t)-0.994564571f, + (float16_t)0.107172425f, (float16_t)-0.994240449f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.113270952f, (float16_t)-0.993564136f, + (float16_t)0.116318631f, (float16_t)-0.993211949f, + (float16_t)0.119365215f, (float16_t)-0.992850414f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.125454983f, (float16_t)-0.992099313f, + (float16_t)0.128498111f, (float16_t)-0.991709754f, + (float16_t)0.131540029f, (float16_t)-0.991310860f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.137620122f, (float16_t)-0.990485084f, + (float16_t)0.140658239f, (float16_t)-0.990058210f, + (float16_t)0.143695033f, (float16_t)-0.989622017f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.149764535f, (float16_t)-0.988721692f, + (float16_t)0.152797185f, (float16_t)-0.988257568f, + (float16_t)0.155828398f, (float16_t)-0.987784142f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.161886394f, (float16_t)-0.986809402f, + (float16_t)0.164913120f, (float16_t)-0.986308097f, + (float16_t)0.167938295f, (float16_t)-0.985797509f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.173983873f, (float16_t)-0.984748502f, + (float16_t)0.177004220f, (float16_t)-0.984210092f, + (float16_t)0.180022901f, (float16_t)-0.983662419f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.186055152f, (float16_t)-0.982539302f, + (float16_t)0.189068664f, (float16_t)-0.981963869f, + (float16_t)0.192080397f, (float16_t)-0.981379193f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.198098411f, (float16_t)-0.980182136f, + (float16_t)0.201104635f, (float16_t)-0.979569766f, + (float16_t)0.204108966f, (float16_t)-0.978948175f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.210111837f, (float16_t)-0.977677358f, + (float16_t)0.213110320f, (float16_t)-0.977028143f, + (float16_t)0.216106797f, (float16_t)-0.976369731f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.222093621f, (float16_t)-0.975025345f, + (float16_t)0.225083911f, (float16_t)-0.974339383f, + (float16_t)0.228072083f, (float16_t)-0.973644250f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.234041959f, (float16_t)-0.972226497f, + (float16_t)0.237023606f, (float16_t)-0.971503891f, + (float16_t)0.240003022f, (float16_t)-0.970772141f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.245955050f, (float16_t)-0.969281235f, + (float16_t)0.248927606f, (float16_t)-0.968522094f, + (float16_t)0.251897818f, (float16_t)-0.967753837f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.257831102f, (float16_t)-0.966190003f, + (float16_t)0.260794118f, (float16_t)-0.965394442f, + (float16_t)0.263754679f, (float16_t)-0.964589793f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.269668326f, (float16_t)-0.962953267f, + (float16_t)0.272621355f, (float16_t)-0.962121404f, + (float16_t)0.275571819f, (float16_t)-0.961280486f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.281464938f, (float16_t)-0.959571513f, + (float16_t)0.284407537f, (float16_t)-0.958703475f, + (float16_t)0.287347460f, (float16_t)-0.957826413f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.293219163f, (float16_t)-0.956045251f, + (float16_t)0.296150888f, (float16_t)-0.955141168f, + (float16_t)0.299079826f, (float16_t)-0.954228095f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.304929230f, (float16_t)-0.952375013f, + (float16_t)0.307849640f, (float16_t)-0.951435021f, + (float16_t)0.310767153f, (float16_t)-0.950486074f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.316593376f, (float16_t)-0.948561350f, + (float16_t)0.319502031f, (float16_t)-0.947585591f, + (float16_t)0.322407679f, (float16_t)-0.946600913f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.328209844f, (float16_t)-0.944604837f, + (float16_t)0.331106306f, (float16_t)-0.943593458f, + (float16_t)0.333999651f, (float16_t)-0.942573198f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.339776884f, (float16_t)-0.940506071f, + (float16_t)0.342660717f, (float16_t)-0.939459224f, + (float16_t)0.345541325f, (float16_t)-0.938403534f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.351292756f, (float16_t)-0.936265667f, + (float16_t)0.354163525f, (float16_t)-0.935183510f, + (float16_t)0.357030961f, (float16_t)-0.934092550f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.362755724f, (float16_t)-0.931884266f, + (float16_t)0.365612998f, (float16_t)-0.930766961f, + (float16_t)0.368466830f, (float16_t)-0.929640896f, + (float16_t)0.371317194f, (float16_t)-0.928506080f, + (float16_t)0.374164063f, (float16_t)-0.927362526f, + (float16_t)0.377007410f, (float16_t)-0.926210242f, + (float16_t)0.379847209f, (float16_t)-0.925049241f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.385516054f, (float16_t)-0.922701128f, + (float16_t)0.388345047f, (float16_t)-0.921514039f, + (float16_t)0.391170384f, (float16_t)-0.920318277f, + (float16_t)0.393992040f, (float16_t)-0.919113852f, + (float16_t)0.396809987f, (float16_t)-0.917900776f, + (float16_t)0.399624200f, (float16_t)-0.916679060f, + (float16_t)0.402434651f, (float16_t)-0.915448716f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.408044163f, (float16_t)-0.912962190f, + (float16_t)0.410843171f, (float16_t)-0.911706032f, + (float16_t)0.413638312f, (float16_t)-0.910441292f, + (float16_t)0.416429560f, (float16_t)-0.909167983f, + (float16_t)0.419216888f, (float16_t)-0.907886116f, + (float16_t)0.422000271f, (float16_t)-0.906595705f, + (float16_t)0.424779681f, (float16_t)-0.905296759f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.430326481f, (float16_t)-0.902673318f, + (float16_t)0.433093819f, (float16_t)-0.901348847f, + (float16_t)0.435857080f, (float16_t)-0.900015892f, + (float16_t)0.438616239f, (float16_t)-0.898674466f, + (float16_t)0.441371269f, (float16_t)-0.897324581f, + (float16_t)0.444122145f, (float16_t)-0.895966250f, + (float16_t)0.446868840f, (float16_t)-0.894599486f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.452349587f, (float16_t)-0.891840709f, + (float16_t)0.455083587f, (float16_t)-0.890448723f, + (float16_t)0.457813304f, (float16_t)-0.889048356f, + (float16_t)0.460538711f, (float16_t)-0.887639620f, + (float16_t)0.463259784f, (float16_t)-0.886222530f, + (float16_t)0.465976496f, (float16_t)-0.884797098f, + (float16_t)0.468688822f, (float16_t)-0.883363339f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.474100215f, (float16_t)-0.880470889f, + (float16_t)0.476799230f, (float16_t)-0.879012226f, + (float16_t)0.479493758f, (float16_t)-0.877545290f, + (float16_t)0.482183772f, (float16_t)-0.876070094f, + (float16_t)0.484869248f, (float16_t)-0.874586652f, + (float16_t)0.487550160f, (float16_t)-0.873094978f, + (float16_t)0.490226483f, (float16_t)-0.871595087f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.495565262f, (float16_t)-0.868570706f, + (float16_t)0.498227667f, (float16_t)-0.867046246f, + (float16_t)0.500885383f, (float16_t)-0.865513624f, + (float16_t)0.503538384f, (float16_t)-0.863972856f, + (float16_t)0.506186645f, (float16_t)-0.862423956f, + (float16_t)0.508830143f, (float16_t)-0.860866939f, + (float16_t)0.511468850f, (float16_t)-0.859301818f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.516731799f, (float16_t)-0.856147328f, + (float16_t)0.519355990f, (float16_t)-0.854557988f, + (float16_t)0.521975293f, (float16_t)-0.852960605f, + (float16_t)0.524589683f, (float16_t)-0.851355193f, + (float16_t)0.527199135f, (float16_t)-0.849741768f, + (float16_t)0.529803625f, (float16_t)-0.848120345f, + (float16_t)0.532403128f, (float16_t)-0.846490939f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.537587076f, (float16_t)-0.843208240f, + (float16_t)0.540171473f, (float16_t)-0.841554977f, + (float16_t)0.542750785f, (float16_t)-0.839893794f, + (float16_t)0.545324988f, (float16_t)-0.838224706f, + (float16_t)0.547894059f, (float16_t)-0.836547727f, + (float16_t)0.550457973f, (float16_t)-0.834862875f, + (float16_t)0.553016706f, (float16_t)-0.833170165f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.558118531f, (float16_t)-0.829761234f, + (float16_t)0.560661576f, (float16_t)-0.828045045f, + (float16_t)0.563199344f, (float16_t)-0.826321063f, + (float16_t)0.565731811f, (float16_t)-0.824589303f, + (float16_t)0.568258953f, (float16_t)-0.822849781f, + (float16_t)0.570780746f, (float16_t)-0.821102515f, + (float16_t)0.573297167f, (float16_t)-0.819347520f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.578313796f, (float16_t)-0.815814411f, + (float16_t)0.580813958f, (float16_t)-0.814036330f, + (float16_t)0.583308653f, (float16_t)-0.812250587f, + (float16_t)0.585797857f, (float16_t)-0.810457198f, + (float16_t)0.588281548f, (float16_t)-0.808656182f, + (float16_t)0.590759702f, (float16_t)-0.806847554f, + (float16_t)0.593232295f, (float16_t)-0.805031331f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.598160707f, (float16_t)-0.801376172f, + (float16_t)0.600616479f, (float16_t)-0.799537269f, + (float16_t)0.603066599f, (float16_t)-0.797690841f, + (float16_t)0.605511041f, (float16_t)-0.795836905f, + (float16_t)0.607949785f, (float16_t)-0.793975478f, + (float16_t)0.610382806f, (float16_t)-0.792106577f, + (float16_t)0.612810082f, (float16_t)-0.790230221f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.617647308f, (float16_t)-0.786455214f, + (float16_t)0.620057212f, (float16_t)-0.784556597f, + (float16_t)0.622461279f, (float16_t)-0.782650596f, + (float16_t)0.624859488f, (float16_t)-0.780737229f, + (float16_t)0.627251815f, (float16_t)-0.778816512f, + (float16_t)0.629638239f, (float16_t)-0.776888466f, + (float16_t)0.632018736f, (float16_t)-0.774953107f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.636761861f, (float16_t)-0.771060524f, + (float16_t)0.639124445f, (float16_t)-0.769103338f, + (float16_t)0.641481013f, (float16_t)-0.767138912f, + (float16_t)0.643831543f, (float16_t)-0.765167266f, + (float16_t)0.646176013f, (float16_t)-0.763188417f, + (float16_t)0.648514401f, (float16_t)-0.761202385f, + (float16_t)0.650846685f, (float16_t)-0.759209189f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.655492853f, (float16_t)-0.755201377f, + (float16_t)0.657806693f, (float16_t)-0.753186799f, + (float16_t)0.660114342f, (float16_t)-0.751165132f, + (float16_t)0.662415778f, (float16_t)-0.749136395f, + (float16_t)0.664710978f, (float16_t)-0.747100606f, + (float16_t)0.666999922f, (float16_t)-0.745057785f, + (float16_t)0.669282588f, (float16_t)-0.743007952f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.673829000f, (float16_t)-0.738887324f, + (float16_t)0.676092704f, (float16_t)-0.736816569f, + (float16_t)0.678350043f, (float16_t)-0.734738878f, + (float16_t)0.680600998f, (float16_t)-0.732654272f, + (float16_t)0.682845546f, (float16_t)-0.730562769f, + (float16_t)0.685083668f, (float16_t)-0.728464390f, + (float16_t)0.687315341f, (float16_t)-0.726359155f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.691759258f, (float16_t)-0.722128194f, + (float16_t)0.693971461f, (float16_t)-0.720002508f, + (float16_t)0.696177131f, (float16_t)-0.717870045f, + (float16_t)0.698376249f, (float16_t)-0.715730825f, + (float16_t)0.700568794f, (float16_t)-0.713584869f, + (float16_t)0.702754744f, (float16_t)-0.711432196f, + (float16_t)0.704934080f, (float16_t)-0.709272826f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.709272826f, (float16_t)-0.704934080f, + (float16_t)0.711432196f, (float16_t)-0.702754744f, + (float16_t)0.713584869f, (float16_t)-0.700568794f, + (float16_t)0.715730825f, (float16_t)-0.698376249f, + (float16_t)0.717870045f, (float16_t)-0.696177131f, + (float16_t)0.720002508f, (float16_t)-0.693971461f, + (float16_t)0.722128194f, (float16_t)-0.691759258f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.726359155f, (float16_t)-0.687315341f, + (float16_t)0.728464390f, (float16_t)-0.685083668f, + (float16_t)0.730562769f, (float16_t)-0.682845546f, + (float16_t)0.732654272f, (float16_t)-0.680600998f, + (float16_t)0.734738878f, (float16_t)-0.678350043f, + (float16_t)0.736816569f, (float16_t)-0.676092704f, + (float16_t)0.738887324f, (float16_t)-0.673829000f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.743007952f, (float16_t)-0.669282588f, + (float16_t)0.745057785f, (float16_t)-0.666999922f, + (float16_t)0.747100606f, (float16_t)-0.664710978f, + (float16_t)0.749136395f, (float16_t)-0.662415778f, + (float16_t)0.751165132f, (float16_t)-0.660114342f, + (float16_t)0.753186799f, (float16_t)-0.657806693f, + (float16_t)0.755201377f, (float16_t)-0.655492853f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.759209189f, (float16_t)-0.650846685f, + (float16_t)0.761202385f, (float16_t)-0.648514401f, + (float16_t)0.763188417f, (float16_t)-0.646176013f, + (float16_t)0.765167266f, (float16_t)-0.643831543f, + (float16_t)0.767138912f, (float16_t)-0.641481013f, + (float16_t)0.769103338f, (float16_t)-0.639124445f, + (float16_t)0.771060524f, (float16_t)-0.636761861f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.774953107f, (float16_t)-0.632018736f, + (float16_t)0.776888466f, (float16_t)-0.629638239f, + (float16_t)0.778816512f, (float16_t)-0.627251815f, + (float16_t)0.780737229f, (float16_t)-0.624859488f, + (float16_t)0.782650596f, (float16_t)-0.622461279f, + (float16_t)0.784556597f, (float16_t)-0.620057212f, + (float16_t)0.786455214f, (float16_t)-0.617647308f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.790230221f, (float16_t)-0.612810082f, + (float16_t)0.792106577f, (float16_t)-0.610382806f, + (float16_t)0.793975478f, (float16_t)-0.607949785f, + (float16_t)0.795836905f, (float16_t)-0.605511041f, + (float16_t)0.797690841f, (float16_t)-0.603066599f, + (float16_t)0.799537269f, (float16_t)-0.600616479f, + (float16_t)0.801376172f, (float16_t)-0.598160707f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.805031331f, (float16_t)-0.593232295f, + (float16_t)0.806847554f, (float16_t)-0.590759702f, + (float16_t)0.808656182f, (float16_t)-0.588281548f, + (float16_t)0.810457198f, (float16_t)-0.585797857f, + (float16_t)0.812250587f, (float16_t)-0.583308653f, + (float16_t)0.814036330f, (float16_t)-0.580813958f, + (float16_t)0.815814411f, (float16_t)-0.578313796f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.819347520f, (float16_t)-0.573297167f, + (float16_t)0.821102515f, (float16_t)-0.570780746f, + (float16_t)0.822849781f, (float16_t)-0.568258953f, + (float16_t)0.824589303f, (float16_t)-0.565731811f, + (float16_t)0.826321063f, (float16_t)-0.563199344f, + (float16_t)0.828045045f, (float16_t)-0.560661576f, + (float16_t)0.829761234f, (float16_t)-0.558118531f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.833170165f, (float16_t)-0.553016706f, + (float16_t)0.834862875f, (float16_t)-0.550457973f, + (float16_t)0.836547727f, (float16_t)-0.547894059f, + (float16_t)0.838224706f, (float16_t)-0.545324988f, + (float16_t)0.839893794f, (float16_t)-0.542750785f, + (float16_t)0.841554977f, (float16_t)-0.540171473f, + (float16_t)0.843208240f, (float16_t)-0.537587076f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.846490939f, (float16_t)-0.532403128f, + (float16_t)0.848120345f, (float16_t)-0.529803625f, + (float16_t)0.849741768f, (float16_t)-0.527199135f, + (float16_t)0.851355193f, (float16_t)-0.524589683f, + (float16_t)0.852960605f, (float16_t)-0.521975293f, + (float16_t)0.854557988f, (float16_t)-0.519355990f, + (float16_t)0.856147328f, (float16_t)-0.516731799f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.859301818f, (float16_t)-0.511468850f, + (float16_t)0.860866939f, (float16_t)-0.508830143f, + (float16_t)0.862423956f, (float16_t)-0.506186645f, + (float16_t)0.863972856f, (float16_t)-0.503538384f, + (float16_t)0.865513624f, (float16_t)-0.500885383f, + (float16_t)0.867046246f, (float16_t)-0.498227667f, + (float16_t)0.868570706f, (float16_t)-0.495565262f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.871595087f, (float16_t)-0.490226483f, + (float16_t)0.873094978f, (float16_t)-0.487550160f, + (float16_t)0.874586652f, (float16_t)-0.484869248f, + (float16_t)0.876070094f, (float16_t)-0.482183772f, + (float16_t)0.877545290f, (float16_t)-0.479493758f, + (float16_t)0.879012226f, (float16_t)-0.476799230f, + (float16_t)0.880470889f, (float16_t)-0.474100215f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.883363339f, (float16_t)-0.468688822f, + (float16_t)0.884797098f, (float16_t)-0.465976496f, + (float16_t)0.886222530f, (float16_t)-0.463259784f, + (float16_t)0.887639620f, (float16_t)-0.460538711f, + (float16_t)0.889048356f, (float16_t)-0.457813304f, + (float16_t)0.890448723f, (float16_t)-0.455083587f, + (float16_t)0.891840709f, (float16_t)-0.452349587f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.894599486f, (float16_t)-0.446868840f, + (float16_t)0.895966250f, (float16_t)-0.444122145f, + (float16_t)0.897324581f, (float16_t)-0.441371269f, + (float16_t)0.898674466f, (float16_t)-0.438616239f, + (float16_t)0.900015892f, (float16_t)-0.435857080f, + (float16_t)0.901348847f, (float16_t)-0.433093819f, + (float16_t)0.902673318f, (float16_t)-0.430326481f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.905296759f, (float16_t)-0.424779681f, + (float16_t)0.906595705f, (float16_t)-0.422000271f, + (float16_t)0.907886116f, (float16_t)-0.419216888f, + (float16_t)0.909167983f, (float16_t)-0.416429560f, + (float16_t)0.910441292f, (float16_t)-0.413638312f, + (float16_t)0.911706032f, (float16_t)-0.410843171f, + (float16_t)0.912962190f, (float16_t)-0.408044163f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.915448716f, (float16_t)-0.402434651f, + (float16_t)0.916679060f, (float16_t)-0.399624200f, + (float16_t)0.917900776f, (float16_t)-0.396809987f, + (float16_t)0.919113852f, (float16_t)-0.393992040f, + (float16_t)0.920318277f, (float16_t)-0.391170384f, + (float16_t)0.921514039f, (float16_t)-0.388345047f, + (float16_t)0.922701128f, (float16_t)-0.385516054f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.925049241f, (float16_t)-0.379847209f, + (float16_t)0.926210242f, (float16_t)-0.377007410f, + (float16_t)0.927362526f, (float16_t)-0.374164063f, + (float16_t)0.928506080f, (float16_t)-0.371317194f, + (float16_t)0.929640896f, (float16_t)-0.368466830f, + (float16_t)0.930766961f, (float16_t)-0.365612998f, + (float16_t)0.931884266f, (float16_t)-0.362755724f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.934092550f, (float16_t)-0.357030961f, + (float16_t)0.935183510f, (float16_t)-0.354163525f, + (float16_t)0.936265667f, (float16_t)-0.351292756f, + (float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.938403534f, (float16_t)-0.345541325f, + (float16_t)0.939459224f, (float16_t)-0.342660717f, + (float16_t)0.940506071f, (float16_t)-0.339776884f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.942573198f, (float16_t)-0.333999651f, + (float16_t)0.943593458f, (float16_t)-0.331106306f, + (float16_t)0.944604837f, (float16_t)-0.328209844f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.946600913f, (float16_t)-0.322407679f, + (float16_t)0.947585591f, (float16_t)-0.319502031f, + (float16_t)0.948561350f, (float16_t)-0.316593376f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.950486074f, (float16_t)-0.310767153f, + (float16_t)0.951435021f, (float16_t)-0.307849640f, + (float16_t)0.952375013f, (float16_t)-0.304929230f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.954228095f, (float16_t)-0.299079826f, + (float16_t)0.955141168f, (float16_t)-0.296150888f, + (float16_t)0.956045251f, (float16_t)-0.293219163f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.957826413f, (float16_t)-0.287347460f, + (float16_t)0.958703475f, (float16_t)-0.284407537f, + (float16_t)0.959571513f, (float16_t)-0.281464938f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.961280486f, (float16_t)-0.275571819f, + (float16_t)0.962121404f, (float16_t)-0.272621355f, + (float16_t)0.962953267f, (float16_t)-0.269668326f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.964589793f, (float16_t)-0.263754679f, + (float16_t)0.965394442f, (float16_t)-0.260794118f, + (float16_t)0.966190003f, (float16_t)-0.257831102f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.967753837f, (float16_t)-0.251897818f, + (float16_t)0.968522094f, (float16_t)-0.248927606f, + (float16_t)0.969281235f, (float16_t)-0.245955050f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.970772141f, (float16_t)-0.240003022f, + (float16_t)0.971503891f, (float16_t)-0.237023606f, + (float16_t)0.972226497f, (float16_t)-0.234041959f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.973644250f, (float16_t)-0.228072083f, + (float16_t)0.974339383f, (float16_t)-0.225083911f, + (float16_t)0.975025345f, (float16_t)-0.222093621f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.976369731f, (float16_t)-0.216106797f, + (float16_t)0.977028143f, (float16_t)-0.213110320f, + (float16_t)0.977677358f, (float16_t)-0.210111837f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.978948175f, (float16_t)-0.204108966f, + (float16_t)0.979569766f, (float16_t)-0.201104635f, + (float16_t)0.980182136f, (float16_t)-0.198098411f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.981379193f, (float16_t)-0.192080397f, + (float16_t)0.981963869f, (float16_t)-0.189068664f, + (float16_t)0.982539302f, (float16_t)-0.186055152f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.983662419f, (float16_t)-0.180022901f, + (float16_t)0.984210092f, (float16_t)-0.177004220f, + (float16_t)0.984748502f, (float16_t)-0.173983873f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.985797509f, (float16_t)-0.167938295f, + (float16_t)0.986308097f, (float16_t)-0.164913120f, + (float16_t)0.986809402f, (float16_t)-0.161886394f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.987784142f, (float16_t)-0.155828398f, + (float16_t)0.988257568f, (float16_t)-0.152797185f, + (float16_t)0.988721692f, (float16_t)-0.149764535f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.989622017f, (float16_t)-0.143695033f, + (float16_t)0.990058210f, (float16_t)-0.140658239f, + (float16_t)0.990485084f, (float16_t)-0.137620122f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.991310860f, (float16_t)-0.131540029f, + (float16_t)0.991709754f, (float16_t)-0.128498111f, + (float16_t)0.992099313f, (float16_t)-0.125454983f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.992850414f, (float16_t)-0.119365215f, + (float16_t)0.993211949f, (float16_t)-0.116318631f, + (float16_t)0.993564136f, (float16_t)-0.113270952f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.994240449f, (float16_t)-0.107172425f, + (float16_t)0.994564571f, (float16_t)-0.104121634f, + (float16_t)0.994879331f, (float16_t)-0.101069863f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.995480755f, (float16_t)-0.094963495f, + (float16_t)0.995767414f, (float16_t)-0.091908956f, + (float16_t)0.996044701f, (float16_t)-0.088853553f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.996571146f, (float16_t)-0.082740265f, + (float16_t)0.996820299f, (float16_t)-0.079682438f, + (float16_t)0.997060070f, (float16_t)-0.076623861f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.997511456f, (float16_t)-0.070504573f, + (float16_t)0.997723067f, (float16_t)-0.067443920f, + (float16_t)0.997925286f, (float16_t)-0.064382631f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.998301545f, (float16_t)-0.058258265f, + (float16_t)0.998475581f, (float16_t)-0.055195244f, + (float16_t)0.998640218f, (float16_t)-0.052131705f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.998941293f, (float16_t)-0.046003182f, + (float16_t)0.999077728f, (float16_t)-0.042938257f, + (float16_t)0.999204759f, (float16_t)-0.039872928f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.999430605f, (float16_t)-0.033741172f, + (float16_t)0.999529418f, (float16_t)-0.030674803f, + (float16_t)0.999618822f, (float16_t)-0.027608146f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999769405f, (float16_t)-0.021474080f, + (float16_t)0.999830582f, (float16_t)-0.018406730f, + (float16_t)0.999882347f, (float16_t)-0.015339206f, + (float16_t)0.999924702f, (float16_t)-0.012271538f, + (float16_t)0.999957645f, (float16_t)-0.009203755f, + (float16_t)0.999981175f, (float16_t)-0.006135885f, + (float16_t)0.999995294f, (float16_t)-0.003067957f +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +*
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } 
+* \par +* where N = 4096 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_4096[8192] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999998823f, (float16_t)0.001533980f, + (float16_t)0.999995294f, (float16_t)0.003067957f, + (float16_t)0.999989411f, (float16_t)0.004601926f, + (float16_t)0.999981175f, (float16_t)0.006135885f, + (float16_t)0.999970586f, (float16_t)0.007669829f, + (float16_t)0.999957645f, (float16_t)0.009203755f, + (float16_t)0.999942350f, (float16_t)0.010737659f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)0.999904701f, (float16_t)0.013805389f, + (float16_t)0.999882347f, (float16_t)0.015339206f, + (float16_t)0.999857641f, (float16_t)0.016872988f, + (float16_t)0.999830582f, (float16_t)0.018406730f, + (float16_t)0.999801170f, (float16_t)0.019940429f, + (float16_t)0.999769405f, (float16_t)0.021474080f, + (float16_t)0.999735288f, (float16_t)0.023007681f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999659997f, (float16_t)0.026074718f, + (float16_t)0.999618822f, (float16_t)0.027608146f, + (float16_t)0.999575296f, (float16_t)0.029141509f, + (float16_t)0.999529418f, (float16_t)0.030674803f, + (float16_t)0.999481187f, (float16_t)0.032208025f, + (float16_t)0.999430605f, (float16_t)0.033741172f, + (float16_t)0.999377670f, (float16_t)0.035274239f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.999264747f, (float16_t)0.038340120f, + (float16_t)0.999204759f, (float16_t)0.039872928f, + (float16_t)0.999142419f, (float16_t)0.041405641f, + (float16_t)0.999077728f, (float16_t)0.042938257f, + (float16_t)0.999010686f, (float16_t)0.044470772f, + (float16_t)0.998941293f, (float16_t)0.046003182f, + (float16_t)0.998869550f, (float16_t)0.047535484f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.998719012f, (float16_t)0.050599749f, + (float16_t)0.998640218f, (float16_t)0.052131705f, + (float16_t)0.998559074f, (float16_t)0.053663538f, + (float16_t)0.998475581f, (float16_t)0.055195244f, + (float16_t)0.998389737f, (float16_t)0.056726821f, + (float16_t)0.998301545f, (float16_t)0.058258265f, + (float16_t)0.998211003f, (float16_t)0.059789571f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.998022874f, (float16_t)0.062851758f, + (float16_t)0.997925286f, (float16_t)0.064382631f, + (float16_t)0.997825350f, (float16_t)0.065913353f, + (float16_t)0.997723067f, (float16_t)0.067443920f, + (float16_t)0.997618435f, (float16_t)0.068974328f, + (float16_t)0.997511456f, (float16_t)0.070504573f, + (float16_t)0.997402130f, (float16_t)0.072034653f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.997176437f, (float16_t)0.075094301f, + (float16_t)0.997060070f, (float16_t)0.076623861f, + (float16_t)0.996941358f, (float16_t)0.078153242f, + (float16_t)0.996820299f, (float16_t)0.079682438f, + (float16_t)0.996696895f, (float16_t)0.081211447f, + (float16_t)0.996571146f, (float16_t)0.082740265f, + (float16_t)0.996443051f, (float16_t)0.084268888f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.996179829f, (float16_t)0.087325535f, + (float16_t)0.996044701f, (float16_t)0.088853553f, + (float16_t)0.995907229f, (float16_t)0.090381361f, + (float16_t)0.995767414f, (float16_t)0.091908956f, + (float16_t)0.995625256f, (float16_t)0.093436336f, + (float16_t)0.995480755f, (float16_t)0.094963495f, + (float16_t)0.995333912f, (float16_t)0.096490431f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.995033199f, (float16_t)0.099543619f, + (float16_t)0.994879331f, (float16_t)0.101069863f, + (float16_t)0.994723121f, (float16_t)0.102595869f, + (float16_t)0.994564571f, (float16_t)0.104121634f, + (float16_t)0.994403680f, (float16_t)0.105647154f, + (float16_t)0.994240449f, (float16_t)0.107172425f, + (float16_t)0.994074879f, (float16_t)0.108697444f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.993736722f, (float16_t)0.111746711f, + (float16_t)0.993564136f, (float16_t)0.113270952f, + (float16_t)0.993389211f, (float16_t)0.114794927f, + (float16_t)0.993211949f, (float16_t)0.116318631f, + (float16_t)0.993032350f, (float16_t)0.117842062f, + (float16_t)0.992850414f, (float16_t)0.119365215f, + (float16_t)0.992666142f, (float16_t)0.120888087f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.992290591f, (float16_t)0.123932975f, + (float16_t)0.992099313f, (float16_t)0.125454983f, + (float16_t)0.991905700f, (float16_t)0.126976696f, + (float16_t)0.991709754f, (float16_t)0.128498111f, + (float16_t)0.991511473f, (float16_t)0.130019223f, + (float16_t)0.991310860f, (float16_t)0.131540029f, + (float16_t)0.991107914f, (float16_t)0.133060525f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.990695025f, (float16_t)0.136100575f, + (float16_t)0.990485084f, (float16_t)0.137620122f, + (float16_t)0.990272812f, (float16_t)0.139139344f, + (float16_t)0.990058210f, (float16_t)0.140658239f, + (float16_t)0.989841278f, (float16_t)0.142176804f, + (float16_t)0.989622017f, (float16_t)0.143695033f, + (float16_t)0.989400428f, (float16_t)0.145212925f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.988950265f, (float16_t)0.148247679f, + (float16_t)0.988721692f, (float16_t)0.149764535f, + (float16_t)0.988490793f, (float16_t)0.151281038f, + (float16_t)0.988257568f, (float16_t)0.152797185f, + (float16_t)0.988022017f, (float16_t)0.154312973f, + (float16_t)0.987784142f, (float16_t)0.155828398f, + (float16_t)0.987543942f, (float16_t)0.157343456f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.987056571f, (float16_t)0.160372457f, + (float16_t)0.986809402f, (float16_t)0.161886394f, + (float16_t)0.986559910f, (float16_t)0.163399949f, + (float16_t)0.986308097f, (float16_t)0.164913120f, + (float16_t)0.986053963f, (float16_t)0.166425904f, + (float16_t)0.985797509f, (float16_t)0.167938295f, + (float16_t)0.985538735f, (float16_t)0.169450291f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.985014231f, (float16_t)0.172473084f, + (float16_t)0.984748502f, (float16_t)0.173983873f, + (float16_t)0.984480455f, (float16_t)0.175494253f, + (float16_t)0.984210092f, (float16_t)0.177004220f, + (float16_t)0.983937413f, (float16_t)0.178513771f, + (float16_t)0.983662419f, (float16_t)0.180022901f, + (float16_t)0.983385110f, (float16_t)0.181531608f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.982823551f, (float16_t)0.184547737f, + (float16_t)0.982539302f, (float16_t)0.186055152f, + (float16_t)0.982252741f, (float16_t)0.187562129f, + (float16_t)0.981963869f, (float16_t)0.189068664f, + (float16_t)0.981672686f, (float16_t)0.190574755f, + (float16_t)0.981379193f, (float16_t)0.192080397f, + (float16_t)0.981083391f, (float16_t)0.193585587f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.980484862f, (float16_t)0.196594598f, + (float16_t)0.980182136f, (float16_t)0.198098411f, + (float16_t)0.979877104f, (float16_t)0.199601758f, + (float16_t)0.979569766f, (float16_t)0.201104635f, + (float16_t)0.979260123f, (float16_t)0.202607039f, + (float16_t)0.978948175f, (float16_t)0.204108966f, + (float16_t)0.978633924f, (float16_t)0.205610413f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.977998515f, (float16_t)0.208611852f, + (float16_t)0.977677358f, (float16_t)0.210111837f, + (float16_t)0.977353900f, (float16_t)0.211611327f, + (float16_t)0.977028143f, (float16_t)0.213110320f, + (float16_t)0.976700086f, (float16_t)0.214608811f, + (float16_t)0.976369731f, (float16_t)0.216106797f, + (float16_t)0.976037079f, (float16_t)0.217604275f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.975364885f, (float16_t)0.220597690f, + (float16_t)0.975025345f, (float16_t)0.222093621f, + (float16_t)0.974683511f, (float16_t)0.223589029f, + (float16_t)0.974339383f, (float16_t)0.225083911f, + (float16_t)0.973992962f, (float16_t)0.226578264f, + (float16_t)0.973644250f, (float16_t)0.228072083f, + (float16_t)0.973293246f, (float16_t)0.229565366f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.972584369f, (float16_t)0.232550307f, + (float16_t)0.972226497f, (float16_t)0.234041959f, + (float16_t)0.971866337f, (float16_t)0.235533059f, + (float16_t)0.971503891f, (float16_t)0.237023606f, + (float16_t)0.971139158f, (float16_t)0.238513595f, + (float16_t)0.970772141f, (float16_t)0.240003022f, + (float16_t)0.970402839f, (float16_t)0.241491885f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.969657385f, (float16_t)0.244467903f, + (float16_t)0.969281235f, (float16_t)0.245955050f, + (float16_t)0.968902805f, (float16_t)0.247441619f, + (float16_t)0.968522094f, (float16_t)0.248927606f, + (float16_t)0.968139105f, (float16_t)0.250413007f, + (float16_t)0.967753837f, (float16_t)0.251897818f, + (float16_t)0.967366292f, (float16_t)0.253382037f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.966584374f, (float16_t)0.256348682f, + (float16_t)0.966190003f, (float16_t)0.257831102f, + (float16_t)0.965793359f, (float16_t)0.259312915f, + (float16_t)0.965394442f, (float16_t)0.260794118f, + (float16_t)0.964993253f, (float16_t)0.262274707f, + (float16_t)0.964589793f, (float16_t)0.263754679f, + (float16_t)0.964184064f, (float16_t)0.265234030f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.963365800f, (float16_t)0.268190857f, + (float16_t)0.962953267f, (float16_t)0.269668326f, + (float16_t)0.962538468f, (float16_t)0.271145160f, + (float16_t)0.962121404f, (float16_t)0.272621355f, + (float16_t)0.961702077f, (float16_t)0.274096910f, + (float16_t)0.961280486f, (float16_t)0.275571819f, + (float16_t)0.960856633f, (float16_t)0.277046080f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.960002146f, (float16_t)0.279992643f, + (float16_t)0.959571513f, (float16_t)0.281464938f, + (float16_t)0.959138622f, (float16_t)0.282936570f, + (float16_t)0.958703475f, (float16_t)0.284407537f, + (float16_t)0.958266071f, (float16_t)0.285877835f, + (float16_t)0.957826413f, (float16_t)0.287347460f, + (float16_t)0.957384501f, (float16_t)0.288816408f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.956493919f, (float16_t)0.291752263f, + (float16_t)0.956045251f, (float16_t)0.293219163f, + (float16_t)0.955594334f, (float16_t)0.294685372f, + (float16_t)0.955141168f, (float16_t)0.296150888f, + (float16_t)0.954685755f, (float16_t)0.297615707f, + (float16_t)0.954228095f, (float16_t)0.299079826f, + (float16_t)0.953768190f, (float16_t)0.300543241f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.952841648f, (float16_t)0.303467947f, + (float16_t)0.952375013f, (float16_t)0.304929230f, + (float16_t)0.951906137f, (float16_t)0.306389795f, + (float16_t)0.951435021f, (float16_t)0.307849640f, + (float16_t)0.950961666f, (float16_t)0.309308760f, + (float16_t)0.950486074f, (float16_t)0.310767153f, + (float16_t)0.950008245f, (float16_t)0.312224814f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.949045882f, (float16_t)0.315137929f, + (float16_t)0.948561350f, (float16_t)0.316593376f, + (float16_t)0.948074586f, (float16_t)0.318048077f, + (float16_t)0.947585591f, (float16_t)0.319502031f, + (float16_t)0.947094366f, (float16_t)0.320955232f, + (float16_t)0.946600913f, (float16_t)0.322407679f, + (float16_t)0.946105232f, (float16_t)0.323859367f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.945107193f, (float16_t)0.326760452f, + (float16_t)0.944604837f, (float16_t)0.328209844f, + (float16_t)0.944100258f, (float16_t)0.329658463f, + (float16_t)0.943593458f, (float16_t)0.331106306f, + (float16_t)0.943084437f, (float16_t)0.332553370f, + (float16_t)0.942573198f, (float16_t)0.333999651f, + (float16_t)0.942059740f, (float16_t)0.335445147f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.941026175f, (float16_t)0.338333767f, + (float16_t)0.940506071f, (float16_t)0.339776884f, + (float16_t)0.939983753f, (float16_t)0.341219202f, + (float16_t)0.939459224f, (float16_t)0.342660717f, + (float16_t)0.938932484f, (float16_t)0.344101426f, + (float16_t)0.938403534f, (float16_t)0.345541325f, + (float16_t)0.937872376f, (float16_t)0.346980411f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.936803442f, (float16_t)0.349856130f, + (float16_t)0.936265667f, (float16_t)0.351292756f, + (float16_t)0.935725689f, (float16_t)0.352728556f, + (float16_t)0.935183510f, (float16_t)0.354163525f, + (float16_t)0.934639130f, (float16_t)0.355597662f, + (float16_t)0.934092550f, (float16_t)0.357030961f, + (float16_t)0.933543773f, (float16_t)0.358463421f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.932439629f, (float16_t)0.361325806f, + (float16_t)0.931884266f, (float16_t)0.362755724f, + (float16_t)0.931326709f, (float16_t)0.364184790f, + (float16_t)0.930766961f, (float16_t)0.365612998f, + (float16_t)0.930205023f, (float16_t)0.367040346f, + (float16_t)0.929640896f, (float16_t)0.368466830f, + (float16_t)0.929074581f, (float16_t)0.369892447f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.927935395f, (float16_t)0.372741067f, + (float16_t)0.927362526f, (float16_t)0.374164063f, + (float16_t)0.926787474f, (float16_t)0.375586178f, + (float16_t)0.926210242f, (float16_t)0.377007410f, + (float16_t)0.925630831f, (float16_t)0.378427755f, + (float16_t)0.925049241f, (float16_t)0.379847209f, + (float16_t)0.924465474f, (float16_t)0.381265769f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.923291417f, (float16_t)0.384100195f, + (float16_t)0.922701128f, (float16_t)0.385516054f, + (float16_t)0.922108669f, (float16_t)0.386931006f, + (float16_t)0.921514039f, (float16_t)0.388345047f, + (float16_t)0.920917242f, (float16_t)0.389758174f, + (float16_t)0.920318277f, (float16_t)0.391170384f, + (float16_t)0.919717146f, (float16_t)0.392581674f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.918508394f, (float16_t)0.395401479f, + (float16_t)0.917900776f, (float16_t)0.396809987f, + (float16_t)0.917290997f, (float16_t)0.398217562f, + (float16_t)0.916679060f, (float16_t)0.399624200f, + (float16_t)0.916064966f, (float16_t)0.401029897f, + (float16_t)0.915448716f, (float16_t)0.402434651f, + (float16_t)0.914830312f, (float16_t)0.403838458f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.913587048f, (float16_t)0.406643217f, + (float16_t)0.912962190f, (float16_t)0.408044163f, + (float16_t)0.912335185f, (float16_t)0.409444149f, + (float16_t)0.911706032f, (float16_t)0.410843171f, + (float16_t)0.911074734f, (float16_t)0.412241227f, + (float16_t)0.910441292f, (float16_t)0.413638312f, + (float16_t)0.909805708f, (float16_t)0.415034424f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.908528119f, (float16_t)0.417823716f, + (float16_t)0.907886116f, (float16_t)0.419216888f, + (float16_t)0.907241978f, (float16_t)0.420609074f, + (float16_t)0.906595705f, (float16_t)0.422000271f, + (float16_t)0.905947298f, (float16_t)0.423390474f, + (float16_t)0.905296759f, (float16_t)0.424779681f, + (float16_t)0.904644091f, (float16_t)0.426167889f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.903332368f, (float16_t)0.428941292f, + (float16_t)0.902673318f, (float16_t)0.430326481f, + (float16_t)0.902012144f, (float16_t)0.431710658f, + (float16_t)0.901348847f, (float16_t)0.433093819f, + (float16_t)0.900683429f, (float16_t)0.434475961f, + (float16_t)0.900015892f, (float16_t)0.435857080f, + (float16_t)0.899346237f, (float16_t)0.437237174f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.898000580f, (float16_t)0.439994271f, + (float16_t)0.897324581f, (float16_t)0.441371269f, + (float16_t)0.896646470f, (float16_t)0.442747228f, + (float16_t)0.895966250f, (float16_t)0.444122145f, + (float16_t)0.895283921f, (float16_t)0.445496017f, + (float16_t)0.894599486f, (float16_t)0.446868840f, + (float16_t)0.893912945f, (float16_t)0.448240612f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.892533555f, (float16_t)0.450980989f, + (float16_t)0.891840709f, (float16_t)0.452349587f, + (float16_t)0.891145765f, (float16_t)0.453717121f, + (float16_t)0.890448723f, (float16_t)0.455083587f, + (float16_t)0.889749586f, (float16_t)0.456448982f, + (float16_t)0.889048356f, (float16_t)0.457813304f, + (float16_t)0.888345033f, (float16_t)0.459176548f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.886932119f, (float16_t)0.461899791f, + (float16_t)0.886222530f, (float16_t)0.463259784f, + (float16_t)0.885510856f, (float16_t)0.464618686f, + (float16_t)0.884797098f, (float16_t)0.465976496f, + (float16_t)0.884081259f, (float16_t)0.467333209f, + (float16_t)0.883363339f, (float16_t)0.468688822f, + (float16_t)0.882643340f, (float16_t)0.470043332f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.881197113f, (float16_t)0.472749032f, + (float16_t)0.880470889f, (float16_t)0.474100215f, + (float16_t)0.879742593f, (float16_t)0.475450282f, + (float16_t)0.879012226f, (float16_t)0.476799230f, + (float16_t)0.878279792f, (float16_t)0.478147056f, + (float16_t)0.877545290f, (float16_t)0.479493758f, + (float16_t)0.876808724f, (float16_t)0.480839331f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.875329403f, (float16_t)0.483527079f, + (float16_t)0.874586652f, (float16_t)0.484869248f, + (float16_t)0.873841843f, (float16_t)0.486210276f, + (float16_t)0.873094978f, (float16_t)0.487550160f, + (float16_t)0.872346059f, (float16_t)0.488888897f, + (float16_t)0.871595087f, (float16_t)0.490226483f, + (float16_t)0.870842063f, (float16_t)0.491562916f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.869329871f, (float16_t)0.494232309f, + (float16_t)0.868570706f, (float16_t)0.495565262f, + (float16_t)0.867809497f, (float16_t)0.496897049f, + (float16_t)0.867046246f, (float16_t)0.498227667f, + (float16_t)0.866280954f, (float16_t)0.499557113f, + (float16_t)0.865513624f, (float16_t)0.500885383f, + (float16_t)0.864744258f, (float16_t)0.502212474f, + (float16_t)0.863972856f, (float16_t)0.503538384f, + (float16_t)0.863199422f, (float16_t)0.504863109f, + (float16_t)0.862423956f, (float16_t)0.506186645f, + (float16_t)0.861646461f, (float16_t)0.507508991f, + (float16_t)0.860866939f, (float16_t)0.508830143f, + (float16_t)0.860085390f, (float16_t)0.510150097f, + (float16_t)0.859301818f, (float16_t)0.511468850f, + (float16_t)0.858516224f, (float16_t)0.512786401f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.856938977f, (float16_t)0.515417878f, + (float16_t)0.856147328f, (float16_t)0.516731799f, + (float16_t)0.855353665f, (float16_t)0.518044504f, + (float16_t)0.854557988f, (float16_t)0.519355990f, + (float16_t)0.853760301f, (float16_t)0.520666254f, + (float16_t)0.852960605f, (float16_t)0.521975293f, + (float16_t)0.852158902f, (float16_t)0.523283103f, + (float16_t)0.851355193f, (float16_t)0.524589683f, + (float16_t)0.850549481f, (float16_t)0.525895027f, + (float16_t)0.849741768f, (float16_t)0.527199135f, + (float16_t)0.848932055f, (float16_t)0.528502002f, + (float16_t)0.848120345f, (float16_t)0.529803625f, + (float16_t)0.847306639f, (float16_t)0.531104001f, + (float16_t)0.846490939f, (float16_t)0.532403128f, + (float16_t)0.845673247f, (float16_t)0.533701002f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.844031895f, (float16_t)0.536292979f, + (float16_t)0.843208240f, (float16_t)0.537587076f, + (float16_t)0.842382600f, (float16_t)0.538879909f, + (float16_t)0.841554977f, (float16_t)0.540171473f, + (float16_t)0.840725375f, (float16_t)0.541461766f, + (float16_t)0.839893794f, (float16_t)0.542750785f, + (float16_t)0.839060237f, (float16_t)0.544038527f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.837387202f, (float16_t)0.546610167f, + (float16_t)0.836547727f, (float16_t)0.547894059f, + (float16_t)0.835706284f, (float16_t)0.549176662f, + (float16_t)0.834862875f, (float16_t)0.550457973f, + (float16_t)0.834017501f, (float16_t)0.551737988f, + (float16_t)0.833170165f, (float16_t)0.553016706f, + (float16_t)0.832320868f, (float16_t)0.554294121f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.830616400f, (float16_t)0.556845037f, + (float16_t)0.829761234f, (float16_t)0.558118531f, + (float16_t)0.828904115f, (float16_t)0.559390712f, + (float16_t)0.828045045f, (float16_t)0.560661576f, + (float16_t)0.827184027f, (float16_t)0.561931121f, + (float16_t)0.826321063f, (float16_t)0.563199344f, + (float16_t)0.825456154f, (float16_t)0.564466242f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.823720511f, (float16_t)0.566996049f, + (float16_t)0.822849781f, (float16_t)0.568258953f, + (float16_t)0.821977115f, (float16_t)0.569520519f, + (float16_t)0.821102515f, (float16_t)0.570780746f, + (float16_t)0.820225983f, (float16_t)0.572039629f, + (float16_t)0.819347520f, (float16_t)0.573297167f, + (float16_t)0.818467130f, (float16_t)0.574553355f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.816700573f, (float16_t)0.577061673f, + (float16_t)0.815814411f, (float16_t)0.578313796f, + (float16_t)0.814926329f, (float16_t)0.579564559f, + (float16_t)0.814036330f, (float16_t)0.580813958f, + (float16_t)0.813144415f, (float16_t)0.582061990f, + (float16_t)0.812250587f, (float16_t)0.583308653f, + (float16_t)0.811354847f, (float16_t)0.584553943f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.809557642f, (float16_t)0.587040394f, + (float16_t)0.808656182f, (float16_t)0.588281548f, + (float16_t)0.807752818f, (float16_t)0.589521319f, + (float16_t)0.806847554f, (float16_t)0.590759702f, + (float16_t)0.805940391f, (float16_t)0.591996695f, + (float16_t)0.805031331f, (float16_t)0.593232295f, + (float16_t)0.804120377f, (float16_t)0.594466499f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.802292796f, (float16_t)0.596930708f, + (float16_t)0.801376172f, (float16_t)0.598160707f, + (float16_t)0.800457662f, (float16_t)0.599389298f, + (float16_t)0.799537269f, (float16_t)0.600616479f, + (float16_t)0.798614995f, (float16_t)0.601842247f, + (float16_t)0.797690841f, (float16_t)0.603066599f, + (float16_t)0.796764810f, (float16_t)0.604289531f, + (float16_t)0.795836905f, (float16_t)0.605511041f, + (float16_t)0.794907126f, (float16_t)0.606731127f, + (float16_t)0.793975478f, (float16_t)0.607949785f, + (float16_t)0.793041960f, (float16_t)0.609167012f, + (float16_t)0.792106577f, (float16_t)0.610382806f, + (float16_t)0.791169330f, (float16_t)0.611597164f, + (float16_t)0.790230221f, (float16_t)0.612810082f, + (float16_t)0.789289253f, (float16_t)0.614021559f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.787401747f, (float16_t)0.616440175f, + (float16_t)0.786455214f, (float16_t)0.617647308f, + (float16_t)0.785506830f, (float16_t)0.618852988f, + (float16_t)0.784556597f, (float16_t)0.620057212f, + (float16_t)0.783604519f, (float16_t)0.621259977f, + (float16_t)0.782650596f, (float16_t)0.622461279f, + (float16_t)0.781694832f, (float16_t)0.623661118f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.779777788f, (float16_t)0.626056388f, + (float16_t)0.778816512f, (float16_t)0.627251815f, + (float16_t)0.777853404f, (float16_t)0.628445767f, + (float16_t)0.776888466f, (float16_t)0.629638239f, + (float16_t)0.775921699f, (float16_t)0.630829230f, + (float16_t)0.774953107f, (float16_t)0.632018736f, + (float16_t)0.773982691f, (float16_t)0.633206755f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.772036397f, (float16_t)0.635578320f, + (float16_t)0.771060524f, (float16_t)0.636761861f, + (float16_t)0.770082837f, (float16_t)0.637943904f, + (float16_t)0.769103338f, (float16_t)0.639124445f, + (float16_t)0.768122029f, (float16_t)0.640303482f, + (float16_t)0.767138912f, (float16_t)0.641481013f, + (float16_t)0.766153990f, (float16_t)0.642657034f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.764178741f, (float16_t)0.645004537f, + (float16_t)0.763188417f, (float16_t)0.646176013f, + (float16_t)0.762196298f, (float16_t)0.647345969f, + (float16_t)0.761202385f, (float16_t)0.648514401f, + (float16_t)0.760206682f, (float16_t)0.649681307f, + (float16_t)0.759209189f, (float16_t)0.650846685f, + (float16_t)0.758209910f, (float16_t)0.652010531f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.756206001f, (float16_t)0.654333618f, + (float16_t)0.755201377f, (float16_t)0.655492853f, + (float16_t)0.754194975f, (float16_t)0.656650546f, + (float16_t)0.753186799f, (float16_t)0.657806693f, + (float16_t)0.752176850f, (float16_t)0.658961293f, + (float16_t)0.751165132f, (float16_t)0.660114342f, + (float16_t)0.750151646f, (float16_t)0.661265838f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.748119380f, (float16_t)0.663564159f, + (float16_t)0.747100606f, (float16_t)0.664710978f, + (float16_t)0.746080074f, (float16_t)0.665856234f, + (float16_t)0.745057785f, (float16_t)0.666999922f, + (float16_t)0.744033744f, (float16_t)0.668142041f, + (float16_t)0.743007952f, (float16_t)0.669282588f, + (float16_t)0.741980412f, (float16_t)0.670421560f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.739920095f, (float16_t)0.672694769f, + (float16_t)0.738887324f, (float16_t)0.673829000f, + (float16_t)0.737852815f, (float16_t)0.674961646f, + (float16_t)0.736816569f, (float16_t)0.676092704f, + (float16_t)0.735778589f, (float16_t)0.677222170f, + (float16_t)0.734738878f, (float16_t)0.678350043f, + (float16_t)0.733697438f, (float16_t)0.679476320f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.731609381f, (float16_t)0.681724074f, + (float16_t)0.730562769f, (float16_t)0.682845546f, + (float16_t)0.729514438f, (float16_t)0.683965412f, + (float16_t)0.728464390f, (float16_t)0.685083668f, + (float16_t)0.727412629f, (float16_t)0.686200312f, + (float16_t)0.726359155f, (float16_t)0.687315341f, + (float16_t)0.725303972f, (float16_t)0.688428753f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.723188489f, (float16_t)0.690650714f, + (float16_t)0.722128194f, (float16_t)0.691759258f, + (float16_t)0.721066199f, (float16_t)0.692866175f, + (float16_t)0.720002508f, (float16_t)0.693971461f, + (float16_t)0.718937122f, (float16_t)0.695075114f, + (float16_t)0.717870045f, (float16_t)0.696177131f, + (float16_t)0.716801279f, (float16_t)0.697277511f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.714658688f, (float16_t)0.699473345f, + (float16_t)0.713584869f, (float16_t)0.700568794f, + (float16_t)0.712509371f, (float16_t)0.701662595f, + (float16_t)0.711432196f, (float16_t)0.702754744f, + (float16_t)0.710353347f, (float16_t)0.703845241f, + (float16_t)0.709272826f, (float16_t)0.704934080f, + (float16_t)0.708190637f, (float16_t)0.706021261f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.706021261f, (float16_t)0.708190637f, + (float16_t)0.704934080f, (float16_t)0.709272826f, + (float16_t)0.703845241f, (float16_t)0.710353347f, + (float16_t)0.702754744f, (float16_t)0.711432196f, + (float16_t)0.701662595f, (float16_t)0.712509371f, + (float16_t)0.700568794f, (float16_t)0.713584869f, + (float16_t)0.699473345f, (float16_t)0.714658688f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.697277511f, (float16_t)0.716801279f, + (float16_t)0.696177131f, (float16_t)0.717870045f, + (float16_t)0.695075114f, (float16_t)0.718937122f, + (float16_t)0.693971461f, (float16_t)0.720002508f, + (float16_t)0.692866175f, (float16_t)0.721066199f, + (float16_t)0.691759258f, (float16_t)0.722128194f, + (float16_t)0.690650714f, (float16_t)0.723188489f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.688428753f, (float16_t)0.725303972f, + (float16_t)0.687315341f, (float16_t)0.726359155f, + (float16_t)0.686200312f, (float16_t)0.727412629f, + (float16_t)0.685083668f, (float16_t)0.728464390f, + (float16_t)0.683965412f, (float16_t)0.729514438f, + (float16_t)0.682845546f, (float16_t)0.730562769f, + (float16_t)0.681724074f, (float16_t)0.731609381f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.679476320f, (float16_t)0.733697438f, + (float16_t)0.678350043f, (float16_t)0.734738878f, + (float16_t)0.677222170f, (float16_t)0.735778589f, + (float16_t)0.676092704f, (float16_t)0.736816569f, + (float16_t)0.674961646f, (float16_t)0.737852815f, + (float16_t)0.673829000f, (float16_t)0.738887324f, + (float16_t)0.672694769f, (float16_t)0.739920095f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.670421560f, (float16_t)0.741980412f, + (float16_t)0.669282588f, (float16_t)0.743007952f, + (float16_t)0.668142041f, (float16_t)0.744033744f, + (float16_t)0.666999922f, (float16_t)0.745057785f, + (float16_t)0.665856234f, (float16_t)0.746080074f, + (float16_t)0.664710978f, (float16_t)0.747100606f, + (float16_t)0.663564159f, (float16_t)0.748119380f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.661265838f, (float16_t)0.750151646f, + (float16_t)0.660114342f, (float16_t)0.751165132f, + (float16_t)0.658961293f, (float16_t)0.752176850f, + (float16_t)0.657806693f, (float16_t)0.753186799f, + (float16_t)0.656650546f, (float16_t)0.754194975f, + (float16_t)0.655492853f, (float16_t)0.755201377f, + (float16_t)0.654333618f, (float16_t)0.756206001f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.652010531f, (float16_t)0.758209910f, + (float16_t)0.650846685f, (float16_t)0.759209189f, + (float16_t)0.649681307f, (float16_t)0.760206682f, + (float16_t)0.648514401f, (float16_t)0.761202385f, + (float16_t)0.647345969f, (float16_t)0.762196298f, + (float16_t)0.646176013f, (float16_t)0.763188417f, + (float16_t)0.645004537f, (float16_t)0.764178741f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.642657034f, (float16_t)0.766153990f, + (float16_t)0.641481013f, (float16_t)0.767138912f, + (float16_t)0.640303482f, (float16_t)0.768122029f, + (float16_t)0.639124445f, (float16_t)0.769103338f, + (float16_t)0.637943904f, (float16_t)0.770082837f, + (float16_t)0.636761861f, (float16_t)0.771060524f, + (float16_t)0.635578320f, (float16_t)0.772036397f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.633206755f, (float16_t)0.773982691f, + (float16_t)0.632018736f, (float16_t)0.774953107f, + (float16_t)0.630829230f, (float16_t)0.775921699f, + (float16_t)0.629638239f, (float16_t)0.776888466f, + (float16_t)0.628445767f, (float16_t)0.777853404f, + (float16_t)0.627251815f, (float16_t)0.778816512f, + (float16_t)0.626056388f, (float16_t)0.779777788f, + (float16_t)0.624859488f, (float16_t)0.780737229f, + (float16_t)0.623661118f, (float16_t)0.781694832f, + (float16_t)0.622461279f, (float16_t)0.782650596f, + (float16_t)0.621259977f, (float16_t)0.783604519f, + (float16_t)0.620057212f, (float16_t)0.784556597f, + (float16_t)0.618852988f, (float16_t)0.785506830f, + (float16_t)0.617647308f, (float16_t)0.786455214f, + (float16_t)0.616440175f, (float16_t)0.787401747f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.614021559f, (float16_t)0.789289253f, + (float16_t)0.612810082f, (float16_t)0.790230221f, + (float16_t)0.611597164f, (float16_t)0.791169330f, + (float16_t)0.610382806f, (float16_t)0.792106577f, + (float16_t)0.609167012f, (float16_t)0.793041960f, + (float16_t)0.607949785f, (float16_t)0.793975478f, + (float16_t)0.606731127f, (float16_t)0.794907126f, + (float16_t)0.605511041f, (float16_t)0.795836905f, + (float16_t)0.604289531f, (float16_t)0.796764810f, + (float16_t)0.603066599f, (float16_t)0.797690841f, + (float16_t)0.601842247f, (float16_t)0.798614995f, + (float16_t)0.600616479f, (float16_t)0.799537269f, + (float16_t)0.599389298f, (float16_t)0.800457662f, + (float16_t)0.598160707f, (float16_t)0.801376172f, + (float16_t)0.596930708f, (float16_t)0.802292796f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.594466499f, (float16_t)0.804120377f, + (float16_t)0.593232295f, (float16_t)0.805031331f, + (float16_t)0.591996695f, (float16_t)0.805940391f, + (float16_t)0.590759702f, (float16_t)0.806847554f, + (float16_t)0.589521319f, (float16_t)0.807752818f, + (float16_t)0.588281548f, (float16_t)0.808656182f, + (float16_t)0.587040394f, (float16_t)0.809557642f, + (float16_t)0.585797857f, (float16_t)0.810457198f, + (float16_t)0.584553943f, (float16_t)0.811354847f, + (float16_t)0.583308653f, (float16_t)0.812250587f, + (float16_t)0.582061990f, (float16_t)0.813144415f, + (float16_t)0.580813958f, (float16_t)0.814036330f, + (float16_t)0.579564559f, (float16_t)0.814926329f, + (float16_t)0.578313796f, (float16_t)0.815814411f, + (float16_t)0.577061673f, (float16_t)0.816700573f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.574553355f, (float16_t)0.818467130f, + (float16_t)0.573297167f, (float16_t)0.819347520f, + (float16_t)0.572039629f, (float16_t)0.820225983f, + (float16_t)0.570780746f, (float16_t)0.821102515f, + (float16_t)0.569520519f, (float16_t)0.821977115f, + (float16_t)0.568258953f, (float16_t)0.822849781f, + (float16_t)0.566996049f, (float16_t)0.823720511f, + (float16_t)0.565731811f, (float16_t)0.824589303f, + (float16_t)0.564466242f, (float16_t)0.825456154f, + (float16_t)0.563199344f, (float16_t)0.826321063f, + (float16_t)0.561931121f, (float16_t)0.827184027f, + (float16_t)0.560661576f, (float16_t)0.828045045f, + (float16_t)0.559390712f, (float16_t)0.828904115f, + (float16_t)0.558118531f, (float16_t)0.829761234f, + (float16_t)0.556845037f, (float16_t)0.830616400f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.554294121f, (float16_t)0.832320868f, + (float16_t)0.553016706f, (float16_t)0.833170165f, + (float16_t)0.551737988f, (float16_t)0.834017501f, + (float16_t)0.550457973f, (float16_t)0.834862875f, + (float16_t)0.549176662f, (float16_t)0.835706284f, + (float16_t)0.547894059f, (float16_t)0.836547727f, + (float16_t)0.546610167f, (float16_t)0.837387202f, + (float16_t)0.545324988f, (float16_t)0.838224706f, + (float16_t)0.544038527f, (float16_t)0.839060237f, + (float16_t)0.542750785f, (float16_t)0.839893794f, + (float16_t)0.541461766f, (float16_t)0.840725375f, + (float16_t)0.540171473f, (float16_t)0.841554977f, + (float16_t)0.538879909f, (float16_t)0.842382600f, + (float16_t)0.537587076f, (float16_t)0.843208240f, + (float16_t)0.536292979f, (float16_t)0.844031895f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.533701002f, (float16_t)0.845673247f, + (float16_t)0.532403128f, (float16_t)0.846490939f, + (float16_t)0.531104001f, (float16_t)0.847306639f, + (float16_t)0.529803625f, (float16_t)0.848120345f, + (float16_t)0.528502002f, (float16_t)0.848932055f, + (float16_t)0.527199135f, (float16_t)0.849741768f, + (float16_t)0.525895027f, (float16_t)0.850549481f, + (float16_t)0.524589683f, (float16_t)0.851355193f, + (float16_t)0.523283103f, (float16_t)0.852158902f, + (float16_t)0.521975293f, (float16_t)0.852960605f, + (float16_t)0.520666254f, (float16_t)0.853760301f, + (float16_t)0.519355990f, (float16_t)0.854557988f, + (float16_t)0.518044504f, (float16_t)0.855353665f, + (float16_t)0.516731799f, (float16_t)0.856147328f, + (float16_t)0.515417878f, (float16_t)0.856938977f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.512786401f, (float16_t)0.858516224f, + (float16_t)0.511468850f, (float16_t)0.859301818f, + (float16_t)0.510150097f, (float16_t)0.860085390f, + (float16_t)0.508830143f, (float16_t)0.860866939f, + (float16_t)0.507508991f, (float16_t)0.861646461f, + (float16_t)0.506186645f, (float16_t)0.862423956f, + (float16_t)0.504863109f, (float16_t)0.863199422f, + (float16_t)0.503538384f, (float16_t)0.863972856f, + (float16_t)0.502212474f, (float16_t)0.864744258f, + (float16_t)0.500885383f, (float16_t)0.865513624f, + (float16_t)0.499557113f, (float16_t)0.866280954f, + (float16_t)0.498227667f, (float16_t)0.867046246f, + (float16_t)0.496897049f, (float16_t)0.867809497f, + (float16_t)0.495565262f, (float16_t)0.868570706f, + (float16_t)0.494232309f, (float16_t)0.869329871f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.491562916f, (float16_t)0.870842063f, + (float16_t)0.490226483f, (float16_t)0.871595087f, + (float16_t)0.488888897f, (float16_t)0.872346059f, + (float16_t)0.487550160f, (float16_t)0.873094978f, + (float16_t)0.486210276f, (float16_t)0.873841843f, + (float16_t)0.484869248f, (float16_t)0.874586652f, + (float16_t)0.483527079f, (float16_t)0.875329403f, + (float16_t)0.482183772f, (float16_t)0.876070094f, + (float16_t)0.480839331f, (float16_t)0.876808724f, + (float16_t)0.479493758f, (float16_t)0.877545290f, + (float16_t)0.478147056f, (float16_t)0.878279792f, + (float16_t)0.476799230f, (float16_t)0.879012226f, + (float16_t)0.475450282f, (float16_t)0.879742593f, + (float16_t)0.474100215f, (float16_t)0.880470889f, + (float16_t)0.472749032f, (float16_t)0.881197113f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.470043332f, (float16_t)0.882643340f, + (float16_t)0.468688822f, (float16_t)0.883363339f, + (float16_t)0.467333209f, (float16_t)0.884081259f, + (float16_t)0.465976496f, (float16_t)0.884797098f, + (float16_t)0.464618686f, (float16_t)0.885510856f, + (float16_t)0.463259784f, (float16_t)0.886222530f, + (float16_t)0.461899791f, (float16_t)0.886932119f, + (float16_t)0.460538711f, (float16_t)0.887639620f, + (float16_t)0.459176548f, (float16_t)0.888345033f, + (float16_t)0.457813304f, (float16_t)0.889048356f, + (float16_t)0.456448982f, (float16_t)0.889749586f, + (float16_t)0.455083587f, (float16_t)0.890448723f, + (float16_t)0.453717121f, (float16_t)0.891145765f, + (float16_t)0.452349587f, (float16_t)0.891840709f, + (float16_t)0.450980989f, (float16_t)0.892533555f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.448240612f, (float16_t)0.893912945f, + (float16_t)0.446868840f, (float16_t)0.894599486f, + (float16_t)0.445496017f, (float16_t)0.895283921f, + (float16_t)0.444122145f, (float16_t)0.895966250f, + (float16_t)0.442747228f, (float16_t)0.896646470f, + (float16_t)0.441371269f, (float16_t)0.897324581f, + (float16_t)0.439994271f, (float16_t)0.898000580f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.437237174f, (float16_t)0.899346237f, + (float16_t)0.435857080f, (float16_t)0.900015892f, + (float16_t)0.434475961f, (float16_t)0.900683429f, + (float16_t)0.433093819f, (float16_t)0.901348847f, + (float16_t)0.431710658f, (float16_t)0.902012144f, + (float16_t)0.430326481f, (float16_t)0.902673318f, + (float16_t)0.428941292f, (float16_t)0.903332368f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.426167889f, (float16_t)0.904644091f, + (float16_t)0.424779681f, (float16_t)0.905296759f, + (float16_t)0.423390474f, (float16_t)0.905947298f, + (float16_t)0.422000271f, (float16_t)0.906595705f, + (float16_t)0.420609074f, (float16_t)0.907241978f, + (float16_t)0.419216888f, (float16_t)0.907886116f, + (float16_t)0.417823716f, (float16_t)0.908528119f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.415034424f, (float16_t)0.909805708f, + (float16_t)0.413638312f, (float16_t)0.910441292f, + (float16_t)0.412241227f, (float16_t)0.911074734f, + (float16_t)0.410843171f, (float16_t)0.911706032f, + (float16_t)0.409444149f, (float16_t)0.912335185f, + (float16_t)0.408044163f, (float16_t)0.912962190f, + (float16_t)0.406643217f, (float16_t)0.913587048f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.403838458f, (float16_t)0.914830312f, + (float16_t)0.402434651f, (float16_t)0.915448716f, + (float16_t)0.401029897f, (float16_t)0.916064966f, + (float16_t)0.399624200f, (float16_t)0.916679060f, + (float16_t)0.398217562f, (float16_t)0.917290997f, + (float16_t)0.396809987f, (float16_t)0.917900776f, + (float16_t)0.395401479f, (float16_t)0.918508394f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.392581674f, (float16_t)0.919717146f, + (float16_t)0.391170384f, (float16_t)0.920318277f, + (float16_t)0.389758174f, (float16_t)0.920917242f, + (float16_t)0.388345047f, (float16_t)0.921514039f, + (float16_t)0.386931006f, (float16_t)0.922108669f, + (float16_t)0.385516054f, (float16_t)0.922701128f, + (float16_t)0.384100195f, (float16_t)0.923291417f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.381265769f, (float16_t)0.924465474f, + (float16_t)0.379847209f, (float16_t)0.925049241f, + (float16_t)0.378427755f, (float16_t)0.925630831f, + (float16_t)0.377007410f, (float16_t)0.926210242f, + (float16_t)0.375586178f, (float16_t)0.926787474f, + (float16_t)0.374164063f, (float16_t)0.927362526f, + (float16_t)0.372741067f, (float16_t)0.927935395f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.369892447f, (float16_t)0.929074581f, + (float16_t)0.368466830f, (float16_t)0.929640896f, + (float16_t)0.367040346f, (float16_t)0.930205023f, + (float16_t)0.365612998f, (float16_t)0.930766961f, + (float16_t)0.364184790f, (float16_t)0.931326709f, + (float16_t)0.362755724f, (float16_t)0.931884266f, + (float16_t)0.361325806f, (float16_t)0.932439629f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.358463421f, (float16_t)0.933543773f, + (float16_t)0.357030961f, (float16_t)0.934092550f, + (float16_t)0.355597662f, (float16_t)0.934639130f, + (float16_t)0.354163525f, (float16_t)0.935183510f, + (float16_t)0.352728556f, (float16_t)0.935725689f, + (float16_t)0.351292756f, (float16_t)0.936265667f, + (float16_t)0.349856130f, (float16_t)0.936803442f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.346980411f, (float16_t)0.937872376f, + (float16_t)0.345541325f, (float16_t)0.938403534f, + (float16_t)0.344101426f, (float16_t)0.938932484f, + (float16_t)0.342660717f, (float16_t)0.939459224f, + (float16_t)0.341219202f, (float16_t)0.939983753f, + (float16_t)0.339776884f, (float16_t)0.940506071f, + (float16_t)0.338333767f, (float16_t)0.941026175f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.335445147f, (float16_t)0.942059740f, + (float16_t)0.333999651f, (float16_t)0.942573198f, + (float16_t)0.332553370f, (float16_t)0.943084437f, + (float16_t)0.331106306f, (float16_t)0.943593458f, + (float16_t)0.329658463f, (float16_t)0.944100258f, + (float16_t)0.328209844f, (float16_t)0.944604837f, + (float16_t)0.326760452f, (float16_t)0.945107193f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.323859367f, (float16_t)0.946105232f, + (float16_t)0.322407679f, (float16_t)0.946600913f, + (float16_t)0.320955232f, (float16_t)0.947094366f, + (float16_t)0.319502031f, (float16_t)0.947585591f, + (float16_t)0.318048077f, (float16_t)0.948074586f, + (float16_t)0.316593376f, (float16_t)0.948561350f, + (float16_t)0.315137929f, (float16_t)0.949045882f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.312224814f, (float16_t)0.950008245f, + (float16_t)0.310767153f, (float16_t)0.950486074f, + (float16_t)0.309308760f, (float16_t)0.950961666f, + (float16_t)0.307849640f, (float16_t)0.951435021f, + (float16_t)0.306389795f, (float16_t)0.951906137f, + (float16_t)0.304929230f, (float16_t)0.952375013f, + (float16_t)0.303467947f, (float16_t)0.952841648f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.300543241f, (float16_t)0.953768190f, + (float16_t)0.299079826f, (float16_t)0.954228095f, + (float16_t)0.297615707f, (float16_t)0.954685755f, + (float16_t)0.296150888f, (float16_t)0.955141168f, + (float16_t)0.294685372f, (float16_t)0.955594334f, + (float16_t)0.293219163f, (float16_t)0.956045251f, + (float16_t)0.291752263f, (float16_t)0.956493919f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.288816408f, (float16_t)0.957384501f, + (float16_t)0.287347460f, (float16_t)0.957826413f, + (float16_t)0.285877835f, (float16_t)0.958266071f, + (float16_t)0.284407537f, (float16_t)0.958703475f, + (float16_t)0.282936570f, (float16_t)0.959138622f, + (float16_t)0.281464938f, (float16_t)0.959571513f, + (float16_t)0.279992643f, (float16_t)0.960002146f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.277046080f, (float16_t)0.960856633f, + (float16_t)0.275571819f, (float16_t)0.961280486f, + (float16_t)0.274096910f, (float16_t)0.961702077f, + (float16_t)0.272621355f, (float16_t)0.962121404f, + (float16_t)0.271145160f, (float16_t)0.962538468f, + (float16_t)0.269668326f, (float16_t)0.962953267f, + (float16_t)0.268190857f, (float16_t)0.963365800f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.265234030f, (float16_t)0.964184064f, + (float16_t)0.263754679f, (float16_t)0.964589793f, + (float16_t)0.262274707f, (float16_t)0.964993253f, + (float16_t)0.260794118f, (float16_t)0.965394442f, + (float16_t)0.259312915f, (float16_t)0.965793359f, + (float16_t)0.257831102f, (float16_t)0.966190003f, + (float16_t)0.256348682f, (float16_t)0.966584374f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.253382037f, (float16_t)0.967366292f, + (float16_t)0.251897818f, (float16_t)0.967753837f, + (float16_t)0.250413007f, (float16_t)0.968139105f, + (float16_t)0.248927606f, (float16_t)0.968522094f, + (float16_t)0.247441619f, (float16_t)0.968902805f, + (float16_t)0.245955050f, (float16_t)0.969281235f, + (float16_t)0.244467903f, (float16_t)0.969657385f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.241491885f, (float16_t)0.970402839f, + (float16_t)0.240003022f, (float16_t)0.970772141f, + (float16_t)0.238513595f, (float16_t)0.971139158f, + (float16_t)0.237023606f, (float16_t)0.971503891f, + (float16_t)0.235533059f, (float16_t)0.971866337f, + (float16_t)0.234041959f, (float16_t)0.972226497f, + (float16_t)0.232550307f, (float16_t)0.972584369f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.229565366f, (float16_t)0.973293246f, + (float16_t)0.228072083f, (float16_t)0.973644250f, + (float16_t)0.226578264f, (float16_t)0.973992962f, + (float16_t)0.225083911f, (float16_t)0.974339383f, + (float16_t)0.223589029f, (float16_t)0.974683511f, + (float16_t)0.222093621f, (float16_t)0.975025345f, + (float16_t)0.220597690f, (float16_t)0.975364885f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.217604275f, (float16_t)0.976037079f, + (float16_t)0.216106797f, (float16_t)0.976369731f, + (float16_t)0.214608811f, (float16_t)0.976700086f, + (float16_t)0.213110320f, (float16_t)0.977028143f, + (float16_t)0.211611327f, (float16_t)0.977353900f, + (float16_t)0.210111837f, (float16_t)0.977677358f, + (float16_t)0.208611852f, (float16_t)0.977998515f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.205610413f, (float16_t)0.978633924f, + (float16_t)0.204108966f, (float16_t)0.978948175f, + (float16_t)0.202607039f, (float16_t)0.979260123f, + (float16_t)0.201104635f, (float16_t)0.979569766f, + (float16_t)0.199601758f, (float16_t)0.979877104f, + (float16_t)0.198098411f, (float16_t)0.980182136f, + (float16_t)0.196594598f, (float16_t)0.980484862f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.193585587f, (float16_t)0.981083391f, + (float16_t)0.192080397f, (float16_t)0.981379193f, + (float16_t)0.190574755f, (float16_t)0.981672686f, + (float16_t)0.189068664f, (float16_t)0.981963869f, + (float16_t)0.187562129f, (float16_t)0.982252741f, + (float16_t)0.186055152f, (float16_t)0.982539302f, + (float16_t)0.184547737f, (float16_t)0.982823551f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.181531608f, (float16_t)0.983385110f, + (float16_t)0.180022901f, (float16_t)0.983662419f, + (float16_t)0.178513771f, (float16_t)0.983937413f, + (float16_t)0.177004220f, (float16_t)0.984210092f, + (float16_t)0.175494253f, (float16_t)0.984480455f, + (float16_t)0.173983873f, (float16_t)0.984748502f, + (float16_t)0.172473084f, (float16_t)0.985014231f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.169450291f, (float16_t)0.985538735f, + (float16_t)0.167938295f, (float16_t)0.985797509f, + (float16_t)0.166425904f, (float16_t)0.986053963f, + (float16_t)0.164913120f, (float16_t)0.986308097f, + (float16_t)0.163399949f, (float16_t)0.986559910f, + (float16_t)0.161886394f, (float16_t)0.986809402f, + (float16_t)0.160372457f, (float16_t)0.987056571f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.157343456f, (float16_t)0.987543942f, + (float16_t)0.155828398f, (float16_t)0.987784142f, + (float16_t)0.154312973f, (float16_t)0.988022017f, + (float16_t)0.152797185f, (float16_t)0.988257568f, + (float16_t)0.151281038f, (float16_t)0.988490793f, + (float16_t)0.149764535f, (float16_t)0.988721692f, + (float16_t)0.148247679f, (float16_t)0.988950265f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.145212925f, (float16_t)0.989400428f, + (float16_t)0.143695033f, (float16_t)0.989622017f, + (float16_t)0.142176804f, (float16_t)0.989841278f, + (float16_t)0.140658239f, (float16_t)0.990058210f, + (float16_t)0.139139344f, (float16_t)0.990272812f, + (float16_t)0.137620122f, (float16_t)0.990485084f, + (float16_t)0.136100575f, (float16_t)0.990695025f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.133060525f, (float16_t)0.991107914f, + (float16_t)0.131540029f, (float16_t)0.991310860f, + (float16_t)0.130019223f, (float16_t)0.991511473f, + (float16_t)0.128498111f, (float16_t)0.991709754f, + (float16_t)0.126976696f, (float16_t)0.991905700f, + (float16_t)0.125454983f, (float16_t)0.992099313f, + (float16_t)0.123932975f, (float16_t)0.992290591f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.120888087f, (float16_t)0.992666142f, + (float16_t)0.119365215f, (float16_t)0.992850414f, + (float16_t)0.117842062f, (float16_t)0.993032350f, + (float16_t)0.116318631f, (float16_t)0.993211949f, + (float16_t)0.114794927f, (float16_t)0.993389211f, + (float16_t)0.113270952f, (float16_t)0.993564136f, + (float16_t)0.111746711f, (float16_t)0.993736722f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.108697444f, (float16_t)0.994074879f, + (float16_t)0.107172425f, (float16_t)0.994240449f, + (float16_t)0.105647154f, (float16_t)0.994403680f, + (float16_t)0.104121634f, (float16_t)0.994564571f, + (float16_t)0.102595869f, (float16_t)0.994723121f, + (float16_t)0.101069863f, (float16_t)0.994879331f, + (float16_t)0.099543619f, (float16_t)0.995033199f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.096490431f, (float16_t)0.995333912f, + (float16_t)0.094963495f, (float16_t)0.995480755f, + (float16_t)0.093436336f, (float16_t)0.995625256f, + (float16_t)0.091908956f, (float16_t)0.995767414f, + (float16_t)0.090381361f, (float16_t)0.995907229f, + (float16_t)0.088853553f, (float16_t)0.996044701f, + (float16_t)0.087325535f, (float16_t)0.996179829f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.084268888f, (float16_t)0.996443051f, + (float16_t)0.082740265f, (float16_t)0.996571146f, + (float16_t)0.081211447f, (float16_t)0.996696895f, + (float16_t)0.079682438f, (float16_t)0.996820299f, + (float16_t)0.078153242f, (float16_t)0.996941358f, + (float16_t)0.076623861f, (float16_t)0.997060070f, + (float16_t)0.075094301f, (float16_t)0.997176437f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.072034653f, (float16_t)0.997402130f, + (float16_t)0.070504573f, (float16_t)0.997511456f, + (float16_t)0.068974328f, (float16_t)0.997618435f, + (float16_t)0.067443920f, (float16_t)0.997723067f, + (float16_t)0.065913353f, (float16_t)0.997825350f, + (float16_t)0.064382631f, (float16_t)0.997925286f, + (float16_t)0.062851758f, (float16_t)0.998022874f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.059789571f, (float16_t)0.998211003f, + (float16_t)0.058258265f, (float16_t)0.998301545f, + (float16_t)0.056726821f, (float16_t)0.998389737f, + (float16_t)0.055195244f, (float16_t)0.998475581f, + (float16_t)0.053663538f, (float16_t)0.998559074f, + (float16_t)0.052131705f, (float16_t)0.998640218f, + (float16_t)0.050599749f, (float16_t)0.998719012f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.047535484f, (float16_t)0.998869550f, + (float16_t)0.046003182f, (float16_t)0.998941293f, + (float16_t)0.044470772f, (float16_t)0.999010686f, + (float16_t)0.042938257f, (float16_t)0.999077728f, + (float16_t)0.041405641f, (float16_t)0.999142419f, + (float16_t)0.039872928f, (float16_t)0.999204759f, + (float16_t)0.038340120f, (float16_t)0.999264747f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.035274239f, (float16_t)0.999377670f, + (float16_t)0.033741172f, (float16_t)0.999430605f, + (float16_t)0.032208025f, (float16_t)0.999481187f, + (float16_t)0.030674803f, (float16_t)0.999529418f, + (float16_t)0.029141509f, (float16_t)0.999575296f, + (float16_t)0.027608146f, (float16_t)0.999618822f, + (float16_t)0.026074718f, (float16_t)0.999659997f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.023007681f, (float16_t)0.999735288f, + (float16_t)0.021474080f, (float16_t)0.999769405f, + (float16_t)0.019940429f, (float16_t)0.999801170f, + (float16_t)0.018406730f, (float16_t)0.999830582f, + (float16_t)0.016872988f, (float16_t)0.999857641f, + (float16_t)0.015339206f, (float16_t)0.999882347f, + (float16_t)0.013805389f, (float16_t)0.999904701f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.010737659f, (float16_t)0.999942350f, + (float16_t)0.009203755f, (float16_t)0.999957645f, + (float16_t)0.007669829f, (float16_t)0.999970586f, + (float16_t)0.006135885f, (float16_t)0.999981175f, + (float16_t)0.004601926f, (float16_t)0.999989411f, + (float16_t)0.003067957f, (float16_t)0.999995294f, + (float16_t)0.001533980f, (float16_t)0.999998823f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.001533980f, (float16_t)0.999998823f, + (float16_t)-0.003067957f, (float16_t)0.999995294f, + (float16_t)-0.004601926f, (float16_t)0.999989411f, + (float16_t)-0.006135885f, (float16_t)0.999981175f, + (float16_t)-0.007669829f, (float16_t)0.999970586f, + (float16_t)-0.009203755f, (float16_t)0.999957645f, + (float16_t)-0.010737659f, (float16_t)0.999942350f, + (float16_t)-0.012271538f, (float16_t)0.999924702f, + (float16_t)-0.013805389f, (float16_t)0.999904701f, + (float16_t)-0.015339206f, (float16_t)0.999882347f, + (float16_t)-0.016872988f, (float16_t)0.999857641f, + (float16_t)-0.018406730f, (float16_t)0.999830582f, + (float16_t)-0.019940429f, (float16_t)0.999801170f, + (float16_t)-0.021474080f, (float16_t)0.999769405f, + (float16_t)-0.023007681f, (float16_t)0.999735288f, + (float16_t)-0.024541229f, (float16_t)0.999698819f, + (float16_t)-0.026074718f, (float16_t)0.999659997f, + (float16_t)-0.027608146f, (float16_t)0.999618822f, + (float16_t)-0.029141509f, (float16_t)0.999575296f, + (float16_t)-0.030674803f, (float16_t)0.999529418f, + (float16_t)-0.032208025f, (float16_t)0.999481187f, + (float16_t)-0.033741172f, (float16_t)0.999430605f, + (float16_t)-0.035274239f, (float16_t)0.999377670f, + (float16_t)-0.036807223f, (float16_t)0.999322385f, + (float16_t)-0.038340120f, (float16_t)0.999264747f, + (float16_t)-0.039872928f, (float16_t)0.999204759f, + (float16_t)-0.041405641f, (float16_t)0.999142419f, + (float16_t)-0.042938257f, (float16_t)0.999077728f, + (float16_t)-0.044470772f, (float16_t)0.999010686f, + (float16_t)-0.046003182f, (float16_t)0.998941293f, + (float16_t)-0.047535484f, (float16_t)0.998869550f, + (float16_t)-0.049067674f, (float16_t)0.998795456f, + (float16_t)-0.050599749f, (float16_t)0.998719012f, + (float16_t)-0.052131705f, (float16_t)0.998640218f, + (float16_t)-0.053663538f, (float16_t)0.998559074f, + (float16_t)-0.055195244f, (float16_t)0.998475581f, + (float16_t)-0.056726821f, (float16_t)0.998389737f, + (float16_t)-0.058258265f, (float16_t)0.998301545f, + (float16_t)-0.059789571f, (float16_t)0.998211003f, + (float16_t)-0.061320736f, (float16_t)0.998118113f, + (float16_t)-0.062851758f, (float16_t)0.998022874f, + (float16_t)-0.064382631f, (float16_t)0.997925286f, + (float16_t)-0.065913353f, (float16_t)0.997825350f, + (float16_t)-0.067443920f, (float16_t)0.997723067f, + (float16_t)-0.068974328f, (float16_t)0.997618435f, + (float16_t)-0.070504573f, (float16_t)0.997511456f, + (float16_t)-0.072034653f, (float16_t)0.997402130f, + (float16_t)-0.073564564f, (float16_t)0.997290457f, + (float16_t)-0.075094301f, (float16_t)0.997176437f, + (float16_t)-0.076623861f, (float16_t)0.997060070f, + (float16_t)-0.078153242f, (float16_t)0.996941358f, + (float16_t)-0.079682438f, (float16_t)0.996820299f, + (float16_t)-0.081211447f, (float16_t)0.996696895f, + (float16_t)-0.082740265f, (float16_t)0.996571146f, + (float16_t)-0.084268888f, (float16_t)0.996443051f, + (float16_t)-0.085797312f, (float16_t)0.996312612f, + (float16_t)-0.087325535f, (float16_t)0.996179829f, + (float16_t)-0.088853553f, (float16_t)0.996044701f, + (float16_t)-0.090381361f, (float16_t)0.995907229f, + (float16_t)-0.091908956f, (float16_t)0.995767414f, + (float16_t)-0.093436336f, (float16_t)0.995625256f, + (float16_t)-0.094963495f, (float16_t)0.995480755f, + (float16_t)-0.096490431f, (float16_t)0.995333912f, + (float16_t)-0.098017140f, (float16_t)0.995184727f, + (float16_t)-0.099543619f, (float16_t)0.995033199f, + (float16_t)-0.101069863f, (float16_t)0.994879331f, + (float16_t)-0.102595869f, (float16_t)0.994723121f, + (float16_t)-0.104121634f, (float16_t)0.994564571f, + (float16_t)-0.105647154f, (float16_t)0.994403680f, + (float16_t)-0.107172425f, (float16_t)0.994240449f, + (float16_t)-0.108697444f, (float16_t)0.994074879f, + (float16_t)-0.110222207f, (float16_t)0.993906970f, + (float16_t)-0.111746711f, (float16_t)0.993736722f, + (float16_t)-0.113270952f, (float16_t)0.993564136f, + (float16_t)-0.114794927f, (float16_t)0.993389211f, + (float16_t)-0.116318631f, (float16_t)0.993211949f, + (float16_t)-0.117842062f, (float16_t)0.993032350f, + (float16_t)-0.119365215f, (float16_t)0.992850414f, + (float16_t)-0.120888087f, (float16_t)0.992666142f, + (float16_t)-0.122410675f, (float16_t)0.992479535f, + (float16_t)-0.123932975f, (float16_t)0.992290591f, + (float16_t)-0.125454983f, (float16_t)0.992099313f, + (float16_t)-0.126976696f, (float16_t)0.991905700f, + (float16_t)-0.128498111f, (float16_t)0.991709754f, + (float16_t)-0.130019223f, (float16_t)0.991511473f, + (float16_t)-0.131540029f, (float16_t)0.991310860f, + (float16_t)-0.133060525f, (float16_t)0.991107914f, + (float16_t)-0.134580709f, (float16_t)0.990902635f, + (float16_t)-0.136100575f, (float16_t)0.990695025f, + (float16_t)-0.137620122f, (float16_t)0.990485084f, + (float16_t)-0.139139344f, (float16_t)0.990272812f, + (float16_t)-0.140658239f, (float16_t)0.990058210f, + (float16_t)-0.142176804f, (float16_t)0.989841278f, + (float16_t)-0.143695033f, (float16_t)0.989622017f, + (float16_t)-0.145212925f, (float16_t)0.989400428f, + (float16_t)-0.146730474f, (float16_t)0.989176510f, + (float16_t)-0.148247679f, (float16_t)0.988950265f, + (float16_t)-0.149764535f, (float16_t)0.988721692f, + (float16_t)-0.151281038f, (float16_t)0.988490793f, + (float16_t)-0.152797185f, (float16_t)0.988257568f, + (float16_t)-0.154312973f, (float16_t)0.988022017f, + (float16_t)-0.155828398f, (float16_t)0.987784142f, + (float16_t)-0.157343456f, (float16_t)0.987543942f, + (float16_t)-0.158858143f, (float16_t)0.987301418f, + (float16_t)-0.160372457f, (float16_t)0.987056571f, + (float16_t)-0.161886394f, (float16_t)0.986809402f, + (float16_t)-0.163399949f, (float16_t)0.986559910f, + (float16_t)-0.164913120f, (float16_t)0.986308097f, + (float16_t)-0.166425904f, (float16_t)0.986053963f, + (float16_t)-0.167938295f, (float16_t)0.985797509f, + (float16_t)-0.169450291f, (float16_t)0.985538735f, + (float16_t)-0.170961889f, (float16_t)0.985277642f, + (float16_t)-0.172473084f, (float16_t)0.985014231f, + (float16_t)-0.173983873f, (float16_t)0.984748502f, + (float16_t)-0.175494253f, (float16_t)0.984480455f, + (float16_t)-0.177004220f, (float16_t)0.984210092f, + (float16_t)-0.178513771f, (float16_t)0.983937413f, + (float16_t)-0.180022901f, (float16_t)0.983662419f, + (float16_t)-0.181531608f, (float16_t)0.983385110f, + (float16_t)-0.183039888f, (float16_t)0.983105487f, + (float16_t)-0.184547737f, (float16_t)0.982823551f, + (float16_t)-0.186055152f, (float16_t)0.982539302f, + (float16_t)-0.187562129f, (float16_t)0.982252741f, + (float16_t)-0.189068664f, (float16_t)0.981963869f, + (float16_t)-0.190574755f, (float16_t)0.981672686f, + (float16_t)-0.192080397f, (float16_t)0.981379193f, + (float16_t)-0.193585587f, (float16_t)0.981083391f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.196594598f, (float16_t)0.980484862f, + (float16_t)-0.198098411f, (float16_t)0.980182136f, + (float16_t)-0.199601758f, (float16_t)0.979877104f, + (float16_t)-0.201104635f, (float16_t)0.979569766f, + (float16_t)-0.202607039f, (float16_t)0.979260123f, + (float16_t)-0.204108966f, (float16_t)0.978948175f, + (float16_t)-0.205610413f, (float16_t)0.978633924f, + (float16_t)-0.207111376f, (float16_t)0.978317371f, + (float16_t)-0.208611852f, (float16_t)0.977998515f, + (float16_t)-0.210111837f, (float16_t)0.977677358f, + (float16_t)-0.211611327f, (float16_t)0.977353900f, + (float16_t)-0.213110320f, (float16_t)0.977028143f, + (float16_t)-0.214608811f, (float16_t)0.976700086f, + (float16_t)-0.216106797f, (float16_t)0.976369731f, + (float16_t)-0.217604275f, (float16_t)0.976037079f, + (float16_t)-0.219101240f, (float16_t)0.975702130f, + (float16_t)-0.220597690f, (float16_t)0.975364885f, + (float16_t)-0.222093621f, (float16_t)0.975025345f, + (float16_t)-0.223589029f, (float16_t)0.974683511f, + (float16_t)-0.225083911f, (float16_t)0.974339383f, + (float16_t)-0.226578264f, (float16_t)0.973992962f, + (float16_t)-0.228072083f, (float16_t)0.973644250f, + (float16_t)-0.229565366f, (float16_t)0.973293246f, + (float16_t)-0.231058108f, (float16_t)0.972939952f, + (float16_t)-0.232550307f, (float16_t)0.972584369f, + (float16_t)-0.234041959f, (float16_t)0.972226497f, + (float16_t)-0.235533059f, (float16_t)0.971866337f, + (float16_t)-0.237023606f, (float16_t)0.971503891f, + (float16_t)-0.238513595f, (float16_t)0.971139158f, + (float16_t)-0.240003022f, (float16_t)0.970772141f, + (float16_t)-0.241491885f, (float16_t)0.970402839f, + (float16_t)-0.242980180f, (float16_t)0.970031253f, + (float16_t)-0.244467903f, (float16_t)0.969657385f, + (float16_t)-0.245955050f, (float16_t)0.969281235f, + (float16_t)-0.247441619f, (float16_t)0.968902805f, + (float16_t)-0.248927606f, (float16_t)0.968522094f, + (float16_t)-0.250413007f, (float16_t)0.968139105f, + (float16_t)-0.251897818f, (float16_t)0.967753837f, + (float16_t)-0.253382037f, (float16_t)0.967366292f, + (float16_t)-0.254865660f, (float16_t)0.966976471f, + (float16_t)-0.256348682f, (float16_t)0.966584374f, + (float16_t)-0.257831102f, (float16_t)0.966190003f, + (float16_t)-0.259312915f, (float16_t)0.965793359f, + (float16_t)-0.260794118f, (float16_t)0.965394442f, + (float16_t)-0.262274707f, (float16_t)0.964993253f, + (float16_t)-0.263754679f, (float16_t)0.964589793f, + (float16_t)-0.265234030f, (float16_t)0.964184064f, + (float16_t)-0.266712757f, (float16_t)0.963776066f, + (float16_t)-0.268190857f, (float16_t)0.963365800f, + (float16_t)-0.269668326f, (float16_t)0.962953267f, + (float16_t)-0.271145160f, (float16_t)0.962538468f, + (float16_t)-0.272621355f, (float16_t)0.962121404f, + (float16_t)-0.274096910f, (float16_t)0.961702077f, + (float16_t)-0.275571819f, (float16_t)0.961280486f, + (float16_t)-0.277046080f, (float16_t)0.960856633f, + (float16_t)-0.278519689f, (float16_t)0.960430519f, + (float16_t)-0.279992643f, (float16_t)0.960002146f, + (float16_t)-0.281464938f, (float16_t)0.959571513f, + (float16_t)-0.282936570f, (float16_t)0.959138622f, + (float16_t)-0.284407537f, (float16_t)0.958703475f, + (float16_t)-0.285877835f, (float16_t)0.958266071f, + (float16_t)-0.287347460f, (float16_t)0.957826413f, + (float16_t)-0.288816408f, (float16_t)0.957384501f, + (float16_t)-0.290284677f, (float16_t)0.956940336f, + (float16_t)-0.291752263f, (float16_t)0.956493919f, + (float16_t)-0.293219163f, (float16_t)0.956045251f, + (float16_t)-0.294685372f, (float16_t)0.955594334f, + (float16_t)-0.296150888f, (float16_t)0.955141168f, + (float16_t)-0.297615707f, (float16_t)0.954685755f, + (float16_t)-0.299079826f, (float16_t)0.954228095f, + (float16_t)-0.300543241f, (float16_t)0.953768190f, + (float16_t)-0.302005949f, (float16_t)0.953306040f, + (float16_t)-0.303467947f, (float16_t)0.952841648f, + (float16_t)-0.304929230f, (float16_t)0.952375013f, + (float16_t)-0.306389795f, (float16_t)0.951906137f, + (float16_t)-0.307849640f, (float16_t)0.951435021f, + (float16_t)-0.309308760f, (float16_t)0.950961666f, + (float16_t)-0.310767153f, (float16_t)0.950486074f, + (float16_t)-0.312224814f, (float16_t)0.950008245f, + (float16_t)-0.313681740f, (float16_t)0.949528181f, + (float16_t)-0.315137929f, (float16_t)0.949045882f, + (float16_t)-0.316593376f, (float16_t)0.948561350f, + (float16_t)-0.318048077f, (float16_t)0.948074586f, + (float16_t)-0.319502031f, (float16_t)0.947585591f, + (float16_t)-0.320955232f, (float16_t)0.947094366f, + (float16_t)-0.322407679f, (float16_t)0.946600913f, + (float16_t)-0.323859367f, (float16_t)0.946105232f, + (float16_t)-0.325310292f, (float16_t)0.945607325f, + (float16_t)-0.326760452f, (float16_t)0.945107193f, + (float16_t)-0.328209844f, (float16_t)0.944604837f, + (float16_t)-0.329658463f, (float16_t)0.944100258f, + (float16_t)-0.331106306f, (float16_t)0.943593458f, + (float16_t)-0.332553370f, (float16_t)0.943084437f, + (float16_t)-0.333999651f, (float16_t)0.942573198f, + (float16_t)-0.335445147f, (float16_t)0.942059740f, + (float16_t)-0.336889853f, (float16_t)0.941544065f, + (float16_t)-0.338333767f, (float16_t)0.941026175f, + (float16_t)-0.339776884f, (float16_t)0.940506071f, + (float16_t)-0.341219202f, (float16_t)0.939983753f, + (float16_t)-0.342660717f, (float16_t)0.939459224f, + (float16_t)-0.344101426f, (float16_t)0.938932484f, + (float16_t)-0.345541325f, (float16_t)0.938403534f, + (float16_t)-0.346980411f, (float16_t)0.937872376f, + (float16_t)-0.348418680f, (float16_t)0.937339012f, + (float16_t)-0.349856130f, (float16_t)0.936803442f, + (float16_t)-0.351292756f, (float16_t)0.936265667f, + (float16_t)-0.352728556f, (float16_t)0.935725689f, + (float16_t)-0.354163525f, (float16_t)0.935183510f, + (float16_t)-0.355597662f, (float16_t)0.934639130f, + (float16_t)-0.357030961f, (float16_t)0.934092550f, + (float16_t)-0.358463421f, (float16_t)0.933543773f, + (float16_t)-0.359895037f, (float16_t)0.932992799f, + (float16_t)-0.361325806f, (float16_t)0.932439629f, + (float16_t)-0.362755724f, (float16_t)0.931884266f, + (float16_t)-0.364184790f, (float16_t)0.931326709f, + (float16_t)-0.365612998f, (float16_t)0.930766961f, + (float16_t)-0.367040346f, (float16_t)0.930205023f, + (float16_t)-0.368466830f, (float16_t)0.929640896f, + (float16_t)-0.369892447f, (float16_t)0.929074581f, + (float16_t)-0.371317194f, (float16_t)0.928506080f, + (float16_t)-0.372741067f, (float16_t)0.927935395f, + (float16_t)-0.374164063f, (float16_t)0.927362526f, + (float16_t)-0.375586178f, (float16_t)0.926787474f, + (float16_t)-0.377007410f, (float16_t)0.926210242f, + (float16_t)-0.378427755f, (float16_t)0.925630831f, + (float16_t)-0.379847209f, (float16_t)0.925049241f, + (float16_t)-0.381265769f, (float16_t)0.924465474f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.384100195f, (float16_t)0.923291417f, + (float16_t)-0.385516054f, (float16_t)0.922701128f, + (float16_t)-0.386931006f, (float16_t)0.922108669f, + (float16_t)-0.388345047f, (float16_t)0.921514039f, + (float16_t)-0.389758174f, (float16_t)0.920917242f, + (float16_t)-0.391170384f, (float16_t)0.920318277f, + (float16_t)-0.392581674f, (float16_t)0.919717146f, + (float16_t)-0.393992040f, (float16_t)0.919113852f, + (float16_t)-0.395401479f, (float16_t)0.918508394f, + (float16_t)-0.396809987f, (float16_t)0.917900776f, + (float16_t)-0.398217562f, (float16_t)0.917290997f, + (float16_t)-0.399624200f, (float16_t)0.916679060f, + (float16_t)-0.401029897f, (float16_t)0.916064966f, + (float16_t)-0.402434651f, (float16_t)0.915448716f, + (float16_t)-0.403838458f, (float16_t)0.914830312f, + (float16_t)-0.405241314f, (float16_t)0.914209756f, + (float16_t)-0.406643217f, (float16_t)0.913587048f, + (float16_t)-0.408044163f, (float16_t)0.912962190f, + (float16_t)-0.409444149f, (float16_t)0.912335185f, + (float16_t)-0.410843171f, (float16_t)0.911706032f, + (float16_t)-0.412241227f, (float16_t)0.911074734f, + (float16_t)-0.413638312f, (float16_t)0.910441292f, + (float16_t)-0.415034424f, (float16_t)0.909805708f, + (float16_t)-0.416429560f, (float16_t)0.909167983f, + (float16_t)-0.417823716f, (float16_t)0.908528119f, + (float16_t)-0.419216888f, (float16_t)0.907886116f, + (float16_t)-0.420609074f, (float16_t)0.907241978f, + (float16_t)-0.422000271f, (float16_t)0.906595705f, + (float16_t)-0.423390474f, (float16_t)0.905947298f, + (float16_t)-0.424779681f, (float16_t)0.905296759f, + (float16_t)-0.426167889f, (float16_t)0.904644091f, + (float16_t)-0.427555093f, (float16_t)0.903989293f, + (float16_t)-0.428941292f, (float16_t)0.903332368f, + (float16_t)-0.430326481f, (float16_t)0.902673318f, + (float16_t)-0.431710658f, (float16_t)0.902012144f, + (float16_t)-0.433093819f, (float16_t)0.901348847f, + (float16_t)-0.434475961f, (float16_t)0.900683429f, + (float16_t)-0.435857080f, (float16_t)0.900015892f, + (float16_t)-0.437237174f, (float16_t)0.899346237f, + (float16_t)-0.438616239f, (float16_t)0.898674466f, + (float16_t)-0.439994271f, (float16_t)0.898000580f, + (float16_t)-0.441371269f, (float16_t)0.897324581f, + (float16_t)-0.442747228f, (float16_t)0.896646470f, + (float16_t)-0.444122145f, (float16_t)0.895966250f, + (float16_t)-0.445496017f, (float16_t)0.895283921f, + (float16_t)-0.446868840f, (float16_t)0.894599486f, + (float16_t)-0.448240612f, (float16_t)0.893912945f, + (float16_t)-0.449611330f, (float16_t)0.893224301f, + (float16_t)-0.450980989f, (float16_t)0.892533555f, + (float16_t)-0.452349587f, (float16_t)0.891840709f, + (float16_t)-0.453717121f, (float16_t)0.891145765f, + (float16_t)-0.455083587f, (float16_t)0.890448723f, + (float16_t)-0.456448982f, (float16_t)0.889749586f, + (float16_t)-0.457813304f, (float16_t)0.889048356f, + (float16_t)-0.459176548f, (float16_t)0.888345033f, + (float16_t)-0.460538711f, (float16_t)0.887639620f, + (float16_t)-0.461899791f, (float16_t)0.886932119f, + (float16_t)-0.463259784f, (float16_t)0.886222530f, + (float16_t)-0.464618686f, (float16_t)0.885510856f, + (float16_t)-0.465976496f, (float16_t)0.884797098f, + (float16_t)-0.467333209f, (float16_t)0.884081259f, + (float16_t)-0.468688822f, (float16_t)0.883363339f, + (float16_t)-0.470043332f, (float16_t)0.882643340f, + (float16_t)-0.471396737f, (float16_t)0.881921264f, + (float16_t)-0.472749032f, (float16_t)0.881197113f, + (float16_t)-0.474100215f, (float16_t)0.880470889f, + (float16_t)-0.475450282f, (float16_t)0.879742593f, + (float16_t)-0.476799230f, (float16_t)0.879012226f, + (float16_t)-0.478147056f, (float16_t)0.878279792f, + (float16_t)-0.479493758f, (float16_t)0.877545290f, + (float16_t)-0.480839331f, (float16_t)0.876808724f, + (float16_t)-0.482183772f, (float16_t)0.876070094f, + (float16_t)-0.483527079f, (float16_t)0.875329403f, + (float16_t)-0.484869248f, (float16_t)0.874586652f, + (float16_t)-0.486210276f, (float16_t)0.873841843f, + (float16_t)-0.487550160f, (float16_t)0.873094978f, + (float16_t)-0.488888897f, (float16_t)0.872346059f, + (float16_t)-0.490226483f, (float16_t)0.871595087f, + (float16_t)-0.491562916f, (float16_t)0.870842063f, + (float16_t)-0.492898192f, (float16_t)0.870086991f, + (float16_t)-0.494232309f, (float16_t)0.869329871f, + (float16_t)-0.495565262f, (float16_t)0.868570706f, + (float16_t)-0.496897049f, (float16_t)0.867809497f, + (float16_t)-0.498227667f, (float16_t)0.867046246f, + (float16_t)-0.499557113f, (float16_t)0.866280954f, + (float16_t)-0.500885383f, (float16_t)0.865513624f, + (float16_t)-0.502212474f, (float16_t)0.864744258f, + (float16_t)-0.503538384f, (float16_t)0.863972856f, + (float16_t)-0.504863109f, (float16_t)0.863199422f, + (float16_t)-0.506186645f, (float16_t)0.862423956f, + (float16_t)-0.507508991f, (float16_t)0.861646461f, + (float16_t)-0.508830143f, (float16_t)0.860866939f, + (float16_t)-0.510150097f, (float16_t)0.860085390f, + (float16_t)-0.511468850f, (float16_t)0.859301818f, + (float16_t)-0.512786401f, (float16_t)0.858516224f, + (float16_t)-0.514102744f, (float16_t)0.857728610f, + (float16_t)-0.515417878f, (float16_t)0.856938977f, + (float16_t)-0.516731799f, (float16_t)0.856147328f, + (float16_t)-0.518044504f, (float16_t)0.855353665f, + (float16_t)-0.519355990f, (float16_t)0.854557988f, + (float16_t)-0.520666254f, (float16_t)0.853760301f, + (float16_t)-0.521975293f, (float16_t)0.852960605f, + (float16_t)-0.523283103f, (float16_t)0.852158902f, + (float16_t)-0.524589683f, (float16_t)0.851355193f, + (float16_t)-0.525895027f, (float16_t)0.850549481f, + (float16_t)-0.527199135f, (float16_t)0.849741768f, + (float16_t)-0.528502002f, (float16_t)0.848932055f, + (float16_t)-0.529803625f, (float16_t)0.848120345f, + (float16_t)-0.531104001f, (float16_t)0.847306639f, + (float16_t)-0.532403128f, (float16_t)0.846490939f, + (float16_t)-0.533701002f, (float16_t)0.845673247f, + (float16_t)-0.534997620f, (float16_t)0.844853565f, + (float16_t)-0.536292979f, (float16_t)0.844031895f, + (float16_t)-0.537587076f, (float16_t)0.843208240f, + (float16_t)-0.538879909f, (float16_t)0.842382600f, + (float16_t)-0.540171473f, (float16_t)0.841554977f, + (float16_t)-0.541461766f, (float16_t)0.840725375f, + (float16_t)-0.542750785f, (float16_t)0.839893794f, + (float16_t)-0.544038527f, (float16_t)0.839060237f, + (float16_t)-0.545324988f, (float16_t)0.838224706f, + (float16_t)-0.546610167f, (float16_t)0.837387202f, + (float16_t)-0.547894059f, (float16_t)0.836547727f, + (float16_t)-0.549176662f, (float16_t)0.835706284f, + (float16_t)-0.550457973f, (float16_t)0.834862875f, + (float16_t)-0.551737988f, (float16_t)0.834017501f, + (float16_t)-0.553016706f, (float16_t)0.833170165f, + (float16_t)-0.554294121f, (float16_t)0.832320868f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.556845037f, (float16_t)0.830616400f, + (float16_t)-0.558118531f, (float16_t)0.829761234f, + (float16_t)-0.559390712f, (float16_t)0.828904115f, + (float16_t)-0.560661576f, (float16_t)0.828045045f, + (float16_t)-0.561931121f, (float16_t)0.827184027f, + (float16_t)-0.563199344f, (float16_t)0.826321063f, + (float16_t)-0.564466242f, (float16_t)0.825456154f, + (float16_t)-0.565731811f, (float16_t)0.824589303f, + (float16_t)-0.566996049f, (float16_t)0.823720511f, + (float16_t)-0.568258953f, (float16_t)0.822849781f, + (float16_t)-0.569520519f, (float16_t)0.821977115f, + (float16_t)-0.570780746f, (float16_t)0.821102515f, + (float16_t)-0.572039629f, (float16_t)0.820225983f, + (float16_t)-0.573297167f, (float16_t)0.819347520f, + (float16_t)-0.574553355f, (float16_t)0.818467130f, + (float16_t)-0.575808191f, (float16_t)0.817584813f, + (float16_t)-0.577061673f, (float16_t)0.816700573f, + (float16_t)-0.578313796f, (float16_t)0.815814411f, + (float16_t)-0.579564559f, (float16_t)0.814926329f, + (float16_t)-0.580813958f, (float16_t)0.814036330f, + (float16_t)-0.582061990f, (float16_t)0.813144415f, + (float16_t)-0.583308653f, (float16_t)0.812250587f, + (float16_t)-0.584553943f, (float16_t)0.811354847f, + (float16_t)-0.585797857f, (float16_t)0.810457198f, + (float16_t)-0.587040394f, (float16_t)0.809557642f, + (float16_t)-0.588281548f, (float16_t)0.808656182f, + (float16_t)-0.589521319f, (float16_t)0.807752818f, + (float16_t)-0.590759702f, (float16_t)0.806847554f, + (float16_t)-0.591996695f, (float16_t)0.805940391f, + (float16_t)-0.593232295f, (float16_t)0.805031331f, + (float16_t)-0.594466499f, (float16_t)0.804120377f, + (float16_t)-0.595699304f, (float16_t)0.803207531f, + (float16_t)-0.596930708f, (float16_t)0.802292796f, + (float16_t)-0.598160707f, (float16_t)0.801376172f, + (float16_t)-0.599389298f, (float16_t)0.800457662f, + (float16_t)-0.600616479f, (float16_t)0.799537269f, + (float16_t)-0.601842247f, (float16_t)0.798614995f, + (float16_t)-0.603066599f, (float16_t)0.797690841f, + (float16_t)-0.604289531f, (float16_t)0.796764810f, + (float16_t)-0.605511041f, (float16_t)0.795836905f, + (float16_t)-0.606731127f, (float16_t)0.794907126f, + (float16_t)-0.607949785f, (float16_t)0.793975478f, + (float16_t)-0.609167012f, (float16_t)0.793041960f, + (float16_t)-0.610382806f, (float16_t)0.792106577f, + (float16_t)-0.611597164f, (float16_t)0.791169330f, + (float16_t)-0.612810082f, (float16_t)0.790230221f, + (float16_t)-0.614021559f, (float16_t)0.789289253f, + (float16_t)-0.615231591f, (float16_t)0.788346428f, + (float16_t)-0.616440175f, (float16_t)0.787401747f, + (float16_t)-0.617647308f, (float16_t)0.786455214f, + (float16_t)-0.618852988f, (float16_t)0.785506830f, + (float16_t)-0.620057212f, (float16_t)0.784556597f, + (float16_t)-0.621259977f, (float16_t)0.783604519f, + (float16_t)-0.622461279f, (float16_t)0.782650596f, + (float16_t)-0.623661118f, (float16_t)0.781694832f, + (float16_t)-0.624859488f, (float16_t)0.780737229f, + (float16_t)-0.626056388f, (float16_t)0.779777788f, + (float16_t)-0.627251815f, (float16_t)0.778816512f, + (float16_t)-0.628445767f, (float16_t)0.777853404f, + (float16_t)-0.629638239f, (float16_t)0.776888466f, + (float16_t)-0.630829230f, (float16_t)0.775921699f, + (float16_t)-0.632018736f, (float16_t)0.774953107f, + (float16_t)-0.633206755f, (float16_t)0.773982691f, + (float16_t)-0.634393284f, (float16_t)0.773010453f, + (float16_t)-0.635578320f, (float16_t)0.772036397f, + (float16_t)-0.636761861f, (float16_t)0.771060524f, + (float16_t)-0.637943904f, (float16_t)0.770082837f, + (float16_t)-0.639124445f, (float16_t)0.769103338f, + (float16_t)-0.640303482f, (float16_t)0.768122029f, + (float16_t)-0.641481013f, (float16_t)0.767138912f, + (float16_t)-0.642657034f, (float16_t)0.766153990f, + (float16_t)-0.643831543f, (float16_t)0.765167266f, + (float16_t)-0.645004537f, (float16_t)0.764178741f, + (float16_t)-0.646176013f, (float16_t)0.763188417f, + (float16_t)-0.647345969f, (float16_t)0.762196298f, + (float16_t)-0.648514401f, (float16_t)0.761202385f, + (float16_t)-0.649681307f, (float16_t)0.760206682f, + (float16_t)-0.650846685f, (float16_t)0.759209189f, + (float16_t)-0.652010531f, (float16_t)0.758209910f, + (float16_t)-0.653172843f, (float16_t)0.757208847f, + (float16_t)-0.654333618f, (float16_t)0.756206001f, + (float16_t)-0.655492853f, (float16_t)0.755201377f, + (float16_t)-0.656650546f, (float16_t)0.754194975f, + (float16_t)-0.657806693f, (float16_t)0.753186799f, + (float16_t)-0.658961293f, (float16_t)0.752176850f, + (float16_t)-0.660114342f, (float16_t)0.751165132f, + (float16_t)-0.661265838f, (float16_t)0.750151646f, + (float16_t)-0.662415778f, (float16_t)0.749136395f, + (float16_t)-0.663564159f, (float16_t)0.748119380f, + (float16_t)-0.664710978f, (float16_t)0.747100606f, + (float16_t)-0.665856234f, (float16_t)0.746080074f, + (float16_t)-0.666999922f, (float16_t)0.745057785f, + (float16_t)-0.668142041f, (float16_t)0.744033744f, + (float16_t)-0.669282588f, (float16_t)0.743007952f, + (float16_t)-0.670421560f, (float16_t)0.741980412f, + (float16_t)-0.671558955f, (float16_t)0.740951125f, + (float16_t)-0.672694769f, (float16_t)0.739920095f, + (float16_t)-0.673829000f, (float16_t)0.738887324f, + (float16_t)-0.674961646f, (float16_t)0.737852815f, + (float16_t)-0.676092704f, (float16_t)0.736816569f, + (float16_t)-0.677222170f, (float16_t)0.735778589f, + (float16_t)-0.678350043f, (float16_t)0.734738878f, + (float16_t)-0.679476320f, (float16_t)0.733697438f, + (float16_t)-0.680600998f, (float16_t)0.732654272f, + (float16_t)-0.681724074f, (float16_t)0.731609381f, + (float16_t)-0.682845546f, (float16_t)0.730562769f, + (float16_t)-0.683965412f, (float16_t)0.729514438f, + (float16_t)-0.685083668f, (float16_t)0.728464390f, + (float16_t)-0.686200312f, (float16_t)0.727412629f, + (float16_t)-0.687315341f, (float16_t)0.726359155f, + (float16_t)-0.688428753f, (float16_t)0.725303972f, + (float16_t)-0.689540545f, (float16_t)0.724247083f, + (float16_t)-0.690650714f, (float16_t)0.723188489f, + (float16_t)-0.691759258f, (float16_t)0.722128194f, + (float16_t)-0.692866175f, (float16_t)0.721066199f, + (float16_t)-0.693971461f, (float16_t)0.720002508f, + (float16_t)-0.695075114f, (float16_t)0.718937122f, + (float16_t)-0.696177131f, (float16_t)0.717870045f, + (float16_t)-0.697277511f, (float16_t)0.716801279f, + (float16_t)-0.698376249f, (float16_t)0.715730825f, + (float16_t)-0.699473345f, (float16_t)0.714658688f, + (float16_t)-0.700568794f, (float16_t)0.713584869f, + (float16_t)-0.701662595f, (float16_t)0.712509371f, + (float16_t)-0.702754744f, (float16_t)0.711432196f, + (float16_t)-0.703845241f, (float16_t)0.710353347f, + (float16_t)-0.704934080f, (float16_t)0.709272826f, + (float16_t)-0.706021261f, (float16_t)0.708190637f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.708190637f, (float16_t)0.706021261f, + (float16_t)-0.709272826f, (float16_t)0.704934080f, + (float16_t)-0.710353347f, (float16_t)0.703845241f, + (float16_t)-0.711432196f, (float16_t)0.702754744f, + (float16_t)-0.712509371f, (float16_t)0.701662595f, + (float16_t)-0.713584869f, (float16_t)0.700568794f, + (float16_t)-0.714658688f, (float16_t)0.699473345f, + (float16_t)-0.715730825f, (float16_t)0.698376249f, + (float16_t)-0.716801279f, (float16_t)0.697277511f, + (float16_t)-0.717870045f, (float16_t)0.696177131f, + (float16_t)-0.718937122f, (float16_t)0.695075114f, + (float16_t)-0.720002508f, (float16_t)0.693971461f, + (float16_t)-0.721066199f, (float16_t)0.692866175f, + (float16_t)-0.722128194f, (float16_t)0.691759258f, + (float16_t)-0.723188489f, (float16_t)0.690650714f, + (float16_t)-0.724247083f, (float16_t)0.689540545f, + (float16_t)-0.725303972f, (float16_t)0.688428753f, + (float16_t)-0.726359155f, (float16_t)0.687315341f, + (float16_t)-0.727412629f, (float16_t)0.686200312f, + (float16_t)-0.728464390f, (float16_t)0.685083668f, + (float16_t)-0.729514438f, (float16_t)0.683965412f, + (float16_t)-0.730562769f, (float16_t)0.682845546f, + (float16_t)-0.731609381f, (float16_t)0.681724074f, + (float16_t)-0.732654272f, (float16_t)0.680600998f, + (float16_t)-0.733697438f, (float16_t)0.679476320f, + (float16_t)-0.734738878f, (float16_t)0.678350043f, + (float16_t)-0.735778589f, (float16_t)0.677222170f, + (float16_t)-0.736816569f, (float16_t)0.676092704f, + (float16_t)-0.737852815f, (float16_t)0.674961646f, + (float16_t)-0.738887324f, (float16_t)0.673829000f, + (float16_t)-0.739920095f, (float16_t)0.672694769f, + (float16_t)-0.740951125f, (float16_t)0.671558955f, + (float16_t)-0.741980412f, (float16_t)0.670421560f, + (float16_t)-0.743007952f, (float16_t)0.669282588f, + (float16_t)-0.744033744f, (float16_t)0.668142041f, + (float16_t)-0.745057785f, (float16_t)0.666999922f, + (float16_t)-0.746080074f, (float16_t)0.665856234f, + (float16_t)-0.747100606f, (float16_t)0.664710978f, + (float16_t)-0.748119380f, (float16_t)0.663564159f, + (float16_t)-0.749136395f, (float16_t)0.662415778f, + (float16_t)-0.750151646f, (float16_t)0.661265838f, + (float16_t)-0.751165132f, (float16_t)0.660114342f, + (float16_t)-0.752176850f, (float16_t)0.658961293f, + (float16_t)-0.753186799f, (float16_t)0.657806693f, + (float16_t)-0.754194975f, (float16_t)0.656650546f, + (float16_t)-0.755201377f, (float16_t)0.655492853f, + (float16_t)-0.756206001f, (float16_t)0.654333618f, + (float16_t)-0.757208847f, (float16_t)0.653172843f, + (float16_t)-0.758209910f, (float16_t)0.652010531f, + (float16_t)-0.759209189f, (float16_t)0.650846685f, + (float16_t)-0.760206682f, (float16_t)0.649681307f, + (float16_t)-0.761202385f, (float16_t)0.648514401f, + (float16_t)-0.762196298f, (float16_t)0.647345969f, + (float16_t)-0.763188417f, (float16_t)0.646176013f, + (float16_t)-0.764178741f, (float16_t)0.645004537f, + (float16_t)-0.765167266f, (float16_t)0.643831543f, + (float16_t)-0.766153990f, (float16_t)0.642657034f, + (float16_t)-0.767138912f, (float16_t)0.641481013f, + (float16_t)-0.768122029f, (float16_t)0.640303482f, + (float16_t)-0.769103338f, (float16_t)0.639124445f, + (float16_t)-0.770082837f, (float16_t)0.637943904f, + (float16_t)-0.771060524f, (float16_t)0.636761861f, + (float16_t)-0.772036397f, (float16_t)0.635578320f, + (float16_t)-0.773010453f, (float16_t)0.634393284f, + (float16_t)-0.773982691f, (float16_t)0.633206755f, + (float16_t)-0.774953107f, (float16_t)0.632018736f, + (float16_t)-0.775921699f, (float16_t)0.630829230f, + (float16_t)-0.776888466f, (float16_t)0.629638239f, + (float16_t)-0.777853404f, (float16_t)0.628445767f, + (float16_t)-0.778816512f, (float16_t)0.627251815f, + (float16_t)-0.779777788f, (float16_t)0.626056388f, + (float16_t)-0.780737229f, (float16_t)0.624859488f, + (float16_t)-0.781694832f, (float16_t)0.623661118f, + (float16_t)-0.782650596f, (float16_t)0.622461279f, + (float16_t)-0.783604519f, (float16_t)0.621259977f, + (float16_t)-0.784556597f, (float16_t)0.620057212f, + (float16_t)-0.785506830f, (float16_t)0.618852988f, + (float16_t)-0.786455214f, (float16_t)0.617647308f, + (float16_t)-0.787401747f, (float16_t)0.616440175f, + (float16_t)-0.788346428f, (float16_t)0.615231591f, + (float16_t)-0.789289253f, (float16_t)0.614021559f, + (float16_t)-0.790230221f, (float16_t)0.612810082f, + (float16_t)-0.791169330f, (float16_t)0.611597164f, + (float16_t)-0.792106577f, (float16_t)0.610382806f, + (float16_t)-0.793041960f, (float16_t)0.609167012f, + (float16_t)-0.793975478f, (float16_t)0.607949785f, + (float16_t)-0.794907126f, (float16_t)0.606731127f, + (float16_t)-0.795836905f, (float16_t)0.605511041f, + (float16_t)-0.796764810f, (float16_t)0.604289531f, + (float16_t)-0.797690841f, (float16_t)0.603066599f, + (float16_t)-0.798614995f, (float16_t)0.601842247f, + (float16_t)-0.799537269f, (float16_t)0.600616479f, + (float16_t)-0.800457662f, (float16_t)0.599389298f, + (float16_t)-0.801376172f, (float16_t)0.598160707f, + (float16_t)-0.802292796f, (float16_t)0.596930708f, + (float16_t)-0.803207531f, (float16_t)0.595699304f, + (float16_t)-0.804120377f, (float16_t)0.594466499f, + (float16_t)-0.805031331f, (float16_t)0.593232295f, + (float16_t)-0.805940391f, (float16_t)0.591996695f, + (float16_t)-0.806847554f, (float16_t)0.590759702f, + (float16_t)-0.807752818f, (float16_t)0.589521319f, + (float16_t)-0.808656182f, (float16_t)0.588281548f, + (float16_t)-0.809557642f, (float16_t)0.587040394f, + (float16_t)-0.810457198f, (float16_t)0.585797857f, + (float16_t)-0.811354847f, (float16_t)0.584553943f, + (float16_t)-0.812250587f, (float16_t)0.583308653f, + (float16_t)-0.813144415f, (float16_t)0.582061990f, + (float16_t)-0.814036330f, (float16_t)0.580813958f, + (float16_t)-0.814926329f, (float16_t)0.579564559f, + (float16_t)-0.815814411f, (float16_t)0.578313796f, + (float16_t)-0.816700573f, (float16_t)0.577061673f, + (float16_t)-0.817584813f, (float16_t)0.575808191f, + (float16_t)-0.818467130f, (float16_t)0.574553355f, + (float16_t)-0.819347520f, (float16_t)0.573297167f, + (float16_t)-0.820225983f, (float16_t)0.572039629f, + (float16_t)-0.821102515f, (float16_t)0.570780746f, + (float16_t)-0.821977115f, (float16_t)0.569520519f, + (float16_t)-0.822849781f, (float16_t)0.568258953f, + (float16_t)-0.823720511f, (float16_t)0.566996049f, + (float16_t)-0.824589303f, (float16_t)0.565731811f, + (float16_t)-0.825456154f, (float16_t)0.564466242f, + (float16_t)-0.826321063f, (float16_t)0.563199344f, + (float16_t)-0.827184027f, (float16_t)0.561931121f, + (float16_t)-0.828045045f, (float16_t)0.560661576f, + (float16_t)-0.828904115f, (float16_t)0.559390712f, + (float16_t)-0.829761234f, (float16_t)0.558118531f, + (float16_t)-0.830616400f, (float16_t)0.556845037f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.832320868f, (float16_t)0.554294121f, + (float16_t)-0.833170165f, (float16_t)0.553016706f, + (float16_t)-0.834017501f, (float16_t)0.551737988f, + (float16_t)-0.834862875f, (float16_t)0.550457973f, + (float16_t)-0.835706284f, (float16_t)0.549176662f, + (float16_t)-0.836547727f, (float16_t)0.547894059f, + (float16_t)-0.837387202f, (float16_t)0.546610167f, + (float16_t)-0.838224706f, (float16_t)0.545324988f, + (float16_t)-0.839060237f, (float16_t)0.544038527f, + (float16_t)-0.839893794f, (float16_t)0.542750785f, + (float16_t)-0.840725375f, (float16_t)0.541461766f, + (float16_t)-0.841554977f, (float16_t)0.540171473f, + (float16_t)-0.842382600f, (float16_t)0.538879909f, + (float16_t)-0.843208240f, (float16_t)0.537587076f, + (float16_t)-0.844031895f, (float16_t)0.536292979f, + (float16_t)-0.844853565f, (float16_t)0.534997620f, + (float16_t)-0.845673247f, (float16_t)0.533701002f, + (float16_t)-0.846490939f, (float16_t)0.532403128f, + (float16_t)-0.847306639f, (float16_t)0.531104001f, + (float16_t)-0.848120345f, (float16_t)0.529803625f, + (float16_t)-0.848932055f, (float16_t)0.528502002f, + (float16_t)-0.849741768f, (float16_t)0.527199135f, + (float16_t)-0.850549481f, (float16_t)0.525895027f, + (float16_t)-0.851355193f, (float16_t)0.524589683f, + (float16_t)-0.852158902f, (float16_t)0.523283103f, + (float16_t)-0.852960605f, (float16_t)0.521975293f, + (float16_t)-0.853760301f, (float16_t)0.520666254f, + (float16_t)-0.854557988f, (float16_t)0.519355990f, + (float16_t)-0.855353665f, (float16_t)0.518044504f, + (float16_t)-0.856147328f, (float16_t)0.516731799f, + (float16_t)-0.856938977f, (float16_t)0.515417878f, + (float16_t)-0.857728610f, (float16_t)0.514102744f, + (float16_t)-0.858516224f, (float16_t)0.512786401f, + (float16_t)-0.859301818f, (float16_t)0.511468850f, + (float16_t)-0.860085390f, (float16_t)0.510150097f, + (float16_t)-0.860866939f, (float16_t)0.508830143f, + (float16_t)-0.861646461f, (float16_t)0.507508991f, + (float16_t)-0.862423956f, (float16_t)0.506186645f, + (float16_t)-0.863199422f, (float16_t)0.504863109f, + (float16_t)-0.863972856f, (float16_t)0.503538384f, + (float16_t)-0.864744258f, (float16_t)0.502212474f, + (float16_t)-0.865513624f, (float16_t)0.500885383f, + (float16_t)-0.866280954f, (float16_t)0.499557113f, + (float16_t)-0.867046246f, (float16_t)0.498227667f, + (float16_t)-0.867809497f, (float16_t)0.496897049f, + (float16_t)-0.868570706f, (float16_t)0.495565262f, + (float16_t)-0.869329871f, (float16_t)0.494232309f, + (float16_t)-0.870086991f, (float16_t)0.492898192f, + (float16_t)-0.870842063f, (float16_t)0.491562916f, + (float16_t)-0.871595087f, (float16_t)0.490226483f, + (float16_t)-0.872346059f, (float16_t)0.488888897f, + (float16_t)-0.873094978f, (float16_t)0.487550160f, + (float16_t)-0.873841843f, (float16_t)0.486210276f, + (float16_t)-0.874586652f, (float16_t)0.484869248f, + (float16_t)-0.875329403f, (float16_t)0.483527079f, + (float16_t)-0.876070094f, (float16_t)0.482183772f, + (float16_t)-0.876808724f, (float16_t)0.480839331f, + (float16_t)-0.877545290f, (float16_t)0.479493758f, + (float16_t)-0.878279792f, (float16_t)0.478147056f, + (float16_t)-0.879012226f, (float16_t)0.476799230f, + (float16_t)-0.879742593f, (float16_t)0.475450282f, + (float16_t)-0.880470889f, (float16_t)0.474100215f, + (float16_t)-0.881197113f, (float16_t)0.472749032f, + (float16_t)-0.881921264f, (float16_t)0.471396737f, + (float16_t)-0.882643340f, (float16_t)0.470043332f, + (float16_t)-0.883363339f, (float16_t)0.468688822f, + (float16_t)-0.884081259f, (float16_t)0.467333209f, + (float16_t)-0.884797098f, (float16_t)0.465976496f, + (float16_t)-0.885510856f, (float16_t)0.464618686f, + (float16_t)-0.886222530f, (float16_t)0.463259784f, + (float16_t)-0.886932119f, (float16_t)0.461899791f, + (float16_t)-0.887639620f, (float16_t)0.460538711f, + (float16_t)-0.888345033f, (float16_t)0.459176548f, + (float16_t)-0.889048356f, (float16_t)0.457813304f, + (float16_t)-0.889749586f, (float16_t)0.456448982f, + (float16_t)-0.890448723f, (float16_t)0.455083587f, + (float16_t)-0.891145765f, (float16_t)0.453717121f, + (float16_t)-0.891840709f, (float16_t)0.452349587f, + (float16_t)-0.892533555f, (float16_t)0.450980989f, + (float16_t)-0.893224301f, (float16_t)0.449611330f, + (float16_t)-0.893912945f, (float16_t)0.448240612f, + (float16_t)-0.894599486f, (float16_t)0.446868840f, + (float16_t)-0.895283921f, (float16_t)0.445496017f, + (float16_t)-0.895966250f, (float16_t)0.444122145f, + (float16_t)-0.896646470f, (float16_t)0.442747228f, + (float16_t)-0.897324581f, (float16_t)0.441371269f, + (float16_t)-0.898000580f, (float16_t)0.439994271f, + (float16_t)-0.898674466f, (float16_t)0.438616239f, + (float16_t)-0.899346237f, (float16_t)0.437237174f, + (float16_t)-0.900015892f, (float16_t)0.435857080f, + (float16_t)-0.900683429f, (float16_t)0.434475961f, + (float16_t)-0.901348847f, (float16_t)0.433093819f, + (float16_t)-0.902012144f, (float16_t)0.431710658f, + (float16_t)-0.902673318f, (float16_t)0.430326481f, + (float16_t)-0.903332368f, (float16_t)0.428941292f, + (float16_t)-0.903989293f, (float16_t)0.427555093f, + (float16_t)-0.904644091f, (float16_t)0.426167889f, + (float16_t)-0.905296759f, (float16_t)0.424779681f, + (float16_t)-0.905947298f, (float16_t)0.423390474f, + (float16_t)-0.906595705f, (float16_t)0.422000271f, + (float16_t)-0.907241978f, (float16_t)0.420609074f, + (float16_t)-0.907886116f, (float16_t)0.419216888f, + (float16_t)-0.908528119f, (float16_t)0.417823716f, + (float16_t)-0.909167983f, (float16_t)0.416429560f, + (float16_t)-0.909805708f, (float16_t)0.415034424f, + (float16_t)-0.910441292f, (float16_t)0.413638312f, + (float16_t)-0.911074734f, (float16_t)0.412241227f, + (float16_t)-0.911706032f, (float16_t)0.410843171f, + (float16_t)-0.912335185f, (float16_t)0.409444149f, + (float16_t)-0.912962190f, (float16_t)0.408044163f, + (float16_t)-0.913587048f, (float16_t)0.406643217f, + (float16_t)-0.914209756f, (float16_t)0.405241314f, + (float16_t)-0.914830312f, (float16_t)0.403838458f, + (float16_t)-0.915448716f, (float16_t)0.402434651f, + (float16_t)-0.916064966f, (float16_t)0.401029897f, + (float16_t)-0.916679060f, (float16_t)0.399624200f, + (float16_t)-0.917290997f, (float16_t)0.398217562f, + (float16_t)-0.917900776f, (float16_t)0.396809987f, + (float16_t)-0.918508394f, (float16_t)0.395401479f, + (float16_t)-0.919113852f, (float16_t)0.393992040f, + (float16_t)-0.919717146f, (float16_t)0.392581674f, + (float16_t)-0.920318277f, (float16_t)0.391170384f, + (float16_t)-0.920917242f, (float16_t)0.389758174f, + (float16_t)-0.921514039f, (float16_t)0.388345047f, + (float16_t)-0.922108669f, (float16_t)0.386931006f, + (float16_t)-0.922701128f, (float16_t)0.385516054f, + (float16_t)-0.923291417f, (float16_t)0.384100195f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.924465474f, (float16_t)0.381265769f, + (float16_t)-0.925049241f, (float16_t)0.379847209f, + (float16_t)-0.925630831f, (float16_t)0.378427755f, + (float16_t)-0.926210242f, (float16_t)0.377007410f, + (float16_t)-0.926787474f, (float16_t)0.375586178f, + (float16_t)-0.927362526f, (float16_t)0.374164063f, + (float16_t)-0.927935395f, (float16_t)0.372741067f, + (float16_t)-0.928506080f, (float16_t)0.371317194f, + (float16_t)-0.929074581f, (float16_t)0.369892447f, + (float16_t)-0.929640896f, (float16_t)0.368466830f, + (float16_t)-0.930205023f, (float16_t)0.367040346f, + (float16_t)-0.930766961f, (float16_t)0.365612998f, + (float16_t)-0.931326709f, (float16_t)0.364184790f, + (float16_t)-0.931884266f, (float16_t)0.362755724f, + (float16_t)-0.932439629f, (float16_t)0.361325806f, + (float16_t)-0.932992799f, (float16_t)0.359895037f, + (float16_t)-0.933543773f, (float16_t)0.358463421f, + (float16_t)-0.934092550f, (float16_t)0.357030961f, + (float16_t)-0.934639130f, (float16_t)0.355597662f, + (float16_t)-0.935183510f, (float16_t)0.354163525f, + (float16_t)-0.935725689f, (float16_t)0.352728556f, + (float16_t)-0.936265667f, (float16_t)0.351292756f, + (float16_t)-0.936803442f, (float16_t)0.349856130f, + (float16_t)-0.937339012f, (float16_t)0.348418680f, + (float16_t)-0.937872376f, (float16_t)0.346980411f, + (float16_t)-0.938403534f, (float16_t)0.345541325f, + (float16_t)-0.938932484f, (float16_t)0.344101426f, + (float16_t)-0.939459224f, (float16_t)0.342660717f, + (float16_t)-0.939983753f, (float16_t)0.341219202f, + (float16_t)-0.940506071f, (float16_t)0.339776884f, + (float16_t)-0.941026175f, (float16_t)0.338333767f, + (float16_t)-0.941544065f, (float16_t)0.336889853f, + (float16_t)-0.942059740f, (float16_t)0.335445147f, + (float16_t)-0.942573198f, (float16_t)0.333999651f, + (float16_t)-0.943084437f, (float16_t)0.332553370f, + (float16_t)-0.943593458f, (float16_t)0.331106306f, + (float16_t)-0.944100258f, (float16_t)0.329658463f, + (float16_t)-0.944604837f, (float16_t)0.328209844f, + (float16_t)-0.945107193f, (float16_t)0.326760452f, + (float16_t)-0.945607325f, (float16_t)0.325310292f, + (float16_t)-0.946105232f, (float16_t)0.323859367f, + (float16_t)-0.946600913f, (float16_t)0.322407679f, + (float16_t)-0.947094366f, (float16_t)0.320955232f, + (float16_t)-0.947585591f, (float16_t)0.319502031f, + (float16_t)-0.948074586f, (float16_t)0.318048077f, + (float16_t)-0.948561350f, (float16_t)0.316593376f, + (float16_t)-0.949045882f, (float16_t)0.315137929f, + (float16_t)-0.949528181f, (float16_t)0.313681740f, + (float16_t)-0.950008245f, (float16_t)0.312224814f, + (float16_t)-0.950486074f, (float16_t)0.310767153f, + (float16_t)-0.950961666f, (float16_t)0.309308760f, + (float16_t)-0.951435021f, (float16_t)0.307849640f, + (float16_t)-0.951906137f, (float16_t)0.306389795f, + (float16_t)-0.952375013f, (float16_t)0.304929230f, + (float16_t)-0.952841648f, (float16_t)0.303467947f, + (float16_t)-0.953306040f, (float16_t)0.302005949f, + (float16_t)-0.953768190f, (float16_t)0.300543241f, + (float16_t)-0.954228095f, (float16_t)0.299079826f, + (float16_t)-0.954685755f, (float16_t)0.297615707f, + (float16_t)-0.955141168f, (float16_t)0.296150888f, + (float16_t)-0.955594334f, (float16_t)0.294685372f, + (float16_t)-0.956045251f, (float16_t)0.293219163f, + (float16_t)-0.956493919f, (float16_t)0.291752263f, + (float16_t)-0.956940336f, (float16_t)0.290284677f, + (float16_t)-0.957384501f, (float16_t)0.288816408f, + (float16_t)-0.957826413f, (float16_t)0.287347460f, + (float16_t)-0.958266071f, (float16_t)0.285877835f, + (float16_t)-0.958703475f, (float16_t)0.284407537f, + (float16_t)-0.959138622f, (float16_t)0.282936570f, + (float16_t)-0.959571513f, (float16_t)0.281464938f, + (float16_t)-0.960002146f, (float16_t)0.279992643f, + (float16_t)-0.960430519f, (float16_t)0.278519689f, + (float16_t)-0.960856633f, (float16_t)0.277046080f, + (float16_t)-0.961280486f, (float16_t)0.275571819f, + (float16_t)-0.961702077f, (float16_t)0.274096910f, + (float16_t)-0.962121404f, (float16_t)0.272621355f, + (float16_t)-0.962538468f, (float16_t)0.271145160f, + (float16_t)-0.962953267f, (float16_t)0.269668326f, + (float16_t)-0.963365800f, (float16_t)0.268190857f, + (float16_t)-0.963776066f, (float16_t)0.266712757f, + (float16_t)-0.964184064f, (float16_t)0.265234030f, + (float16_t)-0.964589793f, (float16_t)0.263754679f, + (float16_t)-0.964993253f, (float16_t)0.262274707f, + (float16_t)-0.965394442f, (float16_t)0.260794118f, + (float16_t)-0.965793359f, (float16_t)0.259312915f, + (float16_t)-0.966190003f, (float16_t)0.257831102f, + (float16_t)-0.966584374f, (float16_t)0.256348682f, + (float16_t)-0.966976471f, (float16_t)0.254865660f, + (float16_t)-0.967366292f, (float16_t)0.253382037f, + (float16_t)-0.967753837f, (float16_t)0.251897818f, + (float16_t)-0.968139105f, (float16_t)0.250413007f, + (float16_t)-0.968522094f, (float16_t)0.248927606f, + (float16_t)-0.968902805f, (float16_t)0.247441619f, + (float16_t)-0.969281235f, (float16_t)0.245955050f, + (float16_t)-0.969657385f, (float16_t)0.244467903f, + (float16_t)-0.970031253f, (float16_t)0.242980180f, + (float16_t)-0.970402839f, (float16_t)0.241491885f, + (float16_t)-0.970772141f, (float16_t)0.240003022f, + (float16_t)-0.971139158f, (float16_t)0.238513595f, + (float16_t)-0.971503891f, (float16_t)0.237023606f, + (float16_t)-0.971866337f, (float16_t)0.235533059f, + (float16_t)-0.972226497f, (float16_t)0.234041959f, + (float16_t)-0.972584369f, (float16_t)0.232550307f, + (float16_t)-0.972939952f, (float16_t)0.231058108f, + (float16_t)-0.973293246f, (float16_t)0.229565366f, + (float16_t)-0.973644250f, (float16_t)0.228072083f, + (float16_t)-0.973992962f, (float16_t)0.226578264f, + (float16_t)-0.974339383f, (float16_t)0.225083911f, + (float16_t)-0.974683511f, (float16_t)0.223589029f, + (float16_t)-0.975025345f, (float16_t)0.222093621f, + (float16_t)-0.975364885f, (float16_t)0.220597690f, + (float16_t)-0.975702130f, (float16_t)0.219101240f, + (float16_t)-0.976037079f, (float16_t)0.217604275f, + (float16_t)-0.976369731f, (float16_t)0.216106797f, + (float16_t)-0.976700086f, (float16_t)0.214608811f, + (float16_t)-0.977028143f, (float16_t)0.213110320f, + (float16_t)-0.977353900f, (float16_t)0.211611327f, + (float16_t)-0.977677358f, (float16_t)0.210111837f, + (float16_t)-0.977998515f, (float16_t)0.208611852f, + (float16_t)-0.978317371f, (float16_t)0.207111376f, + (float16_t)-0.978633924f, (float16_t)0.205610413f, + (float16_t)-0.978948175f, (float16_t)0.204108966f, + (float16_t)-0.979260123f, (float16_t)0.202607039f, + (float16_t)-0.979569766f, (float16_t)0.201104635f, + (float16_t)-0.979877104f, (float16_t)0.199601758f, + (float16_t)-0.980182136f, (float16_t)0.198098411f, + (float16_t)-0.980484862f, (float16_t)0.196594598f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-0.981083391f, (float16_t)0.193585587f, + (float16_t)-0.981379193f, (float16_t)0.192080397f, + (float16_t)-0.981672686f, (float16_t)0.190574755f, + (float16_t)-0.981963869f, (float16_t)0.189068664f, + (float16_t)-0.982252741f, (float16_t)0.187562129f, + (float16_t)-0.982539302f, (float16_t)0.186055152f, + (float16_t)-0.982823551f, (float16_t)0.184547737f, + (float16_t)-0.983105487f, (float16_t)0.183039888f, + (float16_t)-0.983385110f, (float16_t)0.181531608f, + (float16_t)-0.983662419f, (float16_t)0.180022901f, + (float16_t)-0.983937413f, (float16_t)0.178513771f, + (float16_t)-0.984210092f, (float16_t)0.177004220f, + (float16_t)-0.984480455f, (float16_t)0.175494253f, + (float16_t)-0.984748502f, (float16_t)0.173983873f, + (float16_t)-0.985014231f, (float16_t)0.172473084f, + (float16_t)-0.985277642f, (float16_t)0.170961889f, + (float16_t)-0.985538735f, (float16_t)0.169450291f, + (float16_t)-0.985797509f, (float16_t)0.167938295f, + (float16_t)-0.986053963f, (float16_t)0.166425904f, + (float16_t)-0.986308097f, (float16_t)0.164913120f, + (float16_t)-0.986559910f, (float16_t)0.163399949f, + (float16_t)-0.986809402f, (float16_t)0.161886394f, + (float16_t)-0.987056571f, (float16_t)0.160372457f, + (float16_t)-0.987301418f, (float16_t)0.158858143f, + (float16_t)-0.987543942f, (float16_t)0.157343456f, + (float16_t)-0.987784142f, (float16_t)0.155828398f, + (float16_t)-0.988022017f, (float16_t)0.154312973f, + (float16_t)-0.988257568f, (float16_t)0.152797185f, + (float16_t)-0.988490793f, (float16_t)0.151281038f, + (float16_t)-0.988721692f, (float16_t)0.149764535f, + (float16_t)-0.988950265f, (float16_t)0.148247679f, + (float16_t)-0.989176510f, (float16_t)0.146730474f, + (float16_t)-0.989400428f, (float16_t)0.145212925f, + (float16_t)-0.989622017f, (float16_t)0.143695033f, + (float16_t)-0.989841278f, (float16_t)0.142176804f, + (float16_t)-0.990058210f, (float16_t)0.140658239f, + (float16_t)-0.990272812f, (float16_t)0.139139344f, + (float16_t)-0.990485084f, (float16_t)0.137620122f, + (float16_t)-0.990695025f, (float16_t)0.136100575f, + (float16_t)-0.990902635f, (float16_t)0.134580709f, + (float16_t)-0.991107914f, (float16_t)0.133060525f, + (float16_t)-0.991310860f, (float16_t)0.131540029f, + (float16_t)-0.991511473f, (float16_t)0.130019223f, + (float16_t)-0.991709754f, (float16_t)0.128498111f, + (float16_t)-0.991905700f, (float16_t)0.126976696f, + (float16_t)-0.992099313f, (float16_t)0.125454983f, + (float16_t)-0.992290591f, (float16_t)0.123932975f, + (float16_t)-0.992479535f, (float16_t)0.122410675f, + (float16_t)-0.992666142f, (float16_t)0.120888087f, + (float16_t)-0.992850414f, (float16_t)0.119365215f, + (float16_t)-0.993032350f, (float16_t)0.117842062f, + (float16_t)-0.993211949f, (float16_t)0.116318631f, + (float16_t)-0.993389211f, (float16_t)0.114794927f, + (float16_t)-0.993564136f, (float16_t)0.113270952f, + (float16_t)-0.993736722f, (float16_t)0.111746711f, + (float16_t)-0.993906970f, (float16_t)0.110222207f, + (float16_t)-0.994074879f, (float16_t)0.108697444f, + (float16_t)-0.994240449f, (float16_t)0.107172425f, + (float16_t)-0.994403680f, (float16_t)0.105647154f, + (float16_t)-0.994564571f, (float16_t)0.104121634f, + (float16_t)-0.994723121f, (float16_t)0.102595869f, + (float16_t)-0.994879331f, (float16_t)0.101069863f, + (float16_t)-0.995033199f, (float16_t)0.099543619f, + (float16_t)-0.995184727f, (float16_t)0.098017140f, + (float16_t)-0.995333912f, (float16_t)0.096490431f, + (float16_t)-0.995480755f, (float16_t)0.094963495f, + (float16_t)-0.995625256f, (float16_t)0.093436336f, + (float16_t)-0.995767414f, (float16_t)0.091908956f, + (float16_t)-0.995907229f, (float16_t)0.090381361f, + (float16_t)-0.996044701f, (float16_t)0.088853553f, + (float16_t)-0.996179829f, (float16_t)0.087325535f, + (float16_t)-0.996312612f, (float16_t)0.085797312f, + (float16_t)-0.996443051f, (float16_t)0.084268888f, + (float16_t)-0.996571146f, (float16_t)0.082740265f, + (float16_t)-0.996696895f, (float16_t)0.081211447f, + (float16_t)-0.996820299f, (float16_t)0.079682438f, + (float16_t)-0.996941358f, (float16_t)0.078153242f, + (float16_t)-0.997060070f, (float16_t)0.076623861f, + (float16_t)-0.997176437f, (float16_t)0.075094301f, + (float16_t)-0.997290457f, (float16_t)0.073564564f, + (float16_t)-0.997402130f, (float16_t)0.072034653f, + (float16_t)-0.997511456f, (float16_t)0.070504573f, + (float16_t)-0.997618435f, (float16_t)0.068974328f, + (float16_t)-0.997723067f, (float16_t)0.067443920f, + (float16_t)-0.997825350f, (float16_t)0.065913353f, + (float16_t)-0.997925286f, (float16_t)0.064382631f, + (float16_t)-0.998022874f, (float16_t)0.062851758f, + (float16_t)-0.998118113f, (float16_t)0.061320736f, + (float16_t)-0.998211003f, (float16_t)0.059789571f, + (float16_t)-0.998301545f, (float16_t)0.058258265f, + (float16_t)-0.998389737f, (float16_t)0.056726821f, + (float16_t)-0.998475581f, (float16_t)0.055195244f, + (float16_t)-0.998559074f, (float16_t)0.053663538f, + (float16_t)-0.998640218f, (float16_t)0.052131705f, + (float16_t)-0.998719012f, (float16_t)0.050599749f, + (float16_t)-0.998795456f, (float16_t)0.049067674f, + (float16_t)-0.998869550f, (float16_t)0.047535484f, + (float16_t)-0.998941293f, (float16_t)0.046003182f, + (float16_t)-0.999010686f, (float16_t)0.044470772f, + (float16_t)-0.999077728f, (float16_t)0.042938257f, + (float16_t)-0.999142419f, (float16_t)0.041405641f, + (float16_t)-0.999204759f, (float16_t)0.039872928f, + (float16_t)-0.999264747f, (float16_t)0.038340120f, + (float16_t)-0.999322385f, (float16_t)0.036807223f, + (float16_t)-0.999377670f, (float16_t)0.035274239f, + (float16_t)-0.999430605f, (float16_t)0.033741172f, + (float16_t)-0.999481187f, (float16_t)0.032208025f, + (float16_t)-0.999529418f, (float16_t)0.030674803f, + (float16_t)-0.999575296f, (float16_t)0.029141509f, + (float16_t)-0.999618822f, (float16_t)0.027608146f, + (float16_t)-0.999659997f, (float16_t)0.026074718f, + (float16_t)-0.999698819f, (float16_t)0.024541229f, + (float16_t)-0.999735288f, (float16_t)0.023007681f, + (float16_t)-0.999769405f, (float16_t)0.021474080f, + (float16_t)-0.999801170f, (float16_t)0.019940429f, + (float16_t)-0.999830582f, (float16_t)0.018406730f, + (float16_t)-0.999857641f, (float16_t)0.016872988f, + (float16_t)-0.999882347f, (float16_t)0.015339206f, + (float16_t)-0.999904701f, (float16_t)0.013805389f, + (float16_t)-0.999924702f, (float16_t)0.012271538f, + (float16_t)-0.999942350f, (float16_t)0.010737659f, + (float16_t)-0.999957645f, (float16_t)0.009203755f, + (float16_t)-0.999970586f, (float16_t)0.007669829f, + (float16_t)-0.999981175f, (float16_t)0.006135885f, + (float16_t)-0.999989411f, (float16_t)0.004601926f, + (float16_t)-0.999995294f, (float16_t)0.003067957f, + (float16_t)-0.999998823f, (float16_t)0.001533980f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.999998823f, (float16_t)-0.001533980f, + (float16_t)-0.999995294f, (float16_t)-0.003067957f, + (float16_t)-0.999989411f, (float16_t)-0.004601926f, + (float16_t)-0.999981175f, (float16_t)-0.006135885f, + (float16_t)-0.999970586f, (float16_t)-0.007669829f, + (float16_t)-0.999957645f, (float16_t)-0.009203755f, + (float16_t)-0.999942350f, (float16_t)-0.010737659f, + (float16_t)-0.999924702f, (float16_t)-0.012271538f, + (float16_t)-0.999904701f, (float16_t)-0.013805389f, + (float16_t)-0.999882347f, (float16_t)-0.015339206f, + (float16_t)-0.999857641f, (float16_t)-0.016872988f, + (float16_t)-0.999830582f, (float16_t)-0.018406730f, + (float16_t)-0.999801170f, (float16_t)-0.019940429f, + (float16_t)-0.999769405f, (float16_t)-0.021474080f, + (float16_t)-0.999735288f, (float16_t)-0.023007681f, + (float16_t)-0.999698819f, (float16_t)-0.024541229f, + (float16_t)-0.999659997f, (float16_t)-0.026074718f, + (float16_t)-0.999618822f, (float16_t)-0.027608146f, + (float16_t)-0.999575296f, (float16_t)-0.029141509f, + (float16_t)-0.999529418f, (float16_t)-0.030674803f, + (float16_t)-0.999481187f, (float16_t)-0.032208025f, + (float16_t)-0.999430605f, (float16_t)-0.033741172f, + (float16_t)-0.999377670f, (float16_t)-0.035274239f, + (float16_t)-0.999322385f, (float16_t)-0.036807223f, + (float16_t)-0.999264747f, (float16_t)-0.038340120f, + (float16_t)-0.999204759f, (float16_t)-0.039872928f, + (float16_t)-0.999142419f, (float16_t)-0.041405641f, + (float16_t)-0.999077728f, (float16_t)-0.042938257f, + (float16_t)-0.999010686f, (float16_t)-0.044470772f, + (float16_t)-0.998941293f, (float16_t)-0.046003182f, + (float16_t)-0.998869550f, (float16_t)-0.047535484f, + (float16_t)-0.998795456f, (float16_t)-0.049067674f, + (float16_t)-0.998719012f, (float16_t)-0.050599749f, + (float16_t)-0.998640218f, (float16_t)-0.052131705f, + (float16_t)-0.998559074f, (float16_t)-0.053663538f, + (float16_t)-0.998475581f, (float16_t)-0.055195244f, + (float16_t)-0.998389737f, (float16_t)-0.056726821f, + (float16_t)-0.998301545f, (float16_t)-0.058258265f, + (float16_t)-0.998211003f, (float16_t)-0.059789571f, + (float16_t)-0.998118113f, (float16_t)-0.061320736f, + (float16_t)-0.998022874f, (float16_t)-0.062851758f, + (float16_t)-0.997925286f, (float16_t)-0.064382631f, + (float16_t)-0.997825350f, (float16_t)-0.065913353f, + (float16_t)-0.997723067f, (float16_t)-0.067443920f, + (float16_t)-0.997618435f, (float16_t)-0.068974328f, + (float16_t)-0.997511456f, (float16_t)-0.070504573f, + (float16_t)-0.997402130f, (float16_t)-0.072034653f, + (float16_t)-0.997290457f, (float16_t)-0.073564564f, + (float16_t)-0.997176437f, (float16_t)-0.075094301f, + (float16_t)-0.997060070f, (float16_t)-0.076623861f, + (float16_t)-0.996941358f, (float16_t)-0.078153242f, + (float16_t)-0.996820299f, (float16_t)-0.079682438f, + (float16_t)-0.996696895f, (float16_t)-0.081211447f, + (float16_t)-0.996571146f, (float16_t)-0.082740265f, + (float16_t)-0.996443051f, (float16_t)-0.084268888f, + (float16_t)-0.996312612f, (float16_t)-0.085797312f, + (float16_t)-0.996179829f, (float16_t)-0.087325535f, + (float16_t)-0.996044701f, (float16_t)-0.088853553f, + (float16_t)-0.995907229f, (float16_t)-0.090381361f, + (float16_t)-0.995767414f, (float16_t)-0.091908956f, + (float16_t)-0.995625256f, (float16_t)-0.093436336f, + (float16_t)-0.995480755f, (float16_t)-0.094963495f, + (float16_t)-0.995333912f, (float16_t)-0.096490431f, + (float16_t)-0.995184727f, (float16_t)-0.098017140f, + (float16_t)-0.995033199f, (float16_t)-0.099543619f, + (float16_t)-0.994879331f, (float16_t)-0.101069863f, + (float16_t)-0.994723121f, (float16_t)-0.102595869f, + (float16_t)-0.994564571f, (float16_t)-0.104121634f, + (float16_t)-0.994403680f, (float16_t)-0.105647154f, + (float16_t)-0.994240449f, (float16_t)-0.107172425f, + (float16_t)-0.994074879f, (float16_t)-0.108697444f, + (float16_t)-0.993906970f, (float16_t)-0.110222207f, + (float16_t)-0.993736722f, (float16_t)-0.111746711f, + (float16_t)-0.993564136f, (float16_t)-0.113270952f, + (float16_t)-0.993389211f, (float16_t)-0.114794927f, + (float16_t)-0.993211949f, (float16_t)-0.116318631f, + (float16_t)-0.993032350f, (float16_t)-0.117842062f, + (float16_t)-0.992850414f, (float16_t)-0.119365215f, + (float16_t)-0.992666142f, (float16_t)-0.120888087f, + (float16_t)-0.992479535f, (float16_t)-0.122410675f, + (float16_t)-0.992290591f, (float16_t)-0.123932975f, + (float16_t)-0.992099313f, (float16_t)-0.125454983f, + (float16_t)-0.991905700f, (float16_t)-0.126976696f, + (float16_t)-0.991709754f, (float16_t)-0.128498111f, + (float16_t)-0.991511473f, (float16_t)-0.130019223f, + (float16_t)-0.991310860f, (float16_t)-0.131540029f, + (float16_t)-0.991107914f, (float16_t)-0.133060525f, + (float16_t)-0.990902635f, (float16_t)-0.134580709f, + (float16_t)-0.990695025f, (float16_t)-0.136100575f, + (float16_t)-0.990485084f, (float16_t)-0.137620122f, + (float16_t)-0.990272812f, (float16_t)-0.139139344f, + (float16_t)-0.990058210f, (float16_t)-0.140658239f, + (float16_t)-0.989841278f, (float16_t)-0.142176804f, + (float16_t)-0.989622017f, (float16_t)-0.143695033f, + (float16_t)-0.989400428f, (float16_t)-0.145212925f, + (float16_t)-0.989176510f, (float16_t)-0.146730474f, + (float16_t)-0.988950265f, (float16_t)-0.148247679f, + (float16_t)-0.988721692f, (float16_t)-0.149764535f, + (float16_t)-0.988490793f, (float16_t)-0.151281038f, + (float16_t)-0.988257568f, (float16_t)-0.152797185f, + (float16_t)-0.988022017f, (float16_t)-0.154312973f, + (float16_t)-0.987784142f, (float16_t)-0.155828398f, + (float16_t)-0.987543942f, (float16_t)-0.157343456f, + (float16_t)-0.987301418f, (float16_t)-0.158858143f, + (float16_t)-0.987056571f, (float16_t)-0.160372457f, + (float16_t)-0.986809402f, (float16_t)-0.161886394f, + (float16_t)-0.986559910f, (float16_t)-0.163399949f, + (float16_t)-0.986308097f, (float16_t)-0.164913120f, + (float16_t)-0.986053963f, (float16_t)-0.166425904f, + (float16_t)-0.985797509f, (float16_t)-0.167938295f, + (float16_t)-0.985538735f, (float16_t)-0.169450291f, + (float16_t)-0.985277642f, (float16_t)-0.170961889f, + (float16_t)-0.985014231f, (float16_t)-0.172473084f, + (float16_t)-0.984748502f, (float16_t)-0.173983873f, + (float16_t)-0.984480455f, (float16_t)-0.175494253f, + (float16_t)-0.984210092f, (float16_t)-0.177004220f, + (float16_t)-0.983937413f, (float16_t)-0.178513771f, + (float16_t)-0.983662419f, (float16_t)-0.180022901f, + (float16_t)-0.983385110f, (float16_t)-0.181531608f, + (float16_t)-0.983105487f, (float16_t)-0.183039888f, + (float16_t)-0.982823551f, (float16_t)-0.184547737f, + (float16_t)-0.982539302f, (float16_t)-0.186055152f, + (float16_t)-0.982252741f, (float16_t)-0.187562129f, + (float16_t)-0.981963869f, (float16_t)-0.189068664f, + (float16_t)-0.981672686f, (float16_t)-0.190574755f, + (float16_t)-0.981379193f, (float16_t)-0.192080397f, + (float16_t)-0.981083391f, (float16_t)-0.193585587f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.980484862f, (float16_t)-0.196594598f, + (float16_t)-0.980182136f, (float16_t)-0.198098411f, + (float16_t)-0.979877104f, (float16_t)-0.199601758f, + (float16_t)-0.979569766f, (float16_t)-0.201104635f, + (float16_t)-0.979260123f, (float16_t)-0.202607039f, + (float16_t)-0.978948175f, (float16_t)-0.204108966f, + (float16_t)-0.978633924f, (float16_t)-0.205610413f, + (float16_t)-0.978317371f, (float16_t)-0.207111376f, + (float16_t)-0.977998515f, (float16_t)-0.208611852f, + (float16_t)-0.977677358f, (float16_t)-0.210111837f, + (float16_t)-0.977353900f, (float16_t)-0.211611327f, + (float16_t)-0.977028143f, (float16_t)-0.213110320f, + (float16_t)-0.976700086f, (float16_t)-0.214608811f, + (float16_t)-0.976369731f, (float16_t)-0.216106797f, + (float16_t)-0.976037079f, (float16_t)-0.217604275f, + (float16_t)-0.975702130f, (float16_t)-0.219101240f, + (float16_t)-0.975364885f, (float16_t)-0.220597690f, + (float16_t)-0.975025345f, (float16_t)-0.222093621f, + (float16_t)-0.974683511f, (float16_t)-0.223589029f, + (float16_t)-0.974339383f, (float16_t)-0.225083911f, + (float16_t)-0.973992962f, (float16_t)-0.226578264f, + (float16_t)-0.973644250f, (float16_t)-0.228072083f, + (float16_t)-0.973293246f, (float16_t)-0.229565366f, + (float16_t)-0.972939952f, (float16_t)-0.231058108f, + (float16_t)-0.972584369f, (float16_t)-0.232550307f, + (float16_t)-0.972226497f, (float16_t)-0.234041959f, + (float16_t)-0.971866337f, (float16_t)-0.235533059f, + (float16_t)-0.971503891f, (float16_t)-0.237023606f, + (float16_t)-0.971139158f, (float16_t)-0.238513595f, + (float16_t)-0.970772141f, (float16_t)-0.240003022f, + (float16_t)-0.970402839f, (float16_t)-0.241491885f, + (float16_t)-0.970031253f, (float16_t)-0.242980180f, + (float16_t)-0.969657385f, (float16_t)-0.244467903f, + (float16_t)-0.969281235f, (float16_t)-0.245955050f, + (float16_t)-0.968902805f, (float16_t)-0.247441619f, + (float16_t)-0.968522094f, (float16_t)-0.248927606f, + (float16_t)-0.968139105f, (float16_t)-0.250413007f, + (float16_t)-0.967753837f, (float16_t)-0.251897818f, + (float16_t)-0.967366292f, (float16_t)-0.253382037f, + (float16_t)-0.966976471f, (float16_t)-0.254865660f, + (float16_t)-0.966584374f, (float16_t)-0.256348682f, + (float16_t)-0.966190003f, (float16_t)-0.257831102f, + (float16_t)-0.965793359f, (float16_t)-0.259312915f, + (float16_t)-0.965394442f, (float16_t)-0.260794118f, + (float16_t)-0.964993253f, (float16_t)-0.262274707f, + (float16_t)-0.964589793f, (float16_t)-0.263754679f, + (float16_t)-0.964184064f, (float16_t)-0.265234030f, + (float16_t)-0.963776066f, (float16_t)-0.266712757f, + (float16_t)-0.963365800f, (float16_t)-0.268190857f, + (float16_t)-0.962953267f, (float16_t)-0.269668326f, + (float16_t)-0.962538468f, (float16_t)-0.271145160f, + (float16_t)-0.962121404f, (float16_t)-0.272621355f, + (float16_t)-0.961702077f, (float16_t)-0.274096910f, + (float16_t)-0.961280486f, (float16_t)-0.275571819f, + (float16_t)-0.960856633f, (float16_t)-0.277046080f, + (float16_t)-0.960430519f, (float16_t)-0.278519689f, + (float16_t)-0.960002146f, (float16_t)-0.279992643f, + (float16_t)-0.959571513f, (float16_t)-0.281464938f, + (float16_t)-0.959138622f, (float16_t)-0.282936570f, + (float16_t)-0.958703475f, (float16_t)-0.284407537f, + (float16_t)-0.958266071f, (float16_t)-0.285877835f, + (float16_t)-0.957826413f, (float16_t)-0.287347460f, + (float16_t)-0.957384501f, (float16_t)-0.288816408f, + (float16_t)-0.956940336f, (float16_t)-0.290284677f, + (float16_t)-0.956493919f, (float16_t)-0.291752263f, + (float16_t)-0.956045251f, (float16_t)-0.293219163f, + (float16_t)-0.955594334f, (float16_t)-0.294685372f, + (float16_t)-0.955141168f, (float16_t)-0.296150888f, + (float16_t)-0.954685755f, (float16_t)-0.297615707f, + (float16_t)-0.954228095f, (float16_t)-0.299079826f, + (float16_t)-0.953768190f, (float16_t)-0.300543241f, + (float16_t)-0.953306040f, (float16_t)-0.302005949f, + (float16_t)-0.952841648f, (float16_t)-0.303467947f, + (float16_t)-0.952375013f, (float16_t)-0.304929230f, + (float16_t)-0.951906137f, (float16_t)-0.306389795f, + (float16_t)-0.951435021f, (float16_t)-0.307849640f, + (float16_t)-0.950961666f, (float16_t)-0.309308760f, + (float16_t)-0.950486074f, (float16_t)-0.310767153f, + (float16_t)-0.950008245f, (float16_t)-0.312224814f, + (float16_t)-0.949528181f, (float16_t)-0.313681740f, + (float16_t)-0.949045882f, (float16_t)-0.315137929f, + (float16_t)-0.948561350f, (float16_t)-0.316593376f, + (float16_t)-0.948074586f, (float16_t)-0.318048077f, + (float16_t)-0.947585591f, (float16_t)-0.319502031f, + (float16_t)-0.947094366f, (float16_t)-0.320955232f, + (float16_t)-0.946600913f, (float16_t)-0.322407679f, + (float16_t)-0.946105232f, (float16_t)-0.323859367f, + (float16_t)-0.945607325f, (float16_t)-0.325310292f, + (float16_t)-0.945107193f, (float16_t)-0.326760452f, + (float16_t)-0.944604837f, (float16_t)-0.328209844f, + (float16_t)-0.944100258f, (float16_t)-0.329658463f, + (float16_t)-0.943593458f, (float16_t)-0.331106306f, + (float16_t)-0.943084437f, (float16_t)-0.332553370f, + (float16_t)-0.942573198f, (float16_t)-0.333999651f, + (float16_t)-0.942059740f, (float16_t)-0.335445147f, + (float16_t)-0.941544065f, (float16_t)-0.336889853f, + (float16_t)-0.941026175f, (float16_t)-0.338333767f, + (float16_t)-0.940506071f, (float16_t)-0.339776884f, + (float16_t)-0.939983753f, (float16_t)-0.341219202f, + (float16_t)-0.939459224f, (float16_t)-0.342660717f, + (float16_t)-0.938932484f, (float16_t)-0.344101426f, + (float16_t)-0.938403534f, (float16_t)-0.345541325f, + (float16_t)-0.937872376f, (float16_t)-0.346980411f, + (float16_t)-0.937339012f, (float16_t)-0.348418680f, + (float16_t)-0.936803442f, (float16_t)-0.349856130f, + (float16_t)-0.936265667f, (float16_t)-0.351292756f, + (float16_t)-0.935725689f, (float16_t)-0.352728556f, + (float16_t)-0.935183510f, (float16_t)-0.354163525f, + (float16_t)-0.934639130f, (float16_t)-0.355597662f, + (float16_t)-0.934092550f, (float16_t)-0.357030961f, + (float16_t)-0.933543773f, (float16_t)-0.358463421f, + (float16_t)-0.932992799f, (float16_t)-0.359895037f, + (float16_t)-0.932439629f, (float16_t)-0.361325806f, + (float16_t)-0.931884266f, (float16_t)-0.362755724f, + (float16_t)-0.931326709f, (float16_t)-0.364184790f, + (float16_t)-0.930766961f, (float16_t)-0.365612998f, + (float16_t)-0.930205023f, (float16_t)-0.367040346f, + (float16_t)-0.929640896f, (float16_t)-0.368466830f, + (float16_t)-0.929074581f, (float16_t)-0.369892447f, + (float16_t)-0.928506080f, (float16_t)-0.371317194f, + (float16_t)-0.927935395f, (float16_t)-0.372741067f, + (float16_t)-0.927362526f, (float16_t)-0.374164063f, + (float16_t)-0.926787474f, (float16_t)-0.375586178f, + (float16_t)-0.926210242f, (float16_t)-0.377007410f, + (float16_t)-0.925630831f, (float16_t)-0.378427755f, + (float16_t)-0.925049241f, (float16_t)-0.379847209f, + (float16_t)-0.924465474f, (float16_t)-0.381265769f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.923291417f, (float16_t)-0.384100195f, + (float16_t)-0.922701128f, (float16_t)-0.385516054f, + (float16_t)-0.922108669f, (float16_t)-0.386931006f, + (float16_t)-0.921514039f, (float16_t)-0.388345047f, + (float16_t)-0.920917242f, (float16_t)-0.389758174f, + (float16_t)-0.920318277f, (float16_t)-0.391170384f, + (float16_t)-0.919717146f, (float16_t)-0.392581674f, + (float16_t)-0.919113852f, (float16_t)-0.393992040f, + (float16_t)-0.918508394f, (float16_t)-0.395401479f, + (float16_t)-0.917900776f, (float16_t)-0.396809987f, + (float16_t)-0.917290997f, (float16_t)-0.398217562f, + (float16_t)-0.916679060f, (float16_t)-0.399624200f, + (float16_t)-0.916064966f, (float16_t)-0.401029897f, + (float16_t)-0.915448716f, (float16_t)-0.402434651f, + (float16_t)-0.914830312f, (float16_t)-0.403838458f, + (float16_t)-0.914209756f, (float16_t)-0.405241314f, + (float16_t)-0.913587048f, (float16_t)-0.406643217f, + (float16_t)-0.912962190f, (float16_t)-0.408044163f, + (float16_t)-0.912335185f, (float16_t)-0.409444149f, + (float16_t)-0.911706032f, (float16_t)-0.410843171f, + (float16_t)-0.911074734f, (float16_t)-0.412241227f, + (float16_t)-0.910441292f, (float16_t)-0.413638312f, + (float16_t)-0.909805708f, (float16_t)-0.415034424f, + (float16_t)-0.909167983f, (float16_t)-0.416429560f, + (float16_t)-0.908528119f, (float16_t)-0.417823716f, + (float16_t)-0.907886116f, (float16_t)-0.419216888f, + (float16_t)-0.907241978f, (float16_t)-0.420609074f, + (float16_t)-0.906595705f, (float16_t)-0.422000271f, + (float16_t)-0.905947298f, (float16_t)-0.423390474f, + (float16_t)-0.905296759f, (float16_t)-0.424779681f, + (float16_t)-0.904644091f, (float16_t)-0.426167889f, + (float16_t)-0.903989293f, (float16_t)-0.427555093f, + (float16_t)-0.903332368f, (float16_t)-0.428941292f, + (float16_t)-0.902673318f, (float16_t)-0.430326481f, + (float16_t)-0.902012144f, (float16_t)-0.431710658f, + (float16_t)-0.901348847f, (float16_t)-0.433093819f, + (float16_t)-0.900683429f, (float16_t)-0.434475961f, + (float16_t)-0.900015892f, (float16_t)-0.435857080f, + (float16_t)-0.899346237f, (float16_t)-0.437237174f, + (float16_t)-0.898674466f, (float16_t)-0.438616239f, + (float16_t)-0.898000580f, (float16_t)-0.439994271f, + (float16_t)-0.897324581f, (float16_t)-0.441371269f, + (float16_t)-0.896646470f, (float16_t)-0.442747228f, + (float16_t)-0.895966250f, (float16_t)-0.444122145f, + (float16_t)-0.895283921f, (float16_t)-0.445496017f, + (float16_t)-0.894599486f, (float16_t)-0.446868840f, + (float16_t)-0.893912945f, (float16_t)-0.448240612f, + (float16_t)-0.893224301f, (float16_t)-0.449611330f, + (float16_t)-0.892533555f, (float16_t)-0.450980989f, + (float16_t)-0.891840709f, (float16_t)-0.452349587f, + (float16_t)-0.891145765f, (float16_t)-0.453717121f, + (float16_t)-0.890448723f, (float16_t)-0.455083587f, + (float16_t)-0.889749586f, (float16_t)-0.456448982f, + (float16_t)-0.889048356f, (float16_t)-0.457813304f, + (float16_t)-0.888345033f, (float16_t)-0.459176548f, + (float16_t)-0.887639620f, (float16_t)-0.460538711f, + (float16_t)-0.886932119f, (float16_t)-0.461899791f, + (float16_t)-0.886222530f, (float16_t)-0.463259784f, + (float16_t)-0.885510856f, (float16_t)-0.464618686f, + (float16_t)-0.884797098f, (float16_t)-0.465976496f, + (float16_t)-0.884081259f, (float16_t)-0.467333209f, + (float16_t)-0.883363339f, (float16_t)-0.468688822f, + (float16_t)-0.882643340f, (float16_t)-0.470043332f, + (float16_t)-0.881921264f, (float16_t)-0.471396737f, + (float16_t)-0.881197113f, (float16_t)-0.472749032f, + (float16_t)-0.880470889f, (float16_t)-0.474100215f, + (float16_t)-0.879742593f, (float16_t)-0.475450282f, + (float16_t)-0.879012226f, (float16_t)-0.476799230f, + (float16_t)-0.878279792f, (float16_t)-0.478147056f, + (float16_t)-0.877545290f, (float16_t)-0.479493758f, + (float16_t)-0.876808724f, (float16_t)-0.480839331f, + (float16_t)-0.876070094f, (float16_t)-0.482183772f, + (float16_t)-0.875329403f, (float16_t)-0.483527079f, + (float16_t)-0.874586652f, (float16_t)-0.484869248f, + (float16_t)-0.873841843f, (float16_t)-0.486210276f, + (float16_t)-0.873094978f, (float16_t)-0.487550160f, + (float16_t)-0.872346059f, (float16_t)-0.488888897f, + (float16_t)-0.871595087f, (float16_t)-0.490226483f, + (float16_t)-0.870842063f, (float16_t)-0.491562916f, + (float16_t)-0.870086991f, (float16_t)-0.492898192f, + (float16_t)-0.869329871f, (float16_t)-0.494232309f, + (float16_t)-0.868570706f, (float16_t)-0.495565262f, + (float16_t)-0.867809497f, (float16_t)-0.496897049f, + (float16_t)-0.867046246f, (float16_t)-0.498227667f, + (float16_t)-0.866280954f, (float16_t)-0.499557113f, + (float16_t)-0.865513624f, (float16_t)-0.500885383f, + (float16_t)-0.864744258f, (float16_t)-0.502212474f, + (float16_t)-0.863972856f, (float16_t)-0.503538384f, + (float16_t)-0.863199422f, (float16_t)-0.504863109f, + (float16_t)-0.862423956f, (float16_t)-0.506186645f, + (float16_t)-0.861646461f, (float16_t)-0.507508991f, + (float16_t)-0.860866939f, (float16_t)-0.508830143f, + (float16_t)-0.860085390f, (float16_t)-0.510150097f, + (float16_t)-0.859301818f, (float16_t)-0.511468850f, + (float16_t)-0.858516224f, (float16_t)-0.512786401f, + (float16_t)-0.857728610f, (float16_t)-0.514102744f, + (float16_t)-0.856938977f, (float16_t)-0.515417878f, + (float16_t)-0.856147328f, (float16_t)-0.516731799f, + (float16_t)-0.855353665f, (float16_t)-0.518044504f, + (float16_t)-0.854557988f, (float16_t)-0.519355990f, + (float16_t)-0.853760301f, (float16_t)-0.520666254f, + (float16_t)-0.852960605f, (float16_t)-0.521975293f, + (float16_t)-0.852158902f, (float16_t)-0.523283103f, + (float16_t)-0.851355193f, (float16_t)-0.524589683f, + (float16_t)-0.850549481f, (float16_t)-0.525895027f, + (float16_t)-0.849741768f, (float16_t)-0.527199135f, + (float16_t)-0.848932055f, (float16_t)-0.528502002f, + (float16_t)-0.848120345f, (float16_t)-0.529803625f, + (float16_t)-0.847306639f, (float16_t)-0.531104001f, + (float16_t)-0.846490939f, (float16_t)-0.532403128f, + (float16_t)-0.845673247f, (float16_t)-0.533701002f, + (float16_t)-0.844853565f, (float16_t)-0.534997620f, + (float16_t)-0.844031895f, (float16_t)-0.536292979f, + (float16_t)-0.843208240f, (float16_t)-0.537587076f, + (float16_t)-0.842382600f, (float16_t)-0.538879909f, + (float16_t)-0.841554977f, (float16_t)-0.540171473f, + (float16_t)-0.840725375f, (float16_t)-0.541461766f, + (float16_t)-0.839893794f, (float16_t)-0.542750785f, + (float16_t)-0.839060237f, (float16_t)-0.544038527f, + (float16_t)-0.838224706f, (float16_t)-0.545324988f, + (float16_t)-0.837387202f, (float16_t)-0.546610167f, + (float16_t)-0.836547727f, (float16_t)-0.547894059f, + (float16_t)-0.835706284f, (float16_t)-0.549176662f, + (float16_t)-0.834862875f, (float16_t)-0.550457973f, + (float16_t)-0.834017501f, (float16_t)-0.551737988f, + (float16_t)-0.833170165f, (float16_t)-0.553016706f, + (float16_t)-0.832320868f, (float16_t)-0.554294121f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.830616400f, (float16_t)-0.556845037f, + (float16_t)-0.829761234f, (float16_t)-0.558118531f, + (float16_t)-0.828904115f, (float16_t)-0.559390712f, + (float16_t)-0.828045045f, (float16_t)-0.560661576f, + (float16_t)-0.827184027f, (float16_t)-0.561931121f, + (float16_t)-0.826321063f, (float16_t)-0.563199344f, + (float16_t)-0.825456154f, (float16_t)-0.564466242f, + (float16_t)-0.824589303f, (float16_t)-0.565731811f, + (float16_t)-0.823720511f, (float16_t)-0.566996049f, + (float16_t)-0.822849781f, (float16_t)-0.568258953f, + (float16_t)-0.821977115f, (float16_t)-0.569520519f, + (float16_t)-0.821102515f, (float16_t)-0.570780746f, + (float16_t)-0.820225983f, (float16_t)-0.572039629f, + (float16_t)-0.819347520f, (float16_t)-0.573297167f, + (float16_t)-0.818467130f, (float16_t)-0.574553355f, + (float16_t)-0.817584813f, (float16_t)-0.575808191f, + (float16_t)-0.816700573f, (float16_t)-0.577061673f, + (float16_t)-0.815814411f, (float16_t)-0.578313796f, + (float16_t)-0.814926329f, (float16_t)-0.579564559f, + (float16_t)-0.814036330f, (float16_t)-0.580813958f, + (float16_t)-0.813144415f, (float16_t)-0.582061990f, + (float16_t)-0.812250587f, (float16_t)-0.583308653f, + (float16_t)-0.811354847f, (float16_t)-0.584553943f, + (float16_t)-0.810457198f, (float16_t)-0.585797857f, + (float16_t)-0.809557642f, (float16_t)-0.587040394f, + (float16_t)-0.808656182f, (float16_t)-0.588281548f, + (float16_t)-0.807752818f, (float16_t)-0.589521319f, + (float16_t)-0.806847554f, (float16_t)-0.590759702f, + (float16_t)-0.805940391f, (float16_t)-0.591996695f, + (float16_t)-0.805031331f, (float16_t)-0.593232295f, + (float16_t)-0.804120377f, (float16_t)-0.594466499f, + (float16_t)-0.803207531f, (float16_t)-0.595699304f, + (float16_t)-0.802292796f, (float16_t)-0.596930708f, + (float16_t)-0.801376172f, (float16_t)-0.598160707f, + (float16_t)-0.800457662f, (float16_t)-0.599389298f, + (float16_t)-0.799537269f, (float16_t)-0.600616479f, + (float16_t)-0.798614995f, (float16_t)-0.601842247f, + (float16_t)-0.797690841f, (float16_t)-0.603066599f, + (float16_t)-0.796764810f, (float16_t)-0.604289531f, + (float16_t)-0.795836905f, (float16_t)-0.605511041f, + (float16_t)-0.794907126f, (float16_t)-0.606731127f, + (float16_t)-0.793975478f, (float16_t)-0.607949785f, + (float16_t)-0.793041960f, (float16_t)-0.609167012f, + (float16_t)-0.792106577f, (float16_t)-0.610382806f, + (float16_t)-0.791169330f, (float16_t)-0.611597164f, + (float16_t)-0.790230221f, (float16_t)-0.612810082f, + (float16_t)-0.789289253f, (float16_t)-0.614021559f, + (float16_t)-0.788346428f, (float16_t)-0.615231591f, + (float16_t)-0.787401747f, (float16_t)-0.616440175f, + (float16_t)-0.786455214f, (float16_t)-0.617647308f, + (float16_t)-0.785506830f, (float16_t)-0.618852988f, + (float16_t)-0.784556597f, (float16_t)-0.620057212f, + (float16_t)-0.783604519f, (float16_t)-0.621259977f, + (float16_t)-0.782650596f, (float16_t)-0.622461279f, + (float16_t)-0.781694832f, (float16_t)-0.623661118f, + (float16_t)-0.780737229f, (float16_t)-0.624859488f, + (float16_t)-0.779777788f, (float16_t)-0.626056388f, + (float16_t)-0.778816512f, (float16_t)-0.627251815f, + (float16_t)-0.777853404f, (float16_t)-0.628445767f, + (float16_t)-0.776888466f, (float16_t)-0.629638239f, + (float16_t)-0.775921699f, (float16_t)-0.630829230f, + (float16_t)-0.774953107f, (float16_t)-0.632018736f, + (float16_t)-0.773982691f, (float16_t)-0.633206755f, + (float16_t)-0.773010453f, (float16_t)-0.634393284f, + (float16_t)-0.772036397f, (float16_t)-0.635578320f, + (float16_t)-0.771060524f, (float16_t)-0.636761861f, + (float16_t)-0.770082837f, (float16_t)-0.637943904f, + (float16_t)-0.769103338f, (float16_t)-0.639124445f, + (float16_t)-0.768122029f, (float16_t)-0.640303482f, + (float16_t)-0.767138912f, (float16_t)-0.641481013f, + (float16_t)-0.766153990f, (float16_t)-0.642657034f, + (float16_t)-0.765167266f, (float16_t)-0.643831543f, + (float16_t)-0.764178741f, (float16_t)-0.645004537f, + (float16_t)-0.763188417f, (float16_t)-0.646176013f, + (float16_t)-0.762196298f, (float16_t)-0.647345969f, + (float16_t)-0.761202385f, (float16_t)-0.648514401f, + (float16_t)-0.760206682f, (float16_t)-0.649681307f, + (float16_t)-0.759209189f, (float16_t)-0.650846685f, + (float16_t)-0.758209910f, (float16_t)-0.652010531f, + (float16_t)-0.757208847f, (float16_t)-0.653172843f, + (float16_t)-0.756206001f, (float16_t)-0.654333618f, + (float16_t)-0.755201377f, (float16_t)-0.655492853f, + (float16_t)-0.754194975f, (float16_t)-0.656650546f, + (float16_t)-0.753186799f, (float16_t)-0.657806693f, + (float16_t)-0.752176850f, (float16_t)-0.658961293f, + (float16_t)-0.751165132f, (float16_t)-0.660114342f, + (float16_t)-0.750151646f, (float16_t)-0.661265838f, + (float16_t)-0.749136395f, (float16_t)-0.662415778f, + (float16_t)-0.748119380f, (float16_t)-0.663564159f, + (float16_t)-0.747100606f, (float16_t)-0.664710978f, + (float16_t)-0.746080074f, (float16_t)-0.665856234f, + (float16_t)-0.745057785f, (float16_t)-0.666999922f, + (float16_t)-0.744033744f, (float16_t)-0.668142041f, + (float16_t)-0.743007952f, (float16_t)-0.669282588f, + (float16_t)-0.741980412f, (float16_t)-0.670421560f, + (float16_t)-0.740951125f, (float16_t)-0.671558955f, + (float16_t)-0.739920095f, (float16_t)-0.672694769f, + (float16_t)-0.738887324f, (float16_t)-0.673829000f, + (float16_t)-0.737852815f, (float16_t)-0.674961646f, + (float16_t)-0.736816569f, (float16_t)-0.676092704f, + (float16_t)-0.735778589f, (float16_t)-0.677222170f, + (float16_t)-0.734738878f, (float16_t)-0.678350043f, + (float16_t)-0.733697438f, (float16_t)-0.679476320f, + (float16_t)-0.732654272f, (float16_t)-0.680600998f, + (float16_t)-0.731609381f, (float16_t)-0.681724074f, + (float16_t)-0.730562769f, (float16_t)-0.682845546f, + (float16_t)-0.729514438f, (float16_t)-0.683965412f, + (float16_t)-0.728464390f, (float16_t)-0.685083668f, + (float16_t)-0.727412629f, (float16_t)-0.686200312f, + (float16_t)-0.726359155f, (float16_t)-0.687315341f, + (float16_t)-0.725303972f, (float16_t)-0.688428753f, + (float16_t)-0.724247083f, (float16_t)-0.689540545f, + (float16_t)-0.723188489f, (float16_t)-0.690650714f, + (float16_t)-0.722128194f, (float16_t)-0.691759258f, + (float16_t)-0.721066199f, (float16_t)-0.692866175f, + (float16_t)-0.720002508f, (float16_t)-0.693971461f, + (float16_t)-0.718937122f, (float16_t)-0.695075114f, + (float16_t)-0.717870045f, (float16_t)-0.696177131f, + (float16_t)-0.716801279f, (float16_t)-0.697277511f, + (float16_t)-0.715730825f, (float16_t)-0.698376249f, + (float16_t)-0.714658688f, (float16_t)-0.699473345f, + (float16_t)-0.713584869f, (float16_t)-0.700568794f, + (float16_t)-0.712509371f, (float16_t)-0.701662595f, + (float16_t)-0.711432196f, (float16_t)-0.702754744f, + (float16_t)-0.710353347f, (float16_t)-0.703845241f, + (float16_t)-0.709272826f, (float16_t)-0.704934080f, + (float16_t)-0.708190637f, (float16_t)-0.706021261f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.706021261f, (float16_t)-0.708190637f, + (float16_t)-0.704934080f, (float16_t)-0.709272826f, + (float16_t)-0.703845241f, (float16_t)-0.710353347f, + (float16_t)-0.702754744f, (float16_t)-0.711432196f, + (float16_t)-0.701662595f, (float16_t)-0.712509371f, + (float16_t)-0.700568794f, (float16_t)-0.713584869f, + (float16_t)-0.699473345f, (float16_t)-0.714658688f, + (float16_t)-0.698376249f, (float16_t)-0.715730825f, + (float16_t)-0.697277511f, (float16_t)-0.716801279f, + (float16_t)-0.696177131f, (float16_t)-0.717870045f, + (float16_t)-0.695075114f, (float16_t)-0.718937122f, + (float16_t)-0.693971461f, (float16_t)-0.720002508f, + (float16_t)-0.692866175f, (float16_t)-0.721066199f, + (float16_t)-0.691759258f, (float16_t)-0.722128194f, + (float16_t)-0.690650714f, (float16_t)-0.723188489f, + (float16_t)-0.689540545f, (float16_t)-0.724247083f, + (float16_t)-0.688428753f, (float16_t)-0.725303972f, + (float16_t)-0.687315341f, (float16_t)-0.726359155f, + (float16_t)-0.686200312f, (float16_t)-0.727412629f, + (float16_t)-0.685083668f, (float16_t)-0.728464390f, + (float16_t)-0.683965412f, (float16_t)-0.729514438f, + (float16_t)-0.682845546f, (float16_t)-0.730562769f, + (float16_t)-0.681724074f, (float16_t)-0.731609381f, + (float16_t)-0.680600998f, (float16_t)-0.732654272f, + (float16_t)-0.679476320f, (float16_t)-0.733697438f, + (float16_t)-0.678350043f, (float16_t)-0.734738878f, + (float16_t)-0.677222170f, (float16_t)-0.735778589f, + (float16_t)-0.676092704f, (float16_t)-0.736816569f, + (float16_t)-0.674961646f, (float16_t)-0.737852815f, + (float16_t)-0.673829000f, (float16_t)-0.738887324f, + (float16_t)-0.672694769f, (float16_t)-0.739920095f, + (float16_t)-0.671558955f, (float16_t)-0.740951125f, + (float16_t)-0.670421560f, (float16_t)-0.741980412f, + (float16_t)-0.669282588f, (float16_t)-0.743007952f, + (float16_t)-0.668142041f, (float16_t)-0.744033744f, + (float16_t)-0.666999922f, (float16_t)-0.745057785f, + (float16_t)-0.665856234f, (float16_t)-0.746080074f, + (float16_t)-0.664710978f, (float16_t)-0.747100606f, + (float16_t)-0.663564159f, (float16_t)-0.748119380f, + (float16_t)-0.662415778f, (float16_t)-0.749136395f, + (float16_t)-0.661265838f, (float16_t)-0.750151646f, + (float16_t)-0.660114342f, (float16_t)-0.751165132f, + (float16_t)-0.658961293f, (float16_t)-0.752176850f, + (float16_t)-0.657806693f, (float16_t)-0.753186799f, + (float16_t)-0.656650546f, (float16_t)-0.754194975f, + (float16_t)-0.655492853f, (float16_t)-0.755201377f, + (float16_t)-0.654333618f, (float16_t)-0.756206001f, + (float16_t)-0.653172843f, (float16_t)-0.757208847f, + (float16_t)-0.652010531f, (float16_t)-0.758209910f, + (float16_t)-0.650846685f, (float16_t)-0.759209189f, + (float16_t)-0.649681307f, (float16_t)-0.760206682f, + (float16_t)-0.648514401f, (float16_t)-0.761202385f, + (float16_t)-0.647345969f, (float16_t)-0.762196298f, + (float16_t)-0.646176013f, (float16_t)-0.763188417f, + (float16_t)-0.645004537f, (float16_t)-0.764178741f, + (float16_t)-0.643831543f, (float16_t)-0.765167266f, + (float16_t)-0.642657034f, (float16_t)-0.766153990f, + (float16_t)-0.641481013f, (float16_t)-0.767138912f, + (float16_t)-0.640303482f, (float16_t)-0.768122029f, + (float16_t)-0.639124445f, (float16_t)-0.769103338f, + (float16_t)-0.637943904f, (float16_t)-0.770082837f, + (float16_t)-0.636761861f, (float16_t)-0.771060524f, + (float16_t)-0.635578320f, (float16_t)-0.772036397f, + (float16_t)-0.634393284f, (float16_t)-0.773010453f, + (float16_t)-0.633206755f, (float16_t)-0.773982691f, + (float16_t)-0.632018736f, (float16_t)-0.774953107f, + (float16_t)-0.630829230f, (float16_t)-0.775921699f, + (float16_t)-0.629638239f, (float16_t)-0.776888466f, + (float16_t)-0.628445767f, (float16_t)-0.777853404f, + (float16_t)-0.627251815f, (float16_t)-0.778816512f, + (float16_t)-0.626056388f, (float16_t)-0.779777788f, + (float16_t)-0.624859488f, (float16_t)-0.780737229f, + (float16_t)-0.623661118f, (float16_t)-0.781694832f, + (float16_t)-0.622461279f, (float16_t)-0.782650596f, + (float16_t)-0.621259977f, (float16_t)-0.783604519f, + (float16_t)-0.620057212f, (float16_t)-0.784556597f, + (float16_t)-0.618852988f, (float16_t)-0.785506830f, + (float16_t)-0.617647308f, (float16_t)-0.786455214f, + (float16_t)-0.616440175f, (float16_t)-0.787401747f, + (float16_t)-0.615231591f, (float16_t)-0.788346428f, + (float16_t)-0.614021559f, (float16_t)-0.789289253f, + (float16_t)-0.612810082f, (float16_t)-0.790230221f, + (float16_t)-0.611597164f, (float16_t)-0.791169330f, + (float16_t)-0.610382806f, (float16_t)-0.792106577f, + (float16_t)-0.609167012f, (float16_t)-0.793041960f, + (float16_t)-0.607949785f, (float16_t)-0.793975478f, + (float16_t)-0.606731127f, (float16_t)-0.794907126f, + (float16_t)-0.605511041f, (float16_t)-0.795836905f, + (float16_t)-0.604289531f, (float16_t)-0.796764810f, + (float16_t)-0.603066599f, (float16_t)-0.797690841f, + (float16_t)-0.601842247f, (float16_t)-0.798614995f, + (float16_t)-0.600616479f, (float16_t)-0.799537269f, + (float16_t)-0.599389298f, (float16_t)-0.800457662f, + (float16_t)-0.598160707f, (float16_t)-0.801376172f, + (float16_t)-0.596930708f, (float16_t)-0.802292796f, + (float16_t)-0.595699304f, (float16_t)-0.803207531f, + (float16_t)-0.594466499f, (float16_t)-0.804120377f, + (float16_t)-0.593232295f, (float16_t)-0.805031331f, + (float16_t)-0.591996695f, (float16_t)-0.805940391f, + (float16_t)-0.590759702f, (float16_t)-0.806847554f, + (float16_t)-0.589521319f, (float16_t)-0.807752818f, + (float16_t)-0.588281548f, (float16_t)-0.808656182f, + (float16_t)-0.587040394f, (float16_t)-0.809557642f, + (float16_t)-0.585797857f, (float16_t)-0.810457198f, + (float16_t)-0.584553943f, (float16_t)-0.811354847f, + (float16_t)-0.583308653f, (float16_t)-0.812250587f, + (float16_t)-0.582061990f, (float16_t)-0.813144415f, + (float16_t)-0.580813958f, (float16_t)-0.814036330f, + (float16_t)-0.579564559f, (float16_t)-0.814926329f, + (float16_t)-0.578313796f, (float16_t)-0.815814411f, + (float16_t)-0.577061673f, (float16_t)-0.816700573f, + (float16_t)-0.575808191f, (float16_t)-0.817584813f, + (float16_t)-0.574553355f, (float16_t)-0.818467130f, + (float16_t)-0.573297167f, (float16_t)-0.819347520f, + (float16_t)-0.572039629f, (float16_t)-0.820225983f, + (float16_t)-0.570780746f, (float16_t)-0.821102515f, + (float16_t)-0.569520519f, (float16_t)-0.821977115f, + (float16_t)-0.568258953f, (float16_t)-0.822849781f, + (float16_t)-0.566996049f, (float16_t)-0.823720511f, + (float16_t)-0.565731811f, (float16_t)-0.824589303f, + (float16_t)-0.564466242f, (float16_t)-0.825456154f, + (float16_t)-0.563199344f, (float16_t)-0.826321063f, + (float16_t)-0.561931121f, (float16_t)-0.827184027f, + (float16_t)-0.560661576f, (float16_t)-0.828045045f, + (float16_t)-0.559390712f, (float16_t)-0.828904115f, + (float16_t)-0.558118531f, (float16_t)-0.829761234f, + (float16_t)-0.556845037f, (float16_t)-0.830616400f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.554294121f, (float16_t)-0.832320868f, + (float16_t)-0.553016706f, (float16_t)-0.833170165f, + (float16_t)-0.551737988f, (float16_t)-0.834017501f, + (float16_t)-0.550457973f, (float16_t)-0.834862875f, + (float16_t)-0.549176662f, (float16_t)-0.835706284f, + (float16_t)-0.547894059f, (float16_t)-0.836547727f, + (float16_t)-0.546610167f, (float16_t)-0.837387202f, + (float16_t)-0.545324988f, (float16_t)-0.838224706f, + (float16_t)-0.544038527f, (float16_t)-0.839060237f, + (float16_t)-0.542750785f, (float16_t)-0.839893794f, + (float16_t)-0.541461766f, (float16_t)-0.840725375f, + (float16_t)-0.540171473f, (float16_t)-0.841554977f, + (float16_t)-0.538879909f, (float16_t)-0.842382600f, + (float16_t)-0.537587076f, (float16_t)-0.843208240f, + (float16_t)-0.536292979f, (float16_t)-0.844031895f, + (float16_t)-0.534997620f, (float16_t)-0.844853565f, + (float16_t)-0.533701002f, (float16_t)-0.845673247f, + (float16_t)-0.532403128f, (float16_t)-0.846490939f, + (float16_t)-0.531104001f, (float16_t)-0.847306639f, + (float16_t)-0.529803625f, (float16_t)-0.848120345f, + (float16_t)-0.528502002f, (float16_t)-0.848932055f, + (float16_t)-0.527199135f, (float16_t)-0.849741768f, + (float16_t)-0.525895027f, (float16_t)-0.850549481f, + (float16_t)-0.524589683f, (float16_t)-0.851355193f, + (float16_t)-0.523283103f, (float16_t)-0.852158902f, + (float16_t)-0.521975293f, (float16_t)-0.852960605f, + (float16_t)-0.520666254f, (float16_t)-0.853760301f, + (float16_t)-0.519355990f, (float16_t)-0.854557988f, + (float16_t)-0.518044504f, (float16_t)-0.855353665f, + (float16_t)-0.516731799f, (float16_t)-0.856147328f, + (float16_t)-0.515417878f, (float16_t)-0.856938977f, + (float16_t)-0.514102744f, (float16_t)-0.857728610f, + (float16_t)-0.512786401f, (float16_t)-0.858516224f, + (float16_t)-0.511468850f, (float16_t)-0.859301818f, + (float16_t)-0.510150097f, (float16_t)-0.860085390f, + (float16_t)-0.508830143f, (float16_t)-0.860866939f, + (float16_t)-0.507508991f, (float16_t)-0.861646461f, + (float16_t)-0.506186645f, (float16_t)-0.862423956f, + (float16_t)-0.504863109f, (float16_t)-0.863199422f, + (float16_t)-0.503538384f, (float16_t)-0.863972856f, + (float16_t)-0.502212474f, (float16_t)-0.864744258f, + (float16_t)-0.500885383f, (float16_t)-0.865513624f, + (float16_t)-0.499557113f, (float16_t)-0.866280954f, + (float16_t)-0.498227667f, (float16_t)-0.867046246f, + (float16_t)-0.496897049f, (float16_t)-0.867809497f, + (float16_t)-0.495565262f, (float16_t)-0.868570706f, + (float16_t)-0.494232309f, (float16_t)-0.869329871f, + (float16_t)-0.492898192f, (float16_t)-0.870086991f, + (float16_t)-0.491562916f, (float16_t)-0.870842063f, + (float16_t)-0.490226483f, (float16_t)-0.871595087f, + (float16_t)-0.488888897f, (float16_t)-0.872346059f, + (float16_t)-0.487550160f, (float16_t)-0.873094978f, + (float16_t)-0.486210276f, (float16_t)-0.873841843f, + (float16_t)-0.484869248f, (float16_t)-0.874586652f, + (float16_t)-0.483527079f, (float16_t)-0.875329403f, + (float16_t)-0.482183772f, (float16_t)-0.876070094f, + (float16_t)-0.480839331f, (float16_t)-0.876808724f, + (float16_t)-0.479493758f, (float16_t)-0.877545290f, + (float16_t)-0.478147056f, (float16_t)-0.878279792f, + (float16_t)-0.476799230f, (float16_t)-0.879012226f, + (float16_t)-0.475450282f, (float16_t)-0.879742593f, + (float16_t)-0.474100215f, (float16_t)-0.880470889f, + (float16_t)-0.472749032f, (float16_t)-0.881197113f, + (float16_t)-0.471396737f, (float16_t)-0.881921264f, + (float16_t)-0.470043332f, (float16_t)-0.882643340f, + (float16_t)-0.468688822f, (float16_t)-0.883363339f, + (float16_t)-0.467333209f, (float16_t)-0.884081259f, + (float16_t)-0.465976496f, (float16_t)-0.884797098f, + (float16_t)-0.464618686f, (float16_t)-0.885510856f, + (float16_t)-0.463259784f, (float16_t)-0.886222530f, + (float16_t)-0.461899791f, (float16_t)-0.886932119f, + (float16_t)-0.460538711f, (float16_t)-0.887639620f, + (float16_t)-0.459176548f, (float16_t)-0.888345033f, + (float16_t)-0.457813304f, (float16_t)-0.889048356f, + (float16_t)-0.456448982f, (float16_t)-0.889749586f, + (float16_t)-0.455083587f, (float16_t)-0.890448723f, + (float16_t)-0.453717121f, (float16_t)-0.891145765f, + (float16_t)-0.452349587f, (float16_t)-0.891840709f, + (float16_t)-0.450980989f, (float16_t)-0.892533555f, + (float16_t)-0.449611330f, (float16_t)-0.893224301f, + (float16_t)-0.448240612f, (float16_t)-0.893912945f, + (float16_t)-0.446868840f, (float16_t)-0.894599486f, + (float16_t)-0.445496017f, (float16_t)-0.895283921f, + (float16_t)-0.444122145f, (float16_t)-0.895966250f, + (float16_t)-0.442747228f, (float16_t)-0.896646470f, + (float16_t)-0.441371269f, (float16_t)-0.897324581f, + (float16_t)-0.439994271f, (float16_t)-0.898000580f, + (float16_t)-0.438616239f, (float16_t)-0.898674466f, + (float16_t)-0.437237174f, (float16_t)-0.899346237f, + (float16_t)-0.435857080f, (float16_t)-0.900015892f, + (float16_t)-0.434475961f, (float16_t)-0.900683429f, + (float16_t)-0.433093819f, (float16_t)-0.901348847f, + (float16_t)-0.431710658f, (float16_t)-0.902012144f, + (float16_t)-0.430326481f, (float16_t)-0.902673318f, + (float16_t)-0.428941292f, (float16_t)-0.903332368f, + (float16_t)-0.427555093f, (float16_t)-0.903989293f, + (float16_t)-0.426167889f, (float16_t)-0.904644091f, + (float16_t)-0.424779681f, (float16_t)-0.905296759f, + (float16_t)-0.423390474f, (float16_t)-0.905947298f, + (float16_t)-0.422000271f, (float16_t)-0.906595705f, + (float16_t)-0.420609074f, (float16_t)-0.907241978f, + (float16_t)-0.419216888f, (float16_t)-0.907886116f, + (float16_t)-0.417823716f, (float16_t)-0.908528119f, + (float16_t)-0.416429560f, (float16_t)-0.909167983f, + (float16_t)-0.415034424f, (float16_t)-0.909805708f, + (float16_t)-0.413638312f, (float16_t)-0.910441292f, + (float16_t)-0.412241227f, (float16_t)-0.911074734f, + (float16_t)-0.410843171f, (float16_t)-0.911706032f, + (float16_t)-0.409444149f, (float16_t)-0.912335185f, + (float16_t)-0.408044163f, (float16_t)-0.912962190f, + (float16_t)-0.406643217f, (float16_t)-0.913587048f, + (float16_t)-0.405241314f, (float16_t)-0.914209756f, + (float16_t)-0.403838458f, (float16_t)-0.914830312f, + (float16_t)-0.402434651f, (float16_t)-0.915448716f, + (float16_t)-0.401029897f, (float16_t)-0.916064966f, + (float16_t)-0.399624200f, (float16_t)-0.916679060f, + (float16_t)-0.398217562f, (float16_t)-0.917290997f, + (float16_t)-0.396809987f, (float16_t)-0.917900776f, + (float16_t)-0.395401479f, (float16_t)-0.918508394f, + (float16_t)-0.393992040f, (float16_t)-0.919113852f, + (float16_t)-0.392581674f, (float16_t)-0.919717146f, + (float16_t)-0.391170384f, (float16_t)-0.920318277f, + (float16_t)-0.389758174f, (float16_t)-0.920917242f, + (float16_t)-0.388345047f, (float16_t)-0.921514039f, + (float16_t)-0.386931006f, (float16_t)-0.922108669f, + (float16_t)-0.385516054f, (float16_t)-0.922701128f, + (float16_t)-0.384100195f, (float16_t)-0.923291417f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.381265769f, (float16_t)-0.924465474f, + (float16_t)-0.379847209f, (float16_t)-0.925049241f, + (float16_t)-0.378427755f, (float16_t)-0.925630831f, + (float16_t)-0.377007410f, (float16_t)-0.926210242f, + (float16_t)-0.375586178f, (float16_t)-0.926787474f, + (float16_t)-0.374164063f, (float16_t)-0.927362526f, + (float16_t)-0.372741067f, (float16_t)-0.927935395f, + (float16_t)-0.371317194f, (float16_t)-0.928506080f, + (float16_t)-0.369892447f, (float16_t)-0.929074581f, + (float16_t)-0.368466830f, (float16_t)-0.929640896f, + (float16_t)-0.367040346f, (float16_t)-0.930205023f, + (float16_t)-0.365612998f, (float16_t)-0.930766961f, + (float16_t)-0.364184790f, (float16_t)-0.931326709f, + (float16_t)-0.362755724f, (float16_t)-0.931884266f, + (float16_t)-0.361325806f, (float16_t)-0.932439629f, + (float16_t)-0.359895037f, (float16_t)-0.932992799f, + (float16_t)-0.358463421f, (float16_t)-0.933543773f, + (float16_t)-0.357030961f, (float16_t)-0.934092550f, + (float16_t)-0.355597662f, (float16_t)-0.934639130f, + (float16_t)-0.354163525f, (float16_t)-0.935183510f, + (float16_t)-0.352728556f, (float16_t)-0.935725689f, + (float16_t)-0.351292756f, (float16_t)-0.936265667f, + (float16_t)-0.349856130f, (float16_t)-0.936803442f, + (float16_t)-0.348418680f, (float16_t)-0.937339012f, + (float16_t)-0.346980411f, (float16_t)-0.937872376f, + (float16_t)-0.345541325f, (float16_t)-0.938403534f, + (float16_t)-0.344101426f, (float16_t)-0.938932484f, + (float16_t)-0.342660717f, (float16_t)-0.939459224f, + (float16_t)-0.341219202f, (float16_t)-0.939983753f, + (float16_t)-0.339776884f, (float16_t)-0.940506071f, + (float16_t)-0.338333767f, (float16_t)-0.941026175f, + (float16_t)-0.336889853f, (float16_t)-0.941544065f, + (float16_t)-0.335445147f, (float16_t)-0.942059740f, + (float16_t)-0.333999651f, (float16_t)-0.942573198f, + (float16_t)-0.332553370f, (float16_t)-0.943084437f, + (float16_t)-0.331106306f, (float16_t)-0.943593458f, + (float16_t)-0.329658463f, (float16_t)-0.944100258f, + (float16_t)-0.328209844f, (float16_t)-0.944604837f, + (float16_t)-0.326760452f, (float16_t)-0.945107193f, + (float16_t)-0.325310292f, (float16_t)-0.945607325f, + (float16_t)-0.323859367f, (float16_t)-0.946105232f, + (float16_t)-0.322407679f, (float16_t)-0.946600913f, + (float16_t)-0.320955232f, (float16_t)-0.947094366f, + (float16_t)-0.319502031f, (float16_t)-0.947585591f, + (float16_t)-0.318048077f, (float16_t)-0.948074586f, + (float16_t)-0.316593376f, (float16_t)-0.948561350f, + (float16_t)-0.315137929f, (float16_t)-0.949045882f, + (float16_t)-0.313681740f, (float16_t)-0.949528181f, + (float16_t)-0.312224814f, (float16_t)-0.950008245f, + (float16_t)-0.310767153f, (float16_t)-0.950486074f, + (float16_t)-0.309308760f, (float16_t)-0.950961666f, + (float16_t)-0.307849640f, (float16_t)-0.951435021f, + (float16_t)-0.306389795f, (float16_t)-0.951906137f, + (float16_t)-0.304929230f, (float16_t)-0.952375013f, + (float16_t)-0.303467947f, (float16_t)-0.952841648f, + (float16_t)-0.302005949f, (float16_t)-0.953306040f, + (float16_t)-0.300543241f, (float16_t)-0.953768190f, + (float16_t)-0.299079826f, (float16_t)-0.954228095f, + (float16_t)-0.297615707f, (float16_t)-0.954685755f, + (float16_t)-0.296150888f, (float16_t)-0.955141168f, + (float16_t)-0.294685372f, (float16_t)-0.955594334f, + (float16_t)-0.293219163f, (float16_t)-0.956045251f, + (float16_t)-0.291752263f, (float16_t)-0.956493919f, + (float16_t)-0.290284677f, (float16_t)-0.956940336f, + (float16_t)-0.288816408f, (float16_t)-0.957384501f, + (float16_t)-0.287347460f, (float16_t)-0.957826413f, + (float16_t)-0.285877835f, (float16_t)-0.958266071f, + (float16_t)-0.284407537f, (float16_t)-0.958703475f, + (float16_t)-0.282936570f, (float16_t)-0.959138622f, + (float16_t)-0.281464938f, (float16_t)-0.959571513f, + (float16_t)-0.279992643f, (float16_t)-0.960002146f, + (float16_t)-0.278519689f, (float16_t)-0.960430519f, + (float16_t)-0.277046080f, (float16_t)-0.960856633f, + (float16_t)-0.275571819f, (float16_t)-0.961280486f, + (float16_t)-0.274096910f, (float16_t)-0.961702077f, + (float16_t)-0.272621355f, (float16_t)-0.962121404f, + (float16_t)-0.271145160f, (float16_t)-0.962538468f, + (float16_t)-0.269668326f, (float16_t)-0.962953267f, + (float16_t)-0.268190857f, (float16_t)-0.963365800f, + (float16_t)-0.266712757f, (float16_t)-0.963776066f, + (float16_t)-0.265234030f, (float16_t)-0.964184064f, + (float16_t)-0.263754679f, (float16_t)-0.964589793f, + (float16_t)-0.262274707f, (float16_t)-0.964993253f, + (float16_t)-0.260794118f, (float16_t)-0.965394442f, + (float16_t)-0.259312915f, (float16_t)-0.965793359f, + (float16_t)-0.257831102f, (float16_t)-0.966190003f, + (float16_t)-0.256348682f, (float16_t)-0.966584374f, + (float16_t)-0.254865660f, (float16_t)-0.966976471f, + (float16_t)-0.253382037f, (float16_t)-0.967366292f, + (float16_t)-0.251897818f, (float16_t)-0.967753837f, + (float16_t)-0.250413007f, (float16_t)-0.968139105f, + (float16_t)-0.248927606f, (float16_t)-0.968522094f, + (float16_t)-0.247441619f, (float16_t)-0.968902805f, + (float16_t)-0.245955050f, (float16_t)-0.969281235f, + (float16_t)-0.244467903f, (float16_t)-0.969657385f, + (float16_t)-0.242980180f, (float16_t)-0.970031253f, + (float16_t)-0.241491885f, (float16_t)-0.970402839f, + (float16_t)-0.240003022f, (float16_t)-0.970772141f, + (float16_t)-0.238513595f, (float16_t)-0.971139158f, + (float16_t)-0.237023606f, (float16_t)-0.971503891f, + (float16_t)-0.235533059f, (float16_t)-0.971866337f, + (float16_t)-0.234041959f, (float16_t)-0.972226497f, + (float16_t)-0.232550307f, (float16_t)-0.972584369f, + (float16_t)-0.231058108f, (float16_t)-0.972939952f, + (float16_t)-0.229565366f, (float16_t)-0.973293246f, + (float16_t)-0.228072083f, (float16_t)-0.973644250f, + (float16_t)-0.226578264f, (float16_t)-0.973992962f, + (float16_t)-0.225083911f, (float16_t)-0.974339383f, + (float16_t)-0.223589029f, (float16_t)-0.974683511f, + (float16_t)-0.222093621f, (float16_t)-0.975025345f, + (float16_t)-0.220597690f, (float16_t)-0.975364885f, + (float16_t)-0.219101240f, (float16_t)-0.975702130f, + (float16_t)-0.217604275f, (float16_t)-0.976037079f, + (float16_t)-0.216106797f, (float16_t)-0.976369731f, + (float16_t)-0.214608811f, (float16_t)-0.976700086f, + (float16_t)-0.213110320f, (float16_t)-0.977028143f, + (float16_t)-0.211611327f, (float16_t)-0.977353900f, + (float16_t)-0.210111837f, (float16_t)-0.977677358f, + (float16_t)-0.208611852f, (float16_t)-0.977998515f, + (float16_t)-0.207111376f, (float16_t)-0.978317371f, + (float16_t)-0.205610413f, (float16_t)-0.978633924f, + (float16_t)-0.204108966f, (float16_t)-0.978948175f, + (float16_t)-0.202607039f, (float16_t)-0.979260123f, + (float16_t)-0.201104635f, (float16_t)-0.979569766f, + (float16_t)-0.199601758f, (float16_t)-0.979877104f, + (float16_t)-0.198098411f, (float16_t)-0.980182136f, + (float16_t)-0.196594598f, (float16_t)-0.980484862f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.193585587f, (float16_t)-0.981083391f, + (float16_t)-0.192080397f, (float16_t)-0.981379193f, + (float16_t)-0.190574755f, (float16_t)-0.981672686f, + (float16_t)-0.189068664f, (float16_t)-0.981963869f, + (float16_t)-0.187562129f, (float16_t)-0.982252741f, + (float16_t)-0.186055152f, (float16_t)-0.982539302f, + (float16_t)-0.184547737f, (float16_t)-0.982823551f, + (float16_t)-0.183039888f, (float16_t)-0.983105487f, + (float16_t)-0.181531608f, (float16_t)-0.983385110f, + (float16_t)-0.180022901f, (float16_t)-0.983662419f, + (float16_t)-0.178513771f, (float16_t)-0.983937413f, + (float16_t)-0.177004220f, (float16_t)-0.984210092f, + (float16_t)-0.175494253f, (float16_t)-0.984480455f, + (float16_t)-0.173983873f, (float16_t)-0.984748502f, + (float16_t)-0.172473084f, (float16_t)-0.985014231f, + (float16_t)-0.170961889f, (float16_t)-0.985277642f, + (float16_t)-0.169450291f, (float16_t)-0.985538735f, + (float16_t)-0.167938295f, (float16_t)-0.985797509f, + (float16_t)-0.166425904f, (float16_t)-0.986053963f, + (float16_t)-0.164913120f, (float16_t)-0.986308097f, + (float16_t)-0.163399949f, (float16_t)-0.986559910f, + (float16_t)-0.161886394f, (float16_t)-0.986809402f, + (float16_t)-0.160372457f, (float16_t)-0.987056571f, + (float16_t)-0.158858143f, (float16_t)-0.987301418f, + (float16_t)-0.157343456f, (float16_t)-0.987543942f, + (float16_t)-0.155828398f, (float16_t)-0.987784142f, + (float16_t)-0.154312973f, (float16_t)-0.988022017f, + (float16_t)-0.152797185f, (float16_t)-0.988257568f, + (float16_t)-0.151281038f, (float16_t)-0.988490793f, + (float16_t)-0.149764535f, (float16_t)-0.988721692f, + (float16_t)-0.148247679f, (float16_t)-0.988950265f, + (float16_t)-0.146730474f, (float16_t)-0.989176510f, + (float16_t)-0.145212925f, (float16_t)-0.989400428f, + (float16_t)-0.143695033f, (float16_t)-0.989622017f, + (float16_t)-0.142176804f, (float16_t)-0.989841278f, + (float16_t)-0.140658239f, (float16_t)-0.990058210f, + (float16_t)-0.139139344f, (float16_t)-0.990272812f, + (float16_t)-0.137620122f, (float16_t)-0.990485084f, + (float16_t)-0.136100575f, (float16_t)-0.990695025f, + (float16_t)-0.134580709f, (float16_t)-0.990902635f, + (float16_t)-0.133060525f, (float16_t)-0.991107914f, + (float16_t)-0.131540029f, (float16_t)-0.991310860f, + (float16_t)-0.130019223f, (float16_t)-0.991511473f, + (float16_t)-0.128498111f, (float16_t)-0.991709754f, + (float16_t)-0.126976696f, (float16_t)-0.991905700f, + (float16_t)-0.125454983f, (float16_t)-0.992099313f, + (float16_t)-0.123932975f, (float16_t)-0.992290591f, + (float16_t)-0.122410675f, (float16_t)-0.992479535f, + (float16_t)-0.120888087f, (float16_t)-0.992666142f, + (float16_t)-0.119365215f, (float16_t)-0.992850414f, + (float16_t)-0.117842062f, (float16_t)-0.993032350f, + (float16_t)-0.116318631f, (float16_t)-0.993211949f, + (float16_t)-0.114794927f, (float16_t)-0.993389211f, + (float16_t)-0.113270952f, (float16_t)-0.993564136f, + (float16_t)-0.111746711f, (float16_t)-0.993736722f, + (float16_t)-0.110222207f, (float16_t)-0.993906970f, + (float16_t)-0.108697444f, (float16_t)-0.994074879f, + (float16_t)-0.107172425f, (float16_t)-0.994240449f, + (float16_t)-0.105647154f, (float16_t)-0.994403680f, + (float16_t)-0.104121634f, (float16_t)-0.994564571f, + (float16_t)-0.102595869f, (float16_t)-0.994723121f, + (float16_t)-0.101069863f, (float16_t)-0.994879331f, + (float16_t)-0.099543619f, (float16_t)-0.995033199f, + (float16_t)-0.098017140f, (float16_t)-0.995184727f, + (float16_t)-0.096490431f, (float16_t)-0.995333912f, + (float16_t)-0.094963495f, (float16_t)-0.995480755f, + (float16_t)-0.093436336f, (float16_t)-0.995625256f, + (float16_t)-0.091908956f, (float16_t)-0.995767414f, + (float16_t)-0.090381361f, (float16_t)-0.995907229f, + (float16_t)-0.088853553f, (float16_t)-0.996044701f, + (float16_t)-0.087325535f, (float16_t)-0.996179829f, + (float16_t)-0.085797312f, (float16_t)-0.996312612f, + (float16_t)-0.084268888f, (float16_t)-0.996443051f, + (float16_t)-0.082740265f, (float16_t)-0.996571146f, + (float16_t)-0.081211447f, (float16_t)-0.996696895f, + (float16_t)-0.079682438f, (float16_t)-0.996820299f, + (float16_t)-0.078153242f, (float16_t)-0.996941358f, + (float16_t)-0.076623861f, (float16_t)-0.997060070f, + (float16_t)-0.075094301f, (float16_t)-0.997176437f, + (float16_t)-0.073564564f, (float16_t)-0.997290457f, + (float16_t)-0.072034653f, (float16_t)-0.997402130f, + (float16_t)-0.070504573f, (float16_t)-0.997511456f, + (float16_t)-0.068974328f, (float16_t)-0.997618435f, + (float16_t)-0.067443920f, (float16_t)-0.997723067f, + (float16_t)-0.065913353f, (float16_t)-0.997825350f, + (float16_t)-0.064382631f, (float16_t)-0.997925286f, + (float16_t)-0.062851758f, (float16_t)-0.998022874f, + (float16_t)-0.061320736f, (float16_t)-0.998118113f, + (float16_t)-0.059789571f, (float16_t)-0.998211003f, + (float16_t)-0.058258265f, (float16_t)-0.998301545f, + (float16_t)-0.056726821f, (float16_t)-0.998389737f, + (float16_t)-0.055195244f, (float16_t)-0.998475581f, + (float16_t)-0.053663538f, (float16_t)-0.998559074f, + (float16_t)-0.052131705f, (float16_t)-0.998640218f, + (float16_t)-0.050599749f, (float16_t)-0.998719012f, + (float16_t)-0.049067674f, (float16_t)-0.998795456f, + (float16_t)-0.047535484f, (float16_t)-0.998869550f, + (float16_t)-0.046003182f, (float16_t)-0.998941293f, + (float16_t)-0.044470772f, (float16_t)-0.999010686f, + (float16_t)-0.042938257f, (float16_t)-0.999077728f, + (float16_t)-0.041405641f, (float16_t)-0.999142419f, + (float16_t)-0.039872928f, (float16_t)-0.999204759f, + (float16_t)-0.038340120f, (float16_t)-0.999264747f, + (float16_t)-0.036807223f, (float16_t)-0.999322385f, + (float16_t)-0.035274239f, (float16_t)-0.999377670f, + (float16_t)-0.033741172f, (float16_t)-0.999430605f, + (float16_t)-0.032208025f, (float16_t)-0.999481187f, + (float16_t)-0.030674803f, (float16_t)-0.999529418f, + (float16_t)-0.029141509f, (float16_t)-0.999575296f, + (float16_t)-0.027608146f, (float16_t)-0.999618822f, + (float16_t)-0.026074718f, (float16_t)-0.999659997f, + (float16_t)-0.024541229f, (float16_t)-0.999698819f, + (float16_t)-0.023007681f, (float16_t)-0.999735288f, + (float16_t)-0.021474080f, (float16_t)-0.999769405f, + (float16_t)-0.019940429f, (float16_t)-0.999801170f, + (float16_t)-0.018406730f, (float16_t)-0.999830582f, + (float16_t)-0.016872988f, (float16_t)-0.999857641f, + (float16_t)-0.015339206f, (float16_t)-0.999882347f, + (float16_t)-0.013805389f, (float16_t)-0.999904701f, + (float16_t)-0.012271538f, (float16_t)-0.999924702f, + (float16_t)-0.010737659f, (float16_t)-0.999942350f, + (float16_t)-0.009203755f, (float16_t)-0.999957645f, + (float16_t)-0.007669829f, (float16_t)-0.999970586f, + (float16_t)-0.006135885f, (float16_t)-0.999981175f, + (float16_t)-0.004601926f, (float16_t)-0.999989411f, + (float16_t)-0.003067957f, (float16_t)-0.999995294f, + (float16_t)-0.001533980f, (float16_t)-0.999998823f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.001533980f, (float16_t)-0.999998823f, + (float16_t)0.003067957f, (float16_t)-0.999995294f, + (float16_t)0.004601926f, (float16_t)-0.999989411f, + (float16_t)0.006135885f, (float16_t)-0.999981175f, + (float16_t)0.007669829f, (float16_t)-0.999970586f, + (float16_t)0.009203755f, (float16_t)-0.999957645f, + (float16_t)0.010737659f, (float16_t)-0.999942350f, + (float16_t)0.012271538f, (float16_t)-0.999924702f, + (float16_t)0.013805389f, (float16_t)-0.999904701f, + (float16_t)0.015339206f, (float16_t)-0.999882347f, + (float16_t)0.016872988f, (float16_t)-0.999857641f, + (float16_t)0.018406730f, (float16_t)-0.999830582f, + (float16_t)0.019940429f, (float16_t)-0.999801170f, + (float16_t)0.021474080f, (float16_t)-0.999769405f, + (float16_t)0.023007681f, (float16_t)-0.999735288f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.026074718f, (float16_t)-0.999659997f, + (float16_t)0.027608146f, (float16_t)-0.999618822f, + (float16_t)0.029141509f, (float16_t)-0.999575296f, + (float16_t)0.030674803f, (float16_t)-0.999529418f, + (float16_t)0.032208025f, (float16_t)-0.999481187f, + (float16_t)0.033741172f, (float16_t)-0.999430605f, + (float16_t)0.035274239f, (float16_t)-0.999377670f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.038340120f, (float16_t)-0.999264747f, + (float16_t)0.039872928f, (float16_t)-0.999204759f, + (float16_t)0.041405641f, (float16_t)-0.999142419f, + (float16_t)0.042938257f, (float16_t)-0.999077728f, + (float16_t)0.044470772f, (float16_t)-0.999010686f, + (float16_t)0.046003182f, (float16_t)-0.998941293f, + (float16_t)0.047535484f, (float16_t)-0.998869550f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.050599749f, (float16_t)-0.998719012f, + (float16_t)0.052131705f, (float16_t)-0.998640218f, + (float16_t)0.053663538f, (float16_t)-0.998559074f, + (float16_t)0.055195244f, (float16_t)-0.998475581f, + (float16_t)0.056726821f, (float16_t)-0.998389737f, + (float16_t)0.058258265f, (float16_t)-0.998301545f, + (float16_t)0.059789571f, (float16_t)-0.998211003f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.062851758f, (float16_t)-0.998022874f, + (float16_t)0.064382631f, (float16_t)-0.997925286f, + (float16_t)0.065913353f, (float16_t)-0.997825350f, + (float16_t)0.067443920f, (float16_t)-0.997723067f, + (float16_t)0.068974328f, (float16_t)-0.997618435f, + (float16_t)0.070504573f, (float16_t)-0.997511456f, + (float16_t)0.072034653f, (float16_t)-0.997402130f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.075094301f, (float16_t)-0.997176437f, + (float16_t)0.076623861f, (float16_t)-0.997060070f, + (float16_t)0.078153242f, (float16_t)-0.996941358f, + (float16_t)0.079682438f, (float16_t)-0.996820299f, + (float16_t)0.081211447f, (float16_t)-0.996696895f, + (float16_t)0.082740265f, (float16_t)-0.996571146f, + (float16_t)0.084268888f, (float16_t)-0.996443051f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.087325535f, (float16_t)-0.996179829f, + (float16_t)0.088853553f, (float16_t)-0.996044701f, + (float16_t)0.090381361f, (float16_t)-0.995907229f, + (float16_t)0.091908956f, (float16_t)-0.995767414f, + (float16_t)0.093436336f, (float16_t)-0.995625256f, + (float16_t)0.094963495f, (float16_t)-0.995480755f, + (float16_t)0.096490431f, (float16_t)-0.995333912f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.099543619f, (float16_t)-0.995033199f, + (float16_t)0.101069863f, (float16_t)-0.994879331f, + (float16_t)0.102595869f, (float16_t)-0.994723121f, + (float16_t)0.104121634f, (float16_t)-0.994564571f, + (float16_t)0.105647154f, (float16_t)-0.994403680f, + (float16_t)0.107172425f, (float16_t)-0.994240449f, + (float16_t)0.108697444f, (float16_t)-0.994074879f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.111746711f, (float16_t)-0.993736722f, + (float16_t)0.113270952f, (float16_t)-0.993564136f, + (float16_t)0.114794927f, (float16_t)-0.993389211f, + (float16_t)0.116318631f, (float16_t)-0.993211949f, + (float16_t)0.117842062f, (float16_t)-0.993032350f, + (float16_t)0.119365215f, (float16_t)-0.992850414f, + (float16_t)0.120888087f, (float16_t)-0.992666142f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.123932975f, (float16_t)-0.992290591f, + (float16_t)0.125454983f, (float16_t)-0.992099313f, + (float16_t)0.126976696f, (float16_t)-0.991905700f, + (float16_t)0.128498111f, (float16_t)-0.991709754f, + (float16_t)0.130019223f, (float16_t)-0.991511473f, + (float16_t)0.131540029f, (float16_t)-0.991310860f, + (float16_t)0.133060525f, (float16_t)-0.991107914f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.136100575f, (float16_t)-0.990695025f, + (float16_t)0.137620122f, (float16_t)-0.990485084f, + (float16_t)0.139139344f, (float16_t)-0.990272812f, + (float16_t)0.140658239f, (float16_t)-0.990058210f, + (float16_t)0.142176804f, (float16_t)-0.989841278f, + (float16_t)0.143695033f, (float16_t)-0.989622017f, + (float16_t)0.145212925f, (float16_t)-0.989400428f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.148247679f, (float16_t)-0.988950265f, + (float16_t)0.149764535f, (float16_t)-0.988721692f, + (float16_t)0.151281038f, (float16_t)-0.988490793f, + (float16_t)0.152797185f, (float16_t)-0.988257568f, + (float16_t)0.154312973f, (float16_t)-0.988022017f, + (float16_t)0.155828398f, (float16_t)-0.987784142f, + (float16_t)0.157343456f, (float16_t)-0.987543942f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.160372457f, (float16_t)-0.987056571f, + (float16_t)0.161886394f, (float16_t)-0.986809402f, + (float16_t)0.163399949f, (float16_t)-0.986559910f, + (float16_t)0.164913120f, (float16_t)-0.986308097f, + (float16_t)0.166425904f, (float16_t)-0.986053963f, + (float16_t)0.167938295f, (float16_t)-0.985797509f, + (float16_t)0.169450291f, (float16_t)-0.985538735f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.172473084f, (float16_t)-0.985014231f, + (float16_t)0.173983873f, (float16_t)-0.984748502f, + (float16_t)0.175494253f, (float16_t)-0.984480455f, + (float16_t)0.177004220f, (float16_t)-0.984210092f, + (float16_t)0.178513771f, (float16_t)-0.983937413f, + (float16_t)0.180022901f, (float16_t)-0.983662419f, + (float16_t)0.181531608f, (float16_t)-0.983385110f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.184547737f, (float16_t)-0.982823551f, + (float16_t)0.186055152f, (float16_t)-0.982539302f, + (float16_t)0.187562129f, (float16_t)-0.982252741f, + (float16_t)0.189068664f, (float16_t)-0.981963869f, + (float16_t)0.190574755f, (float16_t)-0.981672686f, + (float16_t)0.192080397f, (float16_t)-0.981379193f, + (float16_t)0.193585587f, (float16_t)-0.981083391f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.196594598f, (float16_t)-0.980484862f, + (float16_t)0.198098411f, (float16_t)-0.980182136f, + (float16_t)0.199601758f, (float16_t)-0.979877104f, + (float16_t)0.201104635f, (float16_t)-0.979569766f, + (float16_t)0.202607039f, (float16_t)-0.979260123f, + (float16_t)0.204108966f, (float16_t)-0.978948175f, + (float16_t)0.205610413f, (float16_t)-0.978633924f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.208611852f, (float16_t)-0.977998515f, + (float16_t)0.210111837f, (float16_t)-0.977677358f, + (float16_t)0.211611327f, (float16_t)-0.977353900f, + (float16_t)0.213110320f, (float16_t)-0.977028143f, + (float16_t)0.214608811f, (float16_t)-0.976700086f, + (float16_t)0.216106797f, (float16_t)-0.976369731f, + (float16_t)0.217604275f, (float16_t)-0.976037079f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.220597690f, (float16_t)-0.975364885f, + (float16_t)0.222093621f, (float16_t)-0.975025345f, + (float16_t)0.223589029f, (float16_t)-0.974683511f, + (float16_t)0.225083911f, (float16_t)-0.974339383f, + (float16_t)0.226578264f, (float16_t)-0.973992962f, + (float16_t)0.228072083f, (float16_t)-0.973644250f, + (float16_t)0.229565366f, (float16_t)-0.973293246f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.232550307f, (float16_t)-0.972584369f, + (float16_t)0.234041959f, (float16_t)-0.972226497f, + (float16_t)0.235533059f, (float16_t)-0.971866337f, + (float16_t)0.237023606f, (float16_t)-0.971503891f, + (float16_t)0.238513595f, (float16_t)-0.971139158f, + (float16_t)0.240003022f, (float16_t)-0.970772141f, + (float16_t)0.241491885f, (float16_t)-0.970402839f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.244467903f, (float16_t)-0.969657385f, + (float16_t)0.245955050f, (float16_t)-0.969281235f, + (float16_t)0.247441619f, (float16_t)-0.968902805f, + (float16_t)0.248927606f, (float16_t)-0.968522094f, + (float16_t)0.250413007f, (float16_t)-0.968139105f, + (float16_t)0.251897818f, (float16_t)-0.967753837f, + (float16_t)0.253382037f, (float16_t)-0.967366292f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.256348682f, (float16_t)-0.966584374f, + (float16_t)0.257831102f, (float16_t)-0.966190003f, + (float16_t)0.259312915f, (float16_t)-0.965793359f, + (float16_t)0.260794118f, (float16_t)-0.965394442f, + (float16_t)0.262274707f, (float16_t)-0.964993253f, + (float16_t)0.263754679f, (float16_t)-0.964589793f, + (float16_t)0.265234030f, (float16_t)-0.964184064f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.268190857f, (float16_t)-0.963365800f, + (float16_t)0.269668326f, (float16_t)-0.962953267f, + (float16_t)0.271145160f, (float16_t)-0.962538468f, + (float16_t)0.272621355f, (float16_t)-0.962121404f, + (float16_t)0.274096910f, (float16_t)-0.961702077f, + (float16_t)0.275571819f, (float16_t)-0.961280486f, + (float16_t)0.277046080f, (float16_t)-0.960856633f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.279992643f, (float16_t)-0.960002146f, + (float16_t)0.281464938f, (float16_t)-0.959571513f, + (float16_t)0.282936570f, (float16_t)-0.959138622f, + (float16_t)0.284407537f, (float16_t)-0.958703475f, + (float16_t)0.285877835f, (float16_t)-0.958266071f, + (float16_t)0.287347460f, (float16_t)-0.957826413f, + (float16_t)0.288816408f, (float16_t)-0.957384501f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.291752263f, (float16_t)-0.956493919f, + (float16_t)0.293219163f, (float16_t)-0.956045251f, + (float16_t)0.294685372f, (float16_t)-0.955594334f, + (float16_t)0.296150888f, (float16_t)-0.955141168f, + (float16_t)0.297615707f, (float16_t)-0.954685755f, + (float16_t)0.299079826f, (float16_t)-0.954228095f, + (float16_t)0.300543241f, (float16_t)-0.953768190f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.303467947f, (float16_t)-0.952841648f, + (float16_t)0.304929230f, (float16_t)-0.952375013f, + (float16_t)0.306389795f, (float16_t)-0.951906137f, + (float16_t)0.307849640f, (float16_t)-0.951435021f, + (float16_t)0.309308760f, (float16_t)-0.950961666f, + (float16_t)0.310767153f, (float16_t)-0.950486074f, + (float16_t)0.312224814f, (float16_t)-0.950008245f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.315137929f, (float16_t)-0.949045882f, + (float16_t)0.316593376f, (float16_t)-0.948561350f, + (float16_t)0.318048077f, (float16_t)-0.948074586f, + (float16_t)0.319502031f, (float16_t)-0.947585591f, + (float16_t)0.320955232f, (float16_t)-0.947094366f, + (float16_t)0.322407679f, (float16_t)-0.946600913f, + (float16_t)0.323859367f, (float16_t)-0.946105232f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.326760452f, (float16_t)-0.945107193f, + (float16_t)0.328209844f, (float16_t)-0.944604837f, + (float16_t)0.329658463f, (float16_t)-0.944100258f, + (float16_t)0.331106306f, (float16_t)-0.943593458f, + (float16_t)0.332553370f, (float16_t)-0.943084437f, + (float16_t)0.333999651f, (float16_t)-0.942573198f, + (float16_t)0.335445147f, (float16_t)-0.942059740f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.338333767f, (float16_t)-0.941026175f, + (float16_t)0.339776884f, (float16_t)-0.940506071f, + (float16_t)0.341219202f, (float16_t)-0.939983753f, + (float16_t)0.342660717f, (float16_t)-0.939459224f, + (float16_t)0.344101426f, (float16_t)-0.938932484f, + (float16_t)0.345541325f, (float16_t)-0.938403534f, + (float16_t)0.346980411f, (float16_t)-0.937872376f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.349856130f, (float16_t)-0.936803442f, + (float16_t)0.351292756f, (float16_t)-0.936265667f, + (float16_t)0.352728556f, (float16_t)-0.935725689f, + (float16_t)0.354163525f, (float16_t)-0.935183510f, + (float16_t)0.355597662f, (float16_t)-0.934639130f, + (float16_t)0.357030961f, (float16_t)-0.934092550f, + (float16_t)0.358463421f, (float16_t)-0.933543773f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.361325806f, (float16_t)-0.932439629f, + (float16_t)0.362755724f, (float16_t)-0.931884266f, + (float16_t)0.364184790f, (float16_t)-0.931326709f, + (float16_t)0.365612998f, (float16_t)-0.930766961f, + (float16_t)0.367040346f, (float16_t)-0.930205023f, + (float16_t)0.368466830f, (float16_t)-0.929640896f, + (float16_t)0.369892447f, (float16_t)-0.929074581f, + (float16_t)0.371317194f, (float16_t)-0.928506080f, + (float16_t)0.372741067f, (float16_t)-0.927935395f, + (float16_t)0.374164063f, (float16_t)-0.927362526f, + (float16_t)0.375586178f, (float16_t)-0.926787474f, + (float16_t)0.377007410f, (float16_t)-0.926210242f, + (float16_t)0.378427755f, (float16_t)-0.925630831f, + (float16_t)0.379847209f, (float16_t)-0.925049241f, + (float16_t)0.381265769f, (float16_t)-0.924465474f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.384100195f, (float16_t)-0.923291417f, + (float16_t)0.385516054f, (float16_t)-0.922701128f, + (float16_t)0.386931006f, (float16_t)-0.922108669f, + (float16_t)0.388345047f, (float16_t)-0.921514039f, + (float16_t)0.389758174f, (float16_t)-0.920917242f, + (float16_t)0.391170384f, (float16_t)-0.920318277f, + (float16_t)0.392581674f, (float16_t)-0.919717146f, + (float16_t)0.393992040f, (float16_t)-0.919113852f, + (float16_t)0.395401479f, (float16_t)-0.918508394f, + (float16_t)0.396809987f, (float16_t)-0.917900776f, + (float16_t)0.398217562f, (float16_t)-0.917290997f, + (float16_t)0.399624200f, (float16_t)-0.916679060f, + (float16_t)0.401029897f, (float16_t)-0.916064966f, + (float16_t)0.402434651f, (float16_t)-0.915448716f, + (float16_t)0.403838458f, (float16_t)-0.914830312f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.406643217f, (float16_t)-0.913587048f, + (float16_t)0.408044163f, (float16_t)-0.912962190f, + (float16_t)0.409444149f, (float16_t)-0.912335185f, + (float16_t)0.410843171f, (float16_t)-0.911706032f, + (float16_t)0.412241227f, (float16_t)-0.911074734f, + (float16_t)0.413638312f, (float16_t)-0.910441292f, + (float16_t)0.415034424f, (float16_t)-0.909805708f, + (float16_t)0.416429560f, (float16_t)-0.909167983f, + (float16_t)0.417823716f, (float16_t)-0.908528119f, + (float16_t)0.419216888f, (float16_t)-0.907886116f, + (float16_t)0.420609074f, (float16_t)-0.907241978f, + (float16_t)0.422000271f, (float16_t)-0.906595705f, + (float16_t)0.423390474f, (float16_t)-0.905947298f, + (float16_t)0.424779681f, (float16_t)-0.905296759f, + (float16_t)0.426167889f, (float16_t)-0.904644091f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.428941292f, (float16_t)-0.903332368f, + (float16_t)0.430326481f, (float16_t)-0.902673318f, + (float16_t)0.431710658f, (float16_t)-0.902012144f, + (float16_t)0.433093819f, (float16_t)-0.901348847f, + (float16_t)0.434475961f, (float16_t)-0.900683429f, + (float16_t)0.435857080f, (float16_t)-0.900015892f, + (float16_t)0.437237174f, (float16_t)-0.899346237f, + (float16_t)0.438616239f, (float16_t)-0.898674466f, + (float16_t)0.439994271f, (float16_t)-0.898000580f, + (float16_t)0.441371269f, (float16_t)-0.897324581f, + (float16_t)0.442747228f, (float16_t)-0.896646470f, + (float16_t)0.444122145f, (float16_t)-0.895966250f, + (float16_t)0.445496017f, (float16_t)-0.895283921f, + (float16_t)0.446868840f, (float16_t)-0.894599486f, + (float16_t)0.448240612f, (float16_t)-0.893912945f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.450980989f, (float16_t)-0.892533555f, + (float16_t)0.452349587f, (float16_t)-0.891840709f, + (float16_t)0.453717121f, (float16_t)-0.891145765f, + (float16_t)0.455083587f, (float16_t)-0.890448723f, + (float16_t)0.456448982f, (float16_t)-0.889749586f, + (float16_t)0.457813304f, (float16_t)-0.889048356f, + (float16_t)0.459176548f, (float16_t)-0.888345033f, + (float16_t)0.460538711f, (float16_t)-0.887639620f, + (float16_t)0.461899791f, (float16_t)-0.886932119f, + (float16_t)0.463259784f, (float16_t)-0.886222530f, + (float16_t)0.464618686f, (float16_t)-0.885510856f, + (float16_t)0.465976496f, (float16_t)-0.884797098f, + (float16_t)0.467333209f, (float16_t)-0.884081259f, + (float16_t)0.468688822f, (float16_t)-0.883363339f, + (float16_t)0.470043332f, (float16_t)-0.882643340f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.472749032f, (float16_t)-0.881197113f, + (float16_t)0.474100215f, (float16_t)-0.880470889f, + (float16_t)0.475450282f, (float16_t)-0.879742593f, + (float16_t)0.476799230f, (float16_t)-0.879012226f, + (float16_t)0.478147056f, (float16_t)-0.878279792f, + (float16_t)0.479493758f, (float16_t)-0.877545290f, + (float16_t)0.480839331f, (float16_t)-0.876808724f, + (float16_t)0.482183772f, (float16_t)-0.876070094f, + (float16_t)0.483527079f, (float16_t)-0.875329403f, + (float16_t)0.484869248f, (float16_t)-0.874586652f, + (float16_t)0.486210276f, (float16_t)-0.873841843f, + (float16_t)0.487550160f, (float16_t)-0.873094978f, + (float16_t)0.488888897f, (float16_t)-0.872346059f, + (float16_t)0.490226483f, (float16_t)-0.871595087f, + (float16_t)0.491562916f, (float16_t)-0.870842063f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.494232309f, (float16_t)-0.869329871f, + (float16_t)0.495565262f, (float16_t)-0.868570706f, + (float16_t)0.496897049f, (float16_t)-0.867809497f, + (float16_t)0.498227667f, (float16_t)-0.867046246f, + (float16_t)0.499557113f, (float16_t)-0.866280954f, + (float16_t)0.500885383f, (float16_t)-0.865513624f, + (float16_t)0.502212474f, (float16_t)-0.864744258f, + (float16_t)0.503538384f, (float16_t)-0.863972856f, + (float16_t)0.504863109f, (float16_t)-0.863199422f, + (float16_t)0.506186645f, (float16_t)-0.862423956f, + (float16_t)0.507508991f, (float16_t)-0.861646461f, + (float16_t)0.508830143f, (float16_t)-0.860866939f, + (float16_t)0.510150097f, (float16_t)-0.860085390f, + (float16_t)0.511468850f, (float16_t)-0.859301818f, + (float16_t)0.512786401f, (float16_t)-0.858516224f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.515417878f, (float16_t)-0.856938977f, + (float16_t)0.516731799f, (float16_t)-0.856147328f, + (float16_t)0.518044504f, (float16_t)-0.855353665f, + (float16_t)0.519355990f, (float16_t)-0.854557988f, + (float16_t)0.520666254f, (float16_t)-0.853760301f, + (float16_t)0.521975293f, (float16_t)-0.852960605f, + (float16_t)0.523283103f, (float16_t)-0.852158902f, + (float16_t)0.524589683f, (float16_t)-0.851355193f, + (float16_t)0.525895027f, (float16_t)-0.850549481f, + (float16_t)0.527199135f, (float16_t)-0.849741768f, + (float16_t)0.528502002f, (float16_t)-0.848932055f, + (float16_t)0.529803625f, (float16_t)-0.848120345f, + (float16_t)0.531104001f, (float16_t)-0.847306639f, + (float16_t)0.532403128f, (float16_t)-0.846490939f, + (float16_t)0.533701002f, (float16_t)-0.845673247f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.536292979f, (float16_t)-0.844031895f, + (float16_t)0.537587076f, (float16_t)-0.843208240f, + (float16_t)0.538879909f, (float16_t)-0.842382600f, + (float16_t)0.540171473f, (float16_t)-0.841554977f, + (float16_t)0.541461766f, (float16_t)-0.840725375f, + (float16_t)0.542750785f, (float16_t)-0.839893794f, + (float16_t)0.544038527f, (float16_t)-0.839060237f, + (float16_t)0.545324988f, (float16_t)-0.838224706f, + (float16_t)0.546610167f, (float16_t)-0.837387202f, + (float16_t)0.547894059f, (float16_t)-0.836547727f, + (float16_t)0.549176662f, (float16_t)-0.835706284f, + (float16_t)0.550457973f, (float16_t)-0.834862875f, + (float16_t)0.551737988f, (float16_t)-0.834017501f, + (float16_t)0.553016706f, (float16_t)-0.833170165f, + (float16_t)0.554294121f, (float16_t)-0.832320868f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.556845037f, (float16_t)-0.830616400f, + (float16_t)0.558118531f, (float16_t)-0.829761234f, + (float16_t)0.559390712f, (float16_t)-0.828904115f, + (float16_t)0.560661576f, (float16_t)-0.828045045f, + (float16_t)0.561931121f, (float16_t)-0.827184027f, + (float16_t)0.563199344f, (float16_t)-0.826321063f, + (float16_t)0.564466242f, (float16_t)-0.825456154f, + (float16_t)0.565731811f, (float16_t)-0.824589303f, + (float16_t)0.566996049f, (float16_t)-0.823720511f, + (float16_t)0.568258953f, (float16_t)-0.822849781f, + (float16_t)0.569520519f, (float16_t)-0.821977115f, + (float16_t)0.570780746f, (float16_t)-0.821102515f, + (float16_t)0.572039629f, (float16_t)-0.820225983f, + (float16_t)0.573297167f, (float16_t)-0.819347520f, + (float16_t)0.574553355f, (float16_t)-0.818467130f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.577061673f, (float16_t)-0.816700573f, + (float16_t)0.578313796f, (float16_t)-0.815814411f, + (float16_t)0.579564559f, (float16_t)-0.814926329f, + (float16_t)0.580813958f, (float16_t)-0.814036330f, + (float16_t)0.582061990f, (float16_t)-0.813144415f, + (float16_t)0.583308653f, (float16_t)-0.812250587f, + (float16_t)0.584553943f, (float16_t)-0.811354847f, + (float16_t)0.585797857f, (float16_t)-0.810457198f, + (float16_t)0.587040394f, (float16_t)-0.809557642f, + (float16_t)0.588281548f, (float16_t)-0.808656182f, + (float16_t)0.589521319f, (float16_t)-0.807752818f, + (float16_t)0.590759702f, (float16_t)-0.806847554f, + (float16_t)0.591996695f, (float16_t)-0.805940391f, + (float16_t)0.593232295f, (float16_t)-0.805031331f, + (float16_t)0.594466499f, (float16_t)-0.804120377f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.596930708f, (float16_t)-0.802292796f, + (float16_t)0.598160707f, (float16_t)-0.801376172f, + (float16_t)0.599389298f, (float16_t)-0.800457662f, + (float16_t)0.600616479f, (float16_t)-0.799537269f, + (float16_t)0.601842247f, (float16_t)-0.798614995f, + (float16_t)0.603066599f, (float16_t)-0.797690841f, + (float16_t)0.604289531f, (float16_t)-0.796764810f, + (float16_t)0.605511041f, (float16_t)-0.795836905f, + (float16_t)0.606731127f, (float16_t)-0.794907126f, + (float16_t)0.607949785f, (float16_t)-0.793975478f, + (float16_t)0.609167012f, (float16_t)-0.793041960f, + (float16_t)0.610382806f, (float16_t)-0.792106577f, + (float16_t)0.611597164f, (float16_t)-0.791169330f, + (float16_t)0.612810082f, (float16_t)-0.790230221f, + (float16_t)0.614021559f, (float16_t)-0.789289253f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.616440175f, (float16_t)-0.787401747f, + (float16_t)0.617647308f, (float16_t)-0.786455214f, + (float16_t)0.618852988f, (float16_t)-0.785506830f, + (float16_t)0.620057212f, (float16_t)-0.784556597f, + (float16_t)0.621259977f, (float16_t)-0.783604519f, + (float16_t)0.622461279f, (float16_t)-0.782650596f, + (float16_t)0.623661118f, (float16_t)-0.781694832f, + (float16_t)0.624859488f, (float16_t)-0.780737229f, + (float16_t)0.626056388f, (float16_t)-0.779777788f, + (float16_t)0.627251815f, (float16_t)-0.778816512f, + (float16_t)0.628445767f, (float16_t)-0.777853404f, + (float16_t)0.629638239f, (float16_t)-0.776888466f, + (float16_t)0.630829230f, (float16_t)-0.775921699f, + (float16_t)0.632018736f, (float16_t)-0.774953107f, + (float16_t)0.633206755f, (float16_t)-0.773982691f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.635578320f, (float16_t)-0.772036397f, + (float16_t)0.636761861f, (float16_t)-0.771060524f, + (float16_t)0.637943904f, (float16_t)-0.770082837f, + (float16_t)0.639124445f, (float16_t)-0.769103338f, + (float16_t)0.640303482f, (float16_t)-0.768122029f, + (float16_t)0.641481013f, (float16_t)-0.767138912f, + (float16_t)0.642657034f, (float16_t)-0.766153990f, + (float16_t)0.643831543f, (float16_t)-0.765167266f, + (float16_t)0.645004537f, (float16_t)-0.764178741f, + (float16_t)0.646176013f, (float16_t)-0.763188417f, + (float16_t)0.647345969f, (float16_t)-0.762196298f, + (float16_t)0.648514401f, (float16_t)-0.761202385f, + (float16_t)0.649681307f, (float16_t)-0.760206682f, + (float16_t)0.650846685f, (float16_t)-0.759209189f, + (float16_t)0.652010531f, (float16_t)-0.758209910f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.654333618f, (float16_t)-0.756206001f, + (float16_t)0.655492853f, (float16_t)-0.755201377f, + (float16_t)0.656650546f, (float16_t)-0.754194975f, + (float16_t)0.657806693f, (float16_t)-0.753186799f, + (float16_t)0.658961293f, (float16_t)-0.752176850f, + (float16_t)0.660114342f, (float16_t)-0.751165132f, + (float16_t)0.661265838f, (float16_t)-0.750151646f, + (float16_t)0.662415778f, (float16_t)-0.749136395f, + (float16_t)0.663564159f, (float16_t)-0.748119380f, + (float16_t)0.664710978f, (float16_t)-0.747100606f, + (float16_t)0.665856234f, (float16_t)-0.746080074f, + (float16_t)0.666999922f, (float16_t)-0.745057785f, + (float16_t)0.668142041f, (float16_t)-0.744033744f, + (float16_t)0.669282588f, (float16_t)-0.743007952f, + (float16_t)0.670421560f, (float16_t)-0.741980412f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.672694769f, (float16_t)-0.739920095f, + (float16_t)0.673829000f, (float16_t)-0.738887324f, + (float16_t)0.674961646f, (float16_t)-0.737852815f, + (float16_t)0.676092704f, (float16_t)-0.736816569f, + (float16_t)0.677222170f, (float16_t)-0.735778589f, + (float16_t)0.678350043f, (float16_t)-0.734738878f, + (float16_t)0.679476320f, (float16_t)-0.733697438f, + (float16_t)0.680600998f, (float16_t)-0.732654272f, + (float16_t)0.681724074f, (float16_t)-0.731609381f, + (float16_t)0.682845546f, (float16_t)-0.730562769f, + (float16_t)0.683965412f, (float16_t)-0.729514438f, + (float16_t)0.685083668f, (float16_t)-0.728464390f, + (float16_t)0.686200312f, (float16_t)-0.727412629f, + (float16_t)0.687315341f, (float16_t)-0.726359155f, + (float16_t)0.688428753f, (float16_t)-0.725303972f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.690650714f, (float16_t)-0.723188489f, + (float16_t)0.691759258f, (float16_t)-0.722128194f, + (float16_t)0.692866175f, (float16_t)-0.721066199f, + (float16_t)0.693971461f, (float16_t)-0.720002508f, + (float16_t)0.695075114f, (float16_t)-0.718937122f, + (float16_t)0.696177131f, (float16_t)-0.717870045f, + (float16_t)0.697277511f, (float16_t)-0.716801279f, + (float16_t)0.698376249f, (float16_t)-0.715730825f, + (float16_t)0.699473345f, (float16_t)-0.714658688f, + (float16_t)0.700568794f, (float16_t)-0.713584869f, + (float16_t)0.701662595f, (float16_t)-0.712509371f, + (float16_t)0.702754744f, (float16_t)-0.711432196f, + (float16_t)0.703845241f, (float16_t)-0.710353347f, + (float16_t)0.704934080f, (float16_t)-0.709272826f, + (float16_t)0.706021261f, (float16_t)-0.708190637f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.708190637f, (float16_t)-0.706021261f, + (float16_t)0.709272826f, (float16_t)-0.704934080f, + (float16_t)0.710353347f, (float16_t)-0.703845241f, + (float16_t)0.711432196f, (float16_t)-0.702754744f, + (float16_t)0.712509371f, (float16_t)-0.701662595f, + (float16_t)0.713584869f, (float16_t)-0.700568794f, + (float16_t)0.714658688f, (float16_t)-0.699473345f, + (float16_t)0.715730825f, (float16_t)-0.698376249f, + (float16_t)0.716801279f, (float16_t)-0.697277511f, + (float16_t)0.717870045f, (float16_t)-0.696177131f, + (float16_t)0.718937122f, (float16_t)-0.695075114f, + (float16_t)0.720002508f, (float16_t)-0.693971461f, + (float16_t)0.721066199f, (float16_t)-0.692866175f, + (float16_t)0.722128194f, (float16_t)-0.691759258f, + (float16_t)0.723188489f, (float16_t)-0.690650714f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.725303972f, (float16_t)-0.688428753f, + (float16_t)0.726359155f, (float16_t)-0.687315341f, + (float16_t)0.727412629f, (float16_t)-0.686200312f, + (float16_t)0.728464390f, (float16_t)-0.685083668f, + (float16_t)0.729514438f, (float16_t)-0.683965412f, + (float16_t)0.730562769f, (float16_t)-0.682845546f, + (float16_t)0.731609381f, (float16_t)-0.681724074f, + (float16_t)0.732654272f, (float16_t)-0.680600998f, + (float16_t)0.733697438f, (float16_t)-0.679476320f, + (float16_t)0.734738878f, (float16_t)-0.678350043f, + (float16_t)0.735778589f, (float16_t)-0.677222170f, + (float16_t)0.736816569f, (float16_t)-0.676092704f, + (float16_t)0.737852815f, (float16_t)-0.674961646f, + (float16_t)0.738887324f, (float16_t)-0.673829000f, + (float16_t)0.739920095f, (float16_t)-0.672694769f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.741980412f, (float16_t)-0.670421560f, + (float16_t)0.743007952f, (float16_t)-0.669282588f, + (float16_t)0.744033744f, (float16_t)-0.668142041f, + (float16_t)0.745057785f, (float16_t)-0.666999922f, + (float16_t)0.746080074f, (float16_t)-0.665856234f, + (float16_t)0.747100606f, (float16_t)-0.664710978f, + (float16_t)0.748119380f, (float16_t)-0.663564159f, + (float16_t)0.749136395f, (float16_t)-0.662415778f, + (float16_t)0.750151646f, (float16_t)-0.661265838f, + (float16_t)0.751165132f, (float16_t)-0.660114342f, + (float16_t)0.752176850f, (float16_t)-0.658961293f, + (float16_t)0.753186799f, (float16_t)-0.657806693f, + (float16_t)0.754194975f, (float16_t)-0.656650546f, + (float16_t)0.755201377f, (float16_t)-0.655492853f, + (float16_t)0.756206001f, (float16_t)-0.654333618f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.758209910f, (float16_t)-0.652010531f, + (float16_t)0.759209189f, (float16_t)-0.650846685f, + (float16_t)0.760206682f, (float16_t)-0.649681307f, + (float16_t)0.761202385f, (float16_t)-0.648514401f, + (float16_t)0.762196298f, (float16_t)-0.647345969f, + (float16_t)0.763188417f, (float16_t)-0.646176013f, + (float16_t)0.764178741f, (float16_t)-0.645004537f, + (float16_t)0.765167266f, (float16_t)-0.643831543f, + (float16_t)0.766153990f, (float16_t)-0.642657034f, + (float16_t)0.767138912f, (float16_t)-0.641481013f, + (float16_t)0.768122029f, (float16_t)-0.640303482f, + (float16_t)0.769103338f, (float16_t)-0.639124445f, + (float16_t)0.770082837f, (float16_t)-0.637943904f, + (float16_t)0.771060524f, (float16_t)-0.636761861f, + (float16_t)0.772036397f, (float16_t)-0.635578320f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.773982691f, (float16_t)-0.633206755f, + (float16_t)0.774953107f, (float16_t)-0.632018736f, + (float16_t)0.775921699f, (float16_t)-0.630829230f, + (float16_t)0.776888466f, (float16_t)-0.629638239f, + (float16_t)0.777853404f, (float16_t)-0.628445767f, + (float16_t)0.778816512f, (float16_t)-0.627251815f, + (float16_t)0.779777788f, (float16_t)-0.626056388f, + (float16_t)0.780737229f, (float16_t)-0.624859488f, + (float16_t)0.781694832f, (float16_t)-0.623661118f, + (float16_t)0.782650596f, (float16_t)-0.622461279f, + (float16_t)0.783604519f, (float16_t)-0.621259977f, + (float16_t)0.784556597f, (float16_t)-0.620057212f, + (float16_t)0.785506830f, (float16_t)-0.618852988f, + (float16_t)0.786455214f, (float16_t)-0.617647308f, + (float16_t)0.787401747f, (float16_t)-0.616440175f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.789289253f, (float16_t)-0.614021559f, + (float16_t)0.790230221f, (float16_t)-0.612810082f, + (float16_t)0.791169330f, (float16_t)-0.611597164f, + (float16_t)0.792106577f, (float16_t)-0.610382806f, + (float16_t)0.793041960f, (float16_t)-0.609167012f, + (float16_t)0.793975478f, (float16_t)-0.607949785f, + (float16_t)0.794907126f, (float16_t)-0.606731127f, + (float16_t)0.795836905f, (float16_t)-0.605511041f, + (float16_t)0.796764810f, (float16_t)-0.604289531f, + (float16_t)0.797690841f, (float16_t)-0.603066599f, + (float16_t)0.798614995f, (float16_t)-0.601842247f, + (float16_t)0.799537269f, (float16_t)-0.600616479f, + (float16_t)0.800457662f, (float16_t)-0.599389298f, + (float16_t)0.801376172f, (float16_t)-0.598160707f, + (float16_t)0.802292796f, (float16_t)-0.596930708f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.804120377f, (float16_t)-0.594466499f, + (float16_t)0.805031331f, (float16_t)-0.593232295f, + (float16_t)0.805940391f, (float16_t)-0.591996695f, + (float16_t)0.806847554f, (float16_t)-0.590759702f, + (float16_t)0.807752818f, (float16_t)-0.589521319f, + (float16_t)0.808656182f, (float16_t)-0.588281548f, + (float16_t)0.809557642f, (float16_t)-0.587040394f, + (float16_t)0.810457198f, (float16_t)-0.585797857f, + (float16_t)0.811354847f, (float16_t)-0.584553943f, + (float16_t)0.812250587f, (float16_t)-0.583308653f, + (float16_t)0.813144415f, (float16_t)-0.582061990f, + (float16_t)0.814036330f, (float16_t)-0.580813958f, + (float16_t)0.814926329f, (float16_t)-0.579564559f, + (float16_t)0.815814411f, (float16_t)-0.578313796f, + (float16_t)0.816700573f, (float16_t)-0.577061673f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.818467130f, (float16_t)-0.574553355f, + (float16_t)0.819347520f, (float16_t)-0.573297167f, + (float16_t)0.820225983f, (float16_t)-0.572039629f, + (float16_t)0.821102515f, (float16_t)-0.570780746f, + (float16_t)0.821977115f, (float16_t)-0.569520519f, + (float16_t)0.822849781f, (float16_t)-0.568258953f, + (float16_t)0.823720511f, (float16_t)-0.566996049f, + (float16_t)0.824589303f, (float16_t)-0.565731811f, + (float16_t)0.825456154f, (float16_t)-0.564466242f, + (float16_t)0.826321063f, (float16_t)-0.563199344f, + (float16_t)0.827184027f, (float16_t)-0.561931121f, + (float16_t)0.828045045f, (float16_t)-0.560661576f, + (float16_t)0.828904115f, (float16_t)-0.559390712f, + (float16_t)0.829761234f, (float16_t)-0.558118531f, + (float16_t)0.830616400f, (float16_t)-0.556845037f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.832320868f, (float16_t)-0.554294121f, + (float16_t)0.833170165f, (float16_t)-0.553016706f, + (float16_t)0.834017501f, (float16_t)-0.551737988f, + (float16_t)0.834862875f, (float16_t)-0.550457973f, + (float16_t)0.835706284f, (float16_t)-0.549176662f, + (float16_t)0.836547727f, (float16_t)-0.547894059f, + (float16_t)0.837387202f, (float16_t)-0.546610167f, + (float16_t)0.838224706f, (float16_t)-0.545324988f, + (float16_t)0.839060237f, (float16_t)-0.544038527f, + (float16_t)0.839893794f, (float16_t)-0.542750785f, + (float16_t)0.840725375f, (float16_t)-0.541461766f, + (float16_t)0.841554977f, (float16_t)-0.540171473f, + (float16_t)0.842382600f, (float16_t)-0.538879909f, + (float16_t)0.843208240f, (float16_t)-0.537587076f, + (float16_t)0.844031895f, (float16_t)-0.536292979f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.845673247f, (float16_t)-0.533701002f, + (float16_t)0.846490939f, (float16_t)-0.532403128f, + (float16_t)0.847306639f, (float16_t)-0.531104001f, + (float16_t)0.848120345f, (float16_t)-0.529803625f, + (float16_t)0.848932055f, (float16_t)-0.528502002f, + (float16_t)0.849741768f, (float16_t)-0.527199135f, + (float16_t)0.850549481f, (float16_t)-0.525895027f, + (float16_t)0.851355193f, (float16_t)-0.524589683f, + (float16_t)0.852158902f, (float16_t)-0.523283103f, + (float16_t)0.852960605f, (float16_t)-0.521975293f, + (float16_t)0.853760301f, (float16_t)-0.520666254f, + (float16_t)0.854557988f, (float16_t)-0.519355990f, + (float16_t)0.855353665f, (float16_t)-0.518044504f, + (float16_t)0.856147328f, (float16_t)-0.516731799f, + (float16_t)0.856938977f, (float16_t)-0.515417878f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.858516224f, (float16_t)-0.512786401f, + (float16_t)0.859301818f, (float16_t)-0.511468850f, + (float16_t)0.860085390f, (float16_t)-0.510150097f, + (float16_t)0.860866939f, (float16_t)-0.508830143f, + (float16_t)0.861646461f, (float16_t)-0.507508991f, + (float16_t)0.862423956f, (float16_t)-0.506186645f, + (float16_t)0.863199422f, (float16_t)-0.504863109f, + (float16_t)0.863972856f, (float16_t)-0.503538384f, + (float16_t)0.864744258f, (float16_t)-0.502212474f, + (float16_t)0.865513624f, (float16_t)-0.500885383f, + (float16_t)0.866280954f, (float16_t)-0.499557113f, + (float16_t)0.867046246f, (float16_t)-0.498227667f, + (float16_t)0.867809497f, (float16_t)-0.496897049f, + (float16_t)0.868570706f, (float16_t)-0.495565262f, + (float16_t)0.869329871f, (float16_t)-0.494232309f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.870842063f, (float16_t)-0.491562916f, + (float16_t)0.871595087f, (float16_t)-0.490226483f, + (float16_t)0.872346059f, (float16_t)-0.488888897f, + (float16_t)0.873094978f, (float16_t)-0.487550160f, + (float16_t)0.873841843f, (float16_t)-0.486210276f, + (float16_t)0.874586652f, (float16_t)-0.484869248f, + (float16_t)0.875329403f, (float16_t)-0.483527079f, + (float16_t)0.876070094f, (float16_t)-0.482183772f, + (float16_t)0.876808724f, (float16_t)-0.480839331f, + (float16_t)0.877545290f, (float16_t)-0.479493758f, + (float16_t)0.878279792f, (float16_t)-0.478147056f, + (float16_t)0.879012226f, (float16_t)-0.476799230f, + (float16_t)0.879742593f, (float16_t)-0.475450282f, + (float16_t)0.880470889f, (float16_t)-0.474100215f, + (float16_t)0.881197113f, (float16_t)-0.472749032f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.882643340f, (float16_t)-0.470043332f, + (float16_t)0.883363339f, (float16_t)-0.468688822f, + (float16_t)0.884081259f, (float16_t)-0.467333209f, + (float16_t)0.884797098f, (float16_t)-0.465976496f, + (float16_t)0.885510856f, (float16_t)-0.464618686f, + (float16_t)0.886222530f, (float16_t)-0.463259784f, + (float16_t)0.886932119f, (float16_t)-0.461899791f, + (float16_t)0.887639620f, (float16_t)-0.460538711f, + (float16_t)0.888345033f, (float16_t)-0.459176548f, + (float16_t)0.889048356f, (float16_t)-0.457813304f, + (float16_t)0.889749586f, (float16_t)-0.456448982f, + (float16_t)0.890448723f, (float16_t)-0.455083587f, + (float16_t)0.891145765f, (float16_t)-0.453717121f, + (float16_t)0.891840709f, (float16_t)-0.452349587f, + (float16_t)0.892533555f, (float16_t)-0.450980989f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.893912945f, (float16_t)-0.448240612f, + (float16_t)0.894599486f, (float16_t)-0.446868840f, + (float16_t)0.895283921f, (float16_t)-0.445496017f, + (float16_t)0.895966250f, (float16_t)-0.444122145f, + (float16_t)0.896646470f, (float16_t)-0.442747228f, + (float16_t)0.897324581f, (float16_t)-0.441371269f, + (float16_t)0.898000580f, (float16_t)-0.439994271f, + (float16_t)0.898674466f, (float16_t)-0.438616239f, + (float16_t)0.899346237f, (float16_t)-0.437237174f, + (float16_t)0.900015892f, (float16_t)-0.435857080f, + (float16_t)0.900683429f, (float16_t)-0.434475961f, + (float16_t)0.901348847f, (float16_t)-0.433093819f, + (float16_t)0.902012144f, (float16_t)-0.431710658f, + (float16_t)0.902673318f, (float16_t)-0.430326481f, + (float16_t)0.903332368f, (float16_t)-0.428941292f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.904644091f, (float16_t)-0.426167889f, + (float16_t)0.905296759f, (float16_t)-0.424779681f, + (float16_t)0.905947298f, (float16_t)-0.423390474f, + (float16_t)0.906595705f, (float16_t)-0.422000271f, + (float16_t)0.907241978f, (float16_t)-0.420609074f, + (float16_t)0.907886116f, (float16_t)-0.419216888f, + (float16_t)0.908528119f, (float16_t)-0.417823716f, + (float16_t)0.909167983f, (float16_t)-0.416429560f, + (float16_t)0.909805708f, (float16_t)-0.415034424f, + (float16_t)0.910441292f, (float16_t)-0.413638312f, + (float16_t)0.911074734f, (float16_t)-0.412241227f, + (float16_t)0.911706032f, (float16_t)-0.410843171f, + (float16_t)0.912335185f, (float16_t)-0.409444149f, + (float16_t)0.912962190f, (float16_t)-0.408044163f, + (float16_t)0.913587048f, (float16_t)-0.406643217f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.914830312f, (float16_t)-0.403838458f, + (float16_t)0.915448716f, (float16_t)-0.402434651f, + (float16_t)0.916064966f, (float16_t)-0.401029897f, + (float16_t)0.916679060f, (float16_t)-0.399624200f, + (float16_t)0.917290997f, (float16_t)-0.398217562f, + (float16_t)0.917900776f, (float16_t)-0.396809987f, + (float16_t)0.918508394f, (float16_t)-0.395401479f, + (float16_t)0.919113852f, (float16_t)-0.393992040f, + (float16_t)0.919717146f, (float16_t)-0.392581674f, + (float16_t)0.920318277f, (float16_t)-0.391170384f, + (float16_t)0.920917242f, (float16_t)-0.389758174f, + (float16_t)0.921514039f, (float16_t)-0.388345047f, + (float16_t)0.922108669f, (float16_t)-0.386931006f, + (float16_t)0.922701128f, (float16_t)-0.385516054f, + (float16_t)0.923291417f, (float16_t)-0.384100195f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.924465474f, (float16_t)-0.381265769f, + (float16_t)0.925049241f, (float16_t)-0.379847209f, + (float16_t)0.925630831f, (float16_t)-0.378427755f, + (float16_t)0.926210242f, (float16_t)-0.377007410f, + (float16_t)0.926787474f, (float16_t)-0.375586178f, + (float16_t)0.927362526f, (float16_t)-0.374164063f, + (float16_t)0.927935395f, (float16_t)-0.372741067f, + (float16_t)0.928506080f, (float16_t)-0.371317194f, + (float16_t)0.929074581f, (float16_t)-0.369892447f, + (float16_t)0.929640896f, (float16_t)-0.368466830f, + (float16_t)0.930205023f, (float16_t)-0.367040346f, + (float16_t)0.930766961f, (float16_t)-0.365612998f, + (float16_t)0.931326709f, (float16_t)-0.364184790f, + (float16_t)0.931884266f, (float16_t)-0.362755724f, + (float16_t)0.932439629f, (float16_t)-0.361325806f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.933543773f, (float16_t)-0.358463421f, + (float16_t)0.934092550f, (float16_t)-0.357030961f, + (float16_t)0.934639130f, (float16_t)-0.355597662f, + (float16_t)0.935183510f, (float16_t)-0.354163525f, + (float16_t)0.935725689f, (float16_t)-0.352728556f, + (float16_t)0.936265667f, (float16_t)-0.351292756f, + (float16_t)0.936803442f, (float16_t)-0.349856130f, + (float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.937872376f, (float16_t)-0.346980411f, + (float16_t)0.938403534f, (float16_t)-0.345541325f, + (float16_t)0.938932484f, (float16_t)-0.344101426f, + (float16_t)0.939459224f, (float16_t)-0.342660717f, + (float16_t)0.939983753f, (float16_t)-0.341219202f, + (float16_t)0.940506071f, (float16_t)-0.339776884f, + (float16_t)0.941026175f, (float16_t)-0.338333767f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.942059740f, (float16_t)-0.335445147f, + (float16_t)0.942573198f, (float16_t)-0.333999651f, + (float16_t)0.943084437f, (float16_t)-0.332553370f, + (float16_t)0.943593458f, (float16_t)-0.331106306f, + (float16_t)0.944100258f, (float16_t)-0.329658463f, + (float16_t)0.944604837f, (float16_t)-0.328209844f, + (float16_t)0.945107193f, (float16_t)-0.326760452f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.946105232f, (float16_t)-0.323859367f, + (float16_t)0.946600913f, (float16_t)-0.322407679f, + (float16_t)0.947094366f, (float16_t)-0.320955232f, + (float16_t)0.947585591f, (float16_t)-0.319502031f, + (float16_t)0.948074586f, (float16_t)-0.318048077f, + (float16_t)0.948561350f, (float16_t)-0.316593376f, + (float16_t)0.949045882f, (float16_t)-0.315137929f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.950008245f, (float16_t)-0.312224814f, + (float16_t)0.950486074f, (float16_t)-0.310767153f, + (float16_t)0.950961666f, (float16_t)-0.309308760f, + (float16_t)0.951435021f, (float16_t)-0.307849640f, + (float16_t)0.951906137f, (float16_t)-0.306389795f, + (float16_t)0.952375013f, (float16_t)-0.304929230f, + (float16_t)0.952841648f, (float16_t)-0.303467947f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.953768190f, (float16_t)-0.300543241f, + (float16_t)0.954228095f, (float16_t)-0.299079826f, + (float16_t)0.954685755f, (float16_t)-0.297615707f, + (float16_t)0.955141168f, (float16_t)-0.296150888f, + (float16_t)0.955594334f, (float16_t)-0.294685372f, + (float16_t)0.956045251f, (float16_t)-0.293219163f, + (float16_t)0.956493919f, (float16_t)-0.291752263f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.957384501f, (float16_t)-0.288816408f, + (float16_t)0.957826413f, (float16_t)-0.287347460f, + (float16_t)0.958266071f, (float16_t)-0.285877835f, + (float16_t)0.958703475f, (float16_t)-0.284407537f, + (float16_t)0.959138622f, (float16_t)-0.282936570f, + (float16_t)0.959571513f, (float16_t)-0.281464938f, + (float16_t)0.960002146f, (float16_t)-0.279992643f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.960856633f, (float16_t)-0.277046080f, + (float16_t)0.961280486f, (float16_t)-0.275571819f, + (float16_t)0.961702077f, (float16_t)-0.274096910f, + (float16_t)0.962121404f, (float16_t)-0.272621355f, + (float16_t)0.962538468f, (float16_t)-0.271145160f, + (float16_t)0.962953267f, (float16_t)-0.269668326f, + (float16_t)0.963365800f, (float16_t)-0.268190857f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.964184064f, (float16_t)-0.265234030f, + (float16_t)0.964589793f, (float16_t)-0.263754679f, + (float16_t)0.964993253f, (float16_t)-0.262274707f, + (float16_t)0.965394442f, (float16_t)-0.260794118f, + (float16_t)0.965793359f, (float16_t)-0.259312915f, + (float16_t)0.966190003f, (float16_t)-0.257831102f, + (float16_t)0.966584374f, (float16_t)-0.256348682f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.967366292f, (float16_t)-0.253382037f, + (float16_t)0.967753837f, (float16_t)-0.251897818f, + (float16_t)0.968139105f, (float16_t)-0.250413007f, + (float16_t)0.968522094f, (float16_t)-0.248927606f, + (float16_t)0.968902805f, (float16_t)-0.247441619f, + (float16_t)0.969281235f, (float16_t)-0.245955050f, + (float16_t)0.969657385f, (float16_t)-0.244467903f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.970402839f, (float16_t)-0.241491885f, + (float16_t)0.970772141f, (float16_t)-0.240003022f, + (float16_t)0.971139158f, (float16_t)-0.238513595f, + (float16_t)0.971503891f, (float16_t)-0.237023606f, + (float16_t)0.971866337f, (float16_t)-0.235533059f, + (float16_t)0.972226497f, (float16_t)-0.234041959f, + (float16_t)0.972584369f, (float16_t)-0.232550307f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.973293246f, (float16_t)-0.229565366f, + (float16_t)0.973644250f, (float16_t)-0.228072083f, + (float16_t)0.973992962f, (float16_t)-0.226578264f, + (float16_t)0.974339383f, (float16_t)-0.225083911f, + (float16_t)0.974683511f, (float16_t)-0.223589029f, + (float16_t)0.975025345f, (float16_t)-0.222093621f, + (float16_t)0.975364885f, (float16_t)-0.220597690f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.976037079f, (float16_t)-0.217604275f, + (float16_t)0.976369731f, (float16_t)-0.216106797f, + (float16_t)0.976700086f, (float16_t)-0.214608811f, + (float16_t)0.977028143f, (float16_t)-0.213110320f, + (float16_t)0.977353900f, (float16_t)-0.211611327f, + (float16_t)0.977677358f, (float16_t)-0.210111837f, + (float16_t)0.977998515f, (float16_t)-0.208611852f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.978633924f, (float16_t)-0.205610413f, + (float16_t)0.978948175f, (float16_t)-0.204108966f, + (float16_t)0.979260123f, (float16_t)-0.202607039f, + (float16_t)0.979569766f, (float16_t)-0.201104635f, + (float16_t)0.979877104f, (float16_t)-0.199601758f, + (float16_t)0.980182136f, (float16_t)-0.198098411f, + (float16_t)0.980484862f, (float16_t)-0.196594598f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.981083391f, (float16_t)-0.193585587f, + (float16_t)0.981379193f, (float16_t)-0.192080397f, + (float16_t)0.981672686f, (float16_t)-0.190574755f, + (float16_t)0.981963869f, (float16_t)-0.189068664f, + (float16_t)0.982252741f, (float16_t)-0.187562129f, + (float16_t)0.982539302f, (float16_t)-0.186055152f, + (float16_t)0.982823551f, (float16_t)-0.184547737f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.983385110f, (float16_t)-0.181531608f, + (float16_t)0.983662419f, (float16_t)-0.180022901f, + (float16_t)0.983937413f, (float16_t)-0.178513771f, + (float16_t)0.984210092f, (float16_t)-0.177004220f, + (float16_t)0.984480455f, (float16_t)-0.175494253f, + (float16_t)0.984748502f, (float16_t)-0.173983873f, + (float16_t)0.985014231f, (float16_t)-0.172473084f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.985538735f, (float16_t)-0.169450291f, + (float16_t)0.985797509f, (float16_t)-0.167938295f, + (float16_t)0.986053963f, (float16_t)-0.166425904f, + (float16_t)0.986308097f, (float16_t)-0.164913120f, + (float16_t)0.986559910f, (float16_t)-0.163399949f, + (float16_t)0.986809402f, (float16_t)-0.161886394f, + (float16_t)0.987056571f, (float16_t)-0.160372457f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.987543942f, (float16_t)-0.157343456f, + (float16_t)0.987784142f, (float16_t)-0.155828398f, + (float16_t)0.988022017f, (float16_t)-0.154312973f, + (float16_t)0.988257568f, (float16_t)-0.152797185f, + (float16_t)0.988490793f, (float16_t)-0.151281038f, + (float16_t)0.988721692f, (float16_t)-0.149764535f, + (float16_t)0.988950265f, (float16_t)-0.148247679f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.989400428f, (float16_t)-0.145212925f, + (float16_t)0.989622017f, (float16_t)-0.143695033f, + (float16_t)0.989841278f, (float16_t)-0.142176804f, + (float16_t)0.990058210f, (float16_t)-0.140658239f, + (float16_t)0.990272812f, (float16_t)-0.139139344f, + (float16_t)0.990485084f, (float16_t)-0.137620122f, + (float16_t)0.990695025f, (float16_t)-0.136100575f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.991107914f, (float16_t)-0.133060525f, + (float16_t)0.991310860f, (float16_t)-0.131540029f, + (float16_t)0.991511473f, (float16_t)-0.130019223f, + (float16_t)0.991709754f, (float16_t)-0.128498111f, + (float16_t)0.991905700f, (float16_t)-0.126976696f, + (float16_t)0.992099313f, (float16_t)-0.125454983f, + (float16_t)0.992290591f, (float16_t)-0.123932975f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.992666142f, (float16_t)-0.120888087f, + (float16_t)0.992850414f, (float16_t)-0.119365215f, + (float16_t)0.993032350f, (float16_t)-0.117842062f, + (float16_t)0.993211949f, (float16_t)-0.116318631f, + (float16_t)0.993389211f, (float16_t)-0.114794927f, + (float16_t)0.993564136f, (float16_t)-0.113270952f, + (float16_t)0.993736722f, (float16_t)-0.111746711f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.994074879f, (float16_t)-0.108697444f, + (float16_t)0.994240449f, (float16_t)-0.107172425f, + (float16_t)0.994403680f, (float16_t)-0.105647154f, + (float16_t)0.994564571f, (float16_t)-0.104121634f, + (float16_t)0.994723121f, (float16_t)-0.102595869f, + (float16_t)0.994879331f, (float16_t)-0.101069863f, + (float16_t)0.995033199f, (float16_t)-0.099543619f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.995333912f, (float16_t)-0.096490431f, + (float16_t)0.995480755f, (float16_t)-0.094963495f, + (float16_t)0.995625256f, (float16_t)-0.093436336f, + (float16_t)0.995767414f, (float16_t)-0.091908956f, + (float16_t)0.995907229f, (float16_t)-0.090381361f, + (float16_t)0.996044701f, (float16_t)-0.088853553f, + (float16_t)0.996179829f, (float16_t)-0.087325535f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.996443051f, (float16_t)-0.084268888f, + (float16_t)0.996571146f, (float16_t)-0.082740265f, + (float16_t)0.996696895f, (float16_t)-0.081211447f, + (float16_t)0.996820299f, (float16_t)-0.079682438f, + (float16_t)0.996941358f, (float16_t)-0.078153242f, + (float16_t)0.997060070f, (float16_t)-0.076623861f, + (float16_t)0.997176437f, (float16_t)-0.075094301f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.997402130f, (float16_t)-0.072034653f, + (float16_t)0.997511456f, (float16_t)-0.070504573f, + (float16_t)0.997618435f, (float16_t)-0.068974328f, + (float16_t)0.997723067f, (float16_t)-0.067443920f, + (float16_t)0.997825350f, (float16_t)-0.065913353f, + (float16_t)0.997925286f, (float16_t)-0.064382631f, + (float16_t)0.998022874f, (float16_t)-0.062851758f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.998211003f, (float16_t)-0.059789571f, + (float16_t)0.998301545f, (float16_t)-0.058258265f, + (float16_t)0.998389737f, (float16_t)-0.056726821f, + (float16_t)0.998475581f, (float16_t)-0.055195244f, + (float16_t)0.998559074f, (float16_t)-0.053663538f, + (float16_t)0.998640218f, (float16_t)-0.052131705f, + (float16_t)0.998719012f, (float16_t)-0.050599749f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.998869550f, (float16_t)-0.047535484f, + (float16_t)0.998941293f, (float16_t)-0.046003182f, + (float16_t)0.999010686f, (float16_t)-0.044470772f, + (float16_t)0.999077728f, (float16_t)-0.042938257f, + (float16_t)0.999142419f, (float16_t)-0.041405641f, + (float16_t)0.999204759f, (float16_t)-0.039872928f, + (float16_t)0.999264747f, (float16_t)-0.038340120f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.999377670f, (float16_t)-0.035274239f, + (float16_t)0.999430605f, (float16_t)-0.033741172f, + (float16_t)0.999481187f, (float16_t)-0.032208025f, + (float16_t)0.999529418f, (float16_t)-0.030674803f, + (float16_t)0.999575296f, (float16_t)-0.029141509f, + (float16_t)0.999618822f, (float16_t)-0.027608146f, + (float16_t)0.999659997f, (float16_t)-0.026074718f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999735288f, (float16_t)-0.023007681f, + (float16_t)0.999769405f, (float16_t)-0.021474080f, + (float16_t)0.999801170f, (float16_t)-0.019940429f, + (float16_t)0.999830582f, (float16_t)-0.018406730f, + (float16_t)0.999857641f, (float16_t)-0.016872988f, + (float16_t)0.999882347f, (float16_t)-0.015339206f, + (float16_t)0.999904701f, (float16_t)-0.013805389f, + (float16_t)0.999924702f, (float16_t)-0.012271538f, + (float16_t)0.999942350f, (float16_t)-0.010737659f, + (float16_t)0.999957645f, (float16_t)-0.009203755f, + (float16_t)0.999970586f, (float16_t)-0.007669829f, + (float16_t)0.999981175f, (float16_t)-0.006135885f, + (float16_t)0.999989411f, (float16_t)-0.004601926f, + (float16_t)0.999995294f, (float16_t)-0.003067957f, + (float16_t)0.999998823f, (float16_t)-0.001533980f +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_32) +/** + @par + Example code for Floating-point RFFT Twiddle factors Generation: + @par +
TW = exp(pi/2*i-2*pi*i*[0:L/2-1]/L).' 
+ @par + Real and Imag values are in interleaved fashion +*/ +const float16_t twiddleCoefF16_rfft_32[32] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.195090322f, (float16_t)-0.980785280f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_64) +const float16_t twiddleCoefF16_rfft_64[64] = { + (float16_t)0.000000000000000f, (float16_t)1.000000000000000f, + (float16_t)0.098017140329561f, (float16_t)0.995184726672197f, + (float16_t)0.195090322016128f, (float16_t)0.980785280403230f, + (float16_t)0.290284677254462f, (float16_t)0.956940335732209f, + (float16_t)0.382683432365090f, (float16_t)0.923879532511287f, + (float16_t)0.471396736825998f, (float16_t)0.881921264348355f, + (float16_t)0.555570233019602f, (float16_t)0.831469612302545f, + (float16_t)0.634393284163645f, (float16_t)0.773010453362737f, + (float16_t)0.707106781186547f, (float16_t)0.707106781186548f, + (float16_t)0.773010453362737f, (float16_t)0.634393284163645f, + (float16_t)0.831469612302545f, (float16_t)0.555570233019602f, + (float16_t)0.881921264348355f, (float16_t)0.471396736825998f, + (float16_t)0.923879532511287f, (float16_t)0.382683432365090f, + (float16_t)0.956940335732209f, (float16_t)0.290284677254462f, + (float16_t)0.980785280403230f, (float16_t)0.195090322016128f, + (float16_t)0.995184726672197f, (float16_t)0.098017140329561f, + (float16_t)1.000000000000000f, (float16_t)0.000000000000000f, + (float16_t)0.995184726672197f, (float16_t)-0.098017140329561f, + (float16_t)0.980785280403230f, (float16_t)-0.195090322016128f, + (float16_t)0.956940335732209f, (float16_t)-0.290284677254462f, + (float16_t)0.923879532511287f, (float16_t)-0.382683432365090f, + (float16_t)0.881921264348355f, (float16_t)-0.471396736825998f, + (float16_t)0.831469612302545f, (float16_t)-0.555570233019602f, + (float16_t)0.773010453362737f, (float16_t)-0.634393284163645f, + (float16_t)0.707106781186548f, (float16_t)-0.707106781186547f, + (float16_t)0.634393284163645f, (float16_t)-0.773010453362737f, + (float16_t)0.555570233019602f, (float16_t)-0.831469612302545f, + (float16_t)0.471396736825998f, (float16_t)-0.881921264348355f, + (float16_t)0.382683432365090f, (float16_t)-0.923879532511287f, + (float16_t)0.290284677254462f, (float16_t)-0.956940335732209f, + (float16_t)0.195090322016129f, (float16_t)-0.980785280403230f, + (float16_t)0.098017140329561f, (float16_t)-0.995184726672197f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_128) +const float16_t twiddleCoefF16_rfft_128[128] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.049067674f, (float16_t)-0.998795456f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_256) +const float16_t twiddleCoefF16_rfft_256[256] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.024541229f, (float16_t)-0.999698819f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_512) +const float16_t twiddleCoefF16_rfft_512[512] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.460538711f, (float16_t)0.887639620f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.482183772f, (float16_t)0.876070094f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.503538384f, (float16_t)0.863972856f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.524589683f, (float16_t)0.851355193f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.545324988f, (float16_t)0.838224706f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.565731811f, (float16_t)0.824589303f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.585797857f, (float16_t)0.810457198f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.605511041f, (float16_t)0.795836905f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.624859488f, (float16_t)0.780737229f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.795836905f, (float16_t)0.605511041f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.851355193f, (float16_t)0.524589683f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.863972856f, (float16_t)0.503538384f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999924702f, (float16_t)-0.012271538f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.928506080f, (float16_t)-0.371317194f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.919113852f, (float16_t)-0.393992040f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.909167983f, (float16_t)-0.416429560f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.898674466f, (float16_t)-0.438616239f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.887639620f, (float16_t)-0.460538711f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.876070094f, (float16_t)-0.482183772f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.863972856f, (float16_t)-0.503538384f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.851355193f, (float16_t)-0.524589683f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.838224706f, (float16_t)-0.545324988f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.824589303f, (float16_t)-0.565731811f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.810457198f, (float16_t)-0.585797857f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.795836905f, (float16_t)-0.605511041f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.780737229f, (float16_t)-0.624859488f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.765167266f, (float16_t)-0.643831543f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.749136395f, (float16_t)-0.662415778f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.732654272f, (float16_t)-0.680600998f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.715730825f, (float16_t)-0.698376249f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.698376249f, (float16_t)-0.715730825f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.680600998f, (float16_t)-0.732654272f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.662415778f, (float16_t)-0.749136395f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.643831543f, (float16_t)-0.765167266f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.624859488f, (float16_t)-0.780737229f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.605511041f, (float16_t)-0.795836905f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.585797857f, (float16_t)-0.810457198f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.565731811f, (float16_t)-0.824589303f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.545324988f, (float16_t)-0.838224706f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.524589683f, (float16_t)-0.851355193f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.503538384f, (float16_t)-0.863972856f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.482183772f, (float16_t)-0.876070094f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.460538711f, (float16_t)-0.887639620f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.438616239f, (float16_t)-0.898674466f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.416429560f, (float16_t)-0.909167983f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.393992040f, (float16_t)-0.919113852f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.371317194f, (float16_t)-0.928506080f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.012271538f, (float16_t)-0.999924702f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_1024) +const float16_t twiddleCoefF16_rfft_1024[1024] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.006135885f, (float16_t)0.999981175f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.018406730f, (float16_t)0.999830582f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.030674803f, (float16_t)0.999529418f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.042938257f, (float16_t)0.999077728f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.055195244f, (float16_t)0.998475581f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.067443920f, (float16_t)0.997723067f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.079682438f, (float16_t)0.996820299f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.091908956f, (float16_t)0.995767414f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.104121634f, (float16_t)0.994564571f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.116318631f, (float16_t)0.993211949f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.128498111f, (float16_t)0.991709754f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.140658239f, (float16_t)0.990058210f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.152797185f, (float16_t)0.988257568f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.164913120f, (float16_t)0.986308097f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.177004220f, (float16_t)0.984210092f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.189068664f, (float16_t)0.981963869f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.201104635f, (float16_t)0.979569766f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.213110320f, (float16_t)0.977028143f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.225083911f, (float16_t)0.974339383f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.237023606f, (float16_t)0.971503891f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.248927606f, (float16_t)0.968522094f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.260794118f, (float16_t)0.965394442f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.272621355f, (float16_t)0.962121404f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.284407537f, (float16_t)0.958703475f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.296150888f, (float16_t)0.955141168f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.307849640f, (float16_t)0.951435021f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.319502031f, (float16_t)0.947585591f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.331106306f, (float16_t)0.943593458f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.342660717f, (float16_t)0.939459224f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.354163525f, (float16_t)0.935183510f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.365612998f, (float16_t)0.930766961f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.377007410f, (float16_t)0.926210242f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.388345047f, (float16_t)0.921514039f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.399624200f, (float16_t)0.916679060f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.410843171f, (float16_t)0.911706032f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.422000271f, (float16_t)0.906595705f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.433093819f, (float16_t)0.901348847f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.444122145f, (float16_t)0.895966250f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.455083587f, (float16_t)0.890448723f, + (float16_t)0.460538711f, (float16_t)0.887639620f, + (float16_t)0.465976496f, (float16_t)0.884797098f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.476799230f, (float16_t)0.879012226f, + (float16_t)0.482183772f, (float16_t)0.876070094f, + (float16_t)0.487550160f, (float16_t)0.873094978f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.498227667f, (float16_t)0.867046246f, + (float16_t)0.503538384f, (float16_t)0.863972856f, + (float16_t)0.508830143f, (float16_t)0.860866939f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.519355990f, (float16_t)0.854557988f, + (float16_t)0.524589683f, (float16_t)0.851355193f, + (float16_t)0.529803625f, (float16_t)0.848120345f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.540171473f, (float16_t)0.841554977f, + (float16_t)0.545324988f, (float16_t)0.838224706f, + (float16_t)0.550457973f, (float16_t)0.834862875f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.560661576f, (float16_t)0.828045045f, + (float16_t)0.565731811f, (float16_t)0.824589303f, + (float16_t)0.570780746f, (float16_t)0.821102515f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.580813958f, (float16_t)0.814036330f, + (float16_t)0.585797857f, (float16_t)0.810457198f, + (float16_t)0.590759702f, (float16_t)0.806847554f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.600616479f, (float16_t)0.799537269f, + (float16_t)0.605511041f, (float16_t)0.795836905f, + (float16_t)0.610382806f, (float16_t)0.792106577f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.620057212f, (float16_t)0.784556597f, + (float16_t)0.624859488f, (float16_t)0.780737229f, + (float16_t)0.629638239f, (float16_t)0.776888466f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.639124445f, (float16_t)0.769103338f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.648514401f, (float16_t)0.761202385f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.657806693f, (float16_t)0.753186799f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.666999922f, (float16_t)0.745057785f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.676092704f, (float16_t)0.736816569f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.685083668f, (float16_t)0.728464390f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.693971461f, (float16_t)0.720002508f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.702754744f, (float16_t)0.711432196f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.711432196f, (float16_t)0.702754744f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.720002508f, (float16_t)0.693971461f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.728464390f, (float16_t)0.685083668f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.736816569f, (float16_t)0.676092704f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.745057785f, (float16_t)0.666999922f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.753186799f, (float16_t)0.657806693f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.761202385f, (float16_t)0.648514401f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.769103338f, (float16_t)0.639124445f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.776888466f, (float16_t)0.629638239f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.784556597f, (float16_t)0.620057212f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.792106577f, (float16_t)0.610382806f, + (float16_t)0.795836905f, (float16_t)0.605511041f, + (float16_t)0.799537269f, (float16_t)0.600616479f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.806847554f, (float16_t)0.590759702f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.814036330f, (float16_t)0.580813958f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.821102515f, (float16_t)0.570780746f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.828045045f, (float16_t)0.560661576f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.834862875f, (float16_t)0.550457973f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.841554977f, (float16_t)0.540171473f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.848120345f, (float16_t)0.529803625f, + (float16_t)0.851355193f, (float16_t)0.524589683f, + (float16_t)0.854557988f, (float16_t)0.519355990f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.860866939f, (float16_t)0.508830143f, + (float16_t)0.863972856f, (float16_t)0.503538384f, + (float16_t)0.867046246f, (float16_t)0.498227667f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.873094978f, (float16_t)0.487550160f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.879012226f, (float16_t)0.476799230f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.884797098f, (float16_t)0.465976496f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.890448723f, (float16_t)0.455083587f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.895966250f, (float16_t)0.444122145f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.901348847f, (float16_t)0.433093819f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.906595705f, (float16_t)0.422000271f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.911706032f, (float16_t)0.410843171f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.916679060f, (float16_t)0.399624200f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.921514039f, (float16_t)0.388345047f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.926210242f, (float16_t)0.377007410f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.930766961f, (float16_t)0.365612998f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.935183510f, (float16_t)0.354163525f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.939459224f, (float16_t)0.342660717f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.943593458f, (float16_t)0.331106306f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.947585591f, (float16_t)0.319502031f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.951435021f, (float16_t)0.307849640f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.955141168f, (float16_t)0.296150888f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.958703475f, (float16_t)0.284407537f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.962121404f, (float16_t)0.272621355f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.965394442f, (float16_t)0.260794118f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.968522094f, (float16_t)0.248927606f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.971503891f, (float16_t)0.237023606f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.974339383f, (float16_t)0.225083911f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.977028143f, (float16_t)0.213110320f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.979569766f, (float16_t)0.201104635f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.981963869f, (float16_t)0.189068664f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.984210092f, (float16_t)0.177004220f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.986308097f, (float16_t)0.164913120f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.988257568f, (float16_t)0.152797185f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.990058210f, (float16_t)0.140658239f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.991709754f, (float16_t)0.128498111f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.993211949f, (float16_t)0.116318631f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.994564571f, (float16_t)0.104121634f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.995767414f, (float16_t)0.091908956f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.996820299f, (float16_t)0.079682438f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.997723067f, (float16_t)0.067443920f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.998475581f, (float16_t)0.055195244f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.999077728f, (float16_t)0.042938257f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.999529418f, (float16_t)0.030674803f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999830582f, (float16_t)0.018406730f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)0.999981175f, (float16_t)0.006135885f, + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999981175f, (float16_t)-0.006135885f, + (float16_t)0.999924702f, (float16_t)-0.012271538f, + (float16_t)0.999830582f, (float16_t)-0.018406730f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999529418f, (float16_t)-0.030674803f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.999077728f, (float16_t)-0.042938257f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.998475581f, (float16_t)-0.055195244f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.997723067f, (float16_t)-0.067443920f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.996820299f, (float16_t)-0.079682438f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.995767414f, (float16_t)-0.091908956f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.994564571f, (float16_t)-0.104121634f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.993211949f, (float16_t)-0.116318631f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.991709754f, (float16_t)-0.128498111f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.990058210f, (float16_t)-0.140658239f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.988257568f, (float16_t)-0.152797185f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.986308097f, (float16_t)-0.164913120f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.984210092f, (float16_t)-0.177004220f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.981963869f, (float16_t)-0.189068664f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.979569766f, (float16_t)-0.201104635f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.977028143f, (float16_t)-0.213110320f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.974339383f, (float16_t)-0.225083911f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.971503891f, (float16_t)-0.237023606f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.968522094f, (float16_t)-0.248927606f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.965394442f, (float16_t)-0.260794118f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.962121404f, (float16_t)-0.272621355f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.958703475f, (float16_t)-0.284407537f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.955141168f, (float16_t)-0.296150888f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.951435021f, (float16_t)-0.307849640f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.947585591f, (float16_t)-0.319502031f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.943593458f, (float16_t)-0.331106306f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.939459224f, (float16_t)-0.342660717f, + (float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.935183510f, (float16_t)-0.354163525f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.930766961f, (float16_t)-0.365612998f, + (float16_t)0.928506080f, (float16_t)-0.371317194f, + (float16_t)0.926210242f, (float16_t)-0.377007410f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.921514039f, (float16_t)-0.388345047f, + (float16_t)0.919113852f, (float16_t)-0.393992040f, + (float16_t)0.916679060f, (float16_t)-0.399624200f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.911706032f, (float16_t)-0.410843171f, + (float16_t)0.909167983f, (float16_t)-0.416429560f, + (float16_t)0.906595705f, (float16_t)-0.422000271f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.901348847f, (float16_t)-0.433093819f, + (float16_t)0.898674466f, (float16_t)-0.438616239f, + (float16_t)0.895966250f, (float16_t)-0.444122145f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.890448723f, (float16_t)-0.455083587f, + (float16_t)0.887639620f, (float16_t)-0.460538711f, + (float16_t)0.884797098f, (float16_t)-0.465976496f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.879012226f, (float16_t)-0.476799230f, + (float16_t)0.876070094f, (float16_t)-0.482183772f, + (float16_t)0.873094978f, (float16_t)-0.487550160f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.867046246f, (float16_t)-0.498227667f, + (float16_t)0.863972856f, (float16_t)-0.503538384f, + (float16_t)0.860866939f, (float16_t)-0.508830143f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.854557988f, (float16_t)-0.519355990f, + (float16_t)0.851355193f, (float16_t)-0.524589683f, + (float16_t)0.848120345f, (float16_t)-0.529803625f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.841554977f, (float16_t)-0.540171473f, + (float16_t)0.838224706f, (float16_t)-0.545324988f, + (float16_t)0.834862875f, (float16_t)-0.550457973f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.828045045f, (float16_t)-0.560661576f, + (float16_t)0.824589303f, (float16_t)-0.565731811f, + (float16_t)0.821102515f, (float16_t)-0.570780746f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.814036330f, (float16_t)-0.580813958f, + (float16_t)0.810457198f, (float16_t)-0.585797857f, + (float16_t)0.806847554f, (float16_t)-0.590759702f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.799537269f, (float16_t)-0.600616479f, + (float16_t)0.795836905f, (float16_t)-0.605511041f, + (float16_t)0.792106577f, (float16_t)-0.610382806f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.784556597f, (float16_t)-0.620057212f, + (float16_t)0.780737229f, (float16_t)-0.624859488f, + (float16_t)0.776888466f, (float16_t)-0.629638239f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.769103338f, (float16_t)-0.639124445f, + (float16_t)0.765167266f, (float16_t)-0.643831543f, + (float16_t)0.761202385f, (float16_t)-0.648514401f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.753186799f, (float16_t)-0.657806693f, + (float16_t)0.749136395f, (float16_t)-0.662415778f, + (float16_t)0.745057785f, (float16_t)-0.666999922f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.736816569f, (float16_t)-0.676092704f, + (float16_t)0.732654272f, (float16_t)-0.680600998f, + (float16_t)0.728464390f, (float16_t)-0.685083668f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.720002508f, (float16_t)-0.693971461f, + (float16_t)0.715730825f, (float16_t)-0.698376249f, + (float16_t)0.711432196f, (float16_t)-0.702754744f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.702754744f, (float16_t)-0.711432196f, + (float16_t)0.698376249f, (float16_t)-0.715730825f, + (float16_t)0.693971461f, (float16_t)-0.720002508f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.685083668f, (float16_t)-0.728464390f, + (float16_t)0.680600998f, (float16_t)-0.732654272f, + (float16_t)0.676092704f, (float16_t)-0.736816569f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.666999922f, (float16_t)-0.745057785f, + (float16_t)0.662415778f, (float16_t)-0.749136395f, + (float16_t)0.657806693f, (float16_t)-0.753186799f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.648514401f, (float16_t)-0.761202385f, + (float16_t)0.643831543f, (float16_t)-0.765167266f, + (float16_t)0.639124445f, (float16_t)-0.769103338f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.629638239f, (float16_t)-0.776888466f, + (float16_t)0.624859488f, (float16_t)-0.780737229f, + (float16_t)0.620057212f, (float16_t)-0.784556597f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.610382806f, (float16_t)-0.792106577f, + (float16_t)0.605511041f, (float16_t)-0.795836905f, + (float16_t)0.600616479f, (float16_t)-0.799537269f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.590759702f, (float16_t)-0.806847554f, + (float16_t)0.585797857f, (float16_t)-0.810457198f, + (float16_t)0.580813958f, (float16_t)-0.814036330f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.570780746f, (float16_t)-0.821102515f, + (float16_t)0.565731811f, (float16_t)-0.824589303f, + (float16_t)0.560661576f, (float16_t)-0.828045045f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.550457973f, (float16_t)-0.834862875f, + (float16_t)0.545324988f, (float16_t)-0.838224706f, + (float16_t)0.540171473f, (float16_t)-0.841554977f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.529803625f, (float16_t)-0.848120345f, + (float16_t)0.524589683f, (float16_t)-0.851355193f, + (float16_t)0.519355990f, (float16_t)-0.854557988f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.508830143f, (float16_t)-0.860866939f, + (float16_t)0.503538384f, (float16_t)-0.863972856f, + (float16_t)0.498227667f, (float16_t)-0.867046246f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.487550160f, (float16_t)-0.873094978f, + (float16_t)0.482183772f, (float16_t)-0.876070094f, + (float16_t)0.476799230f, (float16_t)-0.879012226f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.465976496f, (float16_t)-0.884797098f, + (float16_t)0.460538711f, (float16_t)-0.887639620f, + (float16_t)0.455083587f, (float16_t)-0.890448723f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.444122145f, (float16_t)-0.895966250f, + (float16_t)0.438616239f, (float16_t)-0.898674466f, + (float16_t)0.433093819f, (float16_t)-0.901348847f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.422000271f, (float16_t)-0.906595705f, + (float16_t)0.416429560f, (float16_t)-0.909167983f, + (float16_t)0.410843171f, (float16_t)-0.911706032f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.399624200f, (float16_t)-0.916679060f, + (float16_t)0.393992040f, (float16_t)-0.919113852f, + (float16_t)0.388345047f, (float16_t)-0.921514039f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.377007410f, (float16_t)-0.926210242f, + (float16_t)0.371317194f, (float16_t)-0.928506080f, + (float16_t)0.365612998f, (float16_t)-0.930766961f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.354163525f, (float16_t)-0.935183510f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.342660717f, (float16_t)-0.939459224f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.331106306f, (float16_t)-0.943593458f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.319502031f, (float16_t)-0.947585591f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.307849640f, (float16_t)-0.951435021f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.296150888f, (float16_t)-0.955141168f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.284407537f, (float16_t)-0.958703475f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.272621355f, (float16_t)-0.962121404f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.260794118f, (float16_t)-0.965394442f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.248927606f, (float16_t)-0.968522094f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.237023606f, (float16_t)-0.971503891f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.225083911f, (float16_t)-0.974339383f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.213110320f, (float16_t)-0.977028143f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.201104635f, (float16_t)-0.979569766f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.189068664f, (float16_t)-0.981963869f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.177004220f, (float16_t)-0.984210092f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.164913120f, (float16_t)-0.986308097f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.152797185f, (float16_t)-0.988257568f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.140658239f, (float16_t)-0.990058210f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.128498111f, (float16_t)-0.991709754f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.116318631f, (float16_t)-0.993211949f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.104121634f, (float16_t)-0.994564571f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.091908956f, (float16_t)-0.995767414f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.079682438f, (float16_t)-0.996820299f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.067443920f, (float16_t)-0.997723067f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.055195244f, (float16_t)-0.998475581f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.042938257f, (float16_t)-0.999077728f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.030674803f, (float16_t)-0.999529418f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.018406730f, (float16_t)-0.999830582f, + (float16_t)0.012271538f, (float16_t)-0.999924702f, + (float16_t)0.006135885f, (float16_t)-0.999981175f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_2048) +const float16_t twiddleCoefF16_rfft_2048[2048] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.003067957f, (float16_t)0.999995294f, + (float16_t)0.006135885f, (float16_t)0.999981175f, + (float16_t)0.009203755f, (float16_t)0.999957645f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.015339206f, (float16_t)0.999882347f, + (float16_t)0.018406730f, (float16_t)0.999830582f, + (float16_t)0.021474080f, (float16_t)0.999769405f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.027608146f, (float16_t)0.999618822f, + (float16_t)0.030674803f, (float16_t)0.999529418f, + (float16_t)0.033741172f, (float16_t)0.999430605f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.039872928f, (float16_t)0.999204759f, + (float16_t)0.042938257f, (float16_t)0.999077728f, + (float16_t)0.046003182f, (float16_t)0.998941293f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.052131705f, (float16_t)0.998640218f, + (float16_t)0.055195244f, (float16_t)0.998475581f, + (float16_t)0.058258265f, (float16_t)0.998301545f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.064382631f, (float16_t)0.997925286f, + (float16_t)0.067443920f, (float16_t)0.997723067f, + (float16_t)0.070504573f, (float16_t)0.997511456f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.076623861f, (float16_t)0.997060070f, + (float16_t)0.079682438f, (float16_t)0.996820299f, + (float16_t)0.082740265f, (float16_t)0.996571146f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.088853553f, (float16_t)0.996044701f, + (float16_t)0.091908956f, (float16_t)0.995767414f, + (float16_t)0.094963495f, (float16_t)0.995480755f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.101069863f, (float16_t)0.994879331f, + (float16_t)0.104121634f, (float16_t)0.994564571f, + (float16_t)0.107172425f, (float16_t)0.994240449f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.113270952f, (float16_t)0.993564136f, + (float16_t)0.116318631f, (float16_t)0.993211949f, + (float16_t)0.119365215f, (float16_t)0.992850414f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.125454983f, (float16_t)0.992099313f, + (float16_t)0.128498111f, (float16_t)0.991709754f, + (float16_t)0.131540029f, (float16_t)0.991310860f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.137620122f, (float16_t)0.990485084f, + (float16_t)0.140658239f, (float16_t)0.990058210f, + (float16_t)0.143695033f, (float16_t)0.989622017f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.149764535f, (float16_t)0.988721692f, + (float16_t)0.152797185f, (float16_t)0.988257568f, + (float16_t)0.155828398f, (float16_t)0.987784142f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.161886394f, (float16_t)0.986809402f, + (float16_t)0.164913120f, (float16_t)0.986308097f, + (float16_t)0.167938295f, (float16_t)0.985797509f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.173983873f, (float16_t)0.984748502f, + (float16_t)0.177004220f, (float16_t)0.984210092f, + (float16_t)0.180022901f, (float16_t)0.983662419f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.186055152f, (float16_t)0.982539302f, + (float16_t)0.189068664f, (float16_t)0.981963869f, + (float16_t)0.192080397f, (float16_t)0.981379193f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.198098411f, (float16_t)0.980182136f, + (float16_t)0.201104635f, (float16_t)0.979569766f, + (float16_t)0.204108966f, (float16_t)0.978948175f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.210111837f, (float16_t)0.977677358f, + (float16_t)0.213110320f, (float16_t)0.977028143f, + (float16_t)0.216106797f, (float16_t)0.976369731f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.222093621f, (float16_t)0.975025345f, + (float16_t)0.225083911f, (float16_t)0.974339383f, + (float16_t)0.228072083f, (float16_t)0.973644250f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.234041959f, (float16_t)0.972226497f, + (float16_t)0.237023606f, (float16_t)0.971503891f, + (float16_t)0.240003022f, (float16_t)0.970772141f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.245955050f, (float16_t)0.969281235f, + (float16_t)0.248927606f, (float16_t)0.968522094f, + (float16_t)0.251897818f, (float16_t)0.967753837f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.257831102f, (float16_t)0.966190003f, + (float16_t)0.260794118f, (float16_t)0.965394442f, + (float16_t)0.263754679f, (float16_t)0.964589793f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.269668326f, (float16_t)0.962953267f, + (float16_t)0.272621355f, (float16_t)0.962121404f, + (float16_t)0.275571819f, (float16_t)0.961280486f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.281464938f, (float16_t)0.959571513f, + (float16_t)0.284407537f, (float16_t)0.958703475f, + (float16_t)0.287347460f, (float16_t)0.957826413f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.293219163f, (float16_t)0.956045251f, + (float16_t)0.296150888f, (float16_t)0.955141168f, + (float16_t)0.299079826f, (float16_t)0.954228095f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.304929230f, (float16_t)0.952375013f, + (float16_t)0.307849640f, (float16_t)0.951435021f, + (float16_t)0.310767153f, (float16_t)0.950486074f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.316593376f, (float16_t)0.948561350f, + (float16_t)0.319502031f, (float16_t)0.947585591f, + (float16_t)0.322407679f, (float16_t)0.946600913f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.328209844f, (float16_t)0.944604837f, + (float16_t)0.331106306f, (float16_t)0.943593458f, + (float16_t)0.333999651f, (float16_t)0.942573198f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.339776884f, (float16_t)0.940506071f, + (float16_t)0.342660717f, (float16_t)0.939459224f, + (float16_t)0.345541325f, (float16_t)0.938403534f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.351292756f, (float16_t)0.936265667f, + (float16_t)0.354163525f, (float16_t)0.935183510f, + (float16_t)0.357030961f, (float16_t)0.934092550f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.362755724f, (float16_t)0.931884266f, + (float16_t)0.365612998f, (float16_t)0.930766961f, + (float16_t)0.368466830f, (float16_t)0.929640896f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.374164063f, (float16_t)0.927362526f, + (float16_t)0.377007410f, (float16_t)0.926210242f, + (float16_t)0.379847209f, (float16_t)0.925049241f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.385516054f, (float16_t)0.922701128f, + (float16_t)0.388345047f, (float16_t)0.921514039f, + (float16_t)0.391170384f, (float16_t)0.920318277f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.396809987f, (float16_t)0.917900776f, + (float16_t)0.399624200f, (float16_t)0.916679060f, + (float16_t)0.402434651f, (float16_t)0.915448716f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.408044163f, (float16_t)0.912962190f, + (float16_t)0.410843171f, (float16_t)0.911706032f, + (float16_t)0.413638312f, (float16_t)0.910441292f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.419216888f, (float16_t)0.907886116f, + (float16_t)0.422000271f, (float16_t)0.906595705f, + (float16_t)0.424779681f, (float16_t)0.905296759f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.430326481f, (float16_t)0.902673318f, + (float16_t)0.433093819f, (float16_t)0.901348847f, + (float16_t)0.435857080f, (float16_t)0.900015892f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.441371269f, (float16_t)0.897324581f, + (float16_t)0.444122145f, (float16_t)0.895966250f, + (float16_t)0.446868840f, (float16_t)0.894599486f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.452349587f, (float16_t)0.891840709f, + (float16_t)0.455083587f, (float16_t)0.890448723f, + (float16_t)0.457813304f, (float16_t)0.889048356f, + (float16_t)0.460538711f, (float16_t)0.887639620f, + (float16_t)0.463259784f, (float16_t)0.886222530f, + (float16_t)0.465976496f, (float16_t)0.884797098f, + (float16_t)0.468688822f, (float16_t)0.883363339f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.474100215f, (float16_t)0.880470889f, + (float16_t)0.476799230f, (float16_t)0.879012226f, + (float16_t)0.479493758f, (float16_t)0.877545290f, + (float16_t)0.482183772f, (float16_t)0.876070094f, + (float16_t)0.484869248f, (float16_t)0.874586652f, + (float16_t)0.487550160f, (float16_t)0.873094978f, + (float16_t)0.490226483f, (float16_t)0.871595087f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.495565262f, (float16_t)0.868570706f, + (float16_t)0.498227667f, (float16_t)0.867046246f, + (float16_t)0.500885383f, (float16_t)0.865513624f, + (float16_t)0.503538384f, (float16_t)0.863972856f, + (float16_t)0.506186645f, (float16_t)0.862423956f, + (float16_t)0.508830143f, (float16_t)0.860866939f, + (float16_t)0.511468850f, (float16_t)0.859301818f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.516731799f, (float16_t)0.856147328f, + (float16_t)0.519355990f, (float16_t)0.854557988f, + (float16_t)0.521975293f, (float16_t)0.852960605f, + (float16_t)0.524589683f, (float16_t)0.851355193f, + (float16_t)0.527199135f, (float16_t)0.849741768f, + (float16_t)0.529803625f, (float16_t)0.848120345f, + (float16_t)0.532403128f, (float16_t)0.846490939f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.537587076f, (float16_t)0.843208240f, + (float16_t)0.540171473f, (float16_t)0.841554977f, + (float16_t)0.542750785f, (float16_t)0.839893794f, + (float16_t)0.545324988f, (float16_t)0.838224706f, + (float16_t)0.547894059f, (float16_t)0.836547727f, + (float16_t)0.550457973f, (float16_t)0.834862875f, + (float16_t)0.553016706f, (float16_t)0.833170165f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.558118531f, (float16_t)0.829761234f, + (float16_t)0.560661576f, (float16_t)0.828045045f, + (float16_t)0.563199344f, (float16_t)0.826321063f, + (float16_t)0.565731811f, (float16_t)0.824589303f, + (float16_t)0.568258953f, (float16_t)0.822849781f, + (float16_t)0.570780746f, (float16_t)0.821102515f, + (float16_t)0.573297167f, (float16_t)0.819347520f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.578313796f, (float16_t)0.815814411f, + (float16_t)0.580813958f, (float16_t)0.814036330f, + (float16_t)0.583308653f, (float16_t)0.812250587f, + (float16_t)0.585797857f, (float16_t)0.810457198f, + (float16_t)0.588281548f, (float16_t)0.808656182f, + (float16_t)0.590759702f, (float16_t)0.806847554f, + (float16_t)0.593232295f, (float16_t)0.805031331f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.598160707f, (float16_t)0.801376172f, + (float16_t)0.600616479f, (float16_t)0.799537269f, + (float16_t)0.603066599f, (float16_t)0.797690841f, + (float16_t)0.605511041f, (float16_t)0.795836905f, + (float16_t)0.607949785f, (float16_t)0.793975478f, + (float16_t)0.610382806f, (float16_t)0.792106577f, + (float16_t)0.612810082f, (float16_t)0.790230221f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.617647308f, (float16_t)0.786455214f, + (float16_t)0.620057212f, (float16_t)0.784556597f, + (float16_t)0.622461279f, (float16_t)0.782650596f, + (float16_t)0.624859488f, (float16_t)0.780737229f, + (float16_t)0.627251815f, (float16_t)0.778816512f, + (float16_t)0.629638239f, (float16_t)0.776888466f, + (float16_t)0.632018736f, (float16_t)0.774953107f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.636761861f, (float16_t)0.771060524f, + (float16_t)0.639124445f, (float16_t)0.769103338f, + (float16_t)0.641481013f, (float16_t)0.767138912f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.646176013f, (float16_t)0.763188417f, + (float16_t)0.648514401f, (float16_t)0.761202385f, + (float16_t)0.650846685f, (float16_t)0.759209189f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.655492853f, (float16_t)0.755201377f, + (float16_t)0.657806693f, (float16_t)0.753186799f, + (float16_t)0.660114342f, (float16_t)0.751165132f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.664710978f, (float16_t)0.747100606f, + (float16_t)0.666999922f, (float16_t)0.745057785f, + (float16_t)0.669282588f, (float16_t)0.743007952f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.673829000f, (float16_t)0.738887324f, + (float16_t)0.676092704f, (float16_t)0.736816569f, + (float16_t)0.678350043f, (float16_t)0.734738878f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.682845546f, (float16_t)0.730562769f, + (float16_t)0.685083668f, (float16_t)0.728464390f, + (float16_t)0.687315341f, (float16_t)0.726359155f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.691759258f, (float16_t)0.722128194f, + (float16_t)0.693971461f, (float16_t)0.720002508f, + (float16_t)0.696177131f, (float16_t)0.717870045f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.700568794f, (float16_t)0.713584869f, + (float16_t)0.702754744f, (float16_t)0.711432196f, + (float16_t)0.704934080f, (float16_t)0.709272826f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.709272826f, (float16_t)0.704934080f, + (float16_t)0.711432196f, (float16_t)0.702754744f, + (float16_t)0.713584869f, (float16_t)0.700568794f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.717870045f, (float16_t)0.696177131f, + (float16_t)0.720002508f, (float16_t)0.693971461f, + (float16_t)0.722128194f, (float16_t)0.691759258f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.726359155f, (float16_t)0.687315341f, + (float16_t)0.728464390f, (float16_t)0.685083668f, + (float16_t)0.730562769f, (float16_t)0.682845546f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.734738878f, (float16_t)0.678350043f, + (float16_t)0.736816569f, (float16_t)0.676092704f, + (float16_t)0.738887324f, (float16_t)0.673829000f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.743007952f, (float16_t)0.669282588f, + (float16_t)0.745057785f, (float16_t)0.666999922f, + (float16_t)0.747100606f, (float16_t)0.664710978f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.751165132f, (float16_t)0.660114342f, + (float16_t)0.753186799f, (float16_t)0.657806693f, + (float16_t)0.755201377f, (float16_t)0.655492853f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.759209189f, (float16_t)0.650846685f, + (float16_t)0.761202385f, (float16_t)0.648514401f, + (float16_t)0.763188417f, (float16_t)0.646176013f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.767138912f, (float16_t)0.641481013f, + (float16_t)0.769103338f, (float16_t)0.639124445f, + (float16_t)0.771060524f, (float16_t)0.636761861f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.774953107f, (float16_t)0.632018736f, + (float16_t)0.776888466f, (float16_t)0.629638239f, + (float16_t)0.778816512f, (float16_t)0.627251815f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.782650596f, (float16_t)0.622461279f, + (float16_t)0.784556597f, (float16_t)0.620057212f, + (float16_t)0.786455214f, (float16_t)0.617647308f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.790230221f, (float16_t)0.612810082f, + (float16_t)0.792106577f, (float16_t)0.610382806f, + (float16_t)0.793975478f, (float16_t)0.607949785f, + (float16_t)0.795836905f, (float16_t)0.605511041f, + (float16_t)0.797690841f, (float16_t)0.603066599f, + (float16_t)0.799537269f, (float16_t)0.600616479f, + (float16_t)0.801376172f, (float16_t)0.598160707f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.805031331f, (float16_t)0.593232295f, + (float16_t)0.806847554f, (float16_t)0.590759702f, + (float16_t)0.808656182f, (float16_t)0.588281548f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.812250587f, (float16_t)0.583308653f, + (float16_t)0.814036330f, (float16_t)0.580813958f, + (float16_t)0.815814411f, (float16_t)0.578313796f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.819347520f, (float16_t)0.573297167f, + (float16_t)0.821102515f, (float16_t)0.570780746f, + (float16_t)0.822849781f, (float16_t)0.568258953f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.826321063f, (float16_t)0.563199344f, + (float16_t)0.828045045f, (float16_t)0.560661576f, + (float16_t)0.829761234f, (float16_t)0.558118531f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.833170165f, (float16_t)0.553016706f, + (float16_t)0.834862875f, (float16_t)0.550457973f, + (float16_t)0.836547727f, (float16_t)0.547894059f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.839893794f, (float16_t)0.542750785f, + (float16_t)0.841554977f, (float16_t)0.540171473f, + (float16_t)0.843208240f, (float16_t)0.537587076f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.846490939f, (float16_t)0.532403128f, + (float16_t)0.848120345f, (float16_t)0.529803625f, + (float16_t)0.849741768f, (float16_t)0.527199135f, + (float16_t)0.851355193f, (float16_t)0.524589683f, + (float16_t)0.852960605f, (float16_t)0.521975293f, + (float16_t)0.854557988f, (float16_t)0.519355990f, + (float16_t)0.856147328f, (float16_t)0.516731799f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.859301818f, (float16_t)0.511468850f, + (float16_t)0.860866939f, (float16_t)0.508830143f, + (float16_t)0.862423956f, (float16_t)0.506186645f, + (float16_t)0.863972856f, (float16_t)0.503538384f, + (float16_t)0.865513624f, (float16_t)0.500885383f, + (float16_t)0.867046246f, (float16_t)0.498227667f, + (float16_t)0.868570706f, (float16_t)0.495565262f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.871595087f, (float16_t)0.490226483f, + (float16_t)0.873094978f, (float16_t)0.487550160f, + (float16_t)0.874586652f, (float16_t)0.484869248f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.877545290f, (float16_t)0.479493758f, + (float16_t)0.879012226f, (float16_t)0.476799230f, + (float16_t)0.880470889f, (float16_t)0.474100215f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.883363339f, (float16_t)0.468688822f, + (float16_t)0.884797098f, (float16_t)0.465976496f, + (float16_t)0.886222530f, (float16_t)0.463259784f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.889048356f, (float16_t)0.457813304f, + (float16_t)0.890448723f, (float16_t)0.455083587f, + (float16_t)0.891840709f, (float16_t)0.452349587f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.894599486f, (float16_t)0.446868840f, + (float16_t)0.895966250f, (float16_t)0.444122145f, + (float16_t)0.897324581f, (float16_t)0.441371269f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.900015892f, (float16_t)0.435857080f, + (float16_t)0.901348847f, (float16_t)0.433093819f, + (float16_t)0.902673318f, (float16_t)0.430326481f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.905296759f, (float16_t)0.424779681f, + (float16_t)0.906595705f, (float16_t)0.422000271f, + (float16_t)0.907886116f, (float16_t)0.419216888f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.910441292f, (float16_t)0.413638312f, + (float16_t)0.911706032f, (float16_t)0.410843171f, + (float16_t)0.912962190f, (float16_t)0.408044163f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.915448716f, (float16_t)0.402434651f, + (float16_t)0.916679060f, (float16_t)0.399624200f, + (float16_t)0.917900776f, (float16_t)0.396809987f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.920318277f, (float16_t)0.391170384f, + (float16_t)0.921514039f, (float16_t)0.388345047f, + (float16_t)0.922701128f, (float16_t)0.385516054f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.925049241f, (float16_t)0.379847209f, + (float16_t)0.926210242f, (float16_t)0.377007410f, + (float16_t)0.927362526f, (float16_t)0.374164063f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.929640896f, (float16_t)0.368466830f, + (float16_t)0.930766961f, (float16_t)0.365612998f, + (float16_t)0.931884266f, (float16_t)0.362755724f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.934092550f, (float16_t)0.357030961f, + (float16_t)0.935183510f, (float16_t)0.354163525f, + (float16_t)0.936265667f, (float16_t)0.351292756f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.938403534f, (float16_t)0.345541325f, + (float16_t)0.939459224f, (float16_t)0.342660717f, + (float16_t)0.940506071f, (float16_t)0.339776884f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.942573198f, (float16_t)0.333999651f, + (float16_t)0.943593458f, (float16_t)0.331106306f, + (float16_t)0.944604837f, (float16_t)0.328209844f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.946600913f, (float16_t)0.322407679f, + (float16_t)0.947585591f, (float16_t)0.319502031f, + (float16_t)0.948561350f, (float16_t)0.316593376f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.950486074f, (float16_t)0.310767153f, + (float16_t)0.951435021f, (float16_t)0.307849640f, + (float16_t)0.952375013f, (float16_t)0.304929230f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.954228095f, (float16_t)0.299079826f, + (float16_t)0.955141168f, (float16_t)0.296150888f, + (float16_t)0.956045251f, (float16_t)0.293219163f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.957826413f, (float16_t)0.287347460f, + (float16_t)0.958703475f, (float16_t)0.284407537f, + (float16_t)0.959571513f, (float16_t)0.281464938f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.961280486f, (float16_t)0.275571819f, + (float16_t)0.962121404f, (float16_t)0.272621355f, + (float16_t)0.962953267f, (float16_t)0.269668326f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.964589793f, (float16_t)0.263754679f, + (float16_t)0.965394442f, (float16_t)0.260794118f, + (float16_t)0.966190003f, (float16_t)0.257831102f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.967753837f, (float16_t)0.251897818f, + (float16_t)0.968522094f, (float16_t)0.248927606f, + (float16_t)0.969281235f, (float16_t)0.245955050f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.970772141f, (float16_t)0.240003022f, + (float16_t)0.971503891f, (float16_t)0.237023606f, + (float16_t)0.972226497f, (float16_t)0.234041959f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.973644250f, (float16_t)0.228072083f, + (float16_t)0.974339383f, (float16_t)0.225083911f, + (float16_t)0.975025345f, (float16_t)0.222093621f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.976369731f, (float16_t)0.216106797f, + (float16_t)0.977028143f, (float16_t)0.213110320f, + (float16_t)0.977677358f, (float16_t)0.210111837f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.978948175f, (float16_t)0.204108966f, + (float16_t)0.979569766f, (float16_t)0.201104635f, + (float16_t)0.980182136f, (float16_t)0.198098411f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.981379193f, (float16_t)0.192080397f, + (float16_t)0.981963869f, (float16_t)0.189068664f, + (float16_t)0.982539302f, (float16_t)0.186055152f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.983662419f, (float16_t)0.180022901f, + (float16_t)0.984210092f, (float16_t)0.177004220f, + (float16_t)0.984748502f, (float16_t)0.173983873f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.985797509f, (float16_t)0.167938295f, + (float16_t)0.986308097f, (float16_t)0.164913120f, + (float16_t)0.986809402f, (float16_t)0.161886394f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.987784142f, (float16_t)0.155828398f, + (float16_t)0.988257568f, (float16_t)0.152797185f, + (float16_t)0.988721692f, (float16_t)0.149764535f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.989622017f, (float16_t)0.143695033f, + (float16_t)0.990058210f, (float16_t)0.140658239f, + (float16_t)0.990485084f, (float16_t)0.137620122f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.991310860f, (float16_t)0.131540029f, + (float16_t)0.991709754f, (float16_t)0.128498111f, + (float16_t)0.992099313f, (float16_t)0.125454983f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.992850414f, (float16_t)0.119365215f, + (float16_t)0.993211949f, (float16_t)0.116318631f, + (float16_t)0.993564136f, (float16_t)0.113270952f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.994240449f, (float16_t)0.107172425f, + (float16_t)0.994564571f, (float16_t)0.104121634f, + (float16_t)0.994879331f, (float16_t)0.101069863f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.995480755f, (float16_t)0.094963495f, + (float16_t)0.995767414f, (float16_t)0.091908956f, + (float16_t)0.996044701f, (float16_t)0.088853553f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.996571146f, (float16_t)0.082740265f, + (float16_t)0.996820299f, (float16_t)0.079682438f, + (float16_t)0.997060070f, (float16_t)0.076623861f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.997511456f, (float16_t)0.070504573f, + (float16_t)0.997723067f, (float16_t)0.067443920f, + (float16_t)0.997925286f, (float16_t)0.064382631f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.998301545f, (float16_t)0.058258265f, + (float16_t)0.998475581f, (float16_t)0.055195244f, + (float16_t)0.998640218f, (float16_t)0.052131705f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.998941293f, (float16_t)0.046003182f, + (float16_t)0.999077728f, (float16_t)0.042938257f, + (float16_t)0.999204759f, (float16_t)0.039872928f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.999430605f, (float16_t)0.033741172f, + (float16_t)0.999529418f, (float16_t)0.030674803f, + (float16_t)0.999618822f, (float16_t)0.027608146f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999769405f, (float16_t)0.021474080f, + (float16_t)0.999830582f, (float16_t)0.018406730f, + (float16_t)0.999882347f, (float16_t)0.015339206f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)0.999957645f, (float16_t)0.009203755f, + (float16_t)0.999981175f, (float16_t)0.006135885f, + (float16_t)0.999995294f, (float16_t)0.003067957f, + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999995294f, (float16_t)-0.003067957f, + (float16_t)0.999981175f, (float16_t)-0.006135885f, + (float16_t)0.999957645f, (float16_t)-0.009203755f, + (float16_t)0.999924702f, (float16_t)-0.012271538f, + (float16_t)0.999882347f, (float16_t)-0.015339206f, + (float16_t)0.999830582f, (float16_t)-0.018406730f, + (float16_t)0.999769405f, (float16_t)-0.021474080f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999618822f, (float16_t)-0.027608146f, + (float16_t)0.999529418f, (float16_t)-0.030674803f, + (float16_t)0.999430605f, (float16_t)-0.033741172f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.999204759f, (float16_t)-0.039872928f, + (float16_t)0.999077728f, (float16_t)-0.042938257f, + (float16_t)0.998941293f, (float16_t)-0.046003182f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.998640218f, (float16_t)-0.052131705f, + (float16_t)0.998475581f, (float16_t)-0.055195244f, + (float16_t)0.998301545f, (float16_t)-0.058258265f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.997925286f, (float16_t)-0.064382631f, + (float16_t)0.997723067f, (float16_t)-0.067443920f, + (float16_t)0.997511456f, (float16_t)-0.070504573f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.997060070f, (float16_t)-0.076623861f, + (float16_t)0.996820299f, (float16_t)-0.079682438f, + (float16_t)0.996571146f, (float16_t)-0.082740265f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.996044701f, (float16_t)-0.088853553f, + (float16_t)0.995767414f, (float16_t)-0.091908956f, + (float16_t)0.995480755f, (float16_t)-0.094963495f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.994879331f, (float16_t)-0.101069863f, + (float16_t)0.994564571f, (float16_t)-0.104121634f, + (float16_t)0.994240449f, (float16_t)-0.107172425f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.993564136f, (float16_t)-0.113270952f, + (float16_t)0.993211949f, (float16_t)-0.116318631f, + (float16_t)0.992850414f, (float16_t)-0.119365215f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.992099313f, (float16_t)-0.125454983f, + (float16_t)0.991709754f, (float16_t)-0.128498111f, + (float16_t)0.991310860f, (float16_t)-0.131540029f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.990485084f, (float16_t)-0.137620122f, + (float16_t)0.990058210f, (float16_t)-0.140658239f, + (float16_t)0.989622017f, (float16_t)-0.143695033f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.988721692f, (float16_t)-0.149764535f, + (float16_t)0.988257568f, (float16_t)-0.152797185f, + (float16_t)0.987784142f, (float16_t)-0.155828398f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.986809402f, (float16_t)-0.161886394f, + (float16_t)0.986308097f, (float16_t)-0.164913120f, + (float16_t)0.985797509f, (float16_t)-0.167938295f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.984748502f, (float16_t)-0.173983873f, + (float16_t)0.984210092f, (float16_t)-0.177004220f, + (float16_t)0.983662419f, (float16_t)-0.180022901f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.982539302f, (float16_t)-0.186055152f, + (float16_t)0.981963869f, (float16_t)-0.189068664f, + (float16_t)0.981379193f, (float16_t)-0.192080397f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.980182136f, (float16_t)-0.198098411f, + (float16_t)0.979569766f, (float16_t)-0.201104635f, + (float16_t)0.978948175f, (float16_t)-0.204108966f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.977677358f, (float16_t)-0.210111837f, + (float16_t)0.977028143f, (float16_t)-0.213110320f, + (float16_t)0.976369731f, (float16_t)-0.216106797f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.975025345f, (float16_t)-0.222093621f, + (float16_t)0.974339383f, (float16_t)-0.225083911f, + (float16_t)0.973644250f, (float16_t)-0.228072083f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.972226497f, (float16_t)-0.234041959f, + (float16_t)0.971503891f, (float16_t)-0.237023606f, + (float16_t)0.970772141f, (float16_t)-0.240003022f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.969281235f, (float16_t)-0.245955050f, + (float16_t)0.968522094f, (float16_t)-0.248927606f, + (float16_t)0.967753837f, (float16_t)-0.251897818f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.966190003f, (float16_t)-0.257831102f, + (float16_t)0.965394442f, (float16_t)-0.260794118f, + (float16_t)0.964589793f, (float16_t)-0.263754679f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.962953267f, (float16_t)-0.269668326f, + (float16_t)0.962121404f, (float16_t)-0.272621355f, + (float16_t)0.961280486f, (float16_t)-0.275571819f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.959571513f, (float16_t)-0.281464938f, + (float16_t)0.958703475f, (float16_t)-0.284407537f, + (float16_t)0.957826413f, (float16_t)-0.287347460f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.956045251f, (float16_t)-0.293219163f, + (float16_t)0.955141168f, (float16_t)-0.296150888f, + (float16_t)0.954228095f, (float16_t)-0.299079826f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.952375013f, (float16_t)-0.304929230f, + (float16_t)0.951435021f, (float16_t)-0.307849640f, + (float16_t)0.950486074f, (float16_t)-0.310767153f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.948561350f, (float16_t)-0.316593376f, + (float16_t)0.947585591f, (float16_t)-0.319502031f, + (float16_t)0.946600913f, (float16_t)-0.322407679f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.944604837f, (float16_t)-0.328209844f, + (float16_t)0.943593458f, (float16_t)-0.331106306f, + (float16_t)0.942573198f, (float16_t)-0.333999651f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.940506071f, (float16_t)-0.339776884f, + (float16_t)0.939459224f, (float16_t)-0.342660717f, + (float16_t)0.938403534f, (float16_t)-0.345541325f, + (float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.936265667f, (float16_t)-0.351292756f, + (float16_t)0.935183510f, (float16_t)-0.354163525f, + (float16_t)0.934092550f, (float16_t)-0.357030961f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.931884266f, (float16_t)-0.362755724f, + (float16_t)0.930766961f, (float16_t)-0.365612998f, + (float16_t)0.929640896f, (float16_t)-0.368466830f, + (float16_t)0.928506080f, (float16_t)-0.371317194f, + (float16_t)0.927362526f, (float16_t)-0.374164063f, + (float16_t)0.926210242f, (float16_t)-0.377007410f, + (float16_t)0.925049241f, (float16_t)-0.379847209f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.922701128f, (float16_t)-0.385516054f, + (float16_t)0.921514039f, (float16_t)-0.388345047f, + (float16_t)0.920318277f, (float16_t)-0.391170384f, + (float16_t)0.919113852f, (float16_t)-0.393992040f, + (float16_t)0.917900776f, (float16_t)-0.396809987f, + (float16_t)0.916679060f, (float16_t)-0.399624200f, + (float16_t)0.915448716f, (float16_t)-0.402434651f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.912962190f, (float16_t)-0.408044163f, + (float16_t)0.911706032f, (float16_t)-0.410843171f, + (float16_t)0.910441292f, (float16_t)-0.413638312f, + (float16_t)0.909167983f, (float16_t)-0.416429560f, + (float16_t)0.907886116f, (float16_t)-0.419216888f, + (float16_t)0.906595705f, (float16_t)-0.422000271f, + (float16_t)0.905296759f, (float16_t)-0.424779681f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.902673318f, (float16_t)-0.430326481f, + (float16_t)0.901348847f, (float16_t)-0.433093819f, + (float16_t)0.900015892f, (float16_t)-0.435857080f, + (float16_t)0.898674466f, (float16_t)-0.438616239f, + (float16_t)0.897324581f, (float16_t)-0.441371269f, + (float16_t)0.895966250f, (float16_t)-0.444122145f, + (float16_t)0.894599486f, (float16_t)-0.446868840f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.891840709f, (float16_t)-0.452349587f, + (float16_t)0.890448723f, (float16_t)-0.455083587f, + (float16_t)0.889048356f, (float16_t)-0.457813304f, + (float16_t)0.887639620f, (float16_t)-0.460538711f, + (float16_t)0.886222530f, (float16_t)-0.463259784f, + (float16_t)0.884797098f, (float16_t)-0.465976496f, + (float16_t)0.883363339f, (float16_t)-0.468688822f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.880470889f, (float16_t)-0.474100215f, + (float16_t)0.879012226f, (float16_t)-0.476799230f, + (float16_t)0.877545290f, (float16_t)-0.479493758f, + (float16_t)0.876070094f, (float16_t)-0.482183772f, + (float16_t)0.874586652f, (float16_t)-0.484869248f, + (float16_t)0.873094978f, (float16_t)-0.487550160f, + (float16_t)0.871595087f, (float16_t)-0.490226483f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.868570706f, (float16_t)-0.495565262f, + (float16_t)0.867046246f, (float16_t)-0.498227667f, + (float16_t)0.865513624f, (float16_t)-0.500885383f, + (float16_t)0.863972856f, (float16_t)-0.503538384f, + (float16_t)0.862423956f, (float16_t)-0.506186645f, + (float16_t)0.860866939f, (float16_t)-0.508830143f, + (float16_t)0.859301818f, (float16_t)-0.511468850f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.856147328f, (float16_t)-0.516731799f, + (float16_t)0.854557988f, (float16_t)-0.519355990f, + (float16_t)0.852960605f, (float16_t)-0.521975293f, + (float16_t)0.851355193f, (float16_t)-0.524589683f, + (float16_t)0.849741768f, (float16_t)-0.527199135f, + (float16_t)0.848120345f, (float16_t)-0.529803625f, + (float16_t)0.846490939f, (float16_t)-0.532403128f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.843208240f, (float16_t)-0.537587076f, + (float16_t)0.841554977f, (float16_t)-0.540171473f, + (float16_t)0.839893794f, (float16_t)-0.542750785f, + (float16_t)0.838224706f, (float16_t)-0.545324988f, + (float16_t)0.836547727f, (float16_t)-0.547894059f, + (float16_t)0.834862875f, (float16_t)-0.550457973f, + (float16_t)0.833170165f, (float16_t)-0.553016706f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.829761234f, (float16_t)-0.558118531f, + (float16_t)0.828045045f, (float16_t)-0.560661576f, + (float16_t)0.826321063f, (float16_t)-0.563199344f, + (float16_t)0.824589303f, (float16_t)-0.565731811f, + (float16_t)0.822849781f, (float16_t)-0.568258953f, + (float16_t)0.821102515f, (float16_t)-0.570780746f, + (float16_t)0.819347520f, (float16_t)-0.573297167f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.815814411f, (float16_t)-0.578313796f, + (float16_t)0.814036330f, (float16_t)-0.580813958f, + (float16_t)0.812250587f, (float16_t)-0.583308653f, + (float16_t)0.810457198f, (float16_t)-0.585797857f, + (float16_t)0.808656182f, (float16_t)-0.588281548f, + (float16_t)0.806847554f, (float16_t)-0.590759702f, + (float16_t)0.805031331f, (float16_t)-0.593232295f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.801376172f, (float16_t)-0.598160707f, + (float16_t)0.799537269f, (float16_t)-0.600616479f, + (float16_t)0.797690841f, (float16_t)-0.603066599f, + (float16_t)0.795836905f, (float16_t)-0.605511041f, + (float16_t)0.793975478f, (float16_t)-0.607949785f, + (float16_t)0.792106577f, (float16_t)-0.610382806f, + (float16_t)0.790230221f, (float16_t)-0.612810082f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.786455214f, (float16_t)-0.617647308f, + (float16_t)0.784556597f, (float16_t)-0.620057212f, + (float16_t)0.782650596f, (float16_t)-0.622461279f, + (float16_t)0.780737229f, (float16_t)-0.624859488f, + (float16_t)0.778816512f, (float16_t)-0.627251815f, + (float16_t)0.776888466f, (float16_t)-0.629638239f, + (float16_t)0.774953107f, (float16_t)-0.632018736f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.771060524f, (float16_t)-0.636761861f, + (float16_t)0.769103338f, (float16_t)-0.639124445f, + (float16_t)0.767138912f, (float16_t)-0.641481013f, + (float16_t)0.765167266f, (float16_t)-0.643831543f, + (float16_t)0.763188417f, (float16_t)-0.646176013f, + (float16_t)0.761202385f, (float16_t)-0.648514401f, + (float16_t)0.759209189f, (float16_t)-0.650846685f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.755201377f, (float16_t)-0.655492853f, + (float16_t)0.753186799f, (float16_t)-0.657806693f, + (float16_t)0.751165132f, (float16_t)-0.660114342f, + (float16_t)0.749136395f, (float16_t)-0.662415778f, + (float16_t)0.747100606f, (float16_t)-0.664710978f, + (float16_t)0.745057785f, (float16_t)-0.666999922f, + (float16_t)0.743007952f, (float16_t)-0.669282588f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.738887324f, (float16_t)-0.673829000f, + (float16_t)0.736816569f, (float16_t)-0.676092704f, + (float16_t)0.734738878f, (float16_t)-0.678350043f, + (float16_t)0.732654272f, (float16_t)-0.680600998f, + (float16_t)0.730562769f, (float16_t)-0.682845546f, + (float16_t)0.728464390f, (float16_t)-0.685083668f, + (float16_t)0.726359155f, (float16_t)-0.687315341f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.722128194f, (float16_t)-0.691759258f, + (float16_t)0.720002508f, (float16_t)-0.693971461f, + (float16_t)0.717870045f, (float16_t)-0.696177131f, + (float16_t)0.715730825f, (float16_t)-0.698376249f, + (float16_t)0.713584869f, (float16_t)-0.700568794f, + (float16_t)0.711432196f, (float16_t)-0.702754744f, + (float16_t)0.709272826f, (float16_t)-0.704934080f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.704934080f, (float16_t)-0.709272826f, + (float16_t)0.702754744f, (float16_t)-0.711432196f, + (float16_t)0.700568794f, (float16_t)-0.713584869f, + (float16_t)0.698376249f, (float16_t)-0.715730825f, + (float16_t)0.696177131f, (float16_t)-0.717870045f, + (float16_t)0.693971461f, (float16_t)-0.720002508f, + (float16_t)0.691759258f, (float16_t)-0.722128194f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.687315341f, (float16_t)-0.726359155f, + (float16_t)0.685083668f, (float16_t)-0.728464390f, + (float16_t)0.682845546f, (float16_t)-0.730562769f, + (float16_t)0.680600998f, (float16_t)-0.732654272f, + (float16_t)0.678350043f, (float16_t)-0.734738878f, + (float16_t)0.676092704f, (float16_t)-0.736816569f, + (float16_t)0.673829000f, (float16_t)-0.738887324f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.669282588f, (float16_t)-0.743007952f, + (float16_t)0.666999922f, (float16_t)-0.745057785f, + (float16_t)0.664710978f, (float16_t)-0.747100606f, + (float16_t)0.662415778f, (float16_t)-0.749136395f, + (float16_t)0.660114342f, (float16_t)-0.751165132f, + (float16_t)0.657806693f, (float16_t)-0.753186799f, + (float16_t)0.655492853f, (float16_t)-0.755201377f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.650846685f, (float16_t)-0.759209189f, + (float16_t)0.648514401f, (float16_t)-0.761202385f, + (float16_t)0.646176013f, (float16_t)-0.763188417f, + (float16_t)0.643831543f, (float16_t)-0.765167266f, + (float16_t)0.641481013f, (float16_t)-0.767138912f, + (float16_t)0.639124445f, (float16_t)-0.769103338f, + (float16_t)0.636761861f, (float16_t)-0.771060524f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.632018736f, (float16_t)-0.774953107f, + (float16_t)0.629638239f, (float16_t)-0.776888466f, + (float16_t)0.627251815f, (float16_t)-0.778816512f, + (float16_t)0.624859488f, (float16_t)-0.780737229f, + (float16_t)0.622461279f, (float16_t)-0.782650596f, + (float16_t)0.620057212f, (float16_t)-0.784556597f, + (float16_t)0.617647308f, (float16_t)-0.786455214f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.612810082f, (float16_t)-0.790230221f, + (float16_t)0.610382806f, (float16_t)-0.792106577f, + (float16_t)0.607949785f, (float16_t)-0.793975478f, + (float16_t)0.605511041f, (float16_t)-0.795836905f, + (float16_t)0.603066599f, (float16_t)-0.797690841f, + (float16_t)0.600616479f, (float16_t)-0.799537269f, + (float16_t)0.598160707f, (float16_t)-0.801376172f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.593232295f, (float16_t)-0.805031331f, + (float16_t)0.590759702f, (float16_t)-0.806847554f, + (float16_t)0.588281548f, (float16_t)-0.808656182f, + (float16_t)0.585797857f, (float16_t)-0.810457198f, + (float16_t)0.583308653f, (float16_t)-0.812250587f, + (float16_t)0.580813958f, (float16_t)-0.814036330f, + (float16_t)0.578313796f, (float16_t)-0.815814411f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.573297167f, (float16_t)-0.819347520f, + (float16_t)0.570780746f, (float16_t)-0.821102515f, + (float16_t)0.568258953f, (float16_t)-0.822849781f, + (float16_t)0.565731811f, (float16_t)-0.824589303f, + (float16_t)0.563199344f, (float16_t)-0.826321063f, + (float16_t)0.560661576f, (float16_t)-0.828045045f, + (float16_t)0.558118531f, (float16_t)-0.829761234f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.553016706f, (float16_t)-0.833170165f, + (float16_t)0.550457973f, (float16_t)-0.834862875f, + (float16_t)0.547894059f, (float16_t)-0.836547727f, + (float16_t)0.545324988f, (float16_t)-0.838224706f, + (float16_t)0.542750785f, (float16_t)-0.839893794f, + (float16_t)0.540171473f, (float16_t)-0.841554977f, + (float16_t)0.537587076f, (float16_t)-0.843208240f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.532403128f, (float16_t)-0.846490939f, + (float16_t)0.529803625f, (float16_t)-0.848120345f, + (float16_t)0.527199135f, (float16_t)-0.849741768f, + (float16_t)0.524589683f, (float16_t)-0.851355193f, + (float16_t)0.521975293f, (float16_t)-0.852960605f, + (float16_t)0.519355990f, (float16_t)-0.854557988f, + (float16_t)0.516731799f, (float16_t)-0.856147328f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.511468850f, (float16_t)-0.859301818f, + (float16_t)0.508830143f, (float16_t)-0.860866939f, + (float16_t)0.506186645f, (float16_t)-0.862423956f, + (float16_t)0.503538384f, (float16_t)-0.863972856f, + (float16_t)0.500885383f, (float16_t)-0.865513624f, + (float16_t)0.498227667f, (float16_t)-0.867046246f, + (float16_t)0.495565262f, (float16_t)-0.868570706f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.490226483f, (float16_t)-0.871595087f, + (float16_t)0.487550160f, (float16_t)-0.873094978f, + (float16_t)0.484869248f, (float16_t)-0.874586652f, + (float16_t)0.482183772f, (float16_t)-0.876070094f, + (float16_t)0.479493758f, (float16_t)-0.877545290f, + (float16_t)0.476799230f, (float16_t)-0.879012226f, + (float16_t)0.474100215f, (float16_t)-0.880470889f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.468688822f, (float16_t)-0.883363339f, + (float16_t)0.465976496f, (float16_t)-0.884797098f, + (float16_t)0.463259784f, (float16_t)-0.886222530f, + (float16_t)0.460538711f, (float16_t)-0.887639620f, + (float16_t)0.457813304f, (float16_t)-0.889048356f, + (float16_t)0.455083587f, (float16_t)-0.890448723f, + (float16_t)0.452349587f, (float16_t)-0.891840709f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.446868840f, (float16_t)-0.894599486f, + (float16_t)0.444122145f, (float16_t)-0.895966250f, + (float16_t)0.441371269f, (float16_t)-0.897324581f, + (float16_t)0.438616239f, (float16_t)-0.898674466f, + (float16_t)0.435857080f, (float16_t)-0.900015892f, + (float16_t)0.433093819f, (float16_t)-0.901348847f, + (float16_t)0.430326481f, (float16_t)-0.902673318f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.424779681f, (float16_t)-0.905296759f, + (float16_t)0.422000271f, (float16_t)-0.906595705f, + (float16_t)0.419216888f, (float16_t)-0.907886116f, + (float16_t)0.416429560f, (float16_t)-0.909167983f, + (float16_t)0.413638312f, (float16_t)-0.910441292f, + (float16_t)0.410843171f, (float16_t)-0.911706032f, + (float16_t)0.408044163f, (float16_t)-0.912962190f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.402434651f, (float16_t)-0.915448716f, + (float16_t)0.399624200f, (float16_t)-0.916679060f, + (float16_t)0.396809987f, (float16_t)-0.917900776f, + (float16_t)0.393992040f, (float16_t)-0.919113852f, + (float16_t)0.391170384f, (float16_t)-0.920318277f, + (float16_t)0.388345047f, (float16_t)-0.921514039f, + (float16_t)0.385516054f, (float16_t)-0.922701128f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.379847209f, (float16_t)-0.925049241f, + (float16_t)0.377007410f, (float16_t)-0.926210242f, + (float16_t)0.374164063f, (float16_t)-0.927362526f, + (float16_t)0.371317194f, (float16_t)-0.928506080f, + (float16_t)0.368466830f, (float16_t)-0.929640896f, + (float16_t)0.365612998f, (float16_t)-0.930766961f, + (float16_t)0.362755724f, (float16_t)-0.931884266f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.357030961f, (float16_t)-0.934092550f, + (float16_t)0.354163525f, (float16_t)-0.935183510f, + (float16_t)0.351292756f, (float16_t)-0.936265667f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.345541325f, (float16_t)-0.938403534f, + (float16_t)0.342660717f, (float16_t)-0.939459224f, + (float16_t)0.339776884f, (float16_t)-0.940506071f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.333999651f, (float16_t)-0.942573198f, + (float16_t)0.331106306f, (float16_t)-0.943593458f, + (float16_t)0.328209844f, (float16_t)-0.944604837f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.322407679f, (float16_t)-0.946600913f, + (float16_t)0.319502031f, (float16_t)-0.947585591f, + (float16_t)0.316593376f, (float16_t)-0.948561350f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.310767153f, (float16_t)-0.950486074f, + (float16_t)0.307849640f, (float16_t)-0.951435021f, + (float16_t)0.304929230f, (float16_t)-0.952375013f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.299079826f, (float16_t)-0.954228095f, + (float16_t)0.296150888f, (float16_t)-0.955141168f, + (float16_t)0.293219163f, (float16_t)-0.956045251f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.287347460f, (float16_t)-0.957826413f, + (float16_t)0.284407537f, (float16_t)-0.958703475f, + (float16_t)0.281464938f, (float16_t)-0.959571513f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.275571819f, (float16_t)-0.961280486f, + (float16_t)0.272621355f, (float16_t)-0.962121404f, + (float16_t)0.269668326f, (float16_t)-0.962953267f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.263754679f, (float16_t)-0.964589793f, + (float16_t)0.260794118f, (float16_t)-0.965394442f, + (float16_t)0.257831102f, (float16_t)-0.966190003f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.251897818f, (float16_t)-0.967753837f, + (float16_t)0.248927606f, (float16_t)-0.968522094f, + (float16_t)0.245955050f, (float16_t)-0.969281235f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.240003022f, (float16_t)-0.970772141f, + (float16_t)0.237023606f, (float16_t)-0.971503891f, + (float16_t)0.234041959f, (float16_t)-0.972226497f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.228072083f, (float16_t)-0.973644250f, + (float16_t)0.225083911f, (float16_t)-0.974339383f, + (float16_t)0.222093621f, (float16_t)-0.975025345f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.216106797f, (float16_t)-0.976369731f, + (float16_t)0.213110320f, (float16_t)-0.977028143f, + (float16_t)0.210111837f, (float16_t)-0.977677358f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.204108966f, (float16_t)-0.978948175f, + (float16_t)0.201104635f, (float16_t)-0.979569766f, + (float16_t)0.198098411f, (float16_t)-0.980182136f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.192080397f, (float16_t)-0.981379193f, + (float16_t)0.189068664f, (float16_t)-0.981963869f, + (float16_t)0.186055152f, (float16_t)-0.982539302f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.180022901f, (float16_t)-0.983662419f, + (float16_t)0.177004220f, (float16_t)-0.984210092f, + (float16_t)0.173983873f, (float16_t)-0.984748502f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.167938295f, (float16_t)-0.985797509f, + (float16_t)0.164913120f, (float16_t)-0.986308097f, + (float16_t)0.161886394f, (float16_t)-0.986809402f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.155828398f, (float16_t)-0.987784142f, + (float16_t)0.152797185f, (float16_t)-0.988257568f, + (float16_t)0.149764535f, (float16_t)-0.988721692f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.143695033f, (float16_t)-0.989622017f, + (float16_t)0.140658239f, (float16_t)-0.990058210f, + (float16_t)0.137620122f, (float16_t)-0.990485084f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.131540029f, (float16_t)-0.991310860f, + (float16_t)0.128498111f, (float16_t)-0.991709754f, + (float16_t)0.125454983f, (float16_t)-0.992099313f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.119365215f, (float16_t)-0.992850414f, + (float16_t)0.116318631f, (float16_t)-0.993211949f, + (float16_t)0.113270952f, (float16_t)-0.993564136f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.107172425f, (float16_t)-0.994240449f, + (float16_t)0.104121634f, (float16_t)-0.994564571f, + (float16_t)0.101069863f, (float16_t)-0.994879331f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.094963495f, (float16_t)-0.995480755f, + (float16_t)0.091908956f, (float16_t)-0.995767414f, + (float16_t)0.088853553f, (float16_t)-0.996044701f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.082740265f, (float16_t)-0.996571146f, + (float16_t)0.079682438f, (float16_t)-0.996820299f, + (float16_t)0.076623861f, (float16_t)-0.997060070f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.070504573f, (float16_t)-0.997511456f, + (float16_t)0.067443920f, (float16_t)-0.997723067f, + (float16_t)0.064382631f, (float16_t)-0.997925286f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.058258265f, (float16_t)-0.998301545f, + (float16_t)0.055195244f, (float16_t)-0.998475581f, + (float16_t)0.052131705f, (float16_t)-0.998640218f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.046003182f, (float16_t)-0.998941293f, + (float16_t)0.042938257f, (float16_t)-0.999077728f, + (float16_t)0.039872928f, (float16_t)-0.999204759f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.033741172f, (float16_t)-0.999430605f, + (float16_t)0.030674803f, (float16_t)-0.999529418f, + (float16_t)0.027608146f, (float16_t)-0.999618822f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.021474080f, (float16_t)-0.999769405f, + (float16_t)0.018406730f, (float16_t)-0.999830582f, + (float16_t)0.015339206f, (float16_t)-0.999882347f, + (float16_t)0.012271538f, (float16_t)-0.999924702f, + (float16_t)0.009203755f, (float16_t)-0.999957645f, + (float16_t)0.006135885f, (float16_t)-0.999981175f, + (float16_t)0.003067957f, (float16_t)-0.999995294f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_4096) +const float16_t twiddleCoefF16_rfft_4096[4096] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.001533980f, (float16_t)0.999998823f, + (float16_t)0.003067957f, (float16_t)0.999995294f, + (float16_t)0.004601926f, (float16_t)0.999989411f, + (float16_t)0.006135885f, (float16_t)0.999981175f, + (float16_t)0.007669829f, (float16_t)0.999970586f, + (float16_t)0.009203755f, (float16_t)0.999957645f, + (float16_t)0.010737659f, (float16_t)0.999942350f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.013805389f, (float16_t)0.999904701f, + (float16_t)0.015339206f, (float16_t)0.999882347f, + (float16_t)0.016872988f, (float16_t)0.999857641f, + (float16_t)0.018406730f, (float16_t)0.999830582f, + (float16_t)0.019940429f, (float16_t)0.999801170f, + (float16_t)0.021474080f, (float16_t)0.999769405f, + (float16_t)0.023007681f, (float16_t)0.999735288f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.026074718f, (float16_t)0.999659997f, + (float16_t)0.027608146f, (float16_t)0.999618822f, + (float16_t)0.029141509f, (float16_t)0.999575296f, + (float16_t)0.030674803f, (float16_t)0.999529418f, + (float16_t)0.032208025f, (float16_t)0.999481187f, + (float16_t)0.033741172f, (float16_t)0.999430605f, + (float16_t)0.035274239f, (float16_t)0.999377670f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.038340120f, (float16_t)0.999264747f, + (float16_t)0.039872928f, (float16_t)0.999204759f, + (float16_t)0.041405641f, (float16_t)0.999142419f, + (float16_t)0.042938257f, (float16_t)0.999077728f, + (float16_t)0.044470772f, (float16_t)0.999010686f, + (float16_t)0.046003182f, (float16_t)0.998941293f, + (float16_t)0.047535484f, (float16_t)0.998869550f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.050599749f, (float16_t)0.998719012f, + (float16_t)0.052131705f, (float16_t)0.998640218f, + (float16_t)0.053663538f, (float16_t)0.998559074f, + (float16_t)0.055195244f, (float16_t)0.998475581f, + (float16_t)0.056726821f, (float16_t)0.998389737f, + (float16_t)0.058258265f, (float16_t)0.998301545f, + (float16_t)0.059789571f, (float16_t)0.998211003f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.062851758f, (float16_t)0.998022874f, + (float16_t)0.064382631f, (float16_t)0.997925286f, + (float16_t)0.065913353f, (float16_t)0.997825350f, + (float16_t)0.067443920f, (float16_t)0.997723067f, + (float16_t)0.068974328f, (float16_t)0.997618435f, + (float16_t)0.070504573f, (float16_t)0.997511456f, + (float16_t)0.072034653f, (float16_t)0.997402130f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.075094301f, (float16_t)0.997176437f, + (float16_t)0.076623861f, (float16_t)0.997060070f, + (float16_t)0.078153242f, (float16_t)0.996941358f, + (float16_t)0.079682438f, (float16_t)0.996820299f, + (float16_t)0.081211447f, (float16_t)0.996696895f, + (float16_t)0.082740265f, (float16_t)0.996571146f, + (float16_t)0.084268888f, (float16_t)0.996443051f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.087325535f, (float16_t)0.996179829f, + (float16_t)0.088853553f, (float16_t)0.996044701f, + (float16_t)0.090381361f, (float16_t)0.995907229f, + (float16_t)0.091908956f, (float16_t)0.995767414f, + (float16_t)0.093436336f, (float16_t)0.995625256f, + (float16_t)0.094963495f, (float16_t)0.995480755f, + (float16_t)0.096490431f, (float16_t)0.995333912f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.099543619f, (float16_t)0.995033199f, + (float16_t)0.101069863f, (float16_t)0.994879331f, + (float16_t)0.102595869f, (float16_t)0.994723121f, + (float16_t)0.104121634f, (float16_t)0.994564571f, + (float16_t)0.105647154f, (float16_t)0.994403680f, + (float16_t)0.107172425f, (float16_t)0.994240449f, + (float16_t)0.108697444f, (float16_t)0.994074879f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.111746711f, (float16_t)0.993736722f, + (float16_t)0.113270952f, (float16_t)0.993564136f, + (float16_t)0.114794927f, (float16_t)0.993389211f, + (float16_t)0.116318631f, (float16_t)0.993211949f, + (float16_t)0.117842062f, (float16_t)0.993032350f, + (float16_t)0.119365215f, (float16_t)0.992850414f, + (float16_t)0.120888087f, (float16_t)0.992666142f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.123932975f, (float16_t)0.992290591f, + (float16_t)0.125454983f, (float16_t)0.992099313f, + (float16_t)0.126976696f, (float16_t)0.991905700f, + (float16_t)0.128498111f, (float16_t)0.991709754f, + (float16_t)0.130019223f, (float16_t)0.991511473f, + (float16_t)0.131540029f, (float16_t)0.991310860f, + (float16_t)0.133060525f, (float16_t)0.991107914f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.136100575f, (float16_t)0.990695025f, + (float16_t)0.137620122f, (float16_t)0.990485084f, + (float16_t)0.139139344f, (float16_t)0.990272812f, + (float16_t)0.140658239f, (float16_t)0.990058210f, + (float16_t)0.142176804f, (float16_t)0.989841278f, + (float16_t)0.143695033f, (float16_t)0.989622017f, + (float16_t)0.145212925f, (float16_t)0.989400428f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.148247679f, (float16_t)0.988950265f, + (float16_t)0.149764535f, (float16_t)0.988721692f, + (float16_t)0.151281038f, (float16_t)0.988490793f, + (float16_t)0.152797185f, (float16_t)0.988257568f, + (float16_t)0.154312973f, (float16_t)0.988022017f, + (float16_t)0.155828398f, (float16_t)0.987784142f, + (float16_t)0.157343456f, (float16_t)0.987543942f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.160372457f, (float16_t)0.987056571f, + (float16_t)0.161886394f, (float16_t)0.986809402f, + (float16_t)0.163399949f, (float16_t)0.986559910f, + (float16_t)0.164913120f, (float16_t)0.986308097f, + (float16_t)0.166425904f, (float16_t)0.986053963f, + (float16_t)0.167938295f, (float16_t)0.985797509f, + (float16_t)0.169450291f, (float16_t)0.985538735f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.172473084f, (float16_t)0.985014231f, + (float16_t)0.173983873f, (float16_t)0.984748502f, + (float16_t)0.175494253f, (float16_t)0.984480455f, + (float16_t)0.177004220f, (float16_t)0.984210092f, + (float16_t)0.178513771f, (float16_t)0.983937413f, + (float16_t)0.180022901f, (float16_t)0.983662419f, + (float16_t)0.181531608f, (float16_t)0.983385110f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.184547737f, (float16_t)0.982823551f, + (float16_t)0.186055152f, (float16_t)0.982539302f, + (float16_t)0.187562129f, (float16_t)0.982252741f, + (float16_t)0.189068664f, (float16_t)0.981963869f, + (float16_t)0.190574755f, (float16_t)0.981672686f, + (float16_t)0.192080397f, (float16_t)0.981379193f, + (float16_t)0.193585587f, (float16_t)0.981083391f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.196594598f, (float16_t)0.980484862f, + (float16_t)0.198098411f, (float16_t)0.980182136f, + (float16_t)0.199601758f, (float16_t)0.979877104f, + (float16_t)0.201104635f, (float16_t)0.979569766f, + (float16_t)0.202607039f, (float16_t)0.979260123f, + (float16_t)0.204108966f, (float16_t)0.978948175f, + (float16_t)0.205610413f, (float16_t)0.978633924f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.208611852f, (float16_t)0.977998515f, + (float16_t)0.210111837f, (float16_t)0.977677358f, + (float16_t)0.211611327f, (float16_t)0.977353900f, + (float16_t)0.213110320f, (float16_t)0.977028143f, + (float16_t)0.214608811f, (float16_t)0.976700086f, + (float16_t)0.216106797f, (float16_t)0.976369731f, + (float16_t)0.217604275f, (float16_t)0.976037079f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.220597690f, (float16_t)0.975364885f, + (float16_t)0.222093621f, (float16_t)0.975025345f, + (float16_t)0.223589029f, (float16_t)0.974683511f, + (float16_t)0.225083911f, (float16_t)0.974339383f, + (float16_t)0.226578264f, (float16_t)0.973992962f, + (float16_t)0.228072083f, (float16_t)0.973644250f, + (float16_t)0.229565366f, (float16_t)0.973293246f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.232550307f, (float16_t)0.972584369f, + (float16_t)0.234041959f, (float16_t)0.972226497f, + (float16_t)0.235533059f, (float16_t)0.971866337f, + (float16_t)0.237023606f, (float16_t)0.971503891f, + (float16_t)0.238513595f, (float16_t)0.971139158f, + (float16_t)0.240003022f, (float16_t)0.970772141f, + (float16_t)0.241491885f, (float16_t)0.970402839f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.244467903f, (float16_t)0.969657385f, + (float16_t)0.245955050f, (float16_t)0.969281235f, + (float16_t)0.247441619f, (float16_t)0.968902805f, + (float16_t)0.248927606f, (float16_t)0.968522094f, + (float16_t)0.250413007f, (float16_t)0.968139105f, + (float16_t)0.251897818f, (float16_t)0.967753837f, + (float16_t)0.253382037f, (float16_t)0.967366292f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.256348682f, (float16_t)0.966584374f, + (float16_t)0.257831102f, (float16_t)0.966190003f, + (float16_t)0.259312915f, (float16_t)0.965793359f, + (float16_t)0.260794118f, (float16_t)0.965394442f, + (float16_t)0.262274707f, (float16_t)0.964993253f, + (float16_t)0.263754679f, (float16_t)0.964589793f, + (float16_t)0.265234030f, (float16_t)0.964184064f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.268190857f, (float16_t)0.963365800f, + (float16_t)0.269668326f, (float16_t)0.962953267f, + (float16_t)0.271145160f, (float16_t)0.962538468f, + (float16_t)0.272621355f, (float16_t)0.962121404f, + (float16_t)0.274096910f, (float16_t)0.961702077f, + (float16_t)0.275571819f, (float16_t)0.961280486f, + (float16_t)0.277046080f, (float16_t)0.960856633f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.279992643f, (float16_t)0.960002146f, + (float16_t)0.281464938f, (float16_t)0.959571513f, + (float16_t)0.282936570f, (float16_t)0.959138622f, + (float16_t)0.284407537f, (float16_t)0.958703475f, + (float16_t)0.285877835f, (float16_t)0.958266071f, + (float16_t)0.287347460f, (float16_t)0.957826413f, + (float16_t)0.288816408f, (float16_t)0.957384501f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.291752263f, (float16_t)0.956493919f, + (float16_t)0.293219163f, (float16_t)0.956045251f, + (float16_t)0.294685372f, (float16_t)0.955594334f, + (float16_t)0.296150888f, (float16_t)0.955141168f, + (float16_t)0.297615707f, (float16_t)0.954685755f, + (float16_t)0.299079826f, (float16_t)0.954228095f, + (float16_t)0.300543241f, (float16_t)0.953768190f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.303467947f, (float16_t)0.952841648f, + (float16_t)0.304929230f, (float16_t)0.952375013f, + (float16_t)0.306389795f, (float16_t)0.951906137f, + (float16_t)0.307849640f, (float16_t)0.951435021f, + (float16_t)0.309308760f, (float16_t)0.950961666f, + (float16_t)0.310767153f, (float16_t)0.950486074f, + (float16_t)0.312224814f, (float16_t)0.950008245f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.315137929f, (float16_t)0.949045882f, + (float16_t)0.316593376f, (float16_t)0.948561350f, + (float16_t)0.318048077f, (float16_t)0.948074586f, + (float16_t)0.319502031f, (float16_t)0.947585591f, + (float16_t)0.320955232f, (float16_t)0.947094366f, + (float16_t)0.322407679f, (float16_t)0.946600913f, + (float16_t)0.323859367f, (float16_t)0.946105232f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.326760452f, (float16_t)0.945107193f, + (float16_t)0.328209844f, (float16_t)0.944604837f, + (float16_t)0.329658463f, (float16_t)0.944100258f, + (float16_t)0.331106306f, (float16_t)0.943593458f, + (float16_t)0.332553370f, (float16_t)0.943084437f, + (float16_t)0.333999651f, (float16_t)0.942573198f, + (float16_t)0.335445147f, (float16_t)0.942059740f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.338333767f, (float16_t)0.941026175f, + (float16_t)0.339776884f, (float16_t)0.940506071f, + (float16_t)0.341219202f, (float16_t)0.939983753f, + (float16_t)0.342660717f, (float16_t)0.939459224f, + (float16_t)0.344101426f, (float16_t)0.938932484f, + (float16_t)0.345541325f, (float16_t)0.938403534f, + (float16_t)0.346980411f, (float16_t)0.937872376f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.349856130f, (float16_t)0.936803442f, + (float16_t)0.351292756f, (float16_t)0.936265667f, + (float16_t)0.352728556f, (float16_t)0.935725689f, + (float16_t)0.354163525f, (float16_t)0.935183510f, + (float16_t)0.355597662f, (float16_t)0.934639130f, + (float16_t)0.357030961f, (float16_t)0.934092550f, + (float16_t)0.358463421f, (float16_t)0.933543773f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.361325806f, (float16_t)0.932439629f, + (float16_t)0.362755724f, (float16_t)0.931884266f, + (float16_t)0.364184790f, (float16_t)0.931326709f, + (float16_t)0.365612998f, (float16_t)0.930766961f, + (float16_t)0.367040346f, (float16_t)0.930205023f, + (float16_t)0.368466830f, (float16_t)0.929640896f, + (float16_t)0.369892447f, (float16_t)0.929074581f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.372741067f, (float16_t)0.927935395f, + (float16_t)0.374164063f, (float16_t)0.927362526f, + (float16_t)0.375586178f, (float16_t)0.926787474f, + (float16_t)0.377007410f, (float16_t)0.926210242f, + (float16_t)0.378427755f, (float16_t)0.925630831f, + (float16_t)0.379847209f, (float16_t)0.925049241f, + (float16_t)0.381265769f, (float16_t)0.924465474f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.384100195f, (float16_t)0.923291417f, + (float16_t)0.385516054f, (float16_t)0.922701128f, + (float16_t)0.386931006f, (float16_t)0.922108669f, + (float16_t)0.388345047f, (float16_t)0.921514039f, + (float16_t)0.389758174f, (float16_t)0.920917242f, + (float16_t)0.391170384f, (float16_t)0.920318277f, + (float16_t)0.392581674f, (float16_t)0.919717146f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.395401479f, (float16_t)0.918508394f, + (float16_t)0.396809987f, (float16_t)0.917900776f, + (float16_t)0.398217562f, (float16_t)0.917290997f, + (float16_t)0.399624200f, (float16_t)0.916679060f, + (float16_t)0.401029897f, (float16_t)0.916064966f, + (float16_t)0.402434651f, (float16_t)0.915448716f, + (float16_t)0.403838458f, (float16_t)0.914830312f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.406643217f, (float16_t)0.913587048f, + (float16_t)0.408044163f, (float16_t)0.912962190f, + (float16_t)0.409444149f, (float16_t)0.912335185f, + (float16_t)0.410843171f, (float16_t)0.911706032f, + (float16_t)0.412241227f, (float16_t)0.911074734f, + (float16_t)0.413638312f, (float16_t)0.910441292f, + (float16_t)0.415034424f, (float16_t)0.909805708f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.417823716f, (float16_t)0.908528119f, + (float16_t)0.419216888f, (float16_t)0.907886116f, + (float16_t)0.420609074f, (float16_t)0.907241978f, + (float16_t)0.422000271f, (float16_t)0.906595705f, + (float16_t)0.423390474f, (float16_t)0.905947298f, + (float16_t)0.424779681f, (float16_t)0.905296759f, + (float16_t)0.426167889f, (float16_t)0.904644091f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.428941292f, (float16_t)0.903332368f, + (float16_t)0.430326481f, (float16_t)0.902673318f, + (float16_t)0.431710658f, (float16_t)0.902012144f, + (float16_t)0.433093819f, (float16_t)0.901348847f, + (float16_t)0.434475961f, (float16_t)0.900683429f, + (float16_t)0.435857080f, (float16_t)0.900015892f, + (float16_t)0.437237174f, (float16_t)0.899346237f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.439994271f, (float16_t)0.898000580f, + (float16_t)0.441371269f, (float16_t)0.897324581f, + (float16_t)0.442747228f, (float16_t)0.896646470f, + (float16_t)0.444122145f, (float16_t)0.895966250f, + (float16_t)0.445496017f, (float16_t)0.895283921f, + (float16_t)0.446868840f, (float16_t)0.894599486f, + (float16_t)0.448240612f, (float16_t)0.893912945f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.450980989f, (float16_t)0.892533555f, + (float16_t)0.452349587f, (float16_t)0.891840709f, + (float16_t)0.453717121f, (float16_t)0.891145765f, + (float16_t)0.455083587f, (float16_t)0.890448723f, + (float16_t)0.456448982f, (float16_t)0.889749586f, + (float16_t)0.457813304f, (float16_t)0.889048356f, + (float16_t)0.459176548f, (float16_t)0.888345033f, + (float16_t)0.460538711f, (float16_t)0.887639620f, + (float16_t)0.461899791f, (float16_t)0.886932119f, + (float16_t)0.463259784f, (float16_t)0.886222530f, + (float16_t)0.464618686f, (float16_t)0.885510856f, + (float16_t)0.465976496f, (float16_t)0.884797098f, + (float16_t)0.467333209f, (float16_t)0.884081259f, + (float16_t)0.468688822f, (float16_t)0.883363339f, + (float16_t)0.470043332f, (float16_t)0.882643340f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.472749032f, (float16_t)0.881197113f, + (float16_t)0.474100215f, (float16_t)0.880470889f, + (float16_t)0.475450282f, (float16_t)0.879742593f, + (float16_t)0.476799230f, (float16_t)0.879012226f, + (float16_t)0.478147056f, (float16_t)0.878279792f, + (float16_t)0.479493758f, (float16_t)0.877545290f, + (float16_t)0.480839331f, (float16_t)0.876808724f, + (float16_t)0.482183772f, (float16_t)0.876070094f, + (float16_t)0.483527079f, (float16_t)0.875329403f, + (float16_t)0.484869248f, (float16_t)0.874586652f, + (float16_t)0.486210276f, (float16_t)0.873841843f, + (float16_t)0.487550160f, (float16_t)0.873094978f, + (float16_t)0.488888897f, (float16_t)0.872346059f, + (float16_t)0.490226483f, (float16_t)0.871595087f, + (float16_t)0.491562916f, (float16_t)0.870842063f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.494232309f, (float16_t)0.869329871f, + (float16_t)0.495565262f, (float16_t)0.868570706f, + (float16_t)0.496897049f, (float16_t)0.867809497f, + (float16_t)0.498227667f, (float16_t)0.867046246f, + (float16_t)0.499557113f, (float16_t)0.866280954f, + (float16_t)0.500885383f, (float16_t)0.865513624f, + (float16_t)0.502212474f, (float16_t)0.864744258f, + (float16_t)0.503538384f, (float16_t)0.863972856f, + (float16_t)0.504863109f, (float16_t)0.863199422f, + (float16_t)0.506186645f, (float16_t)0.862423956f, + (float16_t)0.507508991f, (float16_t)0.861646461f, + (float16_t)0.508830143f, (float16_t)0.860866939f, + (float16_t)0.510150097f, (float16_t)0.860085390f, + (float16_t)0.511468850f, (float16_t)0.859301818f, + (float16_t)0.512786401f, (float16_t)0.858516224f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.515417878f, (float16_t)0.856938977f, + (float16_t)0.516731799f, (float16_t)0.856147328f, + (float16_t)0.518044504f, (float16_t)0.855353665f, + (float16_t)0.519355990f, (float16_t)0.854557988f, + (float16_t)0.520666254f, (float16_t)0.853760301f, + (float16_t)0.521975293f, (float16_t)0.852960605f, + (float16_t)0.523283103f, (float16_t)0.852158902f, + (float16_t)0.524589683f, (float16_t)0.851355193f, + (float16_t)0.525895027f, (float16_t)0.850549481f, + (float16_t)0.527199135f, (float16_t)0.849741768f, + (float16_t)0.528502002f, (float16_t)0.848932055f, + (float16_t)0.529803625f, (float16_t)0.848120345f, + (float16_t)0.531104001f, (float16_t)0.847306639f, + (float16_t)0.532403128f, (float16_t)0.846490939f, + (float16_t)0.533701002f, (float16_t)0.845673247f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.536292979f, (float16_t)0.844031895f, + (float16_t)0.537587076f, (float16_t)0.843208240f, + (float16_t)0.538879909f, (float16_t)0.842382600f, + (float16_t)0.540171473f, (float16_t)0.841554977f, + (float16_t)0.541461766f, (float16_t)0.840725375f, + (float16_t)0.542750785f, (float16_t)0.839893794f, + (float16_t)0.544038527f, (float16_t)0.839060237f, + (float16_t)0.545324988f, (float16_t)0.838224706f, + (float16_t)0.546610167f, (float16_t)0.837387202f, + (float16_t)0.547894059f, (float16_t)0.836547727f, + (float16_t)0.549176662f, (float16_t)0.835706284f, + (float16_t)0.550457973f, (float16_t)0.834862875f, + (float16_t)0.551737988f, (float16_t)0.834017501f, + (float16_t)0.553016706f, (float16_t)0.833170165f, + (float16_t)0.554294121f, (float16_t)0.832320868f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.556845037f, (float16_t)0.830616400f, + (float16_t)0.558118531f, (float16_t)0.829761234f, + (float16_t)0.559390712f, (float16_t)0.828904115f, + (float16_t)0.560661576f, (float16_t)0.828045045f, + (float16_t)0.561931121f, (float16_t)0.827184027f, + (float16_t)0.563199344f, (float16_t)0.826321063f, + (float16_t)0.564466242f, (float16_t)0.825456154f, + (float16_t)0.565731811f, (float16_t)0.824589303f, + (float16_t)0.566996049f, (float16_t)0.823720511f, + (float16_t)0.568258953f, (float16_t)0.822849781f, + (float16_t)0.569520519f, (float16_t)0.821977115f, + (float16_t)0.570780746f, (float16_t)0.821102515f, + (float16_t)0.572039629f, (float16_t)0.820225983f, + (float16_t)0.573297167f, (float16_t)0.819347520f, + (float16_t)0.574553355f, (float16_t)0.818467130f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.577061673f, (float16_t)0.816700573f, + (float16_t)0.578313796f, (float16_t)0.815814411f, + (float16_t)0.579564559f, (float16_t)0.814926329f, + (float16_t)0.580813958f, (float16_t)0.814036330f, + (float16_t)0.582061990f, (float16_t)0.813144415f, + (float16_t)0.583308653f, (float16_t)0.812250587f, + (float16_t)0.584553943f, (float16_t)0.811354847f, + (float16_t)0.585797857f, (float16_t)0.810457198f, + (float16_t)0.587040394f, (float16_t)0.809557642f, + (float16_t)0.588281548f, (float16_t)0.808656182f, + (float16_t)0.589521319f, (float16_t)0.807752818f, + (float16_t)0.590759702f, (float16_t)0.806847554f, + (float16_t)0.591996695f, (float16_t)0.805940391f, + (float16_t)0.593232295f, (float16_t)0.805031331f, + (float16_t)0.594466499f, (float16_t)0.804120377f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.596930708f, (float16_t)0.802292796f, + (float16_t)0.598160707f, (float16_t)0.801376172f, + (float16_t)0.599389298f, (float16_t)0.800457662f, + (float16_t)0.600616479f, (float16_t)0.799537269f, + (float16_t)0.601842247f, (float16_t)0.798614995f, + (float16_t)0.603066599f, (float16_t)0.797690841f, + (float16_t)0.604289531f, (float16_t)0.796764810f, + (float16_t)0.605511041f, (float16_t)0.795836905f, + (float16_t)0.606731127f, (float16_t)0.794907126f, + (float16_t)0.607949785f, (float16_t)0.793975478f, + (float16_t)0.609167012f, (float16_t)0.793041960f, + (float16_t)0.610382806f, (float16_t)0.792106577f, + (float16_t)0.611597164f, (float16_t)0.791169330f, + (float16_t)0.612810082f, (float16_t)0.790230221f, + (float16_t)0.614021559f, (float16_t)0.789289253f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.616440175f, (float16_t)0.787401747f, + (float16_t)0.617647308f, (float16_t)0.786455214f, + (float16_t)0.618852988f, (float16_t)0.785506830f, + (float16_t)0.620057212f, (float16_t)0.784556597f, + (float16_t)0.621259977f, (float16_t)0.783604519f, + (float16_t)0.622461279f, (float16_t)0.782650596f, + (float16_t)0.623661118f, (float16_t)0.781694832f, + (float16_t)0.624859488f, (float16_t)0.780737229f, + (float16_t)0.626056388f, (float16_t)0.779777788f, + (float16_t)0.627251815f, (float16_t)0.778816512f, + (float16_t)0.628445767f, (float16_t)0.777853404f, + (float16_t)0.629638239f, (float16_t)0.776888466f, + (float16_t)0.630829230f, (float16_t)0.775921699f, + (float16_t)0.632018736f, (float16_t)0.774953107f, + (float16_t)0.633206755f, (float16_t)0.773982691f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.635578320f, (float16_t)0.772036397f, + (float16_t)0.636761861f, (float16_t)0.771060524f, + (float16_t)0.637943904f, (float16_t)0.770082837f, + (float16_t)0.639124445f, (float16_t)0.769103338f, + (float16_t)0.640303482f, (float16_t)0.768122029f, + (float16_t)0.641481013f, (float16_t)0.767138912f, + (float16_t)0.642657034f, (float16_t)0.766153990f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.645004537f, (float16_t)0.764178741f, + (float16_t)0.646176013f, (float16_t)0.763188417f, + (float16_t)0.647345969f, (float16_t)0.762196298f, + (float16_t)0.648514401f, (float16_t)0.761202385f, + (float16_t)0.649681307f, (float16_t)0.760206682f, + (float16_t)0.650846685f, (float16_t)0.759209189f, + (float16_t)0.652010531f, (float16_t)0.758209910f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.654333618f, (float16_t)0.756206001f, + (float16_t)0.655492853f, (float16_t)0.755201377f, + (float16_t)0.656650546f, (float16_t)0.754194975f, + (float16_t)0.657806693f, (float16_t)0.753186799f, + (float16_t)0.658961293f, (float16_t)0.752176850f, + (float16_t)0.660114342f, (float16_t)0.751165132f, + (float16_t)0.661265838f, (float16_t)0.750151646f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.663564159f, (float16_t)0.748119380f, + (float16_t)0.664710978f, (float16_t)0.747100606f, + (float16_t)0.665856234f, (float16_t)0.746080074f, + (float16_t)0.666999922f, (float16_t)0.745057785f, + (float16_t)0.668142041f, (float16_t)0.744033744f, + (float16_t)0.669282588f, (float16_t)0.743007952f, + (float16_t)0.670421560f, (float16_t)0.741980412f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.672694769f, (float16_t)0.739920095f, + (float16_t)0.673829000f, (float16_t)0.738887324f, + (float16_t)0.674961646f, (float16_t)0.737852815f, + (float16_t)0.676092704f, (float16_t)0.736816569f, + (float16_t)0.677222170f, (float16_t)0.735778589f, + (float16_t)0.678350043f, (float16_t)0.734738878f, + (float16_t)0.679476320f, (float16_t)0.733697438f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.681724074f, (float16_t)0.731609381f, + (float16_t)0.682845546f, (float16_t)0.730562769f, + (float16_t)0.683965412f, (float16_t)0.729514438f, + (float16_t)0.685083668f, (float16_t)0.728464390f, + (float16_t)0.686200312f, (float16_t)0.727412629f, + (float16_t)0.687315341f, (float16_t)0.726359155f, + (float16_t)0.688428753f, (float16_t)0.725303972f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.690650714f, (float16_t)0.723188489f, + (float16_t)0.691759258f, (float16_t)0.722128194f, + (float16_t)0.692866175f, (float16_t)0.721066199f, + (float16_t)0.693971461f, (float16_t)0.720002508f, + (float16_t)0.695075114f, (float16_t)0.718937122f, + (float16_t)0.696177131f, (float16_t)0.717870045f, + (float16_t)0.697277511f, (float16_t)0.716801279f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.699473345f, (float16_t)0.714658688f, + (float16_t)0.700568794f, (float16_t)0.713584869f, + (float16_t)0.701662595f, (float16_t)0.712509371f, + (float16_t)0.702754744f, (float16_t)0.711432196f, + (float16_t)0.703845241f, (float16_t)0.710353347f, + (float16_t)0.704934080f, (float16_t)0.709272826f, + (float16_t)0.706021261f, (float16_t)0.708190637f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.708190637f, (float16_t)0.706021261f, + (float16_t)0.709272826f, (float16_t)0.704934080f, + (float16_t)0.710353347f, (float16_t)0.703845241f, + (float16_t)0.711432196f, (float16_t)0.702754744f, + (float16_t)0.712509371f, (float16_t)0.701662595f, + (float16_t)0.713584869f, (float16_t)0.700568794f, + (float16_t)0.714658688f, (float16_t)0.699473345f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.716801279f, (float16_t)0.697277511f, + (float16_t)0.717870045f, (float16_t)0.696177131f, + (float16_t)0.718937122f, (float16_t)0.695075114f, + (float16_t)0.720002508f, (float16_t)0.693971461f, + (float16_t)0.721066199f, (float16_t)0.692866175f, + (float16_t)0.722128194f, (float16_t)0.691759258f, + (float16_t)0.723188489f, (float16_t)0.690650714f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.725303972f, (float16_t)0.688428753f, + (float16_t)0.726359155f, (float16_t)0.687315341f, + (float16_t)0.727412629f, (float16_t)0.686200312f, + (float16_t)0.728464390f, (float16_t)0.685083668f, + (float16_t)0.729514438f, (float16_t)0.683965412f, + (float16_t)0.730562769f, (float16_t)0.682845546f, + (float16_t)0.731609381f, (float16_t)0.681724074f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.733697438f, (float16_t)0.679476320f, + (float16_t)0.734738878f, (float16_t)0.678350043f, + (float16_t)0.735778589f, (float16_t)0.677222170f, + (float16_t)0.736816569f, (float16_t)0.676092704f, + (float16_t)0.737852815f, (float16_t)0.674961646f, + (float16_t)0.738887324f, (float16_t)0.673829000f, + (float16_t)0.739920095f, (float16_t)0.672694769f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.741980412f, (float16_t)0.670421560f, + (float16_t)0.743007952f, (float16_t)0.669282588f, + (float16_t)0.744033744f, (float16_t)0.668142041f, + (float16_t)0.745057785f, (float16_t)0.666999922f, + (float16_t)0.746080074f, (float16_t)0.665856234f, + (float16_t)0.747100606f, (float16_t)0.664710978f, + (float16_t)0.748119380f, (float16_t)0.663564159f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.750151646f, (float16_t)0.661265838f, + (float16_t)0.751165132f, (float16_t)0.660114342f, + (float16_t)0.752176850f, (float16_t)0.658961293f, + (float16_t)0.753186799f, (float16_t)0.657806693f, + (float16_t)0.754194975f, (float16_t)0.656650546f, + (float16_t)0.755201377f, (float16_t)0.655492853f, + (float16_t)0.756206001f, (float16_t)0.654333618f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.758209910f, (float16_t)0.652010531f, + (float16_t)0.759209189f, (float16_t)0.650846685f, + (float16_t)0.760206682f, (float16_t)0.649681307f, + (float16_t)0.761202385f, (float16_t)0.648514401f, + (float16_t)0.762196298f, (float16_t)0.647345969f, + (float16_t)0.763188417f, (float16_t)0.646176013f, + (float16_t)0.764178741f, (float16_t)0.645004537f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.766153990f, (float16_t)0.642657034f, + (float16_t)0.767138912f, (float16_t)0.641481013f, + (float16_t)0.768122029f, (float16_t)0.640303482f, + (float16_t)0.769103338f, (float16_t)0.639124445f, + (float16_t)0.770082837f, (float16_t)0.637943904f, + (float16_t)0.771060524f, (float16_t)0.636761861f, + (float16_t)0.772036397f, (float16_t)0.635578320f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.773982691f, (float16_t)0.633206755f, + (float16_t)0.774953107f, (float16_t)0.632018736f, + (float16_t)0.775921699f, (float16_t)0.630829230f, + (float16_t)0.776888466f, (float16_t)0.629638239f, + (float16_t)0.777853404f, (float16_t)0.628445767f, + (float16_t)0.778816512f, (float16_t)0.627251815f, + (float16_t)0.779777788f, (float16_t)0.626056388f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.781694832f, (float16_t)0.623661118f, + (float16_t)0.782650596f, (float16_t)0.622461279f, + (float16_t)0.783604519f, (float16_t)0.621259977f, + (float16_t)0.784556597f, (float16_t)0.620057212f, + (float16_t)0.785506830f, (float16_t)0.618852988f, + (float16_t)0.786455214f, (float16_t)0.617647308f, + (float16_t)0.787401747f, (float16_t)0.616440175f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.789289253f, (float16_t)0.614021559f, + (float16_t)0.790230221f, (float16_t)0.612810082f, + (float16_t)0.791169330f, (float16_t)0.611597164f, + (float16_t)0.792106577f, (float16_t)0.610382806f, + (float16_t)0.793041960f, (float16_t)0.609167012f, + (float16_t)0.793975478f, (float16_t)0.607949785f, + (float16_t)0.794907126f, (float16_t)0.606731127f, + (float16_t)0.795836905f, (float16_t)0.605511041f, + (float16_t)0.796764810f, (float16_t)0.604289531f, + (float16_t)0.797690841f, (float16_t)0.603066599f, + (float16_t)0.798614995f, (float16_t)0.601842247f, + (float16_t)0.799537269f, (float16_t)0.600616479f, + (float16_t)0.800457662f, (float16_t)0.599389298f, + (float16_t)0.801376172f, (float16_t)0.598160707f, + (float16_t)0.802292796f, (float16_t)0.596930708f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.804120377f, (float16_t)0.594466499f, + (float16_t)0.805031331f, (float16_t)0.593232295f, + (float16_t)0.805940391f, (float16_t)0.591996695f, + (float16_t)0.806847554f, (float16_t)0.590759702f, + (float16_t)0.807752818f, (float16_t)0.589521319f, + (float16_t)0.808656182f, (float16_t)0.588281548f, + (float16_t)0.809557642f, (float16_t)0.587040394f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.811354847f, (float16_t)0.584553943f, + (float16_t)0.812250587f, (float16_t)0.583308653f, + (float16_t)0.813144415f, (float16_t)0.582061990f, + (float16_t)0.814036330f, (float16_t)0.580813958f, + (float16_t)0.814926329f, (float16_t)0.579564559f, + (float16_t)0.815814411f, (float16_t)0.578313796f, + (float16_t)0.816700573f, (float16_t)0.577061673f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.818467130f, (float16_t)0.574553355f, + (float16_t)0.819347520f, (float16_t)0.573297167f, + (float16_t)0.820225983f, (float16_t)0.572039629f, + (float16_t)0.821102515f, (float16_t)0.570780746f, + (float16_t)0.821977115f, (float16_t)0.569520519f, + (float16_t)0.822849781f, (float16_t)0.568258953f, + (float16_t)0.823720511f, (float16_t)0.566996049f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.825456154f, (float16_t)0.564466242f, + (float16_t)0.826321063f, (float16_t)0.563199344f, + (float16_t)0.827184027f, (float16_t)0.561931121f, + (float16_t)0.828045045f, (float16_t)0.560661576f, + (float16_t)0.828904115f, (float16_t)0.559390712f, + (float16_t)0.829761234f, (float16_t)0.558118531f, + (float16_t)0.830616400f, (float16_t)0.556845037f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.832320868f, (float16_t)0.554294121f, + (float16_t)0.833170165f, (float16_t)0.553016706f, + (float16_t)0.834017501f, (float16_t)0.551737988f, + (float16_t)0.834862875f, (float16_t)0.550457973f, + (float16_t)0.835706284f, (float16_t)0.549176662f, + (float16_t)0.836547727f, (float16_t)0.547894059f, + (float16_t)0.837387202f, (float16_t)0.546610167f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.839060237f, (float16_t)0.544038527f, + (float16_t)0.839893794f, (float16_t)0.542750785f, + (float16_t)0.840725375f, (float16_t)0.541461766f, + (float16_t)0.841554977f, (float16_t)0.540171473f, + (float16_t)0.842382600f, (float16_t)0.538879909f, + (float16_t)0.843208240f, (float16_t)0.537587076f, + (float16_t)0.844031895f, (float16_t)0.536292979f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.845673247f, (float16_t)0.533701002f, + (float16_t)0.846490939f, (float16_t)0.532403128f, + (float16_t)0.847306639f, (float16_t)0.531104001f, + (float16_t)0.848120345f, (float16_t)0.529803625f, + (float16_t)0.848932055f, (float16_t)0.528502002f, + (float16_t)0.849741768f, (float16_t)0.527199135f, + (float16_t)0.850549481f, (float16_t)0.525895027f, + (float16_t)0.851355193f, (float16_t)0.524589683f, + (float16_t)0.852158902f, (float16_t)0.523283103f, + (float16_t)0.852960605f, (float16_t)0.521975293f, + (float16_t)0.853760301f, (float16_t)0.520666254f, + (float16_t)0.854557988f, (float16_t)0.519355990f, + (float16_t)0.855353665f, (float16_t)0.518044504f, + (float16_t)0.856147328f, (float16_t)0.516731799f, + (float16_t)0.856938977f, (float16_t)0.515417878f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.858516224f, (float16_t)0.512786401f, + (float16_t)0.859301818f, (float16_t)0.511468850f, + (float16_t)0.860085390f, (float16_t)0.510150097f, + (float16_t)0.860866939f, (float16_t)0.508830143f, + (float16_t)0.861646461f, (float16_t)0.507508991f, + (float16_t)0.862423956f, (float16_t)0.506186645f, + (float16_t)0.863199422f, (float16_t)0.504863109f, + (float16_t)0.863972856f, (float16_t)0.503538384f, + (float16_t)0.864744258f, (float16_t)0.502212474f, + (float16_t)0.865513624f, (float16_t)0.500885383f, + (float16_t)0.866280954f, (float16_t)0.499557113f, + (float16_t)0.867046246f, (float16_t)0.498227667f, + (float16_t)0.867809497f, (float16_t)0.496897049f, + (float16_t)0.868570706f, (float16_t)0.495565262f, + (float16_t)0.869329871f, (float16_t)0.494232309f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.870842063f, (float16_t)0.491562916f, + (float16_t)0.871595087f, (float16_t)0.490226483f, + (float16_t)0.872346059f, (float16_t)0.488888897f, + (float16_t)0.873094978f, (float16_t)0.487550160f, + (float16_t)0.873841843f, (float16_t)0.486210276f, + (float16_t)0.874586652f, (float16_t)0.484869248f, + (float16_t)0.875329403f, (float16_t)0.483527079f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.876808724f, (float16_t)0.480839331f, + (float16_t)0.877545290f, (float16_t)0.479493758f, + (float16_t)0.878279792f, (float16_t)0.478147056f, + (float16_t)0.879012226f, (float16_t)0.476799230f, + (float16_t)0.879742593f, (float16_t)0.475450282f, + (float16_t)0.880470889f, (float16_t)0.474100215f, + (float16_t)0.881197113f, (float16_t)0.472749032f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.882643340f, (float16_t)0.470043332f, + (float16_t)0.883363339f, (float16_t)0.468688822f, + (float16_t)0.884081259f, (float16_t)0.467333209f, + (float16_t)0.884797098f, (float16_t)0.465976496f, + (float16_t)0.885510856f, (float16_t)0.464618686f, + (float16_t)0.886222530f, (float16_t)0.463259784f, + (float16_t)0.886932119f, (float16_t)0.461899791f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.888345033f, (float16_t)0.459176548f, + (float16_t)0.889048356f, (float16_t)0.457813304f, + (float16_t)0.889749586f, (float16_t)0.456448982f, + (float16_t)0.890448723f, (float16_t)0.455083587f, + (float16_t)0.891145765f, (float16_t)0.453717121f, + (float16_t)0.891840709f, (float16_t)0.452349587f, + (float16_t)0.892533555f, (float16_t)0.450980989f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.893912945f, (float16_t)0.448240612f, + (float16_t)0.894599486f, (float16_t)0.446868840f, + (float16_t)0.895283921f, (float16_t)0.445496017f, + (float16_t)0.895966250f, (float16_t)0.444122145f, + (float16_t)0.896646470f, (float16_t)0.442747228f, + (float16_t)0.897324581f, (float16_t)0.441371269f, + (float16_t)0.898000580f, (float16_t)0.439994271f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.899346237f, (float16_t)0.437237174f, + (float16_t)0.900015892f, (float16_t)0.435857080f, + (float16_t)0.900683429f, (float16_t)0.434475961f, + (float16_t)0.901348847f, (float16_t)0.433093819f, + (float16_t)0.902012144f, (float16_t)0.431710658f, + (float16_t)0.902673318f, (float16_t)0.430326481f, + (float16_t)0.903332368f, (float16_t)0.428941292f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.904644091f, (float16_t)0.426167889f, + (float16_t)0.905296759f, (float16_t)0.424779681f, + (float16_t)0.905947298f, (float16_t)0.423390474f, + (float16_t)0.906595705f, (float16_t)0.422000271f, + (float16_t)0.907241978f, (float16_t)0.420609074f, + (float16_t)0.907886116f, (float16_t)0.419216888f, + (float16_t)0.908528119f, (float16_t)0.417823716f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.909805708f, (float16_t)0.415034424f, + (float16_t)0.910441292f, (float16_t)0.413638312f, + (float16_t)0.911074734f, (float16_t)0.412241227f, + (float16_t)0.911706032f, (float16_t)0.410843171f, + (float16_t)0.912335185f, (float16_t)0.409444149f, + (float16_t)0.912962190f, (float16_t)0.408044163f, + (float16_t)0.913587048f, (float16_t)0.406643217f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.914830312f, (float16_t)0.403838458f, + (float16_t)0.915448716f, (float16_t)0.402434651f, + (float16_t)0.916064966f, (float16_t)0.401029897f, + (float16_t)0.916679060f, (float16_t)0.399624200f, + (float16_t)0.917290997f, (float16_t)0.398217562f, + (float16_t)0.917900776f, (float16_t)0.396809987f, + (float16_t)0.918508394f, (float16_t)0.395401479f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.919717146f, (float16_t)0.392581674f, + (float16_t)0.920318277f, (float16_t)0.391170384f, + (float16_t)0.920917242f, (float16_t)0.389758174f, + (float16_t)0.921514039f, (float16_t)0.388345047f, + (float16_t)0.922108669f, (float16_t)0.386931006f, + (float16_t)0.922701128f, (float16_t)0.385516054f, + (float16_t)0.923291417f, (float16_t)0.384100195f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.924465474f, (float16_t)0.381265769f, + (float16_t)0.925049241f, (float16_t)0.379847209f, + (float16_t)0.925630831f, (float16_t)0.378427755f, + (float16_t)0.926210242f, (float16_t)0.377007410f, + (float16_t)0.926787474f, (float16_t)0.375586178f, + (float16_t)0.927362526f, (float16_t)0.374164063f, + (float16_t)0.927935395f, (float16_t)0.372741067f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.929074581f, (float16_t)0.369892447f, + (float16_t)0.929640896f, (float16_t)0.368466830f, + (float16_t)0.930205023f, (float16_t)0.367040346f, + (float16_t)0.930766961f, (float16_t)0.365612998f, + (float16_t)0.931326709f, (float16_t)0.364184790f, + (float16_t)0.931884266f, (float16_t)0.362755724f, + (float16_t)0.932439629f, (float16_t)0.361325806f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.933543773f, (float16_t)0.358463421f, + (float16_t)0.934092550f, (float16_t)0.357030961f, + (float16_t)0.934639130f, (float16_t)0.355597662f, + (float16_t)0.935183510f, (float16_t)0.354163525f, + (float16_t)0.935725689f, (float16_t)0.352728556f, + (float16_t)0.936265667f, (float16_t)0.351292756f, + (float16_t)0.936803442f, (float16_t)0.349856130f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.937872376f, (float16_t)0.346980411f, + (float16_t)0.938403534f, (float16_t)0.345541325f, + (float16_t)0.938932484f, (float16_t)0.344101426f, + (float16_t)0.939459224f, (float16_t)0.342660717f, + (float16_t)0.939983753f, (float16_t)0.341219202f, + (float16_t)0.940506071f, (float16_t)0.339776884f, + (float16_t)0.941026175f, (float16_t)0.338333767f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.942059740f, (float16_t)0.335445147f, + (float16_t)0.942573198f, (float16_t)0.333999651f, + (float16_t)0.943084437f, (float16_t)0.332553370f, + (float16_t)0.943593458f, (float16_t)0.331106306f, + (float16_t)0.944100258f, (float16_t)0.329658463f, + (float16_t)0.944604837f, (float16_t)0.328209844f, + (float16_t)0.945107193f, (float16_t)0.326760452f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.946105232f, (float16_t)0.323859367f, + (float16_t)0.946600913f, (float16_t)0.322407679f, + (float16_t)0.947094366f, (float16_t)0.320955232f, + (float16_t)0.947585591f, (float16_t)0.319502031f, + (float16_t)0.948074586f, (float16_t)0.318048077f, + (float16_t)0.948561350f, (float16_t)0.316593376f, + (float16_t)0.949045882f, (float16_t)0.315137929f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.950008245f, (float16_t)0.312224814f, + (float16_t)0.950486074f, (float16_t)0.310767153f, + (float16_t)0.950961666f, (float16_t)0.309308760f, + (float16_t)0.951435021f, (float16_t)0.307849640f, + (float16_t)0.951906137f, (float16_t)0.306389795f, + (float16_t)0.952375013f, (float16_t)0.304929230f, + (float16_t)0.952841648f, (float16_t)0.303467947f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.953768190f, (float16_t)0.300543241f, + (float16_t)0.954228095f, (float16_t)0.299079826f, + (float16_t)0.954685755f, (float16_t)0.297615707f, + (float16_t)0.955141168f, (float16_t)0.296150888f, + (float16_t)0.955594334f, (float16_t)0.294685372f, + (float16_t)0.956045251f, (float16_t)0.293219163f, + (float16_t)0.956493919f, (float16_t)0.291752263f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.957384501f, (float16_t)0.288816408f, + (float16_t)0.957826413f, (float16_t)0.287347460f, + (float16_t)0.958266071f, (float16_t)0.285877835f, + (float16_t)0.958703475f, (float16_t)0.284407537f, + (float16_t)0.959138622f, (float16_t)0.282936570f, + (float16_t)0.959571513f, (float16_t)0.281464938f, + (float16_t)0.960002146f, (float16_t)0.279992643f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.960856633f, (float16_t)0.277046080f, + (float16_t)0.961280486f, (float16_t)0.275571819f, + (float16_t)0.961702077f, (float16_t)0.274096910f, + (float16_t)0.962121404f, (float16_t)0.272621355f, + (float16_t)0.962538468f, (float16_t)0.271145160f, + (float16_t)0.962953267f, (float16_t)0.269668326f, + (float16_t)0.963365800f, (float16_t)0.268190857f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.964184064f, (float16_t)0.265234030f, + (float16_t)0.964589793f, (float16_t)0.263754679f, + (float16_t)0.964993253f, (float16_t)0.262274707f, + (float16_t)0.965394442f, (float16_t)0.260794118f, + (float16_t)0.965793359f, (float16_t)0.259312915f, + (float16_t)0.966190003f, (float16_t)0.257831102f, + (float16_t)0.966584374f, (float16_t)0.256348682f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.967366292f, (float16_t)0.253382037f, + (float16_t)0.967753837f, (float16_t)0.251897818f, + (float16_t)0.968139105f, (float16_t)0.250413007f, + (float16_t)0.968522094f, (float16_t)0.248927606f, + (float16_t)0.968902805f, (float16_t)0.247441619f, + (float16_t)0.969281235f, (float16_t)0.245955050f, + (float16_t)0.969657385f, (float16_t)0.244467903f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.970402839f, (float16_t)0.241491885f, + (float16_t)0.970772141f, (float16_t)0.240003022f, + (float16_t)0.971139158f, (float16_t)0.238513595f, + (float16_t)0.971503891f, (float16_t)0.237023606f, + (float16_t)0.971866337f, (float16_t)0.235533059f, + (float16_t)0.972226497f, (float16_t)0.234041959f, + (float16_t)0.972584369f, (float16_t)0.232550307f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.973293246f, (float16_t)0.229565366f, + (float16_t)0.973644250f, (float16_t)0.228072083f, + (float16_t)0.973992962f, (float16_t)0.226578264f, + (float16_t)0.974339383f, (float16_t)0.225083911f, + (float16_t)0.974683511f, (float16_t)0.223589029f, + (float16_t)0.975025345f, (float16_t)0.222093621f, + (float16_t)0.975364885f, (float16_t)0.220597690f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.976037079f, (float16_t)0.217604275f, + (float16_t)0.976369731f, (float16_t)0.216106797f, + (float16_t)0.976700086f, (float16_t)0.214608811f, + (float16_t)0.977028143f, (float16_t)0.213110320f, + (float16_t)0.977353900f, (float16_t)0.211611327f, + (float16_t)0.977677358f, (float16_t)0.210111837f, + (float16_t)0.977998515f, (float16_t)0.208611852f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.978633924f, (float16_t)0.205610413f, + (float16_t)0.978948175f, (float16_t)0.204108966f, + (float16_t)0.979260123f, (float16_t)0.202607039f, + (float16_t)0.979569766f, (float16_t)0.201104635f, + (float16_t)0.979877104f, (float16_t)0.199601758f, + (float16_t)0.980182136f, (float16_t)0.198098411f, + (float16_t)0.980484862f, (float16_t)0.196594598f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.981083391f, (float16_t)0.193585587f, + (float16_t)0.981379193f, (float16_t)0.192080397f, + (float16_t)0.981672686f, (float16_t)0.190574755f, + (float16_t)0.981963869f, (float16_t)0.189068664f, + (float16_t)0.982252741f, (float16_t)0.187562129f, + (float16_t)0.982539302f, (float16_t)0.186055152f, + (float16_t)0.982823551f, (float16_t)0.184547737f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.983385110f, (float16_t)0.181531608f, + (float16_t)0.983662419f, (float16_t)0.180022901f, + (float16_t)0.983937413f, (float16_t)0.178513771f, + (float16_t)0.984210092f, (float16_t)0.177004220f, + (float16_t)0.984480455f, (float16_t)0.175494253f, + (float16_t)0.984748502f, (float16_t)0.173983873f, + (float16_t)0.985014231f, (float16_t)0.172473084f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.985538735f, (float16_t)0.169450291f, + (float16_t)0.985797509f, (float16_t)0.167938295f, + (float16_t)0.986053963f, (float16_t)0.166425904f, + (float16_t)0.986308097f, (float16_t)0.164913120f, + (float16_t)0.986559910f, (float16_t)0.163399949f, + (float16_t)0.986809402f, (float16_t)0.161886394f, + (float16_t)0.987056571f, (float16_t)0.160372457f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.987543942f, (float16_t)0.157343456f, + (float16_t)0.987784142f, (float16_t)0.155828398f, + (float16_t)0.988022017f, (float16_t)0.154312973f, + (float16_t)0.988257568f, (float16_t)0.152797185f, + (float16_t)0.988490793f, (float16_t)0.151281038f, + (float16_t)0.988721692f, (float16_t)0.149764535f, + (float16_t)0.988950265f, (float16_t)0.148247679f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.989400428f, (float16_t)0.145212925f, + (float16_t)0.989622017f, (float16_t)0.143695033f, + (float16_t)0.989841278f, (float16_t)0.142176804f, + (float16_t)0.990058210f, (float16_t)0.140658239f, + (float16_t)0.990272812f, (float16_t)0.139139344f, + (float16_t)0.990485084f, (float16_t)0.137620122f, + (float16_t)0.990695025f, (float16_t)0.136100575f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.991107914f, (float16_t)0.133060525f, + (float16_t)0.991310860f, (float16_t)0.131540029f, + (float16_t)0.991511473f, (float16_t)0.130019223f, + (float16_t)0.991709754f, (float16_t)0.128498111f, + (float16_t)0.991905700f, (float16_t)0.126976696f, + (float16_t)0.992099313f, (float16_t)0.125454983f, + (float16_t)0.992290591f, (float16_t)0.123932975f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.992666142f, (float16_t)0.120888087f, + (float16_t)0.992850414f, (float16_t)0.119365215f, + (float16_t)0.993032350f, (float16_t)0.117842062f, + (float16_t)0.993211949f, (float16_t)0.116318631f, + (float16_t)0.993389211f, (float16_t)0.114794927f, + (float16_t)0.993564136f, (float16_t)0.113270952f, + (float16_t)0.993736722f, (float16_t)0.111746711f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.994074879f, (float16_t)0.108697444f, + (float16_t)0.994240449f, (float16_t)0.107172425f, + (float16_t)0.994403680f, (float16_t)0.105647154f, + (float16_t)0.994564571f, (float16_t)0.104121634f, + (float16_t)0.994723121f, (float16_t)0.102595869f, + (float16_t)0.994879331f, (float16_t)0.101069863f, + (float16_t)0.995033199f, (float16_t)0.099543619f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.995333912f, (float16_t)0.096490431f, + (float16_t)0.995480755f, (float16_t)0.094963495f, + (float16_t)0.995625256f, (float16_t)0.093436336f, + (float16_t)0.995767414f, (float16_t)0.091908956f, + (float16_t)0.995907229f, (float16_t)0.090381361f, + (float16_t)0.996044701f, (float16_t)0.088853553f, + (float16_t)0.996179829f, (float16_t)0.087325535f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.996443051f, (float16_t)0.084268888f, + (float16_t)0.996571146f, (float16_t)0.082740265f, + (float16_t)0.996696895f, (float16_t)0.081211447f, + (float16_t)0.996820299f, (float16_t)0.079682438f, + (float16_t)0.996941358f, (float16_t)0.078153242f, + (float16_t)0.997060070f, (float16_t)0.076623861f, + (float16_t)0.997176437f, (float16_t)0.075094301f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.997402130f, (float16_t)0.072034653f, + (float16_t)0.997511456f, (float16_t)0.070504573f, + (float16_t)0.997618435f, (float16_t)0.068974328f, + (float16_t)0.997723067f, (float16_t)0.067443920f, + (float16_t)0.997825350f, (float16_t)0.065913353f, + (float16_t)0.997925286f, (float16_t)0.064382631f, + (float16_t)0.998022874f, (float16_t)0.062851758f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.998211003f, (float16_t)0.059789571f, + (float16_t)0.998301545f, (float16_t)0.058258265f, + (float16_t)0.998389737f, (float16_t)0.056726821f, + (float16_t)0.998475581f, (float16_t)0.055195244f, + (float16_t)0.998559074f, (float16_t)0.053663538f, + (float16_t)0.998640218f, (float16_t)0.052131705f, + (float16_t)0.998719012f, (float16_t)0.050599749f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.998869550f, (float16_t)0.047535484f, + (float16_t)0.998941293f, (float16_t)0.046003182f, + (float16_t)0.999010686f, (float16_t)0.044470772f, + (float16_t)0.999077728f, (float16_t)0.042938257f, + (float16_t)0.999142419f, (float16_t)0.041405641f, + (float16_t)0.999204759f, (float16_t)0.039872928f, + (float16_t)0.999264747f, (float16_t)0.038340120f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.999377670f, (float16_t)0.035274239f, + (float16_t)0.999430605f, (float16_t)0.033741172f, + (float16_t)0.999481187f, (float16_t)0.032208025f, + (float16_t)0.999529418f, (float16_t)0.030674803f, + (float16_t)0.999575296f, (float16_t)0.029141509f, + (float16_t)0.999618822f, (float16_t)0.027608146f, + (float16_t)0.999659997f, (float16_t)0.026074718f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999735288f, (float16_t)0.023007681f, + (float16_t)0.999769405f, (float16_t)0.021474080f, + (float16_t)0.999801170f, (float16_t)0.019940429f, + (float16_t)0.999830582f, (float16_t)0.018406730f, + (float16_t)0.999857641f, (float16_t)0.016872988f, + (float16_t)0.999882347f, (float16_t)0.015339206f, + (float16_t)0.999904701f, (float16_t)0.013805389f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)0.999942350f, (float16_t)0.010737659f, + (float16_t)0.999957645f, (float16_t)0.009203755f, + (float16_t)0.999970586f, (float16_t)0.007669829f, + (float16_t)0.999981175f, (float16_t)0.006135885f, + (float16_t)0.999989411f, (float16_t)0.004601926f, + (float16_t)0.999995294f, (float16_t)0.003067957f, + (float16_t)0.999998823f, (float16_t)0.001533980f, + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999998823f, (float16_t)-0.001533980f, + (float16_t)0.999995294f, (float16_t)-0.003067957f, + (float16_t)0.999989411f, (float16_t)-0.004601926f, + (float16_t)0.999981175f, (float16_t)-0.006135885f, + (float16_t)0.999970586f, (float16_t)-0.007669829f, + (float16_t)0.999957645f, (float16_t)-0.009203755f, + (float16_t)0.999942350f, (float16_t)-0.010737659f, + (float16_t)0.999924702f, (float16_t)-0.012271538f, + (float16_t)0.999904701f, (float16_t)-0.013805389f, + (float16_t)0.999882347f, (float16_t)-0.015339206f, + (float16_t)0.999857641f, (float16_t)-0.016872988f, + (float16_t)0.999830582f, (float16_t)-0.018406730f, + (float16_t)0.999801170f, (float16_t)-0.019940429f, + (float16_t)0.999769405f, (float16_t)-0.021474080f, + (float16_t)0.999735288f, (float16_t)-0.023007681f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999659997f, (float16_t)-0.026074718f, + (float16_t)0.999618822f, (float16_t)-0.027608146f, + (float16_t)0.999575296f, (float16_t)-0.029141509f, + (float16_t)0.999529418f, (float16_t)-0.030674803f, + (float16_t)0.999481187f, (float16_t)-0.032208025f, + (float16_t)0.999430605f, (float16_t)-0.033741172f, + (float16_t)0.999377670f, (float16_t)-0.035274239f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.999264747f, (float16_t)-0.038340120f, + (float16_t)0.999204759f, (float16_t)-0.039872928f, + (float16_t)0.999142419f, (float16_t)-0.041405641f, + (float16_t)0.999077728f, (float16_t)-0.042938257f, + (float16_t)0.999010686f, (float16_t)-0.044470772f, + (float16_t)0.998941293f, (float16_t)-0.046003182f, + (float16_t)0.998869550f, (float16_t)-0.047535484f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.998719012f, (float16_t)-0.050599749f, + (float16_t)0.998640218f, (float16_t)-0.052131705f, + (float16_t)0.998559074f, (float16_t)-0.053663538f, + (float16_t)0.998475581f, (float16_t)-0.055195244f, + (float16_t)0.998389737f, (float16_t)-0.056726821f, + (float16_t)0.998301545f, (float16_t)-0.058258265f, + (float16_t)0.998211003f, (float16_t)-0.059789571f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.998022874f, (float16_t)-0.062851758f, + (float16_t)0.997925286f, (float16_t)-0.064382631f, + (float16_t)0.997825350f, (float16_t)-0.065913353f, + (float16_t)0.997723067f, (float16_t)-0.067443920f, + (float16_t)0.997618435f, (float16_t)-0.068974328f, + (float16_t)0.997511456f, (float16_t)-0.070504573f, + (float16_t)0.997402130f, (float16_t)-0.072034653f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.997176437f, (float16_t)-0.075094301f, + (float16_t)0.997060070f, (float16_t)-0.076623861f, + (float16_t)0.996941358f, (float16_t)-0.078153242f, + (float16_t)0.996820299f, (float16_t)-0.079682438f, + (float16_t)0.996696895f, (float16_t)-0.081211447f, + (float16_t)0.996571146f, (float16_t)-0.082740265f, + (float16_t)0.996443051f, (float16_t)-0.084268888f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.996179829f, (float16_t)-0.087325535f, + (float16_t)0.996044701f, (float16_t)-0.088853553f, + (float16_t)0.995907229f, (float16_t)-0.090381361f, + (float16_t)0.995767414f, (float16_t)-0.091908956f, + (float16_t)0.995625256f, (float16_t)-0.093436336f, + (float16_t)0.995480755f, (float16_t)-0.094963495f, + (float16_t)0.995333912f, (float16_t)-0.096490431f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.995033199f, (float16_t)-0.099543619f, + (float16_t)0.994879331f, (float16_t)-0.101069863f, + (float16_t)0.994723121f, (float16_t)-0.102595869f, + (float16_t)0.994564571f, (float16_t)-0.104121634f, + (float16_t)0.994403680f, (float16_t)-0.105647154f, + (float16_t)0.994240449f, (float16_t)-0.107172425f, + (float16_t)0.994074879f, (float16_t)-0.108697444f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.993736722f, (float16_t)-0.111746711f, + (float16_t)0.993564136f, (float16_t)-0.113270952f, + (float16_t)0.993389211f, (float16_t)-0.114794927f, + (float16_t)0.993211949f, (float16_t)-0.116318631f, + (float16_t)0.993032350f, (float16_t)-0.117842062f, + (float16_t)0.992850414f, (float16_t)-0.119365215f, + (float16_t)0.992666142f, (float16_t)-0.120888087f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.992290591f, (float16_t)-0.123932975f, + (float16_t)0.992099313f, (float16_t)-0.125454983f, + (float16_t)0.991905700f, (float16_t)-0.126976696f, + (float16_t)0.991709754f, (float16_t)-0.128498111f, + (float16_t)0.991511473f, (float16_t)-0.130019223f, + (float16_t)0.991310860f, (float16_t)-0.131540029f, + (float16_t)0.991107914f, (float16_t)-0.133060525f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.990695025f, (float16_t)-0.136100575f, + (float16_t)0.990485084f, (float16_t)-0.137620122f, + (float16_t)0.990272812f, (float16_t)-0.139139344f, + (float16_t)0.990058210f, (float16_t)-0.140658239f, + (float16_t)0.989841278f, (float16_t)-0.142176804f, + (float16_t)0.989622017f, (float16_t)-0.143695033f, + (float16_t)0.989400428f, (float16_t)-0.145212925f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.988950265f, (float16_t)-0.148247679f, + (float16_t)0.988721692f, (float16_t)-0.149764535f, + (float16_t)0.988490793f, (float16_t)-0.151281038f, + (float16_t)0.988257568f, (float16_t)-0.152797185f, + (float16_t)0.988022017f, (float16_t)-0.154312973f, + (float16_t)0.987784142f, (float16_t)-0.155828398f, + (float16_t)0.987543942f, (float16_t)-0.157343456f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.987056571f, (float16_t)-0.160372457f, + (float16_t)0.986809402f, (float16_t)-0.161886394f, + (float16_t)0.986559910f, (float16_t)-0.163399949f, + (float16_t)0.986308097f, (float16_t)-0.164913120f, + (float16_t)0.986053963f, (float16_t)-0.166425904f, + (float16_t)0.985797509f, (float16_t)-0.167938295f, + (float16_t)0.985538735f, (float16_t)-0.169450291f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.985014231f, (float16_t)-0.172473084f, + (float16_t)0.984748502f, (float16_t)-0.173983873f, + (float16_t)0.984480455f, (float16_t)-0.175494253f, + (float16_t)0.984210092f, (float16_t)-0.177004220f, + (float16_t)0.983937413f, (float16_t)-0.178513771f, + (float16_t)0.983662419f, (float16_t)-0.180022901f, + (float16_t)0.983385110f, (float16_t)-0.181531608f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.982823551f, (float16_t)-0.184547737f, + (float16_t)0.982539302f, (float16_t)-0.186055152f, + (float16_t)0.982252741f, (float16_t)-0.187562129f, + (float16_t)0.981963869f, (float16_t)-0.189068664f, + (float16_t)0.981672686f, (float16_t)-0.190574755f, + (float16_t)0.981379193f, (float16_t)-0.192080397f, + (float16_t)0.981083391f, (float16_t)-0.193585587f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.980484862f, (float16_t)-0.196594598f, + (float16_t)0.980182136f, (float16_t)-0.198098411f, + (float16_t)0.979877104f, (float16_t)-0.199601758f, + (float16_t)0.979569766f, (float16_t)-0.201104635f, + (float16_t)0.979260123f, (float16_t)-0.202607039f, + (float16_t)0.978948175f, (float16_t)-0.204108966f, + (float16_t)0.978633924f, (float16_t)-0.205610413f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.977998515f, (float16_t)-0.208611852f, + (float16_t)0.977677358f, (float16_t)-0.210111837f, + (float16_t)0.977353900f, (float16_t)-0.211611327f, + (float16_t)0.977028143f, (float16_t)-0.213110320f, + (float16_t)0.976700086f, (float16_t)-0.214608811f, + (float16_t)0.976369731f, (float16_t)-0.216106797f, + (float16_t)0.976037079f, (float16_t)-0.217604275f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.975364885f, (float16_t)-0.220597690f, + (float16_t)0.975025345f, (float16_t)-0.222093621f, + (float16_t)0.974683511f, (float16_t)-0.223589029f, + (float16_t)0.974339383f, (float16_t)-0.225083911f, + (float16_t)0.973992962f, (float16_t)-0.226578264f, + (float16_t)0.973644250f, (float16_t)-0.228072083f, + (float16_t)0.973293246f, (float16_t)-0.229565366f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.972584369f, (float16_t)-0.232550307f, + (float16_t)0.972226497f, (float16_t)-0.234041959f, + (float16_t)0.971866337f, (float16_t)-0.235533059f, + (float16_t)0.971503891f, (float16_t)-0.237023606f, + (float16_t)0.971139158f, (float16_t)-0.238513595f, + (float16_t)0.970772141f, (float16_t)-0.240003022f, + (float16_t)0.970402839f, (float16_t)-0.241491885f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.969657385f, (float16_t)-0.244467903f, + (float16_t)0.969281235f, (float16_t)-0.245955050f, + (float16_t)0.968902805f, (float16_t)-0.247441619f, + (float16_t)0.968522094f, (float16_t)-0.248927606f, + (float16_t)0.968139105f, (float16_t)-0.250413007f, + (float16_t)0.967753837f, (float16_t)-0.251897818f, + (float16_t)0.967366292f, (float16_t)-0.253382037f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.966584374f, (float16_t)-0.256348682f, + (float16_t)0.966190003f, (float16_t)-0.257831102f, + (float16_t)0.965793359f, (float16_t)-0.259312915f, + (float16_t)0.965394442f, (float16_t)-0.260794118f, + (float16_t)0.964993253f, (float16_t)-0.262274707f, + (float16_t)0.964589793f, (float16_t)-0.263754679f, + (float16_t)0.964184064f, (float16_t)-0.265234030f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.963365800f, (float16_t)-0.268190857f, + (float16_t)0.962953267f, (float16_t)-0.269668326f, + (float16_t)0.962538468f, (float16_t)-0.271145160f, + (float16_t)0.962121404f, (float16_t)-0.272621355f, + (float16_t)0.961702077f, (float16_t)-0.274096910f, + (float16_t)0.961280486f, (float16_t)-0.275571819f, + (float16_t)0.960856633f, (float16_t)-0.277046080f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.960002146f, (float16_t)-0.279992643f, + (float16_t)0.959571513f, (float16_t)-0.281464938f, + (float16_t)0.959138622f, (float16_t)-0.282936570f, + (float16_t)0.958703475f, (float16_t)-0.284407537f, + (float16_t)0.958266071f, (float16_t)-0.285877835f, + (float16_t)0.957826413f, (float16_t)-0.287347460f, + (float16_t)0.957384501f, (float16_t)-0.288816408f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.956493919f, (float16_t)-0.291752263f, + (float16_t)0.956045251f, (float16_t)-0.293219163f, + (float16_t)0.955594334f, (float16_t)-0.294685372f, + (float16_t)0.955141168f, (float16_t)-0.296150888f, + (float16_t)0.954685755f, (float16_t)-0.297615707f, + (float16_t)0.954228095f, (float16_t)-0.299079826f, + (float16_t)0.953768190f, (float16_t)-0.300543241f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.952841648f, (float16_t)-0.303467947f, + (float16_t)0.952375013f, (float16_t)-0.304929230f, + (float16_t)0.951906137f, (float16_t)-0.306389795f, + (float16_t)0.951435021f, (float16_t)-0.307849640f, + (float16_t)0.950961666f, (float16_t)-0.309308760f, + (float16_t)0.950486074f, (float16_t)-0.310767153f, + (float16_t)0.950008245f, (float16_t)-0.312224814f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.949045882f, (float16_t)-0.315137929f, + (float16_t)0.948561350f, (float16_t)-0.316593376f, + (float16_t)0.948074586f, (float16_t)-0.318048077f, + (float16_t)0.947585591f, (float16_t)-0.319502031f, + (float16_t)0.947094366f, (float16_t)-0.320955232f, + (float16_t)0.946600913f, (float16_t)-0.322407679f, + (float16_t)0.946105232f, (float16_t)-0.323859367f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.945107193f, (float16_t)-0.326760452f, + (float16_t)0.944604837f, (float16_t)-0.328209844f, + (float16_t)0.944100258f, (float16_t)-0.329658463f, + (float16_t)0.943593458f, (float16_t)-0.331106306f, + (float16_t)0.943084437f, (float16_t)-0.332553370f, + (float16_t)0.942573198f, (float16_t)-0.333999651f, + (float16_t)0.942059740f, (float16_t)-0.335445147f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.941026175f, (float16_t)-0.338333767f, + (float16_t)0.940506071f, (float16_t)-0.339776884f, + (float16_t)0.939983753f, (float16_t)-0.341219202f, + (float16_t)0.939459224f, (float16_t)-0.342660717f, + (float16_t)0.938932484f, (float16_t)-0.344101426f, + (float16_t)0.938403534f, (float16_t)-0.345541325f, + (float16_t)0.937872376f, (float16_t)-0.346980411f, + (float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.936803442f, (float16_t)-0.349856130f, + (float16_t)0.936265667f, (float16_t)-0.351292756f, + (float16_t)0.935725689f, (float16_t)-0.352728556f, + (float16_t)0.935183510f, (float16_t)-0.354163525f, + (float16_t)0.934639130f, (float16_t)-0.355597662f, + (float16_t)0.934092550f, (float16_t)-0.357030961f, + (float16_t)0.933543773f, (float16_t)-0.358463421f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.932439629f, (float16_t)-0.361325806f, + (float16_t)0.931884266f, (float16_t)-0.362755724f, + (float16_t)0.931326709f, (float16_t)-0.364184790f, + (float16_t)0.930766961f, (float16_t)-0.365612998f, + (float16_t)0.930205023f, (float16_t)-0.367040346f, + (float16_t)0.929640896f, (float16_t)-0.368466830f, + (float16_t)0.929074581f, (float16_t)-0.369892447f, + (float16_t)0.928506080f, (float16_t)-0.371317194f, + (float16_t)0.927935395f, (float16_t)-0.372741067f, + (float16_t)0.927362526f, (float16_t)-0.374164063f, + (float16_t)0.926787474f, (float16_t)-0.375586178f, + (float16_t)0.926210242f, (float16_t)-0.377007410f, + (float16_t)0.925630831f, (float16_t)-0.378427755f, + (float16_t)0.925049241f, (float16_t)-0.379847209f, + (float16_t)0.924465474f, (float16_t)-0.381265769f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.923291417f, (float16_t)-0.384100195f, + (float16_t)0.922701128f, (float16_t)-0.385516054f, + (float16_t)0.922108669f, (float16_t)-0.386931006f, + (float16_t)0.921514039f, (float16_t)-0.388345047f, + (float16_t)0.920917242f, (float16_t)-0.389758174f, + (float16_t)0.920318277f, (float16_t)-0.391170384f, + (float16_t)0.919717146f, (float16_t)-0.392581674f, + (float16_t)0.919113852f, (float16_t)-0.393992040f, + (float16_t)0.918508394f, (float16_t)-0.395401479f, + (float16_t)0.917900776f, (float16_t)-0.396809987f, + (float16_t)0.917290997f, (float16_t)-0.398217562f, + (float16_t)0.916679060f, (float16_t)-0.399624200f, + (float16_t)0.916064966f, (float16_t)-0.401029897f, + (float16_t)0.915448716f, (float16_t)-0.402434651f, + (float16_t)0.914830312f, (float16_t)-0.403838458f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.913587048f, (float16_t)-0.406643217f, + (float16_t)0.912962190f, (float16_t)-0.408044163f, + (float16_t)0.912335185f, (float16_t)-0.409444149f, + (float16_t)0.911706032f, (float16_t)-0.410843171f, + (float16_t)0.911074734f, (float16_t)-0.412241227f, + (float16_t)0.910441292f, (float16_t)-0.413638312f, + (float16_t)0.909805708f, (float16_t)-0.415034424f, + (float16_t)0.909167983f, (float16_t)-0.416429560f, + (float16_t)0.908528119f, (float16_t)-0.417823716f, + (float16_t)0.907886116f, (float16_t)-0.419216888f, + (float16_t)0.907241978f, (float16_t)-0.420609074f, + (float16_t)0.906595705f, (float16_t)-0.422000271f, + (float16_t)0.905947298f, (float16_t)-0.423390474f, + (float16_t)0.905296759f, (float16_t)-0.424779681f, + (float16_t)0.904644091f, (float16_t)-0.426167889f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.903332368f, (float16_t)-0.428941292f, + (float16_t)0.902673318f, (float16_t)-0.430326481f, + (float16_t)0.902012144f, (float16_t)-0.431710658f, + (float16_t)0.901348847f, (float16_t)-0.433093819f, + (float16_t)0.900683429f, (float16_t)-0.434475961f, + (float16_t)0.900015892f, (float16_t)-0.435857080f, + (float16_t)0.899346237f, (float16_t)-0.437237174f, + (float16_t)0.898674466f, (float16_t)-0.438616239f, + (float16_t)0.898000580f, (float16_t)-0.439994271f, + (float16_t)0.897324581f, (float16_t)-0.441371269f, + (float16_t)0.896646470f, (float16_t)-0.442747228f, + (float16_t)0.895966250f, (float16_t)-0.444122145f, + (float16_t)0.895283921f, (float16_t)-0.445496017f, + (float16_t)0.894599486f, (float16_t)-0.446868840f, + (float16_t)0.893912945f, (float16_t)-0.448240612f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.892533555f, (float16_t)-0.450980989f, + (float16_t)0.891840709f, (float16_t)-0.452349587f, + (float16_t)0.891145765f, (float16_t)-0.453717121f, + (float16_t)0.890448723f, (float16_t)-0.455083587f, + (float16_t)0.889749586f, (float16_t)-0.456448982f, + (float16_t)0.889048356f, (float16_t)-0.457813304f, + (float16_t)0.888345033f, (float16_t)-0.459176548f, + (float16_t)0.887639620f, (float16_t)-0.460538711f, + (float16_t)0.886932119f, (float16_t)-0.461899791f, + (float16_t)0.886222530f, (float16_t)-0.463259784f, + (float16_t)0.885510856f, (float16_t)-0.464618686f, + (float16_t)0.884797098f, (float16_t)-0.465976496f, + (float16_t)0.884081259f, (float16_t)-0.467333209f, + (float16_t)0.883363339f, (float16_t)-0.468688822f, + (float16_t)0.882643340f, (float16_t)-0.470043332f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.881197113f, (float16_t)-0.472749032f, + (float16_t)0.880470889f, (float16_t)-0.474100215f, + (float16_t)0.879742593f, (float16_t)-0.475450282f, + (float16_t)0.879012226f, (float16_t)-0.476799230f, + (float16_t)0.878279792f, (float16_t)-0.478147056f, + (float16_t)0.877545290f, (float16_t)-0.479493758f, + (float16_t)0.876808724f, (float16_t)-0.480839331f, + (float16_t)0.876070094f, (float16_t)-0.482183772f, + (float16_t)0.875329403f, (float16_t)-0.483527079f, + (float16_t)0.874586652f, (float16_t)-0.484869248f, + (float16_t)0.873841843f, (float16_t)-0.486210276f, + (float16_t)0.873094978f, (float16_t)-0.487550160f, + (float16_t)0.872346059f, (float16_t)-0.488888897f, + (float16_t)0.871595087f, (float16_t)-0.490226483f, + (float16_t)0.870842063f, (float16_t)-0.491562916f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.869329871f, (float16_t)-0.494232309f, + (float16_t)0.868570706f, (float16_t)-0.495565262f, + (float16_t)0.867809497f, (float16_t)-0.496897049f, + (float16_t)0.867046246f, (float16_t)-0.498227667f, + (float16_t)0.866280954f, (float16_t)-0.499557113f, + (float16_t)0.865513624f, (float16_t)-0.500885383f, + (float16_t)0.864744258f, (float16_t)-0.502212474f, + (float16_t)0.863972856f, (float16_t)-0.503538384f, + (float16_t)0.863199422f, (float16_t)-0.504863109f, + (float16_t)0.862423956f, (float16_t)-0.506186645f, + (float16_t)0.861646461f, (float16_t)-0.507508991f, + (float16_t)0.860866939f, (float16_t)-0.508830143f, + (float16_t)0.860085390f, (float16_t)-0.510150097f, + (float16_t)0.859301818f, (float16_t)-0.511468850f, + (float16_t)0.858516224f, (float16_t)-0.512786401f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.856938977f, (float16_t)-0.515417878f, + (float16_t)0.856147328f, (float16_t)-0.516731799f, + (float16_t)0.855353665f, (float16_t)-0.518044504f, + (float16_t)0.854557988f, (float16_t)-0.519355990f, + (float16_t)0.853760301f, (float16_t)-0.520666254f, + (float16_t)0.852960605f, (float16_t)-0.521975293f, + (float16_t)0.852158902f, (float16_t)-0.523283103f, + (float16_t)0.851355193f, (float16_t)-0.524589683f, + (float16_t)0.850549481f, (float16_t)-0.525895027f, + (float16_t)0.849741768f, (float16_t)-0.527199135f, + (float16_t)0.848932055f, (float16_t)-0.528502002f, + (float16_t)0.848120345f, (float16_t)-0.529803625f, + (float16_t)0.847306639f, (float16_t)-0.531104001f, + (float16_t)0.846490939f, (float16_t)-0.532403128f, + (float16_t)0.845673247f, (float16_t)-0.533701002f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.844031895f, (float16_t)-0.536292979f, + (float16_t)0.843208240f, (float16_t)-0.537587076f, + (float16_t)0.842382600f, (float16_t)-0.538879909f, + (float16_t)0.841554977f, (float16_t)-0.540171473f, + (float16_t)0.840725375f, (float16_t)-0.541461766f, + (float16_t)0.839893794f, (float16_t)-0.542750785f, + (float16_t)0.839060237f, (float16_t)-0.544038527f, + (float16_t)0.838224706f, (float16_t)-0.545324988f, + (float16_t)0.837387202f, (float16_t)-0.546610167f, + (float16_t)0.836547727f, (float16_t)-0.547894059f, + (float16_t)0.835706284f, (float16_t)-0.549176662f, + (float16_t)0.834862875f, (float16_t)-0.550457973f, + (float16_t)0.834017501f, (float16_t)-0.551737988f, + (float16_t)0.833170165f, (float16_t)-0.553016706f, + (float16_t)0.832320868f, (float16_t)-0.554294121f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.830616400f, (float16_t)-0.556845037f, + (float16_t)0.829761234f, (float16_t)-0.558118531f, + (float16_t)0.828904115f, (float16_t)-0.559390712f, + (float16_t)0.828045045f, (float16_t)-0.560661576f, + (float16_t)0.827184027f, (float16_t)-0.561931121f, + (float16_t)0.826321063f, (float16_t)-0.563199344f, + (float16_t)0.825456154f, (float16_t)-0.564466242f, + (float16_t)0.824589303f, (float16_t)-0.565731811f, + (float16_t)0.823720511f, (float16_t)-0.566996049f, + (float16_t)0.822849781f, (float16_t)-0.568258953f, + (float16_t)0.821977115f, (float16_t)-0.569520519f, + (float16_t)0.821102515f, (float16_t)-0.570780746f, + (float16_t)0.820225983f, (float16_t)-0.572039629f, + (float16_t)0.819347520f, (float16_t)-0.573297167f, + (float16_t)0.818467130f, (float16_t)-0.574553355f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.816700573f, (float16_t)-0.577061673f, + (float16_t)0.815814411f, (float16_t)-0.578313796f, + (float16_t)0.814926329f, (float16_t)-0.579564559f, + (float16_t)0.814036330f, (float16_t)-0.580813958f, + (float16_t)0.813144415f, (float16_t)-0.582061990f, + (float16_t)0.812250587f, (float16_t)-0.583308653f, + (float16_t)0.811354847f, (float16_t)-0.584553943f, + (float16_t)0.810457198f, (float16_t)-0.585797857f, + (float16_t)0.809557642f, (float16_t)-0.587040394f, + (float16_t)0.808656182f, (float16_t)-0.588281548f, + (float16_t)0.807752818f, (float16_t)-0.589521319f, + (float16_t)0.806847554f, (float16_t)-0.590759702f, + (float16_t)0.805940391f, (float16_t)-0.591996695f, + (float16_t)0.805031331f, (float16_t)-0.593232295f, + (float16_t)0.804120377f, (float16_t)-0.594466499f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.802292796f, (float16_t)-0.596930708f, + (float16_t)0.801376172f, (float16_t)-0.598160707f, + (float16_t)0.800457662f, (float16_t)-0.599389298f, + (float16_t)0.799537269f, (float16_t)-0.600616479f, + (float16_t)0.798614995f, (float16_t)-0.601842247f, + (float16_t)0.797690841f, (float16_t)-0.603066599f, + (float16_t)0.796764810f, (float16_t)-0.604289531f, + (float16_t)0.795836905f, (float16_t)-0.605511041f, + (float16_t)0.794907126f, (float16_t)-0.606731127f, + (float16_t)0.793975478f, (float16_t)-0.607949785f, + (float16_t)0.793041960f, (float16_t)-0.609167012f, + (float16_t)0.792106577f, (float16_t)-0.610382806f, + (float16_t)0.791169330f, (float16_t)-0.611597164f, + (float16_t)0.790230221f, (float16_t)-0.612810082f, + (float16_t)0.789289253f, (float16_t)-0.614021559f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.787401747f, (float16_t)-0.616440175f, + (float16_t)0.786455214f, (float16_t)-0.617647308f, + (float16_t)0.785506830f, (float16_t)-0.618852988f, + (float16_t)0.784556597f, (float16_t)-0.620057212f, + (float16_t)0.783604519f, (float16_t)-0.621259977f, + (float16_t)0.782650596f, (float16_t)-0.622461279f, + (float16_t)0.781694832f, (float16_t)-0.623661118f, + (float16_t)0.780737229f, (float16_t)-0.624859488f, + (float16_t)0.779777788f, (float16_t)-0.626056388f, + (float16_t)0.778816512f, (float16_t)-0.627251815f, + (float16_t)0.777853404f, (float16_t)-0.628445767f, + (float16_t)0.776888466f, (float16_t)-0.629638239f, + (float16_t)0.775921699f, (float16_t)-0.630829230f, + (float16_t)0.774953107f, (float16_t)-0.632018736f, + (float16_t)0.773982691f, (float16_t)-0.633206755f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.772036397f, (float16_t)-0.635578320f, + (float16_t)0.771060524f, (float16_t)-0.636761861f, + (float16_t)0.770082837f, (float16_t)-0.637943904f, + (float16_t)0.769103338f, (float16_t)-0.639124445f, + (float16_t)0.768122029f, (float16_t)-0.640303482f, + (float16_t)0.767138912f, (float16_t)-0.641481013f, + (float16_t)0.766153990f, (float16_t)-0.642657034f, + (float16_t)0.765167266f, (float16_t)-0.643831543f, + (float16_t)0.764178741f, (float16_t)-0.645004537f, + (float16_t)0.763188417f, (float16_t)-0.646176013f, + (float16_t)0.762196298f, (float16_t)-0.647345969f, + (float16_t)0.761202385f, (float16_t)-0.648514401f, + (float16_t)0.760206682f, (float16_t)-0.649681307f, + (float16_t)0.759209189f, (float16_t)-0.650846685f, + (float16_t)0.758209910f, (float16_t)-0.652010531f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.756206001f, (float16_t)-0.654333618f, + (float16_t)0.755201377f, (float16_t)-0.655492853f, + (float16_t)0.754194975f, (float16_t)-0.656650546f, + (float16_t)0.753186799f, (float16_t)-0.657806693f, + (float16_t)0.752176850f, (float16_t)-0.658961293f, + (float16_t)0.751165132f, (float16_t)-0.660114342f, + (float16_t)0.750151646f, (float16_t)-0.661265838f, + (float16_t)0.749136395f, (float16_t)-0.662415778f, + (float16_t)0.748119380f, (float16_t)-0.663564159f, + (float16_t)0.747100606f, (float16_t)-0.664710978f, + (float16_t)0.746080074f, (float16_t)-0.665856234f, + (float16_t)0.745057785f, (float16_t)-0.666999922f, + (float16_t)0.744033744f, (float16_t)-0.668142041f, + (float16_t)0.743007952f, (float16_t)-0.669282588f, + (float16_t)0.741980412f, (float16_t)-0.670421560f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.739920095f, (float16_t)-0.672694769f, + (float16_t)0.738887324f, (float16_t)-0.673829000f, + (float16_t)0.737852815f, (float16_t)-0.674961646f, + (float16_t)0.736816569f, (float16_t)-0.676092704f, + (float16_t)0.735778589f, (float16_t)-0.677222170f, + (float16_t)0.734738878f, (float16_t)-0.678350043f, + (float16_t)0.733697438f, (float16_t)-0.679476320f, + (float16_t)0.732654272f, (float16_t)-0.680600998f, + (float16_t)0.731609381f, (float16_t)-0.681724074f, + (float16_t)0.730562769f, (float16_t)-0.682845546f, + (float16_t)0.729514438f, (float16_t)-0.683965412f, + (float16_t)0.728464390f, (float16_t)-0.685083668f, + (float16_t)0.727412629f, (float16_t)-0.686200312f, + (float16_t)0.726359155f, (float16_t)-0.687315341f, + (float16_t)0.725303972f, (float16_t)-0.688428753f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.723188489f, (float16_t)-0.690650714f, + (float16_t)0.722128194f, (float16_t)-0.691759258f, + (float16_t)0.721066199f, (float16_t)-0.692866175f, + (float16_t)0.720002508f, (float16_t)-0.693971461f, + (float16_t)0.718937122f, (float16_t)-0.695075114f, + (float16_t)0.717870045f, (float16_t)-0.696177131f, + (float16_t)0.716801279f, (float16_t)-0.697277511f, + (float16_t)0.715730825f, (float16_t)-0.698376249f, + (float16_t)0.714658688f, (float16_t)-0.699473345f, + (float16_t)0.713584869f, (float16_t)-0.700568794f, + (float16_t)0.712509371f, (float16_t)-0.701662595f, + (float16_t)0.711432196f, (float16_t)-0.702754744f, + (float16_t)0.710353347f, (float16_t)-0.703845241f, + (float16_t)0.709272826f, (float16_t)-0.704934080f, + (float16_t)0.708190637f, (float16_t)-0.706021261f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.706021261f, (float16_t)-0.708190637f, + (float16_t)0.704934080f, (float16_t)-0.709272826f, + (float16_t)0.703845241f, (float16_t)-0.710353347f, + (float16_t)0.702754744f, (float16_t)-0.711432196f, + (float16_t)0.701662595f, (float16_t)-0.712509371f, + (float16_t)0.700568794f, (float16_t)-0.713584869f, + (float16_t)0.699473345f, (float16_t)-0.714658688f, + (float16_t)0.698376249f, (float16_t)-0.715730825f, + (float16_t)0.697277511f, (float16_t)-0.716801279f, + (float16_t)0.696177131f, (float16_t)-0.717870045f, + (float16_t)0.695075114f, (float16_t)-0.718937122f, + (float16_t)0.693971461f, (float16_t)-0.720002508f, + (float16_t)0.692866175f, (float16_t)-0.721066199f, + (float16_t)0.691759258f, (float16_t)-0.722128194f, + (float16_t)0.690650714f, (float16_t)-0.723188489f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.688428753f, (float16_t)-0.725303972f, + (float16_t)0.687315341f, (float16_t)-0.726359155f, + (float16_t)0.686200312f, (float16_t)-0.727412629f, + (float16_t)0.685083668f, (float16_t)-0.728464390f, + (float16_t)0.683965412f, (float16_t)-0.729514438f, + (float16_t)0.682845546f, (float16_t)-0.730562769f, + (float16_t)0.681724074f, (float16_t)-0.731609381f, + (float16_t)0.680600998f, (float16_t)-0.732654272f, + (float16_t)0.679476320f, (float16_t)-0.733697438f, + (float16_t)0.678350043f, (float16_t)-0.734738878f, + (float16_t)0.677222170f, (float16_t)-0.735778589f, + (float16_t)0.676092704f, (float16_t)-0.736816569f, + (float16_t)0.674961646f, (float16_t)-0.737852815f, + (float16_t)0.673829000f, (float16_t)-0.738887324f, + (float16_t)0.672694769f, (float16_t)-0.739920095f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.670421560f, (float16_t)-0.741980412f, + (float16_t)0.669282588f, (float16_t)-0.743007952f, + (float16_t)0.668142041f, (float16_t)-0.744033744f, + (float16_t)0.666999922f, (float16_t)-0.745057785f, + (float16_t)0.665856234f, (float16_t)-0.746080074f, + (float16_t)0.664710978f, (float16_t)-0.747100606f, + (float16_t)0.663564159f, (float16_t)-0.748119380f, + (float16_t)0.662415778f, (float16_t)-0.749136395f, + (float16_t)0.661265838f, (float16_t)-0.750151646f, + (float16_t)0.660114342f, (float16_t)-0.751165132f, + (float16_t)0.658961293f, (float16_t)-0.752176850f, + (float16_t)0.657806693f, (float16_t)-0.753186799f, + (float16_t)0.656650546f, (float16_t)-0.754194975f, + (float16_t)0.655492853f, (float16_t)-0.755201377f, + (float16_t)0.654333618f, (float16_t)-0.756206001f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.652010531f, (float16_t)-0.758209910f, + (float16_t)0.650846685f, (float16_t)-0.759209189f, + (float16_t)0.649681307f, (float16_t)-0.760206682f, + (float16_t)0.648514401f, (float16_t)-0.761202385f, + (float16_t)0.647345969f, (float16_t)-0.762196298f, + (float16_t)0.646176013f, (float16_t)-0.763188417f, + (float16_t)0.645004537f, (float16_t)-0.764178741f, + (float16_t)0.643831543f, (float16_t)-0.765167266f, + (float16_t)0.642657034f, (float16_t)-0.766153990f, + (float16_t)0.641481013f, (float16_t)-0.767138912f, + (float16_t)0.640303482f, (float16_t)-0.768122029f, + (float16_t)0.639124445f, (float16_t)-0.769103338f, + (float16_t)0.637943904f, (float16_t)-0.770082837f, + (float16_t)0.636761861f, (float16_t)-0.771060524f, + (float16_t)0.635578320f, (float16_t)-0.772036397f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.633206755f, (float16_t)-0.773982691f, + (float16_t)0.632018736f, (float16_t)-0.774953107f, + (float16_t)0.630829230f, (float16_t)-0.775921699f, + (float16_t)0.629638239f, (float16_t)-0.776888466f, + (float16_t)0.628445767f, (float16_t)-0.777853404f, + (float16_t)0.627251815f, (float16_t)-0.778816512f, + (float16_t)0.626056388f, (float16_t)-0.779777788f, + (float16_t)0.624859488f, (float16_t)-0.780737229f, + (float16_t)0.623661118f, (float16_t)-0.781694832f, + (float16_t)0.622461279f, (float16_t)-0.782650596f, + (float16_t)0.621259977f, (float16_t)-0.783604519f, + (float16_t)0.620057212f, (float16_t)-0.784556597f, + (float16_t)0.618852988f, (float16_t)-0.785506830f, + (float16_t)0.617647308f, (float16_t)-0.786455214f, + (float16_t)0.616440175f, (float16_t)-0.787401747f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.614021559f, (float16_t)-0.789289253f, + (float16_t)0.612810082f, (float16_t)-0.790230221f, + (float16_t)0.611597164f, (float16_t)-0.791169330f, + (float16_t)0.610382806f, (float16_t)-0.792106577f, + (float16_t)0.609167012f, (float16_t)-0.793041960f, + (float16_t)0.607949785f, (float16_t)-0.793975478f, + (float16_t)0.606731127f, (float16_t)-0.794907126f, + (float16_t)0.605511041f, (float16_t)-0.795836905f, + (float16_t)0.604289531f, (float16_t)-0.796764810f, + (float16_t)0.603066599f, (float16_t)-0.797690841f, + (float16_t)0.601842247f, (float16_t)-0.798614995f, + (float16_t)0.600616479f, (float16_t)-0.799537269f, + (float16_t)0.599389298f, (float16_t)-0.800457662f, + (float16_t)0.598160707f, (float16_t)-0.801376172f, + (float16_t)0.596930708f, (float16_t)-0.802292796f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.594466499f, (float16_t)-0.804120377f, + (float16_t)0.593232295f, (float16_t)-0.805031331f, + (float16_t)0.591996695f, (float16_t)-0.805940391f, + (float16_t)0.590759702f, (float16_t)-0.806847554f, + (float16_t)0.589521319f, (float16_t)-0.807752818f, + (float16_t)0.588281548f, (float16_t)-0.808656182f, + (float16_t)0.587040394f, (float16_t)-0.809557642f, + (float16_t)0.585797857f, (float16_t)-0.810457198f, + (float16_t)0.584553943f, (float16_t)-0.811354847f, + (float16_t)0.583308653f, (float16_t)-0.812250587f, + (float16_t)0.582061990f, (float16_t)-0.813144415f, + (float16_t)0.580813958f, (float16_t)-0.814036330f, + (float16_t)0.579564559f, (float16_t)-0.814926329f, + (float16_t)0.578313796f, (float16_t)-0.815814411f, + (float16_t)0.577061673f, (float16_t)-0.816700573f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.574553355f, (float16_t)-0.818467130f, + (float16_t)0.573297167f, (float16_t)-0.819347520f, + (float16_t)0.572039629f, (float16_t)-0.820225983f, + (float16_t)0.570780746f, (float16_t)-0.821102515f, + (float16_t)0.569520519f, (float16_t)-0.821977115f, + (float16_t)0.568258953f, (float16_t)-0.822849781f, + (float16_t)0.566996049f, (float16_t)-0.823720511f, + (float16_t)0.565731811f, (float16_t)-0.824589303f, + (float16_t)0.564466242f, (float16_t)-0.825456154f, + (float16_t)0.563199344f, (float16_t)-0.826321063f, + (float16_t)0.561931121f, (float16_t)-0.827184027f, + (float16_t)0.560661576f, (float16_t)-0.828045045f, + (float16_t)0.559390712f, (float16_t)-0.828904115f, + (float16_t)0.558118531f, (float16_t)-0.829761234f, + (float16_t)0.556845037f, (float16_t)-0.830616400f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.554294121f, (float16_t)-0.832320868f, + (float16_t)0.553016706f, (float16_t)-0.833170165f, + (float16_t)0.551737988f, (float16_t)-0.834017501f, + (float16_t)0.550457973f, (float16_t)-0.834862875f, + (float16_t)0.549176662f, (float16_t)-0.835706284f, + (float16_t)0.547894059f, (float16_t)-0.836547727f, + (float16_t)0.546610167f, (float16_t)-0.837387202f, + (float16_t)0.545324988f, (float16_t)-0.838224706f, + (float16_t)0.544038527f, (float16_t)-0.839060237f, + (float16_t)0.542750785f, (float16_t)-0.839893794f, + (float16_t)0.541461766f, (float16_t)-0.840725375f, + (float16_t)0.540171473f, (float16_t)-0.841554977f, + (float16_t)0.538879909f, (float16_t)-0.842382600f, + (float16_t)0.537587076f, (float16_t)-0.843208240f, + (float16_t)0.536292979f, (float16_t)-0.844031895f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.533701002f, (float16_t)-0.845673247f, + (float16_t)0.532403128f, (float16_t)-0.846490939f, + (float16_t)0.531104001f, (float16_t)-0.847306639f, + (float16_t)0.529803625f, (float16_t)-0.848120345f, + (float16_t)0.528502002f, (float16_t)-0.848932055f, + (float16_t)0.527199135f, (float16_t)-0.849741768f, + (float16_t)0.525895027f, (float16_t)-0.850549481f, + (float16_t)0.524589683f, (float16_t)-0.851355193f, + (float16_t)0.523283103f, (float16_t)-0.852158902f, + (float16_t)0.521975293f, (float16_t)-0.852960605f, + (float16_t)0.520666254f, (float16_t)-0.853760301f, + (float16_t)0.519355990f, (float16_t)-0.854557988f, + (float16_t)0.518044504f, (float16_t)-0.855353665f, + (float16_t)0.516731799f, (float16_t)-0.856147328f, + (float16_t)0.515417878f, (float16_t)-0.856938977f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.512786401f, (float16_t)-0.858516224f, + (float16_t)0.511468850f, (float16_t)-0.859301818f, + (float16_t)0.510150097f, (float16_t)-0.860085390f, + (float16_t)0.508830143f, (float16_t)-0.860866939f, + (float16_t)0.507508991f, (float16_t)-0.861646461f, + (float16_t)0.506186645f, (float16_t)-0.862423956f, + (float16_t)0.504863109f, (float16_t)-0.863199422f, + (float16_t)0.503538384f, (float16_t)-0.863972856f, + (float16_t)0.502212474f, (float16_t)-0.864744258f, + (float16_t)0.500885383f, (float16_t)-0.865513624f, + (float16_t)0.499557113f, (float16_t)-0.866280954f, + (float16_t)0.498227667f, (float16_t)-0.867046246f, + (float16_t)0.496897049f, (float16_t)-0.867809497f, + (float16_t)0.495565262f, (float16_t)-0.868570706f, + (float16_t)0.494232309f, (float16_t)-0.869329871f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.491562916f, (float16_t)-0.870842063f, + (float16_t)0.490226483f, (float16_t)-0.871595087f, + (float16_t)0.488888897f, (float16_t)-0.872346059f, + (float16_t)0.487550160f, (float16_t)-0.873094978f, + (float16_t)0.486210276f, (float16_t)-0.873841843f, + (float16_t)0.484869248f, (float16_t)-0.874586652f, + (float16_t)0.483527079f, (float16_t)-0.875329403f, + (float16_t)0.482183772f, (float16_t)-0.876070094f, + (float16_t)0.480839331f, (float16_t)-0.876808724f, + (float16_t)0.479493758f, (float16_t)-0.877545290f, + (float16_t)0.478147056f, (float16_t)-0.878279792f, + (float16_t)0.476799230f, (float16_t)-0.879012226f, + (float16_t)0.475450282f, (float16_t)-0.879742593f, + (float16_t)0.474100215f, (float16_t)-0.880470889f, + (float16_t)0.472749032f, (float16_t)-0.881197113f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.470043332f, (float16_t)-0.882643340f, + (float16_t)0.468688822f, (float16_t)-0.883363339f, + (float16_t)0.467333209f, (float16_t)-0.884081259f, + (float16_t)0.465976496f, (float16_t)-0.884797098f, + (float16_t)0.464618686f, (float16_t)-0.885510856f, + (float16_t)0.463259784f, (float16_t)-0.886222530f, + (float16_t)0.461899791f, (float16_t)-0.886932119f, + (float16_t)0.460538711f, (float16_t)-0.887639620f, + (float16_t)0.459176548f, (float16_t)-0.888345033f, + (float16_t)0.457813304f, (float16_t)-0.889048356f, + (float16_t)0.456448982f, (float16_t)-0.889749586f, + (float16_t)0.455083587f, (float16_t)-0.890448723f, + (float16_t)0.453717121f, (float16_t)-0.891145765f, + (float16_t)0.452349587f, (float16_t)-0.891840709f, + (float16_t)0.450980989f, (float16_t)-0.892533555f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.448240612f, (float16_t)-0.893912945f, + (float16_t)0.446868840f, (float16_t)-0.894599486f, + (float16_t)0.445496017f, (float16_t)-0.895283921f, + (float16_t)0.444122145f, (float16_t)-0.895966250f, + (float16_t)0.442747228f, (float16_t)-0.896646470f, + (float16_t)0.441371269f, (float16_t)-0.897324581f, + (float16_t)0.439994271f, (float16_t)-0.898000580f, + (float16_t)0.438616239f, (float16_t)-0.898674466f, + (float16_t)0.437237174f, (float16_t)-0.899346237f, + (float16_t)0.435857080f, (float16_t)-0.900015892f, + (float16_t)0.434475961f, (float16_t)-0.900683429f, + (float16_t)0.433093819f, (float16_t)-0.901348847f, + (float16_t)0.431710658f, (float16_t)-0.902012144f, + (float16_t)0.430326481f, (float16_t)-0.902673318f, + (float16_t)0.428941292f, (float16_t)-0.903332368f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.426167889f, (float16_t)-0.904644091f, + (float16_t)0.424779681f, (float16_t)-0.905296759f, + (float16_t)0.423390474f, (float16_t)-0.905947298f, + (float16_t)0.422000271f, (float16_t)-0.906595705f, + (float16_t)0.420609074f, (float16_t)-0.907241978f, + (float16_t)0.419216888f, (float16_t)-0.907886116f, + (float16_t)0.417823716f, (float16_t)-0.908528119f, + (float16_t)0.416429560f, (float16_t)-0.909167983f, + (float16_t)0.415034424f, (float16_t)-0.909805708f, + (float16_t)0.413638312f, (float16_t)-0.910441292f, + (float16_t)0.412241227f, (float16_t)-0.911074734f, + (float16_t)0.410843171f, (float16_t)-0.911706032f, + (float16_t)0.409444149f, (float16_t)-0.912335185f, + (float16_t)0.408044163f, (float16_t)-0.912962190f, + (float16_t)0.406643217f, (float16_t)-0.913587048f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.403838458f, (float16_t)-0.914830312f, + (float16_t)0.402434651f, (float16_t)-0.915448716f, + (float16_t)0.401029897f, (float16_t)-0.916064966f, + (float16_t)0.399624200f, (float16_t)-0.916679060f, + (float16_t)0.398217562f, (float16_t)-0.917290997f, + (float16_t)0.396809987f, (float16_t)-0.917900776f, + (float16_t)0.395401479f, (float16_t)-0.918508394f, + (float16_t)0.393992040f, (float16_t)-0.919113852f, + (float16_t)0.392581674f, (float16_t)-0.919717146f, + (float16_t)0.391170384f, (float16_t)-0.920318277f, + (float16_t)0.389758174f, (float16_t)-0.920917242f, + (float16_t)0.388345047f, (float16_t)-0.921514039f, + (float16_t)0.386931006f, (float16_t)-0.922108669f, + (float16_t)0.385516054f, (float16_t)-0.922701128f, + (float16_t)0.384100195f, (float16_t)-0.923291417f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.381265769f, (float16_t)-0.924465474f, + (float16_t)0.379847209f, (float16_t)-0.925049241f, + (float16_t)0.378427755f, (float16_t)-0.925630831f, + (float16_t)0.377007410f, (float16_t)-0.926210242f, + (float16_t)0.375586178f, (float16_t)-0.926787474f, + (float16_t)0.374164063f, (float16_t)-0.927362526f, + (float16_t)0.372741067f, (float16_t)-0.927935395f, + (float16_t)0.371317194f, (float16_t)-0.928506080f, + (float16_t)0.369892447f, (float16_t)-0.929074581f, + (float16_t)0.368466830f, (float16_t)-0.929640896f, + (float16_t)0.367040346f, (float16_t)-0.930205023f, + (float16_t)0.365612998f, (float16_t)-0.930766961f, + (float16_t)0.364184790f, (float16_t)-0.931326709f, + (float16_t)0.362755724f, (float16_t)-0.931884266f, + (float16_t)0.361325806f, (float16_t)-0.932439629f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.358463421f, (float16_t)-0.933543773f, + (float16_t)0.357030961f, (float16_t)-0.934092550f, + (float16_t)0.355597662f, (float16_t)-0.934639130f, + (float16_t)0.354163525f, (float16_t)-0.935183510f, + (float16_t)0.352728556f, (float16_t)-0.935725689f, + (float16_t)0.351292756f, (float16_t)-0.936265667f, + (float16_t)0.349856130f, (float16_t)-0.936803442f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.346980411f, (float16_t)-0.937872376f, + (float16_t)0.345541325f, (float16_t)-0.938403534f, + (float16_t)0.344101426f, (float16_t)-0.938932484f, + (float16_t)0.342660717f, (float16_t)-0.939459224f, + (float16_t)0.341219202f, (float16_t)-0.939983753f, + (float16_t)0.339776884f, (float16_t)-0.940506071f, + (float16_t)0.338333767f, (float16_t)-0.941026175f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.335445147f, (float16_t)-0.942059740f, + (float16_t)0.333999651f, (float16_t)-0.942573198f, + (float16_t)0.332553370f, (float16_t)-0.943084437f, + (float16_t)0.331106306f, (float16_t)-0.943593458f, + (float16_t)0.329658463f, (float16_t)-0.944100258f, + (float16_t)0.328209844f, (float16_t)-0.944604837f, + (float16_t)0.326760452f, (float16_t)-0.945107193f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.323859367f, (float16_t)-0.946105232f, + (float16_t)0.322407679f, (float16_t)-0.946600913f, + (float16_t)0.320955232f, (float16_t)-0.947094366f, + (float16_t)0.319502031f, (float16_t)-0.947585591f, + (float16_t)0.318048077f, (float16_t)-0.948074586f, + (float16_t)0.316593376f, (float16_t)-0.948561350f, + (float16_t)0.315137929f, (float16_t)-0.949045882f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.312224814f, (float16_t)-0.950008245f, + (float16_t)0.310767153f, (float16_t)-0.950486074f, + (float16_t)0.309308760f, (float16_t)-0.950961666f, + (float16_t)0.307849640f, (float16_t)-0.951435021f, + (float16_t)0.306389795f, (float16_t)-0.951906137f, + (float16_t)0.304929230f, (float16_t)-0.952375013f, + (float16_t)0.303467947f, (float16_t)-0.952841648f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.300543241f, (float16_t)-0.953768190f, + (float16_t)0.299079826f, (float16_t)-0.954228095f, + (float16_t)0.297615707f, (float16_t)-0.954685755f, + (float16_t)0.296150888f, (float16_t)-0.955141168f, + (float16_t)0.294685372f, (float16_t)-0.955594334f, + (float16_t)0.293219163f, (float16_t)-0.956045251f, + (float16_t)0.291752263f, (float16_t)-0.956493919f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.288816408f, (float16_t)-0.957384501f, + (float16_t)0.287347460f, (float16_t)-0.957826413f, + (float16_t)0.285877835f, (float16_t)-0.958266071f, + (float16_t)0.284407537f, (float16_t)-0.958703475f, + (float16_t)0.282936570f, (float16_t)-0.959138622f, + (float16_t)0.281464938f, (float16_t)-0.959571513f, + (float16_t)0.279992643f, (float16_t)-0.960002146f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.277046080f, (float16_t)-0.960856633f, + (float16_t)0.275571819f, (float16_t)-0.961280486f, + (float16_t)0.274096910f, (float16_t)-0.961702077f, + (float16_t)0.272621355f, (float16_t)-0.962121404f, + (float16_t)0.271145160f, (float16_t)-0.962538468f, + (float16_t)0.269668326f, (float16_t)-0.962953267f, + (float16_t)0.268190857f, (float16_t)-0.963365800f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.265234030f, (float16_t)-0.964184064f, + (float16_t)0.263754679f, (float16_t)-0.964589793f, + (float16_t)0.262274707f, (float16_t)-0.964993253f, + (float16_t)0.260794118f, (float16_t)-0.965394442f, + (float16_t)0.259312915f, (float16_t)-0.965793359f, + (float16_t)0.257831102f, (float16_t)-0.966190003f, + (float16_t)0.256348682f, (float16_t)-0.966584374f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.253382037f, (float16_t)-0.967366292f, + (float16_t)0.251897818f, (float16_t)-0.967753837f, + (float16_t)0.250413007f, (float16_t)-0.968139105f, + (float16_t)0.248927606f, (float16_t)-0.968522094f, + (float16_t)0.247441619f, (float16_t)-0.968902805f, + (float16_t)0.245955050f, (float16_t)-0.969281235f, + (float16_t)0.244467903f, (float16_t)-0.969657385f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.241491885f, (float16_t)-0.970402839f, + (float16_t)0.240003022f, (float16_t)-0.970772141f, + (float16_t)0.238513595f, (float16_t)-0.971139158f, + (float16_t)0.237023606f, (float16_t)-0.971503891f, + (float16_t)0.235533059f, (float16_t)-0.971866337f, + (float16_t)0.234041959f, (float16_t)-0.972226497f, + (float16_t)0.232550307f, (float16_t)-0.972584369f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.229565366f, (float16_t)-0.973293246f, + (float16_t)0.228072083f, (float16_t)-0.973644250f, + (float16_t)0.226578264f, (float16_t)-0.973992962f, + (float16_t)0.225083911f, (float16_t)-0.974339383f, + (float16_t)0.223589029f, (float16_t)-0.974683511f, + (float16_t)0.222093621f, (float16_t)-0.975025345f, + (float16_t)0.220597690f, (float16_t)-0.975364885f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.217604275f, (float16_t)-0.976037079f, + (float16_t)0.216106797f, (float16_t)-0.976369731f, + (float16_t)0.214608811f, (float16_t)-0.976700086f, + (float16_t)0.213110320f, (float16_t)-0.977028143f, + (float16_t)0.211611327f, (float16_t)-0.977353900f, + (float16_t)0.210111837f, (float16_t)-0.977677358f, + (float16_t)0.208611852f, (float16_t)-0.977998515f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.205610413f, (float16_t)-0.978633924f, + (float16_t)0.204108966f, (float16_t)-0.978948175f, + (float16_t)0.202607039f, (float16_t)-0.979260123f, + (float16_t)0.201104635f, (float16_t)-0.979569766f, + (float16_t)0.199601758f, (float16_t)-0.979877104f, + (float16_t)0.198098411f, (float16_t)-0.980182136f, + (float16_t)0.196594598f, (float16_t)-0.980484862f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.193585587f, (float16_t)-0.981083391f, + (float16_t)0.192080397f, (float16_t)-0.981379193f, + (float16_t)0.190574755f, (float16_t)-0.981672686f, + (float16_t)0.189068664f, (float16_t)-0.981963869f, + (float16_t)0.187562129f, (float16_t)-0.982252741f, + (float16_t)0.186055152f, (float16_t)-0.982539302f, + (float16_t)0.184547737f, (float16_t)-0.982823551f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.181531608f, (float16_t)-0.983385110f, + (float16_t)0.180022901f, (float16_t)-0.983662419f, + (float16_t)0.178513771f, (float16_t)-0.983937413f, + (float16_t)0.177004220f, (float16_t)-0.984210092f, + (float16_t)0.175494253f, (float16_t)-0.984480455f, + (float16_t)0.173983873f, (float16_t)-0.984748502f, + (float16_t)0.172473084f, (float16_t)-0.985014231f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.169450291f, (float16_t)-0.985538735f, + (float16_t)0.167938295f, (float16_t)-0.985797509f, + (float16_t)0.166425904f, (float16_t)-0.986053963f, + (float16_t)0.164913120f, (float16_t)-0.986308097f, + (float16_t)0.163399949f, (float16_t)-0.986559910f, + (float16_t)0.161886394f, (float16_t)-0.986809402f, + (float16_t)0.160372457f, (float16_t)-0.987056571f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.157343456f, (float16_t)-0.987543942f, + (float16_t)0.155828398f, (float16_t)-0.987784142f, + (float16_t)0.154312973f, (float16_t)-0.988022017f, + (float16_t)0.152797185f, (float16_t)-0.988257568f, + (float16_t)0.151281038f, (float16_t)-0.988490793f, + (float16_t)0.149764535f, (float16_t)-0.988721692f, + (float16_t)0.148247679f, (float16_t)-0.988950265f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.145212925f, (float16_t)-0.989400428f, + (float16_t)0.143695033f, (float16_t)-0.989622017f, + (float16_t)0.142176804f, (float16_t)-0.989841278f, + (float16_t)0.140658239f, (float16_t)-0.990058210f, + (float16_t)0.139139344f, (float16_t)-0.990272812f, + (float16_t)0.137620122f, (float16_t)-0.990485084f, + (float16_t)0.136100575f, (float16_t)-0.990695025f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.133060525f, (float16_t)-0.991107914f, + (float16_t)0.131540029f, (float16_t)-0.991310860f, + (float16_t)0.130019223f, (float16_t)-0.991511473f, + (float16_t)0.128498111f, (float16_t)-0.991709754f, + (float16_t)0.126976696f, (float16_t)-0.991905700f, + (float16_t)0.125454983f, (float16_t)-0.992099313f, + (float16_t)0.123932975f, (float16_t)-0.992290591f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.120888087f, (float16_t)-0.992666142f, + (float16_t)0.119365215f, (float16_t)-0.992850414f, + (float16_t)0.117842062f, (float16_t)-0.993032350f, + (float16_t)0.116318631f, (float16_t)-0.993211949f, + (float16_t)0.114794927f, (float16_t)-0.993389211f, + (float16_t)0.113270952f, (float16_t)-0.993564136f, + (float16_t)0.111746711f, (float16_t)-0.993736722f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.108697444f, (float16_t)-0.994074879f, + (float16_t)0.107172425f, (float16_t)-0.994240449f, + (float16_t)0.105647154f, (float16_t)-0.994403680f, + (float16_t)0.104121634f, (float16_t)-0.994564571f, + (float16_t)0.102595869f, (float16_t)-0.994723121f, + (float16_t)0.101069863f, (float16_t)-0.994879331f, + (float16_t)0.099543619f, (float16_t)-0.995033199f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.096490431f, (float16_t)-0.995333912f, + (float16_t)0.094963495f, (float16_t)-0.995480755f, + (float16_t)0.093436336f, (float16_t)-0.995625256f, + (float16_t)0.091908956f, (float16_t)-0.995767414f, + (float16_t)0.090381361f, (float16_t)-0.995907229f, + (float16_t)0.088853553f, (float16_t)-0.996044701f, + (float16_t)0.087325535f, (float16_t)-0.996179829f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.084268888f, (float16_t)-0.996443051f, + (float16_t)0.082740265f, (float16_t)-0.996571146f, + (float16_t)0.081211447f, (float16_t)-0.996696895f, + (float16_t)0.079682438f, (float16_t)-0.996820299f, + (float16_t)0.078153242f, (float16_t)-0.996941358f, + (float16_t)0.076623861f, (float16_t)-0.997060070f, + (float16_t)0.075094301f, (float16_t)-0.997176437f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.072034653f, (float16_t)-0.997402130f, + (float16_t)0.070504573f, (float16_t)-0.997511456f, + (float16_t)0.068974328f, (float16_t)-0.997618435f, + (float16_t)0.067443920f, (float16_t)-0.997723067f, + (float16_t)0.065913353f, (float16_t)-0.997825350f, + (float16_t)0.064382631f, (float16_t)-0.997925286f, + (float16_t)0.062851758f, (float16_t)-0.998022874f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.059789571f, (float16_t)-0.998211003f, + (float16_t)0.058258265f, (float16_t)-0.998301545f, + (float16_t)0.056726821f, (float16_t)-0.998389737f, + (float16_t)0.055195244f, (float16_t)-0.998475581f, + (float16_t)0.053663538f, (float16_t)-0.998559074f, + (float16_t)0.052131705f, (float16_t)-0.998640218f, + (float16_t)0.050599749f, (float16_t)-0.998719012f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.047535484f, (float16_t)-0.998869550f, + (float16_t)0.046003182f, (float16_t)-0.998941293f, + (float16_t)0.044470772f, (float16_t)-0.999010686f, + (float16_t)0.042938257f, (float16_t)-0.999077728f, + (float16_t)0.041405641f, (float16_t)-0.999142419f, + (float16_t)0.039872928f, (float16_t)-0.999204759f, + (float16_t)0.038340120f, (float16_t)-0.999264747f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.035274239f, (float16_t)-0.999377670f, + (float16_t)0.033741172f, (float16_t)-0.999430605f, + (float16_t)0.032208025f, (float16_t)-0.999481187f, + (float16_t)0.030674803f, (float16_t)-0.999529418f, + (float16_t)0.029141509f, (float16_t)-0.999575296f, + (float16_t)0.027608146f, (float16_t)-0.999618822f, + (float16_t)0.026074718f, (float16_t)-0.999659997f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.023007681f, (float16_t)-0.999735288f, + (float16_t)0.021474080f, (float16_t)-0.999769405f, + (float16_t)0.019940429f, (float16_t)-0.999801170f, + (float16_t)0.018406730f, (float16_t)-0.999830582f, + (float16_t)0.016872988f, (float16_t)-0.999857641f, + (float16_t)0.015339206f, (float16_t)-0.999882347f, + (float16_t)0.013805389f, (float16_t)-0.999904701f, + (float16_t)0.012271538f, (float16_t)-0.999924702f, + (float16_t)0.010737659f, (float16_t)-0.999942350f, + (float16_t)0.009203755f, (float16_t)-0.999957645f, + (float16_t)0.007669829f, (float16_t)-0.999970586f, + (float16_t)0.006135885f, (float16_t)-0.999981175f, + (float16_t)0.004601926f, (float16_t)-0.999989411f, + (float16_t)0.003067957f, (float16_t)-0.999995294f, + (float16_t)0.001533980f, (float16_t)-0.999998823f +}; + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALL_TABLES) */ + +#endif /*!defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)*/ + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) +const float16_t exp_tab_f16[8] = { + (1.f16), + (0.0416598916054f16), + (0.500000596046f16), + (0.00138889f16), + (1.00000011921f16), + (0.00833693705499f16), + (0.166665703058f16), + (0.000195780929062f16), +}; + +const float16_t __logf_lut_f16[8] = { + -2.295614848256274f16, /*p0*/ + -2.470711633419806f16, /*p4*/ + -5.686926051100417f16, /*p2*/ + -0.165253547131978f16, /*p6*/ + +5.175912446351073f16, /*p1*/ + +0.844006986174912f16, /*p5*/ + +4.584458825456749f16, /*p3*/ + +0.014127821926000f16 /*p7*/ +}; + +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif /* Not ARM AC5 */ + + +/** + @} end of CFFT_CIFFT group +*/ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.c new file mode 100644 index 00000000..aff3a130 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.c @@ -0,0 +1,654 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.c + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() or arm_rfft_f32() functions. + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math_types.h" +#include "arm_const_structs.h" + +/* +ALLOW TABLE is true when config table is enabled and the Tramsform folder is included +for compilation. +*/ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +/* Floating-point structs */ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_16) && defined(ARM_TABLE_BITREVIDX_FLT64_16)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len16 = { + 16, (const float64_t *)twiddleCoefF64_16, armBitRevIndexTableF64_16, ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_32) && defined(ARM_TABLE_BITREVIDX_FLT64_32)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len32 = { + 32, (const float64_t *)twiddleCoefF64_32, armBitRevIndexTableF64_32, ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_64) && defined(ARM_TABLE_BITREVIDX_FLT64_64)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len64 = { + 64, (const float64_t *)twiddleCoefF64_64, armBitRevIndexTableF64_64, ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_128) && defined(ARM_TABLE_BITREVIDX_FLT64_128)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len128 = { + 128, (const float64_t *)twiddleCoefF64_128, armBitRevIndexTableF64_128, ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_256) && defined(ARM_TABLE_BITREVIDX_FLT64_256)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len256 = { + 256, (const float64_t *)twiddleCoefF64_256, armBitRevIndexTableF64_256, ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_512) && defined(ARM_TABLE_BITREVIDX_FLT64_512)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len512 = { + 512, (const float64_t *)twiddleCoefF64_512, armBitRevIndexTableF64_512, ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_1024) && defined(ARM_TABLE_BITREVIDX_FLT64_1024)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len1024 = { + 1024, (const float64_t *)twiddleCoefF64_1024, armBitRevIndexTableF64_1024, ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_2048) && defined(ARM_TABLE_BITREVIDX_FLT64_2048)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len2048 = { + 2048, (const float64_t *)twiddleCoefF64_2048, armBitRevIndexTableF64_2048, ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_4096) && defined(ARM_TABLE_BITREVIDX_FLT64_4096)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len4096 = { + 4096, (const float64_t *)twiddleCoefF64_4096, armBitRevIndexTableF64_4096, ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH +}; +#endif + +/* Floating-point structs */ +#if !defined(ARM_MATH_MVEF) || defined(ARM_MATH_AUTOVECTORIZE) + + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_BITREVIDX_FLT_16)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = { + 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE_16_TABLE_LENGTH +}; +#endif + + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = { + 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE_32_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = { + 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE_64_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = { + 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = { + 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = { + 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = { + 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE_1024_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = { + 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE_2048_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = { + 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE_4096_TABLE_LENGTH +}; +#endif + +#endif /* !defined(ARM_MATH_MVEF) || defined(ARM_MATH_AUTOVECTORIZE) */ + +/* Fixed-point structs */ + +#if !defined(ARM_MATH_MVEI) || defined(ARM_MATH_AUTOVECTORIZE) + +/* + +Those structures cannot be used to initialize the MVE version of the FFT Q31 instances. +So they are not compiled when MVE is defined. + +For the MVE version, the new arm_cfft_init_f32 must be used. + + +*/ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len16 = { + 16, twiddleCoef_16_q31, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len32 = { + 32, twiddleCoef_32_q31, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len64 = { + 64, twiddleCoef_64_q31, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len128 = { + 128, twiddleCoef_128_q31, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len256 = { + 256, twiddleCoef_256_q31, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len512 = { + 512, twiddleCoef_512_q31, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024 = { + 1024, twiddleCoef_1024_q31, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048 = { + 2048, twiddleCoef_2048_q31, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096 = { + 4096, twiddleCoef_4096_q31, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH +}; +#endif + + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len16 = { + 16, twiddleCoef_16_q15, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len32 = { + 32, twiddleCoef_32_q15, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len64 = { + 64, twiddleCoef_64_q15, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len128 = { + 128, twiddleCoef_128_q15, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len256 = { + 256, twiddleCoef_256_q15, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len512 = { + 512, twiddleCoef_512_q15, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024 = { + 1024, twiddleCoef_1024_q15, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048 = { + 2048, twiddleCoef_2048_q15, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096 = { + 4096, twiddleCoef_4096_q15, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH +}; +#endif + +#endif /* !defined(ARM_MATH_MVEI) */ + +/* Structure for real-value inputs */ +/* Double precision strucs */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_32) && defined(ARM_TABLE_BITREVIDX_FLT64_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len32 = { + { 16, (const float64_t *)twiddleCoefF64_16, armBitRevIndexTableF64_16, ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH }, + 32U, + (float64_t *)twiddleCoefF64_rfft_32 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_64) && defined(ARM_TABLE_BITREVIDX_FLT64_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len64 = { + { 32, (const float64_t *)twiddleCoefF64_32, armBitRevIndexTableF64_32, ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH }, + 64U, + (float64_t *)twiddleCoefF64_rfft_64 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_128) && defined(ARM_TABLE_BITREVIDX_FLT64_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len128 = { + { 64, (const float64_t *)twiddleCoefF64_64, armBitRevIndexTableF64_64, ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH }, + 128U, + (float64_t *)twiddleCoefF64_rfft_128 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_256) && defined(ARM_TABLE_BITREVIDX_FLT64_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len256 = { + { 128, (const float64_t *)twiddleCoefF64_128, armBitRevIndexTableF64_128, ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH }, + 256U, + (float64_t *)twiddleCoefF64_rfft_256 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_512) && defined(ARM_TABLE_BITREVIDX_FLT64_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len512 = { + { 256, (const float64_t *)twiddleCoefF64_256, armBitRevIndexTableF64_256, ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH }, + 512U, + (float64_t *)twiddleCoefF64_rfft_512 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_1024) && defined(ARM_TABLE_BITREVIDX_FLT64_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len1024 = { + { 512, (const float64_t *)twiddleCoefF64_512, armBitRevIndexTableF64_512, ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH }, + 1024U, + (float64_t *)twiddleCoefF64_rfft_1024 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_2048) && defined(ARM_TABLE_BITREVIDX_FLT64_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len2048 = { + { 1024, (const float64_t *)twiddleCoefF64_1024, armBitRevIndexTableF64_1024, ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH }, + 2048U, + (float64_t *)twiddleCoefF64_rfft_2048 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_4096) && defined(ARM_TABLE_BITREVIDX_FLT64_4096) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len4096 = { + { 2048, (const float64_t *)twiddleCoefF64_2048, armBitRevIndexTableF64_2048, ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH }, + 4096U, + (float64_t *)twiddleCoefF64_rfft_4096 +}; +#endif + +/* Floating-point structs */ + +#if !defined(ARM_MATH_MVEF) || defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_BITREVIDX_FLT_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len32 = { + { 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE_16_TABLE_LENGTH }, + 32U, + (float32_t *)twiddleCoef_rfft_32 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len64 = { + { 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE_32_TABLE_LENGTH }, + 64U, + (float32_t *)twiddleCoef_rfft_64 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len128 = { + { 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE_64_TABLE_LENGTH }, + 128U, + (float32_t *)twiddleCoef_rfft_128 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len256 = { + { 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH }, + 256U, + (float32_t *)twiddleCoef_rfft_256 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len512 = { + { 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH }, + 512U, + (float32_t *)twiddleCoef_rfft_512 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len1024 = { + { 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH }, + 1024U, + (float32_t *)twiddleCoef_rfft_1024 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len2048 = { + { 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE_1024_TABLE_LENGTH }, + 2048U, + (float32_t *)twiddleCoef_rfft_2048 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len4096 = { + { 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE_2048_TABLE_LENGTH }, + 4096U, + (float32_t *)twiddleCoef_rfft_4096 +}; +#endif + +#endif /* #if !defined(ARM_MATH_MVEF) || defined(ARM_MATH_AUTOVECTORIZE) */ + +/* Fixed-point structs */ +/* q31_t */ + +#if !defined(ARM_MATH_MVEI) || defined(ARM_MATH_AUTOVECTORIZE) + +/* + +Those structures cannot be used to initialize the MVE version of the FFT Q31 instances. +So they are not compiled when MVE is defined. + +For the MVE version, the new arm_cfft_init_f32 must be used. + + +*/ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len32 = { + 32U, + 0, + 1, + 256U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len16 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len64 = { + 64U, + 0, + 1, + 128U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len32 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len128 = { + 128U, + 0, + 1, + 64U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len64 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len256 = { + 256U, + 0, + 1, + 32U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len128 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len512 = { + 512U, + 0, + 1, + 16U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len256 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len1024 = { + 1024U, + 0, + 1, + 8U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len512 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len2048 = { + 2048U, + 0, + 1, + 4U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len1024 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len4096 = { + 4096U, + 0, + 1, + 2U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len2048 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len8192 = { + 8192U, + 0, + 1, + 1U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len4096 +}; +#endif + + + +/* q15_t */ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len32 = { + 32U, + 0, + 1, + 256U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len16 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len64 = { + 64U, + 0, + 1, + 128U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len32 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len128 = { + 128U, + 0, + 1, + 64U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len64 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len256 = { + 256U, + 0, + 1, + 32U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len128 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len512 = { + 512U, + 0, + 1, + 16U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len256 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len1024 = { + 1024U, + 0, + 1, + 8U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len512 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len2048 = { + 2048U, + 0, + 1, + 4U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len1024 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len4096 = { + 4096U, + 0, + 1, + 2U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len2048 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len8192 = { + 8192U, + 0, + 1, + 1U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len4096 +}; +#endif + +#endif /* !defined(ARM_MATH_MVEI) */ + + +#endif diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs_f16.c new file mode 100644 index 00000000..c0a20e5b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs_f16.c @@ -0,0 +1,120 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs_f16.c + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() or arm_rfft_f32() functions. + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math_types_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include "arm_const_structs_f16.h" + + +/* +ALLOW TABLE is true when config table is enabled and the Tramsform folder is included +for compilation. +*/ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + + +/* Floating-point structs */ +#if !defined(ARM_MATH_MVE_FLOAT16) || defined(ARM_MATH_AUTOVECTORIZE) + + +/* + +Those structures cannot be used to initialize the MVE version of the FFT F32 instances. +So they are not compiled when MVE is defined. + +For the MVE version, the new arm_cfft_init_f16 must be used. + + +*/ + +#if !defined(__CC_ARM) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_16) && defined(ARM_TABLE_BITREVIDX_FLT_16)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len16 = { + 16, twiddleCoefF16_16, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_32) && defined(ARM_TABLE_BITREVIDX_FLT_32)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len32 = { + 32, twiddleCoefF16_32, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_64) && defined(ARM_TABLE_BITREVIDX_FLT_64)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len64 = { + 64, twiddleCoefF16_64, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_128) && defined(ARM_TABLE_BITREVIDX_FLT_128)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len128 = { + 128, twiddleCoefF16_128, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_256) && defined(ARM_TABLE_BITREVIDX_FLT_256)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len256 = { + 256, twiddleCoefF16_256, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_512) && defined(ARM_TABLE_BITREVIDX_FLT_512)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len512 = { + 512, twiddleCoefF16_512, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len1024 = { + 1024, twiddleCoefF16_1024, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len2048 = { + 2048, twiddleCoefF16_2048, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len4096 = { + 4096, twiddleCoefF16_4096, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH +}; +#endif +#endif + +#endif /* !defined(ARM_MATH_MVEF) || defined(ARM_MATH_AUTOVECTORIZE) */ + + +#endif + +#endif diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/arm_mve_tables.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/arm_mve_tables.c new file mode 100644 index 00000000..cae4bd8d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/arm_mve_tables.c @@ -0,0 +1,6533 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mve_tables.c + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * used for MVE implementation only + * + * @version V1.10.0 + * @date 04 October 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #include "arm_math_types.h" + + + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + +uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2]={ +0,0,}; + +float32_t rearranged_twiddle_stride1_16_f32[8]={ +1.00000000000000000000f,0.00000000000000000000f,0.92387950420379638672f, +0.38268342614173889160f,0.70710676908493041992f,0.70710676908493041992f, +0.38268342614173889160f,0.92387950420379638672f,}; + +float32_t rearranged_twiddle_stride2_16_f32[8]={ +1.00000000000000000000f,0.00000000000000000000f,0.70710676908493041992f, +0.70710676908493041992f,0.00000000000000006123f,1.00000000000000000000f, +-0.70710676908493041992f,0.70710676908493041992f,}; + +float32_t rearranged_twiddle_stride3_16_f32[8]={ +1.00000000000000000000f,0.00000000000000000000f,0.38268342614173889160f, +0.92387950420379638672f,-0.70710676908493041992f,0.70710676908493041992f, +-0.92387950420379638672f,-0.38268342614173889160f,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + +uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3]={ +0,32,0,}; + +float32_t rearranged_twiddle_stride1_64_f32[40]={ +1.00000000000000000000f,0.00000000000000000000f,0.99518471956253051758f, +0.09801714122295379639f,0.98078525066375732422f,0.19509032368659973145f, +0.95694035291671752930f,0.29028466343879699707f,0.92387950420379638672f, +0.38268342614173889160f,0.88192129135131835938f,0.47139674425125122070f, +0.83146959543228149414f,0.55557024478912353516f,0.77301043272018432617f, +0.63439327478408813477f,0.70710676908493041992f,0.70710676908493041992f, +0.63439327478408813477f,0.77301043272018432617f,0.55557024478912353516f, +0.83146959543228149414f,0.47139674425125122070f,0.88192129135131835938f, +0.38268342614173889160f,0.92387950420379638672f,0.29028466343879699707f, +0.95694035291671752930f,0.19509032368659973145f,0.98078525066375732422f, +0.09801714122295379639f,0.99518471956253051758f,1.00000000000000000000f, +0.00000000000000000000f,0.92387950420379638672f,0.38268342614173889160f, +0.70710676908493041992f,0.70710676908493041992f,0.38268342614173889160f, +0.92387950420379638672f,}; + +float32_t rearranged_twiddle_stride2_64_f32[40]={ +1.00000000000000000000f,0.00000000000000000000f,0.98078525066375732422f, +0.19509032368659973145f,0.92387950420379638672f,0.38268342614173889160f, +0.83146959543228149414f,0.55557024478912353516f,0.70710676908493041992f, +0.70710676908493041992f,0.55557024478912353516f,0.83146959543228149414f, +0.38268342614173889160f,0.92387950420379638672f,0.19509032368659973145f, +0.98078525066375732422f,0.00000000000000006123f,1.00000000000000000000f, +-0.19509032368659973145f,0.98078525066375732422f,-0.38268342614173889160f, +0.92387950420379638672f,-0.55557024478912353516f,0.83146959543228149414f, +-0.70710676908493041992f,0.70710676908493041992f,-0.83146959543228149414f, +0.55557024478912353516f,-0.92387950420379638672f,0.38268342614173889160f, +-0.98078525066375732422f,0.19509032368659973145f,1.00000000000000000000f, +0.00000000000000000000f,0.70710676908493041992f,0.70710676908493041992f, +0.00000000000000006123f,1.00000000000000000000f,-0.70710676908493041992f, +0.70710676908493041992f,}; + +float32_t rearranged_twiddle_stride3_64_f32[40]={ +1.00000000000000000000f,0.00000000000000000000f,0.95694035291671752930f, +0.29028466343879699707f,0.83146959543228149414f,0.55557024478912353516f, +0.63439327478408813477f,0.77301043272018432617f,0.38268342614173889160f, +0.92387950420379638672f,0.09801714122295379639f,0.99518471956253051758f, +-0.19509032368659973145f,0.98078525066375732422f,-0.47139674425125122070f, +0.88192129135131835938f,-0.70710676908493041992f,0.70710676908493041992f, +-0.88192129135131835938f,0.47139674425125122070f,-0.98078525066375732422f, +0.19509032368659973145f,-0.99518471956253051758f,-0.09801714122295379639f, +-0.92387950420379638672f,-0.38268342614173889160f,-0.77301043272018432617f, +-0.63439327478408813477f,-0.55557024478912353516f,-0.83146959543228149414f, +-0.29028466343879699707f,-0.95694035291671752930f,1.00000000000000000000f, +0.00000000000000000000f,0.38268342614173889160f,0.92387950420379638672f, +-0.70710676908493041992f,0.70710676908493041992f,-0.92387950420379638672f, +-0.38268342614173889160f,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + +uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4]={ +0,128,160,0,}; + +float32_t rearranged_twiddle_stride1_256_f32[168]={ +1.00000000000000000000f,0.00000000000000000000f,0.99969881772994995117f, +0.02454122900962829590f,0.99879544973373413086f,0.04906767606735229492f, +0.99729043245315551758f,0.07356456667184829712f,0.99518471956253051758f, +0.09801714122295379639f,0.99247956275939941406f,0.12241067737340927124f, +0.98917651176452636719f,0.14673046767711639404f,0.98527765274047851562f, +0.17096188664436340332f,0.98078525066375732422f,0.19509032368659973145f, +0.97570210695266723633f,0.21910123527050018311f,0.97003126144409179688f, +0.24298018217086791992f,0.96377605199813842773f,0.26671275496482849121f, +0.95694035291671752930f,0.29028466343879699707f,0.94952815771102905273f, +0.31368175148963928223f,0.94154405593872070312f,0.33688986301422119141f, +0.93299281597137451172f,0.35989505052566528320f,0.92387950420379638672f, +0.38268342614173889160f,0.91420978307723999023f,0.40524131059646606445f, +0.90398931503295898438f,0.42755508422851562500f,0.89322429895401000977f, +0.44961133599281311035f,0.88192129135131835938f,0.47139674425125122070f, +0.87008696794509887695f,0.49289819598197937012f,0.85772860050201416016f, +0.51410275697708129883f,0.84485357999801635742f,0.53499764204025268555f, +0.83146959543228149414f,0.55557024478912353516f,0.81758481264114379883f, +0.57580816745758056641f,0.80320751667022705078f,0.59569931030273437500f, +0.78834640979766845703f,0.61523157358169555664f,0.77301043272018432617f, +0.63439327478408813477f,0.75720882415771484375f,0.65317285060882568359f, +0.74095112085342407227f,0.67155897617340087891f,0.72424709796905517578f, +0.68954056501388549805f,0.70710676908493041992f,0.70710676908493041992f, +0.68954056501388549805f,0.72424709796905517578f,0.67155897617340087891f, +0.74095112085342407227f,0.65317285060882568359f,0.75720882415771484375f, +0.63439327478408813477f,0.77301043272018432617f,0.61523157358169555664f, +0.78834640979766845703f,0.59569931030273437500f,0.80320751667022705078f, +0.57580816745758056641f,0.81758481264114379883f,0.55557024478912353516f, +0.83146959543228149414f,0.53499764204025268555f,0.84485357999801635742f, +0.51410275697708129883f,0.85772860050201416016f,0.49289819598197937012f, +0.87008696794509887695f,0.47139674425125122070f,0.88192129135131835938f, +0.44961133599281311035f,0.89322429895401000977f,0.42755508422851562500f, +0.90398931503295898438f,0.40524131059646606445f,0.91420978307723999023f, +0.38268342614173889160f,0.92387950420379638672f,0.35989505052566528320f, +0.93299281597137451172f,0.33688986301422119141f,0.94154405593872070312f, +0.31368175148963928223f,0.94952815771102905273f,0.29028466343879699707f, +0.95694035291671752930f,0.26671275496482849121f,0.96377605199813842773f, +0.24298018217086791992f,0.97003126144409179688f,0.21910123527050018311f, +0.97570210695266723633f,0.19509032368659973145f,0.98078525066375732422f, +0.17096188664436340332f,0.98527765274047851562f,0.14673046767711639404f, +0.98917651176452636719f,0.12241067737340927124f,0.99247956275939941406f, +0.09801714122295379639f,0.99518471956253051758f,0.07356456667184829712f, +0.99729043245315551758f,0.04906767606735229492f,0.99879544973373413086f, +0.02454122900962829590f,0.99969881772994995117f,1.00000000000000000000f, +0.00000000000000000000f,0.99518471956253051758f,0.09801714122295379639f, +0.98078525066375732422f,0.19509032368659973145f,0.95694035291671752930f, +0.29028466343879699707f,0.92387950420379638672f,0.38268342614173889160f, +0.88192129135131835938f,0.47139674425125122070f,0.83146959543228149414f, +0.55557024478912353516f,0.77301043272018432617f,0.63439327478408813477f, +0.70710676908493041992f,0.70710676908493041992f,0.63439327478408813477f, +0.77301043272018432617f,0.55557024478912353516f,0.83146959543228149414f, +0.47139674425125122070f,0.88192129135131835938f,0.38268342614173889160f, +0.92387950420379638672f,0.29028466343879699707f,0.95694035291671752930f, +0.19509032368659973145f,0.98078525066375732422f,0.09801714122295379639f, +0.99518471956253051758f,1.00000000000000000000f,0.00000000000000000000f, +0.92387950420379638672f,0.38268342614173889160f,0.70710676908493041992f, +0.70710676908493041992f,0.38268342614173889160f,0.92387950420379638672f,}; + +float32_t rearranged_twiddle_stride2_256_f32[168]={ +1.00000000000000000000f,0.00000000000000000000f,0.99879544973373413086f, +0.04906767606735229492f,0.99518471956253051758f,0.09801714122295379639f, +0.98917651176452636719f,0.14673046767711639404f,0.98078525066375732422f, +0.19509032368659973145f,0.97003126144409179688f,0.24298018217086791992f, +0.95694035291671752930f,0.29028466343879699707f,0.94154405593872070312f, +0.33688986301422119141f,0.92387950420379638672f,0.38268342614173889160f, +0.90398931503295898438f,0.42755508422851562500f,0.88192129135131835938f, +0.47139674425125122070f,0.85772860050201416016f,0.51410275697708129883f, +0.83146959543228149414f,0.55557024478912353516f,0.80320751667022705078f, +0.59569931030273437500f,0.77301043272018432617f,0.63439327478408813477f, +0.74095112085342407227f,0.67155897617340087891f,0.70710676908493041992f, +0.70710676908493041992f,0.67155897617340087891f,0.74095112085342407227f, +0.63439327478408813477f,0.77301043272018432617f,0.59569931030273437500f, +0.80320751667022705078f,0.55557024478912353516f,0.83146959543228149414f, +0.51410275697708129883f,0.85772860050201416016f,0.47139674425125122070f, +0.88192129135131835938f,0.42755508422851562500f,0.90398931503295898438f, +0.38268342614173889160f,0.92387950420379638672f,0.33688986301422119141f, +0.94154405593872070312f,0.29028466343879699707f,0.95694035291671752930f, +0.24298018217086791992f,0.97003126144409179688f,0.19509032368659973145f, +0.98078525066375732422f,0.14673046767711639404f,0.98917651176452636719f, +0.09801714122295379639f,0.99518471956253051758f,0.04906767606735229492f, +0.99879544973373413086f,0.00000000000000006123f,1.00000000000000000000f, +-0.04906767606735229492f,0.99879544973373413086f,-0.09801714122295379639f, +0.99518471956253051758f,-0.14673046767711639404f,0.98917651176452636719f, +-0.19509032368659973145f,0.98078525066375732422f,-0.24298018217086791992f, +0.97003126144409179688f,-0.29028466343879699707f,0.95694035291671752930f, +-0.33688986301422119141f,0.94154405593872070312f,-0.38268342614173889160f, +0.92387950420379638672f,-0.42755508422851562500f,0.90398931503295898438f, +-0.47139674425125122070f,0.88192129135131835938f,-0.51410275697708129883f, +0.85772860050201416016f,-0.55557024478912353516f,0.83146959543228149414f, +-0.59569931030273437500f,0.80320751667022705078f,-0.63439327478408813477f, +0.77301043272018432617f,-0.67155897617340087891f,0.74095112085342407227f, +-0.70710676908493041992f,0.70710676908493041992f,-0.74095112085342407227f, +0.67155897617340087891f,-0.77301043272018432617f,0.63439327478408813477f, +-0.80320751667022705078f,0.59569931030273437500f,-0.83146959543228149414f, +0.55557024478912353516f,-0.85772860050201416016f,0.51410275697708129883f, +-0.88192129135131835938f,0.47139674425125122070f,-0.90398931503295898438f, +0.42755508422851562500f,-0.92387950420379638672f,0.38268342614173889160f, +-0.94154405593872070312f,0.33688986301422119141f,-0.95694035291671752930f, +0.29028466343879699707f,-0.97003126144409179688f,0.24298018217086791992f, +-0.98078525066375732422f,0.19509032368659973145f,-0.98917651176452636719f, +0.14673046767711639404f,-0.99518471956253051758f,0.09801714122295379639f, +-0.99879544973373413086f,0.04906767606735229492f,1.00000000000000000000f, +0.00000000000000000000f,0.98078525066375732422f,0.19509032368659973145f, +0.92387950420379638672f,0.38268342614173889160f,0.83146959543228149414f, +0.55557024478912353516f,0.70710676908493041992f,0.70710676908493041992f, +0.55557024478912353516f,0.83146959543228149414f,0.38268342614173889160f, +0.92387950420379638672f,0.19509032368659973145f,0.98078525066375732422f, +0.00000000000000006123f,1.00000000000000000000f,-0.19509032368659973145f, +0.98078525066375732422f,-0.38268342614173889160f,0.92387950420379638672f, +-0.55557024478912353516f,0.83146959543228149414f,-0.70710676908493041992f, +0.70710676908493041992f,-0.83146959543228149414f,0.55557024478912353516f, +-0.92387950420379638672f,0.38268342614173889160f,-0.98078525066375732422f, +0.19509032368659973145f,1.00000000000000000000f,0.00000000000000000000f, +0.70710676908493041992f,0.70710676908493041992f,0.00000000000000006123f, +1.00000000000000000000f,-0.70710676908493041992f,0.70710676908493041992f,}; + +float32_t rearranged_twiddle_stride3_256_f32[168]={ +1.00000000000000000000f,0.00000000000000000000f,0.99729043245315551758f, +0.07356456667184829712f,0.98917651176452636719f,0.14673046767711639404f, +0.97570210695266723633f,0.21910123527050018311f,0.95694035291671752930f, +0.29028466343879699707f,0.93299281597137451172f,0.35989505052566528320f, +0.90398931503295898438f,0.42755508422851562500f,0.87008696794509887695f, +0.49289819598197937012f,0.83146959543228149414f,0.55557024478912353516f, +0.78834640979766845703f,0.61523157358169555664f,0.74095112085342407227f, +0.67155897617340087891f,0.68954056501388549805f,0.72424709796905517578f, +0.63439327478408813477f,0.77301043272018432617f,0.57580816745758056641f, +0.81758481264114379883f,0.51410275697708129883f,0.85772860050201416016f, +0.44961133599281311035f,0.89322429895401000977f,0.38268342614173889160f, +0.92387950420379638672f,0.31368175148963928223f,0.94952815771102905273f, +0.24298018217086791992f,0.97003126144409179688f,0.17096188664436340332f, +0.98527765274047851562f,0.09801714122295379639f,0.99518471956253051758f, +0.02454122900962829590f,0.99969881772994995117f,-0.04906767606735229492f, +0.99879544973373413086f,-0.12241067737340927124f,0.99247956275939941406f, +-0.19509032368659973145f,0.98078525066375732422f,-0.26671275496482849121f, +0.96377605199813842773f,-0.33688986301422119141f,0.94154405593872070312f, +-0.40524131059646606445f,0.91420978307723999023f,-0.47139674425125122070f, +0.88192129135131835938f,-0.53499764204025268555f,0.84485357999801635742f, +-0.59569931030273437500f,0.80320751667022705078f,-0.65317285060882568359f, +0.75720882415771484375f,-0.70710676908493041992f,0.70710676908493041992f, +-0.75720882415771484375f,0.65317285060882568359f,-0.80320751667022705078f, +0.59569931030273437500f,-0.84485357999801635742f,0.53499764204025268555f, +-0.88192129135131835938f,0.47139674425125122070f,-0.91420978307723999023f, +0.40524131059646606445f,-0.94154405593872070312f,0.33688986301422119141f, +-0.96377605199813842773f,0.26671275496482849121f,-0.98078525066375732422f, +0.19509032368659973145f,-0.99247956275939941406f,0.12241067737340927124f, +-0.99879544973373413086f,0.04906767606735229492f,-0.99969881772994995117f, +-0.02454122900962829590f,-0.99518471956253051758f,-0.09801714122295379639f, +-0.98527765274047851562f,-0.17096188664436340332f,-0.97003126144409179688f, +-0.24298018217086791992f,-0.94952815771102905273f,-0.31368175148963928223f, +-0.92387950420379638672f,-0.38268342614173889160f,-0.89322429895401000977f, +-0.44961133599281311035f,-0.85772860050201416016f,-0.51410275697708129883f, +-0.81758481264114379883f,-0.57580816745758056641f,-0.77301043272018432617f, +-0.63439327478408813477f,-0.72424709796905517578f,-0.68954056501388549805f, +-0.67155897617340087891f,-0.74095112085342407227f,-0.61523157358169555664f, +-0.78834640979766845703f,-0.55557024478912353516f,-0.83146959543228149414f, +-0.49289819598197937012f,-0.87008696794509887695f,-0.42755508422851562500f, +-0.90398931503295898438f,-0.35989505052566528320f,-0.93299281597137451172f, +-0.29028466343879699707f,-0.95694035291671752930f,-0.21910123527050018311f, +-0.97570210695266723633f,-0.14673046767711639404f,-0.98917651176452636719f, +-0.07356456667184829712f,-0.99729043245315551758f,1.00000000000000000000f, +0.00000000000000000000f,0.95694035291671752930f,0.29028466343879699707f, +0.83146959543228149414f,0.55557024478912353516f,0.63439327478408813477f, +0.77301043272018432617f,0.38268342614173889160f,0.92387950420379638672f, +0.09801714122295379639f,0.99518471956253051758f,-0.19509032368659973145f, +0.98078525066375732422f,-0.47139674425125122070f,0.88192129135131835938f, +-0.70710676908493041992f,0.70710676908493041992f,-0.88192129135131835938f, +0.47139674425125122070f,-0.98078525066375732422f,0.19509032368659973145f, +-0.99518471956253051758f,-0.09801714122295379639f,-0.92387950420379638672f, +-0.38268342614173889160f,-0.77301043272018432617f,-0.63439327478408813477f, +-0.55557024478912353516f,-0.83146959543228149414f,-0.29028466343879699707f, +-0.95694035291671752930f,1.00000000000000000000f,0.00000000000000000000f, +0.38268342614173889160f,0.92387950420379638672f,-0.70710676908493041992f, +0.70710676908493041992f,-0.92387950420379638672f,-0.38268342614173889160f,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + +uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5]={ +0,512,640,672,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5]={ +0,512,640,672,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5]={ +0,512,640,672,0,}; + +float32_t rearranged_twiddle_stride1_1024_f32[680]={ +1.00000000000000000000f,0.00000000000000000000f,0.99998116493225097656f, +0.00613588467240333557f,0.99992471933364868164f,0.01227153837680816650f, +0.99983060359954833984f,0.01840673014521598816f,0.99969881772994995117f, +0.02454122900962829590f,0.99952942132949829102f,0.03067480400204658508f, +0.99932235479354858398f,0.03680722415447235107f,0.99907773733139038086f, +0.04293825849890708923f,0.99879544973373413086f,0.04906767606735229492f, +0.99847555160522460938f,0.05519524589180946350f,0.99811810255050659180f, +0.06132073700428009033f,0.99772304296493530273f,0.06744392216205596924f, +0.99729043245315551758f,0.07356456667184829712f,0.99682027101516723633f, +0.07968243956565856934f,0.99631261825561523438f,0.08579730987548828125f, +0.99576741456985473633f,0.09190895408391952515f,0.99518471956253051758f, +0.09801714122295379639f,0.99456459283828735352f,0.10412163287401199341f, +0.99390697479248046875f,0.11022220551967620850f,0.99321192502975463867f, +0.11631862819194793701f,0.99247956275939941406f,0.12241067737340927124f, +0.99170976877212524414f,0.12849810719490051270f,0.99090266227722167969f, +0.13458070158958435059f,0.99005818367004394531f,0.14065824449062347412f, +0.98917651176452636719f,0.14673046767711639404f,0.98825758695602416992f, +0.15279719233512878418f,0.98730140924453735352f,0.15885815024375915527f, +0.98630809783935546875f,0.16491311788558959961f,0.98527765274047851562f, +0.17096188664436340332f,0.98421007394790649414f,0.17700421810150146484f, +0.98310548067092895508f,0.18303988873958587646f,0.98196387290954589844f, +0.18906866014003753662f,0.98078525066375732422f,0.19509032368659973145f, +0.97956979274749755859f,0.20110464096069335938f,0.97831737995147705078f, +0.20711137354373931885f,0.97702813148498535156f,0.21311031281948089600f, +0.97570210695266723633f,0.21910123527050018311f,0.97433936595916748047f, +0.22508391737937927246f,0.97293996810913085938f,0.23105810582637786865f, +0.97150391340255737305f,0.23702360689640045166f,0.97003126144409179688f, +0.24298018217086791992f,0.96852207183837890625f,0.24892760813236236572f, +0.96697646379470825195f,0.25486564636230468750f,0.96539443731307983398f, +0.26079410314559936523f,0.96377605199813842773f,0.26671275496482849121f, +0.96212142705917358398f,0.27262136340141296387f,0.96043050289154052734f, +0.27851969003677368164f,0.95870345830917358398f,0.28440752625465393066f, +0.95694035291671752930f,0.29028466343879699707f,0.95514118671417236328f, +0.29615089297294616699f,0.95330601930618286133f,0.30200594663619995117f, +0.95143502950668334961f,0.30784964561462402344f,0.94952815771102905273f, +0.31368175148963928223f,0.94758558273315429688f,0.31950202584266662598f, +0.94560730457305908203f,0.32531028985977172852f,0.94359344244003295898f, +0.33110630512237548828f,0.94154405593872070312f,0.33688986301422119141f, +0.93945920467376708984f,0.34266072511672973633f,0.93733900785446166992f, +0.34841868281364440918f,0.93518352508544921875f,0.35416352748870849609f, +0.93299281597137451172f,0.35989505052566528320f,0.93076694011688232422f, +0.36561298370361328125f,0.92850607633590698242f,0.37131720781326293945f, +0.92621022462844848633f,0.37700742483139038086f,0.92387950420379638672f, +0.38268342614173889160f,0.92151403427124023438f,0.38834503293037414551f, +0.91911387443542480469f,0.39399203658103942871f,0.91667908430099487305f, +0.39962419867515563965f,0.91420978307723999023f,0.40524131059646606445f, +0.91170603036880493164f,0.41084316372871398926f,0.90916800498962402344f, +0.41642954945564270020f,0.90659570693969726562f,0.42200025916099548340f, +0.90398931503295898438f,0.42755508422851562500f,0.90134882926940917969f, +0.43309381604194641113f,0.89867448806762695312f,0.43861624598503112793f, +0.89596623182296752930f,0.44412213563919067383f,0.89322429895401000977f, +0.44961133599281311035f,0.89044874906539916992f,0.45508357882499694824f, +0.88763964176177978516f,0.46053871512413024902f,0.88479709625244140625f, +0.46597650647163391113f,0.88192129135131835938f,0.47139674425125122070f, +0.87901222705841064453f,0.47679921984672546387f,0.87607008218765258789f, +0.48218378424644470215f,0.87309497594833374023f,0.48755016922950744629f, +0.87008696794509887695f,0.49289819598197937012f,0.86704623699188232422f, +0.49822765588760375977f,0.86397284269332885742f,0.50353837013244628906f, +0.86086696386337280273f,0.50883013010025024414f,0.85772860050201416016f, +0.51410275697708129883f,0.85455799102783203125f,0.51935601234436035156f, +0.85135519504547119141f,0.52458965778350830078f,0.84812033176422119141f, +0.52980363368988037109f,0.84485357999801635742f,0.53499764204025268555f, +0.84155499935150146484f,0.54017144441604614258f,0.83822470903396606445f, +0.54532498121261596680f,0.83486288785934448242f,0.55045795440673828125f, +0.83146959543228149414f,0.55557024478912353516f,0.82804507017135620117f, +0.56066155433654785156f,0.82458931207656860352f,0.56573182344436645508f, +0.82110249996185302734f,0.57078075408935546875f,0.81758481264114379883f, +0.57580816745758056641f,0.81403630971908569336f,0.58081394433975219727f, +0.81045717000961303711f,0.58579784631729125977f,0.80684757232666015625f, +0.59075969457626342773f,0.80320751667022705078f,0.59569931030273437500f, +0.79953724145889282227f,0.60061645507812500000f,0.79583692550659179688f, +0.60551106929779052734f,0.79210656881332397461f,0.61038279533386230469f, +0.78834640979766845703f,0.61523157358169555664f,0.78455656766891479492f, +0.62005722522735595703f,0.78073722124099731445f,0.62485951185226440430f, +0.77688848972320556641f,0.62963825464248657227f,0.77301043272018432617f, +0.63439327478408813477f,0.76910334825515747070f,0.63912445306777954102f, +0.76516723632812500000f,0.64383155107498168945f,0.76120239496231079102f, +0.64851438999176025391f,0.75720882415771484375f,0.65317285060882568359f, +0.75318682193756103516f,0.65780669450759887695f,0.74913638830184936523f, +0.66241580247879028320f,0.74505776166915893555f,0.66699993610382080078f, +0.74095112085342407227f,0.67155897617340087891f,0.73681658506393432617f, +0.67609268426895141602f,0.73265427350997924805f,0.68060100078582763672f, +0.72846436500549316406f,0.68508368730545043945f,0.72424709796905517578f, +0.68954056501388549805f,0.72000253200531005859f,0.69397145509719848633f, +0.71573084592819213867f,0.69837623834609985352f,0.71143221855163574219f, +0.70275473594665527344f,0.70710676908493041992f,0.70710676908493041992f, +0.70275473594665527344f,0.71143221855163574219f,0.69837623834609985352f, +0.71573084592819213867f,0.69397145509719848633f,0.72000253200531005859f, +0.68954056501388549805f,0.72424709796905517578f,0.68508368730545043945f, +0.72846436500549316406f,0.68060100078582763672f,0.73265427350997924805f, +0.67609268426895141602f,0.73681658506393432617f,0.67155897617340087891f, +0.74095112085342407227f,0.66699993610382080078f,0.74505776166915893555f, +0.66241580247879028320f,0.74913638830184936523f,0.65780669450759887695f, +0.75318682193756103516f,0.65317285060882568359f,0.75720882415771484375f, +0.64851438999176025391f,0.76120239496231079102f,0.64383155107498168945f, +0.76516723632812500000f,0.63912445306777954102f,0.76910334825515747070f, +0.63439327478408813477f,0.77301043272018432617f,0.62963825464248657227f, +0.77688848972320556641f,0.62485951185226440430f,0.78073722124099731445f, +0.62005722522735595703f,0.78455656766891479492f,0.61523157358169555664f, +0.78834640979766845703f,0.61038279533386230469f,0.79210656881332397461f, +0.60551106929779052734f,0.79583692550659179688f,0.60061645507812500000f, +0.79953724145889282227f,0.59569931030273437500f,0.80320751667022705078f, +0.59075969457626342773f,0.80684757232666015625f,0.58579784631729125977f, +0.81045717000961303711f,0.58081394433975219727f,0.81403630971908569336f, +0.57580816745758056641f,0.81758481264114379883f,0.57078075408935546875f, +0.82110249996185302734f,0.56573182344436645508f,0.82458931207656860352f, +0.56066155433654785156f,0.82804507017135620117f,0.55557024478912353516f, +0.83146959543228149414f,0.55045795440673828125f,0.83486288785934448242f, +0.54532498121261596680f,0.83822470903396606445f,0.54017144441604614258f, +0.84155499935150146484f,0.53499764204025268555f,0.84485357999801635742f, +0.52980363368988037109f,0.84812033176422119141f,0.52458965778350830078f, +0.85135519504547119141f,0.51935601234436035156f,0.85455799102783203125f, +0.51410275697708129883f,0.85772860050201416016f,0.50883013010025024414f, +0.86086696386337280273f,0.50353837013244628906f,0.86397284269332885742f, +0.49822765588760375977f,0.86704623699188232422f,0.49289819598197937012f, +0.87008696794509887695f,0.48755016922950744629f,0.87309497594833374023f, +0.48218378424644470215f,0.87607008218765258789f,0.47679921984672546387f, +0.87901222705841064453f,0.47139674425125122070f,0.88192129135131835938f, +0.46597650647163391113f,0.88479709625244140625f,0.46053871512413024902f, +0.88763964176177978516f,0.45508357882499694824f,0.89044874906539916992f, +0.44961133599281311035f,0.89322429895401000977f,0.44412213563919067383f, +0.89596623182296752930f,0.43861624598503112793f,0.89867448806762695312f, +0.43309381604194641113f,0.90134882926940917969f,0.42755508422851562500f, +0.90398931503295898438f,0.42200025916099548340f,0.90659570693969726562f, +0.41642954945564270020f,0.90916800498962402344f,0.41084316372871398926f, +0.91170603036880493164f,0.40524131059646606445f,0.91420978307723999023f, +0.39962419867515563965f,0.91667908430099487305f,0.39399203658103942871f, +0.91911387443542480469f,0.38834503293037414551f,0.92151403427124023438f, +0.38268342614173889160f,0.92387950420379638672f,0.37700742483139038086f, +0.92621022462844848633f,0.37131720781326293945f,0.92850607633590698242f, +0.36561298370361328125f,0.93076694011688232422f,0.35989505052566528320f, +0.93299281597137451172f,0.35416352748870849609f,0.93518352508544921875f, +0.34841868281364440918f,0.93733900785446166992f,0.34266072511672973633f, +0.93945920467376708984f,0.33688986301422119141f,0.94154405593872070312f, +0.33110630512237548828f,0.94359344244003295898f,0.32531028985977172852f, +0.94560730457305908203f,0.31950202584266662598f,0.94758558273315429688f, +0.31368175148963928223f,0.94952815771102905273f,0.30784964561462402344f, +0.95143502950668334961f,0.30200594663619995117f,0.95330601930618286133f, +0.29615089297294616699f,0.95514118671417236328f,0.29028466343879699707f, +0.95694035291671752930f,0.28440752625465393066f,0.95870345830917358398f, +0.27851969003677368164f,0.96043050289154052734f,0.27262136340141296387f, +0.96212142705917358398f,0.26671275496482849121f,0.96377605199813842773f, +0.26079410314559936523f,0.96539443731307983398f,0.25486564636230468750f, +0.96697646379470825195f,0.24892760813236236572f,0.96852207183837890625f, +0.24298018217086791992f,0.97003126144409179688f,0.23702360689640045166f, +0.97150391340255737305f,0.23105810582637786865f,0.97293996810913085938f, +0.22508391737937927246f,0.97433936595916748047f,0.21910123527050018311f, +0.97570210695266723633f,0.21311031281948089600f,0.97702813148498535156f, +0.20711137354373931885f,0.97831737995147705078f,0.20110464096069335938f, +0.97956979274749755859f,0.19509032368659973145f,0.98078525066375732422f, +0.18906866014003753662f,0.98196387290954589844f,0.18303988873958587646f, +0.98310548067092895508f,0.17700421810150146484f,0.98421007394790649414f, +0.17096188664436340332f,0.98527765274047851562f,0.16491311788558959961f, +0.98630809783935546875f,0.15885815024375915527f,0.98730140924453735352f, +0.15279719233512878418f,0.98825758695602416992f,0.14673046767711639404f, +0.98917651176452636719f,0.14065824449062347412f,0.99005818367004394531f, +0.13458070158958435059f,0.99090266227722167969f,0.12849810719490051270f, +0.99170976877212524414f,0.12241067737340927124f,0.99247956275939941406f, +0.11631862819194793701f,0.99321192502975463867f,0.11022220551967620850f, +0.99390697479248046875f,0.10412163287401199341f,0.99456459283828735352f, +0.09801714122295379639f,0.99518471956253051758f,0.09190895408391952515f, +0.99576741456985473633f,0.08579730987548828125f,0.99631261825561523438f, +0.07968243956565856934f,0.99682027101516723633f,0.07356456667184829712f, +0.99729043245315551758f,0.06744392216205596924f,0.99772304296493530273f, +0.06132073700428009033f,0.99811810255050659180f,0.05519524589180946350f, +0.99847555160522460938f,0.04906767606735229492f,0.99879544973373413086f, +0.04293825849890708923f,0.99907773733139038086f,0.03680722415447235107f, +0.99932235479354858398f,0.03067480400204658508f,0.99952942132949829102f, +0.02454122900962829590f,0.99969881772994995117f,0.01840673014521598816f, +0.99983060359954833984f,0.01227153837680816650f,0.99992471933364868164f, +0.00613588467240333557f,0.99998116493225097656f,1.00000000000000000000f, +0.00000000000000000000f,0.99969881772994995117f,0.02454122900962829590f, +0.99879544973373413086f,0.04906767606735229492f,0.99729043245315551758f, +0.07356456667184829712f,0.99518471956253051758f,0.09801714122295379639f, +0.99247956275939941406f,0.12241067737340927124f,0.98917651176452636719f, +0.14673046767711639404f,0.98527765274047851562f,0.17096188664436340332f, +0.98078525066375732422f,0.19509032368659973145f,0.97570210695266723633f, +0.21910123527050018311f,0.97003126144409179688f,0.24298018217086791992f, +0.96377605199813842773f,0.26671275496482849121f,0.95694035291671752930f, +0.29028466343879699707f,0.94952815771102905273f,0.31368175148963928223f, +0.94154405593872070312f,0.33688986301422119141f,0.93299281597137451172f, +0.35989505052566528320f,0.92387950420379638672f,0.38268342614173889160f, +0.91420978307723999023f,0.40524131059646606445f,0.90398931503295898438f, +0.42755508422851562500f,0.89322429895401000977f,0.44961133599281311035f, +0.88192129135131835938f,0.47139674425125122070f,0.87008696794509887695f, +0.49289819598197937012f,0.85772860050201416016f,0.51410275697708129883f, +0.84485357999801635742f,0.53499764204025268555f,0.83146959543228149414f, +0.55557024478912353516f,0.81758481264114379883f,0.57580816745758056641f, +0.80320751667022705078f,0.59569931030273437500f,0.78834640979766845703f, +0.61523157358169555664f,0.77301043272018432617f,0.63439327478408813477f, +0.75720882415771484375f,0.65317285060882568359f,0.74095112085342407227f, +0.67155897617340087891f,0.72424709796905517578f,0.68954056501388549805f, +0.70710676908493041992f,0.70710676908493041992f,0.68954056501388549805f, +0.72424709796905517578f,0.67155897617340087891f,0.74095112085342407227f, +0.65317285060882568359f,0.75720882415771484375f,0.63439327478408813477f, +0.77301043272018432617f,0.61523157358169555664f,0.78834640979766845703f, +0.59569931030273437500f,0.80320751667022705078f,0.57580816745758056641f, +0.81758481264114379883f,0.55557024478912353516f,0.83146959543228149414f, +0.53499764204025268555f,0.84485357999801635742f,0.51410275697708129883f, +0.85772860050201416016f,0.49289819598197937012f,0.87008696794509887695f, +0.47139674425125122070f,0.88192129135131835938f,0.44961133599281311035f, +0.89322429895401000977f,0.42755508422851562500f,0.90398931503295898438f, +0.40524131059646606445f,0.91420978307723999023f,0.38268342614173889160f, +0.92387950420379638672f,0.35989505052566528320f,0.93299281597137451172f, +0.33688986301422119141f,0.94154405593872070312f,0.31368175148963928223f, +0.94952815771102905273f,0.29028466343879699707f,0.95694035291671752930f, +0.26671275496482849121f,0.96377605199813842773f,0.24298018217086791992f, +0.97003126144409179688f,0.21910123527050018311f,0.97570210695266723633f, +0.19509032368659973145f,0.98078525066375732422f,0.17096188664436340332f, +0.98527765274047851562f,0.14673046767711639404f,0.98917651176452636719f, +0.12241067737340927124f,0.99247956275939941406f,0.09801714122295379639f, +0.99518471956253051758f,0.07356456667184829712f,0.99729043245315551758f, +0.04906767606735229492f,0.99879544973373413086f,0.02454122900962829590f, +0.99969881772994995117f,1.00000000000000000000f,0.00000000000000000000f, +0.99518471956253051758f,0.09801714122295379639f,0.98078525066375732422f, +0.19509032368659973145f,0.95694035291671752930f,0.29028466343879699707f, +0.92387950420379638672f,0.38268342614173889160f,0.88192129135131835938f, +0.47139674425125122070f,0.83146959543228149414f,0.55557024478912353516f, +0.77301043272018432617f,0.63439327478408813477f,0.70710676908493041992f, +0.70710676908493041992f,0.63439327478408813477f,0.77301043272018432617f, +0.55557024478912353516f,0.83146959543228149414f,0.47139674425125122070f, +0.88192129135131835938f,0.38268342614173889160f,0.92387950420379638672f, +0.29028466343879699707f,0.95694035291671752930f,0.19509032368659973145f, +0.98078525066375732422f,0.09801714122295379639f,0.99518471956253051758f, +1.00000000000000000000f,0.00000000000000000000f,0.92387950420379638672f, +0.38268342614173889160f,0.70710676908493041992f,0.70710676908493041992f, +0.38268342614173889160f,0.92387950420379638672f,}; + +float32_t rearranged_twiddle_stride2_1024_f32[680]={ +1.00000000000000000000f,0.00000000000000000000f,0.99992471933364868164f, +0.01227153837680816650f,0.99969881772994995117f,0.02454122900962829590f, +0.99932235479354858398f,0.03680722415447235107f,0.99879544973373413086f, +0.04906767606735229492f,0.99811810255050659180f,0.06132073700428009033f, +0.99729043245315551758f,0.07356456667184829712f,0.99631261825561523438f, +0.08579730987548828125f,0.99518471956253051758f,0.09801714122295379639f, +0.99390697479248046875f,0.11022220551967620850f,0.99247956275939941406f, +0.12241067737340927124f,0.99090266227722167969f,0.13458070158958435059f, +0.98917651176452636719f,0.14673046767711639404f,0.98730140924453735352f, +0.15885815024375915527f,0.98527765274047851562f,0.17096188664436340332f, +0.98310548067092895508f,0.18303988873958587646f,0.98078525066375732422f, +0.19509032368659973145f,0.97831737995147705078f,0.20711137354373931885f, +0.97570210695266723633f,0.21910123527050018311f,0.97293996810913085938f, +0.23105810582637786865f,0.97003126144409179688f,0.24298018217086791992f, +0.96697646379470825195f,0.25486564636230468750f,0.96377605199813842773f, +0.26671275496482849121f,0.96043050289154052734f,0.27851969003677368164f, +0.95694035291671752930f,0.29028466343879699707f,0.95330601930618286133f, +0.30200594663619995117f,0.94952815771102905273f,0.31368175148963928223f, +0.94560730457305908203f,0.32531028985977172852f,0.94154405593872070312f, +0.33688986301422119141f,0.93733900785446166992f,0.34841868281364440918f, +0.93299281597137451172f,0.35989505052566528320f,0.92850607633590698242f, +0.37131720781326293945f,0.92387950420379638672f,0.38268342614173889160f, +0.91911387443542480469f,0.39399203658103942871f,0.91420978307723999023f, +0.40524131059646606445f,0.90916800498962402344f,0.41642954945564270020f, +0.90398931503295898438f,0.42755508422851562500f,0.89867448806762695312f, +0.43861624598503112793f,0.89322429895401000977f,0.44961133599281311035f, +0.88763964176177978516f,0.46053871512413024902f,0.88192129135131835938f, +0.47139674425125122070f,0.87607008218765258789f,0.48218378424644470215f, +0.87008696794509887695f,0.49289819598197937012f,0.86397284269332885742f, +0.50353837013244628906f,0.85772860050201416016f,0.51410275697708129883f, +0.85135519504547119141f,0.52458965778350830078f,0.84485357999801635742f, +0.53499764204025268555f,0.83822470903396606445f,0.54532498121261596680f, +0.83146959543228149414f,0.55557024478912353516f,0.82458931207656860352f, +0.56573182344436645508f,0.81758481264114379883f,0.57580816745758056641f, +0.81045717000961303711f,0.58579784631729125977f,0.80320751667022705078f, +0.59569931030273437500f,0.79583692550659179688f,0.60551106929779052734f, +0.78834640979766845703f,0.61523157358169555664f,0.78073722124099731445f, +0.62485951185226440430f,0.77301043272018432617f,0.63439327478408813477f, +0.76516723632812500000f,0.64383155107498168945f,0.75720882415771484375f, +0.65317285060882568359f,0.74913638830184936523f,0.66241580247879028320f, +0.74095112085342407227f,0.67155897617340087891f,0.73265427350997924805f, +0.68060100078582763672f,0.72424709796905517578f,0.68954056501388549805f, +0.71573084592819213867f,0.69837623834609985352f,0.70710676908493041992f, +0.70710676908493041992f,0.69837623834609985352f,0.71573084592819213867f, +0.68954056501388549805f,0.72424709796905517578f,0.68060100078582763672f, +0.73265427350997924805f,0.67155897617340087891f,0.74095112085342407227f, +0.66241580247879028320f,0.74913638830184936523f,0.65317285060882568359f, +0.75720882415771484375f,0.64383155107498168945f,0.76516723632812500000f, +0.63439327478408813477f,0.77301043272018432617f,0.62485951185226440430f, +0.78073722124099731445f,0.61523157358169555664f,0.78834640979766845703f, +0.60551106929779052734f,0.79583692550659179688f,0.59569931030273437500f, +0.80320751667022705078f,0.58579784631729125977f,0.81045717000961303711f, +0.57580816745758056641f,0.81758481264114379883f,0.56573182344436645508f, +0.82458931207656860352f,0.55557024478912353516f,0.83146959543228149414f, +0.54532498121261596680f,0.83822470903396606445f,0.53499764204025268555f, +0.84485357999801635742f,0.52458965778350830078f,0.85135519504547119141f, +0.51410275697708129883f,0.85772860050201416016f,0.50353837013244628906f, +0.86397284269332885742f,0.49289819598197937012f,0.87008696794509887695f, +0.48218378424644470215f,0.87607008218765258789f,0.47139674425125122070f, +0.88192129135131835938f,0.46053871512413024902f,0.88763964176177978516f, +0.44961133599281311035f,0.89322429895401000977f,0.43861624598503112793f, +0.89867448806762695312f,0.42755508422851562500f,0.90398931503295898438f, +0.41642954945564270020f,0.90916800498962402344f,0.40524131059646606445f, +0.91420978307723999023f,0.39399203658103942871f,0.91911387443542480469f, +0.38268342614173889160f,0.92387950420379638672f,0.37131720781326293945f, +0.92850607633590698242f,0.35989505052566528320f,0.93299281597137451172f, +0.34841868281364440918f,0.93733900785446166992f,0.33688986301422119141f, +0.94154405593872070312f,0.32531028985977172852f,0.94560730457305908203f, +0.31368175148963928223f,0.94952815771102905273f,0.30200594663619995117f, +0.95330601930618286133f,0.29028466343879699707f,0.95694035291671752930f, +0.27851969003677368164f,0.96043050289154052734f,0.26671275496482849121f, +0.96377605199813842773f,0.25486564636230468750f,0.96697646379470825195f, +0.24298018217086791992f,0.97003126144409179688f,0.23105810582637786865f, +0.97293996810913085938f,0.21910123527050018311f,0.97570210695266723633f, +0.20711137354373931885f,0.97831737995147705078f,0.19509032368659973145f, +0.98078525066375732422f,0.18303988873958587646f,0.98310548067092895508f, +0.17096188664436340332f,0.98527765274047851562f,0.15885815024375915527f, +0.98730140924453735352f,0.14673046767711639404f,0.98917651176452636719f, +0.13458070158958435059f,0.99090266227722167969f,0.12241067737340927124f, +0.99247956275939941406f,0.11022220551967620850f,0.99390697479248046875f, +0.09801714122295379639f,0.99518471956253051758f,0.08579730987548828125f, +0.99631261825561523438f,0.07356456667184829712f,0.99729043245315551758f, +0.06132073700428009033f,0.99811810255050659180f,0.04906767606735229492f, +0.99879544973373413086f,0.03680722415447235107f,0.99932235479354858398f, +0.02454122900962829590f,0.99969881772994995117f,0.01227153837680816650f, +0.99992471933364868164f,0.00000000000000006123f,1.00000000000000000000f, +-0.01227153837680816650f,0.99992471933364868164f,-0.02454122900962829590f, +0.99969881772994995117f,-0.03680722415447235107f,0.99932235479354858398f, +-0.04906767606735229492f,0.99879544973373413086f,-0.06132073700428009033f, +0.99811810255050659180f,-0.07356456667184829712f,0.99729043245315551758f, +-0.08579730987548828125f,0.99631261825561523438f,-0.09801714122295379639f, +0.99518471956253051758f,-0.11022220551967620850f,0.99390697479248046875f, +-0.12241067737340927124f,0.99247956275939941406f,-0.13458070158958435059f, +0.99090266227722167969f,-0.14673046767711639404f,0.98917651176452636719f, +-0.15885815024375915527f,0.98730140924453735352f,-0.17096188664436340332f, +0.98527765274047851562f,-0.18303988873958587646f,0.98310548067092895508f, +-0.19509032368659973145f,0.98078525066375732422f,-0.20711137354373931885f, +0.97831737995147705078f,-0.21910123527050018311f,0.97570210695266723633f, +-0.23105810582637786865f,0.97293996810913085938f,-0.24298018217086791992f, +0.97003126144409179688f,-0.25486564636230468750f,0.96697646379470825195f, +-0.26671275496482849121f,0.96377605199813842773f,-0.27851969003677368164f, +0.96043050289154052734f,-0.29028466343879699707f,0.95694035291671752930f, +-0.30200594663619995117f,0.95330601930618286133f,-0.31368175148963928223f, +0.94952815771102905273f,-0.32531028985977172852f,0.94560730457305908203f, +-0.33688986301422119141f,0.94154405593872070312f,-0.34841868281364440918f, +0.93733900785446166992f,-0.35989505052566528320f,0.93299281597137451172f, +-0.37131720781326293945f,0.92850607633590698242f,-0.38268342614173889160f, +0.92387950420379638672f,-0.39399203658103942871f,0.91911387443542480469f, +-0.40524131059646606445f,0.91420978307723999023f,-0.41642954945564270020f, +0.90916800498962402344f,-0.42755508422851562500f,0.90398931503295898438f, +-0.43861624598503112793f,0.89867448806762695312f,-0.44961133599281311035f, +0.89322429895401000977f,-0.46053871512413024902f,0.88763964176177978516f, +-0.47139674425125122070f,0.88192129135131835938f,-0.48218378424644470215f, +0.87607008218765258789f,-0.49289819598197937012f,0.87008696794509887695f, +-0.50353837013244628906f,0.86397284269332885742f,-0.51410275697708129883f, +0.85772860050201416016f,-0.52458965778350830078f,0.85135519504547119141f, +-0.53499764204025268555f,0.84485357999801635742f,-0.54532498121261596680f, +0.83822470903396606445f,-0.55557024478912353516f,0.83146959543228149414f, +-0.56573182344436645508f,0.82458931207656860352f,-0.57580816745758056641f, +0.81758481264114379883f,-0.58579784631729125977f,0.81045717000961303711f, +-0.59569931030273437500f,0.80320751667022705078f,-0.60551106929779052734f, +0.79583692550659179688f,-0.61523157358169555664f,0.78834640979766845703f, +-0.62485951185226440430f,0.78073722124099731445f,-0.63439327478408813477f, +0.77301043272018432617f,-0.64383155107498168945f,0.76516723632812500000f, +-0.65317285060882568359f,0.75720882415771484375f,-0.66241580247879028320f, +0.74913638830184936523f,-0.67155897617340087891f,0.74095112085342407227f, +-0.68060100078582763672f,0.73265427350997924805f,-0.68954056501388549805f, +0.72424709796905517578f,-0.69837623834609985352f,0.71573084592819213867f, +-0.70710676908493041992f,0.70710676908493041992f,-0.71573084592819213867f, +0.69837623834609985352f,-0.72424709796905517578f,0.68954056501388549805f, +-0.73265427350997924805f,0.68060100078582763672f,-0.74095112085342407227f, +0.67155897617340087891f,-0.74913638830184936523f,0.66241580247879028320f, +-0.75720882415771484375f,0.65317285060882568359f,-0.76516723632812500000f, +0.64383155107498168945f,-0.77301043272018432617f,0.63439327478408813477f, +-0.78073722124099731445f,0.62485951185226440430f,-0.78834640979766845703f, +0.61523157358169555664f,-0.79583692550659179688f,0.60551106929779052734f, +-0.80320751667022705078f,0.59569931030273437500f,-0.81045717000961303711f, +0.58579784631729125977f,-0.81758481264114379883f,0.57580816745758056641f, +-0.82458931207656860352f,0.56573182344436645508f,-0.83146959543228149414f, +0.55557024478912353516f,-0.83822470903396606445f,0.54532498121261596680f, +-0.84485357999801635742f,0.53499764204025268555f,-0.85135519504547119141f, +0.52458965778350830078f,-0.85772860050201416016f,0.51410275697708129883f, +-0.86397284269332885742f,0.50353837013244628906f,-0.87008696794509887695f, +0.49289819598197937012f,-0.87607008218765258789f,0.48218378424644470215f, +-0.88192129135131835938f,0.47139674425125122070f,-0.88763964176177978516f, +0.46053871512413024902f,-0.89322429895401000977f,0.44961133599281311035f, +-0.89867448806762695312f,0.43861624598503112793f,-0.90398931503295898438f, +0.42755508422851562500f,-0.90916800498962402344f,0.41642954945564270020f, +-0.91420978307723999023f,0.40524131059646606445f,-0.91911387443542480469f, +0.39399203658103942871f,-0.92387950420379638672f,0.38268342614173889160f, +-0.92850607633590698242f,0.37131720781326293945f,-0.93299281597137451172f, +0.35989505052566528320f,-0.93733900785446166992f,0.34841868281364440918f, +-0.94154405593872070312f,0.33688986301422119141f,-0.94560730457305908203f, +0.32531028985977172852f,-0.94952815771102905273f,0.31368175148963928223f, +-0.95330601930618286133f,0.30200594663619995117f,-0.95694035291671752930f, +0.29028466343879699707f,-0.96043050289154052734f,0.27851969003677368164f, +-0.96377605199813842773f,0.26671275496482849121f,-0.96697646379470825195f, +0.25486564636230468750f,-0.97003126144409179688f,0.24298018217086791992f, +-0.97293996810913085938f,0.23105810582637786865f,-0.97570210695266723633f, +0.21910123527050018311f,-0.97831737995147705078f,0.20711137354373931885f, +-0.98078525066375732422f,0.19509032368659973145f,-0.98310548067092895508f, +0.18303988873958587646f,-0.98527765274047851562f,0.17096188664436340332f, +-0.98730140924453735352f,0.15885815024375915527f,-0.98917651176452636719f, +0.14673046767711639404f,-0.99090266227722167969f,0.13458070158958435059f, +-0.99247956275939941406f,0.12241067737340927124f,-0.99390697479248046875f, +0.11022220551967620850f,-0.99518471956253051758f,0.09801714122295379639f, +-0.99631261825561523438f,0.08579730987548828125f,-0.99729043245315551758f, +0.07356456667184829712f,-0.99811810255050659180f,0.06132073700428009033f, +-0.99879544973373413086f,0.04906767606735229492f,-0.99932235479354858398f, +0.03680722415447235107f,-0.99969881772994995117f,0.02454122900962829590f, +-0.99992471933364868164f,0.01227153837680816650f,1.00000000000000000000f, +0.00000000000000000000f,0.99879544973373413086f,0.04906767606735229492f, +0.99518471956253051758f,0.09801714122295379639f,0.98917651176452636719f, +0.14673046767711639404f,0.98078525066375732422f,0.19509032368659973145f, +0.97003126144409179688f,0.24298018217086791992f,0.95694035291671752930f, +0.29028466343879699707f,0.94154405593872070312f,0.33688986301422119141f, +0.92387950420379638672f,0.38268342614173889160f,0.90398931503295898438f, +0.42755508422851562500f,0.88192129135131835938f,0.47139674425125122070f, +0.85772860050201416016f,0.51410275697708129883f,0.83146959543228149414f, +0.55557024478912353516f,0.80320751667022705078f,0.59569931030273437500f, +0.77301043272018432617f,0.63439327478408813477f,0.74095112085342407227f, +0.67155897617340087891f,0.70710676908493041992f,0.70710676908493041992f, +0.67155897617340087891f,0.74095112085342407227f,0.63439327478408813477f, +0.77301043272018432617f,0.59569931030273437500f,0.80320751667022705078f, +0.55557024478912353516f,0.83146959543228149414f,0.51410275697708129883f, +0.85772860050201416016f,0.47139674425125122070f,0.88192129135131835938f, +0.42755508422851562500f,0.90398931503295898438f,0.38268342614173889160f, +0.92387950420379638672f,0.33688986301422119141f,0.94154405593872070312f, +0.29028466343879699707f,0.95694035291671752930f,0.24298018217086791992f, +0.97003126144409179688f,0.19509032368659973145f,0.98078525066375732422f, +0.14673046767711639404f,0.98917651176452636719f,0.09801714122295379639f, +0.99518471956253051758f,0.04906767606735229492f,0.99879544973373413086f, +0.00000000000000006123f,1.00000000000000000000f,-0.04906767606735229492f, +0.99879544973373413086f,-0.09801714122295379639f,0.99518471956253051758f, +-0.14673046767711639404f,0.98917651176452636719f,-0.19509032368659973145f, +0.98078525066375732422f,-0.24298018217086791992f,0.97003126144409179688f, +-0.29028466343879699707f,0.95694035291671752930f,-0.33688986301422119141f, +0.94154405593872070312f,-0.38268342614173889160f,0.92387950420379638672f, +-0.42755508422851562500f,0.90398931503295898438f,-0.47139674425125122070f, +0.88192129135131835938f,-0.51410275697708129883f,0.85772860050201416016f, +-0.55557024478912353516f,0.83146959543228149414f,-0.59569931030273437500f, +0.80320751667022705078f,-0.63439327478408813477f,0.77301043272018432617f, +-0.67155897617340087891f,0.74095112085342407227f,-0.70710676908493041992f, +0.70710676908493041992f,-0.74095112085342407227f,0.67155897617340087891f, +-0.77301043272018432617f,0.63439327478408813477f,-0.80320751667022705078f, +0.59569931030273437500f,-0.83146959543228149414f,0.55557024478912353516f, +-0.85772860050201416016f,0.51410275697708129883f,-0.88192129135131835938f, +0.47139674425125122070f,-0.90398931503295898438f,0.42755508422851562500f, +-0.92387950420379638672f,0.38268342614173889160f,-0.94154405593872070312f, +0.33688986301422119141f,-0.95694035291671752930f,0.29028466343879699707f, +-0.97003126144409179688f,0.24298018217086791992f,-0.98078525066375732422f, +0.19509032368659973145f,-0.98917651176452636719f,0.14673046767711639404f, +-0.99518471956253051758f,0.09801714122295379639f,-0.99879544973373413086f, +0.04906767606735229492f,1.00000000000000000000f,0.00000000000000000000f, +0.98078525066375732422f,0.19509032368659973145f,0.92387950420379638672f, +0.38268342614173889160f,0.83146959543228149414f,0.55557024478912353516f, +0.70710676908493041992f,0.70710676908493041992f,0.55557024478912353516f, +0.83146959543228149414f,0.38268342614173889160f,0.92387950420379638672f, +0.19509032368659973145f,0.98078525066375732422f,0.00000000000000006123f, +1.00000000000000000000f,-0.19509032368659973145f,0.98078525066375732422f, +-0.38268342614173889160f,0.92387950420379638672f,-0.55557024478912353516f, +0.83146959543228149414f,-0.70710676908493041992f,0.70710676908493041992f, +-0.83146959543228149414f,0.55557024478912353516f,-0.92387950420379638672f, +0.38268342614173889160f,-0.98078525066375732422f,0.19509032368659973145f, +1.00000000000000000000f,0.00000000000000000000f,0.70710676908493041992f, +0.70710676908493041992f,0.00000000000000006123f,1.00000000000000000000f, +-0.70710676908493041992f,0.70710676908493041992f,}; + +float32_t rearranged_twiddle_stride3_1024_f32[680]={ +1.00000000000000000000f,0.00000000000000000000f,0.99983060359954833984f, +0.01840673014521598816f,0.99932235479354858398f,0.03680722415447235107f, +0.99847555160522460938f,0.05519524589180946350f,0.99729043245315551758f, +0.07356456667184829712f,0.99576741456985473633f,0.09190895408391952515f, +0.99390697479248046875f,0.11022220551967620850f,0.99170976877212524414f, +0.12849810719490051270f,0.98917651176452636719f,0.14673046767711639404f, +0.98630809783935546875f,0.16491311788558959961f,0.98310548067092895508f, +0.18303988873958587646f,0.97956979274749755859f,0.20110464096069335938f, +0.97570210695266723633f,0.21910123527050018311f,0.97150391340255737305f, +0.23702360689640045166f,0.96697646379470825195f,0.25486564636230468750f, +0.96212142705917358398f,0.27262136340141296387f,0.95694035291671752930f, +0.29028466343879699707f,0.95143502950668334961f,0.30784964561462402344f, +0.94560730457305908203f,0.32531028985977172852f,0.93945920467376708984f, +0.34266072511672973633f,0.93299281597137451172f,0.35989505052566528320f, +0.92621022462844848633f,0.37700742483139038086f,0.91911387443542480469f, +0.39399203658103942871f,0.91170603036880493164f,0.41084316372871398926f, +0.90398931503295898438f,0.42755508422851562500f,0.89596623182296752930f, +0.44412213563919067383f,0.88763964176177978516f,0.46053871512413024902f, +0.87901222705841064453f,0.47679921984672546387f,0.87008696794509887695f, +0.49289819598197937012f,0.86086696386337280273f,0.50883013010025024414f, +0.85135519504547119141f,0.52458965778350830078f,0.84155499935150146484f, +0.54017144441604614258f,0.83146959543228149414f,0.55557024478912353516f, +0.82110249996185302734f,0.57078075408935546875f,0.81045717000961303711f, +0.58579784631729125977f,0.79953724145889282227f,0.60061645507812500000f, +0.78834640979766845703f,0.61523157358169555664f,0.77688848972320556641f, +0.62963825464248657227f,0.76516723632812500000f,0.64383155107498168945f, +0.75318682193756103516f,0.65780669450759887695f,0.74095112085342407227f, +0.67155897617340087891f,0.72846436500549316406f,0.68508368730545043945f, +0.71573084592819213867f,0.69837623834609985352f,0.70275473594665527344f, +0.71143221855163574219f,0.68954056501388549805f,0.72424709796905517578f, +0.67609268426895141602f,0.73681658506393432617f,0.66241580247879028320f, +0.74913638830184936523f,0.64851438999176025391f,0.76120239496231079102f, +0.63439327478408813477f,0.77301043272018432617f,0.62005722522735595703f, +0.78455656766891479492f,0.60551106929779052734f,0.79583692550659179688f, +0.59075969457626342773f,0.80684757232666015625f,0.57580816745758056641f, +0.81758481264114379883f,0.56066155433654785156f,0.82804507017135620117f, +0.54532498121261596680f,0.83822470903396606445f,0.52980363368988037109f, +0.84812033176422119141f,0.51410275697708129883f,0.85772860050201416016f, +0.49822765588760375977f,0.86704623699188232422f,0.48218378424644470215f, +0.87607008218765258789f,0.46597650647163391113f,0.88479709625244140625f, +0.44961133599281311035f,0.89322429895401000977f,0.43309381604194641113f, +0.90134882926940917969f,0.41642954945564270020f,0.90916800498962402344f, +0.39962419867515563965f,0.91667908430099487305f,0.38268342614173889160f, +0.92387950420379638672f,0.36561298370361328125f,0.93076694011688232422f, +0.34841868281364440918f,0.93733900785446166992f,0.33110630512237548828f, +0.94359344244003295898f,0.31368175148963928223f,0.94952815771102905273f, +0.29615089297294616699f,0.95514118671417236328f,0.27851969003677368164f, +0.96043050289154052734f,0.26079410314559936523f,0.96539443731307983398f, +0.24298018217086791992f,0.97003126144409179688f,0.22508391737937927246f, +0.97433936595916748047f,0.20711137354373931885f,0.97831737995147705078f, +0.18906866014003753662f,0.98196387290954589844f,0.17096188664436340332f, +0.98527765274047851562f,0.15279719233512878418f,0.98825758695602416992f, +0.13458070158958435059f,0.99090266227722167969f,0.11631862819194793701f, +0.99321192502975463867f,0.09801714122295379639f,0.99518471956253051758f, +0.07968243956565856934f,0.99682027101516723633f,0.06132073700428009033f, +0.99811810255050659180f,0.04293825849890708923f,0.99907773733139038086f, +0.02454122900962829590f,0.99969881772994995117f,0.00613588467240333557f, +0.99998116493225097656f,-0.01227153837680816650f,0.99992471933364868164f, +-0.03067480400204658508f,0.99952942132949829102f,-0.04906767606735229492f, +0.99879544973373413086f,-0.06744392216205596924f,0.99772304296493530273f, +-0.08579730987548828125f,0.99631261825561523438f,-0.10412163287401199341f, +0.99456459283828735352f,-0.12241067737340927124f,0.99247956275939941406f, +-0.14065824449062347412f,0.99005818367004394531f,-0.15885815024375915527f, +0.98730140924453735352f,-0.17700421810150146484f,0.98421007394790649414f, +-0.19509032368659973145f,0.98078525066375732422f,-0.21311031281948089600f, +0.97702813148498535156f,-0.23105810582637786865f,0.97293996810913085938f, +-0.24892760813236236572f,0.96852207183837890625f,-0.26671275496482849121f, +0.96377605199813842773f,-0.28440752625465393066f,0.95870345830917358398f, +-0.30200594663619995117f,0.95330601930618286133f,-0.31950202584266662598f, +0.94758558273315429688f,-0.33688986301422119141f,0.94154405593872070312f, +-0.35416352748870849609f,0.93518352508544921875f,-0.37131720781326293945f, +0.92850607633590698242f,-0.38834503293037414551f,0.92151403427124023438f, +-0.40524131059646606445f,0.91420978307723999023f,-0.42200025916099548340f, +0.90659570693969726562f,-0.43861624598503112793f,0.89867448806762695312f, +-0.45508357882499694824f,0.89044874906539916992f,-0.47139674425125122070f, +0.88192129135131835938f,-0.48755016922950744629f,0.87309497594833374023f, +-0.50353837013244628906f,0.86397284269332885742f,-0.51935601234436035156f, +0.85455799102783203125f,-0.53499764204025268555f,0.84485357999801635742f, +-0.55045795440673828125f,0.83486288785934448242f,-0.56573182344436645508f, +0.82458931207656860352f,-0.58081394433975219727f,0.81403630971908569336f, +-0.59569931030273437500f,0.80320751667022705078f,-0.61038279533386230469f, +0.79210656881332397461f,-0.62485951185226440430f,0.78073722124099731445f, +-0.63912445306777954102f,0.76910334825515747070f,-0.65317285060882568359f, +0.75720882415771484375f,-0.66699993610382080078f,0.74505776166915893555f, +-0.68060100078582763672f,0.73265427350997924805f,-0.69397145509719848633f, +0.72000253200531005859f,-0.70710676908493041992f,0.70710676908493041992f, +-0.72000253200531005859f,0.69397145509719848633f,-0.73265427350997924805f, +0.68060100078582763672f,-0.74505776166915893555f,0.66699993610382080078f, +-0.75720882415771484375f,0.65317285060882568359f,-0.76910334825515747070f, +0.63912445306777954102f,-0.78073722124099731445f,0.62485951185226440430f, +-0.79210656881332397461f,0.61038279533386230469f,-0.80320751667022705078f, +0.59569931030273437500f,-0.81403630971908569336f,0.58081394433975219727f, +-0.82458931207656860352f,0.56573182344436645508f,-0.83486288785934448242f, +0.55045795440673828125f,-0.84485357999801635742f,0.53499764204025268555f, +-0.85455799102783203125f,0.51935601234436035156f,-0.86397284269332885742f, +0.50353837013244628906f,-0.87309497594833374023f,0.48755016922950744629f, +-0.88192129135131835938f,0.47139674425125122070f,-0.89044874906539916992f, +0.45508357882499694824f,-0.89867448806762695312f,0.43861624598503112793f, +-0.90659570693969726562f,0.42200025916099548340f,-0.91420978307723999023f, +0.40524131059646606445f,-0.92151403427124023438f,0.38834503293037414551f, +-0.92850607633590698242f,0.37131720781326293945f,-0.93518352508544921875f, +0.35416352748870849609f,-0.94154405593872070312f,0.33688986301422119141f, +-0.94758558273315429688f,0.31950202584266662598f,-0.95330601930618286133f, +0.30200594663619995117f,-0.95870345830917358398f,0.28440752625465393066f, +-0.96377605199813842773f,0.26671275496482849121f,-0.96852207183837890625f, +0.24892760813236236572f,-0.97293996810913085938f,0.23105810582637786865f, +-0.97702813148498535156f,0.21311031281948089600f,-0.98078525066375732422f, +0.19509032368659973145f,-0.98421007394790649414f,0.17700421810150146484f, +-0.98730140924453735352f,0.15885815024375915527f,-0.99005818367004394531f, +0.14065824449062347412f,-0.99247956275939941406f,0.12241067737340927124f, +-0.99456459283828735352f,0.10412163287401199341f,-0.99631261825561523438f, +0.08579730987548828125f,-0.99772304296493530273f,0.06744392216205596924f, +-0.99879544973373413086f,0.04906767606735229492f,-0.99952942132949829102f, +0.03067480400204658508f,-0.99992471933364868164f,0.01227153837680816650f, +-0.99998116493225097656f,-0.00613588467240333557f,-0.99969881772994995117f, +-0.02454122900962829590f,-0.99907773733139038086f,-0.04293825849890708923f, +-0.99811810255050659180f,-0.06132073700428009033f,-0.99682027101516723633f, +-0.07968243956565856934f,-0.99518471956253051758f,-0.09801714122295379639f, +-0.99321192502975463867f,-0.11631862819194793701f,-0.99090266227722167969f, +-0.13458070158958435059f,-0.98825758695602416992f,-0.15279719233512878418f, +-0.98527765274047851562f,-0.17096188664436340332f,-0.98196387290954589844f, +-0.18906866014003753662f,-0.97831737995147705078f,-0.20711137354373931885f, +-0.97433936595916748047f,-0.22508391737937927246f,-0.97003126144409179688f, +-0.24298018217086791992f,-0.96539443731307983398f,-0.26079410314559936523f, +-0.96043050289154052734f,-0.27851969003677368164f,-0.95514118671417236328f, +-0.29615089297294616699f,-0.94952815771102905273f,-0.31368175148963928223f, +-0.94359344244003295898f,-0.33110630512237548828f,-0.93733900785446166992f, +-0.34841868281364440918f,-0.93076694011688232422f,-0.36561298370361328125f, +-0.92387950420379638672f,-0.38268342614173889160f,-0.91667908430099487305f, +-0.39962419867515563965f,-0.90916800498962402344f,-0.41642954945564270020f, +-0.90134882926940917969f,-0.43309381604194641113f,-0.89322429895401000977f, +-0.44961133599281311035f,-0.88479709625244140625f,-0.46597650647163391113f, +-0.87607008218765258789f,-0.48218378424644470215f,-0.86704623699188232422f, +-0.49822765588760375977f,-0.85772860050201416016f,-0.51410275697708129883f, +-0.84812033176422119141f,-0.52980363368988037109f,-0.83822470903396606445f, +-0.54532498121261596680f,-0.82804507017135620117f,-0.56066155433654785156f, +-0.81758481264114379883f,-0.57580816745758056641f,-0.80684757232666015625f, +-0.59075969457626342773f,-0.79583692550659179688f,-0.60551106929779052734f, +-0.78455656766891479492f,-0.62005722522735595703f,-0.77301043272018432617f, +-0.63439327478408813477f,-0.76120239496231079102f,-0.64851438999176025391f, +-0.74913638830184936523f,-0.66241580247879028320f,-0.73681658506393432617f, +-0.67609268426895141602f,-0.72424709796905517578f,-0.68954056501388549805f, +-0.71143221855163574219f,-0.70275473594665527344f,-0.69837623834609985352f, +-0.71573084592819213867f,-0.68508368730545043945f,-0.72846436500549316406f, +-0.67155897617340087891f,-0.74095112085342407227f,-0.65780669450759887695f, +-0.75318682193756103516f,-0.64383155107498168945f,-0.76516723632812500000f, +-0.62963825464248657227f,-0.77688848972320556641f,-0.61523157358169555664f, +-0.78834640979766845703f,-0.60061645507812500000f,-0.79953724145889282227f, +-0.58579784631729125977f,-0.81045717000961303711f,-0.57078075408935546875f, +-0.82110249996185302734f,-0.55557024478912353516f,-0.83146959543228149414f, +-0.54017144441604614258f,-0.84155499935150146484f,-0.52458965778350830078f, +-0.85135519504547119141f,-0.50883013010025024414f,-0.86086696386337280273f, +-0.49289819598197937012f,-0.87008696794509887695f,-0.47679921984672546387f, +-0.87901222705841064453f,-0.46053871512413024902f,-0.88763964176177978516f, +-0.44412213563919067383f,-0.89596623182296752930f,-0.42755508422851562500f, +-0.90398931503295898438f,-0.41084316372871398926f,-0.91170603036880493164f, +-0.39399203658103942871f,-0.91911387443542480469f,-0.37700742483139038086f, +-0.92621022462844848633f,-0.35989505052566528320f,-0.93299281597137451172f, +-0.34266072511672973633f,-0.93945920467376708984f,-0.32531028985977172852f, +-0.94560730457305908203f,-0.30784964561462402344f,-0.95143502950668334961f, +-0.29028466343879699707f,-0.95694035291671752930f,-0.27262136340141296387f, +-0.96212142705917358398f,-0.25486564636230468750f,-0.96697646379470825195f, +-0.23702360689640045166f,-0.97150391340255737305f,-0.21910123527050018311f, +-0.97570210695266723633f,-0.20110464096069335938f,-0.97956979274749755859f, +-0.18303988873958587646f,-0.98310548067092895508f,-0.16491311788558959961f, +-0.98630809783935546875f,-0.14673046767711639404f,-0.98917651176452636719f, +-0.12849810719490051270f,-0.99170976877212524414f,-0.11022220551967620850f, +-0.99390697479248046875f,-0.09190895408391952515f,-0.99576741456985473633f, +-0.07356456667184829712f,-0.99729043245315551758f,-0.05519524589180946350f, +-0.99847555160522460938f,-0.03680722415447235107f,-0.99932235479354858398f, +-0.01840673014521598816f,-0.99983060359954833984f,1.00000000000000000000f, +0.00000000000000000000f,0.99729043245315551758f,0.07356456667184829712f, +0.98917651176452636719f,0.14673046767711639404f,0.97570210695266723633f, +0.21910123527050018311f,0.95694035291671752930f,0.29028466343879699707f, +0.93299281597137451172f,0.35989505052566528320f,0.90398931503295898438f, +0.42755508422851562500f,0.87008696794509887695f,0.49289819598197937012f, +0.83146959543228149414f,0.55557024478912353516f,0.78834640979766845703f, +0.61523157358169555664f,0.74095112085342407227f,0.67155897617340087891f, +0.68954056501388549805f,0.72424709796905517578f,0.63439327478408813477f, +0.77301043272018432617f,0.57580816745758056641f,0.81758481264114379883f, +0.51410275697708129883f,0.85772860050201416016f,0.44961133599281311035f, +0.89322429895401000977f,0.38268342614173889160f,0.92387950420379638672f, +0.31368175148963928223f,0.94952815771102905273f,0.24298018217086791992f, +0.97003126144409179688f,0.17096188664436340332f,0.98527765274047851562f, +0.09801714122295379639f,0.99518471956253051758f,0.02454122900962829590f, +0.99969881772994995117f,-0.04906767606735229492f,0.99879544973373413086f, +-0.12241067737340927124f,0.99247956275939941406f,-0.19509032368659973145f, +0.98078525066375732422f,-0.26671275496482849121f,0.96377605199813842773f, +-0.33688986301422119141f,0.94154405593872070312f,-0.40524131059646606445f, +0.91420978307723999023f,-0.47139674425125122070f,0.88192129135131835938f, +-0.53499764204025268555f,0.84485357999801635742f,-0.59569931030273437500f, +0.80320751667022705078f,-0.65317285060882568359f,0.75720882415771484375f, +-0.70710676908493041992f,0.70710676908493041992f,-0.75720882415771484375f, +0.65317285060882568359f,-0.80320751667022705078f,0.59569931030273437500f, +-0.84485357999801635742f,0.53499764204025268555f,-0.88192129135131835938f, +0.47139674425125122070f,-0.91420978307723999023f,0.40524131059646606445f, +-0.94154405593872070312f,0.33688986301422119141f,-0.96377605199813842773f, +0.26671275496482849121f,-0.98078525066375732422f,0.19509032368659973145f, +-0.99247956275939941406f,0.12241067737340927124f,-0.99879544973373413086f, +0.04906767606735229492f,-0.99969881772994995117f,-0.02454122900962829590f, +-0.99518471956253051758f,-0.09801714122295379639f,-0.98527765274047851562f, +-0.17096188664436340332f,-0.97003126144409179688f,-0.24298018217086791992f, +-0.94952815771102905273f,-0.31368175148963928223f,-0.92387950420379638672f, +-0.38268342614173889160f,-0.89322429895401000977f,-0.44961133599281311035f, +-0.85772860050201416016f,-0.51410275697708129883f,-0.81758481264114379883f, +-0.57580816745758056641f,-0.77301043272018432617f,-0.63439327478408813477f, +-0.72424709796905517578f,-0.68954056501388549805f,-0.67155897617340087891f, +-0.74095112085342407227f,-0.61523157358169555664f,-0.78834640979766845703f, +-0.55557024478912353516f,-0.83146959543228149414f,-0.49289819598197937012f, +-0.87008696794509887695f,-0.42755508422851562500f,-0.90398931503295898438f, +-0.35989505052566528320f,-0.93299281597137451172f,-0.29028466343879699707f, +-0.95694035291671752930f,-0.21910123527050018311f,-0.97570210695266723633f, +-0.14673046767711639404f,-0.98917651176452636719f,-0.07356456667184829712f, +-0.99729043245315551758f,1.00000000000000000000f,0.00000000000000000000f, +0.95694035291671752930f,0.29028466343879699707f,0.83146959543228149414f, +0.55557024478912353516f,0.63439327478408813477f,0.77301043272018432617f, +0.38268342614173889160f,0.92387950420379638672f,0.09801714122295379639f, +0.99518471956253051758f,-0.19509032368659973145f,0.98078525066375732422f, +-0.47139674425125122070f,0.88192129135131835938f,-0.70710676908493041992f, +0.70710676908493041992f,-0.88192129135131835938f,0.47139674425125122070f, +-0.98078525066375732422f,0.19509032368659973145f,-0.99518471956253051758f, +-0.09801714122295379639f,-0.92387950420379638672f,-0.38268342614173889160f, +-0.77301043272018432617f,-0.63439327478408813477f,-0.55557024478912353516f, +-0.83146959543228149414f,-0.29028466343879699707f,-0.95694035291671752930f, +1.00000000000000000000f,0.00000000000000000000f,0.38268342614173889160f, +0.92387950420379638672f,-0.70710676908493041992f,0.70710676908493041992f, +-0.92387950420379638672f,-0.38268342614173889160f,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) || defined(ARM_TABLE_TWIDDLECOEF_F32_8192) + +uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6]={ +0,2048,2560,2688,2720,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6]={ +0,2048,2560,2688,2720,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6]={ +0,2048,2560,2688,2720,0,}; + +float32_t rearranged_twiddle_stride1_4096_f32[2728]={ +1.00000000000000000000f,0.00000000000000000000f,0.99999880790710449219f, +0.00153398013208061457f,0.99999529123306274414f,0.00306795677170157433f, +0.99998939037322998047f,0.00460192607715725899f,0.99998116493225097656f, +0.00613588467240333557f,0.99997061491012573242f,0.00766982883214950562f, +0.99995762109756469727f,0.00920375436544418335f,0.99994236230850219727f, +0.01073765940964221954f,0.99992471933364868164f,0.01227153837680816650f, +0.99990469217300415039f,0.01380538847297430038f,0.99988234043121337891f, +0.01533920597285032272f,0.99985766410827636719f,0.01687298715114593506f, +0.99983060359954833984f,0.01840673014521598816f,0.99980115890502929688f, +0.01994042843580245972f,0.99976938962936401367f,0.02147408016026020050f, +0.99973529577255249023f,0.02300768159329891205f,0.99969881772994995117f, +0.02454122900962829590f,0.99966001510620117188f,0.02607471868395805359f, +0.99961882829666137695f,0.02760814502835273743f,0.99957531690597534180f, +0.02914150804281234741f,0.99952942132949829102f,0.03067480400204658508f, +0.99948120117187500000f,0.03220802545547485352f,0.99943059682846069336f, +0.03374117240309715271f,0.99937766790390014648f,0.03527423739433288574f, +0.99932235479354858398f,0.03680722415447235107f,0.99926477670669555664f, +0.03834012150764465332f,0.99920475482940673828f,0.03987292572855949402f, +0.99914240837097167969f,0.04140564054250717163f,0.99907773733139038086f, +0.04293825849890708923f,0.99901068210601806641f,0.04447077214717864990f, +0.99894130229949951172f,0.04600318148732185364f,0.99886953830718994141f, +0.04753548279404640198f,0.99879544973373413086f,0.04906767606735229492f, +0.99871903657913208008f,0.05059975013136863708f,0.99864023923873901367f, +0.05213170498609542847f,0.99855905771255493164f,0.05366353690624237061f, +0.99847555160522460938f,0.05519524589180946350f,0.99838972091674804688f, +0.05672682076692581177f,0.99830156564712524414f,0.05825826525688171387f, +0.99821102619171142578f,0.05978957191109657288f,0.99811810255050659180f, +0.06132073700428009033f,0.99802285432815551758f,0.06285175681114196777f, +0.99792528152465820312f,0.06438262760639190674f,0.99782532453536987305f, +0.06591334939002990723f,0.99772304296493530273f,0.06744392216205596924f, +0.99761843681335449219f,0.06897433102130889893f,0.99751144647598266602f, +0.07050457596778869629f,0.99740213155746459961f,0.07203464955091476440f, +0.99729043245315551758f,0.07356456667184829712f,0.99717640876770019531f, +0.07509429752826690674f,0.99706006050109863281f,0.07662386447191238403f, +0.99694132804870605469f,0.07815324515104293823f,0.99682027101516723633f, +0.07968243956565856934f,0.99669688940048217773f,0.08121144771575927734f, +0.99657112360000610352f,0.08274026215076446533f,0.99644303321838378906f, +0.08426889032125473022f,0.99631261825561523438f,0.08579730987548828125f, +0.99617981910705566406f,0.08732553571462631226f,0.99604469537734985352f, +0.08885355293750762939f,0.99590724706649780273f,0.09038136154413223267f, +0.99576741456985473633f,0.09190895408391952515f,0.99562525749206542969f, +0.09343633800745010376f,0.99548077583312988281f,0.09496349841356277466f, +0.99533390998840332031f,0.09649042785167694092f,0.99518471956253051758f, +0.09801714122295379639f,0.99503320455551147461f,0.09954361617565155029f, +0.99487930536270141602f,0.10106986016035079956f,0.99472314119338989258f, +0.10259586572647094727f,0.99456459283828735352f,0.10412163287401199341f, +0.99440366029739379883f,0.10564715415239334106f,0.99424046277999877930f, +0.10717242211103439331f,0.99407488107681274414f,0.10869744420051574707f, +0.99390697479248046875f,0.11022220551967620850f,0.99373674392700195312f, +0.11174671351909637451f,0.99356412887573242188f,0.11327095329761505127f, +0.99338918924331665039f,0.11479492485523223877f,0.99321192502975463867f, +0.11631862819194793701f,0.99303233623504638672f,0.11784206330776214600f, +0.99285042285919189453f,0.11936521530151367188f,0.99266612529754638672f, +0.12088808417320251465f,0.99247956275939941406f,0.12241067737340927124f, +0.99229061603546142578f,0.12393297255039215088f,0.99209928512573242188f, +0.12545497715473175049f,0.99190568923950195312f,0.12697669863700866699f, +0.99170976877212524414f,0.12849810719490051270f,0.99151146411895751953f, +0.13001921772956848145f,0.99131083488464355469f,0.13154003024101257324f, +0.99110794067382812500f,0.13306052982807159424f,0.99090266227722167969f, +0.13458070158958435059f,0.99069499969482421875f,0.13610057532787322998f, +0.99048507213592529297f,0.13762012124061584473f,0.99027281999588012695f, +0.13913933932781219482f,0.99005818367004394531f,0.14065824449062347412f, +0.98984128236770629883f,0.14217680692672729492f,0.98962199687957763672f, +0.14369502663612365723f,0.98940044641494750977f,0.14521291851997375488f, +0.98917651176452636719f,0.14673046767711639404f,0.98895025253295898438f, +0.14824767410755157471f,0.98872166872024536133f,0.14976453781127929688f, +0.98849081993103027344f,0.15128104388713836670f,0.98825758695602416992f, +0.15279719233512878418f,0.98802202939987182617f,0.15431296825408935547f, +0.98778414726257324219f,0.15582840144634246826f,0.98754394054412841797f, +0.15734346210956573486f,0.98730140924453735352f,0.15885815024375915527f, +0.98705655336380004883f,0.16037245094776153564f,0.98680937290191650391f, +0.16188639402389526367f,0.98655992746353149414f,0.16339994966983795166f, +0.98630809783935546875f,0.16491311788558959961f,0.98605394363403320312f, +0.16642589867115020752f,0.98579752445220947266f,0.16793829202651977539f, +0.98553872108459472656f,0.16945029795169830322f,0.98527765274047851562f, +0.17096188664436340332f,0.98501425981521606445f,0.17247308790683746338f, +0.98474848270416259766f,0.17398387193679809570f,0.98448044061660766602f, +0.17549425363540649414f,0.98421007394790649414f,0.17700421810150146484f, +0.98393744230270385742f,0.17851376533508300781f,0.98366242647171020508f, +0.18002289533615112305f,0.98338508605957031250f,0.18153160810470581055f, +0.98310548067092895508f,0.18303988873958587646f,0.98282355070114135742f, +0.18454773724079132080f,0.98253929615020751953f,0.18605515360832214355f, +0.98225271701812744141f,0.18756212294101715088f,0.98196387290954589844f, +0.18906866014003753662f,0.98167270421981811523f,0.19057475030422210693f, +0.98137921094894409180f,0.19208039343357086182f,0.98108339309692382812f, +0.19358558952808380127f,0.98078525066375732422f,0.19509032368659973145f, +0.98048484325408935547f,0.19659459590911865234f,0.98018211126327514648f, +0.19809840619564056396f,0.97987711429595947266f,0.19960175454616546631f, +0.97956979274749755859f,0.20110464096069335938f,0.97926014661788940430f, +0.20260703563690185547f,0.97894817590713500977f,0.20410896837711334229f, +0.97863394021987915039f,0.20561040937900543213f,0.97831737995147705078f, +0.20711137354373931885f,0.97799849510192871094f,0.20861184597015380859f, +0.97767734527587890625f,0.21011184155941009521f,0.97735387086868286133f, +0.21161133050918579102f,0.97702813148498535156f,0.21311031281948089600f, +0.97670006752014160156f,0.21460881829261779785f,0.97636973857879638672f, +0.21610680222511291504f,0.97603708505630493164f,0.21760427951812744141f, +0.97570210695266723633f,0.21910123527050018311f,0.97536486387252807617f, +0.22059768438339233398f,0.97502535581588745117f,0.22209362685680389404f, +0.97468352317810058594f,0.22358903288841247559f,0.97433936595916748047f, +0.22508391737937927246f,0.97399294376373291016f,0.22657826542854309082f, +0.97364425659179687500f,0.22807207703590393066f,0.97329324483871459961f, +0.22956536710262298584f,0.97293996810913085938f,0.23105810582637786865f, +0.97258436679840087891f,0.23255030810832977295f,0.97222650051116943359f, +0.23404195904731750488f,0.97186630964279174805f,0.23553305864334106445f, +0.97150391340255737305f,0.23702360689640045166f,0.97113913297653198242f, +0.23851358890533447266f,0.97077214717864990234f,0.24000301957130432129f, +0.97040283679962158203f,0.24149188399314880371f,0.97003126144409179688f, +0.24298018217086791992f,0.96965736150741577148f,0.24446789920330047607f, +0.96928125619888305664f,0.24595504999160766602f,0.96890282630920410156f, +0.24744161963462829590f,0.96852207183837890625f,0.24892760813236236572f, +0.96813911199569702148f,0.25041300058364868164f,0.96775382757186889648f, +0.25189781188964843750f,0.96736627817153930664f,0.25338202714920043945f, +0.96697646379470825195f,0.25486564636230468750f,0.96658438444137573242f, +0.25634866952896118164f,0.96618998050689697266f,0.25783109664916992188f, +0.96579337120056152344f,0.25931292772293090820f,0.96539443731307983398f, +0.26079410314559936523f,0.96499323844909667969f,0.26227471232414245605f, +0.96458977460861206055f,0.26375466585159301758f,0.96418404579162597656f, +0.26523402333259582520f,0.96377605199813842773f,0.26671275496482849121f, +0.96336579322814941406f,0.26819086074829101562f,0.96295326948165893555f, +0.26966831088066101074f,0.96253848075866699219f,0.27114516496658325195f, +0.96212142705917358398f,0.27262136340141296387f,0.96170204877853393555f, +0.27409690618515014648f,0.96128046512603759766f,0.27557182312011718750f, +0.96085661649703979492f,0.27704608440399169922f,0.96043050289154052734f, +0.27851969003677368164f,0.96000212430953979492f,0.27999264001846313477f, +0.95957154035568237305f,0.28146493434906005859f,0.95913863182067871094f, +0.28293657302856445312f,0.95870345830917358398f,0.28440752625465393066f, +0.95826607942581176758f,0.28587782382965087891f,0.95782643556594848633f, +0.28734746575355529785f,0.95738452672958374023f,0.28881642222404479980f, +0.95694035291671752930f,0.29028466343879699707f,0.95649391412734985352f, +0.29175224900245666504f,0.95604526996612548828f,0.29321914911270141602f, +0.95559436082839965820f,0.29468536376953125000f,0.95514118671417236328f, +0.29615089297294616699f,0.95468574762344360352f,0.29761570692062377930f, +0.95422810316085815430f,0.29907983541488647461f,0.95376819372177124023f, +0.30054324865341186523f,0.95330601930618286133f,0.30200594663619995117f, +0.95284163951873779297f,0.30346795916557312012f,0.95237499475479125977f, +0.30492922663688659668f,0.95190614461898803711f,0.30638980865478515625f, +0.95143502950668334961f,0.30784964561462402344f,0.95096164941787719727f, +0.30930876731872558594f,0.95048606395721435547f,0.31076714396476745605f, +0.95000827312469482422f,0.31222480535507202148f,0.94952815771102905273f, +0.31368175148963928223f,0.94904589653015136719f,0.31513792276382446289f, +0.94856137037277221680f,0.31659337878227233887f,0.94807457923889160156f, +0.31804808974266052246f,0.94758558273315429688f,0.31950202584266662598f, +0.94709438085556030273f,0.32095524668693542480f,0.94660091400146484375f, +0.32240769267082214355f,0.94610524177551269531f,0.32385936379432678223f, +0.94560730457305908203f,0.32531028985977172852f,0.94510722160339355469f, +0.32676044106483459473f,0.94460481405258178711f,0.32820984721183776855f, +0.94410026073455810547f,0.32965844869613647461f,0.94359344244003295898f, +0.33110630512237548828f,0.94308441877365112305f,0.33255335688591003418f, +0.94257318973541259766f,0.33399966359138488770f,0.94205975532531738281f, +0.33544513583183288574f,0.94154405593872070312f,0.33688986301422119141f, +0.94102615118026733398f,0.33833375573158264160f,0.94050604104995727539f, +0.33977687358856201172f,0.93998372554779052734f,0.34121921658515930176f, +0.93945920467376708984f,0.34266072511672973633f,0.93893247842788696289f, +0.34410142898559570312f,0.93840354681015014648f,0.34554132819175720215f, +0.93787235021591186523f,0.34698042273521423340f,0.93733900785446166992f, +0.34841868281364440918f,0.93680346012115478516f,0.34985613822937011719f, +0.93626564741134643555f,0.35129275918006896973f,0.93572568893432617188f, +0.35272854566574096680f,0.93518352508544921875f,0.35416352748870849609f, +0.93463915586471557617f,0.35559767484664916992f,0.93409252166748046875f, +0.35703095793724060059f,0.93354380130767822266f,0.35846340656280517578f, +0.93299281597137451172f,0.35989505052566528320f,0.93243962526321411133f, +0.36132580041885375977f,0.93188428878784179688f,0.36275571584701538086f, +0.93132668733596801758f,0.36418479681015014648f,0.93076694011688232422f, +0.36561298370361328125f,0.93020504713058471680f,0.36704033613204956055f, +0.92964088916778564453f,0.36846682429313659668f,0.92907458543777465820f, +0.36989244818687438965f,0.92850607633590698242f,0.37131720781326293945f, +0.92793542146682739258f,0.37274107336997985840f,0.92736250162124633789f, +0.37416407465934753418f,0.92678749561309814453f,0.37558618187904357910f, +0.92621022462844848633f,0.37700742483139038086f,0.92563080787658691406f, +0.37842774391174316406f,0.92504924535751342773f,0.37984719872474670410f, +0.92446547746658325195f,0.38126575946807861328f,0.92387950420379638672f, +0.38268342614173889160f,0.92329144477844238281f,0.38410019874572753906f, +0.92270112037658691406f,0.38551604747772216797f,0.92210865020751953125f, +0.38693100214004516602f,0.92151403427124023438f,0.38834503293037414551f, +0.92091721296310424805f,0.38975816965103149414f,0.92031830549240112305f, +0.39117038249969482422f,0.91971713304519653320f,0.39258167147636413574f, +0.91911387443542480469f,0.39399203658103942871f,0.91850841045379638672f, +0.39540147781372070312f,0.91790080070495605469f,0.39680999517440795898f, +0.91729098558425903320f,0.39821755886077880859f,0.91667908430099487305f, +0.39962419867515563965f,0.91606497764587402344f,0.40102988481521606445f, +0.91544872522354125977f,0.40243464708328247070f,0.91483032703399658203f, +0.40383845567703247070f,0.91420978307723999023f,0.40524131059646606445f, +0.91358703374862670898f,0.40664321184158325195f,0.91296219825744628906f, +0.40804415941238403320f,0.91233515739440917969f,0.40944415330886840820f, +0.91170603036880493164f,0.41084316372871398926f,0.91107475757598876953f, +0.41224122047424316406f,0.91044127941131591797f,0.41363832354545593262f, +0.90980571508407592773f,0.41503441333770751953f,0.90916800498962402344f, +0.41642954945564270020f,0.90852808952331542969f,0.41782370209693908691f, +0.90788608789443969727f,0.41921690106391906738f,0.90724200010299682617f, +0.42060908675193786621f,0.90659570693969726562f,0.42200025916099548340f, +0.90594726800918579102f,0.42339047789573669434f,0.90529674291610717773f, +0.42477968335151672363f,0.90464407205581665039f,0.42616787552833557129f, +0.90398931503295898438f,0.42755508422851562500f,0.90333235263824462891f, +0.42894127964973449707f,0.90267330408096313477f,0.43032649159431457520f, +0.90201216936111450195f,0.43171066045761108398f,0.90134882926940917969f, +0.43309381604194641113f,0.90068340301513671875f,0.43447595834732055664f, +0.90001589059829711914f,0.43585708737373352051f,0.89934623241424560547f, +0.43723717331886291504f,0.89867448806762695312f,0.43861624598503112793f, +0.89800059795379638672f,0.43999427556991577148f,0.89732456207275390625f, +0.44137126207351684570f,0.89664649963378906250f,0.44274723529815673828f, +0.89596623182296752930f,0.44412213563919067383f,0.89528393745422363281f, +0.44549602270126342773f,0.89459949731826782227f,0.44686883687973022461f, +0.89391297101974487305f,0.44824060797691345215f,0.89322429895401000977f, +0.44961133599281311035f,0.89253354072570800781f,0.45098099112510681152f, +0.89184069633483886719f,0.45234957337379455566f,0.89114576578140258789f, +0.45371711254119873047f,0.89044874906539916992f,0.45508357882499694824f, +0.88974958658218383789f,0.45644897222518920898f,0.88904833793640136719f, +0.45781329274177551270f,0.88834506273269653320f,0.45917654037475585938f, +0.88763964176177978516f,0.46053871512413024902f,0.88693213462829589844f, +0.46189978718757629395f,0.88622254133224487305f,0.46325978636741638184f, +0.88551086187362670898f,0.46461868286132812500f,0.88479709625244140625f, +0.46597650647163391113f,0.88408124446868896484f,0.46733319759368896484f, +0.88336336612701416016f,0.46868881583213806152f,0.88264334201812744141f, +0.47004333138465881348f,0.88192129135131835938f,0.47139674425125122070f, +0.88119709491729736328f,0.47274902462959289551f,0.88047087192535400391f, +0.47410020232200622559f,0.87974262237548828125f,0.47545027732849121094f, +0.87901222705841064453f,0.47679921984672546387f,0.87827980518341064453f, +0.47814705967903137207f,0.87754529714584350586f,0.47949376702308654785f, +0.87680870294570922852f,0.48083934187889099121f,0.87607008218765258789f, +0.48218378424644470215f,0.87532937526702880859f,0.48352706432342529297f, +0.87458664178848266602f,0.48486924171447753906f,0.87384182214736938477f, +0.48621028661727905273f,0.87309497594833374023f,0.48755016922950744629f, +0.87234604358673095703f,0.48888888955116271973f,0.87159508466720581055f, +0.49022647738456726074f,0.87084203958511352539f,0.49156290292739868164f, +0.87008696794509887695f,0.49289819598197937012f,0.86932986974716186523f, +0.49423229694366455078f,0.86857068538665771484f,0.49556526541709899902f, +0.86780947446823120117f,0.49689704179763793945f,0.86704623699188232422f, +0.49822765588760375977f,0.86628097295761108398f,0.49955710768699645996f, +0.86551362276077270508f,0.50088536739349365234f,0.86474424600601196289f, +0.50221246480941772461f,0.86397284269332885742f,0.50353837013244628906f, +0.86319941282272338867f,0.50486308336257934570f,0.86242395639419555664f, +0.50618666410446166992f,0.86164647340774536133f,0.50750899314880371094f, +0.86086696386337280273f,0.50883013010025024414f,0.86008536815643310547f, +0.51015007495880126953f,0.85930180549621582031f,0.51146882772445678711f, +0.85851621627807617188f,0.51278638839721679688f,0.85772860050201416016f, +0.51410275697708129883f,0.85693895816802978516f,0.51541787385940551758f, +0.85614734888076782227f,0.51673179864883422852f,0.85535365343093872070f, +0.51804453134536743164f,0.85455799102783203125f,0.51935601234436035156f, +0.85376030206680297852f,0.52066624164581298828f,0.85296058654785156250f, +0.52197527885437011719f,0.85215890407562255859f,0.52328312397003173828f, +0.85135519504547119141f,0.52458965778350830078f,0.85054945945739746094f, +0.52589499950408935547f,0.84974175691604614258f,0.52719914913177490234f, +0.84893202781677246094f,0.52850198745727539062f,0.84812033176422119141f, +0.52980363368988037109f,0.84730660915374755859f,0.53110402822494506836f, +0.84649091958999633789f,0.53240311145782470703f,0.84567326307296752930f, +0.53370100259780883789f,0.84485357999801635742f,0.53499764204025268555f, +0.84403187036514282227f,0.53629297018051147461f,0.84320825338363647461f, +0.53758704662322998047f,0.84238260984420776367f,0.53887993097305297852f, +0.84155499935150146484f,0.54017144441604614258f,0.84072536230087280273f, +0.54146176576614379883f,0.83989381790161132812f,0.54275077581405639648f, +0.83906024694442749023f,0.54403853416442871094f,0.83822470903396606445f, +0.54532498121261596680f,0.83738720417022705078f,0.54661017656326293945f, +0.83654773235321044922f,0.54789406061172485352f,0.83570629358291625977f, +0.54917663335800170898f,0.83486288785934448242f,0.55045795440673828125f, +0.83401751518249511719f,0.55173796415328979492f,0.83317017555236816406f, +0.55301672220230102539f,0.83232086896896362305f,0.55429410934448242188f, +0.83146959543228149414f,0.55557024478912353516f,0.83061641454696655273f, +0.55684500932693481445f,0.82976120710372924805f,0.55811852216720581055f, +0.82890409231185913086f,0.55939072370529174805f,0.82804507017135620117f, +0.56066155433654785156f,0.82718402147293090820f,0.56193113327026367188f, +0.82632106542587280273f,0.56319934129714965820f,0.82545614242553710938f, +0.56446623802185058594f,0.82458931207656860352f,0.56573182344436645508f, +0.82372051477432250977f,0.56699603796005249023f,0.82284981012344360352f, +0.56825894117355346680f,0.82197713851928710938f,0.56952053308486938477f, +0.82110249996185302734f,0.57078075408935546875f,0.82022595405578613281f, +0.57203960418701171875f,0.81934750080108642578f,0.57329714298248291016f, +0.81846714019775390625f,0.57455337047576904297f,0.81758481264114379883f, +0.57580816745758056641f,0.81670057773590087891f,0.57706165313720703125f, +0.81581443548202514648f,0.57831376791000366211f,0.81492632627487182617f, +0.57956457138061523438f,0.81403630971908569336f,0.58081394433975219727f, +0.81314438581466674805f,0.58206200599670410156f,0.81225061416625976562f, +0.58330863714218139648f,0.81135487556457519531f,0.58455395698547363281f, +0.81045717000961303711f,0.58579784631729125977f,0.80955761671066284180f, +0.58704036474227905273f,0.80865615606307983398f,0.58828157186508178711f, +0.80775284767150878906f,0.58952128887176513672f,0.80684757232666015625f, +0.59075969457626342773f,0.80594038963317871094f,0.59199666976928710938f, +0.80503135919570922852f,0.59323227405548095703f,0.80412036180496215820f, +0.59446650743484497070f,0.80320751667022705078f,0.59569931030273437500f, +0.80229282379150390625f,0.59693068265914916992f,0.80137616395950317383f, +0.59816068410873413086f,0.80045765638351440430f,0.59938931465148925781f, +0.79953724145889282227f,0.60061645507812500000f,0.79861497879028320312f, +0.60184222459793090820f,0.79769086837768554688f,0.60306662321090698242f, +0.79676479101181030273f,0.60428953170776367188f,0.79583692550659179688f, +0.60551106929779052734f,0.79490715265274047852f,0.60673111677169799805f, +0.79397547245025634766f,0.60794979333877563477f,0.79304194450378417969f, +0.60916703939437866211f,0.79210656881332397461f,0.61038279533386230469f, +0.79116934537887573242f,0.61159718036651611328f,0.79023021459579467773f, +0.61281007528305053711f,0.78928923606872558594f,0.61402153968811035156f, +0.78834640979766845703f,0.61523157358169555664f,0.78740173578262329102f, +0.61644017696380615234f,0.78645521402359008789f,0.61764729022979736328f, +0.78550684452056884766f,0.61885297298431396484f,0.78455656766891479492f, +0.62005722522735595703f,0.78360450267791748047f,0.62125998735427856445f, +0.78265058994293212891f,0.62246125936508178711f,0.78169482946395874023f, +0.62366110086441040039f,0.78073722124099731445f,0.62485951185226440430f, +0.77977776527404785156f,0.62605637311935424805f,0.77881652116775512695f, +0.62725180387496948242f,0.77785342931747436523f,0.62844574451446533203f, +0.77688848972320556641f,0.62963825464248657227f,0.77592170238494873047f, +0.63082921504974365234f,0.77495312690734863281f,0.63201874494552612305f, +0.77398270368576049805f,0.63320678472518920898f,0.77301043272018432617f, +0.63439327478408813477f,0.77203637361526489258f,0.63557833433151245117f, +0.77106052637100219727f,0.63676184415817260742f,0.77008283138275146484f, +0.63794392347335815430f,0.76910334825515747070f,0.63912445306777954102f, +0.76812201738357543945f,0.64030349254608154297f,0.76713889837265014648f, +0.64148104190826416016f,0.76615399122238159180f,0.64265704154968261719f, +0.76516723632812500000f,0.64383155107498168945f,0.76417875289916992188f, +0.64500451087951660156f,0.76318842172622680664f,0.64617604017257690430f, +0.76219630241394042969f,0.64734596014022827148f,0.76120239496231079102f, +0.64851438999176025391f,0.76020669937133789062f,0.64968132972717285156f, +0.75920921564102172852f,0.65084666013717651367f,0.75820988416671752930f, +0.65201056003570556641f,0.75720882415771484375f,0.65317285060882568359f, +0.75620597600936889648f,0.65433359146118164062f,0.75520139932632446289f, +0.65549284219741821289f,0.75419497489929199219f,0.65665054321289062500f, +0.75318682193756103516f,0.65780669450759887695f,0.75217682123184204102f, +0.65896129608154296875f,0.75116515159606933594f,0.66011434793472290039f, +0.75015163421630859375f,0.66126585006713867188f,0.74913638830184936523f, +0.66241580247879028320f,0.74811935424804687500f,0.66356414556503295898f, +0.74710059165954589844f,0.66471099853515625000f,0.74608010053634643555f, +0.66585624217987060547f,0.74505776166915893555f,0.66699993610382080078f, +0.74403375387191772461f,0.66814202070236206055f,0.74300795793533325195f, +0.66928261518478393555f,0.74198043346405029297f,0.67042154073715209961f, +0.74095112085342407227f,0.67155897617340087891f,0.73992007970809936523f, +0.67269474267959594727f,0.73888731002807617188f,0.67382901906967163086f, +0.73785281181335449219f,0.67496162652969360352f,0.73681658506393432617f, +0.67609268426895141602f,0.73577857017517089844f,0.67722219228744506836f, +0.73473888635635375977f,0.67835003137588500977f,0.73369741439819335938f, +0.67947632074356079102f,0.73265427350997924805f,0.68060100078582763672f, +0.73160940408706665039f,0.68172407150268554688f,0.73056274652481079102f, +0.68284553289413452148f,0.72951442003250122070f,0.68396538496017456055f, +0.72846436500549316406f,0.68508368730545043945f,0.72741264104843139648f, +0.68620032072067260742f,0.72635912895202636719f,0.68731534481048583984f, +0.72530394792556762695f,0.68842875957489013672f,0.72424709796905517578f, +0.68954056501388549805f,0.72318845987319946289f,0.69065070152282714844f, +0.72212821245193481445f,0.69175922870635986328f,0.72106617689132690430f, +0.69286614656448364258f,0.72000253200531005859f,0.69397145509719848633f, +0.71893709897994995117f,0.69507509469985961914f,0.71787005662918090820f, +0.69617712497711181641f,0.71680128574371337891f,0.69727748632431030273f, +0.71573084592819213867f,0.69837623834609985352f,0.71465867757797241211f, +0.69947332143783569336f,0.71358484029769897461f,0.70056879520416259766f, +0.71250939369201660156f,0.70166260004043579102f,0.71143221855163574219f, +0.70275473594665527344f,0.71035337448120117188f,0.70384526252746582031f, +0.70927280187606811523f,0.70493406057357788086f,0.70819061994552612305f, +0.70602124929428100586f,0.70710676908493041992f,0.70710676908493041992f, +0.70602124929428100586f,0.70819061994552612305f,0.70493406057357788086f, +0.70927280187606811523f,0.70384526252746582031f,0.71035337448120117188f, +0.70275473594665527344f,0.71143221855163574219f,0.70166260004043579102f, +0.71250939369201660156f,0.70056879520416259766f,0.71358484029769897461f, +0.69947332143783569336f,0.71465867757797241211f,0.69837623834609985352f, +0.71573084592819213867f,0.69727748632431030273f,0.71680128574371337891f, +0.69617712497711181641f,0.71787005662918090820f,0.69507509469985961914f, +0.71893709897994995117f,0.69397145509719848633f,0.72000253200531005859f, +0.69286614656448364258f,0.72106617689132690430f,0.69175922870635986328f, +0.72212821245193481445f,0.69065070152282714844f,0.72318845987319946289f, +0.68954056501388549805f,0.72424709796905517578f,0.68842875957489013672f, +0.72530394792556762695f,0.68731534481048583984f,0.72635912895202636719f, +0.68620032072067260742f,0.72741264104843139648f,0.68508368730545043945f, +0.72846436500549316406f,0.68396538496017456055f,0.72951442003250122070f, +0.68284553289413452148f,0.73056274652481079102f,0.68172407150268554688f, +0.73160940408706665039f,0.68060100078582763672f,0.73265427350997924805f, +0.67947632074356079102f,0.73369741439819335938f,0.67835003137588500977f, +0.73473888635635375977f,0.67722219228744506836f,0.73577857017517089844f, +0.67609268426895141602f,0.73681658506393432617f,0.67496162652969360352f, +0.73785281181335449219f,0.67382901906967163086f,0.73888731002807617188f, +0.67269474267959594727f,0.73992007970809936523f,0.67155897617340087891f, +0.74095112085342407227f,0.67042154073715209961f,0.74198043346405029297f, +0.66928261518478393555f,0.74300795793533325195f,0.66814202070236206055f, +0.74403375387191772461f,0.66699993610382080078f,0.74505776166915893555f, +0.66585624217987060547f,0.74608010053634643555f,0.66471099853515625000f, +0.74710059165954589844f,0.66356414556503295898f,0.74811935424804687500f, +0.66241580247879028320f,0.74913638830184936523f,0.66126585006713867188f, +0.75015163421630859375f,0.66011434793472290039f,0.75116515159606933594f, +0.65896129608154296875f,0.75217682123184204102f,0.65780669450759887695f, +0.75318682193756103516f,0.65665054321289062500f,0.75419497489929199219f, +0.65549284219741821289f,0.75520139932632446289f,0.65433359146118164062f, +0.75620597600936889648f,0.65317285060882568359f,0.75720882415771484375f, +0.65201056003570556641f,0.75820988416671752930f,0.65084666013717651367f, +0.75920921564102172852f,0.64968132972717285156f,0.76020669937133789062f, +0.64851438999176025391f,0.76120239496231079102f,0.64734596014022827148f, +0.76219630241394042969f,0.64617604017257690430f,0.76318842172622680664f, +0.64500451087951660156f,0.76417875289916992188f,0.64383155107498168945f, +0.76516723632812500000f,0.64265704154968261719f,0.76615399122238159180f, +0.64148104190826416016f,0.76713889837265014648f,0.64030349254608154297f, +0.76812201738357543945f,0.63912445306777954102f,0.76910334825515747070f, +0.63794392347335815430f,0.77008283138275146484f,0.63676184415817260742f, +0.77106052637100219727f,0.63557833433151245117f,0.77203637361526489258f, +0.63439327478408813477f,0.77301043272018432617f,0.63320678472518920898f, +0.77398270368576049805f,0.63201874494552612305f,0.77495312690734863281f, +0.63082921504974365234f,0.77592170238494873047f,0.62963825464248657227f, +0.77688848972320556641f,0.62844574451446533203f,0.77785342931747436523f, +0.62725180387496948242f,0.77881652116775512695f,0.62605637311935424805f, +0.77977776527404785156f,0.62485951185226440430f,0.78073722124099731445f, +0.62366110086441040039f,0.78169482946395874023f,0.62246125936508178711f, +0.78265058994293212891f,0.62125998735427856445f,0.78360450267791748047f, +0.62005722522735595703f,0.78455656766891479492f,0.61885297298431396484f, +0.78550684452056884766f,0.61764729022979736328f,0.78645521402359008789f, +0.61644017696380615234f,0.78740173578262329102f,0.61523157358169555664f, +0.78834640979766845703f,0.61402153968811035156f,0.78928923606872558594f, +0.61281007528305053711f,0.79023021459579467773f,0.61159718036651611328f, +0.79116934537887573242f,0.61038279533386230469f,0.79210656881332397461f, +0.60916703939437866211f,0.79304194450378417969f,0.60794979333877563477f, +0.79397547245025634766f,0.60673111677169799805f,0.79490715265274047852f, +0.60551106929779052734f,0.79583692550659179688f,0.60428953170776367188f, +0.79676479101181030273f,0.60306662321090698242f,0.79769086837768554688f, +0.60184222459793090820f,0.79861497879028320312f,0.60061645507812500000f, +0.79953724145889282227f,0.59938931465148925781f,0.80045765638351440430f, +0.59816068410873413086f,0.80137616395950317383f,0.59693068265914916992f, +0.80229282379150390625f,0.59569931030273437500f,0.80320751667022705078f, +0.59446650743484497070f,0.80412036180496215820f,0.59323227405548095703f, +0.80503135919570922852f,0.59199666976928710938f,0.80594038963317871094f, +0.59075969457626342773f,0.80684757232666015625f,0.58952128887176513672f, +0.80775284767150878906f,0.58828157186508178711f,0.80865615606307983398f, +0.58704036474227905273f,0.80955761671066284180f,0.58579784631729125977f, +0.81045717000961303711f,0.58455395698547363281f,0.81135487556457519531f, +0.58330863714218139648f,0.81225061416625976562f,0.58206200599670410156f, +0.81314438581466674805f,0.58081394433975219727f,0.81403630971908569336f, +0.57956457138061523438f,0.81492632627487182617f,0.57831376791000366211f, +0.81581443548202514648f,0.57706165313720703125f,0.81670057773590087891f, +0.57580816745758056641f,0.81758481264114379883f,0.57455337047576904297f, +0.81846714019775390625f,0.57329714298248291016f,0.81934750080108642578f, +0.57203960418701171875f,0.82022595405578613281f,0.57078075408935546875f, +0.82110249996185302734f,0.56952053308486938477f,0.82197713851928710938f, +0.56825894117355346680f,0.82284981012344360352f,0.56699603796005249023f, +0.82372051477432250977f,0.56573182344436645508f,0.82458931207656860352f, +0.56446623802185058594f,0.82545614242553710938f,0.56319934129714965820f, +0.82632106542587280273f,0.56193113327026367188f,0.82718402147293090820f, +0.56066155433654785156f,0.82804507017135620117f,0.55939072370529174805f, +0.82890409231185913086f,0.55811852216720581055f,0.82976120710372924805f, +0.55684500932693481445f,0.83061641454696655273f,0.55557024478912353516f, +0.83146959543228149414f,0.55429410934448242188f,0.83232086896896362305f, +0.55301672220230102539f,0.83317017555236816406f,0.55173796415328979492f, +0.83401751518249511719f,0.55045795440673828125f,0.83486288785934448242f, +0.54917663335800170898f,0.83570629358291625977f,0.54789406061172485352f, +0.83654773235321044922f,0.54661017656326293945f,0.83738720417022705078f, +0.54532498121261596680f,0.83822470903396606445f,0.54403853416442871094f, +0.83906024694442749023f,0.54275077581405639648f,0.83989381790161132812f, +0.54146176576614379883f,0.84072536230087280273f,0.54017144441604614258f, +0.84155499935150146484f,0.53887993097305297852f,0.84238260984420776367f, +0.53758704662322998047f,0.84320825338363647461f,0.53629297018051147461f, +0.84403187036514282227f,0.53499764204025268555f,0.84485357999801635742f, +0.53370100259780883789f,0.84567326307296752930f,0.53240311145782470703f, +0.84649091958999633789f,0.53110402822494506836f,0.84730660915374755859f, +0.52980363368988037109f,0.84812033176422119141f,0.52850198745727539062f, +0.84893202781677246094f,0.52719914913177490234f,0.84974175691604614258f, +0.52589499950408935547f,0.85054945945739746094f,0.52458965778350830078f, +0.85135519504547119141f,0.52328312397003173828f,0.85215890407562255859f, +0.52197527885437011719f,0.85296058654785156250f,0.52066624164581298828f, +0.85376030206680297852f,0.51935601234436035156f,0.85455799102783203125f, +0.51804453134536743164f,0.85535365343093872070f,0.51673179864883422852f, +0.85614734888076782227f,0.51541787385940551758f,0.85693895816802978516f, +0.51410275697708129883f,0.85772860050201416016f,0.51278638839721679688f, +0.85851621627807617188f,0.51146882772445678711f,0.85930180549621582031f, +0.51015007495880126953f,0.86008536815643310547f,0.50883013010025024414f, +0.86086696386337280273f,0.50750899314880371094f,0.86164647340774536133f, +0.50618666410446166992f,0.86242395639419555664f,0.50486308336257934570f, +0.86319941282272338867f,0.50353837013244628906f,0.86397284269332885742f, +0.50221246480941772461f,0.86474424600601196289f,0.50088536739349365234f, +0.86551362276077270508f,0.49955710768699645996f,0.86628097295761108398f, +0.49822765588760375977f,0.86704623699188232422f,0.49689704179763793945f, +0.86780947446823120117f,0.49556526541709899902f,0.86857068538665771484f, +0.49423229694366455078f,0.86932986974716186523f,0.49289819598197937012f, +0.87008696794509887695f,0.49156290292739868164f,0.87084203958511352539f, +0.49022647738456726074f,0.87159508466720581055f,0.48888888955116271973f, +0.87234604358673095703f,0.48755016922950744629f,0.87309497594833374023f, +0.48621028661727905273f,0.87384182214736938477f,0.48486924171447753906f, +0.87458664178848266602f,0.48352706432342529297f,0.87532937526702880859f, +0.48218378424644470215f,0.87607008218765258789f,0.48083934187889099121f, +0.87680870294570922852f,0.47949376702308654785f,0.87754529714584350586f, +0.47814705967903137207f,0.87827980518341064453f,0.47679921984672546387f, +0.87901222705841064453f,0.47545027732849121094f,0.87974262237548828125f, +0.47410020232200622559f,0.88047087192535400391f,0.47274902462959289551f, +0.88119709491729736328f,0.47139674425125122070f,0.88192129135131835938f, +0.47004333138465881348f,0.88264334201812744141f,0.46868881583213806152f, +0.88336336612701416016f,0.46733319759368896484f,0.88408124446868896484f, +0.46597650647163391113f,0.88479709625244140625f,0.46461868286132812500f, +0.88551086187362670898f,0.46325978636741638184f,0.88622254133224487305f, +0.46189978718757629395f,0.88693213462829589844f,0.46053871512413024902f, +0.88763964176177978516f,0.45917654037475585938f,0.88834506273269653320f, +0.45781329274177551270f,0.88904833793640136719f,0.45644897222518920898f, +0.88974958658218383789f,0.45508357882499694824f,0.89044874906539916992f, +0.45371711254119873047f,0.89114576578140258789f,0.45234957337379455566f, +0.89184069633483886719f,0.45098099112510681152f,0.89253354072570800781f, +0.44961133599281311035f,0.89322429895401000977f,0.44824060797691345215f, +0.89391297101974487305f,0.44686883687973022461f,0.89459949731826782227f, +0.44549602270126342773f,0.89528393745422363281f,0.44412213563919067383f, +0.89596623182296752930f,0.44274723529815673828f,0.89664649963378906250f, +0.44137126207351684570f,0.89732456207275390625f,0.43999427556991577148f, +0.89800059795379638672f,0.43861624598503112793f,0.89867448806762695312f, +0.43723717331886291504f,0.89934623241424560547f,0.43585708737373352051f, +0.90001589059829711914f,0.43447595834732055664f,0.90068340301513671875f, +0.43309381604194641113f,0.90134882926940917969f,0.43171066045761108398f, +0.90201216936111450195f,0.43032649159431457520f,0.90267330408096313477f, +0.42894127964973449707f,0.90333235263824462891f,0.42755508422851562500f, +0.90398931503295898438f,0.42616787552833557129f,0.90464407205581665039f, +0.42477968335151672363f,0.90529674291610717773f,0.42339047789573669434f, +0.90594726800918579102f,0.42200025916099548340f,0.90659570693969726562f, +0.42060908675193786621f,0.90724200010299682617f,0.41921690106391906738f, +0.90788608789443969727f,0.41782370209693908691f,0.90852808952331542969f, +0.41642954945564270020f,0.90916800498962402344f,0.41503441333770751953f, +0.90980571508407592773f,0.41363832354545593262f,0.91044127941131591797f, +0.41224122047424316406f,0.91107475757598876953f,0.41084316372871398926f, +0.91170603036880493164f,0.40944415330886840820f,0.91233515739440917969f, +0.40804415941238403320f,0.91296219825744628906f,0.40664321184158325195f, +0.91358703374862670898f,0.40524131059646606445f,0.91420978307723999023f, +0.40383845567703247070f,0.91483032703399658203f,0.40243464708328247070f, +0.91544872522354125977f,0.40102988481521606445f,0.91606497764587402344f, +0.39962419867515563965f,0.91667908430099487305f,0.39821755886077880859f, +0.91729098558425903320f,0.39680999517440795898f,0.91790080070495605469f, +0.39540147781372070312f,0.91850841045379638672f,0.39399203658103942871f, +0.91911387443542480469f,0.39258167147636413574f,0.91971713304519653320f, +0.39117038249969482422f,0.92031830549240112305f,0.38975816965103149414f, +0.92091721296310424805f,0.38834503293037414551f,0.92151403427124023438f, +0.38693100214004516602f,0.92210865020751953125f,0.38551604747772216797f, +0.92270112037658691406f,0.38410019874572753906f,0.92329144477844238281f, +0.38268342614173889160f,0.92387950420379638672f,0.38126575946807861328f, +0.92446547746658325195f,0.37984719872474670410f,0.92504924535751342773f, +0.37842774391174316406f,0.92563080787658691406f,0.37700742483139038086f, +0.92621022462844848633f,0.37558618187904357910f,0.92678749561309814453f, +0.37416407465934753418f,0.92736250162124633789f,0.37274107336997985840f, +0.92793542146682739258f,0.37131720781326293945f,0.92850607633590698242f, +0.36989244818687438965f,0.92907458543777465820f,0.36846682429313659668f, +0.92964088916778564453f,0.36704033613204956055f,0.93020504713058471680f, +0.36561298370361328125f,0.93076694011688232422f,0.36418479681015014648f, +0.93132668733596801758f,0.36275571584701538086f,0.93188428878784179688f, +0.36132580041885375977f,0.93243962526321411133f,0.35989505052566528320f, +0.93299281597137451172f,0.35846340656280517578f,0.93354380130767822266f, +0.35703095793724060059f,0.93409252166748046875f,0.35559767484664916992f, +0.93463915586471557617f,0.35416352748870849609f,0.93518352508544921875f, +0.35272854566574096680f,0.93572568893432617188f,0.35129275918006896973f, +0.93626564741134643555f,0.34985613822937011719f,0.93680346012115478516f, +0.34841868281364440918f,0.93733900785446166992f,0.34698042273521423340f, +0.93787235021591186523f,0.34554132819175720215f,0.93840354681015014648f, +0.34410142898559570312f,0.93893247842788696289f,0.34266072511672973633f, +0.93945920467376708984f,0.34121921658515930176f,0.93998372554779052734f, +0.33977687358856201172f,0.94050604104995727539f,0.33833375573158264160f, +0.94102615118026733398f,0.33688986301422119141f,0.94154405593872070312f, +0.33544513583183288574f,0.94205975532531738281f,0.33399966359138488770f, +0.94257318973541259766f,0.33255335688591003418f,0.94308441877365112305f, +0.33110630512237548828f,0.94359344244003295898f,0.32965844869613647461f, +0.94410026073455810547f,0.32820984721183776855f,0.94460481405258178711f, +0.32676044106483459473f,0.94510722160339355469f,0.32531028985977172852f, +0.94560730457305908203f,0.32385936379432678223f,0.94610524177551269531f, +0.32240769267082214355f,0.94660091400146484375f,0.32095524668693542480f, +0.94709438085556030273f,0.31950202584266662598f,0.94758558273315429688f, +0.31804808974266052246f,0.94807457923889160156f,0.31659337878227233887f, +0.94856137037277221680f,0.31513792276382446289f,0.94904589653015136719f, +0.31368175148963928223f,0.94952815771102905273f,0.31222480535507202148f, +0.95000827312469482422f,0.31076714396476745605f,0.95048606395721435547f, +0.30930876731872558594f,0.95096164941787719727f,0.30784964561462402344f, +0.95143502950668334961f,0.30638980865478515625f,0.95190614461898803711f, +0.30492922663688659668f,0.95237499475479125977f,0.30346795916557312012f, +0.95284163951873779297f,0.30200594663619995117f,0.95330601930618286133f, +0.30054324865341186523f,0.95376819372177124023f,0.29907983541488647461f, +0.95422810316085815430f,0.29761570692062377930f,0.95468574762344360352f, +0.29615089297294616699f,0.95514118671417236328f,0.29468536376953125000f, +0.95559436082839965820f,0.29321914911270141602f,0.95604526996612548828f, +0.29175224900245666504f,0.95649391412734985352f,0.29028466343879699707f, +0.95694035291671752930f,0.28881642222404479980f,0.95738452672958374023f, +0.28734746575355529785f,0.95782643556594848633f,0.28587782382965087891f, +0.95826607942581176758f,0.28440752625465393066f,0.95870345830917358398f, +0.28293657302856445312f,0.95913863182067871094f,0.28146493434906005859f, +0.95957154035568237305f,0.27999264001846313477f,0.96000212430953979492f, +0.27851969003677368164f,0.96043050289154052734f,0.27704608440399169922f, +0.96085661649703979492f,0.27557182312011718750f,0.96128046512603759766f, +0.27409690618515014648f,0.96170204877853393555f,0.27262136340141296387f, +0.96212142705917358398f,0.27114516496658325195f,0.96253848075866699219f, +0.26966831088066101074f,0.96295326948165893555f,0.26819086074829101562f, +0.96336579322814941406f,0.26671275496482849121f,0.96377605199813842773f, +0.26523402333259582520f,0.96418404579162597656f,0.26375466585159301758f, +0.96458977460861206055f,0.26227471232414245605f,0.96499323844909667969f, +0.26079410314559936523f,0.96539443731307983398f,0.25931292772293090820f, +0.96579337120056152344f,0.25783109664916992188f,0.96618998050689697266f, +0.25634866952896118164f,0.96658438444137573242f,0.25486564636230468750f, +0.96697646379470825195f,0.25338202714920043945f,0.96736627817153930664f, +0.25189781188964843750f,0.96775382757186889648f,0.25041300058364868164f, +0.96813911199569702148f,0.24892760813236236572f,0.96852207183837890625f, +0.24744161963462829590f,0.96890282630920410156f,0.24595504999160766602f, +0.96928125619888305664f,0.24446789920330047607f,0.96965736150741577148f, +0.24298018217086791992f,0.97003126144409179688f,0.24149188399314880371f, +0.97040283679962158203f,0.24000301957130432129f,0.97077214717864990234f, +0.23851358890533447266f,0.97113913297653198242f,0.23702360689640045166f, +0.97150391340255737305f,0.23553305864334106445f,0.97186630964279174805f, +0.23404195904731750488f,0.97222650051116943359f,0.23255030810832977295f, +0.97258436679840087891f,0.23105810582637786865f,0.97293996810913085938f, +0.22956536710262298584f,0.97329324483871459961f,0.22807207703590393066f, +0.97364425659179687500f,0.22657826542854309082f,0.97399294376373291016f, +0.22508391737937927246f,0.97433936595916748047f,0.22358903288841247559f, +0.97468352317810058594f,0.22209362685680389404f,0.97502535581588745117f, +0.22059768438339233398f,0.97536486387252807617f,0.21910123527050018311f, +0.97570210695266723633f,0.21760427951812744141f,0.97603708505630493164f, +0.21610680222511291504f,0.97636973857879638672f,0.21460881829261779785f, +0.97670006752014160156f,0.21311031281948089600f,0.97702813148498535156f, +0.21161133050918579102f,0.97735387086868286133f,0.21011184155941009521f, +0.97767734527587890625f,0.20861184597015380859f,0.97799849510192871094f, +0.20711137354373931885f,0.97831737995147705078f,0.20561040937900543213f, +0.97863394021987915039f,0.20410896837711334229f,0.97894817590713500977f, +0.20260703563690185547f,0.97926014661788940430f,0.20110464096069335938f, +0.97956979274749755859f,0.19960175454616546631f,0.97987711429595947266f, +0.19809840619564056396f,0.98018211126327514648f,0.19659459590911865234f, +0.98048484325408935547f,0.19509032368659973145f,0.98078525066375732422f, +0.19358558952808380127f,0.98108339309692382812f,0.19208039343357086182f, +0.98137921094894409180f,0.19057475030422210693f,0.98167270421981811523f, +0.18906866014003753662f,0.98196387290954589844f,0.18756212294101715088f, +0.98225271701812744141f,0.18605515360832214355f,0.98253929615020751953f, +0.18454773724079132080f,0.98282355070114135742f,0.18303988873958587646f, +0.98310548067092895508f,0.18153160810470581055f,0.98338508605957031250f, +0.18002289533615112305f,0.98366242647171020508f,0.17851376533508300781f, +0.98393744230270385742f,0.17700421810150146484f,0.98421007394790649414f, +0.17549425363540649414f,0.98448044061660766602f,0.17398387193679809570f, +0.98474848270416259766f,0.17247308790683746338f,0.98501425981521606445f, +0.17096188664436340332f,0.98527765274047851562f,0.16945029795169830322f, +0.98553872108459472656f,0.16793829202651977539f,0.98579752445220947266f, +0.16642589867115020752f,0.98605394363403320312f,0.16491311788558959961f, +0.98630809783935546875f,0.16339994966983795166f,0.98655992746353149414f, +0.16188639402389526367f,0.98680937290191650391f,0.16037245094776153564f, +0.98705655336380004883f,0.15885815024375915527f,0.98730140924453735352f, +0.15734346210956573486f,0.98754394054412841797f,0.15582840144634246826f, +0.98778414726257324219f,0.15431296825408935547f,0.98802202939987182617f, +0.15279719233512878418f,0.98825758695602416992f,0.15128104388713836670f, +0.98849081993103027344f,0.14976453781127929688f,0.98872166872024536133f, +0.14824767410755157471f,0.98895025253295898438f,0.14673046767711639404f, +0.98917651176452636719f,0.14521291851997375488f,0.98940044641494750977f, +0.14369502663612365723f,0.98962199687957763672f,0.14217680692672729492f, +0.98984128236770629883f,0.14065824449062347412f,0.99005818367004394531f, +0.13913933932781219482f,0.99027281999588012695f,0.13762012124061584473f, +0.99048507213592529297f,0.13610057532787322998f,0.99069499969482421875f, +0.13458070158958435059f,0.99090266227722167969f,0.13306052982807159424f, +0.99110794067382812500f,0.13154003024101257324f,0.99131083488464355469f, +0.13001921772956848145f,0.99151146411895751953f,0.12849810719490051270f, +0.99170976877212524414f,0.12697669863700866699f,0.99190568923950195312f, +0.12545497715473175049f,0.99209928512573242188f,0.12393297255039215088f, +0.99229061603546142578f,0.12241067737340927124f,0.99247956275939941406f, +0.12088808417320251465f,0.99266612529754638672f,0.11936521530151367188f, +0.99285042285919189453f,0.11784206330776214600f,0.99303233623504638672f, +0.11631862819194793701f,0.99321192502975463867f,0.11479492485523223877f, +0.99338918924331665039f,0.11327095329761505127f,0.99356412887573242188f, +0.11174671351909637451f,0.99373674392700195312f,0.11022220551967620850f, +0.99390697479248046875f,0.10869744420051574707f,0.99407488107681274414f, +0.10717242211103439331f,0.99424046277999877930f,0.10564715415239334106f, +0.99440366029739379883f,0.10412163287401199341f,0.99456459283828735352f, +0.10259586572647094727f,0.99472314119338989258f,0.10106986016035079956f, +0.99487930536270141602f,0.09954361617565155029f,0.99503320455551147461f, +0.09801714122295379639f,0.99518471956253051758f,0.09649042785167694092f, +0.99533390998840332031f,0.09496349841356277466f,0.99548077583312988281f, +0.09343633800745010376f,0.99562525749206542969f,0.09190895408391952515f, +0.99576741456985473633f,0.09038136154413223267f,0.99590724706649780273f, +0.08885355293750762939f,0.99604469537734985352f,0.08732553571462631226f, +0.99617981910705566406f,0.08579730987548828125f,0.99631261825561523438f, +0.08426889032125473022f,0.99644303321838378906f,0.08274026215076446533f, +0.99657112360000610352f,0.08121144771575927734f,0.99669688940048217773f, +0.07968243956565856934f,0.99682027101516723633f,0.07815324515104293823f, +0.99694132804870605469f,0.07662386447191238403f,0.99706006050109863281f, +0.07509429752826690674f,0.99717640876770019531f,0.07356456667184829712f, +0.99729043245315551758f,0.07203464955091476440f,0.99740213155746459961f, +0.07050457596778869629f,0.99751144647598266602f,0.06897433102130889893f, +0.99761843681335449219f,0.06744392216205596924f,0.99772304296493530273f, +0.06591334939002990723f,0.99782532453536987305f,0.06438262760639190674f, +0.99792528152465820312f,0.06285175681114196777f,0.99802285432815551758f, +0.06132073700428009033f,0.99811810255050659180f,0.05978957191109657288f, +0.99821102619171142578f,0.05825826525688171387f,0.99830156564712524414f, +0.05672682076692581177f,0.99838972091674804688f,0.05519524589180946350f, +0.99847555160522460938f,0.05366353690624237061f,0.99855905771255493164f, +0.05213170498609542847f,0.99864023923873901367f,0.05059975013136863708f, +0.99871903657913208008f,0.04906767606735229492f,0.99879544973373413086f, +0.04753548279404640198f,0.99886953830718994141f,0.04600318148732185364f, +0.99894130229949951172f,0.04447077214717864990f,0.99901068210601806641f, +0.04293825849890708923f,0.99907773733139038086f,0.04140564054250717163f, +0.99914240837097167969f,0.03987292572855949402f,0.99920475482940673828f, +0.03834012150764465332f,0.99926477670669555664f,0.03680722415447235107f, +0.99932235479354858398f,0.03527423739433288574f,0.99937766790390014648f, +0.03374117240309715271f,0.99943059682846069336f,0.03220802545547485352f, +0.99948120117187500000f,0.03067480400204658508f,0.99952942132949829102f, +0.02914150804281234741f,0.99957531690597534180f,0.02760814502835273743f, +0.99961882829666137695f,0.02607471868395805359f,0.99966001510620117188f, +0.02454122900962829590f,0.99969881772994995117f,0.02300768159329891205f, +0.99973529577255249023f,0.02147408016026020050f,0.99976938962936401367f, +0.01994042843580245972f,0.99980115890502929688f,0.01840673014521598816f, +0.99983060359954833984f,0.01687298715114593506f,0.99985766410827636719f, +0.01533920597285032272f,0.99988234043121337891f,0.01380538847297430038f, +0.99990469217300415039f,0.01227153837680816650f,0.99992471933364868164f, +0.01073765940964221954f,0.99994236230850219727f,0.00920375436544418335f, +0.99995762109756469727f,0.00766982883214950562f,0.99997061491012573242f, +0.00613588467240333557f,0.99998116493225097656f,0.00460192607715725899f, +0.99998939037322998047f,0.00306795677170157433f,0.99999529123306274414f, +0.00153398013208061457f,0.99999880790710449219f,1.00000000000000000000f, +0.00000000000000000000f,0.99998116493225097656f,0.00613588467240333557f, +0.99992471933364868164f,0.01227153837680816650f,0.99983060359954833984f, +0.01840673014521598816f,0.99969881772994995117f,0.02454122900962829590f, +0.99952942132949829102f,0.03067480400204658508f,0.99932235479354858398f, +0.03680722415447235107f,0.99907773733139038086f,0.04293825849890708923f, +0.99879544973373413086f,0.04906767606735229492f,0.99847555160522460938f, +0.05519524589180946350f,0.99811810255050659180f,0.06132073700428009033f, +0.99772304296493530273f,0.06744392216205596924f,0.99729043245315551758f, +0.07356456667184829712f,0.99682027101516723633f,0.07968243956565856934f, +0.99631261825561523438f,0.08579730987548828125f,0.99576741456985473633f, +0.09190895408391952515f,0.99518471956253051758f,0.09801714122295379639f, +0.99456459283828735352f,0.10412163287401199341f,0.99390697479248046875f, +0.11022220551967620850f,0.99321192502975463867f,0.11631862819194793701f, +0.99247956275939941406f,0.12241067737340927124f,0.99170976877212524414f, +0.12849810719490051270f,0.99090266227722167969f,0.13458070158958435059f, +0.99005818367004394531f,0.14065824449062347412f,0.98917651176452636719f, +0.14673046767711639404f,0.98825758695602416992f,0.15279719233512878418f, +0.98730140924453735352f,0.15885815024375915527f,0.98630809783935546875f, +0.16491311788558959961f,0.98527765274047851562f,0.17096188664436340332f, +0.98421007394790649414f,0.17700421810150146484f,0.98310548067092895508f, +0.18303988873958587646f,0.98196387290954589844f,0.18906866014003753662f, +0.98078525066375732422f,0.19509032368659973145f,0.97956979274749755859f, +0.20110464096069335938f,0.97831737995147705078f,0.20711137354373931885f, +0.97702813148498535156f,0.21311031281948089600f,0.97570210695266723633f, +0.21910123527050018311f,0.97433936595916748047f,0.22508391737937927246f, +0.97293996810913085938f,0.23105810582637786865f,0.97150391340255737305f, +0.23702360689640045166f,0.97003126144409179688f,0.24298018217086791992f, +0.96852207183837890625f,0.24892760813236236572f,0.96697646379470825195f, +0.25486564636230468750f,0.96539443731307983398f,0.26079410314559936523f, +0.96377605199813842773f,0.26671275496482849121f,0.96212142705917358398f, +0.27262136340141296387f,0.96043050289154052734f,0.27851969003677368164f, +0.95870345830917358398f,0.28440752625465393066f,0.95694035291671752930f, +0.29028466343879699707f,0.95514118671417236328f,0.29615089297294616699f, +0.95330601930618286133f,0.30200594663619995117f,0.95143502950668334961f, +0.30784964561462402344f,0.94952815771102905273f,0.31368175148963928223f, +0.94758558273315429688f,0.31950202584266662598f,0.94560730457305908203f, +0.32531028985977172852f,0.94359344244003295898f,0.33110630512237548828f, +0.94154405593872070312f,0.33688986301422119141f,0.93945920467376708984f, +0.34266072511672973633f,0.93733900785446166992f,0.34841868281364440918f, +0.93518352508544921875f,0.35416352748870849609f,0.93299281597137451172f, +0.35989505052566528320f,0.93076694011688232422f,0.36561298370361328125f, +0.92850607633590698242f,0.37131720781326293945f,0.92621022462844848633f, +0.37700742483139038086f,0.92387950420379638672f,0.38268342614173889160f, +0.92151403427124023438f,0.38834503293037414551f,0.91911387443542480469f, +0.39399203658103942871f,0.91667908430099487305f,0.39962419867515563965f, +0.91420978307723999023f,0.40524131059646606445f,0.91170603036880493164f, +0.41084316372871398926f,0.90916800498962402344f,0.41642954945564270020f, +0.90659570693969726562f,0.42200025916099548340f,0.90398931503295898438f, +0.42755508422851562500f,0.90134882926940917969f,0.43309381604194641113f, +0.89867448806762695312f,0.43861624598503112793f,0.89596623182296752930f, +0.44412213563919067383f,0.89322429895401000977f,0.44961133599281311035f, +0.89044874906539916992f,0.45508357882499694824f,0.88763964176177978516f, +0.46053871512413024902f,0.88479709625244140625f,0.46597650647163391113f, +0.88192129135131835938f,0.47139674425125122070f,0.87901222705841064453f, +0.47679921984672546387f,0.87607008218765258789f,0.48218378424644470215f, +0.87309497594833374023f,0.48755016922950744629f,0.87008696794509887695f, +0.49289819598197937012f,0.86704623699188232422f,0.49822765588760375977f, +0.86397284269332885742f,0.50353837013244628906f,0.86086696386337280273f, +0.50883013010025024414f,0.85772860050201416016f,0.51410275697708129883f, +0.85455799102783203125f,0.51935601234436035156f,0.85135519504547119141f, +0.52458965778350830078f,0.84812033176422119141f,0.52980363368988037109f, +0.84485357999801635742f,0.53499764204025268555f,0.84155499935150146484f, +0.54017144441604614258f,0.83822470903396606445f,0.54532498121261596680f, +0.83486288785934448242f,0.55045795440673828125f,0.83146959543228149414f, +0.55557024478912353516f,0.82804507017135620117f,0.56066155433654785156f, +0.82458931207656860352f,0.56573182344436645508f,0.82110249996185302734f, +0.57078075408935546875f,0.81758481264114379883f,0.57580816745758056641f, +0.81403630971908569336f,0.58081394433975219727f,0.81045717000961303711f, +0.58579784631729125977f,0.80684757232666015625f,0.59075969457626342773f, +0.80320751667022705078f,0.59569931030273437500f,0.79953724145889282227f, +0.60061645507812500000f,0.79583692550659179688f,0.60551106929779052734f, +0.79210656881332397461f,0.61038279533386230469f,0.78834640979766845703f, +0.61523157358169555664f,0.78455656766891479492f,0.62005722522735595703f, +0.78073722124099731445f,0.62485951185226440430f,0.77688848972320556641f, +0.62963825464248657227f,0.77301043272018432617f,0.63439327478408813477f, +0.76910334825515747070f,0.63912445306777954102f,0.76516723632812500000f, +0.64383155107498168945f,0.76120239496231079102f,0.64851438999176025391f, +0.75720882415771484375f,0.65317285060882568359f,0.75318682193756103516f, +0.65780669450759887695f,0.74913638830184936523f,0.66241580247879028320f, +0.74505776166915893555f,0.66699993610382080078f,0.74095112085342407227f, +0.67155897617340087891f,0.73681658506393432617f,0.67609268426895141602f, +0.73265427350997924805f,0.68060100078582763672f,0.72846436500549316406f, +0.68508368730545043945f,0.72424709796905517578f,0.68954056501388549805f, +0.72000253200531005859f,0.69397145509719848633f,0.71573084592819213867f, +0.69837623834609985352f,0.71143221855163574219f,0.70275473594665527344f, +0.70710676908493041992f,0.70710676908493041992f,0.70275473594665527344f, +0.71143221855163574219f,0.69837623834609985352f,0.71573084592819213867f, +0.69397145509719848633f,0.72000253200531005859f,0.68954056501388549805f, +0.72424709796905517578f,0.68508368730545043945f,0.72846436500549316406f, +0.68060100078582763672f,0.73265427350997924805f,0.67609268426895141602f, +0.73681658506393432617f,0.67155897617340087891f,0.74095112085342407227f, +0.66699993610382080078f,0.74505776166915893555f,0.66241580247879028320f, +0.74913638830184936523f,0.65780669450759887695f,0.75318682193756103516f, +0.65317285060882568359f,0.75720882415771484375f,0.64851438999176025391f, +0.76120239496231079102f,0.64383155107498168945f,0.76516723632812500000f, +0.63912445306777954102f,0.76910334825515747070f,0.63439327478408813477f, +0.77301043272018432617f,0.62963825464248657227f,0.77688848972320556641f, +0.62485951185226440430f,0.78073722124099731445f,0.62005722522735595703f, +0.78455656766891479492f,0.61523157358169555664f,0.78834640979766845703f, +0.61038279533386230469f,0.79210656881332397461f,0.60551106929779052734f, +0.79583692550659179688f,0.60061645507812500000f,0.79953724145889282227f, +0.59569931030273437500f,0.80320751667022705078f,0.59075969457626342773f, +0.80684757232666015625f,0.58579784631729125977f,0.81045717000961303711f, +0.58081394433975219727f,0.81403630971908569336f,0.57580816745758056641f, +0.81758481264114379883f,0.57078075408935546875f,0.82110249996185302734f, +0.56573182344436645508f,0.82458931207656860352f,0.56066155433654785156f, +0.82804507017135620117f,0.55557024478912353516f,0.83146959543228149414f, +0.55045795440673828125f,0.83486288785934448242f,0.54532498121261596680f, +0.83822470903396606445f,0.54017144441604614258f,0.84155499935150146484f, +0.53499764204025268555f,0.84485357999801635742f,0.52980363368988037109f, +0.84812033176422119141f,0.52458965778350830078f,0.85135519504547119141f, +0.51935601234436035156f,0.85455799102783203125f,0.51410275697708129883f, +0.85772860050201416016f,0.50883013010025024414f,0.86086696386337280273f, +0.50353837013244628906f,0.86397284269332885742f,0.49822765588760375977f, +0.86704623699188232422f,0.49289819598197937012f,0.87008696794509887695f, +0.48755016922950744629f,0.87309497594833374023f,0.48218378424644470215f, +0.87607008218765258789f,0.47679921984672546387f,0.87901222705841064453f, +0.47139674425125122070f,0.88192129135131835938f,0.46597650647163391113f, +0.88479709625244140625f,0.46053871512413024902f,0.88763964176177978516f, +0.45508357882499694824f,0.89044874906539916992f,0.44961133599281311035f, +0.89322429895401000977f,0.44412213563919067383f,0.89596623182296752930f, +0.43861624598503112793f,0.89867448806762695312f,0.43309381604194641113f, +0.90134882926940917969f,0.42755508422851562500f,0.90398931503295898438f, +0.42200025916099548340f,0.90659570693969726562f,0.41642954945564270020f, +0.90916800498962402344f,0.41084316372871398926f,0.91170603036880493164f, +0.40524131059646606445f,0.91420978307723999023f,0.39962419867515563965f, +0.91667908430099487305f,0.39399203658103942871f,0.91911387443542480469f, +0.38834503293037414551f,0.92151403427124023438f,0.38268342614173889160f, +0.92387950420379638672f,0.37700742483139038086f,0.92621022462844848633f, +0.37131720781326293945f,0.92850607633590698242f,0.36561298370361328125f, +0.93076694011688232422f,0.35989505052566528320f,0.93299281597137451172f, +0.35416352748870849609f,0.93518352508544921875f,0.34841868281364440918f, +0.93733900785446166992f,0.34266072511672973633f,0.93945920467376708984f, +0.33688986301422119141f,0.94154405593872070312f,0.33110630512237548828f, +0.94359344244003295898f,0.32531028985977172852f,0.94560730457305908203f, +0.31950202584266662598f,0.94758558273315429688f,0.31368175148963928223f, +0.94952815771102905273f,0.30784964561462402344f,0.95143502950668334961f, +0.30200594663619995117f,0.95330601930618286133f,0.29615089297294616699f, +0.95514118671417236328f,0.29028466343879699707f,0.95694035291671752930f, +0.28440752625465393066f,0.95870345830917358398f,0.27851969003677368164f, +0.96043050289154052734f,0.27262136340141296387f,0.96212142705917358398f, +0.26671275496482849121f,0.96377605199813842773f,0.26079410314559936523f, +0.96539443731307983398f,0.25486564636230468750f,0.96697646379470825195f, +0.24892760813236236572f,0.96852207183837890625f,0.24298018217086791992f, +0.97003126144409179688f,0.23702360689640045166f,0.97150391340255737305f, +0.23105810582637786865f,0.97293996810913085938f,0.22508391737937927246f, +0.97433936595916748047f,0.21910123527050018311f,0.97570210695266723633f, +0.21311031281948089600f,0.97702813148498535156f,0.20711137354373931885f, +0.97831737995147705078f,0.20110464096069335938f,0.97956979274749755859f, +0.19509032368659973145f,0.98078525066375732422f,0.18906866014003753662f, +0.98196387290954589844f,0.18303988873958587646f,0.98310548067092895508f, +0.17700421810150146484f,0.98421007394790649414f,0.17096188664436340332f, +0.98527765274047851562f,0.16491311788558959961f,0.98630809783935546875f, +0.15885815024375915527f,0.98730140924453735352f,0.15279719233512878418f, +0.98825758695602416992f,0.14673046767711639404f,0.98917651176452636719f, +0.14065824449062347412f,0.99005818367004394531f,0.13458070158958435059f, +0.99090266227722167969f,0.12849810719490051270f,0.99170976877212524414f, +0.12241067737340927124f,0.99247956275939941406f,0.11631862819194793701f, +0.99321192502975463867f,0.11022220551967620850f,0.99390697479248046875f, +0.10412163287401199341f,0.99456459283828735352f,0.09801714122295379639f, +0.99518471956253051758f,0.09190895408391952515f,0.99576741456985473633f, +0.08579730987548828125f,0.99631261825561523438f,0.07968243956565856934f, +0.99682027101516723633f,0.07356456667184829712f,0.99729043245315551758f, +0.06744392216205596924f,0.99772304296493530273f,0.06132073700428009033f, +0.99811810255050659180f,0.05519524589180946350f,0.99847555160522460938f, +0.04906767606735229492f,0.99879544973373413086f,0.04293825849890708923f, +0.99907773733139038086f,0.03680722415447235107f,0.99932235479354858398f, +0.03067480400204658508f,0.99952942132949829102f,0.02454122900962829590f, +0.99969881772994995117f,0.01840673014521598816f,0.99983060359954833984f, +0.01227153837680816650f,0.99992471933364868164f,0.00613588467240333557f, +0.99998116493225097656f,1.00000000000000000000f,0.00000000000000000000f, +0.99969881772994995117f,0.02454122900962829590f,0.99879544973373413086f, +0.04906767606735229492f,0.99729043245315551758f,0.07356456667184829712f, +0.99518471956253051758f,0.09801714122295379639f,0.99247956275939941406f, +0.12241067737340927124f,0.98917651176452636719f,0.14673046767711639404f, +0.98527765274047851562f,0.17096188664436340332f,0.98078525066375732422f, +0.19509032368659973145f,0.97570210695266723633f,0.21910123527050018311f, +0.97003126144409179688f,0.24298018217086791992f,0.96377605199813842773f, +0.26671275496482849121f,0.95694035291671752930f,0.29028466343879699707f, +0.94952815771102905273f,0.31368175148963928223f,0.94154405593872070312f, +0.33688986301422119141f,0.93299281597137451172f,0.35989505052566528320f, +0.92387950420379638672f,0.38268342614173889160f,0.91420978307723999023f, +0.40524131059646606445f,0.90398931503295898438f,0.42755508422851562500f, +0.89322429895401000977f,0.44961133599281311035f,0.88192129135131835938f, +0.47139674425125122070f,0.87008696794509887695f,0.49289819598197937012f, +0.85772860050201416016f,0.51410275697708129883f,0.84485357999801635742f, +0.53499764204025268555f,0.83146959543228149414f,0.55557024478912353516f, +0.81758481264114379883f,0.57580816745758056641f,0.80320751667022705078f, +0.59569931030273437500f,0.78834640979766845703f,0.61523157358169555664f, +0.77301043272018432617f,0.63439327478408813477f,0.75720882415771484375f, +0.65317285060882568359f,0.74095112085342407227f,0.67155897617340087891f, +0.72424709796905517578f,0.68954056501388549805f,0.70710676908493041992f, +0.70710676908493041992f,0.68954056501388549805f,0.72424709796905517578f, +0.67155897617340087891f,0.74095112085342407227f,0.65317285060882568359f, +0.75720882415771484375f,0.63439327478408813477f,0.77301043272018432617f, +0.61523157358169555664f,0.78834640979766845703f,0.59569931030273437500f, +0.80320751667022705078f,0.57580816745758056641f,0.81758481264114379883f, +0.55557024478912353516f,0.83146959543228149414f,0.53499764204025268555f, +0.84485357999801635742f,0.51410275697708129883f,0.85772860050201416016f, +0.49289819598197937012f,0.87008696794509887695f,0.47139674425125122070f, +0.88192129135131835938f,0.44961133599281311035f,0.89322429895401000977f, +0.42755508422851562500f,0.90398931503295898438f,0.40524131059646606445f, +0.91420978307723999023f,0.38268342614173889160f,0.92387950420379638672f, +0.35989505052566528320f,0.93299281597137451172f,0.33688986301422119141f, +0.94154405593872070312f,0.31368175148963928223f,0.94952815771102905273f, +0.29028466343879699707f,0.95694035291671752930f,0.26671275496482849121f, +0.96377605199813842773f,0.24298018217086791992f,0.97003126144409179688f, +0.21910123527050018311f,0.97570210695266723633f,0.19509032368659973145f, +0.98078525066375732422f,0.17096188664436340332f,0.98527765274047851562f, +0.14673046767711639404f,0.98917651176452636719f,0.12241067737340927124f, +0.99247956275939941406f,0.09801714122295379639f,0.99518471956253051758f, +0.07356456667184829712f,0.99729043245315551758f,0.04906767606735229492f, +0.99879544973373413086f,0.02454122900962829590f,0.99969881772994995117f, +1.00000000000000000000f,0.00000000000000000000f,0.99518471956253051758f, +0.09801714122295379639f,0.98078525066375732422f,0.19509032368659973145f, +0.95694035291671752930f,0.29028466343879699707f,0.92387950420379638672f, +0.38268342614173889160f,0.88192129135131835938f,0.47139674425125122070f, +0.83146959543228149414f,0.55557024478912353516f,0.77301043272018432617f, +0.63439327478408813477f,0.70710676908493041992f,0.70710676908493041992f, +0.63439327478408813477f,0.77301043272018432617f,0.55557024478912353516f, +0.83146959543228149414f,0.47139674425125122070f,0.88192129135131835938f, +0.38268342614173889160f,0.92387950420379638672f,0.29028466343879699707f, +0.95694035291671752930f,0.19509032368659973145f,0.98078525066375732422f, +0.09801714122295379639f,0.99518471956253051758f,1.00000000000000000000f, +0.00000000000000000000f,0.92387950420379638672f,0.38268342614173889160f, +0.70710676908493041992f,0.70710676908493041992f,0.38268342614173889160f, +0.92387950420379638672f,}; + +float32_t rearranged_twiddle_stride2_4096_f32[2728]={ +1.00000000000000000000f,0.00000000000000000000f,0.99999529123306274414f, +0.00306795677170157433f,0.99998116493225097656f,0.00613588467240333557f, +0.99995762109756469727f,0.00920375436544418335f,0.99992471933364868164f, +0.01227153837680816650f,0.99988234043121337891f,0.01533920597285032272f, +0.99983060359954833984f,0.01840673014521598816f,0.99976938962936401367f, +0.02147408016026020050f,0.99969881772994995117f,0.02454122900962829590f, +0.99961882829666137695f,0.02760814502835273743f,0.99952942132949829102f, +0.03067480400204658508f,0.99943059682846069336f,0.03374117240309715271f, +0.99932235479354858398f,0.03680722415447235107f,0.99920475482940673828f, +0.03987292572855949402f,0.99907773733139038086f,0.04293825849890708923f, +0.99894130229949951172f,0.04600318148732185364f,0.99879544973373413086f, +0.04906767606735229492f,0.99864023923873901367f,0.05213170498609542847f, +0.99847555160522460938f,0.05519524589180946350f,0.99830156564712524414f, +0.05825826525688171387f,0.99811810255050659180f,0.06132073700428009033f, +0.99792528152465820312f,0.06438262760639190674f,0.99772304296493530273f, +0.06744392216205596924f,0.99751144647598266602f,0.07050457596778869629f, +0.99729043245315551758f,0.07356456667184829712f,0.99706006050109863281f, +0.07662386447191238403f,0.99682027101516723633f,0.07968243956565856934f, +0.99657112360000610352f,0.08274026215076446533f,0.99631261825561523438f, +0.08579730987548828125f,0.99604469537734985352f,0.08885355293750762939f, +0.99576741456985473633f,0.09190895408391952515f,0.99548077583312988281f, +0.09496349841356277466f,0.99518471956253051758f,0.09801714122295379639f, +0.99487930536270141602f,0.10106986016035079956f,0.99456459283828735352f, +0.10412163287401199341f,0.99424046277999877930f,0.10717242211103439331f, +0.99390697479248046875f,0.11022220551967620850f,0.99356412887573242188f, +0.11327095329761505127f,0.99321192502975463867f,0.11631862819194793701f, +0.99285042285919189453f,0.11936521530151367188f,0.99247956275939941406f, +0.12241067737340927124f,0.99209928512573242188f,0.12545497715473175049f, +0.99170976877212524414f,0.12849810719490051270f,0.99131083488464355469f, +0.13154003024101257324f,0.99090266227722167969f,0.13458070158958435059f, +0.99048507213592529297f,0.13762012124061584473f,0.99005818367004394531f, +0.14065824449062347412f,0.98962199687957763672f,0.14369502663612365723f, +0.98917651176452636719f,0.14673046767711639404f,0.98872166872024536133f, +0.14976453781127929688f,0.98825758695602416992f,0.15279719233512878418f, +0.98778414726257324219f,0.15582840144634246826f,0.98730140924453735352f, +0.15885815024375915527f,0.98680937290191650391f,0.16188639402389526367f, +0.98630809783935546875f,0.16491311788558959961f,0.98579752445220947266f, +0.16793829202651977539f,0.98527765274047851562f,0.17096188664436340332f, +0.98474848270416259766f,0.17398387193679809570f,0.98421007394790649414f, +0.17700421810150146484f,0.98366242647171020508f,0.18002289533615112305f, +0.98310548067092895508f,0.18303988873958587646f,0.98253929615020751953f, +0.18605515360832214355f,0.98196387290954589844f,0.18906866014003753662f, +0.98137921094894409180f,0.19208039343357086182f,0.98078525066375732422f, +0.19509032368659973145f,0.98018211126327514648f,0.19809840619564056396f, +0.97956979274749755859f,0.20110464096069335938f,0.97894817590713500977f, +0.20410896837711334229f,0.97831737995147705078f,0.20711137354373931885f, +0.97767734527587890625f,0.21011184155941009521f,0.97702813148498535156f, +0.21311031281948089600f,0.97636973857879638672f,0.21610680222511291504f, +0.97570210695266723633f,0.21910123527050018311f,0.97502535581588745117f, +0.22209362685680389404f,0.97433936595916748047f,0.22508391737937927246f, +0.97364425659179687500f,0.22807207703590393066f,0.97293996810913085938f, +0.23105810582637786865f,0.97222650051116943359f,0.23404195904731750488f, +0.97150391340255737305f,0.23702360689640045166f,0.97077214717864990234f, +0.24000301957130432129f,0.97003126144409179688f,0.24298018217086791992f, +0.96928125619888305664f,0.24595504999160766602f,0.96852207183837890625f, +0.24892760813236236572f,0.96775382757186889648f,0.25189781188964843750f, +0.96697646379470825195f,0.25486564636230468750f,0.96618998050689697266f, +0.25783109664916992188f,0.96539443731307983398f,0.26079410314559936523f, +0.96458977460861206055f,0.26375466585159301758f,0.96377605199813842773f, +0.26671275496482849121f,0.96295326948165893555f,0.26966831088066101074f, +0.96212142705917358398f,0.27262136340141296387f,0.96128046512603759766f, +0.27557182312011718750f,0.96043050289154052734f,0.27851969003677368164f, +0.95957154035568237305f,0.28146493434906005859f,0.95870345830917358398f, +0.28440752625465393066f,0.95782643556594848633f,0.28734746575355529785f, +0.95694035291671752930f,0.29028466343879699707f,0.95604526996612548828f, +0.29321914911270141602f,0.95514118671417236328f,0.29615089297294616699f, +0.95422810316085815430f,0.29907983541488647461f,0.95330601930618286133f, +0.30200594663619995117f,0.95237499475479125977f,0.30492922663688659668f, +0.95143502950668334961f,0.30784964561462402344f,0.95048606395721435547f, +0.31076714396476745605f,0.94952815771102905273f,0.31368175148963928223f, +0.94856137037277221680f,0.31659337878227233887f,0.94758558273315429688f, +0.31950202584266662598f,0.94660091400146484375f,0.32240769267082214355f, +0.94560730457305908203f,0.32531028985977172852f,0.94460481405258178711f, +0.32820984721183776855f,0.94359344244003295898f,0.33110630512237548828f, +0.94257318973541259766f,0.33399966359138488770f,0.94154405593872070312f, +0.33688986301422119141f,0.94050604104995727539f,0.33977687358856201172f, +0.93945920467376708984f,0.34266072511672973633f,0.93840354681015014648f, +0.34554132819175720215f,0.93733900785446166992f,0.34841868281364440918f, +0.93626564741134643555f,0.35129275918006896973f,0.93518352508544921875f, +0.35416352748870849609f,0.93409252166748046875f,0.35703095793724060059f, +0.93299281597137451172f,0.35989505052566528320f,0.93188428878784179688f, +0.36275571584701538086f,0.93076694011688232422f,0.36561298370361328125f, +0.92964088916778564453f,0.36846682429313659668f,0.92850607633590698242f, +0.37131720781326293945f,0.92736250162124633789f,0.37416407465934753418f, +0.92621022462844848633f,0.37700742483139038086f,0.92504924535751342773f, +0.37984719872474670410f,0.92387950420379638672f,0.38268342614173889160f, +0.92270112037658691406f,0.38551604747772216797f,0.92151403427124023438f, +0.38834503293037414551f,0.92031830549240112305f,0.39117038249969482422f, +0.91911387443542480469f,0.39399203658103942871f,0.91790080070495605469f, +0.39680999517440795898f,0.91667908430099487305f,0.39962419867515563965f, +0.91544872522354125977f,0.40243464708328247070f,0.91420978307723999023f, +0.40524131059646606445f,0.91296219825744628906f,0.40804415941238403320f, +0.91170603036880493164f,0.41084316372871398926f,0.91044127941131591797f, +0.41363832354545593262f,0.90916800498962402344f,0.41642954945564270020f, +0.90788608789443969727f,0.41921690106391906738f,0.90659570693969726562f, +0.42200025916099548340f,0.90529674291610717773f,0.42477968335151672363f, +0.90398931503295898438f,0.42755508422851562500f,0.90267330408096313477f, +0.43032649159431457520f,0.90134882926940917969f,0.43309381604194641113f, +0.90001589059829711914f,0.43585708737373352051f,0.89867448806762695312f, +0.43861624598503112793f,0.89732456207275390625f,0.44137126207351684570f, +0.89596623182296752930f,0.44412213563919067383f,0.89459949731826782227f, +0.44686883687973022461f,0.89322429895401000977f,0.44961133599281311035f, +0.89184069633483886719f,0.45234957337379455566f,0.89044874906539916992f, +0.45508357882499694824f,0.88904833793640136719f,0.45781329274177551270f, +0.88763964176177978516f,0.46053871512413024902f,0.88622254133224487305f, +0.46325978636741638184f,0.88479709625244140625f,0.46597650647163391113f, +0.88336336612701416016f,0.46868881583213806152f,0.88192129135131835938f, +0.47139674425125122070f,0.88047087192535400391f,0.47410020232200622559f, +0.87901222705841064453f,0.47679921984672546387f,0.87754529714584350586f, +0.47949376702308654785f,0.87607008218765258789f,0.48218378424644470215f, +0.87458664178848266602f,0.48486924171447753906f,0.87309497594833374023f, +0.48755016922950744629f,0.87159508466720581055f,0.49022647738456726074f, +0.87008696794509887695f,0.49289819598197937012f,0.86857068538665771484f, +0.49556526541709899902f,0.86704623699188232422f,0.49822765588760375977f, +0.86551362276077270508f,0.50088536739349365234f,0.86397284269332885742f, +0.50353837013244628906f,0.86242395639419555664f,0.50618666410446166992f, +0.86086696386337280273f,0.50883013010025024414f,0.85930180549621582031f, +0.51146882772445678711f,0.85772860050201416016f,0.51410275697708129883f, +0.85614734888076782227f,0.51673179864883422852f,0.85455799102783203125f, +0.51935601234436035156f,0.85296058654785156250f,0.52197527885437011719f, +0.85135519504547119141f,0.52458965778350830078f,0.84974175691604614258f, +0.52719914913177490234f,0.84812033176422119141f,0.52980363368988037109f, +0.84649091958999633789f,0.53240311145782470703f,0.84485357999801635742f, +0.53499764204025268555f,0.84320825338363647461f,0.53758704662322998047f, +0.84155499935150146484f,0.54017144441604614258f,0.83989381790161132812f, +0.54275077581405639648f,0.83822470903396606445f,0.54532498121261596680f, +0.83654773235321044922f,0.54789406061172485352f,0.83486288785934448242f, +0.55045795440673828125f,0.83317017555236816406f,0.55301672220230102539f, +0.83146959543228149414f,0.55557024478912353516f,0.82976120710372924805f, +0.55811852216720581055f,0.82804507017135620117f,0.56066155433654785156f, +0.82632106542587280273f,0.56319934129714965820f,0.82458931207656860352f, +0.56573182344436645508f,0.82284981012344360352f,0.56825894117355346680f, +0.82110249996185302734f,0.57078075408935546875f,0.81934750080108642578f, +0.57329714298248291016f,0.81758481264114379883f,0.57580816745758056641f, +0.81581443548202514648f,0.57831376791000366211f,0.81403630971908569336f, +0.58081394433975219727f,0.81225061416625976562f,0.58330863714218139648f, +0.81045717000961303711f,0.58579784631729125977f,0.80865615606307983398f, +0.58828157186508178711f,0.80684757232666015625f,0.59075969457626342773f, +0.80503135919570922852f,0.59323227405548095703f,0.80320751667022705078f, +0.59569931030273437500f,0.80137616395950317383f,0.59816068410873413086f, +0.79953724145889282227f,0.60061645507812500000f,0.79769086837768554688f, +0.60306662321090698242f,0.79583692550659179688f,0.60551106929779052734f, +0.79397547245025634766f,0.60794979333877563477f,0.79210656881332397461f, +0.61038279533386230469f,0.79023021459579467773f,0.61281007528305053711f, +0.78834640979766845703f,0.61523157358169555664f,0.78645521402359008789f, +0.61764729022979736328f,0.78455656766891479492f,0.62005722522735595703f, +0.78265058994293212891f,0.62246125936508178711f,0.78073722124099731445f, +0.62485951185226440430f,0.77881652116775512695f,0.62725180387496948242f, +0.77688848972320556641f,0.62963825464248657227f,0.77495312690734863281f, +0.63201874494552612305f,0.77301043272018432617f,0.63439327478408813477f, +0.77106052637100219727f,0.63676184415817260742f,0.76910334825515747070f, +0.63912445306777954102f,0.76713889837265014648f,0.64148104190826416016f, +0.76516723632812500000f,0.64383155107498168945f,0.76318842172622680664f, +0.64617604017257690430f,0.76120239496231079102f,0.64851438999176025391f, +0.75920921564102172852f,0.65084666013717651367f,0.75720882415771484375f, +0.65317285060882568359f,0.75520139932632446289f,0.65549284219741821289f, +0.75318682193756103516f,0.65780669450759887695f,0.75116515159606933594f, +0.66011434793472290039f,0.74913638830184936523f,0.66241580247879028320f, +0.74710059165954589844f,0.66471099853515625000f,0.74505776166915893555f, +0.66699993610382080078f,0.74300795793533325195f,0.66928261518478393555f, +0.74095112085342407227f,0.67155897617340087891f,0.73888731002807617188f, +0.67382901906967163086f,0.73681658506393432617f,0.67609268426895141602f, +0.73473888635635375977f,0.67835003137588500977f,0.73265427350997924805f, +0.68060100078582763672f,0.73056274652481079102f,0.68284553289413452148f, +0.72846436500549316406f,0.68508368730545043945f,0.72635912895202636719f, +0.68731534481048583984f,0.72424709796905517578f,0.68954056501388549805f, +0.72212821245193481445f,0.69175922870635986328f,0.72000253200531005859f, +0.69397145509719848633f,0.71787005662918090820f,0.69617712497711181641f, +0.71573084592819213867f,0.69837623834609985352f,0.71358484029769897461f, +0.70056879520416259766f,0.71143221855163574219f,0.70275473594665527344f, +0.70927280187606811523f,0.70493406057357788086f,0.70710676908493041992f, +0.70710676908493041992f,0.70493406057357788086f,0.70927280187606811523f, +0.70275473594665527344f,0.71143221855163574219f,0.70056879520416259766f, +0.71358484029769897461f,0.69837623834609985352f,0.71573084592819213867f, +0.69617712497711181641f,0.71787005662918090820f,0.69397145509719848633f, +0.72000253200531005859f,0.69175922870635986328f,0.72212821245193481445f, +0.68954056501388549805f,0.72424709796905517578f,0.68731534481048583984f, +0.72635912895202636719f,0.68508368730545043945f,0.72846436500549316406f, +0.68284553289413452148f,0.73056274652481079102f,0.68060100078582763672f, +0.73265427350997924805f,0.67835003137588500977f,0.73473888635635375977f, +0.67609268426895141602f,0.73681658506393432617f,0.67382901906967163086f, +0.73888731002807617188f,0.67155897617340087891f,0.74095112085342407227f, +0.66928261518478393555f,0.74300795793533325195f,0.66699993610382080078f, +0.74505776166915893555f,0.66471099853515625000f,0.74710059165954589844f, +0.66241580247879028320f,0.74913638830184936523f,0.66011434793472290039f, +0.75116515159606933594f,0.65780669450759887695f,0.75318682193756103516f, +0.65549284219741821289f,0.75520139932632446289f,0.65317285060882568359f, +0.75720882415771484375f,0.65084666013717651367f,0.75920921564102172852f, +0.64851438999176025391f,0.76120239496231079102f,0.64617604017257690430f, +0.76318842172622680664f,0.64383155107498168945f,0.76516723632812500000f, +0.64148104190826416016f,0.76713889837265014648f,0.63912445306777954102f, +0.76910334825515747070f,0.63676184415817260742f,0.77106052637100219727f, +0.63439327478408813477f,0.77301043272018432617f,0.63201874494552612305f, +0.77495312690734863281f,0.62963825464248657227f,0.77688848972320556641f, +0.62725180387496948242f,0.77881652116775512695f,0.62485951185226440430f, +0.78073722124099731445f,0.62246125936508178711f,0.78265058994293212891f, +0.62005722522735595703f,0.78455656766891479492f,0.61764729022979736328f, +0.78645521402359008789f,0.61523157358169555664f,0.78834640979766845703f, +0.61281007528305053711f,0.79023021459579467773f,0.61038279533386230469f, +0.79210656881332397461f,0.60794979333877563477f,0.79397547245025634766f, +0.60551106929779052734f,0.79583692550659179688f,0.60306662321090698242f, +0.79769086837768554688f,0.60061645507812500000f,0.79953724145889282227f, +0.59816068410873413086f,0.80137616395950317383f,0.59569931030273437500f, +0.80320751667022705078f,0.59323227405548095703f,0.80503135919570922852f, +0.59075969457626342773f,0.80684757232666015625f,0.58828157186508178711f, +0.80865615606307983398f,0.58579784631729125977f,0.81045717000961303711f, +0.58330863714218139648f,0.81225061416625976562f,0.58081394433975219727f, +0.81403630971908569336f,0.57831376791000366211f,0.81581443548202514648f, +0.57580816745758056641f,0.81758481264114379883f,0.57329714298248291016f, +0.81934750080108642578f,0.57078075408935546875f,0.82110249996185302734f, +0.56825894117355346680f,0.82284981012344360352f,0.56573182344436645508f, +0.82458931207656860352f,0.56319934129714965820f,0.82632106542587280273f, +0.56066155433654785156f,0.82804507017135620117f,0.55811852216720581055f, +0.82976120710372924805f,0.55557024478912353516f,0.83146959543228149414f, +0.55301672220230102539f,0.83317017555236816406f,0.55045795440673828125f, +0.83486288785934448242f,0.54789406061172485352f,0.83654773235321044922f, +0.54532498121261596680f,0.83822470903396606445f,0.54275077581405639648f, +0.83989381790161132812f,0.54017144441604614258f,0.84155499935150146484f, +0.53758704662322998047f,0.84320825338363647461f,0.53499764204025268555f, +0.84485357999801635742f,0.53240311145782470703f,0.84649091958999633789f, +0.52980363368988037109f,0.84812033176422119141f,0.52719914913177490234f, +0.84974175691604614258f,0.52458965778350830078f,0.85135519504547119141f, +0.52197527885437011719f,0.85296058654785156250f,0.51935601234436035156f, +0.85455799102783203125f,0.51673179864883422852f,0.85614734888076782227f, +0.51410275697708129883f,0.85772860050201416016f,0.51146882772445678711f, +0.85930180549621582031f,0.50883013010025024414f,0.86086696386337280273f, +0.50618666410446166992f,0.86242395639419555664f,0.50353837013244628906f, +0.86397284269332885742f,0.50088536739349365234f,0.86551362276077270508f, +0.49822765588760375977f,0.86704623699188232422f,0.49556526541709899902f, +0.86857068538665771484f,0.49289819598197937012f,0.87008696794509887695f, +0.49022647738456726074f,0.87159508466720581055f,0.48755016922950744629f, +0.87309497594833374023f,0.48486924171447753906f,0.87458664178848266602f, +0.48218378424644470215f,0.87607008218765258789f,0.47949376702308654785f, +0.87754529714584350586f,0.47679921984672546387f,0.87901222705841064453f, +0.47410020232200622559f,0.88047087192535400391f,0.47139674425125122070f, +0.88192129135131835938f,0.46868881583213806152f,0.88336336612701416016f, +0.46597650647163391113f,0.88479709625244140625f,0.46325978636741638184f, +0.88622254133224487305f,0.46053871512413024902f,0.88763964176177978516f, +0.45781329274177551270f,0.88904833793640136719f,0.45508357882499694824f, +0.89044874906539916992f,0.45234957337379455566f,0.89184069633483886719f, +0.44961133599281311035f,0.89322429895401000977f,0.44686883687973022461f, +0.89459949731826782227f,0.44412213563919067383f,0.89596623182296752930f, +0.44137126207351684570f,0.89732456207275390625f,0.43861624598503112793f, +0.89867448806762695312f,0.43585708737373352051f,0.90001589059829711914f, +0.43309381604194641113f,0.90134882926940917969f,0.43032649159431457520f, +0.90267330408096313477f,0.42755508422851562500f,0.90398931503295898438f, +0.42477968335151672363f,0.90529674291610717773f,0.42200025916099548340f, +0.90659570693969726562f,0.41921690106391906738f,0.90788608789443969727f, +0.41642954945564270020f,0.90916800498962402344f,0.41363832354545593262f, +0.91044127941131591797f,0.41084316372871398926f,0.91170603036880493164f, +0.40804415941238403320f,0.91296219825744628906f,0.40524131059646606445f, +0.91420978307723999023f,0.40243464708328247070f,0.91544872522354125977f, +0.39962419867515563965f,0.91667908430099487305f,0.39680999517440795898f, +0.91790080070495605469f,0.39399203658103942871f,0.91911387443542480469f, +0.39117038249969482422f,0.92031830549240112305f,0.38834503293037414551f, +0.92151403427124023438f,0.38551604747772216797f,0.92270112037658691406f, +0.38268342614173889160f,0.92387950420379638672f,0.37984719872474670410f, +0.92504924535751342773f,0.37700742483139038086f,0.92621022462844848633f, +0.37416407465934753418f,0.92736250162124633789f,0.37131720781326293945f, +0.92850607633590698242f,0.36846682429313659668f,0.92964088916778564453f, +0.36561298370361328125f,0.93076694011688232422f,0.36275571584701538086f, +0.93188428878784179688f,0.35989505052566528320f,0.93299281597137451172f, +0.35703095793724060059f,0.93409252166748046875f,0.35416352748870849609f, +0.93518352508544921875f,0.35129275918006896973f,0.93626564741134643555f, +0.34841868281364440918f,0.93733900785446166992f,0.34554132819175720215f, +0.93840354681015014648f,0.34266072511672973633f,0.93945920467376708984f, +0.33977687358856201172f,0.94050604104995727539f,0.33688986301422119141f, +0.94154405593872070312f,0.33399966359138488770f,0.94257318973541259766f, +0.33110630512237548828f,0.94359344244003295898f,0.32820984721183776855f, +0.94460481405258178711f,0.32531028985977172852f,0.94560730457305908203f, +0.32240769267082214355f,0.94660091400146484375f,0.31950202584266662598f, +0.94758558273315429688f,0.31659337878227233887f,0.94856137037277221680f, +0.31368175148963928223f,0.94952815771102905273f,0.31076714396476745605f, +0.95048606395721435547f,0.30784964561462402344f,0.95143502950668334961f, +0.30492922663688659668f,0.95237499475479125977f,0.30200594663619995117f, +0.95330601930618286133f,0.29907983541488647461f,0.95422810316085815430f, +0.29615089297294616699f,0.95514118671417236328f,0.29321914911270141602f, +0.95604526996612548828f,0.29028466343879699707f,0.95694035291671752930f, +0.28734746575355529785f,0.95782643556594848633f,0.28440752625465393066f, +0.95870345830917358398f,0.28146493434906005859f,0.95957154035568237305f, +0.27851969003677368164f,0.96043050289154052734f,0.27557182312011718750f, +0.96128046512603759766f,0.27262136340141296387f,0.96212142705917358398f, +0.26966831088066101074f,0.96295326948165893555f,0.26671275496482849121f, +0.96377605199813842773f,0.26375466585159301758f,0.96458977460861206055f, +0.26079410314559936523f,0.96539443731307983398f,0.25783109664916992188f, +0.96618998050689697266f,0.25486564636230468750f,0.96697646379470825195f, +0.25189781188964843750f,0.96775382757186889648f,0.24892760813236236572f, +0.96852207183837890625f,0.24595504999160766602f,0.96928125619888305664f, +0.24298018217086791992f,0.97003126144409179688f,0.24000301957130432129f, +0.97077214717864990234f,0.23702360689640045166f,0.97150391340255737305f, +0.23404195904731750488f,0.97222650051116943359f,0.23105810582637786865f, +0.97293996810913085938f,0.22807207703590393066f,0.97364425659179687500f, +0.22508391737937927246f,0.97433936595916748047f,0.22209362685680389404f, +0.97502535581588745117f,0.21910123527050018311f,0.97570210695266723633f, +0.21610680222511291504f,0.97636973857879638672f,0.21311031281948089600f, +0.97702813148498535156f,0.21011184155941009521f,0.97767734527587890625f, +0.20711137354373931885f,0.97831737995147705078f,0.20410896837711334229f, +0.97894817590713500977f,0.20110464096069335938f,0.97956979274749755859f, +0.19809840619564056396f,0.98018211126327514648f,0.19509032368659973145f, +0.98078525066375732422f,0.19208039343357086182f,0.98137921094894409180f, +0.18906866014003753662f,0.98196387290954589844f,0.18605515360832214355f, +0.98253929615020751953f,0.18303988873958587646f,0.98310548067092895508f, +0.18002289533615112305f,0.98366242647171020508f,0.17700421810150146484f, +0.98421007394790649414f,0.17398387193679809570f,0.98474848270416259766f, +0.17096188664436340332f,0.98527765274047851562f,0.16793829202651977539f, +0.98579752445220947266f,0.16491311788558959961f,0.98630809783935546875f, +0.16188639402389526367f,0.98680937290191650391f,0.15885815024375915527f, +0.98730140924453735352f,0.15582840144634246826f,0.98778414726257324219f, +0.15279719233512878418f,0.98825758695602416992f,0.14976453781127929688f, +0.98872166872024536133f,0.14673046767711639404f,0.98917651176452636719f, +0.14369502663612365723f,0.98962199687957763672f,0.14065824449062347412f, +0.99005818367004394531f,0.13762012124061584473f,0.99048507213592529297f, +0.13458070158958435059f,0.99090266227722167969f,0.13154003024101257324f, +0.99131083488464355469f,0.12849810719490051270f,0.99170976877212524414f, +0.12545497715473175049f,0.99209928512573242188f,0.12241067737340927124f, +0.99247956275939941406f,0.11936521530151367188f,0.99285042285919189453f, +0.11631862819194793701f,0.99321192502975463867f,0.11327095329761505127f, +0.99356412887573242188f,0.11022220551967620850f,0.99390697479248046875f, +0.10717242211103439331f,0.99424046277999877930f,0.10412163287401199341f, +0.99456459283828735352f,0.10106986016035079956f,0.99487930536270141602f, +0.09801714122295379639f,0.99518471956253051758f,0.09496349841356277466f, +0.99548077583312988281f,0.09190895408391952515f,0.99576741456985473633f, +0.08885355293750762939f,0.99604469537734985352f,0.08579730987548828125f, +0.99631261825561523438f,0.08274026215076446533f,0.99657112360000610352f, +0.07968243956565856934f,0.99682027101516723633f,0.07662386447191238403f, +0.99706006050109863281f,0.07356456667184829712f,0.99729043245315551758f, +0.07050457596778869629f,0.99751144647598266602f,0.06744392216205596924f, +0.99772304296493530273f,0.06438262760639190674f,0.99792528152465820312f, +0.06132073700428009033f,0.99811810255050659180f,0.05825826525688171387f, +0.99830156564712524414f,0.05519524589180946350f,0.99847555160522460938f, +0.05213170498609542847f,0.99864023923873901367f,0.04906767606735229492f, +0.99879544973373413086f,0.04600318148732185364f,0.99894130229949951172f, +0.04293825849890708923f,0.99907773733139038086f,0.03987292572855949402f, +0.99920475482940673828f,0.03680722415447235107f,0.99932235479354858398f, +0.03374117240309715271f,0.99943059682846069336f,0.03067480400204658508f, +0.99952942132949829102f,0.02760814502835273743f,0.99961882829666137695f, +0.02454122900962829590f,0.99969881772994995117f,0.02147408016026020050f, +0.99976938962936401367f,0.01840673014521598816f,0.99983060359954833984f, +0.01533920597285032272f,0.99988234043121337891f,0.01227153837680816650f, +0.99992471933364868164f,0.00920375436544418335f,0.99995762109756469727f, +0.00613588467240333557f,0.99998116493225097656f,0.00306795677170157433f, +0.99999529123306274414f,0.00000000000000006123f,1.00000000000000000000f, +-0.00306795677170157433f,0.99999529123306274414f,-0.00613588467240333557f, +0.99998116493225097656f,-0.00920375436544418335f,0.99995762109756469727f, +-0.01227153837680816650f,0.99992471933364868164f,-0.01533920597285032272f, +0.99988234043121337891f,-0.01840673014521598816f,0.99983060359954833984f, +-0.02147408016026020050f,0.99976938962936401367f,-0.02454122900962829590f, +0.99969881772994995117f,-0.02760814502835273743f,0.99961882829666137695f, +-0.03067480400204658508f,0.99952942132949829102f,-0.03374117240309715271f, +0.99943059682846069336f,-0.03680722415447235107f,0.99932235479354858398f, +-0.03987292572855949402f,0.99920475482940673828f,-0.04293825849890708923f, +0.99907773733139038086f,-0.04600318148732185364f,0.99894130229949951172f, +-0.04906767606735229492f,0.99879544973373413086f,-0.05213170498609542847f, +0.99864023923873901367f,-0.05519524589180946350f,0.99847555160522460938f, +-0.05825826525688171387f,0.99830156564712524414f,-0.06132073700428009033f, +0.99811810255050659180f,-0.06438262760639190674f,0.99792528152465820312f, +-0.06744392216205596924f,0.99772304296493530273f,-0.07050457596778869629f, +0.99751144647598266602f,-0.07356456667184829712f,0.99729043245315551758f, +-0.07662386447191238403f,0.99706006050109863281f,-0.07968243956565856934f, +0.99682027101516723633f,-0.08274026215076446533f,0.99657112360000610352f, +-0.08579730987548828125f,0.99631261825561523438f,-0.08885355293750762939f, +0.99604469537734985352f,-0.09190895408391952515f,0.99576741456985473633f, +-0.09496349841356277466f,0.99548077583312988281f,-0.09801714122295379639f, +0.99518471956253051758f,-0.10106986016035079956f,0.99487930536270141602f, +-0.10412163287401199341f,0.99456459283828735352f,-0.10717242211103439331f, +0.99424046277999877930f,-0.11022220551967620850f,0.99390697479248046875f, +-0.11327095329761505127f,0.99356412887573242188f,-0.11631862819194793701f, +0.99321192502975463867f,-0.11936521530151367188f,0.99285042285919189453f, +-0.12241067737340927124f,0.99247956275939941406f,-0.12545497715473175049f, +0.99209928512573242188f,-0.12849810719490051270f,0.99170976877212524414f, +-0.13154003024101257324f,0.99131083488464355469f,-0.13458070158958435059f, +0.99090266227722167969f,-0.13762012124061584473f,0.99048507213592529297f, +-0.14065824449062347412f,0.99005818367004394531f,-0.14369502663612365723f, +0.98962199687957763672f,-0.14673046767711639404f,0.98917651176452636719f, +-0.14976453781127929688f,0.98872166872024536133f,-0.15279719233512878418f, +0.98825758695602416992f,-0.15582840144634246826f,0.98778414726257324219f, +-0.15885815024375915527f,0.98730140924453735352f,-0.16188639402389526367f, +0.98680937290191650391f,-0.16491311788558959961f,0.98630809783935546875f, +-0.16793829202651977539f,0.98579752445220947266f,-0.17096188664436340332f, +0.98527765274047851562f,-0.17398387193679809570f,0.98474848270416259766f, +-0.17700421810150146484f,0.98421007394790649414f,-0.18002289533615112305f, +0.98366242647171020508f,-0.18303988873958587646f,0.98310548067092895508f, +-0.18605515360832214355f,0.98253929615020751953f,-0.18906866014003753662f, +0.98196387290954589844f,-0.19208039343357086182f,0.98137921094894409180f, +-0.19509032368659973145f,0.98078525066375732422f,-0.19809840619564056396f, +0.98018211126327514648f,-0.20110464096069335938f,0.97956979274749755859f, +-0.20410896837711334229f,0.97894817590713500977f,-0.20711137354373931885f, +0.97831737995147705078f,-0.21011184155941009521f,0.97767734527587890625f, +-0.21311031281948089600f,0.97702813148498535156f,-0.21610680222511291504f, +0.97636973857879638672f,-0.21910123527050018311f,0.97570210695266723633f, +-0.22209362685680389404f,0.97502535581588745117f,-0.22508391737937927246f, +0.97433936595916748047f,-0.22807207703590393066f,0.97364425659179687500f, +-0.23105810582637786865f,0.97293996810913085938f,-0.23404195904731750488f, +0.97222650051116943359f,-0.23702360689640045166f,0.97150391340255737305f, +-0.24000301957130432129f,0.97077214717864990234f,-0.24298018217086791992f, +0.97003126144409179688f,-0.24595504999160766602f,0.96928125619888305664f, +-0.24892760813236236572f,0.96852207183837890625f,-0.25189781188964843750f, +0.96775382757186889648f,-0.25486564636230468750f,0.96697646379470825195f, +-0.25783109664916992188f,0.96618998050689697266f,-0.26079410314559936523f, +0.96539443731307983398f,-0.26375466585159301758f,0.96458977460861206055f, +-0.26671275496482849121f,0.96377605199813842773f,-0.26966831088066101074f, +0.96295326948165893555f,-0.27262136340141296387f,0.96212142705917358398f, +-0.27557182312011718750f,0.96128046512603759766f,-0.27851969003677368164f, +0.96043050289154052734f,-0.28146493434906005859f,0.95957154035568237305f, +-0.28440752625465393066f,0.95870345830917358398f,-0.28734746575355529785f, +0.95782643556594848633f,-0.29028466343879699707f,0.95694035291671752930f, +-0.29321914911270141602f,0.95604526996612548828f,-0.29615089297294616699f, +0.95514118671417236328f,-0.29907983541488647461f,0.95422810316085815430f, +-0.30200594663619995117f,0.95330601930618286133f,-0.30492922663688659668f, +0.95237499475479125977f,-0.30784964561462402344f,0.95143502950668334961f, +-0.31076714396476745605f,0.95048606395721435547f,-0.31368175148963928223f, +0.94952815771102905273f,-0.31659337878227233887f,0.94856137037277221680f, +-0.31950202584266662598f,0.94758558273315429688f,-0.32240769267082214355f, +0.94660091400146484375f,-0.32531028985977172852f,0.94560730457305908203f, +-0.32820984721183776855f,0.94460481405258178711f,-0.33110630512237548828f, +0.94359344244003295898f,-0.33399966359138488770f,0.94257318973541259766f, +-0.33688986301422119141f,0.94154405593872070312f,-0.33977687358856201172f, +0.94050604104995727539f,-0.34266072511672973633f,0.93945920467376708984f, +-0.34554132819175720215f,0.93840354681015014648f,-0.34841868281364440918f, +0.93733900785446166992f,-0.35129275918006896973f,0.93626564741134643555f, +-0.35416352748870849609f,0.93518352508544921875f,-0.35703095793724060059f, +0.93409252166748046875f,-0.35989505052566528320f,0.93299281597137451172f, +-0.36275571584701538086f,0.93188428878784179688f,-0.36561298370361328125f, +0.93076694011688232422f,-0.36846682429313659668f,0.92964088916778564453f, +-0.37131720781326293945f,0.92850607633590698242f,-0.37416407465934753418f, +0.92736250162124633789f,-0.37700742483139038086f,0.92621022462844848633f, +-0.37984719872474670410f,0.92504924535751342773f,-0.38268342614173889160f, +0.92387950420379638672f,-0.38551604747772216797f,0.92270112037658691406f, +-0.38834503293037414551f,0.92151403427124023438f,-0.39117038249969482422f, +0.92031830549240112305f,-0.39399203658103942871f,0.91911387443542480469f, +-0.39680999517440795898f,0.91790080070495605469f,-0.39962419867515563965f, +0.91667908430099487305f,-0.40243464708328247070f,0.91544872522354125977f, +-0.40524131059646606445f,0.91420978307723999023f,-0.40804415941238403320f, +0.91296219825744628906f,-0.41084316372871398926f,0.91170603036880493164f, +-0.41363832354545593262f,0.91044127941131591797f,-0.41642954945564270020f, +0.90916800498962402344f,-0.41921690106391906738f,0.90788608789443969727f, +-0.42200025916099548340f,0.90659570693969726562f,-0.42477968335151672363f, +0.90529674291610717773f,-0.42755508422851562500f,0.90398931503295898438f, +-0.43032649159431457520f,0.90267330408096313477f,-0.43309381604194641113f, +0.90134882926940917969f,-0.43585708737373352051f,0.90001589059829711914f, +-0.43861624598503112793f,0.89867448806762695312f,-0.44137126207351684570f, +0.89732456207275390625f,-0.44412213563919067383f,0.89596623182296752930f, +-0.44686883687973022461f,0.89459949731826782227f,-0.44961133599281311035f, +0.89322429895401000977f,-0.45234957337379455566f,0.89184069633483886719f, +-0.45508357882499694824f,0.89044874906539916992f,-0.45781329274177551270f, +0.88904833793640136719f,-0.46053871512413024902f,0.88763964176177978516f, +-0.46325978636741638184f,0.88622254133224487305f,-0.46597650647163391113f, +0.88479709625244140625f,-0.46868881583213806152f,0.88336336612701416016f, +-0.47139674425125122070f,0.88192129135131835938f,-0.47410020232200622559f, +0.88047087192535400391f,-0.47679921984672546387f,0.87901222705841064453f, +-0.47949376702308654785f,0.87754529714584350586f,-0.48218378424644470215f, +0.87607008218765258789f,-0.48486924171447753906f,0.87458664178848266602f, +-0.48755016922950744629f,0.87309497594833374023f,-0.49022647738456726074f, +0.87159508466720581055f,-0.49289819598197937012f,0.87008696794509887695f, +-0.49556526541709899902f,0.86857068538665771484f,-0.49822765588760375977f, +0.86704623699188232422f,-0.50088536739349365234f,0.86551362276077270508f, +-0.50353837013244628906f,0.86397284269332885742f,-0.50618666410446166992f, +0.86242395639419555664f,-0.50883013010025024414f,0.86086696386337280273f, +-0.51146882772445678711f,0.85930180549621582031f,-0.51410275697708129883f, +0.85772860050201416016f,-0.51673179864883422852f,0.85614734888076782227f, +-0.51935601234436035156f,0.85455799102783203125f,-0.52197527885437011719f, +0.85296058654785156250f,-0.52458965778350830078f,0.85135519504547119141f, +-0.52719914913177490234f,0.84974175691604614258f,-0.52980363368988037109f, +0.84812033176422119141f,-0.53240311145782470703f,0.84649091958999633789f, +-0.53499764204025268555f,0.84485357999801635742f,-0.53758704662322998047f, +0.84320825338363647461f,-0.54017144441604614258f,0.84155499935150146484f, +-0.54275077581405639648f,0.83989381790161132812f,-0.54532498121261596680f, +0.83822470903396606445f,-0.54789406061172485352f,0.83654773235321044922f, +-0.55045795440673828125f,0.83486288785934448242f,-0.55301672220230102539f, +0.83317017555236816406f,-0.55557024478912353516f,0.83146959543228149414f, +-0.55811852216720581055f,0.82976120710372924805f,-0.56066155433654785156f, +0.82804507017135620117f,-0.56319934129714965820f,0.82632106542587280273f, +-0.56573182344436645508f,0.82458931207656860352f,-0.56825894117355346680f, +0.82284981012344360352f,-0.57078075408935546875f,0.82110249996185302734f, +-0.57329714298248291016f,0.81934750080108642578f,-0.57580816745758056641f, +0.81758481264114379883f,-0.57831376791000366211f,0.81581443548202514648f, +-0.58081394433975219727f,0.81403630971908569336f,-0.58330863714218139648f, +0.81225061416625976562f,-0.58579784631729125977f,0.81045717000961303711f, +-0.58828157186508178711f,0.80865615606307983398f,-0.59075969457626342773f, +0.80684757232666015625f,-0.59323227405548095703f,0.80503135919570922852f, +-0.59569931030273437500f,0.80320751667022705078f,-0.59816068410873413086f, +0.80137616395950317383f,-0.60061645507812500000f,0.79953724145889282227f, +-0.60306662321090698242f,0.79769086837768554688f,-0.60551106929779052734f, +0.79583692550659179688f,-0.60794979333877563477f,0.79397547245025634766f, +-0.61038279533386230469f,0.79210656881332397461f,-0.61281007528305053711f, +0.79023021459579467773f,-0.61523157358169555664f,0.78834640979766845703f, +-0.61764729022979736328f,0.78645521402359008789f,-0.62005722522735595703f, +0.78455656766891479492f,-0.62246125936508178711f,0.78265058994293212891f, +-0.62485951185226440430f,0.78073722124099731445f,-0.62725180387496948242f, +0.77881652116775512695f,-0.62963825464248657227f,0.77688848972320556641f, +-0.63201874494552612305f,0.77495312690734863281f,-0.63439327478408813477f, +0.77301043272018432617f,-0.63676184415817260742f,0.77106052637100219727f, +-0.63912445306777954102f,0.76910334825515747070f,-0.64148104190826416016f, +0.76713889837265014648f,-0.64383155107498168945f,0.76516723632812500000f, +-0.64617604017257690430f,0.76318842172622680664f,-0.64851438999176025391f, +0.76120239496231079102f,-0.65084666013717651367f,0.75920921564102172852f, +-0.65317285060882568359f,0.75720882415771484375f,-0.65549284219741821289f, +0.75520139932632446289f,-0.65780669450759887695f,0.75318682193756103516f, +-0.66011434793472290039f,0.75116515159606933594f,-0.66241580247879028320f, +0.74913638830184936523f,-0.66471099853515625000f,0.74710059165954589844f, +-0.66699993610382080078f,0.74505776166915893555f,-0.66928261518478393555f, +0.74300795793533325195f,-0.67155897617340087891f,0.74095112085342407227f, +-0.67382901906967163086f,0.73888731002807617188f,-0.67609268426895141602f, +0.73681658506393432617f,-0.67835003137588500977f,0.73473888635635375977f, +-0.68060100078582763672f,0.73265427350997924805f,-0.68284553289413452148f, +0.73056274652481079102f,-0.68508368730545043945f,0.72846436500549316406f, +-0.68731534481048583984f,0.72635912895202636719f,-0.68954056501388549805f, +0.72424709796905517578f,-0.69175922870635986328f,0.72212821245193481445f, +-0.69397145509719848633f,0.72000253200531005859f,-0.69617712497711181641f, +0.71787005662918090820f,-0.69837623834609985352f,0.71573084592819213867f, +-0.70056879520416259766f,0.71358484029769897461f,-0.70275473594665527344f, +0.71143221855163574219f,-0.70493406057357788086f,0.70927280187606811523f, +-0.70710676908493041992f,0.70710676908493041992f,-0.70927280187606811523f, +0.70493406057357788086f,-0.71143221855163574219f,0.70275473594665527344f, +-0.71358484029769897461f,0.70056879520416259766f,-0.71573084592819213867f, +0.69837623834609985352f,-0.71787005662918090820f,0.69617712497711181641f, +-0.72000253200531005859f,0.69397145509719848633f,-0.72212821245193481445f, +0.69175922870635986328f,-0.72424709796905517578f,0.68954056501388549805f, +-0.72635912895202636719f,0.68731534481048583984f,-0.72846436500549316406f, +0.68508368730545043945f,-0.73056274652481079102f,0.68284553289413452148f, +-0.73265427350997924805f,0.68060100078582763672f,-0.73473888635635375977f, +0.67835003137588500977f,-0.73681658506393432617f,0.67609268426895141602f, +-0.73888731002807617188f,0.67382901906967163086f,-0.74095112085342407227f, +0.67155897617340087891f,-0.74300795793533325195f,0.66928261518478393555f, +-0.74505776166915893555f,0.66699993610382080078f,-0.74710059165954589844f, +0.66471099853515625000f,-0.74913638830184936523f,0.66241580247879028320f, +-0.75116515159606933594f,0.66011434793472290039f,-0.75318682193756103516f, +0.65780669450759887695f,-0.75520139932632446289f,0.65549284219741821289f, +-0.75720882415771484375f,0.65317285060882568359f,-0.75920921564102172852f, +0.65084666013717651367f,-0.76120239496231079102f,0.64851438999176025391f, +-0.76318842172622680664f,0.64617604017257690430f,-0.76516723632812500000f, +0.64383155107498168945f,-0.76713889837265014648f,0.64148104190826416016f, +-0.76910334825515747070f,0.63912445306777954102f,-0.77106052637100219727f, +0.63676184415817260742f,-0.77301043272018432617f,0.63439327478408813477f, +-0.77495312690734863281f,0.63201874494552612305f,-0.77688848972320556641f, +0.62963825464248657227f,-0.77881652116775512695f,0.62725180387496948242f, +-0.78073722124099731445f,0.62485951185226440430f,-0.78265058994293212891f, +0.62246125936508178711f,-0.78455656766891479492f,0.62005722522735595703f, +-0.78645521402359008789f,0.61764729022979736328f,-0.78834640979766845703f, +0.61523157358169555664f,-0.79023021459579467773f,0.61281007528305053711f, +-0.79210656881332397461f,0.61038279533386230469f,-0.79397547245025634766f, +0.60794979333877563477f,-0.79583692550659179688f,0.60551106929779052734f, +-0.79769086837768554688f,0.60306662321090698242f,-0.79953724145889282227f, +0.60061645507812500000f,-0.80137616395950317383f,0.59816068410873413086f, +-0.80320751667022705078f,0.59569931030273437500f,-0.80503135919570922852f, +0.59323227405548095703f,-0.80684757232666015625f,0.59075969457626342773f, +-0.80865615606307983398f,0.58828157186508178711f,-0.81045717000961303711f, +0.58579784631729125977f,-0.81225061416625976562f,0.58330863714218139648f, +-0.81403630971908569336f,0.58081394433975219727f,-0.81581443548202514648f, +0.57831376791000366211f,-0.81758481264114379883f,0.57580816745758056641f, +-0.81934750080108642578f,0.57329714298248291016f,-0.82110249996185302734f, +0.57078075408935546875f,-0.82284981012344360352f,0.56825894117355346680f, +-0.82458931207656860352f,0.56573182344436645508f,-0.82632106542587280273f, +0.56319934129714965820f,-0.82804507017135620117f,0.56066155433654785156f, +-0.82976120710372924805f,0.55811852216720581055f,-0.83146959543228149414f, +0.55557024478912353516f,-0.83317017555236816406f,0.55301672220230102539f, +-0.83486288785934448242f,0.55045795440673828125f,-0.83654773235321044922f, +0.54789406061172485352f,-0.83822470903396606445f,0.54532498121261596680f, +-0.83989381790161132812f,0.54275077581405639648f,-0.84155499935150146484f, +0.54017144441604614258f,-0.84320825338363647461f,0.53758704662322998047f, +-0.84485357999801635742f,0.53499764204025268555f,-0.84649091958999633789f, +0.53240311145782470703f,-0.84812033176422119141f,0.52980363368988037109f, +-0.84974175691604614258f,0.52719914913177490234f,-0.85135519504547119141f, +0.52458965778350830078f,-0.85296058654785156250f,0.52197527885437011719f, +-0.85455799102783203125f,0.51935601234436035156f,-0.85614734888076782227f, +0.51673179864883422852f,-0.85772860050201416016f,0.51410275697708129883f, +-0.85930180549621582031f,0.51146882772445678711f,-0.86086696386337280273f, +0.50883013010025024414f,-0.86242395639419555664f,0.50618666410446166992f, +-0.86397284269332885742f,0.50353837013244628906f,-0.86551362276077270508f, +0.50088536739349365234f,-0.86704623699188232422f,0.49822765588760375977f, +-0.86857068538665771484f,0.49556526541709899902f,-0.87008696794509887695f, +0.49289819598197937012f,-0.87159508466720581055f,0.49022647738456726074f, +-0.87309497594833374023f,0.48755016922950744629f,-0.87458664178848266602f, +0.48486924171447753906f,-0.87607008218765258789f,0.48218378424644470215f, +-0.87754529714584350586f,0.47949376702308654785f,-0.87901222705841064453f, +0.47679921984672546387f,-0.88047087192535400391f,0.47410020232200622559f, +-0.88192129135131835938f,0.47139674425125122070f,-0.88336336612701416016f, +0.46868881583213806152f,-0.88479709625244140625f,0.46597650647163391113f, +-0.88622254133224487305f,0.46325978636741638184f,-0.88763964176177978516f, +0.46053871512413024902f,-0.88904833793640136719f,0.45781329274177551270f, +-0.89044874906539916992f,0.45508357882499694824f,-0.89184069633483886719f, +0.45234957337379455566f,-0.89322429895401000977f,0.44961133599281311035f, +-0.89459949731826782227f,0.44686883687973022461f,-0.89596623182296752930f, +0.44412213563919067383f,-0.89732456207275390625f,0.44137126207351684570f, +-0.89867448806762695312f,0.43861624598503112793f,-0.90001589059829711914f, +0.43585708737373352051f,-0.90134882926940917969f,0.43309381604194641113f, +-0.90267330408096313477f,0.43032649159431457520f,-0.90398931503295898438f, +0.42755508422851562500f,-0.90529674291610717773f,0.42477968335151672363f, +-0.90659570693969726562f,0.42200025916099548340f,-0.90788608789443969727f, +0.41921690106391906738f,-0.90916800498962402344f,0.41642954945564270020f, +-0.91044127941131591797f,0.41363832354545593262f,-0.91170603036880493164f, +0.41084316372871398926f,-0.91296219825744628906f,0.40804415941238403320f, +-0.91420978307723999023f,0.40524131059646606445f,-0.91544872522354125977f, +0.40243464708328247070f,-0.91667908430099487305f,0.39962419867515563965f, +-0.91790080070495605469f,0.39680999517440795898f,-0.91911387443542480469f, +0.39399203658103942871f,-0.92031830549240112305f,0.39117038249969482422f, +-0.92151403427124023438f,0.38834503293037414551f,-0.92270112037658691406f, +0.38551604747772216797f,-0.92387950420379638672f,0.38268342614173889160f, +-0.92504924535751342773f,0.37984719872474670410f,-0.92621022462844848633f, +0.37700742483139038086f,-0.92736250162124633789f,0.37416407465934753418f, +-0.92850607633590698242f,0.37131720781326293945f,-0.92964088916778564453f, +0.36846682429313659668f,-0.93076694011688232422f,0.36561298370361328125f, +-0.93188428878784179688f,0.36275571584701538086f,-0.93299281597137451172f, +0.35989505052566528320f,-0.93409252166748046875f,0.35703095793724060059f, +-0.93518352508544921875f,0.35416352748870849609f,-0.93626564741134643555f, +0.35129275918006896973f,-0.93733900785446166992f,0.34841868281364440918f, +-0.93840354681015014648f,0.34554132819175720215f,-0.93945920467376708984f, +0.34266072511672973633f,-0.94050604104995727539f,0.33977687358856201172f, +-0.94154405593872070312f,0.33688986301422119141f,-0.94257318973541259766f, +0.33399966359138488770f,-0.94359344244003295898f,0.33110630512237548828f, +-0.94460481405258178711f,0.32820984721183776855f,-0.94560730457305908203f, +0.32531028985977172852f,-0.94660091400146484375f,0.32240769267082214355f, +-0.94758558273315429688f,0.31950202584266662598f,-0.94856137037277221680f, +0.31659337878227233887f,-0.94952815771102905273f,0.31368175148963928223f, +-0.95048606395721435547f,0.31076714396476745605f,-0.95143502950668334961f, +0.30784964561462402344f,-0.95237499475479125977f,0.30492922663688659668f, +-0.95330601930618286133f,0.30200594663619995117f,-0.95422810316085815430f, +0.29907983541488647461f,-0.95514118671417236328f,0.29615089297294616699f, +-0.95604526996612548828f,0.29321914911270141602f,-0.95694035291671752930f, +0.29028466343879699707f,-0.95782643556594848633f,0.28734746575355529785f, +-0.95870345830917358398f,0.28440752625465393066f,-0.95957154035568237305f, +0.28146493434906005859f,-0.96043050289154052734f,0.27851969003677368164f, +-0.96128046512603759766f,0.27557182312011718750f,-0.96212142705917358398f, +0.27262136340141296387f,-0.96295326948165893555f,0.26966831088066101074f, +-0.96377605199813842773f,0.26671275496482849121f,-0.96458977460861206055f, +0.26375466585159301758f,-0.96539443731307983398f,0.26079410314559936523f, +-0.96618998050689697266f,0.25783109664916992188f,-0.96697646379470825195f, +0.25486564636230468750f,-0.96775382757186889648f,0.25189781188964843750f, +-0.96852207183837890625f,0.24892760813236236572f,-0.96928125619888305664f, +0.24595504999160766602f,-0.97003126144409179688f,0.24298018217086791992f, +-0.97077214717864990234f,0.24000301957130432129f,-0.97150391340255737305f, +0.23702360689640045166f,-0.97222650051116943359f,0.23404195904731750488f, +-0.97293996810913085938f,0.23105810582637786865f,-0.97364425659179687500f, +0.22807207703590393066f,-0.97433936595916748047f,0.22508391737937927246f, +-0.97502535581588745117f,0.22209362685680389404f,-0.97570210695266723633f, +0.21910123527050018311f,-0.97636973857879638672f,0.21610680222511291504f, +-0.97702813148498535156f,0.21311031281948089600f,-0.97767734527587890625f, +0.21011184155941009521f,-0.97831737995147705078f,0.20711137354373931885f, +-0.97894817590713500977f,0.20410896837711334229f,-0.97956979274749755859f, +0.20110464096069335938f,-0.98018211126327514648f,0.19809840619564056396f, +-0.98078525066375732422f,0.19509032368659973145f,-0.98137921094894409180f, +0.19208039343357086182f,-0.98196387290954589844f,0.18906866014003753662f, +-0.98253929615020751953f,0.18605515360832214355f,-0.98310548067092895508f, +0.18303988873958587646f,-0.98366242647171020508f,0.18002289533615112305f, +-0.98421007394790649414f,0.17700421810150146484f,-0.98474848270416259766f, +0.17398387193679809570f,-0.98527765274047851562f,0.17096188664436340332f, +-0.98579752445220947266f,0.16793829202651977539f,-0.98630809783935546875f, +0.16491311788558959961f,-0.98680937290191650391f,0.16188639402389526367f, +-0.98730140924453735352f,0.15885815024375915527f,-0.98778414726257324219f, +0.15582840144634246826f,-0.98825758695602416992f,0.15279719233512878418f, +-0.98872166872024536133f,0.14976453781127929688f,-0.98917651176452636719f, +0.14673046767711639404f,-0.98962199687957763672f,0.14369502663612365723f, +-0.99005818367004394531f,0.14065824449062347412f,-0.99048507213592529297f, +0.13762012124061584473f,-0.99090266227722167969f,0.13458070158958435059f, +-0.99131083488464355469f,0.13154003024101257324f,-0.99170976877212524414f, +0.12849810719490051270f,-0.99209928512573242188f,0.12545497715473175049f, +-0.99247956275939941406f,0.12241067737340927124f,-0.99285042285919189453f, +0.11936521530151367188f,-0.99321192502975463867f,0.11631862819194793701f, +-0.99356412887573242188f,0.11327095329761505127f,-0.99390697479248046875f, +0.11022220551967620850f,-0.99424046277999877930f,0.10717242211103439331f, +-0.99456459283828735352f,0.10412163287401199341f,-0.99487930536270141602f, +0.10106986016035079956f,-0.99518471956253051758f,0.09801714122295379639f, +-0.99548077583312988281f,0.09496349841356277466f,-0.99576741456985473633f, +0.09190895408391952515f,-0.99604469537734985352f,0.08885355293750762939f, +-0.99631261825561523438f,0.08579730987548828125f,-0.99657112360000610352f, +0.08274026215076446533f,-0.99682027101516723633f,0.07968243956565856934f, +-0.99706006050109863281f,0.07662386447191238403f,-0.99729043245315551758f, +0.07356456667184829712f,-0.99751144647598266602f,0.07050457596778869629f, +-0.99772304296493530273f,0.06744392216205596924f,-0.99792528152465820312f, +0.06438262760639190674f,-0.99811810255050659180f,0.06132073700428009033f, +-0.99830156564712524414f,0.05825826525688171387f,-0.99847555160522460938f, +0.05519524589180946350f,-0.99864023923873901367f,0.05213170498609542847f, +-0.99879544973373413086f,0.04906767606735229492f,-0.99894130229949951172f, +0.04600318148732185364f,-0.99907773733139038086f,0.04293825849890708923f, +-0.99920475482940673828f,0.03987292572855949402f,-0.99932235479354858398f, +0.03680722415447235107f,-0.99943059682846069336f,0.03374117240309715271f, +-0.99952942132949829102f,0.03067480400204658508f,-0.99961882829666137695f, +0.02760814502835273743f,-0.99969881772994995117f,0.02454122900962829590f, +-0.99976938962936401367f,0.02147408016026020050f,-0.99983060359954833984f, +0.01840673014521598816f,-0.99988234043121337891f,0.01533920597285032272f, +-0.99992471933364868164f,0.01227153837680816650f,-0.99995762109756469727f, +0.00920375436544418335f,-0.99998116493225097656f,0.00613588467240333557f, +-0.99999529123306274414f,0.00306795677170157433f,1.00000000000000000000f, +0.00000000000000000000f,0.99992471933364868164f,0.01227153837680816650f, +0.99969881772994995117f,0.02454122900962829590f,0.99932235479354858398f, +0.03680722415447235107f,0.99879544973373413086f,0.04906767606735229492f, +0.99811810255050659180f,0.06132073700428009033f,0.99729043245315551758f, +0.07356456667184829712f,0.99631261825561523438f,0.08579730987548828125f, +0.99518471956253051758f,0.09801714122295379639f,0.99390697479248046875f, +0.11022220551967620850f,0.99247956275939941406f,0.12241067737340927124f, +0.99090266227722167969f,0.13458070158958435059f,0.98917651176452636719f, +0.14673046767711639404f,0.98730140924453735352f,0.15885815024375915527f, +0.98527765274047851562f,0.17096188664436340332f,0.98310548067092895508f, +0.18303988873958587646f,0.98078525066375732422f,0.19509032368659973145f, +0.97831737995147705078f,0.20711137354373931885f,0.97570210695266723633f, +0.21910123527050018311f,0.97293996810913085938f,0.23105810582637786865f, +0.97003126144409179688f,0.24298018217086791992f,0.96697646379470825195f, +0.25486564636230468750f,0.96377605199813842773f,0.26671275496482849121f, +0.96043050289154052734f,0.27851969003677368164f,0.95694035291671752930f, +0.29028466343879699707f,0.95330601930618286133f,0.30200594663619995117f, +0.94952815771102905273f,0.31368175148963928223f,0.94560730457305908203f, +0.32531028985977172852f,0.94154405593872070312f,0.33688986301422119141f, +0.93733900785446166992f,0.34841868281364440918f,0.93299281597137451172f, +0.35989505052566528320f,0.92850607633590698242f,0.37131720781326293945f, +0.92387950420379638672f,0.38268342614173889160f,0.91911387443542480469f, +0.39399203658103942871f,0.91420978307723999023f,0.40524131059646606445f, +0.90916800498962402344f,0.41642954945564270020f,0.90398931503295898438f, +0.42755508422851562500f,0.89867448806762695312f,0.43861624598503112793f, +0.89322429895401000977f,0.44961133599281311035f,0.88763964176177978516f, +0.46053871512413024902f,0.88192129135131835938f,0.47139674425125122070f, +0.87607008218765258789f,0.48218378424644470215f,0.87008696794509887695f, +0.49289819598197937012f,0.86397284269332885742f,0.50353837013244628906f, +0.85772860050201416016f,0.51410275697708129883f,0.85135519504547119141f, +0.52458965778350830078f,0.84485357999801635742f,0.53499764204025268555f, +0.83822470903396606445f,0.54532498121261596680f,0.83146959543228149414f, +0.55557024478912353516f,0.82458931207656860352f,0.56573182344436645508f, +0.81758481264114379883f,0.57580816745758056641f,0.81045717000961303711f, +0.58579784631729125977f,0.80320751667022705078f,0.59569931030273437500f, +0.79583692550659179688f,0.60551106929779052734f,0.78834640979766845703f, +0.61523157358169555664f,0.78073722124099731445f,0.62485951185226440430f, +0.77301043272018432617f,0.63439327478408813477f,0.76516723632812500000f, +0.64383155107498168945f,0.75720882415771484375f,0.65317285060882568359f, +0.74913638830184936523f,0.66241580247879028320f,0.74095112085342407227f, +0.67155897617340087891f,0.73265427350997924805f,0.68060100078582763672f, +0.72424709796905517578f,0.68954056501388549805f,0.71573084592819213867f, +0.69837623834609985352f,0.70710676908493041992f,0.70710676908493041992f, +0.69837623834609985352f,0.71573084592819213867f,0.68954056501388549805f, +0.72424709796905517578f,0.68060100078582763672f,0.73265427350997924805f, +0.67155897617340087891f,0.74095112085342407227f,0.66241580247879028320f, +0.74913638830184936523f,0.65317285060882568359f,0.75720882415771484375f, +0.64383155107498168945f,0.76516723632812500000f,0.63439327478408813477f, +0.77301043272018432617f,0.62485951185226440430f,0.78073722124099731445f, +0.61523157358169555664f,0.78834640979766845703f,0.60551106929779052734f, +0.79583692550659179688f,0.59569931030273437500f,0.80320751667022705078f, +0.58579784631729125977f,0.81045717000961303711f,0.57580816745758056641f, +0.81758481264114379883f,0.56573182344436645508f,0.82458931207656860352f, +0.55557024478912353516f,0.83146959543228149414f,0.54532498121261596680f, +0.83822470903396606445f,0.53499764204025268555f,0.84485357999801635742f, +0.52458965778350830078f,0.85135519504547119141f,0.51410275697708129883f, +0.85772860050201416016f,0.50353837013244628906f,0.86397284269332885742f, +0.49289819598197937012f,0.87008696794509887695f,0.48218378424644470215f, +0.87607008218765258789f,0.47139674425125122070f,0.88192129135131835938f, +0.46053871512413024902f,0.88763964176177978516f,0.44961133599281311035f, +0.89322429895401000977f,0.43861624598503112793f,0.89867448806762695312f, +0.42755508422851562500f,0.90398931503295898438f,0.41642954945564270020f, +0.90916800498962402344f,0.40524131059646606445f,0.91420978307723999023f, +0.39399203658103942871f,0.91911387443542480469f,0.38268342614173889160f, +0.92387950420379638672f,0.37131720781326293945f,0.92850607633590698242f, +0.35989505052566528320f,0.93299281597137451172f,0.34841868281364440918f, +0.93733900785446166992f,0.33688986301422119141f,0.94154405593872070312f, +0.32531028985977172852f,0.94560730457305908203f,0.31368175148963928223f, +0.94952815771102905273f,0.30200594663619995117f,0.95330601930618286133f, +0.29028466343879699707f,0.95694035291671752930f,0.27851969003677368164f, +0.96043050289154052734f,0.26671275496482849121f,0.96377605199813842773f, +0.25486564636230468750f,0.96697646379470825195f,0.24298018217086791992f, +0.97003126144409179688f,0.23105810582637786865f,0.97293996810913085938f, +0.21910123527050018311f,0.97570210695266723633f,0.20711137354373931885f, +0.97831737995147705078f,0.19509032368659973145f,0.98078525066375732422f, +0.18303988873958587646f,0.98310548067092895508f,0.17096188664436340332f, +0.98527765274047851562f,0.15885815024375915527f,0.98730140924453735352f, +0.14673046767711639404f,0.98917651176452636719f,0.13458070158958435059f, +0.99090266227722167969f,0.12241067737340927124f,0.99247956275939941406f, +0.11022220551967620850f,0.99390697479248046875f,0.09801714122295379639f, +0.99518471956253051758f,0.08579730987548828125f,0.99631261825561523438f, +0.07356456667184829712f,0.99729043245315551758f,0.06132073700428009033f, +0.99811810255050659180f,0.04906767606735229492f,0.99879544973373413086f, +0.03680722415447235107f,0.99932235479354858398f,0.02454122900962829590f, +0.99969881772994995117f,0.01227153837680816650f,0.99992471933364868164f, +0.00000000000000006123f,1.00000000000000000000f,-0.01227153837680816650f, +0.99992471933364868164f,-0.02454122900962829590f,0.99969881772994995117f, +-0.03680722415447235107f,0.99932235479354858398f,-0.04906767606735229492f, +0.99879544973373413086f,-0.06132073700428009033f,0.99811810255050659180f, +-0.07356456667184829712f,0.99729043245315551758f,-0.08579730987548828125f, +0.99631261825561523438f,-0.09801714122295379639f,0.99518471956253051758f, +-0.11022220551967620850f,0.99390697479248046875f,-0.12241067737340927124f, +0.99247956275939941406f,-0.13458070158958435059f,0.99090266227722167969f, +-0.14673046767711639404f,0.98917651176452636719f,-0.15885815024375915527f, +0.98730140924453735352f,-0.17096188664436340332f,0.98527765274047851562f, +-0.18303988873958587646f,0.98310548067092895508f,-0.19509032368659973145f, +0.98078525066375732422f,-0.20711137354373931885f,0.97831737995147705078f, +-0.21910123527050018311f,0.97570210695266723633f,-0.23105810582637786865f, +0.97293996810913085938f,-0.24298018217086791992f,0.97003126144409179688f, +-0.25486564636230468750f,0.96697646379470825195f,-0.26671275496482849121f, +0.96377605199813842773f,-0.27851969003677368164f,0.96043050289154052734f, +-0.29028466343879699707f,0.95694035291671752930f,-0.30200594663619995117f, +0.95330601930618286133f,-0.31368175148963928223f,0.94952815771102905273f, +-0.32531028985977172852f,0.94560730457305908203f,-0.33688986301422119141f, +0.94154405593872070312f,-0.34841868281364440918f,0.93733900785446166992f, +-0.35989505052566528320f,0.93299281597137451172f,-0.37131720781326293945f, +0.92850607633590698242f,-0.38268342614173889160f,0.92387950420379638672f, +-0.39399203658103942871f,0.91911387443542480469f,-0.40524131059646606445f, +0.91420978307723999023f,-0.41642954945564270020f,0.90916800498962402344f, +-0.42755508422851562500f,0.90398931503295898438f,-0.43861624598503112793f, +0.89867448806762695312f,-0.44961133599281311035f,0.89322429895401000977f, +-0.46053871512413024902f,0.88763964176177978516f,-0.47139674425125122070f, +0.88192129135131835938f,-0.48218378424644470215f,0.87607008218765258789f, +-0.49289819598197937012f,0.87008696794509887695f,-0.50353837013244628906f, +0.86397284269332885742f,-0.51410275697708129883f,0.85772860050201416016f, +-0.52458965778350830078f,0.85135519504547119141f,-0.53499764204025268555f, +0.84485357999801635742f,-0.54532498121261596680f,0.83822470903396606445f, +-0.55557024478912353516f,0.83146959543228149414f,-0.56573182344436645508f, +0.82458931207656860352f,-0.57580816745758056641f,0.81758481264114379883f, +-0.58579784631729125977f,0.81045717000961303711f,-0.59569931030273437500f, +0.80320751667022705078f,-0.60551106929779052734f,0.79583692550659179688f, +-0.61523157358169555664f,0.78834640979766845703f,-0.62485951185226440430f, +0.78073722124099731445f,-0.63439327478408813477f,0.77301043272018432617f, +-0.64383155107498168945f,0.76516723632812500000f,-0.65317285060882568359f, +0.75720882415771484375f,-0.66241580247879028320f,0.74913638830184936523f, +-0.67155897617340087891f,0.74095112085342407227f,-0.68060100078582763672f, +0.73265427350997924805f,-0.68954056501388549805f,0.72424709796905517578f, +-0.69837623834609985352f,0.71573084592819213867f,-0.70710676908493041992f, +0.70710676908493041992f,-0.71573084592819213867f,0.69837623834609985352f, +-0.72424709796905517578f,0.68954056501388549805f,-0.73265427350997924805f, +0.68060100078582763672f,-0.74095112085342407227f,0.67155897617340087891f, +-0.74913638830184936523f,0.66241580247879028320f,-0.75720882415771484375f, +0.65317285060882568359f,-0.76516723632812500000f,0.64383155107498168945f, +-0.77301043272018432617f,0.63439327478408813477f,-0.78073722124099731445f, +0.62485951185226440430f,-0.78834640979766845703f,0.61523157358169555664f, +-0.79583692550659179688f,0.60551106929779052734f,-0.80320751667022705078f, +0.59569931030273437500f,-0.81045717000961303711f,0.58579784631729125977f, +-0.81758481264114379883f,0.57580816745758056641f,-0.82458931207656860352f, +0.56573182344436645508f,-0.83146959543228149414f,0.55557024478912353516f, +-0.83822470903396606445f,0.54532498121261596680f,-0.84485357999801635742f, +0.53499764204025268555f,-0.85135519504547119141f,0.52458965778350830078f, +-0.85772860050201416016f,0.51410275697708129883f,-0.86397284269332885742f, +0.50353837013244628906f,-0.87008696794509887695f,0.49289819598197937012f, +-0.87607008218765258789f,0.48218378424644470215f,-0.88192129135131835938f, +0.47139674425125122070f,-0.88763964176177978516f,0.46053871512413024902f, +-0.89322429895401000977f,0.44961133599281311035f,-0.89867448806762695312f, +0.43861624598503112793f,-0.90398931503295898438f,0.42755508422851562500f, +-0.90916800498962402344f,0.41642954945564270020f,-0.91420978307723999023f, +0.40524131059646606445f,-0.91911387443542480469f,0.39399203658103942871f, +-0.92387950420379638672f,0.38268342614173889160f,-0.92850607633590698242f, +0.37131720781326293945f,-0.93299281597137451172f,0.35989505052566528320f, +-0.93733900785446166992f,0.34841868281364440918f,-0.94154405593872070312f, +0.33688986301422119141f,-0.94560730457305908203f,0.32531028985977172852f, +-0.94952815771102905273f,0.31368175148963928223f,-0.95330601930618286133f, +0.30200594663619995117f,-0.95694035291671752930f,0.29028466343879699707f, +-0.96043050289154052734f,0.27851969003677368164f,-0.96377605199813842773f, +0.26671275496482849121f,-0.96697646379470825195f,0.25486564636230468750f, +-0.97003126144409179688f,0.24298018217086791992f,-0.97293996810913085938f, +0.23105810582637786865f,-0.97570210695266723633f,0.21910123527050018311f, +-0.97831737995147705078f,0.20711137354373931885f,-0.98078525066375732422f, +0.19509032368659973145f,-0.98310548067092895508f,0.18303988873958587646f, +-0.98527765274047851562f,0.17096188664436340332f,-0.98730140924453735352f, +0.15885815024375915527f,-0.98917651176452636719f,0.14673046767711639404f, +-0.99090266227722167969f,0.13458070158958435059f,-0.99247956275939941406f, +0.12241067737340927124f,-0.99390697479248046875f,0.11022220551967620850f, +-0.99518471956253051758f,0.09801714122295379639f,-0.99631261825561523438f, +0.08579730987548828125f,-0.99729043245315551758f,0.07356456667184829712f, +-0.99811810255050659180f,0.06132073700428009033f,-0.99879544973373413086f, +0.04906767606735229492f,-0.99932235479354858398f,0.03680722415447235107f, +-0.99969881772994995117f,0.02454122900962829590f,-0.99992471933364868164f, +0.01227153837680816650f,1.00000000000000000000f,0.00000000000000000000f, +0.99879544973373413086f,0.04906767606735229492f,0.99518471956253051758f, +0.09801714122295379639f,0.98917651176452636719f,0.14673046767711639404f, +0.98078525066375732422f,0.19509032368659973145f,0.97003126144409179688f, +0.24298018217086791992f,0.95694035291671752930f,0.29028466343879699707f, +0.94154405593872070312f,0.33688986301422119141f,0.92387950420379638672f, +0.38268342614173889160f,0.90398931503295898438f,0.42755508422851562500f, +0.88192129135131835938f,0.47139674425125122070f,0.85772860050201416016f, +0.51410275697708129883f,0.83146959543228149414f,0.55557024478912353516f, +0.80320751667022705078f,0.59569931030273437500f,0.77301043272018432617f, +0.63439327478408813477f,0.74095112085342407227f,0.67155897617340087891f, +0.70710676908493041992f,0.70710676908493041992f,0.67155897617340087891f, +0.74095112085342407227f,0.63439327478408813477f,0.77301043272018432617f, +0.59569931030273437500f,0.80320751667022705078f,0.55557024478912353516f, +0.83146959543228149414f,0.51410275697708129883f,0.85772860050201416016f, +0.47139674425125122070f,0.88192129135131835938f,0.42755508422851562500f, +0.90398931503295898438f,0.38268342614173889160f,0.92387950420379638672f, +0.33688986301422119141f,0.94154405593872070312f,0.29028466343879699707f, +0.95694035291671752930f,0.24298018217086791992f,0.97003126144409179688f, +0.19509032368659973145f,0.98078525066375732422f,0.14673046767711639404f, +0.98917651176452636719f,0.09801714122295379639f,0.99518471956253051758f, +0.04906767606735229492f,0.99879544973373413086f,0.00000000000000006123f, +1.00000000000000000000f,-0.04906767606735229492f,0.99879544973373413086f, +-0.09801714122295379639f,0.99518471956253051758f,-0.14673046767711639404f, +0.98917651176452636719f,-0.19509032368659973145f,0.98078525066375732422f, +-0.24298018217086791992f,0.97003126144409179688f,-0.29028466343879699707f, +0.95694035291671752930f,-0.33688986301422119141f,0.94154405593872070312f, +-0.38268342614173889160f,0.92387950420379638672f,-0.42755508422851562500f, +0.90398931503295898438f,-0.47139674425125122070f,0.88192129135131835938f, +-0.51410275697708129883f,0.85772860050201416016f,-0.55557024478912353516f, +0.83146959543228149414f,-0.59569931030273437500f,0.80320751667022705078f, +-0.63439327478408813477f,0.77301043272018432617f,-0.67155897617340087891f, +0.74095112085342407227f,-0.70710676908493041992f,0.70710676908493041992f, +-0.74095112085342407227f,0.67155897617340087891f,-0.77301043272018432617f, +0.63439327478408813477f,-0.80320751667022705078f,0.59569931030273437500f, +-0.83146959543228149414f,0.55557024478912353516f,-0.85772860050201416016f, +0.51410275697708129883f,-0.88192129135131835938f,0.47139674425125122070f, +-0.90398931503295898438f,0.42755508422851562500f,-0.92387950420379638672f, +0.38268342614173889160f,-0.94154405593872070312f,0.33688986301422119141f, +-0.95694035291671752930f,0.29028466343879699707f,-0.97003126144409179688f, +0.24298018217086791992f,-0.98078525066375732422f,0.19509032368659973145f, +-0.98917651176452636719f,0.14673046767711639404f,-0.99518471956253051758f, +0.09801714122295379639f,-0.99879544973373413086f,0.04906767606735229492f, +1.00000000000000000000f,0.00000000000000000000f,0.98078525066375732422f, +0.19509032368659973145f,0.92387950420379638672f,0.38268342614173889160f, +0.83146959543228149414f,0.55557024478912353516f,0.70710676908493041992f, +0.70710676908493041992f,0.55557024478912353516f,0.83146959543228149414f, +0.38268342614173889160f,0.92387950420379638672f,0.19509032368659973145f, +0.98078525066375732422f,0.00000000000000006123f,1.00000000000000000000f, +-0.19509032368659973145f,0.98078525066375732422f,-0.38268342614173889160f, +0.92387950420379638672f,-0.55557024478912353516f,0.83146959543228149414f, +-0.70710676908493041992f,0.70710676908493041992f,-0.83146959543228149414f, +0.55557024478912353516f,-0.92387950420379638672f,0.38268342614173889160f, +-0.98078525066375732422f,0.19509032368659973145f,1.00000000000000000000f, +0.00000000000000000000f,0.70710676908493041992f,0.70710676908493041992f, +0.00000000000000006123f,1.00000000000000000000f,-0.70710676908493041992f, +0.70710676908493041992f,}; + +float32_t rearranged_twiddle_stride3_4096_f32[2728]={ +1.00000000000000000000f,0.00000000000000000000f,0.99998939037322998047f, +0.00460192607715725899f,0.99995762109756469727f,0.00920375436544418335f, +0.99990469217300415039f,0.01380538847297430038f,0.99983060359954833984f, +0.01840673014521598816f,0.99973529577255249023f,0.02300768159329891205f, +0.99961882829666137695f,0.02760814502835273743f,0.99948120117187500000f, +0.03220802545547485352f,0.99932235479354858398f,0.03680722415447235107f, +0.99914240837097167969f,0.04140564054250717163f,0.99894130229949951172f, +0.04600318148732185364f,0.99871903657913208008f,0.05059975013136863708f, +0.99847555160522460938f,0.05519524589180946350f,0.99821102619171142578f, +0.05978957191109657288f,0.99792528152465820312f,0.06438262760639190674f, +0.99761843681335449219f,0.06897433102130889893f,0.99729043245315551758f, +0.07356456667184829712f,0.99694132804870605469f,0.07815324515104293823f, +0.99657112360000610352f,0.08274026215076446533f,0.99617981910705566406f, +0.08732553571462631226f,0.99576741456985473633f,0.09190895408391952515f, +0.99533390998840332031f,0.09649042785167694092f,0.99487930536270141602f, +0.10106986016035079956f,0.99440366029739379883f,0.10564715415239334106f, +0.99390697479248046875f,0.11022220551967620850f,0.99338918924331665039f, +0.11479492485523223877f,0.99285042285919189453f,0.11936521530151367188f, +0.99229061603546142578f,0.12393297255039215088f,0.99170976877212524414f, +0.12849810719490051270f,0.99110794067382812500f,0.13306052982807159424f, +0.99048507213592529297f,0.13762012124061584473f,0.98984128236770629883f, +0.14217680692672729492f,0.98917651176452636719f,0.14673046767711639404f, +0.98849081993103027344f,0.15128104388713836670f,0.98778414726257324219f, +0.15582840144634246826f,0.98705655336380004883f,0.16037245094776153564f, +0.98630809783935546875f,0.16491311788558959961f,0.98553872108459472656f, +0.16945029795169830322f,0.98474848270416259766f,0.17398387193679809570f, +0.98393744230270385742f,0.17851376533508300781f,0.98310548067092895508f, +0.18303988873958587646f,0.98225271701812744141f,0.18756212294101715088f, +0.98137921094894409180f,0.19208039343357086182f,0.98048484325408935547f, +0.19659459590911865234f,0.97956979274749755859f,0.20110464096069335938f, +0.97863394021987915039f,0.20561040937900543213f,0.97767734527587890625f, +0.21011184155941009521f,0.97670006752014160156f,0.21460881829261779785f, +0.97570210695266723633f,0.21910123527050018311f,0.97468352317810058594f, +0.22358903288841247559f,0.97364425659179687500f,0.22807207703590393066f, +0.97258436679840087891f,0.23255030810832977295f,0.97150391340255737305f, +0.23702360689640045166f,0.97040283679962158203f,0.24149188399314880371f, +0.96928125619888305664f,0.24595504999160766602f,0.96813911199569702148f, +0.25041300058364868164f,0.96697646379470825195f,0.25486564636230468750f, +0.96579337120056152344f,0.25931292772293090820f,0.96458977460861206055f, +0.26375466585159301758f,0.96336579322814941406f,0.26819086074829101562f, +0.96212142705917358398f,0.27262136340141296387f,0.96085661649703979492f, +0.27704608440399169922f,0.95957154035568237305f,0.28146493434906005859f, +0.95826607942581176758f,0.28587782382965087891f,0.95694035291671752930f, +0.29028466343879699707f,0.95559436082839965820f,0.29468536376953125000f, +0.95422810316085815430f,0.29907983541488647461f,0.95284163951873779297f, +0.30346795916557312012f,0.95143502950668334961f,0.30784964561462402344f, +0.95000827312469482422f,0.31222480535507202148f,0.94856137037277221680f, +0.31659337878227233887f,0.94709438085556030273f,0.32095524668693542480f, +0.94560730457305908203f,0.32531028985977172852f,0.94410026073455810547f, +0.32965844869613647461f,0.94257318973541259766f,0.33399966359138488770f, +0.94102615118026733398f,0.33833375573158264160f,0.93945920467376708984f, +0.34266072511672973633f,0.93787235021591186523f,0.34698042273521423340f, +0.93626564741134643555f,0.35129275918006896973f,0.93463915586471557617f, +0.35559767484664916992f,0.93299281597137451172f,0.35989505052566528320f, +0.93132668733596801758f,0.36418479681015014648f,0.92964088916778564453f, +0.36846682429313659668f,0.92793542146682739258f,0.37274107336997985840f, +0.92621022462844848633f,0.37700742483139038086f,0.92446547746658325195f, +0.38126575946807861328f,0.92270112037658691406f,0.38551604747772216797f, +0.92091721296310424805f,0.38975816965103149414f,0.91911387443542480469f, +0.39399203658103942871f,0.91729098558425903320f,0.39821755886077880859f, +0.91544872522354125977f,0.40243464708328247070f,0.91358703374862670898f, +0.40664321184158325195f,0.91170603036880493164f,0.41084316372871398926f, +0.90980571508407592773f,0.41503441333770751953f,0.90788608789443969727f, +0.41921690106391906738f,0.90594726800918579102f,0.42339047789573669434f, +0.90398931503295898438f,0.42755508422851562500f,0.90201216936111450195f, +0.43171066045761108398f,0.90001589059829711914f,0.43585708737373352051f, +0.89800059795379638672f,0.43999427556991577148f,0.89596623182296752930f, +0.44412213563919067383f,0.89391297101974487305f,0.44824060797691345215f, +0.89184069633483886719f,0.45234957337379455566f,0.88974958658218383789f, +0.45644897222518920898f,0.88763964176177978516f,0.46053871512413024902f, +0.88551086187362670898f,0.46461868286132812500f,0.88336336612701416016f, +0.46868881583213806152f,0.88119709491729736328f,0.47274902462959289551f, +0.87901222705841064453f,0.47679921984672546387f,0.87680870294570922852f, +0.48083934187889099121f,0.87458664178848266602f,0.48486924171447753906f, +0.87234604358673095703f,0.48888888955116271973f,0.87008696794509887695f, +0.49289819598197937012f,0.86780947446823120117f,0.49689704179763793945f, +0.86551362276077270508f,0.50088536739349365234f,0.86319941282272338867f, +0.50486308336257934570f,0.86086696386337280273f,0.50883013010025024414f, +0.85851621627807617188f,0.51278638839721679688f,0.85614734888076782227f, +0.51673179864883422852f,0.85376030206680297852f,0.52066624164581298828f, +0.85135519504547119141f,0.52458965778350830078f,0.84893202781677246094f, +0.52850198745727539062f,0.84649091958999633789f,0.53240311145782470703f, +0.84403187036514282227f,0.53629297018051147461f,0.84155499935150146484f, +0.54017144441604614258f,0.83906024694442749023f,0.54403853416442871094f, +0.83654773235321044922f,0.54789406061172485352f,0.83401751518249511719f, +0.55173796415328979492f,0.83146959543228149414f,0.55557024478912353516f, +0.82890409231185913086f,0.55939072370529174805f,0.82632106542587280273f, +0.56319934129714965820f,0.82372051477432250977f,0.56699603796005249023f, +0.82110249996185302734f,0.57078075408935546875f,0.81846714019775390625f, +0.57455337047576904297f,0.81581443548202514648f,0.57831376791000366211f, +0.81314438581466674805f,0.58206200599670410156f,0.81045717000961303711f, +0.58579784631729125977f,0.80775284767150878906f,0.58952128887176513672f, +0.80503135919570922852f,0.59323227405548095703f,0.80229282379150390625f, +0.59693068265914916992f,0.79953724145889282227f,0.60061645507812500000f, +0.79676479101181030273f,0.60428953170776367188f,0.79397547245025634766f, +0.60794979333877563477f,0.79116934537887573242f,0.61159718036651611328f, +0.78834640979766845703f,0.61523157358169555664f,0.78550684452056884766f, +0.61885297298431396484f,0.78265058994293212891f,0.62246125936508178711f, +0.77977776527404785156f,0.62605637311935424805f,0.77688848972320556641f, +0.62963825464248657227f,0.77398270368576049805f,0.63320678472518920898f, +0.77106052637100219727f,0.63676184415817260742f,0.76812201738357543945f, +0.64030349254608154297f,0.76516723632812500000f,0.64383155107498168945f, +0.76219630241394042969f,0.64734596014022827148f,0.75920921564102172852f, +0.65084666013717651367f,0.75620597600936889648f,0.65433359146118164062f, +0.75318682193756103516f,0.65780669450759887695f,0.75015163421630859375f, +0.66126585006713867188f,0.74710059165954589844f,0.66471099853515625000f, +0.74403375387191772461f,0.66814202070236206055f,0.74095112085342407227f, +0.67155897617340087891f,0.73785281181335449219f,0.67496162652969360352f, +0.73473888635635375977f,0.67835003137588500977f,0.73160940408706665039f, +0.68172407150268554688f,0.72846436500549316406f,0.68508368730545043945f, +0.72530394792556762695f,0.68842875957489013672f,0.72212821245193481445f, +0.69175922870635986328f,0.71893709897994995117f,0.69507509469985961914f, +0.71573084592819213867f,0.69837623834609985352f,0.71250939369201660156f, +0.70166260004043579102f,0.70927280187606811523f,0.70493406057357788086f, +0.70602124929428100586f,0.70819061994552612305f,0.70275473594665527344f, +0.71143221855163574219f,0.69947332143783569336f,0.71465867757797241211f, +0.69617712497711181641f,0.71787005662918090820f,0.69286614656448364258f, +0.72106617689132690430f,0.68954056501388549805f,0.72424709796905517578f, +0.68620032072067260742f,0.72741264104843139648f,0.68284553289413452148f, +0.73056274652481079102f,0.67947632074356079102f,0.73369741439819335938f, +0.67609268426895141602f,0.73681658506393432617f,0.67269474267959594727f, +0.73992007970809936523f,0.66928261518478393555f,0.74300795793533325195f, +0.66585624217987060547f,0.74608010053634643555f,0.66241580247879028320f, +0.74913638830184936523f,0.65896129608154296875f,0.75217682123184204102f, +0.65549284219741821289f,0.75520139932632446289f,0.65201056003570556641f, +0.75820988416671752930f,0.64851438999176025391f,0.76120239496231079102f, +0.64500451087951660156f,0.76417875289916992188f,0.64148104190826416016f, +0.76713889837265014648f,0.63794392347335815430f,0.77008283138275146484f, +0.63439327478408813477f,0.77301043272018432617f,0.63082921504974365234f, +0.77592170238494873047f,0.62725180387496948242f,0.77881652116775512695f, +0.62366110086441040039f,0.78169482946395874023f,0.62005722522735595703f, +0.78455656766891479492f,0.61644017696380615234f,0.78740173578262329102f, +0.61281007528305053711f,0.79023021459579467773f,0.60916703939437866211f, +0.79304194450378417969f,0.60551106929779052734f,0.79583692550659179688f, +0.60184222459793090820f,0.79861497879028320312f,0.59816068410873413086f, +0.80137616395950317383f,0.59446650743484497070f,0.80412036180496215820f, +0.59075969457626342773f,0.80684757232666015625f,0.58704036474227905273f, +0.80955761671066284180f,0.58330863714218139648f,0.81225061416625976562f, +0.57956457138061523438f,0.81492632627487182617f,0.57580816745758056641f, +0.81758481264114379883f,0.57203960418701171875f,0.82022595405578613281f, +0.56825894117355346680f,0.82284981012344360352f,0.56446623802185058594f, +0.82545614242553710938f,0.56066155433654785156f,0.82804507017135620117f, +0.55684500932693481445f,0.83061641454696655273f,0.55301672220230102539f, +0.83317017555236816406f,0.54917663335800170898f,0.83570629358291625977f, +0.54532498121261596680f,0.83822470903396606445f,0.54146176576614379883f, +0.84072536230087280273f,0.53758704662322998047f,0.84320825338363647461f, +0.53370100259780883789f,0.84567326307296752930f,0.52980363368988037109f, +0.84812033176422119141f,0.52589499950408935547f,0.85054945945739746094f, +0.52197527885437011719f,0.85296058654785156250f,0.51804453134536743164f, +0.85535365343093872070f,0.51410275697708129883f,0.85772860050201416016f, +0.51015007495880126953f,0.86008536815643310547f,0.50618666410446166992f, +0.86242395639419555664f,0.50221246480941772461f,0.86474424600601196289f, +0.49822765588760375977f,0.86704623699188232422f,0.49423229694366455078f, +0.86932986974716186523f,0.49022647738456726074f,0.87159508466720581055f, +0.48621028661727905273f,0.87384182214736938477f,0.48218378424644470215f, +0.87607008218765258789f,0.47814705967903137207f,0.87827980518341064453f, +0.47410020232200622559f,0.88047087192535400391f,0.47004333138465881348f, +0.88264334201812744141f,0.46597650647163391113f,0.88479709625244140625f, +0.46189978718757629395f,0.88693213462829589844f,0.45781329274177551270f, +0.88904833793640136719f,0.45371711254119873047f,0.89114576578140258789f, +0.44961133599281311035f,0.89322429895401000977f,0.44549602270126342773f, +0.89528393745422363281f,0.44137126207351684570f,0.89732456207275390625f, +0.43723717331886291504f,0.89934623241424560547f,0.43309381604194641113f, +0.90134882926940917969f,0.42894127964973449707f,0.90333235263824462891f, +0.42477968335151672363f,0.90529674291610717773f,0.42060908675193786621f, +0.90724200010299682617f,0.41642954945564270020f,0.90916800498962402344f, +0.41224122047424316406f,0.91107475757598876953f,0.40804415941238403320f, +0.91296219825744628906f,0.40383845567703247070f,0.91483032703399658203f, +0.39962419867515563965f,0.91667908430099487305f,0.39540147781372070312f, +0.91850841045379638672f,0.39117038249969482422f,0.92031830549240112305f, +0.38693100214004516602f,0.92210865020751953125f,0.38268342614173889160f, +0.92387950420379638672f,0.37842774391174316406f,0.92563080787658691406f, +0.37416407465934753418f,0.92736250162124633789f,0.36989244818687438965f, +0.92907458543777465820f,0.36561298370361328125f,0.93076694011688232422f, +0.36132580041885375977f,0.93243962526321411133f,0.35703095793724060059f, +0.93409252166748046875f,0.35272854566574096680f,0.93572568893432617188f, +0.34841868281364440918f,0.93733900785446166992f,0.34410142898559570312f, +0.93893247842788696289f,0.33977687358856201172f,0.94050604104995727539f, +0.33544513583183288574f,0.94205975532531738281f,0.33110630512237548828f, +0.94359344244003295898f,0.32676044106483459473f,0.94510722160339355469f, +0.32240769267082214355f,0.94660091400146484375f,0.31804808974266052246f, +0.94807457923889160156f,0.31368175148963928223f,0.94952815771102905273f, +0.30930876731872558594f,0.95096164941787719727f,0.30492922663688659668f, +0.95237499475479125977f,0.30054324865341186523f,0.95376819372177124023f, +0.29615089297294616699f,0.95514118671417236328f,0.29175224900245666504f, +0.95649391412734985352f,0.28734746575355529785f,0.95782643556594848633f, +0.28293657302856445312f,0.95913863182067871094f,0.27851969003677368164f, +0.96043050289154052734f,0.27409690618515014648f,0.96170204877853393555f, +0.26966831088066101074f,0.96295326948165893555f,0.26523402333259582520f, +0.96418404579162597656f,0.26079410314559936523f,0.96539443731307983398f, +0.25634866952896118164f,0.96658438444137573242f,0.25189781188964843750f, +0.96775382757186889648f,0.24744161963462829590f,0.96890282630920410156f, +0.24298018217086791992f,0.97003126144409179688f,0.23851358890533447266f, +0.97113913297653198242f,0.23404195904731750488f,0.97222650051116943359f, +0.22956536710262298584f,0.97329324483871459961f,0.22508391737937927246f, +0.97433936595916748047f,0.22059768438339233398f,0.97536486387252807617f, +0.21610680222511291504f,0.97636973857879638672f,0.21161133050918579102f, +0.97735387086868286133f,0.20711137354373931885f,0.97831737995147705078f, +0.20260703563690185547f,0.97926014661788940430f,0.19809840619564056396f, +0.98018211126327514648f,0.19358558952808380127f,0.98108339309692382812f, +0.18906866014003753662f,0.98196387290954589844f,0.18454773724079132080f, +0.98282355070114135742f,0.18002289533615112305f,0.98366242647171020508f, +0.17549425363540649414f,0.98448044061660766602f,0.17096188664436340332f, +0.98527765274047851562f,0.16642589867115020752f,0.98605394363403320312f, +0.16188639402389526367f,0.98680937290191650391f,0.15734346210956573486f, +0.98754394054412841797f,0.15279719233512878418f,0.98825758695602416992f, +0.14824767410755157471f,0.98895025253295898438f,0.14369502663612365723f, +0.98962199687957763672f,0.13913933932781219482f,0.99027281999588012695f, +0.13458070158958435059f,0.99090266227722167969f,0.13001921772956848145f, +0.99151146411895751953f,0.12545497715473175049f,0.99209928512573242188f, +0.12088808417320251465f,0.99266612529754638672f,0.11631862819194793701f, +0.99321192502975463867f,0.11174671351909637451f,0.99373674392700195312f, +0.10717242211103439331f,0.99424046277999877930f,0.10259586572647094727f, +0.99472314119338989258f,0.09801714122295379639f,0.99518471956253051758f, +0.09343633800745010376f,0.99562525749206542969f,0.08885355293750762939f, +0.99604469537734985352f,0.08426889032125473022f,0.99644303321838378906f, +0.07968243956565856934f,0.99682027101516723633f,0.07509429752826690674f, +0.99717640876770019531f,0.07050457596778869629f,0.99751144647598266602f, +0.06591334939002990723f,0.99782532453536987305f,0.06132073700428009033f, +0.99811810255050659180f,0.05672682076692581177f,0.99838972091674804688f, +0.05213170498609542847f,0.99864023923873901367f,0.04753548279404640198f, +0.99886953830718994141f,0.04293825849890708923f,0.99907773733139038086f, +0.03834012150764465332f,0.99926477670669555664f,0.03374117240309715271f, +0.99943059682846069336f,0.02914150804281234741f,0.99957531690597534180f, +0.02454122900962829590f,0.99969881772994995117f,0.01994042843580245972f, +0.99980115890502929688f,0.01533920597285032272f,0.99988234043121337891f, +0.01073765940964221954f,0.99994236230850219727f,0.00613588467240333557f, +0.99998116493225097656f,0.00153398013208061457f,0.99999880790710449219f, +-0.00306795677170157433f,0.99999529123306274414f,-0.00766982883214950562f, +0.99997061491012573242f,-0.01227153837680816650f,0.99992471933364868164f, +-0.01687298715114593506f,0.99985766410827636719f,-0.02147408016026020050f, +0.99976938962936401367f,-0.02607471868395805359f,0.99966001510620117188f, +-0.03067480400204658508f,0.99952942132949829102f,-0.03527423739433288574f, +0.99937766790390014648f,-0.03987292572855949402f,0.99920475482940673828f, +-0.04447077214717864990f,0.99901068210601806641f,-0.04906767606735229492f, +0.99879544973373413086f,-0.05366353690624237061f,0.99855905771255493164f, +-0.05825826525688171387f,0.99830156564712524414f,-0.06285175681114196777f, +0.99802285432815551758f,-0.06744392216205596924f,0.99772304296493530273f, +-0.07203464955091476440f,0.99740213155746459961f,-0.07662386447191238403f, +0.99706006050109863281f,-0.08121144771575927734f,0.99669688940048217773f, +-0.08579730987548828125f,0.99631261825561523438f,-0.09038136154413223267f, +0.99590724706649780273f,-0.09496349841356277466f,0.99548077583312988281f, +-0.09954361617565155029f,0.99503320455551147461f,-0.10412163287401199341f, +0.99456459283828735352f,-0.10869744420051574707f,0.99407488107681274414f, +-0.11327095329761505127f,0.99356412887573242188f,-0.11784206330776214600f, +0.99303233623504638672f,-0.12241067737340927124f,0.99247956275939941406f, +-0.12697669863700866699f,0.99190568923950195312f,-0.13154003024101257324f, +0.99131083488464355469f,-0.13610057532787322998f,0.99069499969482421875f, +-0.14065824449062347412f,0.99005818367004394531f,-0.14521291851997375488f, +0.98940044641494750977f,-0.14976453781127929688f,0.98872166872024536133f, +-0.15431296825408935547f,0.98802202939987182617f,-0.15885815024375915527f, +0.98730140924453735352f,-0.16339994966983795166f,0.98655992746353149414f, +-0.16793829202651977539f,0.98579752445220947266f,-0.17247308790683746338f, +0.98501425981521606445f,-0.17700421810150146484f,0.98421007394790649414f, +-0.18153160810470581055f,0.98338508605957031250f,-0.18605515360832214355f, +0.98253929615020751953f,-0.19057475030422210693f,0.98167270421981811523f, +-0.19509032368659973145f,0.98078525066375732422f,-0.19960175454616546631f, +0.97987711429595947266f,-0.20410896837711334229f,0.97894817590713500977f, +-0.20861184597015380859f,0.97799849510192871094f,-0.21311031281948089600f, +0.97702813148498535156f,-0.21760427951812744141f,0.97603708505630493164f, +-0.22209362685680389404f,0.97502535581588745117f,-0.22657826542854309082f, +0.97399294376373291016f,-0.23105810582637786865f,0.97293996810913085938f, +-0.23553305864334106445f,0.97186630964279174805f,-0.24000301957130432129f, +0.97077214717864990234f,-0.24446789920330047607f,0.96965736150741577148f, +-0.24892760813236236572f,0.96852207183837890625f,-0.25338202714920043945f, +0.96736627817153930664f,-0.25783109664916992188f,0.96618998050689697266f, +-0.26227471232414245605f,0.96499323844909667969f,-0.26671275496482849121f, +0.96377605199813842773f,-0.27114516496658325195f,0.96253848075866699219f, +-0.27557182312011718750f,0.96128046512603759766f,-0.27999264001846313477f, +0.96000212430953979492f,-0.28440752625465393066f,0.95870345830917358398f, +-0.28881642222404479980f,0.95738452672958374023f,-0.29321914911270141602f, +0.95604526996612548828f,-0.29761570692062377930f,0.95468574762344360352f, +-0.30200594663619995117f,0.95330601930618286133f,-0.30638980865478515625f, +0.95190614461898803711f,-0.31076714396476745605f,0.95048606395721435547f, +-0.31513792276382446289f,0.94904589653015136719f,-0.31950202584266662598f, +0.94758558273315429688f,-0.32385936379432678223f,0.94610524177551269531f, +-0.32820984721183776855f,0.94460481405258178711f,-0.33255335688591003418f, +0.94308441877365112305f,-0.33688986301422119141f,0.94154405593872070312f, +-0.34121921658515930176f,0.93998372554779052734f,-0.34554132819175720215f, +0.93840354681015014648f,-0.34985613822937011719f,0.93680346012115478516f, +-0.35416352748870849609f,0.93518352508544921875f,-0.35846340656280517578f, +0.93354380130767822266f,-0.36275571584701538086f,0.93188428878784179688f, +-0.36704033613204956055f,0.93020504713058471680f,-0.37131720781326293945f, +0.92850607633590698242f,-0.37558618187904357910f,0.92678749561309814453f, +-0.37984719872474670410f,0.92504924535751342773f,-0.38410019874572753906f, +0.92329144477844238281f,-0.38834503293037414551f,0.92151403427124023438f, +-0.39258167147636413574f,0.91971713304519653320f,-0.39680999517440795898f, +0.91790080070495605469f,-0.40102988481521606445f,0.91606497764587402344f, +-0.40524131059646606445f,0.91420978307723999023f,-0.40944415330886840820f, +0.91233515739440917969f,-0.41363832354545593262f,0.91044127941131591797f, +-0.41782370209693908691f,0.90852808952331542969f,-0.42200025916099548340f, +0.90659570693969726562f,-0.42616787552833557129f,0.90464407205581665039f, +-0.43032649159431457520f,0.90267330408096313477f,-0.43447595834732055664f, +0.90068340301513671875f,-0.43861624598503112793f,0.89867448806762695312f, +-0.44274723529815673828f,0.89664649963378906250f,-0.44686883687973022461f, +0.89459949731826782227f,-0.45098099112510681152f,0.89253354072570800781f, +-0.45508357882499694824f,0.89044874906539916992f,-0.45917654037475585938f, +0.88834506273269653320f,-0.46325978636741638184f,0.88622254133224487305f, +-0.46733319759368896484f,0.88408124446868896484f,-0.47139674425125122070f, +0.88192129135131835938f,-0.47545027732849121094f,0.87974262237548828125f, +-0.47949376702308654785f,0.87754529714584350586f,-0.48352706432342529297f, +0.87532937526702880859f,-0.48755016922950744629f,0.87309497594833374023f, +-0.49156290292739868164f,0.87084203958511352539f,-0.49556526541709899902f, +0.86857068538665771484f,-0.49955710768699645996f,0.86628097295761108398f, +-0.50353837013244628906f,0.86397284269332885742f,-0.50750899314880371094f, +0.86164647340774536133f,-0.51146882772445678711f,0.85930180549621582031f, +-0.51541787385940551758f,0.85693895816802978516f,-0.51935601234436035156f, +0.85455799102783203125f,-0.52328312397003173828f,0.85215890407562255859f, +-0.52719914913177490234f,0.84974175691604614258f,-0.53110402822494506836f, +0.84730660915374755859f,-0.53499764204025268555f,0.84485357999801635742f, +-0.53887993097305297852f,0.84238260984420776367f,-0.54275077581405639648f, +0.83989381790161132812f,-0.54661017656326293945f,0.83738720417022705078f, +-0.55045795440673828125f,0.83486288785934448242f,-0.55429410934448242188f, +0.83232086896896362305f,-0.55811852216720581055f,0.82976120710372924805f, +-0.56193113327026367188f,0.82718402147293090820f,-0.56573182344436645508f, +0.82458931207656860352f,-0.56952053308486938477f,0.82197713851928710938f, +-0.57329714298248291016f,0.81934750080108642578f,-0.57706165313720703125f, +0.81670057773590087891f,-0.58081394433975219727f,0.81403630971908569336f, +-0.58455395698547363281f,0.81135487556457519531f,-0.58828157186508178711f, +0.80865615606307983398f,-0.59199666976928710938f,0.80594038963317871094f, +-0.59569931030273437500f,0.80320751667022705078f,-0.59938931465148925781f, +0.80045765638351440430f,-0.60306662321090698242f,0.79769086837768554688f, +-0.60673111677169799805f,0.79490715265274047852f,-0.61038279533386230469f, +0.79210656881332397461f,-0.61402153968811035156f,0.78928923606872558594f, +-0.61764729022979736328f,0.78645521402359008789f,-0.62125998735427856445f, +0.78360450267791748047f,-0.62485951185226440430f,0.78073722124099731445f, +-0.62844574451446533203f,0.77785342931747436523f,-0.63201874494552612305f, +0.77495312690734863281f,-0.63557833433151245117f,0.77203637361526489258f, +-0.63912445306777954102f,0.76910334825515747070f,-0.64265704154968261719f, +0.76615399122238159180f,-0.64617604017257690430f,0.76318842172622680664f, +-0.64968132972717285156f,0.76020669937133789062f,-0.65317285060882568359f, +0.75720882415771484375f,-0.65665054321289062500f,0.75419497489929199219f, +-0.66011434793472290039f,0.75116515159606933594f,-0.66356414556503295898f, +0.74811935424804687500f,-0.66699993610382080078f,0.74505776166915893555f, +-0.67042154073715209961f,0.74198043346405029297f,-0.67382901906967163086f, +0.73888731002807617188f,-0.67722219228744506836f,0.73577857017517089844f, +-0.68060100078582763672f,0.73265427350997924805f,-0.68396538496017456055f, +0.72951442003250122070f,-0.68731534481048583984f,0.72635912895202636719f, +-0.69065070152282714844f,0.72318845987319946289f,-0.69397145509719848633f, +0.72000253200531005859f,-0.69727748632431030273f,0.71680128574371337891f, +-0.70056879520416259766f,0.71358484029769897461f,-0.70384526252746582031f, +0.71035337448120117188f,-0.70710676908493041992f,0.70710676908493041992f, +-0.71035337448120117188f,0.70384526252746582031f,-0.71358484029769897461f, +0.70056879520416259766f,-0.71680128574371337891f,0.69727748632431030273f, +-0.72000253200531005859f,0.69397145509719848633f,-0.72318845987319946289f, +0.69065070152282714844f,-0.72635912895202636719f,0.68731534481048583984f, +-0.72951442003250122070f,0.68396538496017456055f,-0.73265427350997924805f, +0.68060100078582763672f,-0.73577857017517089844f,0.67722219228744506836f, +-0.73888731002807617188f,0.67382901906967163086f,-0.74198043346405029297f, +0.67042154073715209961f,-0.74505776166915893555f,0.66699993610382080078f, +-0.74811935424804687500f,0.66356414556503295898f,-0.75116515159606933594f, +0.66011434793472290039f,-0.75419497489929199219f,0.65665054321289062500f, +-0.75720882415771484375f,0.65317285060882568359f,-0.76020669937133789062f, +0.64968132972717285156f,-0.76318842172622680664f,0.64617604017257690430f, +-0.76615399122238159180f,0.64265704154968261719f,-0.76910334825515747070f, +0.63912445306777954102f,-0.77203637361526489258f,0.63557833433151245117f, +-0.77495312690734863281f,0.63201874494552612305f,-0.77785342931747436523f, +0.62844574451446533203f,-0.78073722124099731445f,0.62485951185226440430f, +-0.78360450267791748047f,0.62125998735427856445f,-0.78645521402359008789f, +0.61764729022979736328f,-0.78928923606872558594f,0.61402153968811035156f, +-0.79210656881332397461f,0.61038279533386230469f,-0.79490715265274047852f, +0.60673111677169799805f,-0.79769086837768554688f,0.60306662321090698242f, +-0.80045765638351440430f,0.59938931465148925781f,-0.80320751667022705078f, +0.59569931030273437500f,-0.80594038963317871094f,0.59199666976928710938f, +-0.80865615606307983398f,0.58828157186508178711f,-0.81135487556457519531f, +0.58455395698547363281f,-0.81403630971908569336f,0.58081394433975219727f, +-0.81670057773590087891f,0.57706165313720703125f,-0.81934750080108642578f, +0.57329714298248291016f,-0.82197713851928710938f,0.56952053308486938477f, +-0.82458931207656860352f,0.56573182344436645508f,-0.82718402147293090820f, +0.56193113327026367188f,-0.82976120710372924805f,0.55811852216720581055f, +-0.83232086896896362305f,0.55429410934448242188f,-0.83486288785934448242f, +0.55045795440673828125f,-0.83738720417022705078f,0.54661017656326293945f, +-0.83989381790161132812f,0.54275077581405639648f,-0.84238260984420776367f, +0.53887993097305297852f,-0.84485357999801635742f,0.53499764204025268555f, +-0.84730660915374755859f,0.53110402822494506836f,-0.84974175691604614258f, +0.52719914913177490234f,-0.85215890407562255859f,0.52328312397003173828f, +-0.85455799102783203125f,0.51935601234436035156f,-0.85693895816802978516f, +0.51541787385940551758f,-0.85930180549621582031f,0.51146882772445678711f, +-0.86164647340774536133f,0.50750899314880371094f,-0.86397284269332885742f, +0.50353837013244628906f,-0.86628097295761108398f,0.49955710768699645996f, +-0.86857068538665771484f,0.49556526541709899902f,-0.87084203958511352539f, +0.49156290292739868164f,-0.87309497594833374023f,0.48755016922950744629f, +-0.87532937526702880859f,0.48352706432342529297f,-0.87754529714584350586f, +0.47949376702308654785f,-0.87974262237548828125f,0.47545027732849121094f, +-0.88192129135131835938f,0.47139674425125122070f,-0.88408124446868896484f, +0.46733319759368896484f,-0.88622254133224487305f,0.46325978636741638184f, +-0.88834506273269653320f,0.45917654037475585938f,-0.89044874906539916992f, +0.45508357882499694824f,-0.89253354072570800781f,0.45098099112510681152f, +-0.89459949731826782227f,0.44686883687973022461f,-0.89664649963378906250f, +0.44274723529815673828f,-0.89867448806762695312f,0.43861624598503112793f, +-0.90068340301513671875f,0.43447595834732055664f,-0.90267330408096313477f, +0.43032649159431457520f,-0.90464407205581665039f,0.42616787552833557129f, +-0.90659570693969726562f,0.42200025916099548340f,-0.90852808952331542969f, +0.41782370209693908691f,-0.91044127941131591797f,0.41363832354545593262f, +-0.91233515739440917969f,0.40944415330886840820f,-0.91420978307723999023f, +0.40524131059646606445f,-0.91606497764587402344f,0.40102988481521606445f, +-0.91790080070495605469f,0.39680999517440795898f,-0.91971713304519653320f, +0.39258167147636413574f,-0.92151403427124023438f,0.38834503293037414551f, +-0.92329144477844238281f,0.38410019874572753906f,-0.92504924535751342773f, +0.37984719872474670410f,-0.92678749561309814453f,0.37558618187904357910f, +-0.92850607633590698242f,0.37131720781326293945f,-0.93020504713058471680f, +0.36704033613204956055f,-0.93188428878784179688f,0.36275571584701538086f, +-0.93354380130767822266f,0.35846340656280517578f,-0.93518352508544921875f, +0.35416352748870849609f,-0.93680346012115478516f,0.34985613822937011719f, +-0.93840354681015014648f,0.34554132819175720215f,-0.93998372554779052734f, +0.34121921658515930176f,-0.94154405593872070312f,0.33688986301422119141f, +-0.94308441877365112305f,0.33255335688591003418f,-0.94460481405258178711f, +0.32820984721183776855f,-0.94610524177551269531f,0.32385936379432678223f, +-0.94758558273315429688f,0.31950202584266662598f,-0.94904589653015136719f, +0.31513792276382446289f,-0.95048606395721435547f,0.31076714396476745605f, +-0.95190614461898803711f,0.30638980865478515625f,-0.95330601930618286133f, +0.30200594663619995117f,-0.95468574762344360352f,0.29761570692062377930f, +-0.95604526996612548828f,0.29321914911270141602f,-0.95738452672958374023f, +0.28881642222404479980f,-0.95870345830917358398f,0.28440752625465393066f, +-0.96000212430953979492f,0.27999264001846313477f,-0.96128046512603759766f, +0.27557182312011718750f,-0.96253848075866699219f,0.27114516496658325195f, +-0.96377605199813842773f,0.26671275496482849121f,-0.96499323844909667969f, +0.26227471232414245605f,-0.96618998050689697266f,0.25783109664916992188f, +-0.96736627817153930664f,0.25338202714920043945f,-0.96852207183837890625f, +0.24892760813236236572f,-0.96965736150741577148f,0.24446789920330047607f, +-0.97077214717864990234f,0.24000301957130432129f,-0.97186630964279174805f, +0.23553305864334106445f,-0.97293996810913085938f,0.23105810582637786865f, +-0.97399294376373291016f,0.22657826542854309082f,-0.97502535581588745117f, +0.22209362685680389404f,-0.97603708505630493164f,0.21760427951812744141f, +-0.97702813148498535156f,0.21311031281948089600f,-0.97799849510192871094f, +0.20861184597015380859f,-0.97894817590713500977f,0.20410896837711334229f, +-0.97987711429595947266f,0.19960175454616546631f,-0.98078525066375732422f, +0.19509032368659973145f,-0.98167270421981811523f,0.19057475030422210693f, +-0.98253929615020751953f,0.18605515360832214355f,-0.98338508605957031250f, +0.18153160810470581055f,-0.98421007394790649414f,0.17700421810150146484f, +-0.98501425981521606445f,0.17247308790683746338f,-0.98579752445220947266f, +0.16793829202651977539f,-0.98655992746353149414f,0.16339994966983795166f, +-0.98730140924453735352f,0.15885815024375915527f,-0.98802202939987182617f, +0.15431296825408935547f,-0.98872166872024536133f,0.14976453781127929688f, +-0.98940044641494750977f,0.14521291851997375488f,-0.99005818367004394531f, +0.14065824449062347412f,-0.99069499969482421875f,0.13610057532787322998f, +-0.99131083488464355469f,0.13154003024101257324f,-0.99190568923950195312f, +0.12697669863700866699f,-0.99247956275939941406f,0.12241067737340927124f, +-0.99303233623504638672f,0.11784206330776214600f,-0.99356412887573242188f, +0.11327095329761505127f,-0.99407488107681274414f,0.10869744420051574707f, +-0.99456459283828735352f,0.10412163287401199341f,-0.99503320455551147461f, +0.09954361617565155029f,-0.99548077583312988281f,0.09496349841356277466f, +-0.99590724706649780273f,0.09038136154413223267f,-0.99631261825561523438f, +0.08579730987548828125f,-0.99669688940048217773f,0.08121144771575927734f, +-0.99706006050109863281f,0.07662386447191238403f,-0.99740213155746459961f, +0.07203464955091476440f,-0.99772304296493530273f,0.06744392216205596924f, +-0.99802285432815551758f,0.06285175681114196777f,-0.99830156564712524414f, +0.05825826525688171387f,-0.99855905771255493164f,0.05366353690624237061f, +-0.99879544973373413086f,0.04906767606735229492f,-0.99901068210601806641f, +0.04447077214717864990f,-0.99920475482940673828f,0.03987292572855949402f, +-0.99937766790390014648f,0.03527423739433288574f,-0.99952942132949829102f, +0.03067480400204658508f,-0.99966001510620117188f,0.02607471868395805359f, +-0.99976938962936401367f,0.02147408016026020050f,-0.99985766410827636719f, +0.01687298715114593506f,-0.99992471933364868164f,0.01227153837680816650f, +-0.99997061491012573242f,0.00766982883214950562f,-0.99999529123306274414f, +0.00306795677170157433f,-0.99999880790710449219f,-0.00153398013208061457f, +-0.99998116493225097656f,-0.00613588467240333557f,-0.99994236230850219727f, +-0.01073765940964221954f,-0.99988234043121337891f,-0.01533920597285032272f, +-0.99980115890502929688f,-0.01994042843580245972f,-0.99969881772994995117f, +-0.02454122900962829590f,-0.99957531690597534180f,-0.02914150804281234741f, +-0.99943059682846069336f,-0.03374117240309715271f,-0.99926477670669555664f, +-0.03834012150764465332f,-0.99907773733139038086f,-0.04293825849890708923f, +-0.99886953830718994141f,-0.04753548279404640198f,-0.99864023923873901367f, +-0.05213170498609542847f,-0.99838972091674804688f,-0.05672682076692581177f, +-0.99811810255050659180f,-0.06132073700428009033f,-0.99782532453536987305f, +-0.06591334939002990723f,-0.99751144647598266602f,-0.07050457596778869629f, +-0.99717640876770019531f,-0.07509429752826690674f,-0.99682027101516723633f, +-0.07968243956565856934f,-0.99644303321838378906f,-0.08426889032125473022f, +-0.99604469537734985352f,-0.08885355293750762939f,-0.99562525749206542969f, +-0.09343633800745010376f,-0.99518471956253051758f,-0.09801714122295379639f, +-0.99472314119338989258f,-0.10259586572647094727f,-0.99424046277999877930f, +-0.10717242211103439331f,-0.99373674392700195312f,-0.11174671351909637451f, +-0.99321192502975463867f,-0.11631862819194793701f,-0.99266612529754638672f, +-0.12088808417320251465f,-0.99209928512573242188f,-0.12545497715473175049f, +-0.99151146411895751953f,-0.13001921772956848145f,-0.99090266227722167969f, +-0.13458070158958435059f,-0.99027281999588012695f,-0.13913933932781219482f, +-0.98962199687957763672f,-0.14369502663612365723f,-0.98895025253295898438f, +-0.14824767410755157471f,-0.98825758695602416992f,-0.15279719233512878418f, +-0.98754394054412841797f,-0.15734346210956573486f,-0.98680937290191650391f, +-0.16188639402389526367f,-0.98605394363403320312f,-0.16642589867115020752f, +-0.98527765274047851562f,-0.17096188664436340332f,-0.98448044061660766602f, +-0.17549425363540649414f,-0.98366242647171020508f,-0.18002289533615112305f, +-0.98282355070114135742f,-0.18454773724079132080f,-0.98196387290954589844f, +-0.18906866014003753662f,-0.98108339309692382812f,-0.19358558952808380127f, +-0.98018211126327514648f,-0.19809840619564056396f,-0.97926014661788940430f, +-0.20260703563690185547f,-0.97831737995147705078f,-0.20711137354373931885f, +-0.97735387086868286133f,-0.21161133050918579102f,-0.97636973857879638672f, +-0.21610680222511291504f,-0.97536486387252807617f,-0.22059768438339233398f, +-0.97433936595916748047f,-0.22508391737937927246f,-0.97329324483871459961f, +-0.22956536710262298584f,-0.97222650051116943359f,-0.23404195904731750488f, +-0.97113913297653198242f,-0.23851358890533447266f,-0.97003126144409179688f, +-0.24298018217086791992f,-0.96890282630920410156f,-0.24744161963462829590f, +-0.96775382757186889648f,-0.25189781188964843750f,-0.96658438444137573242f, +-0.25634866952896118164f,-0.96539443731307983398f,-0.26079410314559936523f, +-0.96418404579162597656f,-0.26523402333259582520f,-0.96295326948165893555f, +-0.26966831088066101074f,-0.96170204877853393555f,-0.27409690618515014648f, +-0.96043050289154052734f,-0.27851969003677368164f,-0.95913863182067871094f, +-0.28293657302856445312f,-0.95782643556594848633f,-0.28734746575355529785f, +-0.95649391412734985352f,-0.29175224900245666504f,-0.95514118671417236328f, +-0.29615089297294616699f,-0.95376819372177124023f,-0.30054324865341186523f, +-0.95237499475479125977f,-0.30492922663688659668f,-0.95096164941787719727f, +-0.30930876731872558594f,-0.94952815771102905273f,-0.31368175148963928223f, +-0.94807457923889160156f,-0.31804808974266052246f,-0.94660091400146484375f, +-0.32240769267082214355f,-0.94510722160339355469f,-0.32676044106483459473f, +-0.94359344244003295898f,-0.33110630512237548828f,-0.94205975532531738281f, +-0.33544513583183288574f,-0.94050604104995727539f,-0.33977687358856201172f, +-0.93893247842788696289f,-0.34410142898559570312f,-0.93733900785446166992f, +-0.34841868281364440918f,-0.93572568893432617188f,-0.35272854566574096680f, +-0.93409252166748046875f,-0.35703095793724060059f,-0.93243962526321411133f, +-0.36132580041885375977f,-0.93076694011688232422f,-0.36561298370361328125f, +-0.92907458543777465820f,-0.36989244818687438965f,-0.92736250162124633789f, +-0.37416407465934753418f,-0.92563080787658691406f,-0.37842774391174316406f, +-0.92387950420379638672f,-0.38268342614173889160f,-0.92210865020751953125f, +-0.38693100214004516602f,-0.92031830549240112305f,-0.39117038249969482422f, +-0.91850841045379638672f,-0.39540147781372070312f,-0.91667908430099487305f, +-0.39962419867515563965f,-0.91483032703399658203f,-0.40383845567703247070f, +-0.91296219825744628906f,-0.40804415941238403320f,-0.91107475757598876953f, +-0.41224122047424316406f,-0.90916800498962402344f,-0.41642954945564270020f, +-0.90724200010299682617f,-0.42060908675193786621f,-0.90529674291610717773f, +-0.42477968335151672363f,-0.90333235263824462891f,-0.42894127964973449707f, +-0.90134882926940917969f,-0.43309381604194641113f,-0.89934623241424560547f, +-0.43723717331886291504f,-0.89732456207275390625f,-0.44137126207351684570f, +-0.89528393745422363281f,-0.44549602270126342773f,-0.89322429895401000977f, +-0.44961133599281311035f,-0.89114576578140258789f,-0.45371711254119873047f, +-0.88904833793640136719f,-0.45781329274177551270f,-0.88693213462829589844f, +-0.46189978718757629395f,-0.88479709625244140625f,-0.46597650647163391113f, +-0.88264334201812744141f,-0.47004333138465881348f,-0.88047087192535400391f, +-0.47410020232200622559f,-0.87827980518341064453f,-0.47814705967903137207f, +-0.87607008218765258789f,-0.48218378424644470215f,-0.87384182214736938477f, +-0.48621028661727905273f,-0.87159508466720581055f,-0.49022647738456726074f, +-0.86932986974716186523f,-0.49423229694366455078f,-0.86704623699188232422f, +-0.49822765588760375977f,-0.86474424600601196289f,-0.50221246480941772461f, +-0.86242395639419555664f,-0.50618666410446166992f,-0.86008536815643310547f, +-0.51015007495880126953f,-0.85772860050201416016f,-0.51410275697708129883f, +-0.85535365343093872070f,-0.51804453134536743164f,-0.85296058654785156250f, +-0.52197527885437011719f,-0.85054945945739746094f,-0.52589499950408935547f, +-0.84812033176422119141f,-0.52980363368988037109f,-0.84567326307296752930f, +-0.53370100259780883789f,-0.84320825338363647461f,-0.53758704662322998047f, +-0.84072536230087280273f,-0.54146176576614379883f,-0.83822470903396606445f, +-0.54532498121261596680f,-0.83570629358291625977f,-0.54917663335800170898f, +-0.83317017555236816406f,-0.55301672220230102539f,-0.83061641454696655273f, +-0.55684500932693481445f,-0.82804507017135620117f,-0.56066155433654785156f, +-0.82545614242553710938f,-0.56446623802185058594f,-0.82284981012344360352f, +-0.56825894117355346680f,-0.82022595405578613281f,-0.57203960418701171875f, +-0.81758481264114379883f,-0.57580816745758056641f,-0.81492632627487182617f, +-0.57956457138061523438f,-0.81225061416625976562f,-0.58330863714218139648f, +-0.80955761671066284180f,-0.58704036474227905273f,-0.80684757232666015625f, +-0.59075969457626342773f,-0.80412036180496215820f,-0.59446650743484497070f, +-0.80137616395950317383f,-0.59816068410873413086f,-0.79861497879028320312f, +-0.60184222459793090820f,-0.79583692550659179688f,-0.60551106929779052734f, +-0.79304194450378417969f,-0.60916703939437866211f,-0.79023021459579467773f, +-0.61281007528305053711f,-0.78740173578262329102f,-0.61644017696380615234f, +-0.78455656766891479492f,-0.62005722522735595703f,-0.78169482946395874023f, +-0.62366110086441040039f,-0.77881652116775512695f,-0.62725180387496948242f, +-0.77592170238494873047f,-0.63082921504974365234f,-0.77301043272018432617f, +-0.63439327478408813477f,-0.77008283138275146484f,-0.63794392347335815430f, +-0.76713889837265014648f,-0.64148104190826416016f,-0.76417875289916992188f, +-0.64500451087951660156f,-0.76120239496231079102f,-0.64851438999176025391f, +-0.75820988416671752930f,-0.65201056003570556641f,-0.75520139932632446289f, +-0.65549284219741821289f,-0.75217682123184204102f,-0.65896129608154296875f, +-0.74913638830184936523f,-0.66241580247879028320f,-0.74608010053634643555f, +-0.66585624217987060547f,-0.74300795793533325195f,-0.66928261518478393555f, +-0.73992007970809936523f,-0.67269474267959594727f,-0.73681658506393432617f, +-0.67609268426895141602f,-0.73369741439819335938f,-0.67947632074356079102f, +-0.73056274652481079102f,-0.68284553289413452148f,-0.72741264104843139648f, +-0.68620032072067260742f,-0.72424709796905517578f,-0.68954056501388549805f, +-0.72106617689132690430f,-0.69286614656448364258f,-0.71787005662918090820f, +-0.69617712497711181641f,-0.71465867757797241211f,-0.69947332143783569336f, +-0.71143221855163574219f,-0.70275473594665527344f,-0.70819061994552612305f, +-0.70602124929428100586f,-0.70493406057357788086f,-0.70927280187606811523f, +-0.70166260004043579102f,-0.71250939369201660156f,-0.69837623834609985352f, +-0.71573084592819213867f,-0.69507509469985961914f,-0.71893709897994995117f, +-0.69175922870635986328f,-0.72212821245193481445f,-0.68842875957489013672f, +-0.72530394792556762695f,-0.68508368730545043945f,-0.72846436500549316406f, +-0.68172407150268554688f,-0.73160940408706665039f,-0.67835003137588500977f, +-0.73473888635635375977f,-0.67496162652969360352f,-0.73785281181335449219f, +-0.67155897617340087891f,-0.74095112085342407227f,-0.66814202070236206055f, +-0.74403375387191772461f,-0.66471099853515625000f,-0.74710059165954589844f, +-0.66126585006713867188f,-0.75015163421630859375f,-0.65780669450759887695f, +-0.75318682193756103516f,-0.65433359146118164062f,-0.75620597600936889648f, +-0.65084666013717651367f,-0.75920921564102172852f,-0.64734596014022827148f, +-0.76219630241394042969f,-0.64383155107498168945f,-0.76516723632812500000f, +-0.64030349254608154297f,-0.76812201738357543945f,-0.63676184415817260742f, +-0.77106052637100219727f,-0.63320678472518920898f,-0.77398270368576049805f, +-0.62963825464248657227f,-0.77688848972320556641f,-0.62605637311935424805f, +-0.77977776527404785156f,-0.62246125936508178711f,-0.78265058994293212891f, +-0.61885297298431396484f,-0.78550684452056884766f,-0.61523157358169555664f, +-0.78834640979766845703f,-0.61159718036651611328f,-0.79116934537887573242f, +-0.60794979333877563477f,-0.79397547245025634766f,-0.60428953170776367188f, +-0.79676479101181030273f,-0.60061645507812500000f,-0.79953724145889282227f, +-0.59693068265914916992f,-0.80229282379150390625f,-0.59323227405548095703f, +-0.80503135919570922852f,-0.58952128887176513672f,-0.80775284767150878906f, +-0.58579784631729125977f,-0.81045717000961303711f,-0.58206200599670410156f, +-0.81314438581466674805f,-0.57831376791000366211f,-0.81581443548202514648f, +-0.57455337047576904297f,-0.81846714019775390625f,-0.57078075408935546875f, +-0.82110249996185302734f,-0.56699603796005249023f,-0.82372051477432250977f, +-0.56319934129714965820f,-0.82632106542587280273f,-0.55939072370529174805f, +-0.82890409231185913086f,-0.55557024478912353516f,-0.83146959543228149414f, +-0.55173796415328979492f,-0.83401751518249511719f,-0.54789406061172485352f, +-0.83654773235321044922f,-0.54403853416442871094f,-0.83906024694442749023f, +-0.54017144441604614258f,-0.84155499935150146484f,-0.53629297018051147461f, +-0.84403187036514282227f,-0.53240311145782470703f,-0.84649091958999633789f, +-0.52850198745727539062f,-0.84893202781677246094f,-0.52458965778350830078f, +-0.85135519504547119141f,-0.52066624164581298828f,-0.85376030206680297852f, +-0.51673179864883422852f,-0.85614734888076782227f,-0.51278638839721679688f, +-0.85851621627807617188f,-0.50883013010025024414f,-0.86086696386337280273f, +-0.50486308336257934570f,-0.86319941282272338867f,-0.50088536739349365234f, +-0.86551362276077270508f,-0.49689704179763793945f,-0.86780947446823120117f, +-0.49289819598197937012f,-0.87008696794509887695f,-0.48888888955116271973f, +-0.87234604358673095703f,-0.48486924171447753906f,-0.87458664178848266602f, +-0.48083934187889099121f,-0.87680870294570922852f,-0.47679921984672546387f, +-0.87901222705841064453f,-0.47274902462959289551f,-0.88119709491729736328f, +-0.46868881583213806152f,-0.88336336612701416016f,-0.46461868286132812500f, +-0.88551086187362670898f,-0.46053871512413024902f,-0.88763964176177978516f, +-0.45644897222518920898f,-0.88974958658218383789f,-0.45234957337379455566f, +-0.89184069633483886719f,-0.44824060797691345215f,-0.89391297101974487305f, +-0.44412213563919067383f,-0.89596623182296752930f,-0.43999427556991577148f, +-0.89800059795379638672f,-0.43585708737373352051f,-0.90001589059829711914f, +-0.43171066045761108398f,-0.90201216936111450195f,-0.42755508422851562500f, +-0.90398931503295898438f,-0.42339047789573669434f,-0.90594726800918579102f, +-0.41921690106391906738f,-0.90788608789443969727f,-0.41503441333770751953f, +-0.90980571508407592773f,-0.41084316372871398926f,-0.91170603036880493164f, +-0.40664321184158325195f,-0.91358703374862670898f,-0.40243464708328247070f, +-0.91544872522354125977f,-0.39821755886077880859f,-0.91729098558425903320f, +-0.39399203658103942871f,-0.91911387443542480469f,-0.38975816965103149414f, +-0.92091721296310424805f,-0.38551604747772216797f,-0.92270112037658691406f, +-0.38126575946807861328f,-0.92446547746658325195f,-0.37700742483139038086f, +-0.92621022462844848633f,-0.37274107336997985840f,-0.92793542146682739258f, +-0.36846682429313659668f,-0.92964088916778564453f,-0.36418479681015014648f, +-0.93132668733596801758f,-0.35989505052566528320f,-0.93299281597137451172f, +-0.35559767484664916992f,-0.93463915586471557617f,-0.35129275918006896973f, +-0.93626564741134643555f,-0.34698042273521423340f,-0.93787235021591186523f, +-0.34266072511672973633f,-0.93945920467376708984f,-0.33833375573158264160f, +-0.94102615118026733398f,-0.33399966359138488770f,-0.94257318973541259766f, +-0.32965844869613647461f,-0.94410026073455810547f,-0.32531028985977172852f, +-0.94560730457305908203f,-0.32095524668693542480f,-0.94709438085556030273f, +-0.31659337878227233887f,-0.94856137037277221680f,-0.31222480535507202148f, +-0.95000827312469482422f,-0.30784964561462402344f,-0.95143502950668334961f, +-0.30346795916557312012f,-0.95284163951873779297f,-0.29907983541488647461f, +-0.95422810316085815430f,-0.29468536376953125000f,-0.95559436082839965820f, +-0.29028466343879699707f,-0.95694035291671752930f,-0.28587782382965087891f, +-0.95826607942581176758f,-0.28146493434906005859f,-0.95957154035568237305f, +-0.27704608440399169922f,-0.96085661649703979492f,-0.27262136340141296387f, +-0.96212142705917358398f,-0.26819086074829101562f,-0.96336579322814941406f, +-0.26375466585159301758f,-0.96458977460861206055f,-0.25931292772293090820f, +-0.96579337120056152344f,-0.25486564636230468750f,-0.96697646379470825195f, +-0.25041300058364868164f,-0.96813911199569702148f,-0.24595504999160766602f, +-0.96928125619888305664f,-0.24149188399314880371f,-0.97040283679962158203f, +-0.23702360689640045166f,-0.97150391340255737305f,-0.23255030810832977295f, +-0.97258436679840087891f,-0.22807207703590393066f,-0.97364425659179687500f, +-0.22358903288841247559f,-0.97468352317810058594f,-0.21910123527050018311f, +-0.97570210695266723633f,-0.21460881829261779785f,-0.97670006752014160156f, +-0.21011184155941009521f,-0.97767734527587890625f,-0.20561040937900543213f, +-0.97863394021987915039f,-0.20110464096069335938f,-0.97956979274749755859f, +-0.19659459590911865234f,-0.98048484325408935547f,-0.19208039343357086182f, +-0.98137921094894409180f,-0.18756212294101715088f,-0.98225271701812744141f, +-0.18303988873958587646f,-0.98310548067092895508f,-0.17851376533508300781f, +-0.98393744230270385742f,-0.17398387193679809570f,-0.98474848270416259766f, +-0.16945029795169830322f,-0.98553872108459472656f,-0.16491311788558959961f, +-0.98630809783935546875f,-0.16037245094776153564f,-0.98705655336380004883f, +-0.15582840144634246826f,-0.98778414726257324219f,-0.15128104388713836670f, +-0.98849081993103027344f,-0.14673046767711639404f,-0.98917651176452636719f, +-0.14217680692672729492f,-0.98984128236770629883f,-0.13762012124061584473f, +-0.99048507213592529297f,-0.13306052982807159424f,-0.99110794067382812500f, +-0.12849810719490051270f,-0.99170976877212524414f,-0.12393297255039215088f, +-0.99229061603546142578f,-0.11936521530151367188f,-0.99285042285919189453f, +-0.11479492485523223877f,-0.99338918924331665039f,-0.11022220551967620850f, +-0.99390697479248046875f,-0.10564715415239334106f,-0.99440366029739379883f, +-0.10106986016035079956f,-0.99487930536270141602f,-0.09649042785167694092f, +-0.99533390998840332031f,-0.09190895408391952515f,-0.99576741456985473633f, +-0.08732553571462631226f,-0.99617981910705566406f,-0.08274026215076446533f, +-0.99657112360000610352f,-0.07815324515104293823f,-0.99694132804870605469f, +-0.07356456667184829712f,-0.99729043245315551758f,-0.06897433102130889893f, +-0.99761843681335449219f,-0.06438262760639190674f,-0.99792528152465820312f, +-0.05978957191109657288f,-0.99821102619171142578f,-0.05519524589180946350f, +-0.99847555160522460938f,-0.05059975013136863708f,-0.99871903657913208008f, +-0.04600318148732185364f,-0.99894130229949951172f,-0.04140564054250717163f, +-0.99914240837097167969f,-0.03680722415447235107f,-0.99932235479354858398f, +-0.03220802545547485352f,-0.99948120117187500000f,-0.02760814502835273743f, +-0.99961882829666137695f,-0.02300768159329891205f,-0.99973529577255249023f, +-0.01840673014521598816f,-0.99983060359954833984f,-0.01380538847297430038f, +-0.99990469217300415039f,-0.00920375436544418335f,-0.99995762109756469727f, +-0.00460192607715725899f,-0.99998939037322998047f,1.00000000000000000000f, +0.00000000000000000000f,0.99983060359954833984f,0.01840673014521598816f, +0.99932235479354858398f,0.03680722415447235107f,0.99847555160522460938f, +0.05519524589180946350f,0.99729043245315551758f,0.07356456667184829712f, +0.99576741456985473633f,0.09190895408391952515f,0.99390697479248046875f, +0.11022220551967620850f,0.99170976877212524414f,0.12849810719490051270f, +0.98917651176452636719f,0.14673046767711639404f,0.98630809783935546875f, +0.16491311788558959961f,0.98310548067092895508f,0.18303988873958587646f, +0.97956979274749755859f,0.20110464096069335938f,0.97570210695266723633f, +0.21910123527050018311f,0.97150391340255737305f,0.23702360689640045166f, +0.96697646379470825195f,0.25486564636230468750f,0.96212142705917358398f, +0.27262136340141296387f,0.95694035291671752930f,0.29028466343879699707f, +0.95143502950668334961f,0.30784964561462402344f,0.94560730457305908203f, +0.32531028985977172852f,0.93945920467376708984f,0.34266072511672973633f, +0.93299281597137451172f,0.35989505052566528320f,0.92621022462844848633f, +0.37700742483139038086f,0.91911387443542480469f,0.39399203658103942871f, +0.91170603036880493164f,0.41084316372871398926f,0.90398931503295898438f, +0.42755508422851562500f,0.89596623182296752930f,0.44412213563919067383f, +0.88763964176177978516f,0.46053871512413024902f,0.87901222705841064453f, +0.47679921984672546387f,0.87008696794509887695f,0.49289819598197937012f, +0.86086696386337280273f,0.50883013010025024414f,0.85135519504547119141f, +0.52458965778350830078f,0.84155499935150146484f,0.54017144441604614258f, +0.83146959543228149414f,0.55557024478912353516f,0.82110249996185302734f, +0.57078075408935546875f,0.81045717000961303711f,0.58579784631729125977f, +0.79953724145889282227f,0.60061645507812500000f,0.78834640979766845703f, +0.61523157358169555664f,0.77688848972320556641f,0.62963825464248657227f, +0.76516723632812500000f,0.64383155107498168945f,0.75318682193756103516f, +0.65780669450759887695f,0.74095112085342407227f,0.67155897617340087891f, +0.72846436500549316406f,0.68508368730545043945f,0.71573084592819213867f, +0.69837623834609985352f,0.70275473594665527344f,0.71143221855163574219f, +0.68954056501388549805f,0.72424709796905517578f,0.67609268426895141602f, +0.73681658506393432617f,0.66241580247879028320f,0.74913638830184936523f, +0.64851438999176025391f,0.76120239496231079102f,0.63439327478408813477f, +0.77301043272018432617f,0.62005722522735595703f,0.78455656766891479492f, +0.60551106929779052734f,0.79583692550659179688f,0.59075969457626342773f, +0.80684757232666015625f,0.57580816745758056641f,0.81758481264114379883f, +0.56066155433654785156f,0.82804507017135620117f,0.54532498121261596680f, +0.83822470903396606445f,0.52980363368988037109f,0.84812033176422119141f, +0.51410275697708129883f,0.85772860050201416016f,0.49822765588760375977f, +0.86704623699188232422f,0.48218378424644470215f,0.87607008218765258789f, +0.46597650647163391113f,0.88479709625244140625f,0.44961133599281311035f, +0.89322429895401000977f,0.43309381604194641113f,0.90134882926940917969f, +0.41642954945564270020f,0.90916800498962402344f,0.39962419867515563965f, +0.91667908430099487305f,0.38268342614173889160f,0.92387950420379638672f, +0.36561298370361328125f,0.93076694011688232422f,0.34841868281364440918f, +0.93733900785446166992f,0.33110630512237548828f,0.94359344244003295898f, +0.31368175148963928223f,0.94952815771102905273f,0.29615089297294616699f, +0.95514118671417236328f,0.27851969003677368164f,0.96043050289154052734f, +0.26079410314559936523f,0.96539443731307983398f,0.24298018217086791992f, +0.97003126144409179688f,0.22508391737937927246f,0.97433936595916748047f, +0.20711137354373931885f,0.97831737995147705078f,0.18906866014003753662f, +0.98196387290954589844f,0.17096188664436340332f,0.98527765274047851562f, +0.15279719233512878418f,0.98825758695602416992f,0.13458070158958435059f, +0.99090266227722167969f,0.11631862819194793701f,0.99321192502975463867f, +0.09801714122295379639f,0.99518471956253051758f,0.07968243956565856934f, +0.99682027101516723633f,0.06132073700428009033f,0.99811810255050659180f, +0.04293825849890708923f,0.99907773733139038086f,0.02454122900962829590f, +0.99969881772994995117f,0.00613588467240333557f,0.99998116493225097656f, +-0.01227153837680816650f,0.99992471933364868164f,-0.03067480400204658508f, +0.99952942132949829102f,-0.04906767606735229492f,0.99879544973373413086f, +-0.06744392216205596924f,0.99772304296493530273f,-0.08579730987548828125f, +0.99631261825561523438f,-0.10412163287401199341f,0.99456459283828735352f, +-0.12241067737340927124f,0.99247956275939941406f,-0.14065824449062347412f, +0.99005818367004394531f,-0.15885815024375915527f,0.98730140924453735352f, +-0.17700421810150146484f,0.98421007394790649414f,-0.19509032368659973145f, +0.98078525066375732422f,-0.21311031281948089600f,0.97702813148498535156f, +-0.23105810582637786865f,0.97293996810913085938f,-0.24892760813236236572f, +0.96852207183837890625f,-0.26671275496482849121f,0.96377605199813842773f, +-0.28440752625465393066f,0.95870345830917358398f,-0.30200594663619995117f, +0.95330601930618286133f,-0.31950202584266662598f,0.94758558273315429688f, +-0.33688986301422119141f,0.94154405593872070312f,-0.35416352748870849609f, +0.93518352508544921875f,-0.37131720781326293945f,0.92850607633590698242f, +-0.38834503293037414551f,0.92151403427124023438f,-0.40524131059646606445f, +0.91420978307723999023f,-0.42200025916099548340f,0.90659570693969726562f, +-0.43861624598503112793f,0.89867448806762695312f,-0.45508357882499694824f, +0.89044874906539916992f,-0.47139674425125122070f,0.88192129135131835938f, +-0.48755016922950744629f,0.87309497594833374023f,-0.50353837013244628906f, +0.86397284269332885742f,-0.51935601234436035156f,0.85455799102783203125f, +-0.53499764204025268555f,0.84485357999801635742f,-0.55045795440673828125f, +0.83486288785934448242f,-0.56573182344436645508f,0.82458931207656860352f, +-0.58081394433975219727f,0.81403630971908569336f,-0.59569931030273437500f, +0.80320751667022705078f,-0.61038279533386230469f,0.79210656881332397461f, +-0.62485951185226440430f,0.78073722124099731445f,-0.63912445306777954102f, +0.76910334825515747070f,-0.65317285060882568359f,0.75720882415771484375f, +-0.66699993610382080078f,0.74505776166915893555f,-0.68060100078582763672f, +0.73265427350997924805f,-0.69397145509719848633f,0.72000253200531005859f, +-0.70710676908493041992f,0.70710676908493041992f,-0.72000253200531005859f, +0.69397145509719848633f,-0.73265427350997924805f,0.68060100078582763672f, +-0.74505776166915893555f,0.66699993610382080078f,-0.75720882415771484375f, +0.65317285060882568359f,-0.76910334825515747070f,0.63912445306777954102f, +-0.78073722124099731445f,0.62485951185226440430f,-0.79210656881332397461f, +0.61038279533386230469f,-0.80320751667022705078f,0.59569931030273437500f, +-0.81403630971908569336f,0.58081394433975219727f,-0.82458931207656860352f, +0.56573182344436645508f,-0.83486288785934448242f,0.55045795440673828125f, +-0.84485357999801635742f,0.53499764204025268555f,-0.85455799102783203125f, +0.51935601234436035156f,-0.86397284269332885742f,0.50353837013244628906f, +-0.87309497594833374023f,0.48755016922950744629f,-0.88192129135131835938f, +0.47139674425125122070f,-0.89044874906539916992f,0.45508357882499694824f, +-0.89867448806762695312f,0.43861624598503112793f,-0.90659570693969726562f, +0.42200025916099548340f,-0.91420978307723999023f,0.40524131059646606445f, +-0.92151403427124023438f,0.38834503293037414551f,-0.92850607633590698242f, +0.37131720781326293945f,-0.93518352508544921875f,0.35416352748870849609f, +-0.94154405593872070312f,0.33688986301422119141f,-0.94758558273315429688f, +0.31950202584266662598f,-0.95330601930618286133f,0.30200594663619995117f, +-0.95870345830917358398f,0.28440752625465393066f,-0.96377605199813842773f, +0.26671275496482849121f,-0.96852207183837890625f,0.24892760813236236572f, +-0.97293996810913085938f,0.23105810582637786865f,-0.97702813148498535156f, +0.21311031281948089600f,-0.98078525066375732422f,0.19509032368659973145f, +-0.98421007394790649414f,0.17700421810150146484f,-0.98730140924453735352f, +0.15885815024375915527f,-0.99005818367004394531f,0.14065824449062347412f, +-0.99247956275939941406f,0.12241067737340927124f,-0.99456459283828735352f, +0.10412163287401199341f,-0.99631261825561523438f,0.08579730987548828125f, +-0.99772304296493530273f,0.06744392216205596924f,-0.99879544973373413086f, +0.04906767606735229492f,-0.99952942132949829102f,0.03067480400204658508f, +-0.99992471933364868164f,0.01227153837680816650f,-0.99998116493225097656f, +-0.00613588467240333557f,-0.99969881772994995117f,-0.02454122900962829590f, +-0.99907773733139038086f,-0.04293825849890708923f,-0.99811810255050659180f, +-0.06132073700428009033f,-0.99682027101516723633f,-0.07968243956565856934f, +-0.99518471956253051758f,-0.09801714122295379639f,-0.99321192502975463867f, +-0.11631862819194793701f,-0.99090266227722167969f,-0.13458070158958435059f, +-0.98825758695602416992f,-0.15279719233512878418f,-0.98527765274047851562f, +-0.17096188664436340332f,-0.98196387290954589844f,-0.18906866014003753662f, +-0.97831737995147705078f,-0.20711137354373931885f,-0.97433936595916748047f, +-0.22508391737937927246f,-0.97003126144409179688f,-0.24298018217086791992f, +-0.96539443731307983398f,-0.26079410314559936523f,-0.96043050289154052734f, +-0.27851969003677368164f,-0.95514118671417236328f,-0.29615089297294616699f, +-0.94952815771102905273f,-0.31368175148963928223f,-0.94359344244003295898f, +-0.33110630512237548828f,-0.93733900785446166992f,-0.34841868281364440918f, +-0.93076694011688232422f,-0.36561298370361328125f,-0.92387950420379638672f, +-0.38268342614173889160f,-0.91667908430099487305f,-0.39962419867515563965f, +-0.90916800498962402344f,-0.41642954945564270020f,-0.90134882926940917969f, +-0.43309381604194641113f,-0.89322429895401000977f,-0.44961133599281311035f, +-0.88479709625244140625f,-0.46597650647163391113f,-0.87607008218765258789f, +-0.48218378424644470215f,-0.86704623699188232422f,-0.49822765588760375977f, +-0.85772860050201416016f,-0.51410275697708129883f,-0.84812033176422119141f, +-0.52980363368988037109f,-0.83822470903396606445f,-0.54532498121261596680f, +-0.82804507017135620117f,-0.56066155433654785156f,-0.81758481264114379883f, +-0.57580816745758056641f,-0.80684757232666015625f,-0.59075969457626342773f, +-0.79583692550659179688f,-0.60551106929779052734f,-0.78455656766891479492f, +-0.62005722522735595703f,-0.77301043272018432617f,-0.63439327478408813477f, +-0.76120239496231079102f,-0.64851438999176025391f,-0.74913638830184936523f, +-0.66241580247879028320f,-0.73681658506393432617f,-0.67609268426895141602f, +-0.72424709796905517578f,-0.68954056501388549805f,-0.71143221855163574219f, +-0.70275473594665527344f,-0.69837623834609985352f,-0.71573084592819213867f, +-0.68508368730545043945f,-0.72846436500549316406f,-0.67155897617340087891f, +-0.74095112085342407227f,-0.65780669450759887695f,-0.75318682193756103516f, +-0.64383155107498168945f,-0.76516723632812500000f,-0.62963825464248657227f, +-0.77688848972320556641f,-0.61523157358169555664f,-0.78834640979766845703f, +-0.60061645507812500000f,-0.79953724145889282227f,-0.58579784631729125977f, +-0.81045717000961303711f,-0.57078075408935546875f,-0.82110249996185302734f, +-0.55557024478912353516f,-0.83146959543228149414f,-0.54017144441604614258f, +-0.84155499935150146484f,-0.52458965778350830078f,-0.85135519504547119141f, +-0.50883013010025024414f,-0.86086696386337280273f,-0.49289819598197937012f, +-0.87008696794509887695f,-0.47679921984672546387f,-0.87901222705841064453f, +-0.46053871512413024902f,-0.88763964176177978516f,-0.44412213563919067383f, +-0.89596623182296752930f,-0.42755508422851562500f,-0.90398931503295898438f, +-0.41084316372871398926f,-0.91170603036880493164f,-0.39399203658103942871f, +-0.91911387443542480469f,-0.37700742483139038086f,-0.92621022462844848633f, +-0.35989505052566528320f,-0.93299281597137451172f,-0.34266072511672973633f, +-0.93945920467376708984f,-0.32531028985977172852f,-0.94560730457305908203f, +-0.30784964561462402344f,-0.95143502950668334961f,-0.29028466343879699707f, +-0.95694035291671752930f,-0.27262136340141296387f,-0.96212142705917358398f, +-0.25486564636230468750f,-0.96697646379470825195f,-0.23702360689640045166f, +-0.97150391340255737305f,-0.21910123527050018311f,-0.97570210695266723633f, +-0.20110464096069335938f,-0.97956979274749755859f,-0.18303988873958587646f, +-0.98310548067092895508f,-0.16491311788558959961f,-0.98630809783935546875f, +-0.14673046767711639404f,-0.98917651176452636719f,-0.12849810719490051270f, +-0.99170976877212524414f,-0.11022220551967620850f,-0.99390697479248046875f, +-0.09190895408391952515f,-0.99576741456985473633f,-0.07356456667184829712f, +-0.99729043245315551758f,-0.05519524589180946350f,-0.99847555160522460938f, +-0.03680722415447235107f,-0.99932235479354858398f,-0.01840673014521598816f, +-0.99983060359954833984f,1.00000000000000000000f,0.00000000000000000000f, +0.99729043245315551758f,0.07356456667184829712f,0.98917651176452636719f, +0.14673046767711639404f,0.97570210695266723633f,0.21910123527050018311f, +0.95694035291671752930f,0.29028466343879699707f,0.93299281597137451172f, +0.35989505052566528320f,0.90398931503295898438f,0.42755508422851562500f, +0.87008696794509887695f,0.49289819598197937012f,0.83146959543228149414f, +0.55557024478912353516f,0.78834640979766845703f,0.61523157358169555664f, +0.74095112085342407227f,0.67155897617340087891f,0.68954056501388549805f, +0.72424709796905517578f,0.63439327478408813477f,0.77301043272018432617f, +0.57580816745758056641f,0.81758481264114379883f,0.51410275697708129883f, +0.85772860050201416016f,0.44961133599281311035f,0.89322429895401000977f, +0.38268342614173889160f,0.92387950420379638672f,0.31368175148963928223f, +0.94952815771102905273f,0.24298018217086791992f,0.97003126144409179688f, +0.17096188664436340332f,0.98527765274047851562f,0.09801714122295379639f, +0.99518471956253051758f,0.02454122900962829590f,0.99969881772994995117f, +-0.04906767606735229492f,0.99879544973373413086f,-0.12241067737340927124f, +0.99247956275939941406f,-0.19509032368659973145f,0.98078525066375732422f, +-0.26671275496482849121f,0.96377605199813842773f,-0.33688986301422119141f, +0.94154405593872070312f,-0.40524131059646606445f,0.91420978307723999023f, +-0.47139674425125122070f,0.88192129135131835938f,-0.53499764204025268555f, +0.84485357999801635742f,-0.59569931030273437500f,0.80320751667022705078f, +-0.65317285060882568359f,0.75720882415771484375f,-0.70710676908493041992f, +0.70710676908493041992f,-0.75720882415771484375f,0.65317285060882568359f, +-0.80320751667022705078f,0.59569931030273437500f,-0.84485357999801635742f, +0.53499764204025268555f,-0.88192129135131835938f,0.47139674425125122070f, +-0.91420978307723999023f,0.40524131059646606445f,-0.94154405593872070312f, +0.33688986301422119141f,-0.96377605199813842773f,0.26671275496482849121f, +-0.98078525066375732422f,0.19509032368659973145f,-0.99247956275939941406f, +0.12241067737340927124f,-0.99879544973373413086f,0.04906767606735229492f, +-0.99969881772994995117f,-0.02454122900962829590f,-0.99518471956253051758f, +-0.09801714122295379639f,-0.98527765274047851562f,-0.17096188664436340332f, +-0.97003126144409179688f,-0.24298018217086791992f,-0.94952815771102905273f, +-0.31368175148963928223f,-0.92387950420379638672f,-0.38268342614173889160f, +-0.89322429895401000977f,-0.44961133599281311035f,-0.85772860050201416016f, +-0.51410275697708129883f,-0.81758481264114379883f,-0.57580816745758056641f, +-0.77301043272018432617f,-0.63439327478408813477f,-0.72424709796905517578f, +-0.68954056501388549805f,-0.67155897617340087891f,-0.74095112085342407227f, +-0.61523157358169555664f,-0.78834640979766845703f,-0.55557024478912353516f, +-0.83146959543228149414f,-0.49289819598197937012f,-0.87008696794509887695f, +-0.42755508422851562500f,-0.90398931503295898438f,-0.35989505052566528320f, +-0.93299281597137451172f,-0.29028466343879699707f,-0.95694035291671752930f, +-0.21910123527050018311f,-0.97570210695266723633f,-0.14673046767711639404f, +-0.98917651176452636719f,-0.07356456667184829712f,-0.99729043245315551758f, +1.00000000000000000000f,0.00000000000000000000f,0.95694035291671752930f, +0.29028466343879699707f,0.83146959543228149414f,0.55557024478912353516f, +0.63439327478408813477f,0.77301043272018432617f,0.38268342614173889160f, +0.92387950420379638672f,0.09801714122295379639f,0.99518471956253051758f, +-0.19509032368659973145f,0.98078525066375732422f,-0.47139674425125122070f, +0.88192129135131835938f,-0.70710676908493041992f,0.70710676908493041992f, +-0.88192129135131835938f,0.47139674425125122070f,-0.98078525066375732422f, +0.19509032368659973145f,-0.99518471956253051758f,-0.09801714122295379639f, +-0.92387950420379638672f,-0.38268342614173889160f,-0.77301043272018432617f, +-0.63439327478408813477f,-0.55557024478912353516f,-0.83146959543228149414f, +-0.29028466343879699707f,-0.95694035291671752930f,1.00000000000000000000f, +0.00000000000000000000f,0.38268342614173889160f,0.92387950420379638672f, +-0.70710676908493041992f,0.70710676908493041992f,-0.92387950420379638672f, +-0.38268342614173889160f,}; + +#endif + + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) + +uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2]={ +0,0,}; + +q31_t rearranged_twiddle_stride1_16_q31[8]={ +0x7FFFFFFF,0x00000000,0x7641AF3D,0xCF043AB3,0x5A82799A,0xA57D8666,0x30FBC54D, +0x89BE50C3,}; + +q31_t rearranged_twiddle_stride2_16_q31[8]={ +0x7FFFFFFF,0x00000000,0x5A82799A,0xA57D8666,0x00000000,0x80000000,0xA57D8666, +0xA57D8666,}; + +q31_t rearranged_twiddle_stride3_16_q31[8]={ +0x7FFFFFFF,0x00000000,0x30FBC54D,0x89BE50C3,0xA57D8666,0xA57D8666,0x89BE50C3, +0x30FBC54D,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) + +uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3]={ +0,32,0,}; + +q31_t rearranged_twiddle_stride1_64_q31[40]={ +0x7FFFFFFF,0x00000000,0x7F62368F,0xF3742CA2,0x7D8A5F40,0xE70747C4,0x7A7D055B, +0xDAD7F3A2,0x7641AF3D,0xCF043AB3,0x70E2CBC6,0xC3A94590,0x6A6D98A4,0xB8E31319, +0x62F201AC,0xAECC336C,0x5A82799A,0xA57D8666,0x5133CC94,0x9D0DFE54,0x471CECE7, +0x9592675C,0x3C56BA70,0x8F1D343A,0x30FBC54D,0x89BE50C3,0x25280C5E,0x8582FAA5, +0x18F8B83C,0x8275A0C0,0x0C8BD35E,0x809DC971,0x7FFFFFFF,0x00000000,0x7641AF3D, +0xCF043AB3,0x5A82799A,0xA57D8666,0x30FBC54D,0x89BE50C3,}; + +q31_t rearranged_twiddle_stride2_64_q31[40]={ +0x7FFFFFFF,0x00000000,0x7D8A5F40,0xE70747C4,0x7641AF3D,0xCF043AB3,0x6A6D98A4, +0xB8E31319,0x5A82799A,0xA57D8666,0x471CECE7,0x9592675C,0x30FBC54D,0x89BE50C3, +0x18F8B83C,0x8275A0C0,0x00000000,0x80000000,0xE70747C4,0x8275A0C0,0xCF043AB3, +0x89BE50C3,0xB8E31319,0x9592675C,0xA57D8666,0xA57D8666,0x9592675C,0xB8E31319, +0x89BE50C3,0xCF043AB3,0x8275A0C0,0xE70747C4,0x7FFFFFFF,0x00000000,0x5A82799A, +0xA57D8666,0x00000000,0x80000000,0xA57D8666,0xA57D8666,}; + +q31_t rearranged_twiddle_stride3_64_q31[40]={ +0x7FFFFFFF,0x00000000,0x7A7D055B,0xDAD7F3A2,0x6A6D98A4,0xB8E31319,0x5133CC94, +0x9D0DFE54,0x30FBC54D,0x89BE50C3,0x0C8BD35E,0x809DC971,0xE70747C4,0x8275A0C0, +0xC3A94590,0x8F1D343A,0xA57D8666,0xA57D8666,0x8F1D343A,0xC3A94590,0x8275A0C0, +0xE70747C4,0x809DC971,0x0C8BD35E,0x89BE50C3,0x30FBC54D,0x9D0DFE54,0x5133CC94, +0xB8E31319,0x6A6D98A4,0xDAD7F3A2,0x7A7D055B,0x7FFFFFFF,0x00000000,0x30FBC54D, +0x89BE50C3,0xA57D8666,0xA57D8666,0x89BE50C3,0x30FBC54D,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) + +uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4]={ +0,128,160,0,}; + +q31_t rearranged_twiddle_stride1_256_q31[168]={ +0x7FFFFFFF,0x00000000,0x7FF62182,0xFCDBD541,0x7FD8878E,0xF9B82684,0x7FA736B4, +0xF6956FB7,0x7F62368F,0xF3742CA2,0x7F0991C4,0xF054D8D5,0x7E9D55FC,0xED37EF91, +0x7E1D93EA,0xEA1DEBBB,0x7D8A5F40,0xE70747C4,0x7CE3CEB2,0xE3F47D96,0x7C29FBEE, +0xE0E60685,0x7B5D039E,0xDDDC5B3B,0x7A7D055B,0xDAD7F3A2,0x798A23B1,0xD7D946D8, +0x78848414,0xD4E0CB15,0x776C4EDB,0xD1EEF59E,0x7641AF3D,0xCF043AB3,0x7504D345, +0xCC210D79,0x73B5EBD1,0xC945DFEC,0x72552C85,0xC67322CE,0x70E2CBC6,0xC3A94590, +0x6F5F02B2,0xC0E8B648,0x6DCA0D14,0xBE31E19B,0x6C242960,0xBB8532B0,0x6A6D98A4, +0xB8E31319,0x68A69E81,0xB64BEACD,0x66CF8120,0xB3C0200C,0x64E88926,0xB140175B, +0x62F201AC,0xAECC336C,0x60EC3830,0xAC64D510,0x5ED77C8A,0xAA0A5B2E,0x5CB420E0, +0xA7BD22AC,0x5A82799A,0xA57D8666,0x5842DD54,0xA34BDF20,0x55F5A4D2,0xA1288376, +0x539B2AF0,0x9F13C7D0,0x5133CC94,0x9D0DFE54,0x4EBFE8A5,0x9B1776DA,0x4C3FDFF4, +0x99307EE0,0x49B41533,0x9759617F,0x471CECE7,0x9592675C,0x447ACD50,0x93DBD6A0, +0x41CE1E65,0x9235F2EC,0x3F1749B8,0x90A0FD4E,0x3C56BA70,0x8F1D343A,0x398CDD32, +0x8DAAD37B,0x36BA2014,0x8C4A142F,0x33DEF287,0x8AFB2CBB,0x30FBC54D,0x89BE50C3, +0x2E110A62,0x8893B125,0x2B1F34EB,0x877B7BEC,0x2826B928,0x8675DC4F,0x25280C5E, +0x8582FAA5,0x2223A4C5,0x84A2FC62,0x1F19F97B,0x83D60412,0x1C0B826A,0x831C314E, +0x18F8B83C,0x8275A0C0,0x15E21445,0x81E26C16,0x12C8106F,0x8162AA04,0x0FAB272B, +0x80F66E3C,0x0C8BD35E,0x809DC971,0x096A9049,0x8058C94C,0x0647D97C,0x80277872, +0x03242ABF,0x8009DE7E,0x7FFFFFFF,0x00000000,0x7F62368F,0xF3742CA2,0x7D8A5F40, +0xE70747C4,0x7A7D055B,0xDAD7F3A2,0x7641AF3D,0xCF043AB3,0x70E2CBC6,0xC3A94590, +0x6A6D98A4,0xB8E31319,0x62F201AC,0xAECC336C,0x5A82799A,0xA57D8666,0x5133CC94, +0x9D0DFE54,0x471CECE7,0x9592675C,0x3C56BA70,0x8F1D343A,0x30FBC54D,0x89BE50C3, +0x25280C5E,0x8582FAA5,0x18F8B83C,0x8275A0C0,0x0C8BD35E,0x809DC971,0x7FFFFFFF, +0x00000000,0x7641AF3D,0xCF043AB3,0x5A82799A,0xA57D8666,0x30FBC54D,0x89BE50C3,}; + +q31_t rearranged_twiddle_stride2_256_q31[168]={ +0x7FFFFFFF,0x00000000,0x7FD8878E,0xF9B82684,0x7F62368F,0xF3742CA2,0x7E9D55FC, +0xED37EF91,0x7D8A5F40,0xE70747C4,0x7C29FBEE,0xE0E60685,0x7A7D055B,0xDAD7F3A2, +0x78848414,0xD4E0CB15,0x7641AF3D,0xCF043AB3,0x73B5EBD1,0xC945DFEC,0x70E2CBC6, +0xC3A94590,0x6DCA0D14,0xBE31E19B,0x6A6D98A4,0xB8E31319,0x66CF8120,0xB3C0200C, +0x62F201AC,0xAECC336C,0x5ED77C8A,0xAA0A5B2E,0x5A82799A,0xA57D8666,0x55F5A4D2, +0xA1288376,0x5133CC94,0x9D0DFE54,0x4C3FDFF4,0x99307EE0,0x471CECE7,0x9592675C, +0x41CE1E65,0x9235F2EC,0x3C56BA70,0x8F1D343A,0x36BA2014,0x8C4A142F,0x30FBC54D, +0x89BE50C3,0x2B1F34EB,0x877B7BEC,0x25280C5E,0x8582FAA5,0x1F19F97B,0x83D60412, +0x18F8B83C,0x8275A0C0,0x12C8106F,0x8162AA04,0x0C8BD35E,0x809DC971,0x0647D97C, +0x80277872,0x00000000,0x80000000,0xF9B82684,0x80277872,0xF3742CA2,0x809DC971, +0xED37EF91,0x8162AA04,0xE70747C4,0x8275A0C0,0xE0E60685,0x83D60412,0xDAD7F3A2, +0x8582FAA5,0xD4E0CB15,0x877B7BEC,0xCF043AB3,0x89BE50C3,0xC945DFEC,0x8C4A142F, +0xC3A94590,0x8F1D343A,0xBE31E19B,0x9235F2EC,0xB8E31319,0x9592675C,0xB3C0200C, +0x99307EE0,0xAECC336C,0x9D0DFE54,0xAA0A5B2E,0xA1288376,0xA57D8666,0xA57D8666, +0xA1288376,0xAA0A5B2E,0x9D0DFE54,0xAECC336C,0x99307EE0,0xB3C0200C,0x9592675C, +0xB8E31319,0x9235F2EC,0xBE31E19B,0x8F1D343A,0xC3A94590,0x8C4A142F,0xC945DFEC, +0x89BE50C3,0xCF043AB3,0x877B7BEC,0xD4E0CB15,0x8582FAA5,0xDAD7F3A2,0x83D60412, +0xE0E60685,0x8275A0C0,0xE70747C4,0x8162AA04,0xED37EF91,0x809DC971,0xF3742CA2, +0x80277872,0xF9B82684,0x7FFFFFFF,0x00000000,0x7D8A5F40,0xE70747C4,0x7641AF3D, +0xCF043AB3,0x6A6D98A4,0xB8E31319,0x5A82799A,0xA57D8666,0x471CECE7,0x9592675C, +0x30FBC54D,0x89BE50C3,0x18F8B83C,0x8275A0C0,0x00000000,0x80000000,0xE70747C4, +0x8275A0C0,0xCF043AB3,0x89BE50C3,0xB8E31319,0x9592675C,0xA57D8666,0xA57D8666, +0x9592675C,0xB8E31319,0x89BE50C3,0xCF043AB3,0x8275A0C0,0xE70747C4,0x7FFFFFFF, +0x00000000,0x5A82799A,0xA57D8666,0x00000000,0x80000000,0xA57D8666,0xA57D8666,}; + +q31_t rearranged_twiddle_stride3_256_q31[168]={ +0x7FFFFFFF,0x00000000,0x7FA736B4,0xF6956FB7,0x7E9D55FC,0xED37EF91,0x7CE3CEB2, +0xE3F47D96,0x7A7D055B,0xDAD7F3A2,0x776C4EDB,0xD1EEF59E,0x73B5EBD1,0xC945DFEC, +0x6F5F02B2,0xC0E8B648,0x6A6D98A4,0xB8E31319,0x64E88926,0xB140175B,0x5ED77C8A, +0xAA0A5B2E,0x5842DD54,0xA34BDF20,0x5133CC94,0x9D0DFE54,0x49B41533,0x9759617F, +0x41CE1E65,0x9235F2EC,0x398CDD32,0x8DAAD37B,0x30FBC54D,0x89BE50C3,0x2826B928, +0x8675DC4F,0x1F19F97B,0x83D60412,0x15E21445,0x81E26C16,0x0C8BD35E,0x809DC971, +0x03242ABF,0x8009DE7E,0xF9B82684,0x80277872,0xF054D8D5,0x80F66E3C,0xE70747C4, +0x8275A0C0,0xDDDC5B3B,0x84A2FC62,0xD4E0CB15,0x877B7BEC,0xCC210D79,0x8AFB2CBB, +0xC3A94590,0x8F1D343A,0xBB8532B0,0x93DBD6A0,0xB3C0200C,0x99307EE0,0xAC64D510, +0x9F13C7D0,0xA57D8666,0xA57D8666,0x9F13C7D0,0xAC64D510,0x99307EE0,0xB3C0200C, +0x93DBD6A0,0xBB8532B0,0x8F1D343A,0xC3A94590,0x8AFB2CBB,0xCC210D79,0x877B7BEC, +0xD4E0CB15,0x84A2FC62,0xDDDC5B3B,0x8275A0C0,0xE70747C4,0x80F66E3C,0xF054D8D5, +0x80277872,0xF9B82684,0x8009DE7E,0x03242ABF,0x809DC971,0x0C8BD35E,0x81E26C16, +0x15E21445,0x83D60412,0x1F19F97B,0x8675DC4F,0x2826B928,0x89BE50C3,0x30FBC54D, +0x8DAAD37B,0x398CDD32,0x9235F2EC,0x41CE1E65,0x9759617F,0x49B41533,0x9D0DFE54, +0x5133CC94,0xA34BDF20,0x5842DD54,0xAA0A5B2E,0x5ED77C8A,0xB140175B,0x64E88926, +0xB8E31319,0x6A6D98A4,0xC0E8B648,0x6F5F02B2,0xC945DFEC,0x73B5EBD1,0xD1EEF59E, +0x776C4EDB,0xDAD7F3A2,0x7A7D055B,0xE3F47D96,0x7CE3CEB2,0xED37EF91,0x7E9D55FC, +0xF6956FB7,0x7FA736B4,0x7FFFFFFF,0x00000000,0x7A7D055B,0xDAD7F3A2,0x6A6D98A4, +0xB8E31319,0x5133CC94,0x9D0DFE54,0x30FBC54D,0x89BE50C3,0x0C8BD35E,0x809DC971, +0xE70747C4,0x8275A0C0,0xC3A94590,0x8F1D343A,0xA57D8666,0xA57D8666,0x8F1D343A, +0xC3A94590,0x8275A0C0,0xE70747C4,0x809DC971,0x0C8BD35E,0x89BE50C3,0x30FBC54D, +0x9D0DFE54,0x5133CC94,0xB8E31319,0x6A6D98A4,0xDAD7F3A2,0x7A7D055B,0x7FFFFFFF, +0x00000000,0x30FBC54D,0x89BE50C3,0xA57D8666,0xA57D8666,0x89BE50C3,0x30FBC54D,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) + +uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5]={ +0,512,640,672,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5]={ +0,512,640,672,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5]={ +0,512,640,672,0,}; + +q31_t rearranged_twiddle_stride1_1024_q31[680]={ +0x7FFFFFFF,0x00000000,0x7FFF6216,0xFF36F078,0x7FFD885A,0xFE6DE2E0,0x7FFA72D1, +0xFDA4D929,0x7FF62182,0xFCDBD541,0x7FF09478,0xFC12D91A,0x7FE9CBC0,0xFB49E6A3, +0x7FE1C76B,0xFA80FFCB,0x7FD8878E,0xF9B82684,0x7FCE0C3E,0xF8EF5CBB,0x7FC25596, +0xF826A462,0x7FB563B3,0xF75DFF66,0x7FA736B4,0xF6956FB7,0x7F97CEBD,0xF5CCF743, +0x7F872BF3,0xF50497FB,0x7F754E80,0xF43C53CB,0x7F62368F,0xF3742CA2,0x7F4DE451, +0xF2AC246E,0x7F3857F6,0xF1E43D1C,0x7F2191B4,0xF11C789A,0x7F0991C4,0xF054D8D5, +0x7EF05860,0xEF8D5FB8,0x7ED5E5C6,0xEEC60F31,0x7EBA3A39,0xEDFEE92B,0x7E9D55FC, +0xED37EF91,0x7E7F3957,0xEC71244F,0x7E5FE493,0xEBAA894F,0x7E3F57FF,0xEAE4207A, +0x7E1D93EA,0xEA1DEBBB,0x7DFA98A8,0xE957ECFB,0x7DD6668F,0xE8922622,0x7DB0FDF8, +0xE7CC9917,0x7D8A5F40,0xE70747C4,0x7D628AC6,0xE642340D,0x7D3980EC,0xE57D5FDA, +0x7D0F4218,0xE4B8CD11,0x7CE3CEB2,0xE3F47D96,0x7CB72724,0xE330734D,0x7C894BDE, +0xE26CB01B,0x7C5A3D50,0xE1A935E2,0x7C29FBEE,0xE0E60685,0x7BF88830,0xE02323E5, +0x7BC5E290,0xDF608FE4,0x7B920B89,0xDE9E4C60,0x7B5D039E,0xDDDC5B3B,0x7B26CB4F, +0xDD1ABE51,0x7AEF6323,0xDC597781,0x7AB6CBA4,0xDB9888A8,0x7A7D055B,0xDAD7F3A2, +0x7A4210D8,0xDA17BA4A,0x7A05EEAD,0xD957DE7A,0x79C89F6E,0xD898620C,0x798A23B1, +0xD7D946D8,0x794A7C12,0xD71A8EB5,0x7909A92D,0xD65C3B7B,0x78C7ABA2,0xD59E4EFF, +0x78848414,0xD4E0CB15,0x78403329,0xD423B191,0x77FAB989,0xD3670446,0x77B417DF, +0xD2AAC504,0x776C4EDB,0xD1EEF59E,0x77235F2D,0xD13397E2,0x76D94989,0xD078AD9E, +0x768E0EA6,0xCFBE389F,0x7641AF3D,0xCF043AB3,0x75F42C0B,0xCE4AB5A2,0x75A585CF, +0xCD91AB39,0x7555BD4C,0xCCD91D3D,0x7504D345,0xCC210D79,0x74B2C884,0xCB697DB0, +0x745F9DD1,0xCAB26FA9,0x740B53FB,0xC9FBE527,0x73B5EBD1,0xC945DFEC,0x735F6626, +0xC89061BA,0x7307C3D0,0xC7DB6C50,0x72AF05A7,0xC727016D,0x72552C85,0xC67322CE, +0x71FA3949,0xC5BFD22E,0x719E2CD2,0xC50D1149,0x71410805,0xC45AE1D7,0x70E2CBC6, +0xC3A94590,0x708378FF,0xC2F83E2A,0x7023109A,0xC247CD5A,0x6FC19385,0xC197F4D4, +0x6F5F02B2,0xC0E8B648,0x6EFB5F12,0xC03A1368,0x6E96A99D,0xBF8C0DE3,0x6E30E34A, +0xBEDEA765,0x6DCA0D14,0xBE31E19B,0x6D6227FA,0xBD85BE30,0x6CF934FC,0xBCDA3ECB, +0x6C8F351C,0xBC2F6513,0x6C242960,0xBB8532B0,0x6BB812D1,0xBADBA943,0x6B4AF279, +0xBA32CA71,0x6ADCC964,0xB98A97D8,0x6A6D98A4,0xB8E31319,0x69FD614A,0xB83C3DD1, +0x698C246C,0xB796199B,0x6919E320,0xB6F0A812,0x68A69E81,0xB64BEACD,0x683257AB, +0xB5A7E362,0x67BD0FBD,0xB5049368,0x6746C7D8,0xB461FC70,0x66CF8120,0xB3C0200C, +0x66573CBB,0xB31EFFCC,0x65DDFBD3,0xB27E9D3C,0x6563BF92,0xB1DEF9E9,0x64E88926, +0xB140175B,0x646C59BF,0xB0A1F71D,0x63EF3290,0xB0049AB3,0x637114CC,0xAF6803A2, +0x62F201AC,0xAECC336C,0x6271FA69,0xAE312B92,0x61F1003F,0xAD96ED92,0x616F146C, +0xACFD7AE8,0x60EC3830,0xAC64D510,0x60686CCF,0xABCCFD83,0x5FE3B38D,0xAB35F5B5, +0x5F5E0DB3,0xAA9FBF1E,0x5ED77C8A,0xAA0A5B2E,0x5E50015D,0xA975CB57,0x5DC79D7C, +0xA8E21106,0x5D3E5237,0xA84F2DAA,0x5CB420E0,0xA7BD22AC,0x5C290ACC,0xA72BF174, +0x5B9D1154,0xA69B9B68,0x5B1035CF,0xA60C21EE,0x5A82799A,0xA57D8666,0x59F3DE12, +0xA4EFCA31,0x59646498,0xA462EEAC,0x58D40E8C,0xA3D6F534,0x5842DD54,0xA34BDF20, +0x57B0D256,0xA2C1ADC9,0x571DEEFA,0xA2386284,0x568A34A9,0xA1AFFEA3,0x55F5A4D2, +0xA1288376,0x556040E2,0xA0A1F24D,0x54CA0A4B,0xA01C4C73,0x5433027D,0x9F979331, +0x539B2AF0,0x9F13C7D0,0x53028518,0x9E90EB94,0x5269126E,0x9E0EFFC1,0x51CED46E, +0x9D8E0597,0x5133CC94,0x9D0DFE54,0x5097FC5E,0x9C8EEB34,0x4FFB654D,0x9C10CD70, +0x4F5E08E3,0x9B93A641,0x4EBFE8A5,0x9B1776DA,0x4E210617,0x9A9C406E,0x4D8162C4, +0x9A22042D,0x4CE10034,0x99A8C345,0x4C3FDFF4,0x99307EE0,0x4B9E0390,0x98B93828, +0x4AFB6C98,0x9842F043,0x4A581C9E,0x97CDA855,0x49B41533,0x9759617F,0x490F57EE, +0x96E61CE0,0x4869E665,0x9673DB94,0x47C3C22F,0x96029EB6,0x471CECE7,0x9592675C, +0x46756828,0x9523369C,0x45CD358F,0x94B50D87,0x452456BD,0x9447ED2F,0x447ACD50, +0x93DBD6A0,0x43D09AED,0x9370CAE4,0x4325C135,0x9306CB04,0x427A41D0,0x929DD806, +0x41CE1E65,0x9235F2EC,0x4121589B,0x91CF1CB6,0x4073F21D,0x91695663,0x3FC5EC98, +0x9104A0EE,0x3F1749B8,0x90A0FD4E,0x3E680B2C,0x903E6C7B,0x3DB832A6,0x8FDCEF66, +0x3D07C1D6,0x8F7C8701,0x3C56BA70,0x8F1D343A,0x3BA51E29,0x8EBEF7FB,0x3AF2EEB7, +0x8E61D32E,0x3A402DD2,0x8E05C6B7,0x398CDD32,0x8DAAD37B,0x38D8FE93,0x8D50FA59, +0x382493B0,0x8CF83C30,0x376F9E46,0x8CA099DA,0x36BA2014,0x8C4A142F,0x36041AD9, +0x8BF4AC05,0x354D9057,0x8BA0622F,0x34968250,0x8B4D377C,0x33DEF287,0x8AFB2CBB, +0x3326E2C3,0x8AAA42B4,0x326E54C7,0x8A5A7A31,0x31B54A5E,0x8A0BD3F5,0x30FBC54D, +0x89BE50C3,0x3041C761,0x8971F15A,0x2F875262,0x8926B677,0x2ECC681E,0x88DCA0D3, +0x2E110A62,0x8893B125,0x2D553AFC,0x884BE821,0x2C98FBBA,0x88054677,0x2BDC4E6F, +0x87BFCCD7,0x2B1F34EB,0x877B7BEC,0x2A61B101,0x8738545E,0x29A3C485,0x86F656D3, +0x28E5714B,0x86B583EE,0x2826B928,0x8675DC4F,0x27679DF4,0x86376092,0x26A82186, +0x85FA1153,0x25E845B6,0x85BDEF28,0x25280C5E,0x8582FAA5,0x24677758,0x8549345C, +0x23A6887F,0x85109CDD,0x22E541AF,0x84D934B1,0x2223A4C5,0x84A2FC62,0x2161B3A0, +0x846DF477,0x209F701C,0x843A1D70,0x1FDCDC1B,0x840777D0,0x1F19F97B,0x83D60412, +0x1E56CA1E,0x83A5C2B0,0x1D934FE5,0x8376B422,0x1CCF8CB3,0x8348D8DC,0x1C0B826A, +0x831C314E,0x1B4732EF,0x82F0BDE8,0x1A82A026,0x82C67F14,0x19BDCBF3,0x829D753A, +0x18F8B83C,0x8275A0C0,0x183366E9,0x824F0208,0x176DD9DE,0x82299971,0x16A81305, +0x82056758,0x15E21445,0x81E26C16,0x151BDF86,0x81C0A801,0x145576B1,0x81A01B6D, +0x138EDBB1,0x8180C6A9,0x12C8106F,0x8162AA04,0x120116D5,0x8145C5C7,0x1139F0CF, +0x812A1A3A,0x1072A048,0x810FA7A0,0x0FAB272B,0x80F66E3C,0x0EE38766,0x80DE6E4C, +0x0E1BC2E4,0x80C7A80A,0x0D53DB92,0x80B21BAF,0x0C8BD35E,0x809DC971,0x0BC3AC35, +0x808AB180,0x0AFB6805,0x8078D40D,0x0A3308BD,0x80683143,0x096A9049,0x8058C94C, +0x08A2009A,0x804A9C4D,0x07D95B9E,0x803DAA6A,0x0710A345,0x8031F3C2,0x0647D97C, +0x80277872,0x057F0035,0x801E3895,0x04B6195D,0x80163440,0x03ED26E6,0x800F6B88, +0x03242ABF,0x8009DE7E,0x025B26D7,0x80058D2F,0x01921D20,0x800277A6,0x00C90F88, +0x80009DEA,0x7FFFFFFF,0x00000000,0x7FF62182,0xFCDBD541,0x7FD8878E,0xF9B82684, +0x7FA736B4,0xF6956FB7,0x7F62368F,0xF3742CA2,0x7F0991C4,0xF054D8D5,0x7E9D55FC, +0xED37EF91,0x7E1D93EA,0xEA1DEBBB,0x7D8A5F40,0xE70747C4,0x7CE3CEB2,0xE3F47D96, +0x7C29FBEE,0xE0E60685,0x7B5D039E,0xDDDC5B3B,0x7A7D055B,0xDAD7F3A2,0x798A23B1, +0xD7D946D8,0x78848414,0xD4E0CB15,0x776C4EDB,0xD1EEF59E,0x7641AF3D,0xCF043AB3, +0x7504D345,0xCC210D79,0x73B5EBD1,0xC945DFEC,0x72552C85,0xC67322CE,0x70E2CBC6, +0xC3A94590,0x6F5F02B2,0xC0E8B648,0x6DCA0D14,0xBE31E19B,0x6C242960,0xBB8532B0, +0x6A6D98A4,0xB8E31319,0x68A69E81,0xB64BEACD,0x66CF8120,0xB3C0200C,0x64E88926, +0xB140175B,0x62F201AC,0xAECC336C,0x60EC3830,0xAC64D510,0x5ED77C8A,0xAA0A5B2E, +0x5CB420E0,0xA7BD22AC,0x5A82799A,0xA57D8666,0x5842DD54,0xA34BDF20,0x55F5A4D2, +0xA1288376,0x539B2AF0,0x9F13C7D0,0x5133CC94,0x9D0DFE54,0x4EBFE8A5,0x9B1776DA, +0x4C3FDFF4,0x99307EE0,0x49B41533,0x9759617F,0x471CECE7,0x9592675C,0x447ACD50, +0x93DBD6A0,0x41CE1E65,0x9235F2EC,0x3F1749B8,0x90A0FD4E,0x3C56BA70,0x8F1D343A, +0x398CDD32,0x8DAAD37B,0x36BA2014,0x8C4A142F,0x33DEF287,0x8AFB2CBB,0x30FBC54D, +0x89BE50C3,0x2E110A62,0x8893B125,0x2B1F34EB,0x877B7BEC,0x2826B928,0x8675DC4F, +0x25280C5E,0x8582FAA5,0x2223A4C5,0x84A2FC62,0x1F19F97B,0x83D60412,0x1C0B826A, +0x831C314E,0x18F8B83C,0x8275A0C0,0x15E21445,0x81E26C16,0x12C8106F,0x8162AA04, +0x0FAB272B,0x80F66E3C,0x0C8BD35E,0x809DC971,0x096A9049,0x8058C94C,0x0647D97C, +0x80277872,0x03242ABF,0x8009DE7E,0x7FFFFFFF,0x00000000,0x7F62368F,0xF3742CA2, +0x7D8A5F40,0xE70747C4,0x7A7D055B,0xDAD7F3A2,0x7641AF3D,0xCF043AB3,0x70E2CBC6, +0xC3A94590,0x6A6D98A4,0xB8E31319,0x62F201AC,0xAECC336C,0x5A82799A,0xA57D8666, +0x5133CC94,0x9D0DFE54,0x471CECE7,0x9592675C,0x3C56BA70,0x8F1D343A,0x30FBC54D, +0x89BE50C3,0x25280C5E,0x8582FAA5,0x18F8B83C,0x8275A0C0,0x0C8BD35E,0x809DC971, +0x7FFFFFFF,0x00000000,0x7641AF3D,0xCF043AB3,0x5A82799A,0xA57D8666,0x30FBC54D, +0x89BE50C3,}; + +q31_t rearranged_twiddle_stride2_1024_q31[680]={ +0x7FFFFFFF,0x00000000,0x7FFD885A,0xFE6DE2E0,0x7FF62182,0xFCDBD541,0x7FE9CBC0, +0xFB49E6A3,0x7FD8878E,0xF9B82684,0x7FC25596,0xF826A462,0x7FA736B4,0xF6956FB7, +0x7F872BF3,0xF50497FB,0x7F62368F,0xF3742CA2,0x7F3857F6,0xF1E43D1C,0x7F0991C4, +0xF054D8D5,0x7ED5E5C6,0xEEC60F31,0x7E9D55FC,0xED37EF91,0x7E5FE493,0xEBAA894F, +0x7E1D93EA,0xEA1DEBBB,0x7DD6668F,0xE8922622,0x7D8A5F40,0xE70747C4,0x7D3980EC, +0xE57D5FDA,0x7CE3CEB2,0xE3F47D96,0x7C894BDE,0xE26CB01B,0x7C29FBEE,0xE0E60685, +0x7BC5E290,0xDF608FE4,0x7B5D039E,0xDDDC5B3B,0x7AEF6323,0xDC597781,0x7A7D055B, +0xDAD7F3A2,0x7A05EEAD,0xD957DE7A,0x798A23B1,0xD7D946D8,0x7909A92D,0xD65C3B7B, +0x78848414,0xD4E0CB15,0x77FAB989,0xD3670446,0x776C4EDB,0xD1EEF59E,0x76D94989, +0xD078AD9E,0x7641AF3D,0xCF043AB3,0x75A585CF,0xCD91AB39,0x7504D345,0xCC210D79, +0x745F9DD1,0xCAB26FA9,0x73B5EBD1,0xC945DFEC,0x7307C3D0,0xC7DB6C50,0x72552C85, +0xC67322CE,0x719E2CD2,0xC50D1149,0x70E2CBC6,0xC3A94590,0x7023109A,0xC247CD5A, +0x6F5F02B2,0xC0E8B648,0x6E96A99D,0xBF8C0DE3,0x6DCA0D14,0xBE31E19B,0x6CF934FC, +0xBCDA3ECB,0x6C242960,0xBB8532B0,0x6B4AF279,0xBA32CA71,0x6A6D98A4,0xB8E31319, +0x698C246C,0xB796199B,0x68A69E81,0xB64BEACD,0x67BD0FBD,0xB5049368,0x66CF8120, +0xB3C0200C,0x65DDFBD3,0xB27E9D3C,0x64E88926,0xB140175B,0x63EF3290,0xB0049AB3, +0x62F201AC,0xAECC336C,0x61F1003F,0xAD96ED92,0x60EC3830,0xAC64D510,0x5FE3B38D, +0xAB35F5B5,0x5ED77C8A,0xAA0A5B2E,0x5DC79D7C,0xA8E21106,0x5CB420E0,0xA7BD22AC, +0x5B9D1154,0xA69B9B68,0x5A82799A,0xA57D8666,0x59646498,0xA462EEAC,0x5842DD54, +0xA34BDF20,0x571DEEFA,0xA2386284,0x55F5A4D2,0xA1288376,0x54CA0A4B,0xA01C4C73, +0x539B2AF0,0x9F13C7D0,0x5269126E,0x9E0EFFC1,0x5133CC94,0x9D0DFE54,0x4FFB654D, +0x9C10CD70,0x4EBFE8A5,0x9B1776DA,0x4D8162C4,0x9A22042D,0x4C3FDFF4,0x99307EE0, +0x4AFB6C98,0x9842F043,0x49B41533,0x9759617F,0x4869E665,0x9673DB94,0x471CECE7, +0x9592675C,0x45CD358F,0x94B50D87,0x447ACD50,0x93DBD6A0,0x4325C135,0x9306CB04, +0x41CE1E65,0x9235F2EC,0x4073F21D,0x91695663,0x3F1749B8,0x90A0FD4E,0x3DB832A6, +0x8FDCEF66,0x3C56BA70,0x8F1D343A,0x3AF2EEB7,0x8E61D32E,0x398CDD32,0x8DAAD37B, +0x382493B0,0x8CF83C30,0x36BA2014,0x8C4A142F,0x354D9057,0x8BA0622F,0x33DEF287, +0x8AFB2CBB,0x326E54C7,0x8A5A7A31,0x30FBC54D,0x89BE50C3,0x2F875262,0x8926B677, +0x2E110A62,0x8893B125,0x2C98FBBA,0x88054677,0x2B1F34EB,0x877B7BEC,0x29A3C485, +0x86F656D3,0x2826B928,0x8675DC4F,0x26A82186,0x85FA1153,0x25280C5E,0x8582FAA5, +0x23A6887F,0x85109CDD,0x2223A4C5,0x84A2FC62,0x209F701C,0x843A1D70,0x1F19F97B, +0x83D60412,0x1D934FE5,0x8376B422,0x1C0B826A,0x831C314E,0x1A82A026,0x82C67F14, +0x18F8B83C,0x8275A0C0,0x176DD9DE,0x82299971,0x15E21445,0x81E26C16,0x145576B1, +0x81A01B6D,0x12C8106F,0x8162AA04,0x1139F0CF,0x812A1A3A,0x0FAB272B,0x80F66E3C, +0x0E1BC2E4,0x80C7A80A,0x0C8BD35E,0x809DC971,0x0AFB6805,0x8078D40D,0x096A9049, +0x8058C94C,0x07D95B9E,0x803DAA6A,0x0647D97C,0x80277872,0x04B6195D,0x80163440, +0x03242ABF,0x8009DE7E,0x01921D20,0x800277A6,0x00000000,0x80000000,0xFE6DE2E0, +0x800277A6,0xFCDBD541,0x8009DE7E,0xFB49E6A3,0x80163440,0xF9B82684,0x80277872, +0xF826A462,0x803DAA6A,0xF6956FB7,0x8058C94C,0xF50497FB,0x8078D40D,0xF3742CA2, +0x809DC971,0xF1E43D1C,0x80C7A80A,0xF054D8D5,0x80F66E3C,0xEEC60F31,0x812A1A3A, +0xED37EF91,0x8162AA04,0xEBAA894F,0x81A01B6D,0xEA1DEBBB,0x81E26C16,0xE8922622, +0x82299971,0xE70747C4,0x8275A0C0,0xE57D5FDA,0x82C67F14,0xE3F47D96,0x831C314E, +0xE26CB01B,0x8376B422,0xE0E60685,0x83D60412,0xDF608FE4,0x843A1D70,0xDDDC5B3B, +0x84A2FC62,0xDC597781,0x85109CDD,0xDAD7F3A2,0x8582FAA5,0xD957DE7A,0x85FA1153, +0xD7D946D8,0x8675DC4F,0xD65C3B7B,0x86F656D3,0xD4E0CB15,0x877B7BEC,0xD3670446, +0x88054677,0xD1EEF59E,0x8893B125,0xD078AD9E,0x8926B677,0xCF043AB3,0x89BE50C3, +0xCD91AB39,0x8A5A7A31,0xCC210D79,0x8AFB2CBB,0xCAB26FA9,0x8BA0622F,0xC945DFEC, +0x8C4A142F,0xC7DB6C50,0x8CF83C30,0xC67322CE,0x8DAAD37B,0xC50D1149,0x8E61D32E, +0xC3A94590,0x8F1D343A,0xC247CD5A,0x8FDCEF66,0xC0E8B648,0x90A0FD4E,0xBF8C0DE3, +0x91695663,0xBE31E19B,0x9235F2EC,0xBCDA3ECB,0x9306CB04,0xBB8532B0,0x93DBD6A0, +0xBA32CA71,0x94B50D87,0xB8E31319,0x9592675C,0xB796199B,0x9673DB94,0xB64BEACD, +0x9759617F,0xB5049368,0x9842F043,0xB3C0200C,0x99307EE0,0xB27E9D3C,0x9A22042D, +0xB140175B,0x9B1776DA,0xB0049AB3,0x9C10CD70,0xAECC336C,0x9D0DFE54,0xAD96ED92, +0x9E0EFFC1,0xAC64D510,0x9F13C7D0,0xAB35F5B5,0xA01C4C73,0xAA0A5B2E,0xA1288376, +0xA8E21106,0xA2386284,0xA7BD22AC,0xA34BDF20,0xA69B9B68,0xA462EEAC,0xA57D8666, +0xA57D8666,0xA462EEAC,0xA69B9B68,0xA34BDF20,0xA7BD22AC,0xA2386284,0xA8E21106, +0xA1288376,0xAA0A5B2E,0xA01C4C73,0xAB35F5B5,0x9F13C7D0,0xAC64D510,0x9E0EFFC1, +0xAD96ED92,0x9D0DFE54,0xAECC336C,0x9C10CD70,0xB0049AB3,0x9B1776DA,0xB140175B, +0x9A22042D,0xB27E9D3C,0x99307EE0,0xB3C0200C,0x9842F043,0xB5049368,0x9759617F, +0xB64BEACD,0x9673DB94,0xB796199B,0x9592675C,0xB8E31319,0x94B50D87,0xBA32CA71, +0x93DBD6A0,0xBB8532B0,0x9306CB04,0xBCDA3ECB,0x9235F2EC,0xBE31E19B,0x91695663, +0xBF8C0DE3,0x90A0FD4E,0xC0E8B648,0x8FDCEF66,0xC247CD5A,0x8F1D343A,0xC3A94590, +0x8E61D32E,0xC50D1149,0x8DAAD37B,0xC67322CE,0x8CF83C30,0xC7DB6C50,0x8C4A142F, +0xC945DFEC,0x8BA0622F,0xCAB26FA9,0x8AFB2CBB,0xCC210D79,0x8A5A7A31,0xCD91AB39, +0x89BE50C3,0xCF043AB3,0x8926B677,0xD078AD9E,0x8893B125,0xD1EEF59E,0x88054677, +0xD3670446,0x877B7BEC,0xD4E0CB15,0x86F656D3,0xD65C3B7B,0x8675DC4F,0xD7D946D8, +0x85FA1153,0xD957DE7A,0x8582FAA5,0xDAD7F3A2,0x85109CDD,0xDC597781,0x84A2FC62, +0xDDDC5B3B,0x843A1D70,0xDF608FE4,0x83D60412,0xE0E60685,0x8376B422,0xE26CB01B, +0x831C314E,0xE3F47D96,0x82C67F14,0xE57D5FDA,0x8275A0C0,0xE70747C4,0x82299971, +0xE8922622,0x81E26C16,0xEA1DEBBB,0x81A01B6D,0xEBAA894F,0x8162AA04,0xED37EF91, +0x812A1A3A,0xEEC60F31,0x80F66E3C,0xF054D8D5,0x80C7A80A,0xF1E43D1C,0x809DC971, +0xF3742CA2,0x8078D40D,0xF50497FB,0x8058C94C,0xF6956FB7,0x803DAA6A,0xF826A462, +0x80277872,0xF9B82684,0x80163440,0xFB49E6A3,0x8009DE7E,0xFCDBD541,0x800277A6, +0xFE6DE2E0,0x7FFFFFFF,0x00000000,0x7FD8878E,0xF9B82684,0x7F62368F,0xF3742CA2, +0x7E9D55FC,0xED37EF91,0x7D8A5F40,0xE70747C4,0x7C29FBEE,0xE0E60685,0x7A7D055B, +0xDAD7F3A2,0x78848414,0xD4E0CB15,0x7641AF3D,0xCF043AB3,0x73B5EBD1,0xC945DFEC, +0x70E2CBC6,0xC3A94590,0x6DCA0D14,0xBE31E19B,0x6A6D98A4,0xB8E31319,0x66CF8120, +0xB3C0200C,0x62F201AC,0xAECC336C,0x5ED77C8A,0xAA0A5B2E,0x5A82799A,0xA57D8666, +0x55F5A4D2,0xA1288376,0x5133CC94,0x9D0DFE54,0x4C3FDFF4,0x99307EE0,0x471CECE7, +0x9592675C,0x41CE1E65,0x9235F2EC,0x3C56BA70,0x8F1D343A,0x36BA2014,0x8C4A142F, +0x30FBC54D,0x89BE50C3,0x2B1F34EB,0x877B7BEC,0x25280C5E,0x8582FAA5,0x1F19F97B, +0x83D60412,0x18F8B83C,0x8275A0C0,0x12C8106F,0x8162AA04,0x0C8BD35E,0x809DC971, +0x0647D97C,0x80277872,0x00000000,0x80000000,0xF9B82684,0x80277872,0xF3742CA2, +0x809DC971,0xED37EF91,0x8162AA04,0xE70747C4,0x8275A0C0,0xE0E60685,0x83D60412, +0xDAD7F3A2,0x8582FAA5,0xD4E0CB15,0x877B7BEC,0xCF043AB3,0x89BE50C3,0xC945DFEC, +0x8C4A142F,0xC3A94590,0x8F1D343A,0xBE31E19B,0x9235F2EC,0xB8E31319,0x9592675C, +0xB3C0200C,0x99307EE0,0xAECC336C,0x9D0DFE54,0xAA0A5B2E,0xA1288376,0xA57D8666, +0xA57D8666,0xA1288376,0xAA0A5B2E,0x9D0DFE54,0xAECC336C,0x99307EE0,0xB3C0200C, +0x9592675C,0xB8E31319,0x9235F2EC,0xBE31E19B,0x8F1D343A,0xC3A94590,0x8C4A142F, +0xC945DFEC,0x89BE50C3,0xCF043AB3,0x877B7BEC,0xD4E0CB15,0x8582FAA5,0xDAD7F3A2, +0x83D60412,0xE0E60685,0x8275A0C0,0xE70747C4,0x8162AA04,0xED37EF91,0x809DC971, +0xF3742CA2,0x80277872,0xF9B82684,0x7FFFFFFF,0x00000000,0x7D8A5F40,0xE70747C4, +0x7641AF3D,0xCF043AB3,0x6A6D98A4,0xB8E31319,0x5A82799A,0xA57D8666,0x471CECE7, +0x9592675C,0x30FBC54D,0x89BE50C3,0x18F8B83C,0x8275A0C0,0x00000000,0x80000000, +0xE70747C4,0x8275A0C0,0xCF043AB3,0x89BE50C3,0xB8E31319,0x9592675C,0xA57D8666, +0xA57D8666,0x9592675C,0xB8E31319,0x89BE50C3,0xCF043AB3,0x8275A0C0,0xE70747C4, +0x7FFFFFFF,0x00000000,0x5A82799A,0xA57D8666,0x00000000,0x80000000,0xA57D8666, +0xA57D8666,}; + +q31_t rearranged_twiddle_stride3_1024_q31[680]={ +0x7FFFFFFF,0x00000000,0x7FFA72D1,0xFDA4D929,0x7FE9CBC0,0xFB49E6A3,0x7FCE0C3E, +0xF8EF5CBB,0x7FA736B4,0xF6956FB7,0x7F754E80,0xF43C53CB,0x7F3857F6,0xF1E43D1C, +0x7EF05860,0xEF8D5FB8,0x7E9D55FC,0xED37EF91,0x7E3F57FF,0xEAE4207A,0x7DD6668F, +0xE8922622,0x7D628AC6,0xE642340D,0x7CE3CEB2,0xE3F47D96,0x7C5A3D50,0xE1A935E2, +0x7BC5E290,0xDF608FE4,0x7B26CB4F,0xDD1ABE51,0x7A7D055B,0xDAD7F3A2,0x79C89F6E, +0xD898620C,0x7909A92D,0xD65C3B7B,0x78403329,0xD423B191,0x776C4EDB,0xD1EEF59E, +0x768E0EA6,0xCFBE389F,0x75A585CF,0xCD91AB39,0x74B2C884,0xCB697DB0,0x73B5EBD1, +0xC945DFEC,0x72AF05A7,0xC727016D,0x719E2CD2,0xC50D1149,0x708378FF,0xC2F83E2A, +0x6F5F02B2,0xC0E8B648,0x6E30E34A,0xBEDEA765,0x6CF934FC,0xBCDA3ECB,0x6BB812D1, +0xBADBA943,0x6A6D98A4,0xB8E31319,0x6919E320,0xB6F0A812,0x67BD0FBD,0xB5049368, +0x66573CBB,0xB31EFFCC,0x64E88926,0xB140175B,0x637114CC,0xAF6803A2,0x61F1003F, +0xAD96ED92,0x60686CCF,0xABCCFD83,0x5ED77C8A,0xAA0A5B2E,0x5D3E5237,0xA84F2DAA, +0x5B9D1154,0xA69B9B68,0x59F3DE12,0xA4EFCA31,0x5842DD54,0xA34BDF20,0x568A34A9, +0xA1AFFEA3,0x54CA0A4B,0xA01C4C73,0x53028518,0x9E90EB94,0x5133CC94,0x9D0DFE54, +0x4F5E08E3,0x9B93A641,0x4D8162C4,0x9A22042D,0x4B9E0390,0x98B93828,0x49B41533, +0x9759617F,0x47C3C22F,0x96029EB6,0x45CD358F,0x94B50D87,0x43D09AED,0x9370CAE4, +0x41CE1E65,0x9235F2EC,0x3FC5EC98,0x9104A0EE,0x3DB832A6,0x8FDCEF66,0x3BA51E29, +0x8EBEF7FB,0x398CDD32,0x8DAAD37B,0x376F9E46,0x8CA099DA,0x354D9057,0x8BA0622F, +0x3326E2C3,0x8AAA42B4,0x30FBC54D,0x89BE50C3,0x2ECC681E,0x88DCA0D3,0x2C98FBBA, +0x88054677,0x2A61B101,0x8738545E,0x2826B928,0x8675DC4F,0x25E845B6,0x85BDEF28, +0x23A6887F,0x85109CDD,0x2161B3A0,0x846DF477,0x1F19F97B,0x83D60412,0x1CCF8CB3, +0x8348D8DC,0x1A82A026,0x82C67F14,0x183366E9,0x824F0208,0x15E21445,0x81E26C16, +0x138EDBB1,0x8180C6A9,0x1139F0CF,0x812A1A3A,0x0EE38766,0x80DE6E4C,0x0C8BD35E, +0x809DC971,0x0A3308BD,0x80683143,0x07D95B9E,0x803DAA6A,0x057F0035,0x801E3895, +0x03242ABF,0x8009DE7E,0x00C90F88,0x80009DEA,0xFE6DE2E0,0x800277A6,0xFC12D91A, +0x800F6B88,0xF9B82684,0x80277872,0xF75DFF66,0x804A9C4D,0xF50497FB,0x8078D40D, +0xF2AC246E,0x80B21BAF,0xF054D8D5,0x80F66E3C,0xEDFEE92B,0x8145C5C7,0xEBAA894F, +0x81A01B6D,0xE957ECFB,0x82056758,0xE70747C4,0x8275A0C0,0xE4B8CD11,0x82F0BDE8, +0xE26CB01B,0x8376B422,0xE02323E5,0x840777D0,0xDDDC5B3B,0x84A2FC62,0xDB9888A8, +0x8549345C,0xD957DE7A,0x85FA1153,0xD71A8EB5,0x86B583EE,0xD4E0CB15,0x877B7BEC, +0xD2AAC504,0x884BE821,0xD078AD9E,0x8926B677,0xCE4AB5A2,0x8A0BD3F5,0xCC210D79, +0x8AFB2CBB,0xC9FBE527,0x8BF4AC05,0xC7DB6C50,0x8CF83C30,0xC5BFD22E,0x8E05C6B7, +0xC3A94590,0x8F1D343A,0xC197F4D4,0x903E6C7B,0xBF8C0DE3,0x91695663,0xBD85BE30, +0x929DD806,0xBB8532B0,0x93DBD6A0,0xB98A97D8,0x9523369C,0xB796199B,0x9673DB94, +0xB5A7E362,0x97CDA855,0xB3C0200C,0x99307EE0,0xB1DEF9E9,0x9A9C406E,0xB0049AB3, +0x9C10CD70,0xAE312B92,0x9D8E0597,0xAC64D510,0x9F13C7D0,0xAA9FBF1E,0xA0A1F24D, +0xA8E21106,0xA2386284,0xA72BF174,0xA3D6F534,0xA57D8666,0xA57D8666,0xA3D6F534, +0xA72BF174,0xA2386284,0xA8E21106,0xA0A1F24D,0xAA9FBF1E,0x9F13C7D0,0xAC64D510, +0x9D8E0597,0xAE312B92,0x9C10CD70,0xB0049AB3,0x9A9C406E,0xB1DEF9E9,0x99307EE0, +0xB3C0200C,0x97CDA855,0xB5A7E362,0x9673DB94,0xB796199B,0x9523369C,0xB98A97D8, +0x93DBD6A0,0xBB8532B0,0x929DD806,0xBD85BE30,0x91695663,0xBF8C0DE3,0x903E6C7B, +0xC197F4D4,0x8F1D343A,0xC3A94590,0x8E05C6B7,0xC5BFD22E,0x8CF83C30,0xC7DB6C50, +0x8BF4AC05,0xC9FBE527,0x8AFB2CBB,0xCC210D79,0x8A0BD3F5,0xCE4AB5A2,0x8926B677, +0xD078AD9E,0x884BE821,0xD2AAC504,0x877B7BEC,0xD4E0CB15,0x86B583EE,0xD71A8EB5, +0x85FA1153,0xD957DE7A,0x8549345C,0xDB9888A8,0x84A2FC62,0xDDDC5B3B,0x840777D0, +0xE02323E5,0x8376B422,0xE26CB01B,0x82F0BDE8,0xE4B8CD11,0x8275A0C0,0xE70747C4, +0x82056758,0xE957ECFB,0x81A01B6D,0xEBAA894F,0x8145C5C7,0xEDFEE92B,0x80F66E3C, +0xF054D8D5,0x80B21BAF,0xF2AC246E,0x8078D40D,0xF50497FB,0x804A9C4D,0xF75DFF66, +0x80277872,0xF9B82684,0x800F6B88,0xFC12D91A,0x800277A6,0xFE6DE2E0,0x80009DEA, +0x00C90F88,0x8009DE7E,0x03242ABF,0x801E3895,0x057F0035,0x803DAA6A,0x07D95B9E, +0x80683143,0x0A3308BD,0x809DC971,0x0C8BD35E,0x80DE6E4C,0x0EE38766,0x812A1A3A, +0x1139F0CF,0x8180C6A9,0x138EDBB1,0x81E26C16,0x15E21445,0x824F0208,0x183366E9, +0x82C67F14,0x1A82A026,0x8348D8DC,0x1CCF8CB3,0x83D60412,0x1F19F97B,0x846DF477, +0x2161B3A0,0x85109CDD,0x23A6887F,0x85BDEF28,0x25E845B6,0x8675DC4F,0x2826B928, +0x8738545E,0x2A61B101,0x88054677,0x2C98FBBA,0x88DCA0D3,0x2ECC681E,0x89BE50C3, +0x30FBC54D,0x8AAA42B4,0x3326E2C3,0x8BA0622F,0x354D9057,0x8CA099DA,0x376F9E46, +0x8DAAD37B,0x398CDD32,0x8EBEF7FB,0x3BA51E29,0x8FDCEF66,0x3DB832A6,0x9104A0EE, +0x3FC5EC98,0x9235F2EC,0x41CE1E65,0x9370CAE4,0x43D09AED,0x94B50D87,0x45CD358F, +0x96029EB6,0x47C3C22F,0x9759617F,0x49B41533,0x98B93828,0x4B9E0390,0x9A22042D, +0x4D8162C4,0x9B93A641,0x4F5E08E3,0x9D0DFE54,0x5133CC94,0x9E90EB94,0x53028518, +0xA01C4C73,0x54CA0A4B,0xA1AFFEA3,0x568A34A9,0xA34BDF20,0x5842DD54,0xA4EFCA31, +0x59F3DE12,0xA69B9B68,0x5B9D1154,0xA84F2DAA,0x5D3E5237,0xAA0A5B2E,0x5ED77C8A, +0xABCCFD83,0x60686CCF,0xAD96ED92,0x61F1003F,0xAF6803A2,0x637114CC,0xB140175B, +0x64E88926,0xB31EFFCC,0x66573CBB,0xB5049368,0x67BD0FBD,0xB6F0A812,0x6919E320, +0xB8E31319,0x6A6D98A4,0xBADBA943,0x6BB812D1,0xBCDA3ECB,0x6CF934FC,0xBEDEA765, +0x6E30E34A,0xC0E8B648,0x6F5F02B2,0xC2F83E2A,0x708378FF,0xC50D1149,0x719E2CD2, +0xC727016D,0x72AF05A7,0xC945DFEC,0x73B5EBD1,0xCB697DB0,0x74B2C884,0xCD91AB39, +0x75A585CF,0xCFBE389F,0x768E0EA6,0xD1EEF59E,0x776C4EDB,0xD423B191,0x78403329, +0xD65C3B7B,0x7909A92D,0xD898620C,0x79C89F6E,0xDAD7F3A2,0x7A7D055B,0xDD1ABE51, +0x7B26CB4F,0xDF608FE4,0x7BC5E290,0xE1A935E2,0x7C5A3D50,0xE3F47D96,0x7CE3CEB2, +0xE642340D,0x7D628AC6,0xE8922622,0x7DD6668F,0xEAE4207A,0x7E3F57FF,0xED37EF91, +0x7E9D55FC,0xEF8D5FB8,0x7EF05860,0xF1E43D1C,0x7F3857F6,0xF43C53CB,0x7F754E80, +0xF6956FB7,0x7FA736B4,0xF8EF5CBB,0x7FCE0C3E,0xFB49E6A3,0x7FE9CBC0,0xFDA4D929, +0x7FFA72D1,0x7FFFFFFF,0x00000000,0x7FA736B4,0xF6956FB7,0x7E9D55FC,0xED37EF91, +0x7CE3CEB2,0xE3F47D96,0x7A7D055B,0xDAD7F3A2,0x776C4EDB,0xD1EEF59E,0x73B5EBD1, +0xC945DFEC,0x6F5F02B2,0xC0E8B648,0x6A6D98A4,0xB8E31319,0x64E88926,0xB140175B, +0x5ED77C8A,0xAA0A5B2E,0x5842DD54,0xA34BDF20,0x5133CC94,0x9D0DFE54,0x49B41533, +0x9759617F,0x41CE1E65,0x9235F2EC,0x398CDD32,0x8DAAD37B,0x30FBC54D,0x89BE50C3, +0x2826B928,0x8675DC4F,0x1F19F97B,0x83D60412,0x15E21445,0x81E26C16,0x0C8BD35E, +0x809DC971,0x03242ABF,0x8009DE7E,0xF9B82684,0x80277872,0xF054D8D5,0x80F66E3C, +0xE70747C4,0x8275A0C0,0xDDDC5B3B,0x84A2FC62,0xD4E0CB15,0x877B7BEC,0xCC210D79, +0x8AFB2CBB,0xC3A94590,0x8F1D343A,0xBB8532B0,0x93DBD6A0,0xB3C0200C,0x99307EE0, +0xAC64D510,0x9F13C7D0,0xA57D8666,0xA57D8666,0x9F13C7D0,0xAC64D510,0x99307EE0, +0xB3C0200C,0x93DBD6A0,0xBB8532B0,0x8F1D343A,0xC3A94590,0x8AFB2CBB,0xCC210D79, +0x877B7BEC,0xD4E0CB15,0x84A2FC62,0xDDDC5B3B,0x8275A0C0,0xE70747C4,0x80F66E3C, +0xF054D8D5,0x80277872,0xF9B82684,0x8009DE7E,0x03242ABF,0x809DC971,0x0C8BD35E, +0x81E26C16,0x15E21445,0x83D60412,0x1F19F97B,0x8675DC4F,0x2826B928,0x89BE50C3, +0x30FBC54D,0x8DAAD37B,0x398CDD32,0x9235F2EC,0x41CE1E65,0x9759617F,0x49B41533, +0x9D0DFE54,0x5133CC94,0xA34BDF20,0x5842DD54,0xAA0A5B2E,0x5ED77C8A,0xB140175B, +0x64E88926,0xB8E31319,0x6A6D98A4,0xC0E8B648,0x6F5F02B2,0xC945DFEC,0x73B5EBD1, +0xD1EEF59E,0x776C4EDB,0xDAD7F3A2,0x7A7D055B,0xE3F47D96,0x7CE3CEB2,0xED37EF91, +0x7E9D55FC,0xF6956FB7,0x7FA736B4,0x7FFFFFFF,0x00000000,0x7A7D055B,0xDAD7F3A2, +0x6A6D98A4,0xB8E31319,0x5133CC94,0x9D0DFE54,0x30FBC54D,0x89BE50C3,0x0C8BD35E, +0x809DC971,0xE70747C4,0x8275A0C0,0xC3A94590,0x8F1D343A,0xA57D8666,0xA57D8666, +0x8F1D343A,0xC3A94590,0x8275A0C0,0xE70747C4,0x809DC971,0x0C8BD35E,0x89BE50C3, +0x30FBC54D,0x9D0DFE54,0x5133CC94,0xB8E31319,0x6A6D98A4,0xDAD7F3A2,0x7A7D055B, +0x7FFFFFFF,0x00000000,0x30FBC54D,0x89BE50C3,0xA57D8666,0xA57D8666,0x89BE50C3, +0x30FBC54D,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q31_8192) + +uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6]={ +0,2048,2560,2688,2720,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6]={ +0,2048,2560,2688,2720,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6]={ +0,2048,2560,2688,2720,0,}; + +q31_t rearranged_twiddle_stride1_4096_q31[2728]={ +0x7FFFFFFF,0x00000000,0x7FFFF621,0xFFCDBC0B,0x7FFFD886,0xFF9B781D,0x7FFFA72C, +0xFF69343F,0x7FFF6216,0xFF36F078,0x7FFF0943,0xFF04ACD0,0x7FFE9CB2,0xFED2694F, +0x7FFE1C65,0xFEA025FD,0x7FFD885A,0xFE6DE2E0,0x7FFCE093,0xFE3BA002,0x7FFC250F, +0xFE095D69,0x7FFB55CE,0xFDD71B1E,0x7FFA72D1,0xFDA4D929,0x7FF97C18,0xFD729790, +0x7FF871A2,0xFD40565C,0x7FF75370,0xFD0E1594,0x7FF62182,0xFCDBD541,0x7FF4DBD9, +0xFCA9956A,0x7FF38274,0xFC775616,0x7FF21553,0xFC45174E,0x7FF09478,0xFC12D91A, +0x7FEEFFE1,0xFBE09B80,0x7FED5791,0xFBAE5E89,0x7FEB9B85,0xFB7C223D,0x7FE9CBC0, +0xFB49E6A3,0x7FE7E841,0xFB17ABC2,0x7FE5F108,0xFAE571A4,0x7FE3E616,0xFAB3384F, +0x7FE1C76B,0xFA80FFCB,0x7FDF9508,0xFA4EC821,0x7FDD4EEC,0xFA1C9157,0x7FDAF519, +0xF9EA5B75,0x7FD8878E,0xF9B82684,0x7FD6064C,0xF985F28A,0x7FD37153,0xF953BF91, +0x7FD0C8A3,0xF9218D9E,0x7FCE0C3E,0xF8EF5CBB,0x7FCB3C23,0xF8BD2CEF,0x7FC85854, +0xF88AFE42,0x7FC560CF,0xF858D0BB,0x7FC25596,0xF826A462,0x7FBF36AA,0xF7F4793E, +0x7FBC040A,0xF7C24F59,0x7FB8BDB8,0xF79026B9,0x7FB563B3,0xF75DFF66,0x7FB1F5FC, +0xF72BD967,0x7FAE7495,0xF6F9B4C6,0x7FAADF7C,0xF6C79188,0x7FA736B4,0xF6956FB7, +0x7FA37A3C,0xF6634F59,0x7F9FAA15,0xF6313077,0x7F9BC640,0xF5FF1318,0x7F97CEBD, +0xF5CCF743,0x7F93C38C,0xF59ADD02,0x7F8FA4B0,0xF568C45B,0x7F8B7227,0xF536AD56, +0x7F872BF3,0xF50497FB,0x7F82D214,0xF4D28451,0x7F7E648C,0xF4A07261,0x7F79E35A, +0xF46E6231,0x7F754E80,0xF43C53CB,0x7F70A5FE,0xF40A4735,0x7F6BE9D4,0xF3D83C77, +0x7F671A05,0xF3A63398,0x7F62368F,0xF3742CA2,0x7F5D3F75,0xF342279B,0x7F5834B7, +0xF310248A,0x7F531655,0xF2DE2379,0x7F4DE451,0xF2AC246E,0x7F489EAA,0xF27A2771, +0x7F434563,0xF2482C8A,0x7F3DD87C,0xF21633C0,0x7F3857F6,0xF1E43D1C,0x7F32C3D1, +0xF1B248A5,0x7F2D1C0E,0xF1805662,0x7F2760AF,0xF14E665C,0x7F2191B4,0xF11C789A, +0x7F1BAF1E,0xF0EA8D24,0x7F15B8EE,0xF0B8A401,0x7F0FAF25,0xF086BD39,0x7F0991C4, +0xF054D8D5,0x7F0360CB,0xF022F6DA,0x7EFD1C3C,0xEFF11753,0x7EF6C418,0xEFBF3A45, +0x7EF05860,0xEF8D5FB8,0x7EE9D914,0xEF5B87B5,0x7EE34636,0xEF29B243,0x7EDC9FC6, +0xEEF7DF6A,0x7ED5E5C6,0xEEC60F31,0x7ECF1837,0xEE9441A0,0x7EC8371A,0xEE6276BF, +0x7EC14270,0xEE30AE96,0x7EBA3A39,0xEDFEE92B,0x7EB31E78,0xEDCD2687,0x7EABEF2C, +0xED9B66B2,0x7EA4AC58,0xED69A9B3,0x7E9D55FC,0xED37EF91,0x7E95EC1A,0xED063856, +0x7E8E6EB2,0xECD48407,0x7E86DDC6,0xECA2D2AD,0x7E7F3957,0xEC71244F,0x7E778166, +0xEC3F78F6,0x7E6FB5F4,0xEC0DD0A8,0x7E67D703,0xEBDC2B6E,0x7E5FE493,0xEBAA894F, +0x7E57DEA7,0xEB78EA52,0x7E4FC53E,0xEB474E81,0x7E47985B,0xEB15B5E1,0x7E3F57FF, +0xEAE4207A,0x7E37042A,0xEAB28E56,0x7E2E9CDF,0xEA80FF7A,0x7E26221F,0xEA4F73EE, +0x7E1D93EA,0xEA1DEBBB,0x7E14F242,0xE9EC66E8,0x7E0C3D29,0xE9BAE57D,0x7E0374A0, +0xE9896781,0x7DFA98A8,0xE957ECFB,0x7DF1A942,0xE92675F4,0x7DE8A670,0xE8F50273, +0x7DDF9034,0xE8C39280,0x7DD6668F,0xE8922622,0x7DCD2981,0xE860BD61,0x7DC3D90D, +0xE82F5844,0x7DBA7534,0xE7FDF6D4,0x7DB0FDF8,0xE7CC9917,0x7DA77359,0xE79B3F16, +0x7D9DD55A,0xE769E8D8,0x7D9423FC,0xE7389665,0x7D8A5F40,0xE70747C4,0x7D808728, +0xE6D5FCFC,0x7D769BB5,0xE6A4B616,0x7D6C9CE9,0xE6737319,0x7D628AC6,0xE642340D, +0x7D58654D,0xE610F8F9,0x7D4E2C7F,0xE5DFC1E5,0x7D43E05E,0xE5AE8ED8,0x7D3980EC, +0xE57D5FDA,0x7D2F0E2B,0xE54C34F3,0x7D24881B,0xE51B0E2A,0x7D19EEBF,0xE4E9EB87, +0x7D0F4218,0xE4B8CD11,0x7D048228,0xE487B2D0,0x7CF9AEF0,0xE4569CCB,0x7CEEC873, +0xE4258B0A,0x7CE3CEB2,0xE3F47D96,0x7CD8C1AE,0xE3C37474,0x7CCDA169,0xE3926FAD, +0x7CC26DE5,0xE3616F48,0x7CB72724,0xE330734D,0x7CABCD28,0xE2FF7BC3,0x7CA05FF1, +0xE2CE88B3,0x7C94DF83,0xE29D9A23,0x7C894BDE,0xE26CB01B,0x7C7DA505,0xE23BCAA2, +0x7C71EAF9,0xE20AE9C1,0x7C661DBC,0xE1DA0D7E,0x7C5A3D50,0xE1A935E2,0x7C4E49B7, +0xE17862F3,0x7C4242F2,0xE14794BA,0x7C362904,0xE116CB3D,0x7C29FBEE,0xE0E60685, +0x7C1DBBB3,0xE0B54698,0x7C116853,0xE0848B7F,0x7C0501D2,0xE053D541,0x7BF88830, +0xE02323E5,0x7BEBFB70,0xDFF27773,0x7BDF5B94,0xDFC1CFF3,0x7BD2A89E,0xDF912D6B, +0x7BC5E290,0xDF608FE4,0x7BB9096B,0xDF2FF764,0x7BAC1D31,0xDEFF63F4,0x7B9F1DE6, +0xDECED59B,0x7B920B89,0xDE9E4C60,0x7B84E61F,0xDE6DC84B,0x7B77ADA8,0xDE3D4964, +0x7B6A6227,0xDE0CCFB1,0x7B5D039E,0xDDDC5B3B,0x7B4F920E,0xDDABEC08,0x7B420D7A, +0xDD7B8220,0x7B3475E5,0xDD4B1D8C,0x7B26CB4F,0xDD1ABE51,0x7B190DBC,0xDCEA6478, +0x7B0B3D2C,0xDCBA1008,0x7AFD59A4,0xDC89C109,0x7AEF6323,0xDC597781,0x7AE159AE, +0xDC293379,0x7AD33D45,0xDBF8F4F8,0x7AC50DEC,0xDBC8BC06,0x7AB6CBA4,0xDB9888A8, +0x7AA8766F,0xDB685AE9,0x7A9A0E50,0xDB3832CD,0x7A8B9348,0xDB08105E,0x7A7D055B, +0xDAD7F3A2,0x7A6E648A,0xDAA7DCA1,0x7A5FB0D8,0xDA77CB63,0x7A50EA47,0xDA47BFEE, +0x7A4210D8,0xDA17BA4A,0x7A332490,0xD9E7BA7F,0x7A24256F,0xD9B7C094,0x7A151378, +0xD987CC90,0x7A05EEAD,0xD957DE7A,0x79F6B711,0xD927F65B,0x79E76CA7,0xD8F81439, +0x79D80F6F,0xD8C8381D,0x79C89F6E,0xD898620C,0x79B91CA4,0xD868920F,0x79A98715, +0xD838C82D,0x7999DEC4,0xD809046E,0x798A23B1,0xD7D946D8,0x797A55E0,0xD7A98F73, +0x796A7554,0xD779DE47,0x795A820E,0xD74A335B,0x794A7C12,0xD71A8EB5,0x793A6361, +0xD6EAF05F,0x792A37FE,0xD6BB585E,0x7919F9EC,0xD68BC6BA,0x7909A92D,0xD65C3B7B, +0x78F945C3,0xD62CB6A8,0x78E8CFB2,0xD5FD3848,0x78D846FB,0xD5CDC062,0x78C7ABA2, +0xD59E4EFF,0x78B6FDA8,0xD56EE424,0x78A63D11,0xD53F7FDA,0x789569DF,0xD5102228, +0x78848414,0xD4E0CB15,0x78738BB3,0xD4B17AA8,0x786280BF,0xD48230E9,0x7851633B, +0xD452EDDF,0x78403329,0xD423B191,0x782EF08B,0xD3F47C06,0x781D9B65,0xD3C54D47, +0x780C33B8,0xD396255A,0x77FAB989,0xD3670446,0x77E92CD9,0xD337EA12,0x77D78DAA, +0xD308D6C7,0x77C5DC01,0xD2D9CA6A,0x77B417DF,0xD2AAC504,0x77A24148,0xD27BC69C, +0x7790583E,0xD24CCF39,0x777E5CC3,0xD21DDEE2,0x776C4EDB,0xD1EEF59E,0x775A2E89, +0xD1C01375,0x7747FBCE,0xD191386E,0x7735B6AF,0xD1626490,0x77235F2D,0xD13397E2, +0x7710F54C,0xD104D26B,0x76FE790E,0xD0D61434,0x76EBEA77,0xD0A75D42,0x76D94989, +0xD078AD9E,0x76C69647,0xD04A054E,0x76B3D0B4,0xD01B6459,0x76A0F8D2,0xCFECCAC7, +0x768E0EA6,0xCFBE389F,0x767B1231,0xCF8FADE9,0x76680376,0xCF612AAA,0x7654E279, +0xCF32AEEB,0x7641AF3D,0xCF043AB3,0x762E69C4,0xCED5CE08,0x761B1211,0xCEA768F2, +0x7607A828,0xCE790B79,0x75F42C0B,0xCE4AB5A2,0x75E09DBD,0xCE1C6777,0x75CCFD42, +0xCDEE20FC,0x75B94A9C,0xCDBFE23A,0x75A585CF,0xCD91AB39,0x7591AEDD,0xCD637BFE, +0x757DC5CA,0xCD355491,0x7569CA99,0xCD0734F9,0x7555BD4C,0xCCD91D3D,0x75419DE7, +0xCCAB0D65,0x752D6C6C,0xCC7D0578,0x751928E0,0xCC4F057C,0x7504D345,0xCC210D79, +0x74F06B9E,0xCBF31D75,0x74DBF1EF,0xCBC53579,0x74C7663A,0xCB97558A,0x74B2C884, +0xCB697DB0,0x749E18CD,0xCB3BADF3,0x7489571C,0xCB0DE658,0x74748371,0xCAE026E8, +0x745F9DD1,0xCAB26FA9,0x744AA63F,0xCA84C0A3,0x74359CBD,0xCA5719DB,0x74208150, +0xCA297B5A,0x740B53FB,0xC9FBE527,0x73F614C0,0xC9CE5748,0x73E0C3A3,0xC9A0D1C5, +0x73CB60A8,0xC97354A4,0x73B5EBD1,0xC945DFEC,0x73A06522,0xC91873A5,0x738ACC9E, +0xC8EB0FD6,0x73752249,0xC8BDB485,0x735F6626,0xC89061BA,0x73499838,0xC863177B, +0x7333B883,0xC835D5D0,0x731DC70A,0xC8089CBF,0x7307C3D0,0xC7DB6C50,0x72F1AED9, +0xC7AE4489,0x72DB8828,0xC7812572,0x72C54FC1,0xC7540F11,0x72AF05A7,0xC727016D, +0x7298A9DD,0xC6F9FC8D,0x72823C67,0xC6CD0079,0x726BBD48,0xC6A00D37,0x72552C85, +0xC67322CE,0x723E8A20,0xC6464144,0x7227D61C,0xC61968A2,0x7211107E,0xC5EC98EE, +0x71FA3949,0xC5BFD22E,0x71E35080,0xC593146A,0x71CC5626,0xC5665FA9,0x71B54A41, +0xC539B3F1,0x719E2CD2,0xC50D1149,0x7186FDDE,0xC4E077B8,0x716FBD68,0xC4B3E746, +0x71586B74,0xC4875FF9,0x71410805,0xC45AE1D7,0x7129931F,0xC42E6CE8,0x71120CC5, +0xC4020133,0x70FA74FC,0xC3D59EBE,0x70E2CBC6,0xC3A94590,0x70CB1128,0xC37CF5B0, +0x70B34525,0xC350AF26,0x709B67C0,0xC32471F7,0x708378FF,0xC2F83E2A,0x706B78E3, +0xC2CC13C7,0x70536771,0xC29FF2D4,0x703B44AD,0xC273DB58,0x7023109A,0xC247CD5A, +0x700ACB3C,0xC21BC8E1,0x6FF27497,0xC1EFCDF3,0x6FDA0CAE,0xC1C3DC97,0x6FC19385, +0xC197F4D4,0x6FA90921,0xC16C16B0,0x6F906D84,0xC1404233,0x6F77C0B3,0xC1147764, +0x6F5F02B2,0xC0E8B648,0x6F463383,0xC0BCFEE7,0x6F2D532C,0xC0915148,0x6F1461B0, +0xC065AD70,0x6EFB5F12,0xC03A1368,0x6EE24B57,0xC00E8336,0x6EC92683,0xBFE2FCDF, +0x6EAFF099,0xBFB7806C,0x6E96A99D,0xBF8C0DE3,0x6E7D5193,0xBF60A54A,0x6E63E87F, +0xBF3546A8,0x6E4A6E66,0xBF09F205,0x6E30E34A,0xBEDEA765,0x6E174730,0xBEB366D1, +0x6DFD9A1C,0xBE88304F,0x6DE3DC11,0xBE5D03E6,0x6DCA0D14,0xBE31E19B,0x6DB02D29, +0xBE06C977,0x6D963C54,0xBDDBBB7F,0x6D7C3A98,0xBDB0B7BB,0x6D6227FA,0xBD85BE30, +0x6D48047E,0xBD5ACEE5,0x6D2DD027,0xBD2FE9E2,0x6D138AFB,0xBD050F2C,0x6CF934FC, +0xBCDA3ECB,0x6CDECE2F,0xBCAF78C4,0x6CC45698,0xBC84BD1F,0x6CA9CE3B,0xBC5A0BE2, +0x6C8F351C,0xBC2F6513,0x6C748B3F,0xBC04C8BA,0x6C59D0A9,0xBBDA36DD,0x6C3F055D, +0xBBAFAF82,0x6C242960,0xBB8532B0,0x6C093CB6,0xBB5AC06D,0x6BEE3F62,0xBB3058C0, +0x6BD3316A,0xBB05FBB0,0x6BB812D1,0xBADBA943,0x6B9CE39B,0xBAB16180,0x6B81A3CD, +0xBA87246D,0x6B66536B,0xBA5CF210,0x6B4AF279,0xBA32CA71,0x6B2F80FB,0xBA08AD95, +0x6B13FEF5,0xB9DE9B83,0x6AF86C6C,0xB9B49442,0x6ADCC964,0xB98A97D8,0x6AC115E2, +0xB960A64C,0x6AA551E9,0xB936BFA4,0x6A897D7D,0xB90CE3E6,0x6A6D98A4,0xB8E31319, +0x6A51A361,0xB8B94D44,0x6A359DB9,0xB88F926D,0x6A1987B0,0xB865E299,0x69FD614A, +0xB83C3DD1,0x69E12A8C,0xB812A41A,0x69C4E37A,0xB7E9157A,0x69A88C19,0xB7BF91F8, +0x698C246C,0xB796199B,0x696FAC78,0xB76CAC69,0x69532442,0xB7434A67,0x69368BCE, +0xB719F39E,0x6919E320,0xB6F0A812,0x68FD2A3D,0xB6C767CA,0x68E06129,0xB69E32CD, +0x68C387E9,0xB6750921,0x68A69E81,0xB64BEACD,0x6889A4F6,0xB622D7D6,0x686C9B4B, +0xB5F9D043,0x684F8186,0xB5D0D41A,0x683257AB,0xB5A7E362,0x68151DBE,0xB57EFE22, +0x67F7D3C5,0xB556245E,0x67DA79C3,0xB52D561E,0x67BD0FBD,0xB5049368,0x679F95B7, +0xB4DBDC42,0x67820BB7,0xB4B330B3,0x676471C0,0xB48A90C0,0x6746C7D8,0xB461FC70, +0x67290E02,0xB43973CA,0x670B4444,0xB410F6D3,0x66ED6AA1,0xB3E88592,0x66CF8120, +0xB3C0200C,0x66B187C3,0xB397C649,0x66937E91,0xB36F784F,0x6675658C,0xB3473623, +0x66573CBB,0xB31EFFCC,0x66390422,0xB2F6D550,0x661ABBC5,0xB2CEB6B5,0x65FC63A9, +0xB2A6A402,0x65DDFBD3,0xB27E9D3C,0x65BF8447,0xB256A26A,0x65A0FD0B,0xB22EB392, +0x65826622,0xB206D0BA,0x6563BF92,0xB1DEF9E9,0x6545095F,0xB1B72F23,0x6526438F, +0xB18F7071,0x65076E25,0xB167BDD7,0x64E88926,0xB140175B,0x64C99498,0xB1187D05, +0x64AA907F,0xB0F0EEDA,0x648B7CE0,0xB0C96CE0,0x646C59BF,0xB0A1F71D,0x644D2722, +0xB07A8D97,0x642DE50D,0xB0533055,0x640E9386,0xB02BDF5C,0x63EF3290,0xB0049AB3, +0x63CFC231,0xAFDD625F,0x63B0426D,0xAFB63667,0x6390B34A,0xAF8F16D1,0x637114CC, +0xAF6803A2,0x635166F9,0xAF40FCE1,0x6331A9D4,0xAF1A0293,0x6311DD64,0xAEF314C0, +0x62F201AC,0xAECC336C,0x62D216B3,0xAEA55E9E,0x62B21C7B,0xAE7E965B,0x6292130C, +0xAE57DAAB,0x6271FA69,0xAE312B92,0x6251D298,0xAE0A8916,0x62319B9D,0xADE3F33E, +0x6211557E,0xADBD6A10,0x61F1003F,0xAD96ED92,0x61D09BE5,0xAD707DC8,0x61B02876, +0xAD4A1ABA,0x618FA5F7,0xAD23C46E,0x616F146C,0xACFD7AE8,0x614E73DA,0xACD73E30, +0x612DC447,0xACB10E4B,0x610D05B7,0xAC8AEB3E,0x60EC3830,0xAC64D510,0x60CB5BB7, +0xAC3ECBC7,0x60AA7050,0xAC18CF69,0x60897601,0xABF2DFFB,0x60686CCF,0xABCCFD83, +0x604754BF,0xABA72807,0x60262DD6,0xAB815F8D,0x6004F819,0xAB5BA41A,0x5FE3B38D, +0xAB35F5B5,0x5FC26038,0xAB105464,0x5FA0FE1F,0xAAEAC02C,0x5F7F8D46,0xAAC53912, +0x5F5E0DB3,0xAA9FBF1E,0x5F3C7F6B,0xAA7A5253,0x5F1AE274,0xAA54F2BA,0x5EF936D1, +0xAA2FA056,0x5ED77C8A,0xAA0A5B2E,0x5EB5B3A2,0xA9E52347,0x5E93DC1F,0xA9BFF8A8, +0x5E71F606,0xA99ADB56,0x5E50015D,0xA975CB57,0x5E2DFE29,0xA950C8B0,0x5E0BEC6E, +0xA92BD367,0x5DE9CC33,0xA906EB82,0x5DC79D7C,0xA8E21106,0x5DA5604F,0xA8BD43FA, +0x5D8314B1,0xA8988463,0x5D60BAA7,0xA873D246,0x5D3E5237,0xA84F2DAA,0x5D1BDB65, +0xA82A9693,0x5CF95638,0xA8060D08,0x5CD6C2B5,0xA7E1910F,0x5CB420E0,0xA7BD22AC, +0x5C9170BF,0xA798C1E5,0x5C6EB258,0xA7746EC0,0x5C4BE5B0,0xA7502943,0x5C290ACC, +0xA72BF174,0x5C0621B2,0xA707C757,0x5BE32A67,0xA6E3AAF2,0x5BC024F0,0xA6BF9C4B, +0x5B9D1154,0xA69B9B68,0x5B79EF96,0xA677A84E,0x5B56BFBD,0xA653C303,0x5B3381CE, +0xA62FEB8B,0x5B1035CF,0xA60C21EE,0x5AECDBC5,0xA5E8662F,0x5AC973B5,0xA5C4B855, +0x5AA5FDA5,0xA5A11866,0x5A82799A,0xA57D8666,0x5A5EE79A,0xA55A025B,0x5A3B47AB, +0xA5368C4B,0x5A1799D1,0xA513243B,0x59F3DE12,0xA4EFCA31,0x59D01475,0xA4CC7E32, +0x59AC3CFD,0xA4A94043,0x598857B2,0xA486106A,0x59646498,0xA462EEAC,0x594063B5, +0xA43FDB10,0x591C550E,0xA41CD599,0x58F838A9,0xA3F9DE4E,0x58D40E8C,0xA3D6F534, +0x58AFD6BD,0xA3B41A50,0x588B9140,0xA3914DA8,0x58673E1B,0xA36E8F41,0x5842DD54, +0xA34BDF20,0x581E6EF1,0xA3293D4B,0x57F9F2F8,0xA306A9C8,0x57D5696D,0xA2E4249B, +0x57B0D256,0xA2C1ADC9,0x578C2DBA,0xA29F4559,0x57677B9D,0xA27CEB4F,0x5742BC06, +0xA25A9FB1,0x571DEEFA,0xA2386284,0x56F9147E,0xA21633CD,0x56D42C99,0xA1F41392, +0x56AF3750,0xA1D201D7,0x568A34A9,0xA1AFFEA3,0x566524AA,0xA18E09FA,0x56400758, +0xA16C23E1,0x561ADCB9,0xA14A4C5E,0x55F5A4D2,0xA1288376,0x55D05FAA,0xA106C92F, +0x55AB0D46,0xA0E51D8C,0x5585ADAD,0xA0C38095,0x556040E2,0xA0A1F24D,0x553AC6EE, +0xA08072BA,0x55153FD4,0xA05F01E1,0x54EFAB9C,0xA03D9FC8,0x54CA0A4B,0xA01C4C73, +0x54A45BE6,0x9FFB07E7,0x547EA073,0x9FD9D22A,0x5458D7F9,0x9FB8AB41,0x5433027D, +0x9F979331,0x540D2005,0x9F7689FF,0x53E73097,0x9F558FB0,0x53C13439,0x9F34A449, +0x539B2AF0,0x9F13C7D0,0x537514C2,0x9EF2FA49,0x534EF1B5,0x9ED23BB9,0x5328C1D0, +0x9EB18C26,0x53028518,0x9E90EB94,0x52DC3B92,0x9E705A09,0x52B5E546,0x9E4FD78A, +0x528F8238,0x9E2F641B,0x5269126E,0x9E0EFFC1,0x524295F0,0x9DEEAA82,0x521C0CC2, +0x9DCE6463,0x51F576EA,0x9DAE2D68,0x51CED46E,0x9D8E0597,0x51A82555,0x9D6DECF4, +0x518169A5,0x9D4DE385,0x515AA162,0x9D2DE94D,0x5133CC94,0x9D0DFE54,0x510CEB40, +0x9CEE229C,0x50E5FD6D,0x9CCE562C,0x50BF031F,0x9CAE9907,0x5097FC5E,0x9C8EEB34, +0x5070E92F,0x9C6F4CB6,0x5049C999,0x9C4FBD93,0x50229DA1,0x9C303DCF,0x4FFB654D, +0x9C10CD70,0x4FD420A4,0x9BF16C7A,0x4FACCFAB,0x9BD21AF3,0x4F857269,0x9BB2D8DE, +0x4F5E08E3,0x9B93A641,0x4F369320,0x9B748320,0x4F0F1126,0x9B556F81,0x4EE782FB, +0x9B366B68,0x4EBFE8A5,0x9B1776DA,0x4E984229,0x9AF891DB,0x4E708F8F,0x9AD9BC71, +0x4E48D0DD,0x9ABAF6A1,0x4E210617,0x9A9C406E,0x4DF92F46,0x9A7D99DE,0x4DD14C6E, +0x9A5F02F5,0x4DA95D96,0x9A407BB9,0x4D8162C4,0x9A22042D,0x4D595BFE,0x9A039C57, +0x4D31494B,0x99E5443B,0x4D092AB0,0x99C6FBDE,0x4CE10034,0x99A8C345,0x4CB8C9DD, +0x998A9A74,0x4C9087B1,0x996C816F,0x4C6839B7,0x994E783D,0x4C3FDFF4,0x99307EE0, +0x4C177A6E,0x9912955F,0x4BEF092D,0x98F4BBBC,0x4BC68C36,0x98D6F1FE,0x4B9E0390, +0x98B93828,0x4B756F40,0x989B8E40,0x4B4CCF4D,0x987DF449,0x4B2423BE,0x98606A49, +0x4AFB6C98,0x9842F043,0x4AD2A9E2,0x9825863D,0x4AA9DBA2,0x98082C3B,0x4A8101DE, +0x97EAE242,0x4A581C9E,0x97CDA855,0x4A2F2BE6,0x97B07E7A,0x4A062FBD,0x979364B5, +0x49DD282A,0x97765B0A,0x49B41533,0x9759617F,0x498AF6DF,0x973C7817,0x4961CD33, +0x971F9ED7,0x49389836,0x9702D5C3,0x490F57EE,0x96E61CE0,0x48E60C62,0x96C97432, +0x48BCB599,0x96ACDBBE,0x48935397,0x96905388,0x4869E665,0x9673DB94,0x48406E08, +0x965773E7,0x4816EA86,0x963B1C86,0x47ED5BE6,0x961ED574,0x47C3C22F,0x96029EB6, +0x479A1D67,0x95E67850,0x47706D93,0x95CA6247,0x4746B2BC,0x95AE5C9F,0x471CECE7, +0x9592675C,0x46F31C1A,0x95768283,0x46C9405C,0x955AAE17,0x469F59B4,0x953EEA1E, +0x46756828,0x9523369C,0x464B6BBE,0x95079394,0x4621647D,0x94EC010B,0x45F7526B, +0x94D07F05,0x45CD358F,0x94B50D87,0x45A30DF0,0x9499AC95,0x4578DB93,0x947E5C33, +0x454E9E80,0x94631C65,0x452456BD,0x9447ED2F,0x44FA0450,0x942CCE96,0x44CFA740, +0x9411C09E,0x44A53F93,0x93F6C34A,0x447ACD50,0x93DBD6A0,0x4450507E,0x93C0FAA3, +0x4425C923,0x93A62F57,0x43FB3746,0x938B74C1,0x43D09AED,0x9370CAE4,0x43A5F41E, +0x935631C5,0x437B42E1,0x933BA968,0x4350873C,0x932131D1,0x4325C135,0x9306CB04, +0x42FAF0D4,0x92EC7505,0x42D0161E,0x92D22FD9,0x42A5311B,0x92B7FB82,0x427A41D0, +0x929DD806,0x424F4845,0x9283C568,0x42244481,0x9269C3AC,0x41F93689,0x924FD2D7, +0x41CE1E65,0x9235F2EC,0x41A2FC1A,0x921C23EF,0x4177CFB1,0x920265E4,0x414C992F, +0x91E8B8D0,0x4121589B,0x91CF1CB6,0x40F60DFB,0x91B5919A,0x40CAB958,0x919C1781, +0x409F5AB6,0x9182AE6D,0x4073F21D,0x91695663,0x40487F94,0x91500F67,0x401D0321, +0x9136D97D,0x3FF17CCA,0x911DB4A9,0x3FC5EC98,0x9104A0EE,0x3F9A5290,0x90EB9E50, +0x3F6EAEB8,0x90D2ACD4,0x3F430119,0x90B9CC7D,0x3F1749B8,0x90A0FD4E,0x3EEB889C, +0x90883F4D,0x3EBFBDCD,0x906F927C,0x3E93E950,0x9056F6DF,0x3E680B2C,0x903E6C7B, +0x3E3C2369,0x9025F352,0x3E10320D,0x900D8B69,0x3DE4371F,0x8FF534C4,0x3DB832A6, +0x8FDCEF66,0x3D8C24A8,0x8FC4BB53,0x3D600D2C,0x8FAC988F,0x3D33EC39,0x8F94871D, +0x3D07C1D6,0x8F7C8701,0x3CDB8E09,0x8F649840,0x3CAF50DA,0x8F4CBADB,0x3C830A50, +0x8F34EED8,0x3C56BA70,0x8F1D343A,0x3C2A6142,0x8F058B04,0x3BFDFECD,0x8EEDF33B, +0x3BD19318,0x8ED66CE1,0x3BA51E29,0x8EBEF7FB,0x3B78A007,0x8EA7948C,0x3B4C18BA, +0x8E904298,0x3B1F8848,0x8E790222,0x3AF2EEB7,0x8E61D32E,0x3AC64C0F,0x8E4AB5BF, +0x3A99A057,0x8E33A9DA,0x3A6CEB96,0x8E1CAF80,0x3A402DD2,0x8E05C6B7,0x3A136712, +0x8DEEEF82,0x39E6975E,0x8DD829E4,0x39B9BEBC,0x8DC175E0,0x398CDD32,0x8DAAD37B, +0x395FF2C9,0x8D9442B8,0x3932FF87,0x8D7DC399,0x39060373,0x8D675623,0x38D8FE93, +0x8D50FA59,0x38ABF0EF,0x8D3AB03F,0x387EDA8E,0x8D2477D8,0x3851BB77,0x8D0E5127, +0x382493B0,0x8CF83C30,0x37F76341,0x8CE238F6,0x37CA2A30,0x8CCC477D,0x379CE885, +0x8CB667C8,0x376F9E46,0x8CA099DA,0x37424B7B,0x8C8ADDB7,0x3714F02A,0x8C753362, +0x36E78C5B,0x8C5F9ADE,0x36BA2014,0x8C4A142F,0x368CAB5C,0x8C349F58,0x365F2E3B, +0x8C1F3C5D,0x3631A8B8,0x8C09EB40,0x36041AD9,0x8BF4AC05,0x35D684A6,0x8BDF7EB0, +0x35A8E625,0x8BCA6343,0x357B3F5D,0x8BB559C1,0x354D9057,0x8BA0622F,0x351FD918, +0x8B8B7C8F,0x34F219A8,0x8B76A8E4,0x34C4520D,0x8B61E733,0x34968250,0x8B4D377C, +0x3468AA76,0x8B3899C6,0x343ACA87,0x8B240E11,0x340CE28B,0x8B0F9462,0x33DEF287, +0x8AFB2CBB,0x33B0FA84,0x8AE6D720,0x3382FA88,0x8AD29394,0x3354F29B,0x8ABE6219, +0x3326E2C3,0x8AAA42B4,0x32F8CB07,0x8A963567,0x32CAAB6F,0x8A823A36,0x329C8402, +0x8A6E5123,0x326E54C7,0x8A5A7A31,0x32401DC6,0x8A46B564,0x3211DF04,0x8A3302BE, +0x31E39889,0x8A1F6243,0x31B54A5E,0x8A0BD3F5,0x3186F487,0x89F857D8,0x3158970E, +0x89E4EDEF,0x312A31F8,0x89D1963C,0x30FBC54D,0x89BE50C3,0x30CD5115,0x89AB1D87, +0x309ED556,0x8997FC8A,0x30705217,0x8984EDCF,0x3041C761,0x8971F15A,0x30133539, +0x895F072E,0x2FE49BA7,0x894C2F4C,0x2FB5FAB2,0x893969B9,0x2F875262,0x8926B677, +0x2F58A2BE,0x89141589,0x2F29EBCC,0x890186F2,0x2EFB2D95,0x88EF0AB4,0x2ECC681E, +0x88DCA0D3,0x2E9D9B70,0x88CA4951,0x2E6EC792,0x88B80432,0x2E3FEC8B,0x88A5D177, +0x2E110A62,0x8893B125,0x2DE2211E,0x8881A33D,0x2DB330C7,0x886FA7C2,0x2D843964, +0x885DBEB8,0x2D553AFC,0x884BE821,0x2D263596,0x883A23FF,0x2CF72939,0x88287256, +0x2CC815EE,0x8816D327,0x2C98FBBA,0x88054677,0x2C69DAA6,0x87F3CC48,0x2C3AB2B9, +0x87E2649B,0x2C0B83FA,0x87D10F75,0x2BDC4E6F,0x87BFCCD7,0x2BAD1221,0x87AE9CC5, +0x2B7DCF17,0x879D7F41,0x2B4E8558,0x878C744D,0x2B1F34EB,0x877B7BEC,0x2AEFDDD8, +0x876A9621,0x2AC08026,0x8759C2EF,0x2A911BDC,0x87490258,0x2A61B101,0x8738545E, +0x2A323F9E,0x8727B905,0x2A02C7B8,0x8717304E,0x29D34958,0x8706BA3D,0x29A3C485, +0x86F656D3,0x29743946,0x86E60614,0x2944A7A2,0x86D5C802,0x29150FA1,0x86C59C9F, +0x28E5714B,0x86B583EE,0x28B5CCA5,0x86A57DF2,0x288621B9,0x86958AAC,0x2856708D, +0x8685AA20,0x2826B928,0x8675DC4F,0x27F6FB92,0x8666213C,0x27C737D3,0x865678EB, +0x27976DF1,0x8646E35C,0x27679DF4,0x86376092,0x2737C7E3,0x8627F091,0x2707EBC7, +0x86189359,0x26D809A5,0x860948EF,0x26A82186,0x85FA1153,0x26783370,0x85EAEC88, +0x26483F6C,0x85DBDA91,0x26184581,0x85CCDB70,0x25E845B6,0x85BDEF28,0x25B84012, +0x85AF15B9,0x2588349D,0x85A04F28,0x2558235F,0x85919B76,0x25280C5E,0x8582FAA5, +0x24F7EFA2,0x85746CB8,0x24C7CD33,0x8565F1B0,0x2497A517,0x85578991,0x24677758, +0x8549345C,0x243743FA,0x853AF214,0x24070B08,0x852CC2BB,0x23D6CC87,0x851EA652, +0x23A6887F,0x85109CDD,0x23763EF7,0x8502A65C,0x2345EFF8,0x84F4C2D4,0x23159B88, +0x84E6F244,0x22E541AF,0x84D934B1,0x22B4E274,0x84CB8A1B,0x22847DE0,0x84BDF286, +0x225413F8,0x84B06DF2,0x2223A4C5,0x84A2FC62,0x21F3304F,0x84959DD9,0x21C2B69C, +0x84885258,0x219237B5,0x847B19E1,0x2161B3A0,0x846DF477,0x21312A65,0x8460E21A, +0x21009C0C,0x8453E2CF,0x20D0089C,0x8446F695,0x209F701C,0x843A1D70,0x206ED295, +0x842D5762,0x203E300D,0x8420A46C,0x200D888D,0x84140490,0x1FDCDC1B,0x840777D0, +0x1FAC2ABF,0x83FAFE2E,0x1F7B7481,0x83EE97AD,0x1F4AB968,0x83E2444D,0x1F19F97B, +0x83D60412,0x1EE934C3,0x83C9D6FC,0x1EB86B46,0x83BDBD0E,0x1E879D0D,0x83B1B649, +0x1E56CA1E,0x83A5C2B0,0x1E25F282,0x8399E244,0x1DF5163F,0x838E1507,0x1DC4355E, +0x83825AFB,0x1D934FE5,0x8376B422,0x1D6265DD,0x836B207D,0x1D31774D,0x835FA00F, +0x1D00843D,0x835432D8,0x1CCF8CB3,0x8348D8DC,0x1C9E90B8,0x833D921B,0x1C6D9053, +0x83325E97,0x1C3C8B8C,0x83273E52,0x1C0B826A,0x831C314E,0x1BDA74F6,0x8311378D, +0x1BA96335,0x83065110,0x1B784D30,0x82FB7DD8,0x1B4732EF,0x82F0BDE8,0x1B161479, +0x82E61141,0x1AE4F1D6,0x82DB77E5,0x1AB3CB0D,0x82D0F1D5,0x1A82A026,0x82C67F14, +0x1A517128,0x82BC1FA2,0x1A203E1B,0x82B1D381,0x19EF0707,0x82A79AB3,0x19BDCBF3, +0x829D753A,0x198C8CE7,0x82936317,0x195B49EA,0x8289644B,0x192A0304,0x827F78D8, +0x18F8B83C,0x8275A0C0,0x18C7699B,0x826BDC04,0x18961728,0x82622AA6,0x1864C0EA, +0x82588CA7,0x183366E9,0x824F0208,0x1802092C,0x82458ACC,0x17D0A7BC,0x823C26F3, +0x179F429F,0x8232D67F,0x176DD9DE,0x82299971,0x173C6D80,0x82206FCC,0x170AFD8D, +0x82175990,0x16D98A0C,0x820E56BE,0x16A81305,0x82056758,0x1676987F,0x81FC8B60, +0x16451A83,0x81F3C2D7,0x16139918,0x81EB0DBE,0x15E21445,0x81E26C16,0x15B08C12, +0x81D9DDE1,0x157F0086,0x81D16321,0x154D71AA,0x81C8FBD6,0x151BDF86,0x81C0A801, +0x14EA4A1F,0x81B867A5,0x14B8B17F,0x81B03AC2,0x148715AE,0x81A82159,0x145576B1, +0x81A01B6D,0x1423D492,0x819828FD,0x13F22F58,0x81904A0C,0x13C0870A,0x81887E9A, +0x138EDBB1,0x8180C6A9,0x135D2D53,0x8179223A,0x132B7BF9,0x8171914E,0x12F9C7AA, +0x816A13E6,0x12C8106F,0x8162AA04,0x1296564D,0x815B53A8,0x1264994E,0x815410D4, +0x1232D979,0x814CE188,0x120116D5,0x8145C5C7,0x11CF516A,0x813EBD90,0x119D8941, +0x8137C8E6,0x116BBE60,0x8130E7C9,0x1139F0CF,0x812A1A3A,0x11082096,0x8123603A, +0x10D64DBD,0x811CB9CA,0x10A4784B,0x811626EC,0x1072A048,0x810FA7A0,0x1040C5BB, +0x81093BE8,0x100EE8AD,0x8102E3C4,0x0FDD0926,0x80FC9F35,0x0FAB272B,0x80F66E3C, +0x0F7942C7,0x80F050DB,0x0F475BFF,0x80EA4712,0x0F1572DC,0x80E450E2,0x0EE38766, +0x80DE6E4C,0x0EB199A4,0x80D89F51,0x0E7FA99E,0x80D2E3F2,0x0E4DB75B,0x80CD3C2F, +0x0E1BC2E4,0x80C7A80A,0x0DE9CC40,0x80C22784,0x0DB7D376,0x80BCBA9D,0x0D85D88F, +0x80B76156,0x0D53DB92,0x80B21BAF,0x0D21DC87,0x80ACE9AB,0x0CEFDB76,0x80A7CB49, +0x0CBDD865,0x80A2C08B,0x0C8BD35E,0x809DC971,0x0C59CC68,0x8098E5FB,0x0C27C389, +0x8094162C,0x0BF5B8CB,0x808F5A02,0x0BC3AC35,0x808AB180,0x0B919DCF,0x80861CA6, +0x0B5F8D9F,0x80819B74,0x0B2D7BAF,0x807D2DEC,0x0AFB6805,0x8078D40D,0x0AC952AA, +0x80748DD9,0x0A973BA5,0x80705B50,0x0A6522FE,0x806C3C74,0x0A3308BD,0x80683143, +0x0A00ECE8,0x806439C0,0x09CECF89,0x806055EB,0x099CB0A7,0x805C85C4,0x096A9049, +0x8058C94C,0x09386E78,0x80552084,0x09064B3A,0x80518B6B,0x08D42699,0x804E0A04, +0x08A2009A,0x804A9C4D,0x086FD947,0x80474248,0x083DB0A7,0x8043FBF6,0x080B86C2, +0x8040C956,0x07D95B9E,0x803DAA6A,0x07A72F45,0x803A9F31,0x077501BE,0x8037A7AC, +0x0742D311,0x8034C3DD,0x0710A345,0x8031F3C2,0x06DE7262,0x802F375D,0x06AC406F, +0x802C8EAD,0x067A0D76,0x8029F9B4,0x0647D97C,0x80277872,0x0615A48B,0x80250AE7, +0x05E36EA9,0x8022B114,0x05B137DF,0x80206AF8,0x057F0035,0x801E3895,0x054CC7B1, +0x801C19EA,0x051A8E5C,0x801A0EF8,0x04E8543E,0x801817BF,0x04B6195D,0x80163440, +0x0483DDC3,0x8014647B,0x0451A177,0x8012A86F,0x041F6480,0x8011001F,0x03ED26E6, +0x800F6B88,0x03BAE8B2,0x800DEAAD,0x0388A9EA,0x800C7D8C,0x03566A96,0x800B2427, +0x03242ABF,0x8009DE7E,0x02F1EA6C,0x8008AC90,0x02BFA9A4,0x80078E5E,0x028D6870, +0x800683E8,0x025B26D7,0x80058D2F,0x0228E4E2,0x8004AA32,0x01F6A297,0x8003DAF1, +0x01C45FFE,0x80031F6D,0x01921D20,0x800277A6,0x015FDA03,0x8001E39B,0x012D96B1, +0x8001634E,0x00FB5330,0x8000F6BD,0x00C90F88,0x80009DEA,0x0096CBC1,0x800058D4, +0x006487E3,0x8000277A,0x003243F5,0x800009DF,0x7FFFFFFF,0x00000000,0x7FFF6216, +0xFF36F078,0x7FFD885A,0xFE6DE2E0,0x7FFA72D1,0xFDA4D929,0x7FF62182,0xFCDBD541, +0x7FF09478,0xFC12D91A,0x7FE9CBC0,0xFB49E6A3,0x7FE1C76B,0xFA80FFCB,0x7FD8878E, +0xF9B82684,0x7FCE0C3E,0xF8EF5CBB,0x7FC25596,0xF826A462,0x7FB563B3,0xF75DFF66, +0x7FA736B4,0xF6956FB7,0x7F97CEBD,0xF5CCF743,0x7F872BF3,0xF50497FB,0x7F754E80, +0xF43C53CB,0x7F62368F,0xF3742CA2,0x7F4DE451,0xF2AC246E,0x7F3857F6,0xF1E43D1C, +0x7F2191B4,0xF11C789A,0x7F0991C4,0xF054D8D5,0x7EF05860,0xEF8D5FB8,0x7ED5E5C6, +0xEEC60F31,0x7EBA3A39,0xEDFEE92B,0x7E9D55FC,0xED37EF91,0x7E7F3957,0xEC71244F, +0x7E5FE493,0xEBAA894F,0x7E3F57FF,0xEAE4207A,0x7E1D93EA,0xEA1DEBBB,0x7DFA98A8, +0xE957ECFB,0x7DD6668F,0xE8922622,0x7DB0FDF8,0xE7CC9917,0x7D8A5F40,0xE70747C4, +0x7D628AC6,0xE642340D,0x7D3980EC,0xE57D5FDA,0x7D0F4218,0xE4B8CD11,0x7CE3CEB2, +0xE3F47D96,0x7CB72724,0xE330734D,0x7C894BDE,0xE26CB01B,0x7C5A3D50,0xE1A935E2, +0x7C29FBEE,0xE0E60685,0x7BF88830,0xE02323E5,0x7BC5E290,0xDF608FE4,0x7B920B89, +0xDE9E4C60,0x7B5D039E,0xDDDC5B3B,0x7B26CB4F,0xDD1ABE51,0x7AEF6323,0xDC597781, +0x7AB6CBA4,0xDB9888A8,0x7A7D055B,0xDAD7F3A2,0x7A4210D8,0xDA17BA4A,0x7A05EEAD, +0xD957DE7A,0x79C89F6E,0xD898620C,0x798A23B1,0xD7D946D8,0x794A7C12,0xD71A8EB5, +0x7909A92D,0xD65C3B7B,0x78C7ABA2,0xD59E4EFF,0x78848414,0xD4E0CB15,0x78403329, +0xD423B191,0x77FAB989,0xD3670446,0x77B417DF,0xD2AAC504,0x776C4EDB,0xD1EEF59E, +0x77235F2D,0xD13397E2,0x76D94989,0xD078AD9E,0x768E0EA6,0xCFBE389F,0x7641AF3D, +0xCF043AB3,0x75F42C0B,0xCE4AB5A2,0x75A585CF,0xCD91AB39,0x7555BD4C,0xCCD91D3D, +0x7504D345,0xCC210D79,0x74B2C884,0xCB697DB0,0x745F9DD1,0xCAB26FA9,0x740B53FB, +0xC9FBE527,0x73B5EBD1,0xC945DFEC,0x735F6626,0xC89061BA,0x7307C3D0,0xC7DB6C50, +0x72AF05A7,0xC727016D,0x72552C85,0xC67322CE,0x71FA3949,0xC5BFD22E,0x719E2CD2, +0xC50D1149,0x71410805,0xC45AE1D7,0x70E2CBC6,0xC3A94590,0x708378FF,0xC2F83E2A, +0x7023109A,0xC247CD5A,0x6FC19385,0xC197F4D4,0x6F5F02B2,0xC0E8B648,0x6EFB5F12, +0xC03A1368,0x6E96A99D,0xBF8C0DE3,0x6E30E34A,0xBEDEA765,0x6DCA0D14,0xBE31E19B, +0x6D6227FA,0xBD85BE30,0x6CF934FC,0xBCDA3ECB,0x6C8F351C,0xBC2F6513,0x6C242960, +0xBB8532B0,0x6BB812D1,0xBADBA943,0x6B4AF279,0xBA32CA71,0x6ADCC964,0xB98A97D8, +0x6A6D98A4,0xB8E31319,0x69FD614A,0xB83C3DD1,0x698C246C,0xB796199B,0x6919E320, +0xB6F0A812,0x68A69E81,0xB64BEACD,0x683257AB,0xB5A7E362,0x67BD0FBD,0xB5049368, +0x6746C7D8,0xB461FC70,0x66CF8120,0xB3C0200C,0x66573CBB,0xB31EFFCC,0x65DDFBD3, +0xB27E9D3C,0x6563BF92,0xB1DEF9E9,0x64E88926,0xB140175B,0x646C59BF,0xB0A1F71D, +0x63EF3290,0xB0049AB3,0x637114CC,0xAF6803A2,0x62F201AC,0xAECC336C,0x6271FA69, +0xAE312B92,0x61F1003F,0xAD96ED92,0x616F146C,0xACFD7AE8,0x60EC3830,0xAC64D510, +0x60686CCF,0xABCCFD83,0x5FE3B38D,0xAB35F5B5,0x5F5E0DB3,0xAA9FBF1E,0x5ED77C8A, +0xAA0A5B2E,0x5E50015D,0xA975CB57,0x5DC79D7C,0xA8E21106,0x5D3E5237,0xA84F2DAA, +0x5CB420E0,0xA7BD22AC,0x5C290ACC,0xA72BF174,0x5B9D1154,0xA69B9B68,0x5B1035CF, +0xA60C21EE,0x5A82799A,0xA57D8666,0x59F3DE12,0xA4EFCA31,0x59646498,0xA462EEAC, +0x58D40E8C,0xA3D6F534,0x5842DD54,0xA34BDF20,0x57B0D256,0xA2C1ADC9,0x571DEEFA, +0xA2386284,0x568A34A9,0xA1AFFEA3,0x55F5A4D2,0xA1288376,0x556040E2,0xA0A1F24D, +0x54CA0A4B,0xA01C4C73,0x5433027D,0x9F979331,0x539B2AF0,0x9F13C7D0,0x53028518, +0x9E90EB94,0x5269126E,0x9E0EFFC1,0x51CED46E,0x9D8E0597,0x5133CC94,0x9D0DFE54, +0x5097FC5E,0x9C8EEB34,0x4FFB654D,0x9C10CD70,0x4F5E08E3,0x9B93A641,0x4EBFE8A5, +0x9B1776DA,0x4E210617,0x9A9C406E,0x4D8162C4,0x9A22042D,0x4CE10034,0x99A8C345, +0x4C3FDFF4,0x99307EE0,0x4B9E0390,0x98B93828,0x4AFB6C98,0x9842F043,0x4A581C9E, +0x97CDA855,0x49B41533,0x9759617F,0x490F57EE,0x96E61CE0,0x4869E665,0x9673DB94, +0x47C3C22F,0x96029EB6,0x471CECE7,0x9592675C,0x46756828,0x9523369C,0x45CD358F, +0x94B50D87,0x452456BD,0x9447ED2F,0x447ACD50,0x93DBD6A0,0x43D09AED,0x9370CAE4, +0x4325C135,0x9306CB04,0x427A41D0,0x929DD806,0x41CE1E65,0x9235F2EC,0x4121589B, +0x91CF1CB6,0x4073F21D,0x91695663,0x3FC5EC98,0x9104A0EE,0x3F1749B8,0x90A0FD4E, +0x3E680B2C,0x903E6C7B,0x3DB832A6,0x8FDCEF66,0x3D07C1D6,0x8F7C8701,0x3C56BA70, +0x8F1D343A,0x3BA51E29,0x8EBEF7FB,0x3AF2EEB7,0x8E61D32E,0x3A402DD2,0x8E05C6B7, +0x398CDD32,0x8DAAD37B,0x38D8FE93,0x8D50FA59,0x382493B0,0x8CF83C30,0x376F9E46, +0x8CA099DA,0x36BA2014,0x8C4A142F,0x36041AD9,0x8BF4AC05,0x354D9057,0x8BA0622F, +0x34968250,0x8B4D377C,0x33DEF287,0x8AFB2CBB,0x3326E2C3,0x8AAA42B4,0x326E54C7, +0x8A5A7A31,0x31B54A5E,0x8A0BD3F5,0x30FBC54D,0x89BE50C3,0x3041C761,0x8971F15A, +0x2F875262,0x8926B677,0x2ECC681E,0x88DCA0D3,0x2E110A62,0x8893B125,0x2D553AFC, +0x884BE821,0x2C98FBBA,0x88054677,0x2BDC4E6F,0x87BFCCD7,0x2B1F34EB,0x877B7BEC, +0x2A61B101,0x8738545E,0x29A3C485,0x86F656D3,0x28E5714B,0x86B583EE,0x2826B928, +0x8675DC4F,0x27679DF4,0x86376092,0x26A82186,0x85FA1153,0x25E845B6,0x85BDEF28, +0x25280C5E,0x8582FAA5,0x24677758,0x8549345C,0x23A6887F,0x85109CDD,0x22E541AF, +0x84D934B1,0x2223A4C5,0x84A2FC62,0x2161B3A0,0x846DF477,0x209F701C,0x843A1D70, +0x1FDCDC1B,0x840777D0,0x1F19F97B,0x83D60412,0x1E56CA1E,0x83A5C2B0,0x1D934FE5, +0x8376B422,0x1CCF8CB3,0x8348D8DC,0x1C0B826A,0x831C314E,0x1B4732EF,0x82F0BDE8, +0x1A82A026,0x82C67F14,0x19BDCBF3,0x829D753A,0x18F8B83C,0x8275A0C0,0x183366E9, +0x824F0208,0x176DD9DE,0x82299971,0x16A81305,0x82056758,0x15E21445,0x81E26C16, +0x151BDF86,0x81C0A801,0x145576B1,0x81A01B6D,0x138EDBB1,0x8180C6A9,0x12C8106F, +0x8162AA04,0x120116D5,0x8145C5C7,0x1139F0CF,0x812A1A3A,0x1072A048,0x810FA7A0, +0x0FAB272B,0x80F66E3C,0x0EE38766,0x80DE6E4C,0x0E1BC2E4,0x80C7A80A,0x0D53DB92, +0x80B21BAF,0x0C8BD35E,0x809DC971,0x0BC3AC35,0x808AB180,0x0AFB6805,0x8078D40D, +0x0A3308BD,0x80683143,0x096A9049,0x8058C94C,0x08A2009A,0x804A9C4D,0x07D95B9E, +0x803DAA6A,0x0710A345,0x8031F3C2,0x0647D97C,0x80277872,0x057F0035,0x801E3895, +0x04B6195D,0x80163440,0x03ED26E6,0x800F6B88,0x03242ABF,0x8009DE7E,0x025B26D7, +0x80058D2F,0x01921D20,0x800277A6,0x00C90F88,0x80009DEA,0x7FFFFFFF,0x00000000, +0x7FF62182,0xFCDBD541,0x7FD8878E,0xF9B82684,0x7FA736B4,0xF6956FB7,0x7F62368F, +0xF3742CA2,0x7F0991C4,0xF054D8D5,0x7E9D55FC,0xED37EF91,0x7E1D93EA,0xEA1DEBBB, +0x7D8A5F40,0xE70747C4,0x7CE3CEB2,0xE3F47D96,0x7C29FBEE,0xE0E60685,0x7B5D039E, +0xDDDC5B3B,0x7A7D055B,0xDAD7F3A2,0x798A23B1,0xD7D946D8,0x78848414,0xD4E0CB15, +0x776C4EDB,0xD1EEF59E,0x7641AF3D,0xCF043AB3,0x7504D345,0xCC210D79,0x73B5EBD1, +0xC945DFEC,0x72552C85,0xC67322CE,0x70E2CBC6,0xC3A94590,0x6F5F02B2,0xC0E8B648, +0x6DCA0D14,0xBE31E19B,0x6C242960,0xBB8532B0,0x6A6D98A4,0xB8E31319,0x68A69E81, +0xB64BEACD,0x66CF8120,0xB3C0200C,0x64E88926,0xB140175B,0x62F201AC,0xAECC336C, +0x60EC3830,0xAC64D510,0x5ED77C8A,0xAA0A5B2E,0x5CB420E0,0xA7BD22AC,0x5A82799A, +0xA57D8666,0x5842DD54,0xA34BDF20,0x55F5A4D2,0xA1288376,0x539B2AF0,0x9F13C7D0, +0x5133CC94,0x9D0DFE54,0x4EBFE8A5,0x9B1776DA,0x4C3FDFF4,0x99307EE0,0x49B41533, +0x9759617F,0x471CECE7,0x9592675C,0x447ACD50,0x93DBD6A0,0x41CE1E65,0x9235F2EC, +0x3F1749B8,0x90A0FD4E,0x3C56BA70,0x8F1D343A,0x398CDD32,0x8DAAD37B,0x36BA2014, +0x8C4A142F,0x33DEF287,0x8AFB2CBB,0x30FBC54D,0x89BE50C3,0x2E110A62,0x8893B125, +0x2B1F34EB,0x877B7BEC,0x2826B928,0x8675DC4F,0x25280C5E,0x8582FAA5,0x2223A4C5, +0x84A2FC62,0x1F19F97B,0x83D60412,0x1C0B826A,0x831C314E,0x18F8B83C,0x8275A0C0, +0x15E21445,0x81E26C16,0x12C8106F,0x8162AA04,0x0FAB272B,0x80F66E3C,0x0C8BD35E, +0x809DC971,0x096A9049,0x8058C94C,0x0647D97C,0x80277872,0x03242ABF,0x8009DE7E, +0x7FFFFFFF,0x00000000,0x7F62368F,0xF3742CA2,0x7D8A5F40,0xE70747C4,0x7A7D055B, +0xDAD7F3A2,0x7641AF3D,0xCF043AB3,0x70E2CBC6,0xC3A94590,0x6A6D98A4,0xB8E31319, +0x62F201AC,0xAECC336C,0x5A82799A,0xA57D8666,0x5133CC94,0x9D0DFE54,0x471CECE7, +0x9592675C,0x3C56BA70,0x8F1D343A,0x30FBC54D,0x89BE50C3,0x25280C5E,0x8582FAA5, +0x18F8B83C,0x8275A0C0,0x0C8BD35E,0x809DC971,0x7FFFFFFF,0x00000000,0x7641AF3D, +0xCF043AB3,0x5A82799A,0xA57D8666,0x30FBC54D,0x89BE50C3,}; + +q31_t rearranged_twiddle_stride2_4096_q31[2728]={ +0x7FFFFFFF,0x00000000,0x7FFFD886,0xFF9B781D,0x7FFF6216,0xFF36F078,0x7FFE9CB2, +0xFED2694F,0x7FFD885A,0xFE6DE2E0,0x7FFC250F,0xFE095D69,0x7FFA72D1,0xFDA4D929, +0x7FF871A2,0xFD40565C,0x7FF62182,0xFCDBD541,0x7FF38274,0xFC775616,0x7FF09478, +0xFC12D91A,0x7FED5791,0xFBAE5E89,0x7FE9CBC0,0xFB49E6A3,0x7FE5F108,0xFAE571A4, +0x7FE1C76B,0xFA80FFCB,0x7FDD4EEC,0xFA1C9157,0x7FD8878E,0xF9B82684,0x7FD37153, +0xF953BF91,0x7FCE0C3E,0xF8EF5CBB,0x7FC85854,0xF88AFE42,0x7FC25596,0xF826A462, +0x7FBC040A,0xF7C24F59,0x7FB563B3,0xF75DFF66,0x7FAE7495,0xF6F9B4C6,0x7FA736B4, +0xF6956FB7,0x7F9FAA15,0xF6313077,0x7F97CEBD,0xF5CCF743,0x7F8FA4B0,0xF568C45B, +0x7F872BF3,0xF50497FB,0x7F7E648C,0xF4A07261,0x7F754E80,0xF43C53CB,0x7F6BE9D4, +0xF3D83C77,0x7F62368F,0xF3742CA2,0x7F5834B7,0xF310248A,0x7F4DE451,0xF2AC246E, +0x7F434563,0xF2482C8A,0x7F3857F6,0xF1E43D1C,0x7F2D1C0E,0xF1805662,0x7F2191B4, +0xF11C789A,0x7F15B8EE,0xF0B8A401,0x7F0991C4,0xF054D8D5,0x7EFD1C3C,0xEFF11753, +0x7EF05860,0xEF8D5FB8,0x7EE34636,0xEF29B243,0x7ED5E5C6,0xEEC60F31,0x7EC8371A, +0xEE6276BF,0x7EBA3A39,0xEDFEE92B,0x7EABEF2C,0xED9B66B2,0x7E9D55FC,0xED37EF91, +0x7E8E6EB2,0xECD48407,0x7E7F3957,0xEC71244F,0x7E6FB5F4,0xEC0DD0A8,0x7E5FE493, +0xEBAA894F,0x7E4FC53E,0xEB474E81,0x7E3F57FF,0xEAE4207A,0x7E2E9CDF,0xEA80FF7A, +0x7E1D93EA,0xEA1DEBBB,0x7E0C3D29,0xE9BAE57D,0x7DFA98A8,0xE957ECFB,0x7DE8A670, +0xE8F50273,0x7DD6668F,0xE8922622,0x7DC3D90D,0xE82F5844,0x7DB0FDF8,0xE7CC9917, +0x7D9DD55A,0xE769E8D8,0x7D8A5F40,0xE70747C4,0x7D769BB5,0xE6A4B616,0x7D628AC6, +0xE642340D,0x7D4E2C7F,0xE5DFC1E5,0x7D3980EC,0xE57D5FDA,0x7D24881B,0xE51B0E2A, +0x7D0F4218,0xE4B8CD11,0x7CF9AEF0,0xE4569CCB,0x7CE3CEB2,0xE3F47D96,0x7CCDA169, +0xE3926FAD,0x7CB72724,0xE330734D,0x7CA05FF1,0xE2CE88B3,0x7C894BDE,0xE26CB01B, +0x7C71EAF9,0xE20AE9C1,0x7C5A3D50,0xE1A935E2,0x7C4242F2,0xE14794BA,0x7C29FBEE, +0xE0E60685,0x7C116853,0xE0848B7F,0x7BF88830,0xE02323E5,0x7BDF5B94,0xDFC1CFF3, +0x7BC5E290,0xDF608FE4,0x7BAC1D31,0xDEFF63F4,0x7B920B89,0xDE9E4C60,0x7B77ADA8, +0xDE3D4964,0x7B5D039E,0xDDDC5B3B,0x7B420D7A,0xDD7B8220,0x7B26CB4F,0xDD1ABE51, +0x7B0B3D2C,0xDCBA1008,0x7AEF6323,0xDC597781,0x7AD33D45,0xDBF8F4F8,0x7AB6CBA4, +0xDB9888A8,0x7A9A0E50,0xDB3832CD,0x7A7D055B,0xDAD7F3A2,0x7A5FB0D8,0xDA77CB63, +0x7A4210D8,0xDA17BA4A,0x7A24256F,0xD9B7C094,0x7A05EEAD,0xD957DE7A,0x79E76CA7, +0xD8F81439,0x79C89F6E,0xD898620C,0x79A98715,0xD838C82D,0x798A23B1,0xD7D946D8, +0x796A7554,0xD779DE47,0x794A7C12,0xD71A8EB5,0x792A37FE,0xD6BB585E,0x7909A92D, +0xD65C3B7B,0x78E8CFB2,0xD5FD3848,0x78C7ABA2,0xD59E4EFF,0x78A63D11,0xD53F7FDA, +0x78848414,0xD4E0CB15,0x786280BF,0xD48230E9,0x78403329,0xD423B191,0x781D9B65, +0xD3C54D47,0x77FAB989,0xD3670446,0x77D78DAA,0xD308D6C7,0x77B417DF,0xD2AAC504, +0x7790583E,0xD24CCF39,0x776C4EDB,0xD1EEF59E,0x7747FBCE,0xD191386E,0x77235F2D, +0xD13397E2,0x76FE790E,0xD0D61434,0x76D94989,0xD078AD9E,0x76B3D0B4,0xD01B6459, +0x768E0EA6,0xCFBE389F,0x76680376,0xCF612AAA,0x7641AF3D,0xCF043AB3,0x761B1211, +0xCEA768F2,0x75F42C0B,0xCE4AB5A2,0x75CCFD42,0xCDEE20FC,0x75A585CF,0xCD91AB39, +0x757DC5CA,0xCD355491,0x7555BD4C,0xCCD91D3D,0x752D6C6C,0xCC7D0578,0x7504D345, +0xCC210D79,0x74DBF1EF,0xCBC53579,0x74B2C884,0xCB697DB0,0x7489571C,0xCB0DE658, +0x745F9DD1,0xCAB26FA9,0x74359CBD,0xCA5719DB,0x740B53FB,0xC9FBE527,0x73E0C3A3, +0xC9A0D1C5,0x73B5EBD1,0xC945DFEC,0x738ACC9E,0xC8EB0FD6,0x735F6626,0xC89061BA, +0x7333B883,0xC835D5D0,0x7307C3D0,0xC7DB6C50,0x72DB8828,0xC7812572,0x72AF05A7, +0xC727016D,0x72823C67,0xC6CD0079,0x72552C85,0xC67322CE,0x7227D61C,0xC61968A2, +0x71FA3949,0xC5BFD22E,0x71CC5626,0xC5665FA9,0x719E2CD2,0xC50D1149,0x716FBD68, +0xC4B3E746,0x71410805,0xC45AE1D7,0x71120CC5,0xC4020133,0x70E2CBC6,0xC3A94590, +0x70B34525,0xC350AF26,0x708378FF,0xC2F83E2A,0x70536771,0xC29FF2D4,0x7023109A, +0xC247CD5A,0x6FF27497,0xC1EFCDF3,0x6FC19385,0xC197F4D4,0x6F906D84,0xC1404233, +0x6F5F02B2,0xC0E8B648,0x6F2D532C,0xC0915148,0x6EFB5F12,0xC03A1368,0x6EC92683, +0xBFE2FCDF,0x6E96A99D,0xBF8C0DE3,0x6E63E87F,0xBF3546A8,0x6E30E34A,0xBEDEA765, +0x6DFD9A1C,0xBE88304F,0x6DCA0D14,0xBE31E19B,0x6D963C54,0xBDDBBB7F,0x6D6227FA, +0xBD85BE30,0x6D2DD027,0xBD2FE9E2,0x6CF934FC,0xBCDA3ECB,0x6CC45698,0xBC84BD1F, +0x6C8F351C,0xBC2F6513,0x6C59D0A9,0xBBDA36DD,0x6C242960,0xBB8532B0,0x6BEE3F62, +0xBB3058C0,0x6BB812D1,0xBADBA943,0x6B81A3CD,0xBA87246D,0x6B4AF279,0xBA32CA71, +0x6B13FEF5,0xB9DE9B83,0x6ADCC964,0xB98A97D8,0x6AA551E9,0xB936BFA4,0x6A6D98A4, +0xB8E31319,0x6A359DB9,0xB88F926D,0x69FD614A,0xB83C3DD1,0x69C4E37A,0xB7E9157A, +0x698C246C,0xB796199B,0x69532442,0xB7434A67,0x6919E320,0xB6F0A812,0x68E06129, +0xB69E32CD,0x68A69E81,0xB64BEACD,0x686C9B4B,0xB5F9D043,0x683257AB,0xB5A7E362, +0x67F7D3C5,0xB556245E,0x67BD0FBD,0xB5049368,0x67820BB7,0xB4B330B3,0x6746C7D8, +0xB461FC70,0x670B4444,0xB410F6D3,0x66CF8120,0xB3C0200C,0x66937E91,0xB36F784F, +0x66573CBB,0xB31EFFCC,0x661ABBC5,0xB2CEB6B5,0x65DDFBD3,0xB27E9D3C,0x65A0FD0B, +0xB22EB392,0x6563BF92,0xB1DEF9E9,0x6526438F,0xB18F7071,0x64E88926,0xB140175B, +0x64AA907F,0xB0F0EEDA,0x646C59BF,0xB0A1F71D,0x642DE50D,0xB0533055,0x63EF3290, +0xB0049AB3,0x63B0426D,0xAFB63667,0x637114CC,0xAF6803A2,0x6331A9D4,0xAF1A0293, +0x62F201AC,0xAECC336C,0x62B21C7B,0xAE7E965B,0x6271FA69,0xAE312B92,0x62319B9D, +0xADE3F33E,0x61F1003F,0xAD96ED92,0x61B02876,0xAD4A1ABA,0x616F146C,0xACFD7AE8, +0x612DC447,0xACB10E4B,0x60EC3830,0xAC64D510,0x60AA7050,0xAC18CF69,0x60686CCF, +0xABCCFD83,0x60262DD6,0xAB815F8D,0x5FE3B38D,0xAB35F5B5,0x5FA0FE1F,0xAAEAC02C, +0x5F5E0DB3,0xAA9FBF1E,0x5F1AE274,0xAA54F2BA,0x5ED77C8A,0xAA0A5B2E,0x5E93DC1F, +0xA9BFF8A8,0x5E50015D,0xA975CB57,0x5E0BEC6E,0xA92BD367,0x5DC79D7C,0xA8E21106, +0x5D8314B1,0xA8988463,0x5D3E5237,0xA84F2DAA,0x5CF95638,0xA8060D08,0x5CB420E0, +0xA7BD22AC,0x5C6EB258,0xA7746EC0,0x5C290ACC,0xA72BF174,0x5BE32A67,0xA6E3AAF2, +0x5B9D1154,0xA69B9B68,0x5B56BFBD,0xA653C303,0x5B1035CF,0xA60C21EE,0x5AC973B5, +0xA5C4B855,0x5A82799A,0xA57D8666,0x5A3B47AB,0xA5368C4B,0x59F3DE12,0xA4EFCA31, +0x59AC3CFD,0xA4A94043,0x59646498,0xA462EEAC,0x591C550E,0xA41CD599,0x58D40E8C, +0xA3D6F534,0x588B9140,0xA3914DA8,0x5842DD54,0xA34BDF20,0x57F9F2F8,0xA306A9C8, +0x57B0D256,0xA2C1ADC9,0x57677B9D,0xA27CEB4F,0x571DEEFA,0xA2386284,0x56D42C99, +0xA1F41392,0x568A34A9,0xA1AFFEA3,0x56400758,0xA16C23E1,0x55F5A4D2,0xA1288376, +0x55AB0D46,0xA0E51D8C,0x556040E2,0xA0A1F24D,0x55153FD4,0xA05F01E1,0x54CA0A4B, +0xA01C4C73,0x547EA073,0x9FD9D22A,0x5433027D,0x9F979331,0x53E73097,0x9F558FB0, +0x539B2AF0,0x9F13C7D0,0x534EF1B5,0x9ED23BB9,0x53028518,0x9E90EB94,0x52B5E546, +0x9E4FD78A,0x5269126E,0x9E0EFFC1,0x521C0CC2,0x9DCE6463,0x51CED46E,0x9D8E0597, +0x518169A5,0x9D4DE385,0x5133CC94,0x9D0DFE54,0x50E5FD6D,0x9CCE562C,0x5097FC5E, +0x9C8EEB34,0x5049C999,0x9C4FBD93,0x4FFB654D,0x9C10CD70,0x4FACCFAB,0x9BD21AF3, +0x4F5E08E3,0x9B93A641,0x4F0F1126,0x9B556F81,0x4EBFE8A5,0x9B1776DA,0x4E708F8F, +0x9AD9BC71,0x4E210617,0x9A9C406E,0x4DD14C6E,0x9A5F02F5,0x4D8162C4,0x9A22042D, +0x4D31494B,0x99E5443B,0x4CE10034,0x99A8C345,0x4C9087B1,0x996C816F,0x4C3FDFF4, +0x99307EE0,0x4BEF092D,0x98F4BBBC,0x4B9E0390,0x98B93828,0x4B4CCF4D,0x987DF449, +0x4AFB6C98,0x9842F043,0x4AA9DBA2,0x98082C3B,0x4A581C9E,0x97CDA855,0x4A062FBD, +0x979364B5,0x49B41533,0x9759617F,0x4961CD33,0x971F9ED7,0x490F57EE,0x96E61CE0, +0x48BCB599,0x96ACDBBE,0x4869E665,0x9673DB94,0x4816EA86,0x963B1C86,0x47C3C22F, +0x96029EB6,0x47706D93,0x95CA6247,0x471CECE7,0x9592675C,0x46C9405C,0x955AAE17, +0x46756828,0x9523369C,0x4621647D,0x94EC010B,0x45CD358F,0x94B50D87,0x4578DB93, +0x947E5C33,0x452456BD,0x9447ED2F,0x44CFA740,0x9411C09E,0x447ACD50,0x93DBD6A0, +0x4425C923,0x93A62F57,0x43D09AED,0x9370CAE4,0x437B42E1,0x933BA968,0x4325C135, +0x9306CB04,0x42D0161E,0x92D22FD9,0x427A41D0,0x929DD806,0x42244481,0x9269C3AC, +0x41CE1E65,0x9235F2EC,0x4177CFB1,0x920265E4,0x4121589B,0x91CF1CB6,0x40CAB958, +0x919C1781,0x4073F21D,0x91695663,0x401D0321,0x9136D97D,0x3FC5EC98,0x9104A0EE, +0x3F6EAEB8,0x90D2ACD4,0x3F1749B8,0x90A0FD4E,0x3EBFBDCD,0x906F927C,0x3E680B2C, +0x903E6C7B,0x3E10320D,0x900D8B69,0x3DB832A6,0x8FDCEF66,0x3D600D2C,0x8FAC988F, +0x3D07C1D6,0x8F7C8701,0x3CAF50DA,0x8F4CBADB,0x3C56BA70,0x8F1D343A,0x3BFDFECD, +0x8EEDF33B,0x3BA51E29,0x8EBEF7FB,0x3B4C18BA,0x8E904298,0x3AF2EEB7,0x8E61D32E, +0x3A99A057,0x8E33A9DA,0x3A402DD2,0x8E05C6B7,0x39E6975E,0x8DD829E4,0x398CDD32, +0x8DAAD37B,0x3932FF87,0x8D7DC399,0x38D8FE93,0x8D50FA59,0x387EDA8E,0x8D2477D8, +0x382493B0,0x8CF83C30,0x37CA2A30,0x8CCC477D,0x376F9E46,0x8CA099DA,0x3714F02A, +0x8C753362,0x36BA2014,0x8C4A142F,0x365F2E3B,0x8C1F3C5D,0x36041AD9,0x8BF4AC05, +0x35A8E625,0x8BCA6343,0x354D9057,0x8BA0622F,0x34F219A8,0x8B76A8E4,0x34968250, +0x8B4D377C,0x343ACA87,0x8B240E11,0x33DEF287,0x8AFB2CBB,0x3382FA88,0x8AD29394, +0x3326E2C3,0x8AAA42B4,0x32CAAB6F,0x8A823A36,0x326E54C7,0x8A5A7A31,0x3211DF04, +0x8A3302BE,0x31B54A5E,0x8A0BD3F5,0x3158970E,0x89E4EDEF,0x30FBC54D,0x89BE50C3, +0x309ED556,0x8997FC8A,0x3041C761,0x8971F15A,0x2FE49BA7,0x894C2F4C,0x2F875262, +0x8926B677,0x2F29EBCC,0x890186F2,0x2ECC681E,0x88DCA0D3,0x2E6EC792,0x88B80432, +0x2E110A62,0x8893B125,0x2DB330C7,0x886FA7C2,0x2D553AFC,0x884BE821,0x2CF72939, +0x88287256,0x2C98FBBA,0x88054677,0x2C3AB2B9,0x87E2649B,0x2BDC4E6F,0x87BFCCD7, +0x2B7DCF17,0x879D7F41,0x2B1F34EB,0x877B7BEC,0x2AC08026,0x8759C2EF,0x2A61B101, +0x8738545E,0x2A02C7B8,0x8717304E,0x29A3C485,0x86F656D3,0x2944A7A2,0x86D5C802, +0x28E5714B,0x86B583EE,0x288621B9,0x86958AAC,0x2826B928,0x8675DC4F,0x27C737D3, +0x865678EB,0x27679DF4,0x86376092,0x2707EBC7,0x86189359,0x26A82186,0x85FA1153, +0x26483F6C,0x85DBDA91,0x25E845B6,0x85BDEF28,0x2588349D,0x85A04F28,0x25280C5E, +0x8582FAA5,0x24C7CD33,0x8565F1B0,0x24677758,0x8549345C,0x24070B08,0x852CC2BB, +0x23A6887F,0x85109CDD,0x2345EFF8,0x84F4C2D4,0x22E541AF,0x84D934B1,0x22847DE0, +0x84BDF286,0x2223A4C5,0x84A2FC62,0x21C2B69C,0x84885258,0x2161B3A0,0x846DF477, +0x21009C0C,0x8453E2CF,0x209F701C,0x843A1D70,0x203E300D,0x8420A46C,0x1FDCDC1B, +0x840777D0,0x1F7B7481,0x83EE97AD,0x1F19F97B,0x83D60412,0x1EB86B46,0x83BDBD0E, +0x1E56CA1E,0x83A5C2B0,0x1DF5163F,0x838E1507,0x1D934FE5,0x8376B422,0x1D31774D, +0x835FA00F,0x1CCF8CB3,0x8348D8DC,0x1C6D9053,0x83325E97,0x1C0B826A,0x831C314E, +0x1BA96335,0x83065110,0x1B4732EF,0x82F0BDE8,0x1AE4F1D6,0x82DB77E5,0x1A82A026, +0x82C67F14,0x1A203E1B,0x82B1D381,0x19BDCBF3,0x829D753A,0x195B49EA,0x8289644B, +0x18F8B83C,0x8275A0C0,0x18961728,0x82622AA6,0x183366E9,0x824F0208,0x17D0A7BC, +0x823C26F3,0x176DD9DE,0x82299971,0x170AFD8D,0x82175990,0x16A81305,0x82056758, +0x16451A83,0x81F3C2D7,0x15E21445,0x81E26C16,0x157F0086,0x81D16321,0x151BDF86, +0x81C0A801,0x14B8B17F,0x81B03AC2,0x145576B1,0x81A01B6D,0x13F22F58,0x81904A0C, +0x138EDBB1,0x8180C6A9,0x132B7BF9,0x8171914E,0x12C8106F,0x8162AA04,0x1264994E, +0x815410D4,0x120116D5,0x8145C5C7,0x119D8941,0x8137C8E6,0x1139F0CF,0x812A1A3A, +0x10D64DBD,0x811CB9CA,0x1072A048,0x810FA7A0,0x100EE8AD,0x8102E3C4,0x0FAB272B, +0x80F66E3C,0x0F475BFF,0x80EA4712,0x0EE38766,0x80DE6E4C,0x0E7FA99E,0x80D2E3F2, +0x0E1BC2E4,0x80C7A80A,0x0DB7D376,0x80BCBA9D,0x0D53DB92,0x80B21BAF,0x0CEFDB76, +0x80A7CB49,0x0C8BD35E,0x809DC971,0x0C27C389,0x8094162C,0x0BC3AC35,0x808AB180, +0x0B5F8D9F,0x80819B74,0x0AFB6805,0x8078D40D,0x0A973BA5,0x80705B50,0x0A3308BD, +0x80683143,0x09CECF89,0x806055EB,0x096A9049,0x8058C94C,0x09064B3A,0x80518B6B, +0x08A2009A,0x804A9C4D,0x083DB0A7,0x8043FBF6,0x07D95B9E,0x803DAA6A,0x077501BE, +0x8037A7AC,0x0710A345,0x8031F3C2,0x06AC406F,0x802C8EAD,0x0647D97C,0x80277872, +0x05E36EA9,0x8022B114,0x057F0035,0x801E3895,0x051A8E5C,0x801A0EF8,0x04B6195D, +0x80163440,0x0451A177,0x8012A86F,0x03ED26E6,0x800F6B88,0x0388A9EA,0x800C7D8C, +0x03242ABF,0x8009DE7E,0x02BFA9A4,0x80078E5E,0x025B26D7,0x80058D2F,0x01F6A297, +0x8003DAF1,0x01921D20,0x800277A6,0x012D96B1,0x8001634E,0x00C90F88,0x80009DEA, +0x006487E3,0x8000277A,0x00000000,0x80000000,0xFF9B781D,0x8000277A,0xFF36F078, +0x80009DEA,0xFED2694F,0x8001634E,0xFE6DE2E0,0x800277A6,0xFE095D69,0x8003DAF1, +0xFDA4D929,0x80058D2F,0xFD40565C,0x80078E5E,0xFCDBD541,0x8009DE7E,0xFC775616, +0x800C7D8C,0xFC12D91A,0x800F6B88,0xFBAE5E89,0x8012A86F,0xFB49E6A3,0x80163440, +0xFAE571A4,0x801A0EF8,0xFA80FFCB,0x801E3895,0xFA1C9157,0x8022B114,0xF9B82684, +0x80277872,0xF953BF91,0x802C8EAD,0xF8EF5CBB,0x8031F3C2,0xF88AFE42,0x8037A7AC, +0xF826A462,0x803DAA6A,0xF7C24F59,0x8043FBF6,0xF75DFF66,0x804A9C4D,0xF6F9B4C6, +0x80518B6B,0xF6956FB7,0x8058C94C,0xF6313077,0x806055EB,0xF5CCF743,0x80683143, +0xF568C45B,0x80705B50,0xF50497FB,0x8078D40D,0xF4A07261,0x80819B74,0xF43C53CB, +0x808AB180,0xF3D83C77,0x8094162C,0xF3742CA2,0x809DC971,0xF310248A,0x80A7CB49, +0xF2AC246E,0x80B21BAF,0xF2482C8A,0x80BCBA9D,0xF1E43D1C,0x80C7A80A,0xF1805662, +0x80D2E3F2,0xF11C789A,0x80DE6E4C,0xF0B8A401,0x80EA4712,0xF054D8D5,0x80F66E3C, +0xEFF11753,0x8102E3C4,0xEF8D5FB8,0x810FA7A0,0xEF29B243,0x811CB9CA,0xEEC60F31, +0x812A1A3A,0xEE6276BF,0x8137C8E6,0xEDFEE92B,0x8145C5C7,0xED9B66B2,0x815410D4, +0xED37EF91,0x8162AA04,0xECD48407,0x8171914E,0xEC71244F,0x8180C6A9,0xEC0DD0A8, +0x81904A0C,0xEBAA894F,0x81A01B6D,0xEB474E81,0x81B03AC2,0xEAE4207A,0x81C0A801, +0xEA80FF7A,0x81D16321,0xEA1DEBBB,0x81E26C16,0xE9BAE57D,0x81F3C2D7,0xE957ECFB, +0x82056758,0xE8F50273,0x82175990,0xE8922622,0x82299971,0xE82F5844,0x823C26F3, +0xE7CC9917,0x824F0208,0xE769E8D8,0x82622AA6,0xE70747C4,0x8275A0C0,0xE6A4B616, +0x8289644B,0xE642340D,0x829D753A,0xE5DFC1E5,0x82B1D381,0xE57D5FDA,0x82C67F14, +0xE51B0E2A,0x82DB77E5,0xE4B8CD11,0x82F0BDE8,0xE4569CCB,0x83065110,0xE3F47D96, +0x831C314E,0xE3926FAD,0x83325E97,0xE330734D,0x8348D8DC,0xE2CE88B3,0x835FA00F, +0xE26CB01B,0x8376B422,0xE20AE9C1,0x838E1507,0xE1A935E2,0x83A5C2B0,0xE14794BA, +0x83BDBD0E,0xE0E60685,0x83D60412,0xE0848B7F,0x83EE97AD,0xE02323E5,0x840777D0, +0xDFC1CFF3,0x8420A46C,0xDF608FE4,0x843A1D70,0xDEFF63F4,0x8453E2CF,0xDE9E4C60, +0x846DF477,0xDE3D4964,0x84885258,0xDDDC5B3B,0x84A2FC62,0xDD7B8220,0x84BDF286, +0xDD1ABE51,0x84D934B1,0xDCBA1008,0x84F4C2D4,0xDC597781,0x85109CDD,0xDBF8F4F8, +0x852CC2BB,0xDB9888A8,0x8549345C,0xDB3832CD,0x8565F1B0,0xDAD7F3A2,0x8582FAA5, +0xDA77CB63,0x85A04F28,0xDA17BA4A,0x85BDEF28,0xD9B7C094,0x85DBDA91,0xD957DE7A, +0x85FA1153,0xD8F81439,0x86189359,0xD898620C,0x86376092,0xD838C82D,0x865678EB, +0xD7D946D8,0x8675DC4F,0xD779DE47,0x86958AAC,0xD71A8EB5,0x86B583EE,0xD6BB585E, +0x86D5C802,0xD65C3B7B,0x86F656D3,0xD5FD3848,0x8717304E,0xD59E4EFF,0x8738545E, +0xD53F7FDA,0x8759C2EF,0xD4E0CB15,0x877B7BEC,0xD48230E9,0x879D7F41,0xD423B191, +0x87BFCCD7,0xD3C54D47,0x87E2649B,0xD3670446,0x88054677,0xD308D6C7,0x88287256, +0xD2AAC504,0x884BE821,0xD24CCF39,0x886FA7C2,0xD1EEF59E,0x8893B125,0xD191386E, +0x88B80432,0xD13397E2,0x88DCA0D3,0xD0D61434,0x890186F2,0xD078AD9E,0x8926B677, +0xD01B6459,0x894C2F4C,0xCFBE389F,0x8971F15A,0xCF612AAA,0x8997FC8A,0xCF043AB3, +0x89BE50C3,0xCEA768F2,0x89E4EDEF,0xCE4AB5A2,0x8A0BD3F5,0xCDEE20FC,0x8A3302BE, +0xCD91AB39,0x8A5A7A31,0xCD355491,0x8A823A36,0xCCD91D3D,0x8AAA42B4,0xCC7D0578, +0x8AD29394,0xCC210D79,0x8AFB2CBB,0xCBC53579,0x8B240E11,0xCB697DB0,0x8B4D377C, +0xCB0DE658,0x8B76A8E4,0xCAB26FA9,0x8BA0622F,0xCA5719DB,0x8BCA6343,0xC9FBE527, +0x8BF4AC05,0xC9A0D1C5,0x8C1F3C5D,0xC945DFEC,0x8C4A142F,0xC8EB0FD6,0x8C753362, +0xC89061BA,0x8CA099DA,0xC835D5D0,0x8CCC477D,0xC7DB6C50,0x8CF83C30,0xC7812572, +0x8D2477D8,0xC727016D,0x8D50FA59,0xC6CD0079,0x8D7DC399,0xC67322CE,0x8DAAD37B, +0xC61968A2,0x8DD829E4,0xC5BFD22E,0x8E05C6B7,0xC5665FA9,0x8E33A9DA,0xC50D1149, +0x8E61D32E,0xC4B3E746,0x8E904298,0xC45AE1D7,0x8EBEF7FB,0xC4020133,0x8EEDF33B, +0xC3A94590,0x8F1D343A,0xC350AF26,0x8F4CBADB,0xC2F83E2A,0x8F7C8701,0xC29FF2D4, +0x8FAC988F,0xC247CD5A,0x8FDCEF66,0xC1EFCDF3,0x900D8B69,0xC197F4D4,0x903E6C7B, +0xC1404233,0x906F927C,0xC0E8B648,0x90A0FD4E,0xC0915148,0x90D2ACD4,0xC03A1368, +0x9104A0EE,0xBFE2FCDF,0x9136D97D,0xBF8C0DE3,0x91695663,0xBF3546A8,0x919C1781, +0xBEDEA765,0x91CF1CB6,0xBE88304F,0x920265E4,0xBE31E19B,0x9235F2EC,0xBDDBBB7F, +0x9269C3AC,0xBD85BE30,0x929DD806,0xBD2FE9E2,0x92D22FD9,0xBCDA3ECB,0x9306CB04, +0xBC84BD1F,0x933BA968,0xBC2F6513,0x9370CAE4,0xBBDA36DD,0x93A62F57,0xBB8532B0, +0x93DBD6A0,0xBB3058C0,0x9411C09E,0xBADBA943,0x9447ED2F,0xBA87246D,0x947E5C33, +0xBA32CA71,0x94B50D87,0xB9DE9B83,0x94EC010B,0xB98A97D8,0x9523369C,0xB936BFA4, +0x955AAE17,0xB8E31319,0x9592675C,0xB88F926D,0x95CA6247,0xB83C3DD1,0x96029EB6, +0xB7E9157A,0x963B1C86,0xB796199B,0x9673DB94,0xB7434A67,0x96ACDBBE,0xB6F0A812, +0x96E61CE0,0xB69E32CD,0x971F9ED7,0xB64BEACD,0x9759617F,0xB5F9D043,0x979364B5, +0xB5A7E362,0x97CDA855,0xB556245E,0x98082C3B,0xB5049368,0x9842F043,0xB4B330B3, +0x987DF449,0xB461FC70,0x98B93828,0xB410F6D3,0x98F4BBBC,0xB3C0200C,0x99307EE0, +0xB36F784F,0x996C816F,0xB31EFFCC,0x99A8C345,0xB2CEB6B5,0x99E5443B,0xB27E9D3C, +0x9A22042D,0xB22EB392,0x9A5F02F5,0xB1DEF9E9,0x9A9C406E,0xB18F7071,0x9AD9BC71, +0xB140175B,0x9B1776DA,0xB0F0EEDA,0x9B556F81,0xB0A1F71D,0x9B93A641,0xB0533055, +0x9BD21AF3,0xB0049AB3,0x9C10CD70,0xAFB63667,0x9C4FBD93,0xAF6803A2,0x9C8EEB34, +0xAF1A0293,0x9CCE562C,0xAECC336C,0x9D0DFE54,0xAE7E965B,0x9D4DE385,0xAE312B92, +0x9D8E0597,0xADE3F33E,0x9DCE6463,0xAD96ED92,0x9E0EFFC1,0xAD4A1ABA,0x9E4FD78A, +0xACFD7AE8,0x9E90EB94,0xACB10E4B,0x9ED23BB9,0xAC64D510,0x9F13C7D0,0xAC18CF69, +0x9F558FB0,0xABCCFD83,0x9F979331,0xAB815F8D,0x9FD9D22A,0xAB35F5B5,0xA01C4C73, +0xAAEAC02C,0xA05F01E1,0xAA9FBF1E,0xA0A1F24D,0xAA54F2BA,0xA0E51D8C,0xAA0A5B2E, +0xA1288376,0xA9BFF8A8,0xA16C23E1,0xA975CB57,0xA1AFFEA3,0xA92BD367,0xA1F41392, +0xA8E21106,0xA2386284,0xA8988463,0xA27CEB4F,0xA84F2DAA,0xA2C1ADC9,0xA8060D08, +0xA306A9C8,0xA7BD22AC,0xA34BDF20,0xA7746EC0,0xA3914DA8,0xA72BF174,0xA3D6F534, +0xA6E3AAF2,0xA41CD599,0xA69B9B68,0xA462EEAC,0xA653C303,0xA4A94043,0xA60C21EE, +0xA4EFCA31,0xA5C4B855,0xA5368C4B,0xA57D8666,0xA57D8666,0xA5368C4B,0xA5C4B855, +0xA4EFCA31,0xA60C21EE,0xA4A94043,0xA653C303,0xA462EEAC,0xA69B9B68,0xA41CD599, +0xA6E3AAF2,0xA3D6F534,0xA72BF174,0xA3914DA8,0xA7746EC0,0xA34BDF20,0xA7BD22AC, +0xA306A9C8,0xA8060D08,0xA2C1ADC9,0xA84F2DAA,0xA27CEB4F,0xA8988463,0xA2386284, +0xA8E21106,0xA1F41392,0xA92BD367,0xA1AFFEA3,0xA975CB57,0xA16C23E1,0xA9BFF8A8, +0xA1288376,0xAA0A5B2E,0xA0E51D8C,0xAA54F2BA,0xA0A1F24D,0xAA9FBF1E,0xA05F01E1, +0xAAEAC02C,0xA01C4C73,0xAB35F5B5,0x9FD9D22A,0xAB815F8D,0x9F979331,0xABCCFD83, +0x9F558FB0,0xAC18CF69,0x9F13C7D0,0xAC64D510,0x9ED23BB9,0xACB10E4B,0x9E90EB94, +0xACFD7AE8,0x9E4FD78A,0xAD4A1ABA,0x9E0EFFC1,0xAD96ED92,0x9DCE6463,0xADE3F33E, +0x9D8E0597,0xAE312B92,0x9D4DE385,0xAE7E965B,0x9D0DFE54,0xAECC336C,0x9CCE562C, +0xAF1A0293,0x9C8EEB34,0xAF6803A2,0x9C4FBD93,0xAFB63667,0x9C10CD70,0xB0049AB3, +0x9BD21AF3,0xB0533055,0x9B93A641,0xB0A1F71D,0x9B556F81,0xB0F0EEDA,0x9B1776DA, +0xB140175B,0x9AD9BC71,0xB18F7071,0x9A9C406E,0xB1DEF9E9,0x9A5F02F5,0xB22EB392, +0x9A22042D,0xB27E9D3C,0x99E5443B,0xB2CEB6B5,0x99A8C345,0xB31EFFCC,0x996C816F, +0xB36F784F,0x99307EE0,0xB3C0200C,0x98F4BBBC,0xB410F6D3,0x98B93828,0xB461FC70, +0x987DF449,0xB4B330B3,0x9842F043,0xB5049368,0x98082C3B,0xB556245E,0x97CDA855, +0xB5A7E362,0x979364B5,0xB5F9D043,0x9759617F,0xB64BEACD,0x971F9ED7,0xB69E32CD, +0x96E61CE0,0xB6F0A812,0x96ACDBBE,0xB7434A67,0x9673DB94,0xB796199B,0x963B1C86, +0xB7E9157A,0x96029EB6,0xB83C3DD1,0x95CA6247,0xB88F926D,0x9592675C,0xB8E31319, +0x955AAE17,0xB936BFA4,0x9523369C,0xB98A97D8,0x94EC010B,0xB9DE9B83,0x94B50D87, +0xBA32CA71,0x947E5C33,0xBA87246D,0x9447ED2F,0xBADBA943,0x9411C09E,0xBB3058C0, +0x93DBD6A0,0xBB8532B0,0x93A62F57,0xBBDA36DD,0x9370CAE4,0xBC2F6513,0x933BA968, +0xBC84BD1F,0x9306CB04,0xBCDA3ECB,0x92D22FD9,0xBD2FE9E2,0x929DD806,0xBD85BE30, +0x9269C3AC,0xBDDBBB7F,0x9235F2EC,0xBE31E19B,0x920265E4,0xBE88304F,0x91CF1CB6, +0xBEDEA765,0x919C1781,0xBF3546A8,0x91695663,0xBF8C0DE3,0x9136D97D,0xBFE2FCDF, +0x9104A0EE,0xC03A1368,0x90D2ACD4,0xC0915148,0x90A0FD4E,0xC0E8B648,0x906F927C, +0xC1404233,0x903E6C7B,0xC197F4D4,0x900D8B69,0xC1EFCDF3,0x8FDCEF66,0xC247CD5A, +0x8FAC988F,0xC29FF2D4,0x8F7C8701,0xC2F83E2A,0x8F4CBADB,0xC350AF26,0x8F1D343A, +0xC3A94590,0x8EEDF33B,0xC4020133,0x8EBEF7FB,0xC45AE1D7,0x8E904298,0xC4B3E746, +0x8E61D32E,0xC50D1149,0x8E33A9DA,0xC5665FA9,0x8E05C6B7,0xC5BFD22E,0x8DD829E4, +0xC61968A2,0x8DAAD37B,0xC67322CE,0x8D7DC399,0xC6CD0079,0x8D50FA59,0xC727016D, +0x8D2477D8,0xC7812572,0x8CF83C30,0xC7DB6C50,0x8CCC477D,0xC835D5D0,0x8CA099DA, +0xC89061BA,0x8C753362,0xC8EB0FD6,0x8C4A142F,0xC945DFEC,0x8C1F3C5D,0xC9A0D1C5, +0x8BF4AC05,0xC9FBE527,0x8BCA6343,0xCA5719DB,0x8BA0622F,0xCAB26FA9,0x8B76A8E4, +0xCB0DE658,0x8B4D377C,0xCB697DB0,0x8B240E11,0xCBC53579,0x8AFB2CBB,0xCC210D79, +0x8AD29394,0xCC7D0578,0x8AAA42B4,0xCCD91D3D,0x8A823A36,0xCD355491,0x8A5A7A31, +0xCD91AB39,0x8A3302BE,0xCDEE20FC,0x8A0BD3F5,0xCE4AB5A2,0x89E4EDEF,0xCEA768F2, +0x89BE50C3,0xCF043AB3,0x8997FC8A,0xCF612AAA,0x8971F15A,0xCFBE389F,0x894C2F4C, +0xD01B6459,0x8926B677,0xD078AD9E,0x890186F2,0xD0D61434,0x88DCA0D3,0xD13397E2, +0x88B80432,0xD191386E,0x8893B125,0xD1EEF59E,0x886FA7C2,0xD24CCF39,0x884BE821, +0xD2AAC504,0x88287256,0xD308D6C7,0x88054677,0xD3670446,0x87E2649B,0xD3C54D47, +0x87BFCCD7,0xD423B191,0x879D7F41,0xD48230E9,0x877B7BEC,0xD4E0CB15,0x8759C2EF, +0xD53F7FDA,0x8738545E,0xD59E4EFF,0x8717304E,0xD5FD3848,0x86F656D3,0xD65C3B7B, +0x86D5C802,0xD6BB585E,0x86B583EE,0xD71A8EB5,0x86958AAC,0xD779DE47,0x8675DC4F, +0xD7D946D8,0x865678EB,0xD838C82D,0x86376092,0xD898620C,0x86189359,0xD8F81439, +0x85FA1153,0xD957DE7A,0x85DBDA91,0xD9B7C094,0x85BDEF28,0xDA17BA4A,0x85A04F28, +0xDA77CB63,0x8582FAA5,0xDAD7F3A2,0x8565F1B0,0xDB3832CD,0x8549345C,0xDB9888A8, +0x852CC2BB,0xDBF8F4F8,0x85109CDD,0xDC597781,0x84F4C2D4,0xDCBA1008,0x84D934B1, +0xDD1ABE51,0x84BDF286,0xDD7B8220,0x84A2FC62,0xDDDC5B3B,0x84885258,0xDE3D4964, +0x846DF477,0xDE9E4C60,0x8453E2CF,0xDEFF63F4,0x843A1D70,0xDF608FE4,0x8420A46C, +0xDFC1CFF3,0x840777D0,0xE02323E5,0x83EE97AD,0xE0848B7F,0x83D60412,0xE0E60685, +0x83BDBD0E,0xE14794BA,0x83A5C2B0,0xE1A935E2,0x838E1507,0xE20AE9C1,0x8376B422, +0xE26CB01B,0x835FA00F,0xE2CE88B3,0x8348D8DC,0xE330734D,0x83325E97,0xE3926FAD, +0x831C314E,0xE3F47D96,0x83065110,0xE4569CCB,0x82F0BDE8,0xE4B8CD11,0x82DB77E5, +0xE51B0E2A,0x82C67F14,0xE57D5FDA,0x82B1D381,0xE5DFC1E5,0x829D753A,0xE642340D, +0x8289644B,0xE6A4B616,0x8275A0C0,0xE70747C4,0x82622AA6,0xE769E8D8,0x824F0208, +0xE7CC9917,0x823C26F3,0xE82F5844,0x82299971,0xE8922622,0x82175990,0xE8F50273, +0x82056758,0xE957ECFB,0x81F3C2D7,0xE9BAE57D,0x81E26C16,0xEA1DEBBB,0x81D16321, +0xEA80FF7A,0x81C0A801,0xEAE4207A,0x81B03AC2,0xEB474E81,0x81A01B6D,0xEBAA894F, +0x81904A0C,0xEC0DD0A8,0x8180C6A9,0xEC71244F,0x8171914E,0xECD48407,0x8162AA04, +0xED37EF91,0x815410D4,0xED9B66B2,0x8145C5C7,0xEDFEE92B,0x8137C8E6,0xEE6276BF, +0x812A1A3A,0xEEC60F31,0x811CB9CA,0xEF29B243,0x810FA7A0,0xEF8D5FB8,0x8102E3C4, +0xEFF11753,0x80F66E3C,0xF054D8D5,0x80EA4712,0xF0B8A401,0x80DE6E4C,0xF11C789A, +0x80D2E3F2,0xF1805662,0x80C7A80A,0xF1E43D1C,0x80BCBA9D,0xF2482C8A,0x80B21BAF, +0xF2AC246E,0x80A7CB49,0xF310248A,0x809DC971,0xF3742CA2,0x8094162C,0xF3D83C77, +0x808AB180,0xF43C53CB,0x80819B74,0xF4A07261,0x8078D40D,0xF50497FB,0x80705B50, +0xF568C45B,0x80683143,0xF5CCF743,0x806055EB,0xF6313077,0x8058C94C,0xF6956FB7, +0x80518B6B,0xF6F9B4C6,0x804A9C4D,0xF75DFF66,0x8043FBF6,0xF7C24F59,0x803DAA6A, +0xF826A462,0x8037A7AC,0xF88AFE42,0x8031F3C2,0xF8EF5CBB,0x802C8EAD,0xF953BF91, +0x80277872,0xF9B82684,0x8022B114,0xFA1C9157,0x801E3895,0xFA80FFCB,0x801A0EF8, +0xFAE571A4,0x80163440,0xFB49E6A3,0x8012A86F,0xFBAE5E89,0x800F6B88,0xFC12D91A, +0x800C7D8C,0xFC775616,0x8009DE7E,0xFCDBD541,0x80078E5E,0xFD40565C,0x80058D2F, +0xFDA4D929,0x8003DAF1,0xFE095D69,0x800277A6,0xFE6DE2E0,0x8001634E,0xFED2694F, +0x80009DEA,0xFF36F078,0x8000277A,0xFF9B781D,0x7FFFFFFF,0x00000000,0x7FFD885A, +0xFE6DE2E0,0x7FF62182,0xFCDBD541,0x7FE9CBC0,0xFB49E6A3,0x7FD8878E,0xF9B82684, +0x7FC25596,0xF826A462,0x7FA736B4,0xF6956FB7,0x7F872BF3,0xF50497FB,0x7F62368F, +0xF3742CA2,0x7F3857F6,0xF1E43D1C,0x7F0991C4,0xF054D8D5,0x7ED5E5C6,0xEEC60F31, +0x7E9D55FC,0xED37EF91,0x7E5FE493,0xEBAA894F,0x7E1D93EA,0xEA1DEBBB,0x7DD6668F, +0xE8922622,0x7D8A5F40,0xE70747C4,0x7D3980EC,0xE57D5FDA,0x7CE3CEB2,0xE3F47D96, +0x7C894BDE,0xE26CB01B,0x7C29FBEE,0xE0E60685,0x7BC5E290,0xDF608FE4,0x7B5D039E, +0xDDDC5B3B,0x7AEF6323,0xDC597781,0x7A7D055B,0xDAD7F3A2,0x7A05EEAD,0xD957DE7A, +0x798A23B1,0xD7D946D8,0x7909A92D,0xD65C3B7B,0x78848414,0xD4E0CB15,0x77FAB989, +0xD3670446,0x776C4EDB,0xD1EEF59E,0x76D94989,0xD078AD9E,0x7641AF3D,0xCF043AB3, +0x75A585CF,0xCD91AB39,0x7504D345,0xCC210D79,0x745F9DD1,0xCAB26FA9,0x73B5EBD1, +0xC945DFEC,0x7307C3D0,0xC7DB6C50,0x72552C85,0xC67322CE,0x719E2CD2,0xC50D1149, +0x70E2CBC6,0xC3A94590,0x7023109A,0xC247CD5A,0x6F5F02B2,0xC0E8B648,0x6E96A99D, +0xBF8C0DE3,0x6DCA0D14,0xBE31E19B,0x6CF934FC,0xBCDA3ECB,0x6C242960,0xBB8532B0, +0x6B4AF279,0xBA32CA71,0x6A6D98A4,0xB8E31319,0x698C246C,0xB796199B,0x68A69E81, +0xB64BEACD,0x67BD0FBD,0xB5049368,0x66CF8120,0xB3C0200C,0x65DDFBD3,0xB27E9D3C, +0x64E88926,0xB140175B,0x63EF3290,0xB0049AB3,0x62F201AC,0xAECC336C,0x61F1003F, +0xAD96ED92,0x60EC3830,0xAC64D510,0x5FE3B38D,0xAB35F5B5,0x5ED77C8A,0xAA0A5B2E, +0x5DC79D7C,0xA8E21106,0x5CB420E0,0xA7BD22AC,0x5B9D1154,0xA69B9B68,0x5A82799A, +0xA57D8666,0x59646498,0xA462EEAC,0x5842DD54,0xA34BDF20,0x571DEEFA,0xA2386284, +0x55F5A4D2,0xA1288376,0x54CA0A4B,0xA01C4C73,0x539B2AF0,0x9F13C7D0,0x5269126E, +0x9E0EFFC1,0x5133CC94,0x9D0DFE54,0x4FFB654D,0x9C10CD70,0x4EBFE8A5,0x9B1776DA, +0x4D8162C4,0x9A22042D,0x4C3FDFF4,0x99307EE0,0x4AFB6C98,0x9842F043,0x49B41533, +0x9759617F,0x4869E665,0x9673DB94,0x471CECE7,0x9592675C,0x45CD358F,0x94B50D87, +0x447ACD50,0x93DBD6A0,0x4325C135,0x9306CB04,0x41CE1E65,0x9235F2EC,0x4073F21D, +0x91695663,0x3F1749B8,0x90A0FD4E,0x3DB832A6,0x8FDCEF66,0x3C56BA70,0x8F1D343A, +0x3AF2EEB7,0x8E61D32E,0x398CDD32,0x8DAAD37B,0x382493B0,0x8CF83C30,0x36BA2014, +0x8C4A142F,0x354D9057,0x8BA0622F,0x33DEF287,0x8AFB2CBB,0x326E54C7,0x8A5A7A31, +0x30FBC54D,0x89BE50C3,0x2F875262,0x8926B677,0x2E110A62,0x8893B125,0x2C98FBBA, +0x88054677,0x2B1F34EB,0x877B7BEC,0x29A3C485,0x86F656D3,0x2826B928,0x8675DC4F, +0x26A82186,0x85FA1153,0x25280C5E,0x8582FAA5,0x23A6887F,0x85109CDD,0x2223A4C5, +0x84A2FC62,0x209F701C,0x843A1D70,0x1F19F97B,0x83D60412,0x1D934FE5,0x8376B422, +0x1C0B826A,0x831C314E,0x1A82A026,0x82C67F14,0x18F8B83C,0x8275A0C0,0x176DD9DE, +0x82299971,0x15E21445,0x81E26C16,0x145576B1,0x81A01B6D,0x12C8106F,0x8162AA04, +0x1139F0CF,0x812A1A3A,0x0FAB272B,0x80F66E3C,0x0E1BC2E4,0x80C7A80A,0x0C8BD35E, +0x809DC971,0x0AFB6805,0x8078D40D,0x096A9049,0x8058C94C,0x07D95B9E,0x803DAA6A, +0x0647D97C,0x80277872,0x04B6195D,0x80163440,0x03242ABF,0x8009DE7E,0x01921D20, +0x800277A6,0x00000000,0x80000000,0xFE6DE2E0,0x800277A6,0xFCDBD541,0x8009DE7E, +0xFB49E6A3,0x80163440,0xF9B82684,0x80277872,0xF826A462,0x803DAA6A,0xF6956FB7, +0x8058C94C,0xF50497FB,0x8078D40D,0xF3742CA2,0x809DC971,0xF1E43D1C,0x80C7A80A, +0xF054D8D5,0x80F66E3C,0xEEC60F31,0x812A1A3A,0xED37EF91,0x8162AA04,0xEBAA894F, +0x81A01B6D,0xEA1DEBBB,0x81E26C16,0xE8922622,0x82299971,0xE70747C4,0x8275A0C0, +0xE57D5FDA,0x82C67F14,0xE3F47D96,0x831C314E,0xE26CB01B,0x8376B422,0xE0E60685, +0x83D60412,0xDF608FE4,0x843A1D70,0xDDDC5B3B,0x84A2FC62,0xDC597781,0x85109CDD, +0xDAD7F3A2,0x8582FAA5,0xD957DE7A,0x85FA1153,0xD7D946D8,0x8675DC4F,0xD65C3B7B, +0x86F656D3,0xD4E0CB15,0x877B7BEC,0xD3670446,0x88054677,0xD1EEF59E,0x8893B125, +0xD078AD9E,0x8926B677,0xCF043AB3,0x89BE50C3,0xCD91AB39,0x8A5A7A31,0xCC210D79, +0x8AFB2CBB,0xCAB26FA9,0x8BA0622F,0xC945DFEC,0x8C4A142F,0xC7DB6C50,0x8CF83C30, +0xC67322CE,0x8DAAD37B,0xC50D1149,0x8E61D32E,0xC3A94590,0x8F1D343A,0xC247CD5A, +0x8FDCEF66,0xC0E8B648,0x90A0FD4E,0xBF8C0DE3,0x91695663,0xBE31E19B,0x9235F2EC, +0xBCDA3ECB,0x9306CB04,0xBB8532B0,0x93DBD6A0,0xBA32CA71,0x94B50D87,0xB8E31319, +0x9592675C,0xB796199B,0x9673DB94,0xB64BEACD,0x9759617F,0xB5049368,0x9842F043, +0xB3C0200C,0x99307EE0,0xB27E9D3C,0x9A22042D,0xB140175B,0x9B1776DA,0xB0049AB3, +0x9C10CD70,0xAECC336C,0x9D0DFE54,0xAD96ED92,0x9E0EFFC1,0xAC64D510,0x9F13C7D0, +0xAB35F5B5,0xA01C4C73,0xAA0A5B2E,0xA1288376,0xA8E21106,0xA2386284,0xA7BD22AC, +0xA34BDF20,0xA69B9B68,0xA462EEAC,0xA57D8666,0xA57D8666,0xA462EEAC,0xA69B9B68, +0xA34BDF20,0xA7BD22AC,0xA2386284,0xA8E21106,0xA1288376,0xAA0A5B2E,0xA01C4C73, +0xAB35F5B5,0x9F13C7D0,0xAC64D510,0x9E0EFFC1,0xAD96ED92,0x9D0DFE54,0xAECC336C, +0x9C10CD70,0xB0049AB3,0x9B1776DA,0xB140175B,0x9A22042D,0xB27E9D3C,0x99307EE0, +0xB3C0200C,0x9842F043,0xB5049368,0x9759617F,0xB64BEACD,0x9673DB94,0xB796199B, +0x9592675C,0xB8E31319,0x94B50D87,0xBA32CA71,0x93DBD6A0,0xBB8532B0,0x9306CB04, +0xBCDA3ECB,0x9235F2EC,0xBE31E19B,0x91695663,0xBF8C0DE3,0x90A0FD4E,0xC0E8B648, +0x8FDCEF66,0xC247CD5A,0x8F1D343A,0xC3A94590,0x8E61D32E,0xC50D1149,0x8DAAD37B, +0xC67322CE,0x8CF83C30,0xC7DB6C50,0x8C4A142F,0xC945DFEC,0x8BA0622F,0xCAB26FA9, +0x8AFB2CBB,0xCC210D79,0x8A5A7A31,0xCD91AB39,0x89BE50C3,0xCF043AB3,0x8926B677, +0xD078AD9E,0x8893B125,0xD1EEF59E,0x88054677,0xD3670446,0x877B7BEC,0xD4E0CB15, +0x86F656D3,0xD65C3B7B,0x8675DC4F,0xD7D946D8,0x85FA1153,0xD957DE7A,0x8582FAA5, +0xDAD7F3A2,0x85109CDD,0xDC597781,0x84A2FC62,0xDDDC5B3B,0x843A1D70,0xDF608FE4, +0x83D60412,0xE0E60685,0x8376B422,0xE26CB01B,0x831C314E,0xE3F47D96,0x82C67F14, +0xE57D5FDA,0x8275A0C0,0xE70747C4,0x82299971,0xE8922622,0x81E26C16,0xEA1DEBBB, +0x81A01B6D,0xEBAA894F,0x8162AA04,0xED37EF91,0x812A1A3A,0xEEC60F31,0x80F66E3C, +0xF054D8D5,0x80C7A80A,0xF1E43D1C,0x809DC971,0xF3742CA2,0x8078D40D,0xF50497FB, +0x8058C94C,0xF6956FB7,0x803DAA6A,0xF826A462,0x80277872,0xF9B82684,0x80163440, +0xFB49E6A3,0x8009DE7E,0xFCDBD541,0x800277A6,0xFE6DE2E0,0x7FFFFFFF,0x00000000, +0x7FD8878E,0xF9B82684,0x7F62368F,0xF3742CA2,0x7E9D55FC,0xED37EF91,0x7D8A5F40, +0xE70747C4,0x7C29FBEE,0xE0E60685,0x7A7D055B,0xDAD7F3A2,0x78848414,0xD4E0CB15, +0x7641AF3D,0xCF043AB3,0x73B5EBD1,0xC945DFEC,0x70E2CBC6,0xC3A94590,0x6DCA0D14, +0xBE31E19B,0x6A6D98A4,0xB8E31319,0x66CF8120,0xB3C0200C,0x62F201AC,0xAECC336C, +0x5ED77C8A,0xAA0A5B2E,0x5A82799A,0xA57D8666,0x55F5A4D2,0xA1288376,0x5133CC94, +0x9D0DFE54,0x4C3FDFF4,0x99307EE0,0x471CECE7,0x9592675C,0x41CE1E65,0x9235F2EC, +0x3C56BA70,0x8F1D343A,0x36BA2014,0x8C4A142F,0x30FBC54D,0x89BE50C3,0x2B1F34EB, +0x877B7BEC,0x25280C5E,0x8582FAA5,0x1F19F97B,0x83D60412,0x18F8B83C,0x8275A0C0, +0x12C8106F,0x8162AA04,0x0C8BD35E,0x809DC971,0x0647D97C,0x80277872,0x00000000, +0x80000000,0xF9B82684,0x80277872,0xF3742CA2,0x809DC971,0xED37EF91,0x8162AA04, +0xE70747C4,0x8275A0C0,0xE0E60685,0x83D60412,0xDAD7F3A2,0x8582FAA5,0xD4E0CB15, +0x877B7BEC,0xCF043AB3,0x89BE50C3,0xC945DFEC,0x8C4A142F,0xC3A94590,0x8F1D343A, +0xBE31E19B,0x9235F2EC,0xB8E31319,0x9592675C,0xB3C0200C,0x99307EE0,0xAECC336C, +0x9D0DFE54,0xAA0A5B2E,0xA1288376,0xA57D8666,0xA57D8666,0xA1288376,0xAA0A5B2E, +0x9D0DFE54,0xAECC336C,0x99307EE0,0xB3C0200C,0x9592675C,0xB8E31319,0x9235F2EC, +0xBE31E19B,0x8F1D343A,0xC3A94590,0x8C4A142F,0xC945DFEC,0x89BE50C3,0xCF043AB3, +0x877B7BEC,0xD4E0CB15,0x8582FAA5,0xDAD7F3A2,0x83D60412,0xE0E60685,0x8275A0C0, +0xE70747C4,0x8162AA04,0xED37EF91,0x809DC971,0xF3742CA2,0x80277872,0xF9B82684, +0x7FFFFFFF,0x00000000,0x7D8A5F40,0xE70747C4,0x7641AF3D,0xCF043AB3,0x6A6D98A4, +0xB8E31319,0x5A82799A,0xA57D8666,0x471CECE7,0x9592675C,0x30FBC54D,0x89BE50C3, +0x18F8B83C,0x8275A0C0,0x00000000,0x80000000,0xE70747C4,0x8275A0C0,0xCF043AB3, +0x89BE50C3,0xB8E31319,0x9592675C,0xA57D8666,0xA57D8666,0x9592675C,0xB8E31319, +0x89BE50C3,0xCF043AB3,0x8275A0C0,0xE70747C4,0x7FFFFFFF,0x00000000,0x5A82799A, +0xA57D8666,0x00000000,0x80000000,0xA57D8666,0xA57D8666,}; + +q31_t rearranged_twiddle_stride3_4096_q31[2728]={ +0x7FFFFFFF,0x00000000,0x7FFFA72C,0xFF69343F,0x7FFE9CB2,0xFED2694F,0x7FFCE093, +0xFE3BA002,0x7FFA72D1,0xFDA4D929,0x7FF75370,0xFD0E1594,0x7FF38274,0xFC775616, +0x7FEEFFE1,0xFBE09B80,0x7FE9CBC0,0xFB49E6A3,0x7FE3E616,0xFAB3384F,0x7FDD4EEC, +0xFA1C9157,0x7FD6064C,0xF985F28A,0x7FCE0C3E,0xF8EF5CBB,0x7FC560CF,0xF858D0BB, +0x7FBC040A,0xF7C24F59,0x7FB1F5FC,0xF72BD967,0x7FA736B4,0xF6956FB7,0x7F9BC640, +0xF5FF1318,0x7F8FA4B0,0xF568C45B,0x7F82D214,0xF4D28451,0x7F754E80,0xF43C53CB, +0x7F671A05,0xF3A63398,0x7F5834B7,0xF310248A,0x7F489EAA,0xF27A2771,0x7F3857F6, +0xF1E43D1C,0x7F2760AF,0xF14E665C,0x7F15B8EE,0xF0B8A401,0x7F0360CB,0xF022F6DA, +0x7EF05860,0xEF8D5FB8,0x7EDC9FC6,0xEEF7DF6A,0x7EC8371A,0xEE6276BF,0x7EB31E78, +0xEDCD2687,0x7E9D55FC,0xED37EF91,0x7E86DDC6,0xECA2D2AD,0x7E6FB5F4,0xEC0DD0A8, +0x7E57DEA7,0xEB78EA52,0x7E3F57FF,0xEAE4207A,0x7E26221F,0xEA4F73EE,0x7E0C3D29, +0xE9BAE57D,0x7DF1A942,0xE92675F4,0x7DD6668F,0xE8922622,0x7DBA7534,0xE7FDF6D4, +0x7D9DD55A,0xE769E8D8,0x7D808728,0xE6D5FCFC,0x7D628AC6,0xE642340D,0x7D43E05E, +0xE5AE8ED8,0x7D24881B,0xE51B0E2A,0x7D048228,0xE487B2D0,0x7CE3CEB2,0xE3F47D96, +0x7CC26DE5,0xE3616F48,0x7CA05FF1,0xE2CE88B3,0x7C7DA505,0xE23BCAA2,0x7C5A3D50, +0xE1A935E2,0x7C362904,0xE116CB3D,0x7C116853,0xE0848B7F,0x7BEBFB70,0xDFF27773, +0x7BC5E290,0xDF608FE4,0x7B9F1DE6,0xDECED59B,0x7B77ADA8,0xDE3D4964,0x7B4F920E, +0xDDABEC08,0x7B26CB4F,0xDD1ABE51,0x7AFD59A4,0xDC89C109,0x7AD33D45,0xDBF8F4F8, +0x7AA8766F,0xDB685AE9,0x7A7D055B,0xDAD7F3A2,0x7A50EA47,0xDA47BFEE,0x7A24256F, +0xD9B7C094,0x79F6B711,0xD927F65B,0x79C89F6E,0xD898620C,0x7999DEC4,0xD809046E, +0x796A7554,0xD779DE47,0x793A6361,0xD6EAF05F,0x7909A92D,0xD65C3B7B,0x78D846FB, +0xD5CDC062,0x78A63D11,0xD53F7FDA,0x78738BB3,0xD4B17AA8,0x78403329,0xD423B191, +0x780C33B8,0xD396255A,0x77D78DAA,0xD308D6C7,0x77A24148,0xD27BC69C,0x776C4EDB, +0xD1EEF59E,0x7735B6AF,0xD1626490,0x76FE790E,0xD0D61434,0x76C69647,0xD04A054E, +0x768E0EA6,0xCFBE389F,0x7654E279,0xCF32AEEB,0x761B1211,0xCEA768F2,0x75E09DBD, +0xCE1C6777,0x75A585CF,0xCD91AB39,0x7569CA99,0xCD0734F9,0x752D6C6C,0xCC7D0578, +0x74F06B9E,0xCBF31D75,0x74B2C884,0xCB697DB0,0x74748371,0xCAE026E8,0x74359CBD, +0xCA5719DB,0x73F614C0,0xC9CE5748,0x73B5EBD1,0xC945DFEC,0x73752249,0xC8BDB485, +0x7333B883,0xC835D5D0,0x72F1AED9,0xC7AE4489,0x72AF05A7,0xC727016D,0x726BBD48, +0xC6A00D37,0x7227D61C,0xC61968A2,0x71E35080,0xC593146A,0x719E2CD2,0xC50D1149, +0x71586B74,0xC4875FF9,0x71120CC5,0xC4020133,0x70CB1128,0xC37CF5B0,0x708378FF, +0xC2F83E2A,0x703B44AD,0xC273DB58,0x6FF27497,0xC1EFCDF3,0x6FA90921,0xC16C16B0, +0x6F5F02B2,0xC0E8B648,0x6F1461B0,0xC065AD70,0x6EC92683,0xBFE2FCDF,0x6E7D5193, +0xBF60A54A,0x6E30E34A,0xBEDEA765,0x6DE3DC11,0xBE5D03E6,0x6D963C54,0xBDDBBB7F, +0x6D48047E,0xBD5ACEE5,0x6CF934FC,0xBCDA3ECB,0x6CA9CE3B,0xBC5A0BE2,0x6C59D0A9, +0xBBDA36DD,0x6C093CB6,0xBB5AC06D,0x6BB812D1,0xBADBA943,0x6B66536B,0xBA5CF210, +0x6B13FEF5,0xB9DE9B83,0x6AC115E2,0xB960A64C,0x6A6D98A4,0xB8E31319,0x6A1987B0, +0xB865E299,0x69C4E37A,0xB7E9157A,0x696FAC78,0xB76CAC69,0x6919E320,0xB6F0A812, +0x68C387E9,0xB6750921,0x686C9B4B,0xB5F9D043,0x68151DBE,0xB57EFE22,0x67BD0FBD, +0xB5049368,0x676471C0,0xB48A90C0,0x670B4444,0xB410F6D3,0x66B187C3,0xB397C649, +0x66573CBB,0xB31EFFCC,0x65FC63A9,0xB2A6A402,0x65A0FD0B,0xB22EB392,0x6545095F, +0xB1B72F23,0x64E88926,0xB140175B,0x648B7CE0,0xB0C96CE0,0x642DE50D,0xB0533055, +0x63CFC231,0xAFDD625F,0x637114CC,0xAF6803A2,0x6311DD64,0xAEF314C0,0x62B21C7B, +0xAE7E965B,0x6251D298,0xAE0A8916,0x61F1003F,0xAD96ED92,0x618FA5F7,0xAD23C46E, +0x612DC447,0xACB10E4B,0x60CB5BB7,0xAC3ECBC7,0x60686CCF,0xABCCFD83,0x6004F819, +0xAB5BA41A,0x5FA0FE1F,0xAAEAC02C,0x5F3C7F6B,0xAA7A5253,0x5ED77C8A,0xAA0A5B2E, +0x5E71F606,0xA99ADB56,0x5E0BEC6E,0xA92BD367,0x5DA5604F,0xA8BD43FA,0x5D3E5237, +0xA84F2DAA,0x5CD6C2B5,0xA7E1910F,0x5C6EB258,0xA7746EC0,0x5C0621B2,0xA707C757, +0x5B9D1154,0xA69B9B68,0x5B3381CE,0xA62FEB8B,0x5AC973B5,0xA5C4B855,0x5A5EE79A, +0xA55A025B,0x59F3DE12,0xA4EFCA31,0x598857B2,0xA486106A,0x591C550E,0xA41CD599, +0x58AFD6BD,0xA3B41A50,0x5842DD54,0xA34BDF20,0x57D5696D,0xA2E4249B,0x57677B9D, +0xA27CEB4F,0x56F9147E,0xA21633CD,0x568A34A9,0xA1AFFEA3,0x561ADCB9,0xA14A4C5E, +0x55AB0D46,0xA0E51D8C,0x553AC6EE,0xA08072BA,0x54CA0A4B,0xA01C4C73,0x5458D7F9, +0x9FB8AB41,0x53E73097,0x9F558FB0,0x537514C2,0x9EF2FA49,0x53028518,0x9E90EB94, +0x528F8238,0x9E2F641B,0x521C0CC2,0x9DCE6463,0x51A82555,0x9D6DECF4,0x5133CC94, +0x9D0DFE54,0x50BF031F,0x9CAE9907,0x5049C999,0x9C4FBD93,0x4FD420A4,0x9BF16C7A, +0x4F5E08E3,0x9B93A641,0x4EE782FB,0x9B366B68,0x4E708F8F,0x9AD9BC71,0x4DF92F46, +0x9A7D99DE,0x4D8162C4,0x9A22042D,0x4D092AB0,0x99C6FBDE,0x4C9087B1,0x996C816F, +0x4C177A6E,0x9912955F,0x4B9E0390,0x98B93828,0x4B2423BE,0x98606A49,0x4AA9DBA2, +0x98082C3B,0x4A2F2BE6,0x97B07E7A,0x49B41533,0x9759617F,0x49389836,0x9702D5C3, +0x48BCB599,0x96ACDBBE,0x48406E08,0x965773E7,0x47C3C22F,0x96029EB6,0x4746B2BC, +0x95AE5C9F,0x46C9405C,0x955AAE17,0x464B6BBE,0x95079394,0x45CD358F,0x94B50D87, +0x454E9E80,0x94631C65,0x44CFA740,0x9411C09E,0x4450507E,0x93C0FAA3,0x43D09AED, +0x9370CAE4,0x4350873C,0x932131D1,0x42D0161E,0x92D22FD9,0x424F4845,0x9283C568, +0x41CE1E65,0x9235F2EC,0x414C992F,0x91E8B8D0,0x40CAB958,0x919C1781,0x40487F94, +0x91500F67,0x3FC5EC98,0x9104A0EE,0x3F430119,0x90B9CC7D,0x3EBFBDCD,0x906F927C, +0x3E3C2369,0x9025F352,0x3DB832A6,0x8FDCEF66,0x3D33EC39,0x8F94871D,0x3CAF50DA, +0x8F4CBADB,0x3C2A6142,0x8F058B04,0x3BA51E29,0x8EBEF7FB,0x3B1F8848,0x8E790222, +0x3A99A057,0x8E33A9DA,0x3A136712,0x8DEEEF82,0x398CDD32,0x8DAAD37B,0x39060373, +0x8D675623,0x387EDA8E,0x8D2477D8,0x37F76341,0x8CE238F6,0x376F9E46,0x8CA099DA, +0x36E78C5B,0x8C5F9ADE,0x365F2E3B,0x8C1F3C5D,0x35D684A6,0x8BDF7EB0,0x354D9057, +0x8BA0622F,0x34C4520D,0x8B61E733,0x343ACA87,0x8B240E11,0x33B0FA84,0x8AE6D720, +0x3326E2C3,0x8AAA42B4,0x329C8402,0x8A6E5123,0x3211DF04,0x8A3302BE,0x3186F487, +0x89F857D8,0x30FBC54D,0x89BE50C3,0x30705217,0x8984EDCF,0x2FE49BA7,0x894C2F4C, +0x2F58A2BE,0x89141589,0x2ECC681E,0x88DCA0D3,0x2E3FEC8B,0x88A5D177,0x2DB330C7, +0x886FA7C2,0x2D263596,0x883A23FF,0x2C98FBBA,0x88054677,0x2C0B83FA,0x87D10F75, +0x2B7DCF17,0x879D7F41,0x2AEFDDD8,0x876A9621,0x2A61B101,0x8738545E,0x29D34958, +0x8706BA3D,0x2944A7A2,0x86D5C802,0x28B5CCA5,0x86A57DF2,0x2826B928,0x8675DC4F, +0x27976DF1,0x8646E35C,0x2707EBC7,0x86189359,0x26783370,0x85EAEC88,0x25E845B6, +0x85BDEF28,0x2558235F,0x85919B76,0x24C7CD33,0x8565F1B0,0x243743FA,0x853AF214, +0x23A6887F,0x85109CDD,0x23159B88,0x84E6F244,0x22847DE0,0x84BDF286,0x21F3304F, +0x84959DD9,0x2161B3A0,0x846DF477,0x20D0089C,0x8446F695,0x203E300D,0x8420A46C, +0x1FAC2ABF,0x83FAFE2E,0x1F19F97B,0x83D60412,0x1E879D0D,0x83B1B649,0x1DF5163F, +0x838E1507,0x1D6265DD,0x836B207D,0x1CCF8CB3,0x8348D8DC,0x1C3C8B8C,0x83273E52, +0x1BA96335,0x83065110,0x1B161479,0x82E61141,0x1A82A026,0x82C67F14,0x19EF0707, +0x82A79AB3,0x195B49EA,0x8289644B,0x18C7699B,0x826BDC04,0x183366E9,0x824F0208, +0x179F429F,0x8232D67F,0x170AFD8D,0x82175990,0x1676987F,0x81FC8B60,0x15E21445, +0x81E26C16,0x154D71AA,0x81C8FBD6,0x14B8B17F,0x81B03AC2,0x1423D492,0x819828FD, +0x138EDBB1,0x8180C6A9,0x12F9C7AA,0x816A13E6,0x1264994E,0x815410D4,0x11CF516A, +0x813EBD90,0x1139F0CF,0x812A1A3A,0x10A4784B,0x811626EC,0x100EE8AD,0x8102E3C4, +0x0F7942C7,0x80F050DB,0x0EE38766,0x80DE6E4C,0x0E4DB75B,0x80CD3C2F,0x0DB7D376, +0x80BCBA9D,0x0D21DC87,0x80ACE9AB,0x0C8BD35E,0x809DC971,0x0BF5B8CB,0x808F5A02, +0x0B5F8D9F,0x80819B74,0x0AC952AA,0x80748DD9,0x0A3308BD,0x80683143,0x099CB0A7, +0x805C85C4,0x09064B3A,0x80518B6B,0x086FD947,0x80474248,0x07D95B9E,0x803DAA6A, +0x0742D311,0x8034C3DD,0x06AC406F,0x802C8EAD,0x0615A48B,0x80250AE7,0x057F0035, +0x801E3895,0x04E8543E,0x801817BF,0x0451A177,0x8012A86F,0x03BAE8B2,0x800DEAAD, +0x03242ABF,0x8009DE7E,0x028D6870,0x800683E8,0x01F6A297,0x8003DAF1,0x015FDA03, +0x8001E39B,0x00C90F88,0x80009DEA,0x003243F5,0x800009DF,0xFF9B781D,0x8000277A, +0xFF04ACD0,0x8000F6BD,0xFE6DE2E0,0x800277A6,0xFDD71B1E,0x8004AA32,0xFD40565C, +0x80078E5E,0xFCA9956A,0x800B2427,0xFC12D91A,0x800F6B88,0xFB7C223D,0x8014647B, +0xFAE571A4,0x801A0EF8,0xFA4EC821,0x80206AF8,0xF9B82684,0x80277872,0xF9218D9E, +0x802F375D,0xF88AFE42,0x8037A7AC,0xF7F4793E,0x8040C956,0xF75DFF66,0x804A9C4D, +0xF6C79188,0x80552084,0xF6313077,0x806055EB,0xF59ADD02,0x806C3C74,0xF50497FB, +0x8078D40D,0xF46E6231,0x80861CA6,0xF3D83C77,0x8094162C,0xF342279B,0x80A2C08B, +0xF2AC246E,0x80B21BAF,0xF21633C0,0x80C22784,0xF1805662,0x80D2E3F2,0xF0EA8D24, +0x80E450E2,0xF054D8D5,0x80F66E3C,0xEFBF3A45,0x81093BE8,0xEF29B243,0x811CB9CA, +0xEE9441A0,0x8130E7C9,0xEDFEE92B,0x8145C5C7,0xED69A9B3,0x815B53A8,0xECD48407, +0x8171914E,0xEC3F78F6,0x81887E9A,0xEBAA894F,0x81A01B6D,0xEB15B5E1,0x81B867A5, +0xEA80FF7A,0x81D16321,0xE9EC66E8,0x81EB0DBE,0xE957ECFB,0x82056758,0xE8C39280, +0x82206FCC,0xE82F5844,0x823C26F3,0xE79B3F16,0x82588CA7,0xE70747C4,0x8275A0C0, +0xE6737319,0x82936317,0xE5DFC1E5,0x82B1D381,0xE54C34F3,0x82D0F1D5,0xE4B8CD11, +0x82F0BDE8,0xE4258B0A,0x8311378D,0xE3926FAD,0x83325E97,0xE2FF7BC3,0x835432D8, +0xE26CB01B,0x8376B422,0xE1DA0D7E,0x8399E244,0xE14794BA,0x83BDBD0E,0xE0B54698, +0x83E2444D,0xE02323E5,0x840777D0,0xDF912D6B,0x842D5762,0xDEFF63F4,0x8453E2CF, +0xDE6DC84B,0x847B19E1,0xDDDC5B3B,0x84A2FC62,0xDD4B1D8C,0x84CB8A1B,0xDCBA1008, +0x84F4C2D4,0xDC293379,0x851EA652,0xDB9888A8,0x8549345C,0xDB08105E,0x85746CB8, +0xDA77CB63,0x85A04F28,0xD9E7BA7F,0x85CCDB70,0xD957DE7A,0x85FA1153,0xD8C8381D, +0x8627F091,0xD838C82D,0x865678EB,0xD7A98F73,0x8685AA20,0xD71A8EB5,0x86B583EE, +0xD68BC6BA,0x86E60614,0xD5FD3848,0x8717304E,0xD56EE424,0x87490258,0xD4E0CB15, +0x877B7BEC,0xD452EDDF,0x87AE9CC5,0xD3C54D47,0x87E2649B,0xD337EA12,0x8816D327, +0xD2AAC504,0x884BE821,0xD21DDEE2,0x8881A33D,0xD191386E,0x88B80432,0xD104D26B, +0x88EF0AB4,0xD078AD9E,0x8926B677,0xCFECCAC7,0x895F072E,0xCF612AAA,0x8997FC8A, +0xCED5CE08,0x89D1963C,0xCE4AB5A2,0x8A0BD3F5,0xCDBFE23A,0x8A46B564,0xCD355491, +0x8A823A36,0xCCAB0D65,0x8ABE6219,0xCC210D79,0x8AFB2CBB,0xCB97558A,0x8B3899C6, +0xCB0DE658,0x8B76A8E4,0xCA84C0A3,0x8BB559C1,0xC9FBE527,0x8BF4AC05,0xC97354A4, +0x8C349F58,0xC8EB0FD6,0x8C753362,0xC863177B,0x8CB667C8,0xC7DB6C50,0x8CF83C30, +0xC7540F11,0x8D3AB03F,0xC6CD0079,0x8D7DC399,0xC6464144,0x8DC175E0,0xC5BFD22E, +0x8E05C6B7,0xC539B3F1,0x8E4AB5BF,0xC4B3E746,0x8E904298,0xC42E6CE8,0x8ED66CE1, +0xC3A94590,0x8F1D343A,0xC32471F7,0x8F649840,0xC29FF2D4,0x8FAC988F,0xC21BC8E1, +0x8FF534C4,0xC197F4D4,0x903E6C7B,0xC1147764,0x90883F4D,0xC0915148,0x90D2ACD4, +0xC00E8336,0x911DB4A9,0xBF8C0DE3,0x91695663,0xBF09F205,0x91B5919A,0xBE88304F, +0x920265E4,0xBE06C977,0x924FD2D7,0xBD85BE30,0x929DD806,0xBD050F2C,0x92EC7505, +0xBC84BD1F,0x933BA968,0xBC04C8BA,0x938B74C1,0xBB8532B0,0x93DBD6A0,0xBB05FBB0, +0x942CCE96,0xBA87246D,0x947E5C33,0xBA08AD95,0x94D07F05,0xB98A97D8,0x9523369C, +0xB90CE3E6,0x95768283,0xB88F926D,0x95CA6247,0xB812A41A,0x961ED574,0xB796199B, +0x9673DB94,0xB719F39E,0x96C97432,0xB69E32CD,0x971F9ED7,0xB622D7D6,0x97765B0A, +0xB5A7E362,0x97CDA855,0xB52D561E,0x9825863D,0xB4B330B3,0x987DF449,0xB43973CA, +0x98D6F1FE,0xB3C0200C,0x99307EE0,0xB3473623,0x998A9A74,0xB2CEB6B5,0x99E5443B, +0xB256A26A,0x9A407BB9,0xB1DEF9E9,0x9A9C406E,0xB167BDD7,0x9AF891DB,0xB0F0EEDA, +0x9B556F81,0xB07A8D97,0x9BB2D8DE,0xB0049AB3,0x9C10CD70,0xAF8F16D1,0x9C6F4CB6, +0xAF1A0293,0x9CCE562C,0xAEA55E9E,0x9D2DE94D,0xAE312B92,0x9D8E0597,0xADBD6A10, +0x9DEEAA82,0xAD4A1ABA,0x9E4FD78A,0xACD73E30,0x9EB18C26,0xAC64D510,0x9F13C7D0, +0xABF2DFFB,0x9F7689FF,0xAB815F8D,0x9FD9D22A,0xAB105464,0xA03D9FC8,0xAA9FBF1E, +0xA0A1F24D,0xAA2FA056,0xA106C92F,0xA9BFF8A8,0xA16C23E1,0xA950C8B0,0xA1D201D7, +0xA8E21106,0xA2386284,0xA873D246,0xA29F4559,0xA8060D08,0xA306A9C8,0xA798C1E5, +0xA36E8F41,0xA72BF174,0xA3D6F534,0xA6BF9C4B,0xA43FDB10,0xA653C303,0xA4A94043, +0xA5E8662F,0xA513243B,0xA57D8666,0xA57D8666,0xA513243B,0xA5E8662F,0xA4A94043, +0xA653C303,0xA43FDB10,0xA6BF9C4B,0xA3D6F534,0xA72BF174,0xA36E8F41,0xA798C1E5, +0xA306A9C8,0xA8060D08,0xA29F4559,0xA873D246,0xA2386284,0xA8E21106,0xA1D201D7, +0xA950C8B0,0xA16C23E1,0xA9BFF8A8,0xA106C92F,0xAA2FA056,0xA0A1F24D,0xAA9FBF1E, +0xA03D9FC8,0xAB105464,0x9FD9D22A,0xAB815F8D,0x9F7689FF,0xABF2DFFB,0x9F13C7D0, +0xAC64D510,0x9EB18C26,0xACD73E30,0x9E4FD78A,0xAD4A1ABA,0x9DEEAA82,0xADBD6A10, +0x9D8E0597,0xAE312B92,0x9D2DE94D,0xAEA55E9E,0x9CCE562C,0xAF1A0293,0x9C6F4CB6, +0xAF8F16D1,0x9C10CD70,0xB0049AB3,0x9BB2D8DE,0xB07A8D97,0x9B556F81,0xB0F0EEDA, +0x9AF891DB,0xB167BDD7,0x9A9C406E,0xB1DEF9E9,0x9A407BB9,0xB256A26A,0x99E5443B, +0xB2CEB6B5,0x998A9A74,0xB3473623,0x99307EE0,0xB3C0200C,0x98D6F1FE,0xB43973CA, +0x987DF449,0xB4B330B3,0x9825863D,0xB52D561E,0x97CDA855,0xB5A7E362,0x97765B0A, +0xB622D7D6,0x971F9ED7,0xB69E32CD,0x96C97432,0xB719F39E,0x9673DB94,0xB796199B, +0x961ED574,0xB812A41A,0x95CA6247,0xB88F926D,0x95768283,0xB90CE3E6,0x9523369C, +0xB98A97D8,0x94D07F05,0xBA08AD95,0x947E5C33,0xBA87246D,0x942CCE96,0xBB05FBB0, +0x93DBD6A0,0xBB8532B0,0x938B74C1,0xBC04C8BA,0x933BA968,0xBC84BD1F,0x92EC7505, +0xBD050F2C,0x929DD806,0xBD85BE30,0x924FD2D7,0xBE06C977,0x920265E4,0xBE88304F, +0x91B5919A,0xBF09F205,0x91695663,0xBF8C0DE3,0x911DB4A9,0xC00E8336,0x90D2ACD4, +0xC0915148,0x90883F4D,0xC1147764,0x903E6C7B,0xC197F4D4,0x8FF534C4,0xC21BC8E1, +0x8FAC988F,0xC29FF2D4,0x8F649840,0xC32471F7,0x8F1D343A,0xC3A94590,0x8ED66CE1, +0xC42E6CE8,0x8E904298,0xC4B3E746,0x8E4AB5BF,0xC539B3F1,0x8E05C6B7,0xC5BFD22E, +0x8DC175E0,0xC6464144,0x8D7DC399,0xC6CD0079,0x8D3AB03F,0xC7540F11,0x8CF83C30, +0xC7DB6C50,0x8CB667C8,0xC863177B,0x8C753362,0xC8EB0FD6,0x8C349F58,0xC97354A4, +0x8BF4AC05,0xC9FBE527,0x8BB559C1,0xCA84C0A3,0x8B76A8E4,0xCB0DE658,0x8B3899C6, +0xCB97558A,0x8AFB2CBB,0xCC210D79,0x8ABE6219,0xCCAB0D65,0x8A823A36,0xCD355491, +0x8A46B564,0xCDBFE23A,0x8A0BD3F5,0xCE4AB5A2,0x89D1963C,0xCED5CE08,0x8997FC8A, +0xCF612AAA,0x895F072E,0xCFECCAC7,0x8926B677,0xD078AD9E,0x88EF0AB4,0xD104D26B, +0x88B80432,0xD191386E,0x8881A33D,0xD21DDEE2,0x884BE821,0xD2AAC504,0x8816D327, +0xD337EA12,0x87E2649B,0xD3C54D47,0x87AE9CC5,0xD452EDDF,0x877B7BEC,0xD4E0CB15, +0x87490258,0xD56EE424,0x8717304E,0xD5FD3848,0x86E60614,0xD68BC6BA,0x86B583EE, +0xD71A8EB5,0x8685AA20,0xD7A98F73,0x865678EB,0xD838C82D,0x8627F091,0xD8C8381D, +0x85FA1153,0xD957DE7A,0x85CCDB70,0xD9E7BA7F,0x85A04F28,0xDA77CB63,0x85746CB8, +0xDB08105E,0x8549345C,0xDB9888A8,0x851EA652,0xDC293379,0x84F4C2D4,0xDCBA1008, +0x84CB8A1B,0xDD4B1D8C,0x84A2FC62,0xDDDC5B3B,0x847B19E1,0xDE6DC84B,0x8453E2CF, +0xDEFF63F4,0x842D5762,0xDF912D6B,0x840777D0,0xE02323E5,0x83E2444D,0xE0B54698, +0x83BDBD0E,0xE14794BA,0x8399E244,0xE1DA0D7E,0x8376B422,0xE26CB01B,0x835432D8, +0xE2FF7BC3,0x83325E97,0xE3926FAD,0x8311378D,0xE4258B0A,0x82F0BDE8,0xE4B8CD11, +0x82D0F1D5,0xE54C34F3,0x82B1D381,0xE5DFC1E5,0x82936317,0xE6737319,0x8275A0C0, +0xE70747C4,0x82588CA7,0xE79B3F16,0x823C26F3,0xE82F5844,0x82206FCC,0xE8C39280, +0x82056758,0xE957ECFB,0x81EB0DBE,0xE9EC66E8,0x81D16321,0xEA80FF7A,0x81B867A5, +0xEB15B5E1,0x81A01B6D,0xEBAA894F,0x81887E9A,0xEC3F78F6,0x8171914E,0xECD48407, +0x815B53A8,0xED69A9B3,0x8145C5C7,0xEDFEE92B,0x8130E7C9,0xEE9441A0,0x811CB9CA, +0xEF29B243,0x81093BE8,0xEFBF3A45,0x80F66E3C,0xF054D8D5,0x80E450E2,0xF0EA8D24, +0x80D2E3F2,0xF1805662,0x80C22784,0xF21633C0,0x80B21BAF,0xF2AC246E,0x80A2C08B, +0xF342279B,0x8094162C,0xF3D83C77,0x80861CA6,0xF46E6231,0x8078D40D,0xF50497FB, +0x806C3C74,0xF59ADD02,0x806055EB,0xF6313077,0x80552084,0xF6C79188,0x804A9C4D, +0xF75DFF66,0x8040C956,0xF7F4793E,0x8037A7AC,0xF88AFE42,0x802F375D,0xF9218D9E, +0x80277872,0xF9B82684,0x80206AF8,0xFA4EC821,0x801A0EF8,0xFAE571A4,0x8014647B, +0xFB7C223D,0x800F6B88,0xFC12D91A,0x800B2427,0xFCA9956A,0x80078E5E,0xFD40565C, +0x8004AA32,0xFDD71B1E,0x800277A6,0xFE6DE2E0,0x8000F6BD,0xFF04ACD0,0x8000277A, +0xFF9B781D,0x800009DF,0x003243F5,0x80009DEA,0x00C90F88,0x8001E39B,0x015FDA03, +0x8003DAF1,0x01F6A297,0x800683E8,0x028D6870,0x8009DE7E,0x03242ABF,0x800DEAAD, +0x03BAE8B2,0x8012A86F,0x0451A177,0x801817BF,0x04E8543E,0x801E3895,0x057F0035, +0x80250AE7,0x0615A48B,0x802C8EAD,0x06AC406F,0x8034C3DD,0x0742D311,0x803DAA6A, +0x07D95B9E,0x80474248,0x086FD947,0x80518B6B,0x09064B3A,0x805C85C4,0x099CB0A7, +0x80683143,0x0A3308BD,0x80748DD9,0x0AC952AA,0x80819B74,0x0B5F8D9F,0x808F5A02, +0x0BF5B8CB,0x809DC971,0x0C8BD35E,0x80ACE9AB,0x0D21DC87,0x80BCBA9D,0x0DB7D376, +0x80CD3C2F,0x0E4DB75B,0x80DE6E4C,0x0EE38766,0x80F050DB,0x0F7942C7,0x8102E3C4, +0x100EE8AD,0x811626EC,0x10A4784B,0x812A1A3A,0x1139F0CF,0x813EBD90,0x11CF516A, +0x815410D4,0x1264994E,0x816A13E6,0x12F9C7AA,0x8180C6A9,0x138EDBB1,0x819828FD, +0x1423D492,0x81B03AC2,0x14B8B17F,0x81C8FBD6,0x154D71AA,0x81E26C16,0x15E21445, +0x81FC8B60,0x1676987F,0x82175990,0x170AFD8D,0x8232D67F,0x179F429F,0x824F0208, +0x183366E9,0x826BDC04,0x18C7699B,0x8289644B,0x195B49EA,0x82A79AB3,0x19EF0707, +0x82C67F14,0x1A82A026,0x82E61141,0x1B161479,0x83065110,0x1BA96335,0x83273E52, +0x1C3C8B8C,0x8348D8DC,0x1CCF8CB3,0x836B207D,0x1D6265DD,0x838E1507,0x1DF5163F, +0x83B1B649,0x1E879D0D,0x83D60412,0x1F19F97B,0x83FAFE2E,0x1FAC2ABF,0x8420A46C, +0x203E300D,0x8446F695,0x20D0089C,0x846DF477,0x2161B3A0,0x84959DD9,0x21F3304F, +0x84BDF286,0x22847DE0,0x84E6F244,0x23159B88,0x85109CDD,0x23A6887F,0x853AF214, +0x243743FA,0x8565F1B0,0x24C7CD33,0x85919B76,0x2558235F,0x85BDEF28,0x25E845B6, +0x85EAEC88,0x26783370,0x86189359,0x2707EBC7,0x8646E35C,0x27976DF1,0x8675DC4F, +0x2826B928,0x86A57DF2,0x28B5CCA5,0x86D5C802,0x2944A7A2,0x8706BA3D,0x29D34958, +0x8738545E,0x2A61B101,0x876A9621,0x2AEFDDD8,0x879D7F41,0x2B7DCF17,0x87D10F75, +0x2C0B83FA,0x88054677,0x2C98FBBA,0x883A23FF,0x2D263596,0x886FA7C2,0x2DB330C7, +0x88A5D177,0x2E3FEC8B,0x88DCA0D3,0x2ECC681E,0x89141589,0x2F58A2BE,0x894C2F4C, +0x2FE49BA7,0x8984EDCF,0x30705217,0x89BE50C3,0x30FBC54D,0x89F857D8,0x3186F487, +0x8A3302BE,0x3211DF04,0x8A6E5123,0x329C8402,0x8AAA42B4,0x3326E2C3,0x8AE6D720, +0x33B0FA84,0x8B240E11,0x343ACA87,0x8B61E733,0x34C4520D,0x8BA0622F,0x354D9057, +0x8BDF7EB0,0x35D684A6,0x8C1F3C5D,0x365F2E3B,0x8C5F9ADE,0x36E78C5B,0x8CA099DA, +0x376F9E46,0x8CE238F6,0x37F76341,0x8D2477D8,0x387EDA8E,0x8D675623,0x39060373, +0x8DAAD37B,0x398CDD32,0x8DEEEF82,0x3A136712,0x8E33A9DA,0x3A99A057,0x8E790222, +0x3B1F8848,0x8EBEF7FB,0x3BA51E29,0x8F058B04,0x3C2A6142,0x8F4CBADB,0x3CAF50DA, +0x8F94871D,0x3D33EC39,0x8FDCEF66,0x3DB832A6,0x9025F352,0x3E3C2369,0x906F927C, +0x3EBFBDCD,0x90B9CC7D,0x3F430119,0x9104A0EE,0x3FC5EC98,0x91500F67,0x40487F94, +0x919C1781,0x40CAB958,0x91E8B8D0,0x414C992F,0x9235F2EC,0x41CE1E65,0x9283C568, +0x424F4845,0x92D22FD9,0x42D0161E,0x932131D1,0x4350873C,0x9370CAE4,0x43D09AED, +0x93C0FAA3,0x4450507E,0x9411C09E,0x44CFA740,0x94631C65,0x454E9E80,0x94B50D87, +0x45CD358F,0x95079394,0x464B6BBE,0x955AAE17,0x46C9405C,0x95AE5C9F,0x4746B2BC, +0x96029EB6,0x47C3C22F,0x965773E7,0x48406E08,0x96ACDBBE,0x48BCB599,0x9702D5C3, +0x49389836,0x9759617F,0x49B41533,0x97B07E7A,0x4A2F2BE6,0x98082C3B,0x4AA9DBA2, +0x98606A49,0x4B2423BE,0x98B93828,0x4B9E0390,0x9912955F,0x4C177A6E,0x996C816F, +0x4C9087B1,0x99C6FBDE,0x4D092AB0,0x9A22042D,0x4D8162C4,0x9A7D99DE,0x4DF92F46, +0x9AD9BC71,0x4E708F8F,0x9B366B68,0x4EE782FB,0x9B93A641,0x4F5E08E3,0x9BF16C7A, +0x4FD420A4,0x9C4FBD93,0x5049C999,0x9CAE9907,0x50BF031F,0x9D0DFE54,0x5133CC94, +0x9D6DECF4,0x51A82555,0x9DCE6463,0x521C0CC2,0x9E2F641B,0x528F8238,0x9E90EB94, +0x53028518,0x9EF2FA49,0x537514C2,0x9F558FB0,0x53E73097,0x9FB8AB41,0x5458D7F9, +0xA01C4C73,0x54CA0A4B,0xA08072BA,0x553AC6EE,0xA0E51D8C,0x55AB0D46,0xA14A4C5E, +0x561ADCB9,0xA1AFFEA3,0x568A34A9,0xA21633CD,0x56F9147E,0xA27CEB4F,0x57677B9D, +0xA2E4249B,0x57D5696D,0xA34BDF20,0x5842DD54,0xA3B41A50,0x58AFD6BD,0xA41CD599, +0x591C550E,0xA486106A,0x598857B2,0xA4EFCA31,0x59F3DE12,0xA55A025B,0x5A5EE79A, +0xA5C4B855,0x5AC973B5,0xA62FEB8B,0x5B3381CE,0xA69B9B68,0x5B9D1154,0xA707C757, +0x5C0621B2,0xA7746EC0,0x5C6EB258,0xA7E1910F,0x5CD6C2B5,0xA84F2DAA,0x5D3E5237, +0xA8BD43FA,0x5DA5604F,0xA92BD367,0x5E0BEC6E,0xA99ADB56,0x5E71F606,0xAA0A5B2E, +0x5ED77C8A,0xAA7A5253,0x5F3C7F6B,0xAAEAC02C,0x5FA0FE1F,0xAB5BA41A,0x6004F819, +0xABCCFD83,0x60686CCF,0xAC3ECBC7,0x60CB5BB7,0xACB10E4B,0x612DC447,0xAD23C46E, +0x618FA5F7,0xAD96ED92,0x61F1003F,0xAE0A8916,0x6251D298,0xAE7E965B,0x62B21C7B, +0xAEF314C0,0x6311DD64,0xAF6803A2,0x637114CC,0xAFDD625F,0x63CFC231,0xB0533055, +0x642DE50D,0xB0C96CE0,0x648B7CE0,0xB140175B,0x64E88926,0xB1B72F23,0x6545095F, +0xB22EB392,0x65A0FD0B,0xB2A6A402,0x65FC63A9,0xB31EFFCC,0x66573CBB,0xB397C649, +0x66B187C3,0xB410F6D3,0x670B4444,0xB48A90C0,0x676471C0,0xB5049368,0x67BD0FBD, +0xB57EFE22,0x68151DBE,0xB5F9D043,0x686C9B4B,0xB6750921,0x68C387E9,0xB6F0A812, +0x6919E320,0xB76CAC69,0x696FAC78,0xB7E9157A,0x69C4E37A,0xB865E299,0x6A1987B0, +0xB8E31319,0x6A6D98A4,0xB960A64C,0x6AC115E2,0xB9DE9B83,0x6B13FEF5,0xBA5CF210, +0x6B66536B,0xBADBA943,0x6BB812D1,0xBB5AC06D,0x6C093CB6,0xBBDA36DD,0x6C59D0A9, +0xBC5A0BE2,0x6CA9CE3B,0xBCDA3ECB,0x6CF934FC,0xBD5ACEE5,0x6D48047E,0xBDDBBB7F, +0x6D963C54,0xBE5D03E6,0x6DE3DC11,0xBEDEA765,0x6E30E34A,0xBF60A54A,0x6E7D5193, +0xBFE2FCDF,0x6EC92683,0xC065AD70,0x6F1461B0,0xC0E8B648,0x6F5F02B2,0xC16C16B0, +0x6FA90921,0xC1EFCDF3,0x6FF27497,0xC273DB58,0x703B44AD,0xC2F83E2A,0x708378FF, +0xC37CF5B0,0x70CB1128,0xC4020133,0x71120CC5,0xC4875FF9,0x71586B74,0xC50D1149, +0x719E2CD2,0xC593146A,0x71E35080,0xC61968A2,0x7227D61C,0xC6A00D37,0x726BBD48, +0xC727016D,0x72AF05A7,0xC7AE4489,0x72F1AED9,0xC835D5D0,0x7333B883,0xC8BDB485, +0x73752249,0xC945DFEC,0x73B5EBD1,0xC9CE5748,0x73F614C0,0xCA5719DB,0x74359CBD, +0xCAE026E8,0x74748371,0xCB697DB0,0x74B2C884,0xCBF31D75,0x74F06B9E,0xCC7D0578, +0x752D6C6C,0xCD0734F9,0x7569CA99,0xCD91AB39,0x75A585CF,0xCE1C6777,0x75E09DBD, +0xCEA768F2,0x761B1211,0xCF32AEEB,0x7654E279,0xCFBE389F,0x768E0EA6,0xD04A054E, +0x76C69647,0xD0D61434,0x76FE790E,0xD1626490,0x7735B6AF,0xD1EEF59E,0x776C4EDB, +0xD27BC69C,0x77A24148,0xD308D6C7,0x77D78DAA,0xD396255A,0x780C33B8,0xD423B191, +0x78403329,0xD4B17AA8,0x78738BB3,0xD53F7FDA,0x78A63D11,0xD5CDC062,0x78D846FB, +0xD65C3B7B,0x7909A92D,0xD6EAF05F,0x793A6361,0xD779DE47,0x796A7554,0xD809046E, +0x7999DEC4,0xD898620C,0x79C89F6E,0xD927F65B,0x79F6B711,0xD9B7C094,0x7A24256F, +0xDA47BFEE,0x7A50EA47,0xDAD7F3A2,0x7A7D055B,0xDB685AE9,0x7AA8766F,0xDBF8F4F8, +0x7AD33D45,0xDC89C109,0x7AFD59A4,0xDD1ABE51,0x7B26CB4F,0xDDABEC08,0x7B4F920E, +0xDE3D4964,0x7B77ADA8,0xDECED59B,0x7B9F1DE6,0xDF608FE4,0x7BC5E290,0xDFF27773, +0x7BEBFB70,0xE0848B7F,0x7C116853,0xE116CB3D,0x7C362904,0xE1A935E2,0x7C5A3D50, +0xE23BCAA2,0x7C7DA505,0xE2CE88B3,0x7CA05FF1,0xE3616F48,0x7CC26DE5,0xE3F47D96, +0x7CE3CEB2,0xE487B2D0,0x7D048228,0xE51B0E2A,0x7D24881B,0xE5AE8ED8,0x7D43E05E, +0xE642340D,0x7D628AC6,0xE6D5FCFC,0x7D808728,0xE769E8D8,0x7D9DD55A,0xE7FDF6D4, +0x7DBA7534,0xE8922622,0x7DD6668F,0xE92675F4,0x7DF1A942,0xE9BAE57D,0x7E0C3D29, +0xEA4F73EE,0x7E26221F,0xEAE4207A,0x7E3F57FF,0xEB78EA52,0x7E57DEA7,0xEC0DD0A8, +0x7E6FB5F4,0xECA2D2AD,0x7E86DDC6,0xED37EF91,0x7E9D55FC,0xEDCD2687,0x7EB31E78, +0xEE6276BF,0x7EC8371A,0xEEF7DF6A,0x7EDC9FC6,0xEF8D5FB8,0x7EF05860,0xF022F6DA, +0x7F0360CB,0xF0B8A401,0x7F15B8EE,0xF14E665C,0x7F2760AF,0xF1E43D1C,0x7F3857F6, +0xF27A2771,0x7F489EAA,0xF310248A,0x7F5834B7,0xF3A63398,0x7F671A05,0xF43C53CB, +0x7F754E80,0xF4D28451,0x7F82D214,0xF568C45B,0x7F8FA4B0,0xF5FF1318,0x7F9BC640, +0xF6956FB7,0x7FA736B4,0xF72BD967,0x7FB1F5FC,0xF7C24F59,0x7FBC040A,0xF858D0BB, +0x7FC560CF,0xF8EF5CBB,0x7FCE0C3E,0xF985F28A,0x7FD6064C,0xFA1C9157,0x7FDD4EEC, +0xFAB3384F,0x7FE3E616,0xFB49E6A3,0x7FE9CBC0,0xFBE09B80,0x7FEEFFE1,0xFC775616, +0x7FF38274,0xFD0E1594,0x7FF75370,0xFDA4D929,0x7FFA72D1,0xFE3BA002,0x7FFCE093, +0xFED2694F,0x7FFE9CB2,0xFF69343F,0x7FFFA72C,0x7FFFFFFF,0x00000000,0x7FFA72D1, +0xFDA4D929,0x7FE9CBC0,0xFB49E6A3,0x7FCE0C3E,0xF8EF5CBB,0x7FA736B4,0xF6956FB7, +0x7F754E80,0xF43C53CB,0x7F3857F6,0xF1E43D1C,0x7EF05860,0xEF8D5FB8,0x7E9D55FC, +0xED37EF91,0x7E3F57FF,0xEAE4207A,0x7DD6668F,0xE8922622,0x7D628AC6,0xE642340D, +0x7CE3CEB2,0xE3F47D96,0x7C5A3D50,0xE1A935E2,0x7BC5E290,0xDF608FE4,0x7B26CB4F, +0xDD1ABE51,0x7A7D055B,0xDAD7F3A2,0x79C89F6E,0xD898620C,0x7909A92D,0xD65C3B7B, +0x78403329,0xD423B191,0x776C4EDB,0xD1EEF59E,0x768E0EA6,0xCFBE389F,0x75A585CF, +0xCD91AB39,0x74B2C884,0xCB697DB0,0x73B5EBD1,0xC945DFEC,0x72AF05A7,0xC727016D, +0x719E2CD2,0xC50D1149,0x708378FF,0xC2F83E2A,0x6F5F02B2,0xC0E8B648,0x6E30E34A, +0xBEDEA765,0x6CF934FC,0xBCDA3ECB,0x6BB812D1,0xBADBA943,0x6A6D98A4,0xB8E31319, +0x6919E320,0xB6F0A812,0x67BD0FBD,0xB5049368,0x66573CBB,0xB31EFFCC,0x64E88926, +0xB140175B,0x637114CC,0xAF6803A2,0x61F1003F,0xAD96ED92,0x60686CCF,0xABCCFD83, +0x5ED77C8A,0xAA0A5B2E,0x5D3E5237,0xA84F2DAA,0x5B9D1154,0xA69B9B68,0x59F3DE12, +0xA4EFCA31,0x5842DD54,0xA34BDF20,0x568A34A9,0xA1AFFEA3,0x54CA0A4B,0xA01C4C73, +0x53028518,0x9E90EB94,0x5133CC94,0x9D0DFE54,0x4F5E08E3,0x9B93A641,0x4D8162C4, +0x9A22042D,0x4B9E0390,0x98B93828,0x49B41533,0x9759617F,0x47C3C22F,0x96029EB6, +0x45CD358F,0x94B50D87,0x43D09AED,0x9370CAE4,0x41CE1E65,0x9235F2EC,0x3FC5EC98, +0x9104A0EE,0x3DB832A6,0x8FDCEF66,0x3BA51E29,0x8EBEF7FB,0x398CDD32,0x8DAAD37B, +0x376F9E46,0x8CA099DA,0x354D9057,0x8BA0622F,0x3326E2C3,0x8AAA42B4,0x30FBC54D, +0x89BE50C3,0x2ECC681E,0x88DCA0D3,0x2C98FBBA,0x88054677,0x2A61B101,0x8738545E, +0x2826B928,0x8675DC4F,0x25E845B6,0x85BDEF28,0x23A6887F,0x85109CDD,0x2161B3A0, +0x846DF477,0x1F19F97B,0x83D60412,0x1CCF8CB3,0x8348D8DC,0x1A82A026,0x82C67F14, +0x183366E9,0x824F0208,0x15E21445,0x81E26C16,0x138EDBB1,0x8180C6A9,0x1139F0CF, +0x812A1A3A,0x0EE38766,0x80DE6E4C,0x0C8BD35E,0x809DC971,0x0A3308BD,0x80683143, +0x07D95B9E,0x803DAA6A,0x057F0035,0x801E3895,0x03242ABF,0x8009DE7E,0x00C90F88, +0x80009DEA,0xFE6DE2E0,0x800277A6,0xFC12D91A,0x800F6B88,0xF9B82684,0x80277872, +0xF75DFF66,0x804A9C4D,0xF50497FB,0x8078D40D,0xF2AC246E,0x80B21BAF,0xF054D8D5, +0x80F66E3C,0xEDFEE92B,0x8145C5C7,0xEBAA894F,0x81A01B6D,0xE957ECFB,0x82056758, +0xE70747C4,0x8275A0C0,0xE4B8CD11,0x82F0BDE8,0xE26CB01B,0x8376B422,0xE02323E5, +0x840777D0,0xDDDC5B3B,0x84A2FC62,0xDB9888A8,0x8549345C,0xD957DE7A,0x85FA1153, +0xD71A8EB5,0x86B583EE,0xD4E0CB15,0x877B7BEC,0xD2AAC504,0x884BE821,0xD078AD9E, +0x8926B677,0xCE4AB5A2,0x8A0BD3F5,0xCC210D79,0x8AFB2CBB,0xC9FBE527,0x8BF4AC05, +0xC7DB6C50,0x8CF83C30,0xC5BFD22E,0x8E05C6B7,0xC3A94590,0x8F1D343A,0xC197F4D4, +0x903E6C7B,0xBF8C0DE3,0x91695663,0xBD85BE30,0x929DD806,0xBB8532B0,0x93DBD6A0, +0xB98A97D8,0x9523369C,0xB796199B,0x9673DB94,0xB5A7E362,0x97CDA855,0xB3C0200C, +0x99307EE0,0xB1DEF9E9,0x9A9C406E,0xB0049AB3,0x9C10CD70,0xAE312B92,0x9D8E0597, +0xAC64D510,0x9F13C7D0,0xAA9FBF1E,0xA0A1F24D,0xA8E21106,0xA2386284,0xA72BF174, +0xA3D6F534,0xA57D8666,0xA57D8666,0xA3D6F534,0xA72BF174,0xA2386284,0xA8E21106, +0xA0A1F24D,0xAA9FBF1E,0x9F13C7D0,0xAC64D510,0x9D8E0597,0xAE312B92,0x9C10CD70, +0xB0049AB3,0x9A9C406E,0xB1DEF9E9,0x99307EE0,0xB3C0200C,0x97CDA855,0xB5A7E362, +0x9673DB94,0xB796199B,0x9523369C,0xB98A97D8,0x93DBD6A0,0xBB8532B0,0x929DD806, +0xBD85BE30,0x91695663,0xBF8C0DE3,0x903E6C7B,0xC197F4D4,0x8F1D343A,0xC3A94590, +0x8E05C6B7,0xC5BFD22E,0x8CF83C30,0xC7DB6C50,0x8BF4AC05,0xC9FBE527,0x8AFB2CBB, +0xCC210D79,0x8A0BD3F5,0xCE4AB5A2,0x8926B677,0xD078AD9E,0x884BE821,0xD2AAC504, +0x877B7BEC,0xD4E0CB15,0x86B583EE,0xD71A8EB5,0x85FA1153,0xD957DE7A,0x8549345C, +0xDB9888A8,0x84A2FC62,0xDDDC5B3B,0x840777D0,0xE02323E5,0x8376B422,0xE26CB01B, +0x82F0BDE8,0xE4B8CD11,0x8275A0C0,0xE70747C4,0x82056758,0xE957ECFB,0x81A01B6D, +0xEBAA894F,0x8145C5C7,0xEDFEE92B,0x80F66E3C,0xF054D8D5,0x80B21BAF,0xF2AC246E, +0x8078D40D,0xF50497FB,0x804A9C4D,0xF75DFF66,0x80277872,0xF9B82684,0x800F6B88, +0xFC12D91A,0x800277A6,0xFE6DE2E0,0x80009DEA,0x00C90F88,0x8009DE7E,0x03242ABF, +0x801E3895,0x057F0035,0x803DAA6A,0x07D95B9E,0x80683143,0x0A3308BD,0x809DC971, +0x0C8BD35E,0x80DE6E4C,0x0EE38766,0x812A1A3A,0x1139F0CF,0x8180C6A9,0x138EDBB1, +0x81E26C16,0x15E21445,0x824F0208,0x183366E9,0x82C67F14,0x1A82A026,0x8348D8DC, +0x1CCF8CB3,0x83D60412,0x1F19F97B,0x846DF477,0x2161B3A0,0x85109CDD,0x23A6887F, +0x85BDEF28,0x25E845B6,0x8675DC4F,0x2826B928,0x8738545E,0x2A61B101,0x88054677, +0x2C98FBBA,0x88DCA0D3,0x2ECC681E,0x89BE50C3,0x30FBC54D,0x8AAA42B4,0x3326E2C3, +0x8BA0622F,0x354D9057,0x8CA099DA,0x376F9E46,0x8DAAD37B,0x398CDD32,0x8EBEF7FB, +0x3BA51E29,0x8FDCEF66,0x3DB832A6,0x9104A0EE,0x3FC5EC98,0x9235F2EC,0x41CE1E65, +0x9370CAE4,0x43D09AED,0x94B50D87,0x45CD358F,0x96029EB6,0x47C3C22F,0x9759617F, +0x49B41533,0x98B93828,0x4B9E0390,0x9A22042D,0x4D8162C4,0x9B93A641,0x4F5E08E3, +0x9D0DFE54,0x5133CC94,0x9E90EB94,0x53028518,0xA01C4C73,0x54CA0A4B,0xA1AFFEA3, +0x568A34A9,0xA34BDF20,0x5842DD54,0xA4EFCA31,0x59F3DE12,0xA69B9B68,0x5B9D1154, +0xA84F2DAA,0x5D3E5237,0xAA0A5B2E,0x5ED77C8A,0xABCCFD83,0x60686CCF,0xAD96ED92, +0x61F1003F,0xAF6803A2,0x637114CC,0xB140175B,0x64E88926,0xB31EFFCC,0x66573CBB, +0xB5049368,0x67BD0FBD,0xB6F0A812,0x6919E320,0xB8E31319,0x6A6D98A4,0xBADBA943, +0x6BB812D1,0xBCDA3ECB,0x6CF934FC,0xBEDEA765,0x6E30E34A,0xC0E8B648,0x6F5F02B2, +0xC2F83E2A,0x708378FF,0xC50D1149,0x719E2CD2,0xC727016D,0x72AF05A7,0xC945DFEC, +0x73B5EBD1,0xCB697DB0,0x74B2C884,0xCD91AB39,0x75A585CF,0xCFBE389F,0x768E0EA6, +0xD1EEF59E,0x776C4EDB,0xD423B191,0x78403329,0xD65C3B7B,0x7909A92D,0xD898620C, +0x79C89F6E,0xDAD7F3A2,0x7A7D055B,0xDD1ABE51,0x7B26CB4F,0xDF608FE4,0x7BC5E290, +0xE1A935E2,0x7C5A3D50,0xE3F47D96,0x7CE3CEB2,0xE642340D,0x7D628AC6,0xE8922622, +0x7DD6668F,0xEAE4207A,0x7E3F57FF,0xED37EF91,0x7E9D55FC,0xEF8D5FB8,0x7EF05860, +0xF1E43D1C,0x7F3857F6,0xF43C53CB,0x7F754E80,0xF6956FB7,0x7FA736B4,0xF8EF5CBB, +0x7FCE0C3E,0xFB49E6A3,0x7FE9CBC0,0xFDA4D929,0x7FFA72D1,0x7FFFFFFF,0x00000000, +0x7FA736B4,0xF6956FB7,0x7E9D55FC,0xED37EF91,0x7CE3CEB2,0xE3F47D96,0x7A7D055B, +0xDAD7F3A2,0x776C4EDB,0xD1EEF59E,0x73B5EBD1,0xC945DFEC,0x6F5F02B2,0xC0E8B648, +0x6A6D98A4,0xB8E31319,0x64E88926,0xB140175B,0x5ED77C8A,0xAA0A5B2E,0x5842DD54, +0xA34BDF20,0x5133CC94,0x9D0DFE54,0x49B41533,0x9759617F,0x41CE1E65,0x9235F2EC, +0x398CDD32,0x8DAAD37B,0x30FBC54D,0x89BE50C3,0x2826B928,0x8675DC4F,0x1F19F97B, +0x83D60412,0x15E21445,0x81E26C16,0x0C8BD35E,0x809DC971,0x03242ABF,0x8009DE7E, +0xF9B82684,0x80277872,0xF054D8D5,0x80F66E3C,0xE70747C4,0x8275A0C0,0xDDDC5B3B, +0x84A2FC62,0xD4E0CB15,0x877B7BEC,0xCC210D79,0x8AFB2CBB,0xC3A94590,0x8F1D343A, +0xBB8532B0,0x93DBD6A0,0xB3C0200C,0x99307EE0,0xAC64D510,0x9F13C7D0,0xA57D8666, +0xA57D8666,0x9F13C7D0,0xAC64D510,0x99307EE0,0xB3C0200C,0x93DBD6A0,0xBB8532B0, +0x8F1D343A,0xC3A94590,0x8AFB2CBB,0xCC210D79,0x877B7BEC,0xD4E0CB15,0x84A2FC62, +0xDDDC5B3B,0x8275A0C0,0xE70747C4,0x80F66E3C,0xF054D8D5,0x80277872,0xF9B82684, +0x8009DE7E,0x03242ABF,0x809DC971,0x0C8BD35E,0x81E26C16,0x15E21445,0x83D60412, +0x1F19F97B,0x8675DC4F,0x2826B928,0x89BE50C3,0x30FBC54D,0x8DAAD37B,0x398CDD32, +0x9235F2EC,0x41CE1E65,0x9759617F,0x49B41533,0x9D0DFE54,0x5133CC94,0xA34BDF20, +0x5842DD54,0xAA0A5B2E,0x5ED77C8A,0xB140175B,0x64E88926,0xB8E31319,0x6A6D98A4, +0xC0E8B648,0x6F5F02B2,0xC945DFEC,0x73B5EBD1,0xD1EEF59E,0x776C4EDB,0xDAD7F3A2, +0x7A7D055B,0xE3F47D96,0x7CE3CEB2,0xED37EF91,0x7E9D55FC,0xF6956FB7,0x7FA736B4, +0x7FFFFFFF,0x00000000,0x7A7D055B,0xDAD7F3A2,0x6A6D98A4,0xB8E31319,0x5133CC94, +0x9D0DFE54,0x30FBC54D,0x89BE50C3,0x0C8BD35E,0x809DC971,0xE70747C4,0x8275A0C0, +0xC3A94590,0x8F1D343A,0xA57D8666,0xA57D8666,0x8F1D343A,0xC3A94590,0x8275A0C0, +0xE70747C4,0x809DC971,0x0C8BD35E,0x89BE50C3,0x30FBC54D,0x9D0DFE54,0x5133CC94, +0xB8E31319,0x6A6D98A4,0xDAD7F3A2,0x7A7D055B,0x7FFFFFFF,0x00000000,0x30FBC54D, +0x89BE50C3,0xA57D8666,0xA57D8666,0x89BE50C3,0x30FBC54D,}; + +#endif + + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ +#endif /* defined(ARM_MATH_MVEI) */ + + + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) + +uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2]={ +0,0,}; + +q15_t rearranged_twiddle_stride1_16_q15[8]={ +0x7FFF,0x0000,0x7642,0xCF04,0x5A82,0xA57E,0x30FC,0x89BE,}; + +q15_t rearranged_twiddle_stride2_16_q15[8]={ +0x7FFF,0x0000,0x5A82,0xA57E,0x0000,0x8000,0xA57E,0xA57E,}; + +q15_t rearranged_twiddle_stride3_16_q15[8]={ +0x7FFF,0x0000,0x30FC,0x89BE,0xA57E,0xA57E,0x89BE,0x30FC,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) + +uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3]={ +0,32,0,}; + +q15_t rearranged_twiddle_stride1_64_q15[40]={ +0x7FFF,0x0000,0x7F62,0xF374,0x7D8A,0xE707,0x7A7D,0xDAD8,0x7642,0xCF04,0x70E3, +0xC3A9,0x6A6E,0xB8E3,0x62F2,0xAECC,0x5A82,0xA57E,0x5134,0x9D0E,0x471D,0x9592, +0x3C57,0x8F1D,0x30FC,0x89BE,0x2528,0x8583,0x18F9,0x8276,0x0C8C,0x809E,0x7FFF, +0x0000,0x7642,0xCF04,0x5A82,0xA57E,0x30FC,0x89BE,}; + +q15_t rearranged_twiddle_stride2_64_q15[40]={ +0x7FFF,0x0000,0x7D8A,0xE707,0x7642,0xCF04,0x6A6E,0xB8E3,0x5A82,0xA57E,0x471D, +0x9592,0x30FC,0x89BE,0x18F9,0x8276,0x0000,0x8000,0xE707,0x8276,0xCF04,0x89BE, +0xB8E3,0x9592,0xA57E,0xA57E,0x9592,0xB8E3,0x89BE,0xCF04,0x8276,0xE707,0x7FFF, +0x0000,0x5A82,0xA57E,0x0000,0x8000,0xA57E,0xA57E,}; + +q15_t rearranged_twiddle_stride3_64_q15[40]={ +0x7FFF,0x0000,0x7A7D,0xDAD8,0x6A6E,0xB8E3,0x5134,0x9D0E,0x30FC,0x89BE,0x0C8C, +0x809E,0xE707,0x8276,0xC3A9,0x8F1D,0xA57E,0xA57E,0x8F1D,0xC3A9,0x8276,0xE707, +0x809E,0x0C8C,0x89BE,0x30FC,0x9D0E,0x5134,0xB8E3,0x6A6E,0xDAD8,0x7A7D,0x7FFF, +0x0000,0x30FC,0x89BE,0xA57E,0xA57E,0x89BE,0x30FC,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) + +uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4]={ +0,128,160,0,}; + +q15_t rearranged_twiddle_stride1_256_q15[168]={ +0x7FFF,0x0000,0x7FF6,0xFCDC,0x7FD9,0xF9B8,0x7FA7,0xF695,0x7F62,0xF374,0x7F0A, +0xF055,0x7E9D,0xED38,0x7E1E,0xEA1E,0x7D8A,0xE707,0x7CE4,0xE3F4,0x7C2A,0xE0E6, +0x7B5D,0xDDDC,0x7A7D,0xDAD8,0x798A,0xD7D9,0x7885,0xD4E1,0x776C,0xD1EF,0x7642, +0xCF04,0x7505,0xCC21,0x73B6,0xC946,0x7255,0xC673,0x70E3,0xC3A9,0x6F5F,0xC0E9, +0x6DCA,0xBE32,0x6C24,0xBB85,0x6A6E,0xB8E3,0x68A7,0xB64C,0x66D0,0xB3C0,0x64E9, +0xB140,0x62F2,0xAECC,0x60EC,0xAC65,0x5ED7,0xAA0A,0x5CB4,0xA7BD,0x5A82,0xA57E, +0x5843,0xA34C,0x55F6,0xA129,0x539B,0x9F14,0x5134,0x9D0E,0x4EC0,0x9B17,0x4C40, +0x9930,0x49B4,0x9759,0x471D,0x9592,0x447B,0x93DC,0x41CE,0x9236,0x3F17,0x90A1, +0x3C57,0x8F1D,0x398D,0x8DAB,0x36BA,0x8C4A,0x33DF,0x8AFB,0x30FC,0x89BE,0x2E11, +0x8894,0x2B1F,0x877B,0x2827,0x8676,0x2528,0x8583,0x2224,0x84A3,0x1F1A,0x83D6, +0x1C0C,0x831C,0x18F9,0x8276,0x15E2,0x81E2,0x12C8,0x8163,0x0FAB,0x80F6,0x0C8C, +0x809E,0x096B,0x8059,0x0648,0x8027,0x0324,0x800A,0x7FFF,0x0000,0x7F62,0xF374, +0x7D8A,0xE707,0x7A7D,0xDAD8,0x7642,0xCF04,0x70E3,0xC3A9,0x6A6E,0xB8E3,0x62F2, +0xAECC,0x5A82,0xA57E,0x5134,0x9D0E,0x471D,0x9592,0x3C57,0x8F1D,0x30FC,0x89BE, +0x2528,0x8583,0x18F9,0x8276,0x0C8C,0x809E,0x7FFF,0x0000,0x7642,0xCF04,0x5A82, +0xA57E,0x30FC,0x89BE,}; + +q15_t rearranged_twiddle_stride2_256_q15[168]={ +0x7FFF,0x0000,0x7FD9,0xF9B8,0x7F62,0xF374,0x7E9D,0xED38,0x7D8A,0xE707,0x7C2A, +0xE0E6,0x7A7D,0xDAD8,0x7885,0xD4E1,0x7642,0xCF04,0x73B6,0xC946,0x70E3,0xC3A9, +0x6DCA,0xBE32,0x6A6E,0xB8E3,0x66D0,0xB3C0,0x62F2,0xAECC,0x5ED7,0xAA0A,0x5A82, +0xA57E,0x55F6,0xA129,0x5134,0x9D0E,0x4C40,0x9930,0x471D,0x9592,0x41CE,0x9236, +0x3C57,0x8F1D,0x36BA,0x8C4A,0x30FC,0x89BE,0x2B1F,0x877B,0x2528,0x8583,0x1F1A, +0x83D6,0x18F9,0x8276,0x12C8,0x8163,0x0C8C,0x809E,0x0648,0x8027,0x0000,0x8000, +0xF9B8,0x8027,0xF374,0x809E,0xED38,0x8163,0xE707,0x8276,0xE0E6,0x83D6,0xDAD8, +0x8583,0xD4E1,0x877B,0xCF04,0x89BE,0xC946,0x8C4A,0xC3A9,0x8F1D,0xBE32,0x9236, +0xB8E3,0x9592,0xB3C0,0x9930,0xAECC,0x9D0E,0xAA0A,0xA129,0xA57E,0xA57E,0xA129, +0xAA0A,0x9D0E,0xAECC,0x9930,0xB3C0,0x9592,0xB8E3,0x9236,0xBE32,0x8F1D,0xC3A9, +0x8C4A,0xC946,0x89BE,0xCF04,0x877B,0xD4E1,0x8583,0xDAD8,0x83D6,0xE0E6,0x8276, +0xE707,0x8163,0xED38,0x809E,0xF374,0x8027,0xF9B8,0x7FFF,0x0000,0x7D8A,0xE707, +0x7642,0xCF04,0x6A6E,0xB8E3,0x5A82,0xA57E,0x471D,0x9592,0x30FC,0x89BE,0x18F9, +0x8276,0x0000,0x8000,0xE707,0x8276,0xCF04,0x89BE,0xB8E3,0x9592,0xA57E,0xA57E, +0x9592,0xB8E3,0x89BE,0xCF04,0x8276,0xE707,0x7FFF,0x0000,0x5A82,0xA57E,0x0000, +0x8000,0xA57E,0xA57E,}; + +q15_t rearranged_twiddle_stride3_256_q15[168]={ +0x7FFF,0x0000,0x7FA7,0xF695,0x7E9D,0xED38,0x7CE4,0xE3F4,0x7A7D,0xDAD8,0x776C, +0xD1EF,0x73B6,0xC946,0x6F5F,0xC0E9,0x6A6E,0xB8E3,0x64E9,0xB140,0x5ED7,0xAA0A, +0x5843,0xA34C,0x5134,0x9D0E,0x49B4,0x9759,0x41CE,0x9236,0x398D,0x8DAB,0x30FC, +0x89BE,0x2827,0x8676,0x1F1A,0x83D6,0x15E2,0x81E2,0x0C8C,0x809E,0x0324,0x800A, +0xF9B8,0x8027,0xF055,0x80F6,0xE707,0x8276,0xDDDC,0x84A3,0xD4E1,0x877B,0xCC21, +0x8AFB,0xC3A9,0x8F1D,0xBB85,0x93DC,0xB3C0,0x9930,0xAC65,0x9F14,0xA57E,0xA57E, +0x9F14,0xAC65,0x9930,0xB3C0,0x93DC,0xBB85,0x8F1D,0xC3A9,0x8AFB,0xCC21,0x877B, +0xD4E1,0x84A3,0xDDDC,0x8276,0xE707,0x80F6,0xF055,0x8027,0xF9B8,0x800A,0x0324, +0x809E,0x0C8C,0x81E2,0x15E2,0x83D6,0x1F1A,0x8676,0x2827,0x89BE,0x30FC,0x8DAB, +0x398D,0x9236,0x41CE,0x9759,0x49B4,0x9D0E,0x5134,0xA34C,0x5843,0xAA0A,0x5ED7, +0xB140,0x64E9,0xB8E3,0x6A6E,0xC0E9,0x6F5F,0xC946,0x73B6,0xD1EF,0x776C,0xDAD8, +0x7A7D,0xE3F4,0x7CE4,0xED38,0x7E9D,0xF695,0x7FA7,0x7FFF,0x0000,0x7A7D,0xDAD8, +0x6A6E,0xB8E3,0x5134,0x9D0E,0x30FC,0x89BE,0x0C8C,0x809E,0xE707,0x8276,0xC3A9, +0x8F1D,0xA57E,0xA57E,0x8F1D,0xC3A9,0x8276,0xE707,0x809E,0x0C8C,0x89BE,0x30FC, +0x9D0E,0x5134,0xB8E3,0x6A6E,0xDAD8,0x7A7D,0x7FFF,0x0000,0x30FC,0x89BE,0xA57E, +0xA57E,0x89BE,0x30FC,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) + +uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5]={ +0,512,640,672,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5]={ +0,512,640,672,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5]={ +0,512,640,672,0,}; + +q15_t rearranged_twiddle_stride1_1024_q15[680]={ +0x7FFF,0x0000,0x7FFF,0xFF37,0x7FFE,0xFE6E,0x7FFA,0xFDA5,0x7FF6,0xFCDC,0x7FF1, +0xFC13,0x7FEA,0xFB4A,0x7FE2,0xFA81,0x7FD9,0xF9B8,0x7FCE,0xF8EF,0x7FC2,0xF827, +0x7FB5,0xF75E,0x7FA7,0xF695,0x7F98,0xF5CD,0x7F87,0xF505,0x7F75,0xF43C,0x7F62, +0xF374,0x7F4E,0xF2AC,0x7F38,0xF1E4,0x7F22,0xF11C,0x7F0A,0xF055,0x7EF0,0xEF8D, +0x7ED6,0xEEC6,0x7EBA,0xEDFF,0x7E9D,0xED38,0x7E7F,0xEC71,0x7E60,0xEBAB,0x7E3F, +0xEAE4,0x7E1E,0xEA1E,0x7DFB,0xE958,0x7DD6,0xE892,0x7DB1,0xE7CD,0x7D8A,0xE707, +0x7D63,0xE642,0x7D3A,0xE57D,0x7D0F,0xE4B9,0x7CE4,0xE3F4,0x7CB7,0xE330,0x7C89, +0xE26D,0x7C5A,0xE1A9,0x7C2A,0xE0E6,0x7BF9,0xE023,0x7BC6,0xDF61,0x7B92,0xDE9E, +0x7B5D,0xDDDC,0x7B27,0xDD1B,0x7AEF,0xDC59,0x7AB7,0xDB99,0x7A7D,0xDAD8,0x7A42, +0xDA18,0x7A06,0xD958,0x79C9,0xD898,0x798A,0xD7D9,0x794A,0xD71B,0x790A,0xD65C, +0x78C8,0xD59E,0x7885,0xD4E1,0x7840,0xD424,0x77FB,0xD367,0x77B4,0xD2AB,0x776C, +0xD1EF,0x7723,0xD134,0x76D9,0xD079,0x768E,0xCFBE,0x7642,0xCF04,0x75F4,0xCE4B, +0x75A6,0xCD92,0x7556,0xCCD9,0x7505,0xCC21,0x74B3,0xCB69,0x7460,0xCAB2,0x740B, +0xC9FC,0x73B6,0xC946,0x735F,0xC890,0x7308,0xC7DB,0x72AF,0xC727,0x7255,0xC673, +0x71FA,0xC5C0,0x719E,0xC50D,0x7141,0xC45B,0x70E3,0xC3A9,0x7083,0xC2F8,0x7023, +0xC248,0x6FC2,0xC198,0x6F5F,0xC0E9,0x6EFB,0xC03A,0x6E97,0xBF8C,0x6E31,0xBEDF, +0x6DCA,0xBE32,0x6D62,0xBD86,0x6CF9,0xBCDA,0x6C8F,0xBC2F,0x6C24,0xBB85,0x6BB8, +0xBADC,0x6B4B,0xBA33,0x6ADD,0xB98B,0x6A6E,0xB8E3,0x69FD,0xB83C,0x698C,0xB796, +0x691A,0xB6F1,0x68A7,0xB64C,0x6832,0xB5A8,0x67BD,0xB505,0x6747,0xB462,0x66D0, +0xB3C0,0x6657,0xB31F,0x65DE,0xB27F,0x6564,0xB1DF,0x64E9,0xB140,0x646C,0xB0A2, +0x63EF,0xB005,0x6371,0xAF68,0x62F2,0xAECC,0x6272,0xAE31,0x61F1,0xAD97,0x616F, +0xACFD,0x60EC,0xAC65,0x6068,0xABCD,0x5FE4,0xAB36,0x5F5E,0xAAA0,0x5ED7,0xAA0A, +0x5E50,0xA976,0x5DC8,0xA8E2,0x5D3E,0xA84F,0x5CB4,0xA7BD,0x5C29,0xA72C,0x5B9D, +0xA69C,0x5B10,0xA60C,0x5A82,0xA57E,0x59F4,0xA4F0,0x5964,0xA463,0x58D4,0xA3D7, +0x5843,0xA34C,0x57B1,0xA2C2,0x571E,0xA238,0x568A,0xA1B0,0x55F6,0xA129,0x5560, +0xA0A2,0x54CA,0xA01C,0x5433,0x9F98,0x539B,0x9F14,0x5303,0x9E91,0x5269,0x9E0F, +0x51CF,0x9D8E,0x5134,0x9D0E,0x5098,0x9C8F,0x4FFB,0x9C11,0x4F5E,0x9B94,0x4EC0, +0x9B17,0x4E21,0x9A9C,0x4D81,0x9A22,0x4CE1,0x99A9,0x4C40,0x9930,0x4B9E,0x98B9, +0x4AFB,0x9843,0x4A58,0x97CE,0x49B4,0x9759,0x490F,0x96E6,0x486A,0x9674,0x47C4, +0x9603,0x471D,0x9592,0x4675,0x9523,0x45CD,0x94B5,0x4524,0x9448,0x447B,0x93DC, +0x43D1,0x9371,0x4326,0x9307,0x427A,0x929E,0x41CE,0x9236,0x4121,0x91CF,0x4074, +0x9169,0x3FC6,0x9105,0x3F17,0x90A1,0x3E68,0x903E,0x3DB8,0x8FDD,0x3D08,0x8F7D, +0x3C57,0x8F1D,0x3BA5,0x8EBF,0x3AF3,0x8E62,0x3A40,0x8E06,0x398D,0x8DAB,0x38D9, +0x8D51,0x3825,0x8CF8,0x3770,0x8CA1,0x36BA,0x8C4A,0x3604,0x8BF5,0x354E,0x8BA0, +0x3497,0x8B4D,0x33DF,0x8AFB,0x3327,0x8AAA,0x326E,0x8A5A,0x31B5,0x8A0C,0x30FC, +0x89BE,0x3042,0x8972,0x2F87,0x8927,0x2ECC,0x88DD,0x2E11,0x8894,0x2D55,0x884C, +0x2C99,0x8805,0x2BDC,0x87C0,0x2B1F,0x877B,0x2A62,0x8738,0x29A4,0x86F6,0x28E5, +0x86B6,0x2827,0x8676,0x2768,0x8637,0x26A8,0x85FA,0x25E8,0x85BE,0x2528,0x8583, +0x2467,0x8549,0x23A7,0x8511,0x22E5,0x84D9,0x2224,0x84A3,0x2162,0x846E,0x209F, +0x843A,0x1FDD,0x8407,0x1F1A,0x83D6,0x1E57,0x83A6,0x1D93,0x8377,0x1CD0,0x8349, +0x1C0C,0x831C,0x1B47,0x82F1,0x1A83,0x82C6,0x19BE,0x829D,0x18F9,0x8276,0x1833, +0x824F,0x176E,0x822A,0x16A8,0x8205,0x15E2,0x81E2,0x151C,0x81C1,0x1455,0x81A0, +0x138F,0x8181,0x12C8,0x8163,0x1201,0x8146,0x113A,0x812A,0x1073,0x8110,0x0FAB, +0x80F6,0x0EE4,0x80DE,0x0E1C,0x80C8,0x0D54,0x80B2,0x0C8C,0x809E,0x0BC4,0x808B, +0x0AFB,0x8079,0x0A33,0x8068,0x096B,0x8059,0x08A2,0x804B,0x07D9,0x803E,0x0711, +0x8032,0x0648,0x8027,0x057F,0x801E,0x04B6,0x8016,0x03ED,0x800F,0x0324,0x800A, +0x025B,0x8006,0x0192,0x8002,0x00C9,0x8001,0x7FFF,0x0000,0x7FF6,0xFCDC,0x7FD9, +0xF9B8,0x7FA7,0xF695,0x7F62,0xF374,0x7F0A,0xF055,0x7E9D,0xED38,0x7E1E,0xEA1E, +0x7D8A,0xE707,0x7CE4,0xE3F4,0x7C2A,0xE0E6,0x7B5D,0xDDDC,0x7A7D,0xDAD8,0x798A, +0xD7D9,0x7885,0xD4E1,0x776C,0xD1EF,0x7642,0xCF04,0x7505,0xCC21,0x73B6,0xC946, +0x7255,0xC673,0x70E3,0xC3A9,0x6F5F,0xC0E9,0x6DCA,0xBE32,0x6C24,0xBB85,0x6A6E, +0xB8E3,0x68A7,0xB64C,0x66D0,0xB3C0,0x64E9,0xB140,0x62F2,0xAECC,0x60EC,0xAC65, +0x5ED7,0xAA0A,0x5CB4,0xA7BD,0x5A82,0xA57E,0x5843,0xA34C,0x55F6,0xA129,0x539B, +0x9F14,0x5134,0x9D0E,0x4EC0,0x9B17,0x4C40,0x9930,0x49B4,0x9759,0x471D,0x9592, +0x447B,0x93DC,0x41CE,0x9236,0x3F17,0x90A1,0x3C57,0x8F1D,0x398D,0x8DAB,0x36BA, +0x8C4A,0x33DF,0x8AFB,0x30FC,0x89BE,0x2E11,0x8894,0x2B1F,0x877B,0x2827,0x8676, +0x2528,0x8583,0x2224,0x84A3,0x1F1A,0x83D6,0x1C0C,0x831C,0x18F9,0x8276,0x15E2, +0x81E2,0x12C8,0x8163,0x0FAB,0x80F6,0x0C8C,0x809E,0x096B,0x8059,0x0648,0x8027, +0x0324,0x800A,0x7FFF,0x0000,0x7F62,0xF374,0x7D8A,0xE707,0x7A7D,0xDAD8,0x7642, +0xCF04,0x70E3,0xC3A9,0x6A6E,0xB8E3,0x62F2,0xAECC,0x5A82,0xA57E,0x5134,0x9D0E, +0x471D,0x9592,0x3C57,0x8F1D,0x30FC,0x89BE,0x2528,0x8583,0x18F9,0x8276,0x0C8C, +0x809E,0x7FFF,0x0000,0x7642,0xCF04,0x5A82,0xA57E,0x30FC,0x89BE,}; + +q15_t rearranged_twiddle_stride2_1024_q15[680]={ +0x7FFF,0x0000,0x7FFE,0xFE6E,0x7FF6,0xFCDC,0x7FEA,0xFB4A,0x7FD9,0xF9B8,0x7FC2, +0xF827,0x7FA7,0xF695,0x7F87,0xF505,0x7F62,0xF374,0x7F38,0xF1E4,0x7F0A,0xF055, +0x7ED6,0xEEC6,0x7E9D,0xED38,0x7E60,0xEBAB,0x7E1E,0xEA1E,0x7DD6,0xE892,0x7D8A, +0xE707,0x7D3A,0xE57D,0x7CE4,0xE3F4,0x7C89,0xE26D,0x7C2A,0xE0E6,0x7BC6,0xDF61, +0x7B5D,0xDDDC,0x7AEF,0xDC59,0x7A7D,0xDAD8,0x7A06,0xD958,0x798A,0xD7D9,0x790A, +0xD65C,0x7885,0xD4E1,0x77FB,0xD367,0x776C,0xD1EF,0x76D9,0xD079,0x7642,0xCF04, +0x75A6,0xCD92,0x7505,0xCC21,0x7460,0xCAB2,0x73B6,0xC946,0x7308,0xC7DB,0x7255, +0xC673,0x719E,0xC50D,0x70E3,0xC3A9,0x7023,0xC248,0x6F5F,0xC0E9,0x6E97,0xBF8C, +0x6DCA,0xBE32,0x6CF9,0xBCDA,0x6C24,0xBB85,0x6B4B,0xBA33,0x6A6E,0xB8E3,0x698C, +0xB796,0x68A7,0xB64C,0x67BD,0xB505,0x66D0,0xB3C0,0x65DE,0xB27F,0x64E9,0xB140, +0x63EF,0xB005,0x62F2,0xAECC,0x61F1,0xAD97,0x60EC,0xAC65,0x5FE4,0xAB36,0x5ED7, +0xAA0A,0x5DC8,0xA8E2,0x5CB4,0xA7BD,0x5B9D,0xA69C,0x5A82,0xA57E,0x5964,0xA463, +0x5843,0xA34C,0x571E,0xA238,0x55F6,0xA129,0x54CA,0xA01C,0x539B,0x9F14,0x5269, +0x9E0F,0x5134,0x9D0E,0x4FFB,0x9C11,0x4EC0,0x9B17,0x4D81,0x9A22,0x4C40,0x9930, +0x4AFB,0x9843,0x49B4,0x9759,0x486A,0x9674,0x471D,0x9592,0x45CD,0x94B5,0x447B, +0x93DC,0x4326,0x9307,0x41CE,0x9236,0x4074,0x9169,0x3F17,0x90A1,0x3DB8,0x8FDD, +0x3C57,0x8F1D,0x3AF3,0x8E62,0x398D,0x8DAB,0x3825,0x8CF8,0x36BA,0x8C4A,0x354E, +0x8BA0,0x33DF,0x8AFB,0x326E,0x8A5A,0x30FC,0x89BE,0x2F87,0x8927,0x2E11,0x8894, +0x2C99,0x8805,0x2B1F,0x877B,0x29A4,0x86F6,0x2827,0x8676,0x26A8,0x85FA,0x2528, +0x8583,0x23A7,0x8511,0x2224,0x84A3,0x209F,0x843A,0x1F1A,0x83D6,0x1D93,0x8377, +0x1C0C,0x831C,0x1A83,0x82C6,0x18F9,0x8276,0x176E,0x822A,0x15E2,0x81E2,0x1455, +0x81A0,0x12C8,0x8163,0x113A,0x812A,0x0FAB,0x80F6,0x0E1C,0x80C8,0x0C8C,0x809E, +0x0AFB,0x8079,0x096B,0x8059,0x07D9,0x803E,0x0648,0x8027,0x04B6,0x8016,0x0324, +0x800A,0x0192,0x8002,0x0000,0x8000,0xFE6E,0x8002,0xFCDC,0x800A,0xFB4A,0x8016, +0xF9B8,0x8027,0xF827,0x803E,0xF695,0x8059,0xF505,0x8079,0xF374,0x809E,0xF1E4, +0x80C8,0xF055,0x80F6,0xEEC6,0x812A,0xED38,0x8163,0xEBAB,0x81A0,0xEA1E,0x81E2, +0xE892,0x822A,0xE707,0x8276,0xE57D,0x82C6,0xE3F4,0x831C,0xE26D,0x8377,0xE0E6, +0x83D6,0xDF61,0x843A,0xDDDC,0x84A3,0xDC59,0x8511,0xDAD8,0x8583,0xD958,0x85FA, +0xD7D9,0x8676,0xD65C,0x86F6,0xD4E1,0x877B,0xD367,0x8805,0xD1EF,0x8894,0xD079, +0x8927,0xCF04,0x89BE,0xCD92,0x8A5A,0xCC21,0x8AFB,0xCAB2,0x8BA0,0xC946,0x8C4A, +0xC7DB,0x8CF8,0xC673,0x8DAB,0xC50D,0x8E62,0xC3A9,0x8F1D,0xC248,0x8FDD,0xC0E9, +0x90A1,0xBF8C,0x9169,0xBE32,0x9236,0xBCDA,0x9307,0xBB85,0x93DC,0xBA33,0x94B5, +0xB8E3,0x9592,0xB796,0x9674,0xB64C,0x9759,0xB505,0x9843,0xB3C0,0x9930,0xB27F, +0x9A22,0xB140,0x9B17,0xB005,0x9C11,0xAECC,0x9D0E,0xAD97,0x9E0F,0xAC65,0x9F14, +0xAB36,0xA01C,0xAA0A,0xA129,0xA8E2,0xA238,0xA7BD,0xA34C,0xA69C,0xA463,0xA57E, +0xA57E,0xA463,0xA69C,0xA34C,0xA7BD,0xA238,0xA8E2,0xA129,0xAA0A,0xA01C,0xAB36, +0x9F14,0xAC65,0x9E0F,0xAD97,0x9D0E,0xAECC,0x9C11,0xB005,0x9B17,0xB140,0x9A22, +0xB27F,0x9930,0xB3C0,0x9843,0xB505,0x9759,0xB64C,0x9674,0xB796,0x9592,0xB8E3, +0x94B5,0xBA33,0x93DC,0xBB85,0x9307,0xBCDA,0x9236,0xBE32,0x9169,0xBF8C,0x90A1, +0xC0E9,0x8FDD,0xC248,0x8F1D,0xC3A9,0x8E62,0xC50D,0x8DAB,0xC673,0x8CF8,0xC7DB, +0x8C4A,0xC946,0x8BA0,0xCAB2,0x8AFB,0xCC21,0x8A5A,0xCD92,0x89BE,0xCF04,0x8927, +0xD079,0x8894,0xD1EF,0x8805,0xD367,0x877B,0xD4E1,0x86F6,0xD65C,0x8676,0xD7D9, +0x85FA,0xD958,0x8583,0xDAD8,0x8511,0xDC59,0x84A3,0xDDDC,0x843A,0xDF61,0x83D6, +0xE0E6,0x8377,0xE26D,0x831C,0xE3F4,0x82C6,0xE57D,0x8276,0xE707,0x822A,0xE892, +0x81E2,0xEA1E,0x81A0,0xEBAB,0x8163,0xED38,0x812A,0xEEC6,0x80F6,0xF055,0x80C8, +0xF1E4,0x809E,0xF374,0x8079,0xF505,0x8059,0xF695,0x803E,0xF827,0x8027,0xF9B8, +0x8016,0xFB4A,0x800A,0xFCDC,0x8002,0xFE6E,0x7FFF,0x0000,0x7FD9,0xF9B8,0x7F62, +0xF374,0x7E9D,0xED38,0x7D8A,0xE707,0x7C2A,0xE0E6,0x7A7D,0xDAD8,0x7885,0xD4E1, +0x7642,0xCF04,0x73B6,0xC946,0x70E3,0xC3A9,0x6DCA,0xBE32,0x6A6E,0xB8E3,0x66D0, +0xB3C0,0x62F2,0xAECC,0x5ED7,0xAA0A,0x5A82,0xA57E,0x55F6,0xA129,0x5134,0x9D0E, +0x4C40,0x9930,0x471D,0x9592,0x41CE,0x9236,0x3C57,0x8F1D,0x36BA,0x8C4A,0x30FC, +0x89BE,0x2B1F,0x877B,0x2528,0x8583,0x1F1A,0x83D6,0x18F9,0x8276,0x12C8,0x8163, +0x0C8C,0x809E,0x0648,0x8027,0x0000,0x8000,0xF9B8,0x8027,0xF374,0x809E,0xED38, +0x8163,0xE707,0x8276,0xE0E6,0x83D6,0xDAD8,0x8583,0xD4E1,0x877B,0xCF04,0x89BE, +0xC946,0x8C4A,0xC3A9,0x8F1D,0xBE32,0x9236,0xB8E3,0x9592,0xB3C0,0x9930,0xAECC, +0x9D0E,0xAA0A,0xA129,0xA57E,0xA57E,0xA129,0xAA0A,0x9D0E,0xAECC,0x9930,0xB3C0, +0x9592,0xB8E3,0x9236,0xBE32,0x8F1D,0xC3A9,0x8C4A,0xC946,0x89BE,0xCF04,0x877B, +0xD4E1,0x8583,0xDAD8,0x83D6,0xE0E6,0x8276,0xE707,0x8163,0xED38,0x809E,0xF374, +0x8027,0xF9B8,0x7FFF,0x0000,0x7D8A,0xE707,0x7642,0xCF04,0x6A6E,0xB8E3,0x5A82, +0xA57E,0x471D,0x9592,0x30FC,0x89BE,0x18F9,0x8276,0x0000,0x8000,0xE707,0x8276, +0xCF04,0x89BE,0xB8E3,0x9592,0xA57E,0xA57E,0x9592,0xB8E3,0x89BE,0xCF04,0x8276, +0xE707,0x7FFF,0x0000,0x5A82,0xA57E,0x0000,0x8000,0xA57E,0xA57E,}; + +q15_t rearranged_twiddle_stride3_1024_q15[680]={ +0x7FFF,0x0000,0x7FFA,0xFDA5,0x7FEA,0xFB4A,0x7FCE,0xF8EF,0x7FA7,0xF695,0x7F75, +0xF43C,0x7F38,0xF1E4,0x7EF0,0xEF8D,0x7E9D,0xED38,0x7E3F,0xEAE4,0x7DD6,0xE892, +0x7D63,0xE642,0x7CE4,0xE3F4,0x7C5A,0xE1A9,0x7BC6,0xDF61,0x7B27,0xDD1B,0x7A7D, +0xDAD8,0x79C9,0xD898,0x790A,0xD65C,0x7840,0xD424,0x776C,0xD1EF,0x768E,0xCFBE, +0x75A6,0xCD92,0x74B3,0xCB69,0x73B6,0xC946,0x72AF,0xC727,0x719E,0xC50D,0x7083, +0xC2F8,0x6F5F,0xC0E9,0x6E31,0xBEDF,0x6CF9,0xBCDA,0x6BB8,0xBADC,0x6A6E,0xB8E3, +0x691A,0xB6F1,0x67BD,0xB505,0x6657,0xB31F,0x64E9,0xB140,0x6371,0xAF68,0x61F1, +0xAD97,0x6068,0xABCD,0x5ED7,0xAA0A,0x5D3E,0xA84F,0x5B9D,0xA69C,0x59F4,0xA4F0, +0x5843,0xA34C,0x568A,0xA1B0,0x54CA,0xA01C,0x5303,0x9E91,0x5134,0x9D0E,0x4F5E, +0x9B94,0x4D81,0x9A22,0x4B9E,0x98B9,0x49B4,0x9759,0x47C4,0x9603,0x45CD,0x94B5, +0x43D1,0x9371,0x41CE,0x9236,0x3FC6,0x9105,0x3DB8,0x8FDD,0x3BA5,0x8EBF,0x398D, +0x8DAB,0x3770,0x8CA1,0x354E,0x8BA0,0x3327,0x8AAA,0x30FC,0x89BE,0x2ECC,0x88DD, +0x2C99,0x8805,0x2A62,0x8738,0x2827,0x8676,0x25E8,0x85BE,0x23A7,0x8511,0x2162, +0x846E,0x1F1A,0x83D6,0x1CD0,0x8349,0x1A83,0x82C6,0x1833,0x824F,0x15E2,0x81E2, +0x138F,0x8181,0x113A,0x812A,0x0EE4,0x80DE,0x0C8C,0x809E,0x0A33,0x8068,0x07D9, +0x803E,0x057F,0x801E,0x0324,0x800A,0x00C9,0x8001,0xFE6E,0x8002,0xFC13,0x800F, +0xF9B8,0x8027,0xF75E,0x804B,0xF505,0x8079,0xF2AC,0x80B2,0xF055,0x80F6,0xEDFF, +0x8146,0xEBAB,0x81A0,0xE958,0x8205,0xE707,0x8276,0xE4B9,0x82F1,0xE26D,0x8377, +0xE023,0x8407,0xDDDC,0x84A3,0xDB99,0x8549,0xD958,0x85FA,0xD71B,0x86B6,0xD4E1, +0x877B,0xD2AB,0x884C,0xD079,0x8927,0xCE4B,0x8A0C,0xCC21,0x8AFB,0xC9FC,0x8BF5, +0xC7DB,0x8CF8,0xC5C0,0x8E06,0xC3A9,0x8F1D,0xC198,0x903E,0xBF8C,0x9169,0xBD86, +0x929E,0xBB85,0x93DC,0xB98B,0x9523,0xB796,0x9674,0xB5A8,0x97CE,0xB3C0,0x9930, +0xB1DF,0x9A9C,0xB005,0x9C11,0xAE31,0x9D8E,0xAC65,0x9F14,0xAAA0,0xA0A2,0xA8E2, +0xA238,0xA72C,0xA3D7,0xA57E,0xA57E,0xA3D7,0xA72C,0xA238,0xA8E2,0xA0A2,0xAAA0, +0x9F14,0xAC65,0x9D8E,0xAE31,0x9C11,0xB005,0x9A9C,0xB1DF,0x9930,0xB3C0,0x97CE, +0xB5A8,0x9674,0xB796,0x9523,0xB98B,0x93DC,0xBB85,0x929E,0xBD86,0x9169,0xBF8C, +0x903E,0xC198,0x8F1D,0xC3A9,0x8E06,0xC5C0,0x8CF8,0xC7DB,0x8BF5,0xC9FC,0x8AFB, +0xCC21,0x8A0C,0xCE4B,0x8927,0xD079,0x884C,0xD2AB,0x877B,0xD4E1,0x86B6,0xD71B, +0x85FA,0xD958,0x8549,0xDB99,0x84A3,0xDDDC,0x8407,0xE023,0x8377,0xE26D,0x82F1, +0xE4B9,0x8276,0xE707,0x8205,0xE958,0x81A0,0xEBAB,0x8146,0xEDFF,0x80F6,0xF055, +0x80B2,0xF2AC,0x8079,0xF505,0x804B,0xF75E,0x8027,0xF9B8,0x800F,0xFC13,0x8002, +0xFE6E,0x8001,0x00C9,0x800A,0x0324,0x801E,0x057F,0x803E,0x07D9,0x8068,0x0A33, +0x809E,0x0C8C,0x80DE,0x0EE4,0x812A,0x113A,0x8181,0x138F,0x81E2,0x15E2,0x824F, +0x1833,0x82C6,0x1A83,0x8349,0x1CD0,0x83D6,0x1F1A,0x846E,0x2162,0x8511,0x23A7, +0x85BE,0x25E8,0x8676,0x2827,0x8738,0x2A62,0x8805,0x2C99,0x88DD,0x2ECC,0x89BE, +0x30FC,0x8AAA,0x3327,0x8BA0,0x354E,0x8CA1,0x3770,0x8DAB,0x398D,0x8EBF,0x3BA5, +0x8FDD,0x3DB8,0x9105,0x3FC6,0x9236,0x41CE,0x9371,0x43D1,0x94B5,0x45CD,0x9603, +0x47C4,0x9759,0x49B4,0x98B9,0x4B9E,0x9A22,0x4D81,0x9B94,0x4F5E,0x9D0E,0x5134, +0x9E91,0x5303,0xA01C,0x54CA,0xA1B0,0x568A,0xA34C,0x5843,0xA4F0,0x59F4,0xA69C, +0x5B9D,0xA84F,0x5D3E,0xAA0A,0x5ED7,0xABCD,0x6068,0xAD97,0x61F1,0xAF68,0x6371, +0xB140,0x64E9,0xB31F,0x6657,0xB505,0x67BD,0xB6F1,0x691A,0xB8E3,0x6A6E,0xBADC, +0x6BB8,0xBCDA,0x6CF9,0xBEDF,0x6E31,0xC0E9,0x6F5F,0xC2F8,0x7083,0xC50D,0x719E, +0xC727,0x72AF,0xC946,0x73B6,0xCB69,0x74B3,0xCD92,0x75A6,0xCFBE,0x768E,0xD1EF, +0x776C,0xD424,0x7840,0xD65C,0x790A,0xD898,0x79C9,0xDAD8,0x7A7D,0xDD1B,0x7B27, +0xDF61,0x7BC6,0xE1A9,0x7C5A,0xE3F4,0x7CE4,0xE642,0x7D63,0xE892,0x7DD6,0xEAE4, +0x7E3F,0xED38,0x7E9D,0xEF8D,0x7EF0,0xF1E4,0x7F38,0xF43C,0x7F75,0xF695,0x7FA7, +0xF8EF,0x7FCE,0xFB4A,0x7FEA,0xFDA5,0x7FFA,0x7FFF,0x0000,0x7FA7,0xF695,0x7E9D, +0xED38,0x7CE4,0xE3F4,0x7A7D,0xDAD8,0x776C,0xD1EF,0x73B6,0xC946,0x6F5F,0xC0E9, +0x6A6E,0xB8E3,0x64E9,0xB140,0x5ED7,0xAA0A,0x5843,0xA34C,0x5134,0x9D0E,0x49B4, +0x9759,0x41CE,0x9236,0x398D,0x8DAB,0x30FC,0x89BE,0x2827,0x8676,0x1F1A,0x83D6, +0x15E2,0x81E2,0x0C8C,0x809E,0x0324,0x800A,0xF9B8,0x8027,0xF055,0x80F6,0xE707, +0x8276,0xDDDC,0x84A3,0xD4E1,0x877B,0xCC21,0x8AFB,0xC3A9,0x8F1D,0xBB85,0x93DC, +0xB3C0,0x9930,0xAC65,0x9F14,0xA57E,0xA57E,0x9F14,0xAC65,0x9930,0xB3C0,0x93DC, +0xBB85,0x8F1D,0xC3A9,0x8AFB,0xCC21,0x877B,0xD4E1,0x84A3,0xDDDC,0x8276,0xE707, +0x80F6,0xF055,0x8027,0xF9B8,0x800A,0x0324,0x809E,0x0C8C,0x81E2,0x15E2,0x83D6, +0x1F1A,0x8676,0x2827,0x89BE,0x30FC,0x8DAB,0x398D,0x9236,0x41CE,0x9759,0x49B4, +0x9D0E,0x5134,0xA34C,0x5843,0xAA0A,0x5ED7,0xB140,0x64E9,0xB8E3,0x6A6E,0xC0E9, +0x6F5F,0xC946,0x73B6,0xD1EF,0x776C,0xDAD8,0x7A7D,0xE3F4,0x7CE4,0xED38,0x7E9D, +0xF695,0x7FA7,0x7FFF,0x0000,0x7A7D,0xDAD8,0x6A6E,0xB8E3,0x5134,0x9D0E,0x30FC, +0x89BE,0x0C8C,0x809E,0xE707,0x8276,0xC3A9,0x8F1D,0xA57E,0xA57E,0x8F1D,0xC3A9, +0x8276,0xE707,0x809E,0x0C8C,0x89BE,0x30FC,0x9D0E,0x5134,0xB8E3,0x6A6E,0xDAD8, +0x7A7D,0x7FFF,0x0000,0x30FC,0x89BE,0xA57E,0xA57E,0x89BE,0x30FC,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q15_8192) + +uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6]={ +0,2048,2560,2688,2720,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6]={ +0,2048,2560,2688,2720,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6]={ +0,2048,2560,2688,2720,0,}; + +q15_t rearranged_twiddle_stride1_4096_q15[2728]={ +0x7FFF,0x0000,0x7FFF,0xFFCE,0x7FFF,0xFF9B,0x7FFF,0xFF69,0x7FFF,0xFF37,0x7FFF, +0xFF05,0x7FFF,0xFED2,0x7FFE,0xFEA0,0x7FFE,0xFE6E,0x7FFD,0xFE3C,0x7FFC,0xFE09, +0x7FFB,0xFDD7,0x7FFA,0xFDA5,0x7FF9,0xFD73,0x7FF8,0xFD40,0x7FF7,0xFD0E,0x7FF6, +0xFCDC,0x7FF5,0xFCAA,0x7FF4,0xFC77,0x7FF2,0xFC45,0x7FF1,0xFC13,0x7FEF,0xFBE1, +0x7FED,0xFBAE,0x7FEC,0xFB7C,0x7FEA,0xFB4A,0x7FE8,0xFB18,0x7FE6,0xFAE5,0x7FE4, +0xFAB3,0x7FE2,0xFA81,0x7FE0,0xFA4F,0x7FDD,0xFA1D,0x7FDB,0xF9EA,0x7FD9,0xF9B8, +0x7FD6,0xF986,0x7FD3,0xF954,0x7FD1,0xF922,0x7FCE,0xF8EF,0x7FCB,0xF8BD,0x7FC8, +0xF88B,0x7FC5,0xF859,0x7FC2,0xF827,0x7FBF,0xF7F4,0x7FBC,0xF7C2,0x7FB9,0xF790, +0x7FB5,0xF75E,0x7FB2,0xF72C,0x7FAE,0xF6FA,0x7FAB,0xF6C8,0x7FA7,0xF695,0x7FA3, +0xF663,0x7FA0,0xF631,0x7F9C,0xF5FF,0x7F98,0xF5CD,0x7F94,0xF59B,0x7F90,0xF569, +0x7F8B,0xF537,0x7F87,0xF505,0x7F83,0xF4D3,0x7F7E,0xF4A0,0x7F7A,0xF46E,0x7F75, +0xF43C,0x7F71,0xF40A,0x7F6C,0xF3D8,0x7F67,0xF3A6,0x7F62,0xF374,0x7F5D,0xF342, +0x7F58,0xF310,0x7F53,0xF2DE,0x7F4E,0xF2AC,0x7F49,0xF27A,0x7F43,0xF248,0x7F3E, +0xF216,0x7F38,0xF1E4,0x7F33,0xF1B2,0x7F2D,0xF180,0x7F27,0xF14E,0x7F22,0xF11C, +0x7F1C,0xF0EB,0x7F16,0xF0B9,0x7F10,0xF087,0x7F0A,0xF055,0x7F03,0xF023,0x7EFD, +0xEFF1,0x7EF7,0xEFBF,0x7EF0,0xEF8D,0x7EEA,0xEF5C,0x7EE3,0xEF2A,0x7EDD,0xEEF8, +0x7ED6,0xEEC6,0x7ECF,0xEE94,0x7EC8,0xEE62,0x7EC1,0xEE31,0x7EBA,0xEDFF,0x7EB3, +0xEDCD,0x7EAC,0xED9B,0x7EA5,0xED6A,0x7E9D,0xED38,0x7E96,0xED06,0x7E8E,0xECD5, +0x7E87,0xECA3,0x7E7F,0xEC71,0x7E78,0xEC3F,0x7E70,0xEC0E,0x7E68,0xEBDC,0x7E60, +0xEBAB,0x7E58,0xEB79,0x7E50,0xEB47,0x7E48,0xEB16,0x7E3F,0xEAE4,0x7E37,0xEAB3, +0x7E2F,0xEA81,0x7E26,0xEA4F,0x7E1E,0xEA1E,0x7E15,0xE9EC,0x7E0C,0xE9BB,0x7E03, +0xE989,0x7DFB,0xE958,0x7DF2,0xE926,0x7DE9,0xE8F5,0x7DE0,0xE8C4,0x7DD6,0xE892, +0x7DCD,0xE861,0x7DC4,0xE82F,0x7DBA,0xE7FE,0x7DB1,0xE7CD,0x7DA7,0xE79B,0x7D9E, +0xE76A,0x7D94,0xE739,0x7D8A,0xE707,0x7D81,0xE6D6,0x7D77,0xE6A5,0x7D6D,0xE673, +0x7D63,0xE642,0x7D58,0xE611,0x7D4E,0xE5E0,0x7D44,0xE5AF,0x7D3A,0xE57D,0x7D2F, +0xE54C,0x7D25,0xE51B,0x7D1A,0xE4EA,0x7D0F,0xE4B9,0x7D05,0xE488,0x7CFA,0xE457, +0x7CEF,0xE426,0x7CE4,0xE3F4,0x7CD9,0xE3C3,0x7CCE,0xE392,0x7CC2,0xE361,0x7CB7, +0xE330,0x7CAC,0xE2FF,0x7CA0,0xE2CF,0x7C95,0xE29E,0x7C89,0xE26D,0x7C7E,0xE23C, +0x7C72,0xE20B,0x7C66,0xE1DA,0x7C5A,0xE1A9,0x7C4E,0xE178,0x7C42,0xE148,0x7C36, +0xE117,0x7C2A,0xE0E6,0x7C1E,0xE0B5,0x7C11,0xE085,0x7C05,0xE054,0x7BF9,0xE023, +0x7BEC,0xDFF2,0x7BDF,0xDFC2,0x7BD3,0xDF91,0x7BC6,0xDF61,0x7BB9,0xDF30,0x7BAC, +0xDEFF,0x7B9F,0xDECF,0x7B92,0xDE9E,0x7B85,0xDE6E,0x7B78,0xDE3D,0x7B6A,0xDE0D, +0x7B5D,0xDDDC,0x7B50,0xDDAC,0x7B42,0xDD7C,0x7B34,0xDD4B,0x7B27,0xDD1B,0x7B19, +0xDCEA,0x7B0B,0xDCBA,0x7AFD,0xDC8A,0x7AEF,0xDC59,0x7AE1,0xDC29,0x7AD3,0xDBF9, +0x7AC5,0xDBC9,0x7AB7,0xDB99,0x7AA8,0xDB68,0x7A9A,0xDB38,0x7A8C,0xDB08,0x7A7D, +0xDAD8,0x7A6E,0xDAA8,0x7A60,0xDA78,0x7A51,0xDA48,0x7A42,0xDA18,0x7A33,0xD9E8, +0x7A24,0xD9B8,0x7A15,0xD988,0x7A06,0xD958,0x79F7,0xD928,0x79E7,0xD8F8,0x79D8, +0xD8C8,0x79C9,0xD898,0x79B9,0xD869,0x79AA,0xD839,0x799A,0xD809,0x798A,0xD7D9, +0x797A,0xD7AA,0x796A,0xD77A,0x795B,0xD74A,0x794A,0xD71B,0x793A,0xD6EB,0x792A, +0xD6BB,0x791A,0xD68C,0x790A,0xD65C,0x78F9,0xD62D,0x78E9,0xD5FD,0x78D8,0xD5CE, +0x78C8,0xD59E,0x78B7,0xD56F,0x78A6,0xD53F,0x7895,0xD510,0x7885,0xD4E1,0x7874, +0xD4B1,0x7863,0xD482,0x7851,0xD453,0x7840,0xD424,0x782F,0xD3F4,0x781E,0xD3C5, +0x780C,0xD396,0x77FB,0xD367,0x77E9,0xD338,0x77D8,0xD309,0x77C6,0xD2DA,0x77B4, +0xD2AB,0x77A2,0xD27C,0x7790,0xD24D,0x777E,0xD21E,0x776C,0xD1EF,0x775A,0xD1C0, +0x7748,0xD191,0x7736,0xD162,0x7723,0xD134,0x7711,0xD105,0x76FE,0xD0D6,0x76EC, +0xD0A7,0x76D9,0xD079,0x76C7,0xD04A,0x76B4,0xD01B,0x76A1,0xCFED,0x768E,0xCFBE, +0x767B,0xCF90,0x7668,0xCF61,0x7655,0xCF33,0x7642,0xCF04,0x762E,0xCED6,0x761B, +0xCEA7,0x7608,0xCE79,0x75F4,0xCE4B,0x75E1,0xCE1C,0x75CD,0xCDEE,0x75B9,0xCDC0, +0x75A6,0xCD92,0x7592,0xCD63,0x757E,0xCD35,0x756A,0xCD07,0x7556,0xCCD9,0x7542, +0xCCAB,0x752D,0xCC7D,0x7519,0xCC4F,0x7505,0xCC21,0x74F0,0xCBF3,0x74DC,0xCBC5, +0x74C7,0xCB97,0x74B3,0xCB69,0x749E,0xCB3C,0x7489,0xCB0E,0x7475,0xCAE0,0x7460, +0xCAB2,0x744B,0xCA85,0x7436,0xCA57,0x7421,0xCA29,0x740B,0xC9FC,0x73F6,0xC9CE, +0x73E1,0xC9A1,0x73CB,0xC973,0x73B6,0xC946,0x73A0,0xC918,0x738B,0xC8EB,0x7375, +0xC8BE,0x735F,0xC890,0x734A,0xC863,0x7334,0xC836,0x731E,0xC809,0x7308,0xC7DB, +0x72F2,0xC7AE,0x72DC,0xC781,0x72C5,0xC754,0x72AF,0xC727,0x7299,0xC6FA,0x7282, +0xC6CD,0x726C,0xC6A0,0x7255,0xC673,0x723F,0xC646,0x7228,0xC619,0x7211,0xC5ED, +0x71FA,0xC5C0,0x71E3,0xC593,0x71CC,0xC566,0x71B5,0xC53A,0x719E,0xC50D,0x7187, +0xC4E0,0x7170,0xC4B4,0x7158,0xC487,0x7141,0xC45B,0x712A,0xC42E,0x7112,0xC402, +0x70FA,0xC3D6,0x70E3,0xC3A9,0x70CB,0xC37D,0x70B3,0xC351,0x709B,0xC324,0x7083, +0xC2F8,0x706B,0xC2CC,0x7053,0xC2A0,0x703B,0xC274,0x7023,0xC248,0x700B,0xC21C, +0x6FF2,0xC1F0,0x6FDA,0xC1C4,0x6FC2,0xC198,0x6FA9,0xC16C,0x6F90,0xC140,0x6F78, +0xC114,0x6F5F,0xC0E9,0x6F46,0xC0BD,0x6F2D,0xC091,0x6F14,0xC066,0x6EFB,0xC03A, +0x6EE2,0xC00F,0x6EC9,0xBFE3,0x6EB0,0xBFB8,0x6E97,0xBF8C,0x6E7D,0xBF61,0x6E64, +0xBF35,0x6E4A,0xBF0A,0x6E31,0xBEDF,0x6E17,0xBEB3,0x6DFE,0xBE88,0x6DE4,0xBE5D, +0x6DCA,0xBE32,0x6DB0,0xBE07,0x6D96,0xBDDC,0x6D7C,0xBDB1,0x6D62,0xBD86,0x6D48, +0xBD5B,0x6D2E,0xBD30,0x6D14,0xBD05,0x6CF9,0xBCDA,0x6CDF,0xBCAF,0x6CC4,0xBC85, +0x6CAA,0xBC5A,0x6C8F,0xBC2F,0x6C75,0xBC05,0x6C5A,0xBBDA,0x6C3F,0xBBB0,0x6C24, +0xBB85,0x6C09,0xBB5B,0x6BEE,0xBB30,0x6BD3,0xBB06,0x6BB8,0xBADC,0x6B9D,0xBAB1, +0x6B82,0xBA87,0x6B66,0xBA5D,0x6B4B,0xBA33,0x6B30,0xBA09,0x6B14,0xB9DF,0x6AF8, +0xB9B5,0x6ADD,0xB98B,0x6AC1,0xB961,0x6AA5,0xB937,0x6A89,0xB90D,0x6A6E,0xB8E3, +0x6A52,0xB8B9,0x6A36,0xB890,0x6A1A,0xB866,0x69FD,0xB83C,0x69E1,0xB813,0x69C5, +0xB7E9,0x69A9,0xB7C0,0x698C,0xB796,0x6970,0xB76D,0x6953,0xB743,0x6937,0xB71A, +0x691A,0xB6F1,0x68FD,0xB6C7,0x68E0,0xB69E,0x68C4,0xB675,0x68A7,0xB64C,0x688A, +0xB623,0x686D,0xB5FA,0x6850,0xB5D1,0x6832,0xB5A8,0x6815,0xB57F,0x67F8,0xB556, +0x67DA,0xB52D,0x67BD,0xB505,0x67A0,0xB4DC,0x6782,0xB4B3,0x6764,0xB48B,0x6747, +0xB462,0x6729,0xB439,0x670B,0xB411,0x66ED,0xB3E9,0x66D0,0xB3C0,0x66B2,0xB398, +0x6693,0xB36F,0x6675,0xB347,0x6657,0xB31F,0x6639,0xB2F7,0x661B,0xB2CF,0x65FC, +0xB2A7,0x65DE,0xB27F,0x65C0,0xB257,0x65A1,0xB22F,0x6582,0xB207,0x6564,0xB1DF, +0x6545,0xB1B7,0x6526,0xB18F,0x6507,0xB168,0x64E9,0xB140,0x64CA,0xB118,0x64AB, +0xB0F1,0x648B,0xB0C9,0x646C,0xB0A2,0x644D,0xB07B,0x642E,0xB053,0x640F,0xB02C, +0x63EF,0xB005,0x63D0,0xAFDD,0x63B0,0xAFB6,0x6391,0xAF8F,0x6371,0xAF68,0x6351, +0xAF41,0x6332,0xAF1A,0x6312,0xAEF3,0x62F2,0xAECC,0x62D2,0xAEA5,0x62B2,0xAE7F, +0x6292,0xAE58,0x6272,0xAE31,0x6252,0xAE0B,0x6232,0xADE4,0x6211,0xADBD,0x61F1, +0xAD97,0x61D1,0xAD70,0x61B0,0xAD4A,0x6190,0xAD24,0x616F,0xACFD,0x614E,0xACD7, +0x612E,0xACB1,0x610D,0xAC8B,0x60EC,0xAC65,0x60CB,0xAC3F,0x60AA,0xAC19,0x6089, +0xABF3,0x6068,0xABCD,0x6047,0xABA7,0x6026,0xAB81,0x6005,0xAB5C,0x5FE4,0xAB36, +0x5FC2,0xAB10,0x5FA1,0xAAEB,0x5F80,0xAAC5,0x5F5E,0xAAA0,0x5F3C,0xAA7A,0x5F1B, +0xAA55,0x5EF9,0xAA30,0x5ED7,0xAA0A,0x5EB6,0xA9E5,0x5E94,0xA9C0,0x5E72,0xA99B, +0x5E50,0xA976,0x5E2E,0xA951,0x5E0C,0xA92C,0x5DEA,0xA907,0x5DC8,0xA8E2,0x5DA5, +0xA8BD,0x5D83,0xA899,0x5D61,0xA874,0x5D3E,0xA84F,0x5D1C,0xA82B,0x5CF9,0xA806, +0x5CD7,0xA7E2,0x5CB4,0xA7BD,0x5C91,0xA799,0x5C6F,0xA774,0x5C4C,0xA750,0x5C29, +0xA72C,0x5C06,0xA708,0x5BE3,0xA6E4,0x5BC0,0xA6C0,0x5B9D,0xA69C,0x5B7A,0xA678, +0x5B57,0xA654,0x5B34,0xA630,0x5B10,0xA60C,0x5AED,0xA5E8,0x5AC9,0xA5C5,0x5AA6, +0xA5A1,0x5A82,0xA57E,0x5A5F,0xA55A,0x5A3B,0xA537,0x5A18,0xA513,0x59F4,0xA4F0, +0x59D0,0xA4CC,0x59AC,0xA4A9,0x5988,0xA486,0x5964,0xA463,0x5940,0xA440,0x591C, +0xA41D,0x58F8,0xA3FA,0x58D4,0xA3D7,0x58B0,0xA3B4,0x588C,0xA391,0x5867,0xA36F, +0x5843,0xA34C,0x581E,0xA329,0x57FA,0xA307,0x57D5,0xA2E4,0x57B1,0xA2C2,0x578C, +0xA29F,0x5767,0xA27D,0x5743,0xA25B,0x571E,0xA238,0x56F9,0xA216,0x56D4,0xA1F4, +0x56AF,0xA1D2,0x568A,0xA1B0,0x5665,0xA18E,0x5640,0xA16C,0x561B,0xA14A,0x55F6, +0xA129,0x55D0,0xA107,0x55AB,0xA0E5,0x5586,0xA0C4,0x5560,0xA0A2,0x553B,0xA080, +0x5515,0xA05F,0x54F0,0xA03E,0x54CA,0xA01C,0x54A4,0x9FFB,0x547F,0x9FDA,0x5459, +0x9FB9,0x5433,0x9F98,0x540D,0x9F77,0x53E7,0x9F56,0x53C1,0x9F35,0x539B,0x9F14, +0x5375,0x9EF3,0x534F,0x9ED2,0x5329,0x9EB2,0x5303,0x9E91,0x52DC,0x9E70,0x52B6, +0x9E50,0x5290,0x9E2F,0x5269,0x9E0F,0x5243,0x9DEF,0x521C,0x9DCE,0x51F5,0x9DAE, +0x51CF,0x9D8E,0x51A8,0x9D6E,0x5181,0x9D4E,0x515B,0x9D2E,0x5134,0x9D0E,0x510D, +0x9CEE,0x50E6,0x9CCE,0x50BF,0x9CAF,0x5098,0x9C8F,0x5071,0x9C6F,0x504A,0x9C50, +0x5023,0x9C30,0x4FFB,0x9C11,0x4FD4,0x9BF1,0x4FAD,0x9BD2,0x4F85,0x9BB3,0x4F5E, +0x9B94,0x4F37,0x9B75,0x4F0F,0x9B55,0x4EE8,0x9B36,0x4EC0,0x9B17,0x4E98,0x9AF9, +0x4E71,0x9ADA,0x4E49,0x9ABB,0x4E21,0x9A9C,0x4DF9,0x9A7E,0x4DD1,0x9A5F,0x4DA9, +0x9A40,0x4D81,0x9A22,0x4D59,0x9A04,0x4D31,0x99E5,0x4D09,0x99C7,0x4CE1,0x99A9, +0x4CB9,0x998B,0x4C91,0x996D,0x4C68,0x994E,0x4C40,0x9930,0x4C17,0x9913,0x4BEF, +0x98F5,0x4BC7,0x98D7,0x4B9E,0x98B9,0x4B75,0x989C,0x4B4D,0x987E,0x4B24,0x9860, +0x4AFB,0x9843,0x4AD3,0x9826,0x4AAA,0x9808,0x4A81,0x97EB,0x4A58,0x97CE,0x4A2F, +0x97B0,0x4A06,0x9793,0x49DD,0x9776,0x49B4,0x9759,0x498B,0x973C,0x4962,0x9720, +0x4939,0x9703,0x490F,0x96E6,0x48E6,0x96C9,0x48BD,0x96AD,0x4893,0x9690,0x486A, +0x9674,0x4840,0x9657,0x4817,0x963B,0x47ED,0x961F,0x47C4,0x9603,0x479A,0x95E6, +0x4770,0x95CA,0x4747,0x95AE,0x471D,0x9592,0x46F3,0x9577,0x46C9,0x955B,0x469F, +0x953F,0x4675,0x9523,0x464B,0x9508,0x4621,0x94EC,0x45F7,0x94D0,0x45CD,0x94B5, +0x45A3,0x949A,0x4579,0x947E,0x454F,0x9463,0x4524,0x9448,0x44FA,0x942D,0x44D0, +0x9412,0x44A5,0x93F7,0x447B,0x93DC,0x4450,0x93C1,0x4426,0x93A6,0x43FB,0x938B, +0x43D1,0x9371,0x43A6,0x9356,0x437B,0x933C,0x4351,0x9321,0x4326,0x9307,0x42FB, +0x92EC,0x42D0,0x92D2,0x42A5,0x92B8,0x427A,0x929E,0x424F,0x9284,0x4224,0x926A, +0x41F9,0x9250,0x41CE,0x9236,0x41A3,0x921C,0x4178,0x9202,0x414D,0x91E9,0x4121, +0x91CF,0x40F6,0x91B6,0x40CB,0x919C,0x409F,0x9183,0x4074,0x9169,0x4048,0x9150, +0x401D,0x9137,0x3FF1,0x911E,0x3FC6,0x9105,0x3F9A,0x90EC,0x3F6F,0x90D3,0x3F43, +0x90BA,0x3F17,0x90A1,0x3EEC,0x9088,0x3EC0,0x9070,0x3E94,0x9057,0x3E68,0x903E, +0x3E3C,0x9026,0x3E10,0x900E,0x3DE4,0x8FF5,0x3DB8,0x8FDD,0x3D8C,0x8FC5,0x3D60, +0x8FAD,0x3D34,0x8F95,0x3D08,0x8F7D,0x3CDC,0x8F65,0x3CAF,0x8F4D,0x3C83,0x8F35, +0x3C57,0x8F1D,0x3C2A,0x8F06,0x3BFE,0x8EEE,0x3BD2,0x8ED6,0x3BA5,0x8EBF,0x3B79, +0x8EA8,0x3B4C,0x8E90,0x3B20,0x8E79,0x3AF3,0x8E62,0x3AC6,0x8E4B,0x3A9A,0x8E34, +0x3A6D,0x8E1D,0x3A40,0x8E06,0x3A13,0x8DEF,0x39E7,0x8DD8,0x39BA,0x8DC1,0x398D, +0x8DAB,0x3960,0x8D94,0x3933,0x8D7E,0x3906,0x8D67,0x38D9,0x8D51,0x38AC,0x8D3B, +0x387F,0x8D24,0x3852,0x8D0E,0x3825,0x8CF8,0x37F7,0x8CE2,0x37CA,0x8CCC,0x379D, +0x8CB6,0x3770,0x8CA1,0x3742,0x8C8B,0x3715,0x8C75,0x36E8,0x8C60,0x36BA,0x8C4A, +0x368D,0x8C35,0x365F,0x8C1F,0x3632,0x8C0A,0x3604,0x8BF5,0x35D7,0x8BDF,0x35A9, +0x8BCA,0x357B,0x8BB5,0x354E,0x8BA0,0x3520,0x8B8B,0x34F2,0x8B77,0x34C4,0x8B62, +0x3497,0x8B4D,0x3469,0x8B39,0x343B,0x8B24,0x340D,0x8B10,0x33DF,0x8AFB,0x33B1, +0x8AE7,0x3383,0x8AD3,0x3355,0x8ABE,0x3327,0x8AAA,0x32F9,0x8A96,0x32CB,0x8A82, +0x329D,0x8A6E,0x326E,0x8A5A,0x3240,0x8A47,0x3212,0x8A33,0x31E4,0x8A1F,0x31B5, +0x8A0C,0x3187,0x89F8,0x3159,0x89E5,0x312A,0x89D2,0x30FC,0x89BE,0x30CD,0x89AB, +0x309F,0x8998,0x3070,0x8985,0x3042,0x8972,0x3013,0x895F,0x2FE5,0x894C,0x2FB6, +0x8939,0x2F87,0x8927,0x2F59,0x8914,0x2F2A,0x8902,0x2EFB,0x88EF,0x2ECC,0x88DD, +0x2E9E,0x88CA,0x2E6F,0x88B8,0x2E40,0x88A6,0x2E11,0x8894,0x2DE2,0x8882,0x2DB3, +0x8870,0x2D84,0x885E,0x2D55,0x884C,0x2D26,0x883A,0x2CF7,0x8828,0x2CC8,0x8817, +0x2C99,0x8805,0x2C6A,0x87F4,0x2C3B,0x87E2,0x2C0C,0x87D1,0x2BDC,0x87C0,0x2BAD, +0x87AF,0x2B7E,0x879D,0x2B4F,0x878C,0x2B1F,0x877B,0x2AF0,0x876B,0x2AC1,0x875A, +0x2A91,0x8749,0x2A62,0x8738,0x2A32,0x8728,0x2A03,0x8717,0x29D3,0x8707,0x29A4, +0x86F6,0x2974,0x86E6,0x2945,0x86D6,0x2915,0x86C6,0x28E5,0x86B6,0x28B6,0x86A5, +0x2886,0x8696,0x2856,0x8686,0x2827,0x8676,0x27F7,0x8666,0x27C7,0x8656,0x2797, +0x8647,0x2768,0x8637,0x2738,0x8628,0x2708,0x8619,0x26D8,0x8609,0x26A8,0x85FA, +0x2678,0x85EB,0x2648,0x85DC,0x2618,0x85CD,0x25E8,0x85BE,0x25B8,0x85AF,0x2588, +0x85A0,0x2558,0x8592,0x2528,0x8583,0x24F8,0x8574,0x24C8,0x8566,0x2498,0x8558, +0x2467,0x8549,0x2437,0x853B,0x2407,0x852D,0x23D7,0x851F,0x23A7,0x8511,0x2376, +0x8503,0x2346,0x84F5,0x2316,0x84E7,0x22E5,0x84D9,0x22B5,0x84CC,0x2284,0x84BE, +0x2254,0x84B0,0x2224,0x84A3,0x21F3,0x8496,0x21C3,0x8488,0x2192,0x847B,0x2162, +0x846E,0x2131,0x8461,0x2101,0x8454,0x20D0,0x8447,0x209F,0x843A,0x206F,0x842D, +0x203E,0x8421,0x200E,0x8414,0x1FDD,0x8407,0x1FAC,0x83FB,0x1F7B,0x83EF,0x1F4B, +0x83E2,0x1F1A,0x83D6,0x1EE9,0x83CA,0x1EB8,0x83BE,0x1E88,0x83B2,0x1E57,0x83A6, +0x1E26,0x839A,0x1DF5,0x838E,0x1DC4,0x8382,0x1D93,0x8377,0x1D62,0x836B,0x1D31, +0x8360,0x1D01,0x8354,0x1CD0,0x8349,0x1C9F,0x833E,0x1C6E,0x8332,0x1C3D,0x8327, +0x1C0C,0x831C,0x1BDA,0x8311,0x1BA9,0x8306,0x1B78,0x82FB,0x1B47,0x82F1,0x1B16, +0x82E6,0x1AE5,0x82DB,0x1AB4,0x82D1,0x1A83,0x82C6,0x1A51,0x82BC,0x1A20,0x82B2, +0x19EF,0x82A8,0x19BE,0x829D,0x198D,0x8293,0x195B,0x8289,0x192A,0x827F,0x18F9, +0x8276,0x18C7,0x826C,0x1896,0x8262,0x1865,0x8259,0x1833,0x824F,0x1802,0x8246, +0x17D1,0x823C,0x179F,0x8233,0x176E,0x822A,0x173C,0x8220,0x170B,0x8217,0x16DA, +0x820E,0x16A8,0x8205,0x1677,0x81FD,0x1645,0x81F4,0x1614,0x81EB,0x15E2,0x81E2, +0x15B1,0x81DA,0x157F,0x81D1,0x154D,0x81C9,0x151C,0x81C1,0x14EA,0x81B8,0x14B9, +0x81B0,0x1487,0x81A8,0x1455,0x81A0,0x1424,0x8198,0x13F2,0x8190,0x13C1,0x8188, +0x138F,0x8181,0x135D,0x8179,0x132B,0x8172,0x12FA,0x816A,0x12C8,0x8163,0x1296, +0x815B,0x1265,0x8154,0x1233,0x814D,0x1201,0x8146,0x11CF,0x813F,0x119E,0x8138, +0x116C,0x8131,0x113A,0x812A,0x1108,0x8123,0x10D6,0x811D,0x10A4,0x8116,0x1073, +0x8110,0x1041,0x8109,0x100F,0x8103,0x0FDD,0x80FD,0x0FAB,0x80F6,0x0F79,0x80F0, +0x0F47,0x80EA,0x0F15,0x80E4,0x0EE4,0x80DE,0x0EB2,0x80D9,0x0E80,0x80D3,0x0E4E, +0x80CD,0x0E1C,0x80C8,0x0DEA,0x80C2,0x0DB8,0x80BD,0x0D86,0x80B7,0x0D54,0x80B2, +0x0D22,0x80AD,0x0CF0,0x80A8,0x0CBE,0x80A3,0x0C8C,0x809E,0x0C5A,0x8099,0x0C28, +0x8094,0x0BF6,0x808F,0x0BC4,0x808B,0x0B92,0x8086,0x0B60,0x8082,0x0B2D,0x807D, +0x0AFB,0x8079,0x0AC9,0x8075,0x0A97,0x8070,0x0A65,0x806C,0x0A33,0x8068,0x0A01, +0x8064,0x09CF,0x8060,0x099D,0x805D,0x096B,0x8059,0x0938,0x8055,0x0906,0x8052, +0x08D4,0x804E,0x08A2,0x804B,0x0870,0x8047,0x083E,0x8044,0x080C,0x8041,0x07D9, +0x803E,0x07A7,0x803B,0x0775,0x8038,0x0743,0x8035,0x0711,0x8032,0x06DE,0x802F, +0x06AC,0x802D,0x067A,0x802A,0x0648,0x8027,0x0616,0x8025,0x05E3,0x8023,0x05B1, +0x8020,0x057F,0x801E,0x054D,0x801C,0x051B,0x801A,0x04E8,0x8018,0x04B6,0x8016, +0x0484,0x8014,0x0452,0x8013,0x041F,0x8011,0x03ED,0x800F,0x03BB,0x800E,0x0389, +0x800C,0x0356,0x800B,0x0324,0x800A,0x02F2,0x8009,0x02C0,0x8008,0x028D,0x8007, +0x025B,0x8006,0x0229,0x8005,0x01F7,0x8004,0x01C4,0x8003,0x0192,0x8002,0x0160, +0x8002,0x012E,0x8001,0x00FB,0x8001,0x00C9,0x8001,0x0097,0x8000,0x0065,0x8000, +0x0032,0x8000,0x7FFF,0x0000,0x7FFF,0xFF37,0x7FFE,0xFE6E,0x7FFA,0xFDA5,0x7FF6, +0xFCDC,0x7FF1,0xFC13,0x7FEA,0xFB4A,0x7FE2,0xFA81,0x7FD9,0xF9B8,0x7FCE,0xF8EF, +0x7FC2,0xF827,0x7FB5,0xF75E,0x7FA7,0xF695,0x7F98,0xF5CD,0x7F87,0xF505,0x7F75, +0xF43C,0x7F62,0xF374,0x7F4E,0xF2AC,0x7F38,0xF1E4,0x7F22,0xF11C,0x7F0A,0xF055, +0x7EF0,0xEF8D,0x7ED6,0xEEC6,0x7EBA,0xEDFF,0x7E9D,0xED38,0x7E7F,0xEC71,0x7E60, +0xEBAB,0x7E3F,0xEAE4,0x7E1E,0xEA1E,0x7DFB,0xE958,0x7DD6,0xE892,0x7DB1,0xE7CD, +0x7D8A,0xE707,0x7D63,0xE642,0x7D3A,0xE57D,0x7D0F,0xE4B9,0x7CE4,0xE3F4,0x7CB7, +0xE330,0x7C89,0xE26D,0x7C5A,0xE1A9,0x7C2A,0xE0E6,0x7BF9,0xE023,0x7BC6,0xDF61, +0x7B92,0xDE9E,0x7B5D,0xDDDC,0x7B27,0xDD1B,0x7AEF,0xDC59,0x7AB7,0xDB99,0x7A7D, +0xDAD8,0x7A42,0xDA18,0x7A06,0xD958,0x79C9,0xD898,0x798A,0xD7D9,0x794A,0xD71B, +0x790A,0xD65C,0x78C8,0xD59E,0x7885,0xD4E1,0x7840,0xD424,0x77FB,0xD367,0x77B4, +0xD2AB,0x776C,0xD1EF,0x7723,0xD134,0x76D9,0xD079,0x768E,0xCFBE,0x7642,0xCF04, +0x75F4,0xCE4B,0x75A6,0xCD92,0x7556,0xCCD9,0x7505,0xCC21,0x74B3,0xCB69,0x7460, +0xCAB2,0x740B,0xC9FC,0x73B6,0xC946,0x735F,0xC890,0x7308,0xC7DB,0x72AF,0xC727, +0x7255,0xC673,0x71FA,0xC5C0,0x719E,0xC50D,0x7141,0xC45B,0x70E3,0xC3A9,0x7083, +0xC2F8,0x7023,0xC248,0x6FC2,0xC198,0x6F5F,0xC0E9,0x6EFB,0xC03A,0x6E97,0xBF8C, +0x6E31,0xBEDF,0x6DCA,0xBE32,0x6D62,0xBD86,0x6CF9,0xBCDA,0x6C8F,0xBC2F,0x6C24, +0xBB85,0x6BB8,0xBADC,0x6B4B,0xBA33,0x6ADD,0xB98B,0x6A6E,0xB8E3,0x69FD,0xB83C, +0x698C,0xB796,0x691A,0xB6F1,0x68A7,0xB64C,0x6832,0xB5A8,0x67BD,0xB505,0x6747, +0xB462,0x66D0,0xB3C0,0x6657,0xB31F,0x65DE,0xB27F,0x6564,0xB1DF,0x64E9,0xB140, +0x646C,0xB0A2,0x63EF,0xB005,0x6371,0xAF68,0x62F2,0xAECC,0x6272,0xAE31,0x61F1, +0xAD97,0x616F,0xACFD,0x60EC,0xAC65,0x6068,0xABCD,0x5FE4,0xAB36,0x5F5E,0xAAA0, +0x5ED7,0xAA0A,0x5E50,0xA976,0x5DC8,0xA8E2,0x5D3E,0xA84F,0x5CB4,0xA7BD,0x5C29, +0xA72C,0x5B9D,0xA69C,0x5B10,0xA60C,0x5A82,0xA57E,0x59F4,0xA4F0,0x5964,0xA463, +0x58D4,0xA3D7,0x5843,0xA34C,0x57B1,0xA2C2,0x571E,0xA238,0x568A,0xA1B0,0x55F6, +0xA129,0x5560,0xA0A2,0x54CA,0xA01C,0x5433,0x9F98,0x539B,0x9F14,0x5303,0x9E91, +0x5269,0x9E0F,0x51CF,0x9D8E,0x5134,0x9D0E,0x5098,0x9C8F,0x4FFB,0x9C11,0x4F5E, +0x9B94,0x4EC0,0x9B17,0x4E21,0x9A9C,0x4D81,0x9A22,0x4CE1,0x99A9,0x4C40,0x9930, +0x4B9E,0x98B9,0x4AFB,0x9843,0x4A58,0x97CE,0x49B4,0x9759,0x490F,0x96E6,0x486A, +0x9674,0x47C4,0x9603,0x471D,0x9592,0x4675,0x9523,0x45CD,0x94B5,0x4524,0x9448, +0x447B,0x93DC,0x43D1,0x9371,0x4326,0x9307,0x427A,0x929E,0x41CE,0x9236,0x4121, +0x91CF,0x4074,0x9169,0x3FC6,0x9105,0x3F17,0x90A1,0x3E68,0x903E,0x3DB8,0x8FDD, +0x3D08,0x8F7D,0x3C57,0x8F1D,0x3BA5,0x8EBF,0x3AF3,0x8E62,0x3A40,0x8E06,0x398D, +0x8DAB,0x38D9,0x8D51,0x3825,0x8CF8,0x3770,0x8CA1,0x36BA,0x8C4A,0x3604,0x8BF5, +0x354E,0x8BA0,0x3497,0x8B4D,0x33DF,0x8AFB,0x3327,0x8AAA,0x326E,0x8A5A,0x31B5, +0x8A0C,0x30FC,0x89BE,0x3042,0x8972,0x2F87,0x8927,0x2ECC,0x88DD,0x2E11,0x8894, +0x2D55,0x884C,0x2C99,0x8805,0x2BDC,0x87C0,0x2B1F,0x877B,0x2A62,0x8738,0x29A4, +0x86F6,0x28E5,0x86B6,0x2827,0x8676,0x2768,0x8637,0x26A8,0x85FA,0x25E8,0x85BE, +0x2528,0x8583,0x2467,0x8549,0x23A7,0x8511,0x22E5,0x84D9,0x2224,0x84A3,0x2162, +0x846E,0x209F,0x843A,0x1FDD,0x8407,0x1F1A,0x83D6,0x1E57,0x83A6,0x1D93,0x8377, +0x1CD0,0x8349,0x1C0C,0x831C,0x1B47,0x82F1,0x1A83,0x82C6,0x19BE,0x829D,0x18F9, +0x8276,0x1833,0x824F,0x176E,0x822A,0x16A8,0x8205,0x15E2,0x81E2,0x151C,0x81C1, +0x1455,0x81A0,0x138F,0x8181,0x12C8,0x8163,0x1201,0x8146,0x113A,0x812A,0x1073, +0x8110,0x0FAB,0x80F6,0x0EE4,0x80DE,0x0E1C,0x80C8,0x0D54,0x80B2,0x0C8C,0x809E, +0x0BC4,0x808B,0x0AFB,0x8079,0x0A33,0x8068,0x096B,0x8059,0x08A2,0x804B,0x07D9, +0x803E,0x0711,0x8032,0x0648,0x8027,0x057F,0x801E,0x04B6,0x8016,0x03ED,0x800F, +0x0324,0x800A,0x025B,0x8006,0x0192,0x8002,0x00C9,0x8001,0x7FFF,0x0000,0x7FF6, +0xFCDC,0x7FD9,0xF9B8,0x7FA7,0xF695,0x7F62,0xF374,0x7F0A,0xF055,0x7E9D,0xED38, +0x7E1E,0xEA1E,0x7D8A,0xE707,0x7CE4,0xE3F4,0x7C2A,0xE0E6,0x7B5D,0xDDDC,0x7A7D, +0xDAD8,0x798A,0xD7D9,0x7885,0xD4E1,0x776C,0xD1EF,0x7642,0xCF04,0x7505,0xCC21, +0x73B6,0xC946,0x7255,0xC673,0x70E3,0xC3A9,0x6F5F,0xC0E9,0x6DCA,0xBE32,0x6C24, +0xBB85,0x6A6E,0xB8E3,0x68A7,0xB64C,0x66D0,0xB3C0,0x64E9,0xB140,0x62F2,0xAECC, +0x60EC,0xAC65,0x5ED7,0xAA0A,0x5CB4,0xA7BD,0x5A82,0xA57E,0x5843,0xA34C,0x55F6, +0xA129,0x539B,0x9F14,0x5134,0x9D0E,0x4EC0,0x9B17,0x4C40,0x9930,0x49B4,0x9759, +0x471D,0x9592,0x447B,0x93DC,0x41CE,0x9236,0x3F17,0x90A1,0x3C57,0x8F1D,0x398D, +0x8DAB,0x36BA,0x8C4A,0x33DF,0x8AFB,0x30FC,0x89BE,0x2E11,0x8894,0x2B1F,0x877B, +0x2827,0x8676,0x2528,0x8583,0x2224,0x84A3,0x1F1A,0x83D6,0x1C0C,0x831C,0x18F9, +0x8276,0x15E2,0x81E2,0x12C8,0x8163,0x0FAB,0x80F6,0x0C8C,0x809E,0x096B,0x8059, +0x0648,0x8027,0x0324,0x800A,0x7FFF,0x0000,0x7F62,0xF374,0x7D8A,0xE707,0x7A7D, +0xDAD8,0x7642,0xCF04,0x70E3,0xC3A9,0x6A6E,0xB8E3,0x62F2,0xAECC,0x5A82,0xA57E, +0x5134,0x9D0E,0x471D,0x9592,0x3C57,0x8F1D,0x30FC,0x89BE,0x2528,0x8583,0x18F9, +0x8276,0x0C8C,0x809E,0x7FFF,0x0000,0x7642,0xCF04,0x5A82,0xA57E,0x30FC,0x89BE,}; + +q15_t rearranged_twiddle_stride2_4096_q15[2728]={ +0x7FFF,0x0000,0x7FFF,0xFF9B,0x7FFF,0xFF37,0x7FFF,0xFED2,0x7FFE,0xFE6E,0x7FFC, +0xFE09,0x7FFA,0xFDA5,0x7FF8,0xFD40,0x7FF6,0xFCDC,0x7FF4,0xFC77,0x7FF1,0xFC13, +0x7FED,0xFBAE,0x7FEA,0xFB4A,0x7FE6,0xFAE5,0x7FE2,0xFA81,0x7FDD,0xFA1D,0x7FD9, +0xF9B8,0x7FD3,0xF954,0x7FCE,0xF8EF,0x7FC8,0xF88B,0x7FC2,0xF827,0x7FBC,0xF7C2, +0x7FB5,0xF75E,0x7FAE,0xF6FA,0x7FA7,0xF695,0x7FA0,0xF631,0x7F98,0xF5CD,0x7F90, +0xF569,0x7F87,0xF505,0x7F7E,0xF4A0,0x7F75,0xF43C,0x7F6C,0xF3D8,0x7F62,0xF374, +0x7F58,0xF310,0x7F4E,0xF2AC,0x7F43,0xF248,0x7F38,0xF1E4,0x7F2D,0xF180,0x7F22, +0xF11C,0x7F16,0xF0B9,0x7F0A,0xF055,0x7EFD,0xEFF1,0x7EF0,0xEF8D,0x7EE3,0xEF2A, +0x7ED6,0xEEC6,0x7EC8,0xEE62,0x7EBA,0xEDFF,0x7EAC,0xED9B,0x7E9D,0xED38,0x7E8E, +0xECD5,0x7E7F,0xEC71,0x7E70,0xEC0E,0x7E60,0xEBAB,0x7E50,0xEB47,0x7E3F,0xEAE4, +0x7E2F,0xEA81,0x7E1E,0xEA1E,0x7E0C,0xE9BB,0x7DFB,0xE958,0x7DE9,0xE8F5,0x7DD6, +0xE892,0x7DC4,0xE82F,0x7DB1,0xE7CD,0x7D9E,0xE76A,0x7D8A,0xE707,0x7D77,0xE6A5, +0x7D63,0xE642,0x7D4E,0xE5E0,0x7D3A,0xE57D,0x7D25,0xE51B,0x7D0F,0xE4B9,0x7CFA, +0xE457,0x7CE4,0xE3F4,0x7CCE,0xE392,0x7CB7,0xE330,0x7CA0,0xE2CF,0x7C89,0xE26D, +0x7C72,0xE20B,0x7C5A,0xE1A9,0x7C42,0xE148,0x7C2A,0xE0E6,0x7C11,0xE085,0x7BF9, +0xE023,0x7BDF,0xDFC2,0x7BC6,0xDF61,0x7BAC,0xDEFF,0x7B92,0xDE9E,0x7B78,0xDE3D, +0x7B5D,0xDDDC,0x7B42,0xDD7C,0x7B27,0xDD1B,0x7B0B,0xDCBA,0x7AEF,0xDC59,0x7AD3, +0xDBF9,0x7AB7,0xDB99,0x7A9A,0xDB38,0x7A7D,0xDAD8,0x7A60,0xDA78,0x7A42,0xDA18, +0x7A24,0xD9B8,0x7A06,0xD958,0x79E7,0xD8F8,0x79C9,0xD898,0x79AA,0xD839,0x798A, +0xD7D9,0x796A,0xD77A,0x794A,0xD71B,0x792A,0xD6BB,0x790A,0xD65C,0x78E9,0xD5FD, +0x78C8,0xD59E,0x78A6,0xD53F,0x7885,0xD4E1,0x7863,0xD482,0x7840,0xD424,0x781E, +0xD3C5,0x77FB,0xD367,0x77D8,0xD309,0x77B4,0xD2AB,0x7790,0xD24D,0x776C,0xD1EF, +0x7748,0xD191,0x7723,0xD134,0x76FE,0xD0D6,0x76D9,0xD079,0x76B4,0xD01B,0x768E, +0xCFBE,0x7668,0xCF61,0x7642,0xCF04,0x761B,0xCEA7,0x75F4,0xCE4B,0x75CD,0xCDEE, +0x75A6,0xCD92,0x757E,0xCD35,0x7556,0xCCD9,0x752D,0xCC7D,0x7505,0xCC21,0x74DC, +0xCBC5,0x74B3,0xCB69,0x7489,0xCB0E,0x7460,0xCAB2,0x7436,0xCA57,0x740B,0xC9FC, +0x73E1,0xC9A1,0x73B6,0xC946,0x738B,0xC8EB,0x735F,0xC890,0x7334,0xC836,0x7308, +0xC7DB,0x72DC,0xC781,0x72AF,0xC727,0x7282,0xC6CD,0x7255,0xC673,0x7228,0xC619, +0x71FA,0xC5C0,0x71CC,0xC566,0x719E,0xC50D,0x7170,0xC4B4,0x7141,0xC45B,0x7112, +0xC402,0x70E3,0xC3A9,0x70B3,0xC351,0x7083,0xC2F8,0x7053,0xC2A0,0x7023,0xC248, +0x6FF2,0xC1F0,0x6FC2,0xC198,0x6F90,0xC140,0x6F5F,0xC0E9,0x6F2D,0xC091,0x6EFB, +0xC03A,0x6EC9,0xBFE3,0x6E97,0xBF8C,0x6E64,0xBF35,0x6E31,0xBEDF,0x6DFE,0xBE88, +0x6DCA,0xBE32,0x6D96,0xBDDC,0x6D62,0xBD86,0x6D2E,0xBD30,0x6CF9,0xBCDA,0x6CC4, +0xBC85,0x6C8F,0xBC2F,0x6C5A,0xBBDA,0x6C24,0xBB85,0x6BEE,0xBB30,0x6BB8,0xBADC, +0x6B82,0xBA87,0x6B4B,0xBA33,0x6B14,0xB9DF,0x6ADD,0xB98B,0x6AA5,0xB937,0x6A6E, +0xB8E3,0x6A36,0xB890,0x69FD,0xB83C,0x69C5,0xB7E9,0x698C,0xB796,0x6953,0xB743, +0x691A,0xB6F1,0x68E0,0xB69E,0x68A7,0xB64C,0x686D,0xB5FA,0x6832,0xB5A8,0x67F8, +0xB556,0x67BD,0xB505,0x6782,0xB4B3,0x6747,0xB462,0x670B,0xB411,0x66D0,0xB3C0, +0x6693,0xB36F,0x6657,0xB31F,0x661B,0xB2CF,0x65DE,0xB27F,0x65A1,0xB22F,0x6564, +0xB1DF,0x6526,0xB18F,0x64E9,0xB140,0x64AB,0xB0F1,0x646C,0xB0A2,0x642E,0xB053, +0x63EF,0xB005,0x63B0,0xAFB6,0x6371,0xAF68,0x6332,0xAF1A,0x62F2,0xAECC,0x62B2, +0xAE7F,0x6272,0xAE31,0x6232,0xADE4,0x61F1,0xAD97,0x61B0,0xAD4A,0x616F,0xACFD, +0x612E,0xACB1,0x60EC,0xAC65,0x60AA,0xAC19,0x6068,0xABCD,0x6026,0xAB81,0x5FE4, +0xAB36,0x5FA1,0xAAEB,0x5F5E,0xAAA0,0x5F1B,0xAA55,0x5ED7,0xAA0A,0x5E94,0xA9C0, +0x5E50,0xA976,0x5E0C,0xA92C,0x5DC8,0xA8E2,0x5D83,0xA899,0x5D3E,0xA84F,0x5CF9, +0xA806,0x5CB4,0xA7BD,0x5C6F,0xA774,0x5C29,0xA72C,0x5BE3,0xA6E4,0x5B9D,0xA69C, +0x5B57,0xA654,0x5B10,0xA60C,0x5AC9,0xA5C5,0x5A82,0xA57E,0x5A3B,0xA537,0x59F4, +0xA4F0,0x59AC,0xA4A9,0x5964,0xA463,0x591C,0xA41D,0x58D4,0xA3D7,0x588C,0xA391, +0x5843,0xA34C,0x57FA,0xA307,0x57B1,0xA2C2,0x5767,0xA27D,0x571E,0xA238,0x56D4, +0xA1F4,0x568A,0xA1B0,0x5640,0xA16C,0x55F6,0xA129,0x55AB,0xA0E5,0x5560,0xA0A2, +0x5515,0xA05F,0x54CA,0xA01C,0x547F,0x9FDA,0x5433,0x9F98,0x53E7,0x9F56,0x539B, +0x9F14,0x534F,0x9ED2,0x5303,0x9E91,0x52B6,0x9E50,0x5269,0x9E0F,0x521C,0x9DCE, +0x51CF,0x9D8E,0x5181,0x9D4E,0x5134,0x9D0E,0x50E6,0x9CCE,0x5098,0x9C8F,0x504A, +0x9C50,0x4FFB,0x9C11,0x4FAD,0x9BD2,0x4F5E,0x9B94,0x4F0F,0x9B55,0x4EC0,0x9B17, +0x4E71,0x9ADA,0x4E21,0x9A9C,0x4DD1,0x9A5F,0x4D81,0x9A22,0x4D31,0x99E5,0x4CE1, +0x99A9,0x4C91,0x996D,0x4C40,0x9930,0x4BEF,0x98F5,0x4B9E,0x98B9,0x4B4D,0x987E, +0x4AFB,0x9843,0x4AAA,0x9808,0x4A58,0x97CE,0x4A06,0x9793,0x49B4,0x9759,0x4962, +0x9720,0x490F,0x96E6,0x48BD,0x96AD,0x486A,0x9674,0x4817,0x963B,0x47C4,0x9603, +0x4770,0x95CA,0x471D,0x9592,0x46C9,0x955B,0x4675,0x9523,0x4621,0x94EC,0x45CD, +0x94B5,0x4579,0x947E,0x4524,0x9448,0x44D0,0x9412,0x447B,0x93DC,0x4426,0x93A6, +0x43D1,0x9371,0x437B,0x933C,0x4326,0x9307,0x42D0,0x92D2,0x427A,0x929E,0x4224, +0x926A,0x41CE,0x9236,0x4178,0x9202,0x4121,0x91CF,0x40CB,0x919C,0x4074,0x9169, +0x401D,0x9137,0x3FC6,0x9105,0x3F6F,0x90D3,0x3F17,0x90A1,0x3EC0,0x9070,0x3E68, +0x903E,0x3E10,0x900E,0x3DB8,0x8FDD,0x3D60,0x8FAD,0x3D08,0x8F7D,0x3CAF,0x8F4D, +0x3C57,0x8F1D,0x3BFE,0x8EEE,0x3BA5,0x8EBF,0x3B4C,0x8E90,0x3AF3,0x8E62,0x3A9A, +0x8E34,0x3A40,0x8E06,0x39E7,0x8DD8,0x398D,0x8DAB,0x3933,0x8D7E,0x38D9,0x8D51, +0x387F,0x8D24,0x3825,0x8CF8,0x37CA,0x8CCC,0x3770,0x8CA1,0x3715,0x8C75,0x36BA, +0x8C4A,0x365F,0x8C1F,0x3604,0x8BF5,0x35A9,0x8BCA,0x354E,0x8BA0,0x34F2,0x8B77, +0x3497,0x8B4D,0x343B,0x8B24,0x33DF,0x8AFB,0x3383,0x8AD3,0x3327,0x8AAA,0x32CB, +0x8A82,0x326E,0x8A5A,0x3212,0x8A33,0x31B5,0x8A0C,0x3159,0x89E5,0x30FC,0x89BE, +0x309F,0x8998,0x3042,0x8972,0x2FE5,0x894C,0x2F87,0x8927,0x2F2A,0x8902,0x2ECC, +0x88DD,0x2E6F,0x88B8,0x2E11,0x8894,0x2DB3,0x8870,0x2D55,0x884C,0x2CF7,0x8828, +0x2C99,0x8805,0x2C3B,0x87E2,0x2BDC,0x87C0,0x2B7E,0x879D,0x2B1F,0x877B,0x2AC1, +0x875A,0x2A62,0x8738,0x2A03,0x8717,0x29A4,0x86F6,0x2945,0x86D6,0x28E5,0x86B6, +0x2886,0x8696,0x2827,0x8676,0x27C7,0x8656,0x2768,0x8637,0x2708,0x8619,0x26A8, +0x85FA,0x2648,0x85DC,0x25E8,0x85BE,0x2588,0x85A0,0x2528,0x8583,0x24C8,0x8566, +0x2467,0x8549,0x2407,0x852D,0x23A7,0x8511,0x2346,0x84F5,0x22E5,0x84D9,0x2284, +0x84BE,0x2224,0x84A3,0x21C3,0x8488,0x2162,0x846E,0x2101,0x8454,0x209F,0x843A, +0x203E,0x8421,0x1FDD,0x8407,0x1F7B,0x83EF,0x1F1A,0x83D6,0x1EB8,0x83BE,0x1E57, +0x83A6,0x1DF5,0x838E,0x1D93,0x8377,0x1D31,0x8360,0x1CD0,0x8349,0x1C6E,0x8332, +0x1C0C,0x831C,0x1BA9,0x8306,0x1B47,0x82F1,0x1AE5,0x82DB,0x1A83,0x82C6,0x1A20, +0x82B2,0x19BE,0x829D,0x195B,0x8289,0x18F9,0x8276,0x1896,0x8262,0x1833,0x824F, +0x17D1,0x823C,0x176E,0x822A,0x170B,0x8217,0x16A8,0x8205,0x1645,0x81F4,0x15E2, +0x81E2,0x157F,0x81D1,0x151C,0x81C1,0x14B9,0x81B0,0x1455,0x81A0,0x13F2,0x8190, +0x138F,0x8181,0x132B,0x8172,0x12C8,0x8163,0x1265,0x8154,0x1201,0x8146,0x119E, +0x8138,0x113A,0x812A,0x10D6,0x811D,0x1073,0x8110,0x100F,0x8103,0x0FAB,0x80F6, +0x0F47,0x80EA,0x0EE4,0x80DE,0x0E80,0x80D3,0x0E1C,0x80C8,0x0DB8,0x80BD,0x0D54, +0x80B2,0x0CF0,0x80A8,0x0C8C,0x809E,0x0C28,0x8094,0x0BC4,0x808B,0x0B60,0x8082, +0x0AFB,0x8079,0x0A97,0x8070,0x0A33,0x8068,0x09CF,0x8060,0x096B,0x8059,0x0906, +0x8052,0x08A2,0x804B,0x083E,0x8044,0x07D9,0x803E,0x0775,0x8038,0x0711,0x8032, +0x06AC,0x802D,0x0648,0x8027,0x05E3,0x8023,0x057F,0x801E,0x051B,0x801A,0x04B6, +0x8016,0x0452,0x8013,0x03ED,0x800F,0x0389,0x800C,0x0324,0x800A,0x02C0,0x8008, +0x025B,0x8006,0x01F7,0x8004,0x0192,0x8002,0x012E,0x8001,0x00C9,0x8001,0x0065, +0x8000,0x0000,0x8000,0xFF9B,0x8000,0xFF37,0x8001,0xFED2,0x8001,0xFE6E,0x8002, +0xFE09,0x8004,0xFDA5,0x8006,0xFD40,0x8008,0xFCDC,0x800A,0xFC77,0x800C,0xFC13, +0x800F,0xFBAE,0x8013,0xFB4A,0x8016,0xFAE5,0x801A,0xFA81,0x801E,0xFA1D,0x8023, +0xF9B8,0x8027,0xF954,0x802D,0xF8EF,0x8032,0xF88B,0x8038,0xF827,0x803E,0xF7C2, +0x8044,0xF75E,0x804B,0xF6FA,0x8052,0xF695,0x8059,0xF631,0x8060,0xF5CD,0x8068, +0xF569,0x8070,0xF505,0x8079,0xF4A0,0x8082,0xF43C,0x808B,0xF3D8,0x8094,0xF374, +0x809E,0xF310,0x80A8,0xF2AC,0x80B2,0xF248,0x80BD,0xF1E4,0x80C8,0xF180,0x80D3, +0xF11C,0x80DE,0xF0B9,0x80EA,0xF055,0x80F6,0xEFF1,0x8103,0xEF8D,0x8110,0xEF2A, +0x811D,0xEEC6,0x812A,0xEE62,0x8138,0xEDFF,0x8146,0xED9B,0x8154,0xED38,0x8163, +0xECD5,0x8172,0xEC71,0x8181,0xEC0E,0x8190,0xEBAB,0x81A0,0xEB47,0x81B0,0xEAE4, +0x81C1,0xEA81,0x81D1,0xEA1E,0x81E2,0xE9BB,0x81F4,0xE958,0x8205,0xE8F5,0x8217, +0xE892,0x822A,0xE82F,0x823C,0xE7CD,0x824F,0xE76A,0x8262,0xE707,0x8276,0xE6A5, +0x8289,0xE642,0x829D,0xE5E0,0x82B2,0xE57D,0x82C6,0xE51B,0x82DB,0xE4B9,0x82F1, +0xE457,0x8306,0xE3F4,0x831C,0xE392,0x8332,0xE330,0x8349,0xE2CF,0x8360,0xE26D, +0x8377,0xE20B,0x838E,0xE1A9,0x83A6,0xE148,0x83BE,0xE0E6,0x83D6,0xE085,0x83EF, +0xE023,0x8407,0xDFC2,0x8421,0xDF61,0x843A,0xDEFF,0x8454,0xDE9E,0x846E,0xDE3D, +0x8488,0xDDDC,0x84A3,0xDD7C,0x84BE,0xDD1B,0x84D9,0xDCBA,0x84F5,0xDC59,0x8511, +0xDBF9,0x852D,0xDB99,0x8549,0xDB38,0x8566,0xDAD8,0x8583,0xDA78,0x85A0,0xDA18, +0x85BE,0xD9B8,0x85DC,0xD958,0x85FA,0xD8F8,0x8619,0xD898,0x8637,0xD839,0x8656, +0xD7D9,0x8676,0xD77A,0x8696,0xD71B,0x86B6,0xD6BB,0x86D6,0xD65C,0x86F6,0xD5FD, +0x8717,0xD59E,0x8738,0xD53F,0x875A,0xD4E1,0x877B,0xD482,0x879D,0xD424,0x87C0, +0xD3C5,0x87E2,0xD367,0x8805,0xD309,0x8828,0xD2AB,0x884C,0xD24D,0x8870,0xD1EF, +0x8894,0xD191,0x88B8,0xD134,0x88DD,0xD0D6,0x8902,0xD079,0x8927,0xD01B,0x894C, +0xCFBE,0x8972,0xCF61,0x8998,0xCF04,0x89BE,0xCEA7,0x89E5,0xCE4B,0x8A0C,0xCDEE, +0x8A33,0xCD92,0x8A5A,0xCD35,0x8A82,0xCCD9,0x8AAA,0xCC7D,0x8AD3,0xCC21,0x8AFB, +0xCBC5,0x8B24,0xCB69,0x8B4D,0xCB0E,0x8B77,0xCAB2,0x8BA0,0xCA57,0x8BCA,0xC9FC, +0x8BF5,0xC9A1,0x8C1F,0xC946,0x8C4A,0xC8EB,0x8C75,0xC890,0x8CA1,0xC836,0x8CCC, +0xC7DB,0x8CF8,0xC781,0x8D24,0xC727,0x8D51,0xC6CD,0x8D7E,0xC673,0x8DAB,0xC619, +0x8DD8,0xC5C0,0x8E06,0xC566,0x8E34,0xC50D,0x8E62,0xC4B4,0x8E90,0xC45B,0x8EBF, +0xC402,0x8EEE,0xC3A9,0x8F1D,0xC351,0x8F4D,0xC2F8,0x8F7D,0xC2A0,0x8FAD,0xC248, +0x8FDD,0xC1F0,0x900E,0xC198,0x903E,0xC140,0x9070,0xC0E9,0x90A1,0xC091,0x90D3, +0xC03A,0x9105,0xBFE3,0x9137,0xBF8C,0x9169,0xBF35,0x919C,0xBEDF,0x91CF,0xBE88, +0x9202,0xBE32,0x9236,0xBDDC,0x926A,0xBD86,0x929E,0xBD30,0x92D2,0xBCDA,0x9307, +0xBC85,0x933C,0xBC2F,0x9371,0xBBDA,0x93A6,0xBB85,0x93DC,0xBB30,0x9412,0xBADC, +0x9448,0xBA87,0x947E,0xBA33,0x94B5,0xB9DF,0x94EC,0xB98B,0x9523,0xB937,0x955B, +0xB8E3,0x9592,0xB890,0x95CA,0xB83C,0x9603,0xB7E9,0x963B,0xB796,0x9674,0xB743, +0x96AD,0xB6F1,0x96E6,0xB69E,0x9720,0xB64C,0x9759,0xB5FA,0x9793,0xB5A8,0x97CE, +0xB556,0x9808,0xB505,0x9843,0xB4B3,0x987E,0xB462,0x98B9,0xB411,0x98F5,0xB3C0, +0x9930,0xB36F,0x996D,0xB31F,0x99A9,0xB2CF,0x99E5,0xB27F,0x9A22,0xB22F,0x9A5F, +0xB1DF,0x9A9C,0xB18F,0x9ADA,0xB140,0x9B17,0xB0F1,0x9B55,0xB0A2,0x9B94,0xB053, +0x9BD2,0xB005,0x9C11,0xAFB6,0x9C50,0xAF68,0x9C8F,0xAF1A,0x9CCE,0xAECC,0x9D0E, +0xAE7F,0x9D4E,0xAE31,0x9D8E,0xADE4,0x9DCE,0xAD97,0x9E0F,0xAD4A,0x9E50,0xACFD, +0x9E91,0xACB1,0x9ED2,0xAC65,0x9F14,0xAC19,0x9F56,0xABCD,0x9F98,0xAB81,0x9FDA, +0xAB36,0xA01C,0xAAEB,0xA05F,0xAAA0,0xA0A2,0xAA55,0xA0E5,0xAA0A,0xA129,0xA9C0, +0xA16C,0xA976,0xA1B0,0xA92C,0xA1F4,0xA8E2,0xA238,0xA899,0xA27D,0xA84F,0xA2C2, +0xA806,0xA307,0xA7BD,0xA34C,0xA774,0xA391,0xA72C,0xA3D7,0xA6E4,0xA41D,0xA69C, +0xA463,0xA654,0xA4A9,0xA60C,0xA4F0,0xA5C5,0xA537,0xA57E,0xA57E,0xA537,0xA5C5, +0xA4F0,0xA60C,0xA4A9,0xA654,0xA463,0xA69C,0xA41D,0xA6E4,0xA3D7,0xA72C,0xA391, +0xA774,0xA34C,0xA7BD,0xA307,0xA806,0xA2C2,0xA84F,0xA27D,0xA899,0xA238,0xA8E2, +0xA1F4,0xA92C,0xA1B0,0xA976,0xA16C,0xA9C0,0xA129,0xAA0A,0xA0E5,0xAA55,0xA0A2, +0xAAA0,0xA05F,0xAAEB,0xA01C,0xAB36,0x9FDA,0xAB81,0x9F98,0xABCD,0x9F56,0xAC19, +0x9F14,0xAC65,0x9ED2,0xACB1,0x9E91,0xACFD,0x9E50,0xAD4A,0x9E0F,0xAD97,0x9DCE, +0xADE4,0x9D8E,0xAE31,0x9D4E,0xAE7F,0x9D0E,0xAECC,0x9CCE,0xAF1A,0x9C8F,0xAF68, +0x9C50,0xAFB6,0x9C11,0xB005,0x9BD2,0xB053,0x9B94,0xB0A2,0x9B55,0xB0F1,0x9B17, +0xB140,0x9ADA,0xB18F,0x9A9C,0xB1DF,0x9A5F,0xB22F,0x9A22,0xB27F,0x99E5,0xB2CF, +0x99A9,0xB31F,0x996D,0xB36F,0x9930,0xB3C0,0x98F5,0xB411,0x98B9,0xB462,0x987E, +0xB4B3,0x9843,0xB505,0x9808,0xB556,0x97CE,0xB5A8,0x9793,0xB5FA,0x9759,0xB64C, +0x9720,0xB69E,0x96E6,0xB6F1,0x96AD,0xB743,0x9674,0xB796,0x963B,0xB7E9,0x9603, +0xB83C,0x95CA,0xB890,0x9592,0xB8E3,0x955B,0xB937,0x9523,0xB98B,0x94EC,0xB9DF, +0x94B5,0xBA33,0x947E,0xBA87,0x9448,0xBADC,0x9412,0xBB30,0x93DC,0xBB85,0x93A6, +0xBBDA,0x9371,0xBC2F,0x933C,0xBC85,0x9307,0xBCDA,0x92D2,0xBD30,0x929E,0xBD86, +0x926A,0xBDDC,0x9236,0xBE32,0x9202,0xBE88,0x91CF,0xBEDF,0x919C,0xBF35,0x9169, +0xBF8C,0x9137,0xBFE3,0x9105,0xC03A,0x90D3,0xC091,0x90A1,0xC0E9,0x9070,0xC140, +0x903E,0xC198,0x900E,0xC1F0,0x8FDD,0xC248,0x8FAD,0xC2A0,0x8F7D,0xC2F8,0x8F4D, +0xC351,0x8F1D,0xC3A9,0x8EEE,0xC402,0x8EBF,0xC45B,0x8E90,0xC4B4,0x8E62,0xC50D, +0x8E34,0xC566,0x8E06,0xC5C0,0x8DD8,0xC619,0x8DAB,0xC673,0x8D7E,0xC6CD,0x8D51, +0xC727,0x8D24,0xC781,0x8CF8,0xC7DB,0x8CCC,0xC836,0x8CA1,0xC890,0x8C75,0xC8EB, +0x8C4A,0xC946,0x8C1F,0xC9A1,0x8BF5,0xC9FC,0x8BCA,0xCA57,0x8BA0,0xCAB2,0x8B77, +0xCB0E,0x8B4D,0xCB69,0x8B24,0xCBC5,0x8AFB,0xCC21,0x8AD3,0xCC7D,0x8AAA,0xCCD9, +0x8A82,0xCD35,0x8A5A,0xCD92,0x8A33,0xCDEE,0x8A0C,0xCE4B,0x89E5,0xCEA7,0x89BE, +0xCF04,0x8998,0xCF61,0x8972,0xCFBE,0x894C,0xD01B,0x8927,0xD079,0x8902,0xD0D6, +0x88DD,0xD134,0x88B8,0xD191,0x8894,0xD1EF,0x8870,0xD24D,0x884C,0xD2AB,0x8828, +0xD309,0x8805,0xD367,0x87E2,0xD3C5,0x87C0,0xD424,0x879D,0xD482,0x877B,0xD4E1, +0x875A,0xD53F,0x8738,0xD59E,0x8717,0xD5FD,0x86F6,0xD65C,0x86D6,0xD6BB,0x86B6, +0xD71B,0x8696,0xD77A,0x8676,0xD7D9,0x8656,0xD839,0x8637,0xD898,0x8619,0xD8F8, +0x85FA,0xD958,0x85DC,0xD9B8,0x85BE,0xDA18,0x85A0,0xDA78,0x8583,0xDAD8,0x8566, +0xDB38,0x8549,0xDB99,0x852D,0xDBF9,0x8511,0xDC59,0x84F5,0xDCBA,0x84D9,0xDD1B, +0x84BE,0xDD7C,0x84A3,0xDDDC,0x8488,0xDE3D,0x846E,0xDE9E,0x8454,0xDEFF,0x843A, +0xDF61,0x8421,0xDFC2,0x8407,0xE023,0x83EF,0xE085,0x83D6,0xE0E6,0x83BE,0xE148, +0x83A6,0xE1A9,0x838E,0xE20B,0x8377,0xE26D,0x8360,0xE2CF,0x8349,0xE330,0x8332, +0xE392,0x831C,0xE3F4,0x8306,0xE457,0x82F1,0xE4B9,0x82DB,0xE51B,0x82C6,0xE57D, +0x82B2,0xE5E0,0x829D,0xE642,0x8289,0xE6A5,0x8276,0xE707,0x8262,0xE76A,0x824F, +0xE7CD,0x823C,0xE82F,0x822A,0xE892,0x8217,0xE8F5,0x8205,0xE958,0x81F4,0xE9BB, +0x81E2,0xEA1E,0x81D1,0xEA81,0x81C1,0xEAE4,0x81B0,0xEB47,0x81A0,0xEBAB,0x8190, +0xEC0E,0x8181,0xEC71,0x8172,0xECD5,0x8163,0xED38,0x8154,0xED9B,0x8146,0xEDFF, +0x8138,0xEE62,0x812A,0xEEC6,0x811D,0xEF2A,0x8110,0xEF8D,0x8103,0xEFF1,0x80F6, +0xF055,0x80EA,0xF0B9,0x80DE,0xF11C,0x80D3,0xF180,0x80C8,0xF1E4,0x80BD,0xF248, +0x80B2,0xF2AC,0x80A8,0xF310,0x809E,0xF374,0x8094,0xF3D8,0x808B,0xF43C,0x8082, +0xF4A0,0x8079,0xF505,0x8070,0xF569,0x8068,0xF5CD,0x8060,0xF631,0x8059,0xF695, +0x8052,0xF6FA,0x804B,0xF75E,0x8044,0xF7C2,0x803E,0xF827,0x8038,0xF88B,0x8032, +0xF8EF,0x802D,0xF954,0x8027,0xF9B8,0x8023,0xFA1D,0x801E,0xFA81,0x801A,0xFAE5, +0x8016,0xFB4A,0x8013,0xFBAE,0x800F,0xFC13,0x800C,0xFC77,0x800A,0xFCDC,0x8008, +0xFD40,0x8006,0xFDA5,0x8004,0xFE09,0x8002,0xFE6E,0x8001,0xFED2,0x8001,0xFF37, +0x8000,0xFF9B,0x7FFF,0x0000,0x7FFE,0xFE6E,0x7FF6,0xFCDC,0x7FEA,0xFB4A,0x7FD9, +0xF9B8,0x7FC2,0xF827,0x7FA7,0xF695,0x7F87,0xF505,0x7F62,0xF374,0x7F38,0xF1E4, +0x7F0A,0xF055,0x7ED6,0xEEC6,0x7E9D,0xED38,0x7E60,0xEBAB,0x7E1E,0xEA1E,0x7DD6, +0xE892,0x7D8A,0xE707,0x7D3A,0xE57D,0x7CE4,0xE3F4,0x7C89,0xE26D,0x7C2A,0xE0E6, +0x7BC6,0xDF61,0x7B5D,0xDDDC,0x7AEF,0xDC59,0x7A7D,0xDAD8,0x7A06,0xD958,0x798A, +0xD7D9,0x790A,0xD65C,0x7885,0xD4E1,0x77FB,0xD367,0x776C,0xD1EF,0x76D9,0xD079, +0x7642,0xCF04,0x75A6,0xCD92,0x7505,0xCC21,0x7460,0xCAB2,0x73B6,0xC946,0x7308, +0xC7DB,0x7255,0xC673,0x719E,0xC50D,0x70E3,0xC3A9,0x7023,0xC248,0x6F5F,0xC0E9, +0x6E97,0xBF8C,0x6DCA,0xBE32,0x6CF9,0xBCDA,0x6C24,0xBB85,0x6B4B,0xBA33,0x6A6E, +0xB8E3,0x698C,0xB796,0x68A7,0xB64C,0x67BD,0xB505,0x66D0,0xB3C0,0x65DE,0xB27F, +0x64E9,0xB140,0x63EF,0xB005,0x62F2,0xAECC,0x61F1,0xAD97,0x60EC,0xAC65,0x5FE4, +0xAB36,0x5ED7,0xAA0A,0x5DC8,0xA8E2,0x5CB4,0xA7BD,0x5B9D,0xA69C,0x5A82,0xA57E, +0x5964,0xA463,0x5843,0xA34C,0x571E,0xA238,0x55F6,0xA129,0x54CA,0xA01C,0x539B, +0x9F14,0x5269,0x9E0F,0x5134,0x9D0E,0x4FFB,0x9C11,0x4EC0,0x9B17,0x4D81,0x9A22, +0x4C40,0x9930,0x4AFB,0x9843,0x49B4,0x9759,0x486A,0x9674,0x471D,0x9592,0x45CD, +0x94B5,0x447B,0x93DC,0x4326,0x9307,0x41CE,0x9236,0x4074,0x9169,0x3F17,0x90A1, +0x3DB8,0x8FDD,0x3C57,0x8F1D,0x3AF3,0x8E62,0x398D,0x8DAB,0x3825,0x8CF8,0x36BA, +0x8C4A,0x354E,0x8BA0,0x33DF,0x8AFB,0x326E,0x8A5A,0x30FC,0x89BE,0x2F87,0x8927, +0x2E11,0x8894,0x2C99,0x8805,0x2B1F,0x877B,0x29A4,0x86F6,0x2827,0x8676,0x26A8, +0x85FA,0x2528,0x8583,0x23A7,0x8511,0x2224,0x84A3,0x209F,0x843A,0x1F1A,0x83D6, +0x1D93,0x8377,0x1C0C,0x831C,0x1A83,0x82C6,0x18F9,0x8276,0x176E,0x822A,0x15E2, +0x81E2,0x1455,0x81A0,0x12C8,0x8163,0x113A,0x812A,0x0FAB,0x80F6,0x0E1C,0x80C8, +0x0C8C,0x809E,0x0AFB,0x8079,0x096B,0x8059,0x07D9,0x803E,0x0648,0x8027,0x04B6, +0x8016,0x0324,0x800A,0x0192,0x8002,0x0000,0x8000,0xFE6E,0x8002,0xFCDC,0x800A, +0xFB4A,0x8016,0xF9B8,0x8027,0xF827,0x803E,0xF695,0x8059,0xF505,0x8079,0xF374, +0x809E,0xF1E4,0x80C8,0xF055,0x80F6,0xEEC6,0x812A,0xED38,0x8163,0xEBAB,0x81A0, +0xEA1E,0x81E2,0xE892,0x822A,0xE707,0x8276,0xE57D,0x82C6,0xE3F4,0x831C,0xE26D, +0x8377,0xE0E6,0x83D6,0xDF61,0x843A,0xDDDC,0x84A3,0xDC59,0x8511,0xDAD8,0x8583, +0xD958,0x85FA,0xD7D9,0x8676,0xD65C,0x86F6,0xD4E1,0x877B,0xD367,0x8805,0xD1EF, +0x8894,0xD079,0x8927,0xCF04,0x89BE,0xCD92,0x8A5A,0xCC21,0x8AFB,0xCAB2,0x8BA0, +0xC946,0x8C4A,0xC7DB,0x8CF8,0xC673,0x8DAB,0xC50D,0x8E62,0xC3A9,0x8F1D,0xC248, +0x8FDD,0xC0E9,0x90A1,0xBF8C,0x9169,0xBE32,0x9236,0xBCDA,0x9307,0xBB85,0x93DC, +0xBA33,0x94B5,0xB8E3,0x9592,0xB796,0x9674,0xB64C,0x9759,0xB505,0x9843,0xB3C0, +0x9930,0xB27F,0x9A22,0xB140,0x9B17,0xB005,0x9C11,0xAECC,0x9D0E,0xAD97,0x9E0F, +0xAC65,0x9F14,0xAB36,0xA01C,0xAA0A,0xA129,0xA8E2,0xA238,0xA7BD,0xA34C,0xA69C, +0xA463,0xA57E,0xA57E,0xA463,0xA69C,0xA34C,0xA7BD,0xA238,0xA8E2,0xA129,0xAA0A, +0xA01C,0xAB36,0x9F14,0xAC65,0x9E0F,0xAD97,0x9D0E,0xAECC,0x9C11,0xB005,0x9B17, +0xB140,0x9A22,0xB27F,0x9930,0xB3C0,0x9843,0xB505,0x9759,0xB64C,0x9674,0xB796, +0x9592,0xB8E3,0x94B5,0xBA33,0x93DC,0xBB85,0x9307,0xBCDA,0x9236,0xBE32,0x9169, +0xBF8C,0x90A1,0xC0E9,0x8FDD,0xC248,0x8F1D,0xC3A9,0x8E62,0xC50D,0x8DAB,0xC673, +0x8CF8,0xC7DB,0x8C4A,0xC946,0x8BA0,0xCAB2,0x8AFB,0xCC21,0x8A5A,0xCD92,0x89BE, +0xCF04,0x8927,0xD079,0x8894,0xD1EF,0x8805,0xD367,0x877B,0xD4E1,0x86F6,0xD65C, +0x8676,0xD7D9,0x85FA,0xD958,0x8583,0xDAD8,0x8511,0xDC59,0x84A3,0xDDDC,0x843A, +0xDF61,0x83D6,0xE0E6,0x8377,0xE26D,0x831C,0xE3F4,0x82C6,0xE57D,0x8276,0xE707, +0x822A,0xE892,0x81E2,0xEA1E,0x81A0,0xEBAB,0x8163,0xED38,0x812A,0xEEC6,0x80F6, +0xF055,0x80C8,0xF1E4,0x809E,0xF374,0x8079,0xF505,0x8059,0xF695,0x803E,0xF827, +0x8027,0xF9B8,0x8016,0xFB4A,0x800A,0xFCDC,0x8002,0xFE6E,0x7FFF,0x0000,0x7FD9, +0xF9B8,0x7F62,0xF374,0x7E9D,0xED38,0x7D8A,0xE707,0x7C2A,0xE0E6,0x7A7D,0xDAD8, +0x7885,0xD4E1,0x7642,0xCF04,0x73B6,0xC946,0x70E3,0xC3A9,0x6DCA,0xBE32,0x6A6E, +0xB8E3,0x66D0,0xB3C0,0x62F2,0xAECC,0x5ED7,0xAA0A,0x5A82,0xA57E,0x55F6,0xA129, +0x5134,0x9D0E,0x4C40,0x9930,0x471D,0x9592,0x41CE,0x9236,0x3C57,0x8F1D,0x36BA, +0x8C4A,0x30FC,0x89BE,0x2B1F,0x877B,0x2528,0x8583,0x1F1A,0x83D6,0x18F9,0x8276, +0x12C8,0x8163,0x0C8C,0x809E,0x0648,0x8027,0x0000,0x8000,0xF9B8,0x8027,0xF374, +0x809E,0xED38,0x8163,0xE707,0x8276,0xE0E6,0x83D6,0xDAD8,0x8583,0xD4E1,0x877B, +0xCF04,0x89BE,0xC946,0x8C4A,0xC3A9,0x8F1D,0xBE32,0x9236,0xB8E3,0x9592,0xB3C0, +0x9930,0xAECC,0x9D0E,0xAA0A,0xA129,0xA57E,0xA57E,0xA129,0xAA0A,0x9D0E,0xAECC, +0x9930,0xB3C0,0x9592,0xB8E3,0x9236,0xBE32,0x8F1D,0xC3A9,0x8C4A,0xC946,0x89BE, +0xCF04,0x877B,0xD4E1,0x8583,0xDAD8,0x83D6,0xE0E6,0x8276,0xE707,0x8163,0xED38, +0x809E,0xF374,0x8027,0xF9B8,0x7FFF,0x0000,0x7D8A,0xE707,0x7642,0xCF04,0x6A6E, +0xB8E3,0x5A82,0xA57E,0x471D,0x9592,0x30FC,0x89BE,0x18F9,0x8276,0x0000,0x8000, +0xE707,0x8276,0xCF04,0x89BE,0xB8E3,0x9592,0xA57E,0xA57E,0x9592,0xB8E3,0x89BE, +0xCF04,0x8276,0xE707,0x7FFF,0x0000,0x5A82,0xA57E,0x0000,0x8000,0xA57E,0xA57E,}; + +q15_t rearranged_twiddle_stride3_4096_q15[2728]={ +0x7FFF,0x0000,0x7FFF,0xFF69,0x7FFF,0xFED2,0x7FFD,0xFE3C,0x7FFA,0xFDA5,0x7FF7, +0xFD0E,0x7FF4,0xFC77,0x7FEF,0xFBE1,0x7FEA,0xFB4A,0x7FE4,0xFAB3,0x7FDD,0xFA1D, +0x7FD6,0xF986,0x7FCE,0xF8EF,0x7FC5,0xF859,0x7FBC,0xF7C2,0x7FB2,0xF72C,0x7FA7, +0xF695,0x7F9C,0xF5FF,0x7F90,0xF569,0x7F83,0xF4D3,0x7F75,0xF43C,0x7F67,0xF3A6, +0x7F58,0xF310,0x7F49,0xF27A,0x7F38,0xF1E4,0x7F27,0xF14E,0x7F16,0xF0B9,0x7F03, +0xF023,0x7EF0,0xEF8D,0x7EDD,0xEEF8,0x7EC8,0xEE62,0x7EB3,0xEDCD,0x7E9D,0xED38, +0x7E87,0xECA3,0x7E70,0xEC0E,0x7E58,0xEB79,0x7E3F,0xEAE4,0x7E26,0xEA4F,0x7E0C, +0xE9BB,0x7DF2,0xE926,0x7DD6,0xE892,0x7DBA,0xE7FE,0x7D9E,0xE76A,0x7D81,0xE6D6, +0x7D63,0xE642,0x7D44,0xE5AF,0x7D25,0xE51B,0x7D05,0xE488,0x7CE4,0xE3F4,0x7CC2, +0xE361,0x7CA0,0xE2CF,0x7C7E,0xE23C,0x7C5A,0xE1A9,0x7C36,0xE117,0x7C11,0xE085, +0x7BEC,0xDFF2,0x7BC6,0xDF61,0x7B9F,0xDECF,0x7B78,0xDE3D,0x7B50,0xDDAC,0x7B27, +0xDD1B,0x7AFD,0xDC8A,0x7AD3,0xDBF9,0x7AA8,0xDB68,0x7A7D,0xDAD8,0x7A51,0xDA48, +0x7A24,0xD9B8,0x79F7,0xD928,0x79C9,0xD898,0x799A,0xD809,0x796A,0xD77A,0x793A, +0xD6EB,0x790A,0xD65C,0x78D8,0xD5CE,0x78A6,0xD53F,0x7874,0xD4B1,0x7840,0xD424, +0x780C,0xD396,0x77D8,0xD309,0x77A2,0xD27C,0x776C,0xD1EF,0x7736,0xD162,0x76FE, +0xD0D6,0x76C7,0xD04A,0x768E,0xCFBE,0x7655,0xCF33,0x761B,0xCEA7,0x75E1,0xCE1C, +0x75A6,0xCD92,0x756A,0xCD07,0x752D,0xCC7D,0x74F0,0xCBF3,0x74B3,0xCB69,0x7475, +0xCAE0,0x7436,0xCA57,0x73F6,0xC9CE,0x73B6,0xC946,0x7375,0xC8BE,0x7334,0xC836, +0x72F2,0xC7AE,0x72AF,0xC727,0x726C,0xC6A0,0x7228,0xC619,0x71E3,0xC593,0x719E, +0xC50D,0x7158,0xC487,0x7112,0xC402,0x70CB,0xC37D,0x7083,0xC2F8,0x703B,0xC274, +0x6FF2,0xC1F0,0x6FA9,0xC16C,0x6F5F,0xC0E9,0x6F14,0xC066,0x6EC9,0xBFE3,0x6E7D, +0xBF61,0x6E31,0xBEDF,0x6DE4,0xBE5D,0x6D96,0xBDDC,0x6D48,0xBD5B,0x6CF9,0xBCDA, +0x6CAA,0xBC5A,0x6C5A,0xBBDA,0x6C09,0xBB5B,0x6BB8,0xBADC,0x6B66,0xBA5D,0x6B14, +0xB9DF,0x6AC1,0xB961,0x6A6E,0xB8E3,0x6A1A,0xB866,0x69C5,0xB7E9,0x6970,0xB76D, +0x691A,0xB6F1,0x68C4,0xB675,0x686D,0xB5FA,0x6815,0xB57F,0x67BD,0xB505,0x6764, +0xB48B,0x670B,0xB411,0x66B2,0xB398,0x6657,0xB31F,0x65FC,0xB2A7,0x65A1,0xB22F, +0x6545,0xB1B7,0x64E9,0xB140,0x648B,0xB0C9,0x642E,0xB053,0x63D0,0xAFDD,0x6371, +0xAF68,0x6312,0xAEF3,0x62B2,0xAE7F,0x6252,0xAE0B,0x61F1,0xAD97,0x6190,0xAD24, +0x612E,0xACB1,0x60CB,0xAC3F,0x6068,0xABCD,0x6005,0xAB5C,0x5FA1,0xAAEB,0x5F3C, +0xAA7A,0x5ED7,0xAA0A,0x5E72,0xA99B,0x5E0C,0xA92C,0x5DA5,0xA8BD,0x5D3E,0xA84F, +0x5CD7,0xA7E2,0x5C6F,0xA774,0x5C06,0xA708,0x5B9D,0xA69C,0x5B34,0xA630,0x5AC9, +0xA5C5,0x5A5F,0xA55A,0x59F4,0xA4F0,0x5988,0xA486,0x591C,0xA41D,0x58B0,0xA3B4, +0x5843,0xA34C,0x57D5,0xA2E4,0x5767,0xA27D,0x56F9,0xA216,0x568A,0xA1B0,0x561B, +0xA14A,0x55AB,0xA0E5,0x553B,0xA080,0x54CA,0xA01C,0x5459,0x9FB9,0x53E7,0x9F56, +0x5375,0x9EF3,0x5303,0x9E91,0x5290,0x9E2F,0x521C,0x9DCE,0x51A8,0x9D6E,0x5134, +0x9D0E,0x50BF,0x9CAF,0x504A,0x9C50,0x4FD4,0x9BF1,0x4F5E,0x9B94,0x4EE8,0x9B36, +0x4E71,0x9ADA,0x4DF9,0x9A7E,0x4D81,0x9A22,0x4D09,0x99C7,0x4C91,0x996D,0x4C17, +0x9913,0x4B9E,0x98B9,0x4B24,0x9860,0x4AAA,0x9808,0x4A2F,0x97B0,0x49B4,0x9759, +0x4939,0x9703,0x48BD,0x96AD,0x4840,0x9657,0x47C4,0x9603,0x4747,0x95AE,0x46C9, +0x955B,0x464B,0x9508,0x45CD,0x94B5,0x454F,0x9463,0x44D0,0x9412,0x4450,0x93C1, +0x43D1,0x9371,0x4351,0x9321,0x42D0,0x92D2,0x424F,0x9284,0x41CE,0x9236,0x414D, +0x91E9,0x40CB,0x919C,0x4048,0x9150,0x3FC6,0x9105,0x3F43,0x90BA,0x3EC0,0x9070, +0x3E3C,0x9026,0x3DB8,0x8FDD,0x3D34,0x8F95,0x3CAF,0x8F4D,0x3C2A,0x8F06,0x3BA5, +0x8EBF,0x3B20,0x8E79,0x3A9A,0x8E34,0x3A13,0x8DEF,0x398D,0x8DAB,0x3906,0x8D67, +0x387F,0x8D24,0x37F7,0x8CE2,0x3770,0x8CA1,0x36E8,0x8C60,0x365F,0x8C1F,0x35D7, +0x8BDF,0x354E,0x8BA0,0x34C4,0x8B62,0x343B,0x8B24,0x33B1,0x8AE7,0x3327,0x8AAA, +0x329D,0x8A6E,0x3212,0x8A33,0x3187,0x89F8,0x30FC,0x89BE,0x3070,0x8985,0x2FE5, +0x894C,0x2F59,0x8914,0x2ECC,0x88DD,0x2E40,0x88A6,0x2DB3,0x8870,0x2D26,0x883A, +0x2C99,0x8805,0x2C0C,0x87D1,0x2B7E,0x879D,0x2AF0,0x876B,0x2A62,0x8738,0x29D3, +0x8707,0x2945,0x86D6,0x28B6,0x86A5,0x2827,0x8676,0x2797,0x8647,0x2708,0x8619, +0x2678,0x85EB,0x25E8,0x85BE,0x2558,0x8592,0x24C8,0x8566,0x2437,0x853B,0x23A7, +0x8511,0x2316,0x84E7,0x2284,0x84BE,0x21F3,0x8496,0x2162,0x846E,0x20D0,0x8447, +0x203E,0x8421,0x1FAC,0x83FB,0x1F1A,0x83D6,0x1E88,0x83B2,0x1DF5,0x838E,0x1D62, +0x836B,0x1CD0,0x8349,0x1C3D,0x8327,0x1BA9,0x8306,0x1B16,0x82E6,0x1A83,0x82C6, +0x19EF,0x82A8,0x195B,0x8289,0x18C7,0x826C,0x1833,0x824F,0x179F,0x8233,0x170B, +0x8217,0x1677,0x81FD,0x15E2,0x81E2,0x154D,0x81C9,0x14B9,0x81B0,0x1424,0x8198, +0x138F,0x8181,0x12FA,0x816A,0x1265,0x8154,0x11CF,0x813F,0x113A,0x812A,0x10A4, +0x8116,0x100F,0x8103,0x0F79,0x80F0,0x0EE4,0x80DE,0x0E4E,0x80CD,0x0DB8,0x80BD, +0x0D22,0x80AD,0x0C8C,0x809E,0x0BF6,0x808F,0x0B60,0x8082,0x0AC9,0x8075,0x0A33, +0x8068,0x099D,0x805D,0x0906,0x8052,0x0870,0x8047,0x07D9,0x803E,0x0743,0x8035, +0x06AC,0x802D,0x0616,0x8025,0x057F,0x801E,0x04E8,0x8018,0x0452,0x8013,0x03BB, +0x800E,0x0324,0x800A,0x028D,0x8007,0x01F7,0x8004,0x0160,0x8002,0x00C9,0x8001, +0x0032,0x8000,0xFF9B,0x8000,0xFF05,0x8001,0xFE6E,0x8002,0xFDD7,0x8005,0xFD40, +0x8008,0xFCAA,0x800B,0xFC13,0x800F,0xFB7C,0x8014,0xFAE5,0x801A,0xFA4F,0x8020, +0xF9B8,0x8027,0xF922,0x802F,0xF88B,0x8038,0xF7F4,0x8041,0xF75E,0x804B,0xF6C8, +0x8055,0xF631,0x8060,0xF59B,0x806C,0xF505,0x8079,0xF46E,0x8086,0xF3D8,0x8094, +0xF342,0x80A3,0xF2AC,0x80B2,0xF216,0x80C2,0xF180,0x80D3,0xF0EB,0x80E4,0xF055, +0x80F6,0xEFBF,0x8109,0xEF2A,0x811D,0xEE94,0x8131,0xEDFF,0x8146,0xED6A,0x815B, +0xECD5,0x8172,0xEC3F,0x8188,0xEBAB,0x81A0,0xEB16,0x81B8,0xEA81,0x81D1,0xE9EC, +0x81EB,0xE958,0x8205,0xE8C4,0x8220,0xE82F,0x823C,0xE79B,0x8259,0xE707,0x8276, +0xE673,0x8293,0xE5E0,0x82B2,0xE54C,0x82D1,0xE4B9,0x82F1,0xE426,0x8311,0xE392, +0x8332,0xE2FF,0x8354,0xE26D,0x8377,0xE1DA,0x839A,0xE148,0x83BE,0xE0B5,0x83E2, +0xE023,0x8407,0xDF91,0x842D,0xDEFF,0x8454,0xDE6E,0x847B,0xDDDC,0x84A3,0xDD4B, +0x84CC,0xDCBA,0x84F5,0xDC29,0x851F,0xDB99,0x8549,0xDB08,0x8574,0xDA78,0x85A0, +0xD9E8,0x85CD,0xD958,0x85FA,0xD8C8,0x8628,0xD839,0x8656,0xD7AA,0x8686,0xD71B, +0x86B6,0xD68C,0x86E6,0xD5FD,0x8717,0xD56F,0x8749,0xD4E1,0x877B,0xD453,0x87AF, +0xD3C5,0x87E2,0xD338,0x8817,0xD2AB,0x884C,0xD21E,0x8882,0xD191,0x88B8,0xD105, +0x88EF,0xD079,0x8927,0xCFED,0x895F,0xCF61,0x8998,0xCED6,0x89D2,0xCE4B,0x8A0C, +0xCDC0,0x8A47,0xCD35,0x8A82,0xCCAB,0x8ABE,0xCC21,0x8AFB,0xCB97,0x8B39,0xCB0E, +0x8B77,0xCA85,0x8BB5,0xC9FC,0x8BF5,0xC973,0x8C35,0xC8EB,0x8C75,0xC863,0x8CB6, +0xC7DB,0x8CF8,0xC754,0x8D3B,0xC6CD,0x8D7E,0xC646,0x8DC1,0xC5C0,0x8E06,0xC53A, +0x8E4B,0xC4B4,0x8E90,0xC42E,0x8ED6,0xC3A9,0x8F1D,0xC324,0x8F65,0xC2A0,0x8FAD, +0xC21C,0x8FF5,0xC198,0x903E,0xC114,0x9088,0xC091,0x90D3,0xC00F,0x911E,0xBF8C, +0x9169,0xBF0A,0x91B6,0xBE88,0x9202,0xBE07,0x9250,0xBD86,0x929E,0xBD05,0x92EC, +0xBC85,0x933C,0xBC05,0x938B,0xBB85,0x93DC,0xBB06,0x942D,0xBA87,0x947E,0xBA09, +0x94D0,0xB98B,0x9523,0xB90D,0x9577,0xB890,0x95CA,0xB813,0x961F,0xB796,0x9674, +0xB71A,0x96C9,0xB69E,0x9720,0xB623,0x9776,0xB5A8,0x97CE,0xB52D,0x9826,0xB4B3, +0x987E,0xB439,0x98D7,0xB3C0,0x9930,0xB347,0x998B,0xB2CF,0x99E5,0xB257,0x9A40, +0xB1DF,0x9A9C,0xB168,0x9AF9,0xB0F1,0x9B55,0xB07B,0x9BB3,0xB005,0x9C11,0xAF8F, +0x9C6F,0xAF1A,0x9CCE,0xAEA5,0x9D2E,0xAE31,0x9D8E,0xADBD,0x9DEF,0xAD4A,0x9E50, +0xACD7,0x9EB2,0xAC65,0x9F14,0xABF3,0x9F77,0xAB81,0x9FDA,0xAB10,0xA03E,0xAAA0, +0xA0A2,0xAA30,0xA107,0xA9C0,0xA16C,0xA951,0xA1D2,0xA8E2,0xA238,0xA874,0xA29F, +0xA806,0xA307,0xA799,0xA36F,0xA72C,0xA3D7,0xA6C0,0xA440,0xA654,0xA4A9,0xA5E8, +0xA513,0xA57E,0xA57E,0xA513,0xA5E8,0xA4A9,0xA654,0xA440,0xA6C0,0xA3D7,0xA72C, +0xA36F,0xA799,0xA307,0xA806,0xA29F,0xA874,0xA238,0xA8E2,0xA1D2,0xA951,0xA16C, +0xA9C0,0xA107,0xAA30,0xA0A2,0xAAA0,0xA03E,0xAB10,0x9FDA,0xAB81,0x9F77,0xABF3, +0x9F14,0xAC65,0x9EB2,0xACD7,0x9E50,0xAD4A,0x9DEF,0xADBD,0x9D8E,0xAE31,0x9D2E, +0xAEA5,0x9CCE,0xAF1A,0x9C6F,0xAF8F,0x9C11,0xB005,0x9BB3,0xB07B,0x9B55,0xB0F1, +0x9AF9,0xB168,0x9A9C,0xB1DF,0x9A40,0xB257,0x99E5,0xB2CF,0x998B,0xB347,0x9930, +0xB3C0,0x98D7,0xB439,0x987E,0xB4B3,0x9826,0xB52D,0x97CE,0xB5A8,0x9776,0xB623, +0x9720,0xB69E,0x96C9,0xB71A,0x9674,0xB796,0x961F,0xB813,0x95CA,0xB890,0x9577, +0xB90D,0x9523,0xB98B,0x94D0,0xBA09,0x947E,0xBA87,0x942D,0xBB06,0x93DC,0xBB85, +0x938B,0xBC05,0x933C,0xBC85,0x92EC,0xBD05,0x929E,0xBD86,0x9250,0xBE07,0x9202, +0xBE88,0x91B6,0xBF0A,0x9169,0xBF8C,0x911E,0xC00F,0x90D3,0xC091,0x9088,0xC114, +0x903E,0xC198,0x8FF5,0xC21C,0x8FAD,0xC2A0,0x8F65,0xC324,0x8F1D,0xC3A9,0x8ED6, +0xC42E,0x8E90,0xC4B4,0x8E4B,0xC53A,0x8E06,0xC5C0,0x8DC1,0xC646,0x8D7E,0xC6CD, +0x8D3B,0xC754,0x8CF8,0xC7DB,0x8CB6,0xC863,0x8C75,0xC8EB,0x8C35,0xC973,0x8BF5, +0xC9FC,0x8BB5,0xCA85,0x8B77,0xCB0E,0x8B39,0xCB97,0x8AFB,0xCC21,0x8ABE,0xCCAB, +0x8A82,0xCD35,0x8A47,0xCDC0,0x8A0C,0xCE4B,0x89D2,0xCED6,0x8998,0xCF61,0x895F, +0xCFED,0x8927,0xD079,0x88EF,0xD105,0x88B8,0xD191,0x8882,0xD21E,0x884C,0xD2AB, +0x8817,0xD338,0x87E2,0xD3C5,0x87AF,0xD453,0x877B,0xD4E1,0x8749,0xD56F,0x8717, +0xD5FD,0x86E6,0xD68C,0x86B6,0xD71B,0x8686,0xD7AA,0x8656,0xD839,0x8628,0xD8C8, +0x85FA,0xD958,0x85CD,0xD9E8,0x85A0,0xDA78,0x8574,0xDB08,0x8549,0xDB99,0x851F, +0xDC29,0x84F5,0xDCBA,0x84CC,0xDD4B,0x84A3,0xDDDC,0x847B,0xDE6E,0x8454,0xDEFF, +0x842D,0xDF91,0x8407,0xE023,0x83E2,0xE0B5,0x83BE,0xE148,0x839A,0xE1DA,0x8377, +0xE26D,0x8354,0xE2FF,0x8332,0xE392,0x8311,0xE426,0x82F1,0xE4B9,0x82D1,0xE54C, +0x82B2,0xE5E0,0x8293,0xE673,0x8276,0xE707,0x8259,0xE79B,0x823C,0xE82F,0x8220, +0xE8C4,0x8205,0xE958,0x81EB,0xE9EC,0x81D1,0xEA81,0x81B8,0xEB16,0x81A0,0xEBAB, +0x8188,0xEC3F,0x8172,0xECD5,0x815B,0xED6A,0x8146,0xEDFF,0x8131,0xEE94,0x811D, +0xEF2A,0x8109,0xEFBF,0x80F6,0xF055,0x80E4,0xF0EB,0x80D3,0xF180,0x80C2,0xF216, +0x80B2,0xF2AC,0x80A3,0xF342,0x8094,0xF3D8,0x8086,0xF46E,0x8079,0xF505,0x806C, +0xF59B,0x8060,0xF631,0x8055,0xF6C8,0x804B,0xF75E,0x8041,0xF7F4,0x8038,0xF88B, +0x802F,0xF922,0x8027,0xF9B8,0x8020,0xFA4F,0x801A,0xFAE5,0x8014,0xFB7C,0x800F, +0xFC13,0x800B,0xFCAA,0x8008,0xFD40,0x8005,0xFDD7,0x8002,0xFE6E,0x8001,0xFF05, +0x8000,0xFF9B,0x8000,0x0032,0x8001,0x00C9,0x8002,0x0160,0x8004,0x01F7,0x8007, +0x028D,0x800A,0x0324,0x800E,0x03BB,0x8013,0x0452,0x8018,0x04E8,0x801E,0x057F, +0x8025,0x0616,0x802D,0x06AC,0x8035,0x0743,0x803E,0x07D9,0x8047,0x0870,0x8052, +0x0906,0x805D,0x099D,0x8068,0x0A33,0x8075,0x0AC9,0x8082,0x0B60,0x808F,0x0BF6, +0x809E,0x0C8C,0x80AD,0x0D22,0x80BD,0x0DB8,0x80CD,0x0E4E,0x80DE,0x0EE4,0x80F0, +0x0F79,0x8103,0x100F,0x8116,0x10A4,0x812A,0x113A,0x813F,0x11CF,0x8154,0x1265, +0x816A,0x12FA,0x8181,0x138F,0x8198,0x1424,0x81B0,0x14B9,0x81C9,0x154D,0x81E2, +0x15E2,0x81FD,0x1677,0x8217,0x170B,0x8233,0x179F,0x824F,0x1833,0x826C,0x18C7, +0x8289,0x195B,0x82A8,0x19EF,0x82C6,0x1A83,0x82E6,0x1B16,0x8306,0x1BA9,0x8327, +0x1C3D,0x8349,0x1CD0,0x836B,0x1D62,0x838E,0x1DF5,0x83B2,0x1E88,0x83D6,0x1F1A, +0x83FB,0x1FAC,0x8421,0x203E,0x8447,0x20D0,0x846E,0x2162,0x8496,0x21F3,0x84BE, +0x2284,0x84E7,0x2316,0x8511,0x23A7,0x853B,0x2437,0x8566,0x24C8,0x8592,0x2558, +0x85BE,0x25E8,0x85EB,0x2678,0x8619,0x2708,0x8647,0x2797,0x8676,0x2827,0x86A5, +0x28B6,0x86D6,0x2945,0x8707,0x29D3,0x8738,0x2A62,0x876B,0x2AF0,0x879D,0x2B7E, +0x87D1,0x2C0C,0x8805,0x2C99,0x883A,0x2D26,0x8870,0x2DB3,0x88A6,0x2E40,0x88DD, +0x2ECC,0x8914,0x2F59,0x894C,0x2FE5,0x8985,0x3070,0x89BE,0x30FC,0x89F8,0x3187, +0x8A33,0x3212,0x8A6E,0x329D,0x8AAA,0x3327,0x8AE7,0x33B1,0x8B24,0x343B,0x8B62, +0x34C4,0x8BA0,0x354E,0x8BDF,0x35D7,0x8C1F,0x365F,0x8C60,0x36E8,0x8CA1,0x3770, +0x8CE2,0x37F7,0x8D24,0x387F,0x8D67,0x3906,0x8DAB,0x398D,0x8DEF,0x3A13,0x8E34, +0x3A9A,0x8E79,0x3B20,0x8EBF,0x3BA5,0x8F06,0x3C2A,0x8F4D,0x3CAF,0x8F95,0x3D34, +0x8FDD,0x3DB8,0x9026,0x3E3C,0x9070,0x3EC0,0x90BA,0x3F43,0x9105,0x3FC6,0x9150, +0x4048,0x919C,0x40CB,0x91E9,0x414D,0x9236,0x41CE,0x9284,0x424F,0x92D2,0x42D0, +0x9321,0x4351,0x9371,0x43D1,0x93C1,0x4450,0x9412,0x44D0,0x9463,0x454F,0x94B5, +0x45CD,0x9508,0x464B,0x955B,0x46C9,0x95AE,0x4747,0x9603,0x47C4,0x9657,0x4840, +0x96AD,0x48BD,0x9703,0x4939,0x9759,0x49B4,0x97B0,0x4A2F,0x9808,0x4AAA,0x9860, +0x4B24,0x98B9,0x4B9E,0x9913,0x4C17,0x996D,0x4C91,0x99C7,0x4D09,0x9A22,0x4D81, +0x9A7E,0x4DF9,0x9ADA,0x4E71,0x9B36,0x4EE8,0x9B94,0x4F5E,0x9BF1,0x4FD4,0x9C50, +0x504A,0x9CAF,0x50BF,0x9D0E,0x5134,0x9D6E,0x51A8,0x9DCE,0x521C,0x9E2F,0x5290, +0x9E91,0x5303,0x9EF3,0x5375,0x9F56,0x53E7,0x9FB9,0x5459,0xA01C,0x54CA,0xA080, +0x553B,0xA0E5,0x55AB,0xA14A,0x561B,0xA1B0,0x568A,0xA216,0x56F9,0xA27D,0x5767, +0xA2E4,0x57D5,0xA34C,0x5843,0xA3B4,0x58B0,0xA41D,0x591C,0xA486,0x5988,0xA4F0, +0x59F4,0xA55A,0x5A5F,0xA5C5,0x5AC9,0xA630,0x5B34,0xA69C,0x5B9D,0xA708,0x5C06, +0xA774,0x5C6F,0xA7E2,0x5CD7,0xA84F,0x5D3E,0xA8BD,0x5DA5,0xA92C,0x5E0C,0xA99B, +0x5E72,0xAA0A,0x5ED7,0xAA7A,0x5F3C,0xAAEB,0x5FA1,0xAB5C,0x6005,0xABCD,0x6068, +0xAC3F,0x60CB,0xACB1,0x612E,0xAD24,0x6190,0xAD97,0x61F1,0xAE0B,0x6252,0xAE7F, +0x62B2,0xAEF3,0x6312,0xAF68,0x6371,0xAFDD,0x63D0,0xB053,0x642E,0xB0C9,0x648B, +0xB140,0x64E9,0xB1B7,0x6545,0xB22F,0x65A1,0xB2A7,0x65FC,0xB31F,0x6657,0xB398, +0x66B2,0xB411,0x670B,0xB48B,0x6764,0xB505,0x67BD,0xB57F,0x6815,0xB5FA,0x686D, +0xB675,0x68C4,0xB6F1,0x691A,0xB76D,0x6970,0xB7E9,0x69C5,0xB866,0x6A1A,0xB8E3, +0x6A6E,0xB961,0x6AC1,0xB9DF,0x6B14,0xBA5D,0x6B66,0xBADC,0x6BB8,0xBB5B,0x6C09, +0xBBDA,0x6C5A,0xBC5A,0x6CAA,0xBCDA,0x6CF9,0xBD5B,0x6D48,0xBDDC,0x6D96,0xBE5D, +0x6DE4,0xBEDF,0x6E31,0xBF61,0x6E7D,0xBFE3,0x6EC9,0xC066,0x6F14,0xC0E9,0x6F5F, +0xC16C,0x6FA9,0xC1F0,0x6FF2,0xC274,0x703B,0xC2F8,0x7083,0xC37D,0x70CB,0xC402, +0x7112,0xC487,0x7158,0xC50D,0x719E,0xC593,0x71E3,0xC619,0x7228,0xC6A0,0x726C, +0xC727,0x72AF,0xC7AE,0x72F2,0xC836,0x7334,0xC8BE,0x7375,0xC946,0x73B6,0xC9CE, +0x73F6,0xCA57,0x7436,0xCAE0,0x7475,0xCB69,0x74B3,0xCBF3,0x74F0,0xCC7D,0x752D, +0xCD07,0x756A,0xCD92,0x75A6,0xCE1C,0x75E1,0xCEA7,0x761B,0xCF33,0x7655,0xCFBE, +0x768E,0xD04A,0x76C7,0xD0D6,0x76FE,0xD162,0x7736,0xD1EF,0x776C,0xD27C,0x77A2, +0xD309,0x77D8,0xD396,0x780C,0xD424,0x7840,0xD4B1,0x7874,0xD53F,0x78A6,0xD5CE, +0x78D8,0xD65C,0x790A,0xD6EB,0x793A,0xD77A,0x796A,0xD809,0x799A,0xD898,0x79C9, +0xD928,0x79F7,0xD9B8,0x7A24,0xDA48,0x7A51,0xDAD8,0x7A7D,0xDB68,0x7AA8,0xDBF9, +0x7AD3,0xDC8A,0x7AFD,0xDD1B,0x7B27,0xDDAC,0x7B50,0xDE3D,0x7B78,0xDECF,0x7B9F, +0xDF61,0x7BC6,0xDFF2,0x7BEC,0xE085,0x7C11,0xE117,0x7C36,0xE1A9,0x7C5A,0xE23C, +0x7C7E,0xE2CF,0x7CA0,0xE361,0x7CC2,0xE3F4,0x7CE4,0xE488,0x7D05,0xE51B,0x7D25, +0xE5AF,0x7D44,0xE642,0x7D63,0xE6D6,0x7D81,0xE76A,0x7D9E,0xE7FE,0x7DBA,0xE892, +0x7DD6,0xE926,0x7DF2,0xE9BB,0x7E0C,0xEA4F,0x7E26,0xEAE4,0x7E3F,0xEB79,0x7E58, +0xEC0E,0x7E70,0xECA3,0x7E87,0xED38,0x7E9D,0xEDCD,0x7EB3,0xEE62,0x7EC8,0xEEF8, +0x7EDD,0xEF8D,0x7EF0,0xF023,0x7F03,0xF0B9,0x7F16,0xF14E,0x7F27,0xF1E4,0x7F38, +0xF27A,0x7F49,0xF310,0x7F58,0xF3A6,0x7F67,0xF43C,0x7F75,0xF4D3,0x7F83,0xF569, +0x7F90,0xF5FF,0x7F9C,0xF695,0x7FA7,0xF72C,0x7FB2,0xF7C2,0x7FBC,0xF859,0x7FC5, +0xF8EF,0x7FCE,0xF986,0x7FD6,0xFA1D,0x7FDD,0xFAB3,0x7FE4,0xFB4A,0x7FEA,0xFBE1, +0x7FEF,0xFC77,0x7FF4,0xFD0E,0x7FF7,0xFDA5,0x7FFA,0xFE3C,0x7FFD,0xFED2,0x7FFF, +0xFF69,0x7FFF,0x7FFF,0x0000,0x7FFA,0xFDA5,0x7FEA,0xFB4A,0x7FCE,0xF8EF,0x7FA7, +0xF695,0x7F75,0xF43C,0x7F38,0xF1E4,0x7EF0,0xEF8D,0x7E9D,0xED38,0x7E3F,0xEAE4, +0x7DD6,0xE892,0x7D63,0xE642,0x7CE4,0xE3F4,0x7C5A,0xE1A9,0x7BC6,0xDF61,0x7B27, +0xDD1B,0x7A7D,0xDAD8,0x79C9,0xD898,0x790A,0xD65C,0x7840,0xD424,0x776C,0xD1EF, +0x768E,0xCFBE,0x75A6,0xCD92,0x74B3,0xCB69,0x73B6,0xC946,0x72AF,0xC727,0x719E, +0xC50D,0x7083,0xC2F8,0x6F5F,0xC0E9,0x6E31,0xBEDF,0x6CF9,0xBCDA,0x6BB8,0xBADC, +0x6A6E,0xB8E3,0x691A,0xB6F1,0x67BD,0xB505,0x6657,0xB31F,0x64E9,0xB140,0x6371, +0xAF68,0x61F1,0xAD97,0x6068,0xABCD,0x5ED7,0xAA0A,0x5D3E,0xA84F,0x5B9D,0xA69C, +0x59F4,0xA4F0,0x5843,0xA34C,0x568A,0xA1B0,0x54CA,0xA01C,0x5303,0x9E91,0x5134, +0x9D0E,0x4F5E,0x9B94,0x4D81,0x9A22,0x4B9E,0x98B9,0x49B4,0x9759,0x47C4,0x9603, +0x45CD,0x94B5,0x43D1,0x9371,0x41CE,0x9236,0x3FC6,0x9105,0x3DB8,0x8FDD,0x3BA5, +0x8EBF,0x398D,0x8DAB,0x3770,0x8CA1,0x354E,0x8BA0,0x3327,0x8AAA,0x30FC,0x89BE, +0x2ECC,0x88DD,0x2C99,0x8805,0x2A62,0x8738,0x2827,0x8676,0x25E8,0x85BE,0x23A7, +0x8511,0x2162,0x846E,0x1F1A,0x83D6,0x1CD0,0x8349,0x1A83,0x82C6,0x1833,0x824F, +0x15E2,0x81E2,0x138F,0x8181,0x113A,0x812A,0x0EE4,0x80DE,0x0C8C,0x809E,0x0A33, +0x8068,0x07D9,0x803E,0x057F,0x801E,0x0324,0x800A,0x00C9,0x8001,0xFE6E,0x8002, +0xFC13,0x800F,0xF9B8,0x8027,0xF75E,0x804B,0xF505,0x8079,0xF2AC,0x80B2,0xF055, +0x80F6,0xEDFF,0x8146,0xEBAB,0x81A0,0xE958,0x8205,0xE707,0x8276,0xE4B9,0x82F1, +0xE26D,0x8377,0xE023,0x8407,0xDDDC,0x84A3,0xDB99,0x8549,0xD958,0x85FA,0xD71B, +0x86B6,0xD4E1,0x877B,0xD2AB,0x884C,0xD079,0x8927,0xCE4B,0x8A0C,0xCC21,0x8AFB, +0xC9FC,0x8BF5,0xC7DB,0x8CF8,0xC5C0,0x8E06,0xC3A9,0x8F1D,0xC198,0x903E,0xBF8C, +0x9169,0xBD86,0x929E,0xBB85,0x93DC,0xB98B,0x9523,0xB796,0x9674,0xB5A8,0x97CE, +0xB3C0,0x9930,0xB1DF,0x9A9C,0xB005,0x9C11,0xAE31,0x9D8E,0xAC65,0x9F14,0xAAA0, +0xA0A2,0xA8E2,0xA238,0xA72C,0xA3D7,0xA57E,0xA57E,0xA3D7,0xA72C,0xA238,0xA8E2, +0xA0A2,0xAAA0,0x9F14,0xAC65,0x9D8E,0xAE31,0x9C11,0xB005,0x9A9C,0xB1DF,0x9930, +0xB3C0,0x97CE,0xB5A8,0x9674,0xB796,0x9523,0xB98B,0x93DC,0xBB85,0x929E,0xBD86, +0x9169,0xBF8C,0x903E,0xC198,0x8F1D,0xC3A9,0x8E06,0xC5C0,0x8CF8,0xC7DB,0x8BF5, +0xC9FC,0x8AFB,0xCC21,0x8A0C,0xCE4B,0x8927,0xD079,0x884C,0xD2AB,0x877B,0xD4E1, +0x86B6,0xD71B,0x85FA,0xD958,0x8549,0xDB99,0x84A3,0xDDDC,0x8407,0xE023,0x8377, +0xE26D,0x82F1,0xE4B9,0x8276,0xE707,0x8205,0xE958,0x81A0,0xEBAB,0x8146,0xEDFF, +0x80F6,0xF055,0x80B2,0xF2AC,0x8079,0xF505,0x804B,0xF75E,0x8027,0xF9B8,0x800F, +0xFC13,0x8002,0xFE6E,0x8001,0x00C9,0x800A,0x0324,0x801E,0x057F,0x803E,0x07D9, +0x8068,0x0A33,0x809E,0x0C8C,0x80DE,0x0EE4,0x812A,0x113A,0x8181,0x138F,0x81E2, +0x15E2,0x824F,0x1833,0x82C6,0x1A83,0x8349,0x1CD0,0x83D6,0x1F1A,0x846E,0x2162, +0x8511,0x23A7,0x85BE,0x25E8,0x8676,0x2827,0x8738,0x2A62,0x8805,0x2C99,0x88DD, +0x2ECC,0x89BE,0x30FC,0x8AAA,0x3327,0x8BA0,0x354E,0x8CA1,0x3770,0x8DAB,0x398D, +0x8EBF,0x3BA5,0x8FDD,0x3DB8,0x9105,0x3FC6,0x9236,0x41CE,0x9371,0x43D1,0x94B5, +0x45CD,0x9603,0x47C4,0x9759,0x49B4,0x98B9,0x4B9E,0x9A22,0x4D81,0x9B94,0x4F5E, +0x9D0E,0x5134,0x9E91,0x5303,0xA01C,0x54CA,0xA1B0,0x568A,0xA34C,0x5843,0xA4F0, +0x59F4,0xA69C,0x5B9D,0xA84F,0x5D3E,0xAA0A,0x5ED7,0xABCD,0x6068,0xAD97,0x61F1, +0xAF68,0x6371,0xB140,0x64E9,0xB31F,0x6657,0xB505,0x67BD,0xB6F1,0x691A,0xB8E3, +0x6A6E,0xBADC,0x6BB8,0xBCDA,0x6CF9,0xBEDF,0x6E31,0xC0E9,0x6F5F,0xC2F8,0x7083, +0xC50D,0x719E,0xC727,0x72AF,0xC946,0x73B6,0xCB69,0x74B3,0xCD92,0x75A6,0xCFBE, +0x768E,0xD1EF,0x776C,0xD424,0x7840,0xD65C,0x790A,0xD898,0x79C9,0xDAD8,0x7A7D, +0xDD1B,0x7B27,0xDF61,0x7BC6,0xE1A9,0x7C5A,0xE3F4,0x7CE4,0xE642,0x7D63,0xE892, +0x7DD6,0xEAE4,0x7E3F,0xED38,0x7E9D,0xEF8D,0x7EF0,0xF1E4,0x7F38,0xF43C,0x7F75, +0xF695,0x7FA7,0xF8EF,0x7FCE,0xFB4A,0x7FEA,0xFDA5,0x7FFA,0x7FFF,0x0000,0x7FA7, +0xF695,0x7E9D,0xED38,0x7CE4,0xE3F4,0x7A7D,0xDAD8,0x776C,0xD1EF,0x73B6,0xC946, +0x6F5F,0xC0E9,0x6A6E,0xB8E3,0x64E9,0xB140,0x5ED7,0xAA0A,0x5843,0xA34C,0x5134, +0x9D0E,0x49B4,0x9759,0x41CE,0x9236,0x398D,0x8DAB,0x30FC,0x89BE,0x2827,0x8676, +0x1F1A,0x83D6,0x15E2,0x81E2,0x0C8C,0x809E,0x0324,0x800A,0xF9B8,0x8027,0xF055, +0x80F6,0xE707,0x8276,0xDDDC,0x84A3,0xD4E1,0x877B,0xCC21,0x8AFB,0xC3A9,0x8F1D, +0xBB85,0x93DC,0xB3C0,0x9930,0xAC65,0x9F14,0xA57E,0xA57E,0x9F14,0xAC65,0x9930, +0xB3C0,0x93DC,0xBB85,0x8F1D,0xC3A9,0x8AFB,0xCC21,0x877B,0xD4E1,0x84A3,0xDDDC, +0x8276,0xE707,0x80F6,0xF055,0x8027,0xF9B8,0x800A,0x0324,0x809E,0x0C8C,0x81E2, +0x15E2,0x83D6,0x1F1A,0x8676,0x2827,0x89BE,0x30FC,0x8DAB,0x398D,0x9236,0x41CE, +0x9759,0x49B4,0x9D0E,0x5134,0xA34C,0x5843,0xAA0A,0x5ED7,0xB140,0x64E9,0xB8E3, +0x6A6E,0xC0E9,0x6F5F,0xC946,0x73B6,0xD1EF,0x776C,0xDAD8,0x7A7D,0xE3F4,0x7CE4, +0xED38,0x7E9D,0xF695,0x7FA7,0x7FFF,0x0000,0x7A7D,0xDAD8,0x6A6E,0xB8E3,0x5134, +0x9D0E,0x30FC,0x89BE,0x0C8C,0x809E,0xE707,0x8276,0xC3A9,0x8F1D,0xA57E,0xA57E, +0x8F1D,0xC3A9,0x8276,0xE707,0x809E,0x0C8C,0x89BE,0x30FC,0x9D0E,0x5134,0xB8E3, +0x6A6E,0xDAD8,0x7A7D,0x7FFF,0x0000,0x30FC,0x89BE,0xA57E,0xA57E,0x89BE,0x30FC,}; + +#endif + + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ +#endif /* defined(ARM_MATH_MVEI) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/arm_mve_tables_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/arm_mve_tables_f16.c new file mode 100644 index 00000000..cd197e93 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/CommonTables/arm_mve_tables_f16.c @@ -0,0 +1,5576 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mve_tables_f16.c + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * used for MVE implementation only + * + * @version V1.10.0 + * @date 04 October 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #include "arm_math_types_f16.h" + + +#if defined(ARM_FLOAT16_SUPPORTED) + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_16) || defined(ARM_TABLE_TWIDDLECOEF_F16_32) + +uint32_t rearranged_twiddle_tab_stride1_arr_16_f16[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_16_f16[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_16_f16[2]={ +0,0,}; + +float16_t rearranged_twiddle_stride1_16_f16[8]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f,}; + +float16_t rearranged_twiddle_stride2_16_f16[8]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f,}; + +float16_t rearranged_twiddle_stride3_16_f16[8]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_64) || defined(ARM_TABLE_TWIDDLECOEF_F16_128) + +uint32_t rearranged_twiddle_tab_stride1_arr_64_f16[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_64_f16[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_64_f16[3]={ +0,32,0,}; + +float16_t rearranged_twiddle_stride1_64_f16[40]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f,}; + +float16_t rearranged_twiddle_stride2_64_f16[40]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f,}; + +float16_t rearranged_twiddle_stride3_64_f16[40]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_256) || defined(ARM_TABLE_TWIDDLECOEF_F16_512) + +uint32_t rearranged_twiddle_tab_stride1_arr_256_f16[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_256_f16[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_256_f16[4]={ +0,128,160,0,}; + +float16_t rearranged_twiddle_stride1_256_f16[168]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f,}; + +float16_t rearranged_twiddle_stride2_256_f16[168]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)-0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)-0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)-0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)-0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)-0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f,}; + +float16_t rearranged_twiddle_stride3_256_f16[168]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)-0.9995117187500f,(float16_t)-0.0245361328125f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9853515625000f,(float16_t)-0.1710205078125f, +(float16_t)-0.9702148437500f,(float16_t)-0.2429199218750f, +(float16_t)-0.9497070312500f,(float16_t)-0.3137207031250f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.8930664062500f,(float16_t)-0.4497070312500f, +(float16_t)-0.8579101562500f,(float16_t)-0.5141601562500f, +(float16_t)-0.8173828125000f,(float16_t)-0.5756835937500f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.7241210937500f,(float16_t)-0.6894531250000f, +(float16_t)-0.6713867187500f,(float16_t)-0.7407226562500f, +(float16_t)-0.6152343750000f,(float16_t)-0.7885742187500f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.4929199218750f,(float16_t)-0.8701171875000f, +(float16_t)-0.4274902343750f,(float16_t)-0.9038085937500f, +(float16_t)-0.3598632812500f,(float16_t)-0.9331054687500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)-0.2191162109375f,(float16_t)-0.9755859375000f, +(float16_t)-0.1467285156250f,(float16_t)-0.9892578125000f, +(float16_t)-0.0735473632812f,(float16_t)-0.9970703125000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_1024) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048) + +uint32_t rearranged_twiddle_tab_stride1_arr_1024_f16[5]={ +0,512,640,672,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_1024_f16[5]={ +0,512,640,672,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_1024_f16[5]={ +0,512,640,672,0,}; + +float16_t rearranged_twiddle_stride1_1024_f16[680]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0061340332031f, +(float16_t)1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)1.0000000000000f,(float16_t)0.0184020996094f, +(float16_t)0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)0.9995117187500f,(float16_t)0.0306701660156f, +(float16_t)0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)0.9990234375000f,(float16_t)0.0429382324219f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9985351562500f,(float16_t)0.0552062988281f, +(float16_t)0.9980468750000f,(float16_t)0.0613098144531f, +(float16_t)0.9975585937500f,(float16_t)0.0674438476562f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9965820312500f,(float16_t)0.0797119140625f, +(float16_t)0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)0.9956054687500f,(float16_t)0.0919189453125f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9946289062500f,(float16_t)0.1041259765625f, +(float16_t)0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)0.9931640625000f,(float16_t)0.1163330078125f, +(float16_t)0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)0.9916992187500f,(float16_t)0.1285400390625f, +(float16_t)0.9907226562500f,(float16_t)0.1345214843750f, +(float16_t)0.9902343750000f,(float16_t)0.1406250000000f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9882812500000f,(float16_t)0.1528320312500f, +(float16_t)0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)0.9863281250000f,(float16_t)0.1649169921875f, +(float16_t)0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)0.9843750000000f,(float16_t)0.1770019531250f, +(float16_t)0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)0.9819335937500f,(float16_t)0.1890869140625f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9794921875000f,(float16_t)0.2010498046875f, +(float16_t)0.9785156250000f,(float16_t)0.2071533203125f, +(float16_t)0.9770507812500f,(float16_t)0.2131347656250f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9741210937500f,(float16_t)0.2250976562500f, +(float16_t)0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)0.9716796875000f,(float16_t)0.2370605468750f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9687500000000f,(float16_t)0.2489013671875f, +(float16_t)0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)0.9653320312500f,(float16_t)0.2607421875000f, +(float16_t)0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)0.9619140625000f,(float16_t)0.2727050781250f, +(float16_t)0.9604492187500f,(float16_t)0.2785644531250f, +(float16_t)0.9584960937500f,(float16_t)0.2844238281250f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9550781250000f,(float16_t)0.2961425781250f, +(float16_t)0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)0.9516601562500f,(float16_t)0.3078613281250f, +(float16_t)0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)0.9477539062500f,(float16_t)0.3195800781250f, +(float16_t)0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)0.9433593750000f,(float16_t)0.3310546875000f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9394531250000f,(float16_t)0.3427734375000f, +(float16_t)0.9375000000000f,(float16_t)0.3483886718750f, +(float16_t)0.9350585937500f,(float16_t)0.3542480468750f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9306640625000f,(float16_t)0.3657226562500f, +(float16_t)0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)0.9262695312500f,(float16_t)0.3769531250000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9213867187500f,(float16_t)0.3884277343750f, +(float16_t)0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)0.9165039062500f,(float16_t)0.3996582031250f, +(float16_t)0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)0.9116210937500f,(float16_t)0.4108886718750f, +(float16_t)0.9091796875000f,(float16_t)0.4165039062500f, +(float16_t)0.9067382812500f,(float16_t)0.4221191406250f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.9013671875000f,(float16_t)0.4331054687500f, +(float16_t)0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)0.8959960937500f,(float16_t)0.4440917968750f, +(float16_t)0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)0.8906250000000f,(float16_t)0.4550781250000f, +(float16_t)0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)0.8847656250000f,(float16_t)0.4660644531250f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8789062500000f,(float16_t)0.4768066406250f, +(float16_t)0.8759765625000f,(float16_t)0.4821777343750f, +(float16_t)0.8730468750000f,(float16_t)0.4875488281250f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8671875000000f,(float16_t)0.4982910156250f, +(float16_t)0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)0.8608398437500f,(float16_t)0.5087890625000f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8544921875000f,(float16_t)0.5195312500000f, +(float16_t)0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)0.8481445312500f,(float16_t)0.5297851562500f, +(float16_t)0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)0.8417968750000f,(float16_t)0.5400390625000f, +(float16_t)0.8383789062500f,(float16_t)0.5454101562500f, +(float16_t)0.8349609375000f,(float16_t)0.5502929687500f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8281250000000f,(float16_t)0.5605468750000f, +(float16_t)0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)0.8212890625000f,(float16_t)0.5708007812500f, +(float16_t)0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)0.8139648437500f,(float16_t)0.5810546875000f, +(float16_t)0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)0.8066406250000f,(float16_t)0.5908203125000f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.7993164062500f,(float16_t)0.6005859375000f, +(float16_t)0.7958984375000f,(float16_t)0.6054687500000f, +(float16_t)0.7919921875000f,(float16_t)0.6103515625000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7846679687500f,(float16_t)0.6201171875000f, +(float16_t)0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)0.7768554687500f,(float16_t)0.6293945312500f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7690429687500f,(float16_t)0.6391601562500f, +(float16_t)0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)0.7612304687500f,(float16_t)0.6484375000000f, +(float16_t)0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)0.7534179687500f,(float16_t)0.6577148437500f, +(float16_t)0.7490234375000f,(float16_t)0.6625976562500f, +(float16_t)0.7451171875000f,(float16_t)0.6669921875000f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7368164062500f,(float16_t)0.6762695312500f, +(float16_t)0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)0.7285156250000f,(float16_t)0.6850585937500f, +(float16_t)0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)0.7202148437500f,(float16_t)0.6938476562500f, +(float16_t)0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)0.7114257812500f,(float16_t)0.7026367187500f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.7026367187500f,(float16_t)0.7114257812500f, +(float16_t)0.6982421875000f,(float16_t)0.7158203125000f, +(float16_t)0.6938476562500f,(float16_t)0.7202148437500f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6850585937500f,(float16_t)0.7285156250000f, +(float16_t)0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)0.6762695312500f,(float16_t)0.7368164062500f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6669921875000f,(float16_t)0.7451171875000f, +(float16_t)0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)0.6577148437500f,(float16_t)0.7534179687500f, +(float16_t)0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)0.6484375000000f,(float16_t)0.7612304687500f, +(float16_t)0.6440429687500f,(float16_t)0.7651367187500f, +(float16_t)0.6391601562500f,(float16_t)0.7690429687500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6293945312500f,(float16_t)0.7768554687500f, +(float16_t)0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)0.6201171875000f,(float16_t)0.7846679687500f, +(float16_t)0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)0.6103515625000f,(float16_t)0.7919921875000f, +(float16_t)0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)0.6005859375000f,(float16_t)0.7993164062500f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5908203125000f,(float16_t)0.8066406250000f, +(float16_t)0.5859375000000f,(float16_t)0.8105468750000f, +(float16_t)0.5810546875000f,(float16_t)0.8139648437500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5708007812500f,(float16_t)0.8212890625000f, +(float16_t)0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)0.5605468750000f,(float16_t)0.8281250000000f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5502929687500f,(float16_t)0.8349609375000f, +(float16_t)0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)0.5400390625000f,(float16_t)0.8417968750000f, +(float16_t)0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)0.5297851562500f,(float16_t)0.8481445312500f, +(float16_t)0.5244140625000f,(float16_t)0.8515625000000f, +(float16_t)0.5195312500000f,(float16_t)0.8544921875000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.5087890625000f,(float16_t)0.8608398437500f, +(float16_t)0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)0.4982910156250f,(float16_t)0.8671875000000f, +(float16_t)0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)0.4875488281250f,(float16_t)0.8730468750000f, +(float16_t)0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)0.4768066406250f,(float16_t)0.8789062500000f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4660644531250f,(float16_t)0.8847656250000f, +(float16_t)0.4604492187500f,(float16_t)0.8876953125000f, +(float16_t)0.4550781250000f,(float16_t)0.8906250000000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4440917968750f,(float16_t)0.8959960937500f, +(float16_t)0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)0.4331054687500f,(float16_t)0.9013671875000f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.4221191406250f,(float16_t)0.9067382812500f, +(float16_t)0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)0.4108886718750f,(float16_t)0.9116210937500f, +(float16_t)0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)0.3996582031250f,(float16_t)0.9165039062500f, +(float16_t)0.3940429687500f,(float16_t)0.9189453125000f, +(float16_t)0.3884277343750f,(float16_t)0.9213867187500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3769531250000f,(float16_t)0.9262695312500f, +(float16_t)0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)0.3657226562500f,(float16_t)0.9306640625000f, +(float16_t)0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)0.3542480468750f,(float16_t)0.9350585937500f, +(float16_t)0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)0.3427734375000f,(float16_t)0.9394531250000f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.3310546875000f,(float16_t)0.9433593750000f, +(float16_t)0.3251953125000f,(float16_t)0.9458007812500f, +(float16_t)0.3195800781250f,(float16_t)0.9477539062500f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.3078613281250f,(float16_t)0.9516601562500f, +(float16_t)0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)0.2961425781250f,(float16_t)0.9550781250000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2844238281250f,(float16_t)0.9584960937500f, +(float16_t)0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)0.2727050781250f,(float16_t)0.9619140625000f, +(float16_t)0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)0.2607421875000f,(float16_t)0.9653320312500f, +(float16_t)0.2548828125000f,(float16_t)0.9667968750000f, +(float16_t)0.2489013671875f,(float16_t)0.9687500000000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2370605468750f,(float16_t)0.9716796875000f, +(float16_t)0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)0.2250976562500f,(float16_t)0.9741210937500f, +(float16_t)0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)0.2131347656250f,(float16_t)0.9770507812500f, +(float16_t)0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)0.2010498046875f,(float16_t)0.9794921875000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1890869140625f,(float16_t)0.9819335937500f, +(float16_t)0.1829833984375f,(float16_t)0.9829101562500f, +(float16_t)0.1770019531250f,(float16_t)0.9843750000000f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1649169921875f,(float16_t)0.9863281250000f, +(float16_t)0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)0.1528320312500f,(float16_t)0.9882812500000f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.1406250000000f,(float16_t)0.9902343750000f, +(float16_t)0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)0.1285400390625f,(float16_t)0.9916992187500f, +(float16_t)0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)0.1163330078125f,(float16_t)0.9931640625000f, +(float16_t)0.1102294921875f,(float16_t)0.9941406250000f, +(float16_t)0.1041259765625f,(float16_t)0.9946289062500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0919189453125f,(float16_t)0.9956054687500f, +(float16_t)0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)0.0797119140625f,(float16_t)0.9965820312500f, +(float16_t)0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)0.0674438476562f,(float16_t)0.9975585937500f, +(float16_t)0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)0.0552062988281f,(float16_t)0.9985351562500f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0429382324219f,(float16_t)0.9990234375000f, +(float16_t)0.0368041992188f,(float16_t)0.9995117187500f, +(float16_t)0.0306701660156f,(float16_t)0.9995117187500f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)0.0184020996094f,(float16_t)1.0000000000000f, +(float16_t)0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)0.0061340332031f,(float16_t)1.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f,}; + +float16_t rearranged_twiddle_stride2_1024_f16[680]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9980468750000f,(float16_t)0.0613098144531f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)0.9907226562500f,(float16_t)0.1345214843750f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9785156250000f,(float16_t)0.2071533203125f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)0.9604492187500f,(float16_t)0.2785644531250f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9375000000000f,(float16_t)0.3483886718750f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)0.9091796875000f,(float16_t)0.4165039062500f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8759765625000f,(float16_t)0.4821777343750f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)0.8383789062500f,(float16_t)0.5454101562500f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.7958984375000f,(float16_t)0.6054687500000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)0.7490234375000f,(float16_t)0.6625976562500f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6982421875000f,(float16_t)0.7158203125000f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)0.6440429687500f,(float16_t)0.7651367187500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5859375000000f,(float16_t)0.8105468750000f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)0.5244140625000f,(float16_t)0.8515625000000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4604492187500f,(float16_t)0.8876953125000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)0.3940429687500f,(float16_t)0.9189453125000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.3251953125000f,(float16_t)0.9458007812500f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)0.2548828125000f,(float16_t)0.9667968750000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1829833984375f,(float16_t)0.9829101562500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)0.1102294921875f,(float16_t)0.9941406250000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0368041992188f,(float16_t)0.9995117187500f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)-0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)-0.0368041992188f,(float16_t)0.9995117187500f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)-0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)-0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)-0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1102294921875f,(float16_t)0.9941406250000f, +(float16_t)-0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)-0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)-0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)-0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)-0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)-0.1829833984375f,(float16_t)0.9829101562500f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)-0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)-0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)-0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)-0.2548828125000f,(float16_t)0.9667968750000f, +(float16_t)-0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)-0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)-0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)-0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)-0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)-0.3251953125000f,(float16_t)0.9458007812500f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)-0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)-0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.3940429687500f,(float16_t)0.9189453125000f, +(float16_t)-0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)-0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)-0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)-0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)-0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)-0.4604492187500f,(float16_t)0.8876953125000f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)-0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)-0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)-0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)-0.5244140625000f,(float16_t)0.8515625000000f, +(float16_t)-0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)-0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)-0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)-0.5859375000000f,(float16_t)0.8105468750000f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)-0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)-0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)-0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)-0.6440429687500f,(float16_t)0.7651367187500f, +(float16_t)-0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)-0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)-0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)-0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)-0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)-0.6982421875000f,(float16_t)0.7158203125000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)-0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)-0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)-0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)-0.7490234375000f,(float16_t)0.6625976562500f, +(float16_t)-0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)-0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)-0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)-0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)-0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)-0.7958984375000f,(float16_t)0.6054687500000f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)-0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)-0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.8383789062500f,(float16_t)0.5454101562500f, +(float16_t)-0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)-0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)-0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)-0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)-0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)-0.8759765625000f,(float16_t)0.4821777343750f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)-0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)-0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)-0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)-0.9091796875000f,(float16_t)0.4165039062500f, +(float16_t)-0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)-0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)-0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)-0.9375000000000f,(float16_t)0.3483886718750f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)-0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)-0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)-0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)-0.9604492187500f,(float16_t)0.2785644531250f, +(float16_t)-0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)-0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)-0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)-0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)-0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)-0.9785156250000f,(float16_t)0.2071533203125f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)-0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)-0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)-0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)-0.9907226562500f,(float16_t)0.1345214843750f, +(float16_t)-0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)-0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)-0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)-0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)-0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)-0.9980468750000f,(float16_t)0.0613098144531f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)-0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)-0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)-1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)-0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)-0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)-0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)-0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)-0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f,}; + +float16_t rearranged_twiddle_stride3_1024_f16[680]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0184020996094f, +(float16_t)0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)0.9985351562500f,(float16_t)0.0552062988281f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9956054687500f,(float16_t)0.0919189453125f, +(float16_t)0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)0.9916992187500f,(float16_t)0.1285400390625f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9863281250000f,(float16_t)0.1649169921875f, +(float16_t)0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)0.9794921875000f,(float16_t)0.2010498046875f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9716796875000f,(float16_t)0.2370605468750f, +(float16_t)0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)0.9619140625000f,(float16_t)0.2727050781250f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9516601562500f,(float16_t)0.3078613281250f, +(float16_t)0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)0.9394531250000f,(float16_t)0.3427734375000f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9262695312500f,(float16_t)0.3769531250000f, +(float16_t)0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)0.9116210937500f,(float16_t)0.4108886718750f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8959960937500f,(float16_t)0.4440917968750f, +(float16_t)0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)0.8789062500000f,(float16_t)0.4768066406250f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8608398437500f,(float16_t)0.5087890625000f, +(float16_t)0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)0.8417968750000f,(float16_t)0.5400390625000f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8212890625000f,(float16_t)0.5708007812500f, +(float16_t)0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)0.7993164062500f,(float16_t)0.6005859375000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7768554687500f,(float16_t)0.6293945312500f, +(float16_t)0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)0.7534179687500f,(float16_t)0.6577148437500f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7285156250000f,(float16_t)0.6850585937500f, +(float16_t)0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)0.7026367187500f,(float16_t)0.7114257812500f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6762695312500f,(float16_t)0.7368164062500f, +(float16_t)0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)0.6484375000000f,(float16_t)0.7612304687500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6201171875000f,(float16_t)0.7846679687500f, +(float16_t)0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)0.5908203125000f,(float16_t)0.8066406250000f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5605468750000f,(float16_t)0.8281250000000f, +(float16_t)0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)0.5297851562500f,(float16_t)0.8481445312500f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4982910156250f,(float16_t)0.8671875000000f, +(float16_t)0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)0.4660644531250f,(float16_t)0.8847656250000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4331054687500f,(float16_t)0.9013671875000f, +(float16_t)0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)0.3996582031250f,(float16_t)0.9165039062500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3657226562500f,(float16_t)0.9306640625000f, +(float16_t)0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)0.3310546875000f,(float16_t)0.9433593750000f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.2961425781250f,(float16_t)0.9550781250000f, +(float16_t)0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)0.2607421875000f,(float16_t)0.9653320312500f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2250976562500f,(float16_t)0.9741210937500f, +(float16_t)0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)0.1890869140625f,(float16_t)0.9819335937500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1528320312500f,(float16_t)0.9882812500000f, +(float16_t)0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)0.1163330078125f,(float16_t)0.9931640625000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0797119140625f,(float16_t)0.9965820312500f, +(float16_t)0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)0.0429382324219f,(float16_t)0.9990234375000f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)0.0061340332031f,(float16_t)1.0000000000000f, +(float16_t)-0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)-0.0306701660156f,(float16_t)0.9995117187500f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.0674438476562f,(float16_t)0.9975585937500f, +(float16_t)-0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)-0.1041259765625f,(float16_t)0.9946289062500f, +(float16_t)-0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)-0.1406250000000f,(float16_t)0.9902343750000f, +(float16_t)-0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)-0.1770019531250f,(float16_t)0.9843750000000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.2131347656250f,(float16_t)0.9770507812500f, +(float16_t)-0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)-0.2489013671875f,(float16_t)0.9687500000000f, +(float16_t)-0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)-0.2844238281250f,(float16_t)0.9584960937500f, +(float16_t)-0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)-0.3195800781250f,(float16_t)0.9477539062500f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.3542480468750f,(float16_t)0.9350585937500f, +(float16_t)-0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)-0.3884277343750f,(float16_t)0.9213867187500f, +(float16_t)-0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)-0.4221191406250f,(float16_t)0.9067382812500f, +(float16_t)-0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)-0.4550781250000f,(float16_t)0.8906250000000f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.4875488281250f,(float16_t)0.8730468750000f, +(float16_t)-0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)-0.5195312500000f,(float16_t)0.8544921875000f, +(float16_t)-0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)-0.5502929687500f,(float16_t)0.8349609375000f, +(float16_t)-0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)-0.5810546875000f,(float16_t)0.8139648437500f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.6103515625000f,(float16_t)0.7919921875000f, +(float16_t)-0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)-0.6391601562500f,(float16_t)0.7690429687500f, +(float16_t)-0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)-0.6669921875000f,(float16_t)0.7451171875000f, +(float16_t)-0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)-0.6938476562500f,(float16_t)0.7202148437500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7202148437500f,(float16_t)0.6938476562500f, +(float16_t)-0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)-0.7451171875000f,(float16_t)0.6669921875000f, +(float16_t)-0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)-0.7690429687500f,(float16_t)0.6391601562500f, +(float16_t)-0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)-0.7919921875000f,(float16_t)0.6103515625000f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8139648437500f,(float16_t)0.5810546875000f, +(float16_t)-0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)-0.8349609375000f,(float16_t)0.5502929687500f, +(float16_t)-0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)-0.8544921875000f,(float16_t)0.5195312500000f, +(float16_t)-0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)-0.8730468750000f,(float16_t)0.4875488281250f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.8906250000000f,(float16_t)0.4550781250000f, +(float16_t)-0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)-0.9067382812500f,(float16_t)0.4221191406250f, +(float16_t)-0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)-0.9213867187500f,(float16_t)0.3884277343750f, +(float16_t)-0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)-0.9350585937500f,(float16_t)0.3542480468750f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9477539062500f,(float16_t)0.3195800781250f, +(float16_t)-0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)-0.9584960937500f,(float16_t)0.2844238281250f, +(float16_t)-0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)-0.9687500000000f,(float16_t)0.2489013671875f, +(float16_t)-0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)-0.9770507812500f,(float16_t)0.2131347656250f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9843750000000f,(float16_t)0.1770019531250f, +(float16_t)-0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)-0.9902343750000f,(float16_t)0.1406250000000f, +(float16_t)-0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)-0.9946289062500f,(float16_t)0.1041259765625f, +(float16_t)-0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)-0.9975585937500f,(float16_t)0.0674438476562f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)-0.9995117187500f,(float16_t)0.0306701660156f, +(float16_t)-1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)-1.0000000000000f,(float16_t)-0.0061340332031f, +(float16_t)-0.9995117187500f,(float16_t)-0.0245361328125f, +(float16_t)-0.9990234375000f,(float16_t)-0.0429382324219f, +(float16_t)-0.9980468750000f,(float16_t)-0.0613098144531f, +(float16_t)-0.9965820312500f,(float16_t)-0.0797119140625f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9931640625000f,(float16_t)-0.1163330078125f, +(float16_t)-0.9907226562500f,(float16_t)-0.1345214843750f, +(float16_t)-0.9882812500000f,(float16_t)-0.1528320312500f, +(float16_t)-0.9853515625000f,(float16_t)-0.1710205078125f, +(float16_t)-0.9819335937500f,(float16_t)-0.1890869140625f, +(float16_t)-0.9785156250000f,(float16_t)-0.2071533203125f, +(float16_t)-0.9741210937500f,(float16_t)-0.2250976562500f, +(float16_t)-0.9702148437500f,(float16_t)-0.2429199218750f, +(float16_t)-0.9653320312500f,(float16_t)-0.2607421875000f, +(float16_t)-0.9604492187500f,(float16_t)-0.2785644531250f, +(float16_t)-0.9550781250000f,(float16_t)-0.2961425781250f, +(float16_t)-0.9497070312500f,(float16_t)-0.3137207031250f, +(float16_t)-0.9433593750000f,(float16_t)-0.3310546875000f, +(float16_t)-0.9375000000000f,(float16_t)-0.3483886718750f, +(float16_t)-0.9306640625000f,(float16_t)-0.3657226562500f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.9165039062500f,(float16_t)-0.3996582031250f, +(float16_t)-0.9091796875000f,(float16_t)-0.4165039062500f, +(float16_t)-0.9013671875000f,(float16_t)-0.4331054687500f, +(float16_t)-0.8930664062500f,(float16_t)-0.4497070312500f, +(float16_t)-0.8847656250000f,(float16_t)-0.4660644531250f, +(float16_t)-0.8759765625000f,(float16_t)-0.4821777343750f, +(float16_t)-0.8671875000000f,(float16_t)-0.4982910156250f, +(float16_t)-0.8579101562500f,(float16_t)-0.5141601562500f, +(float16_t)-0.8481445312500f,(float16_t)-0.5297851562500f, +(float16_t)-0.8383789062500f,(float16_t)-0.5454101562500f, +(float16_t)-0.8281250000000f,(float16_t)-0.5605468750000f, +(float16_t)-0.8173828125000f,(float16_t)-0.5756835937500f, +(float16_t)-0.8066406250000f,(float16_t)-0.5908203125000f, +(float16_t)-0.7958984375000f,(float16_t)-0.6054687500000f, +(float16_t)-0.7846679687500f,(float16_t)-0.6201171875000f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.7612304687500f,(float16_t)-0.6484375000000f, +(float16_t)-0.7490234375000f,(float16_t)-0.6625976562500f, +(float16_t)-0.7368164062500f,(float16_t)-0.6762695312500f, +(float16_t)-0.7241210937500f,(float16_t)-0.6894531250000f, +(float16_t)-0.7114257812500f,(float16_t)-0.7026367187500f, +(float16_t)-0.6982421875000f,(float16_t)-0.7158203125000f, +(float16_t)-0.6850585937500f,(float16_t)-0.7285156250000f, +(float16_t)-0.6713867187500f,(float16_t)-0.7407226562500f, +(float16_t)-0.6577148437500f,(float16_t)-0.7534179687500f, +(float16_t)-0.6440429687500f,(float16_t)-0.7651367187500f, +(float16_t)-0.6293945312500f,(float16_t)-0.7768554687500f, +(float16_t)-0.6152343750000f,(float16_t)-0.7885742187500f, +(float16_t)-0.6005859375000f,(float16_t)-0.7993164062500f, +(float16_t)-0.5859375000000f,(float16_t)-0.8105468750000f, +(float16_t)-0.5708007812500f,(float16_t)-0.8212890625000f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.5400390625000f,(float16_t)-0.8417968750000f, +(float16_t)-0.5244140625000f,(float16_t)-0.8515625000000f, +(float16_t)-0.5087890625000f,(float16_t)-0.8608398437500f, +(float16_t)-0.4929199218750f,(float16_t)-0.8701171875000f, +(float16_t)-0.4768066406250f,(float16_t)-0.8789062500000f, +(float16_t)-0.4604492187500f,(float16_t)-0.8876953125000f, +(float16_t)-0.4440917968750f,(float16_t)-0.8959960937500f, +(float16_t)-0.4274902343750f,(float16_t)-0.9038085937500f, +(float16_t)-0.4108886718750f,(float16_t)-0.9116210937500f, +(float16_t)-0.3940429687500f,(float16_t)-0.9189453125000f, +(float16_t)-0.3769531250000f,(float16_t)-0.9262695312500f, +(float16_t)-0.3598632812500f,(float16_t)-0.9331054687500f, +(float16_t)-0.3427734375000f,(float16_t)-0.9394531250000f, +(float16_t)-0.3251953125000f,(float16_t)-0.9458007812500f, +(float16_t)-0.3078613281250f,(float16_t)-0.9516601562500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)-0.2727050781250f,(float16_t)-0.9619140625000f, +(float16_t)-0.2548828125000f,(float16_t)-0.9667968750000f, +(float16_t)-0.2370605468750f,(float16_t)-0.9716796875000f, +(float16_t)-0.2191162109375f,(float16_t)-0.9755859375000f, +(float16_t)-0.2010498046875f,(float16_t)-0.9794921875000f, +(float16_t)-0.1829833984375f,(float16_t)-0.9829101562500f, +(float16_t)-0.1649169921875f,(float16_t)-0.9863281250000f, +(float16_t)-0.1467285156250f,(float16_t)-0.9892578125000f, +(float16_t)-0.1285400390625f,(float16_t)-0.9916992187500f, +(float16_t)-0.1102294921875f,(float16_t)-0.9941406250000f, +(float16_t)-0.0919189453125f,(float16_t)-0.9956054687500f, +(float16_t)-0.0735473632812f,(float16_t)-0.9970703125000f, +(float16_t)-0.0552062988281f,(float16_t)-0.9985351562500f, +(float16_t)-0.0368041992188f,(float16_t)-0.9995117187500f, +(float16_t)-0.0184020996094f,(float16_t)-1.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)-0.9995117187500f,(float16_t)-0.0245361328125f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9853515625000f,(float16_t)-0.1710205078125f, +(float16_t)-0.9702148437500f,(float16_t)-0.2429199218750f, +(float16_t)-0.9497070312500f,(float16_t)-0.3137207031250f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.8930664062500f,(float16_t)-0.4497070312500f, +(float16_t)-0.8579101562500f,(float16_t)-0.5141601562500f, +(float16_t)-0.8173828125000f,(float16_t)-0.5756835937500f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.7241210937500f,(float16_t)-0.6894531250000f, +(float16_t)-0.6713867187500f,(float16_t)-0.7407226562500f, +(float16_t)-0.6152343750000f,(float16_t)-0.7885742187500f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.4929199218750f,(float16_t)-0.8701171875000f, +(float16_t)-0.4274902343750f,(float16_t)-0.9038085937500f, +(float16_t)-0.3598632812500f,(float16_t)-0.9331054687500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)-0.2191162109375f,(float16_t)-0.9755859375000f, +(float16_t)-0.1467285156250f,(float16_t)-0.9892578125000f, +(float16_t)-0.0735473632812f,(float16_t)-0.9970703125000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) || defined(ARM_TABLE_TWIDDLECOEF_F16_8192) + +uint32_t rearranged_twiddle_tab_stride1_arr_4096_f16[6]={ +0,2048,2560,2688,2720,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_4096_f16[6]={ +0,2048,2560,2688,2720,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_4096_f16[6]={ +0,2048,2560,2688,2720,0,}; + +float16_t rearranged_twiddle_stride1_4096_f16[2728]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0015335083008f, +(float16_t)1.0000000000000f,(float16_t)0.0030670166016f, +(float16_t)1.0000000000000f,(float16_t)0.0046005249023f, +(float16_t)1.0000000000000f,(float16_t)0.0061340332031f, +(float16_t)1.0000000000000f,(float16_t)0.0076713562012f, +(float16_t)1.0000000000000f,(float16_t)0.0092010498047f, +(float16_t)1.0000000000000f,(float16_t)0.0107345581055f, +(float16_t)1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)1.0000000000000f,(float16_t)0.0138015747070f, +(float16_t)1.0000000000000f,(float16_t)0.0153427124023f, +(float16_t)1.0000000000000f,(float16_t)0.0168762207031f, +(float16_t)1.0000000000000f,(float16_t)0.0184020996094f, +(float16_t)1.0000000000000f,(float16_t)0.0199432373047f, +(float16_t)1.0000000000000f,(float16_t)0.0214691162109f, +(float16_t)0.9995117187500f,(float16_t)0.0230102539062f, +(float16_t)0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)0.9995117187500f,(float16_t)0.0260772705078f, +(float16_t)0.9995117187500f,(float16_t)0.0276031494141f, +(float16_t)0.9995117187500f,(float16_t)0.0291442871094f, +(float16_t)0.9995117187500f,(float16_t)0.0306701660156f, +(float16_t)0.9995117187500f,(float16_t)0.0321960449219f, +(float16_t)0.9995117187500f,(float16_t)0.0337524414062f, +(float16_t)0.9995117187500f,(float16_t)0.0352783203125f, +(float16_t)0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)0.9990234375000f,(float16_t)0.0383300781250f, +(float16_t)0.9990234375000f,(float16_t)0.0398864746094f, +(float16_t)0.9990234375000f,(float16_t)0.0414123535156f, +(float16_t)0.9990234375000f,(float16_t)0.0429382324219f, +(float16_t)0.9990234375000f,(float16_t)0.0444641113281f, +(float16_t)0.9990234375000f,(float16_t)0.0459899902344f, +(float16_t)0.9990234375000f,(float16_t)0.0475463867188f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9985351562500f,(float16_t)0.0505981445312f, +(float16_t)0.9985351562500f,(float16_t)0.0521240234375f, +(float16_t)0.9985351562500f,(float16_t)0.0536499023438f, +(float16_t)0.9985351562500f,(float16_t)0.0552062988281f, +(float16_t)0.9985351562500f,(float16_t)0.0567321777344f, +(float16_t)0.9985351562500f,(float16_t)0.0582580566406f, +(float16_t)0.9980468750000f,(float16_t)0.0597839355469f, +(float16_t)0.9980468750000f,(float16_t)0.0613098144531f, +(float16_t)0.9980468750000f,(float16_t)0.0628662109375f, +(float16_t)0.9980468750000f,(float16_t)0.0643920898438f, +(float16_t)0.9980468750000f,(float16_t)0.0659179687500f, +(float16_t)0.9975585937500f,(float16_t)0.0674438476562f, +(float16_t)0.9975585937500f,(float16_t)0.0689697265625f, +(float16_t)0.9975585937500f,(float16_t)0.0704956054688f, +(float16_t)0.9975585937500f,(float16_t)0.0720214843750f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9970703125000f,(float16_t)0.0750732421875f, +(float16_t)0.9970703125000f,(float16_t)0.0765991210938f, +(float16_t)0.9970703125000f,(float16_t)0.0781250000000f, +(float16_t)0.9965820312500f,(float16_t)0.0797119140625f, +(float16_t)0.9965820312500f,(float16_t)0.0812377929688f, +(float16_t)0.9965820312500f,(float16_t)0.0827636718750f, +(float16_t)0.9965820312500f,(float16_t)0.0842895507812f, +(float16_t)0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)0.9960937500000f,(float16_t)0.0873413085938f, +(float16_t)0.9960937500000f,(float16_t)0.0888671875000f, +(float16_t)0.9960937500000f,(float16_t)0.0903930664062f, +(float16_t)0.9956054687500f,(float16_t)0.0919189453125f, +(float16_t)0.9956054687500f,(float16_t)0.0934448242188f, +(float16_t)0.9956054687500f,(float16_t)0.0949707031250f, +(float16_t)0.9951171875000f,(float16_t)0.0964965820312f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9951171875000f,(float16_t)0.0995483398438f, +(float16_t)0.9951171875000f,(float16_t)0.1010742187500f, +(float16_t)0.9946289062500f,(float16_t)0.1026000976562f, +(float16_t)0.9946289062500f,(float16_t)0.1041259765625f, +(float16_t)0.9946289062500f,(float16_t)0.1056518554688f, +(float16_t)0.9941406250000f,(float16_t)0.1071777343750f, +(float16_t)0.9941406250000f,(float16_t)0.1087036132812f, +(float16_t)0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)0.9936523437500f,(float16_t)0.1117553710938f, +(float16_t)0.9936523437500f,(float16_t)0.1132812500000f, +(float16_t)0.9931640625000f,(float16_t)0.1148071289062f, +(float16_t)0.9931640625000f,(float16_t)0.1163330078125f, +(float16_t)0.9931640625000f,(float16_t)0.1178588867188f, +(float16_t)0.9926757812500f,(float16_t)0.1193847656250f, +(float16_t)0.9926757812500f,(float16_t)0.1209106445312f, +(float16_t)0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)0.9921875000000f,(float16_t)0.1239624023438f, +(float16_t)0.9921875000000f,(float16_t)0.1254882812500f, +(float16_t)0.9916992187500f,(float16_t)0.1269531250000f, +(float16_t)0.9916992187500f,(float16_t)0.1285400390625f, +(float16_t)0.9916992187500f,(float16_t)0.1300048828125f, +(float16_t)0.9912109375000f,(float16_t)0.1315917968750f, +(float16_t)0.9912109375000f,(float16_t)0.1330566406250f, +(float16_t)0.9907226562500f,(float16_t)0.1345214843750f, +(float16_t)0.9907226562500f,(float16_t)0.1361083984375f, +(float16_t)0.9907226562500f,(float16_t)0.1375732421875f, +(float16_t)0.9902343750000f,(float16_t)0.1391601562500f, +(float16_t)0.9902343750000f,(float16_t)0.1406250000000f, +(float16_t)0.9897460937500f,(float16_t)0.1422119140625f, +(float16_t)0.9897460937500f,(float16_t)0.1436767578125f, +(float16_t)0.9892578125000f,(float16_t)0.1452636718750f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9887695312500f,(float16_t)0.1481933593750f, +(float16_t)0.9887695312500f,(float16_t)0.1497802734375f, +(float16_t)0.9882812500000f,(float16_t)0.1512451171875f, +(float16_t)0.9882812500000f,(float16_t)0.1528320312500f, +(float16_t)0.9877929687500f,(float16_t)0.1542968750000f, +(float16_t)0.9877929687500f,(float16_t)0.1558837890625f, +(float16_t)0.9873046875000f,(float16_t)0.1573486328125f, +(float16_t)0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)0.9868164062500f,(float16_t)0.1604003906250f, +(float16_t)0.9868164062500f,(float16_t)0.1618652343750f, +(float16_t)0.9863281250000f,(float16_t)0.1634521484375f, +(float16_t)0.9863281250000f,(float16_t)0.1649169921875f, +(float16_t)0.9858398437500f,(float16_t)0.1663818359375f, +(float16_t)0.9858398437500f,(float16_t)0.1679687500000f, +(float16_t)0.9853515625000f,(float16_t)0.1694335937500f, +(float16_t)0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)0.9848632812500f,(float16_t)0.1724853515625f, +(float16_t)0.9848632812500f,(float16_t)0.1739501953125f, +(float16_t)0.9843750000000f,(float16_t)0.1755371093750f, +(float16_t)0.9843750000000f,(float16_t)0.1770019531250f, +(float16_t)0.9838867187500f,(float16_t)0.1784667968750f, +(float16_t)0.9838867187500f,(float16_t)0.1800537109375f, +(float16_t)0.9833984375000f,(float16_t)0.1815185546875f, +(float16_t)0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)0.9829101562500f,(float16_t)0.1845703125000f, +(float16_t)0.9824218750000f,(float16_t)0.1860351562500f, +(float16_t)0.9824218750000f,(float16_t)0.1876220703125f, +(float16_t)0.9819335937500f,(float16_t)0.1890869140625f, +(float16_t)0.9814453125000f,(float16_t)0.1905517578125f, +(float16_t)0.9814453125000f,(float16_t)0.1921386718750f, +(float16_t)0.9809570312500f,(float16_t)0.1936035156250f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9804687500000f,(float16_t)0.1966552734375f, +(float16_t)0.9799804687500f,(float16_t)0.1981201171875f, +(float16_t)0.9799804687500f,(float16_t)0.1995849609375f, +(float16_t)0.9794921875000f,(float16_t)0.2010498046875f, +(float16_t)0.9794921875000f,(float16_t)0.2026367187500f, +(float16_t)0.9790039062500f,(float16_t)0.2041015625000f, +(float16_t)0.9785156250000f,(float16_t)0.2055664062500f, +(float16_t)0.9785156250000f,(float16_t)0.2071533203125f, +(float16_t)0.9780273437500f,(float16_t)0.2086181640625f, +(float16_t)0.9775390625000f,(float16_t)0.2100830078125f, +(float16_t)0.9775390625000f,(float16_t)0.2116699218750f, +(float16_t)0.9770507812500f,(float16_t)0.2131347656250f, +(float16_t)0.9765625000000f,(float16_t)0.2145996093750f, +(float16_t)0.9765625000000f,(float16_t)0.2160644531250f, +(float16_t)0.9760742187500f,(float16_t)0.2176513671875f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9755859375000f,(float16_t)0.2205810546875f, +(float16_t)0.9750976562500f,(float16_t)0.2220458984375f, +(float16_t)0.9746093750000f,(float16_t)0.2236328125000f, +(float16_t)0.9741210937500f,(float16_t)0.2250976562500f, +(float16_t)0.9741210937500f,(float16_t)0.2265625000000f, +(float16_t)0.9736328125000f,(float16_t)0.2280273437500f, +(float16_t)0.9731445312500f,(float16_t)0.2296142578125f, +(float16_t)0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)0.9726562500000f,(float16_t)0.2325439453125f, +(float16_t)0.9721679687500f,(float16_t)0.2340087890625f, +(float16_t)0.9716796875000f,(float16_t)0.2354736328125f, +(float16_t)0.9716796875000f,(float16_t)0.2370605468750f, +(float16_t)0.9711914062500f,(float16_t)0.2385253906250f, +(float16_t)0.9707031250000f,(float16_t)0.2399902343750f, +(float16_t)0.9702148437500f,(float16_t)0.2414550781250f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9697265625000f,(float16_t)0.2445068359375f, +(float16_t)0.9692382812500f,(float16_t)0.2459716796875f, +(float16_t)0.9687500000000f,(float16_t)0.2474365234375f, +(float16_t)0.9687500000000f,(float16_t)0.2489013671875f, +(float16_t)0.9682617187500f,(float16_t)0.2504882812500f, +(float16_t)0.9677734375000f,(float16_t)0.2519531250000f, +(float16_t)0.9672851562500f,(float16_t)0.2534179687500f, +(float16_t)0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)0.9667968750000f,(float16_t)0.2563476562500f, +(float16_t)0.9663085937500f,(float16_t)0.2578125000000f, +(float16_t)0.9658203125000f,(float16_t)0.2592773437500f, +(float16_t)0.9653320312500f,(float16_t)0.2607421875000f, +(float16_t)0.9648437500000f,(float16_t)0.2622070312500f, +(float16_t)0.9643554687500f,(float16_t)0.2636718750000f, +(float16_t)0.9643554687500f,(float16_t)0.2651367187500f, +(float16_t)0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)0.9633789062500f,(float16_t)0.2683105468750f, +(float16_t)0.9628906250000f,(float16_t)0.2697753906250f, +(float16_t)0.9624023437500f,(float16_t)0.2712402343750f, +(float16_t)0.9619140625000f,(float16_t)0.2727050781250f, +(float16_t)0.9619140625000f,(float16_t)0.2741699218750f, +(float16_t)0.9614257812500f,(float16_t)0.2756347656250f, +(float16_t)0.9609375000000f,(float16_t)0.2770996093750f, +(float16_t)0.9604492187500f,(float16_t)0.2785644531250f, +(float16_t)0.9599609375000f,(float16_t)0.2800292968750f, +(float16_t)0.9594726562500f,(float16_t)0.2814941406250f, +(float16_t)0.9589843750000f,(float16_t)0.2829589843750f, +(float16_t)0.9584960937500f,(float16_t)0.2844238281250f, +(float16_t)0.9584960937500f,(float16_t)0.2858886718750f, +(float16_t)0.9580078125000f,(float16_t)0.2873535156250f, +(float16_t)0.9575195312500f,(float16_t)0.2888183593750f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9565429687500f,(float16_t)0.2917480468750f, +(float16_t)0.9560546875000f,(float16_t)0.2932128906250f, +(float16_t)0.9555664062500f,(float16_t)0.2946777343750f, +(float16_t)0.9550781250000f,(float16_t)0.2961425781250f, +(float16_t)0.9545898437500f,(float16_t)0.2976074218750f, +(float16_t)0.9541015625000f,(float16_t)0.2990722656250f, +(float16_t)0.9536132812500f,(float16_t)0.3005371093750f, +(float16_t)0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)0.9526367187500f,(float16_t)0.3034667968750f, +(float16_t)0.9521484375000f,(float16_t)0.3049316406250f, +(float16_t)0.9521484375000f,(float16_t)0.3063964843750f, +(float16_t)0.9516601562500f,(float16_t)0.3078613281250f, +(float16_t)0.9511718750000f,(float16_t)0.3093261718750f, +(float16_t)0.9506835937500f,(float16_t)0.3107910156250f, +(float16_t)0.9501953125000f,(float16_t)0.3122558593750f, +(float16_t)0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)0.9492187500000f,(float16_t)0.3151855468750f, +(float16_t)0.9487304687500f,(float16_t)0.3166503906250f, +(float16_t)0.9482421875000f,(float16_t)0.3181152343750f, +(float16_t)0.9477539062500f,(float16_t)0.3195800781250f, +(float16_t)0.9472656250000f,(float16_t)0.3210449218750f, +(float16_t)0.9467773437500f,(float16_t)0.3225097656250f, +(float16_t)0.9462890625000f,(float16_t)0.3239746093750f, +(float16_t)0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)0.9453125000000f,(float16_t)0.3266601562500f, +(float16_t)0.9448242187500f,(float16_t)0.3281250000000f, +(float16_t)0.9443359375000f,(float16_t)0.3295898437500f, +(float16_t)0.9433593750000f,(float16_t)0.3310546875000f, +(float16_t)0.9428710937500f,(float16_t)0.3325195312500f, +(float16_t)0.9423828125000f,(float16_t)0.3339843750000f, +(float16_t)0.9418945312500f,(float16_t)0.3354492187500f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9409179687500f,(float16_t)0.3383789062500f, +(float16_t)0.9404296875000f,(float16_t)0.3398437500000f, +(float16_t)0.9399414062500f,(float16_t)0.3413085937500f, +(float16_t)0.9394531250000f,(float16_t)0.3427734375000f, +(float16_t)0.9389648437500f,(float16_t)0.3439941406250f, +(float16_t)0.9384765625000f,(float16_t)0.3454589843750f, +(float16_t)0.9379882812500f,(float16_t)0.3469238281250f, +(float16_t)0.9375000000000f,(float16_t)0.3483886718750f, +(float16_t)0.9370117187500f,(float16_t)0.3498535156250f, +(float16_t)0.9360351562500f,(float16_t)0.3513183593750f, +(float16_t)0.9355468750000f,(float16_t)0.3527832031250f, +(float16_t)0.9350585937500f,(float16_t)0.3542480468750f, +(float16_t)0.9345703125000f,(float16_t)0.3557128906250f, +(float16_t)0.9340820312500f,(float16_t)0.3569335937500f, +(float16_t)0.9335937500000f,(float16_t)0.3583984375000f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9326171875000f,(float16_t)0.3613281250000f, +(float16_t)0.9316406250000f,(float16_t)0.3627929687500f, +(float16_t)0.9311523437500f,(float16_t)0.3642578125000f, +(float16_t)0.9306640625000f,(float16_t)0.3657226562500f, +(float16_t)0.9301757812500f,(float16_t)0.3669433593750f, +(float16_t)0.9296875000000f,(float16_t)0.3684082031250f, +(float16_t)0.9291992187500f,(float16_t)0.3698730468750f, +(float16_t)0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)0.9277343750000f,(float16_t)0.3728027343750f, +(float16_t)0.9272460937500f,(float16_t)0.3742675781250f, +(float16_t)0.9267578125000f,(float16_t)0.3754882812500f, +(float16_t)0.9262695312500f,(float16_t)0.3769531250000f, +(float16_t)0.9257812500000f,(float16_t)0.3784179687500f, +(float16_t)0.9252929687500f,(float16_t)0.3798828125000f, +(float16_t)0.9243164062500f,(float16_t)0.3813476562500f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9233398437500f,(float16_t)0.3840332031250f, +(float16_t)0.9228515625000f,(float16_t)0.3854980468750f, +(float16_t)0.9218750000000f,(float16_t)0.3869628906250f, +(float16_t)0.9213867187500f,(float16_t)0.3884277343750f, +(float16_t)0.9208984375000f,(float16_t)0.3896484375000f, +(float16_t)0.9204101562500f,(float16_t)0.3911132812500f, +(float16_t)0.9199218750000f,(float16_t)0.3925781250000f, +(float16_t)0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)0.9184570312500f,(float16_t)0.3955078125000f, +(float16_t)0.9179687500000f,(float16_t)0.3967285156250f, +(float16_t)0.9174804687500f,(float16_t)0.3981933593750f, +(float16_t)0.9165039062500f,(float16_t)0.3996582031250f, +(float16_t)0.9160156250000f,(float16_t)0.4011230468750f, +(float16_t)0.9155273437500f,(float16_t)0.4023437500000f, +(float16_t)0.9150390625000f,(float16_t)0.4038085937500f, +(float16_t)0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)0.9135742187500f,(float16_t)0.4067382812500f, +(float16_t)0.9130859375000f,(float16_t)0.4079589843750f, +(float16_t)0.9121093750000f,(float16_t)0.4094238281250f, +(float16_t)0.9116210937500f,(float16_t)0.4108886718750f, +(float16_t)0.9111328125000f,(float16_t)0.4123535156250f, +(float16_t)0.9106445312500f,(float16_t)0.4135742187500f, +(float16_t)0.9096679687500f,(float16_t)0.4150390625000f, +(float16_t)0.9091796875000f,(float16_t)0.4165039062500f, +(float16_t)0.9086914062500f,(float16_t)0.4177246093750f, +(float16_t)0.9077148437500f,(float16_t)0.4191894531250f, +(float16_t)0.9072265625000f,(float16_t)0.4206542968750f, +(float16_t)0.9067382812500f,(float16_t)0.4221191406250f, +(float16_t)0.9057617187500f,(float16_t)0.4233398437500f, +(float16_t)0.9052734375000f,(float16_t)0.4248046875000f, +(float16_t)0.9047851562500f,(float16_t)0.4262695312500f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.9033203125000f,(float16_t)0.4289550781250f, +(float16_t)0.9028320312500f,(float16_t)0.4304199218750f, +(float16_t)0.9018554687500f,(float16_t)0.4316406250000f, +(float16_t)0.9013671875000f,(float16_t)0.4331054687500f, +(float16_t)0.9008789062500f,(float16_t)0.4345703125000f, +(float16_t)0.8999023437500f,(float16_t)0.4357910156250f, +(float16_t)0.8994140625000f,(float16_t)0.4372558593750f, +(float16_t)0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)0.8979492187500f,(float16_t)0.4399414062500f, +(float16_t)0.8974609375000f,(float16_t)0.4414062500000f, +(float16_t)0.8964843750000f,(float16_t)0.4426269531250f, +(float16_t)0.8959960937500f,(float16_t)0.4440917968750f, +(float16_t)0.8955078125000f,(float16_t)0.4455566406250f, +(float16_t)0.8945312500000f,(float16_t)0.4467773437500f, +(float16_t)0.8940429687500f,(float16_t)0.4482421875000f, +(float16_t)0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)0.8925781250000f,(float16_t)0.4509277343750f, +(float16_t)0.8916015625000f,(float16_t)0.4523925781250f, +(float16_t)0.8911132812500f,(float16_t)0.4536132812500f, +(float16_t)0.8906250000000f,(float16_t)0.4550781250000f, +(float16_t)0.8896484375000f,(float16_t)0.4565429687500f, +(float16_t)0.8891601562500f,(float16_t)0.4577636718750f, +(float16_t)0.8881835937500f,(float16_t)0.4592285156250f, +(float16_t)0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)0.8867187500000f,(float16_t)0.4619140625000f, +(float16_t)0.8862304687500f,(float16_t)0.4633789062500f, +(float16_t)0.8857421875000f,(float16_t)0.4645996093750f, +(float16_t)0.8847656250000f,(float16_t)0.4660644531250f, +(float16_t)0.8842773437500f,(float16_t)0.4672851562500f, +(float16_t)0.8833007812500f,(float16_t)0.4687500000000f, +(float16_t)0.8828125000000f,(float16_t)0.4699707031250f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8813476562500f,(float16_t)0.4726562500000f, +(float16_t)0.8803710937500f,(float16_t)0.4741210937500f, +(float16_t)0.8798828125000f,(float16_t)0.4753417968750f, +(float16_t)0.8789062500000f,(float16_t)0.4768066406250f, +(float16_t)0.8784179687500f,(float16_t)0.4780273437500f, +(float16_t)0.8774414062500f,(float16_t)0.4794921875000f, +(float16_t)0.8769531250000f,(float16_t)0.4809570312500f, +(float16_t)0.8759765625000f,(float16_t)0.4821777343750f, +(float16_t)0.8754882812500f,(float16_t)0.4836425781250f, +(float16_t)0.8745117187500f,(float16_t)0.4848632812500f, +(float16_t)0.8740234375000f,(float16_t)0.4863281250000f, +(float16_t)0.8730468750000f,(float16_t)0.4875488281250f, +(float16_t)0.8725585937500f,(float16_t)0.4887695312500f, +(float16_t)0.8715820312500f,(float16_t)0.4902343750000f, +(float16_t)0.8706054687500f,(float16_t)0.4914550781250f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8691406250000f,(float16_t)0.4941406250000f, +(float16_t)0.8686523437500f,(float16_t)0.4956054687500f, +(float16_t)0.8676757812500f,(float16_t)0.4968261718750f, +(float16_t)0.8671875000000f,(float16_t)0.4982910156250f, +(float16_t)0.8662109375000f,(float16_t)0.4995117187500f, +(float16_t)0.8657226562500f,(float16_t)0.5009765625000f, +(float16_t)0.8647460937500f,(float16_t)0.5024414062500f, +(float16_t)0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)0.8632812500000f,(float16_t)0.5048828125000f, +(float16_t)0.8623046875000f,(float16_t)0.5063476562500f, +(float16_t)0.8618164062500f,(float16_t)0.5073242187500f, +(float16_t)0.8608398437500f,(float16_t)0.5087890625000f, +(float16_t)0.8598632812500f,(float16_t)0.5102539062500f, +(float16_t)0.8593750000000f,(float16_t)0.5112304687500f, +(float16_t)0.8583984375000f,(float16_t)0.5126953125000f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8569335937500f,(float16_t)0.5156250000000f, +(float16_t)0.8559570312500f,(float16_t)0.5166015625000f, +(float16_t)0.8554687500000f,(float16_t)0.5180664062500f, +(float16_t)0.8544921875000f,(float16_t)0.5195312500000f, +(float16_t)0.8540039062500f,(float16_t)0.5205078125000f, +(float16_t)0.8530273437500f,(float16_t)0.5219726562500f, +(float16_t)0.8520507812500f,(float16_t)0.5234375000000f, +(float16_t)0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)0.8505859375000f,(float16_t)0.5258789062500f, +(float16_t)0.8496093750000f,(float16_t)0.5273437500000f, +(float16_t)0.8491210937500f,(float16_t)0.5283203125000f, +(float16_t)0.8481445312500f,(float16_t)0.5297851562500f, +(float16_t)0.8471679687500f,(float16_t)0.5312500000000f, +(float16_t)0.8466796875000f,(float16_t)0.5322265625000f, +(float16_t)0.8457031250000f,(float16_t)0.5336914062500f, +(float16_t)0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)0.8442382812500f,(float16_t)0.5361328125000f, +(float16_t)0.8432617187500f,(float16_t)0.5375976562500f, +(float16_t)0.8422851562500f,(float16_t)0.5390625000000f, +(float16_t)0.8417968750000f,(float16_t)0.5400390625000f, +(float16_t)0.8408203125000f,(float16_t)0.5415039062500f, +(float16_t)0.8398437500000f,(float16_t)0.5429687500000f, +(float16_t)0.8388671875000f,(float16_t)0.5439453125000f, +(float16_t)0.8383789062500f,(float16_t)0.5454101562500f, +(float16_t)0.8374023437500f,(float16_t)0.5463867187500f, +(float16_t)0.8364257812500f,(float16_t)0.5478515625000f, +(float16_t)0.8359375000000f,(float16_t)0.5493164062500f, +(float16_t)0.8349609375000f,(float16_t)0.5502929687500f, +(float16_t)0.8339843750000f,(float16_t)0.5517578125000f, +(float16_t)0.8330078125000f,(float16_t)0.5532226562500f, +(float16_t)0.8325195312500f,(float16_t)0.5541992187500f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8305664062500f,(float16_t)0.5566406250000f, +(float16_t)0.8295898437500f,(float16_t)0.5581054687500f, +(float16_t)0.8291015625000f,(float16_t)0.5595703125000f, +(float16_t)0.8281250000000f,(float16_t)0.5605468750000f, +(float16_t)0.8271484375000f,(float16_t)0.5620117187500f, +(float16_t)0.8261718750000f,(float16_t)0.5629882812500f, +(float16_t)0.8256835937500f,(float16_t)0.5644531250000f, +(float16_t)0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)0.8237304687500f,(float16_t)0.5668945312500f, +(float16_t)0.8227539062500f,(float16_t)0.5683593750000f, +(float16_t)0.8217773437500f,(float16_t)0.5693359375000f, +(float16_t)0.8212890625000f,(float16_t)0.5708007812500f, +(float16_t)0.8203125000000f,(float16_t)0.5722656250000f, +(float16_t)0.8193359375000f,(float16_t)0.5732421875000f, +(float16_t)0.8183593750000f,(float16_t)0.5747070312500f, +(float16_t)0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)0.8168945312500f,(float16_t)0.5771484375000f, +(float16_t)0.8159179687500f,(float16_t)0.5781250000000f, +(float16_t)0.8149414062500f,(float16_t)0.5795898437500f, +(float16_t)0.8139648437500f,(float16_t)0.5810546875000f, +(float16_t)0.8129882812500f,(float16_t)0.5820312500000f, +(float16_t)0.8120117187500f,(float16_t)0.5834960937500f, +(float16_t)0.8115234375000f,(float16_t)0.5844726562500f, +(float16_t)0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)0.8095703125000f,(float16_t)0.5869140625000f, +(float16_t)0.8085937500000f,(float16_t)0.5883789062500f, +(float16_t)0.8076171875000f,(float16_t)0.5893554687500f, +(float16_t)0.8066406250000f,(float16_t)0.5908203125000f, +(float16_t)0.8061523437500f,(float16_t)0.5917968750000f, +(float16_t)0.8051757812500f,(float16_t)0.5932617187500f, +(float16_t)0.8041992187500f,(float16_t)0.5942382812500f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.8022460937500f,(float16_t)0.5971679687500f, +(float16_t)0.8012695312500f,(float16_t)0.5981445312500f, +(float16_t)0.8002929687500f,(float16_t)0.5996093750000f, +(float16_t)0.7993164062500f,(float16_t)0.6005859375000f, +(float16_t)0.7988281250000f,(float16_t)0.6020507812500f, +(float16_t)0.7978515625000f,(float16_t)0.6030273437500f, +(float16_t)0.7968750000000f,(float16_t)0.6044921875000f, +(float16_t)0.7958984375000f,(float16_t)0.6054687500000f, +(float16_t)0.7949218750000f,(float16_t)0.6069335937500f, +(float16_t)0.7939453125000f,(float16_t)0.6079101562500f, +(float16_t)0.7929687500000f,(float16_t)0.6093750000000f, +(float16_t)0.7919921875000f,(float16_t)0.6103515625000f, +(float16_t)0.7910156250000f,(float16_t)0.6118164062500f, +(float16_t)0.7900390625000f,(float16_t)0.6127929687500f, +(float16_t)0.7890625000000f,(float16_t)0.6142578125000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7875976562500f,(float16_t)0.6162109375000f, +(float16_t)0.7866210937500f,(float16_t)0.6176757812500f, +(float16_t)0.7856445312500f,(float16_t)0.6186523437500f, +(float16_t)0.7846679687500f,(float16_t)0.6201171875000f, +(float16_t)0.7836914062500f,(float16_t)0.6210937500000f, +(float16_t)0.7827148437500f,(float16_t)0.6225585937500f, +(float16_t)0.7817382812500f,(float16_t)0.6235351562500f, +(float16_t)0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)0.7797851562500f,(float16_t)0.6259765625000f, +(float16_t)0.7788085937500f,(float16_t)0.6274414062500f, +(float16_t)0.7778320312500f,(float16_t)0.6284179687500f, +(float16_t)0.7768554687500f,(float16_t)0.6293945312500f, +(float16_t)0.7758789062500f,(float16_t)0.6308593750000f, +(float16_t)0.7749023437500f,(float16_t)0.6318359375000f, +(float16_t)0.7739257812500f,(float16_t)0.6333007812500f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7719726562500f,(float16_t)0.6357421875000f, +(float16_t)0.7709960937500f,(float16_t)0.6367187500000f, +(float16_t)0.7700195312500f,(float16_t)0.6381835937500f, +(float16_t)0.7690429687500f,(float16_t)0.6391601562500f, +(float16_t)0.7680664062500f,(float16_t)0.6401367187500f, +(float16_t)0.7670898437500f,(float16_t)0.6416015625000f, +(float16_t)0.7661132812500f,(float16_t)0.6425781250000f, +(float16_t)0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)0.7641601562500f,(float16_t)0.6450195312500f, +(float16_t)0.7631835937500f,(float16_t)0.6459960937500f, +(float16_t)0.7622070312500f,(float16_t)0.6474609375000f, +(float16_t)0.7612304687500f,(float16_t)0.6484375000000f, +(float16_t)0.7602539062500f,(float16_t)0.6499023437500f, +(float16_t)0.7592773437500f,(float16_t)0.6508789062500f, +(float16_t)0.7583007812500f,(float16_t)0.6518554687500f, +(float16_t)0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)0.7563476562500f,(float16_t)0.6542968750000f, +(float16_t)0.7553710937500f,(float16_t)0.6552734375000f, +(float16_t)0.7543945312500f,(float16_t)0.6567382812500f, +(float16_t)0.7534179687500f,(float16_t)0.6577148437500f, +(float16_t)0.7519531250000f,(float16_t)0.6591796875000f, +(float16_t)0.7509765625000f,(float16_t)0.6601562500000f, +(float16_t)0.7500000000000f,(float16_t)0.6611328125000f, +(float16_t)0.7490234375000f,(float16_t)0.6625976562500f, +(float16_t)0.7480468750000f,(float16_t)0.6635742187500f, +(float16_t)0.7470703125000f,(float16_t)0.6645507812500f, +(float16_t)0.7460937500000f,(float16_t)0.6660156250000f, +(float16_t)0.7451171875000f,(float16_t)0.6669921875000f, +(float16_t)0.7441406250000f,(float16_t)0.6679687500000f, +(float16_t)0.7431640625000f,(float16_t)0.6694335937500f, +(float16_t)0.7421875000000f,(float16_t)0.6704101562500f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7397460937500f,(float16_t)0.6728515625000f, +(float16_t)0.7387695312500f,(float16_t)0.6738281250000f, +(float16_t)0.7377929687500f,(float16_t)0.6748046875000f, +(float16_t)0.7368164062500f,(float16_t)0.6762695312500f, +(float16_t)0.7358398437500f,(float16_t)0.6772460937500f, +(float16_t)0.7348632812500f,(float16_t)0.6782226562500f, +(float16_t)0.7338867187500f,(float16_t)0.6796875000000f, +(float16_t)0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)0.7314453125000f,(float16_t)0.6816406250000f, +(float16_t)0.7304687500000f,(float16_t)0.6826171875000f, +(float16_t)0.7294921875000f,(float16_t)0.6840820312500f, +(float16_t)0.7285156250000f,(float16_t)0.6850585937500f, +(float16_t)0.7275390625000f,(float16_t)0.6860351562500f, +(float16_t)0.7265625000000f,(float16_t)0.6875000000000f, +(float16_t)0.7250976562500f,(float16_t)0.6884765625000f, +(float16_t)0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)0.7231445312500f,(float16_t)0.6904296875000f, +(float16_t)0.7221679687500f,(float16_t)0.6918945312500f, +(float16_t)0.7211914062500f,(float16_t)0.6928710937500f, +(float16_t)0.7202148437500f,(float16_t)0.6938476562500f, +(float16_t)0.7187500000000f,(float16_t)0.6953125000000f, +(float16_t)0.7177734375000f,(float16_t)0.6962890625000f, +(float16_t)0.7167968750000f,(float16_t)0.6972656250000f, +(float16_t)0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)0.7148437500000f,(float16_t)0.6997070312500f, +(float16_t)0.7133789062500f,(float16_t)0.7006835937500f, +(float16_t)0.7124023437500f,(float16_t)0.7016601562500f, +(float16_t)0.7114257812500f,(float16_t)0.7026367187500f, +(float16_t)0.7104492187500f,(float16_t)0.7036132812500f, +(float16_t)0.7094726562500f,(float16_t)0.7050781250000f, +(float16_t)0.7080078125000f,(float16_t)0.7060546875000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.7060546875000f,(float16_t)0.7080078125000f, +(float16_t)0.7050781250000f,(float16_t)0.7094726562500f, +(float16_t)0.7036132812500f,(float16_t)0.7104492187500f, +(float16_t)0.7026367187500f,(float16_t)0.7114257812500f, +(float16_t)0.7016601562500f,(float16_t)0.7124023437500f, +(float16_t)0.7006835937500f,(float16_t)0.7133789062500f, +(float16_t)0.6997070312500f,(float16_t)0.7148437500000f, +(float16_t)0.6982421875000f,(float16_t)0.7158203125000f, +(float16_t)0.6972656250000f,(float16_t)0.7167968750000f, +(float16_t)0.6962890625000f,(float16_t)0.7177734375000f, +(float16_t)0.6953125000000f,(float16_t)0.7187500000000f, +(float16_t)0.6938476562500f,(float16_t)0.7202148437500f, +(float16_t)0.6928710937500f,(float16_t)0.7211914062500f, +(float16_t)0.6918945312500f,(float16_t)0.7221679687500f, +(float16_t)0.6904296875000f,(float16_t)0.7231445312500f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6884765625000f,(float16_t)0.7250976562500f, +(float16_t)0.6875000000000f,(float16_t)0.7265625000000f, +(float16_t)0.6860351562500f,(float16_t)0.7275390625000f, +(float16_t)0.6850585937500f,(float16_t)0.7285156250000f, +(float16_t)0.6840820312500f,(float16_t)0.7294921875000f, +(float16_t)0.6826171875000f,(float16_t)0.7304687500000f, +(float16_t)0.6816406250000f,(float16_t)0.7314453125000f, +(float16_t)0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)0.6796875000000f,(float16_t)0.7338867187500f, +(float16_t)0.6782226562500f,(float16_t)0.7348632812500f, +(float16_t)0.6772460937500f,(float16_t)0.7358398437500f, +(float16_t)0.6762695312500f,(float16_t)0.7368164062500f, +(float16_t)0.6748046875000f,(float16_t)0.7377929687500f, +(float16_t)0.6738281250000f,(float16_t)0.7387695312500f, +(float16_t)0.6728515625000f,(float16_t)0.7397460937500f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6704101562500f,(float16_t)0.7421875000000f, +(float16_t)0.6694335937500f,(float16_t)0.7431640625000f, +(float16_t)0.6679687500000f,(float16_t)0.7441406250000f, +(float16_t)0.6669921875000f,(float16_t)0.7451171875000f, +(float16_t)0.6660156250000f,(float16_t)0.7460937500000f, +(float16_t)0.6645507812500f,(float16_t)0.7470703125000f, +(float16_t)0.6635742187500f,(float16_t)0.7480468750000f, +(float16_t)0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)0.6611328125000f,(float16_t)0.7500000000000f, +(float16_t)0.6601562500000f,(float16_t)0.7509765625000f, +(float16_t)0.6591796875000f,(float16_t)0.7519531250000f, +(float16_t)0.6577148437500f,(float16_t)0.7534179687500f, +(float16_t)0.6567382812500f,(float16_t)0.7543945312500f, +(float16_t)0.6552734375000f,(float16_t)0.7553710937500f, +(float16_t)0.6542968750000f,(float16_t)0.7563476562500f, +(float16_t)0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)0.6518554687500f,(float16_t)0.7583007812500f, +(float16_t)0.6508789062500f,(float16_t)0.7592773437500f, +(float16_t)0.6499023437500f,(float16_t)0.7602539062500f, +(float16_t)0.6484375000000f,(float16_t)0.7612304687500f, +(float16_t)0.6474609375000f,(float16_t)0.7622070312500f, +(float16_t)0.6459960937500f,(float16_t)0.7631835937500f, +(float16_t)0.6450195312500f,(float16_t)0.7641601562500f, +(float16_t)0.6440429687500f,(float16_t)0.7651367187500f, +(float16_t)0.6425781250000f,(float16_t)0.7661132812500f, +(float16_t)0.6416015625000f,(float16_t)0.7670898437500f, +(float16_t)0.6401367187500f,(float16_t)0.7680664062500f, +(float16_t)0.6391601562500f,(float16_t)0.7690429687500f, +(float16_t)0.6381835937500f,(float16_t)0.7700195312500f, +(float16_t)0.6367187500000f,(float16_t)0.7709960937500f, +(float16_t)0.6357421875000f,(float16_t)0.7719726562500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6333007812500f,(float16_t)0.7739257812500f, +(float16_t)0.6318359375000f,(float16_t)0.7749023437500f, +(float16_t)0.6308593750000f,(float16_t)0.7758789062500f, +(float16_t)0.6293945312500f,(float16_t)0.7768554687500f, +(float16_t)0.6284179687500f,(float16_t)0.7778320312500f, +(float16_t)0.6274414062500f,(float16_t)0.7788085937500f, +(float16_t)0.6259765625000f,(float16_t)0.7797851562500f, +(float16_t)0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)0.6235351562500f,(float16_t)0.7817382812500f, +(float16_t)0.6225585937500f,(float16_t)0.7827148437500f, +(float16_t)0.6210937500000f,(float16_t)0.7836914062500f, +(float16_t)0.6201171875000f,(float16_t)0.7846679687500f, +(float16_t)0.6186523437500f,(float16_t)0.7856445312500f, +(float16_t)0.6176757812500f,(float16_t)0.7866210937500f, +(float16_t)0.6162109375000f,(float16_t)0.7875976562500f, +(float16_t)0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)0.6142578125000f,(float16_t)0.7890625000000f, +(float16_t)0.6127929687500f,(float16_t)0.7900390625000f, +(float16_t)0.6118164062500f,(float16_t)0.7910156250000f, +(float16_t)0.6103515625000f,(float16_t)0.7919921875000f, +(float16_t)0.6093750000000f,(float16_t)0.7929687500000f, +(float16_t)0.6079101562500f,(float16_t)0.7939453125000f, +(float16_t)0.6069335937500f,(float16_t)0.7949218750000f, +(float16_t)0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)0.6044921875000f,(float16_t)0.7968750000000f, +(float16_t)0.6030273437500f,(float16_t)0.7978515625000f, +(float16_t)0.6020507812500f,(float16_t)0.7988281250000f, +(float16_t)0.6005859375000f,(float16_t)0.7993164062500f, +(float16_t)0.5996093750000f,(float16_t)0.8002929687500f, +(float16_t)0.5981445312500f,(float16_t)0.8012695312500f, +(float16_t)0.5971679687500f,(float16_t)0.8022460937500f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5942382812500f,(float16_t)0.8041992187500f, +(float16_t)0.5932617187500f,(float16_t)0.8051757812500f, +(float16_t)0.5917968750000f,(float16_t)0.8061523437500f, +(float16_t)0.5908203125000f,(float16_t)0.8066406250000f, +(float16_t)0.5893554687500f,(float16_t)0.8076171875000f, +(float16_t)0.5883789062500f,(float16_t)0.8085937500000f, +(float16_t)0.5869140625000f,(float16_t)0.8095703125000f, +(float16_t)0.5859375000000f,(float16_t)0.8105468750000f, +(float16_t)0.5844726562500f,(float16_t)0.8115234375000f, +(float16_t)0.5834960937500f,(float16_t)0.8120117187500f, +(float16_t)0.5820312500000f,(float16_t)0.8129882812500f, +(float16_t)0.5810546875000f,(float16_t)0.8139648437500f, +(float16_t)0.5795898437500f,(float16_t)0.8149414062500f, +(float16_t)0.5781250000000f,(float16_t)0.8159179687500f, +(float16_t)0.5771484375000f,(float16_t)0.8168945312500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5747070312500f,(float16_t)0.8183593750000f, +(float16_t)0.5732421875000f,(float16_t)0.8193359375000f, +(float16_t)0.5722656250000f,(float16_t)0.8203125000000f, +(float16_t)0.5708007812500f,(float16_t)0.8212890625000f, +(float16_t)0.5693359375000f,(float16_t)0.8217773437500f, +(float16_t)0.5683593750000f,(float16_t)0.8227539062500f, +(float16_t)0.5668945312500f,(float16_t)0.8237304687500f, +(float16_t)0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)0.5644531250000f,(float16_t)0.8256835937500f, +(float16_t)0.5629882812500f,(float16_t)0.8261718750000f, +(float16_t)0.5620117187500f,(float16_t)0.8271484375000f, +(float16_t)0.5605468750000f,(float16_t)0.8281250000000f, +(float16_t)0.5595703125000f,(float16_t)0.8291015625000f, +(float16_t)0.5581054687500f,(float16_t)0.8295898437500f, +(float16_t)0.5566406250000f,(float16_t)0.8305664062500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5541992187500f,(float16_t)0.8325195312500f, +(float16_t)0.5532226562500f,(float16_t)0.8330078125000f, +(float16_t)0.5517578125000f,(float16_t)0.8339843750000f, +(float16_t)0.5502929687500f,(float16_t)0.8349609375000f, +(float16_t)0.5493164062500f,(float16_t)0.8359375000000f, +(float16_t)0.5478515625000f,(float16_t)0.8364257812500f, +(float16_t)0.5463867187500f,(float16_t)0.8374023437500f, +(float16_t)0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)0.5439453125000f,(float16_t)0.8388671875000f, +(float16_t)0.5429687500000f,(float16_t)0.8398437500000f, +(float16_t)0.5415039062500f,(float16_t)0.8408203125000f, +(float16_t)0.5400390625000f,(float16_t)0.8417968750000f, +(float16_t)0.5390625000000f,(float16_t)0.8422851562500f, +(float16_t)0.5375976562500f,(float16_t)0.8432617187500f, +(float16_t)0.5361328125000f,(float16_t)0.8442382812500f, +(float16_t)0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)0.5336914062500f,(float16_t)0.8457031250000f, +(float16_t)0.5322265625000f,(float16_t)0.8466796875000f, +(float16_t)0.5312500000000f,(float16_t)0.8471679687500f, +(float16_t)0.5297851562500f,(float16_t)0.8481445312500f, +(float16_t)0.5283203125000f,(float16_t)0.8491210937500f, +(float16_t)0.5273437500000f,(float16_t)0.8496093750000f, +(float16_t)0.5258789062500f,(float16_t)0.8505859375000f, +(float16_t)0.5244140625000f,(float16_t)0.8515625000000f, +(float16_t)0.5234375000000f,(float16_t)0.8520507812500f, +(float16_t)0.5219726562500f,(float16_t)0.8530273437500f, +(float16_t)0.5205078125000f,(float16_t)0.8540039062500f, +(float16_t)0.5195312500000f,(float16_t)0.8544921875000f, +(float16_t)0.5180664062500f,(float16_t)0.8554687500000f, +(float16_t)0.5166015625000f,(float16_t)0.8559570312500f, +(float16_t)0.5156250000000f,(float16_t)0.8569335937500f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.5126953125000f,(float16_t)0.8583984375000f, +(float16_t)0.5112304687500f,(float16_t)0.8593750000000f, +(float16_t)0.5102539062500f,(float16_t)0.8598632812500f, +(float16_t)0.5087890625000f,(float16_t)0.8608398437500f, +(float16_t)0.5073242187500f,(float16_t)0.8618164062500f, +(float16_t)0.5063476562500f,(float16_t)0.8623046875000f, +(float16_t)0.5048828125000f,(float16_t)0.8632812500000f, +(float16_t)0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)0.5024414062500f,(float16_t)0.8647460937500f, +(float16_t)0.5009765625000f,(float16_t)0.8657226562500f, +(float16_t)0.4995117187500f,(float16_t)0.8662109375000f, +(float16_t)0.4982910156250f,(float16_t)0.8671875000000f, +(float16_t)0.4968261718750f,(float16_t)0.8676757812500f, +(float16_t)0.4956054687500f,(float16_t)0.8686523437500f, +(float16_t)0.4941406250000f,(float16_t)0.8691406250000f, +(float16_t)0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)0.4914550781250f,(float16_t)0.8706054687500f, +(float16_t)0.4902343750000f,(float16_t)0.8715820312500f, +(float16_t)0.4887695312500f,(float16_t)0.8725585937500f, +(float16_t)0.4875488281250f,(float16_t)0.8730468750000f, +(float16_t)0.4863281250000f,(float16_t)0.8740234375000f, +(float16_t)0.4848632812500f,(float16_t)0.8745117187500f, +(float16_t)0.4836425781250f,(float16_t)0.8754882812500f, +(float16_t)0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)0.4809570312500f,(float16_t)0.8769531250000f, +(float16_t)0.4794921875000f,(float16_t)0.8774414062500f, +(float16_t)0.4780273437500f,(float16_t)0.8784179687500f, +(float16_t)0.4768066406250f,(float16_t)0.8789062500000f, +(float16_t)0.4753417968750f,(float16_t)0.8798828125000f, +(float16_t)0.4741210937500f,(float16_t)0.8803710937500f, +(float16_t)0.4726562500000f,(float16_t)0.8813476562500f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4699707031250f,(float16_t)0.8828125000000f, +(float16_t)0.4687500000000f,(float16_t)0.8833007812500f, +(float16_t)0.4672851562500f,(float16_t)0.8842773437500f, +(float16_t)0.4660644531250f,(float16_t)0.8847656250000f, +(float16_t)0.4645996093750f,(float16_t)0.8857421875000f, +(float16_t)0.4633789062500f,(float16_t)0.8862304687500f, +(float16_t)0.4619140625000f,(float16_t)0.8867187500000f, +(float16_t)0.4604492187500f,(float16_t)0.8876953125000f, +(float16_t)0.4592285156250f,(float16_t)0.8881835937500f, +(float16_t)0.4577636718750f,(float16_t)0.8891601562500f, +(float16_t)0.4565429687500f,(float16_t)0.8896484375000f, +(float16_t)0.4550781250000f,(float16_t)0.8906250000000f, +(float16_t)0.4536132812500f,(float16_t)0.8911132812500f, +(float16_t)0.4523925781250f,(float16_t)0.8916015625000f, +(float16_t)0.4509277343750f,(float16_t)0.8925781250000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4482421875000f,(float16_t)0.8940429687500f, +(float16_t)0.4467773437500f,(float16_t)0.8945312500000f, +(float16_t)0.4455566406250f,(float16_t)0.8955078125000f, +(float16_t)0.4440917968750f,(float16_t)0.8959960937500f, +(float16_t)0.4426269531250f,(float16_t)0.8964843750000f, +(float16_t)0.4414062500000f,(float16_t)0.8974609375000f, +(float16_t)0.4399414062500f,(float16_t)0.8979492187500f, +(float16_t)0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)0.4372558593750f,(float16_t)0.8994140625000f, +(float16_t)0.4357910156250f,(float16_t)0.8999023437500f, +(float16_t)0.4345703125000f,(float16_t)0.9008789062500f, +(float16_t)0.4331054687500f,(float16_t)0.9013671875000f, +(float16_t)0.4316406250000f,(float16_t)0.9018554687500f, +(float16_t)0.4304199218750f,(float16_t)0.9028320312500f, +(float16_t)0.4289550781250f,(float16_t)0.9033203125000f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.4262695312500f,(float16_t)0.9047851562500f, +(float16_t)0.4248046875000f,(float16_t)0.9052734375000f, +(float16_t)0.4233398437500f,(float16_t)0.9057617187500f, +(float16_t)0.4221191406250f,(float16_t)0.9067382812500f, +(float16_t)0.4206542968750f,(float16_t)0.9072265625000f, +(float16_t)0.4191894531250f,(float16_t)0.9077148437500f, +(float16_t)0.4177246093750f,(float16_t)0.9086914062500f, +(float16_t)0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)0.4150390625000f,(float16_t)0.9096679687500f, +(float16_t)0.4135742187500f,(float16_t)0.9106445312500f, +(float16_t)0.4123535156250f,(float16_t)0.9111328125000f, +(float16_t)0.4108886718750f,(float16_t)0.9116210937500f, +(float16_t)0.4094238281250f,(float16_t)0.9121093750000f, +(float16_t)0.4079589843750f,(float16_t)0.9130859375000f, +(float16_t)0.4067382812500f,(float16_t)0.9135742187500f, +(float16_t)0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)0.4038085937500f,(float16_t)0.9150390625000f, +(float16_t)0.4023437500000f,(float16_t)0.9155273437500f, +(float16_t)0.4011230468750f,(float16_t)0.9160156250000f, +(float16_t)0.3996582031250f,(float16_t)0.9165039062500f, +(float16_t)0.3981933593750f,(float16_t)0.9174804687500f, +(float16_t)0.3967285156250f,(float16_t)0.9179687500000f, +(float16_t)0.3955078125000f,(float16_t)0.9184570312500f, +(float16_t)0.3940429687500f,(float16_t)0.9189453125000f, +(float16_t)0.3925781250000f,(float16_t)0.9199218750000f, +(float16_t)0.3911132812500f,(float16_t)0.9204101562500f, +(float16_t)0.3896484375000f,(float16_t)0.9208984375000f, +(float16_t)0.3884277343750f,(float16_t)0.9213867187500f, +(float16_t)0.3869628906250f,(float16_t)0.9218750000000f, +(float16_t)0.3854980468750f,(float16_t)0.9228515625000f, +(float16_t)0.3840332031250f,(float16_t)0.9233398437500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3813476562500f,(float16_t)0.9243164062500f, +(float16_t)0.3798828125000f,(float16_t)0.9252929687500f, +(float16_t)0.3784179687500f,(float16_t)0.9257812500000f, +(float16_t)0.3769531250000f,(float16_t)0.9262695312500f, +(float16_t)0.3754882812500f,(float16_t)0.9267578125000f, +(float16_t)0.3742675781250f,(float16_t)0.9272460937500f, +(float16_t)0.3728027343750f,(float16_t)0.9277343750000f, +(float16_t)0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)0.3698730468750f,(float16_t)0.9291992187500f, +(float16_t)0.3684082031250f,(float16_t)0.9296875000000f, +(float16_t)0.3669433593750f,(float16_t)0.9301757812500f, +(float16_t)0.3657226562500f,(float16_t)0.9306640625000f, +(float16_t)0.3642578125000f,(float16_t)0.9311523437500f, +(float16_t)0.3627929687500f,(float16_t)0.9316406250000f, +(float16_t)0.3613281250000f,(float16_t)0.9326171875000f, +(float16_t)0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)0.3583984375000f,(float16_t)0.9335937500000f, +(float16_t)0.3569335937500f,(float16_t)0.9340820312500f, +(float16_t)0.3557128906250f,(float16_t)0.9345703125000f, +(float16_t)0.3542480468750f,(float16_t)0.9350585937500f, +(float16_t)0.3527832031250f,(float16_t)0.9355468750000f, +(float16_t)0.3513183593750f,(float16_t)0.9360351562500f, +(float16_t)0.3498535156250f,(float16_t)0.9370117187500f, +(float16_t)0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)0.3469238281250f,(float16_t)0.9379882812500f, +(float16_t)0.3454589843750f,(float16_t)0.9384765625000f, +(float16_t)0.3439941406250f,(float16_t)0.9389648437500f, +(float16_t)0.3427734375000f,(float16_t)0.9394531250000f, +(float16_t)0.3413085937500f,(float16_t)0.9399414062500f, +(float16_t)0.3398437500000f,(float16_t)0.9404296875000f, +(float16_t)0.3383789062500f,(float16_t)0.9409179687500f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.3354492187500f,(float16_t)0.9418945312500f, +(float16_t)0.3339843750000f,(float16_t)0.9423828125000f, +(float16_t)0.3325195312500f,(float16_t)0.9428710937500f, +(float16_t)0.3310546875000f,(float16_t)0.9433593750000f, +(float16_t)0.3295898437500f,(float16_t)0.9443359375000f, +(float16_t)0.3281250000000f,(float16_t)0.9448242187500f, +(float16_t)0.3266601562500f,(float16_t)0.9453125000000f, +(float16_t)0.3251953125000f,(float16_t)0.9458007812500f, +(float16_t)0.3239746093750f,(float16_t)0.9462890625000f, +(float16_t)0.3225097656250f,(float16_t)0.9467773437500f, +(float16_t)0.3210449218750f,(float16_t)0.9472656250000f, +(float16_t)0.3195800781250f,(float16_t)0.9477539062500f, +(float16_t)0.3181152343750f,(float16_t)0.9482421875000f, +(float16_t)0.3166503906250f,(float16_t)0.9487304687500f, +(float16_t)0.3151855468750f,(float16_t)0.9492187500000f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.3122558593750f,(float16_t)0.9501953125000f, +(float16_t)0.3107910156250f,(float16_t)0.9506835937500f, +(float16_t)0.3093261718750f,(float16_t)0.9511718750000f, +(float16_t)0.3078613281250f,(float16_t)0.9516601562500f, +(float16_t)0.3063964843750f,(float16_t)0.9521484375000f, +(float16_t)0.3049316406250f,(float16_t)0.9521484375000f, +(float16_t)0.3034667968750f,(float16_t)0.9526367187500f, +(float16_t)0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)0.3005371093750f,(float16_t)0.9536132812500f, +(float16_t)0.2990722656250f,(float16_t)0.9541015625000f, +(float16_t)0.2976074218750f,(float16_t)0.9545898437500f, +(float16_t)0.2961425781250f,(float16_t)0.9550781250000f, +(float16_t)0.2946777343750f,(float16_t)0.9555664062500f, +(float16_t)0.2932128906250f,(float16_t)0.9560546875000f, +(float16_t)0.2917480468750f,(float16_t)0.9565429687500f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2888183593750f,(float16_t)0.9575195312500f, +(float16_t)0.2873535156250f,(float16_t)0.9580078125000f, +(float16_t)0.2858886718750f,(float16_t)0.9584960937500f, +(float16_t)0.2844238281250f,(float16_t)0.9584960937500f, +(float16_t)0.2829589843750f,(float16_t)0.9589843750000f, +(float16_t)0.2814941406250f,(float16_t)0.9594726562500f, +(float16_t)0.2800292968750f,(float16_t)0.9599609375000f, +(float16_t)0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)0.2770996093750f,(float16_t)0.9609375000000f, +(float16_t)0.2756347656250f,(float16_t)0.9614257812500f, +(float16_t)0.2741699218750f,(float16_t)0.9619140625000f, +(float16_t)0.2727050781250f,(float16_t)0.9619140625000f, +(float16_t)0.2712402343750f,(float16_t)0.9624023437500f, +(float16_t)0.2697753906250f,(float16_t)0.9628906250000f, +(float16_t)0.2683105468750f,(float16_t)0.9633789062500f, +(float16_t)0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)0.2651367187500f,(float16_t)0.9643554687500f, +(float16_t)0.2636718750000f,(float16_t)0.9643554687500f, +(float16_t)0.2622070312500f,(float16_t)0.9648437500000f, +(float16_t)0.2607421875000f,(float16_t)0.9653320312500f, +(float16_t)0.2592773437500f,(float16_t)0.9658203125000f, +(float16_t)0.2578125000000f,(float16_t)0.9663085937500f, +(float16_t)0.2563476562500f,(float16_t)0.9667968750000f, +(float16_t)0.2548828125000f,(float16_t)0.9667968750000f, +(float16_t)0.2534179687500f,(float16_t)0.9672851562500f, +(float16_t)0.2519531250000f,(float16_t)0.9677734375000f, +(float16_t)0.2504882812500f,(float16_t)0.9682617187500f, +(float16_t)0.2489013671875f,(float16_t)0.9687500000000f, +(float16_t)0.2474365234375f,(float16_t)0.9687500000000f, +(float16_t)0.2459716796875f,(float16_t)0.9692382812500f, +(float16_t)0.2445068359375f,(float16_t)0.9697265625000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2414550781250f,(float16_t)0.9702148437500f, +(float16_t)0.2399902343750f,(float16_t)0.9707031250000f, +(float16_t)0.2385253906250f,(float16_t)0.9711914062500f, +(float16_t)0.2370605468750f,(float16_t)0.9716796875000f, +(float16_t)0.2354736328125f,(float16_t)0.9716796875000f, +(float16_t)0.2340087890625f,(float16_t)0.9721679687500f, +(float16_t)0.2325439453125f,(float16_t)0.9726562500000f, +(float16_t)0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)0.2296142578125f,(float16_t)0.9731445312500f, +(float16_t)0.2280273437500f,(float16_t)0.9736328125000f, +(float16_t)0.2265625000000f,(float16_t)0.9741210937500f, +(float16_t)0.2250976562500f,(float16_t)0.9741210937500f, +(float16_t)0.2236328125000f,(float16_t)0.9746093750000f, +(float16_t)0.2220458984375f,(float16_t)0.9750976562500f, +(float16_t)0.2205810546875f,(float16_t)0.9755859375000f, +(float16_t)0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)0.2176513671875f,(float16_t)0.9760742187500f, +(float16_t)0.2160644531250f,(float16_t)0.9765625000000f, +(float16_t)0.2145996093750f,(float16_t)0.9765625000000f, +(float16_t)0.2131347656250f,(float16_t)0.9770507812500f, +(float16_t)0.2116699218750f,(float16_t)0.9775390625000f, +(float16_t)0.2100830078125f,(float16_t)0.9775390625000f, +(float16_t)0.2086181640625f,(float16_t)0.9780273437500f, +(float16_t)0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)0.2055664062500f,(float16_t)0.9785156250000f, +(float16_t)0.2041015625000f,(float16_t)0.9790039062500f, +(float16_t)0.2026367187500f,(float16_t)0.9794921875000f, +(float16_t)0.2010498046875f,(float16_t)0.9794921875000f, +(float16_t)0.1995849609375f,(float16_t)0.9799804687500f, +(float16_t)0.1981201171875f,(float16_t)0.9799804687500f, +(float16_t)0.1966552734375f,(float16_t)0.9804687500000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1936035156250f,(float16_t)0.9809570312500f, +(float16_t)0.1921386718750f,(float16_t)0.9814453125000f, +(float16_t)0.1905517578125f,(float16_t)0.9814453125000f, +(float16_t)0.1890869140625f,(float16_t)0.9819335937500f, +(float16_t)0.1876220703125f,(float16_t)0.9824218750000f, +(float16_t)0.1860351562500f,(float16_t)0.9824218750000f, +(float16_t)0.1845703125000f,(float16_t)0.9829101562500f, +(float16_t)0.1829833984375f,(float16_t)0.9829101562500f, +(float16_t)0.1815185546875f,(float16_t)0.9833984375000f, +(float16_t)0.1800537109375f,(float16_t)0.9838867187500f, +(float16_t)0.1784667968750f,(float16_t)0.9838867187500f, +(float16_t)0.1770019531250f,(float16_t)0.9843750000000f, +(float16_t)0.1755371093750f,(float16_t)0.9843750000000f, +(float16_t)0.1739501953125f,(float16_t)0.9848632812500f, +(float16_t)0.1724853515625f,(float16_t)0.9848632812500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1694335937500f,(float16_t)0.9853515625000f, +(float16_t)0.1679687500000f,(float16_t)0.9858398437500f, +(float16_t)0.1663818359375f,(float16_t)0.9858398437500f, +(float16_t)0.1649169921875f,(float16_t)0.9863281250000f, +(float16_t)0.1634521484375f,(float16_t)0.9863281250000f, +(float16_t)0.1618652343750f,(float16_t)0.9868164062500f, +(float16_t)0.1604003906250f,(float16_t)0.9868164062500f, +(float16_t)0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)0.1573486328125f,(float16_t)0.9873046875000f, +(float16_t)0.1558837890625f,(float16_t)0.9877929687500f, +(float16_t)0.1542968750000f,(float16_t)0.9877929687500f, +(float16_t)0.1528320312500f,(float16_t)0.9882812500000f, +(float16_t)0.1512451171875f,(float16_t)0.9882812500000f, +(float16_t)0.1497802734375f,(float16_t)0.9887695312500f, +(float16_t)0.1481933593750f,(float16_t)0.9887695312500f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.1452636718750f,(float16_t)0.9892578125000f, +(float16_t)0.1436767578125f,(float16_t)0.9897460937500f, +(float16_t)0.1422119140625f,(float16_t)0.9897460937500f, +(float16_t)0.1406250000000f,(float16_t)0.9902343750000f, +(float16_t)0.1391601562500f,(float16_t)0.9902343750000f, +(float16_t)0.1375732421875f,(float16_t)0.9907226562500f, +(float16_t)0.1361083984375f,(float16_t)0.9907226562500f, +(float16_t)0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)0.1330566406250f,(float16_t)0.9912109375000f, +(float16_t)0.1315917968750f,(float16_t)0.9912109375000f, +(float16_t)0.1300048828125f,(float16_t)0.9916992187500f, +(float16_t)0.1285400390625f,(float16_t)0.9916992187500f, +(float16_t)0.1269531250000f,(float16_t)0.9916992187500f, +(float16_t)0.1254882812500f,(float16_t)0.9921875000000f, +(float16_t)0.1239624023438f,(float16_t)0.9921875000000f, +(float16_t)0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)0.1209106445312f,(float16_t)0.9926757812500f, +(float16_t)0.1193847656250f,(float16_t)0.9926757812500f, +(float16_t)0.1178588867188f,(float16_t)0.9931640625000f, +(float16_t)0.1163330078125f,(float16_t)0.9931640625000f, +(float16_t)0.1148071289062f,(float16_t)0.9931640625000f, +(float16_t)0.1132812500000f,(float16_t)0.9936523437500f, +(float16_t)0.1117553710938f,(float16_t)0.9936523437500f, +(float16_t)0.1102294921875f,(float16_t)0.9941406250000f, +(float16_t)0.1087036132812f,(float16_t)0.9941406250000f, +(float16_t)0.1071777343750f,(float16_t)0.9941406250000f, +(float16_t)0.1056518554688f,(float16_t)0.9946289062500f, +(float16_t)0.1041259765625f,(float16_t)0.9946289062500f, +(float16_t)0.1026000976562f,(float16_t)0.9946289062500f, +(float16_t)0.1010742187500f,(float16_t)0.9951171875000f, +(float16_t)0.0995483398438f,(float16_t)0.9951171875000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0964965820312f,(float16_t)0.9951171875000f, +(float16_t)0.0949707031250f,(float16_t)0.9956054687500f, +(float16_t)0.0934448242188f,(float16_t)0.9956054687500f, +(float16_t)0.0919189453125f,(float16_t)0.9956054687500f, +(float16_t)0.0903930664062f,(float16_t)0.9960937500000f, +(float16_t)0.0888671875000f,(float16_t)0.9960937500000f, +(float16_t)0.0873413085938f,(float16_t)0.9960937500000f, +(float16_t)0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)0.0842895507812f,(float16_t)0.9965820312500f, +(float16_t)0.0827636718750f,(float16_t)0.9965820312500f, +(float16_t)0.0812377929688f,(float16_t)0.9965820312500f, +(float16_t)0.0797119140625f,(float16_t)0.9965820312500f, +(float16_t)0.0781250000000f,(float16_t)0.9970703125000f, +(float16_t)0.0765991210938f,(float16_t)0.9970703125000f, +(float16_t)0.0750732421875f,(float16_t)0.9970703125000f, +(float16_t)0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)0.0720214843750f,(float16_t)0.9975585937500f, +(float16_t)0.0704956054688f,(float16_t)0.9975585937500f, +(float16_t)0.0689697265625f,(float16_t)0.9975585937500f, +(float16_t)0.0674438476562f,(float16_t)0.9975585937500f, +(float16_t)0.0659179687500f,(float16_t)0.9980468750000f, +(float16_t)0.0643920898438f,(float16_t)0.9980468750000f, +(float16_t)0.0628662109375f,(float16_t)0.9980468750000f, +(float16_t)0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)0.0597839355469f,(float16_t)0.9980468750000f, +(float16_t)0.0582580566406f,(float16_t)0.9985351562500f, +(float16_t)0.0567321777344f,(float16_t)0.9985351562500f, +(float16_t)0.0552062988281f,(float16_t)0.9985351562500f, +(float16_t)0.0536499023438f,(float16_t)0.9985351562500f, +(float16_t)0.0521240234375f,(float16_t)0.9985351562500f, +(float16_t)0.0505981445312f,(float16_t)0.9985351562500f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0475463867188f,(float16_t)0.9990234375000f, +(float16_t)0.0459899902344f,(float16_t)0.9990234375000f, +(float16_t)0.0444641113281f,(float16_t)0.9990234375000f, +(float16_t)0.0429382324219f,(float16_t)0.9990234375000f, +(float16_t)0.0414123535156f,(float16_t)0.9990234375000f, +(float16_t)0.0398864746094f,(float16_t)0.9990234375000f, +(float16_t)0.0383300781250f,(float16_t)0.9990234375000f, +(float16_t)0.0368041992188f,(float16_t)0.9995117187500f, +(float16_t)0.0352783203125f,(float16_t)0.9995117187500f, +(float16_t)0.0337524414062f,(float16_t)0.9995117187500f, +(float16_t)0.0321960449219f,(float16_t)0.9995117187500f, +(float16_t)0.0306701660156f,(float16_t)0.9995117187500f, +(float16_t)0.0291442871094f,(float16_t)0.9995117187500f, +(float16_t)0.0276031494141f,(float16_t)0.9995117187500f, +(float16_t)0.0260772705078f,(float16_t)0.9995117187500f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)0.0230102539062f,(float16_t)0.9995117187500f, +(float16_t)0.0214691162109f,(float16_t)1.0000000000000f, +(float16_t)0.0199432373047f,(float16_t)1.0000000000000f, +(float16_t)0.0184020996094f,(float16_t)1.0000000000000f, +(float16_t)0.0168762207031f,(float16_t)1.0000000000000f, +(float16_t)0.0153427124023f,(float16_t)1.0000000000000f, +(float16_t)0.0138015747070f,(float16_t)1.0000000000000f, +(float16_t)0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)0.0107345581055f,(float16_t)1.0000000000000f, +(float16_t)0.0092010498047f,(float16_t)1.0000000000000f, +(float16_t)0.0076713562012f,(float16_t)1.0000000000000f, +(float16_t)0.0061340332031f,(float16_t)1.0000000000000f, +(float16_t)0.0046005249023f,(float16_t)1.0000000000000f, +(float16_t)0.0030670166016f,(float16_t)1.0000000000000f, +(float16_t)0.0015335083008f,(float16_t)1.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0061340332031f, +(float16_t)1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)1.0000000000000f,(float16_t)0.0184020996094f, +(float16_t)0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)0.9995117187500f,(float16_t)0.0306701660156f, +(float16_t)0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)0.9990234375000f,(float16_t)0.0429382324219f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9985351562500f,(float16_t)0.0552062988281f, +(float16_t)0.9980468750000f,(float16_t)0.0613098144531f, +(float16_t)0.9975585937500f,(float16_t)0.0674438476562f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9965820312500f,(float16_t)0.0797119140625f, +(float16_t)0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)0.9956054687500f,(float16_t)0.0919189453125f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9946289062500f,(float16_t)0.1041259765625f, +(float16_t)0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)0.9931640625000f,(float16_t)0.1163330078125f, +(float16_t)0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)0.9916992187500f,(float16_t)0.1285400390625f, +(float16_t)0.9907226562500f,(float16_t)0.1345214843750f, +(float16_t)0.9902343750000f,(float16_t)0.1406250000000f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9882812500000f,(float16_t)0.1528320312500f, +(float16_t)0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)0.9863281250000f,(float16_t)0.1649169921875f, +(float16_t)0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)0.9843750000000f,(float16_t)0.1770019531250f, +(float16_t)0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)0.9819335937500f,(float16_t)0.1890869140625f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9794921875000f,(float16_t)0.2010498046875f, +(float16_t)0.9785156250000f,(float16_t)0.2071533203125f, +(float16_t)0.9770507812500f,(float16_t)0.2131347656250f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9741210937500f,(float16_t)0.2250976562500f, +(float16_t)0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)0.9716796875000f,(float16_t)0.2370605468750f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9687500000000f,(float16_t)0.2489013671875f, +(float16_t)0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)0.9653320312500f,(float16_t)0.2607421875000f, +(float16_t)0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)0.9619140625000f,(float16_t)0.2727050781250f, +(float16_t)0.9604492187500f,(float16_t)0.2785644531250f, +(float16_t)0.9584960937500f,(float16_t)0.2844238281250f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9550781250000f,(float16_t)0.2961425781250f, +(float16_t)0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)0.9516601562500f,(float16_t)0.3078613281250f, +(float16_t)0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)0.9477539062500f,(float16_t)0.3195800781250f, +(float16_t)0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)0.9433593750000f,(float16_t)0.3310546875000f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9394531250000f,(float16_t)0.3427734375000f, +(float16_t)0.9375000000000f,(float16_t)0.3483886718750f, +(float16_t)0.9350585937500f,(float16_t)0.3542480468750f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9306640625000f,(float16_t)0.3657226562500f, +(float16_t)0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)0.9262695312500f,(float16_t)0.3769531250000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9213867187500f,(float16_t)0.3884277343750f, +(float16_t)0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)0.9165039062500f,(float16_t)0.3996582031250f, +(float16_t)0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)0.9116210937500f,(float16_t)0.4108886718750f, +(float16_t)0.9091796875000f,(float16_t)0.4165039062500f, +(float16_t)0.9067382812500f,(float16_t)0.4221191406250f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.9013671875000f,(float16_t)0.4331054687500f, +(float16_t)0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)0.8959960937500f,(float16_t)0.4440917968750f, +(float16_t)0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)0.8906250000000f,(float16_t)0.4550781250000f, +(float16_t)0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)0.8847656250000f,(float16_t)0.4660644531250f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8789062500000f,(float16_t)0.4768066406250f, +(float16_t)0.8759765625000f,(float16_t)0.4821777343750f, +(float16_t)0.8730468750000f,(float16_t)0.4875488281250f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8671875000000f,(float16_t)0.4982910156250f, +(float16_t)0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)0.8608398437500f,(float16_t)0.5087890625000f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8544921875000f,(float16_t)0.5195312500000f, +(float16_t)0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)0.8481445312500f,(float16_t)0.5297851562500f, +(float16_t)0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)0.8417968750000f,(float16_t)0.5400390625000f, +(float16_t)0.8383789062500f,(float16_t)0.5454101562500f, +(float16_t)0.8349609375000f,(float16_t)0.5502929687500f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8281250000000f,(float16_t)0.5605468750000f, +(float16_t)0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)0.8212890625000f,(float16_t)0.5708007812500f, +(float16_t)0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)0.8139648437500f,(float16_t)0.5810546875000f, +(float16_t)0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)0.8066406250000f,(float16_t)0.5908203125000f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.7993164062500f,(float16_t)0.6005859375000f, +(float16_t)0.7958984375000f,(float16_t)0.6054687500000f, +(float16_t)0.7919921875000f,(float16_t)0.6103515625000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7846679687500f,(float16_t)0.6201171875000f, +(float16_t)0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)0.7768554687500f,(float16_t)0.6293945312500f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7690429687500f,(float16_t)0.6391601562500f, +(float16_t)0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)0.7612304687500f,(float16_t)0.6484375000000f, +(float16_t)0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)0.7534179687500f,(float16_t)0.6577148437500f, +(float16_t)0.7490234375000f,(float16_t)0.6625976562500f, +(float16_t)0.7451171875000f,(float16_t)0.6669921875000f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7368164062500f,(float16_t)0.6762695312500f, +(float16_t)0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)0.7285156250000f,(float16_t)0.6850585937500f, +(float16_t)0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)0.7202148437500f,(float16_t)0.6938476562500f, +(float16_t)0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)0.7114257812500f,(float16_t)0.7026367187500f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.7026367187500f,(float16_t)0.7114257812500f, +(float16_t)0.6982421875000f,(float16_t)0.7158203125000f, +(float16_t)0.6938476562500f,(float16_t)0.7202148437500f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6850585937500f,(float16_t)0.7285156250000f, +(float16_t)0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)0.6762695312500f,(float16_t)0.7368164062500f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6669921875000f,(float16_t)0.7451171875000f, +(float16_t)0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)0.6577148437500f,(float16_t)0.7534179687500f, +(float16_t)0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)0.6484375000000f,(float16_t)0.7612304687500f, +(float16_t)0.6440429687500f,(float16_t)0.7651367187500f, +(float16_t)0.6391601562500f,(float16_t)0.7690429687500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6293945312500f,(float16_t)0.7768554687500f, +(float16_t)0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)0.6201171875000f,(float16_t)0.7846679687500f, +(float16_t)0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)0.6103515625000f,(float16_t)0.7919921875000f, +(float16_t)0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)0.6005859375000f,(float16_t)0.7993164062500f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5908203125000f,(float16_t)0.8066406250000f, +(float16_t)0.5859375000000f,(float16_t)0.8105468750000f, +(float16_t)0.5810546875000f,(float16_t)0.8139648437500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5708007812500f,(float16_t)0.8212890625000f, +(float16_t)0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)0.5605468750000f,(float16_t)0.8281250000000f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5502929687500f,(float16_t)0.8349609375000f, +(float16_t)0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)0.5400390625000f,(float16_t)0.8417968750000f, +(float16_t)0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)0.5297851562500f,(float16_t)0.8481445312500f, +(float16_t)0.5244140625000f,(float16_t)0.8515625000000f, +(float16_t)0.5195312500000f,(float16_t)0.8544921875000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.5087890625000f,(float16_t)0.8608398437500f, +(float16_t)0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)0.4982910156250f,(float16_t)0.8671875000000f, +(float16_t)0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)0.4875488281250f,(float16_t)0.8730468750000f, +(float16_t)0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)0.4768066406250f,(float16_t)0.8789062500000f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4660644531250f,(float16_t)0.8847656250000f, +(float16_t)0.4604492187500f,(float16_t)0.8876953125000f, +(float16_t)0.4550781250000f,(float16_t)0.8906250000000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4440917968750f,(float16_t)0.8959960937500f, +(float16_t)0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)0.4331054687500f,(float16_t)0.9013671875000f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.4221191406250f,(float16_t)0.9067382812500f, +(float16_t)0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)0.4108886718750f,(float16_t)0.9116210937500f, +(float16_t)0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)0.3996582031250f,(float16_t)0.9165039062500f, +(float16_t)0.3940429687500f,(float16_t)0.9189453125000f, +(float16_t)0.3884277343750f,(float16_t)0.9213867187500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3769531250000f,(float16_t)0.9262695312500f, +(float16_t)0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)0.3657226562500f,(float16_t)0.9306640625000f, +(float16_t)0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)0.3542480468750f,(float16_t)0.9350585937500f, +(float16_t)0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)0.3427734375000f,(float16_t)0.9394531250000f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.3310546875000f,(float16_t)0.9433593750000f, +(float16_t)0.3251953125000f,(float16_t)0.9458007812500f, +(float16_t)0.3195800781250f,(float16_t)0.9477539062500f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.3078613281250f,(float16_t)0.9516601562500f, +(float16_t)0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)0.2961425781250f,(float16_t)0.9550781250000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2844238281250f,(float16_t)0.9584960937500f, +(float16_t)0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)0.2727050781250f,(float16_t)0.9619140625000f, +(float16_t)0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)0.2607421875000f,(float16_t)0.9653320312500f, +(float16_t)0.2548828125000f,(float16_t)0.9667968750000f, +(float16_t)0.2489013671875f,(float16_t)0.9687500000000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2370605468750f,(float16_t)0.9716796875000f, +(float16_t)0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)0.2250976562500f,(float16_t)0.9741210937500f, +(float16_t)0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)0.2131347656250f,(float16_t)0.9770507812500f, +(float16_t)0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)0.2010498046875f,(float16_t)0.9794921875000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1890869140625f,(float16_t)0.9819335937500f, +(float16_t)0.1829833984375f,(float16_t)0.9829101562500f, +(float16_t)0.1770019531250f,(float16_t)0.9843750000000f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1649169921875f,(float16_t)0.9863281250000f, +(float16_t)0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)0.1528320312500f,(float16_t)0.9882812500000f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.1406250000000f,(float16_t)0.9902343750000f, +(float16_t)0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)0.1285400390625f,(float16_t)0.9916992187500f, +(float16_t)0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)0.1163330078125f,(float16_t)0.9931640625000f, +(float16_t)0.1102294921875f,(float16_t)0.9941406250000f, +(float16_t)0.1041259765625f,(float16_t)0.9946289062500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0919189453125f,(float16_t)0.9956054687500f, +(float16_t)0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)0.0797119140625f,(float16_t)0.9965820312500f, +(float16_t)0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)0.0674438476562f,(float16_t)0.9975585937500f, +(float16_t)0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)0.0552062988281f,(float16_t)0.9985351562500f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0429382324219f,(float16_t)0.9990234375000f, +(float16_t)0.0368041992188f,(float16_t)0.9995117187500f, +(float16_t)0.0306701660156f,(float16_t)0.9995117187500f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)0.0184020996094f,(float16_t)1.0000000000000f, +(float16_t)0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)0.0061340332031f,(float16_t)1.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f,}; + +float16_t rearranged_twiddle_stride2_4096_f16[2728]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0030670166016f, +(float16_t)1.0000000000000f,(float16_t)0.0061340332031f, +(float16_t)1.0000000000000f,(float16_t)0.0092010498047f, +(float16_t)1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)1.0000000000000f,(float16_t)0.0153427124023f, +(float16_t)1.0000000000000f,(float16_t)0.0184020996094f, +(float16_t)1.0000000000000f,(float16_t)0.0214691162109f, +(float16_t)0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)0.9995117187500f,(float16_t)0.0276031494141f, +(float16_t)0.9995117187500f,(float16_t)0.0306701660156f, +(float16_t)0.9995117187500f,(float16_t)0.0337524414062f, +(float16_t)0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)0.9990234375000f,(float16_t)0.0398864746094f, +(float16_t)0.9990234375000f,(float16_t)0.0429382324219f, +(float16_t)0.9990234375000f,(float16_t)0.0459899902344f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9985351562500f,(float16_t)0.0521240234375f, +(float16_t)0.9985351562500f,(float16_t)0.0552062988281f, +(float16_t)0.9985351562500f,(float16_t)0.0582580566406f, +(float16_t)0.9980468750000f,(float16_t)0.0613098144531f, +(float16_t)0.9980468750000f,(float16_t)0.0643920898438f, +(float16_t)0.9975585937500f,(float16_t)0.0674438476562f, +(float16_t)0.9975585937500f,(float16_t)0.0704956054688f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9970703125000f,(float16_t)0.0765991210938f, +(float16_t)0.9965820312500f,(float16_t)0.0797119140625f, +(float16_t)0.9965820312500f,(float16_t)0.0827636718750f, +(float16_t)0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)0.9960937500000f,(float16_t)0.0888671875000f, +(float16_t)0.9956054687500f,(float16_t)0.0919189453125f, +(float16_t)0.9956054687500f,(float16_t)0.0949707031250f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9951171875000f,(float16_t)0.1010742187500f, +(float16_t)0.9946289062500f,(float16_t)0.1041259765625f, +(float16_t)0.9941406250000f,(float16_t)0.1071777343750f, +(float16_t)0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)0.9936523437500f,(float16_t)0.1132812500000f, +(float16_t)0.9931640625000f,(float16_t)0.1163330078125f, +(float16_t)0.9926757812500f,(float16_t)0.1193847656250f, +(float16_t)0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)0.9921875000000f,(float16_t)0.1254882812500f, +(float16_t)0.9916992187500f,(float16_t)0.1285400390625f, +(float16_t)0.9912109375000f,(float16_t)0.1315917968750f, +(float16_t)0.9907226562500f,(float16_t)0.1345214843750f, +(float16_t)0.9907226562500f,(float16_t)0.1375732421875f, +(float16_t)0.9902343750000f,(float16_t)0.1406250000000f, +(float16_t)0.9897460937500f,(float16_t)0.1436767578125f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9887695312500f,(float16_t)0.1497802734375f, +(float16_t)0.9882812500000f,(float16_t)0.1528320312500f, +(float16_t)0.9877929687500f,(float16_t)0.1558837890625f, +(float16_t)0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)0.9868164062500f,(float16_t)0.1618652343750f, +(float16_t)0.9863281250000f,(float16_t)0.1649169921875f, +(float16_t)0.9858398437500f,(float16_t)0.1679687500000f, +(float16_t)0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)0.9848632812500f,(float16_t)0.1739501953125f, +(float16_t)0.9843750000000f,(float16_t)0.1770019531250f, +(float16_t)0.9838867187500f,(float16_t)0.1800537109375f, +(float16_t)0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)0.9824218750000f,(float16_t)0.1860351562500f, +(float16_t)0.9819335937500f,(float16_t)0.1890869140625f, +(float16_t)0.9814453125000f,(float16_t)0.1921386718750f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9799804687500f,(float16_t)0.1981201171875f, +(float16_t)0.9794921875000f,(float16_t)0.2010498046875f, +(float16_t)0.9790039062500f,(float16_t)0.2041015625000f, +(float16_t)0.9785156250000f,(float16_t)0.2071533203125f, +(float16_t)0.9775390625000f,(float16_t)0.2100830078125f, +(float16_t)0.9770507812500f,(float16_t)0.2131347656250f, +(float16_t)0.9765625000000f,(float16_t)0.2160644531250f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9750976562500f,(float16_t)0.2220458984375f, +(float16_t)0.9741210937500f,(float16_t)0.2250976562500f, +(float16_t)0.9736328125000f,(float16_t)0.2280273437500f, +(float16_t)0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)0.9721679687500f,(float16_t)0.2340087890625f, +(float16_t)0.9716796875000f,(float16_t)0.2370605468750f, +(float16_t)0.9707031250000f,(float16_t)0.2399902343750f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9692382812500f,(float16_t)0.2459716796875f, +(float16_t)0.9687500000000f,(float16_t)0.2489013671875f, +(float16_t)0.9677734375000f,(float16_t)0.2519531250000f, +(float16_t)0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)0.9663085937500f,(float16_t)0.2578125000000f, +(float16_t)0.9653320312500f,(float16_t)0.2607421875000f, +(float16_t)0.9643554687500f,(float16_t)0.2636718750000f, +(float16_t)0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)0.9628906250000f,(float16_t)0.2697753906250f, +(float16_t)0.9619140625000f,(float16_t)0.2727050781250f, +(float16_t)0.9614257812500f,(float16_t)0.2756347656250f, +(float16_t)0.9604492187500f,(float16_t)0.2785644531250f, +(float16_t)0.9594726562500f,(float16_t)0.2814941406250f, +(float16_t)0.9584960937500f,(float16_t)0.2844238281250f, +(float16_t)0.9580078125000f,(float16_t)0.2873535156250f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9560546875000f,(float16_t)0.2932128906250f, +(float16_t)0.9550781250000f,(float16_t)0.2961425781250f, +(float16_t)0.9541015625000f,(float16_t)0.2990722656250f, +(float16_t)0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)0.9521484375000f,(float16_t)0.3049316406250f, +(float16_t)0.9516601562500f,(float16_t)0.3078613281250f, +(float16_t)0.9506835937500f,(float16_t)0.3107910156250f, +(float16_t)0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)0.9487304687500f,(float16_t)0.3166503906250f, +(float16_t)0.9477539062500f,(float16_t)0.3195800781250f, +(float16_t)0.9467773437500f,(float16_t)0.3225097656250f, +(float16_t)0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)0.9448242187500f,(float16_t)0.3281250000000f, +(float16_t)0.9433593750000f,(float16_t)0.3310546875000f, +(float16_t)0.9423828125000f,(float16_t)0.3339843750000f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9404296875000f,(float16_t)0.3398437500000f, +(float16_t)0.9394531250000f,(float16_t)0.3427734375000f, +(float16_t)0.9384765625000f,(float16_t)0.3454589843750f, +(float16_t)0.9375000000000f,(float16_t)0.3483886718750f, +(float16_t)0.9360351562500f,(float16_t)0.3513183593750f, +(float16_t)0.9350585937500f,(float16_t)0.3542480468750f, +(float16_t)0.9340820312500f,(float16_t)0.3569335937500f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9316406250000f,(float16_t)0.3627929687500f, +(float16_t)0.9306640625000f,(float16_t)0.3657226562500f, +(float16_t)0.9296875000000f,(float16_t)0.3684082031250f, +(float16_t)0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)0.9272460937500f,(float16_t)0.3742675781250f, +(float16_t)0.9262695312500f,(float16_t)0.3769531250000f, +(float16_t)0.9252929687500f,(float16_t)0.3798828125000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9228515625000f,(float16_t)0.3854980468750f, +(float16_t)0.9213867187500f,(float16_t)0.3884277343750f, +(float16_t)0.9204101562500f,(float16_t)0.3911132812500f, +(float16_t)0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)0.9179687500000f,(float16_t)0.3967285156250f, +(float16_t)0.9165039062500f,(float16_t)0.3996582031250f, +(float16_t)0.9155273437500f,(float16_t)0.4023437500000f, +(float16_t)0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)0.9130859375000f,(float16_t)0.4079589843750f, +(float16_t)0.9116210937500f,(float16_t)0.4108886718750f, +(float16_t)0.9106445312500f,(float16_t)0.4135742187500f, +(float16_t)0.9091796875000f,(float16_t)0.4165039062500f, +(float16_t)0.9077148437500f,(float16_t)0.4191894531250f, +(float16_t)0.9067382812500f,(float16_t)0.4221191406250f, +(float16_t)0.9052734375000f,(float16_t)0.4248046875000f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.9028320312500f,(float16_t)0.4304199218750f, +(float16_t)0.9013671875000f,(float16_t)0.4331054687500f, +(float16_t)0.8999023437500f,(float16_t)0.4357910156250f, +(float16_t)0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)0.8974609375000f,(float16_t)0.4414062500000f, +(float16_t)0.8959960937500f,(float16_t)0.4440917968750f, +(float16_t)0.8945312500000f,(float16_t)0.4467773437500f, +(float16_t)0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)0.8916015625000f,(float16_t)0.4523925781250f, +(float16_t)0.8906250000000f,(float16_t)0.4550781250000f, +(float16_t)0.8891601562500f,(float16_t)0.4577636718750f, +(float16_t)0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)0.8862304687500f,(float16_t)0.4633789062500f, +(float16_t)0.8847656250000f,(float16_t)0.4660644531250f, +(float16_t)0.8833007812500f,(float16_t)0.4687500000000f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8803710937500f,(float16_t)0.4741210937500f, +(float16_t)0.8789062500000f,(float16_t)0.4768066406250f, +(float16_t)0.8774414062500f,(float16_t)0.4794921875000f, +(float16_t)0.8759765625000f,(float16_t)0.4821777343750f, +(float16_t)0.8745117187500f,(float16_t)0.4848632812500f, +(float16_t)0.8730468750000f,(float16_t)0.4875488281250f, +(float16_t)0.8715820312500f,(float16_t)0.4902343750000f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8686523437500f,(float16_t)0.4956054687500f, +(float16_t)0.8671875000000f,(float16_t)0.4982910156250f, +(float16_t)0.8657226562500f,(float16_t)0.5009765625000f, +(float16_t)0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)0.8623046875000f,(float16_t)0.5063476562500f, +(float16_t)0.8608398437500f,(float16_t)0.5087890625000f, +(float16_t)0.8593750000000f,(float16_t)0.5112304687500f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8559570312500f,(float16_t)0.5166015625000f, +(float16_t)0.8544921875000f,(float16_t)0.5195312500000f, +(float16_t)0.8530273437500f,(float16_t)0.5219726562500f, +(float16_t)0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)0.8496093750000f,(float16_t)0.5273437500000f, +(float16_t)0.8481445312500f,(float16_t)0.5297851562500f, +(float16_t)0.8466796875000f,(float16_t)0.5322265625000f, +(float16_t)0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)0.8432617187500f,(float16_t)0.5375976562500f, +(float16_t)0.8417968750000f,(float16_t)0.5400390625000f, +(float16_t)0.8398437500000f,(float16_t)0.5429687500000f, +(float16_t)0.8383789062500f,(float16_t)0.5454101562500f, +(float16_t)0.8364257812500f,(float16_t)0.5478515625000f, +(float16_t)0.8349609375000f,(float16_t)0.5502929687500f, +(float16_t)0.8330078125000f,(float16_t)0.5532226562500f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8295898437500f,(float16_t)0.5581054687500f, +(float16_t)0.8281250000000f,(float16_t)0.5605468750000f, +(float16_t)0.8261718750000f,(float16_t)0.5629882812500f, +(float16_t)0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)0.8227539062500f,(float16_t)0.5683593750000f, +(float16_t)0.8212890625000f,(float16_t)0.5708007812500f, +(float16_t)0.8193359375000f,(float16_t)0.5732421875000f, +(float16_t)0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)0.8159179687500f,(float16_t)0.5781250000000f, +(float16_t)0.8139648437500f,(float16_t)0.5810546875000f, +(float16_t)0.8120117187500f,(float16_t)0.5834960937500f, +(float16_t)0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)0.8085937500000f,(float16_t)0.5883789062500f, +(float16_t)0.8066406250000f,(float16_t)0.5908203125000f, +(float16_t)0.8051757812500f,(float16_t)0.5932617187500f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.8012695312500f,(float16_t)0.5981445312500f, +(float16_t)0.7993164062500f,(float16_t)0.6005859375000f, +(float16_t)0.7978515625000f,(float16_t)0.6030273437500f, +(float16_t)0.7958984375000f,(float16_t)0.6054687500000f, +(float16_t)0.7939453125000f,(float16_t)0.6079101562500f, +(float16_t)0.7919921875000f,(float16_t)0.6103515625000f, +(float16_t)0.7900390625000f,(float16_t)0.6127929687500f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7866210937500f,(float16_t)0.6176757812500f, +(float16_t)0.7846679687500f,(float16_t)0.6201171875000f, +(float16_t)0.7827148437500f,(float16_t)0.6225585937500f, +(float16_t)0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)0.7788085937500f,(float16_t)0.6274414062500f, +(float16_t)0.7768554687500f,(float16_t)0.6293945312500f, +(float16_t)0.7749023437500f,(float16_t)0.6318359375000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7709960937500f,(float16_t)0.6367187500000f, +(float16_t)0.7690429687500f,(float16_t)0.6391601562500f, +(float16_t)0.7670898437500f,(float16_t)0.6416015625000f, +(float16_t)0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)0.7631835937500f,(float16_t)0.6459960937500f, +(float16_t)0.7612304687500f,(float16_t)0.6484375000000f, +(float16_t)0.7592773437500f,(float16_t)0.6508789062500f, +(float16_t)0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)0.7553710937500f,(float16_t)0.6552734375000f, +(float16_t)0.7534179687500f,(float16_t)0.6577148437500f, +(float16_t)0.7509765625000f,(float16_t)0.6601562500000f, +(float16_t)0.7490234375000f,(float16_t)0.6625976562500f, +(float16_t)0.7470703125000f,(float16_t)0.6645507812500f, +(float16_t)0.7451171875000f,(float16_t)0.6669921875000f, +(float16_t)0.7431640625000f,(float16_t)0.6694335937500f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7387695312500f,(float16_t)0.6738281250000f, +(float16_t)0.7368164062500f,(float16_t)0.6762695312500f, +(float16_t)0.7348632812500f,(float16_t)0.6782226562500f, +(float16_t)0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)0.7304687500000f,(float16_t)0.6826171875000f, +(float16_t)0.7285156250000f,(float16_t)0.6850585937500f, +(float16_t)0.7265625000000f,(float16_t)0.6875000000000f, +(float16_t)0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)0.7221679687500f,(float16_t)0.6918945312500f, +(float16_t)0.7202148437500f,(float16_t)0.6938476562500f, +(float16_t)0.7177734375000f,(float16_t)0.6962890625000f, +(float16_t)0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)0.7133789062500f,(float16_t)0.7006835937500f, +(float16_t)0.7114257812500f,(float16_t)0.7026367187500f, +(float16_t)0.7094726562500f,(float16_t)0.7050781250000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.7050781250000f,(float16_t)0.7094726562500f, +(float16_t)0.7026367187500f,(float16_t)0.7114257812500f, +(float16_t)0.7006835937500f,(float16_t)0.7133789062500f, +(float16_t)0.6982421875000f,(float16_t)0.7158203125000f, +(float16_t)0.6962890625000f,(float16_t)0.7177734375000f, +(float16_t)0.6938476562500f,(float16_t)0.7202148437500f, +(float16_t)0.6918945312500f,(float16_t)0.7221679687500f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6875000000000f,(float16_t)0.7265625000000f, +(float16_t)0.6850585937500f,(float16_t)0.7285156250000f, +(float16_t)0.6826171875000f,(float16_t)0.7304687500000f, +(float16_t)0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)0.6782226562500f,(float16_t)0.7348632812500f, +(float16_t)0.6762695312500f,(float16_t)0.7368164062500f, +(float16_t)0.6738281250000f,(float16_t)0.7387695312500f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6694335937500f,(float16_t)0.7431640625000f, +(float16_t)0.6669921875000f,(float16_t)0.7451171875000f, +(float16_t)0.6645507812500f,(float16_t)0.7470703125000f, +(float16_t)0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)0.6601562500000f,(float16_t)0.7509765625000f, +(float16_t)0.6577148437500f,(float16_t)0.7534179687500f, +(float16_t)0.6552734375000f,(float16_t)0.7553710937500f, +(float16_t)0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)0.6508789062500f,(float16_t)0.7592773437500f, +(float16_t)0.6484375000000f,(float16_t)0.7612304687500f, +(float16_t)0.6459960937500f,(float16_t)0.7631835937500f, +(float16_t)0.6440429687500f,(float16_t)0.7651367187500f, +(float16_t)0.6416015625000f,(float16_t)0.7670898437500f, +(float16_t)0.6391601562500f,(float16_t)0.7690429687500f, +(float16_t)0.6367187500000f,(float16_t)0.7709960937500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6318359375000f,(float16_t)0.7749023437500f, +(float16_t)0.6293945312500f,(float16_t)0.7768554687500f, +(float16_t)0.6274414062500f,(float16_t)0.7788085937500f, +(float16_t)0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)0.6225585937500f,(float16_t)0.7827148437500f, +(float16_t)0.6201171875000f,(float16_t)0.7846679687500f, +(float16_t)0.6176757812500f,(float16_t)0.7866210937500f, +(float16_t)0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)0.6127929687500f,(float16_t)0.7900390625000f, +(float16_t)0.6103515625000f,(float16_t)0.7919921875000f, +(float16_t)0.6079101562500f,(float16_t)0.7939453125000f, +(float16_t)0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)0.6030273437500f,(float16_t)0.7978515625000f, +(float16_t)0.6005859375000f,(float16_t)0.7993164062500f, +(float16_t)0.5981445312500f,(float16_t)0.8012695312500f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5932617187500f,(float16_t)0.8051757812500f, +(float16_t)0.5908203125000f,(float16_t)0.8066406250000f, +(float16_t)0.5883789062500f,(float16_t)0.8085937500000f, +(float16_t)0.5859375000000f,(float16_t)0.8105468750000f, +(float16_t)0.5834960937500f,(float16_t)0.8120117187500f, +(float16_t)0.5810546875000f,(float16_t)0.8139648437500f, +(float16_t)0.5781250000000f,(float16_t)0.8159179687500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5732421875000f,(float16_t)0.8193359375000f, +(float16_t)0.5708007812500f,(float16_t)0.8212890625000f, +(float16_t)0.5683593750000f,(float16_t)0.8227539062500f, +(float16_t)0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)0.5629882812500f,(float16_t)0.8261718750000f, +(float16_t)0.5605468750000f,(float16_t)0.8281250000000f, +(float16_t)0.5581054687500f,(float16_t)0.8295898437500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5532226562500f,(float16_t)0.8330078125000f, +(float16_t)0.5502929687500f,(float16_t)0.8349609375000f, +(float16_t)0.5478515625000f,(float16_t)0.8364257812500f, +(float16_t)0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)0.5429687500000f,(float16_t)0.8398437500000f, +(float16_t)0.5400390625000f,(float16_t)0.8417968750000f, +(float16_t)0.5375976562500f,(float16_t)0.8432617187500f, +(float16_t)0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)0.5322265625000f,(float16_t)0.8466796875000f, +(float16_t)0.5297851562500f,(float16_t)0.8481445312500f, +(float16_t)0.5273437500000f,(float16_t)0.8496093750000f, +(float16_t)0.5244140625000f,(float16_t)0.8515625000000f, +(float16_t)0.5219726562500f,(float16_t)0.8530273437500f, +(float16_t)0.5195312500000f,(float16_t)0.8544921875000f, +(float16_t)0.5166015625000f,(float16_t)0.8559570312500f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.5112304687500f,(float16_t)0.8593750000000f, +(float16_t)0.5087890625000f,(float16_t)0.8608398437500f, +(float16_t)0.5063476562500f,(float16_t)0.8623046875000f, +(float16_t)0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)0.5009765625000f,(float16_t)0.8657226562500f, +(float16_t)0.4982910156250f,(float16_t)0.8671875000000f, +(float16_t)0.4956054687500f,(float16_t)0.8686523437500f, +(float16_t)0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)0.4902343750000f,(float16_t)0.8715820312500f, +(float16_t)0.4875488281250f,(float16_t)0.8730468750000f, +(float16_t)0.4848632812500f,(float16_t)0.8745117187500f, +(float16_t)0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)0.4794921875000f,(float16_t)0.8774414062500f, +(float16_t)0.4768066406250f,(float16_t)0.8789062500000f, +(float16_t)0.4741210937500f,(float16_t)0.8803710937500f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4687500000000f,(float16_t)0.8833007812500f, +(float16_t)0.4660644531250f,(float16_t)0.8847656250000f, +(float16_t)0.4633789062500f,(float16_t)0.8862304687500f, +(float16_t)0.4604492187500f,(float16_t)0.8876953125000f, +(float16_t)0.4577636718750f,(float16_t)0.8891601562500f, +(float16_t)0.4550781250000f,(float16_t)0.8906250000000f, +(float16_t)0.4523925781250f,(float16_t)0.8916015625000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4467773437500f,(float16_t)0.8945312500000f, +(float16_t)0.4440917968750f,(float16_t)0.8959960937500f, +(float16_t)0.4414062500000f,(float16_t)0.8974609375000f, +(float16_t)0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)0.4357910156250f,(float16_t)0.8999023437500f, +(float16_t)0.4331054687500f,(float16_t)0.9013671875000f, +(float16_t)0.4304199218750f,(float16_t)0.9028320312500f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.4248046875000f,(float16_t)0.9052734375000f, +(float16_t)0.4221191406250f,(float16_t)0.9067382812500f, +(float16_t)0.4191894531250f,(float16_t)0.9077148437500f, +(float16_t)0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)0.4135742187500f,(float16_t)0.9106445312500f, +(float16_t)0.4108886718750f,(float16_t)0.9116210937500f, +(float16_t)0.4079589843750f,(float16_t)0.9130859375000f, +(float16_t)0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)0.4023437500000f,(float16_t)0.9155273437500f, +(float16_t)0.3996582031250f,(float16_t)0.9165039062500f, +(float16_t)0.3967285156250f,(float16_t)0.9179687500000f, +(float16_t)0.3940429687500f,(float16_t)0.9189453125000f, +(float16_t)0.3911132812500f,(float16_t)0.9204101562500f, +(float16_t)0.3884277343750f,(float16_t)0.9213867187500f, +(float16_t)0.3854980468750f,(float16_t)0.9228515625000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3798828125000f,(float16_t)0.9252929687500f, +(float16_t)0.3769531250000f,(float16_t)0.9262695312500f, +(float16_t)0.3742675781250f,(float16_t)0.9272460937500f, +(float16_t)0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)0.3684082031250f,(float16_t)0.9296875000000f, +(float16_t)0.3657226562500f,(float16_t)0.9306640625000f, +(float16_t)0.3627929687500f,(float16_t)0.9316406250000f, +(float16_t)0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)0.3569335937500f,(float16_t)0.9340820312500f, +(float16_t)0.3542480468750f,(float16_t)0.9350585937500f, +(float16_t)0.3513183593750f,(float16_t)0.9360351562500f, +(float16_t)0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)0.3454589843750f,(float16_t)0.9384765625000f, +(float16_t)0.3427734375000f,(float16_t)0.9394531250000f, +(float16_t)0.3398437500000f,(float16_t)0.9404296875000f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.3339843750000f,(float16_t)0.9423828125000f, +(float16_t)0.3310546875000f,(float16_t)0.9433593750000f, +(float16_t)0.3281250000000f,(float16_t)0.9448242187500f, +(float16_t)0.3251953125000f,(float16_t)0.9458007812500f, +(float16_t)0.3225097656250f,(float16_t)0.9467773437500f, +(float16_t)0.3195800781250f,(float16_t)0.9477539062500f, +(float16_t)0.3166503906250f,(float16_t)0.9487304687500f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.3107910156250f,(float16_t)0.9506835937500f, +(float16_t)0.3078613281250f,(float16_t)0.9516601562500f, +(float16_t)0.3049316406250f,(float16_t)0.9521484375000f, +(float16_t)0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)0.2990722656250f,(float16_t)0.9541015625000f, +(float16_t)0.2961425781250f,(float16_t)0.9550781250000f, +(float16_t)0.2932128906250f,(float16_t)0.9560546875000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2873535156250f,(float16_t)0.9580078125000f, +(float16_t)0.2844238281250f,(float16_t)0.9584960937500f, +(float16_t)0.2814941406250f,(float16_t)0.9594726562500f, +(float16_t)0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)0.2756347656250f,(float16_t)0.9614257812500f, +(float16_t)0.2727050781250f,(float16_t)0.9619140625000f, +(float16_t)0.2697753906250f,(float16_t)0.9628906250000f, +(float16_t)0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)0.2636718750000f,(float16_t)0.9643554687500f, +(float16_t)0.2607421875000f,(float16_t)0.9653320312500f, +(float16_t)0.2578125000000f,(float16_t)0.9663085937500f, +(float16_t)0.2548828125000f,(float16_t)0.9667968750000f, +(float16_t)0.2519531250000f,(float16_t)0.9677734375000f, +(float16_t)0.2489013671875f,(float16_t)0.9687500000000f, +(float16_t)0.2459716796875f,(float16_t)0.9692382812500f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2399902343750f,(float16_t)0.9707031250000f, +(float16_t)0.2370605468750f,(float16_t)0.9716796875000f, +(float16_t)0.2340087890625f,(float16_t)0.9721679687500f, +(float16_t)0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)0.2280273437500f,(float16_t)0.9736328125000f, +(float16_t)0.2250976562500f,(float16_t)0.9741210937500f, +(float16_t)0.2220458984375f,(float16_t)0.9750976562500f, +(float16_t)0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)0.2160644531250f,(float16_t)0.9765625000000f, +(float16_t)0.2131347656250f,(float16_t)0.9770507812500f, +(float16_t)0.2100830078125f,(float16_t)0.9775390625000f, +(float16_t)0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)0.2041015625000f,(float16_t)0.9790039062500f, +(float16_t)0.2010498046875f,(float16_t)0.9794921875000f, +(float16_t)0.1981201171875f,(float16_t)0.9799804687500f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1921386718750f,(float16_t)0.9814453125000f, +(float16_t)0.1890869140625f,(float16_t)0.9819335937500f, +(float16_t)0.1860351562500f,(float16_t)0.9824218750000f, +(float16_t)0.1829833984375f,(float16_t)0.9829101562500f, +(float16_t)0.1800537109375f,(float16_t)0.9838867187500f, +(float16_t)0.1770019531250f,(float16_t)0.9843750000000f, +(float16_t)0.1739501953125f,(float16_t)0.9848632812500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1679687500000f,(float16_t)0.9858398437500f, +(float16_t)0.1649169921875f,(float16_t)0.9863281250000f, +(float16_t)0.1618652343750f,(float16_t)0.9868164062500f, +(float16_t)0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)0.1558837890625f,(float16_t)0.9877929687500f, +(float16_t)0.1528320312500f,(float16_t)0.9882812500000f, +(float16_t)0.1497802734375f,(float16_t)0.9887695312500f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.1436767578125f,(float16_t)0.9897460937500f, +(float16_t)0.1406250000000f,(float16_t)0.9902343750000f, +(float16_t)0.1375732421875f,(float16_t)0.9907226562500f, +(float16_t)0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)0.1315917968750f,(float16_t)0.9912109375000f, +(float16_t)0.1285400390625f,(float16_t)0.9916992187500f, +(float16_t)0.1254882812500f,(float16_t)0.9921875000000f, +(float16_t)0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)0.1193847656250f,(float16_t)0.9926757812500f, +(float16_t)0.1163330078125f,(float16_t)0.9931640625000f, +(float16_t)0.1132812500000f,(float16_t)0.9936523437500f, +(float16_t)0.1102294921875f,(float16_t)0.9941406250000f, +(float16_t)0.1071777343750f,(float16_t)0.9941406250000f, +(float16_t)0.1041259765625f,(float16_t)0.9946289062500f, +(float16_t)0.1010742187500f,(float16_t)0.9951171875000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0949707031250f,(float16_t)0.9956054687500f, +(float16_t)0.0919189453125f,(float16_t)0.9956054687500f, +(float16_t)0.0888671875000f,(float16_t)0.9960937500000f, +(float16_t)0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)0.0827636718750f,(float16_t)0.9965820312500f, +(float16_t)0.0797119140625f,(float16_t)0.9965820312500f, +(float16_t)0.0765991210938f,(float16_t)0.9970703125000f, +(float16_t)0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)0.0704956054688f,(float16_t)0.9975585937500f, +(float16_t)0.0674438476562f,(float16_t)0.9975585937500f, +(float16_t)0.0643920898438f,(float16_t)0.9980468750000f, +(float16_t)0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)0.0582580566406f,(float16_t)0.9985351562500f, +(float16_t)0.0552062988281f,(float16_t)0.9985351562500f, +(float16_t)0.0521240234375f,(float16_t)0.9985351562500f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0459899902344f,(float16_t)0.9990234375000f, +(float16_t)0.0429382324219f,(float16_t)0.9990234375000f, +(float16_t)0.0398864746094f,(float16_t)0.9990234375000f, +(float16_t)0.0368041992188f,(float16_t)0.9995117187500f, +(float16_t)0.0337524414062f,(float16_t)0.9995117187500f, +(float16_t)0.0306701660156f,(float16_t)0.9995117187500f, +(float16_t)0.0276031494141f,(float16_t)0.9995117187500f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)0.0214691162109f,(float16_t)1.0000000000000f, +(float16_t)0.0184020996094f,(float16_t)1.0000000000000f, +(float16_t)0.0153427124023f,(float16_t)1.0000000000000f, +(float16_t)0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)0.0092010498047f,(float16_t)1.0000000000000f, +(float16_t)0.0061340332031f,(float16_t)1.0000000000000f, +(float16_t)0.0030670166016f,(float16_t)1.0000000000000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.0030670166016f,(float16_t)1.0000000000000f, +(float16_t)-0.0061340332031f,(float16_t)1.0000000000000f, +(float16_t)-0.0092010498047f,(float16_t)1.0000000000000f, +(float16_t)-0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)-0.0153427124023f,(float16_t)1.0000000000000f, +(float16_t)-0.0184020996094f,(float16_t)1.0000000000000f, +(float16_t)-0.0214691162109f,(float16_t)1.0000000000000f, +(float16_t)-0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)-0.0276031494141f,(float16_t)0.9995117187500f, +(float16_t)-0.0306701660156f,(float16_t)0.9995117187500f, +(float16_t)-0.0337524414062f,(float16_t)0.9995117187500f, +(float16_t)-0.0368041992188f,(float16_t)0.9995117187500f, +(float16_t)-0.0398864746094f,(float16_t)0.9990234375000f, +(float16_t)-0.0429382324219f,(float16_t)0.9990234375000f, +(float16_t)-0.0459899902344f,(float16_t)0.9990234375000f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.0521240234375f,(float16_t)0.9985351562500f, +(float16_t)-0.0552062988281f,(float16_t)0.9985351562500f, +(float16_t)-0.0582580566406f,(float16_t)0.9985351562500f, +(float16_t)-0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)-0.0643920898438f,(float16_t)0.9980468750000f, +(float16_t)-0.0674438476562f,(float16_t)0.9975585937500f, +(float16_t)-0.0704956054688f,(float16_t)0.9975585937500f, +(float16_t)-0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)-0.0765991210938f,(float16_t)0.9970703125000f, +(float16_t)-0.0797119140625f,(float16_t)0.9965820312500f, +(float16_t)-0.0827636718750f,(float16_t)0.9965820312500f, +(float16_t)-0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)-0.0888671875000f,(float16_t)0.9960937500000f, +(float16_t)-0.0919189453125f,(float16_t)0.9956054687500f, +(float16_t)-0.0949707031250f,(float16_t)0.9956054687500f, +(float16_t)-0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1010742187500f,(float16_t)0.9951171875000f, +(float16_t)-0.1041259765625f,(float16_t)0.9946289062500f, +(float16_t)-0.1071777343750f,(float16_t)0.9941406250000f, +(float16_t)-0.1102294921875f,(float16_t)0.9941406250000f, +(float16_t)-0.1132812500000f,(float16_t)0.9936523437500f, +(float16_t)-0.1163330078125f,(float16_t)0.9931640625000f, +(float16_t)-0.1193847656250f,(float16_t)0.9926757812500f, +(float16_t)-0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)-0.1254882812500f,(float16_t)0.9921875000000f, +(float16_t)-0.1285400390625f,(float16_t)0.9916992187500f, +(float16_t)-0.1315917968750f,(float16_t)0.9912109375000f, +(float16_t)-0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)-0.1375732421875f,(float16_t)0.9907226562500f, +(float16_t)-0.1406250000000f,(float16_t)0.9902343750000f, +(float16_t)-0.1436767578125f,(float16_t)0.9897460937500f, +(float16_t)-0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)-0.1497802734375f,(float16_t)0.9887695312500f, +(float16_t)-0.1528320312500f,(float16_t)0.9882812500000f, +(float16_t)-0.1558837890625f,(float16_t)0.9877929687500f, +(float16_t)-0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)-0.1618652343750f,(float16_t)0.9868164062500f, +(float16_t)-0.1649169921875f,(float16_t)0.9863281250000f, +(float16_t)-0.1679687500000f,(float16_t)0.9858398437500f, +(float16_t)-0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)-0.1739501953125f,(float16_t)0.9848632812500f, +(float16_t)-0.1770019531250f,(float16_t)0.9843750000000f, +(float16_t)-0.1800537109375f,(float16_t)0.9838867187500f, +(float16_t)-0.1829833984375f,(float16_t)0.9829101562500f, +(float16_t)-0.1860351562500f,(float16_t)0.9824218750000f, +(float16_t)-0.1890869140625f,(float16_t)0.9819335937500f, +(float16_t)-0.1921386718750f,(float16_t)0.9814453125000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.1981201171875f,(float16_t)0.9799804687500f, +(float16_t)-0.2010498046875f,(float16_t)0.9794921875000f, +(float16_t)-0.2041015625000f,(float16_t)0.9790039062500f, +(float16_t)-0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)-0.2100830078125f,(float16_t)0.9775390625000f, +(float16_t)-0.2131347656250f,(float16_t)0.9770507812500f, +(float16_t)-0.2160644531250f,(float16_t)0.9765625000000f, +(float16_t)-0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)-0.2220458984375f,(float16_t)0.9750976562500f, +(float16_t)-0.2250976562500f,(float16_t)0.9741210937500f, +(float16_t)-0.2280273437500f,(float16_t)0.9736328125000f, +(float16_t)-0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)-0.2340087890625f,(float16_t)0.9721679687500f, +(float16_t)-0.2370605468750f,(float16_t)0.9716796875000f, +(float16_t)-0.2399902343750f,(float16_t)0.9707031250000f, +(float16_t)-0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)-0.2459716796875f,(float16_t)0.9692382812500f, +(float16_t)-0.2489013671875f,(float16_t)0.9687500000000f, +(float16_t)-0.2519531250000f,(float16_t)0.9677734375000f, +(float16_t)-0.2548828125000f,(float16_t)0.9667968750000f, +(float16_t)-0.2578125000000f,(float16_t)0.9663085937500f, +(float16_t)-0.2607421875000f,(float16_t)0.9653320312500f, +(float16_t)-0.2636718750000f,(float16_t)0.9643554687500f, +(float16_t)-0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)-0.2697753906250f,(float16_t)0.9628906250000f, +(float16_t)-0.2727050781250f,(float16_t)0.9619140625000f, +(float16_t)-0.2756347656250f,(float16_t)0.9614257812500f, +(float16_t)-0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)-0.2814941406250f,(float16_t)0.9594726562500f, +(float16_t)-0.2844238281250f,(float16_t)0.9584960937500f, +(float16_t)-0.2873535156250f,(float16_t)0.9580078125000f, +(float16_t)-0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)-0.2932128906250f,(float16_t)0.9560546875000f, +(float16_t)-0.2961425781250f,(float16_t)0.9550781250000f, +(float16_t)-0.2990722656250f,(float16_t)0.9541015625000f, +(float16_t)-0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)-0.3049316406250f,(float16_t)0.9521484375000f, +(float16_t)-0.3078613281250f,(float16_t)0.9516601562500f, +(float16_t)-0.3107910156250f,(float16_t)0.9506835937500f, +(float16_t)-0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)-0.3166503906250f,(float16_t)0.9487304687500f, +(float16_t)-0.3195800781250f,(float16_t)0.9477539062500f, +(float16_t)-0.3225097656250f,(float16_t)0.9467773437500f, +(float16_t)-0.3251953125000f,(float16_t)0.9458007812500f, +(float16_t)-0.3281250000000f,(float16_t)0.9448242187500f, +(float16_t)-0.3310546875000f,(float16_t)0.9433593750000f, +(float16_t)-0.3339843750000f,(float16_t)0.9423828125000f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.3398437500000f,(float16_t)0.9404296875000f, +(float16_t)-0.3427734375000f,(float16_t)0.9394531250000f, +(float16_t)-0.3454589843750f,(float16_t)0.9384765625000f, +(float16_t)-0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)-0.3513183593750f,(float16_t)0.9360351562500f, +(float16_t)-0.3542480468750f,(float16_t)0.9350585937500f, +(float16_t)-0.3569335937500f,(float16_t)0.9340820312500f, +(float16_t)-0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)-0.3627929687500f,(float16_t)0.9316406250000f, +(float16_t)-0.3657226562500f,(float16_t)0.9306640625000f, +(float16_t)-0.3684082031250f,(float16_t)0.9296875000000f, +(float16_t)-0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)-0.3742675781250f,(float16_t)0.9272460937500f, +(float16_t)-0.3769531250000f,(float16_t)0.9262695312500f, +(float16_t)-0.3798828125000f,(float16_t)0.9252929687500f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.3854980468750f,(float16_t)0.9228515625000f, +(float16_t)-0.3884277343750f,(float16_t)0.9213867187500f, +(float16_t)-0.3911132812500f,(float16_t)0.9204101562500f, +(float16_t)-0.3940429687500f,(float16_t)0.9189453125000f, +(float16_t)-0.3967285156250f,(float16_t)0.9179687500000f, +(float16_t)-0.3996582031250f,(float16_t)0.9165039062500f, +(float16_t)-0.4023437500000f,(float16_t)0.9155273437500f, +(float16_t)-0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)-0.4079589843750f,(float16_t)0.9130859375000f, +(float16_t)-0.4108886718750f,(float16_t)0.9116210937500f, +(float16_t)-0.4135742187500f,(float16_t)0.9106445312500f, +(float16_t)-0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)-0.4191894531250f,(float16_t)0.9077148437500f, +(float16_t)-0.4221191406250f,(float16_t)0.9067382812500f, +(float16_t)-0.4248046875000f,(float16_t)0.9052734375000f, +(float16_t)-0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)-0.4304199218750f,(float16_t)0.9028320312500f, +(float16_t)-0.4331054687500f,(float16_t)0.9013671875000f, +(float16_t)-0.4357910156250f,(float16_t)0.8999023437500f, +(float16_t)-0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)-0.4414062500000f,(float16_t)0.8974609375000f, +(float16_t)-0.4440917968750f,(float16_t)0.8959960937500f, +(float16_t)-0.4467773437500f,(float16_t)0.8945312500000f, +(float16_t)-0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)-0.4523925781250f,(float16_t)0.8916015625000f, +(float16_t)-0.4550781250000f,(float16_t)0.8906250000000f, +(float16_t)-0.4577636718750f,(float16_t)0.8891601562500f, +(float16_t)-0.4604492187500f,(float16_t)0.8876953125000f, +(float16_t)-0.4633789062500f,(float16_t)0.8862304687500f, +(float16_t)-0.4660644531250f,(float16_t)0.8847656250000f, +(float16_t)-0.4687500000000f,(float16_t)0.8833007812500f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.4741210937500f,(float16_t)0.8803710937500f, +(float16_t)-0.4768066406250f,(float16_t)0.8789062500000f, +(float16_t)-0.4794921875000f,(float16_t)0.8774414062500f, +(float16_t)-0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)-0.4848632812500f,(float16_t)0.8745117187500f, +(float16_t)-0.4875488281250f,(float16_t)0.8730468750000f, +(float16_t)-0.4902343750000f,(float16_t)0.8715820312500f, +(float16_t)-0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)-0.4956054687500f,(float16_t)0.8686523437500f, +(float16_t)-0.4982910156250f,(float16_t)0.8671875000000f, +(float16_t)-0.5009765625000f,(float16_t)0.8657226562500f, +(float16_t)-0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)-0.5063476562500f,(float16_t)0.8623046875000f, +(float16_t)-0.5087890625000f,(float16_t)0.8608398437500f, +(float16_t)-0.5112304687500f,(float16_t)0.8593750000000f, +(float16_t)-0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)-0.5166015625000f,(float16_t)0.8559570312500f, +(float16_t)-0.5195312500000f,(float16_t)0.8544921875000f, +(float16_t)-0.5219726562500f,(float16_t)0.8530273437500f, +(float16_t)-0.5244140625000f,(float16_t)0.8515625000000f, +(float16_t)-0.5273437500000f,(float16_t)0.8496093750000f, +(float16_t)-0.5297851562500f,(float16_t)0.8481445312500f, +(float16_t)-0.5322265625000f,(float16_t)0.8466796875000f, +(float16_t)-0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)-0.5375976562500f,(float16_t)0.8432617187500f, +(float16_t)-0.5400390625000f,(float16_t)0.8417968750000f, +(float16_t)-0.5429687500000f,(float16_t)0.8398437500000f, +(float16_t)-0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)-0.5478515625000f,(float16_t)0.8364257812500f, +(float16_t)-0.5502929687500f,(float16_t)0.8349609375000f, +(float16_t)-0.5532226562500f,(float16_t)0.8330078125000f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.5581054687500f,(float16_t)0.8295898437500f, +(float16_t)-0.5605468750000f,(float16_t)0.8281250000000f, +(float16_t)-0.5629882812500f,(float16_t)0.8261718750000f, +(float16_t)-0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)-0.5683593750000f,(float16_t)0.8227539062500f, +(float16_t)-0.5708007812500f,(float16_t)0.8212890625000f, +(float16_t)-0.5732421875000f,(float16_t)0.8193359375000f, +(float16_t)-0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)-0.5781250000000f,(float16_t)0.8159179687500f, +(float16_t)-0.5810546875000f,(float16_t)0.8139648437500f, +(float16_t)-0.5834960937500f,(float16_t)0.8120117187500f, +(float16_t)-0.5859375000000f,(float16_t)0.8105468750000f, +(float16_t)-0.5883789062500f,(float16_t)0.8085937500000f, +(float16_t)-0.5908203125000f,(float16_t)0.8066406250000f, +(float16_t)-0.5932617187500f,(float16_t)0.8051757812500f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.5981445312500f,(float16_t)0.8012695312500f, +(float16_t)-0.6005859375000f,(float16_t)0.7993164062500f, +(float16_t)-0.6030273437500f,(float16_t)0.7978515625000f, +(float16_t)-0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)-0.6079101562500f,(float16_t)0.7939453125000f, +(float16_t)-0.6103515625000f,(float16_t)0.7919921875000f, +(float16_t)-0.6127929687500f,(float16_t)0.7900390625000f, +(float16_t)-0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)-0.6176757812500f,(float16_t)0.7866210937500f, +(float16_t)-0.6201171875000f,(float16_t)0.7846679687500f, +(float16_t)-0.6225585937500f,(float16_t)0.7827148437500f, +(float16_t)-0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)-0.6274414062500f,(float16_t)0.7788085937500f, +(float16_t)-0.6293945312500f,(float16_t)0.7768554687500f, +(float16_t)-0.6318359375000f,(float16_t)0.7749023437500f, +(float16_t)-0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)-0.6367187500000f,(float16_t)0.7709960937500f, +(float16_t)-0.6391601562500f,(float16_t)0.7690429687500f, +(float16_t)-0.6416015625000f,(float16_t)0.7670898437500f, +(float16_t)-0.6440429687500f,(float16_t)0.7651367187500f, +(float16_t)-0.6459960937500f,(float16_t)0.7631835937500f, +(float16_t)-0.6484375000000f,(float16_t)0.7612304687500f, +(float16_t)-0.6508789062500f,(float16_t)0.7592773437500f, +(float16_t)-0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)-0.6552734375000f,(float16_t)0.7553710937500f, +(float16_t)-0.6577148437500f,(float16_t)0.7534179687500f, +(float16_t)-0.6601562500000f,(float16_t)0.7509765625000f, +(float16_t)-0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)-0.6645507812500f,(float16_t)0.7470703125000f, +(float16_t)-0.6669921875000f,(float16_t)0.7451171875000f, +(float16_t)-0.6694335937500f,(float16_t)0.7431640625000f, +(float16_t)-0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)-0.6738281250000f,(float16_t)0.7387695312500f, +(float16_t)-0.6762695312500f,(float16_t)0.7368164062500f, +(float16_t)-0.6782226562500f,(float16_t)0.7348632812500f, +(float16_t)-0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)-0.6826171875000f,(float16_t)0.7304687500000f, +(float16_t)-0.6850585937500f,(float16_t)0.7285156250000f, +(float16_t)-0.6875000000000f,(float16_t)0.7265625000000f, +(float16_t)-0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)-0.6918945312500f,(float16_t)0.7221679687500f, +(float16_t)-0.6938476562500f,(float16_t)0.7202148437500f, +(float16_t)-0.6962890625000f,(float16_t)0.7177734375000f, +(float16_t)-0.6982421875000f,(float16_t)0.7158203125000f, +(float16_t)-0.7006835937500f,(float16_t)0.7133789062500f, +(float16_t)-0.7026367187500f,(float16_t)0.7114257812500f, +(float16_t)-0.7050781250000f,(float16_t)0.7094726562500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7094726562500f,(float16_t)0.7050781250000f, +(float16_t)-0.7114257812500f,(float16_t)0.7026367187500f, +(float16_t)-0.7133789062500f,(float16_t)0.7006835937500f, +(float16_t)-0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)-0.7177734375000f,(float16_t)0.6962890625000f, +(float16_t)-0.7202148437500f,(float16_t)0.6938476562500f, +(float16_t)-0.7221679687500f,(float16_t)0.6918945312500f, +(float16_t)-0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)-0.7265625000000f,(float16_t)0.6875000000000f, +(float16_t)-0.7285156250000f,(float16_t)0.6850585937500f, +(float16_t)-0.7304687500000f,(float16_t)0.6826171875000f, +(float16_t)-0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)-0.7348632812500f,(float16_t)0.6782226562500f, +(float16_t)-0.7368164062500f,(float16_t)0.6762695312500f, +(float16_t)-0.7387695312500f,(float16_t)0.6738281250000f, +(float16_t)-0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)-0.7431640625000f,(float16_t)0.6694335937500f, +(float16_t)-0.7451171875000f,(float16_t)0.6669921875000f, +(float16_t)-0.7470703125000f,(float16_t)0.6645507812500f, +(float16_t)-0.7490234375000f,(float16_t)0.6625976562500f, +(float16_t)-0.7509765625000f,(float16_t)0.6601562500000f, +(float16_t)-0.7534179687500f,(float16_t)0.6577148437500f, +(float16_t)-0.7553710937500f,(float16_t)0.6552734375000f, +(float16_t)-0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)-0.7592773437500f,(float16_t)0.6508789062500f, +(float16_t)-0.7612304687500f,(float16_t)0.6484375000000f, +(float16_t)-0.7631835937500f,(float16_t)0.6459960937500f, +(float16_t)-0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)-0.7670898437500f,(float16_t)0.6416015625000f, +(float16_t)-0.7690429687500f,(float16_t)0.6391601562500f, +(float16_t)-0.7709960937500f,(float16_t)0.6367187500000f, +(float16_t)-0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)-0.7749023437500f,(float16_t)0.6318359375000f, +(float16_t)-0.7768554687500f,(float16_t)0.6293945312500f, +(float16_t)-0.7788085937500f,(float16_t)0.6274414062500f, +(float16_t)-0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)-0.7827148437500f,(float16_t)0.6225585937500f, +(float16_t)-0.7846679687500f,(float16_t)0.6201171875000f, +(float16_t)-0.7866210937500f,(float16_t)0.6176757812500f, +(float16_t)-0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)-0.7900390625000f,(float16_t)0.6127929687500f, +(float16_t)-0.7919921875000f,(float16_t)0.6103515625000f, +(float16_t)-0.7939453125000f,(float16_t)0.6079101562500f, +(float16_t)-0.7958984375000f,(float16_t)0.6054687500000f, +(float16_t)-0.7978515625000f,(float16_t)0.6030273437500f, +(float16_t)-0.7993164062500f,(float16_t)0.6005859375000f, +(float16_t)-0.8012695312500f,(float16_t)0.5981445312500f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8051757812500f,(float16_t)0.5932617187500f, +(float16_t)-0.8066406250000f,(float16_t)0.5908203125000f, +(float16_t)-0.8085937500000f,(float16_t)0.5883789062500f, +(float16_t)-0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)-0.8120117187500f,(float16_t)0.5834960937500f, +(float16_t)-0.8139648437500f,(float16_t)0.5810546875000f, +(float16_t)-0.8159179687500f,(float16_t)0.5781250000000f, +(float16_t)-0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)-0.8193359375000f,(float16_t)0.5732421875000f, +(float16_t)-0.8212890625000f,(float16_t)0.5708007812500f, +(float16_t)-0.8227539062500f,(float16_t)0.5683593750000f, +(float16_t)-0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)-0.8261718750000f,(float16_t)0.5629882812500f, +(float16_t)-0.8281250000000f,(float16_t)0.5605468750000f, +(float16_t)-0.8295898437500f,(float16_t)0.5581054687500f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.8330078125000f,(float16_t)0.5532226562500f, +(float16_t)-0.8349609375000f,(float16_t)0.5502929687500f, +(float16_t)-0.8364257812500f,(float16_t)0.5478515625000f, +(float16_t)-0.8383789062500f,(float16_t)0.5454101562500f, +(float16_t)-0.8398437500000f,(float16_t)0.5429687500000f, +(float16_t)-0.8417968750000f,(float16_t)0.5400390625000f, +(float16_t)-0.8432617187500f,(float16_t)0.5375976562500f, +(float16_t)-0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)-0.8466796875000f,(float16_t)0.5322265625000f, +(float16_t)-0.8481445312500f,(float16_t)0.5297851562500f, +(float16_t)-0.8496093750000f,(float16_t)0.5273437500000f, +(float16_t)-0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)-0.8530273437500f,(float16_t)0.5219726562500f, +(float16_t)-0.8544921875000f,(float16_t)0.5195312500000f, +(float16_t)-0.8559570312500f,(float16_t)0.5166015625000f, +(float16_t)-0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)-0.8593750000000f,(float16_t)0.5112304687500f, +(float16_t)-0.8608398437500f,(float16_t)0.5087890625000f, +(float16_t)-0.8623046875000f,(float16_t)0.5063476562500f, +(float16_t)-0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)-0.8657226562500f,(float16_t)0.5009765625000f, +(float16_t)-0.8671875000000f,(float16_t)0.4982910156250f, +(float16_t)-0.8686523437500f,(float16_t)0.4956054687500f, +(float16_t)-0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)-0.8715820312500f,(float16_t)0.4902343750000f, +(float16_t)-0.8730468750000f,(float16_t)0.4875488281250f, +(float16_t)-0.8745117187500f,(float16_t)0.4848632812500f, +(float16_t)-0.8759765625000f,(float16_t)0.4821777343750f, +(float16_t)-0.8774414062500f,(float16_t)0.4794921875000f, +(float16_t)-0.8789062500000f,(float16_t)0.4768066406250f, +(float16_t)-0.8803710937500f,(float16_t)0.4741210937500f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.8833007812500f,(float16_t)0.4687500000000f, +(float16_t)-0.8847656250000f,(float16_t)0.4660644531250f, +(float16_t)-0.8862304687500f,(float16_t)0.4633789062500f, +(float16_t)-0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)-0.8891601562500f,(float16_t)0.4577636718750f, +(float16_t)-0.8906250000000f,(float16_t)0.4550781250000f, +(float16_t)-0.8916015625000f,(float16_t)0.4523925781250f, +(float16_t)-0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)-0.8945312500000f,(float16_t)0.4467773437500f, +(float16_t)-0.8959960937500f,(float16_t)0.4440917968750f, +(float16_t)-0.8974609375000f,(float16_t)0.4414062500000f, +(float16_t)-0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)-0.8999023437500f,(float16_t)0.4357910156250f, +(float16_t)-0.9013671875000f,(float16_t)0.4331054687500f, +(float16_t)-0.9028320312500f,(float16_t)0.4304199218750f, +(float16_t)-0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)-0.9052734375000f,(float16_t)0.4248046875000f, +(float16_t)-0.9067382812500f,(float16_t)0.4221191406250f, +(float16_t)-0.9077148437500f,(float16_t)0.4191894531250f, +(float16_t)-0.9091796875000f,(float16_t)0.4165039062500f, +(float16_t)-0.9106445312500f,(float16_t)0.4135742187500f, +(float16_t)-0.9116210937500f,(float16_t)0.4108886718750f, +(float16_t)-0.9130859375000f,(float16_t)0.4079589843750f, +(float16_t)-0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)-0.9155273437500f,(float16_t)0.4023437500000f, +(float16_t)-0.9165039062500f,(float16_t)0.3996582031250f, +(float16_t)-0.9179687500000f,(float16_t)0.3967285156250f, +(float16_t)-0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)-0.9204101562500f,(float16_t)0.3911132812500f, +(float16_t)-0.9213867187500f,(float16_t)0.3884277343750f, +(float16_t)-0.9228515625000f,(float16_t)0.3854980468750f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9252929687500f,(float16_t)0.3798828125000f, +(float16_t)-0.9262695312500f,(float16_t)0.3769531250000f, +(float16_t)-0.9272460937500f,(float16_t)0.3742675781250f, +(float16_t)-0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)-0.9296875000000f,(float16_t)0.3684082031250f, +(float16_t)-0.9306640625000f,(float16_t)0.3657226562500f, +(float16_t)-0.9316406250000f,(float16_t)0.3627929687500f, +(float16_t)-0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)-0.9340820312500f,(float16_t)0.3569335937500f, +(float16_t)-0.9350585937500f,(float16_t)0.3542480468750f, +(float16_t)-0.9360351562500f,(float16_t)0.3513183593750f, +(float16_t)-0.9375000000000f,(float16_t)0.3483886718750f, +(float16_t)-0.9384765625000f,(float16_t)0.3454589843750f, +(float16_t)-0.9394531250000f,(float16_t)0.3427734375000f, +(float16_t)-0.9404296875000f,(float16_t)0.3398437500000f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9423828125000f,(float16_t)0.3339843750000f, +(float16_t)-0.9433593750000f,(float16_t)0.3310546875000f, +(float16_t)-0.9448242187500f,(float16_t)0.3281250000000f, +(float16_t)-0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)-0.9467773437500f,(float16_t)0.3225097656250f, +(float16_t)-0.9477539062500f,(float16_t)0.3195800781250f, +(float16_t)-0.9487304687500f,(float16_t)0.3166503906250f, +(float16_t)-0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)-0.9506835937500f,(float16_t)0.3107910156250f, +(float16_t)-0.9516601562500f,(float16_t)0.3078613281250f, +(float16_t)-0.9521484375000f,(float16_t)0.3049316406250f, +(float16_t)-0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)-0.9541015625000f,(float16_t)0.2990722656250f, +(float16_t)-0.9550781250000f,(float16_t)0.2961425781250f, +(float16_t)-0.9560546875000f,(float16_t)0.2932128906250f, +(float16_t)-0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)-0.9580078125000f,(float16_t)0.2873535156250f, +(float16_t)-0.9584960937500f,(float16_t)0.2844238281250f, +(float16_t)-0.9594726562500f,(float16_t)0.2814941406250f, +(float16_t)-0.9604492187500f,(float16_t)0.2785644531250f, +(float16_t)-0.9614257812500f,(float16_t)0.2756347656250f, +(float16_t)-0.9619140625000f,(float16_t)0.2727050781250f, +(float16_t)-0.9628906250000f,(float16_t)0.2697753906250f, +(float16_t)-0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)-0.9643554687500f,(float16_t)0.2636718750000f, +(float16_t)-0.9653320312500f,(float16_t)0.2607421875000f, +(float16_t)-0.9663085937500f,(float16_t)0.2578125000000f, +(float16_t)-0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)-0.9677734375000f,(float16_t)0.2519531250000f, +(float16_t)-0.9687500000000f,(float16_t)0.2489013671875f, +(float16_t)-0.9692382812500f,(float16_t)0.2459716796875f, +(float16_t)-0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)-0.9707031250000f,(float16_t)0.2399902343750f, +(float16_t)-0.9716796875000f,(float16_t)0.2370605468750f, +(float16_t)-0.9721679687500f,(float16_t)0.2340087890625f, +(float16_t)-0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)-0.9736328125000f,(float16_t)0.2280273437500f, +(float16_t)-0.9741210937500f,(float16_t)0.2250976562500f, +(float16_t)-0.9750976562500f,(float16_t)0.2220458984375f, +(float16_t)-0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)-0.9765625000000f,(float16_t)0.2160644531250f, +(float16_t)-0.9770507812500f,(float16_t)0.2131347656250f, +(float16_t)-0.9775390625000f,(float16_t)0.2100830078125f, +(float16_t)-0.9785156250000f,(float16_t)0.2071533203125f, +(float16_t)-0.9790039062500f,(float16_t)0.2041015625000f, +(float16_t)-0.9794921875000f,(float16_t)0.2010498046875f, +(float16_t)-0.9799804687500f,(float16_t)0.1981201171875f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9814453125000f,(float16_t)0.1921386718750f, +(float16_t)-0.9819335937500f,(float16_t)0.1890869140625f, +(float16_t)-0.9824218750000f,(float16_t)0.1860351562500f, +(float16_t)-0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)-0.9838867187500f,(float16_t)0.1800537109375f, +(float16_t)-0.9843750000000f,(float16_t)0.1770019531250f, +(float16_t)-0.9848632812500f,(float16_t)0.1739501953125f, +(float16_t)-0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)-0.9858398437500f,(float16_t)0.1679687500000f, +(float16_t)-0.9863281250000f,(float16_t)0.1649169921875f, +(float16_t)-0.9868164062500f,(float16_t)0.1618652343750f, +(float16_t)-0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)-0.9877929687500f,(float16_t)0.1558837890625f, +(float16_t)-0.9882812500000f,(float16_t)0.1528320312500f, +(float16_t)-0.9887695312500f,(float16_t)0.1497802734375f, +(float16_t)-0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)-0.9897460937500f,(float16_t)0.1436767578125f, +(float16_t)-0.9902343750000f,(float16_t)0.1406250000000f, +(float16_t)-0.9907226562500f,(float16_t)0.1375732421875f, +(float16_t)-0.9907226562500f,(float16_t)0.1345214843750f, +(float16_t)-0.9912109375000f,(float16_t)0.1315917968750f, +(float16_t)-0.9916992187500f,(float16_t)0.1285400390625f, +(float16_t)-0.9921875000000f,(float16_t)0.1254882812500f, +(float16_t)-0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)-0.9926757812500f,(float16_t)0.1193847656250f, +(float16_t)-0.9931640625000f,(float16_t)0.1163330078125f, +(float16_t)-0.9936523437500f,(float16_t)0.1132812500000f, +(float16_t)-0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)-0.9941406250000f,(float16_t)0.1071777343750f, +(float16_t)-0.9946289062500f,(float16_t)0.1041259765625f, +(float16_t)-0.9951171875000f,(float16_t)0.1010742187500f, +(float16_t)-0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)-0.9956054687500f,(float16_t)0.0949707031250f, +(float16_t)-0.9956054687500f,(float16_t)0.0919189453125f, +(float16_t)-0.9960937500000f,(float16_t)0.0888671875000f, +(float16_t)-0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)-0.9965820312500f,(float16_t)0.0827636718750f, +(float16_t)-0.9965820312500f,(float16_t)0.0797119140625f, +(float16_t)-0.9970703125000f,(float16_t)0.0765991210938f, +(float16_t)-0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)-0.9975585937500f,(float16_t)0.0704956054688f, +(float16_t)-0.9975585937500f,(float16_t)0.0674438476562f, +(float16_t)-0.9980468750000f,(float16_t)0.0643920898438f, +(float16_t)-0.9980468750000f,(float16_t)0.0613098144531f, +(float16_t)-0.9985351562500f,(float16_t)0.0582580566406f, +(float16_t)-0.9985351562500f,(float16_t)0.0552062988281f, +(float16_t)-0.9985351562500f,(float16_t)0.0521240234375f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)-0.9990234375000f,(float16_t)0.0459899902344f, +(float16_t)-0.9990234375000f,(float16_t)0.0429382324219f, +(float16_t)-0.9990234375000f,(float16_t)0.0398864746094f, +(float16_t)-0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)-0.9995117187500f,(float16_t)0.0337524414062f, +(float16_t)-0.9995117187500f,(float16_t)0.0306701660156f, +(float16_t)-0.9995117187500f,(float16_t)0.0276031494141f, +(float16_t)-0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)-1.0000000000000f,(float16_t)0.0214691162109f, +(float16_t)-1.0000000000000f,(float16_t)0.0184020996094f, +(float16_t)-1.0000000000000f,(float16_t)0.0153427124023f, +(float16_t)-1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)-1.0000000000000f,(float16_t)0.0092010498047f, +(float16_t)-1.0000000000000f,(float16_t)0.0061340332031f, +(float16_t)-1.0000000000000f,(float16_t)0.0030670166016f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9980468750000f,(float16_t)0.0613098144531f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)0.9907226562500f,(float16_t)0.1345214843750f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9785156250000f,(float16_t)0.2071533203125f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)0.9604492187500f,(float16_t)0.2785644531250f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9375000000000f,(float16_t)0.3483886718750f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)0.9091796875000f,(float16_t)0.4165039062500f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8759765625000f,(float16_t)0.4821777343750f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)0.8383789062500f,(float16_t)0.5454101562500f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.7958984375000f,(float16_t)0.6054687500000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)0.7490234375000f,(float16_t)0.6625976562500f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6982421875000f,(float16_t)0.7158203125000f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)0.6440429687500f,(float16_t)0.7651367187500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5859375000000f,(float16_t)0.8105468750000f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)0.5244140625000f,(float16_t)0.8515625000000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4604492187500f,(float16_t)0.8876953125000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)0.3940429687500f,(float16_t)0.9189453125000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.3251953125000f,(float16_t)0.9458007812500f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)0.2548828125000f,(float16_t)0.9667968750000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1829833984375f,(float16_t)0.9829101562500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)0.1102294921875f,(float16_t)0.9941406250000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0368041992188f,(float16_t)0.9995117187500f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)-0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)-0.0368041992188f,(float16_t)0.9995117187500f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)-0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)-0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)-0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1102294921875f,(float16_t)0.9941406250000f, +(float16_t)-0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)-0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)-0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)-0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)-0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)-0.1829833984375f,(float16_t)0.9829101562500f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)-0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)-0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)-0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)-0.2548828125000f,(float16_t)0.9667968750000f, +(float16_t)-0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)-0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)-0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)-0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)-0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)-0.3251953125000f,(float16_t)0.9458007812500f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)-0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)-0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.3940429687500f,(float16_t)0.9189453125000f, +(float16_t)-0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)-0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)-0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)-0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)-0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)-0.4604492187500f,(float16_t)0.8876953125000f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)-0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)-0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)-0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)-0.5244140625000f,(float16_t)0.8515625000000f, +(float16_t)-0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)-0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)-0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)-0.5859375000000f,(float16_t)0.8105468750000f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)-0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)-0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)-0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)-0.6440429687500f,(float16_t)0.7651367187500f, +(float16_t)-0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)-0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)-0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)-0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)-0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)-0.6982421875000f,(float16_t)0.7158203125000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)-0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)-0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)-0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)-0.7490234375000f,(float16_t)0.6625976562500f, +(float16_t)-0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)-0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)-0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)-0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)-0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)-0.7958984375000f,(float16_t)0.6054687500000f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)-0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)-0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.8383789062500f,(float16_t)0.5454101562500f, +(float16_t)-0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)-0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)-0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)-0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)-0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)-0.8759765625000f,(float16_t)0.4821777343750f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)-0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)-0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)-0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)-0.9091796875000f,(float16_t)0.4165039062500f, +(float16_t)-0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)-0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)-0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)-0.9375000000000f,(float16_t)0.3483886718750f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)-0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)-0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)-0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)-0.9604492187500f,(float16_t)0.2785644531250f, +(float16_t)-0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)-0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)-0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)-0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)-0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)-0.9785156250000f,(float16_t)0.2071533203125f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)-0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)-0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)-0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)-0.9907226562500f,(float16_t)0.1345214843750f, +(float16_t)-0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)-0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)-0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)-0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)-0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)-0.9980468750000f,(float16_t)0.0613098144531f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)-0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)-0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)-1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)-0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)-0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)-0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)-0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)-0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f,}; + +float16_t rearranged_twiddle_stride3_4096_f16[2728]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0046005249023f, +(float16_t)1.0000000000000f,(float16_t)0.0092010498047f, +(float16_t)1.0000000000000f,(float16_t)0.0138015747070f, +(float16_t)1.0000000000000f,(float16_t)0.0184020996094f, +(float16_t)0.9995117187500f,(float16_t)0.0230102539062f, +(float16_t)0.9995117187500f,(float16_t)0.0276031494141f, +(float16_t)0.9995117187500f,(float16_t)0.0321960449219f, +(float16_t)0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)0.9990234375000f,(float16_t)0.0414123535156f, +(float16_t)0.9990234375000f,(float16_t)0.0459899902344f, +(float16_t)0.9985351562500f,(float16_t)0.0505981445312f, +(float16_t)0.9985351562500f,(float16_t)0.0552062988281f, +(float16_t)0.9980468750000f,(float16_t)0.0597839355469f, +(float16_t)0.9980468750000f,(float16_t)0.0643920898438f, +(float16_t)0.9975585937500f,(float16_t)0.0689697265625f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9970703125000f,(float16_t)0.0781250000000f, +(float16_t)0.9965820312500f,(float16_t)0.0827636718750f, +(float16_t)0.9960937500000f,(float16_t)0.0873413085938f, +(float16_t)0.9956054687500f,(float16_t)0.0919189453125f, +(float16_t)0.9951171875000f,(float16_t)0.0964965820312f, +(float16_t)0.9951171875000f,(float16_t)0.1010742187500f, +(float16_t)0.9946289062500f,(float16_t)0.1056518554688f, +(float16_t)0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)0.9931640625000f,(float16_t)0.1148071289062f, +(float16_t)0.9926757812500f,(float16_t)0.1193847656250f, +(float16_t)0.9921875000000f,(float16_t)0.1239624023438f, +(float16_t)0.9916992187500f,(float16_t)0.1285400390625f, +(float16_t)0.9912109375000f,(float16_t)0.1330566406250f, +(float16_t)0.9907226562500f,(float16_t)0.1375732421875f, +(float16_t)0.9897460937500f,(float16_t)0.1422119140625f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9882812500000f,(float16_t)0.1512451171875f, +(float16_t)0.9877929687500f,(float16_t)0.1558837890625f, +(float16_t)0.9868164062500f,(float16_t)0.1604003906250f, +(float16_t)0.9863281250000f,(float16_t)0.1649169921875f, +(float16_t)0.9853515625000f,(float16_t)0.1694335937500f, +(float16_t)0.9848632812500f,(float16_t)0.1739501953125f, +(float16_t)0.9838867187500f,(float16_t)0.1784667968750f, +(float16_t)0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)0.9824218750000f,(float16_t)0.1876220703125f, +(float16_t)0.9814453125000f,(float16_t)0.1921386718750f, +(float16_t)0.9804687500000f,(float16_t)0.1966552734375f, +(float16_t)0.9794921875000f,(float16_t)0.2010498046875f, +(float16_t)0.9785156250000f,(float16_t)0.2055664062500f, +(float16_t)0.9775390625000f,(float16_t)0.2100830078125f, +(float16_t)0.9765625000000f,(float16_t)0.2145996093750f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9746093750000f,(float16_t)0.2236328125000f, +(float16_t)0.9736328125000f,(float16_t)0.2280273437500f, +(float16_t)0.9726562500000f,(float16_t)0.2325439453125f, +(float16_t)0.9716796875000f,(float16_t)0.2370605468750f, +(float16_t)0.9702148437500f,(float16_t)0.2414550781250f, +(float16_t)0.9692382812500f,(float16_t)0.2459716796875f, +(float16_t)0.9682617187500f,(float16_t)0.2504882812500f, +(float16_t)0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)0.9658203125000f,(float16_t)0.2592773437500f, +(float16_t)0.9643554687500f,(float16_t)0.2636718750000f, +(float16_t)0.9633789062500f,(float16_t)0.2683105468750f, +(float16_t)0.9619140625000f,(float16_t)0.2727050781250f, +(float16_t)0.9609375000000f,(float16_t)0.2770996093750f, +(float16_t)0.9594726562500f,(float16_t)0.2814941406250f, +(float16_t)0.9584960937500f,(float16_t)0.2858886718750f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9555664062500f,(float16_t)0.2946777343750f, +(float16_t)0.9541015625000f,(float16_t)0.2990722656250f, +(float16_t)0.9526367187500f,(float16_t)0.3034667968750f, +(float16_t)0.9516601562500f,(float16_t)0.3078613281250f, +(float16_t)0.9501953125000f,(float16_t)0.3122558593750f, +(float16_t)0.9487304687500f,(float16_t)0.3166503906250f, +(float16_t)0.9472656250000f,(float16_t)0.3210449218750f, +(float16_t)0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)0.9443359375000f,(float16_t)0.3295898437500f, +(float16_t)0.9423828125000f,(float16_t)0.3339843750000f, +(float16_t)0.9409179687500f,(float16_t)0.3383789062500f, +(float16_t)0.9394531250000f,(float16_t)0.3427734375000f, +(float16_t)0.9379882812500f,(float16_t)0.3469238281250f, +(float16_t)0.9360351562500f,(float16_t)0.3513183593750f, +(float16_t)0.9345703125000f,(float16_t)0.3557128906250f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9311523437500f,(float16_t)0.3642578125000f, +(float16_t)0.9296875000000f,(float16_t)0.3684082031250f, +(float16_t)0.9277343750000f,(float16_t)0.3728027343750f, +(float16_t)0.9262695312500f,(float16_t)0.3769531250000f, +(float16_t)0.9243164062500f,(float16_t)0.3813476562500f, +(float16_t)0.9228515625000f,(float16_t)0.3854980468750f, +(float16_t)0.9208984375000f,(float16_t)0.3896484375000f, +(float16_t)0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)0.9174804687500f,(float16_t)0.3981933593750f, +(float16_t)0.9155273437500f,(float16_t)0.4023437500000f, +(float16_t)0.9135742187500f,(float16_t)0.4067382812500f, +(float16_t)0.9116210937500f,(float16_t)0.4108886718750f, +(float16_t)0.9096679687500f,(float16_t)0.4150390625000f, +(float16_t)0.9077148437500f,(float16_t)0.4191894531250f, +(float16_t)0.9057617187500f,(float16_t)0.4233398437500f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.9018554687500f,(float16_t)0.4316406250000f, +(float16_t)0.8999023437500f,(float16_t)0.4357910156250f, +(float16_t)0.8979492187500f,(float16_t)0.4399414062500f, +(float16_t)0.8959960937500f,(float16_t)0.4440917968750f, +(float16_t)0.8940429687500f,(float16_t)0.4482421875000f, +(float16_t)0.8916015625000f,(float16_t)0.4523925781250f, +(float16_t)0.8896484375000f,(float16_t)0.4565429687500f, +(float16_t)0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)0.8857421875000f,(float16_t)0.4645996093750f, +(float16_t)0.8833007812500f,(float16_t)0.4687500000000f, +(float16_t)0.8813476562500f,(float16_t)0.4726562500000f, +(float16_t)0.8789062500000f,(float16_t)0.4768066406250f, +(float16_t)0.8769531250000f,(float16_t)0.4809570312500f, +(float16_t)0.8745117187500f,(float16_t)0.4848632812500f, +(float16_t)0.8725585937500f,(float16_t)0.4887695312500f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8676757812500f,(float16_t)0.4968261718750f, +(float16_t)0.8657226562500f,(float16_t)0.5009765625000f, +(float16_t)0.8632812500000f,(float16_t)0.5048828125000f, +(float16_t)0.8608398437500f,(float16_t)0.5087890625000f, +(float16_t)0.8583984375000f,(float16_t)0.5126953125000f, +(float16_t)0.8559570312500f,(float16_t)0.5166015625000f, +(float16_t)0.8540039062500f,(float16_t)0.5205078125000f, +(float16_t)0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)0.8491210937500f,(float16_t)0.5283203125000f, +(float16_t)0.8466796875000f,(float16_t)0.5322265625000f, +(float16_t)0.8442382812500f,(float16_t)0.5361328125000f, +(float16_t)0.8417968750000f,(float16_t)0.5400390625000f, +(float16_t)0.8388671875000f,(float16_t)0.5439453125000f, +(float16_t)0.8364257812500f,(float16_t)0.5478515625000f, +(float16_t)0.8339843750000f,(float16_t)0.5517578125000f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8291015625000f,(float16_t)0.5595703125000f, +(float16_t)0.8261718750000f,(float16_t)0.5629882812500f, +(float16_t)0.8237304687500f,(float16_t)0.5668945312500f, +(float16_t)0.8212890625000f,(float16_t)0.5708007812500f, +(float16_t)0.8183593750000f,(float16_t)0.5747070312500f, +(float16_t)0.8159179687500f,(float16_t)0.5781250000000f, +(float16_t)0.8129882812500f,(float16_t)0.5820312500000f, +(float16_t)0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)0.8076171875000f,(float16_t)0.5893554687500f, +(float16_t)0.8051757812500f,(float16_t)0.5932617187500f, +(float16_t)0.8022460937500f,(float16_t)0.5971679687500f, +(float16_t)0.7993164062500f,(float16_t)0.6005859375000f, +(float16_t)0.7968750000000f,(float16_t)0.6044921875000f, +(float16_t)0.7939453125000f,(float16_t)0.6079101562500f, +(float16_t)0.7910156250000f,(float16_t)0.6118164062500f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7856445312500f,(float16_t)0.6186523437500f, +(float16_t)0.7827148437500f,(float16_t)0.6225585937500f, +(float16_t)0.7797851562500f,(float16_t)0.6259765625000f, +(float16_t)0.7768554687500f,(float16_t)0.6293945312500f, +(float16_t)0.7739257812500f,(float16_t)0.6333007812500f, +(float16_t)0.7709960937500f,(float16_t)0.6367187500000f, +(float16_t)0.7680664062500f,(float16_t)0.6401367187500f, +(float16_t)0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)0.7622070312500f,(float16_t)0.6474609375000f, +(float16_t)0.7592773437500f,(float16_t)0.6508789062500f, +(float16_t)0.7563476562500f,(float16_t)0.6542968750000f, +(float16_t)0.7534179687500f,(float16_t)0.6577148437500f, +(float16_t)0.7500000000000f,(float16_t)0.6611328125000f, +(float16_t)0.7470703125000f,(float16_t)0.6645507812500f, +(float16_t)0.7441406250000f,(float16_t)0.6679687500000f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7377929687500f,(float16_t)0.6748046875000f, +(float16_t)0.7348632812500f,(float16_t)0.6782226562500f, +(float16_t)0.7314453125000f,(float16_t)0.6816406250000f, +(float16_t)0.7285156250000f,(float16_t)0.6850585937500f, +(float16_t)0.7250976562500f,(float16_t)0.6884765625000f, +(float16_t)0.7221679687500f,(float16_t)0.6918945312500f, +(float16_t)0.7187500000000f,(float16_t)0.6953125000000f, +(float16_t)0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)0.7124023437500f,(float16_t)0.7016601562500f, +(float16_t)0.7094726562500f,(float16_t)0.7050781250000f, +(float16_t)0.7060546875000f,(float16_t)0.7080078125000f, +(float16_t)0.7026367187500f,(float16_t)0.7114257812500f, +(float16_t)0.6997070312500f,(float16_t)0.7148437500000f, +(float16_t)0.6962890625000f,(float16_t)0.7177734375000f, +(float16_t)0.6928710937500f,(float16_t)0.7211914062500f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6860351562500f,(float16_t)0.7275390625000f, +(float16_t)0.6826171875000f,(float16_t)0.7304687500000f, +(float16_t)0.6796875000000f,(float16_t)0.7338867187500f, +(float16_t)0.6762695312500f,(float16_t)0.7368164062500f, +(float16_t)0.6728515625000f,(float16_t)0.7397460937500f, +(float16_t)0.6694335937500f,(float16_t)0.7431640625000f, +(float16_t)0.6660156250000f,(float16_t)0.7460937500000f, +(float16_t)0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)0.6591796875000f,(float16_t)0.7519531250000f, +(float16_t)0.6552734375000f,(float16_t)0.7553710937500f, +(float16_t)0.6518554687500f,(float16_t)0.7583007812500f, +(float16_t)0.6484375000000f,(float16_t)0.7612304687500f, +(float16_t)0.6450195312500f,(float16_t)0.7641601562500f, +(float16_t)0.6416015625000f,(float16_t)0.7670898437500f, +(float16_t)0.6381835937500f,(float16_t)0.7700195312500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6308593750000f,(float16_t)0.7758789062500f, +(float16_t)0.6274414062500f,(float16_t)0.7788085937500f, +(float16_t)0.6235351562500f,(float16_t)0.7817382812500f, +(float16_t)0.6201171875000f,(float16_t)0.7846679687500f, +(float16_t)0.6162109375000f,(float16_t)0.7875976562500f, +(float16_t)0.6127929687500f,(float16_t)0.7900390625000f, +(float16_t)0.6093750000000f,(float16_t)0.7929687500000f, +(float16_t)0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)0.6020507812500f,(float16_t)0.7988281250000f, +(float16_t)0.5981445312500f,(float16_t)0.8012695312500f, +(float16_t)0.5942382812500f,(float16_t)0.8041992187500f, +(float16_t)0.5908203125000f,(float16_t)0.8066406250000f, +(float16_t)0.5869140625000f,(float16_t)0.8095703125000f, +(float16_t)0.5834960937500f,(float16_t)0.8120117187500f, +(float16_t)0.5795898437500f,(float16_t)0.8149414062500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5722656250000f,(float16_t)0.8203125000000f, +(float16_t)0.5683593750000f,(float16_t)0.8227539062500f, +(float16_t)0.5644531250000f,(float16_t)0.8256835937500f, +(float16_t)0.5605468750000f,(float16_t)0.8281250000000f, +(float16_t)0.5566406250000f,(float16_t)0.8305664062500f, +(float16_t)0.5532226562500f,(float16_t)0.8330078125000f, +(float16_t)0.5493164062500f,(float16_t)0.8359375000000f, +(float16_t)0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)0.5415039062500f,(float16_t)0.8408203125000f, +(float16_t)0.5375976562500f,(float16_t)0.8432617187500f, +(float16_t)0.5336914062500f,(float16_t)0.8457031250000f, +(float16_t)0.5297851562500f,(float16_t)0.8481445312500f, +(float16_t)0.5258789062500f,(float16_t)0.8505859375000f, +(float16_t)0.5219726562500f,(float16_t)0.8530273437500f, +(float16_t)0.5180664062500f,(float16_t)0.8554687500000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.5102539062500f,(float16_t)0.8598632812500f, +(float16_t)0.5063476562500f,(float16_t)0.8623046875000f, +(float16_t)0.5024414062500f,(float16_t)0.8647460937500f, +(float16_t)0.4982910156250f,(float16_t)0.8671875000000f, +(float16_t)0.4941406250000f,(float16_t)0.8691406250000f, +(float16_t)0.4902343750000f,(float16_t)0.8715820312500f, +(float16_t)0.4863281250000f,(float16_t)0.8740234375000f, +(float16_t)0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)0.4780273437500f,(float16_t)0.8784179687500f, +(float16_t)0.4741210937500f,(float16_t)0.8803710937500f, +(float16_t)0.4699707031250f,(float16_t)0.8828125000000f, +(float16_t)0.4660644531250f,(float16_t)0.8847656250000f, +(float16_t)0.4619140625000f,(float16_t)0.8867187500000f, +(float16_t)0.4577636718750f,(float16_t)0.8891601562500f, +(float16_t)0.4536132812500f,(float16_t)0.8911132812500f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4455566406250f,(float16_t)0.8955078125000f, +(float16_t)0.4414062500000f,(float16_t)0.8974609375000f, +(float16_t)0.4372558593750f,(float16_t)0.8994140625000f, +(float16_t)0.4331054687500f,(float16_t)0.9013671875000f, +(float16_t)0.4289550781250f,(float16_t)0.9033203125000f, +(float16_t)0.4248046875000f,(float16_t)0.9052734375000f, +(float16_t)0.4206542968750f,(float16_t)0.9072265625000f, +(float16_t)0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)0.4123535156250f,(float16_t)0.9111328125000f, +(float16_t)0.4079589843750f,(float16_t)0.9130859375000f, +(float16_t)0.4038085937500f,(float16_t)0.9150390625000f, +(float16_t)0.3996582031250f,(float16_t)0.9165039062500f, +(float16_t)0.3955078125000f,(float16_t)0.9184570312500f, +(float16_t)0.3911132812500f,(float16_t)0.9204101562500f, +(float16_t)0.3869628906250f,(float16_t)0.9218750000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3784179687500f,(float16_t)0.9257812500000f, +(float16_t)0.3742675781250f,(float16_t)0.9272460937500f, +(float16_t)0.3698730468750f,(float16_t)0.9291992187500f, +(float16_t)0.3657226562500f,(float16_t)0.9306640625000f, +(float16_t)0.3613281250000f,(float16_t)0.9326171875000f, +(float16_t)0.3569335937500f,(float16_t)0.9340820312500f, +(float16_t)0.3527832031250f,(float16_t)0.9355468750000f, +(float16_t)0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)0.3439941406250f,(float16_t)0.9389648437500f, +(float16_t)0.3398437500000f,(float16_t)0.9404296875000f, +(float16_t)0.3354492187500f,(float16_t)0.9418945312500f, +(float16_t)0.3310546875000f,(float16_t)0.9433593750000f, +(float16_t)0.3266601562500f,(float16_t)0.9453125000000f, +(float16_t)0.3225097656250f,(float16_t)0.9467773437500f, +(float16_t)0.3181152343750f,(float16_t)0.9482421875000f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.3093261718750f,(float16_t)0.9511718750000f, +(float16_t)0.3049316406250f,(float16_t)0.9521484375000f, +(float16_t)0.3005371093750f,(float16_t)0.9536132812500f, +(float16_t)0.2961425781250f,(float16_t)0.9550781250000f, +(float16_t)0.2917480468750f,(float16_t)0.9565429687500f, +(float16_t)0.2873535156250f,(float16_t)0.9580078125000f, +(float16_t)0.2829589843750f,(float16_t)0.9589843750000f, +(float16_t)0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)0.2741699218750f,(float16_t)0.9619140625000f, +(float16_t)0.2697753906250f,(float16_t)0.9628906250000f, +(float16_t)0.2651367187500f,(float16_t)0.9643554687500f, +(float16_t)0.2607421875000f,(float16_t)0.9653320312500f, +(float16_t)0.2563476562500f,(float16_t)0.9667968750000f, +(float16_t)0.2519531250000f,(float16_t)0.9677734375000f, +(float16_t)0.2474365234375f,(float16_t)0.9687500000000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2385253906250f,(float16_t)0.9711914062500f, +(float16_t)0.2340087890625f,(float16_t)0.9721679687500f, +(float16_t)0.2296142578125f,(float16_t)0.9731445312500f, +(float16_t)0.2250976562500f,(float16_t)0.9741210937500f, +(float16_t)0.2205810546875f,(float16_t)0.9755859375000f, +(float16_t)0.2160644531250f,(float16_t)0.9765625000000f, +(float16_t)0.2116699218750f,(float16_t)0.9775390625000f, +(float16_t)0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)0.2026367187500f,(float16_t)0.9794921875000f, +(float16_t)0.1981201171875f,(float16_t)0.9799804687500f, +(float16_t)0.1936035156250f,(float16_t)0.9809570312500f, +(float16_t)0.1890869140625f,(float16_t)0.9819335937500f, +(float16_t)0.1845703125000f,(float16_t)0.9829101562500f, +(float16_t)0.1800537109375f,(float16_t)0.9838867187500f, +(float16_t)0.1755371093750f,(float16_t)0.9843750000000f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1663818359375f,(float16_t)0.9858398437500f, +(float16_t)0.1618652343750f,(float16_t)0.9868164062500f, +(float16_t)0.1573486328125f,(float16_t)0.9873046875000f, +(float16_t)0.1528320312500f,(float16_t)0.9882812500000f, +(float16_t)0.1481933593750f,(float16_t)0.9887695312500f, +(float16_t)0.1436767578125f,(float16_t)0.9897460937500f, +(float16_t)0.1391601562500f,(float16_t)0.9902343750000f, +(float16_t)0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)0.1300048828125f,(float16_t)0.9916992187500f, +(float16_t)0.1254882812500f,(float16_t)0.9921875000000f, +(float16_t)0.1209106445312f,(float16_t)0.9926757812500f, +(float16_t)0.1163330078125f,(float16_t)0.9931640625000f, +(float16_t)0.1117553710938f,(float16_t)0.9936523437500f, +(float16_t)0.1071777343750f,(float16_t)0.9941406250000f, +(float16_t)0.1026000976562f,(float16_t)0.9946289062500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0934448242188f,(float16_t)0.9956054687500f, +(float16_t)0.0888671875000f,(float16_t)0.9960937500000f, +(float16_t)0.0842895507812f,(float16_t)0.9965820312500f, +(float16_t)0.0797119140625f,(float16_t)0.9965820312500f, +(float16_t)0.0750732421875f,(float16_t)0.9970703125000f, +(float16_t)0.0704956054688f,(float16_t)0.9975585937500f, +(float16_t)0.0659179687500f,(float16_t)0.9980468750000f, +(float16_t)0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)0.0567321777344f,(float16_t)0.9985351562500f, +(float16_t)0.0521240234375f,(float16_t)0.9985351562500f, +(float16_t)0.0475463867188f,(float16_t)0.9990234375000f, +(float16_t)0.0429382324219f,(float16_t)0.9990234375000f, +(float16_t)0.0383300781250f,(float16_t)0.9990234375000f, +(float16_t)0.0337524414062f,(float16_t)0.9995117187500f, +(float16_t)0.0291442871094f,(float16_t)0.9995117187500f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)0.0199432373047f,(float16_t)1.0000000000000f, +(float16_t)0.0153427124023f,(float16_t)1.0000000000000f, +(float16_t)0.0107345581055f,(float16_t)1.0000000000000f, +(float16_t)0.0061340332031f,(float16_t)1.0000000000000f, +(float16_t)0.0015335083008f,(float16_t)1.0000000000000f, +(float16_t)-0.0030670166016f,(float16_t)1.0000000000000f, +(float16_t)-0.0076713562012f,(float16_t)1.0000000000000f, +(float16_t)-0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)-0.0168762207031f,(float16_t)1.0000000000000f, +(float16_t)-0.0214691162109f,(float16_t)1.0000000000000f, +(float16_t)-0.0260772705078f,(float16_t)0.9995117187500f, +(float16_t)-0.0306701660156f,(float16_t)0.9995117187500f, +(float16_t)-0.0352783203125f,(float16_t)0.9995117187500f, +(float16_t)-0.0398864746094f,(float16_t)0.9990234375000f, +(float16_t)-0.0444641113281f,(float16_t)0.9990234375000f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.0536499023438f,(float16_t)0.9985351562500f, +(float16_t)-0.0582580566406f,(float16_t)0.9985351562500f, +(float16_t)-0.0628662109375f,(float16_t)0.9980468750000f, +(float16_t)-0.0674438476562f,(float16_t)0.9975585937500f, +(float16_t)-0.0720214843750f,(float16_t)0.9975585937500f, +(float16_t)-0.0765991210938f,(float16_t)0.9970703125000f, +(float16_t)-0.0812377929688f,(float16_t)0.9965820312500f, +(float16_t)-0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)-0.0903930664062f,(float16_t)0.9960937500000f, +(float16_t)-0.0949707031250f,(float16_t)0.9956054687500f, +(float16_t)-0.0995483398438f,(float16_t)0.9951171875000f, +(float16_t)-0.1041259765625f,(float16_t)0.9946289062500f, +(float16_t)-0.1087036132812f,(float16_t)0.9941406250000f, +(float16_t)-0.1132812500000f,(float16_t)0.9936523437500f, +(float16_t)-0.1178588867188f,(float16_t)0.9931640625000f, +(float16_t)-0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)-0.1269531250000f,(float16_t)0.9916992187500f, +(float16_t)-0.1315917968750f,(float16_t)0.9912109375000f, +(float16_t)-0.1361083984375f,(float16_t)0.9907226562500f, +(float16_t)-0.1406250000000f,(float16_t)0.9902343750000f, +(float16_t)-0.1452636718750f,(float16_t)0.9892578125000f, +(float16_t)-0.1497802734375f,(float16_t)0.9887695312500f, +(float16_t)-0.1542968750000f,(float16_t)0.9877929687500f, +(float16_t)-0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)-0.1634521484375f,(float16_t)0.9863281250000f, +(float16_t)-0.1679687500000f,(float16_t)0.9858398437500f, +(float16_t)-0.1724853515625f,(float16_t)0.9848632812500f, +(float16_t)-0.1770019531250f,(float16_t)0.9843750000000f, +(float16_t)-0.1815185546875f,(float16_t)0.9833984375000f, +(float16_t)-0.1860351562500f,(float16_t)0.9824218750000f, +(float16_t)-0.1905517578125f,(float16_t)0.9814453125000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.1995849609375f,(float16_t)0.9799804687500f, +(float16_t)-0.2041015625000f,(float16_t)0.9790039062500f, +(float16_t)-0.2086181640625f,(float16_t)0.9780273437500f, +(float16_t)-0.2131347656250f,(float16_t)0.9770507812500f, +(float16_t)-0.2176513671875f,(float16_t)0.9760742187500f, +(float16_t)-0.2220458984375f,(float16_t)0.9750976562500f, +(float16_t)-0.2265625000000f,(float16_t)0.9741210937500f, +(float16_t)-0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)-0.2354736328125f,(float16_t)0.9716796875000f, +(float16_t)-0.2399902343750f,(float16_t)0.9707031250000f, +(float16_t)-0.2445068359375f,(float16_t)0.9697265625000f, +(float16_t)-0.2489013671875f,(float16_t)0.9687500000000f, +(float16_t)-0.2534179687500f,(float16_t)0.9672851562500f, +(float16_t)-0.2578125000000f,(float16_t)0.9663085937500f, +(float16_t)-0.2622070312500f,(float16_t)0.9648437500000f, +(float16_t)-0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)-0.2712402343750f,(float16_t)0.9624023437500f, +(float16_t)-0.2756347656250f,(float16_t)0.9614257812500f, +(float16_t)-0.2800292968750f,(float16_t)0.9599609375000f, +(float16_t)-0.2844238281250f,(float16_t)0.9584960937500f, +(float16_t)-0.2888183593750f,(float16_t)0.9575195312500f, +(float16_t)-0.2932128906250f,(float16_t)0.9560546875000f, +(float16_t)-0.2976074218750f,(float16_t)0.9545898437500f, +(float16_t)-0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)-0.3063964843750f,(float16_t)0.9521484375000f, +(float16_t)-0.3107910156250f,(float16_t)0.9506835937500f, +(float16_t)-0.3151855468750f,(float16_t)0.9492187500000f, +(float16_t)-0.3195800781250f,(float16_t)0.9477539062500f, +(float16_t)-0.3239746093750f,(float16_t)0.9462890625000f, +(float16_t)-0.3281250000000f,(float16_t)0.9448242187500f, +(float16_t)-0.3325195312500f,(float16_t)0.9428710937500f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.3413085937500f,(float16_t)0.9399414062500f, +(float16_t)-0.3454589843750f,(float16_t)0.9384765625000f, +(float16_t)-0.3498535156250f,(float16_t)0.9370117187500f, +(float16_t)-0.3542480468750f,(float16_t)0.9350585937500f, +(float16_t)-0.3583984375000f,(float16_t)0.9335937500000f, +(float16_t)-0.3627929687500f,(float16_t)0.9316406250000f, +(float16_t)-0.3669433593750f,(float16_t)0.9301757812500f, +(float16_t)-0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)-0.3754882812500f,(float16_t)0.9267578125000f, +(float16_t)-0.3798828125000f,(float16_t)0.9252929687500f, +(float16_t)-0.3840332031250f,(float16_t)0.9233398437500f, +(float16_t)-0.3884277343750f,(float16_t)0.9213867187500f, +(float16_t)-0.3925781250000f,(float16_t)0.9199218750000f, +(float16_t)-0.3967285156250f,(float16_t)0.9179687500000f, +(float16_t)-0.4011230468750f,(float16_t)0.9160156250000f, +(float16_t)-0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)-0.4094238281250f,(float16_t)0.9121093750000f, +(float16_t)-0.4135742187500f,(float16_t)0.9106445312500f, +(float16_t)-0.4177246093750f,(float16_t)0.9086914062500f, +(float16_t)-0.4221191406250f,(float16_t)0.9067382812500f, +(float16_t)-0.4262695312500f,(float16_t)0.9047851562500f, +(float16_t)-0.4304199218750f,(float16_t)0.9028320312500f, +(float16_t)-0.4345703125000f,(float16_t)0.9008789062500f, +(float16_t)-0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)-0.4426269531250f,(float16_t)0.8964843750000f, +(float16_t)-0.4467773437500f,(float16_t)0.8945312500000f, +(float16_t)-0.4509277343750f,(float16_t)0.8925781250000f, +(float16_t)-0.4550781250000f,(float16_t)0.8906250000000f, +(float16_t)-0.4592285156250f,(float16_t)0.8881835937500f, +(float16_t)-0.4633789062500f,(float16_t)0.8862304687500f, +(float16_t)-0.4672851562500f,(float16_t)0.8842773437500f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.4753417968750f,(float16_t)0.8798828125000f, +(float16_t)-0.4794921875000f,(float16_t)0.8774414062500f, +(float16_t)-0.4836425781250f,(float16_t)0.8754882812500f, +(float16_t)-0.4875488281250f,(float16_t)0.8730468750000f, +(float16_t)-0.4914550781250f,(float16_t)0.8706054687500f, +(float16_t)-0.4956054687500f,(float16_t)0.8686523437500f, +(float16_t)-0.4995117187500f,(float16_t)0.8662109375000f, +(float16_t)-0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)-0.5073242187500f,(float16_t)0.8618164062500f, +(float16_t)-0.5112304687500f,(float16_t)0.8593750000000f, +(float16_t)-0.5156250000000f,(float16_t)0.8569335937500f, +(float16_t)-0.5195312500000f,(float16_t)0.8544921875000f, +(float16_t)-0.5234375000000f,(float16_t)0.8520507812500f, +(float16_t)-0.5273437500000f,(float16_t)0.8496093750000f, +(float16_t)-0.5312500000000f,(float16_t)0.8471679687500f, +(float16_t)-0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)-0.5390625000000f,(float16_t)0.8422851562500f, +(float16_t)-0.5429687500000f,(float16_t)0.8398437500000f, +(float16_t)-0.5463867187500f,(float16_t)0.8374023437500f, +(float16_t)-0.5502929687500f,(float16_t)0.8349609375000f, +(float16_t)-0.5541992187500f,(float16_t)0.8325195312500f, +(float16_t)-0.5581054687500f,(float16_t)0.8295898437500f, +(float16_t)-0.5620117187500f,(float16_t)0.8271484375000f, +(float16_t)-0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)-0.5693359375000f,(float16_t)0.8217773437500f, +(float16_t)-0.5732421875000f,(float16_t)0.8193359375000f, +(float16_t)-0.5771484375000f,(float16_t)0.8168945312500f, +(float16_t)-0.5810546875000f,(float16_t)0.8139648437500f, +(float16_t)-0.5844726562500f,(float16_t)0.8115234375000f, +(float16_t)-0.5883789062500f,(float16_t)0.8085937500000f, +(float16_t)-0.5917968750000f,(float16_t)0.8061523437500f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.5996093750000f,(float16_t)0.8002929687500f, +(float16_t)-0.6030273437500f,(float16_t)0.7978515625000f, +(float16_t)-0.6069335937500f,(float16_t)0.7949218750000f, +(float16_t)-0.6103515625000f,(float16_t)0.7919921875000f, +(float16_t)-0.6142578125000f,(float16_t)0.7890625000000f, +(float16_t)-0.6176757812500f,(float16_t)0.7866210937500f, +(float16_t)-0.6210937500000f,(float16_t)0.7836914062500f, +(float16_t)-0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)-0.6284179687500f,(float16_t)0.7778320312500f, +(float16_t)-0.6318359375000f,(float16_t)0.7749023437500f, +(float16_t)-0.6357421875000f,(float16_t)0.7719726562500f, +(float16_t)-0.6391601562500f,(float16_t)0.7690429687500f, +(float16_t)-0.6425781250000f,(float16_t)0.7661132812500f, +(float16_t)-0.6459960937500f,(float16_t)0.7631835937500f, +(float16_t)-0.6499023437500f,(float16_t)0.7602539062500f, +(float16_t)-0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)-0.6567382812500f,(float16_t)0.7543945312500f, +(float16_t)-0.6601562500000f,(float16_t)0.7509765625000f, +(float16_t)-0.6635742187500f,(float16_t)0.7480468750000f, +(float16_t)-0.6669921875000f,(float16_t)0.7451171875000f, +(float16_t)-0.6704101562500f,(float16_t)0.7421875000000f, +(float16_t)-0.6738281250000f,(float16_t)0.7387695312500f, +(float16_t)-0.6772460937500f,(float16_t)0.7358398437500f, +(float16_t)-0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)-0.6840820312500f,(float16_t)0.7294921875000f, +(float16_t)-0.6875000000000f,(float16_t)0.7265625000000f, +(float16_t)-0.6904296875000f,(float16_t)0.7231445312500f, +(float16_t)-0.6938476562500f,(float16_t)0.7202148437500f, +(float16_t)-0.6972656250000f,(float16_t)0.7167968750000f, +(float16_t)-0.7006835937500f,(float16_t)0.7133789062500f, +(float16_t)-0.7036132812500f,(float16_t)0.7104492187500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7104492187500f,(float16_t)0.7036132812500f, +(float16_t)-0.7133789062500f,(float16_t)0.7006835937500f, +(float16_t)-0.7167968750000f,(float16_t)0.6972656250000f, +(float16_t)-0.7202148437500f,(float16_t)0.6938476562500f, +(float16_t)-0.7231445312500f,(float16_t)0.6904296875000f, +(float16_t)-0.7265625000000f,(float16_t)0.6875000000000f, +(float16_t)-0.7294921875000f,(float16_t)0.6840820312500f, +(float16_t)-0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)-0.7358398437500f,(float16_t)0.6772460937500f, +(float16_t)-0.7387695312500f,(float16_t)0.6738281250000f, +(float16_t)-0.7421875000000f,(float16_t)0.6704101562500f, +(float16_t)-0.7451171875000f,(float16_t)0.6669921875000f, +(float16_t)-0.7480468750000f,(float16_t)0.6635742187500f, +(float16_t)-0.7509765625000f,(float16_t)0.6601562500000f, +(float16_t)-0.7543945312500f,(float16_t)0.6567382812500f, +(float16_t)-0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)-0.7602539062500f,(float16_t)0.6499023437500f, +(float16_t)-0.7631835937500f,(float16_t)0.6459960937500f, +(float16_t)-0.7661132812500f,(float16_t)0.6425781250000f, +(float16_t)-0.7690429687500f,(float16_t)0.6391601562500f, +(float16_t)-0.7719726562500f,(float16_t)0.6357421875000f, +(float16_t)-0.7749023437500f,(float16_t)0.6318359375000f, +(float16_t)-0.7778320312500f,(float16_t)0.6284179687500f, +(float16_t)-0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)-0.7836914062500f,(float16_t)0.6210937500000f, +(float16_t)-0.7866210937500f,(float16_t)0.6176757812500f, +(float16_t)-0.7890625000000f,(float16_t)0.6142578125000f, +(float16_t)-0.7919921875000f,(float16_t)0.6103515625000f, +(float16_t)-0.7949218750000f,(float16_t)0.6069335937500f, +(float16_t)-0.7978515625000f,(float16_t)0.6030273437500f, +(float16_t)-0.8002929687500f,(float16_t)0.5996093750000f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8061523437500f,(float16_t)0.5917968750000f, +(float16_t)-0.8085937500000f,(float16_t)0.5883789062500f, +(float16_t)-0.8115234375000f,(float16_t)0.5844726562500f, +(float16_t)-0.8139648437500f,(float16_t)0.5810546875000f, +(float16_t)-0.8168945312500f,(float16_t)0.5771484375000f, +(float16_t)-0.8193359375000f,(float16_t)0.5732421875000f, +(float16_t)-0.8217773437500f,(float16_t)0.5693359375000f, +(float16_t)-0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)-0.8271484375000f,(float16_t)0.5620117187500f, +(float16_t)-0.8295898437500f,(float16_t)0.5581054687500f, +(float16_t)-0.8325195312500f,(float16_t)0.5541992187500f, +(float16_t)-0.8349609375000f,(float16_t)0.5502929687500f, +(float16_t)-0.8374023437500f,(float16_t)0.5463867187500f, +(float16_t)-0.8398437500000f,(float16_t)0.5429687500000f, +(float16_t)-0.8422851562500f,(float16_t)0.5390625000000f, +(float16_t)-0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)-0.8471679687500f,(float16_t)0.5312500000000f, +(float16_t)-0.8496093750000f,(float16_t)0.5273437500000f, +(float16_t)-0.8520507812500f,(float16_t)0.5234375000000f, +(float16_t)-0.8544921875000f,(float16_t)0.5195312500000f, +(float16_t)-0.8569335937500f,(float16_t)0.5156250000000f, +(float16_t)-0.8593750000000f,(float16_t)0.5112304687500f, +(float16_t)-0.8618164062500f,(float16_t)0.5073242187500f, +(float16_t)-0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)-0.8662109375000f,(float16_t)0.4995117187500f, +(float16_t)-0.8686523437500f,(float16_t)0.4956054687500f, +(float16_t)-0.8706054687500f,(float16_t)0.4914550781250f, +(float16_t)-0.8730468750000f,(float16_t)0.4875488281250f, +(float16_t)-0.8754882812500f,(float16_t)0.4836425781250f, +(float16_t)-0.8774414062500f,(float16_t)0.4794921875000f, +(float16_t)-0.8798828125000f,(float16_t)0.4753417968750f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.8842773437500f,(float16_t)0.4672851562500f, +(float16_t)-0.8862304687500f,(float16_t)0.4633789062500f, +(float16_t)-0.8881835937500f,(float16_t)0.4592285156250f, +(float16_t)-0.8906250000000f,(float16_t)0.4550781250000f, +(float16_t)-0.8925781250000f,(float16_t)0.4509277343750f, +(float16_t)-0.8945312500000f,(float16_t)0.4467773437500f, +(float16_t)-0.8964843750000f,(float16_t)0.4426269531250f, +(float16_t)-0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)-0.9008789062500f,(float16_t)0.4345703125000f, +(float16_t)-0.9028320312500f,(float16_t)0.4304199218750f, +(float16_t)-0.9047851562500f,(float16_t)0.4262695312500f, +(float16_t)-0.9067382812500f,(float16_t)0.4221191406250f, +(float16_t)-0.9086914062500f,(float16_t)0.4177246093750f, +(float16_t)-0.9106445312500f,(float16_t)0.4135742187500f, +(float16_t)-0.9121093750000f,(float16_t)0.4094238281250f, +(float16_t)-0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)-0.9160156250000f,(float16_t)0.4011230468750f, +(float16_t)-0.9179687500000f,(float16_t)0.3967285156250f, +(float16_t)-0.9199218750000f,(float16_t)0.3925781250000f, +(float16_t)-0.9213867187500f,(float16_t)0.3884277343750f, +(float16_t)-0.9233398437500f,(float16_t)0.3840332031250f, +(float16_t)-0.9252929687500f,(float16_t)0.3798828125000f, +(float16_t)-0.9267578125000f,(float16_t)0.3754882812500f, +(float16_t)-0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)-0.9301757812500f,(float16_t)0.3669433593750f, +(float16_t)-0.9316406250000f,(float16_t)0.3627929687500f, +(float16_t)-0.9335937500000f,(float16_t)0.3583984375000f, +(float16_t)-0.9350585937500f,(float16_t)0.3542480468750f, +(float16_t)-0.9370117187500f,(float16_t)0.3498535156250f, +(float16_t)-0.9384765625000f,(float16_t)0.3454589843750f, +(float16_t)-0.9399414062500f,(float16_t)0.3413085937500f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9428710937500f,(float16_t)0.3325195312500f, +(float16_t)-0.9448242187500f,(float16_t)0.3281250000000f, +(float16_t)-0.9462890625000f,(float16_t)0.3239746093750f, +(float16_t)-0.9477539062500f,(float16_t)0.3195800781250f, +(float16_t)-0.9492187500000f,(float16_t)0.3151855468750f, +(float16_t)-0.9506835937500f,(float16_t)0.3107910156250f, +(float16_t)-0.9521484375000f,(float16_t)0.3063964843750f, +(float16_t)-0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)-0.9545898437500f,(float16_t)0.2976074218750f, +(float16_t)-0.9560546875000f,(float16_t)0.2932128906250f, +(float16_t)-0.9575195312500f,(float16_t)0.2888183593750f, +(float16_t)-0.9584960937500f,(float16_t)0.2844238281250f, +(float16_t)-0.9599609375000f,(float16_t)0.2800292968750f, +(float16_t)-0.9614257812500f,(float16_t)0.2756347656250f, +(float16_t)-0.9624023437500f,(float16_t)0.2712402343750f, +(float16_t)-0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)-0.9648437500000f,(float16_t)0.2622070312500f, +(float16_t)-0.9663085937500f,(float16_t)0.2578125000000f, +(float16_t)-0.9672851562500f,(float16_t)0.2534179687500f, +(float16_t)-0.9687500000000f,(float16_t)0.2489013671875f, +(float16_t)-0.9697265625000f,(float16_t)0.2445068359375f, +(float16_t)-0.9707031250000f,(float16_t)0.2399902343750f, +(float16_t)-0.9716796875000f,(float16_t)0.2354736328125f, +(float16_t)-0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)-0.9741210937500f,(float16_t)0.2265625000000f, +(float16_t)-0.9750976562500f,(float16_t)0.2220458984375f, +(float16_t)-0.9760742187500f,(float16_t)0.2176513671875f, +(float16_t)-0.9770507812500f,(float16_t)0.2131347656250f, +(float16_t)-0.9780273437500f,(float16_t)0.2086181640625f, +(float16_t)-0.9790039062500f,(float16_t)0.2041015625000f, +(float16_t)-0.9799804687500f,(float16_t)0.1995849609375f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9814453125000f,(float16_t)0.1905517578125f, +(float16_t)-0.9824218750000f,(float16_t)0.1860351562500f, +(float16_t)-0.9833984375000f,(float16_t)0.1815185546875f, +(float16_t)-0.9843750000000f,(float16_t)0.1770019531250f, +(float16_t)-0.9848632812500f,(float16_t)0.1724853515625f, +(float16_t)-0.9858398437500f,(float16_t)0.1679687500000f, +(float16_t)-0.9863281250000f,(float16_t)0.1634521484375f, +(float16_t)-0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)-0.9877929687500f,(float16_t)0.1542968750000f, +(float16_t)-0.9887695312500f,(float16_t)0.1497802734375f, +(float16_t)-0.9892578125000f,(float16_t)0.1452636718750f, +(float16_t)-0.9902343750000f,(float16_t)0.1406250000000f, +(float16_t)-0.9907226562500f,(float16_t)0.1361083984375f, +(float16_t)-0.9912109375000f,(float16_t)0.1315917968750f, +(float16_t)-0.9916992187500f,(float16_t)0.1269531250000f, +(float16_t)-0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)-0.9931640625000f,(float16_t)0.1178588867188f, +(float16_t)-0.9936523437500f,(float16_t)0.1132812500000f, +(float16_t)-0.9941406250000f,(float16_t)0.1087036132812f, +(float16_t)-0.9946289062500f,(float16_t)0.1041259765625f, +(float16_t)-0.9951171875000f,(float16_t)0.0995483398438f, +(float16_t)-0.9956054687500f,(float16_t)0.0949707031250f, +(float16_t)-0.9960937500000f,(float16_t)0.0903930664062f, +(float16_t)-0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)-0.9965820312500f,(float16_t)0.0812377929688f, +(float16_t)-0.9970703125000f,(float16_t)0.0765991210938f, +(float16_t)-0.9975585937500f,(float16_t)0.0720214843750f, +(float16_t)-0.9975585937500f,(float16_t)0.0674438476562f, +(float16_t)-0.9980468750000f,(float16_t)0.0628662109375f, +(float16_t)-0.9985351562500f,(float16_t)0.0582580566406f, +(float16_t)-0.9985351562500f,(float16_t)0.0536499023438f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)-0.9990234375000f,(float16_t)0.0444641113281f, +(float16_t)-0.9990234375000f,(float16_t)0.0398864746094f, +(float16_t)-0.9995117187500f,(float16_t)0.0352783203125f, +(float16_t)-0.9995117187500f,(float16_t)0.0306701660156f, +(float16_t)-0.9995117187500f,(float16_t)0.0260772705078f, +(float16_t)-1.0000000000000f,(float16_t)0.0214691162109f, +(float16_t)-1.0000000000000f,(float16_t)0.0168762207031f, +(float16_t)-1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)-1.0000000000000f,(float16_t)0.0076713562012f, +(float16_t)-1.0000000000000f,(float16_t)0.0030670166016f, +(float16_t)-1.0000000000000f,(float16_t)-0.0015335083008f, +(float16_t)-1.0000000000000f,(float16_t)-0.0061340332031f, +(float16_t)-1.0000000000000f,(float16_t)-0.0107345581055f, +(float16_t)-1.0000000000000f,(float16_t)-0.0153427124023f, +(float16_t)-1.0000000000000f,(float16_t)-0.0199432373047f, +(float16_t)-0.9995117187500f,(float16_t)-0.0245361328125f, +(float16_t)-0.9995117187500f,(float16_t)-0.0291442871094f, +(float16_t)-0.9995117187500f,(float16_t)-0.0337524414062f, +(float16_t)-0.9990234375000f,(float16_t)-0.0383300781250f, +(float16_t)-0.9990234375000f,(float16_t)-0.0429382324219f, +(float16_t)-0.9990234375000f,(float16_t)-0.0475463867188f, +(float16_t)-0.9985351562500f,(float16_t)-0.0521240234375f, +(float16_t)-0.9985351562500f,(float16_t)-0.0567321777344f, +(float16_t)-0.9980468750000f,(float16_t)-0.0613098144531f, +(float16_t)-0.9980468750000f,(float16_t)-0.0659179687500f, +(float16_t)-0.9975585937500f,(float16_t)-0.0704956054688f, +(float16_t)-0.9970703125000f,(float16_t)-0.0750732421875f, +(float16_t)-0.9965820312500f,(float16_t)-0.0797119140625f, +(float16_t)-0.9965820312500f,(float16_t)-0.0842895507812f, +(float16_t)-0.9960937500000f,(float16_t)-0.0888671875000f, +(float16_t)-0.9956054687500f,(float16_t)-0.0934448242188f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9946289062500f,(float16_t)-0.1026000976562f, +(float16_t)-0.9941406250000f,(float16_t)-0.1071777343750f, +(float16_t)-0.9936523437500f,(float16_t)-0.1117553710938f, +(float16_t)-0.9931640625000f,(float16_t)-0.1163330078125f, +(float16_t)-0.9926757812500f,(float16_t)-0.1209106445312f, +(float16_t)-0.9921875000000f,(float16_t)-0.1254882812500f, +(float16_t)-0.9916992187500f,(float16_t)-0.1300048828125f, +(float16_t)-0.9907226562500f,(float16_t)-0.1345214843750f, +(float16_t)-0.9902343750000f,(float16_t)-0.1391601562500f, +(float16_t)-0.9897460937500f,(float16_t)-0.1436767578125f, +(float16_t)-0.9887695312500f,(float16_t)-0.1481933593750f, +(float16_t)-0.9882812500000f,(float16_t)-0.1528320312500f, +(float16_t)-0.9873046875000f,(float16_t)-0.1573486328125f, +(float16_t)-0.9868164062500f,(float16_t)-0.1618652343750f, +(float16_t)-0.9858398437500f,(float16_t)-0.1663818359375f, +(float16_t)-0.9853515625000f,(float16_t)-0.1710205078125f, +(float16_t)-0.9843750000000f,(float16_t)-0.1755371093750f, +(float16_t)-0.9838867187500f,(float16_t)-0.1800537109375f, +(float16_t)-0.9829101562500f,(float16_t)-0.1845703125000f, +(float16_t)-0.9819335937500f,(float16_t)-0.1890869140625f, +(float16_t)-0.9809570312500f,(float16_t)-0.1936035156250f, +(float16_t)-0.9799804687500f,(float16_t)-0.1981201171875f, +(float16_t)-0.9794921875000f,(float16_t)-0.2026367187500f, +(float16_t)-0.9785156250000f,(float16_t)-0.2071533203125f, +(float16_t)-0.9775390625000f,(float16_t)-0.2116699218750f, +(float16_t)-0.9765625000000f,(float16_t)-0.2160644531250f, +(float16_t)-0.9755859375000f,(float16_t)-0.2205810546875f, +(float16_t)-0.9741210937500f,(float16_t)-0.2250976562500f, +(float16_t)-0.9731445312500f,(float16_t)-0.2296142578125f, +(float16_t)-0.9721679687500f,(float16_t)-0.2340087890625f, +(float16_t)-0.9711914062500f,(float16_t)-0.2385253906250f, +(float16_t)-0.9702148437500f,(float16_t)-0.2429199218750f, +(float16_t)-0.9687500000000f,(float16_t)-0.2474365234375f, +(float16_t)-0.9677734375000f,(float16_t)-0.2519531250000f, +(float16_t)-0.9667968750000f,(float16_t)-0.2563476562500f, +(float16_t)-0.9653320312500f,(float16_t)-0.2607421875000f, +(float16_t)-0.9643554687500f,(float16_t)-0.2651367187500f, +(float16_t)-0.9628906250000f,(float16_t)-0.2697753906250f, +(float16_t)-0.9619140625000f,(float16_t)-0.2741699218750f, +(float16_t)-0.9604492187500f,(float16_t)-0.2785644531250f, +(float16_t)-0.9589843750000f,(float16_t)-0.2829589843750f, +(float16_t)-0.9580078125000f,(float16_t)-0.2873535156250f, +(float16_t)-0.9565429687500f,(float16_t)-0.2917480468750f, +(float16_t)-0.9550781250000f,(float16_t)-0.2961425781250f, +(float16_t)-0.9536132812500f,(float16_t)-0.3005371093750f, +(float16_t)-0.9521484375000f,(float16_t)-0.3049316406250f, +(float16_t)-0.9511718750000f,(float16_t)-0.3093261718750f, +(float16_t)-0.9497070312500f,(float16_t)-0.3137207031250f, +(float16_t)-0.9482421875000f,(float16_t)-0.3181152343750f, +(float16_t)-0.9467773437500f,(float16_t)-0.3225097656250f, +(float16_t)-0.9453125000000f,(float16_t)-0.3266601562500f, +(float16_t)-0.9433593750000f,(float16_t)-0.3310546875000f, +(float16_t)-0.9418945312500f,(float16_t)-0.3354492187500f, +(float16_t)-0.9404296875000f,(float16_t)-0.3398437500000f, +(float16_t)-0.9389648437500f,(float16_t)-0.3439941406250f, +(float16_t)-0.9375000000000f,(float16_t)-0.3483886718750f, +(float16_t)-0.9355468750000f,(float16_t)-0.3527832031250f, +(float16_t)-0.9340820312500f,(float16_t)-0.3569335937500f, +(float16_t)-0.9326171875000f,(float16_t)-0.3613281250000f, +(float16_t)-0.9306640625000f,(float16_t)-0.3657226562500f, +(float16_t)-0.9291992187500f,(float16_t)-0.3698730468750f, +(float16_t)-0.9272460937500f,(float16_t)-0.3742675781250f, +(float16_t)-0.9257812500000f,(float16_t)-0.3784179687500f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.9218750000000f,(float16_t)-0.3869628906250f, +(float16_t)-0.9204101562500f,(float16_t)-0.3911132812500f, +(float16_t)-0.9184570312500f,(float16_t)-0.3955078125000f, +(float16_t)-0.9165039062500f,(float16_t)-0.3996582031250f, +(float16_t)-0.9150390625000f,(float16_t)-0.4038085937500f, +(float16_t)-0.9130859375000f,(float16_t)-0.4079589843750f, +(float16_t)-0.9111328125000f,(float16_t)-0.4123535156250f, +(float16_t)-0.9091796875000f,(float16_t)-0.4165039062500f, +(float16_t)-0.9072265625000f,(float16_t)-0.4206542968750f, +(float16_t)-0.9052734375000f,(float16_t)-0.4248046875000f, +(float16_t)-0.9033203125000f,(float16_t)-0.4289550781250f, +(float16_t)-0.9013671875000f,(float16_t)-0.4331054687500f, +(float16_t)-0.8994140625000f,(float16_t)-0.4372558593750f, +(float16_t)-0.8974609375000f,(float16_t)-0.4414062500000f, +(float16_t)-0.8955078125000f,(float16_t)-0.4455566406250f, +(float16_t)-0.8930664062500f,(float16_t)-0.4497070312500f, +(float16_t)-0.8911132812500f,(float16_t)-0.4536132812500f, +(float16_t)-0.8891601562500f,(float16_t)-0.4577636718750f, +(float16_t)-0.8867187500000f,(float16_t)-0.4619140625000f, +(float16_t)-0.8847656250000f,(float16_t)-0.4660644531250f, +(float16_t)-0.8828125000000f,(float16_t)-0.4699707031250f, +(float16_t)-0.8803710937500f,(float16_t)-0.4741210937500f, +(float16_t)-0.8784179687500f,(float16_t)-0.4780273437500f, +(float16_t)-0.8759765625000f,(float16_t)-0.4821777343750f, +(float16_t)-0.8740234375000f,(float16_t)-0.4863281250000f, +(float16_t)-0.8715820312500f,(float16_t)-0.4902343750000f, +(float16_t)-0.8691406250000f,(float16_t)-0.4941406250000f, +(float16_t)-0.8671875000000f,(float16_t)-0.4982910156250f, +(float16_t)-0.8647460937500f,(float16_t)-0.5024414062500f, +(float16_t)-0.8623046875000f,(float16_t)-0.5063476562500f, +(float16_t)-0.8598632812500f,(float16_t)-0.5102539062500f, +(float16_t)-0.8579101562500f,(float16_t)-0.5141601562500f, +(float16_t)-0.8554687500000f,(float16_t)-0.5180664062500f, +(float16_t)-0.8530273437500f,(float16_t)-0.5219726562500f, +(float16_t)-0.8505859375000f,(float16_t)-0.5258789062500f, +(float16_t)-0.8481445312500f,(float16_t)-0.5297851562500f, +(float16_t)-0.8457031250000f,(float16_t)-0.5336914062500f, +(float16_t)-0.8432617187500f,(float16_t)-0.5375976562500f, +(float16_t)-0.8408203125000f,(float16_t)-0.5415039062500f, +(float16_t)-0.8383789062500f,(float16_t)-0.5454101562500f, +(float16_t)-0.8359375000000f,(float16_t)-0.5493164062500f, +(float16_t)-0.8330078125000f,(float16_t)-0.5532226562500f, +(float16_t)-0.8305664062500f,(float16_t)-0.5566406250000f, +(float16_t)-0.8281250000000f,(float16_t)-0.5605468750000f, +(float16_t)-0.8256835937500f,(float16_t)-0.5644531250000f, +(float16_t)-0.8227539062500f,(float16_t)-0.5683593750000f, +(float16_t)-0.8203125000000f,(float16_t)-0.5722656250000f, +(float16_t)-0.8173828125000f,(float16_t)-0.5756835937500f, +(float16_t)-0.8149414062500f,(float16_t)-0.5795898437500f, +(float16_t)-0.8120117187500f,(float16_t)-0.5834960937500f, +(float16_t)-0.8095703125000f,(float16_t)-0.5869140625000f, +(float16_t)-0.8066406250000f,(float16_t)-0.5908203125000f, +(float16_t)-0.8041992187500f,(float16_t)-0.5942382812500f, +(float16_t)-0.8012695312500f,(float16_t)-0.5981445312500f, +(float16_t)-0.7988281250000f,(float16_t)-0.6020507812500f, +(float16_t)-0.7958984375000f,(float16_t)-0.6054687500000f, +(float16_t)-0.7929687500000f,(float16_t)-0.6093750000000f, +(float16_t)-0.7900390625000f,(float16_t)-0.6127929687500f, +(float16_t)-0.7875976562500f,(float16_t)-0.6162109375000f, +(float16_t)-0.7846679687500f,(float16_t)-0.6201171875000f, +(float16_t)-0.7817382812500f,(float16_t)-0.6235351562500f, +(float16_t)-0.7788085937500f,(float16_t)-0.6274414062500f, +(float16_t)-0.7758789062500f,(float16_t)-0.6308593750000f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.7700195312500f,(float16_t)-0.6381835937500f, +(float16_t)-0.7670898437500f,(float16_t)-0.6416015625000f, +(float16_t)-0.7641601562500f,(float16_t)-0.6450195312500f, +(float16_t)-0.7612304687500f,(float16_t)-0.6484375000000f, +(float16_t)-0.7583007812500f,(float16_t)-0.6518554687500f, +(float16_t)-0.7553710937500f,(float16_t)-0.6552734375000f, +(float16_t)-0.7519531250000f,(float16_t)-0.6591796875000f, +(float16_t)-0.7490234375000f,(float16_t)-0.6625976562500f, +(float16_t)-0.7460937500000f,(float16_t)-0.6660156250000f, +(float16_t)-0.7431640625000f,(float16_t)-0.6694335937500f, +(float16_t)-0.7397460937500f,(float16_t)-0.6728515625000f, +(float16_t)-0.7368164062500f,(float16_t)-0.6762695312500f, +(float16_t)-0.7338867187500f,(float16_t)-0.6796875000000f, +(float16_t)-0.7304687500000f,(float16_t)-0.6826171875000f, +(float16_t)-0.7275390625000f,(float16_t)-0.6860351562500f, +(float16_t)-0.7241210937500f,(float16_t)-0.6894531250000f, +(float16_t)-0.7211914062500f,(float16_t)-0.6928710937500f, +(float16_t)-0.7177734375000f,(float16_t)-0.6962890625000f, +(float16_t)-0.7148437500000f,(float16_t)-0.6997070312500f, +(float16_t)-0.7114257812500f,(float16_t)-0.7026367187500f, +(float16_t)-0.7080078125000f,(float16_t)-0.7060546875000f, +(float16_t)-0.7050781250000f,(float16_t)-0.7094726562500f, +(float16_t)-0.7016601562500f,(float16_t)-0.7124023437500f, +(float16_t)-0.6982421875000f,(float16_t)-0.7158203125000f, +(float16_t)-0.6953125000000f,(float16_t)-0.7187500000000f, +(float16_t)-0.6918945312500f,(float16_t)-0.7221679687500f, +(float16_t)-0.6884765625000f,(float16_t)-0.7250976562500f, +(float16_t)-0.6850585937500f,(float16_t)-0.7285156250000f, +(float16_t)-0.6816406250000f,(float16_t)-0.7314453125000f, +(float16_t)-0.6782226562500f,(float16_t)-0.7348632812500f, +(float16_t)-0.6748046875000f,(float16_t)-0.7377929687500f, +(float16_t)-0.6713867187500f,(float16_t)-0.7407226562500f, +(float16_t)-0.6679687500000f,(float16_t)-0.7441406250000f, +(float16_t)-0.6645507812500f,(float16_t)-0.7470703125000f, +(float16_t)-0.6611328125000f,(float16_t)-0.7500000000000f, +(float16_t)-0.6577148437500f,(float16_t)-0.7534179687500f, +(float16_t)-0.6542968750000f,(float16_t)-0.7563476562500f, +(float16_t)-0.6508789062500f,(float16_t)-0.7592773437500f, +(float16_t)-0.6474609375000f,(float16_t)-0.7622070312500f, +(float16_t)-0.6440429687500f,(float16_t)-0.7651367187500f, +(float16_t)-0.6401367187500f,(float16_t)-0.7680664062500f, +(float16_t)-0.6367187500000f,(float16_t)-0.7709960937500f, +(float16_t)-0.6333007812500f,(float16_t)-0.7739257812500f, +(float16_t)-0.6293945312500f,(float16_t)-0.7768554687500f, +(float16_t)-0.6259765625000f,(float16_t)-0.7797851562500f, +(float16_t)-0.6225585937500f,(float16_t)-0.7827148437500f, +(float16_t)-0.6186523437500f,(float16_t)-0.7856445312500f, +(float16_t)-0.6152343750000f,(float16_t)-0.7885742187500f, +(float16_t)-0.6118164062500f,(float16_t)-0.7910156250000f, +(float16_t)-0.6079101562500f,(float16_t)-0.7939453125000f, +(float16_t)-0.6044921875000f,(float16_t)-0.7968750000000f, +(float16_t)-0.6005859375000f,(float16_t)-0.7993164062500f, +(float16_t)-0.5971679687500f,(float16_t)-0.8022460937500f, +(float16_t)-0.5932617187500f,(float16_t)-0.8051757812500f, +(float16_t)-0.5893554687500f,(float16_t)-0.8076171875000f, +(float16_t)-0.5859375000000f,(float16_t)-0.8105468750000f, +(float16_t)-0.5820312500000f,(float16_t)-0.8129882812500f, +(float16_t)-0.5781250000000f,(float16_t)-0.8159179687500f, +(float16_t)-0.5747070312500f,(float16_t)-0.8183593750000f, +(float16_t)-0.5708007812500f,(float16_t)-0.8212890625000f, +(float16_t)-0.5668945312500f,(float16_t)-0.8237304687500f, +(float16_t)-0.5629882812500f,(float16_t)-0.8261718750000f, +(float16_t)-0.5595703125000f,(float16_t)-0.8291015625000f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.5517578125000f,(float16_t)-0.8339843750000f, +(float16_t)-0.5478515625000f,(float16_t)-0.8364257812500f, +(float16_t)-0.5439453125000f,(float16_t)-0.8388671875000f, +(float16_t)-0.5400390625000f,(float16_t)-0.8417968750000f, +(float16_t)-0.5361328125000f,(float16_t)-0.8442382812500f, +(float16_t)-0.5322265625000f,(float16_t)-0.8466796875000f, +(float16_t)-0.5283203125000f,(float16_t)-0.8491210937500f, +(float16_t)-0.5244140625000f,(float16_t)-0.8515625000000f, +(float16_t)-0.5205078125000f,(float16_t)-0.8540039062500f, +(float16_t)-0.5166015625000f,(float16_t)-0.8559570312500f, +(float16_t)-0.5126953125000f,(float16_t)-0.8583984375000f, +(float16_t)-0.5087890625000f,(float16_t)-0.8608398437500f, +(float16_t)-0.5048828125000f,(float16_t)-0.8632812500000f, +(float16_t)-0.5009765625000f,(float16_t)-0.8657226562500f, +(float16_t)-0.4968261718750f,(float16_t)-0.8676757812500f, +(float16_t)-0.4929199218750f,(float16_t)-0.8701171875000f, +(float16_t)-0.4887695312500f,(float16_t)-0.8725585937500f, +(float16_t)-0.4848632812500f,(float16_t)-0.8745117187500f, +(float16_t)-0.4809570312500f,(float16_t)-0.8769531250000f, +(float16_t)-0.4768066406250f,(float16_t)-0.8789062500000f, +(float16_t)-0.4726562500000f,(float16_t)-0.8813476562500f, +(float16_t)-0.4687500000000f,(float16_t)-0.8833007812500f, +(float16_t)-0.4645996093750f,(float16_t)-0.8857421875000f, +(float16_t)-0.4604492187500f,(float16_t)-0.8876953125000f, +(float16_t)-0.4565429687500f,(float16_t)-0.8896484375000f, +(float16_t)-0.4523925781250f,(float16_t)-0.8916015625000f, +(float16_t)-0.4482421875000f,(float16_t)-0.8940429687500f, +(float16_t)-0.4440917968750f,(float16_t)-0.8959960937500f, +(float16_t)-0.4399414062500f,(float16_t)-0.8979492187500f, +(float16_t)-0.4357910156250f,(float16_t)-0.8999023437500f, +(float16_t)-0.4316406250000f,(float16_t)-0.9018554687500f, +(float16_t)-0.4274902343750f,(float16_t)-0.9038085937500f, +(float16_t)-0.4233398437500f,(float16_t)-0.9057617187500f, +(float16_t)-0.4191894531250f,(float16_t)-0.9077148437500f, +(float16_t)-0.4150390625000f,(float16_t)-0.9096679687500f, +(float16_t)-0.4108886718750f,(float16_t)-0.9116210937500f, +(float16_t)-0.4067382812500f,(float16_t)-0.9135742187500f, +(float16_t)-0.4023437500000f,(float16_t)-0.9155273437500f, +(float16_t)-0.3981933593750f,(float16_t)-0.9174804687500f, +(float16_t)-0.3940429687500f,(float16_t)-0.9189453125000f, +(float16_t)-0.3896484375000f,(float16_t)-0.9208984375000f, +(float16_t)-0.3854980468750f,(float16_t)-0.9228515625000f, +(float16_t)-0.3813476562500f,(float16_t)-0.9243164062500f, +(float16_t)-0.3769531250000f,(float16_t)-0.9262695312500f, +(float16_t)-0.3728027343750f,(float16_t)-0.9277343750000f, +(float16_t)-0.3684082031250f,(float16_t)-0.9296875000000f, +(float16_t)-0.3642578125000f,(float16_t)-0.9311523437500f, +(float16_t)-0.3598632812500f,(float16_t)-0.9331054687500f, +(float16_t)-0.3557128906250f,(float16_t)-0.9345703125000f, +(float16_t)-0.3513183593750f,(float16_t)-0.9360351562500f, +(float16_t)-0.3469238281250f,(float16_t)-0.9379882812500f, +(float16_t)-0.3427734375000f,(float16_t)-0.9394531250000f, +(float16_t)-0.3383789062500f,(float16_t)-0.9409179687500f, +(float16_t)-0.3339843750000f,(float16_t)-0.9423828125000f, +(float16_t)-0.3295898437500f,(float16_t)-0.9443359375000f, +(float16_t)-0.3251953125000f,(float16_t)-0.9458007812500f, +(float16_t)-0.3210449218750f,(float16_t)-0.9472656250000f, +(float16_t)-0.3166503906250f,(float16_t)-0.9487304687500f, +(float16_t)-0.3122558593750f,(float16_t)-0.9501953125000f, +(float16_t)-0.3078613281250f,(float16_t)-0.9516601562500f, +(float16_t)-0.3034667968750f,(float16_t)-0.9526367187500f, +(float16_t)-0.2990722656250f,(float16_t)-0.9541015625000f, +(float16_t)-0.2946777343750f,(float16_t)-0.9555664062500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)-0.2858886718750f,(float16_t)-0.9584960937500f, +(float16_t)-0.2814941406250f,(float16_t)-0.9594726562500f, +(float16_t)-0.2770996093750f,(float16_t)-0.9609375000000f, +(float16_t)-0.2727050781250f,(float16_t)-0.9619140625000f, +(float16_t)-0.2683105468750f,(float16_t)-0.9633789062500f, +(float16_t)-0.2636718750000f,(float16_t)-0.9643554687500f, +(float16_t)-0.2592773437500f,(float16_t)-0.9658203125000f, +(float16_t)-0.2548828125000f,(float16_t)-0.9667968750000f, +(float16_t)-0.2504882812500f,(float16_t)-0.9682617187500f, +(float16_t)-0.2459716796875f,(float16_t)-0.9692382812500f, +(float16_t)-0.2414550781250f,(float16_t)-0.9702148437500f, +(float16_t)-0.2370605468750f,(float16_t)-0.9716796875000f, +(float16_t)-0.2325439453125f,(float16_t)-0.9726562500000f, +(float16_t)-0.2280273437500f,(float16_t)-0.9736328125000f, +(float16_t)-0.2236328125000f,(float16_t)-0.9746093750000f, +(float16_t)-0.2191162109375f,(float16_t)-0.9755859375000f, +(float16_t)-0.2145996093750f,(float16_t)-0.9765625000000f, +(float16_t)-0.2100830078125f,(float16_t)-0.9775390625000f, +(float16_t)-0.2055664062500f,(float16_t)-0.9785156250000f, +(float16_t)-0.2010498046875f,(float16_t)-0.9794921875000f, +(float16_t)-0.1966552734375f,(float16_t)-0.9804687500000f, +(float16_t)-0.1921386718750f,(float16_t)-0.9814453125000f, +(float16_t)-0.1876220703125f,(float16_t)-0.9824218750000f, +(float16_t)-0.1829833984375f,(float16_t)-0.9829101562500f, +(float16_t)-0.1784667968750f,(float16_t)-0.9838867187500f, +(float16_t)-0.1739501953125f,(float16_t)-0.9848632812500f, +(float16_t)-0.1694335937500f,(float16_t)-0.9853515625000f, +(float16_t)-0.1649169921875f,(float16_t)-0.9863281250000f, +(float16_t)-0.1604003906250f,(float16_t)-0.9868164062500f, +(float16_t)-0.1558837890625f,(float16_t)-0.9877929687500f, +(float16_t)-0.1512451171875f,(float16_t)-0.9882812500000f, +(float16_t)-0.1467285156250f,(float16_t)-0.9892578125000f, +(float16_t)-0.1422119140625f,(float16_t)-0.9897460937500f, +(float16_t)-0.1375732421875f,(float16_t)-0.9907226562500f, +(float16_t)-0.1330566406250f,(float16_t)-0.9912109375000f, +(float16_t)-0.1285400390625f,(float16_t)-0.9916992187500f, +(float16_t)-0.1239624023438f,(float16_t)-0.9921875000000f, +(float16_t)-0.1193847656250f,(float16_t)-0.9926757812500f, +(float16_t)-0.1148071289062f,(float16_t)-0.9931640625000f, +(float16_t)-0.1102294921875f,(float16_t)-0.9941406250000f, +(float16_t)-0.1056518554688f,(float16_t)-0.9946289062500f, +(float16_t)-0.1010742187500f,(float16_t)-0.9951171875000f, +(float16_t)-0.0964965820312f,(float16_t)-0.9951171875000f, +(float16_t)-0.0919189453125f,(float16_t)-0.9956054687500f, +(float16_t)-0.0873413085938f,(float16_t)-0.9960937500000f, +(float16_t)-0.0827636718750f,(float16_t)-0.9965820312500f, +(float16_t)-0.0781250000000f,(float16_t)-0.9970703125000f, +(float16_t)-0.0735473632812f,(float16_t)-0.9970703125000f, +(float16_t)-0.0689697265625f,(float16_t)-0.9975585937500f, +(float16_t)-0.0643920898438f,(float16_t)-0.9980468750000f, +(float16_t)-0.0597839355469f,(float16_t)-0.9980468750000f, +(float16_t)-0.0552062988281f,(float16_t)-0.9985351562500f, +(float16_t)-0.0505981445312f,(float16_t)-0.9985351562500f, +(float16_t)-0.0459899902344f,(float16_t)-0.9990234375000f, +(float16_t)-0.0414123535156f,(float16_t)-0.9990234375000f, +(float16_t)-0.0368041992188f,(float16_t)-0.9995117187500f, +(float16_t)-0.0321960449219f,(float16_t)-0.9995117187500f, +(float16_t)-0.0276031494141f,(float16_t)-0.9995117187500f, +(float16_t)-0.0230102539062f,(float16_t)-0.9995117187500f, +(float16_t)-0.0184020996094f,(float16_t)-1.0000000000000f, +(float16_t)-0.0138015747070f,(float16_t)-1.0000000000000f, +(float16_t)-0.0092010498047f,(float16_t)-1.0000000000000f, +(float16_t)-0.0046005249023f,(float16_t)-1.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0184020996094f, +(float16_t)0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)0.9985351562500f,(float16_t)0.0552062988281f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9956054687500f,(float16_t)0.0919189453125f, +(float16_t)0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)0.9916992187500f,(float16_t)0.1285400390625f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9863281250000f,(float16_t)0.1649169921875f, +(float16_t)0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)0.9794921875000f,(float16_t)0.2010498046875f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9716796875000f,(float16_t)0.2370605468750f, +(float16_t)0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)0.9619140625000f,(float16_t)0.2727050781250f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9516601562500f,(float16_t)0.3078613281250f, +(float16_t)0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)0.9394531250000f,(float16_t)0.3427734375000f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9262695312500f,(float16_t)0.3769531250000f, +(float16_t)0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)0.9116210937500f,(float16_t)0.4108886718750f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8959960937500f,(float16_t)0.4440917968750f, +(float16_t)0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)0.8789062500000f,(float16_t)0.4768066406250f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8608398437500f,(float16_t)0.5087890625000f, +(float16_t)0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)0.8417968750000f,(float16_t)0.5400390625000f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8212890625000f,(float16_t)0.5708007812500f, +(float16_t)0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)0.7993164062500f,(float16_t)0.6005859375000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7768554687500f,(float16_t)0.6293945312500f, +(float16_t)0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)0.7534179687500f,(float16_t)0.6577148437500f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7285156250000f,(float16_t)0.6850585937500f, +(float16_t)0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)0.7026367187500f,(float16_t)0.7114257812500f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6762695312500f,(float16_t)0.7368164062500f, +(float16_t)0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)0.6484375000000f,(float16_t)0.7612304687500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6201171875000f,(float16_t)0.7846679687500f, +(float16_t)0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)0.5908203125000f,(float16_t)0.8066406250000f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5605468750000f,(float16_t)0.8281250000000f, +(float16_t)0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)0.5297851562500f,(float16_t)0.8481445312500f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4982910156250f,(float16_t)0.8671875000000f, +(float16_t)0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)0.4660644531250f,(float16_t)0.8847656250000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4331054687500f,(float16_t)0.9013671875000f, +(float16_t)0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)0.3996582031250f,(float16_t)0.9165039062500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3657226562500f,(float16_t)0.9306640625000f, +(float16_t)0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)0.3310546875000f,(float16_t)0.9433593750000f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.2961425781250f,(float16_t)0.9550781250000f, +(float16_t)0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)0.2607421875000f,(float16_t)0.9653320312500f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2250976562500f,(float16_t)0.9741210937500f, +(float16_t)0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)0.1890869140625f,(float16_t)0.9819335937500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1528320312500f,(float16_t)0.9882812500000f, +(float16_t)0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)0.1163330078125f,(float16_t)0.9931640625000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0797119140625f,(float16_t)0.9965820312500f, +(float16_t)0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)0.0429382324219f,(float16_t)0.9990234375000f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)0.0061340332031f,(float16_t)1.0000000000000f, +(float16_t)-0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)-0.0306701660156f,(float16_t)0.9995117187500f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.0674438476562f,(float16_t)0.9975585937500f, +(float16_t)-0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)-0.1041259765625f,(float16_t)0.9946289062500f, +(float16_t)-0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)-0.1406250000000f,(float16_t)0.9902343750000f, +(float16_t)-0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)-0.1770019531250f,(float16_t)0.9843750000000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.2131347656250f,(float16_t)0.9770507812500f, +(float16_t)-0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)-0.2489013671875f,(float16_t)0.9687500000000f, +(float16_t)-0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)-0.2844238281250f,(float16_t)0.9584960937500f, +(float16_t)-0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)-0.3195800781250f,(float16_t)0.9477539062500f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.3542480468750f,(float16_t)0.9350585937500f, +(float16_t)-0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)-0.3884277343750f,(float16_t)0.9213867187500f, +(float16_t)-0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)-0.4221191406250f,(float16_t)0.9067382812500f, +(float16_t)-0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)-0.4550781250000f,(float16_t)0.8906250000000f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.4875488281250f,(float16_t)0.8730468750000f, +(float16_t)-0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)-0.5195312500000f,(float16_t)0.8544921875000f, +(float16_t)-0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)-0.5502929687500f,(float16_t)0.8349609375000f, +(float16_t)-0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)-0.5810546875000f,(float16_t)0.8139648437500f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.6103515625000f,(float16_t)0.7919921875000f, +(float16_t)-0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)-0.6391601562500f,(float16_t)0.7690429687500f, +(float16_t)-0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)-0.6669921875000f,(float16_t)0.7451171875000f, +(float16_t)-0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)-0.6938476562500f,(float16_t)0.7202148437500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7202148437500f,(float16_t)0.6938476562500f, +(float16_t)-0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)-0.7451171875000f,(float16_t)0.6669921875000f, +(float16_t)-0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)-0.7690429687500f,(float16_t)0.6391601562500f, +(float16_t)-0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)-0.7919921875000f,(float16_t)0.6103515625000f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8139648437500f,(float16_t)0.5810546875000f, +(float16_t)-0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)-0.8349609375000f,(float16_t)0.5502929687500f, +(float16_t)-0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)-0.8544921875000f,(float16_t)0.5195312500000f, +(float16_t)-0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)-0.8730468750000f,(float16_t)0.4875488281250f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.8906250000000f,(float16_t)0.4550781250000f, +(float16_t)-0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)-0.9067382812500f,(float16_t)0.4221191406250f, +(float16_t)-0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)-0.9213867187500f,(float16_t)0.3884277343750f, +(float16_t)-0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)-0.9350585937500f,(float16_t)0.3542480468750f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9477539062500f,(float16_t)0.3195800781250f, +(float16_t)-0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)-0.9584960937500f,(float16_t)0.2844238281250f, +(float16_t)-0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)-0.9687500000000f,(float16_t)0.2489013671875f, +(float16_t)-0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)-0.9770507812500f,(float16_t)0.2131347656250f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9843750000000f,(float16_t)0.1770019531250f, +(float16_t)-0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)-0.9902343750000f,(float16_t)0.1406250000000f, +(float16_t)-0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)-0.9946289062500f,(float16_t)0.1041259765625f, +(float16_t)-0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)-0.9975585937500f,(float16_t)0.0674438476562f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)-0.9995117187500f,(float16_t)0.0306701660156f, +(float16_t)-1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)-1.0000000000000f,(float16_t)-0.0061340332031f, +(float16_t)-0.9995117187500f,(float16_t)-0.0245361328125f, +(float16_t)-0.9990234375000f,(float16_t)-0.0429382324219f, +(float16_t)-0.9980468750000f,(float16_t)-0.0613098144531f, +(float16_t)-0.9965820312500f,(float16_t)-0.0797119140625f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9931640625000f,(float16_t)-0.1163330078125f, +(float16_t)-0.9907226562500f,(float16_t)-0.1345214843750f, +(float16_t)-0.9882812500000f,(float16_t)-0.1528320312500f, +(float16_t)-0.9853515625000f,(float16_t)-0.1710205078125f, +(float16_t)-0.9819335937500f,(float16_t)-0.1890869140625f, +(float16_t)-0.9785156250000f,(float16_t)-0.2071533203125f, +(float16_t)-0.9741210937500f,(float16_t)-0.2250976562500f, +(float16_t)-0.9702148437500f,(float16_t)-0.2429199218750f, +(float16_t)-0.9653320312500f,(float16_t)-0.2607421875000f, +(float16_t)-0.9604492187500f,(float16_t)-0.2785644531250f, +(float16_t)-0.9550781250000f,(float16_t)-0.2961425781250f, +(float16_t)-0.9497070312500f,(float16_t)-0.3137207031250f, +(float16_t)-0.9433593750000f,(float16_t)-0.3310546875000f, +(float16_t)-0.9375000000000f,(float16_t)-0.3483886718750f, +(float16_t)-0.9306640625000f,(float16_t)-0.3657226562500f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.9165039062500f,(float16_t)-0.3996582031250f, +(float16_t)-0.9091796875000f,(float16_t)-0.4165039062500f, +(float16_t)-0.9013671875000f,(float16_t)-0.4331054687500f, +(float16_t)-0.8930664062500f,(float16_t)-0.4497070312500f, +(float16_t)-0.8847656250000f,(float16_t)-0.4660644531250f, +(float16_t)-0.8759765625000f,(float16_t)-0.4821777343750f, +(float16_t)-0.8671875000000f,(float16_t)-0.4982910156250f, +(float16_t)-0.8579101562500f,(float16_t)-0.5141601562500f, +(float16_t)-0.8481445312500f,(float16_t)-0.5297851562500f, +(float16_t)-0.8383789062500f,(float16_t)-0.5454101562500f, +(float16_t)-0.8281250000000f,(float16_t)-0.5605468750000f, +(float16_t)-0.8173828125000f,(float16_t)-0.5756835937500f, +(float16_t)-0.8066406250000f,(float16_t)-0.5908203125000f, +(float16_t)-0.7958984375000f,(float16_t)-0.6054687500000f, +(float16_t)-0.7846679687500f,(float16_t)-0.6201171875000f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.7612304687500f,(float16_t)-0.6484375000000f, +(float16_t)-0.7490234375000f,(float16_t)-0.6625976562500f, +(float16_t)-0.7368164062500f,(float16_t)-0.6762695312500f, +(float16_t)-0.7241210937500f,(float16_t)-0.6894531250000f, +(float16_t)-0.7114257812500f,(float16_t)-0.7026367187500f, +(float16_t)-0.6982421875000f,(float16_t)-0.7158203125000f, +(float16_t)-0.6850585937500f,(float16_t)-0.7285156250000f, +(float16_t)-0.6713867187500f,(float16_t)-0.7407226562500f, +(float16_t)-0.6577148437500f,(float16_t)-0.7534179687500f, +(float16_t)-0.6440429687500f,(float16_t)-0.7651367187500f, +(float16_t)-0.6293945312500f,(float16_t)-0.7768554687500f, +(float16_t)-0.6152343750000f,(float16_t)-0.7885742187500f, +(float16_t)-0.6005859375000f,(float16_t)-0.7993164062500f, +(float16_t)-0.5859375000000f,(float16_t)-0.8105468750000f, +(float16_t)-0.5708007812500f,(float16_t)-0.8212890625000f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.5400390625000f,(float16_t)-0.8417968750000f, +(float16_t)-0.5244140625000f,(float16_t)-0.8515625000000f, +(float16_t)-0.5087890625000f,(float16_t)-0.8608398437500f, +(float16_t)-0.4929199218750f,(float16_t)-0.8701171875000f, +(float16_t)-0.4768066406250f,(float16_t)-0.8789062500000f, +(float16_t)-0.4604492187500f,(float16_t)-0.8876953125000f, +(float16_t)-0.4440917968750f,(float16_t)-0.8959960937500f, +(float16_t)-0.4274902343750f,(float16_t)-0.9038085937500f, +(float16_t)-0.4108886718750f,(float16_t)-0.9116210937500f, +(float16_t)-0.3940429687500f,(float16_t)-0.9189453125000f, +(float16_t)-0.3769531250000f,(float16_t)-0.9262695312500f, +(float16_t)-0.3598632812500f,(float16_t)-0.9331054687500f, +(float16_t)-0.3427734375000f,(float16_t)-0.9394531250000f, +(float16_t)-0.3251953125000f,(float16_t)-0.9458007812500f, +(float16_t)-0.3078613281250f,(float16_t)-0.9516601562500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)-0.2727050781250f,(float16_t)-0.9619140625000f, +(float16_t)-0.2548828125000f,(float16_t)-0.9667968750000f, +(float16_t)-0.2370605468750f,(float16_t)-0.9716796875000f, +(float16_t)-0.2191162109375f,(float16_t)-0.9755859375000f, +(float16_t)-0.2010498046875f,(float16_t)-0.9794921875000f, +(float16_t)-0.1829833984375f,(float16_t)-0.9829101562500f, +(float16_t)-0.1649169921875f,(float16_t)-0.9863281250000f, +(float16_t)-0.1467285156250f,(float16_t)-0.9892578125000f, +(float16_t)-0.1285400390625f,(float16_t)-0.9916992187500f, +(float16_t)-0.1102294921875f,(float16_t)-0.9941406250000f, +(float16_t)-0.0919189453125f,(float16_t)-0.9956054687500f, +(float16_t)-0.0735473632812f,(float16_t)-0.9970703125000f, +(float16_t)-0.0552062988281f,(float16_t)-0.9985351562500f, +(float16_t)-0.0368041992188f,(float16_t)-0.9995117187500f, +(float16_t)-0.0184020996094f,(float16_t)-1.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)-0.9995117187500f,(float16_t)-0.0245361328125f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9853515625000f,(float16_t)-0.1710205078125f, +(float16_t)-0.9702148437500f,(float16_t)-0.2429199218750f, +(float16_t)-0.9497070312500f,(float16_t)-0.3137207031250f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.8930664062500f,(float16_t)-0.4497070312500f, +(float16_t)-0.8579101562500f,(float16_t)-0.5141601562500f, +(float16_t)-0.8173828125000f,(float16_t)-0.5756835937500f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.7241210937500f,(float16_t)-0.6894531250000f, +(float16_t)-0.6713867187500f,(float16_t)-0.7407226562500f, +(float16_t)-0.6152343750000f,(float16_t)-0.7885742187500f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.4929199218750f,(float16_t)-0.8701171875000f, +(float16_t)-0.4274902343750f,(float16_t)-0.9038085937500f, +(float16_t)-0.3598632812500f,(float16_t)-0.9331054687500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)-0.2191162109375f,(float16_t)-0.9755859375000f, +(float16_t)-0.1467285156250f,(float16_t)-0.9892578125000f, +(float16_t)-0.0735473632812f,(float16_t)-0.9970703125000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f,}; + +#endif + + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ +#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#endif /* if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/CMakeLists.txt new file mode 100644 index 00000000..5251dd3c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/CMakeLists.txt @@ -0,0 +1,74 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPComplexMath) + +include(configLib) +include(configDsp) + +add_library(CMSISDSPComplexMath STATIC) + +configLib(CMSISDSPComplexMath ${ROOT}) +configDsp(CMSISDSPComplexMath ${ROOT}) + + +include(interpol) +interpol(CMSISDSPComplexMath) + + +if (CONFIGTABLE AND ALLFAST) + target_compile_definitions(CMSISDSPComplexMath PUBLIC ARM_ALL_FAST_TABLES) +endif() + +# Vectorized code is defining sqrt +# so fast tables required even if Fast Math not built. +if (CONFIGTABLE AND (HELIUM OR MVEF OR MVEI)) + target_compile_definitions(CMSISDSPComplexMath PUBLIC ARM_FAST_ALLOW_TABLES) +endif() + + +# MVE code is using a table for computing the fast sqrt arm_cmplx_mag_q31 +# There is the possibility of not compiling this function and not including +# the table. +if (NOT CONFIGTABLE OR ALLFAST OR ARM_CMPLX_MAG_Q31 OR (NOT HELIUM AND NOT MVEI)) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mag_q31.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_CMPLX_MAG_Q15 OR (NOT HELIUM AND NOT MVEI)) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mag_q15.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_CMPLX_MAG_FAST_Q15 OR (NOT HELIUM AND NOT MVEI)) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mag_fast_q15.c) +endif() + +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_conj_f32.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_conj_q15.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_conj_q31.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_dot_prod_f32.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_dot_prod_q15.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_dot_prod_q31.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mag_f32.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mag_f64.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mag_squared_f32.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mag_squared_f64.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mag_squared_q15.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mag_squared_q31.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mult_cmplx_f32.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mult_cmplx_f64.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mult_cmplx_q15.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mult_cmplx_q31.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mult_real_f32.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mult_real_q15.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mult_real_q31.c) + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_conj_f16.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_dot_prod_f16.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mag_f16.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mag_squared_f16.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mult_cmplx_f16.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mult_real_f16.c) +endif() + +### Includes +target_include_directories(CMSISDSPComplexMath PUBLIC "${DSP}/Include") diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c new file mode 100644 index 00000000..9b46bb35 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: CompexMathFunctions.c + * Description: Combination of all comlex math function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_cmplx_conj_f32.c" +#include "arm_cmplx_conj_q15.c" +#include "arm_cmplx_conj_q31.c" +#include "arm_cmplx_dot_prod_f32.c" +#include "arm_cmplx_dot_prod_q15.c" +#include "arm_cmplx_dot_prod_q31.c" +#include "arm_cmplx_mag_f32.c" +#include "arm_cmplx_mag_f64.c" + +#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) + #include "arm_cmplx_mag_q15.c" + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE) + #include "arm_cmplx_mag_fast_q15.c" + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) + #include "arm_cmplx_mag_q31.c" + #endif +#else + #include "arm_cmplx_mag_q15.c" + #include "arm_cmplx_mag_fast_q15.c" + #include "arm_cmplx_mag_q31.c" +#endif + +#include "arm_cmplx_mag_squared_f32.c" +#include "arm_cmplx_mag_squared_f64.c" +#include "arm_cmplx_mag_squared_q15.c" +#include "arm_cmplx_mag_squared_q31.c" +#include "arm_cmplx_mult_cmplx_f32.c" +#include "arm_cmplx_mult_cmplx_f64.c" +#include "arm_cmplx_mult_cmplx_q15.c" +#include "arm_cmplx_mult_cmplx_q31.c" +#include "arm_cmplx_mult_real_f32.c" +#include "arm_cmplx_mult_real_q15.c" +#include "arm_cmplx_mult_real_q31.c" diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c new file mode 100644 index 00000000..d2c77842 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c @@ -0,0 +1,32 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: CompexMathFunctionsF16.c + * Description: Combination of all complex math function f16 source files. + * + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_cmplx_conj_f16.c" +#include "arm_cmplx_dot_prod_f16.c" +#include "arm_cmplx_mag_f16.c" +#include "arm_cmplx_mag_squared_f16.c" +#include "arm_cmplx_mult_cmplx_f16.c" +#include "arm_cmplx_mult_real_f16.c" diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f16.c new file mode 100644 index 00000000..05d7b97c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f16.c @@ -0,0 +1,185 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_conj_f16.c + * Description: Floating-point complex conjugate + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_conj Complex Conjugate + + Conjugates the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the destination data where the result should be written. + numSamples specifies the number of complex samples + and the data in each array is stored in an interleaved fashion + (real, imag, real, imag, ...). + Each array has a total of 2*numSamples values. + + The underlying algorithm is used: +
+  for (n = 0; n < numSamples; n++) {
+      pDst[(2*n)  ] =  pSrc[(2*n)  ];    // real part
+      pDst[(2*n)+1] = -pSrc[(2*n)+1];    // imag part
+  }
+  
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_conj + @{ + */ + +/** + @brief Floating-point complex conjugate. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_conj_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples) +{ + static const float16_t cmplx_conj_sign[8] = { 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f }; + uint32_t blockSize = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + f16x8_t vecSrc; + f16x8_t vecSign; + + /* + * load sign vector + */ + vecSign = *(f16x8_t *) cmplx_conj_sign; + + /* Compute 4 real samples at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrc); + vst1q(pDst,vmulq(vecSrc, vecSign)); + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + blkCnt--; + } + + /* Tail */ + blkCnt = (blockSize & 0x7) >> 1; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#else +void arm_cmplx_conj_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_conj group + */ +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ \ No newline at end of file diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c new file mode 100644 index 00000000..5920a778 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c @@ -0,0 +1,213 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_conj_f32.c + * Description: Floating-point complex conjugate + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_conj Complex Conjugate + + Conjugates the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the destination data where the result should be written. + numSamples specifies the number of complex samples + and the data in each array is stored in an interleaved fashion + (real, imag, real, imag, ...). + Each array has a total of 2*numSamples values. + + The underlying algorithm is used: +
+  for (n = 0; n < numSamples; n++) {
+      pDst[(2*n)  ] =  pSrc[(2*n)  ];    // real part
+      pDst[(2*n)+1] = -pSrc[(2*n)+1];    // imag part
+  }
+  
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_conj + @{ + */ + +/** + @brief Floating-point complex conjugate. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_conj_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + static const float32_t cmplx_conj_sign[4] = { 1.0f, -1.0f, 1.0f, -1.0f }; + uint32_t blockSize = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + f32x4_t vecSrc; + f32x4_t vecSign; + + /* + * load sign vector + */ + vecSign = *(f32x4_t *) cmplx_conj_sign; + + /* Compute 4 real samples at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrc); + vst1q(pDst,vmulq(vecSrc, vecSign)); + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + blkCnt--; + } + + /* Tail */ + blkCnt = (blockSize & 0x3) >> 1; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#else +void arm_cmplx_conj_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + float32x4_t zero; + float32x4x2_t vec; + + zero = vdupq_n_f32(0.0f); + + /* Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0]+jC[1] = A[0]+(-1)*jA[1] */ + /* Calculate Complex Conjugate and then store the results in the destination buffer. */ + vec = vld2q_f32(pSrc); + vec.val[1] = vsubq_f32(zero,vec.val[1]); + vst2q_f32(pDst,vec); + + /* Increment pointers */ + pSrc += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = numSamples & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined (ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_conj group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c new file mode 100644 index 00000000..c076eff6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c @@ -0,0 +1,207 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_conj_q15.c + * Description: Q15 complex conjugate + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_conj + @{ + */ + +/** + @brief Q15 complex conjugate. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q15 value -1 (0x8000) is saturated to the maximum allowable positive value 0x7FFF. + */ + + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_cmplx_conj_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t blockSize = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + q31_t in1; + + q15x8x2_t vecSrc; + q15x8_t zero; + + zero = vdupq_n_s16(0); + + /* Compute 8 real samples at a time */ + blkCnt = blockSize >> 4U; + while (blkCnt > 0U) + { + vecSrc = vld2q(pSrc); + vecSrc.val[1] = vqsubq(zero, vecSrc.val[1]); + vst2q(pDst,vecSrc); + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrc += 16; + pDst += 16; + blkCnt --; + } + + /* Tail */ + blkCnt = (blockSize & 0xF) >> 1; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = __SSAT(-in1, 16); + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_cmplx_conj_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in1; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in2, in3, in4; /* Temporary input variables */ +#endif + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + + #if defined (ARM_MATH_DSP) + in1 = read_q15x2_ia ((q15_t **) &pSrc); + in2 = read_q15x2_ia ((q15_t **) &pSrc); + in3 = read_q15x2_ia ((q15_t **) &pSrc); + in4 = read_q15x2_ia ((q15_t **) &pSrc); + +#ifndef ARM_MATH_BIG_ENDIAN + in1 = __QASX(0, in1); + in2 = __QASX(0, in2); + in3 = __QASX(0, in3); + in4 = __QASX(0, in4); +#else + in1 = __QSAX(0, in1); + in2 = __QSAX(0, in2); + in3 = __QSAX(0, in3); + in4 = __QSAX(0, in4); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = ((uint32_t) in1 >> 16) | ((uint32_t) in1 << 16); + in2 = ((uint32_t) in2 >> 16) | ((uint32_t) in2 << 16); + in3 = ((uint32_t) in3 >> 16) | ((uint32_t) in3 << 16); + in4 = ((uint32_t) in4 >> 16) | ((uint32_t) in4 << 16); + + write_q15x2_ia (&pDst, in1); + write_q15x2_ia (&pDst, in2); + write_q15x2_ia (&pDst, in3); + write_q15x2_ia (&pDst, in4); +#else + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; + + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; + + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; + + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + in1 = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __SSAT(-in1, 16); +#else + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_conj group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c new file mode 100644 index 00000000..ec1b5b70 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c @@ -0,0 +1,193 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_conj_q31.c + * Description: Q31 complex conjugate + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_conj + @{ + */ + +/** + @brief Q31 complex conjugate. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q31 value -1 (0x80000000) is saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_conj_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ + + uint32_t blockSize = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + q31x4x2_t vecSrc; + q31_t in; /* Temporary input variable */ + q31x4_t zero; + + zero = vdupq_n_s32(0); + + + /* Compute 4 real samples at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + + vecSrc = vld2q(pSrc); + vecSrc.val[1] = vqsubq(zero, vecSrc.val[1]); + vst2q(pDst,vecSrc); + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + blkCnt --; + } + + /* Tail */ + blkCnt = (blockSize & 0x7) >> 1; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + in = *pSrc++; + *pDst++ = __QSUB(0, in); + + /* Decrement loop counter */ + blkCnt--; + } + + +} +#else + +void arm_cmplx_conj_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_conj group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f16.c new file mode 100644 index 00000000..f75d04e8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f16.c @@ -0,0 +1,288 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_dot_prod_f16.c + * Description: Floating-point complex dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_dot_prod Complex Dot Product + + Computes the dot product of two complex vectors. + The vectors are multiplied element-by-element and then summed. + + The pSrcA points to the first complex input vector and + pSrcB points to the second complex input vector. + numSamples specifies the number of complex samples + and the data in each array is stored in an interleaved fashion + (real, imag, real, imag, ...). + Each array has a total of 2*numSamples values. + + The underlying algorithm is used: + +
+  realResult = 0;
+  imagResult = 0;
+  for (n = 0; n < numSamples; n++) {
+      realResult += pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];
+      imagResult += pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];
+  }
+  
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_dot_prod + @{ + */ + +/** + @brief Floating-point complex dot product. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] numSamples number of samples in each vector + @param[out] realResult real part of the result returned here + @param[out] imagResult imaginary part of the result returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_cmplx_dot_prod_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t numSamples, + float16_t * realResult, + float16_t * imagResult) +{ + int32_t blkCnt; + float16_t real_sum, imag_sum; + f16x8_t vecSrcA, vecSrcB; + f16x8_t vec_acc = vdupq_n_f16(0.0f16); + f16x8_t vecSrcC, vecSrcD; + + blkCnt = (numSamples >> 3); + blkCnt -= 1; + if (blkCnt > 0) { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q( pSrcA); + vecSrcB = vld1q( pSrcB); + pSrcA += 8; + pSrcB += 8; + + while (blkCnt > 0) { + vec_acc = vcmlaq(vec_acc, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 8; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 8; + + vec_acc = vcmlaq(vec_acc, vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 8; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + vec_acc = vcmlaq(vec_acc, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + + vec_acc = vcmlaq(vec_acc, vecSrcC, vecSrcD); + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 7); + while (blkCnt > 0) { + mve_pred16_t p = vctp16q(blkCnt); + pSrcA += 8; + pSrcB += 8; + + vecSrcA = vldrhq_z_f16(pSrcA, p); + vecSrcB = vldrhq_z_f16(pSrcB, p); + vec_acc = vcmlaq_m(vec_acc, vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + + blkCnt -= 8; + } + } else { + /* small vector */ + blkCnt = numSamples * CMPLX_DIM; + vec_acc = vdupq_n_f16(0.0f16); + + do { + mve_pred16_t p = vctp16q(blkCnt); + + vecSrcA = vldrhq_z_f16(pSrcA, p); + vecSrcB = vldrhq_z_f16(pSrcB, p); + + vec_acc = vcmlaq_m(vec_acc, vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + blkCnt -= 8; + } + while (blkCnt > 0); + } + + /* Sum the partial parts */ + mve_cmplx_sum_intra_r_i_f16(vec_acc, real_sum, imag_sum); + + /* + * Store the real and imaginary results in the destination buffers + */ + *realResult = real_sum; + *imagResult = imag_sum; +} + +#else +void arm_cmplx_dot_prod_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t numSamples, + float16_t * realResult, + float16_t * imagResult) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 real_sum = 0.0f, imag_sum = 0.0f; /* Temporary result variables */ + _Float16 a0,b0,c0,d0; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store real and imaginary result in destination buffer. */ + *realResult = real_sum; + *imagResult = imag_sum; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_dot_prod group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ \ No newline at end of file diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c new file mode 100644 index 00000000..af60d32b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c @@ -0,0 +1,340 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_dot_prod_f32.c + * Description: Floating-point complex dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_dot_prod Complex Dot Product + + Computes the dot product of two complex vectors. + The vectors are multiplied element-by-element and then summed. + + The pSrcA points to the first complex input vector and + pSrcB points to the second complex input vector. + numSamples specifies the number of complex samples + and the data in each array is stored in an interleaved fashion + (real, imag, real, imag, ...). + Each array has a total of 2*numSamples values. + + The underlying algorithm is used: + +
+  realResult = 0;
+  imagResult = 0;
+  for (n = 0; n < numSamples; n++) {
+      realResult += pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];
+      imagResult += pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];
+  }
+  
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_dot_prod + @{ + */ + +/** + @brief Floating-point complex dot product. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] numSamples number of samples in each vector + @param[out] realResult real part of the result returned here + @param[out] imagResult imaginary part of the result returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult) +{ + int32_t blkCnt; + float32_t real_sum, imag_sum; + f32x4_t vecSrcA, vecSrcB; + f32x4_t vec_acc = vdupq_n_f32(0.0f); + f32x4_t vecSrcC, vecSrcD; + + blkCnt = numSamples >> 2; + blkCnt -= 1; + if (blkCnt > 0) { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + pSrcA += 4; + pSrcB += 4; + + while (blkCnt > 0) { + vec_acc = vcmlaq(vec_acc, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 4; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 4; + + vec_acc = vcmlaq(vec_acc, vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 4; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + vec_acc = vcmlaq(vec_acc, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + + vec_acc = vcmlaq(vec_acc, vecSrcC, vecSrcD); + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 3); + while (blkCnt > 0) { + mve_pred16_t p = vctp32q(blkCnt); + pSrcA += 4; + pSrcB += 4; + vecSrcA = vldrwq_z_f32(pSrcA, p); + vecSrcB = vldrwq_z_f32(pSrcB, p); + vec_acc = vcmlaq_m(vec_acc, vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + blkCnt -= 4; + } + } else { + /* small vector */ + blkCnt = numSamples * CMPLX_DIM; + vec_acc = vdupq_n_f32(0.0f); + + do { + mve_pred16_t p = vctp32q(blkCnt); + + vecSrcA = vldrwq_z_f32(pSrcA, p); + vecSrcB = vldrwq_z_f32(pSrcB, p); + + vec_acc = vcmlaq_m(vec_acc, vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + blkCnt -= 4; + } + while (blkCnt > 0); + } + + real_sum = vgetq_lane(vec_acc, 0) + vgetq_lane(vec_acc, 2); + imag_sum = vgetq_lane(vec_acc, 1) + vgetq_lane(vec_acc, 3); + + /* + * Store the real and imaginary results in the destination buffers + */ + *realResult = real_sum; + *imagResult = imag_sum; +} + +#else +void arm_cmplx_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t real_sum = 0.0f, imag_sum = 0.0f; /* Temporary result variables */ + float32_t a0,b0,c0,d0; + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + float32x4x2_t vec1,vec2,vec3,vec4; + float32x4_t accR,accI; + float32x2_t accum = vdup_n_f32(0); + + accR = vdupq_n_f32(0.0f); + accI = vdupq_n_f32(0.0f); + + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = numSamples >> 3U; + + while (blkCnt > 0U) + { + /* C = (A[0]+jA[1])*(B[0]+jB[1]) + ... */ + /* Calculate dot product and then store the result in a temporary buffer. */ + + vec1 = vld2q_f32(pSrcA); + vec2 = vld2q_f32(pSrcB); + + /* Increment pointers */ + pSrcA += 8; + pSrcB += 8; + + /* Re{C} = Re{A}*Re{B} - Im{A}*Im{B} */ + accR = vmlaq_f32(accR,vec1.val[0],vec2.val[0]); + accR = vmlsq_f32(accR,vec1.val[1],vec2.val[1]); + + /* Im{C} = Re{A}*Im{B} + Im{A}*Re{B} */ + accI = vmlaq_f32(accI,vec1.val[1],vec2.val[0]); + accI = vmlaq_f32(accI,vec1.val[0],vec2.val[1]); + + vec3 = vld2q_f32(pSrcA); + vec4 = vld2q_f32(pSrcB); + + /* Increment pointers */ + pSrcA += 8; + pSrcB += 8; + + /* Re{C} = Re{A}*Re{B} - Im{A}*Im{B} */ + accR = vmlaq_f32(accR,vec3.val[0],vec4.val[0]); + accR = vmlsq_f32(accR,vec3.val[1],vec4.val[1]); + + /* Im{C} = Re{A}*Im{B} + Im{A}*Re{B} */ + accI = vmlaq_f32(accI,vec3.val[1],vec4.val[0]); + accI = vmlaq_f32(accI,vec3.val[0],vec4.val[1]); + + /* Decrement the loop counter */ + blkCnt--; + } + + accum = vpadd_f32(vget_low_f32(accR), vget_high_f32(accR)); + real_sum += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(accI), vget_high_f32(accI)); + imag_sum += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + /* Tail */ + blkCnt = numSamples & 0x7; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store real and imaginary result in destination buffer. */ + *realResult = real_sum; + *imagResult = imag_sum; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_dot_prod group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c new file mode 100644 index 00000000..1910d8ad --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c @@ -0,0 +1,256 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_dot_prod_q15.c + * Description: Processing function for the Q15 Complex Dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_dot_prod + @{ + */ + +/** + @brief Q15 complex dot product. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] numSamples number of samples in each vector + @param[out] realResult real part of the result returned here + @param[out] imagResult imaginary part of the result returned her + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result. + These are accumulated in a 64-bit accumulator with 34.30 precision. + As a final step, the accumulators are converted to 8.24 format. + The return results realResult and imagResult are in 8.24 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_cmplx_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult) +{ + int32_t blkCnt; + q63_t accReal = 0LL; + q63_t accImag = 0LL; + q15x8_t vecSrcA, vecSrcB; + q15x8_t vecSrcC, vecSrcD; + + blkCnt = (numSamples >> 3); + blkCnt -= 1; + if (blkCnt > 0) { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + pSrcA += 8; + pSrcB += 8; + + while (blkCnt > 0) { + + accReal = vmlsldavaq(accReal, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 8; + + accImag = vmlaldavaxq(accImag, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 8; + + accReal = vmlsldavaq(accReal, vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 8; + + accImag = vmlaldavaxq(accImag, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + accReal = vmlsldavaq(accReal, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + accImag = vmlaldavaxq(accImag, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + + accReal = vmlsldavaq(accReal, vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + + accImag = vmlaldavaxq(accImag, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 7); + do { + mve_pred16_t p = vctp16q(blkCnt); + + pSrcA += 8; + pSrcB += 8; + + vecSrcA = vldrhq_z_s16(pSrcA, p); + vecSrcB = vldrhq_z_s16(pSrcB, p); + + accReal = vmlsldavaq_p(accReal, vecSrcA, vecSrcB, p); + accImag = vmlaldavaxq_p(accImag, vecSrcA, vecSrcB, p); + + blkCnt -= 8; + } + while ((int32_t) blkCnt > 0); + } else { + blkCnt = numSamples * CMPLX_DIM; + while (blkCnt > 0) { + mve_pred16_t p = vctp16q(blkCnt); + + vecSrcA = vldrhq_z_s16(pSrcA, p); + vecSrcB = vldrhq_z_s16(pSrcB, p); + + accReal = vmlsldavaq_p(accReal, vecSrcA, vecSrcB, p); + accImag = vmlaldavaxq_p(accImag, vecSrcA, vecSrcB, p); + + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + blkCnt -= 8; + } + } + *realResult = asrl(accReal, (14 - 8)); + *imagResult = asrl(accImag, (14 - 8)); +} +#else +void arm_cmplx_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t real_sum = 0, imag_sum = 0; /* Temporary result variables */ + q15_t a0,b0,c0,d0; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store real and imaginary result in 8.24 format */ + /* Convert real data in 34.30 to 8.24 by 6 right shifts */ + *realResult = (q31_t) (real_sum >> 6); + /* Convert imaginary data in 34.30 to 8.24 by 6 right shifts */ + *imagResult = (q31_t) (imag_sum >> 6); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_dot_prod group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c new file mode 100644 index 00000000..fac85bd0 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c @@ -0,0 +1,259 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_dot_prod_q31.c + * Description: Q31 complex dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_dot_prod + @{ + */ + +/** + @brief Q31 complex dot product. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] numSamples number of samples in each vector + @param[out] realResult real part of the result returned here + @param[out] imagResult imaginary part of the result returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format. + The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits. + Additions are nonsaturating and no overflow will occur as long as numSamples is less than 32768. + The return results realResult and imagResult are in 16.48 format. + Input down scaling is not required. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult) +{ + int32_t blkCnt; + q63_t accReal = 0LL; + q63_t accImag = 0LL; + q31x4_t vecSrcA, vecSrcB; + q31x4_t vecSrcC, vecSrcD; + + blkCnt = numSamples >> 2; + blkCnt -= 1; + if (blkCnt > 0) { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + pSrcA += 4; + pSrcB += 4; + + while (blkCnt > 0) { + + accReal = vrmlsldavhaq(accReal, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 4; + + accImag = vrmlaldavhaxq(accImag, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 4; + + accReal = vrmlsldavhaq(accReal, vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 4; + + accImag = vrmlaldavhaxq(accImag, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + accReal = vrmlsldavhaq(accReal, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + accImag = vrmlaldavhaxq(accImag, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + + accReal = vrmlsldavhaq(accReal, vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + + accImag = vrmlaldavhaxq(accImag, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 3); + do { + mve_pred16_t p = vctp32q(blkCnt); + + pSrcA += 4; + pSrcB += 4; + + vecSrcA = vldrwq_z_s32(pSrcA, p); + vecSrcB = vldrwq_z_s32(pSrcB, p); + + accReal = vrmlsldavhaq_p(accReal, vecSrcA, vecSrcB, p); + accImag = vrmlaldavhaxq_p(accImag, vecSrcA, vecSrcB, p); + + blkCnt -= 4; + } + while ((int32_t) blkCnt > 0); + } else { + blkCnt = numSamples * CMPLX_DIM; + while (blkCnt > 0) { + mve_pred16_t p = vctp32q(blkCnt); + + vecSrcA = vldrwq_z_s32(pSrcA, p); + vecSrcB = vldrwq_z_s32(pSrcB, p); + + accReal = vrmlsldavhaq_p(accReal, vecSrcA, vecSrcB, p); + accImag = vrmlaldavhaxq_p(accImag, vecSrcA, vecSrcB, p); + + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + blkCnt -= 4; + } + } + *realResult = asrl(accReal, (14 - 8)); + *imagResult = asrl(accImag, (14 - 8)); + +} + +#else +void arm_cmplx_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t real_sum = 0, imag_sum = 0; /* Temporary result variables */ + q31_t a0,b0,c0,d0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store real and imaginary result in 16.48 format */ + *realResult = real_sum; + *imagResult = imag_sum; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_dot_prod group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f16.c new file mode 100644 index 00000000..c2f31989 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f16.c @@ -0,0 +1,241 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_f16.c + * Description: Floating-point complex magnitude + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_mag Complex Magnitude + + Computes the magnitude of the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the where the result should be written. + numSamples specifies the number of complex samples + in the input array and the data is stored in an interleaved fashion + (real, imag, real, imag, ...). + The input array has a total of 2*numSamples values; + the output array has a total of numSamples values. + + The underlying algorithm is used: + +
+  for (n = 0; n < numSamples; n++) {
+      pDst[n] = sqrt(pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2);
+  }
+  
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Floating-point complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + +void arm_cmplx_mag_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples) +{ + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + f16x8x2_t vecSrc; + f16x8_t sum; + + /* Compute 4 complex samples at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + q15x8_t newtonStartVec; + f16x8_t sumHalf, invSqrt; + + vecSrc = vld2q(pSrc); + pSrc += 16; + sum = vmulq(vecSrc.val[0], vecSrc.val[0]); + sum = vfmaq(sum, vecSrc.val[1], vecSrc.val[1]); + + /* + * inlined Fast SQRT using inverse SQRT newton-raphson method + */ + + /* compute initial value */ + newtonStartVec = vdupq_n_s16(INVSQRT_MAGIC_F16) - vshrq((q15x8_t) sum, 1); + sumHalf = sum * 0.5f; + /* + * compute 3 x iterations + * + * The more iterations, the more accuracy. + * If you need to trade a bit of accuracy for more performance, + * you can comment out the 3rd use of the macro. + */ + INVSQRT_NEWTON_MVE_F16(invSqrt, sumHalf, (f16x8_t) newtonStartVec); + INVSQRT_NEWTON_MVE_F16(invSqrt, sumHalf, invSqrt); + INVSQRT_NEWTON_MVE_F16(invSqrt, sumHalf, invSqrt); + /* + * set negative values to 0 + */ + invSqrt = vdupq_m(invSqrt, (float16_t)0.0f, vcmpltq(invSqrt, (float16_t)0.0f)); + /* + * sqrt(x) = x * invSqrt(x) + */ + sum = vmulq(sum, invSqrt); + vstrhq_f16(pDst, sum); + pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + q15x8_t newtonStartVec; + f16x8_t sumHalf, invSqrt; + + vecSrc = vld2q((float16_t const *)pSrc); + sum = vmulq(vecSrc.val[0], vecSrc.val[0]); + sum = vfmaq(sum, vecSrc.val[1], vecSrc.val[1]); + + /* + * inlined Fast SQRT using inverse SQRT newton-raphson method + */ + + /* compute initial value */ + newtonStartVec = vdupq_n_s16(INVSQRT_MAGIC_F16) - vshrq((q15x8_t) sum, 1); + sumHalf = vmulq(sum, (float16_t)0.5); + /* + * compute 2 x iterations + */ + INVSQRT_NEWTON_MVE_F16(invSqrt, sumHalf, (f16x8_t) newtonStartVec); + INVSQRT_NEWTON_MVE_F16(invSqrt, sumHalf, invSqrt); + /* + * set negative values to 0 + */ + invSqrt = vdupq_m(invSqrt, (float16_t)0.0, vcmpltq(invSqrt, (float16_t)0.0)); + /* + * sqrt(x) = x * invSqrt(x) + */ + sum = vmulq(sum, invSqrt); + vstrhq_p_f16(pDst, sum, p0); + } +} + +#else +void arm_cmplx_mag_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* loop counter */ + _Float16 real, imag; /* Temporary variables to hold input values */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + arm_sqrt_f16((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + arm_sqrt_f16((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + arm_sqrt_f16((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + arm_sqrt_f16((real * real) + (imag * imag), pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + arm_sqrt_f16((real * real) + (imag * imag), pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_mag group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ \ No newline at end of file diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c new file mode 100644 index 00000000..aac6fba8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c @@ -0,0 +1,273 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_f32.c + * Description: Floating-point complex magnitude + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_mag Complex Magnitude + + Computes the magnitude of the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the where the result should be written. + numSamples specifies the number of complex samples + in the input array and the data is stored in an interleaved fashion + (real, imag, real, imag, ...). + The input array has a total of 2*numSamples values; + the output array has a total of numSamples values. + + The underlying algorithm is used: + +
+  for (n = 0; n < numSamples; n++) {
+      pDst[n] = sqrt(pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2);
+  }
+  
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Floating-point complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_vec_math.h" +#endif + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + +void arm_cmplx_mag_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + f32x4x2_t vecSrc; + f32x4_t sum; + float32_t real, imag; /* Temporary variables to hold input values */ + + /* Compute 4 complex samples at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + q31x4_t newtonStartVec; + f32x4_t sumHalf, invSqrt; + + vecSrc = vld2q(pSrc); + pSrc += 8; + sum = vmulq(vecSrc.val[0], vecSrc.val[0]); + sum = vfmaq(sum, vecSrc.val[1], vecSrc.val[1]); + + /* + * inlined Fast SQRT using inverse SQRT newton-raphson method + */ + + /* compute initial value */ + newtonStartVec = vdupq_n_s32(INVSQRT_MAGIC_F32) - vshrq((q31x4_t) sum, 1); + sumHalf = sum * 0.5f; + /* + * compute 3 x iterations + * + * The more iterations, the more accuracy. + * If you need to trade a bit of accuracy for more performance, + * you can comment out the 3rd use of the macro. + */ + INVSQRT_NEWTON_MVE_F32(invSqrt, sumHalf, (f32x4_t) newtonStartVec); + INVSQRT_NEWTON_MVE_F32(invSqrt, sumHalf, invSqrt); + INVSQRT_NEWTON_MVE_F32(invSqrt, sumHalf, invSqrt); + /* + * set negative values to 0 + */ + invSqrt = vdupq_m(invSqrt, 0.0f, vcmpltq(invSqrt, 0.0f)); + /* + * sqrt(x) = x * invSqrt(x) + */ + sum = vmulq(sum, invSqrt); + vst1q(pDst, sum); + pDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_cmplx_mag_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* loop counter */ + float32_t real, imag; /* Temporary variables to hold input values */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + + float32x4x2_t vecA; + float32x4_t vRealA; + float32x4_t vImagA; + float32x4_t vMagSqA; + + float32x4x2_t vecB; + float32x4_t vRealB; + float32x4_t vImagB; + float32x4_t vMagSqB; + + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = numSamples >> 3; + + while (blkCnt > 0U) + { + /* out = sqrt((real * real) + (imag * imag)) */ + + vecA = vld2q_f32(pSrc); + pSrc += 8; + + vecB = vld2q_f32(pSrc); + pSrc += 8; + + vRealA = vmulq_f32(vecA.val[0], vecA.val[0]); + vImagA = vmulq_f32(vecA.val[1], vecA.val[1]); + vMagSqA = vaddq_f32(vRealA, vImagA); + + vRealB = vmulq_f32(vecB.val[0], vecB.val[0]); + vImagB = vmulq_f32(vecB.val[1], vecB.val[1]); + vMagSqB = vaddq_f32(vRealB, vImagB); + + /* Store the result in the destination buffer. */ + vst1q_f32(pDst, __arm_vec_sqrt_f32_neon(vMagSqA)); + pDst += 4; + + vst1q_f32(pDst, __arm_vec_sqrt_f32_neon(vMagSqB)); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + blkCnt = numSamples & 7; + +#else + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_mag group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f64.c new file mode 100644 index 00000000..c2bcd568 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f64.c @@ -0,0 +1,100 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_f64.c + * Description: Floating-point complex magnitude + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_mag Complex Magnitude + + Computes the magnitude of the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the where the result should be written. + numSamples specifies the number of complex samples + in the input array and the data is stored in an interleaved fashion + (real, imag, real, imag, ...). + The input array has a total of 2*numSamples values; + the output array has a total of numSamples values. + + The underlying algorithm is used: + +
+  for (n = 0; n < numSamples; n++) {
+      pDst[n] = sqrt(pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2);
+  }
+  
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Floating-point complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ +void arm_cmplx_mag_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* loop counter */ + float64_t real, imag; /* Temporary variables to hold input values */ + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + *pDst++ = sqrt((real * real) + (imag * imag)); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of cmplx_mag group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_fast_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_fast_q15.c new file mode 100644 index 00000000..eac2a143 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_fast_q15.c @@ -0,0 +1,223 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_fast_q15.c + * Description: Q15 complex magnitude + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Q15 complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format. + Fast functions are less accurate. This function will tend to clamp to 0 + the too small values. So sqrt(x*x) = x will not always be true. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_cmplx_mag_fast_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + q15x8x2_t vecSrc; + q15x8_t sum; + q31_t in; + q31_t acc0; + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vld2q(pSrc); + pSrc += 16; + sum = vqaddq(vmulhq(vecSrc.val[0], vecSrc.val[0]), + vmulhq(vecSrc.val[1], vecSrc.val[1])); + + sum = vshrq(sum, 1); + + sum = FAST_VSQRT_Q15(sum); + + vst1q(pDst, sum); + pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = blockSize & 7; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); + + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_cmplx_mag_fast_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_DSP) + q31_t in; + q31_t acc0; /* Accumulators */ +#else + q15_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + +#if defined (ARM_MATH_DSP) + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); + + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); + + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); + + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + +#if defined (ARM_MATH_DSP) + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_mag group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c new file mode 100644 index 00000000..e29a3d50 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c @@ -0,0 +1,221 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_q15.c + * Description: Q15 complex magnitude + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Q15 complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_cmplx_mag_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + q15x8x2_t vecSrc; + q15x8_t sum; + q31_t in; + q31_t acc0; + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vld2q(pSrc); + pSrc += 16; + sum = vqaddq(vmulhq(vecSrc.val[0], vecSrc.val[0]), + vmulhq(vecSrc.val[1], vecSrc.val[1])); + + sum = vshrq(sum, 1); + + sum = FAST_VSQRT_Q15(sum); + + vst1q(pDst, sum); + pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = blockSize & 7; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); + + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_cmplx_mag_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_DSP) + q31_t in; + q31_t acc0; /* Accumulators */ +#else + q15_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + +#if defined (ARM_MATH_DSP) + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + +#if defined (ARM_MATH_DSP) + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_mag group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c new file mode 100644 index 00000000..57a72f5f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c @@ -0,0 +1,201 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_q31.c + * Description: Q31 complex magnitude + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Q31 complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format. + Input down scaling is not required. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_cmplx_mag_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + + q31x4x2_t vecSrc; + q31x4_t sum; + + q31_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ + + /* Compute 4 complex samples at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + vecSrc = vld2q(pSrc); + + sum = vqaddq(vmulhq(vecSrc.val[0], vecSrc.val[0]), + vmulhq(vecSrc.val[1], vecSrc.val[1])); + + sum = vshrq(sum, 1); + + /* + + This function is using a table. There are compilations flags to avoid + including this table (and in this case, arm_cmplx_maq_q31 must not + be built and linked.) + + */ + sum = FAST_VSQRT_Q31(sum); + + vst1q(pDst, sum); + + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + pSrc += 8; + pDst += 4; + } + + /* + * tail + */ + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + + /* store result in 2.30 format in destination buffer. */ + arm_sqrt_q31(acc0 + acc1, pDst++); + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_cmplx_mag_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + + /* store result in 2.30 format in destination buffer. */ + arm_sqrt_q31(acc0 + acc1, pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + arm_sqrt_q31(acc0 + acc1, pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + arm_sqrt_q31(acc0 + acc1, pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + arm_sqrt_q31(acc0 + acc1, pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + + /* store result in 2.30 format in destination buffer. */ + arm_sqrt_q31(acc0 + acc1, pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_mag group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f16.c new file mode 100644 index 00000000..5d5a3a24 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f16.c @@ -0,0 +1,174 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_squared_f16.c + * Description: Floating-point complex magnitude squared + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_mag_squared Complex Magnitude Squared + + Computes the magnitude squared of the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the where the result should be written. + numSamples specifies the number of complex samples + in the input array and the data is stored in an interleaved fashion + (real, imag, real, imag, ...). + The input array has a total of 2*numSamples values; + the output array has a total of numSamples values. + + The underlying algorithm is used: + +
+  for (n = 0; n < numSamples; n++) {
+      pDst[n] = pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2;
+  }
+  
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_mag_squared + @{ + */ + +/** + @brief Floating-point complex magnitude squared. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mag_squared_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples) +{ + int32_t blockSize = numSamples; /* loop counters */ + f16x8x2_t vecSrc; + f16x8_t sum; + + /* Compute 4 complex samples at a time */ + while (blockSize > 0) + { + mve_pred16_t p = vctp16q(blockSize); + vecSrc = vld2q(pSrc); + sum = vmulq_m(vuninitializedq_f16(),vecSrc.val[0], vecSrc.val[0],p); + sum = vfmaq_m(sum, vecSrc.val[1], vecSrc.val[1],p); + vstrhq_p_f16(pDst, sum,p); + + pSrc += 16; + pDst += 8; + + /* + * Decrement the blockSize loop counter + */ + blockSize-= 8; + } + +} + +#else +void arm_cmplx_mag_squared_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 real, imag; /* Temporary input variables */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_mag_squared group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ \ No newline at end of file diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c new file mode 100644 index 00000000..861585f1 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c @@ -0,0 +1,235 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_squared_f32.c + * Description: Floating-point complex magnitude squared + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_mag_squared Complex Magnitude Squared + + Computes the magnitude squared of the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the where the result should be written. + numSamples specifies the number of complex samples + in the input array and the data is stored in an interleaved fashion + (real, imag, real, imag, ...). + The input array has a total of 2*numSamples values; + the output array has a total of numSamples values. + + The underlying algorithm is used: + +
+  for (n = 0; n < numSamples; n++) {
+      pDst[n] = pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2;
+  }
+  
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_mag_squared + @{ + */ + +/** + @brief Floating-point complex magnitude squared. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mag_squared_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + f32x4x2_t vecSrc; + f32x4_t sum; + float32_t real, imag; /* Temporary input variables */ + + /* Compute 4 complex samples at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + vecSrc = vld2q(pSrc); + sum = vmulq(vecSrc.val[0], vecSrc.val[0]); + sum = vfmaq(sum, vecSrc.val[1], vecSrc.val[1]); + vst1q(pDst, sum); + + pSrc += 8; + pDst += 4; + + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#else +void arm_cmplx_mag_squared_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t real, imag; /* Temporary input variables */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + float32x4x2_t vecA; + float32x4_t vRealA; + float32x4_t vImagA; + float32x4_t vMagSqA; + + float32x4x2_t vecB; + float32x4_t vRealB; + float32x4_t vImagB; + float32x4_t vMagSqB; + + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = numSamples >> 3; + + while (blkCnt > 0U) + { + /* out = sqrt((real * real) + (imag * imag)) */ + + vecA = vld2q_f32(pSrc); + pSrc += 8; + + vRealA = vmulq_f32(vecA.val[0], vecA.val[0]); + vImagA = vmulq_f32(vecA.val[1], vecA.val[1]); + vMagSqA = vaddq_f32(vRealA, vImagA); + + vecB = vld2q_f32(pSrc); + pSrc += 8; + + vRealB = vmulq_f32(vecB.val[0], vecB.val[0]); + vImagB = vmulq_f32(vecB.val[1], vecB.val[1]); + vMagSqB = vaddq_f32(vRealB, vImagB); + + /* Store the result in the destination buffer. */ + vst1q_f32(pDst, vMagSqA); + pDst += 4; + + vst1q_f32(pDst, vMagSqB); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + blkCnt = numSamples & 7; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_mag_squared group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f64.c new file mode 100644 index 00000000..fde0321e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f64.c @@ -0,0 +1,76 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_squared_f64.c + * Description: Floating-point complex magnitude squared + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag_squared + @{ + */ + +/** + @brief Floating-point complex magnitude squared. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ +void arm_cmplx_mag_squared_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + float64_t real, imag; /* Temporary input variables */ + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of cmplx_mag_squared group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c new file mode 100644 index 00000000..42fc442e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c @@ -0,0 +1,221 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_squared_q15.c + * Description: Q15 complex magnitude squared + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag_squared + @{ + */ + +/** + @brief Q15 complex magnitude squared. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mag_squared_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + q31_t in; + q31_t acc0; /* Accumulators */ + q15x8x2_t vecSrc; + q15x8_t vReal, vImag; + q15x8_t vMagSq; + + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vld2q(pSrc); + vReal = vmulhq(vecSrc.val[0], vecSrc.val[0]); + vImag = vmulhq(vecSrc.val[1], vecSrc.val[1]); + vMagSq = vqaddq(vReal, vImag); + vMagSq = vshrq(vMagSq, 1); + + vst1q(pDst, vMagSq); + + pSrc += 16; + pDst += 8; + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + blkCnt --; + } + + /* + * tail + */ + blkCnt = blockSize & 7; + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) (acc0 >> 17); + + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#else +void arm_cmplx_mag_squared_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_DSP) + q31_t in; + q31_t acc0; /* Accumulators */ +#else + q15_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + +#if defined (ARM_MATH_DSP) + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) (acc0 >> 17); + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + *pDst++ = (q15_t) (acc0 >> 17); + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + *pDst++ = (q15_t) (acc0 >> 17); + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + *pDst++ = (q15_t) (acc0 >> 17); +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + +#if defined (ARM_MATH_DSP) + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) (acc0 >> 17); +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_mag_squared group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c new file mode 100644 index 00000000..4ccde36e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c @@ -0,0 +1,187 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_squared_q31.c + * Description: Q31 complex magnitude squared + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag_squared + @{ + */ + +/** + @brief Q31 complex magnitude squared. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format. + Input down scaling is not required. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mag_squared_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + q31x4x2_t vecSrc; + q31x4_t vReal, vImag; + q31x4_t vMagSq; + q31_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ + + /* Compute 4 complex samples at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + vecSrc = vld2q(pSrc); + vReal = vmulhq(vecSrc.val[0], vecSrc.val[0]); + vImag = vmulhq(vecSrc.val[1], vecSrc.val[1]); + vMagSq = vqaddq(vReal, vImag); + vMagSq = vshrq(vMagSq, 1); + + vst1q(pDst, vMagSq); + + pSrc += 8; + pDst += 4; + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + blkCnt --; + } + + /* Tail */ + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + + /* store result in 3.29 format in destination buffer. */ + *pDst++ = acc0 + acc1; + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_cmplx_mag_squared_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + /* store the result in 3.29 format in the destination buffer. */ + *pDst++ = acc0 + acc1; + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + *pDst++ = acc0 + acc1; + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + *pDst++ = acc0 + acc1; + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + *pDst++ = acc0 + acc1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + + /* store result in 3.29 format in destination buffer. */ + *pDst++ = acc0 + acc1; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_mag_squared group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f16.c new file mode 100644 index 00000000..34094509 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f16.c @@ -0,0 +1,271 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_cmplx_f16.c + * Description: Floating-point complex-by-complex multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication + + Multiplies a complex vector by another complex vector and generates a complex result. + The data in the complex arrays is stored in an interleaved fashion + (real, imag, real, imag, ...). + The parameter numSamples represents the number of complex + samples processed. The complex arrays have a total of 2*numSamples + real values. + + The underlying algorithm is used: + +
+  for (n = 0; n < numSamples; n++) {
+      pDst[(2*n)+0] = pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];
+      pDst[(2*n)+1] = pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];
+  }
+  
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup CmplxByCmplxMult + @{ + */ + +/** + @brief Floating-point complex-by-complex multiplication. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mult_cmplx_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t numSamples) +{ + int32_t blkCnt; + f16x8_t vecSrcA, vecSrcB; + f16x8_t vecSrcC, vecSrcD; + f16x8_t vec_acc; + + blkCnt = (numSamples >> 3); + blkCnt -= 1; + if (blkCnt > 0) { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + pSrcA += 8; + pSrcB += 8; + + while (blkCnt > 0) { + vec_acc = vcmulq(vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 8; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 8; + vst1q(pDst, vec_acc); + pDst += 8; + + vec_acc = vcmulq(vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 8; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 8; + vst1q(pDst, vec_acc); + pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + vec_acc = vcmulq(vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + vst1q(pDst, vec_acc); + pDst += 8; + + vec_acc = vcmulq(vecSrcC, vecSrcD); + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + vst1q(pDst, vec_acc); + pDst += 8; + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 7); + while (blkCnt > 0) { + mve_pred16_t p = vctp16q(blkCnt); + pSrcA += 8; + pSrcB += 8; + + vecSrcA = vldrhq_z_f16(pSrcA, p); + vecSrcB = vldrhq_z_f16(pSrcB, p); + vec_acc = vcmulq_m(vuninitializedq_f16(),vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + + vstrhq_p_f16(pDst, vec_acc, p); + pDst += 8; + + blkCnt -= 8; + } + } else { + /* small vector */ + blkCnt = numSamples * CMPLX_DIM; + + do { + mve_pred16_t p = vctp16q(blkCnt); + + vecSrcA = vldrhq_z_f16(pSrcA, p); + vecSrcB = vldrhq_z_f16(pSrcB, p); + + vec_acc = vcmulq_m(vuninitializedq_f16(),vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + vstrhq_p_f16(pDst, vec_acc, p); + pDst += 8; + + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + blkCnt -= 8; + } + while (blkCnt > 0); + } + +} + + +#else +void arm_cmplx_mult_cmplx_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 a, b, c, d; /* Temporary variables to store real and imaginary values */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + /* store result in destination buffer. */ + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in destination buffer. */ + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of CmplxByCmplxMult group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ \ No newline at end of file diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c new file mode 100644 index 00000000..5d2c66c4 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c @@ -0,0 +1,305 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_cmplx_f32.c + * Description: Floating-point complex-by-complex multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication + + Multiplies a complex vector by another complex vector and generates a complex result. + The data in the complex arrays is stored in an interleaved fashion + (real, imag, real, imag, ...). + The parameter numSamples represents the number of complex + samples processed. The complex arrays have a total of 2*numSamples + real values. + + The underlying algorithm is used: + +
+  for (n = 0; n < numSamples; n++) {
+      pDst[(2*n)+0] = pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];
+      pDst[(2*n)+1] = pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];
+  }
+  
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup CmplxByCmplxMult + @{ + */ + +/** + @brief Floating-point complex-by-complex multiplication. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mult_cmplx_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples) +{ + int32_t blkCnt; + f32x4_t vecSrcA, vecSrcB; + f32x4_t vecSrcC, vecSrcD; + f32x4_t vec_acc; + + blkCnt = numSamples >> 2; + blkCnt -= 1; + if (blkCnt > 0) { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + pSrcA += 4; + pSrcB += 4; + + while (blkCnt > 0) { + vec_acc = vcmulq(vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 4; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 4; + vst1q(pDst, vec_acc); + pDst += 4; + + vec_acc = vcmulq(vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 4; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 4; + vst1q(pDst, vec_acc); + pDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + vec_acc = vcmulq(vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + vst1q(pDst, vec_acc); + pDst += 4; + + vec_acc = vcmulq(vecSrcC, vecSrcD); + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + vst1q(pDst, vec_acc); + pDst += 4; + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 3); + while (blkCnt > 0) { + mve_pred16_t p = vctp32q(blkCnt); + pSrcA += 4; + pSrcB += 4; + + vecSrcA = vldrwq_z_f32(pSrcA, p); + vecSrcB = vldrwq_z_f32(pSrcB, p); + vec_acc = vcmulq_m(vuninitializedq_f32(),vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + + vstrwq_p_f32(pDst, vec_acc, p); + pDst += 4; + + blkCnt -= 4; + } + } else { + /* small vector */ + blkCnt = numSamples * CMPLX_DIM; + vec_acc = vdupq_n_f32(0.0f); + + do { + mve_pred16_t p = vctp32q(blkCnt); + + vecSrcA = vldrwq_z_f32(pSrcA, p); + vecSrcB = vldrwq_z_f32(pSrcB, p); + + vec_acc = vcmulq_m(vuninitializedq_f32(),vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + vstrwq_p_f32(pDst, vec_acc, p); + pDst += 4; + + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + blkCnt -= 4; + } + while (blkCnt > 0); + } + +} + +#else +void arm_cmplx_mult_cmplx_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t a, b, c, d; /* Temporary variables to store real and imaginary values */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + float32x4x2_t va, vb; + float32x4x2_t outCplx; + + /* Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + va = vld2q_f32(pSrcA); // load & separate real/imag pSrcA (de-interleave 2) + vb = vld2q_f32(pSrcB); // load & separate real/imag pSrcB + + /* Increment pointers */ + pSrcA += 8; + pSrcB += 8; + + /* Re{C} = Re{A}*Re{B} - Im{A}*Im{B} */ + outCplx.val[0] = vmulq_f32(va.val[0], vb.val[0]); + outCplx.val[0] = vmlsq_f32(outCplx.val[0], va.val[1], vb.val[1]); + + /* Im{C} = Re{A}*Im{B} + Im{A}*Re{B} */ + outCplx.val[1] = vmulq_f32(va.val[0], vb.val[1]); + outCplx.val[1] = vmlaq_f32(outCplx.val[1], va.val[1], vb.val[0]); + + vst2q_f32(pDst, outCplx); + + /* Increment pointer */ + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = numSamples & 3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + /* store result in destination buffer. */ + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in destination buffer. */ + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of CmplxByCmplxMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f64.c new file mode 100644 index 00000000..75a044c4 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f64.c @@ -0,0 +1,83 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_cmplx_f64.c + * Description: Floating-point complex-by-complex multiplication + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByCmplxMult + @{ + */ + +/** + @brief Floating-point complex-by-complex multiplication. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +void arm_cmplx_mult_cmplx_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + float64_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + float64_t a, b, c, d; /* Temporary variables to store real and imaginary values */ + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in destination buffer. */ + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of CmplxByCmplxMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c new file mode 100644 index 00000000..53fbe58d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c @@ -0,0 +1,258 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_cmplx_q15.c + * Description: Q15 complex-by-complex multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByCmplxMult + @{ + */ + +/** + @brief Q15 complex-by-complex multiplication. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mult_cmplx_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples) +{ + int32_t blkCnt; + q15x8_t vecSrcA, vecSrcB; + q15x8_t vecSrcC, vecSrcD; + q15x8_t vecDst; + + blkCnt = (numSamples >> 3); + blkCnt -= 1; + if (blkCnt > 0) + { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + pSrcA += 8; + pSrcB += 8; + + while (blkCnt > 0) + { + + /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */ + vecDst = vqdmlsdhq(vuninitializedq_s16(), vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 8; + + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */ + vecDst = vqdmladhxq(vecDst, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 8; + + vstrhq_s16(pDst, vshrq(vecDst, 2)); + pDst += 8; + + vecDst = vqdmlsdhq(vuninitializedq_s16(), vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 8; + + vecDst = vqdmladhxq(vecDst, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 8; + + vstrhq_s16(pDst, vshrq(vecDst, 2)); + pDst += 8; + + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + vecDst = vqdmlsdhq(vuninitializedq_s16(), vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + vecDst = vqdmladhxq(vecDst, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + + vstrhq_s16(pDst, vshrq(vecDst, 2)); + pDst += 8; + + vecDst = vqdmlsdhq(vuninitializedq_s16(), vecSrcC, vecSrcD); + vecDst = vqdmladhxq(vecDst, vecSrcC, vecSrcD); + + vstrhq_s16(pDst, vshrq(vecDst, 2)); + pDst += 8; + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 7); + do + { + mve_pred16_t p = vctp16q(blkCnt); + + pSrcA += 8; + pSrcB += 8; + + vecSrcA = vldrhq_z_s16(pSrcA, p); + vecSrcB = vldrhq_z_s16(pSrcB, p); + + vecDst = vqdmlsdhq_m(vuninitializedq_s16(), vecSrcA, vecSrcB, p); + vecDst = vqdmladhxq_m(vecDst, vecSrcA, vecSrcB, p); + + vecDst = vshrq_m(vuninitializedq_s16(), vecDst, 2, p); + vstrhq_p_s16(pDst, vecDst, p); + pDst += 8; + + blkCnt -= 8; + } + while ((int32_t) blkCnt > 0); + } + else + { + blkCnt = numSamples * CMPLX_DIM; + while (blkCnt > 0) { + mve_pred16_t p = vctp16q(blkCnt); + + vecSrcA = vldrhq_z_s16(pSrcA, p); + vecSrcB = vldrhq_z_s16(pSrcB, p); + + vecDst = vqdmlsdhq_m(vuninitializedq_s16(), vecSrcA, vecSrcB, p); + vecDst = vqdmladhxq_m(vecDst, vecSrcA, vecSrcB, p); + + vecDst = vshrq_m(vuninitializedq_s16(), vecDst, 2, p); + vstrhq_p_s16(pDst, vecDst, p); + + pDst += 8; + pSrcA += 8; + pSrcB += 8; + + blkCnt -= 8; + } + } +} +#else +void arm_cmplx_mult_cmplx_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q15_t a, b, c, d; /* Temporary variables */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of CmplxByCmplxMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c new file mode 100644 index 00000000..7f945619 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c @@ -0,0 +1,253 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_cmplx_q31.c + * Description: Q31 complex-by-complex multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByCmplxMult + @{ + */ + +/** + @brief Q31 complex-by-complex multiplication. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format. + Input down scaling is not required. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_cmplx_mult_cmplx_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples) +{ + int32_t blkCnt; + q31x4_t vecSrcA, vecSrcB; + q31x4_t vecSrcC, vecSrcD; + q31x4_t vecDst; + + blkCnt = numSamples >> 2; + blkCnt -= 1; + if (blkCnt > 0) { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + pSrcA += 4; + pSrcB += 4; + + while (blkCnt > 0) { + + /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */ + vecDst = vqdmlsdhq(vuninitializedq_s32(), vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 4; + + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */ + vecDst = vqdmladhxq(vecDst, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 4; + + vst1q(pDst, vshrq(vecDst, 2)); + pDst += 4; + + vecDst = vqdmlsdhq(vuninitializedq_s32(), vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 4; + + vecDst = vqdmladhxq(vecDst, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 4; + + vst1q(pDst, vshrq(vecDst, 2)); + pDst += 4; + + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + vecDst = vqdmlsdhq(vuninitializedq_s32(), vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + vecDst = vqdmladhxq(vecDst, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + + vst1q(pDst, vshrq(vecDst, 2)); + pDst += 4; + + vecDst = vqdmlsdhq(vuninitializedq_s32(), vecSrcC, vecSrcD); + vecDst = vqdmladhxq(vecDst, vecSrcC, vecSrcD); + + vst1q(pDst, vshrq(vecDst, 2)); + pDst += 4; + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 3); + do { + mve_pred16_t p = vctp32q(blkCnt); + + pSrcA += 4; + pSrcB += 4; + + vecSrcA = vldrwq_z_s32(pSrcA, p); + vecSrcB = vldrwq_z_s32(pSrcB, p); + + vecDst = vqdmlsdhq_m(vuninitializedq_s32(), vecSrcA, vecSrcB, p); + vecDst = vqdmladhxq_m(vecDst, vecSrcA, vecSrcB, p); + + vecDst = vshrq_m(vuninitializedq_s32(), vecDst, 2, p); + vstrwq_p_s32(pDst, vecDst, p); + pDst += 4; + + blkCnt -= 4; + } + while ((int32_t) blkCnt > 0); + } else { + blkCnt = numSamples * CMPLX_DIM; + while (blkCnt > 0) { + mve_pred16_t p = vctp32q(blkCnt); + + vecSrcA = vldrwq_z_s32(pSrcA, p); + vecSrcB = vldrwq_z_s32(pSrcB, p); + + vecDst = vqdmlsdhq_m(vuninitializedq_s32(), vecSrcA, vecSrcB, p); + vecDst = vqdmladhxq_m(vecDst, vecSrcA, vecSrcB, p); + + vecDst = vshrq_m(vuninitializedq_s32(), vecDst, 2, p); + vstrwq_p_s32(pDst, vecDst, p); + + pDst += 4; + pSrcA += 4; + pSrcB += 4; + + blkCnt -= 4; + } + } +} +#else +void arm_cmplx_mult_cmplx_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t a, b, c, d; /* Temporary variables */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + /* store result in 3.29 format in destination buffer. */ + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in 3.29 format in destination buffer. */ + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of CmplxByCmplxMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f16.c new file mode 100644 index 00000000..248858bc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f16.c @@ -0,0 +1,194 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_real_f16.c + * Description: Floating-point complex by real multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup CmplxByRealMult Complex-by-Real Multiplication + + Multiplies a complex vector by a real vector and generates a complex result. + The data in the complex arrays is stored in an interleaved fashion + (real, imag, real, imag, ...). + The parameter numSamples represents the number of complex + samples processed. The complex arrays have a total of 2*numSamples + real values while the real array has a total of numSamples + real values. + + The underlying algorithm is used: + +
+  for (n = 0; n < numSamples; n++) {
+      pCmplxDst[(2*n)+0] = pSrcCmplx[(2*n)+0] * pSrcReal[n];
+      pCmplxDst[(2*n)+1] = pSrcCmplx[(2*n)+1] * pSrcReal[n];
+  }
+  
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup CmplxByRealMult + @{ + */ + +/** + @brief Floating-point complex-by-real multiplication. + @param[in] pSrcCmplx points to complex input vector + @param[in] pSrcReal points to real input vector + @param[out] pCmplxDst points to complex output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mult_real_f16( + const float16_t * pSrcCmplx, + const float16_t * pSrcReal, + float16_t * pCmplxDst, + uint32_t numSamples) +{ + static const uint16_t stride_cmplx_x_real_16[8] = { + 0, 0, 1, 1, 2, 2, 3, 3 + }; + uint32_t blockSizeC = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + f16x8_t rVec; + f16x8_t cmplxVec; + f16x8_t dstVec; + uint16x8_t strideVec; + + + /* stride vector for pairs of real generation */ + strideVec = vld1q(stride_cmplx_x_real_16); + + /* Compute 4 complex outputs at a time */ + blkCnt = blockSizeC >> 3; + while (blkCnt > 0U) + { + cmplxVec = vld1q(pSrcCmplx); + rVec = vldrhq_gather_shifted_offset_f16(pSrcReal, strideVec); + dstVec = vmulq(cmplxVec, rVec); + vst1q(pCmplxDst, dstVec); + + pSrcReal += 4; + pSrcCmplx += 8; + pCmplxDst += 8; + blkCnt--; + } + + blkCnt = blockSizeC & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + cmplxVec = vld1q(pSrcCmplx); + rVec = vldrhq_gather_shifted_offset_f16(pSrcReal, strideVec); + dstVec = vmulq(cmplxVec, rVec); + vstrhq_p_f16(pCmplxDst, dstVec, p0); + } +} + +#else +void arm_cmplx_mult_real_f16( + const float16_t * pSrcCmplx, + const float16_t * pSrcReal, + float16_t * pCmplxDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + float16_t in; /* Temporary variable */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store result in destination buffer. */ + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + in = *pSrcReal++; + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + in = *pSrcReal++; + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + in = *pSrcReal++; + *pCmplxDst++ = *pSrcCmplx++* in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store result in destination buffer. */ + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of CmplxByRealMult group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ \ No newline at end of file diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c new file mode 100644 index 00000000..bc0f59b2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c @@ -0,0 +1,224 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_real_f32.c + * Description: Floating-point complex by real multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup CmplxByRealMult Complex-by-Real Multiplication + + Multiplies a complex vector by a real vector and generates a complex result. + The data in the complex arrays is stored in an interleaved fashion + (real, imag, real, imag, ...). + The parameter numSamples represents the number of complex + samples processed. The complex arrays have a total of 2*numSamples + real values while the real array has a total of numSamples + real values. + + The underlying algorithm is used: + +
+  for (n = 0; n < numSamples; n++) {
+      pCmplxDst[(2*n)+0] = pSrcCmplx[(2*n)+0] * pSrcReal[n];
+      pCmplxDst[(2*n)+1] = pSrcCmplx[(2*n)+1] * pSrcReal[n];
+  }
+  
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup CmplxByRealMult + @{ + */ + +/** + @brief Floating-point complex-by-real multiplication. + @param[in] pSrcCmplx points to complex input vector + @param[in] pSrcReal points to real input vector + @param[out] pCmplxDst points to complex output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mult_real_f32( + const float32_t * pSrcCmplx, + const float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples) +{ + static const uint32_t stride_cmplx_x_real_32[4] = { 0, 0, 1, 1 }; + + uint32_t blockSizeC = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + f32x4_t rVec; + f32x4_t cmplxVec; + f32x4_t dstVec; + uint32x4_t strideVec; + float32_t in; + + + /* stride vector for pairs of real generation */ + strideVec = vld1q(stride_cmplx_x_real_32); + + /* Compute 4 complex outputs at a time */ + blkCnt = blockSizeC >> 2; + while (blkCnt > 0U) + { + cmplxVec = vld1q(pSrcCmplx); + rVec = vldrwq_gather_shifted_offset_f32(pSrcReal, strideVec); + dstVec = vmulq(cmplxVec, rVec); + vst1q(pCmplxDst, dstVec); + + pSrcReal += 2; + pSrcCmplx += 4; + pCmplxDst += 4; + blkCnt--; + } + + blkCnt = (blockSizeC & 3) >> 1; + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store result in destination buffer. */ + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_cmplx_mult_real_f32( + const float32_t * pSrcCmplx, + const float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t in; /* Temporary variable */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + float32x4_t r; + float32x4x2_t ab,outCplx; + + /* Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + ab = vld2q_f32(pSrcCmplx); // load & separate real/imag pSrcA (de-interleave 2) + r = vld1q_f32(pSrcReal); // load & separate real/imag pSrcB + + /* Increment pointers */ + pSrcCmplx += 8; + pSrcReal += 4; + + outCplx.val[0] = vmulq_f32(ab.val[0], r); + outCplx.val[1] = vmulq_f32(ab.val[1], r); + + vst2q_f32(pCmplxDst, outCplx); + pCmplxDst += 8; + + blkCnt--; + } + + /* Tail */ + blkCnt = numSamples & 3; +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store result in destination buffer. */ + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + in = *pSrcReal++; + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + in = *pSrcReal++; + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + in = *pSrcReal++; + *pCmplxDst++ = *pSrcCmplx++* in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store result in destination buffer. */ + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of CmplxByRealMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c new file mode 100644 index 00000000..a43383b7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c @@ -0,0 +1,238 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_real_q15.c + * Description: Q15 complex by real multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByRealMult + @{ + */ + +/** + @brief Q15 complex-by-real multiplication. + @param[in] pSrcCmplx points to complex input vector + @param[in] pSrcReal points to real input vector + @param[out] pCmplxDst points to complex output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mult_real_q15( + const q15_t * pSrcCmplx, + const q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples) +{ + static const uint16_t stride_cmplx_x_real_16[8] = { + 0, 0, 1, 1, 2, 2, 3, 3 + }; + q15x8_t rVec; + q15x8_t cmplxVec; + q15x8_t dstVec; + uint16x8_t strideVec; + uint32_t blockSizeC = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + q15_t in; + + /* + * stride vector for pairs of real generation + */ + strideVec = vld1q(stride_cmplx_x_real_16); + + blkCnt = blockSizeC >> 3; + + while (blkCnt > 0U) + { + cmplxVec = vld1q(pSrcCmplx); + rVec = vldrhq_gather_shifted_offset_s16(pSrcReal, strideVec); + dstVec = vqdmulhq(cmplxVec, rVec); + vst1q(pCmplxDst, dstVec); + + pSrcReal += 4; + pSrcCmplx += 8; + pCmplxDst += 8; + blkCnt --; + } + + /* Tail */ + blkCnt = (blockSizeC & 7) >> 1; + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store the result in the destination buffer. */ + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_cmplx_mult_real_q15( + const q15_t * pSrcCmplx, + const q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q15_t in; /* Temporary variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t inA1, inA2; /* Temporary variables to hold input data */ + q31_t inB1; /* Temporary variables to hold input data */ + q15_t out1, out2, out3, out4; /* Temporary variables to hold output data */ + q31_t mul1, mul2, mul3, mul4; /* Temporary variables to hold intermediate data */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + +#if defined (ARM_MATH_DSP) + /* read 2 complex numbers both real and imaginary from complex input buffer */ + inA1 = read_q15x2_ia ((q15_t **) &pSrcCmplx); + inA2 = read_q15x2_ia ((q15_t **) &pSrcCmplx); + /* read 2 real values at a time from real input buffer */ + inB1 = read_q15x2_ia ((q15_t **) &pSrcReal); + + /* multiply complex number with real numbers */ +#ifndef ARM_MATH_BIG_ENDIAN + mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1)); + mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1)); + mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16)); + mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16)); +#else + mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16)); + mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16)); + mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1); + mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* saturate the result */ + out1 = (q15_t) __SSAT(mul1 >> 15U, 16); + out2 = (q15_t) __SSAT(mul2 >> 15U, 16); + out3 = (q15_t) __SSAT(mul3 >> 15U, 16); + out4 = (q15_t) __SSAT(mul4 >> 15U, 16); + + /* pack real and imaginary outputs and store them to destination */ + write_q15x2_ia (&pCmplxDst, __PKHBT(out1, out2, 16)); + write_q15x2_ia (&pCmplxDst, __PKHBT(out3, out4, 16)); + + inA1 = read_q15x2_ia ((q15_t **) &pSrcCmplx); + inA2 = read_q15x2_ia ((q15_t **) &pSrcCmplx); + inB1 = read_q15x2_ia ((q15_t **) &pSrcReal); + +#ifndef ARM_MATH_BIG_ENDIAN + mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1)); + mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1)); + mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16)); + mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16)); +#else + mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16)); + mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16)); + mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1); + mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + out1 = (q15_t) __SSAT(mul1 >> 15U, 16); + out2 = (q15_t) __SSAT(mul2 >> 15U, 16); + out3 = (q15_t) __SSAT(mul3 >> 15U, 16); + out4 = (q15_t) __SSAT(mul4 >> 15U, 16); + + write_q15x2_ia (&pCmplxDst, __PKHBT(out1, out2, 16)); + write_q15x2_ia (&pCmplxDst, __PKHBT(out3, out4, 16)); +#else + in = *pSrcReal++; + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + in = *pSrcReal++; + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + in = *pSrcReal++; + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + in = *pSrcReal++; + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store the result in the destination buffer. */ + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of CmplxByRealMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c new file mode 100644 index 00000000..de13757d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c @@ -0,0 +1,204 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_real_q31.c + * Description: Q31 complex by real multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByRealMult + @{ + */ + +/** + @brief Q31 complex-by-real multiplication. + @param[in] pSrcCmplx points to complex input vector + @param[in] pSrcReal points to real input vector + @param[out] pCmplxDst points to complex output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_cmplx_mult_real_q31( + const q31_t * pSrcCmplx, + const q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples) +{ + + static const uint32_t stride_cmplx_x_real_32[4] = { + 0, 0, 1, 1 + }; + q31x4_t rVec; + q31x4_t cmplxVec; + q31x4_t dstVec; + uint32x4_t strideVec; + uint32_t blockSizeC = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + q31_t in; + + /* + * stride vector for pairs of real generation + */ + strideVec = vld1q(stride_cmplx_x_real_32); + + /* Compute 4 complex outputs at a time */ + blkCnt = blockSizeC >> 2; + while (blkCnt > 0U) + { + cmplxVec = vld1q(pSrcCmplx); + rVec = vldrwq_gather_shifted_offset_s32(pSrcReal, strideVec); + dstVec = vqdmulhq(cmplxVec, rVec); + vst1q(pCmplxDst, dstVec); + + pSrcReal += 2; + pSrcCmplx += 4; + pCmplxDst += 4; + blkCnt --; + } + + blkCnt = (blockSizeC & 3) >> 1; + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store saturated result in 1.31 format to destination buffer */ + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_cmplx_mult_real_q31( + const q31_t * pSrcCmplx, + const q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in; /* Temporary variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; +#if defined (ARM_MATH_DSP) + /* store saturated result in 1.31 format to destination buffer */ + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); +#else + /* store result in destination buffer. */ + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + in = *pSrcReal++; +#if defined (ARM_MATH_DSP) + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); +#else + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + in = *pSrcReal++; +#if defined (ARM_MATH_DSP) + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); +#else + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + in = *pSrcReal++; +#if defined (ARM_MATH_DSP) + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); +#else + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; +#if defined (ARM_MATH_DSP) + /* store saturated result in 1.31 format to destination buffer */ + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); +#else + /* store result in destination buffer. */ + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of CmplxByRealMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/CMakeLists.txt new file mode 100644 index 00000000..12dedb4a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/CMakeLists.txt @@ -0,0 +1,41 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPController) + +include(configLib) +include(configDsp) + +add_library(CMSISDSPController STATIC) + +configLib(CMSISDSPController ${ROOT}) +configDsp(CMSISDSPController ${ROOT}) + +include(interpol) +interpol(CMSISDSPController) + +if (CONFIGTABLE AND ALLFAST) + target_compile_definitions(CMSISDSPController PUBLIC ARM_ALL_FAST_TABLES) +endif() + +target_sources(CMSISDSPController PRIVATE arm_pid_init_f32.c) +target_sources(CMSISDSPController PRIVATE arm_pid_init_q15.c) +target_sources(CMSISDSPController PRIVATE arm_pid_init_q31.c) +target_sources(CMSISDSPController PRIVATE arm_pid_reset_f32.c) +target_sources(CMSISDSPController PRIVATE arm_pid_reset_q15.c) +target_sources(CMSISDSPController PRIVATE arm_pid_reset_q31.c) + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_SIN_COS_F32) +target_sources(CMSISDSPController PRIVATE arm_sin_cos_f32.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_SIN_COS_Q31) +target_sources(CMSISDSPController PRIVATE arm_sin_cos_q31.c) +endif() + + + +### Includes +target_include_directories(CMSISDSPController PUBLIC "${DSP}/Include") + + + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c new file mode 100644 index 00000000..e406ac2e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c @@ -0,0 +1,46 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: ControllerFunctions.c + * Description: Combination of all controller function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_pid_init_f32.c" +#include "arm_pid_init_q15.c" +#include "arm_pid_init_q31.c" +#include "arm_pid_reset_f32.c" +#include "arm_pid_reset_q15.c" +#include "arm_pid_reset_q31.c" + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32) +#include "arm_sin_cos_f32.c" +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31) +#include "arm_sin_cos_q31.c" +#endif + +#endif \ No newline at end of file diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c new file mode 100644 index 00000000..384994bd --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_init_f32.c + * Description: Floating-point PID Control initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Initialization function for the floating-point PID Control. + @param[in,out] S points to an instance of the PID structure + @param[in] resetStateFlag + - value = 0: no change in state + - value = 1: reset state + @return none + + @par Details + The resetStateFlag specifies whether to set state to zero or not. \n + The function computes the structure fields: A0, A1 A2 + using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd) + also sets the state variables to all zeros. + */ + +void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag) +{ + /* Derived coefficient A0 */ + S->A0 = S->Kp + S->Ki + S->Kd; + + /* Derived coefficient A1 */ + S->A1 = (-S->Kp) - ((float32_t) 2.0f * S->Kd); + + /* Derived coefficient A2 */ + S->A2 = S->Kd; + + /* Check whether state needs reset or not */ + if (resetStateFlag) + { + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(float32_t)); + } + +} + +/** + @} end of PID group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c new file mode 100644 index 00000000..e1f510b3 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c @@ -0,0 +1,95 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_init_q15.c + * Description: Q15 PID Control initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Initialization function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID structure + @param[in] resetStateFlag + - value = 0: no change in state + - value = 1: reset state + @return none + + @par Details + The resetStateFlag specifies whether to set state to zero or not. \n + The function computes the structure fields: A0, A1 A2 + using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd) + also sets the state variables to all zeros. + */ + +void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag) +{ + +#if defined (ARM_MATH_DSP) + + /* Derived coefficient A0 */ + S->A0 = __QADD16(__QADD16(S->Kp, S->Ki), S->Kd); + + /* Derived coefficients and pack into A1 */ + +#ifndef ARM_MATH_BIG_ENDIAN + S->A1 = __PKHBT(-__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), S->Kd, 16); +#else + S->A1 = __PKHBT(S->Kd, -__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), 16); +#endif + +#else + + q31_t temp; /* to store the sum */ + + /* Derived coefficient A0 */ + temp = S->Kp + S->Ki + S->Kd; + S->A0 = (q15_t) __SSAT(temp, 16); + + /* Derived coefficients and pack into A1 */ + temp = -(S->Kd + S->Kd + S->Kp); + S->A1 = (q15_t) __SSAT(temp, 16); + S->A2 = S->Kd; + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Check whether state needs reset or not */ + if (resetStateFlag) + { + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(q15_t)); + } + +} + +/** + @} end of PID group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c new file mode 100644 index 00000000..53df5ee5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_init_q31.c + * Description: Q31 PID Control initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Initialization function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID structure + @param[in] resetStateFlag + - value = 0: no change in state + - value = 1: reset state + @return none + + @par Details + The resetStateFlag specifies whether to set state to zero or not. \n + The function computes the structure fields: A0, A1 A2 + using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd) + also sets the state variables to all zeros. + */ + +void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag) +{ + +#if defined (ARM_MATH_DSP) + + /* Derived coefficient A0 */ + S->A0 = __QADD(__QADD(S->Kp, S->Ki), S->Kd); + + /* Derived coefficient A1 */ + S->A1 = -__QADD(__QADD(S->Kd, S->Kd), S->Kp); + +#else + + q31_t temp; /* to store the sum */ + + /* Derived coefficient A0 */ + temp = clip_q63_to_q31((q63_t) S->Kp + S->Ki); + S->A0 = clip_q63_to_q31((q63_t) temp + S->Kd); + + /* Derived coefficient A1 */ + temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd); + S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp); + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Derived coefficient A2 */ + S->A2 = S->Kd; + + /* Check whether state needs reset or not */ + if (resetStateFlag) + { + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(q31_t)); + } + +} + +/** + @} end of PID group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c new file mode 100644 index 00000000..cb267adb --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c @@ -0,0 +1,54 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_reset_f32.c + * Description: Floating-point PID Control reset function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Reset function for the floating-point PID Control. + @param[in,out] S points to an instance of the floating-point PID structure + @return none + + @par Details + The function resets the state buffer to zeros. + */ + +void arm_pid_reset_f32( + arm_pid_instance_f32 * S) +{ + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(float32_t)); +} + +/** + @} end of PID group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c new file mode 100644 index 00000000..aa4076ec --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c @@ -0,0 +1,54 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_reset_q15.c + * Description: Q15 PID Control reset function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Reset function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID structure + @return none + + @par Details + The function resets the state buffer to zeros. + */ + +void arm_pid_reset_q15( + arm_pid_instance_q15 * S) +{ + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(q15_t)); +} + +/** + @} end of PID group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c new file mode 100644 index 00000000..3e9c39fe --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c @@ -0,0 +1,54 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_reset_q31.c + * Description: Q31 PID Control reset function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Reset function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID structure + @return none + + @par Details + The function resets the state buffer to zeros. + */ + +void arm_pid_reset_q31( + arm_pid_instance_q31 * S) +{ + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(q31_t)); +} + +/** + @} end of PID group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c new file mode 100644 index 00000000..e6d9d90f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c @@ -0,0 +1,146 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sin_cos_f32.c + * Description: Sine and Cosine calculation for floating-point values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupController + */ + +/** + @defgroup SinCos Sine Cosine + + Computes the trigonometric sine and cosine values using a combination of table lookup + and linear interpolation. + There are separate functions for Q31 and floating-point data types. + The input to the floating-point version is in degrees while the + fixed-point Q31 have a scaled input with the range + [-1 0.9999] mapping to [-180 +180] degrees. + + The floating point function also allows values that are out of the usual range. When this happens, the function will + take extra time to adjust the input value to the range of [-180 180]. + + The result is accurate to 5 digits after the decimal point. + + The implementation is based on table lookup using 360 values together with linear interpolation. + The steps used are: + -# Calculation of the nearest integer table index. + -# Compute the fractional portion (fract) of the input. + -# Fetch the value corresponding to \c index from sine table to \c y0 and also value from \c index+1 to \c y1. + -# Sine value is computed as *psinVal = y0 + (fract * (y1 - y0)). + -# Fetch the value corresponding to \c index from cosine table to \c y0 and also value from \c index+1 to \c y1. + -# Cosine value is computed as *pcosVal = y0 + (fract * (y1 - y0)). + */ + +/** + @addtogroup SinCos + @{ + */ + +/** + @brief Floating-point sin_cos function. + @param[in] theta input value in degrees + @param[out] pSinVal points to processed sine output + @param[out] pCosVal points to processed cosine output + @return none + */ + +void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal) +{ + float32_t fract, in; /* Temporary input, output variables */ + uint16_t indexS, indexC; /* Index variable */ + float32_t f1, f2, d1, d2; /* Two nearest output values */ + float32_t Dn, Df; + float32_t temp, findex; + + /* input x is in degrees */ + /* Scale input, divide input by 360, for cosine add 0.25 (pi/2) to read sine table */ + in = theta * 0.00277777777778f; + + if (in < 0.0f) + { + in = -in; + } + + in = in - (int32_t)in; + + /* Calculate the nearest index */ + findex = (float32_t)FAST_MATH_TABLE_SIZE * in; + indexS = ((uint16_t)findex) & 0x1ff; + indexC = (indexS + (FAST_MATH_TABLE_SIZE / 4)) & 0x1ff; + + /* Calculation of fractional value */ + fract = findex - (float32_t) indexS; + + /* Read two nearest values of input value from the cos & sin tables */ + f1 = sinTable_f32[indexC ]; + f2 = sinTable_f32[indexC+1]; + d1 = -sinTable_f32[indexS ]; + d2 = -sinTable_f32[indexS+1]; + + temp = (1.0f - fract) * f1 + fract * f2; + + Dn = 0.0122718463030f; /* delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE */ + Df = f2 - f1; /* delta between the values of the functions */ + + temp = Dn * (d1 + d2) - 2 * Df; + temp = fract * temp + (3 * Df - (d2 + 2 * d1) * Dn); + temp = fract * temp + d1 * Dn; + + /* Calculation of cosine value */ + *pCosVal = fract * temp + f1; + + /* Read two nearest values of input value from the cos & sin tables */ + f1 = sinTable_f32[indexS ]; + f2 = sinTable_f32[indexS+1]; + d1 = sinTable_f32[indexC ]; + d2 = sinTable_f32[indexC+1]; + + temp = (1.0f - fract) * f1 + fract * f2; + + Df = f2 - f1; // delta between the values of the functions + temp = Dn * (d1 + d2) - 2 * Df; + temp = fract * temp + (3 * Df - (d2 + 2 * d1) * Dn); + temp = fract * temp + d1 * Dn; + + /* Calculation of sine value */ + *pSinVal = fract * temp + f1; + + if (theta < 0.0f) + { + *pSinVal = -*pSinVal; + } +} + +/** + @} end of SinCos group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c new file mode 100644 index 00000000..990c891d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c @@ -0,0 +1,110 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sin_cos_q31.c + * Description: Cosine & Sine calculation for Q31 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupController + */ + +/** + @addtogroup SinCos + @{ + */ + +/** + @brief Q31 sin_cos function. + @param[in] theta scaled input value in degrees + @param[out] pSinVal points to processed sine output + @param[out] pCosVal points to processed cosine output + @return none + + The Q31 input value is in the range [-1 0.999999] and is mapped to a degree value in the range [-180 179]. + */ + +void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal) +{ + q31_t fract; /* Temporary input, output variables */ + uint16_t indexS, indexC; /* Index variable */ + q31_t f1, f2, d1, d2; /* Two nearest output values */ + q31_t Dn, Df; + q63_t temp; + + /* Calculate the nearest index */ + indexS = (uint32_t)theta >> CONTROLLER_Q31_SHIFT; + indexC = (indexS + 128) & 0x1ff; + + /* Calculation of fractional value */ + fract = (theta - (indexS << CONTROLLER_Q31_SHIFT)) << 8; + + /* Read two nearest values of input value from the cos & sin tables */ + f1 = sinTable_q31[indexC ]; + f2 = sinTable_q31[indexC+1]; + d1 = -sinTable_q31[indexS ]; + d2 = -sinTable_q31[indexS+1]; + + Dn = 0x1921FB5; /* delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE */ + Df = f2 - f1; /* delta between the values of the functions */ + + temp = Dn * ((q63_t)d1 + d2); + temp = temp - ((q63_t)Df << 32); + temp = (q63_t)fract * (temp >> 31); + temp = temp + ((3 * (q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1)) * Dn); + temp = (q63_t)fract * (temp >> 31); + temp = temp + (q63_t)d1 * Dn; + temp = (q63_t)fract * (temp >> 31); + + /* Calculation of cosine value */ + *pCosVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1); + + /* Read two nearest values of input value from the cos & sin tables */ + f1 = sinTable_q31[indexS ]; + f2 = sinTable_q31[indexS+1]; + d1 = sinTable_q31[indexC ]; + d2 = sinTable_q31[indexC+1]; + + Df = f2 - f1; // delta between the values of the functions + temp = Dn * ((q63_t)d1 + d2); + temp = temp - ((q63_t)Df << 32); + temp = (q63_t)fract * (temp >> 31); + temp = temp + ((3 * (q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1)) * Dn); + temp = (q63_t)fract * (temp >> 31); + temp = temp + (q63_t)d1 * Dn; + temp = (q63_t)fract * (temp >> 31); + + /* Calculation of sine value */ + *pSinVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1); +} + +/** + @} end of SinCos group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/CMakeLists.txt new file mode 100644 index 00000000..0cfd1c9f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/CMakeLists.txt @@ -0,0 +1,56 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPDistance) + +include(configLib) +include(configDsp) + +file(GLOB SRC "./*_*.c") + +add_library(CMSISDSPDistance STATIC) + +target_sources(CMSISDSPDistance PRIVATE arm_boolean_distance.c) +target_sources(CMSISDSPDistance PRIVATE arm_braycurtis_distance_f32.c) +target_sources(CMSISDSPDistance PRIVATE arm_canberra_distance_f32.c) +target_sources(CMSISDSPDistance PRIVATE arm_chebyshev_distance_f32.c) +target_sources(CMSISDSPDistance PRIVATE arm_chebyshev_distance_f64.c) +target_sources(CMSISDSPDistance PRIVATE arm_cityblock_distance_f32.c) +target_sources(CMSISDSPDistance PRIVATE arm_cityblock_distance_f64.c) +target_sources(CMSISDSPDistance PRIVATE arm_correlation_distance_f32.c) +target_sources(CMSISDSPDistance PRIVATE arm_cosine_distance_f32.c) +target_sources(CMSISDSPDistance PRIVATE arm_cosine_distance_f64.c) +target_sources(CMSISDSPDistance PRIVATE arm_dice_distance.c) +target_sources(CMSISDSPDistance PRIVATE arm_euclidean_distance_f32.c) +target_sources(CMSISDSPDistance PRIVATE arm_euclidean_distance_f64.c) +target_sources(CMSISDSPDistance PRIVATE arm_hamming_distance.c) +target_sources(CMSISDSPDistance PRIVATE arm_jaccard_distance.c) +target_sources(CMSISDSPDistance PRIVATE arm_jensenshannon_distance_f32.c) +target_sources(CMSISDSPDistance PRIVATE arm_kulsinski_distance.c) +target_sources(CMSISDSPDistance PRIVATE arm_minkowski_distance_f32.c) +target_sources(CMSISDSPDistance PRIVATE arm_rogerstanimoto_distance.c) +target_sources(CMSISDSPDistance PRIVATE arm_russellrao_distance.c) +target_sources(CMSISDSPDistance PRIVATE arm_sokalmichener_distance.c) +target_sources(CMSISDSPDistance PRIVATE arm_sokalsneath_distance.c) +target_sources(CMSISDSPDistance PRIVATE arm_yule_distance.c) + + +configLib(CMSISDSPDistance ${ROOT}) +configDsp(CMSISDSPDistance ${ROOT}) + +### Includes +target_include_directories(CMSISDSPDistance PUBLIC "${DSP}/Include") +target_include_directories(CMSISDSPDistance PRIVATE ".") + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPDistance PRIVATE arm_braycurtis_distance_f16.c) +target_sources(CMSISDSPDistance PRIVATE arm_canberra_distance_f16.c) +target_sources(CMSISDSPDistance PRIVATE arm_chebyshev_distance_f16.c) +target_sources(CMSISDSPDistance PRIVATE arm_cityblock_distance_f16.c) +target_sources(CMSISDSPDistance PRIVATE arm_correlation_distance_f16.c) +target_sources(CMSISDSPDistance PRIVATE arm_cosine_distance_f16.c) +target_sources(CMSISDSPDistance PRIVATE arm_euclidean_distance_f16.c) +target_sources(CMSISDSPDistance PRIVATE arm_jensenshannon_distance_f16.c) +target_sources(CMSISDSPDistance PRIVATE arm_minkowski_distance_f16.c) +endif() + + \ No newline at end of file diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctions.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctions.c new file mode 100644 index 00000000..0abcbc5f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctions.c @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: BayesFunctions.c + * Description: Combination of all distance function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_boolean_distance.c" +#include "arm_braycurtis_distance_f32.c" +#include "arm_canberra_distance_f32.c" +#include "arm_chebyshev_distance_f32.c" +#include "arm_chebyshev_distance_f64.c" +#include "arm_cityblock_distance_f32.c" +#include "arm_cityblock_distance_f64.c" +#include "arm_correlation_distance_f32.c" +#include "arm_cosine_distance_f32.c" +#include "arm_cosine_distance_f64.c" +#include "arm_dice_distance.c" +#include "arm_euclidean_distance_f32.c" +#include "arm_euclidean_distance_f64.c" +#include "arm_hamming_distance.c" +#include "arm_jaccard_distance.c" +#include "arm_jensenshannon_distance_f32.c" +#include "arm_kulsinski_distance.c" +#include "arm_minkowski_distance_f32.c" +#include "arm_rogerstanimoto_distance.c" +#include "arm_russellrao_distance.c" +#include "arm_sokalmichener_distance.c" +#include "arm_sokalsneath_distance.c" +#include "arm_yule_distance.c" diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctionsF16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctionsF16.c new file mode 100644 index 00000000..a0be2d44 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctionsF16.c @@ -0,0 +1,36 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: DistanceFunctions.c + * Description: Combination of all distance function f16 source files. + * + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_braycurtis_distance_f16.c" +#include "arm_canberra_distance_f16.c" +#include "arm_chebyshev_distance_f16.c" +#include "arm_cityblock_distance_f16.c" +#include "arm_correlation_distance_f16.c" +#include "arm_cosine_distance_f16.c" +#include "arm_euclidean_distance_f16.c" +#include "arm_jensenshannon_distance_f16.c" +#include "arm_minkowski_distance_f16.c" + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance.c new file mode 100644 index 00000000..57873b1e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance.c @@ -0,0 +1,80 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_linear_init_f32.c + * Description: SVM Linear Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + + +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +#endif + + +#define TT +#define TF +#define FT +#define EXT _TT_TF_FT +#include "arm_boolean_distance_template.h" + +#undef TT +#undef FF +#undef TF +#undef FT +#undef EXT +#define TF +#define FT +#define EXT _TF_FT +#include "arm_boolean_distance_template.h" + +#undef TT +#undef FF +#undef TF +#undef FT +#undef EXT +#define TT +#define FF +#define TF +#define FT +#define EXT _TT_FF_TF_FT +#include "arm_boolean_distance_template.h" + +#undef TT +#undef FF +#undef TF +#undef FT +#undef EXT +#define TT +#define EXT _TT +#include "arm_boolean_distance_template.h" + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance_template.h b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance_template.h new file mode 100644 index 00000000..eb2e2af9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance_template.h @@ -0,0 +1,551 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_boolean_distance.c + * Description: Templates for boolean distances + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + + + +/** + * @defgroup DISTANCEF Distance Functions + * + * Computes Distances between vectors. + * + * Distance functions are useful in a lot of algorithms. + * + */ + + +/** + * @addtogroup DISTANCEF + * @{ + */ + + + + +#define _FUNC(A,B) A##B + +#define FUNC(EXT) _FUNC(arm_boolean_distance, EXT) + +/** + * @brief Elements of boolean distances + * + * Different values which are used to compute boolean distances + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return None + * + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_common_tables.h" + +void FUNC(EXT)(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools +#ifdef TT + , uint32_t *cTT +#endif +#ifdef FF + , uint32_t *cFF +#endif +#ifdef TF + , uint32_t *cTF +#endif +#ifdef FT + , uint32_t *cFT +#endif + ) +{ + +#ifdef TT + uint32_t _ctt=0; +#endif +#ifdef FF + uint32_t _cff=0; +#endif +#ifdef TF + uint32_t _ctf=0; +#endif +#ifdef FT + uint32_t _cft=0; +#endif + uint32_t a, b, ba, bb; + int shift; + const uint8_t *pA8 = (const uint8_t *) pA; + const uint8_t *pB8 = (const uint8_t *) pB; + + /* handle vector blocks */ + uint32_t blkCnt = numberOfBools / 128; + + + + while (blkCnt > 0U) { + uint8x16_t vecA = vld1q((const uint8_t *) pA8); + uint8x16_t vecB = vld1q((const uint8_t *) pB8); + +#ifdef TT + uint8x16_t vecTT = vecA & vecB; + vecTT = vldrbq_gather_offset_u8(hwLUT, vecTT); + _ctt += vaddvq(vecTT); +#endif +#ifdef FF + uint8x16_t vecFF = vmvnq(vecA) & vmvnq(vecB); + vecFF = vldrbq_gather_offset_u8(hwLUT, vecFF); + _cff += vaddvq(vecFF); +#endif +#ifdef TF + uint8x16_t vecTF = vecA & vmvnq(vecB); + vecTF = vldrbq_gather_offset_u8(hwLUT, vecTF); + _ctf += vaddvq(vecTF); +#endif +#ifdef FT + uint8x16_t vecFT = vmvnq(vecA) & vecB; + vecFT = vldrbq_gather_offset_u8(hwLUT, vecFT); + _cft += vaddvq(vecFT); +#endif + + pA8 += 16; + pB8 += 16; + blkCnt--; + + } + + pA = (const uint32_t *)pA8; + pB = (const uint32_t *)pB8; + + blkCnt = numberOfBools & 0x7F; + while(blkCnt >= 32) + { + a = *pA++; + b = *pB++; + shift = 0; + while(shift < 32) + { + ba = a & 1; + bb = b & 1; + a = a >> 1; + b = b >> 1; + +#ifdef TT + _ctt += (ba && bb); +#endif +#ifdef FF + _cff += ((1 ^ ba) && (1 ^ bb)); +#endif +#ifdef TF + _ctf += (ba && (1 ^ bb)); +#endif +#ifdef FT + _cft += ((1 ^ ba) && bb); +#endif + shift ++; + } + + blkCnt -= 32; + } + + a = *pA++; + b = *pB++; + + a = a >> (32 - blkCnt); + b = b >> (32 - blkCnt); + + while(blkCnt > 0) + { + ba = a & 1; + bb = b & 1; + a = a >> 1; + + b = b >> 1; +#ifdef TT + _ctt += (ba && bb); +#endif +#ifdef FF + _cff += ((1 ^ ba) && (1 ^ bb)); +#endif +#ifdef TF + _ctf += (ba && (1 ^ bb)); +#endif +#ifdef FT + _cft += ((1 ^ ba) && bb); +#endif + blkCnt --; + } + +#ifdef TT + *cTT = _ctt; +#endif +#ifdef FF + *cFF = _cff; +#endif +#ifdef TF + *cTF = _ctf; +#endif +#ifdef FT + *cFT = _cft; +#endif +} + +#else +#if defined(ARM_MATH_NEON) + + +void FUNC(EXT)(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools +#ifdef TT + , uint32_t *cTT +#endif +#ifdef FF + , uint32_t *cFF +#endif +#ifdef TF + , uint32_t *cTF +#endif +#ifdef FT + , uint32_t *cFT +#endif + ) +{ +#ifdef TT + uint32_t _ctt=0; +#endif +#ifdef FF + uint32_t _cff=0; +#endif +#ifdef TF + uint32_t _ctf=0; +#endif +#ifdef FT + uint32_t _cft=0; +#endif + uint32_t nbBoolBlock; + uint32_t a,b,ba,bb; + int shift; + uint32x4_t aV, bV; +#ifdef TT + uint32x4_t cttV; +#endif +#ifdef FF + uint32x4_t cffV; +#endif +#ifdef TF + uint32x4_t ctfV; +#endif +#ifdef FT + uint32x4_t cftV; +#endif + uint8x16_t tmp; + uint16x8_t tmp2; + uint32x4_t tmp3; + uint64x2_t tmp4; +#ifdef TT + uint64x2_t tmp4tt; +#endif +#ifdef FF + uint64x2_t tmp4ff; +#endif +#ifdef TF + uint64x2_t tmp4tf; +#endif +#ifdef FT + uint64x2_t tmp4ft; +#endif + +#ifdef TT + tmp4tt = vdupq_n_u64(0); +#endif +#ifdef FF + tmp4ff = vdupq_n_u64(0); +#endif +#ifdef TF + tmp4tf = vdupq_n_u64(0); +#endif +#ifdef FT + tmp4ft = vdupq_n_u64(0); +#endif + + nbBoolBlock = numberOfBools >> 7; + while(nbBoolBlock > 0) + { + aV = vld1q_u32(pA); + bV = vld1q_u32(pB); + pA += 4; + pB += 4; + +#ifdef TT + cttV = vandq_u32(aV,bV); +#endif +#ifdef FF + cffV = vandq_u32(vmvnq_u32(aV),vmvnq_u32(bV)); +#endif +#ifdef TF + ctfV = vandq_u32(aV,vmvnq_u32(bV)); +#endif +#ifdef FT + cftV = vandq_u32(vmvnq_u32(aV),bV); +#endif + +#ifdef TT + tmp = vcntq_u8(vreinterpretq_u8_u32(cttV)); + tmp2 = vpaddlq_u8(tmp); + tmp3 = vpaddlq_u16(tmp2); + tmp4 = vpaddlq_u32(tmp3); + tmp4tt = vaddq_u64(tmp4tt, tmp4); +#endif + +#ifdef FF + tmp = vcntq_u8(vreinterpretq_u8_u32(cffV)); + tmp2 = vpaddlq_u8(tmp); + tmp3 = vpaddlq_u16(tmp2); + tmp4 = vpaddlq_u32(tmp3); + tmp4ff = vaddq_u64(tmp4ff, tmp4); +#endif + +#ifdef TF + tmp = vcntq_u8(vreinterpretq_u8_u32(ctfV)); + tmp2 = vpaddlq_u8(tmp); + tmp3 = vpaddlq_u16(tmp2); + tmp4 = vpaddlq_u32(tmp3); + tmp4tf = vaddq_u64(tmp4tf, tmp4); +#endif + +#ifdef FT + tmp = vcntq_u8(vreinterpretq_u8_u32(cftV)); + tmp2 = vpaddlq_u8(tmp); + tmp3 = vpaddlq_u16(tmp2); + tmp4 = vpaddlq_u32(tmp3); + tmp4ft = vaddq_u64(tmp4ft, tmp4); +#endif + + + nbBoolBlock --; + } + +#ifdef TT + _ctt += vgetq_lane_u64(tmp4tt, 0) + vgetq_lane_u64(tmp4tt, 1); +#endif +#ifdef FF + _cff +=vgetq_lane_u64(tmp4ff, 0) + vgetq_lane_u64(tmp4ff, 1); +#endif +#ifdef TF + _ctf += vgetq_lane_u64(tmp4tf, 0) + vgetq_lane_u64(tmp4tf, 1); +#endif +#ifdef FT + _cft += vgetq_lane_u64(tmp4ft, 0) + vgetq_lane_u64(tmp4ft, 1); +#endif + + nbBoolBlock = numberOfBools & 0x7F; + while(nbBoolBlock >= 32) + { + a = *pA++; + b = *pB++; + shift = 0; + while(shift < 32) + { + ba = a & 1; + bb = b & 1; + a = a >> 1; + b = b >> 1; + +#ifdef TT + _ctt += (ba && bb); +#endif +#ifdef FF + _cff += ((1 ^ ba) && (1 ^ bb)); +#endif +#ifdef TF + _ctf += (ba && (1 ^ bb)); +#endif +#ifdef FT + _cft += ((1 ^ ba) && bb); +#endif + shift ++; + } + + nbBoolBlock -= 32; + } + + a = *pA++; + b = *pB++; + + a = a >> (32 - nbBoolBlock); + b = b >> (32 - nbBoolBlock); + + while(nbBoolBlock > 0) + { + ba = a & 1; + bb = b & 1; + a = a >> 1; + + b = b >> 1; +#ifdef TT + _ctt += (ba && bb); +#endif +#ifdef FF + _cff += ((1 ^ ba) && (1 ^ bb)); +#endif +#ifdef TF + _ctf += (ba && (1 ^ bb)); +#endif +#ifdef FT + _cft += ((1 ^ ba) && bb); +#endif + nbBoolBlock --; + } + +#ifdef TT + *cTT = _ctt; +#endif +#ifdef FF + *cFF = _cff; +#endif +#ifdef TF + *cTF = _ctf; +#endif +#ifdef FT + *cFT = _cft; +#endif +} + +#else + +void FUNC(EXT)(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools +#ifdef TT + , uint32_t *cTT +#endif +#ifdef FF + , uint32_t *cFF +#endif +#ifdef TF + , uint32_t *cTF +#endif +#ifdef FT + , uint32_t *cFT +#endif + ) +{ + +#ifdef TT + uint32_t _ctt=0; +#endif +#ifdef FF + uint32_t _cff=0; +#endif +#ifdef TF + uint32_t _ctf=0; +#endif +#ifdef FT + uint32_t _cft=0; +#endif + uint32_t a,b,ba,bb; + int shift; + + while(numberOfBools >= 32) + { + a = *pA++; + b = *pB++; + shift = 0; + while(shift < 32) + { + ba = a & 1; + bb = b & 1; + a = a >> 1; + b = b >> 1; +#ifdef TT + _ctt += (ba && bb); +#endif +#ifdef FF + _cff += ((1 ^ ba) && (1 ^ bb)); +#endif +#ifdef TF + _ctf += (ba && (1 ^ bb)); +#endif +#ifdef FT + _cft += ((1 ^ ba) && bb); +#endif + shift ++; + } + + numberOfBools -= 32; + } + + a = *pA++; + b = *pB++; + + a = a >> (32 - numberOfBools); + b = b >> (32 - numberOfBools); + + while(numberOfBools > 0) + { + ba = a & 1; + bb = b & 1; + a = a >> 1; + b = b >> 1; + +#ifdef TT + _ctt += (ba && bb); +#endif +#ifdef FF + _cff += ((1 ^ ba) && (1 ^ bb)); +#endif +#ifdef TF + _ctf += (ba && (1 ^ bb)); +#endif +#ifdef FT + _cft += ((1 ^ ba) && bb); +#endif + numberOfBools --; + } + +#ifdef TT + *cTT = _ctt; +#endif +#ifdef FF + *cFF = _cff; +#endif +#ifdef TF + *cTF = _ctf; +#endif +#ifdef FT + *cFT = _cft; +#endif +} +#endif +#endif /* defined(ARM_MATH_MVEI) */ + + +/** + * @} end of DISTANCEF group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_braycurtis_distance_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_braycurtis_distance_f16.c new file mode 100644 index 00000000..be5537ef --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_braycurtis_distance_f16.c @@ -0,0 +1,158 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_braycurtis_distance_f16.c + * Description: Bray-Curtis distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + * @ingroup groupDistance + */ + +/** + * @defgroup FloatDist Float Distances + * + * Distances between two vectors of float values. + */ + +/** + @ingroup FloatDist + */ + +/** + @defgroup braycurtis Bray-Curtis distance + + Bray-Curtis distance between two vectors + */ + +/** + @addtogroup braycurtis + @{ + */ + + +/** + * @brief Bray-Curtis distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +float16_t arm_braycurtis_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 accumDiff = 0.0f, accumSum = 0.0f; + uint32_t blkCnt; + f16x8_t a, b, c, accumDiffV, accumSumV; + + + accumDiffV = vdupq_n_f16(0.0f); + accumSumV = vdupq_n_f16(0.0f); + + blkCnt = blockSize >> 3; + while (blkCnt > 0) { + a = vld1q(pA); + b = vld1q(pB); + + c = vabdq(a, b); + accumDiffV = vaddq(accumDiffV, c); + + c = vaddq_f16(a, b); + c = vabsq_f16(c); + accumSumV = vaddq(accumSumV, c); + + pA += 8; + pB += 8; + blkCnt--; + } + + blkCnt = blockSize & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + a = vldrhq_z_f16(pA, p0); + b = vldrhq_z_f16(pB, p0); + + c = vabdq(a, b); + accumDiffV = vaddq_m(accumDiffV, accumDiffV, c, p0); + + c = vaddq_f16(a, b); + c = vabsq_f16(c); + accumSumV = vaddq_m(accumSumV, accumSumV, c, p0); + } + + accumDiff = vecAddAcrossF16Mve(accumDiffV); + accumSum = vecAddAcrossF16Mve(accumSumV); + + /* + It is assumed that accumSum is not zero. Since it is the sum of several absolute + values it would imply that all of them are zero. It is very unlikely for long vectors. + */ + return (accumDiff / accumSum); +} +#else + +float16_t arm_braycurtis_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 accumDiff=0.0f16, accumSum=0.0f16, tmpA, tmpB; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + accumDiff += (_Float16)fabsf((float32_t)((_Float16)tmpA - (_Float16)tmpB)); + accumSum += (_Float16)fabsf((float32_t)((_Float16)tmpA + (_Float16)tmpB)); + blockSize --; + } + /* + + It is assumed that accumSum is not zero. Since it is the sum of several absolute + values it would imply that all of them are zero. It is very unlikely for long vectors. + + */ + return(accumDiff / accumSum); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of braycurtis group + */ + + + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_braycurtis_distance_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_braycurtis_distance_f32.c new file mode 100644 index 00000000..ae13c358 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_braycurtis_distance_f32.c @@ -0,0 +1,187 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_braycurtis_distance_f32.c + * Description: Bray-Curtis distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +/** + @addtogroup braycurtis + @{ + */ + + +/** + * @brief Bray-Curtis distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accumDiff = 0.0f, accumSum = 0.0f; + uint32_t blkCnt; + f32x4_t a, b, c, accumDiffV, accumSumV; + + + accumDiffV = vdupq_n_f32(0.0f); + accumSumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while (blkCnt > 0) { + a = vld1q(pA); + b = vld1q(pB); + + c = vabdq(a, b); + accumDiffV = vaddq(accumDiffV, c); + + c = vaddq_f32(a, b); + c = vabsq_f32(c); + accumSumV = vaddq(accumSumV, c); + + pA += 4; + pB += 4; + blkCnt--; + } + + blkCnt = blockSize & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + + a = vldrwq_z_f32(pA, p0); + b = vldrwq_z_f32(pB, p0); + + c = vabdq(a, b); + accumDiffV = vaddq_m(accumDiffV, accumDiffV, c, p0); + + c = vaddq_f32(a, b); + c = vabsq_f32(c); + accumSumV = vaddq_m(accumSumV, accumSumV, c, p0); + } + + accumDiff = vecAddAcrossF32Mve(accumDiffV); + accumSum = vecAddAcrossF32Mve(accumSumV); + + /* + It is assumed that accumSum is not zero. Since it is the sum of several absolute + values it would imply that all of them are zero. It is very unlikely for long vectors. + */ + return (accumDiff / accumSum); +} +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accumDiff=0.0f, accumSum=0.0f; + uint32_t blkCnt; + float32x4_t a,b,c,accumDiffV, accumSumV; + float32x2_t accumV2; + + accumDiffV = vdupq_n_f32(0.0f); + accumSumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + a = vld1q_f32(pA); + b = vld1q_f32(pB); + + c = vabdq_f32(a,b); + accumDiffV = vaddq_f32(accumDiffV,c); + + c = vaddq_f32(a,b); + c = vabsq_f32(c); + accumSumV = vaddq_f32(accumSumV,c); + + pA += 4; + pB += 4; + blkCnt --; + } + accumV2 = vpadd_f32(vget_low_f32(accumDiffV),vget_high_f32(accumDiffV)); + accumDiff = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + accumV2 = vpadd_f32(vget_low_f32(accumSumV),vget_high_f32(accumSumV)); + accumSum = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + accumDiff += fabsf(*pA - *pB); + accumSum += fabsf(*pA++ + *pB++); + blkCnt --; + } + /* + + It is assumed that accumSum is not zero. Since it is the sum of several absolute + values it would imply that all of them are zero. It is very unlikely for long vectors. + + */ + return(accumDiff / accumSum); +} + +#else +float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accumDiff=0.0f, accumSum=0.0f, tmpA, tmpB; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + accumDiff += fabsf(tmpA - tmpB); + accumSum += fabsf(tmpA + tmpB); + blockSize --; + } + /* + + It is assumed that accumSum is not zero. Since it is the sum of several absolute + values it would imply that all of them are zero. It is very unlikely for long vectors. + + */ + return(accumDiff / accumSum); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of braycurtis group + */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_canberra_distance_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_canberra_distance_f16.c new file mode 100644 index 00000000..bcefc919 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_canberra_distance_f16.c @@ -0,0 +1,171 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_canberra_distance_f16.c + * Description: Canberra distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup Canberra Canberra distance + + Canberra distance + */ + + +/** + @addtogroup Canberra + @{ + */ + + +/** + * @brief Canberra distance between two vectors + * + * This function may divide by zero when samples pA[i] and pB[i] are both zero. + * The result of the computation will be correct. So the division per zero may be + * ignored. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math_f16.h" + +float16_t arm_canberra_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 accum = 0.0f16; + uint32_t blkCnt; + f16x8_t a, b, c, accumV; + + accumV = vdupq_n_f16(0.0f); + + blkCnt = blockSize >> 3; + while (blkCnt > 0) { + a = vld1q(pA); + b = vld1q(pB); + + c = vabdq(a, b); + + a = vabsq(a); + b = vabsq(b); + a = vaddq(a, b); + + /* + * May divide by zero when a and b have both the same lane at zero. + */ + a = vrecip_hiprec_f16(a); + + /* + * Force result of a division by 0 to 0. It the behavior of the + * sklearn canberra function. + */ + a = vdupq_m_n_f16(a, 0.0f, vcmpeqq(a, 0.0f)); + c = vmulq(c, a); + accumV = vaddq(accumV, c); + + pA += 8; + pB += 8; + blkCnt--; + } + + blkCnt = blockSize & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + a = vldrhq_z_f16(pA, p0); + b = vldrhq_z_f16(pB, p0); + + c = vabdq(a, b); + + a = vabsq(a); + b = vabsq(b); + a = vaddq(a, b); + + /* + * May divide by zero when a and b have both the same lane at zero. + */ + a = vrecip_hiprec_f16(a); + + /* + * Force result of a division by 0 to 0. It the behavior of the + * sklearn canberra function. + */ + a = vdupq_m_n_f16(a, 0.0f, vcmpeqq(a, 0.0f)); + c = vmulq(c, a); + accumV = vaddq_m(accumV, accumV, c, p0); + } + + accum = vecAddAcrossF16Mve(accumV); + + return (accum); +} + + +#else +float16_t arm_canberra_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 accum=0.0f, tmpA, tmpB,diff,sum; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + + diff = fabsf((float32_t)((_Float16)tmpA - (_Float16)tmpB)); + sum = (_Float16)fabsf((float32_t)tmpA) + (_Float16)fabsf((float32_t)tmpB); + if (((_Float16)tmpA != 0.0f16) || ((_Float16)tmpB != 0.0f16)) + { + accum += ((_Float16)diff / (_Float16)sum); + } + blockSize --; + } + return(accum); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Canberra group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_canberra_distance_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_canberra_distance_f32.c new file mode 100644 index 00000000..c786c045 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_canberra_distance_f32.c @@ -0,0 +1,222 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_canberra_distance_f32.c + * Description: Canberra distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup Canberra + @{ + */ + + +/** + * @brief Canberra distance between two vectors + * + * This function may divide by zero when samples pA[i] and pB[i] are both zero. + * The result of the computation will be correct. So the division per zero may be + * ignored. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum = 0.0f; + uint32_t blkCnt; + f32x4_t a, b, c, accumV; + + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while (blkCnt > 0) { + a = vld1q(pA); + b = vld1q(pB); + + c = vabdq(a, b); + + a = vabsq(a); + b = vabsq(b); + a = vaddq(a, b); + + /* + * May divide by zero when a and b have both the same lane at zero. + */ + a = vrecip_medprec_f32(a); + + /* + * Force result of a division by 0 to 0. It the behavior of the + * sklearn canberra function. + */ + a = vdupq_m_n_f32(a, 0.0f, vcmpeqq(a, 0.0f)); + c = vmulq(c, a); + accumV = vaddq(accumV, c); + + pA += 4; + pB += 4; + blkCnt--; + } + + blkCnt = blockSize & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + + a = vldrwq_z_f32(pA, p0); + b = vldrwq_z_f32(pB, p0); + + c = vabdq(a, b); + + a = vabsq(a); + b = vabsq(b); + a = vaddq(a, b); + + /* + * May divide by zero when a and b have both the same lane at zero. + */ + a = vrecip_medprec_f32(a); + + /* + * Force result of a division by 0 to 0. It the behavior of the + * sklearn canberra function. + */ + a = vdupq_m_n_f32(a, 0.0f, vcmpeqq(a, 0.0f)); + c = vmulq(c, a); + accumV = vaddq_m(accumV, accumV, c, p0); + } + + accum = vecAddAcrossF32Mve(accumV); + + return (accum); +} + +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum=0.0f, tmpA, tmpB,diff,sum; + uint32_t blkCnt; + float32x4_t a,b,c,accumV; + float32x2_t accumV2; + uint32x4_t isZeroV; + float32x4_t zeroV = vdupq_n_f32(0.0f); + + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + a = vld1q_f32(pA); + b = vld1q_f32(pB); + + c = vabdq_f32(a,b); + + a = vabsq_f32(a); + b = vabsq_f32(b); + a = vaddq_f32(a,b); + isZeroV = vceqq_f32(a,zeroV); + + /* + * May divide by zero when a and b have both the same lane at zero. + */ + a = vinvq_f32(a); + + /* + * Force result of a division by 0 to 0. It the behavior of the + * sklearn canberra function. + */ + a = vreinterpretq_f32_s32(vbicq_s32(vreinterpretq_s32_f32(a),vreinterpretq_s32_u32(isZeroV))); + c = vmulq_f32(c,a); + accumV = vaddq_f32(accumV,c); + + pA += 4; + pB += 4; + blkCnt --; + } + accumV2 = vpadd_f32(vget_low_f32(accumV),vget_high_f32(accumV)); + accum = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + tmpA = *pA++; + tmpB = *pB++; + + diff = fabsf(tmpA - tmpB); + sum = fabsf(tmpA) + fabsf(tmpB); + if ((tmpA != 0.0f) || (tmpB != 0.0f)) + { + accum += (diff / sum); + } + blkCnt --; + } + return(accum); +} + +#else +float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum=0.0f, tmpA, tmpB,diff,sum; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + + diff = fabsf(tmpA - tmpB); + sum = fabsf(tmpA) + fabsf(tmpB); + if ((tmpA != 0.0f) || (tmpB != 0.0f)) + { + accum += (diff / sum); + } + blockSize --; + } + return(accum); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Canberra group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f16.c new file mode 100644 index 00000000..8dec141f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f16.c @@ -0,0 +1,146 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_chebyshev_distance_f16.c + * Description: Chebyshev distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup Chebyshev Chebyshev distance + + Chebyshev distance + */ + +/** + @addtogroup Chebyshev + @{ + */ + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +float16_t arm_chebyshev_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + f16x8_t vecA, vecB; + f16x8_t vecDiff = vdupq_n_f16(0.0); + float16_t maxValue = 0.0f16; + + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) { + vecA = vld1q(pA); + pA += 8; + vecB = vld1q(pB); + pB += 8; + /* + * update per-lane max. + */ + vecDiff = vmaxnmaq(vsubq(vecA, vecB), vecDiff); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecA = vldrhq_z_f16(pA, p0); + vecB = vldrhq_z_f16(pB, p0); + + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + vecDiff = vmaxnmaq_m(vecDiff, vsubq(vecA, vecB), p0); + } + /* + * Get max value across the vector + */ + return vmaxnmavq(maxValue, vecDiff); +} + +#else +float16_t arm_chebyshev_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 diff=0.0f, maxVal,tmpA, tmpB; + + tmpA = *pA++; + tmpB = *pB++; + diff = (_Float16)fabsf((float32_t)((_Float16)tmpA - (_Float16)tmpB)); + maxVal = diff; + blockSize--; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + diff = (_Float16)fabsf((float32_t)((_Float16)tmpA - (_Float16)tmpB)); + if ((_Float16)diff > (_Float16)maxVal) + { + maxVal = diff; + } + blockSize --; + } + + return(maxVal); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Chebyshev group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f32.c new file mode 100644 index 00000000..41da72d7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f32.c @@ -0,0 +1,213 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_chebyshev_distance_f32.c + * Description: Chebyshev distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup Chebyshev + @{ + */ + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + f32x4_t vecA, vecB; + f32x4_t vecDiff = vdupq_n_f32(0.0); + float32_t maxValue = 0.0; + + + blkCnt = blockSize >> 2; + while (blkCnt > 0U) { + vecA = vld1q(pA); + pA += 4; + vecB = vld1q(pB); + pB += 4; + /* + * update per-lane max. + */ + vecDiff = vmaxnmaq(vsubq(vecA, vecB), vecDiff); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecA = vldrwq_z_f32(pA, p0); + vecB = vldrwq_z_f32(pB, p0); + + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + vecDiff = vmaxnmaq_m(vecDiff, vsubq(vecA, vecB), p0); + } + /* + * Get max value across the vector + */ + return vmaxnmavq(maxValue, vecDiff); +} + +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t diff=0.0f, maxVal=0.0f, tmpA, tmpB; + uint32_t blkCnt; + float32x4_t a,b,diffV, maxValV; + float32x2_t maxValV2; + + if (blockSize <= 3) + { + tmpA = *pA++; + tmpB = *pB++; + diff = fabsf(tmpA - tmpB); + maxVal = diff; + blockSize--; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + diff = fabsf(tmpA - tmpB); + if (diff > maxVal) + { + maxVal = diff; + } + blockSize --; + } + } + else + { + + a = vld1q_f32(pA); + b = vld1q_f32(pB); + pA += 4; + pB += 4; + + diffV = vabdq_f32(a,b); + + blockSize -= 4; + + maxValV = diffV; + + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + a = vld1q_f32(pA); + b = vld1q_f32(pB); + + diffV = vabdq_f32(a,b); + maxValV = vmaxq_f32(maxValV, diffV); + + pA += 4; + pB += 4; + blkCnt --; + } + maxValV2 = vpmax_f32(vget_low_f32(maxValV),vget_high_f32(maxValV)); + maxValV2 = vpmax_f32(maxValV2,maxValV2); + maxVal = vget_lane_f32(maxValV2,0); + + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + tmpA = *pA++; + tmpB = *pB++; + diff = fabsf(tmpA - tmpB); + if (diff > maxVal) + { + maxVal = diff; + } + blkCnt --; + } + } + return(maxVal); +} + +#else +float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t diff=0.0f, maxVal,tmpA, tmpB; + + tmpA = *pA++; + tmpB = *pB++; + diff = fabsf(tmpA - tmpB); + maxVal = diff; + blockSize--; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + diff = fabsf(tmpA - tmpB); + if (diff > maxVal) + { + maxVal = diff; + } + blockSize --; + } + + return(maxVal); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Chebyshev group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f64.c new file mode 100644 index 00000000..899159dd --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f64.c @@ -0,0 +1,76 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_chebyshev_distance_f64.c + * Description: Chebyshev distance between two vectors + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup Chebyshev + @{ + */ + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float64_t arm_chebyshev_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize) +{ + float64_t diff=0., maxVal,tmpA, tmpB; + + tmpA = *pA++; + tmpB = *pB++; + diff = fabs(tmpA - tmpB); + maxVal = diff; + blockSize--; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + diff = fabs(tmpA - tmpB); + if (diff > maxVal) + { + maxVal = diff; + } + blockSize --; + } + + return(maxVal); +} + +/** + * @} end of Chebyshev group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f16.c new file mode 100644 index 00000000..44b3bdfe --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f16.c @@ -0,0 +1,128 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cityblock_distance_f16.c + * Description: Cityblock (Manhattan) distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup Manhattan Cityblock (Manhattan) distance + + Cityblock (Manhattan) distance + */ + +/** + @addtogroup Manhattan + @{ + */ + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +float16_t arm_cityblock_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; + f16x8_t a, b, accumV, tempV; + + accumV = vdupq_n_f16(0.0f); + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + tempV = vabdq(a, b); + accumV = vaddq(accumV, tempV); + + pA += 8; + pB += 8; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + a = vldrhq_z_f16(pA, p0); + b = vldrhq_z_f16(pB, p0); + + tempV = vabdq(a, b); + accumV = vaddq_m(accumV, accumV, tempV, p0); + } + + return vecAddAcrossF16Mve(accumV); +} + +#else +float16_t arm_cityblock_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 accum,tmpA, tmpB; + + accum = 0.0f16; + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + accum += (_Float16)fabsf((float32_t)((_Float16)tmpA - (_Float16)tmpB)); + + blockSize --; + } + + return(accum); +} +#endif + +/** + * @} end of Manhattan group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f32.c new file mode 100644 index 00000000..08d406a2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f32.c @@ -0,0 +1,157 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cityblock_distance_f32.c + * Description: Cityblock (Manhattan) distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + +/** + @addtogroup Manhattan + @{ + */ + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; + f32x4_t a, b, accumV, tempV; + + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + tempV = vabdq(a, b); + accumV = vaddq(accumV, tempV); + + pA += 4; + pB += 4; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + + a = vldrwq_z_f32(pA, p0); + b = vldrwq_z_f32(pB, p0); + + tempV = vabdq(a, b); + accumV = vaddq_m(accumV, accumV, tempV, p0); + } + + return vecAddAcrossF32Mve(accumV); +} + +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum=0.0f, tmpA, tmpB; + uint32_t blkCnt; + float32x4_t a,b,accumV, tempV; + float32x2_t accumV2; + + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + a = vld1q_f32(pA); + b = vld1q_f32(pB); + + tempV = vabdq_f32(a,b); + accumV = vaddq_f32(accumV, tempV); + + pA += 4; + pB += 4; + blkCnt --; + } + accumV2 = vpadd_f32(vget_low_f32(accumV),vget_high_f32(accumV)); + accumV2 = vpadd_f32(accumV2,accumV2); + accum = vget_lane_f32(accumV2,0); + + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + tmpA = *pA++; + tmpB = *pB++; + accum += fabsf(tmpA - tmpB); + + blkCnt --; + } + return(accum); +} + +#else +float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum,tmpA, tmpB; + + accum = 0.0f; + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + accum += fabsf(tmpA - tmpB); + + blockSize --; + } + + return(accum); +} +#endif +#endif + +/** + * @} end of Manhattan group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f64.c new file mode 100644 index 00000000..46c0a6df --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f64.c @@ -0,0 +1,67 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cityblock_distance_f64.c + * Description: Cityblock (Manhattan) distance between two vectors + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + +/** + @addtogroup Manhattan + @{ + */ + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float64_t arm_cityblock_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize) +{ + float64_t accum,tmpA, tmpB; + + accum = 0.; + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + accum += fabs(tmpA - tmpB); + + blockSize --; + } + + return(accum); +} + +/** + * @} end of Manhattan group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_correlation_distance_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_correlation_distance_f16.c new file mode 100644 index 00000000..7517cece --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_correlation_distance_f16.c @@ -0,0 +1,99 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlation_distance_f16.c + * Description: Correlation distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + + +/** + @ingroup FloatDist + */ + +/** + @defgroup Correlation Correlation distance + + Correlation distance + */ + +/** + @addtogroup Correlation + @{ + */ + + +/** + * @brief Correlation distance between two vectors + * + * The input vectors are modified in place ! + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float16_t arm_correlation_distance_f16(float16_t *pA,float16_t *pB, uint32_t blockSize) +{ + float16_t ma,mb,pwra,pwrb,dot,tmp; + + arm_mean_f16(pA, blockSize, &ma); + arm_mean_f16(pB, blockSize, &mb); + + arm_offset_f16(pA, -(_Float16)ma, pA, blockSize); + arm_offset_f16(pB, -(_Float16)mb, pB, blockSize); + + arm_power_f16(pA, blockSize, &pwra); + arm_power_f16(pB, blockSize, &pwrb); + + arm_dot_prod_f16(pA,pB,blockSize,&dot); + + dot = (_Float16)dot / (_Float16)blockSize; + pwra = (_Float16)pwra / (_Float16)blockSize; + pwrb = (_Float16)pwrb / (_Float16)blockSize; + + arm_sqrt_f16((_Float16)pwra * (_Float16)pwrb,&tmp); + + return(1.0f16 - (_Float16)dot / (_Float16)tmp); + + +} + + + +/** + * @} end of Correlation group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_correlation_distance_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_correlation_distance_f32.c new file mode 100644 index 00000000..2578016e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_correlation_distance_f32.c @@ -0,0 +1,84 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlation_distance_f32.c + * Description: Correlation distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +/** + @addtogroup Correlation + @{ + */ + + +/** + * @brief Correlation distance between two vectors + * + * The input vectors are modified in place ! + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize) +{ + float32_t ma,mb,pwra,pwrb,dot,tmp; + + arm_mean_f32(pA, blockSize, &ma); + arm_mean_f32(pB, blockSize, &mb); + + arm_offset_f32(pA, -ma, pA, blockSize); + arm_offset_f32(pB, -mb, pB, blockSize); + + arm_power_f32(pA, blockSize, &pwra); + arm_power_f32(pB, blockSize, &pwrb); + + arm_dot_prod_f32(pA,pB,blockSize,&dot); + + dot = dot / blockSize; + pwra = pwra / blockSize; + pwrb = pwrb / blockSize; + + arm_sqrt_f32(pwra * pwrb,&tmp); + + return(1.0f - dot / tmp); + + +} + + + +/** + * @} end of Correlation group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f16.c new file mode 100644 index 00000000..20f890ba --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f16.c @@ -0,0 +1,88 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cosine_distance_f16.c + * Description: Cosine distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup CosineDist Cosine distance + + Cosine distance + */ + + +/** + @addtogroup CosineDist + @{ + */ + + + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + * @par Description + * cosine_distance(u,v) is 1 - u . v / (Norm(u) Norm(v)) + */ + +float16_t arm_cosine_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + float16_t pwra,pwrb,dot,tmp; + + arm_power_f16(pA, blockSize, &pwra); + arm_power_f16(pB, blockSize, &pwrb); + + arm_dot_prod_f16(pA,pB,blockSize,&dot); + + arm_sqrt_f16((_Float16)pwra * (_Float16)pwrb, &tmp); + return(1.0f16 - (_Float16)dot / (_Float16)tmp); + +} + + + +/** + * @} end of CosineDist group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f32.c new file mode 100644 index 00000000..014bff00 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f32.c @@ -0,0 +1,72 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cosine_distance_f32.c + * Description: Cosine distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup CosineDist + @{ + */ + + + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + * @par Description + * cosine_distance(u,v) is 1 - u . v / (Norm(u) Norm(v)) + */ + +float32_t arm_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t pwra,pwrb,dot,tmp; + + arm_power_f32(pA, blockSize, &pwra); + arm_power_f32(pB, blockSize, &pwrb); + + arm_dot_prod_f32(pA,pB,blockSize,&dot); + + arm_sqrt_f32(pwra * pwrb, &tmp); + return(1.0f - dot / tmp); + +} + + + +/** + * @} end of CosineDist group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f64.c new file mode 100644 index 00000000..c7443a6b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f64.c @@ -0,0 +1,70 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cosine_distance_f64.c + * Description: Cosine distance between two vectors + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup CosineDist + @{ + */ + + + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float64_t arm_cosine_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize) +{ + float64_t pwra,pwrb,dot,tmp; + + arm_power_f64(pA, blockSize, &pwra); + arm_power_f64(pB, blockSize, &pwrb); + + arm_dot_prod_f64(pA,pB,blockSize,&dot); + + tmp = sqrt(pwra * pwrb); + return(1. - dot / tmp); + +} + + + +/** + * @} end of CosineDist group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_dice_distance.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_dice_distance.c new file mode 100644 index 00000000..cae963a6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_dice_distance.c @@ -0,0 +1,92 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dice_distance.c + * Description: Dice distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + +extern void arm_boolean_distance_TT_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + * @ingroup groupDistance + * @{ + */ + +/** + * @defgroup BoolDist Boolean Distances + * + * Distances between two vectors of boolean values. + * + * Booleans are packed in 32 bit words. + * numberOfBooleans argument is the number of booleans and not the + * number of words. + * + * Bits are packed in big-endian mode (because of behavior of numpy packbits in + * in version < 1.17) + */ + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Dice distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,ctf=0,cft=0; + + arm_boolean_distance_TT_TF_FT(pA, pB, numberOfBools, &ctt, &ctf, &cft); + + return(1.0*(ctf + cft) / (2.0*ctt + cft + ctf)); +} + + +/** + * @} end of BoolDist group + */ + +/** + * @} end of groupDistance group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f16.c new file mode 100644 index 00000000..64d5d4a6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f16.c @@ -0,0 +1,131 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_euclidean_distance_f16.c + * Description: Euclidean distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + + +/** + @ingroup FloatDist + */ + +/** + @defgroup Euclidean Euclidean distance + + Euclidean distance + */ + + +/** + @addtogroup Euclidean + @{ + */ + + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" +float16_t arm_euclidean_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; + float16_t tmp; + f16x8_t a, b, accumV, tempV; + + accumV = vdupq_n_f16(0.0f); + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + tempV = vsubq(a, b); + accumV = vfmaq(accumV, tempV, tempV); + + pA += 8; + pB += 8; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + a = vldrhq_z_f16(pA, p0); + b = vldrhq_z_f16(pB, p0); + + tempV = vsubq(a, b); + accumV = vfmaq_m(accumV, tempV, tempV, p0); + } + + arm_sqrt_f16(vecAddAcrossF16Mve(accumV), &tmp); + return (tmp); +} + +#else +float16_t arm_euclidean_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 accum=0.0f,tmp; + float16_t result; + + while(blockSize > 0) + { + tmp = (_Float16)*pA++ - (_Float16)*pB++; + accum += SQ(tmp); + blockSize --; + } + arm_sqrt_f16(accum,&result); + return(result); +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Euclidean group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f32.c new file mode 100644 index 00000000..e226617e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f32.c @@ -0,0 +1,152 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_euclidean_distance_f32.c + * Description: Euclidean distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +/** + @addtogroup Euclidean + @{ + */ + + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" +float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; + float32_t tmp; + f32x4_t a, b, accumV, tempV; + + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + tempV = vsubq(a, b); + accumV = vfmaq(accumV, tempV, tempV); + + pA += 4; + pB += 4; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + + a = vldrwq_z_f32(pA, p0); + b = vldrwq_z_f32(pB, p0); + + tempV = vsubq(a, b); + accumV = vfmaq_m(accumV, tempV, tempV, p0); + } + + arm_sqrt_f32(vecAddAcrossF32Mve(accumV), &tmp); + return (tmp); +} +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum=0.0f,tmp; + uint32_t blkCnt; + float32x4_t a,b,accumV; + float32x2_t accumV2; + + accumV = vdupq_n_f32(0.0f); + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + a = vld1q_f32(pA); + b = vld1q_f32(pB); + + a = vsubq_f32(a,b); + accumV = vmlaq_f32(accumV,a,a); + pA += 4; + pB += 4; + blkCnt --; + } + accumV2 = vpadd_f32(vget_low_f32(accumV),vget_high_f32(accumV)); + accum = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + tmp = *pA++ - *pB++; + accum += SQ(tmp); + blkCnt --; + } + arm_sqrt_f32(accum,&tmp); + return(tmp); +} + +#else +float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum=0.0f,tmp; + + while(blockSize > 0) + { + tmp = *pA++ - *pB++; + accum += SQ(tmp); + blockSize --; + } + arm_sqrt_f32(accum,&tmp); + return(tmp); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Euclidean group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f64.c new file mode 100644 index 00000000..8c8dfde5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f64.c @@ -0,0 +1,66 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_euclidean_distance_f64.c + * Description: Euclidean distance between two vectors + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +/** + @addtogroup Euclidean + @{ + */ + + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float64_t arm_euclidean_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize) +{ + float64_t accum=0.,tmp; + + while(blockSize > 0) + { + tmp = *pA++ - *pB++; + accum += SQ(tmp); + blockSize --; + } + tmp = sqrt(accum); + return(tmp); +} + +/** + * @} end of Euclidean group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_hamming_distance.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_hamming_distance.c new file mode 100644 index 00000000..f95c46eb --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_hamming_distance.c @@ -0,0 +1,70 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_hamming_distance.c + * Description: Hamming distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +extern void arm_boolean_distance_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTF + , uint32_t *cFT + ); + +/** + @addtogroup BoolDist + @{ + */ + + +/** + * @brief Hamming distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctf=0,cft=0; + + arm_boolean_distance_TF_FT(pA, pB, numberOfBools, &ctf, &cft); + + return(1.0*(ctf + cft) / numberOfBools); +} + + +/** + * @} end of BoolDist group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_jaccard_distance.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_jaccard_distance.c new file mode 100644 index 00000000..26617a5d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_jaccard_distance.c @@ -0,0 +1,72 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_jaccard_distance.c + * Description: Jaccard distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +extern void arm_boolean_distance_TT_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Jaccard distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,ctf=0,cft=0; + + arm_boolean_distance_TT_TF_FT(pA, pB, numberOfBools, &ctt, &ctf, &cft); + + return(1.0*(ctf + cft) / (ctt + cft + ctf)); +} + + +/** + * @} end of BoolDist group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_jensenshannon_distance_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_jensenshannon_distance_f16.c new file mode 100644 index 00000000..b31ef348 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_jensenshannon_distance_f16.c @@ -0,0 +1,177 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_jensenshannon_distance_f16.c + * Description: Jensen-Shannon distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup JensenShannon Jensen-Shannon distance + + Jensen-Shannon distance + */ + + +/** + @addtogroup JensenShannon + @{ + */ + +#if !defined(ARM_MATH_MVE_FLOAT16) || defined(ARM_MATH_AUTOVECTORIZE) +/// @private +__STATIC_INLINE float16_t rel_entr(float16_t x, float16_t y) +{ + return ((_Float16)x * (_Float16)logf((float32_t)((_Float16)x / (_Float16)y))); +} +#endif + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math_f16.h" + +float16_t arm_jensenshannon_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; + float16_t tmp; + f16x8_t a, b, t, tmpV, accumV; + + accumV = vdupq_n_f16(0.0f); + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + t = vaddq(a, b); + t = vmulq(t, 0.5f); + + tmpV = vmulq(a, vrecip_medprec_f16(t)); + tmpV = vlogq_f16(tmpV); + accumV = vfmaq(accumV, a, tmpV); + + tmpV = vmulq_f16(b, vrecip_medprec_f16(t)); + tmpV = vlogq_f16(tmpV); + accumV = vfmaq(accumV, b, tmpV); + + pA += 8; + pB += 8; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + a = vldrhq_z_f16(pA, p0); + b = vldrhq_z_f16(pB, p0); + + t = vaddq(a, b); + t = vmulq(t, 0.5f); + + tmpV = vmulq_f16(a, vrecip_medprec_f16(t)); + tmpV = vlogq_f16(tmpV); + accumV = vfmaq_m_f16(accumV, a, tmpV, p0); + + tmpV = vmulq_f16(b, vrecip_medprec_f16(t)); + tmpV = vlogq_f16(tmpV); + accumV = vfmaq_m_f16(accumV, b, tmpV, p0); + + } + + arm_sqrt_f16((_Float16)vecAddAcrossF16Mve(accumV) / 2.0f16, &tmp); + return (tmp); +} + +#else + + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x == 0 and y == 0, + * it will compute the right result (0) but a division by zero will occur + * and should be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + + +float16_t arm_jensenshannon_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 left, right,sum, tmp; + float16_t result; + uint32_t i; + + left = 0.0f16; + right = 0.0f16; + for(i=0; i < blockSize; i++) + { + tmp = ((_Float16)pA[i] + (_Float16)pB[i]) / 2.0f16; + left += (_Float16)rel_entr(pA[i], tmp); + right += (_Float16)rel_entr(pB[i], tmp); + } + + + sum = left + right; + arm_sqrt_f16((_Float16)sum/2.0f16, &result); + return(result); + +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of JensenShannon group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_jensenshannon_distance_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_jensenshannon_distance_f32.c new file mode 100644 index 00000000..5f1a44cc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_jensenshannon_distance_f32.c @@ -0,0 +1,247 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_jensenshannon_distance_f32.c + * Description: Jensen-Shannon distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup JensenShannon + @{ + */ + +#if !defined(ARM_MATH_MVEF) || defined(ARM_MATH_AUTOVECTORIZE) +/// @private +__STATIC_INLINE float32_t rel_entr(float32_t x, float32_t y) +{ + return (x * logf(x / y)); +} +#endif + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; + float32_t tmp; + f32x4_t a, b, t, tmpV, accumV; + + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + t = vaddq(a, b); + t = vmulq(t, 0.5f); + + tmpV = vmulq(a, vrecip_medprec_f32(t)); + tmpV = vlogq_f32(tmpV); + accumV = vfmaq(accumV, a, tmpV); + + tmpV = vmulq_f32(b, vrecip_medprec_f32(t)); + tmpV = vlogq_f32(tmpV); + accumV = vfmaq(accumV, b, tmpV); + + pA += 4; + pB += 4; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + + a = vldrwq_z_f32(pA, p0); + b = vldrwq_z_f32(pB, p0); + + t = vaddq(a, b); + t = vmulq(t, 0.5f); + + tmpV = vmulq_f32(a, vrecip_medprec_f32(t)); + tmpV = vlogq_f32(tmpV); + accumV = vfmaq_m_f32(accumV, a, tmpV, p0); + + tmpV = vmulq_f32(b, vrecip_medprec_f32(t)); + tmpV = vlogq_f32(tmpV); + accumV = vfmaq_m_f32(accumV, b, tmpV, p0); + + } + + arm_sqrt_f32(vecAddAcrossF32Mve(accumV) / 2.0f, &tmp); + return (tmp); +} + +#else + +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x == 0 and y == 0, + * it will compute the right result (0) but a division by zero will occur + * and should be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + + +float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum, result, tmp,a,b; + uint32_t blkCnt; + float32x4_t aV,bV,t, tmpV, accumV; + float32x2_t accumV2; + + accum = 0.0f; + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + aV = vld1q_f32(pA); + bV = vld1q_f32(pB); + t = vaddq_f32(aV,bV); + t = vmulq_n_f32(t, 0.5f); + + tmpV = vmulq_f32(aV, vinvq_f32(t)); + tmpV = vlogq_f32(tmpV); + accumV = vmlaq_f32(accumV, aV, tmpV); + + + tmpV = vmulq_f32(bV, vinvq_f32(t)); + tmpV = vlogq_f32(tmpV); + accumV = vmlaq_f32(accumV, bV, tmpV); + + pA += 4; + pB += 4; + + + blkCnt --; + } + + accumV2 = vpadd_f32(vget_low_f32(accumV),vget_high_f32(accumV)); + accum = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + a = *pA; + b = *pB; + tmp = (a + b) / 2.0f; + accum += rel_entr(a, tmp); + accum += rel_entr(b, tmp); + + pA++; + pB++; + + blkCnt --; + } + + + arm_sqrt_f32(accum/2.0f, &result); + return(result); + +} + +#else + + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x == 0 and y == 0, + * it will compute the right result (0) but a division by zero will occur + * and should be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + + +float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t left, right,sum, result, tmp; + uint32_t i; + + left = 0.0f; + right = 0.0f; + for(i=0; i < blockSize; i++) + { + tmp = (pA[i] + pB[i]) / 2.0f; + left += rel_entr(pA[i], tmp); + right += rel_entr(pB[i], tmp); + } + + + sum = left + right; + arm_sqrt_f32(sum/2.0f, &result); + return(result); + +} + +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of JensenShannon group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_kulsinski_distance.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_kulsinski_distance.c new file mode 100644 index 00000000..239dc0e5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_kulsinski_distance.c @@ -0,0 +1,73 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_kulsinski_distance.c + * Description: Kulsinski distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +extern void arm_boolean_distance_TT_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + @addtogroup BoolDist + @{ + */ + + +/** + * @brief Kulsinski distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,ctf=0,cft=0; + + arm_boolean_distance_TT_TF_FT(pA, pB, numberOfBools, &ctt, &ctf, &cft); + + return(1.0*(ctf + cft - ctt + numberOfBools) / (cft + ctf + numberOfBools)); +} + + +/** + * @} end of BoolDist group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_minkowski_distance_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_minkowski_distance_f16.c new file mode 100644 index 00000000..c5300ab0 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_minkowski_distance_f16.c @@ -0,0 +1,137 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_minkowski_distance_f16.c + * Description: Minkowski distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup Minkowski Minkowski distance + + Minkowski distance + */ + +/** + @addtogroup Minkowski + @{ + */ + + +/** + * @brief Minkowski distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] order Distance order + * @param[in] blockSize Number of samples + * @return distance + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math_f16.h" + +float16_t arm_minkowski_distance_f16(const float16_t *pA,const float16_t *pB, int32_t order, uint32_t blockSize) +{ + uint32_t blkCnt; + f16x8_t a, b, tmpV, sumV; + + sumV = vdupq_n_f16(0.0f); + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + tmpV = vabdq(a, b); + tmpV = vpowq_f16(tmpV, vdupq_n_f16(order)); + sumV = vaddq(sumV, tmpV); + + pA += 8; + pB += 8; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + a = vldrhq_z_f16(pA, p0); + b = vldrhq_z_f16(pB, p0); + + tmpV = vabdq(a, b); + tmpV = vpowq_f16(tmpV, vdupq_n_f16(order)); + sumV = vaddq_m(sumV, sumV, tmpV, p0); + } + + return (powf((float32_t)vecAddAcrossF16Mve(sumV), (1.0f / (float32_t) order))); +} + + +#else + + +float16_t arm_minkowski_distance_f16(const float16_t *pA,const float16_t *pB, int32_t order, uint32_t blockSize) +{ + _Float16 sum; + uint32_t i; + + sum = 0.0f16; + for(i=0; i < blockSize; i++) + { + sum += (_Float16)powf(fabsf((float32_t)((_Float16)pA[i] - (_Float16)pB[i])),order); + } + + + return(_Float16)(powf((float32_t)sum,(1.0f/(float32_t)order))); + +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Minkowski group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_minkowski_distance_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_minkowski_distance_f32.c new file mode 100644 index 00000000..b881fc1f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_minkowski_distance_f32.c @@ -0,0 +1,188 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_minkowski_distance_f32.c + * Description: Minkowski distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup Minkowski + @{ + */ + +/* 6.14 bug */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) && (__ARMCC_VERSION < 6150001) + +__attribute__((weak)) float __powisf2(float a, int b) +{ + const int recip = b < 0; + float r = 1; + while (1) + { + if (b & 1) + r *= a; + b /= 2; + if (b == 0) + break; + a *= a; + } + return recip ? 1/r : r; +} +#endif + +/** + * @brief Minkowski distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] order Distance order + * @param[in] blockSize Number of samples + * @return distance + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize) +{ + uint32_t blkCnt; + f32x4_t a, b, tmpV, sumV; + + sumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + tmpV = vabdq(a, b); + tmpV = vpowq_f32(tmpV, vdupq_n_f32(order)); + sumV = vaddq(sumV, tmpV); + + pA += 4; + pB += 4; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + + a = vldrwq_z_f32(pA, p0); + b = vldrwq_z_f32(pB, p0); + + tmpV = vabdq(a, b); + tmpV = vpowq_f32(tmpV, vdupq_n_f32(order)); + sumV = vaddq_m(sumV, sumV, tmpV, p0); + } + + return (powf(vecAddAcrossF32Mve(sumV), (1.0f / (float32_t) order))); +} + +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize) +{ + float32_t sum; + uint32_t blkCnt; + float32x4_t sumV,aV,bV, tmpV, n; + float32x2_t sumV2; + + sum = 0.0f; + sumV = vdupq_n_f32(0.0f); + n = vdupq_n_f32(order); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + aV = vld1q_f32(pA); + bV = vld1q_f32(pB); + pA += 4; + pB += 4; + + tmpV = vabdq_f32(aV,bV); + tmpV = vpowq_f32(tmpV,n); + sumV = vaddq_f32(sumV, tmpV); + + + blkCnt --; + } + + sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = vget_lane_f32(sumV2, 0) + vget_lane_f32(sumV2, 1); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + sum += powf(fabsf(*pA++ - *pB++),order); + + blkCnt --; + } + + + return(powf(sum,(1.0f/order))); + +} + +#else + + +float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize) +{ + float32_t sum; + uint32_t i; + + sum = 0.0f; + for(i=0; i < blockSize; i++) + { + sum += powf(fabsf(pA[i] - pB[i]),order); + } + + + return(powf(sum,(1.0f/order))); + +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Minkowski group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_rogerstanimoto_distance.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_rogerstanimoto_distance.c new file mode 100644 index 00000000..b918fadb --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_rogerstanimoto_distance.c @@ -0,0 +1,75 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rogerstanimoto_distance.c + * Description: Roger Stanimoto distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +extern void arm_boolean_distance_TT_FF_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cFF + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Rogers Tanimoto distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,cff=0,ctf=0,cft=0,r; + + arm_boolean_distance_TT_FF_TF_FT(pA, pB, numberOfBools, &ctt,&cff, &ctf, &cft); + + r = 2*(ctf + cft); + + return(1.0*r / (r + ctt + cff)); +} + + +/** + * @} end of BoolDist group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_russellrao_distance.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_russellrao_distance.c new file mode 100644 index 00000000..0698a64a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_russellrao_distance.c @@ -0,0 +1,72 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_russellrao_distance.c + * Description: Russell-Rao distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +extern void arm_boolean_distance_TT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + ); + + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Russell-Rao distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0; + + + arm_boolean_distance_TT(pA, pB, numberOfBools, &ctt); + + + return(1.0f*(numberOfBools - ctt) / ((float32_t)numberOfBools)); +} + + +/** + * @} end of BoolDist group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_sokalmichener_distance.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_sokalmichener_distance.c new file mode 100644 index 00000000..8015c97a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_sokalmichener_distance.c @@ -0,0 +1,76 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sokalmichener_distance.c + * Description: Sokal-Michener distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +extern void arm_boolean_distance_TT_FF_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cFF + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Sokal-Michener distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,cff=0,cft=0,ctf=0; + float32_t r,s; + + arm_boolean_distance_TT_FF_TF_FT(pA, pB, numberOfBools, &ctt, &cff, &ctf, &cft); + + r = 2.0*(ctf + cft); + s = 1.0*(cff + ctt); + + return(r / (s+r)); +} + + +/** + * @} end of BoolDist group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_sokalsneath_distance.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_sokalsneath_distance.c new file mode 100644 index 00000000..93d8e50e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_sokalsneath_distance.c @@ -0,0 +1,74 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sokalsneath_distance.c + * Description: Sokal-Sneath distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +extern void arm_boolean_distance_TT_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Sokal-Sneath distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,cft=0,ctf=0; + float32_t r; + + arm_boolean_distance_TT_TF_FT(pA, pB, numberOfBools, &ctt, &ctf, &cft); + + r = 2.0*(ctf + cft); + + return(r / (r + ctt)); +} + + +/** + * @} end of BoolDist group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_yule_distance.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_yule_distance.c new file mode 100644 index 00000000..54afebfa --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_yule_distance.c @@ -0,0 +1,74 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_yule_distance.c + * Description: Yule distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +extern void arm_boolean_distance_TT_FF_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cFF + , uint32_t *cTF + , uint32_t *cFT + ); + +/** + @addtogroup BoolDist + @{ + */ + + +/** + * @brief Yule distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,cff=0,ctf=0,cft=0,r; + + arm_boolean_distance_TT_FF_TF_FT(pA, pB, numberOfBools, &ctt,&cff, &ctf, &cft); + + r = 2*(ctf * cft); + + return(1.0*r / (r/2.0 + ctt * cff)); +} + + +/** + * @} end of BoolDist group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/CMakeLists.txt new file mode 100644 index 00000000..95a9eb61 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/CMakeLists.txt @@ -0,0 +1,80 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPFastMath) + +include(configLib) +include(configDsp) + + +add_library(CMSISDSPFastMath STATIC) +configLib(CMSISDSPFastMath ${ROOT}) +configDsp(CMSISDSPFastMath ${ROOT}) + +include(interpol) +interpol(CMSISDSPFastMath) + +if (CONFIGTABLE AND ALLFAST) + target_compile_definitions(CMSISDSPFastMath PUBLIC ARM_ALL_FAST_TABLES) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_COS_F32) +target_sources(CMSISDSPFastMath PRIVATE arm_cos_f32.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_COS_Q15) +target_sources(CMSISDSPFastMath PRIVATE arm_cos_q15.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_COS_Q31) +target_sources(CMSISDSPFastMath PRIVATE arm_cos_q31.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_SIN_F32) +target_sources(CMSISDSPFastMath PRIVATE arm_sin_f32.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_SIN_Q15) +target_sources(CMSISDSPFastMath PRIVATE arm_sin_q15.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_SIN_Q31) +target_sources(CMSISDSPFastMath PRIVATE arm_sin_q31.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_SQRT_Q31) +target_sources(CMSISDSPFastMath PRIVATE arm_sqrt_q31.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_SQRT_Q15) +target_sources(CMSISDSPFastMath PRIVATE arm_sqrt_q15.c) +endif() + +target_sources(CMSISDSPFastMath PRIVATE arm_vlog_f32.c) +target_sources(CMSISDSPFastMath PRIVATE arm_vlog_f64.c) +target_sources(CMSISDSPFastMath PRIVATE arm_vexp_f32.c) +target_sources(CMSISDSPFastMath PRIVATE arm_vexp_f64.c) + +target_sources(CMSISDSPFastMath PRIVATE arm_vlog_q31.c) +target_sources(CMSISDSPFastMath PRIVATE arm_vlog_q15.c) + + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPFastMath PRIVATE arm_vlog_f16.c) +target_sources(CMSISDSPFastMath PRIVATE arm_vexp_f16.c) +target_sources(CMSISDSPFastMath PRIVATE arm_vinverse_f16.c) +target_sources(CMSISDSPFastMath PRIVATE arm_atan2_f16.c) +endif() + +target_sources(CMSISDSPFastMath PRIVATE arm_divide_q15.c) +target_sources(CMSISDSPFastMath PRIVATE arm_divide_q31.c) + +target_sources(CMSISDSPFastMath PRIVATE arm_atan2_f32.c) +target_sources(CMSISDSPFastMath PRIVATE arm_atan2_q31.c) +target_sources(CMSISDSPFastMath PRIVATE arm_atan2_q15.c) + + +### Includes +target_include_directories(CMSISDSPFastMath PUBLIC "${DSP}/Include") + + + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c new file mode 100644 index 00000000..0146d61b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: FastMathFunctions.c + * Description: Combination of all fast math function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32) +#include "arm_cos_f32.c" +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15) +#include "arm_cos_q15.c" +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31) +#include "arm_cos_q31.c" +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32) +#include "arm_sin_f32.c" +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15) +#include "arm_sin_q15.c" +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31) +#include "arm_sin_q31.c" +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q31) +#include "arm_sqrt_q31.c" +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q15) +#include "arm_sqrt_q15.c" +#endif + +#endif + +#include "arm_vexp_f32.c" +#include "arm_vexp_f64.c" +#include "arm_vlog_f32.c" +#include "arm_vlog_f64.c" +#include "arm_divide_q15.c" +#include "arm_divide_q31.c" +#include "arm_vlog_q31.c" +#include "arm_vlog_q15.c" +#include "arm_atan2_f32.c" +#include "arm_atan2_q31.c" +#include "arm_atan2_q15.c" diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctionsF16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctionsF16.c new file mode 100644 index 00000000..79c731f4 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctionsF16.c @@ -0,0 +1,32 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: FastMathFunctions.c + * Description: Combination of all fast math function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_vexp_f16.c" +#include "arm_vlog_f16.c" +#include "arm_vinverse_f16.c" +#include "arm_atan2_f16.c" diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_f16.c new file mode 100644 index 00000000..b4a03a4b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_f16.c @@ -0,0 +1,171 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_atan2_f16.c + * Description: float16 Arc tangent of y/x + * + * $Date: 22 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/* + +atan for argument between in [0, 1.0] + + +*/ + +#define PIF16 3.14f16 +#define PI16HALF 1.571f16 + +#define ATANHALFF16 0.463648f16 + +#define ATAN2_NB_COEFS_F16 5 + +static const float16_t atan2_coefs_f16[ATAN2_NB_COEFS_F16]={0.f16 +,1.f16 +,0.f16 +,-0.367f16 +,0.152f16 +}; + +__STATIC_FORCEINLINE float16_t arm_atan_limited_f16(float16_t x) +{ + float16_t res=atan2_coefs_f16[ATAN2_NB_COEFS_F16-1]; + int i=1; + for(i=1;i 1.0f16) + { + x = 1.0f16 / (_Float16)x; + res = (_Float16)PI16HALF - (_Float16)arm_atan_limited_f16(x); + } + else + { + res += (_Float16)arm_atan_limited_f16(x); + } + + + if (sign) + { + res = -(_Float16)res; + } + + return(res); +} + +/** + @ingroup groupFastMath + */ + + +/** + @addtogroup atan2 + @{ + */ + +/** + @brief Arc Tangent of y/x using sign of y and x to get right quadrant + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result + @return error status. + + @par Compute the Arc tangent of y/x: + The sign of y and x are used to determine the right quadrant + and compute the right angle. + +*/ +arm_status arm_atan2_f16(float16_t y,float16_t x,float16_t *result) +{ + if ((_Float16)x > 0.0f16) + { + *result=arm_atan_f16((_Float16)y/(_Float16)x); + return(ARM_MATH_SUCCESS); + } + if ((_Float16)x < 0.0f16) + { + if ((_Float16)y > 0.0f16) + { + *result=(_Float16)arm_atan_f16((_Float16)y/(_Float16)x) + (_Float16)PIF16; + } + else if ((_Float16)y < 0.0f16) + { + *result=(_Float16)arm_atan_f16((_Float16)y/(_Float16)x) - (_Float16)PIF16; + } + else + { + if (signbit(y)) + { + *result= -(_Float16)PIF16; + } + else + { + *result= PIF16; + } + } + return(ARM_MATH_SUCCESS); + } + if ((_Float16)x == 0.0f16) + { + if ((_Float16)y > 0.0f16) + { + *result=PI16HALF; + return(ARM_MATH_SUCCESS); + } + if ((_Float16)y < 0.0f16) + { + *result=-(_Float16)PI16HALF; + return(ARM_MATH_SUCCESS); + } + } + + + return(ARM_MATH_NANINF); + +} + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ +/** + @} end of atan2 group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_f32.c new file mode 100644 index 00000000..3e398f78 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_f32.c @@ -0,0 +1,183 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_atan2_f32.c + * Description: float32 Arc tangent of y/x + * + * $Date: 22 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" + +/* + +atan for argument between in [0, 1.0] + + +*/ + +#define ATANHALFF32 0.463648f +#define PIHALFF32 1.5707963267948966192313f + +#define ATAN2_NB_COEFS_F32 10 + +static const float32_t atan2_coefs_f32[ATAN2_NB_COEFS_F32]={0.0f +,1.0000001638308195518f +,-0.0000228941363602264f +,-0.3328086544578890873f +,-0.004404814619311061f +,0.2162217461808173258f +,-0.0207504842057097504f +,-0.1745263362250363339f +,0.1340557235283553386f +,-0.0323664125927477625f +}; + +__STATIC_FORCEINLINE float32_t arm_atan_limited_f32(float32_t x) +{ + float32_t res=atan2_coefs_f32[ATAN2_NB_COEFS_F32-1]; + int i=1; + for(i=1;i 1.0f) + { + x = 1.0f / x; + res = PIHALFF32 - arm_atan_limited_f32(x); + } + else + { + res += arm_atan_limited_f32(x); + } + + + if (sign) + { + res = -res; + } + + return(res); +} + + +/** + @ingroup groupFastMath + */ + +/** + @defgroup atan2 ArcTan2 + + Computing Arc tangent only using the ratio y/x is not enough to determine the angle + since there is an indeterminacy. Opposite quadrants are giving the same ratio. + + ArcTan2 is not using y/x to compute the angle but y and x and use the sign of y and x + to determine the quadrant. + + */ + +/** + @addtogroup atan2 + @{ + */ + +/** + @brief Arc Tangent of y/x using sign of y and x to get right quadrant + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result + @return error status. + + @par Compute the Arc tangent of y/x: + The sign of y and x are used to determine the right quadrant + and compute the right angle. +*/ + + +arm_status arm_atan2_f32(float32_t y,float32_t x,float32_t *result) +{ + if (x > 0.0f) + { + *result=arm_atan_f32(y/x); + return(ARM_MATH_SUCCESS); + } + if (x < 0.0f) + { + if (y > 0.0f) + { + *result=arm_atan_f32(y/x) + PI; + } + else if (y < 0.0f) + { + *result=arm_atan_f32(y/x) - PI; + } + else + { + if (signbit(y)) + { + *result= -PI; + } + else + { + *result= PI; + } + } + return(ARM_MATH_SUCCESS); + } + if (x == 0.0f) + { + if (y > 0.0f) + { + *result=PIHALFF32; + return(ARM_MATH_SUCCESS); + } + if (y < 0.0f) + { + *result=-PIHALFF32; + return(ARM_MATH_SUCCESS); + } + } + + + return(ARM_MATH_NANINF); + +} + +/** + @} end of atan2 group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_q15.c new file mode 100644 index 00000000..ddf98d8c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_q15.c @@ -0,0 +1,201 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_atan2_q15.c + * Description: float32 Arc tangent of y/x + * + * $Date: 22 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "dsp/utils.h" + +/* + +atan for argument between in [0, 1.0] + +*/ + + +/* Q2.13 */ +#define ATANHALFQ13 0xed6 +#define PIHALFQ13 0x3244 +#define PIQ13 0x6488 + +#define ATAN2_NB_COEFS_Q15 10 + +static const q15_t atan2_coefs_q15[ATAN2_NB_COEFS_Q15]={0x0000 +,0x7fff +,0xffff +,0xd567 +,0xff70 +,0x1bad +,0xfd58 +,0xe9a9 +,0x1129 +,0xfbdb +}; + +__STATIC_FORCEINLINE q15_t arm_atan_limited_q15(q15_t x) +{ + q31_t res=(q31_t)atan2_coefs_q15[ATAN2_NB_COEFS_Q15-1]; + int i=1; + for(i=1;i> 15U; + res = res + ((q31_t) atan2_coefs_q15[ATAN2_NB_COEFS_Q15-1-i]) ; + } + + res = __SSAT(res>>2,16); + + + return(res); +} + + +__STATIC_FORCEINLINE q15_t arm_atan_q15(q15_t y,q15_t x) +{ + int sign=0; + q15_t res=0; + + if (y<0) + { + arm_negate_q15(&y,&y,1); + sign=1-sign; + } + + if (x < 0) + { + sign=1 - sign; + arm_negate_q15(&x,&x,1); + } + + if (y > x) + { + q15_t ratio; + int16_t shift; + + arm_divide_q15(x,y,&ratio,&shift); + + arm_shift_q15(&ratio,shift,&ratio,1); + + res = PIHALFQ13 - arm_atan_limited_q15(ratio); + + } + else + { + q15_t ratio; + int16_t shift; + + arm_divide_q15(y,x,&ratio,&shift); + + arm_shift_q15(&ratio,shift,&ratio,1); + + res = arm_atan_limited_q15(ratio); + + } + + + if (sign) + { + arm_negate_q15(&res,&res,1); + } + + return(res); +} + + +/** + @ingroup groupFastMath + */ + + +/** + @addtogroup atan2 + @{ + */ + +/** + @brief Arc Tangent of y/x using sign of y and x to get right quadrant + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result in Q2.13 + @return error status. + + @par Compute the Arc tangent of y/x: + The sign of y and x are used to determine the right quadrant + and compute the right angle. +*/ + + +arm_status arm_atan2_q15(q15_t y,q15_t x,q15_t *result) +{ + if (x > 0) + { + *result=arm_atan_q15(y,x); + return(ARM_MATH_SUCCESS); + } + if (x < 0) + { + if (y > 0) + { + *result=arm_atan_q15(y,x) + PIQ13; + } + else if (y < 0) + { + *result=arm_atan_q15(y,x) - PIQ13; + } + else + { + if (y<0) + { + *result= -PIQ13; + } + else + { + *result= PIQ13; + } + } + return(ARM_MATH_SUCCESS); + } + if (x == 0) + { + if (y > 0) + { + *result=PIHALFQ13; + return(ARM_MATH_SUCCESS); + } + if (y < 0) + { + *result=-PIHALFQ13; + return(ARM_MATH_SUCCESS); + } + } + + + return(ARM_MATH_NANINF); + +} + +/** + @} end of atan2 group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_q31.c new file mode 100644 index 00000000..1c83e436 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_q31.c @@ -0,0 +1,202 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_atan2_q31.c + * Description: float32 Arc tangent of y/x + * + * $Date: 22 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "dsp/utils.h" + +/* + +atan for argument between in [0, 1.0] + +*/ + + +/* Q2.29 */ +#define ATANHALF_Q29 0xed63383 +#define PIHALF_Q29 0x3243f6a9 +#define PIQ29 0x6487ed51 + +#define ATAN2_NB_COEFS_Q31 13 + +static const q31_t atan2_coefs_q31[ATAN2_NB_COEFS_Q31]={0x00000000 +,0x7ffffffe +,0x000001b6 +,0xd555158e +,0x00036463 +,0x1985f617 +,0x001992ae +,0xeed53a7f +,0xf8f15245 +,0x2215a3a4 +,0xe0fab004 +,0x0cdd4825 +,0xfddbc054 +}; + + +__STATIC_FORCEINLINE q31_t arm_atan_limited_q31(q31_t x) +{ + q63_t res=(q63_t)atan2_coefs_q31[ATAN2_NB_COEFS_Q31-1]; + int i=1; + for(i=1;i> 31U; + res = res + ((q63_t) atan2_coefs_q31[ATAN2_NB_COEFS_Q31-1-i]) ; + } + + return(clip_q63_to_q31(res>>2)); +} + + +__STATIC_FORCEINLINE q31_t arm_atan_q31(q31_t y,q31_t x) +{ + int sign=0; + q31_t res=0; + + if (y<0) + { + arm_negate_q31(&y,&y,1); + sign=1-sign; + } + + if (x < 0) + { + sign=1 - sign; + arm_negate_q31(&x,&x,1); + } + + if (y > x) + { + q31_t ratio; + int16_t shift; + + arm_divide_q31(x,y,&ratio,&shift); + + arm_shift_q31(&ratio,shift,&ratio,1); + + res = PIHALF_Q29 - arm_atan_limited_q31(ratio); + + } + else + { + q31_t ratio; + int16_t shift; + + arm_divide_q31(y,x,&ratio,&shift); + + arm_shift_q31(&ratio,shift,&ratio,1); + + res = arm_atan_limited_q31(ratio); + + } + + + if (sign) + { + arm_negate_q31(&res,&res,1); + } + + return(res); +} + + +/** + @ingroup groupFastMath + */ + + +/** + @addtogroup atan2 + @{ + */ + +/** + @brief Arc Tangent of y/x using sign of y and x to get right quadrant + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result in Q2.29 + @return error status. + + @par Compute the Arc tangent of y/x: + The sign of y and x are used to determine the right quadrant + and compute the right angle. +*/ + + +arm_status arm_atan2_q31(q31_t y,q31_t x,q31_t *result) +{ + if (x > 0) + { + *result=arm_atan_q31(y,x); + return(ARM_MATH_SUCCESS); + } + if (x < 0) + { + if (y > 0) + { + *result=arm_atan_q31(y,x) + PIQ29; + } + else if (y < 0) + { + *result=arm_atan_q31(y,x) - PIQ29; + } + else + { + if (y<0) + { + *result= -PIQ29; + } + else + { + *result= PIQ29; + } + } + return(ARM_MATH_SUCCESS); + } + if (x == 0) + { + if (y > 0) + { + *result=PIHALF_Q29; + return(ARM_MATH_SUCCESS); + } + if (y < 0) + { + *result=-PIHALF_Q29; + return(ARM_MATH_SUCCESS); + } + } + + + return(ARM_MATH_NANINF); + +} + +/** + @} end of atan2 group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c new file mode 100644 index 00000000..de037c87 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cos_f32.c + * Description: Fast cosine calculation for floating-point values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @defgroup cos Cosine + + Computes the trigonometric cosine function using a combination of table lookup + and linear interpolation. There are separate functions for + Q15, Q31, and floating-point data types. + The input to the floating-point version is in radians while the + fixed-point Q15 and Q31 have a scaled input with the range + [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a + value of 2*pi wraps around to 0. + + The implementation is based on table lookup using 512 values together with linear interpolation. + The steps used are: + -# Calculation of the nearest integer table index + -# Compute the fractional portion (fract) of the table index. + -# The final result equals (1.0f-fract)*a + fract*b; + + where +
+     a = Table[index];
+     b = Table[index+1];
+  
+ */ + +/** + @addtogroup cos + @{ + */ + +/** + @brief Fast approximation to the trigonometric cosine function for floating-point data. + @param[in] x input value in radians + @return cos(x) + */ +float32_t arm_cos_f32( + float32_t x) +{ + float32_t cosVal, fract, in; /* Temporary input, output variables */ + uint16_t index; /* Index variable */ + float32_t a, b; /* Two nearest output values */ + int32_t n; + float32_t findex; + + /* input x is in radians */ + /* Scale input to [0 1] range from [0 2*PI] , divide input by 2*pi, add 0.25 (pi/2) to read sine table */ + in = x * 0.159154943092f + 0.25f; + + /* Calculation of floor value of input */ + n = (int32_t) in; + + /* Make negative values towards -infinity */ + if (in < 0.0f) + { + n--; + } + + /* Map input value to [0 1] */ + in = in - (float32_t) n; + + /* Calculation of index of the table */ + findex = (float32_t)FAST_MATH_TABLE_SIZE * in; + index = (uint16_t)findex; + + /* when "in" is exactly 1, we need to rotate the index down to 0 */ + if (index >= FAST_MATH_TABLE_SIZE) { + index = 0; + findex -= (float32_t)FAST_MATH_TABLE_SIZE; + } + + /* fractional value calculation */ + fract = findex - (float32_t) index; + + /* Read two nearest values of input value from the cos table */ + a = sinTable_f32[index]; + b = sinTable_f32[index+1]; + + /* Linear interpolation process */ + cosVal = (1.0f - fract) * a + fract * b; + + /* Return output value */ + return (cosVal); +} + +/** + @} end of cos group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c new file mode 100644 index 00000000..6b552f11 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c @@ -0,0 +1,84 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cos_q15.c + * Description: Fast cosine calculation for Q15 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup cos + @{ + */ + +/** + @brief Fast approximation to the trigonometric cosine function for Q15 data. + @param[in] x Scaled input value in radians + @return cos(x) + + The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*PI). + */ + +q15_t arm_cos_q15( + q15_t x) +{ + q15_t cosVal; /* Temporary input, output variables */ + int32_t index; /* Index variable */ + q15_t a, b; /* Two nearest output values */ + q15_t fract; /* Temporary values for fractional values */ + + /* add 0.25 (pi/2) to read sine table */ + x = (uint16_t)x + 0x2000; + if (x < 0) + { /* convert negative numbers to corresponding positive ones */ + x = (uint16_t)x + 0x8000; + } + + /* Calculate the nearest index */ + index = (uint32_t)x >> FAST_MATH_Q15_SHIFT; + + /* Calculation of fractional value */ + fract = (x - (index << FAST_MATH_Q15_SHIFT)) << 9; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_q15[index]; + b = sinTable_q15[index+1]; + + /* Linear interpolation process */ + cosVal = (q31_t) (0x8000 - fract) * a >> 16; + cosVal = (q15_t) ((((q31_t) cosVal << 16) + ((q31_t) fract * b)) >> 16); + + /* Return output value */ + return (cosVal << 1); +} + +/** + @} end of cos group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c new file mode 100644 index 00000000..8386c8f2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c @@ -0,0 +1,84 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cos_q31.c + * Description: Fast cosine calculation for Q31 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup cos + @{ + */ + +/** + @brief Fast approximation to the trigonometric cosine function for Q31 data. + @param[in] x Scaled input value in radians + @return cos(x) + + The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*PI). + */ + +q31_t arm_cos_q31( + q31_t x) +{ + q31_t cosVal; /* Temporary input, output variables */ + int32_t index; /* Index variable */ + q31_t a, b; /* Two nearest output values */ + q31_t fract; /* Temporary values for fractional values */ + + /* add 0.25 (pi/2) to read sine table */ + x = (uint32_t)x + 0x20000000; + if (x < 0) + { /* convert negative numbers to corresponding positive ones */ + x = (uint32_t)x + 0x80000000; + } + + /* Calculate the nearest index */ + index = (uint32_t)x >> FAST_MATH_Q31_SHIFT; + + /* Calculation of fractional value */ + fract = (x - (index << FAST_MATH_Q31_SHIFT)) << 9; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_q31[index]; + b = sinTable_q31[index+1]; + + /* Linear interpolation process */ + cosVal = (q63_t) (0x80000000 - fract) * a >> 32; + cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) fract * b)) >> 32); + + /* Return output value */ + return (cosVal << 1); +} + +/** + @} end of cos group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_divide_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_divide_q15.c new file mode 100644 index 00000000..9c26e06e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_divide_q15.c @@ -0,0 +1,110 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cos_q15.c + * Description: Fast cosine calculation for Q15 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +#include + +/** + @ingroup groupFastMath + */ + +/** + @defgroup divide Fixed point division + + */ + +/** + @addtogroup divide + @{ + */ + +/** + @brief Fixed point division + @param[in] numerator Numerator + @param[in] denominator Denominator + @param[out] quotient Quotient value normalized between -1.0 and 1.0 + @param[out] shift Shift left value to get the unnormalized quotient + @return error status + + When dividing by 0, an error ARM_MATH_NANINF is returned. And the quotient is forced + to the saturated negative or positive value. + */ + +arm_status arm_divide_q15(q15_t numerator, + q15_t denominator, + q15_t *quotient, + int16_t *shift) +{ + int16_t sign=0; + q31_t temp; + int16_t shiftForNormalizing; + + *shift = 0; + + sign = (numerator>>15) ^ (denominator>>15); + + if (denominator == 0) + { + if (sign) + { + *quotient = 0x8000; + } + else + { + *quotient = 0x7FFF; + } + return(ARM_MATH_NANINF); + } + + arm_abs_q15(&numerator,&numerator,1); + arm_abs_q15(&denominator,&denominator,1); + + temp = ((q31_t)numerator << 15) / ((q31_t)denominator); + + shiftForNormalizing= 17 - __CLZ(temp); + if (shiftForNormalizing > 0) + { + *shift = shiftForNormalizing; + temp = temp >> shiftForNormalizing; + } + + if (sign) + { + temp = -temp; + } + + *quotient=temp; + + return(ARM_MATH_SUCCESS); +} + +/** + @} end of divide group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_divide_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_divide_q31.c new file mode 100644 index 00000000..12b727f8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_divide_q31.c @@ -0,0 +1,110 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cos_q31.c + * Description: Fast cosine calculation for Q31 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +#include + +/** + @ingroup groupFastMath + */ + +/** + @defgroup divide Fixed point division + + */ + +/** + @addtogroup divide + @{ + */ + +/** + @brief Fixed point division + @param[in] numerator Numerator + @param[in] denominator Denominator + @param[out] quotient Quotient value normalized between -1.0 and 1.0 + @param[out] shift Shift left value to get the unnormalized quotient + @return error status + + When dividing by 0, an error ARM_MATH_NANINF is returned. And the quotient is forced + to the saturated negative or positive value. + */ + +arm_status arm_divide_q31(q31_t numerator, + q31_t denominator, + q31_t *quotient, + int16_t *shift) +{ + int16_t sign=0; + q63_t temp; + int16_t shiftForNormalizing; + + *shift = 0; + + sign = (numerator>>31) ^ (denominator>>31); + + if (denominator == 0) + { + if (sign) + { + *quotient = 0x80000000; + } + else + { + *quotient = 0x7FFFFFFF; + } + return(ARM_MATH_NANINF); + } + + arm_abs_q31(&numerator,&numerator,1); + arm_abs_q31(&denominator,&denominator,1); + + temp = ((q63_t)numerator << 31) / ((q63_t)denominator); + + shiftForNormalizing= 32 - __CLZ(temp >> 31); + if (shiftForNormalizing > 0) + { + *shift = shiftForNormalizing; + temp = temp >> shiftForNormalizing; + } + + if (sign) + { + temp = -temp; + } + + *quotient=(q31_t)temp; + + return(ARM_MATH_SUCCESS); +} + +/** + @} end of divide group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c new file mode 100644 index 00000000..2fcd6bb1 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sin_f32.c + * Description: Fast sine calculation for floating-point values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @defgroup sin Sine + + Computes the trigonometric sine function using a combination of table lookup + and linear interpolation. There are separate functions for + Q15, Q31, and floating-point data types. + The input to the floating-point version is in radians while the + fixed-point Q15 and Q31 have a scaled input with the range + [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a + value of 2*pi wraps around to 0. + + The implementation is based on table lookup using 512 values together with linear interpolation. + The steps used are: + -# Calculation of the nearest integer table index + -# Compute the fractional portion (fract) of the table index. + -# The final result equals (1.0f-fract)*a + fract*b; + + where +
+     b = Table[index];
+     c = Table[index+1];
+  
+ */ + +/** + @addtogroup sin + @{ + */ + +/** + @brief Fast approximation to the trigonometric sine function for floating-point data. + @param[in] x input value in radians. + @return sin(x) + */ + +float32_t arm_sin_f32( + float32_t x) +{ + float32_t sinVal, fract, in; /* Temporary input, output variables */ + uint16_t index; /* Index variable */ + float32_t a, b; /* Two nearest output values */ + int32_t n; + float32_t findex; + + /* input x is in radians */ + /* Scale input to [0 1] range from [0 2*PI] , divide input by 2*pi */ + in = x * 0.159154943092f; + + /* Calculation of floor value of input */ + n = (int32_t) in; + + /* Make negative values towards -infinity */ + if (in < 0.0f) + { + n--; + } + + /* Map input value to [0 1] */ + in = in - (float32_t) n; + + /* Calculation of index of the table */ + findex = (float32_t)FAST_MATH_TABLE_SIZE * in; + index = (uint16_t)findex; + + /* when "in" is exactly 1, we need to rotate the index down to 0 */ + if (index >= FAST_MATH_TABLE_SIZE) { + index = 0; + findex -= (float32_t)FAST_MATH_TABLE_SIZE; + } + + /* fractional value calculation */ + fract = findex - (float32_t) index; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_f32[index]; + b = sinTable_f32[index+1]; + + /* Linear interpolation process */ + sinVal = (1.0f - fract) * a + fract * b; + + /* Return output value */ + return (sinVal); +} + +/** + @} end of sin group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c new file mode 100644 index 00000000..81f0d627 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c @@ -0,0 +1,83 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sin_q15.c + * Description: Fast sine calculation for Q15 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup sin + @{ + */ + +/** + @brief Fast approximation to the trigonometric sine function for Q15 data. + @param[in] x Scaled input value in radians + @return sin(x) + + The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*PI). + */ + +q15_t arm_sin_q15( + q15_t x) +{ + q15_t sinVal; /* Temporary input, output variables */ + int32_t index; /* Index variable */ + q15_t a, b; /* Two nearest output values */ + q15_t fract; /* Temporary values for fractional values */ + + + if (x < 0) + { /* convert negative numbers to corresponding positive ones */ + x = (uint16_t)x + 0x8000; + } + + /* Calculate the nearest index */ + index = (uint32_t)x >> FAST_MATH_Q15_SHIFT; + + /* Calculation of fractional value */ + fract = (x - (index << FAST_MATH_Q15_SHIFT)) << 9; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_q15[index]; + b = sinTable_q15[index+1]; + + /* Linear interpolation process */ + sinVal = (q31_t) (0x8000 - fract) * a >> 16; + sinVal = (q15_t) ((((q31_t) sinVal << 16) + ((q31_t) fract * b)) >> 16); + + /* Return output value */ + return (sinVal << 1); +} + +/** + @} end of sin group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c new file mode 100644 index 00000000..06262fd5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c @@ -0,0 +1,82 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sin_q31.c + * Description: Fast sine calculation for Q31 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup sin + @{ + */ + +/** + @brief Fast approximation to the trigonometric sine function for Q31 data. + @param[in] x Scaled input value in radians + @return sin(x) + + The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*PI). + */ + +q31_t arm_sin_q31( + q31_t x) +{ + q31_t sinVal; /* Temporary variables for input, output */ + int32_t index; /* Index variable */ + q31_t a, b; /* Two nearest output values */ + q31_t fract; /* Temporary values for fractional values */ + + if (x < 0) + { /* convert negative numbers to corresponding positive ones */ + x = (uint32_t)x + 0x80000000; + } + + /* Calculate the nearest index */ + index = (uint32_t)x >> FAST_MATH_Q31_SHIFT; + + /* Calculation of fractional value */ + fract = (x - (index << FAST_MATH_Q31_SHIFT)) << 9; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_q31[index]; + b = sinTable_q31[index+1]; + + /* Linear interpolation process */ + sinVal = (q63_t) (0x80000000 - fract) * a >> 32; + sinVal = (q31_t) ((((q63_t) sinVal << 32) + ((q63_t) fract * b)) >> 32); + + /* Return output value */ + return (sinVal << 1); +} + +/** + @} end of sin group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c new file mode 100644 index 00000000..defeebe8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c @@ -0,0 +1,123 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sqrt_q15.c + * Description: Q15 square root function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup SQRT + @{ + */ + +/** + @brief Q15 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ + +#define Q12QUARTER 0x2000 +arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut) +{ + q15_t number, var1, signBits1,temp; + + number = in; + + /* If the input is a positive number then compute the signBits. */ + if (number > 0) + { + signBits1 = __CLZ(number) - 17; + + /* Shift by the number of signBits1 */ + if ((signBits1 % 2) == 0) + { + number = number << signBits1; + } + else + { + number = number << (signBits1 - 1); + } + /* Start value for 1/sqrt(x) for the Newton iteration */ + var1 = sqrt_initial_lut_q15[(number>> 11) - (Q12QUARTER >> 11)]; + + /* 0.5 var1 * (3 - number * var1 * var1) */ + /* 1st iteration */ + + temp = ((q31_t) var1 * var1) >> 12; + temp = ((q31_t) number * temp) >> 15; + temp = 0x3000 - temp; + var1 = ((q31_t) var1 * temp) >> 13; + + temp = ((q31_t) var1 * var1) >> 12; + temp = ((q31_t) number * temp) >> 15; + temp = 0x3000 - temp; + var1 = ((q31_t) var1 * temp) >> 13; + + temp = ((q31_t) var1 * var1) >> 12; + temp = ((q31_t) number * temp) >> 15; + temp = 0x3000 - temp; + var1 = ((q31_t) var1 * temp) >> 13; + + /* Multiply the inverse square root with the original value */ + + var1 = ((q15_t) (((q31_t) number * var1) >> 12)); + + /* Shift the output down accordingly */ + if ((signBits1 % 2) == 0) + { + var1 = var1 >> (signBits1 / 2); + } + else + { + var1 = var1 >> ((signBits1 - 1) / 2); + } + *pOut = var1; + + + return (ARM_MATH_SUCCESS); + } + /* If the number is a negative number then store zero as its square root value */ + else + { + *pOut = 0; + + return (ARM_MATH_ARGUMENT_ERROR); + } +} + +/** + @} end of SQRT group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c new file mode 100644 index 00000000..8747670d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sqrt_q31.c + * Description: Q31 square root function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup SQRT + @{ + */ + +/** + @brief Q31 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +#define Q28QUARTER 0x20000000 + +arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut) +{ + q31_t number, var1, signBits1 ,temp; + + number = in; + + /* If the input is a positive number then compute the signBits. */ + if (number > 0) + { + signBits1 = __CLZ(number) - 1; + + /* Shift by the number of signBits1 */ + if ((signBits1 % 2) == 0) + { + number = number << signBits1; + } + else + { + number = number << (signBits1 - 1); + } + + /* Start value for 1/sqrt(x) for the Newton iteration */ + var1 = sqrt_initial_lut_q31[(number>> 26) - (Q28QUARTER >> 26)]; + + /* 0.5 var1 * (3 - number * var1 * var1) */ + + /* 1st iteration */ + + temp = ((q63_t) var1 * var1) >> 28; + temp = ((q63_t) number * temp) >> 31; + temp = 0x30000000 - temp; + var1 = ((q63_t) var1 * temp) >> 29; + + + /* 2nd iteration */ + temp = ((q63_t) var1 * var1) >> 28; + temp = ((q63_t) number * temp) >> 31; + temp = 0x30000000 - temp; + var1 = ((q63_t) var1 * temp) >> 29; + + /* 3nd iteration */ + temp = ((q63_t) var1 * var1) >> 28; + temp = ((q63_t) number * temp) >> 31; + temp = 0x30000000 - temp; + var1 = ((q63_t) var1 * temp) >> 29; + + /* Multiply the inverse square root with the original value */ + var1 = ((q31_t) (((q63_t) number * var1) >> 28)); + + /* Shift the output down accordingly */ + if ((signBits1 % 2) == 0) + { + var1 = var1 >> (signBits1 / 2); + } + else + { + var1 = var1 >> ((signBits1 - 1) / 2); + } + *pOut = var1; + + return (ARM_MATH_SUCCESS); + } + /* If the number is a negative number then store zero as its square root value */ + else + { + *pOut = 0; + + return (ARM_MATH_ARGUMENT_ERROR); + } +} + +/** + @} end of SQRT group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f16.c new file mode 100644 index 00000000..dd7c06ee --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f16.c @@ -0,0 +1,82 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_f16.c + * Description: Fast vectorized log + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include "arm_common_tables.h" + +#include "arm_vec_math_f16.h" + + +void arm_vexp_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + + f16x8_t src; + f16x8_t dst; + + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + src = vld1q(pSrc); + dst = vexpq_f16(src); + vst1q(pDst, dst); + + pSrc += 8; + pDst += 8; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 7; +#else + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = (_Float16)expf((float32_t)*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f32.c new file mode 100644 index 00000000..43b2a86d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f32.c @@ -0,0 +1,97 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_f32.c + * Description: Fast vectorized log + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM) || defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_vec_math.h" +#endif + +void arm_vexp_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t src; + f32x4_t dst; + + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + src = vld1q(pSrc); + dst = vexpq_f32(src); + vst1q(pDst, dst); + + pSrc += 4; + pDst += 4; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 3; +#else +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t src; + f32x4_t dst; + + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + src = vld1q_f32(pSrc); + dst = vexpq_f32(src); + vst1q_f32(pDst, dst); + + pSrc += 4; + pDst += 4; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 3; +#else + blkCnt = blockSize; +#endif +#endif + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = expf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f64.c new file mode 100644 index 00000000..76f80ff5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f64.c @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_f64.c + * Description: Fast vectorized log + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +void arm_vexp_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = exp(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vinverse_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vinverse_f16.c new file mode 100644 index 00000000..1067d02f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vinverse_f16.c @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vinverse_f16.c + * Description: Fast vectorized inverse + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include "arm_common_tables.h" + +#include "arm_vec_math_f16.h" + +void arm_vinverse_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + + f16x8_t src; + f16x8_t dst; + + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + src = vld1q(pSrc); + dst = vrecip_hiprec_f16(src); + vst1q(pDst, dst); + + pSrc += 8; + pDst += 8; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 7; +#else + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + + *pDst++ = 1.0f16 / (_Float16)*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f16.c new file mode 100644 index 00000000..0821d5ab --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f16.c @@ -0,0 +1,222 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_f16.c + * Description: Fast vectorized log + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions_f16.h" +#include "dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/* Degree of the polynomial approximation */ +#define NB_DEG_LOGF16 3 + +/* +Related to the Log2 of the number of approximations. +For instance, with 3 there are 1 + 2^3 polynomials +*/ +#define NB_DIV_LOGF16 3 + +/* Length of the LUT table */ +#define NB_LUT_LOGF16 (NB_DEG_LOGF16+1)*(1 + (1< 1000][[2, 1]], {i, 1, 2, (1.0/2^nb)}]; +coefs = Chop@Flatten[CoefficientList[lut, x]]; + +*/ +static float16_t lut_logf16[NB_LUT_LOGF16]={ + 0,0.125,-0.00781197,0.00063974,0.117783, + 0.111111,-0.00617212,0.000447935,0.223144, + 0.1,-0.00499952,0.000327193,0.318454,0.0909091, + -0.00413191,0.000246234,0.405465,0.0833333, + -0.00347199,0.000189928,0.485508,0.0769231, + -0.00295841,0.00014956,0.559616,0.0714286, + -0.0025509,0.000119868,0.628609,0.0666667, + -0.00222213,0.0000975436,0.693147, + 0.0625,-0.00195305,0.0000804357}; + + +float16_t logf16_scalar(float16_t x) +{ + int16_t i = arm_typecast_s16_f16(x); + + int32_t vecExpUnBiased = (i >> 10) - 15; + i = i - (vecExpUnBiased << 10); + float16_t vecTmpFlt1 = arm_typecast_f16_s16(i); + + float16_t *lut; + int n; + float16_t tmp,v; + + tmp = ((_Float16)vecTmpFlt1 - 1.0f16) * (1 << NB_DIV_LOGF16); + n = (int)floor((double)tmp); + v = (_Float16)tmp - (_Float16)n; + + lut = lut_logf16 + n * (1+NB_DEG_LOGF16); + + float16_t res = lut[NB_DEG_LOGF16-1]; + for(int j=NB_DEG_LOGF16-2; j >=0 ; j--) + { + res = (_Float16)lut[j] + (_Float16)v * (_Float16)res; + } + + res = (_Float16)res + 0.693147f16 * (_Float16)vecExpUnBiased; + + + return(res); +} + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_common_tables.h" +#include "arm_vec_math_f16.h" + + +float16x8_t vlogq_lut_f16(float16x8_t vecIn) +{ + int16x8_t i = vreinterpretq_s16_f16(vecIn); + + int16x8_t vecExpUnBiased = vsubq_n_s16(vshrq_n_s16(i,10), 15); + i = vsubq_s16(i,vshlq_n_s16(vecExpUnBiased,10)); + float16x8_t vecTmpFlt1 = vreinterpretq_f16_s16(i); + + + float16x8_t lutV; + int16x8_t n; + int16x8_t offset; + + float16x8_t tmp,v,res; + + tmp = vmulq_n_f16(vsubq_n_f16(vecTmpFlt1,1.0f16),(_Float16)(1 << NB_DIV_LOGF16)); + + n = vcvtq_s16_f16(tmp); + v = vsubq_f16(tmp,vcvtq_f16_s16(n)); + + + offset = vmulq_n_s16(n,(1+NB_DEG_LOGF16)); + offset = vaddq_n_s16(offset,NB_DEG_LOGF16-1); + + res = vldrhq_gather_shifted_offset_f16(lut_logf16,(uint16x8_t)offset); + offset = vsubq_n_s16(offset,1); + + for(int j=NB_DEG_LOGF16-2; j >=0 ; j--) + { + lutV = vldrhq_gather_shifted_offset_f16(lut_logf16,(uint16x8_t)offset); + res = vfmaq_f16(lutV,v,res); + offset = vsubq_n_s16(offset,1); + + } + + res = vfmaq_n_f16(res,vcvtq_f16_s16(vecExpUnBiased),0.693147f16); + + + return(res); + +} + +#endif + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup vlog + @{ + */ + +/** + @brief Floating-point vector of log values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + + +void arm_vlog_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + f16x8_t src; + f16x8_t dst; + + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + src = vld1q(pSrc); + dst = vlogq_lut_f16(src); + vst1q(pDst, dst); + + pSrc += 8; + pDst += 8; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 7; +#else + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = logf16_scalar(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} + + + +/** + @} end of vlog group + */ + + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f32.c new file mode 100644 index 00000000..888a11f3 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f32.c @@ -0,0 +1,119 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_f32.c + * Description: Fast vectorized log + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + + +/** + @ingroup groupFastMath + */ + + +/** + @defgroup vlog Vector Log + + Compute the log values of a vector of samples. + + */ + +/** + @addtogroup vlog + @{ + */ + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM) || defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_vec_math.h" +#endif + +void arm_vlog_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t src; + f32x4_t dst; + + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + src = vld1q(pSrc); + dst = vlogq_f32(src); + vst1q(pDst, dst); + + pSrc += 4; + pDst += 4; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 3; +#else +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t src; + f32x4_t dst; + + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + src = vld1q_f32(pSrc); + dst = vlogq_f32(src); + vst1q_f32(pDst, dst); + + pSrc += 4; + pDst += 4; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 3; +#else + blkCnt = blockSize; +#endif +#endif + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = logf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} + +/** + @} end of vlog group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f64.c new file mode 100644 index 00000000..a60fff69 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f64.c @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_f64.c + * Description: Fast vectorized log + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +void arm_vlog_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = log(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_q15.c new file mode 100644 index 00000000..896988dc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_q15.c @@ -0,0 +1,264 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_q15 + * Description: Q15 vector log + * + * $Date: 19 July 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include "dsp/fast_math_functions.h" + + +#define LOG_Q15_ACCURACY 15 + +/* Bit to represent the normalization factor + It is Ceiling[Log2[LOG_Q15_ACCURACY]] of the previous value. + The Log2 algorithm is assuming that the value x is + 1 <= x < 2. + + But input value could be as small a 2^-LOG_Q15_ACCURACY + which would give an integer part of -15. +*/ +#define LOG_Q15_INTEGER_PART 4 + +/* 2.0 in q14 */ +#define LOQ_Q15_THRESHOLD (1u << LOG_Q15_ACCURACY) + +/* HALF */ +#define LOQ_Q15_Q16_HALF LOQ_Q15_THRESHOLD +#define LOQ_Q15_Q14_HALF (LOQ_Q15_Q16_HALF >> 2) + + +/* 1.0 / Log2[Exp[1]] in q15 */ +#define LOG_Q15_INVLOG2EXP 0x58b9u + + +/* Clay Turner algorithm */ +static uint16_t arm_scalar_log_q15(uint16_t src) +{ + int i; + + int16_t c = __CLZ(src)-16; + int16_t normalization=0; + + /* 0.5 in q11 */ + uint16_t inc = LOQ_Q15_Q16_HALF >> (LOG_Q15_INTEGER_PART + 1); + + /* Will compute y = log2(x) for 1 <= x < 2.0 */ + uint16_t x; + + /* q11 */ + uint16_t y=0; + + /* q11 */ + int16_t tmp; + + + /* Normalize and convert to q14 format */ + x = src; + if ((c-1) < 0) + { + x = x >> (1-c); + } + else + { + x = x << (c-1); + } + normalization = c; + + + + /* Compute the Log2. Result is in q11 instead of q16 + because we know 0 <= y < 1.0 but + we want a result allowing to do a + product on int16 rather than having to go + through int32 + */ + for(i = 0; i < LOG_Q15_ACCURACY ; i++) + { + x = (((int32_t)x*x)) >> (LOG_Q15_ACCURACY - 1); + + if (x >= LOQ_Q15_THRESHOLD) + { + y += inc ; + x = x >> 1; + } + inc = inc >> 1; + } + + + /* + Convert the Log2 to Log and apply normalization. + We compute (y - normalisation) * (1 / Log2[e]). + + */ + + /* q11 */ + //tmp = y - ((int32_t)normalization << (LOG_Q15_ACCURACY + 1)); + tmp = (int16_t)y - (normalization << (LOG_Q15_ACCURACY - LOG_Q15_INTEGER_PART)); + + /* q4.11 */ + y = ((int32_t)tmp * LOG_Q15_INVLOG2EXP) >> 15; + + return(y); + +} + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + + +q15x8_t vlogq_q15(q15x8_t src) +{ + + int i; + + int16x8_t c = vclzq_s16(src); + int16x8_t normalization = c; + + + /* 0.5 in q11 */ + uint16_t inc = LOQ_Q15_Q16_HALF >> (LOG_Q15_INTEGER_PART + 1); + + /* Will compute y = log2(x) for 1 <= x < 2.0 */ + uint16x8_t x; + + + /* q11 */ + uint16x8_t y = vdupq_n_u16(0); + + + /* q11 */ + int16x8_t vtmp; + + + mve_pred16_t p; + + /* Normalize and convert to q14 format */ + + + vtmp = vsubq_n_s16(c,1); + x = vshlq_u16((uint16x8_t)src,vtmp); + + + /* Compute the Log2. Result is in q11 instead of q16 + because we know 0 <= y < 1.0 but + we want a result allowing to do a + product on int16 rather than having to go + through int32 + */ + for(i = 0; i < LOG_Q15_ACCURACY ; i++) + { + x = vmulhq_u16(x,x); + x = vshlq_n_u16(x,2); + + + p = vcmphiq_u16(x,vdupq_n_u16(LOQ_Q15_THRESHOLD)); + y = vaddq_m_n_u16(y, y,inc,p); + x = vshrq_m_n_u16(x,x,1,p); + + inc = inc >> 1; + } + + + /* + Convert the Log2 to Log and apply normalization. + We compute (y - normalisation) * (1 / Log2[e]). + + */ + + /* q11 */ + // tmp = (int16_t)y - (normalization << (LOG_Q15_ACCURACY - LOG_Q15_INTEGER_PART)); + vtmp = vshlq_n_s16(normalization,LOG_Q15_ACCURACY - LOG_Q15_INTEGER_PART); + vtmp = vsubq_s16((int16x8_t)y,vtmp); + + + + /* q4.11 */ + // y = ((int32_t)tmp * LOG_Q15_INVLOG2EXP) >> 15; + vtmp = vqdmulhq_n_s16(vtmp,LOG_Q15_INVLOG2EXP); + + return(vtmp); +} +#endif + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup vlog + @{ + */ + +/** + @brief q15 vector of log values. + @param[in] pSrc points to the input vector in q15 + @param[out] pDst points to the output vector in q4.11 + @param[in] blockSize number of samples in each vector + @return none + + */ + +void arm_vlog_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + q15x8_t src; + q15x8_t dst; + + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + src = vld1q(pSrc); + dst = vlogq_q15(src); + vst1q(pDst, dst); + + pSrc += 8; + pDst += 8; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 7; + #else + blkCnt = blockSize; + #endif + + while (blkCnt > 0U) + { + *pDst++ = arm_scalar_log_q15(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} + +/** + @} end of vlog group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_q31.c new file mode 100644 index 00000000..00538594 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_q31.c @@ -0,0 +1,258 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_q31 + * Description: Q31 vector log + * + * $Date: 19 July 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" + +#define LOG_Q31_ACCURACY 31 + +/* Bit to represent the normalization factor + It is Ceiling[Log2[LOG_Q31_ACCURACY]] of the previous value. + The Log2 algorithm is assuming that the value x is + 1 <= x < 2. + + But input value could be as small a 2^-LOG_Q31_ACCURACY + which would give an integer part of -31. +*/ +#define LOG_Q31_INTEGER_PART 5 + +/* 2.0 in Q30 */ +#define LOQ_Q31_THRESHOLD (1u << LOG_Q31_ACCURACY) + +/* HALF */ +#define LOQ_Q31_Q32_HALF LOQ_Q31_THRESHOLD +#define LOQ_Q31_Q30_HALF (LOQ_Q31_Q32_HALF >> 2) + + +/* 1.0 / Log2[Exp[1]] in Q31 */ +#define LOG_Q31_INVLOG2EXP 0x58b90bfbuL + +/* Clay Turner algorithm */ +static uint32_t arm_scalar_log_q31(uint32_t src) +{ + int32_t i; + + int32_t c = __CLZ(src); + int32_t normalization=0; + + /* 0.5 in q26 */ + uint32_t inc = LOQ_Q31_Q32_HALF >> (LOG_Q31_INTEGER_PART + 1); + + /* Will compute y = log2(x) for 1 <= x < 2.0 */ + uint32_t x; + + /* q26 */ + uint32_t y=0; + + /* q26 */ + int32_t tmp; + + + /* Normalize and convert to q30 format */ + x = src; + if ((c-1) < 0) + { + x = x >> (1-c); + } + else + { + x = x << (c-1); + } + normalization = c; + + /* Compute the Log2. Result is in q26 + because we know 0 <= y < 1.0 but + do not want to use q32 to allow + following computation with less instructions. + */ + for(i = 0; i < LOG_Q31_ACCURACY ; i++) + { + x = ((int64_t)x*x) >> (LOG_Q31_ACCURACY - 1); + + if (x >= LOQ_Q31_THRESHOLD) + { + y += inc ; + x = x >> 1; + } + inc = inc >> 1; + } + + /* + Convert the Log2 to Log and apply normalization. + We compute (y - normalisation) * (1 / Log2[e]). + + */ + + /* q26 */ + tmp = (int32_t)y - (normalization << (LOG_Q31_ACCURACY - LOG_Q31_INTEGER_PART)); + + + /* q5.26 */ + y = ((int64_t)tmp * LOG_Q31_INVLOG2EXP) >> 31; + + + + return(y); + +} + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + + +q31x4_t vlogq_q31(q31x4_t src) +{ + + int32_t i; + + int32x4_t c = vclzq_s32(src); + int32x4_t normalization = c; + + + /* 0.5 in q11 */ + uint32_t inc = LOQ_Q31_Q32_HALF >> (LOG_Q31_INTEGER_PART + 1); + + /* Will compute y = log2(x) for 1 <= x < 2.0 */ + uint32x4_t x; + + + /* q11 */ + uint32x4_t y = vdupq_n_u32(0); + + + /* q11 */ + int32x4_t vtmp; + + + mve_pred16_t p; + + /* Normalize and convert to q14 format */ + + + vtmp = vsubq_n_s32(c,1); + x = vshlq_u32((uint32x4_t)src,vtmp); + + + /* Compute the Log2. Result is in Q26 + because we know 0 <= y < 1.0 but + do not want to use Q32 to allow + following computation with less instructions. + */ + for(i = 0; i < LOG_Q31_ACCURACY ; i++) + { + x = vmulhq_u32(x,x); + x = vshlq_n_u32(x,2); + + + p = vcmphiq_u32(x,vdupq_n_u32(LOQ_Q31_THRESHOLD)); + y = vaddq_m_n_u32(y, y,inc,p); + x = vshrq_m_n_u32(x,x,1,p); + + inc = inc >> 1; + } + + + /* + Convert the Log2 to Log and apply normalization. + We compute (y - normalisation) * (1 / Log2[e]). + + */ + + /* q11 */ + // tmp = (int16_t)y - (normalization << (LOG_Q15_ACCURACY - LOG_Q15_INTEGER_PART)); + vtmp = vshlq_n_s32(normalization,LOG_Q31_ACCURACY - LOG_Q31_INTEGER_PART); + vtmp = vsubq_s32((int32x4_t)y,vtmp); + + + + /* q4.11 */ + // y = ((int32_t)tmp * LOG_Q15_INVLOG2EXP) >> 15; + vtmp = vqdmulhq_n_s32(vtmp,LOG_Q31_INVLOG2EXP); + + return(vtmp); +} +#endif + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup vlog + @{ + */ + +/** + @brief q31 vector of log values. + @param[in] pSrc points to the input vector in q31 + @param[out] pDst points to the output vector q5.26 + @param[in] blockSize number of samples in each vector + @return none + + */ +void arm_vlog_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + + q31x4_t src; + q31x4_t dst; + + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + src = vld1q(pSrc); + dst = vlogq_q31(src); + vst1q(pDst, dst); + + pSrc += 4; + pDst += 4; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 3; + #else + blkCnt = blockSize; + #endif + + while (blkCnt > 0U) + { + *pDst++=arm_scalar_log_q31(*pSrc++); + + blkCnt--; + } + +} + +/** + @} end of vlog group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/CMakeLists.txt new file mode 100644 index 00000000..9f6ea5df --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/CMakeLists.txt @@ -0,0 +1,148 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPFiltering) + +include(configLib) +include(configDsp) + +add_library(CMSISDSPFiltering STATIC) + +include(interpol) +interpol(CMSISDSPFiltering) + +configLib(CMSISDSPFiltering ${ROOT}) +configDsp(CMSISDSPFiltering ${ROOT}) + +if (CONFIGTABLE AND ALLFAST) +target_compile_definitions(CMSISDSPFiltering PUBLIC ARM_ALL_FAST_TABLES) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_LMS_NORM_Q31) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_norm_init_q31.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_LMS_NORM_Q15) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_norm_init_q15.c) +endif() + +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_32x64_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_32x64_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_fast_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_fast_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df2T_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df2T_f64.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df2T_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df2T_init_f64.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_stereo_df2T_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_stereo_df2T_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_fast_opt_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_fast_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_fast_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_opt_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_opt_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_fast_opt_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_fast_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_fast_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_opt_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_opt_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_f64.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_fast_opt_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_fast_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_fast_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_opt_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_opt_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_fast_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_fast_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_f64.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_fast_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_fast_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_init_f64.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_init_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_interpolate_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_interpolate_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_interpolate_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_interpolate_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_interpolate_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_interpolate_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_lattice_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_lattice_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_lattice_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_lattice_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_lattice_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_lattice_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_init_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_iir_lattice_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_iir_lattice_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_iir_lattice_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_iir_lattice_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_iir_lattice_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_iir_lattice_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_norm_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_norm_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_norm_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_norm_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_levinson_durbin_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_levinson_durbin_q31.c) + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_f16.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_init_f16.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_f16.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_init_f16.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df2T_f16.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df2T_init_f16.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_stereo_df2T_f16.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_stereo_df2T_init_f16.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_f16.c) +target_sources(CMSISDSPFiltering PRIVATE arm_levinson_durbin_f16.c) +endif() + +### Includes +target_include_directories(CMSISDSPFiltering PUBLIC "${DSP}/Include") + + + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c new file mode 100644 index 00000000..e1b26fd7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c @@ -0,0 +1,139 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: FilteringFunctions.c + * Description: Combination of all filtering function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_biquad_cascade_df1_32x64_init_q31.c" +#include "arm_biquad_cascade_df1_32x64_q31.c" +#include "arm_biquad_cascade_df1_f32.c" +#include "arm_biquad_cascade_df1_fast_q15.c" +#include "arm_biquad_cascade_df1_fast_q31.c" +#include "arm_biquad_cascade_df1_init_f32.c" +#include "arm_biquad_cascade_df1_init_q15.c" +#include "arm_biquad_cascade_df1_init_q31.c" +#include "arm_biquad_cascade_df1_q15.c" +#include "arm_biquad_cascade_df1_q31.c" +#include "arm_biquad_cascade_df2T_f32.c" +#include "arm_biquad_cascade_df2T_f64.c" +#include "arm_biquad_cascade_df2T_init_f32.c" +#include "arm_biquad_cascade_df2T_init_f64.c" +#include "arm_biquad_cascade_stereo_df2T_f32.c" +#include "arm_biquad_cascade_stereo_df2T_init_f32.c" +#include "arm_conv_f32.c" +#include "arm_conv_fast_opt_q15.c" +#include "arm_conv_fast_q15.c" +#include "arm_conv_fast_q31.c" +#include "arm_conv_opt_q15.c" +#include "arm_conv_opt_q7.c" +#include "arm_conv_partial_f32.c" +#include "arm_conv_partial_fast_opt_q15.c" +#include "arm_conv_partial_fast_q15.c" +#include "arm_conv_partial_fast_q31.c" +#include "arm_conv_partial_opt_q15.c" +#include "arm_conv_partial_opt_q7.c" +#include "arm_conv_partial_q15.c" +#include "arm_conv_partial_q31.c" +#include "arm_conv_partial_q7.c" +#include "arm_conv_q15.c" +#include "arm_conv_q31.c" +#include "arm_conv_q7.c" +#include "arm_correlate_f32.c" +#include "arm_correlate_f64.c" +#include "arm_correlate_fast_opt_q15.c" +#include "arm_correlate_fast_q15.c" +#include "arm_correlate_fast_q31.c" +#include "arm_correlate_opt_q15.c" +#include "arm_correlate_opt_q7.c" +#include "arm_correlate_q15.c" +#include "arm_correlate_q31.c" +#include "arm_correlate_q7.c" +#include "arm_fir_decimate_f32.c" +#include "arm_fir_decimate_fast_q15.c" +#include "arm_fir_decimate_fast_q31.c" +#include "arm_fir_decimate_init_f32.c" +#include "arm_fir_decimate_init_q15.c" +#include "arm_fir_decimate_init_q31.c" +#include "arm_fir_decimate_q15.c" +#include "arm_fir_decimate_q31.c" +#include "arm_fir_f32.c" +#include "arm_fir_f64.c" +#include "arm_fir_fast_q15.c" +#include "arm_fir_fast_q31.c" +#include "arm_fir_init_f32.c" +#include "arm_fir_init_f64.c" +#include "arm_fir_init_q15.c" +#include "arm_fir_init_q31.c" +#include "arm_fir_init_q7.c" +#include "arm_fir_interpolate_f32.c" +#include "arm_fir_interpolate_init_f32.c" +#include "arm_fir_interpolate_init_q15.c" +#include "arm_fir_interpolate_init_q31.c" +#include "arm_fir_interpolate_q15.c" +#include "arm_fir_interpolate_q31.c" +#include "arm_fir_lattice_f32.c" +#include "arm_fir_lattice_init_f32.c" +#include "arm_fir_lattice_init_q15.c" +#include "arm_fir_lattice_init_q31.c" +#include "arm_fir_lattice_q15.c" +#include "arm_fir_lattice_q31.c" +#include "arm_fir_q15.c" +#include "arm_fir_q31.c" +#include "arm_fir_q7.c" +#include "arm_fir_sparse_f32.c" +#include "arm_fir_sparse_init_f32.c" +#include "arm_fir_sparse_init_q15.c" +#include "arm_fir_sparse_init_q31.c" +#include "arm_fir_sparse_init_q7.c" +#include "arm_fir_sparse_q15.c" +#include "arm_fir_sparse_q31.c" +#include "arm_fir_sparse_q7.c" +#include "arm_iir_lattice_f32.c" +#include "arm_iir_lattice_init_f32.c" +#include "arm_iir_lattice_init_q15.c" +#include "arm_iir_lattice_init_q31.c" +#include "arm_iir_lattice_q15.c" +#include "arm_iir_lattice_q31.c" +#include "arm_lms_f32.c" +#include "arm_lms_init_f32.c" +#include "arm_lms_init_q15.c" +#include "arm_lms_init_q31.c" +#include "arm_lms_norm_f32.c" +#include "arm_lms_norm_init_f32.c" +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15) +#include "arm_lms_norm_init_q15.c" +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31) +#include "arm_lms_norm_init_q31.c" +#endif +#endif +#include "arm_lms_norm_q15.c" +#include "arm_lms_norm_q31.c" +#include "arm_lms_q15.c" +#include "arm_lms_q31.c" + +#include "arm_levinson_durbin_f32.c" +#include "arm_levinson_durbin_q31.c" diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctionsF16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctionsF16.c new file mode 100644 index 00000000..759e4058 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctionsF16.c @@ -0,0 +1,36 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: FilteringFunctions.c + * Description: Combination of all filtering function f16 source files. + * + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_fir_f16.c" +#include "arm_fir_init_f16.c" +#include "arm_biquad_cascade_df1_f16.c" +#include "arm_biquad_cascade_df1_init_f16.c" +#include "arm_biquad_cascade_df2T_f16.c" +#include "arm_biquad_cascade_df2T_init_f16.c" +#include "arm_biquad_cascade_stereo_df2T_f16.c" +#include "arm_biquad_cascade_stereo_df2T_init_f16.c" +#include "arm_correlate_f16.c" +#include "arm_levinson_durbin_f16.c" diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c new file mode 100644 index 00000000..565b494b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_32x64_init_q31.c + * Description: High precision Q31 Biquad cascade filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1_32x64 + @{ + */ + +/** + @brief Initialization function for the Q31 Biquad cascade 32x64 filter. + @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure + @param[in] numStages number of 2nd order stages in the filter + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: +
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+  
+ where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState points to state variables array and size of each state variable is 1.63 format. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the state array as: +
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+  
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign postShift to be applied to the output */ + S->postShift = postShift; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q63_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF1_32x64 group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c new file mode 100644 index 00000000..2c8c911b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c @@ -0,0 +1,807 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_32x64_q31.c + * Description: High precision Q31 Biquad cascade filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup BiquadCascadeDF1_32x64 High Precision Q31 Biquad Cascade Filter + + This function implements a high precision Biquad cascade filter which operates on + Q31 data values. The filter coefficients are in 1.31 format and the state variables + are in 1.63 format. The double precision state variables reduce quantization noise + in the filter and provide a cleaner output. + These filters are particularly useful when implementing filters in which the + singularities are close to the unit circle. This is common for low pass or high + pass filters with very low cutoff frequencies. + + The function operates on blocks of input and output data + and each call to the function processes blockSize samples through + the filter. pSrc and pDst points to input and output arrays + containing blockSize Q31 values. + + @par Algorithm + Each Biquad stage implements a second order filter using the difference equation: +
+      y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+  
+ A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage. + \image html Biquad.gif "Single Biquad filter stage" + Coefficients b0, b1 and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients. + Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. + Pay careful attention to the sign of the feedback coefficients. + Some design tools use the difference equation +
+      y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
+  
+ In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library. + @par + Higher order filters are realized as a cascade of second order sections. + numStages refers to the number of second order stages used. + For example, an 8th order filter would be realized with numStages=4 second order stages. + \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages" + A 9th order filter would be realized with numStages=5 second order stages + with the coefficients for one of the stages configured as a first order filter + (b2=0 and a2=0). + @par + The pState points to state variables array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2] and each state variable in 1.63 format to improve precision. + The state variables are arranged in the array as: +
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+  
+ @par + The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values of data in 1.63 format. + The state variables are updated after each block of data is processed, the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + + @par Init Function + There is also an associated initialization function which performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pCoeffs, postShift, pState. Also set all of the values in pState to zero. + + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + For example, to statically initialize the filter instance structure use +
+      arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};
+  
+ where numStages is the number of Biquad stages in the filter; + pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer; + postShift shift to be applied which is described in detail below. + @par Fixed-Point Behavior + Care must be taken while using Biquad Cascade 32x64 filter function. + Following issues must be considered: + - Scaling of coefficients + - Filter gain + - Overflow and saturation + + @par + Filter coefficients are represented as fractional values and + restricted to lie in the range [-1 +1). + The processing function has an additional scaling parameter postShift + which allows the filter coefficients to exceed the range [+1 -1). + At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. + \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator" + This essentially scales the filter coefficients by 2^postShift. + For example, to realize the coefficients +
+     {1.5, -0.8, 1.2, 1.6, -0.9}
+  
+ set the Coefficient array to: +
+     {0.75, -0.4, 0.6, 0.8, -0.45}
+  
+ and set postShift=1 + @par + The second thing to keep in mind is the gain through the filter. + The frequency response of a Biquad filter is a function of its coefficients. + It is possible for the gain through the filter to exceed 1.0 meaning that the + filter increases the amplitude of certain frequencies. + This means that an input signal with amplitude < 1.0 may result in an output > 1.0 + and these are saturated or overflowed based on the implementation of the filter. + To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 + or the input signal must be scaled down so that the combination of input and filter are never overflowed. + @par + The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version. + This is described in the function specific documentation below. + */ + +/** + @addtogroup BiquadCascadeDF1_32x64 + @{ + */ + +/** + @brief Processing function for the Q31 Biquad cascade 32x64 filter. + @param[in] S points to an instance of the high precision Q31 Biquad cascade filter + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Details + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25). + After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to + 1.31 format by discarding the low 32 bits. + @par + Two related functions are provided in the CMSIS DSP library. + - \ref arm_biquad_cascade_df1_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator. + - \ref arm_biquad_cascade_df1_fast_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +static void arm_biquad_cas_df1_32x64_q31_scalar(const arm_biquad_cas_df1_32x64_ins_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q63_t *pState = S->pState; /* state pointer initialization */ + const q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q63_t acc; /* accumulator */ + q31_t Xn1, Xn2; /* Input Filter state variables */ + q63_t Yn1, Yn2; /* Output Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn; /* temporary input */ + int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* loop counters */ + q31_t acc_l, acc_h; /* temporary output */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = (q31_t) (pState[0]); + Xn2 = (q31_t) (pState[1]); + Yn1 = pState[2]; + Yn2 = pState[3]; + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc = b0 * x[n] */ + acc = (q63_t) Xn * b0; + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn1 * b1; + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn2 * b2; + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn1, a1); + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn2, a2); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + + /* The result is converted to 1.63, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *pOut++ = acc_h; + /* Yn1 = acc << shift; */ + + /* Store the output in the destination buffer in 1.31 format. */ +/* *pOut++ = (q31_t) (acc >> (32 - shift)); */ + + /* decrement loop counter */ + sample--; + } + + /* The first stage output is given as input to the second stage. */ + pIn = pDst; + + /* Reset to destination buffer working pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = (q63_t) Xn1; + *pState++ = (q63_t) Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); + +} + +void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q63_t *pState = S->pState; /* state pointer initialization */ + const q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q31_t Xn1, Xn2; /* Input Filter state variables */ + q63_t Yn1, Yn2; /* Output Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* loop counters */ + q31x4_t vecCoef, vecIn; + q63_t acc; + + if (blockSize <= 3) + { + arm_biquad_cas_df1_32x64_q31_scalar(S,pSrc,pDst,blockSize); + } + else + { + do + { + uint32_t i; + /* + * Reading the coefficients + */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + vecCoef[0] = 0; + vecCoef[1] = b2; + vecCoef[2] = b1; + vecCoef[3] = b0; + /* + * Reading the state values + */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + /* + * append history with initial samples + */ + q31_t hist[6]; + hist[0] = 0; + hist[1] = Xn2; + hist[2] = Xn1; + hist[3] = pIn[0]; + hist[4] = pIn[1]; + hist[5] = pIn[2]; + + const q31_t *pIn1 = hist; + q31x4_t vecIn0 = *(q31x4_t *) & pIn[0]; + q31x4_t vecIn1 = *(q31x4_t *) & pIn[1]; + q31x4_t vecIn2 = *(q31x4_t *) & pIn[2]; + + i = 3; + do + { + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + vecIn = vld1q(pIn1); + pIn1 += 1; + Yn1 = vmlaldavaq(Yn1, vecIn, vecCoef); + Yn1 = asrl(Yn1, -shift); + /* + * Store the output in the destination buffer in 1.31 format. + */ + *pOut++ = (q31_t) (Yn1 >> 32); + } + while (--i); + + sample = blockSize - 3; + pIn1 = pIn + 3; + + i = sample / 4; + while (i > 0U) + { + + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn0, vecCoef); + vecIn = vld1q(pIn1); + pIn1 += 1; + Yn1 = asrl(Yn1, -shift); + /* + * Store the output in the destination buffer in 1.31 format. + */ + *pOut++ = (q31_t) (Yn1 >> 32); + + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn1, vecCoef); + vecIn0 = vld1q(pIn1); + pIn1 += 1; + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn2, vecCoef); + vecIn1 = vld1q(pIn1); + pIn1 += 1; + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn, vecCoef); + vecIn2 = vld1q(pIn1); + pIn1 += 1; + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + /* + * Decrement the loop counter + */ + i--; + } + /* + * save input state + */ + Xn2 = vecIn[2]; + Xn1 = vecIn[3]; + + int loopRemainder = blockSize - 3 - 4 * ((blockSize - 3) / 4); + if (loopRemainder == 1) + { + /* + * remainder + */ + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn0, vecCoef); + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + /* + * save input state + */ + Xn2 = vecIn0[2]; + Xn1 = vecIn0[3]; + + } + else if (loopRemainder == 2) + { + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn0, vecCoef); + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn1, vecCoef); + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + /* + * save input state + */ + Xn2 = vecIn1[2]; + Xn1 = vecIn1[3]; + + } + else if (loopRemainder == 3) + { + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn0, vecCoef); + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn1, vecCoef); + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn2, vecCoef); + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + /* + * save input state + */ + Xn2 = vecIn2[2]; + Xn1 = vecIn2[3]; + + } + + /* + * The first stage output is given as input to the second stage. + */ + pIn = pDst; + /* + * Reset to destination buffer working pointer + */ + pOut = pDst; + /* + * Store the updated state variables back into the pState array + */ + *pState++ = (q63_t) Xn1; + *pState++ = (q63_t) Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + } + while (--stage); + } +} +#else +void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q63_t *pState = S->pState; /* state pointer initialization */ + const q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q63_t acc; /* accumulator */ + q31_t Xn1, Xn2; /* Input Filter state variables */ + q63_t Yn1, Yn2; /* Output Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn; /* temporary input */ + int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* loop counters */ + q31_t acc_l, acc_h; /* temporary output */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = (q31_t) (pState[0]); + Xn2 = (q31_t) (pState[1]); + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variable acc hold output value that is being computed and stored in destination buffer + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc = b0 * x[n] */ + acc = (q63_t) Xn * b0; + + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn1 * b1; + + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn2 * b2; + + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn1, a1); + + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn2, a2); + + /* The result is converted to 1.63 , Yn2 variable is reused */ + Yn2 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *pOut = acc_h; + + /* Read the second input into Xn2, to reuse the value */ + Xn2 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc += b1 * x[n-1] */ + acc = (q63_t) Xn * b1; + + /* acc = b0 * x[n] */ + acc += (q63_t) Xn2 * b0; + + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn1 * b2; + + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn2, a1); + + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn1, a2); + + /* The result is converted to 1.63, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Read the third input into Xn1, to reuse the value */ + Xn1 = *pIn++; + + /* The result is converted to 1.31 */ + /* Store the output in the destination buffer. */ + *(pOut + 1U) = acc_h; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc = b0 * x[n] */ + acc = (q63_t) Xn1 * b0; + + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn2 * b1; + + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn * b2; + + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn1, a1); + + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn2, a2); + + /* The result is converted to 1.63, Yn2 variable is reused */ + Yn2 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *(pOut + 2U) = acc_h; + + /* Read the fourth input into Xn, to reuse the value */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + acc = (q63_t) Xn * b0; + + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn1 * b1; + + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn2 * b2; + + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn2, a1); + + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn1, a2); + + /* The result is converted to 1.63, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *(pOut + 3U) = acc_h; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + + /* update output pointer */ + pOut += 4U; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x3U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc = b0 * x[n] */ + acc = (q63_t) Xn * b0; + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn1 * b1; + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn2 * b2; + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn1, a1); + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn2, a2); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + + /* The result is converted to 1.63, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *pOut++ = acc_h; + /* Yn1 = acc << shift; */ + + /* Store the output in the destination buffer in 1.31 format. */ +/* *pOut++ = (q31_t) (acc >> (32 - shift)); */ + + /* decrement loop counter */ + sample--; + } + + /* The first stage output is given as input to the second stage. */ + pIn = pDst; + + /* Reset to destination buffer working pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = (q63_t) Xn1; + *pState++ = (q63_t) Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BiquadCascadeDF1_32x64 group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f16.c new file mode 100644 index 00000000..c1ac1401 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f16.c @@ -0,0 +1,491 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_f16.c + * Description: Processing function for the floating-point Biquad cascade DirectFormI(DF1) filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters + */ + + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the floating-point Biquad cascade filter. + @param[in] S points to an instance of the floating-point Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_biquad_cascade_df1_f16( + const arm_biquad_casd_df1_inst_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + float16_t *pIn = (float16_t *)pSrc; /* source pointer */ + float16_t *pOut = pDst; /* destination pointer */ + float16_t *pState = S->pState; /* pState pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float16_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + float16_t X0, X1, X2, X3; /* temporary input */ + float16_t X4, X5, X6, X7; /* temporary input */ + _Float16 lastX, lastY; /* X,Y history for tail handling */ + f16x8_t coeffs; + f16x8_t accVec; /* accumultor vector */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do + { + /* + * Reading the pState values + */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + sample = blockSize >> 3U; + + /* + * First part of the processing with loop unrolling. Compute 8 outputs at a time. + */ + while (sample > 0U) + { + X0 = *pIn++; + X1 = *pIn++; + X2 = *pIn++; + X3 = *pIn++; + X4 = *pIn++; + X5 = *pIn++; + X6 = *pIn++; + X7 = *pIn++; + + coeffs = vld1q(pCoeffs); + accVec = vmulq(coeffs, X7); + + coeffs = vld1q(&pCoeffs[8]); + accVec = vfmaq(accVec, coeffs, X6); + + coeffs = vld1q(&pCoeffs[16]); + accVec = vfmaq(accVec, coeffs, X5); + + coeffs = vld1q(&pCoeffs[24]); + accVec = vfmaq(accVec, coeffs, X4); + + coeffs = vld1q(&pCoeffs[32]); + accVec = vfmaq(accVec, coeffs, X3); + + coeffs = vld1q(&pCoeffs[40]); + accVec = vfmaq(accVec, coeffs, X2); + + coeffs = vld1q(&pCoeffs[48]); + accVec = vfmaq(accVec, coeffs, X1); + + coeffs = vld1q(&pCoeffs[56]); + accVec = vfmaq(accVec, coeffs, X0); + + coeffs = vld1q(&pCoeffs[64]); + accVec = vfmaq(accVec, coeffs, Xn1); + + coeffs = vld1q(&pCoeffs[72]); + accVec = vfmaq(accVec, coeffs, Xn2); + + coeffs = vld1q(&pCoeffs[80]); + accVec = vfmaq(accVec, coeffs, Yn1); + + coeffs = vld1q(&pCoeffs[88]); + accVec = vfmaq(accVec, coeffs, Yn2); + /* + * Store the result in the accumulator in the destination buffer. + */ + vst1q(pOut, accVec); + pOut += 8; + + /* + * update recurrence + */ + Xn1 = X7; + Xn2 = X6; + Yn1 = vgetq_lane(accVec, 7); + Yn2 = vgetq_lane(accVec, 6); + /* + * decrement the loop counter + */ + sample--; + } + + /* + * If the blockSize is not a multiple of 8, + * compute any remaining output samples here. + */ + sample = blockSize & 0x7U; + if (sample) + { + /* save previous X, Y for modulo 1 length case */ + lastX = X7; + lastY = Yn1; + + X0 = *pIn++; + X1 = *pIn++; + X2 = *pIn++; + X3 = *pIn++; + X4 = *pIn++; + X5 = *pIn++; + X6 = *pIn++; + X7 = *pIn++; + + coeffs = vld1q(pCoeffs); + accVec = vmulq(coeffs, X7); + + coeffs = vld1q(&pCoeffs[8]); + accVec = vfmaq(accVec, coeffs, X6); + + coeffs = vld1q(&pCoeffs[16]); + accVec = vfmaq(accVec, coeffs, X5); + + coeffs = vld1q(&pCoeffs[24]); + accVec = vfmaq(accVec, coeffs, X4); + + coeffs = vld1q(&pCoeffs[32]); + accVec = vfmaq(accVec, coeffs, X3); + + coeffs = vld1q(&pCoeffs[40]); + accVec = vfmaq(accVec, coeffs, X2); + + coeffs = vld1q(&pCoeffs[48]); + accVec = vfmaq(accVec, coeffs, X1); + + coeffs = vld1q(&pCoeffs[56]); + accVec = vfmaq(accVec, coeffs, X0); + + coeffs = vld1q(&pCoeffs[64]); + accVec = vfmaq(accVec, coeffs, Xn1); + + coeffs = vld1q(&pCoeffs[72]); + accVec = vfmaq(accVec, coeffs, Xn2); + + coeffs = vld1q(&pCoeffs[80]); + accVec = vfmaq(accVec, coeffs, Yn1); + + coeffs = vld1q(&pCoeffs[88]); + accVec = vfmaq(accVec, coeffs, Yn2); + + switch(sample) + { + case 1: + *pOut++ = vgetq_lane(accVec, 0); + Xn1 = X0; + Xn2 = lastX; + Yn1 = vgetq_lane(accVec, 0); + Yn2 = lastY; + break; + case 2: + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + Xn1 = X1; + Xn2 = X0; + Yn1 = vgetq_lane(accVec, 1); + Yn2 = vgetq_lane(accVec, 0); + break; + case 3: + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + *pOut++ = vgetq_lane(accVec, 2); + Xn1 = X2; + Xn2 = X1; + Yn1 = vgetq_lane(accVec, 2); + Yn2 = vgetq_lane(accVec, 1); + break; + + case 4: + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + *pOut++ = vgetq_lane(accVec, 2); + *pOut++ = vgetq_lane(accVec, 3); + Xn1 = X3; + Xn2 = X2; + Yn1 = vgetq_lane(accVec, 3); + Yn2 = vgetq_lane(accVec, 2); + break; + + case 5: + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + *pOut++ = vgetq_lane(accVec, 2); + *pOut++ = vgetq_lane(accVec, 3); + *pOut++ = vgetq_lane(accVec, 4); + Xn1 = X4; + Xn2 = X3; + Yn1 = vgetq_lane(accVec, 4); + Yn2 = vgetq_lane(accVec, 3); + break; + + case 6: + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + *pOut++ = vgetq_lane(accVec, 2); + *pOut++ = vgetq_lane(accVec, 3); + *pOut++ = vgetq_lane(accVec, 4); + *pOut++ = vgetq_lane(accVec, 5); + Xn1 = X5; + Xn2 = X4; + Yn1 = vgetq_lane(accVec, 5); + Yn2 = vgetq_lane(accVec, 4); + break; + + case 7: + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + *pOut++ = vgetq_lane(accVec, 2); + *pOut++ = vgetq_lane(accVec, 3); + *pOut++ = vgetq_lane(accVec, 4); + *pOut++ = vgetq_lane(accVec, 5); + *pOut++ = vgetq_lane(accVec, 6); + Xn1 = X6; + Xn2 = X5; + Yn1 = vgetq_lane(accVec, 6); + Yn2 = vgetq_lane(accVec, 5); + break; + } + } + /* + * Store the updated state variables back into the pState array + */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + pCoeffs += sizeof(arm_biquad_mod_coef_f16) / sizeof(float16_t); + /* + * The first stage goes from the input buffer to the output buffer. + * Subsequent numStages occur in-place in the output buffer + */ + pIn = pDst; + /* + * Reset the output pointer + */ + pOut = pDst; + /* + * decrement the loop counter + */ + stage--; + } + while (stage > 0U); +} + +#else +void arm_biquad_cascade_df1_f16( + const arm_biquad_casd_df1_inst_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + const float16_t *pIn = pSrc; /* Source pointer */ + float16_t *pOut = pDst; /* Destination pointer */ + float16_t *pState = S->pState; /* pState pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + _Float16 acc; /* Accumulator */ + _Float16 b0, b1, b2, a1, a2; /* Filter coefficients */ + _Float16 Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + _Float16 Xn; /* Temporary input */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the first input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the second input */ + Xn2 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1); + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the third input */ + Xn1 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the forth input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1); + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x3U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = acc; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent numStages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset output pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} + +/** + @} end of BiquadCascadeDF1 group + */ +#endif /* #if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#endif /*#if defined(ARM_FLOAT16_SUPPORTED)*/ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c new file mode 100644 index 00000000..77d862bf --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c @@ -0,0 +1,684 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_f32.c + * Description: Processing function for the floating-point Biquad cascade DirectFormI(DF1) filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup BiquadCascadeDF1 Biquad Cascade IIR Filters Using Direct Form I Structure + + This set of functions implements arbitrary order recursive (IIR) filters. + The filters are implemented as a cascade of second order Biquad sections. + The functions support Q15, Q31 and floating-point data types. + Fast version of Q15 and Q31 also available. + + The functions operate on blocks of input and output data and each call to the function + processes blockSize samples through the filter. + pSrc points to the array of input data and + pDst points to the array of output data. + Both arrays contain blockSize values. + + @par Algorithm + Each Biquad stage implements a second order filter using the difference equation: +
+      y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+  
+ A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage. + \image html Biquad.gif "Single Biquad filter stage" + Coefficients b0, b1 and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients. + Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. + Pay careful attention to the sign of the feedback coefficients. + Some design tools use the difference equation +
+      y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
+  
+ In this case the feedback coefficients a1 and a2 + must be negated when used with the CMSIS DSP Library. + + @par + Higher order filters are realized as a cascade of second order sections. + numStages refers to the number of second order stages used. + For example, an 8th order filter would be realized with numStages=4 second order stages. + \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages" + A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0). + + @par + The pState points to state variables array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: +
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+  
+ + @par + The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed, the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Init Function + There is also an associated initialization function for each data type. + The initialization function performs following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pCoeffs, pState. Also set all of the values in pState to zero. + + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + The code below statically initializes each of the 3 different data type filter instance structures +
+      arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};
+      arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};
+      arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};
+  
+ where numStages is the number of Biquad stages in the filter; + pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer; + postShift shift to be applied. + + @par Fixed-Point Behavior + Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions. + Following issues must be considered: + - Scaling of coefficients + - Filter gain + - Overflow and saturation + + @par Scaling of coefficients + Filter coefficients are represented as fractional values and + coefficients are restricted to lie in the range [-1 +1). + The fixed-point functions have an additional scaling parameter postShift + which allow the filter coefficients to exceed the range [+1 -1). + At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. + \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator" + This essentially scales the filter coefficients by 2^postShift. + For example, to realize the coefficients +
+     {1.5, -0.8, 1.2, 1.6, -0.9}
+  
+ set the pCoeffs array to: +
+     {0.75, -0.4, 0.6, 0.8, -0.45}
+  
+ and set postShift=1 + + @par Filter gain + The frequency response of a Biquad filter is a function of its coefficients. + It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies. + This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter. + To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed. + + @par Overflow and saturation + For Q15 and Q31 versions, it is described separately as part of the function specific documentation below. + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the floating-point Biquad cascade filter. + @param[in] S points to an instance of the floating-point Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_helium_utils.h" +void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* pState pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + float32_t lastX, lastY; /* X,Y history for tail handling */ + float32_t X0, X1, X2, X3; /* temporary input */ + f32x4_t coeffs; + f32x4_t accVec; /* accumultor vector */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do + { + /* + * Reading the pState values + */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + sample = blockSize >> 2U; + + /* + * First part of the processing with loop unrolling. Compute 4 outputs at a time. + * second loop below computes the remaining 1 to 3 samples. + */ + while (sample > 0U) + { + X0 = *pIn++; + X1 = *pIn++; + X2 = *pIn++; + X3 = *pIn++; + + coeffs = vld1q(pCoeffs); + accVec = vmulq(coeffs, X3); + + coeffs = vld1q(&pCoeffs[4]); + accVec = vfmaq(accVec, coeffs, X2); + + coeffs = vld1q(&pCoeffs[8]); + accVec = vfmaq(accVec, coeffs, X1); + + coeffs = vld1q(&pCoeffs[12]); + accVec = vfmaq(accVec, coeffs, X0); + + coeffs = vld1q(&pCoeffs[16]); + accVec = vfmaq(accVec, coeffs, Xn1); + + coeffs = vld1q(&pCoeffs[20]); + accVec = vfmaq(accVec, coeffs, Xn2); + + coeffs = vld1q(&pCoeffs[24]); + accVec = vfmaq(accVec, coeffs, Yn1); + + coeffs = vld1q(&pCoeffs[28]); + accVec = vfmaq(accVec, coeffs, Yn2); + /* + * Store the result in the accumulator in the destination buffer. + */ + vst1q(pOut, accVec); + pOut += 4; + + /* + * update recurrence + */ + Xn1 = X3; + Xn2 = X2; + Yn1 = vgetq_lane(accVec, 3); + Yn2 = vgetq_lane(accVec, 2); + /* + * decrement the loop counter + */ + sample--; + } + + /* + * If the blockSize is not a multiple of 4, + * compute any remaining output samples here. + */ + sample = blockSize & 0x3U; + if (sample) + { + /* save previous X, Y for modulo 1 length case */ + lastX = X3; + lastY = Yn1; + + X0 = *pIn++; + X1 = *pIn++; + X2 = *pIn++; + X3 = *pIn++; + + coeffs = vld1q(pCoeffs); + accVec = vmulq(coeffs, X3); + + coeffs = vld1q(&pCoeffs[4]); + accVec = vfmaq(accVec, coeffs, X2); + + coeffs = vld1q(&pCoeffs[8]); + accVec = vfmaq(accVec, coeffs, X1); + + coeffs = vld1q(&pCoeffs[12]); + accVec = vfmaq(accVec, coeffs, X0); + + coeffs = vld1q(&pCoeffs[16]); + accVec = vfmaq(accVec, coeffs, Xn1); + + coeffs = vld1q(&pCoeffs[20]); + accVec = vfmaq(accVec, coeffs, Xn2); + + coeffs = vld1q(&pCoeffs[24]); + accVec = vfmaq(accVec, coeffs, Yn1); + + coeffs = vld1q(&pCoeffs[28]); + accVec = vfmaq(accVec, coeffs, Yn2); + + if (sample == 1) + { + *pOut++ = vgetq_lane(accVec, 0); + Xn1 = X0; + Xn2 = lastX; + Yn1 = vgetq_lane(accVec, 0); + Yn2 = lastY; + } + else if (sample == 2) + { + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + Xn1 = X1; + Xn2 = X0; + Yn1 = vgetq_lane(accVec, 1); + Yn2 = vgetq_lane(accVec, 0); + } + else + { + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + *pOut++ = vgetq_lane(accVec, 2); + Xn1 = X2; + Xn2 = X1; + Yn1 = vgetq_lane(accVec, 2); + Yn2 = vgetq_lane(accVec, 1); + } + } + /* + * Store the updated state variables back into the pState array + */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + pCoeffs += sizeof(arm_biquad_mod_coef_f32) / sizeof(float32_t); + /* + * The first stage goes from the input buffer to the output buffer. + * Subsequent numStages occur in-place in the output buffer + */ + pIn = pDst; + /* + * Reset the output pointer + */ + pOut = pDst; + /* + * decrement the loop counter + */ + stage--; + } + while (stage > 0U); +} +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + + const float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* pState pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t acc; /* Simulates the accumulator */ + + uint32_t sample, stage = S->numStages; /* loop counters */ + + float32x4_t Xn; + float32x2_t Yn; + float32x2_t a; + float32x4_t b; + + float32x4_t x,tmp; + float32x2_t t; + float32x2x2_t y; + + float32_t Xns; + + while (stage > 0U) + { + /* Reading the coefficients */ + Xn = vdupq_n_f32(0.0f); + + Xn = vsetq_lane_f32(pState[0],Xn,2); + Xn = vsetq_lane_f32(pState[1],Xn,3); + Yn = vset_lane_f32(pState[2],Yn,0); + Yn = vset_lane_f32(pState[3],Yn,1); + + b = vld1q_f32(pCoeffs); + b = vrev64q_f32(b); + b = vcombine_f32(vget_high_f32(b), vget_low_f32(b)); + + a = vld1_f32(pCoeffs + 3); + a = vrev64_f32(a); + b = vsetq_lane_f32(0.0f,b,0); + pCoeffs += 5; + + /* Reading the pState values */ + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* The variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the first 4 inputs */ + x = vld1q_f32(pIn); + + pIn += 4; + + tmp = vextq_f32(Xn, x, 1); + t = vmul_f32(vget_high_f32(b), vget_high_f32(tmp)); + t = vmla_f32(t, vget_low_f32(b), vget_low_f32(tmp)); + t = vmla_f32(t, a, Yn); + t = vpadd_f32(t, t); + Yn = vext_f32(Yn, t, 1); + + tmp = vextq_f32(Xn, x, 2); + t = vmul_f32(vget_high_f32(b), vget_high_f32(tmp)); + t = vmla_f32(t, vget_low_f32(b), vget_low_f32(tmp)); + t = vmla_f32(t, a, Yn); + t = vpadd_f32(t, t); + Yn = vext_f32(Yn, t, 1); + + y.val[0] = Yn; + + tmp = vextq_f32(Xn, x, 3); + t = vmul_f32(vget_high_f32(b), vget_high_f32(tmp)); + t = vmla_f32(t, vget_low_f32(b), vget_low_f32(tmp)); + t = vmla_f32(t, a, Yn); + t = vpadd_f32(t, t); + Yn = vext_f32(Yn, t, 1); + + Xn = x; + t = vmul_f32(vget_high_f32(b), vget_high_f32(Xn)); + t = vmla_f32(t, vget_low_f32(b), vget_low_f32(Xn)); + t = vmla_f32(t, a, Yn); + t = vpadd_f32(t, t); + Yn = vext_f32(Yn, t, 1); + + y.val[1] = Yn; + + tmp = vcombine_f32(y.val[0], y.val[1]); + + /* Store the 4 outputs and increment the pointer */ + vst1q_f32(pOut, tmp); + pOut += 4; + + /* Decrement the loop counter */ + sample--; + } + + + /* If the block size is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + sample = blockSize & 0x3U; + + while (sample > 0U) + { + /* Read the input */ + Xns = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = (vgetq_lane_f32(b, 1) * vgetq_lane_f32(Xn, 2)) + + (vgetq_lane_f32(b, 2) * vgetq_lane_f32(Xn, 3)) + + (vgetq_lane_f32(b, 3) * Xns) + + (vget_lane_f32(a, 0) * vget_lane_f32(Yn, 0)) + + (vget_lane_f32(a, 1) * vget_lane_f32(Yn, 1)); + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn = vsetq_lane_f32(vgetq_lane_f32(Xn, 3),Xn,2); + Xn = vsetq_lane_f32(Xns,Xn,3); + Yn = vset_lane_f32(vget_lane_f32(Yn, 1),Yn,0); + Yn = vset_lane_f32(acc,Yn,1); + + /* Decrement the loop counter */ + sample--; + + } + + vst1q_f32(pState,vcombine_f32((vget_high_f32(Xn)),(Yn))); + pState += 4; + /* Store the updated state variables back into the pState array */ + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent numStages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset the output pointer */ + pOut = pDst; + + /* Decrement the loop counter */ + stage--; + } +} + +#else +void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Source pointer */ + float32_t *pOut = pDst; /* Destination pointer */ + float32_t *pState = S->pState; /* pState pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t acc; /* Accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + float32_t Xn; /* Temporary input */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the first input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the second input */ + Xn2 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1); + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the third input */ + Xn1 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the forth input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1); + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x3U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = acc; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent numStages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset output pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} + +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c new file mode 100644 index 00000000..f2dd334d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c @@ -0,0 +1,250 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_fast_q15.c + * Description: Fast processing function for the Q15 Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the Q15 Biquad cascade filter (fast variant). + @param[in] S points to an instance of the Q15 Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process per call + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). + The 2.30 accumulator is then shifted by postShift bits and the result truncated to 1.15 format by discarding the low 16 bits. + @remark + Refer to \ref arm_biquad_cascade_df1_q15() for a slower implementation of this function + which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure. + Use the function \ref arm_biquad_cascade_df1_init_q15() to initialize the filter structure. + */ + +void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + const q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t acc; /* Accumulator */ + q31_t in; /* Temporary variable to hold input value */ + q31_t out; /* Temporary variable to hold output value */ + q31_t b0; /* Temporary variable to hold bo value */ + q31_t b1, a1; /* Filter coefficients */ + q31_t state_in, state_out; /* Filter state variables */ + int32_t shift = (int32_t) (15 - S->postShift); /* Post shift */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Read the b0 and 0 coefficients using SIMD */ + b0 = read_q15x2_ia (&pCoeffs); + + /* Read the b1 and b2 coefficients using SIMD */ + b1 = read_q15x2_ia (&pCoeffs); + + /* Read the a1 and a2 coefficients using SIMD */ + a1 = read_q15x2_ia (&pCoeffs); + + /* Read the input state values from the state buffer: x[n-1], x[n-2] */ + state_in = read_q15x2_ia (&pState); + + /* Read the output state values from the state buffer: y[n-1], y[n-2] */ + state_out = read_q15x2_da (&pState); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 2 output values simultaneously. */ + /* Variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 2 outputs at a time */ + sample = blockSize >> 1U; + + while (sample > 0U) + { + + /* Read the input */ + in = read_q15x2_ia (&pIn); + + /* out = b0 * x[n] + 0 * 0 */ + out = __SMUAD(b0, in); + /* acc = b1 * x[n-1] + acc += b2 * x[n-2] + out */ + acc = __SMLAD(b1, state_in, out); + /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */ + acc = __SMLAD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 and then saturation is applied */ + out = __SSAT((acc >> shift), 16); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ + +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, (in >> 16), 16); + state_out = __PKHBT(state_out >> 16, (out), 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* out = b0 * x[n] + 0 * 0 */ + out = __SMUADX(b0, in); + /* acc0 = b1 * x[n-1] , acc0 += b2 * x[n-2] + out */ + acc = __SMLAD(b1, state_in, out); + /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */ + acc = __SMLAD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 and then saturation is applied */ + out = __SSAT((acc >> shift), 16); + + /* Store the output in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(state_out, out, 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(out, state_out >> 16, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in >> 16, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, in, 16); + state_out = __PKHBT(state_out >> 16, out, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = (blockSize & 0x1U); + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + in = *pIn++; + + /* out = b0 * x[n] + 0 * 0 */ +#ifndef ARM_MATH_BIG_ENDIAN + out = __SMUAD(b0, in); +#else + out = __SMUADX(b0, in); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* acc = b1 * x[n-1], acc += b2 * x[n-2] + out */ + acc = __SMLAD(b1, state_in, out); + /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */ + acc = __SMLAD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 and then saturation is applied */ + out = __SSAT((acc >> shift), 16); + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t) out; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, in, 16); + state_out = __PKHBT(state_out >> 16, out, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* decrement loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent (numStages - 1) occur in-place in the output buffer */ + pIn = pDst; + + /* Reset the output pointer */ + pOut = pDst; + + /* Store the updated state variables back into the state array */ + write_q15x2_ia(&pState, state_in); + write_q15x2_ia(&pState, state_out); + + /* Decrement loop counter */ + stage--; + + } while (stage > 0U); +} + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c new file mode 100644 index 00000000..cefa592a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c @@ -0,0 +1,296 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_fast_q31.c + * Description: Processing function for the Q31 Fast Biquad cascade DirectFormI(DF1) filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the Q31 Biquad cascade filter (fast variant). + @param[in] S points to an instance of the Q31 Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process per call + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are added to a 2.30 accumulator. + Finally, the accumulator is saturated and converted to a 1.31 result. + The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function + arm_biquad_cascade_df1_init_q31() to initialize filter structure. + @remark + Refer to \ref arm_biquad_cascade_df1_q31() for a slower implementation of this function + which uses 64-bit accumulation to provide higher precision. Both the slow and the fast versions use the same instance structure. + Use the function \ref arm_biquad_cascade_df1_init_q31() to initialize the filter structure. + */ + +void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* Source pointer */ + q31_t *pOut = pDst; /* Destination pointer */ + q31_t *pState = S->pState; /* pState pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t acc = 0; /* Accumulator */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + q31_t Xn; /* Temporary input */ + int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variables acc ... acc3 hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b1 * Xn1) >> 32);*/ + mult_32x32_keep32_R(acc, b1, Xn1); + /* acc += b1 * x[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b0 * (Xn))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b0, Xn); + /* acc += b[2] * x[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn2); + /* acc += a1 * y[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn1); + /* acc += a2 * y[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn2); + + /* The result is converted to 1.31 , Yn2 variable is reused */ + Yn2 = acc << shift; + + /* Read the second input */ + Xn2 = *(pIn + 1U); + + /* Store the output in the destination buffer. */ + *pOut = Yn2; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);*/ + mult_32x32_keep32_R(acc, b0, Xn2); + /* acc += b1 * x[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b1, Xn); + /* acc += b[2] * x[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn1); + /* acc += a1 * y[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn2); + /* acc += a2 * y[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn1); + + /* The result is converted to 1.31, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Read the third input */ + Xn1 = *(pIn + 2U); + + /* Store the output in the destination buffer. */ + *(pOut + 1U) = Yn1; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);*/ + mult_32x32_keep32_R(acc, b0, Xn1); + /* acc += b1 * x[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b1, Xn2); + /* acc += b[2] * x[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn); + /* acc += a1 * y[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn1); + /* acc += a2 * y[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn2); + + /* The result is converted to 1.31, Yn2 variable is reused */ + Yn2 = acc << shift; + + /* Read the forth input */ + Xn = *(pIn + 3U); + + /* Store the output in the destination buffer. */ + *(pOut + 2U) = Yn2; + pIn += 4U; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);*/ + mult_32x32_keep32_R(acc, b0, Xn); + /* acc += b1 * x[n-1] */ + /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b1, Xn1); + /* acc += b[2] * x[n-2] */ + /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn2); + /* acc += a1 * y[n-1] */ + /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn2); + /* acc += a2 * y[n-2] */ + /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn1); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + Xn2 = Xn1; + + /* The result is converted to 1.31, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Xn1 = Xn */ + Xn1 = Xn; + + /* Store the output in the destination buffer. */ + *(pOut + 3U) = Yn1; + pOut += 4U; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = (blockSize & 0x3U); + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);*/ + mult_32x32_keep32_R(acc, b0, Xn); + /* acc += b1 * x[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b1, Xn1); + /* acc += b[2] * x[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn2); + /* acc += a1 * y[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn1); + /* acc += a2 * y[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn2); + + /* The result is converted to 1.31 */ + acc = acc << shift; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = acc; + + /* Store the output in the destination buffer. */ + *pOut++ = acc; + + /* decrement loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f16.c new file mode 100644 index 00000000..d18dd3ea --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f16.c @@ -0,0 +1,166 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_init_f16.c + * Description: Floating-point Biquad cascade DirectFormI(DF1) filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Initialization function for the floating-point Biquad cascade filter. + @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: +
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+  
+ + @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: +
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+  
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par For MVE code, an additional buffer of modified coefficients is required. + Its size is numStages and each element of this buffer has type arm_biquad_mod_coef_f16. + So, its total size is 96*numStages float16_t elements. + + The initialization function which must be used is arm_biquad_cascade_df1_mve_init_f16. + */ + + +void arm_biquad_cascade_df1_init_f16( + arm_biquad_casd_df1_inst_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float16_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +/* + +The computation of the coefficients is done in float32 otherwise the +resulting filter is too different from the expected one. + +*/ +static void generateCoefsFastBiquadF16(float16_t b0, float16_t b1, float16_t b2, float16_t a1, float16_t a2, + arm_biquad_mod_coef_f16 * newCoef) +{ + float32_t coeffs[8][12] = { + {0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, (float32_t)a1, (float32_t)a2}, + {0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, (float32_t)a2, 0.0f}, + {0.0f, 0.0f, 0.0f, 0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f}, + {0.0f, 0.0f, 0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f}, + {0.0f, 0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f}, + {0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f}, + {0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f}, + {(float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f} + }; + + for (int i = 0; i < 12; i++) + { + coeffs[1][i] += ((float32_t)a1 * coeffs[0][i]); + coeffs[2][i] += ((float32_t)a1 * coeffs[1][i]) + ((float32_t)a2 * coeffs[0][i]); + coeffs[3][i] += ((float32_t)a1 * coeffs[2][i]) + ((float32_t)a2 * coeffs[1][i]); + coeffs[4][i] += ((float32_t)a1 * coeffs[3][i]) + ((float32_t)a2 * coeffs[2][i]); + coeffs[5][i] += ((float32_t)a1 * coeffs[4][i]) + ((float32_t)a2 * coeffs[3][i]); + coeffs[6][i] += ((float32_t)a1 * coeffs[5][i]) + ((float32_t)a2 * coeffs[4][i]); + coeffs[7][i] += ((float32_t)a1 * coeffs[6][i]) + ((float32_t)a2 * coeffs[5][i]); + + /* + * transpose + */ + newCoef->coeffs[i][0] = (float16_t) coeffs[0][i]; + newCoef->coeffs[i][1] = (float16_t) coeffs[1][i]; + newCoef->coeffs[i][2] = (float16_t) coeffs[2][i]; + newCoef->coeffs[i][3] = (float16_t) coeffs[3][i]; + newCoef->coeffs[i][4] = (float16_t) coeffs[4][i]; + newCoef->coeffs[i][5] = (float16_t) coeffs[5][i]; + newCoef->coeffs[i][6] = (float16_t) coeffs[6][i]; + newCoef->coeffs[i][7] = (float16_t) coeffs[7][i]; + + } +} + +void arm_biquad_cascade_df1_mve_init_f16(arm_biquad_casd_df1_inst_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + arm_biquad_mod_coef_f16 * pCoeffsMod, + float16_t * pState) +{ + arm_biquad_cascade_df1_init_f16(S, numStages, (float16_t *)pCoeffsMod, pState); + + /* Generate SIMD friendly modified coefs */ + for (int i = 0; i < numStages; i++) + { + generateCoefsFastBiquadF16(pCoeffs[0], pCoeffs[1], pCoeffs[2], pCoeffs[3], pCoeffs[4], pCoeffsMod); + pCoeffs += 5; + pCoeffsMod++; + } +} + +#endif + +/** + @} end of BiquadCascadeDF1 group + */ +#endif /* #if defined(ARMfloat16_t_SUPPORTED) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c new file mode 100644 index 00000000..1614594b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c @@ -0,0 +1,146 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_init_f32.c + * Description: Floating-point Biquad cascade DirectFormI(DF1) filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Initialization function for the floating-point Biquad cascade filter. + @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: +
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+  
+ + @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: +
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+  
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par For MVE code, an additional buffer of modified coefficients is required. + Its size is numStages and each element of this buffer has type arm_biquad_mod_coef_f32. + So, its total size is 32*numStages float32_t elements. + + The initialization function which must be used is arm_biquad_cascade_df1_mve_init_f32. + */ + + +void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +static void generateCoefsFastBiquadF32(float32_t b0, float32_t b1, float32_t b2, float32_t a1, float32_t a2, + arm_biquad_mod_coef_f32 * newCoef) +{ + float32_t coeffs[4][8] = { + {0, 0, 0, b0, b1, b2, a1, a2}, + {0, 0, b0, b1, b2, 0, a2, 0}, + {0, b0, b1, b2, 0, 0, 0, 0}, + {b0, b1, b2, 0, 0, 0, 0, 0}, + }; + + for (int i = 0; i < 8; i++) + { + coeffs[1][i] += a1 * coeffs[0][i]; + coeffs[2][i] += a1 * coeffs[1][i] + a2 * coeffs[0][i]; + coeffs[3][i] += a1 * coeffs[2][i] + a2 * coeffs[1][i]; + + /* + * transpose + */ + newCoef->coeffs[i][0] = (float32_t) coeffs[0][i]; + newCoef->coeffs[i][1] = (float32_t) coeffs[1][i]; + newCoef->coeffs[i][2] = (float32_t) coeffs[2][i]; + newCoef->coeffs[i][3] = (float32_t) coeffs[3][i]; + } +} + +void arm_biquad_cascade_df1_mve_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + arm_biquad_mod_coef_f32 * pCoeffsMod, + float32_t * pState) +{ + arm_biquad_cascade_df1_init_f32(S, numStages, (float32_t *)pCoeffsMod, pState); + + /* Generate SIMD friendly modified coefs */ + for (int i = 0; i < numStages; i++) + { + generateCoefsFastBiquadF32(pCoeffs[0], pCoeffs[1], pCoeffs[2], pCoeffs[3], pCoeffs[4], pCoeffsMod); + pCoeffs += 5; + pCoeffsMod++; + } +} +#endif + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c new file mode 100644 index 00000000..0fa38255 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c @@ -0,0 +1,96 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_init_q15.c + * Description: Q15 Biquad cascade DirectFormI(DF1) filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Initialization function for the Q15 Biquad cascade filter. + @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @param[in] postShift Shift to be applied to the accumulator result. Varies according to the coefficients format + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: +
+      {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}
+  
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 6*numStages values. + The zero coefficient between b1 and b2 facilities use of 16-bit SIMD instructions on the Cortex-M4. + @par + The state variables are stored in the array pState. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: +
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+  
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + const q15_t * pCoeffs, + q15_t * pState, + int8_t postShift) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign postShift to be applied to the output */ + S->postShift = postShift; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c new file mode 100644 index 00000000..2b3cb628 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c @@ -0,0 +1,95 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_init_q31.c + * Description: Q31 Biquad cascade DirectFormI(DF1) filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Initialization function for the Q31 Biquad cascade filter. + @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: +
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+  
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState points to state variables array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: +
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+  
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q31_t * pState, + int8_t postShift) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign postShift to be applied to the output */ + S->postShift = postShift; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c new file mode 100644 index 00000000..c77a05c4 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c @@ -0,0 +1,618 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_q15.c + * Description: Processing function for the Q15 Biquad cascade DirectFormI(DF1) filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the Q15 Biquad cascade filter. + @param[in] S points to an instance of the Q15 Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the location where the output result is written + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + The accumulator is then shifted by postShift bits to truncate the result to 1.15 format by discarding the low 16 bits. + Finally, the result is saturated to 1.15 format. + @remark + Refer to \ref arm_biquad_cascade_df1_fast_q15() for a faster but less precise implementation of this filter. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + const q15_t *pIn = pSrc; /* input pointer initialization */ + q15_t *pOut = pDst; /* output pointer initialization */ + int shift; + uint32_t sample, stages = S->numStages; /* loop counters */ + int postShift = S->postShift; + q15x8_t bCoeffs0, bCoeffs1, bCoeffs2, bCoeffs3; /* Coefficients vector */ + q15_t *pState = S->pState; /* pState pointer initialization */ + q15x8_t inVec0; + int64_t acc; + const q15_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q31_t out, out1; + + shift = (15 - postShift) - 32; + + do { + q15_t a2 = pCoeffs[5]; + q15_t a1 = pCoeffs[4]; + + bCoeffs0 = vdupq_n_s16(0); + bCoeffs0[0] = pCoeffs[3]; // b2 + bCoeffs0[1] = pCoeffs[2]; // b1 + bCoeffs0[2] = pCoeffs[0]; // b0 + + uint32_t zero = 0; + bCoeffs1 = bCoeffs0; + bCoeffs1 = vshlcq_s16(bCoeffs1, &zero, 16); + + bCoeffs2 = bCoeffs1; + bCoeffs2 = vshlcq_s16(bCoeffs2, &zero, 16); + + bCoeffs3 = bCoeffs2; + bCoeffs3 = vshlcq_s16(bCoeffs3, &zero, 16); + + bCoeffs0[6] = a2; + bCoeffs0[7] = a1; + bCoeffs1[7] = a2; + bCoeffs1[6] = a1; + + bCoeffs2 = + vsetq_lane_s32(vgetq_lane_s32((q31x4_t) bCoeffs0, 3), (q31x4_t) bCoeffs2, 3); + bCoeffs3 = + vsetq_lane_s32(vgetq_lane_s32((q31x4_t) bCoeffs1, 3), (q31x4_t) bCoeffs3, 3); + + + /* 2 first elements are garbage, will be updated with history */ + inVec0 = vld1q(pIn - 2); + pIn += 2; + + inVec0[0] = pState[1]; + inVec0[1] = pState[0]; + inVec0[6] = pState[3]; + inVec0[7] = pState[2]; + + acc = vmlaldavq(bCoeffs0, inVec0); + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + + inVec0[6] = out1; + acc = vmlaldavq(bCoeffs1, inVec0); + acc = sqrshrl_sat48(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + inVec0[7] = out; + *pOut++ = (q15_t) out1; + *pOut++ = (q15_t) out; + + acc = vmlaldavq(bCoeffs2, inVec0); + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + + + inVec0[6] = out1; + acc = vmlaldavq(bCoeffs3, inVec0); + acc = sqrshrl_sat48(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + /* + * main loop + */ + sample = (blockSize - 4) >> 2U; + /* preload (efficient scheduling) */ + inVec0 = vld1q(pIn); + pIn += 4; + + /* + * Compute 4 outputs at a time. + */ + while (sample > 0U) { + + inVec0[6] = out1; + inVec0[7] = out; + + /* store */ + *pOut++ = (q15_t) out1; + *pOut++ = (q15_t) out; + + /* + * in { x0 x1 x2 x3 x4 x5 yn2 yn1 } + * x + * bCoeffs0 { b2 b1 b0 0 0 0 a2 a1 } + * + */ + acc = vmlaldavq(bCoeffs0, inVec0); + /* shift + saturate to 16 bit */ + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + inVec0[6] = out1; + + /* + * in { x0 x1 x2 x3 x4 x5 y0 yn1 } + * x + * bCoeffs1 { 0 b2 b1 b0 0 0 a1 a2 } + */ + acc = vmlaldavq(bCoeffs1, inVec0); + acc = sqrshrl_sat48(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + *pOut++ = (q15_t) out1; + *pOut++ = (q15_t) out; + + + inVec0[7] = out; + /* + * in { x0 x1 x2 x3 x4 x5 y0 yp1 } + * x + * bCoeffs2 { 0 0 b2 b1 b0 0 a2 a1 } + */ + acc = vmlaldavq(bCoeffs2, inVec0); + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + inVec0[6] = out1; + + /* + * in { x0 x1 x2 x3 x4 x5 y0 yp1 } + * x + * bCoeffs2 { 0 0 0 b2 b1 b0 a1 a2 } + */ + acc = vmlaldavq(bCoeffs3, inVec0); + acc = sqrshrl_sat48(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + inVec0 = vld1q(pIn); + pIn += 4; + + /* decrement the loop counter */ + sample--; + } + + *pOut++ = (q15_t) out1; + *pOut++ = (q15_t) out; + + /* + * Tail handling + */ + int32_t loopRemainder = blockSize & 3; + + if (loopRemainder == 3) { + inVec0[6] = out1; + inVec0[7] = out; + + acc = vmlaldavq(bCoeffs0, inVec0); + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + inVec0[6] = out1; + + acc = vmlaldavq(bCoeffs1, inVec0); + acc = sqrshrl_sat48(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + *pOut++ = (q15_t) out1; + *pOut++ = (q15_t) out; + + inVec0[7] = out; + acc = vmlaldavq(bCoeffs2, inVec0); + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + *pOut++ = (q15_t) out1; + + /* Store the updated state variables back into the pState array */ + pState[0] = vgetq_lane_s16(inVec0, 4); + pState[1] = vgetq_lane_s16(inVec0, 3); + pState[3] = out; + pState[2] = out1; + + } else if (loopRemainder == 2) { + inVec0[6] = out1; + inVec0[7] = out; + + acc = vmlaldavq(bCoeffs0, inVec0); + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + inVec0[6] = out1; + + acc = vmlaldavq(bCoeffs1, inVec0); + acc = sqrshrl_sat48(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + *pOut++ = (q15_t) out1; + *pOut++ = (q15_t) out; + + /* Store the updated state variables back into the pState array */ + pState[0] = vgetq_lane_s16(inVec0, 3); + pState[1] = vgetq_lane_s16(inVec0, 2); + pState[3] = out1; + pState[2] = out; + } else if (loopRemainder == 1) { + + inVec0[6] = out1; + inVec0[7] = out; + + acc = vmlaldavq(bCoeffs0, inVec0); + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + *pOut++ = (q15_t) out1; + + /* Store the updated state variables back into the pState array */ + pState[0] = vgetq_lane_s16(inVec0, 2); + pState[1] = vgetq_lane_s16(inVec0, 1); + pState[3] = out; + pState[2] = out1; + + + } else { + /* Store the updated state variables back into the pState array */ + pState[0] = vgetq_lane_s16(inVec0, 1); + pState[1] = vgetq_lane_s16(inVec0, 0); + pState[3] = out1; + pState[2] = out; + } + + pState += 4; + pCoeffs += 6; + + /* + * The first stage goes from the input buffer to the output buffer. + * Subsequent stages occur in-place in the output buffer + */ + pIn = pDst; + /* + * Reset to destination pointer + */ + pOut = pDst; + } + while (--stages); +} +#else +void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + + +#if defined (ARM_MATH_DSP) + + const q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q31_t in; /* Temporary variable to hold input value */ + q31_t out; /* Temporary variable to hold output value */ + q31_t b0; /* Temporary variable to hold bo value */ + q31_t b1, a1; /* Filter coefficients */ + q31_t state_in, state_out; /* Filter state variables */ + q31_t acc_l, acc_h; + q63_t acc; /* Accumulator */ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */ + uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */ + int32_t uShift = (32 - lShift); + + do + { + /* Read the b0 and 0 coefficients using SIMD */ + b0 = read_q15x2_ia ((q15_t **) &pCoeffs); + + /* Read the b1 and b2 coefficients using SIMD */ + b1 = read_q15x2_ia ((q15_t **) &pCoeffs); + + /* Read the a1 and a2 coefficients using SIMD */ + a1 = read_q15x2_ia ((q15_t **) &pCoeffs); + + /* Read the input state values from the state buffer: x[n-1], x[n-2] */ + state_in = read_q15x2_ia (&pState); + + /* Read the output state values from the state buffer: y[n-1], y[n-2] */ + state_out = read_q15x2_da (&pState); + + /* Apply loop unrolling and compute 2 output values simultaneously. */ + /* The variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + sample = blockSize >> 1U; + + /* First part of the processing with loop unrolling. Compute 2 outputs at a time. + ** a second loop below computes the remaining 1 sample. */ + while (sample > 0U) + { + + /* Read the input */ + in = read_q15x2_ia ((q15_t **) &pIn); + + /* out = b0 * x[n] + 0 * 0 */ + out = __SMUAD(b0, in); + + /* acc += b1 * x[n-1] + b2 * x[n-2] + out */ + acc = __SMLALD(b1, state_in, out); + /* acc += a1 * y[n-1] + a2 * y[n-2] */ + acc = __SMLALD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + out = (uint32_t) acc_l >> lShift | acc_h << uShift; + + out = __SSAT(out, 16); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ + +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, (in >> 16), 16); + state_out = __PKHBT(state_out >> 16, (out), 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* out = b0 * x[n] + 0 * 0 */ + out = __SMUADX(b0, in); + /* acc += b1 * x[n-1] + b2 * x[n-2] + out */ + acc = __SMLALD(b1, state_in, out); + /* acc += a1 * y[n-1] + a2 * y[n-2] */ + acc = __SMLALD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + out = (uint32_t) acc_l >> lShift | acc_h << uShift; + + out = __SSAT(out, 16); + + /* Store the output in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(state_out, out, 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(out, state_out >> 16, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in >> 16, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, in, 16); + state_out = __PKHBT(state_out >> 16, out, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement loop counter */ + sample--; + } + + /* If the blockSize is not a multiple of 2, compute any remaining output samples here. + ** No loop unrolling is used. */ + + if ((blockSize & 0x1U) != 0U) + { + /* Read the input */ + in = *pIn++; + + /* out = b0 * x[n] + 0 * 0 */ +#ifndef ARM_MATH_BIG_ENDIAN + out = __SMUAD(b0, in); +#else + out = __SMUADX(b0, in); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* acc = b1 * x[n-1] + b2 * x[n-2] + out */ + acc = __SMLALD(b1, state_in, out); + /* acc += a1 * y[n-1] + a2 * y[n-2] */ + acc = __SMLALD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + out = (uint32_t) acc_l >> lShift | acc_h << uShift; + + out = __SSAT(out, 16); + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t) out; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, in, 16); + state_out = __PKHBT(state_out >> 16, out, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + } + + /* The first stage goes from the input wire to the output wire. */ + /* Subsequent numStages occur in-place in the output wire */ + pIn = pDst; + + /* Reset the output pointer */ + pOut = pDst; + + /* Store the updated state variables back into the state array */ + write_q15x2_ia (&pState, state_in); + write_q15x2_ia (&pState, state_out); + + /* Decrement loop counter */ + stage--; + + } while (stage > 0U); + +#else + + const q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q15_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q15_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */ + q15_t Xn; /* temporary input */ + q63_t acc; /* Accumulator */ + int32_t shift = (15 - (int32_t) S->postShift); /* Post shift */ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + pCoeffs++; // skip the 0 coefficient + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + /* The variables acc holds the output value that is computed: + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + acc = (q31_t) b0 *Xn; + + /* acc += b1 * x[n-1] */ + acc += (q31_t) b1 *Xn1; + /* acc += b[2] * x[n-2] */ + acc += (q31_t) b2 *Xn2; + /* acc += a1 * y[n-1] */ + acc += (q31_t) a1 *Yn1; + /* acc += a2 * y[n-2] */ + acc += (q31_t) a2 *Yn2; + + /* The result is converted to 1.31 */ + acc = __SSAT((acc >> shift), 16); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = (q15_t) acc; + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t) acc; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); + +#endif /* #if defined (ARM_MATH_DSP) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c new file mode 100644 index 00000000..d938025e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c @@ -0,0 +1,510 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_q31.c + * Description: Processing function for the Q31 Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the Q31 Biquad cascade filter. + @param[in] S points to an instance of the Q31 Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25). + After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to + 1.31 format by discarding the low 32 bits. + @remark + Refer to \ref arm_biquad_cascade_df1_fast_q31() for a faster but less precise implementation of this filter. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + int shift; + uint32_t stages = S->numStages; /* loop counters */ + int postShift = S->postShift; + q31x4_t b0Coeffs, b1Coeffs, a0Coeffs, a1Coeffs; /* Coefficients vector */ + q31x4_t stateVec; + q31_t *pState = S->pState; /* pState pointer initialization */ + q31x4_t inVec0; + int64_t acc; + const q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q31_t out, out1; + + + shift = (postShift + 1 + 8); + + do { + /* + * Reading the coefficients + * generates : + * Fwd0 { b2 b1 b0 0 } + * Fwd1 { 0 b2 b1 b0 } + * Bwd0 { 0 0 a2 a1 } + * Bwd0 { 0 0 a1 a2 } + * (can be moved in init) + */ + b0Coeffs = vdupq_n_s32(0); + a0Coeffs = vdupq_n_s32(0); + + b0Coeffs[0] = pCoeffs[2]; // b2 + b0Coeffs[1] = pCoeffs[1]; // b1 + b0Coeffs[2] = pCoeffs[0]; // b0 + + b1Coeffs = b0Coeffs; + uint32_t zero = 0; + b1Coeffs = vshlcq_s32(b1Coeffs, &zero, 32); + + a0Coeffs[2] = pCoeffs[4]; + a0Coeffs[3] = pCoeffs[3]; + a1Coeffs = vrev64q_s32(a0Coeffs); + + + /* + * prologue consumes history samples + */ + + /* 2 first elements are garbage, will be updated with history */ + inVec0 = vld1q(pIn - 2); + + inVec0[0] = pState[1]; + inVec0[1] = pState[0]; + + stateVec[2] = pState[3]; + stateVec[3] = pState[2]; + + acc = vrmlaldavhq(b0Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a0Coeffs, stateVec); + acc = lsll(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + stateVec[2] = out; + acc = vrmlaldavhq(b1Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a1Coeffs, stateVec); + + acc = lsll(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + + + inVec0 = vld1q(pIn); + pIn += 2; + + /* + * main loop + */ + uint32_t sample = (blockSize - 2) >> 2U; + /* + * First part of the processing with loop unrolling. + * Compute 4 outputs at a time. + */ + while (sample > 0U) { + + stateVec[3] = out1; + + *pOut++ = out; + *pOut++ = out1; + + /* + * in { x0 x1 x2 x3 } + * x + * b0Coeffs { b2 b1 b0 0 } + */ + acc = vrmlaldavhq(b0Coeffs, inVec0); + /* + * out { 0 0 yn2 yn1 } + * x + * a0Coeffs { 0 0 a2 a1 } + */ + acc = vrmlaldavhaq(acc, a0Coeffs, stateVec); + acc = lsll(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + stateVec[2] = out; + + /* + * in { x0 x1 x2 x3 } + * x + * b0Coeffs { 0 b2 b1 b0 } + */ + acc = vrmlaldavhq(b1Coeffs, inVec0); + /* + * out { 0 0 y0 yn1 } + * x + * a0Coeffs { 0 0 a1 a2 } + */ + acc = vrmlaldavhaq(acc, a1Coeffs, stateVec); + acc = lsll(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + + stateVec[3] = out1; + + inVec0 = vld1q(pIn); + pIn += 2; + + /* unrolled part */ + *pOut++ = out; + *pOut++ = out1; + + acc = vrmlaldavhq(b0Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a0Coeffs, stateVec); + acc = lsll(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + stateVec[2] = out; + + acc = vrmlaldavhq(b1Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a1Coeffs, stateVec); + acc = lsll(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + + inVec0 = vld1q(pIn); + pIn += 2; + + sample--; + } + + *pOut++ = out; + *pOut++ = out1; + + /* + * Tail handling + */ + int32_t loopRemainder = blockSize & 3; + if (loopRemainder == 2) { + /* + * Store the updated state variables back into the pState array + */ + pState[0] = inVec0[1]; + pState[1] = inVec0[0]; + pState[3] = out; + pState[2] = out1; + } else if (loopRemainder == 1) { + stateVec[3] = out1; + + acc = vrmlaldavhq(b0Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a0Coeffs, stateVec); + acc = lsll(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + stateVec[2] = out; + + acc = vrmlaldavhq(b1Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a1Coeffs, stateVec); + acc = lsll(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + + stateVec[3] = out1; + + inVec0 = vld1q(pIn); + pIn += 2; + + *pOut++ = out; + *pOut++ = out1; + + acc = vrmlaldavhq(b0Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a0Coeffs, stateVec); + acc = lsll(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + *pOut++ = out; + + /* + * Store the updated state variables back into the pState array + */ + pState[0] = inVec0[2]; + pState[1] = inVec0[1]; + pState[3] = out1; + pState[2] = out; + } else if (loopRemainder == 0) { + stateVec[3] = out1; + + acc = vrmlaldavhq(b0Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a0Coeffs, stateVec); + acc = lsll(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + stateVec[2] = out; + + acc = vrmlaldavhq(b1Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a1Coeffs, stateVec); + acc = lsll(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + + *pOut++ = out; + *pOut++ = out1; + + /* + * Store the updated state variables back into the pState array + */ + pState[0] = inVec0[3]; + pState[1] = inVec0[2]; + pState[3] = out; + pState[2] = out1; + } else { + stateVec[3] = out1; + + acc = vrmlaldavhq(b0Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a0Coeffs, stateVec); + acc = lsll(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + *pOut++ = out; + + /* + * Store the updated state variables back into the pState array + */ + pState[0] = inVec0[2]; + pState[1] = inVec0[1]; + pState[3] = out1; + pState[2] = out; + } + + + pCoeffs += 5; + pState += 4; + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + } + while (--stages); +} +#else +void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* Source pointer */ + q31_t *pOut = pDst; /* Destination pointer */ + q31_t *pState = S->pState; /* pState pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q63_t acc; /* Accumulator */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + q31_t Xn; /* Temporary input */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc_l, acc_h; /* temporary output variables */ +#endif + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the first input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn) + ((q63_t) b1 * Xn1) + ((q63_t) b2 * Xn2) + ((q63_t) a1 * Yn1) + ((q63_t) a2 * Yn2); + + /* The result is converted to 1.31 , Yn2 variable is reused */ + acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */ + acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */ + + /* Apply shift for lower part of acc and upper part of acc */ + Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Read the second input */ + Xn2 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn2) + ((q63_t) b1 * Xn) + ((q63_t) b2 * Xn1) + ((q63_t) a1 * Yn2) + ((q63_t) a2 * Yn1); + + /* The result is converted to 1.31, Yn1 variable is reused */ + acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */ + acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */ + + /* Apply shift for lower part of acc and upper part of acc */ + Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Read the third input */ + Xn1 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn1) + ((q63_t) b1 * Xn2) + ((q63_t) b2 * Xn) + ((q63_t) a1 * Yn1) + ((q63_t) a2 * Yn2); + + /* The result is converted to 1.31, Yn2 variable is reused */ + acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */ + acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */ + + /* Apply shift for lower part of acc and upper part of acc */ + Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Read the forth input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn) + ((q63_t) b1 * Xn1) + ((q63_t) b2 * Xn2) + ((q63_t) a1 * Yn2) + ((q63_t) a2 * Yn1); + + /* The result is converted to 1.31, Yn1 variable is reused */ + acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */ + acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */ + + /* Apply shift for lower part of acc and upper part of acc */ + Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x3U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn) + ((q63_t) b1 * Xn1) + ((q63_t) b2 * Xn2) + ((q63_t) a1 * Yn1) + ((q63_t) a2 * Yn2); + + /* The result is converted to 1.31 */ + acc = acc >> lShift; + + /* Store output in destination buffer. */ + *pOut++ = (q31_t) acc; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = (q31_t) acc; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent numStages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset output pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f16.c new file mode 100644 index 00000000..a7b1c7ab --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f16.c @@ -0,0 +1,494 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df2T_f16.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +#if (defined(ARM_MATH_MVE_FLOAT16) && defined(ARM_MATH_HELIUM_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_biquad_cascade_df2T_f16( + const arm_biquad_cascade_df2T_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + float16_t *pIn = (float16_t *)pSrc; /* source pointer */ + float16_t Xn0, Xn1; + float16_t acc0, acc1; + float16_t *pOut = pDst; /* destination pointer */ + float16_t *pState = S->pState; /* State pointer */ + uint32_t sample, stage = S->numStages; /* loop counters */ + float16_t const *pCurCoeffs = /* coefficient pointer */ + (float16_t const *) S->pCoeffs; + f16x8_t b0Coeffs, a0Coeffs; /* Coefficients vector */ + f16x8_t b1Coeffs, a1Coeffs; /* Modified coef. vector */ + f16x8_t state; /* State vector */ + + do + { + /* + * temporary carry variable for feeding the 128-bit vector shifter + */ + uint32_t tmp = 0; + /* + * Reading the coefficients + * b0Coeffs = {b0, b1, b2, x, x, x, x, x} + * a0Coeffs = { x, a1, a2, x, x, x, x, x} + */ + b0Coeffs = vld1q(pCurCoeffs); pCurCoeffs += 2; + a0Coeffs = vld1q(pCurCoeffs); pCurCoeffs += 3; + /* + * Reading the state values + * state = {d1, d2, 0, 0, x, x, x, x} + */ + state = *(f16x8_t *) pState; + state = vsetq_lane((float16_t)0.0, state, 2); + state = vsetq_lane((float16_t)0.0, state, 3); + + /* b1Coeffs = {0, b0, b1, b2, x, x, x, x} */ + /* b1Coeffs = { x, x, a1, a2, x, x, x, x} */ + b1Coeffs = (f16x8_t)vshlcq_s16((int16x8_t)b0Coeffs, &tmp, 16); + a1Coeffs = (f16x8_t)vshlcq_s16((int16x8_t)a0Coeffs, &tmp, 16); + + sample = blockSize / 2; + + /* unrolled 2 x */ + while (sample > 0U) + { + /* + * Read 2 inputs + */ + Xn0 = *pIn++; + Xn1 = *pIn++; + + /* + * 1st half: + * / acc1 \ / b0 \ / d1 \ / 0 \ + * | d1 | | b1 | | d2 | | a1 | + * | d2 | | b2 | | 0 | | a2 | + * | x | = | x | * Xn1 + | x | + | x | x acc1 + * ... ... ... ... + * \ x / \ x / \ x / \ x / + */ + + state = vfmaq(state, b0Coeffs, Xn0); + acc0 = vgetq_lane(state, 0); + state = vfmaq(state, a0Coeffs, acc0); + state = vsetq_lane((float16_t)0.0, state, 3); + + /* + * 2nd half: + * same as 1st half, but all vector elements shifted down. + * / x \ / x \ / x \ / x \ + * | acc1 | | b0 | | d1 | | 0 | + * | d1 | | b1 | | d2 | | a1 | + * | d2 | | b2 | | 0 | | a2 | + * | x | = | x | * Xn1 + | x | + | x | x acc1 + * ... ... ... ... + * \ x / \ x / \ x / \ x / + */ + + state = vfmaq(state, b1Coeffs, Xn1); + acc1 = vgetq_lane(state, 1); + state = vfmaq(state, a1Coeffs, acc1); + + /* move d1, d2 up + clearing */ + /* expect dual move or long move */ + state = vsetq_lane(vgetq_lane(state, 2), state, 0); + state = vsetq_lane(vgetq_lane(state, 3), state, 1); + state = vsetq_lane((float16_t)0.0, state, 2); + /* + * Store the results in the destination buffer. + */ + *pOut++ = acc0; + *pOut++ = acc1; + /* + * decrement the loop counter + */ + sample--; + } + + /* compiler does not come back when enabled */ + /* + * tail handling + */ + if (blockSize & 1) + { + Xn0 = *pIn++; + state = vfmaq_n_f16(state, b0Coeffs, Xn0); + acc0 = vgetq_lane(state, 0); + + state = vfmaq_n_f16(state, a0Coeffs, acc0); + *pOut++ = acc0; + *pState++ = vgetq_lane(state, 1); + *pState++ = vgetq_lane(state, 2); + } + else + { + *pState++ = vgetq_lane(state, 0); + *pState++ = vgetq_lane(state, 1); + } + /* + * The current stage input is given as the output to the next stage + */ + pIn = pDst; + /* + * Reset the output working pointer + */ + pOut = pDst; + /* + * decrement the loop counter + */ + stage--; + } + while (stage > 0U); +} +#else + +void arm_biquad_cascade_df2T_f16( + const arm_biquad_cascade_df2T_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + const float16_t *pIn = pSrc; /* Source pointer */ + float16_t *pOut = pDst; /* Destination pointer */ + float16_t *pState = S->pState; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + _Float16 acc1; /* Accumulator */ + _Float16 b0, b1, b2, a1, a2; /* Filter coefficients */ + _Float16 Xn1; /* Temporary input */ + _Float16 d1, d2; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + pCoeffs += 5U; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 16 outputs at a time */ + sample = blockSize >> 4U; + + while (sample > 0U) { + + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 2 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 3 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 4 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 5 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 6 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 7 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 8 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 9 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 10 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 11 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 12 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 13 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 14 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 15 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 16 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0xFU; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1; + pState[1] = d2; + + pState += 2U; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} +#endif /* #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of BiquadCascadeDF2T group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c new file mode 100644 index 00000000..922a3965 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c @@ -0,0 +1,652 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df2T_f32.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ +#if (defined(ARM_MATH_MVEF) && defined(ARM_MATH_HELIUM_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_helium_utils.h" + +void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* source pointer */ + float32_t Xn0, Xn1; + float32_t acc0, acc1; + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + uint32_t sample, stage = S->numStages; /* loop counters */ + float32_t const *pCurCoeffs = /* coefficient pointer */ + (float32_t const *) S->pCoeffs; + f32x4_t b0Coeffs, a0Coeffs; /* Coefficients vector */ + f32x4_t b1Coeffs, a1Coeffs; /* Modified coef. vector */ + f32x4_t state; /* State vector */ + + do + { + /* + * temporary carry variable for feeding the 128-bit vector shifter + */ + uint32_t tmp = 0; + /* + * Reading the coefficients + * b0Coeffs = {b0, b1, b2, x} + * a0Coeffs = { x, a1, a2, x} + */ + b0Coeffs = vld1q(pCurCoeffs); pCurCoeffs+= 2; + a0Coeffs = vld1q(pCurCoeffs); pCurCoeffs+= 3; + /* + * Reading the state values + * state = {d1, d2, 0, 0} + */ + state = *(f32x4_t *) pState; + state = vsetq_lane(0.0f, state, 2); + state = vsetq_lane(0.0f, state, 3); + + /* b1Coeffs = {b0, b1, b2, x} */ + /* b1Coeffs = { x, x, a1, a2} */ + b1Coeffs = (f32x4_t)vshlcq_s32((int32x4_t)b0Coeffs, &tmp, 32); + a1Coeffs = (f32x4_t)vshlcq_s32((int32x4_t)a0Coeffs, &tmp, 32); + + sample = blockSize / 2; + + /* unrolled 2 x */ + while (sample > 0U) + { + /* + * Read 2 inputs + */ + Xn0 = *pIn++; + Xn1 = *pIn++; + + /* + * 1st half: + * / acc0 \ / b0 \ / d1 \ / 0 \ + * | d1 | = | b1 | * Xn0 + | d2 | + | a1 | x acc0 + * | d2 | | b2 | | 0 | | a2 | + * \ x / \ x / \ x / \ x / + */ + + state = vfmaq(state, b0Coeffs, Xn0); + acc0 = vgetq_lane(state, 0); + state = vfmaq(state, a0Coeffs, acc0); + state = vsetq_lane(0.0f, state, 3); + + /* + * 2nd half: + * same as 1st half, but all vector elements shifted down. + * / x \ / x \ / x \ / x \ + * | acc1 | = | b0 | * Xn1 + | d1 | + | 0 | x acc1 + * | d1 | | b1 | | d2 | | a1 | + * \ d2 / \ b2 / \ 0 / \ a2 / + */ + + state = vfmaq(state, b1Coeffs, Xn1); + acc1 = vgetq_lane(state, 1); + state = vfmaq(state, a1Coeffs, acc1); + + /* move d1, d2 up + clearing */ + /* expect dual move or long move */ + state = vsetq_lane(vgetq_lane(state, 2), state, 0); + state = vsetq_lane(vgetq_lane(state, 3), state, 1); + state = vsetq_lane(0.0f, state, 2); + /* + * Store the results in the destination buffer. + */ + *pOut++ = acc0; + *pOut++ = acc1; + /* + * decrement the loop counter + */ + sample--; + } + + /* + * tail handling + */ + if (blockSize & 1) + { + Xn0 = *pIn++; + state = vfmaq(state, b0Coeffs, Xn0); + acc0 = vgetq_lane(state, 0); + + state = vfmaq(state, a0Coeffs, acc0); + *pOut++ = acc0; + *pState++ = vgetq_lane(state, 1); + *pState++ = vgetq_lane(state, 2); + } + else + { + *pState++ = vgetq_lane(state, 0); + *pState++ = vgetq_lane(state, 1); + } + /* + * The current stage output is given as the input to the next stage + */ + pIn = pDst; + /* + * Reset the output working pointer + */ + pOut = pDst; + /* + * decrement the loop counter + */ + stage--; + } + while (stage > 0U); +} +#else +#if defined(ARM_MATH_NEON) + +void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t acc1; /* accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1; /* temporary input */ + float32_t d1, d2; /* state variables */ + uint32_t sample, stageCnt,stage = S->numStages; /* loop counters */ + + + float32x4_t XnV, YnV; + float32x4x2_t dV; + float32x4_t zeroV = vdupq_n_f32(0.0); + float32x4_t t1,t2,t3,t4,b1V,b2V,a1V,a2V,s; + + /* Loop unrolling. Compute 4 outputs at a time */ + stageCnt = stage >> 2; + + while (stageCnt > 0U) + { + /* Reading the coefficients */ + t1 = vld1q_f32(pCoeffs); + pCoeffs += 4; + + t2 = vld1q_f32(pCoeffs); + pCoeffs += 4; + + t3 = vld1q_f32(pCoeffs); + pCoeffs += 4; + + t4 = vld1q_f32(pCoeffs); + pCoeffs += 4; + + b1V = vld1q_f32(pCoeffs); + pCoeffs += 4; + + b2V = vld1q_f32(pCoeffs); + pCoeffs += 4; + + a1V = vld1q_f32(pCoeffs); + pCoeffs += 4; + + a2V = vld1q_f32(pCoeffs); + pCoeffs += 4; + + /* Reading the state values */ + dV = vld2q_f32(pState); + + sample = blockSize; + + while (sample > 0U) { + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + + XnV = vdupq_n_f32(*pIn++); + + s = dV.val[0]; + YnV = s; + + s = vextq_f32(zeroV,dV.val[0],3); + YnV = vmlaq_f32(YnV, t1, s); + + s = vextq_f32(zeroV,dV.val[0],2); + YnV = vmlaq_f32(YnV, t2, s); + + s = vextq_f32(zeroV,dV.val[0],1); + YnV = vmlaq_f32(YnV, t3, s); + + YnV = vmlaq_f32(YnV, t4, XnV); + + s = vextq_f32(XnV,YnV,3); + + dV.val[0] = vmlaq_f32(dV.val[1], s, b1V); + dV.val[0] = vmlaq_f32(dV.val[0], YnV, a1V); + + dV.val[1] = vmulq_f32(s, b2V); + dV.val[1] = vmlaq_f32(dV.val[1], YnV, a2V); + + *pOut++ = vgetq_lane_f32(YnV, 3) ; + + sample--; + } + + /* Store the updated state variables back into the state array */ + vst2q_f32(pState,dV); + pState += 8; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /*Reset the output working pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stageCnt--; + + } + + /* Tail */ + stageCnt = stage & 3; + + while (stageCnt > 0U) + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /*Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn1 = *pIn++; + + /* y[n] = b0 * x[n] + d1 */ + acc1 = (b0 * Xn1) + d1; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc1; + + /* Every time after the output is computed state should be updated. */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1 = ((b1 * Xn1) + (a1 * acc1)) + d2; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2 = (b2 * Xn1) + (a2 * acc1); + + /* decrement the loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + *pState++ = d1; + *pState++ = d2; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /*Reset the output working pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stageCnt--; + } +} +#else + +void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Source pointer */ + float32_t *pOut = pDst; /* Destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t acc1; /* Accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1; /* Temporary input */ + float32_t d1, d2; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + pCoeffs += 5U; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 16 outputs at a time */ + sample = blockSize >> 4U; + + while (sample > 0U) { + + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 2 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 3 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 4 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 5 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 6 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 7 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 8 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 9 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 10 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 11 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 12 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 13 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 14 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 15 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 16 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0xFU; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1; + pState[1] = d2; + + pState += 2U; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} + +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c new file mode 100644 index 00000000..521f63b3 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c @@ -0,0 +1,443 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df2T_f64.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters +*/ + +/** + @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure + + This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure. + The filters are implemented as a cascade of second order Biquad sections. + These functions provide a slight memory savings as compared to the direct form I Biquad filter functions. + Only floating-point data is supported. + + This function operate on blocks of input and output data and each call to the function + processes blockSize samples through the filter. + pSrc points to the array of input data and + pDst points to the array of output data. + Both arrays contain blockSize values. + + @par Algorithm + Each Biquad stage implements a second order filter using the difference equation: +
+     y[n] = b0 * x[n] + d1
+     d1 = b1 * x[n] + a1 * y[n] + d2
+     d2 = b2 * x[n] + a2 * y[n]
+  
+ where d1 and d2 represent the two state values. + @par + A Biquad filter using a transposed Direct Form II structure is shown below. + \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad" + Coefficients b0, b1, and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients. + Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. + Pay careful attention to the sign of the feedback coefficients. + Some design tools flip the sign of the feedback coefficients: +
+     y[n] = b0 * x[n] + d1;
+     d1 = b1 * x[n] - a1 * y[n] + d2;
+     d2 = b2 * x[n] - a2 * y[n];
+  
+ In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library. + @par + Higher order filters are realized as a cascade of second order sections. + numStages refers to the number of second order stages used. + For example, an 8th order filter would be realized with numStages=4 second order stages. + A 9th order filter would be realized with numStages=5 second order stages with the + coefficients for one of the stages configured as a first order filter (b2=0 and a2=0). + @par + pState points to the state variable array. + Each Biquad stage has 2 state variables d1 and d2. + The state variables are arranged in the pState array as: +
+      {d11, d12, d21, d22, ...}
+  
+ where d1x refers to the state variables for the first Biquad and + d2x refers to the state variables for the second Biquad. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + @par + The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II. + The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types. + That is why the Direct Form I structure supports Q15 and Q31 data types. + The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2. + Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad. + The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + + @par Init Functions + There is also an associated initialization function. + The initialization function performs following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pCoeffs, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + For example, to statically initialize the instance structure use +
+      arm_biquad_cascade_df2T_instance_f64 S1 = {numStages, pState, pCoeffs};
+      arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};
+  
+ where numStages is the number of Biquad stages in the filter; + pState is the address of the state buffer. + pCoeffs is the address of the coefficient buffer; +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + + +void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + + const float64_t *pIn = pSrc; /* Source pointer */ + float64_t *pOut = pDst; /* Destination pointer */ + float64_t *pState = S->pState; /* State pointer */ + const float64_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float64_t acc1; /* Accumulator */ + float64_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float64_t Xn1; /* Temporary input */ + float64_t d1, d2; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + pCoeffs += 5U; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 16 outputs at a time */ + sample = blockSize >> 4U; + + while (sample > 0U) { + + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + +/* 2 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 3 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 4 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 5 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 6 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 7 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 8 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 9 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 10 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 11 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 12 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 13 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 14 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 15 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 16 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0xFU; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1; + pState[1] = d2; + + pState += 2U; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} + + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f16.c new file mode 100644 index 00000000..3f619e56 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f16.c @@ -0,0 +1,114 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df2T_init_f16.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order + in the not Neon version. +
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+  
+ + @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + + For Neon version, this array is bigger. If numstages = 4x + y, then the array has size: + 32*x + 5*y + and it must be initialized using the function + arm_biquad_cascade_df2T_compute_coefs_f16 which is taking the + standard array coefficient as parameters. + + But, an array of 8*numstages is a good approximation. + + Then, the initialization can be done with: +
+                   arm_biquad_cascade_df2T_init_f16(&SNeon, nbCascade, neonCoefs, stateNeon);
+                   arm_biquad_cascade_df2T_compute_coefs_f16(&SNeon,nbCascade,coefs);
+  
+ + @par In this example, neonCoefs is a bigger array of size 8 * numStages. + coefs is the standard array: + +
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+  
+ + + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_df2T_init_f16( + arm_biquad_cascade_df2T_instance_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 2 * numStages */ + memset(pState, 0, (2U * (uint32_t) numStages) * sizeof(float16_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c new file mode 100644 index 00000000..e3b350c3 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c @@ -0,0 +1,214 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df2T_init_f32.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + + + +#if defined(ARM_MATH_NEON) +/** + @brief Compute new coefficient arrays for use in vectorized filter (Neon only). + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the original filter coefficients. + @param[in] pComputedCoeffs points to the new computed coefficients for the vectorized Neon version. + @return none + + @par Size of coefficient arrays: + pCoeffs has size 5 * numStages + + pComputedCoeffs has size 8 * numStages + + pComputedCoeffs is the array to be used in arm_biquad_cascade_df2T_init_f32. + +*/ +void arm_biquad_cascade_df2T_compute_coefs_f32( + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pComputedCoeffs) +{ + uint8_t cnt; + float32_t b0[4],b1[4],b2[4],a1[4],a2[4]; + + cnt = numStages >> 2; + while(cnt > 0) + { + for(int i=0;i<4;i++) + { + b0[i] = pCoeffs[0]; + b1[i] = pCoeffs[1]; + b2[i] = pCoeffs[2]; + a1[i] = pCoeffs[3]; + a2[i] = pCoeffs[4]; + pCoeffs += 5; + } + + /* Vec 1 */ + *pComputedCoeffs++ = 0; + *pComputedCoeffs++ = b0[1]; + *pComputedCoeffs++ = b0[2]; + *pComputedCoeffs++ = b0[3]; + + /* Vec 2 */ + *pComputedCoeffs++ = 0; + *pComputedCoeffs++ = 0; + *pComputedCoeffs++ = b0[1] * b0[2]; + *pComputedCoeffs++ = b0[2] * b0[3]; + + /* Vec 3 */ + *pComputedCoeffs++ = 0; + *pComputedCoeffs++ = 0; + *pComputedCoeffs++ = 0; + *pComputedCoeffs++ = b0[1] * b0[2] * b0[3]; + + /* Vec 4 */ + *pComputedCoeffs++ = b0[0]; + *pComputedCoeffs++ = b0[0] * b0[1]; + *pComputedCoeffs++ = b0[0] * b0[1] * b0[2]; + *pComputedCoeffs++ = b0[0] * b0[1] * b0[2] * b0[3]; + + /* Vec 5 */ + *pComputedCoeffs++ = b1[0]; + *pComputedCoeffs++ = b1[1]; + *pComputedCoeffs++ = b1[2]; + *pComputedCoeffs++ = b1[3]; + + /* Vec 6 */ + *pComputedCoeffs++ = b2[0]; + *pComputedCoeffs++ = b2[1]; + *pComputedCoeffs++ = b2[2]; + *pComputedCoeffs++ = b2[3]; + + /* Vec 7 */ + *pComputedCoeffs++ = a1[0]; + *pComputedCoeffs++ = a1[1]; + *pComputedCoeffs++ = a1[2]; + *pComputedCoeffs++ = a1[3]; + + /* Vec 8 */ + *pComputedCoeffs++ = a2[0]; + *pComputedCoeffs++ = a2[1]; + *pComputedCoeffs++ = a2[2]; + *pComputedCoeffs++ = a2[3]; + + cnt--; + } + + cnt = numStages & 0x3; + while(cnt > 0) + { + *pComputedCoeffs++ = *pCoeffs++; + *pComputedCoeffs++ = *pCoeffs++; + *pComputedCoeffs++ = *pCoeffs++; + *pComputedCoeffs++ = *pCoeffs++; + *pComputedCoeffs++ = *pCoeffs++; + cnt--; + } + +} +#endif + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order + in the not Neon version. +
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+  
+ + @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + + For Neon version, this array is bigger. If numstages = 4x + y, then the array has size: + 32*x + 5*y + and it must be initialized using the function + arm_biquad_cascade_df2T_compute_coefs_f32 which is taking the + standard array coefficient as parameters. + + But, an array of 8*numstages is a good approximation. + + Then, the initialization can be done with: +
+                   arm_biquad_cascade_df2T_compute_coefs_f32(nbCascade,coefs,computedCoefs);
+                   arm_biquad_cascade_df2T_init_f32(&SNeon, nbCascade, computedCoefs, stateNeon);
+  
+ + @par In this example, computedCoefs is a bigger array of size 8 * numStages. + coefs is the standard array: + +
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+  
+ + + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ +void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 2 * numStages */ + memset(pState, 0, (2U * (uint32_t) numStages) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c new file mode 100644 index 00000000..5ab1c9a2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c @@ -0,0 +1,86 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df2T_init_f64.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure + @param[in] numStages number of 2nd order stages in the filter + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: +
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+  
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + const float64_t * pCoeffs, + float64_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 2 * numStages */ + memset(pState, 0, (2U * (uint32_t) numStages) * sizeof(float64_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f16.c new file mode 100644 index 00000000..60caf8d2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f16.c @@ -0,0 +1,434 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_stereo_df2T_f16.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter. 2 channels + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_biquad_cascade_stereo_df2T_f16 built. Helium version has build issues with gcc." +#endif + +#if (defined(ARM_MATH_MVE_FLOAT16) && defined(ARM_MATH_HELIUM_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) +void arm_biquad_cascade_stereo_df2T_f16( + const arm_biquad_cascade_stereo_df2T_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + float16_t *pIn = (float16_t *)pSrc; /* source pointer */ + float16_t *pOut = pDst; /* destination pointer */ + float16_t *pState = S->pState; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float16_t b0, b1, b2, a1, a2; /* Filter coefficients */ + uint32_t sample, stage = S->numStages; /* loop counters */ + static const uint16_t idx2[] = {2, 3, 8, 9, 2, 3, 8, 9}; + f16x8_t aCoeffs, bCoeffs; + float16_t scratch[16]; + uint16x8_t loadIdxVec; + uint16x8_t reshufledIdxVec; + uint16_t startIdx = 0; + f16x8_t stateVec0, stateVec1; + f16x8_t inVec; + + /* + * {0, 1, 0, 1, 0, 1, 0, 1} generator + */ + loadIdxVec = viwdupq_u16(startIdx, 2, 1); + reshufledIdxVec = *(uint16x8_t *)&idx2; + + /* + * scratch top clearing + * layout : [d1a d1b d2a d2b d1a d1b d2a d2b 0 0] + */ + scratch[8] = (float16_t)0.0; + scratch[9] = (float16_t)0.0; + + do + { + /* + * Reading the coefficients + */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* aCoeffs = {a1 a1 a2 a2 a1 a1 a2 a2} */ + aCoeffs = vdupq_n_f16(a1); + aCoeffs = vsetq_lane(a2, aCoeffs, 2); + aCoeffs = vsetq_lane(a2, aCoeffs, 3); + aCoeffs = vsetq_lane(a2, aCoeffs, 6); + aCoeffs = vsetq_lane(a2, aCoeffs, 7); + + /* bCoeffs = {b1 b1 b2 b2 b1 b1 b2 b2} */ + bCoeffs = vdupq_n_f16(b1); + bCoeffs = vsetq_lane(b2, bCoeffs, 2); + bCoeffs = vsetq_lane(b2, bCoeffs, 3); + bCoeffs = vsetq_lane(b2, bCoeffs, 6); + bCoeffs = vsetq_lane(b2, bCoeffs, 7); + + /* + * Reading the state values + * Save into scratch + */ + *(f16x8_t *) scratch = *(f16x8_t *) pState; + + sample = blockSize; + + while (sample > 0U) + { + /* + * step 1 + * + * 0 | acc1a = xn1a * b0 + d1a + * 1 | acc1b = xn1b * b0 + d1b + * 2 | acc1a = xn1a * b0 + d1a + * 3 | acc1b = xn1b * b0 + d1b + * 4 | + * 5 | ... + */ + + /* + * load {d1a, d1b, d1a, d1b, d1a, d1b, d1a, d1b} + */ + stateVec0 = vldrhq_gather_shifted_offset((float16_t const *) scratch, loadIdxVec); + /* + * load {in0 in1 in0 in1 in0 in1 in0 in1} + */ + inVec = vldrhq_gather_shifted_offset_f16(pIn, loadIdxVec); + + stateVec0 = vfmaq(stateVec0, inVec, b0); + *pOut++ = vgetq_lane(stateVec0, 0); + *pOut++ = vgetq_lane(stateVec0, 1); + + /* + * step 2 + * + * 0 | d1a = b1 * xn1a + a1 * acc1a + d2a + * 1 | d1b = b1 * xn1b + a1 * acc1b + d2b + * 2 | d2a = b2 * xn1a + a2 * acc1a + 0 + * 3 | d2b = b2 * xn1b + a2 * acc1b + 0 + * 4 | + * 5 | ... + */ + + /* + * load {d2a, d2b, 0, 0, d2a, d2b, 0, 0} + */ + stateVec1 = vldrhq_gather_shifted_offset((float16_t const *) scratch, reshufledIdxVec); + stateVec1 = vfmaq(stateVec1, stateVec0, aCoeffs); + stateVec1 = vfmaq(stateVec1, inVec, bCoeffs); + *(f16x8_t *) scratch = stateVec1; + + pIn = pIn + 2; + sample--; + } + + /* + * Store the updated state variables back into the state array + */ + *pState++ = vgetq_lane(stateVec1, 0); + *pState++ = vgetq_lane(stateVec1, 1); + *pState++ = vgetq_lane(stateVec1, 2); + *pState++ = vgetq_lane(stateVec1, 3); + + /* + * The current stage input is given as the output to the next stage + */ + pIn = pDst; + /* + * Reset the output working pointer + */ + pOut = pDst; + /* + * decrement the loop counter + */ + stage--; + } + while (stage > 0U); +} +#else + +void arm_biquad_cascade_stereo_df2T_f16( + const arm_biquad_cascade_stereo_df2T_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + const float16_t *pIn = pSrc; /* Source pointer */ + float16_t *pOut = pDst; /* Destination pointer */ + float16_t *pState = S->pState; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + _Float16 acc1a, acc1b; /* Accumulator */ + _Float16 b0, b1, b2, a1, a2; /* Filter coefficients */ + _Float16 Xn1a, Xn1b; /* Temporary input */ + _Float16 d1a, d2a, d1b, d2b; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1a = pState[0]; + d2a = pState[1]; + d1b = pState[2]; + d2b = pState[3]; + + pCoeffs += 5U; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 8 outputs at a time */ + sample = blockSize >> 3U; + + while (sample > 0U) { + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 2 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 3 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 4 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 5 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 6 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 7 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 8 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x7U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + /* Read the input */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + /* y[n] = b0 * x[n] + d1 */ + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc1a; + *pOut++ = acc1b; + + /* Every time after the output is computed state should be updated. */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1a; + pState[1] = d2a; + + pState[2] = d1b; + pState[3] = d2b; + + pState += 4U; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* Decrement the loop counter */ + stage--; + + } while (stage > 0U); + +} + +#endif /* #if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of BiquadCascadeDF2T group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c new file mode 100644 index 00000000..ddd15462 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c @@ -0,0 +1,420 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_stereo_df2T_f32.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter. 2 channels + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ +#if (defined(ARM_MATH_MVEF) && defined(ARM_MATH_HELIUM_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_helium_utils.h" + +void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + uint32_t sample, stage = S->numStages; /* loop counters */ + float32_t scratch[6]; + uint32x4_t loadIdxVec; + f32x4_t aCoeffs, bCoeffs; + f32x4_t stateVec0, stateVec1; + f32x4_t inVec; + uint32_t startIdx = 0; + + /* + * {0, 1, 0, 1} generator + */ + loadIdxVec = viwdupq_u32(&startIdx, 2, 1); + + /* + * scratch top clearing + * layout : [d1a d1b d2a d2b 0 0] + */ + scratch[4] = 0.0f; + scratch[5] = 0.0f; + + do + { + /* + * Reading the coefficients + */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* + * aCoeffs = {a1 a1 a2 a2} + */ + aCoeffs = vdupq_n_f32(a1); + aCoeffs = vsetq_lane(a2, aCoeffs, 2); + aCoeffs = vsetq_lane(a2, aCoeffs, 3); + + /* + * bCoeffs = {b1 b1 b2 b2} + */ + bCoeffs = vdupq_n_f32(b1); + bCoeffs = vsetq_lane(b2, bCoeffs, 2); + bCoeffs = vsetq_lane(b2, bCoeffs, 3); + + /* + * Reading the state values + * Save into scratch + */ + *(f32x4_t *) scratch = *(f32x4_t *) pState; + + sample = blockSize; + + while (sample > 0U) + { + /* + * step 1 + * + * 0 | acc1a = xn1a * b0 + d1a + * 1 | acc1b = xn1b * b0 + d1b + * 2 | acc1a = xn1a * b0 + d1a + * 3 | acc1b = xn1b * b0 + d1b + */ + /* + * load {d1a, d1b, d1a, d1b} + */ + stateVec0 = (f32x4_t)vldrwq_gather_shifted_offset((uint32_t const *) scratch, loadIdxVec); + /* + * load {in0 in1 in0 in1} + */ + inVec = (f32x4_t)vldrwq_gather_shifted_offset((uint32_t const *) pIn, loadIdxVec); + + stateVec0 = vfmaq(stateVec0, inVec, b0); + *pOut++ = vgetq_lane(stateVec0, 0); + *pOut++ = vgetq_lane(stateVec0, 1); + + /* + * step 2 + * + * 0 | d1a = b1 * xn1a + a1 * acc1a + d2a + * 1 | d1b = b1 * xn1b + a1 * acc1b + d2b + * 2 | d2a = b2 * xn1a + a2 * acc1a + 0 + * 3 | d2b = b2 * xn1b + a2 * acc1b + 0 + */ + + /* + * load {d2a, d2b, 0, 0} + */ + stateVec1 = *(f32x4_t *) & scratch[2]; + stateVec1 = vfmaq(stateVec1, stateVec0, aCoeffs); + stateVec1 = vfmaq(stateVec1, inVec, bCoeffs); + *(f32x4_t *) scratch = stateVec1; + + pIn = pIn + 2; + sample--; + } + + /* + * Store the updated state variables back into the state array + */ + vst1q(pState, stateVec1); + pState += 4; + + /* + * The current stage output is given as the input to the next stage + */ + pIn = pDst; + /* + * Reset the output working pointer + */ + pOut = pDst; + /* + * decrement the loop counter + */ + stage--; + } + while (stage > 0U); +} + +#else + +void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Source pointer */ + float32_t *pOut = pDst; /* Destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t acc1a, acc1b; /* Accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1a, Xn1b; /* Temporary input */ + float32_t d1a, d2a, d1b, d2b; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1a = pState[0]; + d2a = pState[1]; + d1b = pState[2]; + d2b = pState[3]; + + pCoeffs += 5U; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 8 outputs at a time */ + sample = blockSize >> 3U; + + while (sample > 0U) { + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 2 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 3 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 4 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 5 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 6 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 7 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 8 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x7U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + /* Read the input */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + /* y[n] = b0 * x[n] + d1 */ + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc1a; + *pOut++ = acc1b; + + /* Every time after the output is computed state should be updated. */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1a; + pState[1] = d2a; + + pState[2] = d1b; + pState[3] = d2b; + + pState += 4U; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* Decrement the loop counter */ + stage--; + + } while (stage > 0U); + +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f16.c new file mode 100644 index 00000000..633fbfef --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f16.c @@ -0,0 +1,90 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_stereo_df2T_init_f16.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: +
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+  
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2 for each channel. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_stereo_df2T_init_f16( + arm_biquad_cascade_stereo_df2T_instance_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float16_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c new file mode 100644 index 00000000..6932b9a4 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c @@ -0,0 +1,86 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_stereo_df2T_init_f32.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: +
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+  
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2 for each channel. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c new file mode 100644 index 00000000..7f2dd81d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c @@ -0,0 +1,964 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_f32.c + * Description: Convolution of floating-point sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup Conv Convolution + + Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector. + Convolution is similar to correlation and is frequently used in filtering and data analysis. + The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types. + The library also provides fast versions of the Q15 and Q31 functions. + + @par Algorithm + Let a[n] and b[n] be sequences of length srcALen and + srcBLen samples respectively. Then the convolution +
+     c[n] = a[n] * b[n]
+  
+ @par + is defined as + \image html ConvolutionEquation.gif + @par + Note that c[n] is of length srcALen + srcBLen - 1 and is defined over the interval n=0, 1, 2, ..., srcALen + srcBLen - 2. + pSrcA points to the first input vector of length srcALen and + pSrcB points to the second input vector of length srcBLen. + The output result is written to pDst and the calling function must allocate srcALen+srcBLen-1 words for the result. + @par + Conceptually, when two signals a[n] and b[n] are convolved, + the signal b[n] slides over a[n]. + For each offset \c n, the overlapping portions of a[n] and b[n] are multiplied and summed together. + @par + Note that convolution is a commutative operation: +
+     a[n] * b[n] = b[n] * a[n].
+  
+ @par + This means that switching the A and B arguments to the convolution functions has no effect. + + @par Fixed-Point Behavior + Convolution requires summing up a large number of intermediate products. + As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation. + Refer to the function specific documentation below for further details of the particular algorithm used. + + @par Fast Versions + Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of conv and the design requires + the input signals should be scaled down to avoid intermediate overflows. + + @par Opt Versions + Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. + These versions are optimised in cycles and consumes more memory (Scratch memory) compared to Q15 and Q7 versions + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of floating-point sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_filtering.h" + + +void arm_conv_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst) +{ + const float32_t *pIn1 = pSrcA; /* inputA pointer */ + const float32_t *pIn2 = pSrcB; /* inputB pointer */ + /* + * Loop to perform MAC operations according to correlation equation + */ + const float32_t *pX; + const float32_t *pY; + const float32_t *pA; + const float32_t *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t block1, block2, block3; + uint32_t vddupStartIdx = 3; + uint32x4_t decrIdxVec = vddupq_u32(vddupStartIdx, 1); + + if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA; + /* + * Swapping the lengths + */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2 - 3; + + for (i = 0; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + float32_t acc0; + float32_t acc1; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is incrementing for successive accumulators + * Y pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_F32(acc0, acc1, pX, pY, count); + + *pDst++ = acc0; + *pDst++ = acc1; + pB += 2; + } + + for (; i < block1; i++) + { + uint32_t count = i + 1; + float32_t acc; + + pX = pA; + pY = pB; + MVE_INTR_CONV_SINGLE_F32(acc, pX, pY, count); + + *pDst++ = acc; + pB++; + } + + for (i = 0; i <= block2 - 2; i += 2) + { + uint32_t count = srcBLen; + float32_t acc0 = 0; + float32_t acc1 = 0; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_F32(acc0, acc1, pX, pY, count); + *pDst++ = acc0; + *pDst++ = acc1; + pA += 2; + } + if (block2 & 1) + { + uint32_t count = srcBLen; + float32_t acc = 0; + + pX = pA; + pY = pB; + MVE_INTR_CONV_SINGLE_F32(acc, pX, pY, count); + + *pDst++ = acc; + pA++; + } + + for (i = block3; i >= 2; i -= 2) + { + int32_t count = i; + float32_t acc0; + float32_t acc1; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is decrementing for successive accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_F32(acc0, acc1, pX, pY, count); + + *pDst++ = acc0; + *pDst++ = acc1; + pA += 2; + } + for (; i >= 1; i--) + { + int32_t count = i; + float32_t acc; + + pX = pA; + pY = pB; + MVE_INTR_CONV_SINGLE_F32(acc, pX, pY, count); + + *pDst++ = acc; + pA++; + } +} +#else +void arm_conv_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst) +{ + +#if defined(ARM_MATH_DSP) + + const float32_t *pIn1; /* InputA pointer */ + const float32_t *pIn2; /* InputB pointer */ + float32_t *pOut = pDst; /* Output pointer */ + const float32_t *px; /* Intermediate inputA pointer */ + const float32_t *py; /* Intermediate inputB pointer */ + const float32_t *pSrc1, *pSrc2; /* Intermediate pointers */ + float32_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + float32_t acc0, acc1, acc2, acc3, c0; /* Accumulators */ +#if !defined(ARM_MATH_NEON) + float32_t x0, x1, x2, x3; /* Temporary variables to hold state and coefficient values */ +#endif +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ +#if defined(ARM_MATH_NEON) + float32x4_t vec1; + float32x4_t vec2; + float32x4_t res = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0); +#endif /* #if defined(ARM_MATH_NEON) */ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + +#if defined(ARM_MATH_NEON) + res = vdupq_n_f32(0) ; + accum = vdup_n_f32(0); + + /* Compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + + while (k > 0U) + { + vec1 = vld1q_f32(px); + vec2 = vld1q_f32(py-3); + vec2 = vrev64q_f32(vec2); + vec2 = vcombine_f32(vget_high_f32(vec2), vget_low_f32(vec2)); + + res = vmlaq_f32(res,vec1, vec2); + + /* Increment pointers */ + px += 4; + py -= 4; + + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count & 3; +#else + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum += *px++ * *py--; + + /* x[1] * y[srcBLen - 2] */ + sum += *px++ * *py--; + + /* x[2] * y[srcBLen - 3] */ + sum += *px++ * *py--; + + /* x[3] * y[srcBLen - 4] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#endif /* #if defined(ARM_MATH_NEON) */ + +#else /* defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + +#if defined(ARM_MATH_NEON) + float32x4_t c; + float32x4_t x1v; + float32x4_t x2v; + float32x4_t x; + float32x4_t res = vdupq_n_f32(0) ; +#endif /* #if defined(ARM_MATH_NEON) */ + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + +#if defined(ARM_MATH_NEON) + res = vdupq_n_f32(0) ; + + x1v = vld1q_f32(px); + x2v = vld1q_f32(px+4); + + do + { + c = vld1q_f32(py-3); + + px += 4; + x = x1v; + res = vmlaq_n_f32(res,x,c[3]); + + x = vextq_f32(x1v,x2v,1); + + res = vmlaq_n_f32(res,x,c[2]); + + x = vextq_f32(x1v,x2v,2); + + res = vmlaq_n_f32(res,x,c[1]); + + x = vextq_f32(x1v,x2v,3); + + res = vmlaq_n_f32(res,x,c[0]); + + py -= 4; + + x1v = x2v ; + x2v = vld1q_f32(px+4); + + } while (--k); + + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen & 0x3; + + x1v = vld1q_f32(px); + px += 4; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *(py--); + + res = vmlaq_n_f32(res,x1v,c0); + + /* Reuse the present samples for the next MAC */ + x1v[0] = x1v[1]; + x1v[1] = x1v[2]; + x1v[2] = x1v[3]; + + x1v[3] = *(px++); + + /* Decrement the loop counter */ + k--; + } + + acc0 = res[0]; + acc1 = res[1]; + acc2 = res[2]; + acc3 = res[3]; + +#else + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read x[3] sample */ + x3 = *(px); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 += x0 * c0; + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 += x1 * c0; + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 += x2 * c0; + /* acc3 += x[3] * y[srcBLen - 1] */ + acc3 += x3 * c0; + + /* Read y[srcBLen - 2] sample */ + c0 = *py--; + /* Read x[4] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 += x1 * c0; + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 += x2 * c0; + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 += x3 * c0; + /* acc3 += x[4] * y[srcBLen - 2] */ + acc3 += x0 * c0; + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read x[5] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 += x2 * c0; + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 += x3 * c0; + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 += x0 * c0; + /* acc3 += x[5] * y[srcBLen - 2] */ + acc3 += x1 * c0; + + /* Read y[srcBLen - 4] sample */ + c0 = *py--; + /* Read x[6] sample */ + x2 = *(px + 3U); + px += 4U; + + /* Perform the multiply-accumulate */ + /* acc0 += x[3] * y[srcBLen - 4] */ + acc0 += x3 * c0; + /* acc1 += x[4] * y[srcBLen - 4] */ + acc1 += x0 * c0; + /* acc2 += x[5] * y[srcBLen - 4] */ + acc2 += x1 * c0; + /* acc3 += x[6] * y[srcBLen - 4] */ + acc3 += x2 * c0; + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += x0 * c0; + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += x1 * c0; + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += x2 * c0; + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 += x3 * c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } +#endif /* #if defined(ARM_MATH_NEON) */ + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc0; + *pOut++ = acc1; + *pOut++ = acc2; + *pOut++ = acc3; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined (ARM_MATH_NEON)*/ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined(ARM_MATH_NEON) || defined (ARM_MATH_LOOPUNROLL) + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + +#if defined (ARM_MATH_NEON) + float32x4_t res = vdupq_n_f32(0) ; + float32x4_t x = vdupq_n_f32(0) ; + float32x4_t y = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0) ; + + /* First part of the processing. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + x = vld1q_f32(px); + y = vld1q_f32(py-3); + + y = vrev64q_f32(y); + y = vcombine_f32(vget_high_f32(y), vget_low_f32(y)); + + res = vmlaq_f32(res,x,y); + + px += 4 ; + py -= 4 ; + + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen & 0x3U; + +#else + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + sum += *px++ * *py--; + sum += *px++ * *py--; + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#endif /* if defined (ARM_MATH_NEON) */ +#else + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined(ARM_MATH_NEON) || defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + /* Loop unrolling: Compute 4 outputs at a time */ + k = blockSize3 >> 2U; + +#if defined(ARM_MATH_NEON) + float32x4_t res = vdupq_n_f32(0) ; + float32x4_t x = vdupq_n_f32(0) ; + float32x4_t y = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0) ; + + while (k > 0U) + { + x = vld1q_f32(px); + y = vld1q_f32(py-3); + + y = vrev64q_f32(y); + y = vcombine_f32(vget_high_f32(y), vget_low_f32(y)); + + res = vmlaq_f32(res,x,y); + + px += 4 ; + py -= 4 ; + + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; + +#else + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } +#endif /* #if defined (ARM_MATH_NEON) */ + + /* Loop unrolling: Compute remaining outputs */ + k = blockSize3 % 0x4U; +#else + + /* Initialize blkCnt with number of samples */ + k = blockSize3; + +#endif /* #if defined (ARM_MATH_NEON) || defined (ARM_MATH_LOOPUNROLL)*/ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement the loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const float32_t *pIn1 = pSrcA; /* InputA pointer */ + const float32_t *pIn2 = pSrcB; /* InputB pointer */ + float32_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i < (srcALen + srcBLen - 1U); i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0.0f; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ( pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = sum; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Conv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c new file mode 100644 index 00000000..06629f1a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c @@ -0,0 +1,366 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_fast_opt_q15.c + * Description: Fast Q15 Convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1 + @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2 + @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results + but provides only a single guard bit. There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, + as maximum of min(srcALen, srcBLen) number of additions are carried internally. + The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result. + + @remark + Refer to \ref arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. + */ + +void arm_conv_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q31_t acc0; /* Accumulators */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */ + const q15_t *px; /* Intermediate inputA pointer */ + q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, k, blkCnt; /* Loop counter */ + uint32_t tapCnt; /* Loop count */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */ + q31_t y1, y2; /* State variables */ +#endif + + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Pointer to take end of scratch2 buffer */ + pScr2 = pScratch2 + srcBLen - 1; + + /* points to smaller length sequence */ + px = pIn2; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + /* Copy smaller length input sequence in reverse order into second scratch buffer */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Assuming scratch1 buffer is aligned by 32-bit */ + /* Fill (srcBLen - 1U) zeros in scratch1 buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */ + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + + /* Initialization of pIn2 pointer */ + pIn2 = py; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLAD(x2, y2, acc0); + acc2 = __SMLAD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + acc1 = __SMLADX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLADX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (srcALen + srcBLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch1 buffer */ + acc0 += (*pScr1++ * *pIn2++); + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 1U; + } + +} + +/** + @} end of Conv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c new file mode 100644 index 00000000..5337a82e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c @@ -0,0 +1,663 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_fast_q15.c + * Description: Fast Q15 Convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1 + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results + but provides only a single guard bit. There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, + as maximum of min(srcALen, srcBLen) number of additions are carried internally. + The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result. + + @remark + Refer to \ref arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. + */ + +void arm_conv_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations less than 4 */ + /* Second part of this stage computes the MAC operations greater than or equal to 4 */ + + /* The first part of the stage starts here */ + while ((count < 4U) && (blockSize1 > 0U)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Loop over number of MAC operations between + * inputA samples and inputB samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* The second part of the stage starts here */ + /* The internal loop, over count, is unrolled by 4 */ + /* To, read the last two inputB samples using SIMD: + * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */ + py = py - 1; + + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + (count - 1U); + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* -------------------- + * Stage2 process + * -------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unroll over blockSize2, by 4 */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + py = py - 1U; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the last two inputB samples using SIMD: + * y[srcBLen - 1] and y[srcBLen - 2] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLADX(x0, c0, acc0); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLADX(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLADX(x2, c0, acc2); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLADX(x3, c0, acc3); + + /* Read y[srcBLen - 3] and y[srcBLen - 4] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLADX(x2, c0, acc0); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLADX(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLADX(x0, c0, acc2); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLADX(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + * So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[srcBLen - 5] */ + c0 = *(py+1); + +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + acc2 = __SMLADX(x1, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x0, c0, acc0); + acc1 = __SMLADX(x1, c0, acc1); + acc2 = __SMLADX(x3, c0, acc2); + acc3 = __SMLADX(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x0, c0, acc0); + acc1 = __SMLADX(x1, c0, acc1); + acc2 = __SMLADX(x3, c0, acc2); + acc3 = __SMLADX(x2, c0, acc3); + + /* Read y[srcBLen - 7] */ + c0 = *(py-1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x1, c0, acc0); + acc1 = __SMLAD(x2, c0, acc1); + acc2 = __SMLADX(x2, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + /* Store the result in the accumulator in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT((acc0 >> 15), (acc1 >> 15), 16)); + write_q15x2_ia (&pOut, __PKHBT((acc2 >> 15), (acc3 >> 15), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT((acc1 >> 15), (acc0 >> 15), 16)); + write_q15x2_ia (&pOut, __PKHBT((acc3 >> 15), (acc2 >> 15), 16)); +#endif /*#ifndef ARM_MATH_BIG_ENDIAN*/ + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + pIn2 = pSrc2 - 1U; + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations greater than 4 */ + /* Second part of this stage computes the MAC operations less than or equal to 4 */ + + /* The first part of the stage starts here */ + j = blockSize3 >> 2U; + + while ((j > 0U) && (blockSize3 > 0U)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied + * with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied + * with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = blockSize3 % 0x4U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement loop counter */ + blockSize3--; + + j--; + } + + /* The second part of the stage starts here */ + /* SIMD is not used for the next MAC operations, + * so pointer py is updated to read only one sample at a time */ + py = py + 1U; + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement the loop counter */ + blockSize3--; + } + +} + +/** + @} end of Conv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c new file mode 100644 index 00000000..133c322c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c @@ -0,0 +1,558 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_fast_q31.c + * Description: Fast Q31 Convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are accumulated in a 32-bit register in 2.30 format. + Finally, the accumulator is saturated and converted to a 1.31 result. + @par + The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signals must be scaled down. + Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, + as maximum of min(srcALen, srcBLen) number of additions are carried internally. + @remark + Refer to \ref arm_conv_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. + */ + +void arm_conv_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[1] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[2] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[3] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unroll over blockSize2, by 4 */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read x[3] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[3] * y[srcBLen - 1] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + + /* Read y[srcBLen - 2] sample */ + c0 = *py--; + /* Read x[4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc3 += x[4] * y[srcBLen - 2] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32); + + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read x[5] sample */ + x1 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc1 += x[3] * y[srcBLen - 3] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc2 += x[4] * y[srcBLen - 3] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc3 += x[5] * y[srcBLen - 3] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32); + + + /* Read y[srcBLen - 4] sample */ + c0 = *py--; + /* Read x[6] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[3] * y[srcBLen - 4] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc1 += x[4] * y[srcBLen - 4] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc2 += x[5] * y[srcBLen - 4] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc3 += x[6] * y[srcBLen - 4] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32); + + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (acc0 << 1); + *pOut++ = (q31_t) (acc1 << 1); + *pOut++ = (q31_t) (acc2 << 1); + *pOut++ = (q31_t) (acc3 << 1); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = blockSize3 % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement loop counter */ + blockSize3--; + } + +} + +/** + @} end of Conv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c new file mode 100644 index 00000000..1f3efe00 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c @@ -0,0 +1,362 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_opt_q15.c + * Description: Convolution of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both inputs are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + @remark + Refer to \ref arm_conv_fast_q15() for a faster but less precise version of this function. + */ + +void arm_conv_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q63_t acc0; /* Accumulators */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */ + const q15_t *px; /* Intermediate inputA pointer */ + q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, k, blkCnt; /* Loop counter */ + uint32_t tapCnt; /* Loop count */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc1, acc2, acc3; /* Accumulators */ + q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */ + q31_t y1, y2; /* State variables */ +#endif + + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Pointer to take end of scratch2 buffer */ + pScr2 = pScratch2 + srcBLen - 1; + + /* points to smaller length sequence */ + px = pIn2; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + /* Copy smaller length input sequence in reverse order into second scratch buffer */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Assuming scratch1 buffer is aligned by 32-bit */ + /* Fill (srcBLen - 1U) zeros in scratch1 buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */ + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + + /* Initialization of pIn2 pointer */ + pIn2 = py; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLALD(x1, y1, acc0); + acc2 = __SMLALD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLALDX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLALD(x2, y2, acc0); + acc2 = __SMLALD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLALDX(x3, y1, acc3); + acc1 = __SMLALDX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLALDX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (srcALen + srcBLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch1 buffer */ + acc0 += (*pScr1++ * *pIn2++); + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 1U; + } + +} + +/** + @} end of Conv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c new file mode 100644 index 00000000..1f12f0d2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c @@ -0,0 +1,360 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_opt_q7.c + * Description: Convolution of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. + The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format. + */ + +void arm_conv_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch */ + q15_t x4; /* Temporary input variable */ + q15_t *py; /* Temporary input2 pointer */ + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + const q7_t *pIn1, *pIn2; /* InputA and inputB pointer */ + uint32_t j, k, blkCnt, tapCnt; /* Loop counter */ + q31_t x1, x2, x3, y1; /* Temporary input variables */ + const q7_t *px; /* Temporary input1 pointer */ + q7_t *pOut = pDst; /* Output pointer */ + q7_t out0, out1, out2, out3; /* Temporary variables */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* points to smaller length sequence */ + px = pIn2 + srcBLen - 1; + + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + ** a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) *px--; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy (srcALen) samples in scratch buffer */ + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcALen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + ** a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + ** No loop unrolling is used. */ + k = srcALen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) * pIn1++; + *pScr1++ = x4; + + /* Decrement the loop counter */ + k--; + } + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* Initialization of pIn2 pointer */ + pIn2 = (q7_t *) py; + + pScr2 = py; + + /* Actual convolution process starts here */ + blkCnt = (srcALen + srcBLen - 1U) >> 2U; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + acc0 = __SMLAD(x2, y1, acc0); + + acc2 = __SMLAD(x1, y1, acc2); + + acc1 = __SMLADX(x3, y1, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2); + acc1 += (*pScr1++ * *pScr2); + acc2 += (*pScr1++ * *pScr2); + acc3 += (*pScr1++ * *pScr2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + out0 = (q7_t) (__SSAT(acc0 >> 7U, 8)); + out1 = (q7_t) (__SSAT(acc1 >> 7U, 8)); + out2 = (q7_t) (__SSAT(acc2 >> 7U, 8)); + out3 = (q7_t) (__SSAT(acc3 >> 7U, 8)); + + write_q7x4_ia (&pOut, __PACKq7(out0, out1, out2, out3)); + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 4U; + } + + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + acc0 += (*pScr1++ * *pScr2++); + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8)); + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 1U; + } + +} + +/** + @} end of Conv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c new file mode 100644 index 00000000..a8a9bd1a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c @@ -0,0 +1,678 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_f32.c + * Description: Partial convolution of floating-point sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup PartialConv Partial Convolution + + Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated. + Each function has two additional arguments. + firstIndex specifies the starting index of the subset of output samples. + numPoints is the number of output samples to compute. + The function computes the output in the range + [firstIndex, ..., firstIndex+numPoints-1]. + The output array pDst contains numPoints values. + + The allowable range of output indices is [0 srcALen+srcBLen-2]. + If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR. + Otherwise the functions return ARM_MATH_SUCCESS. + \note Refer to \ref arm_conv_f32() for details on fixed point behavior. + + @par Fast Versions + Fast versions are supported for Q31 and Q15 of partial convolution. + Cycles for Fast versions are less compared to Q31 and Q15 of partial conv and the design requires + the input signals should be scaled down to avoid intermediate overflows. + + @par Opt Versions + Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. + These versions are optimised in cycles and consumes more memory (Scratch memory) compared to Q15 and Q7 versions of partial convolution + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of floating-point sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + */ + +arm_status arm_conv_partial_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ +#if defined (ARM_MATH_DSP) + const float32_t *pIn1 = pSrcA; /* InputA pointer */ + const float32_t *pIn2 = pSrcB; /* InputB pointer */ + float32_t *pOut = pDst; /* Output pointer */ + const float32_t *px; /* Intermediate inputA pointer */ + const float32_t *py; /* Intermediate inputB pointer */ + const float32_t *pSrc1, *pSrc2; /* Intermediate pointers */ + float32_t sum; /* Accumulator */ + uint32_t j, k, count, blkCnt, check; + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t acc0, acc1, acc2, acc3; /* Accumulator */ + float32_t x0, x1, x2, x3, c0; /* Temporary variables */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t)numPoints) : 0; + blockSize2 = ((int32_t) check - blockSize3) - (blockSize1 + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + firstIndex; + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum += *px++ * *py--; + + /* x[1] * y[srcBLen - 2] */ + sum += *px++ * *py--; + + /* x[2] * y[srcBLen - 3] */ + sum += *px++ * *py--; + + /* x[3] * y[srcBLen - 4] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc1; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read x[3] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 += x0 * c0; + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 += x1 * c0; + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 += x2 * c0; + /* acc3 += x[3] * y[srcBLen - 1] */ + acc3 += x3 * c0; + + /* Read y[srcBLen - 2] sample */ + c0 = *py--; + /* Read x[4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 += x1 * c0; + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 += x2 * c0; + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 += x3 * c0; + /* acc3 += x[4] * y[srcBLen - 2] */ + acc3 += x0 * c0; + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read x[5] sample */ + x1 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 += x2 * c0; + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 += x3 * c0; + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 += x0 * c0; + /* acc3 += x[5] * y[srcBLen - 2] */ + acc3 += x1 * c0; + + /* Read y[srcBLen - 4] sample */ + c0 = *py--; + /* Read x[6] sample */ + x2 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[3] * y[srcBLen - 4] */ + acc0 += x3 * c0; + /* acc1 += x[4] * y[srcBLen - 4] */ + acc1 += x0 * c0; + /* acc2 += x[5] * y[srcBLen - 4] */ + acc2 += x1 * c0; + /* acc3 += x[6] * y[srcBLen - 4] */ + acc3 += x2 * c0; + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += x0 * c0; + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += x1 * c0; + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += x2 * c0; + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 += x3 * c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc0; + *pOut++ = acc1; + *pOut++ = acc2; + *pOut++ = acc3; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += *px++ * *py--; + sum += *px++ * *py--; + sum += *px++ * *py--; + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#else +/* alternate version for CM0_FAMILY */ + + const float32_t *pIn1 = pSrcA; /* InputA pointer */ + const float32_t *pIn2 = pSrcB; /* InputB pointer */ + float32_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* Loop to calculate convolution for output length number of values */ + for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0.0f; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ( pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = sum; + } + + /* Set status as ARM_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#endif /* defined(ARM_MATH_DSP) */ +} + +/** + @} end of PartialConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c new file mode 100644 index 00000000..a6b9ecf3 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c @@ -0,0 +1,387 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_fast_opt_q15.c + * Description: Fast Q15 Partial convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2 + @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen) + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. + */ + +arm_status arm_conv_partial_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */ + q31_t acc0; /* Accumulator */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + const q15_t *px; /* Intermediate inputA pointer */ + q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, k, blkCnt; /* Loop counter */ + uint32_t tapCnt; /* Loop count */ + arm_status status; /* Status variable */ + q31_t x1; /* Temporary variables to hold state and coefficient values */ + q31_t y1; /* State variables */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulator */ + q31_t x2, x3; /* Temporary variables to hold state and coefficient values */ + q31_t y2; /* State variables */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* pointer to take end of scratch2 buffer */ + pScr2 = pScratch2 + srcBLen - 1; + + /* points to smaller length sequence */ + px = pIn2; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + /* Copy smaller length input sequence in reverse order into second scratch buffer */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Assuming scratch1 buffer is aligned by 32-bit */ + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */ + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Initialization of pIn2 pointer */ + pIn2 = py; + + pScratch1 += firstIndex; + + pOut = pDst + firstIndex; + + /* Actual convolution process starts here */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (numPoints) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLAD(x2, y2, acc0); + acc2 = __SMLAD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + acc1 = __SMLADX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc3 = __SMLADX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numPoints & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numPoints; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read two samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + ** Then store the output in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 1U; + + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of PartialConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c new file mode 100644 index 00000000..3e928180 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c @@ -0,0 +1,707 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_fast_q15.c + * Description: Fast Q15 Partial convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + @remark + Refer to \ref arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. + */ + +arm_status arm_conv_partial_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary input variables */ + uint32_t j, k, count, blkCnt, check; + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t) numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations less than 4 */ + /* Second part of this stage computes the MAC operations greater than or equal to 4 */ + + /* The first part of the stage starts here */ + while ((count < 4U) && (blockSize1 > 0)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Loop over number of MAC operations between + * inputA samples and inputB samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* The second part of the stage starts here */ + /* The internal loop, over count, is unrolled by 4 */ + /* To, read the last two inputB samples using SIMD: + * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */ + py = py - 1; + + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2 - 1U; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + py = py - 1U; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the last two inputB samples using SIMD: + * y[srcBLen - 1] and y[srcBLen - 2] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLADX(x0, c0, acc0); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLADX(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLADX(x2, c0, acc2); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLADX(x3, c0, acc3); + + /* Read y[srcBLen - 3] and y[srcBLen - 4] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLADX(x2, c0, acc0); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLADX(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLADX(x0, c0, acc2); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLADX(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[srcBLen - 5] */ + c0 = *(py + 1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLAD (x0, c0, acc0); + acc1 = __SMLAD (x1, c0, acc1); + acc2 = __SMLADX(x1, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulate */ + acc0 = __SMLADX(x0, c0, acc0); + acc1 = __SMLADX(x1, c0, acc1); + acc2 = __SMLADX(x3, c0, acc2); + acc3 = __SMLADX(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLADX(x0, c0, acc0); + acc1 = __SMLADX(x1, c0, acc1); + acc2 = __SMLADX(x3, c0, acc2); + acc3 = __SMLADX(x2, c0, acc3); + + c0 = *(py-1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x1, c0, acc0); + acc1 = __SMLAD (x2, c0, acc1); + acc2 = __SMLADX(x2, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(acc0 >> 15, acc1 >> 15, 16)); + write_q15x2_ia (&pOut, __PKHBT(acc2 >> 15, acc3 >> 15, 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(acc1 >> 15, acc0 >> 15, 16)); + write_q15x2_ia (&pOut, __PKHBT(acc3 >> 15, acc2 >> 15, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + No loop unrolling is used. */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + pIn2 = pSrc2 - 1U; + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations greater than 4 */ + /* Second part of this stage computes the MAC operations less than or equal to 4 */ + + /* The first part of the stage starts here */ + j = count >> 2U; + + while ((j > 0U) && (blockSize3 > 0)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied + * with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied + * with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement the MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + + j--; + } + + /* The second part of the stage starts here */ + /* SIMD is not used for the next MAC operations, + * so pointer py is updated to read only one sample at a time */ + py = py + 1U; + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement the MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +} + +/** + @} end of PartialConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c new file mode 100644 index 00000000..65269bc9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c @@ -0,0 +1,625 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_fast_q31.c + * Description: Fast Q31 Partial convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. + */ + +arm_status arm_conv_partial_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t sum; /* Accumulators */ + uint32_t j, k, count, check, blkCnt; + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, x3, c0; +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t)numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[1] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[2] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[3] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read x[3] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[3] * y[srcBLen - 1] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Read y[srcBLen - 2] sample */ + c0 = *py--; + /* Read x[4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc3 += x[4] * y[srcBLen - 2] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read x[5] sample */ + x1 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc3 += x[5] * y[srcBLen - 2] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32); + + /* Read y[srcBLen - 4] sample */ + c0 = *py--; + /* Read x[6] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[3] * y[srcBLen - 4] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc1 += x[4] * y[srcBLen - 4] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc2 += x[5] * y[srcBLen - 4] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc3 += x[6] * y[srcBLen - 4] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (acc0 << 1); + *pOut++ = (q31_t) (acc1 << 1); + *pOut++ = (q31_t) (acc2 << 1); + *pOut++ = (q31_t) (acc3 << 1); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) * px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) * px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) * px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) * px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +} + +/** + @} end of PartialConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c new file mode 100644 index 00000000..7a9d6b18 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c @@ -0,0 +1,386 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_opt_q15.c + * Description: Partial convolution of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_fast_q15() for a faster but less precise version of this function. + */ + +arm_status arm_conv_partial_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2) +{ + + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */ + q63_t acc0; /* Accumulator */ + q31_t x1; /* Temporary variables to hold state and coefficient values */ + q31_t y1; /* State variables */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + const q15_t *px; /* Intermediate inputA pointer */ + q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, k, blkCnt; /* Loop counter */ + uint32_t tapCnt; /* Loop count */ + arm_status status; /* Status variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc1, acc2, acc3; /* Accumulator */ + q31_t x2, x3; /* Temporary variables to hold state and coefficient values */ + q31_t y2; /* State variables */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* pointer to take end of scratch2 buffer */ + pScr2 = pScratch2 + srcBLen - 1; + + /* points to smaller length sequence */ + px = pIn2; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + /* Copy smaller length input sequence in reverse order into second scratch buffer */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Assuming scratch1 buffer is aligned by 32-bit */ + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */ + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Initialization of pIn2 pointer */ + pIn2 = py; + + pScratch1 += firstIndex; + + pOut = pDst + firstIndex; + + /* Actual convolution process starts here */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (numPoints) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLALD(x1, y1, acc0); + acc2 = __SMLALD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLALDX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLALD(x2, y2, acc0); + acc2 = __SMLALD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLALDX(x3, y1, acc3); + acc1 = __SMLALDX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLALDX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numPoints & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numPoints; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read two samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + + acc0 = __SMLALD(x1, y1, acc0); + + /* Decrement the loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + ** Then store the output in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 1U; + + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of PartialConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c new file mode 100644 index 00000000..a5c16c50 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c @@ -0,0 +1,390 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_opt_q7.c + * Description: Partial convolution of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + */ + +arm_status arm_conv_partial_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q15_t *pScr2, *pScr1; /* Intermediate pointers for scratch pointers */ + q15_t x4; /* Temporary input variable */ + const q7_t *pIn1, *pIn2; /* InputA and inputB pointer */ + uint32_t j, k, blkCnt, tapCnt; /* Loop counter */ + const q7_t *px; /* Temporary input1 pointer */ + q15_t *py; /* Temporary input2 pointer */ + q31_t acc0, acc1, acc2, acc3; /* Accumulator */ + q31_t x1, x2, x3, y1; /* Temporary input variables */ + arm_status status; + q7_t *pOut = pDst; /* Output pointer */ + q7_t out0, out1, out2, out3; /* Temporary variables */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* pointer to take end of scratch2 buffer */ + pScr2 = pScratch2; + + /* points to smaller length sequence */ + px = pIn2 + srcBLen - 1; + + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + ** a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) *px--; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy (srcALen) samples in scratch buffer */ + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcALen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + ** a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + ** No loop unrolling is used. */ + k = srcALen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + + /* Decrement the loop counter */ + k--; + } + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* Initialization of pIn2 pointer */ + pIn2 = (q7_t *) py; + + pScr2 = py; + + pOut = pDst + firstIndex; + + pScratch1 += firstIndex; + + /* Actual convolution process starts here */ + blkCnt = (numPoints) >> 2; + + while (blkCnt > 0) + { + /* Initialize temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumulators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + acc0 = __SMLAD(x2, y1, acc0); + + acc2 = __SMLAD(x1, y1, acc2); + + acc1 = __SMLADX(x3, y1, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2); + acc1 += (*pScr1++ * *pScr2); + acc2 += (*pScr1++ * *pScr2); + acc3 += (*pScr1++ * *pScr2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + out0 = (q7_t) (__SSAT(acc0 >> 7U, 8)); + out1 = (q7_t) (__SSAT(acc1 >> 7U, 8)); + out2 = (q7_t) (__SSAT(acc2 >> 7U, 8)); + out3 = (q7_t) (__SSAT(acc3 >> 7U, 8)); + + write_q7x4_ia (&pOut, __PACKq7(out0, out1, out2, out3)); + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 4U; + } + + blkCnt = (numPoints) & 0x3; + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read two samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + acc0 = __SMLAD(x1, y1, acc0); + + /* Decrement the loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8)); + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 1U; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + return (status); +} + +/** + @} end of PartialConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c new file mode 100644 index 00000000..cfab5168 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c @@ -0,0 +1,759 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_q15.c + * Description: Partial convolution of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_fast_q15() for a faster but less precise version of this function. + @remark + Refer to \ref arm_conv_partial_opt_q15() for a faster implementation of this function using scratch buffers. + */ + +arm_status arm_conv_partial_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + +#if defined (ARM_MATH_DSP) + + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q63_t sum, acc0, acc1, acc2, acc3; /* Accumulator */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary input variables to hold state and coefficient values */ + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt, check; + arm_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t)numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations less than 4 */ + /* Second part of this stage computes the MAC operations greater than or equal to 4 */ + + /* The first part of the stage starts here */ + while ((count < 4U) && (blockSize1 > 0)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Loop over number of MAC operations between + * inputA samples and inputB samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* The second part of the stage starts here */ + /* The internal loop, over count, is unrolled by 4 */ + /* To, read the last two inputB samples using SIMD: + * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */ + py = py - 1; + + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2 - 1U; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + py = py - 1U; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the last two inputB samples using SIMD: + * y[srcBLen - 1] and y[srcBLen - 2] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLALDX(x0, c0, acc0); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLALDX(x2, c0, acc2); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLALDX(x3, c0, acc3); + + /* Read y[srcBLen - 3] and y[srcBLen - 4] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLALDX(x2, c0, acc0); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLALDX(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLALDX(x0, c0, acc2); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLALDX(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + * So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[srcBLen - 5] */ + c0 = *(py+1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD (x0, c0, acc0); + acc1 = __SMLALD (x1, c0, acc1); + acc2 = __SMLALDX(x1, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALDX(x0, c0, acc0); + acc1 = __SMLALDX(x1, c0, acc1); + acc2 = __SMLALDX(x3, c0, acc2); + acc3 = __SMLALDX(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLALDX(x0, c0, acc0); + acc1 = __SMLALDX(x1, c0, acc1); + acc2 = __SMLALDX(x3, c0, acc2); + acc3 = __SMLALDX(x2, c0, acc3); + + c0 = *(py-1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLALDX(x1, c0, acc0); + acc1 = __SMLALD (x2, c0, acc1); + acc2 = __SMLALDX(x2, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + No loop unrolling is used. */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT(sum >> 15, 16)); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT(sum >> 15, 16)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + pIn2 = pSrc2 - 1U; + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations greater than 4 */ + /* Second part of this stage computes the MAC operations less than or equal to 4 */ + + /* The first part of the stage starts here */ + j = count >> 2U; + + while ((j > 0U) && (blockSize3 > 0)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied + * with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied + * with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + + j--; + } + + /* The second part of the stage starts here */ + /* SIMD is not used for the next MAC operations, + * so pointer py is updated to read only one sample at a time */ + py = py + 1U; + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#else /* #if defined (ARM_MATH_DSP) */ + + const q15_t *pIn1 = pSrcA; /* InputA pointer */ + const q15_t *pIn2 = pSrcB; /* InputB pointer */ + q63_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* Loop to calculate convolution for output length number of values */ + for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q15_t) __SSAT((sum >> 15U), 16U); + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + @} end of PartialConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c new file mode 100644 index 00000000..bcd52983 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c @@ -0,0 +1,640 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_q31.c + * Description: Partial convolution of Q31 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q31 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_fast_q31() for a faster but less precise implementation of this function. + */ + +arm_status arm_conv_partial_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + +#if defined(ARM_MATH_DSP) + + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q63_t sum; /* Accumulator */ + uint32_t j, k, count, blkCnt, check; + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2; /* Accumulator */ + q31_t x0, x1, x2, c0; /* Temporary variables */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t)numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * (*py--); + + /* x[1] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * (*py--); + + /* x[2] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * (*py--); + + /* x[3] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * (*py--); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * (*py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unroll over blkCnt */ + blkCnt = blockSize2 / 3; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + + /* read x[0], x[1] samples */ + x0 = *px++; + x1 = *px++; + + /* Apply loop unrolling and compute 3 MACs simultaneously. */ + k = srcBLen / 3; + + /* First part of the processing with loop unrolling. Compute 3 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 2 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *(py); + + /* Read x[2] sample */ + x2 = *(px); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 += (q63_t) x0 * c0; + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 += (q63_t) x1 * c0; + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 += (q63_t) x2 * c0; + + /* Read y[srcBLen - 2] sample */ + c0 = *(py - 1U); + + /* Read x[3] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 += (q63_t) x1 * c0; + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 += (q63_t) x2 * c0; + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 += (q63_t) x0 * c0; + + /* Read y[srcBLen - 3] sample */ + c0 = *(py - 2U); + + /* Read x[4] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 += (q63_t) x2 * c0; + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 += (q63_t) x0 * c0; + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 += (q63_t) x1 * c0; + + + px += 3U; + + py -= 3U; + + } while (--k); + + /* If the srcBLen is not a multiple of 3, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen - (3 * (srcBLen / 3)); + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += (q63_t) x0 * c0; + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += (q63_t) x1 * c0; + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += (q63_t) x2 * c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (acc0 >> 31); + *pOut++ = (q31_t) (acc1 >> 31); + *pOut++ = (q31_t) (acc2 >> 31); + + /* Increment the pointer pIn1 index, count by 3 */ + count += 3U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 - 3 * (blockSize2 / 3); + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) *px++ * (*py--); + sum += (q63_t) *px++ * (*py--); + sum += (q63_t) *px++ * (*py--); + sum += (q63_t) *px++ * (*py--); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#else +/* alternate version for CM0_FAMILY */ + + const q31_t *pIn1 = pSrcA; /* InputA pointer */ + const q31_t *pIn2 = pSrcB; /* InputB pointer */ + q63_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* Loop to calculate convolution for output length number of values */ + for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q63_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q31_t) (sum >> 31U); + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of PartialConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c new file mode 100644 index 00000000..0532c51e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c @@ -0,0 +1,759 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_q7.c + * Description: Partial convolution of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_opt_q7() for a faster implementation of this function. + */ + +arm_status arm_conv_partial_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + +#if defined(ARM_MATH_DSP) + + const q7_t *pIn1; /* InputA pointer */ + const q7_t *pIn2; /* InputB pointer */ + q7_t *pOut = pDst; /* Output pointer */ + const q7_t *px; /* Intermediate inputA pointer */ + const q7_t *py; /* Intermediate inputB pointer */ + const q7_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t sum; /* Accumulator */ + uint32_t j, k, count, blkCnt, check; /* Loop counters */ + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc0, acc1, acc2, acc3; /* Accumulator */ + q31_t input1, input2; /* Temporary input variables */ + q15_t in1, in2; /* Temporary input variables */ + q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables to hold state and coefficient values */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t)numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] , x[1] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 1] , y[srcBLen - 2] */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* x[0] * y[srcBLen - 1] */ + /* x[1] * y[srcBLen - 2] */ + sum = __SMLAD(input1, input2, sum); + + /* x[2] , x[3] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 3] , y[srcBLen - 4] */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* x[2] * y[srcBLen - 3] */ + /* x[3] * y[srcBLen - 4] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) * px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7, 8)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read y[srcBLen - 2] sample */ + c1 = *py--; + + /* Read x[3] sample */ + x3 = *px++; + + /* x[0] and x[1] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 1] and y[srcBLen - 2] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[1] and x[2] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[4] sample */ + x0 = *px++; + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLAD(input1, input2, acc3); + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read y[srcBLen - 4] sample */ + c1 = *py--; + + /* Read x[5] sample */ + x1 = *px++; + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 3] and y[srcBLen - 4] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[4] and x[5] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[6] sample */ + x2 = *px++; + + /* x[5] and x[6] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLAD(input1, input2, acc3); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += ((q31_t) x0 * c0); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += ((q31_t) x1 * c0); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += ((q31_t) x2 * c0); + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 += ((q31_t) x3 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(acc0 >> 7, 8)); + *pOut++ = (q7_t) (__SSAT(acc1 >> 7, 8)); + *pOut++ = (q7_t) (__SSAT(acc2 >> 7, 8)); + *pOut++ = (q7_t) (__SSAT(acc3 >> 7, 8)); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) * px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7, 8)); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) * px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7, 8)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += ((q31_t) * px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7, 8)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#else +/* alternate version for CM0_FAMILY */ + + const q7_t *pIn1 = pSrcA; /* InputA pointer */ + const q7_t *pIn2 = pSrcB; /* InputB pointer */ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* Loop to calculate convolution for output length number of values */ + for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q15_t) pIn1[j] * (pIn2[i - j])); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q7_t) __SSAT((sum >> 7U), 8U); + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of PartialConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c new file mode 100644 index 00000000..0a28b959 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c @@ -0,0 +1,858 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_q15.c + * Description: Convolution of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both inputs are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + + @remark + Refer to \ref arm_conv_fast_q15() for a faster but less precise version of this function. + @remark + Refer to \ref arm_conv_opt_q15() for a faster implementation of this function using scratch buffers. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_helium_utils.h" +#include "arm_vec_filtering.h" + +void arm_conv_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + const q15_t *pIn1 = pSrcA; /* inputA pointer */ + const q15_t *pIn2 = pSrcB; /* inputB pointer */ + /* + * Loop to perform MAC operations according to correlation equation + */ + const q15_t *pX; + const q15_t *pY; + const q15_t *pA; + const q15_t *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t block1, block2, block3; + + + uint16x8_t decrIdxVec = vddupq_u16(7, 1); + + + if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA; + /* + * Swapping the lengths + */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2 - 7; + + for (i = 0; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_Q15(acc0, acc1, pX, pY, count); + *pDst++ = (q15_t) acc0; + *pDst++ = (q15_t) acc1; + pB += 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q15(acc, pX, pY, count); + *pDst++ = (q15_t) acc; + pB++; + } + + for (i = 0; i <= block2 - 4; i += 4) + { + uint32_t count = srcBLen; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + int64_t acc2 = 0LL; + int64_t acc3 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 4 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_QUAD_INC_X_FIXED_SIZE_Q15(acc0, acc1, acc2, acc3, pX, pY, count); + *pDst++ = (q15_t) acc0; + *pDst++ = (q15_t) acc1; + *pDst++ = (q15_t) acc2; + *pDst++ = (q15_t) acc3; + + pA += 4; + } + for (; i <= block2 - 2; i += 2) + { + uint32_t count = srcBLen; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_Q15(acc0, acc1, pX, pY, count); + *pDst++ = (q15_t) acc0; + *pDst++ = (q15_t) acc1; + + pA += 2; + } + if (block2 & 1) + { + uint32_t count = srcBLen; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q15(acc, pX, pY, count); + *pDst++ = (q15_t) acc; + pA++; + } + + for (i = block3; i >= 1; i -= 2) + { + uint32_t count = i; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_Q15(acc0, acc1, pX, pY, count); + *pDst++ = (q15_t) acc0; + *pDst++ = (q15_t) acc1; + pA += 2; + } + for (; i >= 1; i--) + { + uint32_t count = i; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q15(acc, pX, pY, count); + *pDst++ = (q15_t) acc; + pA++; + } +} +#else +void arm_conv_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + +#if defined (ARM_MATH_DSP) + + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q63_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary input variables to hold state and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations less than 4 */ + /* Second part of this stage computes the MAC operations greater than or equal to 4 */ + + /* The first part of the stage starts here */ + while ((count < 4U) && (blockSize1 > 0U)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Loop over number of MAC operations between + * inputA samples and inputB samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* The second part of the stage starts here */ + /* The internal loop, over count, is unrolled by 4 */ + /* To, read the last two inputB samples using SIMD: + * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */ + py = py - 1; + + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + (count - 1U); + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + py = py - 1U; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the last two inputB samples using SIMD: + * y[srcBLen - 1] and y[srcBLen - 2] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLALDX(x0, c0, acc0); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLALDX(x2, c0, acc2); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLALDX(x3, c0, acc3); + + /* Read y[srcBLen - 3] and y[srcBLen - 4] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLALDX(x2, c0, acc0); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLALDX(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + + px += 4U; + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLALDX(x0, c0, acc2); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLALDX(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + * So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[srcBLen - 5] */ + c0 = *(py + 1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + acc2 = __SMLALDX(x1, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALDX(x0, c0, acc0); + acc1 = __SMLALDX(x1, c0, acc1); + acc2 = __SMLALDX(x3, c0, acc2); + acc3 = __SMLALDX(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLALDX(x0, c0, acc0); + acc1 = __SMLALDX(x1, c0, acc1); + acc2 = __SMLALDX(x3, c0, acc2); + acc3 = __SMLALDX(x2, c0, acc3); + + c0 = *(py-1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLALDX(x1, c0, acc0); + acc1 = __SMLALD(x2, c0, acc1); + acc2 = __SMLALDX(x2, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + /* Store the result in the accumulator in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT(sum >> 15, 16)); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT(sum >> 15, 16)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + blockSize3 = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + pIn2 = pSrc2 - 1U; + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations greater than 4 */ + /* Second part of this stage computes the MAC operations less than or equal to 4 */ + + /* The first part of the stage starts here */ + j = blockSize3 >> 2U; + + while ((j > 0U) && (blockSize3 > 0U)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied + * with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied + * with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = blockSize3 % 0x4U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement loop counter */ + blockSize3--; + + j--; + } + + /* The second part of the stage starts here */ + /* SIMD is not used for the next MAC operations, + * so pointer py is updated to read only one sample at a time */ + py = py + 1U; + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement loop counter */ + blockSize3--; + } + +#else /* #if defined (ARM_MATH_DSP) */ + + const q15_t *pIn1 = pSrcA; /* InputA pointer */ + const q15_t *pIn2 = pSrcB; /* InputB pointer */ + q63_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + + /* Loop to calculate convolution for output length number of values */ + for (i = 0; i < (srcALen + srcBLen - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q15_t) __SSAT((sum >> 15U), 16U); + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Conv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c new file mode 100644 index 00000000..ee37824f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c @@ -0,0 +1,745 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_q31.c + * Description: Convolution of Q31 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q31 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, + as maximum of min(srcALen, srcBLen) number of additions are carried internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + + @remark + Refer to \ref arm_conv_fast_q31() for a faster but less precise implementation of this function. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_helium_utils.h" +#include "arm_vec_filtering.h" + +void arm_conv_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + const q31_t *pIn1 = pSrcA; /* inputA pointer */ + const q31_t *pIn2 = pSrcB; /* inputB pointer */ + /* + * Loop to perform MAC operations according to correlation equation + */ + const q31_t *pX; + const q31_t *pY; + const q31_t *pA; + const q31_t *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t block1, block2, block3; + uint32_t vddupStartIdx = 3; + uint32x4_t decrIdxVec = vddupq_u32(vddupStartIdx, 1); + + if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA; + /* + * Swapping the lengths + */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2 - 3; + + for (i = 0; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_Q31(acc0, acc1, pX, pY, count); + + *pDst++ = (q31_t) acc0; + *pDst++ = (q31_t) acc1; + pB += 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CONV_SINGLE_Q31(acc, pX, pY, count); + + *pDst++ = (q31_t) acc; + pB++; + } + + for (i = 0; i <= block2 - 4; i += 4) + { + uint32_t count = srcBLen; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + int64_t acc2 = 0LL; + int64_t acc3 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 4 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_QUAD_INC_X_FIXED_SIZE_Q31(acc0, acc1, acc2, acc3, pX, pY, count); + *pDst++ = (q31_t) acc0; + *pDst++ = (q31_t) acc1; + *pDst++ = (q31_t) acc2; + *pDst++ = (q31_t) acc3; + + pA += 4; + } + + for (; i <= block2 - 2; i += 2) + { + uint32_t count = srcBLen; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_Q31(acc0, acc1, pX, pY, count); + *pDst++ = (q31_t) acc0; + *pDst++ = (q31_t) acc1; + + pA += 2; + } + if (block2 & 1) + { + uint32_t count = srcBLen; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q31(acc, pX, pY, count); + *pDst++ = (q31_t) acc; + pA++; + } + + for (i = block3; i >= 2; i -= 2) + { + uint32_t count = i; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_Q31(acc0, acc1, pX, pY, count); + *pDst++ = (q31_t) acc0; + *pDst++ = (q31_t) acc1; + pA += 2; + } + + for (; i >= 1; i--) + { + uint32_t count = i; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q31(acc, pX, pY, count); + *pDst++ = (q31_t) acc; + pA++; + } + +} + +#else +void arm_conv_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q63_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2; /* Accumulators */ + q31_t x0, x1, x2, c0; /* Temporary variables to hold state and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * (*py--); + + /* x[1] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * (*py--); + + /* x[2] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * (*py--); + + /* x[3] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * (*py--); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unroll by 3 */ + blkCnt = blockSize2 / 3; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + + /* Apply loop unrolling and compute 3 MACs simultaneously. */ + k = srcBLen / 3; + + /* First part of the processing with loop unrolling. Compute 3 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 2 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *(py); + /* Read x[3] sample */ + x2 = *(px); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 += ((q63_t) x0 * c0); + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 += ((q63_t) x1 * c0); + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 += ((q63_t) x2 * c0); + + /* Read y[srcBLen - 2] sample */ + c0 = *(py - 1U); + /* Read x[4] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 += ((q63_t) x1 * c0); + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 += ((q63_t) x2 * c0); + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 += ((q63_t) x0 * c0); + + /* Read y[srcBLen - 3] sample */ + c0 = *(py - 2U); + /* Read x[5] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 += ((q63_t) x2 * c0); + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 += ((q63_t) x0 * c0); + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 += ((q63_t) x1 * c0); + + /* update scratch pointers */ + px += 3U; + py -= 3U; + + } while (--k); + + /* If the srcBLen is not a multiple of 3, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen - (3 * (srcBLen / 3)); + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += ((q63_t) x0 * c0); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += ((q63_t) x1 * c0); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += ((q63_t) x2 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (acc0 >> 31); + *pOut++ = (q31_t) (acc1 >> 31); + *pOut++ = (q31_t) (acc2 >> 31); + + /* Increment the pointer pIn1 index, count by 3 */ + count += 3U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 - 3 * (blockSize2 / 3); + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) *px++ * *py--; + sum += (q63_t) *px++ * *py--; + sum += (q63_t) *px++ * *py--; + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = blockSize3 >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = blockSize3 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = blockSize3; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const q31_t *pIn1 = pSrcA; /* InputA pointer */ + const q31_t *pIn2 = pSrcB; /* InputB pointer */ + q63_t sum; /* Accumulators */ + uint32_t i, j; /* Loop counters */ + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i < (srcALen + srcBLen - 1U); i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q63_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q31_t) (sum >> 31U); + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Conv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c new file mode 100644 index 00000000..e29a16dd --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c @@ -0,0 +1,860 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_q7.c + * Description: Convolution of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. + The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format. + @remark + Refer to \ref arm_conv_opt_q7() for a faster implementation of this function. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_helium_utils.h" + +#include "arm_vec_filtering.h" + +void arm_conv_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst) +{ + const q7_t *pIn1 = pSrcA; /* inputA pointer */ + const q7_t *pIn2 = pSrcB; /* inputB pointer */ + /* + * Loop to perform MAC operations according to correlation equation + */ + const q7_t *pX; + const q7_t *pY; + const q7_t *pA; + const q7_t *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t block1, block2, block3; + uint8_t vddupStartIdx = 15; + uint8x16_t decrIdxVec = vddupq_u8(vddupStartIdx, 1); + + if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA; + /* + * Swapping the lengths + */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2 - 15; + + for (i = 0; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + int32_t acc0 = 0; + int32_t acc1 = 0; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_Q7(acc0, acc1, pX, pY, count); + *pDst++ = (q7_t) acc0; + *pDst++ = (q7_t) acc1; + pB += 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + int32_t acc = 0; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q7(acc, pX, pY, count); + *pDst++ = (q7_t) acc; + pB++; + } + + for (i = 0; i <= block2 - 4; i += 4) + { + uint32_t count = srcBLen; + int32_t acc0 = 0; + int32_t acc1 = 0; + int32_t acc2 = 0; + int32_t acc3 = 0; + + pX = pA; + pY = pB; + /* + * compute 4 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_QUAD_INC_X_FIXED_SIZE_Q7(acc0, acc1, acc2, acc3, pX, pY, count); + *pDst++ = (q7_t) acc0; + *pDst++ = (q7_t) acc1; + *pDst++ = (q7_t) acc2; + *pDst++ = (q7_t) acc3; + pA += 4; + } + for (; i <= block2 - 2; i += 2) + { + uint32_t count = srcBLen; + int32_t acc0 = 0; + int32_t acc1 = 0; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_Q7(acc0, acc1, pX, pY, count); + *pDst++ = (q7_t) acc0; + *pDst++ = (q7_t) acc1; + pA += 2; + } + if (block2 & 1) + { + uint32_t count = srcBLen; + int32_t acc = 0; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q7(acc, pX, pY, count); + *pDst++ = (q7_t) acc; + pA++; + } + + for (i = block3; i >= 1; i -= 2) + { + uint32_t count = i; + int32_t acc0 = 0; + int32_t acc1 = 0; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_Q7(acc0, acc1, pX, pY, count); + *pDst++ = (q7_t) acc0; + *pDst++ = (q7_t) acc1; + pA += 2; + } + for (; i >= 1; i--) + { + uint32_t count = i; + int32_t acc = 0; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q7(acc, pX, pY, count); + *pDst++ = (q7_t) acc; + pA++; + } +} + +#else +void arm_conv_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst) +{ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + const q7_t *pIn1; /* InputA pointer */ + const q7_t *pIn2; /* InputB pointer */ + q7_t *pOut = pDst; /* Output pointer */ + const q7_t *px; /* Intermediate inputA pointer */ + const q7_t *py; /* Intermediate inputB pointer */ + const q7_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t input1, input2; /* Temporary input variables */ + q15_t in1, in2; /* Temporary input variables */ + q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables to hold state and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] , x[1] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[srcBLen - 1] , y[srcBLen - 2] */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* x[0] * y[srcBLen - 1] */ + /* x[1] * y[srcBLen - 2] */ + sum = __SMLAD(input1, input2, sum); + + /* x[2] , x[3] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[srcBLen - 3] , y[srcBLen - 4] */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* x[2] * y[srcBLen - 3] */ + /* x[3] * y[srcBLen - 4] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read y[srcBLen - 2] sample */ + c1 = *py--; + + /* Read x[3] sample */ + x3 = *px++; + + /* x[0] and x[1] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[srcBLen - 1] and y[srcBLen - 2] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[1] and x[2] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[4] sample */ + x0 = *px++; + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLAD(input1, input2, acc3); + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read y[srcBLen - 4] sample */ + c1 = *py--; + + /* Read x[5] sample */ + x1 = *px++; + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[srcBLen - 3] and y[srcBLen - 4] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[4] and x[5] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[6] sample */ + x2 = *px++; + + /* x[5] and x[6] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLAD(input1, input2, acc3); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += ((q15_t) x0 * c0); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += ((q15_t) x1 * c0); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += ((q15_t) x2 * c0); + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 += ((q15_t) x3 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8)); + *pOut++ = (q7_t) (__SSAT(acc1 >> 7U, 8)); + *pOut++ = (q7_t) (__SSAT(acc2 >> 7U, 8)); + *pOut++ = (q7_t) (__SSAT(acc3 >> 7U, 8)); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8)); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = blockSize3 >> 2U; + + while (k > 0U) + { + /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = blockSize3 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = blockSize3; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += ((q15_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const q7_t *pIn1 = pSrcA; /* InputA pointer */ + const q7_t *pIn2 = pSrcB; /* InputB pointer */ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i < (srcALen + srcBLen - 1U); i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q15_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q7_t) __SSAT((sum >> 7U), 8U); + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Conv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f16.c new file mode 100644 index 00000000..5924b7ac --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f16.c @@ -0,0 +1,1159 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_f16.c + * Description: Correlation of floating-point sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters + */ + +/** + @defgroup Corr Correlation + + Correlation is a mathematical operation that is similar to convolution. + As with convolution, correlation uses two signals to produce a third signal. + The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution. + Correlation is commonly used to measure the similarity between two signals. + It has applications in pattern recognition, cryptanalysis, and searching. + The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types. + Fast versions of the Q15 and Q31 functions are also provided. + + @par Algorithm + Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively. + The convolution of the two signals is denoted by +
+      c[n] = a[n] * b[n]
+  
+ In correlation, one of the signals is flipped in time +
+       c[n] = a[n] * b[-n]
+  
+ @par + and this is mathematically defined as + \image html CorrelateEquation.gif + @par + The pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen. + The result c[n] is of length 2 * max(srcALen, srcBLen) - 1 and is defined over the interval n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2). + The output result is written to pDst and the calling function must allocate 2 * max(srcALen, srcBLen) - 1 words for the result. + + @note + The pDst should be initialized to all zeros before being used. + + @par Fixed-Point Behavior + Correlation requires summing up a large number of intermediate products. + As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation. + Refer to the function specific documentation below for further details of the particular algorithm used. + + @par Fast Versions + Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of correlate and the design requires + the input signals should be scaled down to avoid intermediate overflows. + + @par Opt Versions + Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. + These versions are optimised in cycles and consumes more memory (Scratch memory) compared to Q15 and Q7 versions of correlate + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of floating-point sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_filtering.h" + +#define MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_F16(acc0, acc1, pX, pY, count) \ +{ \ + float16_t const *pSrcX, *pSrcY; \ + f16x8_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f16(0.0f); \ + acc1Vec = vdupq_n_f16(0.0f); \ + pSrcX = (float16_t const *) pX; \ + pSrcY = (float16_t const *) pY; \ + k = count >> 3; \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vldrhq_f16(&pSrcY[-1]); \ + acc1Vec = vfmaq_f16(acc1Vec, xVec, yVec); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + acc0Vec = vfmaq_f16(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x8U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + mve_pred16_t p0 = vctp16q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vldrhq_f16(&pSrcY[-1]); \ + acc1Vec = vfmaq_m_f16(acc1Vec, xVec, yVec,p0); \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + acc0Vec = vfmaq_m_f16(acc0Vec, xVec, yVec,p0); \ + \ + acc0 = vecAddAcrossF16Mve(acc0Vec); \ + acc1 = vecAddAcrossF16Mve(acc1Vec); \ +} + +#define MVE_INTR_CORR_SINGLE_F16(acc, pX, pY, count) \ +{ \ + float16_t const *pSrcX, *pSrcY; \ + f16x8_t accVec, xVec, yVec; \ + uint16_t k; \ + \ + accVec = vdupq_n_f16(0.0f); \ + pSrcX = (float16_t const *) pX; \ + pSrcY = (float16_t const *) pY; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + accVec = vfmaq(accVec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + accVec = vfmaq_m(accVec, xVec, yVec, p0); \ + } \ + \ + acc = vecAddAcrossF16Mve(accVec); \ +} + +#define MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_F16(acc0, acc1, acc2, acc3, pX, pY, count) \ +{ \ + float16_t const *pSrcX, *pSrcY; \ + f16x8_t acc0Vec, acc1Vec, acc2Vec, acc3Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f16(0.0f); \ + acc1Vec = vdupq_n_f16(0.0f); \ + acc2Vec = vdupq_n_f16(0.0f); \ + acc3Vec = vdupq_n_f16(0.0f); \ + pSrcX = (float16_t const *) pX; \ + pSrcY = (float16_t const *) pY; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_f16(&pSrcX[1]); \ + acc1Vec = vfmaq_f16(acc1Vec, xVec, yVec); \ + xVec = vldrhq_f16(&pSrcX[2]); \ + acc2Vec = vfmaq_f16(acc2Vec, xVec, yVec); \ + xVec = vldrhq_f16(&pSrcX[3]); \ + acc3Vec = vfmaq_f16(acc3Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0Vec = vfmaq_f16(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_f16(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f16(acc1Vec, xVec, yVec, p0); \ + xVec = vldrhq_f16(&pSrcX[2]); \ + acc2Vec = vfmaq_m_f16(acc2Vec, xVec, yVec, p0); \ + xVec = vldrhq_f16(&pSrcX[3]); \ + acc3Vec = vfmaq_m_f16(acc3Vec, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0Vec = vfmaq_m_f16(acc0Vec, xVec, yVec, p0); \ + } \ + \ + acc0 = vecAddAcrossF16Mve(acc0Vec); \ + acc1 = vecAddAcrossF16Mve(acc1Vec); \ + acc2 = vecAddAcrossF16Mve(acc2Vec); \ + acc3 = vecAddAcrossF16Mve(acc3Vec); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_F16(acc0, acc1, pX, pY, count) \ +{ \ + float16_t const *pSrcX, *pSrcY; \ + f16x8_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f16(0.0f); \ + acc1Vec = vdupq_n_f16(0.0f); \ + pSrcX = (float16_t const *) pX; \ + pSrcY = (float16_t const *) pY; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_f16(&pSrcX[1]); \ + acc1Vec = vfmaq_f16(acc1Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0Vec = vfmaq_f16(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8;; \ + xVec = vldrhq_f16(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f16(acc1Vec, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0Vec = vfmaq_m_f16(acc0Vec, xVec, yVec, p0); \ + } \ + \ + acc0 = vecAddAcrossF16Mve(acc0Vec); \ + acc1 = vecAddAcrossF16Mve(acc1Vec); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_F16(acc0, acc1, pX, pY, count) \ +{ \ + float16_t const *pSrcX, *pSrcY; \ + f16x8_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f16(0.0f); \ + acc1Vec = vdupq_n_f16(0.0f); \ + pSrcX = (float16_t const *) pX; \ + pSrcY = (float16_t const *) pY; \ + k = (count-1) >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_f16(&pSrcX[1]); \ + acc1Vec = vfmaq_f16(acc1Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0Vec = vfmaq_f16(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + k = (count-1) % 0x8U; \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_f16(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f16(acc1Vec, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp16q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0Vec = vfmaq_m_f16(acc0Vec, xVec, yVec, p0); \ + \ + acc0 = vecAddAcrossF16Mve(acc0Vec); \ + acc1 = vecAddAcrossF16Mve(acc1Vec); \ +} + + + +void arm_correlate_f16( + const float16_t * pSrcA, + uint32_t srcALen, + const float16_t * pSrcB, + uint32_t srcBLen, + float16_t * pDst) +{ + float16_t *pIn1 = (float16_t *)pSrcA; /* inputA pointer */ + float16_t *pIn2 = (float16_t *)pSrcB + (srcBLen - 1U); /* inputB pointer */ + float16_t *pX; + float16_t *pY; + float16_t *pA; + float16_t *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t inv = 2U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + int32_t block1, block2, block3; + int32_t incr; + + tot = ((srcALen + srcBLen) - 2U); + if (srcALen > srcBLen) + { + /* + * Calculating the number of zeros to be padded to the output + */ + j = srcALen - srcBLen; + /* + * Initialize the pointer after zero padding + */ + pDst += j; + } + else if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = (float16_t *)pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = (float16_t *)pSrcA + (srcALen - 1U); + /* + * Initialisation of the pointer after zero padding + */ + pDst = pDst + tot; + /* + * Swapping the lengths + */ + + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + /* + * Setting the reverse flag + */ + inv = -2; + + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2; + incr = inv / 2; + + for (i = 0U; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + _Float16 acc0; + _Float16 acc1; + /* + * compute 2 accumulators per loop + * size is incrementing for second accumulator + * Y pointer is decrementing for second accumulator + */ + pX = pA; + pY = pB; + MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_F16(acc0, acc1, pX, pY, count); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + pB -= 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + _Float16 acc; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_F16(acc, pX, pY, count); + + *pDst = acc; + pDst += incr; + pB--; + } + + for (i = 0U; i <= block2 - 4; i += 4) + { + _Float16 acc0; + _Float16 acc1; + _Float16 acc2; + _Float16 acc3; + + pX = pA; + pY = pB; + /* + * compute 4 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_F16(acc0, acc1, acc2, acc3, pX, pY, srcBLen); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + *pDst = acc2; + pDst += incr; + *pDst = acc3; + pDst += incr; + pA += 4; + } + + for (; i <= block2 - 2; i += 2) + { + _Float16 acc0; + _Float16 acc1; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_F16(acc0, acc1, pX, pY, srcBLen); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + pA += 2; + } + + if (block2 & 1) + { + _Float16 acc; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_F16(acc, pX, pY, srcBLen); + + *pDst = acc; + pDst += incr; + pA++; + } + + for (i = block3 - 1; i >= 0; i -= 2) + { + + uint32_t count = (i + 1); + _Float16 acc0; + _Float16 acc1; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is decrementing for second accumulator + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_F16(acc0, acc1, pX, pY, count); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + pA += 2; + + } + for (; i >= 0; i--) + { + uint32_t count = (i + 1); + _Float16 acc; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_F16(acc, pX, pY, count); + + *pDst = acc; + pDst += incr; + pA++; + } +} + +#else +void arm_correlate_f16( + const float16_t * pSrcA, + uint32_t srcALen, + const float16_t * pSrcB, + uint32_t srcBLen, + float16_t * pDst) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_AUTOVECTORIZE) + + const float16_t *pIn1; /* InputA pointer */ + const float16_t *pIn2; /* InputB pointer */ + float16_t *pOut = pDst; /* Output pointer */ + const float16_t *px; /* Intermediate inputA pointer */ + const float16_t *py; /* Intermediate inputB pointer */ + const float16_t *pSrc1; + _Float16 sum; + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; /* Loop counter */ + int32_t inc = 1; /* Destination address modifier */ + +#if defined (ARM_MATH_LOOPUNROLL) + _Float16 acc0, acc1, acc2, acc3,c0; /* Accumulators */ + _Float16 x0, x1, x2, x3; /* temporary variables for holding input and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we assume zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding has to be done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f16; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* x[1] * y[srcBLen - 3] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* x[2] * y[srcBLen - 2] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* x[3] * y[srcBLen - 1] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0.0f16; + acc1 = 0.0f16; + acc2 = 0.0f16; + acc3 = 0.0f16; + + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[0] sample */ + c0 = *(py++); + /* Read x[3] sample */ + x3 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[0] */ + acc0 += (_Float16)x0 * (_Float16)c0; + /* acc1 += x[1] * y[0] */ + acc1 += (_Float16)x1 * (_Float16)c0; + /* acc2 += x[2] * y[0] */ + acc2 += (_Float16)x2 * (_Float16)c0; + /* acc3 += x[3] * y[0] */ + acc3 += (_Float16)x3 * (_Float16)c0; + + /* Read y[1] sample */ + c0 = *(py++); + /* Read x[4] sample */ + x0 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[1] */ + acc0 += (_Float16)x1 * (_Float16)c0; + /* acc1 += x[2] * y[1] */ + acc1 += (_Float16)x2 * (_Float16)c0; + /* acc2 += x[3] * y[1] */ + acc2 += (_Float16)x3 * (_Float16)c0; + /* acc3 += x[4] * y[1] */ + acc3 += (_Float16)x0 * (_Float16)c0; + + /* Read y[2] sample */ + c0 = *(py++); + /* Read x[5] sample */ + x1 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[2] */ + acc0 += (_Float16)x2 * (_Float16)c0; + /* acc1 += x[3] * y[2] */ + acc1 += (_Float16)x3 * (_Float16)c0; + /* acc2 += x[4] * y[2] */ + acc2 += (_Float16)x0 * (_Float16)c0; + /* acc3 += x[5] * y[2] */ + acc3 += (_Float16)x1 * (_Float16)c0; + + /* Read y[3] sample */ + c0 = *(py++); + /* Read x[6] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[3] * y[3] */ + acc0 += (_Float16)x3 * (_Float16)c0; + /* acc1 += x[4] * y[3] */ + acc1 += (_Float16)x0 * (_Float16)c0; + /* acc2 += x[5] * y[3] */ + acc2 += (_Float16)x1 * (_Float16)c0; + /* acc3 += x[6] * y[3] */ + acc3 += (_Float16)x2 * (_Float16)c0; + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *(py++); + /* Read x[7] sample */ + x3 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[4] * y[4] */ + acc0 += (_Float16)x0 * (_Float16)c0; + /* acc1 += x[5] * y[4] */ + acc1 += (_Float16)x1 * (_Float16)c0; + /* acc2 += x[6] * y[4] */ + acc2 += (_Float16)x2 * (_Float16)c0; + /* acc3 += x[7] * y[4] */ + acc3 += (_Float16)x3 * (_Float16)c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = acc0; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = acc1; + pOut += inc; + + *pOut = acc2; + pOut += inc; + + *pOut = acc3; + pOut += inc; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f16; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (_Float16)*px++ * (_Float16)*py++; + sum += (_Float16)*px++ * (_Float16)*py++; + sum += (_Float16)*px++ * (_Float16)*py++; + sum += (_Float16)*px++ * (_Float16)*py++; + + /* Decrement loop counter */ + k--; + } + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f16; + + /* Loop over srcBLen */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f16; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const float16_t *pIn1 = pSrcA; /* inputA pointer */ + const float16_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + _Float16 sum; /* Accumulator */ + uint32_t i = 0U, j; /* Loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and a varaible, inv is set to 1 */ + /* If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we assume zeroes + * in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer */ + /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer */ + /* Once the zero padding is done the remaining of the output is calcualted + * using convolution but with the shorter signal time shifted. */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0.0f16; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) + { + /* z[i] += x[i-j] * y[j] */ + sum += (_Float16)pIn1[j] * (_Float16)pIn2[-((int32_t) i - (int32_t) j)]; + } + } + + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = sum; + else + *pDst++ = sum; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Corr group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c new file mode 100644 index 00000000..41a69a67 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c @@ -0,0 +1,1095 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_f32.c + * Description: Correlation of floating-point sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup Corr Correlation + + Correlation is a mathematical operation that is similar to convolution. + As with convolution, correlation uses two signals to produce a third signal. + The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution. + Correlation is commonly used to measure the similarity between two signals. + It has applications in pattern recognition, cryptanalysis, and searching. + The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types. + Fast versions of the Q15 and Q31 functions are also provided. + + @par Algorithm + Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively. + The convolution of the two signals is denoted by +
+      c[n] = a[n] * b[n]
+  
+ In correlation, one of the signals is flipped in time +
+       c[n] = a[n] * b[-n]
+  
+ @par + and this is mathematically defined as + \image html CorrelateEquation.gif + @par + The pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen. + The result c[n] is of length 2 * max(srcALen, srcBLen) - 1 and is defined over the interval n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2). + The output result is written to pDst and the calling function must allocate 2 * max(srcALen, srcBLen) - 1 words for the result. + + @note + The pDst should be initialized to all zeros before being used. + + @par Fixed-Point Behavior + Correlation requires summing up a large number of intermediate products. + As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation. + Refer to the function specific documentation below for further details of the particular algorithm used. + + @par Fast Versions + Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of correlate and the design requires + the input signals should be scaled down to avoid intermediate overflows. + + @par Opt Versions + Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. + These versions are optimised in cycles and consumes more memory (Scratch memory) compared to Q15 and Q7 versions of correlate + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of floating-point sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_filtering.h" + + +void arm_correlate_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst) +{ + const float32_t *pIn1 = pSrcA; /* inputA pointer */ + const float32_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + const float32_t *pX, *pY; + const float32_t *pA, *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t inv = 4U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + int32_t block1, block2, block3; + int32_t incr; + + tot = ((srcALen + srcBLen) - 2U); + if (srcALen > srcBLen) + { + /* + * Calculating the number of zeros to be padded to the output + */ + j = srcALen - srcBLen; + /* + * Initialize the pointer after zero padding + */ + pDst += j; + } + else if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA + (srcALen - 1U); + /* + * Initialisation of the pointer after zero padding + */ + pDst = pDst + tot; + /* + * Swapping the lengths + */ + + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + /* + * Setting the reverse flag + */ + inv = -4; + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2; + incr = inv / 4; + + for (i = 0U; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + float32_t acc0; + float32_t acc1; + + /* + * compute 2 accumulators per loop + * size is incrementing for second accumulator + * Y pointer is decrementing for second accumulator + */ + pX = pA; + pY = pB; + MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_F32(acc0, acc1, pX, pY, count); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + pB -= 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + float32_t acc; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_F32(acc, pX, pY, count); + + *pDst = acc; + pDst += incr; + pB--; + } + + for (i = 0U; i <= block2 - 4; i += 4) + { + float32_t acc0; + float32_t acc1; + float32_t acc2; + float32_t acc3; + + pX = pA; + pY = pB; + /* + * compute 4 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_F32(acc0, acc1, acc2, acc3, pX, pY, srcBLen); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + *pDst = acc2; + pDst += incr; + *pDst = acc3; + pDst += incr; + pA += 4; + } + + for (; i <= block2 - 2; i += 2) + { + float32_t acc0; + float32_t acc1; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_F32(acc0, acc1, pX, pY, srcBLen); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + pA += 2; + } + + if (block2 & 1) + { + float32_t acc; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_F32(acc, pX, pY, srcBLen); + + *pDst = acc; + pDst += incr; + pA++; + } + + for (i = block3 - 1; i >= 0; i -= 2) + { + + uint32_t count = (i + 1); + float32_t acc0; + float32_t acc1; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is decrementing for second accumulator + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_F32(acc0, acc1, pX, pY, count); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + pA += 2; + + } + for (; i >= 0; i--) + { + uint32_t count = (i + 1); + float32_t acc; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_F32(acc, pX, pY, count); + + *pDst = acc; + pDst += incr; + pA++; + } +} + +#else +void arm_correlate_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_AUTOVECTORIZE) + + const float32_t *pIn1; /* InputA pointer */ + const float32_t *pIn2; /* InputB pointer */ + float32_t *pOut = pDst; /* Output pointer */ + const float32_t *px; /* Intermediate inputA pointer */ + const float32_t *py; /* Intermediate inputB pointer */ + const float32_t *pSrc1; + float32_t sum; + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; /* Loop counter */ + int32_t inc = 1; /* Destination address modifier */ + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + float32_t acc0, acc1, acc2, acc3,c0; /* Accumulators */ +#if !defined(ARM_MATH_NEON) + float32_t x0, x1, x2, x3; /* temporary variables for holding input and coefficient values */ +#endif +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we assume zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding has to be done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + +#if defined(ARM_MATH_NEON) + float32x4_t x,y; + float32x4_t res = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0); + + while (k > 0U) + { + x = vld1q_f32(px); + y = vld1q_f32(py); + + res = vmlaq_f32(res,x, y); + + px += 4; + py += 4; + + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; + + k = count & 0x3; +#else + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] */ + sum += *px++ * *py++; + + /* x[1] * y[srcBLen - 3] */ + sum += *px++ * *py++; + + /* x[2] * y[srcBLen - 2] */ + sum += *px++ * *py++; + + /* x[3] * y[srcBLen - 1] */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#endif /* #if defined(ARM_MATH_NEON) */ +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + +#if defined(ARM_MATH_NEON) + float32x4_t c; + float32x4_t x1v; + float32x4_t x2v; + float32x4_t x; + float32x4_t res = vdupq_n_f32(0) ; +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + +#if defined(ARM_MATH_NEON) + /* Compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + res = vdupq_n_f32(0) ; + + x1v = vld1q_f32(px); + px += 4; + do + { + x2v = vld1q_f32(px); + c = vld1q_f32(py); + + py += 4; + + x = x1v; + res = vmlaq_n_f32(res,x,c[0]); + + x = vextq_f32(x1v,x2v,1); + + res = vmlaq_n_f32(res,x,c[1]); + + x = vextq_f32(x1v,x2v,2); + + res = vmlaq_n_f32(res,x,c[2]); + + x = vextq_f32(x1v,x2v,3); + + res = vmlaq_n_f32(res,x,c[3]); + + x1v = x2v; + px+=4; + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen & 0x3; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *(py++); + + res = vmlaq_n_f32(res,x1v,c0); + + /* Reuse the present samples for the next MAC */ + x1v[0] = x1v[1]; + x1v[1] = x1v[2]; + x1v[2] = x1v[3]; + + x1v[3] = *(px++); + + /* Decrement the loop counter */ + k--; + } + + px-=1; + + acc0 = res[0]; + acc1 = res[1]; + acc2 = res[2]; + acc3 = res[3]; +#else + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[0] sample */ + c0 = *(py++); + /* Read x[3] sample */ + x3 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[0] */ + acc0 += x0 * c0; + /* acc1 += x[1] * y[0] */ + acc1 += x1 * c0; + /* acc2 += x[2] * y[0] */ + acc2 += x2 * c0; + /* acc3 += x[3] * y[0] */ + acc3 += x3 * c0; + + /* Read y[1] sample */ + c0 = *(py++); + /* Read x[4] sample */ + x0 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[1] */ + acc0 += x1 * c0; + /* acc1 += x[2] * y[1] */ + acc1 += x2 * c0; + /* acc2 += x[3] * y[1] */ + acc2 += x3 * c0; + /* acc3 += x[4] * y[1] */ + acc3 += x0 * c0; + + /* Read y[2] sample */ + c0 = *(py++); + /* Read x[5] sample */ + x1 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[2] */ + acc0 += x2 * c0; + /* acc1 += x[3] * y[2] */ + acc1 += x3 * c0; + /* acc2 += x[4] * y[2] */ + acc2 += x0 * c0; + /* acc3 += x[5] * y[2] */ + acc3 += x1 * c0; + + /* Read y[3] sample */ + c0 = *(py++); + /* Read x[6] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[3] * y[3] */ + acc0 += x3 * c0; + /* acc1 += x[4] * y[3] */ + acc1 += x0 * c0; + /* acc2 += x[5] * y[3] */ + acc2 += x1 * c0; + /* acc3 += x[6] * y[3] */ + acc3 += x2 * c0; + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *(py++); + /* Read x[7] sample */ + x3 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[4] * y[4] */ + acc0 += x0 * c0; + /* acc1 += x[5] * y[4] */ + acc1 += x1 * c0; + /* acc2 += x[6] * y[4] */ + acc2 += x2 * c0; + /* acc3 += x[7] * y[4] */ + acc3 += x3 * c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + +#endif /* #if defined(ARM_MATH_NEON) */ + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = acc0; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = acc1; + pOut += inc; + + *pOut = acc2; + pOut += inc; + + *pOut = acc3; + pOut += inc; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + +#if defined(ARM_MATH_NEON) + float32x4_t x,y; + float32x4_t res = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0); + + while (k > 0U) + { + x = vld1q_f32(px); + y = vld1q_f32(py); + + res = vmlaq_f32(res,x, y); + + px += 4; + py += 4; + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; +#else + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + sum += *px++ * *py++; + sum += *px++ * *py++; + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } +#endif /* #if defined(ARM_MATH_NEON) */ + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + + /* Loop over srcBLen */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + +#if defined(ARM_MATH_NEON) + float32x4_t x,y; + float32x4_t res = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0); + + while (k > 0U) + { + x = vld1q_f32(px); + y = vld1q_f32(py); + + res = vmlaq_f32(res,x, y); + + px += 4; + py += 4; + + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; +#else + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum += *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + sum += *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum += *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + +#endif /* #if defined (ARM_MATH_NEON) */ + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const float32_t *pIn1 = pSrcA; /* inputA pointer */ + const float32_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + float32_t sum; /* Accumulator */ + uint32_t i = 0U, j; /* Loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and a varaible, inv is set to 1 */ + /* If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we assume zeroes + * in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer */ + /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer */ + /* Once the zero padding is done the remaining of the output is calcualted + * using convolution but with the shorter signal time shifted. */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0.0f; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) + { + /* z[i] += x[i-j] * y[j] */ + sum += pIn1[j] * pIn2[-((int32_t) i - (int32_t) j)]; + } + } + + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = sum; + else + *pDst++ = sum; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Corr group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f64.c new file mode 100644 index 00000000..95edd40f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f64.c @@ -0,0 +1,365 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_f64.c + * Description: Correlation of floating-point sequences + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of floating-point sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ + +void arm_correlate_f64( + const float64_t * pSrcA, + uint32_t srcALen, + const float64_t * pSrcB, + uint32_t srcBLen, + float64_t * pDst) +{ + const float64_t *pIn1; /* InputA pointer */ + const float64_t *pIn2; /* InputB pointer */ + float64_t *pOut = pDst; /* Output pointer */ + const float64_t *px; /* Intermediate inputA pointer */ + const float64_t *py; /* Intermediate inputB pointer */ + const float64_t *pSrc1; + float64_t sum; + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; /* Loop counter */ + int32_t inc = 1; /* Destination address modifier */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we assume zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding has to be done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.; + + /* Initialize k with number of samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.; + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.; + + /* Loop over srcBLen */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.; + + /* Initialize blkCnt with number of samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } +} + +/** + @} end of Corr group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c new file mode 100644 index 00000000..0b37b187 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c @@ -0,0 +1,345 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_fast_opt_q15.c + * Description: Fast Q15 Correlation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a + maximum of min(srcALen, srcBLen) number of additions is carried internally. + The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result. + + @remark + Refer to \ref arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. + */ + +void arm_correlate_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch) +{ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q31_t acc0; /* Accumulators */ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch; /* Temporary pointer for scratch */ + const q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, blkCnt, outBlockSize; /* Loop counter */ + int32_t inc = 1; /* Destination address modifier */ + uint32_t tapCnt; /* Loop count */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q31_t x1, x2, x3; /* Temporary variables for holding input and coefficient values */ + q31_t y1, y2; /* State variables */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + pScr1 = pScratch; + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pIn2; + + + /* Actual correlation process starts here */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLAD(x2, y2, acc0); + acc2 = __SMLAD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + acc1 = __SMLADX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLADX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ + *pOut = (__SSAT(acc0 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc1 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc2 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc3 >> 15U, 16)); + pOut += inc; + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (srcALen + srcBLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate correlation for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch buffer */ + acc0 += (*pScr1++ * *pIn2++); + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + ** Then store the output in the destination buffer. */ + *pOut = (q15_t) (__SSAT((acc0 >> 15), 16)); + pOut += inc; + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch += 1U; + } + +} + +/** + @} end of Corr group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c new file mode 100644 index 00000000..7d8857ad --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c @@ -0,0 +1,614 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_fast_q15.c + * Description: Fast Q15 Correlation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a + maximum of min(srcALen, srcBLen) number of additions is carried internally. + The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result. + + @remark + Refer to \ref arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. + */ + +void arm_correlate_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables for holding input and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; /* Destination address modifier */ + + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first loop starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */ + sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */ + sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* x[0] * y[srcBLen - 1] */ + sum = __SMLAD(*px++, *py++, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (sum >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* -------------------- + * Stage2 process + * -------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unroll over blockSize2, by 4 */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the first two inputB samples using SIMD: + * y[0] and y[1] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* acc0 += x[0] * y[0] + x[1] * y[1] */ + acc0 = __SMLAD(x0, c0, acc0); + + /* acc1 += x[1] * y[0] + x[2] * y[1] */ + acc1 = __SMLAD(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[0] + x[3] * y[1] */ + acc2 = __SMLAD(x2, c0, acc2); + + /* acc3 += x[3] * y[0] + x[4] * y[1] */ + acc3 = __SMLAD(x3, c0, acc3); + + /* Read y[2] and y[3] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* acc0 += x[2] * y[2] + x[3] * y[3] */ + acc0 = __SMLAD(x2, c0, acc0); + + /* acc1 += x[3] * y[2] + x[4] * y[3] */ + acc1 = __SMLAD(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[2] + x[5] * y[3] */ + acc2 = __SMLAD(x0, c0, acc2); + + /* acc3 += x[5] * y[2] + x[6] * y[3] */ + acc3 = __SMLAD(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + * So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[4] */ + c0 = *py; + +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD (x0, c0, acc0); + acc1 = __SMLAD (x1, c0, acc1); + acc2 = __SMLADX(x1, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[4], y[5] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + acc2 = __SMLAD(x3, c0, acc2); + acc3 = __SMLAD(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[4], y[5] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + acc2 = __SMLAD(x3, c0, acc2); + acc3 = __SMLAD(x2, c0, acc3); + + c0 = (*py); + /* Read y[6] */ +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x1, c0, acc0); + acc1 = __SMLAD (x2, c0, acc1); + acc2 = __SMLADX(x2, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (acc0 >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q15_t) (acc1 >> 15); + pOut += inc; + + *pOut = (q15_t) (acc2 >> 15); + pOut += inc; + + *pOut = (q15_t) (acc3 >> 15); + pOut += inc; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py++); + sum += ((q31_t) *px++ * *py++); + sum += ((q31_t) *px++ * *py++); + sum += ((q31_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) * px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (sum >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (sum >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */ + sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */ + sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py++, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (sum >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement the MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + +} + +/** + @} end of Corr group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c new file mode 100644 index 00000000..e3d2bbf8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c @@ -0,0 +1,601 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_fast_q31.c + * Description: Fast Q31 Correlation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are accumulated in a 32-bit register in 2.30 format. + Finally, the accumulator is saturated and converted to a 1.31 result. + @par + The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signals must be scaled down. + The input signals should be scaled down to avoid intermediate overflows. + Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a + maximum of min(srcALen, srcBLen) number of additions is carried internally. + + @remark + Refer to \ref arm_correlate_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. + */ + +void arm_correlate_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1; /* Intermediate pointers */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables for holding input and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; /* Destination address modifier */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* x[1] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* x[2] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* x[3] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum << 1; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unroll over blockSize2, by 4 */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[0] sample */ + c0 = *py++; + /* Read x[3] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[0] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[1] * y[0] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[2] * y[0] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[3] * y[0] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + + /* Read y[1] sample */ + c0 = *py++; + /* Read x[4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[1] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc1 += x[2] * y[1] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc2 += x[3] * y[1] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc3 += x[4] * y[1] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32); + + + /* Read y[2] sample */ + c0 = *py++; + /* Read x[5] sample */ + x1 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[2] * y[2] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc1 += x[3] * y[2] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc2 += x[4] * y[2] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc3 += x[5] * y[2] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32); + + + /* Read y[3] sample */ + c0 = *py++; + /* Read x[6] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[3] * y[3] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc1 += x[4] * y[3] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc2 += x[5] * y[3] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc3 += x[6] * y[3] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32); + + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *py++; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[4] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[5] * y[4] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[6] * y[4] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[7] * y[4] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (acc0 << 1); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q31_t) (acc1 << 1); + pOut += inc; + + *pOut = (q31_t) (acc2 << 1); + pOut += inc; + + *pOut = (q31_t) (acc3 << 1); + pOut += inc; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum << 1; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum << 1; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = ((pIn1 + srcALen) - srcBLen) + 1U; + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum << 1; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + } + +} + +/** + @} end of Corr group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c new file mode 100644 index 00000000..00bb0889 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c @@ -0,0 +1,341 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_opt_q15.c + * Description: Correlation of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both inputs are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + + @remark + Refer to \ref arm_correlate_fast_q15() for a faster but less precise version of this function. + */ + +void arm_correlate_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch) +{ + q63_t acc0; /* Accumulators */ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1; /* Temporary pointer for scratch1 */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, blkCnt, outBlockSize; /* Loop counter */ + int32_t inc = 1; /* Output pointer increment */ + uint32_t tapCnt; + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc1, acc2, acc3; /* Accumulators */ + q31_t x1, x2, x3; /* Temporary variables for holding input1 and input2 values */ + q31_t y1, y2; /* State variables */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (srcALen * 2U) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + pScr1 = pScratch; + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pIn2; + + + /* Actual correlation process starts here */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLALD(x1, y1, acc0); + acc2 = __SMLALD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLALDX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLALD(x2, y2, acc0); + acc2 = __SMLALD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLALDX(x3, y1, acc3); + acc1 = __SMLALDX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLALDX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + + /* Store the results in the accumulators in the destination buffer. */ + *pOut = (__SSAT(acc0 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc1 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc2 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc3 >> 15U, 16)); + pOut += inc; + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch += 4U; + } + + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (srcALen + srcBLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate correlation for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch1 buffer */ + acc0 += (*pScr1++ * *pIn2++); + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pOut = (q15_t) (__SSAT((acc0 >> 15), 16)); + pOut += inc; + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch += 1U; + } + +} + +/** + @} end of Corr group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c new file mode 100644 index 00000000..145ba2ae --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c @@ -0,0 +1,388 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_opt_q7.c + * Description: Correlation of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. + The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format. + */ + +void arm_correlate_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch */ + q15_t x4; /* Temporary input variable */ + q15_t *py; /* Temporary input2 pointer */ + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + const q7_t *pIn1, *pIn2; /* InputA and inputB pointer */ + uint32_t j, k, blkCnt, tapCnt; /* Loop counter */ + int32_t inc = 1; /* Output pointer increment */ + uint32_t outBlockSize; /* Loop counter */ + q31_t x1, x2, x3, y1; /* Temporary input variables */ + q7_t *pOut = pDst; /* Output pointer */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (srcALen * 2U) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + + /* Copy (srcBLen) samples in scratch buffer */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy (srcALen) samples in scratch buffer */ + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcALen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + No loop unrolling is used. */ + k = srcALen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) * pIn1++; + *pScr1++ = x4; + + /* Decrement the loop counter */ + k--; + } + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* Initialization of pScr2 pointer */ + pScr2 = pScratch2; + + /* Actual correlation process starts here */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + acc0 = __SMLAD(x2, y1, acc0); + + acc2 = __SMLAD(x1, y1, acc2); + + acc1 = __SMLADX(x3, y1, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2); + acc1 += (*pScr1++ * *pScr2); + acc2 += (*pScr1++ * *pScr2); + acc3 += (*pScr1++ * *pScr2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(acc0 >> 7U, 8)); + pOut += inc; + *pOut = (q7_t) (__SSAT(acc1 >> 7U, 8)); + pOut += inc; + *pOut = (q7_t) (__SSAT(acc2 >> 7U, 8)); + pOut += inc; + *pOut = (q7_t) (__SSAT(acc3 >> 7U, 8)); + pOut += inc; + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 4U; + } + + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + + /* Calculate correlation for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + acc0 += (*pScr1++ * *pScr2++); + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(acc0 >> 7U, 8)); + pOut += inc; + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 1U; + } + +} + +/** + @} end of Corr group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c new file mode 100644 index 00000000..2dd16d72 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c @@ -0,0 +1,903 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_q15.c + * Description: Correlation of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both inputs are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + + @remark + Refer to \ref arm_correlate_fast_q15() for a faster but less precise version of this function. + @remark + Refer to \ref arm_correlate_opt_q15() for a faster implementation of this function using scratch buffers. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_helium_utils.h" +#include "arm_vec_filtering.h" + +void arm_correlate_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + const q15_t *pIn1 = pSrcA; /* inputA pointer */ + const q15_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + /* + * Loop to perform MAC operations according to correlation equation + */ + const q15_t *pX; + const q15_t *pY; + const q15_t *pA; + const q15_t *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t inv = 2U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + int32_t block1, block2, block3; + int32_t incr; + + tot = ((srcALen + srcBLen) - 2U); + if (srcALen > srcBLen) + { + /* + * Calculating the number of zeros to be padded to the output + */ + j = srcALen - srcBLen; + /* + * Initialize the pointer after zero padding + */ + pDst += j; + } + else if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA + (srcALen - 1U); + /* + * Initialisation of the pointer after zero padding + */ + pDst = pDst + tot; + /* + * Swapping the lengths + */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + /* + * Setting the reverse flag + */ + inv = -2; + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2; + incr = inv / 2; + + for (i = 0U; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + /* + * compute 2 accumulators per loop + * size is incrementing for second accumulator + * Y pointer is decrementing for second accumulator + */ + pX = pA; + pY = pB; + MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_Q15(acc0, acc1, pX, pY, count); + + *pDst = (q15_t) acc0; + pDst += incr; + *pDst = (q15_t) acc1; + pDst += incr; + pB -= 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q15(acc, pX, pY, count); + + *pDst = (q15_t) acc; + pDst += incr; + pB--; + } + + for (i = 0U; i <= block2 - 4; i += 4) + { + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + int64_t acc2 = 0LL; + int64_t acc3 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 4 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_Q15(acc0, acc1, acc2, acc3, pX, pY, srcBLen); + + *pDst = (q15_t) acc0; + pDst += incr; + *pDst = (q15_t) acc1; + pDst += incr; + *pDst = (q15_t) acc2; + pDst += incr; + *pDst = (q15_t) acc3; + pDst += incr; + pA += 4; + } + + for (; i <= block2 - 2; i += 2) + { + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_Q15(acc0, acc1, pX, pY, srcBLen); + + *pDst = (q15_t) acc0; + pDst += incr; + *pDst = (q15_t) acc1; + pDst += incr; + pA += 2; + } + + if (block2 & 1) + { + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q15(acc, pX, pY, srcBLen); + + *pDst = (q15_t) acc; + pDst += incr; + pA++; + } + + for (i = block3 - 1; i >= 0; i -= 2) + { + + uint32_t count = (i + 1); + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is decrementing for second accumulator + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_Q15(acc0, acc1, pX, pY, count); + + *pDst = (q15_t) acc0; + pDst += incr; + *pDst = (q15_t) acc1; + pDst += incr; + pA += 2; + + } + for (; i >= 0; i--) + { + uint32_t count = (i + 1); + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q15(acc, pX, pY, count); + + *pDst = (q15_t) acc; + pDst += incr; + pA++; + } +} + +#else +void arm_correlate_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + +#if defined (ARM_MATH_DSP) + + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q63_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary input variables for holding input and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; /* Destination address modifier */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (srcALen * 2U) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first loop starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */ + sum = __SMLALD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */ + sum = __SMLALD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum = __SMLALD(*px++, *py++, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT((sum >> 15), 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the first two inputB samples using SIMD: + * y[0] and y[1] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* acc0 += x[0] * y[0] + x[1] * y[1] */ + acc0 = __SMLALD(x0, c0, acc0); + + /* acc1 += x[1] * y[0] + x[2] * y[1] */ + acc1 = __SMLALD(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[0] + x[3] * y[1] */ + acc2 = __SMLALD(x2, c0, acc2); + + /* acc3 += x[3] * y[0] + x[4] * y[1] */ + acc3 = __SMLALD(x3, c0, acc3); + + /* Read y[2] and y[3] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* acc0 += x[2] * y[2] + x[3] * y[3] */ + acc0 = __SMLALD(x2, c0, acc0); + + /* acc1 += x[3] * y[2] + x[4] * y[3] */ + acc1 = __SMLALD(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[2] + x[5] * y[3] */ + acc2 = __SMLALD(x0, c0, acc2); + + /* acc3 += x[5] * y[2] + x[6] * y[3] */ + acc3 = __SMLALD(x1, c0, acc3); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[4] */ + c0 = *py; +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD (x0, c0, acc0); + acc1 = __SMLALD (x1, c0, acc1); + acc2 = __SMLALDX(x1, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[4], y[5] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + acc2 = __SMLALD(x3, c0, acc2); + acc3 = __SMLALD(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[4], y[5] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + acc2 = __SMLALD(x3, c0, acc2); + acc3 = __SMLALD(x2, c0, acc3); + + c0 = (*py); + + /* Read y[6] */ +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLALDX(x1, c0, acc0); + acc1 = __SMLALD (x2, c0, acc1); + acc2 = __SMLALDX(x2, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT(acc0 >> 15, 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q15_t) (__SSAT(acc1 >> 15, 16)); + pOut += inc; + + *pOut = (q15_t) (__SSAT(acc2 >> 15, 16)); + pOut += inc; + + *pOut = (q15_t) (__SSAT(acc3 >> 15, 16)); + pOut += inc; + + /* Increment the count by 4 as 4 output values are computed */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q63_t) *px++ * *py++); + sum += ((q63_t) *px++ * *py++); + sum += ((q63_t) *px++ * *py++); + sum += ((q63_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q63_t) *px++ * *py++); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT(sum >> 15, 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment count by 1, as one output value is computed */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q63_t) *px++ * *py++); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT(sum >> 15, 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */ + sum = __SMLALD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */ + sum = __SMLALD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = __SMLALD(*px++, *py++, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT((sum >> 15), 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + } + +#else /* #if defined (ARM_MATH_DSP) */ + + const q15_t *pIn1 = pSrcA; /* InputA pointer */ + const q15_t *pIn2 = pSrcB + (srcBLen - 1U); /* InputB pointer */ + q63_t sum; /* Accumulators */ + uint32_t i = 0U, j; /* Loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and a varaible, inv is set to 1 */ + /* If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we include zeroes + * in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer */ + /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer */ + /* Once the zero padding is done the remaining of the output is calcualted + * using convolution but with the shorter signal time shifted. */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + } + + /* Loop to calculate convolution for output length number of values */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - (int32_t) j)]); + } + } + + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q15_t) __SSAT((sum >> 15U), 16U); + else + *pDst++ = (q15_t) __SSAT((sum >> 15U), 16U); + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Corr group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c new file mode 100644 index 00000000..a5f15fec --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c @@ -0,0 +1,879 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_q31.c + * Description: Correlation of Q31 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q31 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a + maximum of min(srcALen, srcBLen) number of additions is carried internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + + @remark + Refer to \ref arm_correlate_fast_q31() for a faster but less precise implementation of this function. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_helium_utils.h" +#include "arm_vec_filtering.h" +void arm_correlate_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + const q31_t *pIn1 = pSrcA; /* inputA pointer */ + const q31_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + /* + * Loop to perform MAC operations according to correlation equation + */ + const q31_t *pX; + const q31_t *pY; + const q31_t *pA; + const q31_t *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t inv = 4; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + int32_t block1, block2, block3; + int32_t incr; + + tot = ((srcALen + srcBLen) - 2U); + if (srcALen > srcBLen) + { + /* + * Calculating the number of zeros to be padded to the output + */ + j = srcALen - srcBLen; + /* + * Initialize the pointer after zero padding + */ + pDst += j; + } + else if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA + (srcALen - 1U); + /* + * Initialization of the pointer after zero padding + */ + pDst = pDst + tot; + /* + * Swapping the lengths + */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + /* + * Setting the reverse flag + */ + inv = -4; + + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + pA = pIn1; + pB = pIn2; + incr = inv / 4; + + for (i = 0U; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + /* compute 2 accumulators per loop */ + /* size is incrementing for second accumulator */ + /* Y pointer is decrementing for second accumulator */ + pX = pA; + pY = pB; + MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_Q31(acc0, acc1, pX, pY, count); + + *pDst = (q31_t) acc0; + pDst += incr; + *pDst = (q31_t) acc1; + pDst += incr; + pB -= 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q31(acc, pX, pY, count); + + *pDst = (q31_t) acc; + pDst += incr; + pB--; + } + + for (i = 0U; i <= block2 - 4; i += 4) + { + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + int64_t acc2 = 0LL; + int64_t acc3 = 0LL; + + pX = pA; + pY = pB; + /* compute 4 accumulators per loop */ + /* size is fixed for all accumulators */ + /* X pointer is incrementing for successive accumulators */ + MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_Q31(acc0, acc1, acc2, acc3, pX, pY, srcBLen); + + *pDst = (q31_t) acc0; + pDst += incr; + *pDst = (q31_t) acc1; + pDst += incr; + *pDst = (q31_t) acc2; + pDst += incr; + *pDst = (q31_t) acc3; + pDst += incr; + pA += 4; + } + + for (; i <= block2 - 2; i += 2) + { + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* compute 2 accumulators per loop */ + /* size is fixed for all accumulators */ + /* X pointer is incrementing for second accumulator */ + MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_Q31(acc0, acc1, pX, pY, srcBLen); + + *pDst = (q31_t) acc0; + pDst += incr; + *pDst = (q31_t) acc1; + pDst += incr; + pA += 2; + } + + if (block2 & 1) + { + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q31(acc, pX, pY, srcBLen); + + *pDst = (q31_t) acc; + pDst += incr; + pA++; + } + + for (i = block3 - 1; i >= 0; i -= 2) + { + + uint32_t count = (i + 1); + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* compute 2 accumulators per loop */ + /* size is decrementing for second accumulator */ + /* X pointer is incrementing for second accumulator */ + MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_Q31(acc0, acc1, pX, pY, count); + + *pDst = (q31_t) acc0; + pDst += incr; + *pDst = (q31_t) acc1; + pDst += incr; + pA += 2; + + } + for (; i >= 0; i--) + { + uint32_t count = (i + 1); + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q31(acc, pX, pY, count); + + *pDst = (q31_t) acc; + pDst += incr; + pA++; + } +} +#else +void arm_correlate_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1; /* Intermediate pointers */ + q63_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; /* Destination address modifier */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2; /* Accumulators */ + q31_t x0, x1, x2, c0; /* Temporary variables for holding input and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * (*py++); + + /* x[1] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * (*py++); + + /* x[2] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * (*py++); + + /* x[3] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * (*py++); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * (*py++); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (sum >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unroll by 3 */ + blkCnt = blockSize2 / 3; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + + /* read x[0], x[1] samples */ + x0 = *px++; + x1 = *px++; + + /* Apply loop unrolling and compute 3 MACs simultaneously. */ + k = srcBLen / 3; + + /* First part of the processing with loop unrolling. Compute 3 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 2 samples. */ + do + { + /* Read y[0] sample */ + c0 = *(py); + /* Read x[2] sample */ + x2 = *(px); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[0] */ + acc0 += ((q63_t) x0 * c0); + /* acc1 += x[1] * y[0] */ + acc1 += ((q63_t) x1 * c0); + /* acc2 += x[2] * y[0] */ + acc2 += ((q63_t) x2 * c0); + + /* Read y[1] sample */ + c0 = *(py + 1U); + /* Read x[3] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[1] */ + acc0 += ((q63_t) x1 * c0); + /* acc1 += x[2] * y[1] */ + acc1 += ((q63_t) x2 * c0); + /* acc2 += x[3] * y[1] */ + acc2 += ((q63_t) x0 * c0); + + /* Read y[2] sample */ + c0 = *(py + 2U); + /* Read x[4] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[2] */ + acc0 += ((q63_t) x2 * c0); + /* acc1 += x[3] * y[2] */ + acc1 += ((q63_t) x0 * c0); + /* acc2 += x[4] * y[2] */ + acc2 += ((q63_t) x1 * c0); + + /* update scratch pointers */ + px += 3U; + py += 3U; + + } while (--k); + + /* If the srcBLen is not a multiple of 3, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen - (3 * (srcBLen / 3)); + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *(py++); + + /* Read x[7] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[4] */ + acc0 += ((q63_t) x0 * c0); + /* acc1 += x[5] * y[4] */ + acc1 += ((q63_t) x1 * c0); + /* acc2 += x[6] * y[4] */ + acc2 += ((q63_t) x2 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (acc0 >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q31_t) (acc1 >> 31); + pOut += inc; + + *pOut = (q31_t) (acc2 >> 31); + pOut += inc; + + /* Increment the pointer pIn1 index, count by 3 */ + count += 3U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 - 3 * (blockSize2 / 3); + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) *px++ * *py++; + sum += (q63_t) *px++ * *py++; + sum += (q63_t) *px++ * *py++; + sum += (q63_t) *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (sum >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (sum >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum += (q63_t) *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + sum += (q63_t) *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum += (q63_t) *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + sum += (q63_t) *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (sum >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const q31_t *pIn1 = pSrcA; /* InputA pointer */ + const q31_t *pIn2 = pSrcB + (srcBLen - 1U); /* InputB pointer */ + q63_t sum; /* Accumulators */ + uint32_t i = 0U, j; /* Loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and a varaible, inv is set to 1 */ + /* If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we include zeroes + * in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer */ + /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer */ + /* Once the zero padding is done the remaining of the output is calcualted + * using correlation but with the shorter signal time shifted. */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + } + + /* Loop to calculate correlation for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to correlation equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q63_t) pIn1[j] * pIn2[-((int32_t) i - (int32_t) j)]); + } + } + + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q31_t) (sum >> 31U); + else + *pDst++ = (q31_t) (sum >> 31U); + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Corr group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c new file mode 100644 index 00000000..0b924e82 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c @@ -0,0 +1,1002 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_q7.c + * Description: Correlation of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. + The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format. + + @remark + Refer to \ref arm_correlate_opt_q7() for a faster implementation of this function. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_helium_utils.h" + +#include "arm_vec_filtering.h" +void arm_correlate_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst) +{ + const q7_t *pIn1 = pSrcA; /* inputA pointer */ + const q7_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + const q7_t *pX, *pY; + const q7_t *pA, *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t inv = 1U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + int32_t block1, block2, block3; + int32_t incr; + + tot = ((srcALen + srcBLen) - 2U); + if (srcALen > srcBLen) + { + /* + * Calculating the number of zeros to be padded to the output + */ + j = srcALen - srcBLen; + /* + * Initialize the pointer after zero padding + */ + pDst += j; + } + else if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA + (srcALen - 1U); + /* + * Initialisation of the pointer after zero padding + */ + pDst = pDst + tot; + /* + * Swapping the lengths + */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + /* + * Setting the reverse flag + */ + inv = -1; + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2; + incr = inv; + + for (i = 0U; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + int32_t acc0 = 0; + int32_t acc1 = 0; + + /* + * compute 2 accumulators per loop + * size is incrementing for second accumulator + * Y pointer is decrementing for second accumulator + */ + pX = pA; + pY = pB; + MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_Q7(acc0, acc1, pX, pY, count); + + *pDst = (q7_t) acc0; + pDst += incr; + *pDst = (q7_t) acc1; + pDst += incr; + pB -= 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + int32_t acc = 0; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q7(acc, pX, pY, count); + + *pDst = (q7_t) acc; + pDst += incr; + pB--; + } + + for (i = 0U; i <= block2 - 4; i += 4) + { + int32_t acc0 = 0; + int32_t acc1 = 0; + int32_t acc2 = 0; + int32_t acc3 = 0; + + pX = pA; + pY = pB; + /* + * compute 4 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_Q7(acc0, acc1, acc2, acc3, pX, pY, srcBLen); + + *pDst = (q7_t) acc0; + pDst += incr; + *pDst = (q7_t) acc1; + pDst += incr; + *pDst = (q7_t) acc2; + pDst += incr; + *pDst = (q7_t) acc3; + pDst += incr; + + pA += 4; + } + + for (; i <= block2 - 2; i += 2) + { + int32_t acc0 = 0LL; + int32_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_Q7(acc0, acc1, pX, pY, srcBLen); + + *pDst = (q7_t) acc0; + pDst += incr; + *pDst = (q7_t) acc1; + pDst += incr; + pA += 2; + } + + if (block2 & 1) + { + int32_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q7(acc, pX, pY, srcBLen); + + *pDst = (q7_t) acc; + pDst += incr; + pA++; + } + + for (i = block3 - 1; i >= 0; i -= 2) + { + uint32_t count = (i + 1); + int32_t acc0 = 0LL; + int32_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is decrementing for second accumulator + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_Q7(acc0, acc1, pX, pY, count); + + *pDst = (q7_t) acc0; + pDst += incr; + *pDst = (q7_t) acc1; + pDst += incr; + pA += 2; + + } + for (; i >= 0; i--) + { + uint32_t count = (i + 1); + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q7(acc, pX, pY, count); + + *pDst = (q7_t) acc; + pDst += incr; + pA++; + } +} + +#else +void arm_correlate_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst) +{ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + const q7_t *pIn1; /* InputA pointer */ + const q7_t *pIn2; /* InputB pointer */ + q7_t *pOut = pDst; /* Output pointer */ + const q7_t *px; /* Intermediate inputA pointer */ + const q7_t *py; /* Intermediate inputB pointer */ + const q7_t *pSrc1; /* Intermediate pointers */ + q31_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t input1, input2; /* Temporary input variables */ + q15_t in1, in2; /* Temporary input variables */ + q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables for holding input and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] , x[1] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 4] , y[srcBLen - 3] */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* x[0] * y[srcBLen - 4] */ + /* x[1] * y[srcBLen - 3] */ + sum = __SMLAD(input1, input2, sum); + + /* x[2] , x[3] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 2] , y[srcBLen - 1] */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* x[2] * y[srcBLen - 2] */ + /* x[3] * y[srcBLen - 1] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum += (q31_t) ((q15_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(sum >> 7U, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[0] sample */ + c0 = *py++; + /* Read y[1] sample */ + c1 = *py++; + + /* Read x[3] sample */ + x3 = *px++; + + /* x[0] and x[1] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[0] and y[1] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc0 += x[0] * y[0] + x[1] * y[1] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[1] and x[2] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc1 += x[1] * y[0] + x[2] * y[1] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc2 += x[2] * y[0] + x[3] * y[1] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[4] sample */ + x0 = *px++; + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc3 += x[3] * y[0] + x[4] * y[1] */ + acc3 = __SMLAD(input1, input2, acc3); + + /* Read y[2] sample */ + c0 = *py++; + /* Read y[3] sample */ + c1 = *py++; + + /* Read x[5] sample */ + x1 = *px++; + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[2] and y[3] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc0 += x[2] * y[2] + x[3] * y[3] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc1 += x[3] * y[2] + x[4] * y[3] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[4] and x[5] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc2 += x[4] * y[2] + x[5] * y[3] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[6] sample */ + x2 = *px++; + + /* x[5] and x[6] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc3 += x[5] * y[2] + x[6] * y[3] */ + acc3 = __SMLAD(input1, input2, acc3); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *py++; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[4] */ + acc0 += ((q15_t) x0 * c0); + /* acc1 += x[5] * y[4] */ + acc1 += ((q15_t) x1 * c0); + /* acc2 += x[6] * y[4] */ + acc2 += ((q15_t) x2 * c0); + /* acc3 += x[7] * y[4] */ + acc3 += ((q15_t) x3 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(acc0 >> 7, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q7_t) (__SSAT(acc1 >> 7, 8)); + pOut += inc; + + *pOut = (q7_t) (__SSAT(acc2 >> 7, 8)); + pOut += inc; + + *pOut = (q7_t) (__SSAT(acc3 >> 7, 8)); + pOut += inc; + + count += 4U; + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py++); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(sum >> 7U, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py++); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(sum >> 7U, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[srcALen - srcBLen + 1] , x[srcALen - srcBLen + 2] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[0] , y[1] */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum = __SMLAD(input1, input2, sum); + + /* x[srcALen - srcBLen + 3] , x[srcALen - srcBLen + 4] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[2] , y[3] */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(sum >> 7U, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const q7_t *pIn1 = pSrcA; /* InputA pointer */ + const q7_t *pIn2 = pSrcB + (srcBLen - 1U); /* InputB pointer */ + q31_t sum; /* Accumulator */ + uint32_t i = 0U, j; /* Loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and a varaible, inv is set to 1 */ + /* If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we include zeroes + * in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer */ + /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer */ + /* Once the zero padding is done the remaining of the output is calcualted + * using convolution but with the shorter signal time shifted. */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q15_t) pIn1[j] * pIn2[-((int32_t) i - (int32_t) j)]); + } + } + + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q7_t) __SSAT((sum >> 7U), 8U); + else + *pDst++ = (q7_t) __SSAT((sum >> 7U), 8U); + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Corr group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c new file mode 100644 index 00000000..443efa02 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c @@ -0,0 +1,951 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_f32.c + * Description: FIR decimation for floating-point sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup FIR_decimate Finite Impulse Response (FIR) Decimator + + These functions combine an FIR filter together with a decimator. + They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion. + Conceptually, the functions are equivalent to the block diagram below: + \image html FIRDecimator.gif "Components included in the FIR Decimator functions" + When decimating by a factor of M, the signal should be prefiltered by a lowpass filter with a normalized + cutoff frequency of 1/M in order to prevent aliasing distortion. + The user of the function is responsible for providing the filter coefficients. + + The FIR decimator functions provided in the CMSIS DSP Library combine the FIR filter and the decimator in an efficient manner. + Instead of calculating all of the FIR filter outputs and discarding M-1 out of every M, only the + samples output by the decimator are computed. + The functions operate on blocks of input and output data. + pSrc points to an array of blockSize input values and + pDst points to an array of blockSize/M output values. + In order to have an integer number of output samples blockSize + must always be a multiple of the decimation factor M. + + The library provides separate functions for Q15, Q31 and floating-point data types. + + @par Algorithm: + The FIR portion of the algorithm uses the standard form filter: +
+      y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+  
+ where, b[n] are the filter coefficients. + @par + The pCoeffs points to a coefficient array of size numTaps. + Coefficients are stored in time reversed order. + @par +
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+  
+ @par + pState points to a state array of size numTaps + blockSize - 1. + Samples in the state buffer are stored in the order: + @par +
+      {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+  
+ The state variables are updated after each block of data is processed, the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable array should be allocated separately. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + - Checks to make sure that the size of the input is a multiple of the decimation factor. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, M (decimation factor), pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + The code below statically initializes each of the 3 different data type filter instance structures +
+      arm_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};
+      arm_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};
+      arm_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};
+  
+ where M is the decimation factor; numTaps is the number of filter coefficients in the filter; + pCoeffs is the address of the coefficient buffer; + pState is the address of the state buffer. + Be sure to set the values in the state buffer to zeros when doing static initialization. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the FIR decimate filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for floating-point FIR decimator. + @param[in] S points to an instance of the floating-point FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + const float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + uint32_t blkCntN4; + const float32_t *px0, *px1, *px2, *px3; + f32x4_t accv, acc0v, acc1v, acc2v, acc3v; + f32x4_t x0v, x1v, x2v, x3v; + f32x4_t c0v; + + /* + * S->pState buffer contains previous frame (numTaps - 1) samples + * pStateCurnt points to the location where the new input data should be written + */ + pStateCurnt = S->pState + (numTaps - 1U); + /* + * Total number of output samples to be computed + */ + blkCnt = outBlockSize / 4; + blkCntN4 = outBlockSize - (4 * blkCnt); + + while (blkCnt > 0U) + { + /* + * Copy 4 * decimation factor number of new input samples into the state buffer + */ + i = (4 * S->M) >> 2; + do + { + vst1q(pStateCurnt, vld1q((const float32_t *)pSrc)); + pSrc += 4; + pStateCurnt += 4; + i--; + } + while (i > 0U); + + /* + * Set accumulators to zero + */ + acc0v = vdupq_n_f32(0.0f); + acc1v = vdupq_n_f32(0.0f); + acc2v = vdupq_n_f32(0.0f); + acc3v = vdupq_n_f32(0.0f); + + /* + * Initialize state pointer for all the samples + */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + /* + * Initialize coeff pointer + */ + pb = pCoeffs; + /* + * Loop unrolling. Process 4 taps at a time. + */ + tapCnt = numTaps >> 2; + /* + * Loop over the number of taps. Unroll by a factor of 4. + * Repeat until we've computed numTaps-4 coefficients. + */ + while (tapCnt > 0U) + { + /* + * Read the b[numTaps-1] coefficient + */ + c0v = vld1q((const float32_t *)pb); + pb += 4; + /* + * Read x[n-numTaps-1] sample for acc0 + */ + x0v = vld1q(px0); + x1v = vld1q(px1); + x2v = vld1q(px2); + x3v = vld1q(px3); + px0 += 4; + px1 += 4; + px2 += 4; + px3 += 4; + + acc0v = vfmaq(acc0v, x0v, c0v); + acc1v = vfmaq(acc1v, x1v, c0v); + acc2v = vfmaq(acc2v, x2v, c0v); + acc3v = vfmaq(acc3v, x3v, c0v); + /* + * Decrement the loop counter + */ + tapCnt--; + } + + /* + * If the filter length is not a multiple of 4, compute the remaining filter taps + * should be tail predicated + */ + tapCnt = numTaps % 0x4U; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + /* + * Read the b[numTaps-1] coefficient + */ + c0v = vldrwq_z_f32(pb, p0); + pb += 4; + /* + * Read x[n-numTaps-1] sample for acc0 + */ + x0v = vld1q(px0); + x1v = vld1q(px1); + x2v = vld1q(px2); + x3v = vld1q(px3); + px0 += 4; + px1 += 4; + px2 += 4; + px3 += 4; + + acc0v = vfmaq_f32(acc0v, x0v, c0v); + acc1v = vfmaq_f32(acc1v, x1v, c0v); + acc2v = vfmaq_f32(acc2v, x2v, c0v); + acc3v = vfmaq_f32(acc3v, x3v, c0v); + } + + /* reduction */ + accv[0] = vecAddAcrossF32Mve(acc0v); + accv[1] = vecAddAcrossF32Mve(acc1v); + accv[2] = vecAddAcrossF32Mve(acc2v); + accv[3] = vecAddAcrossF32Mve(acc3v); + + /* + * Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples + */ + pState = pState + 4 * S->M; + /* + * The result is in the accumulator, store in the destination buffer. + */ + vst1q(pDst, accv); + pDst += 4; + + /* + * Decrement the loop counter + */ + blkCnt--; + } + + while (blkCntN4 > 0U) + { + /* + * Copy decimation factor number of new input samples into the state buffer + */ + i = S->M; + do + { + *pStateCurnt++ = *pSrc++; + } + while (--i); + /* + * Set accumulator to zero + */ + acc0v = vdupq_n_f32(0.0f); + /* + * Initialize state pointer + */ + px = pState; + /* + * Initialize coeff pointer + */ + pb = pCoeffs; + /* + * Loop unrolling. Process 4 taps at a time. + */ + tapCnt = numTaps >> 2; + /* + * Loop over the number of taps. Unroll by a factor of 4. + * Repeat until we've computed numTaps-4 coefficients. + */ + while (tapCnt > 0U) + { + c0v = vldrwq_f32(pb); + x0v = vldrwq_f32(px); + pb += 4; + px += 4; + acc0v = vfmaq_f32(acc0v, x0v, c0v); + /* + * Decrement the loop counter + */ + tapCnt--; + } + tapCnt = numTaps % 0x4U; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + c0v = vldrwq_z_f32(pb, p0); + x0v = vldrwq_f32(px); + acc0v = vfmaq_f32(acc0v, x0v, c0v); + } + accv[0] = vecAddAcrossF32Mve(acc0v); + + /* + * Advance the state pointer by the decimation factor + * * to process the next group of decimation factor number samples + */ + pState = pState + S->M; + /* + * The result is in the accumulator, store in the destination buffer. + */ + *pDst++ = accv[0]; + /* + * Decrement the loop counter + */ + blkCntN4--; + } + + /* + * Processing is complete. + * Now copy the last numTaps - 1 samples to the start of the state buffer. + * This prepares the state buffer for the next function call. + */ + + pStateCurnt = S->pState; + blkCnt =(numTaps - 1) >> 2; + while (blkCnt > 0U) + { + vst1q(pStateCurnt, vldrwq_f32(pState)); + pState += 4; + pStateCurnt += 4; + blkCnt--; + } + blkCnt = (numTaps - 1) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_f32(pStateCurnt, vldrwq_f32(pState), p0); + } +} +#else +#if defined(ARM_MATH_NEON) +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px; /* Temporary pointer for state buffer */ + const float32_t *pb; /* Temporary pointer for coefficient buffer */ + float32_t sum0; /* Accumulator */ + float32_t x0, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + + uint32_t blkCntN4; + float32_t *px0, *px1, *px2, *px3; + float32_t x1, x2, x3; + + float32x4_t accv,acc0v,acc1v,acc2v,acc3v; + float32x4_t x0v, x1v, x2v, x3v; + float32x4_t c0v; + float32x2_t temp; + float32x4_t sum0v; + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 4; + blkCntN4 = outBlockSize - (4 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 4 * decimation factor number of new input samples into the state buffer */ + i = 4 * S->M; + + do + { + *pStateCurnt++ = *pSrc++; + + } while (--i); + + /* Set accumulators to zero */ + acc0v = vdupq_n_f32(0.0); + acc1v = vdupq_n_f32(0.0); + acc2v = vdupq_n_f32(0.0); + acc3v = vdupq_n_f32(0.0); + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + /* Loop over the number of taps. + ** Repeat until we've computed numTaps-4 coefficients. */ + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0v = vld1q_f32(pb); + pb += 4; + + /* Read x[n-numTaps-1] sample for acc0 */ + x0v = vld1q_f32(px0); + x1v = vld1q_f32(px1); + x2v = vld1q_f32(px2); + x3v = vld1q_f32(px3); + + px0 += 4; + px1 += 4; + px2 += 4; + px3 += 4; + + acc0v = vmlaq_f32(acc0v, x0v, c0v); + acc1v = vmlaq_f32(acc1v, x1v, c0v); + acc2v = vmlaq_f32(acc2v, x2v, c0v); + acc3v = vmlaq_f32(acc3v, x3v, c0v); + + /* Decrement the loop counter */ + tapCnt--; + } + + temp = vpadd_f32(vget_low_f32(acc0v),vget_high_f32(acc0v)); + accv = vsetq_lane_f32(vget_lane_f32(temp, 0) + vget_lane_f32(temp, 1),accv,0); + + temp = vpadd_f32(vget_low_f32(acc1v),vget_high_f32(acc1v)); + accv = vsetq_lane_f32(vget_lane_f32(temp, 0) + vget_lane_f32(temp, 1),accv,1); + + temp = vpadd_f32(vget_low_f32(acc2v),vget_high_f32(acc2v)); + accv = vsetq_lane_f32(vget_lane_f32(temp, 0) + vget_lane_f32(temp, 1),accv,2); + + temp = vpadd_f32(vget_low_f32(acc3v),vget_high_f32(acc3v)); + accv = vsetq_lane_f32(vget_lane_f32(temp, 0) + vget_lane_f32(temp, 1),accv,3); + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch state variables for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + accv = vsetq_lane_f32(vgetq_lane_f32(accv, 0) + x0 * c0,accv,0); + accv = vsetq_lane_f32(vgetq_lane_f32(accv, 1) + x1 * c0,accv,1); + accv = vsetq_lane_f32(vgetq_lane_f32(accv, 2) + x2 * c0,accv,2); + accv = vsetq_lane_f32(vgetq_lane_f32(accv, 3) + x3 * c0,accv,3); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + 4 * S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + vst1q_f32(pDst,accv); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + while (blkCntN4 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCurnt++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0v = vdupq_n_f32(0.0); + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + /* Loop over the number of taps. + ** Repeat until we've computed numTaps-4 coefficients. */ + while (tapCnt > 0U) + { + c0v = vld1q_f32(pb); + pb += 4; + + x0v = vld1q_f32(px); + px += 4; + + sum0v = vmlaq_f32(sum0v, x0v, c0v); + + /* Decrement the loop counter */ + tapCnt--; + } + + temp = vpadd_f32(vget_low_f32(sum0v),vget_high_f32(sum0v)); + sum0 = vget_lane_f32(temp, 0) + vget_lane_f32(temp, 1); + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x0 = *(px++); + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = sum0; + + /* Decrement the loop counter */ + blkCntN4--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the satrt of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + i = (numTaps - 1U) >> 2; + + /* Copy data */ + while (i > 0U) + { + sum0v = vld1q_f32(pState); + vst1q_f32(pStateCurnt,sum0v); + pState += 4; + pStateCurnt += 4; + + /* Decrement the loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* Copy data */ + while (i > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + i--; + } +} +#else +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCur; /* Points to the current sample of the state */ + float32_t *px0; /* Temporary pointer for state buffer */ + const float32_t *pb; /* Temporary pointer for coefficient buffer */ + float32_t x0, c0; /* Temporary variables to hold state and coefficient values */ + float32_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t *px1, *px2, *px3; + float32_t x1, x2, x3; + float32_t acc1, acc2, acc3; +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 samples at a time */ + blkCnt = outBlockSize >> 2U; + + /* Samples loop unrolled by 4 */ + while (blkCnt > 0U) + { + /* Copy 4 * decimation factor number of new input samples into the state buffer */ + i = S->M * 4; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-1] sample for acc0 */ + x0 = *(px0++); + /* Read x[n-numTaps-1] sample for acc1 */ + x1 = *(px1++); + /* Read x[n-numTaps-1] sample for acc2 */ + x2 = *(px2++); + /* Read x[n-numTaps-1] sample for acc3 */ + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch state variables for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 4; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = acc0; + *pDst++ = acc1; + *pDst++ = acc2; + *pDst++ = acc3; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining samples */ + blkCnt = outBlockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = outBlockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0.0f; + + /* Initialize state pointer */ + px0 = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = acc0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ + +#endif /*defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of FIR_decimate group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c new file mode 100644 index 00000000..15bbb78a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c @@ -0,0 +1,595 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_fast_q15.c + * Description: Fast Q15 FIR Decimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for the Q15 FIR decimator (fast variant). + @param[in] S points to an instance of the Q15 FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of input samples to process per call + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2). + The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result. + @remark + Refer to \ref arm_fir_decimate_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. + Both the slow and the fast versions use the same instance structure. + Use function \ref arm_fir_decimate_init_q15() to initialize the filter structure. + */ + +#if defined (ARM_MATH_DSP) + +void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */ + q31_t sum0; /* Accumulators */ + q31_t acc0, acc1; + q15_t *px0, *px1; + uint32_t blkCntN3; + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t c1; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 2; + blkCntN3 = outBlockSize - (2 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 2 * decimation factor number of new input samples into the state buffer */ + i = S->M * 2; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */ + x0 = read_q15x2_ia (&px0); + x1 = read_q15x2_ia (&px1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + + /* Read the b[numTaps-3] and b[numTaps-4] coefficient */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */ + x0 = read_q15x2_ia (&px0); + x1 = read_q15x2_ia (&px1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch state variables for acc0, acc1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 2; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + while (blkCntN3 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2] sample */ + x0 = read_q15x2_ia (&px); + + /* Read the b[numTaps-3] and b[numTaps-4] coefficients */ + c1 = read_q15x2_ia ((q15_t **) &pb); + + /* Perform the multiply-accumulate */ + sum0 = __SMLAD(x0, c0, sum0); + + /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */ + x0 = read_q15x2_ia (&px); + + /* Perform the multiply-accumulate */ + sum0 = __SMLAD(x0, c1, sum0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 = __SMLAD(x0, c0, sum0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + blkCntN3--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + i = (numTaps - 1U) >> 2U; + + /* copy data */ + while (i > 0U) + { + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* Copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } + +} + +#else /* #if defined (ARM_MATH_DSP) */ + +void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q15_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */ + q31_t sum0; /* Accumulators */ + q31_t acc0, acc1; + q15_t *px0, *px1; + uint32_t blkCntN3; + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 2; + blkCntN3 = outBlockSize - (2 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 2 * decimation factor number of new input samples into the state buffer */ + i = S->M * 2; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + + /* Initialize state pointer */ + px0 = pState; + px1 = pState + S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the Read b[numTaps-1] coefficients */ + c0 = *pb++; + + /* Read x[n-numTaps-1] for sample 0 and for sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-3] coefficients */ + c0 = *pb++; + + /* Read x[n-numTaps-3] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 2; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + while (blkCntN3 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + blkCntN3--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the satrt of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + i = (numTaps - 1U) >> 2U; + + /* copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } +} + +#endif /* #if defined (ARM_MATH_DSP) */ + +/** + @} end of FIR_decimate group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c new file mode 100644 index 00000000..993f7ac7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c @@ -0,0 +1,390 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_fast_q31.c + * Description: Fast Q31 FIR Decimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for the Q31 FIR decimator (fast variant). + @param[in] S points to an instance of the Q31 FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are added to a 2.30 accumulator. + Finally, the accumulator is saturated and converted to a 1.31 result. + The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2). + + @remark + Refer to \ref arm_fir_decimate_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. + Both the slow and the fast versions use the same instance structure. + Use function \ref arm_fir_decimate_init_q31() to initialize the filter structure. + */ + +void arm_fir_decimate_fast_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + q31_t *px0; /* Temporary pointer for state buffer */ + const q31_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t x0, c0; /* Temporary variables to hold state and coefficient values */ + q63_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t *px1, *px2, *px3; + q31_t x1, x2, x3; + q63_t acc1, acc2, acc3; +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 samples at a time */ + blkCnt = outBlockSize >> 2U; + + /* Samples loop unrolled by 4 */ + while (blkCnt > 0U) + { + /* Copy 4 * decimation factor number of new input samples into the state buffer */ + i = S->M * 4; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-1] sample for acc0 */ + x0 = *(px0++); + /* Read x[n-numTaps-1] sample for acc1 */ + x1 = *(px1++); + /* Read x[n-numTaps-1] sample for acc2 */ + x2 = *(px2++); + /* Read x[n-numTaps-1] sample for acc3 */ + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch state variables for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 4; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (acc0 << 1); + *pDst++ = (q31_t) (acc1 << 1); + *pDst++ = (q31_t) (acc2 << 1); + *pDst++ = (q31_t) (acc3 << 1); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining samples */ + blkCnt = outBlockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = outBlockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px0 = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (acc0 << 1); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of FIR_decimate group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c new file mode 100644 index 00000000..de31b9f4 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c @@ -0,0 +1,105 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_init_f32.c + * Description: Floating-point FIR Decimator initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Initialization function for the floating-point FIR decimator. + @param[in,out] S points to an instance of the floating-point FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: +
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+  
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_f32(). + M is the decimation factor. + */ + +arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The size of the input block must be a multiple of the decimation factor */ + if ((blockSize % M) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Decimation Factor */ + S->M = M; + + status = ARM_MATH_SUCCESS; + } + + return (status); + +} + +/** + @} end of FIR_decimate group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c new file mode 100644 index 00000000..b43df2a0 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c @@ -0,0 +1,106 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_init_q15.c + * Description: Initialization function for the Q15 FIR Decimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Initialization function for the Q15 FIR decimator. + @param[in,out] S points to an instance of the Q15 FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: +
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+  
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples + to the call arm_fir_decimate_q15(). + M is the decimation factor. + */ + +arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The size of the input block must be a multiple of the decimation factor */ + if ((blockSize % M) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Decimation Factor */ + S->M = M; + + status = ARM_MATH_SUCCESS; + } + + return (status); + +} + +/** + @} end of FIR_decimate group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c new file mode 100644 index 00000000..7a9490a3 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c @@ -0,0 +1,105 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_init_q31.c + * Description: Initialization function for Q31 FIR Decimation filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Initialization function for the Q31 FIR decimator. + @param[in,out] S points to an instance of the Q31 FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: +
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+  
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_q31(). + M is the decimation factor. + */ + +arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The size of the input block must be a multiple of the decimation factor */ + if ((blockSize % M) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Decimation Factor */ + S->M = M; + + status = ARM_MATH_SUCCESS; + } + + return (status); + +} + +/** + @} end of FIR_decimate group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c new file mode 100644 index 00000000..21f18e5c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c @@ -0,0 +1,851 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_q15.c + * Description: Q15 FIR Decimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for the Q15 FIR decimator. + @param[in] S points to an instance of the Q15 FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of input samples to process per call + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + + @remark + Refer to \ref arm_fir_decimate_fast_q15() for a faster but less precise implementation of this function. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + const q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + uint32_t blkCntN4; + const q15_t *px0, *px1, *px2, *px3; + q63_t acc0v, acc1v, acc2v, acc3v; + q15x8_t x0v, x1v, x2v, x3v; + q15x8_t c0v; + + /* + * S->pState buffer contains previous frame (numTaps - 1) samples + * pStateCurnt points to the location where the new input data should be written + */ + pStateCurnt = S->pState + (numTaps - 1U); + /* + * Total number of output samples to be computed + */ + blkCnt = outBlockSize / 4; + blkCntN4 = outBlockSize - (4 * blkCnt); + + while (blkCnt > 0U) + { + /* + * Need extra temp variables as 4 * S->M is not necessarily a multiple of 8 + * and cause final tail predicated post incremented pointers to jump ahead + */ + const q15_t *pSrcTmp = pSrc; + q15_t *pStateCurntTmp = pStateCurnt; + + /* + * Copy 4 * decimation factor number of new input samples into the state buffer + */ + i = (4 * S->M) >> 3; + while (i > 0U) + { + vstrhq_s16(pStateCurntTmp, vldrhq_s16(pSrcTmp)); + pSrcTmp += 8; + pStateCurntTmp += 8; + i--; + } + i = (4 * S->M) & 7; + if (i > 0U) + { + mve_pred16_t p0 = vctp16q(i); + vstrhq_p_s16(pStateCurntTmp, vldrhq_s16(pSrcTmp), p0); + } + + pSrc += (4 * S->M); + pStateCurnt += (4 * S->M); + + /* + * Clear all accumulators + */ + acc0v = 0LL; + acc1v = 0LL; + acc2v = 0LL; + acc3v = 0LL; + /* + * Initialize state pointer for all the samples + */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + /* + * Initialize coeff. pointer + */ + pb = pCoeffs; + + tapCnt = numTaps >> 3; + /* + * Loop over the number of taps. Unroll by a factor of 4. + * Repeat until we've computed numTaps-4 coefficients. + */ + while (tapCnt > 0U) + { + /* + * Read the b[numTaps-1] coefficient + */ + c0v = vldrhq_s16(pb); + pb += 8; + /* + * Read x[n-numTaps-1] sample for acc0 + */ + x0v = vld1q(px0); + x1v = vld1q(px1); + x2v = vld1q(px2); + x3v = vld1q(px3); + px0 += 8; + px1 += 8; + px2 += 8; + px3 += 8; + + acc0v = vmlaldavaq(acc0v, x0v, c0v); + acc1v = vmlaldavaq(acc1v, x1v, c0v); + acc2v = vmlaldavaq(acc2v, x2v, c0v); + acc3v = vmlaldavaq(acc3v, x3v, c0v); + /* + * Decrement the loop counter + */ + tapCnt--; + } + + /* + * If the filter length is not a multiple of 4, compute the remaining filter taps + * should be tail predicated + */ + tapCnt = numTaps & 7; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp16q(tapCnt); + /* + * Read the b[numTaps-1] coefficient + */ + c0v = vldrhq_z_s16(pb, p0); + pb += 8; + /* + * Read x[n-numTaps-1] sample for acc0 + */ + x0v = vld1q(px0); + x1v = vld1q(px1); + x2v = vld1q(px2); + x3v = vld1q(px3); + px0 += 8; + px1 += 8; + px2 += 8; + px3 += 8; + + acc0v = vmlaldavaq(acc0v, x0v, c0v); + acc1v = vmlaldavaq(acc1v, x1v, c0v); + acc2v = vmlaldavaq(acc2v, x2v, c0v); + acc3v = vmlaldavaq(acc3v, x3v, c0v); + } + + acc0v = asrl(acc0v, 15); + acc1v = asrl(acc1v, 15); + acc2v = asrl(acc2v, 15); + acc3v = asrl(acc3v, 15); + /* + * store in the destination buffer. + */ + *pDst++ = (q15_t) __SSAT((q31_t) acc0v, 16); + *pDst++ = (q15_t) __SSAT((q31_t) acc1v, 16);; + *pDst++ = (q15_t) __SSAT((q31_t) acc2v, 16);; + *pDst++ = (q15_t) __SSAT((q31_t) acc3v, 16);; + + /* + * Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples + */ + pState = pState + 4 * S->M; + /* + * Decrement the loop counter + */ + blkCnt--; + } + + while (blkCntN4 > 0U) + { + /* + * Copy decimation factor number of new input samples into the state buffer + */ + i = S->M; + do + { + *pStateCurnt++ = *pSrc++; + } + while (--i); + /* + * Set accumulator to zero + */ + acc0v = 0LL; + /* + * Initialize state pointer + */ + px = pState; + /* + * Initialize coeff. pointer + */ + pb = pCoeffs; + + tapCnt = numTaps >> 3; + while (tapCnt > 0U) + { + c0v = vldrhq_s16(pb); + x0v = vldrhq_s16(px); + pb += 8; + px += 8; + acc0v = vmlaldavaq(acc0v, x0v, c0v); + /* + * Decrement the loop counter + */ + tapCnt--; + } + + tapCnt = numTaps & 7; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp16q(tapCnt); + c0v = vldrhq_z_s16(pb, p0); + x0v = vldrhq_z_s16(px, p0); + acc0v = vmlaldavaq_p(acc0v, x0v, c0v, p0); + } + + acc0v = asrl(acc0v, 15); + + /* + * Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples + */ + pState = pState + S->M; + /* + * The result is in the accumulator, store in the destination buffer. + */ + *pDst++ = (q15_t) __SSAT((q31_t) acc0v, 16); + /* + * Decrement the loop counter + */ + blkCntN4--; + } + + /* + * Processing is complete. + * Now copy the last numTaps - 1 samples to the start of the state buffer. + * This prepares the state buffer for the next function call. + */ + + pStateCurnt = S->pState; + blkCnt = (numTaps - 1) >> 3; + while (blkCnt > 0U) + { + vstrhq_s16(pStateCurnt, vldrhq_s16(pState)); + pState += 8; + pStateCurnt += 8; + blkCnt--; + } + blkCnt = (numTaps - 1) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vstrhq_p_s16(pStateCurnt, vldrhq_s16(pState), p0); + } +} +#else +#if defined (ARM_MATH_DSP) + +void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */ + q63_t sum0; /* Accumulators */ + q63_t acc0, acc1; + q15_t *px0, *px1; + uint32_t blkCntN3; + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t c1; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 2; + blkCntN3 = outBlockSize - (2 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 2 * decimation factor number of new input samples into the state buffer */ + i = S->M * 2; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */ + x0 = read_q15x2_ia (&px0); + x1 = read_q15x2_ia (&px1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + + /* Read the b[numTaps-3] and b[numTaps-4] coefficient */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */ + x0 = read_q15x2_ia (&px0); + x1 = read_q15x2_ia (&px1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch state variables for acc0, acc1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 2; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + while (blkCntN3 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2] sample */ + x0 = read_q15x2_ia (&px); + + /* Read the b[numTaps-3] and b[numTaps-4] coefficients */ + c1 = read_q15x2_ia ((q15_t **) &pb); + + /* Perform the multiply-accumulate */ + sum0 = __SMLALD(x0, c0, sum0); + + /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */ + x0 = read_q15x2_ia (&px); + + /* Perform the multiply-accumulate */ + sum0 = __SMLALD(x0, c1, sum0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 = __SMLALD(x0, c0, sum0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + blkCntN3--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + i = (numTaps - 1U) >> 2U; + + /* copy data */ + while (i > 0U) + { + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* Copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } + +} + +#else /* #if defined (ARM_MATH_DSP) */ + +void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q15_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */ + q63_t sum0; /* Accumulators */ + q63_t acc0, acc1; + q15_t *px0, *px1; + uint32_t blkCntN3; + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 2; + blkCntN3 = outBlockSize - (2 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 2 * decimation factor number of new input samples into the state buffer */ + i = S->M * 2; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + + /* Initialize state pointer */ + px0 = pState; + px1 = pState + S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the Read b[numTaps-1] coefficients */ + c0 = *pb++; + + /* Read x[n-numTaps-1] for sample 0 and for sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-3] coefficients */ + c0 = *pb++; + + /* Read x[n-numTaps-3] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 2; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + while (blkCntN3 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + blkCntN3--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the satrt of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + i = (numTaps - 1U) >> 2U; + + /* copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } +} + +#endif /* #if defined (ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) */ +/** + @} end of FIR_decimate group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c new file mode 100644 index 00000000..77bfc168 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c @@ -0,0 +1,634 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_q31.c + * Description: Q31 FIR Decimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for the Q31 FIR decimator. + @param[in] S points to an instance of the Q31 FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2). + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + + @remark + Refer to \ref arm_fir_decimate_fast_q31() for a faster but less precise implementation of this function. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + const q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + uint32_t blkCntN4; + const q31_t *px0, *px1, *px2, *px3; + q63_t acc0v, acc1v, acc2v, acc3v; + q31x4_t x0v, x1v, x2v, x3v; + q31x4_t c0v; + + /* + * S->pState buffer contains previous frame (numTaps - 1) samples + * pStateCurnt points to the location where the new input data should be written + */ + pStateCurnt = S->pState + (numTaps - 1U); + /* + * Total number of output samples to be computed + */ + blkCnt = outBlockSize / 4; + blkCntN4 = outBlockSize - (4 * blkCnt); + + while (blkCnt > 0U) + { + /* + * Copy 4 * decimation factor number of new input samples into the state buffer + */ + i = (4 * S->M) >> 2; + do + { + vst1q(pStateCurnt, vldrwq_s32(pSrc)); + pSrc += 4; + pStateCurnt += 4; + i--; + } + while (i > 0U); + + /* + * Clear all accumulators + */ + acc0v = 0LL; + acc1v = 0LL; + acc2v = 0LL; + acc3v = 0LL; + /* + * Initialize state pointer for all the samples + */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + /* + * Initialize coeff. pointer + */ + pb = pCoeffs; + /* + * Loop unrolling. Process 4 taps at a time. + */ + tapCnt = numTaps >> 2; + /* + * Loop over the number of taps. Unroll by a factor of 4. + * Repeat until we've computed numTaps-4 coefficients. + */ + while (tapCnt > 0U) + { + /* + * Read the b[numTaps-1] coefficient + */ + c0v = vldrwq_s32(pb); + pb += 4; + /* + * Read x[n-numTaps-1] sample for acc0 + */ + x0v = vld1q(px0); + x1v = vld1q(px1); + x2v = vld1q(px2); + x3v = vld1q(px3); + px0 += 4; + px1 += 4; + px2 += 4; + px3 += 4; + + acc0v = vrmlaldavhaq(acc0v, x0v, c0v); + acc1v = vrmlaldavhaq(acc1v, x1v, c0v); + acc2v = vrmlaldavhaq(acc2v, x2v, c0v); + acc3v = vrmlaldavhaq(acc3v, x3v, c0v); + /* + * Decrement the loop counter + */ + tapCnt--; + } + + /* + * If the filter length is not a multiple of 4, compute the remaining filter taps + * should be tail predicated + */ + tapCnt = numTaps % 0x4U; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + /* + * Read the b[numTaps-1] coefficient + */ + c0v = vldrwq_z_s32(pb, p0); + pb += 4; + /* + * Read x[n-numTaps-1] sample for acc0 + */ + x0v = vld1q(px0); + x1v = vld1q(px1); + x2v = vld1q(px2); + x3v = vld1q(px3); + px0 += 4; + px1 += 4; + px2 += 4; + px3 += 4; + + acc0v = vrmlaldavhaq(acc0v, x0v, c0v); + acc1v = vrmlaldavhaq(acc1v, x1v, c0v); + acc2v = vrmlaldavhaq(acc2v, x2v, c0v); + acc3v = vrmlaldavhaq(acc3v, x3v, c0v); + } + + acc0v = asrl(acc0v, 31 - 8); + acc1v = asrl(acc1v, 31 - 8); + acc2v = asrl(acc2v, 31 - 8); + acc3v = asrl(acc3v, 31 - 8); + /* + * store in the destination buffer. + */ + *pDst++ = (q31_t) acc0v; + *pDst++ = (q31_t) acc1v; + *pDst++ = (q31_t) acc2v; + *pDst++ = (q31_t) acc3v; + + /* + * Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples + */ + pState = pState + 4 * S->M; + /* + * Decrement the loop counter + */ + blkCnt--; + } + + while (blkCntN4 > 0U) + { + /* + * Copy decimation factor number of new input samples into the state buffer + */ + i = S->M; + do + { + *pStateCurnt++ = *pSrc++; + } + while (--i); + /* + * Set accumulator to zero + */ + acc0v = 0LL; + /* + * Initialize state pointer + */ + px = pState; + /* + * Initialize coeff. pointer + */ + pb = pCoeffs; + /* + * Loop unrolling. Process 4 taps at a time. + */ + tapCnt = numTaps >> 2; + /* + * Loop over the number of taps. Unroll by a factor of 4. + * Repeat until we've computed numTaps-4 coefficients. + */ + while (tapCnt > 0U) + { + c0v = vldrwq_s32(pb); + x0v = vldrwq_s32(px); + pb += 4; + px += 4; + acc0v = vrmlaldavhaq(acc0v, x0v, c0v); + /* + * Decrement the loop counter + */ + tapCnt--; + } + tapCnt = numTaps % 0x4U; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + c0v = vldrwq_z_s32(pb, p0); + x0v = vldrwq_z_s32(px, p0); + acc0v = vrmlaldavhaq_p(acc0v, x0v, c0v, p0); + } + acc0v = asrl(acc0v, 31 - 8); + + /* + * Advance the state pointer by the decimation factor + * * to process the next group of decimation factor number samples + */ + pState = pState + S->M; + /* + * The result is in the accumulator, store in the destination buffer. + */ + *pDst++ = (q31_t) acc0v; + /* + * Decrement the loop counter + */ + blkCntN4--; + } + + /* + * Processing is complete. + * Now copy the last numTaps - 1 samples to the start of the state buffer. + * This prepares the state buffer for the next function call. + */ + pStateCurnt = S->pState; + blkCnt = (numTaps - 1) >> 2; + while (blkCnt > 0U) + { + vst1q(pStateCurnt, vldrwq_s32(pState)); + pState += 4; + pStateCurnt += 4; + blkCnt--; + } + blkCnt = (numTaps - 1) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_s32(pStateCurnt, vldrwq_s32(pState), p0); + } +} +#else +void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + q31_t *px0; /* Temporary pointer for state buffer */ + const q31_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t x0, c0; /* Temporary variables to hold state and coefficient values */ + q63_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t *px1, *px2, *px3; + q31_t x1, x2, x3; + q63_t acc1, acc2, acc3; +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 samples at a time */ + blkCnt = outBlockSize >> 2U; + + /* Samples loop unrolled by 4 */ + while (blkCnt > 0U) + { + /* Copy 4 * decimation factor number of new input samples into the state buffer */ + i = S->M * 4; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-1] sample for acc0 */ + x0 = *(px0++); + /* Read x[n-numTaps-1] sample for acc1 */ + x1 = *(px1++); + /* Read x[n-numTaps-1] sample for acc2 */ + x2 = *(px2++); + /* Read x[n-numTaps-1] sample for acc3 */ + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch state variables for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 4; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (acc0 >> 31); + *pDst++ = (q31_t) (acc1 >> 31); + *pDst++ = (q31_t) (acc2 >> 31); + *pDst++ = (q31_t) (acc3 >> 31); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining samples */ + blkCnt = outBlockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = outBlockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px0 = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (acc0 >> 31); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ +/** + @} end of FIR_decimate group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f16.c new file mode 100644 index 00000000..f89c2d37 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f16.c @@ -0,0 +1,940 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_f16.c + * Description: Floating-point FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters + */ + + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for floating-point FIR filter. + @param[in] S points to an instance of the floating-point FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define FIR_F32_MAX_COEF_BLK 8 + +#define FIR_F16_CORE(pSamples, c, NB_TAPS) \ + vecAcc0 = vdupq_n_f16(0.0f16); \ + for (int i = 0; i < NB_TAPS; i++) { \ + vecIn0 = vld1q(&pSamples[i]); \ + vecAcc0 = vfmaq(vecAcc0, vecIn0, c[i]); \ + } + +#define NB_TAPS 4 +__STATIC_INLINE void arm_fir_f16_1_4_mve(const arm_fir_instance_f16 * S, + const float16_t * __restrict pSrc, + float16_t * __restrict pDst, uint32_t blockSize) +{ + float16_t *pState = S->pState; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float16_t *pStateCur; /* Points to the current sample of the state */ + const float16_t *pSamples; /* Temporary pointer to the sample buffer */ + float16_t *pOutput; /* Temporary pointer to the output buffer */ + const float16_t *pTempSrc; /* Temporary pointer to the source data */ + float16_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t blkCnt; + float16x8_t vecIn0; + float16x8_t vecAcc0; + float16_t c[NB_TAPS]; + + + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + /* + * Copy new data into state so that we obtain a continuous sample buffer + * containing both the tail end of the old data and the new data. + */ + pSamples = pState; + pTempSrc = pSrc; + pOutput = pDst; + + for (int i = 0; i < NB_TAPS; i++) + c[i] = pCoeffs[i]; + + blkCnt = blockSize >> 3; + while (blkCnt > 0) { + /* + * Save 8 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 8; + pTempSrc += 8; + + FIR_F16_CORE(pSamples, c, NB_TAPS); + + vst1q(pOutput, vecAcc0); + + pOutput += 8; + pSamples += 8; + + blkCnt--; + } + + blkCnt = blockSize & 7; + if (blkCnt) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 8; + pTempSrc += 8; + + FIR_F16_CORE(pSamples, c, NB_TAPS); + + vstrhq_p_f16(pOutput, vecAcc0, p0); + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = numTaps >> 3; + while (blkCnt > 0) { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 8; + pTempDest += 8; + blkCnt--; + } + blkCnt = numTaps & 7; + if (blkCnt > 0) { + mve_pred16_t p0 = vctp16q(blkCnt); + vstrhq_p_f16(pTempDest, vld1q(pTempSrc), p0); + } + +} +#undef NB_TAPS + +#define NB_TAPS 8 +__STATIC_INLINE void arm_fir_f16_5_8_mve(const arm_fir_instance_f16 * S, + const float16_t * __restrict pSrc, + float16_t * __restrict pDst, uint32_t blockSize) +{ + float16_t *pState = S->pState; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float16_t *pStateCur; /* Points to the current sample of the state */ + const float16_t *pSamples; /* Temporary pointer to the sample buffer */ + float16_t *pOutput; /* Temporary pointer to the output buffer */ + const float16_t *pTempSrc; /* Temporary pointer to the source data */ + float16_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t blkCnt; + float16x8_t vecIn0; + float16x8_t vecAcc0; + float16_t c[NB_TAPS]; + + + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + /* + * Copy new data into state so that we obtain a continuous sample buffer + * containing both the tail end of the old data and the new data. + */ + pSamples = pState; + pTempSrc = pSrc; + pOutput = pDst; + + for (int i = 0; i < NB_TAPS; i++) + c[i] = pCoeffs[i]; + + blkCnt = blockSize >> 3; + while (blkCnt > 0) { + /* + * Save 8 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 8; + pTempSrc += 8; + + FIR_F16_CORE(pSamples, c, NB_TAPS); + + vst1q(pOutput, vecAcc0); + + pOutput += 8; + pSamples += 8; + + blkCnt--; + } + + blkCnt = blockSize & 7; + if (blkCnt) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 8; + pTempSrc += 8; + + FIR_F16_CORE(pSamples, c, NB_TAPS); + + vstrhq_p_f16(pOutput, vecAcc0, p0); + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = numTaps >> 3; + while (blkCnt > 0) { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 8; + pTempDest += 8; + blkCnt--; + } + blkCnt = numTaps & 7; + if (blkCnt > 0) { + mve_pred16_t p0 = vctp16q(blkCnt); + vstrhq_p_f16(pTempDest, vld1q(pTempSrc), p0); + } + +} +#undef NB_TAPS + +void arm_fir_f16(const arm_fir_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + float16_t *pRefStatePtr = S->pState + ROUND_UP(blockSize, 8); + float16_t *pState = pRefStatePtr ; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + const float16_t *pSamples; /* Temporary pointer to the sample buffer */ + float16_t *pOutput; /* Temporary pointer to the output buffer */ + const float16_t *pTempSrc; /* Temporary pointer to the source data */ + float16_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t blkCnt; + float16_t c0, c1, c2, c3; + float16_t c4, c5, c6, c7; + + /* + * [1 to 8 taps] specialized routines + */ + if (numTaps <= 4) { + arm_fir_f16_1_4_mve(S, pSrc, pDst, blockSize); + return; + } else if (numTaps <= 8) { + arm_fir_f16_5_8_mve(S, pSrc, pDst, blockSize); + return; + } + + pTempSrc = pSrc; + pTempDest = &(pState[(numTaps - 1u)]); + int cnt = blockSize; + do { + mve_pred16_t p0 = vctp16q(cnt); + vstrhq_p_f16(pTempDest, vld1q(pTempSrc), p0); + pTempDest += 8; + pTempSrc += 8; + cnt -= 8; + } while (cnt > 0); + + float16_t *partial_accu_ptr = S->pState; + + pSamples = pState; + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + c4 = *pCoeffs++; + c5 = *pCoeffs++; + c6 = *pCoeffs++; + c7 = *pCoeffs++; + + cnt = blockSize >> 3; + while (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + pSamples += 8; + vst1q(partial_accu_ptr, vecAcc0); + cnt--; + partial_accu_ptr += 8; + } + + cnt = blockSize & 7; + if (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + mve_pred16_t p0 = vctp16q(cnt); + + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + vstrhq_p_f16(partial_accu_ptr, vecAcc0,p0); + } + + int localTaps = numTaps - FIR_F32_MAX_COEF_BLK; + int sample_offset = FIR_F32_MAX_COEF_BLK; + while (localTaps > FIR_F32_MAX_COEF_BLK) { + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + c4 = *pCoeffs++; + c5 = *pCoeffs++; + c6 = *pCoeffs++; + c7 = *pCoeffs++; + + partial_accu_ptr = S->pState; + pSamples = pState + sample_offset; + int cnt = blockSize >> 3; + while (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + pSamples += 8; + vecAcc0 += vld1q_f16(partial_accu_ptr); + vst1q(partial_accu_ptr, vecAcc0); + cnt--; + partial_accu_ptr += 8; + } + + cnt = blockSize & 7; + if (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + mve_pred16_t p0 = vctp16q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + vecAcc0 += vld1q_f16(partial_accu_ptr); + vstrhq_p_f16(partial_accu_ptr, vecAcc0,p0); + } + + localTaps -= FIR_F32_MAX_COEF_BLK; + sample_offset += FIR_F32_MAX_COEF_BLK; + } + + pSamples = pState + sample_offset; + + if (localTaps > 4) { + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + c4 = *pCoeffs++; + c5 = *pCoeffs++; + c6 = *pCoeffs++; + c7 = *pCoeffs++; + pOutput = pDst; + + partial_accu_ptr = S->pState; + cnt = blockSize >> 3; + while (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + pSamples += 8; + float16x8_t pap = vld1q_f16(partial_accu_ptr); + vst1q(pOutput, vecAcc0 + pap); + cnt--; + partial_accu_ptr += 8; + pOutput += 8; + } + + cnt = blockSize & 7; + if (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + mve_pred16_t p0 = vctp16q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + float16x8_t pap = vld1q_f16(partial_accu_ptr); + vstrhq_p_f16(pOutput, vecAcc0 + pap, p0); + pOutput += cnt; + } + + } else { + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + pOutput = pDst; + + partial_accu_ptr = S->pState; + cnt = blockSize >> 3; + while (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + pSamples += 8; + float16x8_t pap = vld1q_f16(partial_accu_ptr); + vst1q(pOutput, vecAcc0 + pap); + cnt--; + partial_accu_ptr += 8; + pOutput += 8; + } + + cnt = blockSize & 7; + if (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + mve_pred16_t p0 = vctp16q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + float16x8_t pap = vld1q_f16(partial_accu_ptr); + vstrhq_p_f16(pOutput, vecAcc0 + pap, p0); + pOutput += cnt; + } + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = numTaps >> 3; + while (blkCnt > 0U) { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 8; + pTempDest += 8; + blkCnt--; + } + blkCnt = numTaps & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + vstrhq_p_f16(pTempDest, vld1q(pTempSrc), p0); + } +} + +#else + +void arm_fir_f16( + const arm_fir_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + float16_t *pState = S->pState; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float16_t *pStateCurnt; /* Points to the current sample of the state */ + float16_t *px; /* Temporary pointer for state buffer */ + const float16_t *pb; /* Temporary pointer for coefficient buffer */ + _Float16 acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + _Float16 acc1, acc2, acc3, acc4, acc5, acc6, acc7; /* Accumulators */ + _Float16 x0, x1, x2, x3, x4, x5, x6, x7; /* Temporary variables to hold state values */ + _Float16 c0; /* Temporary variable to hold coefficient value */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 8 output values simultaneously. + * The variables acc0 ... acc7 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + acc4 = 0.0f; + acc5 = 0.0f; + acc6 = 0.0f; + acc7 = 0.0f; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* This is separated from the others to avoid + * a call to __aeabi_memmove which would be slower + */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Read the first 7 samples from the state buffer: x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + x3 = *px++; + x4 = *px++; + x5 = *px++; + x6 = *px++; + + /* Loop unrolling: process 8 taps at a time. */ + tapCnt = numTaps >> 3U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample */ + x7 = *(px++); + + /* acc0 += b[numTaps-1] * x[n-numTaps] */ + acc0 += x0 * c0; + + /* acc1 += b[numTaps-1] * x[n-numTaps-1] */ + acc1 += x1 * c0; + + /* acc2 += b[numTaps-1] * x[n-numTaps-2] */ + acc2 += x2 * c0; + + /* acc3 += b[numTaps-1] * x[n-numTaps-3] */ + acc3 += x3 * c0; + + /* acc4 += b[numTaps-1] * x[n-numTaps-4] */ + acc4 += x4 * c0; + + /* acc1 += b[numTaps-1] * x[n-numTaps-5] */ + acc5 += x5 * c0; + + /* acc2 += b[numTaps-1] * x[n-numTaps-6] */ + acc6 += x6 * c0; + + /* acc3 += b[numTaps-1] * x[n-numTaps-7] */ + acc7 += x7 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample */ + x0 = *(px++); + + /* Perform the multiply-accumulate */ + acc0 += x1 * c0; + acc1 += x2 * c0; + acc2 += x3 * c0; + acc3 += x4 * c0; + acc4 += x5 * c0; + acc5 += x6 * c0; + acc6 += x7 * c0; + acc7 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-5] sample */ + x1 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x2 * c0; + acc1 += x3 * c0; + acc2 += x4 * c0; + acc3 += x5 * c0; + acc4 += x6 * c0; + acc5 += x7 * c0; + acc6 += x0 * c0; + acc7 += x1 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x3 * c0; + acc1 += x4 * c0; + acc2 += x5 * c0; + acc3 += x6 * c0; + acc4 += x7 * c0; + acc5 += x0 * c0; + acc6 += x1 * c0; + acc7 += x2 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x3 = *(px++); + /* Perform the multiply-accumulates */ + acc0 += x4 * c0; + acc1 += x5 * c0; + acc2 += x6 * c0; + acc3 += x7 * c0; + acc4 += x0 * c0; + acc5 += x1 * c0; + acc6 += x2 * c0; + acc7 += x3 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x4 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x5 * c0; + acc1 += x6 * c0; + acc2 += x7 * c0; + acc3 += x0 * c0; + acc4 += x1 * c0; + acc5 += x2 * c0; + acc6 += x3 * c0; + acc7 += x4 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x5 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x6 * c0; + acc1 += x7 * c0; + acc2 += x0 * c0; + acc3 += x1 * c0; + acc4 += x2 * c0; + acc5 += x3 * c0; + acc6 += x4 * c0; + acc7 += x5 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x6 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x7 * c0; + acc1 += x0 * c0; + acc2 += x1 * c0; + acc3 += x2 * c0; + acc4 += x3 * c0; + acc5 += x4 * c0; + acc6 += x5 * c0; + acc7 += x6 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = numTaps % 0x8U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x7 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + acc4 += x4 * c0; + acc5 += x5 * c0; + acc6 += x6 * c0; + acc7 += x7 * c0; + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + x2 = x3; + x3 = x4; + x4 = x5; + x5 = x6; + x6 = x7; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by 8 to process the next group of 8 samples */ + pState = pState + 8; + + /* The results in the 8 accumulators, store in the destination buffer. */ + *pDst++ = acc0; + *pDst++ = acc1; + *pDst++ = acc2; + *pDst++ = acc3; + *pDst++ = acc4; + *pDst++ = acc5; + *pDst++ = acc6; + *pDst++ = acc7; + + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x8U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0.0f; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + while (i > 0U) + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + acc0 += (_Float16)*px++ * (_Float16)*pb++; + + i--; + } + + /* Store result in destination buffer. */ + *pDst++ = acc0; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +#endif /* #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** +* @} end of FIR group +*/ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c new file mode 100644 index 00000000..f8c1d806 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c @@ -0,0 +1,1285 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_f32.c + * Description: Floating-point FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup FIR Finite Impulse Response (FIR) Filters + + This set of functions implements Finite Impulse Response (FIR) filters + for Q7, Q15, Q31, and floating-point data types. Fast versions of Q15 and Q31 are also provided. + The functions operate on blocks of input and output data and each call to the function processes + blockSize samples through the filter. pSrc and + pDst points to input and output arrays containing blockSize values. + + @par Algorithm + The FIR filter algorithm is based upon a sequence of multiply-accumulate (MAC) operations. + Each filter coefficient b[n] is multiplied by a state variable which equals a previous input sample x[n]. +
+      y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+  
+ @par + \image html FIR.GIF "Finite Impulse Response filter" + @par + pCoeffs points to a coefficient array of size numTaps. + Coefficients are stored in time reversed order. + @par +
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+  
+ @par + pState points to a state array of size numTaps + blockSize - 1. + Samples in the state buffer are stored in the following order. + @par +
+      {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[n](==pSrc[0]), x[n+1](==pSrc[1]), ..., x[n+blockSize-1](==pSrc[blockSize-1])}
+  
+ @par + Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1. + The increased state buffer length allows circular addressing, which is traditionally used in the FIR filters, + to be avoided and yields a significant speed improvement. + The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 4 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + The code below statically initializes each of the 4 different data type filter instance structures +
+      arm_fir_instance_f32 S = {numTaps, pState, pCoeffs};
+      arm_fir_instance_q31 S = {numTaps, pState, pCoeffs};
+      arm_fir_instance_q15 S = {numTaps, pState, pCoeffs};
+      arm_fir_instance_q7 S =  {numTaps, pState, pCoeffs};
+  
+ where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer. + @par Initialization of Helium version + For Helium version the array of coefficients must be padded with zero to contain + a full number of lanes. + + The array length L must be a multiple of x. L = x * a : + - x is 4 for f32 + - x is 4 for q31 + - x is 4 for f16 (so managed like the f32 version and not like the q15 one) + - x is 8 for q15 + - x is 16 for q7 + + The additional coefficients + (x * a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + + + @par Helium state buffer + The state buffer must contain some additional temporary data + used during the computation but which is not the state of the FIR. + The first A samples are temporary data. + The remaining samples are the state of the FIR filter. + @par + So the state buffer has size numTaps + A + blockSize - 1 : + - A is blockSize for f32 + - A is 8*ceil(blockSize/8) for f16 + - A is 8*ceil(blockSize/4) for q31 + - A is 0 for other datatypes (q15 and q7) + + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the FIR filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for floating-point FIR filter. + @param[in] S points to an instance of the floating-point FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define FIR_F32_MAX_COEF_BLK 8 + +#define FIR_F32_CORE(pSamples, c, NB_TAPS) \ + vecAcc0 = vdupq_n_f32(0.0f); \ + for (int i = 0; i < NB_TAPS; i++) { \ + vecIn0 = vld1q(&pSamples[i]); \ + vecAcc0 = vfmaq(vecAcc0, vecIn0, c[i]); \ + } + + +#define NB_TAPS 4 +__STATIC_INLINE void arm_fir_f32_1_4_mve(const arm_fir_instance_f32 * S, + const float32_t * __restrict pSrc, + float32_t * __restrict pDst, uint32_t blockSize) +{ + float32_t *pRefStatePtr = S->pState + blockSize; + float32_t *pState = pRefStatePtr; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCur; /* Points to the current sample of the state */ + const float32_t *pSamples; /* Temporary pointer to the sample buffer */ + float32_t *pOutput; /* Temporary pointer to the output buffer */ + const float32_t *pTempSrc; /* Temporary pointer to the source data */ + float32_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t blkCnt; + float32x4_t vecIn0; + float32x4_t vecAcc0; + float32_t c[NB_TAPS]; + const float32_t *pCoeffsCur = pCoeffs; + + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + pTempSrc = pSrc; + + pSamples = pState; + pOutput = pDst; + + for (int i = 0; i < NB_TAPS; i++) + c[i] = *pCoeffsCur++; + + blkCnt = blockSize >> 2; + while (blkCnt > 0) { + /* + * Save 4 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + FIR_F32_CORE(pSamples, c, NB_TAPS); + + vst1q(pOutput, vecAcc0); + + pOutput += 4; + pSamples += 4; + + blkCnt--; + } + + blkCnt = blockSize & 3; + if (blkCnt) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + FIR_F32_CORE(pSamples, c, NB_TAPS); + + vstrwq_p_f32(pOutput, vecAcc0, p0); + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = numTaps - 1; + do { + mve_pred16_t p = vctp32q(blkCnt); + + vstrwq_p_f32(pTempDest, vldrwq_z_f32(pTempSrc, p), p); + pTempSrc += 4; + pTempDest += 4; + blkCnt -= 4; + } + while (blkCnt > 0); +} +#undef NB_TAPS + +__STATIC_INLINE void arm_fir_f32_5_8_mve(const arm_fir_instance_f32 * S, + const float32_t * __restrict pSrc, + float32_t * __restrict pDst, uint32_t blockSize) +{ + float32_t *pRefStatePtr = S->pState + blockSize; + float32_t *pState = pRefStatePtr; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + const float32_t *pSamples; /* Temporary pointer to the sample buffer */ + const float32_t *pTempSrc; /* Temporary pointer to the source data */ + float32_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t blkCnt; + float32_t c0, c1, c2, c3; + float32_t c4, c5, c6, c7; + + + pTempSrc = pSrc; + pTempDest = &(pState[(numTaps - 1u)]); + int cnt = blockSize; + do { + mve_pred16_t p0 = vctp32q(cnt); + vstrwq_p_f32(pTempDest, vld1q(pTempSrc), p0); + pTempDest += 4; + pTempSrc += 4; + cnt -= 4; + } while(cnt > 0); + + + + pSamples = pState; + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + c4 = *pCoeffs++; + c5 = *pCoeffs++; + c6 = *pCoeffs++; + c7 = *pCoeffs++; + + cnt = blockSize >> 2; + while(cnt > 0) + { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + pSamples += 4; + vst1q(pDst, vecAcc0); + cnt--; + pDst += 4; + } + + cnt = blockSize & 3; + if (cnt > 0) + { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + mve_pred16_t p0 = vctp32q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + vstrwq_p_f32(pDst, vecAcc0,p0); + } + + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + blkCnt = numTaps; + while (blkCnt > 0) + { + *pTempDest++ = *pTempSrc++; + blkCnt--; + } +} + + + +void arm_fir_f32( +const arm_fir_instance_f32 * S, +const float32_t * pSrc, +float32_t * pDst, +uint32_t blockSize) +{ + /* + S->pState is the arm_fir_partial_accu + S->pState + blockSize is the FIR state + */ + float32_t *pRefStatePtr = S->pState + blockSize; + float32_t *pState = pRefStatePtr ; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + const float32_t *pSamples; /* Temporary pointer to the sample buffer */ + float32_t *pOutput; /* Temporary pointer to the output buffer */ + const float32_t *pTempSrc; /* Temporary pointer to the source data */ + float32_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t blkCnt; + float32_t c0, c1, c2, c3; + float32_t c4, c5, c6, c7; + + /* + * [1 to 8 taps] specialized routines + */ + if (numTaps <= 4) + { + arm_fir_f32_1_4_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 8) + { + arm_fir_f32_5_8_mve(S, pSrc, pDst, blockSize); + return; + } + + pTempSrc = pSrc; + pTempDest = &(pState[(numTaps - 1u)]); + int cnt = blockSize; + do { + mve_pred16_t p0 = vctp32q(cnt); + vstrwq_p_f32(pTempDest, vld1q(pTempSrc), p0); + pTempDest += 4; + pTempSrc += 4; + cnt -= 4; + } while(cnt > 0); + + float32_t *partial_accu_ptr = S->pState; + + pSamples = pState; + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + c4 = *pCoeffs++; + c5 = *pCoeffs++; + c6 = *pCoeffs++; + c7 = *pCoeffs++; + + cnt = blockSize >> 2; + while(cnt > 0) { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + pSamples += 4; + vst1q(partial_accu_ptr, vecAcc0); + cnt--; + partial_accu_ptr += 4; + } + + cnt = blockSize & 3; + if (cnt > 0) + { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + mve_pred16_t p0 = vctp32q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + vstrwq_p_f32(partial_accu_ptr, vecAcc0,p0); + } + + int localTaps = numTaps - FIR_F32_MAX_COEF_BLK; + int sample_offset = FIR_F32_MAX_COEF_BLK; + while (localTaps > FIR_F32_MAX_COEF_BLK) { + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + c4 = *pCoeffs++; + c5 = *pCoeffs++; + c6 = *pCoeffs++; + c7 = *pCoeffs++; + + partial_accu_ptr = S->pState; + pSamples = pState + sample_offset; + int cnt = blockSize >> 2; + while(cnt > 0) { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + pSamples += 4; + vecAcc0 += vld1q_f32(partial_accu_ptr); + vst1q(partial_accu_ptr, vecAcc0); + cnt--; + partial_accu_ptr += 4; + } + + cnt = blockSize & 3; + if (cnt > 0) { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + mve_pred16_t p0 = vctp32q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + vecAcc0 += vld1q_f32(partial_accu_ptr); + vstrwq_p_f32(partial_accu_ptr, vecAcc0,p0); + } + + localTaps -= FIR_F32_MAX_COEF_BLK; + sample_offset += FIR_F32_MAX_COEF_BLK; + } + + pSamples = pState + sample_offset; + + if (localTaps > 4) { + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + c4 = *pCoeffs++; + c5 = *pCoeffs++; + c6 = *pCoeffs++; + c7 = *pCoeffs++; + pOutput = pDst; + + partial_accu_ptr = S->pState; + cnt = blockSize >> 2; + while(cnt > 0) { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + pSamples += 4; + float32x4_t pap = vld1q_f32(partial_accu_ptr); + vst1q(pOutput, vecAcc0+pap); + cnt--; + partial_accu_ptr += 4; + pOutput += 4; + } + + cnt = blockSize & 3; + if (cnt > 0) { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + mve_pred16_t p0 = vctp32q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + float32x4_t pap = vld1q_f32(partial_accu_ptr); + vstrwq_p_f32(pOutput, vecAcc0+pap,p0); + pOutput += cnt; + } + } + else { + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + pOutput = pDst; + + partial_accu_ptr = S->pState; + cnt = blockSize >> 2; + while(cnt > 0) { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + pSamples += 4; + float32x4_t pap = vld1q_f32(partial_accu_ptr); + vst1q(pOutput, vecAcc0+pap); + cnt--; + partial_accu_ptr += 4; + pOutput += 4; + } + + cnt = blockSize & 3; + if (cnt > 0) { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + mve_pred16_t p0 = vctp32q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + float32x4_t pap = vld1q_f32(partial_accu_ptr); + vstrwq_p_f32(pOutput, vecAcc0+pap,p0); + pOutput += cnt; + } + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pRefStatePtr[blockSize]; + pTempDest = pRefStatePtr; + + blkCnt = numTaps >> 2; + while (blkCnt > 0) + { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 4; + pTempDest += 4; + blkCnt--; + } + blkCnt = numTaps & 3; + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_f32(pTempDest, vld1q(pTempSrc), p0); + } +} + +#else +#if defined(ARM_MATH_NEON) + +void arm_fir_f32( +const arm_fir_instance_f32 * S, +const float32_t * pSrc, +float32_t * pDst, +uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px; /* Temporary pointers for state buffer */ + const float32_t *pb; /* Temporary pointers for coefficient buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + + float32x4_t accv0,accv1,samples0,samples1,x0,x1,x2,xa,xb,b; + float32_t acc; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* Loop unrolling */ + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + /* Copy 8 samples at a time into state buffers */ + samples0 = vld1q_f32(pSrc); + vst1q_f32(pStateCurnt,samples0); + + pStateCurnt += 4; + pSrc += 4 ; + + samples1 = vld1q_f32(pSrc); + vst1q_f32(pStateCurnt,samples1); + + pStateCurnt += 4; + pSrc += 4 ; + + /* Set the accumulators to zero */ + accv0 = vdupq_n_f32(0); + accv1 = vdupq_n_f32(0); + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Loop unroling */ + i = numTaps >> 2; + + /* Perform the multiply-accumulates */ + x0 = vld1q_f32(px); + x1 = vld1q_f32(px + 4); + + while(i > 0) + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + x2 = vld1q_f32(px + 8); + b = vld1q_f32(pb); + xa = x0; + xb = x1; + accv0 = vmlaq_n_f32(accv0,xa,vgetq_lane_f32(b, 0)); + accv1 = vmlaq_n_f32(accv1,xb,vgetq_lane_f32(b, 0)); + + xa = vextq_f32(x0,x1,1); + xb = vextq_f32(x1,x2,1); + + accv0 = vmlaq_n_f32(accv0,xa,vgetq_lane_f32(b, 1)); + accv1 = vmlaq_n_f32(accv1,xb,vgetq_lane_f32(b, 1)); + + xa = vextq_f32(x0,x1,2); + xb = vextq_f32(x1,x2,2); + + accv0 = vmlaq_n_f32(accv0,xa,vgetq_lane_f32(b, 2)); + accv1 = vmlaq_n_f32(accv1,xb,vgetq_lane_f32(b, 2)); + + xa = vextq_f32(x0,x1,3); + xb = vextq_f32(x1,x2,3); + + accv0 = vmlaq_n_f32(accv0,xa,vgetq_lane_f32(b, 3)); + accv1 = vmlaq_n_f32(accv1,xb,vgetq_lane_f32(b, 3)); + + pb += 4; + x0 = x1; + x1 = x2; + px += 4; + i--; + + } + + /* Tail */ + i = numTaps & 3; + x2 = vld1q_f32(px + 8); + + /* Perform the multiply-accumulates */ + switch(i) + { + case 3: + { + accv0 = vmlaq_n_f32(accv0,x0,*pb); + accv1 = vmlaq_n_f32(accv1,x1,*pb); + + pb++; + + xa = vextq_f32(x0,x1,1); + xb = vextq_f32(x1,x2,1); + + accv0 = vmlaq_n_f32(accv0,xa,*pb); + accv1 = vmlaq_n_f32(accv1,xb,*pb); + + pb++; + + xa = vextq_f32(x0,x1,2); + xb = vextq_f32(x1,x2,2); + + accv0 = vmlaq_n_f32(accv0,xa,*pb); + accv1 = vmlaq_n_f32(accv1,xb,*pb); + + } + break; + case 2: + { + accv0 = vmlaq_n_f32(accv0,x0,*pb); + accv1 = vmlaq_n_f32(accv1,x1,*pb); + + pb++; + + xa = vextq_f32(x0,x1,1); + xb = vextq_f32(x1,x2,1); + + accv0 = vmlaq_n_f32(accv0,xa,*pb); + accv1 = vmlaq_n_f32(accv1,xb,*pb); + + } + break; + case 1: + { + + accv0 = vmlaq_n_f32(accv0,x0,*pb); + accv1 = vmlaq_n_f32(accv1,x1,*pb); + + } + break; + default: + break; + } + + /* The result is stored in the destination buffer. */ + vst1q_f32(pDst,accv0); + pDst += 4; + vst1q_f32(pDst,accv1); + pDst += 4; + + /* Advance state pointer by 8 for the next 8 samples */ + pState = pState + 8; + + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc = 0.0f; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + do + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + acc += *px++ * *pb++; + i--; + + } while (i > 0U); + + /* The result is stored in the destination buffer. */ + *pDst++ = acc; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the starting of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy numTaps number of values */ + tapCnt = numTaps - 1U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} +#else +void arm_fir_f32( + const arm_fir_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px; /* Temporary pointer for state buffer */ + const float32_t *pb; /* Temporary pointer for coefficient buffer */ + float32_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t acc1, acc2, acc3, acc4, acc5, acc6, acc7; /* Accumulators */ + float32_t x0, x1, x2, x3, x4, x5, x6, x7; /* Temporary variables to hold state values */ + float32_t c0; /* Temporary variable to hold coefficient value */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 8 output values simultaneously. + * The variables acc0 ... acc7 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + acc4 = 0.0f; + acc5 = 0.0f; + acc6 = 0.0f; + acc7 = 0.0f; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* This is separated from the others to avoid + * a call to __aeabi_memmove which would be slower + */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Read the first 7 samples from the state buffer: x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + x3 = *px++; + x4 = *px++; + x5 = *px++; + x6 = *px++; + + /* Loop unrolling: process 8 taps at a time. */ + tapCnt = numTaps >> 3U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample */ + x7 = *(px++); + + /* acc0 += b[numTaps-1] * x[n-numTaps] */ + acc0 += x0 * c0; + + /* acc1 += b[numTaps-1] * x[n-numTaps-1] */ + acc1 += x1 * c0; + + /* acc2 += b[numTaps-1] * x[n-numTaps-2] */ + acc2 += x2 * c0; + + /* acc3 += b[numTaps-1] * x[n-numTaps-3] */ + acc3 += x3 * c0; + + /* acc4 += b[numTaps-1] * x[n-numTaps-4] */ + acc4 += x4 * c0; + + /* acc1 += b[numTaps-1] * x[n-numTaps-5] */ + acc5 += x5 * c0; + + /* acc2 += b[numTaps-1] * x[n-numTaps-6] */ + acc6 += x6 * c0; + + /* acc3 += b[numTaps-1] * x[n-numTaps-7] */ + acc7 += x7 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample */ + x0 = *(px++); + + /* Perform the multiply-accumulate */ + acc0 += x1 * c0; + acc1 += x2 * c0; + acc2 += x3 * c0; + acc3 += x4 * c0; + acc4 += x5 * c0; + acc5 += x6 * c0; + acc6 += x7 * c0; + acc7 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-5] sample */ + x1 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x2 * c0; + acc1 += x3 * c0; + acc2 += x4 * c0; + acc3 += x5 * c0; + acc4 += x6 * c0; + acc5 += x7 * c0; + acc6 += x0 * c0; + acc7 += x1 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x3 * c0; + acc1 += x4 * c0; + acc2 += x5 * c0; + acc3 += x6 * c0; + acc4 += x7 * c0; + acc5 += x0 * c0; + acc6 += x1 * c0; + acc7 += x2 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x3 = *(px++); + /* Perform the multiply-accumulates */ + acc0 += x4 * c0; + acc1 += x5 * c0; + acc2 += x6 * c0; + acc3 += x7 * c0; + acc4 += x0 * c0; + acc5 += x1 * c0; + acc6 += x2 * c0; + acc7 += x3 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x4 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x5 * c0; + acc1 += x6 * c0; + acc2 += x7 * c0; + acc3 += x0 * c0; + acc4 += x1 * c0; + acc5 += x2 * c0; + acc6 += x3 * c0; + acc7 += x4 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x5 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x6 * c0; + acc1 += x7 * c0; + acc2 += x0 * c0; + acc3 += x1 * c0; + acc4 += x2 * c0; + acc5 += x3 * c0; + acc6 += x4 * c0; + acc7 += x5 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x6 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x7 * c0; + acc1 += x0 * c0; + acc2 += x1 * c0; + acc3 += x2 * c0; + acc4 += x3 * c0; + acc5 += x4 * c0; + acc6 += x5 * c0; + acc7 += x6 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = numTaps % 0x8U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x7 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + acc4 += x4 * c0; + acc5 += x5 * c0; + acc6 += x6 * c0; + acc7 += x7 * c0; + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + x2 = x3; + x3 = x4; + x4 = x5; + x5 = x6; + x6 = x7; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by 8 to process the next group of 8 samples */ + pState = pState + 8; + + /* The results in the 8 accumulators, store in the destination buffer. */ + *pDst++ = acc0; + *pDst++ = acc1; + *pDst++ = acc2; + *pDst++ = acc3; + *pDst++ = acc4; + *pDst++ = acc5; + *pDst++ = acc6; + *pDst++ = acc7; + + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x8U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0.0f; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + while (i > 0U) + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + acc0 += *px++ * *pb++; + + i--; + } + + /* Store result in destination buffer. */ + *pDst++ = acc0; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** +* @} end of FIR group +*/ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f64.c new file mode 100644 index 00000000..62e7e998 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f64.c @@ -0,0 +1,129 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_f64.c + * Description: Floating-point FIR filter processing function + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for floating-point FIR filter. + @param[in] S points to an instance of the floating-point FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +void arm_fir_f64( + const arm_fir_instance_f64 * S, + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + float64_t *pState = S->pState; /* State pointer */ + const float64_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float64_t *pStateCurnt; /* Points to the current sample of the state */ + float64_t *px; /* Temporary pointer for state buffer */ + const float64_t *pb; /* Temporary pointer for coefficient buffer */ + float64_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0.; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + while (i > 0U) + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + acc0 += *px++ * *pb++; + + i--; + } + + /* Store result in destination buffer. */ + *pDst++ = acc0; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** +* @} end of FIR group +*/ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c new file mode 100644 index 00000000..ccd3ed8e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c @@ -0,0 +1,332 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_fast_q15.c + * Description: Q15 Fast FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for the Q15 FIR filter (fast version). + @param[in] S points to an instance of the Q15 FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. + The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result. + + @remark + Refer to \ref arm_fir_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure. + Use function \ref arm_fir_init_q15() to initialize the filter structure. + */ + +void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t acc0; /* Accumulators */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, c0; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */ + px = pState; + + /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */ + pb = pCoeffs; + + /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */ + x0 = read_q15x2_ia (&px); + + /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */ + x2 = read_q15x2_ia (&px); + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numTaps-(numTaps%4) coefficients. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */ + acc0 = __SMLAD(x0, c0, acc0); + + /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */ + acc2 = __SMLAD(x2, c0, acc2); + + /* pack x[n-N-1] and x[n-N-2] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* Read state x[n-N-4], x[n-N-5] */ + x0 = read_q15x2_ia (&px); + + /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */ + acc1 = __SMLADX(x1, c0, acc1); + + /* pack x[n-N-3] and x[n-N-4] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x0, x2, 0); +#else + x1 = __PKHBT(x2, x0, 0); +#endif + + /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */ + acc3 = __SMLADX(x1, c0, acc3); + + /* Read coefficients b[N-2], b[N-3] */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */ + acc0 = __SMLAD(x2, c0, acc0); + + /* Read state x[n-N-6], x[n-N-7] with offset */ + x2 = read_q15x2_ia (&px); + + /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */ + acc2 = __SMLAD(x0, c0, acc2); + + /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */ + acc1 = __SMLADX(x1, c0, acc1); + + /* pack x[n-N-5] and x[n-N-6] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */ + acc3 = __SMLADX(x1, c0, acc3); + + /* Decrement tap count */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps. + This is always be 2 taps since the filter length is even. */ + if ((numTaps & 0x3U) != 0U) + { + /* Read last two coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD(x0, c0, acc0); + acc2 = __SMLAD(x2, c0, acc2); + + /* pack state variables */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* Read last state variables */ + x0 = read_q15x2 (px); + + /* Perform the multiply-accumulates */ + acc1 = __SMLADX(x1, c0, acc1); + + /* pack state variables */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x0, x2, 0); +#else + x1 = __PKHBT(x2, x0, 0); +#endif + + /* Perform the multiply-accumulates */ + acc3 = __SMLADX(x1, c0, acc3); + } + + /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation. + Then store the 4 outputs in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy two samples into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Use SIMD to hold states and coefficients */ + px = pState; + pb = pCoeffs; + + tapCnt = numTaps >> 1U; + + do + { + acc0 += (q31_t) *px++ * *pb++; + acc0 += (q31_t) *px++ * *pb++; + + tapCnt--; + } + while (tapCnt > 0U); + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of FIR group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c new file mode 100644 index 00000000..bc628c9f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c @@ -0,0 +1,322 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_fast_q31.c + * Description: Processing function for the Q31 Fast FIR filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for the Q31 FIR filter (fast version). + @param[in] S points to an instance of the Q31 structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are added to a 2.30 accumulator. + Finally, the accumulator is saturated and converted to a 1.31 result. + The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. + + @remark + Refer to \ref arm_fir_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. Both the slow and the fast versions use the same instance structure. + Use function \ref arm_fir_init_q31() to initialize the filter structure. + */ + +void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px; /* Temporary pointer for state buffer */ + const q31_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t acc0; /* Accumulators */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the first 3 samples from the state buffer: + * x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Loop unrolling. Process 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numTaps-4 coefficients. */ + while (tapCnt > 0U) + { + /* Read the b[numTaps] coefficient */ + c0 = *pb; + + /* Read x[n-numTaps-3] sample */ + x3 = *px; + + /* acc0 += b[numTaps] * x[n-numTaps] */ + multAcc_32x32_keep32_R(acc0, x0, c0); + + /* acc1 += b[numTaps] * x[n-numTaps-1] */ + multAcc_32x32_keep32_R(acc1, x1, c0); + + /* acc2 += b[numTaps] * x[n-numTaps-2] */ + multAcc_32x32_keep32_R(acc2, x2, c0); + + /* acc3 += b[numTaps] * x[n-numTaps-3] */ + multAcc_32x32_keep32_R(acc3, x3, c0); + + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb + 1U); + + /* Read x[n-numTaps-4] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulates */ + multAcc_32x32_keep32_R(acc0, x1, c0); + multAcc_32x32_keep32_R(acc1, x2, c0); + multAcc_32x32_keep32_R(acc2, x3, c0); + multAcc_32x32_keep32_R(acc3, x0, c0); + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb + 2U); + + /* Read x[n-numTaps-5] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulates */ + multAcc_32x32_keep32_R(acc0, x2, c0); + multAcc_32x32_keep32_R(acc1, x3, c0); + multAcc_32x32_keep32_R(acc2, x0, c0); + multAcc_32x32_keep32_R(acc3, x1, c0); + + /* Read the b[numTaps-3] coefficients */ + c0 = *(pb + 3U); + + /* Read x[n-numTaps-6] sample */ + x2 = *(px + 3U); + + /* Perform the multiply-accumulates */ + multAcc_32x32_keep32_R(acc0, x3, c0); + multAcc_32x32_keep32_R(acc1, x0, c0); + multAcc_32x32_keep32_R(acc2, x1, c0); + multAcc_32x32_keep32_R(acc3, x2, c0); + + /* update coefficient pointer */ + pb += 4U; + px += 4U; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x3 = *(px++); + + /* Perform the multiply-accumulates */ + multAcc_32x32_keep32_R(acc0, x0, c0); + multAcc_32x32_keep32_R(acc1, x1, c0); + multAcc_32x32_keep32_R(acc2, x2, c0); + multAcc_32x32_keep32_R(acc3, x3, c0); + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The results in the 4 accumulators are in 2.30 format. Convert to 1.31 + Then store the 4 outputs in the destination buffer. */ + *pDst++ = (q31_t) (acc0 << 1); + *pDst++ = (q31_t) (acc1 << 1); + *pDst++ = (q31_t) (acc2 << 1); + *pDst++ = (q31_t) (acc3 << 1); + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + do + { + multAcc_32x32_keep32_R(acc0, (*px++), (*pb++)); + i--; + } while (i > 0U); + + /* The result is in 2.30 format. Convert to 1.31 + Then store the output in the destination buffer. */ + *pDst++ = (q31_t) (acc0 << 1); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} +/** + @} end of FIR group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f16.c new file mode 100644 index 00000000..34913432 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f16.c @@ -0,0 +1,105 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_init_f16.c + * Description: Floating-point FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the floating-point FIR filter. + @param[in,out] S points to an instance of the floating-point FIR filter structure + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficients buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of samples processed per call + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: +
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+  
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 samples (except for Helium - see below), where blockSize is the number of input samples processed by each call to arm_fir_f16(). + @par Initialization of Helium version + For Helium version the array of coefficients must be a multiple of 4 (4a) even if less + then 4a coefficients are defined in the FIR. The additional coefficients + (4a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + + + @par Helium state buffer + The state buffer must contain some additional temporary data + used during the computation but which is not the state of the FIR. + The first 8*ceil(blockSize/8) samples are temporary data. + The remaining samples are the state of the FIR filter. + So the state buffer has size numTaps + 8*ceil(blockSize/8) + blockSize - 1 + + */ + +void arm_fir_init_f16( + arm_fir_instance_f16 * S, + uint16_t numTaps, + const float16_t * pCoeffs, + float16_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + memset(pState, 0, (numTaps + (blockSize - 1U) + ROUND_UP(blockSize, 8)) * sizeof(float16_t)); +#else + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float16_t)); +#endif + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c new file mode 100644 index 00000000..e0a58755 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c @@ -0,0 +1,99 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_init_f32.c + * Description: Floating-point FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the floating-point FIR filter. + @param[in,out] S points to an instance of the floating-point FIR filter structure + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficients buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of samples processed per call + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: +
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+  
+ @par + pState points to the array of state variables and some working memory for the Helium version. + pState is of length numTaps+blockSize-1 samples (except for Helium - see below), where blockSize is the number of input samples processed by each call to arm_fir_f32(). + @par Initialization of Helium version + For Helium version the array of coefficients must be a multiple of 4 (4a) even if less + then 4a coefficients are defined in the FIR. The additional coefficients + (4a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + + @par Helium state buffer + The state buffer must contain some additional temporary data + used during the computation but which is not the state of the FIR. + The first blockSize samples are temporary data. + The remaining samples are the state of the FIR filter. + So the state buffer has size numTaps + 2 * blockSize - 1 + + */ + +void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + memset(pState, 0, (numTaps + (blockSize - 1U) + blockSize) * sizeof(float32_t)); +#else + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float32_t)); +#endif + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f64.c new file mode 100644 index 00000000..8c578b50 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f64.c @@ -0,0 +1,95 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_init_f64.c + * Description: Floating-point FIR filter initialization function + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the floating-point FIR filter. + @param[in,out] S points to an instance of the floating-point FIR filter structure + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficients buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of samples processed per call + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: +
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+  
+ @par + pState points to the array of state variables and some working memory for the Helium version. + pState is of length numTaps+blockSize-1 samples (except for Helium - see below), where blockSize is the number of input samples processed by each call to arm_fir_f32(). + @par Initialization of Helium version + For Helium version the array of coefficients must be a multiple of 4 (4a) even if less + then 4a coefficients are defined in the FIR. The additional coefficients + (4a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + + @par Helium state buffer + The state buffer must contain some additional temporary data + used during the computation but which is not the state of the FIR. + The first blockSize samples are temporary data. + The remaining samples are the state of the FIR filter. + So the state buffer has size numTaps + 2 * blockSize - 1 + + */ + +void arm_fir_init_f64( + arm_fir_instance_f64 * S, + uint16_t numTaps, + const float64_t * pCoeffs, + float64_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float64_t)); + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c new file mode 100644 index 00000000..3682fb09 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c @@ -0,0 +1,145 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_init_q15.c + * Description: Q15 FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the Q15 FIR filter. + @param[in,out] S points to an instance of the Q15 FIR filter structure. + @param[in] numTaps number of filter coefficients in the filter. Must be even and greater than or equal to 4. + @param[in] pCoeffs points to the filter coefficients buffer. + @param[in] pState points to the state buffer. + @param[in] blockSize number of samples processed per call. + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : numTaps is not greater than or equal to 4 and even + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: +
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+  
+ Note that numTaps must be even and greater than or equal to 4. + To implement an odd length filter simply increase numTaps by 1 and set the last coefficient to zero. + For example, to implement a filter with numTaps=3 and coefficients +
+      {0.3, -0.8, 0.3}
+  
+ set numTaps=4 and use the coefficients: +
+      {0.3, -0.8, 0.3, 0}.
+  
+ Similarly, to implement a two point filter +
+      {0.3, -0.3}
+  
+ set numTaps=4 and use the coefficients: +
+      {0.3, -0.3, 0, 0}.
+  
+ pState points to the array of state variables. + pState is of length numTaps+blockSize, when running on Cortex-M4 and Cortex-M3 and is of length numTaps+blockSize-1, when running on Cortex-M0 where blockSize is the number of input samples processed by each call to arm_fir_q15(). + + @par Initialization of Helium version + For Helium version the array of coefficients must be a multiple of 8 (8a) even if less + then 8a coefficients are defined in the FIR. The additional coefficients + (8a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + */ + +arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize) +{ + arm_status status; + +#if defined (ARM_MATH_DSP) + + /* The Number of filter coefficients in the filter must be even and at least 4 */ + if (numTaps & 0x1U) + { + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear the state buffer. The size is always (blockSize + numTaps ) */ + memset(pState, 0, (numTaps + (blockSize)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = ARM_MATH_SUCCESS; + } + + return (status); + +#else + + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = ARM_MATH_SUCCESS; + + return (status); + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + @} end of FIR group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c new file mode 100644 index 00000000..96d1fdde --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c @@ -0,0 +1,100 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_init_q31.c + * Description: Q31 FIR filter initialization function. + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the Q31 FIR filter. + @param[in,out] S points to an instance of the Q31 FIR filter structure + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficients buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of samples processed + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: +
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+  
+ pState points to the array of state variables. + pState is of length numTaps+blockSize-1 samples (except for Helium - see below), where blockSize is the number of input samples processed by each call to arm_fir_q31(). + + @par Initialization of Helium version + For Helium version the array of coefficients must be a multiple of 4 (4a) even if less + then 4a coefficients are defined in the FIR. The additional coefficients + (4a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + + @par Helium state buffer + The state buffer must contain some additional temporary data + used during the computation but which is not the state of the FIR. + The first 2*4*ceil(blockSize/4) samples are temporary data. + The remaining samples are the state of the FIR filter. + So the state buffer has size numTaps + 8*ceil(blockSize/4) + blockSize - 1 + + */ + +void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + memset(pState, 0, (numTaps + (blockSize - 1U) + 2*ROUND_UP(blockSize, 4)) * sizeof(q31_t)); + #else + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t)); + #endif + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c new file mode 100644 index 00000000..1ad05a55 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c @@ -0,0 +1,90 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_init_q7.c + * Description: Q7 FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the Q7 FIR filter. + @param[in,out] S points to an instance of the Q7 FIR filter structure + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficients buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of samples processed + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: +
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+  
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q7(). + + @par Initialization of Helium version + For Helium version the array of coefficients must be a multiple of 16 (16a) even if less + then 16a coefficients are defined in the FIR. The additional coefficients + (16a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + + */ + +void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q7_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c new file mode 100644 index 00000000..b6a6ecb7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c @@ -0,0 +1,1252 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_f32.c + * Description: Floating-point FIR interpolation sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @defgroup FIR_Interpolate Finite Impulse Response (FIR) Interpolator + + These functions combine an upsampler (zero stuffer) and an FIR filter. + They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images. + Conceptually, the functions are equivalent to the block diagram below: + \image html FIRInterpolator.gif "Components included in the FIR Interpolator functions" + After upsampling by a factor of L, the signal should be filtered by a lowpass filter with a normalized + cutoff frequency of 1/L in order to eliminate high frequency copies of the spectrum. + The user of the function is responsible for providing the filter coefficients. + + The FIR interpolator functions provided in the CMSIS DSP Library combine the upsampler and FIR filter in an efficient manner. + The upsampler inserts L-1 zeros between each sample. + Instead of multiplying by these zero values, the FIR filter is designed to skip them. + This leads to an efficient implementation without any wasted effort. + The functions operate on blocks of input and output data. + pSrc points to an array of blockSize input values and + pDst points to an array of blockSize*L output values. + + The library provides separate functions for Q15, Q31, and floating-point data types. + + @par Algorithm + The functions use a polyphase filter structure: +
+      y[n] = b[0] * x[n] + b[L]   * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]
+      y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]
+      ...
+      y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]
+  
+ This approach is more efficient than straightforward upsample-then-filter algorithms. + With this method the computation is reduced by a factor of 1/L when compared to using a standard FIR filter. + @par + pCoeffs points to a coefficient array of size numTaps. + numTaps must be a multiple of the interpolation factor L and this is checked by the + initialization functions. + Internally, the function divides the FIR filter's impulse response into shorter filters of length + phaseLength=numTaps/L. + Coefficients are stored in time reversed order. +
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+  
+ @par + pState points to a state array of size blockSize + phaseLength - 1. + Samples in the state buffer are stored in the order: +
+     {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}
+  
+ @par + The state variables are updated after each block of data is processed, the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable array should be allocated separately. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + - Checks to make sure that the length of the filter is a multiple of the interpolation factor. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + L (interpolation factor), pCoeffs, phaseLength (numTaps / L), pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + The code below statically initializes each of the 3 different data type filter instance structures +
+      arm_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};
+      arm_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};
+      arm_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};
+  
+ @par + where L is the interpolation factor; phaseLength=numTaps/L is the + length of each of the shorter FIR filters used internally, + pCoeffs is the address of the coefficient buffer; + pState is the address of the state buffer. + Be sure to set the values in the state buffer to zeros when doing static initialization. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the FIR interpolate filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Processing function for floating-point FIR interpolator. + @param[in] S points to an instance of the floating-point FIR interpolator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +static void arm_fir_interpolate2_f32_mve( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + const float32_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */ + uint32_t tapCnt; + uint32_t blkCnt; /* Loop counters */ + uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t strides[4] = { 0, 1 * 2, 2 * 2, 3 * 2 }; + uint32x4_t vec_strides0 = vld1q_u32(strides); + uint32x4_t vec_strides1 = vec_strides0 + 1; + f32x4_t acc0, acc1; + + /* + * S->pState buffer contains previous frame (phaseLen - 1) samples + * pStateCurnt points to the location where the new input data should be written + */ + pStateCurnt = S->pState + (phaseLen - 1U); + /* + * Total number of intput samples + */ + blkCnt = blockSize; + /* + * Loop over the blockSize. + */ + while (blkCnt > 0U) + { + /* + * Copy new input sample into the state buffer + */ + *pStateCurnt++ = *pSrc++; + /* + * Initialize state pointer + */ + ptr1 = pState; + + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs; + + tapCnt = phaseLen >> 2; + while (tapCnt > 0U) + { + f32x4_t vecCoef, vecState; + + vecState = vldrwq_f32(ptr1); + + vecCoef = vldrwq_gather_shifted_offset_f32(ptr2, vec_strides1); + acc1 = vfmaq_f32(acc1, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_f32(ptr2, vec_strides0); + acc0 = vfmaq_f32(acc0, vecState, vecCoef); + + ptr2 += 4 * 2; + ptr1 += 4; + /* + * Decrement the loop counter + */ + tapCnt--; + } + + tapCnt = phaseLen & 3; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + f32x4_t vecCoef, vecState; + + vecState = vldrwq_z_f32(ptr1, p0); + + vecCoef = vldrwq_gather_shifted_offset_z_f32(ptr2, vec_strides1, p0); + acc1 = vfmaq_f32(acc1, vecState, vecCoef); + vecCoef = vldrwq_gather_shifted_offset_z_f32(ptr2, vec_strides0, p0); + acc0 = vfmaq_f32(acc0, vecState, vecCoef); + + } + *pDst++ = vecAddAcrossF32Mve(acc1); + *pDst++ = vecAddAcrossF32Mve(acc0); + + /* + * Advance the state pointer by 1 + * * to process the next group of interpolation factor number samples + */ + pState = pState + 1; + /* + * Decrement the loop counter + */ + blkCnt--; + } + + /* + * Processing is complete. + * ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + * ** This prepares the state buffer for the next function call. + */ + + /* + * Points to the start of the state buffer + */ + pStateCurnt = S->pState; + blkCnt = (phaseLen - 1U) >> 2; + while (blkCnt > 0U) + { + vst1q(pStateCurnt, vldrwq_f32(pState)); + pState += 4; + pStateCurnt += 4; + blkCnt--; + } + blkCnt = (phaseLen - 1U) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_f32(pStateCurnt, vldrwq_f32(pState), p0); + } +} + +void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + const float32_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */ + uint32_t tapCnt; + uint32_t i, blkCnt; /* Loop counters */ + uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t strides[4] = { 0, 1 * S->L, 2 * S->L, 3 * S->L }; + uint32_t stridesM[4] = { 4, 3, 2, 1 }; + uint32x4_t vec_stridesM = vld1q_u32(stridesM); + uint32x4_t vec_strides = vld1q_u32(strides); + f32x4_t acc; + + + if ( S->L == 2 ) { + arm_fir_interpolate2_f32_mve(S, pSrc, pDst, blockSize); + return; + } + + /* + * S->pState buffer contains previous frame (phaseLen - 1) samples + */ + /* + * pStateCurnt points to the location where the new input data should be written + */ + pStateCurnt = S->pState + (phaseLen - 1U); + /* + * Total number of intput samples + */ + blkCnt = blockSize; + /* + * Loop over the blockSize. + */ + while (blkCnt > 0U) + { + /* + * Copy new input sample into the state buffer + */ + *pStateCurnt++ = *pSrc++; + /* + * Loop over the Interpolation factor. + */ + i = S->L; + while (i > 0U) + { + /* + * Initialize state pointer + */ + ptr1 = pState; + if (i >= 4) + { + float32_t state0, state1, state2, state3; + acc = vdupq_n_f32(0.0f); + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U) - 4; + tapCnt = phaseLen >> 2; + while (tapCnt > 0U) + { + f32x4_t vecCoef; + const float32_t *pCoef = ptr2; + + state0 = ptr1[0]; + state1 = ptr1[1]; + state2 = ptr1[2]; + state3 = ptr1[3]; + ptr1 += 4; + + vecCoef = vldrwq_gather_shifted_offset_f32(pCoef, vec_stridesM); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state0); + + vecCoef = vldrwq_gather_shifted_offset_f32(pCoef, vec_stridesM); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state1); + + vecCoef = vldrwq_gather_shifted_offset_f32(pCoef, vec_stridesM); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state2); + + vecCoef = vldrwq_gather_shifted_offset_f32(pCoef, vec_stridesM); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state3); + + ptr2 = ptr2 + 4 * S->L; + /* + * Decrement the loop counter + */ + tapCnt--; + } + + tapCnt = phaseLen & 3; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + f32x4_t vecCoef; + const float32_t *pCoef = ptr2; + + state0 = ptr1[0]; + state1 = ptr1[1]; + state2 = ptr1[2]; + state3 = ptr1[3]; + + vecCoef = vldrwq_gather_shifted_offset_z_f32(pCoef, vec_stridesM, p0); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state0); + + vecCoef = vldrwq_gather_shifted_offset_z_f32(pCoef, vec_stridesM, p0); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state1); + + vecCoef = vldrwq_gather_shifted_offset_z_f32(pCoef, vec_stridesM, p0); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state2); + + vecCoef = vldrwq_gather_shifted_offset_z_f32(pCoef, vec_stridesM, p0); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state3); + } + + vst1q(pDst, acc); + pDst += 4; + i -= 4; + } + else + { + acc = vdupq_n_f32(0.0f); + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U); + + tapCnt = phaseLen >> 2; + while (tapCnt > 0U) + { + f32x4_t vecCoef, vecState; + + vecState = vldrwq_f32(ptr1); + ptr1 += 4; + + vecCoef = vldrwq_gather_shifted_offset_f32(ptr2, vec_strides); + ptr2 += 4 * S->L; + acc = vfmaq_f32(acc, vecState, vecCoef); + /* + * Decrement the loop counter + */ + tapCnt--; + } + + tapCnt = phaseLen & 3; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + f32x4_t vecCoef, vecState; + + vecState = vldrwq_z_f32(ptr1, p0); + + vecCoef = vldrwq_gather_shifted_offset_z_f32(ptr2, vec_strides, p0); + acc = vfmaq_f32(acc, vecState, vecCoef); + } + *pDst++ = vecAddAcrossF32Mve(acc); + /* + * Decrement the loop counter + */ + i--; + } + } + + /* + * Advance the state pointer by 1 + * * to process the next group of interpolation factor number samples + */ + pState = pState + 1; + /* + * Decrement the loop counter + */ + blkCnt--; + } + + /* + * Processing is complete. + * ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + * ** This prepares the state buffer for the next function call. + */ + + /* + * Points to the start of the state buffer + */ + pStateCurnt = S->pState; + blkCnt = (phaseLen - 1U) >> 2; + while (blkCnt > 0U) + { + vst1q(pStateCurnt, vldrwq_f32(pState)); + pState += 4; + pStateCurnt += 4; + blkCnt--; + } + blkCnt = (phaseLen - 1U) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_f32(pStateCurnt, vldrwq_f32(pState), p0); + } +} + +#else +#if defined(ARM_MATH_NEON) +void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *ptr1; /* Temporary pointers for state buffer */ + const float32_t *ptr2; /* Temporary pointers for coefficient buffer */ + float32_t sum0; /* Accumulators */ + float32_t c0; /* Temporary variables to hold state and coefficient values */ + uint32_t i, blkCnt, j; /* Loop counters */ + uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */ + uint32_t blkCntN4; + float32_t c1, c2, c3; + + float32x4_t sum0v; + float32x4_t accV0,accV1; + float32x4_t x0v,x1v,x2v,xa,xb; + float32x2_t tempV; + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + (phaseLen - 1U); + + /* Initialise blkCnt */ + blkCnt = blockSize >> 3; + blkCntN4 = blockSize & 7; + + /* Loop unrolling */ + while (blkCnt > 0U) + { + /* Copy new input samples into the state buffer */ + sum0v = vld1q_f32(pSrc); + vst1q_f32(pStateCurnt,sum0v); + pSrc += 4; + pStateCurnt += 4; + + sum0v = vld1q_f32(pSrc); + vst1q_f32(pStateCurnt,sum0v); + pSrc += 4; + pStateCurnt += 4; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = (S->L); + + while (i > 0U) + { + /* Set accumulator to zero */ + accV0 = vdupq_n_f32(0.0); + accV1 = vdupq_n_f32(0.0); + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + ** Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + x0v = vld1q_f32(ptr1); + x1v = vld1q_f32(ptr1 + 4); + + while (tapCnt > 0U) + { + /* Read the input samples */ + x2v = vld1q_f32(ptr1 + 8); + + /* Read the coefficients */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + accV0 = vmlaq_n_f32(accV0,x0v,c0); + accV1 = vmlaq_n_f32(accV1,x1v,c0); + + /* Read the coefficients, inputs and perform multiply-accumulate */ + c1 = *(ptr2 + S->L); + + xa = vextq_f32(x0v,x1v,1); + xb = vextq_f32(x1v,x2v,1); + + accV0 = vmlaq_n_f32(accV0,xa,c1); + accV1 = vmlaq_n_f32(accV1,xb,c1); + + /* Read the coefficients, inputs and perform multiply-accumulate */ + c2 = *(ptr2 + S->L * 2); + + xa = vextq_f32(x0v,x1v,2); + xb = vextq_f32(x1v,x2v,2); + + accV0 = vmlaq_n_f32(accV0,xa,c2); + accV1 = vmlaq_n_f32(accV1,xb,c2); + + /* Read the coefficients, inputs and perform multiply-accumulate */ + c3 = *(ptr2 + S->L * 3); + + xa = vextq_f32(x0v,x1v,3); + xb = vextq_f32(x1v,x2v,3); + + accV0 = vmlaq_n_f32(accV0,xa,c3); + accV1 = vmlaq_n_f32(accV1,xb,c3); + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += 4 * S->L; + ptr1 += 4; + x0v = x1v; + x1v = x2v; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + x2v = vld1q_f32(ptr1 + 8); + + switch (tapCnt) + { + case 3: + c0 = *(ptr2); + accV0 = vmlaq_n_f32(accV0,x0v,c0); + accV1 = vmlaq_n_f32(accV1,x1v,c0); + ptr2 += S->L; + + c0 = *(ptr2); + + xa = vextq_f32(x0v,x1v,1); + xb = vextq_f32(x1v,x2v,1); + + accV0 = vmlaq_n_f32(accV0,xa,c0); + accV1 = vmlaq_n_f32(accV1,xb,c0); + ptr2 += S->L; + + c0 = *(ptr2); + + xa = vextq_f32(x0v,x1v,2); + xb = vextq_f32(x1v,x2v,2); + + accV0 = vmlaq_n_f32(accV0,xa,c0); + accV1 = vmlaq_n_f32(accV1,xb,c0); + ptr2 += S->L; + + break; + + case 2: + c0 = *(ptr2); + accV0 = vmlaq_n_f32(accV0,x0v,c0); + accV1 = vmlaq_n_f32(accV1,x1v,c0); + ptr2 += S->L; + + c0 = *(ptr2); + + xa = vextq_f32(x0v,x1v,1); + xb = vextq_f32(x1v,x2v,1); + + accV0 = vmlaq_n_f32(accV0,xa,c0); + accV1 = vmlaq_n_f32(accV1,xb,c0); + ptr2 += S->L; + + break; + + case 1: + c0 = *(ptr2); + accV0 = vmlaq_n_f32(accV0,x0v,c0); + accV1 = vmlaq_n_f32(accV1,x1v,c0); + ptr2 += S->L; + + break; + + default: + break; + + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst = vgetq_lane_f32(accV0, 0); + *(pDst + S->L) = vgetq_lane_f32(accV0, 1); + *(pDst + 2 * S->L) = vgetq_lane_f32(accV0, 2); + *(pDst + 3 * S->L) = vgetq_lane_f32(accV0, 3); + + *(pDst + 4 * S->L) = vgetq_lane_f32(accV1, 0); + *(pDst + 5 * S->L) = vgetq_lane_f32(accV1, 1); + *(pDst + 6 * S->L) = vgetq_lane_f32(accV1, 2); + *(pDst + 7 * S->L) = vgetq_lane_f32(accV1, 3); + + pDst++; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 8; + + pDst += S->L * 7; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + + while (blkCntN4 > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum0v = vdupq_n_f32(0.0); + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + ** Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + while (tapCnt > 0U) + { + /* Read the coefficient */ + x1v = vsetq_lane_f32(*(ptr2),x1v,0); + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Read the input sample */ + x0v = vld1q_f32(ptr1); + ptr1 += 4; + + /* Read the coefficient */ + x1v = vsetq_lane_f32(*(ptr2),x1v,1); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Read the coefficient */ + x1v = vsetq_lane_f32(*(ptr2),x1v,2); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Read the coefficient */ + x1v = vsetq_lane_f32(*(ptr2),x1v,3); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + sum0v = vmlaq_f32(sum0v,x0v,x1v); + + /* Decrement the loop counter */ + tapCnt--; + } + + tempV = vpadd_f32(vget_low_f32(sum0v),vget_high_f32(sum0v)); + sum0 = vget_lane_f32(tempV, 0) + vget_lane_f32(tempV, 1); + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += *(ptr1++) * (*ptr2); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = sum0; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCntN4--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + tapCnt = (phaseLen - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + sum0v = vld1q_f32(pState); + vst1q_f32(pStateCurnt,sum0v); + pState += 4; + pStateCurnt += 4; + + /* Decrement the loop counter */ + tapCnt--; + } + + tapCnt = (phaseLen - 1U) % 0x04U; + + /* copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} +#else + +void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCur; /* Points to the current sample of the state */ + float32_t *ptr1; /* Temporary pointer for state buffer */ + const float32_t *ptr2; /* Temporary pointer for coefficient buffer */ + float32_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t j; + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t acc0, acc1, acc2, acc3; + float32_t x0, x1, x2, x3; + float32_t c0, c1, c2, c3; +#endif + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = (S->L); + + while (i > 0U) + { + /* Set accumulator to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + x0 = *(ptr1++); + x1 = *(ptr1++); + x2 = *(ptr1++); + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Read the coefficient */ + c1 = *(ptr2 + S->L); + + /* Read the input sample */ + x0 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += x1 * c1; + acc1 += x2 * c1; + acc2 += x3 * c1; + acc3 += x0 * c1; + + /* Read the coefficient */ + c2 = *(ptr2 + S->L * 2); + + /* Read the input sample */ + x1 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += x2 * c2; + acc1 += x3 * c2; + acc2 += x0 * c2; + acc3 += x1 * c2; + + /* Read the coefficient */ + c3 = *(ptr2 + S->L * 3); + + /* Read the input sample */ + x2 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += x3 * c3; + acc1 += x0 * c3; + acc2 += x1 * c3; + acc3 += x2 * c3; + + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += 4 * S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* update states for next sample processing */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *(pDst ) = acc0; + *(pDst + S->L) = acc1; + *(pDst + 2 * S->L) = acc2; + *(pDst + 3 * S->L) = acc3; + + pDst++; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 4; + + pDst += S->L * 3; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0.0f; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = phaseLen >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + sum0 += *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += *ptr1++ * *ptr2; + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = phaseLen % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = phaseLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = sum0; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = (phaseLen - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = (phaseLen - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (phaseLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#else +/* alternate version for CM0_FAMILY */ + + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCur; /* Points to the current sample of the state */ + float32_t *ptr1; /* Temporary pointer for state buffer */ + const float32_t *ptr2; /* Temporary pointer for coefficient buffer */ + float32_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + + /* Total number of intput samples */ + blkCnt = blockSize; + + /* Loop over the blockSize. */ + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0.0f; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (i - 1U); + + /* Loop over the polyPhase length */ + tapCnt = phaseLen; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += *ptr1++ * *ptr2; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = sum0; + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + tapCnt = phaseLen - 1U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of FIR_Interpolate group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c new file mode 100644 index 00000000..67bdff9c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c @@ -0,0 +1,106 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_init_f32.c + * Description: Floating-point FIR interpolator initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Initialization function for the floating-point FIR interpolator. + @param[in,out] S points to an instance of the floating-point FIR interpolator structure + @param[in] L upsample factor + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficient buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : filter length numTaps is not a multiple of the interpolation factor L + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: +
+      {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+  
+ @par + The length of the filter numTaps must be a multiple of the interpolation factor L. + @par + pState points to the array of state variables. + pState is of length (numTaps/L)+blockSize-1 words + where blockSize is the number of input samples processed by each call to arm_fir_interpolate_f32(). + */ + +arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The filter length must be a multiple of the interpolation factor */ + if ((numTaps % L) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign Interpolation factor */ + S->L = L; + + /* Assign polyPhaseLength */ + S->phaseLength = numTaps / L; + + /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */ + memset(pState, 0, (blockSize + ((uint32_t) S->phaseLength - 1U)) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = ARM_MATH_SUCCESS; + } + + return (status); +} + +/** + @} end of FIR_Interpolate group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c new file mode 100644 index 00000000..7436aa43 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c @@ -0,0 +1,106 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_init_q15.c + * Description: Q15 FIR interpolator initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Initialization function for the Q15 FIR interpolator. + @param[in,out] S points to an instance of the Q15 FIR interpolator structure + @param[in] L upsample factor + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficient buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : filter length numTaps is not a multiple of the interpolation factor L + + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: +
+      {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+  
+ The length of the filter numTaps must be a multiple of the interpolation factor L. + @par + pState points to the array of state variables. + pState is of length (numTaps/L)+blockSize-1 words + where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q15(). + */ + +arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The filter length must be a multiple of the interpolation factor */ + if ((numTaps % L) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign Interpolation factor */ + S->L = L; + + /* Assign polyPhaseLength */ + S->phaseLength = numTaps / L; + + /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */ + memset(pState, 0, (blockSize + ((uint32_t) S->phaseLength - 1U)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = ARM_MATH_SUCCESS; + } + + return (status); +} + +/** + @} end of FIR_Interpolate group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c new file mode 100644 index 00000000..15f9e0d3 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c @@ -0,0 +1,105 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_init_q31.c + * Description: Q31 FIR interpolator initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Initialization function for the Q31 FIR interpolator. + @param[in,out] S points to an instance of the Q31 FIR interpolator structure + @param[in] L upsample factor + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficient buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : filter length numTaps is not a multiple of the interpolation factor L + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: +
+      {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+  
+ The length of the filter numTaps must be a multiple of the interpolation factor L. + @par + pState points to the array of state variables. + pState is of length (numTaps/L)+blockSize-1 words + where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q31(). + */ + +arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The filter length must be a multiple of the interpolation factor */ + if ((numTaps % L) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign Interpolation factor */ + S->L = L; + + /* Assign polyPhaseLength */ + S->phaseLength = numTaps / L; + + /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */ + memset(pState, 0, (blockSize + ((uint32_t) S->phaseLength - 1U)) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = ARM_MATH_SUCCESS; + } + + return (status); +} + +/** + @} end of FIR_Interpolate group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c new file mode 100644 index 00000000..523e1557 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c @@ -0,0 +1,774 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_q15.c + * Description: Q15 FIR interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Processing function for the Q15 FIR interpolator. + @param[in] S points to an instance of the Q15 FIR interpolator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + const q15_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */ + + uint32_t i, blkCnt; /* Loop counters */ + uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint16_t strides[8] = { + 0, 1 * S->L, 2 * S->L, 3 * S->L, + 4 * S->L, 5 * S->L, 6 * S->L, 7 * S->L + }; + uint16x8_t vec_strides0 = *(uint16x8_t *) strides; + uint16x8_t vec_strides1 = vec_strides0 + 1; + uint16x8_t vec_strides2 = vec_strides0 + 2; + uint16x8_t vec_strides3 = vec_strides0 + 3; + q15x8_t vecState, vecCoef; + + /* + * S->pState buffer contains previous frame (phaseLen - 1) samples + * pStateCurnt points to the location where the new input data should be written + */ + pStateCurnt = S->pState + ((q15_t) phaseLen - 1); + /* + * Total number of intput samples + */ + blkCnt = blockSize; + /* + * Loop over the blockSize. + */ + while (blkCnt > 0U) + { + /* + * Copy new input sample into the state buffer + */ + *pStateCurnt++ = *pSrc++; + /* + * Loop over the Interpolation factor. + */ + i = S->L; + while (i > 0U) + { + /* + * Initialize state pointer + */ + ptr1 = pState; + if (i >= 4) + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1 - 3U); + + q63_t acc0 = 0LL; + q63_t acc1 = 0LL; + q63_t acc2 = 0LL; + q63_t acc3 = 0LL; + + uint32_t tapCnt = phaseLen >> 3; + while (tapCnt > 0U) + { + vecState = vldrhq_s16(ptr1); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides3); + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides2); + acc1 = vmlaldavaq(acc1, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides1); + acc2 = vmlaldavaq(acc2, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides0); + acc3 = vmlaldavaq(acc3, vecState, vecCoef); + + ptr1 += 8; + ptr2 = ptr2 + S->L * 8; + tapCnt--; + } + tapCnt = phaseLen & 7; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp16q(tapCnt); + + vecState = vldrhq_z_s16(ptr1, p0); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides3, p0); + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides2, p0); + acc1 = vmlaldavaq(acc1, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides1, p0); + acc2 = vmlaldavaq(acc2, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides0, p0); + acc3 = vmlaldavaq(acc3, vecState, vecCoef); + } + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + acc3 = asrl(acc3, 15); + + *pDst++ = (q15_t) __SSAT(acc0, 16); + *pDst++ = (q15_t) __SSAT(acc1, 16); + *pDst++ = (q15_t) __SSAT(acc2, 16); + *pDst++ = (q15_t) __SSAT(acc3, 16); + i -= 4; + } + else if (i >= 3) + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U - 2); + + q63_t acc0 = 0LL; + q63_t acc1 = 0LL; + q63_t acc2 = 0LL; + + uint32_t tapCnt = phaseLen >> 3; + while (tapCnt > 0U) + { + vecState = vldrhq_s16(ptr1); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides2); + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides1); + acc1 = vmlaldavaq(acc1, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides0); + acc2 = vmlaldavaq(acc2, vecState, vecCoef); + + ptr1 += 8; + ptr2 = ptr2 + S->L * 8; + tapCnt--; + } + tapCnt = phaseLen & 7; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp16q(tapCnt); + + vecState = vldrhq_z_s16(ptr1, p0); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides2, p0); + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides1, p0); + acc1 = vmlaldavaq(acc1, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides0, p0); + acc2 = vmlaldavaq(acc2, vecState, vecCoef); + } + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + + *pDst++ = (q15_t) __SSAT(acc0, 16);; + *pDst++ = (q15_t) __SSAT(acc1, 16);; + *pDst++ = (q15_t) __SSAT(acc2, 16);; + i -= 3; + } + else if (i >= 2) + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U - 1); + + q63_t acc0 = 0LL; + q63_t acc1 = 0LL; + + uint32_t tapCnt = phaseLen >> 3; + while (tapCnt > 0U) + { + vecState = vldrhq_s16(ptr1); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides1); + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides0); + acc1 = vmlaldavaq(acc1, vecState, vecCoef); + + ptr1 += 8; + ptr2 = ptr2 + S->L * 8; + tapCnt--; + } + tapCnt = phaseLen & 7; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp16q(tapCnt); + + vecState = vldrhq_z_s16(ptr1, p0); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides1, p0); + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides0, p0); + acc1 = vmlaldavaq(acc1, vecState, vecCoef); + } + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + + *pDst++ = (q15_t) __SSAT(acc0, 16); + *pDst++ = (q15_t) __SSAT(acc1, 16); + i -= 2; + } + else + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U); + + q63_t acc0 = 0LL; + + uint32_t tapCnt = phaseLen >> 3; + while (tapCnt > 0U) + { + vecState = vldrhq_s16(ptr1); + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides0); + + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + + ptr1 += 8; + ptr2 = ptr2 + S->L * 8; + tapCnt--; + } + tapCnt = phaseLen & 7; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp16q(tapCnt); + + vecState = vldrhq_z_s16(ptr1, p0); + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides0, p0); + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + } + + acc0 = asrl(acc0, 15); + *pDst++ = (q15_t) __SSAT(acc0, 16); + /* + * Decrement the loop counter + */ + i--; + } + } + /* + * Advance the state pointer by 1 + * * to process the next group of interpolation factor number samples + */ + pState = pState + 1; + /* + * Decrement the loop counter + */ + blkCnt--; + } + + /* + * Processing is complete. + * Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + * This prepares the state buffer for the next function call. + */ + + /* + * Points to the start of the state buffer + */ + pStateCurnt = S->pState; + blkCnt = (phaseLen - 1U) >> 3; + while (blkCnt > 0U) + { + vstrhq_s16(pStateCurnt, vldrhq_s16(pState)); + pState += 8; + pStateCurnt += 8; + blkCnt--; + } + blkCnt = (phaseLen - 1U) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vstrhq_p_s16(pStateCurnt, vldrhq_s16(pState), p0); + } +} +#else +void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *ptr1; /* Temporary pointer for state buffer */ + const q15_t *ptr2; /* Temporary pointer for coefficient buffer */ + q63_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t j; + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2, acc3; + q15_t x0, x1, x2, x3; + q15_t c0, c1, c2, c3; +#endif + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = (S->L); + + while (i > 0U) + { + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + x0 = *(ptr1++); + x1 = *(ptr1++); + x2 = *(ptr1++); + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the coefficient */ + c1 = *(ptr2 + S->L); + + /* Read the input sample */ + x0 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x1 * c1; + acc1 += (q63_t) x2 * c1; + acc2 += (q63_t) x3 * c1; + acc3 += (q63_t) x0 * c1; + + /* Read the coefficient */ + c2 = *(ptr2 + S->L * 2); + + /* Read the input sample */ + x1 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x2 * c2; + acc1 += (q63_t) x3 * c2; + acc2 += (q63_t) x0 * c2; + acc3 += (q63_t) x1 * c2; + + /* Read the coefficient */ + c3 = *(ptr2 + S->L * 3); + + /* Read the input sample */ + x2 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x3 * c3; + acc1 += (q63_t) x0 * c3; + acc2 += (q63_t) x1 * c3; + acc3 += (q63_t) x2 * c3; + + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += 4 * S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* update states for next sample processing */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *(pDst ) = (q15_t) (__SSAT((acc0 >> 15), 16)); + *(pDst + S->L) = (q15_t) (__SSAT((acc1 >> 15), 16)); + *(pDst + 2 * S->L) = (q15_t) (__SSAT((acc2 >> 15), 16)); + *(pDst + 3 * S->L) = (q15_t) (__SSAT((acc3 >> 15), 16)); + + pDst++; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 4; + + pDst += S->L * 3; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = S->L; + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = phaseLen >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += (q63_t) *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = phaseLen % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = phaseLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += (q63_t) *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = (phaseLen - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = (phaseLen - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (phaseLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#else +/* alternate version for CM0_FAMILY */ + + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *ptr1; /* Temporary pointer for state buffer */ + const q15_t *ptr2; /* Temporary pointer for coefficient buffer */ + q63_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + + /* Total number of intput samples */ + blkCnt = blockSize; + + /* Loop over the blockSize. */ + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (i - 1U); + + /* Loop over the polyPhase length */ + tapCnt = phaseLen; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += ((q63_t) *ptr1++ * *ptr2); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Store the result after converting to 1.15 format in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + tapCnt = phaseLen - 1U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEI)*/ +/** + @} end of FIR_Interpolate group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c new file mode 100644 index 00000000..ea217603 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c @@ -0,0 +1,773 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_q31.c + * Description: Q31 FIR interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Processing function for the Q31 FIR interpolator. + @param[in] S points to an instance of the Q31 FIR interpolator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 1/(numTaps/L). + since numTaps/L additions occur per output sample. + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + const q31_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */ + + uint32_t i, blkCnt; /* Loop counters */ + uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t strides[4] = { 0, 1 * S->L, 2 * S->L, 3 * S->L }; + uint32x4_t vec_strides0 = vld1q_u32(strides); + uint32x4_t vec_strides1 = vec_strides0 + 1; + uint32x4_t vec_strides2 = vec_strides0 + 2; + uint32x4_t vec_strides3 = vec_strides0 + 3; + q31x4_t vecState, vecCoef; + + /* + * S->pState buffer contains previous frame (phaseLen - 1) samples + * pStateCurnt points to the location where the new input data should be written + */ + pStateCurnt = S->pState + ((q31_t) phaseLen - 1); + /* + * Total number of intput samples + */ + blkCnt = blockSize; + /* + * Loop over the blockSize. + */ + while (blkCnt > 0U) + { + /* + * Copy new input sample into the state buffer + */ + *pStateCurnt++ = *pSrc++; + /* + * Loop over the Interpolation factor. + */ + i = S->L; + while (i > 0U) + { + /* + * Initialize state pointer + */ + ptr1 = pState; + if (i >= 4) + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1 - 3U); + + q63_t acc0 = 0LL; + q63_t acc1 = 0LL; + q63_t acc2 = 0LL; + q63_t acc3 = 0LL; + + uint32_t tapCnt = phaseLen >> 2; + while (tapCnt > 0U) + { + vecState = vldrwq_s32(ptr1); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides3); + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides2); + acc1 = vrmlaldavhaq(acc1, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides1); + acc2 = vrmlaldavhaq(acc2, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides0); + acc3 = vrmlaldavhaq(acc3, vecState, vecCoef); + + ptr1 += 4; + ptr2 = ptr2 + S->L * 4; + tapCnt--; + } + tapCnt = phaseLen & 3; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + + vecState = vldrwq_z_s32(ptr1, p0); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides3, p0); + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides2, p0); + acc1 = vrmlaldavhaq(acc1, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides1, p0); + acc2 = vrmlaldavhaq(acc2, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides0, p0); + acc3 = vrmlaldavhaq(acc3, vecState, vecCoef); + } + + acc0 = asrl(acc0, 31 - 8); + acc1 = asrl(acc1, 31 - 8); + acc2 = asrl(acc2, 31 - 8); + acc3 = asrl(acc3, 31 - 8); + + *pDst++ = (q31_t) acc0; + *pDst++ = (q31_t) acc1; + *pDst++ = (q31_t) acc2; + *pDst++ = (q31_t) acc3; + i -= 4; + } + else if (i >= 3) + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U - 2); + + q63_t acc0 = 0LL; + q63_t acc1 = 0LL; + q63_t acc2 = 0LL; + + uint32_t tapCnt = phaseLen >> 2; + while (tapCnt > 0U) + { + vecState = vldrwq_s32(ptr1); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides2); + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides1); + acc1 = vrmlaldavhaq(acc1, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides0); + acc2 = vrmlaldavhaq(acc2, vecState, vecCoef); + + ptr1 += 4; + ptr2 = ptr2 + S->L * 4; + tapCnt--; + } + tapCnt = phaseLen & 3; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + + vecState = vldrwq_z_s32(ptr1, p0); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides2, p0); + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides1, p0); + acc1 = vrmlaldavhaq(acc1, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides0, p0); + acc2 = vrmlaldavhaq(acc2, vecState, vecCoef); + } + + acc0 = asrl(acc0, 31 - 8); + acc1 = asrl(acc1, 31 - 8); + acc2 = asrl(acc2, 31 - 8); + + *pDst++ = (q31_t) acc0; + *pDst++ = (q31_t) acc1; + *pDst++ = (q31_t) acc2; + i -= 3; + } + else if (i >= 2) + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U - 1); + + q63_t acc0 = 0LL; + q63_t acc1 = 0LL; + + uint32_t tapCnt = phaseLen >> 2; + while (tapCnt > 0U) + { + vecState = vldrwq_s32(ptr1); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides1); + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides0); + acc1 = vrmlaldavhaq(acc1, vecState, vecCoef); + + ptr1 += 4; + ptr2 = ptr2 + S->L * 4; + tapCnt--; + } + tapCnt = phaseLen & 3; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + + vecState = vldrwq_z_s32(ptr1, p0); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides1, p0); + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides0, p0); + acc1 = vrmlaldavhaq(acc1, vecState, vecCoef); + } + + acc0 = asrl(acc0, 31 - 8); + acc1 = asrl(acc1, 31 - 8); + + *pDst++ = (q31_t) acc0; + *pDst++ = (q31_t) acc1; + i -= 2; + } + else + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U); + + q63_t acc0 = 0LL; + + uint32_t tapCnt = phaseLen >> 2; + while (tapCnt > 0U) + { + vecState = vldrwq_s32(ptr1); + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides0); + + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + + ptr1 += 4; + ptr2 = ptr2 + S->L * 4; + tapCnt--; + } + tapCnt = phaseLen & 3; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + + vecState = vldrwq_z_s32(ptr1, p0); + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides0, p0); + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + } + + acc0 = asrl(acc0, 31 - 8); + *pDst++ = (q31_t) acc0; + /* + * Decrement the loop counter + */ + i--; + } + } + /* + * Advance the state pointer by 1 + * * to process the next group of interpolation factor number samples + */ + pState = pState + 1; + /* + * Decrement the loop counter + */ + blkCnt--; + } + + /* + * Processing is complete. + * ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + * ** This prepares the state buffer for the next function call. + */ + + /* + * Points to the start of the state buffer + */ + pStateCurnt = S->pState; + blkCnt = (phaseLen - 1U) >> 2; + while (blkCnt > 0U) + { + vst1q(pStateCurnt, vldrwq_s32(pState)); + pState += 4; + pStateCurnt += 4; + blkCnt--; + } + blkCnt = (phaseLen - 1U) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_s32(pStateCurnt, vldrwq_s32(pState), p0); + } +} +#else +void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + q31_t *ptr1; /* Temporary pointer for state buffer */ + const q31_t *ptr2; /* Temporary pointer for coefficient buffer */ + q63_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t j; + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2, acc3; + q31_t x0, x1, x2, x3; + q31_t c0, c1, c2, c3; +#endif + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = (S->L); + + while (i > 0U) + { + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + x0 = *(ptr1++); + x1 = *(ptr1++); + x2 = *(ptr1++); + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the coefficient */ + c1 = *(ptr2 + S->L); + + /* Read the input sample */ + x0 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x1 * c1; + acc1 += (q63_t) x2 * c1; + acc2 += (q63_t) x3 * c1; + acc3 += (q63_t) x0 * c1; + + /* Read the coefficient */ + c2 = *(ptr2 + S->L * 2); + + /* Read the input sample */ + x1 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x2 * c2; + acc1 += (q63_t) x3 * c2; + acc2 += (q63_t) x0 * c2; + acc3 += (q63_t) x1 * c2; + + /* Read the coefficient */ + c3 = *(ptr2 + S->L * 3); + + /* Read the input sample */ + x2 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x3 * c3; + acc1 += (q63_t) x0 * c3; + acc2 += (q63_t) x1 * c3; + acc3 += (q63_t) x2 * c3; + + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += 4 * S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* update states for next sample processing */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *(pDst ) = (q31_t) (acc0 >> 31); + *(pDst + S->L) = (q31_t) (acc1 >> 31); + *(pDst + 2 * S->L) = (q31_t) (acc2 >> 31); + *(pDst + 3 * S->L) = (q31_t) (acc3 >> 31); + + pDst++; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 4; + + pDst += S->L * 3; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = S->L; + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = phaseLen >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += (q63_t) *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = phaseLen % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = phaseLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += (q63_t) *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (sum0 >> 31); + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = (phaseLen - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = (phaseLen - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (phaseLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#else +/* alternate version for CM0_FAMILY */ + + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + q31_t *ptr1; /* Temporary pointer for state buffer */ + const q31_t *ptr2; /* Temporary pointer for coefficient buffer */ + q63_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + + /* Total number of intput samples */ + blkCnt = blockSize; + + /* Loop over the blockSize. */ + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (i - 1U); + + /* Loop over the polyPhase length */ + tapCnt = phaseLen; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += ((q63_t) *ptr1++ * *ptr2); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (sum0 >> 31); + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + tapCnt = phaseLen - 1U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ +/** + @} end of FIR_Interpolate group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c new file mode 100644 index 00000000..77ea75c1 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c @@ -0,0 +1,453 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_f32.c + * Description: Processing function for floating-point FIR Lattice filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup FIR_Lattice Finite Impulse Response (FIR) Lattice Filters + + This set of functions implements Finite Impulse Response (FIR) lattice filters + for Q15, Q31 and floating-point data types. Lattice filters are used in a + variety of adaptive filter applications. The filter structure is feedforward and + the net impulse response is finite length. + The functions operate on blocks + of input and output data and each call to the function processes + blockSize samples through the filter. pSrc and + pDst point to input and output arrays containing blockSize values. + + @par Algorithm + \image html FIRLattice.gif "Finite Impulse Response Lattice filter" + The following difference equation is implemented: + @par +
+      f0[n] = g0[n] = x[n]
+      fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M
+      gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M
+      y[n] = fM[n]
+  
+ @par + pCoeffs points to tha array of reflection coefficients of size numStages. + Reflection Coefficients are stored in the following order. + @par +
+      {k1, k2, ..., kM}
+  
+ where M is number of stages + @par + pState points to a state array of size numStages. + The state variables (g values) hold previous inputs and are stored in the following order. +
+    {g0[n], g1[n], g2[n] ...gM-1[n]}
+  
+ The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pCoeffs, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros and then manually initialize the instance structure as follows: +
+      arm_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};
+      arm_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};
+      arm_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};
+  
+ @par + where numStages is the number of stages in the filter; + pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the FIR Lattice filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Processing function for the floating-point FIR lattice filter. + @param[in] S points to an instance of the floating-point FIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *px; /* Temporary state pointer */ + const float32_t *pk; /* Temporary coefficient pointer */ + uint32_t numStages = S->numStages; /* Number of stages in the filter */ + uint32_t blkCnt, stageCnt; /* Loop counters */ + float32_t fcurr0, fnext0, gnext0, gcurr0; /* Temporary variables */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t fcurr1, fnext1, gnext1; /* Temporary variables for second sample in loop unrolling */ + float32_t fcurr2, fnext2, gnext2; /* Temporary variables for third sample in loop unrolling */ + float32_t fcurr3, fnext3, gnext3; /* Temporary variables for fourth sample in loop unrolling */ +#endif + + gcurr0 = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Read two samples from input buffer */ + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + fcurr1 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* Read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* Process first sample for first tap */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (fcurr0 * (*pk)) + gcurr0; + + /* Process second sample for first tap */ + fnext1 = (fcurr0 * (*pk)) + fcurr1; + gnext1 = (fcurr1 * (*pk)) + fcurr0; + + /* Read next two samples from input buffer */ + /* f0(n+2) = x(n+2) */ + fcurr2 = *pSrc++; + fcurr3 = *pSrc++; + + /* Process third sample for first tap */ + fnext2 = (fcurr1 * (*pk)) + fcurr2; + gnext2 = (fcurr2 * (*pk)) + fcurr1; + + /* Process fourth sample for first tap */ + fnext3 = (fcurr2 * (*pk )) + fcurr3; + gnext3 = (fcurr3 * (*pk++)) + fcurr2; + + /* Copy only last input sample into the state buffer + which will be used for next samples processing */ + *px++ = fcurr3; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + /* Loop unrolling. Process 4 taps at a time . */ + stageCnt = (numStages - 1U) >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numStages-3 coefficients. */ + + /* Process 2nd, 3rd, 4th and 5th taps ... here */ + while (stageCnt > 0U) + { + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext3; + + /* Process first sample for 2nd, 6th .. tap */ + /* Sample processing for K2, K6.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* Process second sample for 2nd, 6th .. tap */ + /* for sample 2 processing */ + fnext1 = (gnext0 * (*pk)) + fcurr1; + + /* Process third sample for 2nd, 6th .. tap */ + fnext2 = (gnext1 * (*pk)) + fcurr2; + + /* Process fourth sample for 2nd, 6th .. tap */ + fnext3 = (gnext2 * (*pk)) + fcurr3; + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (fcurr3 * (*pk)) + gnext2; + + gnext2 = (fcurr2 * (*pk)) + gnext1; + + gnext1 = (fcurr1 * (*pk)) + gnext0; + + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g2(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K3, K7.... */ + /* Process first sample for 3rd, 7th .. tap */ + /* f3(n) = f2(n) + K3 * g2(n-1) */ + fcurr0 = (gcurr0 * (*pk)) + fnext0; + + /* Process second sample for 3rd, 7th .. tap */ + fcurr1 = (gnext0 * (*pk)) + fnext1; + + /* Process third sample for 3rd, 7th .. tap */ + fcurr2 = (gnext1 * (*pk)) + fnext2; + + /* Process fourth sample for 3rd, 7th .. tap */ + fcurr3 = (gnext2 * (*pk)) + fnext3; + + /* Calculation of state values for next stage */ + /* g3(n) = f2(n) * K3 + g2(n-1) */ + gnext3 = (fnext3 * (*pk)) + gnext2; + + gnext2 = (fnext2 * (*pk)) + gnext1; + + gnext1 = (fnext1 * (*pk)) + gnext0; + + gnext0 = (fnext0 * (*pk++)) + gcurr0; + + + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g3(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K4, K8.... */ + /* Process first sample for 4th, 8th .. tap */ + /* f4(n) = f3(n) + K4 * g3(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* Process second sample for 4th, 8th .. tap */ + /* for sample 2 processing */ + fnext1 = (gnext0 * (*pk)) + fcurr1; + + /* Process third sample for 4th, 8th .. tap */ + fnext2 = (gnext1 * (*pk)) + fcurr2; + + /* Process fourth sample for 4th, 8th .. tap */ + fnext3 = (gnext2 * (*pk)) + fcurr3; + + /* g4(n) = f3(n) * K4 + g3(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (fcurr3 * (*pk)) + gnext2; + + gnext2 = (fcurr2 * (*pk)) + gnext1; + + gnext1 = (fcurr1 * (*pk)) + gnext0; + + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g4(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K5, K9.... */ + /* Process first sample for 5th, 9th .. tap */ + /* f5(n) = f4(n) + K5 * g4(n-1) */ + fcurr0 = (gcurr0 * (*pk)) + fnext0; + + /* Process second sample for 5th, 9th .. tap */ + fcurr1 = (gnext0 * (*pk)) + fnext1; + + /* Process third sample for 5th, 9th .. tap */ + fcurr2 = (gnext1 * (*pk)) + fnext2; + + /* Process fourth sample for 5th, 9th .. tap */ + fcurr3 = (gnext2 * (*pk)) + fnext3; + + /* Calculation of state values for next stage */ + /* g5(n) = f4(n) * K5 + g4(n-1) */ + gnext3 = (fnext3 * (*pk)) + gnext2; + + gnext2 = (fnext2 * (*pk)) + gnext1; + + gnext1 = (fnext1 * (*pk)) + gnext0; + + gnext0 = (fnext0 * (*pk++)) + gcurr0; + + stageCnt--; + } + + /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */ + stageCnt = (numStages - 1U) % 0x4U; + + while (stageCnt > 0U) + { + gcurr0 = *px; + + /* save g value in state buffer */ + *px++ = gnext3; + + /* Process four samples for last three taps here */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + fnext1 = (gnext0 * (*pk)) + fcurr1; + + fnext2 = (gnext1 * (*pk)) + fcurr2; + + fnext3 = (gnext2 * (*pk)) + fcurr3; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext3 = (fcurr3 * (*pk)) + gnext2; + + gnext2 = (fcurr2 * (*pk)) + gnext1; + + gnext1 = (fcurr1 * (*pk)) + gnext0; + + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + stageCnt--; + } + + /* The results in the 4 accumulators, store in the destination buffer. */ + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + *pDst++ = fcurr1; + *pDst++ = fcurr2; + *pDst++ = fcurr3; + + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + /* save g1(n) in state buffer */ + *px++ = fcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + + blkCnt--; + } + +} + +/** + @} end of FIR_Lattice group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c new file mode 100644 index 00000000..a3a0c224 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_init_f32.c + * Description: Floating-point FIR Lattice filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Initialization function for the floating-point FIR lattice filter. + @param[in] S points to an instance of the floating-point FIR lattice structure + @param[in] numStages number of filter stages + @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages + @param[in] pState points to the state buffer. The array is of length numStages + @return none + */ + +void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + const float32_t * pCoeffs, + float32_t * pState) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always numStages */ + memset(pState, 0, (numStages) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Lattice group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c new file mode 100644 index 00000000..3996d484 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_init_q15.c + * Description: Q15 FIR Lattice filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Initialization function for the Q15 FIR lattice filter. + @param[in] S points to an instance of the Q15 FIR lattice structure + @param[in] numStages number of filter stages + @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages + @param[in] pState points to the state buffer. The array is of length numStages + @return none + */ + +void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + const q15_t * pCoeffs, + q15_t * pState) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always numStages */ + memset(pState, 0, (numStages) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Lattice group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c new file mode 100644 index 00000000..4a91b590 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_init_q31.c + * Description: Q31 FIR lattice filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Initialization function for the Q31 FIR lattice filter. + @param[in] S points to an instance of the Q31 FIR lattice structure + @param[in] numStages number of filter stages + @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages + @param[in] pState points to the state buffer. The array is of length numStages + @return none + */ + +void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + const q31_t * pCoeffs, + q31_t * pState) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always numStages */ + memset(pState, 0, (numStages) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Lattice group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c new file mode 100644 index 00000000..14b7076d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c @@ -0,0 +1,506 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_q15.c + * Description: Q15 FIR lattice filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Processing function for Q15 FIR lattice filter. + @param[in] S points to an instance of the Q15 FIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *px; /* Temporary state pointer */ + const q15_t *pk; /* Temporary coefficient pointer */ + uint32_t numStages = S->numStages; /* Number of stages in the filter */ + uint32_t blkCnt, stageCnt; /* Loop counters */ + q31_t fcurr0, fnext0, gnext0, gcurr0; /* Temporary variables */ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t fcurr1, fnext1, gnext1; /* Temporary variables for second sample in loop unrolling */ + q31_t fcurr2, fnext2, gnext2; /* Temporary variables for third sample in loop unrolling */ + q31_t fcurr3, fnext3, gnext3; /* Temporary variables for fourth sample in loop unrolling */ +#endif + + gcurr0 = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Read two samples from input buffer */ + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + fcurr1 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* Read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* Process first sample for first tap */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (q31_t) ((fcurr0 * (*pk)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* Process second sample for first tap */ + fnext1 = (q31_t) ((fcurr0 * (*pk)) >> 15U) + fcurr1; + fnext1 = __SSAT(fnext1, 16); + gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + fcurr0; + gnext1 = __SSAT(gnext1, 16); + + /* Read next two samples from input buffer */ + /* f0(n+2) = x(n+2) */ + fcurr2 = *pSrc++; + fcurr3 = *pSrc++; + + /* Process third sample for first tap */ + fnext2 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + fcurr2; + fnext2 = __SSAT(fnext2, 16); + gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + fcurr1; + gnext2 = __SSAT(gnext2, 16); + + /* Process fourth sample for first tap */ + fnext3 = (q31_t) ((fcurr2 * (*pk )) >> 15U) + fcurr3; + fnext3 = __SSAT(fnext3, 16); + gnext3 = (q31_t) ((fcurr3 * (*pk++)) >> 15U) + fcurr2; + gnext3 = __SSAT(gnext3, 16); + + /* Copy only last input sample into the state buffer + which will be used for next samples processing */ + *px++ = (q15_t) fcurr3; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + /* Loop unrolling. Process 4 taps at a time . */ + stageCnt = (numStages - 1U) >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numStages-3 coefficients. */ + + /* Process 2nd, 3rd, 4th and 5th taps ... here */ + while (stageCnt > 0U) + { + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = (q15_t) gnext3; + + /* Process first sample for 2nd, 6th .. tap */ + /* Sample processing for K2, K6.... */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* Process second sample for 2nd, 6th .. tap */ + /* for sample 2 processing */ + fnext1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fcurr1; + fnext1 = __SSAT(fnext1, 16); + + /* Process third sample for 2nd, 6th .. tap */ + fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fcurr2; + fnext2 = __SSAT(fnext2, 16); + + /* Process fourth sample for 2nd, 6th .. tap */ + fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fcurr3; + fnext3 = __SSAT(fnext3, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (q31_t) ((fcurr3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = (q15_t) gnext3; + + /* Sample processing for K3, K7.... */ + /* Process first sample for 3rd, 7th .. tap */ + /* f3(n) = f2(n) + K3 * g2(n-1) */ + fcurr0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fnext0; + fcurr0 = __SSAT(fcurr0, 16); + + /* Process second sample for 3rd, 7th .. tap */ + fcurr1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fnext1; + fcurr1 = __SSAT(fcurr1, 16); + + /* Process third sample for 3rd, 7th .. tap */ + fcurr2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fnext2; + fcurr2 = __SSAT(fcurr2, 16); + + /* Process fourth sample for 3rd, 7th .. tap */ + fcurr3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fnext3; + fcurr3 = __SSAT(fcurr3, 16); + + /* Calculation of state values for next stage */ + /* g3(n) = f2(n) * K3 + g2(n-1) */ + gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fnext1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fnext0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = (q15_t) gnext3; + + /* Sample processing for K4, K8.... */ + /* Process first sample for 4th, 8th .. tap */ + /* f4(n) = f3(n) + K4 * g3(n-1) */ + fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* Process second sample for 4th, 8th .. tap */ + /* for sample 2 processing */ + fnext1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fcurr1; + fnext1 = __SSAT(fnext1, 16); + + /* Process third sample for 4th, 8th .. tap */ + fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fcurr2; + fnext2 = __SSAT(fnext2, 16); + + /* Process fourth sample for 4th, 8th .. tap */ + fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fcurr3; + fnext3 = __SSAT(fnext3, 16); + + /* g4(n) = f3(n) * K4 + g3(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (q31_t) ((fcurr3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g4(n) in state buffer */ + *px++ = (q15_t) gnext3; + + /* Sample processing for K5, K9.... */ + /* Process first sample for 5th, 9th .. tap */ + /* f5(n) = f4(n) + K5 * g4(n-1) */ + fcurr0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fnext0; + fcurr0 = __SSAT(fcurr0, 16); + + /* Process second sample for 5th, 9th .. tap */ + fcurr1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fnext1; + fcurr1 = __SSAT(fcurr1, 16); + + /* Process third sample for 5th, 9th .. tap */ + fcurr2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fnext2; + fcurr2 = __SSAT(fcurr2, 16); + + /* Process fourth sample for 5th, 9th .. tap */ + fcurr3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fnext3; + fcurr3 = __SSAT(fcurr3, 16); + + /* Calculation of state values for next stage */ + /* g5(n) = f4(n) * K5 + g4(n-1) */ + gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fnext1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fnext0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + stageCnt--; + } + + /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */ + stageCnt = (numStages - 1U) % 0x4U; + + while (stageCnt > 0U) + { + gcurr0 = *px; + + /* save g value in state buffer */ + *px++ = (q15_t) gnext3; + + /* Process four samples for last three taps here */ + fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + fnext1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fcurr1; + fnext1 = __SSAT(fnext1, 16); + + fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fcurr2; + fnext2 = __SSAT(fnext2, 16); + + fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fcurr3; + fnext3 = __SSAT(fnext3, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext3 = (q31_t) ((fcurr3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + stageCnt--; + } + + /* The results in the 4 accumulators, store in the destination buffer. */ + /* y(n) = fN(n) */ + +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(fcurr0, fcurr1, 16)); + write_q15x2_ia (&pDst, __PKHBT(fcurr2, fcurr3, 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(fcurr1, fcurr0, 16)); + write_q15x2_ia (&pDst, __PKHBT(fcurr3, fcurr2, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (((q31_t) gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (((q31_t) fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* save g1(n) in state buffer */ + *px++ = (q15_t) fcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = (q15_t) gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (((q31_t) gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = (((q31_t) fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = __SSAT(fcurr0, 16); + + blkCnt--; + } + +#else +/* alternate version for CM0_FAMILY */ + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* save f0(n) in state buffer */ + *px++ = (q15_t) fcurr0; + + /* f1(n) is saved in fcurr for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g1(n-1) from state buffer */ + gcurr0 = *px; + + /* save g0(n-1) in state buffer */ + *px++ = (q15_t) gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = __SSAT(fcurr0, 16); + + blkCnt--; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of FIR_Lattice group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c new file mode 100644 index 00000000..3b835518 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c @@ -0,0 +1,505 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_q31.c + * Description: Q31 FIR lattice filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Processing function for the Q31 FIR lattice filter. + @param[in] S points to an instance of the Q31 FIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits. + */ + +void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *px; /* Temporary state pointer */ + const q31_t *pk; /* Temporary coefficient pointer */ + uint32_t numStages = S->numStages; /* Number of stages in the filter */ + uint32_t blkCnt, stageCnt; /* Loop counters */ + q31_t fcurr0, fnext0, gnext0, gcurr0; /* Temporary variables */ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t fcurr1, fnext1, gnext1; /* Temporary variables for second sample in loop unrolling */ + q31_t fcurr2, fnext2, gnext2; /* Temporary variables for third sample in loop unrolling */ + q31_t fcurr3, fnext3, gnext3; /* Temporary variables for fourth sample in loop unrolling */ +#endif + + gcurr0 = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Read two samples from input buffer */ + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + fcurr1 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* Read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* Process first sample for first tap */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* Process second sample for first tap */ + fnext1 = (q31_t) (((q63_t) fcurr0 * (*pk)) >> 32U); + fnext1 = (fnext1 << 1U) + fcurr1; + gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + fcurr0; + + /* Read next two samples from input buffer */ + /* f0(n+2) = x(n+2) */ + fcurr2 = *pSrc++; + fcurr3 = *pSrc++; + + /* Process third sample for first tap */ + fnext2 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + fnext2 = (fnext2 << 1U) + fcurr2; + gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + fcurr1; + + /* Process fourth sample for first tap */ + fnext3 = (q31_t) (((q63_t) fcurr2 * (*pk )) >> 32U); + fnext3 = (fnext3 << 1U) + fcurr3; + gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk++)) >> 32U); + gnext3 = (gnext3 << 1U) + fcurr2; + + /* Copy only last input sample into the state buffer + which will be used for next samples processing */ + *px++ = fcurr3; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + /* Loop unrolling. Process 4 taps at a time . */ + stageCnt = (numStages - 1U) >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numStages-3 coefficients. */ + + /* Process 2nd, 3rd, 4th and 5th taps ... here */ + while (stageCnt > 0U) + { + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext3; + + /* Process first sample for 2nd, 6th .. tap */ + /* Sample processing for K2, K6.... */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* Process second sample for 2nd, 6th .. tap */ + /* for sample 2 processing */ + fnext1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fnext1 = (fnext1 << 1U) + fcurr1; + + /* Process third sample for 2nd, 6th .. tap */ + fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fnext2 = (fnext2 << 1U) + fcurr2; + + /* Process fourth sample for 2nd, 6th .. tap */ + fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fnext3 = (fnext3 << 1U) + fcurr3; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K3, K7.... */ + /* Process first sample for 3rd, 7th .. tap */ + /* f3(n) = f2(n) + K3 * g2(n-1) */ + fcurr0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fcurr0 = (fcurr0 << 1U) + fnext0; + + /* Process second sample for 3rd, 7th .. tap */ + fcurr1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fcurr1 = (fcurr1 << 1U) + fnext1; + + /* Process third sample for 3rd, 7th .. tap */ + fcurr2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fcurr2 = (fcurr2 << 1U) + fnext2; + + /* Process fourth sample for 3rd, 7th .. tap */ + fcurr3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fcurr3 = (fcurr3 << 1U) + fnext3; + + /* Calculation of state values for next stage */ + /* g3(n) = f2(n) * K3 + g2(n-1) */ + gnext3 = (q31_t) (((q63_t) fnext3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fnext2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fnext1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fnext0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K4, K8.... */ + /* Process first sample for 4th, 8th .. tap */ + /* f4(n) = f3(n) + K4 * g3(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* Process second sample for 4th, 8th .. tap */ + /* for sample 2 processing */ + fnext1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fnext1 = (fnext1 << 1U) + fcurr1; + + /* Process third sample for 4th, 8th .. tap */ + fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fnext2 = (fnext2 << 1U) + fcurr2; + + /* Process fourth sample for 4th, 8th .. tap */ + fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fnext3 = (fnext3 << 1U) + fcurr3; + + /* g4(n) = f3(n) * K4 + g3(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g4(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K5, K9.... */ + /* Process first sample for 5th, 9th .. tap */ + /* f5(n) = f4(n) + K5 * g4(n-1) */ + fcurr0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fcurr0 = (fcurr0 << 1U) + fnext0; + + /* Process second sample for 5th, 9th .. tap */ + fcurr1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fcurr1 = (fcurr1 << 1U) + fnext1; + + /* Process third sample for 5th, 9th .. tap */ + fcurr2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fcurr2 = (fcurr2 << 1U) + fnext2; + + /* Process fourth sample for 5th, 9th .. tap */ + fcurr3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fcurr3 = (fcurr3 << 1U) + fnext3; + + /* Calculation of state values for next stage */ + /* g5(n) = f4(n) * K5 + g4(n-1) */ + gnext3 = (q31_t) (((q63_t) fnext3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fnext2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fnext1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fnext0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + stageCnt--; + } + + /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */ + stageCnt = (numStages - 1U) % 0x4U; + + while (stageCnt > 0U) + { + gcurr0 = *px; + + /* save g value in state buffer */ + *px++ = gnext3; + + /* Process four samples for last three taps here */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + fnext1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fnext1 = (fnext1 << 1U) + fcurr1; + + fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fnext2 = (fnext2 << 1U) + fcurr2; + + fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fnext3 = (fnext3 << 1U) + fcurr3; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + stageCnt--; + } + + /* The results in the 4 accumulators, store in the destination buffer. */ + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + *pDst++ = fcurr1; + *pDst++ = fcurr2; + *pDst++ = fcurr3; + + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* save g1(n) in state buffer */ + *px++ = fcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + + blkCnt--; + } + +#else +/* alternate version for CM0_FAMILY */ + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext << 1U) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* save f0(n) in state buffer */ + *px++ = fcurr0; + + /* f1(n) is saved in fcurr for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g1(n-1) from state buffer */ + gcurr0 = *px; + + /* save g0(n-1) in state buffer */ + *px++ = gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + + blkCnt--; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of FIR_Lattice group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c new file mode 100644 index 00000000..6b7d9905 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c @@ -0,0 +1,732 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_q15.c + * Description: Q15 FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for the Q15 FIR filter. + @param[in] S points to an instance of the Q15 FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + + @remark + Refer to \ref arm_fir_fast_q15() for a faster but less precise implementation of this function. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MVE_ASRL_SAT16(acc, shift) ((sqrshrl_sat48(acc, -(32-shift)) >> 32) & 0xffffffff) + + +#define FIR_Q15_CORE(pOutput, nbAcc, nbVecTaps, pSample, vecCoeffs) \ + for (int j = 0; j < nbAcc; j++) { \ + const q15_t *pSmp = &pSample[j]; \ + q63_t acc[4]; \ + \ + acc[j] = 0; \ + for (int i = 0; i < nbVecTaps; i++) { \ + vecIn0 = vld1q(pSmp + 8 * i); \ + acc[j] = vmlaldavaq(acc[j], vecIn0, vecCoeffs[i]); \ + } \ + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc[j], 15); \ + } + +#define FIR_Q15_MAIN_CORE() \ +{ \ + q15_t *pState = S->pState; /* State pointer */ \ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ \ + q15_t *pStateCur; /* Points to the current sample of the state */ \ + const q15_t *pSamples; /* Temporary pointer to the sample buffer */ \ + q15_t *pOutput; /* Temporary pointer to the output buffer */ \ + const q15_t *pTempSrc; /* Temporary pointer to the source data */ \ + q15_t *pTempDest; /* Temporary pointer to the destination buffer */\ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */\ + int32_t blkCnt; \ + q15x8_t vecIn0; \ + \ + /* \ + * load coefs \ + */ \ + q15x8_t vecCoeffs[NBVECTAPS]; \ + \ + for (int i = 0; i < NBVECTAPS; i++) \ + vecCoeffs[i] = vldrhq_s16(pCoeffs + 8 * i); \ + \ + /* \ + * pState points to state array which contains previous frame (numTaps - 1) samples \ + * pStateCur points to the location where the new input data should be written \ + */ \ + pStateCur = &(pState[(numTaps - 1u)]); \ + pTempSrc = pSrc; \ + pSamples = pState; \ + pOutput = pDst; \ + \ + blkCnt = blockSize >> 2; \ + while (blkCnt > 0) { \ + /* \ + * Save 4 input samples in the history buffer \ + */ \ + vstrhq_s32(pStateCur, vldrhq_s32(pTempSrc)); \ + pStateCur += 4; \ + pTempSrc += 4; \ + \ + FIR_Q15_CORE(pOutput, 4, NBVECTAPS, pSamples, vecCoeffs); \ + pSamples += 4; \ + \ + blkCnt--; \ + } \ + \ + /* tail */ \ + int32_t residual = blockSize & 3; \ + \ + for (int i = 0; i < residual; i++) \ + *pStateCur++ = *pTempSrc++; \ + \ + FIR_Q15_CORE(pOutput, residual, NBVECTAPS, pSamples, vecCoeffs); \ + \ + /* \ + * Copy the samples back into the history buffer start \ + */ \ + pTempSrc = &pState[blockSize]; \ + pTempDest = pState; \ + \ + /* current compiler limitation */ \ + blkCnt = (numTaps - 1) >> 3; \ + while (blkCnt > 0) \ + { \ + vstrhq_s16(pTempDest, vldrhq_s16(pTempSrc)); \ + pTempSrc += 8; \ + pTempDest += 8; \ + blkCnt--; \ + } \ + blkCnt = (numTaps - 1) & 7; \ + if (blkCnt > 0) \ + { \ + mve_pred16_t p = vctp16q(blkCnt); \ + vstrhq_p_s16(pTempDest, vldrhq_z_s16(pTempSrc, p), p); \ + } \ +} + +static void arm_fir_q15_25_32_mve(const arm_fir_instance_q15 * S, + const q15_t * __restrict pSrc, + q15_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 32 + #define NBVECTAPS (NBTAPS / 8) + FIR_Q15_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + +static void arm_fir_q15_17_24_mve(const arm_fir_instance_q15 * S, + const q15_t * __restrict pSrc, + q15_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 24 + #define NBVECTAPS (NBTAPS / 8) + FIR_Q15_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +static void arm_fir_q15_9_16_mve(const arm_fir_instance_q15 * S, + const q15_t * __restrict pSrc, + q15_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 16 + #define NBVECTAPS (NBTAPS / 8) + FIR_Q15_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + +static void arm_fir_q15_1_8_mve(const arm_fir_instance_q15 * S, + const q15_t * __restrict pSrc, + q15_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 8 + #define NBVECTAPS (NBTAPS / 8) + FIR_Q15_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +void arm_fir_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + const q15_t *pSamples; /* Temporary pointer to the sample buffer */ + q15_t *pOutput; /* Temporary pointer to the output buffer */ + const q15_t *pTempSrc; /* Temporary pointer to the source data */ + q15_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t blkCnt; + q15x8_t vecIn0; + uint32_t tapsBlkCnt = (numTaps + 7) / 8; + q63_t acc0, acc1, acc2, acc3; + + +int32_t nbTaps = (numTaps + 7) >> 3; + +switch(nbTaps) { + + case 1: + arm_fir_q15_1_8_mve(S, pSrc, pDst, blockSize); + return; + case 2: + arm_fir_q15_9_16_mve(S, pSrc, pDst, blockSize); + return; + case 3: + arm_fir_q15_17_24_mve(S, pSrc, pDst, blockSize); + return; + case 4: + arm_fir_q15_25_32_mve(S, pSrc, pDst, blockSize); + return; + } + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + pTempSrc = pSrc; + pSamples = pState; + pOutput = pDst; + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + const q15_t *pCoeffsTmp = pCoeffs; + const q15_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + acc3 = 0LL; + + /* + * Save 8 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 8; + pTempSrc += 8; + + int i = tapsBlkCnt; + while (i > 0) + { + /* + * load 8 coefs + */ + q15x8_t vecCoeffs = *(q15x8_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmlaldavaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[1]); + acc1 = vmlaldavaq(acc1, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[2]); + acc2 = vmlaldavaq(acc2, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[3]); + acc3 = vmlaldavaq(acc3, vecIn0, vecCoeffs); + + pSamplesTmp += 8; + pCoeffsTmp += 8; + /* + * Decrement the taps block loop counter + */ + i--; + } + + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc0, 15); + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc1, 15); + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc2, 15); + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc3, 15); + + pSamples += 4; + /* + * Decrement the sample block loop counter + */ + blkCnt--; + } + + uint32_t residual = blockSize & 3; + switch (residual) + { + case 3: + { + const q15_t *pCoeffsTmp = pCoeffs; + const q15_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + + /* + * Save 8 input samples in the history buffer + */ + *(q15x8_t *) pStateCur = *(q15x8_t *) pTempSrc; + pStateCur += 8; + pTempSrc += 8; + + int i = tapsBlkCnt; + while (i > 0) + { + /* + * load 8 coefs + */ + q15x8_t vecCoeffs = *(q15x8_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmlaldavaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[2]); + acc1 = vmlaldavaq(acc1, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[4]); + acc2 = vmlaldavaq(acc2, vecIn0, vecCoeffs); + + pSamplesTmp += 8; + pCoeffsTmp += 8; + /* + * Decrement the taps block loop counter + */ + i--; + } + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc0, 15); + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc1, 15); + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc2, 15); + } + break; + + case 2: + { + const q15_t *pCoeffsTmp = pCoeffs; + const q15_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + acc1 = 0LL; + /* + * Save 8 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 8; + pTempSrc += 8; + + int i = tapsBlkCnt; + while (i > 0) + { + /* + * load 8 coefs + */ + q15x8_t vecCoeffs = *(q15x8_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmlaldavaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[2]); + acc1 = vmlaldavaq(acc1, vecIn0, vecCoeffs); + + pSamplesTmp += 8; + pCoeffsTmp += 8; + /* + * Decrement the taps block loop counter + */ + i--; + } + + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc0, 15); + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc1, 15); + } + break; + + case 1: + { + const q15_t *pCoeffsTmp = pCoeffs; + const q15_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + + /* + * Save 8 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 8; + pTempSrc += 8; + + int i = tapsBlkCnt; + while (i > 0) + { + /* + * load 8 coefs + */ + q15x8_t vecCoeffs = *(q15x8_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmlaldavaq(acc0, vecIn0, vecCoeffs); + + pSamplesTmp += 8; + pCoeffsTmp += 8; + /* + * Decrement the taps block loop counter + */ + i--; + } + + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc0, 15); + } + break; + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = numTaps >> 3; + while (blkCnt > 0U) + { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 8; + pTempDest += 8; + blkCnt--; + } + blkCnt = numTaps & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vstrhq_p_s16(pTempDest, vld1q(pTempSrc), p0); + } +} + +#else +void arm_fir_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q63_t acc0; /* Accumulators */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, c0; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */ + px = pState; + + /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */ + pb = pCoeffs; + + /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */ + x0 = read_q15x2_ia (&px); + + /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */ + x2 = read_q15x2_ia (&px); + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numTaps-(numTaps%4) coefficients. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */ + c0 = read_q15x2_ia (&pb); + + /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */ + acc0 = __SMLALD(x0, c0, acc0); + + /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */ + acc2 = __SMLALD(x2, c0, acc2); + + /* pack x[n-N-1] and x[n-N-2] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* Read state x[n-N-4], x[n-N-5] */ + x0 = read_q15x2_ia (&px); + + /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* pack x[n-N-3] and x[n-N-4] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x0, x2, 0); +#else + x1 = __PKHBT(x2, x0, 0); +#endif + + /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */ + acc3 = __SMLALDX(x1, c0, acc3); + + /* Read coefficients b[N-2], b[N-3] */ + c0 = read_q15x2_ia (&pb); + + /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */ + acc0 = __SMLALD(x2, c0, acc0); + + /* Read state x[n-N-6], x[n-N-7] with offset */ + x2 = read_q15x2_ia (&px); + + /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */ + acc2 = __SMLALD(x0, c0, acc2); + + /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* pack x[n-N-5] and x[n-N-6] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */ + acc3 = __SMLALDX(x1, c0, acc3); + + /* Decrement tap count */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps. + This is always be 2 taps since the filter length is even. */ + if ((numTaps & 0x3U) != 0U) + { + /* Read last two coefficients */ + c0 = read_q15x2_ia (&pb); + + /* Perform the multiply-accumulates */ + acc0 = __SMLALD(x0, c0, acc0); + acc2 = __SMLALD(x2, c0, acc2); + + /* pack state variables */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* Read last state variables */ + x0 = read_q15x2 (px); + + /* Perform the multiply-accumulates */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* pack state variables */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x0, x2, 0); +#else + x1 = __PKHBT(x2, x0, 0); +#endif + + /* Perform the multiply-accumulates */ + acc3 = __SMLALDX(x1, c0, acc3); + } + + /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation. + Then store the 4 outputs in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy two samples into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Use SIMD to hold states and coefficients */ + px = pState; + pb = pCoeffs; + + tapCnt = numTaps >> 1U; + + while (tapCnt > 0U) + { + acc0 += (q31_t) *px++ * *pb++; + acc0 += (q31_t) *px++ * *pb++; + + tapCnt--; + } + + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of FIR group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c new file mode 100644 index 00000000..40fe5270 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c @@ -0,0 +1,1162 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_q31.c + * Description: Q31 FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for Q31 FIR filter. + @param[in] S points to an instance of the Q31 FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. + After all multiply-accumulates are performed, the 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + + @remark + Refer to \ref arm_fir_fast_q31() for a faster but less precise implementation of this filter. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + +#define FIR_Q31_CORE(nbAcc, nbVecTaps, pSample, vecCoeffs) \ + for (int j = 0; j < nbAcc; j++) { \ + const q31_t *pSmp = &pSamples[j]; \ + q31x4_t vecIn0; \ + q63_t acc[4]; \ + \ + acc[j] = 0; \ + for (int i = 0; i < nbVecTaps; i++) { \ + vecIn0 = vld1q(pSmp + 4 * i); \ + acc[j] = vrmlaldavhaq(acc[j], vecIn0, vecCoeffs[i]); \ + } \ + *pOutput++ = (q31_t)asrl(acc[j], 23); \ + } + + +#define FIR_Q31_CORE_STR_PARTIAL(nbAcc, nbVecTaps, pSample, vecCoeffs) \ + for (int j = 0; j < nbAcc; j++) { \ + const q31_t *pSmp = &pSamples[j]; \ + q31x4_t vecIn0; \ + \ + acc[j] = 0; \ + for (int i = 0; i < nbVecTaps; i++) { \ + vecIn0 = vld1q(pSmp + 4 * i); \ + acc[j] = vrmlaldavhaq(acc[j], vecIn0, vecCoeffs[i]); \ + } \ + *arm_fir_partial_accu_ptr++ = acc[j]; \ + } + + +#define FIR_Q31_CORE_LD_PARTIAL(nbAcc, nbVecTaps, pSample, vecCoeffs) \ + for (int j = 0; j < nbAcc; j++) { \ + const q31_t *pSmp = &pSamples[j]; \ + q31x4_t vecIn0; \ + \ + acc[j] = *arm_fir_partial_accu_ptr++; \ + \ + for (int i = 0; i < nbVecTaps; i++) { \ + vecIn0 = vld1q(pSmp + 4 * i); \ + acc[j] = vrmlaldavhaq(acc[j], vecIn0, vecCoeffs[i]); \ + } \ + *pOutput++ = (q31_t)asrl(acc[j], 23); \ + } + + +#define FIR_Q31_MAIN_CORE() \ +{ \ + q31_t *pRefStatePtr = S->pState + 2*ROUND_UP(blockSize, 4); \ + q31_t *pState = pRefStatePtr; /* State pointer */ \ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ \ + q31_t *pStateCur; /* Points to the current sample of the state */ \ + const q31_t *pSamples; /* Temporary pointer to the sample buffer */ \ + q31_t *pOutput; /* Temporary pointer to the output buffer */ \ + const q31_t *pTempSrc; /* Temporary pointer to the source data */ \ + q31_t *pTempDest; /* Temporary pointer to the destination buffer */\ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */\ + int32_t blkCnt; \ + \ + /* \ + * load coefs \ + */ \ + q31x4_t vecCoeffs[NBVECTAPS]; \ + \ + for (int i = 0; i < NBVECTAPS; i++) \ + vecCoeffs[i] = vld1q(pCoeffs + 4 * i); \ + \ + /* \ + * pState points to state array which contains previous frame (numTaps - 1) samples \ + * pStateCur points to the location where the new input data should be written \ + */ \ + pStateCur = &(pState[(numTaps - 1u)]); \ + pTempSrc = pSrc; \ + pSamples = pState; \ + pOutput = pDst; \ + \ + blkCnt = blockSize >> 2; \ + while (blkCnt > 0) { \ + /* \ + * Save 4 input samples in the history buffer \ + */ \ + vstrwq_s32(pStateCur, vldrwq_s32(pTempSrc)); \ + pStateCur += 4; \ + pTempSrc += 4; \ + \ + FIR_Q31_CORE(4, NBVECTAPS, pSamples, vecCoeffs); \ + \ + pSamples += 4; \ + /* \ + * Decrement the sample block loop counter \ + */ \ + blkCnt--; \ + } \ + \ + /* tail */ \ + int32_t residual = blockSize & 3; \ + switch (residual) { \ + case 3: \ + { \ + for (int i = 0; i < residual; i++) \ + *pStateCur++ = *pTempSrc++; \ + \ + FIR_Q31_CORE(3, NBVECTAPS, pSamples, vecCoeffs); \ + } \ + break; \ + \ + case 2: \ + { \ + for (int i = 0; i < residual; i++) \ + *pStateCur++ = *pTempSrc++; \ + \ + FIR_Q31_CORE(2, NBVECTAPS, pSamples, vecCoeffs); \ + } \ + break; \ + \ + case 1: \ + { \ + for (int i = 0; i < residual; i++) \ + *pStateCur++ = *pTempSrc++; \ + \ + FIR_Q31_CORE(1, NBVECTAPS, pSamples, vecCoeffs); \ + } \ + break; \ + } \ + \ + /* \ + * Copy the samples back into the history buffer start \ + */ \ + pTempSrc = &pState[blockSize]; \ + pTempDest = pState; \ + \ + blkCnt =(numTaps - 1) >> 2; \ + while (blkCnt > 0) \ + { \ + vstrwq_s32(pTempDest, vldrwq_s32(pTempSrc)); \ + pTempSrc += 4; \ + pTempDest += 4; \ + blkCnt--; \ + } \ + blkCnt = (numTaps - 1) & 3; \ + if (blkCnt > 0) \ + { \ + mve_pred16_t p0 = vctp32q(blkCnt); \ + vstrwq_p_s32(pTempDest, vldrwq_z_s32(pTempSrc, p0), p0); \ + } \ +} + +static void arm_fir_q31_1_4_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, uint32_t blockSize) +{ + q31_t *pRefStatePtr = S->pState + 2*ROUND_UP(blockSize, 4); + q31_t *pState = pRefStatePtr; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + const q31_t *pSamples; /* Temporary pointer to the sample buffer */ + q31_t *pOutput; /* Temporary pointer to the output buffer */ + const q31_t *pTempSrc; /* Temporary pointer to the source data */ + q31_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t blkCnt; + q31x4_t vecIn0; + + + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + pTempSrc = pSrc; + pSamples = pState; + pOutput = pDst; + + q63_t acc0=0, acc1=0, acc2=0, acc3=0; + /* + * load 4 coefs + */ + q31x4_t vecCoeffs = *(q31x4_t *) pCoeffs; + + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + const q31_t *pSamplesTmp = pSamples; + + /* + * Save 4 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vrmlaldavhq(vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[1]); + acc1 = vrmlaldavhq(vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[2]); + acc2 = vrmlaldavhq(vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[3]); + acc3 = vrmlaldavhq(vecIn0, vecCoeffs); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + *pOutput++ = (q31_t) acc0; + *pOutput++ = (q31_t) acc1; + *pOutput++ = (q31_t) acc2; + *pOutput++ = (q31_t) acc3; + + pSamples += 4; + /* + * Decrement the sample block loop counter + */ + blkCnt--; + } + + uint32_t residual = blockSize & 3; + switch (residual) + { + case 3: + { + /* + * Save 4 input samples in the history buffer + */ + *(q31x4_t *) pStateCur = *(q31x4_t *) pTempSrc; + pStateCur += 4; + pTempSrc += 4; + + vecIn0 = vld1q(pSamples); + acc0 = vrmlaldavhq(vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamples[1]); + acc1 = vrmlaldavhq(vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamples[2]); + acc2 = vrmlaldavhq(vecIn0, vecCoeffs); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + *pOutput++ = (q31_t) acc0; + *pOutput++ = (q31_t) acc1; + *pOutput++ = (q31_t) acc2; + } + break; + + case 2: + { + /* + * Save 4 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + vecIn0 = vld1q(pSamples); + acc0 = vrmlaldavhq(vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamples[1]); + acc1 = vrmlaldavhq(vecIn0, vecCoeffs); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + + *pOutput++ = (q31_t) acc0; + *pOutput++ = (q31_t) acc1; + } + break; + + case 1: + { + /* + * Save 4 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + vecIn0 = vld1q(pSamples); + acc0 = vrmlaldavhq(vecIn0, vecCoeffs); + + acc0 = asrl(acc0, 23); + + *pOutput++ = (q31_t) acc0; + } + break; + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = (numTaps-1) >> 2; + while (blkCnt > 0U) + { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 4; + pTempDest += 4; + blkCnt--; + } + blkCnt = (numTaps-1) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_s32(pTempDest, vld1q(pTempSrc), p0); + } +} + + + +static void arm_fir_q31_5_8_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 8 + #define NBVECTAPS (NBTAPS / 4) + FIR_Q31_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +static void arm_fir_q31_9_12_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 12 + #define NBVECTAPS (NBTAPS / 4) + FIR_Q31_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +static void arm_fir_q31_13_16_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 16 + #define NBVECTAPS (NBTAPS / 4) + FIR_Q31_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +static void arm_fir_q31_17_20_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 20 + #define NBVECTAPS (NBTAPS / 4) + FIR_Q31_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +static void arm_fir_q31_21_24_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 24 + #define NBVECTAPS (NBTAPS / 4) + FIR_Q31_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +static void arm_fir_q31_25_28_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 28 + #define NBVECTAPS (NBTAPS / 4) + FIR_Q31_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + +static void arm_fir_q31_29_32_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, + uint32_t blockSize) +{ + q31_t *pRefStatePtr = S->pState + 2*ROUND_UP(blockSize, 4); + q31_t *pState = pRefStatePtr; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + const q31_t *pSamples; /* Temporary pointer to the sample buffer */ + q31_t *pOutput; /* Temporary pointer to the output buffer */ + const q31_t *pTempSrc; /* Temporary pointer to the source data */ + q31_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t blkCnt; + q63_t acc0, acc1, acc2, acc3; + +#define MAX_VECT_BATCH 7 + + /* + * pre-load 28 1st coefs + */ + q31x4_t vecCoeffs0 = vld1q(pCoeffs + 4 * 0); + q31x4_t vecCoeffs1 = vld1q(pCoeffs + 4 * 1); + q31x4_t vecCoeffs2 = vld1q(pCoeffs + 4 * 2); + q31x4_t vecCoeffs3 = vld1q(pCoeffs + 4 * 3); + q31x4_t vecCoeffs4 = vld1q(pCoeffs + 4 * 4); + q31x4_t vecCoeffs5 = vld1q(pCoeffs + 4 * 5); + q31x4_t vecCoeffs6 = vld1q(pCoeffs + 4 * 6); + + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + pTempSrc = pSrc; + pSamples = pState; + + q63_t *arm_fir_partial_accu_ptr = (q63_t*)S->pState; + + blkCnt = blockSize >> 2; + while (blkCnt > 0) { + /* + * Save 4 input samples in the history buffer + */ + vstrwq_s32(pStateCur, vldrwq_s32(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + const q31_t *pSmp; + q31x4_t vecIn0; + + pSmp = &pSamples[0]; + + vecIn0 = vld1q(pSmp); + acc0 = vrmlaldavhq(vecIn0, vecCoeffs0); + vecIn0 = vld1q(pSmp + 4 * 1); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs1); + vecIn0 = vld1q(pSmp + 4 * 2); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs2); + vecIn0 = vld1q(pSmp + 4 * 3); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs3); + vecIn0 = vld1q(pSmp + 4 * 4); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs4); + vecIn0 = vld1q(pSmp + 4 * 5); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs5); + vecIn0 = vld1q(pSmp + 4 * 6); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs6); + + *arm_fir_partial_accu_ptr++ = acc0; + + pSmp = &pSamples[1]; + + vecIn0 = vld1q(pSmp); + acc1 = vrmlaldavhq(vecIn0, vecCoeffs0); + vecIn0 = vld1q(pSmp + 4 * 1); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs1); + vecIn0 = vld1q(pSmp + 4 * 2); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs2); + vecIn0 = vld1q(pSmp + 4 * 3); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs3); + vecIn0 = vld1q(pSmp + 4 * 4); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs4); + vecIn0 = vld1q(pSmp + 4 * 5); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs5); + vecIn0 = vld1q(pSmp + 4 * 6); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs6); + + *arm_fir_partial_accu_ptr++ = acc1; + + pSmp = &pSamples[2]; + + vecIn0 = vld1q(pSmp); + acc2 = vrmlaldavhq(vecIn0, vecCoeffs0); + vecIn0 = vld1q(pSmp + 4 * 1); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs1); + vecIn0 = vld1q(pSmp + 4 * 2); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs2); + vecIn0 = vld1q(pSmp + 4 * 3); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs3); + vecIn0 = vld1q(pSmp + 4 * 4); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs4); + vecIn0 = vld1q(pSmp + 4 * 5); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs5); + vecIn0 = vld1q(pSmp + 4 * 6); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs6); + *arm_fir_partial_accu_ptr++ = acc2; + + pSmp = &pSamples[3]; + + vecIn0 = vld1q(pSmp); + acc3 = vrmlaldavhq(vecIn0, vecCoeffs0); + vecIn0 = vld1q(pSmp + 4 * 1); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs1); + vecIn0 = vld1q(pSmp + 4 * 2); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs2); + vecIn0 = vld1q(pSmp + 4 * 3); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs3); + vecIn0 = vld1q(pSmp + 4 * 4); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs4); + vecIn0 = vld1q(pSmp + 4 * 5); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs5); + vecIn0 = vld1q(pSmp + 4 * 6); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs6); + + *arm_fir_partial_accu_ptr++ = acc3; + + pSamples += 4; + /* + * Decrement the sample block loop counter + */ + blkCnt--; + } + + + /* reminder */ + + /* load last 4 coef */ + vecCoeffs0 = vld1q(pCoeffs + 4 * MAX_VECT_BATCH); + arm_fir_partial_accu_ptr = (q63_t*)S->pState; + pOutput = pDst; + pSamples = pState + (MAX_VECT_BATCH * 4); + + + blkCnt = blockSize >> 2; + while (blkCnt > 0) { + q31x4_t vecIn0; + + /* reload intermediate MAC */ + acc0 = *arm_fir_partial_accu_ptr++; + acc1 = *arm_fir_partial_accu_ptr++; + acc2 = *arm_fir_partial_accu_ptr++; + acc3 = *arm_fir_partial_accu_ptr++; + + + vecIn0 = vld1q(&pSamples[0]); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs0); + + vecIn0 = vld1q(&pSamples[1]); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs0); + + vecIn0 = vld1q(&pSamples[2]); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs0); + + vecIn0 = vld1q(&pSamples[3]); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs0); + + *pOutput++ = asrl(acc0, 23); + *pOutput++ = asrl(acc1, 23); + *pOutput++ = asrl(acc2, 23); + *pOutput++ = asrl(acc3, 23); + + pSamples += 4; + /* + * Decrement the sample block loop counter + */ + blkCnt--; + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = numTaps - 1; + do { + mve_pred16_t p = vctp32q(blkCnt); + + vstrwq_p_s32(pTempDest, vldrwq_z_s32(pTempSrc, p), p); + pTempSrc += 4; + pTempDest += 4; + blkCnt -= 4; + } + while (blkCnt > 0); +} + + + +void arm_fir_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pRefStatePtr = S->pState + 2*ROUND_UP(blockSize, 4); + q31_t *pState = pRefStatePtr; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + const q31_t *pSamples; /* Temporary pointer to the sample buffer */ + q31_t *pOutput; /* Temporary pointer to the output buffer */ + const q31_t *pTempSrc; /* Temporary pointer to the source data */ + q31_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t blkCnt; + q31x4_t vecIn0; + uint32_t tapsBlkCnt = (numTaps + 3) / 4; + q63_t acc0, acc1, acc2, acc3; + q31x4_t vecCoeffs; + + + /* + * [1 to 32 taps] specialized routines + */ + if (numTaps <= 4) + { + arm_fir_q31_1_4_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 8) + { + arm_fir_q31_5_8_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 12) + { + arm_fir_q31_9_12_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 16) + { + arm_fir_q31_13_16_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 20) + { + arm_fir_q31_17_20_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 24) + { + arm_fir_q31_21_24_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 28) + { + arm_fir_q31_25_28_mve(S, pSrc, pDst, blockSize); + return; + } + else if ((numTaps <= 32) && (blockSize >= 32)) + { + arm_fir_q31_29_32_mve(S, pSrc, pDst, blockSize); + return; + } + + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + pSamples = pState; + pTempSrc = pSrc; + pOutput = pDst; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + const q31_t *pCoeffsTmp = pCoeffs; + const q31_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + acc3 = 0LL; + + /* + * Save 4 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + int i = tapsBlkCnt; + while (i > 0) + { + /* + * load 4 coefs + */ + vecCoeffs = *(q31x4_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[1]); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[2]); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[3]); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs); + + pSamplesTmp += 4; + pCoeffsTmp += 4; + /* + * Decrement the taps block loop counter + */ + i--; + } + + /* .54-> .31 conversion and store accumulators */ + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + *pOutput++ = (q31_t) acc0; + *pOutput++ = (q31_t) acc1; + *pOutput++ = (q31_t) acc2; + *pOutput++ = (q31_t) acc3; + + pSamples += 4; + + /* + * Decrement the sample block loop counter + */ + blkCnt--; + } + + int32_t residual = blockSize & 3; + switch (residual) + { + case 3: + { + const q31_t *pCoeffsTmp = pCoeffs; + const q31_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + + /* + * Save 4 input samples in the history buffer + */ + *(q31x4_t *) pStateCur = *(q31x4_t *) pTempSrc; + pStateCur += 4; + pTempSrc += 4; + + int i = tapsBlkCnt; + while (i > 0) + { + vecCoeffs = *(q31x4_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[1]); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[2]); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs); + + pSamplesTmp += 4; + pCoeffsTmp += 4; + i--; + } + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + *pOutput++ = (q31_t) acc0; + *pOutput++ = (q31_t) acc1; + *pOutput++ = (q31_t) acc2; + } + break; + + case 2: + { + const q31_t *pCoeffsTmp = pCoeffs; + const q31_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + acc1 = 0LL; + + /* + * Save 4 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + int i = tapsBlkCnt; + while (i > 0) + { + vecCoeffs = *(q31x4_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[1]); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs); + + pSamplesTmp += 4; + pCoeffsTmp += 4; + i--; + } + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + + *pOutput++ = (q31_t) acc0; + *pOutput++ = (q31_t) acc1; + } + break; + + case 1: + { + const q31_t *pCoeffsTmp = pCoeffs; + const q31_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + + /* + * Save 4 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + int i = tapsBlkCnt; + while (i > 0) + { + vecCoeffs = *(q31x4_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs); + + pSamplesTmp += 4; + pCoeffsTmp += 4; + i--; + } + + acc0 = asrl(acc0, 23); + + *pOutput++ = (q31_t) acc0; + } + break; + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = (numTaps - 1U) >> 2; + while (blkCnt > 0) + { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 4; + pTempDest += 4; + blkCnt--; + } + blkCnt = (numTaps - 1U) & 3; + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_s32(pTempDest, vld1q(pTempSrc), p0); + } +} + +#else +void arm_fir_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px; /* Temporary pointer for state buffer */ + const q31_t *pb; /* Temporary pointer for coefficient buffer */ + q63_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc1, acc2; /* Accumulators */ + q31_t x0, x1, x2; /* Temporary variables to hold state values */ + q31_t c0; /* Temporary variable to hold coefficient value */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + + blkCnt = blockSize / 3; + + while (blkCnt > 0U) + { + /* Copy 3 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the first 2 samples from the state buffer: x[n-numTaps], x[n-numTaps-1] */ + x0 = *px++; + x1 = *px++; + + /* Loop unrolling: process 3 taps at a time. */ + tapCnt = numTaps / 3; + + while (tapCnt > 0U) + { + /* Read the b[numTaps] coefficient */ + c0 = *pb; + + /* Read x[n-numTaps-2] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += ((q63_t) x0 * c0); + acc1 += ((q63_t) x1 * c0); + acc2 += ((q63_t) x2 * c0); + + /* Read the coefficient and state */ + c0 = *(pb + 1U); + x0 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += ((q63_t) x1 * c0); + acc1 += ((q63_t) x2 * c0); + acc2 += ((q63_t) x0 * c0); + + /* Read the coefficient and state */ + c0 = *(pb + 2U); + x1 = *(px++); + + /* update coefficient pointer */ + pb += 3U; + + /* Perform the multiply-accumulates */ + acc0 += ((q63_t) x2 * c0); + acc1 += ((q63_t) x0 * c0); + acc2 += ((q63_t) x1 * c0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = numTaps % 0x3U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += ((q63_t) x0 * c0); + acc1 += ((q63_t) x1 * c0); + acc2 += ((q63_t) x2 * c0); + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by 3 to process the next group of 3 samples */ + pState = pState + 3; + + /* The result is in 2.30 format. Convert to 1.31 and store in destination buffer. */ + *pDst++ = (q31_t) (acc0 >> 31U); + *pDst++ = (q31_t) (acc1 >> 31U); + *pDst++ = (q31_t) (acc2 >> 31U); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x3U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + do + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + acc0 += (q63_t) *px++ * *pb++; + + i--; + } while (i > 0U); + + /* Result is in 2.62 format. Convert to 1.31 and store in destination buffer. */ + *pDst++ = (q31_t) (acc0 >> 31U); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of FIR group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c new file mode 100644 index 00000000..c05fa321 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c @@ -0,0 +1,714 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_q7.c + * Description: Q7 FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for Q7 FIR filter. + @param[in] S points to an instance of the Q7 FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + The accumulator is converted to 18.7 format by discarding the low 7 bits. + Finally, the result is truncated to 1.7 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define FIR_Q7_CORE(pOutput, nbAcc, nbVecTaps, pSample, vecCoeffs) \ + for (int j = 0; j < nbAcc; j++) { \ + const q7_t *pSmp = &pSample[j]; \ + q31_t acc[4]; \ + \ + acc[j] = 0; \ + for (int i = 0; i < nbVecTaps; i++) { \ + vecIn0 = vld1q(pSmp + 16 * i); \ + acc[j] = vmladavaq(acc[j], vecIn0, vecCoeffs[i]); \ + } \ + *pOutput++ = (q7_t) __SSAT((acc[j] >> 7U), 8); \ + } + +#define FIR_Q7_MAIN_CORE() \ +{ \ + q7_t *pState = S->pState; /* State pointer */ \ + const q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ \ + q7_t *pStateCur; /* Points to the current sample of the state */ \ + const q7_t *pSamples; /* Temporary pointer to the sample buffer */ \ + q7_t *pOutput; /* Temporary pointer to the output buffer */ \ + const q7_t *pTempSrc; /* Temporary pointer to the source data */ \ + q7_t *pTempDest; /* Temporary pointer to the destination buffer */\ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */\ + int32_t blkCnt; \ + q7x16_t vecIn0; \ + \ + /* \ + * load coefs \ + */ \ + q7x16_t vecCoeffs[NBVECTAPS]; \ + \ + for (int i = 0; i < NBVECTAPS; i++) \ + vecCoeffs[i] = vldrbq_s8(pCoeffs + 16 * i); \ + \ + /* \ + * pState points to state array which contains previous frame (numTaps - 1) samples \ + * pStateCur points to the location where the new input data should be written \ + */ \ + pStateCur = &(pState[(numTaps - 1u)]); \ + pTempSrc = pSrc; \ + pSamples = pState; \ + pOutput = pDst; \ + \ + blkCnt = blockSize >> 2; \ + while (blkCnt > 0) { \ + /* \ + * Save 4 input samples in the history buffer \ + */ \ + vstrbq_s32(pStateCur, vldrbq_s32(pTempSrc)); \ + pStateCur += 4; \ + pTempSrc += 4; \ + \ + FIR_Q7_CORE(pOutput, 4, NBVECTAPS, pSamples, vecCoeffs); \ + pSamples += 4; \ + \ + blkCnt--; \ + } \ + \ + /* tail */ \ + int32_t residual = blockSize & 3; \ + \ + for (int i = 0; i < residual; i++) \ + *pStateCur++ = *pTempSrc++; \ + \ + FIR_Q7_CORE(pOutput, residual, NBVECTAPS, pSamples, vecCoeffs); \ + \ + \ + /* \ + * Copy the samples back into the history buffer start \ + */ \ + pTempSrc = &pState[blockSize]; \ + pTempDest = pState; \ + blkCnt = numTaps - 1; \ + do { \ + mve_pred16_t p = vctp8q(blkCnt); \ + \ + vstrbq_p_s8(pTempDest, vldrbq_z_s8(pTempSrc, p), p); \ + pTempSrc += 16; \ + pTempDest += 16; \ + blkCnt -= 16; \ + } \ + while (blkCnt > 0); \ +} + + +static void arm_fir_q7_49_64_mve(const arm_fir_instance_q7 * S, + const q7_t * __restrict pSrc, + q7_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 64 + #define NBVECTAPS (NBTAPS / 16) + FIR_Q7_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +void arm_fir_q7_33_48_mve(const arm_fir_instance_q7 * S, + const q7_t * __restrict pSrc, + q7_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 48 + #define NBVECTAPS (NBTAPS / 16) + FIR_Q7_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + +static void arm_fir_q7_17_32_mve(const arm_fir_instance_q7 * S, + const q7_t * __restrict pSrc, + q7_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 32 + #define NBVECTAPS (NBTAPS / 16) + FIR_Q7_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +void arm_fir_q7_1_16_mve(const arm_fir_instance_q7 * S, + const q7_t * __restrict pSrc, + q7_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 16 + #define NBVECTAPS (NBTAPS / 16) + FIR_Q7_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + +void arm_fir_q7( + const arm_fir_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + q7_t *pState = S->pState; /* State pointer */ + const q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q7_t *pStateCur; /* Points to the current sample of the state */ + const q7_t *pSamples; /* Temporary pointer to the sample buffer */ + q7_t *pOutput; /* Temporary pointer to the output buffer */ + const q7_t *pTempSrc; /* Temporary pointer to the source data */ + q7_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t blkCnt; + q7x16_t vecIn0; + uint32_t tapsBlkCnt = (numTaps + 15) / 16; + q31_t acc0, acc1, acc2, acc3; + q7x16_t vecCoeffs; + + if (numTaps <= 16) + { + /* + * [1 to 16 taps] specialized routine + */ + arm_fir_q7_1_16_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 32) + { + /* + * [17 to 32 taps] specialized routine + */ + arm_fir_q7_17_32_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 48) + { + /* + * [33 to 48 taps] specialized routine + */ + arm_fir_q7_33_48_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 64) + { + /* + * [49 to 64 taps] specialized routine + */ + arm_fir_q7_49_64_mve(S, pSrc, pDst, blockSize); + return; + } + + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + pSamples = pState; + pTempSrc = pSrc; + pOutput = pDst; + blkCnt = blockSize >> 2; + + /* + * outer samples loop + */ + while (blkCnt > 0U) + { + const q7_t *pCoeffsTmp = pCoeffs; + const q7_t *pSamplesTmp = pSamples; + + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + /* + * Save 16 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 16; + pTempSrc += 16; + + /* + * inner coefficients loop + */ + int i = tapsBlkCnt; + while (i > 0) + { + /* + * load 16 coefs + */ + vecCoeffs = *(q7x16_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmladavaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[1]); + acc1 = vmladavaq(acc1, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[2]); + acc2 = vmladavaq(acc2, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[3]); + acc3 = vmladavaq(acc3, vecIn0, vecCoeffs); + + pSamplesTmp += 16; + pCoeffsTmp += 16; + /* + * Decrement the taps block loop counter + */ + i--; + } + /* + * Store the 1.7 format filter output in destination buffer + */ + *pOutput++ = (q7_t) __SSAT((acc0 >> 7U), 8); + *pOutput++ = (q7_t) __SSAT((acc1 >> 7U), 8); + *pOutput++ = (q7_t) __SSAT((acc2 >> 7U), 8); + *pOutput++ = (q7_t) __SSAT((acc3 >> 7U), 8); + + pSamples += 4; + /* + * Decrement the sample block loop counter + */ + blkCnt--; + } + + uint32_t residual = blockSize & 3; + switch (residual) + { + case 3: + { + const q7_t *pCoeffsTmp = pCoeffs; + const q7_t *pSamplesTmp = pSamples; + + acc0 = 0; + acc1 = 0; + acc2 = 0; + /* + * Save 16 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 16; + pTempSrc += 16; + + int i = tapsBlkCnt; + while (i > 0) + { + vecCoeffs = *(q7x16_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmladavaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[4]); + acc1 = vmladavaq(acc1, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[8]); + acc2 = vmladavaq(acc2, vecIn0, vecCoeffs); + + pSamplesTmp += 16; + pCoeffsTmp += 16; + i--; + } + + *pOutput++ = (q7_t) __SSAT((acc0 >> 7U), 8); + *pOutput++ = (q7_t) __SSAT((acc1 >> 7U), 8); + *pOutput++ = (q7_t) __SSAT((acc2 >> 7U), 8); + } + break; + + case 2: + { + const q7_t *pCoeffsTmp = pCoeffs; + const q7_t *pSamplesTmp = pSamples; + + acc0 = 0; + acc1 = 0; + /* + * Save 16 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 16; + pTempSrc += 16; + + int i = tapsBlkCnt; + while (i > 0) + { + vecCoeffs = *(q7x16_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmladavaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[4]); + acc1 = vmladavaq(acc1, vecIn0, vecCoeffs); + + pSamplesTmp += 16; + pCoeffsTmp += 16; + i--; + } + + *pOutput++ = (q7_t) __SSAT((acc0 >> 7U), 8); + *pOutput++ = (q7_t) __SSAT((acc1 >> 7U), 8); + } + break; + + case 1: + { + const q7_t *pCoeffsTmp = pCoeffs; + const q7_t *pSamplesTmp = pSamples; + + acc0 = 0; + /* + * Save 16 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 16; + pTempSrc += 16; + + int i = tapsBlkCnt; + while (i > 0) + { + vecCoeffs = *(q7x16_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmladavaq(acc0, vecIn0, vecCoeffs); + + pSamplesTmp += 16; + pCoeffsTmp += 16; + i--; + } + *pOutput++ = (q7_t) __SSAT((acc0 >> 7U), 8); + } + break; + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = numTaps >> 4; + while (blkCnt > 0U) + { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 16; + pTempDest += 16; + blkCnt--; + } + blkCnt = numTaps & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vstrbq_p_s8(pTempDest, vld1q(pTempSrc), p0); + } +} +#else +void arm_fir_q7( + const arm_fir_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + q7_t *pState = S->pState; /* State pointer */ + const q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q7_t *pStateCurnt; /* Points to the current sample of the state */ + q7_t *px; /* Temporary pointer for state buffer */ + const q7_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t acc0; /* Accumulators */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q7_t x0, x1, x2, x3, c0; /* Temporary variables to hold state */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the first 3 samples from the state buffer: + * x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Loop unrolling. Process 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numTaps-4 coefficients. */ + while (tapCnt > 0U) + { + /* Read the b[numTaps] coefficient */ + c0 = *pb; + + /* Read x[n-numTaps-3] sample */ + x3 = *px; + + /* acc0 += b[numTaps] * x[n-numTaps] */ + acc0 += ((q15_t) x0 * c0); + + /* acc1 += b[numTaps] * x[n-numTaps-1] */ + acc1 += ((q15_t) x1 * c0); + + /* acc2 += b[numTaps] * x[n-numTaps-2] */ + acc2 += ((q15_t) x2 * c0); + + /* acc3 += b[numTaps] * x[n-numTaps-3] */ + acc3 += ((q15_t) x3 * c0); + + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb + 1U); + + /* Read x[n-numTaps-4] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulates */ + acc0 += ((q15_t) x1 * c0); + acc1 += ((q15_t) x2 * c0); + acc2 += ((q15_t) x3 * c0); + acc3 += ((q15_t) x0 * c0); + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb + 2U); + + /* Read x[n-numTaps-5] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulates */ + acc0 += ((q15_t) x2 * c0); + acc1 += ((q15_t) x3 * c0); + acc2 += ((q15_t) x0 * c0); + acc3 += ((q15_t) x1 * c0); + + /* Read the b[numTaps-3] coefficients */ + c0 = *(pb + 3U); + + /* Read x[n-numTaps-6] sample */ + x2 = *(px + 3U); + + /* Perform the multiply-accumulates */ + acc0 += ((q15_t) x3 * c0); + acc1 += ((q15_t) x0 * c0); + acc2 += ((q15_t) x1 * c0); + acc3 += ((q15_t) x2 * c0); + + /* update coefficient pointer */ + pb += 4U; + px += 4U; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x3 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += ((q15_t) x0 * c0); + acc1 += ((q15_t) x1 * c0); + acc2 += ((q15_t) x2 * c0); + acc3 += ((q15_t) x3 * c0); + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The results in the 4 accumulators are in 2.62 format. Convert to 1.31 + Then store the 4 outputs in the destination buffer. */ + acc0 = __SSAT((acc0 >> 7U), 8); + *pDst++ = acc0; + acc1 = __SSAT((acc1 >> 7U), 8); + *pDst++ = acc1; + acc2 = __SSAT((acc2 >> 7U), 8); + *pDst++ = acc2; + acc3 = __SSAT((acc3 >> 7U), 8); + *pDst++ = acc3; + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + while (i > 0U) + { + acc0 += (q15_t) * (px++) * (*(pb++)); + i--; + } + + /* The result is in 2.14 format. Convert to 1.7 + Then store the output in the destination buffer. */ + *pDst++ = __SSAT((acc0 >> 7U), 8); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of FIR group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c new file mode 100644 index 00000000..e6f4d78c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c @@ -0,0 +1,341 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_f32.c + * Description: Floating-point sparse FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup FIR_Sparse Finite Impulse Response (FIR) Sparse Filters + + This group of functions implements sparse FIR filters. + Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero. + Sparse filters are used for simulating reflections in communications and audio applications. + + There are separate functions for Q7, Q15, Q31, and floating-point data types. + The functions operate on blocks of input and output data and each call to the function processes + blockSize samples through the filter. pSrc and + pDst points to input and output arrays respectively containing blockSize values. + + @par Algorithm + The sparse filter instant structure contains an array of tap indices pTapDelay which specifies the locations of the non-zero coefficients. + This is in addition to the coefficient array b. + The implementation essentially skips the multiplications by zero and leads to an efficient realization. +
+      y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]
+  
+ @par + \image html FIRSparse.gif "Sparse FIR filter. b[n] represents the filter coefficients" + @par + pCoeffs points to a coefficient array of size numTaps; + pTapDelay points to an array of nonzero indices and is also of size numTaps; + pState points to a state array of size maxDelay + blockSize, where + maxDelay is the largest offset value that is ever used in the pTapDelay array. + Some of the processing functions also require temporary working buffers. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 4 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, pTapDelay, maxDelay, stateIndex, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + The code below statically initializes each of the 4 different data type filter instance structures +
+      arm_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+      arm_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+      arm_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+      arm_fir_sparse_instance_q7 S =  {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+  
+ + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the sparse FIR filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Processing function for the floating-point sparse FIR filter. + @param[in] S points to an instance of the floating-point sparse FIR structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] pScratchIn points to a temporary buffer of size blockSize + @param[in] blockSize number of input samples to process + @return none + */ + +void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *px; /* Scratch buffer pointer */ + float32_t *py = pState; /* Temporary pointers for state buffer */ + float32_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + float32_t *pOut; /* Destination pointer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + float32_t coeff = *pCoeffs++; /* Read the first coefficient value */ + + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1, (int32_t *) pSrc, 1, blockSize); + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiplications and store in destination buffer */ + *pOut++ = *px++ * coeff; + + *pOut++ = *px++ * coeff; + + *pOut++ = *px++ * coeff; + + *pOut++ = *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiplication and store in destination buffer */ + *pOut++ = *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 2U; + + while (tapCnt > 0U) + { + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + + *pOut++ += *px++ * coeff; + + *pOut++ += *px++ * coeff; + + *pOut++ += *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Decrement tap loop counter */ + tapCnt--; + } + + /* Compute last tap without the final read of pTapDelay */ + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + *pOut++ += *px++ * coeff; + *pOut++ += *px++ * coeff; + *pOut++ += *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of FIR_Sparse group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c new file mode 100644 index 00000000..dce0d6f7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_init_f32.c + * Description: Floating-point sparse FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Initialization function for the floating-point sparse FIR filter. + @param[in,out] S points to an instance of the floating-point sparse FIR structure + @param[in] numTaps number of nonzero coefficients in the filter + @param[in] pCoeffs points to the array of filter coefficients + @param[in] pState points to the state buffer + @param[in] pTapDelay points to the array of offset times + @param[in] maxDelay maximum offset time supported + @param[in] blockSize number of samples that will be processed per block + @return none + + @par Details + pCoeffs holds the filter coefficients and has length numTaps. + pState holds the filter's state variables and must be of length + maxDelay + blockSize, where maxDelay + is the maximum number of delay line values. + blockSize is the + number of samples processed by the arm_fir_sparse_f32() function. + */ + +void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign TapDelay pointer */ + S->pTapDelay = pTapDelay; + + /* Assign MaxDelay */ + S->maxDelay = maxDelay; + + /* reset the stateIndex to 0 */ + S->stateIndex = 0U; + + /* Clear state buffer and size is always maxDelay + blockSize */ + memset(pState, 0, (maxDelay + blockSize) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Sparse group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c new file mode 100644 index 00000000..6a48743e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_init_q15.c + * Description: Q15 sparse FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Initialization function for the Q15 sparse FIR filter. + @param[in,out] S points to an instance of the Q15 sparse FIR structure + @param[in] numTaps number of nonzero coefficients in the filter + @param[in] pCoeffs points to the array of filter coefficients + @param[in] pState points to the state buffer + @param[in] pTapDelay points to the array of offset times + @param[in] maxDelay maximum offset time supported + @param[in] blockSize number of samples that will be processed per block + @return none + + @par Details + pCoeffs holds the filter coefficients and has length numTaps. + pState holds the filter's state variables and must be of length + maxDelay + blockSize, where maxDelay + is the maximum number of delay line values. + blockSize is the + number of words processed by arm_fir_sparse_q15() function. + */ + +void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign TapDelay pointer */ + S->pTapDelay = pTapDelay; + + /* Assign MaxDelay */ + S->maxDelay = maxDelay; + + /* reset the stateIndex to 0 */ + S->stateIndex = 0U; + + /* Clear state buffer and size is always maxDelay + blockSize */ + memset(pState, 0, (maxDelay + blockSize) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Sparse group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c new file mode 100644 index 00000000..a333f1cc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_init_q31.c + * Description: Q31 sparse FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Initialization function for the Q31 sparse FIR filter. + @param[in,out] S points to an instance of the Q31 sparse FIR structure + @param[in] numTaps number of nonzero coefficients in the filter + @param[in] pCoeffs points to the array of filter coefficients + @param[in] pState points to the state buffer + @param[in] pTapDelay points to the array of offset times + @param[in] maxDelay maximum offset time supported + @param[in] blockSize number of samples that will be processed per block + @return none + + @par Details + pCoeffs holds the filter coefficients and has length numTaps. + pState holds the filter's state variables and must be of length + maxDelay + blockSize, where maxDelay + is the maximum number of delay line values. + blockSize is the number of words processed by arm_fir_sparse_q31() function. + */ + +void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign TapDelay pointer */ + S->pTapDelay = pTapDelay; + + /* Assign MaxDelay */ + S->maxDelay = maxDelay; + + /* reset the stateIndex to 0 */ + S->stateIndex = 0U; + + /* Clear state buffer and size is always maxDelay + blockSize */ + memset(pState, 0, (maxDelay + blockSize) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Sparse group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c new file mode 100644 index 00000000..3e2b9c9a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_init_q7.c + * Description: Q7 sparse FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Initialization function for the Q7 sparse FIR filter. + @param[in,out] S points to an instance of the Q7 sparse FIR structure + @param[in] numTaps number of nonzero coefficients in the filter + @param[in] pCoeffs points to the array of filter coefficients + @param[in] pState points to the state buffer + @param[in] pTapDelay points to the array of offset times + @param[in] maxDelay maximum offset time supported + @param[in] blockSize number of samples that will be processed per block + @return none + + @par Details + pCoeffs holds the filter coefficients and has length numTaps. + pState holds the filter's state variables and must be of length + maxDelay + blockSize, where maxDelay + is the maximum number of delay line values. + blockSize is the + number of samples processed by the arm_fir_sparse_q7() function. + */ + +void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign TapDelay pointer */ + S->pTapDelay = pTapDelay; + + /* Assign MaxDelay */ + S->maxDelay = maxDelay; + + /* reset the stateIndex to 0 */ + S->stateIndex = 0U; + + /* Clear state buffer and size is always maxDelay + blockSize */ + memset(pState, 0, (maxDelay + blockSize) * sizeof(q7_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Sparse group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c new file mode 100644 index 00000000..60669225 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c @@ -0,0 +1,341 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_q15.c + * Description: Q15 sparse FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Processing function for the Q15 sparse FIR filter. + @param[in] S points to an instance of the Q15 sparse FIR structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] pScratchIn points to a temporary buffer of size blockSize + @param[in] pScratchOut points to a temporary buffer of size blockSize + @param[in] blockSize number of input samples to process per call + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator. + Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator. + If the accumulator result overflows it will wrap around rather than saturate. + After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format. + In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits. + */ + +void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *px; /* Temporary pointers for scratch buffer */ + q15_t *py = pState; /* Temporary pointers for state buffer */ + q15_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q15_t *pOut = pDst; /* Working pointer for output */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q31_t *pScr2 = pScratchOut; /* Working pointer for scratch buffer of output values */ + q15_t coeff = *pCoeffs++; /* Read the first coefficient value */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t in1, in2; /* Temporary variables */ +#endif + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_q15(py, (int32_t) delaySize, &S->stateIndex, 1,pSrc, 1, blockSize); + + /* Loop over the number of taps. */ + tapCnt = numTaps; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q15(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) *px++ * coeff); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 2U; + + while (tapCnt > 0U) + { + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q15(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t) *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Decrement loop counter */ + tapCnt--; + } + + /* Compute last tap without the final read of pTapDelay */ + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q15(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t) *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* All the output values are in pScratchOut buffer. + Convert them into 1.15 format, saturate and store in the destination buffer. */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + in1 = *pScr2++; + in2 = *pScr2++; + +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = *pScr2++; + in2 = *pScr2++; + +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of FIR_Sparse group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c new file mode 100644 index 00000000..33c66df4 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c @@ -0,0 +1,357 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_q31.c + * Description: Q31 sparse FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Processing function for the Q31 sparse FIR filter. + @param[in] S points to an instance of the Q31 sparse FIR structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] pScratchIn points to a temporary buffer of size blockSize + @param[in] blockSize number of input samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The 1.31 x 1.31 multiplications are truncated to 2.30 format. + This leads to loss of precision on the intermediate multiplications and provides only a single guard bit. + If the accumulator result overflows, it wraps around rather than saturate. + In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits. + */ + +void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *px; /* Scratch buffer pointer */ + q31_t *py = pState; /* Temporary pointers for state buffer */ + q31_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q31_t *pOut; /* Destination pointer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q31_t coeff = *pCoeffs++; /* Read the first coefficient value */ + q31_t in; + q63_t out; /* Temporary output variable */ + + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1, + (int32_t *) pSrc, 1, blockSize); + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiplications and store in destination buffer */ + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiplication and store in destination buffer */ + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 2U; + + while (tapCnt > 0U) + { + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Decrement tap loop counter */ + tapCnt--; + } + + /* Compute last tap without the final read of pTapDelay */ + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t) * px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) * px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) * px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) * px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Working output pointer is updated */ + pOut = pDst; + + /* Output is converted into 1.31 format. */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + in = *pOut << 1; + *pOut++ = in; + in = *pOut << 1; + *pOut++ = in; + in = *pOut << 1; + *pOut++ = in; + in = *pOut << 1; + *pOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + in = *pOut << 1; + *pOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of FIR_Sparse group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c new file mode 100644 index 00000000..e47d889c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c @@ -0,0 +1,341 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_q7.c + * Description: Q7 sparse FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Processing function for the Q7 sparse FIR filter. + @param[in] S points to an instance of the Q7 sparse FIR structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] pScratchIn points to a temporary buffer of size blockSize + @param[in] pScratchOut points to a temporary buffer of size blockSize + @param[in] blockSize number of input samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + The accumulator is then converted to 18.7 format by discarding the low 7 bits. + Finally, the result is truncated to 1.7 format. + */ + +void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize) +{ + q7_t *pState = S->pState; /* State pointer */ + const q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q7_t *px; /* Scratch buffer pointer */ + q7_t *py = pState; /* Temporary pointers for state buffer */ + q7_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q7_t *pOut = pDst; /* Destination pointer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q31_t *pScr2 = pScratchOut; /* Working pointer for scratch buffer of output values */ + q31_t in; + q7_t coeff = *pCoeffs++; /* Read the coefficient value */ + +#if defined (ARM_MATH_LOOPUNROLL) + q7_t in1, in2, in3, in4; +#endif + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1, blockSize); + + /* Loop over the number of taps. */ + tapCnt = numTaps; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) *px++ * coeff); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 2U; + + while (tapCnt > 0U) + { + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t) * px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) * px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) * px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) * px++ * coeff); + *pScratchOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Decrement loop counter */ + tapCnt--; + } + + /* Compute last tap without the final read of pTapDelay */ + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* All the output values are in pScratchOut buffer. + Convert them into 1.15 format, saturate and store in the destination buffer. */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + in1 = (q7_t) __SSAT(*pScr2++ >> 7, 8); + in2 = (q7_t) __SSAT(*pScr2++ >> 7, 8); + in3 = (q7_t) __SSAT(*pScr2++ >> 7, 8); + in4 = (q7_t) __SSAT(*pScr2++ >> 7, 8); + + write_q7x4_ia (&pOut, __PACKq7(in1, in2, in3, in4)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of FIR_Sparse group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c new file mode 100644 index 00000000..bf0b178c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c @@ -0,0 +1,354 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_f32.c + * Description: Floating-point IIR Lattice filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup IIR_Lattice Infinite Impulse Response (IIR) Lattice Filters + + This set of functions implements lattice filters + for Q15, Q31 and floating-point data types. Lattice filters are used in a + variety of adaptive filter applications. The filter structure has feedforward and + feedback components and the net impulse response is infinite length. + The functions operate on blocks + of input and output data and each call to the function processes + blockSize samples through the filter. pSrc and + pDst point to input and output arrays containing blockSize values. + + @par Algorithm + \image html IIRLattice.gif "Infinite Impulse Response Lattice filter" + @par +
+      fN(n)   = x(n)
+      fm-1(n) = fm(n) - km * gm-1(n-1)   for m = N, N-1, ..., 1
+      gm(n)   = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ..., 1
+      y(n)    = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)
+  
+ @par + pkCoeffs points to array of reflection coefficients of size numStages. + Reflection Coefficients are stored in time-reversed order. + @par +
+     {kN, kN-1, ..., k1}
+  
+ @par + pvCoeffs points to the array of ladder coefficients of size (numStages+1). + Ladder coefficients are stored in time-reversed order. +
+      {vN, vN-1, ..., v0}
+  
+ @par + pState points to a state array of size numStages + blockSize. + The state variables shown in the figure above (the g values) are stored in the pState array. + The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pkCoeffs, pvCoeffs, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros and then manually initialize the instance structure as follows: +
+      arm_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};
+      arm_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};
+      arm_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};
+  
+ @par + where numStages is the number of stages in the filter; pState points to the state buffer array; + pkCoeffs points to array of the reflection coefficients; pvCoeffs points to the array of ladder coefficients. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the IIR lattice filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Processing function for the floating-point IIR lattice filter. + @param[in] S points to an instance of the floating-point IIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pStateCur; /* State current pointer */ + float32_t acc; /* Accumlator */ + float32_t fnext1, fnext2, gcurr1, gnext; /* Temporary variables for lattice stages */ + float32_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* Number of stages */ + uint32_t blkCnt, tapCnt; /* Temporary variables for counts */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t gcurr2; /* Temporary variables for lattice stages */ + float32_t k1, k2; + float32_t v1, v2, v3, v4; +#endif + + /* initialise loop count */ + blkCnt = blockSize; + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fnext2 = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0.0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numStages) >> 2U; + + while (tapCnt > 0U) + { + /* Read gN-1(n-1) from state buffer */ + gcurr1 = *px1; + + /* read reflection coefficient kN */ + k1 = *pk; + + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext1 = fnext2 - (k1 * gcurr1); + + /* read ladder coefficient vN */ + v1 = *pv; + + /* read next reflection coefficient kN-1 */ + k2 = *(pk + 1U); + + /* Read gN-2(n-1) from state buffer */ + gcurr2 = *(px1 + 1U); + + /* read next ladder coefficient vN-1 */ + v2 = *(pv + 1U); + + /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */ + fnext2 = fnext1 - (k2 * gcurr2); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = gcurr1 + (k1 * fnext1); + + /* read reflection coefficient kN-2 */ + k1 = *(pk + 2U); + + /* write gN(n) into state for next sample processing */ + *px2++ = gnext; + + /* Read gN-3(n-1) from state buffer */ + gcurr1 = *(px1 + 2U); + + /* y(n) += gN(n) * vN */ + acc += (gnext * v1); + + /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */ + fnext1 = fnext2 - (k1 * gcurr1); + + /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */ + gnext = gcurr2 + (k2 * fnext2); + + /* Read gN-4(n-1) from state buffer */ + gcurr2 = *(px1 + 3U); + + /* y(n) += gN-1(n) * vN-1 */ + acc += (gnext * v2); + + /* read reflection coefficient kN-3 */ + k2 = *(pk + 3U); + + /* write gN-1(n) into state for next sample processing */ + *px2++ = gnext; + + /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */ + fnext2 = fnext1 - (k2 * gcurr2); + + /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */ + gnext = gcurr1 + (k1 * fnext1); + + /* read ladder coefficient vN-2 */ + v3 = *(pv + 2U); + + /* y(n) += gN-2(n) * vN-2 */ + acc += (gnext * v3); + + /* write gN-2(n) into state for next sample processing */ + *px2++ = gnext; + + /* update pointer */ + pk += 4U; + + /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */ + gnext = (fnext2 * k2) + gcurr2; + + /* read next ladder coefficient vN-3 */ + v4 = *(pv + 3U); + + /* y(n) += gN-4(n) * vN-4 */ + acc += (gnext * v4); + + /* write gN-3(n) into state for next sample processing */ + *px2++ = gnext; + + /* update pointers */ + px1 += 4U; + pv += 4U; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numStages % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numStages; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + gcurr1 = *px1++; + /* Process sample for last taps */ + fnext1 = fnext2 - ((*pk) * gcurr1); + gnext = (fnext1 * (*pk++)) + gcurr1; + /* Output samples for last taps */ + acc += (gnext * (*pv++)); + *px2++ = gnext; + fnext2 = fnext1; + + /* Decrement loop counter */ + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += (fnext2 * (*pv)); + + *px2++ = fnext2; + + /* write out into pDst */ + *pDst++ = acc; + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + /* Copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numStages >> 2U; + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numStages % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = numStages; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of IIR_Lattice group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c new file mode 100644 index 00000000..389e1ea8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_init_f32.c + * Description: Floating-point IIR lattice filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Initialization function for the floating-point IIR lattice filter. + @param[in] S points to an instance of the floating-point IIR lattice structure + @param[in] numStages number of stages in the filter + @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages + @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1 + @param[in] pState points to state buffer. The array is of length numStages+blockSize + @param[in] blockSize number of samples to process + @return none + */ + +void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign reflection coefficient pointer */ + S->pkCoeffs = pkCoeffs; + + /* Assign ladder coefficient pointer */ + S->pvCoeffs = pvCoeffs; + + /* Clear state buffer and size is always blockSize + numStages */ + memset(pState, 0, (numStages + blockSize) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of IIR_Lattice group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c new file mode 100644 index 00000000..873c342a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_init_q15.c + * Description: Q15 IIR lattice filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Initialization function for the Q15 IIR lattice filter. + @param[in] S points to an instance of the Q15 IIR lattice structure + @param[in] numStages number of stages in the filter + @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages + @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1 + @param[in] pState points to state buffer. The array is of length numStages+blockSize + @param[in] blockSize number of samples to process + @return none + */ + +void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign reflection coefficient pointer */ + S->pkCoeffs = pkCoeffs; + + /* Assign ladder coefficient pointer */ + S->pvCoeffs = pvCoeffs; + + /* Clear state buffer and size is always blockSize + numStages */ + memset(pState, 0, (numStages + blockSize) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of IIR_Lattice group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c new file mode 100644 index 00000000..59b26d3c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_init_q31.c + * Description: Initialization function for the Q31 IIR lattice filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Initialization function for the Q31 IIR lattice filter. + @param[in] S points to an instance of the Q31 IIR lattice structure + @param[in] numStages number of stages in the filter + @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages + @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1 + @param[in] pState points to state buffer. The array is of length numStages+blockSize + @param[in] blockSize number of samples to process + @return none + */ + +void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign reflection coefficient pointer */ + S->pkCoeffs = pkCoeffs; + + /* Assign ladder coefficient pointer */ + S->pvCoeffs = pvCoeffs; + + /* Clear state buffer and size is always blockSize + numStages */ + memset(pState, 0, (numStages + blockSize) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of IIR_Lattice group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c new file mode 100644 index 00000000..d3cf7f66 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c @@ -0,0 +1,396 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_q15.c + * Description: Q15 IIR Lattice filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Processing function for the Q15 IIR lattice filter. + @param[in] S points to an instance of the Q15 IIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + +void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pStateCur; /* State current pointer */ + q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */ + q63_t acc; /* Accumlator */ + q15_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* Number of stages */ + uint32_t blkCnt, tapCnt; /* Temporary variables for counts */ + q15_t out; /* Temporary variable for output */ + +#if defined (ARM_MATH_DSP) && defined (ARM_MATH_LOOPUNROLL) + q15_t gnext1, gnext2; /* Temporary variables for lattice stages */ + q31_t v; /* Temporary variable for ladder coefficient */ +#endif + + /* initialise loop count */ + blkCnt = blockSize; + +#if defined (ARM_MATH_DSP) + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0; + + /* Process sample for first tap */ + gcurr = *px1++; + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr; + gnext = __SSAT(gnext, 16); + + /* write gN(n) into state for next sample processing */ + *px2++ = (q15_t) gnext; + + /* y(n) += gN(n) * vN */ + acc += (q31_t) ((gnext * (*pv++))); + + /* Update f values for next coefficient processing */ + fcurr = fnext; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numStages - 1U) >> 2U; + + while (tapCnt > 0U) + { + /* Process sample for 2nd, 6th ...taps */ + /* Read gN-2(n-1) from state buffer */ + gcurr = *px1++; + /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */ + fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */ + gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr; + gnext1 = (q15_t) __SSAT(gnext, 16); + /* write gN-1(n) into state for next sample processing */ + *px2++ = (q15_t) gnext1; + + /* Process sample for 3nd, 7th ...taps */ + /* Read gN-3(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 3rd, 7th .. taps */ + /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */ + fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15); + fcurr = __SSAT(fcurr, 16); + /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */ + gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr; + gnext2 = (q15_t) __SSAT(gnext, 16); + /* write gN-2(n) into state */ + *px2++ = (q15_t) gnext2; + + /* Read vN-1 and vN-2 at a time */ + v = read_q15x2_ia (&pv); + + /* Pack gN-1(n) and gN-2(n) */ + +#ifndef ARM_MATH_BIG_ENDIAN + gnext = __PKHBT(gnext1, gnext2, 16); +#else + gnext = __PKHBT(gnext2, gnext1, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* y(n) += gN-1(n) * vN-1 */ + /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */ + /* y(n) += gN-2(n) * vN-2 */ + /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */ + acc = __SMLALD(gnext, v, acc); + + /* Process sample for 4th, 8th ...taps */ + /* Read gN-4(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 4th, 8th .. taps */ + /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */ + fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + /* gN-3(n) = kN-3 * fN-1(n) + gN-1(n-1) */ + gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr; + gnext1 = (q15_t) __SSAT(gnext, 16); + /* write gN-3(n) for the next sample process */ + *px2++ = (q15_t) gnext1; + + /* Process sample for 5th, 9th ...taps */ + /* Read gN-5(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 5th, 9th .. taps */ + /* fN-5(n) = fN-4(n) - kN-4 * gN-5(n-1) */ + fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15); + fcurr = __SSAT(fcurr, 16); + /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */ + gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr; + gnext2 = (q15_t) __SSAT(gnext, 16); + /* write gN-4(n) for the next sample process */ + *px2++ = (q15_t) gnext2; + + /* Read vN-3 and vN-4 at a time */ + v = read_q15x2_ia (&pv); + + /* Pack gN-3(n) and gN-4(n) */ +#ifndef ARM_MATH_BIG_ENDIAN + gnext = __PKHBT(gnext1, gnext2, 16); +#else + gnext = __PKHBT(gnext2, gnext1, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* y(n) += gN-4(n) * vN-4 */ + /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */ + /* y(n) += gN-3(n) * vN-3 */ + /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */ + acc = __SMLALD(gnext, v, acc); + + /* Decrement loop counter */ + tapCnt--; + } + + fnext = fcurr; + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numStages - 1U) % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = (numStages - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample for last taps */ + fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr; + gnext = __SSAT(gnext, 16); + + /* Output samples for last taps */ + acc += (q31_t) (((q31_t) gnext * (*pv++))); + *px2++ = (q15_t) gnext; + fcurr = fnext; + + /* Decrement loop counter */ + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += (q31_t) (((q31_t) fnext * (*pv++))); + + out = (q15_t) __SSAT(acc >> 15, 16); + *px2++ = (q15_t) fnext; + + /* write out into pDst */ + *pDst++ = out; + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numStages >> 2U; + + while (tapCnt > 0U) + { + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numStages % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = (numStages - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#else /* #if defined (ARM_MATH_DSP) */ + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0; + + tapCnt = numStages; + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample */ + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = fcurr - ((gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = ((fnext * (*pk++)) >> 15) + gcurr; + gnext = __SSAT(gnext, 16); + + /* Output samples */ + /* y(n) += gN(n) * vN */ + acc += (q31_t) ((gnext * (*pv++))); + + /* write gN(n) into state for next sample processing */ + *px2++ = (q15_t) gnext; + + /* Update f values for next coefficient processing */ + fcurr = fnext; + + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += (q31_t) ((fnext * (*pv++))); + + out = (q15_t) __SSAT(acc >> 15, 16); + *px2++ = (q15_t) fnext; + + /* write out into pDst */ + *pDst++ = out; + + /* Advance the state pointer by 1 to process the next group of samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + tapCnt = numStages; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + @} end of IIR_Lattice group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c new file mode 100644 index 00000000..63344955 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c @@ -0,0 +1,356 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_q31.c + * Description: Q31 IIR Lattice filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Processing function for the Q31 IIR lattice filter. + @param[in] S points to an instance of the Q31 IIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits. + After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format. + */ + +void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pStateCur; /* State current pointer */ + q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */ + q63_t acc; /* Accumlator */ + q31_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* Number of stages */ + uint32_t blkCnt, tapCnt; /* Temporary variables for counts */ + + + /* initialise loop count */ + blkCnt = blockSize; + +#if defined (ARM_MATH_DSP) + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0; + + /* Process sample for first tap */ + gcurr = *px1++; + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31)); + + /* write gN-1(n-1) into state for next sample processing */ + *px2++ = gnext; + + /* y(n) += gN(n) * vN */ + acc += ((q63_t) gnext * *pv++); + + /* Update f values for next coefficient processing */ + fcurr = fnext; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numStages - 1U) >> 2U; + + while (tapCnt > 0U) + { + /* Process sample for 2nd, 6th ...taps */ + /* Read gN-2(n-1) from state buffer */ + gcurr = *px1++; + /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */ + fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31)); + /* y(n) += gN-1(n) * vN-1 */ + /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */ + acc += ((q63_t) gnext * *pv++); + /* write gN-1(n) into state for next sample processing */ + *px2++ = gnext; + + /* Process sample for 3nd, 7th ...taps */ + /* Read gN-3(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 3rd, 7th .. taps */ + /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */ + fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31)); + /* y(n) += gN-2(n) * vN-2 */ + /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */ + acc += ((q63_t) gnext * *pv++); + /* write gN-2(n) into state for next sample processing */ + *px2++ = gnext; + + /* Process sample for 4th, 8th ...taps */ + /* Read gN-4(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 4th, 8th .. taps */ + /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */ + fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31)); + /* y(n) += gN-3(n) * vN-3 */ + /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */ + acc += ((q63_t) gnext * *pv++); + /* write gN-3(n) into state for next sample processing */ + *px2++ = gnext; + + /* Process sample for 5th, 9th ...taps */ + /* Read gN-5(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 5th, 9th .. taps */ + /* fN-5(n) = fN-4(n) - kN-4 * gN-1(n-1) */ + fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31)); + /* y(n) += gN-4(n) * vN-4 */ + /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */ + acc += ((q63_t) gnext * *pv++); + + /* write gN-4(n) into state for next sample processing */ + *px2++ = gnext; + + /* Decrement loop counter */ + tapCnt--; + } + + fnext = fcurr; + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numStages - 1U) % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = (numStages - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample for last taps */ + fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31)); + + /* Output samples for last taps */ + acc += ((q63_t) gnext * *pv++); + *px2++ = gnext; + fcurr = fnext; + + /* Decrement loop counter */ + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += ((q63_t) fnext * *pv++); + + *px2++ = fnext; + + /* write out into pDst */ + *pDst++ = (q31_t) (acc >> 31U); + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + /* Copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numStages >> 2U; + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numStages % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = (numStages - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#else /* #if defined (ARM_MATH_DSP) */ + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0; + + tapCnt = numStages; + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample */ + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = clip_q63_to_q31(((q63_t) fcurr - ((q31_t) (((q63_t) gcurr * (*pk )) >> 31)))); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = clip_q63_to_q31(((q63_t) gcurr + ((q31_t) (((q63_t) fnext * (*pk++)) >> 31)))); + + /* Output samples */ + /* y(n) += gN(n) * vN */ + acc += ((q63_t) gnext * *pv++); + + /* write gN-1(n-1) into state for next sample processing */ + *px2++ = gnext; + + /* Update f values for next coefficient processing */ + fcurr = fnext; + + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += ((q63_t) fnext * *pv++); + + *px2++ = fnext; + + /* write out into pDst */ + *pDst++ = (q31_t) (acc >> 31U); + + /* Advance the state pointer by 1 to process the next group of samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + tapCnt = numStages; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + @} end of IIR_Lattice group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_f16.c new file mode 100644 index 00000000..36108c20 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_f16.c @@ -0,0 +1,276 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_levinson_durbin_f16.c + * Description: f16 version of Levinson Durbin algorithm + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup LD Levinson Durbin Algorithm + + */ + +/** + @addtogroup LD + @{ + */ + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_levinson_durbin_f16 built. Helium version has build issues with gcc." +#endif + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) + +#include "arm_helium_utils.h" + +#define LANE4567_MASK 0xFF00 + +void arm_levinson_durbin_f16(const float16_t *phi, + float16_t *a, + float16_t *err, + int nbCoefs) +{ + _Float16 e; + static const uint16_t revOffsetArray[8] = {7,6,5,4,3,2,1,0}; + + a[0] = (_Float16)phi[1] / (_Float16)phi[0]; + + e = (_Float16)phi[0] - (_Float16)phi[1] * (_Float16)a[0]; + for(int p=1; p < nbCoefs; p++) + { + _Float16 suma = 0.0f16; + _Float16 sumb = 0.0f16; + f16x8_t vecA,vecRevPhi,vecPhi,vecSumA, vecSumB; + _Float16 k; + uint32_t blkCnt; + const float16_t *pPhi,*pRevPhi,*pA; + uint16x8_t revOffset; + + int nb,j,i; + + revOffset = vld1q(revOffsetArray); + vecSumA = vdupq_n_f16(0.0f16); + vecSumB = vdupq_n_f16(0.0f16); + + pRevPhi = &phi[p-7]; + pPhi = &phi[1]; + pA = a; + + i = 0; + blkCnt = p >> 3; + while(blkCnt > 0) + { + vecA = vld1q(pA); + pA += 8; + + vecPhi = vld1q(pPhi); + pPhi += 8; + + vecRevPhi = vldrhq_gather_shifted_offset_f16(pRevPhi,revOffset); + pRevPhi -= 8; + + vecSumA = vfmaq(vecSumA,vecA,vecRevPhi); + vecSumB = vfmaq(vecSumB,vecA,vecPhi); + + i += 8; + blkCnt--; + + } + + suma = vecAddAcrossF16Mve(vecSumA); + sumb = vecAddAcrossF16Mve(vecSumB); + + blkCnt = p & 7; + while(blkCnt > 0) + { + suma += (_Float16)a[i] * (_Float16)phi[p - i]; + sumb += (_Float16)a[i] * (_Float16)phi[i + 1]; + + i++; + blkCnt--; + } + + k = ((_Float16)phi[p+1] - suma)/((_Float16)phi[0] - sumb); + + f16x8_t vecRevA,tmp; + static int16_t orgOffsetArray[8]={0,1,2,3,-1,-2,-3,-4}; + static const int16_t offsetIncArray[8]={4,4,4,4,-4,-4,-4,-4}; + + uint16x8_t offset,offsetInc,vecTmp; + + + offset = vld1q_u16((uint16_t*)orgOffsetArray); + vecTmp = vdupq_n_u16(p); + + offset = vaddq_m_u16(offset,offset,vecTmp,LANE4567_MASK); + offsetInc = vld1q_u16((uint16_t*)offsetIncArray); + + nb = p >> 3; + j=0; + for(int i = 0; i < nb ; i++) + { + + /* + x0=a[j] - k * a[p-1-j]; + x1=a[j+1] - k * a[p-2-j]; + x3=a[p-1-j] - k * a[j]; + x4=a[p-2-j] - k * a[j+1]; + + a[j] = x0; + a[j+1] = x1; + a[p-1-j] = x2; + a[p-2-j] = x3; + */ + + uint64_t tmpa,tmpb; + vecA = vldrhq_gather_shifted_offset_f16(a,offset); + + + tmpa = vgetq_lane_u64((uint64x2_t)vecA,0); + tmpb = vgetq_lane_u64((uint64x2_t)vecA,1); + vecRevA = (f16x8_t) vsetq_lane_u64(tmpb,(uint64x2_t)vecRevA,0); + vecRevA = (f16x8_t) vsetq_lane_u64(tmpa,(uint64x2_t)vecRevA,1); + + + tmp = vsubq(vecA,vmulq_n_f16(vecRevA,k)); + vstrhq_scatter_shifted_offset_f16(a, offset, tmp); + + offset = vaddq(offset,offsetInc); + + j+=4; + + } + + blkCnt = p & 7; + + if (blkCnt) + { + nb = blkCnt >> 1; + for(int i =0;i < nb ; i++) + { + _Float16 x,y; + + x=(_Float16)a[j] - (_Float16)k * (_Float16)a[p-1-j]; + y=(_Float16)a[p-1-j] - (_Float16)k * (_Float16)a[j]; + + a[j] = x; + a[p-1-j] = y; + + j++; + } + + nb = blkCnt & 1; + if (nb) + { + a[j]=(_Float16)a[j]- (_Float16)k * (_Float16)a[p-1-j]; + } + } + + + a[p] = k; + e = e * (1.0f16 - k*k); + + + } + *err = e; +} + +#else + +#if defined(ARM_FLOAT16_SUPPORTED) + +void arm_levinson_durbin_f16(const float16_t *phi, + float16_t *a, + float16_t *err, + int nbCoefs) +{ + _Float16 e; + + a[0] = (_Float16)phi[1] / (_Float16)phi[0]; + + e = (_Float16)phi[0] - (_Float16)phi[1] * (_Float16)a[0]; + for(int p=1; p < nbCoefs; p++) + { + _Float16 suma=0.0f16; + _Float16 sumb=0.0f16; + _Float16 k; + int nb,j; + + for(int i=0; i < p; i++) + { + suma += (_Float16)a[i] * (_Float16)phi[p - i]; + sumb += (_Float16)a[i] * (_Float16)phi[i + 1]; + } + + k = ((_Float16)phi[p+1]-suma)/((_Float16)phi[0] - sumb); + + + nb = p >> 1; + j=0; + for(int i =0;i < nb ; i++) + { + _Float16 x,y; + + x=(_Float16)a[j] - (_Float16)k * (_Float16)a[p-1-j]; + y=(_Float16)a[p-1-j] - (_Float16)k * (_Float16)a[j]; + + a[j] = x; + a[p-1-j] = y; + + j++; + } + + nb = p & 1; + if (nb) + { + a[j]=(_Float16)a[j]- (_Float16)k * (_Float16)a[p-1-j]; + } + + a[p] = k; + e = e * (1.0f16 - k*k); + + + } + *err = e; +} +#endif /* defined(ARM_FLOAT16_SUPPORTED */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of LD group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_f32.c new file mode 100644 index 00000000..b244048c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_f32.c @@ -0,0 +1,279 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_levinson_durbin_f32.c + * Description: f32 version of Levinson Durbin algorithm + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup LD Levinson Durbin Algorithm + + */ + +/** + @addtogroup LD + @{ + */ + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_levinson_durbin_f32 built. Helium version has build issues with gcc." +#endif + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) + +#include "arm_helium_utils.h" + +#define LANE23_MASK 0xFF00 + +void arm_levinson_durbin_f32(const float32_t *phi, + float32_t *a, + float32_t *err, + int nbCoefs) +{ + float32_t e; + static const uint32_t revOffsetArray[4] = {3,2,1,0}; + + a[0] = phi[1] / phi[0]; + + e = phi[0] - phi[1] * a[0]; + for(int p=1; p < nbCoefs; p++) + { + float32_t suma = 0.0f; + float32_t sumb = 0.0f; + f32x4_t vecA,vecRevPhi,vecPhi,vecSumA, vecSumB; + float32_t k; + uint32_t blkCnt; + const float32_t *pPhi,*pRevPhi,*pA; + uint32x4_t revOffset; + + int nb,j,i; + + revOffset = vld1q(revOffsetArray); + vecSumA = vdupq_n_f32(0.0f); + vecSumB = vdupq_n_f32(0.0f); + + pRevPhi = &phi[p-3]; + pPhi = &phi[1]; + pA = a; + + i = 0; + blkCnt = p >> 2; + while(blkCnt > 0) + { + vecA = vld1q(pA); + pA += 4; + + vecPhi = vld1q(pPhi); + pPhi += 4; + + vecRevPhi = vldrwq_gather_shifted_offset_f32(pRevPhi,revOffset); + pRevPhi -= 4; + + vecSumA = vfmaq(vecSumA,vecA,vecRevPhi); + vecSumB = vfmaq(vecSumB,vecA,vecPhi); + + i += 4; + blkCnt--; + + } + + suma = vecAddAcrossF32Mve(vecSumA); + sumb = vecAddAcrossF32Mve(vecSumB); + + blkCnt = p & 3; + while(blkCnt > 0) + { + suma += a[i] * phi[p - i]; + sumb += a[i] * phi[i + 1]; + + i++; + blkCnt--; + } + + k = (phi[p+1] - suma)/(phi[0] - sumb); + + f32x4_t vecRevA,tmp; + static int32_t orgOffsetArray[4]={0,1,-1,-2}; + static const int32_t offsetIncArray[4]={2,2,-2,-2}; + + uint32x4_t offset,offsetInc,vecTmp; + + + offset = vld1q_u32((uint32_t*)orgOffsetArray); + vecTmp = vdupq_n_u32(p); + + offset = vaddq_m_u32(offset,offset,vecTmp,LANE23_MASK); + offsetInc = vld1q_u32((uint32_t*)offsetIncArray); + + nb = p >> 2; + j=0; + for(int i = 0; i < nb ; i++) + { + + /* + x0=a[j] - k * a[p-1-j]; + x1=a[j+1] - k * a[p-2-j]; + x3=a[p-1-j] - k * a[j]; + x4=a[p-2-j] - k * a[j+1]; + + a[j] = x0; + a[j+1] = x1; + a[p-1-j] = x2; + a[p-2-j] = x3; + */ + + uint64_t tmpa,tmpb; + vecA = vldrwq_gather_shifted_offset_f32(a,offset); + + + tmpa = vgetq_lane_u64((uint64x2_t)vecA,0); + tmpb = vgetq_lane_u64((uint64x2_t)vecA,1); + vecRevA = (f32x4_t) vsetq_lane_u64(tmpb,(uint64x2_t)vecRevA,0); + vecRevA = (f32x4_t) vsetq_lane_u64(tmpa,(uint64x2_t)vecRevA,1); + + + tmp = vsubq(vecA,vmulq_n_f32(vecRevA,k)); + vstrwq_scatter_shifted_offset_f32(a, offset, tmp); + + offset = vaddq(offset,offsetInc); + + j+=2; + + } + + switch(p & 3) + { + case 3: + { + float32_t x,y; + x = a[j] - k * a[p-1-j]; + y = a[p-1-j] - k * a[j]; + + a[j] = x; + a[p-1-j] = y; + + a[j+1] = a[j+1] - k * a[p-1-(j+1)]; + } + break; + + case 2: + { + float32_t x,y; + x = a[j] - k * a[p-1-j]; + y = a[p-1-j] - k * a[j]; + + a[j] = x; + a[p-1-j] = y; + } + break; + + case 1: + a[j] = a[j]- k * a[p-1-j]; + break; + } + + a[p] = k; + e = e * (1.0f - k*k); + + + } + *err = e; +} + +#else +void arm_levinson_durbin_f32(const float32_t *phi, + float32_t *a, + float32_t *err, + int nbCoefs) +{ + float32_t e; + int p; + + a[0] = phi[1] / phi[0]; + + e = phi[0] - phi[1] * a[0]; + for(p=1; p < nbCoefs; p++) + { + float32_t suma=0.0f; + float32_t sumb=0.0f; + float32_t k; + int nb,j,i; + + for(i=0; i < p; i++) + { + suma += a[i] * phi[p - i]; + sumb += a[i] * phi[i + 1]; + } + + k = (phi[p+1]-suma)/(phi[0] - sumb); + + + nb = p >> 1; + j=0; + for(i =0; i < nb ; i++) + { + float32_t x,y; + + x=a[j] - k * a[p-1-j]; + y=a[p-1-j] - k * a[j]; + + a[j] = x; + a[p-1-j] = y; + + j++; + } + + nb = p & 1; + if (nb) + { + a[j]=a[j]- k * a[p-1-j]; + } + + a[p] = k; + e = e * (1.0f - k*k); + + + } + *err = e; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of LD group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_q31.c new file mode 100644 index 00000000..1788d971 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_q31.c @@ -0,0 +1,379 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_levinson_durbin_q31.c + * Description: q31 version of Levinson Durbin algorithm + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +#define ONE_Q31 0x7FFFFFFFL +#define TWO_Q30 0x7FFFFFFFL + +#define HALF_Q31 0x00008000L +#define ONE_Q15 0x7FFF +#define HALF_Q15 0x3FFF +#define LOWPART_MASK 0x07FFF + +__STATIC_FORCEINLINE q31_t mul32x16(q31_t a, q15_t b) +{ + q31_t r = ((q63_t)a * (q63_t)b) >> 15; + + return(r); + +} + +__STATIC_FORCEINLINE q31_t mul32x32(q31_t a, q31_t b) +{ + //q31_t r = __SSAT(((q63_t)a * b) >> 31,31); + q31_t r = ((q63_t)a * b) >> 31; + + return(r); + +} + +__STATIC_FORCEINLINE q31_t divide(q31_t n, q31_t d) +{ + arm_status status; + int16_t shift; + q15_t inverse; + q31_t r; + // We are computing: + // n / d = n / (h + l) where h and l are the high end and low end part. + // 1 / (h + l) = 1 / h (1 - l / h) + // Our division algorithm has a shift. So it is returning a scaled value sh. + // So we need a << shift to convert 1/ sh to 1/h. + // In below code, we are organizing the computation differently. Instead of computing: + // 1 / h (1 - l / h) + // we are computing + // 1 / h (2 - (l + h) / h) + // 1 / h (2 - d / h) + // Also, we are not computing 1/h in Q15 but in Q14. + // 2 is expressed in Q30. + // So at the end of all computation we need a << 2 + + // Result is in Q14 because of use of HALF_Q15 instead of ONE_Q15. + status=arm_divide_q15(HALF_Q15,d>>16,&inverse,&shift); + (void)status; + + // d is used instead of l + // So we will need to substract to 2 instead of 1. + r = mul32x16(d,inverse); + r = TWO_Q30 - (r << shift); + r = mul32x16(r, inverse); + r = mul32x32(r,n) ; + r = r << (shift + 2); + + return(r); + +} + +/** + @ingroup groupFilters + */ + +/** + @defgroup LD Levinson Durbin Algorithm + + */ + +/** + @addtogroup LD + @{ + */ + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_levinson_durbin_q31 built. Helium version has build issues with gcc." +#endif + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) + +#define LANE23_MASK 0xFF00 + +#include "arm_helium_utils.h" +void arm_levinson_durbin_q31(const q31_t *phi, + q31_t *a, + q31_t *err, + int nbCoefs) +{ + q31_t e; + + static const uint32_t revOffsetArray[4] = {3,2,1,0}; + + //a[0] = phi[1] / phi[0]; + a[0] = divide(phi[1], phi[0]); + + + //e = phi[0] - phi[1] * a[0]; + e = phi[0] - mul32x32(phi[1],a[0]); + + for(int p=1; p < nbCoefs; p++) + { + q63_t suma=0; + q63_t sumb=0; + q31x4_t vecA,vecRevPhi,vecPhi; + q31_t k; + uint32_t blkCnt; + const q31_t *pPhi,*pRevPhi,*pA; + uint32x4_t revOffset; + + + int nb,j,i; + + revOffset = vld1q(revOffsetArray); + + pRevPhi = &phi[p-3]; + pPhi = &phi[1]; + pA = a; + + i = 0; + blkCnt = p >> 2; + while(blkCnt > 0) + { + vecA = vld1q(pA); + pA += 4; + + vecPhi = vld1q(pPhi); + pPhi += 4; + + vecRevPhi = vldrwq_gather_shifted_offset_s32(pRevPhi,revOffset); + pRevPhi -= 4; + + suma = vmlaldavaq(suma,vecA,vecRevPhi); + sumb = vmlaldavaq(sumb,vecA,vecPhi); + + i += 4; + blkCnt--; + } + + + blkCnt = p & 3; + while(blkCnt > 0) + { + suma += ((q63_t)a[i] * phi[p - i]); + sumb += ((q63_t)a[i] * phi[i + 1]); + + i++; + blkCnt--; + } + + suma = asrl(suma, 31); + sumb = asrl(sumb, 31); + + + + //k = (phi[p+1]-suma)/(phi[0] - sumb); + k = divide(phi[p+1]-(q31_t)suma,phi[0] - (q31_t)sumb); + + q31x4_t vecRevA,tmp; + static int32_t orgOffsetArray[4]={0,1,-1,-2}; + static const int32_t offsetIncArray[4]={2,2,-2,-2}; + + uint32x4_t offset,offsetInc,vecTmp; + + + offset = vld1q_u32((uint32_t*)orgOffsetArray); + vecTmp = vdupq_n_u32(p); + + offset = vaddq_m_u32(offset,offset,vecTmp,LANE23_MASK); + offsetInc = vld1q_u32((uint32_t*)offsetIncArray); + + + nb = p >> 2; + j=0; + for(int i =0;i < nb ; i++) + { + /* + q31_t x0,x1,x2,x3; + + //x = a[j] - k * a[p-1-j]; + x0 = a[j] - mul32x32(k,a[p-1-j]); + x1 = a[j+1] - mul32x32(k,a[p-2-j]); + + //y = a[p-1-j] - k * a[j]; + x2 = a[p-1-j] - mul32x32(k , a[j]); + x3 = a[p-2-j] - mul32x32(k , a[j+1]); + + a[j] = x0; + a[j+1] = x1; + a[p-1-j] = x2; + a[p-2-j] = x3; + */ + + uint64_t tmpa,tmpb; + vecA = vldrwq_gather_shifted_offset_s32(a,offset); + + + tmpa = vgetq_lane_u64((uint64x2_t)vecA,0); + tmpb = vgetq_lane_u64((uint64x2_t)vecA,1); + vecRevA = (q31x4_t) vsetq_lane_u64(tmpb,(uint64x2_t)vecRevA,0); + vecRevA = (q31x4_t) vsetq_lane_u64(tmpa,(uint64x2_t)vecRevA,1); + + + tmp = vsubq(vecA,vqdmulhq_n_s32(vecRevA,k)); + vstrwq_scatter_shifted_offset_s32(a, offset, tmp); + + offset = vaddq(offset,offsetInc); + + j+=2; + } + + switch(p & 3) + { + case 3: + { + q31_t x,y; + + //x = a[j] - k * a[p-1-j]; + x = a[j] - mul32x32(k,a[p-1-j]); + + //y = a[p-1-j] - k * a[j]; + y = a[p-1-j] - mul32x32(k , a[j]); + + a[j] = x; + a[p-1-j] = y; + + //a[j] = a[j]- k * a[p-1-j]; + a[j+1] = a[j+1] - mul32x32(k,a[p-2-j]); + } + break; + + case 2: + { + q31_t x,y; + + //x = a[j] - k * a[p-1-j]; + x = a[j] - mul32x32(k,a[p-1-j]); + + //y = a[p-1-j] - k * a[j]; + y = a[p-1-j] - mul32x32(k , a[j]); + + a[j] = x; + a[p-1-j] = y; + } + break; + + case 1: + //a[j] = a[j]- k * a[p-1-j]; + a[j] = a[j] - mul32x32(k,a[p-1-j]); + break; + } + + a[p] = k; + + // e = e * (1 - k*k); + e = mul32x32(e,ONE_Q31 - mul32x32(k,k)); + + + } + *err = e; +} + +#else + +void arm_levinson_durbin_q31(const q31_t *phi, + q31_t *a, + q31_t *err, + int nbCoefs) +{ + q31_t e; + int p; + + //a[0] = phi[1] / phi[0]; + a[0] = divide(phi[1], phi[0]); + + + //e = phi[0] - phi[1] * a[0]; + e = phi[0] - mul32x32(phi[1],a[0]); + + for(p=1; p < nbCoefs; p++) + { + q63_t suma=0; + q63_t sumb=0; + q31_t k; + int nb,j,i; + + for(i=0; i < p; i++) + { + suma += ((q63_t)a[i] * phi[p - i]); + sumb += ((q63_t)a[i] * phi[i + 1]); + } + + suma = suma >> 31; + sumb = sumb >> 31; + + + + //k = (phi[p+1]-suma)/(phi[0] - sumb); + k = divide(phi[p+1]-(q31_t)suma,phi[0] - (q31_t)sumb); + + + nb = p >> 1; + j=0; + for(i =0;i < nb ; i++) + { + q31_t x,y; + + //x = a[j] - k * a[p-1-j]; + x = a[j] - mul32x32(k,a[p-1-j]); + + //y = a[p-1-j] - k * a[j]; + y = a[p-1-j] - mul32x32(k , a[j]); + + a[j] = x; + a[p-1-j] = y; + + j++; + } + + nb = p & 1; + if (nb) + { + //a[j] = a[j]- k * a[p-1-j]; + a[j] = a[j] - mul32x32(k,a[p-1-j]); + } + + a[p] = k; + + // e = e * (1 - k*k); + e = mul32x32(e,ONE_Q31 - mul32x32(k,k)); + + + } + *err = e; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of LD group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c new file mode 100644 index 00000000..99cbeb42 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c @@ -0,0 +1,533 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_f32.c + * Description: Processing function for the floating-point LMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup LMS Least Mean Square (LMS) Filters + + LMS filters are a class of adaptive filters that are able to "learn" an unknown transfer functions. + LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal. + Adaptive filters are often used in communication systems, equalizers, and noise removal. + The CMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types. + The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal. + + An LMS filter consists of two components as shown below. + The first component is a standard transversal or FIR filter. + The second component is a coefficient update mechanism. + The LMS filter has two input signals. + The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter. + That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input. + The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input. + This "error signal" tends towards zero as the filter adapts. + The LMS processing functions accept the input and reference input signals and generate the filter output and error signal. + \image html LMS.gif "Internal structure of the Least Mean Square filter" + + The functions operate on blocks of data and each call to the function processes + blockSize samples through the filter. + pSrc points to input signal, pRef points to reference signal, + pOut points to output signal and pErr points to error signal. + All arrays contain blockSize values. + + The functions operate on a block-by-block basis. + Internally, the filter coefficients b[n] are updated on a sample-by-sample basis. + The convergence of the LMS filter is slower compared to the normalized LMS algorithm. + + @par Algorithm + The output signal y[n] is computed by a standard FIR filter: +
+      y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+  
+ + @par + The error signal equals the difference between the reference signal d[n] and the filter output: +
+      e[n] = d[n] - y[n].
+  
+ + @par + After each sample of the error signal is computed, the filter coefficients b[k] are updated on a sample-by-sample basis: +
+      b[k] = b[k] + e[n] * mu * x[n-k],  for k=0, 1, ..., numTaps-1
+  
+ where mu is the step size and controls the rate of coefficient convergence. + @par + In the APIs, pCoeffs points to a coefficient array of size numTaps. + Coefficients are stored in time reversed order. + @par +
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+  
+ @par + pState points to a state array of size numTaps + blockSize - 1. + Samples in the state buffer are stored in the order: + @par +
+     {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+  
+ @par + Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples. + The increased state buffer length allows circular addressing, which is traditionally used in FIR filters, + to be avoided and yields a significant speed improvement. + The state variables are updated after each block of data is processed. + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter and + coefficient and state arrays cannot be shared among instances. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, mu, postShift (not for f32), pState. Also set all of the values in pState to zero. + + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + The code below statically initializes each of the 3 different data type filter instance structures +
+     arm_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};
+     arm_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};
+     arm_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};
+  
+ where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer; mu is the step size parameter; and postShift is the shift applied to coefficients. + + @par Fixed-Point Behavior + Care must be taken when using the Q15 and Q31 versions of the LMS filter. + The following issues must be considered: + - Scaling of coefficients + - Overflow and saturation + + @par Scaling of Coefficients + Filter coefficients are represented as fractional values and + coefficients are restricted to lie in the range [-1 +1). + The fixed-point functions have an additional scaling parameter postShift. + At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. + This essentially scales the filter coefficients by 2^postShift and + allows the filter coefficients to exceed the range [+1 -1). + The value of postShift is set by the user based on the expected gain through the system being modeled. + + @par Overflow and Saturation + Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are + described separately as part of the function specific documentation below. + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Processing function for floating-point LMS filter. + @param[in] S points to an instance of the floating-point LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + */ +#if defined(ARM_MATH_NEON) +void arm_lms_f32( + const arm_lms_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + float32_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + float32_t sum, e, d; /* accumulator, error, reference data sample */ + float32_t w = 0.0f; /* weight factor */ + + float32x4_t tempV, sumV, xV, bV; + float32x2_t tempV2; + + e = 0.0f; + d = 0.0f; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = (pCoeffs); + + /* Set the accumulator to zero */ + sum = 0.0f; + sumV = vdupq_n_f32(0.0); + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + xV = vld1q_f32(px); + bV = vld1q_f32(pb); + sumV = vmlaq_f32(sumV, xV, bV); + + px += 4; + pb += 4; + + /* Decrement the loop counter */ + tapCnt--; + } + tempV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = vget_lane_f32(tempV2, 0) + vget_lane_f32(tempV2, 1); + + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum += (*px++) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result in the accumulator, store in the destination buffer. */ + *pOut++ = sum; + + /* Compute and store error */ + d = (float32_t) (*pRef++); + e = d - sum; + *pErr++ = e; + + /* Calculation of Weighting factor for the updating filter coefficients */ + w = e * mu; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = (pCoeffs); + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + xV = vld1q_f32(px); + bV = vld1q_f32(pb); + px += 4; + bV = vmlaq_n_f32(bV,xV,w); + + vst1q_f32(pb,bV); + pb += 4; + + + /* Decrement the loop counter */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb = *pb + (w * (*px++)); + pb++; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + satrt of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* Process 4 taps at a time for (numTaps - 1U) samples copy */ + tapCnt = (numTaps - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + tempV = vld1q_f32(pState); + vst1q_f32(pStateCurnt,tempV); + pState += 4; + pStateCurnt += 4; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + + /* Copy the remaining q31_t data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + + +} +#else +void arm_lms_f32( + const arm_lms_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + float32_t mu = S->mu; /* Adaptive factor */ + float32_t acc, e; /* Accumulator, error */ + float32_t w; /* Weight factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + + /* Initializations of error, difference, Coefficient update */ + e = 0.0f; + w = 0.0f; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (*px++) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = acc; + + /* Compute and store error */ + e = (float32_t) *pRef++ - acc; + *pErr++ = e; + + /* Calculation of Weighting factor for updating filter coefficients */ + w = e * mu; + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of LMS group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c new file mode 100644 index 00000000..cf472afd --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c @@ -0,0 +1,81 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_init_f32.c + * Description: Floating-point LMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Initialization function for floating-point LMS filter. + @param[in] S points to an instance of the floating-point LMS filter structure + @param[in] numTaps number of filter coefficients + @param[in] pCoeffs points to coefficient buffer + @param[in] pState points to state buffer + @param[in] mu step size that controls filter coefficient updates + @param[in] blockSize number of samples to process + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: +
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+  
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_f32(). + */ + +void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps */ + memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; +} + +/** + @} end of LMS group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c new file mode 100644 index 00000000..31c2bff2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_init_q15.c + * Description: Q15 LMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Initialization function for the Q15 LMS filter. + @param[in] S points to an instance of the Q15 LMS filter structure. + @param[in] numTaps number of filter coefficients. + @param[in] pCoeffs points to coefficient buffer. + @param[in] pState points to state buffer. + @param[in] mu step size that controls filter coefficient updates. + @param[in] blockSize number of samples to process. + @param[in] postShift bit shift applied to coefficients. + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: +
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+  
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to the array of state variables and size of array is + numTaps+blockSize-1 samples, where blockSize is the number of + input samples processed by each call to arm_lms_q15(). + */ + +void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Assign postShift value to be applied */ + S->postShift = postShift; +} + +/** + @} end of LMS group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c new file mode 100644 index 00000000..e657a938 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_init_q31.c + * Description: Q31 LMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Initialization function for Q31 LMS filter. + @param[in] S points to an instance of the Q31 LMS filter structure + @param[in] numTaps number of filter coefficients + @param[in] pCoeffs points to coefficient buffer + @param[in] pState points to state buffer + @param[in] mu step size that controls filter coefficient updates + @param[in] blockSize number of samples to process + @param[in] postShift bit shift applied to coefficients + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: +
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+  
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to an array of length numTaps+blockSize-1 samples, + where blockSize is the number of input samples processed by each call to + arm_lms_q31(). + */ + +void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Assign postShift value to be applied */ + S->postShift = postShift; +} + +/** + @} end of LMS group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c new file mode 100644 index 00000000..85f8211c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c @@ -0,0 +1,564 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_f32.c + * Description: Processing function for the floating-point NLMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup LMS_NORM Normalized LMS Filters + + This set of functions implements a commonly used adaptive filter. + It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization + factor which increases the adaptation rate of the filter. + The CMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types. + + A normalized least mean square (NLMS) filter consists of two components as shown below. + The first component is a standard transversal or FIR filter. + The second component is a coefficient update mechanism. + The NLMS filter has two input signals. + The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter. + That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input. + The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input. + This "error signal" tends towards zero as the filter adapts. + The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal. + \image html LMS.gif "Internal structure of the NLMS adaptive filter" + + The functions operate on blocks of data and each call to the function processes + blockSize samples through the filter. + pSrc points to input signal, pRef points to reference signal, + pOut points to output signal and pErr points to error signal. + All arrays contain blockSize values. + + The functions operate on a block-by-block basis. + Internally, the filter coefficients b[n] are updated on a sample-by-sample basis. + The convergence of the LMS filter is slower compared to the normalized LMS algorithm. + + @par Algorithm + The output signal y[n] is computed by a standard FIR filter: +
+      y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+  
+ + @par + The error signal equals the difference between the reference signal d[n] and the filter output: +
+      e[n] = d[n] - y[n].
+  
+ + @par + After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated: +
+     E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.
+  
+ The filter coefficients b[k] are then updated on a sample-by-sample basis: +
+      b[k] = b[k] + e[n] * (mu/E) * x[n-k],  for k=0, 1, ..., numTaps-1
+  
+ where mu is the step size and controls the rate of coefficient convergence. + @par + In the APIs, pCoeffs points to a coefficient array of size numTaps. + Coefficients are stored in time reversed order. + @par +
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+  
+ @par + pState points to a state array of size numTaps + blockSize - 1. + Samples in the state buffer are stored in the order: + @par +
+     {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+  
+ @par + Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples. + The increased state buffer length allows circular addressing, which is traditionally used in FIR filters, + to be avoided and yields a significant speed improvement. + The state variables are updated after each block of data is processed. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter and + coefficient and state arrays cannot be shared among instances. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, mu, energy, x0, pState. Also set all of the values in pState to zero. + For Q7, Q15, and Q31 the following fields must also be initialized; + recipTable, postShift + @par + Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + @par Fixed-Point Behavior + Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter. + The following issues must be considered: + - Scaling of coefficients + - Overflow and saturation + + @par Scaling of Coefficients (fixed point versions) + Filter coefficients are represented as fractional values and + coefficients are restricted to lie in the range [-1 +1). + The fixed-point functions have an additional scaling parameter postShift. + At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. + This essentially scales the filter coefficients by 2^postShift and + allows the filter coefficients to exceed the range [+1 -1). + The value of postShift is set by the user based on the expected gain through the system being modeled. + + @par Overflow and Saturation (fixed point versions) + Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are + described separately as part of the function specific documentation below. + */ + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Processing function for floating-point normalized LMS filter. + @param[in] S points to an instance of the floating-point normalized LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + */ + +#if defined(ARM_MATH_NEON) +void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + float32_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + float32_t energy; /* Energy of the input */ + float32_t sum, e, d; /* accumulator, error, reference data sample */ + float32_t w, x0, in; /* weight factor, temporary variable to hold input sample and state */ + + float32x4_t tempV, sumV, xV, bV; + float32x2_t tempV2; + + /* Initializations of error, difference, Coefficient update */ + e = 0.0f; + d = 0.0f; + w = 0.0f; + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* Loop over blockSize number of values */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = (pCoeffs); + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy -= x0 * x0; + energy += in * in; + + /* Set the accumulator to zero */ + sum = 0.0f; + sumV = vdupq_n_f32(0.0); + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + xV = vld1q_f32(px); + bV = vld1q_f32(pb); + sumV = vmlaq_f32(sumV, xV, bV); + + px += 4; + pb += 4; + + /* Decrement the loop counter */ + tapCnt--; + } + tempV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = vget_lane_f32(tempV2, 0) + vget_lane_f32(tempV2, 1); + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum += (*px++) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result in the accumulator, store in the destination buffer. */ + *pOut++ = sum; + + /* Compute and store error */ + d = (float32_t) (*pRef++); + e = d - sum; + *pErr++ = e; + + /* Calculation of Weighting factor for updating filter coefficients */ + /* epsilon value 0.000000119209289f */ + w = (e * mu) / (energy + 0.000000119209289f); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = (pCoeffs); + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + xV = vld1q_f32(px); + bV = vld1q_f32(pb); + px += 4; + bV = vmlaq_n_f32(bV,xV,w); + + vst1q_f32(pb,bV); + pb += 4; + + + /* Decrement the loop counter */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + /* Decrement the loop counter */ + tapCnt--; + } + + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + S->energy = energy; + S->x0 = x0; + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + satrt of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* Process 4 taps at a time for (numTaps - 1U)/4 samples copy */ + tapCnt = (numTaps - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + tempV = vld1q_f32(pState); + vst1q_f32(pStateCurnt,tempV); + pState += 4; + pStateCurnt += 4; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + + /* Copy the remaining q31_t data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} +#else +void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + float32_t mu = S->mu; /* Adaptive factor */ + float32_t acc, e; /* Accumulator, error */ + float32_t w; /* Weight factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + float32_t energy; /* Energy of the input */ + float32_t x0, in; /* Temporary variable to hold input sample and state */ + + /* Initializations of error, difference, Coefficient update */ + e = 0.0f; + w = 0.0f; + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy -= x0 * x0; + energy += in * in; + + /* Set the accumulator to zero */ + acc = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (*px++) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = acc; + + /* Compute and store error */ + e = (float32_t) *pRef++ - acc; + *pErr++ = e; + + /* Calculation of Weighting factor for updating filter coefficients */ + /* epsilon value 0.000000119209289f */ + w = (e * mu) / (energy + 0.000000119209289f); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Save energy and x0 values for the next frame */ + S->energy = energy; + S->x0 = x0; + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ +/** + @} end of LMS_NORM group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c new file mode 100644 index 00000000..b0b7ea50 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_init_f32.c + * Description: Floating-point NLMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Initialization function for floating-point normalized LMS filter. + @param[in] S points to an instance of the floating-point LMS filter structure + @param[in] numTaps number of filter coefficients + @param[in] pCoeffs points to coefficient buffer + @param[in] pState points to state buffer + @param[in] mu step size that controls filter coefficient updates + @param[in] blockSize number of samples to process + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: +
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+  
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to an array of length numTaps+blockSize-1 samples, + where blockSize is the number of input samples processed by each call to arm_lms_norm_f32(). + */ + +void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Initialise Energy to zero */ + S->energy = 0.0f; + + /* Initialise x0 to zero */ + S->x0 = 0.0f; +} + +/** + @} end of LMS_NORM group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c new file mode 100644 index 00000000..5bbfc420 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c @@ -0,0 +1,98 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_init_q15.c + * Description: Q15 NLMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" +#include "arm_common_tables.h" + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Initialization function for Q15 normalized LMS filter. + @param[in] S points to an instance of the Q15 normalized LMS filter structure. + @param[in] numTaps number of filter coefficients. + @param[in] pCoeffs points to coefficient buffer. + @param[in] pState points to state buffer. + @param[in] mu step size that controls filter coefficient updates. + @param[in] blockSize number of samples to process. + @param[in] postShift bit shift applied to coefficients. + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: +
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+  
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to the array of state variables and size of array is + numTaps+blockSize-1 samples, where blockSize is the number of input samples processed + by each call to arm_lms_norm_q15(). + */ + +void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t)); + + /* Assign post Shift value applied to coefficients */ + S->postShift = postShift; + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Initialize reciprocal pointer table */ + S->recipTable = (q15_t *) armRecipTableQ15; + + /* Initialise Energy to zero */ + S->energy = 0; + + /* Initialise x0 to zero */ + S->x0 = 0; +} + +/** + @} end of LMS_NORM group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c new file mode 100644 index 00000000..cc429b00 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c @@ -0,0 +1,97 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_init_q31.c + * Description: Q31 NLMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" +#include "arm_common_tables.h" + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Initialization function for Q31 normalized LMS filter. + @param[in] S points to an instance of the Q31 normalized LMS filter structure. + @param[in] numTaps number of filter coefficients. + @param[in] pCoeffs points to coefficient buffer. + @param[in] pState points to state buffer. + @param[in] mu step size that controls filter coefficient updates. + @param[in] blockSize number of samples to process. + @param[in] postShift bit shift applied to coefficients. + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: +
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+  
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to an array of length numTaps+blockSize-1 samples, + where blockSize is the number of input samples processed by each call to arm_lms_norm_q31(). + */ + +void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t)); + + /* Assign post Shift value applied to coefficients */ + S->postShift = postShift; + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Initialize reciprocal pointer table */ + S->recipTable = (q31_t *) armRecipTableQ31; + + /* Initialise Energy to zero */ + S->energy = 0; + + /* Initialise x0 to zero */ + S->x0 = 0; +} + +/** + @} end of LMS_NORM group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c new file mode 100644 index 00000000..b07efdda --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c @@ -0,0 +1,297 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_q15.c + * Description: Processing function for Q15 normalized LMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Processing function for Q15 normalized LMS filter. + @param[in] S points to an instance of the Q15 normalized LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and + multiplications yield a 2.30 result. The 2.30 intermediate results are + accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full + precision of intermediate multiplications is preserved. After all additions + have been performed, the accumulator is truncated to 34.15 format by + discarding low 15 bits. Lastly, the accumulator is saturated to yield a + result in 1.15 format. + @par + In this filter, filter coefficients are updated for each sample and the + updation of filter cofficients are saturted. + */ + +void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q15_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q31_t energy; /* Energy of the input */ + q15_t e = 0, d = 0; /* Error, reference data sample */ + q15_t w = 0, in; /* Weight factor and state */ + q15_t x0; /* Temporary variable to hold input sample */ + q15_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */ + q15_t postShift; /* Post shift to be applied to weight after reciprocal calculation */ + q31_t coef; /* Temporary variable for coefficient */ + q31_t acc_l, acc_h; /* Temporary input */ + int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */ + int32_t uShift = (32 - lShift); + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy -= (((q31_t) x0 * (x0)) >> 15); + energy += (((q31_t) in * (in)) >> 15); + + /* Set the accumulator to zero */ + acc = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + /* acc += b[N] * x[n-N] + b[N-1] * x[n-N-1] */ + acc = __SMLALD(read_q15x2_ia (&px), read_q15x2_ia (&pb), acc); + acc = __SMLALD(read_q15x2_ia (&px), read_q15x2_ia (&pb), acc); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (q63_t) (((q31_t) (*px++) * (*pb++))); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Converting the result to 1.15 format and saturate the output */ + acc = __SSAT(acc, 16U); + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q15_t) acc; + + /* Compute and store error */ + d = *pRef++; + e = d - (q15_t) acc; + *pErr++ = e; + + /* Calculation of 1/energy */ + postShift = arm_recip_q15((q15_t) energy + DELTA_Q15, &oneByEnergy, S->recipTable); + + /* Calculation of e * mu value */ + errorXmu = (q15_t) (((q31_t) e * mu) >> 15); + + /* Calculation of (e * mu) * (1/energy) value */ + acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift)); + + /* Weighting factor for the normalized version */ + w = (q15_t) __SSAT((q31_t) acc, 16); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + /* Decrement loop counter */ + tapCnt--; + } + + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Save energy and x0 values for the next frame */ + S->energy = (q15_t) energy; + S->x0 = x0; + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of LMS_NORM group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c new file mode 100644 index 00000000..6375d8ff --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c @@ -0,0 +1,311 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_q31.c + * Description: Processing function for the Q31 NLMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Processing function for Q31 normalized LMS filter. + @param[in] S points to an instance of the Q31 normalized LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by + log2(numTaps) bits. The reference signal should not be scaled down. + After all multiply-accumulates are performed, the 2.62 accumulator is shifted + and saturated to 1.31 format to yield the final result. + The output signal and error signal are in 1.31 format. + @par + In this filter, filter coefficients are updated for each sample and the + updation of filter cofficients are saturted. + */ + +void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q31_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q63_t energy; /* Energy of the input */ + q31_t e = 0; /* Error data sample */ + q31_t w = 0, in; /* Weight factor and state */ + q31_t x0; /* Temporary variable to hold input sample */ + q31_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */ + q31_t postShift; /* Post shift to be applied to weight after reciprocal calculation */ + q31_t coef; /* Temporary variable for coef */ + q31_t acc_l, acc_h; /* Temporary input */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy = (q31_t) ((((q63_t) energy << 32) - (((q63_t) x0 * x0) << 1)) >> 32); + energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32); + + /* Set the accumulator to zero */ + acc = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + /* acc += b[N] * x[n-N] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-1] * x[n-N-1] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-2] * x[n-N-2] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-3] * x[n-N-3] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Converting the result to 1.31 format */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + acc = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q31_t) acc; + + /* Compute and store error */ + e = *pRef++ - (q31_t) acc; + *pErr++ = e; + + /* Calculates the reciprocal of energy */ + postShift = arm_recip_q31(energy + DELTA_Q31, &oneByEnergy, &S->recipTable[0]); + + /* Calculation of product of (e * mu) */ + errorXmu = (q31_t) (((q63_t) e * mu) >> 31); + + /* Weighting factor for the normalized version */ + w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift)); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + + /* coef is in 2.30 format */ + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + /* get coef in 1.31 format by left shifting */ + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + /* update coefficient buffer to next coefficient */ + pb++; + + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Read the sample from state buffer */ + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Save energy and x0 values for the next frame */ + S->energy = (q31_t) energy; + S->x0 = x0; + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of LMS_NORM group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c new file mode 100644 index 00000000..76cab032 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c @@ -0,0 +1,262 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_q15.c + * Description: Processing function for Q15 LMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Processing function for Q15 LMS filter. + @param[in] S points to an instance of the Q15 LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + @par + In this filter, filter coefficients are updated for each sample and + the updation of filter cofficients are saturted. + */ + +void arm_lms_q15( + const arm_lms_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q15_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q15_t e = 0; /* Error of data sample */ + q15_t alpha; /* Intermediate constant for taps update */ + q31_t coef; /* Temporary variable for coefficient */ + q31_t acc_l, acc_h; /* Temporary input */ + int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */ + int32_t uShift = (32 - lShift); + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + /* acc += b[N] * x[n-N] + b[N-1] * x[n-N-1] */ + acc = __SMLALD(read_q15x2_ia (&px), read_q15x2_ia (&pb), acc); + acc = __SMLALD(read_q15x2_ia (&px), read_q15x2_ia (&pb), acc); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (q63_t) (((q31_t) (*px++) * (*pb++))); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Converting the result to 1.15 format and saturate the output */ + acc = __SSAT(acc, 16U); + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q15_t) acc; + + /* Compute and store error */ + e = *pRef++ - (q15_t) acc; + *pErr++ = (q15_t) e; + + /* Compute alpha i.e. intermediate constant for taps update */ + alpha = (q15_t) (((q31_t) e * (mu)) >> 15); + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of LMS group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c new file mode 100644 index 00000000..1ed61f27 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c @@ -0,0 +1,283 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_q31.c + * Description: Processing function for the Q31 LMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Processing function for Q31 LMS filter. + @param[in] S points to an instance of the Q31 LMS filter structure. + @param[in] pSrc points to the block of input data. + @param[in] pRef points to the block of reference data. + @param[out] pOut points to the block of output data. + @param[out] pErr points to the block of error data. + @param[in] blockSize number of samples to process. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clips. + In order to avoid overflows completely the input signal must be scaled down by + log2(numTaps) bits. + The reference signal should not be scaled down. + After all multiply-accumulates are performed, the 2.62 accumulator is shifted + and saturated to 1.31 format to yield the final result. + The output signal and error signal are in 1.31 format. + @par + In this filter, filter coefficients are updated for each sample and + the updation of filter cofficients are saturted. + */ + +void arm_lms_q31( + const arm_lms_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q31_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q31_t e = 0; /* Error of data sample */ + q31_t alpha; /* Intermediate constant for taps update */ + q31_t coef; /* Temporary variable for coef */ + q31_t acc_l, acc_h; /* Temporary input */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + /* acc += b[N] * x[n-N] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-1] * x[n-N-1] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-2] * x[n-N-2] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-3] * x[n-N-3] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Converting the result to 1.31 format */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + acc = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q31_t) acc; + + /* Compute and store error */ + e = *pRef++ - (q31_t) acc; + *pErr++ = e; + + /* Compute alpha i.e. intermediate constant for taps update */ + alpha = (q31_t) (((q63_t) e * mu) >> 31); + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + + /* coef is in 2.30 format */ + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + /* get coef in 1.31 format by left shifting */ + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + /* update coefficient buffer to next coefficient */ + pb++; + + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of LMS group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/CMakeLists.txt new file mode 100644 index 00000000..7ce79cfe --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/CMakeLists.txt @@ -0,0 +1,34 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPInterpolation) + +include(configLib) +include(configDsp) + + +add_library(CMSISDSPInterpolation STATIC) + +target_sources(CMSISDSPInterpolation PRIVATE arm_bilinear_interp_f32.c) +target_sources(CMSISDSPInterpolation PRIVATE arm_bilinear_interp_q15.c) +target_sources(CMSISDSPInterpolation PRIVATE arm_bilinear_interp_q31.c) +target_sources(CMSISDSPInterpolation PRIVATE arm_bilinear_interp_q7.c) +target_sources(CMSISDSPInterpolation PRIVATE arm_linear_interp_f32.c) +target_sources(CMSISDSPInterpolation PRIVATE arm_linear_interp_q15.c) +target_sources(CMSISDSPInterpolation PRIVATE arm_linear_interp_q31.c) +target_sources(CMSISDSPInterpolation PRIVATE arm_linear_interp_q7.c) +target_sources(CMSISDSPInterpolation PRIVATE arm_spline_interp_f32.c) +target_sources(CMSISDSPInterpolation PRIVATE arm_spline_interp_init_f32.c) + + +configLib(CMSISDSPInterpolation ${ROOT}) +configDsp(CMSISDSPInterpolation ${ROOT}) + +### Includes +target_include_directories(CMSISDSPInterpolation PUBLIC "${DSP}/Include") + + + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPInterpolation PRIVATE arm_bilinear_interp_f16.c) +target_sources(CMSISDSPInterpolation PRIVATE arm_linear_interp_f16.c) +endif() \ No newline at end of file diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctions.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctions.c new file mode 100644 index 00000000..8462395e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctions.c @@ -0,0 +1,41 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: InterpolationFunctions.c + * Description: Combination of all interpolation function source files. + * + * $Date: 22. July 2020 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_bilinear_interp_f32.c" +#include "arm_bilinear_interp_q15.c" +#include "arm_bilinear_interp_q31.c" +#include "arm_bilinear_interp_q7.c" +#include "arm_linear_interp_f32.c" +#include "arm_linear_interp_q15.c" +#include "arm_linear_interp_q31.c" +#include "arm_linear_interp_q7.c" +#include "arm_spline_interp_f32.c" +#include "arm_spline_interp_init_f32.c" + + + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctionsF16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctionsF16.c new file mode 100644 index 00000000..d778de9d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctionsF16.c @@ -0,0 +1,33 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: InterpolationFunctions.c + * Description: Combination of all interpolation function source files. + * + * $Date: 22. July 2020 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_bilinear_interp_f16.c" +#include "arm_linear_interp_f16.c" + + + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_f16.c new file mode 100644 index 00000000..799ed78c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_f16.c @@ -0,0 +1,168 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_bilinear_interp_f16.c + * Description: Floating-point bilinear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupInterpolation + */ + +/** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + *
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float16_t *pData;
+   * } arm_bilinear_interp_instance_f16;
+   * 
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + *
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * 
+ * \par + * The interpolated output point is computed as: + *
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * 
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + float16_t arm_bilinear_interp_f16( + const arm_bilinear_interp_instance_f16 * S, + float16_t X, + float16_t Y) + { + float16_t out; + float16_t f00, f01, f10, f11; + float16_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float16_t xdiff, ydiff; + float16_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numCols - 2) || yIndex < 0 || yIndex > (S->numRows - 2)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex ) + (yIndex ) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex ) + (yIndex+1) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = (_Float16)f01 - (_Float16)f00; + b3 = (_Float16)f10 - (_Float16)f00; + b4 = (_Float16)f00 - (_Float16)f01 - (_Float16)f10 + (_Float16)f11; + + /* Calculation of fractional part in X */ + xdiff = (_Float16)X - (_Float16)xIndex; + + /* Calculation of fractional part in Y */ + ydiff = (_Float16)Y - (_Float16)yIndex; + + /* Calculation of bi-linear interpolated output */ + out = (_Float16)b1 + (_Float16)b2 * (_Float16)xdiff + + (_Float16)b3 * (_Float16)ydiff + (_Float16)b4 * (_Float16)xdiff * (_Float16)ydiff; + + /* return to application */ + return (out); + } + + /** + * @} end of BilinearInterpolate group + */ + + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_f32.c new file mode 100644 index 00000000..fc001d72 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_f32.c @@ -0,0 +1,161 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_bilinear_interp_f32.c + * Description: Floating-point bilinear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + *
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * 
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + *
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * 
+ * \par + * The interpolated output point is computed as: + *
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * 
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numCols - 2) || yIndex < 0 || yIndex > (S->numRows - 2)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex ) + (yIndex ) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex ) + (yIndex+1) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + /** + * @} end of BilinearInterpolate group + */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q15.c new file mode 100644 index 00000000..67267366 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q15.c @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_q15.c + * Description: Q15 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0x0FFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0x0FFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0x0FFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0x0FFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @} end of BilinearInterpolate group + */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q31.c new file mode 100644 index 00000000..cc8560ec --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q31.c @@ -0,0 +1,119 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_q31.c + * Description: Q31 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + + /** + * @} end of BilinearInterpolate group + */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q7.c new file mode 100644 index 00000000..204342e3 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q7.c @@ -0,0 +1,117 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_q7.c + * Description: Q7 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + +/** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_f16.c new file mode 100644 index 00000000..f4ae1e1e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_f16.c @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_f16.c + * Description: Floating-point linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupInterpolation + */ + +/** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + *
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * 
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + +/** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + float16_t arm_linear_interp_f16( + arm_linear_interp_instance_f16 * S, + float16_t x) + { + float16_t y; + float16_t x0, x1; /* Nearest input values */ + float16_t y0, y1; /* Nearest output values */ + float16_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float16_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) (((_Float16)x - (_Float16)S->x1) / (_Float16)xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= (S->nValues - 1)) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = (_Float16)S->x1 + (_Float16)i * (_Float16)xSpacing; + x1 = (_Float16)S->x1 + (_Float16)(i + 1) * (_Float16)xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = (_Float16)y0 + ((_Float16)x - (_Float16)x0) * + (((_Float16)y1 - (_Float16)y0) / ((_Float16)x1 - (_Float16)x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * @} end of LinearInterpolate group + */ + + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_f32.c new file mode 100644 index 00000000..fc60bec4 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_f32.c @@ -0,0 +1,125 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_f32.c + * Description: Floating-point linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + *
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * 
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + +/** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= (S->nValues - 1)) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * @} end of LinearInterpolate group + */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q15.c new file mode 100644 index 00000000..e6339f30 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q15.c @@ -0,0 +1,101 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_q15.c + * Description: Q15 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + q15_t arm_linear_interp_q15( + const q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * @} end of LinearInterpolate group + */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q31.c new file mode 100644 index 00000000..f0c75604 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q31.c @@ -0,0 +1,103 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_q31.c + * Description: Q31 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + + +/** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + q31_t arm_linear_interp_q31( + const q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + + /** + * @} end of LinearInterpolate group + */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q7.c new file mode 100644 index 00000000..8d154325 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q7.c @@ -0,0 +1,99 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_q7.c + * Description: Q7 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + + +/** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + q7_t arm_linear_interp_q7( + const q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + /** + * @} end of LinearInterpolate group + */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_spline_interp_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_spline_interp_f32.c new file mode 100644 index 00000000..3e3d0918 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_spline_interp_f32.c @@ -0,0 +1,283 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_spline_interp_f32.c + * Description: Floating-point cubic spline interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + @defgroup SplineInterpolate Cubic Spline Interpolation + + Spline interpolation is a method of interpolation where the interpolant + is a piecewise-defined polynomial called "spline". + + @par Introduction + + Given a function f defined on the interval [a,b], a set of n nodes x(i) + where a=x(1) + S1(x) x(1) < x < x(2) + S(x) = ... + Sn-1(x) x(n-1) < x < x(n) + + + where + +
 
+  Si(x) = a_i+b_i(x-xi)+c_i(x-xi)^2+d_i(x-xi)^3    i=1, ..., n-1
+  
+ + @par Algorithm + + Having defined h(i) = x(i+1) - x(i) + +
+  h(i-1)c(i-1)+2[h(i-1)+h(i)]c(i)+h(i)c(i+1) = 3/h(i)*[a(i+1)-a(i)]-3/h(i-1)*[a(i)-a(i-1)]    i=2, ..., n-1
+  
+ + It is possible to write the previous conditions in matrix form (Ax=B). + In order to solve the system two boundary conidtions are needed. + - Natural spline: S1''(x1)=2*c(1)=0 ; Sn''(xn)=2*c(n)=0 + In matrix form: + +
+  |  1        0         0  ...    0         0           0     ||  c(1)  | |                        0                        |
+  | h(0) 2[h(0)+h(1)] h(1) ...    0         0           0     ||  c(2)  | |      3/h(2)*[a(3)-a(2)]-3/h(1)*[a(2)-a(1)]      |
+  | ...      ...       ... ...   ...       ...         ...    ||  ...   |=|                       ...                       |
+  |  0        0         0  ... h(n-2) 2[h(n-2)+h(n-1)] h(n-1) || c(n-1) | | 3/h(n-1)*[a(n)-a(n-1)]-3/h(n-2)*[a(n-1)-a(n-2)] |
+  |  0        0         0  ...    0         0           1     ||  c(n)  | |                        0                        |
+  
+ + - Parabolic runout spline: S1''(x1)=2*c(1)=S2''(x2)=2*c(2) ; Sn-1''(xn-1)=2*c(n-1)=Sn''(xn)=2*c(n) + In matrix form: + +
+  |  1       -1         0  ...    0         0           0     ||  c(1)  | |                        0                        |
+  | h(0) 2[h(0)+h(1)] h(1) ...    0         0           0     ||  c(2)  | |      3/h(2)*[a(3)-a(2)]-3/h(1)*[a(2)-a(1)]      |
+  | ...      ...       ... ...   ...       ...         ...    ||  ...   |=|                       ...                       |
+  |  0        0         0  ... h(n-2) 2[h(n-2)+h(n-1)] h(n-1) || c(n-1) | | 3/h(n-1)*[a(n)-a(n-1)]-3/h(n-2)*[a(n-1)-a(n-2)] |
+  |  0        0         0  ...    0        -1           1     ||  c(n)  | |                        0                        |
+  
+ + A is a tridiagonal matrix (a band matrix of bandwidth 3) of size N=n+1. The factorization + algorithms (A=LU) can be simplified considerably because a large number of zeros appear + in regular patterns. The Crout method has been used: + 1) Solve LZ=B + +
+  u(1,2) = A(1,2)/A(1,1)
+  z(1)   = B(1)/l(11)
+ 
+  FOR i=2, ..., N-1
+    l(i,i)   = A(i,i)-A(i,i-1)u(i-1,i)
+    u(i,i+1) = a(i,i+1)/l(i,i)
+    z(i)     = [B(i)-A(i,i-1)z(i-1)]/l(i,i)
+  
+  l(N,N) = A(N,N)-A(N,N-1)u(N-1,N)
+  z(N)   = [B(N)-A(N,N-1)z(N-1)]/l(N,N)
+  
+ + 2) Solve UX=Z + +
+  c(N)=z(N)
+  
+  FOR i=N-1, ..., 1
+    c(i)=z(i)-u(i,i+1)c(i+1) 
+  
+ + c(i) for i=1, ..., n-1 are needed to compute the n-1 polynomials. + b(i) and d(i) are computed as: + - b(i) = [y(i+1)-y(i)]/h(i)-h(i)*[c(i+1)+2*c(i)]/3 + - d(i) = [c(i+1)-c(i)]/[3*h(i)] + Moreover, a(i)=y(i). + + @par Behaviour outside the given intervals + + It is possible to compute the interpolated vector for x values outside the + input range (xqx(n)). The coefficients used to compute the y values for + xqx(n) the + coefficients used for the last interval. + + */ + +/** + @addtogroup SplineInterpolate + @{ + */ + +/** + * @brief Processing function for the floating-point cubic spline interpolation. + * @param[in] S points to an instance of the floating-point spline structure. + * @param[in] xq points to the x values of the interpolated data points. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples of output data. + */ + +void arm_spline_f32( + arm_spline_instance_f32 * S, + const float32_t * xq, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t * x = S->x; + const float32_t * y = S->y; + int32_t n = S->n_x; + + /* Coefficients (a==y for i<=n-1) */ + float32_t * b = (S->coeffs); + float32_t * c = (S->coeffs)+(n-1); + float32_t * d = (S->coeffs)+(2*(n-1)); + + const float32_t * pXq = xq; + int32_t blkCnt = (int32_t)blockSize; + int32_t blkCnt2; + int32_t i; + float32_t x_sc; + +#ifdef ARM_MATH_NEON + float32x4_t xiv; + float32x4_t aiv; + float32x4_t biv; + float32x4_t civ; + float32x4_t div; + + float32x4_t xqv; + + float32x4_t temp; + float32x4_t diff; + float32x4_t yv; +#endif + + /* Create output for x(i) 4 ) + { + /* Load [xq(k) xq(k+1) xq(k+2) xq(k+3)] */ + xqv = vld1q_f32(pXq); + pXq+=4; + + /* Compute [xq(k)-x(i) xq(k+1)-x(i) xq(k+2)-x(i) xq(k+3)-x(i)] */ + diff = vsubq_f32(xqv, xiv); + temp = diff; + + /* y(i) = a(i) + ... */ + yv = aiv; + /* ... + b(i)*(x-x(i)) + ... */ + yv = vmlaq_f32(yv, biv, temp); + /* ... + c(i)*(x-x(i))^2 + ... */ + temp = vmulq_f32(temp, diff); + yv = vmlaq_f32(yv, civ, temp); + /* ... + d(i)*(x-x(i))^3 */ + temp = vmulq_f32(temp, diff); + yv = vmlaq_f32(yv, div, temp); + + /* Store [y(k) y(k+1) y(k+2) y(k+3)] */ + vst1q_f32(pDst, yv); + pDst+=4; + + blkCnt-=4; + } +#endif + while( *pXq <= x[i+1] && blkCnt > 0 ) + { + x_sc = *pXq++; + + *pDst = y[i]+b[i]*(x_sc-x[i])+c[i]*(x_sc-x[i])*(x_sc-x[i])+d[i]*(x_sc-x[i])*(x_sc-x[i])*(x_sc-x[i]); + + pDst++; + blkCnt--; + } + } + + /* Create output for remaining samples (x>=x(n)) */ +#ifdef ARM_MATH_NEON + /* Compute 4 outputs at a time */ + blkCnt2 = blkCnt >> 2; + + while(blkCnt2 > 0) + { + /* Load [xq(k) xq(k+1) xq(k+2) xq(k+3)] */ + xqv = vld1q_f32(pXq); + pXq+=4; + + /* Compute [xq(k)-x(i) xq(k+1)-x(i) xq(k+2)-x(i) xq(k+3)-x(i)] */ + diff = vsubq_f32(xqv, xiv); + temp = diff; + + /* y(i) = a(i) + ... */ + yv = aiv; + /* ... + b(i)*(x-x(i)) + ... */ + yv = vmlaq_f32(yv, biv, temp); + /* ... + c(i)*(x-x(i))^2 + ... */ + temp = vmulq_f32(temp, diff); + yv = vmlaq_f32(yv, civ, temp); + /* ... + d(i)*(x-x(i))^3 */ + temp = vmulq_f32(temp, diff); + yv = vmlaq_f32(yv, div, temp); + + /* Store [y(k) y(k+1) y(k+2) y(k+3)] */ + vst1q_f32(pDst, yv); + pDst+=4; + + blkCnt2--; + } + + /* Tail */ + blkCnt2 = blkCnt & 3; +#else + blkCnt2 = blkCnt; +#endif + + while(blkCnt2 > 0) + { + x_sc = *pXq++; + + *pDst = y[i-1]+b[i-1]*(x_sc-x[i-1])+c[i-1]*(x_sc-x[i-1])*(x_sc-x[i-1])+d[i-1]*(x_sc-x[i-1])*(x_sc-x[i-1])*(x_sc-x[i-1]); + + pDst++; + blkCnt2--; + } +} + +/** + @} end of SplineInterpolate group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_spline_interp_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_spline_interp_init_f32.c new file mode 100644 index 00000000..ae3f2da0 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_spline_interp_init_f32.c @@ -0,0 +1,175 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_spline_interp_init_f32.c + * Description: Floating-point cubic spline initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + @addtogroup SplineInterpolate + @{ + + @par Initialization function + + The initialization function takes as input two arrays that the user has to allocate: + coeffs will contain the b, c, and d coefficients for the (n-1) intervals + (n is the number of known points), hence its size must be 3*(n-1); tempBuffer + is temporally used for internal computations and its size is n+n-1. + + @par + + The x input array must be strictly sorted in ascending order and it must + not contain twice the same value (x(i)x = x; + S->y = y; + S->n_x = n; + + /* == Solve LZ=B to obtain z(i) and u(i) == */ + + /* -- Row 1 -- */ + /* B(0) = 0, not computed */ + /* u(1,2) = a(1,2)/a(1,1) = a(1,2) */ + if(type == ARM_SPLINE_NATURAL) + u[0] = 0; /* a(1,2) = 0 */ + else if(type == ARM_SPLINE_PARABOLIC_RUNOUT) + u[0] = -1; /* a(1,2) = -1 */ + + z[0] = 0; /* z(1) = B(1)/a(1,1) = 0 always */ + + /* -- Rows 2 to N-1 (N=n+1) -- */ + hm1 = x[1] - x[0]; /* Initialize h(i-1) = h(1) = x(2)-x(1) */ + + for (i=1; i<(int32_t)n-1; i++) + { + /* Compute B(i) */ + hi = x[i+1]-x[i]; + Bi = 3*(y[i+1]-y[i])/hi - 3*(y[i]-y[i-1])/hm1; + + /* l(i) = a(i)-a(i,i-1)*u(i-1) = 2[h(i-1)+h(i)]-h(i-1)*u(i-1) */ + li = 2*(hi+hm1) - hm1*u[i-1]; + + /* u(i) = a(i,i+1)/l(i) = h(i)/l(i) */ + u[i] = hi/li; + + /* z(i) = [B(i)-h(i-1)*z(i-1)]/l(i) */ + z[i] = (Bi-hm1*z[i-1])/li; + + /* Update h(i-1) for next iteration */ + hm1 = hi; + } + + /* -- Row N -- */ + /* l(N) = a(N,N)-a(N,N-1)u(N-1) */ + /* z(N) = [-a(N,N-1)z(N-1)]/l(N) */ + if(type == ARM_SPLINE_NATURAL) + { + /* li = 1; a(N,N) = 1; a(N,N-1) = 0 */ + z[n-1] = 0; /* a(N,N-1) = 0 */ + } + else if(type == ARM_SPLINE_PARABOLIC_RUNOUT) + { + li = 1+u[n-2]; /* a(N,N) = 1; a(N,N-1) = -1 */ + z[n-1] = z[n-2]/li; /* a(N,N-1) = -1 */ + } + + /* == Solve UX = Z to obtain c(i) and */ + /* compute b(i) and d(i) from c(i) == */ + + cp1 = z[n-1]; /* Initialize c(i+1) = c(N) = z(N) */ + + for (i=n-2; i>=0; i--) + { + /* c(i) = z(i)-u(i+1)c(i+1) */ + c[i] = z[i]-u[i]*cp1; + + hi = x[i+1]-x[i]; + /* b(i) = [y(i+1)-y(i)]/h(i)-h(i)*[c(i+1)+2*c(i)]/3 */ + b[i] = (y[i+1]-y[i])/hi-hi*(cp1+2*c[i])/3; + + /* d(i) = [c(i+1)-c(i)]/[3*h(i)] */ + d[i] = (cp1-c[i])/(3*hi); + + /* Update c(i+1) for next iteration */ + cp1 = c[i]; + } + + /* == Finally, store the coefficients in the instance == */ + + S->coeffs = coeffs; +} + +/** + @} end of SplineInterpolate group + */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/CMakeLists.txt new file mode 100644 index 00000000..f2b32118 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/CMakeLists.txt @@ -0,0 +1,54 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPMatrix) + +include(configLib) +include(configDsp) + +file(GLOB SRCF64 "./*_f64.c") +file(GLOB SRCF32 "./*_f32.c") +file(GLOB SRCF16 "./*_f16.c") +file(GLOB SRCQ31 "./*_q31.c") +file(GLOB SRCQ15 "./*_q15.c") +file(GLOB SRCQ7 "./*_q7.c") + +file(GLOB SRCU32 "./*_u32.c") +file(GLOB SRCU16 "./*_u16.c") +file(GLOB SRCU8 "./*_u8.c") + +add_library(CMSISDSPMatrix STATIC ${SRCF64}) +target_sources(CMSISDSPMatrix PRIVATE ${SRCF32}) + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPMatrix PRIVATE ${SRCF16}) +endif() + +target_sources(CMSISDSPMatrix PRIVATE ${SRCQ31}) +target_sources(CMSISDSPMatrix PRIVATE ${SRCQ15}) +target_sources(CMSISDSPMatrix PRIVATE ${SRCQ7}) + +target_sources(CMSISDSPMatrix PRIVATE ${SRCU32}) +target_sources(CMSISDSPMatrix PRIVATE ${SRCU16}) +target_sources(CMSISDSPMatrix PRIVATE ${SRCU8}) + +configLib(CMSISDSPMatrix ${ROOT}) +configDsp(CMSISDSPMatrix ${ROOT}) + +### Includes +target_include_directories(CMSISDSPMatrix PUBLIC "${DSP}/Include") + + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPMatrix PRIVATE arm_mat_add_f16.c) +target_sources(CMSISDSPMatrix PRIVATE arm_mat_sub_f16.c) +target_sources(CMSISDSPMatrix PRIVATE arm_mat_trans_f16.c) +target_sources(CMSISDSPMatrix PRIVATE arm_mat_scale_f16.c) +target_sources(CMSISDSPMatrix PRIVATE arm_mat_mult_f16.c) +target_sources(CMSISDSPMatrix PRIVATE arm_mat_vec_mult_f16.c) +target_sources(CMSISDSPMatrix PRIVATE arm_mat_cmplx_trans_f16.c) +target_sources(CMSISDSPMatrix PRIVATE arm_mat_cmplx_mult_f16.c) +target_sources(CMSISDSPMatrix PRIVATE arm_mat_inverse_f16.c) +target_sources(CMSISDSPMatrix PRIVATE arm_mat_init_f16.c) +target_sources(CMSISDSPMatrix PRIVATE arm_mat_cholesky_f16.c) + +endif() diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c new file mode 100644 index 00000000..d4fa42c1 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: MatrixFunctions.c + * Description: Combination of all matrix function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_mat_add_f32.c" +#include "arm_mat_add_q15.c" +#include "arm_mat_add_q31.c" +#include "arm_mat_cmplx_mult_f32.c" +#include "arm_mat_cmplx_mult_q15.c" +#include "arm_mat_cmplx_mult_q31.c" +#include "arm_mat_init_f32.c" +#include "arm_mat_init_q15.c" +#include "arm_mat_init_q31.c" +#include "arm_mat_inverse_f32.c" +#include "arm_mat_inverse_f64.c" +#include "arm_mat_mult_f64.c" +#include "arm_mat_mult_f32.c" +#include "arm_mat_mult_fast_q15.c" +#include "arm_mat_mult_fast_q31.c" +#include "arm_mat_mult_q7.c" +#include "arm_mat_mult_q15.c" +#include "arm_mat_mult_q31.c" +#include "arm_mat_mult_opt_q31.c" +#include "arm_mat_scale_f32.c" +#include "arm_mat_scale_q15.c" +#include "arm_mat_scale_q31.c" +#include "arm_mat_sub_f64.c" +#include "arm_mat_sub_f32.c" +#include "arm_mat_sub_q15.c" +#include "arm_mat_sub_q31.c" +#include "arm_mat_trans_f32.c" +#include "arm_mat_trans_f64.c" +#include "arm_mat_trans_q7.c" +#include "arm_mat_trans_q15.c" +#include "arm_mat_trans_q31.c" +#include "arm_mat_vec_mult_f32.c" +#include "arm_mat_vec_mult_q31.c" +#include "arm_mat_vec_mult_q15.c" +#include "arm_mat_vec_mult_q7.c" +#include "arm_mat_cmplx_trans_f32.c" +#include "arm_mat_cmplx_trans_q31.c" +#include "arm_mat_cmplx_trans_q15.c" +#include "arm_mat_cholesky_f64.c" +#include "arm_mat_cholesky_f32.c" +#include "arm_mat_solve_upper_triangular_f32.c" +#include "arm_mat_solve_lower_triangular_f32.c" +#include "arm_mat_solve_upper_triangular_f64.c" +#include "arm_mat_solve_lower_triangular_f64.c" +#include "arm_mat_ldlt_f32.c" +#include "arm_mat_ldlt_f64.c" diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctionsF16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctionsF16.c new file mode 100644 index 00000000..9d3a41fb --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctionsF16.c @@ -0,0 +1,41 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: MatrixFunctions.c + * Description: Combination of all matrix function f16 source files. + * + * $Date: 18. March 2020 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_mat_add_f16.c" +#include "arm_mat_sub_f16.c" +#include "arm_mat_trans_f16.c" +#include "arm_mat_scale_f16.c" +#include "arm_mat_mult_f16.c" +#include "arm_mat_vec_mult_f16.c" +#include "arm_mat_cmplx_trans_f16.c" +#include "arm_mat_cmplx_mult_f16.c" +#include "arm_mat_inverse_f16.c" +#include "arm_mat_init_f16.c" +#include "arm_mat_cholesky_f16.c" +#include "arm_mat_solve_upper_triangular_f16.c" +#include "arm_mat_solve_lower_triangular_f16.c" diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f16.c new file mode 100644 index 00000000..2db2c2a2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f16.c @@ -0,0 +1,217 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_add_f16.c + * Description: Floating-point matrix addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixAdd + @{ + */ + + +/** + @brief Floating-point matrix addition. + @param[in] pSrcA points to first input matrix structure + @param[in] pSrcB points to second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_add_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + arm_status status; + uint32_t numSamples; /* total number of elements in the matrix */ + float16_t *pDataA, *pDataB, *pDataDst; + f16x8_t vecA, vecB, vecDst; + float16_t const *pSrcAVec; + float16_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (float16_t const *) pDataA; + pSrcBVec = (float16_t const *) pDataB; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 3; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* Add and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + vecB = vld1q(pSrcBVec); + pSrcBVec += 8; + vecDst = vaddq(vecA, vecB); + vst1q(pDataDst, vecDst); + pDataDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + vecDst = vaddq_m(vecDst, vecA, vecB, p0); + vstrhq_p(pDataDst, vecDst, p0); + } + /* set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + return (status); +} +#else + +arm_status arm_mat_add_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float16_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix addition */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add and store result in destination buffer. */ + *pOut++ = (_Float16)*pInA++ + (_Float16)*pInB++; + + *pOut++ = (_Float16)*pInA++ + (_Float16)*pInB++; + + *pOut++ = (_Float16)*pInA++ + (_Float16)*pInB++; + + *pOut++ = (_Float16)*pInA++ + (_Float16)*pInB++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add and store result in destination buffer. */ + *pOut++ = (_Float16)*pInA++ + (_Float16)*pInB++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixAdd group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c new file mode 100644 index 00000000..879c8f8f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c @@ -0,0 +1,304 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_add_f32.c + * Description: Floating-point matrix addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixAdd Matrix Addition + + Adds two matrices. + \image html MatrixAddition.gif "Addition of two 3 x 3 matrices" + + The functions check to make sure that + pSrcA, pSrcB, and pDst have the same + number of rows and columns. + */ + +/** + @addtogroup MatrixAdd + @{ + */ + + +/** + @brief Floating-point matrix addition. + @param[in] pSrcA points to first input matrix structure + @param[in] pSrcB points to second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + arm_status status; + uint32_t numSamples; /* total number of elements in the matrix */ + float32_t *pDataA, *pDataB, *pDataDst; + f32x4_t vecA, vecB, vecDst; + float32_t const *pSrcAVec; + float32_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (float32_t const *) pDataA; + pSrcBVec = (float32_t const *) pDataB; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 2; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* Add and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + vecDst = vaddq(vecA, vecB); + vst1q(pDataDst, vecDst); + pDataDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + vecDst = vaddq_m(vecDst, vecA, vecB, p0); + vstrwq_p(pDataDst, vecDst, p0); + } + /* set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + return (status); +} +#else +#if defined(ARM_MATH_NEON) +/* + +Neon version is assuming the matrix is small enough. +So no blocking is used for taking into account cache effects. +For big matrix, there exist better libraries for Neon. + +*/ +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix addition */ + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + float32x4_t vec1; + float32x4_t vec2; + float32x4_t res; + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + + blkCnt = numSamples >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pIn1); + vec2 = vld1q_f32(pIn2); + res = vaddq_f32(vec1, vec2); + vst1q_f32(pOut, res); + + /* update pointers to process next samples */ + pIn1 += 4U; + pIn2 += 4U; + pOut += 4U; + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the numSamples is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = numSamples % 0x4U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* Add and then store the results in the destination buffer. */ + *pOut++ = (*pIn1++) + (*pIn2++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix addition */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add and store result in destination buffer. */ + *pOut++ = *pInA++ + *pInB++; + + *pOut++ = *pInA++ + *pInB++; + + *pOut++ = *pInA++ + *pInB++; + + *pOut++ = *pInA++ + *pInB++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add and store result in destination buffer. */ + *pOut++ = *pInA++ + *pInB++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixAdd group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c new file mode 100644 index 00000000..e27b72fa --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c @@ -0,0 +1,227 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_add_q15.c + * Description: Q15 matrix addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixAdd + @{ + */ + +/** + @brief Q15 matrix addition. + @param[in] pSrcA points to first input matrix structure + @param[in] pSrcB points to second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + uint32_t numSamples; /* total number of elements in the matrix */ + q15_t *pDataA, *pDataB, *pDataDst; + q15x8_t vecA, vecB, vecDst; + q15_t const *pSrcAVec; + q15_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix addition */ + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (q15_t const *) pDataA; + pSrcBVec = (q15_t const *) pDataB; + + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 3; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* Add and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); pSrcAVec += 8; + vecB = vld1q(pSrcBVec); pSrcBVec += 8; + vecDst = vqaddq(vecA, vecB); + vst1q(pDataDst, vecDst); pDataDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numSamples & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcAVec); pSrcAVec += 8; + vecB = vld1q(pSrcBVec); pSrcBVec += 8; + vecDst = vqaddq_m(vecDst, vecA, vecB, p0); + vstrhq_p(pDataDst, vecDst, p0); + } + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix addition */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add, saturate and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + write_q15x2_ia (&pOut, __QADD16(read_q15x2_ia (&pInA), read_q15x2_ia (&pInB))); + + write_q15x2_ia (&pOut, __QADD16(read_q15x2_ia (&pInA), read_q15x2_ia (&pInB))); +#else + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); + + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); + + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); + + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add, saturate and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pOut++ = (q15_t) __QADD16(*pInA++, *pInB++); +#else + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixAdd group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c new file mode 100644 index 00000000..57f67e71 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c @@ -0,0 +1,216 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_add_q31.c + * Description: Q31 matrix addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixAdd + @{ + */ + +/** + @brief Q31 matrix addition. + @param[in] pSrcA points to first input matrix structure + @param[in] pSrcB points to second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + arm_status status; /* status of matrix addition */ + uint32_t numSamples; /* total number of elements in the matrix */ + q31_t *pDataA, *pDataB, *pDataDst; + q31x4_t vecA, vecB, vecDst; + q31_t const *pSrcAVec; + q31_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (q31_t const *) pDataA; + pSrcBVec = (q31_t const *) pDataB; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 2; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* Add and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + vecDst = vqaddq(vecA, vecB); + vst1q(pDataDst, vecDst); + pDataDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + vecDst = vqaddq_m(vecDst, vecA, vecB, p0); + vstrwq_p(pDataDst, vecDst, p0); + } + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix addition */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add, saturate and store result in destination buffer. */ + *pOut++ = __QADD(*pInA++, *pInB++); + + *pOut++ = __QADD(*pInA++, *pInB++); + + *pOut++ = __QADD(*pInA++, *pInB++); + + *pOut++ = __QADD(*pInA++, *pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add, saturate and store result in destination buffer. */ + *pOut++ = __QADD(*pInA++, *pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixAdd group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f16.c new file mode 100644 index 00000000..9c8acef6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f16.c @@ -0,0 +1,256 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cholesky_f16.c + * Description: Floating-point Cholesky decomposition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point Cholesky decomposition of positive-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pDst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition of A is returning a lower triangular matrix U such that A = U U^t + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +arm_status arm_mat_cholesky_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + int i,j,k; + int n = pSrc->numRows; + _Float16 invSqrtVj; + float16_t *pA,*pG; + int kCnt; + + mve_pred16_t p0; + + f16x8_t acc, acc0, acc1, acc2, acc3; + f16x8_t vecGi; + f16x8_t vecGj,vecGj0,vecGj1,vecGj2,vecGj3; + + + pA = pSrc->pData; + pG = pDst->pData; + + for(i=0 ;i < n ; i++) + { + for(j=i ; j+3 < n ; j+=4) + { + acc0 = vdupq_n_f16(0.0f16); + acc0[0]=pA[(j + 0) * n + i]; + + acc1 = vdupq_n_f16(0.0f16); + acc1[0]=pA[(j + 1) * n + i]; + + acc2 = vdupq_n_f16(0.0f16); + acc2[0]=pA[(j + 2) * n + i]; + + acc3 = vdupq_n_f16(0.0f16); + acc3[0]=pA[(j + 3) * n + i]; + + kCnt = i; + for(k=0; k < i ; k+=8) + { + p0 = vctp16q(kCnt); + + vecGi=vldrhq_z_f16(&pG[i * n + k],p0); + + vecGj0=vldrhq_z_f16(&pG[(j + 0) * n + k],p0); + vecGj1=vldrhq_z_f16(&pG[(j + 1) * n + k],p0); + vecGj2=vldrhq_z_f16(&pG[(j + 2) * n + k],p0); + vecGj3=vldrhq_z_f16(&pG[(j + 3) * n + k],p0); + + acc0 = vfmsq_m(acc0, vecGi, vecGj0, p0); + acc1 = vfmsq_m(acc1, vecGi, vecGj1, p0); + acc2 = vfmsq_m(acc2, vecGi, vecGj2, p0); + acc3 = vfmsq_m(acc3, vecGi, vecGj3, p0); + + kCnt -= 8; + } + pG[(j + 0) * n + i] = vecAddAcrossF16Mve(acc0); + pG[(j + 1) * n + i] = vecAddAcrossF16Mve(acc1); + pG[(j + 2) * n + i] = vecAddAcrossF16Mve(acc2); + pG[(j + 3) * n + i] = vecAddAcrossF16Mve(acc3); + } + + for(; j < n ; j++) + { + + kCnt = i; + acc = vdupq_n_f16(0.0f16); + acc[0] = pA[j * n + i]; + + for(k=0; k < i ; k+=8) + { + p0 = vctp16q(kCnt); + + vecGi=vldrhq_z_f16(&pG[i * n + k],p0); + vecGj=vldrhq_z_f16(&pG[j * n + k],p0); + + acc = vfmsq_m(acc, vecGi, vecGj,p0); + + kCnt -= 8; + } + pG[j * n + i] = vecAddAcrossF16Mve(acc); + } + + if ((_Float16)pG[i * n + i] <= 0.0f16) + { + return(ARM_MATH_DECOMPOSITION_FAILURE); + } + + invSqrtVj = 1.0f16/(_Float16)sqrtf((float32_t)pG[i * n + i]); + for(j=i; j < n ; j++) + { + pG[j * n + i] = (_Float16)pG[j * n + i] * (_Float16)invSqrtVj ; + } + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_cholesky_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + int i,j,k; + int n = pSrc->numRows; + float16_t invSqrtVj; + float16_t *pA,*pG; + + pA = pSrc->pData; + pG = pDst->pData; + + + for(i=0 ; i < n ; i++) + { + for(j=i ; j < n ; j++) + { + pG[j * n + i] = pA[j * n + i]; + + for(k=0; k < i ; k++) + { + pG[j * n + i] = (_Float16)pG[j * n + i] - (_Float16)pG[i * n + k] * (_Float16)pG[j * n + k]; + } + } + + if ((_Float16)pG[i * n + i] <= 0.0f16) + { + return(ARM_MATH_DECOMPOSITION_FAILURE); + } + + /* The division is done in float32 for accuracy reason and + because doing it in f16 would not have any impact on the performances. + */ + invSqrtVj = 1.0f/sqrtf((float32_t)pG[i * n + i]); + for(j=i ; j < n ; j++) + { + pG[j * n + i] = (_Float16)pG[j * n + i] * (_Float16)invSqrtVj ; + } + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixChol group + */ +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f32.c new file mode 100644 index 00000000..94b96895 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f32.c @@ -0,0 +1,438 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cholesky_f32.c + * Description: Floating-point Cholesky decomposition + * + * $Date: 05 October 2021 + * $Revision: V1.9.1 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixChol Cholesky and LDLT decompositions + + Computes the Cholesky or LDL^t decomposition of a matrix. + + + If the input matrix does not have a decomposition, then the + algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE. + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point Cholesky decomposition of positive-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pDst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition of A is returning a lower triangular matrix U such that A = U U^t + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +arm_status arm_mat_cholesky_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + int i,j,k; + int n = pSrc->numRows; + float32_t invSqrtVj; + float32_t *pA,*pG; + int kCnt; + + mve_pred16_t p0; + + f32x4_t acc, acc0, acc1, acc2, acc3; + f32x4_t vecGi; + f32x4_t vecGj,vecGj0,vecGj1,vecGj2,vecGj3; + + + pA = pSrc->pData; + pG = pDst->pData; + + for(i=0 ;i < n ; i++) + { + for(j=i ; j+3 < n ; j+=4) + { + pG[(j + 0) * n + i] = pA[(j + 0) * n + i]; + pG[(j + 1) * n + i] = pA[(j + 1) * n + i]; + pG[(j + 2) * n + i] = pA[(j + 2) * n + i]; + pG[(j + 3) * n + i] = pA[(j + 3) * n + i]; + + kCnt = i; + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + for(k=0; k < i ; k+=4) + { + p0 = vctp32q(kCnt); + + vecGi=vldrwq_z_f32(&pG[i * n + k],p0); + + vecGj0=vldrwq_z_f32(&pG[(j + 0) * n + k],p0); + vecGj1=vldrwq_z_f32(&pG[(j + 1) * n + k],p0); + vecGj2=vldrwq_z_f32(&pG[(j + 2) * n + k],p0); + vecGj3=vldrwq_z_f32(&pG[(j + 3) * n + k],p0); + + acc0 = vfmaq_m(acc0, vecGi, vecGj0, p0); + acc1 = vfmaq_m(acc1, vecGi, vecGj1, p0); + acc2 = vfmaq_m(acc2, vecGi, vecGj2, p0); + acc3 = vfmaq_m(acc3, vecGi, vecGj3, p0); + + kCnt -= 4; + } + pG[(j + 0) * n + i] -= vecAddAcrossF32Mve(acc0); + pG[(j + 1) * n + i] -= vecAddAcrossF32Mve(acc1); + pG[(j + 2) * n + i] -= vecAddAcrossF32Mve(acc2); + pG[(j + 3) * n + i] -= vecAddAcrossF32Mve(acc3); + } + + for(; j < n ; j++) + { + pG[j * n + i] = pA[j * n + i]; + + kCnt = i; + acc = vdupq_n_f32(0.0f); + + for(k=0; k < i ; k+=4) + { + p0 = vctp32q(kCnt); + + vecGi=vldrwq_z_f32(&pG[i * n + k],p0); + vecGj=vldrwq_z_f32(&pG[j * n + k],p0); + + acc = vfmaq_m(acc, vecGi, vecGj,p0); + + kCnt -= 4; + } + pG[j * n + i] -= vecAddAcrossF32Mve(acc); + } + + if (pG[i * n + i] <= 0.0f) + { + return(ARM_MATH_DECOMPOSITION_FAILURE); + } + + invSqrtVj = 1.0f/sqrtf(pG[i * n + i]); + for(j=i; j < n ; j++) + { + pG[j * n + i] = pG[j * n + i] * invSqrtVj ; + } + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_cholesky_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + int i,j,k; + int n = pSrc->numRows; + float32_t invSqrtVj; + float32_t *pA,*pG; + int kCnt; + + + f32x4_t acc, acc0, acc1, acc2, acc3; + f32x4_t vecGi; + f32x4_t vecGj,vecGj0,vecGj1,vecGj2,vecGj3; +#if !defined(__aarch64__) + f32x2_t tmp = vdup_n_f32(0); +#endif + float32_t sum=0.0f; + float32_t sum0=0.0f,sum1=0.0f,sum2=0.0f,sum3=0.0f; + + + pA = pSrc->pData; + pG = pDst->pData; + + for(i=0 ;i < n ; i++) + { + for(j=i ; j+3 < n ; j+=4) + { + pG[(j + 0) * n + i] = pA[(j + 0) * n + i]; + pG[(j + 1) * n + i] = pA[(j + 1) * n + i]; + pG[(j + 2) * n + i] = pA[(j + 2) * n + i]; + pG[(j + 3) * n + i] = pA[(j + 3) * n + i]; + + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + kCnt = i >> 2; + k=0; + while(kCnt > 0) + { + + vecGi=vld1q_f32(&pG[i * n + k]); + + vecGj0=vld1q_f32(&pG[(j + 0) * n + k]); + vecGj1=vld1q_f32(&pG[(j + 1) * n + k]); + vecGj2=vld1q_f32(&pG[(j + 2) * n + k]); + vecGj3=vld1q_f32(&pG[(j + 3) * n + k]); + + acc0 = vfmaq_f32(acc0, vecGi, vecGj0); + acc1 = vfmaq_f32(acc1, vecGi, vecGj1); + acc2 = vfmaq_f32(acc2, vecGi, vecGj2); + acc3 = vfmaq_f32(acc3, vecGi, vecGj3); + + kCnt--; + k+=4; + } + +#if defined(__aarch64__) + sum0 = vpadds_f32(vpadd_f32(vget_low_f32(acc0), vget_high_f32(acc0))); + sum1 = vpadds_f32(vpadd_f32(vget_low_f32(acc1), vget_high_f32(acc1))); + sum2 = vpadds_f32(vpadd_f32(vget_low_f32(acc2), vget_high_f32(acc2))); + sum3 = vpadds_f32(vpadd_f32(vget_low_f32(acc3), vget_high_f32(acc3))); + +#else + tmp = vpadd_f32(vget_low_f32(acc0), vget_high_f32(acc0)); + sum0 = vget_lane_f32(tmp, 0) + vget_lane_f32(tmp, 1); + + tmp = vpadd_f32(vget_low_f32(acc1), vget_high_f32(acc1)); + sum1 = vget_lane_f32(tmp, 0) + vget_lane_f32(tmp, 1); + + tmp = vpadd_f32(vget_low_f32(acc2), vget_high_f32(acc2)); + sum2 = vget_lane_f32(tmp, 0) + vget_lane_f32(tmp, 1); + + tmp = vpadd_f32(vget_low_f32(acc3), vget_high_f32(acc3)); + sum3 = vget_lane_f32(tmp, 0) + vget_lane_f32(tmp, 1); +#endif + + kCnt = i & 3; + while(kCnt > 0) + { + + sum0 = sum0 + pG[i * n + k] * pG[(j + 0) * n + k]; + sum1 = sum1 + pG[i * n + k] * pG[(j + 1) * n + k]; + sum2 = sum2 + pG[i * n + k] * pG[(j + 2) * n + k]; + sum3 = sum3 + pG[i * n + k] * pG[(j + 3) * n + k]; + kCnt--; + k++; + } + + pG[(j + 0) * n + i] -= sum0; + pG[(j + 1) * n + i] -= sum1; + pG[(j + 2) * n + i] -= sum2; + pG[(j + 3) * n + i] -= sum3; + } + + for(; j < n ; j++) + { + pG[j * n + i] = pA[j * n + i]; + + acc = vdupq_n_f32(0.0f); + + kCnt = i >> 2; + k=0; + while(kCnt > 0) + { + + vecGi=vld1q_f32(&pG[i * n + k]); + vecGj=vld1q_f32(&pG[j * n + k]); + + acc = vfmaq_f32(acc, vecGi, vecGj); + + kCnt--; + k+=4; + } + +#if defined(__aarch64__) + sum = vpadds_f32(vpadd_f32(vget_low_f32(acc), vget_high_f32(acc))); +#else + tmp = vpadd_f32(vget_low_f32(acc), vget_high_f32(acc)); + sum = vget_lane_f32(tmp, 0) + vget_lane_f32(tmp, 1); +#endif + + kCnt = i & 3; + while(kCnt > 0) + { + sum = sum + pG[i * n + k] * pG[(j + 0) * n + k]; + + + kCnt--; + k++; + } + + pG[j * n + i] -= sum; + } + + if (pG[i * n + i] <= 0.0f) + { + return(ARM_MATH_DECOMPOSITION_FAILURE); + } + + invSqrtVj = 1.0f/sqrtf(pG[i * n + i]); + for(j=i; j < n ; j++) + { + pG[j * n + i] = pG[j * n + i] * invSqrtVj ; + } + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_cholesky_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + int i,j,k; + int n = pSrc->numRows; + float32_t invSqrtVj; + float32_t *pA,*pG; + + pA = pSrc->pData; + pG = pDst->pData; + + + for(i=0 ; i < n ; i++) + { + for(j=i ; j < n ; j++) + { + pG[j * n + i] = pA[j * n + i]; + + for(k=0; k < i ; k++) + { + pG[j * n + i] = pG[j * n + i] - pG[i * n + k] * pG[j * n + k]; + } + } + + if (pG[i * n + i] <= 0.0f) + { + return(ARM_MATH_DECOMPOSITION_FAILURE); + } + + invSqrtVj = 1.0f/sqrtf(pG[i * n + i]); + for(j=i ; j < n ; j++) + { + pG[j * n + i] = pG[j * n + i] * invSqrtVj ; + } + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixChol group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f64.c new file mode 100644 index 00000000..4e095d06 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f64.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cholesky_f64.c + * Description: Floating-point Cholesky decomposition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point Cholesky decomposition of positive-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pDst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition of A is returning a lower triangular matrix U such that A = U U^t + */ + + +arm_status arm_mat_cholesky_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pDst) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + int i,j,k; + int n = pSrc->numRows; + float64_t invSqrtVj; + float64_t *pA,*pG; + + pA = pSrc->pData; + pG = pDst->pData; + + + for(i=0 ; i < n ; i++) + { + for(j=i ; j < n ; j++) + { + pG[j * n + i] = pA[j * n + i]; + + for(k=0; k < i ; k++) + { + pG[j * n + i] = pG[j * n + i] - pG[i * n + k] * pG[j * n + k]; + } + } + + if (pG[i * n + i] <= 0.0) + { + return(ARM_MATH_DECOMPOSITION_FAILURE); + } + + invSqrtVj = 1.0/sqrt(pG[i * n + i]); + for(j=i ; j < n ; j++) + { + pG[j * n + i] = pG[j * n + i] * invSqrtVj ; + } + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixChol group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f16.c new file mode 100644 index 00000000..f5666962 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f16.c @@ -0,0 +1,935 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_mult_f16.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup CmplxMatrixMult + @{ + */ + +/** + @brief Floating-point Complex matrix multiplication. + @param[in] pSrcA points to first input complex matrix structure + @param[in] pSrcB points to second input complex matrix structure + @param[out] pDst points to output complex matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_mat_cmplx_mult_f16 built. Helium version has build issues with gcc." +#endif + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) + +#include "arm_helium_utils.h" + +#define DONTCARE 0 /* inactive lane content */ + + +__STATIC_FORCEINLINE arm_status arm_mat_cmplx_mult_f16_2x2_mve( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ +#define MATRIX_DIM 2 + float16_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + float16_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16x8_t vecColBOffs0,vecColAOffs0,vecColAOffs1; + float16_t *pInA0 = pInA; + f16x8_t acc0, acc1; + f16x8_t vecB, vecA0, vecA1; + f16x8_t vecTmp; + uint16_t tmp; + static const uint16_t offsetB0[8] = { 0, 1, + MATRIX_DIM * CMPLX_DIM, MATRIX_DIM * CMPLX_DIM + 1, + 2, 3, + MATRIX_DIM * CMPLX_DIM + 2 , MATRIX_DIM * CMPLX_DIM + 3, + }; + + + vecColBOffs0 = vldrhq_u16((uint16_t const *) offsetB0); + + tmp = 0; + vecColAOffs0 = viwdupq_u16(tmp, 4, 1); + + tmp = (CMPLX_DIM * MATRIX_DIM); + vecColAOffs1 = vecColAOffs0 + (uint16_t)(CMPLX_DIM * MATRIX_DIM); + + + pInB = (float16_t const *)pSrcB->pData; + + vecA0 = vldrhq_gather_shifted_offset_f16(pInA0, vecColAOffs0); + vecA1 = vldrhq_gather_shifted_offset_f16(pInA0, vecColAOffs1); + + + vecB = vldrhq_gather_shifted_offset(pInB, vecColBOffs0); + + acc0 = vcmulq(vecA0, vecB); + acc0 = vcmlaq_rot90(acc0, vecA0, vecB); + + acc1 = vcmulq(vecA1, vecB); + acc1 = vcmlaq_rot90(acc1, vecA1, vecB); + + + /* + * Compute + * re0+re1 | im0+im1 | re0+re1 | im0+im1 + * re2+re3 | im2+im3 | re2+re3 | im2+im3 + */ + + vecTmp = (f16x8_t) vrev64q_s32((int32x4_t) acc0); + vecTmp = vaddq(vecTmp, acc0); + + + *(float32_t *)(&pOut[0 * CMPLX_DIM * MATRIX_DIM]) = ((f32x4_t)vecTmp)[0]; + *(float32_t *)(&pOut[0 * CMPLX_DIM * MATRIX_DIM + CMPLX_DIM]) = ((f32x4_t)vecTmp)[2]; + + vecTmp = (f16x8_t) vrev64q_s32((int32x4_t) acc1); + vecTmp = vaddq(vecTmp, acc1); + + *(float32_t *)(&pOut[1 * CMPLX_DIM * MATRIX_DIM]) = ((f32x4_t)vecTmp)[0]; + *(float32_t *)(&pOut[1 * CMPLX_DIM * MATRIX_DIM + CMPLX_DIM]) = ((f32x4_t)vecTmp)[2]; + + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +#undef MATRIX_DIM +} + + + +__STATIC_FORCEINLINE arm_status arm_mat_cmplx_mult_f16_3x3_mve( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ +#define MATRIX_DIM 3 + float16_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + float16_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16x8_t vecColBOffs0; + float16_t *pInA0 = pInA; + float16_t *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM; + float16_t *pInA2 = pInA1 + CMPLX_DIM * MATRIX_DIM; + f16x8_t acc0, acc1, acc2; + f16x8_t vecB, vecA0, vecA1, vecA2; + static const uint16_t offsetB0[8] = { 0, 1, + MATRIX_DIM * CMPLX_DIM, MATRIX_DIM * CMPLX_DIM + 1, + 2 * MATRIX_DIM * CMPLX_DIM, 2 * MATRIX_DIM * CMPLX_DIM + 1, + DONTCARE, DONTCARE + }; + + + /* enable predication to disable upper half complex vector element */ + mve_pred16_t p0 = vctp16q(MATRIX_DIM * CMPLX_DIM); + + vecColBOffs0 = vldrhq_u16((uint16_t const *) offsetB0); + + pInB = (float16_t const *)pSrcB->pData; + + vecA0 = vldrhq_f16(pInA0); + vecA1 = vldrhq_f16(pInA1); + vecA2 = vldrhq_f16(pInA2); + + vecB = vldrhq_gather_shifted_offset_z(pInB, vecColBOffs0, p0); + + acc0 = vcmulq(vecA0, vecB); + acc0 = vcmlaq_rot90(acc0, vecA0, vecB); + + acc1 = vcmulq(vecA1, vecB); + acc1 = vcmlaq_rot90(acc1, vecA1, vecB); + + acc2 = vcmulq(vecA2, vecB); + acc2 = vcmlaq_rot90(acc2, vecA2, vecB); + + mve_cmplx_sum_intra_vec_f16(acc0, &pOut[0 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc1, &pOut[1 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc2, &pOut[2 * CMPLX_DIM * MATRIX_DIM]); + pOut += CMPLX_DIM; + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrhq_gather_shifted_offset_z(pInB, vecColBOffs0, p0); + + acc0 = vcmulq(vecA0, vecB); + acc0 = vcmlaq_rot90(acc0, vecA0, vecB); + + acc1 = vcmulq(vecA1, vecB); + acc1 = vcmlaq_rot90(acc1, vecA1, vecB); + + acc2 = vcmulq(vecA2, vecB); + acc2 = vcmlaq_rot90(acc2, vecA2, vecB); + + mve_cmplx_sum_intra_vec_f16(acc0, &pOut[0 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc1, &pOut[1 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc2, &pOut[2 * CMPLX_DIM * MATRIX_DIM]); + pOut += CMPLX_DIM; + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrhq_gather_shifted_offset_z(pInB, vecColBOffs0, p0); + + acc0 = vcmulq(vecA0, vecB); + acc0 = vcmlaq_rot90(acc0, vecA0, vecB); + + acc1 = vcmulq(vecA1, vecB); + acc1 = vcmlaq_rot90(acc1, vecA1, vecB); + + acc2 = vcmulq(vecA2, vecB); + acc2 = vcmlaq_rot90(acc2, vecA2, vecB); + + mve_cmplx_sum_intra_vec_f16(acc0, &pOut[0 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc1, &pOut[1 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc2, &pOut[2 * CMPLX_DIM * MATRIX_DIM]); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +#undef MATRIX_DIM +} + + + + +__STATIC_FORCEINLINE arm_status arm_mat_cmplx_mult_f16_4x4_mve( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ +#define MATRIX_DIM 4 + float16_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + float16_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16x8_t vecColBOffs0; + float16_t *pInA0 = pInA; + float16_t *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM; + float16_t *pInA2 = pInA1 + CMPLX_DIM * MATRIX_DIM; + float16_t *pInA3 = pInA2 + CMPLX_DIM * MATRIX_DIM; + f16x8_t acc0, acc1, acc2, acc3; + f16x8_t vecB, vecA; + static const uint16_t offsetB0[8] = { 0, 1, + MATRIX_DIM * CMPLX_DIM, MATRIX_DIM * CMPLX_DIM + 1, + 2 * MATRIX_DIM * CMPLX_DIM, 2 * MATRIX_DIM * CMPLX_DIM + 1, + 3 * MATRIX_DIM * CMPLX_DIM, 3 * MATRIX_DIM * CMPLX_DIM + 1 + }; + + vecColBOffs0 = vldrhq_u16((uint16_t const *) offsetB0); + + pInB = (float16_t const *)pSrcB->pData; + + vecB = vldrhq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrhq_f16(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrhq_f16(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrhq_f16(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrhq_f16(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + + mve_cmplx_sum_intra_vec_f16(acc0, &pOut[0 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc1, &pOut[1 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc2, &pOut[2 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc3, &pOut[3 * CMPLX_DIM * MATRIX_DIM]); + pOut += CMPLX_DIM; + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrhq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrhq_f16(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrhq_f16(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrhq_f16(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrhq_f16(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + + mve_cmplx_sum_intra_vec_f16(acc0, &pOut[0 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc1, &pOut[1 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc2, &pOut[2 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc3, &pOut[3 * CMPLX_DIM * MATRIX_DIM]); + pOut += CMPLX_DIM; + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrhq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrhq_f16(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrhq_f16(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrhq_f16(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrhq_f16(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + + mve_cmplx_sum_intra_vec_f16(acc0, &pOut[0 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc1, &pOut[1 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc2, &pOut[2 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc3, &pOut[3 * CMPLX_DIM * MATRIX_DIM]); + pOut += CMPLX_DIM; + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrhq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrhq_f16(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrhq_f16(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrhq_f16(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrhq_f16(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + + mve_cmplx_sum_intra_vec_f16(acc0, &pOut[0 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc1, &pOut[1 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc2, &pOut[2 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc3, &pOut[3 * CMPLX_DIM * MATRIX_DIM]); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +#undef MATRIX_DIM +} + + + +arm_status arm_mat_cmplx_mult_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + float16_t const *pInB = (float16_t const *) pSrcB->pData; /* input data matrix pointer B */ + float16_t const *pInA = (float16_t const *) pSrcA->pData; /* input data matrix pointer A */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + float16_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint16_t col, i = 0U, row = numRowsA; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + uint16x8_t vecOffs, vecColBOffs; + uint32_t blkCnt,rowCnt; /* loop counters */ + + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ +if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + /* + * small squared matrix specialized routines + */ + if (numRowsA == numColsB && numColsB == numColsA) + { + if (numRowsA == 1) + { + pOut[0] = (_Float16)pInA[0] * (_Float16)pInB[0] - (_Float16)pInA[1] * (_Float16)pInB[1]; + pOut[1] = (_Float16)pInA[0] * (_Float16)pInB[1] + (_Float16)pInA[1] * (_Float16)pInB[0]; + return (ARM_MATH_SUCCESS); + } + else if (numRowsA == 2) + return arm_mat_cmplx_mult_f16_2x2_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 3) + return arm_mat_cmplx_mult_f16_3x3_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 4) + return arm_mat_cmplx_mult_f16_4x4_mve(pSrcA, pSrcB, pDst); + } + + vecColBOffs[0] = 0; + vecColBOffs[1] = 1; + vecColBOffs[2] = numColsB * CMPLX_DIM; + vecColBOffs[3] = (numColsB * CMPLX_DIM) + 1; + vecColBOffs[4] = 2*numColsB * CMPLX_DIM; + vecColBOffs[5] = 2*(numColsB * CMPLX_DIM) + 1; + vecColBOffs[6] = 3*numColsB * CMPLX_DIM; + vecColBOffs[7] = 3*(numColsB * CMPLX_DIM) + 1; + + /* + * The following loop performs the dot-product of each row in pSrcA with each column in pSrcB + */ + + /* + * row loop + */ + rowCnt = row >> 2; + while (rowCnt > 0u) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i * CMPLX_DIM; + i = i + 4 * numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (float16_t const *) pSrcB->pData; + /* + * column loop + */ + while (col > 0u) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec; + float16_t const *pInA0 = pInA; + float16_t const *pInA1 = pInA0 + numColsA * CMPLX_DIM; + float16_t const *pInA2 = pInA1 + numColsA * CMPLX_DIM; + float16_t const *pInA3 = pInA2 + numColsA * CMPLX_DIM; + f16x8_t acc0, acc1, acc2, acc3; + + acc0 = vdupq_n_f16(0.0f16); + acc1 = vdupq_n_f16(0.0f16); + acc2 = vdupq_n_f16(0.0f16); + acc3 = vdupq_n_f16(0.0f16); + + pSrcA0Vec = (float16_t const *) pInA0; + pSrcA1Vec = (float16_t const *) pInA1; + pSrcA2Vec = (float16_t const *) pInA2; + pSrcA3Vec = (float16_t const *) pInA3; + + vecOffs = vecColBOffs; + + /* + * process 1 x 4 block output + */ + blkCnt = (numColsA * CMPLX_DIM) >> 3; + while (blkCnt > 0U) + { + f16x8_t vecB, vecA; + + vecB = vldrhq_gather_shifted_offset_f16(pInB, vecOffs); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vaddq_n_u16(vecOffs , (uint16_t) (numColsB * 4 * CMPLX_DIM)); + + vecA = vld1q(pSrcA0Vec); pSrcA0Vec += 8; + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vld1q(pSrcA1Vec); pSrcA1Vec += 8; + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vld1q(pSrcA2Vec); pSrcA2Vec += 8; + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vld1q(pSrcA3Vec); pSrcA3Vec += 8; + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + blkCnt--; + } + /* + * Unsupported addressing mode compiler crash + */ + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numColsA * CMPLX_DIM) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecB, vecA; + + vecB = vldrhq_gather_shifted_offset_z_f16(pInB, vecOffs, p0); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vaddq_n_u16(vecOffs, (uint16_t) (numColsB * 4 * CMPLX_DIM)); + + vecA = vld1q(pSrcA0Vec); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vld1q(pSrcA1Vec); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vld1q(pSrcA2Vec); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vld1q(pSrcA3Vec); + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + } + + + mve_cmplx_sum_intra_vec_f16(acc0, &px[0 * CMPLX_DIM * numColsB + 0]); + mve_cmplx_sum_intra_vec_f16(acc1, &px[1 * CMPLX_DIM * numColsB + 0]); + mve_cmplx_sum_intra_vec_f16(acc2, &px[2 * CMPLX_DIM * numColsB + 0]); + mve_cmplx_sum_intra_vec_f16(acc3, &px[3 * CMPLX_DIM * numColsB + 0]); + + px += CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (float16_t const *) pSrcB->pData + (numColsB - col) * CMPLX_DIM; + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += (numColsA * 4) * CMPLX_DIM; + /* + * Decrement the row loop counter + */ + rowCnt --; + + } + + rowCnt = row & 3; + while (rowCnt > 0u) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i * CMPLX_DIM; + i = i + numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (float16_t const *) pSrcB->pData; + /* + * column loop + */ + while (col > 0u) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + float16_t const *pSrcA0Vec; + float16_t const *pInA0 = pInA; + f16x8_t acc0; + + acc0 = vdupq_n_f16(0.0f16); + + pSrcA0Vec = (float16_t const *) pInA0; + + vecOffs = vecColBOffs; + + /* + * process 1 x 4 block output + */ + blkCnt = (numColsA * CMPLX_DIM) >> 3; + while (blkCnt > 0U) + { + f16x8_t vecB, vecA; + + vecB = vldrhq_gather_shifted_offset(pInB, vecOffs); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vaddq_n_u16(vecOffs, (uint16_t) (4*numColsB * CMPLX_DIM)); + + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + + blkCnt--; + } + + + /* + * tail + */ + blkCnt = (numColsA * CMPLX_DIM) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecB, vecA; + + vecB = vldrhq_gather_shifted_offset_z(pInB, vecOffs, p0); + + vecA = vld1q(pSrcA0Vec); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + } + + mve_cmplx_sum_intra_vec_f16(acc0, &px[0]); + + + px += CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (float16_t const *) pSrcB->pData + (numColsB - col) * CMPLX_DIM; + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += numColsA * CMPLX_DIM; + rowCnt--; + } + + /* + * set status as ARM_MATH_SUCCESS + */ + status = ARM_MATH_SUCCESS; + } + /* + * Return to application + */ + return (status); +} +#else + +arm_status arm_mat_cmplx_mult_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + float16_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + float16_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + float16_t *pOut = pDst->pData; /* Output data matrix pointer */ + float16_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + _Float16 sumReal, sumImag; /* Accumulator */ + _Float16 a1, b1, c1, d1; + uint32_t col, i = 0U, j, row = numRowsA, colCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + +#if defined (ARM_MATH_LOOPUNROLL) + _Float16 a0, b0, c0, d0; +#endif + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + 2 * i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sumReal = 0.0f16; + sumImag = 0.0f16; + + /* Initiate pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + + /* Reading real part of complex matrix A */ + a0 = *pIn1; + + /* Reading real part of complex matrix B */ + c0 = *pIn2; + + /* Reading imaginary part of complex matrix A */ + b0 = *(pIn1 + 1U); + + /* Reading imaginary part of complex matrix B */ + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a0 * c0; + sumImag += b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b0 * d0; + sumImag += a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + a0 = *(pIn1 ); + c0 = *(pIn2 ); + b0 = *(pIn1 + 1U); + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a0 * c0; + sumImag += b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b0 * d0; + sumImag += a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + /* Decrement loop count */ + colCnt--; + } + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = sumReal; + *px++ = sumImag; + + /* Update pointer pIn2 to point to starting address of next column */ + j++; + pIn2 = pSrcB->pData + 2U * j; + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + 2 * numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixMult group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c new file mode 100644 index 00000000..5add938b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c @@ -0,0 +1,1407 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_mult_f32.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup CmplxMatrixMult Complex Matrix Multiplication + + Complex Matrix multiplication is only defined if the number of columns of the + first matrix equals the number of rows of the second matrix. + Multiplying an M x N matrix with an N x P matrix results + in an M x P matrix. + @par + When matrix size checking is enabled, the functions check: + - that the inner dimensions of pSrcA and pSrcB are equal; + - that the size of the output matrix equals the outer dimensions of pSrcA and pSrcB. + */ + + +/** + @addtogroup CmplxMatrixMult + @{ + */ + +/** + @brief Floating-point Complex matrix multiplication. + @param[in] pSrcA points to first input complex matrix structure + @param[in] pSrcB points to second input complex matrix structure + @param[out] pDst points to output complex matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +#define MATRIX_DIM2 2 +#define MATRIX_DIM3 3 +#define MATRIX_DIM4 4 + +__STATIC_INLINE arm_status arm_mat_cmplx_mult_f32_2x2_mve( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs0; + float32_t *pInA0 = pInA; + float32_t *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM2; + f32x4_t acc0, acc1; + f32x4_t vecB, vecA; + + static const uint32_t offsetB0[4] = { 0, 1, + MATRIX_DIM2 * CMPLX_DIM, MATRIX_DIM2 * CMPLX_DIM + 1 + }; + + vecColBOffs0 = vldrwq_u32((uint32_t const *) offsetB0); + + pInB = (float32_t const *)pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 1] = acc1[1] + acc1[3]; + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 1] = acc1[1] + acc1[3]; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +__STATIC_INLINE arm_status arm_mat_cmplx_mult_f32_3x3_mve( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs0, vecColBOffs1; + float32_t *pInA0 = pInA; + float32_t *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM3; + float32_t *pInA2 = pInA1 + CMPLX_DIM * MATRIX_DIM3; + f32x4_t acc0, acc1, acc2; + f32x4_t vecB, vecA; + /* enable predication to disable upper half complex vector element */ + mve_pred16_t p0 = vctp32q(CMPLX_DIM); + + static const uint32_t offsetB0[4] = { 0, 1, + MATRIX_DIM3 * CMPLX_DIM, MATRIX_DIM3 * CMPLX_DIM + 1 + }; + static const uint32_t offsetB1[4] = { 2 * MATRIX_DIM3 * CMPLX_DIM, 2 * MATRIX_DIM3 * CMPLX_DIM + 1, + INACTIVELANE, INACTIVELANE + }; + + vecColBOffs0 = vldrwq_u32((uint32_t const *) offsetB0); + vecColBOffs1 = vldrwq_u32((uint32_t const *) offsetB1); + + pInB = (float32_t const *)pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecColBOffs1, p0); + + vecA = vldrwq_f32(&pInA0[4]); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(&pInA1[4]); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(&pInA2[4]); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc1[1] + acc1[3]; + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc2[0] + acc2[2]; + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc2[1] + acc2[3]; + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecColBOffs1, p0); + + vecA = vldrwq_f32(&pInA0[4]); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(&pInA1[4]); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(&pInA2[4]); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc1[1] + acc1[3]; + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc2[0] + acc2[2]; + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc2[1] + acc2[3]; + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecColBOffs1, p0); + + vecA = vldrwq_f32(&pInA0[4]); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(&pInA1[4]); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(&pInA2[4]); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc1[1] + acc1[3]; + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc2[0] + acc2[2]; + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc2[1] + acc2[3]; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + + +__STATIC_INLINE arm_status arm_mat_cmplx_mult_f32_4x4_mve( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs0, vecColBOffs1; + float32_t *pInA0 = pInA; + float32_t *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM4; + float32_t *pInA2 = pInA1 + CMPLX_DIM * MATRIX_DIM4; + float32_t *pInA3 = pInA2 + CMPLX_DIM * MATRIX_DIM4; + f32x4_t acc0, acc1, acc2, acc3; + f32x4_t vecB, vecA; + + static const uint32_t offsetB0[4] = { 0, 1, + MATRIX_DIM4 * CMPLX_DIM, MATRIX_DIM4 * CMPLX_DIM + 1 + }; + static const uint32_t offsetB1[4] = { 2 * MATRIX_DIM4 * CMPLX_DIM, 2 * MATRIX_DIM4 * CMPLX_DIM + 1, + 3 * MATRIX_DIM4 * CMPLX_DIM, 3 * MATRIX_DIM4 * CMPLX_DIM + 1 + }; + + vecColBOffs0 = vldrwq_u32((uint32_t const *) offsetB0); + vecColBOffs1 = vldrwq_u32((uint32_t const *) offsetB1); + + pInB = (float32_t const *)pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_f32(&pInA0[4]); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(&pInA1[4]); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(&pInA2[4]); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(&pInA3[4]); + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc1[1] + acc1[3]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc2[0] + acc2[2]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc2[1] + acc2[3]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc3[0] + acc3[2]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc3[1] + acc3[3]; + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_f32(&pInA0[4]); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(&pInA1[4]); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(&pInA2[4]); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(&pInA3[4]); + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc1[1] + acc1[3]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc2[0] + acc2[2]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc2[1] + acc2[3]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc3[0] + acc3[2]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc3[1] + acc3[3]; + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_f32(&pInA0[4]); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(&pInA1[4]); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(&pInA2[4]); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(&pInA3[4]); + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc1[1] + acc1[3]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc2[0] + acc2[2]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc2[1] + acc2[3]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc3[0] + acc3[2]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc3[1] + acc3[3]; + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_f32(&pInA0[4]); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(&pInA1[4]); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(&pInA2[4]); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(&pInA3[4]); + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc1[1] + acc1[3]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc2[0] + acc2[2]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc2[1] + acc2[3]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc3[0] + acc3[2]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc3[1] + acc3[3]; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t const *pInB = (float32_t const *) pSrcB->pData; /* input data matrix pointer B */ + float32_t const *pInA = (float32_t const *) pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint16_t col, i = 0U, row = numRowsA; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + uint32x4_t vecOffs, vecColBOffs; + uint32_t blkCnt, rowCnt; /* loop counters */ + + #ifdef ARM_MATH_MATRIX_CHECK + + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols)) + { + + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* + * small squared matrix specialized routines + */ + if (numRowsA == numColsB && numColsB == numColsA) + { + if (numRowsA == 1) + { + pOut[0] = pInA[0] * pInB[0] - pInA[1] * pInB[1]; + pOut[1] = pInA[0] * pInB[1] + pInA[1] * pInB[0]; + return (ARM_MATH_SUCCESS); + } + else if (numRowsA == 2) + return arm_mat_cmplx_mult_f32_2x2_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 3) + return arm_mat_cmplx_mult_f32_3x3_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 4) + return arm_mat_cmplx_mult_f32_4x4_mve(pSrcA, pSrcB, pDst); + } + + vecColBOffs[0] = 0; + vecColBOffs[1] = 1; + vecColBOffs[2] = numColsB * CMPLX_DIM; + vecColBOffs[3] = (numColsB * CMPLX_DIM) + 1; + + /* + * The following loop performs the dot-product of each row in pSrcA with each column in pSrcB + */ + + /* + * row loop + */ + rowCnt = row >> 2; + while (rowCnt > 0u) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i * CMPLX_DIM; + i = i + 4 * numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (float32_t const *) pSrcB->pData; + /* + * column loop + */ + while (col > 0u) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec; + float32_t const *pInA0 = pInA; + float32_t const *pInA1 = pInA0 + numColsA * CMPLX_DIM; + float32_t const *pInA2 = pInA1 + numColsA * CMPLX_DIM; + float32_t const *pInA3 = pInA2 + numColsA * CMPLX_DIM; + f32x4_t acc0, acc1, acc2, acc3; + + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + pSrcA0Vec = (float32_t const *) pInA0; + pSrcA1Vec = (float32_t const *) pInA1; + pSrcA2Vec = (float32_t const *) pInA2; + pSrcA3Vec = (float32_t const *) pInA3; + + vecOffs = vecColBOffs; + + /* + * process 1 x 4 block output + */ + blkCnt = (numColsA * CMPLX_DIM) >> 2; + while (blkCnt > 0U) + { + f32x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset(pInB, vecOffs); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vecOffs + (uint32_t) (numColsB * 2 * CMPLX_DIM); + + vecA = vld1q(pSrcA0Vec); pSrcA0Vec += 4; + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + vecA = vld1q(pSrcA1Vec); pSrcA1Vec += 4; + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + vecA = vld1q(pSrcA2Vec); pSrcA2Vec += 4; + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + vecA = vld1q(pSrcA3Vec); pSrcA3Vec += 4; + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + blkCnt--; + } + + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numColsA * CMPLX_DIM) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecOffs, p0); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vecOffs + (uint32_t) (numColsB * 2 * CMPLX_DIM); + + vecA = vld1q(pSrcA0Vec); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + vecA = vld1q(pSrcA1Vec); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + vecA = vld1q(pSrcA2Vec); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + vecA = vld1q(pSrcA3Vec); + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + } + + px[0 * CMPLX_DIM * numColsB + 0] = acc0[0] + acc0[2]; + px[0 * CMPLX_DIM * numColsB + 1] = acc0[1] + acc0[3]; + px[1 * CMPLX_DIM * numColsB + 0] = acc1[0] + acc1[2]; + px[1 * CMPLX_DIM * numColsB + 1] = acc1[1] + acc1[3]; + px[2 * CMPLX_DIM * numColsB + 0] = acc2[0] + acc2[2]; + px[2 * CMPLX_DIM * numColsB + 1] = acc2[1] + acc2[3]; + px[3 * CMPLX_DIM * numColsB + 0] = acc3[0] + acc3[2]; + px[3 * CMPLX_DIM * numColsB + 1] = acc3[1] + acc3[3]; + px += CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (float32_t const *) pSrcB->pData + (numColsB - col) * CMPLX_DIM; + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += (numColsA * 4) * CMPLX_DIM; + /* + * Decrement the row loop counter + */ + rowCnt --; + + } + + rowCnt = row & 3; + while (rowCnt > 0u) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i * CMPLX_DIM; + i = i + numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (float32_t const *) pSrcB->pData; + /* + * column loop + */ + while (col > 0u) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + float32_t const *pSrcA0Vec; + float32_t const *pInA0 = pInA; + f32x4_t acc0; + + acc0 = vdupq_n_f32(0.0f); + + pSrcA0Vec = (float32_t const *) pInA0; + + vecOffs = vecColBOffs; + + /* + * process 1 x 4 block output + */ + blkCnt = (numColsA * CMPLX_DIM) >> 2; + while (blkCnt > 0U) + { + f32x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset(pInB, vecOffs); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vecOffs + (uint32_t) (numColsB * 2 * CMPLX_DIM); + + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + + blkCnt--; + } + + + /* + * tail + */ + blkCnt = (numColsA * CMPLX_DIM) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecOffs, p0); + + vecA = vld1q(pSrcA0Vec); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + } + + px[0] = acc0[0] + acc0[2]; + px[1] = acc0[1] + acc0[3]; + + px += CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (float32_t const *) pSrcB->pData + (numColsB - col) * CMPLX_DIM; + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += numColsA * CMPLX_DIM; + rowCnt--; + } + + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +} + +#else +#if defined(ARM_MATH_NEON) +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + float32_t sumReal1, sumImag1; /* accumulator */ + float32_t a1, a1B,b1, b1B, c1, d1; + float32_t sumReal2, sumImag2; /* accumulator */ + + + float32x4x2_t a0V, a1V; + float32x4_t accR0,accI0, accR1,accI1,tempR, tempI; + float32x2_t accum = vdup_n_f32(0); + float32_t *pIn1B = pSrcA->pData; + + uint16_t col, i = 0U, j, rowCnt, row = numRowsA, colCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + float32_t sumReal1B, sumImag1B; + float32_t sumReal2B, sumImag2B; + float32_t *pxB; + +#ifdef ARM_MATH_MATRIX_CHECK + + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols)) + { + + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + + rowCnt = row >> 1; + + /* Row loop */ + while (rowCnt > 0U) + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + 2 * i; + pxB = px + 2 * numColsB; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* Column loop */ + while (col > 0U) + { + /* Set the variable sum, that acts as accumulator, to zero */ + sumReal1 = 0.0f; + sumImag1 = 0.0f; + sumReal1B = 0.0f; + sumImag1B = 0.0f; + + sumReal2 = 0.0f; + sumImag2 = 0.0f; + sumReal2B = 0.0f; + sumImag2B = 0.0f; + + /* Initiate the pointer pIn1 to point to the starting address of the column being processed */ + pIn1 = pInA; + pIn1B = pIn1 + 2*numColsA; + + accR0 = vdupq_n_f32(0.0); + accI0 = vdupq_n_f32(0.0); + accR1 = vdupq_n_f32(0.0); + accI1 = vdupq_n_f32(0.0); + + /* Compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2; + + /* Matrix multiplication */ + while (colCnt > 0U) + { + /* Reading real part of complex matrix A */ + a0V = vld2q_f32(pIn1); // load & separate real/imag pSrcA (de-interleave 2) + a1V = vld2q_f32(pIn1B); // load & separate real/imag pSrcA (de-interleave 2) + + pIn1 += 8; + pIn1B += 8; + + tempR = vsetq_lane_f32(*pIn2,tempR,0); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,0); + pIn2 += 2 * numColsB; + + + tempR = vsetq_lane_f32(*pIn2,tempR,1); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,1); + pIn2 += 2 * numColsB; + + tempR = vsetq_lane_f32(*pIn2,tempR,2); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,2); + pIn2 += 2 * numColsB; + + tempR = vsetq_lane_f32(*pIn2,tempR,3); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,3); + pIn2 += 2 * numColsB; + + accR0 = vmlaq_f32(accR0,a0V.val[0],tempR); + accR0 = vmlsq_f32(accR0,a0V.val[1],tempI); + + accI0 = vmlaq_f32(accI0,a0V.val[1],tempR); + accI0 = vmlaq_f32(accI0,a0V.val[0],tempI); + + accR1 = vmlaq_f32(accR1,a1V.val[0],tempR); + accR1 = vmlsq_f32(accR1,a1V.val[1],tempI); + + accI1 = vmlaq_f32(accI1,a1V.val[1],tempR); + accI1 = vmlaq_f32(accI1,a1V.val[0],tempI); + + /* Decrement the loop count */ + colCnt--; + } + + accum = vpadd_f32(vget_low_f32(accR0), vget_high_f32(accR0)); + sumReal1 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(accI0), vget_high_f32(accI0)); + sumImag1 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(accR1), vget_high_f32(accR1)); + sumReal1B += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(accI1), vget_high_f32(accI1)); + sumImag1B += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA & 3; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + a1 = *pIn1; + a1B = *pIn1B; + + c1 = *pIn2; + + b1 = *(pIn1 + 1U); + b1B = *(pIn1B + 1U); + + d1 = *(pIn2 + 1U); + + sumReal1 += a1 * c1; + sumImag1 += b1 * c1; + + sumReal1B += a1B * c1; + sumImag1B += b1B * c1; + + pIn1 += 2U; + pIn1B += 2U; + pIn2 += 2 * numColsB; + + sumReal2 -= b1 * d1; + sumImag2 += a1 * d1; + + sumReal2B -= b1B * d1; + sumImag2B += a1B * d1; + + /* Decrement the loop counter */ + colCnt--; + } + + sumReal1 += sumReal2; + sumImag1 += sumImag2; + + sumReal1B += sumReal2B; + sumImag1B += sumImag2B; + + /* Store the result in the destination buffer */ + *px++ = sumReal1; + *px++ = sumImag1; + *pxB++ = sumReal1B; + *pxB++ = sumImag1B; + + /* Update the pointer pIn2 to point to the starting address of the next column */ + j++; + pIn2 = pSrcB->pData + 2U * j; + + /* Decrement the column loop counter */ + col--; + } + + /* Update the pointer pInA to point to the starting address of the next 2 row */ + i = i + 2*numColsB; + pInA = pInA + 4 * numColsA; + + /* Decrement the row loop counter */ + rowCnt--; + } + + rowCnt = row & 1; + while (rowCnt > 0U) + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + 2 * i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* Column loop */ + while (col > 0U) + { + /* Set the variable sum, that acts as accumulator, to zero */ + sumReal1 = 0.0f; + sumImag1 = 0.0f; + + sumReal2 = 0.0f; + sumImag2 = 0.0f; + + /* Initiate the pointer pIn1 to point to the starting address of the column being processed */ + pIn1 = pInA; + + accR0 = vdupq_n_f32(0.0); + accI0 = vdupq_n_f32(0.0); + + /* Compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2; + + /* Matrix multiplication */ + while (colCnt > 0U) + { + /* Reading real part of complex matrix A */ + a0V = vld2q_f32(pIn1); // load & separate real/imag pSrcA (de-interleave 2) + pIn1 += 8; + + tempR = vsetq_lane_f32(*pIn2,tempR,0); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,0); + pIn2 += 2 * numColsB; + + tempR = vsetq_lane_f32(*pIn2,tempR,1); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,1); + pIn2 += 2 * numColsB; + + tempR = vsetq_lane_f32(*pIn2,tempR,2); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,2); + pIn2 += 2 * numColsB; + + tempR = vsetq_lane_f32(*pIn2,tempR,3); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,3); + pIn2 += 2 * numColsB; + + accR0 = vmlaq_f32(accR0,a0V.val[0],tempR); + accR0 = vmlsq_f32(accR0,a0V.val[1],tempI); + + accI0 = vmlaq_f32(accI0,a0V.val[1],tempR); + accI0 = vmlaq_f32(accI0,a0V.val[0],tempI); + + /* Decrement the loop count */ + colCnt--; + } + + accum = vpadd_f32(vget_low_f32(accR0), vget_high_f32(accR0)); + sumReal1 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(accI0), vget_high_f32(accI0)); + sumImag1 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA & 3; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + a1 = *pIn1; + c1 = *pIn2; + + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + sumReal1 += a1 * c1; + sumImag1 += b1 * c1; + + pIn1 += 2U; + pIn2 += 2 * numColsB; + + sumReal2 -= b1 * d1; + sumImag2 += a1 * d1; + + /* Decrement the loop counter */ + colCnt--; + } + + sumReal1 += sumReal2; + sumImag1 += sumImag2; + + /* Store the result in the destination buffer */ + *px++ = sumReal1; + *px++ = sumImag1; + + /* Update the pointer pIn2 to point to the starting address of the next column */ + j++; + pIn2 = pSrcB->pData + 2U * j; + + /* Decrement the column loop counter */ + col--; + + } + + /* Update the pointer pInA to point to the starting address of the next row */ + i = i + numColsB; + pInA = pInA + 2 * numColsA; + + /* Decrement the row loop counter */ + rowCnt--; + + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* Output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + float32_t sumReal, sumImag; /* Accumulator */ + float32_t a1, b1, c1, d1; + uint32_t col, i = 0U, j, row = numRowsA, colCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t a0, b0, c0, d0; +#endif + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + 2 * i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sumReal = 0.0f; + sumImag = 0.0f; + + /* Initiate pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + + /* Reading real part of complex matrix A */ + a0 = *pIn1; + + /* Reading real part of complex matrix B */ + c0 = *pIn2; + + /* Reading imaginary part of complex matrix A */ + b0 = *(pIn1 + 1U); + + /* Reading imaginary part of complex matrix B */ + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a0 * c0; + sumImag += b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b0 * d0; + sumImag += a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + a0 = *(pIn1 ); + c0 = *(pIn2 ); + b0 = *(pIn1 + 1U); + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a0 * c0; + sumImag += b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b0 * d0; + sumImag += a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + /* Decrement loop count */ + colCnt--; + } + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = sumReal; + *px++ = sumImag; + + /* Update pointer pIn2 to point to starting address of next column */ + j++; + pIn2 = pSrcB->pData + 2U * j; + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + 2 * numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c new file mode 100644 index 00000000..5b9db9f1 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c @@ -0,0 +1,595 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mat_mult_q15.c + * Description: Q15 complex matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup CmplxMatrixMult + @{ + */ + +/** + @brief Q15 Complex matrix multiplication. + @param[in] pSrcA points to first input complex matrix structure + @param[in] pSrcB points to second input complex matrix structure + @param[out] pDst points to output complex matrix structure + @param[in] pScratch points to an array for storing intermediate results + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Conditions for optimum performance + Input, output and state buffers should be aligned by 32-bit + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. The inputs to the + multiplications are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then + truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MVE_ASRL_SAT16(acc, shift) ((sqrshrl_sat48(acc, -(32-shift)) >> 32) & 0xffffffff) + +arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch) +{ + q15_t const *pInA = (q15_t const *) pSrcA->pData; /* input data matrix pointer A of Q15 type */ + q15_t const *pInB = (q15_t const *) pSrcB->pData; /* input data matrix pointer B of Q15 type */ + q15_t const *pInB2; + q15_t *px; /* Temporary output data matrix pointer */ + uint32_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint32_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint32_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint32_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */ + uint32_t col, i = 0u, j, row = numRowsB; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + uint16x8_t vecOffs, vecColBOffs; + arm_status status; /* Status of matrix multiplication */ + (void)pScratch; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + vecColBOffs[0] = 0; + vecColBOffs[1] = 1; + vecColBOffs[2] = numColsB * CMPLX_DIM; + vecColBOffs[3] = (numColsB * CMPLX_DIM) + 1; + vecColBOffs[4] = 2 * numColsB * CMPLX_DIM; + vecColBOffs[5] = 2 * (numColsB * CMPLX_DIM) + 1; + vecColBOffs[6] = 3 * numColsB * CMPLX_DIM; + vecColBOffs[7] = 3 * (numColsB * CMPLX_DIM) + 1; + + /* + * Reset the variables for the usage in the following multiplication process + */ + i = 0; + row = numRowsA; + px = pDst->pData; + + /* + * The following loop performs the dot-product of each row in pSrcA with each column in pSrcB + */ + + /* + * row loop + */ + while (row > 0u) + { + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB >> 1; + j = 0; + /* + * column loop + */ + while (col > 0u) + { + q15_t const *pSrcAVec; + //, *pSrcBVec, *pSrcB2Vec; + q15x8_t vecA, vecB, vecB2; + q63_t acc0, acc1, acc2, acc3; + + /* + * Initiate the pointer pIn1 to point to the starting address of the column being processed + */ + pInA = pSrcA->pData + i; + pInB = pSrcB->pData + j; + pInB2 = pInB + CMPLX_DIM; + + j += 2 * CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + + /* + * Initiate the pointers + * - current Matrix A rows + * - 2 x consecutive Matrix B' rows (j increment is 2 x numRowsB) + */ + pSrcAVec = (q15_t const *) pInA; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + acc3 = 0LL; + + vecOffs = vecColBOffs; + + + blkCnt = (numColsA * CMPLX_DIM) >> 3; + while (blkCnt > 0U) + { + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + vecB = vldrhq_gather_shifted_offset(pInB, vecOffs); + + acc0 = vmlsldavaq_s16(acc0, vecA, vecB); + acc1 = vmlaldavaxq_s16(acc1, vecA, vecB); + vecB2 = vldrhq_gather_shifted_offset(pInB2, vecOffs); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vaddq_n_u16(vecOffs, (uint16_t) (numColsB * 4 * CMPLX_DIM)); + + acc2 = vmlsldavaq_s16(acc2, vecA, vecB2); + acc3 = vmlaldavaxq_s16(acc3, vecA, vecB2); + + blkCnt--; + } + + /* + * tail + */ + blkCnt = (numColsA * CMPLX_DIM) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecB = vldrhq_gather_shifted_offset(pInB, vecOffs); + + vecA = vldrhq_z_s16(pSrcAVec, p0); + + acc0 = vmlsldavaq_s16(acc0, vecA, vecB); + acc1 = vmlaldavaxq_s16(acc1, vecA, vecB); + vecB2 = vldrhq_gather_shifted_offset(pInB2, vecOffs); + + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vaddq_n_u16(vecOffs, (uint16_t) (numColsB * 4 * CMPLX_DIM)); + + acc2 = vmlsldavaq_s16(acc2, vecA, vecB2); + acc3 = vmlaldavaxq_s16(acc3, vecA, vecB2); + + } + /* + * Convert to 1.15, Store the results (1 x 2 block) in the destination buffer + */ + *px++ = (q15_t)MVE_ASRL_SAT16(acc0, 15); + *px++ = (q15_t)MVE_ASRL_SAT16(acc1, 15); + *px++ = (q15_t)MVE_ASRL_SAT16(acc2, 15); + *px++ = (q15_t)MVE_ASRL_SAT16(acc3, 15); + } + + col = numColsB & 1; + /* + * column loop + */ + while (col > 0u) + { + + q15_t const *pSrcAVec; + //, *pSrcBVec, *pSrcB2Vec; + q15x8_t vecA, vecB; + q63_t acc0, acc1; + + /* + * Initiate the pointer pIn1 to point to the starting address of the column being processed + */ + pInA = pSrcA->pData + i; + pInB = pSrcB->pData + j; + + j += CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + + /* + * Initiate the pointers + * - current Matrix A rows + * - 2 x consecutive Matrix B' rows (j increment is 2 x numRowsB) + */ + pSrcAVec = (q15_t const *) pInA; + + acc0 = 0LL; + acc1 = 0LL; + + + vecOffs = vecColBOffs; + + + + blkCnt = (numColsA * CMPLX_DIM) >> 3; + while (blkCnt > 0U) + { + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + vecB = vldrhq_gather_shifted_offset(pInB, vecOffs); + + acc0 = vmlsldavaq_s16(acc0, vecA, vecB); + acc1 = vmlaldavaxq_s16(acc1, vecA, vecB); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vaddq_n_u16(vecOffs, (uint16_t) (numColsB * 4 * CMPLX_DIM)); + + blkCnt--; + } + + /* + * tail + */ + blkCnt = (numColsA * CMPLX_DIM) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecB = vldrhq_gather_shifted_offset(pInB, vecOffs); + vecA = vldrhq_z_s16(pSrcAVec, p0); + + acc0 = vmlsldavaq_s16(acc0, vecA, vecB); + acc1 = vmlaldavaxq_s16(acc1, vecA, vecB); + + } + /* + * Convert to 1.15, Store the results (1 x 2 block) in the destination buffer + */ + *px++ = (q15_t)MVE_ASRL_SAT16(acc0, 15); + *px++ = (q15_t)MVE_ASRL_SAT16(acc1, 15); + + } + + i = i + numColsA * CMPLX_DIM; + + /* + * Decrement the row loop counter + */ + row--; + } + + + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch) +{ + q15_t *pSrcBT = pScratch; /* input data matrix pointer for transpose */ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q15 type */ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q15 type */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint16_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */ + q63_t sumReal, sumImag; /* accumulator */ + uint32_t col, i = 0U, row = numRowsB, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#if defined (ARM_MATH_DSP) + q31_t prod1, prod2; + q31_t pSourceA, pSourceB; +#else + q15_t a, b, c, d; +#endif /* #if defined (ARM_MATH_DSP) */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose */ + do + { + /* The pointer px is set to starting address of column being processed */ + px = pSrcBT + i; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and exchange the columns with row elements */ + col = numColsB >> 2; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + a second loop below computes the remaining 1 to 3 samples. */ + while (col > 0U) + { + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Decrement column loop counter */ + col--; + } + + /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + col = numColsB % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + col = numColsB; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Decrement column loop counter */ + col--; + } + + i = i + 2U; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Reset variables for usage in following multiplication process */ + row = numRowsA; + i = 0U; + px = pDst->pData; + + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of transposed pSrcB data */ + pInB = pSrcBT; + + /* column loop */ + do + { + /* Set variable sum, that acts as accumulator, to zero */ + sumReal = 0; + sumImag = 0; + + /* Initiate pointer pInA to point to starting address of column being processed */ + pInA = pSrcA->pData + i * 2; + + /* Apply loop unrolling and compute 2 MACs simultaneously. */ + colCnt = numColsA >> 1U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + +#if defined (ARM_MATH_DSP) + + /* read real and imag values from pSrcA and pSrcB buffer */ + pSourceA = read_q15x2_ia (&pInA); + pSourceB = read_q15x2_ia (&pInB); + + /* Multiply and Accumlates */ +#ifdef ARM_MATH_BIG_ENDIAN + prod1 = -__SMUSD(pSourceA, pSourceB); +#else + prod1 = __SMUSD(pSourceA, pSourceB); +#endif + prod2 = __SMUADX(pSourceA, pSourceB); + sumReal += (q63_t) prod1; + sumImag += (q63_t) prod2; + + /* read real and imag values from pSrcA and pSrcB buffer */ + pSourceA = read_q15x2_ia (&pInA); + pSourceB = read_q15x2_ia (&pInB); + + /* Multiply and Accumlates */ +#ifdef ARM_MATH_BIG_ENDIAN + prod1 = -__SMUSD(pSourceA, pSourceB); +#else + prod1 = __SMUSD(pSourceA, pSourceB); +#endif + prod2 = __SMUADX(pSourceA, pSourceB); + sumReal += (q63_t) prod1; + sumImag += (q63_t) prod2; + +#else /* #if defined (ARM_MATH_DSP) */ + + /* read real and imag values from pSrcA buffer */ + a = *pInA; + b = *(pInA + 1U); + /* read real and imag values from pSrcB buffer */ + c = *pInB; + d = *(pInB + 1U); + + /* Multiply and Accumlates */ + sumReal += (q31_t) a *c; + sumImag += (q31_t) a *d; + sumReal -= (q31_t) b *d; + sumImag += (q31_t) b *c; + + /* read next real and imag values from pSrcA buffer */ + a = *(pInA + 2U); + b = *(pInA + 3U); + /* read next real and imag values from pSrcB buffer */ + c = *(pInB + 2U); + d = *(pInB + 3U); + + /* update pointer */ + pInA += 4U; + + /* Multiply and Accumlates */ + sumReal += (q31_t) a * c; + sumImag += (q31_t) a * d; + sumReal -= (q31_t) b * d; + sumImag += (q31_t) b * c; + /* update pointer */ + pInB += 4U; + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + colCnt--; + } + + /* process odd column samples */ + if ((numColsA & 0x1U) > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + +#if defined (ARM_MATH_DSP) + /* read real and imag values from pSrcA and pSrcB buffer */ + pSourceA = read_q15x2_ia (&pInA); + pSourceB = read_q15x2_ia (&pInB); + + /* Multiply and Accumlates */ +#ifdef ARM_MATH_BIG_ENDIAN + prod1 = -__SMUSD(pSourceA, pSourceB); +#else + prod1 = __SMUSD(pSourceA, pSourceB); +#endif + prod2 = __SMUADX(pSourceA, pSourceB); + sumReal += (q63_t) prod1; + sumImag += (q63_t) prod2; + +#else /* #if defined (ARM_MATH_DSP) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + a = *pInA++; + b = *pInA++; + c = *pInB++; + d = *pInB++; + + /* Multiply and Accumlates */ + sumReal += (q31_t) a * c; + sumImag += (q31_t) a * d; + sumReal -= (q31_t) b * d; + sumImag += (q31_t) b * c; + +#endif /* #if defined (ARM_MATH_DSP) */ + + } + + /* Saturate and store result in destination buffer */ + *px++ = (q15_t) (__SSAT(sumReal >> 15, 16)); + *px++ = (q15_t) (__SSAT(sumImag >> 15, 16)); + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + i = i + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c new file mode 100644 index 00000000..ee784a6b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c @@ -0,0 +1,1061 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_mult_q31.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup CmplxMatrixMult + @{ + */ + +/** + @brief Q31 Complex matrix multiplication. + @param[in] pSrcA points to first input complex matrix structure + @param[in] pSrcB points to second input complex matrix structure + @param[out] pDst points to output complex matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. There is no saturation + on intermediate additions. Thus, if the accumulator overflows it wraps around and + distorts the result. The input signals should be scaled down to avoid intermediate + overflows. The input is thus scaled down by log2(numColsA) bits + to avoid overflows, as a total of numColsA additions are performed internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +#define MATRIX_DIM2 2 +#define MATRIX_DIM3 3 +#define MATRIX_DIM4 4 + +__STATIC_INLINE arm_status arm_mat_cmplx_mult_q31_2x2_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t const *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs0; + q31_t const *pInA0 = pInA; + q31_t const *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM2; + q63_t acc0, acc1, acc2, acc3; + q31x4_t vecB, vecA; + + static const uint32_t offsetB0[4] = { + 0, 1, + MATRIX_DIM2 * CMPLX_DIM, MATRIX_DIM2 * CMPLX_DIM + 1 + }; + + vecColBOffs0 = vldrwq_u32(offsetB0); + + pInB = (q31_t const *) pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 1] = (q31_t) asrl(acc3, 31); + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + pOut += CMPLX_DIM; + + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 1] = (q31_t) asrl(acc3, 31); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_cmplx_mult_q31_3x3_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t const *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs0, vecColBOffs1; + q31_t const *pInA0 = pInA; + q31_t const *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM3; + q31_t const *pInA2 = pInA1 + CMPLX_DIM * MATRIX_DIM3; + q63_t acc0, acc1, acc2, acc3; + q31x4_t vecB, vecB1, vecA; + /* + * enable predication to disable upper half complex vector element + */ + mve_pred16_t p0 = vctp32q(CMPLX_DIM); + + static const uint32_t offsetB0[4] = { + 0, 1, + MATRIX_DIM3 * CMPLX_DIM, MATRIX_DIM3 * CMPLX_DIM + 1 + }; + static const uint32_t offsetB1[4] = { + 2 * MATRIX_DIM3 * CMPLX_DIM, 2 * MATRIX_DIM3 * CMPLX_DIM + 1, + INACTIVELANE, INACTIVELANE + }; + + vecColBOffs0 = vldrwq_u32(offsetB0); + vecColBOffs1 = vldrwq_u32(offsetB1); + + pInB = (q31_t const *) pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecB1 = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_z_s32(&pInA0[4], p0); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_z_s32(&pInA1[4], p0); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc3, 31); + + vecA = vldrwq_s32(pInA2); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_z_s32(&pInA2[4], p0); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc0, 31); + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc1, 31); + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecB1 = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_z_s32(&pInA0[4], p0); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_z_s32(&pInA1[4], p0); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc3, 31); + + vecA = vldrwq_s32(pInA2); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_z_s32(&pInA2[4], p0); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc0, 31); + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc1, 31); + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecB1 = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_z_s32(&pInA0[4], p0); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_z_s32(&pInA1[4], p0); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc3, 31); + + vecA = vldrwq_s32(pInA2); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_z_s32(&pInA2[4], p0); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc0, 31); + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc1, 31); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_cmplx_mult_q31_4x4_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t const *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs0, vecColBOffs1; + q31_t const *pInA0 = pInA; + q31_t const *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM4; + q31_t const *pInA2 = pInA1 + CMPLX_DIM * MATRIX_DIM4; + q31_t const *pInA3 = pInA2 + CMPLX_DIM * MATRIX_DIM4; + q63_t acc0, acc1, acc2, acc3; + q31x4_t vecB, vecB1, vecA; + + static const uint32_t offsetB0[4] = { + 0, 1, + MATRIX_DIM4 * CMPLX_DIM, MATRIX_DIM4 * CMPLX_DIM + 1 + }; + static const uint32_t offsetB1[4] = { + 2 * MATRIX_DIM4 * CMPLX_DIM, 2 * MATRIX_DIM4 * CMPLX_DIM + 1, + 3 * MATRIX_DIM4 * CMPLX_DIM, 3 * MATRIX_DIM4 * CMPLX_DIM + 1 + }; + + vecColBOffs0 = vldrwq_u32(offsetB0); + vecColBOffs1 = vldrwq_u32(offsetB1); + + pInB = (q31_t const *) pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecB1 = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA0[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA1[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + + vecA = vldrwq_s32(pInA2); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA3); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA2[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA3[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecB1 = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA0[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA1[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + + vecA = vldrwq_s32(pInA2); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA3); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA2[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA3[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + pOut += CMPLX_DIM; + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecB1 = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA0[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA1[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + + vecA = vldrwq_s32(pInA2); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA3); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA2[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA3[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecB1 = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA0[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA1[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + + vecA = vldrwq_s32(pInA2); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA3); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA2[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA3[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t const *pInB = (q31_t const *) pSrcB->pData; /* input data matrix pointer B */ + q31_t const *pInA = (q31_t const *) pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint16_t col, i = 0U, row = numRowsA; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + uint32x4_t vecOffs, vecColBOffs; + uint32_t blkCnt, rowCnt; /* loop counters */ + + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols)) + { + + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* + * small squared matrix specialized routines + */ + if (numRowsA == numColsB && numColsB == numColsA) + { + if (numRowsA == 1) + { + q63_t sumReal = (q63_t) pInA[0] * pInB[0]; + sumReal -= (q63_t) pInA[1] * pInB[1]; + + q63_t sumImag = (q63_t) pInA[0] * pInB[1]; + sumImag += (q63_t) pInA[1] * pInB[0]; + + /* Store result in destination buffer */ + pOut[0] = (q31_t) clip_q63_to_q31(sumReal >> 31); + pOut[1] = (q31_t) clip_q63_to_q31(sumImag >> 31); + return (ARM_MATH_SUCCESS); + } + else if (numRowsA == 2) + return arm_mat_cmplx_mult_q31_2x2_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 3) + return arm_mat_cmplx_mult_q31_3x3_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 4) + return arm_mat_cmplx_mult_q31_4x4_mve(pSrcA, pSrcB, pDst); + } + + vecColBOffs[0] = 0; + vecColBOffs[1] = 1; + vecColBOffs[2] = numColsB * CMPLX_DIM; + vecColBOffs[3] = (numColsB * CMPLX_DIM) + 1; + + /* + * The following loop performs the dot-product of each row in pSrcA with each column in pSrcB + */ + + /* + * row loop + */ + rowCnt = row >> 1; + while (rowCnt > 0u) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i * CMPLX_DIM; + i = i + 2 * numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (q31_t const *) pSrcB->pData; + /* + * column loop + */ + while (col > 0u) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + q31_t const *pSrcA0Vec, *pSrcA1Vec; + q31_t const *pInA0 = pInA; + q31_t const *pInA1 = pInA0 + numColsA * CMPLX_DIM; + q63_t acc0, acc1, acc2, acc3; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + acc3 = 0LL; + + pSrcA0Vec = (q31_t const *) pInA0; + pSrcA1Vec = (q31_t const *) pInA1; + + + vecOffs = vecColBOffs; + + /* + * process 1 x 2 block output + */ + blkCnt = (numColsA * CMPLX_DIM) >> 2; + while (blkCnt > 0U) + { + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset(pInB, vecOffs); + /* + * move Matrix B read offsets, 2 rows down + */ + vecOffs = vecOffs + (uint32_t) (numColsB * 2 * CMPLX_DIM); + + + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vmlsldavaq(acc0, vecA, vecB); + acc1 = vmlaldavaxq(acc1, vecA, vecB); + + + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + + acc2 = vmlsldavaq(acc2, vecA, vecB); + acc3 = vmlaldavaxq(acc3, vecA, vecB); + + + blkCnt--; + } + + + /* + * tail + */ + blkCnt = (numColsA * CMPLX_DIM) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecOffs, p0); + + /* + * move Matrix B read offsets, 2 rows down + */ + vecOffs = vecOffs + (uint32_t) (numColsB * 2 * CMPLX_DIM); + + + vecA = vld1q(pSrcA0Vec); + acc0 = vmlsldavaq(acc0, vecA, vecB); + acc1 = vmlaldavaxq(acc1, vecA, vecB); + vecA = vld1q(pSrcA1Vec); + acc2 = vmlsldavaq(acc2, vecA, vecB); + acc3 = vmlaldavaxq(acc3, vecA, vecB); + + + } + + px[0 * CMPLX_DIM * numColsB + 0] = (q31_t) clip_q63_to_q31(acc0 >> 31); + px[0 * CMPLX_DIM * numColsB + 1] = (q31_t) clip_q63_to_q31(acc1 >> 31); + px[1 * CMPLX_DIM * numColsB + 0] = (q31_t) clip_q63_to_q31(acc2 >> 31); + px[1 * CMPLX_DIM * numColsB + 1] = (q31_t) clip_q63_to_q31(acc3 >> 31); + px += CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (q31_t const *) pSrcB->pData + (numColsB - col) * CMPLX_DIM; + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += (numColsA * 2) * CMPLX_DIM; + /* + * Decrement the row loop counter + */ + rowCnt --; + + } + + rowCnt = row & 1; + while (rowCnt > 0u) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i * CMPLX_DIM; + i = i + numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (q31_t const *) pSrcB->pData; + /* + * column loop + */ + while (col > 0u) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + q31_t const *pSrcA0Vec; + q31_t const *pInA0 = pInA; + q63_t acc0,acc1; + + acc0 = 0LL; + acc1 = 0LL; + + pSrcA0Vec = (q31_t const *) pInA0; + + vecOffs = vecColBOffs; + + /* + * process 1 x 2 block output + */ + blkCnt = (numColsA * CMPLX_DIM) >> 2; + while (blkCnt > 0U) + { + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset(pInB, vecOffs); + /* + * move Matrix B read offsets, 2 rows down + */ + vecOffs = vecOffs + (uint32_t) (numColsB * 2 * CMPLX_DIM); + + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vmlsldavaq(acc0, vecA, vecB); + acc1 = vmlaldavaxq(acc1, vecA, vecB); + + + blkCnt--; + } + + + /* + * tail + */ + blkCnt = (numColsA * CMPLX_DIM) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecOffs, p0); + + /* + * move Matrix B read offsets, 2 rows down + */ + vecOffs = vecOffs + (uint32_t) (numColsB * 2 * CMPLX_DIM); + + vecA = vld1q(pSrcA0Vec); + + + acc0 = vmlsldavaq(acc0, vecA, vecB); + acc1 = vmlaldavaxq(acc1, vecA, vecB); + + + } + + px[0] = (q31_t) clip_q63_to_q31(acc0 >> 31); + px[1] = (q31_t) clip_q63_to_q31(acc1 >> 31); + + + px += CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (q31_t const *) pSrcB->pData + (numColsB - col) * CMPLX_DIM; + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += numColsA * CMPLX_DIM; + rowCnt--; + } + + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* Output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + q63_t sumReal, sumImag; /* Accumulator */ + q31_t a1, b1, c1, d1; + uint32_t col, i = 0U, j, row = numRowsA, colCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t a0, b0, c0, d0; +#endif + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + 2 * i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sumReal = 0.0; + sumImag = 0.0; + + /* Initiate pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + + /* Reading real part of complex matrix A */ + a0 = *pIn1; + + /* Reading real part of complex matrix B */ + c0 = *pIn2; + + /* Reading imaginary part of complex matrix A */ + b0 = *(pIn1 + 1U); + + /* Reading imaginary part of complex matrix B */ + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a0 * c0; + sumImag += (q63_t) b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b0 * d0; + sumImag += (q63_t) a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a1 * c1; + sumImag += (q63_t) b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b1 * d1; + sumImag += (q63_t) a1 * d1; + + a0 = *(pIn1 ); + c0 = *(pIn2 ); + b0 = *(pIn1 + 1U); + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a0 * c0; + sumImag += (q63_t) b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b0 * d0; + sumImag += (q63_t) a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a1 * c1; + sumImag += (q63_t) b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b1 * d1; + sumImag += (q63_t) a1 * d1; + + /* Decrement loop count */ + colCnt--; + } + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a1 * c1; + sumImag += (q63_t) b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b1 * d1; + sumImag += (q63_t) a1 * d1; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = (q31_t) clip_q63_to_q31(sumReal >> 31); + *px++ = (q31_t) clip_q63_to_q31(sumImag >> 31); + + /* Update pointer pIn2 to point to starting address of next column */ + j++; + pIn2 = pSrcB->pData + 2U * j; + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + 2 * numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_f16.c new file mode 100644 index 00000000..5eda8c3c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_f16.c @@ -0,0 +1,131 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_trans_f16.c + * Description: Floating-point complex matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixComplexTrans + @{ + */ + +/** + @brief Floating-point matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +arm_status arm_mat_cmplx_trans_f16(const arm_matrix_instance_f16 * pSrc, arm_matrix_instance_f16 * pDst) +{ + return arm_mat_cmplx_trans_16bit(pSrc->numRows, pSrc->numCols, (uint16_t *) pSrc->pData, + pDst->numRows, pDst->numCols, (uint16_t *) pDst->pData); +} + +#else +arm_status arm_mat_cmplx_trans_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pIn = pSrc->pData; /* input data matrix pointer */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + float16_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nColumns = pSrc->numCols; /* number of columns */ + uint16_t col, i = 0U, row = nRows; /* loop counters */ + arm_status status; /* status of matrix transpose */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* The pointer px is set to starting address of the column being processed */ + px = pOut + CMPLX_DIM * i; + + /* Initialize column loop counter */ + col = nColumns; + + while (col > 0U) + { + /* Read and store the input element in the destination */ + px[0] = *pIn++; // real + px[1] = *pIn++; // imag + + /* Update the pointer px to point to the next row of the transposed matrix */ + px += CMPLX_DIM * nRows; + + /* Decrement the column loop counter */ + col--; + } + i++; + + /* Decrement the row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixTrans group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_f32.c new file mode 100644 index 00000000..222f349e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_f32.c @@ -0,0 +1,133 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_trans_f32.c + * Description: Floating-point complex matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixComplexTrans Complex Matrix Transpose + + Tranposes a complex matrix. + + Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix. + \image html MatrixTranspose.gif "Transpose of a 3 x 3 matrix" + */ + +/** + @addtogroup MatrixComplexTrans + @{ + */ + +/** + @brief Floating-point matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +arm_status arm_mat_cmplx_trans_f32(const arm_matrix_instance_f32 * pSrc, arm_matrix_instance_f32 * pDst) +{ + return arm_mat_cmplx_trans_32bit(pSrc->numRows, pSrc->numCols, (uint32_t *) pSrc->pData, + pDst->numRows, pDst->numCols, (uint32_t *) pDst->pData); +} + +#else +arm_status arm_mat_cmplx_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nColumns = pSrc->numCols; /* number of columns */ + uint16_t col, i = 0U, row = nRows; /* loop counters */ + arm_status status; /* status of matrix transpose */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* The pointer px is set to starting address of the column being processed */ + px = pOut + CMPLX_DIM * i; + + /* Initialize column loop counter */ + col = nColumns; + + while (col > 0U) + { + /* Read and store the input element in the destination */ + px[0] = *pIn++; // real + px[1] = *pIn++; // imag + + /* Update the pointer px to point to the next row of the transposed matrix */ + px += CMPLX_DIM * nRows; + + /* Decrement the column loop counter */ + col--; + } + i++; + + /* Decrement the row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixTrans group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_q15.c new file mode 100644 index 00000000..8a3724ee --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_q15.c @@ -0,0 +1,124 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_trans_q31.c + * Description: Q15 complex matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixComplexTrans + @{ + */ + +/** + @brief Q15 complex matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +arm_status arm_mat_cmplx_trans_q15(const arm_matrix_instance_q15 * pSrc, arm_matrix_instance_q15 * pDst) +{ + return arm_mat_cmplx_trans_16bit(pSrc->numRows, pSrc->numCols, (uint16_t *) pSrc->pData, + pDst->numRows, pDst->numCols, (uint16_t *) pDst->pData); +} + + +#else +arm_status arm_mat_cmplx_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pSrcA = pSrc->pData; /* input data matrix pointer */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of nRows */ + uint16_t nColumns = pSrc->numCols; /* number of nColumns */ + uint16_t col, row = nRows, i = 0U; /* row and column loop counters */ + arm_status status; /* status of matrix transpose */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* The pointer pOut is set to starting address of the column being processed */ + pOut = pDst->pData + CMPLX_DIM * i; + + /* Initialize column loop counter */ + col = nColumns; + + while (col > 0U) + { + /* Read and store the input element in the destination */ + pOut[0] = *pSrcA++; //real + pOut[1] = *pSrcA++; //imag + + /* Update the pointer pOut to point to the next row of the transposed matrix */ + pOut += CMPLX_DIM *nRows; + + /* Decrement the column loop counter */ + col--; + } + + i++; + + /* Decrement the row loop counter */ + row--; + + } while (row > 0U); + + /* set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + * @} end of MatrixTrans group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_q31.c new file mode 100644 index 00000000..a8612a30 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_q31.c @@ -0,0 +1,129 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_trans_q31.c + * Description: Q31 complex matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + + + +/** + @addtogroup MatrixComplexTrans + @{ + */ + +/** + @brief Q31 complex matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + +arm_status arm_mat_cmplx_trans_q31(const arm_matrix_instance_q31 * pSrc, arm_matrix_instance_q31 * pDst) +{ + return arm_mat_cmplx_trans_32bit(pSrc->numRows, pSrc->numCols, (uint32_t *) pSrc->pData, + pDst->numRows, pDst->numCols, (uint32_t *) pDst->pData); +} + + +#else +arm_status arm_mat_cmplx_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pIn = pSrc->pData; /* input data matrix pointer */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of nRows */ + uint16_t nColumns = pSrc->numCols; /* number of nColumns */ + uint16_t col, i = 0U, row = nRows; /* loop counters */ + arm_status status; /* status of matrix transpose */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* The pointer px is set to starting address of the column being processed */ + px = pOut + CMPLX_DIM * i; + + /* Initialize column loop counter */ + col = nColumns; + + while (col > 0U) + { + /* Read and store the input element in the destination */ + px[0] = *pIn++; // real + px[1] = *pIn++; // imag + + /* Update the pointer px to point to the next row of the transposed matrix */ + px += CMPLX_DIM * nRows; + + /* Decrement the column loop counter */ + col--; + } + + i++; + + /* Decrement the row loop counter */ + row--; + + } + while (row > 0U); /* row loop end */ + + /* set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + * @} end of MatrixTrans group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f16.c new file mode 100644 index 00000000..6a48102d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f16.c @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_init_f16.c + * Description: Floating-point matrix initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInit + @{ + */ + +/** + @brief Floating-point matrix initialization. + @param[in,out] S points to an instance of the floating-point matrix structure + @param[in] nRows number of rows in the matrix + @param[in] nColumns number of columns in the matrix + @param[in] pData points to the matrix data array + @return none + */ + +void arm_mat_init_f16( + arm_matrix_instance_f16 * S, + uint16_t nRows, + uint16_t nColumns, + float16_t * pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +/** + @} end of MatrixInit group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c new file mode 100644 index 00000000..d2a52013 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c @@ -0,0 +1,76 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_init_f32.c + * Description: Floating-point matrix initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixInit Matrix Initialization + + Initializes the underlying matrix data structure. + The functions set the numRows, + numCols, and pData fields + of the matrix data structure. + */ + +/** + @addtogroup MatrixInit + @{ + */ + +/** + @brief Floating-point matrix initialization. + @param[in,out] S points to an instance of the floating-point matrix structure + @param[in] nRows number of rows in the matrix + @param[in] nColumns number of columns in the matrix + @param[in] pData points to the matrix data array + @return none + */ + +void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +/** + @} end of MatrixInit group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c new file mode 100644 index 00000000..33942b50 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c @@ -0,0 +1,67 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_init_q15.c + * Description: Q15 matrix initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixInit + @{ + */ + +/** + @brief Q15 matrix initialization. + @param[in,out] S points to an instance of the floating-point matrix structure + @param[in] nRows number of rows in the matrix + @param[in] nColumns number of columns in the matrix + @param[in] pData points to the matrix data array + @return none + */ + +void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +/** + @} end of MatrixInit group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c new file mode 100644 index 00000000..ab735d06 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_init_q31.c + * Description: Q31 matrix initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixInit Matrix Initialization + + */ + +/** + @addtogroup MatrixInit + @{ + */ + +/** + @brief Q31 matrix initialization. + @param[in,out] S points to an instance of the Q31 matrix structure + @param[in] nRows number of rows in the matrix + @param[in] nColumns number of columns in the matrix + @param[in] pData points to the matrix data array + @return none + */ + +void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +/** + @} end of MatrixInit group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f16.c new file mode 100644 index 00000000..90bc06d0 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f16.c @@ -0,0 +1,891 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_inverse_f16.c + * Description: Floating-point matrix inverse + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + +/** + @brief Floating-point matrix inverse. + @param[in] pSrc points to input matrix structure. The source matrix is modified by the function. + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_SINGULAR : Input matrix is found to be singular (non-invertible) + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_inverse_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pIn = pSrc->pData; /* input data matrix pointer */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + float16_t *pInT1, *pInT2; /* Temporary input data matrix pointer */ + float16_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */ + float16_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */ + + uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */ + uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */ + float16_t *pTmpA, *pTmpB; + + _Float16 in = 0.0f16; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, l; /* loop counters */ + arm_status status; /* status of matrix inverse */ + uint32_t blkCnt; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols) + || (pSrc->numRows != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ _ _ _ _ + * | | a11 a12 | | | 1 0 | | | X11 X12 | + * | | | | | | | = | | + * |_ |_ a21 a22 _| | |_0 1 _| _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, src). + * Therefore, the matrix to the right of the bar is our solution(dst matrix, dst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* + * Working pointer for destination matrix + */ + pOutT1 = pOut; + /* + * Loop over the number of rows + */ + rowCnt = numRows; + /* + * Making the destination matrix as identity matrix + */ + while (rowCnt > 0U) + { + /* + * Writing all zeroes in lower triangle of the destination matrix + */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0f16; + j--; + } + /* + * Writing all ones in the diagonal of the destination matrix + */ + *pOutT1++ = 1.0f16; + /* + * Writing all zeroes in upper triangle of the destination matrix + */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0f16; + j--; + } + /* + * Decrement the loop counter + */ + rowCnt--; + } + + /* + * Loop over the number of columns of the input matrix. + * All the elements in each column are processed by the row operations + */ + loopCnt = numCols; + /* + * Index modifier to navigate through the columns + */ + l = 0U; + while (loopCnt > 0U) + { + /* + * Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. + */ + + /* + * Working pointer for the input matrix that points + * * to the pivot element of the particular row + */ + pInT1 = pIn + (l * numCols); + /* + * Working pointer for the destination matrix that points + * * to the pivot element of the particular row + */ + pOutT1 = pOut + (l * numCols); + /* + * Temporary variable to hold the pivot value + */ + in = *pInT1; + + + /* + * Check if the pivot element is zero + */ + if ((_Float16)*pInT1 == 0.0f16) + { + /* + * Loop over the number rows present below + */ + for (i = 1U; i < numRows-l; i++) + { + /* + * Update the input and destination pointers + */ + pInT2 = pInT1 + (numCols * i); + pOutT2 = pOutT1 + (numCols * i); + /* + * Check if there is a non zero pivot element to + * * replace in the rows below + */ + if ((_Float16)*pInT2 != 0.0f16) + { + f16x8_t vecA, vecB; + /* + * Loop over number of columns + * * to the right of the pilot element + */ + pTmpA = pInT1; + pTmpB = pInT2; + blkCnt = (numCols - l) >> 3; + while (blkCnt > 0U) + { + + vecA = vldrhq_f16(pTmpA); + vecB = vldrhq_f16(pTmpB); + vstrhq_f16(pTmpB, vecA); + vstrhq_f16(pTmpA, vecB); + + pTmpA += 8; + pTmpB += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numCols - l) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecA = vldrhq_f16(pTmpA); + vecB = vldrhq_f16(pTmpB); + vstrhq_p_f16(pTmpB, vecA, p0); + vstrhq_p_f16(pTmpA, vecB, p0); + } + + pInT1 += numCols - l; + pInT2 += numCols - l; + pTmpA = pOutT1; + pTmpB = pOutT2; + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + + vecA = vldrhq_f16(pTmpA); + vecB = vldrhq_f16(pTmpB); + vstrhq_f16(pTmpB, vecA); + vstrhq_f16(pTmpA, vecB); + pTmpA += 8; + pTmpB += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecA = vldrhq_f16(pTmpA); + vecB = vldrhq_f16(pTmpB); + vstrhq_p_f16(pTmpB, vecA, p0); + vstrhq_p_f16(pTmpA, vecB, p0); + } + + pOutT1 += numCols; + pOutT2 += numCols; + /* + * Flag to indicate whether exchange is done or not + */ + flag = 1U; + + /* + * Break after exchange is done + */ + break; + } + + } + } + + /* + * Update the status if the matrix is singular + */ + if ((flag != 1U) && (in == 0.0f16)) + { + return ARM_MATH_SINGULAR; + } + + /* + * Points to the pivot row of input and destination matrices + */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* + * Temporary pointers to the pivot row pointers + */ + pInT1 = pPivotRowIn; + pOutT1 = pPivotRowDst; + + /* + * Pivot element of the row + */ + in = *(pIn + (l * numCols)); + + pTmpA = pInT1; + + f16x8_t invIn = vdupq_n_f16(1.0f16 / in); + + blkCnt = (numCols - l) >> 3; + f16x8_t vecA; + while (blkCnt > 0U) + { + *(f16x8_t *) pTmpA = *(f16x8_t *) pTmpA * invIn; + pTmpA += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = (numCols - l) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + + vecA = vldrhq_f16(pTmpA); + vecA = vecA * invIn; + vstrhq_p_f16(pTmpA, vecA, p0); + } + + pInT1 += numCols - l; + /* + * Loop over number of columns + * * to the right of the pilot element + */ + + pTmpA = pOutT1; + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + *(f16x8_t *) pTmpA = *(f16x8_t *) pTmpA *invIn; + pTmpA += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecA = vldrhq_f16(pTmpA); + vecA = vecA * invIn; + vstrhq_p_f16(pTmpA, vecA, p0); + } + + pOutT1 += numCols; + + /* + * Replace the rows with the sum of that row and a multiple of row i + * * so that each new element in column i above row i is zero. + */ + + /* + * Temporary pointers for input and destination matrices + */ + pInT1 = pIn; + pOutT1 = pOut; + + for (i = 0U; i < numRows; i++) + { + /* + * Check for the pivot element + */ + if (i == l) + { + /* + * If the processing element is the pivot element, + * only the columns to the right are to be processed + */ + pInT1 += numCols - l; + pOutT1 += numCols; + } + else + { + /* + * Element of the reference row + */ + + /* + * Working pointers for input and destination pivot rows + */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + /* + * Loop over the number of columns to the right of the pivot element, + * to replace the elements in the input matrix + */ + + in = *pInT1; + f16x8_t tmpV = vdupq_n_f16(in); + + blkCnt = (numCols - l) >> 3; + while (blkCnt > 0U) + { + f16x8_t vec1, vec2; + /* + * Replace the element by the sum of that row + * and a multiple of the reference row + */ + vec1 = vldrhq_f16(pInT1); + vec2 = vldrhq_f16(pPRT_in); + vec1 = vfmsq_f16(vec1, tmpV, vec2); + vstrhq_f16(pInT1, vec1); + pPRT_in += 8; + pInT1 += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numCols - l) & 7; + if (blkCnt > 0U) + { + f16x8_t vec1, vec2; + mve_pred16_t p0 = vctp16q(blkCnt); + + vec1 = vldrhq_f16(pInT1); + vec2 = vldrhq_f16(pPRT_in); + vec1 = vfmsq_f16(vec1, tmpV, vec2); + vstrhq_p_f16(pInT1, vec1, p0); + pInT1 += blkCnt; + } + + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + f16x8_t vec1, vec2; + + /* + * Replace the element by the sum of that row + * and a multiple of the reference row + */ + vec1 = vldrhq_f16(pOutT1); + vec2 = vldrhq_f16(pPRT_pDst); + vec1 = vfmsq_f16(vec1, tmpV, vec2); + vstrhq_f16(pOutT1, vec1); + pPRT_pDst += 8; + pOutT1 += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + f16x8_t vec1, vec2; + mve_pred16_t p0 = vctp16q(blkCnt); + + vec1 = vldrhq_f16(pOutT1); + vec2 = vldrhq_f16(pPRT_pDst); + vec1 = vfmsq_f16(vec1, tmpV, vec2); + vstrhq_p_f16(pOutT1, vec1, p0); + + pInT2 += blkCnt; + pOutT1 += blkCnt; + } + } + /* + * Increment the temporary input pointer + */ + pInT1 = pInT1 + l; + } + /* + * Increment the input pointer + */ + pIn++; + /* + * Decrement the loop counter + */ + loopCnt--; + /* + * Increment the index modifier + */ + l++; + } + + /* + * Set status as ARM_MATH_SUCCESS + */ + status = ARM_MATH_SUCCESS; + + if ((flag != 1U) && (in == 0.0f16)) + { + pIn = pSrc->pData; + for (i = 0; i < numRows * numCols; i++) + { + if ((_Float16)pIn[i] != 0.0f16) + break; + } + + if (i == numRows * numCols) + status = ARM_MATH_SINGULAR; + } + } + /* Return to application */ + return (status); +} + +#else + +arm_status arm_mat_inverse_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pIn = pSrc->pData; /* input data matrix pointer */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + float16_t *pInT1, *pInT2; /* Temporary input data matrix pointer */ + float16_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */ + float16_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */ + uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */ + uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */ + + _Float16 Xchg, in = 0.0f16, in1; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, k,l; /* loop counters */ + arm_status status; /* status of matrix inverse */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ + * | a11 a12 | 1 0 | | X11 X12 | + * | | | = | | + * |_ a21 a22 | 0 1 _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc). + * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pOutT1 = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0f16; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0f16; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0f16; + j--; + } + + /* Decrement loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + loopCnt = numCols; + + /* Index modifier to navigate through the columns */ + l = 0U; + + while (loopCnt > 0U) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + /* Working pointer for the input matrix that points + * to the pivot element of the particular row */ + pInT1 = pIn + (l * numCols); + + /* Working pointer for the destination matrix that points + * to the pivot element of the particular row */ + pOutT1 = pOut + (l * numCols); + + /* Temporary variable to hold the pivot value */ + in = *pInT1; + + + /* Check if the pivot element is zero */ + if ((_Float16)*pInT1 == 0.0f16) + { + /* Loop over the number rows present below */ + + for (i = 1U; i < numRows-l; i++) + { + /* Update the input and destination pointers */ + pInT2 = pInT1 + (numCols * i); + pOutT2 = pOutT1 + (numCols * i); + + /* Check if there is a non zero pivot element to + * replace in the rows below */ + if ((_Float16)*pInT2 != 0.0f16) + { + /* Loop over number of columns + * to the right of the pilot element */ + j = numCols - l; + + while (j > 0U) + { + /* Exchange the row elements of the input matrix */ + Xchg = *pInT2; + *pInT2++ = *pInT1; + *pInT1++ = Xchg; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Exchange the row elements of the destination matrix */ + Xchg = *pOutT2; + *pOutT2++ = *pOutT1; + *pOutT1++ = Xchg; + + /* Decrement loop counter */ + j--; + } + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + /* Break after exchange is done */ + break; + } + + } + } + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (in == 0.0f16)) + { + return ARM_MATH_SINGULAR; + } + + /* Points to the pivot row of input and destination matrices */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* Temporary pointers to the pivot row pointers */ + pInT1 = pPivotRowIn; + pInT2 = pPivotRowDst; + + /* Pivot element of the row */ + in = *pPivotRowIn; + + /* Loop over number of columns + * to the right of the pilot element */ + j = (numCols - l); + + while (j > 0U) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + in1 = *pInT1; + *pInT1++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + in1 = *pInT2; + *pInT2++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + /* Temporary pointers for input and destination matrices */ + pInT1 = pIn; + pInT2 = pOut; + + /* index used to check for pivot element */ + i = 0U; + + /* Loop over number of rows */ + /* to be replaced by the sum of that row and a multiple of row i */ + k = numRows; + + while (k > 0U) + { + /* Check for the pivot element */ + if (i == l) + { + /* If the processing element is the pivot element, + only the columns to the right are to be processed */ + pInT1 += numCols - l; + + pInT2 += numCols; + } + else + { + /* Element of the reference row */ + in = *pInT1; + + /* Working pointers for input and destination pivot rows */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + + /* Loop over the number of columns to the right of the pivot element, + to replace the elements in the input matrix */ + j = (numCols - l); + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT1; + *pInT1++ = (_Float16)in1 - ((_Float16)in * (_Float16)*pPRT_in++); + + /* Decrement the loop counter */ + j--; + } + + /* Loop over the number of columns to + replace the elements in the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT2; + *pInT2++ = (_Float16)in1 - ((_Float16)in * (_Float16)*pPRT_pDst++); + + /* Decrement loop counter */ + j--; + } + + } + + /* Increment temporary input pointer */ + pInT1 = pInT1 + l; + + /* Decrement loop counter */ + k--; + + /* Increment pivot index */ + i++; + } + + /* Increment the input pointer */ + pIn++; + + /* Decrement the loop counter */ + loopCnt--; + + /* Increment the index modifier */ + l++; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + + if ((flag != 1U) && ((_Float16)in == 0.0f16)) + { + pIn = pSrc->pData; + for (i = 0; i < numRows * numCols; i++) + { + if ((_Float16)pIn[i] != 0.0f16) + break; + } + + if (i == numRows * numCols) + status = ARM_MATH_SINGULAR; + } + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixInv group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c new file mode 100644 index 00000000..b0ef7608 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c @@ -0,0 +1,1570 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_inverse_f32.c + * Description: Floating-point matrix inverse + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixInv Matrix Inverse + + Computes the inverse of a matrix. + + The inverse is defined only if the input matrix is square and non-singular (the determinant is non-zero). + The function checks that the input and output matrices are square and of the same size. + + Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix + inversion of floating-point matrices. + + @par Algorithm + The Gauss-Jordan method is used to find the inverse. + The algorithm performs a sequence of elementary row-operations until it + reduces the input matrix to an identity matrix. Applying the same sequence + of elementary row-operations to an identity matrix yields the inverse matrix. + If the input matrix is singular, then the algorithm terminates and returns error status + ARM_MATH_SINGULAR. + \image html MatrixInverse.gif "Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method" + */ + +/** + @addtogroup MatrixInv + @{ + */ + +/** + @brief Floating-point matrix inverse. + @param[in] pSrc points to input matrix structure. The source matrix is modified by the function. + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_SINGULAR : Input matrix is found to be singular (non-invertible) + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *pInT1, *pInT2; /* Temporary input data matrix pointer */ + float32_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */ + float32_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */ + + uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */ + uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */ + float32_t *pTmpA, *pTmpB; + + float32_t in = 0.0f; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, l; /* loop counters */ + arm_status status; /* status of matrix inverse */ + uint32_t blkCnt; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols) + || (pSrc->numRows != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ _ _ _ _ + * | | a11 a12 | | | 1 0 | | | X11 X12 | + * | | | | | | | = | | + * |_ |_ a21 a22 _| | |_0 1 _| _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, src). + * Therefore, the matrix to the right of the bar is our solution(dst matrix, dst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* + * Working pointer for destination matrix + */ + pOutT1 = pOut; + /* + * Loop over the number of rows + */ + rowCnt = numRows; + /* + * Making the destination matrix as identity matrix + */ + while (rowCnt > 0U) + { + /* + * Writing all zeroes in lower triangle of the destination matrix + */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + /* + * Writing all ones in the diagonal of the destination matrix + */ + *pOutT1++ = 1.0f; + /* + * Writing all zeroes in upper triangle of the destination matrix + */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + /* + * Decrement the loop counter + */ + rowCnt--; + } + + /* + * Loop over the number of columns of the input matrix. + * All the elements in each column are processed by the row operations + */ + loopCnt = numCols; + /* + * Index modifier to navigate through the columns + */ + l = 0U; + while (loopCnt > 0U) + { + /* + * Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. + */ + + /* + * Working pointer for the input matrix that points + * * to the pivot element of the particular row + */ + pInT1 = pIn + (l * numCols); + /* + * Working pointer for the destination matrix that points + * * to the pivot element of the particular row + */ + pOutT1 = pOut + (l * numCols); + /* + * Temporary variable to hold the pivot value + */ + in = *pInT1; + + + /* + * Check if the pivot element is zero + */ + if (*pInT1 == 0.0f) + { + /* + * Loop over the number rows present below + */ + for (i = 1U; i < numRows-l; i++) + { + /* + * Update the input and destination pointers + */ + pInT2 = pInT1 + (numCols * i); + pOutT2 = pOutT1 + (numCols * i); + /* + * Check if there is a non zero pivot element to + * * replace in the rows below + */ + if (*pInT2 != 0.0f) + { + f32x4_t vecA, vecB; + /* + * Loop over number of columns + * * to the right of the pilot element + */ + pTmpA = pInT1; + pTmpB = pInT2; + blkCnt = (numCols - l) >> 2; + while (blkCnt > 0U) + { + + vecA = vldrwq_f32(pTmpA); + vecB = vldrwq_f32(pTmpB); + vstrwq_f32(pTmpB, vecA); + vstrwq_f32(pTmpA, vecB); + + pTmpA += 4; + pTmpB += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numCols - l) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecA = vldrwq_f32(pTmpA); + vecB = vldrwq_f32(pTmpB); + vstrwq_p_f32(pTmpB, vecA, p0); + vstrwq_p_f32(pTmpA, vecB, p0); + } + + pInT1 += numCols - l; + pInT2 += numCols - l; + pTmpA = pOutT1; + pTmpB = pOutT2; + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + + vecA = vldrwq_f32(pTmpA); + vecB = vldrwq_f32(pTmpB); + vstrwq_f32(pTmpB, vecA); + vstrwq_f32(pTmpA, vecB); + pTmpA += 4; + pTmpB += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecA = vldrwq_f32(pTmpA); + vecB = vldrwq_f32(pTmpB); + vstrwq_p_f32(pTmpB, vecA, p0); + vstrwq_p_f32(pTmpA, vecB, p0); + } + + pOutT1 += numCols; + pOutT2 += numCols; + /* + * Flag to indicate whether exchange is done or not + */ + flag = 1U; + + /* + * Break after exchange is done + */ + break; + } + + } + } + + /* + * Update the status if the matrix is singular + */ + if ((flag != 1U) && (in == 0.0f)) + { + return ARM_MATH_SINGULAR; + } + + /* + * Points to the pivot row of input and destination matrices + */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* + * Temporary pointers to the pivot row pointers + */ + pInT1 = pPivotRowIn; + pOutT1 = pPivotRowDst; + + /* + * Pivot element of the row + */ + in = *(pIn + (l * numCols)); + + pTmpA = pInT1; + + f32x4_t invIn = vdupq_n_f32(1.0f / in); + + blkCnt = (numCols - l) >> 2; + f32x4_t vecA; + while (blkCnt > 0U) + { + *(f32x4_t *) pTmpA = *(f32x4_t *) pTmpA * invIn; + pTmpA += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = (numCols - l) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + + vecA = vldrwq_f32(pTmpA); + vecA = vecA * invIn; + vstrwq_p_f32(pTmpA, vecA, p0); + } + + pInT1 += numCols - l; + /* + * Loop over number of columns + * * to the right of the pilot element + */ + + pTmpA = pOutT1; + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + *(f32x4_t *) pTmpA = *(f32x4_t *) pTmpA *invIn; + pTmpA += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecA = vldrwq_f32(pTmpA); + vecA = vecA * invIn; + vstrwq_p_f32(pTmpA, vecA, p0); + } + + pOutT1 += numCols; + + /* + * Replace the rows with the sum of that row and a multiple of row i + * * so that each new element in column i above row i is zero. + */ + + /* + * Temporary pointers for input and destination matrices + */ + pInT1 = pIn; + pOutT1 = pOut; + + for (i = 0U; i < numRows; i++) + { + /* + * Check for the pivot element + */ + if (i == l) + { + /* + * If the processing element is the pivot element, + * only the columns to the right are to be processed + */ + pInT1 += numCols - l; + pOutT1 += numCols; + } + else + { + /* + * Element of the reference row + */ + + /* + * Working pointers for input and destination pivot rows + */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + /* + * Loop over the number of columns to the right of the pivot element, + * to replace the elements in the input matrix + */ + + in = *pInT1; + f32x4_t tmpV = vdupq_n_f32(in); + + blkCnt = (numCols - l) >> 2; + while (blkCnt > 0U) + { + f32x4_t vec1, vec2; + /* + * Replace the element by the sum of that row + * and a multiple of the reference row + */ + vec1 = vldrwq_f32(pInT1); + vec2 = vldrwq_f32(pPRT_in); + vec1 = vfmsq_f32(vec1, tmpV, vec2); + vstrwq_f32(pInT1, vec1); + pPRT_in += 4; + pInT1 += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numCols - l) & 3; + if (blkCnt > 0U) + { + f32x4_t vec1, vec2; + mve_pred16_t p0 = vctp32q(blkCnt); + + vec1 = vldrwq_f32(pInT1); + vec2 = vldrwq_f32(pPRT_in); + vec1 = vfmsq_f32(vec1, tmpV, vec2); + vstrwq_p_f32(pInT1, vec1, p0); + pInT1 += blkCnt; + } + + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + f32x4_t vec1, vec2; + + /* + * Replace the element by the sum of that row + * and a multiple of the reference row + */ + vec1 = vldrwq_f32(pOutT1); + vec2 = vldrwq_f32(pPRT_pDst); + vec1 = vfmsq_f32(vec1, tmpV, vec2); + vstrwq_f32(pOutT1, vec1); + pPRT_pDst += 4; + pOutT1 += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + f32x4_t vec1, vec2; + mve_pred16_t p0 = vctp32q(blkCnt); + + vec1 = vldrwq_f32(pOutT1); + vec2 = vldrwq_f32(pPRT_pDst); + vec1 = vfmsq_f32(vec1, tmpV, vec2); + vstrwq_p_f32(pOutT1, vec1, p0); + + pInT2 += blkCnt; + pOutT1 += blkCnt; + } + } + /* + * Increment the temporary input pointer + */ + pInT1 = pInT1 + l; + } + /* + * Increment the input pointer + */ + pIn++; + /* + * Decrement the loop counter + */ + loopCnt--; + /* + * Increment the index modifier + */ + l++; + } + + /* + * Set status as ARM_MATH_SUCCESS + */ + status = ARM_MATH_SUCCESS; + + if ((flag != 1U) && (in == 0.0f)) + { + pIn = pSrc->pData; + for (i = 0; i < numRows * numCols; i++) + { + if (pIn[i] != 0.0f) + break; + } + + if (i == numRows * numCols) + status = ARM_MATH_SINGULAR; + } + } + /* Return to application */ + return (status); +} + +#else +#if defined(ARM_MATH_NEON) +arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *pInT1, *pInT2; /* Temporary input data matrix pointer */ + float32_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */ + float32_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */ + uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */ + uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */ + + + float32_t Xchg, in = 0.0f, in1; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, k, l; /* loop counters */ + arm_status status; /* status of matrix inverse */ + float32x4_t vec1; + float32x4_t vec2; + float32x4_t tmpV; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols) + || (pSrc->numRows != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ + * | a11 a12 | 1 0 | | X11 X12 | + * | | | = | | + * |_ a21 a22 | 0 1 _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc). + * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pOutT1 = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0f; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + + /* Decrement the loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + loopCnt = numCols; + + /* Index modifier to navigate through the columns */ + l = 0U; + + while (loopCnt > 0U) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + /* Working pointer for the input matrix that points + * to the pivot element of the particular row */ + pInT1 = pIn + (l * numCols); + + /* Working pointer for the destination matrix that points + * to the pivot element of the particular row */ + pOutT1 = pOut + (l * numCols); + + /* Temporary variable to hold the pivot value */ + in = *pInT1; + + /* Check if the pivot element is zero */ + if (*pInT1 == 0.0f) + { + /* Loop over the number rows present below */ + for (i = 1U; i < numRows - l; i++) + { + /* Update the input and destination pointers */ + pInT2 = pInT1 + (numCols * i); + pOutT2 = pOutT1 + (numCols * i); + + /* Check if there is a non zero pivot element to + * replace in the rows below */ + if (*pInT2 != 0.0f) + { + /* Loop over number of columns + * to the right of the pilot element */ + j = numCols - l; + + while (j > 0U) + { + /* Exchange the row elements of the input matrix */ + Xchg = *pInT2; + *pInT2++ = *pInT1; + *pInT1++ = Xchg; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Exchange the row elements of the destination matrix */ + Xchg = *pOutT2; + *pOutT2++ = *pOutT1; + *pOutT1++ = Xchg; + + /* Decrement the loop counter */ + j--; + } + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + /* Break after exchange is done */ + break; + } + + + } + } + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (in == 0.0f)) + { + return ARM_MATH_SINGULAR; + } + + /* Points to the pivot row of input and destination matrices */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* Temporary pointers to the pivot row pointers */ + pInT1 = pPivotRowIn; + pInT2 = pPivotRowDst; + + /* Pivot element of the row */ + in = *pPivotRowIn; + tmpV = vdupq_n_f32(1.0f/in); + + /* Loop over number of columns + * to the right of the pilot element */ + j = (numCols - l) >> 2; + + while (j > 0U) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + vec1 = vld1q_f32(pInT1); + + vec1 = vmulq_f32(vec1, tmpV); + vst1q_f32(pInT1, vec1); + pInT1 += 4; + + /* Decrement the loop counter */ + j--; + } + + /* Tail */ + j = (numCols - l) & 3; + + while (j > 0U) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + in1 = *pInT1; + *pInT1++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols >> 2; + + while (j > 0U) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + vec1 = vld1q_f32(pInT2); + + vec1 = vmulq_f32(vec1, tmpV); + vst1q_f32(pInT2, vec1); + pInT2 += 4; + + /* Decrement the loop counter */ + j--; + } + + /* Tail */ + j = numCols & 3; + + while (j > 0U) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + in1 = *pInT2; + *pInT2++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + /* Temporary pointers for input and destination matrices */ + pInT1 = pIn; + pInT2 = pOut; + + /* index used to check for pivot element */ + i = 0U; + + /* Loop over number of rows */ + /* to be replaced by the sum of that row and a multiple of row i */ + k = numRows; + + while (k > 0U) + { + /* Check for the pivot element */ + if (i == l) + { + /* If the processing element is the pivot element, + only the columns to the right are to be processed */ + pInT1 += numCols - l; + + pInT2 += numCols; + } + else + { + /* Element of the reference row */ + in = *pInT1; + tmpV = vdupq_n_f32(in); + + /* Working pointers for input and destination pivot rows */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + + /* Loop over the number of columns to the right of the pivot element, + to replace the elements in the input matrix */ + j = (numCols - l) >> 2; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + vec1 = vld1q_f32(pInT1); + vec2 = vld1q_f32(pPRT_in); + vec1 = vmlsq_f32(vec1, tmpV, vec2); + vst1q_f32(pInT1, vec1); + pPRT_in += 4; + pInT1 += 4; + + /* Decrement the loop counter */ + j--; + } + + /* Tail */ + j = (numCols - l) & 3; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT1; + *pInT1++ = in1 - (in * *pPRT_in++); + + /* Decrement the loop counter */ + j--; + } + + /* Loop over the number of columns to + replace the elements in the destination matrix */ + j = numCols >> 2; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + vec1 = vld1q_f32(pInT2); + vec2 = vld1q_f32(pPRT_pDst); + vec1 = vmlsq_f32(vec1, tmpV, vec2); + vst1q_f32(pInT2, vec1); + pPRT_pDst += 4; + pInT2 += 4; + + /* Decrement the loop counter */ + j--; + } + + /* Tail */ + j = numCols & 3; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT2; + *pInT2++ = in1 - (in * *pPRT_pDst++); + + /* Decrement the loop counter */ + j--; + } + + } + + /* Increment the temporary input pointer */ + pInT1 = pInT1 + l; + + /* Decrement the loop counter */ + k--; + + /* Increment the pivot index */ + i++; + } + + /* Increment the input pointer */ + pIn++; + + /* Decrement the loop counter */ + loopCnt--; + + /* Increment the index modifier */ + l++; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + + if ((flag != 1U) && (in == 0.0f)) + { + pIn = pSrc->pData; + for (i = 0; i < numRows * numCols; i++) + { + if (pIn[i] != 0.0f) + break; + } + + if (i == numRows * numCols) + status = ARM_MATH_SINGULAR; + } + } + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *pInT1, *pInT2; /* Temporary input data matrix pointer */ + float32_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */ + float32_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */ + uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */ + uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */ + +#if defined (ARM_MATH_DSP) + + float32_t Xchg, in = 0.0f, in1; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, k,l; /* loop counters */ + arm_status status; /* status of matrix inverse */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ + * | a11 a12 | 1 0 | | X11 X12 | + * | | | = | | + * |_ a21 a22 | 0 1 _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc). + * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pOutT1 = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0f; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + + /* Decrement loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + loopCnt = numCols; + + /* Index modifier to navigate through the columns */ + l = 0U; + + while (loopCnt > 0U) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + /* Working pointer for the input matrix that points + * to the pivot element of the particular row */ + pInT1 = pIn + (l * numCols); + + /* Working pointer for the destination matrix that points + * to the pivot element of the particular row */ + pOutT1 = pOut + (l * numCols); + + /* Temporary variable to hold the pivot value */ + in = *pInT1; + + + + /* Check if the pivot element is zero */ + if (*pInT1 == 0.0f) + { + /* Loop over the number rows present below */ + + for (i = 1U; i < numRows - l; i++) + { + /* Update the input and destination pointers */ + pInT2 = pInT1 + (numCols * i); + pOutT2 = pOutT1 + (numCols * i); + + /* Check if there is a non zero pivot element to + * replace in the rows below */ + if (*pInT2 != 0.0f) + { + /* Loop over number of columns + * to the right of the pilot element */ + j = numCols - l; + + while (j > 0U) + { + /* Exchange the row elements of the input matrix */ + Xchg = *pInT2; + *pInT2++ = *pInT1; + *pInT1++ = Xchg; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Exchange the row elements of the destination matrix */ + Xchg = *pOutT2; + *pOutT2++ = *pOutT1; + *pOutT1++ = Xchg; + + /* Decrement loop counter */ + j--; + } + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + /* Break after exchange is done */ + break; + } + + + /* Decrement loop counter */ + } + } + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (in == 0.0f)) + { + return ARM_MATH_SINGULAR; + } + + /* Points to the pivot row of input and destination matrices */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* Temporary pointers to the pivot row pointers */ + pInT1 = pPivotRowIn; + pInT2 = pPivotRowDst; + + /* Pivot element of the row */ + in = *pPivotRowIn; + + /* Loop over number of columns + * to the right of the pilot element */ + j = (numCols - l); + + while (j > 0U) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + in1 = *pInT1; + *pInT1++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + in1 = *pInT2; + *pInT2++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + /* Temporary pointers for input and destination matrices */ + pInT1 = pIn; + pInT2 = pOut; + + /* index used to check for pivot element */ + i = 0U; + + /* Loop over number of rows */ + /* to be replaced by the sum of that row and a multiple of row i */ + k = numRows; + + while (k > 0U) + { + /* Check for the pivot element */ + if (i == l) + { + /* If the processing element is the pivot element, + only the columns to the right are to be processed */ + pInT1 += numCols - l; + + pInT2 += numCols; + } + else + { + /* Element of the reference row */ + in = *pInT1; + + /* Working pointers for input and destination pivot rows */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + + /* Loop over the number of columns to the right of the pivot element, + to replace the elements in the input matrix */ + j = (numCols - l); + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT1; + *pInT1++ = in1 - (in * *pPRT_in++); + + /* Decrement the loop counter */ + j--; + } + + /* Loop over the number of columns to + replace the elements in the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT2; + *pInT2++ = in1 - (in * *pPRT_pDst++); + + /* Decrement loop counter */ + j--; + } + + } + + /* Increment temporary input pointer */ + pInT1 = pInT1 + l; + + /* Decrement loop counter */ + k--; + + /* Increment pivot index */ + i++; + } + + /* Increment the input pointer */ + pIn++; + + /* Decrement the loop counter */ + loopCnt--; + + /* Increment the index modifier */ + l++; + } + + +#else + + float32_t Xchg, in = 0.0f; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, l; /* loop counters */ + arm_status status; /* status of matrix inverse */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ _ _ _ _ + * | | a11 a12 | | | 1 0 | | | X11 X12 | + * | | | | | | | = | | + * |_ |_ a21 a22 _| | |_0 1 _| _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, src). + * Therefore, the matrix to the right of the bar is our solution(dst matrix, dst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pOutT1 = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0f; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + + /* Decrement loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + loopCnt = numCols; + + /* Index modifier to navigate through the columns */ + l = 0U; + + while (loopCnt > 0U) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + /* Working pointer for the input matrix that points + * to the pivot element of the particular row */ + pInT1 = pIn + (l * numCols); + + /* Working pointer for the destination matrix that points + * to the pivot element of the particular row */ + pOutT1 = pOut + (l * numCols); + + /* Temporary variable to hold the pivot value */ + in = *pInT1; + + /* Check if the pivot element is zero */ + if (*pInT1 == 0.0f) + { + /* Loop over the number rows present below */ + for (i = 1U; i < numRows-l; i++) + { + /* Update the input and destination pointers */ + pInT2 = pInT1 + (numCols * i); + pOutT2 = pOutT1 + (numCols * i); + + /* Check if there is a non zero pivot element to + * replace in the rows below */ + if (*pInT2 != 0.0f) + { + /* Loop over number of columns + * to the right of the pilot element */ + for (j = 0U; j < (numCols - l); j++) + { + /* Exchange the row elements of the input matrix */ + Xchg = *pInT2; + *pInT2++ = *pInT1; + *pInT1++ = Xchg; + } + + for (j = 0U; j < numCols; j++) + { + Xchg = *pOutT2; + *pOutT2++ = *pOutT1; + *pOutT1++ = Xchg; + } + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + /* Break after exchange is done */ + break; + } + } + } + + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (in == 0.0f)) + { + return ARM_MATH_SINGULAR; + } + + /* Points to the pivot row of input and destination matrices */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* Temporary pointers to the pivot row pointers */ + pInT1 = pPivotRowIn; + pOutT1 = pPivotRowDst; + + /* Pivot element of the row */ + in = *(pIn + (l * numCols)); + + /* Loop over number of columns + * to the right of the pilot element */ + for (j = 0U; j < (numCols - l); j++) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + *pInT1 = *pInT1 / in; + pInT1++; + } + for (j = 0U; j < numCols; j++) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + *pOutT1 = *pOutT1 / in; + pOutT1++; + } + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + /* Temporary pointers for input and destination matrices */ + pInT1 = pIn; + pOutT1 = pOut; + + for (i = 0U; i < numRows; i++) + { + /* Check for the pivot element */ + if (i == l) + { + /* If the processing element is the pivot element, + only the columns to the right are to be processed */ + pInT1 += numCols - l; + pOutT1 += numCols; + } + else + { + /* Element of the reference row */ + in = *pInT1; + + /* Working pointers for input and destination pivot rows */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + + /* Loop over the number of columns to the right of the pivot element, + to replace the elements in the input matrix */ + for (j = 0U; j < (numCols - l); j++) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + *pInT1 = *pInT1 - (in * *pPRT_in++); + pInT1++; + } + + /* Loop over the number of columns to + replace the elements in the destination matrix */ + for (j = 0U; j < numCols; j++) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + *pOutT1 = *pOutT1 - (in * *pPRT_pDst++); + pOutT1++; + } + + } + + /* Increment temporary input pointer */ + pInT1 = pInT1 + l; + } + + /* Increment the input pointer */ + pIn++; + + /* Decrement the loop counter */ + loopCnt--; + + /* Increment the index modifier */ + l++; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + + if ((flag != 1U) && (in == 0.0f)) + { + pIn = pSrc->pData; + for (i = 0; i < numRows * numCols; i++) + { + if (pIn[i] != 0.0f) + break; + } + + if (i == numRows * numCols) + status = ARM_MATH_SINGULAR; + } + } + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixInv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c new file mode 100644 index 00000000..bf99a792 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c @@ -0,0 +1,644 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_inverse_f64.c + * Description: Floating-point matrix inverse + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + +/** + @brief Floating-point (64 bit) matrix inverse. + @param[in] pSrc points to input matrix structure. The source matrix is modified by the function. + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_SINGULAR : Input matrix is found to be singular (non-invertible) + */ + +arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pDst) +{ + float64_t *pIn = pSrc->pData; /* input data matrix pointer */ + float64_t *pOut = pDst->pData; /* output data matrix pointer */ + float64_t *pInT1, *pInT2; /* Temporary input data matrix pointer */ + float64_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */ + float64_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */ + uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */ + uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */ + +#if defined (ARM_MATH_DSP) + + float64_t Xchg, in = 0.0, in1; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, k,l; /* loop counters */ + arm_status status; /* status of matrix inverse */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ + * | a11 a12 | 1 0 | | X11 X12 | + * | | | = | | + * |_ a21 a22 | 0 1 _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc). + * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pOutT1 = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0; + j--; + } + + /* Decrement loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + loopCnt = numCols; + + /* Index modifier to navigate through the columns */ + l = 0U; + + while (loopCnt > 0U) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + /* Working pointer for the input matrix that points + * to the pivot element of the particular row */ + pInT1 = pIn + (l * numCols); + + /* Working pointer for the destination matrix that points + * to the pivot element of the particular row */ + pOutT1 = pOut + (l * numCols); + + /* Temporary variable to hold the pivot value */ + in = *pInT1; + + + + /* Check if the pivot element is zero */ + if (*pInT1 == 0.0) + { + /* Loop over the number rows present below */ + + for (i = 1U; i < numRows - l; i++) + { + /* Update the input and destination pointers */ + pInT2 = pInT1 + (numCols * i); + pOutT2 = pOutT1 + (numCols * i); + + /* Check if there is a non zero pivot element to + * replace in the rows below */ + if (*pInT2 != 0.0) + { + /* Loop over number of columns + * to the right of the pilot element */ + j = numCols - l; + + while (j > 0U) + { + /* Exchange the row elements of the input matrix */ + Xchg = *pInT2; + *pInT2++ = *pInT1; + *pInT1++ = Xchg; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Exchange the row elements of the destination matrix */ + Xchg = *pOutT2; + *pOutT2++ = *pOutT1; + *pOutT1++ = Xchg; + + /* Decrement loop counter */ + j--; + } + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + /* Break after exchange is done */ + break; + } + + + /* Decrement loop counter */ + } + } + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (in == 0.0)) + { + return ARM_MATH_SINGULAR; + } + + /* Points to the pivot row of input and destination matrices */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* Temporary pointers to the pivot row pointers */ + pInT1 = pPivotRowIn; + pInT2 = pPivotRowDst; + + /* Pivot element of the row */ + in = *pPivotRowIn; + + /* Loop over number of columns + * to the right of the pilot element */ + j = (numCols - l); + + while (j > 0U) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + in1 = *pInT1; + *pInT1++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + in1 = *pInT2; + *pInT2++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + /* Temporary pointers for input and destination matrices */ + pInT1 = pIn; + pInT2 = pOut; + + /* index used to check for pivot element */ + i = 0U; + + /* Loop over number of rows */ + /* to be replaced by the sum of that row and a multiple of row i */ + k = numRows; + + while (k > 0U) + { + /* Check for the pivot element */ + if (i == l) + { + /* If the processing element is the pivot element, + only the columns to the right are to be processed */ + pInT1 += numCols - l; + + pInT2 += numCols; + } + else + { + /* Element of the reference row */ + in = *pInT1; + + /* Working pointers for input and destination pivot rows */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + + /* Loop over the number of columns to the right of the pivot element, + to replace the elements in the input matrix */ + j = (numCols - l); + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT1; + *pInT1++ = in1 - (in * *pPRT_in++); + + /* Decrement the loop counter */ + j--; + } + + /* Loop over the number of columns to + replace the elements in the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT2; + *pInT2++ = in1 - (in * *pPRT_pDst++); + + /* Decrement loop counter */ + j--; + } + + } + + /* Increment temporary input pointer */ + pInT1 = pInT1 + l; + + /* Decrement loop counter */ + k--; + + /* Increment pivot index */ + i++; + } + + /* Increment the input pointer */ + pIn++; + + /* Decrement the loop counter */ + loopCnt--; + + /* Increment the index modifier */ + l++; + } + + +#else + + float64_t Xchg, in = 0.0; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, l; /* loop counters */ + arm_status status; /* status of matrix inverse */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ _ _ _ _ + * | | a11 a12 | | | 1 0 | | | X11 X12 | + * | | | | | | | = | | + * |_ |_ a21 a22 _| | |_0 1 _| _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, src). + * Therefore, the matrix to the right of the bar is our solution(dst matrix, dst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pOutT1 = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0; + j--; + } + + /* Decrement loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + loopCnt = numCols; + + /* Index modifier to navigate through the columns */ + l = 0U; + + while (loopCnt > 0U) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + /* Working pointer for the input matrix that points + * to the pivot element of the particular row */ + pInT1 = pIn + (l * numCols); + + /* Working pointer for the destination matrix that points + * to the pivot element of the particular row */ + pOutT1 = pOut + (l * numCols); + + /* Temporary variable to hold the pivot value */ + in = *pInT1; + + /* Check if the pivot element is zero */ + if (*pInT1 == 0.0) + { + /* Loop over the number rows present below */ + for (i = 1U; i < numRows-l; i++) + { + /* Update the input and destination pointers */ + pInT2 = pInT1 + (numCols * i); + pOutT2 = pOutT1 + (numCols * i); + + /* Check if there is a non zero pivot element to + * replace in the rows below */ + if (*pInT2 != 0.0) + { + /* Loop over number of columns + * to the right of the pilot element */ + for (j = 0U; j < (numCols - l); j++) + { + /* Exchange the row elements of the input matrix */ + Xchg = *pInT2; + *pInT2++ = *pInT1; + *pInT1++ = Xchg; + } + + for (j = 0U; j < numCols; j++) + { + Xchg = *pOutT2; + *pOutT2++ = *pOutT1; + *pOutT1++ = Xchg; + } + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + /* Break after exchange is done */ + break; + } + } + } + + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (in == 0.0)) + { + return ARM_MATH_SINGULAR; + } + + /* Points to the pivot row of input and destination matrices */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* Temporary pointers to the pivot row pointers */ + pInT1 = pPivotRowIn; + pOutT1 = pPivotRowDst; + + /* Pivot element of the row */ + in = *(pIn + (l * numCols)); + + /* Loop over number of columns + * to the right of the pilot element */ + for (j = 0U; j < (numCols - l); j++) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + *pInT1 = *pInT1 / in; + pInT1++; + } + for (j = 0U; j < numCols; j++) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + *pOutT1 = *pOutT1 / in; + pOutT1++; + } + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + /* Temporary pointers for input and destination matrices */ + pInT1 = pIn; + pOutT1 = pOut; + + for (i = 0U; i < numRows; i++) + { + /* Check for the pivot element */ + if (i == l) + { + /* If the processing element is the pivot element, + only the columns to the right are to be processed */ + pInT1 += numCols - l; + pOutT1 += numCols; + } + else + { + /* Element of the reference row */ + in = *pInT1; + + /* Working pointers for input and destination pivot rows */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + + /* Loop over the number of columns to the right of the pivot element, + to replace the elements in the input matrix */ + for (j = 0U; j < (numCols - l); j++) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + *pInT1 = *pInT1 - (in * *pPRT_in++); + pInT1++; + } + + /* Loop over the number of columns to + replace the elements in the destination matrix */ + for (j = 0U; j < numCols; j++) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + *pOutT1 = *pOutT1 - (in * *pPRT_pDst++); + pOutT1++; + } + + } + + /* Increment temporary input pointer */ + pInT1 = pInT1 + l; + } + + /* Increment the input pointer */ + pIn++; + + /* Decrement the loop counter */ + loopCnt--; + + /* Increment the index modifier */ + l++; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + + if ((flag != 1U) && (in == 0.0)) + { + pIn = pSrc->pData; + for (i = 0; i < numRows * numCols; i++) + { + if (pIn[i] != 0.0) + break; + } + + if (i == numRows * numCols) + status = ARM_MATH_SINGULAR; + } + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixInv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_ldlt_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_ldlt_f32.c new file mode 100644 index 00000000..1d3586c6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_ldlt_f32.c @@ -0,0 +1,509 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_ldl_f32.c + * Description: Floating-point LDL decomposition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + + + + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + + +/// @private +#define SWAP_ROWS_F32(A,i,j) \ + { \ + int cnt = n; \ + \ + for(int w=0;w < n; w+=4) \ + { \ + f32x4_t tmpa,tmpb; \ + mve_pred16_t p0 = vctp32q(cnt); \ + \ + tmpa=vldrwq_z_f32(&A[i*n + w],p0);\ + tmpb=vldrwq_z_f32(&A[j*n + w],p0);\ + \ + vstrwq_p(&A[i*n + w], tmpb, p0); \ + vstrwq_p(&A[j*n + w], tmpa, p0); \ + \ + cnt -= 4; \ + } \ + } + +/// @private +#define SWAP_COLS_F32(A,i,j) \ + for(int w=0;w < n; w++) \ + { \ + float32_t tmp; \ + tmp = A[w*n + i]; \ + A[w*n + i] = A[w*n + j];\ + A[w*n + j] = tmp; \ + } + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point LDL^t decomposition of positive semi-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pl points to the instance of the output floating-point triangular matrix structure. + * @param[out] pd points to the instance of the output floating-point diagonal matrix structure. + * @param[out] pp points to the instance of the output floating-point permutation vector. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * Computes the LDL^t decomposition of a matrix A such that P A P^t = L D L^t. + */ +arm_status arm_mat_ldlt_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pl, + arm_matrix_instance_f32 * pd, + uint16_t * pp) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pl->numRows != pl->numCols) || + (pd->numRows != pd->numCols) || + (pl->numRows != pd->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + const int n=pSrc->numRows; + int fullRank = 1, diag,k; + float32_t *pA; + + memset(pd->pData,0,sizeof(float32_t)*n*n); + memcpy(pl->pData,pSrc->pData,n*n*sizeof(float32_t)); + pA = pl->pData; + + int cnt = n; + uint16x8_t vecP; + + for(int k=0;k < n; k+=8) + { + mve_pred16_t p0; + p0 = vctp16q(cnt); + + vecP = vidupq_u16((uint16_t)k, 1); + + vstrhq_p(&pp[k], vecP, p0); + + cnt -= 8; + } + + + for(k=0;k < n; k++) + { + /* Find pivot */ + float32_t m=F32_MIN,a; + int j=k; + + + for(int r=k;r m) + { + m = pA[r*n+r]; + j = r; + } + } + + if(j != k) + { + SWAP_ROWS_F32(pA,k,j); + SWAP_COLS_F32(pA,k,j); + } + + + pp[k] = j; + + a = pA[k*n+k]; + + if (fabsf(a) < 1.0e-8f) + { + + fullRank = 0; + break; + } + + float32_t invA; + + invA = 1.0f / a; + + int32x4_t vecOffs; + int w; + vecOffs = vidupq_u32((uint32_t)0, 1); + vecOffs = vmulq_n_s32(vecOffs,n); + + for(w=k+1; wpData[row*n+col], zero, p0); + + cnt -= 4; + } + } + } + + for(int row=0; row < n;row++) + { + mve_pred16_t p0; + int cnt= n-row-1; + f32x4_t zero=vdupq_n_f32(0.0f); + + for(int col=row+1; col < n;col+=4) + { + p0 = vctp32q(cnt); + + vstrwq_p(&pl->pData[row*n+col], zero, p0); + + cnt -= 4; + } + } + + for(int d=0; d < diag;d++) + { + pd->pData[d*n+d] = pl->pData[d*n+d]; + pl->pData[d*n+d] = 1.0; + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} +#else + +/// @private +#define SWAP_ROWS_F32(A,i,j) \ + for(w=0;w < n; w++) \ + { \ + float32_t tmp; \ + tmp = A[i*n + w]; \ + A[i*n + w] = A[j*n + w];\ + A[j*n + w] = tmp; \ + } + +/// @private +#define SWAP_COLS_F32(A,i,j) \ + for(w=0;w < n; w++) \ + { \ + float32_t tmp; \ + tmp = A[w*n + i]; \ + A[w*n + i] = A[w*n + j];\ + A[w*n + j] = tmp; \ + } + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point LDL^t decomposition of positive semi-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pl points to the instance of the output floating-point triangular matrix structure. + * @param[out] pd points to the instance of the output floating-point diagonal matrix structure. + * @param[out] pp points to the instance of the output floating-point permutation vector. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * Computes the LDL^t decomposition of a matrix A such that P A P^t = L D L^t. + */ +arm_status arm_mat_ldlt_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pl, + arm_matrix_instance_f32 * pd, + uint16_t * pp) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pl->numRows != pl->numCols) || + (pd->numRows != pd->numCols) || + (pl->numRows != pd->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + const int n=pSrc->numRows; + int fullRank = 1, diag,k; + float32_t *pA; + int row,d; + + memset(pd->pData,0,sizeof(float32_t)*n*n); + memcpy(pl->pData,pSrc->pData,n*n*sizeof(float32_t)); + pA = pl->pData; + + for(k=0;k < n; k++) + { + pp[k] = k; + } + + + for(k=0;k < n; k++) + { + /* Find pivot */ + float32_t m=F32_MIN,a; + int j=k; + + + int r; + int w; + + for(r=k;r m) + { + m = pA[r*n+r]; + j = r; + } + } + + if(j != k) + { + SWAP_ROWS_F32(pA,k,j); + SWAP_COLS_F32(pA,k,j); + } + + + pp[k] = j; + + a = pA[k*n+k]; + + if (fabsf(a) < 1.0e-8f) + { + + fullRank = 0; + break; + } + + for(w=k+1;wpData[row*n+col]=0.0; + } + } + } + + for(row=0; row < n;row++) + { + int col; + for(col=row+1; col < n;col++) + { + pl->pData[row*n+col] = 0.0; + } + } + + for(d=0; d < diag;d++) + { + pd->pData[d*n+d] = pl->pData[d*n+d]; + pl->pData[d*n+d] = 1.0; + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixChol group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_ldlt_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_ldlt_f64.c new file mode 100644 index 00000000..8f7331dc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_ldlt_f64.c @@ -0,0 +1,229 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_ldl_f64.c + * Description: Floating-point LDL decomposition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" +#include + + + +/// @private +#define SWAP_ROWS_F64(A,i,j) \ +{ \ + int w; \ + for(w=0;w < n; w++) \ + { \ + float64_t tmp; \ + tmp = A[i*n + w]; \ + A[i*n + w] = A[j*n + w];\ + A[j*n + w] = tmp; \ + } \ +} + +/// @private +#define SWAP_COLS_F64(A,i,j) \ +{ \ + int w; \ + for(w=0;w < n; w++) \ + { \ + float64_t tmp; \ + tmp = A[w*n + i]; \ + A[w*n + i] = A[w*n + j];\ + A[w*n + j] = tmp; \ + } \ +} + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point LDL^t decomposition of positive semi-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pl points to the instance of the output floating-point triangular matrix structure. + * @param[out] pd points to the instance of the output floating-point diagonal matrix structure. + * @param[out] pp points to the instance of the output floating-point permutation vector. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * Computes the LDL^t decomposition of a matrix A such that P A P^t = L D L^t. + */ + +arm_status arm_mat_ldlt_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pl, + arm_matrix_instance_f64 * pd, + uint16_t * pp) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pl->numRows != pl->numCols) || + (pd->numRows != pd->numCols) || + (pl->numRows != pd->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + const int n=pSrc->numRows; + int fullRank = 1, diag,k; + float64_t *pA; + + memset(pd->pData,0,sizeof(float64_t)*n*n); + + memcpy(pl->pData,pSrc->pData,n*n*sizeof(float64_t)); + pA = pl->pData; + + for(k=0;k < n; k++) + { + pp[k] = k; + } + + + for(k=0;k < n; k++) + { + /* Find pivot */ + float64_t m=F64_MIN,a; + int w,r,j=k; + + + for(r=k;r m) + { + m = pA[r*n+r]; + j = r; + } + } + + if(j != k) + { + SWAP_ROWS_F64(pA,k,j); + SWAP_COLS_F64(pA,k,j); + } + + + pp[k] = j; + + a = pA[k*n+k]; + + if (fabs(a) < 1.0e-18) + { + + fullRank = 0; + break; + } + + for(w=k+1;wpData[row*n+col]=0.0; + } + } + } + } + + { + int row; + for(row=0; row < n;row++) + { + int col; + for(col=row+1; col < n;col++) + { + pl->pData[row*n+col] = 0.0; + } + } + } + + { + int d; + for(d=0; d < diag;d++) + { + pd->pData[d*n+d] = pl->pData[d*n+d]; + pl->pData[d*n+d] = 1.0; + } + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixChol group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f16.c new file mode 100644 index 00000000..3d3e8209 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f16.c @@ -0,0 +1,763 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_f16.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + * @ingroup groupMatrix + */ + + +/** + * @addtogroup MatrixMult + * @{ + */ + +/** + * @brief Floating-point matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +__STATIC_FORCEINLINE arm_status arm_mat_mult_f16_2x2_mve( + const arm_matrix_instance_f16 *pSrcA, + const arm_matrix_instance_f16 *pSrcB, + arm_matrix_instance_f16 *pDst) +{ + static const uint16_t offsetA[8] = { 0, 0, 2, 2, 0, 0, 2, 2 }; + /* offsetB allows to read and duplicate 1 row of B */ + static const uint16_t offsetB[8] = { 0, 1, 0, 1, 0, 1, 0, 1 }; + uint16x8_t vecOffsA, vecOffsB; + f16x8_t vecInA, vecInB, vecDst; + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + + /* + * load initial offsets + */ + vecOffsA = vldrhq_u16((uint16_t const *) offsetA); + vecOffsB = vldrhq_u16((uint16_t const *) offsetB); + /* + * load {a00 a00 a10 a10 x x x x } + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * load {b00 b01 b00 b01 x x x x } + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 a00 b01 + * a10 b00 a10 b01 + * x x + * x x } + */ + vecDst = vmulq(vecInA, vecInB); + /* + * move to 2nd column of matrix A + */ + vecOffsA = vaddq_n_u16(vecOffsA, (uint16_t) 1); + /* + * load {a01 a01 a11 a11 x x x x} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * move to next B row + */ + vecOffsB = vaddq_n_u16(vecOffsB, (uint16_t) 2); + /* + * load {b10, b11, b10, b11, x x x x } + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 + a01 b10 a00 b01 + a01 b11 + * a10 b00 + a11 b10 a10 b01 + a11 b11 + * x x + * x x } + */ + vecDst = vfmaq(vecDst, vecInA, vecInB); + + mve_pred16_t p0 = vctp16q(2*2); + /* + * Store the result in the destination buffer + * (lower half of the vector) + */ + vstrhq_p(pOut, vecDst, p0); + + return (ARM_MATH_SUCCESS); +} + + + + +__STATIC_FORCEINLINE arm_status arm_mat_mult_f16_3x3_mve( + const arm_matrix_instance_f16 *pSrcA, + const arm_matrix_instance_f16 *pSrcB, + arm_matrix_instance_f16 *pDst) +{ + static const uint16_t offsetA[8] = { 0, 0, 0, 3, 3, 3, 6, 6 }; + /* offsetB allows to read and duplicate 1 row of B */ + static const uint16_t offsetB[8] = { 0, 1, 2, 0, 1, 2, 0, 1 }; + uint16x8_t vecOffsA, vecOffsB; + f16x8_t vecInA, vecInB, vecDst; + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + + /* + * load initial offsets + */ + vecOffsA = vldrhq_u16((uint16_t const *) offsetA); + vecOffsB = vldrhq_u16((uint16_t const *) offsetB); + + /* + * load {a00 a00 a00 a10 a10 a10 a20 a20} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * load {b00 b01 b02 b00 b01 b02 b00 b01} + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 a00 b01 a00 b02 + * a10 b00 a10 b01 a10 b02 + * a20 b00 a20 b01} + */ + vecDst = vmulq(vecInA, vecInB); + + /* + * move to 2nd column of matrix A + */ + vecOffsA = vaddq_n_u16(vecOffsA, (uint16_t) 1); + /* + * load {a01 a01 a01 a11 a11 a11 a21 a21} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * move to next B row + */ + vecOffsB = vaddq_n_u16(vecOffsB, (uint16_t) 3); + /* + * load {b10, b11, b12, b10, b11, b12, b10, b11} + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 + a01 b10 a00 b01 + a01 b11 a00 b02 + a01 b12 + * a10 b00 + a11 b10 a10 b01 + a11 b11 a10 b02 + a11 b12 + * a20 b00 + a21 b10 a20 b01 + a21 b11 } + */ + vecDst = vfmaq(vecDst, vecInA, vecInB); + /* + * move to 3rd column of matrix A + */ + vecOffsA = vaddq_n_u16(vecOffsA, (uint16_t) 1); + /* + * load {a02 a02 a02 a12 a12 a12 a22 a22} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * move to next B row + */ + vecOffsB = vaddq_n_u16(vecOffsB, (uint16_t) 3); + /* + * load {b20, b21, b22, b20, b21, b22, b20, b21} + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * {a00 b00 + a01 b10 + a02 b20 a00 b01 + a01 b11 + a02 b21 a00 b02 + a01 b12 + a02 b22}, + * a10 b00 + a11 b10 + a12 b20 a10 b01 + a11 b11 + a12 b21 a10 b02 + a11 b12 + a12 b22}, + * a20 b00 + a21 b10 + a22 b20 a20 b01 + a21 b11 + a22 b21 } + */ + vecDst = vfmaq(vecDst, vecInA, vecInB); + + /* + * Store the result in the destination buffer + */ + vst1q(pOut, vecDst); pOut += 8; + + /* last element computed in scalar mode + * a20 b02 + a21 b12 + a22 b22 + */ + _Float16 * pA = (_Float16 *)pSrcA->pData; + _Float16 * pB = (_Float16 *)pSrcB->pData; + *pOut = pA[2*3] * pB[2] + pA[2*3+1] * pB[3+2] + pA[2*3+2] * pB[2*3+2]; + + return (ARM_MATH_SUCCESS); +} + + + + + +__STATIC_FORCEINLINE arm_status arm_mat_mult_f16_4x4_mve( + const arm_matrix_instance_f16 *pSrcA, + const arm_matrix_instance_f16 *pSrcB, + arm_matrix_instance_f16 *pDst) +{ + /* offsetA allows to read and duplicate 2 successive column elements of A */ + static const uint16_t offsetA[8] = { 0, 0, 0, 0, 4, 4, 4, 4 }; + /* offsetB allows to read and duplicate 1 row of B */ + static const uint16_t offsetB[8] = { 0, 1, 2, 3, 0, 1, 2, 3 }; + uint16x8_t vecOffsA, vecOffsB; + f16x8_t vecInA, vecInB, vecDst0, vecDst1; + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + + /* + * load initial offsets + */ + vecOffsA = vldrhq_u16((uint16_t const *) offsetA); + vecOffsB = vldrhq_u16((uint16_t const *) offsetB); + + /* + * load {a00 a00 a00 a00 a10 a10 a10 a10} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * load {b00 b01 b02 b03 b00 b01 b02 b03} + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 a00 b01 a00 b02 a00 b03 + * a10 b00 a10 b01 a10 b02 a10 b03 } + */ + vecDst0 = vmulq(vecInA, vecInB); + /* + * jump 2 x A rows (2nd half of matrix) + */ + vecOffsA = vaddq_n_u16(vecOffsA, (uint16_t) 8); + /* + * load {a20 a20 a20 a20 a30 a30 a30 a30} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * { a20 b00 a20 b01 a20 b02 a20 b03 + * a30 b00 a30 b01 a30 b02 + a31 b12 } + */ + vecDst1 = vmulq(vecInA, vecInB); + /* + * rewind back to top half of the A matrix (2nd column) + */ + vecOffsA = vsubq(vecOffsA, (uint16_t) 7); + /* + * load {a01 a01 a01 a01 a11 a11 a11 a11} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * move to next B row + */ + vecOffsB = vaddq_n_u16(vecOffsB, (uint16_t) 4); + /* + * load {b10, b11, b12, b13, b10, b11, b12, b13} + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 + a01 b10 a00 b01 + a01 b11 a00 b02 + a01 b12 a00 b03 + a01 b13 + * a10 b00 + a11 b10 a10 b01 + a11 b11 a10 b02 + a11 b12 a10 b03 + a11 b13 } + */ + vecDst0 = vfmaq(vecDst0, vecInA, vecInB); + /* + * jump 2 x A rows (2nd half of matrix) + */ + vecOffsA = vaddq_n_u16(vecOffsA, (uint16_t) 8); + /* + * load {a21 a21 a21 a21 a31 a31 a31 a31} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * {a20 b00 + a21 b10 a20 b01 + a21 b11 a20 b02 + a21 b12 a20 b03 + a21 b13 + * a30 b00 + a31 b10 a30 b01 + a31 b11 a30 b02 + a31 b12 a30 b03 + a31 b13 } + */ + vecDst1 = vfmaq(vecDst1, vecInA, vecInB); + + /* + * rewind back to top half of the A matrix (3rd column) + */ + vecOffsA = vsubq(vecOffsA, (uint16_t) 7); + /* + * load {a02 a02 a02 a02 a12 a12 a12 a12} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * move to next B row + */ + vecOffsB = vaddq_n_u16(vecOffsB, (uint16_t) 4); + /* + * load {b20, b21, b22, b23, b20, b21, b22, b23} + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 + a01 b10 + a02 b20 a00 b01 + a01 b11 + a02 b21 a00 b02 + a01 b12 + a02 b22 a00 b03 + a01 b13 + a02 b23 + * a10 b00 + a11 b10 + a12 b20 a10 b01 + a11 b11 + a12 b21 a10 b02 + a11 b12 + a12 b22 a10 b03 + a11 b13 + a12 b23 } + */ + vecDst0 = vfmaq(vecDst0, vecInA, vecInB); + /* + * jump 2 x A rows + */ + vecOffsA = vaddq_n_u16(vecOffsA, (uint16_t) 8); + + /* + * load {a22 a22 a22 a22 a32 a32 a32 a32} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * {a20 b00 + a21 b10 + a22 b20 a20 b01 + a21 b11 + a22 b21 a20 b02 + a21 b12 + a22 b22 a20 b03 + a21 b13 + a22 b23 + * a30 b00 + a31 b10 + a32 b20 a30 b01 + a31 b11 + a32 b21 a30 b02 + a31 b12 + a32 b22 a30 b03 + a31 b13 + a32 b23 } + */ + vecDst1 = vfmaq(vecDst1, vecInA, vecInB); + + /* + * rewind back to top half of the A matrix (4th column) + */ + vecOffsA = vsubq(vecOffsA, (uint16_t) 7); + /* + * load {a03 a03 a03 a03 a13 a13 a13 a13} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * move to next B row + */ + vecOffsB = vaddq_n_u16(vecOffsB, (uint16_t) 4); + /* + * load {b30, b31, b32, b33, b30, b31, b32, b33} + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 +...+ a03 b30, a00 b01 +...+ a03 b31, a00 b02 +...+ a03 b32, a00 b03 +...+ a03 b33 + * a10 b00 +...+ a13 b30, a10 b01 +...+ a13 b31, a10 b02 +...+ a13 b32, a10 b03 +...+ a13 b33 } + */ + vecDst0 = vfmaq(vecDst0, vecInA, vecInB); + /* + * jump 2 x A rows + */ + vecOffsA = vaddq_n_u16(vecOffsA, (uint16_t) 8); + /* + * load {a23 a23 a23 a23 a33 a33 a33 a33} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * {a20 b00 +...+ a23 b30, a20 b01 +...+ a23 b31, a20 b02 +...+ a23 b32, a20 b03 +...+ a23 b33 + * a30 b00 +...+ a33 b30, a30 b01 +...+ a33 b31, a30 b02 +...+ a33 b32, a30 b03 +...+ a33 b33 } + */ + vecDst1 = vfmaq(vecDst1, vecInA, vecInB); + + /* + * Store the result in the destination buffer + */ + vst1q(pOut, vecDst0); pOut += 8; + vst1q(pOut, vecDst1); + + return (ARM_MATH_SUCCESS); +} + + +arm_status arm_mat_mult_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float16_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + int numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + int numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + int numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint32_t blkCnt; /* loop counters */ + int i; + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + return(ARM_MATH_SIZE_MISMATCH); + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ +{ + /* small squared matrix specialized routines */ + if(numRowsA == numColsB && numColsB == numColsA) { + if(numRowsA == 2) + return arm_mat_mult_f16_2x2_mve(pSrcA, pSrcB, pDst); + else if(numRowsA == 3) + return arm_mat_mult_f16_3x3_mve(pSrcA, pSrcB, pDst); + else if(numRowsA == 4) + return arm_mat_mult_f16_4x4_mve(pSrcA, pSrcB, pDst); + } + + /* main loop process 4 rows */ + i = numRowsA / 4; + while(i > 0) + { + float16_t *pInA0, *pInA1, *pInA2, *pInA3; + float16_t *pInB0; + float16_t *pOut0, *pOut1, *pOut2, *pOut3; + f16x8_t vecMac0, vecMac1, vecMac2, vecMac3; + f16x8_t vecInB; + + /* pointers to 4 consecutive output rows */ + pOut0 = pOut; + pOut1 = pOut0 + numColsB; + pOut2 = pOut1 + numColsB; + pOut3 = pOut2 + numColsB; + pInB0 = pInB; + + int k = numColsB >> 3; + while(k > 0) + { + /* pointers to 4 consecutive Matrix A rows */ + pInA0 = pInA; + pInA1 = pInA0 + numColsA; + pInA2 = pInA1 + numColsA; + pInA3 = pInA2 + numColsA; + + vecMac0 = vdupq_n_f16(0.0f16); + vecMac1 = vdupq_n_f16(0.0f16); + vecMac2 = vdupq_n_f16(0.0f16); + vecMac3 = vdupq_n_f16(0.0f16); + + blkCnt = numColsA; + + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, bi,4n+3..., bi,4n+7} + */ + vecInB = *(f16x8_t *)pInB0; /* vldrhq_f16(pInB0, 0); */ + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + vecMac3 = vfmaq(vecMac3, vecInB, *pInA3++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* Store the results (4 x 8 block) in the destination buffer */ + vst1q(pOut0, vecMac0); pOut0 += 8; + vst1q(pOut1, vecMac1); pOut1 += 8; + vst1q(pOut2, vecMac2); pOut2 += 8; + vst1q(pOut3, vecMac3); pOut3 += 8; + /* + * rewind + */ + pInB0 -= (numColsB * numColsA) - 8; + k--; + } + + int colBLeft = numColsB & 7; + if (colBLeft) + { + pInA0 = pInA; + pInA1 = pInA0 + numColsA; + pInA2 = pInA1 + numColsA; + pInA3 = pInA2 + numColsA; + mve_pred16_t p0 = vctp16q(colBLeft); + + vecMac0 = vdupq_n_f16(0.0f16); + vecMac1 = vdupq_n_f16(0.0f16); + vecMac2 = vdupq_n_f16(0.0f16); + vecMac3 = vdupq_n_f16(0.0f16); + + blkCnt = numColsA; + + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, ..bi,4n+colBLeft-1, 0, ..} + */ + vecInB = vldrhq_z_f16(pInB0, p0); + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + vecMac3 = vfmaq(vecMac3, vecInB, *pInA3++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* Store the results (4 x colBLeft block) in the destination buffer */ + vstrhq_p_f16(pOut0, vecMac0, p0); + vstrhq_p_f16(pOut1, vecMac1, p0); + vstrhq_p_f16(pOut2, vecMac2, p0); + vstrhq_p_f16(pOut3, vecMac3, p0); + } + + pInA += 4 * numColsA; + pOut += 4 * numColsB; + i--; + } + + /* + * non multiple of 4 rows for Matrix A + * process single row + */ + if (numRowsA & 3) + { + i = numRowsA & 3; + do + { + float16_t *pInA0; + float16_t *pInB0; + float16_t *pOut0; + f16x8_t vecInB; + f16x8_t vecMac0; + + pOut0 = pOut; + pInB0 = pInB; + + int k = numColsB >> 3; + while(k > 0) + { + pInA0 = pInA; + + vecMac0 = vdupq_n_f16(0.0f16); + blkCnt = numColsA; + + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, bi,4n+3, ...bi,4n+7} + */ + vecInB = *(f16x8_t *)pInB0; /* vldrhq_f16(pInB0, 0); */ + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* Store the results (1 x 8 block) in the destination buffer */ + vst1q(pOut0, vecMac0); pOut0 += 8; + /* + * rewind + */ + pInB0 -= (numColsB * numColsA) - 8; + k--; + } + + int colBLeft = numColsB & 7; + if (colBLeft) + { + pInA0 = pInA; + mve_pred16_t p0 = vctp16q(colBLeft); + + vecMac0 = vdupq_n_f16(0.0f16); + blkCnt = numColsA; + + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, ..., bi,4n+colBLeft, 0, ...} + */ + vecInB = vldrhq_z_f16(pInB0, p0); + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* Store the results (1 x colBLeft block) in the destination buffer */ + vstrhq_p_f16(pOut0, vecMac0, p0); + } + + pInA += 1 * numColsA; + pOut += 1 * numColsB; + } + while (--i); + } + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); + } +} +#else + + +arm_status arm_mat_mult_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + float16_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + float16_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + float16_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + float16_t *pOut = pDst->pData; /* Output data matrix pointer */ + float16_t *px; /* Temporary output data matrix pointer */ + _Float16 sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint32_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0.0f16; + + /* Initialize pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 MACs at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += (_Float16)*pIn1++ * (_Float16)*pIn2; + pIn2 += numColsB; + + sum += (_Float16)*pIn1++ * (_Float16)*pIn2; + pIn2 += numColsB; + + sum += (_Float16)*pIn1++ * (_Float16)*pIn2; + pIn2 += numColsB; + + sum += (_Float16)*pIn1++ * (_Float16)*pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining MACs */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize cntCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += (_Float16)*pIn1++ * (_Float16)*pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = sum; + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixMult group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c new file mode 100644 index 00000000..d1fd9eac --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c @@ -0,0 +1,1001 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_f32.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +#if defined(ARM_MATH_NEON) +#define GROUPOFROWS 8 +#endif + +/** + * @ingroup groupMatrix + */ + +/** + * @defgroup MatrixMult Matrix Multiplication + * + * Multiplies two matrices. + * + * \image html MatrixMultiplication.gif "Multiplication of two 3 x 3 matrices" + + * Matrix multiplication is only defined if the number of columns of the + * first matrix equals the number of rows of the second matrix. + * Multiplying an M x N matrix with an N x P matrix results + * in an M x P matrix. + * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of + * pSrcA and pSrcB are equal; and (2) that the size of the output + * matrix equals the outer dimensions of pSrcA and pSrcB. + */ + + +/** + * @addtogroup MatrixMult + * @{ + */ + + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MATRIX_DIM3 3 +#define MATRIX_DIM4 4 + +__STATIC_INLINE arm_status arm_mat_mult_f32_2x2_mve( + const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst) +{ + /* {a00, a00, a10, a10} */ + static const uint32_t offsetA0[4] = { 0, 0, 2, 2 }; + /* {b00, b01, b00, b01} */ + static const uint32_t offsetB0[4] = { 0, 1, 0, 1 }; + /* {a01, a01, a11, a11} */ + static const uint32_t offsetA1[4] = { 1, 1, 3, 3 }; + /* {b10, b11, b10, b11} */ + static const uint32_t offsetB1[4] = { 2, 3, 2, 3 }; + + uint32x4_t vecOffsA, vecOffsB; + f32x4_t vecInA, vecInB, vecDst; + + vecOffsA = vldrwq_u32((uint32_t const *) offsetA0); + vecOffsB = vldrwq_u32((uint32_t const *) offsetB0); + + vecInA = vldrwq_gather_shifted_offset((float32_t const *) pSrcA->pData, vecOffsA); + vecInB = vldrwq_gather_shifted_offset((float32_t const *) pSrcB->pData, vecOffsB); + + vecDst = vmulq(vecInA, vecInB); + + vecOffsA = vldrwq_u32((uint32_t const *) offsetA1); + vecOffsB = vldrwq_u32((uint32_t const *) offsetB1); + + vecInA = vldrwq_gather_shifted_offset((float32_t const *) pSrcA->pData, vecOffsA); + vecInB = vldrwq_gather_shifted_offset((float32_t const *) pSrcB->pData, vecOffsB); + + vecDst = vfmaq(vecDst, vecInA, vecInB); + + vstrwq_f32(pDst->pData, vecDst); + + return (ARM_MATH_SUCCESS); + +} + + +/* + * A = {{a00, a01, a02}, + * {a10, a11, a12}, + * {a20, a21, a22}} + * B = {{b00, b01, b02}, + * {b10, b11, b12}, + * {b20, b21, b22}} + * + * Dst = {{a00 b00 + a01 b10 + a02 b20, a00 b01 + a01 b11 + a02 b21, a00 b02 + a01 b12 + a02 b22}, + * {a10 b00 + a11 b10 + a12 b20, a10 b01 + a11 b11 + a12 b21, a10 b02 + a11 b12 + a12 b22}, + * {a20 b00 + a21 b10 + a22 b20, a20 b01 + a21 b11 + a22 b21, a20 b02 + a21 b12 + a22 b22}} + */ +__STATIC_INLINE arm_status arm_mat_mult_f32_3x3_mve( + const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst) +{ + float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *pInA0, *pInA1, *pInA2; + f32x4_t vecMac0, vecMac1, vecMac2; + f32x4_t vecInB; + float32_t const *pSrBVec; + + pSrBVec = (float32_t const *) pInB; + + pInA0 = pInA; + pInA1 = pInA0 + MATRIX_DIM3; + pInA2 = pInA1 + MATRIX_DIM3; + /* enable predication to disable last (4th) vector element */ + mve_pred16_t p0 = vctp32q(MATRIX_DIM3); + + /* + * load {b0,0, b0,1, b0,2, 0} + */ + vecInB = vldrwq_z_f32(pSrBVec, p0); + pSrBVec += MATRIX_DIM3; + + vecMac0 = vmulq(vecInB, *pInA0++); + vecMac1 = vmulq(vecInB, *pInA1++); + vecMac2 = vmulq(vecInB, *pInA2++); + /* + * load {b1,0, b1,1, b1,2, 0} + */ + vecInB = vldrwq_z_f32(pSrBVec, p0); + pSrBVec += MATRIX_DIM3; + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + /* + * load {b2,0, b2,1 , b2,2, 0} + */ + vecInB = vldrwq_z_f32(pSrBVec, p0); + pSrBVec += MATRIX_DIM3; + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + + /* partial vector stores */ + vstrwq_p_f32(pOut, vecMac0, p0); + pOut += MATRIX_DIM3; + vstrwq_p_f32(pOut, vecMac1, p0); + pOut += MATRIX_DIM3; + vstrwq_p_f32(pOut, vecMac2, p0); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + + + +__STATIC_INLINE arm_status arm_mat_mult_f32_4x4_mve( + const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst) +{ + float32_t const *pSrBVec; + float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *pInA0, *pInA1, *pInA2, *pInA3; + f32x4_t vecMac0, vecMac1, vecMac2, vecMac3; + f32x4_t vecInB; + + pSrBVec = (float32_t const *) pInB; + + pInA0 = pInA; + pInA1 = pInA0 + MATRIX_DIM4; + pInA2 = pInA1 + MATRIX_DIM4; + pInA3 = pInA2 + MATRIX_DIM4; + /* + * load {b0,0, b0,1, b0,2, b0,3} + */ + vecInB = vld1q(pSrBVec); + pSrBVec += MATRIX_DIM4; + + vecMac0 = vmulq(vecInB, *pInA0++); + vecMac1 = vmulq(vecInB, *pInA1++); + vecMac2 = vmulq(vecInB, *pInA2++); + vecMac3 = vmulq(vecInB, *pInA3++); + /* + * load {b1,0, b1,1, b1,2, b1,3} + */ + vecInB = vld1q(pSrBVec); + pSrBVec += MATRIX_DIM4; + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + vecMac3 = vfmaq(vecMac3, vecInB, *pInA3++); + /* + * load {b2,0, b2,1, b2,2, b2,3} + */ + vecInB = vld1q(pSrBVec); + pSrBVec += MATRIX_DIM4; + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + vecMac3 = vfmaq(vecMac3, vecInB, *pInA3++); + /* + * load {b3,0, b3,1, b3,2, b3,3} + */ + vecInB = vld1q(pSrBVec); + pSrBVec += MATRIX_DIM4; + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + vecMac3 = vfmaq(vecMac3, vecInB, *pInA3++); + + vst1q(pOut, vecMac0); + pOut += MATRIX_DIM4; + vst1q(pOut, vecMac1); + pOut += MATRIX_DIM4; + vst1q(pOut, vecMac2); + pOut += MATRIX_DIM4; + vst1q(pOut, vecMac3); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +/** + * @brief Floating-point matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + int numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + int numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + int numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint32_t blkCnt; /* loop counters */ + uint32_t i; + arm_status status; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + /* small squared matrix specialized routines */ + if(numRowsA == numColsB && numColsB == numColsA) { + if (numRowsA == 1) + { + pOut[0] = pInA[0] * pInB[0]; + return(ARM_MATH_SUCCESS); + } + else if(numRowsA == 2) + return arm_mat_mult_f32_2x2_mve(pSrcA, pSrcB, pDst); + else if(numRowsA == 3) + return arm_mat_mult_f32_3x3_mve(pSrcA, pSrcB, pDst); + else if(numRowsA == 4) + return arm_mat_mult_f32_4x4_mve(pSrcA, pSrcB, pDst); + } + + /* main loop process 4 rows */ + i = numRowsA >> 2; + while (i > 0U) + { + float32_t *pInA0, *pInA1, *pInA2, *pInA3; + float32_t *pInB0; + float32_t *pOut0, *pOut1, *pOut2, *pOut3; + f32x4_t vecMac0, vecMac1, vecMac2, vecMac3; + f32x4_t vecInB; + + /* pointers to 4 consecutive output rows */ + pOut0 = pOut; + pOut1 = pOut0 + numColsB; + pOut2 = pOut1 + numColsB; + pOut3 = pOut2 + numColsB; + pInB0 = pInB; + + uint32_t k = numColsB >> 2; + while (k > 0U) + { + /* pointers to 4 consecutive Matrix A rows */ + pInA0 = pInA; + pInA1 = pInA0 + numColsA; + pInA2 = pInA1 + numColsA; + pInA3 = pInA2 + numColsA; + + vecMac0 = vdupq_n_f32(0.0f); + vecMac1 = vdupq_n_f32(0.0f); + vecMac2 = vdupq_n_f32(0.0f); + vecMac3 = vdupq_n_f32(0.0f); + + blkCnt = numColsA; + + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, bi,4n+3} + */ + vecInB = *(f32x4_t *)pInB0; /* vldrwq_f32(pInB0, 0); */ + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + vecMac3 = vfmaq(vecMac3, vecInB, *pInA3++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* Store the results (4 x 4 block) in the destination buffer */ + vst1q(pOut0, vecMac0); + pOut0 += 4; + vst1q(pOut1, vecMac1); + pOut1 += 4; + vst1q(pOut2, vecMac2); + pOut2 += 4; + vst1q(pOut3, vecMac3); + pOut3 += 4; + + /* + * rewind + */ + pInB0 -= (numColsB * numColsA) - 4; + k--; + } + + int colBLeft = numColsB & 3; + if (colBLeft) + { + pInA0 = pInA; + pInA1 = pInA0 + numColsA; + pInA2 = pInA1 + numColsA; + pInA3 = pInA2 + numColsA; + mve_pred16_t p0 = vctp32q(colBLeft); + + vecMac0 = vdupq_n_f32(0.0f); + vecMac1 = vdupq_n_f32(0.0f); + vecMac2 = vdupq_n_f32(0.0f); + vecMac3 = vdupq_n_f32(0.0f); + + blkCnt = numColsA; + + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, bi,4n+3} + */ + vecInB = vldrwq_z_f32(pInB0, p0); + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + vecMac3 = vfmaq(vecMac3, vecInB, *pInA3++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* Store the results (4 x colBLeft block) in the destination buffer */ + vstrwq_p_f32(pOut0, vecMac0, p0); + vstrwq_p_f32(pOut1, vecMac1, p0); + vstrwq_p_f32(pOut2, vecMac2, p0); + vstrwq_p_f32(pOut3, vecMac3, p0); + } + + /* move to next rows */ + pInA += 4 * numColsA; + pOut += 4 * numColsB; + i--; + } + + /* + * non multiple of 4 rows for Matrix A + * process single row + */ + if (numRowsA & 3) + { + i = numRowsA & 3; + while (i > 0U) + { + float32_t *pInA0; + float32_t *pInB0; + float32_t *pOut0; + f32x4_t vecInB; + f32x4_t vecMac0; + + pOut0 = pOut; + pInB0 = pInB; + + uint32_t k = numColsB >> 2; + while (k > 0U) + { + pInA0 = pInA; + + vecMac0 = vdupq_n_f32(0.0f); + blkCnt = numColsA; + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, bi,4n+3} + */ + vecInB = *(f32x4_t *)pInB0; /* vldrwq_f32(pInB0, 0); */ + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* Store the results (1 x 4 block) in the destination buffer */ + vst1q(pOut0, vecMac0); + pOut0 += 4; + + /* + * rewind + */ + pInB0 -= (numColsB * numColsA) - 4; + k--; + } + + int colBLeft = numColsB & 3; + if (colBLeft) + { + pInA0 = pInA; + mve_pred16_t p0 = vctp32q(colBLeft); + + vecMac0 = vdupq_n_f32(0.0f); + blkCnt = numColsA; + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, bi,4n+3} + */ + vecInB = vldrwq_z_f32(pInB0, p0); + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* Store the results (1 x colBLeft block) in the destination buffer */ + vstrwq_p_f32(pOut0, vecMac0, p0); + } + + /* move to next row */ + pInA += 1 * numColsA; + pOut += 1 * numColsB; + i--; + } + + } + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else + +#if defined(ARM_MATH_NEON) +/** + * @brief Floating-point matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + float32_t sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + + + uint16_t col, i = 0U, j, row = numRowsA, rowCnt, colCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + + float32x4_t a0V, a1V, a2V, a3V, a4V, a5V, a6V, a7V; + float32x4_t acc0,acc1,acc2,acc3,acc4,acc5,acc6,acc7,temp; + float32x2_t accum = vdup_n_f32(0); + float32_t *pIn1B = pSrcA->pData; + float32_t *pIn1C = pSrcA->pData; + float32_t *pIn1D = pSrcA->pData; + float32_t *pIn1E = pSrcA->pData; + float32_t *pIn1F = pSrcA->pData; + float32_t *pIn1G = pSrcA->pData; + float32_t *pIn1H = pSrcA->pData; + + float32_t *pxB,*pxC, *pxD, *pxE, *pxF, *pxG, *pxH; /* Temporary output data matrix pointer */ + float32_t sum0,sum1, sum2,sum3, sum4, sum5 , sum6, sum7; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* Row loop */ + rowCnt = row >> 3; + + while(rowCnt > 0) + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + GROUPOFROWS*i; + pxB = px + numColsB; + pxC = px + 2*numColsB; + pxD = px + 3*numColsB; + pxE = px + 4*numColsB; + pxF = px + 5*numColsB; + pxG = px + 6*numColsB; + pxH = px + 7*numColsB; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* Column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum0 = 0.0f; + sum1 = 0.0f; + sum2 = 0.0f; + sum3 = 0.0f; + sum4 = 0.0f; + sum5 = 0.0f; + sum6 = 0.0f; + sum7 = 0.0f; + + /* Initiate the pointer pIn1 to point to the starting address of the column being processed */ + pIn1 = pInA; + pIn1B = pIn1 + numColsA; + pIn1C = pIn1 + 2*numColsA; + pIn1D = pIn1 + 3*numColsA; + pIn1E = pIn1 + 4*numColsA; + pIn1F = pIn1 + 5*numColsA; + pIn1G = pIn1 + 6*numColsA; + pIn1H = pIn1 + 7*numColsA; + + acc0 = vdupq_n_f32(0.0); + acc1 = vdupq_n_f32(0.0); + acc2 = vdupq_n_f32(0.0); + acc3 = vdupq_n_f32(0.0); + acc4 = vdupq_n_f32(0.0); + acc5 = vdupq_n_f32(0.0); + acc6 = vdupq_n_f32(0.0); + acc7 = vdupq_n_f32(0.0); + + /* Compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* Matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + a0V = vld1q_f32(pIn1); + a1V = vld1q_f32(pIn1B); + a2V = vld1q_f32(pIn1C); + a3V = vld1q_f32(pIn1D); + a4V = vld1q_f32(pIn1E); + a5V = vld1q_f32(pIn1F); + a6V = vld1q_f32(pIn1G); + a7V = vld1q_f32(pIn1H); + + pIn1 += 4; + pIn1B += 4; + pIn1C += 4; + pIn1D += 4; + pIn1E += 4; + pIn1F += 4; + pIn1G += 4; + pIn1H += 4; + + temp = vsetq_lane_f32(*pIn2,temp,0); + pIn2 += numColsB; + temp = vsetq_lane_f32(*pIn2,temp,1); + pIn2 += numColsB; + temp = vsetq_lane_f32(*pIn2,temp,2); + pIn2 += numColsB; + temp = vsetq_lane_f32(*pIn2,temp,3); + pIn2 += numColsB; + + acc0 = vmlaq_f32(acc0,a0V,temp); + acc1 = vmlaq_f32(acc1,a1V,temp); + acc2 = vmlaq_f32(acc2,a2V,temp); + acc3 = vmlaq_f32(acc3,a3V,temp); + acc4 = vmlaq_f32(acc4,a4V,temp); + acc5 = vmlaq_f32(acc5,a5V,temp); + acc6 = vmlaq_f32(acc6,a6V,temp); + acc7 = vmlaq_f32(acc7,a7V,temp); + + /* Decrement the loop count */ + colCnt--; + } + + accum = vpadd_f32(vget_low_f32(acc0), vget_high_f32(acc0)); + sum0 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(acc1), vget_high_f32(acc1)); + sum1 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(acc2), vget_high_f32(acc2)); + sum2 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(acc3), vget_high_f32(acc3)); + sum3 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(acc4), vget_high_f32(acc4)); + sum4 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(acc5), vget_high_f32(acc5)); + sum5 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(acc6), vget_high_f32(acc6)); + sum6 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(acc7), vget_high_f32(acc7)); + sum7 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA & 3; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + sum0 += *pIn1++ * (*pIn2); + sum1 += *pIn1B++ * (*pIn2); + sum2 += *pIn1C++ * (*pIn2); + sum3 += *pIn1D++ * (*pIn2); + sum4 += *pIn1E++ * (*pIn2); + sum5 += *pIn1F++ * (*pIn2); + sum6 += *pIn1G++ * (*pIn2); + sum7 += *pIn1H++ * (*pIn2); + pIn2 += numColsB; + + /* Decrement the loop counter */ + colCnt--; + } + + /* Store the result in the destination buffer */ + *px++ = sum0; + *pxB++ = sum1; + *pxC++ = sum2; + *pxD++ = sum3; + *pxE++ = sum4; + *pxF++ = sum5; + *pxG++ = sum6; + *pxH++ = sum7; + + /* Update the pointer pIn2 to point to the starting address of the next column */ + j++; + pIn2 = pSrcB->pData + j; + + /* Decrement the column loop counter */ + col--; + + } while (col > 0U); + + /* Update the pointer pInA to point to the starting address of the next row */ + i = i + numColsB; + pInA = pInA + GROUPOFROWS*numColsA; + + /* Decrement the row loop counter */ + rowCnt--; + } + + /* + + i was the index of a group of rows computed by previous loop. + Now i is the index of a row since below code is computing row per row + and no more group of row per group of rows. + + */ + + i = GROUPOFROWS*i; + rowCnt = row & 7; + + while(rowCnt > 0) + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* Column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0.0f; + + /* Initiate the pointer pIn1 to point to the starting address of the column being processed */ + pIn1 = pInA; + + acc0 = vdupq_n_f32(0.0); + + /* Compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* Matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + a0V = vld1q_f32(pIn1); // load & separate real/imag pSrcA (de-interleave 2) + pIn1 += 4; + + temp = vsetq_lane_f32(*pIn2,temp,0); + pIn2 += numColsB; + temp = vsetq_lane_f32(*pIn2,temp,1); + pIn2 += numColsB; + temp = vsetq_lane_f32(*pIn2,temp,2); + pIn2 += numColsB; + temp = vsetq_lane_f32(*pIn2,temp,3); + pIn2 += numColsB; + + acc0 = vmlaq_f32(acc0,a0V,temp); + + /* Decrement the loop count */ + colCnt--; + } + + accum = vpadd_f32(vget_low_f32(acc0), vget_high_f32(acc0)); + sum += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA % 0x4U; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + sum += *pIn1++ * (*pIn2); + pIn2 += numColsB; + + /* Decrement the loop counter */ + colCnt--; + } + + /* Store the result in the destination buffer */ + *px++ = sum; + + /* Update the pointer pIn2 to point to the starting address of the next column */ + j++; + pIn2 = pSrcB->pData + j; + + /* Decrement the column loop counter */ + col--; + + } while (col > 0U); + + + /* Update the pointer pInA to point to the starting address of the next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement the row loop counter */ + rowCnt--; + + } + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +/** + * @brief Floating-point matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + float32_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* Output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + float32_t sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint32_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0.0f; + + /* Initialize pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 MACs at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,p) = a(m,1) * b(1,p) + a(m,2) * b(2,p) + .... + a(m,n) * b(n,p) */ + + /* Perform the multiply-accumulates */ + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining MACs */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize cntCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,p) = a(m,1) * b(1,p) + a(m,2) * b(2,p) + .... + a(m,n) * b(n,p) */ + + /* Perform the multiply-accumulates */ + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = sum; + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f64.c new file mode 100644 index 00000000..a7bdf2d5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f64.c @@ -0,0 +1,202 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_f64.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + * @ingroup groupMatrix + */ + +/** + * @defgroup MatrixMult Matrix Multiplication + * + * Multiplies two matrices. + * + * \image html MatrixMultiplication.gif "Multiplication of two 3 x 3 matrices" + + * Matrix multiplication is only defined if the number of columns of the + * first matrix equals the number of rows of the second matrix. + * Multiplying an M x N matrix with an N x P matrix results + * in an M x P matrix. + * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of + * pSrcA and pSrcB are equal; and (2) that the size of the output + * matrix equals the outer dimensions of pSrcA and pSrcB. + */ + + +/** + * @addtogroup MatrixMult + * @{ + */ + +/** + * @brief Floating-point matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + +arm_status arm_mat_mult_f64( + const arm_matrix_instance_f64 * pSrcA, + const arm_matrix_instance_f64 * pSrcB, + arm_matrix_instance_f64 * pDst) +{ + float64_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + float64_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + float64_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + float64_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + float64_t *pOut = pDst->pData; /* Output data matrix pointer */ + float64_t *px; /* Temporary output data matrix pointer */ + float64_t sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint64_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0.0; + + /* Initialize pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 MACs at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining MACs */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize cntCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = sum; + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + + +/** + * @} end of MatrixMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c new file mode 100644 index 00000000..314b80e5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c @@ -0,0 +1,483 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_fast_q15.c + * Description: Q15 matrix multiplication (fast variant) + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q15 matrix multiplication (fast variant). + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @param[in] pState points to the array for storing intermediate results + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The difference between the function \ref arm_mat_mult_q15() and this fast variant is that + the fast variant use a 32-bit rather than a 64-bit accumulator. + The result of each 1.15 x 1.15 multiplication is truncated to + 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 + format. Finally, the accumulator is saturated and converted to a 1.15 result. + @par + The fast version has the same overflow behavior as the standard version but provides + less precision since it discards the low 16 bits of each multiplication result. + In order to avoid overflows completely the input signals must be scaled down. + Scale down one of the input matrices by log2(numColsA) bits to avoid overflows, + as a total of numColsA additions are computed internally for each output element. + @remark + Refer to \ref arm_mat_mult_q15() for a slower implementation of this function + which uses 64-bit accumulation to provide higher precision. + */ + +arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState) +{ + q31_t sum; /* Accumulator */ + q15_t *pSrcBT = pState; /* Input data matrix pointer for transpose */ + q15_t *pInA = pSrcA->pData; /* Input data matrix pointer A of Q15 type */ + q15_t *pInB = pSrcB->pData; /* Input data matrix pointer B of Q15 type */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint16_t numRowsB = pSrcB->numRows; /* Number of rows of input matrix B */ + uint32_t col, i = 0U, row = numRowsB, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#if defined (ARM_MATH_DSP) + q31_t in; /* Temporary variable to hold the input value */ + q31_t inA1, inB1, inA2, inB2; + q31_t sum2, sum3, sum4; + q15_t *pInA2, *pInB2, *px2; + uint32_t j = 0; +#else + q15_t in; /* Temporary variable to hold the input value */ + q15_t inA1, inB1, inA2, inB2; +#endif /* #if defined (ARM_MATH_DSP) */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose */ + do + { + /* The pointer px is set to starting address of column being processed */ + px = pSrcBT + i; + + /* Apply loop unrolling and exchange columns with row elements */ + col = numColsB >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (col > 0U) + { + +#if defined (ARM_MATH_DSP) + + /* Read two elements from row */ + in = read_q15x2_ia (&pInB); + + /* Unpack and store one element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *px = (q15_t) in; +#else + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + /* Unpack and store second element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#else + *px = (q15_t) in; +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + in = read_q15x2_ia (&pInB); +#ifndef ARM_MATH_BIG_ENDIAN + *px = (q15_t) in; +#else + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + px += numRowsB; + +#ifndef ARM_MATH_BIG_ENDIAN + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#else + *px = (q15_t) in; +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + px += numRowsB; + +#else /* #if defined (ARM_MATH_DSP) */ + + /* Read one element from row */ + in = *pInB++; + + /* Store one element in destination */ + *px = in; + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + in = *pInB++; + *px = in; + px += numRowsB; + + in = *pInB++; + *px = in; + px += numRowsB; + + in = *pInB++; + *px = in; + px += numRowsB; + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement column loop counter */ + col--; + } + + /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + col = numColsB % 0x4U; + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pInB++; + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Reset variables for usage in following multiplication process */ + row = numRowsA; + i = 0U; + px = pDst->pData; + +#if defined (ARM_MATH_DSP) + /* Process two rows from matrix A at a time and output two rows at a time */ + row = row >> 1U; + px2 = px + numColsB; +#endif + + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + while (row > 0U) + { + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of transposed pSrcB data */ + pInB = pSrcBT; + +#if defined (ARM_MATH_DSP) + /* Process two (transposed) columns from matrix B at a time */ + col = col >> 1U; + j = 0; +#endif + + /* column loop */ + while (col > 0U) + { + /* Set variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initiate pointer pInA to point to starting address of column being processed */ + pInA = pSrcA->pData + i; + +#if defined (ARM_MATH_DSP) + sum2 = 0; + sum3 = 0; + sum4 = 0; + pInB = pSrcBT + j; + pInA2 = pInA + numColsA; + pInB2 = pInB + numRowsB; + + /* Read in two elements at once - allows dual MAC instruction */ + colCnt = numColsA >> 1U; +#else + colCnt = numColsA >> 2U; +#endif + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + +#if defined (ARM_MATH_DSP) + /* read real and imag values from pSrcA and pSrcB buffer */ + inA1 = read_q15x2_ia (&pInA); + inB1 = read_q15x2_ia (&pInB); + + inA2 = read_q15x2_ia (&pInA2); + inB2 = read_q15x2_ia (&pInB2); + + /* Multiply and Accumulates */ + sum = __SMLAD(inA1, inB1, sum); + sum2 = __SMLAD(inA1, inB2, sum2); + sum3 = __SMLAD(inA2, inB1, sum3); + sum4 = __SMLAD(inA2, inB2, sum4); +#else + /* read real and imag values from pSrcA and pSrcB buffer */ + inA1 = *pInA++; + inB1 = *pInB++; + /* Multiply and Accumulates */ + sum += inA1 * inB1; + + inA2 = *pInA++; + inB2 = *pInB++; + sum += inA2 * inB2; + + inA1 = *pInA++; + inB1 = *pInB++; + sum += inA1 * inB1; + + inA2 = *pInA++; + inB2 = *pInB++; + sum += inA2 * inB2; +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + colCnt--; + } + + /* process odd column samples */ +#if defined (ARM_MATH_DSP) + if (numColsA & 1U) { + inA1 = *pInA++; + inB1 = *pInB++; + inA2 = *pInA2++; + inB2 = *pInB2++; + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + } +#else + colCnt = numColsA % 0x4U; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + sum += (q31_t) *pInA++ * *pInB++; + + /* Decrement loop counter */ + colCnt--; + } +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Saturate and store result in destination buffer */ + *px++ = (q15_t) (sum >> 15); + +#if defined (ARM_MATH_DSP) + *px++ = (q15_t) (sum2 >> 15); + *px2++ = (q15_t) (sum3 >> 15); + *px2++ = (q15_t) (sum4 >> 15); + j += numRowsB * 2; +#endif + + /* Decrement column loop counter */ + col--; + + } + + i = i + numColsA; + +#if defined (ARM_MATH_DSP) + i = i + numColsA; + px = px2 + (numColsB & 1U); + px2 = px + numColsB; +#endif + + /* Decrement row loop counter */ + row--; + + } + + /* Compute any remaining odd row/column below */ + +#if defined (ARM_MATH_DSP) + + /* Compute remaining output column */ + if (numColsB & 1U) { + + /* Avoid redundant computation of last element */ + row = numRowsA & (~0x1); + + /* Point to remaining unfilled column in output matrix */ + px = pDst->pData + numColsB-1; + pInA = pSrcA->pData; + + /* row loop */ + while (row > 0) + { + + /* point to last column in matrix B */ + pInB = pSrcBT + numRowsB * (numColsB-1); + + /* Set variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Compute 4 columns at once */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + inA1 = read_q15x2_ia (&pInA); + inA2 = read_q15x2_ia (&pInA); + inB1 = read_q15x2_ia (&pInB); + inB2 = read_q15x2_ia (&pInB); + + sum = __SMLAD(inA1, inB1, sum); + sum = __SMLAD(inA2, inB2, sum); + + /* Decrement loop counter */ + colCnt--; + } + + colCnt = numColsA & 3U; + while (colCnt > 0U) { + sum += (q31_t) (*pInA++) * (*pInB++); + colCnt--; + } + + /* Store result in destination buffer */ + *px = (q15_t) (sum >> 15); + px += numColsB; + + /* Decrement row loop counter */ + row--; + } + } + + /* Compute remaining output row */ + if (numRowsA & 1U) { + + /* point to last row in output matrix */ + px = pDst->pData + (numColsB) * (numRowsA-1); + + pInB = pSrcBT; + col = numColsB; + i = 0U; + + /* col loop */ + while (col > 0) + { + /* point to last row in matrix A */ + pInA = pSrcA->pData + (numRowsA-1) * numColsA; + + /* Set variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Compute 4 columns at once */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + inA1 = read_q15x2_ia (&pInA); + inA2 = read_q15x2_ia (&pInA); + inB1 = read_q15x2_ia (&pInB); + inB2 = read_q15x2_ia (&pInB); + + sum = __SMLAD(inA1, inB1, sum); + sum = __SMLAD(inA2, inB2, sum); + + /* Decrement loop counter */ + colCnt--; + } + + colCnt = numColsA % 4U; + while (colCnt > 0U) { + sum += (q31_t) (*pInA++) * (*pInB++); + + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = (q15_t) (sum >> 15); + + /* Decrement column loop counter */ + col--; + } + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c new file mode 100644 index 00000000..99a42328 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c @@ -0,0 +1,374 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_fast_q31.c + * Description: Q31 matrix multiplication (fast variant) + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q31 matrix multiplication (fast variant). + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The difference between the function \ref arm_mat_mult_q31() and this fast variant is that + the fast variant use a 32-bit rather than a 64-bit accumulator. + The result of each 1.31 x 1.31 multiplication is truncated to + 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 + format. Finally, the accumulator is saturated and converted to a 1.31 result. + @par + The fast version has the same overflow behavior as the standard version but provides + less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signals must be scaled down. + Scale down one of the input matrices by log2(numColsA) bits to avoid overflows, + as a total of numColsA additions are computed internally for each output element. + @remark + Refer to \ref arm_mat_mult_q31() for a slower implementation of this function + which uses 64-bit accumulation to provide higher precision. + */ + +arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pInA2; + q31_t *px; /* Temporary output data matrix pointer */ + q31_t *px2; + q31_t sum1, sum2, sum3, sum4; /* Accumulator */ + q31_t inA1, inA2, inB1, inB2; + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint32_t col, i = 0U, j, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + px = pDst->pData; + + row = row >> 1U; + px2 = px + numColsB; + + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + while (row > 0U) + { + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pInB = pSrcB->pData; + + j = 0U; + + col = col >> 1U; + + /* column loop */ + while (col > 0U) + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum1 = 0; + sum2 = 0; + sum3 = 0; + sum4 = 0; + + /* Initiate data pointers */ + pInA = pSrcA->pData + i; + pInB = pSrcB->pData + j; + pInA2 = pInA + numColsA; + + colCnt = numColsA; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + inA1 = *pInA++; + inB1 = pInB[0]; + inA2 = *pInA2++; + inB2 = pInB[1]; + pInB += numColsB; + +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(inA1, inB1, sum1); + sum2 = __SMMLA(inA1, inB2, sum2); + sum3 = __SMMLA(inA2, inB1, sum3); + sum4 = __SMMLA(inA2, inB2, sum4); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA1 * inB1)) >> 32); + sum2 = (q31_t) ((((q63_t) sum2 << 32) + ((q63_t) inA1 * inB2)) >> 32); + sum3 = (q31_t) ((((q63_t) sum3 << 32) + ((q63_t) inA2 * inB1)) >> 32); + sum4 = (q31_t) ((((q63_t) sum4 << 32) + ((q63_t) inA2 * inB2)) >> 32); +#endif + + /* Decrement loop counter */ + colCnt--; + } + + /* Convert the result from 2.30 to 1.31 format and store in destination buffer */ + *px++ = sum1 << 1; + *px++ = sum2 << 1; + *px2++ = sum3 << 1; + *px2++ = sum4 << 1; + + j += 2; + + /* Decrement column loop counter */ + col--; + } + + i = i + (numColsA << 1U); + px = px2 + (numColsB & 1U); + px2 = px + numColsB; + + /* Decrement row loop counter */ + row--; + } + + /* Compute any remaining odd row/column below */ + + /* Compute remaining output column */ + if (numColsB & 1U) { + + /* Avoid redundant computation of last element */ + row = numRowsA & (~1U); + + /* Point to remaining unfilled column in output matrix */ + px = pDst->pData + numColsB-1; + pInA = pSrcA->pData; + + /* row loop */ + while (row > 0) + { + + /* point to last column in matrix B */ + pInB = pSrcB->pData + numColsB-1; + + /* Set variable sum1, that acts as accumulator, to zero */ + sum1 = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 columns at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining column */ + colCnt = numColsA % 4U; + +#else + + /* Initialize colCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) { +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + + colCnt--; + } + + /* Convert the result from 2.30 to 1.31 format and store in destination buffer */ + *px = sum1 << 1; + px += numColsB; + + /* Decrement row loop counter */ + row--; + } + } + + /* Compute remaining output row */ + if (numRowsA & 1U) { + + /* point to last row in output matrix */ + px = pDst->pData + (numColsB) * (numRowsA-1); + + col = numColsB; + i = 0U; + + /* col loop */ + while (col > 0) + { + + /* point to last row in matrix A */ + pInA = pSrcA->pData + (numRowsA-1) * numColsA; + pInB = pSrcB->pData + i; + + /* Set variable sum1, that acts as accumulator, to zero */ + sum1 = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 columns at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + inA1 = *pInA++; + inA2 = *pInA++; + inB1 = *pInB; + pInB += numColsB; + inB2 = *pInB; + pInB += numColsB; +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(inA1, inB1, sum1); + sum1 = __SMMLA(inA2, inB2, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA1 * inB1)) >> 32); + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA2 * inB2)) >> 32); +#endif + + inA1 = *pInA++; + inA2 = *pInA++; + inB1 = *pInB; + pInB += numColsB; + inB2 = *pInB; + pInB += numColsB; +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(inA1, inB1, sum1); + sum1 = __SMMLA(inA2, inB2, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA1 * inB1)) >> 32); + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA2 * inB2)) >> 32); +#endif + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining column */ + colCnt = numColsA % 4U; + +#else + + /* Initialize colCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) { +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + + colCnt--; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = sum1 << 1; + i++; + + /* Decrement col loop counter */ + col--; + } + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_opt_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_opt_q31.c new file mode 100644 index 00000000..91b1bcd5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_opt_q31.c @@ -0,0 +1,784 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_opt_q31.c + * Description: Q31 matrix multiplication + * + * $Date: 3 Nov 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q31 matrix multiplication. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @param[in] pState points to the array for storing intermediate results + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. There is no saturation + on intermediate additions. Thus, if the accumulator overflows it wraps around and + distorts the result. The input signals should be scaled down to avoid intermediate + overflows. The input is thus scaled down by log2(numColsA) bits + to avoid overflows, as a total of numColsA additions are performed internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + @remark + Refer to \ref arm_mat_mult_fast_q31() for a faster but less precise implementation of this function. + @remark + This function is a faster implementation of arm_mat_mult_q31 for MVE but it is requiring + additional storage for intermediate results. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MATRIX_DIM2 2 +#define MATRIX_DIM3 3 +#define MATRIX_DIM4 4 + +__STATIC_INLINE arm_status arm_mat_mult_opt_q31_2x2_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs; + q31_t *pInA0 = pInA; + q31_t *pInA1 = pInA0 + MATRIX_DIM2; + q63_t acc0, acc1; + q31x4_t vecB, vecA0, vecA1; + /* enable predication to disable half of vector elements */ + mve_pred16_t p0 = vctp32q(MATRIX_DIM2); + + vecColBOffs = vidupq_u32((uint32_t)0, 1); + vecColBOffs = vecColBOffs * MATRIX_DIM2; + + pInB = pSrcB->pData; + + /* load 1st B column (partial load) */ + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + /* load A rows */ + vecA0 = vldrwq_s32(pInA0); + vecA1 = vldrwq_s32(pInA1); + + acc0 = vrmlaldavhq(vecA0, vecB); + acc1 = vrmlaldavhq(vecA1, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + + pOut[0 * MATRIX_DIM2] = (q31_t) acc0; + pOut[1 * MATRIX_DIM2] = (q31_t) acc1; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + acc0 = vrmlaldavhq(vecA0, vecB); + acc1 = vrmlaldavhq(vecA1, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + + pOut[0 * MATRIX_DIM2] = (q31_t) acc0; + pOut[1 * MATRIX_DIM2] = (q31_t) acc1; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + + +__STATIC_INLINE arm_status arm_mat_mult_opt_q31_3x3_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs; + q31_t *pInA0 = pInA; + q31_t *pInA1 = pInA0 + MATRIX_DIM3; + q31_t *pInA2 = pInA1 + MATRIX_DIM3; + q63_t acc0, acc1, acc2; + q31x4_t vecB, vecA; + /* enable predication to disable last (4th) vector element */ + mve_pred16_t p0 = vctp32q(MATRIX_DIM3); + + vecColBOffs = vidupq_u32((uint32_t)0, 1); + vecColBOffs = vecColBOffs * MATRIX_DIM3; + + pInB = pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + pOut[0 * MATRIX_DIM3] = (q31_t) acc0; + pOut[1 * MATRIX_DIM3] = (q31_t) acc1; + pOut[2 * MATRIX_DIM3] = (q31_t) acc2; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + pOut[0 * MATRIX_DIM3] = (q31_t) acc0; + pOut[1 * MATRIX_DIM3] = (q31_t) acc1; + pOut[2 * MATRIX_DIM3] = (q31_t) acc2; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + pOut[0 * MATRIX_DIM3] = (q31_t) acc0; + pOut[1 * MATRIX_DIM3] = (q31_t) acc1; + pOut[2 * MATRIX_DIM3] = (q31_t) acc2; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_mult_opt_q31_4x4_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs; + q31_t *pInA0 = pInA; + q31_t *pInA1 = pInA0 + MATRIX_DIM4; + q31_t *pInA2 = pInA1 + MATRIX_DIM4; + q31_t *pInA3 = pInA2 + MATRIX_DIM4; + q63_t acc0, acc1, acc2, acc3; + q31x4_t vecB, vecA; + + vecColBOffs = vidupq_u32((uint32_t)0, 4); + + pInB = pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +arm_status arm_mat_mult_opt_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst, + q31_t *pState) +{ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pInA2; + q31_t *pInB2; + q31_t *px; /* Temporary output data matrix pointer */ + q31_t *px2; /* Temporary output data matrix pointer */ + uint32_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint32_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint32_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint32_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */ + uint32_t col, i = 0u, j, row = numRowsB; /* loop counters */ + q31_t *pSrcBT = pState; /* input data matrix pointer for transpose */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* Status of matrix multiplication */ + arm_matrix_instance_q31 BT; +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols)) { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + + /* small squared matrix specialized routines */ + if(numRowsA == numColsB && numColsB == numColsA) { + if (numRowsA == 1) + { + q63_t sum = (q63_t) *pInA * *pInB; + pDst->pData[0] = (q31_t)(sum >> 31); + return (ARM_MATH_SUCCESS); + } + else if(numRowsA == 2) + return arm_mat_mult_opt_q31_2x2_mve(pSrcA, pSrcB, pDst); + else if(numRowsA == 3) + return arm_mat_mult_opt_q31_3x3_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 4) + return arm_mat_mult_opt_q31_4x4_mve(pSrcA, pSrcB, pDst); + } + + + /* + * Matrix transpose + */ + BT.numRows = numColsB; + BT.numCols = numRowsB; + BT.pData = pSrcBT; + + arm_mat_trans_q31(pSrcB, &BT); + + + /* + * Reset the variables for the usage in the following multiplication process + */ + i = 0; + row = numRowsA >> 1; + px = pDst->pData; + px2 = px + numColsB; + + /* + * main loop + * compute 2 x 2 output blocks + * with dot products (Matrix A rows * Transposed MAtrix B rows) + */ + while (row > 0u) { + /* + * For every row wise process, the column loop counter is to be initiated + * Compute 2 columns and 2 rows in parrallel + */ + col = numColsB >> 1; + j = 0; + + /* + * column pair loop + */ + while (col > 0u) { + q31_t const *pSrcAVec, *pSrcBVec, *pSrcA2Vec, *pSrcB2Vec; + q31x4_t vecA, vecA2, vecB, vecB2; + q63_t acc0, acc1, acc2, acc3; + + /* + * Initiate the pointers + * - 2 x consecutive Matrix A rows (i increment is 2 x numColsA) + * - 2 x consecutive Matrix B' rows (j increment is 2 x numRowsB) + */ + pInA = pSrcA->pData + i; + pInA2 = pInA + numColsA; + pInB = pSrcBT + j; + pInB2 = pInB + numRowsB; + + + pSrcAVec = (q31_t const *) pInA; + pSrcA2Vec = (q31_t const *) pInA2; + pSrcBVec = (q31_t const *) pInB; + pSrcB2Vec = (q31_t const *) pInB2; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + acc3 = 0LL; + + /* load scheduling */ + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + + blkCnt = (numColsA / 4); + while (blkCnt > 0U) { + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + acc0 = vrmlaldavhaq(acc0, vecA, vecB); + vecA2 = vld1q(pSrcA2Vec); + pSrcA2Vec += 4; + acc1 = vrmlaldavhaq(acc1, vecA2, vecB); + vecB2 = vld1q(pSrcB2Vec); + pSrcB2Vec += 4; + acc2 = vrmlaldavhaq(acc2, vecA, vecB2); + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + acc3 = vrmlaldavhaq(acc3, vecA2, vecB2); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numColsA & 3); + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + vecB = vld1q(pSrcBVec); + acc0 = vrmlaldavhaq_p(acc0, vecA, vecB, p0); + vecA2 = vld1q(pSrcA2Vec); + acc1 = vrmlaldavhaq_p(acc1, vecA2, vecB, p0); + vecB2 = vld1q(pSrcB2Vec); + acc2 = vrmlaldavhaq_p(acc2, vecA, vecB2, p0); + vecA = vld1q(pSrcAVec); + acc3 = vrmlaldavhaq_p(acc3, vecA2, vecB2, p0); + } + + /* Convert to 1.31 */ + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + /* Store the results (2 x 2 block) in the destination buffer */ + *px++ = (q31_t) acc0; + *px++ = (q31_t) acc2; + *px2++ = (q31_t) acc1; + *px2++ = (q31_t) acc3; + + j += numRowsB * 2; + /* + * Decrement the column pair loop counter + */ + col--; + + } + + i = i + numColsA * 2; + px = px2 + (numColsB & 1u); + px2 = px + numColsB; + /* + * Decrement the row pair loop counter + */ + row--; + } + + /* + * Compute remaining row and/or column below + */ + if (numColsB & 1u) { + row = numRowsA & (~0x1); //avoid redundant computation + px = pDst->pData + numColsB - 1; + i = 0; + + /* + * row loop + */ + while (row > 0) { + q31_t const *pSrcAVec, *pSrcBVec; + q31x4_t vecA, vecB; + q63_t acc0; + + /* + * point to last column in matrix B + */ + pInB = pSrcBT + numRowsB * (numColsB - 1); + pInA = pSrcA->pData + i; + + pSrcAVec = (q31_t const *) pInA; + pSrcBVec = (q31_t const *) pInB; + + /* single dot-product */ + acc0 = 0LL; + blkCnt = (numColsA / 4); + while (blkCnt > 0U) { + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + acc0 = vrmlaldavhaq(acc0, vecA, vecB); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numColsA & 3); + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + acc0 = vrmlaldavhaq_p(acc0, vecA, vecB, p0); + } + + acc0 = asrl(acc0, 23); + *px = (q31_t) acc0; + + px += numColsB; + + i += numColsA; + /* + * Decrement the row loop counter + */ + row--; + } + } + + if (numRowsA & 1u) { + col = numColsB; + i = 0u; + /* + * point to last row in output matrix + */ + px = pDst->pData + (numColsB) * (numRowsA - 1); + /* + * col loop + */ + while (col > 0) { + q31_t const *pSrcAVec, *pSrcBVec; + q31x4_t vecA, vecB; + q63_t acc0; + + /* + * point to last row in matrix A + */ + pInA = pSrcA->pData + (numRowsA - 1) * numColsA; + pInB = pSrcBT + i; + + /* + * Set the variable sum, that acts as accumulator, to zero + */ + pSrcAVec = (q31_t const *) pInA; + pSrcBVec = (q31_t const *) pInB; + acc0 = 0LL; + + blkCnt = (numColsA / 4); + while (blkCnt > 0U) { + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + acc0 = vrmlaldavhaq(acc0, vecA, vecB); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numColsA & 3); + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + acc0 = vrmlaldavhaq_p(acc0, vecA, vecB, p0); + } + + acc0 = asrl(acc0, 23); + *px++ = (q31_t) acc0; + + i += numColsA; + /* + * Decrement the col loop counter + */ + col--; + } + } + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + /* + * Return to application + */ + return (status); +} + +#else +arm_status arm_mat_mult_opt_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst, + q31_t *pState) +{ + q31_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pOut = pDst->pData; /* Output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + q63_t sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint32_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + (void)pState; +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initialize pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 MACs at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining MACs */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize cntCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Convert result from 2.62 to 1.31 format and store in destination buffer */ + *px++ = (q31_t) (sum >> 31); + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c new file mode 100644 index 00000000..e078681d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c @@ -0,0 +1,843 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_q15.c + * Description: Q15 matrix multiplication + * + * $Date: 3 Nov 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q15 matrix multiplication. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @param[in] pState points to the array for storing intermediate results + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. The inputs to the + multiplications are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits + and then saturated to 1.15 format. + @par + Refer to \ref arm_mat_mult_fast_q15() for a faster but less precise version of this function. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MVE_ASRL_SAT16(acc, shift) ((sqrshrl_sat48(acc, -(32-shift)) >> 32) & 0xffffffff) + +#define MATRIX_DIM2 2 +#define MATRIX_DIM3 3 +#define MATRIX_DIM4 4 + +__STATIC_INLINE arm_status arm_mat_mult_q15_2x2_mve( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16x8_t vecColBOffs; + q15_t *pInA0 = pInA; + q15_t *pInA1 = pInA0 + MATRIX_DIM2; + q63_t acc0, acc1; + q15x8_t vecB, vecA0, vecA1; + mve_pred16_t p0 = vctp16q(MATRIX_DIM2); + + vecColBOffs = vidupq_u16((uint32_t)0, 2); /* MATRIX_DIM2 */ + + pInB = pSrcB->pData; + + vecB = vldrhq_gather_shifted_offset_z_s16((q15_t const *)pInB, vecColBOffs, p0); + + vecA0 = vldrhq_s16(pInA0); + vecA1 = vldrhq_s16(pInA1); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + + pOut[0 * MATRIX_DIM2] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM2] = (q15_t) __SSAT(acc1, 16); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrhq_gather_shifted_offset_z_s16(pInB, vecColBOffs, p0); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + + pOut[0 * MATRIX_DIM2] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM2] = (q15_t) __SSAT(acc1, 16); + + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + + +__STATIC_INLINE arm_status arm_mat_mult_q15_3x3_mve( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16x8_t vecColBOffs; + q15_t *pInA0 = pInA; + q15_t *pInA1 = pInA0 + MATRIX_DIM3; + q15_t *pInA2 = pInA1 + MATRIX_DIM3; + q63_t acc0, acc1, acc2; + q15x8_t vecB, vecA0, vecA1, vecA2; + mve_pred16_t p0 = vctp16q(MATRIX_DIM3); + + vecColBOffs = vidupq_u16((uint32_t)0, 1); + vecColBOffs = vecColBOffs * MATRIX_DIM3; + + pInB = pSrcB->pData; + + vecB = vldrhq_gather_shifted_offset_z_s16((q15_t const *)pInB, vecColBOffs, p0); + + vecA0 = vldrhq_s16(pInA0); + vecA1 = vldrhq_s16(pInA1); + vecA2 = vldrhq_s16(pInA2); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + acc2 = vmlaldavq(vecA2, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + + pOut[0 * MATRIX_DIM3] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM3] = (q15_t) __SSAT(acc1, 16); + pOut[2 * MATRIX_DIM3] = (q15_t) __SSAT(acc2, 16); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrhq_gather_shifted_offset_z_s16(pInB, vecColBOffs, p0); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + acc2 = vmlaldavq(vecA2, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + + pOut[0 * MATRIX_DIM3] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM3] = (q15_t) __SSAT(acc1, 16); + pOut[2 * MATRIX_DIM3] = (q15_t) __SSAT(acc2, 16); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrhq_gather_shifted_offset_z_s16(pInB, vecColBOffs, p0); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + acc2 = vmlaldavq(vecA2, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + + pOut[0 * MATRIX_DIM3] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM3] = (q15_t) __SSAT(acc1, 16); + pOut[2 * MATRIX_DIM3] = (q15_t) __SSAT(acc2, 16); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +__STATIC_INLINE arm_status arm_mat_mult_q15_4x4_mve( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16x8_t vecColBOffs; + q15_t *pInA0 = pInA; + q15_t *pInA1 = pInA0 + MATRIX_DIM4; + q15_t *pInA2 = pInA1 + MATRIX_DIM4; + q15_t *pInA3 = pInA2 + MATRIX_DIM4; + q63_t acc0, acc1, acc2, acc3; + q15x8_t vecB, vecA0, vecA1, vecA2, vecA3; + mve_pred16_t p0 = vctp16q(MATRIX_DIM4); + + vecColBOffs = vidupq_u16((uint32_t)0, 4); + + pInB = pSrcB->pData; + + vecB = vldrhq_gather_shifted_offset_z_s16((q15_t const *)pInB, vecColBOffs, p0); + + vecA0 = vldrhq_s16(pInA0); + vecA1 = vldrhq_s16(pInA1); + vecA2 = vldrhq_s16(pInA2); + vecA3 = vldrhq_s16(pInA3); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + acc2 = vmlaldavq(vecA2, vecB); + acc3 = vmlaldavq(vecA3, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + acc3 = asrl(acc3, 15); + + pOut[0 * MATRIX_DIM4] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM4] = (q15_t) __SSAT(acc1, 16); + pOut[2 * MATRIX_DIM4] = (q15_t) __SSAT(acc2, 16); + pOut[3 * MATRIX_DIM4] = (q15_t) __SSAT(acc3, 16); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrhq_gather_shifted_offset_z_s16(pInB, vecColBOffs, p0); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + acc2 = vmlaldavq(vecA2, vecB); + acc3 = vmlaldavq(vecA3, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + acc3 = asrl(acc3, 15); + + pOut[0 * MATRIX_DIM4] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM4] = (q15_t) __SSAT(acc1, 16); + pOut[2 * MATRIX_DIM4] = (q15_t) __SSAT(acc2, 16); + pOut[3 * MATRIX_DIM4] = (q15_t) __SSAT(acc3, 16); + + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrhq_gather_shifted_offset_z_s16(pInB, vecColBOffs, p0); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + acc2 = vmlaldavq(vecA2, vecB); + acc3 = vmlaldavq(vecA3, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + acc3 = asrl(acc3, 15); + + pOut[0 * MATRIX_DIM4] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM4] = (q15_t) __SSAT(acc1, 16); + pOut[2 * MATRIX_DIM4] = (q15_t) __SSAT(acc2, 16); + pOut[3 * MATRIX_DIM4] = (q15_t) __SSAT(acc3, 16); + + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrhq_gather_shifted_offset_z_s16(pInB, vecColBOffs, p0); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + acc2 = vmlaldavq(vecA2, vecB); + acc3 = vmlaldavq(vecA3, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + acc3 = asrl(acc3, 15); + + pOut[0 * MATRIX_DIM4] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM4] = (q15_t) __SSAT(acc1, 16); + pOut[2 * MATRIX_DIM4] = (q15_t) __SSAT(acc2, 16); + pOut[3 * MATRIX_DIM4] = (q15_t) __SSAT(acc3, 16); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState) +{ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q15_t *pInA2; + q15_t *pInB2; + q15_t *px; /* Temporary output data matrix pointer */ + q15_t *px2; /* Temporary output data matrix pointer */ + uint32_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint32_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint32_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint32_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */ + uint32_t col, i = 0u, j, row = numRowsB; /* loop counters */ + q15_t *pSrcBT = pState; /* input data matrix pointer for transpose */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* Status of matrix multiplication */ + arm_matrix_instance_q15 BT; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + /* small squared matrix specialized routines */ + if (numRowsA == numColsB && numColsB == numColsA) { + + if (numRowsA == 1) { + q63_t sum; + sum = pInA[0] * pInB[0]; + pDst->pData[0] = (q15_t) __SSAT((sum >> 15), 16); + return (ARM_MATH_SUCCESS); + } else if (numRowsA == 2) + return arm_mat_mult_q15_2x2_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 3) + return arm_mat_mult_q15_3x3_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 4) + return arm_mat_mult_q15_4x4_mve(pSrcA, pSrcB, pDst); + } + + /* + * Matrix transpose + */ + + BT.numRows = numColsB; + BT.numCols = numRowsB; + BT.pData = pSrcBT; + + arm_mat_trans_q15(pSrcB, &BT); + + + /* + * Reset the variables for the usage in the following multiplication process + */ + i = 0; + row = numRowsA >> 1; + px = pDst->pData; + px2 = px + numColsB; + + /* + * The following loop performs the dot-product of each row in pSrcA with each column in pSrcB + */ + + /* + * row loop + */ + while (row > 0u) { + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB >> 1; + /* + * For every row wise process, the pIn2 pointer is set + * to the starting address of the transposed pSrcB data + */ + pInB = pSrcBT; + pInB2 = pInB + numRowsB; + j = 0; + + /* + * column loop + */ + while (col > 0u) { + q15_t const *pSrcAVec, *pSrcBVec, *pSrcA2Vec, *pSrcB2Vec; + q15x8_t vecA, vecA2, vecB, vecB2; + q63_t acc0, acc1, acc2, acc3; + + /* + * Initiate the pointer pIn1 to point to the starting address of the column being processed + */ + pInA = pSrcA->pData + i; + pInA2 = pInA + numColsA; + pInB = pSrcBT + j; + pInB2 = pInB + numRowsB; + + + pSrcAVec = (q15_t const *) pInA; + pSrcA2Vec = (q15_t const *) pInA2; + pSrcBVec = (q15_t const *) pInB; + pSrcB2Vec = (q15_t const *) pInB2; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + acc3 = 0LL; + + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + + blkCnt = numColsA / 8; + while (blkCnt > 0U) { + vecB = vld1q(pSrcBVec); + pSrcBVec += 8; + acc0 = vmlaldavaq(acc0, vecA, vecB); + vecA2 = vld1q(pSrcA2Vec); + pSrcA2Vec += 8; + acc1 = vmlaldavaq(acc1, vecA2, vecB); + vecB2 = vld1q(pSrcB2Vec); + pSrcB2Vec += 8; + acc2 = vmlaldavaq(acc2, vecA, vecB2); + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + acc3 = vmlaldavaq(acc3, vecA2, vecB2); + + blkCnt--; + } + /* + * tail + */ + blkCnt = numColsA & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + vecB = vld1q(pSrcBVec); + acc0 = vmlaldavaq_p(acc0, vecA, vecB, p0); + vecA2 = vld1q(pSrcA2Vec); + acc1 = vmlaldavaq_p(acc1, vecA2, vecB, p0); + vecB2 = vld1q(pSrcB2Vec); + acc2 = vmlaldavaq_p(acc2, vecA, vecB2, p0); + vecA = vld1q(pSrcAVec); + acc3 = vmlaldavaq_p(acc3, vecA2, vecB2, p0); + } + + *px++ = (q15_t) MVE_ASRL_SAT16(acc0, 15); + *px++ = (q15_t) MVE_ASRL_SAT16(acc2, 15); + *px2++ = (q15_t) MVE_ASRL_SAT16(acc1, 15); + *px2++ = (q15_t) MVE_ASRL_SAT16(acc3, 15); + j += numRowsB * 2; + /* + * Decrement the column loop counter + */ + col--; + + } + + i = i + numColsA * 2; + px = px2 + (numColsB & 1u); + px2 = px + numColsB; + /* + * Decrement the row loop counter + */ + row--; + } + + /* + * Compute remaining row and/or column below + */ + + if (numColsB & 1u) { + row = numRowsA & (~0x1); //avoid redundant computation + px = pDst->pData + numColsB - 1; + i = 0; + + /* + * row loop + */ + while (row > 0) { + q15_t const *pSrcAVec, *pSrcBVec; + q15x8_t vecA, vecB; + q63_t acc0; + + /* + * point to last column in matrix B + */ + pInB = pSrcBT + numRowsB * (numColsB - 1); + pInA = pSrcA->pData + i; + + pSrcAVec = (q15_t const *) pInA; + pSrcBVec = (q15_t const *) pInB; + + acc0 = 0LL; + blkCnt = (numColsA) / 8; + while (blkCnt > 0U) { + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + vecB = vld1q(pSrcBVec); + pSrcBVec += 8; + acc0 = vmlaldavaq(acc0, vecA, vecB); + + blkCnt--; + } + /* + * tail + */ + blkCnt = (numColsA & 7); + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + acc0 = vmlaldavaq_p(acc0, vecA, vecB, p0); + } + + *px = (q15_t) MVE_ASRL_SAT16(acc0, 15); + + px += numColsB; + + i += numColsA; + /* + * Decrement the row loop counter + */ + row--; + } + } + + if (numRowsA & 1u) { + col = numColsB; + i = 0u; + /* + * point to last row in output matrix + */ + px = pDst->pData + (numColsB) * (numRowsA - 1); + /* + * col loop + */ + while (col > 0) { + q15_t const *pSrcAVec, *pSrcBVec; + q15x8_t vecA, vecB; + q63_t acc0; + + /* + * point to last row in matrix A + */ + pInA = pSrcA->pData + (numRowsA - 1) * numColsA; + pInB = pSrcBT + i; + + /* + * Set the variable sum, that acts as accumulator, to zero + */ + pSrcAVec = (q15_t const *) pInA; + pSrcBVec = (q15_t const *) pInB; + acc0 = 0LL; + + blkCnt = ((numColsA) / 8); + while (blkCnt > 0U) { + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + vecB = vld1q(pSrcBVec); + pSrcBVec += 8; + acc0 = vmlaldavaq(acc0, vecA, vecB); + + blkCnt--; + } + /* + * tail + */ + blkCnt = (numColsA & 7); + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + acc0 = vmlaldavaq_p(acc0, vecA, vecB, p0); + } + + *px++ = (q15_t) MVE_ASRL_SAT16(acc0, 15); + + i += numColsA; + + /* + * Decrement the col loop counter + */ + col--; + } + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState) +{ + q63_t sum; /* Accumulator */ + +#if defined (ARM_MATH_DSP) /* != CM0 */ + + q15_t *pSrcBT = pState; /* Input data matrix pointer for transpose */ + q15_t *pInA = pSrcA->pData; /* Input data matrix pointer A of Q15 type */ + q15_t *pInB = pSrcB->pData; /* Input data matrix pointer B of Q15 type */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint16_t numRowsB = pSrcB->numRows; /* Number of rows of input matrix B */ + uint32_t col, i = 0U, row = numRowsB, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + + q31_t inA1, inB1, inA2, inB2; + arm_matrix_instance_q15 BT; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + + BT.numRows = numColsB; + BT.numCols = numRowsB; + BT.pData = pSrcBT; + + arm_mat_trans_q15(pSrcB,&BT); + /* Reset variables for usage in following multiplication process */ + row = numRowsA; + i = 0U; + px = pDst->pData; + + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of transposed pSrcB data */ + pInB = pSrcBT; + + /* column loop */ + do + { + /* Set variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initiate pointer pInA to point to starting address of column being processed */ + pInA = pSrcA->pData + i; + + /* Apply loop unrolling and compute 2 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + inA1 = read_q15x2_ia (&pInA); + inB1 = read_q15x2_ia (&pInB); + + inA2 = read_q15x2_ia (&pInA); + inB2 = read_q15x2_ia (&pInB); + + /* Multiply and Accumulates */ + sum = __SMLALD(inA1, inB1, sum); + sum = __SMLALD(inA2, inB2, sum); + + /* Decrement loop counter */ + colCnt--; + } + + /* process remaining column samples */ + colCnt = numColsA % 0x4U; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + sum += *pInA++ * *pInB++; + + /* Decrement loop counter */ + colCnt--; + } + + /* Saturate and store result in destination buffer */ + *px = (q15_t) (__SSAT((sum >> 15), 16)); + px++; + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + i = i + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + +#else /* #if defined (ARM_MATH_DSP) */ + + q15_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + q15_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + q15_t *pInA = pSrcA->pData; /* Input data matrix pointer A of Q15 type */ + q15_t *pInB = pSrcB->pData; /* Input data matrix pointer B of Q15 type */ + q15_t *pOut = pDst->pData; /* Output data matrix pointer */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint32_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + (void)pState; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initiate pointer pIn1 to point to starting address of pSrcA */ + pIn1 = pInA; + + /* Matrix A columns number of MAC operations are to be performed */ + colCnt = numColsA; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform multiply-accumulates */ + sum += (q31_t) * pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Convert result from 34.30 to 1.15 format and store saturated value in destination buffer */ + + /* Saturate and store result in destination buffer */ + *px++ = (q15_t) __SSAT((sum >> 15), 16); + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pSrcA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c new file mode 100644 index 00000000..18738279 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c @@ -0,0 +1,761 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_q31.c + * Description: Q31 matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q31 matrix multiplication. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. There is no saturation + on intermediate additions. Thus, if the accumulator overflows it wraps around and + distorts the result. The input signals should be scaled down to avoid intermediate + overflows. The input is thus scaled down by log2(numColsA) bits + to avoid overflows, as a total of numColsA additions are performed internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + @remark + Refer to \ref arm_mat_mult_fast_q31() for a faster but less precise implementation of this function. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MATRIX_DIM2 2 +#define MATRIX_DIM3 3 +#define MATRIX_DIM4 4 + +__STATIC_INLINE arm_status arm_mat_mult_q31_2x2_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs; + q31_t *pInA0 = pInA; + q31_t *pInA1 = pInA0 + MATRIX_DIM2; + q63_t acc0, acc1; + q31x4_t vecB, vecA0, vecA1; + /* enable predication to disable half of vector elements */ + mve_pred16_t p0 = vctp32q(MATRIX_DIM2); + + vecColBOffs = vidupq_u32((uint32_t)0, 1); + vecColBOffs = vecColBOffs * MATRIX_DIM2; + + pInB = pSrcB->pData; + + /* load 1st B column (partial load) */ + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + /* load A rows */ + vecA0 = vldrwq_s32(pInA0); + vecA1 = vldrwq_s32(pInA1); + + acc0 = vrmlaldavhq(vecA0, vecB); + acc1 = vrmlaldavhq(vecA1, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + + pOut[0 * MATRIX_DIM2] = (q31_t) acc0; + pOut[1 * MATRIX_DIM2] = (q31_t) acc1; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + acc0 = vrmlaldavhq(vecA0, vecB); + acc1 = vrmlaldavhq(vecA1, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + + pOut[0 * MATRIX_DIM2] = (q31_t) acc0; + pOut[1 * MATRIX_DIM2] = (q31_t) acc1; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + + +__STATIC_INLINE arm_status arm_mat_mult_q31_3x3_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs; + q31_t *pInA0 = pInA; + q31_t *pInA1 = pInA0 + MATRIX_DIM3; + q31_t *pInA2 = pInA1 + MATRIX_DIM3; + q63_t acc0, acc1, acc2; + q31x4_t vecB, vecA; + /* enable predication to disable last (4th) vector element */ + mve_pred16_t p0 = vctp32q(MATRIX_DIM3); + + vecColBOffs = vidupq_u32((uint32_t)0, 1); + vecColBOffs = vecColBOffs * MATRIX_DIM3; + + pInB = pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + pOut[0 * MATRIX_DIM3] = (q31_t) acc0; + pOut[1 * MATRIX_DIM3] = (q31_t) acc1; + pOut[2 * MATRIX_DIM3] = (q31_t) acc2; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + pOut[0 * MATRIX_DIM3] = (q31_t) acc0; + pOut[1 * MATRIX_DIM3] = (q31_t) acc1; + pOut[2 * MATRIX_DIM3] = (q31_t) acc2; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + pOut[0 * MATRIX_DIM3] = (q31_t) acc0; + pOut[1 * MATRIX_DIM3] = (q31_t) acc1; + pOut[2 * MATRIX_DIM3] = (q31_t) acc2; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_mult_q31_4x4_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs; + q31_t *pInA0 = pInA; + q31_t *pInA1 = pInA0 + MATRIX_DIM4; + q31_t *pInA2 = pInA1 + MATRIX_DIM4; + q31_t *pInA3 = pInA2 + MATRIX_DIM4; + q63_t acc0, acc1, acc2, acc3; + q31x4_t vecB, vecA; + + vecColBOffs = vidupq_u32((uint32_t)0, 4); + + pInB = pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t const *pInB = (q31_t const *)pSrcB->pData; /* input data matrix pointer B */ + q31_t const *pInA = (q31_t const *)pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint16_t col, i = 0U, row = numRowsA; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + uint32x4_t vecOffs, vecColBOffs; + uint32_t blkCnt, rowCnt; /* loop counters */ + + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* small squared matrix specialized routines */ + if(numRowsA == numColsB && numColsB == numColsA) { + if (numRowsA == 1) + { + q63_t sum = (q63_t) *pInA * *pInB; + pOut[0] = (q31_t)(sum >> 31); + return (ARM_MATH_SUCCESS); + } + else if(numRowsA == 2) + return arm_mat_mult_q31_2x2_mve(pSrcA, pSrcB, pDst); + else if(numRowsA == 3) + return arm_mat_mult_q31_3x3_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 4) + return arm_mat_mult_q31_4x4_mve(pSrcA, pSrcB, pDst); + } + + vecColBOffs = vidupq_u32((uint32_t)0, 1); + vecColBOffs = vecColBOffs * (uint32_t) (numColsB); + + /* + * The following loop performs the dot-product of each row in pSrcA with each column in pSrcB + */ + + /* + * row loop + */ + rowCnt = row >> 2; + while (rowCnt > 0U) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i; + i = i + 4 * numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (q31_t const *)pSrcB->pData; + /* + * column loop + */ + while (col > 0U) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + q31_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec; + q31_t const *pInA0 = pInA; + q31_t const *pInA1 = pInA0 + numColsA; + q31_t const *pInA2 = pInA1 + numColsA; + q31_t const *pInA3 = pInA2 + numColsA; + q63_t acc0, acc1, acc2, acc3; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + acc3 = 0LL; + + pSrcA0Vec = (q31_t const *) pInA0; + pSrcA1Vec = (q31_t const *) pInA1; + pSrcA2Vec = (q31_t const *) pInA2; + pSrcA3Vec = (q31_t const *) pInA3; + + vecOffs = vecColBOffs; + + /* process 1 x 4 block output */ + blkCnt = numColsA >> 2; + while (blkCnt > 0U) + { + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset(pInB, vecOffs); + /* move Matrix B read offsets, 4 rows down */ + vecOffs = vecOffs + (uint32_t) (numColsB * 4); + + vecA = vld1q(pSrcA0Vec); pSrcA0Vec += 4; + acc0 = vrmlaldavhaq(acc0, vecA, vecB); + vecA = vld1q(pSrcA1Vec); pSrcA1Vec += 4; + acc1 = vrmlaldavhaq(acc1, vecA, vecB); + vecA = vld1q(pSrcA2Vec); pSrcA2Vec += 4; + acc2 = vrmlaldavhaq(acc2, vecA, vecB); + vecA = vld1q(pSrcA3Vec); pSrcA3Vec += 4; + acc3 = vrmlaldavhaq(acc3, vecA, vecB); + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numColsA & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecOffs, p0); + //vecOffs = vecOffs + (uint32_t) (numColsB * 4); + + vecA = vld1q(pSrcA0Vec); pSrcA0Vec += 4; + acc0 = vrmlaldavhaq(acc0, vecA, vecB); + vecA = vld1q(pSrcA1Vec); pSrcA1Vec += 4; + acc1 = vrmlaldavhaq(acc1, vecA, vecB); + vecA = vld1q(pSrcA2Vec); pSrcA2Vec += 4; + acc2 = vrmlaldavhaq(acc2, vecA, vecB); + vecA = vld1q(pSrcA3Vec); pSrcA3Vec += 4; + acc3 = vrmlaldavhaq(acc3, vecA, vecB); + } + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + px[0] = (q31_t) acc0; + px[1 * numColsB] = (q31_t) acc1; + px[2 * numColsB] = (q31_t) acc2; + px[3 * numColsB] = (q31_t) acc3; + px++; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (q31_t const *)pSrcB->pData + (numColsB - col); + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += (numColsA * 4); + /* + * Decrement the row loop counter + */ + rowCnt --; + + } + rowCnt = row & 3; + while (rowCnt > 0U) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i; + i = i + numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (q31_t const *)pSrcB->pData; + /* + * column loop + */ + while (col > 0U) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + q31_t const *pSrcA0Vec; + q31_t const *pInA0 = pInA; + q63_t acc0; + + acc0 = 0LL; + + + pSrcA0Vec = (q31_t const *) pInA0; + + vecOffs = vecColBOffs; + + /* process 1 x 4 block output */ + blkCnt = numColsA >> 2; + while (blkCnt > 0U) + { + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset(pInB, vecOffs); + /* move Matrix B read offsets, 4 rows down */ + vecOffs = vecOffs + (uint32_t) (numColsB * 4); + + vecA = vld1q(pSrcA0Vec); pSrcA0Vec += 4; + acc0 = vrmlaldavhaq(acc0, vecA, vecB); + + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numColsA & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecOffs, p0); + //vecOffs = vecOffs + (uint32_t) (numColsB * 4); + + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vrmlaldavhaq(acc0, vecA, vecB); + + } + + acc0 = asrl(acc0, 23); + + + px[0] = (q31_t) acc0; + px++; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (q31_t const *)pSrcB->pData + (numColsB - col); + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += numColsA; + /* + * Decrement the row loop counter + */ + rowCnt--; + } + + /* + * set status as ARM_MATH_SUCCESS + */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pOut = pDst->pData; /* Output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + q63_t sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint32_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initialize pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 MACs at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining MACs */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize cntCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Convert result from 2.62 to 1.31 format and store in destination buffer */ + *px++ = (q31_t) (sum >> 31); + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q7.c new file mode 100644 index 00000000..3ce0fe60 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q7.c @@ -0,0 +1,678 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_q7.c + * Description: Q15 matrix multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + * @brief Q7 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results (Unused in some versions) + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * Scaling and Overflow Behavior: + * + * \par + * The function is implemented using a 32-bit internal accumulator saturated to 1.7 format. + * + * + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +__STATIC_FORCEINLINE arm_status arm_mat_mult_q7_2x2_mve( + const arm_matrix_instance_q7 * pSrcA, + const arm_matrix_instance_q7 * pSrcB, + arm_matrix_instance_q7 * pDst) +{ + const uint32_t MATRIX_DIM = 2; + q7_t const *pInB = (q7_t const *)pSrcB->pData; /* input data matrix pointer B */ + q7_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q7_t *pOut = pDst->pData; /* output data matrix pointer */ + uint8x16_t vecColBOffs; + q7_t *pInA0 = pInA; + q7_t *pInA1 = pInA0 + MATRIX_DIM; + q31_t acc0, acc1; + q7x16_t vecB, vecA0, vecA1; + mve_pred16_t p0 = vctp8q(MATRIX_DIM); + + vecColBOffs = vidupq_u8((uint32_t)0, 2); /* MATRIX_DIM */ + + pInB = pSrcB->pData; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + vecA0 = vldrbq_s8(pInA0); + vecA1 = vldrbq_s8(pInA1); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +__STATIC_FORCEINLINE arm_status arm_mat_mult_q7_3x3_mve( + const arm_matrix_instance_q7 * pSrcA, + const arm_matrix_instance_q7 * pSrcB, + arm_matrix_instance_q7 * pDst) +{ + const uint8_t MATRIX_DIM = 3; + q7_t const *pInB = (q7_t const *)pSrcB->pData; /* input data matrix pointer B */ + q7_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q7_t *pOut = pDst->pData; /* output data matrix pointer */ + uint8x16_t vecColBOffs; + q7_t *pInA0 = pInA; + q7_t *pInA1 = pInA0 + MATRIX_DIM; + q7_t *pInA2 = pInA1 + MATRIX_DIM; + q31_t acc0, acc1, acc2; + q7x16_t vecB, vecA0, vecA1, vecA2; + mve_pred16_t p0 = vctp8q(MATRIX_DIM); + + vecColBOffs = vidupq_u8((uint32_t)0, 1); + vecColBOffs = vecColBOffs * MATRIX_DIM; + + pInB = pSrcB->pData; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + vecA0 = vldrbq_s8(pInA0); + vecA1 = vldrbq_s8(pInA1); + vecA2 = vldrbq_s8(pInA2); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + acc2 = vmladavq_s8(vecA2, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut[2 * MATRIX_DIM] = (q7_t) __SSAT(acc2 >> 7, 8); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + acc2 = vmladavq_s8(vecA2, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut[2 * MATRIX_DIM] = (q7_t) __SSAT(acc2 >> 7, 8); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + acc2 = vmladavq_s8(vecA2, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut[2 * MATRIX_DIM] = (q7_t) __SSAT(acc2 >> 7, 8); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +__STATIC_FORCEINLINE arm_status arm_mat_mult_q7_4x4_mve( + const arm_matrix_instance_q7 * pSrcA, + const arm_matrix_instance_q7 * pSrcB, + arm_matrix_instance_q7 * pDst) +{ + const uint32_t MATRIX_DIM = 4; + q7_t const *pInB = (q7_t const *)pSrcB->pData; /* input data matrix pointer B */ + q7_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q7_t *pOut = pDst->pData; /* output data matrix pointer */ + uint8x16_t vecColBOffs; + q7_t *pInA0 = pInA; + q7_t *pInA1 = pInA0 + MATRIX_DIM; + q7_t *pInA2 = pInA1 + MATRIX_DIM; + q7_t *pInA3 = pInA2 + MATRIX_DIM; + q31_t acc0, acc1, acc2, acc3; + q7x16_t vecB, vecA0, vecA1, vecA2, vecA3; + mve_pred16_t p0 = vctp8q(MATRIX_DIM); + + vecColBOffs = vidupq_u8((uint32_t)0, 4); + + pInB = pSrcB->pData; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + vecA0 = vldrbq_s8(pInA0); + vecA1 = vldrbq_s8(pInA1); + vecA2 = vldrbq_s8(pInA2); + vecA3 = vldrbq_s8(pInA3); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + acc2 = vmladavq_s8(vecA2, vecB); + acc3 = vmladavq_s8(vecA3, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut[2 * MATRIX_DIM] = (q7_t) __SSAT(acc2 >> 7, 8); + pOut[3 * MATRIX_DIM] = (q7_t) __SSAT(acc3 >> 7, 8); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + acc2 = vmladavq_s8(vecA2, vecB); + acc3 = vmladavq_s8(vecA3, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut[2 * MATRIX_DIM] = (q7_t) __SSAT(acc2 >> 7, 8); + pOut[3 * MATRIX_DIM] = (q7_t) __SSAT(acc3 >> 7, 8); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + acc2 = vmladavq_s8(vecA2, vecB); + acc3 = vmladavq_s8(vecA3, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut[2 * MATRIX_DIM] = (q7_t) __SSAT(acc2 >> 7, 8); + pOut[3 * MATRIX_DIM] = (q7_t) __SSAT(acc3 >> 7, 8); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + acc2 = vmladavq_s8(vecA2, vecB); + acc3 = vmladavq_s8(vecA3, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut[2 * MATRIX_DIM] = (q7_t) __SSAT(acc2 >> 7, 8); + pOut[3 * MATRIX_DIM] = (q7_t) __SSAT(acc3 >> 7, 8); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + +arm_status arm_mat_mult_q7( + const arm_matrix_instance_q7 * pSrcA, + const arm_matrix_instance_q7 * pSrcB, + arm_matrix_instance_q7 * pDst, + q7_t * pState) +{ + q7_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q7 type */ + q7_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q7 type */ + q7_t *pInA2; + q7_t *pInB2; + q7_t *px; /* Temporary output data matrix pointer */ + q7_t *px2; /* Temporary output data matrix pointer */ + uint32_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint32_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint32_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint32_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */ + uint32_t col, i = 0u, j, row = numRowsB; /* loop counters */ + q7_t *pSrcBT = pState; /* input data matrix pointer for transpose */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + arm_matrix_instance_q7 BT; + + + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + /* small squared matrix specialized routines */ + if(numRowsA == numColsB && numColsB == numColsA) { + if(numRowsA == 2) + return arm_mat_mult_q7_2x2_mve(pSrcA, pSrcB, pDst); + else if(numRowsA == 3) + return arm_mat_mult_q7_3x3_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 4) + return arm_mat_mult_q7_4x4_mve(pSrcA, pSrcB, pDst); + } + /* + * Matrix transpose + */ + + BT.numRows = numColsB; + BT.numCols = numRowsB; + BT.pData = pSrcBT; + + arm_mat_trans_q7(pSrcB, &BT); + + /* + * Reset the variables for the usage in the following multiplication process + */ + i = 0; + row = numRowsA >> 1; + px = pDst->pData; + px2 = px + numColsB; + + /* + * The following loop performs the dot-product of each row in pSrcA with each column in pSrcB + */ + + /* + * row loop + */ + while (row > 0u) + { + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB >> 1; + /* + * For every row wise process, the pIn2 pointer is set + * to the starting address of the transposed pSrcB data + */ + pInB = pSrcBT; + pInB2 = pInB + numRowsB; + j = 0; + + /* + * column loop + */ + while (col > 0u) + { + q7_t const *pSrcAVec, *pSrcBVec, *pSrcA2Vec, *pSrcB2Vec; + q7x16_t vecA, vecA2, vecB, vecB2; + q31_t acc0, acc1, acc2, acc3; + + /* + * Initiate the pointer pIn1 to point to the starting address of the column being processed + */ + pInA = pSrcA->pData + i; + pInA2 = pInA + numColsA; + pInB = pSrcBT + j; + pInB2 = pInB + numRowsB; + + pSrcAVec = (q7_t const *) pInA; + pSrcA2Vec = (q7_t const *)pInA2; + pSrcBVec = (q7_t const *) pInB; + pSrcB2Vec = (q7_t const *)pInB2; + + acc0 = 0L; + acc1 = 0L; + acc2 = 0L; + acc3 = 0L; + + vecA = vld1q(pSrcAVec); + pSrcAVec += 16; + + blkCnt = numColsA >> 4; + while (blkCnt > 0U) + { + vecB = vld1q(pSrcBVec); + pSrcBVec += 16; + acc0 = vmladavaq_s8(acc0, vecA, vecB); + vecA2 = vld1q(pSrcA2Vec); + pSrcA2Vec += 16; + acc1 = vmladavaq_s8(acc1, vecA2, vecB); + vecB2 = vld1q(pSrcB2Vec); + pSrcB2Vec += 16; + acc2 = vmladavaq_s8(acc2, vecA, vecB2); + vecA = vld1q(pSrcAVec); + pSrcAVec += 16; + acc3 = vmladavaq_s8(acc3, vecA2, vecB2); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numColsA & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecB = vld1q(pSrcBVec); + acc0 = vmladavaq_p_s8(acc0, vecA, vecB, p0); + vecA2 = vld1q(pSrcA2Vec); + acc1 = vmladavaq_p_s8(acc1, vecA2, vecB, p0); + vecB2 = vld1q(pSrcB2Vec); + acc2 = vmladavaq_p_s8(acc2, vecA, vecB2, p0); + vecA = vld1q(pSrcAVec); + acc3 = vmladavaq_p_s8(acc3, vecA2, vecB2, p0); + } + + *px++ = (q7_t) __SSAT(acc0 >> 7, 8); + *px++ = (q7_t) __SSAT(acc2 >> 7, 8); + *px2++ = (q7_t) __SSAT(acc1 >> 7, 8); + *px2++ = (q7_t) __SSAT(acc3 >> 7, 8); + j += numRowsB * 2; + /* + * Decrement the column loop counter + */ + col--; + + } + + i = i + numColsA * 2; + px = px2 + (numColsB & 1u); + px2 = px + numColsB; + /* + * Decrement the row loop counter + */ + row--; + } + + /* + * Compute remaining row and/or column below + */ + + if (numColsB & 1u) + { + row = numRowsA & (~0x1); //avoid redundant computation + px = pDst->pData + numColsB - 1; + i = 0; + + /* + * row loop + */ + while (row > 0) + { + q7_t const *pSrcAVec, *pSrcBVec; + q7x16_t vecA, vecB; + q63_t acc0; + + /* + * point to last column in matrix B + */ + pInB = pSrcBT + numRowsB * (numColsB - 1); + pInA = pSrcA->pData + i; + + pSrcAVec = (q7_t const *) pInA; + pSrcBVec = (q7_t const *) pInB; + + acc0 = 0LL; + blkCnt = (numColsA) >> 4; + while (blkCnt > 0U) + { + vecA = vld1q(pSrcAVec); + pSrcAVec += 16; + vecB = vld1q(pSrcBVec); + pSrcBVec += 16; + acc0 = vmladavaq_s8(acc0, vecA, vecB); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numColsA & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + acc0 = vmladavaq_p_s8(acc0, vecA, vecB, p0); + } + + *px = (q7_t) __SSAT(acc0 >> 7, 8); + + px += numColsB; + + i += numColsA; + /* + * Decrement the row loop counter + */ + row--; + } + } + + if (numRowsA & 1u) + { + col = numColsB; + i = 0u; + /* + * point to last row in output matrix + */ + px = pDst->pData + (numColsB) * (numRowsA - 1); + /* + * col loop + */ + while (col > 0) + { + q7_t const *pSrcAVec, *pSrcBVec; + q7x16_t vecA, vecB; + q63_t acc0; + + /* + * point to last row in matrix A + */ + pInA = pSrcA->pData + (numRowsA - 1) * numColsA; + pInB = pSrcBT + i; + + /* + * Set the variable sum, that acts as accumulator, to zero + */ + pSrcAVec = (q7_t const *) pInA; + pSrcBVec = (q7_t const *) pInB; + acc0 = 0LL; + + blkCnt = (numColsA) >> 4; + while (blkCnt > 0U) + { + vecA = vld1q(pSrcAVec); + pSrcAVec += 16; + vecB = vld1q(pSrcBVec); + pSrcBVec += 16; + acc0 = vmladavaq_s8(acc0, vecA, vecB); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numColsA & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + acc0 = vmladavaq_p_s8(acc0, vecA, vecB, p0); + } + + *px++ = (q7_t) __SSAT(acc0 >> 7, 8); + + i += numColsA; + + /* + * Decrement the col loop counter + */ + col--; + } + } + /* + * Return to application + */ + status = ARM_MATH_SUCCESS; + } + return(status); +} +#else +arm_status arm_mat_mult_q7(const arm_matrix_instance_q7 *pSrcA, const arm_matrix_instance_q7 *pSrcB, arm_matrix_instance_q7 *pDst, q7_t *pState) +{ + q31_t sum; /* accumulator */ + q7_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */ + q7_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */ + q7_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q7 type */ + q7_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q7 type */ + q7_t *pOut = pDst->pData; /* output data matrix pointer */ + q7_t *px; /* Temporary output data matrix pointer */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t col, i = 0U, row = numRowsA, colCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + + (void)pState; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initiate the pointer pIn1 to point to the starting address of pSrcA */ + pIn1 = pInA; + + /* Matrix A columns number of MAC operations are to be performed */ + colCnt = numColsA; + + /* matrix multiplication */ + while (colCnt > 0U) { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */ + /* Perform the multiply-accumulates */ + sum += (q31_t)*pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement the loop counter */ + colCnt--; + } + + /* Convert the result from 34.30 to 1.15 format and store the saturated value in destination buffer */ + /* Saturate and store the result in the destination buffer */ + *px++ = (q7_t)__SSAT((sum >> 7), 8); + + /* Decrement the column loop counter */ + col--; + + /* Update the pointer pIn2 to point to the starting address of the next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update the pointer pSrcA to point to the starting address of the next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement the row loop counter */ + row--; + + } while (row > 0U); + + /* set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f16.c new file mode 100644 index 00000000..fc2193d6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f16.c @@ -0,0 +1,208 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_scale_f16.c + * Description: Multiplies a floating-point matrix by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixScale + @{ + */ + +/** + @brief Floating-point matrix scaling. + @param[in] pSrc points to input matrix + @param[in] scale scale factor to be applied + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_scale_f16( + const arm_matrix_instance_f16 * pSrc, + float16_t scale, + arm_matrix_instance_f16 * pDst) +{ + arm_status status; /* status of matrix scaling */ + #ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + float16_t *pIn = pSrc->pData; /* input data matrix pointer */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + f16x8_t vecIn, vecOut, vecScale; + float16_t const *pInVec; + + pInVec = (float16_t const *) pIn; + + vecScale = vdupq_n_f16(scale); + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + blkCnt = numSamples >> 3; + while (blkCnt > 0U) + { + /* + * C(m,n) = A(m,n) * scale + * Scaling and results are stored in the destination buffer. + */ + vecIn = vld1q(pInVec); + pInVec += 8; + + vecOut = vmulq_f16(vecIn, vecScale); + + vst1q(pOut, vecOut); + pOut += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecIn = vld1q(pInVec); + vecOut = vecIn * scale; + + vstrhq_p(pOut, vecOut, p0); + } + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +} +#else + +arm_status arm_mat_scale_f16( + const arm_matrix_instance_f16 * pSrc, + float16_t scale, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pIn = pSrc->pData; /* Input data matrix pointer */ + float16_t *pOut = pDst->pData; /* Output data matrix pointer */ + uint32_t numSamples; /* Total number of elements in the matrix */ + uint32_t blkCnt; /* Loop counters */ + arm_status status; /* Status of matrix scaling */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + + /* Scale and store result in destination buffer. */ + *pOut++ = (_Float16)(*pIn++) * (_Float16)scale; + *pOut++ = (_Float16)(*pIn++) * (_Float16)scale; + *pOut++ = (_Float16)(*pIn++) * (_Float16)scale; + *pOut++ = (_Float16)(*pIn++) * (_Float16)scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + + /* Scale and store result in destination buffer. */ + *pOut++ = (_Float16)(*pIn++) * (_Float16)scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixScale group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c new file mode 100644 index 00000000..daebbb34 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c @@ -0,0 +1,287 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_scale_f32.c + * Description: Multiplies a floating-point matrix by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixScale Matrix Scale + + Multiplies a matrix by a scalar. This is accomplished by multiplying each element in the + matrix by the scalar. For example: + \image html MatrixScale.gif "Matrix Scaling of a 3 x 3 matrix" + + The function checks to make sure that the input and output matrices are of the same size. + + In the fixed-point Q15 and Q31 functions, scale is represented by + a fractional multiplication scaleFract and an arithmetic shift shift. + The shift allows the gain of the scaling operation to exceed 1.0. + The overall scale factor applied to the fixed-point data is +
+      scale = scaleFract * 2^shift.
+  
+ */ + +/** + @addtogroup MatrixScale + @{ + */ + +/** + @brief Floating-point matrix scaling. + @param[in] pSrc points to input matrix + @param[in] scale scale factor to be applied + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst) +{ + arm_status status; /* status of matrix scaling */ + #ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + f32x4_t vecIn, vecOut; + float32_t const *pInVec; + + pInVec = (float32_t const *) pIn; + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + blkCnt = numSamples >> 2; + while (blkCnt > 0U) + { + /* + * C(m,n) = A(m,n) * scale + * Scaling and results are stored in the destination buffer. + */ + vecIn = vld1q(pInVec); + pInVec += 4; + + vecOut = vecIn * scale; + + vst1q(pOut, vecOut); + pOut += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecIn = vld1q(pInVec); + vecOut = vecIn * scale; + + vstrwq_p(pOut, vecOut, p0); + } + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +} +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix scaling */ + + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + float32x4_t vec1; + float32x4_t res; + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + + blkCnt = numSamples >> 2; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + /* Scaling and results are stored in the destination buffer. */ + vec1 = vld1q_f32(pIn); + res = vmulq_f32(vec1, vdupq_n_f32(scale)); + vst1q_f32(pOut, res); + + /* update pointers to process next sampels */ + pIn += 4U; + pOut += 4U; + + /* Decrement the numSamples loop counter */ + blkCnt--; + } + + /* If the numSamples is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = numSamples % 0x4U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + /* The results are stored in the destination buffer. */ + *pOut++ = (*pIn++) * scale; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* Input data matrix pointer */ + float32_t *pOut = pDst->pData; /* Output data matrix pointer */ + uint32_t numSamples; /* Total number of elements in the matrix */ + uint32_t blkCnt; /* Loop counters */ + arm_status status; /* Status of matrix scaling */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + + /* Scale and store result in destination buffer. */ + *pOut++ = (*pIn++) * scale; + *pOut++ = (*pIn++) * scale; + *pOut++ = (*pIn++) * scale; + *pOut++ = (*pIn++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + + /* Scale and store result in destination buffer. */ + *pOut++ = (*pIn++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixScale group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c new file mode 100644 index 00000000..e43de0ac --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c @@ -0,0 +1,249 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_scale_q15.c + * Description: Multiplies a Q15 matrix by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixScale + @{ + */ + +/** + @brief Q15 matrix scaling. + @param[in] pSrc points to input matrix + @param[in] scaleFract fractional portion of the scale factor + @param[in] shift number of bits to shift the result by + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.15 format. + These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst) +{ + arm_status status; /* Status of matrix scaling */ + q15_t *pIn = pSrc->pData; /* input data matrix pointer */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecIn, vecOut; + q15_t const *pInVec; + int32_t totShift = shift + 1; /* shift to apply after scaling */ + + pInVec = (q15_t const *) pIn; + + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + blkCnt = numSamples >> 3; + while (blkCnt > 0U) + { + /* + * C(m,n) = A(m,n) * scale + * Scaling and results are stored in the destination buffer. + */ + vecIn = vld1q(pInVec); pInVec += 8; + + /* multiply input with scaler value */ + vecOut = vmulhq(vecIn, vdupq_n_s16(scaleFract)); + /* apply shifting */ + vecOut = vqshlq_r(vecOut, totShift); + + vst1q(pOut, vecOut); pOut += 8; + + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numSamples & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecIn = vld1q(pInVec); pInVec += 8; + vecOut = vmulhq(vecIn, vdupq_n_s16(scaleFract)); + vecOut = vqshlq_r(vecOut, totShift); + vstrhq_p(pOut, vecOut, p0); + } + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pIn = pSrc->pData; /* Input data matrix pointer */ + q15_t *pOut = pDst->pData; /* Output data matrix pointer */ + uint32_t numSamples; /* Total number of elements in the matrix */ + uint32_t blkCnt; /* Loop counter */ + arm_status status; /* Status of matrix scaling */ + int32_t kShift = 15 - shift; /* Total shift to apply after scaling */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t inA1, inA2; + q31_t out1, out2, out3, out4; /* Temporary output variables */ + q15_t in1, in2, in3, in4; /* Temporary input variables */ +#endif + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * k */ + +#if defined (ARM_MATH_DSP) + /* read 2 times 2 samples at a time from source */ + inA1 = read_q15x2_ia (&pIn); + inA2 = read_q15x2_ia (&pIn); + + /* Scale inputs and store result in temporary variables + * in single cycle by packing the outputs */ + out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract); + out2 = (q31_t) ((q15_t) (inA1 ) * scaleFract); + out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract); + out4 = (q31_t) ((q15_t) (inA2 ) * scaleFract); + + /* apply shifting */ + out1 = out1 >> kShift; + out2 = out2 >> kShift; + out3 = out3 >> kShift; + out4 = out4 >> kShift; + + /* saturate the output */ + in1 = (q15_t) (__SSAT(out1, 16)); + in2 = (q15_t) (__SSAT(out2, 16)); + in3 = (q15_t) (__SSAT(out3, 16)); + in4 = (q15_t) (__SSAT(out4, 16)); + + /* store result to destination */ + write_q15x2_ia (&pOut, __PKHBT(in2, in1, 16)); + write_q15x2_ia (&pOut, __PKHBT(in4, in3, 16)); + +#else + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * k */ + + /* Scale, saturate and store result in destination buffer. */ + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixScale group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c new file mode 100644 index 00000000..33c08680 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c @@ -0,0 +1,242 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_scale_q31.c + * Description: Multiplies a Q31 matrix by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixScale + @{ + */ + +/** + @brief Q31 matrix scaling. + @param[in] pSrc points to input matrix + @param[in] scaleFract fractional portion of the scale factor + @param[in] shift number of bits to shift the result by + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.31 format. + These are multiplied to yield a 2.62 intermediate result which is shifted with saturation to 1.31 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pIn = pSrc->pData; /* input data matrix pointer */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecIn, vecOut; + q31_t const *pInVec; + int32_t totShift = shift + 1; /* shift to apply after scaling */ + arm_status status; /* Status of matrix scaling */ + + pInVec = (q31_t const *) pIn; + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + blkCnt = numSamples >> 2; + while (blkCnt > 0U) + { + /* + * C(m,n) = A(m,n) * scale + * Scaling and results are stored in the destination buffer. + */ + vecIn = vld1q(pInVec); + pInVec += 4; + /* multiply input with scaler value */ + vecOut = vmulhq(vecIn, vdupq_n_s32(scaleFract)); + /* apply shifting */ + vecOut = vqshlq_r(vecOut, totShift); + + vst1q(pOut, vecOut); + pOut += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecIn = vld1q(pInVec); + pInVec += 4; + vecOut = vmulhq(vecIn, vdupq_n_s32(scaleFract)); + vecOut = vqshlq_r(vecOut, totShift); + vstrwq_p(pOut, vecOut, p0); + } + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pIn = pSrc->pData; /* Input data matrix pointer */ + q31_t *pOut = pDst->pData; /* Output data matrix pointer */ + uint32_t numSamples; /* Total number of elements in the matrix */ + uint32_t blkCnt; /* Loop counter */ + arm_status status; /* Status of matrix scaling */ + int32_t kShift = shift + 1; /* Shift to apply after scaling */ + q31_t in, out; /* Temporary variabels */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * k */ + + /* Scale, saturate and store result in destination buffer. */ + in = *pIn++; /* read four inputs from source */ + in = ((q63_t) in * scaleFract) >> 32; /* multiply input with scaler value */ + out = in << kShift; /* apply shifting */ + if (in != (out >> kShift)) /* saturate the results. */ + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; /* Store result destination */ + + in = *pIn++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; + + in = *pIn++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; + + in = *pIn++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * k */ + + /* Scale, saturate and store result in destination buffer. */ + in = *pIn++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixScale group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f16.c new file mode 100644 index 00000000..8dafc143 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f16.c @@ -0,0 +1,234 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_solve_lower_triangular_f16.c + * Description: Solve linear system LT X = A with LT lower triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + arm_status arm_mat_solve_lower_triangular_f16( + const arm_matrix_instance_f16 * lt, + const arm_matrix_instance_f16 * a, + arm_matrix_instance_f16 * dst) + { + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((lt->numRows != lt->numCols) || + (lt->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float16_t *pX = dst->pData; + float16_t *pLT = lt->pData; + float16_t *pA = a->pData; + + float16_t *lt_row; + float16_t *a_col; + + _Float16 invLT; + + f16x8_t vecA; + f16x8_t vecX; + + for(i=0; i < n ; i++) + { + + for(j=0; j+7 < cols; j += 8) + { + vecA = vld1q_f16(&pA[i * cols + j]); + + for(k=0; k < i; k++) + { + vecX = vld1q_f16(&pX[cols*k+j]); + vecA = vfmsq(vecA,vdupq_n_f16(pLT[n*i + k]),vecX); + } + + if ((_Float16)pLT[n*i + i]==0.0f16) + { + return(ARM_MATH_SINGULAR); + } + + invLT = 1.0f16 / (_Float16)pLT[n*i + i]; + vecA = vmulq(vecA,vdupq_n_f16(invLT)); + vst1q(&pX[i*cols+j],vecA); + + } + + for(; j < cols; j ++) + { + a_col = &pA[j]; + lt_row = &pLT[n*i]; + + _Float16 tmp=a_col[i * cols]; + + for(k=0; k < i; k++) + { + tmp -= (_Float16)lt_row[k] * (_Float16)pX[cols*k+j]; + } + + if ((_Float16)lt_row[i]==0.0f16) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / (_Float16)lt_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} + +#else + arm_status arm_mat_solve_lower_triangular_f16( + const arm_matrix_instance_f16 * lt, + const arm_matrix_instance_f16 * a, + arm_matrix_instance_f16 * dst) + { + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((lt->numRows != lt->numCols) || + (lt->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float16_t *pX = dst->pData; + float16_t *pLT = lt->pData; + float16_t *pA = a->pData; + + float16_t *lt_row; + float16_t *a_col; + + for(j=0; j < cols; j ++) + { + a_col = &pA[j]; + + for(i=0; i < n ; i++) + { + lt_row = &pLT[n*i]; + + float16_t tmp=a_col[i * cols]; + + for(k=0; k < i; k++) + { + tmp -= (_Float16)lt_row[k] * (_Float16)pX[cols*k+j]; + } + + if ((_Float16)lt_row[i]==0.0f16) + { + return(ARM_MATH_SINGULAR); + } + tmp = (_Float16)tmp / (_Float16)lt_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixInv group + */ +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f32.c new file mode 100644 index 00000000..c7cdecc3 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f32.c @@ -0,0 +1,333 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_solve_lower_triangular_f32.c + * Description: Solve linear system LT X = A with LT lower triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + arm_status arm_mat_solve_lower_triangular_f32( + const arm_matrix_instance_f32 * lt, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst) + { + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((lt->numRows != lt->numCols) || + (lt->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float32_t *pX = dst->pData; + float32_t *pLT = lt->pData; + float32_t *pA = a->pData; + + float32_t *lt_row; + float32_t *a_col; + + float32_t invLT; + + f32x4_t vecA; + f32x4_t vecX; + + for(i=0; i < n ; i++) + { + + for(j=0; j+3 < cols; j += 4) + { + vecA = vld1q_f32(&pA[i * cols + j]); + + for(k=0; k < i; k++) + { + vecX = vld1q_f32(&pX[cols*k+j]); + vecA = vfmsq(vecA,vdupq_n_f32(pLT[n*i + k]),vecX); + } + + if (pLT[n*i + i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + + invLT = 1.0f / pLT[n*i + i]; + vecA = vmulq(vecA,vdupq_n_f32(invLT)); + vst1q(&pX[i*cols+j],vecA); + + } + + for(; j < cols; j ++) + { + a_col = &pA[j]; + lt_row = &pLT[n*i]; + + float32_t tmp=a_col[i * cols]; + + for(k=0; k < i; k++) + { + tmp -= lt_row[k] * pX[cols*k+j]; + } + + if (lt_row[i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / lt_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + arm_status arm_mat_solve_lower_triangular_f32( + const arm_matrix_instance_f32 * lt, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst) + { + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((lt->numRows != lt->numCols) || + (lt->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float32_t *pX = dst->pData; + float32_t *pLT = lt->pData; + float32_t *pA = a->pData; + + float32_t *lt_row; + float32_t *a_col; + + float32_t invLT; + + f32x4_t vecA; + f32x4_t vecX; + + for(i=0; i < n ; i++) + { + + for(j=0; j+3 < cols; j += 4) + { + vecA = vld1q_f32(&pA[i * cols + j]); + + for(k=0; k < i; k++) + { + vecX = vld1q_f32(&pX[cols*k+j]); + vecA = vfmsq_f32(vecA,vdupq_n_f32(pLT[n*i + k]),vecX); + } + + if (pLT[n*i + i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + + invLT = 1.0f / pLT[n*i + i]; + vecA = vmulq_f32(vecA,vdupq_n_f32(invLT)); + vst1q_f32(&pX[i*cols+j],vecA); + + } + + for(; j < cols; j ++) + { + a_col = &pA[j]; + lt_row = &pLT[n*i]; + + float32_t tmp=a_col[i * cols]; + + for(k=0; k < i; k++) + { + tmp -= lt_row[k] * pX[cols*k+j]; + } + + if (lt_row[i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / lt_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} +#else + arm_status arm_mat_solve_lower_triangular_f32( + const arm_matrix_instance_f32 * lt, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst) + { + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((lt->numRows != lt->numCols) || + (lt->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n,cols; + + float32_t *pX = dst->pData; + float32_t *pLT = lt->pData; + float32_t *pA = a->pData; + + float32_t *lt_row; + float32_t *a_col; + + n = dst->numRows; + cols = dst -> numCols; + + + for(j=0; j < cols; j ++) + { + a_col = &pA[j]; + + for(i=0; i < n ; i++) + { + float32_t tmp=a_col[i * cols]; + + lt_row = &pLT[n*i]; + + for(k=0; k < i; k++) + { + tmp -= lt_row[k] * pX[cols*k+j]; + } + + if (lt_row[i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / lt_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixInv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f64.c new file mode 100644 index 00000000..d54ff679 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f64.c @@ -0,0 +1,124 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_solve_lower_triangular_f64.c + * Description: Solve linear system LT X = A with LT lower triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_lower_triangular_f64( + const arm_matrix_instance_f64 * lt, + const arm_matrix_instance_f64 * a, + arm_matrix_instance_f64 * dst) + { + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((lt->numRows != lt->numCols) || + (lt->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n,cols; + + float64_t *pX = dst->pData; + float64_t *pLT = lt->pData; + float64_t *pA = a->pData; + + float64_t *lt_row; + float64_t *a_col; + + n = dst->numRows; + cols = dst->numCols; + + for(j=0; j < cols; j ++) + { + a_col = &pA[j]; + + for(i=0; i < n ; i++) + { + float64_t tmp=a_col[i * cols]; + + lt_row = &pLT[n*i]; + + for(k=0; k < i; k++) + { + tmp -= lt_row[k] * pX[cols*k+j]; + } + + if (lt_row[i]==0.0) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / lt_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} +/** + @} end of MatrixInv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f16.c new file mode 100644 index 00000000..332280f0 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f16.c @@ -0,0 +1,226 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_solve_upper_triangular_f16.c + * Description: Solve linear system UT X = A with UT upper triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + +/** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + arm_status arm_mat_solve_upper_triangular_f16( + const arm_matrix_instance_f16 * ut, + const arm_matrix_instance_f16 * a, + arm_matrix_instance_f16 * dst) + { +arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((ut->numRows != ut->numCols) || + (ut->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float16_t *pX = dst->pData; + float16_t *pUT = ut->pData; + float16_t *pA = a->pData; + + float16_t *ut_row; + float16_t *a_col; + + _Float16 invUT; + + f16x8_t vecA; + f16x8_t vecX; + + for(i=n-1; i >= 0 ; i--) + { + for(j=0; j+7 < cols; j +=8) + { + vecA = vld1q_f16(&pA[i * cols + j]); + + for(k=n-1; k > i; k--) + { + vecX = vld1q_f16(&pX[cols*k+j]); + vecA = vfmsq(vecA,vdupq_n_f16(pUT[n*i + k]),vecX); + } + + if ((_Float16)pUT[n*i + i]==0.0f16) + { + return(ARM_MATH_SINGULAR); + } + + invUT = 1.0f16 / (_Float16)pUT[n*i + i]; + vecA = vmulq(vecA,vdupq_n_f16(invUT)); + + + vst1q(&pX[i*cols+j],vecA); + } + + for(; j < cols; j ++) + { + a_col = &pA[j]; + + ut_row = &pUT[n*i]; + + _Float16 tmp=a_col[i * cols]; + + for(k=n-1; k > i; k--) + { + tmp -= (_Float16)ut_row[k] * (_Float16)pX[cols*k+j]; + } + + if ((_Float16)ut_row[i]==0.0f16) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / (_Float16)ut_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#else + arm_status arm_mat_solve_upper_triangular_f16( + const arm_matrix_instance_f16 * ut, + const arm_matrix_instance_f16 * a, + arm_matrix_instance_f16 * dst) + { +arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((ut->numRows != ut->numCols) || + (ut->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float16_t *pX = dst->pData; + float16_t *pUT = ut->pData; + float16_t *pA = a->pData; + + float16_t *ut_row; + float16_t *a_col; + + for(j=0; j < cols; j ++) + { + a_col = &pA[j]; + + for(i=n-1; i >= 0 ; i--) + { + ut_row = &pUT[n*i]; + + float16_t tmp=a_col[i * cols]; + + for(k=n-1; k > i; k--) + { + tmp -= (_Float16)ut_row[k] * (_Float16)pX[cols*k+j]; + } + + if ((_Float16)ut_row[i]==0.0f16) + { + return(ARM_MATH_SINGULAR); + } + tmp = (_Float16)tmp / (_Float16)ut_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixInv group + */ +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f32.c new file mode 100644 index 00000000..f58dfbd9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f32.c @@ -0,0 +1,319 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_solve_upper_triangular_f32.c + * Description: Solve linear system UT X = A with UT upper triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + +/** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + arm_status arm_mat_solve_upper_triangular_f32( + const arm_matrix_instance_f32 * ut, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst) + { +arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((ut->numRows != ut->numCols) || + (ut->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float32_t *pX = dst->pData; + float32_t *pUT = ut->pData; + float32_t *pA = a->pData; + + float32_t *ut_row; + float32_t *a_col; + + float32_t invUT; + + f32x4_t vecA; + f32x4_t vecX; + + for(i=n-1; i >= 0 ; i--) + { + for(j=0; j+3 < cols; j +=4) + { + vecA = vld1q_f32(&pA[i * cols + j]); + + for(k=n-1; k > i; k--) + { + vecX = vld1q_f32(&pX[cols*k+j]); + vecA = vfmsq(vecA,vdupq_n_f32(pUT[n*i + k]),vecX); + } + + if (pUT[n*i + i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + + invUT = 1.0f / pUT[n*i + i]; + vecA = vmulq(vecA,vdupq_n_f32(invUT)); + + + vst1q(&pX[i*cols+j],vecA); + } + + for(; j < cols; j ++) + { + a_col = &pA[j]; + + ut_row = &pUT[n*i]; + + float32_t tmp=a_col[i * cols]; + + for(k=n-1; k > i; k--) + { + tmp -= ut_row[k] * pX[cols*k+j]; + } + + if (ut_row[i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / ut_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + arm_status arm_mat_solve_upper_triangular_f32( + const arm_matrix_instance_f32 * ut, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst) + { +arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((ut->numRows != ut->numCols) || + (ut->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float32_t *pX = dst->pData; + float32_t *pUT = ut->pData; + float32_t *pA = a->pData; + + float32_t *ut_row; + float32_t *a_col; + + float32_t invUT; + + f32x4_t vecA; + f32x4_t vecX; + + for(i=n-1; i >= 0 ; i--) + { + for(j=0; j+3 < cols; j +=4) + { + vecA = vld1q_f32(&pA[i * cols + j]); + + for(k=n-1; k > i; k--) + { + vecX = vld1q_f32(&pX[cols*k+j]); + vecA = vfmsq_f32(vecA,vdupq_n_f32(pUT[n*i + k]),vecX); + } + + if (pUT[n*i + i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + + invUT = 1.0f / pUT[n*i + i]; + vecA = vmulq_f32(vecA,vdupq_n_f32(invUT)); + + + vst1q_f32(&pX[i*cols+j],vecA); + } + + for(; j < cols; j ++) + { + a_col = &pA[j]; + + ut_row = &pUT[n*i]; + + float32_t tmp=a_col[i * cols]; + + for(k=n-1; k > i; k--) + { + tmp -= ut_row[k] * pX[cols*k+j]; + } + + if (ut_row[i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / ut_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#else + arm_status arm_mat_solve_upper_triangular_f32( + const arm_matrix_instance_f32 * ut, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst) + { +arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((ut->numRows != ut->numCols) || + (ut->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + int i,j,k,n,cols; + + float32_t *pX = dst->pData; + float32_t *pUT = ut->pData; + float32_t *pA = a->pData; + + float32_t *ut_row; + float32_t *a_col; + + n = dst->numRows; + cols = dst->numCols; + + for(j=0; j < cols; j ++) + { + a_col = &pA[j]; + + for(i=n-1; i >= 0 ; i--) + { + float32_t tmp=a_col[i * cols]; + + ut_row = &pUT[n*i]; + + for(k=n-1; k > i; k--) + { + tmp -= ut_row[k] * pX[cols*k+j]; + } + + if (ut_row[i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / ut_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixInv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f64.c new file mode 100644 index 00000000..248273d4 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f64.c @@ -0,0 +1,120 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_solve_upper_triangular_f64.c + * Description: Solve linear system UT X = A with UT upper triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + +/** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_upper_triangular_f64( + const arm_matrix_instance_f64 * ut, + const arm_matrix_instance_f64 * a, + arm_matrix_instance_f64 * dst) + { +arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((ut->numRows != ut->numCols) || + (ut->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + int i,j,k,n,cols; + + float64_t *pX = dst->pData; + float64_t *pUT = ut->pData; + float64_t *pA = a->pData; + + float64_t *ut_row; + float64_t *a_col; + + n = dst->numRows; + cols = dst->numCols; + + for(j=0; j < cols; j ++) + { + a_col = &pA[j]; + + for(i=n-1; i >= 0 ; i--) + { + float64_t tmp=a_col[i * cols]; + + ut_row = &pUT[n*i]; + + for(k=n-1; k > i; k--) + { + tmp -= ut_row[k] * pX[cols*k+j]; + } + + if (ut_row[i]==0.0) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / ut_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + + +/** + @} end of MatrixInv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f16.c new file mode 100644 index 00000000..13291b8c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f16.c @@ -0,0 +1,215 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_sub_f16.c + * Description: Floating-point matrix subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Floating-point matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_sub_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + arm_status status; /* status of matrix subtraction */ + uint32_t numSamples; /* total number of elements in the matrix */ + float16_t *pDataA, *pDataB, *pDataDst; + f16x8_t vecA, vecB, vecDst; + float16_t const *pSrcAVec; + float16_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (float16_t const *) pDataA; + pSrcBVec = (float16_t const *) pDataB; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 3; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* sub and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + vecB = vld1q(pSrcBVec); + pSrcBVec += 8; + vecDst = vsubq(vecA, vecB); + vst1q(pDataDst, vecDst); + pDataDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numSamples & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + vecDst = vsubq_m(vecDst, vecA, vecB, p0); + vstrhq_p(pDataDst, vecDst, p0); + } + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else + +arm_status arm_mat_sub_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float16_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (_Float16)(*pInA++) - (_Float16)(*pInB++); + *pOut++ = (_Float16)(*pInA++) - (_Float16)(*pInB++); + *pOut++ = (_Float16)(*pInA++) - (_Float16)(*pInB++); + *pOut++ = (_Float16)(*pInA++) - (_Float16)(*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (_Float16)(*pInA++) - (_Float16)(*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixSub group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c new file mode 100644 index 00000000..e9a17d1b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c @@ -0,0 +1,298 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_sub_f32.c + * Description: Floating-point matrix subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixSub Matrix Subtraction + + Subtract two matrices. + \image html MatrixSubtraction.gif "Subraction of two 3 x 3 matrices" + + The functions check to make sure that + pSrcA, pSrcB, and pDst have the same + number of rows and columns. + */ + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Floating-point matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + arm_status status; /* status of matrix subtraction */ + uint32_t numSamples; /* total number of elements in the matrix */ + float32_t *pDataA, *pDataB, *pDataDst; + f32x4_t vecA, vecB, vecDst; + float32_t const *pSrcAVec; + float32_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (float32_t const *) pDataA; + pSrcBVec = (float32_t const *) pDataB; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 2; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* sub and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + vecDst = vsubq(vecA, vecB); + vst1q(pDataDst, vecDst); + pDataDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numSamples & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + vecDst = vsubq_m(vecDst, vecA, vecB, p0); + vstrwq_p(pDataDst, vecDst, p0); + } + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +#if defined(ARM_MATH_NEON) +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + float32x4_t vec1; + float32x4_t vec2; + float32x4_t res; + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + + blkCnt = numSamples >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + /* Subtract and then store the results in the destination buffer. */ + /* Read values from source A */ + vec1 = vld1q_f32(pIn1); + vec2 = vld1q_f32(pIn2); + res = vsubq_f32(vec1, vec2); + vst1q_f32(pOut, res); + + /* Update pointers to process next samples */ + pIn1 += 4U; + pIn2 += 4U; + pOut += 4U; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the numSamples is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = numSamples % 0x4U; + + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + /* Subtract and then store the results in the destination buffer. */ + *pOut++ = (*pIn1++) - (*pIn2++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (*pInA++) - (*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixSub group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f64.c new file mode 100644 index 00000000..245a76d0 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f64.c @@ -0,0 +1,143 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_sub_f64.c + * Description: Floating-point matrix subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixSub Matrix Subtraction + + Subtract two matrices. + \image html MatrixSubtraction.gif "Subraction of two 3 x 3 matrices" + + The functions check to make sure that + pSrcA, pSrcB, and pDst have the same + number of rows and columns. + */ + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Floating-point matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +arm_status arm_mat_sub_f64( + const arm_matrix_instance_f64 * pSrcA, + const arm_matrix_instance_f64 * pSrcB, + arm_matrix_instance_f64 * pDst) +{ + float64_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float64_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float64_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint64_t numSamples; /* total number of elements in the matrix */ + uint64_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint64_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (*pInA++) - (*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixSub group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c new file mode 100644 index 00000000..c3799969 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c @@ -0,0 +1,219 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_sub_q15.c + * Description: Q15 Matrix subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Q15 matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + uint32_t numSamples; /* total number of elements in the matrix */ + q15_t *pDataA, *pDataB, *pDataDst; + q15x8_t vecA, vecB, vecDst; + q15_t const *pSrcAVec; + q15_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (q15_t const *) pDataA; + pSrcBVec = (q15_t const *) pDataB; + + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 3; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* sub and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); pSrcAVec += 8; + vecB = vld1q(pSrcBVec); pSrcBVec += 8; + vecDst = vqsubq(vecA, vecB); + vst1q(pDataDst, vecDst); pDataDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcAVec); pSrcAVec += 8; + vecB = vld1q(pSrcBVec); pSrcBVec += 8; + vecDst = vqsubq_m(vecDst, vecA, vecB, p0); + vstrhq_p(pDataDst, vecDst, p0); + } + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract, Saturate and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + write_q15x2_ia (&pOut, __QSUB16(read_q15x2_ia (&pInA), read_q15x2_ia (&pInB))); + write_q15x2_ia (&pOut, __QSUB16(read_q15x2_ia (&pInA), read_q15x2_ia (&pInB))); +#else + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pOut++ = (q15_t) __QSUB16(*pInA++, *pInB++); +#else + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixSub group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c new file mode 100644 index 00000000..5045b298 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c @@ -0,0 +1,218 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_sub_q31.c + * Description: Q31 matrix subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Q31 matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + uint32_t numSamples; /* total number of elements in the matrix */ + q31_t *pDataA, *pDataB, *pDataDst; + q31x4_t vecA, vecB, vecDst; + q31_t const *pSrcAVec; + q31_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (q31_t const *) pDataA; + pSrcBVec = (q31_t const *) pDataB; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 2; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* sub and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + vecDst = vqsubq(vecA, vecB); + vst1q(pDataDst, vecDst); + pDataDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + vecDst = vqsubq_m(vecDst, vecA, vecB, p0); + vstrwq_p(pDataDst, vecDst, p0); + } + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract, saturate and then store the results in the destination buffer. */ + *pOut++ = __QSUB(*pInA++, *pInB++); + + *pOut++ = __QSUB(*pInA++, *pInB++); + + *pOut++ = __QSUB(*pInA++, *pInB++); + + *pOut++ = __QSUB(*pInA++, *pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract, saturate and store result in destination buffer. */ + *pOut++ = __QSUB(*pInA++, *pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixSub group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f16.c new file mode 100644 index 00000000..8a41ccbc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f16.c @@ -0,0 +1,202 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_trans_f16.c + * Description: Floating-point matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Floating-point matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +arm_status arm_mat_trans_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst) +{ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + if (pDst->numRows == pDst->numCols) + { + if (pDst->numCols == 1) + { + pDst->pData[0] = pSrc->pData[0]; + return(ARM_MATH_SUCCESS); + } + if (pDst->numCols == 2) + return arm_mat_trans_16bit_2x2((uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + if (pDst->numCols == 3) + return arm_mat_trans_16bit_3x3_mve((uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + if (pDst->numCols == 4) + return arm_mat_trans_16bit_4x4_mve((uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + } + + arm_mat_trans_16bit_generic(pSrc->numRows, pSrc->numCols, (uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else + +arm_status arm_mat_trans_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pIn = pSrc->pData; /* input data matrix pointer */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + float16_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint32_t col, row = nRows, i = 0U; /* Loop counters */ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer px is set to starting address of column being processed */ + px = pOut + i; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { + /* Read and store input element in destination */ + *px = *pIn++; + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pIn++; + + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixTrans group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c new file mode 100644 index 00000000..b4116630 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c @@ -0,0 +1,325 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_trans_f32.c + * Description: Floating-point matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixTrans Matrix Transpose + + Tranposes a matrix. + + Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix. + \image html MatrixTranspose.gif "Transpose of a 3 x 3 matrix" + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Floating-point matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + if (pDst->numRows == pDst->numCols) + { + if (pDst->numCols == 2) + return arm_mat_trans_32bit_2x2_mve((uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + if (pDst->numCols == 3) + return arm_mat_trans_32bit_3x3_mve((uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + if (pDst->numCols == 4) + return arm_mat_trans_32bit_4x4_mve((uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + } + + arm_mat_trans_32bit_generic_mve(pSrc->numRows, pSrc->numCols, (uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +#if defined(ARM_MATH_NEON) + +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nColumns = pSrc->numCols; /* number of columns */ + + uint16_t blkCnt, rowCnt, i = 0U, row = nRows; /* loop counters */ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* Row loop */ + rowCnt = row >> 2; + while (rowCnt > 0U) + { + float32x4_t row0V,row1V,row2V,row3V; + float32x4x2_t ra0,ra1,rb0,rb1; + + blkCnt = nColumns >> 2; + + /* The pointer px is set to starting address of the column being processed */ + px = pOut + i; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) /* Column loop */ + { + row0V = vld1q_f32(pIn); + row1V = vld1q_f32(pIn + 1 * nColumns); + row2V = vld1q_f32(pIn + 2 * nColumns); + row3V = vld1q_f32(pIn + 3 * nColumns); + pIn += 4; + + ra0 = vzipq_f32(row0V,row2V); + ra1 = vzipq_f32(row1V,row3V); + + rb0 = vzipq_f32(ra0.val[0],ra1.val[0]); + rb1 = vzipq_f32(ra0.val[1],ra1.val[1]); + + vst1q_f32(px,rb0.val[0]); + px += nRows; + + vst1q_f32(px,rb0.val[1]); + px += nRows; + + vst1q_f32(px,rb1.val[0]); + px += nRows; + + vst1q_f32(px,rb1.val[1]); + px += nRows; + + /* Decrement the column loop counter */ + blkCnt--; + } + + /* Perform matrix transpose for last 3 samples here. */ + blkCnt = nColumns % 0x4U; + + while (blkCnt > 0U) + { + /* Read and store the input element in the destination */ + *px++ = *pIn; + *px++ = *(pIn + 1 * nColumns); + *px++ = *(pIn + 2 * nColumns); + *px++ = *(pIn + 3 * nColumns); + + px += (nRows - 4); + pIn++; + + /* Decrement the column loop counter */ + blkCnt--; + } + + i += 4; + pIn += 3 * nColumns; + + /* Decrement the row loop counter */ + rowCnt--; + + } /* Row loop end */ + + rowCnt = row & 3; + while (rowCnt > 0U) + { + blkCnt = nColumns ; + /* The pointer px is set to starting address of the column being processed */ + px = pOut + i; + + while (blkCnt > 0U) + { + /* Read and store the input element in the destination */ + *px = *pIn++; + + /* Update the pointer px to point to the next row of the transposed matrix */ + px += nRows; + + /* Decrement the column loop counter */ + blkCnt--; + } + i++; + rowCnt -- ; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint32_t col, row = nRows, i = 0U; /* Loop counters */ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer px is set to starting address of column being processed */ + px = pOut + i; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { + /* Read and store input element in destination */ + *px = *pIn++; + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pIn++; + + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixTrans group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f64.c new file mode 100644 index 00000000..57b5043f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f64.c @@ -0,0 +1,155 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_trans_f64.c + * Description: Floating-point matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixTrans Matrix Transpose + + Tranposes a matrix. + + Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix. + \image html MatrixTranspose.gif "Transpose of a 3 x 3 matrix" + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Floating-point matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +arm_status arm_mat_trans_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pDst) +{ + float64_t *pIn = pSrc->pData; /* input data matrix pointer */ + float64_t *pOut = pDst->pData; /* output data matrix pointer */ + float64_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint64_t col, row = nRows, i = 0U; /* Loop counters */ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer px is set to starting address of column being processed */ + px = pOut + i; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { + /* Read and store input element in destination */ + *px = *pIn++; + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pIn++; + + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + * @} end of MatrixTrans group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c new file mode 100644 index 00000000..e7409222 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c @@ -0,0 +1,233 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_trans_q15.c + * Description: Q15 matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Q15 matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + + +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst) +{ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + if (pDst->numRows == pDst->numCols) + { + if (pDst->numCols == 1) + { + pDst->pData[0] = pSrc->pData[0]; + return(ARM_MATH_SUCCESS); + } + if (pDst->numCols == 2) + return arm_mat_trans_16bit_2x2((uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + if (pDst->numCols == 3) + return arm_mat_trans_16bit_3x3_mve((uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + if (pDst->numCols == 4) + return arm_mat_trans_16bit_4x4_mve((uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + } + + arm_mat_trans_16bit_generic(pSrc->numRows, pSrc->numCols, (uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pIn = pSrc->pData; /* input data matrix pointer */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint32_t col, row = nRows, i = 0U; /* Loop counters */ + arm_status status; /* status of matrix transpose */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t in; /* variable to hold temporary output */ +#endif + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer pOut is set to starting address of column being processed */ + pOut = pDst->pData + i; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { + /* Read two elements from row */ + in = read_q15x2_ia (&pIn); + + /* Unpack and store one element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *pOut = (q15_t) in; +#else + *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Unpack and store second element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#else + *pOut = (q15_t) in; +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Read two elements from row */ + in = read_q15x2_ia (&pIn); + + /* Unpack and store one element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *pOut = (q15_t) in; +#else + *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Unpack and store second element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#else + *pOut = (q15_t) in; +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *pOut = *pIn++; + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixTrans group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c new file mode 100644 index 00000000..2c772547 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c @@ -0,0 +1,191 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_trans_q31.c + * Description: Q31 matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Q31 matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst) +{ + arm_status status; /* status of matrix transpose */ + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + if (pDst->numRows == pDst->numCols) + { + if (pDst->numCols == 2) + return arm_mat_trans_32bit_2x2_mve((uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + if (pDst->numCols == 3) + return arm_mat_trans_32bit_3x3_mve((uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + if (pDst->numCols == 4) + return arm_mat_trans_32bit_4x4_mve((uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + } + + arm_mat_trans_32bit_generic_mve(pSrc->numRows, pSrc->numCols, (uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pIn = pSrc->pData; /* input data matrix pointer */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint32_t col, row = nRows, i = 0U; /* Loop counters */ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer px is set to starting address of column being processed */ + px = pOut + i; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { + /* Read and store input element in destination */ + *px = *pIn++; + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pIn++; + + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixTrans group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q7.c new file mode 100644 index 00000000..a500d055 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q7.c @@ -0,0 +1,171 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_trans_q7.c + * Description: Q7 matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Q7 matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_trans_q7(const arm_matrix_instance_q7 *pSrc, arm_matrix_instance_q7 *pDst) +{ + + uint16x8_t vecOffs; + uint32_t i; + uint32_t blkCnt; + uint8_t const *pDataC; + uint8_t *pDataDestR; + uint16x8_t vecIn; + + const uint8_t * pDataSrc=(const uint8_t *)pSrc->pData; + uint8_t * pDataDst=(uint8_t *)pDst->pData; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + return ARM_MATH_SIZE_MISMATCH; + } +#endif + + vecOffs = vidupq_u16((uint32_t)0, 1); + vecOffs = vecOffs * pSrc->numCols; + + i = pSrc->numCols; + do + { + pDataC = (uint8_t const *) pDataSrc; + pDataDestR = (uint8_t*)pDataDst; + + blkCnt = pSrc->numRows >> 3; + while (blkCnt > 0U) + { + /* widened loads */ + vecIn = vldrbq_gather_offset_u16(pDataC, vecOffs); + vstrbq_u16(pDataDestR, vecIn); + pDataDestR += 8; + pDataC = pDataC + pSrc->numCols * 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = pSrc->numRows & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecIn = vldrbq_gather_offset_u16(pDataC, vecOffs); + vstrbq_p_u16(pDataDestR, vecIn, p0); + } + pDataSrc += 1; + pDataDst += pSrc->numRows; + } + while (--i); + + return (ARM_MATH_SUCCESS); +} +#else +arm_status arm_mat_trans_q7(const arm_matrix_instance_q7 *pSrc, arm_matrix_instance_q7 *pDst) +{ + q7_t *pSrcA = pSrc->pData; /* input data matrix pointer */ + q7_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of nRows */ + uint16_t nColumns = pSrc->numCols; /* number of nColumns */ + uint16_t col, row = nRows, i = 0U; /* row and column loop counters */ + arm_status status; /* status of matrix transpose */ + + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do { + /* The pointer pOut is set to starting address of the column being processed */ + pOut = pDst->pData + i; + + /* Initialize column loop counter */ + col = nColumns; + + + while (col > 0U) { + /* Read and store the input element in the destination */ + *pOut = *pSrcA++; + + /* Update the pointer pOut to point to the next row of the transposed matrix */ + pOut += nRows; + + /* Decrement the column loop counter */ + col--; + } + + i++; + + /* Decrement the row loop counter */ + row--; + + } while (row > 0U); + + /* set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + + +/** + @} end of MatrixTrans group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_f16.c new file mode 100644 index 00000000..f592f6fa --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_f16.c @@ -0,0 +1,396 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_vec_mult_f16.c + * Description: Floating-point matrix and vector multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + * @ingroup groupMatrix + */ + + +/** + * @addtogroup MatrixVectMult + * @{ + */ + +/** + * @brief Floating-point matrix and vector multiplication. + * @param[in] *pSrcMat points to the input matrix structure + * @param[in] *pVec points to input vector + * @param[out] *pDst points to output vector + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_mat_vec_mult_f16( + const arm_matrix_instance_f16 *pSrcMat, + const float16_t *pSrcVec, + float16_t *pDstVec) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const float16_t *pSrcA = pSrcMat->pData; + const float16_t *pInA0; + const float16_t *pInA1; + float16_t *px; + int32_t row; + uint32_t blkCnt; /* loop counters */ + + row = numRows; + px = pDstVec; + + /* + * compute 4 rows in parallel + */ + while (row >= 4) + { + const float16_t *pInA2, *pInA3; + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f16x8_t vecIn, acc0, acc1, acc2, acc3; + float16_t const *pSrcVecPtr = pSrcVec; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + acc2 = vdupq_n_f16(0.0f); + acc3 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 8; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 8; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vld1q(pSrcA0Vec); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + *px++ = vecAddAcrossF16Mve(acc0); + *px++ = vecAddAcrossF16Mve(acc1); + *px++ = vecAddAcrossF16Mve(acc2); + *px++ = vecAddAcrossF16Mve(acc3); + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) + { + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f16x8_t vecIn, acc0, acc1; + float16_t const *pSrcVecPtr = pSrcVec; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vld1q(pSrcA0Vec); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + *px++ = vecAddAcrossF16Mve(acc0); + *px++ = vecAddAcrossF16Mve(acc1); + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) + { + f16x8_t vecIn, acc0; + float16_t const *pSrcA0Vec, *pInVec; + float16_t const *pSrcVecPtr = pSrcVec; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vld1q(pSrcA0Vec); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + *px++ = vecAddAcrossF16Mve(acc0); + } +} +#else +void arm_mat_vec_mult_f16(const arm_matrix_instance_f16 *pSrcMat, const float16_t *pVec, float16_t *pDst) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const float16_t *pSrcA = pSrcMat->pData; + const float16_t *pInA1; /* input data matrix pointer A of Q31 type */ + const float16_t *pInA2; /* input data matrix pointer A of Q31 type */ + const float16_t *pInA3; /* input data matrix pointer A of Q31 type */ + const float16_t *pInA4; /* input data matrix pointer A of Q31 type */ + const float16_t *pInVec; /* input data matrix pointer B of Q31 type */ + float16_t *px; /* Temporary output data matrix pointer */ + uint16_t i, row, colCnt; /* loop counters */ + float16_t matData, matData2, vecData, vecData2; + + + /* Process 4 rows at a time */ + row = numRows >> 2; + i = 0u; + px = pDst; + + /* The following loop performs the dot-product of each row in pSrcA with the vector */ + /* row loop */ + while (row > 0) { + /* For every row wise process, the pInVec pointer is set + ** to the starting address of the vector */ + pInVec = pVec; + + /* Initialize accumulators */ + float16_t sum1 = 0.0f16; + float16_t sum2 = 0.0f16; + float16_t sum3 = 0.0f16; + float16_t sum4 = 0.0f16; + + /* Loop unrolling: process 2 columns per iteration */ + colCnt = numCols; + + /* Initialize pointers to the starting address of the column being processed */ + pInA1 = pSrcA + i; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + pInA4 = pInA3 + numCols; + + + // Main loop: matrix-vector multiplication + while (colCnt > 0u) { + // Read 2 values from vector + vecData = *(pInVec)++; + // Read 8 values from the matrix - 2 values from each of 4 rows, and do multiply accumulate + matData = *(pInA1)++; + sum1 += (_Float16)matData * (_Float16)vecData; + matData = *(pInA2)++; + sum2 += (_Float16)matData * (_Float16)vecData; + matData = *(pInA3)++; + sum3 += (_Float16)matData * (_Float16)vecData; + matData = *(pInA4)++; + sum4 += (_Float16)matData * (_Float16)vecData; + + // Decrement the loop counter + colCnt--; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = sum1; + *px++ = sum2; + *px++ = sum3; + *px++ = sum4; + + i = i + numCols * 4; + + /* Decrement the row loop counter */ + row--; + } + + /* process any remaining rows */ + row = numRows & 3u; + while (row > 0) { + + float16_t sum = 0.0f16; + pInVec = pVec; + pInA1 = pSrcA + i; + + colCnt = numCols >> 1; + + while (colCnt > 0) { + vecData = *(pInVec)++; + vecData2 = *(pInVec)++; + matData = *(pInA1)++; + matData2 = *(pInA1)++; + sum += (_Float16)matData * (_Float16)vecData; + sum += (_Float16)matData2 * (_Float16)vecData2; + colCnt--; + } + // process remainder of row + colCnt = numCols & 1u; + while (colCnt > 0) { + sum += (_Float16)*pInA1++ * (_Float16)*pInVec++; + colCnt--; + } + + *px++ = sum; + i = i + numCols; + row--; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixMult group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_f32.c new file mode 100644 index 00000000..b112d349 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_f32.c @@ -0,0 +1,399 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_vec_mult_f32.c + * Description: Floating-point matrix and vector multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + + +/** + * @ingroup groupMatrix + */ + +/** + * @defgroup MatrixVectMult Matrix Vector Multiplication + * + * Multiplies a matrix and a vector. + * + */ + +/** + * @addtogroup MatrixVectMult + * @{ + */ + +/** + * @brief Floating-point matrix and vector multiplication. + * @param[in] *pSrcMat points to the input matrix structure + * @param[in] *pVec points to input vector + * @param[out] *pDst points to output vector + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_mat_vec_mult_f32( + const arm_matrix_instance_f32 *pSrcMat, + const float32_t *pSrcVec, + float32_t *pDstVec) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const float32_t *pSrcA = pSrcMat->pData; + const float32_t *pInA0; + const float32_t *pInA1; + float32_t *px; + int32_t row; + uint32_t blkCnt; /* loop counters */ + + row = numRows; + px = pDstVec; + + /* + * compute 4 rows in parallel + */ + while (row >= 4) + { + const float32_t *pInA2, *pInA3; + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f32x4_t vecIn, acc0, acc1, acc2, acc3; + float32_t const *pSrcVecPtr = pSrcVec; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 4; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 4; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vld1q(pSrcA0Vec); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + *px++ = vecAddAcrossF32Mve(acc0); + *px++ = vecAddAcrossF32Mve(acc1); + *px++ = vecAddAcrossF32Mve(acc2); + *px++ = vecAddAcrossF32Mve(acc3); + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) + { + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f32x4_t vecIn, acc0, acc1; + float32_t const *pSrcVecPtr = pSrcVec; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vld1q(pSrcA0Vec); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + *px++ = vecAddAcrossF32Mve(acc0); + *px++ = vecAddAcrossF32Mve(acc1); + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) + { + f32x4_t vecIn, acc0; + float32_t const *pSrcA0Vec, *pInVec; + float32_t const *pSrcVecPtr = pSrcVec; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vld1q(pSrcA0Vec); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + *px++ = vecAddAcrossF32Mve(acc0); + } +} +#else + +void arm_mat_vec_mult_f32(const arm_matrix_instance_f32 *pSrcMat, const float32_t *pVec, float32_t *pDst) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const float32_t *pSrcA = pSrcMat->pData; + const float32_t *pInA1; /* input data matrix pointer A of Q31 type */ + const float32_t *pInA2; /* input data matrix pointer A of Q31 type */ + const float32_t *pInA3; /* input data matrix pointer A of Q31 type */ + const float32_t *pInA4; /* input data matrix pointer A of Q31 type */ + const float32_t *pInVec; /* input data matrix pointer B of Q31 type */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t i, row, colCnt; /* loop counters */ + float32_t matData, matData2, vecData, vecData2; + + + /* Process 4 rows at a time */ + row = numRows >> 2; + i = 0u; + px = pDst; + + /* The following loop performs the dot-product of each row in pSrcA with the vector */ + /* row loop */ + while (row > 0) { + /* Initialize accumulators */ + float32_t sum1 = 0.0f; + float32_t sum2 = 0.0f; + float32_t sum3 = 0.0f; + float32_t sum4 = 0.0f; + + /* For every row wise process, the pInVec pointer is set + ** to the starting address of the vector */ + pInVec = pVec; + + /* Loop unrolling: process 2 columns per iteration */ + colCnt = numCols; + + /* Initialize pointers to the starting address of the column being processed */ + pInA1 = pSrcA + i; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + pInA4 = pInA3 + numCols; + + + // Main loop: matrix-vector multiplication + while (colCnt > 0u) { + // Read 2 values from vector + vecData = *(pInVec)++; + // Read 8 values from the matrix - 2 values from each of 4 rows, and do multiply accumulate + matData = *(pInA1)++; + sum1 += matData * vecData; + matData = *(pInA2)++; + sum2 += matData * vecData; + matData = *(pInA3)++; + sum3 += matData * vecData; + matData = *(pInA4)++; + sum4 += matData * vecData; + + // Decrement the loop counter + colCnt--; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = sum1; + *px++ = sum2; + *px++ = sum3; + *px++ = sum4; + + i = i + numCols * 4; + + /* Decrement the row loop counter */ + row--; + } + + /* process any remaining rows */ + row = numRows & 3u; + while (row > 0) { + + float32_t sum = 0.0f; + pInVec = pVec; + pInA1 = pSrcA + i; + + colCnt = numCols >> 1; + while (colCnt > 0) { + vecData = *(pInVec)++; + vecData2 = *(pInVec)++; + matData = *(pInA1)++; + matData2 = *(pInA1)++; + sum += matData * vecData; + sum += matData2 * vecData2; + colCnt--; + } + // process remainder of row + colCnt = numCols & 1u; + + + while (colCnt > 0) { + sum += *pInA1++ * *pInVec++; + colCnt--; + } + + *px++ = sum; + i = i + numCols; + row--; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q15.c new file mode 100644 index 00000000..04499f93 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q15.c @@ -0,0 +1,388 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_vec_mult_q15.c + * Description: Q15 matrix and vector multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + * @ingroup groupMatrix + */ + + + +/** + * @addtogroup MatrixVectMult + * @{ + */ + +/** + * @brief Q15 matrix and vector multiplication. + * @param[in] *pSrcMat points to the input matrix structure + * @param[in] *pVec points to input vector + * @param[out] *pDst points to output vector + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_mat_vec_mult_q15( + const arm_matrix_instance_q15 * pSrcMat, + const q15_t *pSrcVec, + q15_t *pDstVec) +{ + const q15_t *pMatSrc = pSrcMat->pData; + const q15_t *pMat0, *pMat1; + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + q15_t *px; + int32_t row; + uint16_t blkCnt; /* loop counters */ + + row = numRows; + px = pDstVec; + + /* + * compute 3x64-bit accumulators per loop + */ + while (row >= 3) + { + q15_t const *pMat0Vec, *pMat1Vec, *pMat2Vec, *pVec; + const q15_t *pMat2; + q15_t const *pSrcVecPtr = pSrcVec; + q63_t acc0, acc1, acc2; + q15x8_t vecMatA0, vecMatA1, vecMatA2, vecIn; + + + pVec = pSrcVec; + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + pMat1 = pMat0 + numCols; + pMat2 = pMat1 + numCols; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + + pMat0Vec = pMat0; + pMat1Vec = pMat1; + pMat2Vec = pMat2; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 8; + vecMatA1 = vld1q(pMat1Vec); + pMat1Vec += 8; + vecMatA2 = vld1q(pMat2Vec); + pMat2Vec += 8; + vecIn = vld1q(pVec); + pVec += 8; + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + acc2 = vmlaldavaq(acc2, vecIn, vecMatA2); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecMatA1 = vld1q(pMat1Vec); + vecMatA2 = vld1q(pMat2Vec); + vecIn = vldrhq_z_s16(pVec, p0); + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + acc2 = vmlaldavaq(acc2, vecIn, vecMatA2); + } + + *px++ = MVE_ASRL_SAT16(acc0, 15); + *px++ = MVE_ASRL_SAT16(acc1, 15); + *px++ = MVE_ASRL_SAT16(acc2, 15); + + pMatSrc += numCols * 3; + /* + * Decrement the row loop counter + */ + row -= 3; + } + + /* + * process any remaining rows pair + */ + if (row >= 2) + { + q15_t const *pMat0Vec, *pMat1Vec, *pVec; + q15_t const *pSrcVecPtr = pSrcVec; + q63_t acc0, acc1; + q15x8_t vecMatA0, vecMatA1, vecIn; + + /* + * For every row wise process, the pInVec pointer is set + * to the starting address of the vector + */ + pVec = pSrcVec; + + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + pMat1 = pMat0 + numCols; + + acc0 = 0LL; + acc1 = 0LL; + + pMat0Vec = pMat0; + pMat1Vec = pMat1; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 8; + vecMatA1 = vld1q(pMat1Vec); + pMat1Vec += 8; + vecIn = vld1q(pVec); + pVec += 8; + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecMatA1 = vld1q(pMat1Vec); + vecIn = vldrhq_z_s16(pVec, p0); + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + } + + *px++ = MVE_ASRL_SAT16(acc0, 15); + *px++ = MVE_ASRL_SAT16(acc1, 15); + + pMatSrc += numCols * 2; + /* + * Decrement the row loop counter + */ + row -= 2; + } + + if (row >= 1) + { + q15_t const *pMat0Vec, *pVec; + q15_t const *pSrcVecPtr = pSrcVec; + q63_t acc0; + q15x8_t vecMatA0, vecIn; + + /* + * For every row wise process, the pInVec pointer is set + * to the starting address of the vector + */ + pVec = pSrcVec; + + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + + acc0 = 0LL; + + pMat0Vec = pMat0; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 8; + vecIn = vld1q(pVec); + pVec += 8; + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecIn = vldrhq_z_s16(pVec, p0); + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + } + *px++ = MVE_ASRL_SAT16(acc0, 15); + } +} + +#else +void arm_mat_vec_mult_q15(const arm_matrix_instance_q15 *pSrcMat, const q15_t *pVec, q15_t *pDst) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const q15_t *pSrcA = pSrcMat->pData; + const q15_t *pInA1; /* input data matrix pointer A of Q15 type */ + const q15_t *pInA2; /* input data matrix pointer A of Q15 type */ + const q15_t *pInA3; /* input data matrix pointer A of Q15 type */ + const q15_t *pInA4; /* input data matrix pointer A of Q15 type */ + const q15_t *pInVec; /* input data matrix pointer B of Q15 type */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t i, row, colCnt; /* loop counters */ + q31_t matData, matData2, vecData, vecData2; + + + /* Process 4 rows at a time */ + row = numRows >> 2; + i = 0u; + px = pDst; + + /* The following loop performs the dot-product of each row in pSrcA with the vector */ + /* row loop */ + while (row > 0) { + /* Initialize accumulators */ + q63_t sum1 = 0; + q63_t sum2 = 0; + q63_t sum3 = 0; + q63_t sum4 = 0; + + /* For every row wise process, the pInVec pointer is set + ** to the starting address of the vector */ + pInVec = pVec; + + /* Loop unrolling: process 2 columns per iteration */ + colCnt = numCols >> 1; + + /* Initialize pointers to the starting address of the column being processed */ + pInA1 = pSrcA + i; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + pInA4 = pInA3 + numCols; + + // Main loop: matrix-vector multiplication + while (colCnt > 0u) { + // Read 2 values from vector + vecData = read_q15x2_ia (&pInVec); + + // Read 8 values from the matrix - 2 values from each of 4 rows, and do multiply accumulate + matData = read_q15x2_ia (&pInA1); + sum1 = __SMLALD(matData, vecData, sum1); + matData = read_q15x2_ia (&pInA2); + sum2 = __SMLALD(matData, vecData, sum2); + matData = read_q15x2_ia (&pInA3); + sum3 = __SMLALD(matData, vecData, sum3); + matData = read_q15x2_ia (&pInA4); + sum4 = __SMLALD(matData, vecData, sum4); + + // Decrement the loop counter + colCnt--; + } + + /* process any remaining columns */ + colCnt = numCols & 1u; + if (numCols & 1u) { + vecData = *pInVec++; + sum1 += (q63_t)*pInA1++ * vecData; + sum2 += (q63_t)*pInA2++ * vecData; + sum3 += (q63_t)*pInA3++ * vecData; + sum4 += (q63_t)*pInA4++ * vecData; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = (q15_t)(__SSAT((sum1 >> 15), 16)); + *px++ = (q15_t)(__SSAT((sum2 >> 15), 16)); + *px++ = (q15_t)(__SSAT((sum3 >> 15), 16)); + *px++ = (q15_t)(__SSAT((sum4 >> 15), 16)); + + i = i + numCols * 4; + + /* Decrement the row loop counter */ + row--; + } + + /* process any remaining rows */ + row = numRows & 3u; + while (row > 0) { + + q63_t sum = 0; + pInVec = pVec; + pInA1 = pSrcA + i; + + // loop unrolling - process 4 elements at a time + colCnt = numCols >> 2; + + while (colCnt > 0) { + vecData = read_q15x2_ia (&pInVec); + vecData2 = read_q15x2_ia (&pInVec); + matData = read_q15x2_ia (&pInA1); + matData2 = read_q15x2_ia (&pInA1); + sum = __SMLALD(matData, vecData, sum); + sum = __SMLALD(matData2, vecData2, sum); + colCnt--; + } + + // process remainder of row + colCnt = numCols & 3u; + while (colCnt > 0) { + sum += (q63_t)*pInA1++ * *pInVec++; + colCnt--; + } + *px++ = (q15_t)(__SSAT((sum >> 15), 16)); + i = i + numCols; + row--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + * @} end of MatrixMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q31.c new file mode 100644 index 00000000..9f491eab --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q31.c @@ -0,0 +1,376 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_vec_mult_q31.c + * Description: Q31 matrix and vector multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + * @ingroup groupMatrix + */ + + + +/** + * @addtogroup MatrixVectMult + * @{ + */ + +/** + * @brief Q31 matrix and vector multiplication. + * @param[in] *pSrcMat points to the input matrix structure + * @param[in] *pVec points to the input vector + * @param[out] *pDst points to the output vector + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_mat_vec_mult_q31( + const arm_matrix_instance_q31 * pSrcMat, + const q31_t *pSrcVec, + q31_t *pDstVec) +{ + const q31_t *pMatSrc = pSrcMat->pData; + const q31_t *pMat0, *pMat1; + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + q31_t *px; + int32_t row; + uint16_t blkCnt; /* loop counters */ + + row = numRows; + px = pDstVec; + + /* + * compute 3x64-bit accumulators per loop + */ + while (row >= 3) + { + q31_t const *pMat0Vec, *pMat1Vec, *pMat2Vec, *pVec; + const q31_t *pMat2; + q31_t const *pSrcVecPtr = pSrcVec; + q63_t acc0, acc1, acc2; + q31x4_t vecMatA0, vecMatA1, vecMatA2, vecIn; + + + pVec = pSrcVec; + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + pMat1 = pMat0 + numCols; + pMat2 = pMat1 + numCols; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + + pMat0Vec = pMat0; + pMat1Vec = pMat1; + pMat2Vec = pMat2; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 4; + vecMatA1 = vld1q(pMat1Vec); + pMat1Vec += 4; + vecMatA2 = vld1q(pMat2Vec); + pMat2Vec += 4; + vecIn = vld1q(pVec); + pVec += 4; + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + acc2 = vmlaldavaq(acc2, vecIn, vecMatA2); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecMatA1 = vld1q(pMat1Vec); + vecMatA2 = vld1q(pMat2Vec); + vecIn = vldrwq_z_s32(pVec, p0); + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + acc2 = vmlaldavaq(acc2, vecIn, vecMatA2); + } + + *px++ = asrl(acc0, 31); + *px++ = asrl(acc1, 31); + *px++ = asrl(acc2, 31); + + pMatSrc += numCols * 3; + /* + * Decrement the row loop counter + */ + row -= 3; + } + + /* + * process any remaining rows pair + */ + if (row >= 2) + { + q31_t const *pMat0Vec, *pMat1Vec, *pVec; + q31_t const *pSrcVecPtr = pSrcVec; + q63_t acc0, acc1; + q31x4_t vecMatA0, vecMatA1, vecIn; + + /* + * For every row wise process, the pInVec pointer is set + * to the starting address of the vector + */ + pVec = pSrcVec; + + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + pMat1 = pMat0 + numCols; + + acc0 = 0LL; + acc1 = 0LL; + + pMat0Vec = pMat0; + pMat1Vec = pMat1; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 4; + vecMatA1 = vld1q(pMat1Vec); + pMat1Vec += 4; + vecIn = vld1q(pVec); + pVec += 4; + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecMatA1 = vld1q(pMat1Vec); + vecIn = vldrwq_z_s32(pVec, p0); + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + } + + *px++ = asrl(acc0, 31); + *px++ = asrl(acc1, 31); + + pMatSrc += numCols * 2; + /* + * Decrement the row loop counter + */ + row -= 2; + } + + if (row >= 1) + { + q31_t const *pMat0Vec, *pVec; + q31_t const *pSrcVecPtr = pSrcVec; + q63_t acc0; + q31x4_t vecMatA0, vecIn; + + /* + * For every row wise process, the pInVec pointer is set + * to the starting address of the vector + */ + pVec = pSrcVec; + + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + + acc0 = 0LL; + + pMat0Vec = pMat0; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 4; + vecIn = vld1q(pVec); + pVec += 4; + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecIn = vldrwq_z_s32(pVec, p0); + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + } + + *px++ = asrl(acc0, 31); + } +} +#else +void arm_mat_vec_mult_q31(const arm_matrix_instance_q31 *pSrcMat, const q31_t *pVec, q31_t *pDst) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const q31_t *pSrcA = pSrcMat->pData; + const q31_t *pInA1; /* input data matrix pointer A of Q31 type */ + const q31_t *pInA2; /* input data matrix pointer A of Q31 type */ + const q31_t *pInA3; /* input data matrix pointer A of Q31 type */ + const q31_t *pInA4; /* input data matrix pointer A of Q31 type */ + const q31_t *pInVec; /* input data matrix pointer B of Q31 type */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t i, row, colCnt; /* loop counters */ + q31_t matData, matData2, vecData, vecData2; + + + /* Process 4 rows at a time */ + row = numRows >> 2; + i = 0u; + px = pDst; + + /* The following loop performs the dot-product of each row in pSrcA with the vector */ + /* row loop */ + while (row > 0) { + /* Initialize accumulators */ + q63_t sum1 = 0; + q63_t sum2 = 0; + q63_t sum3 = 0; + q63_t sum4 = 0; + + /* For every row wise process, the pInVec pointer is set + ** to the starting address of the vector */ + pInVec = pVec; + + /* Loop unrolling: process 2 columns per iteration */ + colCnt = numCols; + + /* Initialize pointers to the starting address of the column being processed */ + pInA1 = pSrcA + i; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + pInA4 = pInA3 + numCols; + + + // Main loop: matrix-vector multiplication + while (colCnt > 0u) { + // Read 2 values from vector + vecData = *(pInVec)++; + + // Read 8 values from the matrix - 2 values from each of 4 rows, and do multiply accumulate + matData = *(pInA1)++; + sum1 += (q63_t)matData * vecData; + matData = *(pInA2)++; + sum2 += (q63_t)matData * vecData; + matData = *(pInA3)++; + sum3 += (q63_t)matData * vecData; + matData = *(pInA4)++; + sum4 += (q63_t)matData * vecData; + + // Decrement the loop counter + colCnt--; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = (q31_t)(sum1 >> 31); + *px++ = (q31_t)(sum2 >> 31); + *px++ = (q31_t)(sum3 >> 31); + *px++ = (q31_t)(sum4 >> 31); + + i = i + numCols * 4; + + /* Decrement the row loop counter */ + row--; + } + + /* process any remaining rows */ + row = numRows & 3u; + while (row > 0) { + + q63_t sum = 0; + pInVec = pVec; + pInA1 = pSrcA + i; + + colCnt = numCols >> 1; + + while (colCnt > 0) { + vecData = *(pInVec)++; + vecData2 = *(pInVec)++; + matData = *(pInA1)++; + matData2 = *(pInA1)++; + sum += (q63_t)matData * vecData; + sum += (q63_t)matData2 * vecData2; + colCnt--; + } + + // process remainder of row + colCnt = numCols & 1u; + while (colCnt > 0) { + sum += (q63_t)*pInA1++ * *pInVec++; + colCnt--; + } + + *px++ = (q31_t)(sum >> 31); + i = i + numCols; + row--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + * @} end of MatrixMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q7.c new file mode 100644 index 00000000..e7c72816 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q7.c @@ -0,0 +1,420 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_vec_mult_q7.c + * Description: Q7 matrix and vector multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + * @ingroup groupMatrix + */ + + + +/** + * @addtogroup MatrixVectMult + * @{ + */ + +/** + * @brief Q7 matrix and vector multiplication. + * @param[in] *pSrcMat points to the input matrix structure + * @param[in] *pVec points to the input vector + * @param[out] *pDst points to the output vector + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_mat_vec_mult_q7( + const arm_matrix_instance_q7 * pSrcMat, + const q7_t *pSrcVec, + q7_t *pDstVec) +{ + const q7_t *pMatSrc = pSrcMat->pData; + const q7_t *pMat0, *pMat1; + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + q7_t *px; + int32_t row; + uint16_t blkCnt; /* loop counters */ + + row = numRows; + px = pDstVec; + + /* + * compute 4x64-bit accumulators per loop + */ + while (row >= 4) + { + q7_t const *pMat0Vec, *pMat1Vec, *pMat2Vec, *pMat3Vec, *pVec; + const q7_t *pMat2, *pMat3; + q7_t const *pSrcVecPtr = pSrcVec; + q31_t acc0, acc1, acc2, acc3; + q7x16_t vecMatA0, vecMatA1, vecMatA2, vecMatA3, vecIn; + + pVec = pSrcVec; + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + pMat1 = pMat0 + numCols; + pMat2 = pMat1 + numCols; + pMat3 = pMat2 + numCols; + + acc0 = 0L; + acc1 = 0L; + acc2 = 0L; + acc3 = 0L; + + pMat0Vec = pMat0; + pMat1Vec = pMat1; + pMat2Vec = pMat2; + pMat3Vec = pMat3; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 4; + while (blkCnt > 0U) + { + + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 16; + vecMatA1 = vld1q(pMat1Vec); + pMat1Vec += 16; + vecMatA2 = vld1q(pMat2Vec); + pMat2Vec += 16; + vecMatA3 = vld1q(pMat3Vec); + pMat3Vec += 16; + vecIn = vld1q(pVec); + pVec += 16; + + acc0 = vmladavaq(acc0, vecIn, vecMatA0); + acc1 = vmladavaq(acc1, vecIn, vecMatA1); + acc2 = vmladavaq(acc2, vecIn, vecMatA2); + acc3 = vmladavaq(acc3, vecIn, vecMatA3); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecMatA1 = vld1q(pMat1Vec); + vecMatA2 = vld1q(pMat2Vec); + vecMatA3 = vld1q(pMat3Vec); + vecIn = vldrbq_z_s8(pVec, p0); + + acc0 = vmladavaq(acc0, vecIn, vecMatA0); + acc1 = vmladavaq(acc1, vecIn, vecMatA1); + acc2 = vmladavaq(acc2, vecIn, vecMatA2); + acc3 = vmladavaq(acc3, vecIn, vecMatA3); + } + + *px++ = __SSAT(acc0 >> 7, 8); + *px++ = __SSAT(acc1 >> 7, 8); + *px++ = __SSAT(acc2 >> 7, 8); + *px++ = __SSAT(acc3 >> 7, 8); + + pMatSrc += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * process any remaining rows pair + */ + if (row >= 2) + { + q7_t const *pMat0Vec, *pMat1Vec, *pVec; + q7_t const *pSrcVecPtr = pSrcVec; + q31_t acc0, acc1; + q7x16_t vecMatA0, vecMatA1, vecIn; + + /* + * For every row wise process, the pInVec pointer is set + * to the starting address of the vector + */ + pVec = pSrcVec; + + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + pMat1 = pMat0 + numCols; + + acc0 = 0; + acc1 = 0; + + pMat0Vec = pMat0; + pMat1Vec = pMat1; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 4; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 16; + vecMatA1 = vld1q(pMat1Vec); + pMat1Vec += 16; + vecIn = vld1q(pVec); + pVec += 16; + + acc0 = vmladavaq(acc0, vecIn, vecMatA0); + acc1 = vmladavaq(acc1, vecIn, vecMatA1); + + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecMatA1 = vld1q(pMat1Vec); + vecIn = vldrbq_z_s8(pVec, p0); + + acc0 = vmladavaq(acc0, vecIn, vecMatA0); + acc1 = vmladavaq(acc1, vecIn, vecMatA1); + } + + *px++ = __SSAT(acc0 >> 7, 8); + *px++ = __SSAT(acc1 >> 7, 8); + + pMatSrc += numCols * 2; + /* + * Decrement the row loop counter + */ + row -= 2; + } + + if (row >= 1) + { + q7_t const *pMat0Vec, *pVec; + q7_t const *pSrcVecPtr = pSrcVec; + q31_t acc0; + q7x16_t vecMatA0, vecIn; + + /* + * For every row wise process, the pInVec pointer is set + * to the starting address of the vector + */ + pVec = pSrcVec; + + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + + acc0 = 0LL; + + pMat0Vec = pMat0; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 4; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 16; + vecIn = vld1q(pVec); + pVec += 16; + + acc0 = vmladavaq(acc0, vecIn, vecMatA0); + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecIn = vldrbq_z_s8(pVec, p0); + acc0 = vmladavaq(acc0, vecIn, vecMatA0); + } + *px++ = __SSAT(acc0 >> 7, 8); + } +} + +#else +void arm_mat_vec_mult_q7(const arm_matrix_instance_q7 *pSrcMat, const q7_t *pVec, q7_t *pDst) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const q7_t *pSrcA = pSrcMat->pData; + const q7_t *pInA1; /* input data matrix pointer of Q7 type */ + const q7_t *pInA2; /* input data matrix pointer of Q7 type */ + const q7_t *pInA3; /* input data matrix pointer of Q7 type */ + const q7_t *pInA4; /* input data matrix pointer of Q7 type */ + const q7_t *pInVec; /* input data vector pointer of Q7 type */ + q7_t *px; /* output data pointer */ + uint32_t i, row, colCnt; /* loop counters */ + + q31_t matData, matData2, vecData, vecData2; + + + /* Process 4 rows at a time */ + row = numRows >> 2; + i = 0u; + px = pDst; + + + + /* The following loop performs the dot-product of each row in pSrcA with the vector */ + while (row > 0) { + /* Initialize accumulators */ + q31_t sum1 = 0; + q31_t sum2 = 0; + q31_t sum3 = 0; + q31_t sum4 = 0; + + /* For every row wise process, the pInVec pointer is set + ** to the starting address of the vector */ + pInVec = pVec; + + /* Loop unrolling: process 4 columns per iteration */ + colCnt = numCols >> 2; + + /* Initialize row pointers so we can track 4 rows at once */ + pInA1 = pSrcA + i; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + pInA4 = pInA3 + numCols; + + + // Inner loop: matrix-vector multiplication + + while (colCnt > 0u) { + // Read 4 values from vector + vecData = read_q7x4_ia (&pInVec); + vecData2 = __SXTB16(__ROR(vecData, 8)); + vecData = __SXTB16(vecData); + // Read 16 values from the matrix - 4 values from each of 4 rows, and do multiply accumulate + matData = read_q7x4_ia (&pInA1); + matData2 = __SXTB16(__ROR(matData, 8)); + matData = __SXTB16(matData); + sum1 = __SMLAD(matData, vecData, sum1); + sum1 = __SMLAD(matData2, vecData2, sum1); + matData = read_q7x4_ia (&pInA2); + matData2 = __SXTB16(__ROR(matData, 8)); + matData = __SXTB16(matData); + sum2 = __SMLAD(matData, vecData, sum2); + sum2 = __SMLAD(matData2, vecData2, sum2); + matData = read_q7x4_ia (&pInA3); + matData2 = __SXTB16(__ROR(matData, 8)); + matData = __SXTB16(matData); + sum3 = __SMLAD(matData, vecData, sum3); + sum3 = __SMLAD(matData2, vecData2, sum3); + matData = read_q7x4_ia (&pInA4); + matData2 = __SXTB16(__ROR(matData, 8)); + matData = __SXTB16(matData); + sum4 = __SMLAD(matData, vecData, sum4); + sum4 = __SMLAD(matData2, vecData2, sum4); + + // Decrement the loop counter + colCnt--; + } + + /* process any remaining columns */ + + colCnt = numCols & 3u; + + while (colCnt > 0) { + vecData = *pInVec++; + sum1 += *pInA1++ * vecData; + sum2 += *pInA2++ * vecData; + sum3 += *pInA3++ * vecData; + sum4 += *pInA4++ * vecData; + colCnt--; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = (q7_t)(__SSAT((sum1 >> 7), 8)); + *px++ = (q7_t)(__SSAT((sum2 >> 7), 8)); + *px++ = (q7_t)(__SSAT((sum3 >> 7), 8)); + *px++ = (q7_t)(__SSAT((sum4 >> 7), 8)); + + i = i + numCols * 4; + + /* Decrement the row loop counter */ + row--; + } + + /* process any remaining rows */ + row = numRows & 3u; + while (row > 0) { + + q31_t sum = 0; + pInVec = pVec; + pInA1 = pSrcA + i; + + // loop unrolling - process 4 elements at a time + colCnt = numCols >> 2; + + while (colCnt > 0) { + vecData = read_q7x4_ia (&pInVec); + vecData2 = __SXTB16(__ROR(vecData, 8)); + vecData = __SXTB16(vecData); + matData = read_q7x4_ia (&pInA1); + matData2 = __SXTB16(__ROR(matData, 8)); + matData = __SXTB16(matData); + sum = __SMLAD(matData, vecData, sum); + sum = __SMLAD(matData2, vecData2, sum); + colCnt--; + } + + // process remainder of row + colCnt = numCols & 3u; + while (colCnt > 0) { + sum += *pInA1++ * *pInVec++; + colCnt--; + } + *px++ = (q7_t)(__SSAT((sum >> 7), 8)); + i = i + numCols; + row--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + * @} end of MatrixMult group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/CMakeLists.txt new file mode 100644 index 00000000..267626f5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/CMakeLists.txt @@ -0,0 +1,31 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPQuaternionMath) + +include(configLib) +include(configDsp) + + + +add_library(CMSISDSPQuaternionMath STATIC arm_quaternion_norm_f32.c) +target_sources(CMSISDSPQuaternionMath PRIVATE arm_quaternion_inverse_f32.c) +target_sources(CMSISDSPQuaternionMath PRIVATE arm_quaternion_conjugate_f32.c) +target_sources(CMSISDSPQuaternionMath PRIVATE arm_quaternion_normalize_f32.c) +target_sources(CMSISDSPQuaternionMath PRIVATE arm_quaternion_product_single_f32.c) +target_sources(CMSISDSPQuaternionMath PRIVATE arm_quaternion_product_f32.c) +target_sources(CMSISDSPQuaternionMath PRIVATE arm_quaternion2rotation_f32.c) +target_sources(CMSISDSPQuaternionMath PRIVATE arm_rotation2quaternion_f32.c) + + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +endif() + + +configLib(CMSISDSPQuaternionMath ${ROOT}) +configDsp(CMSISDSPQuaternionMath ${ROOT}) + +### Includes +target_include_directories(CMSISDSPQuaternionMath PUBLIC "${DSP}/Include") + + + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/QuaternionMathFunctions.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/QuaternionMathFunctions.c new file mode 100644 index 00000000..7c48178e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/QuaternionMathFunctions.c @@ -0,0 +1,34 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: QuaternionMathFunctions.c + * Description: Combination of all quaternion math function source files. + * + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_quaternion_norm_f32.c" +#include "arm_quaternion_inverse_f32.c" +#include "arm_quaternion_conjugate_f32.c" +#include "arm_quaternion_normalize_f32.c" +#include "arm_quaternion_product_single_f32.c" +#include "arm_quaternion_product_f32.c" +#include "arm_quaternion2rotation_f32.c" +#include "arm_rotation2quaternion_f32.c" diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion2rotation_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion2rotation_f32.c new file mode 100644 index 00000000..21053415 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion2rotation_f32.c @@ -0,0 +1,181 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quaternion2rotation_f32.c + * Description: Floating-point quaternion 2 rotation conversion + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatConv Quaternion conversions + + Conversions between quaternion and rotation representations. + */ + +/** + @ingroup QuatConv + */ + +/** + @defgroup QuatRot Quaternion to Rotation + + Conversions from quaternion to rotation. + */ + +/** + @addtogroup QuatRot + @{ + */ + +/** + @brief Conversion of quaternion to equivalent rotation matrix. + @param[in] pInputQuaternions points to an array of normalized quaternions + @param[out] pOutputRotations points to an array of 3x3 rotations (in row order) + @param[in] nbQuaternions number of quaternions in the array + @return none. + + @par + Format of rotation matrix + + + The quaternion a + ib + jc + kd is converted into rotation matrix: +
+     a^2 + b^2 - c^2 - d^2                 2bc - 2ad                 2bd + 2ac
+                 2bc + 2ad     a^2 - b^2 + c^2 - d^2                 2cd - 2ab
+                 2bd - 2ac                 2cd + 2ab     a^2 - b^2 - c^2 + d^2
+   
+ Rotation matrix is saved in row order : R00 R01 R02 R10 R11 R12 R20 R21 R22 + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_quaternion2rotation_f32(const float32_t *pInputQuaternions, + float32_t *pOutputRotations, + uint32_t nbQuaternions) +{ + f32x4_t vec0,vec1, vec2 ,vec3; + float32_t q2q3, tmp1, tmp2 ; + + for(uint32_t nb=0; nb < nbQuaternions; nb++) + { + + // q0 q1 q2 q3 + vec0 = vld1q(pInputQuaternions); + + // q0^2 q1^2 q2^2 q3^2 + vec1 = vmulq(vec0,vec0); + + // q0^2 q1q0 q2q0 q3q0 + vec2 = vmulq_n_f32(vec0, vgetq_lane(vec0,0)); + + // 2 (q0^2 q1q0 q2q0 q3q0) + vec2 = vmulq_n_f32(vec2, 2.0f); + + + // 2 q2q3 + q2q3 = vgetq_lane(vec0,2) * vgetq_lane(vec0,3); + q2q3 = q2q3 * 2.0f; + + // 2 (q0q1 q1^2 q2q1 q3q1) + vec3 = vmulq_n_f32(vec0, vgetq_lane(vec0,1)); + vec3 = vmulq_n_f32(vec3, 2.0f); + + + + vec0 = vsetq_lane(vgetq_lane(vec1,0) + vgetq_lane(vec1,1),vec0,0); + vec0 = vsetq_lane(vgetq_lane(vec0,0) - vgetq_lane(vec1,2),vec0,0); + vec0 = vsetq_lane(vgetq_lane(vec0,0) - vgetq_lane(vec1,3),vec0,0); + vec0 = vsetq_lane(vgetq_lane(vec3,2) - vgetq_lane(vec2,3),vec0,1); + vec0 = vsetq_lane(vgetq_lane(vec3,3) + vgetq_lane(vec2,2),vec0,2); + vec0 = vsetq_lane(vgetq_lane(vec3,2) + vgetq_lane(vec2,3),vec0,3); + + vst1q(pOutputRotations, vec0); + pOutputRotations += 4; + + tmp1 = vgetq_lane(vec1,0) - vgetq_lane(vec1,1); + tmp2 = vgetq_lane(vec1,2) - vgetq_lane(vec1,3); + + + vec0 = vsetq_lane(tmp1 + tmp2,vec0,0); + vec0 = vsetq_lane(q2q3 - vgetq_lane(vec2,1) ,vec0,1); + vec0 = vsetq_lane(vgetq_lane(vec3,3) - vgetq_lane(vec2,2),vec0,2); + vec0 = vsetq_lane(q2q3 + vgetq_lane(vec2,1) ,vec0,3); + + vst1q(pOutputRotations, vec0); + pOutputRotations += 4; + + *pOutputRotations = tmp1 - tmp2; + pOutputRotations ++; + + pInputQuaternions += 4; + } +} + +#else +void arm_quaternion2rotation_f32(const float32_t *pInputQuaternions, + float32_t *pOutputRotations, + uint32_t nbQuaternions) +{ + uint32_t nb; + for(nb=0; nb < nbQuaternions; nb++) + { + float32_t q00 = SQ(pInputQuaternions[0 + nb * 4]); + float32_t q11 = SQ(pInputQuaternions[1 + nb * 4]); + float32_t q22 = SQ(pInputQuaternions[2 + nb * 4]); + float32_t q33 = SQ(pInputQuaternions[3 + nb * 4]); + float32_t q01 = pInputQuaternions[0 + nb * 4]*pInputQuaternions[1 + nb * 4]; + float32_t q02 = pInputQuaternions[0 + nb * 4]*pInputQuaternions[2 + nb * 4]; + float32_t q03 = pInputQuaternions[0 + nb * 4]*pInputQuaternions[3 + nb * 4]; + float32_t q12 = pInputQuaternions[1 + nb * 4]*pInputQuaternions[2 + nb * 4]; + float32_t q13 = pInputQuaternions[1 + nb * 4]*pInputQuaternions[3 + nb * 4]; + float32_t q23 = pInputQuaternions[2 + nb * 4]*pInputQuaternions[3 + nb * 4]; + + float32_t xx = q00 + q11 - q22 - q33; + float32_t yy = q00 - q11 + q22 - q33; + float32_t zz = q00 - q11 - q22 + q33; + float32_t xy = 2*(q12 - q03); + float32_t xz = 2*(q13 + q02); + float32_t yx = 2*(q12 + q03); + float32_t yz = 2*(q23 - q01); + float32_t zx = 2*(q13 - q02); + float32_t zy = 2*(q23 + q01); + + pOutputRotations[0 + nb * 9] = xx; pOutputRotations[1 + nb * 9] = xy; pOutputRotations[2 + nb * 9] = xz; + pOutputRotations[3 + nb * 9] = yx; pOutputRotations[4 + nb * 9] = yy; pOutputRotations[5 + nb * 9] = yz; + pOutputRotations[6 + nb * 9] = zx; pOutputRotations[7 + nb * 9] = zy; pOutputRotations[8 + nb * 9] = zz; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of QuatRot group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_conjugate_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_conjugate_f32.c new file mode 100644 index 00000000..213a5bbc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_conjugate_f32.c @@ -0,0 +1,98 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quaternion_conjugate_f32.c + * Description: Floating-point quaternion conjugate + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatConjugate Quaternion Conjugate + + Compute the conjugate of a quaternion. + */ + +/** + @addtogroup QuatConjugate + @{ + */ + +/** + @brief Floating-point quaternion conjugates. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pConjugateQuaternions points to the output vector of conjugate quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_quaternion_conjugate_f32(const float32_t *pInputQuaternions, + float32_t *pConjugateQuaternions, + uint32_t nbQuaternions) +{ + f32x4_t vec1; + + for(uint32_t i=0; i < nbQuaternions; i++) + { + vec1 = vld1q(pInputQuaternions); + + + vec1 = vsetq_lane_f32(-vgetq_lane(vec1, 0),vec1,0); + vec1 = vnegq_f32(vec1); + + vst1q(pConjugateQuaternions, vec1); + + + pInputQuaternions += 4; + pConjugateQuaternions += 4; + } +} +#else +void arm_quaternion_conjugate_f32(const float32_t *pInputQuaternions, + float32_t *pConjugateQuaternions, + uint32_t nbQuaternions) +{ + uint32_t i; + for(i=0; i < nbQuaternions; i++) + { + + pConjugateQuaternions[4 * i + 0] = pInputQuaternions[4 * i + 0]; + pConjugateQuaternions[4 * i + 1] = -pInputQuaternions[4 * i + 1]; + pConjugateQuaternions[4 * i + 2] = -pInputQuaternions[4 * i + 2]; + pConjugateQuaternions[4 * i + 3] = -pInputQuaternions[4 * i + 3]; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of QuatConjugate group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_inverse_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_inverse_f32.c new file mode 100644 index 00000000..d82bbbf1 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_inverse_f32.c @@ -0,0 +1,114 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quaternion_inverse_f32.c + * Description: Floating-point quaternion inverse + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatInverse Quaternion Inverse + + Compute the inverse of a quaternion. + */ + +/** + @addtogroup QuatInverse + @{ + */ + +/** + @brief Floating-point quaternion inverse. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pInverseQuaternions points to the output vector of inverse quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_quaternion_inverse_f32(const float32_t *pInputQuaternions, + float32_t *pInverseQuaternions, + uint32_t nbQuaternions) +{ + f32x4_t vec1,vec2; + float32_t squaredSum; + + for(uint32_t i=0; i < nbQuaternions; i++) + { + + vec1 = vld1q(pInputQuaternions); + vec2 = vmulq(vec1,vec1); + squaredSum = vecAddAcrossF32Mve(vec2); + + + vec1 = vmulq_n_f32(vec1, 1.0f / squaredSum); + vec1 = vsetq_lane_f32(-vgetq_lane(vec1, 0),vec1,0); + vec1 = vnegq_f32(vec1); + + vst1q(pInverseQuaternions, vec1); + + + pInputQuaternions += 4; + pInverseQuaternions += 4; + + } +} + +#else +void arm_quaternion_inverse_f32(const float32_t *pInputQuaternions, + float32_t *pInverseQuaternions, + uint32_t nbQuaternions) +{ + float32_t temp; + + uint32_t i; + for(i=0; i < nbQuaternions; i++) + { + + temp = SQ(pInputQuaternions[4 * i + 0]) + + SQ(pInputQuaternions[4 * i + 1]) + + SQ(pInputQuaternions[4 * i + 2]) + + SQ(pInputQuaternions[4 * i + 3]); + + pInverseQuaternions[4 * i + 0] = pInputQuaternions[4 * i + 0] / temp; + pInverseQuaternions[4 * i + 1] = -pInputQuaternions[4 * i + 1] / temp; + pInverseQuaternions[4 * i + 2] = -pInputQuaternions[4 * i + 2] / temp; + pInverseQuaternions[4 * i + 3] = -pInputQuaternions[4 * i + 3] / temp; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of QuatInverse group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_norm_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_norm_f32.c new file mode 100644 index 00000000..af6653a0 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_norm_f32.c @@ -0,0 +1,102 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quaternion_norm_f32.c + * Description: Floating-point quaternion Norm + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatNorm Quaternion Norm + + Compute the norm of a quaternion. + */ + +/** + @addtogroup QuatNorm + @{ + */ + +/** + @brief Floating-point quaternion Norm. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pNorms points to the output vector of norms + @param[in] nbQuaternions number of quaternions in the input vector + @return none + */ + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_quaternion_norm_f32(const float32_t *pInputQuaternions, + float32_t *pNorms, + uint32_t nbQuaternions) +{ + f32x4_t vec1; + float32_t squaredSum; + + for(uint32_t i=0; i < nbQuaternions; i++) + { + vec1 = vld1q(pInputQuaternions); + vec1 = vmulq(vec1,vec1); + squaredSum = vecAddAcrossF32Mve(vec1); + arm_sqrt_f32(squaredSum,pNorms); + + pInputQuaternions+= 4; + pNorms ++; + } + +} + +#else + +void arm_quaternion_norm_f32(const float32_t *pInputQuaternions, + float32_t *pNorms, + uint32_t nbQuaternions) +{ + float32_t temp; + uint32_t i; + + for(i=0; i < nbQuaternions; i++) + { + temp = SQ(pInputQuaternions[4 * i + 0]) + + SQ(pInputQuaternions[4 * i + 1]) + + SQ(pInputQuaternions[4 * i + 2]) + + SQ(pInputQuaternions[4 * i + 3]); + pNorms[i] = sqrtf(temp); + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of QuatNorm group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_normalize_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_normalize_f32.c new file mode 100644 index 00000000..605e558b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_normalize_f32.c @@ -0,0 +1,107 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quaternion_normalize_f32.c + * Description: Floating-point quaternion normalization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatNormalized Quaternion normalization + + Compute a normalized quaternion. + */ + +/** + @addtogroup QuatNormalized + @{ + */ + +/** + @brief Floating-point normalization of quaternions. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pNormalizedQuaternions points to the output vector of normalized quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_quaternion_normalize_f32(const float32_t *pInputQuaternions, + float32_t *pNormalizedQuaternions, + uint32_t nbQuaternions) +{ + f32x4_t vec1,vec2; + float32_t squaredSum,norm; + + for(uint32_t i=0; i < nbQuaternions; i++) + { + vec1 = vld1q(pInputQuaternions); + vec2 = vmulq(vec1,vec1); + squaredSum = vecAddAcrossF32Mve(vec2); + arm_sqrt_f32(squaredSum,&norm); + vec1 = vmulq_n_f32(vec1, 1.0f / norm); + vst1q(pNormalizedQuaternions, vec1); + + pInputQuaternions += 4; + pNormalizedQuaternions += 4; + + } +} + +#else +void arm_quaternion_normalize_f32(const float32_t *pInputQuaternions, + float32_t *pNormalizedQuaternions, + uint32_t nbQuaternions) +{ + float32_t temp; + + uint32_t i; + for(i=0; i < nbQuaternions; i++) + { + temp = SQ(pInputQuaternions[4 * i + 0]) + + SQ(pInputQuaternions[4 * i + 1]) + + SQ(pInputQuaternions[4 * i + 2]) + + SQ(pInputQuaternions[4 * i + 3]); + temp = sqrtf(temp); + + pNormalizedQuaternions[4 * i + 0] = pInputQuaternions[4 * i + 0] / temp; + pNormalizedQuaternions[4 * i + 1] = pInputQuaternions[4 * i + 1] / temp; + pNormalizedQuaternions[4 * i + 2] = pInputQuaternions[4 * i + 2] / temp; + pNormalizedQuaternions[4 * i + 3] = pInputQuaternions[4 * i + 3] / temp; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of QuatNormalized group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_product_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_product_f32.c new file mode 100644 index 00000000..83ebf5ef --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_product_f32.c @@ -0,0 +1,149 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quaternion_product_f32.c + * Description: Floating-point quaternion product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatProd Quaternion Product + + Compute the product of quaternions. + */ + +/** + @ingroup QuatProd + */ + +/** + @defgroup QuatProdVect Elementwise Quaternion Product + + Compute the elementwise product of quaternions. + */ + +/** + @addtogroup QuatProdVect + @{ + */ + +/** + @brief Floating-point elementwise product two quaternions. + @param[in] qa first array of quaternions + @param[in] qb second array of quaternions + @param[out] qr elementwise product of quaternions + @param[in] nbQuaternions number of quaternions in the array + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_quaternion_product_f32(const float32_t *qa, + const float32_t *qb, + float32_t *qr, + uint32_t nbQuaternions) +{ + static uint32_t patternA[4] = { 0, 1, 0, 1 }; + static uint32_t patternB[4] = { 3, 2, 3, 2 }; + static uint32_t patternC[4] = { 3, 2, 1, 0 }; + static float32_t signA[4] = { -1, -1, 1, 1 }; + + uint32x4_t vecA = vld1q_u32(patternA); + uint32x4_t vecB = vld1q_u32(patternB); + uint32x4_t vecC = vld1q_u32(patternC); + f32x4_t vecSignA = vld1q_f32(signA); + + while (nbQuaternions > 0U) + { + f32x4_t vecTmpA, vecTmpB, vecAcc; + + vecTmpA = vldrwq_gather_shifted_offset_f32(qa, vecA); + vecTmpB = vld1q(qb); + /* + * vcmul(r, [a1, a2, a1, a2], [b1, b2, b3, b4], 0) + */ + vecAcc = vcmulq(vecTmpA, vecTmpB); + /* + * vcmla(r, [a1, a2, a1, a2], [b1, b2, b3, b4], 90) + */ + vecAcc = vcmlaq_rot90(vecAcc, vecTmpA, vecTmpB); + + vecTmpA = vldrwq_gather_shifted_offset_f32(qa, vecB); + vecTmpB = vldrwq_gather_shifted_offset_f32(qb, vecC); + /* + * build [-b4, -b3, b2, b1] + */ + vecTmpB = vecTmpB * vecSignA; + /* + * vcmla(r, [a4, a3, a4, a3], [-b4, -b3, b2, b1], 270) + */ + vecAcc = vcmlaq_rot270(vecAcc, vecTmpA, vecTmpB); + /* + * vcmla(r, [a4, a3, a4, a3], [-b4, -b3, b2, b1], 0) + */ + vecAcc = vcmlaq(vecAcc, vecTmpA, vecTmpB); + /* + * store accumulator + */ + vst1q_f32(qr, vecAcc); + + /* move to next quaternion */ + qa += 4; + qb += 4; + qr += 4; + + nbQuaternions--; + } +} + +#else + +void arm_quaternion_product_f32(const float32_t *qa, + const float32_t *qb, + float32_t *qr, + uint32_t nbQuaternions) +{ + uint32_t i; + for(i=0; i < nbQuaternions; i++) + { + arm_quaternion_product_single_f32(qa, qb, qr); + + qa += 4; + qb += 4; + qr += 4; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of QuatProdVect group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_product_single_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_product_single_f32.c new file mode 100644 index 00000000..96f23e99 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_product_single_f32.c @@ -0,0 +1,107 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quaternion_product_single_f32.c + * Description: Floating-point quaternion product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + + +/** + @ingroup QuatProd + */ + +/** + @defgroup QuatProdSingle Quaternion Product + + Compute the product of two quaternions. + */ + +/** + @addtogroup QuatProdSingle + @{ + */ + +/** + @brief Floating-point product of two quaternions. + @param[in] qa first quaternion + @param[in] qb second quaternion + @param[out] qr product of two quaternions + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_quaternion_product_single_f32(const float32_t *qa, + const float32_t *qb, + float32_t *qr) +{ + static uint32_t patternA[4] = { 0, 1, 0, 1 }; + static uint32_t patternB[4] = { 3, 2, 3, 2 }; + static uint32_t patternC[4] = { 3, 2, 1, 0 }; + static float32_t signA[4] = { -1, -1, 1, 1 }; + + uint32x4_t vecA = vld1q_u32(patternA); + uint32x4_t vecB = vld1q_u32(patternB); + uint32x4_t vecC = vld1q_u32(patternC); + f32x4_t vecSignA = vld1q_f32(signA); + + + f32x4_t vecTmpA, vecTmpB, vecAcc; + + vecTmpA = vldrwq_gather_shifted_offset_f32(qa, vecA); + vecTmpB = vld1q_f32(qb); + + vecAcc = vcmulq_f32(vecTmpA, vecTmpB); + vecAcc = vcmlaq_rot90_f32(vecAcc, vecTmpA, vecTmpB); + + vecTmpA = vldrwq_gather_shifted_offset_f32(qa, vecB); + vecTmpB = vldrwq_gather_shifted_offset_f32(qb, vecC); + + vecTmpB = vecTmpB * vecSignA; + + vecAcc = vcmlaq_rot270_f32(vecAcc, vecTmpA, vecTmpB); + vecAcc = vcmlaq_f32(vecAcc, vecTmpA, vecTmpB); + + vst1q_f32(qr, vecAcc); +} + +#else +void arm_quaternion_product_single_f32(const float32_t *qa, + const float32_t *qb, + float32_t *qr) +{ + qr[0] = qa[0] * qb[0] - qa[1] * qb[1] - qa[2] * qb[2] - qa[3] * qb[3]; + qr[1] = qa[0] * qb[1] + qa[1] * qb[0] + qa[2] * qb[3] - qa[3] * qb[2]; + qr[2] = qa[0] * qb[2] + qa[2] * qb[0] + qa[3] * qb[1] - qa[1] * qb[3]; + qr[3] = qa[0] * qb[3] + qa[3] * qb[0] + qa[1] * qb[2] - qa[2] * qb[1]; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of QuatProdSingle group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_rotation2quaternion_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_rotation2quaternion_f32.c new file mode 100644 index 00000000..5d57492b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_rotation2quaternion_f32.c @@ -0,0 +1,225 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rotation2quaternion_f32.c + * Description: Floating-point rotation to quaternion conversion + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + +#define RI(x,y) r[(3*(x) + (y))] + + +/** + @ingroup QuatConv + */ + +/** + @defgroup RotQuat Rotation to Quaternion + + Conversions from rotation to quaternion. + */ + +/** + @addtogroup RotQuat + @{ + */ + +/** + * @brief Conversion of a rotation matrix to an equivalent quaternion. + * @param[in] pInputRotations points to an array 3x3 rotation matrix (in row order) + * @param[out] pOutputQuaternions points to an array quaternions + * @param[in] nbQuaternions number of quaternions in the array + * @return none. + * + * q and -q are representing the same rotation. This ambiguity must be taken into + * account when using the output of this function. + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +#define R00 vgetq_lane(q1,0) +#define R01 vgetq_lane(q1,1) +#define R02 vgetq_lane(q1,2) +#define R10 vgetq_lane(q1,3) +#define R11 vgetq_lane(q2,0) +#define R12 vgetq_lane(q2,1) +#define R20 vgetq_lane(q2,2) +#define R21 vgetq_lane(q2,3) +#define R22 ro22 + +void arm_rotation2quaternion_f32(const float32_t *pInputRotations, + float32_t *pOutputQuaternions, + uint32_t nbQuaternions) +{ + float32_t ro22, trace; + f32x4_t q1,q2, q; + + float32_t doubler; + float32_t s; + + q = vdupq_n_f32(0.0f); + + for(uint32_t nb=0; nb < nbQuaternions; nb++) + { + q1 = vld1q(pInputRotations); + pInputRotations += 4; + + q2 = vld1q(pInputRotations); + pInputRotations += 4; + + ro22 = *pInputRotations++; + + trace = R00 + R11 + R22; + + + if (trace > 0) + { + (void)arm_sqrt_f32(trace + 1.0f, &doubler) ; // invs=4*qw + doubler = 2.0f*doubler; + s = 1.0f / doubler; + + q1 = vmulq_n_f32(q1,s); + q2 = vmulq_n_f32(q2,s); + + q[0] = 0.25f * doubler; + q[1] = R21 - R12; + q[2] = R02 - R20; + q[3] = R10 - R01; + } + else if ((R00 > R11) && (R00 > R22) ) + { + (void)arm_sqrt_f32(1.0f + R00 - R11 - R22,&doubler); // invs=4*qx + doubler = 2.0f*doubler; + s = 1.0f / doubler; + + q1 = vmulq_n_f32(q1,s); + q2 = vmulq_n_f32(q2,s); + + q[0] = R21 - R12; + q[1] = 0.25f * doubler; + q[2] = R01 + R10; + q[3] = R02 + R20; + } + else if (R11 > R22) + { + (void)arm_sqrt_f32(1.0f + R11 - R00 - R22,&doubler); // invs=4*qy + doubler = 2.0f*doubler; + s = 1.0f / doubler; + + q1 = vmulq_n_f32(q1,s); + q2 = vmulq_n_f32(q2,s); + + q[0] = R02 - R20; + q[1] = R01 + R10; + q[2] = 0.25f * doubler; + q[3] = R12 + R21; + } + else + { + (void)arm_sqrt_f32(1.0f + R22 - R00 - R11,&doubler); // invs=4*qz + doubler = 2.0f*doubler; + s = 1.0f / doubler; + + q1 = vmulq_n_f32(q1,s); + q2 = vmulq_n_f32(q2,s); + + q[0] = R10 - R01; + q[1] = R02 + R20; + q[2] = R12 + R21; + q[3] = 0.25f * doubler; + } + + vst1q(pOutputQuaternions, q); + pOutputQuaternions += 4; + + } +} + +#else +void arm_rotation2quaternion_f32(const float32_t *pInputRotations, + float32_t *pOutputQuaternions, + uint32_t nbQuaternions) +{ + uint32_t nb; + for(nb=0; nb < nbQuaternions; nb++) + { + const float32_t *r=&pInputRotations[nb*9]; + float32_t *q=&pOutputQuaternions[nb*4]; + + float32_t trace = RI(0,0) + RI(1,1) + RI(2,2); + + float32_t doubler; + float32_t s; + + + + if (trace > 0.0f) + { + doubler = sqrtf(trace + 1.0f) * 2.0f; // invs=4*qw + s = 1.0f / doubler; + q[0] = 0.25f * doubler; + q[1] = (RI(2,1) - RI(1,2)) * s; + q[2] = (RI(0,2) - RI(2,0)) * s; + q[3] = (RI(1,0) - RI(0,1)) * s; + } + else if ((RI(0,0) > RI(1,1)) && (RI(0,0) > RI(2,2)) ) + { + doubler = sqrtf(1.0f + RI(0,0) - RI(1,1) - RI(2,2)) * 2.0f; // invs=4*qx + s = 1.0f / doubler; + q[0] = (RI(2,1) - RI(1,2)) * s; + q[1] = 0.25f * doubler; + q[2] = (RI(0,1) + RI(1,0)) * s; + q[3] = (RI(0,2) + RI(2,0)) * s; + } + else if (RI(1,1) > RI(2,2)) + { + doubler = sqrtf(1.0f + RI(1,1) - RI(0,0) - RI(2,2)) * 2.0f; // invs=4*qy + s = 1.0f / doubler; + q[0] = (RI(0,2) - RI(2,0)) * s; + q[1] = (RI(0,1) + RI(1,0)) * s; + q[2] = 0.25f * doubler; + q[3] = (RI(1,2) + RI(2,1)) * s; + } + else + { + doubler = sqrtf(1.0f + RI(2,2) - RI(0,0) - RI(1,1)) * 2.0f; // invs=4*qz + s = 1.0f / doubler; + q[0] = (RI(1,0) - RI(0,1)) * s; + q[1] = (RI(0,2) + RI(2,0)) * s; + q[2] = (RI(1,2) + RI(2,1)) * s; + q[3] = 0.25f * doubler; + } + + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of RotQuat group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/CMakeLists.txt new file mode 100644 index 00000000..eb1e0ca3 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/CMakeLists.txt @@ -0,0 +1,41 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPSVM) + +include(configLib) +include(configDsp) + + +add_library(CMSISDSPSVM STATIC) + +target_sources(CMSISDSPSVM PRIVATE arm_svm_linear_init_f32.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_rbf_init_f32.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_linear_predict_f32.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_rbf_predict_f32.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_polynomial_init_f32.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_sigmoid_init_f32.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_polynomial_predict_f32.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_sigmoid_predict_f32.c) + + + +configLib(CMSISDSPSVM ${ROOT}) +configDsp(CMSISDSPSVM ${ROOT}) + +### Includes +target_include_directories(CMSISDSPSVM PUBLIC "${DSP}/Include") + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPSVM PRIVATE arm_svm_linear_init_f16.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_rbf_init_f16.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_linear_predict_f16.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_rbf_predict_f16.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_polynomial_init_f16.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_sigmoid_init_f16.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_polynomial_predict_f16.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_sigmoid_predict_f16.c) +endif() + + + + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/SVMFunctions.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/SVMFunctions.c new file mode 100644 index 00000000..85f19b9e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/SVMFunctions.c @@ -0,0 +1,36 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: BayesFunctions.c + * Description: Combination of all SVM function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_svm_linear_init_f32.c" +#include "arm_svm_linear_predict_f32.c" +#include "arm_svm_polynomial_init_f32.c" +#include "arm_svm_polynomial_predict_f32.c" +#include "arm_svm_rbf_init_f32.c" +#include "arm_svm_rbf_predict_f32.c" +#include "arm_svm_sigmoid_init_f32.c" +#include "arm_svm_sigmoid_predict_f32.c" diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/SVMFunctionsF16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/SVMFunctionsF16.c new file mode 100644 index 00000000..74d26652 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/SVMFunctionsF16.c @@ -0,0 +1,36 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: BayesFunctions.c + * Description: Combination of all SVM function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_svm_linear_init_f16.c" +#include "arm_svm_linear_predict_f16.c" +#include "arm_svm_polynomial_init_f16.c" +#include "arm_svm_polynomial_predict_f16.c" +#include "arm_svm_rbf_init_f16.c" +#include "arm_svm_rbf_predict_f16.c" +#include "arm_svm_sigmoid_init_f16.c" +#include "arm_svm_sigmoid_predict_f16.c" diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_init_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_init_f16.c new file mode 100644 index 00000000..a3ebc7f7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_init_f16.c @@ -0,0 +1,98 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_linear_init_f16.c + * Description: SVM Linear Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + * @defgroup groupSVM SVM Functions + * + */ + +/** + @ingroup groupSVM + */ + +/** + @defgroup linearsvm Linear SVM + + Linear SVM classifier + */ + +/** + * @addtogroup linearsvm + * @{ + */ + + +/** + * @brief SVM linear instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S Parameters for the SVM function + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @return none. + * + */ + + +void arm_svm_linear_init_f16(arm_svm_linear_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; +} + + + +/** + * @} end of linearsvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_init_f32.c new file mode 100644 index 00000000..75395aa9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_init_f32.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_linear_init_f32.c + * Description: SVM Linear Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + +/** + * @defgroup groupSVM SVM Functions + * + */ + +/** + @ingroup groupSVM + */ + +/** + @defgroup linearsvm Linear SVM + + Linear SVM classifier + */ + +/** + * @addtogroup linearsvm + * @{ + */ + + +/** + * @brief SVM linear instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S Parameters for the SVM function + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @return none. + * + */ + + +void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; +} + + + +/** + * @} end of linearsvm group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_predict_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_predict_f16.c new file mode 100644 index 00000000..494ef9a6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_predict_f16.c @@ -0,0 +1,314 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_linear_predict_f16.c + * Description: SVM Linear Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + + +/** + * @addtogroup linearsvm + * @{ + */ + + +/** + * @brief SVM linear prediction + * @param[in] S Pointer to an instance of the linear SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_svm_linear_predict_f16( + const arm_svm_linear_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float16_t *pSupport = S->supportVectors; + const float16_t *pSrcA = pSupport; + const float16_t *pInA0; + const float16_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float16_t *pDualCoef = S->dualCoefficients; + _Float16 sum = S->intercept; + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) + { + const float16_t *pInA2, *pInA3; + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f16x8_t vecIn, acc0, acc1, acc2, acc3; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + acc2 = vdupq_n_f16(0.0f); + acc3 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 8; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 8; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA2Vec, p0); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA3Vec, p0); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + acc0 = vmulq_n_f16(acc0,*pDualCoef++); + acc0 = vfmaq_n_f16(acc0,acc1,*pDualCoef++); + acc0 = vfmaq_n_f16(acc0,acc2,*pDualCoef++); + acc0 = vfmaq_n_f16(acc0,acc3,*pDualCoef++); + + sum += (_Float16)vecAddAcrossF16Mve(acc0); + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parallel + */ + if (row >= 2) { + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f16x8_t vecIn, acc0, acc1; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + acc0 = vmulq_n_f16(acc0,*pDualCoef++); + acc0 = vfmaq_n_f16(acc0,acc1,*pDualCoef++); + + sum += (_Float16)vecAddAcrossF16Mve(acc0); + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f16x8_t vecIn, acc0; + float16_t const *pSrcA0Vec, *pInVec; + float16_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + sum += (_Float16)*pDualCoef++ * (_Float16)vecAddAcrossF16Mve(acc0); + + } + + *pResult = S->classes[STEP(sum)]; +} + +#else +void arm_svm_linear_predict_f16( + const arm_svm_linear_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + _Float16 sum=S->intercept; + _Float16 dot=0; + uint32_t i,j; + const float16_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + in[j]* *pSupport++; + } + sum += S->dualCoefficients[i] * dot; + } + *pResult=S->classes[STEP(sum)]; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of linearsvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_predict_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_predict_f32.c new file mode 100644 index 00000000..caf09df0 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_predict_f32.c @@ -0,0 +1,461 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_linear_predict_f32.c + * Description: SVM Linear Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + + +/** + * @addtogroup linearsvm + * @{ + */ + + +/** + * @brief SVM linear prediction + * @param[in] S Pointer to an instance of the linear SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_svm_linear_predict_f32( + const arm_svm_linear_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float32_t *pSupport = S->supportVectors; + const float32_t *pSrcA = pSupport; + const float32_t *pInA0; + const float32_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float32_t *pDualCoef = S->dualCoefficients; + float32_t sum = S->intercept; + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) + { + const float32_t *pInA2, *pInA3; + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f32x4_t vecIn, acc0, acc1, acc2, acc3; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 4; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 4; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA2Vec, p0); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA3Vec, p0); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + + acc0 = vmulq_n_f32(acc0,*pDualCoef++); + acc0 = vfmaq_n_f32(acc0,acc1,*pDualCoef++); + acc0 = vfmaq_n_f32(acc0,acc2,*pDualCoef++); + acc0 = vfmaq_n_f32(acc0,acc3,*pDualCoef++); + + sum += vecAddAcrossF32Mve(acc0); + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parallel + */ + if (row >= 2) { + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f32x4_t vecIn, acc0, acc1; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + acc0 = vmulq_n_f32(acc0,*pDualCoef++); + acc0 = vfmaq_n_f32(acc0,acc1,*pDualCoef++); + + sum += vecAddAcrossF32Mve(acc0); + + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f32x4_t vecIn, acc0; + float32_t const *pSrcA0Vec, *pInVec; + float32_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + sum += *pDualCoef++ * vecAddAcrossF32Mve(acc0); + + } + + *pResult = S->classes[STEP(sum)]; +} + +#else +#if defined(ARM_MATH_NEON) +void arm_svm_linear_predict_f32( + const arm_svm_linear_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum = S->intercept; + + float32_t dot; + float32x4_t dotV; + + float32x4_t accuma,accumb,accumc,accumd,accum; + float32x2_t accum2; + float32x4_t vec1; + + float32x4_t vec2,vec2a,vec2b,vec2c,vec2d; + + uint32_t blkCnt; + uint32_t vectorBlkCnt; + + const float32_t *pIn = in; + + const float32_t *pSupport = S->supportVectors; + + const float32_t *pSupporta = S->supportVectors; + const float32_t *pSupportb; + const float32_t *pSupportc; + const float32_t *pSupportd; + + pSupportb = pSupporta + S->vectorDimension; + pSupportc = pSupportb + S->vectorDimension; + pSupportd = pSupportc + S->vectorDimension; + + const float32_t *pDualCoefs = S->dualCoefficients; + + vectorBlkCnt = S->nbOfSupportVectors >> 2; + + while (vectorBlkCnt > 0U) + { + accuma = vdupq_n_f32(0); + accumb = vdupq_n_f32(0); + accumc = vdupq_n_f32(0); + accumd = vdupq_n_f32(0); + + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2a = vld1q_f32(pSupporta); + vec2b = vld1q_f32(pSupportb); + vec2c = vld1q_f32(pSupportc); + vec2d = vld1q_f32(pSupportd); + + pIn += 4; + pSupporta += 4; + pSupportb += 4; + pSupportc += 4; + pSupportd += 4; + + accuma = vmlaq_f32(accuma, vec1,vec2a); + accumb = vmlaq_f32(accumb, vec1,vec2b); + accumc = vmlaq_f32(accumc, vec1,vec2c); + accumd = vmlaq_f32(accumd, vec1,vec2d); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accuma),vget_high_f32(accuma)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,0); + + accum2 = vpadd_f32(vget_low_f32(accumb),vget_high_f32(accumb)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,1); + + accum2 = vpadd_f32(vget_low_f32(accumc),vget_high_f32(accumc)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,2); + + accum2 = vpadd_f32(vget_low_f32(accumd),vget_high_f32(accumd)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,3); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,0) + *pIn * *pSupporta++, dotV,0); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,1) + *pIn * *pSupportb++, dotV,1); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,2) + *pIn * *pSupportc++, dotV,2); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,3) + *pIn * *pSupportd++, dotV,3); + + pIn++; + + blkCnt -- ; + } + + vec1 = vld1q_f32(pDualCoefs); + pDualCoefs += 4; + + accum = vmulq_f32(vec1,dotV); + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + sum += vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + pSupporta += 3*S->vectorDimension; + pSupportb += 3*S->vectorDimension; + pSupportc += 3*S->vectorDimension; + pSupportd += 3*S->vectorDimension; + + vectorBlkCnt -- ; + } + + pSupport = pSupporta; + vectorBlkCnt = S->nbOfSupportVectors & 3; + while (vectorBlkCnt > 0U) + { + accum = vdupq_n_f32(0); + dot = 0.0f; + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2 = vld1q_f32(pSupport); + pIn += 4; + pSupport += 4; + + accum = vmlaq_f32(accum, vec1,vec2); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + dot = vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + dot = dot + *pIn++ * *pSupport++; + + blkCnt -- ; + } + + sum += *pDualCoefs++ * dot; + vectorBlkCnt -- ; + } + + *pResult=S->classes[STEP(sum)]; +} +#else +void arm_svm_linear_predict_f32( + const arm_svm_linear_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum=S->intercept; + float32_t dot=0; + uint32_t i,j; + const float32_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + in[j]* *pSupport++; + } + sum += S->dualCoefficients[i] * dot; + } + *pResult=S->classes[STEP(sum)]; +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of linearsvm group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_init_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_init_f16.c new file mode 100644 index 00000000..558ab450 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_init_f16.c @@ -0,0 +1,103 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_polynomial_init_f16.c + * Description: SVM Polynomial Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupSVM + */ + +/** + @defgroup polysvm Polynomial SVM + + Polynomial SVM classifier + */ + +/** + * @addtogroup polysvm + * @{ + */ + + +/** + * @brief SVM polynomial instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] degree Polynomial degree + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + + +void arm_svm_polynomial_init_f16(arm_svm_polynomial_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + int32_t degree, + float16_t coef0, + float16_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->degree = degree; + S->coef0 = coef0; + S->gamma = gamma; +} + + + +/** + * @} end of polysvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_init_f32.c new file mode 100644 index 00000000..7d33cd79 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_init_f32.c @@ -0,0 +1,97 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_polynomial_init_f32.c + * Description: SVM Polynomial Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + +/** + @ingroup groupSVM + */ + +/** + @defgroup polysvm Polynomial SVM + + Polynomial SVM classifier + */ + +/** + * @addtogroup polysvm + * @{ + */ + + +/** + * @brief SVM polynomial instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] degree Polynomial degree + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + + +void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + int32_t degree, + float32_t coef0, + float32_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->degree = degree; + S->coef0 = coef0; + S->gamma = gamma; +} + + + +/** + * @} end of polysvm group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_predict_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_predict_f16.c new file mode 100644 index 00000000..e3e2d6a2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_predict_f16.c @@ -0,0 +1,336 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_polynomial_predict_f16.c + * Description: SVM Polynomial Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + + +/** + * @addtogroup polysvm + * @{ + */ + + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math_f16.h" + +void arm_svm_polynomial_predict_f16( + const arm_svm_polynomial_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float16_t *pSupport = S->supportVectors; + const float16_t *pSrcA = pSupport; + const float16_t *pInA0; + const float16_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float16_t *pDualCoef = S->dualCoefficients; + _Float16 sum = S->intercept; + f16x8_t vSum = vdupq_n_f16(0.0f); + + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) { + const float16_t *pInA2, *pInA3; + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f16x8_t vecIn, acc0, acc1, acc2, acc3; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + acc2 = vdupq_n_f16(0.0f); + acc3 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 8; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 8; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA2Vec, p0); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA3Vec, p0); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc1), vtmp, 1); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc2), vtmp, 2); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc3), vtmp, 3); + + vSum = vfmaq_m_f16(vSum, vld1q(pDualCoef), + arm_vec_exponent_f16 + (vaddq_n_f16(vmulq_n_f16(vtmp, S->gamma), S->coef0), + S->degree),vctp16q(4)); + + pDualCoef += 4; + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) { + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f16x8_t vecIn, acc0, acc1; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc1), vtmp, 1); + + vSum = vfmaq_m_f16(vSum, vld1q(pDualCoef), + arm_vec_exponent_f16 + (vaddq_n_f16(vmulq_n_f16(vtmp, S->gamma), S->coef0), S->degree), + vctp16q(2)); + + pDualCoef += 2; + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f16x8_t vecIn, acc0; + float16_t const *pSrcA0Vec, *pInVec; + float16_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + vSum = vfmaq_m_f16(vSum, vld1q(pDualCoef), + arm_vec_exponent_f16 + (vaddq_n_f16(vmulq_n_f16(vtmp, S->gamma), S->coef0), S->degree), + vctp16q(1)); + } + sum += (_Float16)vecAddAcrossF16Mve(vSum); + + + *pResult = S->classes[STEP(sum)]; +} + +#else +void arm_svm_polynomial_predict_f16( + const arm_svm_polynomial_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + _Float16 sum=S->intercept; + _Float16 dot=0; + uint32_t i,j; + const float16_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + (_Float16)in[j]* (_Float16)*pSupport++; + } + sum += S->dualCoefficients[i] * (_Float16)arm_exponent_f16(S->gamma * dot + S->coef0, S->degree); + } + + *pResult=S->classes[STEP(sum)]; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of polysvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_predict_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_predict_f32.c new file mode 100644 index 00000000..13b1f84c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_predict_f32.c @@ -0,0 +1,490 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_polynomial_predict_f32.c + * Description: SVM Polynomial Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_vec_math.h" +#endif + +/** + * @addtogroup polysvm + * @{ + */ + + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +void arm_svm_polynomial_predict_f32( + const arm_svm_polynomial_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float32_t *pSupport = S->supportVectors; + const float32_t *pSrcA = pSupport; + const float32_t *pInA0; + const float32_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float32_t *pDualCoef = S->dualCoefficients; + float32_t sum = S->intercept; + f32x4_t vSum = vdupq_n_f32(0.0f); + + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) { + const float32_t *pInA2, *pInA3; + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f32x4_t vecIn, acc0, acc1, acc2, acc3; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 4; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 4; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA2Vec, p0); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA3Vec, p0); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc1), vtmp, 1); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc2), vtmp, 2); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc3), vtmp, 3); + + vSum = vfmaq_f32(vSum, vld1q(pDualCoef), + arm_vec_exponent_f32 + (vaddq_n_f32(vmulq_n_f32(vtmp, S->gamma), S->coef0), S->degree)); + + pDualCoef += 4; + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) { + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f32x4_t vecIn, acc0, acc1; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc1), vtmp, 1); + + vSum = vfmaq_m_f32(vSum, vld1q(pDualCoef), + arm_vec_exponent_f32 + (vaddq_n_f32(vmulq_n_f32(vtmp, S->gamma), S->coef0), S->degree), + vctp32q(2)); + + pDualCoef += 2; + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f32x4_t vecIn, acc0; + float32_t const *pSrcA0Vec, *pInVec; + float32_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + vSum = vfmaq_m_f32(vSum, vld1q(pDualCoef), + arm_vec_exponent_f32 + (vaddq_n_f32(vmulq_n_f32(vtmp, S->gamma), S->coef0), S->degree), + vctp32q(1)); + } + sum += vecAddAcrossF32Mve(vSum); + + + *pResult = S->classes[STEP(sum)]; +} + +#else +#if defined(ARM_MATH_NEON) +void arm_svm_polynomial_predict_f32( + const arm_svm_polynomial_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum = S->intercept; + + float32_t dot; + float32x4_t dotV; + + float32x4_t accuma,accumb,accumc,accumd,accum; + float32x2_t accum2; + float32x4_t vec1; + float32x4_t coef0 = vdupq_n_f32(S->coef0); + + float32x4_t vec2,vec2a,vec2b,vec2c,vec2d; + + uint32_t blkCnt; + uint32_t vectorBlkCnt; + + const float32_t *pIn = in; + + const float32_t *pSupport = S->supportVectors; + + const float32_t *pSupporta = S->supportVectors; + const float32_t *pSupportb; + const float32_t *pSupportc; + const float32_t *pSupportd; + + pSupportb = pSupporta + S->vectorDimension; + pSupportc = pSupportb + S->vectorDimension; + pSupportd = pSupportc + S->vectorDimension; + + const float32_t *pDualCoefs = S->dualCoefficients; + + vectorBlkCnt = S->nbOfSupportVectors >> 2; + while (vectorBlkCnt > 0U) + { + accuma = vdupq_n_f32(0); + accumb = vdupq_n_f32(0); + accumc = vdupq_n_f32(0); + accumd = vdupq_n_f32(0); + + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2a = vld1q_f32(pSupporta); + vec2b = vld1q_f32(pSupportb); + vec2c = vld1q_f32(pSupportc); + vec2d = vld1q_f32(pSupportd); + + pIn += 4; + pSupporta += 4; + pSupportb += 4; + pSupportc += 4; + pSupportd += 4; + + accuma = vmlaq_f32(accuma, vec1,vec2a); + accumb = vmlaq_f32(accumb, vec1,vec2b); + accumc = vmlaq_f32(accumc, vec1,vec2c); + accumd = vmlaq_f32(accumd, vec1,vec2d); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accuma),vget_high_f32(accuma)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,0); + + accum2 = vpadd_f32(vget_low_f32(accumb),vget_high_f32(accumb)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,1); + + accum2 = vpadd_f32(vget_low_f32(accumc),vget_high_f32(accumc)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,2); + + accum2 = vpadd_f32(vget_low_f32(accumd),vget_high_f32(accumd)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,3); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,0) + *pIn * *pSupporta++, dotV,0); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,1) + *pIn * *pSupportb++, dotV,1); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,2) + *pIn * *pSupportc++, dotV,2); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,3) + *pIn * *pSupportd++, dotV,3); + + pIn++; + + blkCnt -- ; + } + + vec1 = vld1q_f32(pDualCoefs); + pDualCoefs += 4; + + // To vectorize later + dotV = vmulq_n_f32(dotV, S->gamma); + dotV = vaddq_f32(dotV, coef0); + + dotV = arm_vec_exponent_f32(dotV,S->degree); + + accum = vmulq_f32(vec1,dotV); + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + sum += vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + pSupporta += 3*S->vectorDimension; + pSupportb += 3*S->vectorDimension; + pSupportc += 3*S->vectorDimension; + pSupportd += 3*S->vectorDimension; + + vectorBlkCnt -- ; + } + + pSupport = pSupporta; + vectorBlkCnt = S->nbOfSupportVectors & 3; + + while (vectorBlkCnt > 0U) + { + accum = vdupq_n_f32(0); + dot = 0.0f; + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2 = vld1q_f32(pSupport); + pIn += 4; + pSupport += 4; + + accum = vmlaq_f32(accum, vec1,vec2); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + dot = vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + dot = dot + *pIn++ * *pSupport++; + + blkCnt -- ; + } + + sum += *pDualCoefs++ * arm_exponent_f32(S->gamma * dot + S->coef0, S->degree); + vectorBlkCnt -- ; + } + + *pResult=S->classes[STEP(sum)]; +} +#else +void arm_svm_polynomial_predict_f32( + const arm_svm_polynomial_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum=S->intercept; + float32_t dot=0; + uint32_t i,j; + const float32_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + in[j]* *pSupport++; + } + sum += S->dualCoefficients[i] * arm_exponent_f32(S->gamma * dot + S->coef0, S->degree); + } + + *pResult=S->classes[STEP(sum)]; +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of polysvm group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_init_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_init_f16.c new file mode 100644 index 00000000..43de2498 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_init_f16.c @@ -0,0 +1,97 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_rbf_init_f16.c + * Description: SVM Radial Basis Function Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupSVM + */ + +/** + @defgroup rbfsvm RBF SVM + + RBF SVM classifier + */ + + +/** + * @addtogroup rbfsvm + * @{ + */ + + +/** + * @brief SVM radial basis function instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_rbf_init_f16(arm_svm_rbf_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + float16_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->gamma = gamma; +} + + + +/** + * @} end of rbfsvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_init_f32.c new file mode 100644 index 00000000..77bf2824 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_init_f32.c @@ -0,0 +1,91 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_rbf_init_f32.c + * Description: SVM Radial Basis Function Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + +/** + @ingroup groupSVM + */ + +/** + @defgroup rbfsvm RBF SVM + + RBF SVM classifier + */ + + +/** + * @addtogroup rbfsvm + * @{ + */ + + +/** + * @brief SVM radial basis function instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->gamma = gamma; +} + + + +/** + * @} end of rbfsvm group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_predict_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_predict_f16.c new file mode 100644 index 00000000..7724fda2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_predict_f16.c @@ -0,0 +1,352 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_rbf_predict_f16.c + * Description: SVM Radial Basis Function Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + + +/** + * @addtogroup rbfsvm + * @{ + */ + + +/** + * @brief SVM rbf prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult decision value + * @return none. + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math_f16.h" + +void arm_svm_rbf_predict_f16( + const arm_svm_rbf_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float16_t *pSupport = S->supportVectors; + const float16_t *pSrcA = pSupport; + const float16_t *pInA0; + const float16_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float16_t *pDualCoef = S->dualCoefficients; + _Float16 sum = S->intercept; + f16x8_t vSum = vdupq_n_f16(0); + + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) { + const float16_t *pInA2, *pInA3; + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f16x8_t vecIn, acc0, acc1, acc2, acc3; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + acc2 = vdupq_n_f16(0.0f); + acc3 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + f16x8_t vecDif; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 8; + vecDif = vsubq(vecIn, vecA); + acc2 = vfmaq(acc2, vecDif, vecDif); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 8; + vecDif = vsubq(vecIn, vecA); + acc3 = vfmaq(acc3, vecDif, vecDif); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + f16x8_t vecDif; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + vecA = vldrhq_z_f16(pSrcA2Vec, p0);; + vecDif = vsubq(vecIn, vecA); + acc2 = vfmaq(acc2, vecDif, vecDif); + vecA = vldrhq_z_f16(pSrcA3Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc3 = vfmaq(acc3, vecDif, vecDif); + } + /* + * Sum the partial parts + */ + + //sum += *pDualCoef++ * expf(-S->gamma * vecReduceF16Mve(acc0)); + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc1), vtmp, 1); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc2), vtmp, 2); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc3), vtmp, 3); + + vSum = + vfmaq_m_f16(vSum, vld1q(pDualCoef), + vexpq_f16(vmulq_n_f16(vtmp, -S->gamma)),vctp16q(4)); + pDualCoef += 4; + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) { + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f16x8_t vecIn, acc0, acc1; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + f16x8_t vecDif; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif);; + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA, vecDif; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc1), vtmp, 1); + + vSum = + vfmaq_m_f16(vSum, vld1q(pDualCoef), + vexpq_f16(vmulq_n_f16(vtmp, -S->gamma)), vctp16q(2)); + pDualCoef += 2; + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f16x8_t vecIn, acc0; + float16_t const *pSrcA0Vec, *pInVec; + float16_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA, vecDif; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA, vecDif; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + + vSum = + vfmaq_m_f16(vSum, vld1q(pDualCoef), + vexpq_f16(vmulq_n_f16(vtmp, -S->gamma)), vctp16q(1)); + + } + + + sum += vecAddAcrossF16Mve(vSum); + *pResult = S->classes[STEP(sum)]; +} + +#else +void arm_svm_rbf_predict_f16( + const arm_svm_rbf_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + _Float16 sum=S->intercept; + _Float16 dot=00.f16; + uint32_t i,j; + const float16_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0.0f16; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + SQ((_Float16)in[j] - (_Float16) *pSupport); + pSupport++; + } + sum += (_Float16)S->dualCoefficients[i] * (_Float16)expf(-(_Float16)S->gamma * dot); + } + *pResult=S->classes[STEP(sum)]; +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of rbfsvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_predict_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_predict_f32.c new file mode 100644 index 00000000..d3c43bf6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_predict_f32.c @@ -0,0 +1,523 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_rbf_predict_f32.c + * Description: SVM Radial Basis Function Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + + +/** + * @addtogroup rbfsvm + * @{ + */ + + +/** + * @brief SVM rbf prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult decision value + * @return none. + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +void arm_svm_rbf_predict_f32( + const arm_svm_rbf_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float32_t *pSupport = S->supportVectors; + const float32_t *pSrcA = pSupport; + const float32_t *pInA0; + const float32_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float32_t *pDualCoef = S->dualCoefficients; + float32_t sum = S->intercept; + f32x4_t vSum = vdupq_n_f32(0); + + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) { + const float32_t *pInA2, *pInA3; + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f32x4_t vecIn, acc0, acc1, acc2, acc3; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + f32x4_t vecDif; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 4; + vecDif = vsubq(vecIn, vecA); + acc2 = vfmaq(acc2, vecDif, vecDif); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 4; + vecDif = vsubq(vecIn, vecA); + acc3 = vfmaq(acc3, vecDif, vecDif); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + f32x4_t vecDif; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + vecA = vldrwq_z_f32(pSrcA2Vec, p0);; + vecDif = vsubq(vecIn, vecA); + acc2 = vfmaq(acc2, vecDif, vecDif); + vecA = vldrwq_z_f32(pSrcA3Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc3 = vfmaq(acc3, vecDif, vecDif); + } + /* + * Sum the partial parts + */ + + //sum += *pDualCoef++ * expf(-S->gamma * vecReduceF32Mve(acc0)); + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc1), vtmp, 1); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc2), vtmp, 2); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc3), vtmp, 3); + + vSum = + vfmaq_f32(vSum, vld1q(pDualCoef), + vexpq_f32(vmulq_n_f32(vtmp, -S->gamma))); + pDualCoef += 4; + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) { + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f32x4_t vecIn, acc0, acc1; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + f32x4_t vecDif; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif);; + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA, vecDif; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc1), vtmp, 1); + + vSum = + vfmaq_m_f32(vSum, vld1q(pDualCoef), + vexpq_f32(vmulq_n_f32(vtmp, -S->gamma)), vctp32q(2)); + pDualCoef += 2; + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f32x4_t vecIn, acc0; + float32_t const *pSrcA0Vec, *pInVec; + float32_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA, vecDif; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA, vecDif; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + + vSum = + vfmaq_m_f32(vSum, vld1q(pDualCoef), + vexpq_f32(vmulq_n_f32(vtmp, -S->gamma)), vctp32q(1)); + + } + + + sum += vecAddAcrossF32Mve(vSum); + *pResult = S->classes[STEP(sum)]; +} + + +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +void arm_svm_rbf_predict_f32( + const arm_svm_rbf_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum = S->intercept; + + float32_t dot; + float32x4_t dotV; + + float32x4_t accuma,accumb,accumc,accumd,accum; + float32x2_t accum2; + float32x4_t temp; + float32x4_t vec1; + + float32x4_t vec2,vec2a,vec2b,vec2c,vec2d; + + uint32_t blkCnt; + uint32_t vectorBlkCnt; + + const float32_t *pIn = in; + + const float32_t *pSupport = S->supportVectors; + + const float32_t *pSupporta = S->supportVectors; + const float32_t *pSupportb; + const float32_t *pSupportc; + const float32_t *pSupportd; + + pSupportb = pSupporta + S->vectorDimension; + pSupportc = pSupportb + S->vectorDimension; + pSupportd = pSupportc + S->vectorDimension; + + const float32_t *pDualCoefs = S->dualCoefficients; + + + vectorBlkCnt = S->nbOfSupportVectors >> 2; + while (vectorBlkCnt > 0U) + { + accuma = vdupq_n_f32(0); + accumb = vdupq_n_f32(0); + accumc = vdupq_n_f32(0); + accumd = vdupq_n_f32(0); + + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2a = vld1q_f32(pSupporta); + vec2b = vld1q_f32(pSupportb); + vec2c = vld1q_f32(pSupportc); + vec2d = vld1q_f32(pSupportd); + + pIn += 4; + pSupporta += 4; + pSupportb += 4; + pSupportc += 4; + pSupportd += 4; + + temp = vsubq_f32(vec1, vec2a); + accuma = vmlaq_f32(accuma, temp, temp); + + temp = vsubq_f32(vec1, vec2b); + accumb = vmlaq_f32(accumb, temp, temp); + + temp = vsubq_f32(vec1, vec2c); + accumc = vmlaq_f32(accumc, temp, temp); + + temp = vsubq_f32(vec1, vec2d); + accumd = vmlaq_f32(accumd, temp, temp); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accuma),vget_high_f32(accuma)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,0); + + accum2 = vpadd_f32(vget_low_f32(accumb),vget_high_f32(accumb)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,1); + + accum2 = vpadd_f32(vget_low_f32(accumc),vget_high_f32(accumc)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,2); + + accum2 = vpadd_f32(vget_low_f32(accumd),vget_high_f32(accumd)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,3); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,0) + SQ(*pIn - *pSupporta), dotV,0); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,1) + SQ(*pIn - *pSupportb), dotV,1); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,2) + SQ(*pIn - *pSupportc), dotV,2); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,3) + SQ(*pIn - *pSupportd), dotV,3); + + pSupporta++; + pSupportb++; + pSupportc++; + pSupportd++; + + pIn++; + + blkCnt -- ; + } + + vec1 = vld1q_f32(pDualCoefs); + pDualCoefs += 4; + + // To vectorize later + dotV = vmulq_n_f32(dotV, -S->gamma); + dotV = vexpq_f32(dotV); + + accum = vmulq_f32(vec1,dotV); + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + sum += vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + pSupporta += 3*S->vectorDimension; + pSupportb += 3*S->vectorDimension; + pSupportc += 3*S->vectorDimension; + pSupportd += 3*S->vectorDimension; + + vectorBlkCnt -- ; + } + + pSupport = pSupporta; + vectorBlkCnt = S->nbOfSupportVectors & 3; + + while (vectorBlkCnt > 0U) + { + accum = vdupq_n_f32(0); + dot = 0.0f; + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2 = vld1q_f32(pSupport); + pIn += 4; + pSupport += 4; + + temp = vsubq_f32(vec1,vec2); + accum = vmlaq_f32(accum, temp,temp); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + dot = vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + + dot = dot + SQ(*pIn - *pSupport); + pIn++; + pSupport++; + + blkCnt -- ; + } + + sum += *pDualCoefs++ * expf(-S->gamma * dot); + vectorBlkCnt -- ; + } + + *pResult=S->classes[STEP(sum)]; +} +#else +void arm_svm_rbf_predict_f32( + const arm_svm_rbf_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum=S->intercept; + float32_t dot=0; + uint32_t i,j; + const float32_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + SQ(in[j] - *pSupport); + pSupport++; + } + sum += S->dualCoefficients[i] * expf(-S->gamma * dot); + } + *pResult=S->classes[STEP(sum)]; +} +#endif + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of rbfsvm group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_init_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_init_f16.c new file mode 100644 index 00000000..7a27417f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_init_f16.c @@ -0,0 +1,98 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_sigmoid_predict_f16.c + * Description: SVM Sigmoid Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupSVM + */ + +/** + @defgroup sigmoidsvm Sigmoid SVM + + Sigmoid SVM classifier + */ + +/** + * @addtogroup sigmoidsvm + * @{ + */ + + +/** + * @brief SVM sigmoid instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the rbf SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_sigmoid_init_f16(arm_svm_sigmoid_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + float16_t coef0, + float16_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->coef0 = coef0; + S->gamma = gamma; +} + + +/** + * @} end of sigmoidsvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_init_f32.c new file mode 100644 index 00000000..a7f16c28 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_init_f32.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_sigmoid_predict_f32.c + * Description: SVM Sigmoid Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + +/** + @ingroup groupSVM + */ + +/** + @defgroup sigmoidsvm Sigmoid SVM + + Sigmoid SVM classifier + */ + +/** + * @addtogroup sigmoidsvm + * @{ + */ + + +/** + * @brief SVM sigmoid instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the rbf SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t coef0, + float32_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->coef0 = coef0; + S->gamma = gamma; +} + + +/** + * @} end of sigmoidsvm group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_predict_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_predict_f16.c new file mode 100644 index 00000000..670806b5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_predict_f16.c @@ -0,0 +1,333 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_sigmoid_predict_f16.c + * Description: SVM Sigmoid Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + * @addtogroup sigmoidsvm + * @{ + */ + + + +/** + * @brief SVM sigmoid prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math_f16.h" + +void arm_svm_sigmoid_predict_f16( + const arm_svm_sigmoid_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float16_t *pSupport = S->supportVectors; + const float16_t *pSrcA = pSupport; + const float16_t *pInA0; + const float16_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float16_t *pDualCoef = S->dualCoefficients; + _Float16 sum = S->intercept; + f16x8_t vSum = vdupq_n_f16(0.0f); + + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) { + const float16_t *pInA2, *pInA3; + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f16x8_t vecIn, acc0, acc1, acc2, acc3; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + acc2 = vdupq_n_f16(0.0f); + acc3 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 8; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 8; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA2Vec, p0); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA3Vec, p0); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc1), vtmp, 1); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc2), vtmp, 2); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc3), vtmp, 3); + + vSum = + vfmaq_m_f16(vSum, vld1q(pDualCoef), + vtanhq_f16(vaddq_n_f16(vmulq_n_f16(vtmp, S->gamma), S->coef0)),vctp16q(4)); + + pDualCoef += 4; + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) { + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f16x8_t vecIn, acc0, acc1; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc1), vtmp, 1); + + vSum = + vfmaq_m_f16(vSum, vld1q(pDualCoef), + vtanhq_f16(vaddq_n_f16(vmulq_n_f16(vtmp, S->gamma), S->coef0)), + vctp16q(2)); + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f16x8_t vecIn, acc0; + float16_t const *pSrcA0Vec, *pInVec; + float16_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + + vSum = + vfmaq_m_f16(vSum, vld1q(pDualCoef), + vtanhq_f16(vaddq_n_f16(vmulq_n_f16(vtmp, S->gamma), S->coef0)), + vctp16q(1)); + } + sum += vecAddAcrossF16Mve(vSum); + + *pResult = S->classes[STEP(sum)]; +} + +#else +void arm_svm_sigmoid_predict_f16( + const arm_svm_sigmoid_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + _Float16 sum=S->intercept; + _Float16 dot=0.0f16; + uint32_t i,j; + const float16_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0.0f16; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + (_Float16)in[j] * (_Float16)*pSupport++; + } + sum += (_Float16)S->dualCoefficients[i] * (_Float16)tanhf((_Float16)S->gamma * dot + (_Float16)S->coef0); + } + *pResult=S->classes[STEP(sum)]; +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of sigmoidsvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_predict_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_predict_f32.c new file mode 100644 index 00000000..37c8a080 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_predict_f32.c @@ -0,0 +1,487 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_sigmoid_predict_f32.c + * Description: SVM Sigmoid Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + +/** + * @addtogroup sigmoidsvm + * @{ + */ + + + +/** + * @brief SVM sigmoid prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +void arm_svm_sigmoid_predict_f32( + const arm_svm_sigmoid_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float32_t *pSupport = S->supportVectors; + const float32_t *pSrcA = pSupport; + const float32_t *pInA0; + const float32_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float32_t *pDualCoef = S->dualCoefficients; + float32_t sum = S->intercept; + f32x4_t vSum = vdupq_n_f32(0.0f); + + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) { + const float32_t *pInA2, *pInA3; + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f32x4_t vecIn, acc0, acc1, acc2, acc3; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 4; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 4; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA2Vec, p0); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA3Vec, p0); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc1), vtmp, 1); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc2), vtmp, 2); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc3), vtmp, 3); + + vSum = + vfmaq_f32(vSum, vld1q(pDualCoef), + vtanhq_f32(vaddq_n_f32(vmulq_n_f32(vtmp, S->gamma), S->coef0))); + + pDualCoef += 4; + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) { + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f32x4_t vecIn, acc0, acc1; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc1), vtmp, 1); + + vSum = + vfmaq_m_f32(vSum, vld1q(pDualCoef), + vtanhq_f32(vaddq_n_f32(vmulq_n_f32(vtmp, S->gamma), S->coef0)), + vctp32q(2)); + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f32x4_t vecIn, acc0; + float32_t const *pSrcA0Vec, *pInVec; + float32_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + + vSum = + vfmaq_m_f32(vSum, vld1q(pDualCoef), + vtanhq_f32(vaddq_n_f32(vmulq_n_f32(vtmp, S->gamma), S->coef0)), + vctp32q(1)); + } + sum += vecAddAcrossF32Mve(vSum); + + *pResult = S->classes[STEP(sum)]; +} + +#else +#if defined(ARM_MATH_NEON) +#include "NEMath.h" + +void arm_svm_sigmoid_predict_f32( + const arm_svm_sigmoid_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum = S->intercept; + + float32_t dot; + float32x4_t dotV; + + float32x4_t accuma,accumb,accumc,accumd,accum; + float32x2_t accum2; + float32x4_t vec1; + float32x4_t coef0 = vdupq_n_f32(S->coef0); + + float32x4_t vec2,vec2a,vec2b,vec2c,vec2d; + + uint32_t blkCnt; + uint32_t vectorBlkCnt; + + const float32_t *pIn = in; + + const float32_t *pSupport = S->supportVectors; + + const float32_t *pSupporta = S->supportVectors; + const float32_t *pSupportb; + const float32_t *pSupportc; + const float32_t *pSupportd; + + pSupportb = pSupporta + S->vectorDimension; + pSupportc = pSupportb + S->vectorDimension; + pSupportd = pSupportc + S->vectorDimension; + + const float32_t *pDualCoefs = S->dualCoefficients; + + vectorBlkCnt = S->nbOfSupportVectors >> 2; + while (vectorBlkCnt > 0U) + { + accuma = vdupq_n_f32(0); + accumb = vdupq_n_f32(0); + accumc = vdupq_n_f32(0); + accumd = vdupq_n_f32(0); + + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2a = vld1q_f32(pSupporta); + vec2b = vld1q_f32(pSupportb); + vec2c = vld1q_f32(pSupportc); + vec2d = vld1q_f32(pSupportd); + + pIn += 4; + pSupporta += 4; + pSupportb += 4; + pSupportc += 4; + pSupportd += 4; + + accuma = vmlaq_f32(accuma, vec1,vec2a); + accumb = vmlaq_f32(accumb, vec1,vec2b); + accumc = vmlaq_f32(accumc, vec1,vec2c); + accumd = vmlaq_f32(accumd, vec1,vec2d); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accuma),vget_high_f32(accuma)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,0); + + accum2 = vpadd_f32(vget_low_f32(accumb),vget_high_f32(accumb)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,1); + + accum2 = vpadd_f32(vget_low_f32(accumc),vget_high_f32(accumc)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,2); + + accum2 = vpadd_f32(vget_low_f32(accumd),vget_high_f32(accumd)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,3); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,0) + *pIn * *pSupporta++, dotV,0); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,1) + *pIn * *pSupportb++, dotV,1); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,2) + *pIn * *pSupportc++, dotV,2); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,3) + *pIn * *pSupportd++, dotV,3); + + pIn++; + + blkCnt -- ; + } + + vec1 = vld1q_f32(pDualCoefs); + pDualCoefs += 4; + + // To vectorize later + dotV = vmulq_n_f32(dotV, S->gamma); + dotV = vaddq_f32(dotV, coef0); + + dotV = vtanhq_f32(dotV); + + accum = vmulq_f32(vec1,dotV); + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + sum += vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + pSupporta += 3*S->vectorDimension; + pSupportb += 3*S->vectorDimension; + pSupportc += 3*S->vectorDimension; + pSupportd += 3*S->vectorDimension; + + vectorBlkCnt -- ; + } + + pSupport = pSupporta; + vectorBlkCnt = S->nbOfSupportVectors & 3; + + while (vectorBlkCnt > 0U) + { + accum = vdupq_n_f32(0); + dot = 0.0f; + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2 = vld1q_f32(pSupport); + pIn += 4; + pSupport += 4; + + accum = vmlaq_f32(accum, vec1,vec2); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + dot = vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + dot = dot + *pIn++ * *pSupport++; + + blkCnt -- ; + } + + sum += *pDualCoefs++ * tanhf(S->gamma * dot + S->coef0); + vectorBlkCnt -- ; + } + + *pResult=S->classes[STEP(sum)]; +} +#else +void arm_svm_sigmoid_predict_f32( + const arm_svm_sigmoid_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum=S->intercept; + float32_t dot=0; + uint32_t i,j; + const float32_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + in[j]* *pSupport++; + } + sum += S->dualCoefficients[i] * tanhf(S->gamma * dot + S->coef0); + } + *pResult=S->classes[STEP(sum)]; +} + +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of sigmoidsvm group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/CMakeLists.txt new file mode 100644 index 00000000..48f039e8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/CMakeLists.txt @@ -0,0 +1,80 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPStatistics) + +include(configLib) +include(configDsp) + + + +add_library(CMSISDSPStatistics STATIC) + +target_sources(CMSISDSPStatistics PRIVATE arm_entropy_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_entropy_f64.c) +target_sources(CMSISDSPStatistics PRIVATE arm_kullback_leibler_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_kullback_leibler_f64.c) +target_sources(CMSISDSPStatistics PRIVATE arm_logsumexp_dot_prod_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_logsumexp_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_max_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_max_no_idx_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_max_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_max_q31.c) +target_sources(CMSISDSPStatistics PRIVATE arm_max_q7.c) +target_sources(CMSISDSPStatistics PRIVATE arm_mean_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_mean_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_mean_q31.c) +target_sources(CMSISDSPStatistics PRIVATE arm_mean_q7.c) +target_sources(CMSISDSPStatistics PRIVATE arm_min_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_min_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_min_q31.c) +target_sources(CMSISDSPStatistics PRIVATE arm_min_q7.c) +target_sources(CMSISDSPStatistics PRIVATE arm_power_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_power_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_power_q31.c) +target_sources(CMSISDSPStatistics PRIVATE arm_power_q7.c) +target_sources(CMSISDSPStatistics PRIVATE arm_rms_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_rms_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_rms_q31.c) +target_sources(CMSISDSPStatistics PRIVATE arm_std_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_std_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_std_q31.c) +target_sources(CMSISDSPStatistics PRIVATE arm_var_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_var_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_var_q31.c) + +target_sources(CMSISDSPStatistics PRIVATE arm_absmax_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmax_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmax_q31.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmax_q7.c) + +target_sources(CMSISDSPStatistics PRIVATE arm_absmin_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmin_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmin_q31.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmin_q7.c) + +configLib(CMSISDSPStatistics ${ROOT}) +configDsp(CMSISDSPStatistics ${ROOT}) + +### Includes +target_include_directories(CMSISDSPStatistics PUBLIC "${DSP}/Include") + + + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPStatistics PRIVATE arm_max_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_min_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_mean_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_power_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_rms_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_std_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_var_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_entropy_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_kullback_leibler_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_logsumexp_dot_prod_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_logsumexp_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_max_no_idx_f16.c) + +target_sources(CMSISDSPStatistics PRIVATE arm_absmax_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmin_f16.c) + +endif() \ No newline at end of file diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c new file mode 100644 index 00000000..74109ce0 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c @@ -0,0 +1,68 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: StatisticsFunctions.c + * Description: Combination of all statistics function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_entropy_f32.c" +#include "arm_entropy_f64.c" +#include "arm_kullback_leibler_f32.c" +#include "arm_kullback_leibler_f64.c" +#include "arm_logsumexp_dot_prod_f32.c" +#include "arm_logsumexp_f32.c" +#include "arm_max_f32.c" +#include "arm_max_q15.c" +#include "arm_max_q31.c" +#include "arm_max_q7.c" +#include "arm_max_no_idx_f32.c" +#include "arm_mean_f32.c" +#include "arm_mean_q15.c" +#include "arm_mean_q31.c" +#include "arm_mean_q7.c" +#include "arm_min_f32.c" +#include "arm_min_q15.c" +#include "arm_min_q31.c" +#include "arm_min_q7.c" +#include "arm_power_f32.c" +#include "arm_power_q15.c" +#include "arm_power_q31.c" +#include "arm_power_q7.c" +#include "arm_rms_f32.c" +#include "arm_rms_q15.c" +#include "arm_rms_q31.c" +#include "arm_std_f32.c" +#include "arm_std_q15.c" +#include "arm_std_q31.c" +#include "arm_var_f32.c" +#include "arm_var_q15.c" +#include "arm_var_q31.c" +#include "arm_absmax_f32.c" +#include "arm_absmax_q15.c" +#include "arm_absmax_q31.c" +#include "arm_absmax_q7.c" +#include "arm_absmin_f32.c" +#include "arm_absmin_q15.c" +#include "arm_absmin_q31.c" +#include "arm_absmin_q7.c" \ No newline at end of file diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctionsF16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctionsF16.c new file mode 100644 index 00000000..f5fab8d8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctionsF16.c @@ -0,0 +1,42 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: StatisticsFunctions.c + * Description: Combination of all statistics function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_max_f16.c" +#include "arm_min_f16.c" +#include "arm_mean_f16.c" +#include "arm_power_f16.c" +#include "arm_rms_f16.c" +#include "arm_std_f16.c" +#include "arm_var_f16.c" +#include "arm_entropy_f16.c" +#include "arm_kullback_leibler_f16.c" +#include "arm_logsumexp_dot_prod_f16.c" +#include "arm_logsumexp_f16.c" +#include "arm_max_no_idx_f16.c" +#include "arm_absmax_f16.c" +#include "arm_absmin_f16.c" \ No newline at end of file diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f16.c new file mode 100644 index 00000000..473397f8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f16.c @@ -0,0 +1,274 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_f16.c + * Description: Maximum value of a absolute values of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_absmax_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + uint16_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + float16_t const *pSrcVec; + f16x8_t curExtremValVec = vdupq_n_f16(F16_ABSMIN); + float16_t maxValue = F16_ABSMIN; + uint16_t idx = blockSize; + uint16x8_t indexVec; + uint16x8_t curExtremIdxVec; + mve_pred16_t p0; + + + indexVec = vidupq_u16((uint32_t)0, 1); + curExtremIdxVec = vdupq_n_u16(0); + + pSrcVec = (float16_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vldrhq_f16(pSrcVec); + pSrcVec += 8; + vecSrc = vabsq(vecSrc); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = indexVec + 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + vecSrc = vldrhq_f16(pSrcVec); + pSrcVec += 8; + vecSrc = vabsq(vecSrc); + + p0 = vctp16q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(vecSrc, curExtremValVec, p0); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxnmvq(maxValue, curExtremValVec); + /* + * set index for lower values to max possible index + */ + p0 = vcmpgeq(curExtremValVec, maxValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u16(blockSize), p0); + /* + * Get min index which is thus for a max value + */ + idx = vminvq(idx, indexVec); + /* + * Save result + */ + *pIndex = idx; + *pResult = maxValue; +} +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmax_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0.0f16) ? out : -out; \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f16) ? cur_absmax : -cur_absmax; \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f16) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f16) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f16) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f16) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmax_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = fabsf(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = fabsf(*pSrc++); + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f32.c new file mode 100644 index 00000000..a571ae0d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f32.c @@ -0,0 +1,260 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_f32.c + * Description: Maximum value of absolute values of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + +/** + @defgroup AbsMax Absolute Maximum + + Computes the maximum value of absolute values of an array of data. + The function returns both the maximum value and its position within the array. + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_absmax_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + int32_t blkSize = blockSize; + f32x4_t vecSrc; + f32x4_t curExtremValVec = vdupq_n_f32(F32_ABSMIN); + float32_t maxValue = F32_ABSMIN; + uint32_t idx = blockSize; + uint32x4_t indexVec; + uint32x4_t curExtremIdxVec; + uint32_t curIdx = 0; + mve_pred16_t p0; + + + indexVec = vidupq_wb_u32(&curIdx, 1); + curExtremIdxVec = vdupq_n_u32(0); + + do { + mve_pred16_t p = vctp32q(blkSize); + + vecSrc = vldrwq_z_f32((float32_t const *) pSrc, p); + vecSrc = vabsq_m(vuninitializedq_f32(), vecSrc, p); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(vecSrc, curExtremValVec, p); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + /* Does TP detection works here ?? */ + indexVec = vidupq_wb_u32(&curIdx, 1); + + blkSize -= 4; + pSrc += 4; + } + while (blkSize > 0); + + /* + * Get max value across the vector + */ + maxValue = vmaxnmvq(maxValue, curExtremValVec); + /* + * set index for lower values to max possible index + */ + p0 = vcmpgeq(curExtremValVec, maxValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u32(blockSize), p0); + /* + * Get min index which is thus for a max value + */ + idx = vminvq(idx, indexVec); + /* + * Save result + */ + *pIndex = idx; + *pResult = maxValue; +} + + +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmax_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0.0f) ? out : -out; \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmax_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = fabsf(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = fabsf(*pSrc++); + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f64.c new file mode 100644 index 00000000..987c32ca --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f64.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_f64.c + * Description: Maximum value of absolute values of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +void arm_absmax_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex) +{ + float64_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = fabs(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = fabs(*pSrc++); + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +/** + @} end of AbsMax group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f16.c new file mode 100644 index 00000000..82820c62 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f16.c @@ -0,0 +1,228 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_no_idx_f16.c + * Description: Maximum value of a absolute values of a floating-point vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_absmax_no_idx_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + uint16_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + float16_t const *pSrcVec; + f16x8_t curExtremValVec = vdupq_n_f16(F16_ABSMIN); + float16_t maxValue = F16_ABSMIN; + mve_pred16_t p0; + + + pSrcVec = (float16_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecSrc = vldrhq_f16(pSrcVec); + pSrcVec += 8; + /* + * update per-lane max. + */ + curExtremValVec = vmaxnmaq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + vecSrc = vldrhq_f16(pSrcVec); + pSrcVec += 8; + p0 = vctp16q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxnmaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxnmavq(maxValue, curExtremValVec); + *pResult = maxValue; +} +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmax_no_idx_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + float16_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = ((_Float16)out > 0.0f16) ? out : -(_Float16)out; \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + /* compare for the extrema value */ \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + out = cur_absmax; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + out = cur_absmax; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmax_no_idx_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + float16_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + /* Load first input value that act as reference value for comparision */ + out = (_Float16)fabsf((float32_t)*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (_Float16)fabsf((float32_t)*pSrc++); + + /* compare for the maximum value */ + if ((_Float16)out < (_Float16)maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f32.c new file mode 100644 index 00000000..13d99bab --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f32.c @@ -0,0 +1,225 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_no_idx_f32.c + * Description: Maximum value of absolute values of a floating-point vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_absmax_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + f32x4_t vecSrc; + float32_t const *pSrcVec; + f32x4_t curExtremValVec = vdupq_n_f32(F32_ABSMIN); + float32_t maxValue = F32_ABSMIN; + mve_pred16_t p0; + + + pSrcVec = (float32_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + vecSrc = vldrwq_f32(pSrcVec); + pSrcVec += 4; + /* + * update per-lane max. + */ + curExtremValVec = vmaxnmaq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0) + { + vecSrc = vldrwq_f32(pSrcVec); + pSrcVec += 4; + p0 = vctp32q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxnmaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxnmavq(maxValue, curExtremValVec); + *pResult = maxValue; +} + + +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmax_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0.0f) ? out : -out; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmax_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + + + /* Load first input value that act as reference value for comparision */ + out = fabsf(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = fabsf(*pSrc++); + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f64.c new file mode 100644 index 00000000..23e34005 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f64.c @@ -0,0 +1,87 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_no_idx_f64.c + * Description: Maximum value of absolute values of a floating-point vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ +void arm_absmax_no_idx_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult) +{ + float64_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + + + /* Load first input value that act as reference value for comparision */ + out = fabs(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = fabs(*pSrc++); + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; +} + +/** + @} end of AbsMax group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q15.c new file mode 100644 index 00000000..941f2ddc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q15.c @@ -0,0 +1,220 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_no_idx_q15.c + * Description: Maximum value of absolute values of a Q15 vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_absmax_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint16_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q15_t const *pSrcVec; + uint16x8_t curExtremValVec = vdupq_n_s16(Q15_ABSMIN); + q15_t maxValue = Q15_ABSMIN; + mve_pred16_t p0; + + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + /* + * update per-lane max. + */ + curExtremValVec = vmaxaq(curExtremValVec, vecSrc); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + p0 = vctp16q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxavq(maxValue, (q15x8_t)curExtremValVec); + *pResult = maxValue; +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmax_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q15_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q15_t)__QSUB16(0, out); \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmax_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q15_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q31.c new file mode 100644 index 00000000..8275a535 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q31.c @@ -0,0 +1,220 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_no_idx_q31.c + * Description: Maximum value of absolute values of a Q31 vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_absmax_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q31_t const *pSrcVec; + uint32x4_t curExtremValVec = vdupq_n_s32(Q31_ABSMIN); + q31_t maxValue = Q31_ABSMIN; + mve_pred16_t p0; + + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + /* + * update per-lane max. + */ + curExtremValVec = vmaxaq(curExtremValVec, vecSrc); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + p0 = vctp32q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxavq(maxValue, (q31x4_t)curExtremValVec); + *pResult = maxValue; +} +#else +#if defined(ARM_MATH_DSP) +void arm_absmax_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q31_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q31_t)__QSUB(0, out); \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmax_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q31_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q7.c new file mode 100644 index 00000000..8eaca9b7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q7.c @@ -0,0 +1,224 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_no_idx_q7.c + * Description: Maximum value of absolute values of a Q7 vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include +#include "arm_helium_utils.h" + + + +void arm_absmax_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7_t const *pSrcVec; + uint8x16_t curExtremValVec = vdupq_n_s8(Q7_ABSMIN); + q7_t maxValue = Q7_ABSMIN; + mve_pred16_t p0; + + + pSrcVec = (q7_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + /* + * update per-lane max. + */ + curExtremValVec = vmaxaq(curExtremValVec, vecSrc); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + p0 = vctp8q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxavq(maxValue, (q7x16_t)curExtremValVec); + *pResult = maxValue; +} +#else +#if defined(ARM_MATH_DSP) +void arm_absmax_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + q7_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q7_t)__QSUB8(0, out); \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmax_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + q7_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q15.c new file mode 100644 index 00000000..a898d1f3 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q15.c @@ -0,0 +1,236 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_q15.c + * Description: Maximum value of absolute values of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_absmax_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + q15x8_t extremValVec = vdupq_n_s16(Q15_ABSMIN); + q15_t maxValue = Q15_ABSMIN; + uint16x8_t indexVec; + uint16x8_t extremIdxVec; + mve_pred16_t p0; + uint16_t extremIdxArr[8]; + + indexVec = vidupq_u16(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp16q(blkCnt); + q15x8_t extremIdxVal = vld1q_z_s16(pSrc, p); + + extremIdxVal = vabsq(extremIdxVal); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u16(extremIdxArr, indexVec, p0); + + indexVec += 8; + pSrc += 8; + blkCnt -= 8; + } + while (blkCnt > 0); + + + /* Get max value across the vector */ + maxValue = vmaxvq(maxValue, extremValVec); + + /* set index for lower values to max possible index */ + p0 = vcmpgeq(extremValVec, maxValue); + extremIdxVec = vld1q_u16(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u16(blockSize - 1), p0); + *pIndex = vminvq(blockSize - 1, indexVec); + *pResult = maxValue; +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmax_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q15_t)__QSUB16(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmax_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q31.c new file mode 100644 index 00000000..a4e1e83d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q31.c @@ -0,0 +1,236 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_q31.c + * Description: Maximum value of absolute values of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_absmax_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + q31x4_t extremValVec = vdupq_n_s32(Q31_ABSMIN); + q31_t maxValue = Q31_ABSMIN; + uint32x4_t indexVec; + uint32x4_t extremIdxVec; + mve_pred16_t p0; + uint32_t extremIdxArr[4]; + + indexVec = vidupq_u32(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp32q(blkCnt); + q31x4_t extremIdxVal = vld1q_z_s32(pSrc, p); + + extremIdxVal = vabsq(extremIdxVal); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u32(extremIdxArr, indexVec, p0); + + indexVec += 4; + pSrc += 4; + blkCnt -= 4; + } + while (blkCnt > 0); + + + /* Get max value across the vector */ + maxValue = vmaxvq(maxValue, extremValVec); + + /* set index for lower values to max possible index */ + p0 = vcmpgeq(extremValVec, maxValue); + extremIdxVec = vld1q_u32(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u32(blockSize - 1), p0); + *pIndex = vminvq(blockSize - 1, indexVec); + *pResult = maxValue; +} +#else +#if defined(ARM_MATH_DSP) +void arm_absmax_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q31_t)__QSUB(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmax_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q7.c new file mode 100644 index 00000000..f21b57a4 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q7.c @@ -0,0 +1,294 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_q7.c + * Description: Maximum value of absolute values of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include +#include "arm_helium_utils.h" + +#define MAX_BLKSZ_S8 (UINT8_MAX+1) + +static void arm_small_blk_absmax_q7( + const q7_t * pSrc, + uint16_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + q7x16_t extremValVec = vdupq_n_s8(Q7_ABSMIN); + q7_t maxValue = Q7_ABSMIN; + uint8x16_t indexVec; + uint8x16_t extremIdxVec; + mve_pred16_t p0; + uint8_t extremIdxArr[16]; + + indexVec = vidupq_u8(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp8q(blkCnt); + q7x16_t extremIdxVal = vld1q_z_s8(pSrc, p); + + extremIdxVal = vabsq(extremIdxVal); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u8(extremIdxArr, indexVec, p0); + + indexVec += 16; + pSrc += 16; + blkCnt -= 16; + } + while (blkCnt > 0); + + + /* Get max value across the vector */ + maxValue = vmaxvq(maxValue, extremValVec); + + /* set index for lower values to max possible index */ + p0 = vcmpgeq(extremValVec, maxValue); + extremIdxVec = vld1q_u8(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u8(blockSize - 1), p0); + *pIndex = vminvq_u8(blockSize - 1, indexVec); + *pResult = maxValue; +} + +void arm_absmax_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + int32_t totalSize = blockSize; + + if (totalSize <= MAX_BLKSZ_S8) + { + arm_small_blk_absmax_q7(pSrc, blockSize, pResult, pIndex); + } + else + { + uint32_t curIdx = 0; + q7_t curBlkExtr = Q7_MIN; + uint32_t curBlkPos = 0; + uint32_t curBlkIdx = 0; + /* + * process blocks of 255 elts + */ + while (totalSize >= MAX_BLKSZ_S8) + { + const q7_t *curSrc = pSrc; + + arm_small_blk_absmax_q7(curSrc, MAX_BLKSZ_S8, pResult, pIndex); + if (*pResult > curBlkExtr) + { + /* + * update partial extrema + */ + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + curIdx++; + pSrc += MAX_BLKSZ_S8; + totalSize -= MAX_BLKSZ_S8; + } + /* + * remainder + */ + arm_small_blk_absmax_q7(pSrc, totalSize, pResult, pIndex); + if (*pResult > curBlkExtr) + { + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + *pIndex = curBlkIdx * MAX_BLKSZ_S8 + curBlkPos; + *pResult = curBlkExtr; + } +} +#else +#if defined(ARM_MATH_DSP) +void arm_absmax_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q7_t)__QSUB8(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmax_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f16.c new file mode 100644 index 00000000..45aec490 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f16.c @@ -0,0 +1,276 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_f16.c + * Description: Minimum value of absolute values of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_absmin_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + uint16_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + float16_t const *pSrcVec; + f16x8_t curExtremValVec = vdupq_n_f16(F16_ABSMAX); + float16_t minValue = F16_ABSMAX; + uint16_t idx = blockSize; + uint16x8_t indexVec; + uint16x8_t curExtremIdxVec; + mve_pred16_t p0; + + + indexVec = vidupq_u16((uint32_t)0, 1); + curExtremIdxVec = vdupq_n_u16(0); + + pSrcVec = (float16_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vldrhq_f16(pSrcVec); + pSrcVec += 8; + vecSrc = vabsq(vecSrc); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = indexVec + 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + p0 = vctp16q(blkCnt); + + vecSrc = vldrhq_f16(pSrcVec); + pSrcVec += 8; + vecSrc = vabsq(vecSrc); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpleq_m(vecSrc, curExtremValVec, p0); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminnmvq(minValue, curExtremValVec); + /* + * set index for lower values to max possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u16(blockSize), p0); + /* + * Get min index which is thus for a max value + */ + idx = vminvq(idx, indexVec); + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmin_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0.0f16) ? out : -out; \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f16) ? cur_absmin : -cur_absmin; \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f16) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f16) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f16) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f16) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmin_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = fabsf(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = fabsf(*pSrc++); + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f32.c new file mode 100644 index 00000000..3a963227 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f32.c @@ -0,0 +1,279 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_f32.c + * Description: Minimum value of absolute values of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + + +/** + @ingroup groupStats + */ + +/** + @defgroup AbsMin Absolute Minimum + + Computes the minimum value of absolute values of an array of data. + The function returns both the minimum value and its position within the array. + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_absmin_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + f32x4_t vecSrc; + float32_t const *pSrcVec; + f32x4_t curExtremValVec = vdupq_n_f32(F32_ABSMAX); + float32_t minValue = F32_ABSMAX; + uint32_t idx = blockSize; + uint32x4_t indexVec; + uint32x4_t curExtremIdxVec; + mve_pred16_t p0; + + + indexVec = vidupq_u32((uint32_t)0, 1); + curExtremIdxVec = vdupq_n_u32(0); + + pSrcVec = (float32_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + vecSrc = vldrwq_f32(pSrcVec); + pSrcVec += 4; + vecSrc = vabsq(vecSrc); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = indexVec + 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0) + { + p0 = vctp32q(blkCnt); + + vecSrc = vldrwq_f32(pSrcVec); + pSrcVec += 4; + vecSrc = vabsq(vecSrc); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpleq_m(vecSrc, curExtremValVec, p0); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminnmvq(minValue, curExtremValVec); + /* + * set index for lower values to max possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u32(blockSize), p0); + /* + * Get min index which is thus for a max value + */ + idx = vminvq(idx, indexVec); + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmin_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0.0f) ? out : -out; \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmin_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = fabsf(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = fabsf(*pSrc++); + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f64.c new file mode 100644 index 00000000..7aac9700 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f64.c @@ -0,0 +1,90 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_f64.c + * Description: Minimum value of absolute values of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +void arm_absmin_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex) +{ + float64_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = fabs(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = fabs(*pSrc++); + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +/** + @} end of AbsMin group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f16.c new file mode 100644 index 00000000..62e10543 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f16.c @@ -0,0 +1,230 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_no_idx_f16.c + * Description: Minimum value of absolute values of a floating-point vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_absmin_no_idx_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + float16_t const *pSrcVec; + f16x8_t curExtremValVec = vdupq_n_f16(F16_ABSMAX); + float16_t minValue = F16_ABSMAX; + mve_pred16_t p0; + + + pSrcVec = (float16_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + /* + * update per-lane min. + */ + curExtremValVec = vminnmaq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + p0 = vctp16q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminnmaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get min value across the vector + */ + minValue = vminnmavq(minValue, curExtremValVec); + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmin_no_idx_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + float16_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = ((_Float16)out > 0.0f16) ? out : -(_Float16)out; \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + /* compare for the extrema value */ \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + out = cur_absmin; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + out = cur_absmin; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmin_no_idx_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + float16_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + /* Load first input value that act as reference value for comparision */ + out = (_Float16)fabsf((float32_t)*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (_Float16)fabsf((float32_t)*pSrc++); + + /* compare for the minimum value */ + if ((_Float16)out > (_Float16)minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f32.c new file mode 100644 index 00000000..c7108daa --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f32.c @@ -0,0 +1,226 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_no_idx_f32.c + * Description: Minimum value of absolute values of a floating-point vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_absmin_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + f32x4_t vecSrc; + float32_t const *pSrcVec; + f32x4_t curExtremValVec = vdupq_n_f32(F32_ABSMAX); + float32_t minValue = F32_ABSMAX; + mve_pred16_t p0; + + + pSrcVec = (float32_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + vecSrc = vldrwq_f32(pSrcVec); + pSrcVec += 4; + /* + * update per-lane min. + */ + curExtremValVec = vminnmaq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0) + { + vecSrc = vldrwq_f32(pSrcVec); + pSrcVec += 4; + p0 = vctp32q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminnmaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get min value across the vector + */ + minValue = vminnmavq(minValue, curExtremValVec); + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmin_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0.0f) ? out : -out; \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmin_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + /* Load first input value that act as reference value for comparision */ + out = fabsf(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = fabsf(*pSrc++); + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; +} + +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f64.c new file mode 100644 index 00000000..ac1e9263 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f64.c @@ -0,0 +1,84 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_no_idx_f64.c + * Description: Minimum value of absolute values of a floating-point vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ +void arm_absmin_no_idx_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult) +{ + float64_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + /* Load first input value that act as reference value for comparision */ + out = fabs(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = fabs(*pSrc++); + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; +} + +/** + @} end of AbsMin group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q15.c new file mode 100644 index 00000000..76a17886 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q15.c @@ -0,0 +1,222 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_no_idx_q15.c + * Description: Minimum value of absolute values of a Q15 vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_absmin_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint16_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q15_t const *pSrcVec; + uint16x8_t curExtremValVec = vdupq_n_s16(Q15_ABSMAX); + q15_t minValue = Q15_ABSMAX; + mve_pred16_t p0; + + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + /* + * update per-lane min. + */ + curExtremValVec = vminaq(curExtremValVec, vecSrc); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + p0 = vctp16q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get min value across the vector + */ + minValue = vminavq(minValue, (q15x8_t)curExtremValVec); + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmin_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q15_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q15_t)__QSUB16(0, out); \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmin_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q15_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q31.c new file mode 100644 index 00000000..b52db172 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q31.c @@ -0,0 +1,221 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_no_idx_q31.c + * Description: Minimum value of absolute values of a Q31 vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_absmin_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q31_t const *pSrcVec; + uint32x4_t curExtremValVec = vdupq_n_s32(Q31_ABSMAX); + q31_t minValue = Q31_ABSMAX; + mve_pred16_t p0; + + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + /* + * update per-lane min. + */ + curExtremValVec = vminaq(curExtremValVec, vecSrc); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + p0 = vctp32q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get min value across the vector + */ + minValue = vminavq(minValue, (q31x4_t)curExtremValVec); + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmin_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q31_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q31_t)__QSUB(0, out); \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmin_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q31_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q7.c new file mode 100644 index 00000000..f60f113d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q7.c @@ -0,0 +1,223 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_no_idx_q7.c + * Description: Minimum value of absolute values of a Q7 vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include +#include "arm_helium_utils.h" + + + +void arm_absmin_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7_t const *pSrcVec; + uint8x16_t curExtremValVec = vdupq_n_s8(Q7_ABSMAX); + q7_t minValue = Q7_ABSMAX; + mve_pred16_t p0; + + + pSrcVec = (q7_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + /* + * update per-lane min. + */ + curExtremValVec = vminaq(curExtremValVec, vecSrc); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + p0 = vctp8q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get min value across the vector + */ + minValue = vminavq(minValue, (q7x16_t)curExtremValVec); + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmin_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + q7_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q7_t)__QSUB8(0, out); \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmin_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + q7_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q15.c new file mode 100644 index 00000000..e4d0704a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q15.c @@ -0,0 +1,269 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_q15.c + * Description: Minimum value of absolute values of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_absmin_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + uint16_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q15_t const *pSrcVec; + q15x8_t curExtremValVec = vdupq_n_s16(Q15_ABSMAX); + q15_t minValue = Q15_ABSMAX; + uint16_t idx = blockSize; + uint16x8_t indexVec; + uint16x8_t curExtremIdxVec; + uint32_t startIdx = 0; + mve_pred16_t p0; + + + indexVec = vidupq_wb_u16(&startIdx, 1); + curExtremIdxVec = vdupq_n_u16(0); + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + vecSrc = vabsq(vecSrc); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = vidupq_wb_u16(&startIdx, 1); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + vecSrc = vabsq(vecSrc); + + p0 = vctp16q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq_m(vecSrc, curExtremValVec, p0); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminvq(minValue, curExtremValVec); + /* + * set index for lower values to min possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u16(blockSize), p0); + /* + * Get min index which is thus for a min value + */ + idx = vminvq(idx, indexVec); + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmin_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q15_t)__QSUB16(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmin_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q31.c new file mode 100644 index 00000000..21c769b8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q31.c @@ -0,0 +1,269 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_q31.c + * Description: Minimum value of absolute values of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_absmin_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + uint16_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q31_t const *pSrcVec; + q31x4_t curExtremValVec = vdupq_n_s32(Q31_ABSMAX); + q31_t minValue = Q31_ABSMAX; + uint16_t idx = blockSize; + uint32x4_t indexVec; + uint32x4_t curExtremIdxVec; + uint32_t startIdx = 0; + mve_pred16_t p0; + + + indexVec = vidupq_wb_u32(&startIdx, 1); + curExtremIdxVec = vdupq_n_u32(0); + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + vecSrc = vabsq(vecSrc); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = vidupq_wb_u32(&startIdx, 1); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + vecSrc = vabsq(vecSrc); + + p0 = vctp32q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq_m(vecSrc, curExtremValVec, p0); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminvq(minValue, curExtremValVec); + /* + * set index for lower values to min possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u32(blockSize), p0); + /* + * Get min index which is thus for a min value + */ + idx = vminvq(idx, indexVec); + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmin_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q31_t)__QSUB(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmin_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q7.c new file mode 100644 index 00000000..2889891e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q7.c @@ -0,0 +1,322 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_q7.c + * Description: Minimum value of absolute values of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include +#include "arm_helium_utils.h" + +#define MAX_BLKSZ_S8 (UINT8_MAX+1) + +static void arm_small_blk_absmin_q7( + const q7_t *pSrc, + uint32_t blockSize, + q7_t *pResult, + uint32_t *pIndex) +{ + uint16_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7_t const *pSrcVec; + q7x16_t curExtremValVec = vdupq_n_s8(Q7_ABSMAX); + q7_t minValue = Q7_ABSMAX; + uint16_t idx = blockSize - 1; + uint8x16_t indexVec; + uint8x16_t curExtremIdxVec; + uint32_t startIdx = 0; + mve_pred16_t p0; + + + indexVec = vidupq_wb_u8(&startIdx, 1); + curExtremIdxVec = vdupq_n_u8(0); + + pSrcVec = (q7_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + vecSrc = vabsq(vecSrc); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = vidupq_wb_u8(&startIdx, 1); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + vecSrc = vabsq(vecSrc); + + p0 = vctp8q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq_m(vecSrc, curExtremValVec, p0); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminvq(minValue, curExtremValVec); + /* + * set index for lower values to min possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + idx = vminvq_p_u8(idx, curExtremIdxVec, p0); + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + + +void arm_absmin_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + int32_t totalSize = blockSize; + + if (totalSize <= MAX_BLKSZ_S8) + { + arm_small_blk_absmin_q7(pSrc, blockSize, pResult, pIndex); + } + else + { + uint32_t curIdx = 0; + q7_t curBlkExtr = Q7_MAX; + uint32_t curBlkPos = 0; + uint32_t curBlkIdx = 0; + /* + * process blocks of 255 elts + */ + while (totalSize >= MAX_BLKSZ_S8) + { + const q7_t *curSrc = pSrc; + + arm_small_blk_absmin_q7(curSrc, MAX_BLKSZ_S8, pResult, pIndex); + if (*pResult < curBlkExtr) + { + /* + * update partial extrema + */ + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + curIdx++; + pSrc += MAX_BLKSZ_S8; + totalSize -= MAX_BLKSZ_S8; + } + /* + * remainder + */ + arm_small_blk_absmin_q7(pSrc, totalSize, pResult, pIndex); + if (*pResult < curBlkExtr) + { + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + *pIndex = curBlkIdx * MAX_BLKSZ_S8 + curBlkPos; + *pResult = curBlkExtr; + } +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmin_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q7_t)__QSUB8(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmin_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f16.c new file mode 100644 index 00000000..ffe08f42 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f16.c @@ -0,0 +1,140 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f16.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupStats + */ + +/** + @defgroup Entropy Entropy + + Computes the entropy of a distribution + + */ + +/** + * @addtogroup Entropy + * @{ + */ + + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math_f16.h" + +float16_t arm_entropy_f16(const float16_t * pSrcA,uint32_t blockSize) +{ + uint32_t blkCnt; + _Float16 accum=0.0f16,p; + + + blkCnt = blockSize; + + f16x8_t vSum = vdupq_n_f16(0.0f); + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + f16x8_t vecIn = vld1q(pSrcA); + + vSum = vaddq_f16(vSum, vmulq(vecIn, vlogq_f16(vecIn))); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrcA += 8; + blkCnt --; + } + + accum = vecAddAcrossF16Mve(vSum); + + /* Tail */ + blkCnt = blockSize & 0x7; + while(blkCnt > 0) + { + p = *pSrcA++; + accum += p * logf(p); + + blkCnt--; + + } + + return (-accum); +} + +#else + +float16_t arm_entropy_f16(const float16_t * pSrcA,uint32_t blockSize) +{ + const float16_t *pIn; + uint32_t blkCnt; + _Float16 accum, p; + + pIn = pSrcA; + blkCnt = blockSize; + + accum = 0.0f; + + while(blkCnt > 0) + { + p = *pIn++; + accum += p * logf(p); + + blkCnt--; + + } + + return(-accum); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of Entropy group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f32.c new file mode 100644 index 00000000..a2160c16 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f32.c @@ -0,0 +1,174 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f32.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#include +#include + + +/** + * @addtogroup Entropy + * @{ + */ + + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize) +{ + uint32_t blkCnt; + float32_t accum=0.0f,p; + + + blkCnt = blockSize; + + f32x4_t vSum = vdupq_n_f32(0.0f); + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + f32x4_t vecIn = vld1q(pSrcA); + + vSum = vaddq_f32(vSum, vmulq(vecIn, vlogq_f32(vecIn))); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrcA += 4; + blkCnt --; + } + + accum = vecAddAcrossF32Mve(vSum); + + /* Tail */ + blkCnt = blockSize & 0x3; + while(blkCnt > 0) + { + p = *pSrcA++; + accum += p * logf(p); + + blkCnt--; + + } + + return (-accum); +} + +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "NEMath.h" + +float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize) +{ + const float32_t *pIn; + uint32_t blkCnt; + float32_t accum, p; + + float32x4_t accumV; + float32x2_t accumV2; + float32x4_t tmpV, tmpV2; + + pIn = pSrcA; + + accum = 0.0f; + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + tmpV = vld1q_f32(pIn); + pIn += 4; + + tmpV2 = vlogq_f32(tmpV); + accumV = vmlaq_f32(accumV, tmpV, tmpV2); + + blkCnt--; + + } + + accumV2 = vpadd_f32(vget_low_f32(accumV),vget_high_f32(accumV)); + accum = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + p = *pIn++; + accum += p * logf(p); + + blkCnt--; + + } + + return(-accum); +} + +#else +float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize) +{ + const float32_t *pIn; + uint32_t blkCnt; + float32_t accum, p; + + pIn = pSrcA; + blkCnt = blockSize; + + accum = 0.0f; + + while(blkCnt > 0) + { + p = *pIn++; + accum += p * logf(p); + + blkCnt--; + + } + + return(-accum); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of Entropy group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f64.c new file mode 100644 index 00000000..c208ff48 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f64.c @@ -0,0 +1,73 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f64.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#include +#include + +/** + * @addtogroup Entropy + * @{ + */ + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + +float64_t arm_entropy_f64(const float64_t * pSrcA, uint32_t blockSize) +{ + const float64_t *pIn; + uint32_t blkCnt; + float64_t accum, p; + + pIn = pSrcA; + blkCnt = blockSize; + + accum = 0.0f; + + while(blkCnt > 0) + { + p = *pIn++; + + accum += p * log(p); + + blkCnt--; + + } + + return(-accum); +} + +/** + * @} end of Entropy group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f16.c new file mode 100644 index 00000000..a7da2494 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f16.c @@ -0,0 +1,152 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f16.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupStats + */ + +/** + @defgroup Kullback-Leibler Kullback-Leibler divergence + + Computes the Kullback-Leibler divergence between two distributions + + */ + + +/** + * @addtogroup Kullback-Leibler + * @{ + */ + + +/** + * @brief Kullback-Leibler + * + * Distribution A may contain 0 with Neon version. + * Result will be right but some exception flags will be set. + * + * Distribution B must not contain 0 probability. + * + * @param[in] *pSrcA points to an array of input values for probaility distribution A. + * @param[in] *pSrcB points to an array of input values for probaility distribution B. + * @param[in] blockSize number of samples in the input array. + * @return Kullback-Leibler divergence D(A || B) + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math_f16.h" + +float16_t arm_kullback_leibler_f16(const float16_t * pSrcA,const float16_t * pSrcB,uint32_t blockSize) +{ + uint32_t blkCnt; + _Float16 accum, pA,pB; + + + blkCnt = blockSize; + + accum = 0.0f16; + + f16x8_t vSum = vdupq_n_f16(0.0f); + blkCnt = blockSize >> 3; + while(blkCnt > 0) + { + f16x8_t vecA = vld1q(pSrcA); + f16x8_t vecB = vld1q(pSrcB); + f16x8_t vRatio; + + vRatio = vdiv_f16(vecB, vecA); + vSum = vaddq_f16(vSum, vmulq(vecA, vlogq_f16(vRatio))); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + blkCnt --; + } + + accum = vecAddAcrossF16Mve(vSum); + + blkCnt = blockSize & 7; + while(blkCnt > 0) + { + pA = *pSrcA++; + pB = *pSrcB++; + accum += pA * logf(pB / pA); + + blkCnt--; + + } + + return(-accum); +} + +#else +float16_t arm_kullback_leibler_f16(const float16_t * pSrcA,const float16_t * pSrcB,uint32_t blockSize) +{ + const float16_t *pInA, *pInB; + uint32_t blkCnt; + _Float16 accum, pA,pB; + + pInA = pSrcA; + pInB = pSrcB; + blkCnt = blockSize; + + accum = 0.0f; + + while(blkCnt > 0) + { + pA = *pInA++; + pB = *pInB++; + accum += pA * logf(pB / pA); + + blkCnt--; + + } + + return(-accum); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of Kullback-Leibler group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f32.c new file mode 100644 index 00000000..45a9624c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f32.c @@ -0,0 +1,193 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f32.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#include +#include + + +/** + * @addtogroup Kullback-Leibler + * @{ + */ + + +/** + * @brief Kullback-Leibler + * + * Distribution A may contain 0 with Neon version. + * Result will be right but some exception flags will be set. + * + * Distribution B must not contain 0 probability. + * + * @param[in] *pSrcA points to an array of input values for probaility distribution A. + * @param[in] *pSrcB points to an array of input values for probaility distribution B. + * @param[in] blockSize number of samples in the input array. + * @return Kullback-Leibler divergence D(A || B) + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +float32_t arm_kullback_leibler_f32(const float32_t * pSrcA,const float32_t * pSrcB,uint32_t blockSize) +{ + uint32_t blkCnt; + float32_t accum, pA,pB; + + + blkCnt = blockSize; + + accum = 0.0f; + + f32x4_t vSum = vdupq_n_f32(0.0f); + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + f32x4_t vecA = vld1q(pSrcA); + f32x4_t vecB = vld1q(pSrcB); + f32x4_t vRatio; + + vRatio = vdiv_f32(vecB, vecA); + vSum = vaddq_f32(vSum, vmulq(vecA, vlogq_f32(vRatio))); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + blkCnt --; + } + + accum = vecAddAcrossF32Mve(vSum); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + pA = *pSrcA++; + pB = *pSrcB++; + accum += pA * logf(pB / pA); + + blkCnt--; + + } + + return(-accum); +} + +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "NEMath.h" + +float32_t arm_kullback_leibler_f32(const float32_t * pSrcA,const float32_t * pSrcB,uint32_t blockSize) +{ + const float32_t *pInA, *pInB; + uint32_t blkCnt; + float32_t accum, pA,pB; + + float32x4_t accumV; + float32x2_t accumV2; + float32x4_t tmpVA, tmpVB,tmpV; + + pInA = pSrcA; + pInB = pSrcB; + + accum = 0.0f; + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + tmpVA = vld1q_f32(pInA); + pInA += 4; + + tmpVB = vld1q_f32(pInB); + pInB += 4; + + tmpV = vinvq_f32(tmpVA); + tmpVB = vmulq_f32(tmpVB, tmpV); + tmpVB = vlogq_f32(tmpVB); + + accumV = vmlaq_f32(accumV, tmpVA, tmpVB); + + blkCnt--; + + } + + accumV2 = vpadd_f32(vget_low_f32(accumV),vget_high_f32(accumV)); + accum = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + pA = *pInA++; + pB = *pInB++; + accum += pA * logf(pB/pA); + + blkCnt--; + + } + + return(-accum); +} + +#else +float32_t arm_kullback_leibler_f32(const float32_t * pSrcA,const float32_t * pSrcB,uint32_t blockSize) +{ + const float32_t *pInA, *pInB; + uint32_t blkCnt; + float32_t accum, pA,pB; + + pInA = pSrcA; + pInB = pSrcB; + blkCnt = blockSize; + + accum = 0.0f; + + while(blkCnt > 0) + { + pA = *pInA++; + pB = *pInB++; + accum += pA * logf(pB / pA); + + blkCnt--; + + } + + return(-accum); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of Kullback-Leibler group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f64.c new file mode 100644 index 00000000..b22d0473 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f64.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f64.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#include +#include + +/** + * @addtogroup Kullback-Leibler + * @{ + */ + +/** + * @brief Kullback-Leibler + * + * @param[in] *pSrcA points to an array of input values for probaility distribution A. + * @param[in] *pSrcB points to an array of input values for probaility distribution B. + * @param[in] blockSize number of samples in the input array. + * @return Kullback-Leibler divergence D(A || B) + * + */ + +float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, const float64_t * pSrcB, uint32_t blockSize) +{ + const float64_t *pInA, *pInB; + uint32_t blkCnt; + float64_t accum, pA,pB; + + pInA = pSrcA; + pInB = pSrcB; + blkCnt = blockSize; + + accum = 0.0f; + + while(blkCnt > 0) + { + pA = *pInA++; + pB = *pInB++; + + accum += pA * log(pB / pA); + + blkCnt--; + } + + return(-accum); +} + +/** + * @} end of Kullback-Leibler group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_dot_prod_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_dot_prod_f16.c new file mode 100644 index 00000000..a35ac0e8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_dot_prod_f16.c @@ -0,0 +1,84 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f16.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupStats + */ + +/** + @defgroup LogSumExp LogSumExp + + LogSumExp optimizations to compute sum of probabilities with Gaussian distributions + + */ + +/** + * @addtogroup LogSumExp + * @{ + */ + + +/** + * @brief Dot product with log arithmetic + * + * Vectors are containing the log of the samples + * + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[in] *pTmpBuffer temporary buffer of length blockSize + * @return The log of the dot product. + * + */ + + +float16_t arm_logsumexp_dot_prod_f16(const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t *pTmpBuffer) +{ + float16_t result; + arm_add_f16((float16_t*)pSrcA, (float16_t*)pSrcB, pTmpBuffer, blockSize); + + result = arm_logsumexp_f16(pTmpBuffer, blockSize); + return(result); +} + +/** + * @} end of LogSumExp group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_dot_prod_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_dot_prod_f32.c new file mode 100644 index 00000000..d2a94dac --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_dot_prod_f32.c @@ -0,0 +1,68 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f32.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#include +#include + + +/** + * @addtogroup LogSumExp + * @{ + */ + + +/** + * @brief Dot product with log arithmetic + * + * Vectors are containing the log of the samples + * + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[in] *pTmpBuffer temporary buffer of length blockSize + * @return The log of the dot product. + * + */ + + +float32_t arm_logsumexp_dot_prod_f32(const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t *pTmpBuffer) +{ + float32_t result; + arm_add_f32((float32_t*)pSrcA, (float32_t*)pSrcB, pTmpBuffer, blockSize); + + result = arm_logsumexp_f32(pTmpBuffer, blockSize); + return(result); +} + +/** + * @} end of LogSumExp group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_f16.c new file mode 100644 index 00000000..81272d56 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_f16.c @@ -0,0 +1,172 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f16.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + + +/** + * @addtogroup LogSumExp + * @{ + */ + + +/** + * @brief Computation of the LogSumExp + * + * In probabilistic computations, the dynamic of the probability values can be very + * wide because they come from gaussian functions. + * To avoid underflow and overflow issues, the values are represented by their log. + * In this representation, multiplying the original exp values is easy : their logs are added. + * But adding the original exp values is requiring some special handling and it is the + * goal of the LogSumExp function. + * + * If the values are x1...xn, the function is computing: + * + * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that + * rounding issues are minimised. + * + * The max xm of the values is extracted and the function is computing: + * xm + ln(exp(x1 - xm) + ... + exp(xn - xm)) + * + * @param[in] *in Pointer to an array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return LogSumExp + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math_f16.h" + +float16_t arm_logsumexp_f16(const float16_t *in, uint32_t blockSize) +{ + float16_t maxVal; + const float16_t *pIn; + int32_t blkCnt; + _Float16 accum=0.0f16; + _Float16 tmp; + + + arm_max_no_idx_f16((float16_t *) in, blockSize, &maxVal); + + + blkCnt = blockSize; + pIn = in; + + + f16x8_t vSum = vdupq_n_f16(0.0f16); + blkCnt = blockSize >> 3; + while(blkCnt > 0) + { + f16x8_t vecIn = vld1q(pIn); + f16x8_t vecExp; + + vecExp = vexpq_f16(vsubq_n_f16(vecIn, maxVal)); + + vSum = vaddq_f16(vSum, vecExp); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pIn += 8; + blkCnt --; + } + + /* sum + log */ + accum = vecAddAcrossF16Mve(vSum); + + blkCnt = blockSize & 0x7; + while(blkCnt > 0) + { + tmp = *pIn++; + accum += expf(tmp - maxVal); + blkCnt--; + + } + + accum = maxVal + logf(accum); + + return (accum); +} + +#else +float16_t arm_logsumexp_f16(const float16_t *in, uint32_t blockSize) +{ + _Float16 maxVal; + _Float16 tmp; + const float16_t *pIn; + uint32_t blkCnt; + _Float16 accum; + + pIn = in; + blkCnt = blockSize; + + maxVal = *pIn++; + blkCnt--; + + while(blkCnt > 0) + { + tmp = *pIn++; + + if (tmp > maxVal) + { + maxVal = tmp; + } + blkCnt--; + + } + + blkCnt = blockSize; + pIn = in; + accum = 0; + while(blkCnt > 0) + { + tmp = *pIn++; + accum += expf(tmp - maxVal); + blkCnt--; + + } + accum = maxVal + logf(accum); + + return(accum); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of LogSumExp group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_f32.c new file mode 100644 index 00000000..25daaf05 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_f32.c @@ -0,0 +1,277 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f32.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#include +#include + + +/** + * @addtogroup LogSumExp + * @{ + */ + + +/** + * @brief Computation of the LogSumExp + * + * In probabilistic computations, the dynamic of the probability values can be very + * wide because they come from gaussian functions. + * To avoid underflow and overflow issues, the values are represented by their log. + * In this representation, multiplying the original exp values is easy : their logs are added. + * But adding the original exp values is requiring some special handling and it is the + * goal of the LogSumExp function. + * + * If the values are x1...xn, the function is computing: + * + * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that + * rounding issues are minimised. + * + * The max xm of the values is extracted and the function is computing: + * xm + ln(exp(x1 - xm) + ... + exp(xn - xm)) + * + * @param[in] *in Pointer to an array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return LogSumExp + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize) +{ + float32_t maxVal; + const float32_t *pIn; + int32_t blkCnt; + float32_t accum=0.0f; + float32_t tmp; + + + arm_max_no_idx_f32((float32_t *) in, blockSize, &maxVal); + + + blkCnt = blockSize; + pIn = in; + + + f32x4_t vSum = vdupq_n_f32(0.0f); + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + f32x4_t vecIn = vld1q(pIn); + f32x4_t vecExp; + + vecExp = vexpq_f32(vsubq_n_f32(vecIn, maxVal)); + + vSum = vaddq_f32(vSum, vecExp); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pIn += 4; + blkCnt --; + } + + /* sum + log */ + accum = vecAddAcrossF32Mve(vSum); + + blkCnt = blockSize & 0x3; + while(blkCnt > 0) + { + tmp = *pIn++; + accum += expf(tmp - maxVal); + blkCnt--; + + } + + accum = maxVal + log(accum); + + return (accum); +} + +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "NEMath.h" +float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize) +{ + float32_t maxVal; + float32_t tmp; + float32x4_t tmpV, tmpVb; + float32x4_t maxValV; + uint32x4_t idxV; + float32x4_t accumV; + float32x2_t accumV2; + + const float32_t *pIn; + uint32_t blkCnt; + float32_t accum; + + pIn = in; + + blkCnt = blockSize; + + if (blockSize <= 3) + { + maxVal = *pIn++; + blkCnt--; + + while(blkCnt > 0) + { + tmp = *pIn++; + + if (tmp > maxVal) + { + maxVal = tmp; + } + blkCnt--; + } + } + else + { + maxValV = vld1q_f32(pIn); + pIn += 4; + blkCnt = (blockSize - 4) >> 2; + + while(blkCnt > 0) + { + tmpVb = vld1q_f32(pIn); + pIn += 4; + + idxV = vcgtq_f32(tmpVb, maxValV); + maxValV = vbslq_f32(idxV, tmpVb, maxValV ); + + blkCnt--; + } + + accumV2 = vpmax_f32(vget_low_f32(maxValV),vget_high_f32(maxValV)); + accumV2 = vpmax_f32(accumV2,accumV2); + maxVal = vget_lane_f32(accumV2, 0) ; + + blkCnt = (blockSize - 4) & 3; + + while(blkCnt > 0) + { + tmp = *pIn++; + + if (tmp > maxVal) + { + maxVal = tmp; + } + blkCnt--; + } + + } + + + + maxValV = vdupq_n_f32(maxVal); + pIn = in; + accum = 0; + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + + while(blkCnt > 0) + { + tmpV = vld1q_f32(pIn); + pIn += 4; + tmpV = vsubq_f32(tmpV, maxValV); + tmpV = vexpq_f32(tmpV); + accumV = vaddq_f32(accumV, tmpV); + + blkCnt--; + + } + accumV2 = vpadd_f32(vget_low_f32(accumV),vget_high_f32(accumV)); + accum = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + blkCnt = blockSize & 0x3; + while(blkCnt > 0) + { + tmp = *pIn++; + accum += expf(tmp - maxVal); + blkCnt--; + + } + + accum = maxVal + logf(accum); + + return(accum); +} +#else +float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize) +{ + float32_t maxVal; + float32_t tmp; + const float32_t *pIn; + uint32_t blkCnt; + float32_t accum; + + pIn = in; + blkCnt = blockSize; + + maxVal = *pIn++; + blkCnt--; + + while(blkCnt > 0) + { + tmp = *pIn++; + + if (tmp > maxVal) + { + maxVal = tmp; + } + blkCnt--; + + } + + blkCnt = blockSize; + pIn = in; + accum = 0; + while(blkCnt > 0) + { + tmp = *pIn++; + accum += expf(tmp - maxVal); + blkCnt--; + + } + accum = maxVal + logf(accum); + + return(accum); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of LogSumExp group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f16.c new file mode 100644 index 00000000..b9b64f0b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f16.c @@ -0,0 +1,246 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_f16.c + * Description: Maximum value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_max_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; + f16x8_t vecSrc; + f16x8_t curExtremValVec = vdupq_n_f16(F16_MIN); + float16_t maxValue = F16_MIN; + uint32_t idx = blockSize; + uint16x8_t indexVec; + uint16x8_t curExtremIdxVec; + uint32_t curIdx = 0; + mve_pred16_t p0; + float16_t tmp; + + + indexVec = vidupq_wb_u16(&curIdx, 1); + curExtremIdxVec = vdupq_n_u16(0); + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecSrc = vldrhq_f16(pSrc); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = vidupq_wb_u16(&curIdx, 1); + + pSrc += 8; + /* Decrement the loop counter */ + blkCnt--; + } + + + /* + * Get max value across the vector + */ + maxValue = vmaxnmvq(maxValue, curExtremValVec); + /* + * set index for lower values to max possible index + */ + p0 = vcmpgeq(curExtremValVec, maxValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u16(blockSize), p0); + /* + * Get min index which is thus for a max value + */ + idx = vminvq(idx, indexVec); + + /* Tail */ + blkCnt = blockSize & 7; + + while (blkCnt > 0) + { + /* Initialize tmp to the next consecutive values one by one */ + tmp = *pSrc++; + + /* compare for the maximum value */ + if (maxValue < tmp) + { + /* Update the maximum value and it's index */ + maxValue = tmp; + idx = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* + * Save result + */ + *pIndex = idx; + *pResult = maxValue; +} + +#else +void arm_max_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Max group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c new file mode 100644 index 00000000..d82b0390 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c @@ -0,0 +1,365 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_f32.c + * Description: Maximum value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + +/** + @defgroup Max Maximum + + Computes the maximum value of an array of data. + The function returns both the maximum value and its position within the array. + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + uint32_t blkCnt; + f32x4_t vecSrc; + f32x4_t curExtremValVec = vdupq_n_f32(F32_MIN); + float32_t maxValue = F32_MIN; + uint32_t idx = blockSize; + uint32x4_t indexVec; + uint32x4_t curExtremIdxVec; + uint32_t curIdx = 0; + mve_pred16_t p0; + float32_t tmp; + + + indexVec = vidupq_wb_u32(&curIdx, 1); + curExtremIdxVec = vdupq_n_u32(0); + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + vecSrc = vldrwq_f32(pSrc); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = vidupq_wb_u32(&curIdx, 1); + + pSrc += 4; + /* Decrement the loop counter */ + blkCnt--; + } + + + /* + * Get max value across the vector + */ + maxValue = vmaxnmvq(maxValue, curExtremValVec); + /* + * set index for lower values to max possible index + */ + p0 = vcmpgeq(curExtremValVec, maxValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u32(blockSize), p0); + /* + * Get min index which is thus for a max value + */ + idx = vminvq(idx, indexVec); + + /* Tail */ + blkCnt = blockSize & 0x3; + + while (blkCnt > 0U) + { + /* Initialize tmp to the next consecutive values one by one */ + tmp = *pSrc++; + + /* compare for the maximum value */ + if (maxValue < tmp) + { + /* Update the maximum value and it's index */ + maxValue = tmp; + idx = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* + * Save result + */ + *pIndex = idx; + *pResult = maxValue; +} + +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t maxVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* loop counter */ + + float32x4_t outV, srcV; + float32x2_t outV2; + + uint32x4_t idxV; + uint32x4_t maxIdx; + static const uint32_t indexInit[4]={4,5,6,7}; + static const uint32_t countVInit[4]={0,1,2,3}; + + uint32x4_t index; + uint32x4_t delta; + uint32x4_t countV; + uint32x2_t countV2; + + maxIdx = vdupq_n_u32(ULONG_MAX); + delta = vdupq_n_u32(4); + index = vld1q_u32(indexInit); + countV = vld1q_u32(countVInit); + + + /* Initialise the index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparison */ + if (blockSize <= 3) + { + out = *pSrc++; + + blkCnt = blockSize - 1; + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal1) + { + /* Update the maximum value and it's index */ + out = maxVal1; + outIndex = blockSize - blkCnt; + } + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + outV = vld1q_f32(pSrc); + pSrc += 4; + + /* Compute 4 outputs at a time */ + blkCnt = (blockSize - 4 ) >> 2U; + + while (blkCnt > 0U) + { + srcV = vld1q_f32(pSrc); + pSrc += 4; + + idxV = vcgtq_f32(srcV, outV); + outV = vbslq_f32(idxV, srcV, outV ); + countV = vbslq_u32(idxV, index,countV ); + + index = vaddq_u32(index,delta); + + /* Decrement the loop counter */ + blkCnt--; + } + + outV2 = vpmax_f32(vget_low_f32(outV),vget_high_f32(outV)); + outV2 = vpmax_f32(outV2,outV2); + out = vget_lane_f32(outV2, 0); + + idxV = vceqq_f32(outV, vdupq_n_f32(out)); + countV = vbslq_u32(idxV, countV,maxIdx); + + countV2 = vpmin_u32(vget_low_u32(countV),vget_high_u32(countV)); + countV2 = vpmin_u32(countV2,countV2); + outIndex = vget_lane_u32(countV2,0); + + /* if (blockSize - 1U) is not multiple of 4 */ + blkCnt = (blockSize - 4 ) % 4U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal1) + { + /* Update the maximum value and it's index */ + out = maxVal1; + outIndex = blockSize - blkCnt ; + } + + /* Decrement the loop counter */ + blkCnt--; + } + + + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#else +void arm_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Max group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f64.c new file mode 100644 index 00000000..83612190 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f64.c @@ -0,0 +1,90 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_f64.c + * Description: Maximum value of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +void arm_max_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex) +{ + float64_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +/** + @} end of Max group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f16.c new file mode 100644 index 00000000..3a95b4be --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f16.c @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_no_idx_f16.c + * Description: Maximum value of a floating-point vector without returning the index + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_max_no_idx_f16( + const float16_t *pSrc, + uint32_t blockSize, + float16_t *pResult) +{ + f16x8_t vecSrc; + f16x8_t curExtremValVec = vdupq_n_f16(F16_MIN); + float16_t maxValue = F16_MIN; + float16_t newVal; + uint32_t blkCnt; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + + vecSrc = vldrhq_f16(pSrc); + /* + * update per-lane max. + */ + curExtremValVec = vmaxnmq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 8; + blkCnt --; + } + /* + * Get max value across the vector + */ + maxValue = vmaxnmvq(maxValue, curExtremValVec); + + blkCnt = blockSize & 7; + + while (blkCnt > 0U) + { + newVal = *pSrc++; + + /* compare for the maximum value */ + if (maxValue < newVal) + { + /* Update the maximum value and it's index */ + maxValue = newVal; + } + + blkCnt --; + } + + *pResult = maxValue; +} + +#else + +void arm_max_no_idx_f16( + const float16_t *pSrc, + uint32_t blockSize, + float16_t *pResult) +{ + float16_t maxValue = F16_MIN; + float16_t newVal; + + while (blockSize > 0U) + { + newVal = *pSrc++; + + /* compare for the maximum value */ + if (maxValue < newVal) + { + /* Update the maximum value and it's index */ + maxValue = newVal; + } + + blockSize --; + } + + *pResult = maxValue; +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Max group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f32.c new file mode 100644 index 00000000..9a2a015a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f32.c @@ -0,0 +1,138 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_no_idx_f32.c + * Description: Maximum value of a floating-point vector without returning the index + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_max_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult) +{ + f32x4_t vecSrc; + f32x4_t curExtremValVec = vdupq_n_f32(F32_MIN); + float32_t maxValue = F32_MIN; + float32_t newVal; + uint32_t blkCnt; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + + vecSrc = vldrwq_f32(pSrc); + /* + * update per-lane max. + */ + curExtremValVec = vmaxnmq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 4; + blkCnt --; + } + /* + * Get max value across the vector + */ + maxValue = vmaxnmvq(maxValue, curExtremValVec); + + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + newVal = *pSrc++; + + /* compare for the maximum value */ + if (maxValue < newVal) + { + /* Update the maximum value and it's index */ + maxValue = newVal; + } + + blkCnt --; + } + + *pResult = maxValue; +} + +#else + +void arm_max_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult) +{ + float32_t maxValue = F32_MIN; + float32_t newVal; + + while (blockSize > 0U) + { + newVal = *pSrc++; + + /* compare for the maximum value */ + if (maxValue < newVal) + { + /* Update the maximum value and it's index */ + maxValue = newVal; + } + + blockSize --; + } + + *pResult = maxValue; +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Max group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f64.c new file mode 100644 index 00000000..7eca31c5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f64.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_no_idx_f64.c + * Description: Maximum value of a floating-point vector without returning the index + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ +void arm_max_no_idx_f64( + const float64_t *pSrc, + uint32_t blockSize, + float64_t *pResult) +{ + float64_t maxValue = F64_MIN; + float64_t newVal; + + while (blockSize > 0U) + { + newVal = *pSrc++; + + /* compare for the maximum value */ + if (maxValue < newVal) + { + /* Update the maximum value and it's index */ + maxValue = newVal; + } + + blockSize --; + } + + *pResult = maxValue; +} + +/** + @} end of Max group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q15.c new file mode 100644 index 00000000..2adea1ad --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q15.c @@ -0,0 +1,142 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_no_idx_q15.c + * Description: Maximum value of a q15 vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a q15 vector without index. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_max_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q15_t const *pSrcVec; + q15x8_t curExtremValVec = vdupq_n_s16(Q15_MIN); + q15_t maxValue = Q15_MIN; + mve_pred16_t p0; + + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + /* + * update per-lane max. + */ + curExtremValVec = vmaxq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + p0 = vctp16q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxq_m(curExtremValVec, vecSrc, curExtremValVec, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxvq(maxValue, curExtremValVec); + *pResult = maxValue; +} + +#else +void arm_max_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q15_t maxVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* loop counter */ + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal1) + { + /* Update the maximum value */ + out = maxVal1; + } + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the maximum value into destination pointer */ + *pResult = out; +} + +#endif /* #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of Max group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q31.c new file mode 100644 index 00000000..9c7a425c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q31.c @@ -0,0 +1,142 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_no_idx_q31.c + * Description: Maximum value of a q31 vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a q31 vector without index. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_max_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q31_t const *pSrcVec; + q31x4_t curExtremValVec = vdupq_n_s32(Q31_MIN); + q31_t maxValue = Q31_MIN; + mve_pred16_t p0; + + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + /* + * update per-lane max. + */ + curExtremValVec = vmaxq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + p0 = vctp32q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxq_m(curExtremValVec, vecSrc, curExtremValVec, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxvq(maxValue, curExtremValVec); + *pResult = maxValue; +} + +#else +void arm_max_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q31_t maxVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* loop counter */ + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal1) + { + /* Update the maximum value */ + out = maxVal1; + } + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the maximum value into destination pointer */ + *pResult = out; +} + +#endif /* #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of Max group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q7.c new file mode 100644 index 00000000..a6a61b74 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q7.c @@ -0,0 +1,143 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_no_idx_q7.c + * Description: Maximum value of a q7 vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a q7 vector without index. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_max_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7_t const *pSrcVec; + q7x16_t curExtremValVec = vdupq_n_s8(Q7_MIN); + q7_t maxValue = Q7_MIN; + mve_pred16_t p0; + + + pSrcVec = (q7_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + /* + * update per-lane max. + */ + curExtremValVec = vmaxq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + p0 = vctp8q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxq_m(curExtremValVec, vecSrc, curExtremValVec, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxvq(maxValue, curExtremValVec); + *pResult = maxValue; +} + +#else + +void arm_max_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + q7_t maxVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* loop counter */ + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal1) + { + /* Update the maximum value */ + out = maxVal1; + } + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the maximum value into destination pointer */ + *pResult = out; +} + +#endif /* #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of Max group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c new file mode 100644 index 00000000..5715e37b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c @@ -0,0 +1,201 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_q15.c + * Description: Maximum value of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_max_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + q15x8_t extremValVec = vdupq_n_s16(Q15_MIN); + q15_t maxValue = Q15_MIN; + uint16x8_t indexVec; + uint16x8_t extremIdxVec; + mve_pred16_t p0; + uint16_t extremIdxArr[8]; + + indexVec = vidupq_u16(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp16q(blkCnt); + q15x8_t extremIdxVal = vld1q_z_s16(pSrc, p); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u16(extremIdxArr, indexVec, p0); + + indexVec += 8; + pSrc += 8; + blkCnt -= 8; + } + while (blkCnt > 0); + + + /* Get max value across the vector */ + maxValue = vmaxvq(maxValue, extremValVec); + + /* set index for lower values to max possible index */ + p0 = vcmpgeq(extremValVec, maxValue); + extremIdxVec = vld1q_u16(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u16(blockSize - 1), p0); + *pIndex = vminvq(blockSize - 1, indexVec); + *pResult = maxValue; +} + +#else +void arm_max_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEI) */ +/** + @} end of Max group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c new file mode 100644 index 00000000..fed900b8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c @@ -0,0 +1,202 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_q31.c + * Description: Maximum value of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_max_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + q31x4_t extremValVec = vdupq_n_s32(Q31_MIN); + q31_t maxValue = Q31_MIN; + uint32x4_t indexVec; + uint32x4_t extremIdxVec; + mve_pred16_t p0; + uint32_t extremIdxArr[4]; + + indexVec = vidupq_u32(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp32q(blkCnt); + q31x4_t extremIdxVal = vld1q_z_s32(pSrc, p); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u32(extremIdxArr, indexVec, p0); + + indexVec += 4; + pSrc += 4; + blkCnt -= 4; + } + while (blkCnt > 0); + + + /* Get max value across the vector */ + maxValue = vmaxvq(maxValue, extremValVec); + + /* set index for lower values to max possible index */ + p0 = vcmpgeq(extremValVec, maxValue); + extremIdxVec = vld1q_u32(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u32(blockSize - 1), p0); + *pIndex = vminvq(blockSize - 1, indexVec); + *pResult = maxValue; +} + +#else +void arm_max_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Max group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c new file mode 100644 index 00000000..5deae648 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c @@ -0,0 +1,256 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_q7.c + * Description: Maximum value of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +static void arm_small_blk_max_q7( + const q7_t * pSrc, + uint16_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + q7x16_t extremValVec = vdupq_n_s8(Q7_MIN); + q7_t maxValue = Q7_MIN; + uint8x16_t indexVec; + uint8x16_t extremIdxVec; + mve_pred16_t p0; + uint8_t extremIdxArr[16]; + + indexVec = vidupq_u8(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp8q(blkCnt); + q7x16_t extremIdxVal = vld1q_z_s8(pSrc, p); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u8(extremIdxArr, indexVec, p0); + + indexVec += 16; + pSrc += 16; + blkCnt -= 16; + } + while (blkCnt > 0); + + + /* Get max value across the vector */ + maxValue = vmaxvq(maxValue, extremValVec); + + /* set index for lower values to max possible index */ + p0 = vcmpgeq(extremValVec, maxValue); + extremIdxVec = vld1q_u8(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u8(blockSize - 1), p0); + *pIndex = vminvq_u8(blockSize - 1, indexVec); + *pResult = maxValue; +} + +void arm_max_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + int32_t totalSize = blockSize; + const uint16_t sub_blk_sz = UINT8_MAX + 1; + + if (totalSize <= sub_blk_sz) + { + arm_small_blk_max_q7(pSrc, blockSize, pResult, pIndex); + } + else + { + uint32_t curIdx = 0; + q7_t curBlkExtr = Q7_MIN; + uint32_t curBlkPos = 0; + uint32_t curBlkIdx = 0; + /* + * process blocks of 255 elts + */ + while (totalSize >= sub_blk_sz) + { + const q7_t *curSrc = pSrc; + + arm_small_blk_max_q7(curSrc, sub_blk_sz, pResult, pIndex); + if (*pResult > curBlkExtr) + { + /* + * update partial extrema + */ + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + curIdx++; + pSrc += sub_blk_sz; + totalSize -= sub_blk_sz; + } + /* + * remainder + */ + arm_small_blk_max_q7(pSrc, totalSize, pResult, pIndex); + if (*pResult > curBlkExtr) + { + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + *pIndex = curBlkIdx * sub_blk_sz + curBlkPos; + *pResult = curBlkExtr; + } +} +#else +void arm_max_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Max group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f16.c new file mode 100644 index 00000000..02f495d6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f16.c @@ -0,0 +1,152 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mean_f16.c + * Description: Mean value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + +/** + @defgroup mean Mean + + Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector. + The underlying algorithm is used: + +
+      Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;
+  
+ + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a floating-point vector. + @param[in] pSrc points to the input vector. + @param[in] blockSize number of samples in input vector. + @param[out] pResult mean value returned here. + @return none + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_mean_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + f16x8_t sumVec = vdupq_n_f16(0.0f16); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp16q(blkCnt); + + vecSrc = vldrhq_z_f16((float16_t const *) pSrc, p); + sumVec = vaddq_m_f16(sumVec, sumVec, vecSrc, p); + + blkCnt -= 8; + pSrc += 8; + } + while (blkCnt > 0); + + *pResult = vecAddAcrossF16Mve(sumVec) / (float16_t) blockSize; +} + + +#else + +void arm_mean_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float16_t sum = 0.0f; /* Temporary result storage */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (sum / (float16_t)blockSize); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of mean group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c new file mode 100644 index 00000000..dd6d817a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c @@ -0,0 +1,198 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mean_f32.c + * Description: Mean value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a floating-point vector. + @param[in] pSrc points to the input vector. + @param[in] blockSize number of samples in input vector. + @param[out] pResult mean value returned here. + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + f32x4_t vecSrc; + f32x4_t sumVec = vdupq_n_f32(0.0f); + float32_t sum = 0.0f; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + vecSrc = vldrwq_f32(pSrc); + sumVec = vaddq_f32(sumVec, vecSrc); + + blkCnt --; + pSrc += 4; + } + + sum = vecAddAcrossF32Mve(sumVec); + + /* Tail */ + blkCnt = blockSize & 0x3; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + *pResult = sum / (float32_t) blockSize; +} + + +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t sum = 0.0f; /* Temporary result storage */ + float32x4_t sumV = vdupq_n_f32(0.0f); /* Temporary result storage */ + float32x2_t sumV2; + + uint32_t blkCnt; /* Loop counter */ + + float32x4_t inV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + inV = vld1q_f32(pSrc); + sumV = vaddq_f32(sumV, inV); + + pSrc += 4; + /* Decrement the loop counter */ + blkCnt--; + } + + sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = vget_lane_f32(sumV2, 0) + vget_lane_f32(sumV2, 1); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store the result to the destination */ + *pResult = sum / (float32_t) blockSize; +} +#else +void arm_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (sum / blockSize); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of mean group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f64.c new file mode 100644 index 00000000..72e6f351 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f64.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mean_f64.c + * Description: Mean value of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a floating-point vector. + @param[in] pSrc points to the input vector. + @param[in] blockSize number of samples in input vector. + @param[out] pResult mean value returned here. + @return none + */ +void arm_mean_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float64_t sum = 0.; /* Temporary result storage */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (sum / blockSize); +} + +/** + @} end of mean group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c new file mode 100644 index 00000000..f8af0eda --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c @@ -0,0 +1,156 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mean_q15.c + * Description: Mean value of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + The input is represented in 1.15 format and is accumulated in a 32-bit + accumulator in 17.15 format. + There is no risk of internal overflow with this approach, and the + full precision of intermediate result is preserved. + Finally, the accumulator is truncated to yield a result of 1.15 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_mean_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q31_t sum = 0L; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; + while (blkCnt > 0U) + { + vecSrc = vldrhq_s16(pSrc); + /* + * sum lanes + */ + sum = vaddvaq(sum, vecSrc); + + blkCnt--; + pSrc += 8; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store the result to the destination */ + *pResult = (q15_t) (sum / (int32_t) blockSize); +} +#else +void arm_mean_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Temporary result storage */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t in; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + in = read_q15x2_ia ((q15_t **) &pSrc); + sum += ((in << 16U) >> 16U); + sum += (in >> 16U); + + in = read_q15x2_ia ((q15_t **) &pSrc); + sum += ((in << 16U) >> 16U); + sum += (in >> 16U); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (q15_t) (sum / (int32_t) blockSize); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of mean group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c new file mode 100644 index 00000000..b33ed00c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c @@ -0,0 +1,149 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mean_q31.c + * Description: Mean value of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.31 format and is accumulated in a 64-bit + accumulator in 33.31 format. + There is no risk of internal overflow with this approach, and the + full precision of intermediate result is preserved. + Finally, the accumulator is truncated to yield a result of 1.31 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_mean_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q63_t sum = 0LL; + + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + + vecSrc = vldrwq_s32(pSrc); + /* + * sum lanes + */ + sum = vaddlvaq(sum, vecSrc); + + blkCnt --; + pSrc += 4; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + blkCnt --; + } + + *pResult = arm_div_q63_to_q31(sum, blockSize); +} +#else +void arm_mean_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (q31_t) (sum / blockSize); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of mean group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c new file mode 100644 index 00000000..8cb68b26 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c @@ -0,0 +1,153 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mean_q7.c + * Description: Mean value of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + The input is represented in 1.7 format and is accumulated in a 32-bit + accumulator in 25.7 format. + There is no risk of internal overflow with this approach, and the + full precision of intermediate result is preserved. + Finally, the accumulator is truncated to yield a result of 1.7 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_mean_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q31_t sum = 0L; + + + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + vecSrc = vldrbq_s8(pSrc); + /* + * sum lanes + */ + sum = vaddvaq(sum, vecSrc); + + blkCnt--; + pSrc += 16; + } + + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store the result to the destination */ + *pResult = (q7_t) (sum / (int32_t) blockSize); +} +#else +void arm_mean_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Temporary result storage */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t in; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + in = read_q7x4_ia ((q7_t **) &pSrc); + sum += ((in << 24U) >> 24U); + sum += ((in << 16U) >> 24U); + sum += ((in << 8U) >> 24U); + sum += (in >> 24U); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (q7_t) (sum / (int32_t) blockSize); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of mean group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f16.c new file mode 100644 index 00000000..0d123f54 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f16.c @@ -0,0 +1,240 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_f16.c + * Description: Minimum value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + + +/** + @ingroup groupStats + */ + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_min_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + float16_t const *pSrcVec; + f16x8_t curExtremValVec = vdupq_n_f16(F16_MAX); + float16_t minValue = F16_MAX; + uint32_t idx = blockSize; + uint16x8_t indexVec; + uint16x8_t curExtremIdxVec; + mve_pred16_t p0; + + indexVec = vidupq_u16((uint32_t)0, 1); + curExtremIdxVec = vdupq_n_u16(0); + + pSrcVec = (float16_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecSrc = vldrhq_f16(pSrcVec); pSrcVec += 8; + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = indexVec + 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0) + { + vecSrc = vldrhq_f16(pSrcVec); pSrcVec += 8; + p0 = vctp16q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq_m(vecSrc, curExtremValVec, p0); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminnmvq(minValue, curExtremValVec); + /* + * set index for lower values to min possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u16(blockSize), p0); + /* + * Get min index which is thus for a min value + */ + idx = vminvq(idx, indexVec); + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + +#else + +void arm_min_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Min group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c new file mode 100644 index 00000000..ad8a4720 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c @@ -0,0 +1,363 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_f32.c + * Description: Minimum value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + + +/** + @ingroup groupStats + */ + +/** + @defgroup Min Minimum + + Computes the minimum value of an array of data. + The function returns both the minimum value and its position within the array. + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + uint32_t blkCnt; /* loop counters */ + f32x4_t vecSrc; + float32_t const *pSrcVec; + f32x4_t curExtremValVec = vdupq_n_f32(F32_MAX); + float32_t minValue = F32_MAX; + uint32_t idx = blockSize; + uint32x4_t indexVec; + uint32x4_t curExtremIdxVec; + float32_t tmp; + mve_pred16_t p0; + + indexVec = vidupq_u32((uint32_t)0, 1); + curExtremIdxVec = vdupq_n_u32(0); + + pSrcVec = (float32_t const *) pSrc; + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + vecSrc = vldrwq_f32(pSrcVec); + pSrcVec += 4; + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = indexVec + 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * Get min value across the vector + */ + minValue = vminnmvq(minValue, curExtremValVec); + /* + * set index for lower values to max possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u32(blockSize), p0); + /* + * Get min index which is thus for a max value + */ + idx = vminvq(idx, indexVec); + + /* + * tail + */ + blkCnt = blockSize & 0x3; + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + tmp = *pSrc++; + + /* compare for the minimum value */ + if (minValue > tmp) + { + /* Update the minimum value and it's index */ + minValue = tmp; + idx = blockSize - blkCnt; + } + blkCnt--; + } + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t maxVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* loop counter */ + + float32x4_t outV, srcV; + float32x2_t outV2; + + uint32x4_t idxV; + static const uint32_t indexInit[4]={4,5,6,7}; + static const uint32_t countVInit[4]={0,1,2,3}; + uint32x4_t maxIdx; + uint32x4_t index; + uint32x4_t delta; + uint32x4_t countV; + uint32x2_t countV2; + + maxIdx = vdupq_n_u32(ULONG_MAX); + delta = vdupq_n_u32(4); + index = vld1q_u32(indexInit); + countV = vld1q_u32(countVInit); + + /* Initialise the index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparison */ + if (blockSize <= 3) + { + out = *pSrc++; + + blkCnt = blockSize - 1; + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out > maxVal1) + { + /* Update the maximum value and it's index */ + out = maxVal1; + outIndex = blockSize - blkCnt; + } + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + outV = vld1q_f32(pSrc); + pSrc += 4; + + /* Compute 4 outputs at a time */ + blkCnt = (blockSize - 4 ) >> 2U; + + while (blkCnt > 0U) + { + srcV = vld1q_f32(pSrc); + pSrc += 4; + + idxV = vcltq_f32(srcV, outV); + outV = vbslq_f32(idxV, srcV, outV ); + countV = vbslq_u32(idxV, index,countV ); + + index = vaddq_u32(index,delta); + + /* Decrement the loop counter */ + blkCnt--; + } + + outV2 = vpmin_f32(vget_low_f32(outV),vget_high_f32(outV)); + outV2 = vpmin_f32(outV2,outV2); + out = vget_lane_f32(outV2,0); + + idxV = vceqq_f32(outV, vdupq_n_f32(out)); + countV = vbslq_u32(idxV, countV,maxIdx); + + countV2 = vpmin_u32(vget_low_u32(countV),vget_high_u32(countV)); + countV2 = vpmin_u32(countV2,countV2); + outIndex = vget_lane_u32(countV2,0); + + /* if (blockSize - 1U) is not multiple of 4 */ + blkCnt = (blockSize - 4 ) % 4U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out > maxVal1) + { + /* Update the maximum value and it's index */ + out = maxVal1; + outIndex = blockSize - blkCnt ; + } + + /* Decrement the loop counter */ + blkCnt--; + } + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#else +void arm_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Min group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f64.c new file mode 100644 index 00000000..ef25f920 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f64.c @@ -0,0 +1,90 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_f64.c + * Description: Minimum value of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +void arm_min_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex) +{ + float64_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +/** + @} end of Min group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f16.c new file mode 100644 index 00000000..5b4c0d66 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f16.c @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_no_idx_f16.c + * Description: Minimum value of a floating-point vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_min_no_idx_f16( + const float16_t *pSrc, + uint32_t blockSize, + float16_t *pResult) +{ + f16x8_t vecSrc; + f16x8_t curExtremValVec = vdupq_n_f16(F16_MAX); + float16_t minValue = F16_MAX; + float16_t newVal; + uint32_t blkCnt; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + + vecSrc = vldrhq_f16(pSrc); + /* + * update per-lane min. + */ + curExtremValVec = vminnmq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 8; + blkCnt --; + } + /* + * Get min value across the vector + */ + minValue = vminnmvq(minValue, curExtremValVec); + + blkCnt = blockSize & 7; + + while (blkCnt > 0U) + { + newVal = *pSrc++; + + /* compare for the minimum value */ + if ((_Float16)minValue > (_Float16)newVal) + { + /* Update the minimum value and it's index */ + minValue = newVal; + } + + blkCnt --; + } + + *pResult = minValue; +} + +#else + +void arm_min_no_idx_f16( + const float16_t *pSrc, + uint32_t blockSize, + float16_t *pResult) +{ + float16_t minValue = F16_MAX; + float16_t newVal; + + while (blockSize > 0U) + { + newVal = *pSrc++; + + /* compare for the minimum value */ + if ((_Float16)minValue > (_Float16)newVal) + { + /* Update the minimum value and it's index */ + minValue = newVal; + } + + blockSize --; + } + + *pResult = minValue; +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Min group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f32.c new file mode 100644 index 00000000..ea7c137d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f32.c @@ -0,0 +1,138 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_no_idx_f32.c + * Description: Minimum value of a floating-point vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_min_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult) +{ + f32x4_t vecSrc; + f32x4_t curExtremValVec = vdupq_n_f32(F32_MAX); + float32_t minValue = F32_MAX; + float32_t newVal; + uint32_t blkCnt; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + + vecSrc = vldrwq_f32(pSrc); + /* + * update per-lane min. + */ + curExtremValVec = vminnmq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 4; + blkCnt --; + } + /* + * Get min value across the vector + */ + minValue = vminnmvq(minValue, curExtremValVec); + + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + newVal = *pSrc++; + + /* compare for the minimum value */ + if (minValue > newVal) + { + /* Update the minimum value and it's index */ + minValue = newVal; + } + + blkCnt --; + } + + *pResult = minValue; +} + +#else + +void arm_min_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult) +{ + float32_t minValue = F32_MAX; + float32_t newVal; + + while (blockSize > 0U) + { + newVal = *pSrc++; + + /* compare for the minimum value */ + if (minValue > newVal) + { + /* Update the minimum value and it's index */ + minValue = newVal; + } + + blockSize --; + } + + *pResult = minValue; +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Min group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f64.c new file mode 100644 index 00000000..6e69572d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f64.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_no_idx_f64.c + * Description: Maximum value of a floating-point vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ +void arm_min_no_idx_f64( + const float64_t *pSrc, + uint32_t blockSize, + float64_t *pResult) +{ + float64_t minValue = F64_MAX; + float64_t newVal; + + while (blockSize > 0U) + { + newVal = *pSrc++; + + /* compare for the minimum value */ + if (minValue > newVal) + { + /* Update the minimum value and it's index */ + minValue = newVal; + } + + blockSize --; + } + + *pResult = minValue; +} + +/** + @} end of Min group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q15.c new file mode 100644 index 00000000..207f9ea9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q15.c @@ -0,0 +1,142 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_no_idx_q15.c + * Description: Minimum value of a q15 vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + + +/** + @ingroup groupStats + */ + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a q15 vector without index. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_min_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q15_t const *pSrcVec; + q15x8_t curExtremValVec = vdupq_n_s16(Q15_MAX); + q15_t minValue = Q15_MAX; + mve_pred16_t p0; + + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + /* + * update per-lane min. + */ + curExtremValVec = vminq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + p0 = vctp16q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminq_m(curExtremValVec, vecSrc, curExtremValVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminvq(minValue, curExtremValVec); + *pResult = minValue; +} + +#else +void arm_min_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q15_t minVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* loop counter */ + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal1 = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal1) + { + /* Update the minimum value */ + out = minVal1; + } + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the minimum value into destination pointer */ + *pResult = out; +} + +#endif /* #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of Min group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q31.c new file mode 100644 index 00000000..e425db4f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q31.c @@ -0,0 +1,141 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_no_idx_q31.c + * Description: Minimum value of a q31 vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + + +/** + @ingroup groupStats + */ + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a q31 vector without index. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_min_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q31_t const *pSrcVec; + q31x4_t curExtremValVec = vdupq_n_s32(Q31_MAX); + q31_t minValue = Q31_MAX; + mve_pred16_t p0; + + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + /* + * update per-lane min. + */ + curExtremValVec = vminq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + p0 = vctp32q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminq_m(curExtremValVec, vecSrc, curExtremValVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminvq(minValue, curExtremValVec); + *pResult = minValue; +} + +#else +void arm_min_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q31_t minVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* loop counter */ + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal1 = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal1) + { + /* Update the minimum value */ + out = minVal1; + } + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the minimum value into destination pointer */ + *pResult = out; +} + +#endif /* #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of Min group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q7.c new file mode 100644 index 00000000..2ee9a994 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q7.c @@ -0,0 +1,141 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_no_idx_q7.c + * Description: Minimum value of a q7 vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + + +/** + @ingroup groupStats + */ + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a q7 vector without index. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_min_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7_t const *pSrcVec; + q7x16_t curExtremValVec = vdupq_n_s8(Q7_MAX); + q7_t minValue = Q7_MAX; + mve_pred16_t p0; + + + pSrcVec = (q7_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + /* + * update per-lane min. + */ + curExtremValVec = vminq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + p0 = vctp8q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminq_m(curExtremValVec, vecSrc, curExtremValVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminvq(minValue, curExtremValVec); + *pResult = minValue; +} + +#else +void arm_min_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + q7_t minVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* loop counter */ + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal1 = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal1) + { + /* Update the minimum value */ + out = minVal1; + } + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the minimum value into destination pointer */ + *pResult = out; +} + +#endif /* #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of Min group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c new file mode 100644 index 00000000..f31019db --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c @@ -0,0 +1,203 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_q15.c + * Description: Minimum value of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_min_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + + int32_t blkCnt; /* loop counters */ + q15x8_t extremValVec = vdupq_n_s16(Q15_MAX); + q15_t minValue = Q15_MAX; + uint16x8_t indexVec; + uint16x8_t extremIdxVec; + mve_pred16_t p0; + uint16_t extremIdxArr[8]; + + indexVec = vidupq_u16(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp16q(blkCnt); + q15x8_t extremIdxVal = vld1q_z_s16(pSrc, p); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u16(extremIdxArr, indexVec, p0); + + indexVec += 8; + pSrc += 8; + blkCnt -= 8; + } + while (blkCnt > 0); + + /* Get min value across the vector */ + minValue = vminvq(minValue, extremValVec); + + /* set index for lower values to min possible index */ + p0 = vcmpleq(extremValVec, minValue); + extremIdxVec = vld1q_u16(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u16(blockSize - 1), p0); + *pIndex = vminvq(blockSize - 1, indexVec); + *pResult = minValue; + +} +#else +void arm_min_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Min group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c new file mode 100644 index 00000000..c993004c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c @@ -0,0 +1,203 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_q31.c + * Description: Minimum value of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_min_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + q31x4_t extremValVec = vdupq_n_s32(Q31_MAX); + q31_t minValue = Q31_MAX; + uint32x4_t indexVec; + uint32x4_t extremIdxVec; + mve_pred16_t p0; + uint32_t extremIdxArr[4]; + + indexVec = vidupq_u32(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp32q(blkCnt); + q31x4_t extremIdxVal = vld1q_z_s32(pSrc, p); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u32(extremIdxArr, indexVec, p0); + + indexVec += 4; + pSrc += 4; + blkCnt -= 4; + } + while (blkCnt > 0); + + + /* Get min value across the vector */ + minValue = vminvq(minValue, extremValVec); + + /* set index for lower values to min possible index */ + p0 = vcmpleq(extremValVec, minValue); + extremIdxVec = vld1q_u32(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u32(blockSize - 1), p0); + *pIndex = vminvq(blockSize - 1, indexVec); + *pResult = minValue; +} + +#else +void arm_min_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Min group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c new file mode 100644 index 00000000..3e5aae53 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c @@ -0,0 +1,284 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_q7.c + * Description: Minimum value of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +static void arm_small_blk_min_q7( + const q7_t * pSrc, + uint8_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7x16_t curExtremValVec = vdupq_n_s8(Q7_MAX); + q7_t minValue = Q7_MAX,temp; + uint32_t idx = blockSize; + uint8x16_t indexVec; + uint8x16_t curExtremIdxVec; + mve_pred16_t p0; + + + indexVec = vidupq_u8((uint32_t)0, 1); + curExtremIdxVec = vdupq_n_u8(0); + + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + vecSrc = vldrbq_s8(pSrc); + pSrc += 16; + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = indexVec + 16; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * Get min value across the vector + */ + minValue = vminvq(minValue, curExtremValVec); + /* + * set index for lower values to min possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u8(blockSize), p0); + /* + * Get min index which is thus for a min value + */ + idx = vminvq(idx, indexVec); + + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + temp = *pSrc++; + + /* compare for the minimum value */ + if (minValue > temp) + { + /* Update the minimum value and it's index */ + minValue = temp; + idx = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + +void arm_min_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + int32_t totalSize = blockSize; + + if (totalSize <= UINT8_MAX) + { + arm_small_blk_min_q7(pSrc, blockSize, pResult, pIndex); + } + else + { + uint32_t curIdx = 0; + q7_t curBlkExtr = Q7_MAX; + uint32_t curBlkPos = 0; + uint32_t curBlkIdx = 0; + /* + * process blocks of 255 elts + */ + while (totalSize >= UINT8_MAX) + { + const q7_t *curSrc = pSrc; + + arm_small_blk_min_q7(curSrc, UINT8_MAX, pResult, pIndex); + if (*pResult < curBlkExtr) + { + /* + * update partial extrema + */ + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + curIdx++; + pSrc += UINT8_MAX; + totalSize -= UINT8_MAX; + } + /* + * remainder + */ + arm_small_blk_min_q7(pSrc, totalSize, pResult, pIndex); + if (*pResult < curBlkExtr) + { + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + *pIndex = curBlkIdx * UINT8_MAX + curBlkPos; + *pResult = curBlkExtr; + } +} +#else +void arm_min_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Min group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f16.c new file mode 100644 index 00000000..3b192dd6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f16.c @@ -0,0 +1,203 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mse_f16.c + * Description: Half floating point mean square error + * + * $Date: 05 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup MSE + @{ + */ + +/** + @brief Mean square error between two half floating point vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] result mean square error + @return none + */ + +#if !defined(ARM_MATH_AUTOVECTORIZE) + +#if defined(ARM_MATH_MVE_FLOAT16) +#include "arm_helium_utils.h" + +void arm_mse_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t * result) + +{ + float16x8_t vecA, vecB; + float16x8_t vecSum; + uint32_t blkCnt; + _Float16 sum = 0.0f16; + vecSum = vdupq_n_f16(0.0f16); + + blkCnt = (blockSize) >> 3; + while (blkCnt > 0U) + { + vecA = vld1q(pSrcA); + pSrcA += 8; + + vecB = vld1q(pSrcB); + pSrcB += 8; + + vecA = vsubq(vecA, vecB); + + vecSum = vfmaq(vecSum, vecA, vecA); + /* + * Decrement the blockSize loop counter + */ + blkCnt --; + } + + + blkCnt = (blockSize) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + + vecA = vsubq(vecA, vecB); + vecSum = vfmaq_m(vecSum, vecA, vecA, p0); + } + + sum = vecAddAcrossF16Mve(vecSum); + + /* Store result in destination buffer */ + *result = (_Float16)sum / (_Float16)blockSize; + +} + +#endif + + +#endif /*#if !defined(ARM_MATH_AUTOVECTORIZE)*/ + + +#if defined(ARM_FLOAT16_SUPPORTED) + +#if (!defined(ARM_MATH_MVE_FLOAT16)) || defined(ARM_MATH_AUTOVECTORIZE) + + + +void arm_mse_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t * result) + +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 inA, inB; + _Float16 sum = 0.0f16; /* Temporary return variable */ +#if defined (ARM_MATH_LOOPUNROLL) + blkCnt = (blockSize) >> 3; + + + while (blkCnt > 0U) + { + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + /* Decrement loop counter */ + blkCnt--; + } + + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize) & 7; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + while (blkCnt > 0U) + { + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = (_Float16)sum / (_Float16)blockSize; +} + +#endif /* end of test for vector instruction availability */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ +/** + @} end of MSE group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f32.c new file mode 100644 index 00000000..1c592f50 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f32.c @@ -0,0 +1,247 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mse_f32.c + * Description: Floating point mean square error + * + * $Date: 05 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup MSE + @{ + */ + +/** + @brief Mean square error between two floating point vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] result mean square error + @return none + */ + +#if !defined(ARM_MATH_AUTOVECTORIZE) + +#if defined(ARM_MATH_MVEF) +#include "arm_helium_utils.h" + +void arm_mse_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result) + +{ + float32x4_t vecA, vecB; + float32x4_t vecSum; + uint32_t blkCnt; + float32_t sum = 0.0f; + vecSum = vdupq_n_f32(0.0f); + + /* Compute 4 outputs at a time */ + blkCnt = (blockSize) >> 2; + while (blkCnt > 0U) + { + vecA = vld1q(pSrcA); + pSrcA += 4; + + vecB = vld1q(pSrcB); + pSrcB += 4; + + vecA = vsubq(vecA, vecB); + + vecSum = vfmaq(vecSum, vecA, vecA); + /* + * Decrement the blockSize loop counter + */ + blkCnt --; + } + + + blkCnt = (blockSize) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + + vecA = vsubq(vecA, vecB); + vecSum = vfmaq_m(vecSum, vecA, vecA, p0); + } + + sum = vecAddAcrossF32Mve(vecSum); + + /* Store result in destination buffer */ + *result = sum / blockSize; + +} + +#endif + +#if defined(ARM_MATH_NEON) +void arm_mse_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result) + +{ + float32x4_t vecA, vecB; + float32x4_t vecSum; + uint32_t blkCnt; + float32_t inA, inB; + float32_t sum = 0.0f; + vecSum = vdupq_n_f32(0.0f); +#if !defined(__aarch64__) + f32x2_t tmp = vdup_n_f32(0.0f); +#endif + + /* Compute 4 outputs at a time */ + blkCnt = (blockSize) >> 2; + while (blkCnt > 0U) + { + vecA = vld1q_f32(pSrcA); + pSrcA += 4; + + vecB = vld1q_f32(pSrcB); + pSrcB += 4; + + vecA = vsubq_f32(vecA, vecB); + + vecSum = vfmaq_f32(vecSum, vecA, vecA); + /* + * Decrement the blockSize loop counter + */ + blkCnt --; + } + +#if defined(__aarch64__) + sum = vpadds_f32(vpadd_f32(vget_low_f32(vecSum), vget_high_f32(vecSum))); +#else + tmp = vpadd_f32(vget_low_f32(vecSum), vget_high_f32(vecSum)); + sum = vget_lane_f32(tmp, 0) + vget_lane_f32(tmp, 1); + +#endif + + blkCnt = (blockSize) & 3; + while (blkCnt > 0U) + { + /* Calculate dot product and store result in a temporary buffer. */ + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = sum / blockSize; + +} +#endif + +#endif /*#if !defined(ARM_MATH_AUTOVECTORIZE)*/ + + + +#if (!defined(ARM_MATH_MVEF) && !defined(ARM_MATH_NEON)) || defined(ARM_MATH_AUTOVECTORIZE) + + +void arm_mse_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result) + +{ + uint32_t blkCnt; /* Loop counter */ + float32_t inA, inB; + float32_t sum = 0.0f; /* Temporary return variable */ +#if defined (ARM_MATH_LOOPUNROLL) + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize) >> 2; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + /* Decrement loop counter */ + blkCnt--; + } + + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize) & 3; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + while (blkCnt > 0U) + { + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = sum / blockSize; +} + +#endif /* end of test for vector instruction availability */ + +/** + @} end of MSE group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f64.c new file mode 100644 index 00000000..b785bf82 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f64.c @@ -0,0 +1,110 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mse_f64.c + * Description: Double floating point mean square error + * + * $Date: 05 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup MSE + @{ + */ + +/** + @brief Mean square error between two double floating point vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] result mean square error + @return none + */ + + + + + +void arm_mse_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + uint32_t blockSize, + float64_t * result) + +{ + uint32_t blkCnt; /* Loop counter */ + float64_t inA, inB; + float64_t sum = 0.0; /* Temporary return variable */ +#if defined (ARM_MATH_LOOPUNROLL) + blkCnt = (blockSize) >> 1; + + + while (blkCnt > 0U) + { + + + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + /* Decrement loop counter */ + blkCnt--; + } + + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize) & 1; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + while (blkCnt > 0U) + { + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = sum / blockSize; +} + + +/** + @} end of MSE group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q15.c new file mode 100644 index 00000000..9e6f0c03 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q15.c @@ -0,0 +1,175 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mse_q15.c + * Description: Mean square error between two Q15 vectors + * + * $Date: 04 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup MSE + @{ + */ + +/** + @brief Mean square error between two Q15 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_mse_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrcA,vecSrcB; + q63_t sum = 0LL; + + blkCnt = blockSize >> 3U; + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vecSrcA = vshrq(vecSrcA,1); + vecSrcB = vshrq(vecSrcB,1); + + vecSrcA = vqsubq(vecSrcA,vecSrcB); + /* + * sum lanes + */ + sum = vmlaldavaq(sum, vecSrcA, vecSrcA); + + blkCnt--; + pSrcA += 8; + pSrcB += 8; + } + + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vecSrcA = vshrq(vecSrcA,1); + vecSrcB = vshrq(vecSrcB,1); + + vecSrcA = vqsubq(vecSrcA,vecSrcB); + + sum = vmlaldavaq_p(sum, vecSrcA, vecSrcA, p0); + } + + + + *pResult = (q15_t) __SSAT((q31_t) (sum / blockSize)>>13, 16); +} +#else +void arm_mse_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q15_t inA,inB; /* Temporary variable to store input value */ + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q15_t) __SSAT(((q31_t) inA - (q31_t)inB), 16); + sum += (q63_t)((q31_t) inA * inA); + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q15_t) __SSAT(((q31_t) inA - (q31_t)inB), 16); + sum += (q63_t)((q31_t) inA * inA); + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q15_t) __SSAT(((q31_t) inA - (q31_t)inB), 16); + sum += (q63_t)((q31_t) inA * inA); + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q15_t) __SSAT(((q31_t) inA - (q31_t)inB), 16); + sum += (q63_t)((q31_t) inA * inA); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q15_t) __SSAT(((q31_t) inA - (q31_t)inB), 16); + sum += (q63_t)((q31_t) inA * inA); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in q15 format */ + *pResult = (q15_t) __SSAT((q31_t) (sum / blockSize)>>13, 16); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MSE group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q31.c new file mode 100644 index 00000000..e4444040 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q31.c @@ -0,0 +1,176 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mse_q31.c + * Description: Mean square error between two Q31 vectors + * + * $Date: 04 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup MSE + @{ + */ + +/** + @brief Mean square error between two Q31 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_mse_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrcA,vecSrcB; + q63_t sum = 0LL; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vecSrcA = vshrq(vecSrcA,1); + vecSrcB = vshrq(vecSrcB,1); + + + vecSrcA = vqsubq(vecSrcA,vecSrcB); + /* + * sum lanes + */ + sum = vrmlaldavhaq(sum, vecSrcA, vecSrcA); + + blkCnt--; + pSrcA += 4; + pSrcB += 4; + } + + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vecSrcA = vshrq(vecSrcA,1); + vecSrcB = vshrq(vecSrcB,1); + + vecSrcA = vqsubq(vecSrcA,vecSrcB); + + sum = vrmlaldavhaq_p(sum, vecSrcA, vecSrcA, p0); + } + + + *pResult = (q31_t) ((sum / blockSize)>>21); + +} +#else +void arm_mse_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + + q31_t inA32,inB32; /* Temporary variable to store packed input value */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + inA32 = *pSrcA++ >> 1; + inB32 = *pSrcB++ >> 1; + inA32 = __QSUB(inA32, inB32); + sum += ((q63_t) inA32 * inA32) >> 14U; + + inA32 = *pSrcA++ >> 1; + inB32 = *pSrcB++ >> 1; + inA32 = __QSUB(inA32, inB32); + sum += ((q63_t) inA32 * inA32) >> 14U; + + inA32 = *pSrcA++ >> 1; + inB32 = *pSrcB++ >> 1; + inA32 = __QSUB(inA32, inB32); + sum += ((q63_t) inA32 * inA32) >> 14U; + + inA32 = *pSrcA++ >> 1; + inB32 = *pSrcB++ >> 1; + inA32 = __QSUB(inA32, inB32); + sum += ((q63_t) inA32 * inA32) >> 14U; + + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + inA32 = *pSrcA++ >> 1; + inB32 = *pSrcB++ >> 1; + inA32 = __QSUB(inA32, inB32); + sum += ((q63_t) inA32 * inA32) >> 14U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in q31 format */ + *pResult = (q31_t) ((sum / blockSize)>>15); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MSE group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q7.c new file mode 100644 index 00000000..298e9daf --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q7.c @@ -0,0 +1,179 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mse_q7.c + * Description: Mean square error between two Q7 vectors + * + * $Date: 04 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup MSE Mean Square Error + + Calculates the mean square error between two vectors. + + */ + +/** + @addtogroup MSE + @{ + */ + +/** + @brief Mean square error between two Q7 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_mse_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q7_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrcA,vecSrcB; + q31_t sum = 0LL; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4U; + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vecSrcA = vshrq(vecSrcA,1); + vecSrcB = vshrq(vecSrcB,1); + + vecSrcA = vqsubq(vecSrcA,vecSrcB); + /* + * sum lanes + */ + sum = vmladavaq(sum, vecSrcA, vecSrcA); + + blkCnt--; + pSrcA += 16; + pSrcB += 16; + } + + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vecSrcA = vshrq(vecSrcA,1); + vecSrcB = vshrq(vecSrcB,1); + + vecSrcA = vqsubq(vecSrcA,vecSrcB); + + sum = vmladavaq_p(sum, vecSrcA, vecSrcA, p0); + } + + *pResult = (q7_t) __SSAT((q15_t) (sum / blockSize)>>5, 8); +} +#else +void arm_mse_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q7_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Temporary result storage */ + q7_t inA,inB; /* Temporary variable to store input value */ + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q7_t) __SSAT((q15_t) inA - (q15_t)inB, 8); + sum += ((q15_t) inA * inA); + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q7_t) __SSAT((q15_t) inA - (q15_t)inB, 8); + sum += ((q15_t) inA * inA); + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q7_t) __SSAT((q15_t) inA - (q15_t)inB, 8); + sum += ((q15_t) inA * inA); + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q7_t) __SSAT((q15_t) inA - (q15_t)inB, 8); + sum += ((q15_t) inA * inA); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + + inA = (q7_t) __SSAT((q15_t) inA - (q15_t)inB, 8); + sum += ((q15_t) inA * inA); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in q7 format */ + *pResult = (q7_t) __SSAT((q15_t) (sum / blockSize)>>5, 8);; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MSE group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f16.c new file mode 100644 index 00000000..fd135ebf --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f16.c @@ -0,0 +1,152 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_power_f16.c + * Description: Sum of the squares of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + + + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_power_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + f16x8_t sumVec = vdupq_n_f16(0.0f); + + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp16q(blkCnt); + + vecSrc = vldrhq_z_f16((float16_t const *) pSrc, p); + /* + * sum lanes + */ + sumVec = vfmaq_m(sumVec, vecSrc, vecSrc, p); + + blkCnt -= 8; + pSrc += 8; + } + while (blkCnt > 0); + + *pResult = vecAddAcrossF16Mve(sumVec); +} +#else + +void arm_power_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 sum = 0.0f16; /* Temporary result storage */ + _Float16 in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result to destination */ + *pResult = sum; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of power group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c new file mode 100644 index 00000000..ce12e57e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c @@ -0,0 +1,229 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_power_f32.c + * Description: Sum of the squares of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup power Power + + Calculates the sum of the squares of the elements in the input vector. + The underlying algorithm is used: + +
+      Result = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];
+  
+ + There are separate functions for floating point, Q31, Q15, and Q7 data types. + + Since the result is not divided by the length, those functions are in fact computing + something which is more an energy than a power. + + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + f32x4_t vecSrc; + f32x4_t sumVec = vdupq_n_f32(0.0f); + float32_t sum = 0.0f; + float32_t in; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + vecSrc = vldrwq_f32(pSrc); + /* + * sum lanes + */ + sumVec = vfmaq(sumVec, vecSrc, vecSrc); + + blkCnt --; + pSrc += 4; + } + sum = vecAddAcrossF32Mve(sumVec); + + /* + * tail + */ + blkCnt = blockSize & 0x3; + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + *pResult = sum; +} +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t sum = 0.0f; /* accumulator */ + float32_t in; /* Temporary variable to store input value */ + uint32_t blkCnt; /* loop counter */ + + float32x4_t sumV = vdupq_n_f32(0.0f); /* Temporary result storage */ + float32x2_t sumV2; + float32x4_t inV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* Compute Power and then store the result in a temporary variable, sum. */ + inV = vld1q_f32(pSrc); + sumV = vmlaq_f32(sumV, inV, inV); + pSrc += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = vget_lane_f32(sumV2, 0) + vget_lane_f32(sumV2, 1); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* compute power and then store the result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the result to the destination */ + *pResult = sum; +} +#else +void arm_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + float32_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result to destination */ + *pResult = sum; +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of power group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f64.c new file mode 100644 index 00000000..057e9f7c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f64.c @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_power_f64.c + * Description: Sum of the squares of the elements of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + */ +void arm_power_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float64_t sum = 0.; /* Temporary result storage */ + float64_t in; /* Temporary variable to store input value */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result to destination */ + *pResult = sum; +} + +/** + @} end of power group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c new file mode 100644 index 00000000..37a02c06 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c @@ -0,0 +1,177 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_power_q15.c + * Description: Sum of the squares of the elements of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.15 format. + Intermediate multiplication yields a 2.30 format, and this + result is added without saturation to a 64-bit accumulator in 34.30 format. + With 33 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the return result is in 34.30 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_power_q15( + const q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q63_t sum = 0LL; + q15_t in; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; + while (blkCnt > 0U) + { + vecSrc = vldrhq_s16(pSrc); + /* + * sum lanes + */ + sum = vmlaldavaq(sum, vecSrc, vecSrc); + + blkCnt --; + pSrc += 8; + } + + /* + * tail + */ + blkCnt = blockSize & 0x7; + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q31_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + *pResult = sum; +} +#else +void arm_power_q15( + const q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q15_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in32; /* Temporary variable to store packed input value */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ +#if defined (ARM_MATH_DSP) + in32 = read_q15x2_ia ((q15_t **) &pSrc); + sum = __SMLALD(in32, in32, sum); + + in32 = read_q15x2_ia ((q15_t **) &pSrc); + sum = __SMLALD(in32, in32, sum); +#else + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q31_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in 34.30 format */ + *pResult = sum; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of power group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c new file mode 100644 index 00000000..a39b3a70 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c @@ -0,0 +1,165 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_power_q31.c + * Description: Sum of the squares of the elements of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.31 format. + Intermediate multiplication yields a 2.62 format, and this + result is truncated to 2.48 format by discarding the lower 14 bits. + The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. + With 15 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the return result is in 16.48 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_power_q31( + const q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q63_t sum = 0LL; + q31_t in; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + vecSrc = vldrwq_s32(pSrc); + /* + * sum lanes + */ + sum = vrmlaldavhaq(sum, vecSrc, vecSrc); + + blkCnt --; + pSrc += 4; + } + + /* + * tail + */ + blkCnt = blockSize & 0x3; + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q63_t) in * in) >> 8; + + /* Decrement loop counter */ + blkCnt--; + } + + *pResult = asrl(sum, 6); +} +#else +void arm_power_q31( + const q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q31_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and store result in a temporary variable sum, providing 15 guard bits. */ + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store results in 16.48 format */ + *pResult = sum; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of power group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c new file mode 100644 index 00000000..0545f7c2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c @@ -0,0 +1,180 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_power_q7.c + * Description: Sum of the squares of the elements of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + The input is represented in 1.7 format. + Intermediate multiplication yields a 2.14 format, and this + result is added without saturation to an accumulator in 18.14 format. + With 17 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the return result is in 18.14 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_power_q7( + const q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q31_t sum = 0LL; + q7_t in; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4U; + while (blkCnt > 0U) + { + vecSrc = vldrbq_s8(pSrc); + /* + * sum lanes + */ + sum = vmladavaq(sum, vecSrc, vecSrc); + + blkCnt--; + pSrc += 16; + } + + /* + * tail + */ + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q15_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + *pResult = sum; +} +#else +void arm_power_q7( + const q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Temporary result storage */ + q7_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in32; /* Temporary variable to store packed input value */ + q31_t in1, in2; /* Temporary variables to store input value */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ +#if defined (ARM_MATH_DSP) + in32 = read_q7x4_ia (&pSrc); + + in1 = __SXTB16(__ROR(in32, 8)); + in2 = __SXTB16(in32); + + /* calculate power and accumulate to accumulator */ + sum = __SMLAD(in1, in1, sum); + sum = __SMLAD(in2, in2, sum); +#else + in = *pSrc++; + sum += ((q15_t) in * in); + + in = *pSrc++; + sum += ((q15_t) in * in); + + in = *pSrc++; + sum += ((q15_t) in * in); + + in = *pSrc++; + sum += ((q15_t) in * in); +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q15_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in 18.14 format */ + *pResult = sum; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of power group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f16.c new file mode 100644 index 00000000..42a00efb --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f16.c @@ -0,0 +1,147 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rms_f16.c + * Description: Root mean square value of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + +/** + @defgroup RMS Root mean square (RMS) + + Calculates the Root Mean Square of the elements in the input vector. + The underlying algorithm is used: + +
+      Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));
+  
+ + There are separate functions for floating point, Q31, and Q15 data types. + */ + +/** + @addtogroup RMS + @{ + */ + +/** + @brief Root Mean Square of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult root mean square value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_rms_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + float16_t pow = 0.0f; + + arm_power_f16(pSrc, blockSize, &pow); + + /* Compute Rms and store the result in the destination */ + arm_sqrt_f16((_Float16)pow / (_Float16) blockSize, pResult); +} +#else + +void arm_rms_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 sum = 0.0f16; /* Temporary result storage */ + _Float16 in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sum. */ + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable. */ + sum += ( in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Rms and store result in destination */ + arm_sqrt_f16((_Float16)sum / (_Float16) blockSize, pResult); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of RMS group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c new file mode 100644 index 00000000..cb45752b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rms_f32.c + * Description: Root mean square value of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup RMS Root mean square (RMS) + + Calculates the Root Mean Square of the elements in the input vector. + The underlying algorithm is used: + +
+      Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));
+  
+ + There are separate functions for floating point, Q31, and Q15 data types. + */ + +/** + @addtogroup RMS + @{ + */ + +/** + @brief Root Mean Square of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult root mean square value returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t pow = 0.0f; + + arm_power_f32(pSrc, blockSize, &pow); + + /* Compute Rms and store the result in the destination */ + arm_sqrt_f32(pow / (float32_t) blockSize, pResult); +} +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t sum = 0.0f; /* accumulator */ + float32_t in; /* Temporary variable to store input value */ + uint32_t blkCnt; /* loop counter */ + + float32x4_t sumV = vdupq_n_f32(0.0f); /* Temporary result storage */ + float32x2_t sumV2; + float32x4_t inV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* Compute Power and then store the result in a temporary variable, sum. */ + inV = vld1q_f32(pSrc); + sumV = vmlaq_f32(sumV, inV, inV); + pSrc += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = vget_lane_f32(sumV2, 0) + vget_lane_f32(sumV2, 1); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* compute power and then store the result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Compute Rms and store the result in the destination */ + arm_sqrt_f32(sum / (float32_t) blockSize, pResult); +} +#else +void arm_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + float32_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sum. */ + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable. */ + sum += ( in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Rms and store result in destination */ + arm_sqrt_f32(sum / (float32_t) blockSize, pResult); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of RMS group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c new file mode 100644 index 00000000..1df17b1e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c @@ -0,0 +1,149 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rms_q15.c + * Description: Root Mean Square of the elements of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup RMS + @{ + */ + +/** + @brief Root Mean Square of the elements of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult root mean square value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.15 format. + Intermediate multiplication yields a 2.30 format, and this + result is added without saturation to a 64-bit accumulator in 34.30 format. + With 33 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the 34.30 result is truncated to 34.15 format by discarding the lower + 15 bits, and then saturated to yield a result in 1.15 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_rms_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q63_t pow = 0.0f; + q15_t normalizedPower; + + arm_power_q15(pSrc, blockSize, &pow); + + normalizedPower=__SSAT((pow / (q63_t) blockSize) >> 15,16); + arm_sqrt_q15(normalizedPower, pResult); +} +#else +void arm_rms_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q15_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in32; /* Temporary variable to store input value */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute sum of squares and store result in a temporary variable. */ +#if defined (ARM_MATH_DSP) + in32 = read_q15x2_ia (&pSrc); + sum = __SMLALD(in32, in32, sum); + + in32 = read_q15x2_ia (&pSrc); + sum = __SMLALD(in32, in32, sum); +#else + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable. */ + sum += ((q31_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Truncating and saturating the accumulator to 1.15 format */ + /* Store result in destination */ + arm_sqrt_q15(__SSAT((sum / (q63_t)blockSize) >> 15, 16), pResult); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of RMS group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c new file mode 100644 index 00000000..ba39b7b7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c @@ -0,0 +1,141 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rms_q31.c + * Description: Root Mean Square of the elements of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup RMS + @{ + */ + +/** + @brief Root Mean Square of the elements of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult root mean square value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The input is represented in 1.31 format, and intermediate multiplication + yields a 2.62 format. + The accumulator maintains full precision of the intermediate multiplication results, + but provides only a single guard bit. + There is no saturation on intermediate additions. + If the accumulator overflows, it wraps around and distorts the result. + In order to avoid overflows completely, the input signal must be scaled down by + log2(blockSize) bits, as a total of blockSize additions are performed internally. + Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_rms_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q63_t pow = 0.0f; + q31_t normalizedPower; + arm_power_q31(pSrc, blockSize, &pow); + + normalizedPower=clip_q63_to_q31((pow / (q63_t) blockSize) >> 17); + arm_sqrt_q31(normalizedPower, pResult); + +} + +#else +void arm_rms_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + uint64_t sum = 0; /* Temporary result storage (can get never negative. changed type from q63 to uint64 */ + q31_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sum. */ + sum += ((q63_t) in * in); + + in = *pSrc++; + sum += ((q63_t) in * in); + + in = *pSrc++; + sum += ((q63_t) in * in); + + in = *pSrc++; + sum += ((q63_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable. */ + sum += ((q63_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Convert data in 2.62 to 1.31 by 31 right shifts and saturate */ + /* Compute Rms and store result in destination vector */ + arm_sqrt_q31(clip_q63_to_q31((sum / (q63_t) blockSize) >> 31), pResult); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of RMS group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f16.c new file mode 100644 index 00000000..951d1651 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f16.c @@ -0,0 +1,67 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_std_f16.c + * Description: Standard deviation of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + + + +/** + @addtogroup STD + @{ + */ + +/** + @brief Standard deviation of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult standard deviation value returned here + @return none + */ +void arm_std_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + float16_t var; + arm_var_f16(pSrc,blockSize,&var); + arm_sqrt_f16(var, pResult); +} + +/** + @} end of STD group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c new file mode 100644 index 00000000..682443d9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c @@ -0,0 +1,83 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_std_f32.c + * Description: Standard deviation of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup STD Standard deviation + + Calculates the standard deviation of the elements in the input vector. + + The float implementation is relying on arm_var_f32 which is using a two-pass algorithm + to avoid problem of numerical instabilities and cancellation errors. + + Fixed point versions are using the standard textbook algorithm since the fixed point + numerical behavior is different from the float one. + + Algorithm for fixed point versions is summarized below: + + +
+      Result = sqrt((sumOfSquares - sum2 / blockSize) / (blockSize - 1))
+
+      sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]
+      sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]
+  
+ + There are separate functions for floating point, Q31, and Q15 data types. + */ + +/** + @addtogroup STD + @{ + */ + +/** + @brief Standard deviation of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult standard deviation value returned here + @return none + */ +void arm_std_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t var; + arm_var_f32(pSrc,blockSize,&var); + arm_sqrt_f32(var, pResult); +} + +/** + @} end of STD group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f64.c new file mode 100644 index 00000000..620ec048 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f64.c @@ -0,0 +1,59 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_std_f64.c + * Description: Standard deviation of the elements of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup STD + @{ + */ + +/** + @brief Standard deviation of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult standard deviation value returned here + @return none + */ +void arm_std_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult) +{ + float64_t var; + arm_var_f64(pSrc,blockSize,&var); + *pResult = sqrt(var); +} + +/** + @} end of STD group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c new file mode 100644 index 00000000..88e273aa --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c @@ -0,0 +1,173 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_std_q15.c + * Description: Standard deviation of an array of Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup STD + @{ + */ + +/** + @brief Standard deviation of the elements of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult standard deviation value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.15 format. + Intermediate multiplication yields a 2.30 format, and this + result is added without saturation to a 64-bit accumulator in 34.30 format. + With 33 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the 34.30 result is truncated to 34.15 format by discarding the lower + 15 bits, and then saturated to yield a result in 1.15 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_std_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q15_t var=0; + + arm_var_q15(pSrc, blockSize, &var); + arm_sqrt_q15(var,pResult); +} +#else +void arm_std_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Accumulator */ + q31_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + q15_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in32; /* Temporary variable to store input value */ +#endif + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + /* Compute sum and store result in a temporary variable, sum. */ +#if defined (ARM_MATH_DSP) + in32 = read_q15x2_ia (&pSrc); + sumOfSquares = __SMLALD(in32, in32, sumOfSquares); + sum += ((in32 << 16U) >> 16U); + sum += (in32 >> 16U); + + in32 = read_q15x2_ia (&pSrc); + sumOfSquares = __SMLALD(in32, in32, sumOfSquares); + sum += ((in32 << 16U) >> 16U); + sum += (in32 >> 16U); +#else + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += (in * in); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (q31_t) (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = (q31_t) ((q63_t) sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* mean of squares minus the square of mean. */ + /* Compute standard deviation and store result in destination */ + arm_sqrt_q15(__SSAT((meanOfSquares - squareOfMean) >> 15U, 16U), pResult); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of STD group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c new file mode 100644 index 00000000..63170e79 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c @@ -0,0 +1,159 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_std_q31.c + * Description: Standard deviation of the elements of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup STD + @{ + */ + +/** + @brief Standard deviation of the elements of a Q31 vector. + @param[in] pSrc points to the input vector. + @param[in] blockSize number of samples in input vector. + @param[out] pResult standard deviation value returned here. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The input is represented in 1.31 format, which is then downshifted by 8 bits + which yields 1.23, and intermediate multiplication yields a 2.46 format. + The accumulator maintains full precision of the intermediate multiplication results, + but provides only a 16 guard bits. + There is no saturation on intermediate additions. + If the accumulator overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by + log2(blockSize)-8 bits, as a total of blockSize additions are performed internally. + After division, internal variables should be Q18.46 + Finally, the 18.46 accumulator is right shifted by 15 bits to yield a 1.31 format value. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_std_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q31_t var=0; + + arm_var_q31(pSrc, blockSize, &var); + arm_sqrt_q31(var, pResult); +} +#else +void arm_std_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Accumulator */ + q63_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + q31_t in; /* Temporary variable to store input value */ + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = ( sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* Compute standard deviation and store result in destination */ + arm_sqrt_q31((meanOfSquares - squareOfMean) >> 15U, pResult); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of STD group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f16.c new file mode 100644 index 00000000..0e3ade59 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f16.c @@ -0,0 +1,209 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_var_f16.c + * Description: Variance of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + + +/** + @addtogroup variance + @{ + */ + +/** + @brief Variance of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult variance value returned here + @return none + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + +void arm_var_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + f16x8_t sumVec = vdupq_n_f16(0.0f16); + float16_t fMean; + + if (blockSize <= 1U) { + *pResult = 0; + return; + } + + + arm_mean_f16(pSrc, blockSize, &fMean); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp16q(blkCnt); + + vecSrc = vldrhq_z_f16((float16_t const *) pSrc, p); + /* + * sum lanes + */ + vecSrc = vsubq_m(vuninitializedq_f16(), vecSrc, fMean, p); + sumVec = vfmaq_m(sumVec, vecSrc, vecSrc, p); + + blkCnt -= 8; + pSrc += 8; + } + while (blkCnt > 0); + + /* Variance */ + *pResult = (_Float16)vecAddAcrossF16Mve(sumVec) / (_Float16) (blockSize - 1.0f16); +} +#else + +void arm_var_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 sum = 0.0f; /* Temporary result storage */ + _Float16 fSum = 0.0f; + _Float16 fMean, fValue; + const float16_t * pInput = pSrc; + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + + sum += (_Float16)*pInput++; + sum += (_Float16)*pInput++; + sum += (_Float16)*pInput++; + sum += (_Float16)*pInput++; + + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + + sum += (_Float16)*pInput++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + fMean = (_Float16)sum / (_Float16) blockSize; + + pInput = pSrc; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + fValue = (_Float16)*pInput++ - (_Float16)fMean; + fSum += (_Float16)fValue * (_Float16)fValue; + + fValue = (_Float16)*pInput++ - (_Float16)fMean; + fSum += (_Float16)fValue * (_Float16)fValue; + + fValue = (_Float16)*pInput++ - (_Float16)fMean; + fSum += (_Float16)fValue * (_Float16)fValue; + + fValue = (_Float16)*pInput++ - (_Float16)fMean; + fSum += (_Float16)fValue * (_Float16)fValue; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + fValue = (_Float16)*pInput++ - (_Float16)fMean; + fSum += (_Float16)fValue * (_Float16)fValue; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Variance */ + *pResult = (_Float16)fSum / ((_Float16)blockSize - 1.0f16); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of variance group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c new file mode 100644 index 00000000..7ff344c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c @@ -0,0 +1,293 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_var_f32.c + * Description: Variance of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup variance Variance + + Calculates the variance of the elements in the input vector. + The underlying algorithm used is the direct method sometimes referred to as the two-pass method: + +
+      Result = sum(element - meanOfElements)^2) / numElement - 1
+
+      meanOfElements = ( pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] ) / blockSize
+  
+ + There are separate functions for floating point, Q31, and Q15 data types. + */ + +/** + @addtogroup variance + @{ + */ + +/** + @brief Variance of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult variance value returned here + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + f32x4_t vecSrc; + f32x4_t sumVec = vdupq_n_f32(0.0f); + float32_t fMean; + float32_t sum = 0.0f; /* accumulator */ + float32_t in; /* Temporary variable to store input value */ + + if (blockSize <= 1U) { + *pResult = 0; + return; + } + + arm_mean_f32(pSrc, blockSize, &fMean); + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + + vecSrc = vldrwq_f32(pSrc); + /* + * sum lanes + */ + vecSrc = vsubq(vecSrc, fMean); + sumVec = vfmaq(sumVec, vecSrc, vecSrc); + + blkCnt --; + pSrc += 4; + } + + sum = vecAddAcrossF32Mve(sumVec); + + /* + * tail + */ + blkCnt = blockSize & 0x3; + while (blkCnt > 0U) + { + in = *pSrc++ - fMean; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Variance */ + *pResult = sum / (float32_t) (blockSize - 1); +} +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t mean; + + float32_t sum = 0.0f; /* accumulator */ + float32_t in; /* Temporary variable to store input value */ + uint32_t blkCnt; /* loop counter */ + + float32x4_t sumV = vdupq_n_f32(0.0f); /* Temporary result storage */ + float32x2_t sumV2; + float32x4_t inV; + float32x4_t avg; + + arm_mean_f32(pSrc,blockSize,&mean); + avg = vdupq_n_f32(mean); + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* Compute Power and then store the result in a temporary variable, sum. */ + inV = vld1q_f32(pSrc); + inV = vsubq_f32(inV, avg); + sumV = vmlaq_f32(sumV, inV, inV); + pSrc += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = vget_lane_f32(sumV2, 0) + vget_lane_f32(sumV2, 1); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* compute power and then store the result in a temporary variable, sum. */ + in = *pSrc++; + in = in - mean; + sum += in * in; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Variance */ + *pResult = sum / (float32_t)(blockSize - 1.0f); + +} + +#else +void arm_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + float32_t fSum = 0.0f; + float32_t fMean, fValue; + const float32_t * pInput = pSrc; + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + + sum += *pInput++; + sum += *pInput++; + sum += *pInput++; + sum += *pInput++; + + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + + sum += *pInput++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + fMean = sum / (float32_t) blockSize; + + pInput = pSrc; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Variance */ + *pResult = fSum / (float32_t)(blockSize - 1.0f); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of variance group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f64.c new file mode 100644 index 00000000..6fd106aa --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f64.c @@ -0,0 +1,100 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_var_f64.c + * Description: Variance of the elements of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup variance + @{ + */ + +/** + @brief Variance of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult variance value returned here + @return none + */ +void arm_var_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float64_t sum = 0.; /* Temporary result storage */ + float64_t fSum = 0.; + float64_t fMean, fValue; + const float64_t * pInput = pSrc; + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + + sum += *pInput++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + fMean = sum / (float64_t) blockSize; + + pInput = pSrc; + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Variance */ + *pResult = fSum / (float64_t)(blockSize - 1.); +} + +/** + @} end of variance group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c new file mode 100644 index 00000000..f020c88b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c @@ -0,0 +1,230 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_var_q15.c + * Description: Variance of an array of Q15 type + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup variance + @{ + */ + +/** + @brief Variance of the elements of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult variance value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.15 format. + Intermediate multiplication yields a 2.30 format, and this + result is added without saturation to a 64-bit accumulator in 34.30 format. + With 33 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the 34.30 result is truncated to 34.15 format by discarding the lower + 15 bits, and then saturated to yield a result in 1.15 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_var_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q63_t sumOfSquares = 0LL; + q63_t meanOfSquares, squareOfMean; /* square of mean and mean of square */ + q63_t sum = 0LL; + q15_t in; + + if (blockSize <= 1U) { + *pResult = 0; + return; + } + + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vldrhq_s16(pSrc); + /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */ + /* Compute Sum of squares of the input samples + * and then store the result in a temporary variable, sumOfSquares. */ + + sumOfSquares = vmlaldavaq_s16(sumOfSquares, vecSrc, vecSrc); + sum = vaddvaq_s16(sum, vecSrc); + + blkCnt --; + pSrc += 8; + } + + /* Tail */ + blkCnt = blockSize & 7; + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ +#if defined (ARM_MATH_DSP) + sumOfSquares = __SMLALD(in, in, sumOfSquares); +#else + sumOfSquares += (in * in); +#endif /* #if defined (ARM_MATH_DSP) */ + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares of the input samples + * and then store the result in a temporary variable, meanOfSquares. */ + meanOfSquares = arm_div_q63_to_q31(sumOfSquares, (blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = arm_div_q63_to_q31((q63_t)sum * sum, (q31_t)(blockSize * (blockSize - 1U))); + + /* mean of the squares minus the square of the mean. */ + *pResult = (meanOfSquares - squareOfMean) >> 15; +} +#else +void arm_var_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Accumulator */ + q31_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + q15_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in32; /* Temporary variable to store input value */ +#endif + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + /* Compute sum and store result in a temporary variable, sum. */ +#if defined (ARM_MATH_DSP) + in32 = read_q15x2_ia (&pSrc); + sumOfSquares = __SMLALD(in32, in32, sumOfSquares); + sum += ((in32 << 16U) >> 16U); + sum += (in32 >> 16U); + + in32 = read_q15x2_ia (&pSrc); + sumOfSquares = __SMLALD(in32, in32, sumOfSquares); + sum += ((in32 << 16U) >> 16U); + sum += (in32 >> 16U); +#else + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ +#if defined (ARM_MATH_DSP) + sumOfSquares = __SMLALD(in, in, sumOfSquares); +#else + sumOfSquares += (in * in); +#endif /* #if defined (ARM_MATH_DSP) */ + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (q31_t) (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = (q31_t) ((q63_t) sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* mean of squares minus the square of mean. */ + *pResult = (meanOfSquares - squareOfMean) >> 15U; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of variance group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c new file mode 100644 index 00000000..45b6b66b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c @@ -0,0 +1,214 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_var_q31.c + * Description: Variance of an array of Q31 type + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup variance + @{ + */ + +/** + @brief Variance of the elements of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult variance value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The input is represented in 1.31 format, which is then downshifted by 8 bits + which yields 1.23, and intermediate multiplication yields a 2.46 format. + The accumulator maintains full precision of the intermediate multiplication results, + and as a consequence has only 16 guard bits. + There is no saturation on intermediate additions. + If the accumulator overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by + log2(blockSize)-8 bits, as a total of blockSize additions are performed internally. + After division, internal variables should be Q18.46 + Finally, the 18.46 accumulator is right shifted by 15 bits to yield a 1.31 format value. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_var_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q63_t sumOfSquares = 0LL; + q63_t meanOfSquares, squareOfMean; /* square of mean and mean of square */ + q63_t sum = 0LL; + q31_t in; + + if (blockSize <= 1U) { + *pResult = 0; + return; + } + + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + vecSrc = vldrwq_s32(pSrc); + /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */ + /* Compute Sum of squares of the input samples + * and then store the result in a temporary variable, sumOfSquares. */ + + /* downscale */ + vecSrc = vshrq(vecSrc, 8); + sumOfSquares = vmlaldavaq(sumOfSquares, vecSrc, vecSrc); + sum = vaddlvaq(sum, vecSrc); + + blkCnt --; + pSrc += 4; + } + + + /* + * tail + */ + blkCnt = blockSize & 0x3; + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares of the input samples + * and then store the result in a temporary variable, meanOfSquares. */ + meanOfSquares = sumOfSquares / (q63_t) (blockSize - 1U); + + /* Compute square of mean */ + squareOfMean = sum * sum / (q63_t) (blockSize * (blockSize - 1U)); + + /* Compute standard deviation and then store the result to the destination */ + *pResult = asrl(meanOfSquares - squareOfMean, 15U); +} +#else +void arm_var_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q63_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + q31_t in; /* Temporary variable to store input value */ + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = ( sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* Compute variance and store result in destination */ + *pResult = (meanOfSquares - squareOfMean) >> 15U; +} +#endif +/** + @} end of variance group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/CMakeLists.txt new file mode 100644 index 00000000..41b13f27 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/CMakeLists.txt @@ -0,0 +1,28 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPSupport) + +include(configLib) +include(configDsp) + +file(GLOB SRC "./*_*.c") + +add_library(CMSISDSPSupport STATIC ${SRC}) + +configLib(CMSISDSPSupport ${ROOT}) +configDsp(CMSISDSPSupport ${ROOT}) + +### Includes +target_include_directories(CMSISDSPSupport PUBLIC "${DSP}/Include") + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPSupport PRIVATE arm_copy_f16.c) +target_sources(CMSISDSPSupport PRIVATE arm_fill_f16.c) +target_sources(CMSISDSPSupport PRIVATE arm_f16_to_q15.c) +target_sources(CMSISDSPSupport PRIVATE arm_q15_to_f16.c) +target_sources(CMSISDSPSupport PRIVATE arm_float_to_f16.c) +target_sources(CMSISDSPSupport PRIVATE arm_f16_to_float.c) +target_sources(CMSISDSPSupport PRIVATE arm_weighted_sum_f16.c) +target_sources(CMSISDSPSupport PRIVATE arm_barycenter_f16.c) +endif() + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c new file mode 100644 index 00000000..ca8b1b6c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: SupportFunctions.c + * Description: Combination of all support function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_barycenter_f32.c" +#include "arm_bitonic_sort_f32.c" +#include "arm_bubble_sort_f32.c" +#include "arm_copy_f32.c" +#include "arm_copy_f64.c" +#include "arm_copy_q15.c" +#include "arm_copy_q31.c" +#include "arm_copy_q7.c" +#include "arm_fill_f32.c" +#include "arm_fill_f64.c" +#include "arm_fill_q15.c" +#include "arm_fill_q31.c" +#include "arm_fill_q7.c" +#include "arm_heap_sort_f32.c" +#include "arm_insertion_sort_f32.c" +#include "arm_merge_sort_f32.c" +#include "arm_merge_sort_init_f32.c" +#include "arm_quick_sort_f32.c" +#include "arm_selection_sort_f32.c" +#include "arm_sort_f32.c" +#include "arm_sort_init_f32.c" +#include "arm_weighted_sum_f32.c" + +#include "arm_float_to_q15.c" +#include "arm_float_to_q31.c" +#include "arm_float_to_q7.c" +#include "arm_q15_to_float.c" +#include "arm_q15_to_q31.c" +#include "arm_q15_to_q7.c" +#include "arm_q31_to_float.c" +#include "arm_q31_to_q15.c" +#include "arm_q31_to_q7.c" +#include "arm_q7_to_float.c" +#include "arm_q7_to_q15.c" +#include "arm_q7_to_q31.c" diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/SupportFunctionsF16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/SupportFunctionsF16.c new file mode 100644 index 00000000..0e39d8d1 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/SupportFunctionsF16.c @@ -0,0 +1,36 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: SupportFunctions.c + * Description: Combination of all support function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_copy_f16.c" +#include "arm_fill_f16.c" +#include "arm_f16_to_q15.c" +#include "arm_f16_to_float.c" +#include "arm_q15_to_f16.c" +#include "arm_float_to_f16.c" +#include "arm_weighted_sum_f16.c" +#include "arm_barycenter_f16.c" diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f16.c new file mode 100644 index 00000000..6dfe55c9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f16.c @@ -0,0 +1,274 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_barycenter_f16.c + * Description: Barycenter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupSupport + */ + +/** + @defgroup barycenter Barycenter + + Barycenter of weighted vectors + */ + +/** + @addtogroup barycenter + @{ + */ + + +/** + * @brief Barycenter + * + * + * @param[in] *in List of vectors + * @param[in] *weights Weights of the vectors + * @param[out] *out Barycenter + * @param[in] nbVectors Number of vectors + * @param[in] vecDim Dimension of space (vector dimension) + * @return None + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_barycenter_f16(const float16_t *in, + const float16_t *weights, + float16_t *out, + uint32_t nbVectors, + uint32_t vecDim) +{ + const float16_t *pIn, *pW; + const float16_t *pIn1, *pIn2, *pIn3, *pIn4; + float16_t *pOut; + uint32_t blkCntVector, blkCntSample; + float16_t accum, w; + + blkCntVector = nbVectors; + blkCntSample = vecDim; + + accum = 0.0f; + + pW = weights; + pIn = in; + + + arm_fill_f16(0.0f, out, vecDim); + + + /* Sum */ + pIn1 = pIn; + pIn2 = pIn1 + vecDim; + pIn3 = pIn2 + vecDim; + pIn4 = pIn3 + vecDim; + + blkCntVector = nbVectors >> 2; + while (blkCntVector > 0) + { + f16x8_t outV, inV1, inV2, inV3, inV4; + float16_t w1, w2, w3, w4; + + pOut = out; + w1 = *pW++; + w2 = *pW++; + w3 = *pW++; + w4 = *pW++; + accum += (_Float16)w1 + (_Float16)w2 + (_Float16)w3 + (_Float16)w4; + + blkCntSample = vecDim >> 3; + while (blkCntSample > 0) { + outV = vld1q((const float16_t *) pOut); + inV1 = vld1q(pIn1); + inV2 = vld1q(pIn2); + inV3 = vld1q(pIn3); + inV4 = vld1q(pIn4); + outV = vfmaq(outV, inV1, w1); + outV = vfmaq(outV, inV2, w2); + outV = vfmaq(outV, inV3, w3); + outV = vfmaq(outV, inV4, w4); + vst1q(pOut, outV); + + pOut += 8; + pIn1 += 8; + pIn2 += 8; + pIn3 += 8; + pIn4 += 8; + + blkCntSample--; + } + + blkCntSample = vecDim & 7; + while (blkCntSample > 0) { + *pOut = (_Float16)*pOut + (_Float16)*pIn1++ * (_Float16)w1; + *pOut = (_Float16)*pOut + (_Float16)*pIn2++ * (_Float16)w2; + *pOut = (_Float16)*pOut + (_Float16)*pIn3++ * (_Float16)w3; + *pOut = (_Float16)*pOut + (_Float16)*pIn4++ * (_Float16)w4; + pOut++; + blkCntSample--; + } + + pIn1 += 3 * vecDim; + pIn2 += 3 * vecDim; + pIn3 += 3 * vecDim; + pIn4 += 3 * vecDim; + + blkCntVector--; + } + + pIn = pIn1; + + blkCntVector = nbVectors & 3; + while (blkCntVector > 0) + { + f16x8_t inV, outV; + + pOut = out; + w = *pW++; + accum += (_Float16)w; + + blkCntSample = vecDim >> 3; + while (blkCntSample > 0) + { + outV = vld1q_f16(pOut); + inV = vld1q_f16(pIn); + outV = vfmaq(outV, inV, w); + vst1q_f16(pOut, outV); + pOut += 8; + pIn += 8; + + blkCntSample--; + } + + blkCntSample = vecDim & 7; + while (blkCntSample > 0) + { + *pOut = (_Float16)*pOut + (_Float16)*pIn++ * (_Float16)w; + pOut++; + blkCntSample--; + } + + blkCntVector--; + } + + /* Normalize */ + pOut = out; + accum = 1.0f16 / (_Float16)accum; + + blkCntSample = vecDim >> 3; + while (blkCntSample > 0) + { + f16x8_t tmp; + + tmp = vld1q((const float16_t *) pOut); + tmp = vmulq(tmp, accum); + vst1q(pOut, tmp); + pOut += 8; + blkCntSample--; + } + + blkCntSample = vecDim & 7; + while (blkCntSample > 0) + { + *pOut = (_Float16)*pOut * (_Float16)accum; + pOut++; + blkCntSample--; + } +} +#else +void arm_barycenter_f16(const float16_t *in, const float16_t *weights, float16_t *out, uint32_t nbVectors,uint32_t vecDim) +{ + + const float16_t *pIn,*pW; + float16_t *pOut; + uint32_t blkCntVector,blkCntSample; + float16_t accum, w; + + blkCntVector = nbVectors; + blkCntSample = vecDim; + + accum = 0.0f16; + + pW = weights; + pIn = in; + + /* Set counters to 0 */ + blkCntSample = vecDim; + pOut = out; + + while(blkCntSample > 0) + { + *pOut = 0.0f16; + pOut++; + blkCntSample--; + } + + /* Sum */ + while(blkCntVector > 0) + { + pOut = out; + w = *pW++; + accum += (_Float16)w; + + blkCntSample = vecDim; + while(blkCntSample > 0) + { + *pOut = (_Float16)*pOut + (_Float16)*pIn++ * (_Float16)w; + pOut++; + blkCntSample--; + } + + blkCntVector--; + } + + /* Normalize */ + blkCntSample = vecDim; + pOut = out; + + while(blkCntSample > 0) + { + *pOut = (_Float16)*pOut / (_Float16)accum; + pOut++; + blkCntSample--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of barycenter group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c new file mode 100644 index 00000000..817bb588 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c @@ -0,0 +1,414 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_barycenter_f32.c + * Description: Barycenter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" +#include +#include + + +/** + @ingroup barycenter + */ + + +/** + * @brief Barycenter + * + * + * @param[in] *in List of vectors + * @param[in] *weights Weights of the vectors + * @param[out] *out Barycenter + * @param[in] nbVectors Number of vectors + * @param[in] vecDim Dimension of space (vector dimension) + * @return None + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_barycenter_f32(const float32_t *in, + const float32_t *weights, + float32_t *out, + uint32_t nbVectors, + uint32_t vecDim) +{ + const float32_t *pIn, *pW; + const float32_t *pIn1, *pIn2, *pIn3, *pIn4; + float32_t *pOut; + uint32_t blkCntVector, blkCntSample; + float32_t accum, w; + + blkCntVector = nbVectors; + blkCntSample = vecDim; + + accum = 0.0f; + + pW = weights; + pIn = in; + + + arm_fill_f32(0.0f, out, vecDim); + + + /* Sum */ + pIn1 = pIn; + pIn2 = pIn1 + vecDim; + pIn3 = pIn2 + vecDim; + pIn4 = pIn3 + vecDim; + + blkCntVector = nbVectors >> 2; + while (blkCntVector > 0) + { + f32x4_t outV, inV1, inV2, inV3, inV4; + float32_t w1, w2, w3, w4; + + pOut = out; + w1 = *pW++; + w2 = *pW++; + w3 = *pW++; + w4 = *pW++; + accum += w1 + w2 + w3 + w4; + + blkCntSample = vecDim >> 2; + while (blkCntSample > 0) { + outV = vld1q((const float32_t *) pOut); + inV1 = vld1q(pIn1); + inV2 = vld1q(pIn2); + inV3 = vld1q(pIn3); + inV4 = vld1q(pIn4); + outV = vfmaq(outV, inV1, w1); + outV = vfmaq(outV, inV2, w2); + outV = vfmaq(outV, inV3, w3); + outV = vfmaq(outV, inV4, w4); + vst1q(pOut, outV); + + pOut += 4; + pIn1 += 4; + pIn2 += 4; + pIn3 += 4; + pIn4 += 4; + + blkCntSample--; + } + + blkCntSample = vecDim & 3; + while (blkCntSample > 0) { + *pOut = *pOut + *pIn1++ * w1; + *pOut = *pOut + *pIn2++ * w2; + *pOut = *pOut + *pIn3++ * w3; + *pOut = *pOut + *pIn4++ * w4; + pOut++; + blkCntSample--; + } + + pIn1 += 3 * vecDim; + pIn2 += 3 * vecDim; + pIn3 += 3 * vecDim; + pIn4 += 3 * vecDim; + + blkCntVector--; + } + + pIn = pIn1; + + blkCntVector = nbVectors & 3; + while (blkCntVector > 0) + { + f32x4_t inV, outV; + + pOut = out; + w = *pW++; + accum += w; + + blkCntSample = vecDim >> 2; + while (blkCntSample > 0) + { + outV = vld1q_f32(pOut); + inV = vld1q_f32(pIn); + outV = vfmaq(outV, inV, w); + vst1q_f32(pOut, outV); + pOut += 4; + pIn += 4; + + blkCntSample--; + } + + blkCntSample = vecDim & 3; + while (blkCntSample > 0) + { + *pOut = *pOut + *pIn++ * w; + pOut++; + blkCntSample--; + } + + blkCntVector--; + } + + /* Normalize */ + pOut = out; + accum = 1.0f / accum; + + blkCntSample = vecDim >> 2; + while (blkCntSample > 0) + { + f32x4_t tmp; + + tmp = vld1q((const float32_t *) pOut); + tmp = vmulq(tmp, accum); + vst1q(pOut, tmp); + pOut += 4; + blkCntSample--; + } + + blkCntSample = vecDim & 3; + while (blkCntSample > 0) + { + *pOut = *pOut * accum; + pOut++; + blkCntSample--; + } +} +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" +void arm_barycenter_f32(const float32_t *in, const float32_t *weights, float32_t *out, uint32_t nbVectors,uint32_t vecDim) +{ + + const float32_t *pIn,*pW, *pIn1, *pIn2, *pIn3, *pIn4; + float32_t *pOut; + uint32_t blkCntVector,blkCntSample; + float32_t accum, w,w1,w2,w3,w4; + + float32x4_t tmp, inV,outV, inV1, inV2, inV3, inV4; + + blkCntVector = nbVectors; + blkCntSample = vecDim; + + accum = 0.0f; + + pW = weights; + pIn = in; + + /* Set counters to 0 */ + tmp = vdupq_n_f32(0.0f); + pOut = out; + + blkCntSample = vecDim >> 2; + while(blkCntSample > 0) + { + vst1q_f32(pOut, tmp); + pOut += 4; + blkCntSample--; + } + + blkCntSample = vecDim & 3; + while(blkCntSample > 0) + { + *pOut = 0.0f; + pOut++; + blkCntSample--; + } + + /* Sum */ + + pIn1 = pIn; + pIn2 = pIn1 + vecDim; + pIn3 = pIn2 + vecDim; + pIn4 = pIn3 + vecDim; + + blkCntVector = nbVectors >> 2; + while(blkCntVector > 0) + { + pOut = out; + w1 = *pW++; + w2 = *pW++; + w3 = *pW++; + w4 = *pW++; + accum += w1 + w2 + w3 + w4; + + blkCntSample = vecDim >> 2; + while(blkCntSample > 0) + { + outV = vld1q_f32(pOut); + inV1 = vld1q_f32(pIn1); + inV2 = vld1q_f32(pIn2); + inV3 = vld1q_f32(pIn3); + inV4 = vld1q_f32(pIn4); + outV = vmlaq_n_f32(outV,inV1,w1); + outV = vmlaq_n_f32(outV,inV2,w2); + outV = vmlaq_n_f32(outV,inV3,w3); + outV = vmlaq_n_f32(outV,inV4,w4); + vst1q_f32(pOut, outV); + pOut += 4; + pIn1 += 4; + pIn2 += 4; + pIn3 += 4; + pIn4 += 4; + + blkCntSample--; + } + + blkCntSample = vecDim & 3; + while(blkCntSample > 0) + { + *pOut = *pOut + *pIn1++ * w1; + *pOut = *pOut + *pIn2++ * w2; + *pOut = *pOut + *pIn3++ * w3; + *pOut = *pOut + *pIn4++ * w4; + pOut++; + blkCntSample--; + } + + pIn1 += 3*vecDim; + pIn2 += 3*vecDim; + pIn3 += 3*vecDim; + pIn4 += 3*vecDim; + + blkCntVector--; + } + + pIn = pIn1; + + blkCntVector = nbVectors & 3; + while(blkCntVector > 0) + { + pOut = out; + w = *pW++; + accum += w; + + blkCntSample = vecDim >> 2; + while(blkCntSample > 0) + { + outV = vld1q_f32(pOut); + inV = vld1q_f32(pIn); + outV = vmlaq_n_f32(outV,inV,w); + vst1q_f32(pOut, outV); + pOut += 4; + pIn += 4; + + blkCntSample--; + } + + blkCntSample = vecDim & 3; + while(blkCntSample > 0) + { + *pOut = *pOut + *pIn++ * w; + pOut++; + blkCntSample--; + } + + blkCntVector--; + } + + /* Normalize */ + pOut = out; + accum = 1.0f / accum; + + blkCntSample = vecDim >> 2; + while(blkCntSample > 0) + { + tmp = vld1q_f32(pOut); + tmp = vmulq_n_f32(tmp,accum); + vst1q_f32(pOut, tmp); + pOut += 4; + blkCntSample--; + } + + blkCntSample = vecDim & 3; + while(blkCntSample > 0) + { + *pOut = *pOut * accum; + pOut++; + blkCntSample--; + } + +} +#else +void arm_barycenter_f32(const float32_t *in, const float32_t *weights, float32_t *out, uint32_t nbVectors,uint32_t vecDim) +{ + + const float32_t *pIn,*pW; + float32_t *pOut; + uint32_t blkCntVector,blkCntSample; + float32_t accum, w; + + blkCntVector = nbVectors; + blkCntSample = vecDim; + + accum = 0.0f; + + pW = weights; + pIn = in; + + /* Set counters to 0 */ + blkCntSample = vecDim; + pOut = out; + + while(blkCntSample > 0) + { + *pOut = 0.0f; + pOut++; + blkCntSample--; + } + + /* Sum */ + while(blkCntVector > 0) + { + pOut = out; + w = *pW++; + accum += w; + + blkCntSample = vecDim; + while(blkCntSample > 0) + { + *pOut = *pOut + *pIn++ * w; + pOut++; + blkCntSample--; + } + + blkCntVector--; + } + + /* Normalize */ + blkCntSample = vecDim; + pOut = out; + + while(blkCntSample > 0) + { + *pOut = *pOut / accum; + pOut++; + blkCntSample--; + } + +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of barycenter group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c new file mode 100644 index 00000000..e9612b1b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c @@ -0,0 +1,1039 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_bitonic_sort_f32.c + * Description: Floating point bitonic sort + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" +#include "arm_sorting.h" + + +#if !defined(ARM_MATH_NEON) + +static void arm_bitonic_sort_core_f32(float32_t *pSrc, uint32_t n, uint8_t dir) +{ + uint32_t step; + uint32_t k, j; + float32_t *leftPtr, *rightPtr; + float32_t temp; + + step = n>>1; + leftPtr = pSrc; + rightPtr = pSrc+n-1; + + for(k=0; k *rightPtr)) + { + // Swap + temp=*leftPtr; + *leftPtr=*rightPtr; + *rightPtr=temp; + } + + leftPtr++; // Move right + rightPtr--; // Move left + } + + // Merge + for(step=(n>>2); step>0; step/=2) + { + for(j=0; j *rightPtr) + { + // Swap + temp=*leftPtr; + *leftPtr=*rightPtr; + *rightPtr=temp; + } + + leftPtr++; + rightPtr++; + } + } + } +} +#endif + +#if defined(ARM_MATH_NEON) + + +static float32x4x2_t arm_bitonic_resort_8_f32(float32x4_t a, float32x4_t b, uint8_t dir) +{ + /* Start with two vectors: + * +---+---+---+---+ + * | a | b | c | d | + * +---+---+---+---+ + * +---+---+---+---+ + * | e | f | g | h | + * +---+---+---+---+ + * All the elements of the first are guaranteed to be less than or equal to + * all of the elements in the second, and both vectors are bitonic. + * We need to perform these operations to completely sort both lists: + * vminmax([abcd],[efgh]) + * vminmax([acbd],[egfh]) + */ + vtrn128_64q(a, b); + /* +---+---+---+---+ + * | a | b | e | f | + * +---+---+---+---+ + * +---+---+---+---+ + * | c | d | g | h | + * +---+---+---+---+ + */ + if(dir) + vminmaxq(a, b); + else + vminmaxq(b, a); + + vtrn128_32q(a, b); + /* +---+---+---+---+ + * | a | c | e | g | + * +---+---+---+---+ + * +---+---+---+---+ + * | b | d | f | h | + * +---+---+---+---+ + */ + if(dir) + vminmaxq(a, b); + else + vminmaxq(b, a); + + return vzipq_f32(a, b); +} + + +static float32x4x2_t arm_bitonic_merge_8_f32(float32x4_t a, float32x4_t b, uint8_t dir) +{ + /* a and b are guaranteed to be bitonic */ + // Reverse the element of the second vector + b = vrev128q_f32(b); + + // Compare the two vectors + if(dir) + vminmaxq(a, b); + else + vminmaxq(b, a); + + // Merge the two vectors + float32x4x2_t ab = arm_bitonic_resort_8_f32(a, b, dir); + + return ab; +} + +static void arm_bitonic_resort_16_f32(float32_t * pOut, float32x4x2_t a, float32x4x2_t b, uint8_t dir) +{ + /* Start with two vectors: + * +---+---+---+---+---+---+---+---+ + * | a | b | c | d | e | f | g | h | + * +---+---+---+---+---+---+---+---+ + * +---+---+---+---+---+---+---+---+ + * | i | j | k | l | m | n | o | p | + * +---+---+---+---+---+---+---+---+ + * All the elements of the first are guaranteed to be less than or equal to + * all of the elements in the second, and both vectors are bitonic. + * We need to perform these operations to completely sort both lists: + * vminmax([abcd],[efgh]) vminmax([ijkl],[mnop]) + * vminmax([abef],[cdgh]) vminmax([ijmn],[klop]) + * vminmax([acef],[bdfh]) vminmax([ikmo],[jlmp]) + */ + + vtrn256_128q(a, b); + /* +---+---+---+---+---+---+---+---+ + * | a | b | c | d | i | j | k | l | + * +---+---+---+---+---+---+---+---+ + * +---+---+---+---+---+---+---+---+ + * | e | f | g | h | m | n | o | p | + * +---+---+---+---+---+---+---+---+ + */ + if(dir) + vminmax256q(a, b); + else + vminmax256q(b, a); + + vtrn256_64q(a, b); + + /* +---+---+---+---+---+---+---+---+ + * | a | b | e | f | i | j | m | n | + * +---+---+---+---+---+---+---+---+ + * +---+---+---+---+---+---+---+---+ + * | c | d | g | h | k | l | o | p | + * +---+---+---+---+---+---+---+---+ + */ + if(dir) + vminmax256q(a, b); + else + vminmax256q(b, a); + + vtrn256_32q(a, b); + /* We now have: + * +---+---+---+---+---+---+---+---+ + * | a | c | e | g | i | k | m | o | + * +---+---+---+---+---+---+---+---+ + * +---+---+---+---+---+---+---+---+ + * | b | d | f | h | j | l | n | p | + * +---+---+---+---+---+---+---+---+ + */ + if(dir) + vminmax256q(a, b); + else + vminmax256q(b, a); + + float32x4x2_t out1 = vzipq_f32(a.val[0], b.val[0]); + float32x4x2_t out2 = vzipq_f32(a.val[1], b.val[1]); + + vst1q_f32(pOut, out1.val[0]); + vst1q_f32(pOut+4, out1.val[1]); + vst1q_f32(pOut+8, out2.val[0]); + vst1q_f32(pOut+12, out2.val[1]); +} + +static void arm_bitonic_merge_16_f32(float32_t * pOut, float32x4x2_t a, float32x4x2_t b, uint8_t dir) +{ + // Merge two preordered float32x4x2_t + vrev256q_f32(b); + + if(dir) + vminmax256q(a, b); + else + vminmax256q(b, a); + + arm_bitonic_resort_16_f32(pOut, a, b, dir); +} + +static void arm_bitonic_sort_16_f32(float32_t *pSrc, float32_t *pDst, uint8_t dir) +{ + float32x4_t a; + float32x4_t b; + float32x4_t c; + float32x4_t d; + + // Load 16 samples + a = vld1q_f32(pSrc); + b = vld1q_f32(pSrc+4); + c = vld1q_f32(pSrc+8); + d = vld1q_f32(pSrc+12); + + // Bitonic sorting network for 4 samples x 4 times + if(dir) + { + vminmaxq(a, b); + vminmaxq(c, d); + + vminmaxq(a, d); + vminmaxq(b, c); + + vminmaxq(a, b); + vminmaxq(c, d); + } + else + { + vminmaxq(b, a); + vminmaxq(d, c); + + vminmaxq(d, a); + vminmaxq(c, b); + + vminmaxq(b, a); + vminmaxq(d, c); + } + + float32x4x2_t ab = vtrnq_f32 (a, b); + float32x4x2_t cd = vtrnq_f32 (c, d); + + // Transpose 4 ordered arrays of 4 samples + a = vcombine_f32(vget_low_f32(ab.val[0]), vget_low_f32(cd.val[0])); + b = vcombine_f32(vget_low_f32(ab.val[1]), vget_low_f32(cd.val[1])); + c = vcombine_f32(vget_high_f32(ab.val[0]), vget_high_f32(cd.val[0])); + d = vcombine_f32(vget_high_f32(ab.val[1]), vget_high_f32(cd.val[1])); + + // Merge pairs of arrays of 4 samples + ab = arm_bitonic_merge_8_f32(a, b, dir); + cd = arm_bitonic_merge_8_f32(c, d, dir); + + // Merge arrays of 8 samples + arm_bitonic_merge_16_f32(pDst, ab, cd, dir); +} + + + + + +static void arm_bitonic_merge_32_f32(float32_t * pSrc, float32x4x2_t ab1, float32x4x2_t ab2, float32x4x2_t cd1, float32x4x2_t cd2, uint8_t dir) +{ + //Compare + if(dir) + { + vminmax256q(ab1, cd1); + vminmax256q(ab2, cd2); + } + else + { + vminmax256q(cd1, ab1); + vminmax256q(cd2, ab2); + } + //Transpose 256 + float32x4_t temp; + + temp = ab2.val[0]; + ab2.val[0] = cd1.val[0]; + cd1.val[0] = temp; + temp = ab2.val[1]; + ab2.val[1] = cd1.val[1]; + cd1.val[1] = temp; + + //Compare + if(dir) + { + vminmax256q(ab1, cd1); + vminmax256q(ab2, cd2); + } + else + { + vminmax256q(cd1, ab1); + vminmax256q(cd2, ab2); + } + + //Transpose 128 + arm_bitonic_merge_16_f32(pSrc+0, ab1, cd1, dir); + arm_bitonic_merge_16_f32(pSrc+16, ab2, cd2, dir); +} + +static void arm_bitonic_merge_64_f32(float32_t * pSrc, uint8_t dir) +{ + float32x4x2_t ab1, ab2, ab3, ab4; + float32x4x2_t cd1, cd2, cd3, cd4; + + //Load and reverse second array + ab1.val[0] = vld1q_f32(pSrc+0 ); + ab1.val[1] = vld1q_f32(pSrc+4 ); + ab2.val[0] = vld1q_f32(pSrc+8 ); + ab2.val[1] = vld1q_f32(pSrc+12); + ab3.val[0] = vld1q_f32(pSrc+16); + ab3.val[1] = vld1q_f32(pSrc+20); + ab4.val[0] = vld1q_f32(pSrc+24); + ab4.val[1] = vld1q_f32(pSrc+28); + + vldrev128q_f32(cd4.val[1], pSrc+32); + vldrev128q_f32(cd4.val[0], pSrc+36); + vldrev128q_f32(cd3.val[1], pSrc+40); + vldrev128q_f32(cd3.val[0], pSrc+44); + vldrev128q_f32(cd2.val[1], pSrc+48); + vldrev128q_f32(cd2.val[0], pSrc+52); + vldrev128q_f32(cd1.val[1], pSrc+56); + vldrev128q_f32(cd1.val[0], pSrc+60); + + //Compare + if(dir) + { + vminmax256q(ab1, cd1); + vminmax256q(ab2, cd2); + vminmax256q(ab3, cd3); + vminmax256q(ab4, cd4); + } + else + { + vminmax256q(cd1, ab1); + vminmax256q(cd2, ab2); + vminmax256q(cd3, ab3); + vminmax256q(cd4, ab4); + } + + //Transpose 512 + float32x4_t temp; + + temp = ab3.val[0]; + ab3.val[0] = cd1.val[0]; + cd1.val[0] = temp; + temp = ab3.val[1]; + ab3.val[1] = cd1.val[1]; + cd1.val[1] = temp; + temp = ab4.val[0]; + ab4.val[0] = cd2.val[0]; + cd2.val[0] = temp; + temp = ab4.val[1]; + ab4.val[1] = cd2.val[1]; + cd2.val[1] = temp; + + //Compare + if(dir) + { + vminmax256q(ab1, cd1); + vminmax256q(ab2, cd2); + vminmax256q(ab3, cd3); + vminmax256q(ab4, cd4); + } + else + { + vminmax256q(cd1, ab1); + vminmax256q(cd2, ab2); + vminmax256q(cd3, ab3); + vminmax256q(cd4, ab4); + } + + //Transpose 256 + arm_bitonic_merge_32_f32(pSrc+0, ab1, ab2, cd1, cd2, dir); + arm_bitonic_merge_32_f32(pSrc+32, ab3, ab4, cd3, cd4, dir); +} + +static void arm_bitonic_merge_128_f32(float32_t * pSrc, uint8_t dir) +{ + float32x4x2_t ab1, ab2, ab3, ab4, ab5, ab6, ab7, ab8; + float32x4x2_t cd1, cd2, cd3, cd4, cd5, cd6, cd7, cd8; + + //Load and reverse second array + ab1.val[0] = vld1q_f32(pSrc+0 ); + ab1.val[1] = vld1q_f32(pSrc+4 ); + ab2.val[0] = vld1q_f32(pSrc+8 ); + ab2.val[1] = vld1q_f32(pSrc+12); + ab3.val[0] = vld1q_f32(pSrc+16); + ab3.val[1] = vld1q_f32(pSrc+20); + ab4.val[0] = vld1q_f32(pSrc+24); + ab4.val[1] = vld1q_f32(pSrc+28); + ab5.val[0] = vld1q_f32(pSrc+32); + ab5.val[1] = vld1q_f32(pSrc+36); + ab6.val[0] = vld1q_f32(pSrc+40); + ab6.val[1] = vld1q_f32(pSrc+44); + ab7.val[0] = vld1q_f32(pSrc+48); + ab7.val[1] = vld1q_f32(pSrc+52); + ab8.val[0] = vld1q_f32(pSrc+56); + ab8.val[1] = vld1q_f32(pSrc+60); + + vldrev128q_f32(cd8.val[1], pSrc+64); + vldrev128q_f32(cd8.val[0], pSrc+68); + vldrev128q_f32(cd7.val[1], pSrc+72); + vldrev128q_f32(cd7.val[0], pSrc+76); + vldrev128q_f32(cd6.val[1], pSrc+80); + vldrev128q_f32(cd6.val[0], pSrc+84); + vldrev128q_f32(cd5.val[1], pSrc+88); + vldrev128q_f32(cd5.val[0], pSrc+92); + vldrev128q_f32(cd4.val[1], pSrc+96); + vldrev128q_f32(cd4.val[0], pSrc+100); + vldrev128q_f32(cd3.val[1], pSrc+104); + vldrev128q_f32(cd3.val[0], pSrc+108); + vldrev128q_f32(cd2.val[1], pSrc+112); + vldrev128q_f32(cd2.val[0], pSrc+116); + vldrev128q_f32(cd1.val[1], pSrc+120); + vldrev128q_f32(cd1.val[0], pSrc+124); + + //Compare + if(dir) + { + vminmax256q(ab1, cd1); + vminmax256q(ab2, cd2); + vminmax256q(ab3, cd3); + vminmax256q(ab4, cd4); + vminmax256q(ab5, cd5); + vminmax256q(ab6, cd6); + vminmax256q(ab7, cd7); + vminmax256q(ab8, cd8); + } + else + { + vminmax256q(cd1, ab1); + vminmax256q(cd2, ab2); + vminmax256q(cd3, ab3); + vminmax256q(cd4, ab4); + vminmax256q(cd5, ab5); + vminmax256q(cd6, ab6); + vminmax256q(cd7, ab7); + vminmax256q(cd8, ab8); + } + + //Transpose + float32x4_t temp; + + temp = ab5.val[0]; + ab5.val[0] = cd1.val[0]; + cd1.val[0] = temp; + temp = ab5.val[1]; + ab5.val[1] = cd1.val[1]; + cd1.val[1] = temp; + temp = ab6.val[0]; + ab6.val[0] = cd2.val[0]; + cd2.val[0] = temp; + temp = ab6.val[1]; + ab6.val[1] = cd2.val[1]; + cd2.val[1] = temp; + temp = ab7.val[0]; + ab7.val[0] = cd3.val[0]; + cd3.val[0] = temp; + temp = ab7.val[1]; + ab7.val[1] = cd3.val[1]; + cd3.val[1] = temp; + temp = ab8.val[0]; + ab8.val[0] = cd4.val[0]; + cd4.val[0] = temp; + temp = ab8.val[1]; + ab8.val[1] = cd4.val[1]; + cd4.val[1] = temp; + + //Compare + if(dir) + { + vminmax256q(ab1, cd1); + vminmax256q(ab2, cd2); + vminmax256q(ab3, cd3); + vminmax256q(ab4, cd4); + vminmax256q(ab5, cd5); + vminmax256q(ab6, cd6); + vminmax256q(ab7, cd7); + vminmax256q(ab8, cd8); + } + else + { + vminmax256q(cd1, ab1); + vminmax256q(cd2, ab2); + vminmax256q(cd3, ab3); + vminmax256q(cd4, ab4); + vminmax256q(cd5, ab5); + vminmax256q(cd6, ab6); + vminmax256q(cd7, ab7); + vminmax256q(cd8, ab8); + } + + vst1q_f32(pSrc, ab1.val[0]); + vst1q_f32(pSrc+4, ab1.val[1]); + vst1q_f32(pSrc+8, ab2.val[0]); + vst1q_f32(pSrc+12, ab2.val[1]); + vst1q_f32(pSrc+16, ab3.val[0]); + vst1q_f32(pSrc+20, ab3.val[1]); + vst1q_f32(pSrc+24, ab4.val[0]); + vst1q_f32(pSrc+28, ab4.val[1]); + vst1q_f32(pSrc+32, cd1.val[0]); + vst1q_f32(pSrc+36, cd1.val[1]); + vst1q_f32(pSrc+40, cd2.val[0]); + vst1q_f32(pSrc+44, cd2.val[1]); + vst1q_f32(pSrc+48, cd3.val[0]); + vst1q_f32(pSrc+52, cd3.val[1]); + vst1q_f32(pSrc+56, cd4.val[0]); + vst1q_f32(pSrc+60, cd4.val[1]); + vst1q_f32(pSrc+64, ab5.val[0]); + vst1q_f32(pSrc+68, ab5.val[1]); + vst1q_f32(pSrc+72, ab6.val[0]); + vst1q_f32(pSrc+76, ab6.val[1]); + vst1q_f32(pSrc+80, ab7.val[0]); + vst1q_f32(pSrc+84, ab7.val[1]); + vst1q_f32(pSrc+88, ab8.val[0]); + vst1q_f32(pSrc+92, ab8.val[1]); + vst1q_f32(pSrc+96, cd5.val[0]); + vst1q_f32(pSrc+100, cd5.val[1]); + vst1q_f32(pSrc+104, cd6.val[0]); + vst1q_f32(pSrc+108, cd6.val[1]); + vst1q_f32(pSrc+112, cd7.val[0]); + vst1q_f32(pSrc+116, cd7.val[1]); + vst1q_f32(pSrc+120, cd8.val[0]); + vst1q_f32(pSrc+124, cd8.val[1]); + + //Transpose + arm_bitonic_merge_64_f32(pSrc+0 , dir); + arm_bitonic_merge_64_f32(pSrc+64, dir); +} + +static void arm_bitonic_merge_256_f32(float32_t * pSrc, uint8_t dir) +{ + float32x4x2_t ab1, ab2, ab3, ab4, ab5, ab6, ab7, ab8; + float32x4x2_t ab9, ab10, ab11, ab12, ab13, ab14, ab15, ab16; + float32x4x2_t cd1, cd2, cd3, cd4, cd5, cd6, cd7, cd8; + float32x4x2_t cd9, cd10, cd11, cd12, cd13, cd14, cd15, cd16; + + //Load and reverse second array + ab1.val[0] = vld1q_f32(pSrc+0 ); + ab1.val[1] = vld1q_f32(pSrc+4 ); + ab2.val[0] = vld1q_f32(pSrc+8 ); + ab2.val[1] = vld1q_f32(pSrc+12 ); + ab3.val[0] = vld1q_f32(pSrc+16 ); + ab3.val[1] = vld1q_f32(pSrc+20 ); + ab4.val[0] = vld1q_f32(pSrc+24 ); + ab4.val[1] = vld1q_f32(pSrc+28 ); + ab5.val[0] = vld1q_f32(pSrc+32 ); + ab5.val[1] = vld1q_f32(pSrc+36 ); + ab6.val[0] = vld1q_f32(pSrc+40 ); + ab6.val[1] = vld1q_f32(pSrc+44 ); + ab7.val[0] = vld1q_f32(pSrc+48 ); + ab7.val[1] = vld1q_f32(pSrc+52 ); + ab8.val[0] = vld1q_f32(pSrc+56 ); + ab8.val[1] = vld1q_f32(pSrc+60 ); + ab9.val[0] = vld1q_f32(pSrc+64 ); + ab9.val[1] = vld1q_f32(pSrc+68 ); + ab10.val[0] = vld1q_f32(pSrc+72 ); + ab10.val[1] = vld1q_f32(pSrc+76 ); + ab11.val[0] = vld1q_f32(pSrc+80 ); + ab11.val[1] = vld1q_f32(pSrc+84 ); + ab12.val[0] = vld1q_f32(pSrc+88 ); + ab12.val[1] = vld1q_f32(pSrc+92 ); + ab13.val[0] = vld1q_f32(pSrc+96 ); + ab13.val[1] = vld1q_f32(pSrc+100); + ab14.val[0] = vld1q_f32(pSrc+104); + ab14.val[1] = vld1q_f32(pSrc+108); + ab15.val[0] = vld1q_f32(pSrc+112); + ab15.val[1] = vld1q_f32(pSrc+116); + ab16.val[0] = vld1q_f32(pSrc+120); + ab16.val[1] = vld1q_f32(pSrc+124); + + vldrev128q_f32(cd16.val[1], pSrc+128); + vldrev128q_f32(cd16.val[0], pSrc+132); + vldrev128q_f32(cd15.val[1], pSrc+136); + vldrev128q_f32(cd15.val[0], pSrc+140); + vldrev128q_f32(cd14.val[1], pSrc+144); + vldrev128q_f32(cd14.val[0], pSrc+148); + vldrev128q_f32(cd13.val[1], pSrc+152); + vldrev128q_f32(cd13.val[0], pSrc+156); + vldrev128q_f32(cd12.val[1], pSrc+160); + vldrev128q_f32(cd12.val[0], pSrc+164); + vldrev128q_f32(cd11.val[1], pSrc+168); + vldrev128q_f32(cd11.val[0], pSrc+172); + vldrev128q_f32(cd10.val[1], pSrc+176); + vldrev128q_f32(cd10.val[0], pSrc+180); + vldrev128q_f32(cd9.val[1] , pSrc+184); + vldrev128q_f32(cd9.val[0] , pSrc+188); + vldrev128q_f32(cd8.val[1] , pSrc+192); + vldrev128q_f32(cd8.val[0] , pSrc+196); + vldrev128q_f32(cd7.val[1] , pSrc+200); + vldrev128q_f32(cd7.val[0] , pSrc+204); + vldrev128q_f32(cd6.val[1] , pSrc+208); + vldrev128q_f32(cd6.val[0] , pSrc+212); + vldrev128q_f32(cd5.val[1] , pSrc+216); + vldrev128q_f32(cd5.val[0] , pSrc+220); + vldrev128q_f32(cd4.val[1] , pSrc+224); + vldrev128q_f32(cd4.val[0] , pSrc+228); + vldrev128q_f32(cd3.val[1] , pSrc+232); + vldrev128q_f32(cd3.val[0] , pSrc+236); + vldrev128q_f32(cd2.val[1] , pSrc+240); + vldrev128q_f32(cd2.val[0] , pSrc+244); + vldrev128q_f32(cd1.val[1] , pSrc+248); + vldrev128q_f32(cd1.val[0] , pSrc+252); + + //Compare + if(dir) + { + vminmax256q(ab1 , cd1 ); + vminmax256q(ab2 , cd2 ); + vminmax256q(ab3 , cd3 ); + vminmax256q(ab4 , cd4 ); + vminmax256q(ab5 , cd5 ); + vminmax256q(ab6 , cd6 ); + vminmax256q(ab7 , cd7 ); + vminmax256q(ab8 , cd8 ); + vminmax256q(ab9 , cd9 ); + vminmax256q(ab10, cd10); + vminmax256q(ab11, cd11); + vminmax256q(ab12, cd12); + vminmax256q(ab13, cd13); + vminmax256q(ab14, cd14); + vminmax256q(ab15, cd15); + vminmax256q(ab16, cd16); + } + else + { + vminmax256q(cd1 , ab1 ); + vminmax256q(cd2 , ab2 ); + vminmax256q(cd3 , ab3 ); + vminmax256q(cd4 , ab4 ); + vminmax256q(cd5 , ab5 ); + vminmax256q(cd6 , ab6 ); + vminmax256q(cd7 , ab7 ); + vminmax256q(cd8 , ab8 ); + vminmax256q(cd9 , ab9 ); + vminmax256q(cd10, ab10); + vminmax256q(cd11, ab11); + vminmax256q(cd12, ab12); + vminmax256q(cd13, ab13); + vminmax256q(cd14, ab14); + vminmax256q(cd15, ab15); + vminmax256q(cd16, ab16); + } + + //Transpose + float32x4_t temp; + + temp = ab9.val[0]; + ab9.val[0] = cd1.val[0]; + cd1.val[0] = temp; + temp = ab9.val[1]; + ab9.val[1] = cd1.val[1]; + cd1.val[1] = temp; + temp = ab10.val[0]; + ab10.val[0] = cd2.val[0]; + cd2.val[0] = temp; + temp = ab10.val[1]; + ab10.val[1] = cd2.val[1]; + cd2.val[1] = temp; + temp = ab11.val[0]; + ab11.val[0] = cd3.val[0]; + cd3.val[0] = temp; + temp = ab11.val[1]; + ab11.val[1] = cd3.val[1]; + cd3.val[1] = temp; + temp = ab12.val[0]; + ab12.val[0] = cd4.val[0]; + cd4.val[0] = temp; + temp = ab12.val[1]; + ab12.val[1] = cd4.val[1]; + cd4.val[1] = temp; + temp = ab13.val[0]; + ab13.val[0] = cd5.val[0]; + cd5.val[0] = temp; + temp = ab13.val[1]; + ab13.val[1] = cd5.val[1]; + cd5.val[1] = temp; + temp = ab14.val[0]; + ab14.val[0] = cd6.val[0]; + cd6.val[0] = temp; + temp = ab14.val[1]; + ab14.val[1] = cd6.val[1]; + cd6.val[1] = temp; + temp = ab15.val[0]; + ab15.val[0] = cd7.val[0]; + cd7.val[0] = temp; + temp = ab15.val[1]; + ab15.val[1] = cd7.val[1]; + cd7.val[1] = temp; + temp = ab16.val[0]; + ab16.val[0] = cd8.val[0]; + cd8.val[0] = temp; + temp = ab16.val[1]; + ab16.val[1] = cd8.val[1]; + cd8.val[1] = temp; + + //Compare + if(dir) + { + vminmax256q(ab1 , cd1 ); + vminmax256q(ab2 , cd2 ); + vminmax256q(ab3 , cd3 ); + vminmax256q(ab4 , cd4 ); + vminmax256q(ab5 , cd5 ); + vminmax256q(ab6 , cd6 ); + vminmax256q(ab7 , cd7 ); + vminmax256q(ab8 , cd8 ); + vminmax256q(ab9 , cd9 ); + vminmax256q(ab10, cd10); + vminmax256q(ab11, cd11); + vminmax256q(ab12, cd12); + vminmax256q(ab13, cd13); + vminmax256q(ab14, cd14); + vminmax256q(ab15, cd15); + vminmax256q(ab16, cd16); + } + else + { + vminmax256q(cd1 , ab1 ); + vminmax256q(cd2 , ab2 ); + vminmax256q(cd3 , ab3 ); + vminmax256q(cd4 , ab4 ); + vminmax256q(cd5 , ab5 ); + vminmax256q(cd6 , ab6 ); + vminmax256q(cd7 , ab7 ); + vminmax256q(cd8 , ab8 ); + vminmax256q(cd9 , ab9 ); + vminmax256q(cd10, ab10); + vminmax256q(cd11, ab11); + vminmax256q(cd12, ab12); + vminmax256q(cd13, ab13); + vminmax256q(cd14, ab14); + vminmax256q(cd15, ab15); + vminmax256q(cd16, ab16); + } + + vst1q_f32(pSrc, ab1.val[0] ); + vst1q_f32(pSrc+4, ab1.val[1] ); + vst1q_f32(pSrc+8, ab2.val[0] ); + vst1q_f32(pSrc+12, ab2.val[1] ); + vst1q_f32(pSrc+16, ab3.val[0] ); + vst1q_f32(pSrc+20, ab3.val[1] ); + vst1q_f32(pSrc+24, ab4.val[0] ); + vst1q_f32(pSrc+28, ab4.val[1] ); + vst1q_f32(pSrc+32, ab5.val[0] ); + vst1q_f32(pSrc+36, ab5.val[1] ); + vst1q_f32(pSrc+40, ab6.val[0] ); + vst1q_f32(pSrc+44, ab6.val[1] ); + vst1q_f32(pSrc+48, ab7.val[0] ); + vst1q_f32(pSrc+52, ab7.val[1] ); + vst1q_f32(pSrc+56, ab8.val[0] ); + vst1q_f32(pSrc+60, ab8.val[1] ); + vst1q_f32(pSrc+64, cd1.val[0] ); + vst1q_f32(pSrc+68, cd1.val[1] ); + vst1q_f32(pSrc+72, cd2.val[0] ); + vst1q_f32(pSrc+76, cd2.val[1] ); + vst1q_f32(pSrc+80, cd3.val[0] ); + vst1q_f32(pSrc+84, cd3.val[1] ); + vst1q_f32(pSrc+88, cd4.val[0] ); + vst1q_f32(pSrc+92, cd4.val[1] ); + vst1q_f32(pSrc+96, cd5.val[0] ); + vst1q_f32(pSrc+100, cd5.val[1] ); + vst1q_f32(pSrc+104, cd6.val[0] ); + vst1q_f32(pSrc+108, cd6.val[1] ); + vst1q_f32(pSrc+112, cd7.val[0] ); + vst1q_f32(pSrc+116, cd7.val[1] ); + vst1q_f32(pSrc+120, cd8.val[0] ); + vst1q_f32(pSrc+124, cd8.val[1] ); + vst1q_f32(pSrc+128, ab9.val[0] ); + vst1q_f32(pSrc+132, ab9.val[1] ); + vst1q_f32(pSrc+136, ab10.val[0]); + vst1q_f32(pSrc+140, ab10.val[1]); + vst1q_f32(pSrc+144, ab11.val[0]); + vst1q_f32(pSrc+148, ab11.val[1]); + vst1q_f32(pSrc+152, ab12.val[0]); + vst1q_f32(pSrc+156, ab12.val[1]); + vst1q_f32(pSrc+160, ab13.val[0]); + vst1q_f32(pSrc+164, ab13.val[1]); + vst1q_f32(pSrc+168, ab14.val[0]); + vst1q_f32(pSrc+172, ab14.val[1]); + vst1q_f32(pSrc+176, ab15.val[0]); + vst1q_f32(pSrc+180, ab15.val[1]); + vst1q_f32(pSrc+184, ab16.val[0]); + vst1q_f32(pSrc+188, ab16.val[1]); + vst1q_f32(pSrc+192, cd9.val[0] ); + vst1q_f32(pSrc+196, cd9.val[1] ); + vst1q_f32(pSrc+200, cd10.val[0]); + vst1q_f32(pSrc+204, cd10.val[1]); + vst1q_f32(pSrc+208, cd11.val[0]); + vst1q_f32(pSrc+212, cd11.val[1]); + vst1q_f32(pSrc+216, cd12.val[0]); + vst1q_f32(pSrc+220, cd12.val[1]); + vst1q_f32(pSrc+224, cd13.val[0]); + vst1q_f32(pSrc+228, cd13.val[1]); + vst1q_f32(pSrc+232, cd14.val[0]); + vst1q_f32(pSrc+236, cd14.val[1]); + vst1q_f32(pSrc+240, cd15.val[0]); + vst1q_f32(pSrc+244, cd15.val[1]); + vst1q_f32(pSrc+248, cd16.val[0]); + vst1q_f32(pSrc+252, cd16.val[1]); + + //Transpose + arm_bitonic_merge_128_f32(pSrc+0 , dir); + arm_bitonic_merge_128_f32(pSrc+128, dir); +} + +#define SWAP(a,i,j) \ + temp = vgetq_lane_f32(a, j); \ + a = vsetq_lane_f32(vgetq_lane_f32(a, i), a, j);\ + a = vsetq_lane_f32(temp, a, i); + +static float32x4_t arm_bitonic_sort_4_f32(float32x4_t a, uint8_t dir) +{ + float32_t temp; + + + if( dir==(vgetq_lane_f32(a, 0) > vgetq_lane_f32(a, 1)) ) + { + SWAP(a,0,1); + } + if( dir==(vgetq_lane_f32(a, 2) > vgetq_lane_f32(a, 3)) ) + { + SWAP(a,2,3); + } + + if( dir==(vgetq_lane_f32(a, 0) > vgetq_lane_f32(a, 3)) ) + { + SWAP(a,0,3); + } + if( dir==(vgetq_lane_f32(a, 1) > vgetq_lane_f32(a, 2)) ) + { + SWAP(a,1,2); + } + + if( dir==(vgetq_lane_f32(a, 0) > vgetq_lane_f32(a, 1)) ) + { + SWAP(a,0,1); + } + if( dir==(vgetq_lane_f32(a, 2)>vgetq_lane_f32(a, 3)) ) + { + SWAP(a,2,3); + } + + return a; +} + +static float32x4x2_t arm_bitonic_sort_8_f32(float32x4_t a, float32x4_t b, uint8_t dir) +{ + a = arm_bitonic_sort_4_f32(a, dir); + b = arm_bitonic_sort_4_f32(b, dir); + return arm_bitonic_merge_8_f32(a, b, dir); +} + + + +#endif + +/** + @ingroup groupSupport + */ + +/** + @defgroup Sorting Vector sorting algorithms + + Sort the elements of a vector + + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup Sorting + @{ + */ + +/** + * @private + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void arm_bitonic_sort_f32( +const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint16_t s, i; + uint8_t dir = S->dir; + +#ifdef ARM_MATH_NEON + (void)s; + + float32_t * pOut; + uint16_t counter = blockSize>>5; + + if( (blockSize & (blockSize-1)) == 0 ) // Powers of 2 only + { + if(pSrc == pDst) // in-place + pOut = pSrc; + else + pOut = pDst; + + float32x4x2_t ab1, ab2; + float32x4x2_t cd1, cd2; + + if(blockSize == 1) + pOut = pSrc; + else if(blockSize == 2) + { + float32_t temp; + + if( dir==(pSrc[0]>pSrc[1]) ) + { + temp = pSrc[1]; + pOut[1] = pSrc[0]; + pOut[0] = temp; + } + else + pOut = pSrc; + } + else if(blockSize == 4) + { + float32x4_t a = vld1q_f32(pSrc); + + a = arm_bitonic_sort_4_f32(a, dir); + + vst1q_f32(pOut, a); + } + else if(blockSize == 8) + { + float32x4_t a; + float32x4_t b; + float32x4x2_t ab; + + a = vld1q_f32(pSrc); + b = vld1q_f32(pSrc+4); + + ab = arm_bitonic_sort_8_f32(a, b, dir); + + vst1q_f32(pOut, ab.val[0]); + vst1q_f32(pOut+4, ab.val[1]); + } + else if(blockSize >=16) + { + // Order 16 bits long vectors + for(i=0; i>1; + for(i=0; i>1; + for(i=0; i>1; + for(i=0; idir; + uint32_t i; + uint8_t swapped =1; + float32_t * pA; + float32_t temp; + + if(pSrc != pDst) // out-of-place + { + memcpy(pDst, pSrc, blockSize*sizeof(float32_t) ); + pA = pDst; + } + else + pA = pSrc; + + while(swapped==1) // If nothing has been swapped after one loop stop + { + swapped=0; + + for(i=0; ipA[i+1])) + { + // Swap + temp = pA[i]; + pA[i] = pA[i+1]; + pA[i+1] = temp; + + // Update flag + swapped = 1; + } + } + + blockSize--; + } +} + +/** + @} end of Sorting group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f16.c new file mode 100644 index 00000000..d441332a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f16.c @@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_copy_f16.c + * Description: Copies the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a f16 vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_copy_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + do { + mve_pred16_t p = vctp16q(blockSize); + + vstrhq_p_f16(pDst, + vldrhq_z_f16((float16_t const *) pSrc, p), p); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + blockSize -= 8; + } + while ((int32_t) blockSize > 0); +} + +#else + +void arm_copy_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicCopy group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c new file mode 100644 index 00000000..d739f7cb --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_copy_f32.c + * Description: Copies the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @defgroup copy Vector Copy + + Copies sample by sample from source vector to destination vector. + +
+      pDst[n] = pSrc[n];   0 <= n < blockSize.
+  
+ + There are separate functions for floating point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a floating-point vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time */ + while (blkCnt > 0U) + { + vstrwq_f32(pDst, vldrwq_f32(pSrc)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + blkCnt --; + } + + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + + float32x4_t inV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A */ + /* Copy and then store the results in the destination buffer */ + inV = vld1q_f32(pSrc); + vst1q_f32(pDst, inV); + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + /* C = A */ + /* Copy and then store the results in the destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicCopy group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f64.c new file mode 100644 index 00000000..ec1df54f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f64.c @@ -0,0 +1,71 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_copy_f64.c + * Description: Copies the elements of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a floating-point vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +void arm_copy_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} + +/** + @} end of BasicCopy group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c new file mode 100644 index 00000000..18f33876 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c @@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_copy_q15.c + * Description: Copies the elements of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a Q15 vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_copy_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vstrhq_s16(pDst,vldrhq_s16(pSrc)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + blkCnt --; + } + + blkCnt = blockSize & 7; + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_copy_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ + + /* read 2 times 2 samples at a time */ + write_q15x2_ia (&pDst, read_q15x2_ia (&pSrc)); + write_q15x2_ia (&pDst, read_q15x2_ia (&pSrc)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicCopy group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c new file mode 100644 index 00000000..8e06bdac --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c @@ -0,0 +1,135 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_copy_q31.c + * Description: Copies the elements of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a Q31 vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_copy_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time */ + while (blkCnt > 0U) + { + vstrwq_s32(pDst,vldrwq_s32(pSrc)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + blkCnt --; + } + + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#else +void arm_copy_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicCopy group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c new file mode 100644 index 00000000..1918d3e4 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_copy_q7.c + * Description: Copies the elements of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a Q7 vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_copy_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + + uint32_t blkCnt; + + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + + vstrbq_s8(pDst,vldrbq_s8(pSrc)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 16; + pDst += 16; + blkCnt --; + } + + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_copy_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ + + /* read 4 samples at a time */ + write_q7x4_ia (&pDst, read_q7x4_ia (&pSrc)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicCopy group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_f16_to_float.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_f16_to_float.c new file mode 100644 index 00000000..a0043539 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_f16_to_float.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_float_to_q15.c + * Description: Converts the elements of the floating-point vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + +/** + * @defgroup f16_to_x Convert 16-bit floating point value + */ + +/** + @addtogroup f16_to_x + @{ + */ + +/** + @brief Converts the elements of the f16 vector to f32 vector. + @param[in] pSrc points to the f16 input vector + @param[out] pDst points to the f32 output vector + @param[in] blockSize number of samples in each vector + @return none + + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_f16_to_float built. Helium version has build issues with gcc." +#endif + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) + +void arm_f16_to_float( + const float16_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + int32_t blkCnt; /* loop counters */ + float16x8_t vecDst; + float32x4x2_t tmp; + + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecDst = vldrhq_f16(pSrc); + pSrc += 8; + + tmp.val[0] = vcvtbq_f32_f16(vecDst); + tmp.val[1] = vcvttq_f32_f16(vecDst); + vst2q(pDst,tmp); + + pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + while (blkCnt > 0) + { + + *pDst++ = (float32_t) *pSrc++; + /* + * Decrement the loop counter + */ + blkCnt--; + } +} + +#else +void arm_f16_to_float( + const float16_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float16_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + /* + * Loop over blockSize number of values + */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + + *pDst++ = (float32_t) * pIn++; + /* + * Decrement the loop counter + */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of f16_to_x group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_f16_to_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_f16_to_q15.c new file mode 100644 index 00000000..bb425d13 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_f16_to_q15.c @@ -0,0 +1,157 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_float_to_q15.c + * Description: Converts the elements of the floating-point vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + +/** + @addtogroup f16_to_x + @{ + */ + +/** + @brief Converts the elements of the f16 vector to Q15 vector. + @param[in] pSrc points to the f16 input vector + @param[out] pDst points to the Q15 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: +
+      pDst[n] = (q15_t)(pSrc[n] * 32768);   0 <= n < blockSize.
+  
+ + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + + @note + In order to apply rounding in scalar version, the library should be rebuilt with the ROUNDING macro + defined in the preprocessor section of project options. + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_f16_to_q15( + const float16_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + float16_t maxQ = (float16_t) Q15_MAX; + float16x8_t vecDst; + + + do { + mve_pred16_t p = vctp16q(blockSize); + + vecDst = vldrhq_z_f16((float16_t const *) pSrc, p); + /* C = A * 32767 */ + /* convert from float to Q15 and then store the results in the destination buffer */ + vecDst = vmulq_m(vuninitializedq_f16(), vecDst, maxQ, p); + + vstrhq_p_s16(pDst, + vcvtaq_m(vuninitializedq_s16(), vecDst, p), p); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + blockSize -= 8; + } + while ((int32_t) blockSize > 0); +} + +#else + +void arm_f16_to_q15( + const float16_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + const float16_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ +#ifdef ARM_MATH_ROUNDING + float16_t in; +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* + * Loop over blockSize number of values + */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + + /* + * C = A * 65536 + */ + /* + * convert from float to Q31 and then store the results in the destination buffer + */ + in = *pIn++; + in = (in * 32768.0); + in += in > 0.0 ? 0.5 : -0.5; + *pDst++ = clip_q31_to_q15((q31_t) (in)); + +#else + + /* + * C = A * 32768 + */ + /* + * convert from float to Q31 and then store the results in the destination buffer + */ + *pDst++ = clip_q31_to_q15((q31_t) ((_Float16)*pIn++ * 32768.0f16)); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* + * Decrement the loop counter + */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of f16_to_x group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f16.c new file mode 100644 index 00000000..0b08f12c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f16.c @@ -0,0 +1,127 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fill_f16.c + * Description: Fills a constant value into a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a f16 vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_fill_f16( + float16_t value, + float16_t * pDst, + uint32_t blockSize) +{ + do { + mve_pred16_t p = vctp16q(blockSize); + + vstrhq_p_f16(pDst, + vdupq_m_n_f16(vuninitializedq_f16(), value, p), p); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pDst += 8; + blockSize -= 8; + } + while ((int32_t) blockSize > 0); +} +#else +void arm_fill_f16( + float16_t value, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Fill group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c new file mode 100644 index 00000000..50cdd8fc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c @@ -0,0 +1,189 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fill_f32.c + * Description: Fills a constant value into a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @defgroup Fill Vector Fill + + Fills the destination vector with a constant value. + +
+      pDst[n] = value;   0 <= n < blockSize.
+  
+ + There are separate functions for floating point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a floating-point vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time */ + while (blkCnt > 0U) + { + + vstrwq_f32(pDst,vdupq_n_f32(value)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pDst += 4; + blkCnt --; + } + + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + + + float32x4_t inV = vdupq_n_f32(value); + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = value */ + /* Fill the value in the destination buffer */ + vst1q_f32(pDst, inV); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + /* C = value */ + /* Fill the value in the destination buffer */ + *pDst++ = value; + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Fill group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f64.c new file mode 100644 index 00000000..4bc2700d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f64.c @@ -0,0 +1,71 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fill_f64.c + * Description: Fills a constant value into a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a floating-point vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +void arm_fill_f64( + float64_t value, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} + +/** + @} end of Fill group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c new file mode 100644 index 00000000..997a728d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fill_q15.c + * Description: Fills a constant value into a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a Q15 vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + + vstrhq_s16(pDst,vdupq_n_s16(value)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pDst += 8; + blkCnt --; + } + + blkCnt = blockSize & 7; + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t packedValue; /* value packed to 32 bits */ + + /* Packing two 16 bit values to 32 bit value in order to use SIMD */ + packedValue = __PKHBT(value, value, 16U); + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ + + /* fill 2 times 2 samples at a time */ + write_q15x2_ia (&pDst, packedValue); + write_q15x2_ia (&pDst, packedValue); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Fill group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c new file mode 100644 index 00000000..7da5fb6a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c @@ -0,0 +1,135 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fill_q31.c + * Description: Fills a constant value into a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a Q31 vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time */ + while (blkCnt > 0U) + { + + vstrwq_s32(pDst,vdupq_n_s32(value)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pDst += 4; + blkCnt --; + } + + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#else +void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Fill group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c new file mode 100644 index 00000000..830fc732 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c @@ -0,0 +1,133 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fill_q7.c + * Description: Fills a constant value into a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a Q7 vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + + vstrbq_s8(pDst,vdupq_n_s8(value)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pDst += 16; + blkCnt --; + } + + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t packedValue; /* value packed to 32 bits */ + + /* Packing four 8 bit values to 32 bit value in order to use SIMD */ + packedValue = __PACKq7(value, value, value, value); + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ + + /* fill 4 samples at a time */ + write_q7x4_ia (&pDst, packedValue); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Fill group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_f16.c new file mode 100644 index 00000000..d627a8ad --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_f16.c @@ -0,0 +1,131 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_float_to_q15.c + * Description: Converts the elements of the floating-point vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + +/** + @addtogroup float_to_x + @{ + */ + +/** + @brief Converts the elements of the floating-point vector to f16 vector. + @param[in] pSrc points to the f32 input vector + @param[out] pDst points to the f16 output vector + @param[in] blockSize number of samples in each vector + @return none + + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_float_to_f16 built. Helium version has build issues with gcc." +#endif + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) + +void arm_float_to_f16( + const float32_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + int32_t blkCnt; /* loop counters */ + float32x4x2_t tmp; + float16x8_t vecDst; + float32_t const *pSrcVec; + + + pSrcVec = (float32_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + /* convert from float32 to float16 and then store the results in the destination buffer */ + tmp = vld2q(pSrcVec); pSrcVec += 8; + /* narrow / merge */ + vecDst = vcvtbq_f16_f32(vecDst, tmp.val[0]); + vecDst = vcvttq_f16_f32(vecDst, tmp.val[1]); + vst1q(pDst, vecDst); pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp16q(blkCnt); + tmp = vld2q(pSrcVec); + vecDst = vcvtbq_f16_f32(vecDst, tmp.val[0]); + vecDst = vcvttq_f16_f32(vecDst, tmp.val[1]); + vstrhq_p(pDst, vecDst, p0); + } +} + +#else + +void arm_float_to_f16( + const float32_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + /* + * Loop over blockSize number of values + */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + + *pDst++ = (float16_t) * pIn++; + /* + * Decrement the loop counter + */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of float_to_x group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c new file mode 100644 index 00000000..8061c9f2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c @@ -0,0 +1,308 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_float_to_q15.c + * Description: Converts the elements of the floating-point vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup float_to_x + @{ + */ + +/** + @brief Converts the elements of the floating-point vector to Q15 vector. + @param[in] pSrc points to the floating-point input vector + @param[out] pDst points to the Q15 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: +
+      pDst[n] = (q15_t)(pSrc[n] * 32768);   0 <= n < blockSize.
+  
+ + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + + @note + In order to apply rounding, the library should be rebuilt with the ROUNDING macro + defined in the preprocessor section of project options. + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + float32_t maxQ = (float32_t) Q15_MAX; + f32x4x2_t tmp; + q15x8_t vecDst; +#ifdef ARM_MATH_ROUNDING + float32_t in; +#endif + + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* C = A * 32768 */ + /* convert from float to q15 and then store the results in the destination buffer */ + tmp = vld2q(pSrc); + + tmp.val[0] = vmulq(tmp.val[0], maxQ); + tmp.val[1] = vmulq(tmp.val[1], maxQ); + + vecDst = vqmovnbq(vecDst, vcvtaq_s32_f32(tmp.val[0])); + vecDst = vqmovntq(vecDst, vcvtaq_s32_f32(tmp.val[1])); + vst1q(pDst, vecDst); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + pDst += 8; + pSrc += 8; + } + + blkCnt = blockSize & 7; + while (blkCnt > 0U) + { + /* C = A * 32768 */ + + /* convert from float to Q15 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pSrc++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + +#else + + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t) __SSAT((q31_t) (*pSrc++ * 32768.0f), 16); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + float32x4_t inV; + #ifdef ARM_MATH_ROUNDING + float32x4_t zeroV = vdupq_n_f32(0.0f); + float32x4_t pHalf = vdupq_n_f32(0.5f / 32768.0f); + float32x4_t mHalf = vdupq_n_f32(-0.5f / 32768.0f); + float32x4_t r; + uint32x4_t cmp; + float32_t in; + #endif + + int32x4_t cvt; + int16x4_t outV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + cmp = vcgtq_f32(inV,zeroV); + r = vbslq_f32(cmp,pHalf,mHalf); + inV = vaddq_f32(inV, r); + + pIn += 4; + + cvt = vcvtq_n_s32_f32(inV,15); + outV = vqmovn_s32(cvt); + + vst1_s16(pDst, outV); + pDst += 4; + +#else + + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + + cvt = vcvtq_n_s32_f32(inV,15); + outV = vqmovn_s32(cvt); + + vst1_s16(pDst, outV); + pDst += 4; + pIn += 4; + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + in = *pIn++; + in = (in * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + +#else + + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const float32_t *pIn = pSrc; /* Source pointer */ + +#ifdef ARM_MATH_ROUNDING + float32_t in; +#endif /* #ifdef ARM_MATH_ROUNDING */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * 32768 */ + + /* convert from float to Q15 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + +#else + + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * 32768 */ + + /* convert from float to Q15 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + +#else + + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of float_to_x group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c new file mode 100644 index 00000000..a222e499 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c @@ -0,0 +1,314 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_float_to_q31.c + * Description: Converts the elements of the floating-point vector to Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + * @defgroup float_to_x Convert 32-bit floating point value + */ + +/** + @addtogroup float_to_x + @{ + */ + +/** + @brief Converts the elements of the floating-point vector to Q31 vector. + @param[in] pSrc points to the floating-point input vector + @param[out] pDst points to the Q31 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: +
+      pDst[n] = (q31_t)(pSrc[n] * 2147483648);   0 <= n < blockSize.
+  
+ + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] are saturated. + + @note + In order to apply rounding, the library should be rebuilt with the ROUNDING macro + defined in the preprocessor section of project options. + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + float32_t maxQ = (float32_t) Q31_MAX; + f32x4_t vecDst; +#ifdef ARM_MATH_ROUNDING + float32_t in; +#endif + + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. */ + while (blkCnt > 0U) + { + + vecDst = vldrwq_f32(pSrc); + /* C = A * 2147483648 */ + /* convert from float to Q31 and then store the results in the destination buffer */ + vecDst = vmulq(vecDst, maxQ); + + vstrwq_s32(pDst, vcvtaq_s32_f32(vecDst)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + blkCnt --; + } + + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + /* C = A * 2147483648 */ + + /* convert from float to Q31 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pSrc++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + +#else + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + *pDst++ = clip_q63_to_q31((q63_t) (*pSrc++ * 2147483648.0f)); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +#if defined(ARM_MATH_NEON) +void arm_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + float32x4_t inV; + #ifdef ARM_MATH_ROUNDING + float32_t in; + float32x4_t zeroV = vdupq_n_f32(0.0f); + float32x4_t pHalf = vdupq_n_f32(0.5f / 2147483648.0f); + float32x4_t mHalf = vdupq_n_f32(-0.5f / 2147483648.0f); + float32x4_t r; + uint32x4_t cmp; + #endif + + int32x4_t outV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + + /* C = A * 32768 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + cmp = vcgtq_f32(inV,zeroV); + r = vbslq_f32(cmp,pHalf,mHalf); + inV = vaddq_f32(inV, r); + + pIn += 4; + + outV = vcvtq_n_s32_f32(inV,31); + + vst1q_s32(pDst, outV); + pDst += 4; + +#else + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + + outV = vcvtq_n_s32_f32(inV,31); + + vst1q_s32(pDst, outV); + pDst += 4; + pIn += 4; + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + in = *pIn++; + in = (in * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + +#else + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } + + +} +#else +void arm_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const float32_t *pIn = pSrc; /* Source pointer */ + +#ifdef ARM_MATH_ROUNDING + float32_t in; +#endif /* #ifdef ARM_MATH_ROUNDING */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * 2147483648 */ + + /* convert from float to Q31 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + +#else + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * 2147483648 */ + + /* convert from float to Q31 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + +#else + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of float_to_x group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c new file mode 100644 index 00000000..27af5206 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c @@ -0,0 +1,330 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_float_to_q7.c + * Description: Converts the elements of the floating-point vector to Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup float_to_x + @{ + */ + +/** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + *\par Description: + * \par + * The equation used for the conversion process is: + *
+ * 	pDst[n] = (q7_t)(pSrc[n] * 128);   0 <= n < blockSize.
+ * 
+ * \par Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + * \note + * In order to apply rounding, the library should be rebuilt with the ROUNDING macro + * defined in the preprocessor section of project options. + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + float32_t maxQ = powf(2.0, 7); + f32x4x4_t tmp; + q15x8_t evVec, oddVec; + q7x16_t vecDst; + float32_t const *pSrcVec; +#ifdef ARM_MATH_ROUNDING + float32_t in; +#endif + + pSrcVec = (float32_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0U) { + tmp = vld4q(pSrcVec); + pSrcVec += 16; + /* + * C = A * 128.0 + * convert from float to q7 and then store the results in the destination buffer + */ + tmp.val[0] = vmulq(tmp.val[0], maxQ); + tmp.val[1] = vmulq(tmp.val[1], maxQ); + tmp.val[2] = vmulq(tmp.val[2], maxQ); + tmp.val[3] = vmulq(tmp.val[3], maxQ); + + /* + * convert and pack evens + */ + evVec = vqmovnbq(evVec, vcvtaq_s32_f32(tmp.val[0])); + evVec = vqmovntq(evVec, vcvtaq_s32_f32(tmp.val[2])); + /* + * convert and pack odds + */ + oddVec = vqmovnbq(oddVec, vcvtaq_s32_f32(tmp.val[1])); + oddVec = vqmovntq(oddVec, vcvtaq_s32_f32(tmp.val[3])); + /* + * merge + */ + vecDst = vqmovnbq(vecDst, evVec); + vecDst = vqmovntq(vecDst, oddVec); + + vst1q(pDst, vecDst); + pDst += 16; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* C = A * 128 */ + + /* Convert from float to q7 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pSrcVec++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + +#else + + *pDst++ = (q7_t) __SSAT((q31_t) (*pSrcVec++ * 128.0f), 8); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + +} +#else +#if defined(ARM_MATH_NEON) +void arm_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + float32x4_t inV; + #ifdef ARM_MATH_ROUNDING + float32_t in; + float32x4_t zeroV = vdupq_n_f32(0.0f); + float32x4_t pHalf = vdupq_n_f32(0.5f / 128.0f); + float32x4_t mHalf = vdupq_n_f32(-0.5f / 128.0f); + float32x4_t r; + uint32x4_t cmp; + #endif + + int16x4_t cvt1,cvt2; + int8x8_t outV; + + blkCnt = blockSize >> 3U; + + /* Compute 8 outputs at a time. + ** a second loop below computes the remaining 1 to 7 samples. */ + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + /* C = A * 128 */ + /* Convert from float to q7 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + cmp = vcgtq_f32(inV,zeroV); + r = vbslq_f32(cmp,pHalf,mHalf); + inV = vaddq_f32(inV, r); + cvt1 = vqmovn_s32(vcvtq_n_s32_f32(inV,7)); + pIn += 4; + + inV = vld1q_f32(pIn); + cmp = vcgtq_f32(inV,zeroV); + r = vbslq_f32(cmp,pHalf,mHalf); + inV = vaddq_f32(inV, r); + cvt2 = vqmovn_s32(vcvtq_n_s32_f32(inV,7)); + pIn += 4; + + outV = vqmovn_s16(vcombine_s16(cvt1,cvt2)); + vst1_s8(pDst, outV); + pDst += 8; + +#else + + /* C = A * 128 */ + /* Convert from float to q7 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + cvt1 = vqmovn_s32(vcvtq_n_s32_f32(inV,7)); + pIn += 4; + + inV = vld1q_f32(pIn); + cvt2 = vqmovn_s32(vcvtq_n_s32_f32(inV,7)); + pIn += 4; + + outV = vqmovn_s16(vcombine_s16(cvt1,cvt2)); + + vst1_s8(pDst, outV); + pDst += 8; +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 7; + + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + /* C = A * 128 */ + /* Convert from float to q7 and then store the results in the destination buffer */ + in = *pIn++; + in = (in * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + +#else + + /* C = A * 128 */ + /* Convert from float to q7 and then store the results in the destination buffer */ + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } + +} +#else +void arm_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const float32_t *pIn = pSrc; /* Source pointer */ + +#ifdef ARM_MATH_ROUNDING + float32_t in; +#endif /* #ifdef ARM_MATH_ROUNDING */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * 128 */ + + /* Convert from float to q7 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + +#else + + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * 128 */ + + /* Convert from float to q7 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + +#else + + *pDst++ = (q7_t) __SSAT((q31_t) (*pIn++ * 128.0f), 8); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of float_to_x group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c new file mode 100644 index 00000000..5a46caa3 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c @@ -0,0 +1,119 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_heap_sort_f32.c + * Description: Floating point heap sort + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" +#include "arm_sorting.h" + + + +static void arm_heapify(float32_t * pSrc, uint32_t n, uint32_t i, uint8_t dir) +{ + /* Put all the elements of pSrc in heap order */ + uint32_t k = i; // Initialize largest/smallest as root + uint32_t l = 2*i + 1; // left = 2*i + 1 + uint32_t r = 2*i + 2; // right = 2*i + 2 + float32_t temp; + + if (l < n && dir==(pSrc[l] > pSrc[k]) ) + k = l; + + if (r < n && dir==(pSrc[r] > pSrc[k]) ) + k = r; + + if (k != i) + { + temp = pSrc[i]; + pSrc[i]=pSrc[k]; + pSrc[k]=temp; + + arm_heapify(pSrc, n, k, dir); + } +} + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + +/** + * @private + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * + * @par Algorithm + * The heap sort algorithm is a comparison algorithm that + * divides the input array into a sorted and an unsorted region, + * and shrinks the unsorted region by extracting the largest + * element and moving it to the sorted region. A heap data + * structure is used to find the maximum. + * + * @par It's an in-place algorithm. In order to obtain an out-of-place + * function, a memcpy of the source vector is performed. + */ +void arm_heap_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t * pA; + int32_t i; + float32_t temp; + + if(pSrc != pDst) // out-of-place + { + memcpy(pDst, pSrc, blockSize*sizeof(float32_t) ); + pA = pDst; + } + else + pA = pSrc; + + // Build the heap array so that the largest value is the root + for (i = blockSize/2 - 1; i >= 0; i--) + arm_heapify(pA, blockSize, i, S->dir); + + for (i = blockSize - 1; i >= 0; i--) + { + // Swap + temp = pA[i]; + pA[i] = pA[0]; + pA[0] = temp; + + // Restore heap order + arm_heapify(pA, i, 0, S->dir); + } +} +/** + @} end of Sorting group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c new file mode 100644 index 00000000..4e850438 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_insertion_sort_f32.c + * Description: Floating point insertion sort + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" +#include "arm_sorting.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + +/** + * @private + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * + * @par Algorithm + * The insertion sort is a simple sorting algorithm that + * reads all the element of the input array and removes one element + * at a time, finds the location it belongs in the final sorted list, + * and inserts it there. + * + * @par It's an in-place algorithm. In order to obtain an out-of-place + * function, a memcpy of the source vector is performed. + */ + +void arm_insertion_sort_f32( + const arm_sort_instance_f32 * S, + float32_t *pSrc, + float32_t* pDst, + uint32_t blockSize) +{ + float32_t * pA; + uint8_t dir = S->dir; + uint32_t i, j; + float32_t temp; + + if(pSrc != pDst) // out-of-place + { + memcpy(pDst, pSrc, blockSize*sizeof(float32_t) ); + pA = pDst; + } + else + pA = pSrc; + + // Real all the element of the input array + for(i=0; i0 && dir==(pA[j]= end || dir==(pA[i] <= pA[j])) ) + { + pB[k] = pA[i]; + i++; + } + else + { + pB[k] = pA[j]; + j++; + } + } +} + +static void arm_merge_sort_core_f32(float32_t * pB, uint32_t begin, uint32_t end, float32_t * pA, uint8_t dir) +{ + if((int32_t)end - (int32_t)begin >= 2 ) // If run size != 1 divide + { + int32_t middle = (end + begin) / 2; // Take the middle point + + arm_merge_sort_core_f32(pA, begin, middle, pB, dir); // Sort the left part + arm_merge_sort_core_f32(pA, middle, end, pB, dir); // Sort the right part + + topDownMerge(pB, begin, middle, end, pA, dir); + } +} + + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + +/** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * + * @par Algorithm + * The merge sort algorithm is a comparison algorithm that + * divide the input array in sublists and merge them to produce + * longer sorted sublists until there is only one list remaining. + * + * @par A work array is always needed. It must be allocated by the user + * linked to the instance at initialization time. + * + * @par It's an in-place algorithm. In order to obtain an out-of-place + * function, a memcpy of the source vector is performed + */ + + +void arm_merge_sort_f32( + const arm_merge_sort_instance_f32 * S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize) +{ + float32_t * pA; + + /* Out-of-place */ + if(pSrc != pDst) + { + memcpy(pDst, pSrc, blockSize*sizeof(float32_t)); + pA = pDst; + } + else + pA = pSrc; + + /* A working buffer is needed */ + memcpy(S->buffer, pSrc, blockSize*sizeof(float32_t)); + + arm_merge_sort_core_f32(S->buffer, 0, blockSize, pA, S->dir); +} +/** + @} end of Sorting group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c new file mode 100644 index 00000000..bd93a00f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_merge_sort_init_f32.c + * Description: Floating point merge sort initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] dir Sorting order. + * @param[in] buffer Working buffer. + */ +void arm_merge_sort_init_f32(arm_merge_sort_instance_f32 * S, arm_sort_dir dir, float32_t * buffer) +{ + S->dir = dir; + S->buffer = buffer; +} +/** + @} end of Sorting group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_f16.c new file mode 100644 index 00000000..22a7eaaa --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_f16.c @@ -0,0 +1,155 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q15_to_float.c + * Description: Converts the elements of the Q15 vector to floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + +/** + * @defgroup q15_to_x Convert 16-bit fixed point value + */ + +/** + @addtogroup q15_to_x + @{ + */ + +/** + @brief Converts the elements of the Q15 vector to f16 vector. + @param[in] pSrc points to the Q15 input vector + @param[out] pDst points to the f16 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: +
+      pDst[n] = (float16_t) pSrc[n] / 32768;   0 <= n < blockSize.
+  
+ */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_q15_to_f16( + const q15_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + int32_t blkCnt; /* loop counters */ + q15x8_t vecDst; + q15_t const *pSrcVec; + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + /* C = (float16_t) A / 32768 */ + /* convert from q15 to float and then store the results in the destination buffer */ + vecDst = vld1q(pSrcVec); pSrcVec += 8; + vstrhq(pDst, vcvtq_n_f16_s16(vecDst, 15)); pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecDst = vld1q(pSrcVec); pSrcVec += 8; + vstrhq_p(pDst, vcvtq_n_f16_s16(vecDst, 15), p0); + } +} +#else + +void arm_q15_to_f16( + const q15_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q15_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (float16_t) A / 32768 */ + + /* Convert from q15 to float and store result in destination buffer */ + *pDst++ = ((_Float16) * pIn++ / 32768.0f16); + *pDst++ = ((_Float16) * pIn++ / 32768.0f16); + *pDst++ = ((_Float16) * pIn++ / 32768.0f16); + *pDst++ = ((_Float16) * pIn++ / 32768.0f16); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (float16_t) A / 32768 */ + + /* Convert from q15 to float and store result in destination buffer */ + *pDst++ = ((_Float16) *pIn++ / 32768.0f16); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of q15_to_x group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c new file mode 100644 index 00000000..1a20defe --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c @@ -0,0 +1,207 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q15_to_float.c + * Description: Converts the elements of the Q15 vector to floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + * @defgroup q15_to_x Convert 16-bit fixed point value + */ + +/** + @addtogroup q15_to_x + @{ + */ + +/** + @brief Converts the elements of the Q15 vector to floating-point vector. + @param[in] pSrc points to the Q15 input vector + @param[out] pDst points to the floating-point output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: +
+      pDst[n] = (float32_t) pSrc[n] / 32768;   0 <= n < blockSize.
+  
+ */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + + q15x8_t vecDst; + q15_t const *pSrcVec; + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + /* convert from q15 to float and then store the results in the destination buffer */ + vecDst = vldrhq_s32(pSrcVec); + pSrcVec += 4; + vstrwq(pDst, vcvtq_n_f32_s32((int32x4_t)vecDst, 15)); + pDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + + /* Convert from q15 to float and store result in destination buffer */ + *pDst++ = ((float32_t) *pSrcVec++ / 32768.0f); + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const q15_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + int16x8_t inV; + int32x4_t inV0, inV1; + float32x4_t outV; + + blkCnt = blockSize >> 3U; + + /* Compute 8 outputs at a time. + ** a second loop below computes the remaining 1 to 7 samples. */ + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + /* convert from q15 to float and then store the results in the destination buffer */ + inV = vld1q_s16(pIn); + pIn += 8; + + inV0 = vmovl_s16(vget_low_s16(inV)); + inV1 = vmovl_s16(vget_high_s16(inV)); + + outV = vcvtq_n_f32_s32(inV0,15); + vst1q_f32(pDst, outV); + pDst += 4; + + outV = vcvtq_n_f32_s32(inV1,15); + vst1q_f32(pDst, outV); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 8, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 7; + + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + /* convert from q15 to float and then store the results in the destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q15_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + + /* Convert from q15 to float and store result in destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + + /* Convert from q15 to float and store result in destination buffer */ + *pDst++ = ((float32_t) *pIn++ / 32768.0f); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of q15_to_x group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c new file mode 100644 index 00000000..fc3c8681 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c @@ -0,0 +1,182 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q15_to_q31.c + * Description: Converts the elements of the Q15 vector to Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q15_to_x + @{ + */ + +/** + @brief Converts the elements of the Q15 vector to Q31 vector. + @param[in] pSrc points to the Q15 input vector + @param[out] pDst points to the Q31 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: +
+      pDst[n] = (q31_t) pSrc[n] << 16;   0 <= n < blockSize.
+  
+ */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q15_to_q31( + const q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + + uint32_t blkCnt; + + q31x4_t vecDst; + + blkCnt = blockSize>> 2; + while (blkCnt > 0U) + { + + /* C = (q31_t)A << 16 */ + /* convert from q15 to q31 and then store the results in the destination buffer */ + /* load q15 + 32-bit widening */ + vecDst = vldrhq_s32((q15_t const *) pSrc); + vecDst = vshlq_n(vecDst, 16); + vstrwq_s32(pDst, vecDst); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pDst += 4; + pSrc += 4; + blkCnt --; + } + + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C = (q31_t) A << 16 */ + + /* Convert from q15 to q31 and store result in destination buffer */ + *pDst++ = (q31_t) *pSrc++ << 16; + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_q15_to_q31( + const q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q15_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t in1, in2; + q31_t out1, out2, out3, out4; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q31_t)A << 16 */ + + /* Convert from q15 to q31 and store result in destination buffer */ + in1 = read_q15x2_ia (&pIn); + in2 = read_q15x2_ia (&pIn); + +#ifndef ARM_MATH_BIG_ENDIAN + + /* extract lower 16 bits to 32 bit result */ + out1 = in1 << 16U; + /* extract upper 16 bits to 32 bit result */ + out2 = in1 & 0xFFFF0000; + /* extract lower 16 bits to 32 bit result */ + out3 = in2 << 16U; + /* extract upper 16 bits to 32 bit result */ + out4 = in2 & 0xFFFF0000; + +#else + + /* extract upper 16 bits to 32 bit result */ + out1 = in1 & 0xFFFF0000; + /* extract lower 16 bits to 32 bit result */ + out2 = in1 << 16U; + /* extract upper 16 bits to 32 bit result */ + out3 = in2 & 0xFFFF0000; + /* extract lower 16 bits to 32 bit result */ + out4 = in2 << 16U; + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + *pDst++ = out1; + *pDst++ = out2; + *pDst++ = out3; + *pDst++ = out4; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q31_t) A << 16 */ + + /* Convert from q15 to q31 and store result in destination buffer */ + *pDst++ = (q31_t) *pIn++ << 16; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of q15_to_x group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c new file mode 100644 index 00000000..eac81057 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c @@ -0,0 +1,190 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q15_to_q7.c + * Description: Converts the elements of the Q15 vector to Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q15_to_x + @{ + */ + +/** + @brief Converts the elements of the Q15 vector to Q7 vector. + @param[in] pSrc points to the Q15 input vector + @param[out] pDst points to the Q7 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: +
+      pDst[n] = (q7_t) pSrc[n] >> 8;   0 <= n < blockSize.
+  
+ */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q15_to_q7( + const q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + + uint32_t blkCnt; /* loop counters */ + q15x8x2_t tmp; + q15_t const *pSrcVec; + q7x16_t vecDst; + + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* C = (q7_t) A >> 8 */ + /* convert from q15 to q7 and then store the results in the destination buffer */ + tmp = vld2q(pSrcVec); + pSrcVec += 16; + vecDst = vqshrnbq_n_s16(vecDst, tmp.val[0], 8); + vecDst = vqshrntq_n_s16(vecDst, tmp.val[1], 8); + vst1q(pDst, vecDst); + pDst += 16; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* C = (q7_t) A >> 8 */ + + /* Convert from q15 to q7 and store result in destination buffer */ + *pDst++ = (q7_t) (*pSrcVec++ >> 8); + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_q15_to_q7( + const q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q15_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in1, in2; + q31_t out1, out2; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q7_t) A >> 8 */ + + /* Convert from q15 to q7 and store result in destination buffer */ +#if defined (ARM_MATH_DSP) + + in1 = read_q15x2_ia (&pIn); + in2 = read_q15x2_ia (&pIn); + +#ifndef ARM_MATH_BIG_ENDIAN + + out1 = __PKHTB(in2, in1, 16); + out2 = __PKHBT(in2, in1, 16); + +#else + + out1 = __PKHTB(in1, in2, 16); + out2 = __PKHBT(in1, in2, 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* rotate packed value by 24 */ + out2 = ((uint32_t) out2 << 8) | ((uint32_t) out2 >> 24); + + /* anding with 0xff00ff00 to get two 8 bit values */ + out1 = out1 & 0xFF00FF00; + /* anding with 0x00ff00ff to get two 8 bit values */ + out2 = out2 & 0x00FF00FF; + + /* oring two values(contains two 8 bit values) to get four packed 8 bit values */ + out1 = out1 | out2; + + /* store 4 samples at a time to destiantion buffer */ + write_q7x4_ia (&pDst, out1); + +#else + + *pDst++ = (q7_t) (*pIn++ >> 8); + *pDst++ = (q7_t) (*pIn++ >> 8); + *pDst++ = (q7_t) (*pIn++ >> 8); + *pDst++ = (q7_t) (*pIn++ >> 8); + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q7_t) A >> 8 */ + + /* Convert from q15 to q7 and store result in destination buffer */ + *pDst++ = (q7_t) (*pIn++ >> 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of q15_to_x group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c new file mode 100644 index 00000000..ce7ce422 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c @@ -0,0 +1,202 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q31_to_float.c + * Description: Converts the elements of the Q31 vector to floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + * @defgroup q31_to_x Convert 32-bit fixed point value + */ + +/** + @addtogroup q31_to_x + @{ + */ + +/** + @brief Converts the elements of the Q31 vector to floating-point vector. + @param[in] pSrc points to the Q31 input vector + @param[out] pDst points to the floating-point output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: +
+      pDst[n] = (float32_t) pSrc[n] / 2147483648;   0 <= n < blockSize.
+  
+ */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecDst; + q31_t const *pSrcVec; + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + /* convert from q31 to float and then store the results in the destination buffer */ + vecDst = vld1q(pSrcVec); + pSrcVec += 4; + vstrwq(pDst, vcvtq_n_f32_s32(vecDst, 31)); + pDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + + /* Convert from q31 to float and store result in destination buffer */ + *pDst++ = ((float32_t) *pSrcVec++ / 2147483648.0f); + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + int32x4_t inV; + float32x4_t outV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + /* Convert from q31 to float and then store the results in the destination buffer */ + inV = vld1q_s32(pIn); + pIn += 4; + + outV = vcvtq_n_f32_s32(inV,31); + + vst1q_f32(pDst, outV); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + /* Convert from q31 to float and then store the results in the destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 2147483648.0f); + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + + /* Convert from q31 to float and store result in destination buffer */ + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + + /* Convert from q31 to float and store result in destination buffer */ + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of q31_to_x group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c new file mode 100644 index 00000000..a25a2bb1 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c @@ -0,0 +1,181 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q31_to_q15.c + * Description: Converts the elements of the Q31 vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q31_to_x + @{ + */ + +/** + @brief Converts the elements of the Q31 vector to Q15 vector. + @param[in] pSrc points to the Q31 input vector + @param[out] pDst points to the Q15 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: +
+      pDst[n] = (q15_t) pSrc[n] >> 16;   0 <= n < blockSize.
+  
+ */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q31_to_q15( + const q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4x2_t tmp; + q15x8_t vecDst; + q31_t const *pSrcVec; + + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* C = (q15_t) A >> 16 */ + /* convert from q31 to q15 and then store the results in the destination buffer */ + tmp = vld2q(pSrcVec); + pSrcVec += 8; + vecDst = vshrnbq_n_s32(vecDst, tmp.val[0], 16); + vecDst = vshrntq_n_s32(vecDst, tmp.val[1], 16); + vst1q(pDst, vecDst); + pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = blockSize & 7; + while (blkCnt > 0U) + { + /* C = (q15_t) (A >> 16) */ + + /* Convert from q31 to q15 and store result in destination buffer */ + *pDst++ = (q15_t) (*pSrcVec++ >> 16); + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_q31_to_q15( + const q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q31_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in1, in2, in3, in4; + q31_t out1, out2; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q15_t) (A >> 16) */ + + /* Convert from q31 to q15 and store result in destination buffer */ +#if defined (ARM_MATH_DSP) + + in1 = *pIn++; + in2 = *pIn++; + in3 = *pIn++; + in4 = *pIn++; + + /* pack two higher 16-bit values from two 32-bit values */ +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __PKHTB(in2, in1, 16); + out2 = __PKHTB(in4, in3, 16); +#else + out1 = __PKHTB(in1, in2, 16); + out2 = __PKHTB(in3, in4, 16); +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + write_q15x2_ia (&pDst, out1); + write_q15x2_ia (&pDst, out2); + +#else + + *pDst++ = (q15_t) (*pIn++ >> 16); + *pDst++ = (q15_t) (*pIn++ >> 16); + *pDst++ = (q15_t) (*pIn++ >> 16); + *pDst++ = (q15_t) (*pIn++ >> 16); + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q15_t) (A >> 16) */ + + /* Convert from q31 to q15 and store result in destination buffer */ + *pDst++ = (q15_t) (*pIn++ >> 16); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of q31_to_x group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c new file mode 100644 index 00000000..16fbe186 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c @@ -0,0 +1,169 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q31_to_q7.c + * Description: Converts the elements of the Q31 vector to Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q31_to_x + @{ + */ + +/** + @brief Converts the elements of the Q31 vector to Q7 vector. + @param[in] pSrc points to the Q31 input vector + @param[out] pDst points to the Q7 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: +
+      pDst[n] = (q7_t) pSrc[n] >> 24;   0 <= n < blockSize.
+  
+ */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q31_to_q7( + const q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4x4_t tmp; + q15x8_t evVec, oddVec; + q7x16_t vecDst; + q31_t const *pSrcVec; + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + tmp = vld4q(pSrcVec); + pSrcVec += 16; + /* C = (q7_t) A >> 24 */ + /* convert from q31 to q7 and then store the results in the destination buffer */ + /* + * narrow and pack evens + */ + evVec = vshrnbq_n_s32(evVec, tmp.val[0], 16); + evVec = vshrntq_n_s32(evVec, tmp.val[2], 16); + /* + * narrow and pack odds + */ + oddVec = vshrnbq_n_s32(oddVec, tmp.val[1], 16); + oddVec = vshrntq_n_s32(oddVec, tmp.val[3], 16); + /* + * narrow & merge + */ + vecDst = vshrnbq_n_s16(vecDst, evVec, 8); + vecDst = vshrntq_n_s16(vecDst, oddVec, 8); + + vst1q(pDst, vecDst); + pDst += 16; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* C = (q7_t) (A >> 24) */ + + /* Convert from q31 to q7 and store result in destination buffer */ + *pDst++ = (q7_t) (*pSrcVec++ >> 24); + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_q31_to_q7( + const q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q31_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + + q7_t out1, out2, out3, out4; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q7_t) (A >> 24) */ + + /* Convert from q31 to q7 and store result in destination buffer */ + + out1 = (q7_t) (*pIn++ >> 24); + out2 = (q7_t) (*pIn++ >> 24); + out3 = (q7_t) (*pIn++ >> 24); + out4 = (q7_t) (*pIn++ >> 24); + write_q7x4_ia (&pDst, __PACKq7(out1, out2, out3, out4)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q7_t) (A >> 24) */ + + /* Convert from q31 to q7 and store result in destination buffer */ + *pDst++ = (q7_t) (*pIn++ >> 24); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of q31_to_x group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c new file mode 100644 index 00000000..9cbf8ad0 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c @@ -0,0 +1,218 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q7_to_float.c + * Description: Converts the elements of the Q7 vector to floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + * @defgroup q7_to_x Convert 8-bit fixed point value + */ + +/** + @addtogroup q7_to_x + @{ + */ + +/** + @brief Converts the elements of the Q7 vector to floating-point vector. + @param[in] pSrc points to the Q7 input vector + @param[out] pDst points to the floating-point output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: +
+      pDst[n] = (float32_t) pSrc[n] / 128;   0 <= n < blockSize.
+  
+ */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecDst; + q7_t const *pSrcVec; + + pSrcVec = (q7_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + /* convert from q7 to float and then store the results in the destination buffer */ + vecDst = vldrbq_s32(pSrcVec); + pSrcVec += 4; + vstrwq(pDst, vcvtq_n_f32_s32((int32x4_t)vecDst, 7)); + pDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C = (float32_t) A / 128 */ + + /* Convert from q7 to float and store result in destination buffer */ + *pDst++ = ((float32_t) * pSrcVec++ / 128.0f); + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +#if defined(ARM_MATH_NEON) +void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const q7_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + int8x16_t inV; + int16x8_t inVLO, inVHI; + int32x4_t inVLL, inVLH, inVHL, inVHH; + float32x4_t outV; + + blkCnt = blockSize >> 4U; + + /* Compute 16 outputs at a time. + ** a second loop below computes the remaining 1 to 15 samples. */ + while (blkCnt > 0U) + { + /* C = (float32_t) A / 128 */ + /* Convert from q7 to float and then store the results in the destination buffer */ + inV = vld1q_s8(pIn); + pIn += 16; + + inVLO = vmovl_s8(vget_low_s8(inV)); + inVHI = vmovl_s8(vget_high_s8(inV)); + + inVLL = vmovl_s16(vget_low_s16(inVLO)); + inVLH = vmovl_s16(vget_high_s16(inVLO)); + inVHL = vmovl_s16(vget_low_s16(inVHI)); + inVHH = vmovl_s16(vget_high_s16(inVHI)); + + outV = vcvtq_n_f32_s32(inVLL,7); + vst1q_f32(pDst, outV); + pDst += 4; + + outV = vcvtq_n_f32_s32(inVLH,7); + vst1q_f32(pDst, outV); + pDst += 4; + + outV = vcvtq_n_f32_s32(inVHL,7); + vst1q_f32(pDst, outV); + pDst += 4; + + outV = vcvtq_n_f32_s32(inVHH,7); + vst1q_f32(pDst, outV); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 16, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 0xF; + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 128 */ + /* Convert from q7 to float and then store the results in the destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 128.0f); + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q7_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 128 */ + + /* Convert from q7 to float and store result in destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 128.0f); + *pDst++ = ((float32_t) * pIn++ / 128.0f); + *pDst++ = ((float32_t) * pIn++ / 128.0f); + *pDst++ = ((float32_t) * pIn++ / 128.0f); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 128 */ + + /* Convert from q7 to float and store result in destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 128.0f); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of q7_to_x group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c new file mode 100644 index 00000000..be525316 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c @@ -0,0 +1,188 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q7_to_q15.c + * Description: Converts the elements of the Q7 vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q7_to_x + @{ + */ + +/** + @brief Converts the elements of the Q7 vector to Q15 vector. + @param[in] pSrc points to the Q7 input vector + @param[out] pDst points to the Q15 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: +
+      pDst[n] = (q15_t) pSrc[n] << 8;   0 <= n < blockSize.
+  
+ */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q7_to_q15( + const q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + + uint32_t blkCnt; /* loop counters */ + q15x8_t vecDst; + q7_t const *pSrcVec; + + + pSrcVec = (q7_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + /* load q7 + 32-bit widening */ + vecDst = vldrbq_s16(pSrcVec); + pSrcVec += 8; + vecDst = vecDst << 8; + vstrhq(pDst, vecDst); + pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + blkCnt = blockSize & 7; + while (blkCnt > 0U) + { + /* C = (q15_t) A << 8 */ + + /* Convert from q7 to q15 and store result in destination buffer */ + *pDst++ = (q15_t) * pSrcVec++ << 8; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#else +void arm_q7_to_q15( + const q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q7_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in; + q31_t in1, in2; + q31_t out1, out2; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q15_t) A << 8 */ + + /* Convert from q7 to q15 and store result in destination buffer */ +#if defined (ARM_MATH_DSP) + + in = read_q7x4_ia (&pIn); + + /* rotatate in by 8 and extend two q7_t values to q15_t values */ + in1 = __SXTB16(__ROR(in, 8)); + + /* extend remainig two q7_t values to q15_t values */ + in2 = __SXTB16(in); + + in1 = in1 << 8U; + in2 = in2 << 8U; + + in1 = in1 & 0xFF00FF00; + in2 = in2 & 0xFF00FF00; + +#ifndef ARM_MATH_BIG_ENDIAN + out2 = __PKHTB(in1, in2, 16); + out1 = __PKHBT(in2, in1, 16); +#else + out1 = __PKHTB(in1, in2, 16); + out2 = __PKHBT(in2, in1, 16); +#endif + + write_q15x2_ia (&pDst, out1); + write_q15x2_ia (&pDst, out2); + +#else + + *pDst++ = (q15_t) *pIn++ << 8; + *pDst++ = (q15_t) *pIn++ << 8; + *pDst++ = (q15_t) *pIn++ << 8; + *pDst++ = (q15_t) *pIn++ << 8; + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q15_t) A << 8 */ + + /* Convert from q7 to q15 and store result in destination buffer */ + *pDst++ = (q15_t) * pIn++ << 8; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of q7_to_x group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c new file mode 100644 index 00000000..01d5f2b6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c @@ -0,0 +1,164 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q7_to_q31.c + * Description: Converts the elements of the Q7 vector to Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q7_to_x + @{ + */ + +/** + @brief Converts the elements of the Q7 vector to Q31 vector. + @param[in] pSrc points to the Q7 input vector + @param[out] pDst points to the Q31 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: +
+      pDst[n] = (q31_t) pSrc[n] << 24;   0 <= n < blockSize.
+  
+ */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q7_to_q31( + const q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + q31x4_t vecDst; + + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + + /* C = (q31_t)A << 16 */ + /* convert from q15 to q31 and then store the results in the destination buffer */ + /* load q15 + 32-bit widening */ + vecDst = vldrbq_s32((q7_t const *) pSrc); + vecDst = vshlq_n(vecDst, 24); + vstrwq_s32(pDst, vecDst); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pDst += 4; + pSrc += 4; + blkCnt --; + } + + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C = (q31_t) A << 24 */ + + /* Convert from q7 to q31 and store result in destination buffer */ + *pDst++ = (q31_t) *pSrc++ << 24; + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_q7_to_q31( + const q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q7_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + + q31_t in; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q31_t) A << 24 */ + + /* Convert from q7 to q31 and store result in destination buffer */ + in = read_q7x4_ia (&pIn); + +#ifndef ARM_MATH_BIG_ENDIAN + + *pDst++ = (__ROR(in, 8)) & 0xFF000000; + *pDst++ = (__ROR(in, 16)) & 0xFF000000; + *pDst++ = (__ROR(in, 24)) & 0xFF000000; + *pDst++ = (in & 0xFF000000); + +#else + + *pDst++ = (in & 0xFF000000); + *pDst++ = (__ROR(in, 24)) & 0xFF000000; + *pDst++ = (__ROR(in, 16)) & 0xFF000000; + *pDst++ = (__ROR(in, 8)) & 0xFF000000; + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q31_t) A << 24 */ + + /* Convert from q7 to q31 and store result in destination buffer */ + *pDst++ = (q31_t) * pIn++ << 24; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of q7_to_x group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c new file mode 100644 index 00000000..c6c44d96 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c @@ -0,0 +1,181 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quick_sort_f32.c + * Description: Floating point quick sort + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_sorting.h" + +static uint32_t arm_quick_sort_partition_f32(float32_t *pSrc, int32_t first, int32_t last, uint8_t dir) +{ + /* This function will be called */ + int32_t i, j, pivot_index; + float32_t pivot; + float32_t temp; + + /* The first element is the pivot */ + pivot_index = first; + pivot = pSrc[pivot_index]; + + /* Initialize indices for do-while loops */ + i = first - 1; + j = last + 1; + + while(i < j) + { + /* The loop will stop as soon as the indices i and j cross each other. + * + * This event will happen surely since the values of the indices are incremented and + * decrement in the do-while loops that are executed at least once. + * It is impossible to loop forever inside the do-while loops since the pivot is + * always an element of the array and the conditions cannot be always true (at least + * the i-th or the j-th element will be equal to the pivot-th element). + * For example, in the extreme case of an ordered array the do-while loop related to i will stop + * at the first iteration (because pSrc[i]=pSrc[pivot] already), and the loop related to j + * will stop after (last-first) iterations (when j=pivot=i=first). j is returned and + * j+1 is going to be used as pivot by other calls of the function, until j=pivot=last. */ + + /* Move indices to the right and to the left */ + if(dir) + { + /* Compare left elements with pivot */ + do + { + i++; + } while (pSrc[i] < pivot && i pivot); + } + else + { + /* Compare left elements with pivot */ + do + { + i++; + } while (pSrc[i] > pivot && i Swap */ + temp=pSrc[i]; + pSrc[i]=pSrc[j]; + pSrc[j]=temp; + } + } + + return j; +} + +static void arm_quick_sort_core_f32(float32_t *pSrc, int32_t first, int32_t last, uint8_t dir) +{ + /* If the array [first ... last] has more than one element */ + if(firstdir); + /* The previous function could be called recursively a maximum + * of (blockSize-1) times, generating a stack consumption of 4*(blockSize-1) bytes. */ +} + +/** + @} end of Sorting group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c new file mode 100644 index 00000000..ad534bc0 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c @@ -0,0 +1,107 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_selection_sort_f32.c + * Description: Floating point selection sort + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_sorting.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + +/** + * @private + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * + * @par Algorithm + * The Selection sort algorithm is a comparison algorithm that + * divides the input array into a sorted and an unsorted sublist + * (initially the sorted sublist is empty and the unsorted sublist + * is the input array), looks for the smallest (or biggest) + * element in the unsorted sublist, swapping it with the leftmost + * one, and moving the sublists boundary one element to the right. + * + * @par It's an in-place algorithm. In order to obtain an out-of-place + * function, a memcpy of the source vector is performed. + */ + +void arm_selection_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t i, j, k; + uint8_t dir = S->dir; + float32_t temp; + + float32_t * pA; + + if(pSrc != pDst) // out-of-place + { + memcpy(pDst, pSrc, blockSize*sizeof(float32_t) ); + pA = pDst; + } + else + pA = pSrc; + + /* Move the boundary one element to the right */ + for (i=0; ialg) + { + case ARM_SORT_BITONIC: + arm_bitonic_sort_f32(S, pSrc, pDst, blockSize); + break; + + case ARM_SORT_BUBBLE: + arm_bubble_sort_f32(S, pSrc, pDst, blockSize); + break; + + case ARM_SORT_HEAP: + arm_heap_sort_f32(S, pSrc, pDst, blockSize); + break; + + case ARM_SORT_INSERTION: + arm_insertion_sort_f32(S, pSrc, pDst, blockSize); + break; + + case ARM_SORT_QUICK: + arm_quick_sort_f32(S, pSrc, pDst, blockSize); + break; + + case ARM_SORT_SELECTION: + arm_selection_sort_f32(S, pSrc, pDst, blockSize); + break; + } +} + +/** + @} end of Sorting group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c new file mode 100644 index 00000000..72ad9c55 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c @@ -0,0 +1,54 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sort_init_f32.c + * Description: Floating point sort initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_sorting.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] alg Selected algorithm. + * @param[in] dir Sorting order. + */ +void arm_sort_init_f32(arm_sort_instance_f32 * S, arm_sort_alg alg, arm_sort_dir dir) +{ + S->alg = alg; + S->dir = dir; +} + +/** + @} end of Sorting group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f16.c new file mode 100644 index 00000000..f9aae6b0 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f16.c @@ -0,0 +1,146 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_weighted_sum_f16.c + * Description: Weighted Sum + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include + +#include "dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupSupport + */ + +/** + @defgroup weightedsum Weighted Sum + + Weighted sum of values + */ + + +/** + * @addtogroup weightedsum + * @{ + */ + + +/** + * @brief Weighted sum + * + * + * @param[in] *in Array of input values. + * @param[in] *weigths Weights + * @param[in] blockSize Number of samples in the input array. + * @return Weighted sum + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +float16_t arm_weighted_sum_f16(const float16_t *in,const float16_t *weigths, uint32_t blockSize) +{ + _Float16 accum1, accum2; + float16x8_t accum1V, accum2V; + float16x8_t inV, wV; + const float16_t *pIn, *pW; + uint32_t blkCnt; + + + pIn = in; + pW = weigths; + + + accum1V = vdupq_n_f16(0.0f16); + accum2V = vdupq_n_f16(0.0f16); + + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + inV = vld1q(pIn); + wV = vld1q(pW); + + pIn += 4; + pW += 4; + + accum1V = vfmaq(accum1V, inV, wV); + accum2V = vaddq(accum2V, wV); + blkCnt--; + } + + accum1 = vecAddAcrossF16Mve(accum1V); + accum2 = vecAddAcrossF16Mve(accum2V); + + blkCnt = blockSize & 7; + while(blkCnt > 0) + { + accum1 += (_Float16)*pIn++ * (_Float16)*pW; + accum2 += (_Float16)*pW++; + blkCnt--; + } + + + return (accum1 / accum2); +} + +#else + +float16_t arm_weighted_sum_f16(const float16_t *in, const float16_t *weigths, uint32_t blockSize) +{ + + _Float16 accum1, accum2; + const float16_t *pIn, *pW; + uint32_t blkCnt; + + + pIn = in; + pW = weigths; + + accum1=0.0f16; + accum2=0.0f16; + + blkCnt = blockSize; + while(blkCnt > 0) + { + accum1 += (_Float16)*pIn++ * (_Float16)*pW; + accum2 += (_Float16)*pW++; + blkCnt--; + } + + return(accum1 / accum2); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of weightedsum group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c new file mode 100644 index 00000000..dd378615 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c @@ -0,0 +1,187 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_weighted_sum_f32.c + * Description: Weighted Sum + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include + +#include "dsp/support_functions.h" + +/** + * @addtogroup weightedsum + * @{ + */ + + +/** + * @brief Weighted sum + * + * + * @param[in] *in Array of input values. + * @param[in] *weigths Weights + * @param[in] blockSize Number of samples in the input array. + * @return Weighted sum + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +float32_t arm_weighted_sum_f32(const float32_t *in,const float32_t *weigths, uint32_t blockSize) +{ + float32_t accum1, accum2; + f32x4_t accum1V, accum2V; + f32x4_t inV, wV; + const float32_t *pIn, *pW; + uint32_t blkCnt; + + + pIn = in; + pW = weigths; + + + accum1V = vdupq_n_f32(0.0); + accum2V = vdupq_n_f32(0.0); + + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + inV = vld1q(pIn); + wV = vld1q(pW); + + pIn += 4; + pW += 4; + + accum1V = vfmaq(accum1V, inV, wV); + accum2V = vaddq(accum2V, wV); + blkCnt--; + } + + accum1 = vecAddAcrossF32Mve(accum1V); + accum2 = vecAddAcrossF32Mve(accum2V); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + accum1 += *pIn++ * *pW; + accum2 += *pW++; + blkCnt--; + } + + + return (accum1 / accum2); +} + +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" +float32_t arm_weighted_sum_f32(const float32_t *in,const float32_t *weigths, uint32_t blockSize) +{ + + float32_t accum1, accum2; + float32x4_t accum1V, accum2V; + float32x2_t tempV; + + float32x4_t inV,wV; + + const float32_t *pIn, *pW; + uint32_t blkCnt; + + + pIn = in; + pW = weigths; + + accum1=0.0f; + accum2=0.0f; + + accum1V = vdupq_n_f32(0.0f); + accum2V = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + inV = vld1q_f32(pIn); + wV = vld1q_f32(pW); + + pIn += 4; + pW += 4; + + accum1V = vmlaq_f32(accum1V,inV,wV); + accum2V = vaddq_f32(accum2V,wV); + blkCnt--; + } + + tempV = vpadd_f32(vget_low_f32(accum1V),vget_high_f32(accum1V)); + accum1 = vget_lane_f32(tempV, 0) + vget_lane_f32(tempV, 1); + + tempV = vpadd_f32(vget_low_f32(accum2V),vget_high_f32(accum2V)); + accum2 = vget_lane_f32(tempV, 0) + vget_lane_f32(tempV, 1); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + accum1 += *pIn++ * *pW; + accum2 += *pW++; + blkCnt--; + } + + + return(accum1 / accum2); +} +#else +float32_t arm_weighted_sum_f32(const float32_t *in, const float32_t *weigths, uint32_t blockSize) +{ + + float32_t accum1, accum2; + const float32_t *pIn, *pW; + uint32_t blkCnt; + + + pIn = in; + pW = weigths; + + accum1=0.0f; + accum2=0.0f; + + blkCnt = blockSize; + while(blkCnt > 0) + { + accum1 += *pIn++ * *pW; + accum2 += *pW++; + blkCnt--; + } + + return(accum1 / accum2); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of weightedsum group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/CMakeLists.txt new file mode 100644 index 00000000..e598f822 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/CMakeLists.txt @@ -0,0 +1,213 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPTransform) + +include(configLib) +include(configDsp) + +add_library(CMSISDSPTransform STATIC) +configLib(CMSISDSPTransform ${ROOT}) +configDsp(CMSISDSPTransform ${ROOT}) + +include(fft) +fft(CMSISDSPTransform) + +if (CONFIGTABLE AND ALLFFT) +target_compile_definitions(CMSISDSPTransform PUBLIC ARM_ALL_FFT_TABLES) +endif() + +target_sources(CMSISDSPTransform PRIVATE arm_bitreversal.c) +target_sources(CMSISDSPTransform PRIVATE arm_bitreversal2.c) + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPTransform PRIVATE arm_bitreversal_f16.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR CFFT_F32_16 OR CFFT_F32_32 OR CFFT_F32_64 OR CFFT_F32_128 OR CFFT_F32_256 OR CFFT_F32_512 + OR CFFT_F32_1024 OR CFFT_F32_2048 OR CFFT_F32_4096) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix2_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix8_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_f32.c) +endif() + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +if (NOT CONFIGTABLE OR ALLFFT OR CFFT_F16_16 OR CFFT_F16_32 OR CFFT_F16_64 OR CFFT_F16_128 OR CFFT_F16_256 OR CFFT_F16_512 + OR CFFT_F16_1024 OR CFFT_F16_2048 OR CFFT_F16_4096) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix2_f16.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_f16.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_f16.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_f16.c) +endif() +endif() + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +if (NOT CONFIGTABLE OR ALLFFT OR RFFT_F16_128 OR RFFT_F16_512 OR RFFT_F16_2048 OR RFFT_F16_8192) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_init_f16.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_f16.c) +endif() +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR CFFT_F64_16 OR CFFT_F64_32 OR CFFT_F64_64 OR CFFT_F64_128 OR CFFT_F64_256 OR CFFT_F64_512 + OR CFFT_F64_1024 OR CFFT_F64_2048 OR CFFT_F64_4096) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_f64.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_f64.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR CFFT_Q15_16 OR CFFT_Q15_32 OR CFFT_Q15_64 OR CFFT_Q15_128 OR CFFT_Q15_256 OR CFFT_Q15_512 + OR CFFT_Q15_1024 OR CFFT_Q15_2048 OR CFFT_Q15_4096) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix2_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_q15.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR CFFT_Q31_16 OR CFFT_Q31_32 OR CFFT_Q31_64 OR CFFT_Q31_128 OR CFFT_Q31_256 OR CFFT_Q31_512 + OR CFFT_Q31_1024 OR CFFT_Q31_2048 OR CFFT_Q31_4096) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix2_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_q31.c) +endif() + + +if (NOT CONFIGTABLE OR ALLFFT OR DCT4_F32_128 OR DCT4_F32_512 OR DCT4_F32_2048 OR DCT4_F32_8192) +target_sources(CMSISDSPTransform PRIVATE arm_dct4_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_dct4_init_f32.c) + +target_sources(CMSISDSPTransform PRIVATE arm_rfft_init_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_init_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_f32.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR DCT4_Q31_128 OR DCT4_Q31_512 OR DCT4_Q31_2048 OR DCT4_Q31_8192) +target_sources(CMSISDSPTransform PRIVATE arm_dct4_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_dct4_init_q31.c) + +target_sources(CMSISDSPTransform PRIVATE arm_rfft_init_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_init_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_q31.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR ALLFFT OR DCT4_Q15_128 OR DCT4_Q15_512 OR DCT4_Q15_2048 OR DCT4_Q15_8192) +target_sources(CMSISDSPTransform PRIVATE arm_dct4_init_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_dct4_q15.c) + +target_sources(CMSISDSPTransform PRIVATE arm_rfft_init_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_init_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_q15.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR RFFT_FAST_F32_32 OR RFFT_FAST_F32_64 OR RFFT_FAST_F32_128 + OR RFFT_FAST_F32_256 OR RFFT_FAST_F32_512 OR RFFT_FAST_F32_1024 OR RFFT_FAST_F32_2048 + OR RFFT_FAST_F32_4096 ) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_fast_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_fast_init_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix8_f32.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR RFFT_FAST_F64_32 OR RFFT_FAST_F64_64 OR RFFT_FAST_F64_128 + OR RFFT_FAST_F64_256 OR RFFT_FAST_F64_512 OR RFFT_FAST_F64_1024 OR RFFT_FAST_F64_2048 + OR RFFT_FAST_F64_4096 ) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_fast_f64.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_fast_init_f64.c) +endif() + +if ((NOT DISABLEFLOAT16)) +if (NOT CONFIGTABLE OR ALLFFT OR RFFT_FAST_F16_32 OR RFFT_FAST_F16_64 OR RFFT_FAST_F16_128 + OR RFFT_FAST_F16_256 OR RFFT_FAST_F16_512 OR RFFT_FAST_F16_1024 OR RFFT_FAST_F16_2048 + OR RFFT_FAST_F16_4096 ) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_fast_f16.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_fast_init_f16.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_f16.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_f16.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix8_f16.c) +endif() +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR RFFT_F32_128 OR RFFT_F32_512 OR RFFT_F32_2048 OR RFFT_F32_8192) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_init_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_init_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_f32.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR RFFT_Q15_32 OR RFFT_Q15_64 OR RFFT_Q15_128 OR RFFT_Q15_256 + OR RFFT_Q15_512 OR RFFT_Q15_1024 OR RFFT_Q15_2048 OR RFFT_Q15_4096 OR RFFT_Q15_8192) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_init_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_q15.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR RFFT_Q31_32 OR RFFT_Q31_64 OR RFFT_Q31_128 OR RFFT_Q31_256 + OR RFFT_Q31_512 OR RFFT_Q31_1024 OR RFFT_Q31_2048 OR RFFT_Q31_4096 OR RFFT_Q31_8192) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_init_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_q31.c) +endif() + +if (WRAPPER OR ARM_CFFT_RADIX2_Q15) + target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix2_init_q15.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR ARM_CFFT_RADIX4_Q15) + target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_init_q15.c) +endif() + +if (WRAPPER OR ARM_CFFT_RADIX2_Q31) + target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix2_init_q31.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR ARM_CFFT_RADIX4_Q31) + target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_init_q31.c) +endif() + +# For scipy or wrappers or benchmarks +if (WRAPPER) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix2_init_f32.c) +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix2_init_f16.c) +endif() + + target_compile_definitions(CMSISDSPTransform PUBLIC ARM_TABLE_BITREV_1024) + target_compile_definitions(CMSISDSPTransform PUBLIC ARM_TABLE_TWIDDLECOEF_F32_4096) + target_compile_definitions(CMSISDSPTransform PUBLIC ARM_TABLE_TWIDDLECOEF_Q31_4096) + target_compile_definitions(CMSISDSPTransform PUBLIC ARM_TABLE_TWIDDLECOEF_Q15_4096) +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) + target_compile_definitions(CMSISDSPTransform PUBLIC ARM_TABLE_TWIDDLECOEF_F16_4096) +endif() +endif() + +target_sources(CMSISDSPTransform PRIVATE arm_mfcc_init_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_mfcc_f32.c) + +target_sources(CMSISDSPTransform PRIVATE arm_mfcc_init_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_mfcc_q31.c) + +target_sources(CMSISDSPTransform PRIVATE arm_mfcc_init_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_mfcc_q15.c) + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPTransform PRIVATE arm_mfcc_init_f16.c) +target_sources(CMSISDSPTransform PRIVATE arm_mfcc_f16.c) +endif() + +### Includes +target_include_directories(CMSISDSPTransform PUBLIC "${DSP}/Include") + + + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c new file mode 100644 index 00000000..f327801e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c @@ -0,0 +1,83 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: TransformFunctions.c + * Description: Combination of all transform function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_bitreversal.c" +#include "arm_bitreversal2.c" +#include "arm_cfft_f32.c" +#include "arm_cfft_f64.c" +#include "arm_cfft_q15.c" +#include "arm_cfft_q31.c" +#include "arm_cfft_init_f32.c" +#include "arm_cfft_init_f64.c" +#include "arm_cfft_init_q15.c" +#include "arm_cfft_init_q31.c" +#include "arm_cfft_radix2_f32.c" +#include "arm_cfft_radix2_q15.c" +#include "arm_cfft_radix2_q31.c" +#include "arm_cfft_radix4_f32.c" +#include "arm_cfft_radix4_q15.c" +#include "arm_cfft_radix4_q31.c" +#include "arm_cfft_radix8_f32.c" +#include "arm_rfft_fast_f32.c" +#include "arm_rfft_fast_f64.c" +#include "arm_rfft_fast_init_f32.c" +#include "arm_rfft_fast_init_f64.c" + +#include "arm_mfcc_init_f32.c" +#include "arm_mfcc_f32.c" + +#include "arm_mfcc_init_q31.c" +#include "arm_mfcc_q31.c" + +#include "arm_mfcc_init_q15.c" +#include "arm_mfcc_q15.c" + +/* Deprecated */ + +#include "arm_dct4_f32.c" +#include "arm_dct4_init_f32.c" +#include "arm_dct4_init_q15.c" +#include "arm_dct4_init_q31.c" +#include "arm_dct4_q15.c" +#include "arm_dct4_q31.c" + +#include "arm_rfft_f32.c" +#include "arm_rfft_q15.c" +#include "arm_rfft_q31.c" + +#include "arm_rfft_init_f32.c" +#include "arm_rfft_init_q15.c" +#include "arm_rfft_init_q31.c" + +#include "arm_cfft_radix4_init_f32.c" +#include "arm_cfft_radix4_init_q15.c" +#include "arm_cfft_radix4_init_q31.c" + +#include "arm_cfft_radix2_init_f32.c" +#include "arm_cfft_radix2_init_q15.c" +#include "arm_cfft_radix2_init_q31.c" diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/TransformFunctionsF16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/TransformFunctionsF16.c new file mode 100644 index 00000000..b082d447 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/TransformFunctionsF16.c @@ -0,0 +1,44 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: TransformFunctionsF16.c + * Description: Combination of all transform function f16 source files. + * + * $Date: 20. April 2020 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_cfft_f16.c" +#include "arm_cfft_init_f16.c" +#include "arm_cfft_radix2_f16.c" +#include "arm_cfft_radix4_f16.c" +#include "arm_rfft_fast_init_f16.c" +#include "arm_rfft_fast_f16.c" +#include "arm_cfft_radix8_f16.c" + +#include "arm_bitreversal_f16.c" + +#include "arm_mfcc_init_f16.c" +#include "arm_mfcc_f16.c" + +/* Deprecated */ +#include "arm_cfft_radix2_init_f16.c" +#include "arm_cfft_radix4_init_f16.c" diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c new file mode 100644 index 00000000..687a9e86 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c @@ -0,0 +1,230 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_bitreversal.c + * Description: Bitreversal functions + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + + +/** + @brief In-place floating-point bit reversal function. + @param[in,out] pSrc points to in-place floating-point data buffer + @param[in] fftSize length of FFT + @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + @param[in] pBitRevTab points to bit reversal table + @return none + */ + +void arm_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab) +{ + uint16_t fftLenBy2, fftLenBy2p1; + uint16_t i, j; + float32_t in; + + /* Initializations */ + j = 0U; + fftLenBy2 = fftSize >> 1U; + fftLenBy2p1 = (fftSize >> 1U) + 1U; + + /* Bit Reversal Implementation */ + for (i = 0U; i <= (fftLenBy2 - 2U); i += 2U) + { + if (i < j) + { + /* pSrc[i] <-> pSrc[j]; */ + in = pSrc[2U * i]; + pSrc[2U * i] = pSrc[2U * j]; + pSrc[2U * j] = in; + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[(2U * i) + 1U]; + pSrc[(2U * i) + 1U] = pSrc[(2U * j) + 1U]; + pSrc[(2U * j) + 1U] = in; + + /* pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */ + in = pSrc[2U * (i + fftLenBy2p1)]; + pSrc[2U * (i + fftLenBy2p1)] = pSrc[2U * (j + fftLenBy2p1)]; + pSrc[2U * (j + fftLenBy2p1)] = in; + + /* pSrc[i+fftLenBy2p1+1U] <-> pSrc[j+fftLenBy2p1+1U] */ + in = pSrc[(2U * (i + fftLenBy2p1)) + 1U]; + pSrc[(2U * (i + fftLenBy2p1)) + 1U] = + pSrc[(2U * (j + fftLenBy2p1)) + 1U]; + pSrc[(2U * (j + fftLenBy2p1)) + 1U] = in; + + } + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[2U * (i + 1U)]; + pSrc[2U * (i + 1U)] = pSrc[2U * (j + fftLenBy2)]; + pSrc[2U * (j + fftLenBy2)] = in; + + /* pSrc[i+2U] <-> pSrc[j+2U] */ + in = pSrc[(2U * (i + 1U)) + 1U]; + pSrc[(2U * (i + 1U)) + 1U] = pSrc[(2U * (j + fftLenBy2)) + 1U]; + pSrc[(2U * (j + fftLenBy2)) + 1U] = in; + + /* Reading the index for the bit reversal */ + j = *pBitRevTab; + + /* Updating the bit reversal index depending on the fft length */ + pBitRevTab += bitRevFactor; + } +} + + +/** + @brief In-place Q31 bit reversal function. + @param[in,out] pSrc points to in-place Q31 data buffer. + @param[in] fftLen length of FFT. + @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void arm_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab) +{ + uint32_t fftLenBy2, fftLenBy2p1, i, j; + q31_t in; + + /* Initializations */ + j = 0U; + fftLenBy2 = fftLen / 2U; + fftLenBy2p1 = (fftLen / 2U) + 1U; + + /* Bit Reversal Implementation */ + for (i = 0U; i <= (fftLenBy2 - 2U); i += 2U) + { + if (i < j) + { + /* pSrc[i] <-> pSrc[j]; */ + in = pSrc[2U * i]; + pSrc[2U * i] = pSrc[2U * j]; + pSrc[2U * j] = in; + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[(2U * i) + 1U]; + pSrc[(2U * i) + 1U] = pSrc[(2U * j) + 1U]; + pSrc[(2U * j) + 1U] = in; + + /* pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */ + in = pSrc[2U * (i + fftLenBy2p1)]; + pSrc[2U * (i + fftLenBy2p1)] = pSrc[2U * (j + fftLenBy2p1)]; + pSrc[2U * (j + fftLenBy2p1)] = in; + + /* pSrc[i+fftLenBy2p1+1U] <-> pSrc[j+fftLenBy2p1+1U] */ + in = pSrc[(2U * (i + fftLenBy2p1)) + 1U]; + pSrc[(2U * (i + fftLenBy2p1)) + 1U] = + pSrc[(2U * (j + fftLenBy2p1)) + 1U]; + pSrc[(2U * (j + fftLenBy2p1)) + 1U] = in; + + } + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[2U * (i + 1U)]; + pSrc[2U * (i + 1U)] = pSrc[2U * (j + fftLenBy2)]; + pSrc[2U * (j + fftLenBy2)] = in; + + /* pSrc[i+2U] <-> pSrc[j+2U] */ + in = pSrc[(2U * (i + 1U)) + 1U]; + pSrc[(2U * (i + 1U)) + 1U] = pSrc[(2U * (j + fftLenBy2)) + 1U]; + pSrc[(2U * (j + fftLenBy2)) + 1U] = in; + + /* Reading the index for the bit reversal */ + j = *pBitRevTab; + + /* Updating the bit reversal index depending on the fft length */ + pBitRevTab += bitRevFactor; + } +} + + + +/** + @brief In-place Q15 bit reversal function. + @param[in,out] pSrc16 points to in-place Q15 data buffer + @param[in] fftLen length of FFT + @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void arm_bitreversal_q15( + q15_t * pSrc16, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab) +{ + q31_t *pSrc = (q31_t *) pSrc16; + q31_t in; + uint32_t fftLenBy2, fftLenBy2p1; + uint32_t i, j; + + /* Initializations */ + j = 0U; + fftLenBy2 = fftLen / 2U; + fftLenBy2p1 = (fftLen / 2U) + 1U; + + /* Bit Reversal Implementation */ + for (i = 0U; i <= (fftLenBy2 - 2U); i += 2U) + { + if (i < j) + { + /* pSrc[i] <-> pSrc[j]; */ + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[i]; + pSrc[i] = pSrc[j]; + pSrc[j] = in; + + /* pSrc[i + fftLenBy2p1] <-> pSrc[j + fftLenBy2p1]; */ + /* pSrc[i + fftLenBy2p1+1U] <-> pSrc[j + fftLenBy2p1+1U] */ + in = pSrc[i + fftLenBy2p1]; + pSrc[i + fftLenBy2p1] = pSrc[j + fftLenBy2p1]; + pSrc[j + fftLenBy2p1] = in; + } + + /* pSrc[i+1U] <-> pSrc[j+fftLenBy2]; */ + /* pSrc[i+2] <-> pSrc[j+fftLenBy2+1U] */ + in = pSrc[i + 1U]; + pSrc[i + 1U] = pSrc[j + fftLenBy2]; + pSrc[j + fftLenBy2] = in; + + /* Reading the index for the bit reversal */ + j = *pBitRevTab; + + /* Updating the bit reversal index depending on the fft length */ + pBitRevTab += bitRevFactor; + } +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S new file mode 100644 index 00000000..c16091b1 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S @@ -0,0 +1,216 @@ +;/* ---------------------------------------------------------------------- +; * Project: CMSIS DSP Library +; * Title: arm_bitreversal2.S +; * Description: arm_bitreversal_32 function done in assembly for maximum speed. +; * Called after doing an fft to reorder the output. +; * The function is loop unrolled by 2. arm_bitreversal_16 as well. +; * +; * $Date: 18. March 2019 +; * $Revision: V1.5.2 +; * +; * Target Processor: Cortex-M cores +; * -------------------------------------------------------------------- */ +;/* +; * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +#if defined ( __CC_ARM ) /* Keil */ + #define CODESECT AREA ||.text||, CODE, READONLY, ALIGN=2 + #define LABEL +#elif defined ( __IASMARM__ ) /* IAR */ + #define CODESECT SECTION `.text`:CODE + #define PROC + #define LABEL + #define ENDP + #define EXPORT PUBLIC +#elif defined ( __CSMC__ ) /* Cosmic */ + #define CODESECT switch .text + #define THUMB + #define EXPORT xdef + #define PROC : + #define LABEL : + #define ENDP + #define arm_bitreversal_32 _arm_bitreversal_32 +#elif defined ( __TI_ARM__ ) /* TI ARM */ + #define THUMB .thumb + #define CODESECT .text + #define EXPORT .global + #define PROC : .asmfunc + #define LABEL : + #define ENDP .endasmfunc + #define END +#elif defined ( __GNUC__ ) /* GCC */ + #define THUMB .thumb + #define CODESECT .section .text + #define EXPORT .global + #define PROC : + #define LABEL : + #define ENDP + #define END + + .syntax unified +#endif + + CODESECT + THUMB + +;/** +; @brief In-place bit reversal function. +; @param[in,out] pSrc points to the in-place buffer of unknown 32-bit data type +; @param[in] bitRevLen bit reversal table length +; @param[in] pBitRevTab points to bit reversal table +; @return none +; */ + EXPORT arm_bitreversal_32 + EXPORT arm_bitreversal_16 + +#if defined ( __CC_ARM ) /* Keil */ +#elif defined ( __IASMARM__ ) /* IAR */ +#elif defined ( __CSMC__ ) /* Cosmic */ +#elif defined ( __TI_ARM__ ) /* TI ARM */ +#elif defined ( __GNUC__ ) /* GCC */ + .type arm_bitreversal_16, %function + .type arm_bitreversal_32, %function +#endif + +#if defined (ARM_MATH_CM0_FAMILY) + +arm_bitreversal_32 PROC + ADDS r3,r1,#1 + PUSH {r4-r6} + ADDS r1,r2,#0 + LSRS r3,r3,#1 +arm_bitreversal_32_0 LABEL + LDRH r2,[r1,#2] + LDRH r6,[r1,#0] + ADD r2,r0,r2 + ADD r6,r0,r6 + LDR r5,[r2,#0] + LDR r4,[r6,#0] + STR r5,[r6,#0] + STR r4,[r2,#0] + LDR r5,[r2,#4] + LDR r4,[r6,#4] + STR r5,[r6,#4] + STR r4,[r2,#4] + ADDS r1,r1,#4 + SUBS r3,r3,#1 + BNE arm_bitreversal_32_0 + POP {r4-r6} + BX lr + ENDP + +arm_bitreversal_16 PROC + ADDS r3,r1,#1 + PUSH {r4-r6} + ADDS r1,r2,#0 + LSRS r3,r3,#1 +arm_bitreversal_16_0 LABEL + LDRH r2,[r1,#2] + LDRH r6,[r1,#0] + LSRS r2,r2,#1 + LSRS r6,r6,#1 + ADD r2,r0,r2 + ADD r6,r0,r6 + LDR r5,[r2,#0] + LDR r4,[r6,#0] + STR r5,[r6,#0] + STR r4,[r2,#0] + ADDS r1,r1,#4 + SUBS r3,r3,#1 + BNE arm_bitreversal_16_0 + POP {r4-r6} + BX lr + ENDP + +#else + +arm_bitreversal_32 PROC + ADDS r3,r1,#1 + CMP r3,#1 + IT LS + BXLS lr + PUSH {r4-r9} + ADDS r1,r2,#2 + LSRS r3,r3,#2 +arm_bitreversal_32_0 LABEL ;/* loop unrolled by 2 */ + LDRH r8,[r1,#4] + LDRH r9,[r1,#2] + LDRH r2,[r1,#0] + LDRH r12,[r1,#-2] + ADD r8,r0,r8 + ADD r9,r0,r9 + ADD r2,r0,r2 + ADD r12,r0,r12 + LDR r7,[r9,#0] + LDR r6,[r8,#0] + LDR r5,[r2,#0] + LDR r4,[r12,#0] + STR r6,[r9,#0] + STR r7,[r8,#0] + STR r5,[r12,#0] + STR r4,[r2,#0] + LDR r7,[r9,#4] + LDR r6,[r8,#4] + LDR r5,[r2,#4] + LDR r4,[r12,#4] + STR r6,[r9,#4] + STR r7,[r8,#4] + STR r5,[r12,#4] + STR r4,[r2,#4] + ADDS r1,r1,#8 + SUBS r3,r3,#1 + BNE arm_bitreversal_32_0 + POP {r4-r9} + BX lr + ENDP + +arm_bitreversal_16 PROC + ADDS r3,r1,#1 + CMP r3,#1 + IT LS + BXLS lr + PUSH {r4-r9} + ADDS r1,r2,#2 + LSRS r3,r3,#2 +arm_bitreversal_16_0 LABEL ;/* loop unrolled by 2 */ + LDRH r8,[r1,#4] + LDRH r9,[r1,#2] + LDRH r2,[r1,#0] + LDRH r12,[r1,#-2] + ADD r8,r0,r8,LSR #1 + ADD r9,r0,r9,LSR #1 + ADD r2,r0,r2,LSR #1 + ADD r12,r0,r12,LSR #1 + LDR r7,[r9,#0] + LDR r6,[r8,#0] + LDR r5,[r2,#0] + LDR r4,[r12,#0] + STR r6,[r9,#0] + STR r7,[r8,#0] + STR r5,[r12,#0] + STR r4,[r2,#0] + ADDS r1,r1,#8 + SUBS r3,r3,#1 + BNE arm_bitreversal_16_0 + POP {r4-r9} + BX lr + ENDP + +#endif + + END diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.c new file mode 100644 index 00000000..77fac1f8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_bitreversal2.c + * Description: Bitreversal functions + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + + +/** + @brief In-place 64 bit reversal function. + @param[in,out] pSrc points to in-place buffer of unknown 64-bit data type + @param[in] bitRevLen bit reversal table length + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void arm_bitreversal_64( + uint64_t *pSrc, + const uint16_t bitRevLen, + const uint16_t *pBitRevTab) +{ + uint64_t a, b, i, tmp; + + for (i = 0; i < bitRevLen; ) + { + a = pBitRevTab[i ] >> 2; + b = pBitRevTab[i + 1] >> 2; + + //real + tmp = pSrc[a]; + pSrc[a] = pSrc[b]; + pSrc[b] = tmp; + + //complex + tmp = pSrc[a+1]; + pSrc[a+1] = pSrc[b+1]; + pSrc[b+1] = tmp; + + i += 2; + } +} + +/** + @brief In-place 32 bit reversal function. + @param[in,out] pSrc points to in-place buffer of unknown 32-bit data type + @param[in] bitRevLen bit reversal table length + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void arm_bitreversal_32( + uint32_t *pSrc, + const uint16_t bitRevLen, + const uint16_t *pBitRevTab) +{ + uint32_t a, b, i, tmp; + + for (i = 0; i < bitRevLen; ) + { + a = pBitRevTab[i ] >> 2; + b = pBitRevTab[i + 1] >> 2; + + //real + tmp = pSrc[a]; + pSrc[a] = pSrc[b]; + pSrc[b] = tmp; + + //complex + tmp = pSrc[a+1]; + pSrc[a+1] = pSrc[b+1]; + pSrc[b+1] = tmp; + + i += 2; + } +} + + +/** + @brief In-place 16 bit reversal function. + @param[in,out] pSrc points to in-place buffer of unknown 16-bit data type + @param[in] bitRevLen bit reversal table length + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void arm_bitreversal_16( + uint16_t *pSrc, + const uint16_t bitRevLen, + const uint16_t *pBitRevTab) +{ + uint16_t a, b, i, tmp; + + for (i = 0; i < bitRevLen; ) + { + a = pBitRevTab[i ] >> 2; + b = pBitRevTab[i + 1] >> 2; + + //real + tmp = pSrc[a]; + pSrc[a] = pSrc[b]; + pSrc[b] = tmp; + + //complex + tmp = pSrc[a+1]; + pSrc[a+1] = pSrc[b+1]; + pSrc[b+1] = tmp; + + i += 2; + } +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal_f16.c new file mode 100644 index 00000000..2e646368 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal_f16.c @@ -0,0 +1,102 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_bitreversal_f16.c + * Description: Bitreversal functions + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" + +/* +* @brief In-place bit reversal function. +* @param[in, out] *pSrc points to the in-place buffer of floating-point data type. +* @param[in] fftSize length of the FFT. +* @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table. +* @param[in] *pBitRevTab points to the bit reversal table. +* @return none. +*/ + +#if defined(ARM_FLOAT16_SUPPORTED) + +void arm_bitreversal_f16( +float16_t * pSrc, +uint16_t fftSize, +uint16_t bitRevFactor, +const uint16_t * pBitRevTab) +{ + uint16_t fftLenBy2, fftLenBy2p1; + uint16_t i, j; + float16_t in; + + /* Initializations */ + j = 0U; + fftLenBy2 = fftSize >> 1U; + fftLenBy2p1 = (fftSize >> 1U) + 1U; + + /* Bit Reversal Implementation */ + for (i = 0U; i <= (fftLenBy2 - 2U); i += 2U) + { + if (i < j) + { + /* pSrc[i] <-> pSrc[j]; */ + in = pSrc[2U * i]; + pSrc[2U * i] = pSrc[2U * j]; + pSrc[2U * j] = in; + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[(2U * i) + 1U]; + pSrc[(2U * i) + 1U] = pSrc[(2U * j) + 1U]; + pSrc[(2U * j) + 1U] = in; + + /* pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */ + in = pSrc[2U * (i + fftLenBy2p1)]; + pSrc[2U * (i + fftLenBy2p1)] = pSrc[2U * (j + fftLenBy2p1)]; + pSrc[2U * (j + fftLenBy2p1)] = in; + + /* pSrc[i+fftLenBy2p1+1U] <-> pSrc[j+fftLenBy2p1+1U] */ + in = pSrc[(2U * (i + fftLenBy2p1)) + 1U]; + pSrc[(2U * (i + fftLenBy2p1)) + 1U] = + pSrc[(2U * (j + fftLenBy2p1)) + 1U]; + pSrc[(2U * (j + fftLenBy2p1)) + 1U] = in; + + } + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[2U * (i + 1U)]; + pSrc[2U * (i + 1U)] = pSrc[2U * (j + fftLenBy2)]; + pSrc[2U * (j + fftLenBy2)] = in; + + /* pSrc[i+2U] <-> pSrc[j+2U] */ + in = pSrc[(2U * (i + 1U)) + 1U]; + pSrc[(2U * (i + 1U)) + 1U] = pSrc[(2U * (j + fftLenBy2)) + 1U]; + pSrc[(2U * (j + fftLenBy2)) + 1U] = in; + + /* Reading the index for the bit reversal */ + j = *pBitRevTab; + + /* Updating the bit reversal index depending on the fft length */ + pBitRevTab += bitRevFactor; + } +} +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f16.c new file mode 100644 index 00000000..edfc0b4a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f16.c @@ -0,0 +1,842 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_f32.c + * Description: Combined Radix Decimation in Frequency CFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" +#include "arm_common_tables_f16.h" + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_fft.h" +#include "arm_mve_tables_f16.h" + + +static float16_t arm_inverse_fft_length_f16(uint16_t fftLen) +{ + float16_t retValue=1.0; + + switch (fftLen) + { + + case 4096U: + retValue = (float16_t)0.000244140625f; + break; + + case 2048U: + retValue = (float16_t)0.00048828125f; + break; + + case 1024U: + retValue = (float16_t)0.0009765625f; + break; + + case 512U: + retValue = (float16_t)0.001953125f; + break; + + case 256U: + retValue = (float16_t)0.00390625f; + break; + + case 128U: + retValue = (float16_t)0.0078125f; + break; + + case 64U: + retValue = (float16_t)0.015625f; + break; + + case 32U: + retValue = (float16_t)0.03125f; + break; + + case 16U: + retValue = (float16_t)0.0625f; + break; + + + default: + break; + } + return(retValue); +} + + +static void _arm_radix4_butterfly_f16_mve(const arm_cfft_instance_f16 * S,float16_t * pSrc, uint32_t fftLen) +{ + f16x8_t vecTmp0, vecTmp1; + f16x8_t vecSum0, vecDiff0, vecSum1, vecDiff1; + f16x8_t vecA, vecB, vecC, vecD; + uint32_t blkCnt; + uint32_t n1, n2; + uint32_t stage = 0; + int32_t iter = 1; + static const int32_t strides[4] = + { ( 0 - 16) * (int32_t)sizeof(float16_t *) + , ( 4 - 16) * (int32_t)sizeof(float16_t *) + , ( 8 - 16) * (int32_t)sizeof(float16_t *) + , (12 - 16) * (int32_t)sizeof(float16_t *)}; + + n2 = fftLen; + n1 = n2; + n2 >>= 2u; + for (int k = fftLen / 4u; k > 1; k >>= 2) + { + float16_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + float16_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + float16_t const *p_rearranged_twiddle_tab_stride3 = + &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + float16_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + float16_t *inA = pBase; + float16_t *inB = inA + n2 * CMPLX_DIM; + float16_t *inC = inB + n2 * CMPLX_DIM; + float16_t *inD = inC + n2 * CMPLX_DIM; + float16_t const *pW1 = p_rearranged_twiddle_tab_stride1; + float16_t const *pW2 = p_rearranged_twiddle_tab_stride2; + float16_t const *pW3 = p_rearranged_twiddle_tab_stride3; + f16x8_t vecW; + + blkCnt = n2 / 4; + /* + * load 2 f16 complex pair + */ + vecA = vldrhq_f16(inA); + vecC = vldrhq_f16(inC); + while (blkCnt > 0U) + { + vecB = vldrhq_f16(inB); + vecD = vldrhq_f16(inD); + + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vecSum0 + vecSum1; + vst1q(inA, vecTmp0); + inA += 8; + + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vecSum0 - vecSum1; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW2); + pW2 += 8; + vecTmp1 = MVE_CMPLX_MULT_FLT_Conj_AxB(vecW, vecTmp0); + vst1q(inB, vecTmp1); + inB += 8; + + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW1); + pW1 +=8; + vecTmp1 = MVE_CMPLX_MULT_FLT_Conj_AxB(vecW, vecTmp0); + vst1q(inC, vecTmp1); + inC += 8; + + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 8; + vecTmp1 = MVE_CMPLX_MULT_FLT_Conj_AxB(vecW, vecTmp0); + vst1q(inD, vecTmp1); + inD += 8; + + vecA = vldrhq_f16(inA); + vecC = vldrhq_f16(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* load scheduling */ + vecA = (f16x8_t)vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 8); + + blkCnt = (fftLen >> 4); + while (blkCnt > 0U) + { + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecB = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 4); + vecD = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 12); + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + + /* pre-load for next iteration */ + vecA = (f16x8_t)vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 8); + + vecTmp0 = vecSum0 + vecSum1; + vstrwq_scatter_base_f32(vecScGathAddr, -64, (f32x4_t)vecTmp0); + + vecTmp0 = vecSum0 - vecSum1; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 4, (f32x4_t)vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 8, (f32x4_t)vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 12, (f32x4_t)vecTmp0); + + blkCnt--; + } + + /* + * End of last stage process + */ +} + +static void arm_cfft_radix4by2_f16_mve(const arm_cfft_instance_f16 * S, float16_t *pSrc, uint32_t fftLen) +{ + float16_t const *pCoefVec; + float16_t const *pCoef = S->pTwiddle; + float16_t *pIn0, *pIn1; + uint32_t n2; + uint32_t blkCnt; + f16x8_t vecIn0, vecIn1, vecSum, vecDiff; + f16x8_t vecCmplxTmp, vecTw; + + + n2 = fftLen >> 1; + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + pCoefVec = pCoef; + + blkCnt = n2 / 4; + while (blkCnt > 0U) + { + vecIn0 = *(f16x8_t *) pIn0; + vecIn1 = *(f16x8_t *) pIn1; + vecTw = vld1q(pCoefVec); + pCoefVec += 8; + + vecSum = vaddq(vecIn0, vecIn1); + vecDiff = vsubq(vecIn0, vecIn1); + + vecCmplxTmp = MVE_CMPLX_MULT_FLT_Conj_AxB(vecTw, vecDiff); + + vst1q(pIn0, vecSum); + pIn0 += 8; + vst1q(pIn1, vecCmplxTmp); + pIn1 += 8; + + blkCnt--; + } + + _arm_radix4_butterfly_f16_mve(S, pSrc, n2); + + _arm_radix4_butterfly_f16_mve(S, pSrc + fftLen, n2); + + pIn0 = pSrc; +} + +static void _arm_radix4_butterfly_inverse_f16_mve(const arm_cfft_instance_f16 * S,float16_t * pSrc, uint32_t fftLen, float16_t onebyfftLen) +{ + f16x8_t vecTmp0, vecTmp1; + f16x8_t vecSum0, vecDiff0, vecSum1, vecDiff1; + f16x8_t vecA, vecB, vecC, vecD; + uint32_t blkCnt; + uint32_t n1, n2; + uint32_t stage = 0; + int32_t iter = 1; + static const int32_t strides[4] = { + ( 0 - 16) * (int32_t)sizeof(q31_t *), + ( 4 - 16) * (int32_t)sizeof(q31_t *), + ( 8 - 16) * (int32_t)sizeof(q31_t *), + (12 - 16) * (int32_t)sizeof(q31_t *) + }; + + n2 = fftLen; + n1 = n2; + n2 >>= 2u; + for (int k = fftLen / 4; k > 1; k >>= 2) + { + float16_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + float16_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + float16_t const *p_rearranged_twiddle_tab_stride3 = + &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + + float16_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + float16_t *inA = pBase; + float16_t *inB = inA + n2 * CMPLX_DIM; + float16_t *inC = inB + n2 * CMPLX_DIM; + float16_t *inD = inC + n2 * CMPLX_DIM; + float16_t const *pW1 = p_rearranged_twiddle_tab_stride1; + float16_t const *pW2 = p_rearranged_twiddle_tab_stride2; + float16_t const *pW3 = p_rearranged_twiddle_tab_stride3; + f16x8_t vecW; + + blkCnt = n2 / 4; + /* + * load 2 f32 complex pair + */ + vecA = vldrhq_f16(inA); + vecC = vldrhq_f16(inC); + while (blkCnt > 0U) + { + vecB = vldrhq_f16(inB); + vecD = vldrhq_f16(inD); + + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vecSum0 + vecSum1; + vst1q(inA, vecTmp0); + inA += 8; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vecSum0 - vecSum1; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW2); + pW2 += 8; + vecTmp1 = MVE_CMPLX_MULT_FLT_AxB(vecW, vecTmp0); + vst1q(inB, vecTmp1); + inB += 8; + + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW1); + pW1 += 8; + vecTmp1 = MVE_CMPLX_MULT_FLT_AxB(vecW, vecTmp0); + vst1q(inC, vecTmp1); + inC += 8; + + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 8; + vecTmp1 = MVE_CMPLX_MULT_FLT_AxB(vecW, vecTmp0); + vst1q(inD, vecTmp1); + inD += 8; + + vecA = vldrhq_f16(inA); + vecC = vldrhq_f16(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* + * load scheduling + */ + vecA = (f16x8_t)vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 8); + + blkCnt = (fftLen >> 4); + while (blkCnt > 0U) + { + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecB = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 4); + vecD = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 12); + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + + vecA = (f16x8_t)vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 8); + + vecTmp0 = vecSum0 + vecSum1; + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64, (f32x4_t)vecTmp0); + + vecTmp0 = vecSum0 - vecSum1; + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 4, (f32x4_t)vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 8, (f32x4_t)vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 12, (f32x4_t)vecTmp0); + + blkCnt--; + } + + /* + * End of last stage process + */ +} + +static void arm_cfft_radix4by2_inverse_f16_mve(const arm_cfft_instance_f16 * S,float16_t *pSrc, uint32_t fftLen) +{ + float16_t const *pCoefVec; + float16_t const *pCoef = S->pTwiddle; + float16_t *pIn0, *pIn1; + uint32_t n2; + float16_t onebyfftLen = arm_inverse_fft_length_f16(fftLen); + uint32_t blkCnt; + f16x8_t vecIn0, vecIn1, vecSum, vecDiff; + f16x8_t vecCmplxTmp, vecTw; + + + n2 = fftLen >> 1; + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + pCoefVec = pCoef; + + blkCnt = n2 / 4; + while (blkCnt > 0U) + { + vecIn0 = *(f16x8_t *) pIn0; + vecIn1 = *(f16x8_t *) pIn1; + vecTw = vld1q(pCoefVec); + pCoefVec += 8; + + vecSum = vaddq(vecIn0, vecIn1); + vecDiff = vsubq(vecIn0, vecIn1); + + vecCmplxTmp = MVE_CMPLX_MULT_FLT_AxB(vecTw, vecDiff); + + vst1q(pIn0, vecSum); + pIn0 += 8; + vst1q(pIn1, vecCmplxTmp); + pIn1 += 8; + + blkCnt--; + } + + _arm_radix4_butterfly_inverse_f16_mve(S, pSrc, n2, onebyfftLen); + + _arm_radix4_butterfly_inverse_f16_mve(S, pSrc + fftLen, n2, onebyfftLen); +} + + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the floating-point complex FFT. + @param[in] S points to an instance of the floating-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + + +void arm_cfft_f16( + const arm_cfft_instance_f16 * S, + float16_t * pSrc, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t fftLen = S->fftLen; + + if (ifftFlag == 1U) { + + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_inverse_f16_mve(S, pSrc, fftLen, arm_inverse_fft_length_f16(S->fftLen)); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_inverse_f16_mve(S, pSrc, fftLen); + break; + } + } else { + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_f16_mve(S, pSrc, fftLen); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_f16_mve(S, pSrc, fftLen); + break; + } + } + + + if (bitReverseFlag) + { + + arm_bitreversal_16_inpl_mve((uint16_t*)pSrc, S->bitRevLength, S->pBitRevTable); + + } +} + +#else + +#if defined(ARM_FLOAT16_SUPPORTED) + +extern void arm_bitreversal_16( + uint16_t * pSrc, + const uint16_t bitRevLen, + const uint16_t * pBitRevTable); + + +extern void arm_cfft_radix4by2_f16( + float16_t * pSrc, + uint32_t fftLen, + const float16_t * pCoef); + +extern void arm_radix4_butterfly_f16( + float16_t * pSrc, + uint16_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier); + +/** + @ingroup groupTransforms + */ + +/** + @defgroup ComplexFFT Complex FFT Functions + + @par + The Fast Fourier Transform (FFT) is an efficient algorithm for computing the + Discrete Fourier Transform (DFT). The FFT can be orders of magnitude faster + than the DFT, especially for long lengths. + The algorithms described in this section + operate on complex data. A separate set of functions is devoted to handling + of real sequences. + @par + There are separate algorithms for handling floating-point, Q15, and Q31 data + types. The algorithms available for each data type are described next. + @par + The FFT functions operate in-place. That is, the array holding the input data + will also be used to hold the corresponding result. The input data is complex + and contains 2*fftLen interleaved values as shown below. +
{real[0], imag[0], real[1], imag[1], ...} 
+ The FFT result will be contained in the same array and the frequency domain + values will have the same interleaving. + + @par Floating-point + The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-8 + stages are performed along with a single radix-2 or radix-4 stage, as needed. + The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses + a different twiddle factor table. + @par + The function uses the standard FFT definition and output values may grow by a + factor of fftLen when computing the forward transform. The + inverse transform includes a scale of 1/fftLen as part of the + calculation and this matches the textbook definition of the inverse FFT. + @par + For the MVE version, the new arm_cfft_init_f32 initialization function is + mandatory. Compilation flags are available to include only the required tables for the + needed FFTs. Other FFT versions can continue to be initialized as + explained below. + @par + For not MVE versions, pre-initialized data structures containing twiddle factors + and bit reversal tables are provided and defined in arm_const_structs.h. Include + this header in your function and then pass one of the constant structures as + an argument to arm_cfft_f32. For example: + @par + arm_cfft_f32(arm_cfft_sR_f32_len64, pSrc, 1, 1) + @par + computes a 64-point inverse complex FFT including bit reversal. + The data structures are treated as constant data and not modified during the + calculation. The same data structure can be reused for multiple transforms + including mixing forward and inverse transforms. + @par + Earlier releases of the library provided separate radix-2 and radix-4 + algorithms that operated on floating-point data. These functions are still + provided but are deprecated. The older functions are slower and less general + than the new functions. + @par + An example of initialization of the constants for the arm_cfft_f32 function follows: + @code + const static arm_cfft_instance_f32 *S; + ... + switch (length) { + case 16: + S = &arm_cfft_sR_f32_len16; + break; + case 32: + S = &arm_cfft_sR_f32_len32; + break; + case 64: + S = &arm_cfft_sR_f32_len64; + break; + case 128: + S = &arm_cfft_sR_f32_len128; + break; + case 256: + S = &arm_cfft_sR_f32_len256; + break; + case 512: + S = &arm_cfft_sR_f32_len512; + break; + case 1024: + S = &arm_cfft_sR_f32_len1024; + break; + case 2048: + S = &arm_cfft_sR_f32_len2048; + break; + case 4096: + S = &arm_cfft_sR_f32_len4096; + break; + } + @endcode + @par + The new arm_cfft_init_f32 can also be used. + @par Q15 and Q31 + The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-4 + stages are performed along with a single radix-2 stage, as needed. + The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses + a different twiddle factor table. + @par + The function uses the standard FFT definition and output values may grow by a + factor of fftLen when computing the forward transform. The + inverse transform includes a scale of 1/fftLen as part of the + calculation and this matches the textbook definition of the inverse FFT. + @par + Pre-initialized data structures containing twiddle factors and bit reversal + tables are provided and defined in arm_const_structs.h. Include + this header in your function and then pass one of the constant structures as + an argument to arm_cfft_q31. For example: + @par + arm_cfft_q31(arm_cfft_sR_q31_len64, pSrc, 1, 1) + @par + computes a 64-point inverse complex FFT including bit reversal. + The data structures are treated as constant data and not modified during the + calculation. The same data structure can be reused for multiple transforms + including mixing forward and inverse transforms. + @par + Earlier releases of the library provided separate radix-2 and radix-4 + algorithms that operated on floating-point data. These functions are still + provided but are deprecated. The older functions are slower and less general + than the new functions. + @par + An example of initialization of the constants for the arm_cfft_q31 function follows: + @code + const static arm_cfft_instance_q31 *S; + ... + switch (length) { + case 16: + S = &arm_cfft_sR_q31_len16; + break; + case 32: + S = &arm_cfft_sR_q31_len32; + break; + case 64: + S = &arm_cfft_sR_q31_len64; + break; + case 128: + S = &arm_cfft_sR_q31_len128; + break; + case 256: + S = &arm_cfft_sR_q31_len256; + break; + case 512: + S = &arm_cfft_sR_q31_len512; + break; + case 1024: + S = &arm_cfft_sR_q31_len1024; + break; + case 2048: + S = &arm_cfft_sR_q31_len2048; + break; + case 4096: + S = &arm_cfft_sR_q31_len4096; + break; + } + @endcode + + */ + + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the floating-point complex FFT. + @param[in] S points to an instance of the floating-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + +void arm_cfft_f16( + const arm_cfft_instance_f16 * S, + float16_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen, l; + float16_t invL, * pSrc; + + if (ifftFlag == 1U) + { + /* Conjugate input data */ + pSrc = p1 + 1; + for(l=0; lpTwiddle, 1U); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_f16 ( p1, L, (float16_t*)S->pTwiddle); + break; + + } + + if ( bitReverseFlag ) + arm_bitreversal_16((uint16_t*)p1, S->bitRevLength,(uint16_t*)S->pBitRevTable); + + if (ifftFlag == 1U) + { + invL = 1.0f16/(_Float16)L; + /* Conjugate and scale output data */ + pSrc = p1; + for(l=0; l>= 2u; + for (int k = fftLen / 4u; k > 1; k >>= 2) + { + float32_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + float32_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + float32_t const *p_rearranged_twiddle_tab_stride3 = + &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + + float32_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + float32_t *inA = pBase; + float32_t *inB = inA + n2 * CMPLX_DIM; + float32_t *inC = inB + n2 * CMPLX_DIM; + float32_t *inD = inC + n2 * CMPLX_DIM; + float32_t const *pW1 = p_rearranged_twiddle_tab_stride1; + float32_t const *pW2 = p_rearranged_twiddle_tab_stride2; + float32_t const *pW3 = p_rearranged_twiddle_tab_stride3; + f32x4_t vecW; + + blkCnt = n2 / 2; + /* + * load 2 f32 complex pair + */ + vecA = vldrwq_f32(inA); + vecC = vldrwq_f32(inC); + while (blkCnt > 0U) + { + vecB = vldrwq_f32(inB); + vecD = vldrwq_f32(inD); + + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vecSum0 + vecSum1; + vst1q(inA, vecTmp0); + inA += 4; + + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vecSum0 - vecSum1; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW2); + pW2 += 4; + vecTmp1 = MVE_CMPLX_MULT_FLT_Conj_AxB(vecW, vecTmp0); + vst1q(inB, vecTmp1); + inB += 4; + + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW1); + pW1 +=4; + vecTmp1 = MVE_CMPLX_MULT_FLT_Conj_AxB(vecW, vecTmp0); + vst1q(inC, vecTmp1); + inC += 4; + + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 4; + vecTmp1 = MVE_CMPLX_MULT_FLT_Conj_AxB(vecW, vecTmp0); + vst1q(inD, vecTmp1); + inD += 4; + + vecA = vldrwq_f32(inA); + vecC = vldrwq_f32(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* load scheduling */ + vecA = vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_f32(vecScGathAddr, 16); + + blkCnt = (fftLen >> 3); + while (blkCnt > 0U) + { + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecB = vldrwq_gather_base_f32(vecScGathAddr, 8); + vecD = vldrwq_gather_base_f32(vecScGathAddr, 24); + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + + /* pre-load for next iteration */ + vecA = vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_f32(vecScGathAddr, 16); + + vecTmp0 = vecSum0 + vecSum1; + vstrwq_scatter_base_f32(vecScGathAddr, -64, vecTmp0); + + vecTmp0 = vecSum0 - vecSum1; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 8, vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 16, vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 24, vecTmp0); + + blkCnt--; + } + + /* + * End of last stage process + */ +} + +static void arm_cfft_radix4by2_f32_mve(const arm_cfft_instance_f32 * S, float32_t *pSrc, uint32_t fftLen) +{ + float32_t const *pCoefVec; + float32_t const *pCoef = S->pTwiddle; + float32_t *pIn0, *pIn1; + uint32_t n2; + uint32_t blkCnt; + f32x4_t vecIn0, vecIn1, vecSum, vecDiff; + f32x4_t vecCmplxTmp, vecTw; + + + n2 = fftLen >> 1; + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + pCoefVec = pCoef; + + blkCnt = n2 / 2; + while (blkCnt > 0U) + { + vecIn0 = *(f32x4_t *) pIn0; + vecIn1 = *(f32x4_t *) pIn1; + vecTw = vld1q(pCoefVec); + pCoefVec += 4; + + vecSum = vecIn0 + vecIn1; + vecDiff = vecIn0 - vecIn1; + + vecCmplxTmp = MVE_CMPLX_MULT_FLT_Conj_AxB(vecTw, vecDiff); + + vst1q(pIn0, vecSum); + pIn0 += 4; + vst1q(pIn1, vecCmplxTmp); + pIn1 += 4; + + blkCnt--; + } + + _arm_radix4_butterfly_f32_mve(S, pSrc, n2); + + _arm_radix4_butterfly_f32_mve(S, pSrc + fftLen, n2); + + pIn0 = pSrc; +} + +static void _arm_radix4_butterfly_inverse_f32_mve(const arm_cfft_instance_f32 * S,float32_t * pSrc, uint32_t fftLen, float32_t onebyfftLen) +{ + f32x4_t vecTmp0, vecTmp1; + f32x4_t vecSum0, vecDiff0, vecSum1, vecDiff1; + f32x4_t vecA, vecB, vecC, vecD; + uint32_t blkCnt; + uint32_t n1, n2; + uint32_t stage = 0; + int32_t iter = 1; + static const int32_t strides[4] = { + (0 - 16) * (int32_t)sizeof(q31_t *), + (1 - 16) * (int32_t)sizeof(q31_t *), + (8 - 16) * (int32_t)sizeof(q31_t *), + (9 - 16) * (int32_t)sizeof(q31_t *) + }; + + n2 = fftLen; + n1 = n2; + n2 >>= 2u; + for (int k = fftLen / 4; k > 1; k >>= 2) + { + float32_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + float32_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + float32_t const *p_rearranged_twiddle_tab_stride3 = + &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + + float32_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + float32_t *inA = pBase; + float32_t *inB = inA + n2 * CMPLX_DIM; + float32_t *inC = inB + n2 * CMPLX_DIM; + float32_t *inD = inC + n2 * CMPLX_DIM; + float32_t const *pW1 = p_rearranged_twiddle_tab_stride1; + float32_t const *pW2 = p_rearranged_twiddle_tab_stride2; + float32_t const *pW3 = p_rearranged_twiddle_tab_stride3; + f32x4_t vecW; + + blkCnt = n2 / 2; + /* + * load 2 f32 complex pair + */ + vecA = vldrwq_f32(inA); + vecC = vldrwq_f32(inC); + while (blkCnt > 0U) + { + vecB = vldrwq_f32(inB); + vecD = vldrwq_f32(inD); + + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vecSum0 + vecSum1; + vst1q(inA, vecTmp0); + inA += 4; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vecSum0 - vecSum1; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW2); + pW2 += 4; + vecTmp1 = MVE_CMPLX_MULT_FLT_AxB(vecW, vecTmp0); + vst1q(inB, vecTmp1); + inB += 4; + + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW1); + pW1 += 4; + vecTmp1 = MVE_CMPLX_MULT_FLT_AxB(vecW, vecTmp0); + vst1q(inC, vecTmp1); + inC += 4; + + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 4; + vecTmp1 = MVE_CMPLX_MULT_FLT_AxB(vecW, vecTmp0); + vst1q(inD, vecTmp1); + inD += 4; + + vecA = vldrwq_f32(inA); + vecC = vldrwq_f32(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32 ((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* + * load scheduling + */ + vecA = vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_f32(vecScGathAddr, 16); + + blkCnt = (fftLen >> 3); + while (blkCnt > 0U) + { + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecB = vldrwq_gather_base_f32(vecScGathAddr, 8); + vecD = vldrwq_gather_base_f32(vecScGathAddr, 24); + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + + vecA = vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_f32(vecScGathAddr, 16); + + vecTmp0 = vecSum0 + vecSum1; + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64, vecTmp0); + + vecTmp0 = vecSum0 - vecSum1; + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 8, vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 16, vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 24, vecTmp0); + + blkCnt--; + } + + /* + * End of last stage process + */ +} + +static void arm_cfft_radix4by2_inverse_f32_mve(const arm_cfft_instance_f32 * S,float32_t *pSrc, uint32_t fftLen) +{ + float32_t const *pCoefVec; + float32_t const *pCoef = S->pTwiddle; + float32_t *pIn0, *pIn1; + uint32_t n2; + float32_t onebyfftLen = arm_inverse_fft_length_f32(fftLen); + uint32_t blkCnt; + f32x4_t vecIn0, vecIn1, vecSum, vecDiff; + f32x4_t vecCmplxTmp, vecTw; + + + n2 = fftLen >> 1; + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + pCoefVec = pCoef; + + blkCnt = n2 / 2; + while (blkCnt > 0U) + { + vecIn0 = *(f32x4_t *) pIn0; + vecIn1 = *(f32x4_t *) pIn1; + vecTw = vld1q(pCoefVec); + pCoefVec += 4; + + vecSum = vecIn0 + vecIn1; + vecDiff = vecIn0 - vecIn1; + + vecCmplxTmp = MVE_CMPLX_MULT_FLT_AxB(vecTw, vecDiff); + + vst1q(pIn0, vecSum); + pIn0 += 4; + vst1q(pIn1, vecCmplxTmp); + pIn1 += 4; + + blkCnt--; + } + + _arm_radix4_butterfly_inverse_f32_mve(S, pSrc, n2, onebyfftLen); + + _arm_radix4_butterfly_inverse_f32_mve(S, pSrc + fftLen, n2, onebyfftLen); +} + + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the floating-point complex FFT. + @param[in] S points to an instance of the floating-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + + +void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * pSrc, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t fftLen = S->fftLen; + + if (ifftFlag == 1U) { + + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_inverse_f32_mve(S, pSrc, fftLen, arm_inverse_fft_length_f32(S->fftLen)); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_inverse_f32_mve(S, pSrc, fftLen); + break; + } + } else { + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_f32_mve(S, pSrc, fftLen); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_f32_mve(S, pSrc, fftLen); + break; + } + } + + + if (bitReverseFlag) + { + + arm_bitreversal_32_inpl_mve((uint32_t*)pSrc, S->bitRevLength, S->pBitRevTable); + + } +} + + +#else +extern void arm_radix8_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier); + +extern void arm_bitreversal_32( + uint32_t * pSrc, + const uint16_t bitRevLen, + const uint16_t * pBitRevTable); + +/** + @ingroup groupTransforms + */ + +/** + @defgroup ComplexFFT Complex FFT Functions + + @par + The Fast Fourier Transform (FFT) is an efficient algorithm for computing the + Discrete Fourier Transform (DFT). The FFT can be orders of magnitude faster + than the DFT, especially for long lengths. + The algorithms described in this section + operate on complex data. A separate set of functions is devoted to handling + of real sequences. + @par + There are separate algorithms for handling floating-point, Q15, and Q31 data + types. The algorithms available for each data type are described next. + @par + The FFT functions operate in-place. That is, the array holding the input data + will also be used to hold the corresponding result. The input data is complex + and contains 2*fftLen interleaved values as shown below. +
{real[0], imag[0], real[1], imag[1], ...} 
+ The FFT result will be contained in the same array and the frequency domain + values will have the same interleaving. + + @par Floating-point + The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-8 + stages are performed along with a single radix-2 or radix-4 stage, as needed. + The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses + a different twiddle factor table. + @par + The function uses the standard FFT definition and output values may grow by a + factor of fftLen when computing the forward transform. The + inverse transform includes a scale of 1/fftLen as part of the + calculation and this matches the textbook definition of the inverse FFT. + @par + For the MVE version, the new arm_cfft_init_f32 initialization function is + mandatory. Compilation flags are available to include only the required tables for the + needed FFTs. Other FFT versions can continue to be initialized as + explained below. + @par + For not MVE versions, pre-initialized data structures containing twiddle factors + and bit reversal tables are provided and defined in arm_const_structs.h. Include + this header in your function and then pass one of the constant structures as + an argument to arm_cfft_f32. For example: + @par + arm_cfft_f32(arm_cfft_sR_f32_len64, pSrc, 1, 1) + @par + computes a 64-point inverse complex FFT including bit reversal. + The data structures are treated as constant data and not modified during the + calculation. The same data structure can be reused for multiple transforms + including mixing forward and inverse transforms. + @par + Earlier releases of the library provided separate radix-2 and radix-4 + algorithms that operated on floating-point data. These functions are still + provided but are deprecated. The older functions are slower and less general + than the new functions. + @par + An example of initialization of the constants for the arm_cfft_f32 function follows: + @code + const static arm_cfft_instance_f32 *S; + ... + switch (length) { + case 16: + S = &arm_cfft_sR_f32_len16; + break; + case 32: + S = &arm_cfft_sR_f32_len32; + break; + case 64: + S = &arm_cfft_sR_f32_len64; + break; + case 128: + S = &arm_cfft_sR_f32_len128; + break; + case 256: + S = &arm_cfft_sR_f32_len256; + break; + case 512: + S = &arm_cfft_sR_f32_len512; + break; + case 1024: + S = &arm_cfft_sR_f32_len1024; + break; + case 2048: + S = &arm_cfft_sR_f32_len2048; + break; + case 4096: + S = &arm_cfft_sR_f32_len4096; + break; + } + @endcode + @par + The new arm_cfft_init_f32 can also be used. + @par Q15 and Q31 + The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-4 + stages are performed along with a single radix-2 stage, as needed. + The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses + a different twiddle factor table. + @par + The function uses the standard FFT definition and output values may grow by a + factor of fftLen when computing the forward transform. The + inverse transform includes a scale of 1/fftLen as part of the + calculation and this matches the textbook definition of the inverse FFT. + @par + Pre-initialized data structures containing twiddle factors and bit reversal + tables are provided and defined in arm_const_structs.h. Include + this header in your function and then pass one of the constant structures as + an argument to arm_cfft_q31. For example: + @par + arm_cfft_q31(arm_cfft_sR_q31_len64, pSrc, 1, 1) + @par + computes a 64-point inverse complex FFT including bit reversal. + The data structures are treated as constant data and not modified during the + calculation. The same data structure can be reused for multiple transforms + including mixing forward and inverse transforms. + @par + Earlier releases of the library provided separate radix-2 and radix-4 + algorithms that operated on floating-point data. These functions are still + provided but are deprecated. The older functions are slower and less general + than the new functions. + @par + An example of initialization of the constants for the arm_cfft_q31 function follows: + @code + const static arm_cfft_instance_q31 *S; + ... + switch (length) { + case 16: + S = &arm_cfft_sR_q31_len16; + break; + case 32: + S = &arm_cfft_sR_q31_len32; + break; + case 64: + S = &arm_cfft_sR_q31_len64; + break; + case 128: + S = &arm_cfft_sR_q31_len128; + break; + case 256: + S = &arm_cfft_sR_q31_len256; + break; + case 512: + S = &arm_cfft_sR_q31_len512; + break; + case 1024: + S = &arm_cfft_sR_q31_len1024; + break; + case 2048: + S = &arm_cfft_sR_q31_len2048; + break; + case 4096: + S = &arm_cfft_sR_q31_len4096; + break; + } + @endcode + + */ + +void arm_cfft_radix8by2_f32 (arm_cfft_instance_f32 * S, float32_t * p1) +{ + uint32_t L = S->fftLen; + float32_t * pCol1, * pCol2, * pMid1, * pMid2; + float32_t * p2 = p1 + L; + const float32_t * tw = (float32_t *) S->pTwiddle; + float32_t t1[4], t2[4], t3[4], t4[4], twR, twI; + float32_t m0, m1, m2, m3; + uint32_t l; + + pCol1 = p1; + pCol2 = p2; + + /* Define new length */ + L >>= 1; + + /* Initialize mid pointers */ + pMid1 = p1 + L; + pMid2 = p2 + L; + + /* do two dot Fourier transform */ + for (l = L >> 2; l > 0; l-- ) + { + t1[0] = p1[0]; + t1[1] = p1[1]; + t1[2] = p1[2]; + t1[3] = p1[3]; + + t2[0] = p2[0]; + t2[1] = p2[1]; + t2[2] = p2[2]; + t2[3] = p2[3]; + + t3[0] = pMid1[0]; + t3[1] = pMid1[1]; + t3[2] = pMid1[2]; + t3[3] = pMid1[3]; + + t4[0] = pMid2[0]; + t4[1] = pMid2[1]; + t4[2] = pMid2[2]; + t4[3] = pMid2[3]; + + *p1++ = t1[0] + t2[0]; + *p1++ = t1[1] + t2[1]; + *p1++ = t1[2] + t2[2]; + *p1++ = t1[3] + t2[3]; /* col 1 */ + + t2[0] = t1[0] - t2[0]; + t2[1] = t1[1] - t2[1]; + t2[2] = t1[2] - t2[2]; + t2[3] = t1[3] - t2[3]; /* for col 2 */ + + *pMid1++ = t3[0] + t4[0]; + *pMid1++ = t3[1] + t4[1]; + *pMid1++ = t3[2] + t4[2]; + *pMid1++ = t3[3] + t4[3]; /* col 1 */ + + t4[0] = t4[0] - t3[0]; + t4[1] = t4[1] - t3[1]; + t4[2] = t4[2] - t3[2]; + t4[3] = t4[3] - t3[3]; /* for col 2 */ + + twR = *tw++; + twI = *tw++; + + /* multiply by twiddle factors */ + m0 = t2[0] * twR; + m1 = t2[1] * twI; + m2 = t2[1] * twR; + m3 = t2[0] * twI; + + /* R = R * Tr - I * Ti */ + *p2++ = m0 + m1; + /* I = I * Tr + R * Ti */ + *p2++ = m2 - m3; + + /* use vertical symmetry */ + /* 0.9988 - 0.0491i <==> -0.0491 - 0.9988i */ + m0 = t4[0] * twI; + m1 = t4[1] * twR; + m2 = t4[1] * twI; + m3 = t4[0] * twR; + + *pMid2++ = m0 - m1; + *pMid2++ = m2 + m3; + + twR = *tw++; + twI = *tw++; + + m0 = t2[2] * twR; + m1 = t2[3] * twI; + m2 = t2[3] * twR; + m3 = t2[2] * twI; + + *p2++ = m0 + m1; + *p2++ = m2 - m3; + + m0 = t4[2] * twI; + m1 = t4[3] * twR; + m2 = t4[3] * twI; + m3 = t4[2] * twR; + + *pMid2++ = m0 - m1; + *pMid2++ = m2 + m3; + } + + /* first col */ + arm_radix8_butterfly_f32 (pCol1, L, (float32_t *) S->pTwiddle, 2U); + + /* second col */ + arm_radix8_butterfly_f32 (pCol2, L, (float32_t *) S->pTwiddle, 2U); +} + +void arm_cfft_radix8by4_f32 (arm_cfft_instance_f32 * S, float32_t * p1) +{ + uint32_t L = S->fftLen >> 1; + float32_t * pCol1, *pCol2, *pCol3, *pCol4, *pEnd1, *pEnd2, *pEnd3, *pEnd4; + const float32_t *tw2, *tw3, *tw4; + float32_t * p2 = p1 + L; + float32_t * p3 = p2 + L; + float32_t * p4 = p3 + L; + float32_t t2[4], t3[4], t4[4], twR, twI; + float32_t p1ap3_0, p1sp3_0, p1ap3_1, p1sp3_1; + float32_t m0, m1, m2, m3; + uint32_t l, twMod2, twMod3, twMod4; + + pCol1 = p1; /* points to real values by default */ + pCol2 = p2; + pCol3 = p3; + pCol4 = p4; + pEnd1 = p2 - 1; /* points to imaginary values by default */ + pEnd2 = p3 - 1; + pEnd3 = p4 - 1; + pEnd4 = pEnd3 + L; + + tw2 = tw3 = tw4 = (float32_t *) S->pTwiddle; + + L >>= 1; + + /* do four dot Fourier transform */ + + twMod2 = 2; + twMod3 = 4; + twMod4 = 6; + + /* TOP */ + p1ap3_0 = p1[0] + p3[0]; + p1sp3_0 = p1[0] - p3[0]; + p1ap3_1 = p1[1] + p3[1]; + p1sp3_1 = p1[1] - p3[1]; + + /* col 2 */ + t2[0] = p1sp3_0 + p2[1] - p4[1]; + t2[1] = p1sp3_1 - p2[0] + p4[0]; + /* col 3 */ + t3[0] = p1ap3_0 - p2[0] - p4[0]; + t3[1] = p1ap3_1 - p2[1] - p4[1]; + /* col 4 */ + t4[0] = p1sp3_0 - p2[1] + p4[1]; + t4[1] = p1sp3_1 + p2[0] - p4[0]; + /* col 1 */ + *p1++ = p1ap3_0 + p2[0] + p4[0]; + *p1++ = p1ap3_1 + p2[1] + p4[1]; + + /* Twiddle factors are ones */ + *p2++ = t2[0]; + *p2++ = t2[1]; + *p3++ = t3[0]; + *p3++ = t3[1]; + *p4++ = t4[0]; + *p4++ = t4[1]; + + tw2 += twMod2; + tw3 += twMod3; + tw4 += twMod4; + + for (l = (L - 2) >> 1; l > 0; l-- ) + { + /* TOP */ + p1ap3_0 = p1[0] + p3[0]; + p1sp3_0 = p1[0] - p3[0]; + p1ap3_1 = p1[1] + p3[1]; + p1sp3_1 = p1[1] - p3[1]; + /* col 2 */ + t2[0] = p1sp3_0 + p2[1] - p4[1]; + t2[1] = p1sp3_1 - p2[0] + p4[0]; + /* col 3 */ + t3[0] = p1ap3_0 - p2[0] - p4[0]; + t3[1] = p1ap3_1 - p2[1] - p4[1]; + /* col 4 */ + t4[0] = p1sp3_0 - p2[1] + p4[1]; + t4[1] = p1sp3_1 + p2[0] - p4[0]; + /* col 1 - top */ + *p1++ = p1ap3_0 + p2[0] + p4[0]; + *p1++ = p1ap3_1 + p2[1] + p4[1]; + + /* BOTTOM */ + p1ap3_1 = pEnd1[-1] + pEnd3[-1]; + p1sp3_1 = pEnd1[-1] - pEnd3[-1]; + p1ap3_0 = pEnd1[ 0] + pEnd3[0]; + p1sp3_0 = pEnd1[ 0] - pEnd3[0]; + /* col 2 */ + t2[2] = pEnd2[0] - pEnd4[0] + p1sp3_1; + t2[3] = pEnd1[0] - pEnd3[0] - pEnd2[-1] + pEnd4[-1]; + /* col 3 */ + t3[2] = p1ap3_1 - pEnd2[-1] - pEnd4[-1]; + t3[3] = p1ap3_0 - pEnd2[ 0] - pEnd4[ 0]; + /* col 4 */ + t4[2] = pEnd2[ 0] - pEnd4[ 0] - p1sp3_1; + t4[3] = pEnd4[-1] - pEnd2[-1] - p1sp3_0; + /* col 1 - Bottom */ + *pEnd1-- = p1ap3_0 + pEnd2[ 0] + pEnd4[ 0]; + *pEnd1-- = p1ap3_1 + pEnd2[-1] + pEnd4[-1]; + + /* COL 2 */ + /* read twiddle factors */ + twR = *tw2++; + twI = *tw2++; + /* multiply by twiddle factors */ + /* let Z1 = a + i(b), Z2 = c + i(d) */ + /* => Z1 * Z2 = (a*c - b*d) + i(b*c + a*d) */ + + /* Top */ + m0 = t2[0] * twR; + m1 = t2[1] * twI; + m2 = t2[1] * twR; + m3 = t2[0] * twI; + + *p2++ = m0 + m1; + *p2++ = m2 - m3; + /* use vertical symmetry col 2 */ + /* 0.9997 - 0.0245i <==> 0.0245 - 0.9997i */ + /* Bottom */ + m0 = t2[3] * twI; + m1 = t2[2] * twR; + m2 = t2[2] * twI; + m3 = t2[3] * twR; + + *pEnd2-- = m0 - m1; + *pEnd2-- = m2 + m3; + + /* COL 3 */ + twR = tw3[0]; + twI = tw3[1]; + tw3 += twMod3; + /* Top */ + m0 = t3[0] * twR; + m1 = t3[1] * twI; + m2 = t3[1] * twR; + m3 = t3[0] * twI; + + *p3++ = m0 + m1; + *p3++ = m2 - m3; + /* use vertical symmetry col 3 */ + /* 0.9988 - 0.0491i <==> -0.9988 - 0.0491i */ + /* Bottom */ + m0 = -t3[3] * twR; + m1 = t3[2] * twI; + m2 = t3[2] * twR; + m3 = t3[3] * twI; + + *pEnd3-- = m0 - m1; + *pEnd3-- = m3 - m2; + + /* COL 4 */ + twR = tw4[0]; + twI = tw4[1]; + tw4 += twMod4; + /* Top */ + m0 = t4[0] * twR; + m1 = t4[1] * twI; + m2 = t4[1] * twR; + m3 = t4[0] * twI; + + *p4++ = m0 + m1; + *p4++ = m2 - m3; + /* use vertical symmetry col 4 */ + /* 0.9973 - 0.0736i <==> -0.0736 + 0.9973i */ + /* Bottom */ + m0 = t4[3] * twI; + m1 = t4[2] * twR; + m2 = t4[2] * twI; + m3 = t4[3] * twR; + + *pEnd4-- = m0 - m1; + *pEnd4-- = m2 + m3; + } + + /* MIDDLE */ + /* Twiddle factors are */ + /* 1.0000 0.7071-0.7071i -1.0000i -0.7071-0.7071i */ + p1ap3_0 = p1[0] + p3[0]; + p1sp3_0 = p1[0] - p3[0]; + p1ap3_1 = p1[1] + p3[1]; + p1sp3_1 = p1[1] - p3[1]; + + /* col 2 */ + t2[0] = p1sp3_0 + p2[1] - p4[1]; + t2[1] = p1sp3_1 - p2[0] + p4[0]; + /* col 3 */ + t3[0] = p1ap3_0 - p2[0] - p4[0]; + t3[1] = p1ap3_1 - p2[1] - p4[1]; + /* col 4 */ + t4[0] = p1sp3_0 - p2[1] + p4[1]; + t4[1] = p1sp3_1 + p2[0] - p4[0]; + /* col 1 - Top */ + *p1++ = p1ap3_0 + p2[0] + p4[0]; + *p1++ = p1ap3_1 + p2[1] + p4[1]; + + /* COL 2 */ + twR = tw2[0]; + twI = tw2[1]; + + m0 = t2[0] * twR; + m1 = t2[1] * twI; + m2 = t2[1] * twR; + m3 = t2[0] * twI; + + *p2++ = m0 + m1; + *p2++ = m2 - m3; + /* COL 3 */ + twR = tw3[0]; + twI = tw3[1]; + + m0 = t3[0] * twR; + m1 = t3[1] * twI; + m2 = t3[1] * twR; + m3 = t3[0] * twI; + + *p3++ = m0 + m1; + *p3++ = m2 - m3; + /* COL 4 */ + twR = tw4[0]; + twI = tw4[1]; + + m0 = t4[0] * twR; + m1 = t4[1] * twI; + m2 = t4[1] * twR; + m3 = t4[0] * twI; + + *p4++ = m0 + m1; + *p4++ = m2 - m3; + + /* first col */ + arm_radix8_butterfly_f32 (pCol1, L, (float32_t *) S->pTwiddle, 4U); + + /* second col */ + arm_radix8_butterfly_f32 (pCol2, L, (float32_t *) S->pTwiddle, 4U); + + /* third col */ + arm_radix8_butterfly_f32 (pCol3, L, (float32_t *) S->pTwiddle, 4U); + + /* fourth col */ + arm_radix8_butterfly_f32 (pCol4, L, (float32_t *) S->pTwiddle, 4U); +} + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the floating-point complex FFT. + @param[in] S points to an instance of the floating-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + +void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen, l; + float32_t invL, * pSrc; + + if (ifftFlag == 1U) + { + /* Conjugate input data */ + pSrc = p1 + 1; + for (l = 0; l < L; l++) + { + *pSrc = -*pSrc; + pSrc += 2; + } + } + + switch (L) + { + case 16: + case 128: + case 1024: + arm_cfft_radix8by2_f32 ( (arm_cfft_instance_f32 *) S, p1); + break; + case 32: + case 256: + case 2048: + arm_cfft_radix8by4_f32 ( (arm_cfft_instance_f32 *) S, p1); + break; + case 64: + case 512: + case 4096: + arm_radix8_butterfly_f32 ( p1, L, (float32_t *) S->pTwiddle, 1); + break; + } + + if ( bitReverseFlag ) + arm_bitreversal_32 ((uint32_t*) p1, S->bitRevLength, S->pBitRevTable); + + if (ifftFlag == 1U) + { + invL = 1.0f / (float32_t)L; + + /* Conjugate and scale output data */ + pSrc = p1; + for (l= 0; l < L; l++) + { + *pSrc++ *= invL ; + *pSrc = -(*pSrc) * invL; + pSrc++; + } + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of ComplexFFT group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f64.c new file mode 100644 index 00000000..d686eb8c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f64.c @@ -0,0 +1,318 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_f64.c + * Description: Combined Radix Decimation in Frequency CFFT Double Precision Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + + +extern void arm_radix4_butterfly_f64( + float64_t * pSrc, + uint16_t fftLen, + const float64_t * pCoef, + uint16_t twidCoefModifier); + +extern void arm_bitreversal_64( + uint64_t * pSrc, + const uint16_t bitRevLen, + const uint16_t * pBitRevTable); + +/** +* @} end of ComplexFFT group +*/ + +/* ---------------------------------------------------------------------- + * Internal helper function used by the FFTs + * ---------------------------------------------------------------------- */ + +/* +* @brief Core function for the Double Precision floating-point CFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of F64 data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to the twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @return none. +*/ + +void arm_radix4_butterfly_f64( + float64_t * pSrc, + uint16_t fftLen, + const float64_t * pCoef, + uint16_t twidCoefModifier) +{ + + float64_t co1, co2, co3, si1, si2, si3; + uint32_t ia1, ia2, ia3; + uint32_t i0, i1, i2, i3; + uint32_t n1, n2, j, k; + + float64_t t1, t2, r1, r2, s1, s2; + + + /* Initializations for the fft calculation */ + n2 = fftLen; + n1 = n2; + for (k = fftLen; k > 1U; k >>= 2U) + { + /* Initializations for the fft calculation */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* FFT Calculation */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* xa + xc */ + r1 = pSrc[(2U * i0)] + pSrc[(2U * i2)]; + + /* xa - xc */ + r2 = pSrc[(2U * i0)] - pSrc[(2U * i2)]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = r1 + t1; + + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = s1 + t2; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (r1 * co2) + (s1 * si2); + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (s1 * co2) - (r1 * si2); + + /* (xa - xc) + (yb - yd) */ + r1 = r2 + t1; + + /* (xa - xc) - (yb - yd) */ + r2 = r2 - t1; + + /* (ya - yc) - (xb - xd) */ + s1 = s2 - t2; + + /* (ya - yc) + (xb - xd) */ + s2 = s2 + t2; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (r1 * co1) + (s1 * si1); + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (s1 * co1) - (r1 * si1); + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (r2 * co3) + (s2 * si3); + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (s2 * co3) - (r2 * si3); + + i0 += n1; + } while ( i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } +} + +/* +* @brief Core function for the Double Precision floating-point CFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of F64 data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to the twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @return none. +*/ + +void arm_cfft_radix4by2_f64( + float64_t * pSrc, + uint32_t fftLen, + const float64_t * pCoef) +{ + uint32_t i, l; + uint32_t n2, ia; + float64_t xt, yt, cosVal, sinVal; + float64_t p0, p1,p2,p3,a0,a1; + + n2 = fftLen >> 1; + ia = 0; + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2*ia]; + sinVal = pCoef[2*ia + 1]; + ia++; + + l = i + n2; + + /* Butterfly implementation */ + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + } + + // first col + arm_radix4_butterfly_f64( pSrc, n2, (float64_t*)pCoef, 2U); + // second col + arm_radix4_butterfly_f64( pSrc + fftLen, n2, (float64_t*)pCoef, 2U); + +} + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the Double Precision floating-point complex FFT. + @param[in] S points to an instance of the Double Precision floating-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + +void arm_cfft_f64( + const arm_cfft_instance_f64 * S, + float64_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen, l; + float64_t invL, * pSrc; + + if (ifftFlag == 1U) + { + /* Conjugate input data */ + pSrc = p1 + 1; + for(l=0; lpTwiddle, 1U); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_f64 ( p1, L, (float64_t*)S->pTwiddle); + break; + + } + + if ( bitReverseFlag ) + arm_bitreversal_64((uint64_t*)p1, S->bitRevLength,S->pBitRevTable); + + if (ifftFlag == 1U) + { + invL = 1.0 / (float64_t)L; + /* Conjugate and scale output data */ + pSrc = p1; + for(l=0; lbitRevLength = arm_cfft_sR_##EXT##_len##SIZE.bitRevLength; \ + S->pBitRevTable = arm_cfft_sR_##EXT##_len##SIZE.pBitRevTable; \ + S->pTwiddle = arm_cfft_sR_##EXT##_len##SIZE.pTwiddle; + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the cfft f16 function + @param[in,out] S points to an instance of the floating-point CFFT structure + @param[in] fftLen fft length (number of complex samples) + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + + @par Use of this function is mandatory only for the MVE version of the FFT. + Other versions can still initialize directly the data structure using + variables declared in arm_const_structs.h + */ + +#include "dsp/transform_functions_f16.h" +#include "arm_common_tables_f16.h" +#include "arm_const_structs_f16.h" + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_vec_fft.h" +#include "arm_mve_tables_f16.h" + +arm_status arm_cfft_radix4by2_rearrange_twiddles_f16(arm_cfft_instance_f16 *S, int twidCoefModifier) +{ + + switch (S->fftLen >> (twidCoefModifier - 1)) { + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) + case 4096U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_4096_f16; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_4096_f16; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_4096_f16; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_4096_f16; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_4096_f16; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_4096_f16; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F16_1024) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048) + case 1024U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_1024_f16; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_1024_f16; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_1024_f16; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_1024_f16; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_1024_f16; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_1024_f16; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F16_256) || defined(ARM_TABLE_TWIDDLECOEF_F16_512) + case 256U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_256_f16; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_256_f16; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_256_f16; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_256_f16; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_256_f16; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_256_f16; + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F16_64) || defined(ARM_TABLE_TWIDDLECOEF_F16_128) + case 64U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_64_f16; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_64_f16; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_64_f16; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_64_f16; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_64_f16; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_64_f16; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F16_16) || defined(ARM_TABLE_TWIDDLECOEF_F16_32) + case 16U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_16_f16; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_16_f16; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_16_f16; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_16_f16; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_16_f16; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_16_f16; + break; +#endif + + default: + return(ARM_MATH_ARGUMENT_ERROR); + break; + /* invalid sizes already filtered */ + } + + return(ARM_MATH_SUCCESS); + +} + +arm_status arm_cfft_init_f16( + arm_cfft_instance_f16 * S, + uint16_t fftLen) +{ + + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { + /* Initializations of structure parameters for 4096 point FFT */ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_4096) && defined(ARM_TABLE_TWIDDLECOEF_F16_4096)) + case 4096U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_4096; + S->pTwiddle = (float16_t *)twiddleCoefF16_4096; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_2048) && defined(ARM_TABLE_TWIDDLECOEF_F16_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_2048; + S->pTwiddle = (float16_t *)twiddleCoefF16_2048; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_1024) && defined(ARM_TABLE_TWIDDLECOEF_F16_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_1024; + S->pTwiddle = (float16_t *)twiddleCoefF16_1024; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_512) && defined(ARM_TABLE_TWIDDLECOEF_F16_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_512; + S->pTwiddle = (float16_t *)twiddleCoefF16_512; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_256) && defined(ARM_TABLE_TWIDDLECOEF_F16_256)) + case 256U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_256; + S->pTwiddle = (float16_t *)twiddleCoefF16_256; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_128) && defined(ARM_TABLE_TWIDDLECOEF_F16_128)) + case 128U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_128; + S->pTwiddle = (float16_t *)twiddleCoefF16_128; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_64) && defined(ARM_TABLE_TWIDDLECOEF_F16_64)) + case 64U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_64; + S->pTwiddle = (float16_t *)twiddleCoefF16_64; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_32) && defined(ARM_TABLE_TWIDDLECOEF_F16_32)) + case 32U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_32; + S->pTwiddle = (float16_t *)twiddleCoefF16_32; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_16) && defined(ARM_TABLE_TWIDDLECOEF_F16_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_16; + S->pTwiddle = (float16_t *)twiddleCoefF16_16; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 1); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#else + +#if defined(ARM_FLOAT16_SUPPORTED) + +arm_status arm_cfft_init_f16( + arm_cfft_instance_f16 * S, + uint16_t fftLen) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096)) + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f16,4096); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f16,2048); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f16,1024); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_512) && defined(ARM_TABLE_BITREVIDX_FLT_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f16,512); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_256) && defined(ARM_TABLE_BITREVIDX_FLT_256)) + case 256U: + FFTINIT(f16,256); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_128) && defined(ARM_TABLE_BITREVIDX_FLT_128)) + case 128U: + FFTINIT(f16,128); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_64) && defined(ARM_TABLE_BITREVIDX_FLT_64)) + case 64U: + FFTINIT(f16,64); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_32) && defined(ARM_TABLE_BITREVIDX_FLT_32)) + case 32U: + FFTINIT(f16,32); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_16) && defined(ARM_TABLE_BITREVIDX_FLT_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTINIT(f16,16); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of ComplexFFT group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_f32.c new file mode 100644 index 00000000..abfab4af --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_f32.c @@ -0,0 +1,358 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_init_f32.c + * Description: Initialization function for cfft f32 instance + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define FFTINIT(EXT,SIZE) \ + S->bitRevLength = arm_cfft_sR_##EXT##_len##SIZE.bitRevLength; \ + S->pBitRevTable = arm_cfft_sR_##EXT##_len##SIZE.pBitRevTable; \ + S->pTwiddle = arm_cfft_sR_##EXT##_len##SIZE.pTwiddle; + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the cfft f32 function + @param[in,out] S points to an instance of the floating-point CFFT structure + @param[in] fftLen fft length (number of complex samples) + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + + @par Use of this function is mandatory only for the MVE version of the FFT. + Other versions can still initialize directly the data structure using + variables declared in arm_const_structs.h + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" +#include "arm_const_structs.h" + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_vec_fft.h" +#include "arm_mve_tables.h" + +arm_status arm_cfft_radix4by2_rearrange_twiddles_f32(arm_cfft_instance_f32 *S, int twidCoefModifier) +{ + + switch (S->fftLen >> (twidCoefModifier - 1)) { + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + case 4096U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_4096_f32; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_4096_f32; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_4096_f32; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_4096_f32; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_4096_f32; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_4096_f32; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + case 1024U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_1024_f32; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_1024_f32; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_1024_f32; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_1024_f32; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_1024_f32; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_1024_f32; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + case 256U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_256_f32; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_256_f32; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_256_f32; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_256_f32; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_256_f32; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_256_f32; + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + case 64U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_64_f32; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_64_f32; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_64_f32; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_64_f32; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_64_f32; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_64_f32; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + case 16U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_16_f32; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_16_f32; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_16_f32; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_16_f32; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_16_f32; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_16_f32; + break; +#endif + + default: + return(ARM_MATH_ARGUMENT_ERROR); + break; + /* invalid sizes already filtered */ + } + + return(ARM_MATH_SUCCESS); + +} + +arm_status arm_cfft_init_f32( + arm_cfft_instance_f32 * S, + uint16_t fftLen) +{ + + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { + /* Initializations of structure parameters for 4096 point FFT */ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_4096) && defined(ARM_TABLE_TWIDDLECOEF_F32_4096)) + case 4096U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_4096; + S->pTwiddle = (float32_t *)twiddleCoef_4096; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_2048) && defined(ARM_TABLE_TWIDDLECOEF_F32_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_2048; + S->pTwiddle = (float32_t *)twiddleCoef_2048; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_1024) && defined(ARM_TABLE_TWIDDLECOEF_F32_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_1024; + S->pTwiddle = (float32_t *)twiddleCoef_1024; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_512) && defined(ARM_TABLE_TWIDDLECOEF_F32_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_512; + S->pTwiddle = (float32_t *)twiddleCoef_512; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_256) && defined(ARM_TABLE_TWIDDLECOEF_F32_256)) + case 256U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_256; + S->pTwiddle = (float32_t *)twiddleCoef_256; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_128) && defined(ARM_TABLE_TWIDDLECOEF_F32_128)) + case 128U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_128; + S->pTwiddle = (float32_t *)twiddleCoef_128; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_64) && defined(ARM_TABLE_TWIDDLECOEF_F32_64)) + case 64U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_64; + S->pTwiddle = (float32_t *)twiddleCoef_64; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_32) && defined(ARM_TABLE_TWIDDLECOEF_F32_32)) + case 32U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_32; + S->pTwiddle = (float32_t *)twiddleCoef_32; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_16) && defined(ARM_TABLE_TWIDDLECOEF_F32_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_16; + S->pTwiddle = (float32_t *)twiddleCoef_16; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 1); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#else +arm_status arm_cfft_init_f32( + arm_cfft_instance_f32 * S, + uint16_t fftLen) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096)) + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f32,4096); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f32,2048); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f32,1024); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f32,512); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256)) + case 256U: + FFTINIT(f32,256); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128)) + case 128U: + FFTINIT(f32,128); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64)) + case 64U: + FFTINIT(f32,64); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32)) + case 32U: + FFTINIT(f32,32); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_BITREVIDX_FLT_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTINIT(f32,16); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of ComplexFFT group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_f64.c new file mode 100644 index 00000000..61167fdb --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_f64.c @@ -0,0 +1,150 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_init_f64.c + * Description: Initialization function for cfft f64 instance + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define FFTINIT(EXT,SIZE) \ + S->bitRevLength = arm_cfft_sR_##EXT##_len##SIZE.bitRevLength; \ + S->pBitRevTable = arm_cfft_sR_##EXT##_len##SIZE.pBitRevTable; \ + S->pTwiddle = arm_cfft_sR_##EXT##_len##SIZE.pTwiddle; + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the cfft f64 function + @param[in,out] S points to an instance of the floating-point CFFT structure + @param[in] fftLen fft length (number of complex samples) + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + + @par Use of this function is mandatory only for the MVE version of the FFT. + Other versions can still initialize directly the data structure using + variables declared in arm_const_structs.h + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" +#include "arm_const_structs.h" + + +arm_status arm_cfft_init_f64( + arm_cfft_instance_f64 * S, + uint16_t fftLen) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096)) + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f64,4096); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f64,2048); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f64,1024); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_512) && defined(ARM_TABLE_BITREVIDX_FLT_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f64,512); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_256) && defined(ARM_TABLE_BITREVIDX_FLT_256)) + case 256U: + FFTINIT(f64,256); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_128) && defined(ARM_TABLE_BITREVIDX_FLT_128)) + case 128U: + FFTINIT(f64,128); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_64) && defined(ARM_TABLE_BITREVIDX_FLT_64)) + case 64U: + FFTINIT(f64,64); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_32) && defined(ARM_TABLE_BITREVIDX_FLT_32)) + case 32U: + FFTINIT(f64,32); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_16) && defined(ARM_TABLE_BITREVIDX_FLT_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTINIT(f64,16); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_q15.c new file mode 100644 index 00000000..3cf6e3a6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_q15.c @@ -0,0 +1,356 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_init_q15.c + * Description: Initialization function for cfft q15 instance + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define FFTINIT(EXT,SIZE) \ + S->bitRevLength = arm_cfft_sR_##EXT##_len##SIZE.bitRevLength; \ + S->pBitRevTable = arm_cfft_sR_##EXT##_len##SIZE.pBitRevTable; \ + S->pTwiddle = arm_cfft_sR_##EXT##_len##SIZE.pTwiddle; + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the cfft q15 function + @param[in,out] S points to an instance of the floating-point CFFT structure + @param[in] fftLen fft length (number of complex samples) + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + + @par Use of this function is mandatory only for the MVE version of the FFT. + Other versions can still initialize directly the data structure using + variables declared in arm_const_structs.h + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" +#include "arm_const_structs.h" + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_vec_fft.h" +#include "arm_mve_tables.h" + + +arm_status arm_cfft_radix4by2_rearrange_twiddles_q15(arm_cfft_instance_q15 *S, int twidCoefModifier) +{ + + switch (S->fftLen >> (twidCoefModifier - 1)) { + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_4096) && defined(ARM_TABLE_TWIDDLECOEF_Q15_4096)) + case 4096U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_4096_q15; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_4096_q15; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_4096_q15; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_4096_q15; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_4096_q15; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_4096_q15; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_1024) && defined(ARM_TABLE_TWIDDLECOEF_Q15_1024)) || (defined(ARM_TABLE_BITREVIDX_FXT_2048) && defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)) + case 1024U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_1024_q15; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_1024_q15; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_1024_q15; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_1024_q15; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_1024_q15; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_1024_q15; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_256) && defined(ARM_TABLE_TWIDDLECOEF_Q15_256)) || (defined(ARM_TABLE_BITREVIDX_FXT_512) && defined(ARM_TABLE_TWIDDLECOEF_Q15_512)) + case 256U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_256_q15; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_256_q15; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_256_q15; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_256_q15; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_256_q15; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_256_q15; + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_64) && defined(ARM_TABLE_TWIDDLECOEF_Q15_64)) || (defined(ARM_TABLE_BITREVIDX_FXT_128) && defined(ARM_TABLE_TWIDDLECOEF_Q15_128)) + case 64U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_64_q15; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_64_q15; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_64_q15; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_64_q15; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_64_q15; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_64_q15; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_16) && defined(ARM_TABLE_TWIDDLECOEF_Q15_16)) || (defined(ARM_TABLE_BITREVIDX_FXT_32) && defined(ARM_TABLE_TWIDDLECOEF_Q15_32)) + case 16U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_16_q15; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_16_q15; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_16_q15; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_16_q15; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_16_q15; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_16_q15; + break; +#endif + + default: + return(ARM_MATH_ARGUMENT_ERROR); + break; + /* invalid sizes already filtered */ + } + + return(ARM_MATH_SUCCESS); + +} + + + +arm_status arm_cfft_init_q15( + arm_cfft_instance_q15 * S, + uint16_t fftLen) +{ + + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { + /* Initializations of structure parameters for 4096 point FFT */ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_4096) && defined(ARM_TABLE_TWIDDLECOEF_Q15_4096)) + case 4096U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_4096; + S->pTwiddle = (q15_t *)twiddleCoef_4096_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_2048) && defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_2048; + S->pTwiddle = (q15_t *)twiddleCoef_2048_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_1024) && defined(ARM_TABLE_TWIDDLECOEF_Q15_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_1024; + S->pTwiddle = (q15_t *)twiddleCoef_1024_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_512) && defined(ARM_TABLE_TWIDDLECOEF_Q15_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_512; + S->pTwiddle = (q15_t *)twiddleCoef_512_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_256) && defined(ARM_TABLE_TWIDDLECOEF_Q15_256)) + case 256U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_256; + S->pTwiddle = (q15_t *)twiddleCoef_256_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_128) && defined(ARM_TABLE_TWIDDLECOEF_Q15_128)) + case 128U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_128; + S->pTwiddle = (q15_t *)twiddleCoef_128_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_64) && defined(ARM_TABLE_TWIDDLECOEF_Q15_64)) + case 64U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_64; + S->pTwiddle = (q15_t *)twiddleCoef_64_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_32) && defined(ARM_TABLE_TWIDDLECOEF_Q15_32)) + case 32U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_32; + S->pTwiddle = (q15_t *)twiddleCoef_32_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_16) && defined(ARM_TABLE_TWIDDLECOEF_Q15_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_16; + S->pTwiddle = (q15_t *)twiddleCoef_16_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 1); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#else +arm_status arm_cfft_init_q15( + arm_cfft_instance_q15 * S, + uint16_t fftLen) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q15,4096); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q15,2048); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q15,1024); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q15,512); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) + case 256U: + FFTINIT(q15,256); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) + case 128U: + FFTINIT(q15,128); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) + case 64U: + FFTINIT(q15,64); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) + case 32U: + FFTINIT(q15,32); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTINIT(q15,16); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of ComplexFFT group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_q31.c new file mode 100644 index 00000000..3722a680 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_q31.c @@ -0,0 +1,356 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_init_q31.c + * Description: Initialization function for cfft q31 instance + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define FFTINIT(EXT,SIZE) \ + S->bitRevLength = arm_cfft_sR_##EXT##_len##SIZE.bitRevLength; \ + S->pBitRevTable = arm_cfft_sR_##EXT##_len##SIZE.pBitRevTable; \ + S->pTwiddle = arm_cfft_sR_##EXT##_len##SIZE.pTwiddle; + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the cfft q31 function + @param[in,out] S points to an instance of the floating-point CFFT structure + @param[in] fftLen fft length (number of complex samples) + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + + @par Use of this function is mandatory only for the MVE version of the FFT. + Other versions can still initialize directly the data structure using + variables declared in arm_const_structs.h + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" +#include "arm_const_structs.h" + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_vec_fft.h" +#include "arm_mve_tables.h" + + +arm_status arm_cfft_radix4by2_rearrange_twiddles_q31(arm_cfft_instance_q31 *S, int twidCoefModifier) +{ + + switch (S->fftLen >> (twidCoefModifier - 1)) { + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_4096) && defined(ARM_TABLE_TWIDDLECOEF_Q31_4096)) + case 4096U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_4096_q31; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_4096_q31; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_4096_q31; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_4096_q31; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_4096_q31; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_4096_q31; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_1024) && defined(ARM_TABLE_TWIDDLECOEF_Q31_1024)) || (defined(ARM_TABLE_BITREVIDX_FXT_2048) && defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)) + case 1024U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_1024_q31; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_1024_q31; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_1024_q31; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_1024_q31; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_1024_q31; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_1024_q31; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_256) && defined(ARM_TABLE_TWIDDLECOEF_Q31_256)) || (defined(ARM_TABLE_BITREVIDX_FXT_512) && defined(ARM_TABLE_TWIDDLECOEF_Q31_512)) + case 256U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_256_q31; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_256_q31; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_256_q31; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_256_q31; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_256_q31; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_256_q31; + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_64) && defined(ARM_TABLE_TWIDDLECOEF_Q31_64)) || (defined(ARM_TABLE_BITREVIDX_FXT_128) && defined(ARM_TABLE_TWIDDLECOEF_Q31_128)) + case 64U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_64_q31; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_64_q31; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_64_q31; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_64_q31; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_64_q31; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_64_q31; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_16) && defined(ARM_TABLE_TWIDDLECOEF_Q31_16)) || (defined(ARM_TABLE_BITREVIDX_FXT_32) && defined(ARM_TABLE_TWIDDLECOEF_Q31_32)) + case 16U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_16_q31; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_16_q31; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_16_q31; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_16_q31; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_16_q31; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_16_q31; + break; +#endif + + default: + return(ARM_MATH_ARGUMENT_ERROR); + break; + /* invalid sizes already filtered */ + } + + return(ARM_MATH_SUCCESS); + +} + + + +arm_status arm_cfft_init_q31( + arm_cfft_instance_q31 * S, + uint16_t fftLen) +{ + + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { + /* Initializations of structure parameters for 4096 point FFT */ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_4096) && defined(ARM_TABLE_TWIDDLECOEF_Q31_4096)) + case 4096U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_4096; + S->pTwiddle = (q31_t *)twiddleCoef_4096_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_2048) && defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_2048; + S->pTwiddle = (q31_t *)twiddleCoef_2048_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_1024) && defined(ARM_TABLE_TWIDDLECOEF_Q31_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_1024; + S->pTwiddle = (q31_t *)twiddleCoef_1024_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_512) && defined(ARM_TABLE_TWIDDLECOEF_Q31_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_512; + S->pTwiddle = (q31_t *)twiddleCoef_512_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_256) && defined(ARM_TABLE_TWIDDLECOEF_Q31_256)) + case 256U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_256; + S->pTwiddle = (q31_t *)twiddleCoef_256_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_128) && defined(ARM_TABLE_TWIDDLECOEF_Q31_128)) + case 128U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_128; + S->pTwiddle = (q31_t *)twiddleCoef_128_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_64) && defined(ARM_TABLE_TWIDDLECOEF_Q31_64)) + case 64U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_64; + S->pTwiddle = (q31_t *)twiddleCoef_64_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_32) && defined(ARM_TABLE_TWIDDLECOEF_Q31_32)) + case 32U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_32; + S->pTwiddle = (q31_t *)twiddleCoef_32_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_16) && defined(ARM_TABLE_TWIDDLECOEF_Q31_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_16; + S->pTwiddle = (q31_t *)twiddleCoef_16_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 1); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#else +arm_status arm_cfft_init_q31( + arm_cfft_instance_q31 * S, + uint16_t fftLen) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q31,4096); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q31,2048); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q31,1024); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q31,512); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) + case 256U: + FFTINIT(q31,256); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) + case 128U: + FFTINIT(q31,128); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) + case 64U: + FFTINIT(q31,64); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) + case 32U: + FFTINIT(q31,32); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTINIT(q31,16); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of ComplexFFT group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.c new file mode 100644 index 00000000..74a6e7aa --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.c @@ -0,0 +1,893 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_q15.c + * Description: Combined Radix Decimation in Q15 Frequency CFFT processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_vec_fft.h" + + +static void _arm_radix4_butterfly_q15_mve( + const arm_cfft_instance_q15 * S, + q15_t *pSrc, + uint32_t fftLen) +{ + q15x8_t vecTmp0, vecTmp1; + q15x8_t vecSum0, vecDiff0, vecSum1, vecDiff1; + q15x8_t vecA, vecB, vecC, vecD; + uint32_t blkCnt; + uint32_t n1, n2; + uint32_t stage = 0; + int32_t iter = 1; + static const int32_t strides[4] = { + (0 - 16) * (int32_t)sizeof(q15_t *), (4 - 16) * (int32_t)sizeof(q15_t *), + (8 - 16) * (int32_t)sizeof(q15_t *), (12 - 16) * (int32_t)sizeof(q15_t *) + }; + + /* + * Process first stages + * Each stage in middle stages provides two down scaling of the input + */ + n2 = fftLen; + n1 = n2; + n2 >>= 2u; + + for (int k = fftLen / 4u; k > 1; k >>= 2u) + { + q15_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + q15_t const *p_rearranged_twiddle_tab_stride3 = &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + q15_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + + q15_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + q15_t *inA = pBase; + q15_t *inB = inA + n2 * CMPLX_DIM; + q15_t *inC = inB + n2 * CMPLX_DIM; + q15_t *inD = inC + n2 * CMPLX_DIM; + q15_t const *pW1 = p_rearranged_twiddle_tab_stride1; + q15_t const *pW2 = p_rearranged_twiddle_tab_stride2; + q15_t const *pW3 = p_rearranged_twiddle_tab_stride3; + q15x8_t vecW; + + blkCnt = n2 / 4; + /* + * load 4 x q15 complex pair + */ + vecA = vldrhq_s16(inA); + vecC = vldrhq_s16(inC); + while (blkCnt > 0U) + { + vecB = vldrhq_s16(inB); + vecD = vldrhq_s16(inD); + + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vhaddq(vecSum0, vecSum1); + vst1q(inA, vecTmp0); + inA += 8; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vhsubq(vecSum0, vecSum1); + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW2); + pW2 += 8; + vecTmp1 = MVE_CMPLX_MULT_FX_AxB(vecW, vecTmp0, q15x8_t); + + vst1q(inB, vecTmp1); + inB += 8; + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW1); + pW1 += 8; + vecTmp1 = MVE_CMPLX_MULT_FX_AxB(vecW, vecTmp0, q15x8_t); + vst1q(inC, vecTmp1); + inC += 8; + + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 8; + vecTmp1 = MVE_CMPLX_MULT_FX_AxB(vecW, vecTmp0, q15x8_t); + vst1q(inD, vecTmp1); + inD += 8; + + vecA = vldrhq_s16(inA); + vecC = vldrhq_s16(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32 ((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* + * load scheduling + */ + vecA = (q15x8_t) vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 8); + + blkCnt = (fftLen >> 4); + while (blkCnt > 0U) + { + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecB = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 4); + vecD = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 12); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * pre-load for next iteration + */ + vecA = (q15x8_t) vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 8); + + vecTmp0 = vhaddq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64, (int32x4_t) vecTmp0); + + vecTmp0 = vhsubq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 4, (int32x4_t) vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 8, (int32x4_t) vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 12, (int32x4_t) vecTmp0); + + blkCnt--; + } + +} + +static void arm_cfft_radix4by2_q15_mve(const arm_cfft_instance_q15 *S, q15_t *pSrc, uint32_t fftLen) +{ + uint32_t n2; + q15_t *pIn0; + q15_t *pIn1; + const q15_t *pCoef = S->pTwiddle; + uint32_t blkCnt; + q15x8_t vecIn0, vecIn1, vecSum, vecDiff; + q15x8_t vecCmplxTmp, vecTw; + q15_t const *pCoefVec; + + n2 = fftLen >> 1; + + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + pCoefVec = pCoef; + + blkCnt = n2 / 4; + + while (blkCnt > 0U) + { + vecIn0 = *(q15x8_t *) pIn0; + vecIn1 = *(q15x8_t *) pIn1; + + vecIn0 = vecIn0 >> 1; + vecIn1 = vecIn1 >> 1; + vecSum = vhaddq(vecIn0, vecIn1); + vst1q(pIn0, vecSum); + pIn0 += 8; + + vecTw = vld1q(pCoefVec); + pCoefVec += 8; + + vecDiff = vhsubq(vecIn0, vecIn1); + vecCmplxTmp = MVE_CMPLX_MULT_FX_AxConjB(vecDiff, vecTw, q15x8_t); + vst1q(pIn1, vecCmplxTmp); + pIn1 += 8; + + blkCnt--; + } + + _arm_radix4_butterfly_q15_mve(S, pSrc, n2); + + _arm_radix4_butterfly_q15_mve(S, pSrc + fftLen, n2); + + + pIn0 = pSrc; + blkCnt = (fftLen << 1) >> 3; + while (blkCnt > 0U) + { + vecIn0 = *(q15x8_t *) pIn0; + vecIn0 = vecIn0 << 1; + vst1q(pIn0, vecIn0); + pIn0 += 8; + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (fftLen << 1) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecIn0 = *(q15x8_t *) pIn0; + vecIn0 = vecIn0 << 1; + vstrhq_p(pIn0, vecIn0, p0); + } +} + +static void _arm_radix4_butterfly_inverse_q15_mve(const arm_cfft_instance_q15 *S,q15_t *pSrc, uint32_t fftLen) +{ + q15x8_t vecTmp0, vecTmp1; + q15x8_t vecSum0, vecDiff0, vecSum1, vecDiff1; + q15x8_t vecA, vecB, vecC, vecD; + uint32_t blkCnt; + uint32_t n1, n2; + uint32_t stage = 0; + int32_t iter = 1; + static const int32_t strides[4] = { + (0 - 16) * (int32_t)sizeof(q15_t *), (4 - 16) * (int32_t)sizeof(q15_t *), + (8 - 16) * (int32_t)sizeof(q15_t *), (12 - 16) * (int32_t)sizeof(q15_t *) + }; + + + /* + * Process first stages + * Each stage in middle stages provides two down scaling of the input + */ + n2 = fftLen; + n1 = n2; + n2 >>= 2u; + + for (int k = fftLen / 4u; k > 1; k >>= 2u) + { + q15_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + q15_t const *p_rearranged_twiddle_tab_stride3 = &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + q15_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + + q15_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + q15_t *inA = pBase; + q15_t *inB = inA + n2 * CMPLX_DIM; + q15_t *inC = inB + n2 * CMPLX_DIM; + q15_t *inD = inC + n2 * CMPLX_DIM; + q15_t const *pW1 = p_rearranged_twiddle_tab_stride1; + q15_t const *pW2 = p_rearranged_twiddle_tab_stride2; + q15_t const *pW3 = p_rearranged_twiddle_tab_stride3; + q15x8_t vecW; + + + blkCnt = n2 / 4; + /* + * load 4 x q15 complex pair + */ + vecA = vldrhq_s16(inA); + vecC = vldrhq_s16(inC); + while (blkCnt > 0U) + { + vecB = vldrhq_s16(inB); + vecD = vldrhq_s16(inD); + + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vhaddq(vecSum0, vecSum1); + vst1q(inA, vecTmp0); + inA += 8; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vhsubq(vecSum0, vecSum1); + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW2); + pW2 += 8; + vecTmp1 = MVE_CMPLX_MULT_FX_AxConjB(vecTmp0, vecW, q15x8_t); + + vst1q(inB, vecTmp1); + inB += 8; + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW1); + pW1 += 8; + vecTmp1 = MVE_CMPLX_MULT_FX_AxConjB(vecTmp0, vecW, q15x8_t); + vst1q(inC, vecTmp1); + inC += 8; + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 8; + vecTmp1 = MVE_CMPLX_MULT_FX_AxConjB(vecTmp0, vecW, q15x8_t); + vst1q(inD, vecTmp1); + inD += 8; + + vecA = vldrhq_s16(inA); + vecC = vldrhq_s16(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* + * load scheduling + */ + vecA = (q15x8_t) vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 8); + + blkCnt = (fftLen >> 4); + while (blkCnt > 0U) + { + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecB = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 4); + vecD = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 12); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * pre-load for next iteration + */ + vecA = (q15x8_t) vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 8); + + vecTmp0 = vhaddq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64, (int32x4_t) vecTmp0); + + vecTmp0 = vhsubq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 4, (int32x4_t) vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 8, (int32x4_t) vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 12, (int32x4_t) vecTmp0); + + blkCnt--; + } +} + +static void arm_cfft_radix4by2_inverse_q15_mve(const arm_cfft_instance_q15 *S, q15_t *pSrc, uint32_t fftLen) +{ + uint32_t n2; + q15_t *pIn0; + q15_t *pIn1; + const q15_t *pCoef = S->pTwiddle; + + uint32_t blkCnt; + q15x8_t vecIn0, vecIn1, vecSum, vecDiff; + q15x8_t vecCmplxTmp, vecTw; + q15_t const *pCoefVec; + + n2 = fftLen >> 1; + + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + pCoefVec = pCoef; + + blkCnt = n2 / 4; + + while (blkCnt > 0U) + { + vecIn0 = *(q15x8_t *) pIn0; + vecIn1 = *(q15x8_t *) pIn1; + + vecIn0 = vecIn0 >> 1; + vecIn1 = vecIn1 >> 1; + vecSum = vhaddq(vecIn0, vecIn1); + vst1q(pIn0, vecSum); + pIn0 += 8; + + vecTw = vld1q(pCoefVec); + pCoefVec += 8; + + vecDiff = vhsubq(vecIn0, vecIn1); + vecCmplxTmp = vqrdmlsdhq(vuninitializedq_s16() , vecDiff, vecTw); + vecCmplxTmp = vqrdmladhxq(vecCmplxTmp, vecDiff, vecTw); + vst1q(pIn1, vecCmplxTmp); + pIn1 += 8; + + blkCnt--; + } + + + _arm_radix4_butterfly_inverse_q15_mve(S, pSrc, n2); + + _arm_radix4_butterfly_inverse_q15_mve(S, pSrc + fftLen, n2); + + pIn0 = pSrc; + blkCnt = (fftLen << 1) >> 3; + while (blkCnt > 0U) + { + vecIn0 = *(q15x8_t *) pIn0; + vecIn0 = vecIn0 << 1; + vst1q(pIn0, vecIn0); + pIn0 += 8; + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (fftLen << 1) & 7; + while (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecIn0 = *(q15x8_t *) pIn0; + vecIn0 = vecIn0 << 1; + vstrhq_p(pIn0, vecIn0, p0); + } +} + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for Q15 complex FFT. + @param[in] S points to an instance of Q15 CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * pSrc, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t fftLen = S->fftLen; + + if (ifftFlag == 1U) { + + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_inverse_q15_mve(S, pSrc, fftLen); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_inverse_q15_mve(S, pSrc, fftLen); + break; + } + } else { + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_q15_mve(S, pSrc, fftLen); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_q15_mve(S, pSrc, fftLen); + break; + } + } + + + if (bitReverseFlag) + { + + arm_bitreversal_16_inpl_mve((uint16_t*)pSrc, S->bitRevLength, S->pBitRevTable); + + } +} + +#else + +extern void arm_radix4_butterfly_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint32_t twidCoefModifier); + +extern void arm_radix4_butterfly_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint32_t twidCoefModifier); + +extern void arm_bitreversal_16( + uint16_t * pSrc, + const uint16_t bitRevLen, + const uint16_t * pBitRevTable); + +void arm_cfft_radix4by2_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef); + +void arm_cfft_radix4by2_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for Q15 complex FFT. + @param[in] S points to an instance of Q15 CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen; + + if (ifftFlag == 1U) + { + switch (L) + { + case 16: + case 64: + case 256: + case 1024: + case 4096: + arm_radix4_butterfly_inverse_q15 ( p1, L, (q15_t*)S->pTwiddle, 1 ); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_inverse_q15 ( p1, L, S->pTwiddle ); + break; + } + } + else + { + switch (L) + { + case 16: + case 64: + case 256: + case 1024: + case 4096: + arm_radix4_butterfly_q15 ( p1, L, (q15_t*)S->pTwiddle, 1 ); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_q15 ( p1, L, S->pTwiddle ); + break; + } + } + + if ( bitReverseFlag ) + arm_bitreversal_16 ((uint16_t*) p1, S->bitRevLength, S->pBitRevTable); +} + +/** + @} end of ComplexFFT group + */ + +void arm_cfft_radix4by2_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef) +{ + uint32_t i; + uint32_t n2; + q15_t p0, p1, p2, p3; +#if defined (ARM_MATH_DSP) + q31_t T, S, R; + q31_t coeff, out1, out2; + const q15_t *pC = pCoef; + q15_t *pSi = pSrc; + q15_t *pSl = pSrc + fftLen; +#else + uint32_t l; + q15_t xt, yt, cosVal, sinVal; +#endif + + n2 = fftLen >> 1U; + +#if defined (ARM_MATH_DSP) + + for (i = n2; i > 0; i--) + { + coeff = read_q15x2_ia (&pC); + + T = read_q15x2 (pSi); + T = __SHADD16(T, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + S = read_q15x2 (pSl); + S = __SHADD16(S, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + R = __QSUB16(T, S); + + write_q15x2_ia (&pSi, __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(coeff, R) >> 16U; + out2 = __SMUSDX(coeff, R); +#else + out1 = __SMUSDX(R, coeff) >> 16U; + out2 = __SMUAD(coeff, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2_ia (&pSl, (q31_t)__PKHBT( out1, out2, 0 ) ); + } + +#else /* #if defined (ARM_MATH_DSP) */ + + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2 * i]; + sinVal = pCoef[2 * i + 1]; + + l = i + n2; + + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16U)) + + ((int16_t) (((q31_t) yt * sinVal) >> 16U)) ); + + pSrc[2 * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16U)) - + ((int16_t) (((q31_t) xt * sinVal) >> 16U)) ); + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* first col */ + arm_radix4_butterfly_q15( pSrc, n2, (q15_t*)pCoef, 2U); + + /* second col */ + arm_radix4_butterfly_q15( pSrc + fftLen, n2, (q15_t*)pCoef, 2U); + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + p0 = pSrc[4 * i + 0]; + p1 = pSrc[4 * i + 1]; + p2 = pSrc[4 * i + 2]; + p3 = pSrc[4 * i + 3]; + + p0 <<= 1U; + p1 <<= 1U; + p2 <<= 1U; + p3 <<= 1U; + + pSrc[4 * i + 0] = p0; + pSrc[4 * i + 1] = p1; + pSrc[4 * i + 2] = p2; + pSrc[4 * i + 3] = p3; + } + +} + +void arm_cfft_radix4by2_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef) +{ + uint32_t i; + uint32_t n2; + q15_t p0, p1, p2, p3; +#if defined (ARM_MATH_DSP) + q31_t T, S, R; + q31_t coeff, out1, out2; + const q15_t *pC = pCoef; + q15_t *pSi = pSrc; + q15_t *pSl = pSrc + fftLen; +#else + uint32_t l; + q15_t xt, yt, cosVal, sinVal; +#endif + + n2 = fftLen >> 1U; + +#if defined (ARM_MATH_DSP) + + for (i = n2; i > 0; i--) + { + coeff = read_q15x2_ia (&pC); + + T = read_q15x2 (pSi); + T = __SHADD16(T, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + S = read_q15x2 (pSl); + S = __SHADD16(S, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + R = __QSUB16(T, S); + + write_q15x2_ia (&pSi, __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(coeff, R) >> 16U; + out2 = __SMUADX(coeff, R); +#else + out1 = __SMUADX(R, coeff) >> 16U; + out2 = __SMUSD(__QSUB(0, coeff), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2_ia (&pSl, (q31_t)__PKHBT( out1, out2, 0 )); + } + +#else /* #if defined (ARM_MATH_DSP) */ + + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2 * i]; + sinVal = pCoef[2 * i + 1]; + + l = i + n2; + + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16U)) - + ((int16_t) (((q31_t) yt * sinVal) >> 16U)) ); + + pSrc[2 * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16U)) + + ((int16_t) (((q31_t) xt * sinVal) >> 16U)) ); + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* first col */ + arm_radix4_butterfly_inverse_q15( pSrc, n2, (q15_t*)pCoef, 2U); + + /* second col */ + arm_radix4_butterfly_inverse_q15( pSrc + fftLen, n2, (q15_t*)pCoef, 2U); + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + p0 = pSrc[4 * i + 0]; + p1 = pSrc[4 * i + 1]; + p2 = pSrc[4 * i + 2]; + p3 = pSrc[4 * i + 3]; + + p0 <<= 1U; + p1 <<= 1U; + p2 <<= 1U; + p3 <<= 1U; + + pSrc[4 * i + 0] = p0; + pSrc[4 * i + 1] = p1; + pSrc[4 * i + 2] = p2; + pSrc[4 * i + 3] = p3; + } +} + +#endif /* defined(ARM_MATH_MVEI) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c new file mode 100644 index 00000000..78ce5053 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c @@ -0,0 +1,847 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_q31.c + * Description: Combined Radix Decimation in Frequency CFFT fixed point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + + + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_vec_fft.h" + + +static void _arm_radix4_butterfly_q31_mve( + const arm_cfft_instance_q31 * S, + q31_t *pSrc, + uint32_t fftLen) +{ + q31x4_t vecTmp0, vecTmp1; + q31x4_t vecSum0, vecDiff0, vecSum1, vecDiff1; + q31x4_t vecA, vecB, vecC, vecD; + uint32_t blkCnt; + uint32_t n1, n2; + uint32_t stage = 0; + int32_t iter = 1; + static const int32_t strides[4] = { + (0 - 16) * (int32_t)sizeof(q31_t *), (1 - 16) * (int32_t)sizeof(q31_t *), + (8 - 16) * (int32_t)sizeof(q31_t *), (9 - 16) * (int32_t)sizeof(q31_t *) + }; + + + /* + * Process first stages + * Each stage in middle stages provides two down scaling of the input + */ + n2 = fftLen; + n1 = n2; + n2 >>= 2u; + + for (int k = fftLen / 4u; k > 1; k >>= 2u) + { + q31_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + q31_t const *p_rearranged_twiddle_tab_stride3 = &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + q31_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + + q31_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + q31_t *inA = pBase; + q31_t *inB = inA + n2 * CMPLX_DIM; + q31_t *inC = inB + n2 * CMPLX_DIM; + q31_t *inD = inC + n2 * CMPLX_DIM; + q31_t const *pW1 = p_rearranged_twiddle_tab_stride1; + q31_t const *pW2 = p_rearranged_twiddle_tab_stride2; + q31_t const *pW3 = p_rearranged_twiddle_tab_stride3; + q31x4_t vecW; + + + blkCnt = n2 / 2; + /* + * load 2 x q31 complex pair + */ + vecA = vldrwq_s32(inA); + vecC = vldrwq_s32(inC); + while (blkCnt > 0U) + { + vecB = vldrwq_s32(inB); + vecD = vldrwq_s32(inD); + + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vhaddq(vecSum0, vecSum1); + vst1q(inA, vecTmp0); + inA += 4; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vhsubq(vecSum0, vecSum1); + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW2); + pW2 += 4; + vecTmp1 = MVE_CMPLX_MULT_FX_AxB(vecW, vecTmp0, q31x4_t); + + vst1q(inB, vecTmp1); + inB += 4; + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW1); + pW1 += 4; + vecTmp1 = MVE_CMPLX_MULT_FX_AxB(vecW, vecTmp0, q31x4_t); + vst1q(inC, vecTmp1); + inC += 4; + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 4; + vecTmp1 = MVE_CMPLX_MULT_FX_AxB(vecW, vecTmp0, q31x4_t); + vst1q(inD, vecTmp1); + inD += 4; + + vecA = vldrwq_s32(inA); + vecC = vldrwq_s32(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * End of 1st stages process + * data is in 11.21(q21) format for the 1024 point as there are 3 middle stages + * data is in 9.23(q23) format for the 256 point as there are 2 middle stages + * data is in 7.25(q25) format for the 64 point as there are 1 middle stage + * data is in 5.27(q27) format for the 16 point as there are no middle stages + */ + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* + * load scheduling + */ + vecA = vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_s32(vecScGathAddr, 16); + + blkCnt = (fftLen >> 3); + while (blkCnt > 0U) + { + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecB = vldrwq_gather_base_s32(vecScGathAddr, 8); + vecD = vldrwq_gather_base_s32(vecScGathAddr, 24); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * pre-load for next iteration + */ + vecA = vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_s32(vecScGathAddr, 16); + + vecTmp0 = vhaddq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64, vecTmp0); + + vecTmp0 = vhsubq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 8, vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 16, vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 24, vecTmp0); + + blkCnt--; + } + + /* + * output is in 11.21(q21) format for the 1024 point + * output is in 9.23(q23) format for the 256 point + * output is in 7.25(q25) format for the 64 point + * output is in 5.27(q27) format for the 16 point + */ +} + + +static void arm_cfft_radix4by2_q31_mve(const arm_cfft_instance_q31 *S, q31_t *pSrc, uint32_t fftLen) +{ + uint32_t n2; + q31_t *pIn0; + q31_t *pIn1; + const q31_t *pCoef = S->pTwiddle; + uint32_t blkCnt; + q31x4_t vecIn0, vecIn1, vecSum, vecDiff; + q31x4_t vecCmplxTmp, vecTw; + + n2 = fftLen >> 1; + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + + blkCnt = n2 / 2; + + while (blkCnt > 0U) + { + vecIn0 = vld1q_s32(pIn0); + vecIn1 = vld1q_s32(pIn1); + + vecIn0 = vecIn0 >> 1; + vecIn1 = vecIn1 >> 1; + vecSum = vhaddq(vecIn0, vecIn1); + vst1q(pIn0, vecSum); + pIn0 += 4; + + vecTw = vld1q_s32(pCoef); + pCoef += 4; + vecDiff = vhsubq(vecIn0, vecIn1); + + vecCmplxTmp = MVE_CMPLX_MULT_FX_AxConjB(vecDiff, vecTw, q31x4_t); + vst1q(pIn1, vecCmplxTmp); + pIn1 += 4; + + blkCnt--; + } + + _arm_radix4_butterfly_q31_mve(S, pSrc, n2); + + _arm_radix4_butterfly_q31_mve(S, pSrc + fftLen, n2); + + pIn0 = pSrc; + blkCnt = (fftLen << 1) >> 2; + while (blkCnt > 0U) + { + vecIn0 = vld1q_s32(pIn0); + vecIn0 = vecIn0 << 1; + vst1q(pIn0, vecIn0); + pIn0 += 4; + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (fftLen << 1) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecIn0 = vld1q_s32(pIn0); + vecIn0 = vecIn0 << 1; + vstrwq_p(pIn0, vecIn0, p0); + } + +} + +static void _arm_radix4_butterfly_inverse_q31_mve( + const arm_cfft_instance_q31 *S, + q31_t *pSrc, + uint32_t fftLen) +{ + q31x4_t vecTmp0, vecTmp1; + q31x4_t vecSum0, vecDiff0, vecSum1, vecDiff1; + q31x4_t vecA, vecB, vecC, vecD; + uint32_t blkCnt; + uint32_t n1, n2; + uint32_t stage = 0; + int32_t iter = 1; + static const int32_t strides[4] = { + (0 - 16) * (int32_t)sizeof(q31_t *), (1 - 16) * (int32_t)sizeof(q31_t *), + (8 - 16) * (int32_t)sizeof(q31_t *), (9 - 16) * (int32_t)sizeof(q31_t *) + }; + + /* + * Process first stages + * Each stage in middle stages provides two down scaling of the input + */ + n2 = fftLen; + n1 = n2; + n2 >>= 2u; + + for (int k = fftLen / 4u; k > 1; k >>= 2u) + { + q31_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + q31_t const *p_rearranged_twiddle_tab_stride3 = &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + q31_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + + q31_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + q31_t *inA = pBase; + q31_t *inB = inA + n2 * CMPLX_DIM; + q31_t *inC = inB + n2 * CMPLX_DIM; + q31_t *inD = inC + n2 * CMPLX_DIM; + q31_t const *pW1 = p_rearranged_twiddle_tab_stride1; + q31_t const *pW2 = p_rearranged_twiddle_tab_stride2; + q31_t const *pW3 = p_rearranged_twiddle_tab_stride3; + q31x4_t vecW; + + blkCnt = n2 / 2; + /* + * load 2 x q31 complex pair + */ + vecA = vldrwq_s32(inA); + vecC = vldrwq_s32(inC); + while (blkCnt > 0U) + { + vecB = vldrwq_s32(inB); + vecD = vldrwq_s32(inD); + + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vhaddq(vecSum0, vecSum1); + vst1q(inA, vecTmp0); + inA += 4; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vhsubq(vecSum0, vecSum1); + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW2); + pW2 += 4; + vecTmp1 = MVE_CMPLX_MULT_FX_AxConjB(vecTmp0, vecW, q31x4_t); + + vst1q(inB, vecTmp1); + inB += 4; + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW1); + pW1 += 4; + vecTmp1 = MVE_CMPLX_MULT_FX_AxConjB(vecTmp0, vecW, q31x4_t); + vst1q(inC, vecTmp1); + inC += 4; + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 4; + vecTmp1 = MVE_CMPLX_MULT_FX_AxConjB(vecTmp0, vecW, q31x4_t); + vst1q(inD, vecTmp1); + inD += 4; + + vecA = vldrwq_s32(inA); + vecC = vldrwq_s32(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * End of 1st stages process + * data is in 11.21(q21) format for the 1024 point as there are 3 middle stages + * data is in 9.23(q23) format for the 256 point as there are 2 middle stages + * data is in 7.25(q25) format for the 64 point as there are 1 middle stage + * data is in 5.27(q27) format for the 16 point as there are no middle stages + */ + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* + * load scheduling + */ + vecA = vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_s32(vecScGathAddr, 16); + + blkCnt = (fftLen >> 3); + while (blkCnt > 0U) + { + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecB = vldrwq_gather_base_s32(vecScGathAddr, 8); + vecD = vldrwq_gather_base_s32(vecScGathAddr, 24); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * pre-load for next iteration + */ + vecA = vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_s32(vecScGathAddr, 16); + + vecTmp0 = vhaddq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64, vecTmp0); + + vecTmp0 = vhsubq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 8, vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 16, vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 24, vecTmp0); + + blkCnt--; + } + /* + * output is in 11.21(q21) format for the 1024 point + * output is in 9.23(q23) format for the 256 point + * output is in 7.25(q25) format for the 64 point + * output is in 5.27(q27) format for the 16 point + */ +} + +static void arm_cfft_radix4by2_inverse_q31_mve(const arm_cfft_instance_q31 *S, q31_t *pSrc, uint32_t fftLen) +{ + uint32_t n2; + q31_t *pIn0; + q31_t *pIn1; + const q31_t *pCoef = S->pTwiddle; + + //uint16_t twidCoefModifier = arm_cfft_radix2_twiddle_factor(S->fftLen); + //q31_t twidIncr = (2 * twidCoefModifier * sizeof(q31_t)); + uint32_t blkCnt; + //uint64x2_t vecOffs; + q31x4_t vecIn0, vecIn1, vecSum, vecDiff; + q31x4_t vecCmplxTmp, vecTw; + + n2 = fftLen >> 1; + + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + //vecOffs[0] = 0; + //vecOffs[1] = (uint64_t) twidIncr; + blkCnt = n2 / 2; + + while (blkCnt > 0U) + { + vecIn0 = vld1q_s32(pIn0); + vecIn1 = vld1q_s32(pIn1); + + vecIn0 = vecIn0 >> 1; + vecIn1 = vecIn1 >> 1; + vecSum = vhaddq(vecIn0, vecIn1); + vst1q(pIn0, vecSum); + pIn0 += 4; + + //vecTw = (q31x4_t) vldrdq_gather_offset_s64(pCoef, vecOffs); + vecTw = vld1q_s32(pCoef); + pCoef += 4; + vecDiff = vhsubq(vecIn0, vecIn1); + + vecCmplxTmp = MVE_CMPLX_MULT_FX_AxB(vecDiff, vecTw, q31x4_t); + vst1q(pIn1, vecCmplxTmp); + pIn1 += 4; + + //vecOffs = vaddq((q31x4_t) vecOffs, 2 * twidIncr); + blkCnt--; + } + + _arm_radix4_butterfly_inverse_q31_mve(S, pSrc, n2); + + _arm_radix4_butterfly_inverse_q31_mve(S, pSrc + fftLen, n2); + + pIn0 = pSrc; + blkCnt = (fftLen << 1) >> 2; + while (blkCnt > 0U) + { + vecIn0 = vld1q_s32(pIn0); + vecIn0 = vecIn0 << 1; + vst1q(pIn0, vecIn0); + pIn0 += 4; + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (fftLen << 1) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecIn0 = vld1q_s32(pIn0); + vecIn0 = vecIn0 << 1; + vstrwq_p(pIn0, vecIn0, p0); + } + +} + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the Q31 complex FFT. + @param[in] S points to an instance of the fixed-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * pSrc, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t fftLen = S->fftLen; + + if (ifftFlag == 1U) { + + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_inverse_q31_mve(S, pSrc, fftLen); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_inverse_q31_mve(S, pSrc, fftLen); + break; + } + } else { + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_q31_mve(S, pSrc, fftLen); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_q31_mve(S, pSrc, fftLen); + break; + } + } + + + if (bitReverseFlag) + { + + arm_bitreversal_32_inpl_mve((uint32_t*)pSrc, S->bitRevLength, S->pBitRevTable); + + } +} +#else + +extern void arm_radix4_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier); + +extern void arm_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier); + +extern void arm_bitreversal_32( + uint32_t * pSrc, + const uint16_t bitRevLen, + const uint16_t * pBitRevTable); + +void arm_cfft_radix4by2_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef); + +void arm_cfft_radix4by2_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef); + + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the Q31 complex FFT. + @param[in] S points to an instance of the fixed-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen; + + if (ifftFlag == 1U) + { + switch (L) + { + case 16: + case 64: + case 256: + case 1024: + case 4096: + arm_radix4_butterfly_inverse_q31 ( p1, L, (q31_t*)S->pTwiddle, 1 ); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_inverse_q31 ( p1, L, S->pTwiddle ); + break; + } + } + else + { + switch (L) + { + case 16: + case 64: + case 256: + case 1024: + case 4096: + arm_radix4_butterfly_q31 ( p1, L, (q31_t*)S->pTwiddle, 1 ); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_q31 ( p1, L, S->pTwiddle ); + break; + } + } + + if ( bitReverseFlag ) + arm_bitreversal_32 ((uint32_t*) p1, S->bitRevLength, S->pBitRevTable); +} + +/** + @} end of ComplexFFT group + */ + +void arm_cfft_radix4by2_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef) +{ + uint32_t i, l; + uint32_t n2; + q31_t xt, yt, cosVal, sinVal; + q31_t p0, p1; + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2 * i]; + sinVal = pCoef[2 * i + 1]; + + l = i + n2; + + xt = (pSrc[2 * i] >> 2U) - (pSrc[2 * l] >> 2U); + pSrc[2 * i] = (pSrc[2 * i] >> 2U) + (pSrc[2 * l] >> 2U); + + yt = (pSrc[2 * i + 1] >> 2U) - (pSrc[2 * l + 1] >> 2U); + pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2U) + (pSrc[2 * i + 1] >> 2U); + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multAcc_32x32_keep32_R(p0, yt, sinVal); + multSub_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2 * l] = p0 << 1; + pSrc[2 * l + 1] = p1 << 1; + } + + + /* first col */ + arm_radix4_butterfly_q31 (pSrc, n2, (q31_t*)pCoef, 2U); + + /* second col */ + arm_radix4_butterfly_q31 (pSrc + fftLen, n2, (q31_t*)pCoef, 2U); + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + p0 = pSrc[4 * i + 0]; + p1 = pSrc[4 * i + 1]; + xt = pSrc[4 * i + 2]; + yt = pSrc[4 * i + 3]; + + p0 <<= 1U; + p1 <<= 1U; + xt <<= 1U; + yt <<= 1U; + + pSrc[4 * i + 0] = p0; + pSrc[4 * i + 1] = p1; + pSrc[4 * i + 2] = xt; + pSrc[4 * i + 3] = yt; + } + +} + +void arm_cfft_radix4by2_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef) +{ + uint32_t i, l; + uint32_t n2; + q31_t xt, yt, cosVal, sinVal; + q31_t p0, p1; + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2 * i]; + sinVal = pCoef[2 * i + 1]; + + l = i + n2; + + xt = (pSrc[2 * i] >> 2U) - (pSrc[2 * l] >> 2U); + pSrc[2 * i] = (pSrc[2 * i] >> 2U) + (pSrc[2 * l] >> 2U); + + yt = (pSrc[2 * i + 1] >> 2U) - (pSrc[2 * l + 1] >> 2U); + pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2U) + (pSrc[2 * i + 1] >> 2U); + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multSub_32x32_keep32_R(p0, yt, sinVal); + multAcc_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2 * l] = p0 << 1U; + pSrc[2 * l + 1] = p1 << 1U; + } + + /* first col */ + arm_radix4_butterfly_inverse_q31( pSrc, n2, (q31_t*)pCoef, 2U); + + /* second col */ + arm_radix4_butterfly_inverse_q31( pSrc + fftLen, n2, (q31_t*)pCoef, 2U); + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + p0 = pSrc[4 * i + 0]; + p1 = pSrc[4 * i + 1]; + xt = pSrc[4 * i + 2]; + yt = pSrc[4 * i + 3]; + + p0 <<= 1U; + p1 <<= 1U; + xt <<= 1U; + yt <<= 1U; + + pSrc[4 * i + 0] = p0; + pSrc[4 * i + 1] = p1; + pSrc[4 * i + 2] = xt; + pSrc[4 * i + 3] = yt; + } +} +#endif /* defined(ARM_MATH_MVEI) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f16.c new file mode 100644 index 00000000..8863fbc9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f16.c @@ -0,0 +1,475 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_f16.c + * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +void arm_radix2_butterfly_f16( + float16_t * pSrc, + uint32_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier); + +void arm_radix2_butterfly_inverse_f16( + float16_t * pSrc, + uint32_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier, + float16_t onebyfftLen); + +extern void arm_bitreversal_f16( + float16_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Radix-2 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f16 and will be removed in the future + @param[in] S points to an instance of the floating-point Radix-2 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void arm_cfft_radix2_f16( +const arm_cfft_radix2_instance_f16 * S, + float16_t * pSrc) +{ + + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-2 */ + arm_radix2_butterfly_inverse_f16(pSrc, S->fftLen, S->pTwiddle, + S->twidCoefModifier, S->onebyfftLen); + } + else + { + /* Complex FFT radix-2 */ + arm_radix2_butterfly_f16(pSrc, S->fftLen, S->pTwiddle, + S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + arm_bitreversal_f16(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + + +/** + @} end of ComplexFFT group + */ + + + +/* ---------------------------------------------------------------------- +** Internal helper function used by the FFTs +** ------------------------------------------------------------------- */ + +/* +* @brief Core function for the floating-point CFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of floating-point data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to the twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @return none. +*/ + +void arm_radix2_butterfly_f16( +float16_t * pSrc, +uint32_t fftLen, +const float16_t * pCoef, +uint16_t twidCoefModifier) +{ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + float16_t xt, yt, cosVal, sinVal; + float16_t p0, p1, p2, p3; + float16_t a0, a1; + +#if defined (ARM_MATH_DSP) + + /* Initializations for the first stage */ + n2 = fftLen >> 1; + ia = 0; + i = 0; + + // loop for groups + for (k = n2; k > 0; k--) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + + /* Twiddle coefficients index modifier */ + ia += twidCoefModifier; + + /* index calculation for the input as, */ + /* pSrc[i + 0], pSrc[i + fftLen/1] */ + l = i + n2; + + /* Butterfly implementation */ + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + + p0 = (_Float16)xt * (_Float16)cosVal; + p1 = (_Float16)yt * (_Float16)sinVal; + p2 = (_Float16)yt * (_Float16)cosVal; + p3 = (_Float16)xt * (_Float16)sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = (_Float16)p0 + (_Float16)p1; + pSrc[2 * l + 1] = (_Float16)p2 - (_Float16)p3; + + i++; + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = n2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + + p0 = (_Float16)xt * (_Float16)cosVal; + p1 = (_Float16)yt * (_Float16)sinVal; + p2 = (_Float16)yt * (_Float16)cosVal; + p3 = (_Float16)xt * (_Float16)sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = (_Float16)p0 + (_Float16)p1; + pSrc[2 * l + 1] = (_Float16)p2 - (_Float16)p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while ( j < n2); // groups loop end + twidCoefModifier <<= 1U; + } // stages loop end + + // loop for butterfly + for (i = 0; i < fftLen; i += 2) + { + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * i + 2]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * i + 2]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * i + 3]; + a1 = (_Float16)pSrc[2 * i + 3] + (_Float16)pSrc[2 * i + 1]; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + pSrc[2 * i + 2] = xt; + pSrc[2 * i + 3] = yt; + } // groups loop end + +#else + + n2 = fftLen; + + // loop for stage + for (k = fftLen; k > 1; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + + p0 = (_Float16)xt * (_Float16)cosVal; + p1 = (_Float16)yt * (_Float16)sinVal; + p2 = (_Float16)yt * (_Float16)cosVal; + p3 = (_Float16)xt * (_Float16)sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = (_Float16)p0 + (_Float16)p1; + pSrc[2 * l + 1] = (_Float16)p2 - (_Float16)p3; + + i += n1; + } while (i < fftLen); + j++; + } while (j < n2); + twidCoefModifier <<= 1U; + } + +#endif // #if defined (ARM_MATH_DSP) + +} + + +void arm_radix2_butterfly_inverse_f16( +float16_t * pSrc, +uint32_t fftLen, +const float16_t * pCoef, +uint16_t twidCoefModifier, +float16_t onebyfftLen) +{ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + float16_t xt, yt, cosVal, sinVal; + float16_t p0, p1, p2, p3; + float16_t a0, a1; + +#if defined (ARM_MATH_DSP) + + n2 = fftLen >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + l = i + n2; + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + + p0 = (_Float16)xt * (_Float16)cosVal; + p1 = (_Float16)yt * (_Float16)sinVal; + p2 = (_Float16)yt * (_Float16)cosVal; + p3 = (_Float16)xt * (_Float16)sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = (_Float16)p0 - (_Float16)p1; + pSrc[2 * l + 1] = (_Float16)p2 + (_Float16)p3; + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + + p0 = (_Float16)xt * (_Float16)cosVal; + p1 = (_Float16)yt * (_Float16)sinVal; + p2 = (_Float16)yt * (_Float16)cosVal; + p3 = (_Float16)xt * (_Float16)sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = (_Float16)p0 - (_Float16)p1; + pSrc[2 * l + 1] = (_Float16)p2 + (_Float16)p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while (j < n2); // groups loop end + + twidCoefModifier <<= 1U; + } // stages loop end + + // loop for butterfly + for (i = 0; i < fftLen; i += 2) + { + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * i + 2]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * i + 2]; + + a1 = (_Float16)pSrc[2 * i + 3] + (_Float16)pSrc[2 * i + 1]; + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * i + 3]; + + p0 = (_Float16)a0 * (_Float16)onebyfftLen; + p2 = (_Float16)xt * (_Float16)onebyfftLen; + p1 = (_Float16)a1 * (_Float16)onebyfftLen; + p3 = (_Float16)yt * (_Float16)onebyfftLen; + + pSrc[2 * i] = p0; + pSrc[2 * i + 1] = p1; + pSrc[2 * i + 2] = p2; + pSrc[2 * i + 3] = p3; + } // butterfly loop end + +#else + + n2 = fftLen; + + // loop for stage + for (k = fftLen; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + + p0 = (_Float16)xt * (_Float16)cosVal; + p1 = (_Float16)yt * (_Float16)sinVal; + p2 = (_Float16)yt * (_Float16)cosVal; + p3 = (_Float16)xt * (_Float16)sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = (_Float16)p0 - (_Float16)p1; + pSrc[2 * l + 1] = (_Float16)p2 + (_Float16)p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while ( j < n2 ); // groups loop end + + twidCoefModifier = twidCoefModifier << 1U; + } // stages loop end + + n1 = n2; + n2 = n2 >> 1; + + // loop for butterfly + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + + p0 = (_Float16)a0 * (_Float16)onebyfftLen; + p2 = (_Float16)xt * (_Float16)onebyfftLen; + p1 = (_Float16)a1 * (_Float16)onebyfftLen; + p3 = (_Float16)yt * (_Float16)onebyfftLen; + + pSrc[2 * i] = p0; + pSrc[2U * l] = p2; + + pSrc[2 * i + 1] = p1; + pSrc[2U * l + 1U] = p3; + } // butterfly loop end + +#endif // #if defined (ARM_MATH_DSP) + +} + + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c new file mode 100644 index 00000000..ab218a50 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c @@ -0,0 +1,470 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_f32.c + * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +void arm_radix2_butterfly_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier); + +void arm_radix2_butterfly_inverse_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + +extern void arm_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Radix-2 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed in the future + @param[in] S points to an instance of the floating-point Radix-2 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void arm_cfft_radix2_f32( +const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc) +{ + + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-2 */ + arm_radix2_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle, + S->twidCoefModifier, S->onebyfftLen); + } + else + { + /* Complex FFT radix-2 */ + arm_radix2_butterfly_f32(pSrc, S->fftLen, S->pTwiddle, + S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + + +/** + @} end of ComplexFFT group + */ + + + +/* ---------------------------------------------------------------------- + ** Internal helper function used by the FFTs + ** ------------------------------------------------------------------- */ + +/** + brief Core function for the floating-point CFFT butterfly process. + param[in,out] pSrc points to in-place buffer of floating-point data type + param[in] fftLen length of the FFT + param[in] pCoef points to twiddle coefficient buffer + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + return none + */ + +void arm_radix2_butterfly_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier) +{ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + float32_t xt, yt, cosVal, sinVal; + float32_t p0, p1, p2, p3; + float32_t a0, a1; + +#if defined (ARM_MATH_DSP) + + /* Initializations for the first stage */ + n2 = fftLen >> 1; + ia = 0; + i = 0; + + // loop for groups + for (k = n2; k > 0; k--) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + + /* Twiddle coefficients index modifier */ + ia += twidCoefModifier; + + /* index calculation for the input as, */ + /* pSrc[i + 0], pSrc[i + fftLen/1] */ + l = i + n2; + + /* Butterfly implementation */ + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + i++; + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = n2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while ( j < n2); // groups loop end + twidCoefModifier <<= 1U; + } // stages loop end + + // loop for butterfly + for (i = 0; i < fftLen; i += 2) + { + a0 = pSrc[2 * i] + pSrc[2 * i + 2]; + xt = pSrc[2 * i] - pSrc[2 * i + 2]; + + yt = pSrc[2 * i + 1] - pSrc[2 * i + 3]; + a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1]; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + pSrc[2 * i + 2] = xt; + pSrc[2 * i + 3] = yt; + } // groups loop end + +#else /* #if defined (ARM_MATH_DSP) */ + + n2 = fftLen; + + // loop for stage + for (k = fftLen; k > 1; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + i += n1; + } while (i < fftLen); + j++; + } while (j < n2); + twidCoefModifier <<= 1U; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + + +void arm_radix2_butterfly_inverse_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen) +{ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + float32_t xt, yt, cosVal, sinVal; + float32_t p0, p1, p2, p3; + float32_t a0, a1; + +#if defined (ARM_MATH_DSP) + + n2 = fftLen >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 - p1; + pSrc[2 * l + 1] = p2 + p3; + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 - p1; + pSrc[2 * l + 1] = p2 + p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while (j < n2); // groups loop end + + twidCoefModifier <<= 1U; + } // stages loop end + + // loop for butterfly + for (i = 0; i < fftLen; i += 2) + { + a0 = pSrc[2 * i] + pSrc[2 * i + 2]; + xt = pSrc[2 * i] - pSrc[2 * i + 2]; + + a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1]; + yt = pSrc[2 * i + 1] - pSrc[2 * i + 3]; + + p0 = a0 * onebyfftLen; + p2 = xt * onebyfftLen; + p1 = a1 * onebyfftLen; + p3 = yt * onebyfftLen; + + pSrc[2 * i] = p0; + pSrc[2 * i + 1] = p1; + pSrc[2 * i + 2] = p2; + pSrc[2 * i + 3] = p3; + } // butterfly loop end + +#else /* #if defined (ARM_MATH_DSP) */ + + n2 = fftLen; + + // loop for stage + for (k = fftLen; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 - p1; + pSrc[2 * l + 1] = p2 + p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while ( j < n2 ); // groups loop end + + twidCoefModifier = twidCoefModifier << 1U; + } // stages loop end + + n1 = n2; + n2 = n2 >> 1; + + // loop for butterfly + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + + p0 = a0 * onebyfftLen; + p2 = xt * onebyfftLen; + p1 = a1 * onebyfftLen; + p3 = yt * onebyfftLen; + + pSrc[2 * i] = p0; + pSrc[2 * l] = p2; + + pSrc[2 * i + 1] = p1; + pSrc[2 * l + 1] = p3; + } // butterfly loop end + +#endif /* #if defined (ARM_MATH_DSP) */ + +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f16.c new file mode 100644 index 00000000..e021a0ea --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f16.c @@ -0,0 +1,214 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_init_f16.c + * Description: Radix-2 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" +#include "arm_common_tables.h" +#include "arm_common_tables_f16.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the floating-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f16 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +#if defined(ARM_FLOAT16_SUPPORTED) + +arm_status arm_cfft_radix2_init_f16( + arm_cfft_radix2_instance_f16 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) + + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (float16_t *) twiddleCoefF16_4096; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.000244140625; + break; + + case 2048U: + /* Initializations of structure parameters for 2048 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 2U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 2U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[1]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.00048828125; + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.0009765625f; + break; + + case 512U: + /* Initializations of structure parameters for 512 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 8U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 8U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[7]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.001953125; + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + S->onebyfftLen = 0.00390625f; + break; + + case 128U: + /* Initializations of structure parameters for 128 point FFT */ + S->twidCoefModifier = 32U; + S->bitRevFactor = 32U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[31]; + S->onebyfftLen = 0.0078125; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + S->onebyfftLen = 0.015625f; + break; + + case 32U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 128U; + S->bitRevFactor = 128U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[127]; + S->onebyfftLen = 0.03125; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + S->onebyfftLen = 0.0625f; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ +/** + @} end of ComplexFFT group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c new file mode 100644 index 00000000..ae9f29a8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c @@ -0,0 +1,209 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_init_f32.c + * Description: Radix-2 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the floating-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (float32_t *) twiddleCoef; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.000244140625; + break; + + case 2048U: + /* Initializations of structure parameters for 2048 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 2U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 2U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[1]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.00048828125; + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.0009765625f; + break; + + case 512U: + /* Initializations of structure parameters for 512 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 8U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 8U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[7]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.001953125; + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + S->onebyfftLen = 0.00390625f; + break; + + case 128U: + /* Initializations of structure parameters for 128 point FFT */ + S->twidCoefModifier = 32U; + S->bitRevFactor = 32U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[31]; + S->onebyfftLen = 0.0078125; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + S->onebyfftLen = 0.015625f; + break; + + case 32U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 128U; + S->bitRevFactor = 128U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[127]; + S->onebyfftLen = 0.03125; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + S->onebyfftLen = 0.0625f; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c new file mode 100644 index 00000000..68c99308 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c @@ -0,0 +1,194 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_init_q15.c + * Description: Radix-2 Decimation in Frequency Q15 FFT & IFFT initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the Q15 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed + @param[in,out] S points to an instance of the Q15 CFFT/CIFFT structure. + @param[in] fftLen length of the FFT. + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (q15_t *) twiddleCoef_4096_q15; + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + + break; + + case 2048U: + /* Initializations of structure parameters for 2048 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 2U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 2U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[1]; + + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + S->twidCoefModifier = 4U; + S->bitRevFactor = 4U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + + break; + + case 512U: + /* Initializations of structure parameters for 512 point FFT */ + S->twidCoefModifier = 8U; + S->bitRevFactor = 8U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[7]; + + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + + break; + + case 128U: + /* Initializations of structure parameters for 128 point FFT */ + S->twidCoefModifier = 32U; + S->bitRevFactor = 32U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[31]; + + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + + break; + + case 32U: + /* Initializations of structure parameters for 32 point FFT */ + S->twidCoefModifier = 128U; + S->bitRevFactor = 128U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[127]; + + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + + break; + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c new file mode 100644 index 00000000..73b8a39f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c @@ -0,0 +1,191 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_init_q31.c + * Description: Radix-2 Decimation in Frequency Fixed-point CFFT & CIFFT Initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the Q31 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed in the future. + @param[in,out] S points to an instance of the Q31 CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (q31_t *) twiddleCoef_4096_q31; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) + { + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + break; + + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 2U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 2U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[1]; + break; + + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + break; + + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 8U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 8U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[7]; + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + break; + + case 128U: + /* Initializations of structure parameters for 128 point FFT */ + S->twidCoefModifier = 32U; + S->bitRevFactor = 32U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[31]; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + break; + + case 32U: + /* Initializations of structure parameters for 32 point FFT */ + S->twidCoefModifier = 128U; + S->bitRevFactor = 128U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[127]; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c new file mode 100644 index 00000000..ca15ea18 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c @@ -0,0 +1,689 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_q15.c + * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +void arm_radix2_butterfly_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint16_t twidCoefModifier); + +void arm_radix2_butterfly_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint16_t twidCoefModifier); + +void arm_bitreversal_q15( + q15_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the fixed-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed in the future. + @param[in] S points to an instance of the fixed-point CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc) +{ + + if (S->ifftFlag == 1U) + { + arm_radix2_butterfly_inverse_q15 (pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + else + { + arm_radix2_butterfly_q15 (pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); +} + +/** + @} end of ComplexFFT group + */ + +void arm_radix2_butterfly_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint16_t twidCoefModifier) +{ +#if defined (ARM_MATH_DSP) + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + q15_t in; + q31_t T, S, R; + q31_t coeff, out1, out2; + + //N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + in = ((int16_t) (T & 0xFFFF)) >> 1; + T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + S = read_q15x2 (pSrc + (2 * l)); + in = ((int16_t) (S & 0xFFFF)) >> 1; + S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(coeff, R) >> 16; + out2 = __SMUSDX(coeff, R); +#else + out1 = __SMUSDX(R, coeff) >> 16U; + out2 = __SMUAD(coeff, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2U * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + i++; + l++; + + T = read_q15x2 (pSrc + (2 * i)); + in = ((int16_t) (T & 0xFFFF)) >> 1; + T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + S = read_q15x2 (pSrc + (2 * l)); + in = ((int16_t) (S & 0xFFFF)) >> 1; + S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(coeff, R) >> 16; + out2 = __SMUSDX(coeff, R); +#else + + out1 = __SMUSDX(R, coeff) >> 16U; + out2 = __SMUAD(coeff, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2U * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + + /* loop for stage */ + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(coeff, R) >> 16; + out2 = __SMUSDX(coeff, R); +#else + out1 = __SMUSDX(R, coeff) >> 16U; + out2 = __SMUAD(coeff, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2U * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + i += n1; + + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(coeff, R) >> 16; + out2 = __SMUSDX(coeff, R); +#else + out1 = __SMUSDX(R, coeff) >> 16U; + out2 = __SMUAD(coeff, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2U * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + } /* stages loop end */ + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __QADD16(T, S)); + + write_q15x2 (pSrc + (2 * l), R); + + i += n1; + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __QADD16(T, S)); + + write_q15x2 (pSrc + (2 * l), R); + + } /* groups loop end */ + + +#else /* #if defined (ARM_MATH_DSP) */ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + q15_t xt, yt, cosVal, sinVal; + + + // N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[(ia * 2)]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = ((pSrc[2 * l + 1] >> 1U) + + (pSrc[2 * i + 1] >> 1U) ) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) + + ((int16_t) (((q31_t) yt * sinVal) >> 16))); + + pSrc[2U * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) - + ((int16_t) (((q31_t) xt * sinVal) >> 16))); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + + /* loop for stage */ + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) + + ((int16_t) (((q31_t) yt * sinVal) >> 16))); + + pSrc[2U * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) - + ((int16_t) (((q31_t) xt * sinVal) >> 16))); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + } /* stages loop end */ + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2 * l] = xt; + + pSrc[2 * l + 1] = yt; + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + + +void arm_radix2_butterfly_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint16_t twidCoefModifier) +{ +#if defined (ARM_MATH_DSP) + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + q15_t in; + q31_t T, S, R; + q31_t coeff, out1, out2; + + // N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (i = 0; i < n2; i++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + in = ((int16_t) (T & 0xFFFF)) >> 1; + T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + S = read_q15x2 (pSrc + (2 * l)); + in = ((int16_t) (S & 0xFFFF)) >> 1; + S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(coeff, R) >> 16; + out2 = __SMUADX(coeff, R); +#else + out1 = __SMUADX(R, coeff) >> 16U; + out2 = __SMUSD(__QSUB(0, coeff), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2 * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + i++; + l++; + + T = read_q15x2 (pSrc + (2 * i)); + in = ((int16_t) (T & 0xFFFF)) >> 1; + T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + S = read_q15x2 (pSrc + (2 * l)); + in = ((int16_t) (S & 0xFFFF)) >> 1; + S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(coeff, R) >> 16; + out2 = __SMUADX(coeff, R); +#else + out1 = __SMUADX(R, coeff) >> 16U; + out2 = __SMUSD(__QSUB(0, coeff), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2 * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + + /* loop for stage */ + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(coeff, R) >> 16; + out2 = __SMUADX(coeff, R); +#else + out1 = __SMUADX(R, coeff) >> 16U; + out2 = __SMUSD(__QSUB(0, coeff), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2 * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + i += n1; + + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(coeff, R) >> 16; + out2 = __SMUADX(coeff, R); +#else + out1 = __SMUADX(R, coeff) >> 16U; + out2 = __SMUSD(__QSUB(0, coeff), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2 * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + } /* stages loop end */ + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __QADD16(T, S)); + + write_q15x2 (pSrc + (2 * l), R); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + +#else /* #if defined (ARM_MATH_DSP) */ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + q15_t xt, yt, cosVal, sinVal; + + // N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[(ia * 2)]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = ((pSrc[2 * l + 1] >> 1U) + + (pSrc[2 * i + 1] >> 1U) ) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) - + ((int16_t) (((q31_t) yt * sinVal) >> 16))); + + pSrc[2 * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) + + ((int16_t) (((q31_t) xt * sinVal) >> 16))); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + + /* loop for stage */ + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[(ia * 2)]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) - + ((int16_t) (((q31_t) yt * sinVal) >> 16)) ); + + pSrc[2 * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) + + ((int16_t) (((q31_t) xt * sinVal) >> 16)) ); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + } /* stages loop end */ + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + cosVal = pCoef[(ia * 2)]; + sinVal = pCoef[(ia * 2) + 1]; + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2 * l] = xt; + + pSrc[2 * l + 1] = yt; + + } /* groups loop end */ + + +#endif /* #if defined (ARM_MATH_DSP) */ + +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c new file mode 100644 index 00000000..996e91d3 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c @@ -0,0 +1,337 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_q31.c + * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +void arm_radix2_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint16_t twidCoefModifier); + +void arm_radix2_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint16_t twidCoefModifier); + +void arm_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the fixed-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed in the future. + @param[in] S points to an instance of the fixed-point CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc) +{ + + if (S->ifftFlag == 1U) + { + arm_radix2_butterfly_inverse_q31(pSrc, S->fftLen, + S->pTwiddle, S->twidCoefModifier); + } + else + { + arm_radix2_butterfly_q31(pSrc, S->fftLen, + S->pTwiddle, S->twidCoefModifier); + } + + arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); +} + +/** + @} end of ComplexFFT group + */ + +void arm_radix2_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint16_t twidCoefModifier) +{ + + unsigned i, j, k, l, m; + unsigned n1, n2, ia; + q31_t xt, yt, cosVal, sinVal; + q31_t p0, p1; + + //N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + l = i + n2; + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = + ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U; + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multAcc_32x32_keep32_R(p0, yt, sinVal); + multSub_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2U * l] = p0; + pSrc[2U * l + 1U] = p1; + + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (j = 0; j < n2; j++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + i = j; + m = fftLen / n1; + do + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U; + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multAcc_32x32_keep32_R(p0, yt, sinVal); + multSub_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2U * l] = p0; + pSrc[2U * l + 1U] = p1; + i += n1; + m--; + } while ( m > 0); // butterfly loop end + + } // groups loop end + + twidCoefModifier <<= 1U; + } // stages loop end + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2U * l] = xt; + + pSrc[2U * l + 1U] = yt; + + i += n1; + l = i + n2; + + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2U * l] = xt; + + pSrc[2U * l + 1U] = yt; + + } // butterfly loop end + +} + + +void arm_radix2_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint16_t twidCoefModifier) +{ + + unsigned i, j, k, l; + unsigned n1, n2, ia; + q31_t xt, yt, cosVal, sinVal; + q31_t p0, p1; + + //N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + l = i + n2; + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = + ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U; + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multSub_32x32_keep32_R(p0, yt, sinVal); + multAcc_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2U * l] = p0; + pSrc[2U * l + 1U] = p1; + } // groups loop end + + twidCoefModifier = twidCoefModifier << 1U; + + // loop for stage + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (j = 0; j < n2; j++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U; + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multSub_32x32_keep32_R(p0, yt, sinVal); + multAcc_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2U * l] = p0; + pSrc[2U * l + 1U] = p1; + } // butterfly loop end + + } // groups loop end + + twidCoefModifier = twidCoefModifier << 1U; + } // stages loop end + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2U * l] = xt; + + pSrc[2U * l + 1U] = yt; + + i += n1; + l = i + n2; + + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2U * l] = xt; + + pSrc[2U * l + 1U] = yt; + + } // butterfly loop end + +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f16.c new file mode 100644 index 00000000..1fc5169a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f16.c @@ -0,0 +1,1272 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_f16.c + * Description: Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +extern void arm_bitreversal_f16( + float16_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +void arm_radix4_butterfly_f16( + float16_t * pSrc, + uint16_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier); + +void arm_radix4_butterfly_inverse_f16( + float16_t * pSrc, + uint16_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier, + float16_t onebyfftLen); + + +void arm_cfft_radix4by2_f16( + float16_t * pSrc, + uint32_t fftLen, + const float16_t * pCoef); + + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/* +* @brief Core function for the floating-point CFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of floating-point data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to the twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @return none. +*/ + +void arm_cfft_radix4by2_f16( + float16_t * pSrc, + uint32_t fftLen, + const float16_t * pCoef) +{ + uint32_t i, l; + uint32_t n2, ia; + float16_t xt, yt, cosVal, sinVal; + float16_t p0, p1,p2,p3,a0,a1; + + n2 = fftLen >> 1; + ia = 0; + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2*ia]; + sinVal = pCoef[2*ia + 1]; + ia++; + + l = i + n2; + + /* Butterfly implementation */ + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + + p0 = (_Float16)xt * (_Float16)cosVal; + p1 = (_Float16)yt * (_Float16)sinVal; + p2 = (_Float16)yt * (_Float16)cosVal; + p3 = (_Float16)xt * (_Float16)sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = (_Float16)p0 + (_Float16)p1; + pSrc[2 * l + 1] = (_Float16)p2 - (_Float16)p3; + + } + + // first col + arm_radix4_butterfly_f16( pSrc, n2, (float16_t*)pCoef, 2U); + // second col + arm_radix4_butterfly_f16( pSrc + fftLen, n2, (float16_t*)pCoef, 2U); + +} + + +/** + @brief Processing function for the floating-point Radix-4 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f16 and will be removed in the future. + @param[in] S points to an instance of the floating-point Radix-4 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void arm_cfft_radix4_f16( + const arm_cfft_radix4_instance_f16 * S, + float16_t * pSrc) +{ + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-4 */ + arm_radix4_butterfly_inverse_f16(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier, S->onebyfftLen); + } + else + { + /* Complex FFT radix-4 */ + arm_radix4_butterfly_f16(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + arm_bitreversal_f16(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + +/** + @} end of ComplexFFT group + */ + +/* ---------------------------------------------------------------------- + * Internal helper function used by the FFTs + * ---------------------------------------------------------------------- */ + +/* +* @brief Core function for the floating-point CFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of floating-point data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to the twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @return none. +*/ + +void arm_radix4_butterfly_f16( +float16_t * pSrc, +uint16_t fftLen, +const float16_t * pCoef, +uint16_t twidCoefModifier) +{ + + float16_t co1, co2, co3, si1, si2, si3; + uint32_t ia1, ia2, ia3; + uint32_t i0, i1, i2, i3; + uint32_t n1, n2, j, k; + +#if defined (ARM_MATH_DSP) + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + + float16_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn; + float16_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc, + Ybminusd; + float16_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out; + float16_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out; + float16_t *ptr1; + float16_t p0,p1,p2,p3,p4,p5; + float16_t a0,a1,a2,a3,a4,a5,a6,a7; + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa + xc */ + Xaplusc = (_Float16)xaIn + (_Float16)xcIn; + /* xb + xd */ + Xbplusd = (_Float16)xbIn + (_Float16)xdIn; + /* ya + yc */ + Yaplusc = (_Float16)yaIn + (_Float16)ycIn; + /* yb + yd */ + Ybplusd = (_Float16)ybIn + (_Float16)ydIn; + + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xa - xc */ + Xaminusc = (_Float16)xaIn - (_Float16)xcIn; + /* xb - xd */ + Xbminusd = (_Float16)xbIn - (_Float16)xdIn; + /* ya - yc */ + Yaminusc = (_Float16)yaIn - (_Float16)ycIn; + /* yb - yd */ + Ybminusd = (_Float16)ybIn - (_Float16)ydIn; + + /* xa' = xa + xb + xc + xd */ + pSrc[(2U * i0)] = (_Float16)Xaplusc + (_Float16)Xbplusd; + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (_Float16)Yaplusc + (_Float16)Ybplusd; + + /* (xa - xc) + (yb - yd) */ + Xb12C_out = ((_Float16)Xaminusc + (_Float16)Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = ((_Float16)Yaminusc - (_Float16)Xbminusd); + /* (xa + xc) - (xb + xd) */ + Xc12C_out = ((_Float16)Xaplusc - (_Float16)Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = ((_Float16)Yaplusc - (_Float16)Ybplusd); + /* (xa - xc) - (yb - yd) */ + Xd12C_out = ((_Float16)Xaminusc - (_Float16)Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yd12C_out = ((_Float16)Xbminusd + (_Float16)Yaminusc); + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* index calculation for the coefficients */ + ia3 = ia2 + ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + Xb12_out = (_Float16)Xb12C_out * (_Float16)co1; + Yb12_out = (_Float16)Yb12C_out * (_Float16)co1; + Xc12_out = (_Float16)Xc12C_out * (_Float16)co2; + Yc12_out = (_Float16)Yc12C_out * (_Float16)co2; + Xd12_out = (_Float16)Xd12C_out * (_Float16)co3; + Yd12_out = (_Float16)Yd12C_out * (_Float16)co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = (_Float16)Yb12C_out * (_Float16)si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = (_Float16)Xb12C_out * (_Float16)si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = (_Float16)Yc12C_out * (_Float16)si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = (_Float16)Xc12C_out * (_Float16)si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = (_Float16)Yd12C_out * (_Float16)si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = (_Float16)Xd12C_out * (_Float16)si3; + + Xb12_out += (_Float16)p0; + Yb12_out -= (_Float16)p1; + Xc12_out += (_Float16)p2; + Yc12_out -= (_Float16)p3; + Xd12_out += (_Float16)p4; + Yd12_out -= (_Float16)p5; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + /* Twiddle coefficients index modifier */ + ia1 += twidCoefModifier; + + /* Updating input index */ + i0++; + + } + while (--j); + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen >> 2U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 += twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa - xc */ + Xaminusc = (_Float16)xaIn - (_Float16)xcIn; + /* (xb - xd) */ + Xbminusd = (_Float16)xbIn - (_Float16)xdIn; + /* ya - yc */ + Yaminusc = (_Float16)yaIn - (_Float16)ycIn; + /* (yb - yd) */ + Ybminusd = (_Float16)ybIn - (_Float16)ydIn; + + /* xa + xc */ + Xaplusc = (_Float16)xaIn + (_Float16)xcIn; + /* xb + xd */ + Xbplusd = (_Float16)xbIn + (_Float16)xdIn; + /* ya + yc */ + Yaplusc = (_Float16)yaIn + (_Float16)ycIn; + /* yb + yd */ + Ybplusd = (_Float16)ybIn + (_Float16)ydIn; + + /* (xa - xc) + (yb - yd) */ + Xb12C_out = ((_Float16)Xaminusc + (_Float16)Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yb12C_out = ((_Float16)Yaminusc - (_Float16)Xbminusd); + /* xa + xc -(xb + xd) */ + Xc12C_out = ((_Float16)Xaplusc - (_Float16)Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = ((_Float16)Yaplusc - (_Float16)Ybplusd); + /* (xa - xc) - (yb - yd) */ + Xd12C_out = ((_Float16)Xaminusc - (_Float16)Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yd12C_out = ((_Float16)Xbminusd + (_Float16)Yaminusc); + + pSrc[(2U * i0)] = (_Float16)Xaplusc + (_Float16)Xbplusd; + pSrc[(2U * i0) + 1U] = (_Float16)Yaplusc + (_Float16)Ybplusd; + + Xb12_out = (_Float16)Xb12C_out * (_Float16)co1; + Yb12_out = (_Float16)Yb12C_out * (_Float16)co1; + Xc12_out = (_Float16)Xc12C_out * (_Float16)co2; + Yc12_out = (_Float16)Yc12C_out * (_Float16)co2; + Xd12_out = (_Float16)Xd12C_out * (_Float16)co3; + Yd12_out = (_Float16)Yd12C_out * (_Float16)co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = (_Float16)Yb12C_out * (_Float16)si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = (_Float16)Xb12C_out * (_Float16)si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = (_Float16)Yc12C_out * (_Float16)si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = (_Float16)Xc12C_out * (_Float16)si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = (_Float16)Yd12C_out * (_Float16)si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = (_Float16)Xd12C_out * (_Float16)si3; + + Xb12_out += (_Float16)p0; + Yb12_out -= (_Float16)p1; + Xc12_out += (_Float16)p2; + Yc12_out -= (_Float16)p3; + Xd12_out += (_Float16)p4; + Yd12_out -= (_Float16)p5; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + i0 += n1; + } while (i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + xaIn = ptr1[0]; + yaIn = ptr1[1]; + xbIn = ptr1[2]; + ybIn = ptr1[3]; + xcIn = ptr1[4]; + ycIn = ptr1[5]; + xdIn = ptr1[6]; + ydIn = ptr1[7]; + + /* xa + xc */ + Xaplusc = (_Float16)xaIn + (_Float16)xcIn; + + /* xa - xc */ + Xaminusc = (_Float16)xaIn - (_Float16)xcIn; + + /* ya + yc */ + Yaplusc = (_Float16)yaIn + (_Float16)ycIn; + + /* ya - yc */ + Yaminusc = (_Float16)yaIn - (_Float16)ycIn; + + /* xb + xd */ + Xbplusd = (_Float16)xbIn + (_Float16)xdIn; + + /* yb + yd */ + Ybplusd = (_Float16)ybIn + (_Float16)ydIn; + + /* (xb-xd) */ + Xbminusd = (_Float16)xbIn - (_Float16)xdIn; + + /* (yb-yd) */ + Ybminusd = (_Float16)ybIn - (_Float16)ydIn; + + /* xa' = xa + xb + xc + xd */ + a0 = ((_Float16)Xaplusc + (_Float16)Xbplusd); + /* ya' = ya + yb + yc + yd */ + a1 = ((_Float16)Yaplusc + (_Float16)Ybplusd); + /* xc' = (xa-xb+xc-xd) */ + a2 = ((_Float16)Xaplusc - (_Float16)Xbplusd); + /* yc' = (ya-yb+yc-yd) */ + a3 = ((_Float16)Yaplusc - (_Float16)Ybplusd); + /* xb' = (xa+yb-xc-yd) */ + a4 = ((_Float16)Xaminusc + (_Float16)Ybminusd); + /* yb' = (ya-xb-yc+xd) */ + a5 = ((_Float16)Yaminusc - (_Float16)Xbminusd); + /* xd' = (xa-yb-xc+yd)) */ + a6 = ((_Float16)Xaminusc - (_Float16)Ybminusd); + /* yd' = (ya+xb-yc-xd) */ + a7 = ((_Float16)Xbminusd + (_Float16)Yaminusc); + + ptr1[0] = a0; + ptr1[1] = a1; + ptr1[2] = a2; + ptr1[3] = a3; + ptr1[4] = a4; + ptr1[5] = a5; + ptr1[6] = a6; + ptr1[7] = a7; + + /* increment pointer by 8 */ + ptr1 += 8U; + } while (--j); + +#else + + float16_t t1, t2, r1, r2, s1, s2; + + /* Run the below code for Cortex-M0 */ + + /* Initializations for the fft calculation */ + n2 = fftLen; + n1 = n2; + for (k = fftLen; k > 1U; k >>= 2U) + { + /* Initializations for the fft calculation */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* FFT Calculation */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* xa + xc */ + r1 = (_Float16)pSrc[(2U * i0)] + (_Float16)pSrc[(2U * i2)]; + + /* xa - xc */ + r2 = (_Float16)pSrc[(2U * i0)] - (_Float16)pSrc[(2U * i2)]; + + /* ya + yc */ + s1 = (_Float16)pSrc[(2U * i0) + 1U] + (_Float16)pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = (_Float16)pSrc[(2U * i0) + 1U] - (_Float16)pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = (_Float16)pSrc[2U * i1] + (_Float16)pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (_Float16)r1 + (_Float16)t1; + + /* xa + xc -(xb + xd) */ + r1 = (_Float16)r1 - (_Float16)t1; + + /* yb + yd */ + t2 = (_Float16)pSrc[(2U * i1) + 1U] + (_Float16)pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (_Float16)s1 + (_Float16)t2; + + /* (ya + yc) - (yb + yd) */ + s1 = (_Float16)s1 - (_Float16)t2; + + /* (yb - yd) */ + t1 = (_Float16)pSrc[(2U * i1) + 1U] - (_Float16)pSrc[(2U * i3) + 1U]; + + /* (xb - xd) */ + t2 = (_Float16)pSrc[2U * i1] - (_Float16)pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = ((_Float16)r1 * (_Float16)co2) + ((_Float16)s1 * (_Float16)si2); + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = ((_Float16)s1 * (_Float16)co2) - ((_Float16)r1 * (_Float16)si2); + + /* (xa - xc) + (yb - yd) */ + r1 = (_Float16)r2 + (_Float16)t1; + + /* (xa - xc) - (yb - yd) */ + r2 = (_Float16)r2 - (_Float16)t1; + + /* (ya - yc) - (xb - xd) */ + s1 = (_Float16)s2 - (_Float16)t2; + + /* (ya - yc) + (xb - xd) */ + s2 = (_Float16)s2 + (_Float16)t2; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = ((_Float16)r1 * (_Float16)co1) + ((_Float16)s1 * (_Float16)si1); + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = ((_Float16)s1 * (_Float16)co1) - ((_Float16)r1 * (_Float16)si1); + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = ((_Float16)r2 * (_Float16)co3) + ((_Float16)s2 * (_Float16)si3); + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = ((_Float16)s2 * (_Float16)co3) - ((_Float16)r2 * (_Float16)si3); + + i0 += n1; + } while ( i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/* +* @brief Core function for the floating-point CIFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of floating-point data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @param[in] onebyfftLen value of 1/fftLen. +* @return none. +*/ + +void arm_radix4_butterfly_inverse_f16( +float16_t * pSrc, +uint16_t fftLen, +const float16_t * pCoef, +uint16_t twidCoefModifier, +float16_t onebyfftLen) +{ + float16_t co1, co2, co3, si1, si2, si3; + uint32_t ia1, ia2, ia3; + uint32_t i0, i1, i2, i3; + uint32_t n1, n2, j, k; + +#if defined (ARM_MATH_DSP) + + float16_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn; + float16_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc, + Ybminusd; + float16_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out; + float16_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out; + float16_t *ptr1; + float16_t p0,p1,p2,p3,p4,p5,p6,p7; + float16_t a0,a1,a2,a3,a4,a5,a6,a7; + + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa + xc */ + Xaplusc = (_Float16)xaIn + (_Float16)xcIn; + /* xb + xd */ + Xbplusd = (_Float16)xbIn + (_Float16)xdIn; + /* ya + yc */ + Yaplusc = (_Float16)yaIn + (_Float16)ycIn; + /* yb + yd */ + Ybplusd = (_Float16)ybIn + (_Float16)ydIn; + + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xa - xc */ + Xaminusc = (_Float16)xaIn - (_Float16)xcIn; + /* xb - xd */ + Xbminusd = (_Float16)xbIn - (_Float16)xdIn; + /* ya - yc */ + Yaminusc = (_Float16)yaIn - (_Float16)ycIn; + /* yb - yd */ + Ybminusd = (_Float16)ybIn - (_Float16)ydIn; + + /* xa' = xa + xb + xc + xd */ + pSrc[(2U * i0)] = (_Float16)Xaplusc + (_Float16)Xbplusd; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (_Float16)Yaplusc + (_Float16)Ybplusd; + + /* (xa - xc) - (yb - yd) */ + Xb12C_out = ((_Float16)Xaminusc - (_Float16)Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = ((_Float16)Yaminusc + (_Float16)Xbminusd); + /* (xa + xc) - (xb + xd) */ + Xc12C_out = ((_Float16)Xaplusc - (_Float16)Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = ((_Float16)Yaplusc - (_Float16)Ybplusd); + /* (xa - xc) + (yb - yd) */ + Xd12C_out = ((_Float16)Xaminusc + (_Float16)Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yd12C_out = ((_Float16)Yaminusc - (_Float16)Xbminusd); + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* index calculation for the coefficients */ + ia3 = ia2 + ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + Xb12_out = (_Float16)Xb12C_out * (_Float16)co1; + Yb12_out = (_Float16)Yb12C_out * (_Float16)co1; + Xc12_out = (_Float16)Xc12C_out * (_Float16)co2; + Yc12_out = (_Float16)Yc12C_out * (_Float16)co2; + Xd12_out = (_Float16)Xd12C_out * (_Float16)co3; + Yd12_out = (_Float16)Yd12C_out * (_Float16)co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = (_Float16)Yb12C_out * (_Float16)si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = (_Float16)Xb12C_out * (_Float16)si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = (_Float16)Yc12C_out * (_Float16)si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = (_Float16)Xc12C_out * (_Float16)si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = (_Float16)Yd12C_out * (_Float16)si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 =(_Float16) Xd12C_out * (_Float16)si3; + + Xb12_out -= (_Float16)p0; + Yb12_out += (_Float16)p1; + Xc12_out -= (_Float16)p2; + Yc12_out += (_Float16)p3; + Xd12_out -= (_Float16)p4; + Yd12_out += (_Float16)p5; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen >> 2U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa - xc */ + Xaminusc = (_Float16)xaIn - (_Float16)xcIn; + /* (xb - xd) */ + Xbminusd = (_Float16)xbIn - (_Float16)xdIn; + /* ya - yc */ + Yaminusc = (_Float16)yaIn - (_Float16)ycIn; + /* (yb - yd) */ + Ybminusd = (_Float16)ybIn - (_Float16)ydIn; + + /* xa + xc */ + Xaplusc = (_Float16)xaIn + (_Float16)xcIn; + /* xb + xd */ + Xbplusd = (_Float16)xbIn + (_Float16)xdIn; + /* ya + yc */ + Yaplusc = (_Float16)yaIn + (_Float16)ycIn; + /* yb + yd */ + Ybplusd = (_Float16)ybIn + (_Float16)ydIn; + + /* (xa - xc) - (yb - yd) */ + Xb12C_out = ((_Float16)Xaminusc - (_Float16)Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = ((_Float16)Yaminusc + (_Float16)Xbminusd); + /* xa + xc -(xb + xd) */ + Xc12C_out = ((_Float16)Xaplusc - (_Float16)Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = ((_Float16)Yaplusc - (_Float16)Ybplusd); + /* (xa - xc) + (yb - yd) */ + Xd12C_out = ((_Float16)Xaminusc + (_Float16)Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yd12C_out = ((_Float16)Yaminusc - (_Float16)Xbminusd); + + pSrc[(2U * i0)] = (_Float16)Xaplusc + (_Float16)Xbplusd; + pSrc[(2U * i0) + 1U] = (_Float16)Yaplusc + (_Float16)Ybplusd; + + Xb12_out = (_Float16)Xb12C_out * (_Float16)co1; + Yb12_out = (_Float16)Yb12C_out * (_Float16)co1; + Xc12_out = (_Float16)Xc12C_out * (_Float16)co2; + Yc12_out = (_Float16)Yc12C_out * (_Float16)co2; + Xd12_out = (_Float16)Xd12C_out * (_Float16)co3; + Yd12_out = (_Float16)Yd12C_out * (_Float16)co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = (_Float16)Yb12C_out * (_Float16)si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = (_Float16)Xb12C_out * (_Float16)si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = (_Float16)Yc12C_out * (_Float16)si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = (_Float16)Xc12C_out * (_Float16)si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = (_Float16)Yd12C_out * (_Float16)si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = (_Float16)Xd12C_out * (_Float16)si3; + + Xb12_out -= (_Float16)p0; + Yb12_out += (_Float16)p1; + Xc12_out -= (_Float16)p2; + Yc12_out += (_Float16)p3; + Xd12_out -= (_Float16)p4; + Yd12_out += (_Float16)p5; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + i0 += n1; + } while (i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + /* Initializations of last stage */ + + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + xaIn = ptr1[0]; + yaIn = ptr1[1]; + xbIn = ptr1[2]; + ybIn = ptr1[3]; + xcIn = ptr1[4]; + ycIn = ptr1[5]; + xdIn = ptr1[6]; + ydIn = ptr1[7]; + + /* Butterfly implementation */ + /* xa + xc */ + Xaplusc = (_Float16)xaIn + (_Float16)xcIn; + + /* xa - xc */ + Xaminusc = (_Float16)xaIn - (_Float16)xcIn; + + /* ya + yc */ + Yaplusc = (_Float16)yaIn + (_Float16)ycIn; + + /* ya - yc */ + Yaminusc = (_Float16)yaIn - (_Float16)ycIn; + + /* xb + xd */ + Xbplusd = (_Float16)xbIn + (_Float16)xdIn; + + /* yb + yd */ + Ybplusd = (_Float16)ybIn + (_Float16)ydIn; + + /* (xb-xd) */ + Xbminusd = (_Float16)xbIn - (_Float16)xdIn; + + /* (yb-yd) */ + Ybminusd = (_Float16)ybIn - (_Float16)ydIn; + + /* xa' = (xa+xb+xc+xd) * onebyfftLen */ + a0 = ((_Float16)Xaplusc + (_Float16)Xbplusd); + /* ya' = (ya+yb+yc+yd) * onebyfftLen */ + a1 = ((_Float16)Yaplusc + (_Float16)Ybplusd); + /* xc' = (xa-xb+xc-xd) * onebyfftLen */ + a2 = ((_Float16)Xaplusc - (_Float16)Xbplusd); + /* yc' = (ya-yb+yc-yd) * onebyfftLen */ + a3 = ((_Float16)Yaplusc - (_Float16)Ybplusd); + /* xb' = (xa-yb-xc+yd) * onebyfftLen */ + a4 = ((_Float16)Xaminusc - (_Float16)Ybminusd); + /* yb' = (ya+xb-yc-xd) * onebyfftLen */ + a5 = ((_Float16)Yaminusc + (_Float16)Xbminusd); + /* xd' = (xa-yb-xc+yd) * onebyfftLen */ + a6 = ((_Float16)Xaminusc + (_Float16)Ybminusd); + /* yd' = (ya-xb-yc+xd) * onebyfftLen */ + a7 = ((_Float16)Yaminusc - (_Float16)Xbminusd); + + p0 = (_Float16)a0 * (_Float16)onebyfftLen; + p1 = (_Float16)a1 * (_Float16)onebyfftLen; + p2 = (_Float16)a2 * (_Float16)onebyfftLen; + p3 = (_Float16)a3 * (_Float16)onebyfftLen; + p4 = (_Float16)a4 * (_Float16)onebyfftLen; + p5 = (_Float16)a5 * (_Float16)onebyfftLen; + p6 = (_Float16)a6 * (_Float16)onebyfftLen; + p7 = (_Float16)a7 * (_Float16)onebyfftLen; + + /* xa' = (xa+xb+xc+xd) * onebyfftLen */ + ptr1[0] = p0; + /* ya' = (ya+yb+yc+yd) * onebyfftLen */ + ptr1[1] = p1; + /* xc' = (xa-xb+xc-xd) * onebyfftLen */ + ptr1[2] = p2; + /* yc' = (ya-yb+yc-yd) * onebyfftLen */ + ptr1[3] = p3; + /* xb' = (xa-yb-xc+yd) * onebyfftLen */ + ptr1[4] = p4; + /* yb' = (ya+xb-yc-xd) * onebyfftLen */ + ptr1[5] = p5; + /* xd' = (xa-yb-xc+yd) * onebyfftLen */ + ptr1[6] = p6; + /* yd' = (ya-xb-yc+xd) * onebyfftLen */ + ptr1[7] = p7; + + /* increment source pointer by 8 for next calculations */ + ptr1 = ptr1 + 8U; + + } while (--j); + +#else + + float16_t t1, t2, r1, r2, s1, s2; + + /* Run the below code for Cortex-M0 */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* Calculation of first stage */ + for (k = fftLen; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* xa + xc */ + r1 = (_Float16)pSrc[(2U * i0)] + (_Float16)pSrc[(2U * i2)]; + + /* xa - xc */ + r2 = (_Float16)pSrc[(2U * i0)] - (_Float16)pSrc[(2U * i2)]; + + /* ya + yc */ + s1 = (_Float16)pSrc[(2U * i0) + 1U] + (_Float16)pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = (_Float16)pSrc[(2U * i0) + 1U] - (_Float16)pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = (_Float16)pSrc[2U * i1] + (_Float16)pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (_Float16)r1 + (_Float16)t1; + + /* xa + xc -(xb + xd) */ + r1 = (_Float16)r1 - (_Float16)t1; + + /* yb + yd */ + t2 = (_Float16)pSrc[(2U * i1) + 1U] + (_Float16)pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (_Float16)s1 + (_Float16)t2; + + /* (ya + yc) - (yb + yd) */ + s1 = (_Float16)s1 - (_Float16)t2; + + /* (yb - yd) */ + t1 = (_Float16)pSrc[(2U * i1) + 1U] - (_Float16)pSrc[(2U * i3) + 1U]; + + /* (xb - xd) */ + t2 = (_Float16)pSrc[2U * i1] - (_Float16)pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = ((_Float16)r1 * (_Float16)co2) - ((_Float16)s1 * (_Float16)si2); + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = ((_Float16)s1 * (_Float16)co2) + ((_Float16)r1 * (_Float16)si2); + + /* (xa - xc) - (yb - yd) */ + r1 = (_Float16)r2 - (_Float16)t1; + + /* (xa - xc) + (yb - yd) */ + r2 = (_Float16)r2 + (_Float16)t1; + + /* (ya - yc) + (xb - xd) */ + s1 = (_Float16)s2 + (_Float16)t2; + + /* (ya - yc) - (xb - xd) */ + s2 = (_Float16)s2 - (_Float16)t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = ((_Float16)r1 * (_Float16)co1) - ((_Float16)s1 * (_Float16)si1); + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = ((_Float16)s1 * (_Float16)co1) + ((_Float16)r1 * (_Float16)si1); + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = ((_Float16)r2 * (_Float16)co3) - ((_Float16)s2 * (_Float16)si3); + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = ((_Float16)s2 * (_Float16)co3) + ((_Float16)r2 * (_Float16)si3); + + i0 += n1; + } while ( i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + /* Initializations of last stage */ + n1 = n2; + n2 >>= 2U; + + /* Calculations of last stage */ + for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = (_Float16)pSrc[2U * i0] + (_Float16)pSrc[2U * i2]; + + /* xa - xc */ + r2 = (_Float16)pSrc[2U * i0] - (_Float16)pSrc[2U * i2]; + + /* ya + yc */ + s1 = (_Float16)pSrc[(2U * i0) + 1U] + (_Float16)pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = (_Float16)pSrc[(2U * i0) + 1U] - (_Float16)pSrc[(2U * i2) + 1U]; + + /* xc + xd */ + t1 = (_Float16)pSrc[2U * i1] + (_Float16)pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = ((_Float16)r1 + (_Float16)t1) * (_Float16)onebyfftLen; + + /* (xa + xb) - (xc + xd) */ + r1 = (_Float16)r1 - (_Float16)t1; + + /* yb + yd */ + t2 = (_Float16)pSrc[(2U * i1) + 1U] + (_Float16)pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = ((_Float16)s1 + (_Float16)t2) * (_Float16)onebyfftLen; + + /* (ya + yc) - (yb + yd) */ + s1 = (_Float16)s1 - (_Float16)t2; + + /* (yb-yd) */ + t1 = (_Float16)pSrc[(2U * i1) + 1U] - (_Float16)pSrc[(2U * i3) + 1U]; + + /* (xb-xd) */ + t2 = (_Float16)pSrc[2U * i1] - (_Float16)pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (_Float16)r1 * (_Float16)onebyfftLen; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (_Float16)s1 * (_Float16)onebyfftLen; + + /* (xa - xc) - (yb-yd) */ + r1 = (_Float16)r2 - (_Float16)t1; + + /* (xa - xc) + (yb-yd) */ + r2 = (_Float16)r2 + (_Float16)t1; + + /* (ya - yc) + (xb-xd) */ + s1 = (_Float16)s2 + (_Float16)t2; + + /* (ya - yc) - (xb-xd) */ + s2 = (_Float16)s2 - (_Float16)t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (_Float16)r1 * (_Float16)onebyfftLen; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (_Float16)s1 * (_Float16)onebyfftLen; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (_Float16)r2 * (_Float16)onebyfftLen; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (_Float16)s2 * (_Float16)onebyfftLen; + } + +#endif /* #if defined (ARM_MATH_DSP) */ +} + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c new file mode 100644 index 00000000..9d9d4d56 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c @@ -0,0 +1,1203 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_f32.c + * Description: Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +extern void arm_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +void arm_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier); + +void arm_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + + + + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + + +/** + @brief Processing function for the floating-point Radix-4 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed in the future. + @param[in] S points to an instance of the floating-point Radix-4 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc) +{ + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-4 */ + arm_radix4_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier, S->onebyfftLen); + } + else + { + /* Complex FFT radix-4 */ + arm_radix4_butterfly_f32(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + +/** + @} end of ComplexFFT group + */ + +/* ---------------------------------------------------------------------- + * Internal helper function used by the FFTs + * ---------------------------------------------------------------------- */ + +/** + brief Core function for the floating-point CFFT butterfly process. + param[in,out] pSrc points to the in-place buffer of floating-point data type + param[in] fftLen length of the FFT + param[in] pCoef points to the twiddle coefficient buffer + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + return none + */ + +void arm_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier) +{ + float32_t co1, co2, co3, si1, si2, si3; + uint32_t ia1, ia2, ia3; + uint32_t i0, i1, i2, i3; + uint32_t n1, n2, j, k; + +#if defined (ARM_MATH_LOOPUNROLL) + + float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn; + float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc, + Ybminusd; + float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out; + float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out; + float32_t *ptr1; + float32_t p0,p1,p2,p3,p4,p5; + float32_t a0,a1,a2,a3,a4,a5,a6,a7; + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* xb - xd */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* yb - yd */ + Ybminusd = ybIn - ydIn; + + /* xa' = xa + xb + xc + xd */ + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + /* (xa - xc) + (yb - yd) */ + Xb12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = (Yaminusc - Xbminusd); + /* (xa + xc) - (xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) - (yb - yd) */ + Xd12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yd12C_out = (Xbminusd + Yaminusc); + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* index calculation for the coefficients */ + ia3 = ia2 + ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out += p0; + Yb12_out -= p1; + Xc12_out += p2; + Yc12_out -= p3; + Xd12_out += p4; + Yd12_out -= p5; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + /* Twiddle coefficients index modifier */ + ia1 += twidCoefModifier; + + /* Updating input index */ + i0++; + + } + while (--j); + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen >> 2U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[(ia1 * 2U)]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[(ia2 * 2U)]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[(ia3 * 2U)]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 += twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* (xb - xd) */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* (yb - yd) */ + Ybminusd = ybIn - ydIn; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xa - xc) + (yb - yd) */ + Xb12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yb12C_out = (Yaminusc - Xbminusd); + /* xa + xc -(xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) - (yb - yd) */ + Xd12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yd12C_out = (Xbminusd + Yaminusc); + + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out += p0; + Yb12_out -= p1; + Xc12_out += p2; + Yc12_out -= p3; + Xd12_out += p4; + Yd12_out -= p5; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + i0 += n1; + } while (i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + xaIn = ptr1[0]; + yaIn = ptr1[1]; + xbIn = ptr1[2]; + ybIn = ptr1[3]; + xcIn = ptr1[4]; + ycIn = ptr1[5]; + xdIn = ptr1[6]; + ydIn = ptr1[7]; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + + /* ya + yc */ + Yaplusc = yaIn + ycIn; + + /* ya - yc */ + Yaminusc = yaIn - ycIn; + + /* xb + xd */ + Xbplusd = xbIn + xdIn; + + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xb-xd) */ + Xbminusd = xbIn - xdIn; + + /* (yb-yd) */ + Ybminusd = ybIn - ydIn; + + /* xa' = xa + xb + xc + xd */ + a0 = (Xaplusc + Xbplusd); + /* ya' = ya + yb + yc + yd */ + a1 = (Yaplusc + Ybplusd); + /* xc' = (xa-xb+xc-xd) */ + a2 = (Xaplusc - Xbplusd); + /* yc' = (ya-yb+yc-yd) */ + a3 = (Yaplusc - Ybplusd); + /* xb' = (xa+yb-xc-yd) */ + a4 = (Xaminusc + Ybminusd); + /* yb' = (ya-xb-yc+xd) */ + a5 = (Yaminusc - Xbminusd); + /* xd' = (xa-yb-xc+yd)) */ + a6 = (Xaminusc - Ybminusd); + /* yd' = (ya+xb-yc-xd) */ + a7 = (Xbminusd + Yaminusc); + + ptr1[0] = a0; + ptr1[1] = a1; + ptr1[2] = a2; + ptr1[3] = a3; + ptr1[4] = a4; + ptr1[5] = a5; + ptr1[6] = a6; + ptr1[7] = a7; + + /* increment pointer by 8 */ + ptr1 += 8U; + } while (--j); + +#else + + float32_t t1, t2, r1, r2, s1, s2; + + /* Initializations for the fft calculation */ + n2 = fftLen; + n1 = n2; + for (k = fftLen; k > 1U; k >>= 2U) + { + /* Initializations for the fft calculation */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* FFT Calculation */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* xa + xc */ + r1 = pSrc[(2U * i0)] + pSrc[(2U * i2)]; + + /* xa - xc */ + r2 = pSrc[(2U * i0)] - pSrc[(2U * i2)]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = r1 + t1; + + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = s1 + t2; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (r1 * co2) + (s1 * si2); + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (s1 * co2) - (r1 * si2); + + /* (xa - xc) + (yb - yd) */ + r1 = r2 + t1; + + /* (xa - xc) - (yb - yd) */ + r2 = r2 - t1; + + /* (ya - yc) - (xb - xd) */ + s1 = s2 - t2; + + /* (ya - yc) + (xb - xd) */ + s2 = s2 + t2; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (r1 * co1) + (s1 * si1); + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (s1 * co1) - (r1 * si1); + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (r2 * co3) + (s2 * si3); + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (s2 * co3) - (r2 * si3); + + i0 += n1; + } while ( i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + +} + +/** + brief Core function for the floating-point CIFFT butterfly process. + param[in,out] pSrc points to the in-place buffer of floating-point data type + param[in] fftLen length of the FFT + param[in] pCoef points to twiddle coefficient buffer + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + param[in] onebyfftLen value of 1/fftLen + return none + */ + +void arm_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen) +{ + float32_t co1, co2, co3, si1, si2, si3; + uint32_t ia1, ia2, ia3; + uint32_t i0, i1, i2, i3; + uint32_t n1, n2, j, k; + +#if defined (ARM_MATH_LOOPUNROLL) + + float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn; + float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc, + Ybminusd; + float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out; + float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out; + float32_t *ptr1; + float32_t p0,p1,p2,p3,p4,p5,p6,p7; + float32_t a0,a1,a2,a3,a4,a5,a6,a7; + + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* xb - xd */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* yb - yd */ + Ybminusd = ybIn - ydIn; + + /* xa' = xa + xb + xc + xd */ + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + /* (xa - xc) - (yb - yd) */ + Xb12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = (Yaminusc + Xbminusd); + /* (xa + xc) - (xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) + (yb - yd) */ + Xd12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yd12C_out = (Yaminusc - Xbminusd); + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* index calculation for the coefficients */ + ia3 = ia2 + ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out -= p0; + Yb12_out += p1; + Xc12_out -= p2; + Yc12_out += p3; + Xd12_out -= p4; + Yd12_out += p5; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen >> 2U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* (xb - xd) */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* (yb - yd) */ + Ybminusd = ybIn - ydIn; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xa - xc) - (yb - yd) */ + Xb12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = (Yaminusc + Xbminusd); + /* xa + xc -(xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) + (yb - yd) */ + Xd12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yd12C_out = (Yaminusc - Xbminusd); + + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out -= p0; + Yb12_out += p1; + Xc12_out -= p2; + Yc12_out += p3; + Xd12_out -= p4; + Yd12_out += p5; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + i0 += n1; + } while (i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + /* Initializations of last stage */ + + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + xaIn = ptr1[0]; + yaIn = ptr1[1]; + xbIn = ptr1[2]; + ybIn = ptr1[3]; + xcIn = ptr1[4]; + ycIn = ptr1[5]; + xdIn = ptr1[6]; + ydIn = ptr1[7]; + + /* Butterfly implementation */ + /* xa + xc */ + Xaplusc = xaIn + xcIn; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + + /* ya + yc */ + Yaplusc = yaIn + ycIn; + + /* ya - yc */ + Yaminusc = yaIn - ycIn; + + /* xb + xd */ + Xbplusd = xbIn + xdIn; + + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xb-xd) */ + Xbminusd = xbIn - xdIn; + + /* (yb-yd) */ + Ybminusd = ybIn - ydIn; + + /* xa' = (xa+xb+xc+xd) * onebyfftLen */ + a0 = (Xaplusc + Xbplusd); + /* ya' = (ya+yb+yc+yd) * onebyfftLen */ + a1 = (Yaplusc + Ybplusd); + /* xc' = (xa-xb+xc-xd) * onebyfftLen */ + a2 = (Xaplusc - Xbplusd); + /* yc' = (ya-yb+yc-yd) * onebyfftLen */ + a3 = (Yaplusc - Ybplusd); + /* xb' = (xa-yb-xc+yd) * onebyfftLen */ + a4 = (Xaminusc - Ybminusd); + /* yb' = (ya+xb-yc-xd) * onebyfftLen */ + a5 = (Yaminusc + Xbminusd); + /* xd' = (xa-yb-xc+yd) * onebyfftLen */ + a6 = (Xaminusc + Ybminusd); + /* yd' = (ya-xb-yc+xd) * onebyfftLen */ + a7 = (Yaminusc - Xbminusd); + + p0 = a0 * onebyfftLen; + p1 = a1 * onebyfftLen; + p2 = a2 * onebyfftLen; + p3 = a3 * onebyfftLen; + p4 = a4 * onebyfftLen; + p5 = a5 * onebyfftLen; + p6 = a6 * onebyfftLen; + p7 = a7 * onebyfftLen; + + /* xa' = (xa+xb+xc+xd) * onebyfftLen */ + ptr1[0] = p0; + /* ya' = (ya+yb+yc+yd) * onebyfftLen */ + ptr1[1] = p1; + /* xc' = (xa-xb+xc-xd) * onebyfftLen */ + ptr1[2] = p2; + /* yc' = (ya-yb+yc-yd) * onebyfftLen */ + ptr1[3] = p3; + /* xb' = (xa-yb-xc+yd) * onebyfftLen */ + ptr1[4] = p4; + /* yb' = (ya+xb-yc-xd) * onebyfftLen */ + ptr1[5] = p5; + /* xd' = (xa-yb-xc+yd) * onebyfftLen */ + ptr1[6] = p6; + /* yd' = (ya-xb-yc+xd) * onebyfftLen */ + ptr1[7] = p7; + + /* increment source pointer by 8 for next calculations */ + ptr1 = ptr1 + 8U; + + } while (--j); + +#else + + float32_t t1, t2, r1, r2, s1, s2; + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* Calculation of first stage */ + for (k = fftLen; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* xa + xc */ + r1 = pSrc[(2U * i0)] + pSrc[(2U * i2)]; + + /* xa - xc */ + r2 = pSrc[(2U * i0)] - pSrc[(2U * i2)]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = r1 + t1; + + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = s1 + t2; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (r1 * co2) - (s1 * si2); + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (s1 * co2) + (r1 * si2); + + /* (xa - xc) - (yb - yd) */ + r1 = r2 - t1; + + /* (xa - xc) + (yb - yd) */ + r2 = r2 + t1; + + /* (ya - yc) + (xb - xd) */ + s1 = s2 + t2; + + /* (ya - yc) - (xb - xd) */ + s2 = s2 - t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (r1 * co1) - (s1 * si1); + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (s1 * co1) + (r1 * si1); + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (r2 * co3) - (s2 * si3); + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (s2 * co3) + (r2 * si3); + + i0 += n1; + } while ( i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + /* Initializations of last stage */ + n1 = n2; + n2 >>= 2U; + + /* Calculations of last stage */ + for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = pSrc[2U * i0] + pSrc[2U * i2]; + + /* xa - xc */ + r2 = pSrc[2U * i0] - pSrc[2U * i2]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xc + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1) * onebyfftLen; + + /* (xa + xb) - (xc + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2) * onebyfftLen; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb-yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + + /* (xb-xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = r1 * onebyfftLen; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = s1 * onebyfftLen; + + /* (xa - xc) - (yb-yd) */ + r1 = r2 - t1; + + /* (xa - xc) + (yb-yd) */ + r2 = r2 + t1; + + /* (ya - yc) + (xb-xd) */ + s1 = s2 + t2; + + /* (ya - yc) - (xb-xd) */ + s2 = s2 - t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = r1 * onebyfftLen; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = s1 * onebyfftLen; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = r2 * onebyfftLen; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = s2 * onebyfftLen; + } + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +} + + diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f16.c new file mode 100644 index 00000000..cb45cd80 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f16.c @@ -0,0 +1,171 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_init_f16.c + * Description: Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" +#include "arm_common_tables.h" +#include "arm_common_tables_f16.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the floating-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superceded by \ref arm_cfft_f16 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +#if defined(ARM_FLOAT16_SUPPORTED) + +arm_status arm_cfft_radix4_init_f16( + arm_cfft_radix4_instance_f16 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (float16_t *) twiddleCoefF16; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.000244140625; + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.0009765625f; + break; + + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + S->onebyfftLen = 0.00390625f; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + S->onebyfftLen = 0.015625f; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + S->onebyfftLen = 0.0625f; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ +/** + @} end of ComplexFFT group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c new file mode 100644 index 00000000..b3aabbb2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c @@ -0,0 +1,168 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_init_f32.c + * Description: Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the floating-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superceded by \ref arm_cfft_f32 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (float32_t *) twiddleCoef; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.000244140625; + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.0009765625f; + break; + + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + S->onebyfftLen = 0.00390625f; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + S->onebyfftLen = 0.015625f; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + S->onebyfftLen = 0.0625f; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } +#endif +#endif +#endif + + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c new file mode 100644 index 00000000..77742439 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c @@ -0,0 +1,157 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_init_q15.c + * Description: Radix-4 Decimation in Frequency Q15 FFT & IFFT initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + + +/** + @addtogroup ComplexFFT + @{ + */ + + +/** + @brief Initialization function for the Q15 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed in the future. + @param[in,out] S points to an instance of the Q15 CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + /* Initialise the FFT length */ + S->fftLen = fftLen; + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (q15_t *) twiddleCoef_4096_q15; + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + S->twidCoefModifier = 4U; + S->bitRevFactor = 4U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + + break; + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c new file mode 100644 index 00000000..04ba393a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c @@ -0,0 +1,154 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_init_q31.c + * Description: Radix-4 Decimation in Frequency Q31 FFT & IFFT initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + + @brief Initialization function for the Q31 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed in the future. + @param[in,out] S points to an instance of the Q31 CFFT/CIFFT structure. + @param[in] fftLen length of the FFT. + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + /* Initialise the FFT length */ + S->fftLen = fftLen; + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (q31_t *) twiddleCoef_4096_q31; + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) + { + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + break; + + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + break; + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c new file mode 100644 index 00000000..280acca1 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c @@ -0,0 +1,1809 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_q15.c + * Description: This file has function definition of Radix-4 FFT & IFFT function and + * In-place bit reversal using bit reversal table + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + + +void arm_radix4_butterfly_q15( + q15_t * pSrc16, + uint32_t fftLen, + const q15_t * pCoef16, + uint32_t twidCoefModifier); + +void arm_radix4_butterfly_inverse_q15( + q15_t * pSrc16, + uint32_t fftLen, + const q15_t * pCoef16, + uint32_t twidCoefModifier); + +void arm_bitreversal_q15( + q15_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + + +/** + @brief Processing function for the Q15 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed in the future. + @param[in] S points to an instance of the Q15 CFFT/CIFFT structure. + @param[in,out] pSrc points to the complex data buffer. Processing occurs in-place. + @return none + + @par Input and output formats: + Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. + Hence the output format is different for different FFT sizes. + The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT: + @par + \image html CFFTQ15.gif "Input and Output Formats for Q15 CFFT" + \image html CIFFTQ15.gif "Input and Output Formats for Q15 CIFFT" + */ + +void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc) +{ + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-4 */ + arm_radix4_butterfly_inverse_q15(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + else + { + /* Complex FFT radix-4 */ + arm_radix4_butterfly_q15(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + +/** + @} end of ComplexFFT group + */ + +/* + * Radix-4 FFT algorithm used is : + * + * Input real and imaginary data: + * x(n) = xa + j * ya + * x(n+N/4 ) = xb + j * yb + * x(n+N/2 ) = xc + j * yc + * x(n+3N 4) = xd + j * yd + * + * + * Output real and imaginary data: + * x(4r) = xa'+ j * ya' + * x(4r+1) = xb'+ j * yb' + * x(4r+2) = xc'+ j * yc' + * x(4r+3) = xd'+ j * yd' + * + * + * Twiddle factors for radix-4 FFT: + * Wn = co1 + j * (- si1) + * W2n = co2 + j * (- si2) + * W3n = co3 + j * (- si3) + + * The real and imaginary output values for the radix-4 butterfly are + * xa' = xa + xb + xc + xd + * ya' = ya + yb + yc + yd + * xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) + * yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) + * xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) + * yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) + * xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) + * yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) + * + */ + +/** + @brief Core function for the Q15 CFFT butterfly process. + @param[in,out] pSrc16 points to the in-place buffer of Q15 data type + @param[in] fftLen length of the FFT + @param[in] pCoef16 points to twiddle coefficient buffer + @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +void arm_radix4_butterfly_q15( + q15_t * pSrc16, + uint32_t fftLen, + const q15_t * pCoef16, + uint32_t twidCoefModifier) +{ + +#if defined (ARM_MATH_DSP) + + q31_t R, S, T, U; + q31_t C1, C2, C3, out1, out2; + uint32_t n1, n2, ic, i0, j, k; + + q15_t *ptr1; + q15_t *pSi0; + q15_t *pSi1; + q15_t *pSi2; + q15_t *pSi3; + + q31_t xaya, xbyb, xcyc, xdyd; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + + /* Index for twiddle coefficient */ + ic = 0U; + + /* Index for input read and output write */ + j = n2; + + pSi0 = pSrc16; + pSi1 = pSi0 + 2 * n2; + pSi2 = pSi1 + 2 * n2; + pSi3 = pSi2 + 2 * n2; + + /* Input is in 1.15(q15) format */ + + /* start of first stage process */ + do + { + /* Butterfly implementation */ + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T = read_q15x2 (pSi0); + T = __SHADD16(T, 0); /* this is just a SIMD arithmetic shift right by 1 */ + T = __SHADD16(T, 0); /* it turns out doing this twice is 2 cycles, the alternative takes 3 cycles */ +/* + in = ((int16_t) (T & 0xFFFF)) >> 2; // alternative code that takes 3 cycles + T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF); +*/ + + /* Read yc (real), xc(imag) input */ + S = read_q15x2 (pSi2); + S = __SHADD16(S, 0); + S = __SHADD16(S, 0); + + /* R = packed((ya + yc), (xa + xc) ) */ + R = __QADD16(T, S); + + /* S = packed((ya - yc), (xa - xc) ) */ + S = __QSUB16(T, S); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + T = __SHADD16(T, 0); + T = __SHADD16(T, 0); + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + U = __SHADD16(U, 0); + U = __SHADD16(U, 0); + + /* T = packed((yb + yd), (xb + xd) ) */ + T = __QADD16(T, U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + write_q15x2_ia (&pSi0, __SHADD16(R, T)); + + /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */ + R = __QSUB16(R, T); + + /* co2 & si2 are read from SIMD Coefficient pointer */ + C2 = read_q15x2 ((q15_t *) pCoef16 + (4U * ic)); + +#ifndef ARM_MATH_BIG_ENDIAN + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out1 = __SMUAD(C2, R) >> 16U; + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = __SMUSDX(C2, R); +#else + /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out1 = __SMUSDX(R, C2) >> 16U; + /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out2 = __SMUAD(C2, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Reading i0+fftLen/4 */ + /* T = packed(yb, xb) */ + T = read_q15x2 (pSi1); + T = __SHADD16(T, 0); + T = __SHADD16(T, 0); + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* writing output(xc', yc') in little endian format */ + write_q15x2_ia (&pSi1, (q31_t) __PKHBT( out1, out2, 0 )); + + /* Butterfly calculations */ + /* U = packed(yd, xd) */ + U = read_q15x2 (pSi3); + U = __SHADD16(U, 0); + U = __SHADD16(U, 0); + + /* T = packed(yb-yd, xb-xd) */ + T = __QSUB16(T, U); + +#ifndef ARM_MATH_BIG_ENDIAN + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __QASX(S, T); + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __QSAX(S, T); +#else + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __QSAX(S, T); + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __QASX(S, T); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* co1 & si1 are read from SIMD Coefficient pointer */ + C1 = read_q15x2 ((q15_t *) pCoef16 + (2U * ic)); + /* Butterfly process for the i0+fftLen/2 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out1 = __SMUAD(C1, S) >> 16U; + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out2 = __SMUSDX(C1, S); +#else + /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out1 = __SMUSDX(S, C1) >> 16U; + /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out2 = __SMUAD(C1, S); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* writing output(xb', yb') in little endian format */ + write_q15x2_ia (&pSi2, __PKHBT( out1, out2, 0 )); + + /* co3 & si3 are read from SIMD Coefficient pointer */ + C3 = read_q15x2 ((q15_t *) pCoef16 + (6U * ic)); + /* Butterfly process for the i0+3fftLen/4 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + out1 = __SMUAD(C3, R) >> 16U; + /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + out2 = __SMUSDX(C3, R); +#else + /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + out1 = __SMUSDX(R, C3) >> 16U; + /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + out2 = __SMUAD(C3, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* writing output(xd', yd') in little endian format */ + write_q15x2_ia (&pSi3, __PKHBT( out1, out2, 0 )); + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + } while (--j); + /* data is in 4.11(q11) format */ + + /* end of first stage process */ + + + /* start of middle stage process */ + + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + + /* Calculation of Middle stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the middle stage */ + n1 = n2; + n2 >>= 2U; + ic = 0U; + + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + C1 = read_q15x2 ((q15_t *) pCoef16 + (2U * ic)); + C2 = read_q15x2 ((q15_t *) pCoef16 + (4U * ic)); + C3 = read_q15x2 ((q15_t *) pCoef16 + (6U * ic)); + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + pSi0 = pSrc16 + 2 * j; + pSi1 = pSi0 + 2 * n2; + pSi2 = pSi1 + 2 * n2; + pSi3 = pSi2 + 2 * n2; + + /* Butterfly implementation */ + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T = read_q15x2 (pSi0); + + /* Read yc (real), xc(imag) input */ + S = read_q15x2 (pSi2); + + /* R = packed( (ya + yc), (xa + xc)) */ + R = __QADD16(T, S); + + /* S = packed((ya - yc), (xa - xc)) */ + S = __QSUB16(T, S); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + + /* T = packed( (yb + yd), (xb + xd)) */ + T = __QADD16(T, U); + + /* writing the butterfly processed i0 sample */ + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + out1 = __SHADD16(R, T); + out1 = __SHADD16(out1, 0); + write_q15x2 (pSi0, out1); + pSi0 += 2 * n1; + + /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */ + R = __SHSUB16(R, T); + +#ifndef ARM_MATH_BIG_ENDIAN + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out1 = __SMUAD(C2, R) >> 16U; + + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = __SMUSDX(C2, R); +#else + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out1 = __SMUSDX(R, C2) >> 16U; + + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out2 = __SMUAD(C2, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Reading i0+3fftLen/4 */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + write_q15x2 (pSi1, __PKHBT( out1, out2, 0 )); + pSi1 += 2 * n1; + + /* Butterfly calculations */ + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + + /* T = packed(yb-yd, xb-xd) */ + T = __QSUB16(T, U); + +#ifndef ARM_MATH_BIG_ENDIAN + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __SHASX(S, T); + + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __SHSAX(S, T); + + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = __SMUAD(C1, S) >> 16U; + out2 = __SMUSDX(C1, S); +#else + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __SHSAX(S, T); + + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __SHASX(S, T); + + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = __SMUSDX(S, C1) >> 16U; + out2 = __SMUAD(C1, S); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + write_q15x2 (pSi2, __PKHBT( out1, out2, 0 )); + pSi2 += 2 * n1; + + /* Butterfly process for the i0+3fftLen/4 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(C3, R) >> 16U; + out2 = __SMUSDX(C3, R); +#else + out1 = __SMUSDX(R, C3) >> 16U; + out2 = __SMUAD(C3, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + write_q15x2 (pSi3, __PKHBT( out1, out2, 0 )); + pSi3 += 2 * n1; + } + } + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + } + /* end of middle stage process */ + + + /* data is in 10.6(q6) format for the 1024 point */ + /* data is in 8.8(q8) format for the 256 point */ + /* data is in 6.10(q10) format for the 64 point */ + /* data is in 4.12(q12) format for the 16 point */ + + /* Initializations for the last stage */ + j = fftLen >> 2; + + ptr1 = &pSrc16[0]; + + /* start of last stage process */ + + /* Butterfly implementation */ + do + { + /* Read xa (real), ya(imag) input */ + xaya = read_q15x2_ia (&ptr1); + + /* Read xb (real), yb(imag) input */ + xbyb = read_q15x2_ia (&ptr1); + + /* Read xc (real), yc(imag) input */ + xcyc = read_q15x2_ia (&ptr1); + + /* Read xd (real), yd(imag) input */ + xdyd = read_q15x2_ia (&ptr1); + + /* R = packed((ya + yc), (xa + xc)) */ + R = __QADD16(xaya, xcyc); + + /* T = packed((yb + yd), (xb + xd)) */ + T = __QADD16(xbyb, xdyd); + + /* pointer updation for writing */ + ptr1 = ptr1 - 8U; + + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + write_q15x2_ia (&ptr1, __SHADD16(R, T)); + + /* T = packed((yb + yd), (xb + xd)) */ + T = __QADD16(xbyb, xdyd); + + /* xc' = (xa-xb+xc-xd) */ + /* yc' = (ya-yb+yc-yd) */ + write_q15x2_ia (&ptr1, __SHSUB16(R, T)); + + /* S = packed((ya - yc), (xa - xc)) */ + S = __QSUB16(xaya, xcyc); + + /* Read yd (real), xd(imag) input */ + /* T = packed( (yb - yd), (xb - xd)) */ + U = __QSUB16(xbyb, xdyd); + +#ifndef ARM_MATH_BIG_ENDIAN + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + write_q15x2_ia (&ptr1, __SHSAX(S, U)); + + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + write_q15x2_ia (&ptr1, __SHASX(S, U)); +#else + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + write_q15x2_ia (&ptr1, __SHASX(S, U)); + + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + write_q15x2_ia (&ptr1, __SHSAX(S, U)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + } while (--j); + + /* end of last stage process */ + + /* output is in 11.5(q5) format for the 1024 point */ + /* output is in 9.7(q7) format for the 256 point */ + /* output is in 7.9(q9) format for the 64 point */ + /* output is in 5.11(q11) format for the 16 point */ + + +#else /* #if defined (ARM_MATH_DSP) */ + + q15_t R0, R1, S0, S1, T0, T1, U0, U1; + q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2; + uint32_t n1, n2, ic, i0, i1, i2, i3, j, k; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + + /* Index for twiddle coefficient */ + ic = 0U; + + /* Index for input read and output write */ + i0 = 0U; + j = n2; + + /* Input is in 1.15(q15) format */ + + /* start of first stage process */ + do + { + /* Butterfly implementation */ + + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + + /* input is down scale by 4 to avoid overflow */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U] >> 2U; + T1 = pSrc16[(i0 * 2U) + 1U] >> 2U; + + /* input is down scale by 4 to avoid overflow */ + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U] >> 2U; + S1 = pSrc16[(i2 * 2U) + 1U] >> 2U; + + /* R0 = (ya + yc) */ + R0 = __SSAT(T0 + S0, 16U); + /* R1 = (xa + xc) */ + R1 = __SSAT(T1 + S1, 16U); + + /* S0 = (ya - yc) */ + S0 = __SSAT(T0 - S0, 16); + /* S1 = (xa - xc) */ + S1 = __SSAT(T1 - S1, 16); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* input is down scale by 4 to avoid overflow */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U] >> 2U; + T1 = pSrc16[(i1 * 2U) + 1U] >> 2U; + + /* input is down scale by 4 to avoid overflow */ + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U] >> 2U; + U1 = pSrc16[(i3 * 2U) + 1] >> 2U; + + /* T0 = (yb + yd) */ + T0 = __SSAT(T0 + U0, 16U); + /* T1 = (xb + xd) */ + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* ya' = ya + yb + yc + yd */ + /* xa' = xa + xb + xc + xd */ + pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U); + pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U); + + /* R0 = (ya + yc) - (yb + yd) */ + /* R1 = (xa + xc) - (xb + xd) */ + R0 = __SSAT(R0 - T0, 16U); + R1 = __SSAT(R1 - T1, 16U); + + /* co2 & si2 are read from Coefficient pointer */ + Co2 = pCoef16[2U * ic * 2U]; + Si2 = pCoef16[(2U * ic * 2U) + 1]; + + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out1 = (q15_t) ((Co2 * R0 + Si2 * R1) >> 16U); + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = (q15_t) ((-Si2 * R0 + Co2 * R1) >> 16U); + + /* Reading i0+fftLen/4 */ + /* input is down scale by 4 to avoid overflow */ + /* T0 = yb, T1 = xb */ + T0 = pSrc16[i1 * 2U] >> 2; + T1 = pSrc16[(i1 * 2U) + 1] >> 2; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* writing output(xc', yc') in little endian format */ + pSrc16[i1 * 2U] = out1; + pSrc16[(i1 * 2U) + 1] = out2; + + /* Butterfly calculations */ + /* input is down scale by 4 to avoid overflow */ + /* U0 = yd, U1 = xd */ + U0 = pSrc16[i3 * 2U] >> 2; + U1 = pSrc16[(i3 * 2U) + 1] >> 2; + /* T0 = yb-yd */ + T0 = __SSAT(T0 - U0, 16); + /* T1 = xb-xd */ + T1 = __SSAT(T1 - U1, 16); + + /* R1 = (ya-yc) + (xb- xd), R0 = (xa-xc) - (yb-yd)) */ + R0 = (q15_t) __SSAT((q31_t) (S0 - T1), 16); + R1 = (q15_t) __SSAT((q31_t) (S1 + T0), 16); + + /* S1 = (ya-yc) - (xb- xd), S0 = (xa-xc) + (yb-yd)) */ + S0 = (q15_t) __SSAT(((q31_t) S0 + T1), 16U); + S1 = (q15_t) __SSAT(((q31_t) S1 - T0), 16U); + + /* co1 & si1 are read from Coefficient pointer */ + Co1 = pCoef16[ic * 2U]; + Si1 = pCoef16[(ic * 2U) + 1]; + /* Butterfly process for the i0+fftLen/2 sample */ + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out1 = (q15_t) ((Si1 * S1 + Co1 * S0) >> 16); + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out2 = (q15_t) ((-Si1 * S0 + Co1 * S1) >> 16); + + /* writing output(xb', yb') in little endian format */ + pSrc16[i2 * 2U] = out1; + pSrc16[(i2 * 2U) + 1] = out2; + + /* Co3 & si3 are read from Coefficient pointer */ + Co3 = pCoef16[3U * (ic * 2U)]; + Si3 = pCoef16[(3U * (ic * 2U)) + 1]; + /* Butterfly process for the i0+3fftLen/4 sample */ + /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */ + out1 = (q15_t) ((Si3 * R1 + Co3 * R0) >> 16U); + /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */ + out2 = (q15_t) ((-Si3 * R0 + Co3 * R1) >> 16U); + /* writing output(xd', yd') in little endian format */ + pSrc16[i3 * 2U] = out1; + pSrc16[(i3 * 2U) + 1] = out2; + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + /* data is in 4.11(q11) format */ + + /* end of first stage process */ + + + /* start of middle stage process */ + + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + + /* Calculation of Middle stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the middle stage */ + n1 = n2; + n2 >>= 2U; + ic = 0U; + + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + Co1 = pCoef16[ic * 2U]; + Si1 = pCoef16[(ic * 2U) + 1U]; + Co2 = pCoef16[2U * (ic * 2U)]; + Si2 = pCoef16[(2U * (ic * 2U)) + 1U]; + Co3 = pCoef16[3U * (ic * 2U)]; + Si3 = pCoef16[(3U * (ic * 2U)) + 1U]; + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + /* Butterfly implementation */ + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U]; + T1 = pSrc16[(i0 * 2U) + 1U]; + + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U]; + S1 = pSrc16[(i2 * 2U) + 1U]; + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16); + R1 = __SSAT(T1 + S1, 16); + + /* S0 = (ya - yc), S1 =(xa - xc) */ + S0 = __SSAT(T0 - S0, 16); + S1 = __SSAT(T1 - S1, 16); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + + /* T0 = (yb + yd), T1 = (xb + xd) */ + T0 = __SSAT(T0 + U0, 16); + T1 = __SSAT(T1 + U1, 16); + + /* writing the butterfly processed i0 sample */ + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + out1 = ((R0 >> 1U) + (T0 >> 1U)) >> 1U; + out2 = ((R1 >> 1U) + (T1 >> 1U)) >> 1U; + + pSrc16[i0 * 2U] = out1; + pSrc16[(2U * i0) + 1U] = out2; + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */ + R0 = (R0 >> 1U) - (T0 >> 1U); + R1 = (R1 >> 1U) - (T1 >> 1U); + + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out1 = (q15_t) ((Co2 * R0 + Si2 * R1) >> 16U); + + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = (q15_t) ((-Si2 * R0 + Co2 * R1) >> 16U); + + /* Reading i0+3fftLen/4 */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + pSrc16[i1 * 2U] = out1; + pSrc16[(i1 * 2U) + 1U] = out2; + + /* Butterfly calculations */ + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = yb-yd, T1 = xb-xd */ + T0 = __SSAT(T0 - U0, 16); + T1 = __SSAT(T1 - U1, 16); + + /* R0 = (ya-yc) + (xb- xd), R1 = (xa-xc) - (yb-yd)) */ + R0 = (S0 >> 1U) - (T1 >> 1U); + R1 = (S1 >> 1U) + (T0 >> 1U); + + /* S0 = (ya-yc) - (xb- xd), S1 = (xa-xc) + (yb-yd)) */ + S0 = (S0 >> 1U) + (T1 >> 1U); + S1 = (S1 >> 1U) - (T0 >> 1U); + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = (q15_t) ((Co1 * S0 + Si1 * S1) >> 16U); + + out2 = (q15_t) ((-Si1 * S0 + Co1 * S1) >> 16U); + + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + pSrc16[i2 * 2U] = out1; + pSrc16[(i2 * 2U) + 1U] = out2; + + /* Butterfly process for the i0+3fftLen/4 sample */ + out1 = (q15_t) ((Si3 * R1 + Co3 * R0) >> 16U); + + out2 = (q15_t) ((-Si3 * R0 + Co3 * R1) >> 16U); + /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */ + /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */ + pSrc16[i3 * 2U] = out1; + pSrc16[(i3 * 2U) + 1U] = out2; + } + } + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + } + /* end of middle stage process */ + + + /* data is in 10.6(q6) format for the 1024 point */ + /* data is in 8.8(q8) format for the 256 point */ + /* data is in 6.10(q10) format for the 64 point */ + /* data is in 4.12(q12) format for the 16 point */ + + /* Initializations for the last stage */ + n1 = n2; + n2 >>= 2U; + + /* start of last stage process */ + + /* Butterfly implementation */ + for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U]; + T1 = pSrc16[(i0 * 2U) + 1U]; + + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U]; + S1 = pSrc16[(i2 * 2U) + 1U]; + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16U); + R1 = __SSAT(T1 + S1, 16U); + + /* S0 = (ya - yc), S1 = (xa - xc) */ + S0 = __SSAT(T0 - S0, 16U); + S1 = __SSAT(T1 - S1, 16U); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = (yb + yd), T1 = (xb + xd)) */ + T0 = __SSAT(T0 + U0, 16U); + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U); + pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U); + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */ + R0 = (R0 >> 1U) - (T0 >> 1U); + R1 = (R1 >> 1U) - (T1 >> 1U); + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd) */ + /* yc' = (ya-yb+yc-yd) */ + pSrc16[i1 * 2U] = R0; + pSrc16[(i1 * 2U) + 1U] = R1; + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + /* T0 = (yb - yd), T1 = (xb - xd) */ + T0 = __SSAT(T0 - U0, 16U); + T1 = __SSAT(T1 - U1, 16U); + + /* writing the butterfly processed i0 + fftLen/2 sample */ + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + pSrc16[i2 * 2U] = (S0 >> 1U) + (T1 >> 1U); + pSrc16[(i2 * 2U) + 1U] = (S1 >> 1U) - (T0 >> 1U); + + /* writing the butterfly processed i0 + 3fftLen/4 sample */ + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + pSrc16[i3 * 2U] = (S0 >> 1U) - (T1 >> 1U); + pSrc16[(i3 * 2U) + 1U] = (S1 >> 1U) + (T0 >> 1U); + + } + + /* end of last stage process */ + + /* output is in 11.5(q5) format for the 1024 point */ + /* output is in 9.7(q7) format for the 256 point */ + /* output is in 7.9(q9) format for the 64 point */ + /* output is in 5.11(q11) format for the 16 point */ + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + + +/** + @brief Core function for the Q15 CIFFT butterfly process. + @param[in,out] pSrc16 points to the in-place buffer of Q15 data type + @param[in] fftLen length of the FFT + @param[in] pCoef16 points to twiddle coefficient buffer + @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + @return none + */ + +/* + * Radix-4 IFFT algorithm used is : + * + * CIFFT uses same twiddle coefficients as CFFT function + * x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4] + * + * + * IFFT is implemented with following changes in equations from FFT + * + * Input real and imaginary data: + * x(n) = xa + j * ya + * x(n+N/4 ) = xb + j * yb + * x(n+N/2 ) = xc + j * yc + * x(n+3N 4) = xd + j * yd + * + * + * Output real and imaginary data: + * x(4r) = xa'+ j * ya' + * x(4r+1) = xb'+ j * yb' + * x(4r+2) = xc'+ j * yc' + * x(4r+3) = xd'+ j * yd' + * + * + * Twiddle factors for radix-4 IFFT: + * Wn = co1 + j * (si1) + * W2n = co2 + j * (si2) + * W3n = co3 + j * (si3) + + * The real and imaginary output values for the radix-4 butterfly are + * xa' = xa + xb + xc + xd + * ya' = ya + yb + yc + yd + * xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) + * yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) + * xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) + * yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) + * xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3) + * yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3) + * + */ + +void arm_radix4_butterfly_inverse_q15( + q15_t * pSrc16, + uint32_t fftLen, + const q15_t * pCoef16, + uint32_t twidCoefModifier) +{ + +#if defined (ARM_MATH_DSP) + + q31_t R, S, T, U; + q31_t C1, C2, C3, out1, out2; + uint32_t n1, n2, ic, i0, j, k; + + q15_t *ptr1; + q15_t *pSi0; + q15_t *pSi1; + q15_t *pSi2; + q15_t *pSi3; + + q31_t xaya, xbyb, xcyc, xdyd; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + + /* Index for twiddle coefficient */ + ic = 0U; + + /* Index for input read and output write */ + j = n2; + + pSi0 = pSrc16; + pSi1 = pSi0 + 2 * n2; + pSi2 = pSi1 + 2 * n2; + pSi3 = pSi2 + 2 * n2; + + /* Input is in 1.15(q15) format */ + + /* start of first stage process */ + do + { + /* Butterfly implementation */ + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T = read_q15x2 (pSi0); + T = __SHADD16(T, 0); + T = __SHADD16(T, 0); + + /* Read yc (real), xc(imag) input */ + S = read_q15x2 (pSi2); + S = __SHADD16(S, 0); + S = __SHADD16(S, 0); + + /* R = packed((ya + yc), (xa + xc) ) */ + R = __QADD16(T, S); + + /* S = packed((ya - yc), (xa - xc) ) */ + S = __QSUB16(T, S); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + T = __SHADD16(T, 0); + T = __SHADD16(T, 0); + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + U = __SHADD16(U, 0); + U = __SHADD16(U, 0); + + /* T = packed((yb + yd), (xb + xd) ) */ + T = __QADD16(T, U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + write_q15x2_ia (&pSi0, __SHADD16(R, T)); + + /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */ + R = __QSUB16(R, T); + + /* co2 & si2 are read from SIMD Coefficient pointer */ + C2 = read_q15x2 ((q15_t *) pCoef16 + (4U * ic)); + +#ifndef ARM_MATH_BIG_ENDIAN + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out1 = __SMUSD(C2, R) >> 16U; + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = __SMUADX(C2, R); +#else + /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out1 = __SMUADX(C2, R) >> 16U; + /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out2 = __SMUSD(__QSUB16(0, C2), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Reading i0+fftLen/4 */ + /* T = packed(yb, xb) */ + T = read_q15x2 (pSi1); + T = __SHADD16(T, 0); + T = __SHADD16(T, 0); + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* writing output(xc', yc') in little endian format */ + write_q15x2_ia (&pSi1, (q31_t) __PKHBT( out1, out2, 0 )); + + /* Butterfly calculations */ + /* U = packed(yd, xd) */ + U = read_q15x2 (pSi3); + U = __SHADD16(U, 0); + U = __SHADD16(U, 0); + + /* T = packed(yb-yd, xb-xd) */ + T = __QSUB16(T, U); + +#ifndef ARM_MATH_BIG_ENDIAN + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __QSAX(S, T); + /* S = packed((ya-yc) + (xb- xd), (xa-xc) - (yb-yd)) */ + S = __QASX(S, T); +#else + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __QASX(S, T); + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __QSAX(S, T); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* co1 & si1 are read from SIMD Coefficient pointer */ + C1 = read_q15x2 ((q15_t *) pCoef16 + (2U * ic)); + /* Butterfly process for the i0+fftLen/2 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out1 = __SMUSD(C1, S) >> 16U; + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out2 = __SMUADX(C1, S); +#else + /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out1 = __SMUADX(C1, S) >> 16U; + /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out2 = __SMUSD(__QSUB16(0, C1), S); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* writing output(xb', yb') in little endian format */ + write_q15x2_ia (&pSi2, __PKHBT( out1, out2, 0 )); + + /* co3 & si3 are read from SIMD Coefficient pointer */ + C3 = read_q15x2 ((q15_t *) pCoef16 + (6U * ic)); + /* Butterfly process for the i0+3fftLen/4 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + out1 = __SMUSD(C3, R) >> 16U; + /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + out2 = __SMUADX(C3, R); +#else + /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + out1 = __SMUADX(C3, R) >> 16U; + /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + out2 = __SMUSD(__QSUB16(0, C3), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* writing output(xd', yd') in little endian format */ + write_q15x2_ia (&pSi3, __PKHBT( out1, out2, 0 )); + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + } while (--j); + /* data is in 4.11(q11) format */ + + /* end of first stage process */ + + + /* start of middle stage process */ + + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + + /* Calculation of Middle stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the middle stage */ + n1 = n2; + n2 >>= 2U; + ic = 0U; + + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + C1 = read_q15x2 ((q15_t *) pCoef16 + (2U * ic)); + C2 = read_q15x2 ((q15_t *) pCoef16 + (4U * ic)); + C3 = read_q15x2 ((q15_t *) pCoef16 + (6U * ic)); + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + pSi0 = pSrc16 + 2 * j; + pSi1 = pSi0 + 2 * n2; + pSi2 = pSi1 + 2 * n2; + pSi3 = pSi2 + 2 * n2; + + /* Butterfly implementation */ + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T = read_q15x2 (pSi0); + + /* Read yc (real), xc(imag) input */ + S = read_q15x2 (pSi2); + + /* R = packed( (ya + yc), (xa + xc)) */ + R = __QADD16(T, S); + + /* S = packed((ya - yc), (xa - xc)) */ + S = __QSUB16(T, S); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + + /* T = packed( (yb + yd), (xb + xd)) */ + T = __QADD16(T, U); + + /* writing the butterfly processed i0 sample */ + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + out1 = __SHADD16(R, T); + out1 = __SHADD16(out1, 0); + write_q15x2 (pSi0, out1); + pSi0 += 2 * n1; + + /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */ + R = __SHSUB16(R, T); + +#ifndef ARM_MATH_BIG_ENDIAN + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out1 = __SMUSD(C2, R) >> 16U; + + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = __SMUADX(C2, R); +#else + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out1 = __SMUADX(R, C2) >> 16U; + + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out2 = __SMUSD(__QSUB16(0, C2), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Reading i0+3fftLen/4 */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + write_q15x2 (pSi1, __PKHBT( out1, out2, 0 )); + pSi1 += 2 * n1; + + /* Butterfly calculations */ + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + + /* T = packed(yb-yd, xb-xd) */ + T = __QSUB16(T, U); + +#ifndef ARM_MATH_BIG_ENDIAN + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __SHSAX(S, T); + + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __SHASX(S, T); + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = __SMUSD(C1, S) >> 16U; + out2 = __SMUADX(C1, S); +#else + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __SHASX(S, T); + + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __SHSAX(S, T); + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = __SMUADX(S, C1) >> 16U; + out2 = __SMUSD(__QSUB16(0, C1), S); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + write_q15x2 (pSi2, __PKHBT( out1, out2, 0 )); + pSi2 += 2 * n1; + + /* Butterfly process for the i0+3fftLen/4 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(C3, R) >> 16U; + out2 = __SMUADX(C3, R); +#else + out1 = __SMUADX(C3, R) >> 16U; + out2 = __SMUSD(__QSUB16(0, C3), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + write_q15x2 (pSi3, __PKHBT( out1, out2, 0 )); + pSi3 += 2 * n1; + } + } + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + } + /* end of middle stage process */ + + /* data is in 10.6(q6) format for the 1024 point */ + /* data is in 8.8(q8) format for the 256 point */ + /* data is in 6.10(q10) format for the 64 point */ + /* data is in 4.12(q12) format for the 16 point */ + + /* Initializations for the last stage */ + j = fftLen >> 2; + + ptr1 = &pSrc16[0]; + + /* start of last stage process */ + + /* Butterfly implementation */ + do + { + /* Read xa (real), ya(imag) input */ + xaya = read_q15x2_ia (&ptr1); + + /* Read xb (real), yb(imag) input */ + xbyb = read_q15x2_ia (&ptr1); + + /* Read xc (real), yc(imag) input */ + xcyc = read_q15x2_ia (&ptr1); + + /* Read xd (real), yd(imag) input */ + xdyd = read_q15x2_ia (&ptr1); + + /* R = packed((ya + yc), (xa + xc)) */ + R = __QADD16(xaya, xcyc); + + /* T = packed((yb + yd), (xb + xd)) */ + T = __QADD16(xbyb, xdyd); + + /* pointer updation for writing */ + ptr1 = ptr1 - 8U; + + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + write_q15x2_ia (&ptr1, __SHADD16(R, T)); + + /* T = packed((yb + yd), (xb + xd)) */ + T = __QADD16(xbyb, xdyd); + + /* xc' = (xa-xb+xc-xd) */ + /* yc' = (ya-yb+yc-yd) */ + write_q15x2_ia (&ptr1, __SHSUB16(R, T)); + + /* S = packed((ya - yc), (xa - xc)) */ + S = __QSUB16(xaya, xcyc); + + /* Read yd (real), xd(imag) input */ + /* T = packed( (yb - yd), (xb - xd)) */ + U = __QSUB16(xbyb, xdyd); + +#ifndef ARM_MATH_BIG_ENDIAN + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + write_q15x2_ia (&ptr1, __SHASX(S, U)); + + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + write_q15x2_ia (&ptr1, __SHSAX(S, U)); +#else + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + write_q15x2_ia (&ptr1, __SHSAX(S, U)); + + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + write_q15x2_ia (&ptr1, __SHASX(S, U)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + } while (--j); + + /* end of last stage process */ + + /* output is in 11.5(q5) format for the 1024 point */ + /* output is in 9.7(q7) format for the 256 point */ + /* output is in 7.9(q9) format for the 64 point */ + /* output is in 5.11(q11) format for the 16 point */ + + +#else /* arm_radix4_butterfly_inverse_q15 */ + + q15_t R0, R1, S0, S1, T0, T1, U0, U1; + q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2; + uint32_t n1, n2, ic, i0, i1, i2, i3, j, k; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + + /* Index for twiddle coefficient */ + ic = 0U; + + /* Index for input read and output write */ + i0 = 0U; + + j = n2; + + /* Input is in 1.15(q15) format */ + + /* Start of first stage process */ + do + { + /* Butterfly implementation */ + + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* input is down scale by 4 to avoid overflow */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U] >> 2U; + T1 = pSrc16[(i0 * 2U) + 1U] >> 2U; + /* input is down scale by 4 to avoid overflow */ + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U] >> 2U; + S1 = pSrc16[(i2 * 2U) + 1U] >> 2U; + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16U); + R1 = __SSAT(T1 + S1, 16U); + /* S0 = (ya - yc), S1 = (xa - xc) */ + S0 = __SSAT(T0 - S0, 16U); + S1 = __SSAT(T1 - S1, 16U); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* input is down scale by 4 to avoid overflow */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U] >> 2U; + T1 = pSrc16[(i1 * 2U) + 1U] >> 2U; + /* Read yd (real), xd(imag) input */ + /* input is down scale by 4 to avoid overflow */ + U0 = pSrc16[i3 * 2U] >> 2U; + U1 = pSrc16[(i3 * 2U) + 1U] >> 2U; + + /* T0 = (yb + yd), T1 = (xb + xd) */ + T0 = __SSAT(T0 + U0, 16U); + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U); + pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U); + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc)- (xb + xd) */ + R0 = __SSAT(R0 - T0, 16U); + R1 = __SSAT(R1 - T1, 16U); + /* co2 & si2 are read from Coefficient pointer */ + Co2 = pCoef16[2U * ic * 2U]; + Si2 = pCoef16[(2U * ic * 2U) + 1U]; + /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */ + out1 = (q15_t) ((Co2 * R0 - Si2 * R1) >> 16U); + /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */ + out2 = (q15_t) ((Si2 * R0 + Co2 * R1) >> 16U); + + /* Reading i0+fftLen/4 */ + /* input is down scale by 4 to avoid overflow */ + /* T0 = yb, T1 = xb */ + T0 = pSrc16[i1 * 2U] >> 2U; + T1 = pSrc16[(i1 * 2U) + 1U] >> 2U; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* writing output(xc', yc') in little endian format */ + pSrc16[i1 * 2U] = out1; + pSrc16[(i1 * 2U) + 1U] = out2; + + /* Butterfly calculations */ + /* input is down scale by 4 to avoid overflow */ + /* U0 = yd, U1 = xd) */ + U0 = pSrc16[i3 * 2U] >> 2U; + U1 = pSrc16[(i3 * 2U) + 1U] >> 2U; + + /* T0 = yb-yd, T1 = xb-xd) */ + T0 = __SSAT(T0 - U0, 16U); + T1 = __SSAT(T1 - U1, 16U); + /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */ + R0 = (q15_t) __SSAT((q31_t) (S0 + T1), 16); + R1 = (q15_t) __SSAT((q31_t) (S1 - T0), 16); + /* S = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */ + S0 = (q15_t) __SSAT((q31_t) (S0 - T1), 16); + S1 = (q15_t) __SSAT((q31_t) (S1 + T0), 16); + + /* co1 & si1 are read from Coefficient pointer */ + Co1 = pCoef16[ic * 2U]; + Si1 = pCoef16[(ic * 2U) + 1U]; + /* Butterfly process for the i0+fftLen/2 sample */ + /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */ + out1 = (q15_t) ((Co1 * S0 - Si1 * S1) >> 16U); + /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */ + out2 = (q15_t) ((Si1 * S0 + Co1 * S1) >> 16U); + /* writing output(xb', yb') in little endian format */ + pSrc16[i2 * 2U] = out1; + pSrc16[(i2 * 2U) + 1U] = out2; + + /* Co3 & si3 are read from Coefficient pointer */ + Co3 = pCoef16[3U * ic * 2U]; + Si3 = pCoef16[(3U * ic * 2U) + 1U]; + /* Butterfly process for the i0+3fftLen/4 sample */ + /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */ + out1 = (q15_t) ((Co3 * R0 - Si3 * R1) >> 16U); + /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */ + out2 = (q15_t) ((Si3 * R0 + Co3 * R1) >> 16U); + /* writing output(xd', yd') in little endian format */ + pSrc16[i3 * 2U] = out1; + pSrc16[(i3 * 2U) + 1U] = out2; + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + /* End of first stage process */ + + /* data is in 4.11(q11) format */ + + + /* Start of Middle stage process */ + + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + + /* Calculation of Middle stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the middle stage */ + n1 = n2; + n2 >>= 2U; + ic = 0U; + + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + Co1 = pCoef16[ic * 2U]; + Si1 = pCoef16[(ic * 2U) + 1U]; + Co2 = pCoef16[2U * ic * 2U]; + Si2 = pCoef16[2U * ic * 2U + 1U]; + Co3 = pCoef16[3U * ic * 2U]; + Si3 = pCoef16[(3U * ic * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + /* Butterfly implementation */ + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U]; + T1 = pSrc16[(i0 * 2U) + 1U]; + + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U]; + S1 = pSrc16[(i2 * 2U) + 1U]; + + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16U); + R1 = __SSAT(T1 + S1, 16U); + /* S0 = (ya - yc), S1 = (xa - xc) */ + S0 = __SSAT(T0 - S0, 16U); + S1 = __SSAT(T1 - S1, 16U); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = (yb + yd), T1 = (xb + xd) */ + T0 = __SSAT(T0 + U0, 16U); + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + pSrc16[i0 * 2U] = ((R0 >> 1U) + (T0 >> 1U)) >> 1U; + pSrc16[(i0 * 2U) + 1U] = ((R1 >> 1U) + (T1 >> 1U)) >> 1U; + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */ + R0 = (R0 >> 1U) - (T0 >> 1U); + R1 = (R1 >> 1U) - (T1 >> 1U); + + /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */ + out1 = (q15_t) ((Co2 * R0 - Si2 * R1) >> 16); + /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */ + out2 = (q15_t) ((Si2 * R0 + Co2 * R1) >> 16); + + /* Reading i0+3fftLen/4 */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */ + /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */ + pSrc16[i1 * 2U] = out1; + pSrc16[(i1 * 2U) + 1U] = out2; + + /* Butterfly calculations */ + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = yb-yd, T1 = xb-xd) */ + T0 = __SSAT(T0 - U0, 16U); + T1 = __SSAT(T1 - U1, 16U); + + /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */ + R0 = (S0 >> 1U) + (T1 >> 1U); + R1 = (S1 >> 1U) - (T0 >> 1U); + + /* S1 = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */ + S0 = (S0 >> 1U) - (T1 >> 1U); + S1 = (S1 >> 1U) + (T0 >> 1U); + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = (q15_t) ((Co1 * S0 - Si1 * S1) >> 16U); + out2 = (q15_t) ((Si1 * S0 + Co1 * S1) >> 16U); + /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */ + /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */ + pSrc16[i2 * 2U] = out1; + pSrc16[(i2 * 2U) + 1U] = out2; + + /* Butterfly process for the i0+3fftLen/4 sample */ + out1 = (q15_t) ((Co3 * R0 - Si3 * R1) >> 16U); + + out2 = (q15_t) ((Si3 * R0 + Co3 * R1) >> 16U); + /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */ + /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */ + pSrc16[i3 * 2U] = out1; + pSrc16[(i3 * 2U) + 1U] = out2; + + + } + } + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + } + /* End of Middle stages process */ + + + /* data is in 10.6(q6) format for the 1024 point */ + /* data is in 8.8(q8) format for the 256 point */ + /* data is in 6.10(q10) format for the 64 point */ + /* data is in 4.12(q12) format for the 16 point */ + + /* start of last stage process */ + + + /* Initializations for the last stage */ + n1 = n2; + n2 >>= 2U; + + /* Butterfly implementation */ + for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U]; + T1 = pSrc16[(i0 * 2U) + 1U]; + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U]; + S1 = pSrc16[(i2 * 2U) + 1U]; + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16U); + R1 = __SSAT(T1 + S1, 16U); + /* S0 = (ya - yc), S1 = (xa - xc) */ + S0 = __SSAT(T0 - S0, 16U); + S1 = __SSAT(T1 - S1, 16U); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = (yb + yd), T1 = (xb + xd) */ + T0 = __SSAT(T0 + U0, 16U); + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U); + pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U); + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */ + R0 = (R0 >> 1U) - (T0 >> 1U); + R1 = (R1 >> 1U) - (T1 >> 1U); + + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd) */ + /* yc' = (ya-yb+yc-yd) */ + pSrc16[i1 * 2U] = R0; + pSrc16[(i1 * 2U) + 1U] = R1; + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + /* T0 = (yb - yd), T1 = (xb - xd) */ + T0 = __SSAT(T0 - U0, 16U); + T1 = __SSAT(T1 - U1, 16U); + + /* writing the butterfly processed i0 + fftLen/2 sample */ + /* xb' = (xa-yb-xc+yd) */ + /* yb' = (ya+xb-yc-xd) */ + pSrc16[i2 * 2U] = (S0 >> 1U) - (T1 >> 1U); + pSrc16[(i2 * 2U) + 1U] = (S1 >> 1U) + (T0 >> 1U); + + + /* writing the butterfly processed i0 + 3fftLen/4 sample */ + /* xd' = (xa+yb-xc-yd) */ + /* yd' = (ya-xb-yc+xd) */ + pSrc16[i3 * 2U] = (S0 >> 1U) + (T1 >> 1U); + pSrc16[(i3 * 2U) + 1U] = (S1 >> 1U) - (T0 >> 1U); + } + /* end of last stage process */ + + /* output is in 11.5(q5) format for the 1024 point */ + /* output is in 9.7(q7) format for the 256 point */ + /* output is in 7.9(q9) format for the 64 point */ + /* output is in 5.11(q11) format for the 16 point */ + +#endif /* #if defined (ARM_MATH_DSP) */ + +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c new file mode 100644 index 00000000..46c1e478 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c @@ -0,0 +1,827 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_q31.c + * Description: This file has function definition of Radix-4 FFT & IFFT function and + * In-place bit reversal using bit reversal table + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +void arm_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier); + +void arm_radix4_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier); + +void arm_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the Q31 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed in the future. + @param[in] S points to an instance of the Q31 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + + @par Input and output formats: + Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. + Hence the output format is different for different FFT sizes. + The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT: + @par + \image html CFFTQ31.gif "Input and Output Formats for Q31 CFFT" + \image html CIFFTQ31.gif "Input and Output Formats for Q31 CIFFT" + */ + +void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc) +{ + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-4 */ + arm_radix4_butterfly_inverse_q31(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + else + { + /* Complex FFT radix-4 */ + arm_radix4_butterfly_q31(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + +/** + @} end of ComplexFFT group + */ + +/* + * Radix-4 FFT algorithm used is : + * + * Input real and imaginary data: + * x(n) = xa + j * ya + * x(n+N/4 ) = xb + j * yb + * x(n+N/2 ) = xc + j * yc + * x(n+3N 4) = xd + j * yd + * + * + * Output real and imaginary data: + * x(4r) = xa'+ j * ya' + * x(4r+1) = xb'+ j * yb' + * x(4r+2) = xc'+ j * yc' + * x(4r+3) = xd'+ j * yd' + * + * + * Twiddle factors for radix-4 FFT: + * Wn = co1 + j * (- si1) + * W2n = co2 + j * (- si2) + * W3n = co3 + j * (- si3) + * + * Butterfly implementation: + * xa' = xa + xb + xc + xd + * ya' = ya + yb + yc + yd + * xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) + * yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) + * xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) + * yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) + * xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) + * yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) + * + */ + +/** + @brief Core function for the Q31 CFFT butterfly process. + @param[in,out] pSrc points to the in-place buffer of Q31 data type. + @param[in] fftLen length of the FFT. + @param[in] pCoef points to twiddle coefficient buffer. + @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + @return none + */ + +void arm_radix4_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier) +{ + uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k; + q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3; + + q31_t xa, xb, xc, xd; + q31_t ya, yb, yc, yd; + q31_t xa_out, xb_out, xc_out, xd_out; + q31_t ya_out, yb_out, yc_out, yd_out; + + q31_t *ptr1; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + + /* start of first stage process */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* input is in 1.31(q31) format and provide 4 guard bits for the input */ + + /* Butterfly implementation */ + /* xa + xc */ + r1 = (pSrc[(2U * i0)] >> 4U) + (pSrc[(2U * i2)] >> 4U); + /* xa - xc */ + r2 = (pSrc[(2U * i0)] >> 4U) - (pSrc[(2U * i2)] >> 4U); + + /* xb + xd */ + t1 = (pSrc[(2U * i1)] >> 4U) + (pSrc[(2U * i3)] >> 4U); + + /* ya + yc */ + s1 = (pSrc[(2U * i0) + 1U] >> 4U) + (pSrc[(2U * i2) + 1U] >> 4U); + /* ya - yc */ + s2 = (pSrc[(2U * i0) + 1U] >> 4U) - (pSrc[(2U * i2) + 1U] >> 4U); + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1); + /* (xa + xc) - (xb + xd) */ + r1 = r1 - t1; + /* yb + yd */ + t2 = (pSrc[(2U * i1) + 1U] >> 4U) + (pSrc[(2U * i3) + 1U] >> 4U); + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2); + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* yb - yd */ + t1 = (pSrc[(2U * i1) + 1U] >> 4U) - (pSrc[(2U * i3) + 1U] >> 4U); + /* xb - xd */ + t2 = (pSrc[(2U * i1)] >> 4U) - (pSrc[(2U * i3)] >> 4U); + + /* index calculation for the coefficients */ + ia2 = 2U * ia1; + co2 = pCoef[(ia2 * 2U)]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) + + ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1U; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32)) - + ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1U; + + /* (xa - xc) + (yb - yd) */ + r1 = r2 + t1; + /* (xa - xc) - (yb - yd) */ + r2 = r2 - t1; + + /* (ya - yc) - (xb - xd) */ + s1 = s2 - t2; + /* (ya - yc) + (xb - xd) */ + s2 = s2 + t2; + + co1 = pCoef[(ia1 * 2U)]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) + + ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1U; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) - + ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1U; + + /* index calculation for the coefficients */ + ia3 = 3U * ia1; + co3 = pCoef[(ia3 * 2U)]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) + + ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1U; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) - + ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1U; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + /* end of first stage process */ + + /* data is in 5.27(q27) format */ + + + /* start of Middle stages process */ + + + /* each stage in middle stages provides two down scaling of the input */ + + twidCoefModifier <<= 2U; + + + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[(ia1 * 2U)]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[(ia2 * 2U)]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[(ia3 * 2U)]; + si3 = pCoef[(ia3 * 2U) + 1U]; + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = pSrc[2U * i0] + pSrc[2U * i2]; + /* xa - xc */ + r2 = pSrc[2U * i0] - pSrc[2U * i2]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1) >> 2U; + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2) >> 2U; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) + + ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1U; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32)) - + ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1U; + + /* (xa - xc) + (yb - yd) */ + r1 = r2 + t1; + /* (xa - xc) - (yb - yd) */ + r2 = r2 - t1; + + /* (ya - yc) - (xb - xd) */ + s1 = s2 - t2; + /* (ya - yc) + (xb - xd) */ + s2 = s2 + t2; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) + + ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1U; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) - + ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1U; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) + + ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1U; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) - + ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1U; + } + } + twidCoefModifier <<= 2U; + } + + /* End of Middle stages process */ + + /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */ + /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */ + /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */ + /* data is in 5.27(q27) format for the 16 point as there are no middle stages */ + + + /* start of Last stage process */ + /* Initializations for the last stage */ + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + /* Read xa (real), ya(imag) input */ + xa = *ptr1++; + ya = *ptr1++; + + /* Read xb (real), yb(imag) input */ + xb = *ptr1++; + yb = *ptr1++; + + /* Read xc (real), yc(imag) input */ + xc = *ptr1++; + yc = *ptr1++; + + /* Read xc (real), yc(imag) input */ + xd = *ptr1++; + yd = *ptr1++; + + /* xa' = xa + xb + xc + xd */ + xa_out = xa + xb + xc + xd; + + /* ya' = ya + yb + yc + yd */ + ya_out = ya + yb + yc + yd; + + /* pointer updation for writing */ + ptr1 = ptr1 - 8U; + + /* writing xa' and ya' */ + *ptr1++ = xa_out; + *ptr1++ = ya_out; + + xc_out = (xa - xb + xc - xd); + yc_out = (ya - yb + yc - yd); + + /* writing xc' and yc' */ + *ptr1++ = xc_out; + *ptr1++ = yc_out; + + xb_out = (xa + yb - xc - yd); + yb_out = (ya - xb - yc + xd); + + /* writing xb' and yb' */ + *ptr1++ = xb_out; + *ptr1++ = yb_out; + + xd_out = (xa - yb - xc + yd); + yd_out = (ya + xb - yc - xd); + + /* writing xd' and yd' */ + *ptr1++ = xd_out; + *ptr1++ = yd_out; + + + } while (--j); + + /* output is in 11.21(q21) format for the 1024 point */ + /* output is in 9.23(q23) format for the 256 point */ + /* output is in 7.25(q25) format for the 64 point */ + /* output is in 5.27(q27) format for the 16 point */ + + /* End of last stage process */ + +} + + +/** + @brief Core function for the Q31 CIFFT butterfly process. + @param[in,out] pSrc points to the in-place buffer of Q31 data type. + @param[in] fftLen length of the FFT. + @param[in] pCoef points to twiddle coefficient buffer. + @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + @return none + */ + +/* + * Radix-4 IFFT algorithm used is : + * + * CIFFT uses same twiddle coefficients as CFFT Function + * x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4] + * + * + * IFFT is implemented with following changes in equations from FFT + * + * Input real and imaginary data: + * x(n) = xa + j * ya + * x(n+N/4 ) = xb + j * yb + * x(n+N/2 ) = xc + j * yc + * x(n+3N 4) = xd + j * yd + * + * + * Output real and imaginary data: + * x(4r) = xa'+ j * ya' + * x(4r+1) = xb'+ j * yb' + * x(4r+2) = xc'+ j * yc' + * x(4r+3) = xd'+ j * yd' + * + * + * Twiddle factors for radix-4 IFFT: + * Wn = co1 + j * (si1) + * W2n = co2 + j * (si2) + * W3n = co3 + j * (si3) + + * The real and imaginary output values for the radix-4 butterfly are + * xa' = xa + xb + xc + xd + * ya' = ya + yb + yc + yd + * xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) + * yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) + * xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) + * yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) + * xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3) + * yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3) + * + */ + +void arm_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier) +{ + uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k; + q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3; + q31_t xa, xb, xc, xd; + q31_t ya, yb, yc, yd; + q31_t xa_out, xb_out, xc_out, xd_out; + q31_t ya_out, yb_out, yc_out, yd_out; + + q31_t *ptr1; + + /* input is be 1.31(q31) format for all FFT sizes */ + /* Total process is divided into three stages */ + /* process first stage, middle stages, & last stage */ + + /* Start of first stage process */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + do + { + /* input is in 1.31(q31) format and provide 4 guard bits for the input */ + + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = (pSrc[2U * i0] >> 4U) + (pSrc[2U * i2] >> 4U); + /* xa - xc */ + r2 = (pSrc[2U * i0] >> 4U) - (pSrc[2U * i2] >> 4U); + + /* xb + xd */ + t1 = (pSrc[2U * i1] >> 4U) + (pSrc[2U * i3] >> 4U); + + /* ya + yc */ + s1 = (pSrc[(2U * i0) + 1U] >> 4U) + (pSrc[(2U * i2) + 1U] >> 4U); + /* ya - yc */ + s2 = (pSrc[(2U * i0) + 1U] >> 4U) - (pSrc[(2U * i2) + 1U] >> 4U); + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1); + /* (xa + xc) - (xb + xd) */ + r1 = r1 - t1; + /* yb + yd */ + t2 = (pSrc[(2U * i1) + 1U] >> 4U) + (pSrc[(2U * i3) + 1U] >> 4U); + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2); + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* yb - yd */ + t1 = (pSrc[(2U * i1) + 1U] >> 4U) - (pSrc[(2U * i3) + 1U] >> 4U); + /* xb - xd */ + t2 = (pSrc[2U * i1] >> 4U) - (pSrc[2U * i3] >> 4U); + + /* index calculation for the coefficients */ + ia2 = 2U * ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) - + ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1U; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[2U * i1 + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32)) + + ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1U; + + /* (xa - xc) - (yb - yd) */ + r1 = r2 - t1; + /* (xa - xc) + (yb - yd) */ + r2 = r2 + t1; + + /* (ya - yc) + (xb - xd) */ + s1 = s2 + t2; + /* (ya - yc) - (xb - xd) */ + s2 = s2 - t2; + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) - + ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1U; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) + + ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1U; + + /* index calculation for the coefficients */ + ia3 = 3U * ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) - + ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1U; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) + + ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1U; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + /* data is in 5.27(q27) format */ + /* each stage provides two down scaling of the input */ + + + /* Start of Middle stages process */ + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + for (j = 0; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[(ia1 * 2U)]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[(ia2 * 2U)]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[(ia3 * 2U)]; + si3 = pCoef[(ia3 * 2U) + 1U]; + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = pSrc[2U * i0] + pSrc[2U * i2]; + /* xa - xc */ + r2 = pSrc[2U * i0] - pSrc[2U * i2]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1) >> 2U; + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2) >> 2U; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32U)) - + ((int32_t) (((q63_t) s1 * si2) >> 32U))) >> 1U; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32U)) + + ((int32_t) (((q63_t) r1 * si2) >> 32U))) >> 1U; + + /* (xa - xc) - (yb - yd) */ + r1 = r2 - t1; + /* (xa - xc) + (yb - yd) */ + r2 = r2 + t1; + + /* (ya - yc) + (xb - xd) */ + s1 = s2 + t2; + /* (ya - yc) - (xb - xd) */ + s2 = s2 - t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) - + ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1U; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) + + ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1U; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[(2U * i3)] = (((int32_t) (((q63_t) r2 * co3) >> 32)) - + ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1U; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) + + ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1U; + } + } + twidCoefModifier <<= 2U; + } + + /* End of Middle stages process */ + + /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */ + /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */ + /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */ + /* data is in 5.27(q27) format for the 16 point as there are no middle stages */ + + + /* Start of last stage process */ + + + /* Initializations for the last stage */ + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + /* Read xa (real), ya(imag) input */ + xa = *ptr1++; + ya = *ptr1++; + + /* Read xb (real), yb(imag) input */ + xb = *ptr1++; + yb = *ptr1++; + + /* Read xc (real), yc(imag) input */ + xc = *ptr1++; + yc = *ptr1++; + + /* Read xc (real), yc(imag) input */ + xd = *ptr1++; + yd = *ptr1++; + + /* xa' = xa + xb + xc + xd */ + xa_out = xa + xb + xc + xd; + + /* ya' = ya + yb + yc + yd */ + ya_out = ya + yb + yc + yd; + + /* pointer updation for writing */ + ptr1 = ptr1 - 8U; + + /* writing xa' and ya' */ + *ptr1++ = xa_out; + *ptr1++ = ya_out; + + xc_out = (xa - xb + xc - xd); + yc_out = (ya - yb + yc - yd); + + /* writing xc' and yc' */ + *ptr1++ = xc_out; + *ptr1++ = yc_out; + + xb_out = (xa - yb - xc + yd); + yb_out = (ya + xb - yc - xd); + + /* writing xb' and yb' */ + *ptr1++ = xb_out; + *ptr1++ = yb_out; + + xd_out = (xa + yb - xc - yd); + yd_out = (ya - xb - yc + xd); + + /* writing xd' and yd' */ + *ptr1++ = xd_out; + *ptr1++ = yd_out; + + } while (--j); + + /* output is in 11.21(q21) format for the 1024 point */ + /* output is in 9.23(q23) format for the 256 point */ + /* output is in 7.25(q25) format for the 64 point */ + /* output is in 5.27(q27) format for the 16 point */ + + /* End of last stage process */ +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f16.c new file mode 100644 index 00000000..b7eb37aa --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f16.c @@ -0,0 +1,289 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix8_f16.c + * Description: Radix-8 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/* ---------------------------------------------------------------------- + * Internal helper function used by the FFTs + * -------------------------------------------------------------------- */ + +/** + brief Core function for the floating-point CFFT butterfly process. + param[in,out] pSrc points to the in-place buffer of floating-point data type. + param[in] fftLen length of the FFT. + param[in] pCoef points to the twiddle coefficient buffer. + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + return none +*/ + +void arm_radix8_butterfly_f16( + float16_t * pSrc, + uint16_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier) +{ + uint32_t ia1, ia2, ia3, ia4, ia5, ia6, ia7; + uint32_t i1, i2, i3, i4, i5, i6, i7, i8; + uint32_t id; + uint32_t n1, n2, j; + + float16_t r1, r2, r3, r4, r5, r6, r7, r8; + float16_t t1, t2; + float16_t s1, s2, s3, s4, s5, s6, s7, s8; + float16_t p1, p2, p3, p4; + float16_t co2, co3, co4, co5, co6, co7, co8; + float16_t si2, si3, si4, si5, si6, si7, si8; + const float16_t C81 = 0.70710678118f16; + + n2 = fftLen; + + do + { + n1 = n2; + n2 = n2 >> 3; + i1 = 0; + + do + { + i2 = i1 + n2; + i3 = i2 + n2; + i4 = i3 + n2; + i5 = i4 + n2; + i6 = i5 + n2; + i7 = i6 + n2; + i8 = i7 + n2; + r1 = (_Float16)pSrc[2 * i1] + (_Float16)pSrc[2 * i5]; + r5 = (_Float16)pSrc[2 * i1] - (_Float16)pSrc[2 * i5]; + r2 = (_Float16)pSrc[2 * i2] + (_Float16)pSrc[2 * i6]; + r6 = (_Float16)pSrc[2 * i2] - (_Float16)pSrc[2 * i6]; + r3 = (_Float16)pSrc[2 * i3] + (_Float16)pSrc[2 * i7]; + r7 = (_Float16)pSrc[2 * i3] - (_Float16)pSrc[2 * i7]; + r4 = (_Float16)pSrc[2 * i4] + (_Float16)pSrc[2 * i8]; + r8 = (_Float16)pSrc[2 * i4] - (_Float16)pSrc[2 * i8]; + t1 = (_Float16)r1 - (_Float16)r3; + r1 = (_Float16)r1 + (_Float16)r3; + r3 = (_Float16)r2 - (_Float16)r4; + r2 = (_Float16)r2 + (_Float16)r4; + pSrc[2 * i1] = (_Float16)r1 + (_Float16)r2; + pSrc[2 * i5] = (_Float16)r1 - (_Float16)r2; + r1 = (_Float16)pSrc[2 * i1 + 1] + (_Float16)pSrc[2 * i5 + 1]; + s5 = (_Float16)pSrc[2 * i1 + 1] - (_Float16)pSrc[2 * i5 + 1]; + r2 = (_Float16)pSrc[2 * i2 + 1] + (_Float16)pSrc[2 * i6 + 1]; + s6 = (_Float16)pSrc[2 * i2 + 1] - (_Float16)pSrc[2 * i6 + 1]; + s3 = (_Float16)pSrc[2 * i3 + 1] + (_Float16)pSrc[2 * i7 + 1]; + s7 = (_Float16)pSrc[2 * i3 + 1] - (_Float16)pSrc[2 * i7 + 1]; + r4 = (_Float16)pSrc[2 * i4 + 1] + (_Float16)pSrc[2 * i8 + 1]; + s8 = (_Float16)pSrc[2 * i4 + 1] - (_Float16)pSrc[2 * i8 + 1]; + t2 = (_Float16)r1 - (_Float16)s3; + r1 = (_Float16)r1 + (_Float16)s3; + s3 = (_Float16)r2 - (_Float16)r4; + r2 = (_Float16)r2 + (_Float16)r4; + pSrc[2 * i1 + 1] = (_Float16)r1 + (_Float16)r2; + pSrc[2 * i5 + 1] = (_Float16)r1 - (_Float16)r2; + pSrc[2 * i3] = (_Float16)t1 + (_Float16)s3; + pSrc[2 * i7] = (_Float16)t1 - (_Float16)s3; + pSrc[2 * i3 + 1] = (_Float16)t2 - (_Float16)r3; + pSrc[2 * i7 + 1] = (_Float16)t2 + (_Float16)r3; + r1 = ((_Float16)r6 - (_Float16)r8) * (_Float16)C81; + r6 = ((_Float16)r6 + (_Float16)r8) * (_Float16)C81; + r2 = ((_Float16)s6 - (_Float16)s8) * (_Float16)C81; + s6 = ((_Float16)s6 + (_Float16)s8) * (_Float16)C81; + t1 = (_Float16)r5 - (_Float16)r1; + r5 = (_Float16)r5 + (_Float16)r1; + r8 = (_Float16)r7 - (_Float16)r6; + r7 = (_Float16)r7 + (_Float16)r6; + t2 = (_Float16)s5 - (_Float16)r2; + s5 = (_Float16)s5 + (_Float16)r2; + s8 = (_Float16)s7 - (_Float16)s6; + s7 = (_Float16)s7 + (_Float16)s6; + pSrc[2 * i2] = (_Float16)r5 + (_Float16)s7; + pSrc[2 * i8] = (_Float16)r5 - (_Float16)s7; + pSrc[2 * i6] = (_Float16)t1 + (_Float16)s8; + pSrc[2 * i4] = (_Float16)t1 - (_Float16)s8; + pSrc[2 * i2 + 1] = (_Float16)s5 - (_Float16)r7; + pSrc[2 * i8 + 1] = (_Float16)s5 + (_Float16)r7; + pSrc[2 * i6 + 1] = (_Float16)t2 - (_Float16)r8; + pSrc[2 * i4 + 1] = (_Float16)t2 + (_Float16)r8; + + i1 += n1; + } while (i1 < fftLen); + + if (n2 < 8) + break; + + ia1 = 0; + j = 1; + + do + { + /* index calculation for the coefficients */ + id = ia1 + twidCoefModifier; + ia1 = id; + ia2 = ia1 + id; + ia3 = ia2 + id; + ia4 = ia3 + id; + ia5 = ia4 + id; + ia6 = ia5 + id; + ia7 = ia6 + id; + + co2 = pCoef[2 * ia1]; + co3 = pCoef[2 * ia2]; + co4 = pCoef[2 * ia3]; + co5 = pCoef[2 * ia4]; + co6 = pCoef[2 * ia5]; + co7 = pCoef[2 * ia6]; + co8 = pCoef[2 * ia7]; + si2 = pCoef[2 * ia1 + 1]; + si3 = pCoef[2 * ia2 + 1]; + si4 = pCoef[2 * ia3 + 1]; + si5 = pCoef[2 * ia4 + 1]; + si6 = pCoef[2 * ia5 + 1]; + si7 = pCoef[2 * ia6 + 1]; + si8 = pCoef[2 * ia7 + 1]; + + i1 = j; + + do + { + /* index calculation for the input */ + i2 = i1 + n2; + i3 = i2 + n2; + i4 = i3 + n2; + i5 = i4 + n2; + i6 = i5 + n2; + i7 = i6 + n2; + i8 = i7 + n2; + r1 = (_Float16)pSrc[2 * i1] + (_Float16)pSrc[2 * i5]; + r5 = (_Float16)pSrc[2 * i1] - (_Float16)pSrc[2 * i5]; + r2 = (_Float16)pSrc[2 * i2] + (_Float16)pSrc[2 * i6]; + r6 = (_Float16)pSrc[2 * i2] - (_Float16)pSrc[2 * i6]; + r3 = (_Float16)pSrc[2 * i3] + (_Float16)pSrc[2 * i7]; + r7 = (_Float16)pSrc[2 * i3] - (_Float16)pSrc[2 * i7]; + r4 = (_Float16)pSrc[2 * i4] + (_Float16)pSrc[2 * i8]; + r8 = (_Float16)pSrc[2 * i4] - (_Float16)pSrc[2 * i8]; + t1 = (_Float16)r1 - (_Float16)r3; + r1 = (_Float16)r1 + (_Float16)r3; + r3 = (_Float16)r2 - (_Float16)r4; + r2 = (_Float16)r2 + (_Float16)r4; + pSrc[2 * i1] = (_Float16)r1 + (_Float16)r2; + r2 = (_Float16)r1 - (_Float16)r2; + s1 = (_Float16)pSrc[2 * i1 + 1] + (_Float16)pSrc[2 * i5 + 1]; + s5 = (_Float16)pSrc[2 * i1 + 1] - (_Float16)pSrc[2 * i5 + 1]; + s2 = (_Float16)pSrc[2 * i2 + 1] + (_Float16)pSrc[2 * i6 + 1]; + s6 = (_Float16)pSrc[2 * i2 + 1] - (_Float16)pSrc[2 * i6 + 1]; + s3 = (_Float16)pSrc[2 * i3 + 1] + (_Float16)pSrc[2 * i7 + 1]; + s7 = (_Float16)pSrc[2 * i3 + 1] - (_Float16)pSrc[2 * i7 + 1]; + s4 = (_Float16)pSrc[2 * i4 + 1] + (_Float16)pSrc[2 * i8 + 1]; + s8 = (_Float16)pSrc[2 * i4 + 1] - (_Float16)pSrc[2 * i8 + 1]; + t2 = (_Float16)s1 - (_Float16)s3; + s1 = (_Float16)s1 + (_Float16)s3; + s3 = (_Float16)s2 - (_Float16)s4; + s2 = (_Float16)s2 + (_Float16)s4; + r1 = (_Float16)t1 + (_Float16)s3; + t1 = (_Float16)t1 - (_Float16)s3; + pSrc[2 * i1 + 1] = (_Float16)s1 + (_Float16)s2; + s2 = (_Float16)s1 - (_Float16)s2; + s1 = (_Float16)t2 - (_Float16)r3; + t2 = (_Float16)t2 + (_Float16)r3; + p1 = (_Float16)co5 * (_Float16)r2; + p2 = (_Float16)si5 * (_Float16)s2; + p3 = (_Float16)co5 * (_Float16)s2; + p4 = (_Float16)si5 * (_Float16)r2; + pSrc[2 * i5] = (_Float16)p1 + (_Float16)p2; + pSrc[2 * i5 + 1] = (_Float16)p3 - (_Float16)p4; + p1 = (_Float16)co3 * (_Float16)r1; + p2 = (_Float16)si3 * (_Float16)s1; + p3 = (_Float16)co3 * (_Float16)s1; + p4 = (_Float16)si3 * (_Float16)r1; + pSrc[2 * i3] = (_Float16)p1 + (_Float16)p2; + pSrc[2 * i3 + 1] = (_Float16)p3 - (_Float16)p4; + p1 = (_Float16)co7 * (_Float16)t1; + p2 = (_Float16)si7 * (_Float16)t2; + p3 = (_Float16)co7 * (_Float16)t2; + p4 = (_Float16)si7 * (_Float16)t1; + pSrc[2 * i7] = (_Float16)p1 + (_Float16)p2; + pSrc[2 * i7 + 1] = (_Float16)p3 - (_Float16)p4; + r1 = ((_Float16)r6 - (_Float16)r8) * (_Float16)C81; + r6 = ((_Float16)r6 + (_Float16)r8) * (_Float16)C81; + s1 = ((_Float16)s6 - (_Float16)s8) * (_Float16)C81; + s6 = ((_Float16)s6 + (_Float16)s8) * (_Float16)C81; + t1 = (_Float16)r5 - (_Float16)r1; + r5 = (_Float16)r5 + (_Float16)r1; + r8 = (_Float16)r7 - (_Float16)r6; + r7 = (_Float16)r7 + (_Float16)r6; + t2 = (_Float16)s5 - (_Float16)s1; + s5 = (_Float16)s5 + (_Float16)s1; + s8 = (_Float16)s7 - (_Float16)s6; + s7 = (_Float16)s7 + (_Float16)s6; + r1 = (_Float16)r5 + (_Float16)s7; + r5 = (_Float16)r5 - (_Float16)s7; + r6 = (_Float16)t1 + (_Float16)s8; + t1 = (_Float16)t1 - (_Float16)s8; + s1 = (_Float16)s5 - (_Float16)r7; + s5 = (_Float16)s5 + (_Float16)r7; + s6 = (_Float16)t2 - (_Float16)r8; + t2 = (_Float16)t2 + (_Float16)r8; + p1 = (_Float16)co2 * (_Float16)r1; + p2 = (_Float16)si2 * (_Float16)s1; + p3 = (_Float16)co2 * (_Float16)s1; + p4 = (_Float16)si2 * (_Float16)r1; + pSrc[2 * i2] = (_Float16)p1 + (_Float16)p2; + pSrc[2 * i2 + 1] = (_Float16)p3 - (_Float16)p4; + p1 = (_Float16)co8 * (_Float16)r5; + p2 = (_Float16)si8 * (_Float16)s5; + p3 = (_Float16)co8 * (_Float16)s5; + p4 = (_Float16)si8 * (_Float16)r5; + pSrc[2 * i8] = (_Float16)p1 + (_Float16)p2; + pSrc[2 * i8 + 1] = (_Float16)p3 - (_Float16)p4; + p1 = (_Float16)co6 * (_Float16)r6; + p2 = (_Float16)si6 * (_Float16)s6; + p3 = (_Float16)co6 * (_Float16)s6; + p4 = (_Float16)si6 * (_Float16)r6; + pSrc[2 * i6] = (_Float16)p1 + (_Float16)p2; + pSrc[2 * i6 + 1] = (_Float16)p3 - (_Float16)p4; + p1 = (_Float16)co4 * (_Float16)t1; + p2 = (_Float16)si4 * (_Float16)t2; + p3 = (_Float16)co4 * (_Float16)t2; + p4 = (_Float16)si4 * (_Float16)t1; + pSrc[2 * i4] = (_Float16)p1 + (_Float16)p2; + pSrc[2 * i4 + 1] = (_Float16)p3 - (_Float16)p4; + + i1 += n1; + } while (i1 < fftLen); + + j++; + } while (j < n2); + + twidCoefModifier <<= 3; + } while (n2 > 7); +} + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c new file mode 100644 index 00000000..7990d479 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c @@ -0,0 +1,285 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix8_f32.c + * Description: Radix-8 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + + +/* ---------------------------------------------------------------------- + * Internal helper function used by the FFTs + * -------------------------------------------------------------------- */ + +/** + brief Core function for the floating-point CFFT butterfly process. + param[in,out] pSrc points to the in-place buffer of floating-point data type. + param[in] fftLen length of the FFT. + param[in] pCoef points to the twiddle coefficient buffer. + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + return none +*/ + +void arm_radix8_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier) +{ + uint32_t ia1, ia2, ia3, ia4, ia5, ia6, ia7; + uint32_t i1, i2, i3, i4, i5, i6, i7, i8; + uint32_t id; + uint32_t n1, n2, j; + + float32_t r1, r2, r3, r4, r5, r6, r7, r8; + float32_t t1, t2; + float32_t s1, s2, s3, s4, s5, s6, s7, s8; + float32_t p1, p2, p3, p4; + float32_t co2, co3, co4, co5, co6, co7, co8; + float32_t si2, si3, si4, si5, si6, si7, si8; + const float32_t C81 = 0.70710678118f; + + n2 = fftLen; + + do + { + n1 = n2; + n2 = n2 >> 3; + i1 = 0; + + do + { + i2 = i1 + n2; + i3 = i2 + n2; + i4 = i3 + n2; + i5 = i4 + n2; + i6 = i5 + n2; + i7 = i6 + n2; + i8 = i7 + n2; + r1 = pSrc[2 * i1] + pSrc[2 * i5]; + r5 = pSrc[2 * i1] - pSrc[2 * i5]; + r2 = pSrc[2 * i2] + pSrc[2 * i6]; + r6 = pSrc[2 * i2] - pSrc[2 * i6]; + r3 = pSrc[2 * i3] + pSrc[2 * i7]; + r7 = pSrc[2 * i3] - pSrc[2 * i7]; + r4 = pSrc[2 * i4] + pSrc[2 * i8]; + r8 = pSrc[2 * i4] - pSrc[2 * i8]; + t1 = r1 - r3; + r1 = r1 + r3; + r3 = r2 - r4; + r2 = r2 + r4; + pSrc[2 * i1] = r1 + r2; + pSrc[2 * i5] = r1 - r2; + r1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1]; + s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1]; + r2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1]; + s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1]; + s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1]; + s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1]; + r4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1]; + s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1]; + t2 = r1 - s3; + r1 = r1 + s3; + s3 = r2 - r4; + r2 = r2 + r4; + pSrc[2 * i1 + 1] = r1 + r2; + pSrc[2 * i5 + 1] = r1 - r2; + pSrc[2 * i3] = t1 + s3; + pSrc[2 * i7] = t1 - s3; + pSrc[2 * i3 + 1] = t2 - r3; + pSrc[2 * i7 + 1] = t2 + r3; + r1 = (r6 - r8) * C81; + r6 = (r6 + r8) * C81; + r2 = (s6 - s8) * C81; + s6 = (s6 + s8) * C81; + t1 = r5 - r1; + r5 = r5 + r1; + r8 = r7 - r6; + r7 = r7 + r6; + t2 = s5 - r2; + s5 = s5 + r2; + s8 = s7 - s6; + s7 = s7 + s6; + pSrc[2 * i2] = r5 + s7; + pSrc[2 * i8] = r5 - s7; + pSrc[2 * i6] = t1 + s8; + pSrc[2 * i4] = t1 - s8; + pSrc[2 * i2 + 1] = s5 - r7; + pSrc[2 * i8 + 1] = s5 + r7; + pSrc[2 * i6 + 1] = t2 - r8; + pSrc[2 * i4 + 1] = t2 + r8; + + i1 += n1; + } while (i1 < fftLen); + + if (n2 < 8) + break; + + ia1 = 0; + j = 1; + + do + { + /* index calculation for the coefficients */ + id = ia1 + twidCoefModifier; + ia1 = id; + ia2 = ia1 + id; + ia3 = ia2 + id; + ia4 = ia3 + id; + ia5 = ia4 + id; + ia6 = ia5 + id; + ia7 = ia6 + id; + + co2 = pCoef[2 * ia1]; + co3 = pCoef[2 * ia2]; + co4 = pCoef[2 * ia3]; + co5 = pCoef[2 * ia4]; + co6 = pCoef[2 * ia5]; + co7 = pCoef[2 * ia6]; + co8 = pCoef[2 * ia7]; + si2 = pCoef[2 * ia1 + 1]; + si3 = pCoef[2 * ia2 + 1]; + si4 = pCoef[2 * ia3 + 1]; + si5 = pCoef[2 * ia4 + 1]; + si6 = pCoef[2 * ia5 + 1]; + si7 = pCoef[2 * ia6 + 1]; + si8 = pCoef[2 * ia7 + 1]; + + i1 = j; + + do + { + /* index calculation for the input */ + i2 = i1 + n2; + i3 = i2 + n2; + i4 = i3 + n2; + i5 = i4 + n2; + i6 = i5 + n2; + i7 = i6 + n2; + i8 = i7 + n2; + r1 = pSrc[2 * i1] + pSrc[2 * i5]; + r5 = pSrc[2 * i1] - pSrc[2 * i5]; + r2 = pSrc[2 * i2] + pSrc[2 * i6]; + r6 = pSrc[2 * i2] - pSrc[2 * i6]; + r3 = pSrc[2 * i3] + pSrc[2 * i7]; + r7 = pSrc[2 * i3] - pSrc[2 * i7]; + r4 = pSrc[2 * i4] + pSrc[2 * i8]; + r8 = pSrc[2 * i4] - pSrc[2 * i8]; + t1 = r1 - r3; + r1 = r1 + r3; + r3 = r2 - r4; + r2 = r2 + r4; + pSrc[2 * i1] = r1 + r2; + r2 = r1 - r2; + s1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1]; + s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1]; + s2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1]; + s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1]; + s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1]; + s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1]; + s4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1]; + s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1]; + t2 = s1 - s3; + s1 = s1 + s3; + s3 = s2 - s4; + s2 = s2 + s4; + r1 = t1 + s3; + t1 = t1 - s3; + pSrc[2 * i1 + 1] = s1 + s2; + s2 = s1 - s2; + s1 = t2 - r3; + t2 = t2 + r3; + p1 = co5 * r2; + p2 = si5 * s2; + p3 = co5 * s2; + p4 = si5 * r2; + pSrc[2 * i5] = p1 + p2; + pSrc[2 * i5 + 1] = p3 - p4; + p1 = co3 * r1; + p2 = si3 * s1; + p3 = co3 * s1; + p4 = si3 * r1; + pSrc[2 * i3] = p1 + p2; + pSrc[2 * i3 + 1] = p3 - p4; + p1 = co7 * t1; + p2 = si7 * t2; + p3 = co7 * t2; + p4 = si7 * t1; + pSrc[2 * i7] = p1 + p2; + pSrc[2 * i7 + 1] = p3 - p4; + r1 = (r6 - r8) * C81; + r6 = (r6 + r8) * C81; + s1 = (s6 - s8) * C81; + s6 = (s6 + s8) * C81; + t1 = r5 - r1; + r5 = r5 + r1; + r8 = r7 - r6; + r7 = r7 + r6; + t2 = s5 - s1; + s5 = s5 + s1; + s8 = s7 - s6; + s7 = s7 + s6; + r1 = r5 + s7; + r5 = r5 - s7; + r6 = t1 + s8; + t1 = t1 - s8; + s1 = s5 - r7; + s5 = s5 + r7; + s6 = t2 - r8; + t2 = t2 + r8; + p1 = co2 * r1; + p2 = si2 * s1; + p3 = co2 * s1; + p4 = si2 * r1; + pSrc[2 * i2] = p1 + p2; + pSrc[2 * i2 + 1] = p3 - p4; + p1 = co8 * r5; + p2 = si8 * s5; + p3 = co8 * s5; + p4 = si8 * r5; + pSrc[2 * i8] = p1 + p2; + pSrc[2 * i8 + 1] = p3 - p4; + p1 = co6 * r6; + p2 = si6 * s6; + p3 = co6 * s6; + p4 = si6 * r6; + pSrc[2 * i6] = p1 + p2; + pSrc[2 * i6 + 1] = p3 - p4; + p1 = co4 * t1; + p2 = si4 * t2; + p3 = co4 * t2; + p4 = si4 * t1; + pSrc[2 * i4] = p1 + p2; + pSrc[2 * i4 + 1] = p3 - p4; + + i1 += n1; + } while (i1 < fftLen); + + j++; + } while (j < n2); + + twidCoefModifier <<= 3; + } while (n2 > 7); +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c new file mode 100644 index 00000000..b9dff3fb --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c @@ -0,0 +1,448 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_f32.c + * Description: Processing function of DCT4 & IDCT4 F32 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +/** + @ingroup groupTransforms + */ + +/** + @defgroup DCT4_IDCT4 DCT Type IV Functions + + Representation of signals by minimum number of values is important for storage and transmission. + The possibility of large discontinuity between the beginning and end of a period of a signal + in DFT can be avoided by extending the signal so that it is even-symmetric. + Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the + spectrum and is very widely used in signal and image coding applications. + The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions. + DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular. + + DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal. + Reordering of the input data makes the computation of DCT just a problem of + computing the DFT of a real signal with a few additional operations. + This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations. + + DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used. + DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing. + DCT2 implementation can be described in the following steps: + - Re-ordering input + - Calculating Real FFT + - Multiplication of weights and Real FFT output and getting real part from the product. + + This process is explained by the block diagram below: + \image html DCT4.gif "Discrete Cosine Transform - type-IV" + + @par Algorithm + The N-point type-IV DCT is defined as a real, linear transformation by the formula: + \image html DCT4Equation.gif + where k = 0, 1, 2, ..., N-1 + @par + Its inverse is defined as follows: + \image html IDCT4Equation.gif + where n = 0, 1, 2, ..., N-1 + @par + The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N). + The symmetry of the transform matrix indicates that the fast algorithms for the forward + and inverse transform computation are identical. + Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both. + + @par Lengths supported by the transform: + As DCT4 internally uses Real FFT, it supports all the lengths 128, 512, 2048 and 8192. + The library provides separate functions for Q15, Q31, and floating-point data types. + + @par Instance Structure + The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure. + A separate instance structure must be defined for each transform. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Initializes Real FFT as its process function is used internally in DCT4, by calling \ref arm_rfft_init_f32(). + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Manually initialize the instance structure as follows: +
+      arm_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+      arm_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+      arm_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+  
+ where \c N is the length of the DCT4; \c Nby2 is half of the length of the DCT4; + \c normalize is normalizing factor used and is equal to sqrt(2/N); + \c pTwiddle points to the twiddle factor table; + \c pCosFactor points to the cosFactor table; + \c pRfft points to the real FFT instance; + \c pCfft points to the complex FFT instance; + The CFFT and RFFT structures also needs to be initialized, refer to arm_cfft_radix4_f32() + and arm_rfft_f32() respectively for details regarding static initialization. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the DCT4 transform functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + + /** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Processing function for the floating-point DCT4/IDCT4. + @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure + @param[in] pState points to state buffer + @param[in,out] pInlineBuffer points to the in-place input and output buffer + @return none + */ + +void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer) +{ + const float32_t *weights = S->pTwiddle; /* Pointer to the Weights table */ + const float32_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */ + float32_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */ + float32_t in; /* Temporary variable */ + uint32_t i; /* Loop counter */ + + + /* DCT4 computation involves DCT2 (which is calculated using RFFT) + * along with some pre-processing and post-processing. + * Computational procedure is explained as follows: + * (a) Pre-processing involves multiplying input with cos factor, + * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n)) + * where, + * r(n) -- output of preprocessing + * u(n) -- input to preprocessing(actual Source buffer) + * (b) Calculation of DCT2 using FFT is divided into three steps: + * Step1: Re-ordering of even and odd elements of input. + * Step2: Calculating FFT of the re-ordered input. + * Step3: Taking the real part of the product of FFT output and weights. + * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation: + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * where, + * Y4 -- DCT4 output, Y2 -- DCT2 output + * (d) Multiplying the output with the normalizing factor sqrt(2/N). + */ + + /*-------- Pre-processing ------------*/ + /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */ + arm_scale_f32(pInlineBuffer, 2.0f, pInlineBuffer, S->N); + arm_mult_f32(pInlineBuffer, cosFact, pInlineBuffer, S->N); + + /* ---------------------------------------------------------------- + * Step1: Re-ordering of even and odd elements as + * pState[i] = pInlineBuffer[2*i] and + * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2 + ---------------------------------------------------------------------*/ + + /* pS1 initialized to pState */ + pS1 = pState; + + /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */ + pS2 = pState + (S->N - 1U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */ + i = S->Nby2 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. + * Compute 4 outputs at a time */ + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_f32 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_f32 (pState, weights, pState, S->N); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */ + i = (S->N - 1U) >> 2U; + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ * (float32_t) 0.5; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + /* points to the next real value */ + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + i = (S->N - 1U) % 0x4U; + + while (i > 0U) + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement the loop counter */ + i--; + } + + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* pbuff initialized to the pInlineBuffer(now contains the output values) */ + pbuff = pInlineBuffer; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */ + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = in * S->normalize; + + in = *pbuff; + *pbuff++ = in * S->normalize; + + in = *pbuff; + *pbuff++ = in * S->normalize; + + in = *pbuff; + *pbuff++ = in * S->normalize; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + +#else + + /* Initializing the loop counter to N/2 */ + i = S->Nby2; + + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter */ + i = S->N; + + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_f32 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_f32 (pState, weights, pState, S->N); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ * (float32_t) 0.5; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* Initializing the loop counter */ + i = (S->N - 1U); + + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing loop counter */ + i = S->N; + + /* pbuff initialized to the pInlineBuffer (now contains the output values) */ + pbuff = pInlineBuffer; + + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = in * S->normalize; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c new file mode 100644 index 00000000..e1d80c0e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c @@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_init_f32.c + * Description: Initialization function of DCT-4 & IDCT4 F32 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + + /** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Initialization function for the floating-point DCT4/IDCT4. + @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure + @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure + @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure + @param[in] N length of the DCT4 + @param[in] Nby2 half of the length of the DCT4 + @param[in] normalize normalizing factor. + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : N is not a supported transform length + + @par Normalizing factor + The normalizing factor is sqrt(2/N), which depends on the size of transform N. + Floating-point normalizing factors are mentioned in the table below for different DCT sizes: + + \image html dct4NormalizingF32Table.gif + */ + +arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize) +{ + /* Initialize the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + + /* Initialize the DCT4 length */ + S->N = N; + + /* Initialize the half of DCT4 length */ + S->Nby2 = Nby2; + + /* Initialize the DCT4 Normalizing factor */ + S->normalize = normalize; + + /* Initialize Real FFT Instance */ + S->pRfft = S_RFFT; + + /* Initialize Complex FFT Instance */ + S->pCfft = S_CFFT; + + switch (N) + { + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192) + /* Initialize the table modifier values */ + case 8192U: + S->pTwiddle = Weights_8192; + S->pCosFactor = cos_factors_8192; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048) + case 2048U: + S->pTwiddle = Weights_2048; + S->pCosFactor = cos_factors_2048; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512) + case 512U: + S->pTwiddle = Weights_512; + S->pCosFactor = cos_factors_512; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128) + case 128U: + S->pTwiddle = Weights_128; + S->pCosFactor = cos_factors_128; + break; + #endif + default: + status = ARM_MATH_ARGUMENT_ERROR; + } + + /* Initialize the RFFT/RIFFT Function */ + arm_rfft_init_f32(S->pRfft, S->pCfft, S->N, 0U, 1U); + + /* return the status of DCT4 Init function */ + return (status); +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c new file mode 100644 index 00000000..5390da3c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c @@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_init_q15.c + * Description: Initialization function of DCT-4 & IDCT4 Q15 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + + /** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Initialization function for the Q15 DCT4/IDCT4. + @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure + @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure + @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure + @param[in] N length of the DCT4 + @param[in] Nby2 half of the length of the DCT4 + @param[in] normalize normalizing factor + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : N is not a supported transform length + + @par Normalizing factor + The normalizing factor is sqrt(2/N), which depends on the size of transform N. + Normalizing factors in 1.15 format are mentioned in the table below for different DCT sizes: + + \image html dct4NormalizingQ15Table.gif + */ + +arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialize the DCT4 length */ + S->N = N; + + /* Initialize the half of DCT4 length */ + S->Nby2 = Nby2; + + /* Initialize the DCT4 Normalizing factor */ + S->normalize = normalize; + + /* Initialize Real FFT Instance */ + S->pRfft = S_RFFT; + + /* Initialize Complex FFT Instance */ + S->pCfft = S_CFFT; + + switch (N) + { + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192) + /* Initialize the table modifier values */ + case 8192U: + S->pTwiddle = WeightsQ15_8192; + S->pCosFactor = cos_factorsQ15_8192; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048) + case 2048U: + S->pTwiddle = WeightsQ15_2048; + S->pCosFactor = cos_factorsQ15_2048; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512) + case 512U: + S->pTwiddle = WeightsQ15_512; + S->pCosFactor = cos_factorsQ15_512; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128) + case 128U: + S->pTwiddle = WeightsQ15_128; + S->pCosFactor = cos_factorsQ15_128; + break; + #endif + + default: + status = ARM_MATH_ARGUMENT_ERROR; + } + + /* Initialize the RFFT/RIFFT */ + arm_rfft_init_q15(S->pRfft, S->N, 0U, 1U); + + /* return the status of DCT4 Init function */ + return (status); +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c new file mode 100644 index 00000000..4c7622a1 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c @@ -0,0 +1,129 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_init_q31.c + * Description: Initialization function of DCT-4 & IDCT4 Q31 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + + /** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Initialization function for the Q31 DCT4/IDCT4. + @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + @param[in] N length of the DCT4. + @param[in] Nby2 half of the length of the DCT4. + @param[in] normalize normalizing factor. + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : N is not a supported transform length + + @par Normalizing factor: + The normalizing factor is sqrt(2/N), which depends on the size of transform N. + Normalizing factors in 1.31 format are mentioned in the table below for different DCT sizes: + + \image html dct4NormalizingQ31Table.gif + */ + +arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize) +{ + /* Initialize the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialize the DCT4 length */ + S->N = N; + + /* Initialize the half of DCT4 length */ + S->Nby2 = Nby2; + + /* Initialize the DCT4 Normalizing factor */ + S->normalize = normalize; + + /* Initialize Real FFT Instance */ + S->pRfft = S_RFFT; + + /* Initialize Complex FFT Instance */ + S->pCfft = S_CFFT; + + switch (N) + { + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192) + /* Initialize the table modifier values */ + case 8192U: + S->pTwiddle = WeightsQ31_8192; + S->pCosFactor = cos_factorsQ31_8192; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048) + case 2048U: + S->pTwiddle = WeightsQ31_2048; + S->pCosFactor = cos_factorsQ31_2048; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512) + case 512U: + S->pTwiddle = WeightsQ31_512; + S->pCosFactor = cos_factorsQ31_512; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128) + case 128U: + S->pTwiddle = WeightsQ31_128; + S->pCosFactor = cos_factorsQ31_128; + break; + #endif + default: + status = ARM_MATH_ARGUMENT_ERROR; + } + + /* Initialize the RFFT/RIFFT Function */ + arm_rfft_init_q31(S->pRfft, S->N, 0U, 1U); + + /* return the status of DCT4 Init function */ + return (status); +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c new file mode 100644 index 00000000..a4650da2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c @@ -0,0 +1,381 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_q15.c + * Description: Processing function of DCT4 & IDCT4 Q15 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +/** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Processing function for the Q15 DCT4/IDCT4. + @param[in] S points to an instance of the Q15 DCT4 structure. + @param[in] pState points to state buffer. + @param[in,out] pInlineBuffer points to the in-place input and output buffer. + @return none + + @par Input an output formats + Internally inputs are downscaled in the RFFT process function to avoid overflows. + Number of bits downscaled, depends on the size of the transform. The input and output + formats for different DCT sizes and number of bits to upscale are mentioned in the table below: + + \image html dct4FormatsQ15Table.gif + */ + +void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer) +{ + const q15_t *weights = S->pTwiddle; /* Pointer to the Weights table */ + const q15_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */ + q15_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */ + q15_t in; /* Temporary variable */ + uint32_t i; /* Loop counter */ + + + /* DCT4 computation involves DCT2 (which is calculated using RFFT) + * along with some pre-processing and post-processing. + * Computational procedure is explained as follows: + * (a) Pre-processing involves multiplying input with cos factor, + * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n)) + * where, + * r(n) -- output of preprocessing + * u(n) -- input to preprocessing(actual Source buffer) + * (b) Calculation of DCT2 using FFT is divided into three steps: + * Step1: Re-ordering of even and odd elements of input. + * Step2: Calculating FFT of the re-ordered input. + * Step3: Taking the real part of the product of FFT output and weights. + * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation: + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * where, + * Y4 -- DCT4 output, Y2 -- DCT2 output + * (d) Multiplying the output with the normalizing factor sqrt(2/N). + */ + + /*-------- Pre-processing ------------*/ + /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */ + arm_mult_q15 (pInlineBuffer, cosFact, pInlineBuffer, S->N); + arm_shift_q15 (pInlineBuffer, 1, pInlineBuffer, S->N); + + /* ---------------------------------------------------------------- + * Step1: Re-ordering of even and odd elements as + * pState[i] = pInlineBuffer[2*i] and + * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2 + ---------------------------------------------------------------------*/ + + /* pS1 initialized to pState */ + pS1 = pState; + + /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */ + pS2 = pState + (S->N - 1U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */ + i = S->Nby2 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. + * Compute 4 outputs at a time */ + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_q15 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_q15 (pState, weights, pState, S->N); + + /* The output of complex multiplication is in 3.13 format. + * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */ + arm_shift_q15 (pState, 2, pState, S->N * 2); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */ + i = (S->N - 1U) >> 2U; + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ >> 1U; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + /* points to the next real value */ + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + i = (S->N - 1U) % 0x4U; + + while (i > 0U) + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } + + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* pbuff initialized to the pInlineBuffer(now contains the output values) */ + pbuff = pInlineBuffer; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */ + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + +#else + + /* Initializing the loop counter to N/2 */ + i = S->Nby2; + + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter */ + i = S->N; + + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_q15 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_q15 (pState, weights, pState, S->N); + + /* The output of complex multiplication is in 3.13 format. + * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */ + arm_shift_q15 (pState, 2, pState, S->N * 2); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ >> 1U; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* Initializing the loop counter */ + i = (S->N - 1U); + + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing loop counter */ + i = S->N; + + /* pbuff initialized to the pInlineBuffer (now contains the output values) */ + pbuff = pInlineBuffer; + + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + /* Decrement loop counter */ + i--; + + } while (i > 0U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c new file mode 100644 index 00000000..6cbccff8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c @@ -0,0 +1,383 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_q31.c + * Description: Processing function of DCT4 & IDCT4 Q31 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +/** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Processing function for the Q31 DCT4/IDCT4. + @param[in] S points to an instance of the Q31 DCT4 structure. + @param[in] pState points to state buffer. + @param[in,out] pInlineBuffer points to the in-place input and output buffer. + @return none + + @par Input an output formats + Input samples need to be downscaled by 1 bit to avoid saturations in the Q31 DCT process, + as the conversion from DCT2 to DCT4 involves one subtraction. + Internally inputs are downscaled in the RFFT process function to avoid overflows. + Number of bits downscaled, depends on the size of the transform. + The input and output formats for different DCT sizes and number of bits to upscale are + mentioned in the table below: + + \image html dct4FormatsQ31Table.gif + */ + +void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer) +{ + const q31_t *weights = S->pTwiddle; /* Pointer to the Weights table */ + const q31_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */ + q31_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */ + q31_t in; /* Temporary variable */ + uint32_t i; /* Loop counter */ + + + /* DCT4 computation involves DCT2 (which is calculated using RFFT) + * along with some pre-processing and post-processing. + * Computational procedure is explained as follows: + * (a) Pre-processing involves multiplying input with cos factor, + * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n)) + * where, + * r(n) -- output of preprocessing + * u(n) -- input to preprocessing(actual Source buffer) + * (b) Calculation of DCT2 using FFT is divided into three steps: + * Step1: Re-ordering of even and odd elements of input. + * Step2: Calculating FFT of the re-ordered input. + * Step3: Taking the real part of the product of FFT output and weights. + * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation: + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * where, + * Y4 -- DCT4 output, Y2 -- DCT2 output + * (d) Multiplying the output with the normalizing factor sqrt(2/N). + */ + + /*-------- Pre-processing ------------*/ + /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */ + arm_mult_q31 (pInlineBuffer, cosFact, pInlineBuffer, S->N); + arm_shift_q31 (pInlineBuffer, 1, pInlineBuffer, S->N); + + /* ---------------------------------------------------------------- + * Step1: Re-ordering of even and odd elements as + * pState[i] = pInlineBuffer[2*i] and + * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2 + ---------------------------------------------------------------------*/ + + /* pS1 initialized to pState */ + pS1 = pState; + + /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */ + pS2 = pState + (S->N - 1U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */ + i = S->Nby2 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. + * Compute 4 outputs at a time */ + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_q31 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_q31 (pState, weights, pState, S->N); + + /* The output of complex multiplication is in 3.29 format. + * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */ + arm_shift_q31 (pState, 2, pState, S->N * 2); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */ + i = (S->N - 1U) >> 2U; + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ >> 1U; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + /* points to the next real value */ + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + i = (S->N - 1U) % 0x4U; + + while (i > 0U) + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } + + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* pbuff initialized to the pInlineBuffer(now contains the output values) */ + pbuff = pInlineBuffer; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */ + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + +#else + + /* Initializing the loop counter to N/2 */ + i = S->Nby2; + + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter */ + i = S->N; + + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_q31 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_q31 (pState, weights, pState, S->N); + + /* The output of complex multiplication is in 3.29 format. + * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */ + arm_shift_q31(pState, 2, pState, S->N * 2); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ >> 1U; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* Initializing the loop counter */ + i = (S->N - 1U); + + while (i > 0U) + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing loop counter */ + i = S->N; + + /* pbuff initialized to the pInlineBuffer (now contains the output values) */ + pbuff = pInlineBuffer; + + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + /* Decrement loop counter */ + i--; + } while (i > 0U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_f16.c new file mode 100644 index 00000000..4ec6cd99 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_f16.c @@ -0,0 +1,161 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_f16.c + * Description: MFCC function for the f16 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include "dsp/transform_functions_f16.h" +#include "dsp/statistics_functions_f16.h" +#include "dsp/basic_math_functions_f16.h" +#include "dsp/complex_math_functions_f16.h" +#include "dsp/fast_math_functions_f16.h" +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupTransforms + */ + + +/** + @defgroup MFCC MFCC + + MFCC Transform + + There are separate functions for floating-point, Q15, and Q31 data types. + */ + + + +/** + @addtogroup MFCC + @{ + */ + +/** + @brief MFCC F16 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples + @param[out] pDst points to the output MFCC values + @param[inout] pTmp points to a temporary buffer of complex + + @return none + + @par Description + The number of input samples if the FFT length used + when initializing the instance data structure. + + The temporary buffer has a 2*fft length size when MFCC + is implemented with CFFT. + It has length FFT Length + 2 when implemented with RFFT + (default implementation). + + The source buffer is modified by this function. + + */ +void arm_mfcc_f16( + const arm_mfcc_instance_f16 * S, + float16_t *pSrc, + float16_t *pDst, + float16_t *pTmp + ) +{ + float16_t maxValue; + uint32_t index; + uint32_t i; + float16_t result; + const float16_t *coefs=S->filterCoefs; + arm_matrix_instance_f16 pDctMat; + + /* Normalize */ + arm_absmax_f16(pSrc,S->fftLen,&maxValue,&index); + + arm_scale_f16(pSrc,1.0f16/(_Float16)maxValue,pSrc,S->fftLen); + + /* Multiply by window */ + arm_mult_f16(pSrc,S->windowCoefs,pSrc,S->fftLen); + + /* Compute spectrum magnitude + */ +#if defined(ARM_MFCC_CFFT_BASED) + /* some HW accelerator for CMSIS-DSP used in some boards + are only providing acceleration for CFFT. + With ARM_MFCC_CFFT_BASED enabled, CFFT is used and the MFCC + will be accelerated on those boards. + + The default is to use RFFT + */ + /* Convert from real to complex */ + for(i=0; i < S->fftLen ; i++) + { + pTmp[2*i] = pSrc[i]; + pTmp[2*i+1] = 0.0f16; + } + arm_cfft_f16(&(S->cfft),pTmp,0,1); +#else + /* Default RFFT based implementation */ + arm_rfft_fast_f16(&(S->rfft),pSrc,pTmp,0); + /* Unpack real values */ + pTmp[S->fftLen]=pTmp[1]; + pTmp[S->fftLen+1]=0.0f16; + pTmp[1]=0.0f; +#endif + arm_cmplx_mag_f16(pTmp,pSrc,S->fftLen); + + /* Apply MEL filters */ + for(i=0; inbMelFilters; i++) + { + arm_dot_prod_f16(pSrc+S->filterPos[i], + coefs, + S->filterLengths[i], + &result); + + coefs += S->filterLengths[i]; + + pTmp[i] = result; + + } + + /* Compute the log */ + arm_offset_f16(pTmp,1.0e-4f16,pTmp,S->nbMelFilters); + arm_vlog_f16(pTmp,pTmp,S->nbMelFilters); + + /* Multiply with the DCT matrix */ + + pDctMat.numRows=S->nbDctOutputs; + pDctMat.numCols=S->nbMelFilters; + pDctMat.pData=(float16_t*)S->dctCoefs; + + arm_mat_vec_mult_f16(&pDctMat, pTmp, pDst); + + +} + +#endif /* defined(ARM_FLOAT16_SUPPORTED) */ +/** + @} end of MFCC group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_f32.c new file mode 100644 index 00000000..5ac94588 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_f32.c @@ -0,0 +1,159 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_f32.c + * Description: MFCC function for the f32 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + + +#include "dsp/transform_functions.h" +#include "dsp/statistics_functions.h" +#include "dsp/basic_math_functions.h" +#include "dsp/complex_math_functions.h" +#include "dsp/fast_math_functions.h" +#include "dsp/matrix_functions.h" + +/** + @ingroup groupTransforms + */ + + +/** + @defgroup MFCC MFCC + + MFCC Transform + + There are separate functions for floating-point, Q15, and Q31 data types. + */ + + + +/** + @addtogroup MFCC + @{ + */ + +/** + @brief MFCC F32 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples + @param[out] pDst points to the output MFCC values + @param[inout] pTmp points to a temporary buffer of complex + + @return none + + @par Description + The number of input samples if the FFT length used + when initializing the instance data structure. + + The temporary buffer has a 2*fft length size when MFCC + is implemented with CFFT. + It has length FFT Length + 2 when implemented with RFFT + (default implementation). + + The source buffer is modified by this function. + + */ +void arm_mfcc_f32( + const arm_mfcc_instance_f32 * S, + float32_t *pSrc, + float32_t *pDst, + float32_t *pTmp + ) +{ + float32_t maxValue; + uint32_t index; + uint32_t i; + float32_t result; + const float32_t *coefs=S->filterCoefs; + arm_matrix_instance_f32 pDctMat; + + /* Normalize */ + arm_absmax_f32(pSrc,S->fftLen,&maxValue,&index); + + arm_scale_f32(pSrc,1.0f/maxValue,pSrc,S->fftLen); + + /* Multiply by window */ + arm_mult_f32(pSrc,S->windowCoefs,pSrc,S->fftLen); + + /* Compute spectrum magnitude + */ +#if defined(ARM_MFCC_CFFT_BASED) + /* some HW accelerator for CMSIS-DSP used in some boards + are only providing acceleration for CFFT. + With ARM_MFCC_CFFT_BASED enabled, CFFT is used and the MFCC + will be accelerated on those boards. + + The default is to use RFFT + */ + /* Convert from real to complex */ + for(i=0; i < S->fftLen ; i++) + { + pTmp[2*i] = pSrc[i]; + pTmp[2*i+1] = 0.0f; + } + arm_cfft_f32(&(S->cfft),pTmp,0,1); +#else + /* Default RFFT based implementation */ + arm_rfft_fast_f32(&(S->rfft),pSrc,pTmp,0); + /* Unpack real values */ + pTmp[S->fftLen]=pTmp[1]; + pTmp[S->fftLen+1]=0.0f; + pTmp[1]=0.0f; +#endif + arm_cmplx_mag_f32(pTmp,pSrc,S->fftLen); + + /* Apply MEL filters */ + for(i=0; inbMelFilters; i++) + { + arm_dot_prod_f32(pSrc+S->filterPos[i], + coefs, + S->filterLengths[i], + &result); + + coefs += S->filterLengths[i]; + + pTmp[i] = result; + + } + + /* Compute the log */ + arm_offset_f32(pTmp,1.0e-6f,pTmp,S->nbMelFilters); + arm_vlog_f32(pTmp,pTmp,S->nbMelFilters); + + /* Multiply with the DCT matrix */ + + pDctMat.numRows=S->nbDctOutputs; + pDctMat.numCols=S->nbMelFilters; + pDctMat.pData=(float32_t*)S->dctCoefs; + + arm_mat_vec_mult_f32(&pDctMat, pTmp, pDst); + + +} + +/** + @} end of MFCC group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_f16.c new file mode 100644 index 00000000..d90fd0dc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_f16.c @@ -0,0 +1,110 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_init_f16.c + * Description: MFCC initialization function for the f16 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + @ingroup groupTransforms + */ + + +/** + @addtogroup MFCC + @{ + */ + + +#include "dsp/transform_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + + +/** + @brief Initialization of the MFCC F16 instance structure + @param[out] S points to the mfcc instance structure + @param[in] fftLen fft length + @param[in] nbMelFilters number of Mel filters + @param[in] nbDctOutputs number of Dct outputs + @param[in] dctCoefs points to an array of DCT coefficients + @param[in] filterPos points of the array of filter positions + @param[in] filterLengths points to the array of filter lengths + @param[in] filterCoefs points to the array of filter coefficients + @param[in] windowCoefs points to the array of window coefficients + + @return error status + + @par Description + The matrix of Mel filter coefficients is sparse. + Most of the coefficients are zero. + To avoid multiplying the spectrogram by those zeros, the + filter is applied only to a given position in the spectrogram + and on a given number of FFT bins (the filter length). + It is the reason for the arrays filterPos and filterLengths. + + window coefficients can describe (for instance) a Hamming window. + The array has the same size as the FFT length. + + The folder Scripts is containing a Python script which can be used + to generate the filter, dct and window arrays. + */ + +arm_status arm_mfcc_init_f16( + arm_mfcc_instance_f16 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const float16_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const float16_t *filterCoefs, + const float16_t *windowCoefs + ) +{ + arm_status status; + + S->fftLen=fftLen; + S->nbMelFilters=nbMelFilters; + S->nbDctOutputs=nbDctOutputs; + S->dctCoefs=dctCoefs; + S->filterPos=filterPos; + S->filterLengths=filterLengths; + S->filterCoefs=filterCoefs; + S->windowCoefs=windowCoefs; + + #if defined(ARM_MFCC_CFFT_BASED) + status=arm_cfft_init_f16(&(S->cfft),fftLen); + #else + status=arm_rfft_fast_init_f16(&(S->rfft),fftLen); + #endif + + return(status); +} + +#endif /* defined(ARM_FLOAT16_SUPPORTED) */ +/** + @} end of MFCC group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_f32.c new file mode 100644 index 00000000..0690782e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_f32.c @@ -0,0 +1,107 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_init_f32.c + * Description: MFCC initialization function for the f32 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + @ingroup groupTransforms + */ + + +/** + @addtogroup MFCC + @{ + */ + + +#include "dsp/transform_functions.h" + + + +/** + @brief Initialization of the MFCC F32 instance structure + @param[out] S points to the mfcc instance structure + @param[in] fftLen fft length + @param[in] nbMelFilters number of Mel filters + @param[in] nbDctOutputs number of Dct outputs + @param[in] dctCoefs points to an array of DCT coefficients + @param[in] filterPos points of the array of filter positions + @param[in] filterLengths points to the array of filter lengths + @param[in] filterCoefs points to the array of filter coefficients + @param[in] windowCoefs points to the array of window coefficients + + @return error status + + @par Description + The matrix of Mel filter coefficients is sparse. + Most of the coefficients are zero. + To avoid multiplying the spectrogram by those zeros, the + filter is applied only to a given position in the spectrogram + and on a given number of FFT bins (the filter length). + It is the reason for the arrays filterPos and filterLengths. + + window coefficients can describe (for instance) a Hamming window. + The array has the same size as the FFT length. + + The folder Scripts is containing a Python script which can be used + to generate the filter, dct and window arrays. + */ + +arm_status arm_mfcc_init_f32( + arm_mfcc_instance_f32 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const float32_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const float32_t *filterCoefs, + const float32_t *windowCoefs + ) +{ + arm_status status; + + S->fftLen=fftLen; + S->nbMelFilters=nbMelFilters; + S->nbDctOutputs=nbDctOutputs; + S->dctCoefs=dctCoefs; + S->filterPos=filterPos; + S->filterLengths=filterLengths; + S->filterCoefs=filterCoefs; + S->windowCoefs=windowCoefs; + + #if defined(ARM_MFCC_CFFT_BASED) + status=arm_cfft_init_f32(&(S->cfft),fftLen); + #else + status=arm_rfft_fast_init_f32(&(S->rfft),fftLen); + #endif + + return(status); +} + +/** + @} end of MFCC group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_q15.c new file mode 100644 index 00000000..60ff9f23 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_q15.c @@ -0,0 +1,107 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_init_q15.c + * Description: MFCC initialization function for the q15 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + @ingroup groupTransforms + */ + + +/** + @addtogroup MFCC + @{ + */ + + +#include "dsp/transform_functions.h" + + + +/** + @brief Initialization of the MFCC F32 instance structure + @param[out] S points to the mfcc instance structure + @param[in] fftLen fft length + @param[in] nbMelFilters number of Mel filters + @param[in] nbDctOutputs number of Dct outputs + @param[in] dctCoefs points to an array of DCT coefficients + @param[in] filterPos points of the array of filter positions + @param[in] filterLengths points to the array of filter lengths + @param[in] filterCoefs points to the array of filter coefficients + @param[in] windowCoefs points to the array of window coefficients + + @return error status + + @par Description + The matrix of Mel filter coefficients is sparse. + Most of the coefficients are zero. + To avoid multiplying the spectrogram by those zeros, the + filter is applied only to a given position in the spectrogram + and on a given number of FFT bins (the filter length). + It is the reason for the arrays filterPos and filterLengths. + + window coefficients can describe (for instance) a Hamming window. + The array has the same size as the FFT length. + + The folder Scripts is containing a Python script which can be used + to generate the filter, dct and window arrays. + */ + +arm_status arm_mfcc_init_q15( + arm_mfcc_instance_q15 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const q15_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const q15_t *filterCoefs, + const q15_t *windowCoefs + ) +{ + arm_status status; + + S->fftLen=fftLen; + S->nbMelFilters=nbMelFilters; + S->nbDctOutputs=nbDctOutputs; + S->dctCoefs=dctCoefs; + S->filterPos=filterPos; + S->filterLengths=filterLengths; + S->filterCoefs=filterCoefs; + S->windowCoefs=windowCoefs; + + #if defined(ARM_MFCC_CFFT_BASED) + status=arm_cfft_init_q15(&(S->cfft),fftLen); + #else + status=arm_rfft_init_q15(&(S->rfft),fftLen,0,1); + #endif + + return(status); +} + +/** + @} end of MFCC group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_q31.c new file mode 100644 index 00000000..ce3d9dc0 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_q31.c @@ -0,0 +1,107 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_init_q31.c + * Description: MFCC initialization function for the q31 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + @ingroup groupTransforms + */ + + +/** + @addtogroup MFCC + @{ + */ + + +#include "dsp/transform_functions.h" + + + +/** + @brief Initialization of the MFCC F32 instance structure + @param[out] S points to the mfcc instance structure + @param[in] fftLen fft length + @param[in] nbMelFilters number of Mel filters + @param[in] nbDctOutputs number of Dct outputs + @param[in] dctCoefs points to an array of DCT coefficients + @param[in] filterPos points of the array of filter positions + @param[in] filterLengths points to the array of filter lengths + @param[in] filterCoefs points to the array of filter coefficients + @param[in] windowCoefs points to the array of window coefficients + + @return error status + + @par Description + The matrix of Mel filter coefficients is sparse. + Most of the coefficients are zero. + To avoid multiplying the spectrogram by those zeros, the + filter is applied only to a given position in the spectrogram + and on a given number of FFT bins (the filter length). + It is the reason for the arrays filterPos and filterLengths. + + window coefficients can describe (for instance) a Hamming window. + The array has the same size as the FFT length. + + The folder Scripts is containing a Python script which can be used + to generate the filter, dct and window arrays. + */ + +arm_status arm_mfcc_init_q31( + arm_mfcc_instance_q31 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const q31_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const q31_t *filterCoefs, + const q31_t *windowCoefs + ) +{ + arm_status status; + + S->fftLen=fftLen; + S->nbMelFilters=nbMelFilters; + S->nbDctOutputs=nbDctOutputs; + S->dctCoefs=dctCoefs; + S->filterPos=filterPos; + S->filterLengths=filterLengths; + S->filterCoefs=filterCoefs; + S->windowCoefs=windowCoefs; + + #if defined(ARM_MFCC_CFFT_BASED) + status=arm_cfft_init_q31(&(S->cfft),fftLen); + #else + status=arm_rfft_init_q31(&(S->rfft),fftLen,0,1); + #endif + + return(status); +} + +/** + @} end of MFCC group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_q15.c new file mode 100644 index 00000000..417cf9ee --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_q15.c @@ -0,0 +1,208 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_q15.c + * Description: MFCC function for the q15 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + + +#include "dsp/transform_functions.h" +#include "dsp/statistics_functions.h" +#include "dsp/basic_math_functions.h" +#include "dsp/complex_math_functions.h" +#include "dsp/fast_math_functions.h" +#include "dsp/matrix_functions.h" + +/* Constants for Q15 implementation */ +#define LOG2TOLOG_Q15 0x02C5C860 +#define MICRO_Q15 0x00000219 +#define SHIFT_MELFILTER_SATURATION_Q15 10 +/** + @ingroup groupTransforms + */ + + +/** + @defgroup MFCC MFCC + + MFCC Transform + + There are separate functions for floating-point, Q15, and Q15 data types. + */ + + + +/** + @addtogroup MFCC + @{ + */ + +/** + @brief MFCC Q15 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples in Q15 + @param[out] pDst points to the output MFCC values in q8.7 format + @param[inout] pTmp points to a temporary buffer of complex + + @return none + + @par Description + The number of input samples is the FFT length used + when initializing the instance data structure. + + The temporary buffer has a 2*fft length. + + The source buffer is modified by this function. + + The function may saturate. If the FFT length is too + big and the number of MEL filters too small then the fixed + point computations may saturate. + + */ + +arm_status arm_mfcc_q15( + const arm_mfcc_instance_q15 * S, + q15_t *pSrc, + q15_t *pDst, + q31_t *pTmp + ) +{ + q15_t m; + uint32_t index; + uint32_t fftShift=0; + q31_t logExponent; + q63_t result; + arm_matrix_instance_q15 pDctMat; + uint32_t i; + uint32_t coefsPos; + uint32_t filterLimit; + q15_t *pTmp2=(q15_t*)pTmp; + + arm_status status = ARM_MATH_SUCCESS; + + // q15 + arm_absmax_q15(pSrc,S->fftLen,&m,&index); + + if (m !=0) + { + q15_t quotient; + int16_t shift; + + status = arm_divide_q15(0x7FFF,m,"ient,&shift); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + + arm_scale_q15(pSrc,quotient,shift,pSrc,S->fftLen); + } + + + // q15 + arm_mult_q15(pSrc,S->windowCoefs, pSrc, S->fftLen); + + + /* Compute spectrum magnitude + */ + fftShift = 31 - __CLZ(S->fftLen); +#if defined(ARM_MFCC_CFFT_BASED) + /* some HW accelerator for CMSIS-DSP used in some boards + are only providing acceleration for CFFT. + With ARM_MFCC_CFFT_BASED enabled, CFFT is used and the MFCC + will be accelerated on those boards. + + The default is to use RFFT + */ + /* Convert from real to complex */ + for(i=0; i < S->fftLen ; i++) + { + pTmp2[2*i] = pSrc[i]; + pTmp2[2*i+1] = 0; + } + arm_cfft_q15(&(S->cfft),pTmp2,0,1); +#else + /* Default RFFT based implementation */ + arm_rfft_q15(&(S->rfft),pSrc,pTmp2); +#endif + filterLimit = 1 + (S->fftLen >> 1); + + + // q15 - fftShift + arm_cmplx_mag_q15(pTmp2,pSrc,filterLimit); + // q14 - fftShift + + /* Apply MEL filters */ + coefsPos = 0; + for(i=0; inbMelFilters; i++) + { + arm_dot_prod_q15(pSrc+S->filterPos[i], + &(S->filterCoefs[coefsPos]), + S->filterLengths[i], + &result); + + coefsPos += S->filterLengths[i]; + + // q34.29 - fftShift + result += MICRO_Q15; + result >>= SHIFT_MELFILTER_SATURATION_Q15; + // q34.29 - fftShift - satShift + pTmp[i] = __SSAT(result,31) ; + + } + + + // q34.29 - fftShift - satShift + /* Compute the log */ + arm_vlog_q31(pTmp,pTmp,S->nbMelFilters); + + + // q5.26 + + logExponent = fftShift + 2 + SHIFT_MELFILTER_SATURATION_Q15; + logExponent = logExponent * LOG2TOLOG_Q15; + + + // q8.26 + arm_offset_q31(pTmp,logExponent,pTmp,S->nbMelFilters); + arm_shift_q31(pTmp,-19,pTmp,S->nbMelFilters); + for(i=0; inbMelFilters; i++) + { + pSrc[i] = __SSAT((q15_t)pTmp[i],16); + } + + // q8.7 + + pDctMat.numRows=S->nbDctOutputs; + pDctMat.numCols=S->nbMelFilters; + pDctMat.pData=(q15_t*)S->dctCoefs; + + arm_mat_vec_mult_q15(&pDctMat, pSrc, pDst); + + return(status); +} + +/** + @} end of MFCC group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_q31.c new file mode 100644 index 00000000..57db4b35 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_q31.c @@ -0,0 +1,207 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_q31.c + * Description: MFCC function for the q31 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + + +#include "dsp/transform_functions.h" +#include "dsp/statistics_functions.h" +#include "dsp/basic_math_functions.h" +#include "dsp/complex_math_functions.h" +#include "dsp/fast_math_functions.h" +#include "dsp/matrix_functions.h" + +/* Constants for Q31 implementation */ +#define LOG2TOLOG_Q31 0x02C5C860 +#define MICRO_Q31 0x08637BD0 +#define SHIFT_MELFILTER_SATURATION_Q31 10 +/** + @ingroup groupTransforms + */ + + +/** + @defgroup MFCC MFCC + + MFCC Transform + + There are separate functions for floating-point, Q31, and Q31 data types. + */ + + + +/** + @addtogroup MFCC + @{ + */ + +/** + @brief MFCC Q31 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples in Q31 + @param[out] pDst points to the output MFCC values in q8.23 format + @param[inout] pTmp points to a temporary buffer of complex + + @return none + + @par Description + The number of input samples is the FFT length used + when initializing the instance data structure. + + The temporary buffer has a 2*fft length. + + The source buffer is modified by this function. + + The function may saturate. If the FFT length is too + big and the number of MEL filters too small then the fixed + point computations may saturate. + + */ + + +arm_status arm_mfcc_q31( + const arm_mfcc_instance_q31 * S, + q31_t *pSrc, + q31_t *pDst, + q31_t *pTmp + ) +{ + q31_t m; + uint32_t index; + uint32_t fftShift=0; + q31_t logExponent; + q63_t result; + arm_matrix_instance_q31 pDctMat; + uint32_t i; + uint32_t coefsPos; + uint32_t filterLimit; + q31_t *pTmp2=(q31_t*)pTmp; + + arm_status status = ARM_MATH_SUCCESS; + + // q31 + arm_absmax_q31(pSrc,S->fftLen,&m,&index); + + if (m !=0) + { + q31_t quotient; + int16_t shift; + + status = arm_divide_q31(0x7FFFFFFF,m,"ient,&shift); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + + arm_scale_q31(pSrc,quotient,shift,pSrc,S->fftLen); + } + + + // q31 + arm_mult_q31(pSrc,S->windowCoefs, pSrc, S->fftLen); + + + /* Compute spectrum magnitude + */ + fftShift = 31 - __CLZ(S->fftLen); +#if defined(ARM_MFCC_CFFT_BASED) + /* some HW accelerator for CMSIS-DSP used in some boards + are only providing acceleration for CFFT. + With ARM_MFCC_CFFT_BASED enabled, CFFT is used and the MFCC + will be accelerated on those boards. + + The default is to use RFFT + */ + /* Convert from real to complex */ + for(i=0; i < S->fftLen ; i++) + { + pTmp2[2*i] = pSrc[i]; + pTmp2[2*i+1] = 0; + } + arm_cfft_q31(&(S->cfft),pTmp2,0,1); +#else + /* Default RFFT based implementation */ + arm_rfft_q31(&(S->rfft),pSrc,pTmp2); +#endif + filterLimit = 1 + (S->fftLen >> 1); + + + // q31 - fftShift + arm_cmplx_mag_q31(pTmp2,pSrc,filterLimit); + // q30 - fftShift + + + /* Apply MEL filters */ + coefsPos = 0; + for(i=0; inbMelFilters; i++) + { + arm_dot_prod_q31(pSrc+S->filterPos[i], + &(S->filterCoefs[coefsPos]), + S->filterLengths[i], + &result); + + coefsPos += S->filterLengths[i]; + + // q16.48 - fftShift + result += MICRO_Q31; + result >>= (SHIFT_MELFILTER_SATURATION_Q31 + 18); + // q16.29 - fftShift - satShift + pTmp[i] = __SSAT(result,31) ; + + } + + + // q16.29 - fftShift - satShift + /* Compute the log */ + arm_vlog_q31(pTmp,pTmp,S->nbMelFilters); + + + // q5.26 + + logExponent = fftShift + 2 + SHIFT_MELFILTER_SATURATION_Q31; + logExponent = logExponent * LOG2TOLOG_Q31; + + + // q5.26 + arm_offset_q31(pTmp,logExponent,pTmp,S->nbMelFilters); + arm_shift_q31(pTmp,-3,pTmp,S->nbMelFilters); + + + // q8.23 + + pDctMat.numRows=S->nbDctOutputs; + pDctMat.numCols=S->nbMelFilters; + pDctMat.pData=(q31_t*)S->dctCoefs; + + arm_mat_vec_mult_q31(&pDctMat, pTmp, pDst); + + return(status); +} + +/** + @} end of MFCC group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c new file mode 100644 index 00000000..8844b73a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c @@ -0,0 +1,318 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_f32.c + * Description: RFFT & RIFFT Floating point process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +/* ---------------------------------------------------------------------- + * Internal functions prototypes + * -------------------------------------------------------------------- */ + +extern void arm_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier); + +extern void arm_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + +extern void arm_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +void arm_split_rfft_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pATable, + const float32_t * pBTable, + float32_t * pDst, + uint32_t modifier); + +void arm_split_rifft_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pATable, + const float32_t * pBTable, + float32_t * pDst, + uint32_t modifier); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Processing function for the floating-point RFFT/RIFFT. + Source buffer is modified by this function. + + @deprecated Do not use this function. It has been superceded by \ref arm_rfft_fast_f32 and will be removed in the future. + @param[in] S points to an instance of the floating-point RFFT/RIFFT structure + @param[in] pSrc points to the input buffer + @param[out] pDst points to the output buffer + @return none + + @par + For the RIFFT, the source buffer must at least have length + fftLenReal + 2. + The last two elements must be equal to what would be generated + by the RFFT: + (pSrc[0] - pSrc[1]) and 0.0f + */ + +void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst) +{ + const arm_cfft_radix4_instance_f32 *S_CFFT = S->pCfft; + + /* Calculation of Real IFFT of input */ + if (S->ifftFlagR == 1U) + { + /* Real IFFT core process */ + arm_split_rifft_f32 (pSrc, S->fftLenBy2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + + + /* Complex radix-4 IFFT process */ + arm_radix4_butterfly_inverse_f32 (pDst, S_CFFT->fftLen, S_CFFT->pTwiddle, S_CFFT->twidCoefModifier, S_CFFT->onebyfftLen); + + /* Bit reversal process */ + if (S->bitReverseFlagR == 1U) + { + arm_bitreversal_f32 (pDst, S_CFFT->fftLen, S_CFFT->bitRevFactor, S_CFFT->pBitRevTable); + } + } + else + { + /* Calculation of RFFT of input */ + + /* Complex radix-4 FFT process */ + arm_radix4_butterfly_f32 (pSrc, S_CFFT->fftLen, S_CFFT->pTwiddle, S_CFFT->twidCoefModifier); + + /* Bit reversal process */ + if (S->bitReverseFlagR == 1U) + { + arm_bitreversal_f32 (pSrc, S_CFFT->fftLen, S_CFFT->bitRevFactor, S_CFFT->pBitRevTable); + } + + /* Real FFT core process */ + arm_split_rfft_f32 (pSrc, S->fftLenBy2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + } + +} + +/** + @} end of RealFFT group + */ + +/** + @brief Core Real FFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +void arm_split_rfft_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pATable, + const float32_t * pBTable, + float32_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + float32_t outR, outI; /* Temporary variables for output */ + const float32_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + float32_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */ + float32_t *pDst1 = &pDst[2], *pDst2 = &pDst[(4U * fftLen) - 1U]; /* temp pointers for output buffer */ + float32_t *pSrc1 = &pSrc[2], *pSrc2 = &pSrc[(2U * fftLen) - 1U]; /* temp pointers for input buffer */ + + /* Init coefficient pointers */ + pCoefA = &pATable[modifier * 2]; + pCoefB = &pBTable[modifier * 2]; + + i = fftLen - 1U; + + while (i > 0U) + { + /* + outR = ( pSrc[2 * i] * pATable[2 * i] + - pSrc[2 * i + 1] * pATable[2 * i + 1] + + pSrc[2 * n - 2 * i] * pBTable[2 * i] + + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + + pIn[2 * i] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + /* read pATable[2 * i] */ + CoefA1 = *pCoefA++; + /* pATable[2 * i + 1] */ + CoefA2 = *pCoefA; + + /* pSrc[2 * i] * pATable[2 * i] */ + outR = *pSrc1 * CoefA1; + /* pSrc[2 * i] * CoefA2 */ + outI = *pSrc1++ * CoefA2; + + /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */ + outR -= (*pSrc1 + *pSrc2) * CoefA2; + /* pSrc[2 * i + 1] * CoefA1 */ + outI += *pSrc1++ * CoefA1; + + CoefB1 = *pCoefB; + + /* pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */ + outI -= *pSrc2-- * CoefB1; + /* pSrc[2 * fftLen - 2 * i] * CoefA2 */ + outI -= *pSrc2 * CoefA2; + + /* pSrc[2 * fftLen - 2 * i] * CoefB1 */ + outR += *pSrc2-- * CoefB1; + + /* write output */ + *pDst1++ = outR; + *pDst1++ = outI; + + /* write complex conjugate output */ + *pDst2-- = -outI; + *pDst2-- = outR; + + /* update coefficient pointer */ + pCoefB = pCoefB + (modifier * 2U); + pCoefA = pCoefA + ((modifier * 2U) - 1U); + + i--; + + } + + pDst[2U * fftLen] = pSrc[0] - pSrc[1]; + pDst[(2U * fftLen) + 1U] = 0.0f; + + pDst[0] = pSrc[0] + pSrc[1]; + pDst[1] = 0.0f; + +} + + +/** + @brief Core Real IFFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +void arm_split_rifft_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pATable, + const float32_t * pBTable, + float32_t * pDst, + uint32_t modifier) +{ + float32_t outR, outI; /* Temporary variables for output */ + const float32_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + float32_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */ + float32_t *pSrc1 = &pSrc[0], *pSrc2 = &pSrc[(2U * fftLen) + 1U]; + + pCoefA = &pATable[0]; + pCoefB = &pBTable[0]; + + while (fftLen > 0U) + { + /* + outR = ( pIn[2 * i] * pATable[2 * i] + + pIn[2 * i + 1] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + - pIn[2 * i] * pATable[2 * i + 1] + - pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + CoefA1 = *pCoefA++; + CoefA2 = *pCoefA; + + /* outR = (pSrc[2 * i] * CoefA1 */ + outR = *pSrc1 * CoefA1; + + /* - pSrc[2 * i] * CoefA2 */ + outI = -(*pSrc1++) * CoefA2; + + /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */ + outR += (*pSrc1 + *pSrc2) * CoefA2; + + /* pSrc[2 * i + 1] * CoefA1 */ + outI += (*pSrc1++) * CoefA1; + + CoefB1 = *pCoefB; + + /* - pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */ + outI -= *pSrc2-- * CoefB1; + + /* pSrc[2 * fftLen - 2 * i] * CoefB1 */ + outR += *pSrc2 * CoefB1; + + /* pSrc[2 * fftLen - 2 * i] * CoefA2 */ + outI += *pSrc2-- * CoefA2; + + /* write output */ + *pDst++ = outR; + *pDst++ = outI; + + /* update coefficient pointer */ + pCoefB = pCoefB + (modifier * 2); + pCoefA = pCoefA + (modifier * 2 - 1); + + /* Decrement loop count */ + fftLen--; + } + +} diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f16.c new file mode 100644 index 00000000..9048f835 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f16.c @@ -0,0 +1,612 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_fast_f16.c + * Description: RFFT & RIFFT Floating point process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" +#include "arm_common_tables_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void stage_rfft_f16( + const arm_rfft_fast_instance_f16 * S, + float16_t * p, + float16_t * pOut) +{ + int32_t k; /* Loop Counter */ + float16_t twR, twI; /* RFFT Twiddle coefficients */ + const float16_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float16_t *pA = p; /* increasing pointer */ + float16_t *pB = p; /* decreasing pointer */ + float16_t xAR, xAI, xBR, xBI; /* temporary variables */ + float16_t t1a, t1b; /* temporary variables */ + float16_t p0, p1, p2, p3; /* temporary variables */ + + float16x8x2_t tw,xA,xB; + float16x8x2_t tmp1, tmp2, res; + + uint16x8_t vecStridesBkwd; + + vecStridesBkwd = vddupq_u16((uint16_t)14, 2); + + + int blockCnt; + + + k = (S->Sint).fftLen - 1; + + /* Pack first and last sample of the frequency domain together */ + + xBR = pB[0]; + xBI = pB[1]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++ ; + twI = *pCoeff++ ; + + // U1 = XA(1) + XB(1); % It is real + t1a = (_Float16)xBR + (_Float16)xAR ; + + // U2 = XB(1) - XA(1); % It is imaginary + t1b = (_Float16)xBI + (_Float16)xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + *pOut++ = 0.5f16 * ( (_Float16)t1a + (_Float16)t1b ); + *pOut++ = 0.5f16 * ( (_Float16)t1a - (_Float16)t1b ); + + // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) )); + pB = p + 2*k - 14; + pA += 2; + + blockCnt = k >> 3; + while (blockCnt > 0) + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + + xA = vld2q_f16(pA); + pA += 16; + + xB = vld2q_f16(pB); + + xB.val[0] = vldrhq_gather_shifted_offset_f16(pB, vecStridesBkwd); + xB.val[1] = vldrhq_gather_shifted_offset_f16(&pB[1], vecStridesBkwd); + + xB.val[1] = vnegq_f16(xB.val[1]); + pB -= 16; + + + tw = vld2q_f16(pCoeff); + pCoeff += 16; + + + tmp1.val[0] = vaddq_f16(xA.val[0],xB.val[0]); + tmp1.val[1] = vaddq_f16(xA.val[1],xB.val[1]); + + tmp2.val[0] = vsubq_f16(xB.val[0],xA.val[0]); + tmp2.val[1] = vsubq_f16(xB.val[1],xA.val[1]); + + res.val[0] = vmulq(tw.val[0], tmp2.val[0]); + res.val[0] = vfmsq(res.val[0],tw.val[1], tmp2.val[1]); + + res.val[1] = vmulq(tw.val[0], tmp2.val[1]); + res.val[1] = vfmaq(res.val[1], tw.val[1], tmp2.val[0]); + + res.val[0] = vaddq_f16(res.val[0],tmp1.val[0] ); + res.val[1] = vaddq_f16(res.val[1],tmp1.val[1] ); + + res.val[0] = vmulq_n_f16(res.val[0], 0.5f); + res.val[1] = vmulq_n_f16(res.val[1], 0.5f); + + + vst2q_f16(pOut, res); + pOut += 16; + + + blockCnt--; + } + + pB += 14; + blockCnt = k & 7; + while (blockCnt > 0) + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + xBI = pB[1]; + xBR = pB[0]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = (_Float16)xBR - (_Float16)xAR ; + t1b = (_Float16)xBI + (_Float16)xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + p0 = (_Float16)twR * (_Float16)t1a; + p1 = (_Float16)twI * (_Float16)t1a; + p2 = (_Float16)twR * (_Float16)t1b; + p3 = (_Float16)twI * (_Float16)t1b; + + *pOut++ = 0.5f16 * ((_Float16)xAR + (_Float16)xBR + (_Float16)p0 + (_Float16)p3 ); //xAR + *pOut++ = 0.5f16 * ((_Float16)xAI - (_Float16)xBI + (_Float16)p1 - (_Float16)p2 ); //xAI + + pA += 2; + pB -= 2; + blockCnt--; + } +} + +/* Prepares data for inverse cfft */ +void merge_rfft_f16( + const arm_rfft_fast_instance_f16 * S, + float16_t * p, + float16_t * pOut) +{ + int32_t k; /* Loop Counter */ + float16_t twR, twI; /* RFFT Twiddle coefficients */ + const float16_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float16_t *pA = p; /* increasing pointer */ + float16_t *pB = p; /* decreasing pointer */ + float16_t xAR, xAI, xBR, xBI; /* temporary variables */ + float16_t t1a, t1b, r, s, t, u; /* temporary variables */ + + float16x8x2_t tw,xA,xB; + float16x8x2_t tmp1, tmp2, res; + uint16x8_t vecStridesBkwd; + + vecStridesBkwd = vddupq_u16((uint16_t)14, 2); + + int blockCnt; + + + k = (S->Sint).fftLen - 1; + + xAR = pA[0]; + xAI = pA[1]; + + pCoeff += 2 ; + + *pOut++ = 0.5f16 * ( (_Float16)xAR + (_Float16)xAI ); + *pOut++ = 0.5f16 * ( (_Float16)xAR - (_Float16)xAI ); + + pB = p + 2*k - 14; + pA += 2 ; + + blockCnt = k >> 3; + while (blockCnt > 0) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xA = vld2q_f16(pA); + pA += 16; + + xB = vld2q_f16(pB); + + xB.val[0] = vldrhq_gather_shifted_offset_f16(pB, vecStridesBkwd); + xB.val[1] = vldrhq_gather_shifted_offset_f16(&pB[1], vecStridesBkwd); + + xB.val[1] = vnegq_f16(xB.val[1]); + pB -= 16; + + + tw = vld2q_f16(pCoeff); + tw.val[1] = vnegq_f16(tw.val[1]); + pCoeff += 16; + + + tmp1.val[0] = vaddq_f16(xA.val[0],xB.val[0]); + tmp1.val[1] = vaddq_f16(xA.val[1],xB.val[1]); + + tmp2.val[0] = vsubq_f16(xB.val[0],xA.val[0]); + tmp2.val[1] = vsubq_f16(xB.val[1],xA.val[1]); + + res.val[0] = vmulq(tw.val[0], tmp2.val[0]); + res.val[0] = vfmsq(res.val[0],tw.val[1], tmp2.val[1]); + + res.val[1] = vmulq(tw.val[0], tmp2.val[1]); + res.val[1] = vfmaq(res.val[1], tw.val[1], tmp2.val[0]); + + res.val[0] = vaddq_f16(res.val[0],tmp1.val[0] ); + res.val[1] = vaddq_f16(res.val[1],tmp1.val[1] ); + + res.val[0] = vmulq_n_f16(res.val[0], 0.5f); + res.val[1] = vmulq_n_f16(res.val[1], 0.5f); + + + vst2q_f16(pOut, res); + pOut += 16; + + + blockCnt--; + } + + pB += 14; + blockCnt = k & 7; + while (blockCnt > 0) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xBI = pB[1] ; + xBR = pB[0] ; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = (_Float16)xAR - (_Float16)xBR ; + t1b = (_Float16)xAI + (_Float16)xBI ; + + r = (_Float16)twR * (_Float16)t1a; + s = (_Float16)twI * (_Float16)t1b; + t = (_Float16)twI * (_Float16)t1a; + u = (_Float16)twR * (_Float16)t1b; + + // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI); + // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI); + *pOut++ = 0.5f16 * ((_Float16)xAR + (_Float16)xBR - (_Float16)r - (_Float16)s ); //xAR + *pOut++ = 0.5f16 * ((_Float16)xAI - (_Float16)xBI + (_Float16)t - (_Float16)u ); //xAI + + pA += 2; + pB -= 2; + blockCnt--; + } + +} +#else +void stage_rfft_f16( + const arm_rfft_fast_instance_f16 * S, + float16_t * p, + float16_t * pOut) +{ + int32_t k; /* Loop Counter */ + float16_t twR, twI; /* RFFT Twiddle coefficients */ + const float16_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float16_t *pA = p; /* increasing pointer */ + float16_t *pB = p; /* decreasing pointer */ + float16_t xAR, xAI, xBR, xBI; /* temporary variables */ + float16_t t1a, t1b; /* temporary variables */ + float16_t p0, p1, p2, p3; /* temporary variables */ + + + k = (S->Sint).fftLen - 1; + + /* Pack first and last sample of the frequency domain together */ + + xBR = pB[0]; + xBI = pB[1]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++ ; + twI = *pCoeff++ ; + + + // U1 = XA(1) + XB(1); % It is real + t1a = (_Float16)xBR + (_Float16)xAR ; + + // U2 = XB(1) - XA(1); % It is imaginary + t1b = (_Float16)xBI + (_Float16)xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + *pOut++ = 0.5f16 * ( (_Float16)t1a + (_Float16)t1b ); + *pOut++ = 0.5f16 * ( (_Float16)t1a - (_Float16)t1b ); + + // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) )); + pB = p + 2*k; + pA += 2; + + do + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + xBI = pB[1]; + xBR = pB[0]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = (_Float16)xBR - (_Float16)xAR ; + t1b = (_Float16)xBI + (_Float16)xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + p0 = (_Float16)twR * (_Float16)t1a; + p1 = (_Float16)twI * (_Float16)t1a; + p2 = (_Float16)twR * (_Float16)t1b; + p3 = (_Float16)twI * (_Float16)t1b; + + *pOut++ = 0.5f16 * ((_Float16)xAR + (_Float16)xBR + (_Float16)p0 + (_Float16)p3 ); //xAR + *pOut++ = 0.5f16 * ((_Float16)xAI - (_Float16)xBI + (_Float16)p1 - (_Float16)p2 ); //xAI + + + pA += 2; + pB -= 2; + k--; + } while (k > 0); +} + +/* Prepares data for inverse cfft */ +void merge_rfft_f16( + const arm_rfft_fast_instance_f16 * S, + float16_t * p, + float16_t * pOut) +{ + int32_t k; /* Loop Counter */ + float16_t twR, twI; /* RFFT Twiddle coefficients */ + const float16_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float16_t *pA = p; /* increasing pointer */ + float16_t *pB = p; /* decreasing pointer */ + float16_t xAR, xAI, xBR, xBI; /* temporary variables */ + float16_t t1a, t1b, r, s, t, u; /* temporary variables */ + + k = (S->Sint).fftLen - 1; + + xAR = pA[0]; + xAI = pA[1]; + + pCoeff += 2 ; + + *pOut++ = 0.5f16 * ( (_Float16)xAR + (_Float16)xAI ); + *pOut++ = 0.5f16 * ( (_Float16)xAR - (_Float16)xAI ); + + pB = p + 2*k ; + pA += 2 ; + + while (k > 0) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xBI = pB[1] ; + xBR = pB[0] ; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = (_Float16)xAR - (_Float16)xBR ; + t1b = (_Float16)xAI + (_Float16)xBI ; + + r = (_Float16)twR * (_Float16)t1a; + s = (_Float16)twI * (_Float16)t1b; + t = (_Float16)twI * (_Float16)t1a; + u = (_Float16)twR * (_Float16)t1b; + + // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI); + // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI); + *pOut++ = 0.5f16 * ((_Float16)xAR + (_Float16)xBR - (_Float16)r - (_Float16)s ); //xAR + *pOut++ = 0.5f16 * ((_Float16)xAI - (_Float16)xBI + (_Float16)t - (_Float16)u ); //xAI + + pA += 2; + pB -= 2; + k--; + } + +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @ingroup groupTransforms +*/ + +/** + @defgroup RealFFT Real FFT Functions + + @par + The CMSIS DSP library includes specialized algorithms for computing the + FFT of real data sequences. The FFT is defined over complex data but + in many applications the input is real. Real FFT algorithms take advantage + of the symmetry properties of the FFT and have a speed advantage over complex + algorithms of the same length. + @par + The Fast RFFT algorithm relays on the mixed radix CFFT that save processor usage. + @par + The real length N forward FFT of a sequence is computed using the steps shown below. + @par + \image html RFFT.gif "Real Fast Fourier Transform" + @par + The real sequence is initially treated as if it were complex to perform a CFFT. + Later, a processing stage reshapes the data to obtain half of the frequency spectrum + in complex format. Except the first complex number that contains the two real numbers + X[0] and X[N/2] all the data is complex. In other words, the first complex sample + contains two real values packed. + @par + The input for the inverse RFFT should keep the same format as the output of the + forward RFFT. A first processing stage pre-process the data to later perform an + inverse CFFT. + @par + \image html RIFFT.gif "Real Inverse Fast Fourier Transform" + @par + The algorithms for floating-point, Q15, and Q31 data are slightly different + and we describe each algorithm in turn. + @par Floating-point + The main functions are \ref arm_rfft_fast_f16() and \ref arm_rfft_fast_init_f16(). + + @par + The FFT of a real N-point sequence has even symmetry in the frequency domain. + The second half of the data equals the conjugate of the first half flipped in frequency. + Looking at the data, we see that we can uniquely represent the FFT using only N/2 complex numbers. + These are packed into the output array in alternating real and imaginary components: + @par + X = { real[0], imag[0], real[1], imag[1], real[2], imag[2] ... + real[(N/2)-1], imag[(N/2)-1 } + @par + It happens that the first complex number (real[0], imag[0]) is actually + all real. real[0] represents the DC offset, and imag[0] should be 0. + (real[1], imag[1]) is the fundamental frequency, (real[2], imag[2]) is + the first harmonic and so on. + @par + The real FFT functions pack the frequency domain data in this fashion. + The forward transform outputs the data in this form and the inverse + transform expects input data in this form. The function always performs + the needed bitreversal so that the input and output data is always in + normal order. The functions support lengths of [32, 64, 128, ..., 4096] + samples. + @par Q15 and Q31 + The real algorithms are defined in a similar manner and utilize N/2 complex + transforms behind the scenes. + @par + The complex transforms used internally include scaling to prevent fixed-point + overflows. The overall scaling equals 1/(fftLen/2). + Due to the use of complex transform internally, the source buffer is + modified by the rfft. + @par + A separate instance structure must be defined for each transform used but + twiddle factor and bit reversal tables can be reused. + @par + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Initializes twiddle factor table and bit reversal table pointers. + - Initializes the internal complex FFT data structure. + @par + Use of the initialization function is optional **except for MVE versions where it is mandatory**. + If you don't use the initialization functions, then the structures should be initialized with code + similar to the one below: +
+      arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+      arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+  
+ where fftLenReal is the length of the real transform; + fftLenBy2 length of the internal complex transform (fftLenReal/2). + ifftFlagR Selects forward (=0) or inverse (=1) transform. + bitReverseFlagR Selects bit reversed output (=0) or normal order + output (=1). + twidCoefRModifier stride modifier for the twiddle factor table. + The value is based on the FFT length; + pTwiddleARealpoints to the A array of twiddle coefficients; + pTwiddleBRealpoints to the B array of twiddle coefficients; + pCfft points to the CFFT Instance structure. The CFFT structure + must also be initialized. +@par + Note that with MVE versions you can't initialize instance structures directly and **must + use the initialization function**. + */ + +/** + @addtogroup RealFFT + @{ +*/ + +/** + @brief Processing function for the floating-point real FFT. + @param[in] S points to an arm_rfft_fast_instance_f16 structure + @param[in] p points to input buffer (Source buffer is modified by this function.) + @param[in] pOut points to output buffer + @param[in] ifftFlag + - value = 0: RFFT + - value = 1: RIFFT + @return none +*/ + +void arm_rfft_fast_f16( + const arm_rfft_fast_instance_f16 * S, + float16_t * p, + float16_t * pOut, + uint8_t ifftFlag) +{ + const arm_cfft_instance_f16 * Sint = &(S->Sint); + + + /* Calculation of Real FFT */ + if (ifftFlag) + { + /* Real FFT compression */ + merge_rfft_f16(S, p, pOut); + /* Complex radix-4 IFFT process */ + arm_cfft_f16( Sint, pOut, ifftFlag, 1); + } + else + { + + /* Calculation of RFFT of input */ + arm_cfft_f16( Sint, p, ifftFlag, 1); + + /* Real FFT extraction */ + stage_rfft_f16(S, p, pOut); + } +} + +/** +* @} end of RealFFT group +*/ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c new file mode 100644 index 00000000..67125043 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c @@ -0,0 +1,603 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_fast_f32.c + * Description: RFFT & RIFFT Floating point process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void stage_rfft_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, + float32_t * pOut) +{ + int32_t k; /* Loop Counter */ + float32_t twR, twI; /* RFFT Twiddle coefficients */ + const float32_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float32_t *pA = p; /* increasing pointer */ + float32_t *pB = p; /* decreasing pointer */ + float32_t xAR, xAI, xBR, xBI; /* temporary variables */ + float32_t t1a, t1b; /* temporary variables */ + float32_t p0, p1, p2, p3; /* temporary variables */ + + float32x4x2_t tw,xA,xB; + float32x4x2_t tmp1, tmp2, res; + + uint32x4_t vecStridesFwd, vecStridesBkwd; + + vecStridesFwd = vidupq_u32((uint32_t)0, 2); + vecStridesBkwd = -vecStridesFwd; + + int blockCnt; + + + k = (S->Sint).fftLen - 1; + + /* Pack first and last sample of the frequency domain together */ + + xBR = pB[0]; + xBI = pB[1]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++ ; + twI = *pCoeff++ ; + + // U1 = XA(1) + XB(1); % It is real + t1a = xBR + xAR ; + + // U2 = XB(1) - XA(1); % It is imaginary + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + *pOut++ = 0.5f * ( t1a + t1b ); + *pOut++ = 0.5f * ( t1a - t1b ); + + // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) )); + pB = p + 2*k; + pA += 2; + + blockCnt = k >> 2; + while (blockCnt > 0) + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + + xA = vld2q_f32(pA); + pA += 8; + + xB = vld2q_f32(pB); + + xB.val[0] = vldrwq_gather_shifted_offset_f32(pB, vecStridesBkwd); + xB.val[1] = vldrwq_gather_shifted_offset_f32(&pB[1], vecStridesBkwd); + + xB.val[1] = vnegq_f32(xB.val[1]); + pB -= 8; + + + tw = vld2q_f32(pCoeff); + pCoeff += 8; + + + tmp1.val[0] = vaddq_f32(xA.val[0],xB.val[0]); + tmp1.val[1] = vaddq_f32(xA.val[1],xB.val[1]); + + tmp2.val[0] = vsubq_f32(xB.val[0],xA.val[0]); + tmp2.val[1] = vsubq_f32(xB.val[1],xA.val[1]); + + res.val[0] = vmulq(tw.val[0], tmp2.val[0]); + res.val[0] = vfmsq(res.val[0],tw.val[1], tmp2.val[1]); + + res.val[1] = vmulq(tw.val[0], tmp2.val[1]); + res.val[1] = vfmaq(res.val[1], tw.val[1], tmp2.val[0]); + + res.val[0] = vaddq_f32(res.val[0],tmp1.val[0] ); + res.val[1] = vaddq_f32(res.val[1],tmp1.val[1] ); + + res.val[0] = vmulq_n_f32(res.val[0], 0.5f); + res.val[1] = vmulq_n_f32(res.val[1], 0.5f); + + + vst2q_f32(pOut, res); + pOut += 8; + + + blockCnt--; + } + + blockCnt = k & 3; + while (blockCnt > 0) + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + xBI = pB[1]; + xBR = pB[0]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xBR - xAR ; + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + p0 = twR * t1a; + p1 = twI * t1a; + p2 = twR * t1b; + p3 = twI * t1b; + + *pOut++ = 0.5f * (xAR + xBR + p0 + p3 ); //xAR + *pOut++ = 0.5f * (xAI - xBI + p1 - p2 ); //xAI + + pA += 2; + pB -= 2; + blockCnt--; + } +} + +/* Prepares data for inverse cfft */ +void merge_rfft_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, + float32_t * pOut) +{ + int32_t k; /* Loop Counter */ + float32_t twR, twI; /* RFFT Twiddle coefficients */ + const float32_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float32_t *pA = p; /* increasing pointer */ + float32_t *pB = p; /* decreasing pointer */ + float32_t xAR, xAI, xBR, xBI; /* temporary variables */ + float32_t t1a, t1b, r, s, t, u; /* temporary variables */ + + float32x4x2_t tw,xA,xB; + float32x4x2_t tmp1, tmp2, res; + uint32x4_t vecStridesFwd, vecStridesBkwd; + + vecStridesFwd = vidupq_u32((uint32_t)0, 2); + vecStridesBkwd = -vecStridesFwd; + + int blockCnt; + + + k = (S->Sint).fftLen - 1; + + xAR = pA[0]; + xAI = pA[1]; + + pCoeff += 2 ; + + *pOut++ = 0.5f * ( xAR + xAI ); + *pOut++ = 0.5f * ( xAR - xAI ); + + pB = p + 2*k ; + pA += 2 ; + + blockCnt = k >> 2; + while (blockCnt > 0) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xA = vld2q_f32(pA); + pA += 8; + + xB = vld2q_f32(pB); + + xB.val[0] = vldrwq_gather_shifted_offset_f32(pB, vecStridesBkwd); + xB.val[1] = vldrwq_gather_shifted_offset_f32(&pB[1], vecStridesBkwd); + + xB.val[1] = vnegq_f32(xB.val[1]); + pB -= 8; + + + tw = vld2q_f32(pCoeff); + tw.val[1] = vnegq_f32(tw.val[1]); + pCoeff += 8; + + + tmp1.val[0] = vaddq_f32(xA.val[0],xB.val[0]); + tmp1.val[1] = vaddq_f32(xA.val[1],xB.val[1]); + + tmp2.val[0] = vsubq_f32(xB.val[0],xA.val[0]); + tmp2.val[1] = vsubq_f32(xB.val[1],xA.val[1]); + + res.val[0] = vmulq(tw.val[0], tmp2.val[0]); + res.val[0] = vfmsq(res.val[0],tw.val[1], tmp2.val[1]); + + res.val[1] = vmulq(tw.val[0], tmp2.val[1]); + res.val[1] = vfmaq(res.val[1], tw.val[1], tmp2.val[0]); + + res.val[0] = vaddq_f32(res.val[0],tmp1.val[0] ); + res.val[1] = vaddq_f32(res.val[1],tmp1.val[1] ); + + res.val[0] = vmulq_n_f32(res.val[0], 0.5f); + res.val[1] = vmulq_n_f32(res.val[1], 0.5f); + + + vst2q_f32(pOut, res); + pOut += 8; + + + blockCnt--; + } + + blockCnt = k & 3; + while (blockCnt > 0) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xBI = pB[1] ; + xBR = pB[0] ; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xAR - xBR ; + t1b = xAI + xBI ; + + r = twR * t1a; + s = twI * t1b; + t = twI * t1a; + u = twR * t1b; + + // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI); + // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI); + *pOut++ = 0.5f * (xAR + xBR - r - s ); //xAR + *pOut++ = 0.5f * (xAI - xBI + t - u ); //xAI + + pA += 2; + pB -= 2; + blockCnt--; + } + +} +#else +void stage_rfft_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, + float32_t * pOut) +{ + int32_t k; /* Loop Counter */ + float32_t twR, twI; /* RFFT Twiddle coefficients */ + const float32_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float32_t *pA = p; /* increasing pointer */ + float32_t *pB = p; /* decreasing pointer */ + float32_t xAR, xAI, xBR, xBI; /* temporary variables */ + float32_t t1a, t1b; /* temporary variables */ + float32_t p0, p1, p2, p3; /* temporary variables */ + + + k = (S->Sint).fftLen - 1; + + /* Pack first and last sample of the frequency domain together */ + + xBR = pB[0]; + xBI = pB[1]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++ ; + twI = *pCoeff++ ; + + + // U1 = XA(1) + XB(1); % It is real + t1a = xBR + xAR ; + + // U2 = XB(1) - XA(1); % It is imaginary + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + *pOut++ = 0.5f * ( t1a + t1b ); + *pOut++ = 0.5f * ( t1a - t1b ); + + // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) )); + pB = p + 2*k; + pA += 2; + + do + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + xBI = pB[1]; + xBR = pB[0]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xBR - xAR ; + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + p0 = twR * t1a; + p1 = twI * t1a; + p2 = twR * t1b; + p3 = twI * t1b; + + *pOut++ = 0.5f * (xAR + xBR + p0 + p3 ); //xAR + *pOut++ = 0.5f * (xAI - xBI + p1 - p2 ); //xAI + + + pA += 2; + pB -= 2; + k--; + } while (k > 0); +} + +/* Prepares data for inverse cfft */ +void merge_rfft_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, + float32_t * pOut) +{ + int32_t k; /* Loop Counter */ + float32_t twR, twI; /* RFFT Twiddle coefficients */ + const float32_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float32_t *pA = p; /* increasing pointer */ + float32_t *pB = p; /* decreasing pointer */ + float32_t xAR, xAI, xBR, xBI; /* temporary variables */ + float32_t t1a, t1b, r, s, t, u; /* temporary variables */ + + k = (S->Sint).fftLen - 1; + + xAR = pA[0]; + xAI = pA[1]; + + pCoeff += 2 ; + + *pOut++ = 0.5f * ( xAR + xAI ); + *pOut++ = 0.5f * ( xAR - xAI ); + + pB = p + 2*k ; + pA += 2 ; + + while (k > 0) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xBI = pB[1] ; + xBR = pB[0] ; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xAR - xBR ; + t1b = xAI + xBI ; + + r = twR * t1a; + s = twI * t1b; + t = twI * t1a; + u = twR * t1b; + + // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI); + // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI); + *pOut++ = 0.5f * (xAR + xBR - r - s ); //xAR + *pOut++ = 0.5f * (xAI - xBI + t - u ); //xAI + + pA += 2; + pB -= 2; + k--; + } + +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @ingroup groupTransforms +*/ + +/** + @defgroup RealFFT Real FFT Functions + + @par + The CMSIS DSP library includes specialized algorithms for computing the + FFT of real data sequences. The FFT is defined over complex data but + in many applications the input is real. Real FFT algorithms take advantage + of the symmetry properties of the FFT and have a speed advantage over complex + algorithms of the same length. + @par + The Fast RFFT algorithm relays on the mixed radix CFFT that save processor usage. + @par + The real length N forward FFT of a sequence is computed using the steps shown below. + @par + \image html RFFT.gif "Real Fast Fourier Transform" + @par + The real sequence is initially treated as if it were complex to perform a CFFT. + Later, a processing stage reshapes the data to obtain half of the frequency spectrum + in complex format. Except the first complex number that contains the two real numbers + X[0] and X[N/2] all the data is complex. In other words, the first complex sample + contains two real values packed. + @par + The input for the inverse RFFT should keep the same format as the output of the + forward RFFT. A first processing stage pre-process the data to later perform an + inverse CFFT. + @par + \image html RIFFT.gif "Real Inverse Fast Fourier Transform" + @par + The algorithms for floating-point, Q15, and Q31 data are slightly different + and we describe each algorithm in turn. + @par Floating-point + The main functions are \ref arm_rfft_fast_f32() and \ref arm_rfft_fast_init_f32(). + The older functions \ref arm_rfft_f32() and \ref arm_rfft_init_f32() have been deprecated + but are still documented. + @par + The FFT of a real N-point sequence has even symmetry in the frequency domain. + The second half of the data equals the conjugate of the first half flipped in frequency. + Looking at the data, we see that we can uniquely represent the FFT using only N/2 complex numbers. + These are packed into the output array in alternating real and imaginary components: + @par + X = { real[0], imag[0], real[1], imag[1], real[2], imag[2] ... + real[(N/2)-1], imag[(N/2)-1 } + @par + It happens that the first complex number (real[0], imag[0]) is actually + all real. real[0] represents the DC offset, and imag[0] should be 0. + (real[1], imag[1]) is the fundamental frequency, (real[2], imag[2]) is + the first harmonic and so on. + @par + The real FFT functions pack the frequency domain data in this fashion. + The forward transform outputs the data in this form and the inverse + transform expects input data in this form. The function always performs + the needed bitreversal so that the input and output data is always in + normal order. The functions support lengths of [32, 64, 128, ..., 4096] + samples. + @par Q15 and Q31 + The real algorithms are defined in a similar manner and utilize N/2 complex + transforms behind the scenes. + @par + The complex transforms used internally include scaling to prevent fixed-point + overflows. The overall scaling equals 1/(fftLen/2). + Due to the use of complex transform internally, the source buffer is + modified by the rfft. + @par + A separate instance structure must be defined for each transform used but + twiddle factor and bit reversal tables can be reused. + @par + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Initializes twiddle factor table and bit reversal table pointers. + - Initializes the internal complex FFT data structure. + @par + Use of the initialization function is optional **except for MVE versions where it is mandatory**. + If you don't use the initialization functions, then the structures should be initialized with code + similar to the one below: +
+      arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+      arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+  
+ where fftLenReal is the length of the real transform; + fftLenBy2 length of the internal complex transform (fftLenReal/2). + ifftFlagR Selects forward (=0) or inverse (=1) transform. + bitReverseFlagR Selects bit reversed output (=0) or normal order + output (=1). + twidCoefRModifier stride modifier for the twiddle factor table. + The value is based on the FFT length; + pTwiddleARealpoints to the A array of twiddle coefficients; + pTwiddleBRealpoints to the B array of twiddle coefficients; + pCfft points to the CFFT Instance structure. The CFFT structure + must also be initialized. +@par + Note that with MVE versions you can't initialize instance structures directly and **must + use the initialization function**. + */ + +/** + @addtogroup RealFFT + @{ +*/ + +/** + @brief Processing function for the floating-point real FFT. + @param[in] S points to an arm_rfft_fast_instance_f32 structure + @param[in] p points to input buffer (Source buffer is modified by this function.) + @param[in] pOut points to output buffer + @param[in] ifftFlag + - value = 0: RFFT + - value = 1: RIFFT + @return none +*/ + +void arm_rfft_fast_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, + float32_t * pOut, + uint8_t ifftFlag) +{ + const arm_cfft_instance_f32 * Sint = &(S->Sint); + + /* Calculation of Real FFT */ + if (ifftFlag) + { + /* Real FFT compression */ + merge_rfft_f32(S, p, pOut); + /* Complex radix-4 IFFT process */ + arm_cfft_f32( Sint, pOut, ifftFlag, 1); + } + else + { + /* Calculation of RFFT of input */ + arm_cfft_f32( Sint, p, ifftFlag, 1); + + /* Real FFT extraction */ + stage_rfft_f32(S, p, pOut); + } +} + +/** +* @} end of RealFFT group +*/ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f64.c new file mode 100644 index 00000000..a1e4ed01 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f64.c @@ -0,0 +1,228 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_fast_f64.c + * Description: RFFT & RIFFT Double precision Floating point process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +void stage_rfft_f64( + const arm_rfft_fast_instance_f64 * S, + float64_t * p, + float64_t * pOut) +{ + uint32_t k; /* Loop Counter */ + float64_t twR, twI; /* RFFT Twiddle coefficients */ + const float64_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float64_t *pA = p; /* increasing pointer */ + float64_t *pB = p; /* decreasing pointer */ + float64_t xAR, xAI, xBR, xBI; /* temporary variables */ + float64_t t1a, t1b; /* temporary variables */ + float64_t p0, p1, p2, p3; /* temporary variables */ + + + k = (S->Sint).fftLen - 1; + + /* Pack first and last sample of the frequency domain together */ + + xBR = pB[0]; + xBI = pB[1]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++ ; + twI = *pCoeff++ ; + + // U1 = XA(1) + XB(1); % It is real + t1a = xBR + xAR ; + + // U2 = XB(1) - XA(1); % It is imaginary + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + *pOut++ = 0.5 * ( t1a + t1b ); + *pOut++ = 0.5 * ( t1a - t1b ); + + // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) )); + pB = p + 2*k; + pA += 2; + + do + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + xBI = pB[1]; + xBR = pB[0]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xBR - xAR ; + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + p0 = twR * t1a; + p1 = twI * t1a; + p2 = twR * t1b; + p3 = twI * t1b; + + *pOut++ = 0.5 * (xAR + xBR + p0 + p3 ); //xAR + *pOut++ = 0.5 * (xAI - xBI + p1 - p2 ); //xAI + + pA += 2; + pB -= 2; + k--; + } while (k > 0U); +} + +/* Prepares data for inverse cfft */ +void merge_rfft_f64( + const arm_rfft_fast_instance_f64 * S, + float64_t * p, + float64_t * pOut) +{ + uint32_t k; /* Loop Counter */ + float64_t twR, twI; /* RFFT Twiddle coefficients */ + const float64_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float64_t *pA = p; /* increasing pointer */ + float64_t *pB = p; /* decreasing pointer */ + float64_t xAR, xAI, xBR, xBI; /* temporary variables */ + float64_t t1a, t1b, r, s, t, u; /* temporary variables */ + + k = (S->Sint).fftLen - 1; + + xAR = pA[0]; + xAI = pA[1]; + + pCoeff += 2 ; + + *pOut++ = 0.5 * ( xAR + xAI ); + *pOut++ = 0.5 * ( xAR - xAI ); + + pB = p + 2*k ; + pA += 2 ; + + while (k > 0U) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xBI = pB[1] ; + xBR = pB[0] ; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xAR - xBR ; + t1b = xAI + xBI ; + + r = twR * t1a; + s = twI * t1b; + t = twI * t1a; + u = twR * t1b; + + // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI); + // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI); + *pOut++ = 0.5 * (xAR + xBR - r - s ); //xAR + *pOut++ = 0.5 * (xAI - xBI + t - u ); //xAI + + pA += 2; + pB -= 2; + k--; + } + +} + +/** + @ingroup groupTransforms +*/ + + +/** + @addtogroup RealFFT + @{ +*/ + +/** + @brief Processing function for the Double Precision floating-point real FFT. + @param[in] S points to an arm_rfft_fast_instance_f64 structure + @param[in] p points to input buffer (Source buffer is modified by this function.) + @param[in] pOut points to output buffer + @param[in] ifftFlag + - value = 0: RFFT + - value = 1: RIFFT + @return none +*/ + +void arm_rfft_fast_f64( + arm_rfft_fast_instance_f64 * S, + float64_t * p, + float64_t * pOut, + uint8_t ifftFlag) +{ + arm_cfft_instance_f64 * Sint = &(S->Sint); + Sint->fftLen = S->fftLenRFFT / 2; + + /* Calculation of Real FFT */ + if (ifftFlag) + { + /* Real FFT compression */ + merge_rfft_f64(S, p, pOut); + + /* Complex radix-4 IFFT process */ + arm_cfft_f64( Sint, pOut, ifftFlag, 1); + } + else + { + /* Calculation of RFFT of input */ + arm_cfft_f64( Sint, p, ifftFlag, 1); + + /* Real FFT extraction */ + stage_rfft_f64(S, p, pOut); + } +} + +/** +* @} end of RealFFT group +*/ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f16.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f16.c new file mode 100644 index 00000000..158180b4 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f16.c @@ -0,0 +1,357 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_fast_init_f16.c + * Description: Split Radix Decimation in Frequency CFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" +#include "arm_common_tables_f16.h" +#include "arm_const_structs_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup RealFFT + @{ + */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_16) && defined(ARM_TABLE_BITREVIDX_FLT_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_32)) + +/** + @private + @brief Initialization function for the 32pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_32_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),16); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + + S->fftLenRFFT = 32U; + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_32; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_32) && defined(ARM_TABLE_BITREVIDX_FLT_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_64)) + +/** + @private + @brief Initialization function for the 64pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_64_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),32); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 64U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_64; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_64) && defined(ARM_TABLE_BITREVIDX_FLT_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_128)) + +/** + @private + @brief Initialization function for the 128pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_128_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),64); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 128; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_128; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_128) && defined(ARM_TABLE_BITREVIDX_FLT_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_256)) + +/** + @private + @brief Initialization function for the 256pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected +*/ + +static arm_status arm_rfft_256_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),128); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 256U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_256; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_256) && defined(ARM_TABLE_BITREVIDX_FLT_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_512)) + +/** + @private + @brief Initialization function for the 512pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_512_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),256); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 512U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_512; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_512) && defined(ARM_TABLE_BITREVIDX_FLT_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_1024)) +/** + @private + @brief Initialization function for the 1024pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_1024_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),512); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 1024U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_1024; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_2048)) +/** + @private + @brief Initialization function for the 2048pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ +static arm_status arm_rfft_2048_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),1024); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 2048U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_2048; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_4096)) +/** + @private +* @brief Initialization function for the 4096pt floating-point real FFT. +* @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_4096_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),2048); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 4096U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_4096; + + return ARM_MATH_SUCCESS; +} +#endif + +/** + @brief Initialization function for the floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @param[in] fftLen length of the Real Sequence + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Description + The parameter fftLen specifies the length of RFFT/CIFFT process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +arm_status arm_rfft_fast_init_f16( + arm_rfft_fast_instance_f16 * S, + uint16_t fftLen) +{ + typedef arm_status(*fft_init_ptr)( arm_rfft_fast_instance_f16 *); + fft_init_ptr fptr = 0x0; + + switch (fftLen) + { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_4096)) + case 4096U: + fptr = arm_rfft_4096_fast_init_f16; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_2048)) + case 2048U: + fptr = arm_rfft_2048_fast_init_f16; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_512) && defined(ARM_TABLE_BITREVIDX_FLT_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_1024)) + case 1024U: + fptr = arm_rfft_1024_fast_init_f16; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_256) && defined(ARM_TABLE_BITREVIDX_FLT_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_512)) + case 512U: + fptr = arm_rfft_512_fast_init_f16; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_128) && defined(ARM_TABLE_BITREVIDX_FLT_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_256)) + case 256U: + fptr = arm_rfft_256_fast_init_f16; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_64) && defined(ARM_TABLE_BITREVIDX_FLT_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_128)) + case 128U: + fptr = arm_rfft_128_fast_init_f16; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_32) && defined(ARM_TABLE_BITREVIDX_FLT_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_64)) + case 64U: + fptr = arm_rfft_64_fast_init_f16; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_16) && defined(ARM_TABLE_BITREVIDX_FLT_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_32)) + case 32U: + fptr = arm_rfft_32_fast_init_f16; + break; +#endif + default: + break; + } + + if( ! fptr ) return ARM_MATH_ARGUMENT_ERROR; + return fptr( S ); + +} + +/** + @} end of RealFFT group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c new file mode 100644 index 00000000..e8273b47 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c @@ -0,0 +1,352 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_fast_init_f32.c + * Description: Split Radix Decimation in Frequency CFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup RealFFT + @{ + */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_BITREVIDX_FLT_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)) + +/** + @private + @brief Initialization function for the 32pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_32_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),16); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + + S->fftLenRFFT = 32U; + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_32; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)) + +/** + @private + @brief Initialization function for the 64pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_64_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),32); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 64U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_64; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)) + +/** + @private + @brief Initialization function for the 128pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_128_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),64); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 128; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_128; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)) + +/** + @private + @brief Initialization function for the 256pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected +*/ + +static arm_status arm_rfft_256_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),128); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 256U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_256; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)) + +/** + @private + @brief Initialization function for the 512pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_512_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),256); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 512U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_512; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)) +/** + @private + @brief Initialization function for the 1024pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_1024_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),512); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 1024U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_1024; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)) +/** + @private + @brief Initialization function for the 2048pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ +static arm_status arm_rfft_2048_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),1024); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 2048U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_2048; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)) +/** + @private +* @brief Initialization function for the 4096pt floating-point real FFT. +* @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_4096_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),2048); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 4096U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_4096; + + return ARM_MATH_SUCCESS; +} +#endif + +/** + @brief Initialization function for the floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @param[in] fftLen length of the Real Sequence + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Description + The parameter fftLen specifies the length of RFFT/CIFFT process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +arm_status arm_rfft_fast_init_f32( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen) +{ + typedef arm_status(*fft_init_ptr)( arm_rfft_fast_instance_f32 *); + fft_init_ptr fptr = 0x0; + + switch (fftLen) + { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)) + case 4096U: + fptr = arm_rfft_4096_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)) + case 2048U: + fptr = arm_rfft_2048_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)) + case 1024U: + fptr = arm_rfft_1024_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)) + case 512U: + fptr = arm_rfft_512_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)) + case 256U: + fptr = arm_rfft_256_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)) + case 128U: + fptr = arm_rfft_128_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)) + case 64U: + fptr = arm_rfft_64_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_BITREVIDX_FLT_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)) + case 32U: + fptr = arm_rfft_32_fast_init_f32; + break; +#endif + default: + break; + } + + if( ! fptr ) return ARM_MATH_ARGUMENT_ERROR; + return fptr( S ); + +} + +/** + @} end of RealFFT group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f64.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f64.c new file mode 100644 index 00000000..c6d3e69c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f64.c @@ -0,0 +1,344 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_fast_init_f64.c + * Description: Split Radix Decimation in Frequency CFFT Double Precision Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup RealFFT + @{ + */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_16) && defined(ARM_TABLE_BITREVIDX_FLT64_16) && defined(ARM_TABLE_TWIDDLECOEF_F64_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32)) + +/** + @brief Initialization function for the 32pt double precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_32_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 16U; + S->fftLenRFFT = 32U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_16; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_16; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_32; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_32) && defined(ARM_TABLE_BITREVIDX_FLT64_32) && defined(ARM_TABLE_TWIDDLECOEF_F64_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64)) + +/** + @brief Initialization function for the 64pt Double Precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_64_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 32U; + S->fftLenRFFT = 64U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_32; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_32; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_64; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_64) && defined(ARM_TABLE_BITREVIDX_FLT64_64) && defined(ARM_TABLE_TWIDDLECOEF_F64_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128)) + +/** + @brief Initialization function for the 128pt Double Precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_128_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 64U; + S->fftLenRFFT = 128U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_64; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_64; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_128; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_128) && defined(ARM_TABLE_BITREVIDX_FLT64_128) && defined(ARM_TABLE_TWIDDLECOEF_F64_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256)) + +/** + @brief Initialization function for the 256pt Double Precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected +*/ + +static arm_status arm_rfft_256_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 128U; + S->fftLenRFFT = 256U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_128; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_128; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_256; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_256) && defined(ARM_TABLE_BITREVIDX_FLT64_256) && defined(ARM_TABLE_TWIDDLECOEF_F64_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512)) + +/** + @brief Initialization function for the 512pt Double Precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_512_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 256U; + S->fftLenRFFT = 512U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_256; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_256; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_512; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_512) && defined(ARM_TABLE_BITREVIDX_FLT64_512) && defined(ARM_TABLE_TWIDDLECOEF_F64_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024)) +/** + @brief Initialization function for the 1024pt Double Precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_1024_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 512U; + S->fftLenRFFT = 1024U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_512; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_512; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_1024; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_1024) && defined(ARM_TABLE_BITREVIDX_FLT64_1024) && defined(ARM_TABLE_TWIDDLECOEF_F64_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048)) +/** + @brief Initialization function for the 2048pt Double Precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ +static arm_status arm_rfft_2048_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 1024U; + S->fftLenRFFT = 2048U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_1024; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_1024; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_2048; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_2048) && defined(ARM_TABLE_BITREVIDX_FLT64_2048) && defined(ARM_TABLE_TWIDDLECOEF_F64_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096)) +/** +* @brief Initialization function for the 4096pt Double Precision floating-point real FFT. +* @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_4096_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 2048U; + S->fftLenRFFT = 4096U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_2048; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_2048; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_4096; + + return ARM_MATH_SUCCESS; +} +#endif + +/** + @brief Initialization function for the Double Precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @param[in] fftLen length of the Real Sequence + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Description + The parameter fftLen specifies the length of RFFT/CIFFT process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +arm_status arm_rfft_fast_init_f64( + arm_rfft_fast_instance_f64 * S, + uint16_t fftLen) +{ + typedef arm_status(*fft_init_ptr)( arm_rfft_fast_instance_f64 *); + fft_init_ptr fptr = 0x0; + + switch (fftLen) + { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_2048) && defined(ARM_TABLE_BITREVIDX_FLT64_2048) && defined(ARM_TABLE_TWIDDLECOEF_F64_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096)) + case 4096U: + fptr = arm_rfft_4096_fast_init_f64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_1024) && defined(ARM_TABLE_BITREVIDX_FLT64_1024) && defined(ARM_TABLE_TWIDDLECOEF_F64_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048)) + case 2048U: + fptr = arm_rfft_2048_fast_init_f64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_512) && defined(ARM_TABLE_BITREVIDX_FLT64_512) && defined(ARM_TABLE_TWIDDLECOEF_F64_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024)) + case 1024U: + fptr = arm_rfft_1024_fast_init_f64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_256) && defined(ARM_TABLE_BITREVIDX_FLT64_256) && defined(ARM_TABLE_TWIDDLECOEF_F64_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512)) + case 512U: + fptr = arm_rfft_512_fast_init_f64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_128) && defined(ARM_TABLE_BITREVIDX_FLT64_128) && defined(ARM_TABLE_TWIDDLECOEF_F64_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256)) + case 256U: + fptr = arm_rfft_256_fast_init_f64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_64) && defined(ARM_TABLE_BITREVIDX_FLT64_64) && defined(ARM_TABLE_TWIDDLECOEF_F64_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128)) + case 128U: + fptr = arm_rfft_128_fast_init_f64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_32) && defined(ARM_TABLE_BITREVIDX_FLT64_32) && defined(ARM_TABLE_TWIDDLECOEF_F64_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64)) + case 64U: + fptr = arm_rfft_64_fast_init_f64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_16) && defined(ARM_TABLE_BITREVIDX_FLT64_16) && defined(ARM_TABLE_TWIDDLECOEF_F64_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32)) + case 32U: + fptr = arm_rfft_32_fast_init_f64; + break; +#endif + default: + break; + } + + if( ! fptr ) return ARM_MATH_ARGUMENT_ERROR; + return fptr( S ); + +} + +/** + @} end of RealFFT group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c new file mode 100644 index 00000000..0a32da66 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c @@ -0,0 +1,147 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_init_f32.c + * Description: RFFT & RIFFT Floating point initialisation function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Initialization function for the floating-point RFFT/RIFFT. + @deprecated Do not use this function. It has been superceded by \ref arm_rfft_fast_init_f32 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point RFFT/RIFFT structure + @param[in,out] S_CFFT points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLenReal length of the FFT. + @param[in] ifftFlagR flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLenReal is not a supported length + + @par Description + The parameter fftLenRealspecifies length of RFFT/RIFFT Process. + Supported FFT Lengths are 128, 512, 2048. + @par + The parameter ifftFlagR controls whether a forward or inverse transform is computed. + Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + This function also initializes Twiddle factor table. + */ + +arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialize the Real FFT length */ + S->fftLenReal = (uint16_t) fftLenReal; + + /* Initialize the Complex FFT length */ + S->fftLenBy2 = (uint16_t) fftLenReal / 2U; + + /* Initialize the Twiddle coefficientA pointer */ + S->pTwiddleAReal = (float32_t *) realCoefA; + + /* Initialize the Twiddle coefficientB pointer */ + S->pTwiddleBReal = (float32_t *) realCoefB; + + /* Initialize the Flag for selection of RFFT or RIFFT */ + S->ifftFlagR = (uint8_t) ifftFlagR; + + /* Initialize the Flag for calculation Bit reversal or not */ + S->bitReverseFlagR = (uint8_t) bitReverseFlag; + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLenReal) + { + /* Init table modifier value */ + case 8192U: + S->twidCoefRModifier = 1U; + break; + case 2048U: + S->twidCoefRModifier = 4U; + break; + case 512U: + S->twidCoefRModifier = 16U; + break; + case 128U: + S->twidCoefRModifier = 64U; + break; + default: + /* Reporting argument error if rfftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + /* Init Complex FFT Instance */ + S->pCfft = S_CFFT; + + if (S->ifftFlagR) + { + /* Initializes the CIFFT Module for fftLenreal/2 length */ + arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 1U, 0U); + } + else + { + /* Initializes the CFFT Module for fftLenreal/2 length */ + arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 0U, 0U); + } + +#endif +#endif + /* return the status of RFFT Init function */ + return (status); + +} + +/** + @} end of RealFFT group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c new file mode 100644 index 00000000..e70f8af9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c @@ -0,0 +1,248 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_init_q15.c + * Description: RFFT & RIFFT Q15 initialisation function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" +#include "arm_const_structs.h" + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Initialization function for the Q15 RFFT/RIFFT. + @param[in,out] S points to an instance of the Q15 RFFT/RIFFT structure + @param[in] fftLenReal length of the FFT + @param[in] ifftFlagR flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLenReal is not a supported length + + @par Details + The parameter fftLenReal specifies length of RFFT/RIFFT Process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192. + @par + The parameter ifftFlagR controls whether a forward or inverse transform is computed. + Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + This function also initializes Twiddle factor table. + */ + +arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialize the Real FFT length */ + S->fftLenReal = (uint16_t) fftLenReal; + + /* Initialize the Twiddle coefficientA pointer */ + S->pTwiddleAReal = (q15_t *) realCoefAQ15; + + /* Initialize the Twiddle coefficientB pointer */ + S->pTwiddleBReal = (q15_t *) realCoefBQ15; + + /* Initialize the Flag for selection of RFFT or RIFFT */ + S->ifftFlagR = (uint8_t) ifftFlagR; + + /* Initialize the Flag for calculation Bit reversal or not */ + S->bitReverseFlagR = (uint8_t) bitReverseFlag; + + /* Initialization of coef modifier depending on the FFT length */ + switch (S->fftLenReal) + { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) + case 8192U: + S->twidCoefRModifier = 1U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),4096); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len4096; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) + case 4096U: + S->twidCoefRModifier = 2U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),2048); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len2048; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) + case 2048U: + S->twidCoefRModifier = 4U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),1024); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len1024; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) + case 1024U: + S->twidCoefRModifier = 8U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),512); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len512; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) + case 512U: + S->twidCoefRModifier = 16U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),256); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len256; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) + case 256U: + S->twidCoefRModifier = 32U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),128); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len128; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) + case 128U: + S->twidCoefRModifier = 64U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),64); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len64; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) + case 64U: + S->twidCoefRModifier = 128U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),32); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len32; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) + case 32U: + S->twidCoefRModifier = 256U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),16); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len16; + #endif + break; +#endif + default: + /* Reporting argument error if rfftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif + /* return the status of RFFT Init function */ + return (status); +} + +/** + @} end of RealFFT group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c new file mode 100644 index 00000000..0a28719e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c @@ -0,0 +1,246 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_init_q31.c + * Description: RFFT & RIFFT Q31 initialisation function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" +#include "arm_const_structs.h" + + + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Initialization function for the Q31 RFFT/RIFFT. + @param[in,out] S points to an instance of the Q31 RFFT/RIFFT structure + @param[in] fftLenReal length of the FFT + @param[in] ifftFlagR flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLenReal is not a supported length + + @par Details + The parameter fftLenReal specifies length of RFFT/RIFFT Process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192. + @par + The parameter ifftFlagR controls whether a forward or inverse transform is computed. + Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + This function also initializes Twiddle factor table. +*/ + +arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialize the Real FFT length */ + S->fftLenReal = (uint16_t) fftLenReal; + + /* Initialize the Twiddle coefficientA pointer */ + S->pTwiddleAReal = (q31_t *) realCoefAQ31; + + /* Initialize the Twiddle coefficientB pointer */ + S->pTwiddleBReal = (q31_t *) realCoefBQ31; + + /* Initialize the Flag for selection of RFFT or RIFFT */ + S->ifftFlagR = (uint8_t) ifftFlagR; + + /* Initialize the Flag for calculation Bit reversal or not */ + S->bitReverseFlagR = (uint8_t) bitReverseFlag; + + /* Initialization of coef modifier depending on the FFT length */ + switch (S->fftLenReal) + { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) + case 8192U: + + + S->twidCoefRModifier = 1U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),4096); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len4096; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) + case 4096U: + S->twidCoefRModifier = 2U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),2048); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len2048; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) + case 2048U: + S->twidCoefRModifier = 4U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),1024); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len1024; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) + case 1024U: + S->twidCoefRModifier = 8U; + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),512); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len512; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) + case 512U: + S->twidCoefRModifier = 16U; + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),256); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len256; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) + case 256U: + S->twidCoefRModifier = 32U; + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),128); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len128; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) + case 128U: + S->twidCoefRModifier = 64U; + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),64); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len64; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) + case 64U: + S->twidCoefRModifier = 128U; + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),32); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len32; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) + case 32U: + S->twidCoefRModifier = 256U; + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),16); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len16; + #endif + break; +#endif + default: + /* Reporting argument error if rfftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif + /* return the status of RFFT Init function */ + return (status); +} + +/** + @} end of RealFFT group + */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c new file mode 100644 index 00000000..7d149c60 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c @@ -0,0 +1,526 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_q15.c + * Description: RFFT & RIFFT Q15 process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +/* ---------------------------------------------------------------------- + * Internal functions prototypes + * -------------------------------------------------------------------- */ + +void arm_split_rfft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier); + +void arm_split_rifft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier); + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Processing function for the Q15 RFFT/RIFFT. + @param[in] S points to an instance of the Q15 RFFT/RIFFT structure + @param[in] pSrc points to input buffer (Source buffer is modified by this function.) + @param[out] pDst points to output buffer + @return none + + @par Input an output formats + Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. + Hence the output format is different for different RFFT sizes. + The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT: + @par + \image html RFFTQ15.gif "Input and Output Formats for Q15 RFFT" + @par + \image html RIFFTQ15.gif "Input and Output Formats for Q15 RIFFT" + @par + If the input buffer is of length N, the output buffer must have length 2*N. + The input buffer is modified by this function. + @par + For the RIFFT, the source buffer must at least have length + fftLenReal + 2. + The last two elements must be equal to what would be generated + by the RFFT: + (pSrc[0] - pSrc[1]) >> 1 and 0 + */ + +void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst) +{ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + const arm_cfft_instance_q15 *S_CFFT = &(S->cfftInst); +#else + const arm_cfft_instance_q15 *S_CFFT = S->pCfft; +#endif + uint32_t L2 = S->fftLenReal >> 1U; + + /* Calculation of RIFFT of input */ + if (S->ifftFlagR == 1U) + { + /* Real IFFT core process */ + arm_split_rifft_q15 (pSrc, L2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + + /* Complex IFFT process */ + arm_cfft_q15 (S_CFFT, pDst, S->ifftFlagR, S->bitReverseFlagR); + + arm_shift_q15(pDst, 1, pDst, S->fftLenReal); + } + else + { + /* Calculation of RFFT of input */ + + /* Complex FFT process */ + arm_cfft_q15 (S_CFFT, pSrc, S->ifftFlagR, S->bitReverseFlagR); + + /* Real FFT core process */ + arm_split_rfft_q15 (pSrc, L2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + } + +} + +/** + @} end of RealFFT group + */ + +/** + @brief Core Real FFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + + @par + The function implements a Real FFT + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_fft.h" + +#if defined(__CMSIS_GCC_H) +#define MVE_CMPLX_MULT_FX_AxB_S16(A,B) vqdmladhxq_s16(vqdmlsdhq_s16((__typeof(A))vuninitializedq_s16(), A, B), A, B) +#define MVE_CMPLX_MULT_FX_AxConjB_S16(A,B) vqdmladhq_s16(vqdmlsdhxq_s16((__typeof(A))vuninitializedq_s16(), A, B), A, B) + +#endif + +void arm_split_rfft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + const q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q15_t *pOut1 = &pDst[2]; + q15_t *pIn1 = &pSrc[2]; + uint16x8_t offsetIn = { 6, 7, 4, 5, 2, 3, 0, 1 }; + uint16x8_t offsetCoef; + const uint16_t offsetCoefArr[16] = { + 0, 0, 2, 2, 4, 4, 6, 6, + 0, 1, 0, 1, 0, 1, 0, 1 + }; + + offsetCoef = vmulq_n_u16(vld1q_u16(offsetCoefArr), modifier) + vld1q_u16(offsetCoefArr + 8); + offsetIn = vaddq_n_u16(offsetIn, (2 * fftLen - 8)); + + /* Init coefficient pointers */ + pCoefA = &pATable[modifier * 2]; + pCoefB = &pBTable[modifier * 2]; + + const q15_t *pCoefAb, *pCoefBb; + pCoefAb = pCoefA; + pCoefBb = pCoefB; + + pIn1 = &pSrc[2]; + + i = fftLen - 1U; + i = i / 4 + 1; + while (i > 0U) { + q15x8_t in1 = vld1q_s16(pIn1); + q15x8_t in2 = vldrhq_gather_shifted_offset_s16(pSrc, offsetIn); + q15x8_t coefA = vldrhq_gather_shifted_offset_s16(pCoefAb, offsetCoef); + q15x8_t coefB = vldrhq_gather_shifted_offset_s16(pCoefBb, offsetCoef); + +#if defined(__CMSIS_GCC_H) + q15x8_t out = vhaddq_s16(MVE_CMPLX_MULT_FX_AxB_S16(in1, coefA), + MVE_CMPLX_MULT_FX_AxConjB_S16(coefB, in2)); +#else + q15x8_t out = vhaddq_s16(MVE_CMPLX_MULT_FX_AxB(in1, coefA, q15x8_t), + MVE_CMPLX_MULT_FX_AxConjB(coefB, in2, q15x8_t)); +#endif + vst1q_s16(pOut1, out); + pOut1 += 8; + + offsetCoef = vaddq_n_u16(offsetCoef, modifier * 8); + offsetIn -= 8; + pIn1 += 8; + i -= 1; + } + + pDst[2 * fftLen] = (pSrc[0] - pSrc[1]) >> 1U; + pDst[2 * fftLen + 1] = 0; + + pDst[0] = (pSrc[0] + pSrc[1]) >> 1U; + pDst[1] = 0; +} +#else +void arm_split_rfft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + q31_t outR, outI; /* Temporary variables for output */ + const q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q15_t *pSrc1, *pSrc2; +#if defined (ARM_MATH_DSP) + q15_t *pD1, *pD2; +#endif + + /* Init coefficient pointers */ + pCoefA = &pATable[modifier * 2]; + pCoefB = &pBTable[modifier * 2]; + + pSrc1 = &pSrc[2]; + pSrc2 = &pSrc[(2U * fftLen) - 2U]; + +#if defined (ARM_MATH_DSP) + + i = 1U; + pD1 = pDst + 2; + pD2 = pDst + (4U * fftLen) - 2; + + for (i = fftLen - 1; i > 0; i--) + { + /* + outR = ( pSrc[2 * i] * pATable[2 * i] + - pSrc[2 * i + 1] * pATable[2 * i + 1] + + pSrc[2 * n - 2 * i] * pBTable[2 * i] + + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + + pIn[2 * i] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]) + */ + + +#ifndef ARM_MATH_BIG_ENDIAN + /* pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1] */ + outR = __SMUSD(read_q15x2 (pSrc1), read_q15x2((q15_t *) pCoefA)); +#else + /* -(pSrc[2 * i + 1] * pATable[2 * i + 1] - pSrc[2 * i] * pATable[2 * i]) */ + outR = -(__SMUSD(read_q15x2 (pSrc1), read_q15x2((q15_t *) pCoefA))); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* pSrc[2 * n - 2 * i] * pBTable[2 * i] + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */ + outR = __SMLAD(read_q15x2 (pSrc2), read_q15x2((q15_t *) pCoefB), outR) >> 16U; + + /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] - pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */ +#ifndef ARM_MATH_BIG_ENDIAN + outI = __SMUSDX(read_q15x2_da (&pSrc2), read_q15x2((q15_t *) pCoefB)); +#else + outI = __SMUSDX(read_q15x2 ((q15_t *) pCoefB), read_q15x2_da (&pSrc2)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] */ + outI = __SMLADX(read_q15x2_ia (&pSrc1), read_q15x2 ((q15_t *) pCoefA), outI); + + /* write output */ + *pD1++ = (q15_t) outR; + *pD1++ = outI >> 16U; + + /* write complex conjugate output */ + pD2[0] = (q15_t) outR; + pD2[1] = -(outI >> 16U); + pD2 -= 2; + + /* update coefficient pointer */ + pCoefB = pCoefB + (2U * modifier); + pCoefA = pCoefA + (2U * modifier); + } + + pDst[2U * fftLen] = (pSrc[0] - pSrc[1]) >> 1U; + pDst[2U * fftLen + 1U] = 0; + + pDst[0] = (pSrc[0] + pSrc[1]) >> 1U; + pDst[1] = 0; + +#else + + i = 1U; + + while (i < fftLen) + { + /* + outR = ( pSrc[2 * i] * pATable[2 * i] + - pSrc[2 * i + 1] * pATable[2 * i + 1] + + pSrc[2 * n - 2 * i] * pBTable[2 * i] + + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + */ + + outR = *pSrc1 * *pCoefA; + outR = outR - (*(pSrc1 + 1) * *(pCoefA + 1)); + outR = outR + (*pSrc2 * *pCoefB); + outR = (outR + (*(pSrc2 + 1) * *(pCoefB + 1))) >> 16; + + /* + outI = ( pIn[2 * i + 1] * pATable[2 * i] + + pIn[2 * i] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + outI = *pSrc2 * *(pCoefB + 1); + outI = outI - (*(pSrc2 + 1) * *pCoefB); + outI = outI + (*(pSrc1 + 1) * *pCoefA); + outI = outI + (*pSrc1 * *(pCoefA + 1)); + + /* update input pointers */ + pSrc1 += 2U; + pSrc2 -= 2U; + + /* write output */ + pDst[2U * i] = (q15_t) outR; + pDst[2U * i + 1U] = outI >> 16U; + + /* write complex conjugate output */ + pDst[(4U * fftLen) - (2U * i)] = (q15_t) outR; + pDst[((4U * fftLen) - (2U * i)) + 1U] = -(outI >> 16U); + + /* update coefficient pointer */ + pCoefB = pCoefB + (2U * modifier); + pCoefA = pCoefA + (2U * modifier); + + i++; + } + + pDst[2U * fftLen] = (pSrc[0] - pSrc[1]) >> 1; + pDst[2U * fftLen + 1U] = 0; + + pDst[0] = (pSrc[0] + pSrc[1]) >> 1; + pDst[1] = 0; + +#endif /* #if defined (ARM_MATH_DSP) */ +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @brief Core Real IFFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + + @par + The function implements a Real IFFT + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_fft.h" + +void arm_split_rifft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + const q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q15_t *pIn1; + uint16x8_t offset = { 6, 7, 4, 5, 2, 3, 0, 1 }; + uint16x8_t offsetCoef; + int16x8_t conj = { 1, -1, 1, -1, 1, -1, 1, -1 }; /* conjugate */ + const uint16_t offsetCoefArr[16] = { + 0, 0, 2, 2, 4, 4, 6, 6, + 0, 1, 0, 1, 0, 1, 0, 1 + }; + + offsetCoef = vmulq_n_u16(vld1q_u16(offsetCoefArr), modifier) + vld1q_u16(offsetCoefArr + 8); + + offset = vaddq_n_u16(offset, (2 * fftLen - 6)); + + /* Init coefficient pointers */ + pCoefA = &pATable[0]; + pCoefB = &pBTable[0]; + + const q15_t *pCoefAb, *pCoefBb; + pCoefAb = pCoefA; + pCoefBb = pCoefB; + + pIn1 = &pSrc[0]; + + i = fftLen; + i = i / 4; + + while (i > 0U) { + q15x8_t in1 = vld1q_s16(pIn1); + q15x8_t in2 = vldrhq_gather_shifted_offset_s16(pSrc, offset); + q15x8_t coefA = vldrhq_gather_shifted_offset_s16(pCoefAb, offsetCoef); + q15x8_t coefB = vldrhq_gather_shifted_offset_s16(pCoefBb, offsetCoef); + + /* can we avoid the conjugate here ? */ + q15x8_t out = vhaddq_s16(MVE_CMPLX_MULT_FX_AxConjB(in1, coefA, q15x8_t), + vmulq(conj, MVE_CMPLX_MULT_FX_AxB(in2, coefB, q15x8_t))); + + vst1q_s16(pDst, out); + pDst += 8; + + offsetCoef = vaddq_n_u16(offsetCoef, modifier * 8); + offset -= 8; + + pIn1 += 8; + i -= 1; + } +} +#else +void arm_split_rifft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + q31_t outR, outI; /* Temporary variables for output */ + const q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q15_t *pSrc1, *pSrc2; + q15_t *pDst1 = &pDst[0]; + + pCoefA = &pATable[0]; + pCoefB = &pBTable[0]; + + pSrc1 = &pSrc[0]; + pSrc2 = &pSrc[2 * fftLen]; + + i = fftLen; + while (i > 0U) + { + /* + outR = ( pIn[2 * i] * pATable[2 * i] + + pIn[2 * i + 1] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + - pIn[2 * i] * pATable[2 * i + 1] + - pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + +#if defined (ARM_MATH_DSP) + +#ifndef ARM_MATH_BIG_ENDIAN + /* pIn[2 * n - 2 * i] * pBTable[2 * i] - pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */ + outR = __SMUSD(read_q15x2(pSrc2), read_q15x2((q15_t *) pCoefB)); +#else + /* -(-pIn[2 * n - 2 * i] * pBTable[2 * i] + pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1])) */ + outR = -(__SMUSD(read_q15x2(pSrc2), read_q15x2((q15_t *) pCoefB))); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] + pIn[2 * n - 2 * i] * pBTable[2 * i] */ + outR = __SMLAD(read_q15x2(pSrc1), read_q15x2 ((q15_t *) pCoefA), outR) >> 16U; + + /* -pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */ + outI = __SMUADX(read_q15x2_da (&pSrc2), read_q15x2((q15_t *) pCoefB)); + + /* pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] */ +#ifndef ARM_MATH_BIG_ENDIAN + outI = __SMLSDX(read_q15x2 ((q15_t *) pCoefA), read_q15x2_ia (&pSrc1), -outI); +#else + outI = __SMLSDX(read_q15x2_ia (&pSrc1), read_q15x2 ((q15_t *) pCoefA), -outI); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* write output */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst1, __PKHBT(outR, (outI >> 16U), 16)); +#else + write_q15x2_ia (&pDst1, __PKHBT((outI >> 16U), outR, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + +#else /* #if defined (ARM_MATH_DSP) */ + + outR = *pSrc2 * *pCoefB; + outR = outR - (*(pSrc2 + 1) * *(pCoefB + 1)); + outR = outR + (*pSrc1 * *pCoefA); + outR = (outR + (*(pSrc1 + 1) * *(pCoefA + 1))) >> 16; + + outI = *(pSrc1 + 1) * *pCoefA; + outI = outI - (*pSrc1 * *(pCoefA + 1)); + outI = outI - (*pSrc2 * *(pCoefB + 1)); + outI = outI - (*(pSrc2 + 1) * *(pCoefB)); + + /* update input pointers */ + pSrc1 += 2U; + pSrc2 -= 2U; + + /* write output */ + *pDst1++ = (q15_t) outR; + *pDst1++ = (q15_t) (outI >> 16); + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* update coefficient pointer */ + pCoefB = pCoefB + (2 * modifier); + pCoefA = pCoefA + (2 * modifier); + + i--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ diff --git a/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c new file mode 100644 index 00000000..ad3212db --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c @@ -0,0 +1,430 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_q31.c + * Description: FFT & RIFFT Q31 process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +/* ---------------------------------------------------------------------- + * Internal functions prototypes + * -------------------------------------------------------------------- */ + +void arm_split_rfft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier); + +void arm_split_rifft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier); + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Processing function for the Q31 RFFT/RIFFT. + @param[in] S points to an instance of the Q31 RFFT/RIFFT structure + @param[in] pSrc points to input buffer (Source buffer is modified by this function) + @param[out] pDst points to output buffer + @return none + + @par Input an output formats + Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. + Hence the output format is different for different RFFT sizes. + The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT: + @par + \image html RFFTQ31.gif "Input and Output Formats for Q31 RFFT" + @par + \image html RIFFTQ31.gif "Input and Output Formats for Q31 RIFFT" + @par + If the input buffer is of length N, the output buffer must have length 2*N. + The input buffer is modified by this function. + @par + For the RIFFT, the source buffer must at least have length + fftLenReal + 2. + The last two elements must be equal to what would be generated + by the RFFT: + (pSrc[0] - pSrc[1]) >> 1 and 0 + + */ + +void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst) +{ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + const arm_cfft_instance_q31 *S_CFFT = &(S->cfftInst); +#else + const arm_cfft_instance_q31 *S_CFFT = S->pCfft; +#endif + uint32_t L2 = S->fftLenReal >> 1U; + + /* Calculation of RIFFT of input */ + if (S->ifftFlagR == 1U) + { + /* Real IFFT core process */ + arm_split_rifft_q31 (pSrc, L2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + + /* Complex IFFT process */ + arm_cfft_q31 (S_CFFT, pDst, S->ifftFlagR, S->bitReverseFlagR); + + arm_shift_q31(pDst, 1, pDst, S->fftLenReal); + } + else + { + /* Calculation of RFFT of input */ + + /* Complex FFT process */ + arm_cfft_q31 (S_CFFT, pSrc, S->ifftFlagR, S->bitReverseFlagR); + + /* Real FFT core process */ + arm_split_rfft_q31 (pSrc, L2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + } + +} + +/** + @} end of RealFFT group + */ + +/** + @brief Core Real FFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_fft.h" + +#if defined(__CMSIS_GCC_H) + +#define MVE_CMPLX_MULT_FX_AxB_S32(A,B) vqdmladhxq_s32(vqdmlsdhq_s32((__typeof(A))vuninitializedq_s32(), A, B), A, B) +#define MVE_CMPLX_MULT_FX_AxConjB_S32(A,B) vqdmladhq_s32(vqdmlsdhxq_s32((__typeof(A))vuninitializedq_s32(), A, B), A, B) + +#endif + +void arm_split_rfft_q31( + q31_t *pSrc, + uint32_t fftLen, + const q31_t *pATable, + const q31_t *pBTable, + q31_t *pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + const q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q31_t *pOut1 = &pDst[2]; + q31_t *pIn1 = &pSrc[2]; + uint32x4_t offset = { 2, 3, 0, 1 }; + uint32x4_t offsetCoef = { 0, 1, modifier * 2, modifier * 2 + 1 }; + + offset = offset + (2 * fftLen - 4); + + + /* Init coefficient pointers */ + pCoefA = &pATable[modifier * 2]; + pCoefB = &pBTable[modifier * 2]; + + const q31_t *pCoefAb, *pCoefBb; + pCoefAb = pCoefA; + pCoefBb = pCoefB; + + pIn1 = &pSrc[2]; + + i = fftLen - 1U; + i = i / 2 + 1; + while (i > 0U) { + q31x4_t in1 = vld1q_s32(pIn1); + q31x4_t in2 = vldrwq_gather_shifted_offset_s32(pSrc, offset); + q31x4_t coefA = vldrwq_gather_shifted_offset_s32(pCoefAb, offsetCoef); + q31x4_t coefB = vldrwq_gather_shifted_offset_s32(pCoefBb, offsetCoef); +#if defined(__CMSIS_GCC_H) + q31x4_t out = vhaddq_s32(MVE_CMPLX_MULT_FX_AxB_S32(in1, coefA),MVE_CMPLX_MULT_FX_AxConjB_S32(coefB, in2)); +#else + q31x4_t out = vhaddq_s32(MVE_CMPLX_MULT_FX_AxB(in1, coefA, q31x4_t), + MVE_CMPLX_MULT_FX_AxConjB(coefB, in2, q31x4_t)); +#endif + vst1q(pOut1, out); + pOut1 += 4; + + offsetCoef += modifier * 4; + offset -= 4; + + pIn1 += 4; + i -= 1; + } + + pDst[2 * fftLen] = (pSrc[0] - pSrc[1]) >> 1U; + pDst[2 * fftLen + 1] = 0; + + pDst[0] = (pSrc[0] + pSrc[1]) >> 1U; + pDst[1] = 0; +} +#else +void arm_split_rfft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + q31_t outR, outI; /* Temporary variables for output */ + const q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q31_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */ + q31_t *pOut1 = &pDst[2], *pOut2 = &pDst[4 * fftLen - 1]; + q31_t *pIn1 = &pSrc[2], *pIn2 = &pSrc[2 * fftLen - 1]; + + /* Init coefficient pointers */ + pCoefA = &pATable[modifier * 2]; + pCoefB = &pBTable[modifier * 2]; + + i = fftLen - 1U; + + while (i > 0U) + { + /* + outR = ( pSrc[2 * i] * pATable[2 * i] + - pSrc[2 * i + 1] * pATable[2 * i + 1] + + pSrc[2 * n - 2 * i] * pBTable[2 * i] + + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + + pIn[2 * i] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + CoefA1 = *pCoefA++; + CoefA2 = *pCoefA; + + /* outR = (pSrc[2 * i] * pATable[2 * i] */ + mult_32x32_keep32_R (outR, *pIn1, CoefA1); + + /* outI = pIn[2 * i] * pATable[2 * i + 1] */ + mult_32x32_keep32_R (outI, *pIn1++, CoefA2); + + /* - pSrc[2 * i + 1] * pATable[2 * i + 1] */ + multSub_32x32_keep32_R (outR, *pIn1, CoefA2); + + /* (pIn[2 * i + 1] * pATable[2 * i] */ + multAcc_32x32_keep32_R (outI, *pIn1++, CoefA1); + + /* pSrc[2 * n - 2 * i] * pBTable[2 * i] */ + multSub_32x32_keep32_R (outR, *pIn2, CoefA2); + CoefB1 = *pCoefB; + + /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */ + multSub_32x32_keep32_R (outI, *pIn2--, CoefB1); + + /* pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */ + multAcc_32x32_keep32_R (outR, *pIn2, CoefB1); + + /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */ + multSub_32x32_keep32_R (outI, *pIn2--, CoefA2); + + /* write output */ + *pOut1++ = outR; + *pOut1++ = outI; + + /* write complex conjugate output */ + *pOut2-- = -outI; + *pOut2-- = outR; + + /* update coefficient pointer */ + pCoefB = pCoefB + (2 * modifier); + pCoefA = pCoefA + (2 * modifier - 1); + + /* Decrement loop count */ + i--; + } + + pDst[2 * fftLen] = (pSrc[0] - pSrc[1]) >> 1U; + pDst[2 * fftLen + 1] = 0; + + pDst[0] = (pSrc[0] + pSrc[1]) >> 1U; + pDst[1] = 0; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @brief Core Real IFFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_split_rifft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + const q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q31_t *pIn1; + uint32x4_t offset = { 2, 3, 0, 1 }; + uint32x4_t offsetCoef = { 0, 1, modifier * 2, modifier * 2 + 1 }; + int32x4_t conj = { 1, -1, 1, -1 }; + + offset = offset + (2 * fftLen - 2); + + /* Init coefficient pointers */ + pCoefA = &pATable[0]; + pCoefB = &pBTable[0]; + + const q31_t *pCoefAb, *pCoefBb; + pCoefAb = pCoefA; + pCoefBb = pCoefB; + + pIn1 = &pSrc[0]; + + i = fftLen; + i = i >> 1; + while (i > 0U) { + q31x4_t in1 = vld1q_s32(pIn1); + q31x4_t in2 = vldrwq_gather_shifted_offset_s32(pSrc, offset); + q31x4_t coefA = vldrwq_gather_shifted_offset_s32(pCoefAb, offsetCoef); + q31x4_t coefB = vldrwq_gather_shifted_offset_s32(pCoefBb, offsetCoef); + + /* can we avoid the conjugate here ? */ +#if defined(__CMSIS_GCC_H) + q31x4_t out = vhaddq_s32(MVE_CMPLX_MULT_FX_AxConjB_S32(in1, coefA), + vmulq_s32(conj, MVE_CMPLX_MULT_FX_AxB_S32(in2, coefB))); +#else + q31x4_t out = vhaddq_s32(MVE_CMPLX_MULT_FX_AxConjB(in1, coefA, q31x4_t), + vmulq_s32(conj, MVE_CMPLX_MULT_FX_AxB(in2, coefB, q31x4_t))); +#endif + vst1q_s32(pDst, out); + pDst += 4; + + offsetCoef += modifier * 4; + offset -= 4; + + pIn1 += 4; + i -= 1; + } +} +#else +void arm_split_rifft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier) +{ + q31_t outR, outI; /* Temporary variables for output */ + const q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q31_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */ + q31_t *pIn1 = &pSrc[0], *pIn2 = &pSrc[2 * fftLen + 1]; + + pCoefA = &pATable[0]; + pCoefB = &pBTable[0]; + + while (fftLen > 0U) + { + /* + outR = ( pIn[2 * i] * pATable[2 * i] + + pIn[2 * i + 1] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + - pIn[2 * i] * pATable[2 * i + 1] + - pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + CoefA1 = *pCoefA++; + CoefA2 = *pCoefA; + + /* outR = (pIn[2 * i] * pATable[2 * i] */ + mult_32x32_keep32_R (outR, *pIn1, CoefA1); + + /* - pIn[2 * i] * pATable[2 * i + 1] */ + mult_32x32_keep32_R (outI, *pIn1++, -CoefA2); + + /* pIn[2 * i + 1] * pATable[2 * i + 1] */ + multAcc_32x32_keep32_R (outR, *pIn1, CoefA2); + + /* pIn[2 * i + 1] * pATable[2 * i] */ + multAcc_32x32_keep32_R (outI, *pIn1++, CoefA1); + + /* pIn[2 * n - 2 * i] * pBTable[2 * i] */ + multAcc_32x32_keep32_R (outR, *pIn2, CoefA2); + CoefB1 = *pCoefB; + + /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */ + multSub_32x32_keep32_R (outI, *pIn2--, CoefB1); + + /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */ + multAcc_32x32_keep32_R (outR, *pIn2, CoefB1); + + /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */ + multAcc_32x32_keep32_R (outI, *pIn2--, CoefA2); + + /* write output */ + *pDst++ = outR; + *pDst++ = outI; + + /* update coefficient pointer */ + pCoefB = pCoefB + (modifier * 2); + pCoefA = pCoefA + (modifier * 2 - 1); + + /* Decrement loop count */ + fftLen--; + } + +} + +#endif /* defined(ARM_MATH_MVEI) */ diff --git a/benchmark/interface/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h b/benchmark/interface/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h index f681a555..d334d934 100644 --- a/benchmark/interface/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h +++ b/benchmark/interface/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h @@ -1,4 +1,4 @@ -/** +/** ****************************************************************************** * @file stm32h573xx.h * @author MCD Application Team diff --git a/benchmark/interface/Drivers/CMSIS/Device/ST/STM32H5xx/LICENSE.md b/benchmark/interface/Drivers/CMSIS/Device/ST/STM32H5xx/LICENSE.md new file mode 100644 index 00000000..20b36299 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/Device/ST/STM32H5xx/LICENSE.md @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright {yyyy} {name of copyright owner} + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/benchmark/interface/Drivers/CMSIS/NN/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/NN/CMakeLists.txt new file mode 100644 index 00000000..ad3b748b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/CMakeLists.txt @@ -0,0 +1,29 @@ +# +# Copyright (c) 2019-2021 Arm Limited. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +cmake_minimum_required(VERSION 3.15.6) + +project(CMSISNN) + +set(CMSIS_PATH "${CMAKE_CURRENT_SOURCE_DIR}/../..") + +option(BUILD_CMSIS_NN_FUNCTIONS "Build CMSIS-NN Source." ON) + +if(BUILD_CMSIS_NN_FUNCTIONS) + add_subdirectory(Source) +endif() diff --git a/benchmark/interface/Drivers/CMSIS/NN/Include/arm_nn_math_types.h b/benchmark/interface/Drivers/CMSIS/NN/Include/arm_nn_math_types.h new file mode 100644 index 00000000..390fe782 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Include/arm_nn_math_types.h @@ -0,0 +1,169 @@ +/****************************************************************************** + * @file arm_nn_math_types.h + * @brief Compiler include and basic types + * @version V1.1.0 + * @date 09 March 2022 + * Target Processor: Cortex-M + ******************************************************************************/ +/* + * Copyright (c) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + Copied from CMSIS/DSP/arm_math_types.h and modified +*/ + +#ifndef _ARM_NN_MATH_TYPES_H_ + +#define _ARM_NN_MATH_TYPES_H_ + +/* DSP inlcude for enum arm_status. */ +#include "arm_math_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined(__CC_ARM) + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + +#elif defined(__GNUC__) + +#elif defined(__ICCARM__) + +#elif defined(__TI_ARM__) + +#elif defined(__CSMC__) + +#elif defined(__TASKING__) + +#elif defined(_MSC_VER) + +#else +#error Unknown compiler +#endif + +/* Included for instrinsics definitions */ +#if defined(_MSC_VER) +#include +#ifndef __STATIC_FORCEINLINE +#define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static __inline +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __declspec(align(x)) +#endif + +#elif defined(__GNUC_PYTHON__) +#include +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __STATIC_FORCEINLINE +#define __STATIC_FORCEINLINE static inline __attribute__((always_inline)) +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif + +#else +#include "cmsis_compiler.h" +#endif + +#include +#include +#include +#include + +/* evaluate ARM DSP feature */ +#if (defined(__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) +#ifndef ARM_MATH_DSP +#define ARM_MATH_DSP 1 +#endif +#endif + +#if __ARM_FEATURE_MVE +#ifndef ARM_MATH_MVEI +#define ARM_MATH_MVEI +#endif +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined(__CC_ARM) + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + +#elif defined(__GNUC__) +// #pragma GCC diagnostic pop + +#elif defined(__ICCARM__) + +#elif defined(__TI_ARM__) + +#elif defined(__CSMC__) + +#elif defined(__TASKING__) + +#elif defined(_MSC_VER) + +#else +#error Unknown compiler +#endif + +#ifdef __cplusplus +} +#endif + +#if __ARM_FEATURE_MVE +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Add necessary typedefs + */ + +#define NN_Q31_MAX ((q31_t)(0x7FFFFFFFL)) +#define NN_Q15_MAX ((q15_t)(0x7FFF)) +#define NN_Q7_MAX ((q7_t)(0x7F)) +#define NN_Q31_MIN ((q31_t)(0x80000000L)) +#define NN_Q15_MIN ((q15_t)(0x8000)) +#define NN_Q7_MIN ((q7_t)(0x80)) + +/** + * @brief Error status returned by some functions in the library. + */ + +typedef enum +{ + ARM_CMSIS_NN_SUCCESS = 0, /**< No error */ + ARM_CMSIS_NN_ARG_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_CMSIS_NN_NO_IMPL_ERROR = -2, /**< No implementation available */ +} arm_cmsis_nn_status; + +#ifdef __cplusplus +} +#endif + +#endif /*ifndef _ARM_NN_MATH_TYPES_H_ */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Include/arm_nn_tables.h b/benchmark/interface/Drivers/CMSIS/NN/Include/arm_nn_tables.h new file mode 100644 index 00000000..327294d6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Include/arm_nn_tables.h @@ -0,0 +1,56 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_tables.h + * Description: Extern declaration for NN tables + * + * $Date: 17. August 2021 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_NN_TABLES_H +#define _ARM_NN_TABLES_H + +#include "arm_nn_math_types.h" + +/** + * @brief tables for various activation functions + * + */ + +extern const q15_t sigmoidTable_q15[256]; +extern const q7_t sigmoidTable_q7[256]; + +extern const q7_t tanhTable_q7[256]; +extern const q15_t tanhTable_q15[256]; + +/** + * @brief 2-way tables for various activation functions + * + * 2-way table, H table for value larger than 1/4 + * L table for value smaller than 1/4, H table for remaining + * We have this only for the q15_t version. It does not make + * sense to have it for q7_t type + */ +extern const q15_t sigmoidHTable_q15[192]; +extern const q15_t sigmoidLTable_q15[128]; + +#endif /* ARM_NN_TABLES_H */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Include/arm_nn_types.h b/benchmark/interface/Drivers/CMSIS/NN/Include/arm_nn_types.h new file mode 100644 index 00000000..6040d725 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Include/arm_nn_types.h @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2020-2022 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_types.h + * Description: Public header file to contain the CMSIS-NN structs for the + * TensorFlowLite micro compliant functions + * + * $Date: 22. Februari 2022 + * $Revision: V.2.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#ifndef _ARM_NN_TYPES_H +#define _ARM_NN_TYPES_H + +#include + +/** CMSIS-NN object to contain the width and height of a tile */ +typedef struct +{ + int32_t w; /**< Width */ + int32_t h; /**< Height */ +} cmsis_nn_tile; + +/** CMSIS-NN object used for the function context. */ +typedef struct +{ + void *buf; /**< Pointer to a buffer needed for the optimization */ + int32_t size; /**< Buffer size */ +} cmsis_nn_context; + +/** CMSIS-NN object to contain the dimensions of the tensors */ +typedef struct +{ + int32_t n; /**< Generic dimension to contain either the batch size or output channels. + Please refer to the function documentation for more information */ + int32_t h; /**< Height */ + int32_t w; /**< Width */ + int32_t c; /**< Input channels */ +} cmsis_nn_dims; + +/** CMSIS-NN object for the per-channel quantization parameters */ +typedef struct +{ + int32_t *multiplier; /**< Multiplier values */ + int32_t *shift; /**< Shift values */ +} cmsis_nn_per_channel_quant_params; + +/** CMSIS-NN object for the per-tensor quantization parameters */ +typedef struct +{ + int32_t multiplier; /**< Multiplier value */ + int32_t shift; /**< Shift value */ +} cmsis_nn_per_tensor_quant_params; + +/** CMSIS-NN object for the quantized Relu activation */ +typedef struct +{ + int32_t min; /**< Min value used to clamp the result */ + int32_t max; /**< Max value used to clamp the result */ +} cmsis_nn_activation; + +/** CMSIS-NN object for the convolution layer parameters */ +typedef struct +{ + int32_t input_offset; /**< Zero value for the input tensor */ + int32_t output_offset; /**< Zero value for the output tensor */ + cmsis_nn_tile stride; + cmsis_nn_tile padding; + cmsis_nn_tile dilation; + cmsis_nn_activation activation; +} cmsis_nn_conv_params; + +/** CMSIS-NN object for Depthwise convolution layer parameters */ +typedef struct +{ + int32_t input_offset; /**< Zero value for the input tensor */ + int32_t output_offset; /**< Zero value for the output tensor */ + int32_t ch_mult; /**< Channel Multiplier. ch_mult * in_ch = out_ch */ + cmsis_nn_tile stride; + cmsis_nn_tile padding; + cmsis_nn_tile dilation; + cmsis_nn_activation activation; +} cmsis_nn_dw_conv_params; +/** CMSIS-NN object for pooling layer parameters */ +typedef struct +{ + cmsis_nn_tile stride; + cmsis_nn_tile padding; + cmsis_nn_activation activation; +} cmsis_nn_pool_params; + +/** CMSIS-NN object for Fully Connected layer parameters */ +typedef struct +{ + int32_t input_offset; /**< Zero value for the input tensor */ + int32_t filter_offset; /**< Zero value for the filter tensor. Not used */ + int32_t output_offset; /**< Zero value for the output tensor */ + cmsis_nn_activation activation; +} cmsis_nn_fc_params; + +/** CMSIS-NN object for SVDF layer parameters */ +typedef struct +{ + int32_t rank; + int32_t input_offset; /**< Zero value for the input tensor */ + int32_t output_offset; /**< Zero value for the output tensor */ + cmsis_nn_activation input_activation; + cmsis_nn_activation output_activation; +} cmsis_nn_svdf_params; + +/** CMSIS-NN object for Softmax s16 layer parameters */ +typedef struct +{ + const int16_t *exp_lut; + const int16_t *one_by_one_lut; +} cmsis_nn_softmax_lut_s16; + +#endif // _ARM_NN_TYPES_H diff --git a/benchmark/interface/Drivers/CMSIS/NN/Include/arm_nnfunctions.h b/benchmark/interface/Drivers/CMSIS/NN/Include/arm_nnfunctions.h new file mode 100644 index 00000000..deaade78 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Include/arm_nnfunctions.h @@ -0,0 +1,2532 @@ +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nnfunctions.h + * Description: Public header file for CMSIS NN Library + * + * $Date: 19 April 2022 + * $Revision: V.9.0.0 + * + * Target Processor: Cortex-M CPUs + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS NN Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS NN software library, + * a collection of efficient neural network kernels developed to maximize the + * performance and minimize the memory footprint of neural networks on Cortex-M processor cores. + * + * The library is divided into a number of functions each covering a specific category: + * - Convolution Functions + * - Activation Functions + * - Fully-connected Layer Functions + * - SVDF Layer Functions + * - Pooling Functions + * - Softmax Functions + * - Basic math Functions + * + * The library has separate functions for operating on different weight and activation data + * types including 8-bit integers (q7_t) and 16-bit integers (q15_t). The descrition of the + * kernels are included in the function description. The implementation details are also + * described in this paper [1]. + * + * Supported Processors + * ------- + * CMSIS-NN targets Cortex-M processors with typically three different implementations for each function. Each + * targets a different group of processors. + * - Processors without SIMD capability (e.g, Cortex-M0) + * - Processors with DSP extention (e.g Cortex-M4) + * - Processors with MVE extension (e.g Cortex-M55) + * The right implementation is picked through feature flags and the user usually does not have to explicit set it. + * + * Function Classification + * -------- + * The functions can be classified into two segments + * - Legacy functions supporting ARM's internal symmetric quantization(8 bits). + * - Functions that support TensorFlow Lite framework with symmetric quantization(8 bits). + * + * The legacy functions can be identified with their suffix of _q7 or _q15 and are no new development is done there. + * The article in [2] describes in detail how to run a network using the legacy functions. + * + * The functions supporting TensorFlow Lite framework is identified by the _s8 suffix and can be invoked from TFL + * micro. The functions are bit exact to TensorFlow Lite. Refer to the TensorFlow's documentation in [3] on how to run + * a TensorFlow Lite model using optimized CMSIS-NN kernels. + * + * Block Diagram + * -------- + * \image html CMSIS-NN-OVERVIEW.PNG + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Pre-processor Macros + * ------------ + * + * Each library project have different pre-processor macros. + * + * - ARM_MATH_DSP: + * + * Define macro ARM_MATH_DSP, If the silicon supports DSP instructions(DSP extension). + * + * - ARM_MATH_MVEI: + * + * Define macro ARM_MATH_MVEI, If the silicon supports M-Profile Vector Extension. + + * - ARM_MATH_AUTOVECTORIZE + * Used in conjucture with ARM_MATH_MVEI to let the compiler auto vectorize for the functions that uses inline + * assembly. It does not affect functions that use C or intrinsics. + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. This is supported only for the legacy + * functions i.e, functions targetted at TensorFlow Lite do not support big endianness. By default library builds for + * little endian targets. + * + * - ARM_NN_TRUNCATE: + * + * Define macro ARM_NN_TRUNCATE to use floor instead of round-to-the-nearest-int for the computation. + * + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2019 Arm Limited. All rights reserved. + * + * [1] CMSIS-NN: Efficient Neural Network Kernels for Arm Cortex-M CPUs https://arxiv.org/abs/1801.06601 + * + * [2] Converting a Neural Network for Arm Cortex-M with CMSIS-NN + * + https://developer.arm.com/solutions/machine-learning-on-arm/developer-material/how-to-guides/converting-a-neural-network-for-arm-cortex-m-with-cmsis-nn/single-page + * [3] https://www.tensorflow.org/lite/microcontrollers/library + * + * [4] https://github.com/ARM-software/CMSIS_5/tree/develop/CMSIS/NN#legacy-vs-tfl-micro-compliant-apis + */ + +/** + * @defgroup groupNN Neural Network Functions + * A collection of functions to perform basic operations for neural network layers. Functions with a _s8 suffix support + * TensorFlow Lite framework. + */ + +#ifndef _ARM_NNFUNCTIONS_H +#define _ARM_NNFUNCTIONS_H + +#include "arm_nn_math_types.h" +#include "arm_nn_types.h" + +#define USE_INTRINSIC + +//#define ARM_NN_TRUNCATE /* This config the rounding model to floor or round to the nearest int */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Struct for specifying activation function types + * + */ +typedef enum +{ + ARM_SIGMOID = 0, + /**< Sigmoid activation function */ + ARM_TANH = 1, + /**< Tanh activation function */ +} arm_nn_activation_type; + +/** + * @defgroup NNConv Convolution Functions + * + * Collection of convolution, depthwise convolution functions and their variants. + * + * The convolution is implemented in 2 steps: im2col and GEMM + * + * im2col is a process of converting each patch of image data into + * a column. After im2col, the convolution is computed as matrix-matrix + * multiplication. + * + * To reduce the memory footprint, the im2col is performed partially. + * Each iteration, only a few column (i.e., patches) are generated and + * computed with GEMM kernels similar to CMSIS-DSP arm_mat_mult functions. + * + */ + +/** + * @brief s8 convolution layer wrapper function with the main purpose to call the optimal kernel available in + cmsis-nn + * to perform the convolution. + * + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + arm_convolve_wrapper_s8_get_buffer_size will return the buffer_size if required + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * Range of conv_params->input_offset : [-127, 128] + * Range of conv_params->output_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the + * spatial filter dimensions + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int8 + * + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH if argument constraints fail. or, + * ARM_MATH_SUCCESS on successful completion. + * + */ +arm_status arm_convolve_wrapper_s8(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for arm_convolve_wrapper_s8 + * + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * Range of conv_params->input_offset : [-127, 128] + * Range of conv_params->output_offset : [-128, 127] + * @param[in] input_dims Input (activation) dimensions. Format: [N, H, W, C_IN] + * @param[in] filter_dims Filter dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the spatial + * filter dimensions + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * + * @return The function returns required buffer size(bytes) + * + */ +int32_t arm_convolve_wrapper_s8_get_buffer_size(const cmsis_nn_conv_params *conv_params, + const cmsis_nn_dims *input_dims, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims); + +/** + * @brief s16 convolution layer wrapper function with the main purpose to call the optimal kernel available in + cmsis-nn + * to perform the convolution. + * + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + arm_convolve_wrapper_s8_get_buffer_size will return the buffer_size if required + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * conv_params->input_offset : Not used + * conv_params->output_offset : Not used + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int16 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the + * spatial filter dimensions + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Bias data pointer. Data type: int64 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int16 + * + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH if argument constraints fail. or, + * ARM_MATH_SUCCESS on successful completion. + * + */ +arm_status arm_convolve_wrapper_s16(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data); + +/** + * @brief Get the required buffer size for arm_convolve_wrapper_s16 + * + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * conv_params->input_offset : Not used + * conv_params->output_offset : Not used + * @param[in] input_dims Input (activation) dimensions. Format: [N, H, W, C_IN] + * @param[in] filter_dims Filter dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the spatial + * filter dimensions + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * + * @return The function returns required buffer size(bytes) + * + */ +int32_t arm_convolve_wrapper_s16_get_buffer_size(const cmsis_nn_conv_params *conv_params, + const cmsis_nn_dims *input_dims, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims); + +/** + * @brief Basic s8 convolution function + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + arm_convolve_s8_get_buffer_size will return the buffer_size if required + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * Range of conv_params->input_offset : [-127, 128] + * Range of conv_params->output_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the + * spatial filter dimensions + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Optional bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int8 + + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * 1. Supported framework: TensorFlow Lite micro + * 2. q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + * 3. Additional memory is required for optimization. Refer to argument 'ctx' for details. + * + */ +arm_status arm_convolve_s8(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for s8 convolution function + * + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK + * are the spatial filter dimensions + * @return The function returns required buffer size(bytes) + * + */ +int32_t arm_convolve_s8_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims); + +/** + * @brief Basic s16 convolution function + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + arm_convolve_s16_get_buffer_size will return the buffer_size if required + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * conv_params->input_offset : Not used + * conv_params->output_offset : Not used + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int16 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the + * spatial filter dimensions + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Optional bias data pointer. Data type: int64 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int16 + + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * 1. Supported framework: TensorFlow Lite micro + * 2. q7/q15 is used as data type eventhough it is s8/s16 data. It is done so to be consistent with existing APIs. + * 3. Additional memory is required for optimization. Refer to argument 'ctx' for details. + * + */ +arm_status arm_convolve_s16(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data); +/** + * @brief Optimized s16 convolution function + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + arm_convolve_fast_s16_get_buffer_size will return the buffer_size if required + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * conv_params->input_offset : Not used + * conv_params->output_offset : Not used + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int16 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the + * spatial filter dimensions. (filter_dims->w * filter_dims->h * input_dims->c) must not + exceed 512 + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Optional bias data pointer. Data type: int64 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int16 + + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * 1. Supported framework: TensorFlow Lite micro + * 2. q7/q15 is used as data type eventhough it is s8/s16 data. It is done so to be consistent with existing APIs. + * 3. Additional memory is required for optimization. Refer to argument 'ctx' for details. + * 4. Implementation supports kernel volumes (filter width * filter height * input channels) < 512. + * + */ + +arm_status arm_convolve_fast_s16(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data); + +/** + * @brief Get the required buffer size for s16 convolution function + * + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK + * are the spatial filter dimensions + * @return The function returns required buffer size(bytes) + * + */ +int32_t arm_convolve_s16_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims); + +/** + * @brief Get the required buffer size for fast s16 convolution function + * + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK + * are the spatial filter dimensions + * @return The function returns required buffer size(bytes) + * + */ +int32_t arm_convolve_fast_s16_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims); + +/** + * @brief Basic Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + * + */ +arm_status arm_convolve_HWC_q7_basic(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Basic Q7 convolution function (non-square shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + */ +arm_status arm_convolve_HWC_q7_basic_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Basic Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + * + */ +arm_status arm_convolve_HWC_q15_basic(const q15_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ +arm_status arm_convolve_HWC_q7_fast(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ + +arm_status arm_convolve_HWC_q7_fast_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast Q7 version of 1x1 convolution (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH if argument constraints fail. or, + * ARM_MATH_SUCCESS on successful completion. + * + * This function implement convolution with 1x1 kernel size (i.e., dim_kernel_x=1 + * and dim_kernel_y=1). It can be used for + * second half of MobileNets after depthwise separable convolution. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ +arm_status arm_convolve_1x1_HWC_q7_fast_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast s8 version for 1x1 convolution (non-square shape) + * + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + arm_convolve_1x1_s8_fast_get_buffer_size will return the buffer_size if required + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * Range of conv_params->input_offset : [-127, 128] + * Range of conv_params->output_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, 1, 1, C_IN] + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Optional bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int8 + * + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH if argument constraints fail. or, + * ARM_MATH_SUCCESS on successful completion. + * + * @details + * - Supported framework : TensorFlow Lite Micro + * - The following constrains on the arguments apply + * -# input_dims->c is a multiple of 4 + * -# conv_params->padding.w = conv_params->padding.h = 0 + * -# conv_params->stride.w = conv_params->stride.h = 1 + * + */ +arm_status arm_convolve_1x1_s8_fast(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for arm_convolve_1x1_s8_fast + * + * @param[in] input_dims Input (activation) dimensions + * @return The function returns the required buffer size in bytes + * + */ +int32_t arm_convolve_1x1_s8_fast_get_buffer_size(const cmsis_nn_dims *input_dims); + +/** + * @brief 1xn convolution + * + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + arm_convolve_1_x_n_s8_get_buffer_size will return the buffer_size if required + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * Range of conv_params->input_offset : [-127, 128] + * Range of conv_params->output_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, 1, WK, C_IN] where WK is the horizontal + * spatial filter dimension + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Optional bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int8 + * + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH if argument constraints fail. or, + * ARM_MATH_SUCCESS on successful completion. + * + * @details + * - Supported framework : TensorFlow Lite Micro + * - The following constrains on the arguments apply + * -# input_dims->n equals 1 + * -# ouput_dims->w is a multiple of 4 + * -# Explicit constraints(since it is for 1xN convolution) + * -## input_dims->h equals 1 + * -## output_dims->h equals 1 + * -## filter_dims->h equals 1 + *@todo Remove constraint on output_dims->w to make the function generic. + * + */ +arm_status arm_convolve_1_x_n_s8(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required additional buffer size for 1xn convolution + * + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, 1, WK, C_IN] where WK is the + * horizontal spatial filter dimension + * @return The function returns required buffer size(bytes) + * + */ +int32_t arm_convolve_1_x_n_s8_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims); + +/** + * @brief Q7 version of convolution for RGB image + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This kernel is written exclusively for convolution with ch_im_in + * equals 3. This applies on the first layer of CNNs which has input + * image with RGB format. + */ + +arm_status arm_convolve_HWC_q7_RGB(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + * dim_im_out is a multiple of 2 + */ + +arm_status arm_convolve_HWC_q15_fast(const q15_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast Q15 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 2 + * + * ch_im_out is multipe of 2 + * + */ + +arm_status arm_convolve_HWC_q15_fast_nonsquare(const q15_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Q7 depthwise separable convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + */ + +arm_status arm_depthwise_separable_conv_HWC_q7(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Q7 depthwise separable convolution function (non-square shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding sizes x + * @param[in] padding_y padding sizes y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + */ +arm_status arm_depthwise_separable_conv_HWC_q7_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Wrapper function to pick the right optimized s8 depthwise convolution function + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if required. + * @param[in] dw_conv_params Depthwise convolution parameters (e.g. strides, dilations, pads,...) + * dw_conv_params->dilation is not used. + * Range of dw_conv_params->input_offset : [-127, 128] + * Range of dw_conv_params->output_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each + * output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Batch argument N is not used and assumed to be 1. + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in, out] output_data Output data pointer. Data type: int8 + * @return The function returns + * ARM_MATH_SUCCESS - Successful completion. + * + * @details + * - Supported framework: TensorFlow Lite + * - Picks one of the the following functions + * -# arm_depthwise_conv_s8() + * -# arm_depthwise_conv_3x3_s8() - Cortex-M CPUs with DSP extension only + * -# arm_depthwise_conv_s8_opt() + * - q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + * - Check details of arm_depthwise_conv_s8_opt() for potential data that can be accessed outside of the + * boundary. + */ +arm_status arm_depthwise_conv_wrapper_s8(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get size of additional buffer required by arm_depthwise_conv_wrapper_s8() + * + * @param[in] dw_conv_params Depthwise convolution parameters (e.g. strides, dilations, pads,...) + * dw_conv_params->dilation is not used. + * Range of dw_conv_params->input_offset : [-127, 128] + * Range of dw_conv_params->input_offset : [-128, 127] + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Batch argument N is not used and assumed to be 1. + * @param[in] filter_dims Filter tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in] output_dims Output tensor dimensions. Format: [1, H, W, C_OUT] + * @return Size of additional memory required for optimizations in bytes. + * + */ +int32_t arm_depthwise_conv_wrapper_s8_get_buffer_size(const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_dims *input_dims, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims); + +/** + * @brief Basic s8 depthwise convolution function that doesn't have any constraints on the input dimensions. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * exists if additional memory is. + * @param[in] dw_conv_params Depthwise convolution parameters (e.g. strides, dilations, pads,...) + * dw_conv_params->dilation is not used. + * Range of dw_conv_params->input_offset : [-127, 128] + * Range of dw_conv_params->input_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each + * output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * Batch argument N is not used. + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[in, out] output_data Output data pointer. Data type: int8 + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * - Supported framework: TensorFlow Lite + * - q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + */ +arm_status arm_depthwise_conv_s8(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Basic s16 depthwise convolution function that doesn't have any constraints on the input dimensions. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * exists if additional memory is. + * @param[in] dw_conv_params Depthwise convolution parameters (e.g. strides, dilations, pads,...) + * conv_params->input_offset : Not used + * conv_params->output_offset : Not used + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each + * output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * Batch argument N is not used. + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Bias data pointer. Data type: int64 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[in, out] output_data Output data pointer. Data type: int16 + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * - Supported framework: TensorFlow Lite + * - q15 is used as data type eventhough it is s16 data. It is done so to be consistent with existing APIs. + */ +arm_status arm_depthwise_conv_s16(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data); + +/** + * @brief Optimized s8 depthwise convolution function for 3x3 kernel size with some constraints on + * the input arguments(documented below). Refer arm_depthwise_conv_s8() for function + * argument details. + * + * @return The function returns one of the following + * ARM_MATH_SIZE_MISMATCH - Unsupported dimension of tensors + * ARM_MATH_ARGUMENT_ERROR - Unsupported pad size along the x axis + * ARM_MATH_SUCCESS - Successful operation + * + * @details + * - Supported framework : TensorFlow Lite Micro + * - The following constrains on the arguments apply + * -# Number of input channel equals number of output channels + * -# Filter height and width equals 3 + * -# Padding along x is either 0 or 1. + * + */ +arm_status arm_depthwise_conv_3x3_s8(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Optimized s8 depthwise convolution function with constraint that in_channel equals out_channel. + * Refer arm_depthwise_conv_s8() for function argument details. + * + * @return The function returns one of the following + * ARM_MATH_SIZE_MISMATCH - input channel != output channel or + * ch_mult != 1 + * ARM_MATH_SUCCESS - Successful operation + * + * @note If number of channels is not a multiple of 4, upto 3 elements outside the boundary will be read out + * for the following if MVE optimizations(Arm Helium Technology) are used. + * - Output shift + * - Output multiplier + * - Output bias + * - kernel + * @details + * - Supported framework: TensorFlow Lite + * - The following constrains on the arguments apply + * -# Number of input channel equals number of output channels or ch_mult equals 1 + * - q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + * - Reccomended when number of channels is 4 or greater. + * + */ +arm_status arm_depthwise_conv_s8_opt(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for optimized s8 depthwise convolution + * function with constraint that in_channel equals out_channel. + * @param[in] input_dims Input (activation) tensor dimensions. Format: [1, H, W, C_IN] + * Batch argument N is not used. + * @param[in] filter_dims Filter tensor dimensions. Format: [1, H, W, C_OUT] + * @return The function returns required buffer size in bytes + * + */ +int32_t arm_depthwise_conv_s8_opt_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims); + +/** + * @defgroup FC Fully-connected Layer Functions + * + * Collection of fully-connected and matrix multiplication functions. + * + * Fully-connected layer is basically a matrix-vector multiplication + * with bias. The matrix is the weights and the input/output vectors + * are the activation values. Supported {weight, activation} precisions + * include {8-bit, 8-bit}, {16-bit, 16-bit}, and {8-bit, 16-bit}. + * + * Here we have two types of kernel functions. The basic function + * implements the function using regular GEMV approach. The opt functions + * operates with weights in interleaved formats. + * + */ + +/** + *@brief Q7 basic fully-connected layer function + *@param[in] pV pointer to input vector + *@param[in] pM pointer to matrix weights + *@param[in] dim_vec length of the vector + *@param[in] num_of_rows number of rows in weight matrix + *@param[in] bias_shift amount of left-shift for bias + *@param[in] out_shift amount of right-shift for output + *@param[in] bias pointer to bias + *@param[in,out] pOut pointer to output vector + *@param[in,out] vec_buffer pointer to buffer space for input + *@return The function returns ARM_MATH_SUCCESS + * + */ + +arm_status arm_fully_connected_q7(const q7_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Basic s8 Fully Connected function. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * @param[in] fc_params Fully Connected layer parameters. + * Range of fc_params->input_offset : [-127, 128] + * fc_params->filter_offset : 0 + * Range of fc_params->output_offset : [-128, 127] + * @param[in] quant_params Per-tensor quantization info. + * It contains the multiplier and shift values to be applied to the output tensor. + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * Input dimension is taken as Nx(H * W * C_IN) + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Two dimensional filter dimensions. Format: [N, C] + * N : accumulation depth and equals (H * W * C_IN) from input_dims + * C : output depth and equals C_OUT in output_dims + * H & W : Not used + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * N, H, W : Not used + * @param[in] bias_data Bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, C_OUT] + * N : Batches + * C_OUT : Output depth + * H & W : Not used. + * @param[in, out] output_data Output data pointer. Data type: int8 + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * - Supported framework: TensorFlow Lite + * - q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + */ +arm_status arm_fully_connected_s8(const cmsis_nn_context *ctx, + const cmsis_nn_fc_params *fc_params, + const cmsis_nn_per_tensor_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for S8 basic fully-connected and + * matrix multiplication layer function for TF Lite + * @param[in] filter_dims dimension of filter + * @return The function returns required buffer size in bytes + * + */ +int32_t arm_fully_connected_s8_get_buffer_size(const cmsis_nn_dims *filter_dims); + +/** + * @brief Basic s16 Fully Connected function. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * @param[in] fc_params Fully Connected layer parameters. + * fc_params->input_offset : 0 + * fc_params->filter_offset : 0 + * fc_params->output_offset : 0 + * @param[in] quant_params Per-tensor quantization info. + * It contains the multiplier and shift values to be applied to the output tensor. + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * Input dimension is taken as Nx(H * W * C_IN) + * @param[in] input_data Input (activation) data pointer. Data type: int16 + * @param[in] filter_dims Two dimensional filter dimensions. Format: [N, C] + * N : accumulation depth and equals (H * W * C_IN) from input_dims + * C : output depth and equals C_OUT in output_dims + * H & W : Not used + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * N, H, W : Not used + * @param[in] bias_data Bias data pointer. Data type: int64 + * @param[in] output_dims Output tensor dimensions. Format: [N, C_OUT] + * N : Batches + * C_OUT : Output depth + * H & W : Not used. + * @param[in, out] output_data Output data pointer. Data type: int16 + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * - Supported framework: TensorFlow Lite + * - q15 is used as data type eventhough it is s16 data. It is done so to be consistent with existing APIs. + */ +arm_status arm_fully_connected_s16(const cmsis_nn_context *ctx, + const cmsis_nn_fc_params *fc_params, + const cmsis_nn_per_tensor_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data); + +/** + * @brief Get the required buffer size for S16 basic fully-connected and + * matrix multiplication layer function for TF Lite + * @param[in] filter_dims dimension of filter + * @return The function returns required buffer size in bytes + * + */ +int32_t arm_fully_connected_s16_get_buffer_size(const cmsis_nn_dims *filter_dims); + +/** + * @brief Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + */ + +arm_status arm_fully_connected_q7_opt(const q7_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Q15 basic fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + */ + +arm_status arm_fully_connected_q15(const q15_t *pV, + const q15_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t *bias, + q15_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Q15 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + */ + +arm_status arm_fully_connected_q15_opt(const q15_t *pV, + const q15_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t *bias, + q15_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Mixed Q15-Q7 fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + */ + +arm_status arm_fully_connected_mat_q7_vec_q15(const q15_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q15_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Mixed Q15-Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + */ + +arm_status arm_fully_connected_mat_q7_vec_q15_opt(const q15_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q15_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Matrix-Multiplication Kernels for Convolution + * + * These functions are used within convolution layer functions for + * matrix multiplication. + * + * The implementation is similar to CMSIS-DSP arm_mat_mult functions + * with one Q7 and one Q15 operands. The Q15 operand is the im2col + * output which is always with 2 columns. + * + */ + +/** + * @brief Matrix-multiplication function for convolution + * @param[in] pA pointer to operand A + * @param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + * @param[in] ch_im_out numRow of A + * @param[in] numCol_A numCol of A + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias the bias + * @param[in,out] pOut pointer to output + * @return The function returns the incremented output pointer + */ + +q7_t *arm_nn_mat_mult_kernel_q7_q15(const q7_t *pA, + const q15_t *pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut); + +#ifdef __cplusplus +} +#endif + +/* + * Other functions + * These layers are typically not timing critical + * Basic implementation is supported here + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup BasicMath Basic math functions + * + * Elementwise add and multiplication functions. + * + */ + +/** + * @brief s8 elementwise add of two vectors + * @param[in] input_1_vect pointer to input vector 1 + * @param[in] input_2_vect pointer to input vector 2 + * @param[in] input_1_offset offset for input 1. Range: -127 to 128 + * @param[in] input_1_mult multiplier for input 1 + * @param[in] input_1_shift shift for input 1 + * @param[in] input_2_offset offset for input 2. Range: -127 to 128 + * @param[in] input_2_mult multiplier for input 2 + * @param[in] input_2_shift shift for input 2 + * @param[in] left_shift input left shift + * @param[in,out] output pointer to output vector + * @param[in] out_offset output offset. Range: -128 to 127 + * @param[in] out_mult output multiplier + * @param[in] out_shift output shift + * @param[in] out_activation_min minimum value to clamp output to. Min: -128 + * @param[in] out_activation_max maximum value to clamp output to. Max: 127 + * @param[in] block_size number of samples + * @return The function returns ARM_MATH_SUCCESS + */ +arm_status arm_elementwise_add_s8(const int8_t *input_1_vect, + const int8_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_1_mult, + const int32_t input_1_shift, + const int32_t input_2_offset, + const int32_t input_2_mult, + const int32_t input_2_shift, + const int32_t left_shift, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const int32_t block_size); + +/** + * @brief s16 elementwise add of two vectors + * @param[in] input_1_vect pointer to input vector 1 + * @param[in] input_2_vect pointer to input vector 2 + * @param[in] input_1_offset offset for input 1. Not used. + * @param[in] input_1_mult multiplier for input 1 + * @param[in] input_1_shift shift for input 1 + * @param[in] input_2_offset offset for input 2. Not used. + * @param[in] input_2_mult multiplier for input 2 + * @param[in] input_2_shift shift for input 2 + * @param[in] left_shift input left shift + * @param[in,out] output pointer to output vector + * @param[in] out_offset output offset. Not used. + * @param[in] out_mult output multiplier + * @param[in] out_shift output shift + * @param[in] out_activation_min minimum value to clamp output to. Min: -32768 + * @param[in] out_activation_max maximum value to clamp output to. Max: 32767 + * @param[in] block_size number of samples + * @return The function returns ARM_MATH_SUCCESS + */ +arm_status arm_elementwise_add_s16(const int16_t *input_1_vect, + const int16_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_1_mult, + const int32_t input_1_shift, + const int32_t input_2_offset, + const int32_t input_2_mult, + const int32_t input_2_shift, + const int32_t left_shift, + int16_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const int32_t block_size); + +/** + * @brief s8 elementwise multiplication + * @param[in] input_1_vect pointer to input vector 1 + * @param[in] input_2_vect pointer to input vector 2 + * @param[in] input_1_offset offset for input 1. Range: -127 to 128 + * @param[in] input_2_offset offset for input 2. Range: -127 to 128 + * @param[in,out] output pointer to output vector + * @param[in] out_offset output offset. Range: -128 to 127 + * @param[in] out_mult output multiplier + * @param[in] out_shift output shift + * @param[in] out_activation_min minimum value to clamp output to. Min: -128 + * @param[in] out_activation_max maximum value to clamp output to. Max: 127 + * @param[in] block_size number of samples + * @return The function returns ARM_MATH_SUCCESS + * + * @details Supported framework: TensorFlow Lite micro + */ +arm_status arm_elementwise_mul_s8(const int8_t *input_1_vect, + const int8_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_2_offset, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const int32_t block_size); + +/** + * @brief s16 elementwise multiplication + * @param[in] input_1_vect pointer to input vector 1 + * @param[in] input_2_vect pointer to input vector 2 + * @param[in] input_1_offset offset for input 1. Not used. + * @param[in] input_2_offset offset for input 2. Not used. + * @param[in,out] output pointer to output vector + * @param[in] out_offset output offset. Not used. + * @param[in] out_mult output multiplier + * @param[in] out_shift output shift + * @param[in] out_activation_min minimum value to clamp output to. Min: -32768 + * @param[in] out_activation_max maximum value to clamp output to. Max: 32767 + * @param[in] block_size number of samples + * @return The function returns ARM_MATH_SUCCESS + * + * @details Supported framework: TensorFlow Lite micro + */ +arm_status arm_elementwise_mul_s16(const int16_t *input_1_vect, + const int16_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_2_offset, + int16_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const int32_t block_size); + +/** + * @defgroup Acti Activation Functions + * + * Perform activation layers, including ReLU (Rectified Linear Unit), + * sigmoid and tanh + * + */ + +/** + * @brief Q7 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @return none. + */ + +void arm_relu_q7(q7_t *data, uint16_t size); + +/** + * @brief s8 ReLU6 function + * @param[in,out] data pointer to input + * @param[in] size number of elements + */ + +void arm_relu6_s8(q7_t *data, uint16_t size); + +/** + * @brief Q15 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @return none. + */ + +void arm_relu_q15(q15_t *data, uint16_t size); + +/** + * @brief Q7 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * @return none. + */ + +void arm_nn_activations_direct_q7(q7_t *data, uint16_t size, uint16_t int_width, arm_nn_activation_type type); + +/** + * @brief Q15 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * @return none. + * + * @details + * + * This is the direct table look-up approach. + * + * Assume here the integer part of the fixed-point is <= 3. + * More than 3 just not making much sense, makes no difference with + * saturation followed by any of these activation functions. + */ + +void arm_nn_activations_direct_q15(q15_t *data, uint16_t size, uint16_t int_width, arm_nn_activation_type type); + +/** + * @defgroup Pooling Pooling Functions + * + * Perform pooling functions, including max pooling and average pooling + * + */ + +/** + * @brief Q7 max pooling function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * @return none. + * + */ + +void arm_maxpool_q7_HWC(q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const uint16_t dim_im_out, + q7_t *bufferA, + q7_t *Im_out); + +/** + * @brief Q7 average pooling function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * @return none. + * + */ + +void arm_avepool_q7_HWC(q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const uint16_t dim_im_out, + q7_t *bufferA, + q7_t *Im_out); + +/** + * @brief s8 average pooling function. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * @param[in] pool_params Pooling parameters + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Argument 'N' is not used. + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [H, W] + * Argument N and C are not used. + * @param[in] output_dims Output tensor dimensions. Format: [H, W, C_OUT] + * Argument N is not used. + * C_OUT equals C_IN. + * @param[in, out] output_data Output data pointer. Data type: int8 + * @return The function returns + * ARM_MATH_SUCCESS - Successful operation + * + * @details + * - Supported Framework: TensorFlow Lite + * + */ +arm_status arm_avgpool_s8(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for S8 average pooling function + * @param[in] dim_dst_width output tensor dimension + * @param[in] ch_src number of input tensor channels + * @return The function returns required buffer size in bytes + * + */ +int32_t arm_avgpool_s8_get_buffer_size(const int dim_dst_width, const int ch_src); + +/** + * @brief s16 average pooling function. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * @param[in] pool_params Pooling parameters + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Argument 'N' is not used. + * @param[in] input_data Input (activation) data pointer. Data type: int16 + * @param[in] filter_dims Filter tensor dimensions. Format: [H, W] + * Argument N and C are not used. + * @param[in] output_dims Output tensor dimensions. Format: [H, W, C_OUT] + * Argument N is not used. + * C_OUT equals C_IN. + * @param[in, out] output_data Output data pointer. Data type: int16 + * @return The function returns + * ARM_MATH_SUCCESS - Successful operation + * + * @details + * - Supported Framework: TensorFlow Lite + * + */ +arm_status arm_avgpool_s16(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const int16_t *input_data, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + int16_t *output_data); + +/** + * @brief Get the required buffer size for S16 average pooling function + * @param[in] dim_dst_width output tensor dimension + * @param[in] ch_src number of input tensor channels + * @return The function returns required buffer size in bytes + * + */ +int32_t arm_avgpool_s16_get_buffer_size(const int dim_dst_width, const int ch_src); + +/** + * @brief s8 max pooling function. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * @param[in] pool_params Pooling parameters + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Argument 'N' is not used. + * @param[in] input_data Input (activation) data pointer. The input tensor must not + * overlap with the output tensor. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [H, W] + * Argument N and C are not used. + * @param[in] output_dims Output tensor dimensions. Format: [H, W, C_OUT] + * Argument N is not used. + * C_OUT equals C_IN. + * @param[in, out] output_data Output data pointer. Data type: int8 + * @return The function returns + * ARM_MATH_SUCCESS - Successful operation + * + * @details + * - Supported Framework: TensorFlow Lite + * + */ +arm_status arm_max_pool_s8(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief s16 max pooling function. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * @param[in] pool_params Pooling parameters + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Argument 'N' is not used. + * @param[in] src Input (activation) data pointer. The input tensor must not + * overlap with the output tensor. Data type: int16 + * @param[in] filter_dims Filter tensor dimensions. Format: [H, W] + * Argument N and C are not used. + * @param[in] output_dims Output tensor dimensions. Format: [H, W, C_OUT] + * Argument N is not used. + * C_OUT equals C_IN. + * @param[in, out] dst Output data pointer. Data type: int16 + * @return The function returns + * ARM_MATH_SUCCESS - Successful operation + * + * @details + * - Supported Framework: TensorFlow Lite + * + */ +arm_status arm_max_pool_s16(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const int16_t *src, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + int16_t *dst); + +/** + * @defgroup Softmax Softmax Functions + * + * EXP(2) based softmax functions. + * + */ + +/** + * @brief Q7 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimension + * @param[out] p_out pointer to output vector + * + * @note This function is an optimized version which is not bit-accurate with + * TensorFlow Lite's kernel + * + */ + +void arm_softmax_q7(const q7_t *vec_in, const uint16_t dim_vec, q7_t *p_out); + +/** + * @brief Q7 softmax function with batch parameter + * @param[in] vec_in pointer to input vector + * @param[in] nb_batches number of batches + * @param[in] dim_vec input vector dimension + * @param[out] p_out pointer to output vector + * @return none. + * + * @note This function is an optimized version which is not bit-accurate with + * TensorFlow Lite's kernel + * + */ + +void arm_softmax_with_batch_q7(const q7_t *vec_in, const uint16_t nb_batches, const uint16_t dim_vec, q7_t *p_out); +/** + * @brief Q15 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimension + * @param[out] p_out pointer to output vector + * @return none. + * + * @note This function is an optimized version which is not bit-accurate with + * TensorFlow Lite's kernel + * + */ + +void arm_softmax_q15(const q15_t *vec_in, const uint16_t dim_vec, q15_t *p_out); + +/** + * @brief S8 softmax function + * @param[in] input Pointer to the input tensor + * @param[in] num_rows Number of rows in the input tensor + * @param[in] row_size Number of elements in each input row + * @param[in] mult Input quantization multiplier + * @param[in] shift Input quantization shift within the range [0, 31] + * @param[in] diff_min Minimum difference with max in row. Used to check if + * the quantized exponential operation can be performed + * @param[out] output Pointer to the output tensor + * + * @note Supported framework: TensorFlow Lite micro (bit-accurate) + * + */ +void arm_softmax_s8(const int8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + int8_t *output); + +/** + * @brief S8 to s16 softmax function + * @param[in] input Pointer to the input tensor + * @param[in] num_rows Number of rows in the input tensor + * @param[in] row_size Number of elements in each input row + * @param[in] mult Input quantization multiplier + * @param[in] shift Input quantization shift within the range [0, 31] + * @param[in] diff_min Minimum difference with max in row. Used to check if + * the quantized exponential operation can be performed + * @param[out] output Pointer to the output tensor + * + * @note Supported framework: TensorFlow Lite micro (bit-accurate) + * + */ +void arm_softmax_s8_s16(const int8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + int16_t *output); + +/** + * @brief S16 softmax function + * @param[in] input Pointer to the input tensor + * @param[in] num_rows Number of rows in the input tensor + * @param[in] row_size Number of elements in each input row + * @param[in] mult Input quantization multiplier + * @param[in] shift Input quantization shift within the range [0, 31] + * @param[in] softmax_params Softmax s16 layer parameters with two pointers to LUTs speficied below. + * For indexing the high 9 bits are used and 7 remaining for interpolation. + * That means 512 entries for the 9-bit indexing and 1 extra for interpolation, i.e. 513 + * values for each LUT. + * - Lookup table for exp(x), where x uniform distributed between [-10.0 , 0.0] + * - Lookup table for 1 / (1 + x), where x uniform distributed between [0.0 , 1.0] + * @param[out] output Pointer to the output tensor + * @return The function returns + * ARM_MATH_ARGUMENT_ERROR if LUTs are NULL + * ARM_MATH_SUCCESS - Successful operation + * + * @note Supported framework: TensorFlow Lite micro (bit-accurate) + * + */ +arm_status arm_softmax_s16(const int16_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const cmsis_nn_softmax_lut_s16 *softmax_params, + int16_t *output); + +/** + * @brief U8 softmax function + * @param[in] input Pointer to the input tensor + * @param[in] num_rows Number of rows in the input tensor + * @param[in] row_size Number of elements in each input row + * @param[in] mult Input quantization multiplier + * @param[in] shift Input quantization shift within the range [0, 31] + * @param[in] diff_min Minimum difference with max in row. Used to check if + * the quantized exponential operation can be performed + * @param[out] output Pointer to the output tensor + * + * @note Supported framework: TensorFlow Lite micro (bit-accurate) + * + */ + +void arm_softmax_u8(const uint8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + uint8_t *output); + +/** + * @brief uint8 depthwise convolution function with asymmetric quantization + * Unless specified otherwise, arguments are mandatory. + * + * @param[in] input Pointer to input tensor + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_ch Channels in input tensor + * @param[in] kernel Pointer to kernel weights + * @param[in] kernel_x Width of kernel + * @param[in] kernel_y Height of kernel + * @param[in] ch_mult Number of channel multiplier + * @param[in] pad_x Padding sizes x + * @param[in] pad_y Padding sizes y + * @param[in] stride_x stride along the width + * @param[in] stride_y stride along the height + * @param[in] dilation_x Dilation along width. Not used and intended for future enhancement. + * @param[in] dilation_y Dilation along height. Not used and intended for future enhancement. + * @param[in] bias Pointer to optional bias values. If no bias is + * availble, NULL is expected + * @param[in] input_offset Input tensor zero offset + * @param[in] filter_offset Kernel tensor zero offset + * @param[in] output_offset Output tensor zero offset + * @param[in,out] output Pointer to output tensor + * @param[in] output_x Width of output tensor + * @param[in] output_y Height of output tensor + * @param[in] output_activation_min Minimum value to clamp the output to. Range : {0, 255} + * @param[in] output_activation_max Minimum value to clamp the output to. Range : {0, 255} + * @param[in] out_shift Amount of right-shift for output + * @param[in] out_mult Output multiplier for requantization + * @return The function returns the following + * ARM_MATH_SUCCESS - Successful operation + * + */ +arm_status arm_depthwise_conv_u8_basic_ver1(const uint8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_ch, + const uint8_t *kernel, + const uint16_t kernel_x, + const uint16_t kernel_y, + const int16_t ch_mult, + const int16_t pad_x, + const int16_t pad_y, + const int16_t stride_x, + const int16_t stride_y, + const int16_t dilation_x, + const int16_t dilation_y, + const int32_t *bias, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_offset, + uint8_t *output, + const uint16_t output_x, + const uint16_t output_y, + const int32_t output_activation_min, + const int32_t output_activation_max, + const int32_t out_shift, + const int32_t out_mult); + +/** + * @defgroup Reshape Reshape Functions + * + */ + +/** + * @brief Reshape a s8 vector into another with different shape + * @param[in] input points to the s8 input vector + * @param[out] output points to the s8 output vector + * @param[in] total_size total size of the input and output vectors in bytes + * + * @note The output is expected to be in a memory area that does not overlap with the input's + * + */ +void arm_reshape_s8(const int8_t *input, int8_t *output, const uint32_t total_size); + +/** + * @defgroup Concatenation Concatenation Functions + * + */ + +/** + * @brief int8/uint8 concatenation function to be used for concatenating N-tensors along the X axis + * This function should be called for each input tensor to concatenate. The argument offset_x + * will be used to store the input tensor in the correct position in the output tensor + * + * i.e. offset_x = 0 + * for(i = 0 i < num_input_tensors; ++i) + * { + * arm_concatenation_s8_x(&input[i], ..., &output, ..., ..., offset_x) + * offset_x += input_x[i] + * } + * + * This function assumes that the output tensor has: + * -# The same height of the input tensor + * -# The same number of channels of the input tensor + * -# The same batch size of the input tensor + * + * Unless specified otherwise, arguments are mandatory. + * + * @note This function, data layout independent, can be used to concatenate either int8 or uint8 tensors because it + * does not involve any arithmetic operation + * + * @param[in] input Pointer to input tensor. Input tensor must not overlap with the output tensor. + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_z Channels in input tensor + * @param[in] input_w Batch size in input tensor + * @param[out] output Pointer to output tensor. Expected to be at least + * (input_x * input_y * input_z * input_w) + offset_x + * bytes. + * @param[in] output_x Width of output tensor + * @param[in] offset_x The offset (in number of elements) on the X axis to start concatenating the input tensor + * It is user responsibility to provide the correct value + * + * Input constraints + * offset_x is less than output_x + * + */ +void arm_concatenation_s8_x(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_x, + const uint32_t offset_x); + +/** + * @brief int8/uint8 concatenation function to be used for concatenating N-tensors along the Y axis + * This function should be called for each input tensor to concatenate. The argument offset_y + * will be used to store the input tensor in the correct position in the output tensor + * + * i.e. offset_y = 0 + * for(i = 0 i < num_input_tensors; ++i) + * { + * arm_concatenation_s8_y(&input[i], ..., &output, ..., ..., offset_y) + * offset_y += input_y[i] + * } + * + * This function assumes that the output tensor has: + * -# The same width of the input tensor + * -# The same number of channels of the input tensor + * -# The same batch size of the input tensor + * + * Unless specified otherwise, arguments are mandatory. + * + * @note This function, data layout independent, can be used to concatenate either int8 or uint8 tensors because it + * does not involve any arithmetic operation + * + * @param[in] input Pointer to input tensor. Input tensor must not overlap with the output tensor. + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_z Channels in input tensor + * @param[in] input_w Batch size in input tensor + * @param[out] output Pointer to output tensor. Expected to be at least + * (input_z * input_w * input_x * input_y) + offset_y + * bytes. + * @param[in] output_y Height of output tensor + * @param[in] offset_y The offset on the Y axis to start concatenating the input tensor + * It is user responsibility to provide the correct value + * + * Input constraints + * offset_y is less than output_y + * + */ +void arm_concatenation_s8_y(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_y, + const uint32_t offset_y); + +/** + * @brief int8/uint8 concatenation function to be used for concatenating N-tensors along the Z axis + * This function should be called for each input tensor to concatenate. The argument offset_z + * will be used to store the input tensor in the correct position in the output tensor + * + * i.e. offset_z = 0 + * for(i = 0 i < num_input_tensors; ++i) + * { + * arm_concatenation_s8_z(&input[i], ..., &output, ..., ..., offset_z) + * offset_z += input_z[i] + * } + * + * This function assumes that the output tensor has: + * -# The same width of the input tensor + * -# The same height of the input tensor + * -# The same batch size of the input tensor + * + * Unless specified otherwise, arguments are mandatory. + * + * @note This function, data layout independent, can be used to concatenate either int8 or uint8 tensors because it + * does not involve any arithmetic operation + * + * @param[in] input Pointer to input tensor. Input tensor must not overlap with output tensor. + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_z Channels in input tensor + * @param[in] input_w Batch size in input tensor + * @param[out] output Pointer to output tensor. Expected to be at least + * (input_x * input_y * input_z * input_w) + offset_z + * bytes. + * @param[in] output_z Channels in output tensor + * @param[in] offset_z The offset on the Z axis to start concatenating the input tensor + * It is user responsibility to provide the correct value + * + * Input constraints + * offset_z is less than output_z + * + */ +void arm_concatenation_s8_z(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_z, + const uint32_t offset_z); + +/** + * @brief int8/uint8 concatenation function to be used for concatenating N-tensors along the W axis (Batch size) + * This function should be called for each input tensor to concatenate. The argument offset_w + * will be used to store the input tensor in the correct position in the output tensor + * + * i.e. offset_w = 0 + * for(i = 0 i < num_input_tensors; ++i) + * { + * arm_concatenation_s8_w(&input[i], ..., &output, ..., ..., offset_w) + * offset_w += input_w[i] + * } + * + * This function assumes that the output tensor has: + * -# The same width of the input tensor + * -# The same height of the input tensor + * -# The same number o channels of the input tensor + * + * Unless specified otherwise, arguments are mandatory. + * + * @note This function, data layout independent, can be used to concatenate either int8 or uint8 tensors because it + * does not involve any arithmetic operation + * + * @param[in] input Pointer to input tensor + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_z Channels in input tensor + * @param[in] input_w Batch size in input tensor + * @param[out] output Pointer to output tensor. Expected to be at least + * input_x * input_y * input_z * input_w + * bytes. + * @param[in] offset_w The offset on the W axis to start concatenating the input tensor + * It is user responsibility to provide the correct value + * + */ +void arm_concatenation_s8_w(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint32_t offset_w); +/** + * @defgroup SVDF SVDF Layer Functions + * + */ + +/** + * @brief s8 SVDF function with 8 bit state tensor and 8 bit time weights + * + * @param[in] input_ctx Temporary scratch buffer + * @param[in] output_ctx Temporary output scratch buffer + * @param[in] svdf_params SVDF Parameters + * Range of svdf_params->input_offset : [-128, 127] + * Range of svdf_params->output_offset : [-128, 127] + * @param[in] input_quant_params Input quantization parameters + * @param[in] output_quant_params Output quantization parameters + * @param[in] input_dims Input tensor dimensions + * @param[in] input_data Pointer to input tensor + * @param[in] state_dims State tensor dimensions + * @param[in] state_data Pointer to state tensor + * @param[in] weights_feature_dims Weights (feature) tensor dimensions + * @param[in] weights_feature_data Pointer to the weights (feature) tensor + * @param[in] weights_time_dims Weights (time) tensor dimensions + * @param[in] weights_time_data Pointer to the weights (time) tensor + * @param[in] bias_dims Bias tensor dimensions + * @param[in] bias_data Pointer to bias tensor + * @param[in] output_dims Output tensor dimensions + * @param[out] output_data Pointer to the output tensor + * + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * 1. Supported framework: TensorFlow Lite micro + * 2. q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + * + */ +arm_status arm_svdf_s8(const cmsis_nn_context *input_ctx, + const cmsis_nn_context *output_ctx, + const cmsis_nn_svdf_params *svdf_params, + const cmsis_nn_per_tensor_quant_params *input_quant_params, + const cmsis_nn_per_tensor_quant_params *output_quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *state_dims, + q7_t *state_data, + const cmsis_nn_dims *weights_feature_dims, + const q7_t *weights_feature_data, + const cmsis_nn_dims *weights_time_dims, + const q7_t *weights_time_data, + const cmsis_nn_dims *bias_dims, + const q31_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief s8 SVDF function with 16 bit state tensor and 16 bit time weights + * + * @param[in] input_ctx Temporary scratch buffer + * @param[in] output_ctx Temporary output scratch buffer + * @param[in] svdf_params SVDF Parameters + * Range of svdf_params->input_offset : [-128, 127] + * Range of svdf_params->output_offset : [-128, 127] + * @param[in] input_quant_params Input quantization parameters + * @param[in] output_quant_params Output quantization parameters + * @param[in] input_dims Input tensor dimensions + * @param[in] input_data Pointer to input tensor + * @param[in] state_dims State tensor dimensions + * @param[in] state_data Pointer to state tensor + * @param[in] weights_feature_dims Weights (feature) tensor dimensions + * @param[in] weights_feature_data Pointer to the weights (feature) tensor + * @param[in] weights_time_dims Weights (time) tensor dimensions + * @param[in] weights_time_data Pointer to the weights (time) tensor + * @param[in] bias_dims Bias tensor dimensions + * @param[in] bias_data Pointer to bias tensor + * @param[in] output_dims Output tensor dimensions + * @param[out] output_data Pointer to the output tensor + * + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * 1. Supported framework: TensorFlow Lite micro + * 2. q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + * + */ +arm_status arm_svdf_state_s16_s8(const cmsis_nn_context *input_ctx, + const cmsis_nn_context *output_ctx, + const cmsis_nn_svdf_params *svdf_params, + const cmsis_nn_per_tensor_quant_params *input_quant_params, + const cmsis_nn_per_tensor_quant_params *output_quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *state_dims, + q15_t *state_data, + const cmsis_nn_dims *weights_feature_dims, + const q7_t *weights_feature_data, + const cmsis_nn_dims *weights_time_dims, + const q15_t *weights_time_data, + const cmsis_nn_dims *bias_dims, + const q31_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/benchmark/interface/Drivers/CMSIS/NN/Include/arm_nnsupportfunctions.h b/benchmark/interface/Drivers/CMSIS/NN/Include/arm_nnsupportfunctions.h new file mode 100644 index 00000000..4b505640 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Include/arm_nnsupportfunctions.h @@ -0,0 +1,1186 @@ +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nnsupportfunctions.h + * Description: Public header file of support functions for CMSIS NN Library + * + * $Date: 19. April 2022 + * $Revision: V.7.0.1 + * + * Target Processor: Cortex-M CPUs + * -------------------------------------------------------------------- */ + +#ifndef _ARM_NNSUPPORTFUNCTIONS_H_ +#define _ARM_NNSUPPORTFUNCTIONS_H_ + +#include "arm_nn_math_types.h" +#include "arm_nn_types.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define LEFT_SHIFT(_shift) (_shift > 0 ? _shift : 0) +#define RIGHT_SHIFT(_shift) (_shift > 0 ? 0 : -_shift) +#define MASK_IF_ZERO(x) (x) == 0 ? ~0 : 0 +#define MASK_IF_NON_ZERO(x) (x) != 0 ? ~0 : 0 +#define SELECT_USING_MASK(mask, a, b) ((mask) & (a)) ^ (~(mask) & (b)) + +#define MAX(A, B) ((A) > (B) ? (A) : (B)) +#define MIN(A, B) ((A) < (B) ? (A) : (B)) +#define CLAMP(x, h, l) MAX(MIN((x), (h)), (l)) +#define REDUCE_MULTIPLIER(_mult) ((_mult < 0x7FFF0000) ? ((_mult + (1 << 15)) >> 16) : 0x7FFF) + +/** + * @brief definition to pack four 8 bit values. + */ +#define PACK_Q7x4_32x1(v0, v1, v2, v3) \ + ((((int32_t)(v0) << 0) & (int32_t)0x000000FF) | (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | (((int32_t)(v3) << 24) & (int32_t)0xFF000000)) + +/** + * @brief Union for SIMD access of q31/q15/q7 types + */ +union arm_nnword +{ + q31_t word; + /**< q31 type */ + q15_t half_words[2]; + /**< q15 type */ + q7_t bytes[4]; + /**< q7 type */ +}; + +/** + * @brief Union for data type long long + */ +struct arm_nn_double +{ + uint32_t low; + int32_t high; +}; + +union arm_nn_long_long +{ + int64_t long_long; + struct arm_nn_double word; +}; + +/** + * @defgroup nndata_convert Neural Network Data Conversion Functions + * + * Perform data type conversion in-between neural network operations + * + */ + +/** + * @brief Converts the elements of the q7 vector to q15 vector without left-shift + * @param[in] *pSrc points to the q7 input vector + * @param[out] *pDst points to the q15 output vector + * @param[in] blockSize length of the input vector + * + */ +void arm_q7_to_q15_no_shift(const q7_t *pSrc, q15_t *pDst, uint32_t blockSize); + +/** + * @brief Non-saturating addition of elements of a q7 vector + * @param[in] *input Pointer to the q7 input vector + * @param[out] *output Pointer to the q31 output variable. + * @param[in] block_size length of the input vector + * \par Description: + * + * 2^24 samples can be added without saturating the result. + * + * The equation used for the conversion process is: + * + *
+ *  sum = input[0] + input[1] + .. + input[block_size -1]
+ * 
+ * + * */ +void arm_nn_add_q7(const q7_t *input, q31_t *output, uint32_t block_size); + +/** + * @brief Converts the elements of the q7 vector to reordered q15 vector without left-shift + * @param[in] *pSrc points to the q7 input vector + * @param[out] *pDst points to the q15 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + */ +void arm_q7_to_q15_reordered_no_shift(const q7_t *pSrc, q15_t *pDst, uint32_t blockSize); + +/** + * @brief Converts the elements from a q7 vector to a q15 vector with an added offset + * @param[in] src pointer to the q7 input vector + * @param[out] dst pointer to the q15 output vector + * @param[in] block_size length of the input vector + * @param[in] offset q7 offset to be added to each input vector element. + * + * \par Description: + * + * The equation used for the conversion process is: + * + *
+ *  dst[n] = (q15_t) src[n] + offset;   0 <= n < block_size.
+ * 
+ * + */ +void arm_q7_to_q15_with_offset(const q7_t *src, q15_t *dst, uint32_t block_size, q15_t offset); + +/** + * @brief Converts the elements of the q7 vector to reordered q15 vector with an added offset + * @param[in] src pointer to the q7 input vector + * @param[out] dst pointer to the q15 output vector + * @param[in] block_size length of the input vector + * @param[in] offset offset to be added to each input vector element. + * @return none. + * + * @details This function does the q7 to q15 expansion with re-ordering of bytes. Re-ordering is a consequence of + * the sign extension intrinsic(DSP extension). The tail (i.e., last (N % 4) elements) retains its + * original order. + * + */ +void arm_q7_to_q15_reordered_with_offset(const q7_t *src, q15_t *dst, uint32_t block_size, q15_t offset); + +/** + * @brief Converts the elements from a q7 vector and accumulate to a q15 vector + * @param[in] *src points to the q7 input vector + * @param[out] *dst points to the q15 output vector + * @param[in] block_size length of the input vector + * + * \par Description: + * + * The equation used for the conversion process is: + * + *
+ *  dst[n] += (q15_t) src[n] ;   0 <= n < block_size.
+ * 
+ * + */ +void arm_nn_accumulate_q7_to_q15(q15_t *dst, const q7_t *src, uint32_t block_size); + +/** + * @brief Depthwise conv on an im2col buffer where the input channel equals output channel. + * @param[in] row pointer to row + * @param[in] col pointer to im2col buffer, always consists of 2 columns. + * @param[in] num_ch number of channels + * @param[in] out_shift pointer to per output channel requantization shift parameter. + * @param[in] out_mult pointer to per output channel requantization multiplier parameter. + * @param[in] out_offset output tensor offset. + * @param[in] activation_min minimum value to clamp the output to. Range : int8 + * @param[in] activation_max maximum value to clamp the output to. Range : int8 + * @param[in] kernel_size number of elements in one column. + * @param[in] output_bias per output channel bias. Range : int32 + * @param[out] out pointer to output + * @return The function returns one of the two + * 1. The incremented output pointer for a successful operation or + * 2. NULL if implementation is not available. + * + * @details Supported framework: TensorFlow Lite micro. + */ +q7_t *arm_nn_depthwise_conv_s8_core(const q7_t *row, + const q15_t *col, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t kernel_size, + const int32_t *const output_bias, + q7_t *out); + +/** + * @brief General Matrix-multiplication function with per-channel requantization. + * @param[in] input_row pointer to row operand + * @param[in] input_col pointer to col operand + * @param[in] output_ch number of rows of input_row + * @param[in] col_batches number of column batches. Range: 1 to 4 + * @param[in] output_shift pointer to per output channel requantization shift parameter. + * @param[in] output_mult pointer to per output channel requantization multiplier parameter. + * @param[in] out_offset output tensor offset. + * @param[in] col_offset input tensor(col) offset. + * @param[in] row_offset kernel offset(row). Not used. + * @param[in] out_activation_min minimum value to clamp the output to. Range : int8 + * @param[in] out_activation_max maximum value to clamp the output to. Range : int8 + * @param[in] row_len number of elements in each row + * @param[in] bias per output channel bias. Range : int32 + * @param[in,out] out pointer to output + * @return The function returns one of the two + * 1. The incremented output pointer for a successful operation or + * 2. NULL if implementation is not available. + * + * @details Supported framework: TensorFlow Lite + */ +q7_t *arm_nn_mat_mult_s8(const q7_t *input_row, + const q7_t *input_col, + const uint16_t output_ch, + const uint16_t col_batches, + const int32_t *output_shift, + const int32_t *output_mult, + const int32_t out_offset, + const int32_t col_offset, + const int32_t row_offset, + const int16_t out_activation_min, + const int16_t out_activation_max, + const uint16_t row_len, + const int32_t *const bias, + q7_t *out); +/** + * @brief Matrix-multiplication function for convolution with per-channel requantization for 16 bits convolution. + * @param[in] input_a pointer to operand A + * @param[in] input_b pointer to operand B, always consists of 2 vectors. + * @param[in] output_ch number of rows of A + * @param[in] out_shift pointer to per output channel requantization shift parameter. + * @param[in] out_mult pointer to per output channel requantization multiplier parameter. + * @param[in] activation_min minimum value to clamp the output to. Range : int16 + * @param[in] activation_max maximum value to clamp the output to. Range : int16 + * @param[in] num_col_a number of columns of A + * @param[in] output_bias per output channel bias. Range : int64 + * @param[in,out] out_0 pointer to output + * @return The function returns one of the two + * 1. The incremented output pointer for a successful operation or + * 2. NULL if implementation is not available. + * + * @details This function does the matrix multiplication of weight matrix for all output channels + * with 2 columns from im2col and produces two elements/output_channel. The outputs are + * clamped in the range provided by activation min and max. + * Supported framework: TensorFlow Lite micro. + */ +q15_t *arm_nn_mat_mult_kernel_s16(const q7_t *input_a, + const q15_t *input_b, + const int32_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int16_t activation_min, + const int16_t activation_max, + const int32_t num_col_a, + const int64_t *const output_bias, + q15_t *out_0); +/** + * @brief General Matrix-multiplication without requantization for one row & one column + * @param[in] row_elements number of row elements + * @param[in] row_base pointer to row operand + * @param[in] col_base pointer to col operand + * @param[out] sum_col pointer to store sum of column elements + * @param[out] output pointer to store result of multiply-accumulate + * @return The function returns the multiply-accumulated result of the row by column. + * + * @details Pseudo-code + * *output = 0 + * sum_col = 0 + * for (i = 0; i < row_elements; i++) + * *output += row_base[i] * col_base[i] + * sum_col += col_base[i] + * + */ +arm_status arm_nn_mat_mul_core_1x_s8(int32_t row_elements, + const int8_t *row_base, + const int8_t *col_base, + int32_t *const sum_col, + int32_t *const output); + +/** + * @brief Matrix-multiplication with requantization & activation function for four rows and one column + * @param[in] row_elements number of row elements + * @param[in] offset offset between rows. Can be the same as row_elements. + * For e.g, in a 1x1 conv scenario with stride as 1. + * @param[in] row_base pointer to row operand + * @param[in] col_base pointer to col operand + * @param[in] out_ch Number of output channels + * @param[in] conv_params Pointer to convolution parameters like offsets and activation values + * @param[in] quant_params Pointer to per-channel quantization parameters + * @param[in] bias Pointer to per-channel bias + * @param[out] output Pointer to output where int8 results are stored. + * + * @return The function returns the updated output pointer or NULL if implementation is not available. + * + * @details Compliant to TFLM int8 specification. MVE implementation only + */ +int8_t *arm_nn_mat_mul_core_4x_s8(const int32_t row_elements, + const int32_t offset, + const int8_t *row_base, + const int8_t *col_base, + const int32_t out_ch, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const int32_t *bias, + int8_t *output); + +/** + * @brief General Matrix-multiplication function with per-channel requantization. + * This function assumes: + * - LHS input matrix NOT transposed (nt) + * - RHS input matrix transposed (t) + * + * @note This operation also performs the broadcast bias addition before the requantization + * + * @param[in] lhs Pointer to the LHS input matrix + * @param[in] rhs Pointer to the RHS input matrix + * @param[in] bias Pointer to the bias vector. The length of this vector is equal to the number of + * output columns (or RHS input rows) + * @param[out] dst Pointer to the output matrix with "m" rows and "n" columns + * @param[in] dst_multipliers Pointer to the multipliers vector needed for the per-channel requantization. + * The length of this vector is equal to the number of output columns (or RHS input + * rows) + * @param[in] dst_shifts Pointer to the shifts vector needed for the per-channel requantization. The length + * of this vector is equal to the number of output columns (or RHS input rows) + * @param[in] lhs_rows Number of LHS input rows + * @param[in] rhs_rows Number of RHS input rows + * @param[in] rhs_cols Number of LHS/RHS input columns + * @param[in] lhs_offset Offset to be applied to the LHS input value + * @param[in] dst_offset Offset to be applied the output result + * @param[in] activation_min Minimum value to clamp down the output. Range : int8 + * @param[in] activation_max Maximum value to clamp up the output. Range : int8 + * + * @return The function returns ARM_MATH_SUCCESS + * + */ +arm_status arm_nn_mat_mult_nt_t_s8(const q7_t *lhs, + const q7_t *rhs, + const q31_t *bias, + q7_t *dst, + const int32_t *dst_multipliers, + const int32_t *dst_shifts, + const int32_t lhs_rows, + const int32_t rhs_rows, + const int32_t rhs_cols, + const int32_t lhs_offset, + const int32_t dst_offset, + const int32_t activation_min, + const int32_t activation_max); + +/** + * @brief s8 Vector by Matrix (transposed) multiplication + * + * @param[in] lhs Input left-hand side vector + * @param[in] rhs Input right-hand side matrix (transposed) + * @param[in] bias Input bias + * @param[out] dst Output vector + * @param[in] lhs_offset Offset to be added to the input values of the left-hand side vector. + * Range: -127 to 128 + * @param[in] rhs_offset Not used + * @param[in] dst_offset Offset to be added to the output values. Range: -127 to 128 + * @param[in] dst_multiplier Output multiplier + * @param[in] dst_shift Output shift + * @param[in] rhs_cols Number of columns in the right-hand side input matrix + * @param[in] rhs_rows Number of rows in the right-hand side input matrix + * @param[in] activation_min Minimum value to clamp the output to. Range: int8 + * @param[in] activation_max Maximum value to clamp the output to. Range: int8 + * @param[in] address_offset Memory position offset for dst. First output is stored at 'dst', the + * second at 'dst + address_offset' and so on. Default value is typically 1. + * + * @return The function returns ARM_MATH_SUCCESS + * + */ +arm_status arm_nn_vec_mat_mult_t_s8(const q7_t *lhs, + const q7_t *rhs, + const q31_t *bias, + q7_t *dst, + const int32_t lhs_offset, + const int32_t rhs_offset, + const int32_t dst_offset, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max, + const int32_t address_offset); + +/** + * @brief s16 Vector by Matrix (transposed) multiplication + * + * @param[in] lhs Input left-hand side vector + * @param[in] rhs Input right-hand side matrix (transposed) + * @param[in] bias Input bias + * @param[out] dst Output vector + * @param[in] dst_multiplier Output multiplier + * @param[in] dst_shift Output shift + * @param[in] rhs_cols Number of columns in the right-hand side input matrix + * @param[in] rhs_rows Number of rows in the right-hand side input matrix + * @param[in] activation_min Minimum value to clamp the output to. Range: int16 + * @param[in] activation_max Maximum value to clamp the output to. Range: int16 + * + * @return The function returns ARM_MATH_SUCCESS + * + */ +arm_status arm_nn_vec_mat_mult_t_s16(const q15_t *lhs, + const q7_t *rhs, + const q63_t *bias, + q15_t *dst, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max); + +/** + * @brief s8 Vector by Matrix (transposed) multiplication with s16 output + * + * @param[in] lhs Input left-hand side vector + * @param[in] rhs Input right-hand side matrix (transposed) + * @param[out] dst Output vector + * @param[in] lhs_offset Offset to be added to the input values of the left-hand side + * vector. Range: -127 to 128 + * @param[in] rhs_offset Not used + * @param[in] scatter_offset Address offset for dst. First output is stored at 'dst', the + * second at 'dst + scatter_offset' and so on. + * @param[in] dst_multiplier Output multiplier + * @param[in] dst_shift Output shift + * @param[in] rhs_cols Number of columns in the right-hand side input matrix + * @param[in] rhs_rows Number of rows in the right-hand side input matrix + * @param[in] activation_min Minimum value to clamp the output to. Range: int16 + * @param[in] activation_max Maximum value to clamp the output to. Range: int16 + * + * @return The function returns ARM_MATH_SUCCESS + * + */ +arm_status arm_nn_vec_mat_mult_t_svdf_s8(const q7_t *lhs, + const q7_t *rhs, + q15_t *dst, + const int32_t lhs_offset, + const int32_t rhs_offset, + const int32_t scatter_offset, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max); + +/** + * @brief Depthwise convolution of transposed rhs matrix with 4 lhs matrices. To be used in padded cases where + * the padding is -lhs_offset(Range: int8). Dimensions are the same for lhs and rhs. + * + * @param[in] lhs Input left-hand side matrix + * @param[in] rhs Input right-hand side matrix (transposed) + * @param[in] lhs_offset LHS matrix offset(input offset). Range: -127 to 128 + * @param[in] num_ch Number of channels in LHS/RHS + * @param[in] out_shift Per channel output shift. Length of vector is equal to number of channels + * @param[in] out_mult Per channel output multiplier. Length of vector is equal to number of channels + * @param[in] out_offset Offset to be added to the output values. Range: -127 to 128 + * @param[in] activation_min Minimum value to clamp the output to. Range: int8 + * @param[in] activation_max Maximum value to clamp the output to. Range: int8 + * @param[in] row_x_col (row_dimension * col_dimension) of LHS/RHS matrix + * @param[in] output_bias Per channel output bias. Length of vector is equal to number of channels + * @param[in] out Output pointer + * + * @return The function returns one of the two + * - Updated output pointer if an implementation is available + * - NULL if no implementation is available. + * + * @note If number of channels is not a multiple of 4, upto 3 elements outside the boundary will be read + * out for the following. + * - Output shift + * - Output multiplier + * - Output bias + * - rhs + */ +q7_t *arm_nn_depthwise_conv_nt_t_padded_s8(const q7_t *lhs, + const q7_t *rhs, + const int32_t lhs_offset, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t row_x_col, + const int32_t *const output_bias, + q7_t *out); + +/** + * @brief Depthwise convolution of transposed rhs matrix with 4 lhs matrices. To be used in non-padded cases. + * Dimensions are the same for lhs and rhs. + * + * @param[in] lhs Input left-hand side matrix + * @param[in] rhs Input right-hand side matrix (transposed) + * @param[in] lhs_offset LHS matrix offset(input offset). Range: -127 to 128 + * @param[in] num_ch Number of channels in LHS/RHS + * @param[in] out_shift Per channel output shift. Length of vector is equal to number of channels. + * @param[in] out_mult Per channel output multiplier. Length of vector is equal to number of channels. + * @param[in] out_offset Offset to be added to the output values. Range: -127 to 128 + * @param[in] activation_min Minimum value to clamp the output to. Range: int8 + * @param[in] activation_max Maximum value to clamp the output to. Range: int8 + * @param[in] row_x_col (row_dimension * col_dimension) of LHS/RHS matrix + * @param[in] output_bias Per channel output bias. Length of vector is equal to number of channels. + * @param[in] out Output pointer + * + * @return The function returns one of the two + * - Updated output pointer if an implementation is available + * - NULL if no implementation is available. + * + * @note If number of channels is not a multiple of 4, upto 3 elements outside the boundary will be read + * out for the following. + * - Output shift + * - Output multiplier + * - Output bias + * - rhs + */ +q7_t *arm_nn_depthwise_conv_nt_t_s8(const q7_t *lhs, + const q7_t *rhs, + const int32_t lhs_offset, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t row_x_col, + const int32_t *const output_bias, + q7_t *out); + +/** + *@brief Matrix-multiplication function for convolution with reordered columns + *@param[in] pA pointer to operand A + *@param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + *@param[in] ch_im_out numRow of A + *@param[in] numCol_A numCol of A + *@param[in] bias_shift amount of left-shift for bias + *@param[in] out_shift amount of right-shift for output + *@param[in] bias the bias + *@param[in,out] pOut pointer to output + *@return The function returns the incremented output pointer + * + *@details This function assumes that data in pInBuffer are reordered + */ +q7_t *arm_nn_mat_mult_kernel_q7_q15_reordered(const q7_t *pA, + const q15_t *pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut); + +/** + @brief Read 2 q15 elements and post increment pointer. + @param[in] in_q15 Pointer to pointer that holds address of input. + @return q31 value + */ +__STATIC_FORCEINLINE q31_t arm_nn_read_q15x2_ia(const q15_t **in_q15) +{ + q31_t val; + + memcpy(&val, *in_q15, 4); + *in_q15 += 2; + + return (val); +} + +/** + @brief Read 4 q7 from q7 pointer and post increment pointer. + @param[in] in_q7 Pointer to pointer that holds address of input. + @return q31 value + */ +__STATIC_FORCEINLINE q31_t arm_nn_read_q7x4_ia(const q7_t **in_q7) +{ + q31_t val; + memcpy(&val, *in_q7, 4); + *in_q7 += 4; + + return (val); +} + +/** + @brief Read 2 q15 from q15 pointer. + @param[in] in_q15 pointer to address of input. + @return q31 value + */ +__STATIC_FORCEINLINE q31_t arm_nn_read_q15x2(const q15_t *in_q15) +{ + q31_t val; + memcpy(&val, in_q15, 4); + + return (val); +} + +/** + @brief Read 4 q7 values. + @param[in] in_q7 pointer to address of input. + @return q31 value + */ +__STATIC_FORCEINLINE q31_t arm_nn_read_q7x4(const q7_t *in_q7) +{ + q31_t val; + memcpy(&val, in_q7, 4); + + return (val); +} + +/** + @brief Write four q7 to q7 pointer and increment pointer afterwards. + @param[in] in Double pointer to input value + @param[in] value Four bytes to copy + */ +__STATIC_FORCEINLINE void arm_nn_write_q7x4_ia(q7_t **in, q31_t value) +{ + memcpy(*in, &value, 4); + *in += 4; +} + +/** + * @brief memset optimized for MVE + * @param[in, out] dst Destination pointer + * @param[in] val Value to set + * @param[in] block_size Number of bytes to copy. + * + */ +__STATIC_FORCEINLINE void arm_memset_q7(q7_t *dst, const q7_t val, uint32_t block_size) +{ +#if defined(ARM_MATH_MVEI) + __asm volatile(" vdup.8 q0, %[set_val] \n" + " wlstp.8 lr, %[cnt], 1f \n" + "2: \n" + " vstrb.8 q0, [%[in]], #16 \n" + " letp lr, 2b \n" + "1: \n" + : [ in ] "+r"(dst) + : [ cnt ] "r"(block_size), [ set_val ] "r"(val) + : "q0", "memory", "r14"); +#else + memset(dst, val, block_size); +#endif +} + +#if defined(ARM_MATH_DSP) + +/** + * @brief read and expand one q7 word into two q15 words + */ + +__STATIC_FORCEINLINE const q7_t *read_and_pad(const q7_t *source, q31_t *out1, q31_t *out2) +{ + q31_t inA = arm_nn_read_q7x4_ia(&source); + q31_t inAbuf1 = __SXTB16_RORn((uint32_t)inA, 8); + q31_t inAbuf2 = __SXTB16(inA); + +#ifndef ARM_MATH_BIG_ENDIAN + *out2 = (int32_t)(__PKHTB(inAbuf1, inAbuf2, 16)); + *out1 = (int32_t)(__PKHBT(inAbuf2, inAbuf1, 16)); +#else + *out1 = (int32_t)(__PKHTB(inAbuf1, inAbuf2, 16)); + *out2 = (int32_t)(__PKHBT(inAbuf2, inAbuf1, 16)); +#endif + + return source; +} + +/** + * @brief read and expand one q7 word into two q15 words with reordering + */ + +__STATIC_FORCEINLINE const q7_t *read_and_pad_reordered(const q7_t *source, q31_t *out1, q31_t *out2) +{ + q31_t inA = arm_nn_read_q7x4_ia(&source); +#ifndef ARM_MATH_BIG_ENDIAN + *out2 = __SXTB16(__ROR((uint32_t)inA, 8)); + *out1 = __SXTB16(inA); +#else + *out1 = __SXTB16(__ROR((uint32_t)inA, 8)); + *out2 = __SXTB16(inA); +#endif + + return source; +} + +/** + * @brief read and expand one q7 word into two q15 words with reordering and add an offset + */ +__STATIC_FORCEINLINE const q7_t * +read_and_pad_reordered_with_offset(const q7_t *source, q31_t *out1, q31_t *out2, q31_t offset) +{ + q31_t inA = arm_nn_read_q7x4_ia(&source); + +#ifndef ARM_MATH_BIG_ENDIAN + *out2 = __SXTB16(__ROR((uint32_t)inA, 8)); + *out1 = __SXTB16(inA); +#else + *out1 = __SXTB16(__ROR((uint32_t)inA, 8)); + *out2 = __SXTB16(inA); +#endif + *out1 = __QADD16(*out1, offset); + *out2 = __QADD16(*out2, offset); + + return source; +} + +#endif + +/** + * @defgroup NNBasicMath Basic Math Functions for Neural Network Computation + * + * Basic Math Functions for Neural Network Computation + * + */ + +/** + * @brief q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_nn_mult_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, const uint16_t out_shift, uint32_t blockSize); + +/** + * @brief q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable q7 range [0x80 0x7F] will be saturated. + */ + +void arm_nn_mult_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, const uint16_t out_shift, uint32_t blockSize); + +/** + * @brief Matrix-multiplication function for convolution with per-channel requantization. + * @param[in] input_a pointer to operand A + * @param[in] input_b pointer to operand B, always consists of 2 vectors. + * @param[in] output_ch number of rows of A + * @param[in] out_shift pointer to per output channel requantization shift parameter. + * @param[in] out_mult pointer to per output channel requantization multiplier parameter. + * @param[in] out_offset output tensor offset. + * @param[in] activation_min minimum value to clamp the output to. Range : int8 + * @param[in] activation_max maximum value to clamp the output to. Range : int8 + * @param[in] num_col_a number of columns of A + * @param[in] output_bias per output channel bias. Range : int32 + * @param[in,out] out_0 pointer to output + * @return The function returns one of the two + * 1. The incremented output pointer for a successful operation or + * 2. NULL if implementation is not available. + * + * @details This function does the matrix multiplication of weight matrix for all output channels + * with 2 columns from im2col and produces two elements/output_channel. The outputs are + * clamped in the range provided by activation min and max. + * Supported framework: TensorFlow Lite micro. + */ +q7_t *arm_nn_mat_mult_kernel_s8_s16(const q7_t *input_a, + const q15_t *input_b, + const uint16_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t num_col_a, + const int32_t *const output_bias, + q7_t *out_0); + +/** + * @brief Common softmax function for s8 input and s8 or s16 output + * @param[in] input Pointer to the input tensor + * @param[in] num_rows Number of rows in the input tensor + * @param[in] row_size Number of elements in each input row + * @param[in] mult Input quantization multiplier + * @param[in] shift Input quantization shift within the range [0, 31] + * @param[in] diff_min Minimum difference with max in row. Used to check if + * the quantized exponential operation can be performed + * @param[in] int16_output Indicating s8 output if 0 else s16 output + * @param[out] output Pointer to the output tensor + * + * @note Supported framework: TensorFlow Lite micro (bit-accurate) + * + */ +void arm_nn_softmax_common_s8(const int8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + const bool int16_output, + void *output); + +/** + * @brief macro for adding rounding offset + */ +#ifndef ARM_NN_TRUNCATE +#define NN_ROUND(out_shift) ((0x1 << out_shift) >> 1) +#else +#define NN_ROUND(out_shift) 0 +#endif + +// Macros for shortening quantization functions' names and avoid long lines +#define MUL_SAT(a, b) arm_nn_doubling_high_mult((a), (b)) +#define MUL_SAT_MVE(a, b) arm_doubling_high_mult_mve_32x4((a), (b)) +#define MUL_POW2(a, b) arm_nn_mult_by_power_of_two((a), (b)) + +#define DIV_POW2(a, b) arm_nn_divide_by_power_of_two((a), (b)) +#define DIV_POW2_MVE(a, b) arm_divide_by_power_of_two_mve((a), (b)) + +#define EXP_ON_NEG(x) arm_nn_exp_on_negative_values((x)) +#define ONE_OVER1(x) arm_nn_one_over_one_plus_x_for_x_in_0_1((x)) + +/** + * @brief Saturating doubling high multiply. Result matches + * NEON instruction VQRDMULH. + * @param[in] m1 Multiplicand. Range: {NN_Q31_MIN, NN_Q31_MAX} + * @param[in] m2 Multiplier. Range: {NN_Q31_MIN, NN_Q31_MAX} + * @return Result of multiplication. + * + */ +__STATIC_FORCEINLINE q31_t arm_nn_doubling_high_mult(const q31_t m1, const q31_t m2) +{ + q31_t result = 0; + // Rounding offset to add for a right shift of 31 + q63_t mult = 1 << 30; + + if ((m1 < 0) ^ (m2 < 0)) + { + mult = 1 - mult; + } + // Gets resolved as a SMLAL instruction + mult = mult + (q63_t)m1 * m2; + + // Utilize all of the upper 32 bits. This is the doubling step + // as well. + result = (int32_t)(mult / (1ll << 31)); + + if ((m1 == m2) && (m1 == (int32_t)NN_Q31_MIN)) + { + result = NN_Q31_MAX; + } + return result; +} + +/** + * @brief Doubling high multiply without saturation. This is intended + * for requantization where the scale is a positive integer + * + * @param[in] m1 Multiplicand. Range: {NN_Q31_MIN, NN_Q31_MAX} + * @param[in] m2 Multiplier Range: {NN_Q31_MIN, NN_Q31_MAX} + * @return Result of multiplication. + * @note The result of this matches that of neon instruction + * VQRDMULH for m1 in range {NN_Q31_MIN, NN_Q31_MAX} and m2 in + * range {NN_Q31_MIN + 1, NN_Q31_MAX}. Saturation occurs when + * m1 equals m2 equals NN_Q31_MIN and that is not handled by + * this function. + * + */ +__STATIC_FORCEINLINE q31_t arm_nn_doubling_high_mult_no_sat(const q31_t m1, const q31_t m2) +{ + q31_t result = 0; + union arm_nn_long_long mult; + + // Rounding offset to add for a right shift of 31 + mult.word.low = 1 << 30; + mult.word.high = 0; + + // Gets resolved as a SMLAL instruction + mult.long_long = mult.long_long + (q63_t)m1 * m2; + + // Utilize all of the upper 32 bits. This is the doubling step + // as well. + result = (int32_t)(mult.long_long >> 31); + + return result; +} + +/** + * @brief Rounding divide by power of two. + * @param[in] dividend - Dividend + * @param[in] exponent - Divisor = power(2, exponent) + * Range: [0, 31] + * @return Rounded result of division. Midpoint is rounded away from zero. + * + */ +__STATIC_FORCEINLINE q31_t arm_nn_divide_by_power_of_two(const q31_t dividend, const q31_t exponent) +{ + q31_t result = 0; + const q31_t remainder_mask = (1 << exponent) - 1; + int32_t remainder = remainder_mask & dividend; + + // Basic division + result = dividend >> exponent; + + // Adjust 'result' for rounding (mid point away from zero) + q31_t threshold = remainder_mask >> 1; + if (result < 0) + { + threshold++; + } + if (remainder > threshold) + { + result++; + } + + return result; +} + +/** + * @brief Requantize a given value. + * @param[in] val Value to be requantized + * @param[in] multiplier multiplier. Range {NN_Q31_MIN + 1, Q32_MAX} + * @param[in] shift left or right shift for 'val * multiplier' + * + * @return Returns (val * multiplier)/(2 ^ shift) + * + */ +__STATIC_FORCEINLINE q31_t arm_nn_requantize(const q31_t val, const q31_t multiplier, const q31_t shift) +{ +#ifdef CMSIS_NN_USE_SINGLE_ROUNDING + const int64_t total_shift = 31 - shift; + const int64_t new_val = val * (int64_t)multiplier; + + int32_t result = new_val >> (total_shift - 1); + result = (result + 1) >> 1; + + return result; +#else + return arm_nn_divide_by_power_of_two(arm_nn_doubling_high_mult_no_sat(val * (1 << LEFT_SHIFT(shift)), multiplier), + RIGHT_SHIFT(shift)); +#endif +} + +/** + * @brief Requantize a given 64 bit value. + * @param[in] val Value to be requantized in the range {-(1<<47)} to {(1<<47) - 1} + * @param[in] reduced_multiplier Reduced multiplier in the range {NN_Q31_MIN + 1, Q32_MAX} to {Q16_MIN + 1, + * Q16_MAX} + * @param[in] shift Left or right shift for 'val * multiplier' in the range {-31} to {7} + * + * @return Returns (val * multiplier)/(2 ^ shift) + * + */ +__STATIC_FORCEINLINE q31_t arm_nn_requantize_s64(const q63_t val, const q31_t reduced_multiplier, const q31_t shift) +{ + const q63_t new_val = val * reduced_multiplier; + + q31_t result = new_val >> (14 - shift); // 64->32 bit reduction + result = (result + 1) >> 1; // Last shift position and insert round + + return result; +} + +/** + * @brief memcpy optimized for MVE + * @param[in, out] dst Destination pointer + * @param[in] src Source pointer. + * @param[in] block_size Number of bytes to copy. + * + */ +__STATIC_FORCEINLINE void arm_memcpy_q7(q7_t *__RESTRICT dst, const q7_t *__RESTRICT src, uint32_t block_size) +{ +#if defined(ARM_MATH_MVEI) + __asm volatile(" wlstp.8 lr, %[cnt], 1f \n" + "2: \n" + " vldrb.8 q0, [%[in]], #16 \n" + " vstrb.8 q0, [%[out]], #16 \n" + " letp lr, 2b \n" + "1: \n" + : [ in ] "+r"(src), [ out ] "+r"(dst) + : [ cnt ] "r"(block_size) + : "q0", "memory", "r14"); +#else + memcpy(dst, src, block_size); +#endif +} + +#if defined(ARM_MATH_MVEI) +/** + * @brief Vector saturating doubling high multiply returning high half. + * @param[in] m1 Multiplicand + * @param[in] m2 Multiplier + * @return Result of multiplication. + * + */ +__STATIC_FORCEINLINE int32x4_t arm_doubling_high_mult_mve(const int32x4_t m1, const q31_t m2) +{ + return vqrdmulhq_n_s32(m1, m2); +} + +/** + * @brief Vector rounding divide by power of two. + * @param[in] dividend - Dividend vector + * @param[in] exponent - Divisor = power(2, exponent) + * Range: [0, 31] + * @return Rounded result of division. Midpoint is rounded away from zero. + * + */ +__STATIC_FORCEINLINE int32x4_t arm_divide_by_power_of_two_mve(const int32x4_t dividend, const q31_t exponent) +{ + const int32x4_t shift = vdupq_n_s32(-exponent); + const int32x4_t fixup = vshrq_n_s32(vandq_s32(dividend, shift), 31); + const int32x4_t fixed_up_dividend = vqaddq_s32(dividend, fixup); + return vrshlq_s32(fixed_up_dividend, shift); +} + +/** + * @brief Requantize a given vector. + * @param[in] val Vector to be requantized + * @param[in] multiplier multiplier + * @param[in] shift shift + * + * @return Returns (val * multiplier)/(2 ^ shift) + * + */ +__STATIC_FORCEINLINE int32x4_t arm_requantize_mve(const int32x4_t val, const q31_t multiplier, const q31_t shift) +{ +#ifdef CMSIS_NN_USE_SINGLE_ROUNDING + const int right_shift = MIN(-1, shift); + const int left_shift = shift - right_shift; + + const int32x4_t left_shift_dup = vdupq_n_s32(left_shift); + const int32x4_t right_shift_dup = vdupq_n_s32(right_shift); + + int32x4_t result = vqdmulhq_n_s32(vshlq_s32(val, left_shift_dup), multiplier); + result = vrshlq_s32(result, right_shift_dup); + + return result; +#else + return arm_divide_by_power_of_two_mve( + arm_doubling_high_mult_mve(vshlq_s32(val, vdupq_n_s32(LEFT_SHIFT(shift))), multiplier), RIGHT_SHIFT(shift)); +#endif +} + +__STATIC_FORCEINLINE int32x4_t arm_doubling_high_mult_mve_32x4(const int32x4_t m1, const int32x4_t m2) +{ + return vqrdmulhq_s32(m1, m2); +} + +__STATIC_FORCEINLINE int32x4_t arm_divide_by_power_of_two_mve_32x4(const int32x4_t dividend, const int32x4_t exponent) +{ + const int32x4_t shift = -exponent; + const int32x4_t fixup = vshrq_n_s32(vandq_s32(dividend, shift), 31); + const int32x4_t fixed_up_dividend = vqaddq_s32(dividend, fixup); + return vrshlq_s32(fixed_up_dividend, shift); +} + +__STATIC_FORCEINLINE int32x4_t arm_requantize_mve_32x4(const int32x4_t val, + const int32x4_t multiplier, + const int32x4_t shift) +{ +#ifdef CMSIS_NN_USE_SINGLE_ROUNDING + const int32x4_t right_shift = vminq_s32(vdupq_n_s32(-1), shift); + const int32x4_t left_shift = vqsubq_s32(shift, right_shift); + + int32x4_t result = vqdmulhq_s32(vshlq_s32(val, left_shift), multiplier); + result = vrshlq_s32(result, right_shift); + + return result; +#else + const int32x4_t zz = vdupq_n_s32(0); + const mve_pred16_t p = vcmpgtq_n_s32(shift, 0); + + const int32x4_t left_shift = vpselq_s32(shift, zz, p); + const int32x4_t right_shift = -vpselq_s32(zz, shift, p); + + return arm_divide_by_power_of_two_mve_32x4(arm_doubling_high_mult_mve_32x4(vshlq_s32(val, left_shift), multiplier), + right_shift); +#endif +} +#endif + +// @note The following functions are used only for softmax layer, scaled bits = 5 assumed + +__STATIC_FORCEINLINE int32_t arm_nn_exp_on_negative_values(int32_t val) +{ + int32_t mask = 0; + int32_t shift = 24; + + const int32_t val_mod_minus_quarter = (val & ((1 << shift) - 1)) - (1 << shift); + const int32_t remainder = val_mod_minus_quarter - val; + const int32_t x = (val_mod_minus_quarter << 5) + (1 << 28); + const int32_t x2 = MUL_SAT(x, x); + + int32_t result = 1895147668 + + MUL_SAT(1895147668, x + DIV_POW2(MUL_SAT(DIV_POW2(MUL_SAT(x2, x2), 2) + MUL_SAT(x2, x), 715827883) + x2, 1)); + +#define SELECT_IF_NON_ZERO(x) \ + { \ + mask = MASK_IF_NON_ZERO(remainder & (1 << shift++)); \ + result = SELECT_USING_MASK(mask, MUL_SAT(result, x), result); \ + } + + SELECT_IF_NON_ZERO(1672461947) + SELECT_IF_NON_ZERO(1302514674) + SELECT_IF_NON_ZERO(790015084) + SELECT_IF_NON_ZERO(290630308) + SELECT_IF_NON_ZERO(39332535) + SELECT_IF_NON_ZERO(720401) + SELECT_IF_NON_ZERO(242) + +#undef SELECT_IF_NON_ZERO + + mask = MASK_IF_ZERO(val); + return SELECT_USING_MASK(mask, NN_Q31_MAX, result); +} + +__STATIC_FORCEINLINE q31_t arm_nn_mult_by_power_of_two(const int32_t val, const int32_t exp) +{ + const int32_t thresh = ((1 << (31 - exp)) - 1); + int32_t result = val << exp; + result = SELECT_USING_MASK(MASK_IF_NON_ZERO(val > thresh), NN_Q31_MAX, result); + result = SELECT_USING_MASK(MASK_IF_NON_ZERO(val < -thresh), NN_Q31_MIN, result); + return result; +} + +__STATIC_FORCEINLINE int32_t arm_nn_one_over_one_plus_x_for_x_in_0_1(int32_t val) +{ + const int64_t sum = (int64_t)val + (int64_t)NN_Q31_MAX; + const int32_t half_denominator = (int32_t)((sum + (sum >= 0 ? 1 : -1)) / 2L); + int32_t x = 1515870810 + MUL_SAT(half_denominator, -1010580540); + + const int32_t shift = (1 << 29); + x += MUL_POW2(MUL_SAT(x, shift - MUL_SAT(half_denominator, x)), 2); + x += MUL_POW2(MUL_SAT(x, shift - MUL_SAT(half_denominator, x)), 2); + x += MUL_POW2(MUL_SAT(x, shift - MUL_SAT(half_denominator, x)), 2); + + return MUL_POW2(x, 1); +} + +/** + @brief Write 2 q15 elements and post increment pointer. + @param[in] dest_q15 Pointer to pointer that holds address of destination. + @param[in] src_q31 Input value to be written. + */ +__STATIC_FORCEINLINE void arm_nn_write_q15x2_ia(q15_t **dest_q15, q31_t src_q31) +{ + q31_t val = src_q31; + + memcpy(*dest_q15, &val, 4); + *dest_q15 += 2; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ActivationFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/NN/Source/ActivationFunctions/CMakeLists.txt new file mode 100644 index 00000000..c53f635c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ActivationFunctions/CMakeLists.txt @@ -0,0 +1,30 @@ +# +# Copyright (c) 2019-2021 Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +project(CMSISNNActivation) + +file(GLOB SRC "./*_s8.c") +add_library(CMSISNNActivation STATIC ${SRC}) + +### Includes +target_include_directories(CMSISNNActivation PUBLIC "${NN}/Include") +target_include_directories(CMSISNNActivation PUBLIC "${ROOT}/CMSIS/Core/Include") +target_include_directories(CMSISNNActivation PUBLIC "${ROOT}/CMSIS/DSP/Include") + + + diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c new file mode 100644 index 00000000..cb8a08fe --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_activations_q15.c + * Description: Q15 neural network activation function using direct table look-up + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nn_tables.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + +/** + * @brief neural network activation function using direct table look-up + * + * @note Refer header file for details. + * + */ + +void arm_nn_activations_direct_q15(q15_t *data, uint16_t size, uint16_t int_width, arm_nn_activation_type type) +{ + uint16_t i = size; + q15_t *pIn = data; + q15_t *pOut = data; + uint16_t shift_size = 8 + 3 - int_width; + uint32_t bit_mask = 0x7FF >> int_width; + uint32_t full_frac = bit_mask + 1; + const q15_t *lookup_table; + + switch (type) + { + case ARM_SIGMOID: + lookup_table = sigmoidTable_q15; + break; + case ARM_TANH: + default: + lookup_table = tanhTable_q15; + break; + } + + while (i) + { + q15_t out; + q15_t in = *pIn++; + q15_t frac = (uint32_t)in & bit_mask; + q15_t value = lookup_table[(uint8_t)(in >> shift_size)]; + if ((in >> shift_size) != 0x7f) + { + q15_t value2 = lookup_table[(uint8_t)(1 + ((uint8_t)(in >> shift_size)))]; + /* doing the interpolation here for better accuracy */ + out = ((q31_t)(full_frac - frac) * value + (q31_t)value2 * frac) >> shift_size; + } + else + { + /* the largest positive value does not have a right side for linear interpolation */ + out = value; + } + + *pOut++ = out; + i--; + } +} + +/** + * @} end of Acti group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c new file mode 100644 index 00000000..72a0b156 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_activations_q7.c + * Description: Q7 neural network activation function using direct table look-up + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nn_tables.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + +/** + * @brief Q7 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * + * @details + * + * This is the direct table look-up approach. + * + * Assume here the integer part of the fixed-point is <= 3. + * More than 3 just not making much sense, makes no difference with + * saturation followed by any of these activation functions. + */ + +void arm_nn_activations_direct_q7(q7_t *data, uint16_t size, uint16_t int_width, arm_nn_activation_type type) +{ + uint16_t i = size; + q7_t *pIn = data; + q7_t *pOut = data; + q7_t in; + q7_t out; + uint16_t shift_size = 3 - int_width; + const q7_t *lookup_table; + switch (type) + { + case ARM_SIGMOID: + lookup_table = sigmoidTable_q7; + break; + case ARM_TANH: + default: + lookup_table = tanhTable_q7; + break; + } + while (i) + { + in = *pIn++; + out = lookup_table[(uint8_t)(in >> shift_size)]; + *pOut++ = out; + i--; + } +} + +/** + * @} end of Acti group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu6_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu6_s8.c new file mode 100644 index 00000000..a460b305 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu6_s8.c @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_relu6_s8.c + * Description: Basic s8 version of ReLU6 + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + +/* + * Basic ReLU6 function + * + * Refer to header file for details. + * + */ + +void arm_relu6_s8(q7_t *data, uint16_t size) +{ + int32_t i; + + for (i = 0; i < size; i++) + { + int32_t ip = data[i]; + + ip = MAX(ip, 0); + data[i] = MIN(ip, 6); + } +} + +/** + * @} end of Acti group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c new file mode 100644 index 00000000..d62117c7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_relu_q15.c + * Description: Q15 version of ReLU + * + * $Date: 09. October 2020 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + +/** + * @brief Q15 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * + * @details + * + * Optimized relu with QSUB instructions. + * + */ + +void arm_relu_q15(q15_t *data, uint16_t size) +{ + +#if defined(ARM_MATH_DSP) + /* Run the following code for M cores with DSP extension */ + + uint16_t i = size >> 1; + q15_t *input = data; + q15_t *output = data; + q31_t in; + q31_t buf; + q31_t mask; + + while (i) + { + in = read_q15x2_ia(&input); + + /* extract the first bit */ + buf = __ROR(in & 0x80008000, 15); + + /* if MSB=1, mask will be 0xFF, 0x0 otherwise */ + mask = __QSUB16(0x00000000, buf); + + arm_nn_write_q15x2_ia(&output, in & (~mask)); + i--; + } + + if (size & 0x1) + { + if (*input < 0) + { + *input = 0; + } + input++; + } +#else + /* Run the following code as reference implementation for M cores without DSP extension */ + uint16_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } + +#endif /* ARM_MATH_DSP */ +} + +/** + * @} end of Acti group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c new file mode 100644 index 00000000..a3163cdd --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_relu_q7.c + * Description: Q7 version of ReLU + * + * $Date: 20. July 2021 + * $Revision: V.1.1.3 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + +/** + * @brief Q7 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * + * @details + * + * Optimized relu with QSUB instructions. + * + */ + +void arm_relu_q7(q7_t *data, uint16_t size) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for M cores with DSP extension */ + + uint16_t i = size >> 2; + q7_t *input = data; + q7_t *output = data; + q31_t in; + q31_t buf; + q31_t mask; + + while (i) + { + in = arm_nn_read_q7x4_ia((const q7_t **)&input); + + /* extract the first bit */ + buf = (int32_t)__ROR((uint32_t)in & 0x80808080, 7); + + /* if MSB=1, mask will be 0xFF, 0x0 otherwise */ + mask = __QSUB8(0x00000000, buf); + + arm_nn_write_q7x4_ia(&output, in & (~mask)); + + i--; + } + + i = size & 0x3; + while (i) + { + if (*input < 0) + { + *input = 0; + } + input++; + i--; + } + +#else + /* Run the following code as reference implementation for cores without DSP extension */ + + uint16_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } + +#endif +} + +/** + * @} end of Acti group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/BasicMathFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/NN/Source/BasicMathFunctions/CMakeLists.txt new file mode 100644 index 00000000..fcd7a193 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/BasicMathFunctions/CMakeLists.txt @@ -0,0 +1,31 @@ +# +# Copyright (c) 2019-2021 Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +project(CMSISNNBasicMaths) + +file(GLOB SRC "./*_*.c") + +add_library(CMSISNNBasicMaths STATIC ${SRC}) + +### Includes +target_include_directories(CMSISNNBasicMaths PUBLIC "${NN}/Include") +target_include_directories(CMSISNNBasicMaths PUBLIC "${ROOT}/CMSIS/Core/Include") +target_include_directories(CMSISNNBasicMaths PUBLIC "${ROOT}/CMSIS/DSP/Include") + + + diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s16.c b/benchmark/interface/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s16.c new file mode 100644 index 00000000..6b1366da --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s16.c @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_elementwise_add_s16 + * Description: Elementwise add + * + * $Date: 14 Februari 2022 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup BasicMath + * @{ + */ + +/* + * s16 elementwise add + * + * Refer header file for details. + * + */ + +/* Note: __SHIFT is expected to be <=0 */ + +arm_status arm_elementwise_add_s16(const int16_t *input_1_vect, + const int16_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_1_mult, + const int32_t input_1_shift, + const int32_t input_2_offset, + const int32_t input_2_mult, + const int32_t input_2_shift, + const int32_t left_shift, + int16_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const int32_t block_size) +{ + (void)input_1_offset; + (void)input_2_offset; + (void)out_offset; + int32_t loop_count; + int32_t input_1; + int32_t input_2; + int32_t sum; + + loop_count = block_size; + + while (loop_count > 0) + { + /* C = A + B */ + input_1 = *input_1_vect++ << left_shift; + input_2 = *input_2_vect++ << left_shift; + + input_1 = arm_nn_requantize(input_1, input_1_mult, input_1_shift); + input_2 = arm_nn_requantize(input_2, input_2_mult, input_2_shift); + + sum = input_1 + input_2; + sum = arm_nn_requantize(sum, out_mult, out_shift); + + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + + *output++ = (int16_t)sum; + + /* Decrement loop counter */ + loop_count--; + } + + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of BasicMath group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s8.c new file mode 100644 index 00000000..85740edb --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s8.c @@ -0,0 +1,255 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_elementwise_add_s8 + * Description: Element wise add + * + * $Date: 01. March 2021 + * $Revision: V.2.5.3 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" +#if defined(ARM_MATH_MVEI) +#include "arm_helium_utils.h" +#endif + +#if defined(ARM_MATH_MVEI) +#define SAT_INPUT_VECT(__INPUT_V, __MULT, __SHIFT) \ + __INPUT_V = arm_doubling_high_mult_mve(__INPUT_V, __MULT); \ + __INPUT_V = arm_divide_by_power_of_two_mve(__INPUT_V, -__SHIFT); +#endif + +/** + * @note The *_no_sat API does not mean that the input not saturated, Since + * __MULT is a positive integer, it is saturated. The API definition + * has more info about it. + */ +#define SAT_INPUT(__INPUT, __MULT, __SHIFT) \ + __INPUT = arm_nn_doubling_high_mult_no_sat(__INPUT, __MULT); \ + __INPUT = arm_nn_divide_by_power_of_two(__INPUT, -__SHIFT); + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup BasicMath + * @{ + */ + +/* + * s8 element wise add + * + * Refer header file for details. + * + */ + +/* Note: __SHIFT is expected to be <=0 */ + +arm_status arm_elementwise_add_s8(const int8_t *input_1_vect, + const int8_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_1_mult, + const int32_t input_1_shift, + const int32_t input_2_offset, + const int32_t input_2_mult, + const int32_t input_2_shift, + const int32_t left_shift, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const uint32_t block_size) +{ +#if defined(ARM_MATH_MVEI) + int32_t count = (int32_t)block_size; + + while (count > 0) + { + int32x4_t vect_1; + int32x4_t vect_2; + + mve_pred16_t p = vctp32q((uint32_t)count); + + vect_1 = vldrbq_z_s32(input_1_vect, p); + vect_2 = vldrbq_z_s32(input_2_vect, p); + + vect_1 = vaddq_s32(vect_1, vdupq_n_s32(input_1_offset)); + vect_2 = vaddq_s32(vect_2, vdupq_n_s32(input_2_offset)); + + vect_1 = vshlq_r_s32(vect_1, left_shift); + vect_2 = vshlq_r_s32(vect_2, left_shift); + + SAT_INPUT_VECT(vect_1, input_1_mult, input_1_shift); + SAT_INPUT_VECT(vect_2, input_2_mult, input_2_shift); + + vect_1 = vaddq_s32(vect_1, vect_2); + SAT_INPUT_VECT(vect_1, out_mult, out_shift); + + vect_1 = vaddq_n_s32(vect_1, out_offset); + + vect_1 = vmaxq_s32(vect_1, vdupq_n_s32(out_activation_min)); + vect_1 = vminq_s32(vect_1, vdupq_n_s32(out_activation_max)); + + input_1_vect += 4; + input_2_vect += 4; + vstrbq_p_s32(output, vect_1, p); + + output += 4; + count -= 4; + } +#else + uint32_t loop_count; + int32_t input_1; + int32_t input_2; + int32_t sum; + +#if defined(ARM_MATH_DSP) + int32_t a_1, b_1, a_2, b_2; + + int32_t offset_1_packed, offset_2_packed; + + int8_t r1, r2, r3, r4; + + offset_1_packed = (input_1_offset << 16U) | (input_1_offset & 0x0FFFFL); + offset_2_packed = (input_2_offset << 16U) | (input_2_offset & 0x0FFFFL); + + loop_count = block_size >> 2; + + while (loop_count > 0U) + { + /* 4 outputs are calculated in one loop. The order of calculation is follows the order of output sign extension + intrinsic */ + input_1_vect = read_and_pad_reordered(input_1_vect, &b_1, &a_1); + input_2_vect = read_and_pad_reordered(input_2_vect, &b_2, &a_2); + + a_1 = __SADD16(a_1, offset_1_packed); + b_1 = __SADD16(b_1, offset_1_packed); + + a_2 = __SADD16(a_2, offset_2_packed); + b_2 = __SADD16(b_2, offset_2_packed); + + /* Sum 1 */ + input_1 = (b_1 & 0x0FFFF) << left_shift; + + SAT_INPUT(input_1, input_1_mult, input_1_shift); + + input_2 = (b_2 & 0x0FFFF) << left_shift; + SAT_INPUT(input_2, input_2_mult, input_2_shift); + + sum = input_1 + input_2; + SAT_INPUT(sum, out_mult, out_shift); + sum += out_offset; + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + r1 = (q7_t)sum; + + /* Sum 3 */ + input_1 = ((b_1 >> 16) & 0x0FFFF) << left_shift; + SAT_INPUT(input_1, input_1_mult, input_1_shift); + + input_2 = ((b_2 >> 16) & 0x0FFFF) << left_shift; + SAT_INPUT(input_2, input_2_mult, input_2_shift); + + sum = input_1 + input_2; + SAT_INPUT(sum, out_mult, out_shift); + sum += out_offset; + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + r3 = (q7_t)sum; + + /* Sum 2 */ + input_1 = (a_1 & 0x0FFFF) << left_shift; + SAT_INPUT(input_1, input_1_mult, input_1_shift); + + input_2 = (a_2 & 0x0FFFF) << left_shift; + SAT_INPUT(input_2, input_2_mult, input_2_shift); + + sum = input_1 + input_2; + SAT_INPUT(sum, out_mult, out_shift); + sum += out_offset; + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + r2 = (q7_t)sum; + + /* Sum 4 */ + input_1 = ((a_1 >> 16) & 0x0FFFF) << left_shift; + SAT_INPUT(input_1, input_1_mult, input_1_shift); + + input_2 = ((a_2 >> 16) & 0x0FFFF) << left_shift; + SAT_INPUT(input_2, input_2_mult, input_2_shift); + + sum = input_1 + input_2; + SAT_INPUT(sum, out_mult, out_shift); + sum += out_offset; + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + r4 = (q7_t)sum; + + write_q7x4_ia(&output, __PACKq7(r1, r2, r3, r4)); + + loop_count--; + } + + loop_count = block_size & 0x3; +#else + loop_count = block_size; +#endif + + while (loop_count > 0U) + { + /* C = A + B */ + + input_1 = (*input_1_vect++ + input_1_offset) << left_shift; + input_2 = (*input_2_vect++ + input_2_offset) << left_shift; + + input_1 = arm_nn_doubling_high_mult(input_1, input_1_mult); + input_1 = arm_nn_divide_by_power_of_two(input_1, -input_1_shift); + + input_2 = arm_nn_doubling_high_mult(input_2, input_2_mult); + input_2 = arm_nn_divide_by_power_of_two(input_2, -input_2_shift); + + sum = input_1 + input_2; + SAT_INPUT(sum, out_mult, out_shift); + sum += out_offset; + + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + + *output++ = (q7_t)sum; + + /* Decrement loop counter */ + loop_count--; + } + +#endif /* ARM_MATH_MVEI */ + + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of BasicMath group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s16.c b/benchmark/interface/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s16.c new file mode 100644 index 00000000..4e255741 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s16.c @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_elementwise_mul_s16 + * Description: Element wise multiplication + * + * $Date: 14 Februari 2022 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup BasicMath + * @{ + */ + +/** + * @brief s16 element wise multiplication of two vectors + * + * @note Refer header file for details. + * + */ +arm_status arm_elementwise_mul_s16(const int16_t *input_1_vect, + const int16_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_2_offset, + int16_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const int32_t block_size) +{ + (void)input_1_offset; + (void)input_2_offset; + (void)out_offset; + int32_t loop_count; + int32_t input_1; + int32_t input_2; + int32_t mul_res; + + loop_count = block_size; + + while (loop_count > 0) + { + /* C = A * B */ + + input_1 = *input_1_vect++; + input_2 = *input_2_vect++; + + mul_res = input_1 * input_2; + mul_res = arm_nn_requantize(mul_res, out_mult, out_shift); + + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + + *output++ = (int16_t)mul_res; + + /* Decrement loop counter */ + loop_count--; + } + + return ARM_MATH_SUCCESS; +} + +/** + * @} end of BasicMath group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s8.c new file mode 100644 index 00000000..7c560fe5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s8.c @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_elementwise_mul_s8 + * Description: Element wise multiplication + * + * $Date: January 26, 2021 + * $Revision: V.1.0.5 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup BasicMath + * @{ + */ + +/** + * @brief s8 element wise multiplication of two vectors + * + * @note Refer header file for details. + * + */ + +arm_status arm_elementwise_mul_s8(const int8_t *input_1_vect, + const int8_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_2_offset, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const uint32_t block_size) +{ + + int32_t loop_count; +#if defined(ARM_MATH_MVEI) + + loop_count = (block_size + 3) / 4; + uint32_t num_elements = block_size; + + for (int i = 0; i < loop_count; i++) + { + mve_pred16_t p = vctp32q(num_elements); + + int32x4_t input_1 = vldrbq_z_s32(input_1_vect, p); + input_1 = vaddq_n_s32(input_1, input_1_offset); + + int32x4_t input_2 = vldrbq_z_s32(input_2_vect, p); + input_2 = vaddq_n_s32(input_2, input_2_offset); + + int32x4_t res_0 = vmulq_s32(input_1, input_2); + + res_0 = arm_requantize_mve_32x4(res_0, vdupq_n_s32(out_mult), vdupq_n_s32(out_shift)); + + res_0 += vdupq_n_s32(out_offset); + + res_0 = vmaxq_s32(res_0, vdupq_n_s32(out_activation_min)); + res_0 = vminq_s32(res_0, vdupq_n_s32(out_activation_max)); + + vstrbq_p_s32(output, res_0, p); + input_1_vect += 4; + input_2_vect += 4; + output += 4; + num_elements -= 4; + } + +#else + int32_t input_1; + int32_t input_2; + int32_t mul_res; + +#if defined(ARM_MATH_DSP) + int32_t a_1, b_1, a_2, b_2; + + int32_t offset_1_packed, offset_2_packed; + + int8_t r1, r2, r3, r4; + + offset_1_packed = (input_1_offset << 16U) | (input_1_offset & 0x0FFFFL); + offset_2_packed = (input_2_offset << 16U) | (input_2_offset & 0x0FFFFL); + + loop_count = block_size >> 2; + + while (loop_count > 0) + { + /* 4 outputs are calculated in one loop. The order of calculation is follows the order of output sign extension + intrinsic */ + input_1_vect = read_and_pad_reordered(input_1_vect, &b_1, &a_1); + input_2_vect = read_and_pad_reordered(input_2_vect, &b_2, &a_2); + + a_1 = __SADD16(a_1, offset_1_packed); + b_1 = __SADD16(b_1, offset_1_packed); + + a_2 = __SADD16(a_2, offset_2_packed); + b_2 = __SADD16(b_2, offset_2_packed); + + /* Mul 1 */ + input_1 = (int16_t)(b_1 & 0x0FFFFL); + input_2 = (int16_t)(b_2 & 0x0FFFFL); + + mul_res = input_1 * input_2; + mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset; + + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + r1 = (q7_t)mul_res; + + /* Mul 3 */ + input_1 = (int16_t)((b_1 >> 16U) & 0x0FFFFL); + input_2 = (int16_t)((b_2 >> 16U) & 0x0FFFFL); + + mul_res = input_1 * input_2; + mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset; + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + r3 = (q7_t)mul_res; + + /* Mul 2 */ + input_1 = (int16_t)(a_1 & 0x0FFFFL); + input_2 = (int16_t)(a_2 & 0x0FFFFL); + + mul_res = input_1 * input_2; + mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset; + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + r2 = (q7_t)mul_res; + + /* Mul 4 */ + input_1 = (int16_t)((a_1 >> 16U) & 0x0FFFFL); + input_2 = (int16_t)((a_2 >> 16U) & 0x0FFFFL); + + mul_res = input_1 * input_2; + mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset; + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + r4 = (q7_t)mul_res; + + write_q7x4_ia(&output, __PACKq7(r1, r2, r3, r4)); + + loop_count--; + } + + loop_count = block_size & 0x3; +#else + loop_count = block_size; +#endif + + while (loop_count > 0) + { + /* C = A * B */ + + input_1 = *input_1_vect++ + input_1_offset; + input_2 = *input_2_vect++ + input_2_offset; + + mul_res = input_1 * input_2; + mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset; + + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + + *output++ = (q7_t)mul_res; + + /* Decrement loop counter */ + loop_count--; + } +#endif + return ARM_MATH_SUCCESS; +} + +/** + * @} end of BasicMath group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/NN/Source/CMakeLists.txt new file mode 100644 index 00000000..4150df35 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/CMakeLists.txt @@ -0,0 +1,98 @@ +# +# Copyright (c) 2019-2021 Arm Limited. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +SET(ROOT ${CMSIS_PATH}) + +# Select which parts of the CMSIS-DSP must be compiled. +# There are some dependencies between the parts but they are not tracked +# by this cmake. So, enabling some functions may require to enable some +# other ones. +option(CONCATENATION "Concatenation" ON) +option(FULLYCONNECTED "Fully Connected" ON) +option(CONVOLUTION "Convolutions" ON) +option(ACTIVATION "Activations" ON) +option(POOLING "Pooling" ON) +option(SOFTMAX "Softmax" ON) +option(BASICMATHSNN "Basic Maths for NN" ON) +option(RESHAPE "Reshape" ON) +option(SVDF "SVDF" ON) + +# When OFF it is the default behavior : all tables are included. +option(NNSUPPORT "NN Support" ON) + + +########################### +# +# CMSIS NN +# +########################### + +# NN Sources +SET(NN ${ROOT}/CMSIS/NN) + +list(APPEND CMAKE_MODULE_PATH ${NN}/Source) + +add_library(cmsis-nn STATIC) + +target_compile_options(cmsis-nn PRIVATE -Ofast) + +### Includes +target_include_directories(cmsis-nn PUBLIC "${NN}/Include") +target_include_directories(cmsis-nn PUBLIC "${ROOT}/CMSIS/Core/Include") +target_include_directories(cmsis-nn PUBLIC "${ROOT}/CMSIS/DSP/Include") + +if (BASICMATHSNN) + add_subdirectory(BasicMathFunctions) +endif() + +if (CONCATENATION) + add_subdirectory(ConcatenationFunctions) +endif() + +if (FULLYCONNECTED) + add_subdirectory(FullyConnectedFunctions) +endif() + +if (CONVOLUTION) + add_subdirectory(ConvolutionFunctions) +endif() + +if (ACTIVATION) + add_subdirectory(ActivationFunctions) +endif() + +if (POOLING) + add_subdirectory(PoolingFunctions) +endif() + +if (SOFTMAX) + add_subdirectory(SoftmaxFunctions) +endif() + +if (SVDF) + add_subdirectory(SVDFunctions) +endif() + +if (RESHAPE) + add_subdirectory(ReshapeFunctions) +endif() + +# Keep NNSUPPORT at the end +if (NNSUPPORT) + add_subdirectory(NNSupportFunctions) +endif() diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConcatenationFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/NN/Source/ConcatenationFunctions/CMakeLists.txt new file mode 100644 index 00000000..9d3f543a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConcatenationFunctions/CMakeLists.txt @@ -0,0 +1,20 @@ +# +# Copyright (c) 2019-2021 Arm Limited. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +file(GLOB SRC "./*_*.c") +target_sources(cmsis-nn PRIVATE ${SRC}) diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_w.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_w.c new file mode 100644 index 00000000..257e6a66 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_w.c @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_concatenation_s8_w.c + * Description: s8 version of concatenation along the W axis + * + * $Date: October 2019 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Concatenation + * @{ + */ + +/* + * s8 version of concatenation along the W axis + * + * Refer to header file for details. + * + */ +void arm_concatenation_s8_w(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint32_t offset_w) +{ + const uint32_t input_copy_size = input_x * input_y * input_z * input_w; + + output += offset_w * (input_x * input_y * input_z); + + arm_memcpy_q7(output, input, input_copy_size); +} + +/** + * @} end of Concatenation group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_x.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_x.c new file mode 100644 index 00000000..7e8487a6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_x.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_concatenation_s8_x.c + * Description: s8 version of concatenation along the X axis + * + * $Date: October 2019 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Concatenation + * @{ + */ + +/* + * s8 version of concatenation along the X axis + * + * Refer to header file for details. + * + */ +void arm_concatenation_s8_x(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_x, + const uint32_t offset_x) +{ + const uint32_t num_iterations = input_y * input_z * input_w; + + output += offset_x; + + uint32_t i; + + // Copy per row + for (i = 0; i < num_iterations; ++i) + { + arm_memcpy_q7(output, input, input_x); + input += input_x; + output += output_x; + } +} + +/** + * @} end of Concatenation group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_y.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_y.c new file mode 100644 index 00000000..075a702e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_y.c @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_concatenation_s8_y.c + * Description: s8 version of concatenation along the Y axis + * + * $Date: October 2019 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Concatenation + * @{ + */ + +/* + * s8 version of concatenation along the Y axis + * + * Refer to header file for details. + * + */ +void arm_concatenation_s8_y(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_y, + const uint32_t offset_y) +{ + const uint32_t num_iterations = input_z * input_w; + const uint32_t input_copy_size = input_x * input_y; + const uint32_t output_stride = input_x * output_y; + + output += offset_y * input_x; + uint32_t i; + + // Copy per tile + for (i = 0; i < num_iterations; ++i) + { + arm_memcpy_q7(output, input, input_copy_size); + input += input_copy_size; + output += output_stride; + } +} + +/** + * @} end of Concatenation group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_z.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_z.c new file mode 100644 index 00000000..3bd84f2a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_z.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_concatenation_s8_z.c + * Description: s8 version of concatenation along the Z axis + * + * $Date: October 2019 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Concatenation + * @{ + */ + +/* + * s8 version of concatenation along the Z axis + * + * Refer to header file for details. + * + */ +void arm_concatenation_s8_z(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_z, + const uint32_t offset_z) +{ + const uint32_t input_copy_size = input_x * input_y * input_z; + const uint32_t output_stride = input_x * input_y * output_z; + + output += offset_z * (input_x * input_y); + + uint32_t i; + + for (i = 0; i < input_w; ++i) + { + arm_memcpy_q7(output, input, input_copy_size); + input += input_copy_size; + output += output_stride; + } +} + +/** + * @} end of Concatenation group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/CMakeLists.txt new file mode 100644 index 00000000..30be0fee --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/CMakeLists.txt @@ -0,0 +1,24 @@ +# +# Copyright (c) 2019-2022 Arm Limited. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +file(GLOB SRC "./*_s8*.c") +file(GLOB SRC_S16 "./*_s16*.c") +target_sources(cmsis-nn PRIVATE ${SRC} ${SRC_S16}) + + + diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c new file mode 100644 index 00000000..a3edd40e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c @@ -0,0 +1,205 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_1_x_n_s8.c + * Description: s8 version of 1xN convolution using symmetric quantization. + * + * $Date: December 14, 2021 + * $Revision: V.2.1.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * 1xN s8 convolution function. + * + * Refer header file for details. + * + */ + +arm_status arm_convolve_1_x_n_s8(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data) +{ + (void)bias_dims; + arm_status status = ARM_MATH_SUCCESS; + if (output_dims->w % 4 != 0) + { + status = ARM_MATH_SIZE_MISMATCH; + goto out; + } + +#if defined(ARM_MATH_MVEI) + (void)ctx; + + const uint16_t input_x = input_dims->w; + const uint16_t kernel_x = filter_dims->w; + const uint16_t output_x = output_dims->w; + const uint16_t output_ch = output_dims->c; + const uint16_t input_ch = input_dims->c; + const uint16_t pad_x = conv_params->padding.w; + const uint16_t stride_x = conv_params->stride.w; + + const int32_t input_offset = conv_params->input_offset; + const int32_t out_offset = conv_params->output_offset; + const int32_t out_activation_min = conv_params->activation.min; + const int32_t out_activation_max = conv_params->activation.max; + int32_t *output_mult = quant_params->multiplier; + int32_t *output_shift = quant_params->shift; + + for (int i_out_x = 0; i_out_x <= (output_x - 4); i_out_x += 4) + { + int32_t input_begin_idx[4]; + int32_t ker_begin_idx[4]; + int32_t ker_end_idx[4]; + + for (int i = 0; i < 4; i++) + { + const int32_t est_input_x_idx = stride_x * (i_out_x + i) - pad_x; + input_begin_idx[i] = MAX(0, est_input_x_idx); + ker_begin_idx[i] = MAX(0, -est_input_x_idx); + ker_end_idx[i] = MIN(kernel_x, input_x - est_input_x_idx); + } + + if ((ker_begin_idx[0] != 0) || (ker_end_idx[3] != kernel_x)) + { + for (int i_out_ch = 0; i_out_ch < output_ch; i_out_ch++) + { + int32x4_t s_offset; + int32_t acc[4]; + { + int32_t sum_row[4]; + + (void)arm_nn_mat_mul_core_1x_s8((ker_end_idx[0] - ker_begin_idx[0]) * input_ch, + input_data + input_begin_idx[0] * input_ch, + filter_data + (input_ch * kernel_x * i_out_ch) + + (ker_begin_idx[0] * input_ch), + &sum_row[0], + &acc[0]); + (void)arm_nn_mat_mul_core_1x_s8((ker_end_idx[1] - ker_begin_idx[1]) * input_ch, + input_data + input_begin_idx[1] * input_ch, + filter_data + (input_ch * kernel_x * i_out_ch) + + (ker_begin_idx[1] * input_ch), + &sum_row[1], + &acc[1]); + + (void)arm_nn_mat_mul_core_1x_s8((ker_end_idx[2] - ker_begin_idx[2]) * input_ch, + input_data + input_begin_idx[2] * input_ch, + filter_data + (input_ch * kernel_x * i_out_ch) + + (ker_begin_idx[2] * input_ch), + &sum_row[2], + &acc[2]); + + (void)arm_nn_mat_mul_core_1x_s8((ker_end_idx[3] - ker_begin_idx[3]) * input_ch, + input_data + input_begin_idx[3] * input_ch, + filter_data + (input_ch * kernel_x * i_out_ch) + + (ker_begin_idx[3] * input_ch), + &sum_row[3], + &acc[3]); + + s_offset = vldrwq_s32(sum_row); + } + int32x4_t res = vldrwq_s32(acc); + s_offset = vmulq_n_s32(s_offset, input_offset); + res = vaddq_s32(res, s_offset); + if (bias_data) + { + res = vaddq_n_s32(res, bias_data[i_out_ch]); + } + res = arm_requantize_mve(res, output_mult[i_out_ch], output_shift[i_out_ch]); + res = vaddq_n_s32(res, out_offset); + + res = vmaxq_s32(res, vdupq_n_s32(out_activation_min)); + res = vminq_s32(res, vdupq_n_s32(out_activation_max)); + + const uint32x4_t scatter_offset = {0, output_ch, output_ch * 2, output_ch * 3}; + vstrbq_scatter_offset_s32(output_data, scatter_offset, res); + output_data++; + } + output_data += (3 * output_ch); + } + else + { + output_data = arm_nn_mat_mul_core_4x_s8(kernel_x * input_ch, + stride_x * input_ch, + input_data + input_begin_idx[0] * input_ch, + filter_data, + output_ch, + conv_params, + quant_params, + bias_data, + output_data); + } + } + +#else + status = arm_convolve_s8(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); +#endif + +out: + /* Return to application */ + return status; +} + +int32_t arm_convolve_1_x_n_s8_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims) +{ +#if !defined(ARM_MATH_MVEI) + return (2 * input_dims->c * filter_dims->w * filter_dims->h) * sizeof(int16_t); +#else + (void)input_dims; + (void)filter_dims; + return 0; +#endif +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c new file mode 100644 index 00000000..3db3ba4c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c @@ -0,0 +1,235 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_1x1_HWC_q7_fast_nonsquare.c + * Description: Fast Q7 version of 1x1 convolution (non-square shape) + * + * $Date: July 20, 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q7 version of 1x1 convolution (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is optimized for convolution with 1x1 kernel size (i.e., dim_kernel_x=1 + * and dim_kernel_y=1). It can be used for the second half of MobileNets [1] after depthwise + * separable convolution. + * + * This function is the version with full list of optimization tricks, but with + * some constraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + * + * [1] MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications + * https://arxiv.org/abs/1704.04861 + */ + +arm_status arm_convolve_1x1_HWC_q7_fast_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + (void)dim_im_in_y; + int16_t i_out_y, i_out_x; + int16_t i_ch_out; + + /* ----------------------- + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0 || dim_kernel_x != 1 || dim_kernel_y != 1 || padding_x != 0 || + padding_y != 0 || stride_x != 1 || stride_y != 1) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_out_y * dim_im_in_x + i_out_x) * ch_im_in, pBuffer, ch_im_in); + pBuffer += ch_im_in; + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* check if there is left-over for compute */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + q31_t sum = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); + const q15_t *pB = bufferA; + /* basically each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel_x * dim_kernel_y >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = read_and_pad_reordered(pA, &inA1, &inA2); + + inB1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA1, inB1, sum); + inB2 = arm_nn_read_q15x2_ia(&pB); + + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q7_t)__SSAT((sum >> out_shift), 8); + pOut++; + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0 || dim_kernel_x != 1 || dim_kernel_y != 1 || padding_x != 0 || + padding_y != 0 || stride_x != 1 || stride_y != 1) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + // if-for implementation + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_y + n) * ch_im_in + + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c new file mode 100644 index 00000000..6183f55e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_1x1_s8_fast.c + * Description: Fast q7 version of 1x1 convolution (non-square shape) + * + * $Date: 12. November 2021 + * $Revision: V.2.0.4 + * + * Target Processor: Cortex-M Processors + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" +#include + +#define DIM_KER_X (1U) +#define DIM_KER_Y (1U) + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Fast s8 version for 1x1 convolution (non-square shape) + * + * Refer header file for details. + * + */ + +arm_status arm_convolve_1x1_s8_fast(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data) +{ + if (input_dims->c % 4 != 0 || conv_params->padding.w != 0 || conv_params->padding.h != 0 || + conv_params->stride.w != 1 || conv_params->stride.h != 1) + { + return ARM_MATH_SIZE_MISMATCH; + } + + (void)ctx; + (void)filter_dims; + (void)bias_dims; + +#if defined(ARM_MATH_MVEI) + + const int32_t col_len = input_dims->w * input_dims->h * input_dims->n; + const int32_t output_ch = output_dims->c; + const int32_t input_ch = input_dims->c; + const int32_t input_offset = conv_params->input_offset; + const int32_t out_offset = conv_params->output_offset; + const int32_t out_activation_min = conv_params->activation.min; + const int32_t out_activation_max = conv_params->activation.max; + int32_t *output_mult = quant_params->multiplier; + int32_t *output_shift = quant_params->shift; + + for (int i_items = 0; i_items <= (col_len - 4); i_items += 4) + { + + output_data = arm_nn_mat_mul_core_4x_s8(input_ch, + input_ch, + input_data + i_items * input_ch, + filter_data, + output_ch, + conv_params, + quant_params, + bias_data, + output_data); + } + + /* Handle left over elements */ + for (int i_items = (col_len & ~0x3); i_items < col_len; i_items++) + { + for (int i_out_ch = 0; i_out_ch < output_ch; i_out_ch++) + { + int32_t sum_row = 0; + int32_t acc; + (void)arm_nn_mat_mul_core_1x_s8( + input_ch, input_data + i_items * input_ch, filter_data + i_out_ch * input_ch, &sum_row, &acc); + if (bias_data) + { + acc += bias_data[i_out_ch]; + } + sum_row = (sum_row * input_offset); + acc += sum_row; + acc = arm_nn_requantize(acc, output_mult[i_out_ch], output_shift[i_out_ch]); + acc += out_offset; + + acc = MAX(acc, out_activation_min); + acc = MIN(acc, out_activation_max); + *output_data++ = acc; + } + } + +#else + /* Run the following code as reference implementation for Cortex-M processors with or without DSP extension */ + + const int32_t lhs_rows = input_dims->w * input_dims->h * input_dims->n; + const int32_t rhs_rows = output_dims->c; + const int32_t rhs_cols = input_dims->c; + + arm_nn_mat_mult_nt_t_s8(input_data, + filter_data, + bias_data, + output_data, + quant_params->multiplier, + quant_params->shift, + lhs_rows, + rhs_rows, + rhs_cols, + conv_params->input_offset, + conv_params->output_offset, + conv_params->activation.min, + conv_params->activation.max); + +#endif + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +int32_t arm_convolve_1x1_s8_fast_get_buffer_size(const cmsis_nn_dims *input_dims) +{ + (void)input_dims; + return 0; +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c new file mode 100644 index 00000000..0a6868a2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q15_basic.c + * Description: Q15 version of convolution + * + * $Date: July 20, 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Basic Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * bufferA size: ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * This basic version is designed to work for any input tensor and weight + * dimension. + */ + +arm_status arm_convolve_HWC_q15_basic(const q15_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + uint16_t im2col_out_pixel_index = 0; + q15_t *pBuffer = bufferA; + q15_t *pOut = Im_out; + q15_t *im_buffer = bufferA; + const q15_t *pA; + int i; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* Filling 0 for out-of-bound paddings */ + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, + * ch_im_in); */ + memcpy(pBuffer, + (q15_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, + sizeof(q15_t) * ch_im_in); + } + pBuffer += ch_im_in; + } + } + + pA = wt; + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + const q15_t *pB = im_buffer; + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; + while (colCnt) + { + q31_t inA1 = arm_nn_read_q15x2_ia(&pA); + q31_t inB1 = arm_nn_read_q15x2_ia(&pB); + q31_t inA2 = arm_nn_read_q15x2_ia(&pA); + q31_t inB2 = arm_nn_read_q15x2_ia(&pB); + + sum = __SMLAD(inA1, inB1, sum); + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q15_t)__SSAT((sum >> out_shift), 16); + pOut++; + } + + /* counter reset */ + pBuffer = im_buffer; + im2col_out_pixel_index++; + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t)__SSAT((conv_out >> out_shift), 16); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c new file mode 100644 index 00000000..66fbc00e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c @@ -0,0 +1,259 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q15_fast.c + * Description: Fast Q15 version of convolution + * + * $Date: July 20, 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 2 + * + * ch_im_out is multiple of 2 + * + * dim_im_out is a multiple of 2 + * + */ + +arm_status arm_convolve_HWC_q15_fast(const q15_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + q15_t *pBuffer = bufferA; + q15_t *im_buffer = bufferA; + q15_t *pOut = Im_out; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0 || dim_im_out & 0x1) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, + * ch_im_in); */ + memcpy(pBuffer, + (q15_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, + sizeof(q15_t) * ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (i_out_x & 0x1) + { + int i; + /* initialize the matrix pointers for A */ + const q15_t *pA = wt; + + /* set up the second output pointers */ + q15_t *pOut2 = pOut + ch_im_out; + + /* this loop over rows in A */ + for (i = 0; i < ch_im_out; i += 2) + { + /* setup pointers for B */ + const q15_t *pB = im_buffer; + const q15_t *pB2 = pB + ch_im_in * dim_kernel * dim_kernel; + + /* aling the second pointer for A */ + const q15_t *pA2 = pA + ch_im_in * dim_kernel * dim_kernel; + + /* init the sum with bias */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 1; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA1 = arm_nn_read_q15x2_ia(&pA); + q31_t inB1 = arm_nn_read_q15x2_ia(&pB); + q31_t inA2 = arm_nn_read_q15x2_ia(&pA2); + q31_t inB2 = arm_nn_read_q15x2_ia(&pB2); + + sum = __SMLAD(inA1, inB1, sum); + sum2 = __SMLAD(inA1, inB2, sum2); + sum3 = __SMLAD(inA2, inB1, sum3); + sum4 = __SMLAD(inA2, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x1; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inB1 = *pB++; + q15_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q15_t)__SSAT(sum >> out_shift, 16); + *pOut++ = (q15_t)__SSAT(sum3 >> out_shift, 16); + *pOut2++ = (q15_t)__SSAT(sum2 >> out_shift, 16); + *pOut2++ = (q15_t)__SSAT(sum4 >> out_shift, 16); + + /* skip the row computed with A2 */ + pA += ch_im_in * dim_kernel * dim_kernel; + } /* for over ch_im_out */ + + pOut += ch_im_out; + /* counter reset */ + pBuffer = im_buffer; + } + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t)__SSAT((conv_out >> out_shift), 16); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c new file mode 100644 index 00000000..7babe51e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c @@ -0,0 +1,270 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q15_fast.c + * Description: Fast Q15 version of convolution + * + * $Date: July 20, 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q15 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 2 + * + * ch_im_out is multiple of 2 + * + */ + +arm_status arm_convolve_HWC_q15_fast_nonsquare(const q15_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + q15_t *pBuffer = bufferA; + q15_t *im_buffer = bufferA; + q15_t *pOut = Im_out; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, + * ch_im_in); */ + memcpy(pBuffer, + (q15_t *)Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, + sizeof(q15_t) * ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (i_out_x & 0x1) + { + int i; + /* initialize the matrix pointers for A */ + const q15_t *pA = wt; + + /* set up the second output pointers */ + q15_t *pOut2 = pOut + ch_im_out; + + /* this loop over rows in A */ + for (i = 0; i < ch_im_out; i += 2) + { + /* setup pointers for B */ + const q15_t *pB = im_buffer; + const q15_t *pB2 = pB + ch_im_in * dim_kernel_y * dim_kernel_x; + + /* aling the second pointer for A */ + const q15_t *pA2 = pA + ch_im_in * dim_kernel_y * dim_kernel_x; + + /* init the sum with bias */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x >> 1; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA1 = arm_nn_read_q15x2_ia(&pA); + q31_t inB1 = arm_nn_read_q15x2_ia(&pB); + q31_t inA2 = arm_nn_read_q15x2_ia(&pA2); + q31_t inB2 = arm_nn_read_q15x2_ia(&pB2); + + sum = __SMLAD(inA1, inB1, sum); + sum2 = __SMLAD(inA1, inB2, sum2); + sum3 = __SMLAD(inA2, inB1, sum3); + sum4 = __SMLAD(inA2, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x1; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inB1 = *pB++; + q15_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q15_t)__SSAT(sum >> out_shift, 16); + *pOut++ = (q15_t)__SSAT(sum3 >> out_shift, 16); + *pOut2++ = (q15_t)__SSAT(sum2 >> out_shift, 16); + *pOut2++ = (q15_t)__SSAT(sum4 >> out_shift, 16); + + /* skip the row computed with A2 */ + pA += ch_im_in * dim_kernel_y * dim_kernel_x; + } /* for over ch_im_out */ + + pOut += ch_im_out; + /* counter reset */ + pBuffer = im_buffer; + } + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_x * dim_kernel_y + (m * dim_kernel_x + n) * ch_im_in + + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q15_t)__SSAT((conv_out >> out_shift), 16); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c new file mode 100644 index 00000000..618f4923 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c @@ -0,0 +1,280 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_RGB.c + * Description: Q7 version of convolution for RGB image + * + * $Date: July 20, 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Q7 convolution function for RGB image + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in equals 3 + * + * This kernel is written exclusively for convolution with ch_im_in + * equals 3. This applies on the first layer of CNNs which has input + * image with RGB format. + */ + +arm_status arm_convolve_HWC_q7_RGB(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + // check if number of input channels is 3 + if (ch_im_in != 3) + { + return ARM_MATH_SIZE_MISMATCH; + } + // This part implements the im2col function + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* Equivalent to arm_fill_q15(0, pBuffer, ch_im_in) with assumption: ch_im_in = 3 */ + arm_memset_q7((q7_t *)pBuffer, (q7_t)0, 3 * sizeof(q15_t)); + pBuffer += 3; + } + else + { + /* + * Equivalent to: + * arm_q7_to_q15_no_shift( (q7_t*)Im_in+(i_ker_y*dim_im_in+i_ker_x)*3, pBuffer, 3); + */ + + const q7_t *pPixel = Im_in + (i_ker_y * dim_im_in + i_ker_x) * 3; + q31_t buf = arm_nn_read_q7x4(pPixel); + + union arm_nnword top; + union arm_nnword bottom; + + top.word = __SXTB16(buf); + bottom.word = __SXTB16(__ROR(buf, 8)); + +#ifndef ARM_MATH_BIG_ENDIAN + /* + * little-endian, | omit | 3rd | 2nd | 1st | + * MSB LSB + * top | 3rd | 1st |; bottom | omit | 2nd | + * + * version 1, need to swap 2nd and 3rd weight + * *__SIMD32(pBuffer) = top.word; + * *(pBuffer+2) = bottom.half_words[0]; + * + * version 2, no weight shuffling required + */ + *pBuffer++ = top.half_words[0]; + int32_t packed_word = __PKHBT(bottom.word, top.word, 0); + arm_memcpy_q7((q7_t *)pBuffer, (q7_t *)&packed_word, 4); +#else + /* + * big-endian, | 1st | 2nd | 3rd | omit | + * MSB LSB + * top | 2nd | omit |; bottom | 1st | 3rd | + * + * version 1, need to swap 2nd and 3rd weight + * *__SIMD32(pBuffer) = bottom.word; + * *(pBuffer+2) = top.half_words[1]; + * + * version 2, no weight shuffling required + */ + *pBuffer++ = bottom.half_words[0]; + int32_t packed_word = __PKHTB(top.word, bottom.word, 0); + arm_memcpy_q7((q7_t *)pBuffer, (q7_t *)&packed_word, 4); +#endif + pBuffer += 2; + } + } + } + + if (pBuffer == bufferA + 2 * 3 * dim_kernel * dim_kernel) + { + pOut = arm_nn_mat_mult_kernel_q7_q15( + wt, bufferA, ch_im_out, 3 * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* left-over because odd number of output pixels */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q15_t *pB = bufferA; + /* basically each time it process 4 entries */ + uint16_t colCnt = 3 * dim_kernel * dim_kernel >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = read_and_pad(pA, &inA1, &inA2); + + inB1 = arm_nn_read_q15x2_ia((const q15_t **)&pB); + sum = __SMLAD(inA1, inB1, sum); + inB2 = arm_nn_read_q15x2_ia((const q15_t **)&pB); + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = 3 * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + } + } +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + // check if number of input channels is 3 + if (ch_im_in != 3) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = (bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + /* if-for implementation */ + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c new file mode 100644 index 00000000..e274413a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c @@ -0,0 +1,227 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_basic.c + * Description: Q7 version of convolution + * + * $Date: 20. July 2021 + * $Revision: V.1.1.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Basic Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * This basic version is designed to work for any input tensor and weight + * dimension. + */ + +arm_status arm_convolve_HWC_q7_basic(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* Filling 0 for out-of-bound paddings */ + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + /* Copying the pixel data to column */ + arm_q7_to_q15_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* Computation is filed for every 2 columns */ + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = arm_nn_mat_mult_kernel_q7_q15( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* left-over because odd number of output pixels */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + /* Load the accumulator with bias first */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + + /* Point to the beging of the im2col buffer */ + const q15_t *pB = bufferA; + + /* Each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; + + while (colCnt) + { + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = read_and_pad(pA, &inA1, &inA2); + + inB1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA1, inB1, sum); + inB2 = arm_nn_read_q15x2_ia(&pB); + + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + } + } +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + (void)bufferA; + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + // if-for implementation + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c new file mode 100644 index 00000000..b42a57dc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c @@ -0,0 +1,229 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_basic.c + * Description: Q7 version of convolution + * + * $Date: July 20, 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Basic Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + */ + +arm_status arm_convolve_HWC_q7_basic_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* Filling 0 for out-of-bound paddings */ + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + /* Copying the pixel data to column */ + arm_q7_to_q15_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* Computation is filed for every 2 columns */ + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_y * dim_kernel_x) + { + pOut = arm_nn_mat_mult_kernel_q7_q15( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel_y * dim_kernel_x, bias_shift, out_shift, bias, pOut); + + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* left-over because odd number of output pixels */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + /* Load the accumulator with bias first */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + + /* Point to the beging of the im2col buffer */ + const q15_t *pB = bufferA; + + /* Each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x >> 2; + + while (colCnt) + { + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = read_and_pad(pA, &inA1, &inA2); + + inB1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA1, inB1, sum); + inB2 = arm_nn_read_q15x2_ia(&pB); + + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + } + } +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + (void)bufferA; + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + // if-for implementation + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_x + n) * ch_im_in + + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c new file mode 100644 index 00000000..51d98fd8 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c @@ -0,0 +1,380 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_fast.c + * Description: Fast Q7 version of convolution + * + * $Date: July 20, 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 4 ( because of the SIMD32 read and swap ) + * + * ch_im_out is multiple of 2 ( bacause 2x2 mat_mult kernel ) + * + * The im2col converts the Q7 tensor input into Q15 column, which is stored in + * bufferA. There is reordering happenning during this im2col process with + * arm_q7_to_q15_reordered_no_shift. For every four elements, the second and + * third elements are swapped. + * + * The computation kernel arm_nn_mat_mult_kernel_q7_q15_reordered does the + * GEMM computation with the reordered columns. + * + * To speed-up the determination of the padding condition, we split the + * computation into 3x3 parts, i.e., {top, mid, bottom} X {left, mid, right}. + * This reduces the total number of boundary condition checks and improves + * the data copying performance. + */ + +arm_status arm_convolve_HWC_q7_fast(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + /* + * Here we split the entire matrix into three regions depending on the padding situation + * Top: i_out_y from 0 to padding - 1 + * Middle: i_out_y from padding to dim_im_out-padding-1 + * Bottom: i_out_y from dim_im_out-padding to dim_im_out-1 + */ + + /* top part */ + for (i_out_y = 0; i_out_y < padding; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* middle part, here we also divide the x into left, mid and right */ + for (; i_out_y < dim_im_out - padding; i_out_y++) + { + + /* left part */ + for (i_out_x = 0; i_out_x < padding; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* mid part */ + for (; i_out_x < dim_im_out - padding; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + arm_q7_to_q15_reordered_no_shift((q7_t *)Im_in + + (i_ker_y * dim_im_in + i_out_x * stride - padding) * ch_im_in, + pBuffer, + ch_im_in * dim_kernel); + pBuffer += ch_im_in * dim_kernel; + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* right part */ + for (; i_out_x < dim_im_out; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + for (; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* check if there is left-over for compute */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + const q15_t *pB = bufferA; + /* each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = read_and_pad_reordered(pA, &inA1, &inA2); + + inB1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA1, inB1, sum); + inB2 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q7_t)__SSAT((sum >> out_shift), 8); + pOut++; + } + } +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = (bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + // if-for implementation + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c new file mode 100644 index 00000000..25f17bb4 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c @@ -0,0 +1,378 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_fast_nonsquare.c + * Description: Fast Q7 version of convolution (non-sqaure shape) + * + * $Date: July 20, 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some constraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ + +arm_status arm_convolve_HWC_q7_fast_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* ----------------------- + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + /* + * Here we split the entire matrix into three regions depending on the padding situation + * Top: i_out_y from 0 to padding - 1 + * Middle: i_out_y from padding to dim_im_out-padding-1 + * Bottom: i_out_y from dim_im_out-padding to dim_im_out-1 + */ + + /* top part */ + for (i_out_y = 0; i_out_y < padding_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* middle part, here we also divide the x into left, mid and right */ + for (; i_out_y < dim_im_out_y - padding_y; i_out_y++) + { + + /* left part */ + for (i_out_x = 0; i_out_x < padding_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* mid part */ + for (; i_out_x < dim_im_out_x - padding_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in_x + i_out_x * stride_x - padding_x) * ch_im_in, + pBuffer, + ch_im_in * dim_kernel_x); + pBuffer += ch_im_in * dim_kernel_x; + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* right part */ + for (; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + for (; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* check if there is left-over for compute */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + const q15_t *pB = bufferA; + /* basically each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel_x * dim_kernel_y >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = read_and_pad_reordered(pA, &inA1, &inA2); + + inB1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA1, inB1, sum); + inB2 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = (ch_im_in * dim_kernel_y * dim_kernel_x) & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q7_t)__SSAT((sum >> out_shift), 8); + pOut++; + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + /* if-for implementation */ + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_x + n) * ch_im_in + + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_fast_s16.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_fast_s16.c new file mode 100644 index 00000000..f509f26c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_fast_s16.c @@ -0,0 +1,241 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_fast_s16.c + * Description: Optimized s16 version of convolution. + * + * $Date: 12 August 2021 + * $Revision: V.1.1.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Basic s16 convolution function. + * + * Refer header file for details. Optimal use case for the DSP/MVE implementation is when input and output channels + * are multiples of 4 or atleast greater than 4. + * + */ + +arm_status arm_convolve_fast_s16(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data) +{ + (void)bias_dims; + if (filter_dims->w * filter_dims->h * input_dims->c >= 512) + { + return ARM_MATH_SIZE_MISMATCH; + } + + if (ctx->buf == NULL && arm_convolve_s8_get_buffer_size(input_dims, filter_dims) > 0) + { + return ARM_MATH_ARGUMENT_ERROR; + } + q15_t *buffer_a = (q15_t *)ctx->buf; + + const int32_t input_batches = input_dims->n; + const int32_t input_x = input_dims->w; + const int32_t input_y = input_dims->h; + const int32_t input_ch = input_dims->c; + const int32_t kernel_x = filter_dims->w; + const int32_t kernel_y = filter_dims->h; + const int32_t output_x = output_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_ch = output_dims->c; + + const int32_t pad_x = conv_params->padding.w; + const int32_t pad_y = conv_params->padding.h; + const int32_t stride_x = conv_params->stride.w; + const int32_t stride_y = conv_params->stride.h; + + const int16_t out_activation_min = conv_params->activation.min; + const int16_t out_activation_max = conv_params->activation.max; + int32_t *output_mult = quant_params->multiplier; + int32_t *output_shift = quant_params->shift; + + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Generate two columns from the input tensor a GEMM computation */ + q15_t *two_column_buf = buffer_a; + q15_t *out = output_data; + /* This part implements the im2col function */ + for (int32_t i_out_y = 0; i_out_y < output_y; i_out_y++) + { + for (int32_t i_out_x = 0; i_out_x < output_x; i_out_x++) + { + for (int32_t i_ker_y = i_out_y * stride_y - pad_y; i_ker_y < i_out_y * stride_y - pad_y + kernel_y; + i_ker_y++) + { + for (int32_t i_ker_x = i_out_x * stride_x - pad_x; i_ker_x < i_out_x * stride_x - pad_x + kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= input_y || i_ker_x < 0 || i_ker_x >= input_x) + { + /* Filling 0 for out-of-bound paddings */ + arm_memset_q7((q7_t *)two_column_buf, 0, sizeof(q15_t) * input_ch); + } + else + { + arm_memcpy_q7((q7_t *)two_column_buf, + (const q7_t *)(input_data + (i_ker_y * input_x + i_ker_x) * input_ch), + input_ch * sizeof(q15_t)); + } + two_column_buf += input_ch; + } + } + /* Computation is filed for every 2 columns */ + if (two_column_buf == buffer_a + 2 * input_ch * kernel_y * kernel_x) + { + out = arm_nn_mat_mult_kernel_s16(filter_data, + buffer_a, + output_ch, + output_shift, + output_mult, + out_activation_min, + out_activation_max, + (input_ch * kernel_y * kernel_x), + bias_data, + out); + + /* Counter reset */ + two_column_buf = buffer_a; + } + } + } + + /* Left-over because odd number of output pixels */ + if (two_column_buf != buffer_a) + { + const q7_t *ker_a = filter_data; + int i; + + for (i = 0; i < output_ch; i++) + { + /* Init the accumulator*/ + q31_t sum = 0; + + /* Point to the beginning of the im2col buffer where the input is available as a rearranged column */ + const q15_t *ip_as_col = buffer_a; + + /* 4 multiply and accumulates are done in one loop. */ + uint16_t col_count = (input_ch * kernel_y * kernel_x) >> 2; + + while (col_count) + { + q31_t ker_a1, ker_a2; + q31_t ip_b1, ip_b2; + + ker_a = read_and_pad(ker_a, &ker_a1, &ker_a2); + + ip_b1 = arm_nn_read_q15x2_ia(&ip_as_col); + sum = __SMLAD(ker_a1, ip_b1, sum); + ip_b2 = arm_nn_read_q15x2_ia(&ip_as_col); + sum = __SMLAD(ker_a2, ip_b2, sum); + + col_count--; + } + /* Handle left over mac */ + col_count = input_ch * kernel_y * kernel_x & 0x3; + while (col_count) + { + q7_t ker_a1 = *ker_a++; + q15_t ip_b1 = *ip_as_col++; + sum += ker_a1 * ip_b1; + col_count--; + } + if (bias_data) + { + q31_t reduced_multiplier = REDUCE_MULTIPLIER(output_mult[i]); + q63_t acc_64 = sum + bias_data[i]; + sum = arm_nn_requantize_s64(acc_64, reduced_multiplier, output_shift[i]); + } + else + { + sum = arm_nn_requantize(sum, output_mult[i], output_shift[i]); + } + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + *out++ = (q15_t)sum; + } + } +#else + (void)input_data; + (void)output_data; + (void)bias_data; + (void)filter_data; + (void)buffer_a; + (void)kernel_x; + (void)kernel_y; + (void)pad_x; + (void)pad_y; + (void)stride_x; + (void)stride_y; + (void)out_activation_min; + (void)out_activation_max; + (void)output_mult; + (void)output_shift; + return ARM_MATH_ARGUMENT_ERROR; +#endif + /* Advance to the next batch */ + input_data += (input_x * input_y * input_ch); + output_data += (output_x * output_y * output_ch); + } + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +int32_t arm_convolve_fast_s16_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims) +{ +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + return (2 * input_dims->c * filter_dims->w * filter_dims->h) * (int32_t)sizeof(int16_t); +#else + (void)input_dims; + (void)filter_dims; + return 0; +#endif +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_s16.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_s16.c new file mode 100644 index 00000000..9702575b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_s16.c @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_s16.c + * Description: s16 version of convolution using symmetric quantization. + * + * $Date: January 13, 2022 + * $Revision: V.1.1.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Basic s16 convolution function. + * + * Refer header file for details. Optimal use case for the DSP/MVE implementation is when input and output channels + * are multiples of 4 or atleast greater than 4. + * + */ + +arm_status arm_convolve_s16(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data) +{ + (void)bias_dims; + (void)ctx; + + const int32_t input_batches = input_dims->n; + const int32_t input_x = input_dims->w; + const int32_t input_y = input_dims->h; + const int32_t input_ch = input_dims->c; + const int32_t kernel_x = filter_dims->w; + const int32_t kernel_y = filter_dims->h; + const int32_t output_x = output_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_ch = output_dims->c; + + const int32_t pad_x = conv_params->padding.w; + const int32_t pad_y = conv_params->padding.h; + const int32_t stride_x = conv_params->stride.w; + const int32_t stride_y = conv_params->stride.h; + const int32_t dilation_x = conv_params->dilation.w; + const int32_t dilation_y = conv_params->dilation.h; + + const int32_t out_activation_min = conv_params->activation.min; + const int32_t out_activation_max = conv_params->activation.max; + int32_t *output_mult = quant_params->multiplier; + int32_t *output_shift = quant_params->shift; + + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + for (int32_t i_out_ch = 0; i_out_ch < output_ch; i_out_ch++) + { + const q31_t reduced_multiplier = REDUCE_MULTIPLIER(output_mult[i_out_ch]); + + for (int32_t base_idx_y = -pad_y, i_out_y = 0; i_out_y < output_y; base_idx_y += stride_y, i_out_y++) + { + for (int32_t base_idx_x = -pad_x, i_out_x = 0; i_out_x < output_x; base_idx_x += stride_x, i_out_x++) + { + int64_t conv_out_acc = 0; + + const int32_t start_y_max = (-base_idx_y + dilation_y - 1) / dilation_y; + const int32_t ker_y_start = MAX(0, start_y_max); + const int32_t start_x_max = (-base_idx_x + dilation_x - 1) / dilation_x; + const int32_t ker_x_start = MAX(0, start_x_max); + const int32_t end_min_y = (input_y - base_idx_y + dilation_y - 1) / dilation_y; + const int32_t ker_y_end = MIN(kernel_y, end_min_y); + const int32_t end_min_x = (input_x - base_idx_x + dilation_x - 1) / dilation_x; + const int32_t ker_x_end = MIN(kernel_x, end_min_x); + + for (int32_t i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + for (int32_t i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t in_row = base_idx_y + dilation_y * i_ker_y; + const int32_t in_col = base_idx_x + dilation_x * i_ker_x; + + for (int32_t i_input_ch = 0; i_input_ch < input_ch; i_input_ch++) + { + conv_out_acc += input_data[(in_row * input_x + in_col) * input_ch + i_input_ch] * + filter_data[i_out_ch * input_ch * kernel_y * kernel_x + + (i_ker_y * kernel_x + i_ker_x) * input_ch + i_input_ch]; + } + } + } + + if (bias_data) + { + conv_out_acc += bias_data[i_out_ch]; + } + + int32_t conv_out = arm_nn_requantize_s64(conv_out_acc, reduced_multiplier, output_shift[i_out_ch]); + conv_out = MAX(conv_out, out_activation_min); + conv_out = MIN(conv_out, out_activation_max); + output_data[i_out_ch + (i_out_y * output_x + i_out_x) * output_ch] = (int16_t)conv_out; + } + } + } + /* Advance to the next batch */ + input_data += (input_x * input_y * input_ch); + output_data += (output_x * output_y * output_ch); + } + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +int32_t arm_convolve_s16_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims) +{ + (void)input_dims; + (void)filter_dims; + return 0; +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_s8.c new file mode 100644 index 00000000..e884b31e --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_s8.c @@ -0,0 +1,335 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_s8.c + * Description: s8 version of convolution using symmetric quantization. + * + * $Date: December 14, 2021 + * $Revision: V.2.1.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Basic s8 convolution function. + * + * Refer header file for details. Optimal use case for the DSP/MVE implementation is when input and output channels + * are multiples of 4 or atleast greater than 4. + * + */ + +arm_status arm_convolve_s8(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data) +{ + (void)bias_dims; + + if (ctx->buf == NULL && arm_convolve_s8_get_buffer_size(input_dims, filter_dims) > 0) + { + return ARM_MATH_ARGUMENT_ERROR; + } + q15_t *buffer_a = (q15_t *)ctx->buf; + + const int32_t input_batches = input_dims->n; + const uint16_t input_x = input_dims->w; + const uint16_t input_y = input_dims->h; + const uint16_t input_ch = input_dims->c; + const uint16_t kernel_x = filter_dims->w; + const uint16_t kernel_y = filter_dims->h; + const uint16_t output_x = output_dims->w; + const uint16_t output_y = output_dims->h; + const uint16_t output_ch = output_dims->c; + + const uint16_t pad_x = conv_params->padding.w; + const uint16_t pad_y = conv_params->padding.h; + const uint16_t stride_x = conv_params->stride.w; + const uint16_t stride_y = conv_params->stride.h; + + const int32_t input_offset = conv_params->input_offset; + const int32_t out_offset = conv_params->output_offset; + const int32_t out_activation_min = conv_params->activation.min; + const int32_t out_activation_max = conv_params->activation.max; + int32_t *output_mult = quant_params->multiplier; + int32_t *output_shift = quant_params->shift; + + int i_batch; + for (i_batch = 0; i_batch < input_batches; i_batch++) + { +#if defined(ARM_MATH_MVEI) + /* Generate upto four columns from the input tensor a GEMM computation */ + q7_t *im2col_buf = (q7_t *)buffer_a; + q7_t *out = output_data; + int32_t buffer_fill_cnt = 0; + int32_t padded = 0; + const int32_t num_elem = kernel_x * kernel_y * input_ch; + const int32_t dilation_x = conv_params->dilation.w; + const int32_t dilation_y = conv_params->dilation.h; + + /* This part implements the im2col function */ + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int32_t base_idx_x = stride_x * i_out_x - pad_x; + const int32_t base_idx_y = stride_y * i_out_y - pad_y; + + for (int32_t i_ker_y = 0; i_ker_y < kernel_y; i_ker_y++) + { + for (int32_t i_ker_x = 0; i_ker_x < kernel_x; i_ker_x++) + { + const int32_t k_y = base_idx_y + dilation_y * i_ker_y; + const int32_t k_x = base_idx_x + dilation_x * i_ker_x; + + if (k_y < 0 || k_y >= input_y || k_x < 0 || k_x >= input_x) + { + memset(im2col_buf, (int8_t)-input_offset, sizeof(q7_t) * input_ch); + padded = 1; + } + else + { + arm_memcpy_q7(im2col_buf, input_data + (k_y * input_x + k_x) * input_ch, input_ch); + } + im2col_buf += input_ch; + } + } + + buffer_fill_cnt++; + + /* Computation is filed for every 4 columns */ + if (buffer_fill_cnt == 4 && (padded == 0)) + { + buffer_fill_cnt = 0; + out = arm_nn_mat_mul_core_4x_s8(num_elem, + num_elem, + (q7_t *)buffer_a, + filter_data, + output_ch, + conv_params, + quant_params, + bias_data, + out); + im2col_buf = (q7_t *)buffer_a; + } + else if (buffer_fill_cnt == 4 && (padded != 0)) + { + buffer_fill_cnt = 0; + out = arm_nn_mat_mult_s8(filter_data, + (q7_t *)buffer_a, + output_ch, + 4, + output_shift, + output_mult, + out_offset, + input_offset, + 0, + out_activation_min, + out_activation_max, + num_elem, + bias_data, + out); + + im2col_buf = (q7_t *)buffer_a; + padded = 0; + } + } + } + /* Handle left over columns */ + if (buffer_fill_cnt != 0) + { + out = arm_nn_mat_mult_s8(filter_data, + (q7_t *)buffer_a, + output_ch, + buffer_fill_cnt, + output_shift, + output_mult, + out_offset, + input_offset, + 0, + out_activation_min, + out_activation_max, + num_elem, + bias_data, + out); + } +#else // #if defined(ARM_MATH_MVEI) + const uint16_t dilation_x = conv_params->dilation.w; + const uint16_t dilation_y = conv_params->dilation.h; + + int32_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* Generate two columns from the input tensor a GEMM computation */ + q15_t *two_column_buf = buffer_a; + q7_t *out = output_data; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < output_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int32_t base_idx_y = stride_y * i_out_y - pad_y; + const int32_t base_idx_x = stride_x * i_out_x - pad_x; + + for (i_ker_y = 0; i_ker_y < kernel_y; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < kernel_x; i_ker_x++) + { + const int32_t k_y = base_idx_y + dilation_y * i_ker_y; + const int32_t k_x = base_idx_x + dilation_x * i_ker_x; + + if (k_y < 0 || k_y >= input_y || k_x < 0 || k_x >= input_x) + { + /* Filling 0 for out-of-bound paddings */ + memset(two_column_buf, 0, sizeof(q15_t) * input_ch); + } + else + { + /* Copying the pixel data to column */ + arm_q7_to_q15_with_offset( + input_data + (k_y * input_x + k_x) * input_ch, two_column_buf, input_ch, input_offset); + } + two_column_buf += input_ch; + } + } + + /* Computation is filed for every 2 columns */ + if (two_column_buf == buffer_a + 2 * input_ch * kernel_y * kernel_x) + { + out = arm_nn_mat_mult_kernel_s8_s16(filter_data, + buffer_a, + output_ch, + output_shift, + output_mult, + out_offset, + out_activation_min, + out_activation_max, + input_ch * kernel_y * kernel_x, + bias_data, + out); + + /* counter reset */ + two_column_buf = buffer_a; + } + } + } + + /* left-over because odd number of output pixels */ + if (two_column_buf != buffer_a) + { + const q7_t *ker_a = filter_data; + int i; + + for (i = 0; i < output_ch; i++) + { + /* Load the accumulator with bias first */ + q31_t sum = 0; + if (bias_data) + { + sum = bias_data[i]; + } + + /* Point to the beginning of the im2col buffer where the input is available as a rearranged column */ + const q15_t *ip_as_col = buffer_a; + + /* 4 multiply and accumulates are done in one loop. */ +#if defined(ARM_MATH_DSP) + uint16_t col_count = (input_ch * kernel_y * kernel_x) >> 2; + + while (col_count) + { + q31_t ker_a1, ker_a2; + q31_t ip_b1, ip_b2; + + ker_a = read_and_pad(ker_a, &ker_a1, &ker_a2); + + ip_b1 = arm_nn_read_q15x2_ia(&ip_as_col); + sum = __SMLAD(ker_a1, ip_b1, sum); + ip_b2 = arm_nn_read_q15x2_ia(&ip_as_col); + sum = __SMLAD(ker_a2, ip_b2, sum); + + col_count--; + } + /* Handle left over mac */ + col_count = input_ch * kernel_y * kernel_x & 0x3; +#else + uint16_t col_count = input_ch * kernel_y * kernel_x; +#endif + while (col_count) + { + q7_t ker_a1 = *ker_a++; + q15_t ip_b1 = *ip_as_col++; + sum += ker_a1 * ip_b1; + col_count--; + } + + sum = arm_nn_requantize(sum, output_mult[i], output_shift[i]); + sum += out_offset; + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + *out++ = (q7_t)sum; + } + } +#endif // #if defined(ARM_MATH_MVEI) + /* Advance to the next batch */ + input_data += (input_x * input_y * input_ch); + output_data += (output_x * output_y * output_ch); + } + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +int32_t arm_convolve_s8_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims) +{ +#if defined(ARM_MATH_MVEI) + int32_t col_length = input_dims->c * filter_dims->w * filter_dims->h; + // Get number of complete int16 lanes(multiple of 8) for given col_length. This is dependent on + // implementation of arm_nn_mat_mult_s8 + col_length = (col_length + 7) / 8; + // 4 -> number of im2col buffers, 8 -> 8 elements per Q register + return 4 * col_length * 8 * (int32_t)sizeof(int8_t); +#else + return (2 * input_dims->c * filter_dims->w * filter_dims->h) * (int32_t)sizeof(int16_t); +#endif +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_wrapper_s16.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_wrapper_s16.c new file mode 100644 index 00000000..75bb26f5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_wrapper_s16.c @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2021-2022 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_wrapper_s16.c + * Description: s16 convolution layer wrapper function with the main purpose to call the optimal kernel available in + * cmsis-nn to perform the convolution. + * + * $Date: 13 January 2022 + * $Revision: V.1.2.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Convolution layer + * + * Refer header file for details. + * + */ + +arm_status arm_convolve_wrapper_s16(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data) +{ +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + if (filter_dims->w * filter_dims->h * input_dims->c < 512 && + (conv_params->dilation.w == 1 && conv_params->dilation.h == 1)) + { + return arm_convolve_fast_s16(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + } + else + { + return arm_convolve_s16(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + } +#else + return arm_convolve_s16(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); +#endif +} + +int32_t arm_convolve_wrapper_s16_get_buffer_size(const cmsis_nn_conv_params *conv_params, + const cmsis_nn_dims *input_dims, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims) +{ + (void)conv_params; + (void)output_dims; + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + if (filter_dims->w * filter_dims->h * input_dims->c < 512 && + (conv_params->dilation.w == 1 && conv_params->dilation.h == 1)) + { + return arm_convolve_fast_s16_get_buffer_size(input_dims, filter_dims); + } + + return arm_convolve_s16_get_buffer_size(input_dims, filter_dims); +#else + return arm_convolve_s16_get_buffer_size(input_dims, filter_dims); +#endif +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c new file mode 100644 index 00000000..bf1cd702 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_wrapper_s8.c + * Description: s8 convolution layer wrapper function with the main purpose to call the optimal kernel available in + * cmsis-nn to perform the convolution. + * + * $Date: 02. December 2021 + * $Revision: V.1.1.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Convolution layer + * + * Refer header file for details. + * + */ + +arm_status arm_convolve_wrapper_s8(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data) +{ + if ((conv_params->padding.w == 0) && (conv_params->padding.h == 0) && (input_dims->c % 4 == 0) && + (conv_params->stride.w == 1) && (conv_params->stride.h == 1) && (filter_dims->w == 1) && + (filter_dims->h == 1) && (conv_params->dilation.w == 1 && conv_params->dilation.h == 1)) + { + return arm_convolve_1x1_s8_fast(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + } + else if ((output_dims->h == 1) && (input_dims->h == 1) && (filter_dims->h == 1) && (output_dims->w % 4 == 0) && + (input_dims->n == 1) && (conv_params->dilation.w == 1 && conv_params->dilation.h == 1)) + { + return arm_convolve_1_x_n_s8(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + } + else + { + return arm_convolve_s8(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + } +} + +int32_t arm_convolve_wrapper_s8_get_buffer_size(const cmsis_nn_conv_params *conv_params, + const cmsis_nn_dims *input_dims, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims) +{ + if ((conv_params->padding.w == 0) && (conv_params->padding.h == 0) && (input_dims->c % 4 == 0) && + (conv_params->stride.w == 1) && (conv_params->stride.h == 1) && (filter_dims->w == 1) && + (filter_dims->h == 1) && (conv_params->dilation.w == 1 && conv_params->dilation.h == 1)) + { + return arm_convolve_1x1_s8_fast_get_buffer_size(input_dims); + } + else if ((output_dims->h == 1) && (input_dims->h == 1) && (filter_dims->h == 1) && (output_dims->w % 4 == 0) && + (input_dims->n == 1) && (conv_params->dilation.w == 1 && conv_params->dilation.h == 1)) + { + return arm_convolve_1_x_n_s8_get_buffer_size(input_dims, filter_dims); + } + else + { + return arm_convolve_s8_get_buffer_size(input_dims, filter_dims); + } +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c new file mode 100644 index 00000000..d5569b39 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c @@ -0,0 +1,212 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_conv_3x3_s8.c + * Description: Optimized s8 depthwise convolution function for channel + * multiplier of 1 and 3x3 kernel size. + * + * $Date: 09. October 2020 + * $Revision: V.2.0.1 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Optimized s8 depthwise convolution function with constraint that + * in_channel == out_channel and kernel_x == kernel_y == 3 with pads at most 1 + * + * Refer prototype header file for details. + * + */ + +arm_status arm_depthwise_conv_3x3_s8(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *kernel, + const cmsis_nn_dims *bias_dims, + const int32_t *bias, + const cmsis_nn_dims *output_dims, + q7_t *output) +{ + (void)ctx; + (void)bias_dims; + + const int32_t input_x = input_dims->w; + const int32_t input_y = input_dims->h; + const int32_t input_ch = input_dims->c; + const int32_t output_ch = output_dims->c; + const int32_t pad_x = dw_conv_params->padding.w; + const int32_t pad_y = dw_conv_params->padding.h; + const int32_t stride_x = dw_conv_params->stride.w; + const int32_t stride_y = dw_conv_params->stride.h; + const int32_t *output_shift = quant_params->shift; + const int32_t *output_mult = quant_params->multiplier; + const int32_t output_x = output_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_offset = dw_conv_params->output_offset; + const int32_t input_offset = dw_conv_params->input_offset; + const int32_t output_activation_min = dw_conv_params->activation.min; + const int32_t output_activation_max = dw_conv_params->activation.max; + + /* Check input constraints input_ch == output_ch */ + if (input_ch != output_ch) + { + return ARM_MATH_SIZE_MISMATCH; + } + /* Check input constraints pad_x <= 1 */ + if (pad_x > 1 || filter_dims->w != 3 || filter_dims->h != 3) + { + return ARM_MATH_ARGUMENT_ERROR; + } + + for (int32_t in_h = -pad_y, out_h = 0, out_idx = 0; out_h < output_y; in_h += stride_y, ++out_h) + { + for (int32_t in_w = -pad_x, out_w = 0, ker_h_start = MAX(0, -in_h); out_w < output_x; in_w += stride_x, ++out_w) + { + int32_t in_ch = 0; + int32_t ker_w_start = MAX(0, -in_w); + + for (; in_ch <= (input_ch - 4); in_ch += 4) + { + int32_t out_buff0 = bias[in_ch + 0]; + int32_t out_buff1 = bias[in_ch + 1]; + int32_t out_buff2 = bias[in_ch + 2]; + int32_t out_buff3 = bias[in_ch + 3]; + + const int8_t *input_ptr = input + (in_h + ker_h_start) * (input_ch * input_x) + in_w * input_ch + in_ch; + const int8_t *kernel_ptr = kernel + ker_h_start * (input_ch * 3) + in_ch; + + for (int32_t ker_h = ker_h_start; ker_h < MIN(3, input_y - in_h); ++ker_h) + { + int32_t in_val = 0; + int32_t ker_val = 0; + + if (ker_w_start == 0) + { + in_val = arm_nn_read_q7x4(input_ptr); + ker_val = arm_nn_read_q7x4(kernel_ptr); + + out_buff0 += ((int8_t)in_val + input_offset) * (int8_t)ker_val; + out_buff1 += ((int8_t)(in_val >> 8) + input_offset) * (int8_t)(ker_val >> 8); + out_buff2 += ((int8_t)(in_val >> 16) + input_offset) * (int8_t)(ker_val >> 16); + out_buff3 += ((int8_t)(in_val >> 24) + input_offset) * (int8_t)(ker_val >> 24); + } + + in_val = arm_nn_read_q7x4(input_ptr + input_ch); + ker_val = arm_nn_read_q7x4(kernel_ptr + input_ch); + + out_buff0 += ((int8_t)in_val + input_offset) * (int8_t)ker_val; + out_buff1 += ((int8_t)(in_val >> 8) + input_offset) * (int8_t)(ker_val >> 8); + out_buff2 += ((int8_t)(in_val >> 16) + input_offset) * (int8_t)(ker_val >> 16); + out_buff3 += ((int8_t)(in_val >> 24) + input_offset) * (int8_t)(ker_val >> 24); + + if ((input_x - in_w) >= 3) + { + in_val = arm_nn_read_q7x4(input_ptr + (input_ch << 1)); + ker_val = arm_nn_read_q7x4(kernel_ptr + (input_ch << 1)); + + out_buff0 += ((int8_t)in_val + input_offset) * (int8_t)ker_val; + out_buff1 += ((int8_t)(in_val >> 8) + input_offset) * (int8_t)(ker_val >> 8); + out_buff2 += ((int8_t)(in_val >> 16) + input_offset) * (int8_t)(ker_val >> 16); + out_buff3 += ((int8_t)(in_val >> 24) + input_offset) * (int8_t)(ker_val >> 24); + } + + input_ptr += (input_ch * input_x); + kernel_ptr += (input_ch * 3); + } + + out_buff0 = arm_nn_requantize(out_buff0, output_mult[in_ch + 0], output_shift[in_ch + 0]); + out_buff1 = arm_nn_requantize(out_buff1, output_mult[in_ch + 1], output_shift[in_ch + 1]); + out_buff2 = arm_nn_requantize(out_buff2, output_mult[in_ch + 2], output_shift[in_ch + 2]); + out_buff3 = arm_nn_requantize(out_buff3, output_mult[in_ch + 3], output_shift[in_ch + 3]); + + out_buff0 += output_offset; + out_buff1 += output_offset; + out_buff2 += output_offset; + out_buff3 += output_offset; + + out_buff0 = MIN(MAX(out_buff0, output_activation_min), output_activation_max); + out_buff1 = MIN(MAX(out_buff1, output_activation_min), output_activation_max); + out_buff2 = MIN(MAX(out_buff2, output_activation_min), output_activation_max); + out_buff3 = MIN(MAX(out_buff3, output_activation_min), output_activation_max); + + output[out_idx++] = (int8_t)out_buff0; + output[out_idx++] = (int8_t)out_buff1; + output[out_idx++] = (int8_t)out_buff2; + output[out_idx++] = (int8_t)out_buff3; + } + + // Leftover + for (; in_ch < input_ch; ++in_ch) + { + int32_t out_buff = bias[in_ch]; + + const int8_t *input_ptr = input + (in_h + ker_h_start) * (input_ch * input_x) + in_w * input_ch + in_ch; + const int8_t *kernel_ptr = kernel + ker_h_start * (input_ch * 3) + in_ch; + + for (int32_t ker_h = ker_h_start; ker_h < MIN(3, input_y - in_h); ++ker_h) + { + if (ker_w_start == 0) + { + out_buff += (*(input_ptr) + input_offset) * *(kernel_ptr); + } + + out_buff += (*(input_ptr + input_ch) + input_offset) * *(kernel_ptr + input_ch); + + if ((input_x - in_w) >= 3) + { + out_buff += (*(input_ptr + (input_ch << 1)) + input_offset) * *(kernel_ptr + (input_ch << 1)); + } + + input_ptr += (input_ch * input_x); + kernel_ptr += (input_ch * 3); + } + + out_buff = arm_nn_requantize(out_buff, output_mult[in_ch], output_shift[in_ch]); + out_buff += output_offset; + out_buff = MIN(MAX(out_buff, output_activation_min), output_activation_max); + output[out_idx++] = (int8_t)out_buff; + } + } + } + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s16.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s16.c new file mode 100644 index 00000000..42e4bbd6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s16.c @@ -0,0 +1,292 @@ +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_conv_s16.c + * Description: s16 version of depthwise convolution. + * + * $Date: 26. Jan 2022 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +static void __attribute__((unused)) depthwise_conv_s16_mult_4_s16(const int16_t *input, + const int32_t input_x, + const int32_t input_y, + const int32_t input_ch, + const int8_t *kernel, + const int32_t output_ch, + const int32_t ch_mult, + const int32_t kernel_x, + const int32_t kernel_y, + const int32_t pad_x, + const int32_t pad_y, + const int32_t stride_x, + const int32_t stride_y, + const int64_t *bias, + int16_t *output, + const int32_t *output_shift, + const int32_t *output_mult, + const int32_t output_x, + const int32_t output_y, + const int32_t output_activation_min, + const int32_t output_activation_max) +{ + for (int32_t in_h = -pad_y, out_h = 0, out_idx = 0; out_h < output_y; in_h += stride_y, ++out_h) + { + for (int32_t in_w = -pad_x, out_w = 0, ker_h_start = MAX(0, -in_h); out_w < output_x; in_w += stride_x, ++out_w) + { + for (int32_t in_ch = 0, out_ch = 0, ker_w_start = MAX(0, -in_w); out_ch < output_ch; + ++in_ch, out_ch += ch_mult) + { + for (int mult_tile = 0; mult_tile < ch_mult; mult_tile += 4) + { + int32_t out_buff32[4] = {REDUCE_MULTIPLIER(output_mult[out_ch + 0 + mult_tile]), + REDUCE_MULTIPLIER(output_mult[out_ch + 1 + mult_tile]), + REDUCE_MULTIPLIER(output_mult[out_ch + 2 + mult_tile]), + REDUCE_MULTIPLIER(output_mult[out_ch + 3 + mult_tile])}; + + int64_t out_buff[4] = {0, 0, 0, 0}; + + if (bias) + { + out_buff[0] = bias[out_ch + 0 + mult_tile]; + out_buff[1] = bias[out_ch + 1 + mult_tile]; + out_buff[2] = bias[out_ch + 2 + mult_tile]; + out_buff[3] = bias[out_ch + 3 + mult_tile]; + } + + for (int32_t ker_h = ker_h_start; ker_h < MIN(kernel_y, input_y - in_h); ++ker_h) + { + int32_t ker_idx = ker_h * (output_ch * kernel_x) + ker_w_start * output_ch + out_ch; + int32_t in_idx = (in_h + ker_h) * (input_ch * input_x) + in_w * input_ch + in_ch; +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang loop unroll(disable) +#endif + for (int32_t ker_w = ker_w_start; ker_w < MIN(kernel_x, input_x - in_w); + ++ker_w, ker_idx += output_ch) + { + // TODO: Unroll of 4 with 64 bit accumulator will probably result in too much register + // spills. Try with unroll of 2 when enabling this. + int32_t in_val = input[in_idx + ker_w * input_ch]; + out_buff[0] += in_val * kernel[ker_idx + 0 + mult_tile]; + out_buff[1] += in_val * kernel[ker_idx + 1 + mult_tile]; + out_buff[2] += in_val * kernel[ker_idx + 2 + mult_tile]; + out_buff[3] += in_val * kernel[ker_idx + 3 + mult_tile]; + } + } + + out_buff32[0] = + arm_nn_requantize_s64(out_buff[0], out_buff32[0], output_shift[out_ch + 0 + mult_tile]); + out_buff32[1] = + arm_nn_requantize_s64(out_buff[1], out_buff32[1], output_shift[out_ch + 1 + mult_tile]); + out_buff32[2] = + arm_nn_requantize_s64(out_buff[2], out_buff32[2], output_shift[out_ch + 2 + mult_tile]); + out_buff32[3] = + arm_nn_requantize_s64(out_buff[3], out_buff32[3], output_shift[out_ch + 3 + mult_tile]); + + out_buff32[0] = MIN(MAX(out_buff32[0], output_activation_min), output_activation_max); + out_buff32[1] = MIN(MAX(out_buff32[1], output_activation_min), output_activation_max); + out_buff32[2] = MIN(MAX(out_buff32[2], output_activation_min), output_activation_max); + out_buff32[3] = MIN(MAX(out_buff32[3], output_activation_min), output_activation_max); + + output[out_idx++] = (int16_t)out_buff32[0]; + output[out_idx++] = (int16_t)out_buff32[1]; + output[out_idx++] = (int16_t)out_buff32[2]; + output[out_idx++] = (int16_t)out_buff32[3]; + } + } + } + } +} + +static void depthwise_conv_s16_generic_s16(const int16_t *input, + const uint16_t input_batches, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_ch, + const int8_t *kernel, + const uint16_t ch_mult, + const uint16_t kernel_x, + const uint16_t kernel_y, + const uint16_t pad_x, + const uint16_t pad_y, + const uint16_t stride_x, + const uint16_t stride_y, + const int64_t *bias, + int16_t *output, + const int32_t *output_shift, + const int32_t *output_mult, + const uint16_t output_x, + const uint16_t output_y, + const int32_t output_activation_min, + const int32_t output_activation_max, + const uint16_t dilation_x, + const uint16_t dilation_y) + +{ + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + const int16_t base_idx_y = (i_out_y * stride_y) - pad_y; + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int16_t base_idx_x = (i_out_x * stride_x) - pad_x; + for (int i_input_ch = 0; i_input_ch < input_ch; i_input_ch++) + { + for (int i_ch_mult = 0; i_ch_mult < ch_mult; i_ch_mult++) + { + const int idx_out_ch = i_ch_mult + i_input_ch * ch_mult; + + const q31_t reduced_multiplier = REDUCE_MULTIPLIER(output_mult[idx_out_ch]); + int64_t acc_0 = 0; + + int ker_y_start; + int ker_x_start; + int ker_y_end; + int ker_x_end; + + if (dilation_x > 1) + { + const int32_t start_x_max = (-base_idx_x + dilation_x - 1) / dilation_x; + ker_x_start = MAX(0, start_x_max); + const int32_t end_min_x = (input_x - base_idx_x + dilation_x - 1) / dilation_x; + ker_x_end = MIN(kernel_x, end_min_x); + } + else + { + ker_x_start = MAX(0, -base_idx_x); + ker_x_end = MIN(kernel_x, input_x - base_idx_x); + } + + if (dilation_y > 1) + { + const int32_t start_y_max = (-base_idx_y + dilation_y - 1) / dilation_y; + ker_y_start = MAX(0, start_y_max); + const int32_t end_min_y = (input_y - base_idx_y + dilation_y - 1) / dilation_y; + ker_y_end = MIN(kernel_y, end_min_y); + } + else + { + ker_y_start = MAX(0, -base_idx_y); + ker_y_end = MIN(kernel_y, input_y - base_idx_y); + } + + if (bias) + { + acc_0 = bias[idx_out_ch]; + } + + for (int i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + dilation_y * i_ker_y; + for (int i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t idx_x = base_idx_x + dilation_x * i_ker_x; + int32_t idx_0 = (idx_y * input_x + idx_x) * input_ch + i_input_ch; + int32_t ker_idx_0 = (i_ker_y * kernel_x + i_ker_x) * (input_ch * ch_mult) + idx_out_ch; + + acc_0 += input[idx_0] * kernel[ker_idx_0]; + } + } + + /* Requantize and clamp output to provided range */ + int32_t result = arm_nn_requantize_s64(acc_0, reduced_multiplier, output_shift[idx_out_ch]); + result = MAX(result, output_activation_min); + result = MIN(result, output_activation_max); + *output++ = (int16_t)result; + } + } + } + } + /* Advance to the next batch */ + input += (input_x * input_y * input_ch); + } +} + +/* + * Basic s16 depthwise convolution function. + * + * Refer header file for details. + * + */ +arm_status arm_depthwise_conv_s16(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *kernel, + const cmsis_nn_dims *bias_dims, + const int64_t *bias, + const cmsis_nn_dims *output_dims, + q15_t *output) +{ + const uint16_t dilation_x = dw_conv_params->dilation.w; + const uint16_t dilation_y = dw_conv_params->dilation.h; + + (void)bias_dims; + (void)ctx; + + depthwise_conv_s16_generic_s16(input, + input_dims->n, + input_dims->w, + input_dims->h, + input_dims->c, + kernel, + dw_conv_params->ch_mult, + filter_dims->w, + filter_dims->h, + dw_conv_params->padding.w, + dw_conv_params->padding.h, + dw_conv_params->stride.w, + dw_conv_params->stride.h, + bias, + output, + quant_params->shift, + quant_params->multiplier, + output_dims->w, + output_dims->h, + dw_conv_params->activation.min, + dw_conv_params->activation.max, + dilation_x, + dilation_y); + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s8.c new file mode 100644 index 00000000..297b7afb --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s8.c @@ -0,0 +1,347 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_conv_s8.c + * Description: s8 version of depthwise convolution. + * + * $Date: 30. Dec 2021 + * $Revision: V.2.7.1 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +static void depthwise_conv_s8_mult_4(const int8_t *input, + const int32_t input_x, + const int32_t input_y, + const int32_t input_ch, + const int8_t *kernel, + const int32_t output_ch, + const int32_t ch_mult, + const int32_t kernel_x, + const int32_t kernel_y, + const int32_t pad_x, + const int32_t pad_y, + const int32_t stride_x, + const int32_t stride_y, + const int32_t *bias, + int8_t *output, + const int32_t *output_shift, + const int32_t *output_mult, + const int32_t output_x, + const int32_t output_y, + const int32_t output_offset, + const int32_t input_offset, + const int32_t output_activation_min, + const int32_t output_activation_max) +{ + for (int32_t in_h = -pad_y, out_h = 0, out_idx = 0; out_h < output_y; in_h += stride_y, ++out_h) + { + for (int32_t in_w = -pad_x, out_w = 0, ker_h_start = MAX(0, -in_h); out_w < output_x; in_w += stride_x, ++out_w) + { + for (int32_t in_ch = 0, out_ch = 0, ker_w_start = MAX(0, -in_w); out_ch < output_ch; + ++in_ch, out_ch += ch_mult) + { + for (int mult_tile = 0; mult_tile < ch_mult; mult_tile += 4) + { + int32_t out_buff[4] = {0, 0, 0, 0}; + if (bias) + { + out_buff[0] = bias[out_ch + 0 + mult_tile]; + out_buff[1] = bias[out_ch + 1 + mult_tile]; + out_buff[2] = bias[out_ch + 2 + mult_tile]; + out_buff[3] = bias[out_ch + 3 + mult_tile]; + } + + for (int32_t ker_h = ker_h_start; ker_h < MIN(kernel_y, input_y - in_h); ++ker_h) + { + int32_t ker_idx = ker_h * (output_ch * kernel_x) + ker_w_start * output_ch + out_ch; + int32_t in_idx = (in_h + ker_h) * (input_ch * input_x) + in_w * input_ch + in_ch; +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang loop unroll(disable) +#endif + for (int32_t ker_w = ker_w_start; ker_w < MIN(kernel_x, input_x - in_w); + ++ker_w, ker_idx += output_ch) + { + int32_t in_val = input[in_idx + ker_w * input_ch] + input_offset; + out_buff[0] += in_val * kernel[ker_idx + 0 + mult_tile]; + out_buff[1] += in_val * kernel[ker_idx + 1 + mult_tile]; + out_buff[2] += in_val * kernel[ker_idx + 2 + mult_tile]; + out_buff[3] += in_val * kernel[ker_idx + 3 + mult_tile]; + } + } +#if defined(ARM_MATH_MVEI) + (void)out_idx; + int32x4_t res = vldrwq_s32(out_buff); + res = arm_requantize_mve_32x4(res, + vldrwq_s32(&output_mult[out_ch + mult_tile]), + vldrwq_s32(&output_shift[out_ch + mult_tile])); + res = vaddq_n_s32(res, output_offset); + + res = vmaxq_s32(res, vdupq_n_s32(output_activation_min)); + res = vminq_s32(res, vdupq_n_s32(output_activation_max)); + vstrbq_s32(output, res); + output += 4; +#else + out_buff[0] = arm_nn_requantize( + out_buff[0], output_mult[out_ch + 0 + mult_tile], output_shift[out_ch + 0 + mult_tile]); + out_buff[1] = arm_nn_requantize( + out_buff[1], output_mult[out_ch + 1 + mult_tile], output_shift[out_ch + 1 + mult_tile]); + out_buff[2] = arm_nn_requantize( + out_buff[2], output_mult[out_ch + 2 + mult_tile], output_shift[out_ch + 2 + mult_tile]); + out_buff[3] = arm_nn_requantize( + out_buff[3], output_mult[out_ch + 3 + mult_tile], output_shift[out_ch + 3 + mult_tile]); + + out_buff[0] += output_offset; + out_buff[1] += output_offset; + out_buff[2] += output_offset; + out_buff[3] += output_offset; + + out_buff[0] = MIN(MAX(out_buff[0], output_activation_min), output_activation_max); + out_buff[1] = MIN(MAX(out_buff[1], output_activation_min), output_activation_max); + out_buff[2] = MIN(MAX(out_buff[2], output_activation_min), output_activation_max); + out_buff[3] = MIN(MAX(out_buff[3], output_activation_min), output_activation_max); + + output[out_idx++] = (int8_t)out_buff[0]; + output[out_idx++] = (int8_t)out_buff[1]; + output[out_idx++] = (int8_t)out_buff[2]; + output[out_idx++] = (int8_t)out_buff[3]; + +#endif + } + } + } + } +} + +static void depthwise_conv_s8_generic(const q7_t *input, + const uint16_t input_batches, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_ch, + const q7_t *kernel, + const uint16_t output_ch, + const uint16_t ch_mult, + const uint16_t kernel_x, + const uint16_t kernel_y, + const uint16_t pad_x, + const uint16_t pad_y, + const uint16_t stride_x, + const uint16_t stride_y, + const int32_t *bias, + q7_t *output, + const int32_t *output_shift, + const int32_t *output_mult, + const uint16_t output_x, + const uint16_t output_y, + const int32_t output_offset, + const int32_t input_offset, + const int32_t output_activation_min, + const int32_t output_activation_max, + const uint16_t dilation_x, + const uint16_t dilation_y) + +{ + (void)output_ch; + int i_out = 0; + int i_batch; + + for (i_batch = 0; i_batch < input_batches; i_batch++) + { + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + const int16_t base_idx_y = (i_out_y * stride_y) - pad_y; + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int16_t base_idx_x = (i_out_x * stride_x) - pad_x; + for (int i_input_ch = 0; i_input_ch < input_ch; i_input_ch++) + { + for (int i_ch_mult = 0; i_ch_mult < ch_mult; i_ch_mult++) + { + const int idx_out_ch = i_ch_mult + i_input_ch * ch_mult; + int32_t acc_0 = 0; + + int ker_y_start; + int ker_x_start; + int ker_y_end; + int ker_x_end; + + if (dilation_x > 1) + { + const int32_t start_x_max = (-base_idx_x + dilation_x - 1) / dilation_x; + ker_x_start = MAX(0, start_x_max); + const int32_t end_min_x = (input_x - base_idx_x + dilation_x - 1) / dilation_x; + ker_x_end = MIN(kernel_x, end_min_x); + } + else + { + ker_x_start = MAX(0, -base_idx_x); + ker_x_end = MIN(kernel_x, input_x - base_idx_x); + } + + if (dilation_y > 1) + { + const int32_t start_y_max = (-base_idx_y + dilation_y - 1) / dilation_y; + ker_y_start = MAX(0, start_y_max); + const int32_t end_min_y = (input_y - base_idx_y + dilation_y - 1) / dilation_y; + ker_y_end = MIN(kernel_y, end_min_y); + } + else + { + ker_y_start = MAX(0, -base_idx_y); + ker_y_end = MIN(kernel_y, input_y - base_idx_y); + } + + if (bias) + { + acc_0 = bias[idx_out_ch]; + } + + for (int i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + dilation_y * i_ker_y; + for (int i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t idx_x = base_idx_x + dilation_x * i_ker_x; + int32_t idx_0 = (idx_y * input_x + idx_x) * input_ch + i_input_ch; + int32_t ker_idx_0 = (i_ker_y * kernel_x + i_ker_x) * (input_ch * ch_mult) + idx_out_ch; + + acc_0 += (input[idx_0] + input_offset) * kernel[ker_idx_0]; + } + } + + /* Requantize and clamp output to provided range */ + acc_0 = arm_nn_requantize(acc_0, output_mult[idx_out_ch], output_shift[idx_out_ch]); + acc_0 += output_offset; + acc_0 = MAX(acc_0, output_activation_min); + acc_0 = MIN(acc_0, output_activation_max); + + output[i_out++] = acc_0; + } + } + } + } + /* Advance to the next batch */ + input += (input_x * input_y * input_ch); + } +} + +/* + * Basic s8 depthwise convolution function. + * + * Refer header file for details. + * Optimization using DSP extension is not available for the generic case where channel multiplier is > 1. + * + */ +arm_status arm_depthwise_conv_s8(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *kernel, + const cmsis_nn_dims *bias_dims, + const int32_t *bias, + const cmsis_nn_dims *output_dims, + q7_t *output) +{ + const uint16_t dilation_x = dw_conv_params->dilation.w; + const uint16_t dilation_y = dw_conv_params->dilation.h; + + (void)dw_conv_params->dilation; + (void)bias_dims; + (void)ctx; + + if (dw_conv_params->ch_mult % 4 == 0 && input_dims->n == 1 && dw_conv_params->dilation.w == 1 && + dw_conv_params->dilation.h == 1) + { + depthwise_conv_s8_mult_4(input, + input_dims->w, + input_dims->h, + input_dims->c, + kernel, + output_dims->c, + dw_conv_params->ch_mult, + filter_dims->w, + filter_dims->h, + dw_conv_params->padding.w, + dw_conv_params->padding.h, + dw_conv_params->stride.w, + dw_conv_params->stride.h, + bias, + output, + quant_params->shift, + quant_params->multiplier, + output_dims->w, + output_dims->h, + dw_conv_params->output_offset, + dw_conv_params->input_offset, + dw_conv_params->activation.min, + dw_conv_params->activation.max); + } + else + { + depthwise_conv_s8_generic(input, + input_dims->n, + input_dims->w, + input_dims->h, + input_dims->c, + kernel, + output_dims->c, + dw_conv_params->ch_mult, + filter_dims->w, + filter_dims->h, + dw_conv_params->padding.w, + dw_conv_params->padding.h, + dw_conv_params->stride.w, + dw_conv_params->stride.h, + bias, + output, + quant_params->shift, + quant_params->multiplier, + output_dims->w, + output_dims->h, + dw_conv_params->output_offset, + dw_conv_params->input_offset, + dw_conv_params->activation.min, + dw_conv_params->activation.max, + dilation_x, + dilation_y); + } + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c new file mode 100644 index 00000000..1edac046 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c @@ -0,0 +1,433 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_conv_s8_opt.c + * Description: Optimized s8 depthwise separable convolution function for + * channel multiplier of 1. + * + * $Date: January 26, 2021 + * $Revision: V.2.0.3 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Optimized s8 depthwise convolution function with constraint that in_channel equals out_channel + * + * Refer prototype header file for details. + * + */ + +arm_status arm_depthwise_conv_s8_opt(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *kernel, + const cmsis_nn_dims *bias_dims, + const int32_t *bias, + const cmsis_nn_dims *output_dims, + q7_t *output) +{ + + const int32_t input_ch = input_dims->c; + const int32_t output_ch = output_dims->c; + + /* Check input constraints input_ch == output_ch */ + if (input_ch != output_ch) + { + return ARM_MATH_SIZE_MISMATCH; + } + + if (ctx->buf == NULL && arm_depthwise_conv_s8_opt_get_buffer_size(input_dims, filter_dims) > 0) + { + return ARM_MATH_ARGUMENT_ERROR; + } +#ifdef ARM_MATH_DSP + const int32_t input_x = input_dims->w; + const int32_t input_y = input_dims->h; + const int32_t kernel_x = filter_dims->w; + const int32_t kernel_y = filter_dims->h; + const int32_t pad_x = dw_conv_params->padding.w; + const int32_t pad_y = dw_conv_params->padding.h; + const int32_t stride_x = dw_conv_params->stride.w; + const int32_t stride_y = dw_conv_params->stride.h; + const int32_t *output_shift = quant_params->shift; + const int32_t *output_mult = quant_params->multiplier; + const int32_t output_x = output_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_offset = dw_conv_params->output_offset; + const int32_t input_offset = dw_conv_params->input_offset; + const int32_t output_activation_min = dw_conv_params->activation.min; + const int32_t output_activation_max = dw_conv_params->activation.max; + q15_t *buffer_a = (q15_t *)ctx->buf; + +#ifdef ARM_MATH_MVEI + (void)bias_dims; + /* Generate two columns from the input tensor */ + q7_t *lhs_buffer = (q7_t *)buffer_a; + q7_t *out = output; + int padded = 0; + int buffer_count = 0; + const int32_t kernel_size = kernel_x * kernel_y; + + /* This part implements the im2col function */ + for (int i_out_y = 0, base_idx_y = -pad_y; i_out_y < output_y; base_idx_y += stride_y, i_out_y++) + { + for (int i_out_x = 0, base_idx_x = -pad_x; i_out_x < output_x; base_idx_x += stride_x, i_out_x++) + { + for (int i_ker_y = base_idx_y; i_ker_y < base_idx_y + kernel_y; i_ker_y++) + { + for (int i_ker_x = base_idx_x; i_ker_x < base_idx_x + kernel_x; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= input_y || i_ker_x < 0 || i_ker_x >= input_x) + { + arm_memset_q7(lhs_buffer, (int8_t)-input_offset, (uint32_t)input_ch); + padded = 1; + } + else + { + arm_memcpy_q7(lhs_buffer, input + (i_ker_y * input_x + i_ker_x) * input_ch, (uint32_t)input_ch); + } + lhs_buffer += input_ch; + } + } + buffer_count++; + + if (buffer_count == 4) + { + lhs_buffer = (q7_t *)buffer_a; + if (padded == 0) + { + out = arm_nn_depthwise_conv_nt_t_s8(lhs_buffer, + kernel, + input_offset, + input_ch, + output_shift, + output_mult, + output_offset, + output_activation_min, + output_activation_max, + kernel_size, + bias, + out); + } + else + { + out = arm_nn_depthwise_conv_nt_t_padded_s8(lhs_buffer, + kernel, + input_offset, + input_ch, + output_shift, + output_mult, + output_offset, + output_activation_min, + output_activation_max, + kernel_size, + bias, + out); + padded = 0; + } + buffer_count = 0; + } + } + } + + /* Handle left over buffers */ + lhs_buffer = (q7_t *)buffer_a; + + for (int i_buf = 0; i_buf < buffer_count; i_buf++) + { + int32_t loop_count = (input_ch + 3) / 4; + + int32_t num_ch_to_process = input_ch; + for (int i_loop_cnt = 0, offset = 0; i_loop_cnt < loop_count; num_ch_to_process -= 4, offset += 4, i_loop_cnt++) + { + const int8_t *col_0 = lhs_buffer + (kernel_size * input_ch * i_buf) + offset; + const int8_t *row_0 = kernel + offset; + int32x4_t out_0 = vldrwq_s32(&bias[offset]); + + for (int i_ker = 0; i_ker < kernel_size; i_ker++) + { + const int32x4_t ker_0 = vldrbq_s32(row_0); + + int32x4_t ip_0 = vldrbq_s32(col_0); + ip_0 = vaddq_n_s32(ip_0, input_offset); + out_0 += vmulq_s32(ip_0, ker_0); + + col_0 += input_ch; + row_0 += input_ch; + } + + const int32x4_t mult = vldrwq_s32(&output_mult[offset]); + const int32x4_t shift = vldrwq_s32(&output_shift[offset]); + + out_0 = arm_requantize_mve_32x4(out_0, mult, shift); + out_0 = vaddq_n_s32(out_0, output_offset); + out_0 = vmaxq_s32(out_0, vdupq_n_s32(output_activation_min)); + out_0 = vminq_s32(out_0, vdupq_n_s32(output_activation_max)); + mve_pred16_t p = vctp32q((uint32_t)num_ch_to_process); + vstrbq_p_s32(out, out_0, p); + + out += 4; + } + + const int tail_ch = input_ch & 0x3; + if (tail_ch != 0) + { + out -= (4 - tail_ch); + } + } + +#else // ARM_MATH_DSP + (void)bias_dims; + /* Run the following code in cores using DSP extension */ + q15_t *const col_buffer_start = buffer_a; + q15_t *col_buffer = col_buffer_start; + const int32_t *const bias_start_pos = bias; + const q31_t *const out_mult_start_pos = output_mult; + const q31_t *const out_shift_start_pos = output_shift; + uint16_t row_count; + uint16_t row_shift; + + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + const int16_t base_idx_y = (i_out_y * stride_y) - pad_y; + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int16_t base_idx_x = (i_out_x * stride_x) - pad_x; + + /* Out of bounds is only considered for the y axis as it provides a contiguous zero'ing opportunity than + along the x axis */ + const int ker_y_start = MAX(0, -base_idx_y); + /* Condition for kernel end dimension: (base_idx_y + ker_y_end) < input_y */ + const int ker_y_end = MIN(kernel_y, input_y - base_idx_y); + + int32_t index = 0; + if (ker_y_start != 0) + { + memset(&col_buffer[index], 0, (kernel_x * input_ch) * ker_y_start * sizeof(q15_t)); + index += (kernel_x * input_ch) * ker_y_start; + } + + for (int i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + i_ker_y; + + for (int i_ker_x = 0; i_ker_x < kernel_x; i_ker_x++) + { + const int32_t idx_x = base_idx_x + i_ker_x; + if (idx_x < 0 || idx_x >= input_x) + { + memset(&col_buffer[index], 0, input_ch * sizeof(q15_t)); + } + else + { + arm_q7_to_q15_with_offset((q7_t *)input + (idx_y * input_x + idx_x) * input_ch, + &col_buffer[index], + input_ch, + input_offset); + } + index += input_ch; + } + } + + const int diff = kernel_y - ker_y_end; + if (diff != 0) + { + memset(&col_buffer[index], 0, (kernel_x * input_ch) * diff * sizeof(q15_t)); + } + + row_count = output_ch / 4; + row_shift = 0; + bias = bias_start_pos; + output_mult = out_mult_start_pos; + output_shift = out_shift_start_pos; + + while (row_count) + { + q31_t sum = *bias++; + q31_t sum_2 = *bias++; + q31_t sum_3 = *bias++; + q31_t sum_4 = *bias++; + + uint16_t col_count = (kernel_x * kernel_y) / 2; + q15_t *col_pos = col_buffer_start + row_shift; + const q7_t *row_pos = kernel + row_shift; + row_shift += 4; + + while (col_count) + { + /* General idea is to read 4 + 4 (input, kernel) pair and re-arrange them in the right order to + use in a SMLAD instruction . One run of this loop produces 4 partial outputs with 8 MACs. */ + /* Note: variable names can be improved here to align with rows and columns. */ + q31_t ip_a1, ip_a2, ip_b1, ip_b2, op_a, op_b, op_c; + /* Read 4 weights */ + ip_b1 = arm_nn_read_q7x4(row_pos); + ip_a1 = arm_nn_read_q7x4(row_pos + input_ch); + op_a = arm_nn_read_q15x2(col_pos); + op_b = arm_nn_read_q15x2(col_pos + input_ch); + + ip_a2 = __SXTB16(ip_b1); + ip_b1 = __SXTB16(__ROR(ip_b1, 8)); + + ip_b2 = __SXTB16(ip_a1); + ip_a1 = __SXTB16(__ROR(ip_a1, 8)); + + op_c = __PKHBT(op_b, op_a, 16); + op_a = __PKHTB(op_b, op_a, 16); + op_b = __PKHBT(ip_b2, ip_a2, 16); + sum = __SMLAD(op_c, op_b, sum); + + op_b = __PKHBT(ip_b1, ip_a1, 16); + sum_2 = __SMLAD(op_a, op_b, sum_2); + + op_a = arm_nn_read_q15x2(col_pos + 2); + op_b = arm_nn_read_q15x2(col_pos + input_ch + 2); + + op_c = __PKHBT(op_b, op_a, 16); + op_a = __PKHTB(op_b, op_a, 16); + op_b = __PKHTB(ip_a2, ip_b2, 16); + sum_3 = __SMLAD(op_c, op_b, sum_3); + + op_b = __PKHTB(ip_a1, ip_b1, 16); + sum_4 = __SMLAD(op_a, op_b, sum_4); + + row_pos += input_ch << 1; + col_pos += input_ch << 1; + col_count--; + } + + col_count = (kernel_x * kernel_y) & 0x1; + while (col_count) + { + sum += row_pos[0] * col_pos[0]; + sum_2 += row_pos[1] * col_pos[1]; + sum_3 += row_pos[2] * col_pos[2]; + sum_4 += row_pos[3] * col_pos[3]; + + row_pos += input_ch; + col_pos += input_ch; + + col_count--; + } + sum = arm_nn_requantize(sum, *output_mult++, *output_shift++); + sum += output_offset; + sum = MAX(sum, output_activation_min); + sum = MIN(sum, output_activation_max); + *output++ = (q7_t)sum; + + sum_2 = arm_nn_requantize(sum_2, *output_mult++, *output_shift++); + sum_2 += output_offset; + sum_2 = MAX(sum_2, output_activation_min); + sum_2 = MIN(sum_2, output_activation_max); + *output++ = (q7_t)sum_2; + sum_3 = arm_nn_requantize(sum_3, *output_mult++, *output_shift++); + sum_3 += output_offset; + sum_3 = MAX(sum_3, output_activation_min); + sum_3 = MIN(sum_3, output_activation_max); + *output++ = (q7_t)sum_3; + + sum_4 = arm_nn_requantize(sum_4, *output_mult++, *output_shift++); + sum_4 += output_offset; + sum_4 = MAX(sum_4, output_activation_min); + sum_4 = MIN(sum_4, output_activation_max); + *output++ = (q7_t)sum_4; + + row_count--; + } + + row_count = output_ch & 0x3; + while (row_count) + { + q15_t *col_pos = col_buffer_start + row_shift; + const q7_t *row_pos = kernel + row_shift; + q31_t sum = *bias++; + const uint16_t col_count = (kernel_x * kernel_y); + row_shift += 1; + + for (int i = 0; i < col_count; i++) + { + sum += row_pos[i * input_ch] * col_pos[i * input_ch]; + } + sum = arm_nn_requantize(sum, *output_mult++, *output_shift++); + sum += output_offset; + sum = MAX(sum, output_activation_min); + sum = MIN(sum, output_activation_max); + *output++ = (q7_t)sum; + + row_count--; + } + + // clear counter and pointers + col_buffer = col_buffer_start; + } + } +#endif +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + return arm_depthwise_conv_s8(ctx, + dw_conv_params, + quant_params, + input_dims, + input, + filter_dims, + kernel, + bias_dims, + bias, + output_dims, + output); +#endif /* ARM_MATH_MVEI | ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +int32_t arm_depthwise_conv_s8_opt_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims) +{ +#if defined(ARM_MATH_MVEI) + /* The + 4 accounts for out of bounds read of the lhs buffers in the *_nt_t_* functions. */ + return (2 * input_dims->c * filter_dims->w * filter_dims->h) * (int32_t)sizeof(int16_t) + 4; +#elif defined(ARM_MATH_DSP) + return (input_dims->c * filter_dims->w * filter_dims->h) * sizeof(int16_t); +#else + (void)input_dims; + (void)filter_dims; + return 0; +#endif +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.c new file mode 100644 index 00000000..c9d0afc2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.c @@ -0,0 +1,336 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_conv_u8_basic_ver1.c + * Description: u8 depthwise convolution function + * + * $Date: 09. October 2020 + * $Revision: V.1.1.1 + * + * Target : Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +static void depthwise_conv_u8_mult_4(const uint8_t *input, + const int32_t input_x, + const int32_t input_y, + const int32_t input_ch, + const uint8_t *kernel, + const int32_t output_ch, + const int32_t ch_mult, + const int32_t kernel_x, + const int32_t kernel_y, + const int32_t pad_x, + const int32_t pad_y, + const int32_t stride_x, + const int32_t stride_y, + const int32_t *bias, + uint8_t *output, + const int32_t output_shift, + const int32_t output_mult, + const int32_t output_x, + const int32_t output_y, + const int32_t output_offset, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_activation_min, + const int32_t output_activation_max) +{ + for (int32_t in_h = -pad_y, out_h = 0, out_idx = 0; out_h < output_y; in_h += stride_y, ++out_h) + { + for (int32_t in_w = -pad_x, out_w = 0, ker_h_start = MAX(0, -in_h); out_w < output_x; in_w += stride_x, ++out_w) + { + for (int32_t in_ch = 0, out_ch = 0, ker_w_start = MAX(0, -in_w); out_ch < output_ch; + ++in_ch, out_ch += ch_mult) + { + for (int mult_tile = 0; mult_tile < ch_mult; mult_tile += 4) + { + int32_t out_buff[4]; + + out_buff[0] = 0; + out_buff[1] = 0; + out_buff[2] = 0; + out_buff[3] = 0; + + for (int32_t ker_h = ker_h_start; ker_h < MIN(kernel_y, input_y - in_h); ++ker_h) + { + int32_t ker_idx = ker_h * (output_ch * kernel_x) + ker_w_start * output_ch + out_ch; + int32_t in_idx = (in_h + ker_h) * (input_ch * input_x) + in_w * input_ch + in_ch; + + for (int32_t ker_w = ker_w_start; ker_w < MIN(kernel_x, input_x - in_w); + ++ker_w, ker_idx += output_ch) + { + int32_t in_val = input[in_idx + ker_w * input_ch] + input_offset; + out_buff[0] += in_val * (kernel[ker_idx + 0 + mult_tile] + filter_offset); + out_buff[1] += in_val * (kernel[ker_idx + 1 + mult_tile] + filter_offset); + out_buff[2] += in_val * (kernel[ker_idx + 2 + mult_tile] + filter_offset); + out_buff[3] += in_val * (kernel[ker_idx + 3 + mult_tile] + filter_offset); + } + } + + if (bias != NULL) + { + out_buff[0] += bias[out_ch + 0 + mult_tile]; + out_buff[1] += bias[out_ch + 1 + mult_tile]; + out_buff[2] += bias[out_ch + 2 + mult_tile]; + out_buff[3] += bias[out_ch + 3 + mult_tile]; + } + out_buff[0] = arm_nn_requantize(out_buff[0], output_mult, output_shift); + out_buff[1] = arm_nn_requantize(out_buff[1], output_mult, output_shift); + out_buff[2] = arm_nn_requantize(out_buff[2], output_mult, output_shift); + out_buff[3] = arm_nn_requantize(out_buff[3], output_mult, output_shift); + + out_buff[0] += output_offset; + out_buff[1] += output_offset; + out_buff[2] += output_offset; + out_buff[3] += output_offset; + + out_buff[0] = MIN(MAX(out_buff[0], output_activation_min), output_activation_max); + out_buff[1] = MIN(MAX(out_buff[1], output_activation_min), output_activation_max); + out_buff[2] = MIN(MAX(out_buff[2], output_activation_min), output_activation_max); + out_buff[3] = MIN(MAX(out_buff[3], output_activation_min), output_activation_max); + + output[out_idx++] = (uint8_t)out_buff[0]; + output[out_idx++] = (uint8_t)out_buff[1]; + output[out_idx++] = (uint8_t)out_buff[2]; + output[out_idx++] = (uint8_t)out_buff[3]; + } + } + } + } +} + +static void depthwise_conv_u8_generic(const uint8_t *input, + const int32_t input_x, + const int32_t input_y, + const int32_t input_ch, + const uint8_t *kernel, + const int32_t output_ch, + const int32_t ch_mult, + const int32_t kernel_x, + const int32_t kernel_y, + const int32_t pad_x, + const int32_t pad_y, + const int32_t stride_x, + const int32_t stride_y, + const int32_t *bias, + uint8_t *output, + const int32_t output_shift, + const int32_t output_mult, + const int32_t output_x, + const int32_t output_y, + const int32_t output_offset, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_activation_min, + const int32_t output_activation_max) +{ + (void)output_ch; + int i_out = 0; + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + const int16_t base_idx_y = (i_out_y * stride_y) - pad_y; + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int16_t base_idx_x = (i_out_x * stride_x) - pad_x; + for (int i_input_ch = 0; i_input_ch < input_ch; i_input_ch++) + { + for (int i_ch_mult = 0; i_ch_mult < ch_mult; i_ch_mult++) + { + const int idx_out_ch = i_ch_mult + i_input_ch * ch_mult; + int32_t acc_0; + /* Condition for kernel start dimension: (base_idx_ + ker__start) >= 0 */ + const int ker_y_start = MAX(0, -base_idx_y); + const int ker_x_start = MAX(0, -base_idx_x); + /* Condition for kernel end dimension: (base_idx_ + ker__end) < input_ */ + const int ker_y_end = MIN(kernel_y, input_y - base_idx_y); + const int ker_x_end = MIN(kernel_x, input_x - base_idx_x); + acc_0 = 0; + + for (int i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + i_ker_y; + for (int i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t idx_x = base_idx_x + i_ker_x; + int32_t idx_0 = (idx_y * input_x + idx_x) * input_ch + i_input_ch; + int32_t ker_idx_0 = (i_ker_y * kernel_x + i_ker_x) * (input_ch * ch_mult) + idx_out_ch; + + acc_0 += (input[idx_0] + input_offset) * (kernel[ker_idx_0] + filter_offset); + } + } + if (bias != NULL) + { + acc_0 += bias[idx_out_ch]; + } + + /* Requantize and clamp output to provided range */ + acc_0 = arm_nn_requantize(acc_0, output_mult, output_shift); + acc_0 += output_offset; + acc_0 = MAX(acc_0, output_activation_min); + acc_0 = MIN(acc_0, output_activation_max); + + output[i_out++] = acc_0; + } + } + } + } +} + +/** + * @brief uint8 depthwise convolution function with asymmetric quantization + * + * @param[in] input Pointer to input tensor + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_ch Channels in input tensor + * @param[in] kernel Pointer to kernel weights + * @param[in] kernel_x Width of kernel + * @param[in] kernel_y Height of kernel + * @param[in] ch_mult Number of channel multiplier + * @param[in] pad_x Padding sizes x + * @param[in] pad_y Padding sizes y + * @param[in] stride_x Convolution stride along the width + * @param[in] stride_y Convolution stride along the height + * @param[in] dilation_x Dilation along width. Not used and intended for future enhancement. + * @param[in] dilation_y Dilation along height. Not used and intended for future enhancement. + * @param[in] bias Pointer to optional bias values. If no bias is + * available, NULL is expected + * @param[in] input_offset Input tensor zero offset + * @param[in] filter_offset Kernel tensor zero offset + * @param[in] output_offset Output tensor zero offset + * @param[in,out] output Pointer to output tensor + * @param[in] output_x Width of output tensor + * @param[in] output_y Height of output tensor + * @param[in] output_activation_min Minimum value to clamp the output to. Range : {0, 255} + * @param[in] output_activation_max Minimum value to clamp the output to. Range : {0, 255} + * @param[in] output_shift Amount of right-shift for output + * @param[in] output_mult Output multiplier for requantization + * @return The function returns one of the following + * ARM_MATH_SIZE_MISMATCH - Not supported dimension of tensors + * ARM_MATH_SUCCESS - Successful operation + * ARM_MATH_ARGUMENT_ERROR - Implementation not available + * + * + */ + +arm_status arm_depthwise_conv_u8_basic_ver1(const uint8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_ch, + const uint8_t *kernel, + const uint16_t kernel_x, + const uint16_t kernel_y, + const int16_t ch_mult, + const int16_t pad_x, + const int16_t pad_y, + const int16_t stride_x, + const int16_t stride_y, + const int16_t dilation_x, + const int16_t dilation_y, + const int32_t *bias, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_offset, + uint8_t *output, + const uint16_t output_x, + const uint16_t output_y, + const int32_t output_activation_min, + const int32_t output_activation_max, + const int32_t output_shift, + const int32_t output_mult) +{ + (void)dilation_x; + (void)dilation_y; + + if (ch_mult % 4 == 0) + { + depthwise_conv_u8_mult_4(input, + input_x, + input_y, + input_ch, + kernel, + ch_mult * input_ch, + ch_mult, + kernel_x, + kernel_y, + pad_x, + pad_y, + stride_x, + stride_y, + bias, + output, + output_shift, + output_mult, + output_x, + output_y, + output_offset, + input_offset, + filter_offset, + output_activation_min, + output_activation_max); + } + else + { + depthwise_conv_u8_generic(input, + input_x, + input_y, + input_ch, + kernel, + ch_mult * input_ch, + ch_mult, + kernel_x, + kernel_y, + pad_x, + pad_y, + stride_x, + stride_y, + bias, + output, + output_shift, + output_mult, + output_x, + output_y, + output_offset, + input_offset, + filter_offset, + output_activation_min, + output_activation_max); + } + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c new file mode 100644 index 00000000..23c8e46b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_conv_wrapper_s8.c + * Description: Wrapper API to select appropriate depthwise conv API based + * on dimensions. + * + * $Date: 20. Dec 2021 + * $Revision: V.1.4.0 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * s8 Depthwise conv wrapper function + * + * Refer header file for details. + * + */ +arm_status arm_depthwise_conv_wrapper_s8(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *filter, + const cmsis_nn_dims *bias_dims, + const int32_t *bias, + const cmsis_nn_dims *output_dims, + q7_t *output) +{ + arm_status status = ARM_MATH_SUCCESS; + if (1 == dw_conv_params->ch_mult && input_dims->n == 1 && dw_conv_params->dilation.w == 1 && + dw_conv_params->dilation.h == 1) + { +#if !defined(ARM_MATH_MVEI) + if ((filter_dims->w == 3) && (filter_dims->h == 3) && (dw_conv_params->padding.h <= 1) && + (dw_conv_params->padding.w <= 1)) + { + status = arm_depthwise_conv_3x3_s8(ctx, + dw_conv_params, + quant_params, + input_dims, + input, + filter_dims, + filter, + bias_dims, + bias, + output_dims, + output); + } + else +#endif + { + status = arm_depthwise_conv_s8_opt(ctx, + dw_conv_params, + quant_params, + input_dims, + input, + filter_dims, + filter, + bias_dims, + bias, + output_dims, + output); + } + } + else + { + status = arm_depthwise_conv_s8(ctx, + dw_conv_params, + quant_params, + input_dims, + input, + filter_dims, + filter, + bias_dims, + bias, + output_dims, + output); + } + + /* Return to application */ + return status; +} + +int32_t arm_depthwise_conv_wrapper_s8_get_buffer_size(const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_dims *input_dims, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims) +{ + (void)dw_conv_params; + int32_t size = 0; + + if (input_dims->c == output_dims->c && input_dims->n == 1 && dw_conv_params->dilation.w == 1 && + dw_conv_params->dilation.h == 1) + { + size = arm_depthwise_conv_s8_opt_get_buffer_size(input_dims, filter_dims); + } + + return size; +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c new file mode 100644 index 00000000..729147fd --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c @@ -0,0 +1,422 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_separable_conv_HWC_q7.c + * Description: Q7 depthwise separable convolution function + * + * $Date: July 20, 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Q7 depthwise separable convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in equals ch_im_out + * + * Implementation: + * There are 3 nested loop here: + * Inner loop: calculate each output value with MAC instruction over an accumulator + * Mid loop: loop over different output channel + * Outer loop: loop over different output (x, y) + */ + +arm_status arm_depthwise_separable_conv_HWC_q7(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x; + int16_t i_ker_y, i_ker_x; + q7_t *colBuffer = (q7_t *)bufferA; + q7_t *pBuffer = colBuffer; + const q7_t *pBias = bias; + q7_t *pOut = Im_out; + uint16_t rowCnt; + uint16_t row_shift; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + /* we first do im2col here */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q7(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, ch_im_in); + } + else + { + /* arm_copy_q7((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + */ + memcpy(pBuffer, (q7_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* we will do the computation here for each channel */ + rowCnt = ch_im_out >> 2; + row_shift = 0; + pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = (dim_kernel * dim_kernel) >> 1; + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + row_shift += 4; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = arm_nn_read_q7x4(pB); + pB += ch_im_in; + opB = arm_nn_read_q7x4(pB); + pB += ch_im_in; + inB2 = __PKHTB(opB, inB1, 16); + inB1 = __PKHBT(inB1, opB, 16); + inA1 = arm_nn_read_q7x4(pA); + pA += ch_im_in; + opB = arm_nn_read_q7x4(pA); + pA += ch_im_in; + inA2 = __PKHTB(opB, inA1, 16); + inA1 = __PKHBT(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum3 = __SMLAD(opA, opB, sum3); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum4 = __SMLAD(opA, opB, sum4); + colCnt--; + } +#else + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = arm_nn_read_q7x4(pB); + pB += ch_im_in; + opB = arm_nn_read_q7x4(pB); + pB += ch_im_in; + inB2 = __PKHBT(opB, inB1, 16); + inB1 = __PKHTB(inB1, opB, 16); + inA1 = arm_nn_read_q7x4(pA); + pA += ch_im_in; + opB = arm_nn_read_q7x4(pA); + pA += ch_im_in; + inA2 = __PKHBT(opB, inA1, 16); + inA1 = __PKHTB(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum4 = __SMLAD(opA, opB, sum4); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum3 = __SMLAD(opA, opB, sum3); + colCnt--; + } + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + +#ifndef ARM_MATH_BIG_ENDIAN + /* + * r0 r1 r2 r3 r4 r5 + * inA1, inA2, inB1, inB2, opA, opB + */ + + asm volatile("COL_LOOP_%=:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhtb r3, r5, r2, ASR #16\n" + "pkhbt r2, r2, r5, LSL #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhtb r1, r5, r0, ASR #16\n" + "pkhbt r0, r0, r5, LSL #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum], r4, r5, %[sum]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n" + : [ sum ] "+r"(sum), + [ sum2 ] "+r"(sum2), + [ sum3 ] "+r"(sum3), + [ sum4 ] "+r"(sum4), + [ pB ] "+r"(pB), + [ pA ] "+r"(pA) + : [ colCnt ] "r"(colCnt), [ ch_im_in ] "r"(ch_im_in) + : "r0", "r1", "r2", "r3", "r4", "r5"); +#else + /* + * r0 r1 r2 r3 r4 r5 + * inA1, inA2, inB1, inB2, opA, opB + */ + asm volatile("COL_LOOP_%=:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhbt r3, r5, r2, LSL #16\n" + "pkhtb r2, r2, r5, ASR #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhbt r1, r5, r0, LSL #16\n" + "pkhtb r0, r0, r5, ASR #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum], r4, r5, %[sum]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n" + : [ sum ] "+r"(sum), + [ sum2 ] "+r"(sum2), + [ sum3 ] "+r"(sum3), + [ sum4 ] "+r"(sum4), + [ pB ] "+r"(pB), + [ pA ] "+r"(pA) + : [ colCnt ] "r"(colCnt), [ ch_im_in ] "r"(ch_im_in) + : "r0", "r1", "r2", "r3", "r4", "r5"); + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = (dim_kernel * dim_kernel) & 0x1; + while (colCnt) + { + union arm_nnword inA, inB; + inA.word = arm_nn_read_q7x4(pA); + pA += ch_im_in; + inB.word = arm_nn_read_q7x4(pB); + pB += ch_im_in; + sum += inA.bytes[0] * inB.bytes[0]; + sum2 += inA.bytes[1] * inB.bytes[1]; + sum3 += inA.bytes[2] * inB.bytes[2]; + sum4 += inA.bytes[3] * inB.bytes[3]; + colCnt--; + } + + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum3 >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = ch_im_out & 0x3; + while (rowCnt) + { + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = (dim_kernel * dim_kernel); + + row_shift += 1; + + while (colCnt) + { + q7_t A1 = *pA; + q7_t B1 = *pB; + pA += ch_im_in; + pB += ch_im_in; + sum += A1 * B1; + + colCnt--; + } + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + rowCnt--; + } + + /* clear counter and pointers */ + pBuffer = colBuffer; + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i_out_y, i_out_x, i_ch_out, i_ker_x, i_ker_y; + int conv_out; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output + conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); + for (i_ker_y = 0; i_ker_y < dim_kernel; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel; i_ker_x++) + { + int in_row = stride * i_out_y + i_ker_y - padding; + int in_col = stride * i_out_x + i_ker_x - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + i_ch_out] * + wt[(i_ker_y * dim_kernel + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out + i_out_x) * ch_im_out + i_ch_out] = + (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c new file mode 100644 index 00000000..829acf90 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c @@ -0,0 +1,427 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_separable_conv_HWC_q7_nonsquare.c + * Description: Q7 depthwise separable convolution function (non-square shape) + * + * $Date: July 20, 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Q7 depthwise separable convolution function (non-square shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding sizes x + * @param[in] padding_y padding sizes y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some constraints: + * ch_im_in is equal to ch_im_out + * + */ + +arm_status arm_depthwise_separable_conv_HWC_q7_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB) +{ + + (void)bufferB; + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + /* + * Implementation: + * There are 3 nested loop here: + * Inner loop: calculate each output value with MAC instruction over an accumulator + * Mid loop: loop over different output channel + * Outer loop: loop over different output (x, y) + * + */ + + int16_t i_out_y, i_out_x; + int16_t i_ker_y, i_ker_x; + q7_t *colBuffer = (q7_t *)bufferA; + q7_t *pBuffer = colBuffer; + const q7_t *pBias = bias; + q7_t *pOut = Im_out; + uint16_t rowCnt; + uint16_t row_shift; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* we first do im2col here */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q7(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, ch_im_in); + } + else + { + /* arm_copy_q7((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, + * ch_im_in); */ + memcpy(pBuffer, (q7_t *)Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* we will do the computation here for each channel */ + rowCnt = ch_im_out >> 2; + row_shift = 0; + pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = (dim_kernel_x * dim_kernel_y) >> 1; + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + row_shift += 4; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = arm_nn_read_q7x4(pB); + pB += ch_im_in; + opB = arm_nn_read_q7x4(pB); + pB += ch_im_in; + inB2 = __PKHTB(opB, inB1, 16); + inB1 = __PKHBT(inB1, opB, 16); + inA1 = arm_nn_read_q7x4(pA); + pA += ch_im_in; + opB = arm_nn_read_q7x4(pA); + pA += ch_im_in; + inA2 = __PKHTB(opB, inA1, 16); + inA1 = __PKHBT(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum3 = __SMLAD(opA, opB, sum3); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum4 = __SMLAD(opA, opB, sum4); + colCnt--; + } +#else + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = arm_nn_read_q7x4(pB); + pB += ch_im_in; + opB = arm_nn_read_q7x4(pB); + pB += ch_im_in; + inB2 = __PKHBT(opB, inB1, 16); + inB1 = __PKHTB(inB1, opB, 16); + inA1 = arm_nn_read_q7x4(pA); + pA += ch_im_in; + opB = arm_nn_read_q7x4(pA); + pA += ch_im_in; + inA2 = __PKHBT(opB, inA1, 16); + inA1 = __PKHTB(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum4 = __SMLAD(opA, opB, sum4); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum3 = __SMLAD(opA, opB, sum3); + colCnt--; + } + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + +#ifndef ARM_MATH_BIG_ENDIAN + // r0 r1 r2 r3 r4 r5 + // inA1, inA2, inB1, inB2, opA, opB + asm volatile("COL_LOOP:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhtb r3, r5, r2, ASR #16\n" + "pkhbt r2, r2, r5, LSL #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhtb r1, r5, r0, ASR #16\n" + "pkhbt r0, r0, r5, LSL #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum], r4, r5, %[sum]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP\n" + : [ sum ] "+r"(sum), + [ sum2 ] "+r"(sum2), + [ sum3 ] "+r"(sum3), + [ sum4 ] "+r"(sum4), + [ pB ] "+r"(pB), + [ pA ] "+r"(pA) + : [ colCnt ] "r"(colCnt), [ ch_im_in ] "r"(ch_im_in) + : "r0", "r1", "r2", "r3", "r4", "r5"); +#else + // r0 r1 r2 r3 r4 r5 + // inA1, inA2, inB1, inB2, opA, opB + asm volatile("COL_LOOP:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhbt r3, r5, r2, LSL #16\n" + "pkhtb r2, r2, r5, ASR #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhbt r1, r5, r0, LSL #16\n" + "pkhtb r0, r0, r5, ASR #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum], r4, r5, %[sum]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP\n" + : [ sum ] "+r"(sum), + [ sum2 ] "+r"(sum2), + [ sum3 ] "+r"(sum3), + [ sum4 ] "+r"(sum4), + [ pB ] "+r"(pB), + [ pA ] "+r"(pA) + : [ colCnt ] "r"(colCnt), [ ch_im_in ] "r"(ch_im_in) + : "r0", "r1", "r2", "r3", "r4", "r5"); +#endif /*ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = (dim_kernel_x * dim_kernel_y) & 0x1; + while (colCnt) + { + union arm_nnword inA, inB; + inA.word = arm_nn_read_q7x4(pA); + pA += ch_im_in; + inB.word = arm_nn_read_q7x4(pB); + pB += ch_im_in; + sum += inA.bytes[0] * inB.bytes[0]; + sum2 += inA.bytes[1] * inB.bytes[1]; + sum3 += inA.bytes[2] * inB.bytes[2]; + sum4 += inA.bytes[3] * inB.bytes[3]; + colCnt--; + } + + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum3 >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = ch_im_out & 0x3; + while (rowCnt) + { + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = (dim_kernel_x * dim_kernel_y); + + row_shift += 1; + + while (colCnt) + { + q7_t A1 = *pA; + q7_t B1 = *pB; + pA += ch_im_in; + pB += ch_im_in; + sum += A1 * B1; + + colCnt--; + } + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + rowCnt--; + } + + // clear counter and pointers + pBuffer = colBuffer; + } + } + +#else + (void)bufferA; + + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i_out_y, i_out_x, i_ch_out; + int i_ker_y, i_ker_x; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output + int conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); + for (i_ker_y = 0; i_ker_y < dim_kernel_y; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel_x; i_ker_x++) + { + int in_row = stride_y * i_out_y + i_ker_y - padding_y; + int in_col = stride_x * i_out_x + i_ker_x - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + i_ch_out] * + wt[(i_ker_y * dim_kernel_x + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out_x + i_out_x) * ch_im_out + i_ch_out] = + (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c new file mode 100644 index 00000000..481eeba6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c @@ -0,0 +1,218 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_depthwise_conv_s8_core.c + * Description: Depthwise convolution on im2col buffers. + * + * $Date: 09. October 2020 + * $Revision: V.1.0.4 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/* + * Depthwise conv on an im2col buffer where the input channel equals + * output channel. + * + * Refer header file for details. + * + */ + +q7_t *arm_nn_depthwise_conv_s8_core(const q7_t *row, + const q15_t *col, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t kernel_size, + const int32_t *const output_bias, + q7_t *out) +{ +#if defined(ARM_MATH_MVEI) + int32_t ch_per_loop = num_ch / 4; + + const int32_t *bias = output_bias; + int8_t *out_tmp = out; + + int32_t idx = 0; + + while (ch_per_loop > 0) + { + int32x4_t ip_0; + int32x4_t ip_1; + int32_t ker_loop = kernel_size / 3; + int32x4_t out_0 = vldrwq_s32(bias); + int32x4_t out_1 = out_0; + bias += 4; + + const int32_t offset = idx * 4; + const int8_t *row_0 = row + offset; + const int16_t *col_0 = col + offset; + const int16_t *col_1 = col + kernel_size * num_ch + offset; + + int32x4_t ker_0 = vldrbq_s32(row_0); + + while (ker_loop > 0) + { + const int8_t *row_1 = row_0 + num_ch; + const int8_t *row_2 = row_0 + 2 * num_ch; + const int32x4_t ker_1 = vldrbq_s32(row_1); + const int32x4_t ker_2 = vldrbq_s32(row_2); + + ip_0 = vldrhq_s32(col_0); + ip_1 = vldrhq_s32(col_1); + col_0 += num_ch; + col_1 += num_ch; + + out_0 += vmulq_s32(ip_0, ker_0); + out_1 += vmulq_s32(ip_1, ker_0); + + ip_0 = vldrhq_s32(col_0); + ip_1 = vldrhq_s32(col_1); + col_0 += num_ch; + col_1 += num_ch; + + out_0 += vmulq_s32(ip_0, ker_1); + out_1 += vmulq_s32(ip_1, ker_1); + + ip_0 = vldrhq_s32(col_0); + ip_1 = vldrhq_s32(col_1); + col_0 += num_ch; + col_1 += num_ch; + + out_0 += vmulq_s32(ip_0, ker_2); + out_1 += vmulq_s32(ip_1, ker_2); + row_0 += 3 * num_ch; + + ker_0 = vldrbq_s32(row_0); + ker_loop--; + } + + idx++; + /* Handle tail kernel elements */ + ker_loop = kernel_size - ((kernel_size / 3) * 3); + while (ker_loop > 0) + { + ip_0 = vldrhq_s32(col_0); + ip_1 = vldrhq_s32(col_1); + + out_0 += vmulq_s32(ip_0, ker_0); + out_1 += vmulq_s32(ip_1, ker_0); + + col_0 += num_ch; + col_1 += num_ch; + + ip_0 = vldrhq_s32(col_0); + ip_1 = vldrhq_s32(col_1); + + row_0 += num_ch; + ker_0 = vldrbq_s32(row_0); + ker_loop--; + } + const int32x4_t mult = vldrwq_s32(out_mult); + const int32x4_t shift = vldrwq_s32(out_shift); + out_mult += 4; + out_shift += 4; + + out_0 = arm_requantize_mve_32x4(out_0, mult, shift); + out_1 = arm_requantize_mve_32x4(out_1, mult, shift); + + out_0 = vaddq_n_s32(out_0, out_offset); + out_0 = vmaxq_s32(out_0, vdupq_n_s32(activation_min)); + out_0 = vminq_s32(out_0, vdupq_n_s32(activation_max)); + vstrbq_s32(out_tmp, out_0); + + out_1 = vaddq_n_s32(out_1, out_offset); + out_1 = vmaxq_s32(out_1, vdupq_n_s32(activation_min)); + out_1 = vminq_s32(out_1, vdupq_n_s32(activation_max)); + vstrbq_s32(out_tmp + num_ch, out_1); + + out_tmp += 4; + ch_per_loop--; + } + + int32_t tail_ch = num_ch & 3; + if (tail_ch != 0) + { + int32_t ch_idx = (num_ch & ~3); + int32x4_t col_0_sum; + int32x4_t col_1_sum; + + const int32_t single_buffer_size = kernel_size * num_ch; + for (int i = 0; i < tail_ch; i++) + { + const int16_t *col_pos_0 = col + ch_idx; + const int16_t *col_pos_1 = col_pos_0 + single_buffer_size; + + const int8_t *row_pos = row + ch_idx; + int32_t sum_0 = bias[i]; + int32_t sum_1 = bias[i]; + + for (int j = 0; j < kernel_size; j++) + { + const int8_t row_val = row_pos[j * num_ch]; + sum_0 += row_val * col_pos_0[j * num_ch]; + sum_1 += row_val * col_pos_1[j * num_ch]; + } + col_0_sum[i] = sum_0; + col_1_sum[i] = sum_1; + + ch_idx++; + } + const mve_pred16_t p = vctp32q((uint32_t)tail_ch); + const int32x4_t mult = vldrwq_z_s32(out_mult, p); + const int32x4_t shift = vldrwq_z_s32(out_shift, p); + + col_0_sum = arm_requantize_mve_32x4(col_0_sum, mult, shift); + col_1_sum = arm_requantize_mve_32x4(col_1_sum, mult, shift); + + col_0_sum = vaddq_n_s32(col_0_sum, out_offset); + col_0_sum = vmaxq_s32(col_0_sum, vdupq_n_s32(activation_min)); + col_0_sum = vminq_s32(col_0_sum, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out_tmp, col_0_sum, p); + + col_1_sum = vaddq_n_s32(col_1_sum, out_offset); + col_1_sum = vmaxq_s32(col_1_sum, vdupq_n_s32(activation_min)); + col_1_sum = vminq_s32(col_1_sum, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out_tmp + num_ch, col_1_sum, p); + + out_tmp += tail_ch; + } + + return out_tmp + num_ch; +#else + (void)row; + (void)col; + (void)num_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)kernel_size; + (void)output_bias; + (void)out; + return NULL; +#endif +} diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c new file mode 100644 index 00000000..05c95b66 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c @@ -0,0 +1,186 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_kernel_q7_q15.c + * Description: Matrix-multiplication function for convolution + * + * $Date: January 26, 2021 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @brief Matrix-multiplication function for convolution. + * + * @details Refer to header file for details. + * + */ + +q7_t *arm_nn_mat_mult_kernel_q7_q15(const q7_t *pA, + const q15_t *pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut) +{ +#if defined(ARM_MATH_DSP) + /* set up the second output pointers */ + q7_t *pOut2 = pOut + ch_im_out; + const q7_t *pBias = bias; + + uint16_t rowCnt = ch_im_out >> 1; + /* this loop over rows in A */ + while (rowCnt) + { + /* setup pointers for B */ + const q15_t *pB = pInBuffer; + const q15_t *pB2 = pB + numCol_A; + + /* align the second pointer for A */ + const q7_t *pA2 = pA + numCol_A; + + /* init the sum with bias */ + q31_t sum = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = numCol_A >> 2; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA11, inA12, inA21, inA22; + + q31_t inB1 = arm_nn_read_q15x2_ia(&pB); + q31_t inB2 = arm_nn_read_q15x2_ia(&pB2); + + pA = read_and_pad(pA, &inA11, &inA12); + pA2 = read_and_pad(pA2, &inA21, &inA22); + + sum = __SMLAD(inA11, inB1, sum); + sum2 = __SMLAD(inA11, inB2, sum2); + sum3 = __SMLAD(inA21, inB1, sum3); + sum4 = __SMLAD(inA21, inB2, sum4); + + inB1 = arm_nn_read_q15x2_ia(&pB); + inB2 = arm_nn_read_q15x2_ia(&pB2); + + sum = __SMLAD(inA12, inB1, sum); + sum2 = __SMLAD(inA12, inB2, sum2); + sum3 = __SMLAD(inA22, inB1, sum3); + sum4 = __SMLAD(inA22, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = numCol_A & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + q7_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum3 >> out_shift), 8); + *pOut2++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + *pOut2++ = (q7_t)__SSAT((sum4 >> out_shift), 8); + + /* skip the row computed with A2 */ + pA += numCol_A; + rowCnt--; + } /* for over ch_im_out */ + + /* compute left-over row if any */ + if (ch_im_out & 0x1) + { + /* setup pointers for B */ + const q15_t *pB = pInBuffer; + const q15_t *pB2 = pB + numCol_A; + + /* load the bias */ + q31_t sum = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = numCol_A >> 2; + while (colCnt) + { + q31_t inA11, inA12; + + q31_t inB1 = arm_nn_read_q15x2_ia(&pB); + q31_t inB2 = arm_nn_read_q15x2_ia(&pB2); + + pA = read_and_pad(pA, &inA11, &inA12); + + sum = __SMLAD(inA11, inB1, sum); + sum2 = __SMLAD(inA11, inB2, sum2); + + inB1 = arm_nn_read_q15x2_ia(&pB); + inB2 = arm_nn_read_q15x2_ia(&pB2); + + sum = __SMLAD(inA12, inB1, sum); + sum2 = __SMLAD(inA12, inB2, sum2); + + colCnt--; + } + colCnt = numCol_A & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + colCnt--; + } + + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pOut2++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + } + + pOut += ch_im_out; + + /* return the new output pointer with offset */ + return pOut; +#else + (void)pA; + (void)pInBuffer; + (void)ch_im_out; + (void)numCol_A; + (void)bias_shift; + (void)out_shift; + (void)bias; + (void)pOut; + /* To be completed */ + return NULL; +#endif /* ARM_MATH_DSP */ +} diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c new file mode 100644 index 00000000..0870ac32 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_kernel_q7_q15_reordered.c + * Description: Matrix-multiplication function for convolution with reordered columns + * + * $Date: January 26, 2021 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @brief Matrix-multiplication function for convolution with re-ordered input. + * + * @details Refer to header file for details. + * + */ + +q7_t *arm_nn_mat_mult_kernel_q7_q15_reordered(const q7_t *pA, + const q15_t *pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut) +{ + +#if defined(ARM_MATH_DSP) + /* set up the second output pointers */ + q7_t *pOut2 = pOut + ch_im_out; + int i; + + /* this loop over rows in A */ + for (i = 0; i < ch_im_out; i += 2) + { + /* setup pointers for B */ + const q15_t *pB = pInBuffer; + const q15_t *pB2 = pB + numCol_A; + + /* align the second pointer for A */ + const q7_t *pA2 = pA + numCol_A; + + /* init the sum with bias */ + q31_t sum = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(bias[i + 1]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(bias[i + 1]) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = numCol_A >> 2; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA11, inA12, inA21, inA22; + + q31_t inB1 = arm_nn_read_q15x2_ia(&pB); + q31_t inB2 = arm_nn_read_q15x2_ia(&pB2); + + pA = read_and_pad_reordered(pA, &inA11, &inA12); + pA2 = read_and_pad_reordered(pA2, &inA21, &inA22); + + sum = __SMLAD(inA11, inB1, sum); + sum2 = __SMLAD(inA11, inB2, sum2); + sum3 = __SMLAD(inA21, inB1, sum3); + sum4 = __SMLAD(inA21, inB2, sum4); + + inB1 = arm_nn_read_q15x2_ia(&pB); + inB2 = arm_nn_read_q15x2_ia(&pB2); + + sum = __SMLAD(inA12, inB1, sum); + sum2 = __SMLAD(inA12, inB2, sum2); + sum3 = __SMLAD(inA22, inB1, sum3); + sum4 = __SMLAD(inA22, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = numCol_A & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + q7_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum3 >> out_shift), 8); + *pOut2++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + *pOut2++ = (q7_t)__SSAT((sum4 >> out_shift), 8); + + /* skip the row computed with A2 */ + pA += numCol_A; + } /* for over ch_im_out */ + + pOut += ch_im_out; + + /* return the new output pointer with offset */ + return pOut; +#else + (void)pA; + (void)pInBuffer; + (void)ch_im_out; + (void)numCol_A; + (void)bias_shift; + (void)out_shift; + (void)bias; + (void)pOut; + /* To be completed */ + return NULL; +#endif /* ARM_MATH_DSP */ +} diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c new file mode 100644 index 00000000..cb300689 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c @@ -0,0 +1,245 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_kernel_s8_s16.c + * Description: Matrix-multiplication function for convolution + * + * $Date: 14. December 2021 + * $Revision: V.1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/* + * Matrix-multiplication function for convolution with per-channel requantization. + * + * Refer header file for details. + * + */ + +q7_t *arm_nn_mat_mult_kernel_s8_s16(const q7_t *input_a, + const q15_t *input_b, + const uint16_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t num_col_a, + const int32_t *const output_bias, + q7_t *out_0) +{ +#if !defined(ARM_MATH_MVEI) + /* set up the second output pointers */ + q7_t *out_1 = out_0 + output_ch; + const int32_t *bias = output_bias; + + uint16_t row_count = output_ch / 2; + const q7_t *ip_a0 = input_a; + /* this loop over rows in A */ + while (row_count) + { + /* setup pointers for B */ + const q15_t *ip_b0 = input_b; + const q15_t *ip_b1 = ip_b0 + num_col_a; + + /* align the second pointer for A */ + const q7_t *ip_a1 = ip_a0 + num_col_a; + + q31_t ch_0_out_0 = 0; + q31_t ch_0_out_1 = 0; + q31_t ch_1_out_0 = 0; + q31_t ch_1_out_1 = 0; + /* Init accumulator with bias for channel N and N + 1 */ + if (bias) + { + ch_0_out_0 = *bias; + ch_0_out_1 = *bias++; + ch_1_out_0 = *bias; + ch_1_out_1 = *bias++; + } + +#if defined(ARM_MATH_DSP) + uint16_t col_count = num_col_a / 4; + /* accumulate over the vector */ + while (col_count) + { + q31_t a01, a02, a11, a12; + q31_t b0 = arm_nn_read_q15x2_ia(&ip_b0); + q31_t b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ip_a0 = read_and_pad(ip_a0, &a01, &a02); + ip_a1 = read_and_pad(ip_a1, &a11, &a12); + + ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + ch_1_out_0 = __SMLAD(a11, b0, ch_1_out_0); + ch_1_out_1 = __SMLAD(a11, b1, ch_1_out_1); + + b0 = arm_nn_read_q15x2_ia(&ip_b0); + b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + ch_1_out_0 = __SMLAD(a12, b0, ch_1_out_0); + ch_1_out_1 = __SMLAD(a12, b1, ch_1_out_1); + + col_count--; + } /* while over col_count */ + col_count = num_col_a & 0x3; +#else + uint16_t col_count = num_col_a; +#endif + while (col_count) + { + q7_t a0 = *ip_a0++; + q15_t b0 = *ip_b0++; + q7_t a1 = *ip_a1++; + q15_t b1 = *ip_b1++; + + ch_0_out_0 += a0 * b0; + ch_0_out_1 += a0 * b1; + ch_1_out_0 += a1 * b0; + ch_1_out_1 += a1 * b1; + col_count--; + } /* while over col_count */ + + ch_0_out_0 = arm_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_0 += out_offset; + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q7_t)ch_0_out_0; + + ch_0_out_1 = arm_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + ch_0_out_1 += out_offset; + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q7_t)ch_0_out_1; + out_mult++; + out_shift++; + + ch_1_out_0 = arm_nn_requantize(ch_1_out_0, *out_mult, *out_shift); + ch_1_out_0 += out_offset; + ch_1_out_0 = MAX(ch_1_out_0, activation_min); + ch_1_out_0 = MIN(ch_1_out_0, activation_max); + *out_0++ = (q7_t)ch_1_out_0; + + ch_1_out_1 = arm_nn_requantize(ch_1_out_1, *out_mult, *out_shift); + ch_1_out_1 += out_offset; + ch_1_out_1 = MAX(ch_1_out_1, activation_min); + ch_1_out_1 = MIN(ch_1_out_1, activation_max); + *out_1++ = (q7_t)ch_1_out_1; + out_mult++; + out_shift++; + + /* skip row */ + ip_a0 += num_col_a; + row_count--; + } + + /* compute the last odd numbered row if any */ + if (output_ch & 0x1) + { + /* setup pointers for B */ + const q15_t *ip_b0 = input_b; + const q15_t *ip_b1 = ip_b0 + num_col_a; + + q31_t ch_0_out_0 = 0; + q31_t ch_0_out_1 = 0; + + /* load the bias */ + if (bias) + { + ch_0_out_0 = *bias; + ch_0_out_1 = *bias++; + } + +#if defined(ARM_MATH_DSP) + uint16_t col_count = num_col_a >> 2; + while (col_count) + { + q31_t a01, a02; + q31_t b0 = arm_nn_read_q15x2_ia(&ip_b0); + q31_t b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ip_a0 = read_and_pad(ip_a0, &a01, &a02); + + ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + + b0 = arm_nn_read_q15x2_ia(&ip_b0); + b1 = arm_nn_read_q15x2_ia(&ip_b1); + ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + + col_count--; + } + col_count = num_col_a & 0x3; +#else + uint16_t col_count = num_col_a; +#endif + while (col_count) + { + q7_t a0 = *ip_a0++; + q15_t b0 = *ip_b0++; + q15_t b1 = *ip_b1++; + + ch_0_out_0 += a0 * b0; + ch_0_out_1 += a0 * b1; + col_count--; + } + ch_0_out_0 = arm_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_0 += out_offset; + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q7_t)ch_0_out_0; + + ch_0_out_1 = arm_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + ch_0_out_1 += out_offset; + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q7_t)ch_0_out_1; + out_mult++; + out_shift++; + } + + out_0 += output_ch; + + /* return the new output pointer with offset */ + return out_0; +#else + (void)input_a; + (void)input_b; + (void)output_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)num_col_a; + (void)output_bias; + (void)out_0; + /* To be completed */ + return NULL; +#endif +} diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16_reordered.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16_reordered.c new file mode 100644 index 00000000..842a1803 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16_reordered.c @@ -0,0 +1,201 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_kernel_s8_s16_reordered.c + * Description: Matrix-multiplication function for convolution with reordered columns + * + * $Date: 09. October 2020 + * $Revision: V.1.0.3 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/* + * Matrix-multiplication with re-ordered input and bias inputs for convolution with per-channel + * requantization. The re-ordering is a consequence of sign extension is done by the SXTB16 command. + * + * Refer header file for details. This function differs from arm_nn_mat_mult_kernel_s8_s16(), in that it uses + * read_and_pad_reordered() instead of arm_nn_mat_mult_kernel_s8_s16(). Investigating the cycles impact and + * unifying these two functions is a potential future improvement. + * + */ + +q7_t *arm_nn_mat_mult_kernel_s8_s16_reordered(const q7_t *input_a, + const q15_t *input_b, + const uint16_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t num_col_a, + const int32_t *const output_bias, + q7_t *out_0) +{ +#if defined(ARM_MATH_DSP) + /* set up the second output pointers */ + q7_t *out_1 = out_0 + output_ch; + const int32_t *bias = output_bias; + + uint16_t row_count = output_ch / 2; + const q7_t *ip_a0 = input_a; + /* this loop over rows in A */ + while (row_count) + { + /* setup pointers for B */ + const q15_t *ip_b0 = input_b; + const q15_t *ip_b1 = ip_b0 + num_col_a; + + /* align the second pointer for A */ + const q7_t *ip_a1 = ip_a0 + num_col_a; + + /* Init accumulator with bias for channel N and N + 1 */ + q31_t ch_0_out_0 = *bias; + q31_t ch_0_out_1 = *bias++; + q31_t ch_1_out_0 = *bias; + q31_t ch_1_out_1 = *bias++; + + uint16_t col_count = num_col_a / 4; + /* accumulate over the vector */ + while (col_count) + { + q31_t a01, a02, a11, a12; + q31_t b0 = arm_nn_read_q15x2_ia(&ip_b0); + q31_t b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ip_a0 = read_and_pad_reordered(ip_a0, &a01, &a02); + ip_a1 = read_and_pad_reordered(ip_a1, &a11, &a12); + + ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + ch_1_out_0 = __SMLAD(a11, b0, ch_1_out_0); + ch_1_out_1 = __SMLAD(a11, b1, ch_1_out_1); + + b0 = arm_nn_read_q15x2_ia(&ip_b0); + b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + ch_1_out_0 = __SMLAD(a12, b0, ch_1_out_0); + ch_1_out_1 = __SMLAD(a12, b1, ch_1_out_1); + + col_count--; + } /* while over col_count */ + + ch_0_out_0 = arm_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_0 += out_offset; + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q7_t)ch_0_out_0; + + ch_0_out_1 = arm_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + ch_0_out_1 += out_offset; + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q7_t)ch_0_out_1; + out_mult++; + out_shift++; + + ch_1_out_0 = arm_nn_requantize(ch_1_out_0, *out_mult, *out_shift); + ch_1_out_0 += out_offset; + ch_1_out_0 = MAX(ch_1_out_0, activation_min); + ch_1_out_0 = MIN(ch_1_out_0, activation_max); + *out_0++ = (q7_t)ch_1_out_0; + + ch_1_out_1 = arm_nn_requantize(ch_1_out_1, *out_mult, *out_shift); + ch_1_out_1 += out_offset; + ch_1_out_1 = MAX(ch_1_out_1, activation_min); + ch_1_out_1 = MIN(ch_1_out_1, activation_max); + *out_1++ = (q7_t)ch_1_out_1; + out_mult++; + out_shift++; + + /* skip row */ + ip_a0 += num_col_a; + row_count--; + } + + if (output_ch & 1) + { + /* setup pointers for B */ + const q15_t *ip_b0 = input_b; + const q15_t *ip_b1 = ip_b0 + num_col_a; + + /* Init accumulator with bias for channel N + 1 */ + q31_t ch_0_out_0 = *bias; + q31_t ch_0_out_1 = ch_0_out_0; + + int32_t col_count = num_col_a / 4; + while (col_count) + { + q31_t a01, a02; + q31_t b0 = arm_nn_read_q15x2_ia(&ip_b0); + q31_t b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ip_a0 = read_and_pad_reordered(ip_a0, &a01, &a02); + + ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + + b0 = arm_nn_read_q15x2_ia(&ip_b0); + b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + + col_count--; + } /* while over col_count */ + + ch_0_out_0 = arm_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_0 += out_offset; + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q7_t)ch_0_out_0; + + ch_0_out_1 = arm_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + ch_0_out_1 += out_offset; + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q7_t)ch_0_out_1; + } + + out_0 += output_ch; + + /* return the new output pointer with offset */ + return out_0; +#else + (void)input_a; + (void)input_b; + (void)output_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)num_col_a; + (void)output_bias; + (void)out_0; + /* To be completed */ + return NULL; +#endif +} diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c new file mode 100644 index 00000000..adfa702d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c @@ -0,0 +1,180 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_s8.c + * Description: General Matrix-multiplication function + * + * $Date: 27. October 2021 + * $Revision: V.2.0.6 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/* + * s8 General matrix multiplication function with per-channel requantization for upto 4 column batches. + * + * Refer header file for details. + * + */ + +q7_t *arm_nn_mat_mult_s8(const q7_t *input_row, + const q7_t *input_col, + const uint16_t output_ch, + const uint16_t col_batches, + const int32_t *output_shift, + const int32_t *output_mult, + const int32_t out_offset, + const int32_t col_offset, + const int32_t row_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t row_len, + const int32_t *const bias, + q7_t *out) +{ +#if defined(ARM_MATH_MVEI) + (void)row_offset; + if (col_batches == 4) + { + for (int i_out_ch = 0; i_out_ch < output_ch; i_out_ch++) + { + int32_t row_len_tmp = row_len; + const int8_t *ip_r0 = input_row + (i_out_ch * row_len); + const int8_t *ip_c0 = input_col; + const int8_t *ip_c1 = input_col + row_len; + const int8_t *ip_c2 = input_col + (2 * row_len); + const int8_t *ip_c3 = input_col + (3 * row_len); + + int32_t acc_0 = 0; + int32_t acc_1 = 0; + int32_t acc_2 = 0; + int32_t acc_3 = 0; + const int32_t row_loop_cnt = (row_len + 7) / 8; + + for (int i_row_loop = 0; i_row_loop < row_loop_cnt; i_row_loop++) + { + mve_pred16_t p = vctp16q((uint32_t)row_len_tmp); + const int16x8_t offset = vdupq_m_n_s16(vuninitializedq_s16(), col_offset, p); + row_len_tmp -= 8; + + int16x8_t c0 = vldrbq_s16(ip_c0); + ip_c0 += 8; + c0 = vaddq_s16(c0, offset); + + int16x8_t c1 = vldrbq_s16(ip_c1); + ip_c1 += 8; + c1 = vaddq_s16(c1, offset); + + int16x8_t c2 = vldrbq_s16(ip_c2); + ip_c2 += 8; + c2 = vaddq_s16(c2, offset); + + int16x8_t c3 = vldrbq_s16(ip_c3); + ip_c3 += 8; + c3 = vaddq_s16(c3, offset); + + int16x8_t r0 = vldrbq_z_s16(ip_r0, p); + ip_r0 += 8; + + acc_0 = vmladavaq_p_s16(acc_0, r0, c0, p); + acc_1 = vmladavaq_p_s16(acc_1, r0, c1, p); + acc_2 = vmladavaq_p_s16(acc_2, r0, c2, p); + acc_3 = vmladavaq_p_s16(acc_3, r0, c3, p); + } + + int32x4_t res = {acc_0, acc_1, acc_2, acc_3}; + if (bias) + { + res = vaddq_n_s32(res, bias[i_out_ch]); + } + res = arm_requantize_mve(res, output_mult[i_out_ch], output_shift[i_out_ch]); + res = vaddq_n_s32(res, out_offset); + + res = vmaxq_s32(res, vdupq_n_s32(activation_min)); + res = vminq_s32(res, vdupq_n_s32(activation_max)); + + const uint32x4_t scatter_offset = {0, output_ch, output_ch * 2, output_ch * 3}; + vstrbq_scatter_offset_s32(&out[i_out_ch], scatter_offset, res); + } + out += 4 * output_ch; + } + else + { + for (int i_col_batch = (col_batches & ~0x3); i_col_batch < (col_batches & 0x3); i_col_batch++) + { + for (int i_out_ch = 0; i_out_ch < output_ch; i_out_ch++) + { + int32_t row_len_tmp = row_len; + + const int8_t *ip_r0 = input_row + (i_out_ch * row_len); + const int8_t *ip_c0 = input_col + (i_col_batch * row_len); + int32_t acc_0 = 0; + const int32_t row_loop_cnt = (row_len + 7) / 8; + + for (int i_row_loop = 0; i_row_loop < row_loop_cnt; i_row_loop++) + { + const mve_pred16_t p = vctp16q((uint32_t)row_len_tmp); + const int16x8_t offset = vdupq_m_n_s16(vuninitializedq_s16(), col_offset, p); + row_len_tmp -= 8; + + int16x8_t c0 = vldrbq_s16(ip_c0); + ip_c0 += 8; + c0 = vaddq_s16(c0, offset); + + int16x8_t r0 = vldrbq_z_s16(ip_r0, p); + ip_r0 += 8; + acc_0 = vmladavaq_p_s16(acc_0, r0, c0, p); + } + + if (bias) + { + acc_0 += bias[i_out_ch]; + } + acc_0 = arm_nn_requantize(acc_0, output_mult[i_out_ch], output_shift[i_out_ch]); + acc_0 += out_offset; + acc_0 = MAX(acc_0, activation_min); + acc_0 = MIN(acc_0, activation_max); + out[i_out_ch] = (q7_t)acc_0; + } + out += output_ch; + } + } + return out; + +#else + (void)input_row; + (void)input_col; + (void)output_ch; + (void)col_batches; + (void)output_shift; + (void)output_mult; + (void)out_offset; + (void)col_offset; + (void)row_offset; + (void)activation_min; + (void)activation_max; + (void)row_len; + (void)bias; + (void)out; + return NULL; +#endif +} diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/CMakeLists.txt new file mode 100644 index 00000000..cccd996f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/CMakeLists.txt @@ -0,0 +1,21 @@ +# +# Copyright (c) 2019-2021 Arm Limited. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +file(GLOB SRC "./*_s8.c") +target_sources(cmsis-nn PRIVATE ${SRC} arm_fully_connected_s16.c) + diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c b/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c new file mode 100644 index 00000000..9eb02ebe --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c @@ -0,0 +1,197 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_mat_q7_vec_q15.c + * Description: Mixed Q15-Q7 fully-connected layer function + * + * $Date: 20. July 2021 + * $Revision: V.1.1.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/** + * @brief Mixed Q15-Q7 fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + * Q7_Q15 version of the fully connected layer + * + * Weights are in q7_t and Activations are in q15_t + * + */ + +arm_status arm_fully_connected_mat_q7_vec_q15(const q15_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q15_t *pOut, + q15_t *vec_buffer) +{ + (void)vec_buffer; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + const q7_t *pB2; + q15_t *pO = pOut; + const q7_t *pBias = bias; + const q15_t *pA = pV; + + uint16_t rowCnt = num_of_rows >> 1; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + pB2 = pB + dim_vec; + + while (colCnt) + { + q31_t inV, inM11, inM12, inM21, inM22; + pB = read_and_pad(pB, &inM11, &inM12); + pB2 = read_and_pad(pB2, &inM21, &inM22); + + inV = arm_nn_read_q15x2_ia(&pA); + + sum = __SMLAD(inV, inM11, sum); + sum2 = __SMLAD(inV, inM21, sum2); + + inV = arm_nn_read_q15x2_ia(&pA); + + sum = __SMLAD(inV, inM12, sum); + sum2 = __SMLAD(inV, inM22, sum2); + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + q7_t inM2 = *pB2++; + + sum += inV * inM; + sum2 += inV * inM2; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum2 >> out_shift), 16)); + + /*adjust the pointers and counters */ + pB += dim_vec; + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x1; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = read_and_pad(pB, &inM11, &inM12); + + inV1 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV1, inM11, sum); + + inV2 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + int i, j; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t)__SSAT((ip_out >> out_shift), 16); + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of FC group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c b/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c new file mode 100644 index 00000000..a2da7729 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c @@ -0,0 +1,417 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_mat_q7_vec_q15_opt.c + * Description: Mixed Q15-Q7 opt fully-connected layer function + * + * $Date: 20. July 2021 + * $Revision: V.1.1.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/** + * @brief Mixed Q15-Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + * Q7_Q15 version of the fully connected layer + * + * Weights are in q7_t and Activations are in q15_t + * + * Limitation: x4 version requires weight reordering to work + * + * Here we use only one pointer to read 4 rows in the weight + * matrix. So if the original q7_t matrix looks like this: + * + * | a11 | a12 | a13 | a14 | a15 | a16 | a17 | + * + * | a21 | a22 | a23 | a24 | a25 | a26 | a27 | + * + * | a31 | a32 | a33 | a34 | a35 | a36 | a37 | + * + * | a41 | a42 | a43 | a44 | a45 | a46 | a47 | + * + * | a51 | a52 | a53 | a54 | a55 | a56 | a57 | + * + * | a61 | a62 | a63 | a64 | a65 | a66 | a67 | + * + * We operates on multiple-of-4 rows, so the first four rows becomes + * + * | a11 | a21 | a12 | a22 | a31 | a41 | a32 | a42 | + * + * | a13 | a23 | a14 | a24 | a33 | a43 | a34 | a44 | + * + * | a15 | a25 | a16 | a26 | a35 | a45 | a36 | a46 | + * + * The column left over will be in-order. + * which is: + * | a17 | a27 | a37 | a47 | + * + * For the left-over rows, we do 1x1 computation, so the data remains + * as its original order. + * + * So the stored weight matrix looks like this: + * + * | a11 | a21 | a12 | a22 | a31 | a41 | + * + * | a32 | a42 | a13 | a23 | a14 | a24 | + * + * | a33 | a43 | a34 | a44 | a15 | a25 | + * + * | a16 | a26 | a35 | a45 | a36 | a46 | + * + * | a17 | a27 | a37 | a47 | a51 | a52 | + * + * | a53 | a54 | a55 | a56 | a57 | a61 | + * + * | a62 | a63 | a64 | a65 | a66 | a67 | + * + */ + +arm_status arm_fully_connected_mat_q7_vec_q15_opt(const q15_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q15_t *pOut, + q15_t *vec_buffer) +{ + + (void)vec_buffer; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + q15_t *pO = pOut; + const q7_t *pBias = bias; + const q15_t *pA = pV; + + uint16_t rowCnt = num_of_rows >> 2; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = arm_nn_read_q15x2_ia(&pA); + inM11 = arm_nn_read_q7x4_ia(&pB); + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM11, inV, sum); + sum2 = __SMLAD(inM12, inV, sum2); + inM13 = arm_nn_read_q7x4_ia(&pB); + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM13, inV, sum3); + sum4 = __SMLAD(inM14, inV, sum4); + colCnt--; + } + +#else + + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = *__SIMD32(pA)++; + inM11 = arm_nn_read_q7x4_ia(&pB); + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM12, inV, sum); + sum2 = __SMLAD(inM11, inV, sum2); + inM13 = arm_nn_read_q7x4_ia(&pB); + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM14, inV, sum3); + sum4 = __SMLAD(inM13, inV, sum4); + colCnt--; + } + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + + /* + * register needed: + * loop counter: colCnt + * accumulators: sum, sum2, sum3, sum4 + * pointers: pB, pA + * weight data: inM11, inM12, inM13, inM14 + * activation data: inV + */ + +#ifndef ARM_MATH_BIG_ENDIAN + asm volatile("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #4\n" + "ldr.w r1, [%[pB]], #8\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r1, %[sum]\n" + "smlad %[sum2], r4, r0, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r3, %[sum3]\n" + "smlad %[sum4], r4, r2, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n" + : [ sum ] "+r"(sum), + [ sum2 ] "+r"(sum2), + [ sum3 ] "+r"(sum3), + [ sum4 ] "+r"(sum4), + [ pB ] "+r"(pB), + [ pA ] "+r"(pA) + : [ colCnt ] "r"(colCnt) + : "r0", "r1", "r2", "r3", "r4"); +#else + asm volatile("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #4\n" + "ldr.w r1, [%[pB]], #8\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r0, %[sum]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n" + : [ sum ] "+r"(sum), + [ sum2 ] "+r"(sum2), + [ sum3 ] "+r"(sum3), + [ sum4 ] "+r"(sum4), + [ pB ] "+r"(pB), + [ pA ] "+r"(pA) + : [ colCnt ] "r"(colCnt) + : "r0", "r1", "r2", "r3", "r4"); +#endif /* ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + q7_t inM2 = *pB++; + q7_t inM3 = *pB++; + q7_t inM4 = *pB++; + + sum += inV * inM; + sum2 += inV * inM2; + sum3 += inV * inM3; + sum4 += inV * inM4; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum2 >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum3 >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum4 >> out_shift), 16)); + + /* adjust the pointers and counters */ + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = read_and_pad(pB, &inM11, &inM12); + + inV1 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV1, inM11, sum); + + inV2 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + colCnt--; + } + + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q15_t)__SSAT((sum >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t)__SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of FC group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c b/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c new file mode 100644 index 00000000..d8b6887b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q15.c + * Description: Q15 basic fully-connected layer function + * + * $Date: 20. July 2021 + * $Revision: V.1.1.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/** + * @brief Q15 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + */ + +arm_status arm_fully_connected_q15(const q15_t *pV, + const q15_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t *bias, + q15_t *pOut, + q15_t *vec_buffer) +{ + (void)vec_buffer; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q15_t *pB = pM; + const q15_t *pB2 = pB + dim_vec; + q15_t *pO = pOut; + const q15_t *pA; + const q15_t *pBias = bias; + uint16_t rowCnt = num_of_rows >> 1; + + /* this loop loops over different output */ + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + pB2 = pB + dim_vec; + + while (colCnt) + { + q31_t inV1, inM1, inM2; + inV1 = arm_nn_read_q15x2_ia(&pA); + inM1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inV1, inM1, sum); + inM2 = arm_nn_read_q15x2_ia(&pB2); + sum2 = __SMLAD(inV1, inM2, sum2); + + inV1 = arm_nn_read_q15x2_ia(&pA); + inM1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inV1, inM1, sum); + inM2 = arm_nn_read_q15x2_ia(&pB2); + sum2 = __SMLAD(inV1, inM2, sum2); + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q15_t inM = *pB++; + q15_t inM2 = *pB2++; + + sum += inV * inM; + sum2 += inV * inM2; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum2 >> out_shift), 16)); + + /* adjust the pointers and counters */ + pB = pB + dim_vec; + rowCnt--; + } + + rowCnt = num_of_rows & 0x1; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q31_t inV1, inM1; + inV1 = arm_nn_read_q15x2_ia(&pA); + inM1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inV1, inM1, sum); + + inV1 = arm_nn_read_q15x2_ia(&pA); + inM1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inV1, inM1, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q15_t inM = *pB++; + + sum += inV * inM; + + colCnt--; + } + + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + int i, j; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t)__SSAT((ip_out >> out_shift), 16); + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of FC group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c b/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c new file mode 100644 index 00000000..f6c9b169 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c @@ -0,0 +1,336 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q15_opt.c + * Description: Q15 opt fully-connected layer function + * + * $Date: 20. July 2021 + * $Revision: V.1.1.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/** + * @brief Q15 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + * Here we use only one pointer to read 4 rows in the weight + * matrix. So if the original matrix looks like this: + * + * | a11 | a12 | a13 | + * + * | a21 | a22 | a23 | + * + * | a31 | a32 | a33 | + * + * | a41 | a42 | a43 | + * + * | a51 | a52 | a53 | + * + * | a61 | a62 | a63 | + * + * We operates on multiple-of-4 rows, so the first four rows becomes + * + * | a11 | a12 | a21 | a22 | a31 | a32 | a41 | a42 | + * + * | a13 | a23 | a33 | a43 | + * + * Remaining rows are kept the same original order. + * + * So the stored weight matrix looks like this: + * + * + * | a11 | a12 | a21 | a22 | a31 | a32 | a41 | a42 | + * + * | a13 | a23 | a33 | a43 | a51 | a52 | a53 | a61 | + * + * | a62 | a63 | + */ + +arm_status arm_fully_connected_q15_opt(const q15_t *pV, + const q15_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t *bias, + q15_t *pOut, + q15_t *vec_buffer) +{ + (void)vec_buffer; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q15_t *pB = pM; + q15_t *pO = pOut; + const q15_t *pBias = bias; + const q15_t *pA = pV; + + uint16_t rowCnt = num_of_rows >> 2; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + +#ifdef USE_INTRINSIC + + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = arm_nn_read_q15x2_ia(&pA); + inM11 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inV, inM11, sum); + inM12 = arm_nn_read_q15x2_ia(&pB); + sum2 = __SMLAD(inV, inM12, sum2); + inM13 = arm_nn_read_q15x2_ia(&pB); + sum3 = __SMLAD(inV, inM13, sum3); + inM14 = arm_nn_read_q15x2_ia(&pB); + sum4 = __SMLAD(inV, inM14, sum4); + colCnt--; + } + +#else + + /* + * register needed: + * loop counter: colCnt + * accumulators: sum, sum2, sum3, sum4 + * pointers: pB, pA + * weight data: inM11, inM12, inM13, inM14 + * activation data: inV + */ + + asm volatile("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #4\n" + "ldr.w r0, [%[pB]], #16\n" + "smlad %[sum], r4, r0, %[sum]\n" + "ldr.w r1, [%[pB] , #-12]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r2, [%[pB] , #-8]\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "ldr.w r3, [%[pB] , #-4]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n" + : [ sum ] "+r"(sum), + [ sum2 ] "+r"(sum2), + [ sum3 ] "+r"(sum3), + [ sum4 ] "+r"(sum4), + [ pB ] "+r"(pB), + [ pA ] "+r"(pA) + : [ colCnt ] "r"(colCnt) + : "r0", "r1", "r2", "r3", "r4"); + +#endif /* USE_INTRINSIC */ + + colCnt = dim_vec & 0x1; + while (colCnt) + { + + q15_t inV = *pA++; + q15_t inM = *pB++; + q15_t inM2 = *pB++; + q15_t inM3 = *pB++; + q15_t inM4 = *pB++; + + sum += inV * inM; + sum2 += inV * inM2; + sum3 += inV * inM3; + sum4 += inV * inM4; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum2 >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum3 >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum4 >> out_shift), 16)); + + /* adjust the pointers and counters */ + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q31_t inV1, inV2, inM1, inM2; + + inM1 = arm_nn_read_q15x2_ia(&pB); + inV1 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV1, inM1, sum); + + inM2 = arm_nn_read_q15x2_ia(&pB); + inV2 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV2, inM2, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q15_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t rowCnt = num_of_rows >> 2; + const q15_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q15_t *pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q15_t inB1 = *pB++; + q15_t inB2 = *pB++; + sum += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum2 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum3 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum4 += inA1 * inB1 + inA2 * inB2; + + colCnt--; + } + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + colCnt--; + } + *pO++ = (q15_t)__SSAT((sum >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t)__SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of FC group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c b/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c new file mode 100644 index 00000000..d500efe9 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q7.c + * Description: Q7 basic fully-connected layer function + * + * $Date: July 20, 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/** + * @brief Q7 basic fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: dim_vec + * + * This basic function is designed to work with regular weight + * matrix without interleaving. + * + */ + +arm_status arm_fully_connected_q7(const q7_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut, + q15_t *vec_buffer) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + const q7_t *pB2; + q7_t *pO = pOut; + const q7_t *pBias = bias; + const q15_t *pA; + uint16_t rowCnt = num_of_rows >> 1; + + /* expand the vector into the buffer */ + arm_q7_to_q15_reordered_no_shift(pV, vec_buffer, dim_vec); + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = vec_buffer; + pB2 = pB + dim_vec; + + while (colCnt) + { + q31_t inV, inM11, inM12, inM21, inM22; + pB = read_and_pad_reordered(pB, &inM11, &inM12); + pB2 = read_and_pad_reordered(pB2, &inM21, &inM22); + + inV = arm_nn_read_q15x2_ia(&pA); + + sum = __SMLAD(inV, inM11, sum); + sum2 = __SMLAD(inV, inM21, sum2); + + inV = arm_nn_read_q15x2_ia(&pA); + + sum = __SMLAD(inV, inM12, sum); + sum2 = __SMLAD(inV, inM22, sum2); + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inV = *pA++; + q15_t inM = *pB++; + q15_t inM2 = *pB2++; + + sum += inV * inM; + sum2 += inV * inM2; + colCnt--; + } /* while over colCnt */ + *pO++ = (q7_t)(__SSAT((sum >> out_shift), 8)); + *pO++ = (q7_t)(__SSAT((sum2 >> out_shift), 8)); + + /* adjust the pointers and counters */ + pB += dim_vec; + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x1; + + while (rowCnt) + { + uint16_t colCnt = dim_vec >> 2; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + pA = vec_buffer; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = read_and_pad_reordered(pB, &inM11, &inM12); + + inV1 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV1, inM11, sum); + + inV2 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inV = *pA++; + q15_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q7_t)(__SSAT((sum >> out_shift), 8)); + + rowCnt--; + } + +#else + (void)vec_buffer; + int i, j; + + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q7_t)__SSAT((ip_out >> out_shift), 8); + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of FC group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c b/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c new file mode 100644 index 00000000..2f3d6539 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c @@ -0,0 +1,495 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q7_opt.c + * Description: Q7 basic fully-connected layer function + * + * $Date: 20. July 2021 + * $Revision: V.1.1.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/** + * @brief Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: dim_vec + * + * This opt function is designed to work with interleaved weight + * matrix. The vector input is assumed in q7_t format, we call + * arm_q7_to_q15_no_shift_shuffle function to expand into + * q15_t format with certain weight re-ordering, refer to the function + * comments for more details. + * Here we use only one pointer to read 4 rows in the weight + * matrix. So if the original q7_t matrix looks like this: + * + * | a11 | a12 | a13 | a14 | a15 | a16 | a17 | + * + * | a21 | a22 | a23 | a24 | a25 | a26 | a27 | + * + * | a31 | a32 | a33 | a34 | a35 | a36 | a37 | + * + * | a41 | a42 | a43 | a44 | a45 | a46 | a47 | + * + * | a51 | a52 | a53 | a54 | a55 | a56 | a57 | + * + * | a61 | a62 | a63 | a64 | a65 | a66 | a67 | + * + * + * We operates on multiple-of-4 rows, so the first four rows becomes + * + * | a11 | a21 | a13 | a23 | a31 | a41 | a33 | a43 | + * + * | a12 | a22 | a14 | a24 | a32 | a42 | a34 | a44 | + * + * | a15 | a25 | a35 | a45 | a16 | a26 | a36 | a46 | + * + * So within the kernel, we first read the re-ordered vector in as: + * + * | b1 | b3 | and | b2 | b4 | + * + * the four q31_t weights will look like + * + * | a11 | a13 |, | a21 | a23 |, | a31 | a33 |, | a41 | a43 | + * + * | a12 | a14 |, | a22 | a24 |, | a32 | a34 |, | a42 | a44 | + * + * The column left over will be in-order. + * which is: + * + * | a17 | a27 | a37 | a47 | + * + * For the left-over rows, we do 1x1 computation, so the data remains + * as its original order. + * + * So the stored weight matrix looks like this: + * + * | a11 | a21 | a13 | a23 | a31 | a41 | + * + * | a33 | a43 | a12 | a22 | a14 | a24 | + * + * | a32 | a42 | a34 | a44 | a15 | a25 | + * + * | a35 | a45 | a16 | a26 | a36 | a46 | + * + * | a17 | a27 | a37 | a47 | a51 | a52 | + * + * | a53 | a54 | a55 | a56 | a57 | a61 | + * + * | a62 | a63 | a64 | a65 | a66 | a67 | + * + * + */ + +arm_status arm_fully_connected_q7_opt(const q7_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut, + q15_t *vec_buffer) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + q7_t *pO = pOut; + const q7_t *pBias = bias; + const q15_t *pA; + uint16_t rowCnt = num_of_rows >> 2; + + arm_q7_to_q15_reordered_no_shift(pV, vec_buffer, dim_vec); + + while (rowCnt) + { + + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = vec_buffer; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = arm_nn_read_q15x2_ia(&pA); + inM11 = arm_nn_read_q7x4_ia(&pB); + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM11, inV, sum); + sum2 = __SMLAD(inM12, inV, sum2); + inM13 = arm_nn_read_q7x4_ia(&pB); + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM13, inV, sum3); + sum4 = __SMLAD(inM14, inV, sum4); + + inV = arm_nn_read_q15x2_ia(&pA); + inM11 = arm_nn_read_q7x4_ia(&pB); + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM11, inV, sum); + sum2 = __SMLAD(inM12, inV, sum2); + inM13 = arm_nn_read_q7x4_ia(&pB); + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM13, inV, sum3); + sum4 = __SMLAD(inM14, inV, sum4); + colCnt--; + } +#else + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = arm_nn_read_q15x2_ia(&pA); + inM11 = arm_nn_read_q7x4_ia(&pB); + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM12, inV, sum); + sum2 = __SMLAD(inM11, inV, sum2); + inM13 = arm_nn_read_q7x4_ia(&pB); + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM14, inV, sum3); + sum4 = __SMLAD(inM13, inV, sum4); + + inV = arm_nn_read_q15x2_ia(&pA); + inM11 = arm_nn_read_q7x4_ia(&pB); + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM12, inV, sum); + sum2 = __SMLAD(inM11, inV, sum2); + inM13 = arm_nn_read_q7x4_ia(&pB); + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM14, inV, sum3); + sum4 = __SMLAD(inM13, inV, sum4); + colCnt--; + } +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + + /* + * register needed: + * loop counter: colCnt + * accumulators: sum, sum2, sum3, sum4 + * pointers: pB, pA + * weight data: inM11, inM12, inM13, inM14 + * activation data: inV + */ + +#ifndef ARM_MATH_BIG_ENDIAN + asm volatile("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #8\n" + "ldr.w r1, [%[pB]], #16\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r1, %[sum]\n" + "smlad %[sum2], r4, r0, %[sum2]\n" + "ldr.w r3, [%[pB], #-12]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r3, %[sum3]\n" + "smlad %[sum4], r4, r2, %[sum4]\n" + "ldr.w r4, [%[pA], #-4]\n" + "ldr.w r1, [%[pB], #-8]\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r1, %[sum]\n" + "smlad %[sum2], r4, r0, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r3, %[sum3]\n" + "smlad %[sum4], r4, r2, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n" + : [ sum ] "+r"(sum), + [ sum2 ] "+r"(sum2), + [ sum3 ] "+r"(sum3), + [ sum4 ] "+r"(sum4), + [ pB ] "+r"(pB), + [ pA ] "+r"(pA) + : [ colCnt ] "r"(colCnt) + : "r0", "r1", "r2", "r3", "r4"); +#else + asm volatile("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #8\n" + "ldr.w r1, [%[pB]], #16\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r0, %[sum]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r3, [%[pB], #-12]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "ldr.w r4, [%[pA], #-4]\n" + "ldr.w r1, [%[pB], #-8]\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r0, %[sum]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n" + : [ sum ] "+r"(sum), + [ sum2 ] "+r"(sum2), + [ sum3 ] "+r"(sum3), + [ sum4 ] "+r"(sum4), + [ pB ] "+r"(pB), + [ pA ] "+r"(pA) + : [ colCnt ] "r"(colCnt) + : "r0", "r1", "r2", "r3", "r4"); +#endif /* ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + q7_t inM2 = *pB++; + q7_t inM3 = *pB++; + q7_t inM4 = *pB++; + + sum += inV * inM; + sum2 += inV * inM2; + sum3 += inV * inM3; + sum4 += inV * inM4; + colCnt--; + } /* while over colCnt */ + *pO++ = (q7_t)(__SSAT((sum >> out_shift), 8)); + *pO++ = (q7_t)(__SSAT((sum2 >> out_shift), 8)); + *pO++ = (q7_t)(__SSAT((sum3 >> out_shift), 8)); + *pO++ = (q7_t)(__SSAT((sum4 >> out_shift), 8)); + + /* adjust the pointers and counters */ + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = vec_buffer; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = read_and_pad_reordered(pB, &inM11, &inM12); + + inV1 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV1, inM11, sum); + + inV2 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q7_t)(__SSAT((sum >> out_shift), 8)); + + rowCnt--; + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + (void)vec_buffer; + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q7_t *pA; + q7_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q7_t inA1 = *pA++; + q7_t inA3 = *pA++; + q7_t inA2 = *pA++; + q7_t inA4 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum += inA3 * inB1 + inA4 * inB2; + sum2 += inA3 * inB3 + inA4 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA3 * inB1 + inA4 * inB2; + sum4 += inA3 * inB3 + inA4 * inB4; + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pO++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + *pO++ = (q7_t)__SSAT((sum3 >> out_shift), 8); + *pO++ = (q7_t)__SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q7_t)__SSAT((ip_out >> out_shift), 8); + + rowCnt--; + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of FC group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_s16.c b/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_s16.c new file mode 100644 index 00000000..46df5786 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_s16.c @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_s16 + * Description: Fully connected function compatible with TF Lite. + * + * $Date: 3. August 2021 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/* + * S16 basic fully-connected and matrix multiplication layer function for TensorFlow Lite + * + * Refer header file for details. + * + */ +arm_status arm_fully_connected_s16(const cmsis_nn_context *ctx, + const cmsis_nn_fc_params *fc_params, + const cmsis_nn_per_tensor_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *kernel, + const cmsis_nn_dims *bias_dims, + const int64_t *bias, + const cmsis_nn_dims *output_dims, + q15_t *output) +{ + (void)bias_dims; + (void)ctx; + (void)fc_params->filter_offset; + + int32_t batch_cnt = input_dims->n; + + const q31_t reduced_multiplier = REDUCE_MULTIPLIER(quant_params->multiplier); + + while (batch_cnt) + { + arm_nn_vec_mat_mult_t_s16(input, + kernel, + bias, + output, + reduced_multiplier, + quant_params->shift, + filter_dims->n, /* col_dim or accum_depth */ + output_dims->c, /* row_dim or output_depth */ + fc_params->activation.min, + fc_params->activation.max); + input += filter_dims->n; + output += output_dims->c; + batch_cnt--; + } + + return (ARM_MATH_SUCCESS); +} + +int32_t arm_fully_connected_s16_get_buffer_size(const cmsis_nn_dims *filter_dims) +{ + (void)filter_dims; + return 0; +} + +/** + * @} end of FC group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_s8.c new file mode 100644 index 00000000..96157016 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_s8.c @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_s8 + * Description: Fully connected function compatible with TF Lite. + * + * $Date: 8 April 2022 + * $Revision: V.3.1.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/* + * S8 basic fully-connected and matrix multiplication layer function for TensorFlow Lite + * + * Refer header file for details. + * + */ + +arm_status arm_fully_connected_s8(const cmsis_nn_context *ctx, + const cmsis_nn_fc_params *fc_params, + const cmsis_nn_per_tensor_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *kernel, + const cmsis_nn_dims *bias_dims, + const int32_t *bias, + const cmsis_nn_dims *output_dims, + q7_t *output) +{ + (void)bias_dims; + (void)ctx; + (void)fc_params->filter_offset; + + int32_t batch_cnt = input_dims->n; + + while (batch_cnt) + { + arm_nn_vec_mat_mult_t_s8(input, + kernel, + bias, + output, + fc_params->input_offset, + 0, + fc_params->output_offset, + quant_params->multiplier, + quant_params->shift, + filter_dims->n, /* col_dim or accum_depth */ + output_dims->c, /* row_dim or output_depth */ + fc_params->activation.min, + fc_params->activation.max, + 1L); + input += filter_dims->n; + output += output_dims->c; + batch_cnt--; + } + return (ARM_MATH_SUCCESS); +} + +int32_t arm_fully_connected_s8_get_buffer_size(const cmsis_nn_dims *filter_dims) +{ + (void)filter_dims; + return 0; +} + +/** + * @} end of FC group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/CMakeLists.txt new file mode 100644 index 00000000..0aa9f385 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/CMakeLists.txt @@ -0,0 +1,26 @@ +# +# Copyright (c) 2019-2022 Arm Limited. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +file(GLOB SRC "./*_s8.c") +target_sources(cmsis-nn PRIVATE ${SRC} arm_q7_to_q15_with_offset.c + arm_nn_mat_mul_kernel_s16.c + arm_q7_to_q15_with_offset.c + arm_nn_mat_mul_kernel_s16.c + arm_nn_vec_mat_mult_t_s16.c + arm_q7_to_q15_no_shift.c) + diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_accumulate_q7_to_q15.c b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_accumulate_q7_to_q15.c new file mode 100644 index 00000000..c3f666aa --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_accumulate_q7_to_q15.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_accumulate_q7_to_q15.c + * Description: Accumulate q7 vector into q15 one. + * + * $Date: 20 July 2021 + * $Revision: V.1.1.2 + * + * pSrc Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +void arm_nn_accumulate_q7_to_q15(q15_t *pDst, const q7_t *pSrc, uint32_t length) +{ + q15_t *pCnt = pDst; + const q7_t *pV = pSrc; + int32_t count = length; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + q31_t v1, v2, vo1, vo2; + count = length >> 2; + q31_t in; + + while (count > 0l) + { + q31_t value = arm_nn_read_q7x4_ia(&pV); + v1 = __SXTB16(__ROR((uint32_t)value, 8)); + v2 = __SXTB16(value); +#ifndef ARM_MATH_BIG_ENDIAN + vo2 = (q31_t)__PKHTB(v1, v2, 16); + vo1 = (q31_t)__PKHBT(v2, v1, 16); +#else + vo1 = (q31_t)__PKHTB(v1, v2, 16); + vo2 = (q31_t)__PKHBT(v2, v1, 16); +#endif + + in = arm_nn_read_q15x2(pCnt); + arm_nn_write_q15x2_ia(&pCnt, __QADD16(vo1, in)); + + in = arm_nn_read_q15x2(pCnt); + arm_nn_write_q15x2_ia(&pCnt, __QADD16(vo2, in)); + + count--; + } + count = length & 0x3; +#endif + while (count > 0l) + { + *pCnt++ += *pV++; + count--; + } +} + +/** + * @} end of NNBasicMath group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_add_q7.c b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_add_q7.c new file mode 100644 index 00000000..511e5863 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_add_q7.c @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_add_q7.c + * Description: Non saturating addition of elements of a q7 vector. + * + * $Date: 20. July 2021 + * $Revision: V.1.1.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nn_tables.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +void arm_nn_add_q7(const q7_t *input, q31_t *output, uint32_t block_size) +{ + uint32_t block_count; + q31_t result = 0; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Loop unrolling: Compute 4 outputs at a time */ + block_count = block_size >> 2U; + + while (block_count > 0U) + { + const int32_t mult_q15x2 = (1UL << 16) | 1UL; + q31_t in_q7x4 = arm_nn_read_q7x4_ia(&input); + q31_t temp_q15x2 = __SXTAB16(__SXTB16(in_q7x4), __ROR((uint32_t)in_q7x4, 8)); + + result = __SMLAD(temp_q15x2, mult_q15x2, result); + + /* Decrement loop counter */ + block_count--; + } + + /* Loop unrolling: Compute remaining outputs */ + block_count = block_size & 0x3; +#else + block_count = block_size; +#endif + while (block_count > 0U) + { + /* Add and store result in destination buffer. */ + result += *input++; + + /* Decrement loop counter */ + block_count--; + } + + *output = result; +} + +/** + * @} end of NNBasicMath group + */ \ No newline at end of file diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c new file mode 100644 index 00000000..b633ef4a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_depthwise_conv_nt_t_padded_s8.c + * Description: Depthwise convolution with padded matrices. + * + * $Date: 09. October 2020 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M processors with MVE extension + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * Depthwise convolution of transposed rhs matrix with 4 lhs matrices. One or more of the rhs matrices are padded. + * Dimensions are the same for lhs and rhs. + * + * Refer header file for details. + * + */ + +q7_t *arm_nn_depthwise_conv_nt_t_padded_s8(const q7_t *lhs, + const q7_t *rhs, + const int32_t input_offset, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t row_x_col, + const int32_t *const output_bias, + q7_t *out) +{ +#if defined(ARM_MATH_MVEI) + int32_t loop_count = (num_ch + 3) / 4; + const int32_t *bias = output_bias; + uint32_t num_ch_to_process = num_ch; + + for (int i_loop_cnt = 0, offset = 0; i_loop_cnt < loop_count; + num_ch_to_process -= 4, out += 4, offset += 4, i_loop_cnt++) + { + int32x4_t out_0 = vldrwq_s32(bias); + int32x4_t out_1 = out_0; + int32x4_t out_2 = out_0; + int32x4_t out_3 = out_0; + bias += 4; + + const int8_t *rhs_0 = rhs + offset; + const int8_t *lhs_0 = lhs + offset; + const int8_t *lhs_1 = lhs + row_x_col * num_ch + offset; + const int8_t *lhs_2 = lhs + (row_x_col * num_ch * 2) + offset; + const int8_t *lhs_3 = lhs + (row_x_col * num_ch * 3) + offset; + + for (int i_row_x_col = 0; i_row_x_col < row_x_col; i_row_x_col++) + { + const int32x4_t ker_0 = vldrbq_s32(rhs_0); + + int32x4_t ip_0 = vldrbq_s32(lhs_0); + ip_0 = vaddq_n_s32(ip_0, input_offset); + out_0 += vmulq_s32(ip_0, ker_0); + + int32x4_t ip_1 = vldrbq_s32(lhs_1); + ip_1 = vaddq_n_s32(ip_1, input_offset); + out_1 += vmulq_s32(ip_1, ker_0); + + int32x4_t ip_2 = vldrbq_s32(lhs_2); + ip_2 = vaddq_n_s32(ip_2, input_offset); + out_2 += vmulq_s32(ip_2, ker_0); + + int32x4_t ip_3 = vldrbq_s32(lhs_3); + ip_3 = vaddq_n_s32(ip_3, input_offset); + + out_3 += vmulq_s32(ip_3, ker_0); + + lhs_0 += num_ch; + lhs_1 += num_ch; + lhs_2 += num_ch; + lhs_3 += num_ch; + + rhs_0 += num_ch; + } + + const int32x4_t mult = vldrwq_s32(out_mult); + const int32x4_t shift = vldrwq_s32(out_shift); + out_mult += 4; + out_shift += 4; + + out_0 = arm_requantize_mve_32x4(out_0, mult, shift); + out_0 = vaddq_n_s32(out_0, out_offset); + out_0 = vmaxq_s32(out_0, vdupq_n_s32(activation_min)); + out_0 = vminq_s32(out_0, vdupq_n_s32(activation_max)); + mve_pred16_t p = vctp32q(num_ch_to_process); + vstrbq_p_s32(out, out_0, p); + + out_1 = arm_requantize_mve_32x4(out_1, mult, shift); + out_1 = vaddq_n_s32(out_1, out_offset); + out_1 = vmaxq_s32(out_1, vdupq_n_s32(activation_min)); + out_1 = vminq_s32(out_1, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out + num_ch, out_1, p); + + out_2 = arm_requantize_mve_32x4(out_2, mult, shift); + out_2 = vaddq_n_s32(out_2, out_offset); + out_2 = vmaxq_s32(out_2, vdupq_n_s32(activation_min)); + out_2 = vminq_s32(out_2, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out + 2 * num_ch, out_2, p); + + out_3 = arm_requantize_mve_32x4(out_3, mult, shift); + out_3 = vaddq_n_s32(out_3, out_offset); + out_3 = vmaxq_s32(out_3, vdupq_n_s32(activation_min)); + out_3 = vminq_s32(out_3, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out + 3 * num_ch, out_3, p); + } + + const int tail_ch = num_ch & 0x3; + if (tail_ch != 0) + { + out -= (4 - tail_ch); + } + return out + (3 * num_ch); + +#else + (void)lhs; + (void)rhs; + (void)input_offset; + (void)num_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)row_x_col; + (void)output_bias; + (void)out; + return NULL; +#endif +} + +/** + * @} end of NNBasicMath group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c new file mode 100644 index 00000000..dda12fd2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c @@ -0,0 +1,170 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_depthwise_conv_nt_t_s8.c + * Description: Depthwise convolution on matrices with no padding. + * + * $Date: 09. October 2020 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M processors with MVE extension. + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * Depthwise convolution of rhs matrix with 4 lhs matrices with no padding. Dimensions are the same for lhs and rhs. + * + * Refer header file for details. + * + */ + +q7_t *arm_nn_depthwise_conv_nt_t_s8(const q7_t *lhs, + const q7_t *rhs, + const int32_t input_offset, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t row_x_col, + const int32_t *const output_bias, + q7_t *out) +{ +#if defined(ARM_MATH_MVEI) + const int32_t *bias = output_bias; + int32_t loop_count = (num_ch + 3) / 4; + uint32_t num_ch_to_process = num_ch; + + for (int i_loop_cnt = 0, offset = 0; i_loop_cnt < loop_count; + num_ch_to_process -= 4, offset += 4, out += 4, i_loop_cnt++) + { + int32x4_t out_0 = vldrwq_s32(bias); + int32x4_t out_1 = out_0; + int32x4_t out_2 = out_0; + int32x4_t out_3 = out_0; + bias += 4; + + const int8_t *rhs_0 = rhs + offset; + const int8_t *lhs_0 = lhs + offset; + const int8_t *lhs_1 = lhs + row_x_col * num_ch + offset; + const int8_t *lhs_2 = lhs + (row_x_col * num_ch * 2) + offset; + const int8_t *lhs_3 = lhs + (row_x_col * num_ch * 3) + offset; + int32x4_t ker_sum = vdupq_n_s32(0); + + for (int i_row_x_col = 0; i_row_x_col < row_x_col; i_row_x_col++) + { + const int32x4_t ker_0 = vldrbq_s32(rhs_0); + ker_sum = vaddq_s32(ker_sum, ker_0); + + int32x4_t ip_0 = vldrbq_s32(lhs_0); + out_0 += vmulq_s32(ip_0, ker_0); + + int32x4_t ip_1 = vldrbq_s32(lhs_1); + out_1 += vmulq_s32(ip_1, ker_0); + + int32x4_t ip_2 = vldrbq_s32(lhs_2); + out_2 += vmulq_s32(ip_2, ker_0); + + int32x4_t ip_3 = vldrbq_s32(lhs_3); + out_3 += vmulq_s32(ip_3, ker_0); + + lhs_0 += num_ch; + lhs_1 += num_ch; + lhs_2 += num_ch; + lhs_3 += num_ch; + + rhs_0 += num_ch; + } + + ker_sum = vmulq_n_s32(ker_sum, input_offset); + out_0 = ker_sum + out_0; + out_1 = ker_sum + out_1; + out_2 = ker_sum + out_2; + out_3 = ker_sum + out_3; + + const int32x4_t mult = vldrwq_s32(out_mult); + const int32x4_t shift = vldrwq_s32(out_shift); + out_mult += 4; + out_shift += 4; + mve_pred16_t p = vctp32q(num_ch_to_process); + + out_0 = arm_requantize_mve_32x4(out_0, mult, shift); + out_0 = vaddq_n_s32(out_0, out_offset); + out_0 = vmaxq_s32(out_0, vdupq_n_s32(activation_min)); + out_0 = vminq_s32(out_0, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out, out_0, p); + + out_1 = arm_requantize_mve_32x4(out_1, mult, shift); + out_1 = vaddq_n_s32(out_1, out_offset); + out_1 = vmaxq_s32(out_1, vdupq_n_s32(activation_min)); + out_1 = vminq_s32(out_1, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out + num_ch, out_1, p); + + out_2 = arm_requantize_mve_32x4(out_2, mult, shift); + out_2 = vaddq_n_s32(out_2, out_offset); + out_2 = vmaxq_s32(out_2, vdupq_n_s32(activation_min)); + out_2 = vminq_s32(out_2, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out + 2 * num_ch, out_2, p); + + out_3 = arm_requantize_mve_32x4(out_3, mult, shift); + out_3 = vaddq_n_s32(out_3, out_offset); + out_3 = vmaxq_s32(out_3, vdupq_n_s32(activation_min)); + out_3 = vminq_s32(out_3, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out + 3 * num_ch, out_3, p); + } + + const int tail_ch = num_ch & 0x3; + if (tail_ch != 0) + { + out -= (4 - tail_ch); + } + + return out + (3 * num_ch); +#else + (void)lhs; + (void)rhs; + (void)input_offset; + (void)num_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)row_x_col; + (void)output_bias; + (void)out; + return NULL; +#endif +} + +/** + * @} end of NNBasicMath group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c new file mode 100644 index 00000000..8b1bf6ea --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mul_core_1x_s8.c + * Description: General Matrix-multiplication function + * + * $Date: 19. April 2022 + * $Revision: V.1.0.3 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 matrix multiplication to process 1 row + * + * Refer header file for details. + * + */ + +arm_status arm_nn_mat_mul_core_1x_s8(int32_t row_elements, + const int8_t *row_base, + const int8_t *col_base, + int32_t *const sum_col, + int32_t *const output) +{ + int32_t acc_n0 = 0; + int32_t sum_tmp = 0; + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + + __ASM volatile(" vldrb.8 q0, [%[col]], #16 \n" + " wlstp.8 lr, %[cnt], 1f \n" + "2: \n" + " vaddva.s8 %[sum], q0 \n" + " vldrb.8 q1, [%[row0]], #16 \n" + " vmladava.s8 %[out0], q0, q1 \n" + " vldrb.8 q0, [%[col]], #16 \n" + " letp lr, 2b \n" + "1: \n" + : [col] "+r"(col_base), [sum] "+Te"(sum_tmp), [row0] "+r"(row_base), [out0] "+Te"(acc_n0) + : [cnt] "r"(row_elements) + : "q0", "q1", "memory", "r14"); +#else + for (int i = 0; i < row_elements; i++) + { + sum_tmp += col_base[i]; + acc_n0 += row_base[i] * col_base[i]; + } +#endif + + *sum_col = sum_tmp; + *output = acc_n0; + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c new file mode 100644 index 00000000..ff427ad1 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mul_core_4x_s8.c + * Description: General matrix multiplication function for MVE extension + * + * $Date: 19. April 2022 + * $Revision: V.3.0.1 + * + * Target Processor: Cortex-M processors + * -------------------------------------------------------------------- */ +#include "arm_nn_types.h" +#include "arm_nnsupportfunctions.h" +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 matrix multiplication to process 4 rows and one column + * + * Refer header file for details. + * + */ + +int8_t *arm_nn_mat_mul_core_4x_s8(const int32_t row_elements, + const int32_t offset, + const int8_t *row_base, + const int8_t *col_base_ref, + const int32_t out_ch, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const int32_t *bias, + int8_t *output) +{ + +#if defined(ARM_MATH_MVEI) + for (int i = 0; i < out_ch; i++) + { + int32_t acc_n0 = 0; + int32_t acc_n1 = 0; + int32_t acc_n2 = 0; + int32_t acc_n3 = 0; + + const int8_t *ip_row_0 = row_base; + const int8_t *ip_row_1 = row_base + offset; + const int8_t *ip_row_2 = row_base + (2 * offset); + const int8_t *ip_row_3 = row_base + (3 * offset); + const int8_t *col_base = col_base_ref + i * row_elements; + int32_t sum_tmp = 0; + + __ASM volatile(" vldrb.8 q0, [%[col]], #16 \n" + " wlstp.8 lr, %[cnt], 1f \n" + "2: \n" + " vaddva.s8 %[sum], q0 \n" + " vldrb.8 q1, [%[row0]], #16 \n" + " vmladava.s8 %[out0], q0, q1 \n" + " vldrb.8 q2, [%[row1]], #16 \n" + " vmladava.s8 %[out1], q0, q2 \n" + " vldrb.8 q3, [%[row2]], #16 \n" + " vmladava.s8 %[out2], q0, q3 \n" + " vldrb.8 q4, [%[row3]], #16 \n" + " vmladava.s8 %[out3], q0, q4 \n" + " vldrb.8 q0, [%[col]], #16 \n" + " letp lr, 2b \n" + "1: \n" + : [col] "+r"(col_base), + [sum] "+Te"(sum_tmp), + [row0] "+r"(ip_row_0), + [row1] "+r"(ip_row_1), + [row2] "+r"(ip_row_2), + [row3] "+r"(ip_row_3), + [out0] "+Te"(acc_n0), + [out1] "+Te"(acc_n1), + [out2] "+Te"(acc_n2), + [out3] "+Te"(acc_n3) + : [cnt] "r"(row_elements) + : "q0", "q1", "q2", "q3", "q4", "memory", "r14"); + + int32x4_t res = {acc_n0, acc_n1, acc_n2, acc_n3}; + sum_tmp *= conv_params->input_offset; + if (bias) + { + sum_tmp += bias[i]; + } + res = vaddq_n_s32(res, sum_tmp); + + res = arm_requantize_mve(res, quant_params->multiplier[i], quant_params->shift[i]); + res = vaddq_n_s32(res, conv_params->output_offset); + + res = vmaxq_s32(res, vdupq_n_s32(conv_params->activation.min)); + res = vminq_s32(res, vdupq_n_s32(conv_params->activation.max)); + + const uint32x4_t scatter_offset = {0, (uint32_t)out_ch, (uint32_t)out_ch * 2, (uint32_t)out_ch * 3}; + vstrbq_scatter_offset_s32(output, scatter_offset, res); + output++; + } + + return output + (3 * out_ch); +#else + (void)row_elements; + (void)offset; + (void)row_base; + (void)col_base_ref; + (void)out_ch; + (void)conv_params; + (void)quant_params; + (void)bias; + (void)output; + return NULL; +#endif +} + +/** + * @} end of NNBasicMath group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_kernel_s16.c b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_kernel_s16.c new file mode 100644 index 00000000..41d0bc9a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_kernel_s16.c @@ -0,0 +1,250 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_kernel_s16.c + * Description: Matrix-multiplication function for convolution + * + * $Date: 12 August 2021 + * $Revision: V.1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/* + * Matrix-multiplication function for convolution with per-channel requantization. + * + * Refer header file for details. + * + */ + +q15_t *arm_nn_mat_mult_kernel_s16(const q7_t *input_a, + const q15_t *input_b, + const int32_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int16_t activation_min, + const int16_t activation_max, + const int32_t num_col_a, + const int64_t *const output_bias, + q15_t *out_0) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* set up the second output pointers */ + q15_t *out_1 = out_0 + output_ch; + const int64_t *bias = output_bias; + uint16_t row_count = output_ch / 2; + const q7_t *ip_a0 = input_a; + + /* this loop over rows in A */ + while (row_count) + { + /* setup pointers for B */ + const q15_t *ip_b0 = input_b; + const q15_t *ip_b1 = ip_b0 + num_col_a; + + /* align the second pointer for A */ + const q7_t *ip_a1 = ip_a0 + num_col_a; + + /* Init accumulator for channel N and N + 1 */ + q31_t ch_0_out_0 = 0; + q31_t ch_0_out_1 = 0; + q31_t ch_1_out_0 = 0; + q31_t ch_1_out_1 = 0; + + uint16_t col_count = num_col_a / 4; + /* accumulate over the vector */ + while (col_count) + { + q31_t a01, a02, a11, a12; + q31_t b0 = arm_nn_read_q15x2_ia(&ip_b0); + q31_t b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ip_a0 = read_and_pad(ip_a0, &a01, &a02); + ip_a1 = read_and_pad(ip_a1, &a11, &a12); + + ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + ch_1_out_0 = __SMLAD(a11, b0, ch_1_out_0); + ch_1_out_1 = __SMLAD(a11, b1, ch_1_out_1); + + b0 = arm_nn_read_q15x2_ia(&ip_b0); + b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + ch_1_out_0 = __SMLAD(a12, b0, ch_1_out_0); + ch_1_out_1 = __SMLAD(a12, b1, ch_1_out_1); + + col_count--; + } /* while over col_count */ + col_count = num_col_a & 0x3; + while (col_count) + { + q7_t a0 = *ip_a0++; + q15_t b0 = *ip_b0++; + q7_t a1 = *ip_a1++; + q15_t b1 = *ip_b1++; + + ch_0_out_0 += a0 * b0; + ch_0_out_1 += a0 * b1; + ch_1_out_0 += a1 * b0; + ch_1_out_1 += a1 * b1; + col_count--; + } /* while over col_count */ + if (bias) + { + q31_t reduced_multiplier = REDUCE_MULTIPLIER(*out_mult); + q63_t acc_64 = ch_0_out_0 + *bias; + ch_0_out_0 = arm_nn_requantize_s64(acc_64, reduced_multiplier, *out_shift); + acc_64 = ch_0_out_1 + *bias++; + ch_0_out_1 = arm_nn_requantize_s64(acc_64, reduced_multiplier, *out_shift); + out_mult++; + } + else + { + ch_0_out_0 = arm_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_1 = arm_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + out_mult++; + } + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q15_t)ch_0_out_0; + + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q15_t)ch_0_out_1; + out_shift++; + + if (bias) + { + q31_t reduced_multiplier = REDUCE_MULTIPLIER(*out_mult); + q63_t acc_64 = ch_1_out_0 + *bias; + ch_1_out_0 = arm_nn_requantize_s64(acc_64, reduced_multiplier, *out_shift); + acc_64 = ch_1_out_1 + *bias++; + ch_1_out_1 = arm_nn_requantize_s64(acc_64, reduced_multiplier, *out_shift); + out_mult++; + } + else + { + ch_1_out_0 = arm_nn_requantize(ch_1_out_0, *out_mult, *out_shift); + ch_1_out_1 = arm_nn_requantize(ch_1_out_1, *out_mult, *out_shift); + out_mult++; + } + ch_1_out_0 = MAX(ch_1_out_0, activation_min); + ch_1_out_0 = MIN(ch_1_out_0, activation_max); + *out_0++ = (q15_t)ch_1_out_0; + + ch_1_out_1 = MAX(ch_1_out_1, activation_min); + ch_1_out_1 = MIN(ch_1_out_1, activation_max); + *out_1++ = (q15_t)ch_1_out_1; + out_shift++; + + /* skip row */ + ip_a0 += num_col_a; + row_count--; + } + + /* compute the last odd numbered row if any */ + if (output_ch & 0x1) + { + /* setup pointers for B */ + const q15_t *ip_b0 = input_b; + const q15_t *ip_b1 = ip_b0 + num_col_a; + + q31_t ch_0_out_0 = 0; + q31_t ch_0_out_1 = 0; + + uint16_t col_count = num_col_a >> 2; + while (col_count) + { + q31_t a01, a02; + q31_t b0 = arm_nn_read_q15x2_ia(&ip_b0); + q31_t b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ip_a0 = read_and_pad(ip_a0, &a01, &a02); + + ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + + b0 = arm_nn_read_q15x2_ia(&ip_b0); + b1 = arm_nn_read_q15x2_ia(&ip_b1); + ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + + col_count--; + } + col_count = num_col_a & 0x3; + while (col_count) + { + q7_t a0 = *ip_a0++; + q15_t b0 = *ip_b0++; + q15_t b1 = *ip_b1++; + + ch_0_out_0 += a0 * b0; + ch_0_out_1 += a0 * b1; + col_count--; + } + if (bias) + { + q31_t reduced_multiplier = REDUCE_MULTIPLIER(*out_mult); + q63_t acc_64 = ch_0_out_0 + *bias; + ch_0_out_0 = arm_nn_requantize_s64(acc_64, reduced_multiplier, *out_shift); + acc_64 = ch_0_out_1 + *bias++; + ch_0_out_1 = arm_nn_requantize_s64(acc_64, reduced_multiplier, *out_shift); + } + else + { + ch_0_out_0 = arm_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_1 = arm_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + } + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q15_t)ch_0_out_0; + + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q15_t)ch_0_out_1; + out_mult++; + out_shift++; + } + + out_0 += output_ch; + + /* return the new output pointer with offset */ + return out_0; +#else + (void)input_a; + (void)input_b; + (void)output_ch; + (void)out_shift; + (void)out_mult; + (void)activation_min; + (void)activation_max; + (void)num_col_a; + (void)output_bias; + (void)out_0; + /* To be completed */ + return NULL; +#endif +} diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c new file mode 100644 index 00000000..d0420c23 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c @@ -0,0 +1,582 @@ +/* + * Copyright (C) 2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_s8_nt_t_s8 + * Description: Matrix multiplication support function with the right-hand-side (rhs) matrix transposed + * + * $Date: 09. October 2020 + * $Revision: V.1.0.3 + * + * Target Processor: Cortex-M + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 matrix multiplication with the right-hand-side matrix transposed + * + * Refer header file for details. + * + */ +arm_status arm_nn_mat_mult_nt_t_s8(const q7_t *lhs, + const q7_t *rhs, + const q31_t *bias, + q7_t *dst, + const int32_t *dst_multipliers, + const int32_t *dst_shifts, + const int32_t lhs_rows, + const int32_t rhs_rows, + const int32_t rhs_cols, + const int32_t lhs_offset, + const int32_t dst_offset, + const int32_t activation_min, + const int32_t activation_max) +{ +#if defined(ARM_MATH_DSP) + const int32_t off0 = rhs_cols - 4; + + for (int32_t rhs_rows_idx = 0; rhs_rows_idx <= (rhs_rows - 2); rhs_rows_idx += 2) + { + const q7_t *lhs_ptr = &lhs[0]; + q7_t *dst_ptr = &dst[0]; + + q31_t lhs_offset_contribution0 = 0; + q31_t lhs_offset_contribution1 = 0; + + for (int32_t x = 0; x < rhs_cols; ++x) + { + lhs_offset_contribution0 += rhs[x]; + lhs_offset_contribution1 += rhs[x + rhs_cols]; + } + + lhs_offset_contribution0 *= lhs_offset; + lhs_offset_contribution1 *= lhs_offset; + if (bias) + { + lhs_offset_contribution0 += bias[rhs_rows_idx]; + lhs_offset_contribution1 += bias[rhs_rows_idx + 1]; + } + + int32_t lhs_rows_idx = lhs_rows >> 1; + + while (lhs_rows_idx) + { + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = lhs_offset_contribution0; + q31_t res01 = lhs_offset_contribution1; + q31_t res10 = lhs_offset_contribution0; + q31_t res11 = lhs_offset_contribution1; + + int32_t rhs_cols_idx = 0; + + q31_t val0, val1, val2, val3, val4, val5; + + for (; rhs_cols_idx <= (rhs_cols - 16); rhs_cols_idx += 16) + { + val1 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + val2 = __SXTB16(val1); + val0 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val4 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val1 = __SXTB16_RORn(val1, 8); + val0 = __SXTB16_RORn(val0, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val3, val2, res00); + val5 = __SXTB16(val4); + res00 = __SMLAD(val0, val1, res00); + val4 = __SXTB16_RORn(val4, 8); + res01 = __SMLAD(val3, val5, res01); + res01 = __SMLAD(val0, val4, res01); + + // 4 x MAC res10, res11 + val0 = arm_nn_read_q7x4((const q7_t *)&lhs_ptr[off0]); + val3 = __SXTB16(val0); + val0 = __SXTB16_RORn(val0, 8); + res10 = __SMLAD(val3, val2, res10); + res11 = __SMLAD(val3, val5, res11); + res10 = __SMLAD(val0, val1, res10); + val1 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + res11 = __SMLAD(val0, val4, res11); + + val4 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = __SXTB16(val1); + val0 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val1 = __SXTB16_RORn(val1, 8); + val0 = __SXTB16_RORn(val0, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val3, val2, res00); + val5 = __SXTB16(val4); + res00 = __SMLAD(val0, val1, res00); + val4 = __SXTB16_RORn(val4, 8); + res01 = __SMLAD(val3, val5, res01); + res01 = __SMLAD(val0, val4, res01); + + // 4 x MAC res10, res11 + val0 = arm_nn_read_q7x4((const q7_t *)&lhs_ptr[off0]); + val3 = __SXTB16(val0); + val0 = __SXTB16_RORn(val0, 8); + res10 = __SMLAD(val3, val2, res10); + res11 = __SMLAD(val3, val5, res11); + res10 = __SMLAD(val0, val1, res10); + val1 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + res11 = __SMLAD(val0, val4, res11); + + val4 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = __SXTB16(val1); + val0 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val1 = __SXTB16_RORn(val1, 8); + val0 = __SXTB16_RORn(val0, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val3, val2, res00); + val5 = __SXTB16(val4); + res00 = __SMLAD(val0, val1, res00); + val4 = __SXTB16_RORn(val4, 8); + res01 = __SMLAD(val3, val5, res01); + res01 = __SMLAD(val0, val4, res01); + + // 4 x MAC res10, res11 + val0 = arm_nn_read_q7x4((const q7_t *)&lhs_ptr[off0]); + val3 = __SXTB16(val0); + val0 = __SXTB16_RORn(val0, 8); + res10 = __SMLAD(val3, val2, res10); + res11 = __SMLAD(val3, val5, res11); + res10 = __SMLAD(val0, val1, res10); + val1 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + res11 = __SMLAD(val0, val4, res11); + + val4 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = __SXTB16(val1); + val0 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val1 = __SXTB16_RORn(val1, 8); + val0 = __SXTB16_RORn(val0, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val3, val2, res00); + val5 = __SXTB16(val4); + res00 = __SMLAD(val0, val1, res00); + val4 = __SXTB16_RORn(val4, 8); + res01 = __SMLAD(val3, val5, res01); + res01 = __SMLAD(val0, val4, res01); + + // 4 x MAC res10, res11 + val0 = arm_nn_read_q7x4((const q7_t *)&lhs_ptr[off0]); + val3 = __SXTB16(val0); + val0 = __SXTB16_RORn(val0, 8); + res10 = __SMLAD(val3, val2, res10); + res11 = __SMLAD(val3, val5, res11); + res10 = __SMLAD(val0, val1, res10); + res11 = __SMLAD(val0, val4, res11); + } + + for (; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q7_t rhs_value0 = rhs_ptr[0]; + q7_t rhs_value1 = rhs_ptr[rhs_cols]; + q7_t lhs_value = lhs_ptr[0]; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + + lhs_value = lhs_ptr[rhs_cols]; + res10 += lhs_value * rhs_value0; + res11 += lhs_value * rhs_value1; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res01 = arm_nn_requantize(res01, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + res10 = arm_nn_requantize(res10, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res11 = arm_nn_requantize(res11, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + res10 += dst_offset; + res11 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + res10 = MAX(res10, activation_min); + res10 = MIN(res10, activation_max); + res11 = MAX(res11, activation_min); + res11 = MIN(res11, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr[1] = (q7_t)res01; + dst_ptr += rhs_rows; + dst_ptr[0] = (q7_t)res10; + dst_ptr[1] = (q7_t)res11; + dst_ptr += rhs_rows; + + lhs_ptr += rhs_cols; + + lhs_rows_idx--; + } + + // Left-over rows + if (lhs_rows % 2) + { + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = lhs_offset_contribution0; + q31_t res01 = lhs_offset_contribution1; + + int32_t rhs_cols_idx = 0; + + q31_t val0, val1, val2, val3, val4, val5; + for (; rhs_cols_idx <= (rhs_cols - 16); rhs_cols_idx += 16) + { + val0 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + val1 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val5 = __SXTB16(val2); + val4 = __SXTB16(val1); + val0 = __SXTB16_RORn(val0, 8); + val2 = __SXTB16_RORn(val2, 8); + val1 = __SXTB16_RORn(val1, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val5, val3, res00); + res00 = __SMLAD(val2, val0, res00); + res01 = __SMLAD(val5, val4, res01); + res01 = __SMLAD(val2, val1, res01); + + val0 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + val1 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val5 = __SXTB16(val2); + val4 = __SXTB16(val1); + val0 = __SXTB16_RORn(val0, 8); + val2 = __SXTB16_RORn(val2, 8); + val1 = __SXTB16_RORn(val1, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val5, val3, res00); + res00 = __SMLAD(val2, val0, res00); + res01 = __SMLAD(val5, val4, res01); + res01 = __SMLAD(val2, val1, res01); + + val0 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + val1 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val5 = __SXTB16(val2); + val4 = __SXTB16(val1); + val0 = __SXTB16_RORn(val0, 8); + val2 = __SXTB16_RORn(val2, 8); + val1 = __SXTB16_RORn(val1, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val5, val3, res00); + res00 = __SMLAD(val2, val0, res00); + res01 = __SMLAD(val5, val4, res01); + res01 = __SMLAD(val2, val1, res01); + + val0 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + val1 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val5 = __SXTB16(val2); + val4 = __SXTB16(val1); + val0 = __SXTB16_RORn(val0, 8); + val2 = __SXTB16_RORn(val2, 8); + val1 = __SXTB16_RORn(val1, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val5, val3, res00); + res00 = __SMLAD(val2, val0, res00); + res01 = __SMLAD(val5, val4, res01); + res01 = __SMLAD(val2, val1, res01); + } + + // Left-over accumulations + for (; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q7_t rhs_value0 = rhs_ptr[0]; + q7_t rhs_value1 = rhs_ptr[rhs_cols]; + q7_t lhs_value = lhs_ptr[0]; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res01 = arm_nn_requantize(res01, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr[1] = (q7_t)res01; + } + + rhs += 2 * rhs_cols; + dst += 2; + } + + if (rhs_rows % 2) + { + const q7_t *lhs_ptr = &lhs[0]; + q7_t *dst_ptr = &dst[0]; + + for (int32_t lhs_rows_idx = 0; lhs_rows_idx < lhs_rows; ++lhs_rows_idx) + { + const q7_t *rhs_ptr = &rhs[0]; + q31_t res00 = 0; + if (bias) + { + res00 = bias[rhs_rows - 1]; + } + + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q31_t rhs_value = rhs_ptr[0]; + q31_t lhs_value = lhs_ptr[0] + lhs_offset; + + res00 += lhs_value * rhs_value; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multipliers[rhs_rows - 1], dst_shifts[rhs_rows - 1]); + + // Add offset + res00 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr += rhs_rows; + } + } +#else + for (int32_t rhs_rows_idx = 0; rhs_rows_idx <= (rhs_rows - 2); rhs_rows_idx += 2) + { + const q7_t *lhs_ptr = &lhs[0]; + q7_t *dst_ptr = &dst[0]; + + q31_t lhs_offset_contribution0 = 0; + q31_t lhs_offset_contribution1 = 0; + + for (int32_t x = 0; x < rhs_cols; ++x) + { + lhs_offset_contribution0 += rhs[x]; + lhs_offset_contribution1 += rhs[x + rhs_cols]; + } + + lhs_offset_contribution0 *= lhs_offset; + lhs_offset_contribution1 *= lhs_offset; + if (bias) + { + lhs_offset_contribution0 += bias[rhs_rows_idx]; + lhs_offset_contribution1 += bias[rhs_rows_idx + 1]; + } + + int32_t lhs_rows_idx = lhs_rows >> 1; + + while (lhs_rows_idx) + { + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = lhs_offset_contribution0; + q31_t res01 = lhs_offset_contribution1; + q31_t res10 = lhs_offset_contribution0; + q31_t res11 = lhs_offset_contribution1; + + for (int32_t rhs_cols_idx = rhs_cols; rhs_cols_idx != 0; rhs_cols_idx--) + { + q7_t rhs_value0 = rhs_ptr[0]; + q7_t rhs_value1 = rhs_ptr[rhs_cols]; + q7_t lhs_value = lhs_ptr[0]; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + + lhs_value = lhs_ptr[rhs_cols]; + res10 += lhs_value * rhs_value0; + res11 += lhs_value * rhs_value1; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res01 = arm_nn_requantize(res01, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + res10 = arm_nn_requantize(res10, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res11 = arm_nn_requantize(res11, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + res10 += dst_offset; + res11 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + res10 = MAX(res10, activation_min); + res10 = MIN(res10, activation_max); + res11 = MAX(res11, activation_min); + res11 = MIN(res11, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr[1] = (q7_t)res01; + dst_ptr += rhs_rows; + dst_ptr[0] = (q7_t)res10; + dst_ptr[1] = (q7_t)res11; + dst_ptr += rhs_rows; + + lhs_ptr += rhs_cols; + + lhs_rows_idx--; + } + + // Left-over rows + if (lhs_rows % 2) + { + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = lhs_offset_contribution0; + q31_t res01 = lhs_offset_contribution1; + + for (int32_t rhs_cols_idx = rhs_cols; rhs_cols_idx != 0; rhs_cols_idx--) + { + q7_t rhs_value0 = rhs_ptr[0]; + q7_t rhs_value1 = rhs_ptr[rhs_cols]; + q7_t lhs_value = lhs_ptr[0]; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res01 = arm_nn_requantize(res01, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr[1] = (q7_t)res01; + } + + rhs += 2 * rhs_cols; + dst += 2; + } + + if (rhs_rows % 2) + { + const q7_t *lhs_ptr = &lhs[0]; + q7_t *dst_ptr = &dst[0]; + + for (int32_t lhs_rows_idx = 0; lhs_rows_idx < lhs_rows; ++lhs_rows_idx) + { + const q7_t *rhs_ptr = &rhs[0]; + q31_t res00 = 0; + if (bias) + { + res00 = bias[rhs_rows - 1]; + } + + for (int32_t rhs_cols_idx = rhs_cols; rhs_cols_idx != 0; rhs_cols_idx--) + { + q31_t rhs_value = rhs_ptr[0]; + q31_t lhs_value = lhs_ptr[0] + lhs_offset; + + res00 += lhs_value * rhs_value; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multipliers[rhs_rows - 1], dst_shifts[rhs_rows - 1]); + + // Add offset + res00 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr += rhs_rows; + } + } +#endif + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c new file mode 100644 index 00000000..d6a45efe --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mult_q15.c + * Description: Q15 vector multiplication with variable output shifts + * + * $Date: 20. July 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/** + * @brief Q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_nn_mult_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, const uint16_t out_shift, uint32_t blockSize) +{ + uint32_t blkCnt = blockSize; /* loop counters */ + + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q15_t)__SSAT(((q31_t)((q31_t)(*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 16); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of NNBasicMath group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c new file mode 100644 index 00000000..fdced4cf --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mult_q7.c + * Description: Q7 vector multiplication with variable output shifts + * + * $Date: 20. July 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/** + * @brief Q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void arm_nn_mult_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, const uint16_t out_shift, uint32_t blockSize) +{ + uint32_t blkCnt = blockSize; /* loop counters */ + + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q7_t)__SSAT(((q15_t)((q15_t)(*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of NNBasicMath group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s16.c b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s16.c new file mode 100644 index 00000000..5956d3aa --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s16.c @@ -0,0 +1,211 @@ +/* + * Copyright (C) 2020-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_vec_mat_mult_t_s16 + * Description: s16 vector by matrix (transposed) multiplication + * + * $Date: 04. January 2022 + * $Revision: V.1.2.0 + * + * Target Processor: Cortex-M + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s16 vector(lhs) by matrix (transposed) multiplication + * + * Refer header file for details. + * + */ +arm_status arm_nn_vec_mat_mult_t_s16(const q15_t *lhs, + const q7_t *rhs, + const q63_t *bias, + q15_t *dst, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max) +{ +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + const int32_t row_loop_cnt = rhs_rows / 2; + + int32_t rhs_cols_fast = rhs_cols; + + if (rhs_cols > 512) + { + rhs_cols_fast = 512; + } + + for (int32_t i = 0; i < row_loop_cnt; i++) + { + q63_t acc_64_0 = 0; + q63_t acc_64_1 = 0; + int32_t acc_0 = 0; + int32_t acc_1 = 0; + + const int32_t col_loop_cnt = rhs_cols_fast / 4; + + const int16_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + const int8_t *rhs_1 = rhs + rhs_cols; + rhs += 2 * rhs_cols; + + for (int j = col_loop_cnt; j != 0; j--) + { + int32_t ker_0, ker_1, vec_part_0, vec_part_1; + vec_part_0 = arm_nn_read_q15x2_ia(&lhs_vec); + vec_part_1 = arm_nn_read_q15x2_ia(&lhs_vec); + + rhs_0 = read_and_pad(rhs_0, &ker_0, &ker_1); + + acc_0 = __SMLAD(ker_0, vec_part_0, acc_0); + acc_0 = __SMLAD(ker_1, vec_part_1, acc_0); + + rhs_1 = read_and_pad(rhs_1, &ker_0, &ker_1); + + acc_1 = __SMLAD(ker_0, vec_part_0, acc_1); + acc_1 = __SMLAD(ker_1, vec_part_1, acc_1); + } + + acc_64_0 += acc_0; + acc_64_1 += acc_1; + + for (int k = col_loop_cnt * 4; k < rhs_cols; k++) + { + const int32_t lhs_temp = (*lhs_vec); + lhs_vec++; + acc_64_0 += lhs_temp * (*rhs_0); + rhs_0++; + acc_64_1 += lhs_temp * (*rhs_1); + rhs_1++; + } + + if (bias) + { + acc_64_0 += *bias++; + acc_64_1 += *bias++; + } + q31_t tmp; + tmp = arm_nn_requantize_s64(acc_64_0, dst_multiplier, dst_shift); + tmp = MAX(tmp, activation_min); + tmp = MIN(tmp, activation_max); + *dst++ = (q15_t)tmp; + + tmp = arm_nn_requantize_s64(acc_64_1, dst_multiplier, dst_shift); + tmp = MAX(tmp, activation_min); + tmp = MIN(tmp, activation_max); + *dst++ = (q15_t)tmp; + } + + if (rhs_rows & 0x1) + { + q63_t acc_64_0 = 0; + int32_t acc_0 = 0; + const int32_t col_loop_cnt = rhs_cols_fast / 4; + + const int16_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + + for (int i = col_loop_cnt; i != 0; i--) + { + int32_t ker_0, ker_1, vec; + rhs_0 = read_and_pad(rhs_0, &ker_0, &ker_1); + + vec = arm_nn_read_q15x2_ia(&lhs_vec); + acc_0 = __SMLAD(ker_0, vec, acc_0); + + vec = arm_nn_read_q15x2_ia(&lhs_vec); + acc_0 = __SMLAD(ker_1, vec, acc_0); + } + + acc_64_0 += acc_0; + + for (int j = col_loop_cnt * 4; j < rhs_cols; j++) + { + const int32_t lhs_temp = (*lhs_vec); + lhs_vec++; + acc_64_0 += lhs_temp * (*rhs_0); + rhs_0++; + } + + if (bias) + { + acc_64_0 += *bias++; + } + q31_t tmp; + tmp = arm_nn_requantize_s64(acc_64_0, dst_multiplier, dst_shift); + tmp = MAX(tmp, activation_min); + tmp = MIN(tmp, activation_max); + *dst++ = (q15_t)tmp; + } + +#else + for (int i_row_loop_cnt = 0; i_row_loop_cnt < rhs_rows; i_row_loop_cnt++) + { + const q15_t *lhs_ptr = lhs; + const q7_t *rhs_ptr_0 = &rhs[0]; + + q63_t result = 0; + + if (bias) + { + result = *bias++; + } + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + const q63_t rhs_value0 = (int8_t)*rhs_ptr_0; + const q63_t lhs_value = *lhs_ptr; + + result += lhs_value * rhs_value0; + + ++rhs_ptr_0; + ++lhs_ptr; + } + + // Quantize down + result = arm_nn_requantize_s64(result, dst_multiplier, dst_shift); + + // Clamp the result + result = ((result) > (activation_min) ? (result) : (activation_min)); + result = ((result) < (activation_max) ? (result) : (activation_max)); + + *dst++ = (q15_t)result; + rhs += rhs_cols; + } +#endif + + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c new file mode 100644 index 00000000..c7dfd140 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c @@ -0,0 +1,402 @@ +/* + * Copyright (C) 2020-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_vec_mat_mult_t_s8 + * Description: s8 vector by matrix (transposed) multiplication + * + * $Date: 28 April 2022 + * $Revision: V.3.0.1 + * + * Target Processor: Cortex-M + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 vector(lhs) by matrix (transposed) multiplication + * + * Refer header file for details. + * + */ +arm_status arm_nn_vec_mat_mult_t_s8(const q7_t *lhs, + const q7_t *rhs, + const q31_t *bias, + q7_t *dst, + const int32_t lhs_offset, + const int32_t rhs_offset, + const int32_t dst_offset, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max, + const int32_t address_offset) +{ + (void)rhs_offset; +#if defined(ARM_MATH_MVEI) + const int32_t row_loop_cnt = rhs_rows / 3; + const uint32x4_t address_offset_array = {0, address_offset, address_offset * 2, address_offset * 3}; + + for (int i_row_loop_cnt = 0; i_row_loop_cnt < row_loop_cnt; i_row_loop_cnt++) + { + int32_t acc_0 = 0; + int32_t acc_1 = 0; + int32_t acc_2 = 0; + + const int32_t col_loop_cnt = (rhs_cols + 15) / 16; + + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + const int8_t *rhs_1 = rhs + rhs_cols; + const int8_t *rhs_2 = rhs + 2 * rhs_cols; + + int32_t rhs_sum_0 = 0; + int32_t rhs_sum_1 = 0; + int32_t rhs_sum_2 = 0; + + uint32_t col_cnt = (uint32_t)rhs_cols; + + for (int i = 0; i < col_loop_cnt; i++) + { + mve_pred16_t p = vctp8q(col_cnt); + col_cnt -= 16; + + const int8x16_t input = vldrbq_z_s8(lhs_vec, p); + + const int8x16_t ker_0 = vldrbq_z_s8(rhs_0, p); + rhs_sum_0 = vaddvaq_p_s8(rhs_sum_0, ker_0, p); + acc_0 = vmladavaq_p_s8(acc_0, ker_0, input, p); + + const int8x16_t ker_1 = vldrbq_z_s8(rhs_1, p); + rhs_sum_1 = vaddvaq_p_s8(rhs_sum_1, ker_1, p); + acc_1 = vmladavaq_p_s8(acc_1, ker_1, input, p); + + const int8x16_t ker_2 = vldrbq_z_s8(rhs_2, p); + rhs_sum_2 = vaddvaq_p_s8(rhs_sum_2, ker_2, p); + acc_2 = vmladavaq_p_s8(acc_2, ker_2, input, p); + + lhs_vec += 16; + rhs_0 += 16; + rhs_1 += 16; + rhs_2 += 16; + } + rhs += 3 * rhs_cols; + + int32x4_t acc = {acc_0, acc_1, acc_2, 0}; + mve_pred16_t p = vctp32q(3); + if (bias) + { + int32x4_t b = vldrwq_z_s32(bias, p); + acc = vaddq_m_s32(vuninitializedq_s32(), acc, b, p); + bias += 3; + } + const int32x4_t rhs_sum = {rhs_sum_0, rhs_sum_1, rhs_sum_2, 0}; + acc += vdupq_n_s32(lhs_offset) * rhs_sum; + + acc = arm_requantize_mve(acc, dst_multiplier, dst_shift); + acc = vaddq_s32(acc, vdupq_n_s32(dst_offset)); + acc = vmaxq_s32(acc, vdupq_n_s32(activation_min)); + acc = vminq_s32(acc, vdupq_n_s32(activation_max)); + + if (address_offset > 1L) + { + vstrbq_scatter_offset_s32(dst, address_offset_array, acc); + } + else + { + vstrbq_p_s32(dst, acc, p); + } + dst += 3 * address_offset; + } + + const int loop_cnt = rhs_rows % 3; + for (int i_row_loop_cnt = 0; i_row_loop_cnt < loop_cnt; i_row_loop_cnt++) + { + int32_t acc_0 = 0; + const int32_t col_loop_cnt = (rhs_cols + 15) / 16; + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + int32_t rhs_sum_0 = 0; + uint32_t col_cnt = (uint32_t)rhs_cols; + + for (int i = 0; i < col_loop_cnt; i++) + { + mve_pred16_t p = vctp8q(col_cnt); + col_cnt -= 16; + const int8x16_t input = vldrbq_z_s8(lhs_vec, p); + + const int8x16_t ker_0 = vldrbq_z_s8(rhs_0, p); + rhs_sum_0 = vaddvaq_p_s8(rhs_sum_0, ker_0, p); + acc_0 = vmladavaq_p_s8(acc_0, ker_0, input, p); + + lhs_vec += 16; + rhs_0 += 16; + } + rhs += rhs_cols; + + if (bias) + { + acc_0 += *bias; + bias++; + } + const int32_t offsets = rhs_sum_0 * lhs_offset; + acc_0 += offsets; + acc_0 = arm_nn_requantize(acc_0, dst_multiplier, dst_shift); + acc_0 += dst_offset; + + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + *dst = MIN(acc_0, activation_max); + dst += address_offset; + } + +#elif defined(ARM_MATH_DSP) + const int32_t row_loop_cnt = rhs_rows / 2; + const int16_t lhs_offset_s16 = (int16_t)lhs_offset; + const uint32_t lhs_offset_s16x2 = __PKHBT(lhs_offset_s16, lhs_offset_s16, 16); + + for (int32_t i = 0; i < row_loop_cnt; i++) + { + int32_t acc_0 = 0; + int32_t acc_1 = 0; + if (bias) + { + acc_0 = *bias++; + acc_1 = *bias++; + } + + const int32_t col_loop_cnt = rhs_cols / 4; + + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + const int8_t *rhs_1 = rhs + rhs_cols; + rhs += 2 * rhs_cols; + + for (int j = col_loop_cnt; j != 0; j--) + { + int32_t vec_0 = arm_nn_read_q7x4_ia(&lhs_vec); + int32_t vec_1 = __SXTAB16_RORn(lhs_offset_s16x2, (uint32_t)vec_0, 8); + + vec_0 = __SXTAB16(lhs_offset_s16x2, vec_0); + + int32_t ker_0 = arm_nn_read_q7x4_ia(&rhs_0); + int32_t ker_1 = __SXTB16_RORn((uint32_t)ker_0, 8); + ker_0 = __SXTB16(ker_0); + + acc_0 = __SMLAD(ker_1, vec_1, acc_0); + acc_0 = __SMLAD(ker_0, vec_0, acc_0); + + ker_0 = arm_nn_read_q7x4_ia(&rhs_1); + ker_1 = __SXTB16_RORn((uint32_t)ker_0, 8); + ker_0 = __SXTB16(ker_0); + + acc_1 = __SMLAD(ker_1, vec_1, acc_1); + acc_1 = __SMLAD(ker_0, vec_0, acc_1); + } + + for (int k = col_loop_cnt * 4; k < rhs_cols; k++) + { + const int32_t lhs_temp = (*lhs_vec + lhs_offset); + lhs_vec++; + acc_0 += lhs_temp * (*rhs_0); + rhs_0++; + acc_1 += lhs_temp * (*rhs_1); + rhs_1++; + } + + acc_0 = arm_nn_requantize(acc_0, dst_multiplier, dst_shift); + acc_1 = arm_nn_requantize(acc_1, dst_multiplier, dst_shift); + + // Add offset + acc_0 += dst_offset; + acc_1 += dst_offset; + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + acc_0 = MIN(acc_0, activation_max); + acc_1 = MAX(acc_1, activation_min); + acc_1 = MIN(acc_1, activation_max); + *dst = (int8_t)acc_0; + *(dst + address_offset) = (int8_t)acc_1; + dst += 2 * address_offset; + } + + if (rhs_rows & 0x1) + { + int32_t acc_0 = 0; + if (bias) + { + acc_0 = *bias++; + } + const int32_t col_loop_cnt = rhs_cols / 4; + + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + + for (int i = col_loop_cnt; i != 0; i--) + { + int32_t vec_0 = arm_nn_read_q7x4_ia(&lhs_vec); + int32_t vec_1 = __SXTAB16_RORn(lhs_offset_s16x2, (uint32_t)vec_0, 8); + vec_0 = __SXTAB16(lhs_offset_s16x2, vec_0); + + int32_t ker_0 = arm_nn_read_q7x4_ia(&rhs_0); + int32_t ker_1 = __SXTB16_RORn((uint32_t)ker_0, 8); + ker_0 = __SXTB16(ker_0); + + acc_0 = __SMLAD(ker_1, vec_1, acc_0); + acc_0 = __SMLAD(ker_0, vec_0, acc_0); + } + + for (int j = col_loop_cnt * 4; j < rhs_cols; j++) + { + const int32_t lhs_temp = (*lhs_vec + lhs_offset); + lhs_vec++; + acc_0 += lhs_temp * (*rhs_0); + rhs_0++; + } + + acc_0 = arm_nn_requantize(acc_0, dst_multiplier, dst_shift); + + // Add offset + acc_0 += dst_offset; + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + acc_0 = MIN(acc_0, activation_max); + *dst = (int8_t)acc_0; + dst += address_offset; + } + +#else + + const int32_t row_loop_cnt = rhs_rows / 3; + + for (int i_row_loop_cnt = 0; i_row_loop_cnt < row_loop_cnt; i_row_loop_cnt++) + { + const q7_t *lhs_ptr = lhs; + const q7_t *rhs_ptr_0 = &rhs[0]; + const q7_t *rhs_ptr_1 = &rhs[rhs_cols]; + const q7_t *rhs_ptr_2 = &rhs[rhs_cols * 2]; + + q31_t res00 = 0; + q31_t res01 = 0; + q31_t res02 = 0; + if (bias) + { + res00 = *bias++; + res01 = *bias++; + res02 = *bias++; + } + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + const q31_t rhs_value0 = (int8_t)*rhs_ptr_0; + const q31_t rhs_value1 = (int8_t)*rhs_ptr_1; + const q31_t rhs_value2 = (int8_t)*rhs_ptr_2; + const q31_t lhs_value = (int8_t)*lhs_ptr + lhs_offset; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + res02 += lhs_value * rhs_value2; + + ++rhs_ptr_0; + ++rhs_ptr_1; + ++rhs_ptr_2; + ++lhs_ptr; + } + // Quantize down + res00 = arm_nn_requantize(res00, dst_multiplier, dst_shift); + res01 = arm_nn_requantize(res01, dst_multiplier, dst_shift); + res02 = arm_nn_requantize(res02, dst_multiplier, dst_shift); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + res02 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + res02 = MAX(res02, activation_min); + res02 = MIN(res02, activation_max); + + *dst = (q7_t)res00; + *(dst + address_offset) = (q7_t)res01; + *(dst + 2 * address_offset) = (q7_t)res02; + dst += 3 * address_offset; + + rhs += 3 * rhs_cols; + } + + const int loop_cnt = rhs_rows % 3; + + for (int i_loop_cnt = 0; i_loop_cnt < loop_cnt; i_loop_cnt++) + { + const q7_t *lhs_ptr = &lhs[0]; + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = 0; + if (bias) + { + res00 = *bias++; + } + + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q31_t rhs_value0 = (int8_t)rhs_ptr[0]; + q31_t lhs_value = (int8_t)lhs_ptr[0] + lhs_offset; + + res00 += lhs_value * rhs_value0; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multiplier, dst_shift); + + // Add offset + res00 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + + *dst = (int8_t)res00; + dst += address_offset; + rhs += rhs_cols; + } +#endif + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c new file mode 100644 index 00000000..5b821c3b --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c @@ -0,0 +1,341 @@ +/* + * Copyright (C) 2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_vec_mat_mult_t_svdf_s8 + * Description: s8 vector by matrix (transposed) multiplication with + * s16 output. Targetted at SVDF operator. + * + * $Date: 15. April 2021 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 vector(lhs) by matrix (transposed) multiplication + * + * Refer header file for details. + * + */ +arm_status arm_nn_vec_mat_mult_t_svdf_s8(const q7_t *lhs, + const q7_t *rhs, + q15_t *dst, + const int32_t lhs_offset, + const int32_t rhs_offset, + const int32_t dst_offset, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max) +{ + (void)rhs_offset; + if (rhs_cols < 0 || (NN_Q31_MAX - rhs_cols) < 16 || dst_offset < 0) + { + return ARM_MATH_ARGUMENT_ERROR; + } + + (void)rhs_offset; +#if defined(ARM_MATH_MVEI) + int32_t row_loop_cnt = rhs_rows / 3; + + for (int i_row_loop_cnt = 0; i_row_loop_cnt < row_loop_cnt; i_row_loop_cnt++) + { + int32_t acc_0 = 0; + int32_t acc_1 = 0; + int32_t acc_2 = 0; + + const int32_t col_loop_cnt = (rhs_cols + 15) / 16; + + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + const int8_t *rhs_1 = rhs + rhs_cols; + const int8_t *rhs_2 = rhs + 2 * rhs_cols; + + int32_t rhs_sum_0 = 0; + int32_t rhs_sum_1 = 0; + int32_t rhs_sum_2 = 0; + + uint32_t col_cnt = (uint32_t)rhs_cols; + + for (int i = 0; i < col_loop_cnt; i++) + { + mve_pred16_t p = vctp8q(col_cnt); + col_cnt -= 16; + + const int8x16_t input = vldrbq_z_s8(lhs_vec, p); + + const int8x16_t ker_0 = vldrbq_z_s8(rhs_0, p); + rhs_sum_0 = vaddvaq_p_s8(rhs_sum_0, ker_0, p); + acc_0 = vmladavaq_p_s8(acc_0, ker_0, input, p); + + const int8x16_t ker_1 = vldrbq_z_s8(rhs_1, p); + rhs_sum_1 = vaddvaq_p_s8(rhs_sum_1, ker_1, p); + acc_1 = vmladavaq_p_s8(acc_1, ker_1, input, p); + + const int8x16_t ker_2 = vldrbq_z_s8(rhs_2, p); + rhs_sum_2 = vaddvaq_p_s8(rhs_sum_2, ker_2, p); + acc_2 = vmladavaq_p_s8(acc_2, ker_2, input, p); + + lhs_vec += 16; + rhs_0 += 16; + rhs_1 += 16; + rhs_2 += 16; + } + rhs += 3 * rhs_cols; + + int32x4_t acc = {acc_0, acc_1, acc_2, 0}; + const int32x4_t rhs_sum = {rhs_sum_0, rhs_sum_1, rhs_sum_2, 0}; + acc += vdupq_n_s32(lhs_offset) * rhs_sum; + + acc = arm_requantize_mve(acc, dst_multiplier, dst_shift); + acc = vmaxq_s32(acc, vdupq_n_s32(activation_min)); + acc = vminq_s32(acc, vdupq_n_s32(activation_max)); + *(dst) = (int16_t)acc[0]; + *(dst + dst_offset) = (int16_t)acc[1]; + *(dst + 2 * dst_offset) = (int16_t)acc[2]; + dst += 3 * dst_offset; + } + + const int loop_cnt = rhs_rows % 3; + for (int i_row_loop_cnt = 0; i_row_loop_cnt < loop_cnt; i_row_loop_cnt++) + { + int32_t acc_0 = 0; + const int32_t col_loop_cnt = (rhs_cols + 15) / 16; + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + int32_t rhs_sum_0 = 0; + uint32_t col_cnt = (uint32_t)rhs_cols; + + for (int i = 0; i < col_loop_cnt; i++) + { + mve_pred16_t p = vctp8q(col_cnt); + col_cnt -= 16; + const int8x16_t input = vldrbq_z_s8(lhs_vec, p); + + const int8x16_t ker_0 = vldrbq_z_s8(rhs_0, p); + rhs_sum_0 = vaddvaq_p_s8(rhs_sum_0, ker_0, p); + acc_0 = vmladavaq_p_s8(acc_0, ker_0, input, p); + + lhs_vec += 16; + rhs_0 += 16; + } + rhs += rhs_cols; + + const int32_t offsets = rhs_sum_0 * lhs_offset; + acc_0 = __QADD(acc_0, offsets); + acc_0 = arm_nn_requantize(acc_0, dst_multiplier, dst_shift); + + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + *dst = (q15_t)MIN(acc_0, activation_max); + dst += dst_offset; + } + +#elif defined(ARM_MATH_DSP) + int32_t row_loop_cnt = rhs_rows / 2; + + const int16_t lhs_offset_s16 = lhs_offset; + const int16_t rhs_offset_s16 = rhs_offset; + + const uint32_t lhs_offset_s16x2 = __PKHBT(lhs_offset_s16, lhs_offset_s16, 16); + const uint32_t rhs_offset_s16x2 = __PKHBT(rhs_offset_s16, rhs_offset_s16, 16); + for (int32_t i = 0; i < row_loop_cnt; i++) + { + int32_t acc_0 = 0; + int32_t acc_1 = 0; + + const int32_t col_loop_cnt = rhs_cols / 4; + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + const int8_t *rhs_1 = rhs + rhs_cols; + rhs += 2 * rhs_cols; + for (int j = col_loop_cnt; j != 0; j--) + { + int32_t vec_0 = arm_nn_read_q7x4_ia(&lhs_vec); + int32_t vec_1 = __SXTAB16_RORn(lhs_offset_s16x2, (uint32_t)vec_0, 8); + vec_0 = __SXTAB16(lhs_offset_s16x2, vec_0); + int32_t ker_0 = arm_nn_read_q7x4_ia(&rhs_0); + int32_t ker_1 = __SXTAB16_RORn(rhs_offset_s16x2, (uint32_t)ker_0, 8); + ker_0 = __SXTAB16(rhs_offset_s16x2, ker_0); + acc_0 = __SMLAD(ker_1, vec_1, acc_0); + acc_0 = __SMLAD(ker_0, vec_0, acc_0); + ker_0 = arm_nn_read_q7x4_ia(&rhs_1); + ker_1 = __SXTAB16_RORn(rhs_offset_s16x2, (uint32_t)ker_0, 8); + ker_0 = __SXTAB16(rhs_offset_s16x2, ker_0); + acc_1 = __SMLAD(ker_1, vec_1, acc_1); + acc_1 = __SMLAD(ker_0, vec_0, acc_1); + } + for (int k = col_loop_cnt * 4; k < rhs_cols; k++) + { + const int32_t lhs_temp = (*lhs_vec + lhs_offset); + lhs_vec++; + acc_0 += lhs_temp * (*rhs_0 + rhs_offset); + rhs_0++; + acc_1 += lhs_temp * (*rhs_1 + rhs_offset); + rhs_1++; + } + acc_0 = arm_nn_requantize(acc_0, dst_multiplier, dst_shift); + acc_1 = arm_nn_requantize(acc_1, dst_multiplier, dst_shift); + + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + acc_0 = MIN(acc_0, activation_max); + acc_1 = MAX(acc_1, activation_min); + acc_1 = MIN(acc_1, activation_max); + *dst = (q15_t)acc_0; + *(dst + dst_offset) = (q15_t)acc_1; + dst += 2 * dst_offset; + } + if (rhs_rows & 0x1) + { + int32_t acc_0 = 0; + const int32_t col_loop_cnt = rhs_cols / 4; + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + for (int i = col_loop_cnt; i != 0; i--) + { + int32_t vec_0 = arm_nn_read_q7x4_ia(&lhs_vec); + int32_t vec_1 = __SXTAB16(lhs_offset_s16x2, __ROR((uint32_t)vec_0, 8)); + vec_0 = __SXTAB16(lhs_offset_s16x2, vec_0); + int32_t ker_0 = arm_nn_read_q7x4_ia(&rhs_0); + int32_t ker_1 = __SXTAB16(rhs_offset_s16x2, __ROR((uint32_t)ker_0, 8)); + ker_0 = __SXTAB16(rhs_offset_s16x2, ker_0); + acc_0 = __SMLAD(ker_1, vec_1, acc_0); + acc_0 = __SMLAD(ker_0, vec_0, acc_0); + } + for (int j = col_loop_cnt * 4; j < rhs_cols; j++) + { + const int32_t lhs_temp = (*lhs_vec + lhs_offset); + lhs_vec++; + acc_0 += lhs_temp * (*rhs_0 + rhs_offset); + rhs_0++; + } + acc_0 = arm_nn_requantize(acc_0, dst_multiplier, dst_shift); + + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + acc_0 = MIN(acc_0, activation_max); + *dst = (q15_t)acc_0; + dst += dst_offset; + } + +#else + + int32_t row_loop_cnt = rhs_rows / 3; + + for (int i_row_loop_cnt = 0; i_row_loop_cnt < row_loop_cnt; i_row_loop_cnt++) + { + const q7_t *lhs_ptr = lhs; + const q7_t *rhs_ptr_0 = &rhs[0]; + const q7_t *rhs_ptr_1 = &rhs[rhs_cols]; + const q7_t *rhs_ptr_2 = &rhs[rhs_cols * 2]; + + q31_t res00 = 0; + q31_t res01 = 0; + q31_t res02 = 0; + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + const q31_t rhs_value0 = (int8_t)*rhs_ptr_0; + const q31_t rhs_value1 = (int8_t)*rhs_ptr_1; + const q31_t rhs_value2 = (int8_t)*rhs_ptr_2; + const q31_t lhs_value = (int8_t)*lhs_ptr + lhs_offset; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + res02 += lhs_value * rhs_value2; + + ++rhs_ptr_0; + ++rhs_ptr_1; + ++rhs_ptr_2; + ++lhs_ptr; + } + // Quantize down + res00 = arm_nn_requantize(res00, dst_multiplier, dst_shift); + res01 = arm_nn_requantize(res01, dst_multiplier, dst_shift); + res02 = arm_nn_requantize(res02, dst_multiplier, dst_shift); + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + res02 = MAX(res02, activation_min); + res02 = MIN(res02, activation_max); + + *dst = (q15_t)res00; + *(dst + dst_offset) = (q15_t)res01; + *(dst + 2 * dst_offset) = (q15_t)res02; + dst += 3 * dst_offset; + rhs += 3 * rhs_cols; + } + + const int loop_cnt = rhs_rows % 3; + + for (int i_loop_cnt = 0; i_loop_cnt < loop_cnt; i_loop_cnt++) + { + const q7_t *lhs_ptr = &lhs[0]; + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = 0; + + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q31_t rhs_value0 = (int8_t)rhs_ptr[0] + rhs_offset; + q31_t lhs_value = (int8_t)lhs_ptr[0] + lhs_offset; + + res00 += lhs_value * rhs_value0; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multiplier, dst_shift); + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + + *dst = (q15_t)res00; + dst += dst_offset; + rhs += rhs_cols; + } +#endif + + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c new file mode 100644 index 00000000..5a8cea2f --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c @@ -0,0 +1,203 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nntables.c + * Description: Converts the elements of the Q7 vector to Q15 vector without left-shift + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @brief tables for various activation functions + * + * This file include the declaration of common tables. + * Most of them are used for activation functions + * + * Assumption: + * Unified table: input is 3.x format, i.e, range of [-8, 8) + * sigmoid(8) = 0.9996646498695336 + * tanh(8) = 0.9999997749296758 + * The accuracy here should be good enough + * + * 2-stage HL table: + * + * The entire input range is divided into two parts: + * + * Low range table: 0x000x xxxx or 0x111x xxxx + * table entry will be the binary number excluding the first + * two digits, i.e., 0x0x xxxx or 0x1x xxxx + * + * + * + * High range table 0x0010 0000 -- 0x0111 1111 + * 0x1000 0000 -- 0x1101 1111 + * + * For positive numbers, table entry will be + * 0x0010 0000 -- 0x0111 1111 minus 0x0010 0000 + * i.e., 0x0000 0000 - 0x0101 11111 + * + * same thing for the negative numbers, table entry will be + * 0x1000 0000 -- 0x1101 1111 minux 0x0010 0000 + * i.e., 0x0110 0000 - 0x1011 1111 + */ + +const q7_t sigmoidTable_q7[256] = { + 0x40, 0x42, 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x4e, 0x50, 0x52, 0x53, 0x55, 0x57, 0x59, 0x5a, 0x5c, 0x5e, 0x5f, 0x61, + 0x62, 0x63, 0x65, 0x66, 0x67, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x72, 0x73, 0x74, 0x74, + 0x75, 0x76, 0x76, 0x77, 0x77, 0x78, 0x78, 0x79, 0x79, 0x7a, 0x7a, 0x7a, 0x7b, 0x7b, 0x7b, 0x7c, 0x7c, 0x7c, 0x7c, + 0x7c, 0x7d, 0x7d, 0x7d, 0x7d, 0x7d, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, 0x02, + 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x04, 0x04, 0x04, 0x04, 0x04, 0x05, 0x05, 0x05, 0x06, 0x06, + 0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x09, 0x0a, 0x0a, 0x0b, 0x0c, 0x0c, 0x0d, 0x0e, 0x0e, 0x0f, 0x10, 0x11, 0x12, + 0x13, 0x14, 0x15, 0x16, 0x17, 0x19, 0x1a, 0x1b, 0x1d, 0x1e, 0x1f, 0x21, 0x22, 0x24, 0x26, 0x27, 0x29, 0x2b, 0x2d, + 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e, +}; + +const q15_t sigmoidTable_q15[256] = { + 0x4000, 0x4200, 0x43ff, 0x45fc, 0x47f5, 0x49eb, 0x4bdc, 0x4dc8, 0x4fad, 0x518a, 0x5360, 0x552c, 0x56ef, 0x58a8, + 0x5a57, 0x5bfb, 0x5d93, 0x5f20, 0x60a1, 0x6216, 0x637f, 0x64db, 0x662b, 0x676f, 0x68a6, 0x69d2, 0x6af1, 0x6c05, + 0x6d0d, 0x6e09, 0x6efb, 0x6fe2, 0x70be, 0x7190, 0x7258, 0x7316, 0x73cc, 0x7478, 0x751b, 0x75b7, 0x764a, 0x76d6, + 0x775b, 0x77d8, 0x784f, 0x78c0, 0x792a, 0x798f, 0x79ee, 0x7a48, 0x7a9d, 0x7aed, 0x7b39, 0x7b80, 0x7bc4, 0x7c03, + 0x7c3f, 0x7c78, 0x7cad, 0x7ce0, 0x7d0f, 0x7d3c, 0x7d66, 0x7d8d, 0x7db3, 0x7dd6, 0x7df7, 0x7e16, 0x7e33, 0x7e4f, + 0x7e69, 0x7e81, 0x7e98, 0x7eae, 0x7ec2, 0x7ed5, 0x7ee7, 0x7ef8, 0x7f08, 0x7f17, 0x7f25, 0x7f32, 0x7f3e, 0x7f4a, + 0x7f55, 0x7f5f, 0x7f69, 0x7f72, 0x7f7b, 0x7f83, 0x7f8a, 0x7f91, 0x7f98, 0x7f9e, 0x7fa4, 0x7faa, 0x7faf, 0x7fb4, + 0x7fb8, 0x7fbd, 0x7fc1, 0x7fc5, 0x7fc8, 0x7fcc, 0x7fcf, 0x7fd2, 0x7fd5, 0x7fd7, 0x7fda, 0x7fdc, 0x7fde, 0x7fe0, + 0x7fe2, 0x7fe4, 0x7fe6, 0x7fe7, 0x7fe9, 0x7fea, 0x7feb, 0x7fed, 0x7fee, 0x7fef, 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3, + 0x7ff4, 0x7ff4, 0x000b, 0x000c, 0x000c, 0x000d, 0x000e, 0x000f, 0x0010, 0x0011, 0x0012, 0x0013, 0x0015, 0x0016, + 0x0017, 0x0019, 0x001a, 0x001c, 0x001e, 0x0020, 0x0022, 0x0024, 0x0026, 0x0029, 0x002b, 0x002e, 0x0031, 0x0034, + 0x0038, 0x003b, 0x003f, 0x0043, 0x0048, 0x004c, 0x0051, 0x0056, 0x005c, 0x0062, 0x0068, 0x006f, 0x0076, 0x007d, + 0x0085, 0x008e, 0x0097, 0x00a1, 0x00ab, 0x00b6, 0x00c2, 0x00ce, 0x00db, 0x00e9, 0x00f8, 0x0108, 0x0119, 0x012b, + 0x013e, 0x0152, 0x0168, 0x017f, 0x0197, 0x01b1, 0x01cd, 0x01ea, 0x0209, 0x022a, 0x024d, 0x0273, 0x029a, 0x02c4, + 0x02f1, 0x0320, 0x0353, 0x0388, 0x03c1, 0x03fd, 0x043c, 0x0480, 0x04c7, 0x0513, 0x0563, 0x05b8, 0x0612, 0x0671, + 0x06d6, 0x0740, 0x07b1, 0x0828, 0x08a5, 0x092a, 0x09b6, 0x0a49, 0x0ae5, 0x0b88, 0x0c34, 0x0cea, 0x0da8, 0x0e70, + 0x0f42, 0x101e, 0x1105, 0x11f7, 0x12f3, 0x13fb, 0x150f, 0x162e, 0x175a, 0x1891, 0x19d5, 0x1b25, 0x1c81, 0x1dea, + 0x1f5f, 0x20e0, 0x226d, 0x2405, 0x25a9, 0x2758, 0x2911, 0x2ad4, 0x2ca0, 0x2e76, 0x3053, 0x3238, 0x3424, 0x3615, + 0x380b, 0x3a04, 0x3c01, 0x3e00, +}; + +const q15_t sigmoidLTable_q15[128] = { + 0x4000, 0x4100, 0x4200, 0x42ff, 0x43ff, 0x44fd, 0x45fc, 0x46f9, 0x47f5, 0x48f1, 0x49eb, 0x4ae5, 0x4bdc, + 0x4cd3, 0x4dc8, 0x4ebb, 0x4fad, 0x509c, 0x518a, 0x5276, 0x5360, 0x5447, 0x552c, 0x560f, 0x56ef, 0x57cd, + 0x58a8, 0x5981, 0x5a57, 0x5b2a, 0x5bfb, 0x5cc9, 0x5d93, 0x5e5b, 0x5f20, 0x5fe2, 0x60a1, 0x615d, 0x6216, + 0x62cc, 0x637f, 0x642e, 0x64db, 0x6584, 0x662b, 0x66ce, 0x676f, 0x680c, 0x68a6, 0x693d, 0x69d2, 0x6a63, + 0x6af1, 0x6b7c, 0x6c05, 0x6c8a, 0x6d0d, 0x6d8d, 0x6e09, 0x6e84, 0x6efb, 0x6f70, 0x6fe2, 0x7051, 0x0f42, + 0x0faf, 0x101e, 0x1090, 0x1105, 0x117c, 0x11f7, 0x1273, 0x12f3, 0x1376, 0x13fb, 0x1484, 0x150f, 0x159d, + 0x162e, 0x16c3, 0x175a, 0x17f4, 0x1891, 0x1932, 0x19d5, 0x1a7c, 0x1b25, 0x1bd2, 0x1c81, 0x1d34, 0x1dea, + 0x1ea3, 0x1f5f, 0x201e, 0x20e0, 0x21a5, 0x226d, 0x2337, 0x2405, 0x24d6, 0x25a9, 0x267f, 0x2758, 0x2833, + 0x2911, 0x29f1, 0x2ad4, 0x2bb9, 0x2ca0, 0x2d8a, 0x2e76, 0x2f64, 0x3053, 0x3145, 0x3238, 0x332d, 0x3424, + 0x351b, 0x3615, 0x370f, 0x380b, 0x3907, 0x3a04, 0x3b03, 0x3c01, 0x3d01, 0x3e00, 0x3f00, +}; + +const q15_t sigmoidHTable_q15[192] = { + 0x70be, 0x7190, 0x7258, 0x7316, 0x73cc, 0x7478, 0x751b, 0x75b7, 0x764a, 0x76d6, 0x775b, 0x77d8, 0x784f, 0x78c0, + 0x792a, 0x798f, 0x79ee, 0x7a48, 0x7a9d, 0x7aed, 0x7b39, 0x7b80, 0x7bc4, 0x7c03, 0x7c3f, 0x7c78, 0x7cad, 0x7ce0, + 0x7d0f, 0x7d3c, 0x7d66, 0x7d8d, 0x7db3, 0x7dd6, 0x7df7, 0x7e16, 0x7e33, 0x7e4f, 0x7e69, 0x7e81, 0x7e98, 0x7eae, + 0x7ec2, 0x7ed5, 0x7ee7, 0x7ef8, 0x7f08, 0x7f17, 0x7f25, 0x7f32, 0x7f3e, 0x7f4a, 0x7f55, 0x7f5f, 0x7f69, 0x7f72, + 0x7f7b, 0x7f83, 0x7f8a, 0x7f91, 0x7f98, 0x7f9e, 0x7fa4, 0x7faa, 0x7faf, 0x7fb4, 0x7fb8, 0x7fbd, 0x7fc1, 0x7fc5, + 0x7fc8, 0x7fcc, 0x7fcf, 0x7fd2, 0x7fd5, 0x7fd7, 0x7fda, 0x7fdc, 0x7fde, 0x7fe0, 0x7fe2, 0x7fe4, 0x7fe6, 0x7fe7, + 0x7fe9, 0x7fea, 0x7feb, 0x7fed, 0x7fee, 0x7fef, 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3, 0x7ff4, 0x7ff4, 0x000b, 0x000c, + 0x000c, 0x000d, 0x000e, 0x000f, 0x0010, 0x0011, 0x0012, 0x0013, 0x0015, 0x0016, 0x0017, 0x0019, 0x001a, 0x001c, + 0x001e, 0x0020, 0x0022, 0x0024, 0x0026, 0x0029, 0x002b, 0x002e, 0x0031, 0x0034, 0x0038, 0x003b, 0x003f, 0x0043, + 0x0048, 0x004c, 0x0051, 0x0056, 0x005c, 0x0062, 0x0068, 0x006f, 0x0076, 0x007d, 0x0085, 0x008e, 0x0097, 0x00a1, + 0x00ab, 0x00b6, 0x00c2, 0x00ce, 0x00db, 0x00e9, 0x00f8, 0x0108, 0x0119, 0x012b, 0x013e, 0x0152, 0x0168, 0x017f, + 0x0197, 0x01b1, 0x01cd, 0x01ea, 0x0209, 0x022a, 0x024d, 0x0273, 0x029a, 0x02c4, 0x02f1, 0x0320, 0x0353, 0x0388, + 0x03c1, 0x03fd, 0x043c, 0x0480, 0x04c7, 0x0513, 0x0563, 0x05b8, 0x0612, 0x0671, 0x06d6, 0x0740, 0x07b1, 0x0828, + 0x08a5, 0x092a, 0x09b6, 0x0a49, 0x0ae5, 0x0b88, 0x0c34, 0x0cea, 0x0da8, 0x0e70, +}; + +const q7_t tanhTable_q7[256] = { + 0x00, 0x08, 0x10, 0x18, 0x1f, 0x27, 0x2e, 0x35, 0x3b, 0x41, 0x47, 0x4c, 0x51, 0x56, 0x5a, 0x5e, 0x61, 0x65, 0x68, + 0x6a, 0x6d, 0x6f, 0x71, 0x72, 0x74, 0x75, 0x76, 0x78, 0x78, 0x79, 0x7a, 0x7b, 0x7b, 0x7c, 0x7c, 0x7d, 0x7d, 0x7e, + 0x7e, 0x7e, 0x7e, 0x7e, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, + 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x82, 0x82, 0x82, 0x82, 0x82, 0x83, 0x83, 0x84, 0x84, 0x85, 0x85, 0x86, 0x87, + 0x88, 0x88, 0x8a, 0x8b, 0x8c, 0x8e, 0x8f, 0x91, 0x93, 0x96, 0x98, 0x9b, 0x9f, 0xa2, 0xa6, 0xaa, 0xaf, 0xb4, 0xb9, + 0xbf, 0xc5, 0xcb, 0xd2, 0xd9, 0xe1, 0xe8, 0xf0, 0xf8, +}; + +const q15_t tanhTable_q15[256] = { + 0x0000, 0x07fd, 0x0feb, 0x17b9, 0x1f59, 0x26bf, 0x2ddf, 0x34ae, 0x3b27, 0x4142, 0x46fd, 0x4c56, 0x514d, 0x55e2, + 0x5a1a, 0x5df6, 0x617c, 0x64b0, 0x6797, 0x6a37, 0x6c95, 0x6eb5, 0x709e, 0x7254, 0x73dc, 0x753a, 0x7672, 0x7788, + 0x787f, 0x795b, 0x7a1e, 0x7acb, 0x7b65, 0x7bee, 0x7c66, 0x7cd1, 0x7d30, 0x7d84, 0x7dce, 0x7e0f, 0x7e49, 0x7e7d, + 0x7eaa, 0x7ed2, 0x7ef5, 0x7f14, 0x7f30, 0x7f48, 0x7f5e, 0x7f71, 0x7f82, 0x7f91, 0x7f9e, 0x7fa9, 0x7fb3, 0x7fbc, + 0x7fc4, 0x7fcb, 0x7fd1, 0x7fd7, 0x7fdc, 0x7fe0, 0x7fe4, 0x7fe7, 0x7fea, 0x7fed, 0x7fef, 0x7ff1, 0x7ff3, 0x7ff4, + 0x7ff6, 0x7ff7, 0x7ff8, 0x7ff9, 0x7ffa, 0x7ffa, 0x7ffb, 0x7ffc, 0x7ffc, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffe, 0x7ffe, + 0x7ffe, 0x7ffe, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, + 0x8001, 0x8001, 0x8001, 0x8002, 0x8002, 0x8002, 0x8002, 0x8003, 0x8003, 0x8003, 0x8004, 0x8004, 0x8005, 0x8006, + 0x8006, 0x8007, 0x8008, 0x8009, 0x800a, 0x800c, 0x800d, 0x800f, 0x8011, 0x8013, 0x8016, 0x8019, 0x801c, 0x8020, + 0x8024, 0x8029, 0x802f, 0x8035, 0x803c, 0x8044, 0x804d, 0x8057, 0x8062, 0x806f, 0x807e, 0x808f, 0x80a2, 0x80b8, + 0x80d0, 0x80ec, 0x810b, 0x812e, 0x8156, 0x8183, 0x81b7, 0x81f1, 0x8232, 0x827c, 0x82d0, 0x832f, 0x839a, 0x8412, + 0x849b, 0x8535, 0x85e2, 0x86a5, 0x8781, 0x8878, 0x898e, 0x8ac6, 0x8c24, 0x8dac, 0x8f62, 0x914b, 0x936b, 0x95c9, + 0x9869, 0x9b50, 0x9e84, 0xa20a, 0xa5e6, 0xaa1e, 0xaeb3, 0xb3aa, 0xb903, 0xbebe, 0xc4d9, 0xcb52, 0xd221, 0xd941, + 0xe0a7, 0xe847, 0xf015, 0xf803, +}; + +const q15_t tanhLTable_q15[128] = { + 0x0000, 0x0400, 0x07fd, 0x0bf7, 0x0feb, 0x13d7, 0x17b9, 0x1b90, 0x1f59, 0x2314, 0x26bf, 0x2a58, 0x2ddf, + 0x3151, 0x34ae, 0x37f6, 0x3b27, 0x3e40, 0x4142, 0x442c, 0x46fd, 0x49b6, 0x4c56, 0x4edd, 0x514d, 0x53a3, + 0x55e2, 0x580a, 0x5a1a, 0x5c13, 0x5df6, 0x5fc4, 0x617c, 0x6320, 0x64b0, 0x662d, 0x6797, 0x68f0, 0x6a37, + 0x6b6e, 0x6c95, 0x6dac, 0x6eb5, 0x6fb0, 0x709e, 0x717f, 0x7254, 0x731e, 0x73dc, 0x7490, 0x753a, 0x75da, + 0x7672, 0x7701, 0x7788, 0x7807, 0x787f, 0x78f0, 0x795b, 0x79bf, 0x7a1e, 0x7a77, 0x7acb, 0x7b1b, 0x849b, + 0x84e5, 0x8535, 0x8589, 0x85e2, 0x8641, 0x86a5, 0x8710, 0x8781, 0x87f9, 0x8878, 0x88ff, 0x898e, 0x8a26, + 0x8ac6, 0x8b70, 0x8c24, 0x8ce2, 0x8dac, 0x8e81, 0x8f62, 0x9050, 0x914b, 0x9254, 0x936b, 0x9492, 0x95c9, + 0x9710, 0x9869, 0x99d3, 0x9b50, 0x9ce0, 0x9e84, 0xa03c, 0xa20a, 0xa3ed, 0xa5e6, 0xa7f6, 0xaa1e, 0xac5d, + 0xaeb3, 0xb123, 0xb3aa, 0xb64a, 0xb903, 0xbbd4, 0xbebe, 0xc1c0, 0xc4d9, 0xc80a, 0xcb52, 0xceaf, 0xd221, + 0xd5a8, 0xd941, 0xdcec, 0xe0a7, 0xe470, 0xe847, 0xec29, 0xf015, 0xf409, 0xf803, 0xfc00, +}; + +const q15_t tanhHTable_q15[192] = { + 0x7b65, 0x7bee, 0x7c66, 0x7cd1, 0x7d30, 0x7d84, 0x7dce, 0x7e0f, 0x7e49, 0x7e7d, 0x7eaa, 0x7ed2, 0x7ef5, 0x7f14, + 0x7f30, 0x7f48, 0x7f5e, 0x7f71, 0x7f82, 0x7f91, 0x7f9e, 0x7fa9, 0x7fb3, 0x7fbc, 0x7fc4, 0x7fcb, 0x7fd1, 0x7fd7, + 0x7fdc, 0x7fe0, 0x7fe4, 0x7fe7, 0x7fea, 0x7fed, 0x7fef, 0x7ff1, 0x7ff3, 0x7ff4, 0x7ff6, 0x7ff7, 0x7ff8, 0x7ff9, + 0x7ffa, 0x7ffa, 0x7ffb, 0x7ffc, 0x7ffc, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8002, + 0x8002, 0x8002, 0x8002, 0x8003, 0x8003, 0x8003, 0x8004, 0x8004, 0x8005, 0x8006, 0x8006, 0x8007, 0x8008, 0x8009, + 0x800a, 0x800c, 0x800d, 0x800f, 0x8011, 0x8013, 0x8016, 0x8019, 0x801c, 0x8020, 0x8024, 0x8029, 0x802f, 0x8035, + 0x803c, 0x8044, 0x804d, 0x8057, 0x8062, 0x806f, 0x807e, 0x808f, 0x80a2, 0x80b8, 0x80d0, 0x80ec, 0x810b, 0x812e, + 0x8156, 0x8183, 0x81b7, 0x81f1, 0x8232, 0x827c, 0x82d0, 0x832f, 0x839a, 0x8412, +}; diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c new file mode 100644 index 00000000..6f2f5753 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_q7_to_q15_no_shift.c + * Description: Converts the elements of the Q7 vector to Q15 vector without left-shift + * + * $Date: May 29, 2020 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/** + * @brief Converts the elements of the Q7 vector to Q15 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * + * \par Description: + * + * The equation used for the conversion process is: + * + *
+ * 	pDst[n] = (q15_t) pSrc[n];   0 <= n < blockSize.
+ * 
+ * + */ + +void arm_q7_to_q15_no_shift(const q7_t *pSrc, q15_t *pDst, uint32_t blockSize) +{ + const q7_t *pIn = pSrc; + uint32_t blkCnt; + +#if defined(ARM_MATH_DSP) + q31_t in; + q31_t in1, in2; + q31_t out1, out2; + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. */ + while (blkCnt > 0u) + { + in = arm_nn_read_q7x4_ia(&pIn); + + /* rotatate in by 8 and extend two q7_t values to q15_t values */ + in1 = __SXTB16(__ROR((uint32_t)in, 8)); + + /* extend remaining two q7_t values to q15_t values */ + in2 = __SXTB16(in); + +#ifndef ARM_MATH_BIG_ENDIAN + out2 = (int32_t)__PKHTB(in1, in2, 16); + out1 = (int32_t)__PKHBT(in2, in1, 16); +#else + out1 = (int32_t)__PKHTB(in1, in2, 16); + out2 = (int32_t)__PKHBT(in2, in1, 16); +#endif + arm_nn_write_q15x2_ia(&pDst, out1); + arm_nn_write_q15x2_ia(&pDst, out2); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Loop over blockSize number of values */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0_FAMILY */ + + while (blkCnt > 0u) + { + /* convert from q7 to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t)*pIn++; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of nndata_convert group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c new file mode 100644 index 00000000..8abbc3a5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_q7_to_q15_reordered_no_shift.c + * Description: Converts the elements of the Q7 vector to reordered Q15 vector without left-shift + * + * $Date: July 20, 2021 + * $Revision: V.1.1.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/** + * @brief Converts the elements of the Q7 vector to reordered Q15 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * + * @details + * + * This function does the q7 to q15 expansion with re-ordering + * + *
+ *                          |   A1   |   A2   |   A3   |   A4   |
+ *
+ *                           0      7 8     15 16    23 24    31
+ * 
+ * + * is converted into: + * + *
+ *  |       A1       |       A3       |   and  |       A2       |       A4       |
+ *
+ *   0             15 16            31          0             15 16            31
+ * 
+ * + * + * This looks strange but is natural considering how sign-extension is done at + * assembly level. + * + * The expansion of other other oprand will follow the same rule so that the end + * results are the same. + * + * The tail (i.e., last (N % 4) elements) will still be in original order. + * + */ + +void arm_q7_to_q15_reordered_no_shift(const q7_t *pSrc, q15_t *pDst, uint32_t blockSize) +{ + const q7_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + q31_t in; + q31_t in1, in2; + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + in = arm_nn_read_q7x4_ia(&pIn); + + /* rotatate in by 8 and extend two q7_t values to q15_t values */ + in1 = __SXTB16(__ROR((uint32_t)in, 8)); + + /* extend remainig two q7_t values to q15_t values */ + in2 = __SXTB16(in); + +#ifndef ARM_MATH_BIG_ENDIAN + arm_nn_write_q7x4_ia((q7_t **)&pDst, in2); + arm_nn_write_q7x4_ia((q7_t **)&pDst, in1); +#else + arm_nn_write_q7x4_ia((q7_t **)&pDst, in1); + arm_nn_write_q7x4_ia((q7_t **)&pDst, in2); +#endif + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Loop over blockSize number of values */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0_FAMILY */ + + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t)*pIn++; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of q7_to_x group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_with_offset.c b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_with_offset.c new file mode 100644 index 00000000..765929d5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_with_offset.c @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_q7_to_q15_reordered_with_offset.c + * Description: Converts the elements of the Q7 vector to a reordered Q15 vector with an added offset. The re-ordering + * is a signature of sign extension intrinsic(DSP extension). + * + * $Date: May 29, 2020 + * $Revision: V.2.0.3 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/** + * @brief Converts the elements of the Q7 vector to a reordered Q15 vector with an added offset. + * + * @note Refer header file for details. + * + */ + +void arm_q7_to_q15_reordered_with_offset(const q7_t *src, q15_t *dst, uint32_t block_size, q15_t offset) +{ + +#if defined(ARM_MATH_DSP) + uint32_t block_cnt; + /* Run the below code for cores that support SIMD instructions */ + q31_t in_q7x4; + q31_t out_q15x2_1; + q31_t out_q15x2_2; + + /*loop unrolling */ + block_cnt = block_size >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. */ + const q31_t offset_q15x2 = (q31_t)__PKHBT(offset, offset, 16); + while (block_cnt > 0u) + { + /* convert from q7 to q15 and then store the results in the destination buffer */ + in_q7x4 = arm_nn_read_q7x4_ia(&src); + + /* Extract and sign extend each of the four q7 values to q15 */ + out_q15x2_1 = __SXTAB16(offset_q15x2, __ROR((uint32_t)in_q7x4, 8)); + out_q15x2_2 = __SXTAB16(offset_q15x2, in_q7x4); + + arm_nn_write_q15x2_ia(&dst, out_q15x2_2); + arm_nn_write_q15x2_ia(&dst, out_q15x2_1); + + block_cnt--; + } + /* Handle left over samples */ + block_cnt = block_size % 0x4u; + + while (block_cnt > 0u) + { + *dst++ = (q15_t)*src++ + offset; + + /* Decrement the loop counter */ + block_cnt--; + } +#else + (void)src; + (void)dst; + (void)block_size; + (void)offset; + /* Not available */ +#endif +} + +/** + * @} end of nndata_convert group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c new file mode 100644 index 00000000..ea29986d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in_q7x4 compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in_q7x4 writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_q7_to_q15_with_offset.c + * Description: Converts the elements of the Q7 vector to Q15 vector with an added offset + * + * $Date: March 3, 2020 + * $Revision: V.2.0.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +void arm_q7_to_q15_with_offset(const q7_t *src, q15_t *dst, uint32_t block_size, q15_t offset) +{ + int block_cnt; + +#if defined(ARM_MATH_MVEI) + + int16x8_t source; + const int16x8_t source_offset = vdupq_n_s16(offset); + block_cnt = block_size / 8; + + while (block_cnt > 0) + { + source = vldrbq_s16(src); + source = vaddq_s16(source, source_offset); + vstrhq_s16(dst, source); + dst += 8; + src += 8; + block_cnt--; + } + + block_cnt = block_size & 0x7; + +#elif defined(ARM_MATH_DSP) + /* Run the below code for cores that support SIMD instructions */ + q31_t in_q7x4; + q31_t in_q15x2_1; + q31_t in_q15x2_2; + q31_t out_q15x2_1; + q31_t out_q15x2_2; + + /*loop unrolling */ + block_cnt = block_size >> 2; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. */ + const q31_t offset_q15x2 = __PKHBT(offset, offset, 16); + while (block_cnt > 0) + { + /* convert from q7 to q15 and then store the results in the destination buffer */ + in_q7x4 = arm_nn_read_q7x4_ia(&src); + + /* Extract and sign extend each of the four q7 values to q15 */ + in_q15x2_1 = __SXTAB16(offset_q15x2, __ROR(in_q7x4, 8)); + in_q15x2_2 = __SXTAB16(offset_q15x2, in_q7x4); + + out_q15x2_2 = __PKHTB(in_q15x2_1, in_q15x2_2, 16); + out_q15x2_1 = __PKHBT(in_q15x2_2, in_q15x2_1, 16); + + arm_nn_write_q15x2_ia(&dst, out_q15x2_1); + arm_nn_write_q15x2_ia(&dst, out_q15x2_2); + + block_cnt--; + } + /* Handle left over samples */ + block_cnt = block_size % 0x4; + +#else + /* Run the below code for Cortex-M0 */ + /* Loop over block_size number of values */ + block_cnt = block_size; +#endif + + while (block_cnt > 0) + { + *dst++ = (q15_t)*src++ + offset; + + /* Decrement the loop counter */ + block_cnt--; + } +} + +/** + * @} end of nndata_convert group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/PoolingFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/NN/Source/PoolingFunctions/CMakeLists.txt new file mode 100644 index 00000000..a37503b6 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/PoolingFunctions/CMakeLists.txt @@ -0,0 +1,24 @@ +# +# Copyright (c) 2019-2022 Arm Limited. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +file(GLOB SRC "./*_s8.c") +file(GLOB SRC_S16 "./*_s16.c") +target_sources(cmsis-nn PRIVATE ${SRC} ${SRC_S16}) + + + diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_avgpool_s16.c b/benchmark/interface/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_avgpool_s16.c new file mode 100644 index 00000000..5cd2b1ce --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_avgpool_s16.c @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_avgpool_s16.c + * Description: Pooling function implementations + * + * $Date: 3. February 2022 + * $Revision: V.1.0.1 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + +/* + * s16 average pooling function + * + * Refer to header file for details. + * + */ +arm_status arm_avgpool_s16(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const q15_t *src, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + q15_t *dst) +{ + (void)ctx; + const int32_t input_y = input_dims->h; + const int32_t input_x = input_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_x = output_dims->w; + const int32_t stride_y = pool_params->stride.h; + const int32_t stride_x = pool_params->stride.w; + const int32_t kernel_y = filter_dims->h; + const int32_t kernel_x = filter_dims->w; + const int32_t pad_y = pool_params->padding.h; + const int32_t pad_x = pool_params->padding.w; + const int32_t act_min = pool_params->activation.min; + const int32_t act_max = pool_params->activation.max; + const int32_t ch_src = input_dims->c; + + /* Reference C code adapted from CMSIS-NN arm_avgpool_s8.c. + */ + + for (int i_y = 0, base_idx_y = -pad_y; i_y < output_y; base_idx_y += stride_y, i_y++) + { + for (int i_x = 0, base_idx_x = -pad_x; i_x < output_x; base_idx_x += stride_x, i_x++) + { + /* Condition for kernel start dimension: (base_idx_ + kernel__start) >= 0 */ + const int32_t ker_y_start = MAX(0, -base_idx_y); + const int32_t ker_x_start = MAX(0, -base_idx_x); + + /* Condition for kernel end dimension: (base_idx_ + kernel__end) < dim_src_ */ + const int32_t kernel_y_end = MIN(kernel_y, input_y - base_idx_y); + const int32_t kernel_x_end = MIN(kernel_x, input_x - base_idx_x); + + for (int i_ch_in = 0; i_ch_in < ch_src; i_ch_in++) + { + int sum = 0; + int count = 0; + + for (int k_y = ker_y_start; k_y < kernel_y_end; k_y++) + { + for (int k_x = ker_x_start; k_x < kernel_x_end; k_x++) + { + sum += src[i_ch_in + ch_src * (k_x + base_idx_x + (k_y + base_idx_y) * input_x)]; + count++; + } + } + + // Prevent static code issue DIVIDE_BY_ZERO. + if (count == 0) + { + return ARM_MATH_ARGUMENT_ERROR; + } + + sum = sum > 0 ? (sum + count / 2) / count : (sum - count / 2) / count; + sum = MAX(sum, act_min); + sum = MIN(sum, act_max); + + dst[i_ch_in + ch_src * (i_x + i_y * output_x)] = sum; + } + } + } + + return ARM_MATH_SUCCESS; +} + +int32_t arm_avgpool_s16_get_buffer_size(const int output_x, const int ch_src) +{ + (void)output_x; + (void)ch_src; + return 0; +} + +/** + * @} end of Pooling group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_avgpool_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_avgpool_s8.c new file mode 100644 index 00000000..3e9861ec --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_avgpool_s8.c @@ -0,0 +1,401 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_avgpool_s8.c + * Description: Pooling function implementations + * + * $Date: 01. March 2021 + * $Revision: V.2.0.4 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + +static void scale_q31_to_q7_and_clamp(const q31_t *buffer, + q7_t *target, + int32_t length, + const int32_t count, + const int act_min, + const int act_max) +{ + const int half_count = count / 2; + + // Prevent static code issue DIVIDE_BY_ZERO. + if (count == 0) + { + return; + } + + for (int i = 0; i < length; i++) + { + int32_t sum = buffer[i] > 0 ? (buffer[i] + half_count) : (buffer[i] - half_count); + sum = sum / count; + sum = MAX(sum, act_min); + sum = MIN(sum, act_max); + + target[i] = (q7_t)sum; + } +} +#endif + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + +/* + * s8 average pooling function + * + * Refer to header file for details. + * + */ + +#if defined(ARM_MATH_MVEI) + +arm_status arm_avgpool_s8(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const q7_t *src, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + q7_t *dst) +{ + (void)ctx; + const int32_t input_y = input_dims->h; + const int32_t input_x = input_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_x = output_dims->w; + const int32_t stride_y = pool_params->stride.h; + const int32_t stride_x = pool_params->stride.w; + const int32_t kernel_y = filter_dims->h; + const int32_t kernel_x = filter_dims->w; + const int32_t pad_y = pool_params->padding.h; + const int32_t pad_x = pool_params->padding.w; + const int32_t act_min = pool_params->activation.min; + const int32_t act_max = pool_params->activation.max; + const int32_t ch_src = input_dims->c; + + int32_t i_x, i_y; + int32_t k_x, k_y; + + for (i_y = 0; i_y < output_y; i_y++) + { + for (i_x = 0; i_x < output_x; i_x++) + { + + int32_t k_y_start, k_y_end; + int32_t k_x_start, k_x_end; + int32_t chCnt; + const int8_t *pTmp, *pTmpInner; + int8_t *pDst; + + k_y_start = MAX(0, i_y * stride_y - pad_y); + k_y_end = MIN(i_y * stride_y - pad_y + kernel_y, input_y); + + k_x_start = MAX(0, i_x * stride_x - pad_x); + k_x_end = MIN(i_x * stride_x - pad_x + kernel_x, input_x); + + pTmp = src; + pDst = &dst[ch_src * (i_x + i_y * output_x)]; + + chCnt = ch_src >> 4; + while (chCnt > 0) + { + int32x4_t sumV1, sumV2, sumV3, sumV4; + + int8x16_t tempV; + int16x8_t tempVLO, tempVHI; + int32x4_t tempVLOLO, tempVLOHI, tempVHILO, tempVHIHI; + int32_t count = 0; + + sumV1 = vdupq_n_s32(0); + sumV2 = vdupq_n_s32(0); + sumV3 = vdupq_n_s32(0); + sumV4 = vdupq_n_s32(0); + + for (k_y = k_y_start; k_y < k_y_end; k_y++) + { + for (k_x = k_x_start; k_x < k_x_end; k_x++) + { + pTmpInner = pTmp + (ch_src * (k_x + k_y * input_x)); + tempV = vldrbq_s8(pTmpInner); + + tempVLO = vmovlbq_s8(tempV); + tempVHI = vmovltq_s8(tempV); + + tempVLOLO = vmovlbq_s16(tempVLO); + tempVLOHI = vmovltq_s16(tempVLO); + + tempVHILO = vmovlbq_s16(tempVHI); + tempVHIHI = vmovltq_s16(tempVHI); + + sumV1 = vaddq_s32(sumV1, tempVLOLO); + sumV2 = vaddq_s32(sumV2, tempVLOHI); + sumV3 = vaddq_s32(sumV3, tempVHILO); + sumV4 = vaddq_s32(sumV4, tempVHIHI); + + count++; + } + } + + // Prevent static code issue DIVIDE_BY_ZERO. + if (count == 0) + { + return ARM_MATH_ARGUMENT_ERROR; + } + + sumV1[0] = sumV1[0] > 0 ? (sumV1[0] + count / 2) / count : (sumV1[0] - count / 2) / count; + sumV1[1] = sumV1[1] > 0 ? (sumV1[1] + count / 2) / count : (sumV1[1] - count / 2) / count; + sumV1[2] = sumV1[2] > 0 ? (sumV1[2] + count / 2) / count : (sumV1[2] - count / 2) / count; + sumV1[3] = sumV1[3] > 0 ? (sumV1[3] + count / 2) / count : (sumV1[3] - count / 2) / count; + + sumV2[0] = sumV2[0] > 0 ? (sumV2[0] + count / 2) / count : (sumV2[0] - count / 2) / count; + sumV2[1] = sumV2[1] > 0 ? (sumV2[1] + count / 2) / count : (sumV2[1] - count / 2) / count; + sumV2[2] = sumV2[2] > 0 ? (sumV2[2] + count / 2) / count : (sumV2[2] - count / 2) / count; + sumV2[3] = sumV2[3] > 0 ? (sumV2[3] + count / 2) / count : (sumV2[3] - count / 2) / count; + + sumV3[0] = sumV3[0] > 0 ? (sumV3[0] + count / 2) / count : (sumV3[0] - count / 2) / count; + sumV3[1] = sumV3[1] > 0 ? (sumV3[1] + count / 2) / count : (sumV3[1] - count / 2) / count; + sumV3[2] = sumV3[2] > 0 ? (sumV3[2] + count / 2) / count : (sumV3[2] - count / 2) / count; + sumV3[3] = sumV3[3] > 0 ? (sumV3[3] + count / 2) / count : (sumV3[3] - count / 2) / count; + + sumV4[0] = sumV4[0] > 0 ? (sumV4[0] + count / 2) / count : (sumV4[0] - count / 2) / count; + sumV4[1] = sumV4[1] > 0 ? (sumV4[1] + count / 2) / count : (sumV4[1] - count / 2) / count; + sumV4[2] = sumV4[2] > 0 ? (sumV4[2] + count / 2) / count : (sumV4[2] - count / 2) / count; + sumV4[3] = sumV4[3] > 0 ? (sumV4[3] + count / 2) / count : (sumV4[3] - count / 2) / count; + + sumV1 = vmaxq_s32(sumV1, vdupq_n_s32(act_min)); + sumV1 = vminq_s32(sumV1, vdupq_n_s32(act_max)); + + sumV2 = vmaxq_s32(sumV2, vdupq_n_s32(act_min)); + sumV2 = vminq_s32(sumV2, vdupq_n_s32(act_max)); + + sumV3 = vmaxq_s32(sumV3, vdupq_n_s32(act_min)); + sumV3 = vminq_s32(sumV3, vdupq_n_s32(act_max)); + + sumV4 = vmaxq_s32(sumV4, vdupq_n_s32(act_min)); + sumV4 = vminq_s32(sumV4, vdupq_n_s32(act_max)); + + tempVLO = vmovnbq_s32(tempVLO, sumV1); + tempVLO = vmovntq_s32(tempVLO, sumV2); + + tempVHI = vmovnbq_s32(tempVHI, sumV3); + tempVHI = vmovntq_s32(tempVHI, sumV4); + + tempV = vmovnbq_s16(tempV, tempVLO); + tempV = vmovntq_s16(tempV, tempVHI); + + vstrbq_s8(pDst, tempV); + pDst += 16; + + chCnt--; + pTmp += 16; + } + + chCnt = ch_src & 0xF; + while (chCnt > 0) + { + int32_t sum = 0; + int32_t count = 0; + + for (k_y = k_y_start; k_y < k_y_end; k_y++) + { + for (k_x = k_x_start; k_x < k_x_end; k_x++) + { + sum += pTmp[ch_src * (k_x + k_y * input_x)]; + count++; + } + } + + // Prevent static code issue DIVIDE_BY_ZERO. + if (count == 0) + { + return ARM_MATH_ARGUMENT_ERROR; + } + + sum = sum > 0 ? (sum + count / 2) / count : (sum - count / 2) / count; + sum = MAX(sum, act_min); + sum = MIN(sum, act_max); + + *pDst++ = sum; + + chCnt--; + pTmp++; + } + } + } + return ARM_MATH_SUCCESS; +} + +#else +arm_status arm_avgpool_s8(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const q7_t *src, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + q7_t *dst) +{ + const int32_t input_y = input_dims->h; + const int32_t input_x = input_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_x = output_dims->w; + const int32_t stride_y = pool_params->stride.h; + const int32_t stride_x = pool_params->stride.w; + const int32_t kernel_y = filter_dims->h; + const int32_t kernel_x = filter_dims->w; + const int32_t pad_y = pool_params->padding.h; + const int32_t pad_x = pool_params->padding.w; + const int32_t act_min = pool_params->activation.min; + const int32_t act_max = pool_params->activation.max; + const int32_t ch_src = input_dims->c; + + if (ctx->buf == NULL && arm_avgpool_s8_get_buffer_size(output_dims->w, input_dims->c)) + { + return ARM_MATH_ARGUMENT_ERROR; + } + q31_t *buffer = (q31_t *)ctx->buf; + +#if defined(ARM_MATH_DSP) + + /* Run the following code for CPU's with DSP extension + */ + for (int i_y = 0, idx_y = -pad_y; i_y < output_y; idx_y += stride_y, i_y++) + { + for (int i_x = 0, idx_x = -pad_x; i_x < output_x; idx_x += stride_x, i_x++) + { + /* Condition for kernel start dimension: + (base_idx_ + kernel__start) >= 0 */ + const int32_t kernel_y_start = MAX(0, -idx_y); + const int32_t kernel_x_start = MAX(0, -idx_x); + + /* Condition for kernel end dimension: + (base_idx_ + kernel__end) < dim_src_ */ + const int32_t kernel_y_end = MIN(kernel_y, input_y - idx_y); + const int32_t kernel_x_end = MIN(kernel_x, input_x - idx_x); + + int count = 0; + + for (int k_y = kernel_y_start; k_y < kernel_y_end; k_y++) + { + for (int k_x = kernel_x_start; k_x < kernel_x_end; k_x++) + { + const q7_t *start = src + ch_src * (k_x + idx_x + (k_y + idx_y) * input_x); + + if (count == 0) + { + for (int i = 0; i < ch_src; i++) + { + buffer[i] = start[i]; + } + } + else + { + for (int i = 0; i < ch_src; i++) + { + buffer[i] = __QADD(start[i], buffer[i]); + } + } + count++; + } + } + + // Prevent static code issue DIVIDE_BY_ZERO. + if (count == 0) + { + return ARM_MATH_ARGUMENT_ERROR; + } + + scale_q31_to_q7_and_clamp(buffer, dst, ch_src, count, act_min, act_max); + dst += ch_src; + } + } +#else + + /* Reference C code adapted from CMSIS-NN arm_avepool_q7_HWC. + */ + (void)buffer; + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_y = 0; i_y < output_y; i_y++) + { + for (i_x = 0; i_x < output_x; i_x++) + { + for (i_ch_in = 0; i_ch_in < ch_src; i_ch_in++) + { + int sum = 0; + int count = 0; + for (k_y = i_y * stride_y - pad_y; k_y < i_y * stride_y - pad_y + kernel_y; k_y++) + { + for (k_x = i_x * stride_x - pad_x; k_x < i_x * stride_x - pad_x + kernel_x; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < input_y && k_x < input_x) + { + sum += src[i_ch_in + ch_src * (k_x + k_y * input_x)]; + count++; + } + } + } + + // Prevent static code issue DIVIDE_BY_ZERO. + if (count == 0) + { + return ARM_MATH_ARGUMENT_ERROR; + } + + sum = sum > 0 ? (sum + count / 2) / count : (sum - count / 2) / count; + sum = MAX(sum, act_min); + sum = MIN(sum, act_max); + + dst[i_ch_in + ch_src * (i_x + i_y * output_x)] = sum; + } + } + } + +#endif + return ARM_MATH_SUCCESS; +} + +#endif /* ARM_MATH_MVEI */ + +int32_t arm_avgpool_s8_get_buffer_size(const int output_x, const int ch_src) +{ + (void)output_x; + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + return (ch_src * sizeof(int32_t)); +#else + (void)ch_src; + return 0; +#endif +} +/** + * @} end of Pooling group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_max_pool_s16.c b/benchmark/interface/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_max_pool_s16.c new file mode 100644 index 00000000..483f8742 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_max_pool_s16.c @@ -0,0 +1,180 @@ +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_max_pool_s16.c + * Description: Pooling function implementations + * + * $Date: 24. January 2022 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +static void compare_and_replace_if_larger(int16_t *base, const int16_t *target, int32_t length) +{ + q15_t *dst = base; + const q15_t *src = target; + union arm_nnword ref_max; + union arm_nnword comp_max; + int32_t cnt = length >> 1; + + while (cnt > 0l) + { + ref_max.word = arm_nn_read_q15x2(dst); + comp_max.word = arm_nn_read_q15x2_ia(&src); + + if (comp_max.half_words[0] > ref_max.half_words[0]) + { + ref_max.half_words[0] = comp_max.half_words[0]; + } + if (comp_max.half_words[1] > ref_max.half_words[1]) + { + ref_max.half_words[1] = comp_max.half_words[1]; + } + + arm_nn_write_q15x2_ia(&dst, ref_max.word); + + cnt--; + } + + if (length & 0x1) + { + if (*src > *dst) + { + *dst = *src; + } + } +} + +static void clamp_output(int16_t *source, int32_t length, const int16_t act_min, const int16_t act_max) +{ + union arm_nnword in; + int32_t cnt = length >> 1; + + while (cnt > 0l) + { + in.word = arm_nn_read_q15x2(source); + + in.half_words[0] = MAX(in.half_words[0], act_min); + in.half_words[0] = MIN(in.half_words[0], act_max); + in.half_words[1] = MAX(in.half_words[1], act_min); + in.half_words[1] = MIN(in.half_words[1], act_max); + + arm_nn_write_q15x2_ia(&source, in.word); + cnt--; + } + + if (length & 0x1) + { + int16_t comp = *source; + comp = MAX(comp, act_min); + comp = MIN(comp, act_max); + *source = comp; + } +} + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + +/* + * Optimized s16 max pooling function + * + * Refer to header file for details. + * + */ + +arm_status arm_max_pool_s16(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const int16_t *src, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + int16_t *dst) +{ + const int32_t input_y = input_dims->h; + const int32_t input_x = input_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_x = output_dims->w; + const int32_t stride_y = pool_params->stride.h; + const int32_t stride_x = pool_params->stride.w; + const int32_t kernel_y = filter_dims->h; + const int32_t kernel_x = filter_dims->w; + const int32_t pad_y = pool_params->padding.h; + const int32_t pad_x = pool_params->padding.w; + const int16_t act_min = pool_params->activation.min; + const int16_t act_max = pool_params->activation.max; + const int32_t channel_in = input_dims->c; + (void)ctx; + int16_t *dst_base = dst; + + for (int i_y = 0, base_idx_y = -pad_y; i_y < output_y; base_idx_y += stride_y, i_y++) + { + for (int i_x = 0, base_idx_x = -pad_x; i_x < output_x; base_idx_x += stride_x, i_x++) + { + /* Condition for kernel start dimension: (base_idx_ + kernel__start) >= 0 */ + const int32_t ker_y_start = MAX(0, -base_idx_y); + const int32_t ker_x_start = MAX(0, -base_idx_x); + + /* Condition for kernel end dimension: (base_idx_ + kernel__end) < dim_src_ */ + const int32_t kernel_y_end = MIN(kernel_y, input_y - base_idx_y); + const int32_t kernel_x_end = MIN(kernel_x, input_x - base_idx_x); + + int count = 0; + + for (int k_y = ker_y_start; k_y < kernel_y_end; k_y++) + { + for (int k_x = ker_x_start; k_x < kernel_x_end; k_x++) + { + const int16_t *start = src + channel_in * (k_x + base_idx_x + (k_y + base_idx_y) * input_x); + + if (count == 0) + { + memcpy(dst, start, channel_in * sizeof(int16_t)); + count++; + } + else + { + compare_and_replace_if_larger(dst, start, channel_in); + } + } + } + /* 'count' is expected to be non-zero here. */ + dst += channel_in; + } + } + + clamp_output(dst_base, output_x * output_y * channel_in, act_min, act_max); + + return ARM_MATH_SUCCESS; +} + +/** + * @} end of Pooling group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_max_pool_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_max_pool_s8.c new file mode 100644 index 00000000..4fbbc915 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_max_pool_s8.c @@ -0,0 +1,229 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_max_pool_s8.c + * Description: Pooling function implementations + * + * $Date: 20. July 2021 + * $Revision: V.2.0.3 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +static void compare_and_replace_if_larger_q7(q7_t *base, const q7_t *target, int32_t length) +{ +#if defined(ARM_MATH_MVEI) + int32_t loop_count = (length + 15) / 16; + for (int i = 0; i < loop_count; i++) + { + mve_pred16_t p = vctp8q((uint32_t)length); + const int8x16_t op_1 = vldrbq_z_s8(base, p); + const int8x16_t op_2 = vldrbq_z_s8(target, p); + const int8x16_t max = vmaxq_m_s8(vuninitializedq_s8(), op_1, op_2, p); + vstrbq_p_s8(base, max, p); + base += 16; + target += 16; + length -= 16; + } +#else + q7_t *dst = base; + const q7_t *src = target; + union arm_nnword ref_max; + union arm_nnword comp_max; + int32_t cnt = length >> 2; + + while (cnt > 0l) + { + ref_max.word = arm_nn_read_q7x4(dst); + comp_max.word = arm_nn_read_q7x4_ia(&src); + + if (comp_max.bytes[0] > ref_max.bytes[0]) + { + ref_max.bytes[0] = comp_max.bytes[0]; + } + if (comp_max.bytes[1] > ref_max.bytes[1]) + { + ref_max.bytes[1] = comp_max.bytes[1]; + } + if (comp_max.bytes[2] > ref_max.bytes[2]) + { + ref_max.bytes[2] = comp_max.bytes[2]; + } + if (comp_max.bytes[3] > ref_max.bytes[3]) + { + ref_max.bytes[3] = comp_max.bytes[3]; + } + + arm_nn_write_q7x4_ia(&dst, ref_max.word); + + cnt--; + } + + cnt = length & 0x3; + while (cnt > 0l) + { + if (*src > *dst) + { + *dst = *src; + } + dst++; + src++; + cnt--; + } +#endif +} + +static void clamp_output(q7_t *source, int32_t length, const int32_t act_min, const int32_t act_max) +{ +#if defined(ARM_MATH_MVEI) + int32_t loop_count = (length + 15) / 16; + for (int i = 0; i < loop_count; i++) + { + mve_pred16_t p = vctp8q((uint32_t)length); + length -= 16; + const int8x16_t src = vldrbq_z_s8(source, p); + const int8x16_t predicated_min = vdupq_m_n_s8(vuninitializedq_s8(), (int8_t)act_min, p); + const int8x16_t predicated_max = vdupq_m_n_s8(vuninitializedq_s8(), (int8_t)act_max, p); + int8x16_t res = vmaxq_m_s8(vuninitializedq_s8(), src, predicated_min, p); + res = vminq_m_s8(vuninitializedq_s8(), res, predicated_max, p); + vstrbq_p_s8(source, res, p); + source += 16; + } +#else + union arm_nnword in; + int32_t cnt = length >> 2; + + while (cnt > 0l) + { + in.word = arm_nn_read_q7x4(source); + + in.bytes[0] = MAX(in.bytes[0], act_min); + in.bytes[0] = MIN(in.bytes[0], act_max); + in.bytes[1] = MAX(in.bytes[1], act_min); + in.bytes[1] = MIN(in.bytes[1], act_max); + in.bytes[2] = MAX(in.bytes[2], act_min); + in.bytes[2] = MIN(in.bytes[2], act_max); + in.bytes[3] = MAX(in.bytes[3], act_min); + in.bytes[3] = MIN(in.bytes[3], act_max); + + arm_nn_write_q7x4_ia(&source, in.word); + cnt--; + } + + cnt = length & 0x3; + while (cnt > 0l) + { + int32_t comp = *source; + comp = MAX(comp, act_min); + comp = MIN(comp, act_max); + *source++ = (int8_t)comp; + cnt--; + } +#endif +} + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + +/* + * Optimized s8 max pooling function + * + * Refer to header file for details. + * + */ + +arm_status arm_max_pool_s8(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const q7_t *src, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + q7_t *dst) +{ + const int32_t input_y = input_dims->h; + const int32_t input_x = input_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_x = output_dims->w; + const int32_t stride_y = pool_params->stride.h; + const int32_t stride_x = pool_params->stride.w; + const int32_t kernel_y = filter_dims->h; + const int32_t kernel_x = filter_dims->w; + const int32_t pad_y = pool_params->padding.h; + const int32_t pad_x = pool_params->padding.w; + const int32_t act_min = pool_params->activation.min; + const int32_t act_max = pool_params->activation.max; + const int32_t channel_in = input_dims->c; + (void)ctx; + q7_t *dst_base = dst; + + for (int i_y = 0, base_idx_y = -pad_y; i_y < output_y; base_idx_y += stride_y, i_y++) + { + for (int i_x = 0, base_idx_x = -pad_x; i_x < output_x; base_idx_x += stride_x, i_x++) + { + /* Condition for kernel start dimension: (base_idx_ + kernel__start) >= 0 */ + const int32_t ker_y_start = MAX(0, -base_idx_y); + const int32_t ker_x_start = MAX(0, -base_idx_x); + + /* Condition for kernel end dimension: (base_idx_ + kernel__end) < dim_src_ */ + const int32_t kernel_y_end = MIN(kernel_y, input_y - base_idx_y); + const int32_t kernel_x_end = MIN(kernel_x, input_x - base_idx_x); + + int count = 0; + + for (int k_y = ker_y_start; k_y < kernel_y_end; k_y++) + { + for (int k_x = ker_x_start; k_x < kernel_x_end; k_x++) + { + const q7_t *start = src + channel_in * (k_x + base_idx_x + (k_y + base_idx_y) * input_x); + + if (count == 0) + { + arm_memcpy_q7(dst, start, channel_in); + count++; + } + else + { + compare_and_replace_if_larger_q7(dst, start, channel_in); + } + } + } + /* 'count' is expected to be non-zero here. */ + dst += channel_in; + } + } + + clamp_output(dst_base, output_x * output_y * channel_in, act_min, act_max); + + return ARM_MATH_SUCCESS; +} + +/** + * @} end of Pooling group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c b/benchmark/interface/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c new file mode 100644 index 00000000..5a3b1afd --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c @@ -0,0 +1,464 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_pool_q7_HWC.c + * Description: Pooling function implementations + * + * $Date: 20. July 2021 + * $Revision: V.1.1.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + +/** + * @brief A few utility functions used by pooling functions + * + * + */ + +static void buffer_scale_back_q15_to_q7(q15_t *buffer, q7_t *target, uint16_t length, uint16_t scale) +{ + int i; + + for (i = 0; i < length; i++) + { + target[i] = (q7_t)(buffer[i] / scale); + } +} + +static void compare_and_replace_if_larger_q7(q7_t *base, // base data + const q7_t *target, // compare target + const uint16_t length // data length +) +{ + q7_t *pIn = base; + const q7_t *pCom = target; + union arm_nnword in; + union arm_nnword com; + uint16_t cnt = length >> 2; + + while (cnt > 0u) + { + in.word = arm_nn_read_q7x4((const q7_t *)pIn); + com.word = arm_nn_read_q7x4_ia((const q7_t **)&pCom); + + // if version + if (com.bytes[0] > in.bytes[0]) + in.bytes[0] = com.bytes[0]; + if (com.bytes[1] > in.bytes[1]) + in.bytes[1] = com.bytes[1]; + if (com.bytes[2] > in.bytes[2]) + in.bytes[2] = com.bytes[2]; + if (com.bytes[3] > in.bytes[3]) + in.bytes[3] = com.bytes[3]; + + arm_nn_write_q7x4_ia(&pIn, in.word); + + cnt--; + } + + cnt = length & 0x3; + while (cnt > 0u) + { + if (*pCom > *pIn) + { + *pIn = *pCom; + } + pIn++; + pCom++; + cnt--; + } +} + +static void accumulate_q7_to_q15(q15_t *base, q7_t *target, const uint16_t length) +{ + q15_t *pCnt = base; + q7_t *pV = target; + q31_t v1, v2, vo1, vo2; + uint16_t cnt = length >> 2; + q31_t in; + + while (cnt > 0u) + { + q31_t value = arm_nn_read_q7x4_ia((const q7_t **)&pV); + v1 = __SXTB16(__ROR(value, 8)); + v2 = __SXTB16(value); +#ifndef ARM_MATH_BIG_ENDIAN + + vo2 = __PKHTB(v1, v2, 16); + vo1 = __PKHBT(v2, v1, 16); + +#else + + vo1 = __PKHTB(v1, v2, 16); + vo2 = __PKHBT(v2, v1, 16); + +#endif + + in = arm_nn_read_q15x2(pCnt); + arm_nn_write_q15x2_ia(&pCnt, __QADD16(vo1, in)); + + in = arm_nn_read_q15x2(pCnt); + arm_nn_write_q15x2_ia(&pCnt, __QADD16(vo2, in)); + + cnt--; + } + cnt = length & 0x3; + while (cnt > 0u) + { + *pCnt++ += *pV++; + cnt--; + } +} + +#endif // ARM_MATH_DSP + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + +/** + * @brief Q7 max pooling function + * @param[in, out] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA Not used + * @param[in,out] Im_out pointer to output tensor + * + * @details + * + * The pooling function is implemented as split x-pooling then + * y-pooling. + * + * This pooling function is input-destructive. Input data is undefined + * after calling this function. + * + */ + +void arm_maxpool_q7_HWC(q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const uint16_t dim_im_out, + q7_t *bufferA, + q7_t *Im_out) +{ + (void)bufferA; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_x, i_y; + + /* first does the pooling along x axis */ + for (i_y = 0; i_y < dim_im_in; i_y++) + { + + for (i_x = 0; i_x < dim_im_out; i_x++) + { + /* for each output pixel */ + q7_t *target = Im_in + (i_y * dim_im_in + i_x) * ch_im_in; + q7_t *win_start; + q7_t *win_stop; + if (i_x * stride - padding < 0) + { + win_start = target; + } + else + { + win_start = Im_in + (i_y * dim_im_in + i_x * stride - padding) * ch_im_in; + } + + if (i_x * stride - padding + dim_kernel >= dim_im_in) + { + win_stop = Im_in + (i_y * dim_im_in + dim_im_in) * ch_im_in; + } + else + { + win_stop = Im_in + (i_y * dim_im_in + i_x * stride - padding + dim_kernel) * ch_im_in; + } + + /* first step is to copy over initial data */ + /* arm_copy_q7(win_start, target, ch_im_in); */ + memmove(target, win_start, ch_im_in); + + /* start the max operation from the second part */ + win_start += ch_im_in; + for (; win_start < win_stop; win_start += ch_im_in) + { + compare_and_replace_if_larger_q7(target, win_start, ch_im_in); + } + } + } + + /* then does the pooling along y axis */ + for (i_y = 0; i_y < dim_im_out; i_y++) + { + + /* for each output row */ + q7_t *target = Im_out + i_y * dim_im_out * ch_im_in; + q7_t *row_start; + q7_t *row_end; + /* setting the starting row */ + if (i_y * stride - padding < 0) + { + row_start = Im_in; + } + else + { + row_start = Im_in + (i_y * stride - padding) * dim_im_in * ch_im_in; + } + /* setting the stopping row */ + if (i_y * stride - padding + dim_kernel >= dim_im_in) + { + row_end = Im_in + dim_im_in * dim_im_in * ch_im_in; + } + else + { + row_end = Im_in + (i_y * stride - padding + dim_kernel) * dim_im_in * ch_im_in; + } + + /* copy over the first row */ + /* arm_copy_q7(row_start, target, dim_im_out * ch_im_in); */ + memmove(target, row_start, dim_im_out * ch_im_in); + + /* move over to next row */ + row_start += ch_im_in * dim_im_in; + + for (; row_start < row_end; row_start += dim_im_in * ch_im_in) + { + compare_and_replace_if_larger_q7(target, row_start, dim_im_out * ch_im_in); + } + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out; i_y++) + { + for (i_x = 0; i_x < dim_im_out; i_x++) + { + int max = -129; + for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) + { + for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) + { + if (Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)] > max) + { + max = Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; + } + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = max; + } + } + } + +#endif /* ARM_MATH_DSP */ +} + +/** + * @brief Q7 average pooling function + * @param[in,out] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * + * @details + * + * Buffer size: + * + * bufferA size: 2*dim_im_out*ch_im_in + * + * The pooling function is implemented as split x-pooling then + * y-pooling. + * + * This pooling function is input-destructive. Input data is undefined + * after calling this function. + * + */ + +void arm_avepool_q7_HWC(q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const uint16_t dim_im_out, + q7_t *bufferA, + q7_t *Im_out) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + q15_t *buffer = (q15_t *)bufferA; + int16_t i_x, i_y; + int16_t count = 0; + + /* first does the pooling along x axis */ + for (i_y = 0; i_y < dim_im_in; i_y++) + { + + for (i_x = 0; i_x < dim_im_out; i_x++) + { + /* for each output pixel */ + q7_t *target = Im_in + (i_y * dim_im_in + i_x) * ch_im_in; + q7_t *win_start; + q7_t *win_stop; + if (i_x * stride - padding < 0) + { + win_start = target; + } + else + { + win_start = Im_in + (i_y * dim_im_in + i_x * stride - padding) * ch_im_in; + } + + if (i_x * stride - padding + dim_kernel >= dim_im_in) + { + win_stop = Im_in + (i_y * dim_im_in + dim_im_in) * ch_im_in; + } + else + { + win_stop = Im_in + (i_y * dim_im_in + i_x * stride - padding + dim_kernel) * ch_im_in; + } + + /* first step is to copy over initial data */ + arm_q7_to_q15_no_shift(win_start, buffer, ch_im_in); + count = 1; + + /* start the max operation from the second part */ + win_start += ch_im_in; + for (; win_start < win_stop; win_start += ch_im_in) + { + accumulate_q7_to_q15(buffer, win_start, ch_im_in); + count++; + } + buffer_scale_back_q15_to_q7(buffer, target, ch_im_in, count); + } + } + + /* then does the pooling along y axis */ + for (i_y = 0; i_y < dim_im_out; i_y++) + { + /* for each output row */ + q7_t *target = Im_out + i_y * dim_im_out * ch_im_in; + q7_t *row_start; + q7_t *row_end; + /* setting the starting row */ + if (i_y * stride - padding < 0) + { + row_start = Im_in; + } + else + { + row_start = Im_in + (i_y * stride - padding) * dim_im_in * ch_im_in; + } + /* setting the stopping row */ + if (i_y * stride - padding + dim_kernel >= dim_im_in) + { + row_end = Im_in + dim_im_in * dim_im_in * ch_im_in; + } + else + { + row_end = Im_in + (i_y * stride - padding + dim_kernel) * dim_im_in * ch_im_in; + } + + /* copy over the first row */ + arm_q7_to_q15_no_shift(row_start, buffer, dim_im_out * ch_im_in); + count = 1; + + /* move over to next row */ + row_start += ch_im_in * dim_im_in; + + for (; row_start < row_end; row_start += dim_im_in * ch_im_in) + { + accumulate_q7_to_q15(buffer, row_start, dim_im_out * ch_im_in); + count++; + } + buffer_scale_back_q15_to_q7(buffer, target, dim_im_out * ch_im_in, count); + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + (void)bufferA; + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out; i_y++) + { + for (i_x = 0; i_x < dim_im_out; i_x++) + { + int sum = 0; + int count = 0; + for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) + { + for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) + { + sum += Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; + count++; + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = sum / count; + } + } + } + +#endif /* ARM_MATH_DSP */ +} + +/** + * @} end of Pooling group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ReshapeFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/NN/Source/ReshapeFunctions/CMakeLists.txt new file mode 100644 index 00000000..4866a9a3 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ReshapeFunctions/CMakeLists.txt @@ -0,0 +1,29 @@ +# +# Copyright (c) 2019-2021 Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +project(CMSISNNReshape) + +file(GLOB SRC "./*_*.c") + +add_library(CMSISNNReshape STATIC ${SRC}) + +### Includes +target_include_directories(CMSISNNReshape PUBLIC "${NN}/Include") +target_include_directories(CMSISNNReshape PUBLIC "${ROOT}/CMSIS/Core/Include") +target_include_directories(CMSISNNReshape PUBLIC "${ROOT}/CMSIS/DSP/Include") + diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/ReshapeFunctions/arm_reshape_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/ReshapeFunctions/arm_reshape_s8.c new file mode 100644 index 00000000..cd839dcc --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/ReshapeFunctions/arm_reshape_s8.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_reshape_s8.c + * Description: Reshape a s8 vector + * + * $Date: September 2019 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Reshape + * @{ + */ + +/** + * Basic s8 reshape function. + * + * Refer header file for details. + * + */ + +void arm_reshape_s8(const int8_t *input, int8_t *output, const uint32_t total_size) +{ + memcpy(output, input, total_size); +} + +/** + * @} end of Reshape group + */ \ No newline at end of file diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/SVDFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/NN/Source/SVDFunctions/CMakeLists.txt new file mode 100644 index 00000000..b3adff6d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/SVDFunctions/CMakeLists.txt @@ -0,0 +1,31 @@ +# +# Copyright (c) 2019-2021 Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +project(CMSISNNSVDF) + +file(GLOB SRC "./*_s8.c") + +add_library(CMSISNNSVDF STATIC ${SRC}) + +### Includes +target_include_directories(CMSISNNSVDF PUBLIC "${NN}/Include") +target_include_directories(CMSISNNSVDF PUBLIC "${ROOT}/CMSIS/Core/Include") +target_include_directories(CMSISNNSVDF PUBLIC "${ROOT}/CMSIS/DSP/Include") + + + diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/SVDFunctions/arm_svdf_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/SVDFunctions/arm_svdf_s8.c new file mode 100644 index 00000000..c8bed031 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/SVDFunctions/arm_svdf_s8.c @@ -0,0 +1,254 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_svdf_s8.c + * Description: S8 basic SVDF layer function + * + * $Date: 15. April 2021 + * $Revision: V.1.5.0 + * + * Target Processor: Cortex-M processors + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup SVDF + * @{ + */ + +/* + * S8 SVDF layer function for TensorFlow Lite + * + * Refer to header file for details. + * + */ + +arm_status arm_svdf_s8(const cmsis_nn_context *input_ctx, + const cmsis_nn_context *output_ctx, + const cmsis_nn_svdf_params *svdf_params, + const cmsis_nn_per_tensor_quant_params *input_quant_params, + const cmsis_nn_per_tensor_quant_params *output_quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *state_dims, + q15_t *state_data, + const cmsis_nn_dims *weights_feature_dims, + const q7_t *weights_feature_data, + const cmsis_nn_dims *weights_time_dims, + const q15_t *weights_time_data, + const cmsis_nn_dims *bias_dims, + const q31_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data) +{ + (void)bias_dims; + (void)state_dims; + (void)output_dims; + + const q31_t multiplier_in = input_quant_params->multiplier; + const q31_t shift_in = input_quant_params->shift; + const q31_t multiplier_out = output_quant_params->multiplier; + const q31_t shift_2 = output_quant_params->shift; + const int32_t zp_in = svdf_params->input_offset; + const int32_t zp_out = svdf_params->output_offset; + const int32_t in_activation_min = svdf_params->input_activation.min; + const int32_t in_activation_max = svdf_params->input_activation.max; + const int32_t out_activation_min = svdf_params->output_activation.min; + const int32_t out_activation_max = svdf_params->output_activation.max; + const int16_t rank = svdf_params->rank; + + const int32_t input_batches = input_dims->n; + const int32_t input_height = input_dims->h; + const int32_t feature_batches = weights_feature_dims->n; + const int32_t time_batches = weights_time_dims->h; + const int32_t unit_count = feature_batches / rank; + + q31_t *buffer_a = (q31_t *)input_ctx->buf; + q31_t *buffer_b = (q31_t *)output_ctx->buf; + + memmove((q15_t *)state_data, + (q15_t *)state_data + 1, + (size_t)(input_batches * feature_batches * time_batches * (int32_t)sizeof(int16_t))); + + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q15_t *res_ptr = state_data + (time_batches * i_batch * feature_batches) + (time_batches - 1); + const q7_t *weight = weights_feature_data; + const q7_t *input = input_data + i_batch * input_height; + + arm_status res = arm_nn_vec_mat_mult_t_svdf_s8(input, + weight, + res_ptr, + -zp_in, + 0, + time_batches, + multiplier_in, + shift_in, + input_height, + feature_batches, + in_activation_min, + in_activation_max); + + if (res != ARM_MATH_SUCCESS) + { + return res; + } + } + + { + q31_t *ptr_a = buffer_a; + const q15_t *v2 = state_data; + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + const q15_t *v1 = weights_time_data; + + for (int i_feature_batch = 0; i_feature_batch < feature_batches; i_feature_batch++) + { + *ptr_a = 0; + int32_t sum = 0; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + int j = 0; + int32_t block_count = time_batches >> 1; + for (int i = 0; i < block_count; i++) + { + j += 2; + q31_t r1 = arm_nn_read_q15x2_ia(&v1); + q31_t r2 = arm_nn_read_q15x2_ia(&v2); + + sum = __SMLAD(r1, r2, sum); + } + + // Process the remaining data + for (; j < time_batches; j++) + { + sum += *v1 * *v2; + v1++; + v2++; + } +#else + for (int j = 0; j < time_batches; j++) + { + sum += *v1 * *v2; + v1++; + v2++; + } +#endif + + *ptr_a = sum; + ptr_a++; + } + } + } + + if (bias_data) + { + if (unit_count == feature_batches) + { + for (int i = 0; i < input_batches; i++) + { + q31_t *output_temp = buffer_b + i * feature_batches; + const q31_t *ptr_a = buffer_a + i * feature_batches; + + const int32_t *bi = bias_data; + for (int j = 0; j < feature_batches; j++) + { + output_temp[j] = ptr_a[j] + bi[j]; + } + } + } + else + { + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q31_t *output_data_temp = buffer_b + i_batch * unit_count; + q31_t *ptr_a = buffer_a + i_batch * feature_batches; + + for (int i = 0; i < unit_count; i++) + { + int32_t sum = bias_data[i]; + for (int j = 0; j < rank; j++) + { + sum += *ptr_a; + ptr_a++; + } + output_data_temp[i] = sum; + } + } + } + } + else + { + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q31_t *output_data_temp = buffer_b + i_batch * unit_count; + q31_t *ptr_a = buffer_a + i_batch * feature_batches; + + for (int i = 0; i < unit_count; i++) + { + int32_t sum = 0; + for (int j = 0; j < rank; j++) + { + sum += *ptr_a; + ptr_a++; + } + output_data_temp[i] = sum; + } + } + } + +#if defined(ARM_MATH_MVEI) + int32_t num_elements = input_batches * unit_count; + const int32_t loop_count = (num_elements + 3) / 4; + for (int i_op = 0; i_op < loop_count; i_op++) + { + mve_pred16_t p = vctp32q((uint32_t)num_elements); + int32x4_t op = vldrwq_z_s32(buffer_b, p); + op = arm_requantize_mve(op, multiplier_out, shift_2); + op = vaddq_n_s32(op, zp_out); + const int32x4_t min_vec = vdupq_n_s32((int8_t)out_activation_min); + const int32x4_t max_vec = vdupq_n_s32((int8_t)out_activation_max); + op = vmaxq_s32(op, min_vec); + op = vminq_s32(op, max_vec); + vstrbq_p_s32(output_data, op, p); + output_data += 4; + buffer_b += 4; + num_elements -= 4; + } +#else + for (int i = 0; i < input_batches * unit_count; i++) + { + output_data[i] = (q7_t)CLAMP( + arm_nn_requantize(buffer_b[i], multiplier_out, shift_2) + zp_out, out_activation_max, out_activation_min); + } +#endif + + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of SVDF group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/SVDFunctions/arm_svdf_state_s16_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/SVDFunctions/arm_svdf_state_s16_s8.c new file mode 100644 index 00000000..988409b7 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/SVDFunctions/arm_svdf_state_s16_s8.c @@ -0,0 +1,267 @@ +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_svdf_s8.c + * Description: S8 basic SVDF layer function with s16 state tensor + * + * $Date: 28 April 2022 + * $Revision: V.1.0.1 + * + * Target Processor: Cortex-M processors + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup SVDF + * @{ + */ + +/* + * S8 SVDF layer function for TensorFlow Lite with 16 bit state tensor + * + * Refer to header file for details. + * + */ + +arm_status arm_svdf_state_s16_s8(const cmsis_nn_context *input_ctx, + const cmsis_nn_context *output_ctx, + const cmsis_nn_svdf_params *svdf_params, + const cmsis_nn_per_tensor_quant_params *input_quant_params, + const cmsis_nn_per_tensor_quant_params *output_quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *state_dims, + q15_t *state_data, + const cmsis_nn_dims *weights_feature_dims, + const q7_t *weights_feature_data, + const cmsis_nn_dims *weights_time_dims, + const q15_t *weights_time_data, + const cmsis_nn_dims *bias_dims, + const q31_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data) +{ + (void)bias_dims; + (void)state_dims; + (void)output_dims; + + const q31_t multiplier_in = input_quant_params->multiplier; + const q31_t shift_in = input_quant_params->shift; + const q31_t multiplier_out = output_quant_params->multiplier; + const q31_t shift_2 = output_quant_params->shift; + const int32_t zp_in = svdf_params->input_offset; + const int32_t zp_out = svdf_params->output_offset; + const int32_t in_activation_min = svdf_params->input_activation.min; + const int32_t in_activation_max = svdf_params->input_activation.max; + const int32_t out_activation_min = svdf_params->output_activation.min; + const int32_t out_activation_max = svdf_params->output_activation.max; + const int16_t rank = svdf_params->rank; + + const int32_t input_batches = input_dims->n; + const int32_t input_height = input_dims->h; + const int32_t feature_batches = weights_feature_dims->n; + const int32_t time_batches = weights_time_dims->h; + const int32_t unit_count = feature_batches / rank; + + if (input_ctx->buf == NULL) + { + return ARM_MATH_ARGUMENT_ERROR; + } + q31_t *buffer_a = (q31_t *)input_ctx->buf; + + if (output_ctx->buf == NULL) + { + return ARM_MATH_ARGUMENT_ERROR; + } + q31_t *buffer_b = (q31_t *)output_ctx->buf; + + // Left shift state + memmove((q15_t *)state_data, + (q15_t *)state_data + 1, + (size_t)((input_batches * feature_batches * time_batches - 1) * (int32_t)sizeof(int16_t))); + + // Matrix multiplication input * feature weight + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q15_t *res_ptr = state_data + (time_batches * i_batch * feature_batches) + (time_batches - 1); + const q7_t *weight = weights_feature_data; + const q7_t *input = input_data + i_batch * input_height; + + arm_status res = arm_nn_vec_mat_mult_t_svdf_s8(input, + weight, + res_ptr, + -zp_in, + 0, + time_batches, + multiplier_in, + shift_in, + input_height, + feature_batches, + in_activation_min, + in_activation_max); + + if (res != ARM_MATH_SUCCESS) + { + return res; + } + } + + { + // Matrix multiplication time weight * state tensors + q31_t *ptr_a = buffer_a; + const q15_t *v2 = state_data; + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + const q15_t *v1 = weights_time_data; + + for (int i_feature_batch = 0; i_feature_batch < feature_batches; i_feature_batch++) + { + *ptr_a = 0; + int32_t sum = 0; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + // Perform matrix multiplication in blocks of two + int j = 0; + int32_t block_count = time_batches >> 1; + for (int i = 0; i < block_count; i++) + { + j += 2; + q31_t r1 = arm_nn_read_q15x2_ia(&v1); + q31_t r2 = arm_nn_read_q15x2_ia(&v2); + + sum = __SMLAD(r1, r2, sum); + } + + // Process the remaining data + for (; j < time_batches; j++) + { + sum += *v1 * *v2; + v1++; + v2++; + } +#else + for (int j = 0; j < time_batches; j++) + { + sum += *v1 * *v2; + v1++; + v2++; + } +#endif + + *ptr_a = sum; + ptr_a++; + } + } + } + + if (bias_data) + { + if (unit_count == feature_batches) + { + for (int i = 0; i < input_batches; i++) + { + q31_t *output_temp = buffer_b + i * feature_batches; + const q31_t *ptr_a = buffer_a + i * feature_batches; + + const int32_t *bi = bias_data; + for (int j = 0; j < feature_batches; j++) + { + output_temp[j] = ptr_a[j] + bi[j]; + } + } + } + else + { + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q31_t *output_data_temp = buffer_b + i_batch * unit_count; + q31_t *ptr_a = buffer_a + i_batch * feature_batches; + + for (int i = 0; i < unit_count; i++) + { + int32_t sum = bias_data[i]; + for (int j = 0; j < rank; j++) + { + sum += *ptr_a; + ptr_a++; + } + output_data_temp[i] = sum; + } + } + } + } + else + { + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q31_t *output_data_temp = buffer_b + i_batch * unit_count; + q31_t *ptr_a = buffer_a + i_batch * feature_batches; + + for (int i = 0; i < unit_count; i++) + { + int32_t sum = 0; + for (int j = 0; j < rank; j++) + { + sum += *ptr_a; + ptr_a++; + } + output_data_temp[i] = sum; + } + } + } + +#if defined(ARM_MATH_MVEI) + int32_t num_elements = input_batches * unit_count; + const int32_t loop_count = (num_elements + 3) / 4; + for (int i_op = 0; i_op < loop_count; i_op++) + { + mve_pred16_t p = vctp32q((uint32_t)num_elements); + int32x4_t op = vldrwq_z_s32(buffer_b, p); + op = arm_requantize_mve(op, multiplier_out, shift_2); + op = vaddq_n_s32(op, zp_out); + const int32x4_t min_vec = vdupq_n_s32((int8_t)out_activation_min); + const int32x4_t max_vec = vdupq_n_s32((int8_t)out_activation_max); + op = vmaxq_s32(op, min_vec); + op = vminq_s32(op, max_vec); + vstrbq_p_s32(output_data, op, p); + output_data += 4; + buffer_b += 4; + num_elements -= 4; + } +#else + for (int i = 0; i < input_batches * unit_count; i++) + { + output_data[i] = (q7_t)CLAMP( + arm_nn_requantize(buffer_b[i], multiplier_out, shift_2) + zp_out, out_activation_max, out_activation_min); + } +#endif + + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of SVDF group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/CMakeLists.txt b/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/CMakeLists.txt new file mode 100644 index 00000000..a74a9947 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/CMakeLists.txt @@ -0,0 +1,30 @@ +# +# Copyright (c) 2019-2021 Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +project(CMSISNNSoftmax) + +file(GLOB SRC "./*_s8.c") +add_library(CMSISNNSoftmax STATIC ${SRC}) + +### Includes +target_include_directories(CMSISNNSoftmax PUBLIC "${NN}/Include") +target_include_directories(CMSISNNSoftmax PUBLIC "${ROOT}/CMSIS/Core/Include") +target_include_directories(CMSISNNSoftmax PUBLIC "${ROOT}/CMSIS/DSP/Include") + + + diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_nn_softmax_common_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_nn_softmax_common_s8.c new file mode 100644 index 00000000..84d1ac85 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_nn_softmax_common_s8.c @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_softmax_common_s8.c + * Description: Softmax with s8 input and output of s8 or s16. + * + * $Date: 17 March 2022 + * $Revision: V.1.0.1 + * + * Target Processor: Cortex-M processors + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +#define ACCUM_BITS 12 + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup Softmax + * @{ + */ + +/* + * Softmax function with s8 input and output of s8 or s16. + * + * Refer header file for details. + * + */ +void arm_nn_softmax_common_s8(const int8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + const bool int16_output, + void *output) +{ + const int32_t mask = (1 << shift); + + int32_t col = 0; + int32_t row_idx; + + for (row_idx = 0; row_idx < num_rows; ++row_idx) + { + // Find the maximum value in order to ensure numerical stability + int8_t max = *input; + + for (col = 1; col < row_size; ++col) + { + max = MAX(max, input[col]); + } + + int32_t diff = 0; + int32_t sum = 0; + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + if (diff >= diff_min) + { + sum += DIV_POW2(EXP_ON_NEG(MUL_SAT(diff * mask, mult)), ACCUM_BITS); + } + } + + const int32_t headroom = __CLZ(sum); + const int32_t shifted_scale = ONE_OVER1((sum > 0 ? sum << headroom : 0) - (1 << 31)); + int32_t bits_over_unit; + + if (int16_output) + { + int16_t *output_s16 = (int16_t *)output + row_idx * row_size; + + bits_over_unit = ACCUM_BITS - headroom + 15; + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + + if (diff >= diff_min) + { + const int32_t res = + DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit) + + NN_Q15_MIN; + output_s16[col] = (int16_t)CLAMP(res, (int32_t)NN_Q15_MAX, (int32_t)NN_Q15_MIN); + } + else + { + output_s16[col] = NN_Q15_MIN; + } + } + } + else + { + int8_t *output_s8 = (int8_t *)output + row_idx * row_size; + + bits_over_unit = ACCUM_BITS - headroom + 23; + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + if (diff >= diff_min) + { + const int32_t res = + DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit) + + NN_Q7_MIN; + output_s8[col] = (int8_t)CLAMP(res, (int32_t)NN_Q7_MAX, (int32_t)NN_Q7_MIN); + } + else + { + output_s8[col] = NN_Q7_MIN; + } + } + } + + input += row_size; + } +} + +/** + * @} end of NNBasicMath group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c b/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c new file mode 100644 index 00000000..18f3e836 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_q15.c + * Description: Q15 softmax function + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + +/** + * @brief Q15 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * + * @details + * + * Here, instead of typical e based softmax, we use + * 2-based softmax, i.e.,: + * + * y_i = 2^(x_i) / sum(2^x_j) + * + * The relative output will be different here. + * But mathematically, the gradient will be the same + * with a log(2) scaling factor. + * + */ + +void arm_softmax_q15(const q15_t *vec_in, const uint16_t dim_vec, q15_t *p_out) +{ + q31_t sum; + int16_t i; + uint8_t shift; + q31_t base; + base = -1 * 0x100000; + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + base = vec_in[i]; + } + } + + /* we ignore really small values + * anyway, they will be 0 after shrinking + * to q15_t + */ + base = base - 16; + + sum = 0; + + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + shift = (uint8_t)__USAT(vec_in[i] - base, 5); + sum += 0x1 << shift; + } + } + + /* This is effectively (0x1 << 32) / sum */ + int64_t div_base = 0x100000000LL; + int output_base = (int32_t)(div_base / sum); + + /* Final confidence will be output_base >> ( 17 - (vec_in[i] - base) ) + * so 32768 (0x1<<15) -> 100% confidence when sum = 0x1 << 16, output_base = 0x1 << 16 + * and vec_in[i]-base = 16 + */ + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + /* Here minimum value of 17+base-vec[i] will be 1 */ + shift = (uint8_t)__USAT(17 + base - vec_in[i], 5); + p_out[i] = (q15_t)__SSAT((output_base >> shift), 16); + } + else + { + p_out[i] = 0; + } + } +} + +/** + * @} end of Softmax group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c b/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c new file mode 100644 index 00000000..58eb990d --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_q7.c + * Description: Q7 softmax function + * + * $Date: 09. October 2020 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + +/** + * @brief Q7 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * + * @details + * + * Here, instead of typical natural logarithm e based softmax, we use + * 2-based softmax here, i.e.,: + * + * y_i = 2^(x_i) / sum(2^x_j) + * + * The relative output will be different here. + * But mathematically, the gradient will be the same + * with a log(2) scaling factor. + * + */ + +void arm_softmax_q7(const q7_t *vec_in, const uint16_t dim_vec, q7_t *p_out) +{ + q31_t sum; + int16_t i; + uint8_t shift; + q15_t base; + base = -128; + + /* We first search for the maximum */ + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + base = vec_in[i]; + } + } + + /* + * So the base is set to max-8, meaning + * that we ignore really small values. + * anyway, they will be 0 after shrinking to q7_t. + */ + base = base - (1 << 3); + + sum = 0; + + for (i = 0; i < dim_vec; i++) + { + shift = (uint8_t)__USAT(vec_in[i] - base, 3); + sum += 0x1 << shift; + } + + /* This is effectively (0x1 << 20) / sum */ + int output_base = (1 << 20) / sum; + + for (i = 0; i < dim_vec; i++) + { + + /* Here minimum value of 13+base-vec_in[i] will be 5 */ + shift = (uint8_t)__USAT(13 + base - vec_in[i], 5); + p_out[i] = (q7_t)__SSAT((output_base >> shift), 8); + } +} + +/** + * @} end of Softmax group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s16.c b/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s16.c new file mode 100644 index 00000000..e8408934 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s16.c @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_s16.c + * Description: S16 softmax function + * + * $Date: 9 March 2022 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @addtogroup Softmax + * @{ + */ + +arm_status arm_softmax_s16(const int16_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const cmsis_nn_softmax_lut_s16 *softmax_params, + int16_t *output) +{ + int32_t col = 0; + int32_t row_idx; + + if (softmax_params->exp_lut == NULL || softmax_params->one_by_one_lut == NULL) + { + return ARM_MATH_ARGUMENT_ERROR; + } + + for (row_idx = 0; row_idx < num_rows; ++row_idx) + { + // Find the maximum value in order to ensure numerical stability + int16_t max = *input; + for (col = 1; col < row_size; ++col) + { + max = MAX(max, input[col]); + } + + int32_t diff = 0; + int32_t sum = 0; + int16_t *cached_exp_results = output; + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + const int32_t scaled_diff = arm_nn_requantize(diff, mult, shift); + const int32_t symmetric_scaled_diff = scaled_diff + NN_Q15_MAX; + const int16_t saturated_symmetric_scaled_diff = MIN(MAX(symmetric_scaled_diff, NN_Q15_MIN), NN_Q15_MAX); + + // Lookup from exp table and cache result for next step + const int16_t index = (256 + (saturated_symmetric_scaled_diff >> 7)); + const int16_t offset = saturated_symmetric_scaled_diff & 0x7f; + const int16_t base = softmax_params->exp_lut[index]; + const int16_t slope = softmax_params->exp_lut[index + 1] - softmax_params->exp_lut[index]; + const int16_t delta = (slope * offset + 64) >> 7; + const int16_t result = (base + delta); + cached_exp_results[col] = result; + + sum += cached_exp_results[col]; + } + + const int32_t headroom = __CLZ(sum); + + // Compute the reciprocal 1/sum + const int32_t shifted_sum = (((sum) << (headroom - 1)) + (1 << 13)) >> 14; + + // Since LUT computes 1/(1 + x), compute x = (sum - 1) => -65536 + // Since LUT expects a symmetrical input, recenter from [UINT16_MIN, UINT16_MAX] to [INT16_MIN, INT16_MAX] => + // -32768 ==> So in total -65536 -32768 => -98304 + const int16_t symmetric_shifted_sum = shifted_sum - 98304; + + // Lookup from one by one table + const int16_t index = (256 + (symmetric_shifted_sum >> 7)); + const int16_t offset = symmetric_shifted_sum & 0x7f; + const int16_t base = softmax_params->one_by_one_lut[index]; + const int16_t slope = softmax_params->one_by_one_lut[index + 1] - softmax_params->one_by_one_lut[index]; + const int16_t delta = (slope * offset + 64) >> 7; + const int16_t one_by_one_result = (base + delta); + + for (col = 0; col < row_size; ++col) + { + const int16_t right_shift = 30 - headroom; + int32_t result = (cached_exp_results[col] * one_by_one_result) >> right_shift; + result = (result + 1) >> 1; // Last shift position and insert round + output[col] = (int16_t)result; + } + + output += row_size; + input += row_size; + } + + return ARM_MATH_SUCCESS; +} + +/** + * @} end of Softmax group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s8.c new file mode 100644 index 00000000..09ac947c --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s8.c @@ -0,0 +1,261 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_s8.c + * Description: S8 softmax function + * + * $Date: 01. March 2021 + * $Revision: V.2.0.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +#define ACCUM_BITS 12 + +#ifdef ARM_MATH_MVEI +static int32x4_t arm_exp_on_negative_values_mve_32x4(int32x4_t val) +{ +#define SHIFT_START (24) + int32_t shift = SHIFT_START; + int32x4_t mask; + + const int32x4_t val_mod_minus_quarter = + vandq_s32(val, vdupq_n_s32((1 << SHIFT_START) - 1)) - vdupq_n_s32(1 << SHIFT_START); + const int32x4_t remainder = vsubq_s32(val_mod_minus_quarter, val); + const int32x4_t x = vaddq_n_s32(val_mod_minus_quarter << 5, 1 << 28); + const int32x4_t x2 = MUL_SAT_MVE(x, x); + const int32x4_t op_1 = DIV_POW2_MVE(MUL_SAT_MVE(x2, x2), 2) + MUL_SAT_MVE(x2, x); + const int32x4_t op_2 = x + DIV_POW2_MVE(MUL_SAT_MVE(op_1, vdupq_n_s32(715827883)) + x2, 1); + int32x4_t result = vdupq_n_s32(1895147668) + MUL_SAT_MVE(vdupq_n_s32(1895147668), op_2); + +#define SELECT_IF_NON_ZERO(x) \ + { \ + mve_pred16_t p = vcmpneq_n_s32(remainder & vdupq_n_s32(1 << shift++), 0); \ + mask = vmvnq_m_s32(vdupq_n_s32(0), vdupq_n_s32(0), p); \ + result = SELECT_USING_MASK(mask, MUL_SAT_MVE(result, vdupq_n_s32(x)), result); \ + } + + SELECT_IF_NON_ZERO(1672461947) + SELECT_IF_NON_ZERO(1302514674) + SELECT_IF_NON_ZERO(790015084) + SELECT_IF_NON_ZERO(290630308) + SELECT_IF_NON_ZERO(39332535) + SELECT_IF_NON_ZERO(720401) + SELECT_IF_NON_ZERO(242) + +#undef SELECT_IF_NON_ZERO + + mve_pred16_t p = vcmpeqq_n_s32(val, 0); + mask = vmvnq_m_s32(vdupq_n_s32(0), vdupq_n_s32(0), p); + + result = SELECT_USING_MASK(mask, vdupq_n_s32(Q31_MAX), result); + return result; +} +#endif + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + +void arm_softmax_s8(const int8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + int8_t *output) +{ +#ifdef ARM_MATH_MVEI + +#define ACT_MIN ((int8_t)Q7_MIN) +#define ACT_MAX ((int8_t)Q7_MAX) + + const int32_t mask = (1 << shift); + + for (int i_num_rows = 0; i_num_rows < num_rows; ++i_num_rows) + { + int8_t max = ACT_MIN; + + int32_t vec_count = (row_size + 15) / 16; + uint32_t r_count = (uint32_t)row_size; + for (int i = 0; i < vec_count; i++) + { + mve_pred16_t p = vctp8q(r_count); + const int8x16_t ip = vldrbq_z_s8(&input[i * 16], p); + max = vmaxvq_p_s8(max, ip, p); + r_count -= 16; + } + + vec_count = row_size / 4; + int32_t idx = 0; + int32_t sum = 0; + + while (vec_count) + { + int32x4_t ip = vldrbq_s32(&input[idx * 4]); + ip = vsubq_n_s32(ip, max); + mve_pred16_t p = vcmpgeq_n_s32(ip, diff_min); + if (p != 0) + { + ip = vmulq_n_s32(ip, mask); + + int32x4_t res = MUL_SAT_MVE(ip, vdupq_n_s32(mult)); + + res = arm_exp_on_negative_values_mve_32x4(res); + res = DIV_POW2_MVE(res, ACCUM_BITS); + res = vpselq_s32(res, vdupq_n_s32(0), p); + sum += vaddvq_s32(res); + } + + vec_count--; + idx++; + } + + const int32_t tail_idx = row_size & ~3; + for (int i = 0; i < (row_size & 3); i++) + { + const int32_t diff = input[tail_idx + i] - max; + if (diff >= diff_min) + { + sum += DIV_POW2(EXP_ON_NEG(MUL_SAT(diff * mask, mult)), ACCUM_BITS); + } + } + + const int32_t headroom = __CLZ((uint32_t)sum); + const int32_t bits_over_unit = ACCUM_BITS - headroom + 23; + const int32_t shifted_scale = ONE_OVER1((sum > 0 ? sum << headroom : 0) - (1 << 31)); + + vec_count = row_size / 4; + idx = 0; + + while (vec_count) + { + int32x4_t ip = vldrbq_s32(&input[idx]); + ip = vsubq_n_s32(ip, max); + + mve_pred16_t p = vcmpgeq_n_s32(ip, diff_min); + + int32x4_t tmp_res; + + if (p != 0) + { + ip = vmulq_n_s32(ip, mask); + + tmp_res = MUL_SAT_MVE(ip, vdupq_n_s32(mult)); + tmp_res = arm_exp_on_negative_values_mve_32x4(tmp_res); + tmp_res = MUL_SAT_MVE(vdupq_n_s32(shifted_scale), tmp_res); + tmp_res = DIV_POW2_MVE(tmp_res, bits_over_unit); + tmp_res += vdupq_n_s32(ACT_MIN); + + tmp_res = vmaxq_s32(tmp_res, vdupq_n_s32(ACT_MIN)); + tmp_res = vminq_s32(tmp_res, vdupq_n_s32(ACT_MAX)); + tmp_res = vpselq_s32(tmp_res, vdupq_n_s32(ACT_MIN), p); + } + else + { + tmp_res = vdupq_n_s32(ACT_MIN); + } + vstrbq_s32(&output[idx], tmp_res); + vec_count--; + idx += 4; + } + + for (int i = 0; i < (row_size & 3); i++) + { + int32_t diff = input[tail_idx + i] - max; + if (diff >= diff_min) + { + const int32_t res = + DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit) - 128; + output[tail_idx + i] = (int8_t)CLAMP(res, (int32_t)ACT_MAX, (int32_t)ACT_MIN); + } + else + { + output[tail_idx + i] = ACT_MIN; + } + } + + input += row_size; + output += row_size; + } +#else + const int32_t mask = (1 << shift); + + int32_t col = 0; + int32_t row_idx; + + for (row_idx = 0; row_idx < num_rows; ++row_idx) + { + // Find the maximum value in order to ensure numerical stability + int8_t max = *input; + + for (col = 1; col < row_size; ++col) + { + max = MAX(max, input[col]); + } + + int32_t diff = 0; + int32_t sum = 0; + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + if (diff >= diff_min) + { + sum += DIV_POW2(EXP_ON_NEG(MUL_SAT(diff * mask, mult)), ACCUM_BITS); + } + } + + const int32_t headroom = __CLZ(sum); + const int32_t bits_over_unit = ACCUM_BITS - headroom + 23; + const int32_t shifted_scale = ONE_OVER1((sum > 0 ? sum << headroom : 0) - (1 << 31)); + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + if (diff >= diff_min) + { + const int32_t res = + DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit) - 128; + output[col] = (int8_t)CLAMP(res, (int32_t)127, (int32_t)-128); + } + else + { + output[col] = -128; + } + } + input += row_size; + output += row_size; + } + +#endif +} +/** + * @} end of Softmax group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s8_s16.c b/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s8_s16.c new file mode 100644 index 00000000..9ba0b9a2 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s8_s16.c @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_s8_s16.c + * Description: S8 to s16 softmax function + * + * $Date: 7 January 2022 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + +void arm_softmax_s8_s16(const int8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + int16_t *output) +{ + arm_nn_softmax_common_s8(input, num_rows, row_size, mult, shift, diff_min, true, (void *)output); +} +/** + * @} end of Softmax group + */ diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_u8.c b/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_u8.c new file mode 100644 index 00000000..c4df8f8a --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_u8.c @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_u8.c + * Description: U8 softmax function + * + * $Date: 09. October 2020 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +#define ACCUM_BITS 12 + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ +void arm_softmax_u8(const uint8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + uint8_t *output) +{ + const int32_t mask = (1 << shift); + + int32_t col = 0; + int32_t row_idx; + + for (row_idx = 0; row_idx < num_rows; ++row_idx) + { + // Find the maximum value in order to ensure numerical stability + uint8_t max = *input; + + for (col = 1; col < row_size; ++col) + { + max = MAX(max, input[col]); + } + + int32_t diff = 0; + int32_t sum = 0; + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + if (diff >= diff_min) + { + sum += DIV_POW2(EXP_ON_NEG(MUL_SAT(diff * mask, mult)), ACCUM_BITS); + } + } + + const int32_t headroom = __CLZ((uint32_t)sum); + const int32_t bits_over_unit = ACCUM_BITS - headroom + 23; + const int32_t shifted_scale = ONE_OVER1((sum << headroom) - (1 << 31)); + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + if (diff >= diff_min) + { + const int32_t res = + DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit); + output[col] = (uint8_t)CLAMP(res, (int32_t)255, (int32_t)0); + } + else + { + output[col] = 0; + } + } + input += row_size; + output += row_size; + } +} +/** + * @} end of Softmax group + */ \ No newline at end of file diff --git a/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_with_batch_q7.c b/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_with_batch_q7.c new file mode 100644 index 00000000..66e892e0 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_with_batch_q7.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_with_batch_q7.c + * Description: Q7 softmax function + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: Cortex-M and Cortex-A cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + +/** + * @brief Q7 softmax function with batch parameter + * @param[in] vec_in pointer to input vector + * @param[in] nb_batches number of batches + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * + * @details + * + * Here, instead of typical natural logarithm e based softmax, we use + * 2-based softmax here, i.e.,: + * + * y_i = 2^(x_i) / sum(2^x_j) + * + * The relative output will be different here. + * But mathematically, the gradient will be the same + * with a log(2) scaling factor. + * + */ + +void arm_softmax_with_batch_q7(const q7_t *vec_in, const uint16_t nb_batches, const uint16_t dim_vec, q7_t *p_out) +{ + for (int i = 0; i < nb_batches; i++) + { + arm_softmax_q7(vec_in, dim_vec, p_out); + vec_in += dim_vec; + p_out += dim_vec; + } +} + +/** + * @} end of Softmax group + */ diff --git a/benchmark/interface/Drivers/CMSIS/RTOS/Template/cmsis_os.h b/benchmark/interface/Drivers/CMSIS/RTOS/Template/cmsis_os.h new file mode 100644 index 00000000..30068d35 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/RTOS/Template/cmsis_os.h @@ -0,0 +1,698 @@ +/* ---------------------------------------------------------------------- + * $Date: 5. February 2013 + * $Revision: V1.02 + * + * Project: CMSIS-RTOS API + * Title: cmsis_os.h template header file + * + * Version 0.02 + * Initial Proposal Phase + * Version 0.03 + * osKernelStart added, optional feature: main started as thread + * osSemaphores have standard behavior + * osTimerCreate does not start the timer, added osTimerStart + * osThreadPass is renamed to osThreadYield + * Version 1.01 + * Support for C++ interface + * - const attribute removed from the osXxxxDef_t typedef's + * - const attribute added to the osXxxxDef macros + * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete + * Added: osKernelInitialize + * Version 1.02 + * Control functions for short timeouts in microsecond resolution: + * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec + * Removed: osSignalGet + *---------------------------------------------------------------------------- + * + * Copyright (c) 2013-2017 ARM LIMITED + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *---------------------------------------------------------------------------*/ + + +#ifndef _CMSIS_OS_H +#define _CMSIS_OS_H + +/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version. +#define osCMSIS 0x10002 ///< API version (main [31:16] .sub [15:0]) + +/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number. +#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0]) + +/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS. +#define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string + +/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS. +#define osFeature_MainThread 1 ///< main thread 1=main can be thread, 0=not available +#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available +#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available +#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available +#define osFeature_Signals 8 ///< maximum number of Signal Flags available per thread +#define osFeature_Semaphore 30 ///< maximum count for \ref osSemaphoreCreate function +#define osFeature_Wait 1 ///< osWait function: 1=available, 0=not available +#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumeration, structures, defines ==== + +/// Priority used for thread control. +/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS. +typedef enum { + osPriorityIdle = -3, ///< priority: idle (lowest) + osPriorityLow = -2, ///< priority: low + osPriorityBelowNormal = -1, ///< priority: below normal + osPriorityNormal = 0, ///< priority: normal (default) + osPriorityAboveNormal = +1, ///< priority: above normal + osPriorityHigh = +2, ///< priority: high + osPriorityRealtime = +3, ///< priority: realtime (highest) + osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority +} osPriority; + +/// Timeout value. +/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS. +#define osWaitForever 0xFFFFFFFF ///< wait forever timeout value + +/// Status code values returned by CMSIS-RTOS functions. +/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS. +typedef enum { + osOK = 0, ///< function completed; no error or event occurred. + osEventSignal = 0x08, ///< function completed; signal event occurred. + osEventMessage = 0x10, ///< function completed; message event occurred. + osEventMail = 0x20, ///< function completed; mail event occurred. + osEventTimeout = 0x40, ///< function completed; timeout occurred. + osErrorParameter = 0x80, ///< parameter error: a mandatory parameter was missing or specified an incorrect object. + osErrorResource = 0x81, ///< resource not available: a specified resource was not available. + osErrorTimeoutResource = 0xC1, ///< resource not available within given time: a specified resource was not available within the timeout period. + osErrorISR = 0x82, ///< not allowed in ISR context: the function cannot be called from interrupt service routines. + osErrorISRRecursive = 0x83, ///< function called multiple times from ISR with same object. + osErrorPriority = 0x84, ///< system cannot determine priority or thread has illegal priority. + osErrorNoMemory = 0x85, ///< system is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorValue = 0x86, ///< value of a parameter is out of range. + osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits. + os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization. +} osStatus; + + +/// Timer type value for the timer definition. +/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS. +typedef enum { + osTimerOnce = 0, ///< one-shot timer + osTimerPeriodic = 1 ///< repeating timer +} os_timer_type; + +/// Entry point of a thread. +/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. +typedef void (*os_pthread) (void const *argument); + +/// Entry point of a timer call back function. +/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. +typedef void (*os_ptimer) (void const *argument); + +// >>> the following data type definitions may shall adapted towards a specific RTOS + +/// Thread ID identifies the thread (pointer to a thread control block). +/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_thread_cb *osThreadId; + +/// Timer ID identifies the timer (pointer to a timer control block). +/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_timer_cb *osTimerId; + +/// Mutex ID identifies the mutex (pointer to a mutex control block). +/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mutex_cb *osMutexId; + +/// Semaphore ID identifies the semaphore (pointer to a semaphore control block). +/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_semaphore_cb *osSemaphoreId; + +/// Pool ID identifies the memory pool (pointer to a memory pool control block). +/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_cb *osPoolId; + +/// Message ID identifies the message queue (pointer to a message queue control block). +/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_messageQ_cb *osMessageQId; + +/// Mail ID identifies the mail queue (pointer to a mail queue control block). +/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_cb *osMailQId; + + +/// Thread Definition structure contains startup information of a thread. +/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. +typedef struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osPriority tpriority; ///< initial thread priority + uint32_t instances; ///< maximum number of instances of that thread function + uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size +} osThreadDef_t; + +/// Timer Definition structure contains timer parameters. +/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS. +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function +} osTimerDef_t; + +/// Mutex Definition structure contains setup information for a mutex. +/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS. +typedef struct os_mutex_def { + uint32_t dummy; ///< dummy value. +} osMutexDef_t; + +/// Semaphore Definition structure contains setup information for a semaphore. +/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS. +typedef struct os_semaphore_def { + uint32_t dummy; ///< dummy value. +} osSemaphoreDef_t; + +/// Definition structure for memory block allocation. +/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + void *pool; ///< pointer to memory for pool +} osPoolDef_t; + +/// Definition structure for message queue. +/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS. +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for messages +} osMessageQDef_t; + +/// Definition structure for mail queue. +/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for mail +} osMailQDef_t; + +/// Event structure contains detailed information about an event. +/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS. +/// However the struct may be extended at the end. +typedef struct { + osStatus status; ///< status code: event or error information + union { + uint32_t v; ///< message as 32-bit value + void *p; ///< message or mail as void pointer + int32_t signals; ///< signal flags + } value; ///< event value + union { + osMailQId mail_id; ///< mail id obtained by \ref osMailCreate + osMessageQId message_id; ///< message id obtained by \ref osMessageCreate + } def; ///< event definition +} osEvent; + + +// ==== Kernel Control Functions ==== + +/// Initialize the RTOS Kernel for creating objects. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS. +osStatus osKernelInitialize (void); + +/// Start the RTOS Kernel. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. +osStatus osKernelStart (void); + +/// Check if the RTOS kernel is already started. +/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. +/// \return 0 RTOS is not started, 1 RTOS is started. +int32_t osKernelRunning(void); + +#if (defined (osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available + +/// Get the RTOS kernel system timer counter +/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS. +/// \return RTOS kernel system timer as 32-bit value +uint32_t osKernelSysTick (void); + +/// The RTOS kernel system timer frequency in Hz +/// \note Reflects the system timer setting and is typically defined in a configuration file. +#define osKernelSysTickFrequency 100000000 + +/// Convert a microseconds value to a RTOS kernel system timer value. +/// \param microsec time value in microseconds. +/// \return time value normalized to the \ref osKernelSysTickFrequency +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000) + +#endif // System Timer available + +// ==== Thread Management ==== + +/// Create a Thread Definition with function, priority, and stack requirements. +/// \param name name of the thread function. +/// \param priority initial priority of the thread function. +/// \param instances number of possible thread instances. +/// \param stacksz stack size (in bytes) requirements for the thread function. +/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osThreadDef(name, priority, instances, stacksz) \ +extern const osThreadDef_t os_thread_def_##name +#else // define the object +#define osThreadDef(name, priority, instances, stacksz) \ +const osThreadDef_t os_thread_def_##name = \ +{ (name), (priority), (instances), (stacksz) } +#endif + +/// Access a Thread definition. +/// \param name name of the thread definition object. +/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osThread(name) \ +&os_thread_def_##name + +/// Create a thread and add it to Active Threads and set it to state READY. +/// \param[in] thread_def thread definition referenced with \ref osThread. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS. +osThreadId osThreadGetId (void); + +/// Terminate execution of a thread and remove it from Active Threads. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS. +osStatus osThreadTerminate (osThreadId thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS. +osStatus osThreadYield (void); + +/// Change priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS. +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); + +/// Get current priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return current priority value of the thread function. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS. +osPriority osThreadGetPriority (osThreadId thread_id); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value +/// \return status code that indicates the execution status of the function. +osStatus osDelay (uint32_t millisec); + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available + +/// Wait for Signal, Message, Mail, or Timeout. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return event that contains signal, message, or mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS. +osEvent osWait (uint32_t millisec); + +#endif // Generic Wait available + + +// ==== Timer Management Functions ==== +/// Define a Timer object. +/// \param name name of the timer object. +/// \param function name of the timer call back function. +/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osTimerDef(name, function) \ +extern const osTimerDef_t os_timer_def_##name +#else // define the object +#define osTimerDef(name, function) \ +const osTimerDef_t os_timer_def_##name = \ +{ (function) } +#endif + +/// Access a Timer definition. +/// \param name name of the timer object. +/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osTimer(name) \ +&os_timer_def_##name + +/// Create a timer. +/// \param[in] timer_def timer object referenced with \ref osTimer. +/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer call back function. +/// \return timer ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS. +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS. +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); + +/// Stop the timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS. +osStatus osTimerStop (osTimerId timer_id); + +/// Delete a timer that was created by \ref osTimerCreate. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS. +osStatus osTimerDelete (osTimerId timer_id); + + +// ==== Signal Management ==== + +/// Set the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that should be set. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS. +int32_t osSignalSet (osThreadId thread_id, int32_t signals); + +/// Clear the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that shall be cleared. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR. +/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS. +int32_t osSignalClear (osThreadId thread_id, int32_t signals); + +/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event flag information or error code. +/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS. +osEvent osSignalWait (int32_t signals, uint32_t millisec); + + +// ==== Mutex Management ==== + +/// Define a Mutex. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMutexDef(name) \ +extern const osMutexDef_t os_mutex_def_##name +#else // define the object +#define osMutexDef(name) \ +const osMutexDef_t os_mutex_def_##name = { 0 } +#endif + +/// Access a Mutex definition. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMutex(name) \ +&os_mutex_def_##name + +/// Create and Initialize a Mutex object. +/// \param[in] mutex_def mutex definition referenced with \ref osMutex. +/// \return mutex ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS. +osMutexId osMutexCreate (const osMutexDef_t *mutex_def); + +/// Wait until a Mutex becomes available. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS. +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); + +/// Release a Mutex that was obtained by \ref osMutexWait. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS. +osStatus osMutexRelease (osMutexId mutex_id); + +/// Delete a Mutex that was created by \ref osMutexCreate. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS. +osStatus osMutexDelete (osMutexId mutex_id); + + +// ==== Semaphore Management Functions ==== + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) // Semaphore available + +/// Define a Semaphore object. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osSemaphoreDef(name) \ +extern const osSemaphoreDef_t os_semaphore_def_##name +#else // define the object +#define osSemaphoreDef(name) \ +const osSemaphoreDef_t os_semaphore_def_##name = { 0 } +#endif + +/// Access a Semaphore definition. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osSemaphore(name) \ +&os_semaphore_def_##name + +/// Create and Initialize a Semaphore object used for managing resources. +/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. +/// \param[in] count number of available resources. +/// \return semaphore ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS. +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count); + +/// Wait until a Semaphore token becomes available. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return number of available tokens, or -1 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); + +/// Release a Semaphore token. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); + +/// Delete a Semaphore that was created by \ref osSemaphoreCreate. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id); + +#endif // Semaphore available + + +// ==== Memory Pool Management Functions ==== + +#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available + +/// \brief Define a Memory Pool. +/// \param name name of the memory pool. +/// \param no maximum number of blocks (objects) in the memory pool. +/// \param type data type of a single block (object). +/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osPoolDef(name, no, type) \ +extern const osPoolDef_t os_pool_def_##name +#else // define the object +#define osPoolDef(name, no, type) \ +const osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), NULL } +#endif + +/// \brief Access a Memory Pool definition. +/// \param name name of the memory pool +/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osPool(name) \ +&os_pool_def_##name + +/// Create and Initialize a memory pool. +/// \param[in] pool_def memory pool definition referenced with \ref osPool. +/// \return memory pool ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS. +osPoolId osPoolCreate (const osPoolDef_t *pool_def); + +/// Allocate a memory block from a memory pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolAlloc (osPoolId pool_id); + +/// Allocate a memory block from a memory pool and set memory block to zero. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolCAlloc (osPoolId pool_id); + +/// Return an allocated memory block back to a specific memory pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \param[in] block address of the allocated memory block that is returned to the memory pool. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS. +osStatus osPoolFree (osPoolId pool_id, void *block); + +#endif // Memory Pool Management available + + +// ==== Message Queue Management Functions ==== + +#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queues available + +/// \brief Create a Message Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of messages in the queue. +/// \param type data type of a single message element (for debugger). +/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMessageQDef(name, queue_sz, type) \ +extern const osMessageQDef_t os_messageQ_def_##name +#else // define the object +#define osMessageQDef(name, queue_sz, type) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), sizeof (type) } +#endif + +/// \brief Access a Message Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMessageQ(name) \ +&os_messageQ_def_##name + +/// Create and Initialize a Message Queue. +/// \param[in] queue_def queue definition referenced with \ref osMessageQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return message queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS. +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id); + +/// Put a Message to a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] info message information. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS. +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); + +/// Get a Message or Wait for a Message from a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event information that includes status code. +/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS. +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); + +#endif // Message Queues available + + +// ==== Mail Queue Management Functions ==== + +#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queues available + +/// \brief Create a Mail Queue Definition. +/// \param name name of the queue +/// \param queue_sz maximum number of messages in queue +/// \param type data type of a single message element +/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMailQDef(name, queue_sz, type) \ +extern const osMailQDef_t os_mailQ_def_##name +#else // define the object +#define osMailQDef(name, queue_sz, type) \ +const osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof (type) } +#endif + +/// \brief Access a Mail Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMailQ(name) \ +&os_mailQ_def_##name + +/// Create and Initialize mail queue. +/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return mail queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS. +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id); + +/// Allocate a memory block from a mail. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS. +void *osMailAlloc (osMailQId queue_id, uint32_t millisec); + +/// Allocate a memory block from a mail and set memory block to zero. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS. +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); + +/// Put a mail to a queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS. +osStatus osMailPut (osMailQId queue_id, void *mail); + +/// Get a mail from a queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return event that contains mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS. +osEvent osMailGet (osMailQId queue_id, uint32_t millisec); + +/// Free a memory block from a mail. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS. +osStatus osMailFree (osMailQId queue_id, void *mail); + +#endif // Mail Queues available + + +#ifdef __cplusplus +} +#endif + +#endif // _CMSIS_OS_H diff --git a/benchmark/interface/Drivers/CMSIS/RTOS2/Include/cmsis_os2.h b/benchmark/interface/Drivers/CMSIS/RTOS2/Include/cmsis_os2.h new file mode 100644 index 00000000..76612e29 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/RTOS2/Include/cmsis_os2.h @@ -0,0 +1,756 @@ +/* + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 12. June 2020 + * $Revision: V2.1.3 + * + * Project: CMSIS-RTOS2 API + * Title: cmsis_os2.h header file + * + * Version 2.1.3 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osThreadGetId + * Version 2.1.2 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetInfo, osKernelGetState + * Version 2.1.1 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetTickCount, osKernelGetTickFreq + * Changed Kernel Tick type to uint32_t: + * - updated: osKernelGetTickCount, osDelayUntil + * Version 2.1.0 + * Support for critical and uncritical sections (nesting safe): + * - updated: osKernelLock, osKernelUnlock + * - added: osKernelRestoreLock + * Updated Thread and Event Flags: + * - changed flags parameter and return type from int32_t to uint32_t + * Version 2.0.0 + * Initial Release + *---------------------------------------------------------------------------*/ + +#ifndef CMSIS_OS2_H_ +#define CMSIS_OS2_H_ + +#ifndef __NO_RETURN +#if defined(__CC_ARM) +#define __NO_RETURN __declspec(noreturn) +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define __NO_RETURN __attribute__((__noreturn__)) +#elif defined(__GNUC__) +#define __NO_RETURN __attribute__((__noreturn__)) +#elif defined(__ICCARM__) +#define __NO_RETURN __noreturn +#else +#define __NO_RETURN +#endif +#endif + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumerations, structures, defines ==== + +/// Version information. +typedef struct { + uint32_t api; ///< API version (major.minor.rev: mmnnnrrrr dec). + uint32_t kernel; ///< Kernel version (major.minor.rev: mmnnnrrrr dec). +} osVersion_t; + +/// Kernel state. +typedef enum { + osKernelInactive = 0, ///< Inactive. + osKernelReady = 1, ///< Ready. + osKernelRunning = 2, ///< Running. + osKernelLocked = 3, ///< Locked. + osKernelSuspended = 4, ///< Suspended. + osKernelError = -1, ///< Error. + osKernelReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osKernelState_t; + +/// Thread state. +typedef enum { + osThreadInactive = 0, ///< Inactive. + osThreadReady = 1, ///< Ready. + osThreadRunning = 2, ///< Running. + osThreadBlocked = 3, ///< Blocked. + osThreadTerminated = 4, ///< Terminated. + osThreadError = -1, ///< Error. + osThreadReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osThreadState_t; + +/// Priority values. +typedef enum { + osPriorityNone = 0, ///< No priority (not initialized). + osPriorityIdle = 1, ///< Reserved for Idle thread. + osPriorityLow = 8, ///< Priority: low + osPriorityLow1 = 8+1, ///< Priority: low + 1 + osPriorityLow2 = 8+2, ///< Priority: low + 2 + osPriorityLow3 = 8+3, ///< Priority: low + 3 + osPriorityLow4 = 8+4, ///< Priority: low + 4 + osPriorityLow5 = 8+5, ///< Priority: low + 5 + osPriorityLow6 = 8+6, ///< Priority: low + 6 + osPriorityLow7 = 8+7, ///< Priority: low + 7 + osPriorityBelowNormal = 16, ///< Priority: below normal + osPriorityBelowNormal1 = 16+1, ///< Priority: below normal + 1 + osPriorityBelowNormal2 = 16+2, ///< Priority: below normal + 2 + osPriorityBelowNormal3 = 16+3, ///< Priority: below normal + 3 + osPriorityBelowNormal4 = 16+4, ///< Priority: below normal + 4 + osPriorityBelowNormal5 = 16+5, ///< Priority: below normal + 5 + osPriorityBelowNormal6 = 16+6, ///< Priority: below normal + 6 + osPriorityBelowNormal7 = 16+7, ///< Priority: below normal + 7 + osPriorityNormal = 24, ///< Priority: normal + osPriorityNormal1 = 24+1, ///< Priority: normal + 1 + osPriorityNormal2 = 24+2, ///< Priority: normal + 2 + osPriorityNormal3 = 24+3, ///< Priority: normal + 3 + osPriorityNormal4 = 24+4, ///< Priority: normal + 4 + osPriorityNormal5 = 24+5, ///< Priority: normal + 5 + osPriorityNormal6 = 24+6, ///< Priority: normal + 6 + osPriorityNormal7 = 24+7, ///< Priority: normal + 7 + osPriorityAboveNormal = 32, ///< Priority: above normal + osPriorityAboveNormal1 = 32+1, ///< Priority: above normal + 1 + osPriorityAboveNormal2 = 32+2, ///< Priority: above normal + 2 + osPriorityAboveNormal3 = 32+3, ///< Priority: above normal + 3 + osPriorityAboveNormal4 = 32+4, ///< Priority: above normal + 4 + osPriorityAboveNormal5 = 32+5, ///< Priority: above normal + 5 + osPriorityAboveNormal6 = 32+6, ///< Priority: above normal + 6 + osPriorityAboveNormal7 = 32+7, ///< Priority: above normal + 7 + osPriorityHigh = 40, ///< Priority: high + osPriorityHigh1 = 40+1, ///< Priority: high + 1 + osPriorityHigh2 = 40+2, ///< Priority: high + 2 + osPriorityHigh3 = 40+3, ///< Priority: high + 3 + osPriorityHigh4 = 40+4, ///< Priority: high + 4 + osPriorityHigh5 = 40+5, ///< Priority: high + 5 + osPriorityHigh6 = 40+6, ///< Priority: high + 6 + osPriorityHigh7 = 40+7, ///< Priority: high + 7 + osPriorityRealtime = 48, ///< Priority: realtime + osPriorityRealtime1 = 48+1, ///< Priority: realtime + 1 + osPriorityRealtime2 = 48+2, ///< Priority: realtime + 2 + osPriorityRealtime3 = 48+3, ///< Priority: realtime + 3 + osPriorityRealtime4 = 48+4, ///< Priority: realtime + 4 + osPriorityRealtime5 = 48+5, ///< Priority: realtime + 5 + osPriorityRealtime6 = 48+6, ///< Priority: realtime + 6 + osPriorityRealtime7 = 48+7, ///< Priority: realtime + 7 + osPriorityISR = 56, ///< Reserved for ISR deferred thread. + osPriorityError = -1, ///< System cannot determine priority or illegal priority. + osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osPriority_t; + +/// Entry point of a thread. +typedef void (*osThreadFunc_t) (void *argument); + +/// Timer callback function. +typedef void (*osTimerFunc_t) (void *argument); + +/// Timer type. +typedef enum { + osTimerOnce = 0, ///< One-shot timer. + osTimerPeriodic = 1 ///< Repeating timer. +} osTimerType_t; + +// Timeout value. +#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value. + +// Flags options (\ref osThreadFlagsWait and \ref osEventFlagsWait). +#define osFlagsWaitAny 0x00000000U ///< Wait for any flag (default). +#define osFlagsWaitAll 0x00000001U ///< Wait for all flags. +#define osFlagsNoClear 0x00000002U ///< Do not clear flags which have been specified to wait for. + +// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx). +#define osFlagsError 0x80000000U ///< Error indicator. +#define osFlagsErrorUnknown 0xFFFFFFFFU ///< osError (-1). +#define osFlagsErrorTimeout 0xFFFFFFFEU ///< osErrorTimeout (-2). +#define osFlagsErrorResource 0xFFFFFFFDU ///< osErrorResource (-3). +#define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4). +#define osFlagsErrorISR 0xFFFFFFFAU ///< osErrorISR (-6). + +// Thread attributes (attr_bits in \ref osThreadAttr_t). +#define osThreadDetached 0x00000000U ///< Thread created in detached mode (default) +#define osThreadJoinable 0x00000001U ///< Thread created in joinable mode + +// Mutex attributes (attr_bits in \ref osMutexAttr_t). +#define osMutexRecursive 0x00000001U ///< Recursive mutex. +#define osMutexPrioInherit 0x00000002U ///< Priority inherit protocol. +#define osMutexRobust 0x00000008U ///< Robust mutex. + +/// Status code values returned by CMSIS-RTOS functions. +typedef enum { + osOK = 0, ///< Operation completed successfully. + osError = -1, ///< Unspecified RTOS error: run-time error but no other error message fits. + osErrorTimeout = -2, ///< Operation not completed within the timeout period. + osErrorResource = -3, ///< Resource not available. + osErrorParameter = -4, ///< Parameter error. + osErrorNoMemory = -5, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorISR = -6, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines. + osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osStatus_t; + + +/// \details Thread ID identifies the thread. +typedef void *osThreadId_t; + +/// \details Timer ID identifies the timer. +typedef void *osTimerId_t; + +/// \details Event Flags ID identifies the event flags. +typedef void *osEventFlagsId_t; + +/// \details Mutex ID identifies the mutex. +typedef void *osMutexId_t; + +/// \details Semaphore ID identifies the semaphore. +typedef void *osSemaphoreId_t; + +/// \details Memory Pool ID identifies the memory pool. +typedef void *osMemoryPoolId_t; + +/// \details Message Queue ID identifies the message queue. +typedef void *osMessageQueueId_t; + + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + + +/// Attributes structure for thread. +typedef struct { + const char *name; ///< name of the thread + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *stack_mem; ///< memory for stack + uint32_t stack_size; ///< size of stack + osPriority_t priority; ///< initial thread priority (default: osPriorityNormal) + TZ_ModuleId_t tz_module; ///< TrustZone module identifier + uint32_t reserved; ///< reserved (must be 0) +} osThreadAttr_t; + +/// Attributes structure for timer. +typedef struct { + const char *name; ///< name of the timer + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osTimerAttr_t; + +/// Attributes structure for event flags. +typedef struct { + const char *name; ///< name of the event flags + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osEventFlagsAttr_t; + +/// Attributes structure for mutex. +typedef struct { + const char *name; ///< name of the mutex + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osMutexAttr_t; + +/// Attributes structure for semaphore. +typedef struct { + const char *name; ///< name of the semaphore + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osSemaphoreAttr_t; + +/// Attributes structure for memory pool. +typedef struct { + const char *name; ///< name of the memory pool + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *mp_mem; ///< memory for data storage + uint32_t mp_size; ///< size of provided memory for data storage +} osMemoryPoolAttr_t; + +/// Attributes structure for message queue. +typedef struct { + const char *name; ///< name of the message queue + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *mq_mem; ///< memory for data storage + uint32_t mq_size; ///< size of provided memory for data storage +} osMessageQueueAttr_t; + + +// ==== Kernel Management Functions ==== + +/// Initialize the RTOS Kernel. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelInitialize (void); + +/// Get RTOS Kernel Information. +/// \param[out] version pointer to buffer for retrieving version information. +/// \param[out] id_buf pointer to buffer for retrieving kernel identification string. +/// \param[in] id_size size of buffer for kernel identification string. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size); + +/// Get the current RTOS Kernel state. +/// \return current RTOS Kernel state. +osKernelState_t osKernelGetState (void); + +/// Start the RTOS Kernel scheduler. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelStart (void); + +/// Lock the RTOS Kernel scheduler. +/// \return previous lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelLock (void); + +/// Unlock the RTOS Kernel scheduler. +/// \return previous lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelUnlock (void); + +/// Restore the RTOS Kernel scheduler lock state. +/// \param[in] lock lock state obtained by \ref osKernelLock or \ref osKernelUnlock. +/// \return new lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelRestoreLock (int32_t lock); + +/// Suspend the RTOS Kernel scheduler. +/// \return time in ticks, for how long the system can sleep or power-down. +uint32_t osKernelSuspend (void); + +/// Resume the RTOS Kernel scheduler. +/// \param[in] sleep_ticks time in ticks for how long the system was in sleep or power-down mode. +void osKernelResume (uint32_t sleep_ticks); + +/// Get the RTOS kernel tick count. +/// \return RTOS kernel current tick count. +uint32_t osKernelGetTickCount (void); + +/// Get the RTOS kernel tick frequency. +/// \return frequency of the kernel tick in hertz, i.e. kernel ticks per second. +uint32_t osKernelGetTickFreq (void); + +/// Get the RTOS kernel system timer count. +/// \return RTOS kernel current system timer count as 32-bit value. +uint32_t osKernelGetSysTimerCount (void); + +/// Get the RTOS kernel system timer frequency. +/// \return frequency of the system timer in hertz, i.e. timer ticks per second. +uint32_t osKernelGetSysTimerFreq (void); + + +// ==== Thread Management Functions ==== + +/// Create a thread and add it to Active Threads. +/// \param[in] func thread function. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \param[in] attr thread attributes; NULL: default values. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr); + +/// Get name of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return name as null-terminated string. +const char *osThreadGetName (osThreadId_t thread_id); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId_t osThreadGetId (void); + +/// Get current thread state of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return current thread state of the specified thread. +osThreadState_t osThreadGetState (osThreadId_t thread_id); + +/// Get stack size of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return stack size in bytes. +uint32_t osThreadGetStackSize (osThreadId_t thread_id); + +/// Get available stack space of a thread based on stack watermark recording during execution. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return remaining stack space in bytes. +uint32_t osThreadGetStackSpace (osThreadId_t thread_id); + +/// Change priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority); + +/// Get current priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return current priority value of the specified thread. +osPriority_t osThreadGetPriority (osThreadId_t thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadYield (void); + +/// Suspend execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadSuspend (osThreadId_t thread_id); + +/// Resume execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadResume (osThreadId_t thread_id); + +/// Detach a thread (thread storage can be reclaimed when thread terminates). +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadDetach (osThreadId_t thread_id); + +/// Wait for specified thread to terminate. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadJoin (osThreadId_t thread_id); + +/// Terminate execution of current running thread. +__NO_RETURN void osThreadExit (void); + +/// Terminate execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadTerminate (osThreadId_t thread_id); + +/// Get number of active threads. +/// \return number of active threads. +uint32_t osThreadGetCount (void); + +/// Enumerate active threads. +/// \param[out] thread_array pointer to array for retrieving thread IDs. +/// \param[in] array_items maximum number of items in array for retrieving thread IDs. +/// \return number of enumerated threads. +uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items); + + +// ==== Thread Flags Functions ==== + +/// Set the specified Thread Flags of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \param[in] flags specifies the flags of the thread that shall be set. +/// \return thread flags after setting or error code if highest bit set. +uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags); + +/// Clear the specified Thread Flags of current running thread. +/// \param[in] flags specifies the flags of the thread that shall be cleared. +/// \return thread flags before clearing or error code if highest bit set. +uint32_t osThreadFlagsClear (uint32_t flags); + +/// Get the current Thread Flags of current running thread. +/// \return current thread flags. +uint32_t osThreadFlagsGet (void); + +/// Wait for one or more Thread Flags of the current running thread to become signaled. +/// \param[in] flags specifies the flags to wait for. +/// \param[in] options specifies flags options (osFlagsXxxx). +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return thread flags before clearing or error code if highest bit set. +uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value +/// \return status code that indicates the execution status of the function. +osStatus_t osDelay (uint32_t ticks); + +/// Wait until specified time. +/// \param[in] ticks absolute time in ticks +/// \return status code that indicates the execution status of the function. +osStatus_t osDelayUntil (uint32_t ticks); + + +// ==== Timer Management Functions ==== + +/// Create and Initialize a timer. +/// \param[in] func function pointer to callback function. +/// \param[in] type \ref osTimerOnce for one-shot or \ref osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer callback function. +/// \param[in] attr timer attributes; NULL: default values. +/// \return timer ID for reference by other functions or NULL in case of error. +osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr); + +/// Get name of a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return name as null-terminated string. +const char *osTimerGetName (osTimerId_t timer_id); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks); + +/// Stop a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerStop (osTimerId_t timer_id); + +/// Check if a timer is running. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return 0 not running, 1 running. +uint32_t osTimerIsRunning (osTimerId_t timer_id); + +/// Delete a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerDelete (osTimerId_t timer_id); + + +// ==== Event Flags Management Functions ==== + +/// Create and Initialize an Event Flags object. +/// \param[in] attr event flags attributes; NULL: default values. +/// \return event flags ID for reference by other functions or NULL in case of error. +osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr); + +/// Get name of an Event Flags object. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return name as null-terminated string. +const char *osEventFlagsGetName (osEventFlagsId_t ef_id); + +/// Set the specified Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags that shall be set. +/// \return event flags after setting or error code if highest bit set. +uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags); + +/// Clear the specified Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags that shall be cleared. +/// \return event flags before clearing or error code if highest bit set. +uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags); + +/// Get the current Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return current event flags. +uint32_t osEventFlagsGet (osEventFlagsId_t ef_id); + +/// Wait for one or more Event Flags to become signaled. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags to wait for. +/// \param[in] options specifies flags options (osFlagsXxxx). +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event flags before clearing or error code if highest bit set. +uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout); + +/// Delete an Event Flags object. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id); + + +// ==== Mutex Management Functions ==== + +/// Create and Initialize a Mutex object. +/// \param[in] attr mutex attributes; NULL: default values. +/// \return mutex ID for reference by other functions or NULL in case of error. +osMutexId_t osMutexNew (const osMutexAttr_t *attr); + +/// Get name of a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return name as null-terminated string. +const char *osMutexGetName (osMutexId_t mutex_id); + +/// Acquire a Mutex or timeout if it is locked. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout); + +/// Release a Mutex that was acquired by \ref osMutexAcquire. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexRelease (osMutexId_t mutex_id); + +/// Get Thread which owns a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return thread ID of owner thread or NULL when mutex was not acquired. +osThreadId_t osMutexGetOwner (osMutexId_t mutex_id); + +/// Delete a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexDelete (osMutexId_t mutex_id); + + +// ==== Semaphore Management Functions ==== + +/// Create and Initialize a Semaphore object. +/// \param[in] max_count maximum number of available tokens. +/// \param[in] initial_count initial number of available tokens. +/// \param[in] attr semaphore attributes; NULL: default values. +/// \return semaphore ID for reference by other functions or NULL in case of error. +osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr); + +/// Get name of a Semaphore object. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return name as null-terminated string. +const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id); + +/// Acquire a Semaphore token or timeout if no tokens are available. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout); + +/// Release a Semaphore token up to the initial maximum count. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id); + +/// Get current Semaphore token count. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return number of tokens available. +uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id); + +/// Delete a Semaphore object. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id); + + +// ==== Memory Pool Management Functions ==== + +/// Create and Initialize a Memory Pool object. +/// \param[in] block_count maximum number of memory blocks in memory pool. +/// \param[in] block_size memory block size in bytes. +/// \param[in] attr memory pool attributes; NULL: default values. +/// \return memory pool ID for reference by other functions or NULL in case of error. +osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr); + +/// Get name of a Memory Pool object. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return name as null-terminated string. +const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id); + +/// Allocate a memory block from a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return address of the allocated memory block or NULL in case of no memory is available. +void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout); + +/// Return an allocated memory block back to a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \param[in] block address of the allocated memory block to be returned to the memory pool. +/// \return status code that indicates the execution status of the function. +osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block); + +/// Get maximum number of memory blocks in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return maximum number of memory blocks. +uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id); + +/// Get memory block size in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return memory block size in bytes. +uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id); + +/// Get number of memory blocks used in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return number of memory blocks used. +uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id); + +/// Get number of memory blocks available in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return number of memory blocks available. +uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id); + +/// Delete a Memory Pool object. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id); + + +// ==== Message Queue Management Functions ==== + +/// Create and Initialize a Message Queue object. +/// \param[in] msg_count maximum number of messages in queue. +/// \param[in] msg_size maximum message size in bytes. +/// \param[in] attr message queue attributes; NULL: default values. +/// \return message queue ID for reference by other functions or NULL in case of error. +osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr); + +/// Get name of a Message Queue object. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return name as null-terminated string. +const char *osMessageQueueGetName (osMessageQueueId_t mq_id); + +/// Put a Message into a Queue or timeout if Queue is full. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \param[in] msg_ptr pointer to buffer with message to put into a queue. +/// \param[in] msg_prio message priority. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout); + +/// Get a Message from a Queue or timeout if Queue is empty. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \param[out] msg_ptr pointer to buffer for message to get from a queue. +/// \param[out] msg_prio pointer to buffer for message priority or NULL. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout); + +/// Get maximum number of messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return maximum number of messages. +uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id); + +/// Get maximum message size in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return maximum message size in bytes. +uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id); + +/// Get number of queued messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return number of queued messages. +uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id); + +/// Get number of available slots for messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return number of available slots for messages. +uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id); + +/// Reset a Message Queue to initial empty state. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id); + +/// Delete a Message Queue object. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id); + + +#ifdef __cplusplus +} +#endif + +#endif // CMSIS_OS2_H_ diff --git a/benchmark/interface/Drivers/CMSIS/RTOS2/Include/os_tick.h b/benchmark/interface/Drivers/CMSIS/RTOS2/Include/os_tick.h new file mode 100644 index 00000000..3cfd8954 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/RTOS2/Include/os_tick.h @@ -0,0 +1,80 @@ +/**************************************************************************//** + * @file os_tick.h + * @brief CMSIS OS Tick header file + * @version V1.0.2 + * @date 19. March 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef OS_TICK_H +#define OS_TICK_H + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +/// IRQ Handler. +#ifndef IRQHANDLER_T +#define IRQHANDLER_T +typedef void (*IRQHandler_t) (void); +#endif + +/// Setup OS Tick timer to generate periodic RTOS Kernel Ticks +/// \param[in] freq tick frequency in Hz +/// \param[in] handler tick IRQ handler +/// \return 0 on success, -1 on error. +int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler); + +/// Enable OS Tick timer interrupt +void OS_Tick_Enable (void); + +/// Disable OS Tick timer interrupt +void OS_Tick_Disable (void); + +/// Acknowledge execution of OS Tick timer interrupt +void OS_Tick_AcknowledgeIRQ (void); + +/// Get OS Tick timer IRQ number +/// \return OS Tick IRQ number +int32_t OS_Tick_GetIRQn (void); + +/// Get OS Tick timer clock frequency +/// \return OS Tick timer clock frequency in Hz +uint32_t OS_Tick_GetClock (void); + +/// Get OS Tick timer interval reload value +/// \return OS Tick timer interval reload value +uint32_t OS_Tick_GetInterval (void); + +/// Get OS Tick timer counter value +/// \return OS Tick timer counter value +uint32_t OS_Tick_GetCount (void); + +/// Get OS Tick timer overflow status +/// \return OS Tick overflow status (1 - overflow, 0 - no overflow). +uint32_t OS_Tick_GetOverflow (void); + +#ifdef __cplusplus +} +#endif + +#endif /* OS_TICK_H */ diff --git a/benchmark/interface/Drivers/CMSIS/RTOS2/Source/os_systick.c b/benchmark/interface/Drivers/CMSIS/RTOS2/Source/os_systick.c new file mode 100644 index 00000000..3cce53c5 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/RTOS2/Source/os_systick.c @@ -0,0 +1,133 @@ +/**************************************************************************//** + * @file os_systick.c + * @brief CMSIS OS Tick SysTick implementation + * @version V1.0.3 + * @date 19. March 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "os_tick.h" + +//lint -emacro((923,9078),SCB,SysTick) "cast from unsigned long to pointer" +#include "RTE_Components.h" +#include CMSIS_device_header + +#ifdef SysTick + +#ifndef SYSTICK_IRQ_PRIORITY +#define SYSTICK_IRQ_PRIORITY 0xFFU +#endif + +static uint8_t PendST __attribute__((section(".bss.os"))); + +// Setup OS Tick. +__WEAK int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { + uint32_t load; + (void)handler; + + if (freq == 0U) { + //lint -e{904} "Return statement before end of function" + return (-1); + } + + load = (SystemCoreClock / freq) - 1U; + if (load > 0x00FFFFFFU) { + //lint -e{904} "Return statement before end of function" + return (-1); + } + + // Set SysTick Interrupt Priority +#if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)) || \ + (defined(__CORTEX_M) && (__CORTEX_M == 7U))) + SCB->SHPR[11] = SYSTICK_IRQ_PRIORITY; +#elif (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + SCB->SHPR[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24); +#elif ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0))) + SCB->SHP[11] = SYSTICK_IRQ_PRIORITY; +#elif (defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) + SCB->SHP[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24); +#else +#error "Unknown ARM Core!" +#endif + + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk; + SysTick->LOAD = load; + SysTick->VAL = 0U; + + PendST = 0U; + + return (0); +} + +/// Enable OS Tick. +__WEAK void OS_Tick_Enable (void) { + + if (PendST != 0U) { + PendST = 0U; + SCB->ICSR = SCB_ICSR_PENDSTSET_Msk; + } + + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; +} + +/// Disable OS Tick. +__WEAK void OS_Tick_Disable (void) { + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + + if ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0U) { + SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk; + PendST = 1U; + } +} + +// Acknowledge OS Tick IRQ. +__WEAK void OS_Tick_AcknowledgeIRQ (void) { + (void)SysTick->CTRL; +} + +// Get OS Tick IRQ number. +__WEAK int32_t OS_Tick_GetIRQn (void) { + return ((int32_t)SysTick_IRQn); +} + +// Get OS Tick clock. +__WEAK uint32_t OS_Tick_GetClock (void) { + return (SystemCoreClock); +} + +// Get OS Tick interval. +__WEAK uint32_t OS_Tick_GetInterval (void) { + return (SysTick->LOAD + 1U); +} + +// Get OS Tick count value. +__WEAK uint32_t OS_Tick_GetCount (void) { + uint32_t load = SysTick->LOAD; + return (load - SysTick->VAL); +} + +// Get OS Tick overflow status. +__WEAK uint32_t OS_Tick_GetOverflow (void) { + return ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) >> SCB_ICSR_PENDSTSET_Pos); +} + +#endif // SysTick diff --git a/benchmark/interface/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c b/benchmark/interface/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c new file mode 100644 index 00000000..22cfa930 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c @@ -0,0 +1,187 @@ +/**************************************************************************//** + * @file os_tick_gtim.c + * @brief CMSIS OS Tick implementation for Generic Timer + * @version V1.0.1 + * @date 24. November 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "os_tick.h" +#include "irq_ctrl.h" + +#include "RTE_Components.h" +#include CMSIS_device_header + +#ifndef GTIM_IRQ_PRIORITY +#define GTIM_IRQ_PRIORITY 0xFFU +#endif + +#ifndef GTIM_IRQ_NUM +#define GTIM_IRQ_NUM SecurePhyTimer_IRQn +#endif + +// Timer interrupt pending flag +static uint8_t GTIM_PendIRQ; + +// Timer tick frequency +static uint32_t GTIM_Clock; + +// Timer load value +static uint32_t GTIM_Load; + +// Setup OS Tick. +int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { + uint32_t prio, bits; + + if (freq == 0U) { + return (-1); + } + + GTIM_PendIRQ = 0U; + + // Get timer clock +#ifdef SCTR_BASE + GTIM_Clock = *(uint32_t*)(SCTR_BASE+0x20); +#else + // FVP REFCLK CNTControl 100MHz + GTIM_Clock = 100000000UL; +#endif + + PL1_SetCounterFrequency(GTIM_Clock); + + // Calculate load value + GTIM_Load = (GTIM_Clock / freq) - 1U; + + // Disable Generic Timer and set load value + PL1_SetControl(0U); + PL1_SetLoadValue(GTIM_Load); + + // Disable corresponding IRQ + IRQ_Disable(GTIM_IRQ_NUM); + IRQ_ClearPending(GTIM_IRQ_NUM); + + // Determine number of implemented priority bits + IRQ_SetPriority(GTIM_IRQ_NUM, 0xFFU); + + prio = IRQ_GetPriority(GTIM_IRQ_NUM); + + // At least bits [7:4] must be implemented + if ((prio & 0xF0U) == 0U) { + return (-1); + } + + for (bits = 0; bits < 4; bits++) { + if ((prio & 0x01) != 0) { + break; + } + prio >>= 1; + } + + // Adjust configured priority to the number of implemented priority bits + prio = (GTIM_IRQ_PRIORITY << bits) & 0xFFUL; + + // Set Private Timer interrupt priority + IRQ_SetPriority(GTIM_IRQ_NUM, prio-1U); + + // Set edge-triggered IRQ + IRQ_SetMode(GTIM_IRQ_NUM, IRQ_MODE_TRIG_EDGE); + + // Register tick interrupt handler function + IRQ_SetHandler(GTIM_IRQ_NUM, handler); + + // Enable corresponding interrupt + IRQ_Enable(GTIM_IRQ_NUM); + + // Enable system counter and timer control +#ifdef SCTR_BASE + *(uint32_t*)SCTR_BASE |= 3U; +#endif + + // Enable timer control + PL1_SetControl(1U); + + return (0); +} + +/// Enable OS Tick. +void OS_Tick_Enable (void) { + uint32_t ctrl; + + // Set pending interrupt if flag set + if (GTIM_PendIRQ != 0U) { + GTIM_PendIRQ = 0U; + IRQ_SetPending (GTIM_IRQ_NUM); + } + + // Start the Private Timer + ctrl = PL1_GetControl(); + // Set bit: Timer enable + ctrl |= 1U; + PL1_SetControl(ctrl); +} + +/// Disable OS Tick. +void OS_Tick_Disable (void) { + uint32_t ctrl; + + // Stop the Private Timer + ctrl = PL1_GetControl(); + // Clear bit: Timer enable + ctrl &= ~1U; + PL1_SetControl(ctrl); + + // Remember pending interrupt flag + if (IRQ_GetPending(GTIM_IRQ_NUM) != 0) { + IRQ_ClearPending(GTIM_IRQ_NUM); + GTIM_PendIRQ = 1U; + } +} + +// Acknowledge OS Tick IRQ. +void OS_Tick_AcknowledgeIRQ (void) { + IRQ_ClearPending (GTIM_IRQ_NUM); + PL1_SetLoadValue(GTIM_Load); +} + +// Get OS Tick IRQ number. +int32_t OS_Tick_GetIRQn (void) { + return (GTIM_IRQ_NUM); +} + +// Get OS Tick clock. +uint32_t OS_Tick_GetClock (void) { + return (GTIM_Clock); +} + +// Get OS Tick interval. +uint32_t OS_Tick_GetInterval (void) { + return (GTIM_Load + 1U); +} + +// Get OS Tick count value. +uint32_t OS_Tick_GetCount (void) { + return (GTIM_Load - PL1_GetCurrentValue()); +} + +// Get OS Tick overflow status. +uint32_t OS_Tick_GetOverflow (void) { + CNTP_CTL_Type cntp_ctl; + cntp_ctl.w = PL1_GetControl(); + return (cntp_ctl.b.ISTATUS); +} diff --git a/benchmark/interface/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c b/benchmark/interface/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c new file mode 100644 index 00000000..e75ac3a3 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c @@ -0,0 +1,165 @@ +/**************************************************************************//** + * @file os_tick_ptim.c + * @brief CMSIS OS Tick implementation for Private Timer + * @version V1.0.2 + * @date 02. March 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "RTE_Components.h" +#include CMSIS_device_header + +#if defined(PTIM) + +#include "os_tick.h" +#include "irq_ctrl.h" + +#ifndef PTIM_IRQ_PRIORITY +#define PTIM_IRQ_PRIORITY 0xFFU +#endif + +static uint8_t PTIM_PendIRQ; // Timer interrupt pending flag + +// Setup OS Tick. +int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { + uint32_t load; + uint32_t prio; + uint32_t bits; + + if (freq == 0U) { + return (-1); + } + + PTIM_PendIRQ = 0U; + + // Private Timer runs with the system frequency + load = (SystemCoreClock / freq) - 1U; + + // Disable Private Timer and set load value + PTIM_SetControl (0U); + PTIM_SetLoadValue (load); + + // Disable corresponding IRQ + IRQ_Disable (PrivTimer_IRQn); + IRQ_ClearPending(PrivTimer_IRQn); + + // Determine number of implemented priority bits + IRQ_SetPriority (PrivTimer_IRQn, 0xFFU); + + prio = IRQ_GetPriority (PrivTimer_IRQn); + + // At least bits [7:4] must be implemented + if ((prio & 0xF0U) == 0U) { + return (-1); + } + + for (bits = 0; bits < 4; bits++) { + if ((prio & 0x01) != 0) { + break; + } + prio >>= 1; + } + + // Adjust configured priority to the number of implemented priority bits + prio = (PTIM_IRQ_PRIORITY << bits) & 0xFFUL; + + // Set Private Timer interrupt priority + IRQ_SetPriority(PrivTimer_IRQn, prio-1U); + + // Set edge-triggered IRQ + IRQ_SetMode(PrivTimer_IRQn, IRQ_MODE_TRIG_EDGE); + + // Register tick interrupt handler function + IRQ_SetHandler(PrivTimer_IRQn, handler); + + // Enable corresponding interrupt + IRQ_Enable (PrivTimer_IRQn); + + // Set bits: IRQ enable and Auto reload + PTIM_SetControl (0x06U); + + return (0); +} + +/// Enable OS Tick. +void OS_Tick_Enable (void) { + uint32_t ctrl; + + // Set pending interrupt if flag set + if (PTIM_PendIRQ != 0U) { + PTIM_PendIRQ = 0U; + IRQ_SetPending (PrivTimer_IRQn); + } + + // Start the Private Timer + ctrl = PTIM_GetControl(); + // Set bit: Timer enable + ctrl |= 1U; + PTIM_SetControl (ctrl); +} + +/// Disable OS Tick. +void OS_Tick_Disable (void) { + uint32_t ctrl; + + // Stop the Private Timer + ctrl = PTIM_GetControl(); + // Clear bit: Timer enable + ctrl &= ~1U; + PTIM_SetControl (ctrl); + + // Remember pending interrupt flag + if (IRQ_GetPending(PrivTimer_IRQn) != 0) { + IRQ_ClearPending (PrivTimer_IRQn); + PTIM_PendIRQ = 1U; + } +} + +// Acknowledge OS Tick IRQ. +void OS_Tick_AcknowledgeIRQ (void) { + PTIM_ClearEventFlag(); +} + +// Get OS Tick IRQ number. +int32_t OS_Tick_GetIRQn (void) { + return (PrivTimer_IRQn); +} + +// Get OS Tick clock. +uint32_t OS_Tick_GetClock (void) { + return (SystemCoreClock); +} + +// Get OS Tick interval. +uint32_t OS_Tick_GetInterval (void) { + return (PTIM_GetLoadValue() + 1U); +} + +// Get OS Tick count value. +uint32_t OS_Tick_GetCount (void) { + uint32_t load = PTIM_GetLoadValue(); + return (load - PTIM_GetCurrentValue()); +} + +// Get OS Tick overflow status. +uint32_t OS_Tick_GetOverflow (void) { + return (PTIM->ISR & 1); +} + +#endif // PTIM diff --git a/benchmark/interface/Drivers/CMSIS/RTOS2/Template/cmsis_os.h b/benchmark/interface/Drivers/CMSIS/RTOS2/Template/cmsis_os.h new file mode 100644 index 00000000..376dbf70 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/RTOS2/Template/cmsis_os.h @@ -0,0 +1,922 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 18. June 2018 + * $Revision: V2.1.3 + * + * Project: CMSIS-RTOS API + * Title: cmsis_os.h template header file + * + * Version 0.02 + * Initial Proposal Phase + * Version 0.03 + * osKernelStart added, optional feature: main started as thread + * osSemaphores have standard behavior + * osTimerCreate does not start the timer, added osTimerStart + * osThreadPass is renamed to osThreadYield + * Version 1.01 + * Support for C++ interface + * - const attribute removed from the osXxxxDef_t typedefs + * - const attribute added to the osXxxxDef macros + * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete + * Added: osKernelInitialize + * Version 1.02 + * Control functions for short timeouts in microsecond resolution: + * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec + * Removed: osSignalGet + * Version 2.0.0 + * OS objects creation without macros (dynamic creation and resource allocation): + * - added: osXxxxNew functions which replace osXxxxCreate + * - added: osXxxxAttr_t structures + * - deprecated: osXxxxCreate functions, osXxxxDef_t structures + * - deprecated: osXxxxDef and osXxxx macros + * osStatus codes simplified and renamed to osStatus_t + * osEvent return structure deprecated + * Kernel: + * - added: osKernelInfo_t and osKernelGetInfo + * - added: osKernelState_t and osKernelGetState (replaces osKernelRunning) + * - added: osKernelLock, osKernelUnlock + * - added: osKernelSuspend, osKernelResume + * - added: osKernelGetTickCount, osKernelGetTickFreq + * - renamed osKernelSysTick to osKernelGetSysTimerCount + * - replaced osKernelSysTickFrequency with osKernelGetSysTimerFreq + * - deprecated osKernelSysTickMicroSec + * Thread: + * - extended number of thread priorities + * - renamed osPrioriry to osPrioriry_t + * - replaced osThreadCreate with osThreadNew + * - added: osThreadGetName + * - added: osThreadState_t and osThreadGetState + * - added: osThreadGetStackSize, osThreadGetStackSpace + * - added: osThreadSuspend, osThreadResume + * - added: osThreadJoin, osThreadDetach, osThreadExit + * - added: osThreadGetCount, osThreadEnumerate + * - added: Thread Flags (moved from Signals) + * Signals: + * - renamed osSignals to osThreadFlags (moved to Thread Flags) + * - changed return value of Set/Clear/Wait functions + * - Clear function limited to current running thread + * - extended Wait function (options) + * - added: osThreadFlagsGet + * Event Flags: + * - added new independent object for handling Event Flags + * Delay and Wait functions: + * - added: osDelayUntil + * - deprecated: osWait + * Timer: + * - replaced osTimerCreate with osTimerNew + * - added: osTimerGetName, osTimerIsRunning + * Mutex: + * - extended: attributes (Recursive, Priority Inherit, Robust) + * - replaced osMutexCreate with osMutexNew + * - renamed osMutexWait to osMutexAcquire + * - added: osMutexGetName, osMutexGetOwner + * Semaphore: + * - extended: maximum and initial token count + * - replaced osSemaphoreCreate with osSemaphoreNew + * - renamed osSemaphoreWait to osSemaphoreAcquire (changed return value) + * - added: osSemaphoreGetName, osSemaphoreGetCount + * Memory Pool: + * - using osMemoryPool prefix instead of osPool + * - replaced osPoolCreate with osMemoryPoolNew + * - extended osMemoryPoolAlloc (timeout) + * - added: osMemoryPoolGetName + * - added: osMemoryPoolGetCapacity, osMemoryPoolGetBlockSize + * - added: osMemoryPoolGetCount, osMemoryPoolGetSpace + * - added: osMemoryPoolDelete + * - deprecated: osPoolCAlloc + * Message Queue: + * - extended: fixed size message instead of a single 32-bit value + * - using osMessageQueue prefix instead of osMessage + * - replaced osMessageCreate with osMessageQueueNew + * - updated: osMessageQueuePut, osMessageQueueGet + * - added: osMessageQueueGetName + * - added: osMessageQueueGetCapacity, osMessageQueueGetMsgSize + * - added: osMessageQueueGetCount, osMessageQueueGetSpace + * - added: osMessageQueueReset, osMessageQueueDelete + * Mail Queue: + * - deprecated (superseded by extended Message Queue functionality) + * Version 2.1.0 + * Support for critical and uncritical sections (nesting safe): + * - updated: osKernelLock, osKernelUnlock + * - added: osKernelRestoreLock + * Updated Thread and Event Flags: + * - changed flags parameter and return type from int32_t to uint32_t + * Version 2.1.1 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetTickCount, osKernelGetTickFreq + * Changed Kernel Tick type to uint32_t: + * - updated: osKernelGetTickCount, osDelayUntil + * Version 2.1.2 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetInfo, osKernelGetState + * Version 2.1.3 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osThreadGetId + *---------------------------------------------------------------------------*/ + +#ifndef CMSIS_OS_H_ +#define CMSIS_OS_H_ + +/// \b osCMSIS identifies the CMSIS-RTOS API version. +#define osCMSIS 0x20001U ///< API version (main[31:16].sub[15:0]) + +/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number. +#define osCMSIS_KERNEL 0x10000U ///< RTOS identification and version (main[31:16].sub[15:0]) + +/// \note CAN BE CHANGED: \b osKernelSystemId identifies the underlying RTOS kernel. +#define osKernelSystemId "KERNEL V1.0" ///< RTOS identification string + +/// \note CAN BE CHANGED: \b osFeature_xxx identifies RTOS features. +#define osFeature_MainThread 0 ///< main thread 1=main can be thread, 0=not available +#define osFeature_Signals 16U ///< maximum number of Signal Flags available per thread +#define osFeature_Semaphore 65535U ///< maximum count for \ref osSemaphoreCreate function +#define osFeature_Wait 0 ///< osWait function: 1=available, 0=not available +#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available +#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available +#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available +#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available + +#if (osCMSIS >= 0x20000U) +#include "cmsis_os2.h" +#else +#include +#include +#endif + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumerations, structures, defines ==== + +/// Priority values. +#if (osCMSIS < 0x20000U) +typedef enum { + osPriorityIdle = -3, ///< Priority: idle (lowest) + osPriorityLow = -2, ///< Priority: low + osPriorityBelowNormal = -1, ///< Priority: below normal + osPriorityNormal = 0, ///< Priority: normal (default) + osPriorityAboveNormal = +1, ///< Priority: above normal + osPriorityHigh = +2, ///< Priority: high + osPriorityRealtime = +3, ///< Priority: realtime (highest) + osPriorityError = 0x84, ///< System cannot determine priority or illegal priority. + osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osPriority; +#else +#define osPriority osPriority_t +#endif + +/// Entry point of a thread. +typedef void (*os_pthread) (void const *argument); + +/// Entry point of a timer call back function. +typedef void (*os_ptimer) (void const *argument); + +/// Timer type. +#if (osCMSIS < 0x20000U) +typedef enum { + osTimerOnce = 0, ///< One-shot timer. + osTimerPeriodic = 1 ///< Repeating timer. +} os_timer_type; +#else +#define os_timer_type osTimerType_t +#endif + +/// Timeout value. +#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value. + +/// Status code values returned by CMSIS-RTOS functions. +#if (osCMSIS < 0x20000U) +typedef enum { + osOK = 0, ///< Function completed; no error or event occurred. + osEventSignal = 0x08, ///< Function completed; signal event occurred. + osEventMessage = 0x10, ///< Function completed; message event occurred. + osEventMail = 0x20, ///< Function completed; mail event occurred. + osEventTimeout = 0x40, ///< Function completed; timeout occurred. + osErrorParameter = 0x80, ///< Parameter error: a mandatory parameter was missing or specified an incorrect object. + osErrorResource = 0x81, ///< Resource not available: a specified resource was not available. + osErrorTimeoutResource = 0xC1, ///< Resource not available within given time: a specified resource was not available within the timeout period. + osErrorISR = 0x82, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines. + osErrorISRRecursive = 0x83, ///< Function called multiple times from ISR with same object. + osErrorPriority = 0x84, ///< System cannot determine priority or thread has illegal priority. + osErrorNoMemory = 0x85, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorValue = 0x86, ///< Value of a parameter is out of range. + osErrorOS = 0xFF, ///< Unspecified RTOS error: run-time error but no other error message fits. + osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osStatus; +#else +typedef int32_t osStatus; +#define osEventSignal (0x08) +#define osEventMessage (0x10) +#define osEventMail (0x20) +#define osEventTimeout (0x40) +#define osErrorOS osError +#define osErrorTimeoutResource osErrorTimeout +#define osErrorISRRecursive (-126) +#define osErrorValue (-127) +#define osErrorPriority (-128) +#endif + + +// >>> the following data type definitions may be adapted towards a specific RTOS + +/// Thread ID identifies the thread. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef void *osThreadId; +#else +#define osThreadId osThreadId_t +#endif + +/// Timer ID identifies the timer. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef void *osTimerId; +#else +#define osTimerId osTimerId_t +#endif + +/// Mutex ID identifies the mutex. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef void *osMutexId; +#else +#define osMutexId osMutexId_t +#endif + +/// Semaphore ID identifies the semaphore. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef void *osSemaphoreId; +#else +#define osSemaphoreId osSemaphoreId_t +#endif + +/// Pool ID identifies the memory pool. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +typedef void *osPoolId; + +/// Message ID identifies the message queue. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +typedef void *osMessageQId; + +/// Mail ID identifies the mail queue. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +typedef void *osMailQId; + + +/// Thread Definition structure contains startup information of a thread. +/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osPriority tpriority; ///< initial thread priority + uint32_t instances; ///< maximum number of instances of that thread function + uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size +} osThreadDef_t; +#else +typedef struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osThreadAttr_t attr; ///< thread attributes +} osThreadDef_t; +#endif + +/// Timer Definition structure contains timer parameters. +/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function +} osTimerDef_t; +#else +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function + osTimerAttr_t attr; ///< timer attributes +} osTimerDef_t; +#endif + +/// Mutex Definition structure contains setup information for a mutex. +/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_mutex_def { + uint32_t dummy; ///< dummy value +} osMutexDef_t; +#else +#define osMutexDef_t osMutexAttr_t +#endif + +/// Semaphore Definition structure contains setup information for a semaphore. +/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_semaphore_def { + uint32_t dummy; ///< dummy value +} osSemaphoreDef_t; +#else +#define osSemaphoreDef_t osSemaphoreAttr_t +#endif + +/// Definition structure for memory block allocation. +/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + void *pool; ///< pointer to memory for pool +} osPoolDef_t; +#else +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + osMemoryPoolAttr_t attr; ///< memory pool attributes +} osPoolDef_t; +#endif + +/// Definition structure for message queue. +/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + void *pool; ///< memory array for messages +} osMessageQDef_t; +#else +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + osMessageQueueAttr_t attr; ///< message queue attributes +} osMessageQDef_t; +#endif + +/// Definition structure for mail queue. +/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for mail +} osMailQDef_t; +#else +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *mail; ///< pointer to mail + osMemoryPoolAttr_t mp_attr; ///< memory pool attributes + osMessageQueueAttr_t mq_attr; ///< message queue attributes +} osMailQDef_t; +#endif + + +/// Event structure contains detailed information about an event. +typedef struct { + osStatus status; ///< status code: event or error information + union { + uint32_t v; ///< message as 32-bit value + void *p; ///< message or mail as void pointer + int32_t signals; ///< signal flags + } value; ///< event value + union { + osMailQId mail_id; ///< mail id obtained by \ref osMailCreate + osMessageQId message_id; ///< message id obtained by \ref osMessageCreate + } def; ///< event definition +} osEvent; + + +// ==== Kernel Management Functions ==== + +/// Initialize the RTOS Kernel for creating objects. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osKernelInitialize (void); +#endif + +/// Start the RTOS Kernel scheduler. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osKernelStart (void); +#endif + +/// Check if the RTOS kernel is already started. +/// \return 0 RTOS is not started, 1 RTOS is started. +#if (osCMSIS < 0x20000U) +int32_t osKernelRunning(void); +#endif + +#if (defined(osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available + +/// Get the RTOS kernel system timer counter. +/// \return RTOS kernel system timer as 32-bit value +#if (osCMSIS < 0x20000U) +uint32_t osKernelSysTick (void); +#else +#define osKernelSysTick osKernelGetSysTimerCount +#endif + +/// The RTOS kernel system timer frequency in Hz. +/// \note Reflects the system timer setting and is typically defined in a configuration file. +#if (osCMSIS < 0x20000U) +#define osKernelSysTickFrequency 100000000 +#endif + +/// Convert a microseconds value to a RTOS kernel system timer value. +/// \param microsec time value in microseconds. +/// \return time value normalized to the \ref osKernelSysTickFrequency +#if (osCMSIS < 0x20000U) +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000) +#else +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * osKernelGetSysTimerFreq()) / 1000000) +#endif + +#endif // System Timer available + + +// ==== Thread Management Functions ==== + +/// Create a Thread Definition with function, priority, and stack requirements. +/// \param name name of the thread function. +/// \param priority initial priority of the thread function. +/// \param instances number of possible thread instances. +/// \param stacksz stack size (in bytes) requirements for the thread function. +/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osThreadDef(name, priority, instances, stacksz) \ +extern const osThreadDef_t os_thread_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osThreadDef(name, priority, instances, stacksz) \ +const osThreadDef_t os_thread_def_##name = \ +{ (name), (priority), (instances), (stacksz) } +#else +#define osThreadDef(name, priority, instances, stacksz) \ +const osThreadDef_t os_thread_def_##name = \ +{ (name), \ + { NULL, osThreadDetached, NULL, 0U, NULL, 8*((stacksz+7)/8), (priority), 0U, 0U } } +#endif +#endif + +/// Access a Thread definition. +/// \param name name of the thread definition object. +/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osThread(name) \ +&os_thread_def_##name + +/// Create a thread and add it to Active Threads and set it to state READY. +/// \param[in] thread_def thread definition referenced with \ref osThread. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +#if (osCMSIS < 0x20000U) +osThreadId osThreadGetId (void); +#endif + +/// Change priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); +#endif + +/// Get current priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return current priority value of the specified thread. +#if (osCMSIS < 0x20000U) +osPriority osThreadGetPriority (osThreadId thread_id); +#endif + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osThreadYield (void); +#endif + +/// Terminate execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osThreadTerminate (osThreadId thread_id); +#endif + + +// ==== Signal Management ==== + +/// Set the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that should be set. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +int32_t osSignalSet (osThreadId thread_id, int32_t signals); + +/// Clear the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that shall be cleared. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR. +int32_t osSignalClear (osThreadId thread_id, int32_t signals); + +/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event flag information or error code. +osEvent osSignalWait (int32_t signals, uint32_t millisec); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osDelay (uint32_t millisec); +#endif + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available + +/// Wait for Signal, Message, Mail, or Timeout. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return event that contains signal, message, or mail information or error code. +osEvent osWait (uint32_t millisec); + +#endif // Generic Wait available + + +// ==== Timer Management Functions ==== + +/// Define a Timer object. +/// \param name name of the timer object. +/// \param function name of the timer call back function. +/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osTimerDef(name, function) \ +extern const osTimerDef_t os_timer_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osTimerDef(name, function) \ +const osTimerDef_t os_timer_def_##name = { (function) } +#else +#define osTimerDef(name, function) \ +const osTimerDef_t os_timer_def_##name = \ +{ (function), { NULL, 0U, NULL, 0U } } +#endif +#endif + +/// Access a Timer definition. +/// \param name name of the timer object. +/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osTimer(name) \ +&os_timer_def_##name + +/// Create and Initialize a timer. +/// \param[in] timer_def timer object referenced with \ref osTimer. +/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer call back function. +/// \return timer ID for reference by other functions or NULL in case of error. +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); +#endif + +/// Stop a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osTimerStop (osTimerId timer_id); +#endif + +/// Delete a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osTimerDelete (osTimerId timer_id); +#endif + + +// ==== Mutex Management Functions ==== + +/// Define a Mutex. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMutexDef(name) \ +extern const osMutexDef_t os_mutex_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osMutexDef(name) \ +const osMutexDef_t os_mutex_def_##name = { 0 } +#else +#define osMutexDef(name) \ +const osMutexDef_t os_mutex_def_##name = \ +{ NULL, osMutexRecursive | osMutexPrioInherit | osMutexRobust, NULL, 0U } +#endif +#endif + +/// Access a Mutex definition. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMutex(name) \ +&os_mutex_def_##name + +/// Create and Initialize a Mutex object. +/// \param[in] mutex_def mutex definition referenced with \ref osMutex. +/// \return mutex ID for reference by other functions or NULL in case of error. +osMutexId osMutexCreate (const osMutexDef_t *mutex_def); + +/// Wait until a Mutex becomes available. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); +#else +#define osMutexWait osMutexAcquire +#endif + +/// Release a Mutex that was obtained by \ref osMutexWait. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osMutexRelease (osMutexId mutex_id); +#endif + +/// Delete a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osMutexDelete (osMutexId mutex_id); +#endif + + +// ==== Semaphore Management Functions ==== + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) // Semaphore available + +/// Define a Semaphore object. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osSemaphoreDef(name) \ +extern const osSemaphoreDef_t os_semaphore_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osSemaphoreDef(name) \ +const osSemaphoreDef_t os_semaphore_def_##name = { 0 } +#else +#define osSemaphoreDef(name) \ +const osSemaphoreDef_t os_semaphore_def_##name = \ +{ NULL, 0U, NULL, 0U } +#endif +#endif + +/// Access a Semaphore definition. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osSemaphore(name) \ +&os_semaphore_def_##name + +/// Create and Initialize a Semaphore object. +/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. +/// \param[in] count maximum and initial number of available tokens. +/// \return semaphore ID for reference by other functions or NULL in case of error. +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count); + +/// Wait until a Semaphore token becomes available. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return number of available tokens, or -1 in case of incorrect parameters. +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); + +/// Release a Semaphore token. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); +#endif + +/// Delete a Semaphore object. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id); +#endif + +#endif // Semaphore available + + +// ==== Memory Pool Management Functions ==== + +#if (defined(osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool available + +/// \brief Define a Memory Pool. +/// \param name name of the memory pool. +/// \param no maximum number of blocks (objects) in the memory pool. +/// \param type data type of a single block (object). +/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osPoolDef(name, no, type) \ +extern const osPoolDef_t os_pool_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osPoolDef(name, no, type) \ +const osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), NULL } +#else +#define osPoolDef(name, no, type) \ +const osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), { NULL, 0U, NULL, 0U, NULL, 0U } } +#endif +#endif + +/// \brief Access a Memory Pool definition. +/// \param name name of the memory pool +/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osPool(name) \ +&os_pool_def_##name + +/// Create and Initialize a Memory Pool object. +/// \param[in] pool_def memory pool definition referenced with \ref osPool. +/// \return memory pool ID for reference by other functions or NULL in case of error. +osPoolId osPoolCreate (const osPoolDef_t *pool_def); + +/// Allocate a memory block from a Memory Pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +void *osPoolAlloc (osPoolId pool_id); + +/// Allocate a memory block from a Memory Pool and set memory block to zero. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +void *osPoolCAlloc (osPoolId pool_id); + +/// Return an allocated memory block back to a Memory Pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \param[in] block address of the allocated memory block to be returned to the memory pool. +/// \return status code that indicates the execution status of the function. +osStatus osPoolFree (osPoolId pool_id, void *block); + +#endif // Memory Pool available + + +// ==== Message Queue Management Functions ==== + +#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queue available + +/// \brief Create a Message Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of messages in the queue. +/// \param type data type of a single message element (for debugger). +/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMessageQDef(name, queue_sz, type) \ +extern const osMessageQDef_t os_messageQ_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osMessageQDef(name, queue_sz, type) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), NULL } +#else +#define osMessageQDef(name, queue_sz, type) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), { NULL, 0U, NULL, 0U, NULL, 0U } } +#endif +#endif + +/// \brief Access a Message Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMessageQ(name) \ +&os_messageQ_def_##name + +/// Create and Initialize a Message Queue object. +/// \param[in] queue_def message queue definition referenced with \ref osMessageQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return message queue ID for reference by other functions or NULL in case of error. +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id); + +/// Put a Message to a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] info message information. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); + +/// Get a Message from a Queue or timeout if Queue is empty. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event information that includes status code. +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); + +#endif // Message Queue available + + +// ==== Mail Queue Management Functions ==== + +#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queue available + +/// \brief Create a Mail Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of mails in the queue. +/// \param type data type of a single mail element. +/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMailQDef(name, queue_sz, type) \ +extern const osMailQDef_t os_mailQ_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osMailQDef(name, queue_sz, type) \ +const osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof(type), NULL } +#else +#define osMailQDef(name, queue_sz, type) \ +static void *os_mail_p_##name[2]; \ +const osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof(type), (&os_mail_p_##name), \ + { NULL, 0U, NULL, 0U, NULL, 0U }, \ + { NULL, 0U, NULL, 0U, NULL, 0U } } +#endif +#endif + +/// \brief Access a Mail Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMailQ(name) \ +&os_mailQ_def_##name + +/// Create and Initialize a Mail Queue object. +/// \param[in] queue_def mail queue definition referenced with \ref osMailQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return mail queue ID for reference by other functions or NULL in case of error. +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id); + +/// Allocate a memory block for mail from a mail memory pool. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +void *osMailAlloc (osMailQId queue_id, uint32_t millisec); + +/// Allocate a memory block for mail from a mail memory pool and set memory block to zero. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); + +/// Put a Mail into a Queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to memory with mail to put into a queue. +/// \return status code that indicates the execution status of the function. +osStatus osMailPut (osMailQId queue_id, const void *mail); + +/// Get a Mail from a Queue or timeout if Queue is empty. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event information that includes status code. +osEvent osMailGet (osMailQId queue_id, uint32_t millisec); + +/// Free a memory block by returning it to a mail memory pool. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to memory block that was obtained with \ref osMailGet. +/// \return status code that indicates the execution status of the function. +osStatus osMailFree (osMailQId queue_id, void *mail); + +#endif // Mail Queue available + + +#ifdef __cplusplus +} +#endif + +#endif // CMSIS_OS_H_ diff --git a/benchmark/interface/Drivers/CMSIS/RTOS2/Template/cmsis_os1.c b/benchmark/interface/Drivers/CMSIS/RTOS2/Template/cmsis_os1.c new file mode 100644 index 00000000..de1650c4 --- /dev/null +++ b/benchmark/interface/Drivers/CMSIS/RTOS2/Template/cmsis_os1.c @@ -0,0 +1,361 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 10. January 2017 + * $Revision: V1.2 + * + * Project: CMSIS-RTOS API V1 + * Title: cmsis_os_v1.c V1 module file + *---------------------------------------------------------------------------*/ + +#include +#include "cmsis_os.h" + +#if (osCMSIS >= 0x20000U) + + +// Thread +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) { + + if (thread_def == NULL) { + return (osThreadId)NULL; + } + return osThreadNew((osThreadFunc_t)thread_def->pthread, argument, &thread_def->attr); +} + + +// Signals + +#define SignalMask ((1U< 0U) && (flags < 0x80000000U)) { + event.status = osEventSignal; + event.value.signals = (int32_t)flags; + } else { + switch ((int32_t)flags) { + case osErrorResource: + event.status = osOK; + break; + case osErrorTimeout: + event.status = osEventTimeout; + break; + case osErrorParameter: + event.status = osErrorValue; + break; + default: + event.status = (osStatus)flags; + break; + } + } + return event; +} + + +// Timer +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) { + + if (timer_def == NULL) { + return (osTimerId)NULL; + } + return osTimerNew((osTimerFunc_t)timer_def->ptimer, type, argument, &timer_def->attr); +} + + +// Mutex +osMutexId osMutexCreate (const osMutexDef_t *mutex_def) { + + if (mutex_def == NULL) { + return (osMutexId)NULL; + } + return osMutexNew(mutex_def); +} + + +// Semaphore + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) + +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) { + + if (semaphore_def == NULL) { + return (osSemaphoreId)NULL; + } + return osSemaphoreNew((uint32_t)count, (uint32_t)count, semaphore_def); +} + +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) { + osStatus_t status; + uint32_t count; + + status = osSemaphoreAcquire(semaphore_id, millisec); + switch (status) { + case osOK: + count = osSemaphoreGetCount(semaphore_id); + return ((int32_t)count + 1); + case osErrorResource: + case osErrorTimeout: + return 0; + default: + break; + } + return -1; +} + +#endif // Semaphore + + +// Memory Pool + +#if (defined(osFeature_Pool) && (osFeature_Pool != 0)) + +osPoolId osPoolCreate (const osPoolDef_t *pool_def) { + + if (pool_def == NULL) { + return (osPoolId)NULL; + } + return ((osPoolId)(osMemoryPoolNew(pool_def->pool_sz, pool_def->item_sz, &pool_def->attr))); +} + +void *osPoolAlloc (osPoolId pool_id) { + return osMemoryPoolAlloc((osMemoryPoolId_t)pool_id, 0U); +} + +void *osPoolCAlloc (osPoolId pool_id) { + void *block; + uint32_t block_size; + + block_size = osMemoryPoolGetBlockSize((osMemoryPoolId_t)pool_id); + if (block_size == 0U) { + return NULL; + } + block = osMemoryPoolAlloc((osMemoryPoolId_t)pool_id, 0U); + if (block != NULL) { + memset(block, 0, block_size); + } + return block; +} + +osStatus osPoolFree (osPoolId pool_id, void *block) { + return osMemoryPoolFree((osMemoryPoolId_t)pool_id, block); +} + +#endif // Memory Pool + + +// Message Queue + +#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) + +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) { + (void)thread_id; + + if (queue_def == NULL) { + return (osMessageQId)NULL; + } + return ((osMessageQId)(osMessageQueueNew(queue_def->queue_sz, sizeof(uint32_t), &queue_def->attr))); +} + +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) { + return osMessageQueuePut((osMessageQueueId_t)queue_id, &info, 0U, millisec); +} + +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) { + osStatus_t status; + osEvent event; + uint32_t message; + + status = osMessageQueueGet((osMessageQueueId_t)queue_id, &message, NULL, millisec); + switch (status) { + case osOK: + event.status = osEventMessage; + event.value.v = message; + break; + case osErrorResource: + event.status = osOK; + break; + case osErrorTimeout: + event.status = osEventTimeout; + break; + default: + event.status = status; + break; + } + return event; +} + +#endif // Message Queue + + +// Mail Queue + +#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) + +typedef struct os_mail_queue_s { + osMemoryPoolId_t mp_id; + osMessageQueueId_t mq_id; +} os_mail_queue_t; + +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) { + os_mail_queue_t *ptr; + (void)thread_id; + + if (queue_def == NULL) { + return (osMailQId)NULL; + } + + ptr = queue_def->mail; + if (ptr == NULL) { + return (osMailQId)NULL; + } + + ptr->mp_id = osMemoryPoolNew (queue_def->queue_sz, queue_def->item_sz, &queue_def->mp_attr); + ptr->mq_id = osMessageQueueNew(queue_def->queue_sz, sizeof(void *), &queue_def->mq_attr); + if ((ptr->mp_id == (osMemoryPoolId_t)NULL) || (ptr->mq_id == (osMessageQueueId_t)NULL)) { + if (ptr->mp_id != (osMemoryPoolId_t)NULL) { + osMemoryPoolDelete(ptr->mp_id); + } + if (ptr->mq_id != (osMessageQueueId_t)NULL) { + osMessageQueueDelete(ptr->mq_id); + } + return (osMailQId)NULL; + } + + return (osMailQId)ptr; +} + +void *osMailAlloc (osMailQId queue_id, uint32_t millisec) { + os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; + + if (ptr == NULL) { + return NULL; + } + return osMemoryPoolAlloc(ptr->mp_id, millisec); +} + +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec) { + os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; + void *block; + uint32_t block_size; + + if (ptr == NULL) { + return NULL; + } + block_size = osMemoryPoolGetBlockSize(ptr->mp_id); + if (block_size == 0U) { + return NULL; + } + block = osMemoryPoolAlloc(ptr->mp_id, millisec); + if (block != NULL) { + memset(block, 0, block_size); + } + + return block; + +} + +osStatus osMailPut (osMailQId queue_id, const void *mail) { + os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; + + if (ptr == NULL) { + return osErrorParameter; + } + if (mail == NULL) { + return osErrorValue; + } + return osMessageQueuePut(ptr->mq_id, &mail, 0U, 0U); +} + +osEvent osMailGet (osMailQId queue_id, uint32_t millisec) { + os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; + osStatus_t status; + osEvent event; + void *mail; + + if (ptr == NULL) { + event.status = osErrorParameter; + return event; + } + + status = osMessageQueueGet(ptr->mq_id, &mail, NULL, millisec); + switch (status) { + case osOK: + event.status = osEventMail; + event.value.p = mail; + break; + case osErrorResource: + event.status = osOK; + break; + case osErrorTimeout: + event.status = osEventTimeout; + break; + default: + event.status = status; + break; + } + return event; +} + +osStatus osMailFree (osMailQId queue_id, void *mail) { + os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; + + if (ptr == NULL) { + return osErrorParameter; + } + if (mail == NULL) { + return osErrorValue; + } + return osMemoryPoolFree(ptr->mp_id, mail); +} + +#endif // Mail Queue + + +#endif // osCMSIS diff --git a/benchmark/interface/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_tim.h b/benchmark/interface/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_tim.h new file mode 100644 index 00000000..bae31679 --- /dev/null +++ b/benchmark/interface/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_tim.h @@ -0,0 +1,6269 @@ +/** + ****************************************************************************** + * @file stm32h5xx_ll_tim.h + * @author MCD Application Team + * @brief Header file of TIM LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H5xx_LL_TIM_H +#define __STM32H5xx_LL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx.h" + +/** @addtogroup STM32H5xx_LL_Driver + * @{ + */ + +#if defined (TIM1) \ + || defined (TIM2) \ + || defined (TIM3) \ + || defined (TIM4) \ + || defined (TIM5) \ + || defined (TIM6) \ + || defined (TIM7) \ + || defined (TIM8) \ + || defined (TIM12) \ + || defined (TIM13) \ + || defined (TIM14) \ + || defined (TIM15) \ + || defined (TIM16) \ + || defined (TIM17) + +/** @defgroup TIM_LL TIM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Variables TIM Private Variables + * @{ + */ +static const uint8_t OFFSET_TAB_CCMRx[] = +{ + 0x00U, /* 0: TIMx_CH1 */ + 0x00U, /* 1: TIMx_CH1N */ + 0x00U, /* 2: TIMx_CH2 */ + 0x00U, /* 3: TIMx_CH2N */ + 0x04U, /* 4: TIMx_CH3 */ + 0x04U, /* 5: TIMx_CH3N */ + 0x04U, /* 6: TIMx_CH4 */ + 0x04U, /* 7: TIMx_CH4N */ + 0x38U, /* 8: TIMx_CH5 */ + 0x38U /* 9: TIMx_CH6 */ + +}; + +static const uint8_t SHIFT_TAB_OCxx[] = +{ + 0U, /* 0: OC1M, OC1FE, OC1PE */ + 0U, /* 1: - NA */ + 8U, /* 2: OC2M, OC2FE, OC2PE */ + 0U, /* 3: - NA */ + 0U, /* 4: OC3M, OC3FE, OC3PE */ + 0U, /* 5: - NA */ + 8U, /* 6: OC4M, OC4FE, OC4PE */ + 0U, /* 7: - NA */ + 0U, /* 8: OC5M, OC5FE, OC5PE */ + 8U /* 9: OC6M, OC6FE, OC6PE */ +}; + +static const uint8_t SHIFT_TAB_ICxx[] = +{ + 0U, /* 0: CC1S, IC1PSC, IC1F */ + 0U, /* 1: - NA */ + 8U, /* 2: CC2S, IC2PSC, IC2F */ + 0U, /* 3: - NA */ + 0U, /* 4: CC3S, IC3PSC, IC3F */ + 0U, /* 5: - NA */ + 8U, /* 6: CC4S, IC4PSC, IC4F */ + 0U, /* 7: - NA */ + 0U, /* 8: - NA */ + 0U /* 9: - NA */ +}; + +static const uint8_t SHIFT_TAB_CCxP[] = +{ + 0U, /* 0: CC1P */ + 2U, /* 1: CC1NP */ + 4U, /* 2: CC2P */ + 6U, /* 3: CC2NP */ + 8U, /* 4: CC3P */ + 10U, /* 5: CC3NP */ + 12U, /* 6: CC4P */ + 14U, /* 7: CC4NP */ + 16U, /* 8: CC5P */ + 20U /* 9: CC6P */ +}; + +static const uint8_t SHIFT_TAB_OISx[] = +{ + 0U, /* 0: OIS1 */ + 1U, /* 1: OIS1N */ + 2U, /* 2: OIS2 */ + 3U, /* 3: OIS2N */ + 4U, /* 4: OIS3 */ + 5U, /* 5: OIS3N */ + 6U, /* 6: OIS4 */ + 7U, /* 7: OIS4N */ + 8U, /* 8: OIS5 */ + 10U /* 9: OIS6 */ +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Constants TIM Private Constants + * @{ + */ + +/* Defines used for the bit position in the register and perform offsets */ +#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) + +/* Generic bit definitions for TIMx_AF1 register */ +#define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */ +#define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */ + + +/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ +#define DT_DELAY_1 ((uint8_t)0x7F) +#define DT_DELAY_2 ((uint8_t)0x3F) +#define DT_DELAY_3 ((uint8_t)0x1F) +#define DT_DELAY_4 ((uint8_t)0x1F) + +/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ +#define DT_RANGE_1 ((uint8_t)0x00) +#define DT_RANGE_2 ((uint8_t)0x80) +#define DT_RANGE_3 ((uint8_t)0xC0) +#define DT_RANGE_4 ((uint8_t)0xE0) + +/** Legacy definitions for compatibility purpose +@cond 0 + */ +/** +@endcond + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Macros TIM Private Macros + * @{ + */ +/** @brief Convert channel id into channel index. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval none + */ +#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ + (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U) + +/** @brief Calculate the deadtime sampling period(in ps). + * @param __TIMCLK__ timer input clock frequency (in Hz). + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval none + */ +#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ + (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ + ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ + ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure + * @{ + */ + +/** + * @brief TIM Time Base configuration structure definition. + */ +typedef struct +{ + uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetPrescaler().*/ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetCounterMode().*/ + + uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + Some timer instances may support 32 bits counters. In that case this parameter must + be a number between 0x0000 and 0xFFFFFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetAutoReload().*/ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetClockDivision().*/ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetRepetitionCounter().*/ +} LL_TIM_InitTypeDef; + +/** + * @brief TIM Output Compare configuration structure definition. + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the output mode. + This parameter can be a value of @ref TIM_LL_EC_OCMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetMode().*/ + + uint32_t OCState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function + LL_TIM_OC_SetCompareCHx (x=1..6).*/ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ +} LL_TIM_OC_InitTypeDef; + +/** + * @brief TIM Input Capture configuration structure definition. + */ + +typedef struct +{ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t ICActiveInput; /*!< Specifies the input. + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ +} LL_TIM_IC_InitTypeDef; + + +/** + * @brief TIM Encoder interface configuration structure definition. + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). + This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetEncoderMode().*/ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + + uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC2Filter; /*!< Specifies the TI2 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + +} LL_TIM_ENCODER_InitTypeDef; + +/** + * @brief TIM Hall sensor interface configuration structure definition. + */ +typedef struct +{ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + Prescaler must be set to get a maximum counter period longer than the + time interval between 2 consecutive changes on the Hall inputs. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of + @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + + uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. + A positive pulse (TRGO event) is generated with a programmable delay every time + a change occurs on the Hall inputs. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetCompareCH2().*/ +} LL_TIM_HALLSENSOR_InitTypeDef; + +/** + * @brief BDTR (Break and Dead Time) structure definition + */ +typedef struct +{ + uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_LL_EC_OSSR + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ + + uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_LL_EC_OSSI + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ + + uint32_t LockLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL + + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR + register has been written, their content is frozen until the next reset.*/ + + uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetDeadTime() + + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been + programmed. */ + + uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. + This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input. + This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_ConfigBRK() + + @note Bidirectional break input is only supported by advanced timers instances. + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_ConfigBRK2() + + @note Bidirectional break input is only supported by advanced timers instances. + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ +} LL_TIM_BDTR_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_TIM_ReadReg function. + * @{ + */ +#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ +#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ +#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ +#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ +#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ +#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */ +#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */ +#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ +#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ +#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ +#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */ +#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ +#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ +#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ +#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ +#define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */ +#define LL_TIM_SR_IDXF TIM_SR_IDXF /*!< Index interrupt flag */ +#define LL_TIM_SR_DIRF TIM_SR_DIRF /*!< Direction Change interrupt flag */ +#define LL_TIM_SR_IERRF TIM_SR_IERRF /*!< Index Error flag */ +#define LL_TIM_SR_TERRF TIM_SR_TERRF /*!< Transition Error flag */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable + * @{ + */ +#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ +#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable + * @{ + */ +#define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ +#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable + * @{ + */ +#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup TIM_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. + * @{ + */ +#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ +#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ +#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ +#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ +#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ +#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ +#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ +#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ +#define LL_TIM_DIER_IDXIE TIM_DIER_IDXIE /*!< Index interrupt enable */ +#define LL_TIM_DIER_DIRIE TIM_DIER_DIRIE /*!< Direction Change interrupt enable */ +#define LL_TIM_DIER_IERRIE TIM_DIER_IERRIE /*!< Index Error interrupt enable */ +#define LL_TIM_DIER_TERRIE TIM_DIER_TERRIE /*!< Transition Error interrupt enable */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source + * @{ + */ +#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ +#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode + * @{ + */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode + * @{ + */ +#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!TIMx_CCRy else active.*/ +#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/ +#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!__REG__, (__VALUE__)) + +/** + * @brief Read a value in TIM register. + * @param __INSTANCE__ TIM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) +/** + * @} + */ + +/** + * @brief HELPER macro retrieving the UIFCPY flag from the counter value. + * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); + * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied + * to TIMx_CNT register bit 31) + * @param __CNT__ Counter value + * @retval UIF status bit + */ +#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ + (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) + +/** + * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. + * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @param __DT__ deadtime duration (in ns) + * @retval DTG[0:7] + */ +#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ + ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ + (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ + 0U) + +/** + * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. + * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CNTCLK__ counter clock frequency (in Hz) + * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ + (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. + * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __FREQ__ output signal frequency (in Hz) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ + ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required + * output signal frequency. + * @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __FREQ__ output signal frequency (in Hz) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \ + ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \ + (uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U) + +/** + * @brief HELPER macro calculating the compare value required to achieve the required timer output compare + * active/inactive delay. + * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @retval Compare value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ + ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + +/** + * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer + * output compare active/inactive delay. + * @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @retval Compare value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__) \ + ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration + * (when the timer operates in one pulse mode). + * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @param __PULSE__ pulse duration (in us) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ + ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) + +/** + * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required + * pulse duration (when the timer operates in one pulse mode). + * @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @param __PULSE__ pulse duration (in us) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ + ((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__)))) + +/** + * @brief HELPER macro retrieving the ratio of the input capture prescaler + * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); + * @param __ICPSC__ This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval Input capture prescaler ratio (1, 2, 4 or 8) + */ +#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ + ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_LL_EF_Time_Base Time Base configuration + * @{ + */ +/** + * @brief Enable timer counter. + * @rmtoll CR1 CEN LL_TIM_EnableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Disable timer counter. + * @rmtoll CR1 CEN LL_TIM_DisableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Indicates whether the timer counter is enabled. + * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable update event generation. + * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Disable update event generation. + * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Indicates whether update event generation is enabled. + * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent + * @param TIMx Timer instance + * @retval Inverted state of bit (0 or 1). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); +} + +/** + * @brief Set update event source + * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events + * generate an update interrupt or DMA request if enabled: + * - Counter overflow/underflow + * - Setting the UG bit + * - Update generation through the slave mode controller + * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter + * overflow/underflow generates an update interrupt or DMA request if enabled. + * @rmtoll CR1 URS LL_TIM_SetUpdateSource + * @param TIMx Timer instance + * @param UpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); +} + +/** + * @brief Get actual event update source + * @rmtoll CR1 URS LL_TIM_GetUpdateSource + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + */ +__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); +} + +/** + * @brief Set one pulse mode (one shot v.s. repetitive). + * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode + * @param TIMx Timer instance + * @param OnePulseMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); +} + +/** + * @brief Get actual one pulse mode. + * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + */ +__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); +} + +/** + * @brief Set the timer counter counting mode. + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n + * CR1 CMS LL_TIM_SetCounterMode + * @param TIMx Timer instance + * @param CounterMode This parameter can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) +{ + MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); +} + +/** + * @brief Get actual counter mode. + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n + * CR1 CMS LL_TIM_GetCounterMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) +{ + uint32_t counter_mode; + + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); + + if (counter_mode == 0U) + { + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); + } + + return counter_mode; +} + +/** + * @brief Enable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Disable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Indicates whether auto-reload (ARR) preload is enabled. + * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); +} + +/** + * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators + * (when supported) and the digital filters. + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_SetClockDivision + * @param TIMx Timer instance + * @param ClockDivision This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); +} + +/** + * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time + * generators (when supported) and the digital filters. + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_GetClockDivision + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + */ +__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); +} + +/** + * @brief Set the counter value. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note If dithering is activated, pay attention to the Counter value interpretation + * @rmtoll CNT CNT LL_TIM_SetCounter + * @param TIMx Timer instance + * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) +{ + WRITE_REG(TIMx->CNT, Counter); +} + +/** + * @brief Get the counter value. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note If dithering is activated, pay attention to the Counter value interpretation + * @rmtoll CNT CNT LL_TIM_GetCounter + * @param TIMx Timer instance + * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CNT)); +} + +/** + * @brief Get the current direction of the counter + * @rmtoll CR1 DIR LL_TIM_GetDirection + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERDIRECTION_UP + * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); +} + +/** + * @brief Set the prescaler value. + * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). + * @note The prescaler can be changed on the fly as this control register is buffered. The new + * prescaler ratio is taken into account at the next update event. + * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter + * @rmtoll PSC PSC LL_TIM_SetPrescaler + * @param TIMx Timer instance + * @param Prescaler between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) +{ + WRITE_REG(TIMx->PSC, Prescaler); +} + +/** + * @brief Get the prescaler value. + * @rmtoll PSC PSC LL_TIM_GetPrescaler + * @param TIMx Timer instance + * @retval Prescaler value between Min_Data=0 and Max_Data=65535 + */ +__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->PSC)); +} + +/** + * @brief Set the auto-reload value. + * @note The counter is blocked while the auto-reload value is null. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter + * In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload + * parameter. + * @rmtoll ARR ARR LL_TIM_SetAutoReload + * @param TIMx Timer instance + * @param AutoReload between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) +{ + WRITE_REG(TIMx->ARR, AutoReload); +} + +/** + * @brief Get the auto-reload value. + * @rmtoll ARR ARR LL_TIM_GetAutoReload + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note If dithering is activated, pay attention to the returned value interpretation + * @param TIMx Timer instance + * @retval Auto-reload value + */ +__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->ARR)); +} + +/** + * @brief Set the repetition counter value. + * @note For advanced timer instances RepetitionCounter can be up to 65535. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_SetRepetitionCounter + * @param TIMx Timer instance + * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) +{ + WRITE_REG(TIMx->RCR, RepetitionCounter); +} + +/** + * @brief Get the repetition counter value. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_GetRepetitionCounter + * @param TIMx Timer instance + * @retval Repetition counter value + */ +__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->RCR)); +} + +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. + * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); +} + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); +} + +/** + * @brief Indicate whether update interrupt flag (UIF) copy is set. + * @param Counter Counter value + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter) +{ + return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); +} + +/** + * @brief Enable dithering. + * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides dithering. + * @rmtoll CR1 DITHEN LL_TIM_EnableDithering + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_DITHEN); +} + +/** + * @brief Disable dithering. + * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides dithering. + * @rmtoll CR1 DITHEN LL_TIM_DisableDithering + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN); +} + +/** + * @brief Indicates whether dithering is activated. + * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides dithering. + * @rmtoll CR1 DITHEN LL_TIM_IsEnabledDithering + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration + * @{ + */ +/** + * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, + * they are updated only when a commutation event (COM) occurs. + * @note Only on channels that have a complementary output. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate + * @param TIMx Timer instance + * @param CCUpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); +} + +/** + * @brief Set the trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger + * @param TIMx Timer instance + * @param DMAReqTrigger This parameter can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); +} + +/** + * @brief Get actual trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + */ +__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); +} + +/** + * @brief Set the lock level to freeze the + * configuration of several capture/compare parameters. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * the lock mechanism is supported by a timer instance. + * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel + * @param TIMx Timer instance + * @param LockLevel This parameter can be one of the following values: + * @arg @ref LL_TIM_LOCKLEVEL_OFF + * @arg @ref LL_TIM_LOCKLEVEL_1 + * @arg @ref LL_TIM_LOCKLEVEL_2 + * @arg @ref LL_TIM_LOCKLEVEL_3 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); +} + +/** + * @brief Enable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n + * CCER CC1NE LL_TIM_CC_EnableChannel\n + * CCER CC2E LL_TIM_CC_EnableChannel\n + * CCER CC2NE LL_TIM_CC_EnableChannel\n + * CCER CC3E LL_TIM_CC_EnableChannel\n + * CCER CC3NE LL_TIM_CC_EnableChannel\n + * CCER CC4E LL_TIM_CC_EnableChannel\n + * CCER CC4NE LL_TIM_CC_EnableChannel\n + * CCER CC5E LL_TIM_CC_EnableChannel\n + * CCER CC6E LL_TIM_CC_EnableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + SET_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Disable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n + * CCER CC1NE LL_TIM_CC_DisableChannel\n + * CCER CC2E LL_TIM_CC_DisableChannel\n + * CCER CC2NE LL_TIM_CC_DisableChannel\n + * CCER CC3E LL_TIM_CC_DisableChannel\n + * CCER CC3NE LL_TIM_CC_DisableChannel\n + * CCER CC4E LL_TIM_CC_DisableChannel\n + * CCER CC4NE LL_TIM_CC_DisableChannel\n + * CCER CC5E LL_TIM_CC_DisableChannel\n + * CCER CC6E LL_TIM_CC_DisableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + CLEAR_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Indicate whether channel(s) is(are) enabled. + * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n + * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC2E LL_TIM_CC_IsEnabledChannel\n + * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC3E LL_TIM_CC_IsEnabledChannel\n + * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC4E LL_TIM_CC_IsEnabledChannel\n + * CCER CC4NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC5E LL_TIM_CC_IsEnabledChannel\n + * CCER CC6E LL_TIM_CC_IsEnabledChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) +{ + return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration + * @{ + */ +/** + * @brief Configure an output channel. + * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n + * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n + * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n + * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n + * CCER CC1P LL_TIM_OC_ConfigOutput\n + * CCER CC2P LL_TIM_OC_ConfigOutput\n + * CCER CC3P LL_TIM_OC_ConfigOutput\n + * CCER CC4P LL_TIM_OC_ConfigOutput\n + * CCER CC5P LL_TIM_OC_ConfigOutput\n + * CCER CC6P LL_TIM_OC_ConfigOutput\n + * CR2 OIS1 LL_TIM_OC_ConfigOutput\n + * CR2 OIS2 LL_TIM_OC_ConfigOutput\n + * CR2 OIS3 LL_TIM_OC_ConfigOutput\n + * CR2 OIS4 LL_TIM_OC_ConfigOutput\n + * CR2 OIS5 LL_TIM_OC_ConfigOutput\n + * CR2 OIS6 LL_TIM_OC_ConfigOutput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW + * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), + (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), + (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Define the behavior of the output reference signal OCxREF from which + * OCx and OCxN (when relevant) are derived. + * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n + * CCMR1 OC2M LL_TIM_OC_SetMode\n + * CCMR2 OC3M LL_TIM_OC_SetMode\n + * CCMR2 OC4M LL_TIM_OC_SetMode\n + * CCMR3 OC5M LL_TIM_OC_SetMode\n + * CCMR3 OC6M LL_TIM_OC_SetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 + * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 + * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only) + * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only) + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Get the output compare mode of an output channel. + * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n + * CCMR1 OC2M LL_TIM_OC_GetMode\n + * CCMR2 OC3M LL_TIM_OC_GetMode\n + * CCMR2 OC4M LL_TIM_OC_GetMode\n + * CCMR3 OC5M LL_TIM_OC_GetMode\n + * CCMR3 OC6M LL_TIM_OC_GetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 + * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 + * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only) + * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Set the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n + * CCER CC1NP LL_TIM_OC_SetPolarity\n + * CCER CC2P LL_TIM_OC_SetPolarity\n + * CCER CC2NP LL_TIM_OC_SetPolarity\n + * CCER CC3P LL_TIM_OC_SetPolarity\n + * CCER CC3NP LL_TIM_OC_SetPolarity\n + * CCER CC4P LL_TIM_OC_SetPolarity\n + * CCER CC4NP LL_TIM_OC_SetPolarity\n + * CCER CC5P LL_TIM_OC_SetPolarity\n + * CCER CC6P LL_TIM_OC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n + * CCER CC1NP LL_TIM_OC_GetPolarity\n + * CCER CC2P LL_TIM_OC_GetPolarity\n + * CCER CC2NP LL_TIM_OC_GetPolarity\n + * CCER CC3P LL_TIM_OC_GetPolarity\n + * CCER CC3NP LL_TIM_OC_GetPolarity\n + * CCER CC4P LL_TIM_OC_GetPolarity\n + * CCER CC4NP LL_TIM_OC_GetPolarity\n + * CCER CC5P LL_TIM_OC_GetPolarity\n + * CCER CC6P LL_TIM_OC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the IDLE state of an output channel + * @note This function is significant only for the timer instances + * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) + * can be used to check whether or not a timer instance provides + * a break input. + * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n + * CR2 OIS2N LL_TIM_OC_SetIdleState\n + * CR2 OIS2 LL_TIM_OC_SetIdleState\n + * CR2 OIS2N LL_TIM_OC_SetIdleState\n + * CR2 OIS3 LL_TIM_OC_SetIdleState\n + * CR2 OIS3N LL_TIM_OC_SetIdleState\n + * CR2 OIS4 LL_TIM_OC_SetIdleState\n + * CR2 OIS4N LL_TIM_OC_SetIdleState\n + * CR2 OIS5 LL_TIM_OC_SetIdleState\n + * CR2 OIS6 LL_TIM_OC_SetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param IdleState This parameter can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Get the IDLE state of an output channel + * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n + * CR2 OIS2N LL_TIM_OC_GetIdleState\n + * CR2 OIS2 LL_TIM_OC_GetIdleState\n + * CR2 OIS2N LL_TIM_OC_GetIdleState\n + * CR2 OIS3 LL_TIM_OC_GetIdleState\n + * CR2 OIS3N LL_TIM_OC_GetIdleState\n + * CR2 OIS4 LL_TIM_OC_GetIdleState\n + * CR2 OIS4N LL_TIM_OC_GetIdleState\n + * CR2 OIS5 LL_TIM_OC_GetIdleState\n + * CR2 OIS6 LL_TIM_OC_GetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Enable fast mode for the output channel. + * @note Acts only if the channel is configured in PWM1 or PWM2 mode. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n + * CCMR1 OC2FE LL_TIM_OC_EnableFast\n + * CCMR2 OC3FE LL_TIM_OC_EnableFast\n + * CCMR2 OC4FE LL_TIM_OC_EnableFast\n + * CCMR3 OC5FE LL_TIM_OC_EnableFast\n + * CCMR3 OC6FE LL_TIM_OC_EnableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Disable fast mode for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n + * CCMR1 OC2FE LL_TIM_OC_DisableFast\n + * CCMR2 OC3FE LL_TIM_OC_DisableFast\n + * CCMR2 OC4FE LL_TIM_OC_DisableFast\n + * CCMR3 OC5FE LL_TIM_OC_DisableFast\n + * CCMR3 OC6FE LL_TIM_OC_DisableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Indicates whether fast mode is enabled for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n + * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n + * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n + * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n + * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n + * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n + * CCMR3 OC6PE LL_TIM_OC_EnablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n + * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n + * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n + * CCMR3 OC6PE LL_TIM_OC_DisablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n + * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n + * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n + * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n + * CCMR1 OC2CE LL_TIM_OC_EnableClear\n + * CCMR2 OC3CE LL_TIM_OC_EnableClear\n + * CCMR2 OC4CE LL_TIM_OC_EnableClear\n + * CCMR3 OC5CE LL_TIM_OC_EnableClear\n + * CCMR3 OC6CE LL_TIM_OC_EnableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable clearing the output channel on an external event. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n + * CCMR1 OC2CE LL_TIM_OC_DisableClear\n + * CCMR2 OC3CE LL_TIM_OC_DisableClear\n + * CCMR2 OC4CE LL_TIM_OC_DisableClear\n + * CCMR3 OC5CE LL_TIM_OC_DisableClear\n + * CCMR3 OC6CE LL_TIM_OC_DisableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates clearing the output channel on an external event is enabled for the output channel. + * @note This function enables clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n + * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n + * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n + * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of + * the Ocx and OCxN signals). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * dead-time insertion feature is supported by a timer instance. + * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter + * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime + * @param TIMx Timer instance + * @param DeadTime between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); +} + +/** + * @brief Set compare value for output channel 1 (TIMx_CCR1). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . + * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR1, CompareValue); +} + +/** + * @brief Set compare value for output channel 2 (TIMx_CCR2). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . + * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR2, CompareValue); +} + +/** + * @brief Set compare value for output channel 3 (TIMx_CCR3). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel is supported by a timer instance. + * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . + * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR3, CompareValue); +} + +/** + * @brief Set compare value for output channel 4 (TIMx_CCR4). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . + * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR4, CompareValue); +} + +/** + * @brief Set compare value for output channel 5 (TIMx_CCR5). + * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * output channel 5 is supported by a timer instance. + * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . + * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); +} + +/** + * @brief Set compare value for output channel 6 (TIMx_CCR6). + * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * output channel 6 is supported by a timer instance. + * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . + * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR6, CompareValue); +} + +/** + * @brief Get compare value (TIMx_CCR1) set for output channel 1. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get compare value (TIMx_CCR2) set for output channel 2. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get compare value (TIMx_CCR3) set for output channel 3. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel 3 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get compare value (TIMx_CCR4) set for output channel 4. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @brief Get compare value (TIMx_CCR5) set for output channel 5. + * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * output channel 5 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); +} + +/** + * @brief Get compare value (TIMx_CCR6) set for output channel 6. + * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * output channel 6 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR6)); +} + +/** + * @brief Select on which reference signal the OC5REF is combined to. + * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the combined 3-phase PWM mode. + * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n + * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n + * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels + * @param TIMx Timer instance + * @param GroupCH5 This parameter can be a combination of the following values: + * @arg @ref LL_TIM_GROUPCH5_NONE + * @arg @ref LL_TIM_GROUPCH5_OC1REFC + * @arg @ref LL_TIM_GROUPCH5_OC2REFC + * @arg @ref LL_TIM_GROUPCH5_OC3REFC + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) +{ + MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); +} + +/** + * @brief Set the pulse on compare pulse width prescaler. + * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check + * whether or not the pulse on compare feature is supported by the timer + * instance. + * @rmtoll ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler + * @param TIMx Timer instance + * @param PulseWidthPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_PWPRSC_X1 + * @arg @ref LL_TIM_PWPRSC_X2 + * @arg @ref LL_TIM_PWPRSC_X4 + * @arg @ref LL_TIM_PWPRSC_X8 + * @arg @ref LL_TIM_PWPRSC_X16 + * @arg @ref LL_TIM_PWPRSC_X32 + * @arg @ref LL_TIM_PWPRSC_X64 + * @arg @ref LL_TIM_PWPRSC_X128 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler) +{ + MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler); +} + +/** + * @brief Get the pulse on compare pulse width prescaler. + * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check + * whether or not the pulse on compare feature is supported by the timer + * instance. + * @rmtoll ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_PWPRSC_X1 + * @arg @ref LL_TIM_PWPRSC_X2 + * @arg @ref LL_TIM_PWPRSC_X4 + * @arg @ref LL_TIM_PWPRSC_X8 + * @arg @ref LL_TIM_PWPRSC_X16 + * @arg @ref LL_TIM_PWPRSC_X32 + * @arg @ref LL_TIM_PWPRSC_X64 + * @arg @ref LL_TIM_PWPRSC_X128 + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC)); +} + +/** + * @brief Set the pulse on compare pulse width duration. + * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check + * whether or not the pulse on compare feature is supported by the timer + * instance. + * @rmtoll ECR PW LL_TIM_OC_SetPulseWidth + * @param TIMx Timer instance + * @param PulseWidth This parameter can be between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth) +{ + MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos); +} + +/** + * @brief Get the pulse on compare pulse width duration. + * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check + * whether or not the pulse on compare feature is supported by the timer + * instance. + * @rmtoll ECR PW LL_TIM_OC_GetPulseWidth + * @param TIMx Timer instance + * @retval Returned value can be between Min_Data=0 and Max_Data=255: + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration + * @{ + */ +/** + * @brief Configure input channel. + * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n + * CCMR1 IC1PSC LL_TIM_IC_Config\n + * CCMR1 IC1F LL_TIM_IC_Config\n + * CCMR1 CC2S LL_TIM_IC_Config\n + * CCMR1 IC2PSC LL_TIM_IC_Config\n + * CCMR1 IC2F LL_TIM_IC_Config\n + * CCMR2 CC3S LL_TIM_IC_Config\n + * CCMR2 IC3PSC LL_TIM_IC_Config\n + * CCMR2 IC3F LL_TIM_IC_Config\n + * CCMR2 CC4S LL_TIM_IC_Config\n + * CCMR2 IC4PSC LL_TIM_IC_Config\n + * CCMR2 IC4F LL_TIM_IC_Config\n + * CCER CC1P LL_TIM_IC_Config\n + * CCER CC1NP LL_TIM_IC_Config\n + * CCER CC2P LL_TIM_IC_Config\n + * CCER CC2NP LL_TIM_IC_Config\n + * CCER CC3P LL_TIM_IC_Config\n + * CCER CC3NP LL_TIM_IC_Config\n + * CCER CC4P LL_TIM_IC_Config\n + * CCER CC4NP LL_TIM_IC_Config + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC + * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 + * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), + ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ + << SHIFT_TAB_ICxx[iChannel]); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_SetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICActiveInput This parameter can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_GetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the prescaler of input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current prescaler value acting on an input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n + * CCMR1 IC2F LL_TIM_IC_SetFilter\n + * CCMR2 IC3F LL_TIM_IC_SetFilter\n + * CCMR2 IC4F LL_TIM_IC_SetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n + * CCMR1 IC2F LL_TIM_IC_GetFilter\n + * CCMR2 IC3F LL_TIM_IC_GetFilter\n + * CCMR2 IC4F LL_TIM_IC_GetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n + * CCER CC1NP LL_TIM_IC_SetPolarity\n + * CCER CC2P LL_TIM_IC_SetPolarity\n + * CCER CC2NP LL_TIM_IC_SetPolarity\n + * CCER CC3P LL_TIM_IC_SetPolarity\n + * CCER CC3NP LL_TIM_IC_SetPolarity\n + * CCER CC4P LL_TIM_IC_SetPolarity\n + * CCER CC4NP LL_TIM_IC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + ICPolarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the current input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n + * CCER CC1NP LL_TIM_IC_GetPolarity\n + * CCER CC2P LL_TIM_IC_GetPolarity\n + * CCER CC2NP LL_TIM_IC_GetPolarity\n + * CCER CC3P LL_TIM_IC_GetPolarity\n + * CCER CC3NP LL_TIM_IC_GetPolarity\n + * CCER CC4P LL_TIM_IC_GetPolarity\n + * CCER CC4NP LL_TIM_IC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> + SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); +} + +/** + * @brief Get captured value for input channel 1. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * input channel 1 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get captured value for input channel 2. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * input channel 2 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get captured value for input channel 3. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * input channel 3 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get captured value for input channel 4. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * input channel 4 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection + * @{ + */ +/** + * @brief Enable external clock mode 2. + * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_EnableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Disable external clock mode 2. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_DisableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Indicate whether external clock mode 2 is enabled. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); +} + +/** + * @brief Set the clock source of the counter clock. + * @note when selected clock source is external clock mode 1, the timer input + * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() + * function. This timer input must be configured by calling + * the @ref LL_TIM_IC_Config() function. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode1. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR SMS LL_TIM_SetClockSource\n + * SMCR ECE LL_TIM_SetClockSource + * @param TIMx Timer instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); +} + +/** + * @brief Set the encoder interface mode. + * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the encoder mode. + * @rmtoll SMCR SMS LL_TIM_SetEncoderMode + * @param TIMx Timer instance + * @param EncoderMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 + * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 + * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 + * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 + * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 + * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 + * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 + * @arg @ref LL_TIM_ENCODERMODE_X1_TI1 + * @arg @ref LL_TIM_ENCODERMODE_X1_TI2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration + * @{ + */ +/** + * @brief Set the trigger output (TRGO) used for timer synchronization . + * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance can operate as a master timer. + * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput + * @param TIMx Timer instance + * @param TimerSynchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO_RESET + * @arg @ref LL_TIM_TRGO_ENABLE + * @arg @ref LL_TIM_TRGO_UPDATE + * @arg @ref LL_TIM_TRGO_CC1IF + * @arg @ref LL_TIM_TRGO_OC1REF + * @arg @ref LL_TIM_TRGO_OC2REF + * @arg @ref LL_TIM_TRGO_OC3REF + * @arg @ref LL_TIM_TRGO_OC4REF + * @arg @ref LL_TIM_TRGO_ENCODERCLK + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); +} + +/** + * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . + * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance can be used for ADC synchronization. + * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 + * @param TIMx Timer Instance + * @param ADCSynchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO2_RESET + * @arg @ref LL_TIM_TRGO2_ENABLE + * @arg @ref LL_TIM_TRGO2_UPDATE + * @arg @ref LL_TIM_TRGO2_CC1F + * @arg @ref LL_TIM_TRGO2_OC1 + * @arg @ref LL_TIM_TRGO2_OC2 + * @arg @ref LL_TIM_TRGO2_OC3 + * @arg @ref LL_TIM_TRGO2_OC4 + * @arg @ref LL_TIM_TRGO2_OC5 + * @arg @ref LL_TIM_TRGO2_OC6 + * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING + * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); +} + +/** + * @brief Set the synchronization mode of a slave timer. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR SMS LL_TIM_SetSlaveMode + * @param TIMx Timer instance + * @param SlaveMode This parameter can be one of the following values: + * @arg @ref LL_TIM_SLAVEMODE_DISABLED + * @arg @ref LL_TIM_SLAVEMODE_RESET + * @arg @ref LL_TIM_SLAVEMODE_GATED + * @arg @ref LL_TIM_SLAVEMODE_TRIGGER + * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER + * @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); +} + +/** + * @brief Set the selects the trigger input to be used to synchronize the counter. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR TS LL_TIM_SetTriggerInput + * @param TIMx Timer instance + * @param TriggerInput This parameter can be one of the following values: + * @arg @ref LL_TIM_TS_ITR0 + * @arg @ref LL_TIM_TS_ITR1 + * @arg @ref LL_TIM_TS_ITR2 + * @arg @ref LL_TIM_TS_ITR3 + * @arg @ref LL_TIM_TS_ITR4 + * @arg @ref LL_TIM_TS_ITR5 + * @arg @ref LL_TIM_TS_ITR6 + * @arg @ref LL_TIM_TS_ITR7 + * @arg @ref LL_TIM_TS_ITR8 + * @arg @ref LL_TIM_TS_ITR9 + * @arg @ref LL_TIM_TS_ITR10 + * @arg @ref LL_TIM_TS_ITR11 + * @arg @ref LL_TIM_TS_ITR12 + * @arg @ref LL_TIM_TS_TI1F_ED + * @arg @ref LL_TIM_TS_TI1FP1 + * @arg @ref LL_TIM_TS_TI2FP2 + * @arg @ref LL_TIM_TS_ETRF + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); +} + +/** + * @brief Enable the Master/Slave mode. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Disable the Master/Slave mode. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Indicates whether the Master/Slave mode is enabled. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); +} + +/** + * @brief Configure the external trigger (ETR) input. + * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an external trigger input. + * @rmtoll SMCR ETP LL_TIM_ConfigETR\n + * SMCR ETPS LL_TIM_ConfigETR\n + * SMCR ETF LL_TIM_ConfigETR + * @param TIMx Timer instance + * @param ETRPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED + * @arg @ref LL_TIM_ETR_POLARITY_INVERTED + * @param ETRPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 + * @param ETRFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_FILTER_FDIV1 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, + uint32_t ETRFilter) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); +} + +/** + * @brief Select the external trigger (ETR) input source. + * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or + * not a timer instance supports ETR source selection. + * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource + * @param TIMx Timer instance + * @param ETRSource This parameter can be one of the following values: + * + * TIM1: any combination of ETR_RMP where + * + * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO + * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1 (*) + * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 + * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 + * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 + * + * TIM2: any combination of ETR_RMP where + * + * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO + * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1 (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE + * @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSA (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR + * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_ETH_PPS (*) + + * + * TIM3: any combination of ETR_RMP where + * + * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO + * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1 (*) + * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR + * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (*) + * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM5_ETR (*) + * @arg @ref LL_TIM_TIM3_ETRSOURCE_ETH_PPS (*) + * + * TIM4: any combination of ETR_RMP where (**) + * + * @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO + * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM2_ETR + * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR + * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR + * + * TIM5: any combination of ETR_RMP where (**) + * + * @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO + * @arg @ref LL_TIM_TIM5_ETRSOURCE_SAI2_FSA + * @arg @ref LL_TIM_TIM5_ETRSOURCE_SAI2_FSB + * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR + * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR + * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM4_ETR + * + * TIM8: any combination of ETR_RMP where (**) + * + * . . ETR_RMP can be one of the following values + * @arg @ref LL_TIM_TIM8_ETRSOURCE_GPIO + * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 + * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 + * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 + * + * (*) Value not defined in all devices. \n + * (**) Timer instance not available on all devices. \n + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource) +{ + MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource); +} + +/** + * @brief Enable SMS preload. + * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the preload of SMS field in SMCR register. + * @rmtoll SMCR SMSPE LL_TIM_EnableSMSPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE); +} + +/** + * @brief Disable SMS preload. + * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the preload of SMS field in SMCR register. + * @rmtoll SMCR SMSPE LL_TIM_DisableSMSPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE); +} + +/** + * @brief Indicate whether SMS preload is enabled. + * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the preload of SMS field in SMCR register. + * @rmtoll SMCR SMSPE LL_TIM_IsEnabledSMSPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL); +} + +/** + * @brief Set the preload source of SMS. + * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the preload of SMS field in SMCR register. + * @rmtoll SMCR SMSPS LL_TIM_SetSMSPreloadSource\n + * @param TIMx Timer instance + * @param PreloadSource This parameter can be one of the following values: + * @arg @ref LL_TIM_SMSPS_TIMUPDATE + * @arg @ref LL_TIM_SMSPS_INDEX + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource); +} + +/** + * @brief Get the preload source of SMS. + * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the preload of SMS field in SMCR register. + * @rmtoll SMCR SMSPS LL_TIM_GetSMSPreloadSource\n + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_SMSPS_TIMUPDATE + * @arg @ref LL_TIM_SMSPS_INDEX + */ +__STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Break_Function Break function configuration + * @{ + */ +/** + * @brief Enable the break function. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR BKE LL_TIM_EnableBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); +} + +/** + * @brief Disable the break function. + * @rmtoll BDTR BKE LL_TIM_DisableBRK + * @param TIMx Timer instance + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); +} + +/** + * @brief Configure the break input. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @note Bidirectional mode is only supported by advanced timer instances. + * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not + * a timer instance is an advanced-control timer. + * @note In bidirectional mode (BKBID bit set), the Break input is configured both + * in input mode and in open drain output mode. Any active Break event will + * assert a low logic level on the Break input to indicate an internal break + * event to external devices. + * @note When bidirectional mode isn't supported, BreakAFMode must be set to + * LL_TIM_BREAK_AFMODE_INPUT. + * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n + * BDTR BKF LL_TIM_ConfigBRK\n + * BDTR BKBID LL_TIM_ConfigBRK + * @param TIMx Timer instance + * @param BreakPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_POLARITY_LOW + * @arg @ref LL_TIM_BREAK_POLARITY_HIGH + * @param BreakFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 + * @param BreakAFMode This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_AFMODE_INPUT + * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter, + uint32_t BreakAFMode) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode); +} + +/** + * @brief Disarm the break input (when it operates in bidirectional mode). + * @note The break input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output . + * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); +} + +/** + * @brief Re-arm the break input (when it operates in bidirectional mode). + * @note The Break input is automatically armed as soon as MOE bit is set. + * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); +} + +/** + * @brief Enable the break 2 function. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); +} + +/** + * @brief Disable the break 2 function. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); +} + +/** + * @brief Configure the break 2 input. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @note Bidirectional mode is only supported by advanced timer instances. + * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not + * a timer instance is an advanced-control timer. + * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both + * in input mode and in open drain output mode. Any active Break event will + * assert a low logic level on the Break 2 input to indicate an internal break + * event to external devices. + * @note When bidirectional mode isn't supported, Break2AFMode must be set to + * LL_TIM_BREAK2_AFMODE_INPUT. + * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n + * BDTR BK2F LL_TIM_ConfigBRK2\n + * BDTR BK2BID LL_TIM_ConfigBRK2 + * @param TIMx Timer instance + * @param Break2Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_POLARITY_LOW + * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH + * @param Break2Filter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 + * @param Break2AFMode This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT + * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter, + uint32_t Break2AFMode) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode); +} + +/** + * @brief Disarm the break 2 input (when it operates in bidirectional mode). + * @note The break 2 input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output. + * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); +} + +/** + * @brief Re-arm the break 2 input (when it operates in bidirectional mode). + * @note The Break 2 input is automatically armed as soon as MOE bit is set. + * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); +} + +/** + * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n + * BDTR OSSR LL_TIM_SetOffStates + * @param TIMx Timer instance + * @param OffStateIdle This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSI_DISABLE + * @arg @ref LL_TIM_OSSI_ENABLE + * @param OffStateRun This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSR_DISABLE + * @arg @ref LL_TIM_OSSR_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); +} + +/** + * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Disable automatic output (MOE can be set only by software). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Indicate whether automatic output is enabled. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Indicates whether outputs are enabled. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the signals connected to the designated timer break input. + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n + * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n + * AF2 BK2INE LL_TIM_EnableBreakInputSource\n + * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*) + * + * (*) Value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + SET_BIT(*pReg, Source); +} + +/** + * @brief Disable the signals connected to the designated timer break input. + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n + * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n + * AF2 BK2INE LL_TIM_DisableBreakInputSource\n + * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*) + * + * (*) Value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + CLEAR_BIT(*pReg, Source); +} + +/** + * @brief Set the polarity of the break signal for the timer break input. + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n + * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n + * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n + * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*) + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_POLARITY_LOW + * @arg @ref LL_TIM_BKIN_POLARITY_HIGH + * + * (*) Value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, + uint32_t Polarity) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE)); +} +/** + * @brief Enable asymmetrical deadtime. + * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides asymmetrical deadtime. + * @rmtoll DTR2 DTAE LL_TIM_EnableAsymmetricalDeadTime + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE); +} + +/** + * @brief Disable asymmetrical dead-time. + * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides asymmetrical deadtime. + * @rmtoll DTR2 DTAE LL_TIM_DisableAsymmetricalDeadTime + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE); +} + +/** + * @brief Indicates whether asymmetrical deadtime is activated. + * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides asymmetrical deadtime. + * @rmtoll DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); +} + +/** + * @brief Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the + * rising edge of OCxN signals). + * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not + * asymmetrical dead-time insertion feature is supported by a timer instance. + * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter + * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed + * (LOCK bits in TIMx_BDTR register). + * @rmtoll DTR2 DTGF LL_TIM_SetFallingDeadTime + * @param TIMx Timer instance + * @param DeadTime between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) +{ + MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime); +} + +/** + * @brief Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and + * the rising edge of OCxN signals). + * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not + * asymmetrical dead-time insertion feature is supported by a timer instance. + * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed + * (LOCK bits in TIMx_BDTR register). + * @rmtoll DTR2 DTGF LL_TIM_GetFallingDeadTime + * @param TIMx Timer instance + * @retval Returned value can be between Min_Data=0 and Max_Data=255: + */ +__STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF)); +} + +/** + * @brief Enable deadtime preload. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides deadtime preload. + * @rmtoll DTR2 DTPE LL_TIM_EnableDeadTimePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE); +} + +/** + * @brief Disable dead-time preload. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides deadtime preload. + * @rmtoll DTR2 DTPE LL_TIM_DisableDeadTimePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE); +} + +/** + * @brief Indicates whether deadtime preload is activated. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides deadtime preload. + * @rmtoll DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration + * @{ + */ +/** + * @brief Configures the timer DMA burst feature. + * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or + * not a timer instance supports the DMA burst mode. + * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n + * DCR DBA LL_TIM_ConfigDMABurst + * @param TIMx Timer instance + * @param DMABurstBaseAddress This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER + * @arg @ref LL_TIM_DMABURST_BASEADDR_SR + * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER + * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT + * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC + * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR + * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 + * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_ECR + * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 + * @param DMABurstLength This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER + * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS + * @param DMABurstSource This parameter can be one of the following values: + * @arg @ref LL_TIM_DMA_UPDATE + * @arg @ref LL_TIM_DMA_CC1 + * @arg @ref LL_TIM_DMA_CC2 + * @arg @ref LL_TIM_DMA_CC3 + * @arg @ref LL_TIM_DMA_CC4 + * @arg @ref LL_TIM_DMA_COM + * @arg @ref LL_TIM_DMA_TRIGGER + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength, + uint32_t DMABurstSource) +{ + MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA | TIM_DCR_DBSS), + (DMABurstBaseAddress | DMABurstLength | DMABurstSource)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Encoder Encoder configuration + * @{ + */ + +/** + * @brief Enable encoder index. + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IE LL_TIM_EnableEncoderIndex + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->ECR, TIM_ECR_IE); +} + +/** + * @brief Disable encoder index. + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IE LL_TIM_DisableEncoderIndex + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->ECR, TIM_ECR_IE); +} + +/** + * @brief Indicate whether encoder index is enabled. + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IE LL_TIM_IsEnabledEncoderIndex + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U); +} + +/** + * @brief Set index direction + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IDIR LL_TIM_SetIndexDirection + * @param TIMx Timer instance + * @param IndexDirection This parameter can be one of the following values: + * @arg @ref LL_TIM_INDEX_UP_DOWN + * @arg @ref LL_TIM_INDEX_UP + * @arg @ref LL_TIM_INDEX_DOWN + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection) +{ + MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection); +} + +/** + * @brief Get actual index direction + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IDIR LL_TIM_GetIndexDirection + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_INDEX_UP_DOWN + * @arg @ref LL_TIM_INDEX_UP + * @arg @ref LL_TIM_INDEX_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR)); +} + +/** + * @brief Set index blanking + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IBLK LL_TIM_SetIndexblanking + * @param TIMx Timer instance + * @param Indexblanking This parameter can be one of the following values: + * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS + * @arg @ref LL_TIM_INDEX_BLANK_TI3 + * @arg @ref LL_TIM_INDEX_BLANK_TI4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetIndexblanking(TIM_TypeDef *TIMx, uint32_t Indexblanking) +{ + MODIFY_REG(TIMx->ECR, TIM_ECR_IBLK, Indexblanking); +} + +/** + * @brief Get actual index blanking + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IBLK LL_TIM_GetIndexblanking + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS + * @arg @ref LL_TIM_INDEX_BLANK_TI3 + * @arg @ref LL_TIM_INDEX_BLANK_TI4 + */ +__STATIC_INLINE uint32_t LL_TIM_GetIndexblanking(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IBLK)); +} + + +/** + * @brief Enable first index. + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR FIDX LL_TIM_EnableFirstIndex + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->ECR, TIM_ECR_FIDX); +} + +/** + * @brief Disable first index. + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR FIDX LL_TIM_DisableFirstIndex + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX); +} + +/** + * @brief Indicates whether first index is enabled. + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR FIDX LL_TIM_IsEnabledFirstIndex + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL); +} + +/** + * @brief Set index positioning + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IPOS LL_TIM_SetIndexPositionning + * @param TIMx Timer instance + * @param IndexPositionning This parameter can be one of the following values: + * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP + * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_UP_UP + * @arg @ref LL_TIM_INDEX_POSITION_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_UP + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning) +{ + MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning); +} + +/** + * @brief Get actual index positioning + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IPOS LL_TIM_GetIndexPositionning + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP + * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_UP_UP + * @arg @ref LL_TIM_INDEX_POSITION_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_UP + */ +__STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS)); +} + +/** + * @brief Configure encoder index. + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IDIR LL_TIM_ConfigIDX\n + * ECR IBLK LL_TIM_ConfigIDX\n + * ECR FIDX LL_TIM_ConfigIDX\n + * ECR IPOS LL_TIM_ConfigIDX + * @param TIMx Timer instance + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN + * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS or @ref LL_TIM_INDEX_BLANK_TI3 or @ref LL_TIM_INDEX_BLANK_TI4 + * @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY + * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration) +{ + MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping + * @{ + */ +/** + * @brief Remap TIM inputs (input channel, internal/external triggers). + * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not + * a some timer inputs can be remapped. + * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM2_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM2_TISEL TI2SEL LL_TIM_SetRemap\n + * TIM2_TISEL TI4SEL LL_TIM_SetRemap\n + * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n + * TIM4_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM4_TISEL TI2SEL LL_TIM_SetRemap\n + * TIM5_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM5_TISEL TI2SEL LL_TIM_SetRemap\n + * TIM8_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM12_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM13_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM14_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM15_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM15_TISEL TI2SEL LL_TIM_SetRemap\n + * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM17_TISEL TI1SEL LL_TIM_SetRemap\n + * + * @param TIMx Timer instance + * @param Remap Remap param depends on the TIMx. Description available only + * in CHM version of the User Manual (not in .pdf). + * Otherwise see Reference Manual description of TISEL registers. + * + * Below description summarizes "Timer Instance" and "Remap" param combinations: + * + * TIM1: one of the following values: + * @arg LL_TIM_TIM1_TI1_RMP_GPIO: TIM1 TI1 is connected to GPIO + * @arg LL_TIM_TIM1_TI1_RMP_COMP1: TIM1 TI1 is connected to COMP1 output (*) + * @arg LL_TIM_TIM1_TI2_RMP_GPIO: TIM1 TI2 is connected to GPIO + * @arg LL_TIM_TIM1_TI3_RMP_GPIO: TIM1 TI3 is connected to GPIO + * @arg LL_TIM_TIM1_TI4_RMP_GPIO: TIM1 TI4 is connected to GPIO + * + * TIM2: one of the following values: + * @arg LL_TIM_TIM2_TI1_RMP_GPIO: TIM2 TI1 is connected to GPIO + * @arg LL_TIM_TIM2_TI1_RMP_LSI: TIM2 TI1 is connected to LSI (*) + * @arg LL_TIM_TIM2_TI1_RMP_LSE: TIM2 TI1 is connected to LSE (*) + * @arg LL_TIM_TIM2_TI1_RMP_RTC: TIM2 TI1 is connected to RTC (*) + * @arg LL_TIM_TIM2_TI1_RMP_TIM3_TI1: TIM2 TI1 is connected to TIM3 TI1 (*) + * @arg LL_TIM_TIM2_TI1_RMP_ETH_PPS: TIM2 TI1 is connected to ETH PPS (*) + * @arg LL_TIM_TIM2_TI2_RMP_GPIO: TIM2 TI2 is connected to GPIO + * @arg LL_TIM_TIM2_TI2_RMP_HSI_1024: TIM2 TI2 is connected to HSI 1024 (*) + * @arg LL_TIM_TIM2_TI2_RMP_CSI_128: TIM2 TI2 is connected to CSI 128 (*) + * @arg LL_TIM_TIM2_TI2_RMP_MCO2: TIM2 TI2 is connected to MCO2 (*) + * @arg LL_TIM_TIM2_TI2_RMP_MCO1: TIM2 TI2 is connected to MCO1 (*) + * @arg LL_TIM_TIM2_TI3_RMP_GPIO: TIM2 TI3 is connected to GPIO + * @arg LL_TIM_TIM2_TI4_RMP_GPIO: TIM2 TI4 is connected to GPIO + * @arg LL_TIM_TIM2_TI4_RMP_COMP1: TIM2 TI4 is connected to COMP1 (*) + * + * TIM3: one of the following values: + * @arg LL_TIM_TIM3_TI1_RMP_GPIO: TIM3 TI1 is connected to GPIO + * @arg LL_TIM_TIM3_TI1_RMP_COMP1: TIM3 TI1 is connected to COMP1 output (*) + * @arg LL_TIM_TIM3_TI1_RMP_MCO1: TIM3 TI1 is connected to MCO1 (*) + * @arg LL_TIM_TIM3_TI1_RMP_TIM2_TI1: TIM3 TI1 is connected to TIM2 TI1 (*) + * @arg LL_TIM_TIM3_TI1_RMP_HSE_1MHZ: TIM3 TI1 is connected to HSE_1MHZ (*) + * @arg LL_TIM_TIM3_TI1_RMP_ETH_PPS: TIM3 TI1 is connected to ETH PPS (*) + * @arg LL_TIM_TIM3_TI2_RMP_GPIO: TIM3 TI2 is connected to GPIO + * @arg LL_TIM_TIM3_TI2_RMP_CSI_128: TIM3 TI2 is connected to CSI_128 (*) + * @arg LL_TIM_TIM3_TI2_RMP_MCO2: TIM3 TI2 is connected to MCO2 (*) + * @arg LL_TIM_TIM3_TI2_RMP_HSI_1024: TIM3 TI2 is connected to HSI_1024 (*) + * @arg LL_TIM_TIM3_TI3_RMP_GPIO: TIM3 TI3 is connected to GPIO + * @arg LL_TIM_TIM3_TI4_RMP_GPIO: TIM3 TI4 is connected to GPIO + * + * TIM4: one of the following values: (**) + * @arg LL_TIM_TIM4_TI1_RMP_GPIO: TIM4 TI1 is connected to GPIO + * @arg LL_TIM_TIM4_TI2_RMP_GPIO: TIM4 TI2 is connected to GPIO + * @arg LL_TIM_TIM4_TI3_RMP_GPIO: TIM4 TI3 is connected to GPIO + * @arg LL_TIM_TIM4_TI4_RMP_GPIO: TIM4 TI4 is connected to GPIO + * + * TIM5: one of the following values: (**) + * @arg LL_TIM_TIM5_TI1_RMP_GPIO: TIM5 TI1 is connected to GPIO + * @arg LL_TIM_TIM5_TI2_RMP_GPIO: TIM5 TI2 is connected to GPIO + * @arg LL_TIM_TIM5_TI3_RMP_GPIO: TIM5 TI3 is connected to GPIO + * @arg LL_TIM_TIM5_TI4_RMP_GPIO: TIM5 TI4 is connected to GPIO + * + * TIM8: one of the following values: (**) + * @arg LL_TIM_TIM8_TI1_RMP_GPIO: TIM8 TI1 is connected to GPIO + * @arg LL_TIM_TIM8_TI2_RMP_GPIO: TIM8 TI2 is connected to GPIO + * @arg LL_TIM_TIM8_TI3_RMP_GPIO: TIM8 TI3 is connected to GPIO + * @arg LL_TIM_TIM8_TI4_RMP_GPIO: TIM8 TI4 is connected to GPIO + * + * TIM12: one of the following values: (**) + * @arg LL_TIM_TIM12_TI1_RMP_GPIO: TIM12 TI1 is connected to GPIO + * @arg LL_TIM_TIM12_TI1_RMP_HSI_1024: TIM12 TI1 is connected to GPIO + * @arg LL_TIM_TIM12_TI1_RMP_CSI_128: TIM12 TI1 is connected to GPIO + * + * TIM13: one of the following values: (**) + * @arg LL_TIM_TIM13_TI1_RMP_GPIO: TIM13 TI1 is connected to GPIO + * + * TIM14: one of the following values: (**) + * @arg LL_TIM_TIM14_TI1_RMP_GPIO: TIM14 TI1 is connected to GPIO + * + * TIM15: one of the following values: (**) + * @arg LL_TIM_TIM15_TI1_RMP_GPIO: TIM15 TI1 is connected to GPIO + * @arg LL_TIM_TIM15_TI1_RMP_TIM2: TIM15 TI1 is connected to TIM2 + * @arg LL_TIM_TIM15_TI1_RMP_TIM3: TIM15 TI1 is connected to TIM3 + * @arg LL_TIM_TIM15_TI1_RMP_TIM4: TIM15 TI1 is connected to TIM4 + * @arg LL_TIM_TIM15_TI1_RMP_LSE: TIM15 TI1 is connected to LSE + * @arg LL_TIM_TIM15_TI1_RMP_CSI_128: TIM15 TI1 is connected to CSI/128 + * @arg LL_TIM_TIM15_TI1_RMP_MCO2: TIM15 TI1 is connected to MCO2 + * @arg LL_TIM_TIM15_TI2_RMP_GPIO: TIM15 TI1 is connected to GPIO + * @arg LL_TIM_TIM15_TI2_RMP_TIM2: TIM15 TI1 is connected to TIM2 + * @arg LL_TIM_TIM15_TI2_RMP_TIM3: TIM15 TI1 is connected to TIM3 + * @arg LL_TIM_TIM15_TI2_RMP_TIM4: TIM15 TI1 is connected to TIM4 + * + * TIM16: one of the following values: (**) + * @arg LL_TIM_TIM16_TI1_RMP_GPIO: TIM16 TI1 is connected to GPIO + * @arg LL_TIM_TIM16_TI1_RMP_LSI: TIM16 TI1 is connected to LSI + * @arg LL_TIM_TIM16_TI1_RMP_LSE: TIM16 TI1 is connected to LSE + * @arg LL_TIM_TIM16_TI1_RMP_RTC_WKUP: TIM16 TI1 is connected to RTC_WKUP + * + * TIM17: one of the following values: (**) + * @arg LL_TIM_TIM17_TI1_RMP_GPIO: TIM17 TI1 is connected to GPIO + * @arg LL_TIM_TIM17_TI1_RMP_HSE_1MHZ: TIM17 TI1 is connected to HSE_1MHZ + * @arg LL_TIM_TIM17_TI1_RMP_MCO1: TIM17 TI1 is connected to MCO1 + * + * (*) Value not defined in all devices. \n + * (**) Timer instance not available on all devices. \n + * + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) +{ + MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management + * @{ + */ +/** + * @brief Set the OCREF clear input source + * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT + * @note This function can only be used in Output compare and PWM modes. + * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource + * @param TIMx Timer instance + * @param OCRefClearInputSource This parameter can be one of the following values: + * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR + * @arg @ref LL_TIM_OCREF_CLR_INT_ETR + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource); +} +/** + * @} + */ + +/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management + * @{ + */ +/** + * @brief Clear the update interrupt flag (UIF). + * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); +} + +/** + * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). + * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). + * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). + * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). + * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). + * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). + * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). + * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). + * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). + * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); +} + +/** + * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending). + * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). + * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); +} + +/** + * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending). + * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the commutation interrupt flag (COMIF). + * @rmtoll SR COMIF LL_TIM_ClearFlag_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); +} + +/** + * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). + * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the trigger interrupt flag (TIF). + * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); +} + +/** + * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). + * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the break interrupt flag (BIF). + * @rmtoll SR BIF LL_TIM_ClearFlag_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); +} + +/** + * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). + * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the break 2 interrupt flag (B2IF). + * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); +} + +/** + * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). + * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). + * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set + * (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). + * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set + * (Capture/Compare 2 over-capture interrupt is pending). + * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). + * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set + * (Capture/Compare 3 over-capture interrupt is pending). + * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). + * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set + * (Capture/Compare 4 over-capture interrupt is pending). + * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the system break interrupt flag (SBIF). + * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); +} + +/** + * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending). + * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the transition error interrupt flag (TERRF). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll SR TERRF LL_TIM_ClearFlag_TERR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF)); +} + +/** + * @brief Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll SR TERRF LL_TIM_IsActiveFlag_TERR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the index error interrupt flag (IERRF). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll SR IERRF LL_TIM_ClearFlag_IERR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF)); +} + +/** + * @brief Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll SR IERRF LL_TIM_IsActiveFlag_IERR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the direction change interrupt flag (DIRF). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll SR DIRF LL_TIM_ClearFlag_DIR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF)); +} + +/** + * @brief Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll SR DIRF LL_TIM_IsActiveFlag_DIR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the index interrupt flag (IDXF). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll SR IDXF LL_TIM_ClearFlag_IDX + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF)); +} + +/** + * @brief Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll SR IDXF LL_TIM_IsActiveFlag_IDX + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL); +} +/** + * @} + */ + +/** @defgroup TIM_LL_EF_IT_Management IT-Management + * @{ + */ +/** + * @brief Enable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Disable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Indicates whether the update interrupt (UIE) is enabled. + * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Disable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. + * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Disable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. + * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Disable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. + * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Disable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. + * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_EnableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Disable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_DisableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Indicates whether the commutation interrupt (COMIE) is enabled. + * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Disable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Indicates whether the trigger interrupt (TIE) is enabled. + * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_EnableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Disable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_DisableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Indicates whether the break interrupt (BIE) is enabled. + * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable transition error interrupt (TERRIE). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll DIER TERRIE LL_TIM_EnableIT_TERR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TERRIE); +} + +/** + * @brief Disable transition error interrupt (TERRIE). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll DIER TERRIE LL_TIM_DisableIT_TERR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE); +} + +/** + * @brief Indicates whether the transition error interrupt (TERRIE) is enabled. + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll DIER TERRIE LL_TIM_IsEnabledIT_TERR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable index error interrupt (IERRIE). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll DIER IERRIE LL_TIM_EnableIT_IERR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_IERRIE); +} + +/** + * @brief Disable index error interrupt (IERRIE). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll DIER IERRIE LL_TIM_DisableIT_IERR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE); +} + +/** + * @brief Indicates whether the index error interrupt (IERRIE) is enabled. + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll DIER IERRIE LL_TIM_IsEnabledIT_IERR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable direction change interrupt (DIRIE). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll DIER DIRIE LL_TIM_EnableIT_DIR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_DIRIE); +} + +/** + * @brief Disable direction change interrupt (DIRIE). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll DIER DIRIE LL_TIM_DisableIT_DIR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE); +} + +/** + * @brief Indicates whether the direction change interrupt (DIRIE) is enabled. + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll DIER DIRIE LL_TIM_IsEnabledIT_DIR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable index interrupt (IDXIE). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll DIER IDXIE LL_TIM_EnableIT_IDX + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_IDXIE); +} + +/** + * @brief Disable index interrupt (IDXIE). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll DIER IDXIE LL_TIM_DisableIT_IDX + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE); +} + +/** + * @brief Indicates whether the index interrupt (IDXIE) is enabled. + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll DIER IDXIE LL_TIM_IsEnabledIT_IDX + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Management DMA Management + * @{ + */ +/** + * @brief Enable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Disable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Indicates whether the update DMA request (UDE) is enabled. + * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Disable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. + * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Disable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. + * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Disable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. + * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Disable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. + * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Disable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Indicates whether the commutation DMA request (COMDE) is enabled. + * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Disable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Indicates whether the trigger interrupt (TDE) is enabled. + * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management + * @{ + */ +/** + * @brief Generate an update event. + * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_UG); +} + +/** + * @brief Generate Capture/Compare 1 event. + * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC1G); +} + +/** + * @brief Generate Capture/Compare 2 event. + * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC2G); +} + +/** + * @brief Generate Capture/Compare 3 event. + * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC3G); +} + +/** + * @brief Generate Capture/Compare 4 event. + * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC4G); +} + +/** + * @brief Generate commutation event. + * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_COMG); +} + +/** + * @brief Generate trigger event. + * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_TG); +} + +/** + * @brief Generate break event. + * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_BG); +} + +/** + * @brief Generate break 2 event. + * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_B2G); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions + * @{ + */ + +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx); +void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); +void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); +void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H5xx_LL_TIM_H */ diff --git a/benchmark/interface/Drivers/STM32H5xx_HAL_Driver/LICENSE.md b/benchmark/interface/Drivers/STM32H5xx_HAL_Driver/LICENSE.md new file mode 100644 index 00000000..9226612a --- /dev/null +++ b/benchmark/interface/Drivers/STM32H5xx_HAL_Driver/LICENSE.md @@ -0,0 +1,27 @@ +Copyright 2021 STMicroelectronics. +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its contributors +may be used to endorse or promote products derived from this software without +specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/benchmark/interface/README.md b/benchmark/interface/README.md index 1a60ce65..dae1384d 100644 --- a/benchmark/interface/README.md +++ b/benchmark/interface/README.md @@ -1,5 +1,16 @@ # Interface board software +## Installing Firmware + - A pre-built binary is in this directory named `benchmark-interface.elf`. + - Use the ST Programmer appliation to load the elf file onto the board. + - Connect the board to your host's USB port using connector CN10 (also labeled ST-Link). This one is next to two LEDs. + - To avoid confusion, it is easiest if the interface board is the only board connected to your computer for this step. + - Open the ST Programmer application. + - In the ST-Link panel, click "Connect". + - There should be a tab labeled '+' in the top of the main area. Click this and select "Open File". Navigate to `benchmark-interface.elf`. + - Click the "Download" button. + - The log window at the bottom should show "File download complete". + ## Features - Interacts with `runner` python code on the host machine. - Interacts with the device under test @@ -116,6 +127,47 @@ https://www.st.com/resource/en/user_manual/um3143-discovery-kit-with-stm32h573ii https://www.st.com/resource/en/reference_manual/rm0481-stm32h563h573-and-stm32h562-armbased-32bit-mcus-stmicroelectronics.pdf https://app.trinetexpense.com/users/login +## Troubleshooting notes +- This is specifically for the 'Nonetype' error when trying to run the test in the runner folder +- Make sure you are using the updated STM32 compiler code. In the UART file specifically the baud rate should be 115200 +- Access the device port using Device manager and use PUTTY or a similar software to connect to the device + - Keep in mind if the device is configured properly you only need the Interface board plugged into the computer +- Send commands such as dut profile%, and dut name% +- dut name% should return + ```serial + m-dut-passthrough(name) + m-ready + [dut]: m-name-dut-[unspecified] + [dut]: m-ready + ``` +- dut profile% should return + ```serial + m-dut-passthrough(profile) + m-ready + [dut]: m-profile-[ULPMark for tinyML Firmware V0.0.1] + [dut]: m-model-[kws01] + [dut]: m-ready + ``` +- If you have to send the commands multiple times to get the correct results you will need to make a change to the 'device_under_test.py' file + +- The code changes will involve adding a counter loop so the program tries to fetch the data multiple times before moving on. Heres an example for the get name function +```python +def _get_name(self): + name_retrieved = False + for attempt in range(5): # This line allows for us to retry fetching the name + print(f"Attempting to retrieve name, attempt {attempt + 1}") + for l in self._port.send_command("name"): + match = re.match(r'^m-(name)-dut-\[([^]]+)]$', l) + if match: + self.__setattr__(f"_{match.group(1)}", match.group(2)) + name_retrieved = True + if name_retrieved: + print(f"Device name retrieved: {self._name}") # Print name for troubleshooting purposes + break + print(f"WARNING: Attempt {attempt + 1} failed, retrying...") + time.sleep(1) # Wait for 1 second before retrying +``` + ## Open Items - Add a second thread for the `Task::TaskRunner` - I2C playback does not finish the audio clip (need to send the remainder of the buffer after all the blocks are sent) diff --git a/benchmark/interface/STM32CubeIDE/.project b/benchmark/interface/STM32CubeIDE/.project index 62ad6db0..85d7e614 100644 --- a/benchmark/interface/STM32CubeIDE/.project +++ b/benchmark/interface/STM32CubeIDE/.project @@ -304,6 +304,11 @@ 1 PARENT-1-PROJECT_LOC/Core/Src/gpio.c + + Application/User/Core/i2c.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/i2c.c + Application/User/Core/icache.c 1 @@ -354,6 +359,11 @@ 1 PARENT-1-PROJECT_LOC/Core/Src/stm32h5xx_it.c + + Application/User/Core/tim.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/tim.c + Application/User/Core/tx_initialize_low_level.S 1 diff --git a/benchmark/interface/STM32CubeIDE/.settings/language.settings.xml b/benchmark/interface/STM32CubeIDE/.settings/language.settings.xml deleted file mode 100644 index fe09ee1c..00000000 --- a/benchmark/interface/STM32CubeIDE/.settings/language.settings.xml +++ /dev/null @@ -1,25 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/benchmark/interface/STM32CubeIDE/.settings/stm32cubeide.project.prefs b/benchmark/interface/STM32CubeIDE/.settings/stm32cubeide.project.prefs deleted file mode 100644 index 763f93f7..00000000 --- a/benchmark/interface/STM32CubeIDE/.settings/stm32cubeide.project.prefs +++ /dev/null @@ -1,4 +0,0 @@ -2F62501ED4689FB349E356AB974DBE57=D14451AD13420E8B490C774158332D67 -8DF89ED150041C4CBC7CB9A9CAA90856=D14451AD13420E8B490C774158332D67 -DC22A860405A8BF2F2C095E5B6529F12=16CFD4EBFD1E580AF063F322918CE8AB -eclipse.preferences.version=1 diff --git a/benchmark/interface/STM32CubeIDE/Application/User/Core/baud_config.c b/benchmark/interface/STM32CubeIDE/Application/User/Core/baud_config.c new file mode 100644 index 00000000..09b193c0 --- /dev/null +++ b/benchmark/interface/STM32CubeIDE/Application/User/Core/baud_config.c @@ -0,0 +1,68 @@ +#include // <-- Fixes uint32_t issues +#include "stm32h5xx_hal.h" // <-- Fixes HAL_StatusTypeDef and Flash HAL +#include "baud_config.h" // Your header (if it exists) +#include "stm32h5xx_hal_flash.h" + +#define CONFIG_FLASH_ADDR ((uint32_t)0x080FF800U) // Ensure 16-byte aligned and valid range +#define CONFIG_FLASH_SECTOR FLASH_SECTOR_127 // Choose based on actual layout +#define CONFIG_FLASH_BANK FLASH_BANK_1 + +typedef struct __attribute__((aligned(16))) { + uint32_t baudrate; + uint32_t reserved[3]; +} FlashBaudRate_t; + +static const FlashBaudRate_t *flash_data = (FlashBaudRate_t *)CONFIG_FLASH_ADDR; + +uint32_t LoadBaudRateFromFlashWithDefault(uint32_t fallback) +{ + uint32_t baud = flash_data->baudrate; + + if (baud == 0xFFFFFFFF || baud == 0 || baud > 2000000) { + return fallback; + } + + return baud; +} +uint32_t LoadBaudRateFromFlash(void) +{ + return LoadBaudRateFromFlashWithDefault(DEFAULT_BAUDRATE); +} + +HAL_StatusTypeDef SaveBaudRateToFlash(uint32_t baud) +{ + HAL_StatusTypeDef status; + FlashBaudRate_t data_to_write = { + .baudrate = baud, + .reserved = {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF} + }; + + HAL_FLASH_Unlock(); + + FLASH_EraseInitTypeDef erase = { + .TypeErase = FLASH_TYPEERASE_SECTORS, + .Banks = CONFIG_FLASH_BANK, + .Sector = CONFIG_FLASH_SECTOR, + .NbSectors = 1 + }; + + uint32_t sector_error = 0; + status = HAL_FLASHEx_Erase(&erase, §or_error); + if (status != HAL_OK) { + HAL_FLASH_Lock(); + return status; + } + + status = HAL_FLASH_Program(FLASH_TYPEPROGRAM_QUADWORD, + CONFIG_FLASH_ADDR, + (uint32_t)&data_to_write); + + HAL_FLASH_Lock(); + + // Optional: Confirm write + if (status == HAL_OK && flash_data->baudrate != baud) { + return HAL_ERROR; + } + + return status; +} diff --git a/benchmark/interface/STM32CubeIDE/Application/User/Core/exti_handlers.c b/benchmark/interface/STM32CubeIDE/Application/User/Core/exti_handlers.c new file mode 100644 index 00000000..6090710e --- /dev/null +++ b/benchmark/interface/STM32CubeIDE/Application/User/Core/exti_handlers.c @@ -0,0 +1,46 @@ +/* + * exti_handlers.c + * + * Created on: Feb 10, 2025 + * Author: jeremy + */ + +#include "sdmmc.h" +#include "tx_api.h" +#include "CLI/InterfaceMenu.h" +#include + +//extern void record_detection(void); + +extern TX_SEMAPHORE card_in_semaphore; +extern TX_SEMAPHORE card_out_semaphore; +/** + * @brief EXTI line detection callback. + * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin) +{ + if(GPIO_Pin == uSD_DETECT_Pin) + { + tx_semaphore_ceiling_put(&card_in_semaphore, 1); + } + else if(GPIO_Pin == WW_DET_IN_Pin) { + Record_WW_Detection(); + } + else if(GPIO_Pin == DUT_DUTY_CYCLE_Pin) { + Record_Dutycycle_Stop(); + } +} + +void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin) +{ + if(GPIO_Pin == uSD_DETECT_Pin) + { + tx_semaphore_ceiling_put(&card_out_semaphore, 1); + } + else if(GPIO_Pin == DUT_DUTY_CYCLE_Pin) { + Record_Dutycycle_Start(); + } +} + diff --git a/benchmark/interface/STM32CubeIDE/Application/User/Test/DeviceUnderTest.h b/benchmark/interface/STM32CubeIDE/Application/User/Test/DeviceUnderTest.h new file mode 100644 index 00000000..ee39e0bf --- /dev/null +++ b/benchmark/interface/STM32CubeIDE/Application/User/Test/DeviceUnderTest.h @@ -0,0 +1,13 @@ +/* + * DeviceUnderTest.h + * + * Created on: Feb 15, 2025 + * Author: jeremy + */ + +#ifndef APPLICATION_USER_TEST_DEVICEUNDERTEST_H_ +#define APPLICATION_USER_TEST_DEVICEUNDERTEST_H_ + + + +#endif /* APPLICATION_USER_TEST_DEVICEUNDERTEST_H_ */ diff --git a/benchmark/interface/STM32CubeIDE/benchmark-interface.launch b/benchmark/interface/STM32CubeIDE/benchmark-interface.launch deleted file mode 100644 index 987155ea..00000000 --- a/benchmark/interface/STM32CubeIDE/benchmark-interface.launch +++ /dev/null @@ -1,93 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmark/interface/benchmark-interface.elf b/benchmark/interface/benchmark-interface.elf new file mode 100755 index 00000000..826e0947 Binary files /dev/null and b/benchmark/interface/benchmark-interface.elf differ diff --git a/benchmark/interface/benchmark-interface.ioc b/benchmark/interface/benchmark-interface.ioc index 5b6141f2..272322c7 100644 --- a/benchmark/interface/benchmark-interface.ioc +++ b/benchmark/interface/benchmark-interface.ioc @@ -1,7 +1,7 @@ #MicroXplorer Configuration settings - do not modify ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_3 ADC1.ClockPrescaler=ADC_CLOCK_ASYNC_DIV2 -ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,MonitoredBy-0\#ChannelRegularConversion,NbrOfConversionFlag,master,ClockPrescaler +ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,MonitoredBy-0\#ChannelRegularConversion,NbrOfConversionFlag,ClockPrescaler,master ADC1.MonitoredBy-0\#ChannelRegularConversion=__NULL ADC1.NbrOfConversionFlag=1 ADC1.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE @@ -39,6 +39,8 @@ GPDMA2.IPParameters=PRIORITY_LL_GPDMACH2,LINKEDLISTMODE_GPDMACH2 GPDMA2.LINKEDLISTMODE_GPDMACH2=DMA_LINKEDLIST_CIRCULAR GPDMA2.PRIORITY_LL_GPDMACH2=DMA_HIGH_PRIORITY GPIO.groupedBy=Show All +I2C1.IPParameters=Timing +I2C1.Timing=0x108088B1 KeepUserPlacement=false Linkedlist.MDMA_Channel0.GP_SW.0.BlkHWRequest=DMA_BREQ_SINGLE_BURST Linkedlist.MDMA_Channel0.GP_SW.0.DataHandling=NONE @@ -153,21 +155,23 @@ Mcu.ContextProject=TrustZoneDisabled Mcu.Family=STM32H5 Mcu.IP0=ADC1 Mcu.IP1=ADC2 -Mcu.IP10=ICACHE -Mcu.IP11=LINKEDLIST -Mcu.IP12=MEMORYMAP -Mcu.IP13=NVIC -Mcu.IP14=OCTOSPI1 -Mcu.IP15=PWR -Mcu.IP16=RCC -Mcu.IP17=SAI1 -Mcu.IP18=SDMMC1 -Mcu.IP19=SYS +Mcu.IP10=I2C1 +Mcu.IP11=ICACHE +Mcu.IP12=LINKEDLIST +Mcu.IP13=MEMORYMAP +Mcu.IP14=NVIC +Mcu.IP15=OCTOSPI1 +Mcu.IP16=PWR +Mcu.IP17=RCC +Mcu.IP18=SAI1 +Mcu.IP19=SDMMC1 Mcu.IP2=BOOTPATH -Mcu.IP20=THREADX -Mcu.IP21=UCPD1 -Mcu.IP22=USART1 -Mcu.IP23=USART3 +Mcu.IP20=SYS +Mcu.IP21=THREADX +Mcu.IP22=TIM2 +Mcu.IP23=UCPD1 +Mcu.IP24=USART1 +Mcu.IP25=USART3 Mcu.IP3=CORTEX_M33_NS Mcu.IP4=DEBUG Mcu.IP5=ETH @@ -175,7 +179,7 @@ Mcu.IP6=FILEX Mcu.IP7=FMC Mcu.IP8=GPDMA1 Mcu.IP9=GPDMA2 -Mcu.IPNb=24 +Mcu.IPNb=26 Mcu.Name=STM32H573IIKxQ Mcu.Package=UFBGA176 Mcu.Pin0=PI7 @@ -226,8 +230,9 @@ Mcu.Pin138=VP_SAI1_VP_$IpInstance_SAIB_SAI_BASIC Mcu.Pin139=VP_SYS_VS_tim6 Mcu.Pin14=PE1 Mcu.Pin140=VP_THREADX_VS_RTOSJjThreadXJjCoreJjDefault -Mcu.Pin141=VP_BOOTPATH_VS_BOOTPATH -Mcu.Pin142=VP_MEMORYMAP_VS_MEMORYMAP +Mcu.Pin141=VP_TIM2_VS_ClockSourceINT +Mcu.Pin142=VP_BOOTPATH_VS_BOOTPATH +Mcu.Pin143=VP_MEMORYMAP_VS_MEMORYMAP Mcu.Pin15=PB6 Mcu.Pin16=PB3(JTDO/TRACESWO) Mcu.Pin17=PG12 @@ -321,7 +326,7 @@ Mcu.Pin96=PF12 Mcu.Pin97=PE9 Mcu.Pin98=PE14 Mcu.Pin99=PE15 -Mcu.PinsNb=143 +Mcu.PinsNb=144 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32H573IIKxQ @@ -330,6 +335,8 @@ MxDb.Version=DB.6.0.100 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false NVIC.EXTI14_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true\:true +NVIC.EXTI15_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true\:true +NVIC.EXTI5_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true\:true NVIC.ForceEnableDMAVector=true NVIC.GPDMA1_Channel2_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true\:true NVIC.GPDMA2_Channel2_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true\:true @@ -473,17 +480,21 @@ PB4(NJTRST).GPIOParameters=GPIO_Label PB4(NJTRST).GPIO_Label=NJTRST PB4(NJTRST).Locked=true PB4(NJTRST).Signal=DEBUG_JTRST -PB5.GPIOParameters=GPIO_Label -PB5.GPIO_Label=ARD_D3 +PB5.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI +PB5.GPIO_Label=DUT_DUTY_CYCLE +PB5.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING +PB5.GPIO_PuPd=GPIO_PULLUP PB5.Locked=true -PB5.Signal=S_TIM3_CH2 +PB5.Signal=GPXTI5 PB6.GPIOParameters=GPIO_Label PB6.GPIO_Label=I2C1_SCL PB6.Locked=true +PB6.Mode=I2C PB6.Signal=I2C1_SCL PB7.GPIOParameters=GPIO_Label PB7.GPIO_Label=I2C1_SDA PB7.Locked=true +PB7.Mode=I2C PB7.Signal=I2C1_SDA PC1.GPIOParameters=GPIO_Label PC1.GPIO_Label=RMII_MDC @@ -762,10 +773,12 @@ PG14.GPIO_Label=TRACED1 PG14.Locked=true PG14.Mode=Trace_Synchro_4bits_JTAG PG14.Signal=DEBUG_TRACED1 -PG15.GPIOParameters=GPIO_Label -PG15.GPIO_Label=ARD_D2 +PG15.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI +PG15.GPIO_Label=WW_DET_IN +PG15.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING +PG15.GPIO_PuPd=GPIO_PULLUP PG15.Locked=true -PG15.Signal=GPIO_Output +PG15.Signal=GPXTI15 PG3.GPIOParameters=GPIO_Label PG3.GPIO_Label=LCD_CTP_RST PG3.Locked=true @@ -927,7 +940,7 @@ ProjectManager.ToolChainLocation= ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_GPDMA1_Init-GPDMA1-false-HAL-true,4-MX_GPDMA2_Init-GPDMA2-false-HAL-true,5-MX_ETH_Init-ETH-false-HAL-true,6-MX_FMC_Init-FMC-false-HAL-true,7-MX_ICACHE_Init-ICACHE-false-HAL-true,8-MX_OCTOSPI1_Init-OCTOSPI1-false-HAL-true,9-MX_SDMMC1_SD_Init-SDMMC1-false-HAL-true,10-MX_UCPD1_Init-UCPD1-false-LL-true,11-MX_USART1_UART_Init-USART1-false-HAL-true,12-MX_USART3_UART_Init-USART3-false-HAL-true,13-MX_ADC1_Init-ADC1-false-HAL-true,14-MX_FileX_Init-FILEX-true-HAL-false,15-MX_ADC2_Init-ADC2-false-HAL-true,16-MX_SAI1_Init-SAI1-false-HAL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_GPDMA1_Init-GPDMA1-false-HAL-true,4-MX_GPDMA2_Init-GPDMA2-false-HAL-true,5-MX_ETH_Init-ETH-false-HAL-true,6-MX_FMC_Init-FMC-false-HAL-true,7-MX_ICACHE_Init-ICACHE-false-HAL-true,8-MX_OCTOSPI1_Init-OCTOSPI1-false-HAL-true,9-MX_SDMMC1_SD_Init-SDMMC1-false-HAL-true,10-MX_UCPD1_Init-UCPD1-false-LL-true,11-MX_USART1_UART_Init-USART1-false-HAL-true,12-MX_USART3_UART_Init-USART3-false-HAL-true,13-MX_ADC1_Init-ADC1-false-HAL-true,14-MX_FileX_Init-FILEX-true-HAL-false,15-MX_ADC2_Init-ADC2-false-HAL-true,16-MX_SAI1_Init-SAI1-false-HAL-true,17-MX_I2C1_Init-I2C1-false-HAL-true,18-MX_TIM2_Init-TIM2-false-HAL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true RCC.ADCFreq_Value=64000701.904296875 RCC.AHBFreq_Value=64000701.904296875 RCC.APB1Freq_Value=64000701.904296875 @@ -956,7 +969,7 @@ RCC.I2C2Freq_Value=64000701.904296875 RCC.I2C3Freq_Value=64000701.904296875 RCC.I2C4Freq_Value=64000701.904296875 RCC.I3C1Freq_Value=64000701.904296875 -RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CECFreq_Value,CKPERFreq_Value,CRSFreq_Value,CSI_VALUE,CortexFreq_Value,DACFreq_Value,EPOD_VALUE,ETHFreq_Value,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSIDiv,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I3C1Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM3Freq_Value,LPTIM4Freq_Value,LPTIM5Freq_Value,LPTIM6Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSIRC_VALUE,MCO1PinFreq_Value,MCO2PinFreq_Value,OCTOSPIMFreq_Value,PLL2FRACN,PLL2N,PLL2PoutputFreq_Value,PLL2QoutputFreq_Value,PLL2RoutputFreq_Value,PLL3PoutputFreq_Value,PLL3QoutputFreq_Value,PLL3RoutputFreq_Value,PLLFRACN,PLLM,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC1Freq_Value,SDMMC2Freq_Value,SPI1Freq_Value,SPI2Freq_Value,SPI3Freq_Value,SPI4Freq_Value,SPI5Freq_Value,SPI6Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART12Freq_Value,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,UART9Freq_Value,UCPD1outputFreq_Value,USART10Freq_Value,USART11Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOPLL2OutputFreq_Value,VCOPLL3OutputFreq_Value +RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CECFreq_Value,CKPERFreq_Value,CRSFreq_Value,CSI_VALUE,CortexFreq_Value,DACFreq_Value,EPOD_VALUE,ETHFreq_Value,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSIDiv,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I3C1Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM3Freq_Value,LPTIM4Freq_Value,LPTIM5Freq_Value,LPTIM6Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSIRC_VALUE,MCO1PinFreq_Value,MCO2PinFreq_Value,OCTOSPIMFreq_Value,PLL2FRACN,PLL2M,PLL2N,PLL2P,PLL2PoutputFreq_Value,PLL2QoutputFreq_Value,PLL2RoutputFreq_Value,PLL2Source,PLL3FRACN,PLL3PoutputFreq_Value,PLL3QoutputFreq_Value,PLL3RoutputFreq_Value,PLLFRACN,PLLM,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC1Freq_Value,SDMMC2Freq_Value,SPI1Freq_Value,SPI2Freq_Value,SPI3Freq_Value,SPI4Freq_Value,SPI5Freq_Value,SPI6Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART12Freq_Value,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,UART9Freq_Value,UCPD1outputFreq_Value,USART10Freq_Value,USART11Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOPLL2OutputFreq_Value,VCOPLL3OutputFreq_Value RCC.LPTIM1Freq_Value=64000701.904296875 RCC.LPTIM2Freq_Value=64000701.904296875 RCC.LPTIM3Freq_Value=64000701.904296875 @@ -971,10 +984,14 @@ RCC.MCO1PinFreq_Value=64000000 RCC.MCO2PinFreq_Value=64000701.904296875 RCC.OCTOSPIMFreq_Value=64000701.904296875 RCC.PLL2FRACN=0 -RCC.PLL2N=32 -RCC.PLL2PoutputFreq_Value=64000000 -RCC.PLL2QoutputFreq_Value=64000000 -RCC.PLL2RoutputFreq_Value=64000000 +RCC.PLL2M=25 +RCC.PLL2N=96 +RCC.PLL2P=5 +RCC.PLL2PoutputFreq_Value=49152000 +RCC.PLL2QoutputFreq_Value=122880000 +RCC.PLL2RoutputFreq_Value=122880000 +RCC.PLL2Source=RCC_PLL2_SOURCE_HSI +RCC.PLL3FRACN=0 RCC.PLL3PoutputFreq_Value=258000000 RCC.PLL3QoutputFreq_Value=258000000 RCC.PLL3RoutputFreq_Value=258000000 @@ -986,8 +1003,8 @@ RCC.PLLQoutputFreq_Value=64000701.904296875 RCC.PLLSourceVirtual=RCC_PLL1_SOURCE_HSE RCC.PWRFreq_Value=64000701.904296875 RCC.RNGFreq_Value=48000000 -RCC.SAI1Freq_Value=64000000 -RCC.SAI2Freq_Value=64000000 +RCC.SAI1Freq_Value=49152000 +RCC.SAI2Freq_Value=49152000 RCC.SDMMC1Freq_Value=64000701.904296875 RCC.SDMMC2Freq_Value=64000701.904296875 RCC.SPI1Freq_Value=64000701.904296875 @@ -1012,18 +1029,20 @@ RCC.USART2Freq_Value=64000701.904296875 RCC.USART3Freq_Value=64000701.904296875 RCC.USART6Freq_Value=64000701.904296875 RCC.USBFreq_Value=48000000 -RCC.VCOInput2Freq_Value=4000000 +RCC.VCOInput2Freq_Value=2560000 RCC.VCOInput3Freq_Value=4000000 RCC.VCOInputFreq_Value=12500000 RCC.VCOOutputFreq_Value=128001403.80859375 -RCC.VCOPLL2OutputFreq_Value=128000000 +RCC.VCOPLL2OutputFreq_Value=245760000 RCC.VCOPLL3OutputFreq_Value=516000000 -SAI1.ErrorAudioFreq-SAI_B_MasterWithClock=30.2 % -SAI1.IPParameters=Instance-SAI_B_MasterWithClock,VirtualMode-SAI_B_MasterWithClock,MckOutput-SAI_B_MasterWithClock,RealAudioFreq-SAI_B_MasterWithClock,ErrorAudioFreq-SAI_B_MasterWithClock,InitProtocol-SAI_B_MasterWithClock,VirtualProtocol-SAI_B_BASIC +SAI1.AudioFrequency-SAI_B_MasterWithClock=SAI_AUDIO_FREQUENCY_16K +SAI1.ErrorAudioFreq-SAI_B_MasterWithClock=0.0 % +SAI1.IPParameters=Instance-SAI_B_MasterWithClock,VirtualMode-SAI_B_MasterWithClock,MckOutput-SAI_B_MasterWithClock,RealAudioFreq-SAI_B_MasterWithClock,ErrorAudioFreq-SAI_B_MasterWithClock,InitProtocol-SAI_B_MasterWithClock,VirtualProtocol-SAI_B_BASIC,NoDivider-SAI_B_MasterWithClock,AudioFrequency-SAI_B_MasterWithClock SAI1.InitProtocol-SAI_B_MasterWithClock=Enable SAI1.Instance-SAI_B_MasterWithClock=SAI$Index_Block_B SAI1.MckOutput-SAI_B_MasterWithClock=SAI_MCK_OUTPUT_ENABLE -SAI1.RealAudioFreq-SAI_B_MasterWithClock=250.0 KHz +SAI1.NoDivider-SAI_B_MasterWithClock=SAI_MASTERDIVIDER_ENABLE +SAI1.RealAudioFreq-SAI_B_MasterWithClock=16.0 KHz SAI1.VirtualMode-SAI_B_MasterWithClock=VM_MASTER SAI1.VirtualProtocol-SAI_B_BASIC=VM_BASIC_PROTOCOL SDMMC1.ClockDiv=4 @@ -1086,12 +1105,14 @@ SH.GPXTI13.0=GPIO_EXTI13 SH.GPXTI13.ConfNb=1 SH.GPXTI14.0=GPIO_EXTI14 SH.GPXTI14.ConfNb=1 +SH.GPXTI15.0=GPIO_EXTI15 +SH.GPXTI15.ConfNb=1 +SH.GPXTI5.0=GPIO_EXTI5 +SH.GPXTI5.ConfNb=1 SH.GPXTI7.0=GPIO_EXTI7 SH.GPXTI7.ConfNb=1 SH.S_TIM1_CH1.0=TIM1_CH1 SH.S_TIM1_CH1.ConfNb=1 -SH.S_TIM3_CH2.0=TIM3_CH2 -SH.S_TIM3_CH2.ConfNb=1 SH.S_TIM5_CH1.0=TIM5_CH1 SH.S_TIM5_CH1.ConfNb=1 SH.S_TIM5_CH2.0=TIM5_CH2 @@ -1102,11 +1123,13 @@ THREADX.TX_APP_CREATION=1 THREADX.TX_APP_GENERATE_INIT_CODE=true THREADX.TX_APP_MEM_POOL_SIZE=2 * 1024 THREADX.TX_APP_STACK_SIZE=1024 -USART1.BaudRate=921600 +TIM2.IPParameters=Prescaler +TIM2.Prescaler=640-1 +USART1.BaudRate=115200 USART1.FIFOMode=FIFOMODE_ENABLE USART1.IPParameters=VirtualMode,BaudRate,FIFOMode USART1.VirtualMode=VM_ASYNC -USART3.BaudRate=9600 +USART3.BaudRate=115200 USART3.FIFOMode=FIFOMODE_ENABLE USART3.IPParameters=VirtualMode,BaudRate,FIFOMode USART3.VirtualMode=VM_ASYNC @@ -1136,5 +1159,8 @@ VP_SYS_VS_tim6.Mode=TIM6 VP_SYS_VS_tim6.Signal=SYS_VS_tim6 VP_THREADX_VS_RTOSJjThreadXJjCoreJjDefault.Mode=Core_Default VP_THREADX_VS_RTOSJjThreadXJjCoreJjDefault.Signal=THREADX_VS_RTOSJjThreadXJjCoreJjDefault +VP_TIM2_VS_ClockSourceINT.Mode=Internal +VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT board=STM32H573I-DK boardIOC=true +isbadioc=false diff --git a/benchmark/interface/check_files.sh b/benchmark/interface/check_files.sh new file mode 100644 index 00000000..89ba3634 --- /dev/null +++ b/benchmark/interface/check_files.sh @@ -0,0 +1,618 @@ + +file_list=( \ + ".mxproject" \ + "AZURE_RTOS/App/app_azure_rtos.c" \ + "AZURE_RTOS/App/app_azure_rtos.h" \ + "AZURE_RTOS/App/app_azure_rtos_config.h" \ + "Core/Inc/adc.h" \ + "Core/Inc/app_threadx.h" \ + "Core/Inc/eth.h" \ + "Core/Inc/fmc.h" \ + "Core/Inc/gpdma.h" \ + "Core/Inc/gpio.h" \ + "Core/Inc/icache.h" \ + "Core/Inc/linked_list.h" \ + "Core/Inc/main.h" \ + "Core/Inc/memorymap.h" \ + "Core/Inc/octospi.h" \ + "Core/Inc/sai.h" \ + "Core/Inc/sdmmc.h" \" \ + "Core/Inc/stm32_assert.h" \ + "Core/Inc/stm32h5xx_hal_conf.h" \ + "Core/Inc/stm32h5xx_it.h" \ + "Core/Inc/tx_user.h" \ + "Core/Inc/ucpd.h" \ + "Core/Inc/usart.h" \ + "Core/Src/adc.c" \ + "Core/Src/app_threadx.c" \ + "Core/Src/eth.c" \ + "Core/Src/fmc.c" \ + "Core/Src/gpdma.c" \ + "Core/Src/gpio.c" \ + "Core/Src/icache.c" \ + "Core/Src/linked_list.c" \ + "Core/Src/main.c" \ + "Core/Src/memorymap.c" \ + "Core/Src/octospi.c" \ + "Core/Src/sai.c" \ + "Core/Src/sdmmc.c" \ + "Core/Src/stm32h5xx_hal_msp.c" \ + "Core/Src/stm32h5xx_hal_timebase_tim.c" \ + "Core/Src/stm32h5xx_it.c" \ + "Core/Src/tx_initialize_low_level.S" \ + "Core/Src/ucpd.c" \ + "Core/Src/usart.c" \ + "Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h" \ + "Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h" \ + "Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h" \ + "Drivers/CMSIS/Device/ST/STM32H5xx/LICENSE.txt" \ + "Drivers/CMSIS/Include/cachel1_armv7.h" \ + "Drivers/CMSIS/Include/cmsis_armcc.h" \ + "Drivers/CMSIS/Include/cmsis_armclang.h" \ + "Drivers/CMSIS/Include/cmsis_armclang_ltm.h" \ + "Drivers/CMSIS/Include/cmsis_compiler.h" \ + "Drivers/CMSIS/Include/cmsis_gcc.h" \ + "Drivers/CMSIS/Include/cmsis_iccarm.h" \ + "Drivers/CMSIS/Include/cmsis_version.h" \ + "Drivers/CMSIS/Include/core_armv81mml.h" \ + "Drivers/CMSIS/Include/core_armv8mbl.h" \ + "Drivers/CMSIS/Include/core_armv8mml.h" \ + "Drivers/CMSIS/Include/core_cm0.h" \ + "Drivers/CMSIS/Include/core_cm0plus.h" \ + "Drivers/CMSIS/Include/core_cm1.h" \ + "Drivers/CMSIS/Include/core_cm23.h" \ + "Drivers/CMSIS/Include/core_cm3.h" \ + "Drivers/CMSIS/Include/core_cm33.h" \ + "Drivers/CMSIS/Include/core_cm35p.h" \ + "Drivers/CMSIS/Include/core_cm4.h" \ + "Drivers/CMSIS/Include/core_cm55.h" \ + "Drivers/CMSIS/Include/core_cm7.h" \ + "Drivers/CMSIS/Include/core_cm85.h" \ + "Drivers/CMSIS/Include/core_sc000.h" \ + "Drivers/CMSIS/Include/core_sc300.h" \ + "Drivers/CMSIS/Include/core_starmc1.h" \ + "Drivers/CMSIS/Include/mpu_armv7.h" \ + "Drivers/CMSIS/Include/mpu_armv8.h" \ + "Drivers/CMSIS/Include/pac_armv81.h" \ + "Drivers/CMSIS/Include/pmu_armv8.h" \ + "Drivers/CMSIS/Include/tz_context.h" \ + "Drivers/CMSIS/LICENSE.txt" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc_ex.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth_ex.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c_ex.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sai.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sai_ex.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sd.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sd_ex.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sram.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim_ex.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_xspi.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crs.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dlyb.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_fmc.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i2c.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_lpuart.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_sdmmc.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_ucpd.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_usart.h" \ + "Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h" \ + "Drivers/STM32H5xx_HAL_Driver/LICENSE.txt" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc_ex.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth_ex.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c_ex.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai_ex.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd_ex.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim_ex.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_xspi.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dlyb.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dma.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmc.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_gpio.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rcc.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_sdmmc.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_ucpd.c" \ + "Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_utils.c" \ + "FileX/App/app_filex.c" \ + "FileX/App/app_filex.h" \ + "FileX/App/fx_user.h" \ + "FileX/Target/fx_stm32_sd_driver.h" \ + "FileX/Target/fx_stm32_sd_driver_glue.c" \ + "Middlewares/ST/filex/LICENSE.txt" \ + "Middlewares/ST/filex/LICENSED-HARDWARE.txt" \ + "Middlewares/ST/filex/common/drivers/fx_stm32_sd_driver.c" \ + "Middlewares/ST/filex/common/inc/fx_api.h" \ + "Middlewares/ST/filex/common/inc/fx_directory.h" \ + "Middlewares/ST/filex/common/inc/fx_directory_exFAT.h" \ + "Middlewares/ST/filex/common/inc/fx_fault_tolerant.h" \ + "Middlewares/ST/filex/common/inc/fx_file.h" \ + "Middlewares/ST/filex/common/inc/fx_media.h" \ + "Middlewares/ST/filex/common/inc/fx_system.h" \ + "Middlewares/ST/filex/common/inc/fx_unicode.h" \ + "Middlewares/ST/filex/common/inc/fx_user_sample.h" \ + "Middlewares/ST/filex/common/inc/fx_utility.h" \ + "Middlewares/ST/filex/common/src/fx_directory_attributes_read.c" \ + "Middlewares/ST/filex/common/src/fx_directory_attributes_set.c" \ + "Middlewares/ST/filex/common/src/fx_directory_create.c" \ + "Middlewares/ST/filex/common/src/fx_directory_default_get.c" \ + "Middlewares/ST/filex/common/src/fx_directory_default_get_copy.c" \ + "Middlewares/ST/filex/common/src/fx_directory_default_set.c" \ + "Middlewares/ST/filex/common/src/fx_directory_delete.c" \ + "Middlewares/ST/filex/common/src/fx_directory_entry_read.c" \ + "Middlewares/ST/filex/common/src/fx_directory_entry_write.c" \ + "Middlewares/ST/filex/common/src/fx_directory_exFAT_entry_read.c" \ + "Middlewares/ST/filex/common/src/fx_directory_exFAT_entry_write.c" \ + "Middlewares/ST/filex/common/src/fx_directory_exFAT_free_search.c" \ + "Middlewares/ST/filex/common/src/fx_directory_exFAT_unicode_entry_write.c" \ + "Middlewares/ST/filex/common/src/fx_directory_first_entry_find.c" \ + "Middlewares/ST/filex/common/src/fx_directory_first_full_entry_find.c" \ + "Middlewares/ST/filex/common/src/fx_directory_free_search.c" \ + "Middlewares/ST/filex/common/src/fx_directory_information_get.c" \ + "Middlewares/ST/filex/common/src/fx_directory_local_path_clear.c" \ + "Middlewares/ST/filex/common/src/fx_directory_local_path_get.c" \ + "Middlewares/ST/filex/common/src/fx_directory_local_path_get_copy.c" \ + "Middlewares/ST/filex/common/src/fx_directory_local_path_restore.c" \ + "Middlewares/ST/filex/common/src/fx_directory_local_path_set.c" \ + "Middlewares/ST/filex/common/src/fx_directory_long_name_get.c" \ + "Middlewares/ST/filex/common/src/fx_directory_long_name_get_extended.c" \ + "Middlewares/ST/filex/common/src/fx_directory_name_extract.c" \ + "Middlewares/ST/filex/common/src/fx_directory_name_test.c" \ + "Middlewares/ST/filex/common/src/fx_directory_next_entry_find.c" \ + "Middlewares/ST/filex/common/src/fx_directory_next_full_entry_find.c" \ + "Middlewares/ST/filex/common/src/fx_directory_rename.c" \ + "Middlewares/ST/filex/common/src/fx_directory_search.c" \ + "Middlewares/ST/filex/common/src/fx_directory_short_name_get.c" \ + "Middlewares/ST/filex/common/src/fx_directory_short_name_get_extended.c" \ + "Middlewares/ST/filex/common/src/fx_fault_tolerant_add_FAT_log.c" \ + "Middlewares/ST/filex/common/src/fx_fault_tolerant_add_bitmap_log.c" \ + "Middlewares/ST/filex/common/src/fx_fault_tolerant_add_checksum_log.c" \ + "Middlewares/ST/filex/common/src/fx_fault_tolerant_add_dir_log.c" \ + "Middlewares/ST/filex/common/src/fx_fault_tolerant_apply_logs.c" \ + "Middlewares/ST/filex/common/src/fx_fault_tolerant_calculate_checksum.c" \ + "Middlewares/ST/filex/common/src/fx_fault_tolerant_cleanup_FAT_chain.c" \ + "Middlewares/ST/filex/common/src/fx_fault_tolerant_create_log_file.c" \ + "Middlewares/ST/filex/common/src/fx_fault_tolerant_enable.c" \ + "Middlewares/ST/filex/common/src/fx_fault_tolerant_read_FAT.c" \ + "Middlewares/ST/filex/common/src/fx_fault_tolerant_read_directory_sector.c" \ + "Middlewares/ST/filex/common/src/fx_fault_tolerant_read_log_file.c" \ + "Middlewares/ST/filex/common/src/fx_fault_tolerant_recover.c" \ + "Middlewares/ST/filex/common/src/fx_fault_tolerant_reset_log_file.c" \ + "Middlewares/ST/filex/common/src/fx_fault_tolerant_set_FAT_chain.c" \ + "Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_end.c" \ + "Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_fail.c" \ + "Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_start.c" \ + "Middlewares/ST/filex/common/src/fx_fault_tolerant_write_log_file.c" \ + "Middlewares/ST/filex/common/src/fx_file_allocate.c" \ + "Middlewares/ST/filex/common/src/fx_file_attributes_read.c" \ + "Middlewares/ST/filex/common/src/fx_file_attributes_set.c" \ + "Middlewares/ST/filex/common/src/fx_file_best_effort_allocate.c" \ + "Middlewares/ST/filex/common/src/fx_file_close.c" \ + "Middlewares/ST/filex/common/src/fx_file_create.c" \ + "Middlewares/ST/filex/common/src/fx_file_date_time_set.c" \ + "Middlewares/ST/filex/common/src/fx_file_delete.c" \ + "Middlewares/ST/filex/common/src/fx_file_extended_allocate.c" \ + "Middlewares/ST/filex/common/src/fx_file_extended_best_effort_allocate.c" \ + "Middlewares/ST/filex/common/src/fx_file_extended_relative_seek.c" \ + "Middlewares/ST/filex/common/src/fx_file_extended_seek.c" \ + "Middlewares/ST/filex/common/src/fx_file_extended_truncate.c" \ + "Middlewares/ST/filex/common/src/fx_file_extended_truncate_release.c" \ + "Middlewares/ST/filex/common/src/fx_file_open.c" \ + "Middlewares/ST/filex/common/src/fx_file_read.c" \ + "Middlewares/ST/filex/common/src/fx_file_relative_seek.c" \ + "Middlewares/ST/filex/common/src/fx_file_rename.c" \ + "Middlewares/ST/filex/common/src/fx_file_seek.c" \ + "Middlewares/ST/filex/common/src/fx_file_truncate.c" \ + "Middlewares/ST/filex/common/src/fx_file_truncate_release.c" \ + "Middlewares/ST/filex/common/src/fx_file_write.c" \ + "Middlewares/ST/filex/common/src/fx_file_write_notify_set.c" \ + "Middlewares/ST/filex/common/src/fx_media_abort.c" \ + "Middlewares/ST/filex/common/src/fx_media_boot_info_extract.c" \ + "Middlewares/ST/filex/common/src/fx_media_cache_invalidate.c" \ + "Middlewares/ST/filex/common/src/fx_media_check.c" \ + "Middlewares/ST/filex/common/src/fx_media_check_FAT_chain_check.c" \ + "Middlewares/ST/filex/common/src/fx_media_check_lost_cluster_check.c" \ + "Middlewares/ST/filex/common/src/fx_media_close.c" \ + "Middlewares/ST/filex/common/src/fx_media_close_notify_set.c" \ + "Middlewares/ST/filex/common/src/fx_media_exFAT_format.c" \ + "Middlewares/ST/filex/common/src/fx_media_extended_space_available.c" \ + "Middlewares/ST/filex/common/src/fx_media_flush.c" \ + "Middlewares/ST/filex/common/src/fx_media_format.c" \ + "Middlewares/ST/filex/common/src/fx_media_format_oem_name_set.c" \ + "Middlewares/ST/filex/common/src/fx_media_format_type_set.c" \ + "Middlewares/ST/filex/common/src/fx_media_format_volume_id_set.c" \ + "Middlewares/ST/filex/common/src/fx_media_open.c" \ + "Middlewares/ST/filex/common/src/fx_media_open_notify_set.c" \ + "Middlewares/ST/filex/common/src/fx_media_read.c" \ + "Middlewares/ST/filex/common/src/fx_media_space_available.c" \ + "Middlewares/ST/filex/common/src/fx_media_volume_get.c" \ + "Middlewares/ST/filex/common/src/fx_media_volume_get_extended.c" \ + "Middlewares/ST/filex/common/src/fx_media_volume_set.c" \ + "Middlewares/ST/filex/common/src/fx_media_write.c" \ + "Middlewares/ST/filex/common/src/fx_partition_offset_calculate.c" \ + "Middlewares/ST/filex/common/src/fx_system_date_get.c" \ + "Middlewares/ST/filex/common/src/fx_system_date_set.c" \ + "Middlewares/ST/filex/common/src/fx_system_initialize.c" \ + "Middlewares/ST/filex/common/src/fx_system_time_get.c" \ + "Middlewares/ST/filex/common/src/fx_system_time_set.c" \ + "Middlewares/ST/filex/common/src/fx_system_timer_entry.c" \ + "Middlewares/ST/filex/common/src/fx_unicode_directory_create.c" \ + "Middlewares/ST/filex/common/src/fx_unicode_directory_entry_change.c" \ + "Middlewares/ST/filex/common/src/fx_unicode_directory_entry_read.c" \ + "Middlewares/ST/filex/common/src/fx_unicode_directory_rename.c" \ + "Middlewares/ST/filex/common/src/fx_unicode_directory_search.c" \ + "Middlewares/ST/filex/common/src/fx_unicode_file_create.c" \ + "Middlewares/ST/filex/common/src/fx_unicode_file_rename.c" \ + "Middlewares/ST/filex/common/src/fx_unicode_length_get.c" \ + "Middlewares/ST/filex/common/src/fx_unicode_length_get_extended.c" \ + "Middlewares/ST/filex/common/src/fx_unicode_name_get.c" \ + "Middlewares/ST/filex/common/src/fx_unicode_name_get_extended.c" \ + "Middlewares/ST/filex/common/src/fx_unicode_short_name_get.c" \ + "Middlewares/ST/filex/common/src/fx_unicode_short_name_get_extended.c" \ + "Middlewares/ST/filex/common/src/fx_utility_16_unsigned_read.c" \ + "Middlewares/ST/filex/common/src/fx_utility_16_unsigned_write.c" \ + "Middlewares/ST/filex/common/src/fx_utility_32_unsigned_read.c" \ + "Middlewares/ST/filex/common/src/fx_utility_32_unsigned_write.c" \ + "Middlewares/ST/filex/common/src/fx_utility_64_unsigned_read.c" \ + "Middlewares/ST/filex/common/src/fx_utility_64_unsigned_write.c" \ + "Middlewares/ST/filex/common/src/fx_utility_FAT_entry_read.c" \ + "Middlewares/ST/filex/common/src/fx_utility_FAT_entry_write.c" \ + "Middlewares/ST/filex/common/src/fx_utility_FAT_flush.c" \ + "Middlewares/ST/filex/common/src/fx_utility_FAT_map_flush.c" \ + "Middlewares/ST/filex/common/src/fx_utility_FAT_sector_get.c" \ + "Middlewares/ST/filex/common/src/fx_utility_absolute_path_get.c" \ + "Middlewares/ST/filex/common/src/fx_utility_exFAT_allocate_new_cluster.c" \ + "Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_cache_prepare.c" \ + "Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_cache_update.c" \ + "Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_flush.c" \ + "Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_free_cluster_find.c" \ + "Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_initialize.c" \ + "Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_start_sector_get.c" \ + "Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_free.c" \ + "Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_state_get.c" \ + "Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_state_set.c" \ + "Middlewares/ST/filex/common/src/fx_utility_exFAT_geometry_check.c" \ + "Middlewares/ST/filex/common/src/fx_utility_exFAT_name_hash_get.c" \ + "Middlewares/ST/filex/common/src/fx_utility_exFAT_size_calculate.c" \ + "Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_checksum_verify.c" \ + "Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_checksum_write.c" \ + "Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_format.c" \ + "Middlewares/ST/filex/common/src/fx_utility_exFAT_system_sector_write.c" \ + "Middlewares/ST/filex/common/src/fx_utility_exFAT_unicode_name_hash_get.c" \ + "Middlewares/ST/filex/common/src/fx_utility_exFAT_upcase_table.c" \ + "Middlewares/ST/filex/common/src/fx_utility_logical_sector_cache_entry_read.c" \ + "Middlewares/ST/filex/common/src/fx_utility_logical_sector_flush.c" \ + "Middlewares/ST/filex/common/src/fx_utility_logical_sector_read.c" \ + "Middlewares/ST/filex/common/src/fx_utility_logical_sector_write.c" \ + "Middlewares/ST/filex/common/src/fx_utility_memory_copy.c" \ + "Middlewares/ST/filex/common/src/fx_utility_memory_set.c" \ + "Middlewares/ST/filex/common/src/fx_utility_string_length_get.c" \ + "Middlewares/ST/filex/common/src/fx_utility_token_length_get.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_attributes_read.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_attributes_set.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_create.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_default_get.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_default_get_copy.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_default_set.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_delete.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_first_entry_find.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_first_full_entry_find.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_information_get.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_local_path_clear.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_local_path_get.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_local_path_get_copy.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_local_path_restore.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_local_path_set.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_long_name_get.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_long_name_get_extended.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_name_test.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_next_entry_find.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_next_full_entry_find.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_rename.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_short_name_get.c" \ + "Middlewares/ST/filex/common/src/fxe_directory_short_name_get_extended.c" \ + "Middlewares/ST/filex/common/src/fxe_fault_tolerant_enable.c" \ + "Middlewares/ST/filex/common/src/fxe_file_allocate.c" \ + "Middlewares/ST/filex/common/src/fxe_file_attributes_read.c" \ + "Middlewares/ST/filex/common/src/fxe_file_attributes_set.c" \ + "Middlewares/ST/filex/common/src/fxe_file_best_effort_allocate.c" \ + "Middlewares/ST/filex/common/src/fxe_file_close.c" \ + "Middlewares/ST/filex/common/src/fxe_file_create.c" \ + "Middlewares/ST/filex/common/src/fxe_file_date_time_set.c" \ + "Middlewares/ST/filex/common/src/fxe_file_delete.c" \ + "Middlewares/ST/filex/common/src/fxe_file_extended_allocate.c" \ + "Middlewares/ST/filex/common/src/fxe_file_extended_best_effort_allocate.c" \ + "Middlewares/ST/filex/common/src/fxe_file_extended_relative_seek.c" \ + "Middlewares/ST/filex/common/src/fxe_file_extended_seek.c" \ + "Middlewares/ST/filex/common/src/fxe_file_extended_truncate.c" \ + "Middlewares/ST/filex/common/src/fxe_file_extended_truncate_release.c" \ + "Middlewares/ST/filex/common/src/fxe_file_open.c" \ + "Middlewares/ST/filex/common/src/fxe_file_read.c" \ + "Middlewares/ST/filex/common/src/fxe_file_relative_seek.c" \ + "Middlewares/ST/filex/common/src/fxe_file_rename.c" \ + "Middlewares/ST/filex/common/src/fxe_file_seek.c" \ + "Middlewares/ST/filex/common/src/fxe_file_truncate.c" \ + "Middlewares/ST/filex/common/src/fxe_file_truncate_release.c" \ + "Middlewares/ST/filex/common/src/fxe_file_write.c" \ + "Middlewares/ST/filex/common/src/fxe_file_write_notify_set.c" \ + "Middlewares/ST/filex/common/src/fxe_media_abort.c" \ + "Middlewares/ST/filex/common/src/fxe_media_cache_invalidate.c" \ + "Middlewares/ST/filex/common/src/fxe_media_check.c" \ + "Middlewares/ST/filex/common/src/fxe_media_close.c" \ + "Middlewares/ST/filex/common/src/fxe_media_close_notify_set.c" \ + "Middlewares/ST/filex/common/src/fxe_media_exFAT_format.c" \ + "Middlewares/ST/filex/common/src/fxe_media_extended_space_available.c" \ + "Middlewares/ST/filex/common/src/fxe_media_flush.c" \ + "Middlewares/ST/filex/common/src/fxe_media_format.c" \ + "Middlewares/ST/filex/common/src/fxe_media_open.c" \ + "Middlewares/ST/filex/common/src/fxe_media_open_notify_set.c" \ + "Middlewares/ST/filex/common/src/fxe_media_read.c" \ + "Middlewares/ST/filex/common/src/fxe_media_space_available.c" \ + "Middlewares/ST/filex/common/src/fxe_media_volume_get.c" \ + "Middlewares/ST/filex/common/src/fxe_media_volume_get_extended.c" \ + "Middlewares/ST/filex/common/src/fxe_media_volume_set.c" \ + "Middlewares/ST/filex/common/src/fxe_media_write.c" \ + "Middlewares/ST/filex/common/src/fxe_system_date_get.c" \ + "Middlewares/ST/filex/common/src/fxe_system_date_set.c" \ + "Middlewares/ST/filex/common/src/fxe_system_time_get.c" \ + "Middlewares/ST/filex/common/src/fxe_system_time_set.c" \ + "Middlewares/ST/filex/common/src/fxe_unicode_directory_create.c" \ + "Middlewares/ST/filex/common/src/fxe_unicode_directory_rename.c" \ + "Middlewares/ST/filex/common/src/fxe_unicode_file_create.c" \ + "Middlewares/ST/filex/common/src/fxe_unicode_file_rename.c" \ + "Middlewares/ST/filex/common/src/fxe_unicode_name_get.c" \ + "Middlewares/ST/filex/common/src/fxe_unicode_name_get_extended.c" \ + "Middlewares/ST/filex/common/src/fxe_unicode_short_name_get.c" \ + "Middlewares/ST/filex/common/src/fxe_unicode_short_name_get_extended.c" \ + "Middlewares/ST/filex/ports/generic/inc/fx_port.h" \ + "Middlewares/ST/threadx/LICENSE.txt" \ + "Middlewares/ST/threadx/LICENSED-HARDWARE.txt" \ + "Middlewares/ST/threadx/common/inc/tx_api.h" \ + "Middlewares/ST/threadx/common/inc/tx_block_pool.h" \ + "Middlewares/ST/threadx/common/inc/tx_byte_pool.h" \ + "Middlewares/ST/threadx/common/inc/tx_event_flags.h" \ + "Middlewares/ST/threadx/common/inc/tx_initialize.h" \ + "Middlewares/ST/threadx/common/inc/tx_mutex.h" \ + "Middlewares/ST/threadx/common/inc/tx_queue.h" \ + "Middlewares/ST/threadx/common/inc/tx_semaphore.h" \ + "Middlewares/ST/threadx/common/inc/tx_thread.h" \ + "Middlewares/ST/threadx/common/inc/tx_timer.h" \ + "Middlewares/ST/threadx/common/inc/tx_trace.h" \ + "Middlewares/ST/threadx/common/src/tx_block_allocate.c" \ + "Middlewares/ST/threadx/common/src/tx_block_pool_cleanup.c" \ + "Middlewares/ST/threadx/common/src/tx_block_pool_create.c" \ + "Middlewares/ST/threadx/common/src/tx_block_pool_delete.c" \ + "Middlewares/ST/threadx/common/src/tx_block_pool_info_get.c" \ + "Middlewares/ST/threadx/common/src/tx_block_pool_initialize.c" \ + "Middlewares/ST/threadx/common/src/tx_block_pool_prioritize.c" \ + "Middlewares/ST/threadx/common/src/tx_block_release.c" \ + "Middlewares/ST/threadx/common/src/tx_byte_allocate.c" \ + "Middlewares/ST/threadx/common/src/tx_byte_pool_cleanup.c" \ + "Middlewares/ST/threadx/common/src/tx_byte_pool_create.c" \ + "Middlewares/ST/threadx/common/src/tx_byte_pool_delete.c" \ + "Middlewares/ST/threadx/common/src/tx_byte_pool_info_get.c" \ + "Middlewares/ST/threadx/common/src/tx_byte_pool_initialize.c" \ + "Middlewares/ST/threadx/common/src/tx_byte_pool_prioritize.c" \ + "Middlewares/ST/threadx/common/src/tx_byte_pool_search.c" \ + "Middlewares/ST/threadx/common/src/tx_byte_release.c" \ + "Middlewares/ST/threadx/common/src/tx_event_flags_cleanup.c" \ + "Middlewares/ST/threadx/common/src/tx_event_flags_create.c" \ + "Middlewares/ST/threadx/common/src/tx_event_flags_delete.c" \ + "Middlewares/ST/threadx/common/src/tx_event_flags_get.c" \ + "Middlewares/ST/threadx/common/src/tx_event_flags_info_get.c" \ + "Middlewares/ST/threadx/common/src/tx_event_flags_initialize.c" \ + "Middlewares/ST/threadx/common/src/tx_event_flags_set.c" \ + "Middlewares/ST/threadx/common/src/tx_event_flags_set_notify.c" \ + "Middlewares/ST/threadx/common/src/tx_initialize_high_level.c" \ + "Middlewares/ST/threadx/common/src/tx_initialize_kernel_enter.c" \ + "Middlewares/ST/threadx/common/src/tx_initialize_kernel_setup.c" \ + "Middlewares/ST/threadx/common/src/tx_mutex_cleanup.c" \ + "Middlewares/ST/threadx/common/src/tx_mutex_create.c" \ + "Middlewares/ST/threadx/common/src/tx_mutex_delete.c" \ + "Middlewares/ST/threadx/common/src/tx_mutex_get.c" \ + "Middlewares/ST/threadx/common/src/tx_mutex_info_get.c" \ + "Middlewares/ST/threadx/common/src/tx_mutex_initialize.c" \ + "Middlewares/ST/threadx/common/src/tx_mutex_prioritize.c" \ + "Middlewares/ST/threadx/common/src/tx_mutex_priority_change.c" \ + "Middlewares/ST/threadx/common/src/tx_mutex_put.c" \ + "Middlewares/ST/threadx/common/src/tx_queue_cleanup.c" \ + "Middlewares/ST/threadx/common/src/tx_queue_create.c" \ + "Middlewares/ST/threadx/common/src/tx_queue_delete.c" \ + "Middlewares/ST/threadx/common/src/tx_queue_flush.c" \ + "Middlewares/ST/threadx/common/src/tx_queue_front_send.c" \ + "Middlewares/ST/threadx/common/src/tx_queue_info_get.c" \ + "Middlewares/ST/threadx/common/src/tx_queue_initialize.c" \ + "Middlewares/ST/threadx/common/src/tx_queue_prioritize.c" \ + "Middlewares/ST/threadx/common/src/tx_queue_receive.c" \ + "Middlewares/ST/threadx/common/src/tx_queue_send.c" \ + "Middlewares/ST/threadx/common/src/tx_queue_send_notify.c" \ + "Middlewares/ST/threadx/common/src/tx_semaphore_ceiling_put.c" \ + "Middlewares/ST/threadx/common/src/tx_semaphore_cleanup.c" \ + "Middlewares/ST/threadx/common/src/tx_semaphore_create.c" \ + "Middlewares/ST/threadx/common/src/tx_semaphore_delete.c" \ + "Middlewares/ST/threadx/common/src/tx_semaphore_get.c" \ + "Middlewares/ST/threadx/common/src/tx_semaphore_info_get.c" \ + "Middlewares/ST/threadx/common/src/tx_semaphore_initialize.c" \ + "Middlewares/ST/threadx/common/src/tx_semaphore_prioritize.c" \ + "Middlewares/ST/threadx/common/src/tx_semaphore_put.c" \ + "Middlewares/ST/threadx/common/src/tx_semaphore_put_notify.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_create.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_delete.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_entry_exit_notify.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_identify.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_info_get.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_initialize.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_preemption_change.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_priority_change.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_relinquish.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_reset.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_resume.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_shell_entry.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_sleep.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_stack_analyze.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_stack_error_handler.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_stack_error_notify.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_suspend.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_system_preempt_check.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_system_resume.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_system_suspend.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_terminate.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_time_slice.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_time_slice_change.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_timeout.c" \ + "Middlewares/ST/threadx/common/src/tx_thread_wait_abort.c" \ + "Middlewares/ST/threadx/common/src/tx_time_get.c" \ + "Middlewares/ST/threadx/common/src/tx_time_set.c" \ + "Middlewares/ST/threadx/common/src/tx_timer_activate.c" \ + "Middlewares/ST/threadx/common/src/tx_timer_change.c" \ + "Middlewares/ST/threadx/common/src/tx_timer_create.c" \ + "Middlewares/ST/threadx/common/src/tx_timer_deactivate.c" \ + "Middlewares/ST/threadx/common/src/tx_timer_delete.c" \ + "Middlewares/ST/threadx/common/src/tx_timer_expiration_process.c" \ + "Middlewares/ST/threadx/common/src/tx_timer_info_get.c" \ + "Middlewares/ST/threadx/common/src/tx_timer_initialize.c" \ + "Middlewares/ST/threadx/common/src/tx_timer_system_activate.c" \ + "Middlewares/ST/threadx/common/src/tx_timer_system_deactivate.c" \ + "Middlewares/ST/threadx/common/src/tx_timer_thread_entry.c" \ + "Middlewares/ST/threadx/common/src/txe_block_allocate.c" \ + "Middlewares/ST/threadx/common/src/txe_block_pool_create.c" \ + "Middlewares/ST/threadx/common/src/txe_block_pool_delete.c" \ + "Middlewares/ST/threadx/common/src/txe_block_pool_info_get.c" \ + "Middlewares/ST/threadx/common/src/txe_block_pool_prioritize.c" \ + "Middlewares/ST/threadx/common/src/txe_block_release.c" \ + "Middlewares/ST/threadx/common/src/txe_byte_allocate.c" \ + "Middlewares/ST/threadx/common/src/txe_byte_pool_create.c" \ + "Middlewares/ST/threadx/common/src/txe_byte_pool_delete.c" \ + "Middlewares/ST/threadx/common/src/txe_byte_pool_info_get.c" \ + "Middlewares/ST/threadx/common/src/txe_byte_pool_prioritize.c" \ + "Middlewares/ST/threadx/common/src/txe_byte_release.c" \ + "Middlewares/ST/threadx/common/src/txe_event_flags_create.c" \ + "Middlewares/ST/threadx/common/src/txe_event_flags_delete.c" \ + "Middlewares/ST/threadx/common/src/txe_event_flags_get.c" \ + "Middlewares/ST/threadx/common/src/txe_event_flags_info_get.c" \ + "Middlewares/ST/threadx/common/src/txe_event_flags_set.c" \ + "Middlewares/ST/threadx/common/src/txe_event_flags_set_notify.c" \ + "Middlewares/ST/threadx/common/src/txe_mutex_create.c" \ + "Middlewares/ST/threadx/common/src/txe_mutex_delete.c" \ + "Middlewares/ST/threadx/common/src/txe_mutex_get.c" \ + "Middlewares/ST/threadx/common/src/txe_mutex_info_get.c" \ + "Middlewares/ST/threadx/common/src/txe_mutex_prioritize.c" \ + "Middlewares/ST/threadx/common/src/txe_mutex_put.c" \ + "Middlewares/ST/threadx/common/src/txe_queue_create.c" \ + "Middlewares/ST/threadx/common/src/txe_queue_delete.c" \ + "Middlewares/ST/threadx/common/src/txe_queue_flush.c" \ + "Middlewares/ST/threadx/common/src/txe_queue_front_send.c" \ + "Middlewares/ST/threadx/common/src/txe_queue_info_get.c" \ + "Middlewares/ST/threadx/common/src/txe_queue_prioritize.c" \ + "Middlewares/ST/threadx/common/src/txe_queue_receive.c" \ + "Middlewares/ST/threadx/common/src/txe_queue_send.c" \ + "Middlewares/ST/threadx/common/src/txe_queue_send_notify.c" \ + "Middlewares/ST/threadx/common/src/txe_semaphore_ceiling_put.c" \ + "Middlewares/ST/threadx/common/src/txe_semaphore_create.c" \ + "Middlewares/ST/threadx/common/src/txe_semaphore_delete.c" \ + "Middlewares/ST/threadx/common/src/txe_semaphore_get.c" \ + "Middlewares/ST/threadx/common/src/txe_semaphore_info_get.c" \ + "Middlewares/ST/threadx/common/src/txe_semaphore_prioritize.c" \ + "Middlewares/ST/threadx/common/src/txe_semaphore_put.c" \ + "Middlewares/ST/threadx/common/src/txe_semaphore_put_notify.c" \ + "Middlewares/ST/threadx/common/src/txe_thread_create.c" \ + "Middlewares/ST/threadx/common/src/txe_thread_delete.c" \ + "Middlewares/ST/threadx/common/src/txe_thread_entry_exit_notify.c" \ + "Middlewares/ST/threadx/common/src/txe_thread_info_get.c" \ + "Middlewares/ST/threadx/common/src/txe_thread_preemption_change.c" \ + "Middlewares/ST/threadx/common/src/txe_thread_priority_change.c" \ + "Middlewares/ST/threadx/common/src/txe_thread_relinquish.c" \ + "Middlewares/ST/threadx/common/src/txe_thread_reset.c" \ + "Middlewares/ST/threadx/common/src/txe_thread_resume.c" \ + "Middlewares/ST/threadx/common/src/txe_thread_suspend.c" \ + "Middlewares/ST/threadx/common/src/txe_thread_terminate.c" \ + "Middlewares/ST/threadx/common/src/txe_thread_time_slice_change.c" \ + "Middlewares/ST/threadx/common/src/txe_thread_wait_abort.c" \ + "Middlewares/ST/threadx/common/src/txe_timer_activate.c" \ + "Middlewares/ST/threadx/common/src/txe_timer_change.c" \ + "Middlewares/ST/threadx/common/src/txe_timer_create.c" \ + "Middlewares/ST/threadx/common/src/txe_timer_deactivate.c" \ + "Middlewares/ST/threadx/common/src/txe_timer_delete.c" \ + "Middlewares/ST/threadx/common/src/txe_timer_info_get.c" \ + "Middlewares/ST/threadx/ports/cortex_m33/gnu/inc/tx_port.h" \ + "Middlewares/ST/threadx/ports/cortex_m33/gnu/inc/tx_secure_interface.h" \ + "Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_context_restore.S" \ + "Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_context_save.S" \ + "Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_interrupt_control.S" \ + "Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_interrupt_disable.S" \ + "Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_interrupt_restore.S" \ + "Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_schedule.S" \ + "Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_stack_build.S" \ + "Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_thread_system_return.S" \ + "Middlewares/ST/threadx/ports/cortex_m33/gnu/src/tx_timer_interrupt.S" \ + "STM32CubeIDE/.project" \ + "benchmark-interface.ioc" \ + ) + +echo "list built" + +for file in "${file_list[@]}"; do + if git diff -b -- "$file" | grep -q '.'; then + echo "$file" + else + git checkout "$file" + fi +done + + +#### + + diff --git a/benchmark/interface/copy_drivers.sh b/benchmark/interface/copy_drivers.sh new file mode 100644 index 00000000..a8e76fe4 --- /dev/null +++ b/benchmark/interface/copy_drivers.sh @@ -0,0 +1,12 @@ +cp -n ~/STM32Cube/Repository/STM32Cube_FW_H5_V1.1.1/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim.h ./Drivers/STM32H5xx_HAL_Driver/Inc +cp -n ~/STM32Cube/Repository/STM32Cube_FW_H5_V1.1.1/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c ./Drivers/STM32H5xx_HAL_Driver/Src + +cp -n ~/STM32Cube/Repository/STM32Cube_FW_H5_V1.1.1/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim_ex.h ./Drivers/STM32H5xx_HAL_Driver/Inc +cp -n ~/STM32Cube/Repository/STM32Cube_FW_H5_V1.1.1/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim_ex.c ./Drivers/STM32H5xx_HAL_Driver/Src + +cp -n ~/STM32Cube/Repository/STM32Cube_FW_H5_V1.1.1/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c.h ./Drivers/STM32H5xx_HAL_Driver/Inc +cp -n ~/STM32Cube/Repository/STM32Cube_FW_H5_V1.1.1/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c ./Drivers/STM32H5xx_HAL_Driver/Src + +cp -n ~/STM32Cube/Repository/STM32Cube_FW_H5_V1.1.1/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c_ex.h ./Drivers/STM32H5xx_HAL_Driver/Inc +cp -n ~/STM32Cube/Repository/STM32Cube_FW_H5_V1.1.1/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c_ex.c ./Drivers/STM32H5xx_HAL_Driver/Src + diff --git a/benchmark/reference_submissions/streaming_wakeword/README.md b/benchmark/reference_submissions/streaming_wakeword/README.md new file mode 100644 index 00000000..5776b991 --- /dev/null +++ b/benchmark/reference_submissions/streaming_wakeword/README.md @@ -0,0 +1,30 @@ + +In this directory, are two projects, `sww_ref_l4r5zi` and `sww_testing_l4r5zi`, both targeted at the NUCLEO L4R5ZI reference board. + +### Test Project +The test project `sww_testing_l4r5zi` is primarily intended for testing individual components of the system, such as running a model on a static input tensor, running feature extraction, and verifying I2S communication. +This project is designed to take commands over UART (via USB and the ST-LINK connector) directly from the host at 115200 baud. Each command is terminated with a '%' character. +* name -- print out an identifying message +* run_model -- run the NN model. An optional argument class0, class1, or class2 runs the model on a selected input that is expected to return 0 (WW), 1 (silent), or 2(other) +* extract -- run the feature extractor on the first block of a predefined wav form (test_wav_marvin) +* i2scap -- Captures about 1s of stereo audio over an I2S link +* log -- The I2S capture function can write debug messages to a log. Prints and clears that log. +* help -- Print a help message + +To demonstrate an I2S transaction, you will need to have a stereo (2-channel) wav file on the SD card on the interface board. Assume that file is named `test.wav`. Connect the I2S ports as described below in "I2S Connections" and connect both boards to the host via USB. Establish a terminal connection to each of them. Optionally type `name%` into each terminal to verify that UART communication is working and that you know which device is on which terminal. Start I2S reception on the DUT with the command `i2scap%`. Then start I2S transmission on the interface board with the command `play happy_2ch.wav%`. The length of the capture is defined by the variable `g_i2s_wav_len` in sww_util.c. After capturing that many (currently 8192) samples, it will print the values out in a format that is relatively easy to import into python. If you want to check the recorded samples against the original file, you'll need to turn on some kind of log capture in your terminal program. (I use `screen -L /dev/cu.usbmodelXXXX 115200`, but the `XXXX` part changes whenever the device is reconnected.) + + + +### Reference Project +The main reference project `sww_ref_l4r5zi` will be a complete working implementation of the the streaming wakeword detection benchmark. + + +### I2S Connections +For both projects, you should connect the I2S port on the DUT to the I2S port on the interface board (STM32H573I-DK). On the interface board, the I2S connection is on CN6, the PMOD connector. On the DUT, it is on CN9, the lower left connector (with the ST-LINK connector on top) on the top of the board. + +| DUT Signal | DUT Pin | Interface Board Signal | Interface Board Pin | +| --------- | ------- | --------------------- | ------------------- | +| `SAI1_FS_A` | CN9.16 | `SAI1_FS_B` | CN6.2 | +| `SAI1_SCK_A`| CN9.18 | `SAI1_SCK_B` | CN6.3 | +| `SAI1_SD_A` | CN9.20 | `SAI1_SD_B` | CN6.1 | + diff --git a/benchmark/reference_submissions/streaming_wakeword/setup_example.sh b/benchmark/reference_submissions/streaming_wakeword/setup_example.sh deleted file mode 100755 index 976c6e14..00000000 --- a/benchmark/reference_submissions/streaming_wakeword/setup_example.sh +++ /dev/null @@ -1,47 +0,0 @@ -# define TensorFlow version as git branch/tag/hash -TF_VERSION=v2.3.1 - -# enable CMSIS-NN -TF_MAKE_TAGS="cmsis-nn" - -if [ "$1" == "clean" ]; then - rm api/internally* - rm -rf main.cpp - rm -rf util - rm -rf tensorflow-master.zip - rm -rf tensorflow - rm -rf mbed-os - rm -rf mbed_settings* - rm -rf master* - rm -rf tensorflow-master - rm -f CMakeLists.txt - rm -rf BUILD - rm -rf third_party - rm -f LICENSE - rm -f README_MBED.md - rm -rf __pycache__ - -else - -#cd $(dirname $0) - TFMICRO_DIR=tensorflow - if [ ! -f "$TFMICRO_DIR" ]; then - wget https://github.com/tensorflow/tensorflow/archive/$TF_VERSION.zip - unzip -o $TF_VERSION.zip - pushd tensorflow-* # we can't use TF_VERSION here, as github seems not to be consistent with naming (v2.3.1 vs 2.3.1) - LC_ALL=C gmake -f tensorflow/lite/micro/tools/make/Makefile TAGS=$TF_MAKE_TAGS third_party_downloads - LC_ALL=C gmake -f tensorflow/lite/micro/tools/make/Makefile TAGS=$TF_MAKE_TAGS generate_hello_world_mbed_project -j18 - mv -n tensorflow/lite/micro/tools/make/gen/*/prj/hello_world/mbed/* ../ - popd - rm -rf tensorflow-* - rm -rf tensorflow/lite/micro/examples/hello_world - fi - - mbed config root . - mbed deploy - cp ../../api/internally* api/ - cp ../../main.cpp . - cp -r ../../util . - -fi - diff --git a/benchmark/reference_submissions/streaming_wakeword/str_ww/strww_model_data.cc b/benchmark/reference_submissions/streaming_wakeword/str_ww/strww_model_data.cc deleted file mode 100644 index 7516318e..00000000 --- a/benchmark/reference_submissions/streaming_wakeword/str_ww/strww_model_data.cc +++ /dev/null @@ -1,5338 +0,0 @@ -#include "strww_model_data.h" - -const unsigned char g_strww_model_data[] = { - 0x20, 0x00, 0x00, 0x00, 0x54, 0x46, 0x4c, 0x33, 0x00, 0x00, 0x00, 0x00, - 0x14, 0x00, 0x20, 0x00, 0x1c, 0x00, 0x18, 0x00, 0x14, 0x00, 0x10, 0x00, - 0x0c, 0x00, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, 0x14, 0x00, 0x00, 0x00, - 0x1c, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00, 0xdc, 0x00, 0x00, 0x00, - 0x8c, 0x90, 0x00, 0x00, 0x9c, 0x90, 0x00, 0x00, 0x34, 0xf9, 0x00, 0x00, - 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0xa6, 0x6e, 0xff, 0xff, 0x0c, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, - 0x3c, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x73, 0x65, 0x72, 0x76, - 0x69, 0x6e, 0x67, 0x5f, 0x64, 0x65, 0x66, 0x61, 0x75, 0x6c, 0x74, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x98, 0xff, 0xff, 0xff, - 0x25, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, - 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x64, 0x65, 0x6e, 0x73, 0x65, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xfe, 0x6f, 0xff, 0xff, - 0x04, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x69, 0x6e, 0x70, 0x75, - 0x74, 0x5f, 0x31, 0x00, 0x02, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0xdc, 0xff, 0xff, 0xff, 0x28, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x43, 0x4f, 0x4e, 0x56, - 0x45, 0x52, 0x53, 0x49, 0x4f, 0x4e, 0x5f, 0x4d, 0x45, 0x54, 0x41, 0x44, - 0x41, 0x54, 0x41, 0x00, 0x08, 0x00, 0x0c, 0x00, 0x08, 0x00, 0x04, 0x00, - 0x08, 0x00, 0x00, 0x00, 0x27, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x13, 0x00, 0x00, 0x00, 0x6d, 0x69, 0x6e, 0x5f, 0x72, 0x75, 0x6e, 0x74, - 0x69, 0x6d, 0x65, 0x5f, 0x76, 0x65, 0x72, 0x73, 0x69, 0x6f, 0x6e, 0x00, - 0x29, 0x00, 0x00, 0x00, 0xac, 0x8f, 0x00, 0x00, 0xa4, 0x8f, 0x00, 0x00, - 0x8c, 0x8f, 0x00, 0x00, 0xac, 0x8e, 0x00, 0x00, 0xfc, 0x8d, 0x00, 0x00, - 0xf4, 0x8d, 0x00, 0x00, 0xe4, 0x79, 0x00, 0x00, 0xd4, 0x77, 0x00, 0x00, - 0xcc, 0x77, 0x00, 0x00, 0x3c, 0x75, 0x00, 0x00, 0x2c, 0x73, 0x00, 0x00, - 0x24, 0x73, 0x00, 0x00, 0x14, 0x53, 0x00, 0x00, 0x04, 0x52, 0x00, 0x00, - 0xfc, 0x51, 0x00, 0x00, 0x2c, 0x4f, 0x00, 0x00, 0x1c, 0x4e, 0x00, 0x00, - 0x14, 0x4e, 0x00, 0x00, 0x04, 0x3e, 0x00, 0x00, 0xf4, 0x3c, 0x00, 0x00, - 0xec, 0x3c, 0x00, 0x00, 0x9c, 0x39, 0x00, 0x00, 0x94, 0x39, 0x00, 0x00, - 0x8c, 0x39, 0x00, 0x00, 0x7c, 0x29, 0x00, 0x00, 0x6c, 0x28, 0x00, 0x00, - 0x64, 0x28, 0x00, 0x00, 0x94, 0x24, 0x00, 0x00, 0x8c, 0x24, 0x00, 0x00, - 0x84, 0x24, 0x00, 0x00, 0x74, 0x04, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, - 0x5c, 0x02, 0x00, 0x00, 0x54, 0x02, 0x00, 0x00, 0x4c, 0x02, 0x00, 0x00, - 0x44, 0x02, 0x00, 0x00, 0xb4, 0x00, 0x00, 0x00, 0x98, 0x00, 0x00, 0x00, - 0x90, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x16, 0x71, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, 0x5c, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x00, 0x08, 0x00, 0x0e, 0x00, 0x08, 0x00, 0x04, 0x00, - 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x06, 0x00, 0x08, 0x00, 0x04, 0x00, 0x06, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0xeb, 0x03, 0x00, 0x00, - 0xd0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x10, 0x00, 0x0c, 0x00, - 0x08, 0x00, 0x04, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x02, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, - 0x32, 0x2e, 0x31, 0x35, 0x2e, 0x30, 0x00, 0x00, 0x7e, 0x71, 0xff, 0xff, - 0x04, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x31, 0x2e, 0x31, 0x34, - 0x2e, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xa4, 0x09, 0xff, 0xff, 0x9e, 0x71, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x00, 0x96, 0x00, 0x00, 0x00, 0x3a, 0x02, 0x00, 0x00, - 0x66, 0xfe, 0xff, 0xff, 0xb6, 0x71, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, - 0x80, 0x01, 0x00, 0x00, 0xe0, 0x46, 0xed, 0xa2, 0xf1, 0x3c, 0x27, 0xf3, - 0x50, 0x5d, 0x36, 0x36, 0x49, 0x1c, 0xd8, 0xc5, 0xc0, 0xff, 0xc4, 0x0b, - 0x1d, 0xf4, 0xce, 0x1a, 0xdf, 0xa5, 0xa1, 0x3e, 0x04, 0x60, 0xe8, 0xd3, - 0x6a, 0x04, 0x32, 0xa2, 0x2e, 0xda, 0xdf, 0x29, 0xfd, 0xcc, 0xe0, 0x69, - 0x41, 0x51, 0xc2, 0x50, 0x00, 0x4b, 0xd5, 0x0d, 0x25, 0xa5, 0xad, 0xdd, - 0x4a, 0x2b, 0xd0, 0x3d, 0x39, 0x58, 0x5e, 0x60, 0xf7, 0x12, 0xc1, 0x57, - 0x35, 0xe5, 0xea, 0x3e, 0x27, 0x23, 0xb0, 0xd3, 0xb2, 0xf8, 0xef, 0xb0, - 0x9f, 0x37, 0xce, 0x0b, 0x2b, 0x6f, 0x48, 0x08, 0x48, 0xdc, 0x27, 0xc8, - 0x1e, 0x45, 0x1b, 0xee, 0xf2, 0x3d, 0xb3, 0x48, 0x14, 0x53, 0xe5, 0x4d, - 0xb7, 0xa5, 0x11, 0x3c, 0xa2, 0x41, 0xdc, 0xd1, 0x2e, 0xda, 0xb1, 0xfd, - 0x6a, 0x56, 0x25, 0xda, 0xc3, 0x13, 0x9f, 0x13, 0xcc, 0xa1, 0x01, 0xe7, - 0x53, 0x39, 0x08, 0xa8, 0xd8, 0xef, 0xd2, 0xd8, 0x5e, 0xfe, 0x96, 0x61, - 0x47, 0xdb, 0x10, 0xf2, 0xf9, 0x0d, 0x42, 0xd7, 0xe2, 0x1d, 0xaa, 0xcf, - 0x4c, 0xd8, 0x45, 0x0f, 0xef, 0xa1, 0xbb, 0xd4, 0x02, 0x12, 0xd1, 0xef, - 0xae, 0xde, 0x6a, 0x16, 0x12, 0xb5, 0x06, 0xb9, 0x59, 0xc2, 0xe9, 0xda, - 0x1f, 0xde, 0x57, 0x43, 0x3d, 0x4a, 0xc0, 0xd9, 0x56, 0x49, 0x11, 0x3c, - 0x12, 0x91, 0xd0, 0xca, 0x4f, 0x60, 0xfd, 0xbc, 0xae, 0xc6, 0x2f, 0x48, - 0x5b, 0xdf, 0xf2, 0x02, 0xd7, 0xfa, 0xfb, 0xcc, 0xe9, 0x43, 0x61, 0x45, - 0xed, 0xdc, 0x52, 0x9f, 0xfe, 0x1e, 0x2c, 0xbe, 0xc7, 0xb6, 0xf2, 0xf1, - 0x1d, 0x92, 0x2e, 0x50, 0xa4, 0xae, 0xa5, 0xaa, 0xa4, 0xb5, 0x66, 0x18, - 0x33, 0xec, 0xd2, 0x51, 0x06, 0x3f, 0xfc, 0xd1, 0xf3, 0x43, 0xa4, 0x66, - 0x60, 0xd9, 0xff, 0xac, 0x61, 0x26, 0x25, 0xa3, 0x42, 0x7f, 0x45, 0x06, - 0x3c, 0xc9, 0xe5, 0x49, 0x2c, 0x53, 0x2b, 0xf0, 0xbc, 0xd6, 0xa3, 0x28, - 0x2e, 0x77, 0x5b, 0x75, 0xd7, 0xad, 0x05, 0x4c, 0x9d, 0x4a, 0x08, 0xed, - 0x69, 0xc3, 0x4e, 0x1f, 0x29, 0x5c, 0x7f, 0x28, 0xdd, 0x4b, 0x60, 0x69, - 0x5a, 0x2f, 0x41, 0x57, 0xbe, 0x51, 0x69, 0xb5, 0x63, 0xb4, 0xb5, 0x4a, - 0xad, 0x07, 0x57, 0x38, 0xdd, 0xbe, 0xa7, 0xb9, 0xae, 0x11, 0xd5, 0x17, - 0x44, 0x3a, 0xef, 0x08, 0xd5, 0x23, 0x5c, 0xfc, 0x1b, 0xcb, 0x3c, 0x63, - 0x49, 0x57, 0x55, 0x1f, 0x57, 0xaf, 0x4f, 0x3d, 0x7f, 0x1a, 0xb8, 0xff, - 0x68, 0x5a, 0xc1, 0x34, 0xb8, 0xc2, 0x4d, 0xb0, 0x58, 0x2d, 0xc5, 0xd8, - 0xb2, 0xde, 0x46, 0xcf, 0xf9, 0x0a, 0x24, 0x67, 0xec, 0x10, 0x6e, 0x70, - 0xa2, 0x7c, 0x41, 0x4d, 0x25, 0xf6, 0xef, 0xe2, 0x69, 0x52, 0x5c, 0x11, - 0xf8, 0xfe, 0xb1, 0x1c, 0x4c, 0x0b, 0xff, 0xff, 0x50, 0x0b, 0xff, 0xff, - 0x54, 0x0b, 0xff, 0xff, 0x58, 0x0b, 0xff, 0xff, 0x52, 0x73, 0xff, 0xff, - 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x7f, 0x02, 0x00, 0x00, - 0x32, 0x01, 0x00, 0x00, 0xfa, 0x04, 0x00, 0x00, 0x3a, 0x03, 0x00, 0x00, - 0xca, 0x09, 0x00, 0x00, 0x59, 0xfe, 0xff, 0xff, 0x5c, 0x01, 0x00, 0x00, - 0x21, 0x01, 0x00, 0x00, 0x9f, 0xf4, 0xff, 0xff, 0x06, 0x06, 0x00, 0x00, - 0x54, 0x0b, 0x00, 0x00, 0xd3, 0xf4, 0xff, 0xff, 0x40, 0xff, 0xff, 0xff, - 0x17, 0x01, 0x00, 0x00, 0x6e, 0x04, 0x00, 0x00, 0x12, 0x04, 0x00, 0x00, - 0x16, 0x07, 0x00, 0x00, 0x26, 0xff, 0xff, 0xff, 0xcd, 0x02, 0x00, 0x00, - 0x77, 0x04, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0xbf, 0x02, 0x00, 0x00, - 0xc6, 0x10, 0x00, 0x00, 0x21, 0x06, 0x00, 0x00, 0x03, 0x01, 0x00, 0x00, - 0xf7, 0x15, 0x00, 0x00, 0xda, 0x00, 0x00, 0x00, 0x84, 0xfc, 0xff, 0xff, - 0x73, 0xfe, 0xff, 0xff, 0xdf, 0xfe, 0xff, 0xff, 0xac, 0x13, 0x00, 0x00, - 0x6e, 0x02, 0x00, 0x00, 0xf7, 0xfa, 0xff, 0xff, 0x12, 0x04, 0x00, 0x00, - 0x9b, 0xfb, 0xff, 0xff, 0x5b, 0x04, 0x00, 0x00, 0x5c, 0x02, 0x00, 0x00, - 0xe1, 0x0b, 0x00, 0x00, 0xab, 0x02, 0x00, 0x00, 0x9d, 0x07, 0x00, 0x00, - 0x7f, 0x05, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x95, 0x03, 0x00, 0x00, - 0x1b, 0x06, 0x00, 0x00, 0xcf, 0x06, 0x00, 0x00, 0x16, 0xff, 0xff, 0xff, - 0xfb, 0xff, 0xff, 0xff, 0x56, 0x00, 0x00, 0x00, 0xba, 0xfd, 0xff, 0xff, - 0x8c, 0x06, 0x00, 0x00, 0x9f, 0x08, 0x00, 0x00, 0x87, 0x01, 0x00, 0x00, - 0xc5, 0xfd, 0xff, 0xff, 0xf6, 0xfb, 0xff, 0xff, 0x05, 0x0c, 0x00, 0x00, - 0x25, 0x07, 0x00, 0x00, 0xee, 0xf2, 0xff, 0xff, 0x74, 0xfb, 0xff, 0xff, - 0x98, 0x09, 0x00, 0x00, 0xeb, 0x01, 0x00, 0x00, 0x84, 0xfd, 0xff, 0xff, - 0x61, 0xff, 0xff, 0xff, 0x13, 0xfe, 0xff, 0xff, 0x85, 0xf7, 0xff, 0xff, - 0xd0, 0x00, 0x00, 0x00, 0xe4, 0xf9, 0xff, 0xff, 0x65, 0x0a, 0x00, 0x00, - 0xf7, 0xf4, 0xff, 0xff, 0x2e, 0xff, 0xff, 0xff, 0x39, 0x03, 0x00, 0x00, - 0xb2, 0x08, 0x00, 0x00, 0x2e, 0xf9, 0xff, 0xff, 0x04, 0xf0, 0xff, 0xff, - 0xf7, 0xff, 0xff, 0xff, 0x62, 0x04, 0x00, 0x00, 0xf5, 0xfe, 0xff, 0xff, - 0x89, 0x16, 0x00, 0x00, 0x8f, 0x03, 0x00, 0x00, 0xb3, 0xfe, 0xff, 0xff, - 0xe7, 0x00, 0x00, 0x00, 0xcd, 0xfe, 0xff, 0xff, 0x8b, 0xfd, 0xff, 0xff, - 0x96, 0x02, 0x00, 0x00, 0xe4, 0xfe, 0xff, 0xff, 0x7b, 0x03, 0x00, 0x00, - 0x8f, 0xf8, 0xff, 0xff, 0x88, 0xfc, 0xff, 0xff, 0x2f, 0xff, 0xff, 0xff, - 0xe0, 0xf7, 0xff, 0xff, 0xd7, 0xff, 0xff, 0xff, 0xd7, 0x03, 0x00, 0x00, - 0x1b, 0x00, 0x00, 0x00, 0x3d, 0x00, 0x00, 0x00, 0xdd, 0xfa, 0xff, 0xff, - 0x1f, 0x16, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0xa2, 0xfc, 0xff, 0xff, - 0xdb, 0x04, 0x00, 0x00, 0x3a, 0x06, 0x00, 0x00, 0xc7, 0xfe, 0xff, 0xff, - 0x2c, 0xfd, 0xff, 0xff, 0x0e, 0x02, 0x00, 0x00, 0x1b, 0x01, 0x00, 0x00, - 0xdf, 0x02, 0x00, 0x00, 0x2d, 0x05, 0x00, 0x00, 0xd7, 0xff, 0xff, 0xff, - 0x55, 0xf4, 0xff, 0xff, 0xf6, 0xea, 0xff, 0xff, 0xc2, 0x01, 0x00, 0x00, - 0x74, 0xfa, 0xff, 0xff, 0xdb, 0xf1, 0xff, 0xff, 0x39, 0xfb, 0xff, 0xff, - 0x9e, 0x04, 0x00, 0x00, 0x90, 0xfd, 0xff, 0xff, 0x32, 0x05, 0x00, 0x00, - 0x03, 0x00, 0x00, 0x00, 0x25, 0xfb, 0xff, 0xff, 0x8f, 0xf8, 0xff, 0xff, - 0x76, 0x04, 0x00, 0x00, 0xeb, 0x00, 0x00, 0x00, 0x57, 0x02, 0x00, 0x00, - 0x86, 0x01, 0x00, 0x00, 0x16, 0x06, 0x00, 0x00, 0x43, 0xfe, 0xff, 0xff, - 0x91, 0x06, 0x00, 0x00, 0xe2, 0xfb, 0xff, 0xff, 0x31, 0xf9, 0xff, 0xff, - 0x4e, 0x00, 0x00, 0x00, 0x5e, 0x75, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, - 0x00, 0x20, 0x00, 0x00, 0x44, 0x15, 0x0e, 0xd1, 0xd7, 0x2a, 0x33, 0x01, - 0xbf, 0xdc, 0xf2, 0xdf, 0xf8, 0xfb, 0xd9, 0xcc, 0xdf, 0xd4, 0xe2, 0xd1, - 0x36, 0x10, 0x09, 0x14, 0xe2, 0x10, 0xa2, 0x51, 0x03, 0x0f, 0xdf, 0x03, - 0xcf, 0xdc, 0x08, 0x30, 0xff, 0xc9, 0xca, 0xff, 0xe1, 0xd3, 0xe9, 0xfd, - 0x03, 0x05, 0x29, 0x06, 0x0e, 0xa6, 0xe4, 0xee, 0xf4, 0xeb, 0xff, 0x01, - 0xea, 0x30, 0xfb, 0x24, 0xef, 0xdf, 0xdd, 0x81, 0x39, 0xeb, 0x05, 0xe3, - 0xff, 0xec, 0x40, 0x26, 0x25, 0x20, 0x0f, 0x05, 0xb5, 0xda, 0xeb, 0x28, - 0x03, 0x1b, 0x30, 0xe6, 0x24, 0xf9, 0x1e, 0xe0, 0x7f, 0xff, 0x04, 0x54, - 0xeb, 0x3f, 0x01, 0x09, 0xd9, 0xd7, 0x1a, 0x0d, 0xf7, 0xb5, 0xb5, 0x1d, - 0xcf, 0xec, 0xe7, 0xd1, 0xff, 0xe3, 0x33, 0xfd, 0x19, 0xd9, 0xf1, 0x12, - 0x1a, 0xef, 0x09, 0xfd, 0xd7, 0x05, 0x1d, 0xdc, 0xfd, 0xc5, 0x92, 0x19, - 0x03, 0x11, 0xfd, 0xec, 0x0d, 0x25, 0xa7, 0xf4, 0x07, 0xd9, 0x19, 0xf0, - 0x0a, 0x08, 0xe7, 0x0a, 0x08, 0x02, 0xe8, 0xf9, 0x03, 0xf9, 0x04, 0xfc, - 0x15, 0xeb, 0xf6, 0xfc, 0x02, 0xfe, 0x1c, 0xfb, 0xee, 0x06, 0xe5, 0x08, - 0x19, 0x24, 0x14, 0xfa, 0x15, 0x0d, 0x04, 0xf9, 0xfc, 0x0a, 0xed, 0x12, - 0xf5, 0x7b, 0xfd, 0x1e, 0xe9, 0x14, 0x0c, 0xfe, 0xf6, 0xfc, 0x0c, 0x1a, - 0x14, 0x07, 0x7f, 0x09, 0xef, 0xe5, 0xf3, 0x1c, 0xfe, 0x28, 0xe4, 0xdd, - 0xff, 0xed, 0x05, 0xf1, 0xd8, 0xff, 0x0a, 0xfe, 0xfa, 0x0d, 0x00, 0xf6, - 0xe6, 0x0d, 0xe4, 0x01, 0x0d, 0x08, 0xe7, 0x81, 0xea, 0x1d, 0x1f, 0xda, - 0x1d, 0x09, 0x17, 0xf6, 0x34, 0xf8, 0x15, 0x1f, 0xd1, 0xf6, 0xf6, 0x3f, - 0x1d, 0x03, 0xf7, 0x16, 0xef, 0x07, 0x06, 0xef, 0x24, 0x09, 0x30, 0x09, - 0x1f, 0xd9, 0xe4, 0xf2, 0x15, 0xdc, 0x1b, 0xc1, 0xf7, 0x15, 0x0a, 0x03, - 0xee, 0x30, 0x9e, 0x09, 0xd3, 0xf5, 0x22, 0x3b, 0x05, 0x49, 0x10, 0x96, - 0xc8, 0x0b, 0xdb, 0xe6, 0xf5, 0xf3, 0xd7, 0x00, 0xa3, 0xef, 0x05, 0xf0, - 0x0c, 0xf5, 0x48, 0x48, 0xf6, 0x11, 0xfd, 0x35, 0xf7, 0xf5, 0xeb, 0xda, - 0xee, 0x35, 0x1e, 0xff, 0x1d, 0x30, 0x29, 0x5c, 0xfe, 0x7f, 0xee, 0x31, - 0xd7, 0x0f, 0xfd, 0x0e, 0x2a, 0xd8, 0xe0, 0x32, 0x3a, 0xfe, 0x57, 0x14, - 0xf9, 0xcf, 0xee, 0x29, 0xe5, 0x25, 0x18, 0x4f, 0xe9, 0xf9, 0x09, 0x12, - 0x14, 0x24, 0xd9, 0x00, 0xf7, 0xed, 0xf5, 0x1e, 0xd7, 0xfc, 0x16, 0x14, - 0xe0, 0x04, 0x05, 0x0f, 0x40, 0xd9, 0x1f, 0x09, 0x31, 0xda, 0x08, 0x0a, - 0xf4, 0x21, 0x1b, 0xe1, 0xf5, 0xd1, 0x11, 0x04, 0x08, 0xcb, 0xe8, 0x7f, - 0xdc, 0xda, 0xcc, 0xf8, 0xff, 0xf0, 0x1b, 0x3c, 0xda, 0xf4, 0xf6, 0x19, - 0x03, 0x07, 0xfb, 0x1d, 0x13, 0xec, 0x0f, 0x10, 0x4e, 0x60, 0x2a, 0x66, - 0xdf, 0xf0, 0xd1, 0x7f, 0xff, 0x40, 0x08, 0xff, 0xd3, 0x14, 0xcf, 0x2c, - 0xbf, 0x1d, 0xf9, 0x04, 0x04, 0xc7, 0xde, 0x1f, 0x20, 0x06, 0xea, 0x48, - 0x11, 0xe9, 0x08, 0x1a, 0xf7, 0x08, 0x3b, 0xe1, 0xe7, 0xe4, 0x1c, 0x26, - 0xf3, 0xf3, 0xfd, 0x6c, 0xf8, 0xeb, 0xb8, 0xc3, 0xd9, 0x0f, 0x05, 0x25, - 0x15, 0x1b, 0xfb, 0xe6, 0xf9, 0xfc, 0x22, 0x13, 0xdf, 0x1c, 0xf4, 0x0d, - 0xe3, 0x1d, 0xbb, 0xd1, 0x1b, 0xe7, 0x06, 0xeb, 0x0d, 0x09, 0xe3, 0xd5, - 0xce, 0x03, 0x0c, 0xf5, 0x0d, 0xf0, 0xfc, 0x22, 0xcd, 0xf2, 0x16, 0xdf, - 0x17, 0xed, 0xfc, 0x0d, 0x12, 0x0b, 0xff, 0x19, 0x28, 0x10, 0x2b, 0xfc, - 0x06, 0x1c, 0x10, 0x17, 0x0b, 0x0f, 0xec, 0x1d, 0x04, 0x7f, 0xe6, 0x31, - 0xde, 0x00, 0x22, 0x1e, 0xe9, 0xe3, 0x25, 0x26, 0x03, 0x28, 0x31, 0xf5, - 0xd6, 0xf5, 0x4a, 0x38, 0x0c, 0xfa, 0x28, 0x4c, 0x5c, 0x09, 0x1e, 0x48, - 0xf8, 0x7f, 0x90, 0xf3, 0xd1, 0xe7, 0xfb, 0xbc, 0xde, 0xfa, 0x3b, 0x4f, - 0x73, 0x3c, 0xc0, 0x4f, 0x0e, 0xfd, 0x3f, 0x24, 0xf1, 0xe4, 0xb0, 0x64, - 0x04, 0x4e, 0xf4, 0x08, 0xf9, 0x54, 0x7e, 0xf9, 0xb5, 0x01, 0xb7, 0x43, - 0x9a, 0xf9, 0xd5, 0x16, 0xe1, 0xd4, 0xf5, 0x38, 0xf5, 0x21, 0xf2, 0x2e, - 0x0b, 0xe6, 0xb7, 0x1b, 0xf6, 0xdb, 0x23, 0x10, 0xe1, 0xdd, 0x7f, 0xb8, - 0x0c, 0x04, 0xf1, 0xec, 0xca, 0x52, 0xf7, 0x60, 0xe1, 0x45, 0xf8, 0x21, - 0xee, 0xd2, 0xd6, 0xb6, 0x12, 0xda, 0x35, 0x0c, 0xe5, 0x48, 0xca, 0x11, - 0x1e, 0xfa, 0x0b, 0x41, 0xaf, 0x90, 0x37, 0xbc, 0x17, 0xd1, 0xe2, 0x16, - 0xdd, 0x03, 0x0f, 0xcd, 0xf6, 0x18, 0xd5, 0xa8, 0xf6, 0x27, 0x93, 0x0a, - 0x1c, 0x17, 0xfc, 0x6d, 0xb9, 0xae, 0xf0, 0x00, 0x24, 0xf3, 0xf0, 0x17, - 0x2b, 0x7f, 0x03, 0x04, 0x1a, 0xea, 0x00, 0x0b, 0xb3, 0x25, 0x26, 0xbc, - 0xf0, 0x0f, 0xe9, 0x1f, 0x0a, 0xfb, 0x21, 0xfb, 0xfe, 0xbd, 0xff, 0x28, - 0x25, 0xf8, 0x01, 0xfd, 0x13, 0xf4, 0xf8, 0x17, 0xd9, 0xd2, 0xc2, 0xf8, - 0x1b, 0xe8, 0x08, 0x37, 0xf0, 0xd3, 0xee, 0x2e, 0xea, 0xe7, 0xef, 0x21, - 0xfc, 0xb6, 0x29, 0xf5, 0xea, 0x17, 0xd9, 0xfb, 0x2d, 0x16, 0x09, 0x00, - 0xf4, 0x27, 0x69, 0xdd, 0x35, 0xdd, 0x02, 0x2d, 0x13, 0xee, 0x4c, 0xf6, - 0xfd, 0xfc, 0x9b, 0x03, 0x16, 0xd6, 0x04, 0x81, 0xd2, 0xe9, 0xe6, 0x98, - 0x32, 0x1c, 0xbc, 0x1a, 0xc1, 0xf3, 0x5e, 0xd0, 0xac, 0x00, 0x07, 0x32, - 0xf1, 0x66, 0x09, 0xcf, 0x45, 0xf2, 0x17, 0xeb, 0x26, 0x04, 0xfc, 0x76, - 0xe0, 0x17, 0xe1, 0x5a, 0xf8, 0x56, 0xa9, 0x66, 0xfa, 0xee, 0x1f, 0xe0, - 0x1c, 0xc2, 0xb5, 0xf5, 0xe7, 0xed, 0xbd, 0xbb, 0x17, 0xed, 0xcc, 0xbb, - 0x04, 0x24, 0x83, 0x0a, 0x08, 0x49, 0xc7, 0xe0, 0xcc, 0x54, 0x32, 0x1c, - 0xbf, 0x2d, 0x09, 0xaf, 0x3d, 0xf2, 0x34, 0x13, 0xf0, 0x33, 0xc1, 0x2a, - 0xf1, 0x3b, 0xdc, 0xc8, 0x03, 0x35, 0xf3, 0x97, 0xb5, 0x0f, 0x64, 0xe2, - 0x81, 0x22, 0xd4, 0x41, 0xab, 0xf0, 0x02, 0x00, 0xe6, 0xd9, 0xf6, 0xc8, - 0x46, 0xe2, 0xdd, 0x14, 0xf1, 0x05, 0xd2, 0x47, 0xe4, 0xd5, 0x08, 0x0d, - 0x1c, 0x14, 0x26, 0x7f, 0x16, 0x09, 0xc1, 0x4f, 0x0a, 0x3d, 0xd3, 0xee, - 0xcd, 0x08, 0xe5, 0x17, 0xff, 0x21, 0x04, 0xe7, 0xf2, 0xd9, 0xd6, 0x0d, - 0x33, 0xfe, 0xea, 0xfd, 0x25, 0xc4, 0xfa, 0x00, 0xf9, 0x1e, 0x13, 0x00, - 0x13, 0xe1, 0xfb, 0x15, 0x04, 0xdc, 0xf1, 0x7d, 0xe6, 0xeb, 0xc6, 0xe4, - 0xf7, 0x07, 0xf5, 0x26, 0x15, 0x1d, 0xe0, 0xd3, 0xdf, 0x0b, 0x14, 0x15, - 0x08, 0x06, 0xd1, 0x13, 0x02, 0x01, 0x00, 0xd6, 0xe4, 0xfc, 0xea, 0xdb, - 0xf3, 0xf2, 0xe5, 0xfc, 0x3d, 0xee, 0xda, 0x49, 0xcf, 0x29, 0x38, 0x7f, - 0xf1, 0xde, 0x0f, 0x07, 0xec, 0x31, 0x19, 0xd3, 0x2b, 0x03, 0xe3, 0x06, - 0xfe, 0xdd, 0xe1, 0xe5, 0xc6, 0x3f, 0x38, 0x0f, 0xb7, 0x32, 0xee, 0xff, - 0x6b, 0xfa, 0x5f, 0x2a, 0x1e, 0xd3, 0xff, 0xaf, 0xf0, 0xf3, 0xe7, 0xf9, - 0xeb, 0xfc, 0x08, 0x03, 0xf8, 0x1f, 0xf2, 0x1b, 0x17, 0x22, 0xd2, 0x04, - 0xe9, 0xea, 0x00, 0xdf, 0x23, 0x0f, 0xee, 0xd9, 0xec, 0x08, 0xf3, 0xfc, - 0x08, 0xfd, 0x09, 0x02, 0x05, 0x22, 0x25, 0xeb, 0x0c, 0xe6, 0x00, 0xf2, - 0x09, 0x1d, 0x08, 0x0f, 0x06, 0x03, 0xfa, 0xef, 0x01, 0xe9, 0x0f, 0xef, - 0x17, 0x11, 0xfd, 0xe7, 0x21, 0x7f, 0x0a, 0xec, 0xe6, 0x0e, 0x12, 0x27, - 0xfa, 0x08, 0x0d, 0xd9, 0x04, 0xe1, 0x7b, 0x18, 0xe8, 0xd1, 0xf7, 0x05, - 0x20, 0xeb, 0xab, 0xca, 0x1f, 0xfa, 0x13, 0x2b, 0x00, 0x13, 0xf4, 0x20, - 0x08, 0xf0, 0x04, 0x09, 0x04, 0x1b, 0xf5, 0xfb, 0xdd, 0x20, 0xe2, 0xd4, - 0x0c, 0xdf, 0xed, 0xf9, 0x0d, 0x01, 0xc9, 0x27, 0x03, 0x16, 0x02, 0xfe, - 0x07, 0xfb, 0x06, 0xf3, 0x0b, 0x28, 0xf9, 0x13, 0xe8, 0x60, 0x21, 0x1b, - 0xf1, 0xe5, 0xf8, 0xf9, 0x15, 0xf9, 0xf3, 0xe7, 0xfe, 0x14, 0x7f, 0x0c, - 0x3d, 0x06, 0xfc, 0x30, 0x1f, 0xc5, 0x6e, 0x25, 0xd4, 0x1f, 0xe3, 0xd1, - 0xbc, 0xd1, 0x1f, 0x2e, 0x27, 0x05, 0x2d, 0xf4, 0xda, 0xcc, 0x0b, 0x04, - 0x00, 0xf0, 0x34, 0x44, 0xe9, 0x4c, 0xff, 0xf8, 0xfb, 0xf9, 0xfb, 0xe4, - 0xd3, 0xe2, 0xe0, 0x12, 0xde, 0x04, 0xe5, 0xfc, 0xfa, 0xc8, 0x08, 0xd2, - 0xf2, 0x81, 0xbe, 0xc4, 0x32, 0x19, 0x29, 0xdc, 0x19, 0x43, 0xcc, 0x0d, - 0xe9, 0x12, 0x9e, 0xc6, 0xf7, 0xd1, 0xf8, 0x21, 0xfd, 0xf1, 0xab, 0xcb, - 0xeb, 0x20, 0x17, 0xfd, 0x27, 0xed, 0x24, 0x0a, 0x07, 0x02, 0x0f, 0x32, - 0xdf, 0x3e, 0x02, 0xf5, 0x3f, 0x11, 0x4f, 0x17, 0x1d, 0xf7, 0xfe, 0x0a, - 0x24, 0x0f, 0xe5, 0x06, 0x09, 0x1a, 0x0f, 0xf0, 0x1b, 0xf7, 0x0c, 0xd4, - 0xff, 0x0e, 0xfd, 0xda, 0xf5, 0x7f, 0x10, 0x0a, 0xfb, 0xe1, 0xb0, 0xe7, - 0xe8, 0x0a, 0x3d, 0x28, 0xe4, 0x03, 0x4b, 0x3f, 0x4e, 0xd7, 0xf6, 0xf5, - 0xea, 0xea, 0xe4, 0x09, 0xd8, 0x09, 0x33, 0x3c, 0x18, 0x32, 0x1f, 0x45, - 0x1c, 0xf9, 0xe9, 0x1b, 0xe7, 0xd2, 0x00, 0x03, 0x05, 0x0d, 0xfa, 0x6c, - 0x27, 0xf2, 0xcf, 0x38, 0xd3, 0x27, 0x27, 0x07, 0xc6, 0x91, 0x8a, 0xee, - 0xee, 0xc4, 0xbd, 0xd5, 0x3d, 0xfe, 0x28, 0xcf, 0x0e, 0x93, 0xb7, 0x2f, - 0xfe, 0x23, 0xb5, 0xa9, 0xcc, 0x7f, 0xd3, 0x05, 0x99, 0xcb, 0xe6, 0x42, - 0xaf, 0xff, 0x25, 0xe0, 0xae, 0xf3, 0x07, 0x7f, 0x09, 0x0e, 0x44, 0xfd, - 0x01, 0x18, 0x30, 0xb7, 0x05, 0x07, 0xcf, 0xc9, 0xd5, 0xf8, 0x06, 0xd8, - 0x08, 0xce, 0xec, 0x11, 0x06, 0xc7, 0xe9, 0xfb, 0xdc, 0xe4, 0x35, 0x39, - 0x3e, 0xec, 0xd8, 0x11, 0x4a, 0x14, 0xfa, 0x0d, 0x43, 0xc3, 0x30, 0x56, - 0x1d, 0xe6, 0xf5, 0xc7, 0x02, 0x00, 0x4b, 0xf8, 0xf8, 0x09, 0xdb, 0x12, - 0xc8, 0xf2, 0xed, 0x1a, 0x25, 0x0e, 0xa8, 0x05, 0x1c, 0x04, 0x08, 0xd7, - 0xff, 0x31, 0x0e, 0x17, 0x1c, 0xe9, 0xdd, 0xe3, 0xf6, 0xcd, 0x0c, 0x23, - 0x1c, 0x0b, 0xf0, 0x2f, 0x16, 0x09, 0x12, 0x06, 0xe8, 0x20, 0xe3, 0xf1, - 0xac, 0xee, 0x15, 0xb6, 0xe9, 0x0d, 0xda, 0x49, 0x26, 0x1f, 0xe4, 0x27, - 0xd5, 0x12, 0xf9, 0x15, 0x7f, 0xe3, 0x13, 0xf7, 0x42, 0xf3, 0x00, 0xb6, - 0x20, 0xf2, 0x0b, 0x1e, 0xe6, 0x20, 0x15, 0xda, 0x52, 0xcb, 0xc3, 0xd2, - 0x13, 0x55, 0x84, 0xdf, 0xfb, 0x4b, 0xdb, 0x12, 0x9c, 0x01, 0x2d, 0x9c, - 0x02, 0xc3, 0xb6, 0xde, 0xf6, 0xd2, 0x31, 0x16, 0xd0, 0xa2, 0x14, 0xc3, - 0xd6, 0x7f, 0x17, 0x08, 0x0e, 0xef, 0xe6, 0x24, 0xa9, 0xdd, 0xb3, 0xc0, - 0xd6, 0x26, 0x13, 0x53, 0x01, 0xf2, 0x07, 0x2d, 0x3d, 0x25, 0x10, 0xcd, - 0xf1, 0x12, 0x55, 0x42, 0xf6, 0x81, 0xb0, 0xc7, 0x27, 0xf2, 0xe9, 0xdb, - 0xde, 0x35, 0x11, 0x17, 0xdf, 0xbf, 0xf3, 0x2e, 0x1e, 0x01, 0xe3, 0xe8, - 0xdb, 0x4b, 0x27, 0x28, 0x11, 0x1b, 0xf2, 0x20, 0xd9, 0x03, 0xff, 0xe3, - 0x30, 0xcf, 0x08, 0x4f, 0x28, 0xd3, 0xc6, 0x1d, 0x0b, 0x2a, 0x28, 0x30, - 0xcf, 0x1c, 0xe1, 0xc6, 0x27, 0xde, 0xfa, 0xd0, 0x04, 0xff, 0xf8, 0x97, - 0xe4, 0x15, 0xef, 0x3d, 0xed, 0xf5, 0x13, 0xf3, 0x1b, 0x27, 0x40, 0xf4, - 0xda, 0x7f, 0x1c, 0x1a, 0xf1, 0xe8, 0xf0, 0x20, 0x06, 0xe0, 0x1d, 0x58, - 0x18, 0x7f, 0xaf, 0x31, 0x20, 0xe9, 0xd4, 0x10, 0x0c, 0x04, 0xee, 0x35, - 0xc9, 0x0b, 0x08, 0xf3, 0x15, 0xff, 0x57, 0x11, 0x2e, 0xfd, 0x21, 0xd1, - 0x37, 0x1a, 0x14, 0x47, 0x13, 0xfc, 0x21, 0x34, 0xe3, 0x04, 0xec, 0x10, - 0x5f, 0x15, 0x28, 0x52, 0x18, 0xeb, 0x99, 0xef, 0xec, 0x15, 0xeb, 0xba, - 0x09, 0x15, 0x24, 0x05, 0x18, 0xf1, 0x0b, 0x1a, 0x2d, 0xd1, 0xf7, 0xc0, - 0x21, 0x0e, 0xd4, 0x0f, 0x1e, 0x13, 0x35, 0xe4, 0xc0, 0x28, 0x1d, 0xf9, - 0x21, 0x20, 0x34, 0x32, 0x66, 0xcf, 0x50, 0x00, 0xef, 0xf6, 0xfc, 0xe2, - 0x24, 0x34, 0x0a, 0x05, 0xdd, 0xd2, 0x32, 0x2c, 0xd4, 0xe2, 0xbb, 0xe3, - 0xd3, 0xe4, 0x0c, 0x74, 0xec, 0x03, 0xf4, 0x0e, 0xd8, 0x7f, 0xeb, 0x0f, - 0x1d, 0x23, 0x24, 0x10, 0xee, 0xd1, 0xcb, 0xb9, 0x1f, 0xff, 0x30, 0xfd, - 0xc1, 0xd4, 0xf1, 0x1b, 0xf0, 0x0f, 0x93, 0x19, 0x2d, 0x76, 0xcd, 0xda, - 0xf5, 0xe4, 0x1a, 0x3d, 0xd4, 0xde, 0x66, 0x08, 0xcd, 0x48, 0x32, 0x02, - 0x4a, 0x0a, 0x7f, 0x82, 0xed, 0x03, 0xf6, 0xca, 0x27, 0xcd, 0xdb, 0xcf, - 0x01, 0x10, 0x3d, 0x1c, 0x33, 0x34, 0x20, 0x0f, 0xd9, 0x0f, 0xf8, 0xb2, - 0x09, 0xee, 0x30, 0xf2, 0x11, 0x05, 0xd4, 0xcb, 0x27, 0xd4, 0x5b, 0xf1, - 0x31, 0xec, 0x32, 0xfd, 0x08, 0x51, 0xf2, 0x2e, 0x18, 0x08, 0xf4, 0xba, - 0xda, 0xfb, 0xa8, 0x3d, 0x57, 0x0b, 0xd0, 0x1c, 0xe2, 0xc5, 0x2b, 0x01, - 0xdb, 0x1d, 0xc8, 0xd7, 0x19, 0x32, 0x28, 0x25, 0xfa, 0x44, 0xe3, 0xd0, - 0x2c, 0x0c, 0x07, 0xbc, 0xe2, 0x41, 0x18, 0xdc, 0xfd, 0xce, 0x6a, 0xdf, - 0xb9, 0xe1, 0xc4, 0x53, 0x81, 0xff, 0xc4, 0x39, 0x53, 0xcf, 0xfa, 0x2b, - 0xea, 0x0f, 0x2c, 0x01, 0x40, 0xf9, 0xfc, 0x3b, 0x17, 0xf5, 0xf0, 0x37, - 0x0a, 0x09, 0xe7, 0xd2, 0x19, 0xe5, 0x08, 0xf5, 0x2b, 0x1d, 0x00, 0x98, - 0xd7, 0xfe, 0xc3, 0xf7, 0xdf, 0x28, 0xd2, 0x36, 0x0c, 0x14, 0xe7, 0x9b, - 0xf5, 0x05, 0x11, 0xf4, 0x0c, 0x1b, 0xdd, 0xf3, 0x44, 0x50, 0x31, 0xf4, - 0xf4, 0x18, 0x10, 0x27, 0xe3, 0xef, 0xf3, 0x2d, 0xf7, 0x7f, 0xfa, 0xe0, - 0xee, 0xeb, 0xec, 0x2d, 0xf9, 0xb4, 0xe7, 0xc9, 0x4d, 0x0c, 0x4e, 0xf7, - 0xd5, 0x11, 0xf2, 0xf6, 0xe6, 0x11, 0x1d, 0x1f, 0xf7, 0xd4, 0x03, 0x21, - 0xf9, 0x24, 0x26, 0xa6, 0x0f, 0x0c, 0x02, 0xe6, 0x03, 0x16, 0x0b, 0x13, - 0x24, 0xd0, 0x05, 0x23, 0x11, 0xdc, 0x19, 0x02, 0xd8, 0xf4, 0x29, 0xec, - 0x31, 0x36, 0xe9, 0x33, 0x0d, 0xe1, 0xee, 0xf8, 0x09, 0xdf, 0x04, 0x7f, - 0x33, 0x12, 0x1a, 0x03, 0xf6, 0x1b, 0x45, 0xf1, 0x19, 0xe8, 0x04, 0xf9, - 0xea, 0x06, 0xdb, 0xd8, 0x0c, 0x03, 0xdf, 0x1c, 0xe1, 0x42, 0xda, 0xd8, - 0xcd, 0xeb, 0x3f, 0x16, 0xd2, 0x2f, 0x09, 0xc8, 0x10, 0x19, 0x20, 0x19, - 0x61, 0xcc, 0x2a, 0x08, 0x12, 0xe3, 0x25, 0xf0, 0x20, 0x51, 0x4a, 0x32, - 0xe8, 0xe7, 0xfd, 0x14, 0xa6, 0xd0, 0xee, 0xc5, 0xcc, 0xe7, 0xf9, 0x60, - 0x0e, 0x09, 0xff, 0x1e, 0xe9, 0x7f, 0xec, 0xed, 0x10, 0xbb, 0x51, 0xf4, - 0x35, 0xce, 0xb7, 0xb7, 0xf3, 0x38, 0xfb, 0xeb, 0xe5, 0xf7, 0xff, 0xe3, - 0x02, 0x13, 0xa1, 0xd7, 0xf3, 0xd6, 0x14, 0x2e, 0x03, 0x11, 0xdf, 0x03, - 0xe0, 0x0c, 0xec, 0xf6, 0xee, 0x24, 0xee, 0xf1, 0xde, 0xf9, 0x03, 0xf7, - 0x0b, 0xda, 0x19, 0x14, 0xe9, 0x21, 0x13, 0xf5, 0xfa, 0x1c, 0x0c, 0x00, - 0x05, 0x13, 0x07, 0xfe, 0x0a, 0x22, 0xdd, 0x08, 0x0d, 0x7f, 0xfb, 0x18, - 0xf9, 0xe4, 0x2c, 0x17, 0xfc, 0xea, 0x15, 0x01, 0x23, 0x1f, 0x5d, 0x0a, - 0xeb, 0x61, 0x1b, 0xef, 0x03, 0xcf, 0x3a, 0xeb, 0x2c, 0x37, 0x1a, 0xb8, - 0x7c, 0x12, 0xbf, 0x61, 0xf6, 0x0a, 0x34, 0xe9, 0x09, 0xeb, 0xea, 0x57, - 0x1b, 0x21, 0xcf, 0x29, 0xa2, 0x50, 0x1c, 0xfb, 0xfa, 0x53, 0x2b, 0xd8, - 0xb2, 0xf0, 0xc8, 0x0e, 0xbd, 0x43, 0x7f, 0xde, 0xfb, 0x57, 0x1d, 0xea, - 0x02, 0xec, 0x1b, 0x0d, 0x47, 0x64, 0xf7, 0xf0, 0xfa, 0xf8, 0x2b, 0x23, - 0xdc, 0x0d, 0xf7, 0x0c, 0x31, 0x15, 0x02, 0x28, 0xeb, 0xed, 0x50, 0xee, - 0xfd, 0x25, 0x07, 0xd4, 0xb5, 0x0f, 0xcd, 0x42, 0x35, 0xfa, 0xec, 0xd4, - 0x29, 0x2d, 0x42, 0xe7, 0xf9, 0xe7, 0x1a, 0x7f, 0x26, 0x1f, 0xf2, 0x09, - 0xf7, 0xfd, 0x37, 0xf4, 0xcb, 0xe9, 0xd7, 0x00, 0xc7, 0xef, 0xef, 0xe2, - 0x05, 0xf8, 0x28, 0xe7, 0x14, 0xca, 0xdd, 0x0d, 0x0b, 0xe0, 0xda, 0xe1, - 0xfc, 0x43, 0xe4, 0xd8, 0xc6, 0x09, 0xf7, 0x05, 0x24, 0xea, 0xff, 0x43, - 0x1c, 0xe0, 0x4a, 0x23, 0x0e, 0x18, 0xfe, 0xac, 0xfb, 0xb9, 0x1f, 0x7f, - 0x37, 0xf5, 0x35, 0x31, 0x4f, 0xf2, 0x1b, 0xec, 0x77, 0xfe, 0xf4, 0xf3, - 0xa9, 0x21, 0xdd, 0xfb, 0x1a, 0xbd, 0xdf, 0xcf, 0xea, 0xe7, 0xea, 0x4e, - 0xca, 0xc8, 0x0e, 0x19, 0xee, 0xc2, 0x25, 0xd2, 0xf2, 0x99, 0x26, 0x00, - 0x2b, 0x00, 0xc8, 0x2f, 0x1c, 0x21, 0xbf, 0x1f, 0xd8, 0xaf, 0xd4, 0xf5, - 0xec, 0x10, 0x16, 0x10, 0x10, 0xef, 0xa1, 0xfd, 0xfa, 0xf6, 0x1f, 0x11, - 0x23, 0x09, 0xf4, 0xf7, 0x0b, 0x2a, 0x05, 0x11, 0xd8, 0xf2, 0xe2, 0x1e, - 0xfb, 0x06, 0x1e, 0xdf, 0x05, 0xf1, 0xf3, 0xdf, 0x0f, 0x0f, 0x09, 0x1f, - 0xf4, 0xf4, 0x23, 0xf0, 0x0c, 0x22, 0xf7, 0xd7, 0xe3, 0x10, 0xfc, 0x04, - 0x1c, 0x7f, 0x08, 0x21, 0x16, 0xec, 0xf5, 0x19, 0xe8, 0xf9, 0x06, 0xe9, - 0xfc, 0xe2, 0x49, 0x0e, 0x08, 0xba, 0xf7, 0xdb, 0x20, 0x52, 0x14, 0x2b, - 0xdf, 0x0b, 0xf6, 0x17, 0xec, 0x2f, 0x0b, 0xda, 0xed, 0x03, 0xe6, 0x1b, - 0xff, 0xf0, 0x1f, 0xf6, 0xea, 0xd2, 0xfe, 0xdf, 0x1a, 0xf2, 0xf2, 0x3f, - 0x02, 0xeb, 0x20, 0x1b, 0x1c, 0xe0, 0x27, 0xed, 0xfc, 0xd1, 0x06, 0xf6, - 0xfd, 0xe3, 0xd3, 0x7f, 0xd5, 0xde, 0xd0, 0xdd, 0xe8, 0xdd, 0x00, 0x05, - 0x13, 0x06, 0x03, 0x07, 0x18, 0x1a, 0xdb, 0x1a, 0x09, 0xff, 0xfd, 0x23, - 0xe6, 0x40, 0x87, 0xf7, 0xea, 0xf1, 0x0f, 0xff, 0xc3, 0xd9, 0xc7, 0x93, - 0xd0, 0xe1, 0x5b, 0x00, 0x0e, 0xe2, 0x07, 0xe7, 0xb9, 0xb0, 0xf8, 0xa9, - 0x09, 0x4a, 0x4d, 0xca, 0xf5, 0xf2, 0xfe, 0xbc, 0xdf, 0xe1, 0x0e, 0x35, - 0xb8, 0x08, 0x21, 0x7f, 0xd6, 0xcb, 0xe4, 0x07, 0xfa, 0x0b, 0x24, 0xf9, - 0x22, 0xde, 0x03, 0xf9, 0x32, 0xd1, 0xae, 0xd4, 0x29, 0xbb, 0x3d, 0xdf, - 0x3e, 0x1b, 0xfd, 0xe0, 0xee, 0x0c, 0x05, 0x1f, 0x04, 0xda, 0x0f, 0xe5, - 0xe0, 0x0c, 0xd4, 0xe3, 0xfa, 0xf2, 0xe2, 0xd1, 0x2a, 0x00, 0x0d, 0x08, - 0xe2, 0x20, 0xbc, 0x7f, 0x19, 0xea, 0x0e, 0xee, 0xed, 0x01, 0x15, 0x40, - 0xde, 0xe8, 0xe3, 0xf0, 0xee, 0xcc, 0xd9, 0x1a, 0x04, 0x07, 0x26, 0x0e, - 0xf1, 0xc8, 0xe9, 0x19, 0xf2, 0x04, 0xec, 0x0b, 0xec, 0x1f, 0x2a, 0x2a, - 0xdb, 0x14, 0xf7, 0xb5, 0x36, 0xcc, 0x03, 0xed, 0xe9, 0xc0, 0x64, 0x1c, - 0xd6, 0x0e, 0x1e, 0xf2, 0xba, 0x1c, 0xed, 0x69, 0x33, 0x1c, 0x1c, 0xe7, - 0x0f, 0xf0, 0x18, 0x0f, 0x22, 0xe9, 0x02, 0x76, 0x0d, 0x57, 0xfc, 0xa5, - 0xd8, 0xe8, 0x0c, 0xfd, 0xc3, 0xa2, 0xb5, 0x15, 0xbe, 0xd0, 0xe2, 0xce, - 0x5e, 0xed, 0x3a, 0xf4, 0xe3, 0x81, 0xdf, 0x09, 0x2d, 0xf6, 0xda, 0xd0, - 0xd2, 0x62, 0xf0, 0x32, 0xb5, 0xdb, 0xf6, 0x21, 0x0a, 0x1b, 0xf6, 0x10, - 0xfb, 0x1d, 0xab, 0xe8, 0x0b, 0x0a, 0xff, 0x00, 0xff, 0x01, 0x06, 0xe2, - 0x00, 0x0b, 0x0b, 0xf0, 0xee, 0xf4, 0xe4, 0x10, 0x05, 0xf1, 0xf3, 0xf4, - 0x04, 0xdf, 0xf7, 0xfb, 0xfe, 0x18, 0xf0, 0x21, 0xf3, 0x1b, 0xf4, 0xfa, - 0x1e, 0x06, 0x13, 0x04, 0x0a, 0x13, 0x01, 0x04, 0xff, 0x7f, 0xec, 0x06, - 0xf1, 0xf9, 0xe9, 0x0b, 0x07, 0xee, 0x08, 0x18, 0x12, 0x00, 0x6c, 0x0c, - 0xea, 0xe7, 0xec, 0x1e, 0xf9, 0x1d, 0xbe, 0x07, 0x15, 0xdb, 0xf0, 0x0b, - 0x21, 0xfe, 0xed, 0xf3, 0xda, 0xdf, 0x00, 0xec, 0xd9, 0xf3, 0xb2, 0xeb, - 0x0d, 0xf0, 0xfc, 0x81, 0xed, 0x0b, 0xde, 0xe8, 0x0f, 0xf1, 0x22, 0xf1, - 0x0b, 0x17, 0x0c, 0x0d, 0xe4, 0x0e, 0xfc, 0xe2, 0xf8, 0x03, 0x07, 0xf0, - 0x02, 0x0f, 0x08, 0xe5, 0xff, 0xeb, 0x40, 0x15, 0x0c, 0xf3, 0xe9, 0xe0, - 0x10, 0x14, 0x49, 0x0c, 0xdf, 0xd5, 0x02, 0xf6, 0x04, 0x0c, 0x8d, 0xef, - 0x0c, 0xfa, 0xfe, 0xf8, 0x1a, 0x07, 0xf9, 0x01, 0xf6, 0x2b, 0xfa, 0x04, - 0x07, 0x0d, 0xee, 0x01, 0xfc, 0xf1, 0x0a, 0xe7, 0xfa, 0xfb, 0x1c, 0xfe, - 0xfb, 0x02, 0x11, 0x06, 0xf4, 0x1a, 0x0e, 0x11, 0xf4, 0x16, 0xfb, 0xe9, - 0x06, 0x15, 0xde, 0x06, 0x09, 0x69, 0xfe, 0xfc, 0xfc, 0xf2, 0xf2, 0x08, - 0x0b, 0xfb, 0x22, 0xd2, 0x08, 0x24, 0x7f, 0x1f, 0xf9, 0xea, 0x02, 0x20, - 0x0f, 0x81, 0x36, 0x01, 0xf8, 0xf9, 0xf5, 0x55, 0xcd, 0x15, 0xc9, 0x1d, - 0xf0, 0x1b, 0xb3, 0x14, 0x10, 0xe4, 0x01, 0xf3, 0x5d, 0xa4, 0x13, 0xc8, - 0x1c, 0x14, 0x03, 0xf4, 0x09, 0xd7, 0x29, 0x29, 0xf3, 0xf3, 0x1d, 0x1b, - 0xfe, 0xbd, 0xdb, 0x11, 0x30, 0x91, 0x2e, 0xe7, 0xf1, 0xca, 0xe1, 0xe2, - 0x12, 0xf1, 0x86, 0xf6, 0x1d, 0x45, 0xdc, 0x25, 0x10, 0xea, 0x2a, 0xf2, - 0xf1, 0x01, 0x7f, 0xdd, 0x1d, 0x1f, 0xf9, 0x15, 0x1a, 0xe5, 0x16, 0x22, - 0xe5, 0xca, 0x08, 0x34, 0x14, 0x20, 0x35, 0x0c, 0x09, 0x0e, 0x35, 0x40, - 0xf6, 0x11, 0x35, 0xf4, 0x43, 0xf9, 0xea, 0xfd, 0xf6, 0x23, 0xe6, 0x20, - 0x2a, 0x01, 0x0b, 0x13, 0xfb, 0x16, 0x39, 0xf5, 0xdb, 0xd4, 0xcb, 0x2d, - 0xa3, 0xf0, 0x5b, 0x19, 0x4b, 0xf7, 0x0c, 0xd9, 0xfc, 0x0a, 0x1d, 0xd8, - 0x11, 0x19, 0xee, 0xe9, 0xec, 0x35, 0xf6, 0xde, 0xeb, 0x64, 0xfb, 0xd9, - 0xcd, 0x09, 0x0b, 0xde, 0x37, 0x13, 0x08, 0x81, 0xe3, 0x04, 0x11, 0xc9, - 0xe2, 0xf0, 0x23, 0x1f, 0xb4, 0x21, 0xd2, 0x4b, 0xd9, 0x17, 0xd6, 0xfa, - 0xff, 0x14, 0xd4, 0x01, 0x25, 0x06, 0xc1, 0x0a, 0x03, 0x34, 0x1d, 0xe5, - 0x0e, 0x19, 0x08, 0x23, 0xec, 0x05, 0xf1, 0x40, 0xfc, 0xf3, 0x1c, 0xcf, - 0xea, 0xbd, 0x07, 0xc5, 0x14, 0x0c, 0x24, 0x06, 0xfb, 0xf9, 0x12, 0x27, - 0xfc, 0x12, 0x98, 0xe6, 0xfd, 0xe6, 0xe9, 0x21, 0x06, 0xf9, 0xef, 0xf0, - 0xd6, 0xdf, 0x22, 0xdd, 0x11, 0x2f, 0xe6, 0x02, 0x21, 0x0e, 0x12, 0x81, - 0xe9, 0x01, 0xe8, 0x2f, 0xfd, 0xea, 0x0e, 0xe7, 0x32, 0x25, 0x0c, 0x2a, - 0xfd, 0x00, 0x2d, 0x1e, 0x10, 0x28, 0xe0, 0xf2, 0x14, 0x4a, 0xfe, 0xda, - 0xf8, 0x08, 0xf4, 0x06, 0xed, 0xc7, 0x11, 0x27, 0x2d, 0xf4, 0x1b, 0xfe, - 0xfa, 0x0d, 0x0a, 0x28, 0x2b, 0x31, 0xea, 0x53, 0x22, 0xe1, 0xcd, 0x4d, - 0xd9, 0x09, 0xce, 0xd3, 0xf8, 0x1f, 0xe9, 0x2d, 0xee, 0x05, 0xeb, 0xe4, - 0x17, 0xef, 0x0e, 0x13, 0x25, 0xdb, 0xe5, 0x03, 0xff, 0xec, 0x1d, 0x06, - 0xdc, 0x17, 0x11, 0xdd, 0x3d, 0x11, 0x12, 0xf8, 0xdf, 0x03, 0xf5, 0x7f, - 0xfd, 0xf8, 0x29, 0xd4, 0x10, 0xe7, 0xe3, 0x33, 0x10, 0xf4, 0x0a, 0xed, - 0xe6, 0xd0, 0xdd, 0x13, 0x19, 0x02, 0x01, 0x27, 0x20, 0xea, 0x42, 0x13, - 0xd8, 0x3a, 0xfa, 0xd6, 0xf9, 0x0b, 0xf2, 0xdf, 0x14, 0xe3, 0x18, 0x0e, - 0x24, 0xe9, 0x21, 0xe8, 0x15, 0x14, 0x17, 0x2d, 0xd5, 0x35, 0x0d, 0x1d, - 0x01, 0xf6, 0x1c, 0xf1, 0x21, 0xba, 0xe4, 0xfd, 0xce, 0xe4, 0xd3, 0xf5, - 0x03, 0xc2, 0x15, 0xd9, 0x0f, 0x81, 0xee, 0xe3, 0x1c, 0x1b, 0x03, 0xe8, - 0x01, 0x4f, 0xdc, 0xee, 0x1a, 0xdf, 0x83, 0xcd, 0xe3, 0xd4, 0x29, 0xcd, - 0x11, 0x4d, 0x23, 0x5c, 0x56, 0xea, 0x1b, 0x21, 0x17, 0x33, 0xe6, 0x22, - 0xdb, 0xf1, 0x1c, 0x23, 0xc2, 0x11, 0x2b, 0x0f, 0x0a, 0x36, 0x08, 0xf9, - 0x13, 0x37, 0xcb, 0xc6, 0x46, 0x59, 0x1b, 0x33, 0xf5, 0x3d, 0xe2, 0xdb, - 0xfe, 0xfd, 0x55, 0xfe, 0x45, 0xe9, 0x45, 0x7f, 0xab, 0xdc, 0x56, 0x0a, - 0x3e, 0x35, 0x4c, 0x1b, 0xbc, 0x03, 0xb7, 0x2b, 0xfd, 0xcf, 0x0d, 0x1b, - 0x31, 0xdd, 0x3c, 0xfa, 0xe2, 0xd6, 0x1a, 0x2f, 0xf5, 0x45, 0x22, 0xe4, - 0x09, 0xe1, 0xfa, 0x0a, 0x25, 0x81, 0x1a, 0x0d, 0x0c, 0xc6, 0xe5, 0xdd, - 0xed, 0xf4, 0x3b, 0x06, 0xed, 0x18, 0xc7, 0xec, 0xa9, 0xf6, 0x15, 0x04, - 0xef, 0x21, 0x12, 0x09, 0x34, 0xea, 0xff, 0xf5, 0xe2, 0x50, 0x2f, 0x07, - 0xf6, 0x08, 0xe2, 0x13, 0xe4, 0x29, 0x17, 0x04, 0x0c, 0x14, 0x04, 0xf1, - 0xe9, 0x39, 0x11, 0xa7, 0x2f, 0x2b, 0xfb, 0xdb, 0x08, 0xf1, 0x7f, 0xf7, - 0x0f, 0xd5, 0x06, 0x1a, 0xaa, 0xf3, 0xee, 0x18, 0xfd, 0x06, 0x44, 0xd8, - 0x1a, 0xc9, 0x37, 0xf9, 0xe3, 0x07, 0xc2, 0x3b, 0xf4, 0xff, 0x24, 0xe9, - 0xbe, 0xcc, 0xd0, 0x28, 0xe3, 0xab, 0xe1, 0x15, 0xcf, 0xf2, 0xf1, 0xe4, - 0x15, 0xe7, 0x2c, 0x2f, 0xe2, 0xd7, 0x04, 0x23, 0xe8, 0xf7, 0x1b, 0xe1, - 0xfe, 0x04, 0xf1, 0x2a, 0xf3, 0x0c, 0x8e, 0x91, 0xf4, 0xf6, 0x70, 0xfc, - 0x24, 0x19, 0x09, 0xd0, 0x07, 0xf7, 0xae, 0xf8, 0x25, 0xc0, 0x00, 0xf6, - 0xd7, 0x81, 0x1d, 0xde, 0xf7, 0x19, 0xd6, 0x69, 0xe1, 0x00, 0xc8, 0x22, - 0x3a, 0xdc, 0x9a, 0x1b, 0xfe, 0x40, 0x1a, 0xdd, 0x51, 0xc1, 0xe5, 0x11, - 0xf5, 0xf5, 0x41, 0xc7, 0x30, 0x01, 0xea, 0x35, 0x8f, 0x06, 0xf8, 0xba, - 0xfd, 0xea, 0x18, 0x6a, 0x37, 0xdd, 0x53, 0x01, 0x5d, 0x25, 0xfd, 0x1a, - 0xda, 0xed, 0xf5, 0x33, 0xce, 0xe4, 0xea, 0xbb, 0x31, 0x26, 0x05, 0xd8, - 0x04, 0xf3, 0x3e, 0x4f, 0xa7, 0x2f, 0xf8, 0x4f, 0xb1, 0x7f, 0x3f, 0xfc, - 0xe4, 0x30, 0x5c, 0xa3, 0xfa, 0xff, 0x1d, 0xd4, 0x29, 0x02, 0xbd, 0xb4, - 0x2a, 0x67, 0x4e, 0x0b, 0x0c, 0x3b, 0x03, 0xf6, 0x05, 0x27, 0xa2, 0xf5, - 0xee, 0x3c, 0xff, 0x02, 0x30, 0xfa, 0xe4, 0xd3, 0x1e, 0xd3, 0x30, 0xd7, - 0x4e, 0xce, 0x56, 0x32, 0x20, 0x25, 0xf3, 0xe5, 0xf5, 0x36, 0x81, 0xea, - 0xea, 0xd9, 0xfb, 0x11, 0xb6, 0xd2, 0x41, 0x07, 0xd1, 0xf3, 0xe1, 0xf6, - 0x2b, 0x19, 0x30, 0x0d, 0x9e, 0xd6, 0xe7, 0x82, 0x13, 0x43, 0x05, 0xce, - 0x05, 0xe4, 0xea, 0xb8, 0x49, 0xe2, 0xec, 0x25, 0xd8, 0xee, 0x10, 0x62, - 0x31, 0xf8, 0x1c, 0x15, 0xf2, 0x12, 0x0f, 0xf1, 0x16, 0xd0, 0xd4, 0xf8, - 0x05, 0x05, 0xa9, 0x30, 0x31, 0xf1, 0x1c, 0xe5, 0x17, 0xf0, 0xf8, 0x02, - 0x21, 0x24, 0x9c, 0xd3, 0x17, 0x15, 0x00, 0x02, 0xe6, 0x01, 0x24, 0xd9, - 0xe7, 0xe5, 0x1a, 0xdf, 0xf6, 0x19, 0xe7, 0xf3, 0xf1, 0xd9, 0x03, 0x81, - 0xdf, 0x2a, 0x1b, 0xef, 0xf6, 0xe1, 0x13, 0xcd, 0x0c, 0xcc, 0xf2, 0x21, - 0xaf, 0xec, 0x02, 0x6b, 0x24, 0xe4, 0xf4, 0x2b, 0xfc, 0x24, 0x1d, 0x01, - 0x1e, 0xfc, 0x37, 0x10, 0x1b, 0xdb, 0xa1, 0xfb, 0xfc, 0xb9, 0xf8, 0xfb, - 0x30, 0xf9, 0x7f, 0x28, 0xf5, 0x08, 0x37, 0xfa, 0x45, 0xd7, 0x05, 0x04, - 0x1d, 0x12, 0xd0, 0x1d, 0xd8, 0xc3, 0xdb, 0xdb, 0x9e, 0xe1, 0xcd, 0x9e, - 0x42, 0x02, 0xc2, 0x2a, 0xc5, 0xd3, 0xda, 0x26, 0x1e, 0xd7, 0x2f, 0x1c, - 0xf6, 0x13, 0x10, 0xdd, 0x21, 0x01, 0xfe, 0xee, 0xe6, 0x17, 0xda, 0x57, - 0x16, 0xdc, 0xb2, 0x18, 0x9e, 0x34, 0xe7, 0x52, 0xfc, 0x2c, 0x2f, 0xda, - 0x19, 0xb3, 0x02, 0xfa, 0xe0, 0xee, 0x7f, 0x16, 0xe0, 0x04, 0x07, 0xfd, - 0xdc, 0xc5, 0x2d, 0x23, 0xef, 0x25, 0xd7, 0x1b, 0x04, 0xfb, 0xe5, 0xf2, - 0x0a, 0xfd, 0xe8, 0xf9, 0xf0, 0x04, 0x07, 0x07, 0x1c, 0xe7, 0x0f, 0x0b, - 0x1b, 0x00, 0xff, 0x06, 0x23, 0x24, 0x1b, 0xf4, 0xfa, 0x04, 0x02, 0xf4, - 0x05, 0x11, 0xf7, 0xfe, 0xbb, 0xfc, 0x3e, 0x1a, 0xba, 0x0d, 0x15, 0x4a, - 0xe7, 0x0d, 0xd7, 0xfe, 0x35, 0x08, 0xea, 0x28, 0x39, 0xea, 0x59, 0x1f, - 0xfd, 0x09, 0x03, 0xfa, 0x0d, 0x09, 0xa6, 0x00, 0xf4, 0xa2, 0x16, 0xfd, - 0x06, 0xd3, 0xe9, 0x1f, 0x04, 0x14, 0x22, 0xe7, 0x03, 0x11, 0xf4, 0xed, - 0x2c, 0xe6, 0xed, 0xed, 0xb8, 0x8a, 0xff, 0xe2, 0x16, 0xfd, 0x09, 0xc8, - 0xd6, 0xb2, 0xf3, 0xff, 0x60, 0xe4, 0x14, 0x06, 0xd5, 0xe4, 0x81, 0xe0, - 0xfa, 0x40, 0x14, 0xc2, 0x13, 0x16, 0x1a, 0x18, 0xf6, 0x08, 0x23, 0xea, - 0x04, 0x4f, 0x7f, 0xf4, 0xcd, 0x19, 0x11, 0x38, 0xf8, 0xd4, 0x46, 0xc8, - 0x1d, 0x0c, 0xa1, 0x2b, 0xb6, 0xf7, 0x14, 0x04, 0x1a, 0xba, 0xce, 0xe9, - 0x41, 0x4b, 0x44, 0x01, 0x43, 0x00, 0xe6, 0xe6, 0xe8, 0xd4, 0x29, 0x09, - 0xc5, 0xfc, 0xe4, 0x9b, 0xcc, 0x20, 0x0d, 0xff, 0x1d, 0x2f, 0x21, 0x51, - 0xb9, 0xc7, 0x83, 0xd4, 0xc0, 0x4d, 0x13, 0x1c, 0x56, 0xe1, 0x46, 0xe7, - 0x32, 0xb9, 0x11, 0xea, 0x11, 0x06, 0x0d, 0xff, 0xe8, 0x2f, 0xe6, 0xf0, - 0xe6, 0x2c, 0x47, 0xed, 0x33, 0xe1, 0x2c, 0x20, 0x2a, 0x00, 0x0a, 0x25, - 0x16, 0x02, 0x27, 0xca, 0xf7, 0x10, 0x2e, 0x26, 0xd7, 0x21, 0x23, 0xb0, - 0xf0, 0xf1, 0xe6, 0xc3, 0x30, 0x11, 0xef, 0x22, 0x5c, 0x3d, 0x1f, 0xff, - 0x1e, 0x31, 0xe4, 0x7f, 0xd7, 0xd6, 0x1d, 0xd4, 0x1f, 0x16, 0x28, 0xf6, - 0x3e, 0x22, 0xbe, 0xed, 0xf1, 0x18, 0xe0, 0x40, 0xe1, 0x17, 0xfe, 0x2a, - 0xd0, 0x7f, 0xf5, 0x04, 0xde, 0x01, 0x08, 0xeb, 0xf8, 0xc4, 0xee, 0xbf, - 0x27, 0x05, 0x18, 0xe6, 0xe2, 0x1f, 0xd3, 0x10, 0x1d, 0x57, 0x0d, 0x09, - 0xca, 0x33, 0xf0, 0x04, 0x01, 0x15, 0x1f, 0xec, 0x14, 0xf3, 0xd7, 0x1a, - 0x05, 0x25, 0x30, 0x00, 0x22, 0x1e, 0x08, 0x2a, 0xd4, 0x1a, 0x15, 0xe2, - 0xe7, 0xf7, 0x75, 0xfe, 0xf1, 0x2b, 0x07, 0xf9, 0xe3, 0x05, 0xe0, 0x0e, - 0x65, 0xba, 0xb0, 0xd5, 0x15, 0x83, 0x48, 0xfb, 0xe0, 0x12, 0xda, 0xe6, - 0x33, 0xa1, 0xcd, 0xb9, 0x25, 0xcf, 0x09, 0xf9, 0x62, 0xe8, 0x11, 0x51, - 0xfa, 0xe8, 0xdd, 0xe1, 0xf2, 0xd3, 0x2d, 0xb4, 0xf7, 0x04, 0x42, 0x2f, - 0xe4, 0x27, 0xc9, 0x7f, 0xe9, 0x05, 0x41, 0xe8, 0x37, 0xc9, 0x57, 0xba, - 0xe8, 0x12, 0x31, 0x07, 0x22, 0xc6, 0xa4, 0xbf, 0xbd, 0x28, 0x00, 0xd3, - 0x3e, 0x68, 0xf5, 0xdb, 0xb7, 0x04, 0x0e, 0xf1, 0xb9, 0x81, 0x11, 0x05, - 0xf7, 0xec, 0x47, 0xa3, 0x5a, 0xe7, 0x39, 0x58, 0xf2, 0xeb, 0x45, 0xc9, - 0x0f, 0x05, 0x03, 0xed, 0x3e, 0x0f, 0x1e, 0x2d, 0xb4, 0xfd, 0x07, 0xbb, - 0x04, 0x64, 0x25, 0xb5, 0x61, 0x01, 0xb3, 0xc4, 0xed, 0x68, 0x62, 0xf9, - 0xc1, 0x3a, 0x3b, 0xf6, 0x12, 0xf4, 0x0f, 0x13, 0x06, 0x1b, 0xfa, 0xf5, - 0xe1, 0x00, 0x1d, 0x0b, 0xd6, 0x4f, 0x01, 0x0c, 0x01, 0x2e, 0x02, 0xf7, - 0xf8, 0xd1, 0xf3, 0xe6, 0x2b, 0x3e, 0xe0, 0xfd, 0xf9, 0x05, 0xcd, 0x72, - 0x06, 0x32, 0x28, 0x38, 0xc6, 0x39, 0x1d, 0x3f, 0x13, 0x2f, 0x57, 0xe9, - 0x09, 0xd8, 0x0f, 0x0d, 0x1c, 0x2a, 0xc0, 0xed, 0xfa, 0x29, 0x24, 0x13, - 0x24, 0xfe, 0x30, 0xdf, 0x09, 0x2a, 0xdc, 0xe9, 0x01, 0x7f, 0x1f, 0xfd, - 0xf4, 0x39, 0xd1, 0xc8, 0xf2, 0xf5, 0x3a, 0x27, 0x28, 0xfa, 0x73, 0x4f, - 0x41, 0x2f, 0xf8, 0xf3, 0x20, 0x0f, 0x0c, 0x04, 0xe4, 0xa4, 0xf4, 0xd1, - 0x06, 0xfd, 0xd5, 0xc9, 0xe6, 0xe8, 0x2d, 0xc1, 0x2b, 0x09, 0xf8, 0x1c, - 0x53, 0x03, 0x9d, 0x01, 0xe0, 0xf5, 0x1d, 0xca, 0xa8, 0xdf, 0x37, 0x34, - 0x0b, 0x0f, 0xdd, 0xf2, 0xc1, 0xfa, 0xfb, 0xf8, 0x31, 0xdf, 0x39, 0x4a, - 0xe9, 0xb0, 0xf7, 0xe8, 0xd5, 0xc9, 0xb3, 0x11, 0x2d, 0xf6, 0xf2, 0x43, - 0x00, 0xde, 0x81, 0x83, 0xae, 0xf7, 0xed, 0xf7, 0xfe, 0x12, 0xc2, 0xda, - 0x08, 0x26, 0xe6, 0x20, 0xf4, 0xf1, 0xfc, 0x5c, 0x2a, 0x1b, 0xfc, 0x4d, - 0x22, 0x2e, 0xfa, 0x03, 0xfd, 0xf9, 0x07, 0x22, 0x03, 0xf6, 0x0f, 0x29, - 0x0f, 0x30, 0xe7, 0x23, 0xd2, 0x1a, 0x0e, 0xee, 0x1e, 0x06, 0xdf, 0xf0, - 0xf2, 0x1f, 0xdb, 0x03, 0xe2, 0x0b, 0x1a, 0xfb, 0x1f, 0x00, 0xcb, 0xc7, - 0x18, 0xfb, 0x0b, 0x0b, 0x0e, 0x12, 0x7f, 0x23, 0xdf, 0xc2, 0x0d, 0x13, - 0xc3, 0x84, 0xe7, 0xc0, 0x28, 0xf4, 0x29, 0xde, 0x23, 0xc6, 0xe8, 0x49, - 0x57, 0x18, 0x06, 0xb2, 0xb3, 0xb7, 0x3c, 0x25, 0x3b, 0x53, 0x07, 0x17, - 0x81, 0xf6, 0x0a, 0xf3, 0xeb, 0x1c, 0xd0, 0xae, 0x4d, 0x1f, 0xdb, 0xe3, - 0xef, 0x63, 0x6a, 0x14, 0xbd, 0x7d, 0x00, 0xce, 0xe1, 0x18, 0x04, 0x40, - 0x1a, 0xe2, 0xd0, 0xd6, 0xd8, 0x6b, 0xf0, 0x72, 0x1d, 0xfd, 0x1f, 0x11, - 0x4a, 0xf4, 0xf4, 0xcd, 0xbe, 0x7c, 0xf4, 0x0f, 0xb9, 0x1b, 0x51, 0xfb, - 0x44, 0xbf, 0x36, 0xb8, 0xfd, 0xd0, 0xbe, 0xfc, 0x12, 0xde, 0x15, 0x3f, - 0xd0, 0x0f, 0xcd, 0x38, 0xd8, 0x64, 0x3e, 0xb2, 0x06, 0x31, 0xe1, 0xd9, - 0x13, 0x32, 0xc7, 0x3a, 0x10, 0x49, 0x22, 0x2c, 0xd6, 0xe1, 0x38, 0xfd, - 0x14, 0xf4, 0x7f, 0xee, 0xf8, 0x1f, 0x47, 0xfe, 0xee, 0xcb, 0xa9, 0x28, - 0x32, 0x50, 0xf6, 0xfb, 0x17, 0x45, 0x04, 0x03, 0xef, 0x79, 0xab, 0x13, - 0x11, 0xde, 0xe7, 0x34, 0x0f, 0x50, 0xbf, 0x81, 0xeb, 0xcb, 0x1c, 0x10, - 0xcc, 0xfb, 0xdf, 0xec, 0x0e, 0x21, 0x28, 0x8f, 0xcb, 0x0b, 0x42, 0x37, - 0xed, 0xcf, 0xcc, 0xfe, 0x25, 0x4a, 0x2b, 0xf8, 0xe4, 0x50, 0x2b, 0x17, - 0xf7, 0x24, 0xfd, 0x5d, 0x06, 0x74, 0x32, 0x05, 0x12, 0x04, 0xe4, 0x2c, - 0x03, 0x9a, 0xe9, 0x12, 0x3a, 0x0d, 0x29, 0xbc, 0xeb, 0xed, 0x0e, 0xdd, - 0x26, 0xfd, 0xee, 0xf2, 0xff, 0xfb, 0x02, 0x0a, 0xca, 0xf8, 0xf7, 0xe8, - 0xf5, 0x05, 0x15, 0x0b, 0x0e, 0x0a, 0x0c, 0xe3, 0x22, 0xe9, 0x1f, 0x81, - 0xef, 0x38, 0x39, 0xec, 0xf6, 0x14, 0x0b, 0xf3, 0xfc, 0xf0, 0xe3, 0x14, - 0xd2, 0x0a, 0xf9, 0x35, 0x04, 0x0a, 0x06, 0x1f, 0x11, 0x34, 0xf5, 0xea, - 0x1b, 0xdf, 0x18, 0xf5, 0x05, 0xc2, 0xce, 0x14, 0x09, 0xc7, 0xed, 0x0c, - 0xf7, 0xd6, 0x70, 0x02, 0x13, 0x15, 0x22, 0x1f, 0x3b, 0xee, 0x8e, 0x13, - 0x09, 0xdb, 0xe9, 0xf9, 0xc3, 0x33, 0x10, 0xe0, 0xc3, 0x33, 0xd3, 0x81, - 0x2a, 0x28, 0xab, 0x18, 0xed, 0xe3, 0xcc, 0x41, 0x4a, 0x1e, 0xba, 0x7c, - 0xd9, 0x20, 0x1a, 0x11, 0x17, 0xe0, 0xf2, 0x10, 0xdb, 0x09, 0x1f, 0x31, - 0xe6, 0x07, 0xe3, 0xc6, 0x13, 0x0e, 0xdb, 0x10, 0xfc, 0x0c, 0x46, 0xeb, - 0x47, 0xe7, 0xda, 0xe3, 0xfd, 0xe8, 0x15, 0x1b, 0xdd, 0x1b, 0x19, 0xef, - 0xfd, 0x0e, 0x62, 0xee, 0x35, 0x4d, 0xe3, 0x27, 0xe2, 0xf9, 0xfd, 0x83, - 0x06, 0x31, 0xd2, 0x1b, 0x34, 0x0d, 0x81, 0x42, 0xfd, 0xc7, 0x0f, 0xf8, - 0xde, 0xe7, 0xdd, 0x64, 0x12, 0x1a, 0x24, 0x09, 0xd0, 0x3f, 0x1b, 0xe7, - 0xfd, 0xe5, 0x34, 0x40, 0xf5, 0xea, 0xb7, 0x2c, 0xe5, 0xff, 0xdc, 0x55, - 0x26, 0xe4, 0x0b, 0x10, 0xd7, 0xeb, 0xc7, 0xeb, 0xec, 0x2c, 0x57, 0x09, - 0xee, 0x7f, 0x12, 0x64, 0xe9, 0x1d, 0x4c, 0x19, 0x35, 0xf9, 0x1e, 0x06, - 0x07, 0x31, 0x02, 0xad, 0xee, 0xf0, 0x27, 0xeb, 0xf6, 0x49, 0x17, 0x07, - 0xdf, 0x0d, 0x29, 0xdc, 0x11, 0xf5, 0x5c, 0xe6, 0xf3, 0x17, 0x9a, 0x50, - 0x08, 0x00, 0x3d, 0xe5, 0x30, 0xd8, 0xef, 0x6b, 0x1c, 0xf8, 0xe9, 0xc4, - 0x03, 0xe0, 0x07, 0x08, 0xe3, 0xd4, 0xb7, 0x1b, 0xfd, 0x25, 0xe9, 0x13, - 0xe9, 0xdb, 0xe8, 0x16, 0xff, 0x21, 0xd2, 0xd8, 0xe5, 0x00, 0xf9, 0xe0, - 0xff, 0xfe, 0xee, 0xe3, 0xde, 0xff, 0x20, 0x0a, 0x0a, 0xf1, 0xda, 0xfb, - 0x0c, 0x25, 0x2f, 0xdf, 0x0b, 0xd8, 0x0f, 0xd3, 0x13, 0xfe, 0x0b, 0x0d, - 0x0e, 0xf5, 0xf7, 0x07, 0x1a, 0xf9, 0x0a, 0xf8, 0x0b, 0x24, 0xf5, 0x0f, - 0x0e, 0x7f, 0xfa, 0x07, 0xf4, 0xdf, 0xeb, 0x04, 0xf0, 0x2b, 0x07, 0x27, - 0x02, 0xef, 0x6e, 0x19, 0x2a, 0xf1, 0x0e, 0x3e, 0x0f, 0xd8, 0x17, 0x15, - 0xd2, 0x2d, 0xee, 0x11, 0xcf, 0xd6, 0xf6, 0x31, 0x0b, 0x09, 0x49, 0xff, - 0x1e, 0x09, 0x2f, 0x04, 0x5b, 0xb8, 0x26, 0x1b, 0xc6, 0x0e, 0xe1, 0x51, - 0x19, 0x02, 0x1f, 0xe8, 0x27, 0xa4, 0xf4, 0x18, 0xac, 0x1a, 0xd9, 0xd2, - 0x2e, 0x04, 0x29, 0xb9, 0xf3, 0x81, 0xde, 0xd4, 0x33, 0xe5, 0x37, 0xca, - 0x30, 0xf2, 0x4d, 0x12, 0x01, 0xfa, 0x96, 0xae, 0x24, 0x25, 0xf5, 0xbd, - 0x14, 0x30, 0xe8, 0xe2, 0xdb, 0x1c, 0xf1, 0x05, 0xb3, 0x2c, 0xe7, 0x13, - 0x0e, 0x17, 0xc1, 0x0c, 0x55, 0x00, 0xe2, 0x07, 0xc3, 0xc9, 0x1a, 0xe9, - 0x3e, 0x3c, 0x44, 0xb9, 0xf0, 0x0d, 0xef, 0x03, 0x8b, 0xaa, 0xbb, 0xf5, - 0x0f, 0xd6, 0xfa, 0x53, 0x0d, 0xf6, 0x30, 0x21, 0x1f, 0x7f, 0xf8, 0x18, - 0x0d, 0x1f, 0x47, 0x15, 0xe3, 0xc9, 0xf0, 0x22, 0xe4, 0x4f, 0x14, 0x26, - 0x21, 0xff, 0xeb, 0x50, 0x28, 0x44, 0x83, 0x0d, 0xec, 0xdf, 0xe2, 0xbe, - 0x05, 0xe4, 0xbc, 0xac, 0xf8, 0xeb, 0x64, 0xbe, 0xd6, 0x47, 0x01, 0xfd, - 0xb8, 0xf1, 0xea, 0x81, 0xbd, 0x42, 0x39, 0x07, 0x1b, 0xe9, 0xce, 0xe9, - 0x22, 0x42, 0x48, 0x1c, 0x31, 0x01, 0x5d, 0x7e, 0x12, 0xe4, 0xd9, 0x13, - 0xd2, 0x1f, 0x1e, 0xbd, 0xe4, 0xbc, 0x13, 0xf7, 0xfc, 0xea, 0xde, 0xf4, - 0x54, 0xd5, 0x56, 0xb4, 0xef, 0xe0, 0x13, 0xfb, 0x1a, 0x05, 0xb7, 0x0f, - 0x16, 0xf0, 0x0c, 0xe3, 0x11, 0xf0, 0x30, 0xf8, 0xf0, 0x20, 0xf5, 0xdd, - 0x0d, 0x08, 0x04, 0x05, 0xee, 0xf3, 0xed, 0x99, 0xf3, 0xf9, 0x18, 0x20, - 0xf8, 0x1a, 0xde, 0xf7, 0x37, 0x31, 0x38, 0xf6, 0x0f, 0x1b, 0xf3, 0xda, - 0x00, 0xfe, 0xd4, 0x1f, 0x10, 0x7f, 0x17, 0x1c, 0xec, 0xf1, 0x15, 0x1e, - 0x15, 0x16, 0x3e, 0x06, 0x18, 0x12, 0x45, 0x08, 0xe8, 0x08, 0x02, 0xd8, - 0xf9, 0xf8, 0xdd, 0x04, 0x11, 0xda, 0xf3, 0x12, 0x10, 0xfb, 0xe1, 0xe7, - 0xe1, 0xf5, 0xf3, 0xf7, 0xf0, 0x09, 0xe5, 0x1c, 0xf0, 0x07, 0xfe, 0xa2, - 0xe0, 0xd2, 0x31, 0x02, 0x1b, 0x0f, 0xcf, 0xfd, 0x03, 0x1e, 0x10, 0x04, - 0xe7, 0x1f, 0x17, 0xf8, 0x11, 0x04, 0x1a, 0x05, 0xfc, 0x7f, 0x09, 0x06, - 0xe9, 0x18, 0x04, 0x25, 0x10, 0xf9, 0xfd, 0x0a, 0x24, 0x03, 0x7f, 0x16, - 0xdc, 0xf4, 0x0d, 0x00, 0x1b, 0x04, 0xce, 0xf9, 0x33, 0xd0, 0xf8, 0xf8, - 0x22, 0x09, 0x1c, 0xed, 0xc1, 0xee, 0x1c, 0xdd, 0x1a, 0xf1, 0xf8, 0xff, - 0x13, 0x04, 0xfa, 0x81, 0xd3, 0xdc, 0xdb, 0x0c, 0x0c, 0xff, 0xfd, 0xff, - 0x19, 0x47, 0x19, 0x18, 0x18, 0x0d, 0x23, 0x33, 0x01, 0x1e, 0xf8, 0xfe, - 0x10, 0x4b, 0x1f, 0x18, 0xe8, 0xe8, 0xf4, 0x35, 0x1f, 0xe1, 0x01, 0x11, - 0xfe, 0xf8, 0x71, 0x13, 0xf1, 0x11, 0xe7, 0xef, 0x38, 0xed, 0x0a, 0xf0, - 0x28, 0x03, 0xec, 0x29, 0xf4, 0x1d, 0x0b, 0x1b, 0xd3, 0x7a, 0xe5, 0x14, - 0x20, 0x1a, 0x4f, 0xd2, 0xee, 0x01, 0x39, 0xf0, 0xd2, 0x1f, 0x10, 0x1d, - 0x7f, 0x60, 0xde, 0xcf, 0xeb, 0xea, 0x25, 0xd8, 0xb4, 0x21, 0x3e, 0x12, - 0xbd, 0x4e, 0xcf, 0xdf, 0x08, 0x03, 0x1c, 0xf8, 0xfe, 0x14, 0x0e, 0xfc, - 0xd1, 0xdd, 0x08, 0xf1, 0xe3, 0x21, 0xd9, 0x36, 0x4e, 0xe5, 0x24, 0xbb, - 0x11, 0xe4, 0x44, 0x0c, 0xf9, 0xb8, 0x11, 0x11, 0x10, 0xcf, 0x41, 0xa5, - 0x1d, 0xde, 0xec, 0xb9, 0x4a, 0xef, 0x19, 0xfb, 0xbe, 0xbb, 0xbd, 0x7f, - 0x32, 0x25, 0xeb, 0xc9, 0xec, 0x20, 0x30, 0xfd, 0xc3, 0x07, 0xe8, 0xd3, - 0xda, 0xca, 0xcb, 0x38, 0x24, 0xf2, 0x27, 0x21, 0xf9, 0xda, 0xea, 0x06, - 0xe5, 0x22, 0xed, 0x12, 0xee, 0x35, 0xc5, 0xd7, 0xf2, 0x2e, 0x8a, 0x88, - 0x7d, 0xcc, 0xe3, 0xf0, 0xfa, 0x0f, 0x0a, 0xff, 0xe1, 0xc3, 0xfd, 0x01, - 0xd5, 0x19, 0xd7, 0xaf, 0x07, 0x0b, 0x43, 0xa1, 0x3d, 0x1c, 0x0a, 0x12, - 0x38, 0xda, 0x8b, 0x7f, 0xfd, 0xe7, 0x02, 0x29, 0xa8, 0xd9, 0xf5, 0x5f, - 0xd6, 0x9d, 0xcf, 0xfb, 0xf9, 0xf6, 0xc1, 0xcd, 0x34, 0xf8, 0x1c, 0x2d, - 0x02, 0xd1, 0x1d, 0xec, 0xec, 0x17, 0xe7, 0x1d, 0xe6, 0x4a, 0x13, 0x34, - 0xa6, 0x24, 0xb6, 0xdd, 0x2d, 0x31, 0xf2, 0xfa, 0xf4, 0xba, 0x69, 0xf5, - 0x28, 0xd3, 0x01, 0x0e, 0xc1, 0xde, 0x34, 0x5e, 0xed, 0x06, 0x4e, 0xed, - 0x19, 0x26, 0x13, 0xbe, 0x7f, 0xf8, 0x2b, 0xf9, 0xc4, 0x2d, 0x16, 0xca, - 0x00, 0xe8, 0x1d, 0xa3, 0xd0, 0xb5, 0xe5, 0x40, 0x17, 0xcf, 0xdb, 0x25, - 0xe7, 0xdd, 0x0e, 0xba, 0xd6, 0x8b, 0xff, 0x17, 0x4e, 0xc6, 0xe2, 0xf0, - 0xe7, 0x30, 0xeb, 0x36, 0xe1, 0xc6, 0x14, 0xda, 0xcb, 0xf6, 0x2d, 0xbc, - 0x58, 0xb0, 0xd9, 0xef, 0xfb, 0xdd, 0xa6, 0x24, 0xe0, 0x39, 0x41, 0x5c, - 0xb7, 0xf6, 0x0c, 0x27, 0x9f, 0xc5, 0xce, 0xe2, 0x41, 0xb4, 0x33, 0x07, - 0xff, 0xc6, 0xf2, 0xcd, 0x00, 0xef, 0x2f, 0x3b, 0x39, 0x0f, 0x7f, 0xbd, - 0xd4, 0xa8, 0xdb, 0xce, 0xc8, 0x07, 0x00, 0xbd, 0xe5, 0xd6, 0xd0, 0xd8, - 0xe8, 0xdd, 0xbd, 0x33, 0xe9, 0x38, 0x55, 0xfc, 0xec, 0xa1, 0x07, 0x4c, - 0xb8, 0x33, 0xc1, 0x3d, 0x51, 0x12, 0x0f, 0xda, 0x28, 0xc2, 0xc5, 0xdf, - 0xb6, 0xcc, 0xcf, 0x1a, 0x11, 0xee, 0xe9, 0xba, 0x43, 0x10, 0xdb, 0xfe, - 0x19, 0x2c, 0x81, 0x11, 0x2d, 0x04, 0xc5, 0x0a, 0x14, 0x54, 0xec, 0xd7, - 0x38, 0xb9, 0x05, 0xbf, 0x3c, 0xdc, 0x2c, 0xfa, 0x09, 0xcb, 0xb3, 0xa1, - 0xd3, 0x11, 0x43, 0x29, 0xc0, 0x13, 0x18, 0x58, 0x00, 0xd5, 0x20, 0x1d, - 0x3c, 0xea, 0x10, 0xc3, 0x07, 0x3f, 0x01, 0xed, 0xc8, 0x2e, 0x23, 0x2c, - 0xf4, 0xf0, 0x1b, 0xd9, 0x1b, 0x05, 0x00, 0x8e, 0x06, 0x11, 0x01, 0xe5, - 0xd5, 0xf0, 0xf7, 0x09, 0xdf, 0x50, 0xec, 0xfc, 0xec, 0x2d, 0x03, 0x17, - 0x01, 0x3f, 0x21, 0xed, 0x0f, 0x1c, 0xcb, 0xe8, 0x21, 0x4a, 0x29, 0xd3, - 0xef, 0x57, 0xf4, 0x1a, 0x09, 0x30, 0x1f, 0x23, 0x00, 0x2a, 0x7f, 0xe9, - 0x09, 0xe1, 0xfa, 0x0c, 0x1c, 0x4b, 0x17, 0x0b, 0xca, 0x16, 0x18, 0xbc, - 0xd8, 0xc4, 0xf3, 0xe3, 0xf4, 0x0c, 0xd1, 0x3a, 0x3c, 0x22, 0x30, 0x42, - 0xde, 0xed, 0x0d, 0x0a, 0xe1, 0xbe, 0xea, 0xf1, 0xda, 0x26, 0xf4, 0x65, - 0xef, 0xaa, 0x85, 0x0e, 0x0d, 0x4c, 0xa8, 0x11, 0xff, 0x39, 0x36, 0xb2, - 0x09, 0xfa, 0x38, 0xca, 0xd7, 0x31, 0xb7, 0xb2, 0xd9, 0x14, 0xe1, 0x36, - 0xea, 0xd4, 0xd3, 0xe5, 0xf2, 0x7f, 0x41, 0x26, 0xe9, 0x74, 0x05, 0x48, - 0xee, 0x04, 0x0b, 0xe9, 0xdf, 0x1b, 0xbc, 0x06, 0xfd, 0xce, 0xe7, 0x23, - 0x1c, 0xe8, 0xe4, 0x10, 0xf0, 0xe6, 0x34, 0xc7, 0x2e, 0xee, 0x01, 0xd9, - 0xf4, 0xf1, 0xff, 0x81, 0xd5, 0x01, 0xdd, 0xf5, 0x23, 0xe1, 0xee, 0x0a, - 0x1c, 0x36, 0x17, 0xe3, 0xde, 0x0f, 0x27, 0x23, 0x1a, 0xfd, 0xf1, 0xdc, - 0x0d, 0x35, 0x21, 0x0e, 0xf3, 0x34, 0x2f, 0x25, 0x31, 0xad, 0xe1, 0xed, - 0xe9, 0x09, 0x0b, 0xd5, 0xce, 0xfa, 0x26, 0xd1, 0xde, 0xa6, 0x12, 0x5d, - 0xf2, 0x31, 0x44, 0x1f, 0x19, 0x7f, 0x00, 0xdb, 0x1a, 0xc4, 0x0c, 0x59, - 0xc0, 0x2e, 0x55, 0x89, 0x23, 0xed, 0x40, 0x14, 0xe0, 0xbb, 0xf0, 0xe0, - 0x07, 0xb5, 0x24, 0xee, 0x07, 0xe7, 0x63, 0x79, 0x2f, 0xe6, 0xca, 0xf9, - 0x55, 0x97, 0x21, 0x44, 0x50, 0xf0, 0xe8, 0xf8, 0x40, 0x30, 0x15, 0x9a, - 0x15, 0x10, 0x2a, 0x0e, 0xff, 0xf0, 0x04, 0x05, 0x03, 0xdd, 0xf8, 0xe2, - 0xf4, 0x0a, 0xd6, 0x08, 0x0d, 0xde, 0x07, 0x03, 0x1e, 0xf2, 0x12, 0xf4, - 0xe3, 0x1b, 0x11, 0xe0, 0xf5, 0x00, 0xed, 0x0a, 0xf4, 0x10, 0x01, 0xf3, - 0x07, 0xee, 0xfc, 0xe6, 0x05, 0xf2, 0x04, 0xfd, 0xf8, 0xfb, 0x1b, 0x03, - 0xee, 0x05, 0x0e, 0xee, 0xe9, 0x0b, 0xe1, 0x14, 0x11, 0x7f, 0x07, 0xf8, - 0xeb, 0xdf, 0x1f, 0x11, 0x12, 0x0b, 0xf8, 0xfd, 0xf3, 0x01, 0x40, 0x0c, - 0x04, 0x07, 0x1f, 0x06, 0xbb, 0x0e, 0x1f, 0x00, 0xf3, 0xfc, 0x0f, 0xf4, - 0xec, 0x2f, 0xfc, 0xce, 0x1d, 0x02, 0xc6, 0xd0, 0xf8, 0xdd, 0x06, 0x1e, - 0x06, 0xf2, 0x10, 0x0b, 0xf3, 0xe9, 0x3c, 0xf9, 0xd9, 0xf3, 0x5a, 0x0a, - 0x18, 0x49, 0xc6, 0x24, 0x43, 0xe8, 0x2d, 0xee, 0x0d, 0xcc, 0xea, 0x7f, - 0x29, 0xe7, 0x09, 0xf2, 0xe6, 0x0e, 0x2e, 0xf3, 0xf1, 0xe7, 0xbb, 0x0a, - 0xf3, 0x16, 0xf9, 0x08, 0x0d, 0xcc, 0x0b, 0x04, 0x3d, 0x7f, 0xfc, 0x67, - 0xe0, 0xf6, 0x8b, 0x3e, 0x1b, 0x0b, 0x28, 0x1a, 0x9a, 0x1c, 0xbf, 0x02, - 0x94, 0x14, 0x1d, 0xc7, 0xe5, 0xcc, 0xea, 0x27, 0x0f, 0x01, 0xdd, 0x4b, - 0xf5, 0x0e, 0x28, 0x37, 0xc7, 0x38, 0x60, 0xe8, 0x0f, 0xeb, 0xfb, 0x2d, - 0x2e, 0xc7, 0xe3, 0x7c, 0x1e, 0xf0, 0xda, 0xcd, 0x01, 0x32, 0xf3, 0x41, - 0x4a, 0x2e, 0xc8, 0x1d, 0x38, 0xf5, 0xf1, 0x25, 0x45, 0x14, 0xef, 0x05, - 0xd0, 0x1d, 0x34, 0xfd, 0x0e, 0x1e, 0xfc, 0x58, 0x84, 0x2a, 0xc6, 0x23, - 0xe5, 0xf5, 0x29, 0x33, 0x61, 0x05, 0x16, 0x1c, 0xc1, 0xe4, 0xce, 0xb5, - 0xc4, 0x7b, 0xf0, 0x20, 0x00, 0xfd, 0xdb, 0x14, 0xcf, 0x95, 0xd3, 0xf3, - 0xce, 0x18, 0x1a, 0x61, 0xf8, 0xdc, 0xc5, 0x3c, 0x05, 0x7f, 0xea, 0xfe, - 0xe7, 0xf4, 0x4c, 0x29, 0xdd, 0xe0, 0xb9, 0x0d, 0x14, 0x41, 0x3d, 0x19, - 0xc6, 0x13, 0xa9, 0xe3, 0xcc, 0xd0, 0x16, 0x7f, 0x20, 0x11, 0x08, 0x42, - 0xdc, 0x70, 0x45, 0xcf, 0x3b, 0xab, 0xea, 0x44, 0x22, 0x18, 0x58, 0xd3, - 0xf9, 0x1d, 0x4d, 0xfb, 0xfa, 0xd0, 0x09, 0x09, 0xf9, 0xd6, 0xec, 0x29, - 0x4a, 0x26, 0x65, 0x42, 0x30, 0xfc, 0xd6, 0x18, 0x3f, 0xec, 0x06, 0xf2, - 0x09, 0xff, 0xc3, 0x36, 0x47, 0xf9, 0x09, 0xc5, 0xdf, 0x01, 0x12, 0x07, - 0xfc, 0x0a, 0xe1, 0x09, 0x3e, 0xdb, 0x01, 0x35, 0x0a, 0xf6, 0x36, 0xd8, - 0xfe, 0x14, 0x03, 0x02, 0xce, 0xf1, 0xeb, 0x0b, 0x05, 0xd7, 0x10, 0xe9, - 0xf8, 0xcb, 0x2d, 0xf5, 0xeb, 0xba, 0x29, 0x2c, 0xd0, 0x33, 0x0c, 0x29, - 0xfc, 0xd1, 0xf7, 0xcd, 0xf8, 0xca, 0xe1, 0x1a, 0xc4, 0x18, 0xfd, 0xc6, - 0xf2, 0xe2, 0x1b, 0xdc, 0xff, 0x81, 0xdf, 0xf5, 0x04, 0xc5, 0x2f, 0xcf, - 0x2d, 0x47, 0xff, 0xf8, 0xe3, 0xd5, 0x82, 0xd3, 0x19, 0xc3, 0xe9, 0x18, - 0x0b, 0x3f, 0x3f, 0x41, 0x1f, 0x06, 0x01, 0x13, 0x8e, 0xf2, 0x11, 0x92, - 0x42, 0x1c, 0x16, 0x20, 0xdf, 0x09, 0xfb, 0x06, 0x2d, 0x81, 0xea, 0xcf, - 0x2c, 0x0b, 0x2e, 0xef, 0x11, 0xb8, 0xc2, 0xfc, 0x2c, 0xf3, 0x17, 0x1f, - 0x28, 0xca, 0xea, 0x05, 0x06, 0x93, 0xef, 0x66, 0xfa, 0x5b, 0x19, 0xe9, - 0x06, 0x02, 0xd2, 0x40, 0x27, 0xf7, 0xd6, 0x0e, 0xdb, 0xb8, 0xc1, 0xde, - 0xfe, 0xfe, 0x0a, 0x0d, 0x24, 0x05, 0x0e, 0xe8, 0xed, 0x1c, 0xe3, 0xed, - 0x0a, 0xc3, 0xf4, 0xee, 0xd9, 0x81, 0xf2, 0x08, 0x20, 0x0b, 0xf4, 0x09, - 0x0d, 0xec, 0x09, 0xfd, 0x0f, 0xec, 0xfc, 0x19, 0xe8, 0xed, 0x02, 0xd4, - 0xda, 0xf1, 0xff, 0xf2, 0x0c, 0x05, 0xfd, 0x02, 0x15, 0x18, 0xe5, 0xfb, - 0xed, 0xfe, 0x21, 0xff, 0x26, 0x17, 0x16, 0xf8, 0x05, 0x0a, 0xec, 0x0b, - 0xfb, 0xf2, 0x1b, 0x8e, 0xe3, 0xe9, 0x7f, 0x20, 0xf9, 0xee, 0xed, 0x22, - 0x0a, 0xe0, 0x06, 0x2c, 0x36, 0x09, 0x0e, 0xf0, 0xf6, 0xeb, 0x26, 0xfb, - 0xcc, 0xc5, 0xff, 0xbc, 0x13, 0x06, 0x17, 0x08, 0xe8, 0xeb, 0x07, 0xd7, - 0xf9, 0xcb, 0x14, 0x58, 0x26, 0xfc, 0xec, 0xdc, 0x06, 0xce, 0x01, 0xf6, - 0xdb, 0x0d, 0xc2, 0x0e, 0x9c, 0xe5, 0xe0, 0xca, 0xbc, 0x0d, 0xe6, 0x03, - 0xd3, 0xfb, 0x2c, 0xfb, 0x2a, 0x07, 0xdf, 0x1a, 0x10, 0xca, 0xf1, 0x17, - 0x08, 0x27, 0x17, 0x4b, 0xfc, 0xfa, 0xbb, 0x59, 0x03, 0xf6, 0x0f, 0x18, - 0x10, 0xe3, 0x17, 0x12, 0x0d, 0x37, 0xf9, 0xd1, 0xf1, 0xcb, 0xe2, 0x16, - 0x36, 0xda, 0x1d, 0x4d, 0x25, 0xdc, 0xd9, 0x35, 0x17, 0x2c, 0x23, 0xe3, - 0xfa, 0xe4, 0x0b, 0x16, 0xe3, 0xd1, 0x00, 0x7f, 0x0c, 0x0c, 0xf3, 0xaa, - 0xf2, 0xed, 0x06, 0x46, 0x2d, 0x11, 0x20, 0xed, 0xec, 0xf4, 0xfc, 0x15, - 0xd9, 0xe5, 0x03, 0x0f, 0x07, 0x7f, 0xe2, 0x32, 0x12, 0x0a, 0x06, 0x17, - 0xed, 0x1e, 0xe1, 0xd5, 0x00, 0x0a, 0xd4, 0x12, 0xed, 0xe8, 0xe9, 0xef, - 0x25, 0xc0, 0x01, 0x04, 0x2c, 0xfb, 0xda, 0x1d, 0xf4, 0x17, 0xfe, 0x04, - 0x12, 0x0d, 0x06, 0xca, 0x27, 0xfb, 0x00, 0x38, 0x10, 0xe6, 0xe2, 0x58, - 0xf0, 0xe4, 0xde, 0xdb, 0xf3, 0xe2, 0x1b, 0x03, 0xde, 0x12, 0x02, 0xfb, - 0x17, 0xf9, 0xd3, 0x24, 0xe0, 0xc8, 0xf0, 0x20, 0x1c, 0x5e, 0x98, 0xfc, - 0x14, 0xd8, 0xf0, 0xee, 0x30, 0x00, 0xee, 0xbb, 0xac, 0x06, 0x1b, 0x0e, - 0x33, 0x19, 0xcc, 0x33, 0xb9, 0x08, 0xfe, 0xf0, 0xf6, 0xd1, 0x4b, 0xe6, - 0x08, 0x20, 0xc8, 0xf0, 0x09, 0x13, 0x2f, 0xef, 0xe8, 0x17, 0x15, 0xf3, - 0x0d, 0x06, 0x1f, 0x2a, 0x0c, 0x7f, 0x2e, 0xe7, 0xbe, 0x01, 0x1c, 0x29, - 0x12, 0x18, 0xdc, 0xc6, 0x10, 0x18, 0x67, 0x0a, 0x00, 0xf0, 0x28, 0xd1, - 0xc2, 0x7f, 0xff, 0x05, 0x02, 0xf4, 0x35, 0x13, 0xf0, 0xff, 0x28, 0xb9, - 0x0f, 0x26, 0xea, 0xd9, 0x15, 0x24, 0x00, 0x27, 0xce, 0x24, 0x0f, 0x3f, - 0xe9, 0x14, 0x0b, 0xde, 0x0b, 0x03, 0x07, 0xce, 0x27, 0xe1, 0xd9, 0x0b, - 0x05, 0x04, 0x03, 0x0c, 0xd3, 0xed, 0xff, 0x2c, 0xd1, 0x10, 0xf3, 0x13, - 0x20, 0x18, 0x1e, 0xf8, 0xf7, 0x09, 0xff, 0x33, 0xf4, 0x0f, 0xfb, 0x1f, - 0x14, 0xba, 0x0b, 0xdd, 0x02, 0x4a, 0xc3, 0xef, 0x02, 0x07, 0x08, 0x06, - 0x2d, 0x3b, 0x11, 0xca, 0xc9, 0x17, 0x1d, 0x09, 0xfa, 0x1b, 0xc2, 0x14, - 0xdd, 0x2a, 0xe1, 0x1c, 0x0f, 0xe4, 0x04, 0xd2, 0xfb, 0xff, 0x21, 0x1d, - 0xf7, 0x16, 0xf7, 0x03, 0x0b, 0xfc, 0x1b, 0x15, 0xfc, 0x16, 0xd0, 0x6e, - 0x03, 0x3e, 0xf3, 0xfd, 0x05, 0xc7, 0x04, 0x16, 0x06, 0xbb, 0x35, 0xea, - 0x23, 0x1b, 0x7f, 0x08, 0x07, 0xcc, 0x09, 0x00, 0x04, 0x18, 0xed, 0xea, - 0xdb, 0xd5, 0xf1, 0x18, 0x00, 0xff, 0x31, 0xed, 0xf9, 0xec, 0x12, 0xed, - 0x13, 0xf0, 0xf7, 0x17, 0x0c, 0xfe, 0xf9, 0xb2, 0xd5, 0xfb, 0x09, 0xfa, - 0x0c, 0xfd, 0x0b, 0xe0, 0x2b, 0x1c, 0x37, 0xf8, 0xf9, 0x1b, 0x39, 0x0f, - 0x16, 0xf5, 0xe3, 0x0e, 0x0a, 0x53, 0x1e, 0x07, 0xd5, 0xfe, 0x1e, 0x0e, - 0xf1, 0x81, 0xea, 0x13, 0x26, 0x02, 0x37, 0xfe, 0x57, 0x1c, 0x23, 0xf9, - 0x1f, 0xe5, 0x4b, 0x2c, 0xee, 0xa2, 0xfd, 0x1d, 0x24, 0xf5, 0x06, 0xfa, - 0xc4, 0xed, 0xf8, 0xab, 0x23, 0xc0, 0xe6, 0x1a, 0x0f, 0x00, 0x81, 0x59, - 0xd6, 0xce, 0xe0, 0xd2, 0x99, 0xfe, 0xe3, 0x00, 0x12, 0x17, 0x12, 0x1c, - 0x1b, 0x14, 0x07, 0xe3, 0x3b, 0xf7, 0x12, 0x24, 0xfd, 0xdf, 0x03, 0xfa, - 0xe7, 0xdd, 0x04, 0x1a, 0xfc, 0x0b, 0xed, 0xfb, 0x2e, 0xdc, 0xe6, 0xd6, - 0xdd, 0x03, 0x1b, 0x45, 0xbe, 0x06, 0x0a, 0xeb, 0x0a, 0xe6, 0x05, 0xf6, - 0x52, 0xd7, 0x18, 0x59, 0xb6, 0x16, 0xe1, 0xce, 0xd0, 0xe8, 0xea, 0xdc, - 0x07, 0x60, 0x22, 0x55, 0xfc, 0x91, 0xca, 0x18, 0x1c, 0x0a, 0xb1, 0x14, - 0x64, 0x68, 0x3a, 0xf7, 0x32, 0x06, 0x38, 0x81, 0x0b, 0x14, 0x05, 0xa7, - 0x1d, 0xfb, 0x21, 0x22, 0x05, 0xf7, 0xdc, 0x10, 0x01, 0xff, 0x0a, 0x14, - 0x1d, 0xe6, 0x09, 0x0e, 0xcc, 0x28, 0xfa, 0xe4, 0xdf, 0xfd, 0xe6, 0x0a, - 0xf8, 0x53, 0xe2, 0xc3, 0x37, 0x1f, 0x51, 0x59, 0xcb, 0xe1, 0x64, 0x62, - 0x08, 0x64, 0xf1, 0xf4, 0xde, 0x35, 0x7f, 0x08, 0xf9, 0xe5, 0x14, 0xd1, - 0x30, 0x07, 0xe6, 0x01, 0x0a, 0x25, 0x03, 0xf6, 0x15, 0x28, 0x19, 0xf9, - 0xb7, 0x14, 0xe9, 0xc9, 0x1e, 0x74, 0xfd, 0xe1, 0x12, 0x06, 0xef, 0x01, - 0x03, 0x1f, 0xf7, 0x2c, 0x2d, 0xc3, 0x49, 0x4d, 0xec, 0x00, 0x18, 0xbf, - 0xb9, 0xb5, 0xe2, 0xc1, 0xda, 0x02, 0x3b, 0xf3, 0x5d, 0x21, 0x1a, 0x19, - 0xec, 0xf9, 0xf2, 0xe5, 0x38, 0xd6, 0xed, 0x3e, 0xea, 0x38, 0x10, 0x3a, - 0xe1, 0x00, 0x31, 0xc9, 0xe8, 0x4d, 0x17, 0xdc, 0xe4, 0x3d, 0x91, 0x02, - 0xdd, 0x48, 0x30, 0x28, 0xff, 0x03, 0x56, 0xf0, 0x1b, 0xad, 0x3f, 0x43, - 0x39, 0x12, 0xbf, 0xea, 0xcb, 0xed, 0x7f, 0xfa, 0x21, 0x53, 0xfb, 0xff, - 0xfe, 0x13, 0x1e, 0x14, 0x0b, 0xed, 0x10, 0x21, 0x1e, 0x18, 0xfc, 0x25, - 0x5f, 0xea, 0x41, 0x08, 0x0d, 0x30, 0xf8, 0xd1, 0xec, 0xda, 0xcf, 0x2a, - 0xf0, 0x3f, 0x02, 0x7c, 0xfc, 0x81, 0xce, 0x24, 0x1c, 0x0e, 0xde, 0x13, - 0x08, 0x1d, 0x42, 0x15, 0xe6, 0x0f, 0xf4, 0xc5, 0xeb, 0x19, 0xcc, 0xa4, - 0x0c, 0xd6, 0x07, 0x23, 0xd9, 0xf9, 0x07, 0xea, 0xec, 0x46, 0x22, 0x41, - 0x17, 0x23, 0x4a, 0x1a, 0x3e, 0x0c, 0x01, 0xed, 0x23, 0x15, 0x1a, 0x34, - 0xcf, 0xaf, 0x1f, 0xdd, 0xef, 0xe2, 0x27, 0x11, 0x0c, 0x1e, 0xe2, 0xd3, - 0x05, 0x25, 0x26, 0xf6, 0xec, 0x0c, 0xaf, 0x79, 0x0c, 0xb1, 0xed, 0x1e, - 0xb7, 0xfd, 0xd4, 0x47, 0xc4, 0x2a, 0xd8, 0xdc, 0x14, 0xd9, 0xde, 0xba, - 0xf6, 0x1e, 0x18, 0x02, 0xff, 0x05, 0xdd, 0x46, 0xbc, 0xf6, 0x01, 0x23, - 0xf9, 0x7f, 0xfc, 0x39, 0xb6, 0x75, 0xd7, 0x0c, 0x1c, 0x36, 0xdb, 0xcd, - 0x04, 0xef, 0x14, 0x13, 0x41, 0x06, 0x00, 0x08, 0x21, 0x01, 0x33, 0x07, - 0xee, 0xd0, 0x11, 0x12, 0x2d, 0x23, 0x0d, 0xe5, 0xdc, 0x20, 0xff, 0xf2, - 0xf3, 0xfa, 0x1b, 0xe9, 0xb0, 0x2c, 0xf2, 0xd2, 0x31, 0x29, 0xd2, 0x20, - 0xfc, 0x01, 0x23, 0x24, 0x14, 0x24, 0xf8, 0x01, 0x06, 0xf1, 0x12, 0x1a, - 0x7f, 0xd4, 0xf1, 0xb7, 0x06, 0xe4, 0xf7, 0xef, 0xb8, 0x24, 0x00, 0xe4, - 0x21, 0xd1, 0x0a, 0x37, 0xee, 0xd5, 0x3b, 0xef, 0xd4, 0xe4, 0x08, 0xf8, - 0xd0, 0x03, 0x16, 0x0c, 0x28, 0xe7, 0x36, 0xc4, 0xf8, 0x0d, 0xff, 0xe2, - 0x04, 0xbd, 0xcc, 0xe2, 0xfa, 0x07, 0xdd, 0x1c, 0xe7, 0xf9, 0x10, 0xf3, - 0x02, 0xd0, 0xda, 0xf9, 0xfb, 0xfd, 0xee, 0xe7, 0x29, 0x03, 0x0f, 0xba, - 0xfd, 0x89, 0x01, 0x22, 0x1c, 0x01, 0xe6, 0xdc, 0x07, 0xdc, 0xe8, 0xdb, - 0xe1, 0xd1, 0x81, 0x99, 0xfb, 0xd6, 0x02, 0x06, 0xed, 0x03, 0xb4, 0xdc, - 0xf5, 0xe9, 0x13, 0x1d, 0x03, 0x0f, 0x00, 0x02, 0xef, 0x0c, 0xfa, 0xf5, - 0xe1, 0xe0, 0xe4, 0x12, 0xd9, 0xf8, 0xf0, 0xcc, 0x13, 0xe4, 0xe6, 0xef, - 0x17, 0x27, 0x04, 0x07, 0xec, 0x16, 0x2d, 0x0f, 0x00, 0xf1, 0x09, 0x16, - 0x06, 0x16, 0xdb, 0x16, 0xee, 0x7f, 0xfd, 0x26, 0x0d, 0x21, 0xed, 0xfd, - 0xe5, 0x33, 0x04, 0x03, 0xf4, 0x12, 0x62, 0x21, 0xe6, 0xeb, 0xed, 0xea, - 0xd3, 0x3d, 0xac, 0xeb, 0xbd, 0xd4, 0x1e, 0xda, 0x00, 0x23, 0xe9, 0xe0, - 0xce, 0x06, 0xb9, 0xeb, 0xdb, 0x08, 0x16, 0x20, 0x0a, 0x10, 0xea, 0xa4, - 0xe4, 0xc6, 0xe6, 0xf3, 0x09, 0xfc, 0xc9, 0x2d, 0x0e, 0x38, 0x19, 0xdd, - 0xd9, 0x39, 0x2a, 0xfa, 0x0c, 0x2e, 0xe0, 0x1f, 0x19, 0x7f, 0xe4, 0x1b, - 0xd8, 0xd3, 0x37, 0x22, 0x31, 0xdd, 0xf0, 0xd6, 0x26, 0xf7, 0x5a, 0xed, - 0xf7, 0xe0, 0x1f, 0xd6, 0xf7, 0x81, 0x19, 0x25, 0x22, 0xe9, 0xbf, 0x09, - 0x0c, 0xeb, 0xe9, 0x76, 0x00, 0x10, 0xf5, 0x0a, 0xdd, 0xe6, 0xbd, 0x95, - 0x31, 0xe3, 0x21, 0x19, 0x49, 0x2a, 0xd9, 0xf0, 0xf8, 0x98, 0xc8, 0x2b, - 0xd0, 0x42, 0x25, 0x0e, 0x4b, 0xc8, 0xe4, 0x0d, 0xd1, 0xc4, 0x19, 0xe2, - 0x03, 0x2a, 0x9b, 0xca, 0x08, 0xe2, 0xc2, 0x20, 0x34, 0x32, 0x2d, 0x15, - 0xf2, 0xb2, 0xec, 0x23, 0xeb, 0x04, 0x19, 0x2a, 0x54, 0x0f, 0x04, 0xe0, - 0xec, 0xd3, 0xc1, 0x20, 0xe0, 0x41, 0x11, 0xf9, 0xe9, 0x26, 0xfb, 0xcb, - 0xf1, 0x15, 0xe3, 0x81, 0x27, 0x04, 0xe9, 0x14, 0xea, 0xc5, 0x1b, 0x11, - 0x39, 0xc9, 0x18, 0x3a, 0xe2, 0x3a, 0x63, 0xcd, 0xf7, 0xc8, 0x13, 0xda, - 0x57, 0xc0, 0xce, 0xfc, 0xce, 0x07, 0xc9, 0xb4, 0xe7, 0xc9, 0x11, 0x23, - 0x10, 0xf4, 0x36, 0xf4, 0x6a, 0xfb, 0xd7, 0xee, 0xf9, 0x4b, 0x09, 0xdf, - 0xd0, 0xf1, 0x08, 0x4e, 0x2c, 0xfb, 0x1e, 0x58, 0x1b, 0x1c, 0x09, 0x81, - 0xf0, 0x58, 0xf0, 0xac, 0x2f, 0x00, 0xd5, 0xff, 0xd4, 0x81, 0xcb, 0x17, - 0x3d, 0x0b, 0x0c, 0x1b, 0xf2, 0xf9, 0x3e, 0x32, 0xe2, 0x25, 0xcd, 0x32, - 0x3b, 0x09, 0x3d, 0x09, 0x45, 0xce, 0x2f, 0x1e, 0x43, 0xe3, 0x28, 0x15, - 0xf8, 0xdd, 0x3d, 0xc4, 0x0b, 0x23, 0x8f, 0xb7, 0xf6, 0x03, 0xfb, 0xe2, - 0x0d, 0x04, 0x17, 0x10, 0x20, 0x1a, 0xee, 0x4b, 0xec, 0x7f, 0xf2, 0x1e, - 0x2b, 0xf7, 0x1d, 0x29, 0x0d, 0xf9, 0xfc, 0x21, 0xed, 0x10, 0x13, 0xe9, - 0x00, 0xfc, 0x41, 0x1b, 0xf4, 0x19, 0xf2, 0x17, 0xde, 0xfe, 0x13, 0xfe, - 0xe2, 0x17, 0xfd, 0x02, 0xea, 0x21, 0xe8, 0xe9, 0xf2, 0x27, 0xf4, 0x12, - 0x3d, 0xd0, 0x12, 0x07, 0xfd, 0xe9, 0xf0, 0x04, 0x1d, 0xe1, 0x13, 0xf9, - 0xef, 0x03, 0xf7, 0x12, 0x59, 0x19, 0x12, 0x1e, 0xd6, 0x0e, 0x05, 0x42, - 0xfa, 0xab, 0x09, 0xfd, 0xe1, 0xd6, 0x0d, 0xb6, 0x18, 0xb0, 0xea, 0xfc, - 0x17, 0xb6, 0x09, 0x09, 0x2d, 0x2c, 0xc9, 0x37, 0x13, 0xf2, 0xc9, 0xcd, - 0xcd, 0xdb, 0x08, 0x0e, 0x03, 0xb0, 0xef, 0x0a, 0xb8, 0xc6, 0xe7, 0x21, - 0xe5, 0x07, 0x2c, 0x0e, 0xfa, 0xa2, 0x09, 0x14, 0x04, 0x0b, 0xeb, 0x07, - 0x02, 0x43, 0x08, 0x2c, 0xc6, 0xe3, 0xab, 0x81, 0x0b, 0xf7, 0xf3, 0xfd, - 0x12, 0xd7, 0x0a, 0x08, 0xfe, 0x04, 0x09, 0x37, 0xf5, 0x00, 0xe0, 0x66, - 0x2c, 0x07, 0x0d, 0x15, 0x35, 0xea, 0xed, 0xcb, 0x46, 0xf5, 0xff, 0xed, - 0xb6, 0x2a, 0x09, 0x30, 0x0d, 0xf5, 0x43, 0xf9, 0x2a, 0xab, 0x00, 0xf6, - 0xe8, 0xe0, 0x05, 0x1d, 0x0b, 0xd1, 0x0f, 0x81, 0xda, 0xb5, 0xfd, 0x0e, - 0x29, 0xf4, 0x02, 0xe8, 0x1b, 0x3c, 0xf8, 0xe2, 0xf3, 0xbe, 0xdf, 0xd9, - 0x00, 0x0b, 0xef, 0xbe, 0xeb, 0x19, 0x9c, 0x12, 0x23, 0x06, 0x24, 0x1d, - 0x10, 0xec, 0xd8, 0xd7, 0xf8, 0xfc, 0xfc, 0x25, 0x06, 0x19, 0xd4, 0x0c, - 0xd4, 0x0e, 0xf0, 0xfd, 0x10, 0xe9, 0xde, 0x26, 0x0c, 0x1e, 0x08, 0x2c, - 0x2f, 0xeb, 0x28, 0xfd, 0x0d, 0x27, 0xf5, 0x07, 0xdf, 0x0a, 0xfe, 0x27, - 0xed, 0x7f, 0x0d, 0x1b, 0xdc, 0x1e, 0xcb, 0x03, 0x1a, 0xda, 0xed, 0xd2, - 0x15, 0x02, 0x71, 0x30, 0xda, 0x52, 0x10, 0x24, 0xfe, 0x3a, 0x29, 0x2e, - 0xe4, 0xb9, 0xe0, 0x1f, 0x20, 0x3d, 0xce, 0xca, 0x31, 0x21, 0x0f, 0xe3, - 0xbd, 0x4c, 0xe3, 0xcf, 0xc1, 0xf4, 0xec, 0xfe, 0x66, 0x9c, 0x1f, 0x01, - 0xfd, 0x9f, 0x33, 0x21, 0x30, 0xfc, 0x35, 0xf5, 0xf5, 0xcb, 0xd0, 0xed, - 0xda, 0x81, 0xfc, 0x41, 0x22, 0x56, 0x05, 0x24, 0x15, 0xed, 0x79, 0xde, - 0x25, 0xef, 0x36, 0xd0, 0x0f, 0xf8, 0xfc, 0x21, 0xe2, 0x05, 0x35, 0x03, - 0xef, 0xd9, 0x07, 0xeb, 0x1f, 0xff, 0x06, 0xe5, 0xfb, 0xdb, 0x05, 0x0c, - 0xe1, 0x8c, 0xfe, 0x16, 0x07, 0xf7, 0xf7, 0xec, 0x0c, 0xeb, 0x0d, 0xca, - 0x15, 0x0c, 0xe2, 0xd8, 0xe3, 0x12, 0xe4, 0xcf, 0x0d, 0x17, 0xeb, 0xf1, - 0xd1, 0x13, 0x12, 0x0c, 0x26, 0x07, 0x06, 0xda, 0x10, 0x3c, 0xef, 0x24, - 0x1d, 0x3d, 0xfc, 0xf2, 0x38, 0xdf, 0x20, 0x0b, 0x0d, 0xf7, 0xfc, 0x81, - 0x9b, 0xb3, 0xf3, 0x4e, 0xd4, 0xdd, 0x81, 0xd7, 0x00, 0x70, 0xe0, 0xe0, - 0x3e, 0x0b, 0xd2, 0x7b, 0x95, 0x1f, 0x00, 0x6c, 0xc8, 0x29, 0x29, 0xd6, - 0x0a, 0x48, 0x45, 0x94, 0xed, 0x10, 0xb1, 0x38, 0xeb, 0xe8, 0x93, 0xd7, - 0xfe, 0x3f, 0x0f, 0x17, 0x15, 0x39, 0xf3, 0x92, 0xe8, 0x03, 0xf9, 0x04, - 0x27, 0x04, 0x3b, 0xf4, 0x14, 0x32, 0x18, 0xc9, 0xf8, 0xc5, 0xf5, 0xe8, - 0x24, 0xaf, 0x3a, 0x68, 0x0a, 0x02, 0x35, 0x21, 0xc1, 0x54, 0x21, 0xcb, - 0xe8, 0xb9, 0x3a, 0xfc, 0x21, 0xaf, 0x00, 0x1d, 0xea, 0xb3, 0x1a, 0xe1, - 0x0b, 0xf8, 0xe6, 0x1c, 0xe9, 0x18, 0xb3, 0xd8, 0x1e, 0xd4, 0xa4, 0xfa, - 0x7f, 0xf4, 0xf4, 0x61, 0x3d, 0xba, 0x3c, 0xe9, 0x1c, 0x8d, 0xf2, 0x0f, - 0x00, 0x1b, 0xed, 0xf9, 0xad, 0x03, 0x2a, 0x93, 0xa8, 0x60, 0xe4, 0x49, - 0x0a, 0x06, 0xd1, 0xfb, 0xe1, 0x02, 0xeb, 0x39, 0xf4, 0xf4, 0xee, 0x24, - 0x0a, 0x3f, 0x01, 0x2a, 0x1c, 0x1a, 0x0b, 0xfd, 0x24, 0xe8, 0xea, 0x81, - 0xc2, 0xf1, 0x28, 0xc3, 0xca, 0x06, 0x29, 0xd3, 0xe4, 0xe6, 0x0b, 0xc1, - 0xb9, 0xed, 0x21, 0x15, 0xcf, 0xe4, 0xe8, 0xe6, 0x4f, 0xf3, 0x1c, 0xff, - 0xd7, 0xed, 0xf8, 0x03, 0x1d, 0xe7, 0x0c, 0x0a, 0x2d, 0x28, 0x14, 0xd3, - 0x25, 0xb0, 0x46, 0x20, 0x0b, 0xf7, 0xa2, 0x28, 0x46, 0x11, 0x24, 0xdf, - 0x74, 0x2d, 0xff, 0xff, 0x78, 0x2d, 0xff, 0xff, 0x72, 0x95, 0xff, 0xff, - 0x04, 0x00, 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x02, 0x19, 0xf8, 0xfb, - 0xf1, 0xd6, 0xfa, 0xfb, 0xf9, 0x01, 0xb9, 0xf1, 0xf8, 0xf9, 0xf8, 0x09, - 0xee, 0x06, 0x0c, 0xee, 0x16, 0xfd, 0x0a, 0xca, 0xff, 0x1f, 0xf1, 0xfc, - 0xfd, 0x13, 0x00, 0x0d, 0xf3, 0xd5, 0x0d, 0xec, 0xfa, 0x00, 0x2e, 0x12, - 0xff, 0x0b, 0x21, 0x0b, 0x07, 0xeb, 0x05, 0x01, 0x03, 0xff, 0xbb, 0xeb, - 0x00, 0x09, 0xfc, 0x11, 0xe6, 0xfc, 0xf6, 0xf9, 0xff, 0xdb, 0xfe, 0xfe, - 0x04, 0xfd, 0x02, 0xfb, 0xeb, 0xf3, 0x01, 0xf2, 0xfc, 0xf9, 0xe8, 0xe7, - 0xfd, 0xfd, 0xf5, 0x0b, 0xe7, 0x07, 0x08, 0xeb, 0xf2, 0xfd, 0x07, 0xc0, - 0x13, 0x1e, 0xfd, 0xf4, 0x00, 0x08, 0x03, 0x0b, 0xf9, 0xf4, 0xf8, 0xf6, - 0x02, 0x00, 0x22, 0x19, 0x00, 0x0c, 0x0a, 0x10, 0x0d, 0xed, 0xee, 0x06, - 0x10, 0xf9, 0xe9, 0xec, 0xfb, 0x15, 0x0b, 0x1c, 0xf9, 0x0d, 0xfd, 0xf6, - 0x07, 0xeb, 0x01, 0xfe, 0x05, 0xfc, 0xf9, 0x00, 0xf4, 0xd3, 0xfb, 0xf2, - 0xf7, 0xff, 0xed, 0xeb, 0xfe, 0xfe, 0x05, 0xfd, 0xe9, 0xf5, 0x0e, 0xf2, - 0xfe, 0xff, 0xfa, 0xf2, 0x02, 0x1a, 0xf7, 0x01, 0xf8, 0xfe, 0x04, 0xf7, - 0xf8, 0xf9, 0xfd, 0xec, 0x06, 0xfa, 0x17, 0x16, 0xf0, 0x15, 0x12, 0xff, - 0x19, 0xf8, 0xff, 0x06, 0x1e, 0x0b, 0xda, 0xf8, 0xfb, 0x0c, 0xeb, 0x0c, - 0xfc, 0xef, 0xff, 0xfb, 0xfc, 0xe1, 0x03, 0x03, 0x0d, 0xf8, 0xed, 0x01, - 0xf7, 0xc9, 0x14, 0xf2, 0x01, 0x06, 0x13, 0xf3, 0xeb, 0xfa, 0x03, 0x04, - 0xf6, 0xf4, 0x04, 0xf4, 0xf3, 0x00, 0x01, 0x19, 0x1f, 0x0a, 0x01, 0x01, - 0xfd, 0x03, 0x0a, 0x02, 0x0d, 0xea, 0xf1, 0xfc, 0x0c, 0xf9, 0x10, 0x22, - 0xf4, 0x15, 0x16, 0xfb, 0x10, 0xe6, 0x0c, 0x02, 0x08, 0xf9, 0xea, 0xf0, - 0x06, 0xfe, 0xe7, 0x09, 0x0a, 0x00, 0x00, 0xf4, 0x00, 0xd9, 0xef, 0x0a, - 0x07, 0x01, 0xf3, 0xfb, 0x01, 0xbe, 0xef, 0xf0, 0xf8, 0x04, 0x15, 0x0b, - 0x03, 0xee, 0x05, 0x07, 0xfc, 0xfc, 0x0e, 0xf4, 0xff, 0x00, 0xfe, 0xe7, - 0x1e, 0x11, 0xfe, 0xfb, 0x02, 0x05, 0x0a, 0x0b, 0x0f, 0xe5, 0xf5, 0xf4, - 0x0c, 0x05, 0x16, 0x17, 0xed, 0x17, 0x11, 0xf2, 0x0e, 0xf0, 0xff, 0xe6, - 0x22, 0x0c, 0x13, 0xee, 0xfb, 0xf7, 0xd5, 0x14, 0x09, 0x00, 0x09, 0x08, - 0xff, 0xe4, 0xfe, 0x08, 0x07, 0x08, 0x03, 0xfd, 0x08, 0xde, 0xfd, 0xfe, - 0xfb, 0x03, 0xfc, 0xe9, 0x08, 0xf1, 0xfb, 0x23, 0xff, 0x02, 0x08, 0xf1, - 0xfe, 0xfe, 0x03, 0x02, 0x28, 0x15, 0xf3, 0x1c, 0x02, 0xfb, 0x0f, 0x10, - 0xff, 0xe5, 0x01, 0xee, 0x16, 0x05, 0x1b, 0x0e, 0xed, 0x14, 0x19, 0xfa, - 0x0c, 0xfc, 0x01, 0xd4, 0x21, 0x1c, 0x02, 0x02, 0xfc, 0xf6, 0xf0, 0x15, - 0x0e, 0x1c, 0x0a, 0x01, 0x0c, 0xf3, 0xfa, 0x0d, 0x0c, 0x04, 0xe9, 0xf5, - 0x13, 0xb5, 0x36, 0xf5, 0x17, 0x03, 0xf6, 0xfa, 0x0b, 0xef, 0xf9, 0x0b, - 0xfc, 0xff, 0xff, 0xf6, 0xf3, 0x06, 0xfb, 0x09, 0x31, 0x05, 0xfb, 0x40, - 0x0f, 0x01, 0x0a, 0x0b, 0xf5, 0xda, 0x1a, 0xf2, 0x16, 0x18, 0x19, 0x0a, - 0xea, 0x14, 0x11, 0xdd, 0x07, 0x1d, 0x06, 0xdb, 0x12, 0x03, 0xf2, 0xf0, - 0x0f, 0xf7, 0xd2, 0x10, 0x06, 0x0c, 0x15, 0xf2, 0xfc, 0xe9, 0xed, 0x11, - 0x08, 0xf9, 0xcd, 0xf0, 0x0e, 0xc9, 0x47, 0xfa, 0x11, 0xf1, 0xd5, 0xec, - 0x36, 0xe5, 0xf4, 0x0d, 0xfd, 0xf8, 0xe5, 0xf8, 0xf7, 0xf6, 0xfd, 0x03, - 0x20, 0x10, 0xfc, 0x4b, 0x15, 0xf7, 0x0a, 0x0d, 0xf9, 0xe5, 0xf6, 0xee, - 0x1d, 0x28, 0x20, 0x0b, 0x00, 0x15, 0x0a, 0xf2, 0x00, 0x27, 0xf1, 0xad, - 0x20, 0xc7, 0xf7, 0x0d, 0xfa, 0xf9, 0xcf, 0x01, 0x10, 0x1e, 0x0f, 0xf9, - 0x04, 0xf1, 0xe3, 0x09, 0x18, 0x01, 0xda, 0xe4, 0x06, 0xe1, 0x5c, 0xe4, - 0xfe, 0xf7, 0xea, 0xfd, 0x40, 0xff, 0xf3, 0x18, 0xf7, 0x04, 0xf1, 0xf9, - 0xea, 0xf4, 0xe9, 0x06, 0x0f, 0x09, 0xfe, 0x5e, 0x13, 0xe2, 0x0b, 0x04, - 0xe9, 0xf8, 0xfe, 0xe5, 0x2e, 0x33, 0x13, 0x08, 0xff, 0x10, 0xf8, 0xd6, - 0x0e, 0x2a, 0xf4, 0xc1, 0x14, 0xb6, 0x20, 0x12, 0x00, 0x06, 0xcf, 0x16, - 0x00, 0x3d, 0x09, 0x01, 0x06, 0xfb, 0xd3, 0x0a, 0xf5, 0x07, 0xd4, 0xf9, - 0x04, 0xd5, 0x5e, 0xdb, 0x10, 0xe9, 0xeb, 0xf4, 0x31, 0xe4, 0xf2, 0x25, - 0xf2, 0x01, 0xfd, 0xf3, 0xea, 0xfc, 0xf5, 0xf0, 0x06, 0x12, 0xf1, 0x4f, - 0x10, 0xde, 0x05, 0x03, 0x18, 0xf2, 0xf8, 0xf6, 0x24, 0x39, 0x11, 0x01, - 0xfc, 0x0e, 0xf9, 0xdf, 0xeb, 0x2b, 0xe9, 0xab, 0x13, 0x9b, 0x11, 0x18, - 0xef, 0x17, 0xf5, 0x11, 0x0b, 0x43, 0x1c, 0xf9, 0x03, 0x0f, 0x9b, 0x1a, - 0xf2, 0x06, 0xdf, 0xf1, 0xf9, 0xec, 0x44, 0xcd, 0xfa, 0xd4, 0x0c, 0xe0, - 0x32, 0xe4, 0xfe, 0x1f, 0xff, 0x23, 0x04, 0xef, 0xda, 0xed, 0xf2, 0xf4, - 0xf6, 0x0d, 0xf3, 0x5b, 0xfb, 0xd6, 0x08, 0x00, 0x1c, 0x0a, 0x0b, 0x04, - 0x26, 0x2a, 0x11, 0x0f, 0x0b, 0x09, 0xe1, 0xe6, 0xe5, 0x12, 0xfb, 0x95, - 0x10, 0x83, 0x02, 0x11, 0xea, 0x15, 0xea, 0x0f, 0x03, 0x36, 0x07, 0x02, - 0x07, 0x0f, 0x90, 0x21, 0xe7, 0x02, 0xe0, 0x0c, 0xf7, 0xee, 0x4c, 0xda, - 0x03, 0xe4, 0x1e, 0x06, 0x3a, 0xef, 0xfe, 0x08, 0xf7, 0x28, 0x0b, 0xf2, - 0xd8, 0xe8, 0xf7, 0x12, 0x17, 0x00, 0xe7, 0x1c, 0xeb, 0xd5, 0x06, 0xf9, - 0x1a, 0x09, 0xe7, 0xf4, 0x10, 0x1d, 0x03, 0xfd, 0x08, 0x0f, 0xde, 0xe7, - 0xff, 0x17, 0xfb, 0xae, 0x28, 0x86, 0x0e, 0x22, 0xde, 0x0e, 0xe0, 0x17, - 0x0f, 0x17, 0x12, 0xfb, 0x17, 0x27, 0x81, 0x43, 0xd4, 0xef, 0xe0, 0x0d, - 0xf8, 0xd2, 0x1d, 0xd3, 0x05, 0xe1, 0x27, 0xf7, 0x35, 0xfe, 0xfd, 0x19, - 0xeb, 0x34, 0x24, 0xeb, 0xec, 0xf9, 0x06, 0x3b, 0xff, 0x03, 0xde, 0x00, - 0xe1, 0xd0, 0x00, 0xfe, 0x2e, 0x04, 0xd7, 0x15, 0xf8, 0x0f, 0xfd, 0xea, - 0x1f, 0x07, 0xdd, 0xf1, 0xeb, 0x10, 0xfa, 0xc6, 0x18, 0xad, 0x2e, 0x15, - 0xde, 0x13, 0xeb, 0x13, 0x07, 0x1e, 0x11, 0xf7, 0x19, 0x1f, 0x94, 0x43, - 0xd0, 0xf6, 0xd0, 0x23, 0x02, 0xd2, 0x06, 0xd8, 0xf2, 0xd1, 0x0e, 0xfe, - 0x1f, 0xfd, 0x00, 0x18, 0xf2, 0x41, 0x0c, 0xe5, 0xfc, 0xe7, 0x03, 0x06, - 0x09, 0xfb, 0xe5, 0xeb, 0xe2, 0xc7, 0x14, 0xfd, 0x1f, 0x28, 0xf9, 0x21, - 0xed, 0x18, 0xf2, 0xeb, 0x22, 0x05, 0xd8, 0xdf, 0xd0, 0x11, 0xeb, 0xda, - 0x0a, 0xea, 0x11, 0x03, 0xd7, 0x04, 0xda, 0x11, 0x05, 0x27, 0x18, 0x01, - 0x15, 0x16, 0xc1, 0x49, 0xde, 0xe6, 0xbb, 0x15, 0x05, 0xce, 0xee, 0xde, - 0xf9, 0xbb, 0x1b, 0x16, 0x27, 0x05, 0xf1, 0x16, 0xe9, 0x47, 0x06, 0xe6, - 0xf9, 0xe8, 0xf2, 0x14, 0x12, 0xf4, 0xac, 0xd6, 0xe0, 0xd4, 0x0a, 0xf9, - 0x21, 0x33, 0xe6, 0x2d, 0xeb, 0x0d, 0xe7, 0xf8, 0x18, 0xf9, 0xd9, 0xf6, - 0xde, 0x1d, 0xe2, 0x04, 0xfe, 0x37, 0x0a, 0x06, 0xd2, 0x0d, 0xe0, 0x1c, - 0xf2, 0x0e, 0x23, 0xf8, 0x26, 0x19, 0xf2, 0x49, 0x48, 0x31, 0xff, 0xff, - 0x42, 0x99, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, - 0xdf, 0x06, 0x00, 0x00, 0xe1, 0xfc, 0xff, 0xff, 0xd2, 0xec, 0xff, 0xff, - 0xff, 0xe1, 0xff, 0xff, 0x69, 0xfb, 0xff, 0xff, 0x16, 0xd1, 0xff, 0xff, - 0x34, 0x02, 0x00, 0x00, 0x6c, 0xd4, 0xff, 0xff, 0x30, 0xfe, 0xff, 0xff, - 0xd8, 0x0f, 0x00, 0x00, 0x5f, 0xfb, 0xff, 0xff, 0xd4, 0xdb, 0xff, 0xff, - 0x5a, 0x0d, 0x00, 0x00, 0x34, 0x16, 0x00, 0x00, 0xe1, 0xf4, 0xff, 0xff, - 0x58, 0xea, 0xff, 0xff, 0x42, 0xf2, 0xff, 0xff, 0x9e, 0xf4, 0xff, 0xff, - 0xfc, 0xef, 0xff, 0xff, 0x30, 0x18, 0x00, 0x00, 0x03, 0x05, 0x00, 0x00, - 0x32, 0x17, 0x00, 0x00, 0x56, 0x04, 0x00, 0x00, 0xc2, 0xfe, 0xff, 0xff, - 0xba, 0xf2, 0xff, 0xff, 0x50, 0xf4, 0xff, 0xff, 0x4b, 0x0d, 0x00, 0x00, - 0xe4, 0xfb, 0xff, 0xff, 0x02, 0xf5, 0xff, 0xff, 0xd6, 0x18, 0x00, 0x00, - 0xb2, 0xfd, 0xff, 0xff, 0x08, 0x07, 0x00, 0x00, 0xae, 0xf2, 0xff, 0xff, - 0xb9, 0x03, 0x00, 0x00, 0x29, 0xf1, 0xff, 0xff, 0x3e, 0x03, 0x00, 0x00, - 0xe4, 0x05, 0x00, 0x00, 0xad, 0x0b, 0x00, 0x00, 0x42, 0x10, 0x00, 0x00, - 0x25, 0x02, 0x00, 0x00, 0x50, 0xfd, 0xff, 0xff, 0x9d, 0x01, 0x00, 0x00, - 0xa0, 0x0e, 0x00, 0x00, 0x39, 0xe9, 0xff, 0xff, 0x08, 0x0b, 0x00, 0x00, - 0x25, 0x14, 0x00, 0x00, 0x57, 0xee, 0xff, 0xff, 0xb4, 0xc6, 0xff, 0xff, - 0x49, 0x02, 0x00, 0x00, 0x44, 0xf4, 0xff, 0xff, 0x88, 0xf5, 0xff, 0xff, - 0x30, 0x10, 0x00, 0x00, 0xcb, 0x02, 0x00, 0x00, 0x71, 0x0d, 0x00, 0x00, - 0xa6, 0xe8, 0xff, 0xff, 0xaf, 0x10, 0x00, 0x00, 0xae, 0xfe, 0xff, 0xff, - 0x26, 0xfa, 0xff, 0xff, 0x9d, 0xeb, 0xff, 0xff, 0x13, 0xff, 0xff, 0xff, - 0x16, 0xfc, 0xff, 0xff, 0x4e, 0x07, 0x00, 0x00, 0x2b, 0xfb, 0xff, 0xff, - 0xea, 0xf9, 0xff, 0xff, 0x4e, 0x9a, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, - 0x00, 0x10, 0x00, 0x00, 0x01, 0xf7, 0xb9, 0xe4, 0x3b, 0x7f, 0xcc, 0xb8, - 0xe8, 0xcc, 0xaa, 0x1d, 0xd4, 0xa8, 0xa6, 0xd9, 0x39, 0xb5, 0x57, 0x53, - 0xae, 0x56, 0x24, 0x72, 0xda, 0x24, 0x48, 0xfc, 0x37, 0x05, 0xa1, 0xd5, - 0x00, 0x74, 0x27, 0xb9, 0x3a, 0x0e, 0x40, 0xcb, 0x13, 0xdf, 0xf0, 0xb6, - 0x0c, 0xbb, 0xfb, 0x38, 0xde, 0x4c, 0xac, 0xd0, 0xea, 0xfe, 0x4a, 0x8f, - 0xde, 0xbf, 0xde, 0x36, 0x53, 0x14, 0xd5, 0x5e, 0x21, 0x23, 0x0d, 0xe6, - 0xac, 0xec, 0xf3, 0x7f, 0x01, 0xf3, 0x4f, 0xae, 0xd4, 0x07, 0x4f, 0x67, - 0x99, 0xc9, 0x49, 0x4e, 0x1f, 0x5d, 0xf7, 0x03, 0x41, 0x76, 0x16, 0x91, - 0xe2, 0xf1, 0xcb, 0xce, 0x57, 0xc3, 0x0f, 0x39, 0x3e, 0x66, 0xec, 0x3e, - 0xa9, 0x08, 0x1f, 0xfd, 0x38, 0x58, 0xcd, 0x47, 0x6c, 0x4d, 0xed, 0xdb, - 0xf4, 0x54, 0xb0, 0x47, 0xcb, 0x05, 0x5c, 0xed, 0x0b, 0xf5, 0xd2, 0x0c, - 0x64, 0xd6, 0x21, 0xfc, 0x41, 0x61, 0xe2, 0x1d, 0xd2, 0xed, 0xe0, 0xe3, - 0x36, 0xc6, 0x14, 0x0e, 0x2f, 0x46, 0xcc, 0x07, 0x81, 0xfd, 0x36, 0xfe, - 0xd0, 0x14, 0xba, 0xe3, 0xc8, 0x4b, 0xdb, 0x22, 0xee, 0xc0, 0x0f, 0xb7, - 0xf9, 0xc0, 0xed, 0xcf, 0x4c, 0x9f, 0x41, 0x08, 0x17, 0xde, 0x46, 0x7b, - 0xa7, 0xdf, 0xf1, 0x21, 0x51, 0xa7, 0xf4, 0x34, 0xa4, 0xa5, 0xbe, 0x09, - 0xe6, 0x32, 0x01, 0xc5, 0xb5, 0xcf, 0xa0, 0x56, 0x3e, 0x1f, 0x98, 0xe7, - 0xbe, 0x4d, 0x19, 0xc6, 0x00, 0x26, 0xa7, 0xb4, 0xd7, 0xb6, 0xf4, 0x30, - 0x20, 0x09, 0x78, 0x81, 0xd6, 0xb8, 0x04, 0x9b, 0x00, 0x37, 0x67, 0x3b, - 0xe4, 0xc4, 0x47, 0xc6, 0xa2, 0x43, 0x69, 0x1b, 0x1a, 0x0f, 0xf0, 0x40, - 0x64, 0x79, 0xc9, 0x00, 0x0a, 0x2e, 0xf8, 0x01, 0xb6, 0x27, 0xf0, 0x46, - 0x2a, 0x82, 0x65, 0x26, 0x9a, 0x19, 0x2b, 0x62, 0x8f, 0xa4, 0xda, 0xee, - 0x23, 0xfa, 0xe4, 0xc5, 0x4c, 0xff, 0x83, 0xdb, 0x8a, 0xbc, 0x27, 0x53, - 0xb0, 0xa9, 0xe9, 0x5e, 0xe9, 0x2b, 0x43, 0x40, 0xe8, 0xfe, 0x41, 0x9a, - 0x51, 0xd7, 0x35, 0xd7, 0xf8, 0x04, 0x1d, 0x09, 0xdf, 0x3b, 0xb7, 0x32, - 0x59, 0xce, 0x57, 0x3f, 0x98, 0x1b, 0x26, 0x18, 0x25, 0x42, 0xfb, 0x7f, - 0x26, 0x1e, 0xa9, 0x03, 0x25, 0x48, 0x09, 0x01, 0xac, 0x3c, 0x55, 0xf6, - 0xc3, 0xdc, 0x61, 0x06, 0x31, 0xb3, 0x2a, 0x41, 0x44, 0xcc, 0xd2, 0xc4, - 0x7f, 0xe0, 0x12, 0x14, 0x2f, 0x5b, 0xba, 0xff, 0xf2, 0x2e, 0x13, 0x27, - 0xd9, 0xe5, 0x08, 0xea, 0xe9, 0xd2, 0x02, 0xe8, 0xcd, 0xff, 0xf9, 0xd9, - 0xfd, 0xf5, 0xb7, 0xd7, 0x46, 0xe5, 0xb4, 0xd1, 0x30, 0x2f, 0x52, 0x31, - 0xb1, 0xb6, 0xfe, 0x08, 0xd5, 0xda, 0x38, 0x38, 0x25, 0xe5, 0x06, 0xd5, - 0xce, 0xea, 0xc0, 0xb5, 0x2e, 0xc1, 0x17, 0x04, 0xf2, 0xb0, 0xfa, 0x27, - 0xc6, 0x2b, 0xdb, 0xd4, 0x04, 0x12, 0xe7, 0x7f, 0x21, 0xfb, 0xd3, 0x18, - 0xc1, 0x25, 0x0d, 0xbb, 0x1e, 0x1c, 0xd7, 0xab, 0xf2, 0xf4, 0xcf, 0xfb, - 0x08, 0xf1, 0x08, 0x45, 0xde, 0xa0, 0xd7, 0xd2, 0x05, 0x2d, 0x45, 0xed, - 0x6a, 0xca, 0xc9, 0xf1, 0x1e, 0xf4, 0x5a, 0xfb, 0xec, 0xfc, 0x16, 0xed, - 0xfa, 0x65, 0x2d, 0xe8, 0xe2, 0x83, 0x0b, 0xf4, 0xf5, 0x24, 0x05, 0xb3, - 0x02, 0xce, 0x41, 0xf1, 0xd2, 0x07, 0x87, 0xc7, 0xa8, 0xf6, 0xfa, 0x22, - 0x12, 0x0b, 0xa9, 0x22, 0xdb, 0x14, 0x49, 0xf2, 0x45, 0xff, 0xe8, 0xfd, - 0xdd, 0x20, 0xf4, 0xf2, 0xad, 0xcd, 0x32, 0x30, 0x0f, 0x26, 0x5f, 0x02, - 0x33, 0xd0, 0xb8, 0x2f, 0xde, 0x36, 0x2f, 0x29, 0x2b, 0x66, 0x2a, 0x81, - 0xaf, 0x28, 0xd9, 0xf3, 0xea, 0x94, 0x22, 0x2b, 0xc8, 0x79, 0x20, 0x08, - 0x02, 0x26, 0x65, 0xc0, 0x1c, 0xf7, 0x3e, 0xef, 0x27, 0x50, 0x8f, 0x56, - 0x73, 0x38, 0xba, 0x9f, 0x3d, 0xd2, 0xf8, 0x4a, 0x21, 0xc4, 0xc5, 0x1f, - 0x53, 0xb9, 0xbf, 0x3a, 0x9a, 0x15, 0x66, 0xbe, 0x81, 0xc9, 0x0c, 0x00, - 0xc1, 0x1a, 0x16, 0xe8, 0x0e, 0xa9, 0x29, 0xc0, 0x36, 0xc7, 0x49, 0xc7, - 0x53, 0x53, 0x51, 0x1c, 0x0d, 0x03, 0xf9, 0x12, 0x26, 0xcd, 0x1b, 0xe8, - 0x41, 0x31, 0xa0, 0x07, 0xc2, 0x3b, 0xe5, 0xc6, 0x1b, 0x10, 0x2b, 0xb6, - 0xf0, 0x0a, 0x00, 0x0b, 0xb1, 0x7c, 0x81, 0xf3, 0xc1, 0x1e, 0x23, 0x08, - 0xda, 0x0b, 0x46, 0x1e, 0x03, 0xc9, 0xd1, 0x22, 0xcf, 0x00, 0xcf, 0xad, - 0xd9, 0xf9, 0x00, 0xfd, 0x5c, 0xe1, 0x28, 0xa6, 0xfe, 0x12, 0xc1, 0x2b, - 0x2f, 0xc4, 0xbe, 0x01, 0x26, 0x01, 0xb1, 0xe3, 0xeb, 0x4a, 0xd1, 0x00, - 0x36, 0x8b, 0xca, 0x9e, 0x2a, 0x18, 0x0d, 0x31, 0xf4, 0xb2, 0x09, 0x6b, - 0x39, 0x7f, 0xf5, 0xae, 0xe8, 0x8e, 0x3b, 0x93, 0x1f, 0x25, 0x25, 0x1d, - 0x2d, 0x34, 0x34, 0xff, 0xdf, 0x0a, 0x06, 0x1e, 0xc8, 0xe0, 0xa9, 0x27, - 0xda, 0xb3, 0xbe, 0x3a, 0xd5, 0xeb, 0x68, 0xcb, 0x1a, 0x24, 0xd2, 0x1a, - 0x0f, 0x35, 0x11, 0x17, 0xc4, 0x19, 0xc3, 0x28, 0x2d, 0x42, 0x00, 0x3c, - 0x47, 0xcd, 0x35, 0xc1, 0xf4, 0xc9, 0xf4, 0x03, 0xd5, 0xc8, 0x64, 0xd1, - 0xc5, 0x2b, 0xee, 0xc9, 0x7f, 0xb2, 0xd4, 0xf9, 0xcd, 0xe6, 0xbd, 0x11, - 0x86, 0x90, 0xb4, 0x11, 0xe2, 0x5a, 0xeb, 0x6e, 0x04, 0x4e, 0x21, 0xcb, - 0x7e, 0x37, 0xee, 0xf6, 0x9f, 0x9b, 0xae, 0xc3, 0x3b, 0xd0, 0x44, 0x49, - 0xfb, 0x28, 0xbf, 0x01, 0xe8, 0xe5, 0xc1, 0x35, 0x5b, 0xdc, 0x0c, 0x67, - 0x34, 0x6c, 0xe0, 0x17, 0x8a, 0x45, 0x2b, 0xb8, 0x24, 0xb6, 0x5a, 0x2e, - 0xf0, 0x54, 0x49, 0xf7, 0xe3, 0xf7, 0xd7, 0xe3, 0x10, 0x7f, 0xfb, 0x05, - 0x22, 0xca, 0xed, 0xfe, 0xf4, 0x02, 0xeb, 0xfa, 0x5f, 0x16, 0x12, 0xf4, - 0x30, 0xbb, 0xef, 0x33, 0xdc, 0xec, 0x06, 0x0f, 0x1f, 0xfc, 0x2d, 0xb9, - 0x41, 0x20, 0x06, 0xf4, 0x0b, 0x21, 0x03, 0x06, 0x0b, 0x09, 0xe1, 0xf1, - 0xa5, 0xbc, 0x2f, 0x03, 0xf1, 0xf7, 0xba, 0x07, 0x17, 0x02, 0xe1, 0x09, - 0xcd, 0x11, 0x2c, 0x03, 0x09, 0xf0, 0xfa, 0x0f, 0xc7, 0x21, 0x22, 0x33, - 0xe9, 0x59, 0x0b, 0xd8, 0xe7, 0x43, 0x99, 0xf0, 0x00, 0xff, 0x9e, 0xff, - 0x54, 0xa5, 0xda, 0x6a, 0xb0, 0x93, 0xf3, 0x62, 0xe9, 0xe1, 0xaf, 0x11, - 0x14, 0x49, 0xf4, 0xb0, 0x50, 0x59, 0x58, 0x34, 0xc0, 0xfb, 0x37, 0x53, - 0xe4, 0x07, 0xd9, 0xf9, 0xde, 0x26, 0x00, 0x0f, 0x55, 0xc1, 0x0c, 0xbd, - 0x1d, 0xcc, 0x33, 0x17, 0x19, 0x88, 0x0e, 0x81, 0xd5, 0x01, 0xff, 0xcd, - 0xea, 0x50, 0x9e, 0xb9, 0x46, 0xf1, 0xd1, 0xdf, 0x24, 0x9f, 0xc4, 0x94, - 0xd6, 0xfd, 0x83, 0xfe, 0xe1, 0x59, 0x68, 0xb1, 0x5e, 0x57, 0x6a, 0x92, - 0x98, 0x04, 0x22, 0xfe, 0x07, 0x4c, 0x69, 0xf7, 0x58, 0x7f, 0x38, 0xcc, - 0xf9, 0x2b, 0x59, 0x7e, 0x1d, 0xf5, 0xfe, 0x2a, 0x02, 0x2f, 0x17, 0x4e, - 0x27, 0xe4, 0xb8, 0x38, 0x12, 0x9d, 0x10, 0x07, 0x15, 0x1a, 0x06, 0xe0, - 0x34, 0x81, 0xf9, 0x36, 0x5e, 0x3a, 0xdb, 0xee, 0x44, 0xb5, 0x14, 0xf6, - 0xde, 0x46, 0x28, 0xdf, 0x45, 0x31, 0xb0, 0xf1, 0xc0, 0xd5, 0xc9, 0x42, - 0xcc, 0x60, 0x30, 0x0b, 0xef, 0x48, 0x33, 0xf7, 0xe4, 0x7d, 0x06, 0x47, - 0xe2, 0x81, 0x1d, 0xd1, 0x17, 0xe2, 0xba, 0x0a, 0x38, 0x03, 0x18, 0x2c, - 0x64, 0x2b, 0x0a, 0x11, 0x56, 0x1c, 0x58, 0xce, 0x5a, 0xed, 0xc3, 0xc0, - 0x06, 0x03, 0xeb, 0x1c, 0xd0, 0xb7, 0x13, 0x03, 0x0f, 0x15, 0x04, 0xdd, - 0x18, 0x2a, 0x0f, 0xdc, 0xd9, 0x6b, 0xe3, 0xdf, 0xfe, 0xf8, 0x7f, 0xcd, - 0xc1, 0x6d, 0xfd, 0x21, 0x24, 0xfe, 0xe1, 0xb7, 0xe4, 0x14, 0x06, 0x2d, - 0x07, 0x01, 0x02, 0xbd, 0x07, 0x1c, 0x07, 0xcb, 0x08, 0xf1, 0xe6, 0xee, - 0xea, 0xeb, 0xcf, 0x24, 0x3b, 0x46, 0x01, 0xe6, 0x13, 0x08, 0x3a, 0x37, - 0x10, 0x40, 0x11, 0xd8, 0xa8, 0x33, 0x34, 0x52, 0x1a, 0x01, 0x1b, 0xb7, - 0x6d, 0x88, 0x12, 0x87, 0xfa, 0x02, 0xd4, 0x37, 0x9a, 0x83, 0x11, 0x14, - 0xc6, 0xb6, 0x1b, 0x7a, 0x6e, 0xae, 0x1b, 0x05, 0x0f, 0xd4, 0xf9, 0x20, - 0x81, 0x64, 0x3d, 0x07, 0x8b, 0xee, 0x2e, 0x18, 0xfc, 0xe7, 0xd6, 0xef, - 0x69, 0xd7, 0x32, 0xe1, 0xd8, 0xd7, 0x66, 0xf8, 0x32, 0x9d, 0x26, 0x42, - 0xde, 0xf3, 0x7f, 0xd6, 0x1b, 0xd7, 0xc0, 0x18, 0x20, 0xb3, 0x4f, 0x49, - 0x4f, 0x75, 0x07, 0xc1, 0xd0, 0xcd, 0x07, 0xa8, 0x7f, 0xa8, 0xdc, 0x1c, - 0x12, 0x16, 0xa4, 0x00, 0x55, 0x0e, 0xa8, 0x11, 0x03, 0xce, 0xda, 0xce, - 0xeb, 0x2d, 0xb9, 0xdf, 0xc3, 0xbd, 0xa2, 0xb1, 0x27, 0xff, 0x23, 0x4e, - 0x2f, 0xe9, 0x00, 0xb2, 0xf3, 0xf6, 0x04, 0xa3, 0xb8, 0x9a, 0x37, 0xaf, - 0x23, 0xf4, 0xa8, 0xeb, 0xb6, 0x4c, 0x6f, 0xae, 0x32, 0x9b, 0xa3, 0x1d, - 0x3f, 0xbb, 0x8b, 0xbb, 0x19, 0x50, 0x7d, 0x11, 0xb4, 0xeb, 0xcc, 0x01, - 0x01, 0xf7, 0xf4, 0x00, 0xef, 0x2e, 0xfc, 0x1d, 0xd5, 0xe1, 0x19, 0x16, - 0xdc, 0xfd, 0xf8, 0x12, 0xfc, 0x0b, 0xdc, 0xf5, 0x3f, 0xdf, 0x31, 0x1b, - 0x1d, 0xed, 0x16, 0xeb, 0xdd, 0x4d, 0xa6, 0x3f, 0xf5, 0xf4, 0xf2, 0xe9, - 0xd7, 0xfc, 0xc5, 0x1e, 0xe4, 0xc8, 0xf3, 0x90, 0x11, 0x26, 0x05, 0x28, - 0xd4, 0x7f, 0xbe, 0x40, 0xea, 0x4e, 0xd7, 0x8d, 0x1c, 0x2d, 0xd2, 0xdc, - 0x40, 0xe0, 0xdf, 0xee, 0x4c, 0x1f, 0xe7, 0xa6, 0x1e, 0x1e, 0xf1, 0x07, - 0xe0, 0x05, 0x10, 0x04, 0x71, 0xe1, 0xe8, 0xfd, 0x15, 0x1b, 0x02, 0x6d, - 0xfa, 0xbe, 0x22, 0x66, 0x1f, 0xe8, 0x2a, 0x00, 0x20, 0xed, 0xcd, 0xe0, - 0xfc, 0xf2, 0xe2, 0x16, 0xd8, 0x14, 0x04, 0xc9, 0x81, 0x12, 0x14, 0x32, - 0xf0, 0x2d, 0x00, 0xbb, 0x40, 0x22, 0xff, 0xe8, 0xf2, 0xe4, 0x1c, 0x2a, - 0xb7, 0xfd, 0x51, 0xf0, 0xd5, 0xee, 0xdf, 0x51, 0xb3, 0x1c, 0x4a, 0x05, - 0x0c, 0x1e, 0x16, 0x26, 0xc2, 0x08, 0x81, 0x1a, 0x24, 0x41, 0x42, 0x25, - 0xf9, 0x23, 0xd4, 0xd3, 0xe8, 0xac, 0x0b, 0xfc, 0x23, 0xe1, 0xb6, 0x9c, - 0x1c, 0x06, 0xba, 0x35, 0xf0, 0xdd, 0x06, 0x63, 0xc4, 0x24, 0xa8, 0xc3, - 0x05, 0xbd, 0xd9, 0xc3, 0x65, 0x2c, 0x2a, 0xd1, 0xaa, 0x2e, 0x1e, 0xef, - 0xa0, 0xca, 0xf7, 0xf9, 0xd6, 0x0f, 0xe5, 0x17, 0x33, 0xf3, 0x7f, 0x17, - 0xb3, 0x49, 0x92, 0xfd, 0x02, 0x03, 0x20, 0xe5, 0xaf, 0x11, 0x21, 0xcb, - 0xb8, 0xda, 0x1f, 0x0a, 0x0d, 0x03, 0xd4, 0xd9, 0x20, 0x3b, 0xcc, 0x78, - 0x0e, 0x02, 0xeb, 0xbb, 0x4f, 0xcc, 0xf9, 0xcf, 0xe9, 0xff, 0xe4, 0xde, - 0xb5, 0x0c, 0x88, 0xc1, 0xd0, 0x54, 0x95, 0x8a, 0x39, 0x07, 0x0e, 0xd4, - 0x2a, 0x3c, 0x13, 0x42, 0xdf, 0x1b, 0xc9, 0x30, 0x2c, 0x19, 0x9e, 0x5f, - 0xdd, 0xff, 0x04, 0x62, 0x17, 0x7f, 0xe7, 0xab, 0x07, 0xdb, 0x5a, 0xb8, - 0x2f, 0x41, 0x00, 0x1a, 0xee, 0xdc, 0xeb, 0xf4, 0xe3, 0xe0, 0x33, 0x10, - 0xe0, 0xcb, 0xe1, 0x00, 0xd7, 0xdd, 0xbf, 0x24, 0x46, 0xe9, 0xfb, 0xd0, - 0x19, 0xeb, 0xe8, 0xeb, 0x2a, 0xcd, 0xa5, 0x0d, 0xda, 0x01, 0xc3, 0x41, - 0x68, 0x08, 0xf3, 0x1a, 0xf4, 0xc4, 0x0f, 0xf8, 0x30, 0xe2, 0x2f, 0xd5, - 0x07, 0xf7, 0x20, 0xfe, 0x4b, 0xdb, 0xe3, 0x33, 0xdf, 0x81, 0xc8, 0xec, - 0xac, 0x51, 0xf6, 0x3c, 0x2d, 0xdb, 0xf1, 0x22, 0xda, 0x05, 0xd3, 0x52, - 0xba, 0x52, 0xc7, 0xf8, 0x35, 0x33, 0x0b, 0xc7, 0x07, 0xfc, 0xa8, 0xab, - 0xdd, 0x0a, 0x2a, 0xee, 0xd3, 0xf4, 0xce, 0xc5, 0xbc, 0x47, 0xdb, 0xbc, - 0x37, 0x3d, 0xbe, 0xe9, 0x0e, 0x1b, 0x2b, 0x07, 0x0c, 0xe2, 0xbb, 0xce, - 0x4c, 0x50, 0x49, 0x0b, 0xc4, 0x13, 0xbc, 0xdc, 0x09, 0xf4, 0x14, 0x2b, - 0xd7, 0xfd, 0xf0, 0xee, 0x3d, 0x0d, 0x97, 0xc5, 0x86, 0xb8, 0x30, 0xbb, - 0xa5, 0x70, 0xb8, 0x0f, 0xdb, 0xf8, 0x9b, 0x0e, 0xd2, 0x21, 0x56, 0xf8, - 0xd6, 0xef, 0x0e, 0xdc, 0xbc, 0xf7, 0xbf, 0xd7, 0xfc, 0x3a, 0xda, 0x21, - 0x8e, 0xf6, 0x73, 0xf4, 0x61, 0x98, 0xc8, 0xf2, 0x2d, 0xe6, 0x3e, 0xea, - 0x02, 0x10, 0x21, 0x7f, 0xf3, 0xe8, 0x1a, 0xb0, 0xe8, 0xf4, 0xf2, 0xfc, - 0x12, 0xc6, 0xc4, 0xd0, 0x02, 0x04, 0x0b, 0xe7, 0x10, 0xf7, 0xe9, 0xea, - 0x03, 0x2d, 0xd0, 0xfa, 0x00, 0x02, 0xd9, 0xfa, 0xef, 0xed, 0x0b, 0xfd, - 0x00, 0x1e, 0xe6, 0xd7, 0xc3, 0x31, 0x02, 0xf8, 0x1e, 0x23, 0xb2, 0xe2, - 0xfd, 0xdc, 0xf4, 0x0f, 0x02, 0x3e, 0xbd, 0x12, 0xda, 0xf5, 0x0c, 0xc4, - 0x28, 0xc4, 0x10, 0x1f, 0xd8, 0x18, 0xd3, 0xf7, 0x13, 0xc7, 0xf7, 0x81, - 0xf4, 0x0c, 0x24, 0xda, 0x23, 0x09, 0xdf, 0x10, 0xf1, 0x92, 0x1e, 0x04, - 0x34, 0xf5, 0xbf, 0xcd, 0xfd, 0x14, 0xf7, 0x7f, 0xe2, 0xf2, 0xc8, 0x10, - 0x85, 0x07, 0xe9, 0x0b, 0x02, 0x12, 0x00, 0xae, 0xe7, 0x08, 0xe0, 0xeb, - 0xb4, 0xb4, 0xe0, 0x2c, 0xe5, 0x04, 0x1f, 0x34, 0xca, 0xe1, 0x2d, 0x0d, - 0x74, 0xe5, 0xe2, 0xfc, 0x0d, 0xd7, 0x08, 0x10, 0xf3, 0xf3, 0x18, 0x1c, - 0x22, 0x51, 0xe5, 0xda, 0xfa, 0x94, 0xd0, 0xdb, 0x46, 0xaa, 0x09, 0x45, - 0x3d, 0xd0, 0x93, 0x55, 0x3f, 0xec, 0x7f, 0xac, 0xe4, 0xd8, 0x35, 0xed, - 0xd5, 0xc3, 0x2e, 0x1f, 0xd2, 0xd9, 0xde, 0xcb, 0x33, 0x35, 0xc6, 0x8c, - 0x4f, 0x09, 0x46, 0xc2, 0x1b, 0xfa, 0x6e, 0xce, 0x55, 0x94, 0xcd, 0x0f, - 0x52, 0xcc, 0x0d, 0xe9, 0x99, 0x0b, 0xd7, 0x3c, 0xfe, 0x2b, 0x0c, 0xe3, - 0x1d, 0x9f, 0x4a, 0x1e, 0xef, 0x66, 0x27, 0x25, 0x4b, 0x16, 0x14, 0x36, - 0xda, 0x41, 0xeb, 0xed, 0x15, 0x7f, 0x26, 0xeb, 0x1a, 0xe5, 0x2d, 0xea, - 0xe3, 0x25, 0x11, 0xf6, 0x06, 0x27, 0x3f, 0x01, 0xe7, 0xcc, 0x26, 0x39, - 0xdf, 0x28, 0xd2, 0x70, 0x22, 0x0e, 0x23, 0x1c, 0x4c, 0x19, 0xf1, 0x07, - 0x39, 0x0d, 0x0d, 0x27, 0xdb, 0xe0, 0xec, 0xf4, 0x84, 0x35, 0x26, 0xdc, - 0x32, 0x17, 0xa6, 0xed, 0x12, 0x2f, 0xd1, 0xe5, 0x1e, 0x22, 0xde, 0xe3, - 0xf8, 0x00, 0x02, 0xe7, 0xea, 0x8d, 0x08, 0xd4, 0x0b, 0xd7, 0xb6, 0x43, - 0xf0, 0xf6, 0x6d, 0x52, 0x36, 0x89, 0xf9, 0x11, 0x37, 0xcb, 0xaa, 0x0a, - 0x3f, 0xf3, 0x44, 0x43, 0xcc, 0xd3, 0xef, 0x81, 0x38, 0x0b, 0x02, 0x15, - 0xf9, 0x01, 0x2a, 0xd5, 0xb3, 0xcd, 0xf2, 0xf2, 0x11, 0xad, 0x2e, 0xcc, - 0xe3, 0xd6, 0x0f, 0x2d, 0x1e, 0x9a, 0x24, 0xc3, 0x65, 0xcb, 0xcb, 0x1f, - 0xa5, 0xf6, 0x3d, 0x2b, 0x29, 0xef, 0x8c, 0x08, 0xa4, 0xa4, 0x4a, 0xbf, - 0x07, 0x79, 0xa8, 0xf4, 0x10, 0xca, 0xa3, 0x40, 0x4c, 0x04, 0xd5, 0xef, - 0x1a, 0xed, 0xbc, 0x14, 0x45, 0xee, 0x94, 0x50, 0x20, 0xe1, 0xd8, 0x69, - 0x7b, 0x34, 0xda, 0x08, 0xe3, 0xa1, 0x19, 0xde, 0x65, 0xa5, 0xd4, 0xf0, - 0x3a, 0xf8, 0xeb, 0xdb, 0x35, 0xd8, 0x06, 0x07, 0x7f, 0xcf, 0x0e, 0x18, - 0xd7, 0xf7, 0xaf, 0xb6, 0xde, 0x79, 0x9c, 0x65, 0x3b, 0x49, 0xf1, 0x35, - 0x41, 0xcd, 0x09, 0xd8, 0xd3, 0x1d, 0xe5, 0xe5, 0x15, 0x02, 0xf5, 0xe0, - 0x98, 0xad, 0x0b, 0x3c, 0x11, 0xe8, 0xdd, 0x7f, 0xcf, 0x57, 0xf7, 0xe0, - 0x0e, 0x17, 0x48, 0x4b, 0xb6, 0x21, 0x28, 0xd4, 0x23, 0x25, 0x47, 0xd0, - 0x63, 0xdf, 0xe5, 0xfa, 0xe2, 0xf1, 0x16, 0xcd, 0xd0, 0x47, 0x1d, 0x23, - 0x15, 0x22, 0xd2, 0xc9, 0xf3, 0xbb, 0x0b, 0xbc, 0xfa, 0xa5, 0xde, 0x34, - 0x25, 0x5b, 0x3e, 0x51, 0x0f, 0x2d, 0x25, 0x28, 0xeb, 0x73, 0x35, 0xd9, - 0x0e, 0xbd, 0x3c, 0x2e, 0x7c, 0x28, 0x24, 0x0d, 0x0a, 0x4f, 0x04, 0x10, - 0x8b, 0xcb, 0xf1, 0x2f, 0xfd, 0x27, 0xce, 0x28, 0xd6, 0xe2, 0x13, 0x29, - 0x72, 0x16, 0x54, 0xa7, 0x12, 0x87, 0xe4, 0x17, 0x55, 0x2d, 0xdd, 0xcc, - 0x04, 0x81, 0x65, 0x3c, 0xdb, 0xb7, 0xc9, 0x2d, 0x43, 0xc1, 0x1f, 0xbf, - 0xee, 0xac, 0x40, 0xc7, 0x1e, 0xe7, 0x03, 0x02, 0xc7, 0x54, 0xfc, 0xde, - 0x3f, 0xc9, 0x22, 0x1f, 0x3e, 0xd3, 0xee, 0x15, 0x3d, 0xd0, 0xd2, 0xcd, - 0x0e, 0xce, 0xe1, 0x3f, 0x14, 0xfc, 0xe8, 0x1e, 0xf4, 0x2f, 0xcf, 0x31, - 0xab, 0x48, 0xe5, 0xf7, 0x1e, 0x15, 0xff, 0x23, 0x39, 0xfa, 0x03, 0xd0, - 0x41, 0xd2, 0x34, 0x08, 0x13, 0x53, 0x23, 0xd4, 0x3a, 0x0f, 0x3d, 0x0c, - 0xd6, 0x33, 0xf0, 0xbc, 0x20, 0xde, 0xce, 0x7f, 0x45, 0x58, 0xc5, 0xec, - 0x33, 0xa3, 0x41, 0xbb, 0x35, 0x39, 0xc5, 0xce, 0x24, 0xcd, 0xe9, 0xc3, - 0xfe, 0x06, 0x18, 0x31, 0xe8, 0x00, 0x26, 0x2d, 0x3e, 0x0e, 0x08, 0x7f, - 0x00, 0x02, 0x1f, 0x1c, 0xc1, 0xff, 0x9c, 0xd4, 0x01, 0xe7, 0xdb, 0x1a, - 0x12, 0xb8, 0xe5, 0xd8, 0xb6, 0xb8, 0xe3, 0xaf, 0xeb, 0x97, 0xfd, 0xcd, - 0xea, 0x65, 0x1f, 0xd4, 0xe6, 0x10, 0xe6, 0xe6, 0x15, 0xc6, 0x29, 0x1f, - 0x0b, 0x45, 0x07, 0x09, 0x18, 0x12, 0xf3, 0x22, 0xf1, 0x63, 0xd8, 0xdc, - 0x37, 0xf1, 0xe9, 0xb9, 0x0a, 0xe1, 0x19, 0xea, 0x35, 0x0f, 0x2b, 0xee, - 0xe5, 0xff, 0x14, 0x7f, 0xe4, 0xf2, 0xd3, 0x4b, 0x38, 0x0c, 0x3f, 0xc4, - 0x18, 0x20, 0xf0, 0xee, 0x24, 0xdb, 0x40, 0x19, 0xe0, 0x06, 0xf7, 0x25, - 0xd3, 0xe8, 0x1e, 0x27, 0xdf, 0x01, 0xbf, 0xd9, 0x16, 0x05, 0x16, 0xea, - 0xc1, 0xe7, 0xd8, 0x23, 0xf1, 0x00, 0xc8, 0xe9, 0x31, 0x13, 0x1a, 0xf6, - 0xf8, 0x7f, 0xf6, 0xe1, 0x16, 0xd8, 0x03, 0xf5, 0xf8, 0x13, 0x22, 0xf3, - 0x60, 0x33, 0x14, 0xf6, 0xe8, 0xf5, 0x32, 0x49, 0x0a, 0xe3, 0x05, 0x47, - 0x1e, 0x04, 0xfd, 0x0a, 0x4e, 0xf6, 0xe6, 0xe8, 0x21, 0x0c, 0x09, 0xeb, - 0x16, 0xbd, 0x25, 0xc5, 0xaf, 0x1e, 0x25, 0x00, 0xf2, 0x08, 0xc5, 0x10, - 0x4e, 0xf1, 0x16, 0x23, 0xc2, 0xf1, 0x1b, 0xf9, 0x19, 0xdd, 0x00, 0x0c, - 0x0d, 0xf0, 0x23, 0xea, 0xd0, 0x44, 0x20, 0x9b, 0xe6, 0xf1, 0x41, 0xaa, - 0x16, 0x4d, 0x22, 0xfc, 0xd1, 0x47, 0x1f, 0xa1, 0xf0, 0x81, 0x2a, 0x1d, - 0xd8, 0xf0, 0xab, 0x1d, 0xe7, 0xe6, 0x13, 0x30, 0x25, 0x09, 0xf0, 0xf6, - 0x2a, 0x01, 0xe1, 0x40, 0xf7, 0xb5, 0x4d, 0x2f, 0xb2, 0xa3, 0x17, 0x39, - 0x22, 0x40, 0xcb, 0x31, 0x41, 0xe7, 0x4c, 0x09, 0x16, 0x1a, 0xd2, 0x17, - 0xb8, 0x02, 0x00, 0xf5, 0x1a, 0xb9, 0x5d, 0xdb, 0x07, 0xdd, 0x08, 0xf5, - 0xbf, 0xdc, 0x0e, 0xec, 0x02, 0xb9, 0xd9, 0xda, 0x54, 0xda, 0xdb, 0x2d, - 0x27, 0xbe, 0xd2, 0x0d, 0xcf, 0xe4, 0xa7, 0xea, 0xd5, 0xe7, 0x0d, 0xa7, - 0x2c, 0x00, 0xb5, 0x2a, 0xc6, 0xa6, 0x0c, 0x99, 0x53, 0x81, 0x16, 0x28, - 0xbf, 0xff, 0x7b, 0x1e, 0x0e, 0xee, 0xa5, 0x1e, 0xdd, 0xd6, 0x3d, 0x07, - 0xc3, 0xd4, 0xdd, 0x28, 0x2e, 0x30, 0xfb, 0xd7, 0x11, 0x45, 0xe7, 0x0b, - 0x3c, 0xd8, 0xaa, 0xb3, 0x3c, 0x43, 0xc8, 0x03, 0xd6, 0xff, 0x0c, 0xbb, - 0x7f, 0x01, 0x00, 0x3e, 0x32, 0xe1, 0x0f, 0x5b, 0x36, 0xf1, 0x33, 0x40, - 0x65, 0xab, 0xdd, 0xd8, 0x08, 0x1f, 0x23, 0x00, 0x5a, 0x0c, 0x2b, 0xb4, - 0xf0, 0xd2, 0xf6, 0x04, 0x1e, 0xec, 0x33, 0x4d, 0x07, 0x39, 0xcd, 0xb9, - 0xff, 0x1a, 0x28, 0xad, 0xf5, 0xe2, 0x44, 0x1c, 0xe0, 0xf1, 0x59, 0x7a, - 0x03, 0xb7, 0x1f, 0xe1, 0x18, 0xee, 0x03, 0x99, 0x28, 0x05, 0xca, 0x9a, - 0xea, 0xb9, 0x35, 0x19, 0x01, 0xbf, 0xd6, 0x38, 0x04, 0xef, 0xe7, 0x08, - 0x3d, 0x40, 0x99, 0xda, 0xf9, 0xee, 0xa8, 0x06, 0xd1, 0x25, 0xa0, 0xdf, - 0x1b, 0x0c, 0x08, 0xfc, 0x26, 0xc4, 0x62, 0x33, 0x07, 0x81, 0x0f, 0xe9, - 0xf7, 0x4b, 0xe4, 0xcd, 0xed, 0xd5, 0xec, 0x21, 0x90, 0x04, 0xa9, 0xfa, - 0xd5, 0x20, 0x5a, 0xe9, 0x11, 0xc8, 0xe8, 0xde, 0xae, 0x52, 0xe5, 0xb1, - 0xfc, 0xd4, 0xf0, 0xe1, 0xc3, 0x60, 0x52, 0xfe, 0xd2, 0xcb, 0x18, 0x25, - 0xd7, 0x2c, 0xf4, 0x39, 0x08, 0x30, 0xc8, 0x7f, 0xe2, 0x37, 0xf5, 0x0d, - 0x2c, 0xe4, 0xa4, 0xba, 0x3a, 0x48, 0xbb, 0x3a, 0x02, 0x06, 0x55, 0x39, - 0xe6, 0x31, 0x18, 0xd2, 0x24, 0x21, 0x0b, 0x0b, 0x33, 0x5e, 0xfb, 0x05, - 0xe7, 0x3e, 0xc5, 0x67, 0xc3, 0x2c, 0xff, 0xaa, 0xdb, 0xbc, 0x5b, 0xf2, - 0x43, 0x0e, 0x13, 0xcf, 0x55, 0xf3, 0xe3, 0xdb, 0x17, 0xf7, 0x7f, 0xea, - 0xc7, 0x1a, 0xe3, 0xe8, 0xe5, 0xcd, 0x2f, 0xcf, 0xe0, 0x08, 0xd1, 0xb1, - 0xed, 0xe7, 0x07, 0xcb, 0xb9, 0x09, 0xb0, 0xf1, 0xfc, 0x2f, 0x24, 0x50, - 0xf7, 0xab, 0x17, 0xea, 0x6d, 0xea, 0xeb, 0xee, 0xca, 0x3a, 0x3a, 0x45, - 0x2e, 0x30, 0x0c, 0x37, 0x27, 0x0f, 0xe3, 0x05, 0x2b, 0xe6, 0xd9, 0xe7, - 0x94, 0xae, 0x92, 0x3e, 0x6b, 0x04, 0x03, 0x28, 0xc4, 0x9e, 0x6e, 0x1c, - 0xfe, 0xd7, 0xeb, 0x3e, 0x7f, 0xa8, 0xe7, 0x37, 0xfd, 0x34, 0xc0, 0x76, - 0x22, 0xca, 0xa1, 0xf6, 0x10, 0x51, 0xb5, 0xd0, 0x3a, 0x23, 0xf3, 0xb6, - 0x29, 0xda, 0xd7, 0xf7, 0xf7, 0xb0, 0xd1, 0xcf, 0x2e, 0x8d, 0x6c, 0x75, - 0x3b, 0xb1, 0xa8, 0xe3, 0x27, 0xe5, 0x12, 0x04, 0xb7, 0xb1, 0x53, 0xe6, - 0x2b, 0x01, 0x1b, 0xca, 0xf2, 0xa1, 0x41, 0xfb, 0xf8, 0x58, 0x01, 0xc3, - 0x41, 0xec, 0x33, 0x3f, 0x19, 0xb1, 0xc1, 0x2b, 0x3c, 0x5d, 0xb5, 0xf7, - 0x55, 0xb3, 0x1c, 0x4f, 0x1c, 0x44, 0x95, 0xfe, 0x48, 0xc0, 0xdf, 0x9c, - 0xb9, 0x67, 0xd7, 0x7f, 0xd9, 0xb7, 0x0b, 0xf2, 0x45, 0x22, 0xdc, 0x14, - 0xda, 0xcf, 0xd0, 0xdb, 0xc6, 0xbb, 0x93, 0x16, 0x1d, 0x34, 0xc4, 0x70, - 0x31, 0xd1, 0xb0, 0xc8, 0x52, 0xde, 0xe7, 0xa4, 0x68, 0xf2, 0xf5, 0x08, - 0x6c, 0xeb, 0x33, 0x70, 0x57, 0x64, 0xea, 0xd7, 0x19, 0xc0, 0xf2, 0xfe, - 0x0d, 0xe0, 0x1f, 0x41, 0x48, 0x48, 0x37, 0xf8, 0xba, 0xcf, 0xfb, 0x7f, - 0xc4, 0xc6, 0x54, 0xca, 0x20, 0xb3, 0x0d, 0xdf, 0x4c, 0x2b, 0xe6, 0xcf, - 0xe3, 0x25, 0x36, 0xa9, 0x58, 0x2a, 0x51, 0x5f, 0x34, 0x2b, 0x32, 0x5f, - 0xbb, 0x4a, 0xea, 0x98, 0x17, 0xe2, 0x03, 0x4e, 0x35, 0x0a, 0x26, 0xf9, - 0xc4, 0xe5, 0x38, 0xc3, 0x3e, 0xa0, 0x37, 0x2f, 0xbb, 0x50, 0xf0, 0xb3, - 0xe0, 0xbe, 0x25, 0x34, 0xca, 0x11, 0x9d, 0x5c, 0xd1, 0x02, 0x11, 0xd2, - 0xf4, 0xac, 0xf6, 0xc9, 0x9a, 0x0d, 0xbe, 0x81, 0x01, 0xa7, 0x00, 0xe4, - 0xb8, 0x12, 0x1d, 0xe4, 0x06, 0x1b, 0xdb, 0xf7, 0x63, 0xe1, 0x2b, 0x13, - 0xc3, 0x00, 0x23, 0x0c, 0xdd, 0x0d, 0xde, 0x35, 0x13, 0x99, 0xdc, 0x31, - 0xe5, 0x14, 0xb6, 0x16, 0x3a, 0xc3, 0xfa, 0x61, 0xcb, 0x58, 0xd6, 0x4f, - 0x44, 0xde, 0x11, 0x1a, 0x4a, 0x14, 0x03, 0x6f, 0x01, 0x17, 0xf2, 0x09, - 0xc0, 0xbb, 0xe9, 0x0f, 0x29, 0xf6, 0xfe, 0x03, 0xb7, 0xbb, 0xd4, 0xf2, - 0x0c, 0xb9, 0x5c, 0x26, 0xd7, 0x91, 0xf9, 0xea, 0x25, 0x81, 0x3c, 0xcc, - 0x35, 0xdf, 0x2f, 0x5d, 0xda, 0xea, 0xf8, 0x37, 0x11, 0xd9, 0xff, 0x42, - 0x14, 0xb2, 0x49, 0xf5, 0x32, 0x04, 0x0c, 0xd0, 0x13, 0xde, 0x1b, 0x0a, - 0x29, 0x8d, 0xc3, 0x34, 0xf2, 0x15, 0xe0, 0xea, 0xed, 0xd9, 0xbf, 0x61, - 0xcd, 0xde, 0xca, 0x5c, 0xcf, 0xd2, 0xe5, 0xd5, 0x03, 0x18, 0xf6, 0x9f, - 0x17, 0x30, 0xd4, 0x2e, 0xc2, 0xbd, 0x30, 0x21, 0xfc, 0x81, 0xe5, 0x09, - 0xe5, 0xdb, 0xf1, 0xd0, 0x41, 0x17, 0xd8, 0xfa, 0x02, 0x04, 0x67, 0x0e, - 0xf7, 0xfb, 0xfd, 0x0f, 0x0e, 0x30, 0xe3, 0xf6, 0x0e, 0xac, 0x09, 0x2d, - 0xc0, 0xce, 0x16, 0x4e, 0x1c, 0x0f, 0x08, 0xe0, 0xd0, 0xf8, 0x7f, 0xb5, - 0x35, 0xfe, 0xe5, 0x5f, 0x14, 0x47, 0xb4, 0xf4, 0xc5, 0x16, 0x37, 0x58, - 0x09, 0xbb, 0x8c, 0xfd, 0x07, 0xf8, 0x4c, 0x37, 0xfc, 0xd8, 0x1a, 0xfb, - 0xb9, 0x9b, 0x04, 0xcd, 0x4e, 0xd1, 0xc2, 0xbf, 0xee, 0xaf, 0xfc, 0x45, - 0xff, 0xd7, 0xc2, 0xf6, 0x02, 0xe7, 0x5f, 0xe2, 0xda, 0xbc, 0x10, 0x48, - 0x19, 0x38, 0x25, 0xc4, 0x36, 0xbe, 0x0e, 0xfb, 0xff, 0x5b, 0x36, 0x27, - 0x37, 0x94, 0xed, 0x27, 0x4d, 0x07, 0xf6, 0x5a, 0x37, 0x08, 0xd1, 0x38, - 0xfa, 0x81, 0x1c, 0x04, 0xe6, 0xf5, 0x04, 0xf2, 0xe3, 0xa9, 0xfd, 0x03, - 0x2b, 0xfe, 0xeb, 0xec, 0x27, 0xb1, 0x1b, 0x3a, 0x0d, 0xfd, 0x45, 0xf6, - 0xce, 0xab, 0x3e, 0xde, 0xf4, 0xd9, 0xbe, 0x41, 0xde, 0xc5, 0xf0, 0x2c, - 0x20, 0xf0, 0x0d, 0xce, 0x21, 0xfa, 0xf7, 0xba, 0xfb, 0x20, 0x92, 0xc4, - 0x24, 0xf6, 0xcc, 0x3f, 0x02, 0xcd, 0x12, 0x3f, 0x36, 0xe0, 0xc5, 0xca, - 0xd4, 0xc0, 0xf2, 0xcb, 0xfc, 0xfd, 0xe1, 0x1f, 0x37, 0xcd, 0x39, 0x7f, - 0xb9, 0x56, 0x36, 0xd1, 0x1f, 0x3d, 0x04, 0x4a, 0x2a, 0x12, 0xdf, 0x37, - 0xaf, 0xcd, 0xb9, 0x01, 0xc8, 0x48, 0xaa, 0x2d, 0x65, 0x5f, 0xeb, 0xd5, - 0xcd, 0x73, 0x24, 0xd4, 0x67, 0xa8, 0x54, 0x45, 0x2b, 0x76, 0xc2, 0x1f, - 0xf4, 0xec, 0xef, 0x46, 0x25, 0x47, 0x52, 0x91, 0xde, 0xfb, 0xd8, 0xbe, - 0x8f, 0xfc, 0xfe, 0x2a, 0x2e, 0x23, 0x42, 0x25, 0x19, 0x98, 0x33, 0x7f, - 0xc2, 0xe6, 0x04, 0x5a, 0x00, 0x41, 0x03, 0xf3, 0xc9, 0xe4, 0x90, 0x32, - 0xec, 0x74, 0xe6, 0x0a, 0x40, 0xe9, 0x22, 0x60, 0x15, 0xc7, 0xc7, 0xbf, - 0xfb, 0x2e, 0xfc, 0xfc, 0xce, 0x45, 0x2f, 0x25, 0xb9, 0xd2, 0xce, 0xa7, - 0xc2, 0x1f, 0x2d, 0x17, 0x49, 0x4c, 0x30, 0xf5, 0xe9, 0xb2, 0xc9, 0xf6, - 0x3e, 0x7f, 0xd3, 0x22, 0x1d, 0x0b, 0x04, 0xf8, 0xed, 0x84, 0x0b, 0x24, - 0xb7, 0x33, 0x00, 0xce, 0x0c, 0xe0, 0xfc, 0xd1, 0x14, 0xdd, 0xef, 0x3b, - 0xf3, 0xb3, 0xbc, 0xde, 0x40, 0x00, 0x8a, 0xf1, 0x19, 0x13, 0xd5, 0x1a, - 0x5a, 0x45, 0x9e, 0xbb, 0x07, 0xfe, 0x1e, 0x02, 0x25, 0x05, 0x1f, 0xcf, - 0xfb, 0x47, 0xd3, 0x39, 0x38, 0xa8, 0x2b, 0x26, 0xda, 0x39, 0xa1, 0x21, - 0x69, 0x02, 0x11, 0x04, 0xbc, 0x08, 0xfd, 0xfd, 0x59, 0x3b, 0x81, 0xe0, - 0x1b, 0x91, 0x38, 0x5e, 0xef, 0x4a, 0xd0, 0xd8, 0xdd, 0xcb, 0x00, 0x06, - 0x0d, 0xed, 0x20, 0xd3, 0x48, 0x17, 0x15, 0x04, 0xdf, 0xab, 0xd1, 0x26, - 0x5f, 0x14, 0xc8, 0xb4, 0xff, 0x26, 0x9a, 0xc8, 0x2a, 0x2d, 0xfb, 0xe7, - 0xda, 0x05, 0xaa, 0xae, 0x3c, 0xf3, 0xdb, 0x09, 0x2c, 0x02, 0xd9, 0x53, - 0x49, 0x0c, 0xc4, 0xe1, 0x43, 0x7f, 0xe8, 0x12, 0xf7, 0x0c, 0xc2, 0x29, - 0xce, 0x07, 0xfd, 0x00, 0xe3, 0x3c, 0x39, 0x12, 0x30, 0xd0, 0xb5, 0x1d, - 0xf2, 0x43, 0xcb, 0xd7, 0xc8, 0x63, 0x20, 0x18, 0xaf, 0xc5, 0x51, 0xc4, - 0xea, 0xda, 0xb3, 0x9a, 0x7c, 0x6d, 0x4a, 0xcc, 0x91, 0x87, 0x71, 0x36, - 0x7f, 0x3c, 0x3f, 0xb8, 0xd8, 0x42, 0xad, 0xfb, 0xee, 0x14, 0xf2, 0x3a, - 0x12, 0xee, 0x47, 0x0d, 0x3a, 0xb3, 0x1d, 0x0e, 0xd5, 0xe5, 0xdf, 0x37, - 0x64, 0x0c, 0xa2, 0xba, 0x0d, 0x0c, 0x15, 0x72, 0xe8, 0x2a, 0xd9, 0x22, - 0xee, 0xbb, 0xd2, 0xd7, 0x07, 0xe2, 0x21, 0xda, 0xf5, 0x06, 0xec, 0xd2, - 0x81, 0xcc, 0xfc, 0x00, 0x39, 0x30, 0xeb, 0x07, 0x1a, 0xde, 0x0a, 0xfc, - 0x61, 0x12, 0x3d, 0xd9, 0x53, 0xb8, 0xeb, 0xe8, 0x00, 0x4d, 0xd7, 0xf0, - 0xcc, 0x0e, 0xcd, 0xea, 0x05, 0x92, 0xe4, 0xd5, 0xf8, 0xff, 0x4c, 0x81, - 0xc8, 0xe2, 0xda, 0x62, 0x0a, 0x1d, 0x97, 0x19, 0xaf, 0xe0, 0x4d, 0x17, - 0x0d, 0x53, 0xd3, 0x45, 0x3d, 0xed, 0x25, 0xdf, 0xfa, 0x46, 0xbf, 0xe6, - 0xc7, 0xce, 0x39, 0xbf, 0xaa, 0xe5, 0x95, 0x33, 0x2a, 0x33, 0x14, 0x42, - 0xc8, 0x0f, 0x10, 0xba, 0x50, 0xc7, 0x54, 0xac, 0x40, 0x4a, 0xfc, 0x08, - 0x8b, 0xe6, 0x4e, 0xdf, 0xe3, 0xd5, 0x10, 0xaf, 0x02, 0xfc, 0x62, 0xec, - 0x52, 0x0a, 0x43, 0x35, 0xf5, 0x81, 0x3b, 0xcb, 0x02, 0x18, 0xd8, 0x29, - 0x21, 0x04, 0xe4, 0xc7, 0xcc, 0x52, 0xf4, 0x20, 0xa2, 0x2b, 0x3c, 0xee, - 0xcb, 0x10, 0x4d, 0x4d, 0x39, 0xd2, 0xc7, 0x57, 0x07, 0xfb, 0xa7, 0xe7, - 0x3e, 0xb0, 0xa8, 0x65, 0xf9, 0x2c, 0xb0, 0x5d, 0x05, 0x16, 0x18, 0xd6, - 0xf9, 0xec, 0x1a, 0xf5, 0x0a, 0xfc, 0xbc, 0x0e, 0x1d, 0x21, 0x1e, 0x0a, - 0x4b, 0xd4, 0x45, 0x27, 0xeb, 0x48, 0x16, 0xb0, 0x07, 0xc8, 0x23, 0x54, - 0xe6, 0x23, 0xd2, 0x33, 0xd0, 0x02, 0xb5, 0x0c, 0x03, 0x43, 0xe2, 0x31, - 0x02, 0x50, 0xf9, 0xfb, 0x60, 0xd1, 0xf1, 0x0d, 0xf8, 0xd7, 0x13, 0xce, - 0x47, 0x5a, 0x0d, 0x0d, 0xbc, 0x34, 0x0d, 0xec, 0x6c, 0x03, 0x17, 0xb8, - 0xb9, 0xfb, 0xc1, 0x3b, 0x16, 0x7f, 0x50, 0xde, 0x1b, 0x30, 0x0c, 0x17, - 0xf6, 0xe5, 0x47, 0x06, 0x07, 0x01, 0x25, 0x5d, 0xe3, 0x07, 0x16, 0xf4, - 0xe6, 0x34, 0x3b, 0x36, 0x4b, 0x10, 0x23, 0x01, 0xd3, 0xfe, 0xfc, 0x01, - 0x25, 0xf7, 0x01, 0xc5, 0x0e, 0xb2, 0xf3, 0x5e, 0x25, 0x1a, 0xc8, 0x4f, - 0x52, 0xf8, 0x1a, 0xef, 0x6d, 0x10, 0x27, 0xef, 0xf3, 0x03, 0x19, 0xe4, - 0x26, 0x97, 0xd5, 0xea, 0x8f, 0xdc, 0x01, 0x16, 0xe4, 0x20, 0x81, 0xfe, - 0x37, 0xbc, 0x40, 0x1d, 0x34, 0x4c, 0x40, 0x18, 0xdf, 0x0d, 0x14, 0x09, - 0x00, 0xe5, 0xfb, 0xdb, 0x10, 0x84, 0xd5, 0xe6, 0xd1, 0x41, 0xca, 0xdb, - 0x3a, 0x28, 0xca, 0x6e, 0xef, 0xc7, 0xb3, 0x21, 0xf7, 0x0d, 0x28, 0xcf, - 0x27, 0x06, 0xe9, 0x81, 0x21, 0xf4, 0xc8, 0x0e, 0xd9, 0xad, 0x0e, 0x36, - 0x0e, 0xd6, 0xeb, 0xe4, 0xeb, 0xe7, 0x41, 0xcf, 0x67, 0xf1, 0xc2, 0xf3, - 0xf7, 0xd3, 0x48, 0x19, 0x10, 0xd5, 0xf2, 0xe1, 0xe4, 0x43, 0x26, 0xcd, - 0xe0, 0x11, 0x07, 0x17, 0xd9, 0xa2, 0x28, 0x14, 0xb5, 0x03, 0xa4, 0xcd, - 0x1f, 0xd1, 0xc9, 0xef, 0xca, 0xbc, 0x43, 0x39, 0x61, 0xea, 0x13, 0x2e, - 0xfc, 0xcb, 0x19, 0x6a, 0xef, 0x04, 0xe3, 0xd3, 0xab, 0x3a, 0x0b, 0xc1, - 0xaf, 0xef, 0x24, 0x16, 0x7f, 0x51, 0x05, 0xe0, 0xc5, 0x13, 0x4f, 0xe6, - 0xd8, 0x8d, 0xdf, 0x30, 0xac, 0x2c, 0x5a, 0x9b, 0x3d, 0xf5, 0xde, 0x22, - 0xcd, 0xec, 0xd2, 0x27, 0x34, 0x05, 0x66, 0x26, 0x64, 0x42, 0xff, 0xff, - 0x68, 0x42, 0xff, 0xff, 0x62, 0xaa, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, - 0x40, 0x03, 0x00, 0x00, 0xd4, 0x30, 0x18, 0xc4, 0x23, 0xb5, 0x03, 0xc9, - 0x05, 0xe9, 0x97, 0xca, 0x5b, 0xa5, 0xe7, 0xe2, 0x0d, 0xae, 0x25, 0xf0, - 0x13, 0x4c, 0x19, 0x1d, 0xe3, 0x00, 0x2b, 0xa7, 0xe2, 0x30, 0xf0, 0x5d, - 0xc6, 0x01, 0x42, 0xf1, 0xed, 0xdd, 0x28, 0xbb, 0x43, 0x38, 0xe5, 0x24, - 0x00, 0xc7, 0xf3, 0x47, 0xb7, 0x4f, 0x49, 0x03, 0xf7, 0xb0, 0xec, 0xc0, - 0x1c, 0xe2, 0xeb, 0x31, 0xf2, 0xfc, 0xcb, 0x26, 0x17, 0x2d, 0x01, 0xc5, - 0x2a, 0xef, 0xe3, 0x04, 0x0d, 0xde, 0xd4, 0xca, 0x33, 0xb1, 0x3a, 0x8a, - 0x01, 0xac, 0x0b, 0xda, 0xe1, 0x07, 0xf5, 0xf8, 0x25, 0x23, 0x34, 0xb2, - 0xc5, 0x2f, 0xc3, 0x3a, 0xca, 0xeb, 0x2c, 0xfe, 0xd9, 0xef, 0x19, 0x01, - 0x48, 0x1c, 0xf8, 0x32, 0x29, 0xc8, 0xe0, 0x28, 0xe1, 0x14, 0x4b, 0x2f, - 0xd2, 0xda, 0xd6, 0xe0, 0x16, 0xef, 0x1b, 0x25, 0xf3, 0x09, 0x22, 0x1b, - 0xe2, 0x12, 0x10, 0xd4, 0x23, 0xcc, 0xe9, 0x25, 0x07, 0xba, 0xbd, 0xf5, - 0x01, 0xd6, 0x38, 0xbb, 0xec, 0xef, 0xe6, 0x02, 0x1f, 0x18, 0x27, 0xf2, - 0x19, 0x02, 0xe2, 0xd4, 0x0b, 0x2c, 0x1d, 0x2d, 0xdf, 0xcd, 0x2c, 0xe5, - 0xe0, 0x26, 0x0c, 0xeb, 0xef, 0x30, 0xed, 0x19, 0x3a, 0xd0, 0xf7, 0x37, - 0xd1, 0x2e, 0x2e, 0x11, 0x17, 0xa9, 0xfb, 0xf2, 0x0e, 0xf5, 0x31, 0x0e, - 0x02, 0x0f, 0xd1, 0x31, 0xf3, 0x2c, 0xfd, 0xf5, 0x39, 0xd9, 0xe4, 0x2b, - 0x2c, 0xc2, 0x0c, 0x04, 0x47, 0xdf, 0x0a, 0xce, 0xe5, 0x10, 0x03, 0x1e, - 0x18, 0xec, 0x14, 0xed, 0x3c, 0x19, 0x33, 0xc3, 0x0a, 0xf3, 0x1b, 0x14, - 0xde, 0xea, 0x3b, 0x00, 0xc0, 0x05, 0x11, 0xe6, 0xf7, 0x15, 0xf4, 0xdc, - 0x26, 0x06, 0x0c, 0x48, 0xe5, 0x16, 0xf5, 0x23, 0xe8, 0xb5, 0x22, 0x11, - 0xef, 0xe1, 0xd5, 0x2c, 0xe5, 0x15, 0xe8, 0x32, 0xf9, 0x11, 0x1d, 0x24, - 0x19, 0xda, 0xe9, 0x39, 0x19, 0xfd, 0xf6, 0x25, 0xfd, 0xdd, 0x21, 0xbb, - 0xc2, 0x12, 0xe9, 0xd5, 0x1a, 0x0a, 0xf4, 0x08, 0x1b, 0x16, 0xe7, 0xa8, - 0xe7, 0x0d, 0x06, 0x29, 0xc4, 0xd4, 0x11, 0x11, 0xd3, 0x0f, 0x1e, 0xe1, - 0x1c, 0xea, 0xf3, 0xe6, 0xf5, 0x0d, 0xf1, 0x40, 0xc3, 0x16, 0x09, 0x0d, - 0xf4, 0xe0, 0x00, 0xfd, 0x0d, 0xde, 0xcf, 0x30, 0xdd, 0x00, 0x30, 0x03, - 0xf7, 0x03, 0x22, 0x39, 0xfd, 0xb4, 0xd7, 0x45, 0x06, 0xd6, 0xcf, 0xef, - 0xfe, 0xc6, 0x2a, 0xd4, 0xd0, 0x02, 0xc6, 0xec, 0xed, 0x16, 0x1f, 0xb0, - 0xea, 0xdb, 0xe2, 0x85, 0xed, 0xb6, 0x4a, 0x08, 0xc5, 0xb7, 0x0b, 0x17, - 0x05, 0xf3, 0x19, 0xdb, 0x2c, 0x07, 0xe2, 0xde, 0x39, 0x29, 0x07, 0x04, - 0xf4, 0x0e, 0x27, 0xdb, 0xd9, 0xd2, 0x26, 0xde, 0xee, 0xd1, 0xfe, 0x12, - 0x20, 0x18, 0xfb, 0x08, 0xda, 0xfd, 0xe9, 0x01, 0xf9, 0xad, 0xdd, 0x29, - 0x01, 0xd8, 0x0d, 0xee, 0x0a, 0xe1, 0x2e, 0xe5, 0xb0, 0x0e, 0xbe, 0xfc, - 0x03, 0x27, 0xf6, 0xb4, 0xe9, 0x03, 0x16, 0xa1, 0xd4, 0x17, 0xea, 0x10, - 0xd7, 0xc7, 0x24, 0xf1, 0xf6, 0x2a, 0xf4, 0x21, 0x1d, 0xfd, 0xbb, 0xfd, - 0x1e, 0xf6, 0xee, 0xfb, 0x14, 0xf6, 0x37, 0xfb, 0xf3, 0xed, 0x0f, 0x01, - 0xef, 0xfd, 0xce, 0x1f, 0xee, 0x16, 0x1e, 0xe9, 0xcd, 0x26, 0x44, 0xff, - 0x22, 0xbd, 0x1d, 0x24, 0xe7, 0x00, 0xe9, 0x2b, 0xc7, 0xf3, 0x04, 0xfb, - 0xbd, 0x30, 0xdf, 0xd5, 0x1b, 0x1f, 0x15, 0x95, 0xe0, 0xe3, 0x2e, 0xb5, - 0xb1, 0xd7, 0x3a, 0x12, 0xc2, 0xe2, 0xec, 0xf0, 0x1b, 0x30, 0x2e, 0x08, - 0x29, 0xfe, 0xe8, 0x1f, 0x28, 0x2f, 0xf3, 0xf0, 0xf0, 0x0b, 0x18, 0xbd, - 0xe0, 0xdd, 0x2a, 0x00, 0x20, 0xc9, 0x24, 0x1e, 0xdc, 0x3a, 0x48, 0x1a, - 0x0d, 0xef, 0xe4, 0x26, 0x20, 0xc8, 0x0b, 0xf0, 0x2c, 0x03, 0x0b, 0x04, - 0xcb, 0xca, 0x58, 0x0c, 0xe0, 0x07, 0xb7, 0xeb, 0x19, 0x1a, 0xe7, 0xde, - 0x04, 0x20, 0x29, 0xe2, 0xef, 0xd8, 0x26, 0xe3, 0xe2, 0xcc, 0xfc, 0xec, - 0x2a, 0x19, 0x40, 0x08, 0x04, 0xf5, 0x03, 0x0d, 0x33, 0x29, 0x18, 0x2c, - 0xd2, 0xe5, 0x0b, 0xdc, 0xe1, 0xcb, 0x01, 0x4d, 0x08, 0xb2, 0x36, 0x0d, - 0x06, 0x22, 0xfd, 0x0b, 0xde, 0x20, 0x3e, 0xf4, 0x19, 0xe6, 0x0d, 0x34, - 0x3c, 0x09, 0xf5, 0xe3, 0xdd, 0xf9, 0x5f, 0x1b, 0xcd, 0x29, 0xe0, 0xcd, - 0x41, 0x24, 0xe7, 0xc7, 0xed, 0x07, 0x05, 0x08, 0xd9, 0xfe, 0x21, 0x16, - 0xb3, 0xe4, 0x0f, 0xb5, 0x34, 0x1b, 0x1e, 0xfc, 0x25, 0x03, 0xcf, 0xf6, - 0x17, 0x2c, 0x29, 0xfa, 0x10, 0x00, 0x39, 0xc3, 0xd9, 0xe4, 0x1c, 0xed, - 0x26, 0xc6, 0x01, 0x49, 0xf3, 0x49, 0x2c, 0xdb, 0xeb, 0xf0, 0x32, 0x23, - 0xe2, 0xc6, 0xf2, 0xfc, 0x1f, 0xe7, 0xf7, 0x0d, 0xc1, 0x05, 0x7d, 0xcd, - 0xd2, 0xff, 0xf3, 0xd2, 0x5a, 0x45, 0x02, 0xd7, 0x1c, 0x10, 0x41, 0x3e, - 0xa7, 0xde, 0xe8, 0xf5, 0xdc, 0xe1, 0xda, 0xd5, 0x27, 0x34, 0x0d, 0xfe, - 0xd3, 0x35, 0xed, 0x22, 0x25, 0x1f, 0x2d, 0x0d, 0x0f, 0xe4, 0x35, 0xd9, - 0xb2, 0xe2, 0xfc, 0x08, 0x1f, 0xa8, 0x22, 0x1c, 0xfe, 0x54, 0x04, 0xce, - 0xfc, 0x30, 0x0c, 0x0a, 0xf2, 0xe3, 0x16, 0xeb, 0x09, 0x0d, 0xc9, 0xe3, - 0xd1, 0xe7, 0x75, 0xe3, 0x02, 0x49, 0xd6, 0xf1, 0x34, 0x58, 0x2a, 0xf9, - 0x0c, 0xef, 0xf6, 0x51, 0xb5, 0xf1, 0x0d, 0x19, 0x10, 0xd1, 0x0d, 0xfc, - 0xfb, 0x49, 0xfe, 0xeb, 0xce, 0x3a, 0xdd, 0xfd, 0x05, 0x6d, 0x4a, 0x2f, - 0x1d, 0xa1, 0xff, 0xfd, 0xe0, 0xbf, 0x19, 0x21, 0x11, 0xa0, 0xf2, 0x63, - 0xf1, 0x42, 0x2c, 0x17, 0xfb, 0x36, 0x1f, 0xf6, 0x0c, 0x1a, 0x46, 0x16, - 0x0f, 0x39, 0xfd, 0xaf, 0xa8, 0xe1, 0x73, 0xeb, 0xd1, 0x42, 0xcf, 0xdd, - 0xf1, 0x1f, 0x0d, 0x16, 0x01, 0xd4, 0x0c, 0x73, 0x98, 0x05, 0x43, 0xb7, - 0x05, 0xf8, 0xf5, 0xf7, 0xe1, 0x5f, 0x1f, 0x2f, 0xe7, 0x55, 0xc0, 0x05, - 0xfc, 0x7c, 0x45, 0x58, 0xe3, 0xa7, 0x22, 0x0a, 0xec, 0xd0, 0x2a, 0x4b, - 0x0f, 0x81, 0x35, 0x1e, 0x11, 0x35, 0xf3, 0xd2, 0xb8, 0x45, 0xff, 0xff, - 0xb2, 0xad, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, - 0xe3, 0xf6, 0xff, 0xff, 0x31, 0xf4, 0xff, 0xff, 0x53, 0x1b, 0x00, 0x00, - 0xa1, 0xfe, 0xff, 0xff, 0x5d, 0x06, 0x00, 0x00, 0x42, 0xd2, 0xff, 0xff, - 0x49, 0x12, 0x00, 0x00, 0x64, 0xe5, 0xff, 0xff, 0x59, 0x13, 0x00, 0x00, - 0x11, 0x18, 0x00, 0x00, 0x2a, 0xe9, 0xff, 0xff, 0xbf, 0x00, 0x00, 0x00, - 0x36, 0x1a, 0x00, 0x00, 0xde, 0x15, 0x00, 0x00, 0x78, 0x20, 0x00, 0x00, - 0xb1, 0xec, 0xff, 0xff, 0x4e, 0xee, 0xff, 0xff, 0x6e, 0x1d, 0x00, 0x00, - 0x22, 0x1c, 0x00, 0x00, 0xe7, 0xf7, 0xff, 0xff, 0x76, 0xf7, 0xff, 0xff, - 0x21, 0xe1, 0xff, 0xff, 0xea, 0xf9, 0xff, 0xff, 0x37, 0xf2, 0xff, 0xff, - 0xef, 0xe1, 0xff, 0xff, 0x2b, 0x18, 0x00, 0x00, 0x3f, 0xe1, 0xff, 0xff, - 0xf0, 0xc8, 0xff, 0xff, 0x3e, 0xd1, 0xff, 0xff, 0x4f, 0x02, 0x00, 0x00, - 0x36, 0xf6, 0xff, 0xff, 0x47, 0x15, 0x00, 0x00, 0x79, 0xef, 0xff, 0xff, - 0x0f, 0x20, 0x00, 0x00, 0xec, 0x1a, 0x00, 0x00, 0xe6, 0x0a, 0x00, 0x00, - 0x15, 0xe4, 0xff, 0xff, 0x43, 0xe1, 0xff, 0xff, 0xd0, 0x0f, 0x00, 0x00, - 0x91, 0xf0, 0xff, 0xff, 0xed, 0xed, 0xff, 0xff, 0xeb, 0xfd, 0xff, 0xff, - 0xd6, 0xf2, 0xff, 0xff, 0xa9, 0x03, 0x00, 0x00, 0x4d, 0xec, 0xff, 0xff, - 0xf9, 0xec, 0xff, 0xff, 0x7c, 0x19, 0x00, 0x00, 0xa2, 0x09, 0x00, 0x00, - 0x7d, 0x0a, 0x00, 0x00, 0x30, 0x0c, 0x00, 0x00, 0xf2, 0xeb, 0xff, 0xff, - 0x24, 0x07, 0x00, 0x00, 0x50, 0x08, 0x00, 0x00, 0x8d, 0x1e, 0x00, 0x00, - 0x3d, 0x12, 0x00, 0x00, 0x09, 0x26, 0x00, 0x00, 0x15, 0xe6, 0xff, 0xff, - 0xdb, 0xff, 0xff, 0xff, 0x26, 0x03, 0x00, 0x00, 0x3b, 0x15, 0x00, 0x00, - 0x1b, 0x13, 0x00, 0x00, 0xfd, 0xea, 0xff, 0xff, 0xe0, 0x04, 0x00, 0x00, - 0xf8, 0xee, 0xff, 0xff, 0xbe, 0xae, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, - 0x00, 0x10, 0x00, 0x00, 0x11, 0x3a, 0x6a, 0xab, 0x93, 0x2d, 0x2b, 0xba, - 0xe6, 0x42, 0x15, 0x99, 0x17, 0x61, 0x45, 0xad, 0xb6, 0x0b, 0x34, 0x64, - 0x5d, 0x0f, 0xd8, 0x66, 0xd6, 0x1b, 0x7f, 0x07, 0xff, 0x00, 0xb0, 0xde, - 0xcf, 0x88, 0xc0, 0xdd, 0xd4, 0x10, 0x99, 0x5c, 0x13, 0x60, 0xc5, 0x5b, - 0x22, 0xf9, 0x71, 0x9e, 0x6b, 0x46, 0x1e, 0x1b, 0xeb, 0xbe, 0x2f, 0xd1, - 0x0e, 0x88, 0xa6, 0x44, 0xf9, 0x5c, 0x14, 0x24, 0x8c, 0x0f, 0xf0, 0xc1, - 0x44, 0x13, 0xbb, 0x59, 0x13, 0x4b, 0x1c, 0xa9, 0xe6, 0x3a, 0x34, 0xaf, - 0x3c, 0x13, 0xa3, 0xc5, 0xab, 0xf3, 0x7f, 0xa3, 0x58, 0x9d, 0xce, 0xf5, - 0xac, 0x65, 0xfe, 0x09, 0xd7, 0x08, 0x5a, 0x22, 0x20, 0xa9, 0x68, 0xbe, - 0xee, 0x4c, 0xf7, 0x31, 0x21, 0xe2, 0xc3, 0xf7, 0xb7, 0x18, 0xfe, 0xbd, - 0x1d, 0x1a, 0xe5, 0x53, 0xb2, 0xf1, 0xe5, 0xe2, 0xe7, 0x9d, 0xdf, 0xd6, - 0x28, 0xfd, 0xf6, 0x3c, 0x5b, 0xc4, 0xcb, 0x73, 0x3b, 0xcc, 0x0b, 0xdb, - 0x29, 0x88, 0xd9, 0xf5, 0x1d, 0x05, 0x53, 0xe9, 0x3f, 0x23, 0x71, 0x33, - 0x57, 0xd7, 0xd5, 0xd7, 0xcc, 0xc4, 0xde, 0x14, 0x05, 0xea, 0x2d, 0xe6, - 0xf0, 0xa6, 0xd9, 0x56, 0x37, 0x42, 0x81, 0x60, 0xc7, 0x29, 0x4c, 0xe8, - 0x0e, 0xdd, 0x34, 0xfc, 0xff, 0xd6, 0x0a, 0xb7, 0x50, 0xcd, 0x0d, 0xce, - 0xfa, 0x19, 0xab, 0x33, 0xb8, 0xff, 0x53, 0x49, 0xbe, 0x35, 0x29, 0xe9, - 0x30, 0x39, 0x16, 0xfa, 0xf4, 0xc1, 0x7f, 0x1a, 0xb4, 0x45, 0xa7, 0xd7, - 0xbe, 0xff, 0xfe, 0x18, 0x0b, 0x23, 0xdc, 0xe9, 0x1b, 0x33, 0x23, 0x10, - 0xeb, 0x26, 0xbc, 0x5d, 0x43, 0x09, 0xc6, 0xae, 0x20, 0x3a, 0xe1, 0xce, - 0x08, 0x4e, 0x11, 0xac, 0xad, 0x42, 0x0e, 0xe2, 0xec, 0xae, 0x1b, 0xb4, - 0x4f, 0x39, 0xb3, 0x2a, 0xc4, 0xd2, 0xab, 0x2c, 0xdc, 0x7f, 0xda, 0x47, - 0x5f, 0x0c, 0xd5, 0x55, 0x4a, 0x2f, 0x06, 0xfd, 0x2b, 0xd8, 0x0c, 0xb2, - 0x2c, 0x41, 0x06, 0xf7, 0xfa, 0x09, 0x0b, 0x2b, 0xfc, 0x30, 0x22, 0x17, - 0xce, 0xb7, 0x02, 0xef, 0xed, 0x83, 0x51, 0x42, 0x02, 0xbb, 0xe3, 0xfe, - 0x31, 0x05, 0x2c, 0x41, 0x21, 0xbd, 0xfb, 0x01, 0xc4, 0x04, 0xf3, 0x34, - 0xdd, 0xed, 0xba, 0x33, 0xaf, 0xb5, 0x17, 0x17, 0x12, 0x27, 0xa2, 0x0d, - 0xd9, 0x81, 0x07, 0xdd, 0xef, 0x2a, 0xdb, 0xac, 0xed, 0x22, 0xf5, 0x07, - 0xfe, 0x03, 0x4c, 0x04, 0x7a, 0x99, 0xaa, 0xe0, 0x35, 0x41, 0x0d, 0x04, - 0x2d, 0xeb, 0x3e, 0x1f, 0x05, 0x30, 0x5c, 0xb9, 0xbd, 0xdd, 0xe5, 0xfc, - 0x35, 0x3d, 0x3c, 0x41, 0x3c, 0x3c, 0x28, 0xb9, 0x38, 0x46, 0xd5, 0xfd, - 0xa2, 0xc8, 0xe5, 0x10, 0xda, 0x64, 0x12, 0x64, 0x82, 0x39, 0xb4, 0x13, - 0xcb, 0x18, 0x3e, 0x30, 0x00, 0xe9, 0xdf, 0x59, 0x5e, 0x4b, 0xd1, 0x60, - 0xef, 0x37, 0xfe, 0x0c, 0x18, 0x1e, 0xd7, 0xbc, 0x3c, 0x06, 0x9f, 0xa7, - 0x1e, 0xb0, 0x23, 0xc1, 0x2c, 0xc8, 0x07, 0xe9, 0xd5, 0x0b, 0xcd, 0x19, - 0x6e, 0x16, 0x1c, 0x23, 0x38, 0xea, 0x88, 0x08, 0xb5, 0xff, 0xbf, 0xd3, - 0x01, 0xcd, 0x06, 0xd1, 0x35, 0x8f, 0x04, 0x05, 0xda, 0xec, 0x01, 0xcc, - 0xd1, 0xd8, 0x7f, 0xdb, 0xc7, 0x0c, 0xe5, 0x0a, 0x86, 0xa5, 0xf5, 0xa0, - 0x6c, 0x9e, 0xd9, 0xf9, 0xe6, 0x2b, 0xf0, 0x3a, 0x72, 0x4e, 0xb6, 0x75, - 0x1c, 0x24, 0xe8, 0xc8, 0x9b, 0x12, 0xdb, 0xe4, 0x6b, 0x2f, 0xaf, 0x5a, - 0x4b, 0x5c, 0x1c, 0xcb, 0x2e, 0x58, 0x79, 0x14, 0x12, 0x7f, 0x1f, 0xf0, - 0x01, 0x54, 0x6e, 0x2f, 0x4b, 0x59, 0xfd, 0x5f, 0xd8, 0x38, 0x4b, 0x75, - 0xe8, 0x37, 0x69, 0x2a, 0x1b, 0x5e, 0xf6, 0x23, 0x05, 0xfd, 0xf2, 0x75, - 0xba, 0x24, 0x55, 0x5b, 0xfd, 0xfa, 0x40, 0x2b, 0xdb, 0xe6, 0xd7, 0x23, - 0xa9, 0xe5, 0xa5, 0xc5, 0xf6, 0x1f, 0xdd, 0x08, 0x29, 0xd3, 0x07, 0xc9, - 0xa8, 0x13, 0x2a, 0xd1, 0x21, 0x0b, 0xaa, 0x27, 0x4e, 0x81, 0xe3, 0xc6, - 0x0f, 0xe8, 0x89, 0x67, 0xa7, 0xdc, 0xd0, 0xf3, 0x10, 0xf9, 0x3e, 0x59, - 0xd8, 0xc1, 0x27, 0x27, 0x2b, 0xc4, 0x1a, 0xfd, 0xd2, 0xd6, 0x23, 0x18, - 0xe6, 0xd9, 0x3f, 0x12, 0xd1, 0x19, 0x25, 0xca, 0x3d, 0xfa, 0x19, 0x14, - 0x46, 0x0e, 0xbb, 0x1a, 0x21, 0xf4, 0x8b, 0x47, 0xc7, 0x1b, 0x0a, 0xa9, - 0x24, 0xfa, 0xfb, 0x07, 0xb7, 0xd6, 0xde, 0x28, 0xe1, 0xe4, 0xe7, 0xf0, - 0xc7, 0x81, 0x11, 0x45, 0x15, 0xc8, 0x22, 0xd9, 0xbd, 0x19, 0x55, 0xbd, - 0x11, 0x2b, 0x20, 0x02, 0xe9, 0x47, 0xc5, 0x21, 0xe1, 0x50, 0xda, 0x33, - 0xd8, 0x8a, 0x57, 0x04, 0x12, 0x0d, 0x35, 0x48, 0x2a, 0xc1, 0x3c, 0xd6, - 0x11, 0x71, 0x5b, 0xd7, 0xab, 0x45, 0xd5, 0x2a, 0x23, 0x13, 0x35, 0xbd, - 0x4b, 0xe5, 0xdc, 0x81, 0x11, 0x67, 0x4d, 0x1d, 0x9c, 0xb1, 0xf3, 0x62, - 0xf8, 0x49, 0x00, 0x7c, 0x91, 0x87, 0x45, 0x1a, 0xee, 0x3e, 0x50, 0x32, - 0xae, 0xc2, 0x4f, 0xaf, 0xfc, 0x16, 0x57, 0xab, 0x03, 0xfe, 0x86, 0xed, - 0x50, 0x4d, 0x9c, 0x45, 0xb9, 0x4d, 0xfe, 0x6b, 0x19, 0x74, 0xcb, 0xd7, - 0x49, 0x70, 0xa9, 0x4a, 0x46, 0xd5, 0x46, 0x6d, 0xe0, 0x2b, 0xc6, 0xce, - 0x3c, 0xf6, 0xa2, 0x38, 0x5e, 0x62, 0x33, 0x0e, 0xcf, 0xd3, 0xf4, 0xbd, - 0x32, 0xc6, 0x1a, 0x42, 0x37, 0xfa, 0xdb, 0xdf, 0xc2, 0xae, 0xf0, 0x48, - 0x5a, 0x48, 0x2c, 0xc3, 0x4e, 0x48, 0xdc, 0xb9, 0x19, 0xaa, 0x68, 0xd7, - 0x1c, 0x05, 0xc2, 0x7f, 0x18, 0x08, 0x2a, 0xd5, 0xaf, 0xa7, 0xcb, 0xd0, - 0xe9, 0xed, 0x18, 0xd5, 0x0e, 0x0a, 0xd3, 0xeb, 0x1e, 0xd6, 0x21, 0x78, - 0x17, 0xde, 0x32, 0x01, 0xd6, 0x1c, 0x27, 0xf1, 0x22, 0x0c, 0x28, 0x24, - 0x18, 0xd6, 0xd3, 0x33, 0x07, 0xb0, 0xbc, 0x14, 0x36, 0xf5, 0x0a, 0x2f, - 0xfa, 0xfc, 0x28, 0x10, 0xcf, 0xff, 0x81, 0x3f, 0xf1, 0x0f, 0xfa, 0xaa, - 0x0f, 0x2b, 0x2b, 0x2a, 0x45, 0x28, 0xe2, 0xd9, 0x3c, 0x32, 0x28, 0x7c, - 0x0f, 0x0a, 0x0b, 0xcd, 0xca, 0x5d, 0x18, 0x07, 0x41, 0x1a, 0xf4, 0x62, - 0x51, 0x14, 0xe6, 0x5b, 0x14, 0xcd, 0xb4, 0xf7, 0xa5, 0xe7, 0xa2, 0x35, - 0x11, 0xe3, 0x65, 0x15, 0xda, 0x0c, 0x8a, 0x28, 0xf9, 0x1a, 0x24, 0xa3, - 0x27, 0xb9, 0x0e, 0xfa, 0x38, 0x9b, 0xce, 0xa3, 0xc7, 0x3e, 0xd2, 0x51, - 0xc0, 0xbc, 0x35, 0xde, 0xe2, 0xe9, 0xe6, 0xf8, 0x7f, 0xf3, 0xbe, 0x96, - 0x00, 0xf6, 0xc7, 0xe6, 0x35, 0x31, 0xd1, 0x3f, 0x32, 0x1b, 0xf1, 0x2e, - 0x7a, 0x37, 0x44, 0x1d, 0x49, 0x39, 0x3a, 0x5e, 0xef, 0xb8, 0x01, 0xe3, - 0xea, 0x30, 0x29, 0xc0, 0xbc, 0xfd, 0x0f, 0xec, 0xd5, 0xea, 0xe7, 0x3f, - 0xd4, 0xfd, 0xce, 0x17, 0xd7, 0xdc, 0xeb, 0x0a, 0x05, 0xe3, 0xcf, 0x18, - 0xe4, 0x3d, 0xd0, 0xf1, 0x18, 0x18, 0xe8, 0xdc, 0xf3, 0x18, 0xe7, 0xbf, - 0xf2, 0xc6, 0x24, 0xc8, 0xd6, 0xd6, 0xfa, 0xe9, 0x2e, 0xe1, 0x7f, 0xe9, - 0x1b, 0xec, 0xe5, 0x00, 0x0d, 0x20, 0xd2, 0xec, 0x54, 0x98, 0x17, 0x08, - 0x4f, 0x39, 0x3e, 0xf2, 0xfd, 0xfc, 0xb6, 0xa7, 0x07, 0x15, 0x02, 0x37, - 0x49, 0x30, 0xd9, 0xb7, 0xf2, 0xff, 0xeb, 0xa7, 0xe2, 0xd7, 0xca, 0xa5, - 0x3b, 0x7f, 0xf0, 0xec, 0xab, 0xad, 0x4a, 0x01, 0x51, 0xe1, 0xdb, 0xe7, - 0xbf, 0xd3, 0x2e, 0xa4, 0x20, 0xc3, 0xf6, 0x24, 0xa8, 0xcc, 0xd5, 0xca, - 0x19, 0x42, 0xde, 0xa9, 0x5b, 0xe5, 0xb1, 0x50, 0xa0, 0xd4, 0x0a, 0xd6, - 0xa1, 0x26, 0x68, 0x96, 0x8a, 0x00, 0xb6, 0x67, 0x3d, 0xe7, 0x48, 0x49, - 0x2e, 0xc3, 0x3f, 0x81, 0xf0, 0x49, 0x0a, 0x56, 0xb7, 0xd8, 0x6f, 0xc8, - 0x33, 0x40, 0x1e, 0x03, 0xc6, 0xcb, 0xd0, 0x38, 0x70, 0xcc, 0xd2, 0x9b, - 0xb4, 0xb3, 0x66, 0x97, 0xbf, 0xd3, 0x11, 0xdc, 0x6c, 0x5c, 0xaa, 0x27, - 0x8e, 0xed, 0xfd, 0xe3, 0xf3, 0xf0, 0x17, 0xaf, 0xbd, 0xf8, 0x3a, 0x11, - 0xf6, 0x45, 0x51, 0x07, 0x67, 0xee, 0xf4, 0x5a, 0x19, 0xe0, 0xe0, 0x14, - 0x36, 0x40, 0x2f, 0x27, 0xf3, 0x0c, 0x34, 0xc5, 0x52, 0xf0, 0xe3, 0x47, - 0x2c, 0xe8, 0x30, 0xe9, 0xe8, 0x3f, 0x0b, 0x52, 0x19, 0xa6, 0xf0, 0x09, - 0xc2, 0x22, 0xb0, 0xc9, 0x06, 0xe2, 0xec, 0xf6, 0x44, 0x37, 0x2b, 0xce, - 0xea, 0xb9, 0x6a, 0x0b, 0xc7, 0xc5, 0x4a, 0xcd, 0x32, 0x89, 0x7f, 0x22, - 0xdd, 0xe5, 0x1b, 0xc6, 0xd8, 0x66, 0x2c, 0x3d, 0xc4, 0x14, 0x42, 0x6b, - 0xd3, 0xfa, 0x26, 0x0c, 0x0e, 0xdc, 0xaf, 0xe7, 0xb0, 0x76, 0x0c, 0xec, - 0xc5, 0xbb, 0xae, 0x07, 0xe4, 0x9c, 0xd2, 0xff, 0xd2, 0x05, 0x8c, 0x09, - 0x56, 0xc7, 0x5f, 0xf6, 0x23, 0xff, 0x12, 0xbe, 0xd4, 0x2c, 0xcb, 0x30, - 0x0b, 0x81, 0xcf, 0x1c, 0x2a, 0x2f, 0xf0, 0x30, 0x0b, 0x5b, 0xeb, 0x3a, - 0x30, 0x3c, 0xfc, 0xc6, 0xda, 0x22, 0xf0, 0x36, 0xb6, 0xfa, 0x69, 0xba, - 0xd7, 0x1e, 0xec, 0x3b, 0x74, 0x1f, 0xe4, 0xd9, 0xe9, 0x2b, 0xfc, 0x9b, - 0xf9, 0xeb, 0xa1, 0xec, 0xfe, 0x91, 0xda, 0x48, 0x21, 0x4d, 0xbd, 0x36, - 0xe1, 0xf8, 0x18, 0xeb, 0xdd, 0x0a, 0x3a, 0x1e, 0xa5, 0xc5, 0x20, 0x8e, - 0xc5, 0x62, 0xaa, 0x0d, 0x8d, 0xe1, 0xc6, 0x13, 0xd2, 0x3d, 0x73, 0x1a, - 0x36, 0xb1, 0x52, 0xd3, 0x0e, 0x03, 0xeb, 0x81, 0x4e, 0x21, 0x16, 0x34, - 0xe1, 0x61, 0xde, 0x1e, 0xc4, 0xf6, 0xd4, 0xd0, 0x65, 0x0c, 0xe2, 0x92, - 0x1e, 0xf0, 0x2a, 0xd1, 0xf6, 0xe7, 0xf8, 0x2f, 0xe2, 0xcd, 0x23, 0x3a, - 0xb2, 0x02, 0xcf, 0x52, 0xb7, 0xf5, 0xf4, 0x12, 0x2e, 0xab, 0x44, 0xfd, - 0xda, 0x1e, 0x3a, 0xde, 0x68, 0x4b, 0x1c, 0xe7, 0x19, 0x01, 0x5a, 0x03, - 0xd0, 0xfd, 0x04, 0xf0, 0xea, 0xdb, 0xe0, 0x26, 0x37, 0xff, 0x04, 0x67, - 0xcd, 0x7f, 0xd5, 0x40, 0x1d, 0xb0, 0x97, 0x0a, 0xbf, 0xed, 0x8c, 0x96, - 0xd8, 0x3f, 0x2d, 0xce, 0x6b, 0x10, 0x4a, 0xb0, 0x01, 0x03, 0xb1, 0xd0, - 0xbe, 0x4f, 0x6f, 0xc2, 0xf2, 0x81, 0x13, 0xf8, 0x4e, 0x50, 0x29, 0x1c, - 0xf2, 0xde, 0xaf, 0xa4, 0x44, 0x20, 0x5a, 0x31, 0x12, 0xc3, 0xe0, 0xef, - 0x42, 0xf6, 0xc3, 0x16, 0x15, 0xba, 0xa8, 0xd1, 0xe9, 0x14, 0x55, 0x75, - 0x10, 0x7b, 0xed, 0x15, 0x22, 0xec, 0x13, 0xe2, 0xe9, 0xb8, 0x1e, 0xb3, - 0xe5, 0x32, 0xf8, 0xb7, 0xc3, 0x56, 0xb4, 0xb0, 0x4b, 0x57, 0x3d, 0x4e, - 0xc4, 0x81, 0xbd, 0xd8, 0xbb, 0xcc, 0xdb, 0x51, 0x0b, 0xee, 0x4e, 0xfb, - 0x05, 0x7e, 0x1e, 0xd4, 0x62, 0xf7, 0x56, 0x28, 0xf2, 0xc3, 0x98, 0x05, - 0x0e, 0x1f, 0x91, 0x95, 0x5d, 0xf2, 0x07, 0x63, 0xe5, 0xb4, 0xd4, 0x56, - 0xa8, 0x3e, 0xb4, 0x1c, 0x3a, 0xd8, 0xd0, 0x70, 0xbb, 0x02, 0x10, 0x02, - 0x95, 0xfa, 0xf7, 0xcc, 0x9c, 0xdb, 0x17, 0x81, 0xa9, 0xd7, 0xd5, 0x01, - 0x25, 0x6b, 0x23, 0x62, 0xe3, 0xb1, 0xa9, 0x9d, 0xd3, 0xfb, 0xca, 0xd7, - 0x1c, 0x95, 0xd4, 0xdd, 0x07, 0x1d, 0x07, 0x4d, 0xa9, 0x10, 0xba, 0x48, - 0x3d, 0xf7, 0x5b, 0x19, 0xcc, 0x8e, 0x1f, 0x03, 0x40, 0xe0, 0x0f, 0x28, - 0xf4, 0xcf, 0x3c, 0xf7, 0x07, 0x0d, 0x36, 0x4d, 0xd4, 0xc3, 0xa6, 0x02, - 0xb9, 0xe1, 0x49, 0xca, 0xb4, 0xd9, 0xa7, 0x4c, 0x3d, 0x1f, 0x81, 0xea, - 0x6e, 0x1b, 0xae, 0x0a, 0xd3, 0xcf, 0xc2, 0x9b, 0x1d, 0xc3, 0xa4, 0x12, - 0x3e, 0xc2, 0x6a, 0xc9, 0x50, 0xa6, 0x1b, 0xf8, 0xc9, 0xd6, 0xde, 0x15, - 0xb7, 0xd9, 0x17, 0xde, 0x25, 0x1c, 0x06, 0x08, 0x20, 0xd3, 0x5b, 0xa3, - 0x9e, 0xd1, 0xdb, 0xb6, 0xfc, 0x45, 0x94, 0x46, 0x3b, 0x99, 0x2c, 0xd5, - 0x2a, 0xdb, 0xd4, 0x1c, 0x27, 0x48, 0xd3, 0x1b, 0x44, 0x53, 0x31, 0xd7, - 0x70, 0x4b, 0x21, 0xfd, 0x53, 0x95, 0x17, 0x4e, 0x31, 0xa4, 0xbd, 0x51, - 0x4a, 0xbc, 0x91, 0x12, 0x0e, 0xb7, 0x72, 0x43, 0x9f, 0xa2, 0xd4, 0x53, - 0xbe, 0x9c, 0x21, 0xeb, 0x62, 0x14, 0x20, 0x5f, 0xd1, 0xb4, 0x3f, 0xb0, - 0x8a, 0x9f, 0x81, 0x25, 0xef, 0x63, 0xcc, 0x08, 0xba, 0x93, 0xf0, 0xa1, - 0x2e, 0x2a, 0xbd, 0xdf, 0xbb, 0x23, 0xc0, 0xb3, 0x0a, 0xc8, 0xdb, 0xbc, - 0x8e, 0x2b, 0x10, 0xce, 0x3b, 0x2b, 0x98, 0xf5, 0xc3, 0xea, 0xa4, 0x92, - 0xf7, 0x3b, 0xce, 0x88, 0x0c, 0xa9, 0xb0, 0x15, 0x00, 0xed, 0x6e, 0xb7, - 0x5c, 0xa6, 0xd5, 0xde, 0x0c, 0x7f, 0xe5, 0xc4, 0x0c, 0xd8, 0xd2, 0xb1, - 0x36, 0x37, 0xef, 0xfd, 0x0f, 0x3d, 0x3f, 0xdd, 0x47, 0xe0, 0xec, 0xe5, - 0x3b, 0xf4, 0x16, 0x55, 0x01, 0xec, 0x37, 0x4b, 0x47, 0x79, 0xb8, 0x5b, - 0x72, 0xbc, 0x25, 0x30, 0x01, 0xf2, 0xb6, 0xe9, 0xe7, 0x07, 0xc1, 0xc7, - 0xe3, 0x34, 0xdf, 0xbe, 0x0f, 0x44, 0xf8, 0x5b, 0x4b, 0x81, 0xbb, 0x29, - 0x06, 0x09, 0x20, 0xda, 0x26, 0x2e, 0x32, 0xe8, 0x1a, 0x16, 0x14, 0xcf, - 0xac, 0x29, 0x40, 0xdc, 0x0a, 0xc9, 0x1a, 0xc9, 0x36, 0x9e, 0x59, 0x0e, - 0x32, 0x3b, 0x1a, 0x29, 0xb2, 0x23, 0x1a, 0xe1, 0xe6, 0xeb, 0x34, 0x1f, - 0x04, 0x5c, 0xb3, 0x52, 0x56, 0x0b, 0x59, 0xfe, 0xb2, 0xf6, 0x9b, 0xae, - 0x08, 0xe4, 0x36, 0x1c, 0x2f, 0x14, 0x56, 0xd5, 0x05, 0xf7, 0xea, 0x39, - 0x5e, 0x10, 0xa6, 0xf7, 0x25, 0x6a, 0xe4, 0xf0, 0x2b, 0x67, 0x31, 0xf3, - 0xae, 0xe5, 0x55, 0xe7, 0xc4, 0x07, 0xf8, 0x20, 0x9d, 0x7f, 0x41, 0x53, - 0xba, 0xad, 0x59, 0xb0, 0x7a, 0xec, 0xf9, 0xe2, 0xde, 0x54, 0xf5, 0x4a, - 0xbf, 0x27, 0xf8, 0xfa, 0xc6, 0xdc, 0xee, 0x10, 0x16, 0x10, 0x1b, 0x0c, - 0xe4, 0x04, 0xae, 0x03, 0x5b, 0x2c, 0xfb, 0xe0, 0x1f, 0x3e, 0x07, 0xe2, - 0x65, 0x5d, 0x7a, 0xcf, 0xe4, 0x28, 0xfb, 0x1e, 0x18, 0xa8, 0x19, 0xef, - 0xe3, 0x30, 0x36, 0xd1, 0x19, 0x0a, 0x10, 0x6e, 0xfb, 0x81, 0x1e, 0x2e, - 0xa3, 0xe0, 0x28, 0xd1, 0x08, 0xab, 0xac, 0x4f, 0xf9, 0x78, 0x87, 0x55, - 0xfc, 0x84, 0x0c, 0x35, 0x46, 0xc0, 0x73, 0xae, 0xeb, 0x1d, 0x7b, 0x3b, - 0xa2, 0xa2, 0x00, 0x43, 0xb4, 0x45, 0x9e, 0x48, 0x22, 0x99, 0xae, 0x0e, - 0xf8, 0x1b, 0x13, 0x2e, 0x55, 0x02, 0x79, 0x16, 0x5c, 0xcd, 0xcf, 0xae, - 0xcd, 0x25, 0x4b, 0x4c, 0x13, 0xc2, 0xd7, 0x2e, 0x52, 0xf2, 0xff, 0xf1, - 0x3c, 0x03, 0x40, 0x02, 0x50, 0x41, 0x4d, 0xdf, 0xe7, 0x9f, 0xcc, 0x3b, - 0xf6, 0xf2, 0x3e, 0xc3, 0x1f, 0xc3, 0xa4, 0xfa, 0xad, 0x6b, 0x35, 0x7f, - 0xf7, 0x26, 0xe4, 0xeb, 0x2a, 0x36, 0x11, 0xc0, 0x3b, 0xc2, 0xcb, 0x1a, - 0x09, 0xc1, 0xe8, 0x5e, 0x2a, 0x33, 0xda, 0x7f, 0x2a, 0xed, 0x25, 0x2d, - 0x0c, 0x46, 0xd8, 0x0c, 0xe0, 0x18, 0x47, 0xff, 0xd7, 0x01, 0x32, 0xc6, - 0x3d, 0x52, 0x0a, 0xc6, 0x35, 0xb0, 0x27, 0xc8, 0x47, 0x54, 0xd6, 0x05, - 0xac, 0x16, 0x2f, 0x04, 0x27, 0x43, 0xaf, 0x11, 0x9e, 0xd7, 0xf1, 0xc5, - 0xc9, 0x53, 0x44, 0xfe, 0xd6, 0xed, 0x3a, 0xc3, 0xd2, 0x0e, 0x3e, 0xb9, - 0x92, 0x9f, 0x36, 0xcb, 0xdf, 0xee, 0x06, 0xa1, 0x81, 0xdb, 0xb2, 0x3d, - 0x13, 0x11, 0xe5, 0xf2, 0x12, 0xff, 0x67, 0x95, 0x2b, 0x39, 0xbf, 0x78, - 0xac, 0x23, 0xb9, 0x28, 0x11, 0xe9, 0xfd, 0x13, 0x15, 0xed, 0x26, 0x15, - 0xef, 0x4b, 0xeb, 0x3a, 0xc0, 0xce, 0x52, 0x2e, 0xde, 0x18, 0xbd, 0x1f, - 0x04, 0x2e, 0xfc, 0x8f, 0xd0, 0xf5, 0x9e, 0xf0, 0x96, 0x28, 0x0e, 0x4b, - 0xbe, 0x00, 0x21, 0x8d, 0x05, 0x7f, 0x28, 0xf4, 0xee, 0xc4, 0x5b, 0x22, - 0xf5, 0xf7, 0xe0, 0x4a, 0xe4, 0xea, 0xe9, 0xba, 0xda, 0x33, 0xb3, 0xbc, - 0xeb, 0x10, 0x31, 0xe0, 0xb7, 0xbf, 0xd6, 0x45, 0x2c, 0xff, 0xbb, 0x08, - 0x09, 0xea, 0xe8, 0xd6, 0x1e, 0xe6, 0x22, 0xa9, 0xb7, 0x47, 0xeb, 0x47, - 0x9d, 0xe1, 0xe5, 0x2e, 0xf8, 0xdb, 0xf5, 0xfd, 0xb6, 0xbd, 0x17, 0xca, - 0xf3, 0xd5, 0x56, 0xcc, 0x85, 0xf4, 0xb4, 0xda, 0x6e, 0x7a, 0x27, 0xf8, - 0xde, 0xc1, 0x14, 0xe3, 0xf6, 0xd6, 0x1f, 0x26, 0x28, 0xb0, 0x9f, 0xde, - 0xf8, 0x65, 0x08, 0x07, 0xc9, 0x12, 0x22, 0xe0, 0x2b, 0xfd, 0x30, 0xba, - 0xca, 0x27, 0x04, 0xef, 0x45, 0xdf, 0x68, 0xce, 0x2e, 0xef, 0xf6, 0x37, - 0x3c, 0xce, 0xc5, 0xfe, 0x12, 0x77, 0x01, 0xe9, 0xc3, 0xe2, 0x3b, 0x51, - 0xfd, 0x4d, 0x81, 0x46, 0x3a, 0x09, 0x72, 0x48, 0xe8, 0xca, 0xf6, 0xe3, - 0xe5, 0x47, 0x0c, 0xe1, 0xc9, 0x49, 0xeb, 0x61, 0x30, 0x3b, 0xae, 0x27, - 0x28, 0x31, 0x3c, 0x0c, 0x14, 0xd7, 0x20, 0xc5, 0x6a, 0x53, 0xde, 0x2e, - 0x6b, 0x10, 0xad, 0x12, 0x4f, 0x52, 0xc5, 0x44, 0x06, 0x97, 0x31, 0xa7, - 0x93, 0x2c, 0xd7, 0x2d, 0xbc, 0xe5, 0x40, 0x4e, 0xec, 0x7a, 0x61, 0x0d, - 0x1f, 0xf7, 0x09, 0xcb, 0x10, 0x19, 0x45, 0xe3, 0x07, 0x95, 0x7f, 0x5a, - 0xbb, 0x12, 0x31, 0x25, 0x9d, 0xd5, 0x0b, 0x6b, 0x47, 0xbd, 0xda, 0x18, - 0x4f, 0xcd, 0x75, 0x19, 0xf8, 0xec, 0x04, 0xbb, 0x41, 0x31, 0x4c, 0x22, - 0x04, 0xe5, 0xae, 0xe6, 0xbe, 0x49, 0xe9, 0x2c, 0xb5, 0x28, 0xe9, 0xf5, - 0xe2, 0xf4, 0xcc, 0xdc, 0xa9, 0x1a, 0xf0, 0x04, 0x13, 0xb3, 0x2a, 0x54, - 0x3e, 0xca, 0xe8, 0xae, 0xee, 0x53, 0x81, 0xdf, 0x22, 0x84, 0x09, 0xc9, - 0xe6, 0xbf, 0xc5, 0xf3, 0x1b, 0x25, 0xd6, 0xec, 0x24, 0xc0, 0x05, 0xf0, - 0x2b, 0xf6, 0xcd, 0xcf, 0x39, 0x52, 0x6c, 0xa7, 0x01, 0x12, 0x0c, 0x32, - 0x18, 0xf0, 0x06, 0x43, 0x24, 0xec, 0xfe, 0x18, 0x04, 0x62, 0xf8, 0xb6, - 0xbd, 0x9f, 0x13, 0xb8, 0xd2, 0x5e, 0xf8, 0x4f, 0xfd, 0x2a, 0x1c, 0xce, - 0x69, 0xbc, 0xc0, 0x5d, 0x0c, 0x96, 0x7f, 0x90, 0x00, 0x37, 0x1b, 0xb1, - 0xfb, 0xd2, 0x0a, 0xee, 0x38, 0x55, 0xa7, 0x02, 0xdd, 0x9c, 0x39, 0x49, - 0xce, 0x36, 0x2a, 0x12, 0x4a, 0x5e, 0xcc, 0xd8, 0xde, 0xe5, 0x48, 0x05, - 0xc9, 0xcc, 0x3e, 0x17, 0xc9, 0x50, 0xd0, 0x1f, 0xff, 0x16, 0x7f, 0x16, - 0xcb, 0xd2, 0xdd, 0xee, 0x09, 0x05, 0x69, 0x11, 0x48, 0x95, 0x3d, 0x2f, - 0x04, 0xdc, 0x49, 0xfa, 0xef, 0x32, 0x28, 0x20, 0xf6, 0x12, 0xd2, 0x0f, - 0x34, 0x08, 0xff, 0x3d, 0xeb, 0x6c, 0x14, 0x4b, 0x11, 0xf0, 0xc9, 0x60, - 0x31, 0x32, 0xe7, 0x6a, 0xe5, 0xcc, 0x14, 0x58, 0xba, 0x0d, 0x05, 0xa7, - 0x25, 0xc9, 0xda, 0x9b, 0x20, 0x92, 0x05, 0x7f, 0xcf, 0xee, 0x20, 0x1f, - 0xc1, 0xfa, 0x9b, 0x22, 0x3a, 0x4c, 0x34, 0xd4, 0xcf, 0xa1, 0x69, 0xbe, - 0xe1, 0xb4, 0xfa, 0x29, 0xb1, 0x57, 0x3e, 0x3d, 0xf3, 0x13, 0xe7, 0x02, - 0x57, 0x1a, 0xf0, 0xd5, 0xc9, 0x01, 0xbf, 0xd4, 0xdd, 0xff, 0x2e, 0xcc, - 0xdd, 0xc9, 0xe7, 0x08, 0x24, 0xcc, 0x3e, 0xf4, 0xf3, 0xd4, 0xc3, 0xa4, - 0xa9, 0x3f, 0x2c, 0x01, 0xc2, 0xc1, 0x3f, 0xf8, 0xcd, 0xd6, 0x53, 0x5c, - 0x37, 0x33, 0xde, 0x27, 0x81, 0x37, 0xd3, 0x09, 0x21, 0xce, 0x4f, 0xf1, - 0x22, 0x0b, 0x0b, 0xc0, 0x09, 0x9c, 0x52, 0x45, 0x3b, 0x0c, 0xe3, 0x2a, - 0x73, 0xde, 0x40, 0xd4, 0x3a, 0xc4, 0x3b, 0x54, 0x24, 0x57, 0xda, 0x24, - 0x44, 0xbf, 0x4f, 0x21, 0x2e, 0xbf, 0x0c, 0xb5, 0x0a, 0x30, 0x1f, 0x47, - 0xb3, 0x5e, 0x07, 0xa0, 0x31, 0xe2, 0x10, 0x21, 0xb6, 0x1d, 0x34, 0xcf, - 0xf7, 0x60, 0x2d, 0xec, 0x0d, 0xb4, 0x26, 0xbe, 0x4e, 0xf6, 0x6e, 0xe8, - 0xca, 0x81, 0x19, 0x57, 0x1b, 0x3f, 0xf2, 0x41, 0xb9, 0x42, 0xa4, 0xbc, - 0xb3, 0x1f, 0xeb, 0x3b, 0x0b, 0xcb, 0x10, 0x4c, 0xcd, 0x9b, 0xeb, 0x0d, - 0xcd, 0x19, 0x8b, 0xcb, 0xda, 0xf2, 0xf5, 0x4f, 0x3d, 0xe3, 0xd0, 0x5f, - 0xa5, 0xbb, 0xc4, 0xd9, 0x12, 0x31, 0xa9, 0xe8, 0x32, 0x50, 0xf6, 0xb4, - 0x3c, 0x61, 0x0b, 0x02, 0x52, 0xb7, 0x81, 0xda, 0x4b, 0xed, 0xee, 0xc8, - 0xec, 0xb7, 0xe5, 0x06, 0x0b, 0xb9, 0x43, 0x39, 0xea, 0xbc, 0xbb, 0xb3, - 0x2e, 0x32, 0xf2, 0xd9, 0x6a, 0xf1, 0x39, 0xe2, 0x17, 0x5f, 0xd5, 0x26, - 0xaa, 0x08, 0xf0, 0x26, 0xa0, 0xf8, 0xc5, 0x3c, 0xe1, 0x14, 0xe6, 0xcb, - 0x0e, 0x2d, 0x17, 0x29, 0x38, 0xd5, 0x02, 0xf6, 0xf8, 0xe1, 0xaa, 0xa8, - 0xeb, 0xb8, 0x78, 0x65, 0x0b, 0x52, 0xb0, 0x3c, 0x29, 0xfe, 0xc2, 0xee, - 0xd9, 0xf3, 0x25, 0x29, 0x4a, 0x48, 0x0d, 0xf9, 0x8e, 0x3b, 0xd2, 0x3e, - 0xb0, 0x5f, 0xdd, 0xaf, 0xcc, 0xc6, 0x51, 0xb7, 0xe7, 0x3a, 0x7b, 0x32, - 0xa2, 0x7f, 0xa2, 0x60, 0xff, 0x3d, 0xbd, 0xa3, 0x68, 0xc1, 0x02, 0xba, - 0x25, 0xd3, 0xd9, 0xa9, 0x46, 0xc8, 0xeb, 0x01, 0xcf, 0x63, 0x3d, 0x29, - 0xdb, 0x8e, 0x3b, 0x40, 0xda, 0x3c, 0xfc, 0xa5, 0xad, 0xe9, 0xfb, 0x29, - 0x7f, 0x52, 0xfc, 0x28, 0xcb, 0x8d, 0x0b, 0x9c, 0x0f, 0x4d, 0x2a, 0xf4, - 0x14, 0x9f, 0xcd, 0xd1, 0x51, 0xbb, 0x1e, 0x07, 0xb3, 0xcb, 0xeb, 0xae, - 0x5f, 0x43, 0xfe, 0x2f, 0x15, 0x01, 0x49, 0xd7, 0x47, 0x27, 0xfd, 0x1e, - 0xe9, 0xc6, 0x0e, 0xad, 0xd8, 0x40, 0xd9, 0x53, 0x02, 0x46, 0xce, 0x50, - 0x2c, 0x38, 0x3f, 0xbb, 0xc1, 0xb0, 0xde, 0xa2, 0xda, 0x99, 0xd6, 0x1c, - 0xe5, 0xe7, 0xc0, 0x19, 0x75, 0x09, 0x18, 0x19, 0x34, 0xda, 0xa2, 0xfe, - 0xe4, 0x41, 0xf1, 0xed, 0x1e, 0xc9, 0xfb, 0x36, 0x05, 0x54, 0x4c, 0xff, - 0xa0, 0x1a, 0xb5, 0x2c, 0xfb, 0x48, 0x2c, 0x08, 0xc3, 0xfb, 0xf4, 0x20, - 0x32, 0xb6, 0x52, 0x4f, 0xf6, 0xce, 0xee, 0x10, 0x15, 0x4a, 0xfe, 0x7f, - 0x22, 0xbe, 0xb1, 0x0b, 0xfe, 0x1b, 0x41, 0x04, 0x48, 0x34, 0xdf, 0x40, - 0xf4, 0xd9, 0x2e, 0x30, 0xd8, 0x1f, 0xe6, 0xf7, 0xca, 0xdd, 0x1c, 0xef, - 0xe9, 0x02, 0xe7, 0xdb, 0xf8, 0xa5, 0x03, 0x40, 0xc9, 0x27, 0xfd, 0x19, - 0x16, 0xe4, 0x4b, 0x27, 0xf2, 0xe4, 0x2c, 0x14, 0x2a, 0xd8, 0xd2, 0x08, - 0xcf, 0xd6, 0xcb, 0xf1, 0x1c, 0x36, 0xcd, 0x43, 0xbb, 0xbb, 0x6e, 0x1f, - 0x1e, 0xff, 0x06, 0xcf, 0xdf, 0xad, 0x7f, 0x0d, 0x4f, 0x45, 0xf4, 0xe6, - 0x47, 0xa3, 0xa9, 0x74, 0x34, 0xb0, 0xd7, 0x1b, 0xc0, 0xb4, 0x71, 0x02, - 0xf3, 0xf9, 0x20, 0x70, 0x18, 0xd4, 0x69, 0x9a, 0x29, 0x68, 0x2a, 0xb9, - 0x38, 0xec, 0xd8, 0x00, 0xe2, 0x4f, 0x25, 0xc1, 0x3f, 0xef, 0x1f, 0x53, - 0x3c, 0x2c, 0x9c, 0x17, 0x0c, 0x11, 0x18, 0xc6, 0xd8, 0x02, 0xe3, 0xc2, - 0xda, 0x7f, 0xf0, 0x6f, 0xc3, 0x34, 0xb4, 0x12, 0x0e, 0xf5, 0x6b, 0xca, - 0x31, 0x35, 0x1a, 0x38, 0x20, 0xc2, 0x26, 0x62, 0xf3, 0x1f, 0xbb, 0x43, - 0xbb, 0xf8, 0x5c, 0xdd, 0x94, 0x18, 0xf6, 0x3c, 0x2e, 0x46, 0xf1, 0x5c, - 0x9e, 0x38, 0xbb, 0x4c, 0x3f, 0x5d, 0x27, 0xcc, 0xb9, 0x81, 0x03, 0xc4, - 0xda, 0xaa, 0xcc, 0xda, 0x15, 0xc5, 0x9f, 0x34, 0x02, 0xbe, 0xad, 0x42, - 0x12, 0x2f, 0xd0, 0xe4, 0x0f, 0xb8, 0xd5, 0xc7, 0xd2, 0xe4, 0x1f, 0xfc, - 0xf6, 0x23, 0x24, 0xbd, 0x27, 0xd3, 0xfc, 0x4d, 0xf5, 0xf7, 0xf7, 0x0b, - 0xa0, 0x5d, 0x52, 0xd5, 0x6a, 0x9e, 0xc6, 0x0d, 0x1d, 0x05, 0x27, 0x15, - 0x81, 0xcd, 0xed, 0x36, 0x46, 0x51, 0x17, 0xc3, 0xe0, 0x67, 0xe3, 0xea, - 0x3d, 0x25, 0x28, 0x40, 0x22, 0x98, 0xb6, 0x0f, 0xe2, 0x58, 0x4c, 0x11, - 0xc9, 0x36, 0xfd, 0xdf, 0xee, 0x12, 0x29, 0x4d, 0x24, 0xec, 0x65, 0x43, - 0xb5, 0xf2, 0xfe, 0xda, 0x2a, 0x91, 0x06, 0xd4, 0x52, 0x00, 0xe0, 0xa1, - 0xe4, 0x96, 0x2f, 0x06, 0x0e, 0xed, 0xda, 0xaa, 0x29, 0x23, 0x0b, 0x61, - 0x44, 0x63, 0x52, 0xc0, 0x2e, 0xf0, 0x4f, 0xaf, 0x1e, 0x61, 0x0a, 0xef, - 0x06, 0x18, 0x28, 0xd0, 0x0a, 0x39, 0xea, 0xef, 0xa7, 0x29, 0xc1, 0x28, - 0x35, 0xd4, 0x12, 0x54, 0xa6, 0x11, 0x50, 0x16, 0xdc, 0x28, 0x09, 0x23, - 0x09, 0xbd, 0x29, 0xbc, 0x4a, 0x01, 0xc9, 0x7f, 0xbd, 0x11, 0xcd, 0x35, - 0x8a, 0x40, 0x4f, 0xa5, 0xfa, 0xc2, 0x11, 0x6e, 0x7f, 0xdf, 0x94, 0x02, - 0xed, 0x1b, 0xc3, 0xb8, 0xda, 0xd4, 0xdf, 0xfa, 0xd9, 0x9e, 0xea, 0x1f, - 0x6e, 0x1f, 0x29, 0xbd, 0xc1, 0xef, 0x35, 0x90, 0xa3, 0x50, 0x1d, 0x74, - 0x9d, 0x3f, 0xca, 0xb1, 0xbb, 0xdc, 0xac, 0xc8, 0x34, 0x0a, 0x56, 0x4a, - 0xce, 0x73, 0xcb, 0x1f, 0xc8, 0x3f, 0xc8, 0x0b, 0x2a, 0xf5, 0x31, 0x7d, - 0x57, 0xd4, 0x61, 0xf1, 0xd0, 0x72, 0x30, 0x2d, 0xf6, 0xec, 0xeb, 0x44, - 0x15, 0x37, 0x56, 0x23, 0xc0, 0x12, 0x1b, 0xff, 0xc1, 0x9d, 0x0a, 0x0c, - 0xdb, 0x35, 0x7f, 0x3a, 0x02, 0x16, 0xd5, 0x24, 0x4c, 0xd9, 0xcb, 0x22, - 0xea, 0xa0, 0xd4, 0x27, 0x4b, 0xf6, 0xba, 0x05, 0xaf, 0xa1, 0x13, 0x45, - 0x56, 0x36, 0x1e, 0x42, 0xac, 0xb0, 0x50, 0x2d, 0xf9, 0x94, 0xa6, 0xcd, - 0x39, 0xdd, 0x24, 0xe3, 0xf5, 0xc0, 0xdd, 0xa6, 0xdb, 0xf1, 0xff, 0xfc, - 0x00, 0x26, 0xf2, 0x24, 0x0f, 0x00, 0xf4, 0x3b, 0xf9, 0xfb, 0xcd, 0x22, - 0xe3, 0x06, 0x81, 0x19, 0xd4, 0x4a, 0x08, 0xe9, 0xe5, 0x4c, 0xf6, 0x1d, - 0xcf, 0xd5, 0x01, 0xdd, 0xec, 0xe7, 0xcf, 0x20, 0xf3, 0xf6, 0x0d, 0xfc, - 0x3c, 0xe2, 0xf4, 0x0b, 0x0f, 0x07, 0xfd, 0xd2, 0xf9, 0x33, 0xc8, 0x57, - 0xd4, 0xf7, 0x08, 0x28, 0xda, 0x49, 0x0e, 0x18, 0xf5, 0x12, 0x35, 0xa9, - 0xce, 0xd4, 0x04, 0xda, 0x7f, 0x6a, 0x44, 0x57, 0xfc, 0xfd, 0xfb, 0xfe, - 0x31, 0xcb, 0x2e, 0x26, 0xf7, 0xf4, 0x58, 0xf4, 0xe8, 0xfe, 0xea, 0x3f, - 0x0a, 0xfd, 0x16, 0x12, 0xbc, 0x43, 0xce, 0x1a, 0x60, 0xaf, 0x6a, 0x1b, - 0xcc, 0x47, 0x1e, 0x4a, 0x00, 0x29, 0xb4, 0x26, 0x21, 0x02, 0xe3, 0x36, - 0xd6, 0xf1, 0x31, 0xc9, 0xac, 0x1b, 0x27, 0xd6, 0xab, 0xda, 0x2b, 0xe8, - 0xa5, 0xf2, 0x28, 0x39, 0xaf, 0xc5, 0xda, 0xbb, 0x4f, 0x76, 0x95, 0x37, - 0xf2, 0x0d, 0x57, 0x7d, 0x58, 0xe2, 0x0d, 0x08, 0x06, 0x08, 0xe5, 0x2a, - 0x19, 0x0f, 0xb6, 0x41, 0xb6, 0xff, 0xb2, 0xd6, 0xb1, 0xfa, 0x81, 0xd2, - 0xb2, 0x09, 0x25, 0x41, 0x10, 0xd4, 0x19, 0x03, 0x05, 0xa7, 0x98, 0x0b, - 0xb2, 0xee, 0xa3, 0xac, 0xcd, 0x36, 0x0a, 0xf1, 0x47, 0xa3, 0xf8, 0x22, - 0xde, 0x97, 0xca, 0x94, 0x27, 0xce, 0x5f, 0xc1, 0x41, 0xe4, 0xa4, 0x08, - 0x1a, 0xda, 0x09, 0x8b, 0xa7, 0xd5, 0x12, 0xe6, 0x20, 0x51, 0x65, 0x34, - 0x4c, 0xa0, 0xe0, 0xfd, 0x78, 0xf6, 0xfa, 0xac, 0xc5, 0xb3, 0x5c, 0x37, - 0x2e, 0xc0, 0x5e, 0xe7, 0x2c, 0x2f, 0x7f, 0xd6, 0x10, 0x0d, 0xdd, 0xf2, - 0x32, 0xeb, 0xe3, 0xc4, 0x4f, 0xc5, 0x60, 0xe4, 0xf0, 0xcb, 0x39, 0xe1, - 0x87, 0x65, 0x60, 0x42, 0xa7, 0x48, 0x21, 0x29, 0xd6, 0xf8, 0xd8, 0x6d, - 0x10, 0x06, 0x30, 0x08, 0xc6, 0x0b, 0xdf, 0x20, 0xd1, 0xf1, 0xc2, 0x4a, - 0xe0, 0x3c, 0xf3, 0xd8, 0xe4, 0x20, 0x04, 0x0e, 0x05, 0xe8, 0xf3, 0x20, - 0xca, 0xf6, 0x17, 0x00, 0xd8, 0xea, 0x52, 0xe2, 0xe9, 0x27, 0x52, 0x08, - 0x2f, 0x81, 0xff, 0x24, 0xe4, 0x12, 0xa5, 0x2b, 0xdd, 0xf0, 0x0a, 0xb5, - 0x31, 0xc4, 0xeb, 0xfe, 0x05, 0x61, 0x10, 0x41, 0xd9, 0xd7, 0x24, 0x25, - 0xc2, 0xd3, 0xd2, 0x3e, 0xbb, 0xfd, 0x00, 0xed, 0xb8, 0xce, 0xf5, 0xaa, - 0xda, 0x0e, 0x3b, 0xa4, 0x30, 0xe7, 0xd4, 0x43, 0xec, 0x4b, 0xed, 0x30, - 0xf2, 0x06, 0x98, 0x57, 0xf5, 0xf2, 0xe9, 0xc1, 0x8b, 0xe1, 0x58, 0xf3, - 0x17, 0x30, 0x23, 0xed, 0xf1, 0x2b, 0x88, 0xbd, 0xc3, 0xaa, 0xf4, 0xb8, - 0x47, 0xdb, 0x7f, 0x18, 0x8c, 0x66, 0x0d, 0xbd, 0x7a, 0x65, 0x6f, 0x01, - 0x56, 0xdc, 0x02, 0x31, 0x98, 0xb9, 0xf4, 0x55, 0xd3, 0xbd, 0x1d, 0xcf, - 0x01, 0x1c, 0x35, 0xfa, 0x12, 0xbc, 0x19, 0x3e, 0x29, 0x51, 0x95, 0x4a, - 0x03, 0x31, 0xf1, 0xde, 0xcf, 0xda, 0xc1, 0x24, 0x18, 0x12, 0x3e, 0xe2, - 0xd8, 0x0e, 0x3d, 0xfe, 0x4c, 0xd8, 0xf9, 0x05, 0x24, 0xfc, 0x05, 0x2d, - 0xf7, 0xe9, 0x21, 0x05, 0xb6, 0xaf, 0xd7, 0xd9, 0x17, 0xfb, 0xae, 0x25, - 0xf1, 0xc5, 0x11, 0x0f, 0x3c, 0x5f, 0x35, 0x7f, 0x0c, 0x05, 0x21, 0xd9, - 0xb4, 0xfd, 0x43, 0xc2, 0xe5, 0x7f, 0x23, 0x3f, 0xe0, 0x18, 0x47, 0xfa, - 0xea, 0x14, 0xa2, 0x2c, 0x32, 0xda, 0x26, 0xc8, 0xee, 0x3b, 0x2b, 0xc6, - 0xc7, 0xc5, 0xcb, 0xd4, 0xe4, 0xd2, 0x01, 0xce, 0x57, 0x59, 0xb5, 0x5e, - 0xaf, 0xf4, 0x15, 0x1d, 0xd1, 0x90, 0xb7, 0x3c, 0xa6, 0x4a, 0x3d, 0x64, - 0xa9, 0x2d, 0x49, 0xa7, 0xc3, 0x5d, 0x9a, 0x71, 0xef, 0x1d, 0x9f, 0x1b, - 0x4c, 0x01, 0x1e, 0x44, 0xa1, 0x50, 0xbf, 0xd8, 0xa4, 0x45, 0x01, 0x6c, - 0xce, 0xe2, 0xa3, 0xd6, 0x43, 0x3d, 0x41, 0x8f, 0x0b, 0x36, 0x3a, 0x8d, - 0x00, 0x02, 0x2d, 0x4c, 0xe2, 0x9f, 0x23, 0x57, 0xc3, 0x10, 0x1f, 0xb2, - 0xdd, 0x33, 0x50, 0x10, 0xec, 0xe9, 0x54, 0xad, 0xeb, 0xe6, 0xf4, 0x47, - 0xef, 0xdc, 0xc0, 0xf3, 0x76, 0xf5, 0x50, 0xfc, 0x37, 0x35, 0xeb, 0x7f, - 0x2e, 0xae, 0xc0, 0x06, 0xe3, 0x34, 0x02, 0x59, 0xaf, 0x38, 0xbf, 0x03, - 0x65, 0xfc, 0x12, 0xca, 0x27, 0xeb, 0xff, 0x46, 0x14, 0x1f, 0xee, 0xf4, - 0x4a, 0xbc, 0xf0, 0x4e, 0xfb, 0xe2, 0x08, 0x4f, 0xf2, 0x44, 0xab, 0xe3, - 0xc4, 0x17, 0xf1, 0xe6, 0x35, 0x95, 0x1b, 0xcb, 0x08, 0x81, 0xfd, 0x1c, - 0xb5, 0xf0, 0xa4, 0xe0, 0xe2, 0x06, 0x2e, 0xe6, 0xce, 0xce, 0xe4, 0xbe, - 0x22, 0x51, 0xe0, 0xd1, 0x20, 0x08, 0x40, 0xf5, 0xbb, 0x40, 0xee, 0x34, - 0xe4, 0x6a, 0x12, 0x41, 0xa3, 0x00, 0xee, 0x1c, 0xf9, 0x32, 0x0f, 0xc9, - 0x63, 0x1c, 0x62, 0xb6, 0xc9, 0xc2, 0xee, 0xc7, 0x31, 0x27, 0x21, 0x30, - 0x4a, 0x2f, 0xff, 0x17, 0xe2, 0x14, 0x05, 0x4a, 0x4d, 0x28, 0x7f, 0x37, - 0xfe, 0xcf, 0x28, 0xcf, 0x19, 0x2e, 0xae, 0x16, 0x25, 0xf5, 0x24, 0xeb, - 0x2c, 0x26, 0x34, 0x4a, 0x92, 0xee, 0x71, 0xeb, 0xec, 0x2e, 0x87, 0xc2, - 0xdf, 0x19, 0xc8, 0x33, 0x4d, 0x39, 0xb4, 0x43, 0xd4, 0x56, 0xff, 0xff, - 0xce, 0xbe, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xda, 0xbf, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, - 0xc0, 0x02, 0x00, 0x00, 0x9d, 0xd4, 0xdb, 0x26, 0x09, 0x1a, 0xcc, 0xe8, - 0xe4, 0xf4, 0x13, 0x10, 0x37, 0xe0, 0x68, 0xe8, 0x3d, 0x02, 0xad, 0xb2, - 0x30, 0x52, 0x39, 0xd0, 0x1c, 0xd8, 0x51, 0x42, 0x39, 0x60, 0x89, 0x15, - 0xa6, 0xe5, 0x0c, 0xd7, 0x5b, 0x26, 0xff, 0xec, 0x2a, 0xa4, 0x1d, 0x0d, - 0x3d, 0x99, 0x05, 0x17, 0xc4, 0x3e, 0xb0, 0x31, 0xe6, 0xd5, 0xf2, 0xd8, - 0xc0, 0x15, 0xbe, 0x74, 0xe7, 0x47, 0x03, 0xff, 0xd2, 0xd9, 0xd8, 0xf0, - 0xbd, 0x41, 0xda, 0xe1, 0xe8, 0x3e, 0x12, 0x00, 0x0b, 0xd3, 0x40, 0xd2, - 0x35, 0xf8, 0xca, 0x0f, 0x19, 0x00, 0x1a, 0xff, 0x35, 0x15, 0x49, 0x1b, - 0xfb, 0x4f, 0xab, 0xf2, 0xe1, 0xc1, 0x08, 0x16, 0x2f, 0xfe, 0xee, 0xe5, - 0x0d, 0xeb, 0x64, 0xcf, 0x00, 0xa0, 0x0d, 0x21, 0xd2, 0x3c, 0xdf, 0x42, - 0x11, 0x32, 0xdc, 0x9c, 0xd8, 0x27, 0xc7, 0x32, 0xee, 0x30, 0x59, 0xe1, - 0xd1, 0xc6, 0xb2, 0xd8, 0xdf, 0x04, 0xfa, 0xa8, 0xee, 0x25, 0x09, 0x0a, - 0x41, 0xe0, 0x10, 0x98, 0x15, 0x0a, 0xdd, 0xd9, 0xd6, 0x05, 0x2b, 0xc6, - 0x09, 0x2a, 0xf8, 0x02, 0x44, 0x24, 0xf9, 0xee, 0xce, 0xe8, 0x2e, 0xf6, - 0x23, 0x26, 0x20, 0xd1, 0x03, 0xd3, 0x3e, 0xe8, 0x4e, 0xf6, 0x1f, 0x02, - 0x22, 0x09, 0xfc, 0x46, 0x34, 0xcd, 0x1f, 0xf8, 0xde, 0x1b, 0xd8, 0x2e, - 0xf9, 0x1c, 0x0e, 0xe6, 0xf5, 0xd0, 0x19, 0xfc, 0xe0, 0x1f, 0xce, 0xc9, - 0xc3, 0xe3, 0xfe, 0x20, 0x10, 0x00, 0xe4, 0x9e, 0x1d, 0xd9, 0x01, 0x1f, - 0x06, 0x02, 0xd8, 0x1a, 0x19, 0x09, 0xe9, 0xe0, 0xfa, 0xf5, 0xf6, 0x12, - 0xd4, 0x07, 0x1f, 0xc4, 0xf6, 0x20, 0x07, 0xe4, 0x1d, 0x07, 0x3e, 0xe8, - 0xf4, 0x11, 0xf9, 0x23, 0xdd, 0xe9, 0x19, 0x15, 0xff, 0xce, 0x05, 0xdc, - 0x15, 0x2a, 0x0a, 0x27, 0x1c, 0x31, 0x15, 0xf4, 0xfe, 0xd1, 0xdd, 0xbd, - 0xbe, 0x1d, 0xe8, 0xb3, 0xc6, 0x03, 0x05, 0xe6, 0x2e, 0xfa, 0x06, 0xde, - 0x46, 0xf6, 0x0b, 0x20, 0xcc, 0x22, 0x3c, 0xe7, 0x37, 0x35, 0x0e, 0x0a, - 0x08, 0xe1, 0x08, 0xdb, 0x04, 0x02, 0x13, 0x23, 0x2b, 0x29, 0x4f, 0x05, - 0x33, 0xcc, 0xfd, 0x03, 0x12, 0xce, 0x21, 0x1e, 0xc7, 0x0b, 0xc3, 0x1d, - 0x01, 0xd0, 0x0d, 0xc0, 0xf7, 0xdf, 0xba, 0xfb, 0x06, 0x49, 0x18, 0x05, - 0xca, 0xe1, 0xe0, 0x07, 0xf7, 0x14, 0xd3, 0xc0, 0xe2, 0xe8, 0x2a, 0xff, - 0xf4, 0x0b, 0xbc, 0xba, 0x2c, 0xaa, 0xeb, 0xf5, 0x0c, 0x33, 0xf3, 0xf7, - 0x06, 0x07, 0x28, 0xeb, 0xee, 0xfc, 0x2b, 0x15, 0x0f, 0xe9, 0xfa, 0xf2, - 0xd1, 0xde, 0x36, 0x02, 0xfd, 0xf4, 0x26, 0x17, 0x37, 0xdc, 0xe7, 0x14, - 0xc8, 0x3a, 0xdb, 0x09, 0x34, 0xe9, 0xd8, 0xb4, 0xd7, 0x26, 0xfb, 0xf5, - 0x36, 0xd4, 0x3a, 0xf5, 0xd7, 0xb2, 0xe2, 0x18, 0xd1, 0xf8, 0xee, 0xb2, - 0xe3, 0x15, 0x2d, 0xdb, 0x03, 0x27, 0xcf, 0xb2, 0x01, 0xc9, 0xed, 0x1e, - 0x01, 0x45, 0xd1, 0x2d, 0x2e, 0x07, 0x52, 0x2e, 0xe6, 0x0e, 0x08, 0xe8, - 0xca, 0x13, 0xf4, 0x05, 0xd5, 0x1d, 0x56, 0xe1, 0x35, 0xd6, 0x30, 0xfd, - 0x19, 0xe8, 0xea, 0xc5, 0xdf, 0x32, 0x16, 0x29, 0x1e, 0xc5, 0x2e, 0xac, - 0x06, 0x0d, 0xbc, 0xe2, 0x19, 0xcb, 0xf8, 0xf0, 0xd4, 0x15, 0x17, 0xe3, - 0xf2, 0xd5, 0x12, 0xd4, 0xee, 0xef, 0x30, 0xf1, 0x2b, 0x27, 0xd5, 0xd0, - 0x45, 0xc6, 0x05, 0x53, 0xe8, 0x41, 0xd8, 0x19, 0x28, 0x31, 0xf0, 0xd8, - 0xf1, 0xd0, 0xe9, 0xcb, 0x2c, 0x3c, 0xd7, 0x23, 0x1b, 0xe0, 0x4c, 0x1d, - 0x11, 0xde, 0x41, 0xe7, 0x26, 0xe5, 0x30, 0x00, 0x0b, 0xe8, 0xd5, 0x1f, - 0xd0, 0xd2, 0x20, 0xbb, 0xe7, 0x52, 0xe7, 0x32, 0x15, 0xdb, 0x11, 0x2d, - 0xdd, 0xd5, 0xe0, 0xf0, 0xea, 0xe0, 0x23, 0x0d, 0x12, 0x1a, 0x14, 0xb5, - 0x25, 0xec, 0xee, 0xed, 0x20, 0xed, 0xe0, 0x2d, 0x18, 0x04, 0x13, 0xf1, - 0xdb, 0x51, 0xb8, 0x39, 0xf6, 0xe2, 0xe2, 0xda, 0xaf, 0x3d, 0xf1, 0xe8, - 0xce, 0x2a, 0x50, 0xe2, 0xf4, 0x06, 0x1b, 0x12, 0x38, 0xfd, 0x10, 0xe3, - 0xee, 0x58, 0xcb, 0x28, 0x18, 0x13, 0x2c, 0xb4, 0x1b, 0x33, 0xbc, 0xdd, - 0x40, 0x02, 0x30, 0x3a, 0x15, 0x9e, 0x16, 0xef, 0x29, 0xd9, 0xfd, 0xb0, - 0xdf, 0x4e, 0x1a, 0xc0, 0x04, 0xfa, 0x4e, 0xc6, 0x42, 0xb0, 0x1b, 0x2b, - 0x1e, 0x4e, 0xc6, 0xdc, 0xfa, 0x2d, 0x03, 0x13, 0xe6, 0xe4, 0x19, 0x02, - 0xc1, 0x5c, 0xe9, 0xd9, 0x95, 0xf0, 0x45, 0x02, 0x17, 0xc2, 0x1c, 0x1c, - 0xfe, 0xdc, 0xf9, 0xfc, 0x0a, 0x01, 0xfe, 0xf5, 0xe3, 0x1b, 0x45, 0xcf, - 0x2c, 0x51, 0xcc, 0xcb, 0x5f, 0xef, 0x28, 0x39, 0xcd, 0xaf, 0xf1, 0xca, - 0xeb, 0xdf, 0x1c, 0xb5, 0x19, 0x6d, 0x4d, 0x9b, 0xe8, 0xb0, 0x39, 0x00, - 0x0e, 0xf6, 0x2e, 0x04, 0x40, 0x29, 0xef, 0x2f, 0x1e, 0x4a, 0x2a, 0x3c, - 0xf6, 0x1d, 0xf0, 0xd9, 0xe4, 0x7c, 0x38, 0x15, 0xeb, 0xfb, 0x7f, 0xfd, - 0xcd, 0x02, 0x3a, 0xe1, 0x08, 0x3b, 0x4f, 0xb0, 0x44, 0x0b, 0xdd, 0x0c, - 0x16, 0xf4, 0xeb, 0x9a, 0x0b, 0x75, 0xb5, 0x0f, 0xfe, 0xe1, 0xe3, 0x35, - 0xb0, 0x5a, 0xff, 0xff, 0xaa, 0xc2, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, - 0x00, 0x01, 0x00, 0x00, 0x6c, 0x17, 0x00, 0x00, 0x7c, 0xf3, 0xff, 0xff, - 0x06, 0xee, 0xff, 0xff, 0xcd, 0x13, 0x00, 0x00, 0x26, 0x02, 0x00, 0x00, - 0x49, 0xfa, 0xff, 0xff, 0x17, 0xe2, 0xff, 0xff, 0x75, 0xfe, 0xff, 0xff, - 0xf3, 0x27, 0x00, 0x00, 0x8d, 0x0b, 0x00, 0x00, 0x52, 0xec, 0xff, 0xff, - 0xf5, 0x05, 0x00, 0x00, 0xef, 0x1b, 0x00, 0x00, 0x8a, 0xf8, 0xff, 0xff, - 0x62, 0xe4, 0xff, 0xff, 0x46, 0x2f, 0x00, 0x00, 0x47, 0x1b, 0x00, 0x00, - 0x3f, 0x2d, 0x00, 0x00, 0xa0, 0x0a, 0x00, 0x00, 0xa0, 0xf9, 0xff, 0xff, - 0x3b, 0xf4, 0xff, 0xff, 0x7e, 0xfc, 0xff, 0xff, 0xca, 0xed, 0xff, 0xff, - 0xa6, 0xfb, 0xff, 0xff, 0xa8, 0x0d, 0x00, 0x00, 0x8f, 0x19, 0x00, 0x00, - 0x9b, 0x21, 0x00, 0x00, 0x62, 0x0d, 0x00, 0x00, 0x46, 0xfb, 0xff, 0xff, - 0x73, 0xfc, 0xff, 0xff, 0x1b, 0x2c, 0x00, 0x00, 0x99, 0xe1, 0xff, 0xff, - 0x5e, 0xfc, 0xff, 0xff, 0x9a, 0x1d, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, - 0x1e, 0xf8, 0xff, 0xff, 0xae, 0xfc, 0xff, 0xff, 0x1b, 0x06, 0x00, 0x00, - 0x4d, 0x15, 0x00, 0x00, 0x32, 0x0c, 0x00, 0x00, 0x62, 0x0d, 0x00, 0x00, - 0x6f, 0x0d, 0x00, 0x00, 0x92, 0x05, 0x00, 0x00, 0x91, 0x12, 0x00, 0x00, - 0xcb, 0x26, 0x00, 0x00, 0xd0, 0x2a, 0x00, 0x00, 0x19, 0xdb, 0xff, 0xff, - 0x8a, 0xe6, 0xff, 0xff, 0xf3, 0x02, 0x00, 0x00, 0x6a, 0xe1, 0xff, 0xff, - 0x84, 0x1a, 0x00, 0x00, 0xfa, 0xf1, 0xff, 0xff, 0xf5, 0xfe, 0xff, 0xff, - 0x49, 0x0f, 0x00, 0x00, 0x4b, 0x0f, 0x00, 0x00, 0x46, 0x0c, 0x00, 0x00, - 0x76, 0x19, 0x00, 0x00, 0x52, 0x01, 0x00, 0x00, 0x99, 0x0d, 0x00, 0x00, - 0xe1, 0xd3, 0xff, 0xff, 0xcd, 0x1c, 0x00, 0x00, 0x8c, 0x0c, 0x00, 0x00, - 0xd3, 0x22, 0x00, 0x00, 0x6c, 0x03, 0x00, 0x00, 0xb6, 0xc3, 0xff, 0xff, - 0x04, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0xff, 0xd2, 0xd8, 0x13, - 0x39, 0xe1, 0x34, 0x1d, 0x11, 0x47, 0xcd, 0x3f, 0xbc, 0xe0, 0xd1, 0xdf, - 0x06, 0x4f, 0x32, 0xa7, 0x19, 0x10, 0x2a, 0x1b, 0xee, 0xab, 0x3d, 0x1d, - 0x1c, 0xd7, 0xff, 0x2a, 0xd7, 0xd7, 0xf4, 0xc7, 0x0f, 0xc4, 0xf0, 0x0c, - 0xe8, 0x26, 0xc3, 0xd1, 0xca, 0xb5, 0x1a, 0xd1, 0xd7, 0x4b, 0xc9, 0x1a, - 0xf6, 0xc8, 0x29, 0xf1, 0x0e, 0xbb, 0x49, 0xd1, 0xb8, 0x09, 0x65, 0xda, - 0xd7, 0xd9, 0x33, 0xb9, 0x1c, 0xe2, 0xcd, 0x27, 0x3d, 0xfe, 0x40, 0xf9, - 0xc3, 0x4f, 0xe3, 0xf6, 0xfa, 0x54, 0x17, 0x1b, 0xd4, 0x2a, 0x02, 0x0b, - 0x09, 0x0b, 0xc0, 0xfa, 0xf6, 0xc7, 0xb2, 0x35, 0xd2, 0x34, 0x40, 0xc5, - 0xfa, 0xe2, 0xc4, 0xed, 0xac, 0xdd, 0x13, 0xf1, 0xbe, 0x21, 0xc5, 0xf1, - 0xf6, 0xe7, 0x36, 0x81, 0xd9, 0xca, 0x19, 0xfc, 0xe5, 0xe7, 0xac, 0x08, - 0x1d, 0xc7, 0xae, 0x03, 0xc8, 0x05, 0xc9, 0x17, 0x1e, 0xf0, 0xdd, 0xd0, - 0xeb, 0xd3, 0x22, 0x46, 0xf5, 0x3b, 0x0c, 0x02, 0xe0, 0x46, 0xfe, 0xc2, - 0x43, 0x1a, 0xcc, 0xf4, 0x19, 0xba, 0x06, 0x1d, 0xfe, 0xfc, 0x12, 0x37, - 0x08, 0xe9, 0xff, 0xd1, 0xfa, 0x1b, 0x16, 0x24, 0xbd, 0x07, 0xc6, 0xf9, - 0xd4, 0x05, 0xf6, 0xe8, 0x03, 0x3f, 0x99, 0x68, 0x03, 0xe5, 0xe3, 0x7f, - 0xd0, 0xcc, 0x2f, 0x49, 0xf0, 0xe1, 0x10, 0xf2, 0x15, 0xae, 0x4d, 0xde, - 0x0b, 0xf9, 0xd4, 0xe7, 0xc7, 0xf6, 0xc8, 0x1d, 0xeb, 0x5a, 0x0f, 0x57, - 0x0f, 0x30, 0x3f, 0xf1, 0xf2, 0xed, 0x1a, 0x3b, 0xec, 0xe7, 0xd7, 0xaa, - 0x2c, 0xe1, 0x1f, 0x15, 0xd5, 0x23, 0x1b, 0xa4, 0x21, 0xe7, 0xd7, 0xf3, - 0xbb, 0x4b, 0x07, 0xe6, 0x12, 0xbd, 0xef, 0xe7, 0xa6, 0x40, 0xe4, 0x47, - 0x31, 0x1a, 0xad, 0x50, 0x5a, 0x22, 0x0d, 0x1f, 0xb8, 0xb0, 0xcb, 0x02, - 0xf5, 0x5a, 0xbb, 0xfc, 0xbc, 0xc4, 0xe7, 0xea, 0x7f, 0x34, 0xe5, 0x4a, - 0xfe, 0x1a, 0x33, 0x34, 0xed, 0xbf, 0xd0, 0xd3, 0x37, 0x93, 0x33, 0xb1, - 0xbd, 0xc3, 0xe5, 0xdd, 0x37, 0x1f, 0x43, 0x23, 0x0e, 0xd3, 0x28, 0xc2, - 0xb2, 0x50, 0x0a, 0x56, 0x16, 0xcd, 0xec, 0x0e, 0x12, 0x56, 0xa3, 0x01, - 0x16, 0xa9, 0xe0, 0x01, 0xe1, 0x2c, 0xcf, 0x3f, 0x01, 0x55, 0x1d, 0x46, - 0xe9, 0xb8, 0x2a, 0x27, 0x1c, 0xb4, 0xe8, 0xf4, 0xf7, 0x33, 0xc3, 0xa7, - 0x36, 0x34, 0x2a, 0x5c, 0xf9, 0xac, 0x4e, 0xe3, 0x48, 0xd8, 0xf8, 0xc0, - 0xd3, 0xfb, 0x92, 0xef, 0x4c, 0x07, 0x33, 0x16, 0xc4, 0xb6, 0xdf, 0x94, - 0x3d, 0x1c, 0xfb, 0xd4, 0x34, 0xb5, 0x22, 0x17, 0x0b, 0x25, 0x4b, 0x4f, - 0x3d, 0xf4, 0x4a, 0xb6, 0x07, 0x43, 0x01, 0x29, 0x2a, 0x34, 0xee, 0x22, - 0x29, 0x19, 0x2e, 0x52, 0x27, 0x1a, 0xe6, 0x08, 0xf0, 0xc6, 0xc8, 0xda, - 0x54, 0xe1, 0xa2, 0xb4, 0xe8, 0x32, 0x27, 0x20, 0xfc, 0xdc, 0xfb, 0xe2, - 0xcd, 0x01, 0xd3, 0xdc, 0xed, 0xfa, 0xcc, 0xdf, 0xfa, 0x30, 0xbe, 0xd3, - 0xda, 0xcb, 0xe3, 0xfe, 0x21, 0x1b, 0x4f, 0x06, 0x19, 0x22, 0x3a, 0x3d, - 0xf8, 0xd1, 0x17, 0x17, 0x2d, 0xc1, 0xd7, 0x38, 0x35, 0x22, 0xbc, 0x5b, - 0x44, 0x11, 0x3f, 0x2e, 0x39, 0xe5, 0x6e, 0x29, 0x11, 0xc0, 0x19, 0x08, - 0x01, 0x00, 0x2a, 0x2e, 0xe9, 0xf5, 0x17, 0xab, 0xe6, 0xd3, 0xf7, 0xf3, - 0xcf, 0x24, 0x2c, 0xdc, 0x5f, 0xee, 0xca, 0x2e, 0xb8, 0x3e, 0xeb, 0x06, - 0xf6, 0xbd, 0x27, 0xd7, 0xf6, 0xba, 0xd5, 0x5e, 0xd8, 0x50, 0xe0, 0x81, - 0xcb, 0x08, 0xd6, 0x37, 0xdd, 0x17, 0x33, 0x49, 0x21, 0xe7, 0x3c, 0x18, - 0x3d, 0x08, 0x06, 0x87, 0xfd, 0x29, 0x2e, 0xf2, 0x47, 0x0b, 0xe8, 0xcb, - 0xbf, 0xb4, 0x3f, 0x50, 0xd8, 0x38, 0xec, 0x1a, 0xbd, 0x0b, 0x2c, 0x18, - 0x2f, 0xdb, 0xd9, 0xe0, 0xfd, 0x03, 0xb7, 0xeb, 0xd3, 0xf7, 0x05, 0xbf, - 0xdb, 0x09, 0xb8, 0xee, 0xce, 0x91, 0x4c, 0xcf, 0xe9, 0xfa, 0xd0, 0xa4, - 0x56, 0x27, 0x5d, 0x43, 0x0e, 0x51, 0xe5, 0xbc, 0xf6, 0x30, 0xff, 0xd3, - 0xf1, 0x20, 0x10, 0x06, 0xac, 0x28, 0xb8, 0x19, 0xe5, 0x32, 0x17, 0xe0, - 0xe8, 0xcc, 0x7f, 0x2e, 0x48, 0xe5, 0x0c, 0xe3, 0x16, 0xd6, 0xf0, 0xc2, - 0xea, 0x18, 0x45, 0x6f, 0x55, 0xd1, 0x2f, 0x9c, 0xf6, 0xf2, 0xc8, 0xdc, - 0xa1, 0x1f, 0x19, 0xc7, 0xa2, 0x48, 0xbe, 0xf3, 0xf0, 0xdf, 0xa5, 0xf2, - 0xfe, 0xce, 0x1e, 0xdd, 0x23, 0x42, 0x09, 0xf9, 0x1f, 0xba, 0xd4, 0x2a, - 0x09, 0x1c, 0x58, 0x53, 0x0f, 0x1d, 0xc5, 0xd8, 0xf3, 0xe0, 0x17, 0x9c, - 0xb8, 0xe5, 0x14, 0x54, 0xec, 0xad, 0xa2, 0x22, 0x06, 0xbd, 0x13, 0xec, - 0xe8, 0x7f, 0xbf, 0xd4, 0x34, 0xd9, 0xad, 0x60, 0x3c, 0x53, 0xc5, 0xdb, - 0x4c, 0x21, 0x46, 0xdf, 0xb1, 0xb3, 0x68, 0xd3, 0x60, 0x64, 0x5f, 0x7e, - 0x52, 0xd6, 0xd0, 0xfd, 0x46, 0xe5, 0x46, 0xe0, 0xbc, 0x74, 0xbb, 0x3e, - 0x33, 0x44, 0x38, 0x14, 0xdd, 0xa4, 0x7a, 0xbe, 0xff, 0xdc, 0xda, 0x9b, - 0x22, 0x1c, 0x19, 0xf2, 0x20, 0x06, 0x0c, 0xc5, 0x59, 0xac, 0x2e, 0x0d, - 0xb4, 0x42, 0x3b, 0xfd, 0xb3, 0xac, 0xbb, 0xe6, 0x61, 0xc8, 0xe4, 0xde, - 0x5e, 0xd5, 0x20, 0x0c, 0xef, 0xf0, 0xc9, 0xa1, 0x10, 0xb9, 0x3a, 0x00, - 0xd3, 0x4c, 0x44, 0xea, 0x67, 0x51, 0xa7, 0xa6, 0x01, 0xfe, 0x52, 0x16, - 0xb7, 0x5e, 0x19, 0x94, 0xf4, 0xbc, 0xba, 0x9e, 0xd7, 0xcc, 0x7f, 0x9e, - 0xe3, 0xf9, 0xc7, 0x7b, 0x38, 0x37, 0xf2, 0xee, 0xc6, 0xf0, 0xed, 0xf6, - 0x5d, 0x68, 0xe2, 0x51, 0x38, 0x1c, 0x27, 0xc1, 0x02, 0xcc, 0x07, 0xff, - 0x15, 0xc3, 0x36, 0xb4, 0x95, 0xe4, 0xe5, 0x54, 0xe1, 0x75, 0x9f, 0x20, - 0x48, 0x29, 0x1e, 0xcc, 0x3c, 0x26, 0x17, 0xd6, 0x30, 0x32, 0x16, 0xe0, - 0x0a, 0x41, 0x12, 0xed, 0x4f, 0x9a, 0xf9, 0xfd, 0x7f, 0xe5, 0xfd, 0xe4, - 0x44, 0xef, 0x17, 0xe5, 0x3f, 0xb3, 0xe2, 0x02, 0x5b, 0xf2, 0xeb, 0x23, - 0xb1, 0x27, 0xe4, 0x65, 0x26, 0xfe, 0xc9, 0x00, 0xd3, 0x6b, 0xf8, 0x09, - 0xde, 0xcf, 0xb8, 0xe8, 0x38, 0x2a, 0x05, 0x46, 0xcd, 0x69, 0xd1, 0xe2, - 0x57, 0xb9, 0xfe, 0x20, 0x83, 0x33, 0x35, 0x67, 0xff, 0xce, 0xbf, 0xec, - 0x1a, 0xfa, 0xb5, 0xc5, 0xec, 0xf9, 0x02, 0x2d, 0xbc, 0x1f, 0xcf, 0x3f, - 0x1b, 0xc8, 0xef, 0x37, 0x62, 0x0c, 0x05, 0xd0, 0x39, 0x14, 0xf1, 0xe4, - 0xa6, 0xf7, 0x07, 0x17, 0xa2, 0xb3, 0x24, 0xd6, 0xf3, 0xa6, 0x49, 0xcf, - 0x1b, 0x4b, 0x03, 0x08, 0x18, 0xd7, 0x2b, 0x81, 0x1c, 0xb5, 0xa5, 0xfa, - 0x55, 0x35, 0x2f, 0xd2, 0xc2, 0x09, 0x2b, 0x25, 0x1e, 0x48, 0x06, 0xeb, - 0xf6, 0xf9, 0x07, 0x4b, 0x52, 0xf0, 0xc8, 0x46, 0xeb, 0x12, 0xce, 0x16, - 0xf4, 0x04, 0xcf, 0xcd, 0xc6, 0x01, 0x6b, 0x18, 0xb8, 0xe1, 0xcc, 0xc7, - 0xca, 0x1c, 0xa1, 0x52, 0x31, 0x1f, 0x9d, 0x07, 0x2c, 0xb3, 0xc6, 0x14, - 0x01, 0x11, 0x27, 0x04, 0xec, 0xbd, 0x36, 0x1e, 0xba, 0xdd, 0xea, 0xae, - 0xf7, 0x86, 0x93, 0x33, 0x35, 0xdc, 0x4b, 0xc0, 0xd0, 0xba, 0x20, 0x46, - 0x21, 0x5f, 0x12, 0xea, 0x9f, 0xe3, 0x11, 0x32, 0x03, 0x0a, 0xca, 0x05, - 0xdc, 0x37, 0xa2, 0x29, 0xc0, 0xc5, 0x2e, 0xec, 0xcd, 0xe8, 0xd6, 0x29, - 0xd5, 0x0f, 0x50, 0x60, 0x3f, 0x2f, 0xec, 0x4b, 0xd2, 0xcc, 0xcb, 0xf2, - 0xb4, 0x12, 0xfc, 0x16, 0x2a, 0xb5, 0x85, 0xb9, 0xa9, 0x1c, 0xd0, 0x5c, - 0xc3, 0x96, 0x58, 0xba, 0x08, 0xfd, 0xdf, 0x11, 0x6d, 0x45, 0xef, 0x2a, - 0x28, 0xb7, 0xf0, 0x3b, 0x1c, 0xe6, 0xf4, 0x59, 0xd6, 0xed, 0x3a, 0xcc, - 0xd8, 0x60, 0x81, 0x3f, 0xda, 0x1c, 0xd5, 0x00, 0xc6, 0xf5, 0xc0, 0xe2, - 0x00, 0xd7, 0xb7, 0xe3, 0xdb, 0x26, 0xf0, 0x51, 0x22, 0xb9, 0x26, 0xcc, - 0xa5, 0x4f, 0x34, 0x61, 0x5d, 0x2d, 0xfa, 0xe3, 0xc7, 0x43, 0x0f, 0x22, - 0x07, 0x35, 0x47, 0x2c, 0xf4, 0x70, 0x24, 0x31, 0x09, 0xea, 0x0a, 0x35, - 0xf0, 0x49, 0x19, 0xfe, 0xee, 0xc1, 0xf9, 0x2e, 0x1d, 0xb8, 0xe8, 0xd1, - 0x24, 0xe7, 0x88, 0x0a, 0x18, 0x33, 0x31, 0x32, 0x26, 0xe3, 0x07, 0xb3, - 0x2d, 0x32, 0x15, 0x96, 0xfc, 0x22, 0x00, 0x34, 0x2e, 0xe6, 0x9c, 0xda, - 0x45, 0xd8, 0x45, 0xc0, 0x31, 0xec, 0xc0, 0x84, 0xe7, 0x36, 0xe3, 0x06, - 0xd5, 0xd4, 0x96, 0x3f, 0x7a, 0x06, 0xb8, 0x12, 0xaf, 0x3f, 0x11, 0xd0, - 0xde, 0x15, 0xbc, 0xf6, 0x5d, 0xb8, 0xf0, 0x04, 0xd0, 0xde, 0x2b, 0x3c, - 0xb1, 0x0b, 0xcb, 0x22, 0xf7, 0x66, 0x27, 0x03, 0x4f, 0xdf, 0xcb, 0x14, - 0xad, 0xd0, 0xea, 0x41, 0x24, 0x69, 0xbf, 0xca, 0xe7, 0x2d, 0x00, 0xcf, - 0x0c, 0x0f, 0xae, 0xdb, 0x1e, 0x51, 0xb0, 0x53, 0xc4, 0x43, 0xc2, 0x39, - 0xc4, 0x23, 0xbf, 0xf5, 0x27, 0xf4, 0x3f, 0x43, 0xcf, 0x0f, 0xf8, 0x5c, - 0xb8, 0x0a, 0x55, 0x10, 0xed, 0xee, 0x1f, 0xa9, 0x21, 0x21, 0x1f, 0xd6, - 0x5b, 0x0d, 0x11, 0x15, 0x12, 0xe1, 0x43, 0x1c, 0xe2, 0x02, 0xf0, 0xe3, - 0xa8, 0xd1, 0x12, 0xb4, 0xd8, 0x41, 0x36, 0xef, 0x33, 0xc7, 0xcb, 0xfe, - 0xd3, 0x22, 0x81, 0xdb, 0x00, 0xcf, 0x0d, 0xdf, 0x02, 0xc0, 0x2d, 0xc9, - 0xdf, 0x0e, 0xaa, 0x98, 0x35, 0x30, 0xbd, 0xda, 0xbe, 0xa1, 0xbf, 0xba, - 0x32, 0xf2, 0xe0, 0xe2, 0x01, 0x49, 0x2d, 0xe3, 0xdd, 0xe7, 0x1c, 0x18, - 0x39, 0x4c, 0xea, 0x04, 0xb9, 0xd8, 0x1b, 0xf7, 0xcb, 0x23, 0x57, 0xe6, - 0xf7, 0xae, 0x58, 0x38, 0xf2, 0xc8, 0xff, 0xaa, 0xc6, 0x59, 0xf7, 0x28, - 0xf9, 0xf5, 0xb6, 0x35, 0xf4, 0x19, 0x0d, 0x2e, 0xd4, 0x6b, 0x2e, 0x0f, - 0x2e, 0x3e, 0xb5, 0xf4, 0x24, 0xbf, 0x3a, 0x3e, 0xf3, 0xbf, 0xe8, 0xdc, - 0xe5, 0xee, 0x2c, 0x64, 0xe1, 0xfc, 0xc3, 0xee, 0xe9, 0xc0, 0xc1, 0x42, - 0x4c, 0x08, 0x1a, 0x04, 0xea, 0xf7, 0xb7, 0x0e, 0xde, 0xae, 0x53, 0xc9, - 0xed, 0x13, 0x13, 0x4f, 0xf7, 0xb5, 0xb8, 0x08, 0x24, 0xe1, 0x0b, 0xf7, - 0xd7, 0x1d, 0x04, 0x0f, 0x0c, 0xcc, 0xfc, 0xd3, 0xf9, 0xe5, 0xbc, 0xa7, - 0xde, 0xb4, 0x0a, 0xef, 0x7f, 0x47, 0x09, 0xd6, 0x31, 0x14, 0x5c, 0xd2, - 0x4d, 0xf6, 0x66, 0xc1, 0xd6, 0xd2, 0x2d, 0xed, 0x68, 0xdd, 0xbc, 0x8d, - 0x05, 0x12, 0x48, 0x20, 0x18, 0xcb, 0xe7, 0xd8, 0xf8, 0xef, 0x3a, 0x0d, - 0x1a, 0xec, 0xe9, 0xbc, 0xe2, 0x4d, 0xa0, 0xf3, 0x28, 0x81, 0x24, 0x9c, - 0xec, 0x16, 0xf7, 0xd9, 0xd5, 0x1c, 0x11, 0xe4, 0xbe, 0xb7, 0x36, 0xb0, - 0xc8, 0xfe, 0x88, 0x54, 0xb6, 0x1e, 0x2c, 0x2b, 0x07, 0x10, 0xe6, 0xdd, - 0xe0, 0xc7, 0xdb, 0x28, 0x26, 0xc9, 0xf0, 0x13, 0x3c, 0xd8, 0x32, 0xb3, - 0x18, 0xe5, 0xff, 0xf0, 0x2d, 0x31, 0x01, 0x22, 0xb9, 0xbc, 0xe3, 0xb8, - 0x27, 0x59, 0x02, 0xc4, 0xd3, 0xcd, 0xc6, 0xc3, 0x0b, 0xf8, 0x20, 0x31, - 0x0f, 0xdf, 0xe2, 0x25, 0x15, 0x49, 0x3d, 0x28, 0xe7, 0x12, 0x02, 0x02, - 0x5e, 0x1d, 0x15, 0xd0, 0x17, 0xb7, 0xf1, 0x02, 0xc4, 0xdf, 0xdd, 0xec, - 0x22, 0xe4, 0x3a, 0x2a, 0x00, 0x30, 0xbc, 0xbe, 0x7f, 0x10, 0x48, 0x1a, - 0xc8, 0x46, 0xe5, 0x55, 0xbb, 0x14, 0x4b, 0xcb, 0x4d, 0x23, 0xf1, 0x33, - 0x1b, 0x2f, 0xac, 0xc4, 0x37, 0x46, 0xe3, 0xf3, 0xd6, 0xef, 0xc5, 0xd9, - 0xe2, 0xc6, 0xe0, 0x0a, 0xce, 0xca, 0x2d, 0x81, 0x27, 0xfe, 0x2b, 0x3f, - 0x11, 0x14, 0x0a, 0x38, 0x6a, 0xc8, 0x44, 0xa6, 0xea, 0xc6, 0x01, 0xdc, - 0x21, 0xd9, 0xe5, 0x4b, 0x0b, 0xe6, 0xaf, 0xf9, 0xf8, 0xb4, 0xe7, 0x9d, - 0x0e, 0x4f, 0xcd, 0xae, 0x38, 0x52, 0x09, 0xb4, 0x47, 0xfe, 0x23, 0x51, - 0x37, 0x62, 0xbb, 0x3f, 0xd2, 0xc0, 0xf5, 0xf0, 0xc1, 0xc7, 0x16, 0x05, - 0x6b, 0x17, 0x42, 0xaf, 0xcf, 0xef, 0x13, 0x40, 0xc1, 0x0f, 0xd3, 0xd1, - 0xbf, 0xf0, 0x6a, 0x09, 0xba, 0xbe, 0xda, 0x03, 0xc3, 0x34, 0xb3, 0xbc, - 0xf6, 0x27, 0x93, 0xff, 0x2c, 0xe9, 0xe9, 0x32, 0xa4, 0x40, 0x3f, 0x48, - 0x45, 0x1f, 0xd7, 0x99, 0x04, 0x3a, 0x49, 0x2b, 0x04, 0x42, 0xc5, 0xbe, - 0x0b, 0xcc, 0xe4, 0x2d, 0x25, 0xf0, 0x0e, 0x95, 0x42, 0xe9, 0x65, 0xc3, - 0x14, 0xd4, 0x43, 0x31, 0xc8, 0x4b, 0xfd, 0x19, 0x27, 0xce, 0xb9, 0x59, - 0x71, 0x9e, 0x47, 0x06, 0x10, 0xc5, 0x00, 0xb3, 0x2f, 0x4e, 0x10, 0x0e, - 0x1c, 0x39, 0xa0, 0xf4, 0x24, 0x07, 0x25, 0x81, 0x5d, 0x30, 0xf6, 0xb1, - 0x14, 0xe9, 0x5a, 0x3d, 0x02, 0xd6, 0x00, 0x1a, 0xcb, 0xf5, 0xf0, 0xf8, - 0x1d, 0x21, 0x84, 0x27, 0x2d, 0xec, 0x53, 0xf7, 0xb4, 0x3f, 0x0f, 0xfd, - 0xb6, 0x11, 0x3d, 0x2c, 0x3a, 0xe2, 0x28, 0x39, 0xf8, 0x3e, 0x0e, 0xfe, - 0x23, 0x0d, 0xfb, 0x40, 0x04, 0xa2, 0x15, 0x0c, 0xc9, 0xa4, 0x34, 0x15, - 0xd6, 0xeb, 0x27, 0x5f, 0x60, 0x6b, 0x2b, 0x5a, 0x5b, 0xcc, 0xc6, 0xae, - 0x05, 0xaa, 0xa6, 0x36, 0x2e, 0x50, 0x0d, 0xcb, 0x0a, 0x6d, 0xd2, 0xce, - 0x51, 0x41, 0x14, 0x0d, 0x29, 0x0d, 0x38, 0xfd, 0xff, 0xd3, 0x9d, 0xcd, - 0xd4, 0x2f, 0x5f, 0xc9, 0xa3, 0xe4, 0xb2, 0x12, 0xc3, 0xce, 0xd2, 0xd6, - 0xf5, 0xdd, 0xfb, 0x8e, 0x26, 0x0a, 0xde, 0xb9, 0x01, 0xfb, 0x33, 0xd0, - 0x26, 0xf4, 0xf2, 0x3f, 0x3a, 0x3e, 0x2d, 0x00, 0x42, 0xd8, 0x34, 0x08, - 0xf6, 0xa9, 0x0a, 0xcf, 0x28, 0x1f, 0x56, 0x00, 0xd2, 0xe2, 0x99, 0xc2, - 0xc0, 0x20, 0xf7, 0xa1, 0xbd, 0x1a, 0xce, 0xfc, 0x2a, 0x47, 0xf0, 0xfd, - 0xcf, 0xe1, 0xc9, 0xff, 0xc9, 0xcf, 0x06, 0xea, 0x33, 0xa7, 0x27, 0x3b, - 0x8a, 0xf0, 0xd2, 0xee, 0x27, 0xec, 0xfd, 0x07, 0xc6, 0x5c, 0xd6, 0x44, - 0xa3, 0xf9, 0x2b, 0xd2, 0x7f, 0xf4, 0xa4, 0x6c, 0xc5, 0xc8, 0x1f, 0xd0, - 0xfe, 0xef, 0x22, 0xc8, 0x44, 0x45, 0xfd, 0x0e, 0x22, 0xd2, 0xe4, 0x14, - 0x05, 0xfe, 0x1f, 0x14, 0xf2, 0x01, 0x3c, 0xf4, 0x2e, 0xfa, 0x5a, 0x2b, - 0xbd, 0x53, 0x35, 0xf9, 0xa8, 0xcc, 0xc7, 0x2a, 0xd1, 0xda, 0xfb, 0xd9, - 0x25, 0xfb, 0x8c, 0xd7, 0x35, 0x2a, 0xf4, 0xe9, 0xe1, 0x0b, 0x54, 0x17, - 0x11, 0x42, 0xf7, 0x2c, 0x10, 0x04, 0xfb, 0xc8, 0xcd, 0xd2, 0x34, 0x0e, - 0xf1, 0xf3, 0x16, 0xf2, 0xf0, 0x1b, 0xc7, 0x05, 0x5d, 0xcc, 0xb1, 0x31, - 0xe1, 0x0b, 0x1a, 0x16, 0x20, 0x32, 0xec, 0x2f, 0x32, 0x26, 0xd1, 0xf5, - 0x0c, 0xd2, 0xce, 0xcd, 0x14, 0xc8, 0x24, 0x2c, 0xf1, 0xfe, 0x3e, 0x06, - 0x21, 0x18, 0xe3, 0x9b, 0xbd, 0xf5, 0xcd, 0xf0, 0x0f, 0x3c, 0x24, 0x26, - 0x5a, 0x0e, 0xd2, 0x45, 0x09, 0x33, 0x05, 0x44, 0x2f, 0x40, 0xcd, 0x3e, - 0x2f, 0xee, 0x45, 0xbb, 0xd7, 0xd7, 0xd5, 0x08, 0x27, 0x37, 0x3a, 0xd8, - 0x34, 0xbe, 0x30, 0x4b, 0xe4, 0x32, 0xb6, 0xac, 0xeb, 0xca, 0x4b, 0x0d, - 0x3e, 0xfc, 0x16, 0x81, 0x1d, 0x3f, 0x08, 0x20, 0x40, 0xae, 0xcb, 0x2c, - 0xd8, 0xca, 0x16, 0x1e, 0x2d, 0xc9, 0x19, 0xad, 0x11, 0xf3, 0x0c, 0xfa, - 0x47, 0x7f, 0x72, 0xa2, 0x4f, 0xb6, 0xbd, 0xd9, 0xde, 0x50, 0x2f, 0x20, - 0xd3, 0xe2, 0xdb, 0xad, 0xfb, 0x33, 0xfe, 0xba, 0x9f, 0xf9, 0xe6, 0xd2, - 0xe4, 0x61, 0x19, 0x46, 0x01, 0x09, 0xf4, 0x55, 0x1d, 0x53, 0xdd, 0x52, - 0xbe, 0x48, 0x44, 0xc4, 0x38, 0x35, 0xe2, 0xed, 0xf5, 0x02, 0x0f, 0xa8, - 0xa6, 0xf1, 0x12, 0x41, 0x18, 0xb8, 0xdd, 0x3b, 0xab, 0x5c, 0xcb, 0x46, - 0xef, 0xb6, 0x12, 0xd7, 0xda, 0x38, 0x29, 0xe9, 0x1c, 0xc8, 0x09, 0x1d, - 0xf1, 0xcb, 0xcc, 0x1f, 0x12, 0xd0, 0xd2, 0x46, 0xe2, 0xd9, 0x73, 0x44, - 0x35, 0x21, 0x5a, 0xfc, 0x42, 0xd3, 0xdc, 0xe5, 0xc4, 0xc9, 0xfe, 0x4d, - 0xf5, 0xf3, 0xd4, 0x88, 0x24, 0xff, 0x5a, 0x05, 0xe7, 0xc6, 0x91, 0xa6, - 0xfd, 0x21, 0x36, 0xc2, 0xc9, 0x21, 0xd7, 0x04, 0x52, 0x61, 0x5e, 0x22, - 0x6a, 0x0b, 0x36, 0xca, 0x2e, 0x17, 0xc5, 0xd9, 0x2f, 0x62, 0xd4, 0xb5, - 0x56, 0x03, 0xdc, 0x04, 0xf6, 0x1d, 0xb4, 0x4a, 0xd3, 0x01, 0xc3, 0xef, - 0x01, 0x1b, 0x16, 0xc5, 0xfd, 0x40, 0x15, 0xe2, 0x38, 0x20, 0x16, 0x15, - 0x25, 0xf0, 0xb3, 0xd4, 0x10, 0x2c, 0x16, 0x71, 0xc7, 0x37, 0x2c, 0x03, - 0xfd, 0xe1, 0x2c, 0x06, 0x06, 0x59, 0xc7, 0x91, 0xcf, 0xe3, 0x1f, 0x22, - 0x3f, 0xb8, 0x08, 0xba, 0xca, 0x4f, 0x27, 0xbf, 0xd1, 0xd0, 0xea, 0x26, - 0x3e, 0xe6, 0x2a, 0xe9, 0x23, 0x11, 0x37, 0xee, 0x4f, 0x81, 0xd7, 0x1b, - 0xf3, 0xe4, 0xe1, 0x03, 0xdd, 0x37, 0x18, 0xfd, 0xd2, 0xd1, 0x19, 0xf5, - 0x20, 0x0a, 0xb8, 0xcc, 0xd6, 0x23, 0xd3, 0x00, 0xf4, 0xd9, 0xcf, 0xc1, - 0x16, 0x21, 0x0d, 0xf8, 0x28, 0xc4, 0xcb, 0xc4, 0xdc, 0x3b, 0xb4, 0x29, - 0x26, 0x30, 0xfe, 0xe4, 0x26, 0xf6, 0xec, 0x38, 0x23, 0x68, 0xb1, 0xd2, - 0xe1, 0x25, 0x29, 0x05, 0x15, 0x66, 0x24, 0x16, 0x6a, 0x15, 0x18, 0x23, - 0x5a, 0x38, 0xdc, 0xc6, 0x28, 0x69, 0xb0, 0x99, 0x29, 0xe4, 0xe0, 0x0e, - 0xc7, 0x7f, 0x00, 0x1c, 0xda, 0x5b, 0xab, 0x40, 0x55, 0xbc, 0xe6, 0x57, - 0xe3, 0x49, 0x60, 0x23, 0x4b, 0xaf, 0x2f, 0x43, 0xf4, 0xf9, 0x18, 0x07, - 0xd4, 0x01, 0xb6, 0xb9, 0x12, 0x0a, 0xce, 0xc8, 0x64, 0xf8, 0x51, 0x2f, - 0x5d, 0x08, 0xbb, 0xdb, 0x3e, 0xa5, 0xc8, 0xe6, 0xc2, 0x32, 0x31, 0xe6, - 0x0c, 0xb6, 0x70, 0xc7, 0x08, 0x8d, 0x0d, 0xb0, 0x1a, 0xc1, 0xd8, 0x04, - 0x45, 0x06, 0x1f, 0xcb, 0xb7, 0xea, 0xc6, 0x1a, 0xc9, 0x16, 0x03, 0x67, - 0x86, 0x3f, 0xc0, 0x44, 0xe9, 0xe0, 0xdb, 0xde, 0x3b, 0x1a, 0x2e, 0xc3, - 0x37, 0xf4, 0x4e, 0x28, 0x44, 0x15, 0x21, 0xe0, 0xb0, 0xa0, 0x2b, 0xc3, - 0x6a, 0xd5, 0xee, 0x4e, 0x05, 0xbb, 0x09, 0x03, 0xc9, 0x13, 0x39, 0xd1, - 0xd3, 0x60, 0x02, 0xba, 0x3a, 0xdb, 0xea, 0xc3, 0x34, 0x5a, 0x27, 0xd1, - 0x15, 0xf9, 0x0b, 0xe2, 0x06, 0x7f, 0xc9, 0xdd, 0xe8, 0xd9, 0xfc, 0x10, - 0xb2, 0xe0, 0xe5, 0xfa, 0xcf, 0xee, 0xc3, 0x26, 0x1c, 0x07, 0xed, 0x11, - 0x4b, 0xc7, 0xd1, 0x28, 0xd4, 0x1e, 0x15, 0xd4, 0xf0, 0x13, 0xa5, 0x59, - 0xdf, 0x32, 0xec, 0x94, 0xcd, 0x33, 0xc3, 0x13, 0x53, 0x19, 0xd3, 0x0a, - 0xd3, 0xb2, 0xae, 0xe1, 0x37, 0x40, 0xbb, 0xbb, 0xec, 0x4f, 0xaf, 0xf2, - 0x4d, 0xd0, 0xa7, 0x4c, 0xf8, 0x1e, 0x99, 0xe0, 0xd5, 0x27, 0xe7, 0x09, - 0x3d, 0xbb, 0x00, 0x04, 0xf0, 0xe2, 0xd0, 0x19, 0x10, 0xbd, 0x9f, 0xdc, - 0xd7, 0x23, 0xf5, 0x50, 0xf5, 0xf3, 0xd6, 0xc5, 0x01, 0x04, 0xab, 0x15, - 0x4e, 0xf3, 0xe3, 0xdf, 0xdd, 0xbd, 0xe6, 0xf2, 0x06, 0xff, 0x10, 0xe0, - 0x55, 0x2b, 0x2c, 0x32, 0xcf, 0x47, 0x4c, 0xb7, 0xc6, 0xcd, 0x24, 0xed, - 0x42, 0x7f, 0xa6, 0x00, 0x3e, 0x0b, 0xa6, 0x0c, 0xd0, 0xad, 0x5d, 0x07, - 0xea, 0x5b, 0xb1, 0x4d, 0xc2, 0xa6, 0x1c, 0x2e, 0x19, 0x1d, 0xfb, 0x52, - 0xd6, 0xe2, 0x32, 0x2c, 0xef, 0x22, 0x17, 0x65, 0x47, 0x0e, 0xc6, 0xf0, - 0xd7, 0x02, 0x0a, 0xce, 0xce, 0x65, 0x30, 0x26, 0x64, 0x47, 0x6a, 0x75, - 0xfd, 0x8f, 0xf7, 0xed, 0xe6, 0xc3, 0x1b, 0x5e, 0xdc, 0xbc, 0x47, 0x47, - 0x66, 0xe5, 0x33, 0xd7, 0x07, 0x0b, 0x07, 0x46, 0xbb, 0x17, 0x06, 0xae, - 0xe1, 0x0e, 0x1c, 0x22, 0xfa, 0xe9, 0xf2, 0xaa, 0x4c, 0x94, 0xbc, 0xae, - 0x3e, 0xe0, 0xe4, 0xf1, 0xe7, 0xe9, 0x5f, 0x76, 0xb2, 0xae, 0xf3, 0x3a, - 0x4c, 0xb0, 0xfe, 0xd5, 0x6a, 0x14, 0xbe, 0xd0, 0x03, 0xb5, 0x26, 0x10, - 0x09, 0xaf, 0x53, 0x06, 0xf5, 0xd2, 0xf6, 0x48, 0xd9, 0x9f, 0xd0, 0xd8, - 0xfc, 0x1c, 0x2d, 0x14, 0x15, 0x11, 0x10, 0xc4, 0x9b, 0xe2, 0x5f, 0x15, - 0xfc, 0xca, 0x1f, 0xce, 0xc1, 0x04, 0xd8, 0xa3, 0xd6, 0x23, 0x4e, 0xe3, - 0xfb, 0x17, 0x00, 0xd0, 0xcb, 0xef, 0xd3, 0x4c, 0x0a, 0x04, 0x40, 0xb5, - 0x81, 0x00, 0xe3, 0xae, 0x33, 0x22, 0x5e, 0x12, 0xd3, 0x45, 0xff, 0xf4, - 0xca, 0x07, 0xf1, 0x5c, 0xad, 0xec, 0x6a, 0x25, 0x1f, 0x0b, 0x5d, 0xc3, - 0xe3, 0xe2, 0x2d, 0xca, 0x3a, 0xca, 0xc6, 0x25, 0x4f, 0x07, 0xd2, 0xd5, - 0xff, 0x35, 0x10, 0x2e, 0xa8, 0x28, 0xe4, 0x24, 0x1e, 0x55, 0x0a, 0x07, - 0xc2, 0xc2, 0xba, 0xeb, 0xa0, 0xf7, 0xf8, 0x01, 0xe0, 0x14, 0x0c, 0xe0, - 0xbb, 0x49, 0xd4, 0xd8, 0x37, 0x6e, 0x56, 0x1a, 0xb5, 0x51, 0xe9, 0x0d, - 0xc1, 0xed, 0xd1, 0x17, 0xef, 0xe9, 0x02, 0x04, 0x6b, 0xea, 0xf1, 0x21, - 0xee, 0xde, 0xee, 0x34, 0xaa, 0x5e, 0x1d, 0xd0, 0x58, 0x1c, 0x54, 0xdf, - 0x7f, 0xa3, 0xa7, 0x3a, 0xe1, 0xe1, 0xee, 0xc4, 0x55, 0x9e, 0x1b, 0x31, - 0xe4, 0xc5, 0x3a, 0xc7, 0xab, 0x82, 0xe1, 0x38, 0x29, 0xd1, 0xce, 0x47, - 0xa0, 0xdc, 0xe9, 0xf7, 0xfc, 0x0c, 0xc7, 0xe5, 0xdf, 0xee, 0x06, 0x4a, - 0x0a, 0xb7, 0x1c, 0x31, 0x36, 0xa5, 0x3a, 0x97, 0xb1, 0xea, 0x95, 0x63, - 0x25, 0xef, 0x1b, 0x67, 0xb7, 0x5b, 0xbb, 0x29, 0x16, 0xa3, 0x1f, 0x13, - 0xae, 0xcf, 0xfd, 0x2a, 0xf3, 0xc4, 0x09, 0x46, 0x24, 0xe0, 0xc9, 0xc8, - 0xb0, 0x8e, 0x1b, 0x9d, 0x03, 0x1f, 0x33, 0x49, 0x34, 0x25, 0x5b, 0xc8, - 0xe3, 0x27, 0xa9, 0xd2, 0x09, 0x29, 0xc8, 0xe1, 0xb4, 0xfa, 0x01, 0xa3, - 0xec, 0x4c, 0x3c, 0x43, 0x1f, 0x22, 0xfa, 0x1a, 0x0d, 0xde, 0x05, 0xe2, - 0xd8, 0x36, 0xf2, 0xda, 0xa4, 0x17, 0x64, 0xf8, 0x14, 0xf5, 0xb8, 0xe2, - 0xfd, 0xd5, 0x5a, 0x13, 0x38, 0x45, 0xc6, 0xf9, 0x02, 0xdf, 0x29, 0x4b, - 0x08, 0xc9, 0x47, 0x05, 0xb9, 0xdc, 0x40, 0x58, 0xa4, 0xf4, 0x4c, 0x00, - 0x4e, 0x0a, 0x2f, 0x0e, 0x5d, 0x9b, 0xb2, 0x48, 0x23, 0xb3, 0xe1, 0xbc, - 0xe1, 0x57, 0xfd, 0x12, 0x57, 0x9b, 0x5b, 0xf7, 0xed, 0x07, 0xc4, 0x43, - 0xc8, 0xbc, 0x9d, 0xfc, 0x7f, 0x60, 0x2e, 0xe0, 0x3c, 0xfd, 0x6f, 0x19, - 0x07, 0xfc, 0x8a, 0xa7, 0x46, 0x19, 0x2d, 0xb7, 0xd6, 0xb8, 0x1c, 0xdb, - 0xfa, 0x07, 0xf1, 0xe1, 0x9a, 0x4e, 0xb1, 0xf9, 0xa6, 0x4a, 0x7c, 0xbe, - 0xdc, 0x03, 0xd3, 0xa7, 0xab, 0x29, 0x2a, 0x57, 0xb9, 0x2e, 0xbe, 0x99, - 0x66, 0x52, 0x23, 0x47, 0x35, 0xde, 0x51, 0x78, 0xff, 0xbc, 0xe5, 0x1b, - 0x66, 0x42, 0x9f, 0x6f, 0xcd, 0xe6, 0xfc, 0x17, 0xfd, 0xeb, 0x68, 0xf3, - 0x49, 0x92, 0x17, 0x71, 0x06, 0x67, 0xf3, 0xc5, 0x18, 0x11, 0x40, 0xef, - 0xef, 0x64, 0x24, 0xfc, 0xcc, 0x5c, 0x00, 0xc7, 0xc5, 0xfd, 0xf9, 0xed, - 0x3a, 0xd5, 0xf7, 0xd3, 0x07, 0xed, 0x35, 0x23, 0xdb, 0x23, 0xd6, 0xe1, - 0x1b, 0x3c, 0x2a, 0x27, 0x36, 0xcf, 0xde, 0x13, 0xe7, 0xe6, 0xc8, 0x04, - 0x1b, 0xc9, 0x08, 0x19, 0x2f, 0x25, 0xff, 0x1a, 0xf7, 0xd2, 0x2b, 0x2a, - 0xd4, 0x04, 0xfd, 0xf7, 0x1a, 0xf2, 0xc3, 0x25, 0x49, 0xbb, 0xda, 0x2f, - 0x29, 0x63, 0xd5, 0x0c, 0x0e, 0x28, 0x3c, 0x33, 0x20, 0x25, 0x2a, 0xf2, - 0xf2, 0x39, 0x43, 0xbc, 0x01, 0xb2, 0x18, 0x7f, 0x00, 0xf9, 0xc4, 0xe7, - 0x0e, 0x1b, 0x15, 0xb8, 0x2c, 0xdf, 0xe8, 0x0f, 0x3e, 0x19, 0xd7, 0x26, - 0xb8, 0xff, 0xe7, 0x1e, 0x16, 0x2c, 0x91, 0x9a, 0xee, 0x38, 0x34, 0xa6, - 0x2f, 0x27, 0xdd, 0xd2, 0x1e, 0x34, 0x20, 0x39, 0x2b, 0xfe, 0x2b, 0xf8, - 0xe2, 0x40, 0xe7, 0x1d, 0xda, 0xdc, 0xfe, 0xd7, 0x1a, 0x30, 0xdd, 0x0e, - 0x16, 0xca, 0xe5, 0x35, 0xf1, 0x30, 0x53, 0x0a, 0xef, 0x18, 0xf8, 0x4c, - 0x55, 0xf3, 0x18, 0xd3, 0xf2, 0xc3, 0xfa, 0x1b, 0xe9, 0x9e, 0x45, 0x38, - 0xa5, 0xc8, 0xfa, 0x5c, 0x32, 0x12, 0xa1, 0xd2, 0x47, 0x11, 0x03, 0x23, - 0x50, 0xdb, 0x16, 0x31, 0xea, 0xfe, 0x42, 0xff, 0x03, 0x4b, 0x37, 0x91, - 0xd8, 0x4b, 0xe0, 0xb7, 0x10, 0xeb, 0xcd, 0x0a, 0x17, 0x76, 0x28, 0x43, - 0x19, 0xdf, 0x42, 0x5e, 0xfa, 0xec, 0x0d, 0xc7, 0xf7, 0xf8, 0xb9, 0xf1, - 0xdb, 0xab, 0xdf, 0x65, 0x51, 0xcc, 0xf3, 0x3e, 0x06, 0xdb, 0x1e, 0xcf, - 0xe2, 0xcf, 0x00, 0xe0, 0x2c, 0x02, 0xb0, 0xbc, 0x0e, 0xc4, 0x00, 0xfe, - 0x15, 0x49, 0x95, 0xd7, 0x31, 0x4c, 0xb7, 0xba, 0xd7, 0x62, 0xe3, 0x25, - 0x27, 0x3d, 0x96, 0x22, 0x05, 0xb4, 0xf3, 0xee, 0x7f, 0xcf, 0xbf, 0x51, - 0xb0, 0xac, 0xe7, 0xc5, 0x07, 0x14, 0xc0, 0xfe, 0x32, 0xc9, 0x34, 0xf1, - 0xf8, 0x11, 0x39, 0x1b, 0x10, 0x20, 0x1c, 0x7f, 0x06, 0x26, 0x05, 0xcc, - 0xd0, 0xee, 0xff, 0x41, 0xd1, 0xb5, 0xc4, 0x34, 0xd3, 0x27, 0xe7, 0x12, - 0x06, 0xfb, 0x1c, 0xbd, 0xdb, 0xdc, 0x0b, 0xfc, 0xec, 0xf7, 0xfd, 0x12, - 0x09, 0x1d, 0xbc, 0x49, 0x2b, 0xea, 0xb7, 0xfc, 0xd9, 0xb7, 0x00, 0xdb, - 0xe0, 0xda, 0x41, 0x29, 0xe6, 0x59, 0x0a, 0xc3, 0xe4, 0xcc, 0x13, 0x22, - 0x61, 0x41, 0x3f, 0x05, 0x19, 0x2a, 0x3e, 0x04, 0xa3, 0xfd, 0x52, 0x33, - 0xb6, 0x09, 0xf7, 0x3e, 0xf4, 0x02, 0xd2, 0xb0, 0xef, 0xc5, 0xd7, 0x29, - 0xce, 0xf3, 0x39, 0xbe, 0x2a, 0x22, 0xfd, 0x30, 0xe4, 0xfc, 0x1a, 0x14, - 0xa8, 0x1f, 0xcb, 0x4a, 0xd9, 0xe6, 0xee, 0xdc, 0xb7, 0x1b, 0xb7, 0x24, - 0xd7, 0xfc, 0xa6, 0xd1, 0x1b, 0x0f, 0x42, 0xe4, 0x2b, 0x3f, 0xc2, 0x28, - 0x54, 0xc0, 0xf8, 0x09, 0x8a, 0x1e, 0xec, 0x2f, 0xbb, 0xb6, 0xd3, 0x8b, - 0x4a, 0xd3, 0xbb, 0x30, 0xb7, 0x32, 0xd3, 0xc2, 0x2c, 0x6f, 0x06, 0xef, - 0x5a, 0x23, 0xc0, 0xd0, 0x37, 0xa4, 0x3e, 0x00, 0xe2, 0xc9, 0xd7, 0xa3, - 0xf8, 0x03, 0xf3, 0x2c, 0xf0, 0x35, 0xb9, 0xa9, 0xe9, 0x45, 0x34, 0xc2, - 0x03, 0x44, 0x4c, 0x35, 0xd5, 0xc7, 0xb3, 0xed, 0xb7, 0xb7, 0xb8, 0xe7, - 0x4e, 0x0f, 0x2b, 0xd8, 0x20, 0x21, 0x65, 0xe5, 0xdb, 0x0b, 0xbe, 0xcc, - 0x49, 0xd3, 0xa9, 0xec, 0xee, 0xaa, 0xea, 0x3a, 0xf2, 0xd4, 0x0a, 0x09, - 0x33, 0x4c, 0x60, 0xe9, 0xb4, 0x1d, 0x52, 0xee, 0x00, 0x3c, 0x57, 0xbb, - 0x1b, 0xcc, 0x30, 0x42, 0xcf, 0x44, 0x10, 0xec, 0x33, 0xec, 0xe1, 0x2e, - 0xb5, 0x81, 0x08, 0x87, 0x12, 0x3a, 0x0e, 0xd2, 0x12, 0xf2, 0xd0, 0xf7, - 0x24, 0xdb, 0xfc, 0x12, 0x0b, 0xd5, 0x48, 0x1c, 0xc2, 0xfa, 0x38, 0xba, - 0x8e, 0xf3, 0xc9, 0xd4, 0x57, 0xd5, 0xbf, 0xe4, 0xd7, 0x03, 0x3d, 0x17, - 0xf9, 0xe9, 0xc1, 0xa8, 0xc4, 0xfe, 0xe0, 0xdb, 0xd2, 0xff, 0xd9, 0x3a, - 0xa8, 0xb6, 0xfd, 0xe3, 0xf4, 0xcf, 0x23, 0xf9, 0x57, 0x3a, 0x43, 0xea, - 0x58, 0xf1, 0xf4, 0x29, 0xe8, 0x26, 0x15, 0xc8, 0xec, 0xe4, 0xfa, 0x30, - 0x36, 0xf1, 0xbf, 0xb3, 0xb5, 0xbe, 0xee, 0x5b, 0xb2, 0x5e, 0xd1, 0x1c, - 0xfc, 0xbf, 0xbb, 0x1b, 0xe8, 0xc2, 0x21, 0x06, 0x1b, 0xdc, 0x15, 0xde, - 0xfb, 0x33, 0x57, 0x47, 0xe4, 0xcc, 0xe2, 0x29, 0xd1, 0x1e, 0xe5, 0x79, - 0x06, 0xc4, 0x01, 0x1c, 0xaf, 0x3a, 0xbe, 0x21, 0x20, 0xbf, 0xdf, 0x52, - 0xbc, 0xd1, 0x23, 0x90, 0xf3, 0x21, 0xe5, 0xa3, 0xe8, 0xb1, 0x7f, 0xaa, - 0xea, 0x01, 0x1d, 0xaf, 0xe6, 0xde, 0x4b, 0xc0, 0x27, 0x56, 0x10, 0x32, - 0xfa, 0x62, 0x2a, 0xb8, 0x06, 0xfb, 0xeb, 0x51, 0x46, 0x4f, 0x61, 0x90, - 0xff, 0x01, 0x9b, 0x1f, 0x49, 0x2f, 0xb9, 0xd2, 0x1b, 0x37, 0x4b, 0x19, - 0x9b, 0x0d, 0x5a, 0x48, 0x39, 0x1a, 0x4f, 0x61, 0x23, 0xe5, 0x2b, 0xd7, - 0xa5, 0xd9, 0xe4, 0x3e, 0x4a, 0x28, 0x6e, 0xff, 0x0b, 0x39, 0x9a, 0x61, - 0x1a, 0xfa, 0x5e, 0xb4, 0x6c, 0xb0, 0x41, 0x20, 0x1a, 0x09, 0x3b, 0xc5, - 0x0e, 0x2b, 0xdf, 0xb2, 0x32, 0x23, 0xc8, 0x07, 0x4f, 0x82, 0xf6, 0xc4, - 0x4d, 0xe1, 0x06, 0x5d, 0x7f, 0xcd, 0xed, 0x9f, 0x30, 0xd3, 0x7f, 0x25, - 0xd3, 0x07, 0xf2, 0xd0, 0x33, 0xff, 0x60, 0xab, 0x3b, 0xa5, 0xfa, 0x92, - 0x15, 0x19, 0xd8, 0x03, 0x21, 0x40, 0x2d, 0x1b, 0xdb, 0xc4, 0x01, 0x2a, - 0x50, 0xba, 0x38, 0x32, 0xd7, 0xe0, 0xd1, 0xc1, 0xb7, 0x5b, 0x58, 0xbd, - 0x05, 0x26, 0x1b, 0x05, 0x16, 0xdb, 0x9d, 0x3d, 0x02, 0xeb, 0x1a, 0x9c, - 0x1a, 0xbc, 0x3b, 0x24, 0x0a, 0x00, 0xc2, 0xbd, 0x06, 0xc1, 0xd3, 0x48, - 0xcb, 0x3d, 0x32, 0xdf, 0xb5, 0xe3, 0xe8, 0x37, 0x1f, 0x33, 0xa3, 0xa3, - 0xd5, 0xdf, 0xe9, 0xb4, 0x1c, 0xbb, 0x0d, 0xbd, 0x0e, 0xf7, 0xb1, 0x4f, - 0xec, 0xcf, 0x16, 0x40, 0x28, 0x18, 0x3f, 0xcf, 0xf5, 0xf2, 0xf7, 0x6a, - 0xc8, 0x07, 0x36, 0xbb, 0xe2, 0xe6, 0x20, 0xe4, 0x10, 0xf7, 0x79, 0x3a, - 0xcb, 0x44, 0xda, 0x09, 0xea, 0xce, 0x14, 0xfd, 0x37, 0xd5, 0xdd, 0xc6, - 0x2a, 0x68, 0xbc, 0xf2, 0x2e, 0x1d, 0xfc, 0xee, 0xdf, 0x95, 0x22, 0x0b, - 0xf2, 0x2a, 0x54, 0x99, 0x04, 0x07, 0xf7, 0x54, 0xcf, 0xe7, 0xd1, 0x99, - 0xf0, 0xfd, 0x05, 0x56, 0xd5, 0x5e, 0xd0, 0xce, 0x2e, 0x94, 0xec, 0xe6, - 0x32, 0x20, 0x17, 0xda, 0xf9, 0x32, 0x2a, 0xf7, 0x53, 0x52, 0xfd, 0xf7, - 0xff, 0x1d, 0x81, 0x2f, 0x3d, 0x05, 0xe2, 0x45, 0xac, 0xaa, 0x43, 0x08, - 0xca, 0xcf, 0xc5, 0x40, 0xe2, 0x3a, 0xed, 0xc5, 0xef, 0x12, 0xf6, 0xdb, - 0xe9, 0x30, 0x48, 0x39, 0x36, 0x58, 0x3e, 0x5b, 0xfb, 0x00, 0xd2, 0x2c, - 0x4c, 0x60, 0x5c, 0x0a, 0x08, 0x56, 0x5d, 0x4e, 0x07, 0x4d, 0xdb, 0xb3, - 0x65, 0x2b, 0x14, 0x20, 0x58, 0xaa, 0xc9, 0xc8, 0xf2, 0x11, 0xf9, 0xcb, - 0x52, 0xbc, 0x41, 0x19, 0x0f, 0x51, 0x1c, 0xb6, 0x28, 0x32, 0xfe, 0x15, - 0x16, 0xf1, 0x3a, 0xf2, 0x17, 0x36, 0x31, 0xef, 0xd3, 0x05, 0x7a, 0x22, - 0x46, 0x46, 0xe8, 0xda, 0x40, 0x44, 0x56, 0xf9, 0x47, 0x1f, 0xbf, 0xd3, - 0xdb, 0x40, 0xff, 0xd8, 0x81, 0xfc, 0x3c, 0x2f, 0x1e, 0xe8, 0xc1, 0xe8, - 0x14, 0xc1, 0xc7, 0x06, 0x3a, 0xf6, 0x0a, 0x30, 0xcf, 0xbc, 0x01, 0xe8, - 0xbb, 0xf5, 0x31, 0xa6, 0xf2, 0xdc, 0x01, 0xc4, 0xda, 0xfb, 0x59, 0xe7, - 0x1f, 0xc3, 0xa8, 0x2f, 0xb8, 0xf7, 0x15, 0x0c, 0xf4, 0xb0, 0x54, 0x13, - 0xcb, 0x66, 0xe9, 0x00, 0x02, 0x4b, 0xce, 0xca, 0x58, 0x30, 0x1f, 0xe6, - 0xee, 0xa3, 0xd1, 0xe2, 0x38, 0xd8, 0xf7, 0xdf, 0xa1, 0x00, 0xf6, 0xf9, - 0x06, 0x5a, 0x24, 0x1c, 0xeb, 0x0b, 0xf2, 0xc4, 0x13, 0xdd, 0x3d, 0xef, - 0xa4, 0x0d, 0x9d, 0x3d, 0x37, 0x14, 0x3b, 0x66, 0xaa, 0x9f, 0x31, 0x10, - 0xce, 0x29, 0x02, 0x04, 0x2a, 0x18, 0xef, 0x2d, 0xd7, 0x28, 0xf7, 0xd9, - 0x4e, 0xc8, 0xf6, 0x34, 0xcd, 0x0f, 0x43, 0x1f, 0xb5, 0x64, 0x2d, 0x0b, - 0x0f, 0x23, 0x29, 0x46, 0xf5, 0xa7, 0x0e, 0x98, 0xb8, 0x6b, 0x81, 0xdc, - 0xf1, 0x01, 0xfa, 0xb6, 0xab, 0x5b, 0xc3, 0xab, 0x8e, 0x02, 0x03, 0xdf, - 0x66, 0x3d, 0xd6, 0x0a, 0xd5, 0x27, 0x03, 0xff, 0xdc, 0xc2, 0xc1, 0x4e, - 0xb7, 0xd5, 0x94, 0x02, 0xf7, 0x28, 0xd6, 0x52, 0xf0, 0xf3, 0xf6, 0xe1, - 0x26, 0xc6, 0xa1, 0xcb, 0x6e, 0x23, 0x3a, 0xc2, 0x4d, 0x9f, 0xe9, 0x65, - 0x2f, 0xf6, 0x29, 0x35, 0xd7, 0x31, 0xe3, 0xf0, 0x33, 0xc3, 0xfb, 0x03, - 0xe3, 0x02, 0x05, 0x18, 0xcf, 0x1f, 0xf5, 0x0c, 0xe9, 0xf3, 0x3b, 0x57, - 0xd2, 0x0c, 0xcf, 0x29, 0x41, 0xbc, 0x81, 0xf7, 0xc0, 0x43, 0xb8, 0x08, - 0xd8, 0x14, 0xd8, 0x0f, 0xda, 0xbd, 0x2b, 0x0a, 0x1c, 0xf1, 0x29, 0x2a, - 0xcb, 0xda, 0x4b, 0xc6, 0xff, 0xdb, 0x1f, 0xc1, 0xc9, 0x50, 0xeb, 0x2a, - 0xd5, 0xfd, 0x37, 0xf0, 0x0c, 0x0c, 0xe8, 0x16, 0xc8, 0xf3, 0x17, 0x05, - 0x31, 0xdd, 0x2e, 0xd1, 0x06, 0x2b, 0xfd, 0x1e, 0x36, 0x31, 0xaf, 0xb5, - 0xfd, 0x17, 0xef, 0x1a, 0xd1, 0x32, 0x22, 0xef, 0x1a, 0xdf, 0x41, 0x0c, - 0xf9, 0xf6, 0x13, 0xc1, 0xd8, 0xf7, 0x2e, 0xcd, 0xe2, 0xed, 0xbc, 0x29, - 0xc3, 0xfb, 0xc9, 0x33, 0xba, 0xf8, 0xc0, 0x67, 0xd9, 0x39, 0xfa, 0xdf, - 0x0f, 0xe4, 0xe6, 0xa0, 0x18, 0xc8, 0x31, 0x41, 0xcb, 0x02, 0xb3, 0xe0, - 0x17, 0x25, 0x57, 0x04, 0x98, 0xd4, 0xad, 0xf2, 0x1a, 0x31, 0x43, 0xd0, - 0x14, 0xb6, 0xc4, 0xba, 0x29, 0x40, 0x8e, 0x74, 0xd2, 0x60, 0xdc, 0x2d, - 0xc1, 0x0e, 0xe6, 0x0e, 0xdd, 0xcd, 0x72, 0x50, 0x65, 0xe5, 0xe6, 0xa0, - 0xf3, 0x29, 0x4c, 0xd7, 0xdd, 0xaf, 0xd6, 0x7f, 0xb7, 0x0f, 0x48, 0x53, - 0x2e, 0xcd, 0xbb, 0xe5, 0xe9, 0xa3, 0x43, 0x61, 0xb1, 0x3b, 0xc1, 0x10, - 0xf2, 0x3a, 0x11, 0xe9, 0xd1, 0xe8, 0x2f, 0xd8, 0x9f, 0x0e, 0x6a, 0xea, - 0xff, 0x11, 0xef, 0xfb, 0x13, 0x23, 0x1e, 0xd9, 0x85, 0xce, 0x6a, 0x23, - 0xa3, 0xd6, 0xf3, 0x08, 0x39, 0xd9, 0xd0, 0xfb, 0xc8, 0x1b, 0xf7, 0x10, - 0xcb, 0x27, 0xf9, 0xc9, 0x07, 0xb6, 0xbf, 0xcf, 0xcb, 0xf3, 0x4b, 0xc6, - 0x08, 0x26, 0xf1, 0x4b, 0x6b, 0x97, 0xe1, 0xe9, 0x3f, 0x99, 0x0c, 0xc7, - 0x17, 0x26, 0x98, 0xf0, 0x2a, 0xd9, 0x43, 0x2d, 0x46, 0xe5, 0x10, 0x3d, - 0x53, 0xde, 0x4f, 0xac, 0xee, 0xa4, 0xcd, 0xe3, 0x19, 0x3c, 0x98, 0xd4, - 0x3d, 0xec, 0x76, 0xb8, 0xff, 0xc5, 0xf0, 0xdd, 0x0a, 0xf3, 0x0f, 0xaf, - 0x19, 0xfe, 0x0d, 0xbd, 0x12, 0xc1, 0xae, 0xd8, 0x0c, 0x4a, 0xf8, 0x07, - 0x0d, 0xf4, 0xe8, 0xf4, 0x59, 0x34, 0x2b, 0x17, 0x0b, 0x29, 0x04, 0xdf, - 0x0c, 0x25, 0xde, 0xcd, 0x2a, 0xdb, 0x7f, 0xd0, 0xd9, 0xb4, 0xb5, 0xb6, - 0xd1, 0xfa, 0xf6, 0x43, 0xc4, 0x99, 0xec, 0xf7, 0x3f, 0x27, 0xba, 0x4e, - 0x52, 0x1c, 0x39, 0x3e, 0x43, 0xf6, 0x26, 0x30, 0x09, 0xbb, 0x09, 0x5e, - 0x17, 0x2f, 0xf6, 0x4e, 0x24, 0x0b, 0x4c, 0xf3, 0x54, 0x3f, 0xe9, 0x42, - 0xe8, 0xd5, 0xf7, 0x25, 0xd9, 0xf7, 0x50, 0x10, 0x1d, 0xf6, 0xed, 0x47, - 0xdc, 0x26, 0x4f, 0x49, 0xe9, 0x05, 0x1b, 0xeb, 0x73, 0x81, 0xab, 0x2f, - 0xef, 0xf9, 0xfc, 0xcd, 0xf0, 0xc6, 0x1f, 0x4e, 0x00, 0x24, 0xe5, 0x32, - 0xd5, 0xbb, 0xbf, 0xf0, 0x18, 0x84, 0x36, 0xdb, 0x00, 0xd0, 0x9c, 0x16, - 0x3d, 0x1a, 0x2f, 0xf6, 0xf9, 0x3f, 0x13, 0xdb, 0x3b, 0x3a, 0x35, 0xb8, - 0x1b, 0xce, 0xb1, 0xae, 0xee, 0x02, 0x05, 0xbf, 0xdc, 0xa9, 0xdb, 0xf7, - 0x52, 0xd5, 0x58, 0x53, 0xd0, 0xc3, 0xe5, 0x47, 0x3b, 0xfa, 0x4d, 0xd7, - 0x2c, 0x15, 0xe7, 0x0d, 0xdb, 0x75, 0xc8, 0x02, 0x16, 0xae, 0x0c, 0x11, - 0xc2, 0x02, 0xed, 0x39, 0xa7, 0x46, 0x3b, 0xac, 0x29, 0x4f, 0xfe, 0x40, - 0x3c, 0xf1, 0x00, 0x46, 0x40, 0x19, 0xbf, 0x07, 0x3d, 0x30, 0xad, 0xb1, - 0xc3, 0xe2, 0xb4, 0x12, 0x12, 0xda, 0x20, 0x51, 0x19, 0x27, 0xd8, 0xdd, - 0x4c, 0x2b, 0xee, 0x2d, 0x06, 0xb8, 0xc1, 0x49, 0x15, 0x1a, 0x1e, 0x51, - 0x4d, 0x29, 0x19, 0x06, 0x19, 0x2c, 0x26, 0x17, 0xf9, 0x60, 0x19, 0xb3, - 0xe4, 0x0b, 0x94, 0x51, 0x18, 0xc7, 0x44, 0xfa, 0xc0, 0xe3, 0x5b, 0xdc, - 0x1d, 0x28, 0x3d, 0xee, 0x1d, 0x29, 0x63, 0x1e, 0x13, 0xc7, 0x99, 0x0b, - 0x64, 0xa4, 0x3f, 0x13, 0xce, 0x60, 0x81, 0x1e, 0xec, 0x59, 0xe4, 0x79, - 0xb0, 0x15, 0xce, 0x3c, 0xc9, 0xaf, 0x0d, 0xa5, 0x54, 0x41, 0xab, 0x94, - 0x3a, 0xc3, 0xc7, 0xe3, 0x10, 0xc5, 0xd3, 0x25, 0xab, 0xb9, 0xb0, 0x06, - 0xd9, 0x38, 0x42, 0xea, 0xfc, 0x49, 0xc8, 0x6b, 0xba, 0xc9, 0x8f, 0x88, - 0x19, 0x68, 0x11, 0x58, 0x02, 0x23, 0xfb, 0xc4, 0xd6, 0xbc, 0x62, 0xb2, - 0x11, 0xe2, 0x0f, 0xed, 0x29, 0xb9, 0xdf, 0xa9, 0xfe, 0x06, 0x38, 0x22, - 0xb6, 0x51, 0xe1, 0x2d, 0x5b, 0xa0, 0xb0, 0x35, 0xed, 0xcf, 0x0d, 0xc6, - 0x00, 0xac, 0xf2, 0x0c, 0x1f, 0xdd, 0xc8, 0xee, 0x02, 0x13, 0xe2, 0xdd, - 0xe1, 0x1c, 0xe8, 0x40, 0xd9, 0xfd, 0xfd, 0xcc, 0x04, 0xb8, 0x1f, 0x0e, - 0x58, 0x03, 0x03, 0x0d, 0xe8, 0xe4, 0x1f, 0x20, 0x07, 0x10, 0x04, 0xf4, - 0x25, 0x0c, 0xd4, 0x14, 0x89, 0xc4, 0x1a, 0x34, 0xd1, 0x0c, 0xc2, 0x47, - 0x05, 0x5b, 0xb7, 0x15, 0x10, 0xde, 0x1d, 0x4e, 0xc9, 0xad, 0x50, 0x02, - 0xf6, 0xe2, 0x47, 0xe3, 0x27, 0xd8, 0x28, 0xc6, 0xe0, 0xfe, 0x21, 0x33, - 0xd7, 0x27, 0xd8, 0xe6, 0x2b, 0xd2, 0x19, 0xd9, 0xfc, 0x3e, 0x09, 0xcd, - 0x15, 0x3f, 0xf7, 0x22, 0x2d, 0xf9, 0x15, 0x1d, 0xc5, 0x25, 0xca, 0x3a, - 0x1c, 0x01, 0xef, 0xa3, 0xc5, 0x45, 0xac, 0x2d, 0xfe, 0x14, 0xfc, 0xea, - 0xe9, 0xc7, 0x13, 0xdc, 0x34, 0xe5, 0xe5, 0xc2, 0x10, 0xf7, 0x12, 0x21, - 0x07, 0x2a, 0x81, 0xf4, 0xe7, 0xb8, 0xe7, 0x22, 0x0e, 0x1e, 0x44, 0x4e, - 0x2e, 0xe6, 0x66, 0x01, 0x3e, 0xcf, 0xe6, 0x33, 0x32, 0xc6, 0x26, 0xea, - 0x19, 0x0a, 0x53, 0x51, 0xfe, 0xee, 0xcd, 0xfd, 0xda, 0x9d, 0x37, 0xb4, - 0x52, 0x57, 0x23, 0xad, 0x69, 0x00, 0xad, 0xdd, 0x1f, 0xfe, 0x3a, 0xf6, - 0xe6, 0x90, 0x3b, 0x53, 0x49, 0xaf, 0x4e, 0x0f, 0xd0, 0x41, 0x5d, 0x38, - 0x26, 0xab, 0x3e, 0xdd, 0xd6, 0x14, 0xa2, 0xd0, 0x07, 0x1c, 0xf2, 0x31, - 0x58, 0xd7, 0xed, 0xd6, 0xd2, 0x09, 0xe7, 0xea, 0x78, 0x34, 0xf9, 0x3d, - 0xb3, 0xf0, 0x1f, 0x36, 0xf8, 0x2e, 0x03, 0x6b, 0x28, 0x1a, 0xc4, 0xdf, - 0xa7, 0xa4, 0x2e, 0xa0, 0x32, 0x40, 0x17, 0xcf, 0x2b, 0xf7, 0xea, 0xb8, - 0x16, 0x0a, 0x30, 0xc0, 0x09, 0xa2, 0xfe, 0x97, 0x96, 0xc7, 0xe7, 0x81, - 0x43, 0x11, 0xa5, 0x3c, 0xb2, 0x3f, 0x31, 0xfb, 0x5b, 0xdf, 0x12, 0x54, - 0xe4, 0x36, 0x02, 0x9e, 0x37, 0x1f, 0x3e, 0xcf, 0x23, 0xe7, 0x01, 0x02, - 0x06, 0x14, 0xed, 0xd5, 0xe5, 0x21, 0xbc, 0x35, 0xf6, 0x32, 0x12, 0x08, - 0x38, 0x13, 0xf9, 0x81, 0x1d, 0xfe, 0xf3, 0x0f, 0xfa, 0xbd, 0xe0, 0xbb, - 0x09, 0xe9, 0xec, 0x50, 0xc7, 0xc0, 0xd4, 0x04, 0xd7, 0xec, 0x27, 0x25, - 0x33, 0x61, 0x1c, 0xfc, 0xe2, 0xdb, 0xf2, 0xb8, 0xcc, 0xc7, 0x37, 0x29, - 0x34, 0x42, 0xde, 0xa0, 0xa6, 0xd5, 0x45, 0xe7, 0xd8, 0x1e, 0x2d, 0x30, - 0x2d, 0xf0, 0xba, 0x5c, 0x10, 0xd1, 0x65, 0xb3, 0x38, 0x12, 0xc2, 0xf9, - 0x17, 0x3a, 0x0d, 0x5c, 0xc1, 0xb6, 0x9f, 0x17, 0xb6, 0xe8, 0x6d, 0x21, - 0x50, 0x23, 0x1b, 0xa0, 0x00, 0xf0, 0xf5, 0x29, 0xf6, 0x09, 0xcc, 0x61, - 0x09, 0xdd, 0x04, 0xaa, 0x17, 0xd1, 0xcd, 0x2a, 0xe8, 0x11, 0x30, 0xde, - 0x05, 0xdc, 0x07, 0x05, 0x52, 0x41, 0xe0, 0x1f, 0x58, 0x19, 0xf5, 0xf1, - 0x0f, 0xac, 0xb0, 0xeb, 0xcd, 0xde, 0x8a, 0x0f, 0x3b, 0x3c, 0xb3, 0x3f, - 0xed, 0x29, 0x01, 0x7f, 0xa8, 0xd7, 0x36, 0x06, 0x0f, 0x07, 0x0f, 0x1a, - 0xd1, 0x9a, 0x25, 0xb2, 0x1c, 0xf9, 0x2e, 0xaa, 0x42, 0x48, 0x15, 0xb8, - 0x2a, 0x31, 0x3b, 0xd6, 0xf0, 0xe4, 0x18, 0x25, 0x5a, 0xcd, 0x33, 0xfa, - 0x3c, 0xe5, 0x27, 0xee, 0xef, 0xf3, 0xc1, 0xff, 0xd2, 0x19, 0x2e, 0x10, - 0xb3, 0x56, 0x31, 0x16, 0x0b, 0xcf, 0x2b, 0x15, 0xeb, 0xc6, 0xe8, 0xa2, - 0x15, 0x4d, 0x16, 0x42, 0x44, 0xe5, 0x3e, 0x2a, 0xa2, 0xc5, 0x75, 0x93, - 0x30, 0x1d, 0xc3, 0x25, 0x01, 0x36, 0xd1, 0xf8, 0x58, 0x28, 0xcd, 0x59, - 0xf4, 0xc0, 0x13, 0xa2, 0x29, 0x52, 0xc7, 0x2c, 0xb4, 0xfc, 0xc5, 0xf6, - 0xc1, 0xb6, 0xc5, 0xcd, 0xfa, 0x2a, 0x45, 0x40, 0x08, 0x37, 0xee, 0x73, - 0xd5, 0x2b, 0x85, 0x36, 0xcc, 0xf0, 0x9e, 0x24, 0x0b, 0xf3, 0x2d, 0xff, - 0xff, 0xcb, 0xc7, 0xce, 0x2c, 0x1e, 0xc1, 0xe0, 0xff, 0xd1, 0xf4, 0x55, - 0x31, 0xfc, 0x2d, 0xf5, 0x3e, 0x34, 0xe6, 0x13, 0x07, 0x97, 0x03, 0xe3, - 0xe5, 0x9c, 0xb1, 0xf4, 0xf2, 0xee, 0x0a, 0xd4, 0x26, 0x31, 0xd0, 0x0c, - 0xc1, 0x30, 0xc9, 0xd7, 0x31, 0x03, 0x16, 0x5b, 0xf8, 0x55, 0x8d, 0x0a, - 0xe4, 0x9e, 0x7f, 0x7f, 0x2b, 0xff, 0x2f, 0x33, 0xdc, 0x55, 0x6e, 0x50, - 0x45, 0x02, 0x51, 0xa1, 0x14, 0x1e, 0xc9, 0x27, 0x29, 0x1c, 0xd2, 0xa3, - 0x4b, 0xd9, 0xe6, 0x5a, 0xe3, 0x31, 0x57, 0x4b, 0xd7, 0x37, 0xc2, 0xd9, - 0x36, 0x4b, 0x0c, 0xf8, 0xd3, 0xf7, 0xe1, 0x3f, 0x07, 0xa9, 0xce, 0xc7, - 0x02, 0x14, 0x15, 0xd4, 0xfd, 0xf0, 0x10, 0x19, 0xbb, 0xdf, 0xde, 0xef, - 0xe8, 0x55, 0x67, 0x15, 0x18, 0xb7, 0x9f, 0x60, 0x35, 0xaf, 0xb2, 0x2a, - 0xb7, 0x1b, 0x8f, 0xed, 0xc8, 0x11, 0x33, 0xce, 0x02, 0xc9, 0xd3, 0xd9, - 0xeb, 0xcc, 0x06, 0x1a, 0xdc, 0x26, 0xe0, 0xf2, 0xa9, 0x13, 0x51, 0x2a, - 0x58, 0xdd, 0x46, 0x0d, 0x7f, 0xb2, 0x3b, 0x6d, 0x5d, 0xee, 0xbd, 0x07, - 0x04, 0x3b, 0xa7, 0xdd, 0x40, 0x23, 0x35, 0xfb, 0xf2, 0x2f, 0x9c, 0xdb, - 0xdc, 0xde, 0x66, 0xff, 0xb8, 0x1e, 0x8d, 0xff, 0x34, 0x0d, 0x0f, 0xeb, - 0xef, 0xf5, 0x4b, 0xb6, 0x65, 0x52, 0x43, 0x04, 0x56, 0x24, 0x30, 0xe4, - 0xbd, 0x37, 0x29, 0xce, 0x1a, 0xc4, 0x35, 0x91, 0xfb, 0x12, 0x27, 0x25, - 0xca, 0x62, 0xde, 0xfc, 0x2b, 0xe6, 0xc9, 0x49, 0xb9, 0x1a, 0xf6, 0x25, - 0xc1, 0xfc, 0x3c, 0x39, 0x32, 0x0b, 0xd8, 0xc6, 0x1e, 0x1f, 0x26, 0x2c, - 0x2d, 0x4d, 0xf5, 0xd6, 0x97, 0xc9, 0xfd, 0x53, 0x0a, 0x05, 0xdc, 0x25, - 0xb1, 0xf2, 0x93, 0x20, 0x39, 0xfc, 0xd8, 0x20, 0x0d, 0x42, 0xed, 0x3e, - 0x09, 0xc7, 0x5f, 0x58, 0x0a, 0x75, 0x4b, 0x02, 0xe0, 0xe4, 0x17, 0x98, - 0xcb, 0xc5, 0xef, 0x66, 0x34, 0x59, 0xfa, 0xf7, 0x17, 0xf8, 0x60, 0xe6, - 0xf1, 0xfc, 0xd4, 0xf1, 0x83, 0x2b, 0x11, 0x38, 0xc7, 0x9e, 0x0c, 0x13, - 0x1d, 0xc8, 0xea, 0xd6, 0xb8, 0xcd, 0xa0, 0x30, 0x1e, 0xc6, 0x9f, 0x39, - 0xfa, 0x41, 0x2c, 0x7c, 0x30, 0xd5, 0xd5, 0x81, 0x0c, 0x2d, 0x02, 0xa4, - 0x25, 0x1f, 0xfa, 0xd7, 0xf8, 0xfd, 0xd6, 0xfa, 0xe9, 0xb7, 0xb6, 0xa1, - 0x1c, 0x6f, 0xd4, 0xfd, 0xf5, 0xce, 0xe8, 0xf7, 0xe0, 0xe5, 0xde, 0x4c, - 0xb7, 0x61, 0xc2, 0x5d, 0xfe, 0x11, 0x3b, 0x1d, 0x0f, 0x4a, 0xf4, 0x4a, - 0xe6, 0xfd, 0x47, 0x9c, 0xa3, 0xaa, 0x68, 0x7c, 0xa8, 0x69, 0x83, 0x9a, - 0x51, 0xfc, 0x43, 0x4d, 0x66, 0x5b, 0xe5, 0xf1, 0xde, 0x09, 0xcc, 0xf7, - 0xc3, 0x02, 0xd3, 0x71, 0x7b, 0x3f, 0x3f, 0x28, 0x2a, 0xcf, 0xd0, 0x11, - 0x1f, 0x5d, 0xd7, 0xd9, 0xf3, 0x31, 0x21, 0xbe, 0xf7, 0xe6, 0x07, 0x1a, - 0xf4, 0x31, 0xd1, 0x09, 0xc2, 0xed, 0xa4, 0xee, 0x3c, 0x10, 0xb3, 0xb6, - 0xeb, 0x12, 0x12, 0x0b, 0xca, 0xad, 0xed, 0x13, 0xd8, 0xb8, 0xc2, 0xe9, - 0x2b, 0xe3, 0xc3, 0x1d, 0xea, 0x45, 0x36, 0x1d, 0x05, 0xff, 0x9c, 0x64, - 0x09, 0xfa, 0x20, 0xf9, 0x2c, 0xb2, 0x25, 0x1a, 0xc8, 0x23, 0xf1, 0xd5, - 0x25, 0x19, 0x02, 0x07, 0xe7, 0x13, 0xd3, 0xb4, 0xb5, 0xc0, 0xc5, 0x47, - 0xd2, 0x26, 0x0c, 0xed, 0x24, 0x04, 0xd3, 0x33, 0x2a, 0x0c, 0xeb, 0x5a, - 0xff, 0xcf, 0x5a, 0xdc, 0x46, 0x3b, 0x0c, 0xdf, 0x41, 0xf5, 0x3c, 0xbe, - 0x09, 0x16, 0x19, 0xe8, 0xcc, 0xe8, 0xfd, 0xd2, 0xaa, 0x1d, 0x0e, 0x17, - 0x27, 0x4d, 0x04, 0x81, 0x09, 0xc7, 0xe7, 0x3f, 0x31, 0x28, 0x2b, 0xce, - 0x12, 0xd9, 0x0c, 0x1a, 0xa7, 0x20, 0x50, 0x24, 0x05, 0x1d, 0x6d, 0x4b, - 0x3b, 0x51, 0x00, 0x12, 0xf9, 0xee, 0xe0, 0x26, 0xcb, 0xdb, 0xe5, 0xbe, - 0xfc, 0x94, 0x38, 0x2e, 0x8a, 0x2c, 0xd2, 0xdb, 0x37, 0xce, 0xd5, 0x0e, - 0x22, 0xc1, 0x65, 0x08, 0x27, 0xdf, 0xf0, 0xfc, 0x1f, 0xcd, 0x45, 0xf3, - 0x25, 0x44, 0x3e, 0xe0, 0x2c, 0x19, 0x02, 0xa0, 0xb3, 0x2d, 0xa6, 0xde, - 0x4f, 0x00, 0x3f, 0x65, 0xfc, 0x14, 0x31, 0xb9, 0xf3, 0x0c, 0x0f, 0x54, - 0x3d, 0x31, 0x7f, 0x3f, 0x01, 0x2a, 0xe4, 0x14, 0xdc, 0xee, 0xb0, 0x41, - 0x5f, 0xff, 0xdc, 0xad, 0xa1, 0x1a, 0x05, 0x16, 0x6a, 0x3e, 0x93, 0x10, - 0x57, 0x2a, 0x67, 0x1b, 0x61, 0xdf, 0x5e, 0x49, 0x6a, 0x00, 0x03, 0x07, - 0x00, 0x05, 0x74, 0x55, 0xc1, 0x1f, 0xb6, 0x36, 0xf6, 0x10, 0xb3, 0x89, - 0x7b, 0x8a, 0x6f, 0xb0, 0xae, 0x11, 0x29, 0x31, 0x3a, 0x6a, 0x60, 0xaa, - 0xba, 0xbc, 0xb3, 0x61, 0xdc, 0xf7, 0xf9, 0x03, 0x57, 0x59, 0xc4, 0x2c, - 0x05, 0x43, 0xb7, 0xe0, 0x41, 0xcc, 0x25, 0x31, 0xea, 0x3c, 0x3c, 0x54, - 0xc2, 0x22, 0xb5, 0xd9, 0xce, 0x29, 0x14, 0x07, 0x4c, 0x52, 0x60, 0xef, - 0x5a, 0x17, 0xe0, 0x35, 0x07, 0x16, 0x34, 0xdb, 0xf8, 0x1e, 0x57, 0xce, - 0x61, 0x3a, 0xcd, 0x14, 0x57, 0xf6, 0xa8, 0x31, 0x32, 0x42, 0xab, 0x39, - 0x6b, 0xd9, 0xde, 0x42, 0x19, 0x9d, 0xa1, 0x3a, 0xc9, 0xfa, 0x53, 0xcf, - 0xca, 0xb7, 0x51, 0x2e, 0x1b, 0xa7, 0xe9, 0x07, 0x42, 0xfc, 0x3c, 0xd9, - 0x08, 0x35, 0xf5, 0x0a, 0x62, 0x14, 0x18, 0x3f, 0x09, 0x73, 0x7f, 0xc5, - 0xf1, 0xe1, 0xe2, 0x15, 0xee, 0xc0, 0xcd, 0xe3, 0xc9, 0xb7, 0x27, 0x43, - 0xde, 0xab, 0x48, 0x3d, 0x20, 0x56, 0xae, 0x34, 0xd7, 0x99, 0x18, 0x5e, - 0x48, 0xfc, 0xa2, 0xf8, 0x2a, 0x02, 0xce, 0x1e, 0x46, 0x0d, 0x1c, 0xdd, - 0xca, 0xe5, 0x12, 0xec, 0x11, 0xd8, 0xc7, 0x1f, 0xdb, 0xfc, 0x21, 0xe8, - 0xdf, 0xeb, 0xd6, 0xec, 0x15, 0xad, 0x07, 0xc2, 0x3c, 0xfe, 0x14, 0xd5, - 0xdf, 0x5d, 0x65, 0xdb, 0x22, 0x0e, 0xbd, 0x36, 0xc7, 0x27, 0x2d, 0x0f, - 0xd9, 0xd7, 0x2e, 0x3f, 0x4d, 0xfc, 0xd4, 0xe3, 0xcd, 0xc1, 0xe7, 0xca, - 0x22, 0xec, 0x95, 0x81, 0x5b, 0xed, 0x44, 0xb9, 0xb5, 0xc0, 0x0c, 0x2b, - 0xfe, 0x08, 0x30, 0xf6, 0xef, 0xf2, 0x3d, 0x21, 0xd4, 0xa4, 0x1e, 0xcc, - 0xf0, 0xfe, 0xd4, 0xea, 0xf0, 0x1b, 0xe2, 0x36, 0x31, 0x1b, 0x29, 0xcd, - 0x52, 0xda, 0x27, 0x03, 0x07, 0xfb, 0x11, 0xf9, 0xda, 0xc7, 0x09, 0x09, - 0x1c, 0x44, 0x3a, 0xef, 0xd9, 0xca, 0xbb, 0x2c, 0x1d, 0x30, 0x15, 0x0f, - 0x07, 0xd5, 0x12, 0xc4, 0x2a, 0x2d, 0xd7, 0xca, 0xf6, 0x16, 0x18, 0xf7, - 0x16, 0xf2, 0x1b, 0xc7, 0xc9, 0xba, 0xaf, 0x09, 0x4d, 0xf3, 0x2c, 0xa4, - 0x58, 0xf1, 0x1e, 0xe3, 0x8c, 0xe3, 0x93, 0x6c, 0xc2, 0xab, 0xe7, 0x96, - 0x03, 0x09, 0x7f, 0x2e, 0xa0, 0x48, 0x0e, 0x23, 0x3d, 0x35, 0x64, 0xa4, - 0x0e, 0x2d, 0x3b, 0x01, 0xcf, 0x55, 0x47, 0xfa, 0xe5, 0xd1, 0x2b, 0x49, - 0x34, 0xfb, 0xa3, 0xd6, 0xc0, 0xf5, 0x1d, 0x07, 0xe7, 0x11, 0xa6, 0xf5, - 0xf0, 0xed, 0xa4, 0x68, 0x7d, 0x13, 0x3c, 0xee, 0x44, 0x41, 0x40, 0x4a, - 0x1c, 0xbc, 0xa8, 0x1a, 0xc7, 0xfe, 0xa7, 0xc5, 0xa8, 0xe5, 0xb5, 0xb1, - 0x77, 0x5c, 0xf9, 0xdf, 0xbe, 0xa3, 0x12, 0xc6, 0x38, 0x56, 0xe8, 0x08, - 0xa7, 0xe2, 0x2d, 0xfa, 0x64, 0x06, 0xd4, 0xc8, 0x1e, 0x06, 0xdb, 0xc2, - 0xff, 0x56, 0x3d, 0xc5, 0x66, 0xe5, 0x02, 0x30, 0x4f, 0x4e, 0xd9, 0xb5, - 0x52, 0xd0, 0x53, 0x0f, 0xba, 0x4b, 0x9e, 0xfc, 0x28, 0x33, 0x28, 0xfd, - 0x1d, 0xc9, 0x6e, 0x56, 0xc9, 0x59, 0xeb, 0x3d, 0x25, 0x2c, 0xe0, 0xe1, - 0xd8, 0xe9, 0xaa, 0x7f, 0x06, 0x10, 0x04, 0xd2, 0xaf, 0x5a, 0x13, 0x02, - 0x05, 0xbb, 0xbb, 0xed, 0xdb, 0x53, 0x14, 0x05, 0x33, 0xd3, 0x39, 0xed, - 0xfd, 0xb8, 0xab, 0x3a, 0xb7, 0x2e, 0xf7, 0x08, 0x18, 0x91, 0x2c, 0xd4, - 0xbf, 0xef, 0x0f, 0x47, 0xf0, 0xad, 0x01, 0xc4, 0xf2, 0xee, 0xab, 0xe1, - 0x30, 0x8f, 0xda, 0x1c, 0xc6, 0x1a, 0x5c, 0xf2, 0xf5, 0xe9, 0xb4, 0x20, - 0xe9, 0xd9, 0x59, 0xb5, 0xb2, 0x35, 0xfa, 0x02, 0x51, 0xed, 0xfc, 0xd5, - 0xe4, 0x0a, 0xed, 0xe2, 0xfc, 0x38, 0xe2, 0xd8, 0x55, 0xfe, 0x47, 0xf3, - 0xe6, 0x41, 0xe8, 0xee, 0x30, 0xf6, 0xfa, 0xf2, 0x3e, 0x1a, 0xd2, 0x27, - 0xf2, 0x1c, 0xbd, 0xfa, 0xc5, 0x0f, 0x0e, 0xbf, 0xd3, 0x5c, 0x13, 0x25, - 0x40, 0x2b, 0xff, 0x1a, 0xeb, 0xec, 0xc1, 0xe1, 0x24, 0xd5, 0xcd, 0x34, - 0x03, 0x19, 0xe1, 0x2e, 0x19, 0xfd, 0xb9, 0xd1, 0xc3, 0xd3, 0xd5, 0x66, - 0xe9, 0xd4, 0x36, 0xf3, 0x19, 0xa2, 0x15, 0xff, 0xca, 0x05, 0x1a, 0xda, - 0xd0, 0x09, 0x5d, 0xc3, 0xe0, 0x4b, 0x04, 0x28, 0xe4, 0x4c, 0x3d, 0x09, - 0xcb, 0x44, 0x01, 0x13, 0xb9, 0xe4, 0xd7, 0xe5, 0x0e, 0x6a, 0x4b, 0xf2, - 0x0a, 0xd3, 0x05, 0xed, 0x44, 0x15, 0x03, 0xf0, 0x2d, 0x12, 0xea, 0x26, - 0x18, 0xb8, 0xd2, 0x46, 0x25, 0x31, 0xfe, 0xc9, 0x16, 0xdb, 0xee, 0x3f, - 0x52, 0xd8, 0xea, 0xc4, 0x16, 0xce, 0xcb, 0xcc, 0x81, 0xb0, 0xf7, 0x15, - 0x05, 0x1a, 0x06, 0x25, 0x09, 0xb6, 0x0d, 0xe7, 0x55, 0xe9, 0xcc, 0xf3, - 0x1c, 0x37, 0x31, 0xb2, 0x0a, 0x04, 0x16, 0x1c, 0x72, 0xee, 0xfb, 0x1f, - 0x4c, 0x62, 0xbb, 0xbb, 0xf4, 0xf3, 0x08, 0xda, 0x17, 0xee, 0xb8, 0x20, - 0xdd, 0xd0, 0x54, 0xbd, 0xb3, 0xd9, 0xc5, 0xe1, 0xa4, 0x97, 0x57, 0x54, - 0x5e, 0xe3, 0x16, 0x9a, 0xaf, 0x05, 0xdc, 0x6c, 0x63, 0x2e, 0x52, 0x35, - 0xa8, 0x3d, 0x63, 0x38, 0xd5, 0x4a, 0xe3, 0xb1, 0x22, 0xdc, 0xee, 0x3c, - 0x00, 0xce, 0x65, 0xcd, 0xc5, 0x17, 0xbe, 0xd1, 0xfb, 0x06, 0x3c, 0x22, - 0xde, 0x26, 0xd1, 0xad, 0xbe, 0x50, 0x20, 0x52, 0x1c, 0xc7, 0x3e, 0xc5, - 0xda, 0x29, 0xe0, 0xe8, 0x63, 0x56, 0xbe, 0xd4, 0x36, 0x1c, 0xfb, 0x2b, - 0xbc, 0x35, 0xd9, 0x4d, 0xb6, 0xbb, 0xdb, 0x82, 0xe4, 0x3a, 0x45, 0xdf, - 0x59, 0x3a, 0xf0, 0x54, 0xb8, 0x40, 0xd8, 0xd5, 0x81, 0x1d, 0x0e, 0xa7, - 0x48, 0xd7, 0x5e, 0x12, 0xcf, 0xde, 0x08, 0x2e, 0xe5, 0x0d, 0x63, 0x22, - 0xfe, 0x50, 0x36, 0xe7, 0xf5, 0x28, 0x45, 0x68, 0x12, 0x4a, 0xe0, 0xc4, - 0xea, 0x00, 0x61, 0xea, 0xcd, 0x0a, 0x3a, 0xef, 0xce, 0xe7, 0x06, 0xe5, - 0x2a, 0xb8, 0xbd, 0xb8, 0xd4, 0xec, 0x3d, 0x3f, 0xc7, 0x05, 0x06, 0xcf, - 0xfe, 0xfb, 0x2c, 0xb5, 0x66, 0x1e, 0x62, 0x2a, 0x6d, 0x2e, 0xee, 0xfd, - 0x00, 0x81, 0x35, 0xe5, 0xc7, 0xc0, 0xdc, 0xe5, 0xe4, 0x8c, 0x1c, 0xff, - 0x25, 0xba, 0xfb, 0xc1, 0xfe, 0xdd, 0xf0, 0x12, 0xd1, 0x36, 0x56, 0xe2, - 0xf6, 0xd6, 0xec, 0x18, 0x07, 0xf7, 0xba, 0xe5, 0xd9, 0xff, 0x9c, 0xdd, - 0x93, 0x27, 0xc7, 0x36, 0xbe, 0x2b, 0xd2, 0x05, 0xe7, 0x37, 0x52, 0x5c, - 0x55, 0xd6, 0x13, 0xf3, 0xfd, 0x57, 0xad, 0x60, 0xf3, 0x4f, 0x18, 0x40, - 0x62, 0xc2, 0xa9, 0xc4, 0xfc, 0x41, 0xfa, 0x04, 0xc8, 0x35, 0x3d, 0xdd, - 0x46, 0x91, 0xf0, 0x3f, 0x43, 0x15, 0xce, 0x76, 0x25, 0x00, 0x9d, 0x05, - 0x10, 0xec, 0x12, 0xb5, 0xba, 0x25, 0x08, 0xa0, 0xc8, 0x31, 0x2f, 0xc4, - 0x14, 0xdb, 0xf7, 0xe6, 0x54, 0x07, 0xc0, 0xea, 0xc2, 0xd4, 0x1c, 0xca, - 0x19, 0xaa, 0x07, 0x92, 0x1e, 0x3d, 0xf4, 0x44, 0x24, 0x28, 0x4a, 0x3f, - 0x32, 0x59, 0xf4, 0x4c, 0xc7, 0xb3, 0xec, 0xdd, 0xcf, 0xce, 0x3e, 0x4f, - 0xe9, 0xe5, 0x2c, 0xe2, 0x33, 0x01, 0xbb, 0xb8, 0xab, 0x64, 0x44, 0x47, - 0xc5, 0xde, 0xf0, 0x8e, 0x10, 0x1d, 0x1e, 0x23, 0x83, 0xd9, 0xad, 0x47, - 0x5f, 0x1d, 0xfa, 0xb3, 0xbb, 0xd0, 0xd7, 0xca, 0xdb, 0x06, 0x73, 0xc8, - 0xbc, 0xc6, 0x0e, 0x44, 0x3a, 0xa7, 0x54, 0xce, 0x45, 0xc3, 0x26, 0xf6, - 0xe8, 0xc3, 0x39, 0x19, 0x35, 0x0c, 0x0f, 0xcb, 0xd8, 0x02, 0xa3, 0x9b, - 0x00, 0x0f, 0xe4, 0x43, 0x1b, 0xda, 0x28, 0x4f, 0x38, 0x2f, 0x44, 0x81, - 0x47, 0xc4, 0xd1, 0x49, 0xa8, 0x44, 0x47, 0x1c, 0xc4, 0xf3, 0xf5, 0x1a, - 0x4c, 0xcf, 0x4b, 0x34, 0xd9, 0x5c, 0x45, 0x47, 0xfc, 0xb3, 0xcf, 0x31, - 0x30, 0xc8, 0xb7, 0xbe, 0x15, 0x2d, 0xbc, 0xe6, 0xf4, 0x23, 0x47, 0x32, - 0x21, 0x1a, 0x28, 0x1d, 0x1d, 0x49, 0x53, 0xf1, 0x12, 0x0f, 0xc5, 0xff, - 0x47, 0x09, 0xca, 0xd9, 0xf1, 0x8e, 0xd2, 0xa3, 0x5f, 0xe9, 0xe2, 0x2d, - 0x19, 0x22, 0xdf, 0x47, 0x3f, 0xb9, 0x34, 0x86, 0x2d, 0x86, 0x27, 0x13, - 0x2a, 0x0f, 0x23, 0x1a, 0x5a, 0xdd, 0x1d, 0x0e, 0x13, 0xfe, 0x36, 0xbf, - 0xe4, 0x10, 0x1f, 0x21, 0x26, 0xb3, 0xb1, 0xb8, 0xc7, 0xf6, 0x00, 0xf7, - 0xda, 0x2e, 0xd4, 0x15, 0x4c, 0x09, 0xd8, 0xf5, 0xe9, 0x33, 0x81, 0x32, - 0xbc, 0x13, 0xd6, 0xf8, 0xee, 0xb6, 0x02, 0x22, 0x0b, 0xd3, 0x04, 0xd3, - 0x29, 0x0e, 0x05, 0x20, 0x26, 0x98, 0x10, 0x11, 0x41, 0xc5, 0x0c, 0x3c, - 0x45, 0xdd, 0xaa, 0xf2, 0xd8, 0x0f, 0xc1, 0x19, 0x48, 0x75, 0x61, 0x96, - 0x06, 0x3e, 0xd6, 0x31, 0x1d, 0xb0, 0x1c, 0x1b, 0xeb, 0xf4, 0x2a, 0xba, - 0x71, 0x4e, 0xdc, 0x33, 0xde, 0x39, 0xcb, 0x4b, 0xe6, 0xe9, 0x2a, 0xea, - 0x4e, 0x01, 0x2b, 0xac, 0x57, 0xe3, 0x07, 0x38, 0x1c, 0xbc, 0x3f, 0xf7, - 0xbb, 0xc8, 0xf9, 0xbe, 0xb3, 0xc7, 0x10, 0x9e, 0xe4, 0x29, 0x31, 0x1c, - 0xf4, 0xbc, 0xb1, 0x2c, 0xd4, 0xe7, 0xb9, 0x5b, 0x35, 0xe0, 0xd1, 0xb8, - 0xf3, 0x1a, 0x30, 0x17, 0xd9, 0x46, 0xb7, 0x81, 0xf8, 0x2f, 0x4d, 0xbc, - 0x34, 0xba, 0xea, 0x5a, 0xca, 0xf8, 0xd8, 0x45, 0x01, 0x22, 0x4a, 0x31, - 0x29, 0xbe, 0xf9, 0x4a, 0xcf, 0xa9, 0xb9, 0x2d, 0x36, 0xb7, 0xd3, 0xde, - 0x18, 0xf0, 0x40, 0xb5, 0x05, 0xc8, 0x72, 0x07, 0xfa, 0xbf, 0xb3, 0xeb, - 0x40, 0xff, 0xc9, 0xc8, 0xc9, 0xc0, 0x1f, 0xf7, 0x3a, 0x34, 0xdc, 0xcc, - 0xf8, 0xd8, 0x60, 0x03, 0x05, 0xe3, 0x15, 0x9b, 0x0c, 0x4b, 0x13, 0xb9, - 0x2b, 0x4e, 0x0b, 0xf4, 0xe5, 0xb8, 0xe8, 0x1e, 0x22, 0xb3, 0xb3, 0x71, - 0x37, 0xa8, 0xdf, 0xe4, 0x27, 0x53, 0x11, 0x29, 0x16, 0x20, 0x33, 0xcc, - 0xfc, 0x50, 0xd5, 0x22, 0x5c, 0x45, 0x50, 0xe8, 0x43, 0xfd, 0xe8, 0x5b, - 0x43, 0xef, 0x04, 0x1f, 0x4b, 0x2a, 0x38, 0xcf, 0x9f, 0x30, 0x13, 0xeb, - 0x94, 0xdf, 0x9e, 0xb6, 0x33, 0x21, 0xc4, 0xc8, 0x0d, 0xe3, 0x9e, 0x2b, - 0xe0, 0x88, 0xf0, 0x0d, 0x40, 0xd4, 0x54, 0x6f, 0x33, 0xae, 0x1f, 0xd6, - 0xb3, 0xfc, 0x8e, 0xd5, 0xff, 0x81, 0x45, 0xb0, 0x19, 0x95, 0xec, 0x07, - 0x20, 0xd7, 0xf0, 0xff, 0x18, 0x5e, 0xaa, 0xc2, 0xac, 0x1b, 0xd5, 0xd4, - 0xd8, 0xd9, 0x07, 0x5d, 0x1b, 0xda, 0xd7, 0x02, 0xff, 0xff, 0xd8, 0xb0, - 0xcf, 0xbb, 0xb2, 0xfd, 0x00, 0x0e, 0x33, 0x52, 0x2d, 0x56, 0x42, 0x62, - 0xf3, 0xf8, 0x0f, 0xfd, 0xe6, 0x5f, 0xaf, 0x1c, 0x1c, 0x98, 0xb6, 0x03, - 0x00, 0xcd, 0xab, 0x5d, 0xd8, 0xc0, 0x13, 0xea, 0x20, 0x34, 0xc6, 0xf7, - 0xdc, 0x20, 0xbf, 0xe9, 0xea, 0xd5, 0x34, 0x25, 0x24, 0xee, 0x1e, 0xf7, - 0x07, 0xf5, 0x15, 0xf6, 0x1f, 0xc6, 0x1e, 0xed, 0x2a, 0x2a, 0x2c, 0x10, - 0x00, 0x1b, 0xc7, 0xde, 0xbb, 0x07, 0x27, 0x38, 0xf6, 0xe7, 0xd2, 0xd0, - 0xd8, 0xef, 0xe3, 0x0d, 0xa1, 0x4e, 0xb9, 0x17, 0x39, 0x19, 0xfb, 0x25, - 0xd1, 0xe9, 0x24, 0x00, 0xf9, 0x31, 0x27, 0xdf, 0xca, 0x02, 0x3c, 0x11, - 0xe8, 0xe6, 0xce, 0xdc, 0x24, 0xf6, 0xd5, 0xdf, 0xf9, 0xdd, 0x0e, 0x25, - 0xc6, 0x2b, 0xfc, 0x0e, 0xc1, 0x40, 0xfb, 0xf8, 0x22, 0xf4, 0xd3, 0xc2, - 0x42, 0xf3, 0xdb, 0x08, 0xed, 0xef, 0x2a, 0xcb, 0xd6, 0x14, 0xf2, 0x03, - 0xf6, 0x28, 0x2c, 0xfc, 0x0b, 0x26, 0x0d, 0xd5, 0x0a, 0x13, 0x1b, 0xc3, - 0x1d, 0x29, 0x1d, 0xfe, 0xec, 0xc2, 0xf8, 0xc6, 0xca, 0xbc, 0x81, 0x28, - 0xcf, 0x00, 0x28, 0x7f, 0xf0, 0xf1, 0x0d, 0xfb, 0xc4, 0xd8, 0x39, 0x2b, - 0xba, 0x0b, 0x05, 0xb5, 0xfd, 0xf1, 0xe6, 0x33, 0x30, 0x3b, 0xe4, 0x39, - 0xb7, 0xc3, 0x11, 0xe7, 0x29, 0x32, 0xe2, 0xe5, 0x04, 0xc4, 0xe8, 0x2a, - 0x5c, 0xd7, 0x50, 0xcb, 0xbe, 0x35, 0x0c, 0xcc, 0xd5, 0xdf, 0x53, 0x06, - 0x57, 0x15, 0x30, 0x01, 0xde, 0x33, 0x41, 0xfd, 0x2a, 0x48, 0x08, 0x29, - 0xfd, 0x1b, 0xb5, 0xa2, 0xea, 0x91, 0x22, 0x59, 0xb5, 0x44, 0xfd, 0x70, - 0x1f, 0x07, 0xd7, 0xbe, 0xdd, 0x12, 0xe3, 0xca, 0xcc, 0x59, 0x0a, 0xad, - 0x50, 0x3d, 0x2e, 0x2b, 0x4a, 0xf0, 0xaf, 0xfb, 0x3e, 0x34, 0x43, 0x0a, - 0xf6, 0xb3, 0x10, 0x20, 0xc6, 0x47, 0x8a, 0xd6, 0x0d, 0x1a, 0x1d, 0x1f, - 0x44, 0xce, 0x0b, 0xd9, 0x04, 0x43, 0x1b, 0x30, 0xf5, 0xb2, 0xd9, 0xd1, - 0xb3, 0xdd, 0x67, 0xab, 0x01, 0xc7, 0x0b, 0xf7, 0x52, 0x07, 0xee, 0x07, - 0x06, 0x43, 0x0f, 0x21, 0xe6, 0x30, 0xfb, 0x1c, 0x2a, 0x0e, 0x48, 0x3f, - 0xd5, 0xce, 0xfb, 0x3c, 0x38, 0x35, 0x12, 0xae, 0xe4, 0xc8, 0xd0, 0xf3, - 0x42, 0xe8, 0xb6, 0x34, 0xc9, 0x27, 0xea, 0x2d, 0x3c, 0xce, 0x13, 0xaa, - 0xe4, 0x0e, 0xda, 0xed, 0x05, 0x3c, 0x0f, 0xd2, 0x2f, 0xf5, 0x25, 0xdf, - 0xee, 0x1d, 0x2f, 0xb5, 0xbb, 0xd7, 0x0d, 0xa1, 0x2a, 0xe7, 0x13, 0xd5, - 0xd0, 0x6a, 0xca, 0x26, 0x08, 0x43, 0xd1, 0x0c, 0xf6, 0xc4, 0xee, 0x03, - 0x14, 0x1e, 0x1b, 0x3c, 0xd2, 0x81, 0xe1, 0x62, 0x0e, 0x32, 0xe3, 0xfb, - 0x19, 0x22, 0xf0, 0xee, 0xe1, 0x2c, 0x05, 0x23, 0xdf, 0xfc, 0xf0, 0x1c, - 0xee, 0x1a, 0x2e, 0x3a, 0xe2, 0xcf, 0xaf, 0x1a, 0x22, 0x39, 0x20, 0xdb, - 0x3a, 0xed, 0x5a, 0x1c, 0xe8, 0x58, 0xef, 0xe7, 0x48, 0x0c, 0xe0, 0xc0, - 0x1e, 0x1a, 0x2a, 0x28, 0x58, 0xd8, 0x13, 0x0b, 0xbc, 0x17, 0x9e, 0xc2, - 0x13, 0xc5, 0xd9, 0xdc, 0xdb, 0xe0, 0xc0, 0x16, 0x22, 0xe9, 0xe1, 0xe0, - 0x09, 0xd3, 0x96, 0x69, 0xcc, 0x99, 0xce, 0xcf, 0xe2, 0xf1, 0x5c, 0xe0, - 0x45, 0xe3, 0x39, 0x94, 0x28, 0x2b, 0x3d, 0x6d, 0xb3, 0x45, 0x02, 0x13, - 0xae, 0xa6, 0xbe, 0x5a, 0x10, 0x3a, 0x44, 0x24, 0xa0, 0xe5, 0xf8, 0x09, - 0x9e, 0xad, 0xfe, 0x15, 0x3f, 0x03, 0x2c, 0x3a, 0x0f, 0x0d, 0xf7, 0xaa, - 0x59, 0x40, 0xe6, 0xd8, 0x3b, 0x1f, 0x28, 0x6a, 0xcd, 0xa6, 0xff, 0x2f, - 0xac, 0x28, 0xf5, 0xd4, 0x3c, 0x03, 0x21, 0x42, 0x21, 0x09, 0x12, 0xaf, - 0x9c, 0xae, 0x27, 0xdf, 0xeb, 0xba, 0xf5, 0xff, 0x4c, 0x04, 0x9d, 0xb7, - 0xfa, 0x5b, 0x1f, 0x43, 0x2e, 0xab, 0xb2, 0x3d, 0xf0, 0xda, 0xb3, 0xef, - 0x11, 0x2f, 0xae, 0xf6, 0xff, 0xd7, 0xae, 0x43, 0x2a, 0xbb, 0x81, 0x2c, - 0x16, 0x2e, 0xb7, 0xe1, 0x1c, 0x0f, 0xc3, 0x46, 0x61, 0xf8, 0x46, 0x11, - 0x08, 0x32, 0xf7, 0xce, 0x49, 0xe8, 0xcc, 0x03, 0xd6, 0x09, 0xe4, 0xa2, - 0x10, 0x16, 0xe3, 0xf7, 0xdf, 0x11, 0x02, 0x38, 0xca, 0x3d, 0x21, 0x21, - 0xb6, 0xc9, 0xab, 0x47, 0xdc, 0xe9, 0xad, 0x56, 0x32, 0xda, 0x3f, 0x01, - 0x42, 0x1b, 0xc8, 0xd0, 0x22, 0xf4, 0xb9, 0xdd, 0xd4, 0x0c, 0xef, 0xd3, - 0x2e, 0xd0, 0x07, 0x34, 0xf8, 0x18, 0x10, 0x10, 0xe7, 0xc9, 0x17, 0xeb, - 0x31, 0x29, 0xf3, 0x12, 0x10, 0x00, 0xc7, 0x3a, 0x2f, 0x9a, 0xdd, 0x27, - 0x20, 0xda, 0xf8, 0x3a, 0xf6, 0xdf, 0x60, 0xf1, 0xfd, 0xda, 0xfa, 0xe0, - 0x02, 0x05, 0xf0, 0xbc, 0xcb, 0xe2, 0x43, 0x50, 0xbc, 0xea, 0x86, 0x2a, - 0xf8, 0x0d, 0x48, 0x1c, 0x43, 0xaf, 0xb4, 0xf7, 0x1d, 0xf0, 0x25, 0xf6, - 0x4e, 0x1b, 0xcf, 0x07, 0x7f, 0xeb, 0xe5, 0x09, 0xb3, 0x42, 0x06, 0xc3, - 0xba, 0x3d, 0x1a, 0x2a, 0x3a, 0xeb, 0xbf, 0x16, 0x78, 0x81, 0xeb, 0xae, - 0x76, 0x57, 0xcf, 0x58, 0x23, 0xb2, 0x07, 0x03, 0x3d, 0x76, 0xed, 0xed, - 0xea, 0x14, 0x73, 0x3a, 0x19, 0xc8, 0xe9, 0x98, 0xca, 0x07, 0xb0, 0xba, - 0xc3, 0x13, 0x2d, 0xd0, 0xcf, 0x2b, 0xbc, 0x12, 0xe6, 0x3f, 0x39, 0x9b, - 0x61, 0x1e, 0xaf, 0x07, 0xc0, 0x23, 0xdb, 0x22, 0x93, 0x63, 0xe3, 0x55, - 0x33, 0x4f, 0x24, 0xf5, 0xdd, 0xeb, 0x5e, 0x09, 0x49, 0x20, 0xaf, 0xfb, - 0xf8, 0xf4, 0xf4, 0x11, 0xec, 0x0f, 0x35, 0xee, 0x4f, 0x61, 0x3f, 0x8d, - 0x11, 0x50, 0x58, 0x22, 0x12, 0xce, 0x4b, 0xd5, 0x15, 0xa3, 0xf9, 0xd5, - 0x3a, 0xba, 0x2f, 0x35, 0xc9, 0xb2, 0xf0, 0xd5, 0xd9, 0xd9, 0xab, 0xfd, - 0x5b, 0xe4, 0x68, 0xd9, 0xb1, 0x5e, 0xb1, 0x07, 0x04, 0x1e, 0xd0, 0x0d, - 0xc2, 0xd1, 0x91, 0x21, 0xcc, 0x7b, 0xff, 0xff, 0xc6, 0xe3, 0xff, 0xff, - 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xd2, 0xe5, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, - 0x80, 0x02, 0x00, 0x00, 0xdb, 0x2d, 0x46, 0x49, 0x0d, 0xf6, 0xc8, 0xf0, - 0x42, 0x15, 0x1a, 0x32, 0xd9, 0xed, 0xb2, 0xa4, 0xe0, 0x25, 0x0a, 0xca, - 0x1c, 0x2a, 0x36, 0x0b, 0xef, 0x62, 0xe0, 0xff, 0xc8, 0xe1, 0x3b, 0x16, - 0xfa, 0xd7, 0x10, 0xe0, 0x17, 0xf7, 0x3e, 0x09, 0x25, 0x12, 0xe2, 0xb5, - 0x28, 0xd5, 0xaa, 0xe0, 0x16, 0xbb, 0x4d, 0xb0, 0x12, 0xc8, 0xc1, 0x65, - 0xf8, 0xdc, 0xfa, 0x0a, 0xb9, 0x2d, 0xd5, 0x2c, 0x1d, 0xbc, 0xd7, 0xe3, - 0x2b, 0x46, 0x2f, 0x3d, 0xd2, 0x20, 0xfd, 0xd1, 0xca, 0xc2, 0xe9, 0x17, - 0x44, 0x7d, 0x04, 0x36, 0x1b, 0x24, 0x05, 0xea, 0xf1, 0x13, 0xba, 0x15, - 0xd2, 0x00, 0xca, 0x03, 0xcd, 0xe3, 0xd1, 0x44, 0xea, 0x07, 0xc8, 0xe8, - 0xff, 0x0d, 0x67, 0xdd, 0x1e, 0x0b, 0x3b, 0xea, 0xb2, 0xbd, 0x38, 0x4f, - 0x0f, 0xaa, 0x40, 0x07, 0xc3, 0xfb, 0x58, 0xe5, 0x0b, 0x25, 0x0e, 0x4a, - 0xf3, 0x2f, 0x0d, 0x57, 0xe8, 0xd2, 0xf9, 0xee, 0x20, 0xa4, 0x02, 0x0d, - 0xba, 0x01, 0xd3, 0xe8, 0x28, 0xd9, 0x08, 0xde, 0x28, 0x2c, 0x2c, 0xf0, - 0x04, 0x47, 0xd8, 0x15, 0x00, 0x4c, 0xdf, 0xd6, 0x2f, 0x17, 0xfe, 0xfd, - 0x1b, 0xed, 0x20, 0x3a, 0xfe, 0x1e, 0xec, 0x96, 0xd6, 0xca, 0xc0, 0xfd, - 0x0b, 0xe1, 0x1f, 0xcc, 0x2f, 0xe3, 0x06, 0x4c, 0x2c, 0x24, 0x10, 0x41, - 0xfb, 0x1b, 0xe7, 0x1f, 0x10, 0xc5, 0x25, 0x32, 0xe4, 0x04, 0xe4, 0x4e, - 0xb7, 0x1d, 0xcc, 0xbf, 0x3b, 0xc1, 0xc0, 0xb0, 0x0d, 0x58, 0x1b, 0xc8, - 0x47, 0x1a, 0xdc, 0xd2, 0xf8, 0xf0, 0xb7, 0x30, 0x07, 0x24, 0x29, 0xd6, - 0x06, 0xb4, 0x16, 0x0a, 0xc4, 0x12, 0xa5, 0xb3, 0x04, 0xdc, 0xf7, 0x33, - 0x44, 0x13, 0x05, 0xfe, 0xbb, 0xc2, 0x22, 0x55, 0xe5, 0xb5, 0x16, 0xe1, - 0x0a, 0xdc, 0x3a, 0xcf, 0xe0, 0x15, 0x5b, 0xd6, 0x1d, 0x47, 0xef, 0xeb, - 0xec, 0xdf, 0x21, 0xee, 0xe2, 0xdd, 0x0e, 0x22, 0xea, 0x5b, 0xd5, 0xda, - 0xd8, 0xf3, 0x23, 0xd5, 0x34, 0x04, 0x2c, 0x34, 0xcf, 0x46, 0xcd, 0x17, - 0xdb, 0x18, 0x01, 0xff, 0x13, 0x06, 0x2d, 0x1b, 0xdd, 0x5a, 0x29, 0x42, - 0x46, 0x01, 0x22, 0xa7, 0xfe, 0xfc, 0xff, 0xe7, 0xf1, 0xe0, 0x06, 0xd1, - 0xfe, 0x1d, 0xc7, 0x31, 0x21, 0x27, 0xc0, 0xef, 0x0b, 0x2c, 0xcf, 0x15, - 0xfc, 0xce, 0x0d, 0x31, 0xff, 0x32, 0x0b, 0x09, 0xef, 0xf2, 0xf6, 0xed, - 0x30, 0xf6, 0xc0, 0xd6, 0x2d, 0x08, 0xf8, 0xe1, 0xd2, 0xfc, 0x35, 0xcd, - 0x44, 0xe9, 0xbe, 0x1f, 0xd0, 0x0c, 0x1d, 0xbf, 0x19, 0x2b, 0x00, 0x59, - 0xdc, 0xfa, 0xfb, 0xcf, 0x05, 0xf2, 0x58, 0x59, 0x1b, 0x2b, 0x1a, 0xce, - 0xcc, 0x2c, 0x27, 0x1d, 0xff, 0xed, 0xf4, 0xd7, 0xc8, 0x37, 0x3f, 0x18, - 0xc9, 0x2e, 0x5c, 0xcc, 0xf5, 0x14, 0x0e, 0xe0, 0xcf, 0x1c, 0x43, 0xec, - 0xaa, 0xed, 0xf9, 0xfa, 0x0b, 0x0a, 0xdd, 0xda, 0x14, 0xd6, 0x2b, 0xc5, - 0x36, 0xde, 0x05, 0x5d, 0xd4, 0x61, 0x24, 0x0e, 0xda, 0xf7, 0x0d, 0x23, - 0xc3, 0x07, 0xf4, 0xe4, 0xf9, 0x24, 0x37, 0x0c, 0x13, 0xfc, 0x2f, 0x08, - 0x19, 0x10, 0x16, 0x0f, 0x11, 0xd5, 0x2a, 0xc1, 0xd6, 0x2b, 0xda, 0x78, - 0x2a, 0x26, 0xe9, 0x3b, 0x58, 0x13, 0xda, 0xbd, 0xdb, 0xe8, 0x00, 0x4e, - 0xff, 0x5c, 0x31, 0x00, 0x06, 0x30, 0xeb, 0x26, 0xe1, 0xd2, 0xfb, 0xed, - 0xf6, 0x2d, 0xeb, 0xb0, 0xbf, 0xed, 0x24, 0x2e, 0x1e, 0xdb, 0xd3, 0x17, - 0xf8, 0xe4, 0x23, 0x06, 0x2e, 0x28, 0xd5, 0x0b, 0x18, 0xf2, 0xf7, 0xee, - 0xc4, 0xd0, 0x2e, 0xfd, 0x2e, 0xd2, 0xd9, 0x31, 0xf1, 0xfe, 0x08, 0x21, - 0xf7, 0x0f, 0x02, 0xff, 0x29, 0x48, 0x48, 0x4c, 0xd2, 0xf8, 0x26, 0xc9, - 0xb7, 0xdb, 0xe3, 0xff, 0x16, 0xd0, 0x4a, 0x3e, 0xc4, 0xf6, 0xee, 0x22, - 0xd9, 0x4a, 0x2c, 0xd6, 0xe0, 0xf7, 0xbf, 0x0f, 0xdd, 0x97, 0x09, 0xec, - 0xcd, 0x46, 0x10, 0x21, 0x27, 0xe8, 0x19, 0xfd, 0x1c, 0x68, 0x11, 0x3b, - 0xa0, 0x4a, 0x36, 0x9e, 0x39, 0xd5, 0x39, 0xda, 0x0e, 0x3c, 0x19, 0x1f, - 0x26, 0xf2, 0x42, 0x07, 0xef, 0x22, 0xf1, 0x56, 0x16, 0x29, 0x9b, 0x7f, - 0xef, 0xf6, 0xf2, 0xe9, 0xf1, 0xcf, 0xdc, 0x35, 0xdd, 0x27, 0xec, 0xdd, - 0x0e, 0x20, 0xe2, 0x16, 0x24, 0x12, 0x1d, 0xf4, 0xc7, 0x2f, 0xc6, 0xc6, - 0xe7, 0xb4, 0xf9, 0xcd, 0x06, 0xea, 0xc4, 0x1c, 0x20, 0xeb, 0x3d, 0x04, - 0x5a, 0xef, 0x29, 0x4c, 0x37, 0xd4, 0xf3, 0xe4, 0xd9, 0xc8, 0x5c, 0x38, - 0x18, 0x1e, 0xb5, 0x25, 0x41, 0x4e, 0xa0, 0x30, 0x51, 0x13, 0x1e, 0xfb, - 0xbd, 0x3b, 0x1e, 0xe5, 0x9f, 0x0c, 0xfe, 0xc8, 0x68, 0x80, 0xff, 0xff, - 0x62, 0xe8, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, - 0xe1, 0x19, 0x00, 0x00, 0x60, 0xf4, 0xff, 0xff, 0x1e, 0xe8, 0xff, 0xff, - 0xf9, 0x08, 0x00, 0x00, 0x4e, 0xeb, 0xff, 0xff, 0xd5, 0x22, 0x00, 0x00, - 0x04, 0xe5, 0xff, 0xff, 0x7a, 0xfd, 0xff, 0xff, 0x45, 0x0a, 0x00, 0x00, - 0xb8, 0x0c, 0x00, 0x00, 0xe2, 0x10, 0x00, 0x00, 0x76, 0xf7, 0xff, 0xff, - 0x10, 0x32, 0x00, 0x00, 0x88, 0xfa, 0xff, 0xff, 0x20, 0x01, 0x00, 0x00, - 0x23, 0x0a, 0x00, 0x00, 0x48, 0x1d, 0x00, 0x00, 0x39, 0x21, 0x00, 0x00, - 0xa7, 0x20, 0x00, 0x00, 0x67, 0x22, 0x00, 0x00, 0x3c, 0xf8, 0xff, 0xff, - 0xdc, 0x18, 0x00, 0x00, 0xf8, 0xed, 0xff, 0xff, 0x7c, 0x2b, 0x00, 0x00, - 0x30, 0xf3, 0xff, 0xff, 0x65, 0x17, 0x00, 0x00, 0xac, 0xfc, 0xff, 0xff, - 0x75, 0xf5, 0xff, 0xff, 0x3e, 0x0a, 0x00, 0x00, 0xa6, 0x20, 0x00, 0x00, - 0x15, 0x08, 0x00, 0x00, 0xa7, 0xee, 0xff, 0xff, 0x89, 0x04, 0x00, 0x00, - 0x0c, 0xfa, 0xff, 0xff, 0xe4, 0x05, 0x00, 0x00, 0xec, 0xec, 0xff, 0xff, - 0x63, 0xf5, 0xff, 0xff, 0xb1, 0x03, 0x00, 0x00, 0xb5, 0xf9, 0xff, 0xff, - 0x99, 0x01, 0x00, 0x00, 0xbb, 0xeb, 0xff, 0xff, 0x34, 0xdf, 0xff, 0xff, - 0x02, 0xf2, 0xff, 0xff, 0xef, 0xf9, 0xff, 0xff, 0x22, 0x0c, 0x00, 0x00, - 0x8f, 0x0b, 0x00, 0x00, 0x4b, 0xfe, 0xff, 0xff, 0xe4, 0x02, 0x00, 0x00, - 0x28, 0xf8, 0xff, 0xff, 0x3a, 0xf2, 0xff, 0xff, 0x0d, 0xda, 0xff, 0xff, - 0xd6, 0xf2, 0xff, 0xff, 0x21, 0xef, 0xff, 0xff, 0xcc, 0x02, 0x00, 0x00, - 0x13, 0x11, 0x00, 0x00, 0x48, 0x5f, 0x00, 0x00, 0xea, 0xf0, 0xff, 0xff, - 0x64, 0xcb, 0xff, 0xff, 0x17, 0xdc, 0xff, 0xff, 0x6e, 0x41, 0x00, 0x00, - 0x8d, 0x20, 0x00, 0x00, 0xb9, 0x1f, 0x00, 0x00, 0x6d, 0xf8, 0xff, 0xff, - 0xab, 0x16, 0x00, 0x00, 0xdd, 0xef, 0xff, 0xff, 0xa3, 0x47, 0x00, 0x00, - 0xb1, 0x04, 0x00, 0x00, 0x3f, 0xef, 0xff, 0xff, 0x6e, 0x01, 0x00, 0x00, - 0xf6, 0x0a, 0x00, 0x00, 0x0b, 0x15, 0x00, 0x00, 0x27, 0xf4, 0xff, 0xff, - 0x83, 0x1e, 0x00, 0x00, 0xd1, 0x14, 0x00, 0x00, 0x7d, 0x1e, 0x00, 0x00, - 0x1f, 0x11, 0x00, 0x00, 0xba, 0x11, 0x00, 0x00, 0x3d, 0xfd, 0xff, 0xff, - 0xbb, 0xfe, 0xff, 0xff, 0xd2, 0xe8, 0xff, 0xff, 0x69, 0x0f, 0x00, 0x00, - 0xfe, 0x50, 0x00, 0x00, 0x4f, 0x0c, 0x00, 0x00, 0x7d, 0x00, 0x00, 0x00, - 0x06, 0xee, 0xff, 0xff, 0x1e, 0xf4, 0xff, 0xff, 0xd8, 0x0e, 0x00, 0x00, - 0xe7, 0xf0, 0xff, 0xff, 0xb4, 0x08, 0x00, 0x00, 0xc8, 0xfc, 0xff, 0xff, - 0x19, 0xf7, 0xff, 0xff, 0xbf, 0xdd, 0xff, 0xff, 0x9b, 0x08, 0x00, 0x00, - 0x14, 0x12, 0x00, 0x00, 0xfe, 0x20, 0x00, 0x00, 0xd5, 0xee, 0xff, 0xff, - 0xc9, 0xff, 0xff, 0xff, 0xe8, 0x06, 0x00, 0x00, 0x7d, 0x12, 0x00, 0x00, - 0x9d, 0xe7, 0xff, 0xff, 0x74, 0xfe, 0xff, 0xff, 0xbb, 0xf1, 0xff, 0xff, - 0x65, 0xeb, 0xff, 0xff, 0xcb, 0x0f, 0x00, 0x00, 0x8b, 0x01, 0x00, 0x00, - 0xf8, 0xf7, 0xff, 0xff, 0xe7, 0x1e, 0x00, 0x00, 0x7d, 0x00, 0x00, 0x00, - 0x95, 0xfb, 0xff, 0xff, 0x32, 0xfe, 0xff, 0xff, 0x5a, 0xfe, 0xff, 0xff, - 0x9a, 0x0b, 0x00, 0x00, 0x88, 0x08, 0x00, 0x00, 0x2e, 0xfe, 0xff, 0xff, - 0x6f, 0x09, 0x00, 0x00, 0x7b, 0x96, 0xff, 0xff, 0xf9, 0x0e, 0x00, 0x00, - 0x43, 0x05, 0x00, 0x00, 0xdd, 0xee, 0xff, 0xff, 0x6d, 0xdf, 0xff, 0xff, - 0x7a, 0xf1, 0xff, 0xff, 0xc7, 0x1c, 0x00, 0x00, 0x8b, 0xe9, 0xff, 0xff, - 0x42, 0x1a, 0x00, 0x00, 0x6c, 0x48, 0x00, 0x00, 0x56, 0xec, 0xff, 0xff, - 0xf3, 0xef, 0xff, 0xff, 0xfa, 0xec, 0xff, 0xff, 0x6e, 0xea, 0xff, 0xff, - 0x04, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x58, 0x85, 0xc3, 0xd4, - 0xc5, 0xa1, 0xd4, 0x92, 0x34, 0x5c, 0xae, 0x39, 0x97, 0x18, 0x4e, 0x34, - 0xee, 0x54, 0xed, 0x02, 0x1b, 0x13, 0x19, 0x19, 0x34, 0x1a, 0xe2, 0x40, - 0x0d, 0xe8, 0x05, 0xae, 0xbb, 0x81, 0x44, 0xcd, 0xf5, 0x4e, 0xf8, 0x0e, - 0x10, 0x0f, 0x40, 0x39, 0xf0, 0x53, 0xd3, 0x06, 0x74, 0xa3, 0xd5, 0x55, - 0xfc, 0xf7, 0x40, 0x07, 0xbc, 0x32, 0x7f, 0xed, 0x24, 0x70, 0x48, 0x5c, - 0x3d, 0x56, 0x2d, 0x33, 0x4d, 0x18, 0x59, 0x06, 0xff, 0x39, 0x42, 0xfe, - 0xb7, 0x0d, 0x2d, 0x63, 0x12, 0x22, 0xe5, 0xed, 0xfe, 0xc3, 0x4c, 0xd6, - 0xba, 0x96, 0xdf, 0x81, 0x23, 0xa2, 0x59, 0x36, 0x71, 0x99, 0x0c, 0x72, - 0xca, 0x19, 0x9e, 0x19, 0xf7, 0xe8, 0x89, 0xff, 0x2d, 0x1f, 0x94, 0xe4, - 0x68, 0x49, 0x4e, 0xe7, 0xa0, 0x78, 0x44, 0xc0, 0x28, 0x09, 0xfc, 0xc9, - 0x37, 0x73, 0x4a, 0x68, 0xa3, 0xcd, 0x35, 0x7f, 0x42, 0xca, 0x7c, 0x64, - 0x2e, 0x4b, 0x9f, 0xe0, 0xd7, 0x04, 0x37, 0xa9, 0xe4, 0x16, 0x2f, 0x86, - 0x96, 0xa9, 0x2a, 0x5b, 0xea, 0x44, 0x28, 0x1d, 0xac, 0xde, 0xf1, 0xfe, - 0x26, 0x63, 0x6a, 0xf1, 0x4b, 0xc8, 0x50, 0xf2, 0x6a, 0xfd, 0x00, 0x07, - 0x04, 0xdc, 0xe0, 0xcc, 0x88, 0xd1, 0x63, 0x31, 0x88, 0xeb, 0x08, 0x3b, - 0xcc, 0xd8, 0x06, 0x6b, 0x11, 0xab, 0x18, 0xe4, 0x73, 0x7f, 0xcb, 0xc8, - 0xb7, 0xdb, 0x16, 0x40, 0x28, 0xba, 0x05, 0xbe, 0x81, 0x9c, 0xdf, 0xcf, - 0x31, 0x6c, 0xc8, 0x01, 0xca, 0x22, 0xd7, 0xd8, 0x56, 0xec, 0xd0, 0x30, - 0x3f, 0x0c, 0xc1, 0xaf, 0xde, 0x1f, 0xf0, 0xc3, 0x65, 0xca, 0x0d, 0xc0, - 0x4e, 0xdd, 0x3c, 0x5b, 0xb6, 0xb8, 0x35, 0xc5, 0x5f, 0xa2, 0x22, 0xb0, - 0x50, 0x5f, 0x1d, 0xec, 0x04, 0x81, 0x17, 0xc6, 0x2b, 0xee, 0xeb, 0x0d, - 0xa4, 0xfd, 0xd6, 0x02, 0x0e, 0x71, 0xbb, 0xc4, 0xab, 0xc2, 0xaa, 0x35, - 0xb9, 0xc8, 0x0a, 0xcb, 0xde, 0xed, 0xdb, 0x58, 0xfa, 0x21, 0x17, 0x28, - 0xe1, 0x23, 0x24, 0x00, 0x99, 0x2b, 0x01, 0xb8, 0x1c, 0x06, 0xf4, 0xfb, - 0x8f, 0xc8, 0xf8, 0xf7, 0xf3, 0xea, 0xc7, 0x7f, 0x05, 0x7f, 0x05, 0x35, - 0xd7, 0x31, 0xbc, 0x2a, 0x16, 0xc2, 0x91, 0x6a, 0x42, 0x4d, 0x88, 0x96, - 0xfd, 0xb3, 0xc2, 0xf1, 0xe2, 0x00, 0x3d, 0x7a, 0x42, 0x3a, 0x14, 0xf5, - 0xb4, 0x35, 0x94, 0x16, 0x7f, 0x3a, 0xf3, 0x08, 0x6b, 0x18, 0xb1, 0xb1, - 0x83, 0x9b, 0xd4, 0xe1, 0xa5, 0x0b, 0x54, 0x1f, 0xaf, 0xc7, 0x12, 0x2d, - 0x5b, 0x3f, 0xca, 0x0e, 0x26, 0xb7, 0x3c, 0xca, 0x81, 0xd2, 0xf4, 0x36, - 0xd4, 0xa2, 0xef, 0xb2, 0x39, 0x4d, 0x5a, 0x09, 0x0f, 0xe3, 0xca, 0x9f, - 0x0c, 0xe6, 0x12, 0x4a, 0x2c, 0x19, 0xef, 0xc7, 0x0d, 0x65, 0x99, 0x41, - 0x51, 0xa2, 0xec, 0x4c, 0x06, 0xcb, 0x05, 0xe5, 0x7b, 0x64, 0x54, 0x1d, - 0x9e, 0xaf, 0x3f, 0x63, 0xe3, 0x09, 0x67, 0x20, 0x04, 0x58, 0xd8, 0xb9, - 0xf3, 0xba, 0x46, 0xc1, 0x36, 0x32, 0x85, 0x31, 0x6f, 0xed, 0x1a, 0x7f, - 0xe2, 0xf0, 0x51, 0xfb, 0x08, 0xb8, 0xc8, 0xff, 0x23, 0x16, 0xed, 0x51, - 0x94, 0x8e, 0x9e, 0x2e, 0x20, 0xd4, 0xa6, 0x91, 0xcf, 0x5b, 0x8c, 0x95, - 0xa2, 0x31, 0x39, 0xf7, 0xcc, 0x34, 0xaf, 0x29, 0xd5, 0x0b, 0x57, 0x20, - 0xfd, 0xdc, 0x5b, 0x7f, 0x09, 0xba, 0x2f, 0xdf, 0x34, 0xce, 0xc4, 0x0c, - 0xe9, 0x25, 0xba, 0x9e, 0x32, 0x17, 0xba, 0x1e, 0x19, 0x81, 0x60, 0xe2, - 0x18, 0xc2, 0x3a, 0xa4, 0xaa, 0x44, 0x12, 0x59, 0x8d, 0x84, 0xf2, 0x4c, - 0xfb, 0xea, 0xe8, 0x0f, 0xf8, 0x9d, 0x05, 0xee, 0xda, 0x06, 0x4a, 0x1e, - 0xd1, 0x08, 0x41, 0xb1, 0xc0, 0xd2, 0xbb, 0xd6, 0x1a, 0xab, 0x58, 0x5c, - 0x39, 0xc5, 0xf4, 0x7f, 0xf9, 0xfe, 0x63, 0x25, 0xfd, 0xc2, 0x34, 0x21, - 0xda, 0xf7, 0x2a, 0x60, 0xea, 0x04, 0xd6, 0x17, 0xd1, 0x3d, 0x01, 0x1b, - 0xdf, 0x03, 0xe7, 0xce, 0xd6, 0x0e, 0x2a, 0xe5, 0xc8, 0xd5, 0xb6, 0xf6, - 0xff, 0xbf, 0x05, 0x13, 0x99, 0x2b, 0xaf, 0x7d, 0xcd, 0x1d, 0x3d, 0x29, - 0xf1, 0x6f, 0xfa, 0xe5, 0x35, 0x1a, 0x07, 0x34, 0xda, 0xe3, 0xb3, 0xfa, - 0x81, 0x78, 0xb1, 0x08, 0xd3, 0x56, 0x47, 0xd8, 0x10, 0x3d, 0xb0, 0x21, - 0x25, 0xc0, 0x64, 0x62, 0x3b, 0xe6, 0x44, 0xd6, 0x0b, 0xec, 0x92, 0x52, - 0x1d, 0xe4, 0x74, 0x60, 0xe8, 0xe3, 0xca, 0x1d, 0xe4, 0xb3, 0xd4, 0x0f, - 0x8d, 0x81, 0x47, 0xd1, 0xae, 0x31, 0x41, 0xef, 0x30, 0xe2, 0xf8, 0x0f, - 0x31, 0xd7, 0x46, 0x9c, 0xfc, 0x1d, 0x29, 0x2d, 0x95, 0xed, 0x42, 0x03, - 0xbd, 0x67, 0x50, 0xdc, 0x13, 0x81, 0x47, 0xa4, 0xbe, 0x06, 0xc3, 0xb6, - 0xaa, 0xb7, 0xb2, 0x67, 0x15, 0x67, 0xa8, 0xa6, 0x24, 0xbe, 0xa8, 0x4d, - 0x3e, 0x58, 0xb5, 0x01, 0x11, 0xff, 0xbf, 0x0a, 0xab, 0xa9, 0xfe, 0xa5, - 0x08, 0x05, 0x0d, 0x39, 0x3b, 0x24, 0xcc, 0xd4, 0xce, 0x0f, 0x4e, 0xb7, - 0x70, 0x61, 0x22, 0xd6, 0xd8, 0xb5, 0x67, 0xa3, 0xf3, 0xd4, 0xda, 0x53, - 0xff, 0xd2, 0x7f, 0x71, 0x66, 0x70, 0x73, 0x06, 0xa1, 0x22, 0x3f, 0xb1, - 0x93, 0xf4, 0x6d, 0x29, 0xf7, 0xe5, 0xe7, 0x1b, 0xc2, 0x81, 0x99, 0x35, - 0xb8, 0xea, 0xaa, 0x97, 0xd0, 0x05, 0x10, 0xbb, 0x60, 0xdd, 0xae, 0x94, - 0x2a, 0xe2, 0xd4, 0xa6, 0xa1, 0xf1, 0xe9, 0x41, 0x35, 0x30, 0x2e, 0x53, - 0x05, 0x26, 0xd7, 0x20, 0xb1, 0xe7, 0x7a, 0xe5, 0x6d, 0xbb, 0x1d, 0x16, - 0x49, 0x81, 0x5d, 0x12, 0x22, 0xe6, 0x0a, 0xae, 0xb6, 0x64, 0x54, 0x2d, - 0xfa, 0x05, 0x19, 0x3d, 0x14, 0xde, 0xe5, 0xf1, 0xf0, 0xd7, 0x1c, 0xee, - 0xfb, 0xf1, 0xd5, 0xd7, 0x14, 0xf0, 0x42, 0xf1, 0x10, 0x0e, 0x34, 0xd4, - 0x48, 0xcb, 0x2c, 0x11, 0x16, 0x10, 0x66, 0x2b, 0xa9, 0xfc, 0x30, 0xdd, - 0x50, 0x23, 0x5e, 0xad, 0x10, 0xfe, 0xba, 0x12, 0xf7, 0x06, 0x28, 0x1b, - 0x7f, 0x0b, 0x0f, 0x10, 0xf9, 0xe5, 0xe7, 0x1d, 0x36, 0x1a, 0x20, 0x3a, - 0x1f, 0xdb, 0x3b, 0xd1, 0xd7, 0x0b, 0x01, 0x01, 0x25, 0xda, 0x16, 0xcf, - 0xfb, 0xef, 0x18, 0x4f, 0x69, 0x24, 0x9d, 0x1a, 0x0b, 0x08, 0xe7, 0xdf, - 0xa9, 0x1b, 0xe1, 0x40, 0x16, 0xcf, 0x1b, 0x99, 0x7f, 0xf2, 0x3d, 0x31, - 0x0b, 0xb2, 0x14, 0xcb, 0x30, 0xb5, 0xe7, 0x2d, 0x3c, 0xeb, 0xbe, 0xfc, - 0x0e, 0xd9, 0x89, 0xd1, 0x39, 0x42, 0x04, 0x1a, 0x0c, 0x1f, 0xea, 0xf6, - 0x7f, 0x24, 0x2c, 0xd2, 0xaf, 0x4a, 0x0a, 0xbb, 0x76, 0x9d, 0xd4, 0x00, - 0x19, 0xfa, 0x2f, 0xaf, 0xdb, 0xc9, 0x9f, 0xfa, 0xf6, 0xee, 0x30, 0x30, - 0xe1, 0x49, 0x95, 0xcf, 0xb6, 0xaf, 0xc1, 0xc2, 0x81, 0xc4, 0xc9, 0xa2, - 0xd5, 0xf0, 0xe1, 0x40, 0x13, 0x3e, 0x0a, 0xa2, 0x1d, 0x0d, 0x01, 0x1e, - 0x1c, 0x9b, 0x0f, 0xde, 0x6a, 0xcc, 0xa4, 0x71, 0xe8, 0x99, 0x2d, 0x1c, - 0x93, 0xd5, 0xeb, 0xaa, 0x19, 0xb3, 0x05, 0xf8, 0xed, 0xe6, 0x0f, 0x65, - 0x1d, 0x9f, 0x9f, 0xfe, 0x4d, 0xe9, 0x31, 0x97, 0xec, 0x7f, 0x8e, 0xa6, - 0x1f, 0x67, 0x4f, 0xc9, 0x27, 0xd8, 0x30, 0x1a, 0xd9, 0x6f, 0x39, 0x98, - 0x1a, 0x92, 0xa8, 0xc2, 0x50, 0x06, 0x6f, 0xe4, 0x96, 0xea, 0x32, 0xf0, - 0xed, 0xfe, 0xcc, 0xe1, 0x4b, 0xf7, 0x41, 0xc3, 0xe7, 0x15, 0x38, 0x09, - 0x2f, 0x2d, 0x7f, 0x0c, 0x1d, 0x1a, 0xb3, 0xc7, 0xe0, 0xe5, 0x1f, 0xcf, - 0x0a, 0xd3, 0xf2, 0x36, 0x44, 0xf5, 0xce, 0xbd, 0xe0, 0xe2, 0x0b, 0x1b, - 0x02, 0x02, 0x23, 0xcd, 0x24, 0x61, 0xef, 0x2f, 0x7a, 0x02, 0x7c, 0xca, - 0xf4, 0xe5, 0x7b, 0x49, 0x7f, 0x1c, 0xca, 0x07, 0x26, 0x3d, 0x07, 0xdb, - 0x50, 0xc2, 0xc7, 0x07, 0x0b, 0x55, 0xf3, 0xe0, 0xbc, 0x96, 0x2b, 0xba, - 0x5e, 0xa8, 0x54, 0xbe, 0xda, 0xec, 0xae, 0x2b, 0x81, 0x01, 0xfa, 0x4d, - 0x03, 0xbf, 0x29, 0x08, 0xfd, 0x76, 0xf7, 0x66, 0xab, 0xff, 0x64, 0xde, - 0xc2, 0x2c, 0x9a, 0x06, 0xce, 0xd3, 0x0f, 0x3e, 0xbe, 0x12, 0xd4, 0xbd, - 0xda, 0x24, 0xc7, 0x03, 0xc9, 0x0a, 0xd7, 0xe4, 0x18, 0xfc, 0x89, 0x5d, - 0xf6, 0xf5, 0xf0, 0x23, 0x1f, 0xf3, 0xc5, 0x37, 0xc2, 0x64, 0xe3, 0x30, - 0x62, 0x3f, 0x3f, 0x18, 0xc8, 0xc8, 0x0e, 0x1e, 0x34, 0x81, 0xf8, 0xfa, - 0x36, 0xd6, 0x0d, 0xf4, 0xb1, 0xea, 0xe6, 0x10, 0xf0, 0x23, 0xe7, 0xf1, - 0x0f, 0x1c, 0x59, 0xe9, 0xd9, 0x29, 0xd3, 0xc2, 0xc4, 0x09, 0x98, 0xf7, - 0x8e, 0x55, 0x81, 0xc6, 0xfe, 0xad, 0x97, 0xe7, 0xf6, 0xcb, 0xbb, 0x42, - 0x4c, 0xb6, 0x49, 0x18, 0xcb, 0xf2, 0xc8, 0x11, 0x55, 0xbc, 0x73, 0xac, - 0x9d, 0x43, 0x65, 0x31, 0x6a, 0xa4, 0xa9, 0x13, 0x90, 0xd3, 0x08, 0xd1, - 0x97, 0x4f, 0x25, 0x2f, 0x21, 0xea, 0xba, 0xc3, 0xf5, 0x0b, 0x81, 0x9c, - 0x04, 0xaf, 0xde, 0xe2, 0x44, 0x20, 0xf6, 0xc5, 0xdc, 0xe4, 0x66, 0x2c, - 0xe1, 0xc5, 0x39, 0x23, 0x9b, 0xa3, 0xb9, 0xd0, 0x0c, 0xad, 0x58, 0xa4, - 0x37, 0xf4, 0xe3, 0x95, 0x0c, 0x3b, 0x59, 0xad, 0x03, 0x23, 0x19, 0x4d, - 0xec, 0xec, 0x18, 0x07, 0x31, 0x3b, 0x19, 0x49, 0x61, 0x34, 0x36, 0x8c, - 0xe1, 0xf5, 0x0a, 0x09, 0x62, 0xf3, 0x2f, 0xad, 0x4f, 0xed, 0x4d, 0xca, - 0xe1, 0x7f, 0x90, 0xc5, 0x3b, 0x21, 0x42, 0x28, 0x32, 0xd9, 0x36, 0x64, - 0x15, 0xed, 0xed, 0x6e, 0xf7, 0x3f, 0xbb, 0x7f, 0x13, 0x42, 0x0f, 0xe9, - 0x35, 0xf5, 0xd3, 0x43, 0xa0, 0x27, 0x57, 0x36, 0x6d, 0x64, 0x8b, 0xaa, - 0x07, 0x21, 0xf4, 0x32, 0x60, 0xb0, 0x42, 0x7c, 0xf3, 0xe1, 0x29, 0xbe, - 0xc0, 0xc1, 0x4b, 0x4e, 0xcb, 0x41, 0x63, 0x04, 0xc1, 0xe0, 0x75, 0x06, - 0xc3, 0xcd, 0xeb, 0x7f, 0xe9, 0x36, 0x32, 0x52, 0xb4, 0xe9, 0x59, 0x42, - 0x96, 0xc9, 0x5b, 0x57, 0x95, 0xf6, 0x40, 0xd2, 0xcf, 0x04, 0xe7, 0xe6, - 0x55, 0x18, 0x94, 0xb2, 0x6a, 0x1a, 0x3a, 0x05, 0xd1, 0x78, 0xd3, 0xd9, - 0x29, 0x04, 0x03, 0x9c, 0x4b, 0x6a, 0xa2, 0x49, 0x54, 0x31, 0xa2, 0xfb, - 0x61, 0x64, 0x5c, 0x5d, 0x3c, 0x3b, 0x2a, 0x9a, 0xe6, 0x81, 0xa8, 0xa7, - 0x9a, 0xe9, 0x01, 0xa7, 0xc6, 0x02, 0xfa, 0x36, 0x47, 0x00, 0x04, 0xc5, - 0xe6, 0xf1, 0xb7, 0xe2, 0x0d, 0xe7, 0xcf, 0x44, 0x41, 0xf7, 0x14, 0x01, - 0x81, 0x0a, 0xa6, 0x3f, 0x51, 0xa1, 0x1c, 0xa3, 0xd4, 0x1e, 0x09, 0x59, - 0xb1, 0x09, 0x55, 0xd4, 0xd2, 0xb6, 0xc5, 0x0b, 0xcf, 0x3a, 0x05, 0xdd, - 0xd2, 0xa9, 0x0e, 0x35, 0xcc, 0xc9, 0x16, 0x43, 0x32, 0xb3, 0xf8, 0x0d, - 0x81, 0x27, 0x4f, 0x38, 0xa1, 0x57, 0xd4, 0xbb, 0x44, 0x06, 0xac, 0x7f, - 0x2b, 0x1d, 0x2b, 0x5e, 0x19, 0xfb, 0xb3, 0x0a, 0x2a, 0x7c, 0x0b, 0xfd, - 0x49, 0xae, 0x28, 0xe7, 0xa9, 0x89, 0xbe, 0x53, 0x11, 0x3f, 0xf6, 0x41, - 0xcb, 0xe7, 0xe0, 0x3c, 0x20, 0xfc, 0x34, 0xd2, 0xe0, 0x4b, 0xe7, 0xc4, - 0x02, 0x1c, 0x46, 0xb7, 0xb0, 0xca, 0x31, 0x27, 0x3d, 0xee, 0xfd, 0xb0, - 0x81, 0xe3, 0xd9, 0xd1, 0xc9, 0x87, 0x55, 0xdf, 0x81, 0x13, 0xf0, 0xc8, - 0x1e, 0x1e, 0x58, 0xee, 0x43, 0xe7, 0xc9, 0x33, 0xf8, 0x21, 0xcb, 0x74, - 0xfa, 0xee, 0x12, 0x37, 0x10, 0xff, 0x20, 0xd0, 0x0a, 0x74, 0x3f, 0xe5, - 0xab, 0x29, 0x08, 0x3e, 0x2d, 0x61, 0xe3, 0xfc, 0x0c, 0xe8, 0x98, 0xc2, - 0x7f, 0xfa, 0xef, 0xa8, 0x06, 0x39, 0x1f, 0x8f, 0x06, 0x2b, 0x40, 0xd2, - 0xbb, 0xdc, 0xcc, 0x9b, 0xab, 0x0e, 0x22, 0x21, 0xb1, 0xe3, 0x37, 0xfa, - 0x36, 0xd9, 0xd1, 0x1c, 0x3c, 0xe9, 0xf3, 0x7b, 0x3c, 0xee, 0xe0, 0xbc, - 0x00, 0x19, 0xf7, 0x5e, 0xf6, 0xe4, 0x3f, 0xcf, 0x36, 0xbf, 0xed, 0x0f, - 0x3d, 0x0d, 0xf6, 0x5c, 0x2b, 0x1a, 0xd6, 0xfc, 0x81, 0x48, 0xcd, 0x3e, - 0xe6, 0xd1, 0x41, 0x1f, 0xdb, 0x09, 0x37, 0xd5, 0x21, 0x4d, 0x13, 0x27, - 0x1c, 0x00, 0xcf, 0xde, 0x58, 0xd5, 0x81, 0x2d, 0x02, 0x43, 0xd1, 0x4d, - 0xba, 0x0e, 0xea, 0xe9, 0x9d, 0x40, 0xbc, 0x1f, 0x15, 0x02, 0x3b, 0x1b, - 0xd1, 0xea, 0xc5, 0xdb, 0xd5, 0x05, 0x7a, 0xce, 0x26, 0x10, 0x9c, 0xd7, - 0x66, 0xfd, 0xa8, 0xb9, 0xb8, 0x0f, 0x36, 0x52, 0x1b, 0x49, 0x0c, 0xbf, - 0x52, 0x45, 0xe7, 0x57, 0xb2, 0xe1, 0xaf, 0x04, 0xe8, 0x40, 0xc2, 0x17, - 0xef, 0x12, 0x31, 0xaf, 0x81, 0x92, 0x11, 0xe5, 0xce, 0xd1, 0x08, 0x3f, - 0x8d, 0xc9, 0xb1, 0xb8, 0x09, 0xf1, 0xe8, 0xda, 0xf7, 0x5b, 0x13, 0x91, - 0x13, 0xc0, 0x67, 0x09, 0xa9, 0x97, 0x8f, 0xb9, 0x7f, 0x0b, 0x2d, 0x17, - 0xfb, 0x00, 0x33, 0xee, 0x52, 0xd6, 0x38, 0xc9, 0x29, 0x03, 0xe6, 0x0e, - 0xc4, 0xff, 0x83, 0x6b, 0xf5, 0x7b, 0x36, 0x1b, 0x15, 0x1b, 0xc9, 0xa2, - 0xea, 0x0e, 0x12, 0x3a, 0x71, 0x32, 0x2a, 0x99, 0x13, 0x64, 0x7f, 0x66, - 0xd7, 0x71, 0xa5, 0x55, 0x1a, 0x31, 0xf7, 0x69, 0x75, 0xba, 0xc0, 0x33, - 0x35, 0xd4, 0x11, 0xec, 0x2e, 0x45, 0xc3, 0x6e, 0x85, 0x37, 0x36, 0xa0, - 0x3b, 0x44, 0xe0, 0x6d, 0x29, 0x50, 0x9b, 0x4b, 0x40, 0xfc, 0xc3, 0x81, - 0xeb, 0x32, 0x5b, 0x18, 0xcb, 0xbc, 0x51, 0x54, 0x1a, 0xbb, 0x11, 0xc8, - 0x54, 0xa6, 0xd0, 0xb8, 0xfc, 0xd7, 0x30, 0xfd, 0x30, 0x04, 0xff, 0xb2, - 0x2d, 0x4a, 0x3e, 0xf0, 0xff, 0xc0, 0x25, 0xd7, 0xb8, 0x0a, 0x00, 0x5f, - 0xf4, 0xfb, 0x11, 0xb4, 0x39, 0xb7, 0x1e, 0xed, 0xd7, 0xd7, 0xbf, 0xae, - 0x00, 0x7f, 0x10, 0xfd, 0x37, 0xf8, 0x15, 0x27, 0x1a, 0xd1, 0x2b, 0xe3, - 0x40, 0x47, 0x01, 0xc7, 0x1a, 0x32, 0xa4, 0x34, 0xb2, 0x55, 0x06, 0x3e, - 0xbb, 0x25, 0x21, 0xdf, 0x07, 0xba, 0x2f, 0x7f, 0x2e, 0x0b, 0x22, 0x00, - 0xf6, 0xe6, 0xff, 0xf2, 0x3b, 0xcf, 0x1a, 0x1f, 0xfe, 0xae, 0xf2, 0x04, - 0xe9, 0xcf, 0xc3, 0x1d, 0xea, 0x2c, 0x03, 0xc8, 0x1e, 0xd4, 0xe3, 0x1d, - 0xc4, 0xd0, 0x3e, 0xe2, 0x11, 0x1f, 0x1d, 0xe0, 0xf2, 0xf5, 0x95, 0x37, - 0xfd, 0x56, 0x7f, 0x45, 0x76, 0xee, 0x38, 0xf2, 0x91, 0x94, 0x55, 0x5d, - 0xc3, 0x4d, 0x0c, 0xd2, 0xb5, 0xcb, 0x2f, 0x28, 0xa8, 0x36, 0x2d, 0xb9, - 0x04, 0xad, 0xbe, 0xeb, 0x33, 0x40, 0x25, 0x9c, 0x59, 0xbd, 0xd5, 0x31, - 0x3c, 0x7f, 0x3d, 0x6e, 0x14, 0xda, 0x4c, 0x61, 0x56, 0x41, 0x13, 0xf7, - 0xb7, 0xc0, 0x6f, 0xfa, 0x4a, 0x0c, 0x60, 0x55, 0xfd, 0xdf, 0x14, 0x4f, - 0xfb, 0xc6, 0xd4, 0xd1, 0x03, 0xf9, 0x9e, 0x18, 0xc3, 0x3c, 0xf9, 0x24, - 0x68, 0xde, 0x03, 0x2e, 0xcb, 0xf9, 0x2a, 0x56, 0xcf, 0xee, 0x61, 0x19, - 0x59, 0xa8, 0x75, 0xe7, 0x7f, 0x37, 0xfd, 0xdf, 0xe0, 0x1f, 0xea, 0xe6, - 0xf1, 0x59, 0x23, 0x3c, 0x99, 0x1c, 0xea, 0xde, 0x0c, 0x35, 0xd3, 0xe8, - 0x43, 0xbb, 0xf1, 0x17, 0x36, 0x3b, 0xff, 0x01, 0xea, 0x0f, 0xf7, 0x5b, - 0x3d, 0xc8, 0xfd, 0x34, 0x0f, 0xbc, 0xde, 0x1b, 0xa2, 0xce, 0xd1, 0xd8, - 0x07, 0x27, 0x7f, 0x42, 0xbb, 0x4f, 0xfb, 0xb6, 0x34, 0x27, 0x08, 0x2c, - 0x0e, 0xc6, 0x07, 0x34, 0xd2, 0xd2, 0xfc, 0xe6, 0xdb, 0xe2, 0xfd, 0x3a, - 0x3a, 0x08, 0x5b, 0x61, 0x09, 0xf0, 0x65, 0x9d, 0xdd, 0x42, 0x3f, 0xc7, - 0x47, 0x2a, 0xca, 0x81, 0xf8, 0x7d, 0x98, 0x89, 0xb6, 0xc1, 0xbf, 0xe3, - 0xd6, 0xc9, 0xfb, 0x5d, 0x40, 0x11, 0xb7, 0x96, 0xc5, 0x4a, 0xc8, 0x99, - 0xf1, 0x6b, 0x08, 0xde, 0x81, 0x3a, 0xf7, 0xf5, 0xbb, 0x9e, 0xcd, 0x33, - 0xc8, 0xe9, 0xcc, 0x45, 0x51, 0x2c, 0x1d, 0xe0, 0x6a, 0x12, 0xcf, 0xa3, - 0x29, 0x41, 0xf5, 0x38, 0x07, 0x1c, 0xae, 0x2b, 0x69, 0x71, 0x41, 0x24, - 0x13, 0x59, 0x66, 0xe4, 0x54, 0xaa, 0xb2, 0x3d, 0xb5, 0x48, 0x09, 0xa7, - 0xa0, 0xf3, 0xfc, 0x50, 0x1c, 0xdb, 0xd6, 0x07, 0xb2, 0xbd, 0xb8, 0xf3, - 0x12, 0x28, 0xb9, 0x3a, 0x2e, 0x36, 0x4c, 0xb4, 0xdc, 0x17, 0x27, 0xc6, - 0x52, 0x44, 0xd3, 0xf4, 0x0b, 0x06, 0xe0, 0x7f, 0xc3, 0xcc, 0x54, 0xcc, - 0x1e, 0x83, 0x61, 0x0e, 0x99, 0xe0, 0xb6, 0xfb, 0xd4, 0x34, 0x4a, 0x71, - 0x03, 0xb7, 0x37, 0x1c, 0x29, 0xc3, 0x82, 0xd7, 0x1d, 0xcf, 0x79, 0xdf, - 0x55, 0x45, 0xd1, 0x59, 0x01, 0xa9, 0x04, 0xf6, 0x04, 0xe4, 0xea, 0x3e, - 0x28, 0x81, 0x14, 0xf4, 0xcb, 0x38, 0xe7, 0x68, 0x4f, 0x2a, 0x02, 0xe0, - 0x58, 0xa2, 0xc2, 0xdb, 0xcf, 0x03, 0xbe, 0x24, 0xa7, 0x1b, 0xde, 0x7f, - 0x91, 0x3e, 0x2e, 0xae, 0x45, 0x01, 0xce, 0x38, 0xee, 0x58, 0xdc, 0xc3, - 0x59, 0xd0, 0x1e, 0xd0, 0x39, 0xd2, 0x1f, 0x70, 0xf7, 0x81, 0xe0, 0x8a, - 0x2b, 0x5f, 0xfd, 0x59, 0x6b, 0x83, 0xbc, 0xa3, 0xf0, 0x57, 0xe4, 0xde, - 0xab, 0xe1, 0xf7, 0xf4, 0x75, 0x28, 0xa2, 0xcb, 0x00, 0x09, 0x0a, 0x8d, - 0xa6, 0xf1, 0x6a, 0x2d, 0xdf, 0x62, 0x0c, 0x88, 0xec, 0xfe, 0x6b, 0xa1, - 0xba, 0x22, 0xfa, 0x65, 0xf0, 0x20, 0x5d, 0x18, 0x48, 0x46, 0xe4, 0x02, - 0x7f, 0x43, 0x38, 0x24, 0xeb, 0x14, 0x06, 0xe5, 0xc0, 0x0d, 0x20, 0x64, - 0x93, 0xd7, 0x13, 0x29, 0x13, 0x53, 0x1c, 0x19, 0x66, 0x31, 0x65, 0x2e, - 0x01, 0x47, 0xe4, 0xd8, 0x60, 0xa5, 0x52, 0xc5, 0xab, 0xb2, 0xde, 0x8f, - 0x81, 0x3c, 0x34, 0x3f, 0x94, 0xab, 0x28, 0x77, 0xda, 0xde, 0x08, 0x36, - 0xc4, 0xda, 0x3b, 0x57, 0x32, 0x15, 0x2d, 0x33, 0xc5, 0xc6, 0x16, 0xee, - 0x38, 0xc3, 0xcd, 0x2e, 0x22, 0x23, 0x48, 0xd5, 0xfa, 0x81, 0xff, 0xa8, - 0xc1, 0x46, 0x20, 0xaf, 0x4f, 0x21, 0xa7, 0x06, 0x51, 0x07, 0xf6, 0x34, - 0xaf, 0xd3, 0x14, 0x15, 0x38, 0x29, 0x3c, 0x4b, 0x5e, 0xeb, 0x25, 0x38, - 0x34, 0x9b, 0xb2, 0xb8, 0xb5, 0xf2, 0x4b, 0x34, 0xb9, 0x37, 0x64, 0x3d, - 0xa7, 0x06, 0x49, 0xc2, 0xf9, 0xfd, 0x45, 0xa7, 0x97, 0x6c, 0xc7, 0x11, - 0x13, 0xda, 0x49, 0x13, 0xbf, 0xc5, 0x2b, 0x18, 0x3b, 0xfe, 0xf2, 0xfc, - 0x38, 0x6c, 0x4a, 0xb3, 0xd0, 0x15, 0xaf, 0xc6, 0xcc, 0xb6, 0xe3, 0xd6, - 0x7f, 0x98, 0x09, 0x5a, 0xbd, 0x60, 0xe5, 0x4a, 0x5a, 0x23, 0xdc, 0x53, - 0x63, 0xf2, 0x44, 0x22, 0xb3, 0x81, 0x10, 0x3d, 0x47, 0xee, 0xde, 0x00, - 0xde, 0xad, 0xe8, 0x95, 0x9c, 0xf8, 0xcf, 0xcd, 0x43, 0xea, 0xf1, 0x53, - 0x77, 0x77, 0xac, 0xca, 0xd1, 0x98, 0xd2, 0x15, 0xa2, 0xd0, 0xec, 0xec, - 0x2c, 0x81, 0xfa, 0x1d, 0x08, 0x46, 0x56, 0xdd, 0xf0, 0x4b, 0xb9, 0xf0, - 0x0e, 0x40, 0xe9, 0xcd, 0xf0, 0x99, 0x69, 0x2e, 0x5e, 0x9a, 0xef, 0xe1, - 0x3b, 0xe9, 0x1e, 0x12, 0x71, 0x2d, 0xbd, 0x29, 0x9f, 0xb0, 0x91, 0xbf, - 0x5c, 0xc0, 0xd2, 0x45, 0x09, 0xb9, 0xdc, 0x17, 0xa5, 0xe1, 0xcf, 0xf0, - 0x6d, 0xc8, 0xbf, 0xdd, 0xf4, 0x34, 0xd0, 0x56, 0x85, 0xd8, 0x3c, 0xf9, - 0x2b, 0xa9, 0x49, 0xb8, 0xf1, 0xb0, 0x75, 0xf3, 0xbf, 0xd6, 0x29, 0x81, - 0xd6, 0x04, 0xe0, 0x2f, 0x30, 0xae, 0xd3, 0xa4, 0x81, 0xba, 0x87, 0xa8, - 0xa7, 0x0d, 0x5e, 0x45, 0xea, 0xb0, 0xd1, 0x44, 0x14, 0xa1, 0xbd, 0x2b, - 0xdc, 0xcd, 0x6a, 0xf8, 0x2b, 0x65, 0xe8, 0x72, 0x6c, 0x9e, 0xd2, 0x51, - 0x19, 0x0b, 0xbf, 0xff, 0x34, 0x02, 0x19, 0x41, 0xe3, 0x2c, 0x2e, 0xc4, - 0xb8, 0x63, 0x40, 0x52, 0x24, 0x2c, 0x81, 0x30, 0xd8, 0x15, 0x3c, 0xb4, - 0x8c, 0x8c, 0x2b, 0x07, 0xec, 0x0c, 0x04, 0xca, 0xa1, 0xfb, 0xb5, 0x56, - 0x01, 0xc3, 0x13, 0x3f, 0x5c, 0xc0, 0x73, 0x14, 0xd1, 0x95, 0xd2, 0xc5, - 0x2a, 0x06, 0xb0, 0x81, 0x06, 0xe7, 0x16, 0x38, 0xda, 0xc9, 0x23, 0xb5, - 0x45, 0x63, 0xbd, 0x16, 0xc6, 0x3f, 0xc6, 0x19, 0x2f, 0xd1, 0x9e, 0x2e, - 0xc7, 0x0d, 0x60, 0xdd, 0xfe, 0x64, 0x92, 0x0d, 0xbc, 0x9e, 0x3d, 0x2d, - 0x50, 0xc5, 0x5d, 0x05, 0xc4, 0xf0, 0xa9, 0x0f, 0x16, 0xdd, 0xa3, 0xe3, - 0x12, 0xa3, 0x13, 0x48, 0x99, 0x52, 0x51, 0xc1, 0x09, 0x25, 0xfe, 0x07, - 0x22, 0x8f, 0x81, 0x42, 0xf5, 0xfc, 0xc6, 0x4a, 0x3b, 0x2b, 0xd3, 0x1f, - 0xe4, 0x1d, 0x12, 0x69, 0x01, 0xe3, 0xa2, 0x01, 0xce, 0x26, 0xea, 0x28, - 0xf4, 0xc4, 0x57, 0xf3, 0x52, 0x21, 0x36, 0x50, 0x33, 0x9b, 0x1b, 0xeb, - 0x55, 0xe7, 0x1d, 0x3a, 0x7f, 0xf3, 0xfc, 0x50, 0xfc, 0x25, 0x27, 0xe6, - 0xde, 0x24, 0xcb, 0xb9, 0xd4, 0x19, 0xda, 0x1e, 0x2d, 0xcd, 0xe8, 0xb4, - 0x88, 0x2d, 0xfe, 0x00, 0xd2, 0x38, 0x1c, 0x43, 0x5a, 0xc3, 0xf0, 0xda, - 0xb4, 0xc8, 0x48, 0xce, 0xd7, 0xcd, 0xfa, 0xee, 0xc2, 0xdb, 0x47, 0xa4, - 0x72, 0xbc, 0xc2, 0xa5, 0xf9, 0xd7, 0x0e, 0xc1, 0xc7, 0x6a, 0x20, 0x34, - 0x0c, 0x81, 0xcb, 0xd5, 0x5e, 0xbe, 0x2e, 0x43, 0xbf, 0x10, 0xc8, 0x1c, - 0x04, 0xc1, 0x59, 0x07, 0x44, 0xb9, 0x01, 0xd8, 0x14, 0x48, 0xfd, 0x08, - 0x36, 0x5f, 0xe5, 0x01, 0x36, 0x36, 0x28, 0x2c, 0x1e, 0xd3, 0x4c, 0xdb, - 0x39, 0xde, 0xd8, 0xdd, 0x26, 0x7f, 0xe6, 0x54, 0x08, 0x35, 0x4a, 0x7f, - 0xe0, 0xbd, 0x0b, 0xb5, 0x41, 0xb8, 0xa7, 0xf9, 0xc0, 0x21, 0x12, 0xdf, - 0xa5, 0xc4, 0xd6, 0xcc, 0xa2, 0x43, 0xcb, 0xdf, 0x26, 0x43, 0xe1, 0xf7, - 0xec, 0xa1, 0xee, 0xf5, 0x41, 0x9f, 0xf0, 0x5c, 0x38, 0xb1, 0x57, 0xd0, - 0xfe, 0x79, 0x6d, 0xaf, 0xfe, 0xee, 0x39, 0x9a, 0xc9, 0xd2, 0x6d, 0xad, - 0x5e, 0xee, 0x1e, 0x7f, 0xd3, 0xaa, 0x46, 0x92, 0xcc, 0xfd, 0x31, 0xc0, - 0x37, 0xb0, 0xe3, 0x32, 0x4d, 0x2c, 0xa5, 0x8d, 0x9c, 0xdc, 0x9b, 0xec, - 0xd5, 0xbb, 0xa7, 0x17, 0x2c, 0xe0, 0xe3, 0x2c, 0xdc, 0xfa, 0x9e, 0x81, - 0xc2, 0x4b, 0xec, 0xba, 0x0c, 0xe3, 0x3a, 0xf0, 0x6b, 0x1d, 0xa1, 0x99, - 0x6d, 0x3b, 0x36, 0xc4, 0x48, 0x28, 0x54, 0xa0, 0xa3, 0x27, 0x44, 0x2f, - 0xe7, 0x3f, 0x50, 0x1b, 0x52, 0xf3, 0xb7, 0x92, 0xe5, 0x81, 0x69, 0x5d, - 0x98, 0xa5, 0x4c, 0x3c, 0x10, 0x46, 0xca, 0xfc, 0x52, 0xe2, 0x42, 0x23, - 0xd4, 0x57, 0xb1, 0x78, 0x21, 0x07, 0x2f, 0xd6, 0x35, 0xce, 0x2e, 0x6d, - 0xa3, 0xda, 0xaf, 0x3e, 0x25, 0x2e, 0x32, 0xa5, 0xec, 0x27, 0x30, 0xf2, - 0x46, 0x26, 0x10, 0x00, 0xbb, 0x26, 0x2c, 0x4e, 0xd8, 0xf0, 0x01, 0x71, - 0x27, 0x48, 0x4c, 0x6b, 0x27, 0x59, 0x44, 0xbe, 0xb3, 0x2e, 0x39, 0x30, - 0x39, 0x7f, 0x51, 0xe5, 0x0c, 0x95, 0x98, 0xe7, 0x3b, 0xe4, 0xe6, 0x4d, - 0x21, 0x2c, 0xc5, 0x30, 0xd7, 0xf8, 0x5b, 0xa7, 0xaa, 0x67, 0xf7, 0x1c, - 0xef, 0xb6, 0xcf, 0xc4, 0xeb, 0x42, 0x92, 0xeb, 0xa9, 0xf7, 0xd0, 0x3e, - 0x43, 0x06, 0xb2, 0xd9, 0x1d, 0xa2, 0xc2, 0xf7, 0x28, 0x32, 0x81, 0x11, - 0xdc, 0xba, 0xe8, 0x3e, 0x0b, 0xc2, 0x19, 0xc1, 0x23, 0x3e, 0x5a, 0x3a, - 0x1f, 0xe3, 0x21, 0xc0, 0x7f, 0x3f, 0x7b, 0xc6, 0x02, 0x14, 0x19, 0xe4, - 0x12, 0x34, 0xdc, 0x44, 0x6a, 0xd4, 0x09, 0x67, 0xf9, 0x6c, 0xf8, 0xef, - 0x25, 0xd9, 0x09, 0xb5, 0x57, 0x30, 0x52, 0xed, 0xf8, 0x28, 0x1a, 0x0d, - 0x76, 0x11, 0x0d, 0xa8, 0x1a, 0x0f, 0x53, 0x37, 0x00, 0x9f, 0xdf, 0x43, - 0xb8, 0x5f, 0x9a, 0x81, 0x67, 0x68, 0xce, 0xe5, 0xe8, 0x72, 0x16, 0xf0, - 0x2f, 0xa4, 0xa7, 0xa5, 0x54, 0xf4, 0x41, 0x1e, 0x2a, 0xe4, 0x17, 0x07, - 0xbe, 0xb0, 0xe7, 0x18, 0x24, 0x5b, 0x2e, 0x7f, 0x48, 0xd9, 0x3a, 0x46, - 0xaf, 0x60, 0x48, 0xdc, 0xf5, 0x05, 0x4f, 0x0a, 0x46, 0xfb, 0x1d, 0xc4, - 0xba, 0xf9, 0xda, 0xe3, 0x28, 0x49, 0xfd, 0xcc, 0x2d, 0xdb, 0x2d, 0x2b, - 0xe9, 0x91, 0x01, 0x1f, 0x0f, 0xd2, 0xc7, 0xa4, 0x14, 0xb6, 0x2a, 0xfe, - 0x81, 0xd4, 0xa4, 0xc9, 0xc8, 0x09, 0x47, 0x63, 0xb3, 0x9a, 0x02, 0xff, - 0x11, 0xf5, 0xd9, 0xc4, 0xe5, 0xb8, 0x65, 0x2d, 0x60, 0x1e, 0x1d, 0x4d, - 0x3e, 0xbd, 0x19, 0xb1, 0x0f, 0xa6, 0x11, 0x03, 0x03, 0xeb, 0x20, 0xf1, - 0x07, 0xd1, 0x9a, 0xd8, 0xe9, 0xdc, 0xcb, 0x54, 0xdc, 0x1e, 0xa0, 0x09, - 0x12, 0x0e, 0x3d, 0xea, 0xb4, 0xb8, 0x1b, 0x45, 0x79, 0x33, 0xa8, 0xbf, - 0x32, 0x25, 0x45, 0x87, 0xf5, 0xcd, 0xa2, 0xb9, 0xa2, 0xe0, 0x4a, 0x2d, - 0xea, 0xe9, 0x7f, 0x88, 0xf3, 0x0b, 0x52, 0xe0, 0x96, 0xb4, 0x38, 0xdf, - 0x0a, 0x1f, 0xcc, 0xd4, 0xab, 0xc4, 0x3f, 0xaf, 0xb0, 0xcd, 0x20, 0x2f, - 0x12, 0xde, 0x27, 0x23, 0xef, 0x17, 0x21, 0x3a, 0x3e, 0x42, 0x38, 0x33, - 0xac, 0x49, 0x4e, 0x9d, 0xc6, 0xd6, 0x81, 0xd5, 0xa4, 0xdc, 0xa8, 0x5c, - 0xd8, 0xa0, 0xcd, 0x34, 0x50, 0x5e, 0xb4, 0x4c, 0x0a, 0xee, 0xc3, 0x25, - 0x81, 0xed, 0x65, 0x00, 0x9f, 0x68, 0x35, 0x96, 0x36, 0x6b, 0x7a, 0x4b, - 0x7c, 0x10, 0xcf, 0x4b, 0xe1, 0x4c, 0xa6, 0x9c, 0x24, 0x54, 0xbd, 0x63, - 0xd6, 0xde, 0x1e, 0x45, 0xf3, 0x39, 0xa1, 0x49, 0x12, 0xf9, 0x31, 0xce, - 0xb0, 0x15, 0x3e, 0xb2, 0x58, 0xce, 0xe4, 0xfc, 0x81, 0x56, 0x92, 0x8e, - 0x01, 0xcb, 0xc4, 0xc4, 0x50, 0x1a, 0x98, 0xec, 0x40, 0x4d, 0x02, 0x00, - 0xb7, 0xba, 0x34, 0xa7, 0x59, 0xf7, 0xbc, 0x89, 0x1c, 0xd1, 0x16, 0xf5, - 0x89, 0x42, 0xa0, 0xbf, 0x81, 0x3f, 0xe6, 0xec, 0x05, 0x48, 0xd8, 0x89, - 0x35, 0xd4, 0x78, 0x0a, 0xe0, 0x27, 0xc7, 0xfc, 0xab, 0xa8, 0xcb, 0x52, - 0x23, 0x9d, 0x19, 0x1f, 0xeb, 0x5a, 0x02, 0x5e, 0x60, 0x2e, 0x0f, 0xd4, - 0x6e, 0x10, 0x4b, 0x7f, 0xf2, 0x08, 0xa8, 0x1c, 0x09, 0xbb, 0xf5, 0xbf, - 0x06, 0xbf, 0xf2, 0x0a, 0xeb, 0x60, 0xc7, 0x4b, 0x00, 0x48, 0x53, 0x32, - 0xd0, 0x36, 0x55, 0x0e, 0x04, 0x17, 0x41, 0xdc, 0x4a, 0xc9, 0xf1, 0xf3, - 0xe6, 0xd5, 0xd6, 0x17, 0x00, 0xb9, 0x1d, 0x45, 0x1e, 0xbe, 0xbf, 0xb8, - 0x24, 0x1b, 0x81, 0xca, 0xe4, 0xd9, 0x29, 0xfc, 0xb2, 0xd0, 0x3f, 0xbb, - 0x3d, 0xfc, 0x33, 0x11, 0xe3, 0xf9, 0x3c, 0xad, 0x25, 0xf9, 0xe4, 0xe8, - 0xef, 0xc4, 0x3c, 0xbf, 0x24, 0x11, 0x27, 0x05, 0xb4, 0x17, 0x47, 0xe3, - 0x2c, 0xb1, 0x31, 0xfb, 0x22, 0xce, 0xa9, 0x50, 0x36, 0xb7, 0x1c, 0xbe, - 0xbd, 0x46, 0x4e, 0x06, 0xe7, 0x33, 0xc4, 0xa1, 0xdb, 0xd2, 0x07, 0xfc, - 0x4c, 0xc5, 0xc9, 0x5c, 0xf9, 0x7f, 0x26, 0x23, 0xd7, 0x95, 0x5d, 0x5c, - 0xa9, 0xaf, 0xdb, 0xd3, 0x14, 0x4f, 0x05, 0xf5, 0x3e, 0x28, 0x29, 0x40, - 0xc7, 0xed, 0xd2, 0x2e, 0xe1, 0xdc, 0xc1, 0x2f, 0xbe, 0x14, 0xb1, 0xc4, - 0x21, 0x20, 0xd7, 0x7f, 0xf7, 0x1b, 0x01, 0xd1, 0xaa, 0x1a, 0x2e, 0xe7, - 0x02, 0xd9, 0x01, 0x65, 0xdc, 0x3d, 0x4f, 0x47, 0x5a, 0xf8, 0xfb, 0x16, - 0x3b, 0x77, 0x4f, 0xd4, 0x6b, 0x16, 0x83, 0xaf, 0xf9, 0x90, 0xf2, 0xb3, - 0xd2, 0x9d, 0x18, 0xde, 0xc3, 0x7f, 0xa5, 0xf0, 0x4a, 0x5c, 0x37, 0xc5, - 0x69, 0x2c, 0xdb, 0x66, 0x7e, 0xcd, 0x32, 0xf7, 0x94, 0xaf, 0x71, 0xf1, - 0xdf, 0x1f, 0xf3, 0x1a, 0x97, 0x60, 0x94, 0xdb, 0xeb, 0x0b, 0x4a, 0xd1, - 0xf9, 0x02, 0x2c, 0xad, 0x00, 0x92, 0xd8, 0xad, 0x65, 0xae, 0x0d, 0x25, - 0x29, 0x7c, 0x7c, 0x42, 0x1b, 0x0b, 0x7f, 0x09, 0x40, 0xe5, 0x35, 0x46, - 0xc3, 0x43, 0xe9, 0x33, 0xce, 0x4b, 0x3a, 0xe2, 0x1f, 0x04, 0x01, 0xed, - 0x7f, 0x47, 0x50, 0xce, 0x9d, 0x23, 0xbd, 0x66, 0x33, 0x63, 0x60, 0x4d, - 0xf0, 0x03, 0xa4, 0xc6, 0xb2, 0x34, 0xb9, 0xe9, 0x08, 0xc6, 0x35, 0xbe, - 0x12, 0xe0, 0x8e, 0xb5, 0x58, 0xdf, 0x30, 0xc7, 0x00, 0xd1, 0x72, 0xa3, - 0x5c, 0x42, 0xd1, 0xe2, 0x37, 0xb1, 0x03, 0xad, 0xe5, 0x0c, 0x30, 0x08, - 0x21, 0x66, 0xb3, 0x60, 0xdb, 0x94, 0x91, 0xd9, 0x0f, 0xe5, 0x7f, 0x5d, - 0x6c, 0x08, 0x3e, 0xf6, 0x06, 0x04, 0x19, 0xdd, 0xfd, 0x4a, 0x4b, 0xf2, - 0x44, 0x18, 0x81, 0xe7, 0x9a, 0xd0, 0x9a, 0x34, 0xa7, 0x1b, 0x37, 0x29, - 0x06, 0x5b, 0xe4, 0xf8, 0xec, 0x3e, 0x00, 0xd6, 0x4d, 0xe3, 0x24, 0xfe, - 0x36, 0x09, 0xc7, 0x40, 0x18, 0xf3, 0xaa, 0xe4, 0x01, 0x65, 0x52, 0x22, - 0x8b, 0xa8, 0x14, 0xd2, 0x50, 0xd4, 0xcd, 0xd0, 0xbf, 0x33, 0x32, 0xde, - 0x5c, 0x18, 0x2e, 0x0a, 0x10, 0x58, 0x1c, 0x9a, 0x7f, 0xec, 0x26, 0xa1, - 0xc4, 0xa8, 0x26, 0x0d, 0x0d, 0x3f, 0x13, 0x3d, 0xdb, 0x2f, 0x5b, 0x02, - 0x72, 0x9a, 0x9b, 0xaa, 0x2e, 0xb2, 0xd6, 0xde, 0x0e, 0x34, 0xe0, 0x46, - 0x43, 0xcf, 0xc3, 0xb2, 0xc0, 0x52, 0xca, 0x27, 0x0f, 0x17, 0x12, 0xc7, - 0x31, 0x7f, 0x26, 0x14, 0xfa, 0xc2, 0x0e, 0x44, 0xfa, 0x45, 0xe6, 0x25, - 0xc4, 0x24, 0xae, 0x3e, 0x0a, 0xc9, 0x2d, 0x94, 0xc6, 0x54, 0x05, 0x7f, - 0xf2, 0xc4, 0x34, 0xfa, 0x1f, 0x35, 0x01, 0x55, 0x2f, 0xcb, 0x63, 0xf2, - 0x57, 0xbc, 0x3f, 0x07, 0xef, 0xb8, 0x0b, 0x4b, 0x0a, 0xfd, 0xf4, 0x53, - 0x46, 0xe3, 0xd7, 0x3d, 0x47, 0x99, 0xd1, 0xcd, 0x68, 0x4b, 0xf4, 0x6a, - 0xef, 0x33, 0x10, 0x7f, 0xf3, 0xad, 0x42, 0x14, 0x30, 0xa7, 0xe2, 0x30, - 0xcf, 0x02, 0x49, 0x2a, 0xad, 0xbf, 0xe2, 0x39, 0xe4, 0xda, 0xd2, 0xe9, - 0x98, 0xbc, 0x24, 0xf0, 0x64, 0x6f, 0x0a, 0xdd, 0x07, 0x08, 0x3e, 0x38, - 0x58, 0xee, 0x1c, 0xb7, 0x64, 0x07, 0x6a, 0x37, 0xd7, 0x0c, 0x99, 0xd8, - 0x38, 0xdb, 0x5c, 0x0e, 0x28, 0x43, 0x02, 0xf8, 0xa6, 0xb6, 0x42, 0xcc, - 0xda, 0x1b, 0x3a, 0x05, 0xdd, 0x7f, 0xb7, 0x01, 0x01, 0x3d, 0xa9, 0x4c, - 0x4d, 0x2f, 0x2d, 0xc7, 0xd1, 0xc9, 0x81, 0x9d, 0xe2, 0x82, 0x3d, 0x8e, - 0xb0, 0xa4, 0x2d, 0xd0, 0x0a, 0x42, 0xcc, 0x99, 0x68, 0x56, 0xfe, 0x2c, - 0xf9, 0x43, 0x97, 0x85, 0xb3, 0x5f, 0x18, 0x16, 0x05, 0x98, 0x47, 0x84, - 0x41, 0xfa, 0xdf, 0x31, 0x43, 0xf2, 0xf3, 0x6d, 0xef, 0x52, 0x7f, 0xab, - 0xb9, 0xad, 0x96, 0x40, 0xe7, 0xee, 0xbd, 0x30, 0x33, 0xf4, 0x4e, 0x15, - 0x26, 0xe1, 0x0e, 0x11, 0x26, 0x02, 0x9f, 0x27, 0xb9, 0xa4, 0xcc, 0xd9, - 0x09, 0xe8, 0x31, 0x54, 0x18, 0x2b, 0x0e, 0xb7, 0xfe, 0xf5, 0x1d, 0xd5, - 0xf8, 0x02, 0x72, 0x04, 0x05, 0xa6, 0xac, 0xdd, 0xb2, 0xff, 0x61, 0xfe, - 0x98, 0xbc, 0xab, 0xf3, 0xb9, 0xce, 0x13, 0x50, 0x9a, 0xd8, 0x46, 0xd9, - 0x59, 0xcf, 0x6a, 0x16, 0x0f, 0xe1, 0x7f, 0xe9, 0x20, 0xf7, 0x2a, 0xfe, - 0xfd, 0x34, 0xa3, 0xf6, 0x45, 0xb8, 0xee, 0x0f, 0xcc, 0x81, 0x5f, 0x56, - 0xcf, 0x0a, 0xb1, 0x51, 0x1d, 0x95, 0x95, 0x29, 0xdb, 0xc9, 0x14, 0x5c, - 0xf5, 0x20, 0x12, 0xad, 0xb7, 0xbe, 0x36, 0x59, 0xfe, 0xd9, 0xb6, 0x93, - 0xcd, 0x1e, 0xc6, 0xf3, 0xf4, 0x2d, 0x1d, 0x55, 0xf1, 0x42, 0xf1, 0x03, - 0x1a, 0x00, 0x28, 0x5e, 0xc0, 0x0e, 0xab, 0xf6, 0xd7, 0x1d, 0x1d, 0x23, - 0x08, 0x0d, 0xe5, 0x15, 0x81, 0x29, 0x38, 0xaa, 0xd7, 0xd1, 0xed, 0xd9, - 0x35, 0xe9, 0x07, 0xb6, 0x38, 0x0d, 0xab, 0x32, 0xf7, 0xe9, 0x3c, 0x3a, - 0x19, 0x84, 0x7a, 0xb0, 0x81, 0xe7, 0x0c, 0xe2, 0x9b, 0x14, 0xc8, 0x01, - 0xdc, 0x04, 0x0e, 0x59, 0xd7, 0x45, 0xca, 0x0e, 0x13, 0xa3, 0x18, 0xa5, - 0x01, 0x5a, 0x09, 0x70, 0x0b, 0x65, 0x43, 0x0c, 0x14, 0xe8, 0xe9, 0x2c, - 0x4a, 0x48, 0x09, 0x33, 0x54, 0xa8, 0xbf, 0x4f, 0x90, 0xd9, 0x01, 0x8c, - 0x29, 0x60, 0x1d, 0xb0, 0xb2, 0xa6, 0x2b, 0x81, 0x4a, 0x4f, 0x25, 0x9c, - 0xf1, 0x22, 0x47, 0xbb, 0xb4, 0x8d, 0xa3, 0x6f, 0x67, 0x6c, 0xff, 0x33, - 0xf4, 0xa2, 0x08, 0xe3, 0x6d, 0x5f, 0x3d, 0xda, 0x40, 0x11, 0xce, 0x2c, - 0x18, 0x01, 0x09, 0xb5, 0xc5, 0x13, 0xe9, 0xab, 0xf5, 0x2d, 0xab, 0xc6, - 0x39, 0x2e, 0x19, 0x2d, 0x7f, 0xc5, 0x1e, 0x14, 0x40, 0x03, 0xeb, 0xa9, - 0xe3, 0x31, 0x1f, 0xe7, 0x34, 0x05, 0x41, 0x57, 0xd3, 0x38, 0x2f, 0xf3, - 0x21, 0xc6, 0x5f, 0x5c, 0xf1, 0x00, 0x02, 0x27, 0x23, 0x19, 0xea, 0xd0, - 0x9f, 0xc9, 0x30, 0x9b, 0x9d, 0xe3, 0xf9, 0xb0, 0x67, 0x02, 0x0d, 0xf8, - 0xb9, 0x9d, 0x81, 0x55, 0xc1, 0x1c, 0x21, 0xa1, 0x9e, 0xf4, 0x02, 0x34, - 0xbb, 0x02, 0xce, 0xf6, 0x18, 0x32, 0xec, 0x7f, 0x38, 0xfe, 0x3f, 0x00, - 0x16, 0x4e, 0x09, 0xf5, 0xd2, 0x32, 0x64, 0x09, 0xe8, 0xcb, 0x40, 0x9d, - 0xdc, 0xeb, 0x19, 0x07, 0xc1, 0xf3, 0xdb, 0xf3, 0x50, 0xec, 0x14, 0xf8, - 0xc2, 0xed, 0x3f, 0xf6, 0x32, 0xed, 0x21, 0xe1, 0x74, 0xbe, 0x1e, 0xd2, - 0xd9, 0x9e, 0xeb, 0x5d, 0x40, 0x24, 0xc0, 0x16, 0xc3, 0xa8, 0x6a, 0x22, - 0x5a, 0x46, 0xb5, 0x58, 0x7f, 0x18, 0xd7, 0x55, 0x05, 0x28, 0xbd, 0xec, - 0x50, 0xac, 0xd8, 0xa2, 0x29, 0x3e, 0x5a, 0x17, 0x3c, 0x17, 0xa0, 0x50, - 0xc9, 0x81, 0x2e, 0xfd, 0x94, 0x0e, 0xe0, 0xcd, 0xc9, 0x53, 0xe9, 0x3c, - 0x23, 0xff, 0xf0, 0x56, 0x4d, 0xe0, 0x21, 0xfc, 0xb2, 0xc7, 0xbf, 0x4f, - 0xd8, 0xee, 0x3a, 0xca, 0xcc, 0x4d, 0x1c, 0xf5, 0x0c, 0x11, 0x54, 0xaa, - 0x23, 0xc1, 0x39, 0xfb, 0x2a, 0x43, 0xef, 0xe2, 0xfd, 0x28, 0x2c, 0xd4, - 0xda, 0x9e, 0x8b, 0xef, 0xb5, 0xad, 0x2b, 0x0e, 0x68, 0x06, 0x64, 0x3e, - 0xd9, 0xd1, 0x81, 0xd6, 0x27, 0xe0, 0x02, 0x9f, 0x5c, 0x5a, 0xb9, 0xb4, - 0x60, 0xaf, 0x2f, 0x09, 0x08, 0xad, 0x4f, 0x0e, 0xa4, 0xf8, 0x7f, 0xd5, - 0xc4, 0xda, 0xf6, 0xb3, 0x6a, 0xef, 0xca, 0xb9, 0x38, 0xc4, 0xf7, 0xb0, - 0x0b, 0x31, 0xda, 0x7a, 0x26, 0x45, 0xf5, 0xbc, 0x71, 0x4c, 0x1e, 0x1c, - 0x4f, 0x47, 0x0c, 0x55, 0x57, 0x03, 0x4c, 0x00, 0x42, 0xec, 0x1c, 0x3f, - 0x0a, 0x55, 0xf7, 0x2a, 0x56, 0x5f, 0x70, 0x7f, 0x70, 0xa0, 0xdc, 0xb6, - 0x01, 0x4f, 0x07, 0xae, 0xc3, 0x58, 0x58, 0x45, 0xc4, 0x5a, 0xe9, 0xdf, - 0xc8, 0x9d, 0x41, 0xae, 0x08, 0x53, 0x48, 0x12, 0xf3, 0x0b, 0xc9, 0x9b, - 0xd8, 0x2e, 0xb0, 0x56, 0x96, 0x35, 0xc4, 0xf3, 0x9f, 0x14, 0x31, 0x34, - 0x71, 0xd2, 0x81, 0x74, 0xf8, 0x2e, 0xa7, 0x27, 0x4d, 0x0b, 0xdb, 0x26, - 0xf5, 0xf8, 0x57, 0x37, 0x6f, 0xa9, 0x2a, 0x34, 0xc0, 0xa1, 0xeb, 0xd9, - 0xae, 0x4c, 0x24, 0x05, 0x86, 0xdc, 0xb7, 0x1e, 0xe5, 0x07, 0x2e, 0x35, - 0x30, 0xa2, 0x0b, 0xc1, 0xcc, 0x00, 0x14, 0xc3, 0xb2, 0x9e, 0xaa, 0x42, - 0x20, 0x27, 0xfc, 0xe4, 0x6d, 0xd8, 0xe1, 0xb2, 0x2e, 0xb7, 0xce, 0xfe, - 0xa9, 0xf1, 0xc0, 0x44, 0xc7, 0x7f, 0xc3, 0xb5, 0xb1, 0xee, 0xa1, 0x2d, - 0xe6, 0x1d, 0xd8, 0x7d, 0x45, 0x67, 0xb7, 0x17, 0x0f, 0x35, 0x3c, 0xda, - 0xb4, 0x2f, 0x61, 0xba, 0x35, 0x5b, 0xf1, 0x56, 0x3d, 0x66, 0x0d, 0xa8, - 0xef, 0xc5, 0x39, 0xe1, 0xef, 0x38, 0x94, 0x3f, 0xb6, 0x0b, 0x7f, 0xcd, - 0xbb, 0x9d, 0x3c, 0x81, 0xb5, 0xc1, 0x23, 0x2a, 0xe5, 0x1d, 0x52, 0x13, - 0x50, 0xb5, 0xa2, 0xd9, 0xe4, 0x21, 0x9b, 0x37, 0xc7, 0x29, 0x14, 0xff, - 0xa6, 0x7f, 0xc0, 0x31, 0xfb, 0x3b, 0x05, 0xfc, 0x33, 0x53, 0x52, 0xdf, - 0x39, 0xc2, 0xef, 0x01, 0x37, 0xf7, 0x0d, 0xee, 0x4e, 0xf1, 0x3d, 0x81, - 0x35, 0x4b, 0x1b, 0x12, 0x52, 0x13, 0xf0, 0x2c, 0xaa, 0x37, 0x54, 0xa1, - 0x96, 0x46, 0x36, 0xc3, 0x0f, 0x13, 0xad, 0xf0, 0x24, 0xc9, 0x0f, 0x9c, - 0xd8, 0x51, 0xe0, 0xaa, 0x0c, 0xbd, 0xdc, 0x24, 0xc2, 0xa3, 0xd4, 0xc2, - 0x31, 0xf7, 0xd8, 0xb7, 0x2b, 0xe5, 0xfe, 0x13, 0x03, 0x4a, 0xf6, 0x22, - 0x2b, 0x09, 0xf4, 0xb8, 0xc8, 0x14, 0xc6, 0x2d, 0xda, 0xbe, 0xc8, 0x11, - 0x30, 0x00, 0xea, 0x5d, 0x36, 0x14, 0x03, 0xf1, 0x22, 0x37, 0xf7, 0x2e, - 0xda, 0x81, 0x60, 0x30, 0x13, 0x0c, 0xfe, 0x7f, 0x0e, 0x06, 0x28, 0x4b, - 0x3b, 0xfd, 0xde, 0x29, 0x15, 0xda, 0x65, 0x38, 0xc4, 0x27, 0x59, 0x2d, - 0xa0, 0xe6, 0x36, 0x0a, 0xcd, 0x25, 0x32, 0xe1, 0xc5, 0xf5, 0x00, 0xe2, - 0x26, 0xd9, 0x34, 0xcb, 0xda, 0x3a, 0x3f, 0xe7, 0xe5, 0x62, 0x26, 0x8a, - 0xe1, 0x9f, 0x64, 0x57, 0x9f, 0x03, 0x6f, 0x60, 0x38, 0x83, 0xda, 0x49, - 0x6f, 0x47, 0x41, 0xba, 0xfa, 0x2e, 0xc4, 0x48, 0xc8, 0x7f, 0x47, 0xb6, - 0x64, 0xaa, 0x04, 0x2e, 0x20, 0xa5, 0x02, 0x46, 0x6b, 0xee, 0xfb, 0xad, - 0x1d, 0x87, 0xed, 0xfd, 0x20, 0x92, 0xdb, 0xa0, 0xb1, 0x49, 0xef, 0x33, - 0x81, 0x83, 0xd9, 0x38, 0x2b, 0xa3, 0xb2, 0xae, 0x30, 0x84, 0x6e, 0xf8, - 0x02, 0x7a, 0xe0, 0xd6, 0xf5, 0xa3, 0xd0, 0x1e, 0xb6, 0xaa, 0x50, 0xb1, - 0xd4, 0xbe, 0xb9, 0xea, 0x25, 0x1d, 0x21, 0x7f, 0x43, 0x2d, 0xea, 0xb9, - 0x27, 0x19, 0xd0, 0x0f, 0x1c, 0x1b, 0x22, 0x25, 0x0d, 0x12, 0x1c, 0xc5, - 0xe0, 0xe4, 0xce, 0xe4, 0xc3, 0xea, 0x40, 0xbc, 0xca, 0x41, 0x17, 0x2c, - 0xcf, 0xf9, 0x29, 0x2c, 0xdb, 0xd2, 0x9e, 0xdc, 0xc9, 0x43, 0xae, 0xf7, - 0x4e, 0x01, 0x5e, 0x54, 0xc7, 0x2c, 0x00, 0x17, 0xca, 0x92, 0xe5, 0x7f, - 0x51, 0x28, 0xac, 0x9c, 0xf5, 0x19, 0xc6, 0x43, 0x9f, 0x88, 0xdb, 0xaa, - 0x8e, 0xe0, 0xff, 0x1b, 0xa4, 0xc0, 0x91, 0x61, 0xb8, 0x09, 0xf4, 0x2e, - 0xd2, 0x50, 0xcb, 0x7f, 0x94, 0xa6, 0xf9, 0x5c, 0x7c, 0xce, 0x2a, 0x00, - 0x31, 0xfa, 0xe4, 0x8d, 0x21, 0x57, 0x0a, 0x3d, 0x8d, 0x53, 0xbc, 0xd2, - 0x6a, 0x88, 0xbd, 0x0e, 0x5b, 0x3a, 0x4e, 0xb6, 0xe3, 0x01, 0x45, 0xdf, - 0x15, 0x9c, 0x35, 0xbf, 0x84, 0x96, 0xff, 0xff, 0x7e, 0xfe, 0xff, 0xff, - 0x04, 0x00, 0x00, 0x00, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x2a, 0xff, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, 0xc8, 0x00, 0x00, 0x00, - 0xd4, 0x32, 0xf4, 0xbd, 0x6c, 0x4c, 0xf9, 0x4b, 0x1c, 0xb8, 0x97, 0xa1, - 0xfc, 0x5f, 0xba, 0xc8, 0xfb, 0x1c, 0x66, 0xe4, 0xb3, 0x7b, 0xc8, 0xe9, - 0xdd, 0x9d, 0x34, 0xbe, 0xd0, 0x5b, 0xcd, 0x27, 0x74, 0xcf, 0xf2, 0xcf, - 0x0c, 0x53, 0xc9, 0x51, 0x34, 0x52, 0x9d, 0xbd, 0x6e, 0x32, 0x43, 0x55, - 0xdb, 0xdf, 0xca, 0x0c, 0xe6, 0x52, 0xd5, 0xbf, 0xa3, 0xf2, 0x4f, 0x32, - 0xc3, 0x1f, 0xb1, 0xc1, 0xa7, 0xbd, 0xf0, 0xa6, 0x35, 0xcb, 0xde, 0x05, - 0xd4, 0x5f, 0x26, 0xd3, 0xc0, 0x4a, 0xf5, 0x16, 0xcd, 0x24, 0x9e, 0x48, - 0x2b, 0x13, 0x15, 0x54, 0x4b, 0xa8, 0x21, 0xdf, 0xe5, 0xdb, 0x15, 0xf7, - 0xe8, 0x30, 0x0e, 0x4b, 0xc5, 0x16, 0xe3, 0xe0, 0xb0, 0xf4, 0xe7, 0xb1, - 0x20, 0x49, 0x44, 0xcb, 0xe7, 0xe9, 0xd2, 0x03, 0x53, 0x5f, 0x90, 0x18, - 0xaa, 0x5c, 0x35, 0x1a, 0x24, 0xd8, 0x28, 0x40, 0x75, 0xf1, 0xf9, 0xbd, - 0x2f, 0x57, 0xfc, 0xfd, 0x0e, 0xf8, 0xf8, 0x2c, 0x4e, 0xf6, 0xaa, 0x6b, - 0xc5, 0x04, 0xc3, 0xf6, 0xc1, 0xf1, 0x12, 0x2e, 0x06, 0x3e, 0xfa, 0xeb, - 0x03, 0x10, 0x09, 0xc8, 0x0d, 0x1e, 0xf6, 0x70, 0x13, 0x53, 0x09, 0x00, - 0x3f, 0xe2, 0x2e, 0xbc, 0x7f, 0x71, 0x27, 0xa4, 0x10, 0x45, 0x2b, 0x40, - 0x38, 0x39, 0x17, 0x56, 0x99, 0xf1, 0x3e, 0x23, 0xe4, 0x38, 0x4e, 0x2c, - 0xd5, 0xe3, 0xfd, 0xb2, 0xd8, 0xf9, 0x17, 0x18, 0x00, 0x00, 0x06, 0x00, - 0x08, 0x00, 0x04, 0x00, 0x06, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x08, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00, - 0x24, 0x98, 0xff, 0xff, 0x28, 0x98, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, - 0x4d, 0x4c, 0x49, 0x52, 0x20, 0x43, 0x6f, 0x6e, 0x76, 0x65, 0x72, 0x74, - 0x65, 0x64, 0x2e, 0x00, 0x01, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x0e, 0x00, 0x18, 0x00, 0x14, 0x00, 0x10, 0x00, 0x0c, 0x00, - 0x08, 0x00, 0x04, 0x00, 0x0e, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, - 0x1c, 0x00, 0x00, 0x00, 0xf4, 0x03, 0x00, 0x00, 0xf8, 0x03, 0x00, 0x00, - 0xfc, 0x03, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x6d, 0x61, 0x69, 0x6e, - 0x00, 0x00, 0x00, 0x00, 0x0e, 0x00, 0x00, 0x00, 0x8c, 0x03, 0x00, 0x00, - 0x28, 0x03, 0x00, 0x00, 0xd4, 0x02, 0x00, 0x00, 0x8c, 0x02, 0x00, 0x00, - 0x48, 0x02, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0xbc, 0x01, 0x00, 0x00, - 0x74, 0x01, 0x00, 0x00, 0x30, 0x01, 0x00, 0x00, 0xe8, 0x00, 0x00, 0x00, - 0x94, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x1a, 0xfd, 0xff, 0xff, 0x14, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x08, 0x10, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, - 0x05, 0x00, 0x00, 0x00, 0xd0, 0x98, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, - 0x25, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x23, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0xda, 0xff, 0xff, 0xff, - 0x0c, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x21, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, - 0x10, 0x00, 0x0c, 0x00, 0x08, 0x00, 0x04, 0x00, 0x0a, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x20, 0x00, 0x00, 0x00, 0x9e, 0xfd, 0xff, 0xff, 0x24, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x05, 0x34, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, - 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x00, 0x18, 0x00, 0x17, 0x00, - 0x10, 0x00, 0x0c, 0x00, 0x08, 0x00, 0x04, 0x00, 0x0e, 0x00, 0x00, 0x00, - 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, - 0x20, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x00, - 0xee, 0xfd, 0xff, 0xff, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, - 0x20, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0xe0, 0xfd, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, - 0x1d, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0xd2, 0xfd, 0xff, 0xff, - 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x1c, 0x00, 0x00, 0x00, - 0x20, 0x00, 0x00, 0x00, 0xc4, 0xfd, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, - 0x01, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x19, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x00, 0x00, - 0x72, 0xfe, 0xff, 0xff, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, - 0x20, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x64, 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, - 0x19, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, - 0x17, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x56, 0xfe, 0xff, 0xff, - 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x1c, 0x00, 0x00, 0x00, - 0x20, 0x00, 0x00, 0x00, 0x48, 0xfe, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, - 0x01, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x13, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, - 0xf6, 0xfe, 0xff, 0xff, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, - 0x20, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0xe8, 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, - 0x13, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, - 0x11, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0xda, 0xfe, 0xff, 0xff, - 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x1c, 0x00, 0x00, 0x00, - 0x20, 0x00, 0x00, 0x00, 0xcc, 0xfe, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, - 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x0d, 0x00, 0x00, 0x00, 0x0e, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x7a, 0xff, 0xff, 0xff, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, - 0x20, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x6c, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, - 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, - 0x0b, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x5e, 0xff, 0xff, 0xff, - 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x1c, 0x00, 0x00, 0x00, - 0x20, 0x00, 0x00, 0x00, 0x50, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, - 0x01, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x07, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x0e, 0x00, 0x18, 0x00, 0x14, 0x00, 0x10, 0x00, 0x0c, 0x00, - 0x0b, 0x00, 0x04, 0x00, 0x0e, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x01, 0x2c, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x14, 0x00, 0x13, 0x00, 0x0c, 0x00, - 0x08, 0x00, 0x07, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, - 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, - 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x0e, 0x00, 0x14, 0x00, 0x00, 0x00, 0x10, 0x00, 0x0c, 0x00, - 0x0b, 0x00, 0x04, 0x00, 0x0e, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x02, 0x28, 0x00, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x14, 0x00, 0x13, 0x00, 0x0c, 0x00, 0x08, 0x00, 0x04, 0x00, - 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x25, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x26, 0x00, 0x00, 0x00, 0xdc, 0x63, 0x00, 0x00, 0x74, 0x63, 0x00, 0x00, - 0xa0, 0x60, 0x00, 0x00, 0x54, 0x5e, 0x00, 0x00, 0xb8, 0x5d, 0x00, 0x00, - 0x0c, 0x57, 0x00, 0x00, 0x98, 0x50, 0x00, 0x00, 0xa4, 0x4f, 0x00, 0x00, - 0xd4, 0x48, 0x00, 0x00, 0x74, 0x42, 0x00, 0x00, 0xd8, 0x41, 0x00, 0x00, - 0x24, 0x3e, 0x00, 0x00, 0xb0, 0x3a, 0x00, 0x00, 0xa4, 0x39, 0x00, 0x00, - 0xd4, 0x35, 0x00, 0x00, 0x64, 0x32, 0x00, 0x00, 0xc8, 0x31, 0x00, 0x00, - 0x14, 0x2e, 0x00, 0x00, 0xa0, 0x2a, 0x00, 0x00, 0x94, 0x29, 0x00, 0x00, - 0xc4, 0x25, 0x00, 0x00, 0x54, 0x22, 0x00, 0x00, 0xb8, 0x21, 0x00, 0x00, - 0x04, 0x1e, 0x00, 0x00, 0x90, 0x1a, 0x00, 0x00, 0x84, 0x19, 0x00, 0x00, - 0xb4, 0x15, 0x00, 0x00, 0x44, 0x12, 0x00, 0x00, 0xa8, 0x11, 0x00, 0x00, - 0xf4, 0x0a, 0x00, 0x00, 0x80, 0x04, 0x00, 0x00, 0x9c, 0x03, 0x00, 0x00, - 0x00, 0x03, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0xa0, 0x01, 0x00, 0x00, - 0xfc, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0xd2, 0x9c, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x00, - 0x20, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x09, 0x50, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0xff, 0xff, 0xff, 0xff, 0x03, 0x00, 0x00, 0x00, 0xb4, 0x9c, 0xff, 0xff, - 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0xad, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, - 0x57, 0x1f, 0xa5, 0x3d, 0x19, 0x00, 0x00, 0x00, 0x53, 0x74, 0x61, 0x74, - 0x65, 0x66, 0x75, 0x6c, 0x50, 0x61, 0x72, 0x74, 0x69, 0x74, 0x69, 0x6f, - 0x6e, 0x65, 0x64, 0x43, 0x61, 0x6c, 0x6c, 0x3a, 0x30, 0x00, 0x00, 0x00, - 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0xae, 0x9d, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x14, 0x00, 0x00, 0x00, - 0x34, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, - 0x58, 0x00, 0x00, 0x00, 0x1c, 0x9d, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, - 0x14, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x33, 0x0a, 0xc4, 0x38, 0x28, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, - 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x64, 0x65, 0x6e, 0x73, - 0x65, 0x2f, 0x42, 0x69, 0x61, 0x73, 0x41, 0x64, 0x64, 0x2f, 0x52, 0x65, - 0x61, 0x64, 0x56, 0x61, 0x72, 0x69, 0x61, 0x62, 0x6c, 0x65, 0x4f, 0x70, - 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x26, 0x9e, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x14, 0x00, 0x00, 0x00, - 0x30, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, - 0x7c, 0x00, 0x00, 0x00, 0x94, 0x9d, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, - 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xbb, 0x3e, 0x49, 0x3b, - 0x51, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, - 0x61, 0x6e, 0x74, 0x5f, 0x64, 0x65, 0x6e, 0x73, 0x65, 0x2f, 0x4d, 0x61, - 0x74, 0x4d, 0x75, 0x6c, 0x3b, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, - 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x64, 0x65, 0x6e, 0x73, 0x65, 0x2f, 0x4c, - 0x61, 0x73, 0x74, 0x56, 0x61, 0x6c, 0x75, 0x65, 0x51, 0x75, 0x61, 0x6e, - 0x74, 0x2f, 0x46, 0x61, 0x6b, 0x65, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x57, - 0x69, 0x74, 0x68, 0x4d, 0x69, 0x6e, 0x4d, 0x61, 0x78, 0x56, 0x61, 0x72, - 0x73, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x62, 0x9e, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, - 0x18, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, - 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x98, 0x00, 0x00, 0x00, - 0x02, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00, - 0x44, 0x9e, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x94, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0x01, 0x00, 0x00, 0x00, 0xe9, 0x60, 0xf9, 0x3c, 0x63, 0x00, 0x00, 0x00, - 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, - 0x66, 0x6c, 0x61, 0x74, 0x74, 0x65, 0x6e, 0x2f, 0x52, 0x65, 0x73, 0x68, - 0x61, 0x70, 0x65, 0x3b, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, - 0x61, 0x6e, 0x74, 0x5f, 0x61, 0x76, 0x65, 0x72, 0x61, 0x67, 0x65, 0x5f, - 0x70, 0x6f, 0x6f, 0x6c, 0x69, 0x6e, 0x67, 0x32, 0x64, 0x2f, 0x4d, 0x6f, - 0x76, 0x69, 0x6e, 0x67, 0x41, 0x76, 0x67, 0x51, 0x75, 0x61, 0x6e, 0x74, - 0x69, 0x7a, 0x65, 0x2f, 0x46, 0x61, 0x6b, 0x65, 0x51, 0x75, 0x61, 0x6e, - 0x74, 0x57, 0x69, 0x74, 0x68, 0x4d, 0x69, 0x6e, 0x4d, 0x61, 0x78, 0x56, - 0x61, 0x72, 0x73, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x22, 0x9f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, - 0x18, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, - 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x68, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x0c, 0x9f, 0xff, 0xff, - 0x08, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x94, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0xe9, 0x60, 0xf9, 0x3c, 0x26, 0x00, 0x00, 0x00, - 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, - 0x61, 0x76, 0x65, 0x72, 0x61, 0x67, 0x65, 0x5f, 0x70, 0x6f, 0x6f, 0x6c, - 0x69, 0x6e, 0x67, 0x32, 0x64, 0x2f, 0x41, 0x76, 0x67, 0x50, 0x6f, 0x6f, - 0x6c, 0x31, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, - 0xba, 0x9f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x00, - 0x28, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x09, 0x68, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0xff, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0xa4, 0x9f, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, - 0x14, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x92, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x55, 0x64, 0x0b, 0x3d, 0x25, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, - 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x61, 0x76, 0x65, 0x72, - 0x61, 0x67, 0x65, 0x5f, 0x70, 0x6f, 0x6f, 0x6c, 0x69, 0x6e, 0x67, 0x32, - 0x64, 0x2f, 0x41, 0x76, 0x67, 0x50, 0x6f, 0x6f, 0x6c, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x52, 0xa0, 0xff, 0xff, - 0x00, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, - 0x48, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, - 0xb0, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, - 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, - 0x3c, 0xa0, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x92, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x55, 0x64, 0x0b, 0x3d, - 0x6c, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, - 0x61, 0x6e, 0x74, 0x5f, 0x61, 0x63, 0x74, 0x69, 0x76, 0x61, 0x74, 0x69, - 0x6f, 0x6e, 0x5f, 0x34, 0x2f, 0x52, 0x65, 0x6c, 0x75, 0x3b, 0x6d, 0x6f, - 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x62, 0x61, - 0x74, 0x63, 0x68, 0x5f, 0x6e, 0x6f, 0x72, 0x6d, 0x61, 0x6c, 0x69, 0x7a, - 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x5f, 0x34, 0x2f, 0x46, 0x75, 0x73, 0x65, - 0x64, 0x42, 0x61, 0x74, 0x63, 0x68, 0x4e, 0x6f, 0x72, 0x6d, 0x56, 0x33, - 0x3b, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, - 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, 0x5f, 0x34, 0x2f, 0x43, 0x6f, - 0x6e, 0x76, 0x32, 0x44, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x96, 0xa1, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, - 0x14, 0x00, 0x00, 0x00, 0x24, 0x06, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x02, 0x50, 0x06, 0x00, 0x00, 0x04, 0xa1, 0xff, 0xff, - 0x08, 0x00, 0x00, 0x00, 0x08, 0x04, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0xab, 0xb8, 0x6e, 0x39, - 0x48, 0x27, 0x81, 0x39, 0xfe, 0x99, 0x5b, 0x39, 0x1a, 0xc7, 0xb3, 0x39, - 0x11, 0xb1, 0x32, 0x39, 0x76, 0xa1, 0xb1, 0x39, 0x57, 0x7d, 0x8d, 0x39, - 0xe2, 0xe0, 0x65, 0x39, 0x9f, 0xb8, 0x7e, 0x39, 0x86, 0x09, 0x90, 0x39, - 0x4d, 0x2f, 0xc8, 0x39, 0x44, 0xe3, 0x79, 0x39, 0x20, 0x2b, 0xd9, 0x39, - 0xe4, 0x58, 0x93, 0x39, 0xb0, 0x31, 0xa6, 0x39, 0x14, 0x10, 0x56, 0x39, - 0xc1, 0xfd, 0x50, 0x39, 0xd8, 0x07, 0x28, 0x39, 0x24, 0xdf, 0x82, 0x39, - 0x77, 0xd5, 0x5a, 0x39, 0x60, 0x53, 0x90, 0x39, 0xf6, 0x3a, 0xb7, 0x39, - 0x2d, 0xb5, 0x5f, 0x39, 0x08, 0x87, 0xc8, 0x39, 0xa5, 0xdf, 0xa5, 0x39, - 0x5d, 0xe8, 0x96, 0x39, 0x8f, 0xa2, 0x8a, 0x39, 0x47, 0x75, 0xda, 0x39, - 0xb3, 0xc0, 0x39, 0x39, 0xc0, 0x98, 0xd9, 0x39, 0xc3, 0x34, 0x9b, 0x39, - 0x92, 0x77, 0x5c, 0x39, 0xbd, 0xbd, 0xb5, 0x39, 0x99, 0x80, 0x72, 0x39, - 0x0d, 0xd3, 0x4c, 0x39, 0xde, 0x07, 0x69, 0x39, 0xad, 0x43, 0xa0, 0x39, - 0x37, 0x05, 0x5d, 0x39, 0x05, 0x32, 0xac, 0x39, 0xc8, 0xfb, 0x4f, 0x39, - 0xdc, 0x1f, 0x66, 0x39, 0x8a, 0xe4, 0x78, 0x39, 0x57, 0x65, 0x51, 0x39, - 0x70, 0xf8, 0xb1, 0x39, 0x45, 0xd6, 0xb4, 0x39, 0x73, 0xaa, 0xbd, 0x39, - 0xaa, 0x58, 0x73, 0x39, 0x3c, 0x80, 0xa6, 0x39, 0x5a, 0x38, 0x36, 0x39, - 0xef, 0x22, 0x73, 0x39, 0x40, 0x7f, 0x87, 0x39, 0x26, 0x2e, 0x56, 0x39, - 0x2a, 0xa5, 0xa7, 0x39, 0xc4, 0x33, 0x43, 0x39, 0xd1, 0x89, 0x7d, 0x39, - 0xe1, 0xf7, 0x94, 0x39, 0xcc, 0xaf, 0x96, 0x39, 0xb1, 0x38, 0xe0, 0x39, - 0x83, 0xbf, 0xa5, 0x39, 0x99, 0xcc, 0x57, 0x39, 0xe2, 0x0b, 0xce, 0x39, - 0xbc, 0xd6, 0x03, 0x3a, 0xab, 0x35, 0x93, 0x39, 0x9a, 0xaa, 0xa7, 0x39, - 0x1c, 0x81, 0x5f, 0x39, 0x09, 0xc4, 0x74, 0x39, 0x6e, 0x6c, 0x98, 0x39, - 0xc6, 0x41, 0x79, 0x39, 0xb3, 0xdb, 0xae, 0x39, 0x02, 0x40, 0x29, 0x39, - 0xde, 0x5e, 0xc6, 0x39, 0x60, 0x2e, 0xbf, 0x39, 0xc2, 0xe8, 0xba, 0x39, - 0xa3, 0x44, 0x87, 0x39, 0x9e, 0xe6, 0x6b, 0x39, 0x0f, 0x22, 0x39, 0x39, - 0x30, 0xe4, 0x8f, 0x39, 0x63, 0xeb, 0x27, 0x39, 0x19, 0xb7, 0x4b, 0x39, - 0x80, 0x92, 0x39, 0x39, 0xfe, 0x83, 0x3b, 0x39, 0x58, 0xdf, 0xaa, 0x39, - 0x4d, 0x00, 0x40, 0x39, 0x9b, 0xca, 0x76, 0x39, 0xbc, 0x04, 0x60, 0x39, - 0x4b, 0x7f, 0xb7, 0x39, 0x2e, 0x28, 0x63, 0x39, 0x47, 0xdb, 0x8e, 0x39, - 0x33, 0x5f, 0x8c, 0x39, 0x51, 0x1c, 0x89, 0x39, 0x88, 0xb6, 0x78, 0x39, - 0x4e, 0xf1, 0x84, 0x39, 0x31, 0x06, 0xc9, 0x39, 0xe4, 0xdb, 0x8a, 0x39, - 0x06, 0xb6, 0x85, 0x39, 0x42, 0x81, 0xbc, 0x39, 0x5f, 0x7a, 0x36, 0x39, - 0x39, 0x4f, 0x85, 0x39, 0x02, 0x58, 0xea, 0x39, 0x84, 0x04, 0x9a, 0x39, - 0x26, 0xb7, 0xb1, 0x39, 0xc3, 0xfa, 0xac, 0x39, 0x91, 0x83, 0x27, 0x39, - 0xee, 0x45, 0xfd, 0x39, 0x63, 0x41, 0x5d, 0x39, 0x23, 0x05, 0x75, 0x39, - 0x40, 0xa2, 0xc5, 0x39, 0xd7, 0xb2, 0xb1, 0x39, 0xb1, 0x9d, 0x81, 0x39, - 0x9d, 0x74, 0xb6, 0x39, 0x87, 0x31, 0x80, 0x39, 0xc0, 0x34, 0x94, 0x39, - 0xff, 0xaf, 0xde, 0x39, 0xa6, 0x24, 0x43, 0x39, 0x37, 0x85, 0x4f, 0x39, - 0xf3, 0xa2, 0x26, 0x39, 0x94, 0x7e, 0xc0, 0x39, 0x2a, 0x92, 0xc5, 0x39, - 0x84, 0x8a, 0xd2, 0x39, 0x6a, 0xfb, 0xc9, 0x39, 0xb9, 0xe0, 0x4a, 0x39, - 0xbb, 0xc3, 0x8c, 0x39, 0x22, 0x9e, 0x39, 0x39, 0x12, 0x1a, 0x8b, 0x39, - 0xe2, 0xcd, 0xea, 0x39, 0x97, 0xb2, 0x53, 0x39, 0x7b, 0x82, 0xbc, 0x39, - 0xd1, 0x57, 0x8a, 0x39, 0x32, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, - 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x62, 0x61, 0x74, 0x63, - 0x68, 0x5f, 0x6e, 0x6f, 0x72, 0x6d, 0x61, 0x6c, 0x69, 0x7a, 0x61, 0x74, - 0x69, 0x6f, 0x6e, 0x5f, 0x34, 0x2f, 0x46, 0x75, 0x73, 0x65, 0x64, 0x42, - 0x61, 0x74, 0x63, 0x68, 0x4e, 0x6f, 0x72, 0x6d, 0x56, 0x33, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x06, 0xa8, 0xff, 0xff, - 0x00, 0x00, 0x00, 0x01, 0x14, 0x00, 0x00, 0x00, 0x28, 0x06, 0x00, 0x00, - 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x84, 0x06, 0x00, 0x00, - 0x74, 0xa7, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, 0x0c, 0x04, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x55, 0x21, 0x0a, 0x3c, 0x80, 0x76, 0x15, 0x3c, - 0x4c, 0x22, 0xfe, 0x3b, 0x41, 0x0c, 0x50, 0x3c, 0x80, 0xca, 0xce, 0x3b, - 0x2f, 0x90, 0x4d, 0x3c, 0x29, 0xbd, 0x23, 0x3c, 0x72, 0x03, 0x05, 0x3c, - 0x5a, 0x63, 0x13, 0x3c, 0xe6, 0xaf, 0x26, 0x3c, 0xf6, 0xa9, 0x67, 0x3c, - 0x63, 0x97, 0x10, 0x3c, 0x7b, 0x51, 0x7b, 0x3c, 0x85, 0x84, 0x2a, 0x3c, - 0x04, 0x54, 0x40, 0x3c, 0x6a, 0xb9, 0xf7, 0x3b, 0xed, 0xda, 0xf1, 0x3b, - 0x1b, 0x74, 0xc2, 0x3b, 0x87, 0x73, 0x17, 0x3c, 0xdd, 0x3e, 0xfd, 0x3b, - 0x5d, 0x05, 0x27, 0x3c, 0x1a, 0x0b, 0x54, 0x3c, 0x64, 0x71, 0x01, 0x3c, - 0x7c, 0x0f, 0x68, 0x3c, 0x12, 0xf5, 0x3f, 0x3c, 0x51, 0xa3, 0x2e, 0x3c, - 0x77, 0x6f, 0x20, 0x3c, 0x8d, 0xcf, 0x7c, 0x3c, 0x62, 0xf6, 0xd6, 0x3b, - 0x59, 0xd0, 0x7b, 0x3c, 0xc2, 0x9c, 0x33, 0x3c, 0xb8, 0x22, 0xff, 0x3b, - 0xee, 0x51, 0x52, 0x3c, 0x66, 0x51, 0x0c, 0x3c, 0x7c, 0x08, 0xed, 0x3b, - 0x63, 0xd6, 0x06, 0x3c, 0x4c, 0x77, 0x39, 0x3c, 0xa3, 0xc6, 0xff, 0x3b, - 0xf0, 0x45, 0x47, 0x3c, 0x64, 0xb0, 0xf0, 0x3b, 0xe3, 0x27, 0x05, 0x3c, - 0xff, 0x03, 0x10, 0x3c, 0xce, 0x52, 0xf2, 0x3b, 0xd6, 0xf4, 0x4d, 0x3c, - 0x10, 0x46, 0x51, 0x3c, 0xa8, 0x7d, 0x5b, 0x3c, 0x6c, 0xce, 0x0c, 0x3c, - 0xea, 0xae, 0x40, 0x3c, 0xd3, 0xdf, 0xd2, 0x3b, 0x55, 0xaf, 0x0c, 0x3c, - 0xd6, 0xcd, 0x1c, 0x3c, 0x37, 0xdc, 0xf7, 0x3b, 0xe9, 0x01, 0x42, 0x3c, - 0xd9, 0xe5, 0xe1, 0x3b, 0x24, 0xb4, 0x12, 0x3c, 0xc3, 0x64, 0x2c, 0x3c, - 0xdc, 0x61, 0x2e, 0x3c, 0x7d, 0xbd, 0x81, 0x3c, 0xe2, 0xcf, 0x3f, 0x3c, - 0xd6, 0xbb, 0xf9, 0x3b, 0x82, 0x72, 0x6e, 0x3c, 0x0d, 0x92, 0x98, 0x3c, - 0xc1, 0x5b, 0x2a, 0x3c, 0x33, 0x08, 0x42, 0x3c, 0x43, 0x53, 0x01, 0x3c, - 0xad, 0xa0, 0x0d, 0x3c, 0x69, 0x64, 0x30, 0x3c, 0xf2, 0x39, 0x10, 0x3c, - 0xcf, 0x5a, 0x4a, 0x3c, 0x5c, 0xdd, 0xc3, 0x3b, 0x7f, 0x90, 0x65, 0x3c, - 0x96, 0x3e, 0x5d, 0x3c, 0xff, 0x4c, 0x58, 0x3c, 0x02, 0x8a, 0x1c, 0x3c, - 0x89, 0x7f, 0x08, 0x3c, 0xcc, 0x3e, 0xd6, 0x3b, 0xb1, 0x84, 0x26, 0x3c, - 0x2c, 0x53, 0xc2, 0x3b, 0xe2, 0xbf, 0xeb, 0x3b, 0xeb, 0xc0, 0xd6, 0x3b, - 0xa4, 0x00, 0xd9, 0x3b, 0x01, 0xbe, 0x45, 0x3c, 0x85, 0x31, 0xde, 0x3b, - 0xbc, 0xcc, 0x0e, 0x3c, 0x6c, 0x9f, 0x01, 0x3c, 0x2e, 0x5a, 0x54, 0x3c, - 0x51, 0x70, 0x03, 0x3c, 0x21, 0x52, 0x25, 0x3c, 0x07, 0x72, 0x22, 0x3c, - 0xdb, 0xab, 0x1e, 0x3c, 0x60, 0xe9, 0x0f, 0x3c, 0x0f, 0xd9, 0x19, 0x3c, - 0xa4, 0xa2, 0x68, 0x3c, 0xd0, 0xb1, 0x20, 0x3c, 0xb6, 0xbc, 0x1a, 0x3c, - 0xbc, 0x25, 0x5a, 0x3c, 0x3a, 0x2c, 0xd3, 0x3b, 0xbe, 0x45, 0x1a, 0x3c, - 0xe3, 0x98, 0x87, 0x3c, 0xab, 0x3c, 0x32, 0x3c, 0x48, 0xa9, 0x4d, 0x3c, - 0x3f, 0x2e, 0x48, 0x3c, 0x06, 0xdb, 0xc1, 0x3b, 0xdd, 0x8c, 0x92, 0x3c, - 0x22, 0x06, 0x00, 0x3c, 0x58, 0xc6, 0x0d, 0x3c, 0x37, 0xb6, 0x64, 0x3c, - 0x4b, 0xa4, 0x4d, 0x3c, 0x87, 0xff, 0x15, 0x3c, 0x90, 0x25, 0x53, 0x3c, - 0x19, 0x5a, 0x14, 0x3c, 0xf3, 0x82, 0x2b, 0x3c, 0x44, 0xda, 0x80, 0x3c, - 0x5a, 0xd4, 0xe1, 0x3b, 0x2d, 0x27, 0xf0, 0x3b, 0x17, 0xd7, 0xc0, 0x3b, - 0xa7, 0xc3, 0x5e, 0x3c, 0x9a, 0xa3, 0x64, 0x3c, 0x14, 0xa6, 0x73, 0x3c, - 0x6d, 0xbe, 0x69, 0x3c, 0xcb, 0xc7, 0xea, 0x3b, 0x5d, 0xe6, 0x22, 0x3c, - 0x61, 0xce, 0xd6, 0x3b, 0xc5, 0xf9, 0x20, 0x3c, 0x18, 0xdd, 0x87, 0x3c, - 0xb6, 0xfc, 0xf4, 0x3b, 0x26, 0x27, 0x5a, 0x3c, 0xf8, 0x18, 0x20, 0x3c, - 0x61, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, - 0x61, 0x6e, 0x74, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, 0x5f, 0x34, - 0x2f, 0x43, 0x6f, 0x6e, 0x76, 0x32, 0x44, 0x3b, 0x6d, 0x6f, 0x64, 0x65, - 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x63, 0x6f, 0x6e, 0x76, - 0x32, 0x64, 0x5f, 0x34, 0x2f, 0x4c, 0x61, 0x73, 0x74, 0x56, 0x61, 0x6c, - 0x75, 0x65, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x2f, 0x46, 0x61, 0x6b, 0x65, - 0x51, 0x75, 0x61, 0x6e, 0x74, 0x57, 0x69, 0x74, 0x68, 0x4d, 0x69, 0x6e, - 0x4d, 0x61, 0x78, 0x56, 0x61, 0x72, 0x73, 0x50, 0x65, 0x72, 0x43, 0x68, - 0x61, 0x6e, 0x6e, 0x65, 0x6c, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x40, 0x00, 0x00, 0x00, 0x52, 0xae, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, - 0x18, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, - 0x1d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x68, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0x05, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x3c, 0xae, 0xff, 0xff, - 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0xc9, 0x36, 0xdd, 0x3c, 0x29, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, - 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x64, 0x65, 0x70, 0x74, - 0x68, 0x77, 0x69, 0x73, 0x65, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, - 0x5f, 0x34, 0x2f, 0x64, 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, 0x65, - 0x33, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, - 0x4e, 0xaf, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x14, 0x00, 0x00, 0x00, - 0x28, 0x03, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, - 0x4c, 0x03, 0x00, 0x00, 0xbc, 0xae, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, - 0x0c, 0x02, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, - 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, - 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, - 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, - 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, - 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, - 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, - 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, - 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, - 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, - 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, - 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, - 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, - 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, - 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, - 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, - 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, - 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, - 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, - 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, - 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, - 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, 0x92, 0x24, 0x48, 0x38, - 0x92, 0x24, 0x48, 0x38, 0x29, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, - 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x64, 0x65, 0x70, 0x74, - 0x68, 0x77, 0x69, 0x73, 0x65, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, - 0x5f, 0x34, 0x2f, 0x64, 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, 0x65, - 0x32, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, - 0xba, 0xb2, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x14, 0x00, 0x00, 0x00, - 0x2c, 0x03, 0x00, 0x00, 0x1b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, - 0xa0, 0x03, 0x00, 0x00, 0x72, 0xb5, 0xff, 0xff, 0x03, 0x00, 0x00, 0x00, - 0x08, 0x00, 0x00, 0x00, 0x0c, 0x02, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x40, 0x00, 0x00, 0x00, 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, - 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, - 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, - 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, - 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, - 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, - 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, - 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, - 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, - 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, - 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, - 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, - 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, - 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, - 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, - 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, - 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, - 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, - 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, - 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, - 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, - 0xab, 0xc0, 0xed, 0x3a, 0xab, 0xc0, 0xed, 0x3a, 0x78, 0x00, 0x00, 0x00, - 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, - 0x64, 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, 0x65, 0x5f, 0x63, 0x6f, - 0x6e, 0x76, 0x32, 0x64, 0x5f, 0x34, 0x2f, 0x64, 0x65, 0x70, 0x74, 0x68, - 0x77, 0x69, 0x73, 0x65, 0x3b, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, - 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x64, 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, - 0x73, 0x65, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, 0x5f, 0x34, 0x2f, - 0x4c, 0x61, 0x73, 0x74, 0x56, 0x61, 0x6c, 0x75, 0x65, 0x51, 0x75, 0x61, - 0x6e, 0x74, 0x2f, 0x46, 0x61, 0x6b, 0x65, 0x51, 0x75, 0x61, 0x6e, 0x74, - 0x57, 0x69, 0x74, 0x68, 0x4d, 0x69, 0x6e, 0x4d, 0x61, 0x78, 0x56, 0x61, - 0x72, 0x73, 0x50, 0x65, 0x72, 0x43, 0x68, 0x61, 0x6e, 0x6e, 0x65, 0x6c, - 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x0f, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, - 0x22, 0xb6, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x00, - 0x28, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x09, 0xd8, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0xff, 0xff, 0xff, 0xff, 0x13, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x40, 0x00, 0x00, 0x00, 0x0c, 0xb6, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, - 0x14, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x97, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0xf3, 0x80, 0xd7, 0x3c, 0x95, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, - 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x61, 0x63, 0x74, 0x69, - 0x76, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x5f, 0x33, 0x2f, 0x52, 0x65, 0x6c, - 0x75, 0x3b, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, - 0x74, 0x5f, 0x62, 0x61, 0x74, 0x63, 0x68, 0x5f, 0x6e, 0x6f, 0x72, 0x6d, - 0x61, 0x6c, 0x69, 0x7a, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x5f, 0x33, 0x2f, - 0x46, 0x75, 0x73, 0x65, 0x64, 0x42, 0x61, 0x74, 0x63, 0x68, 0x4e, 0x6f, - 0x72, 0x6d, 0x56, 0x33, 0x3b, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, - 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x64, 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, - 0x73, 0x65, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, 0x5f, 0x34, 0x2f, - 0x64, 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, 0x65, 0x3b, 0x6d, 0x6f, - 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x63, 0x6f, - 0x6e, 0x76, 0x32, 0x64, 0x5f, 0x33, 0x2f, 0x43, 0x6f, 0x6e, 0x76, 0x32, - 0x44, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x13, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, - 0x8e, 0xb7, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x14, 0x00, 0x00, 0x00, - 0x24, 0x03, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, - 0x50, 0x03, 0x00, 0x00, 0xfc, 0xb6, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, - 0x08, 0x02, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0xcb, 0x45, 0x3d, 0x39, - 0x0c, 0x02, 0x2a, 0x39, 0x3b, 0xf6, 0x2a, 0x39, 0xb6, 0x32, 0xee, 0x38, - 0xa2, 0x16, 0x72, 0x39, 0xee, 0xcf, 0x1d, 0x39, 0x0d, 0x51, 0x08, 0x39, - 0x7a, 0x5a, 0x17, 0x39, 0x71, 0xd4, 0x30, 0x39, 0x4f, 0x75, 0x54, 0x39, - 0x95, 0xae, 0x50, 0x39, 0x8e, 0x55, 0x0a, 0x39, 0x40, 0x14, 0x3f, 0x39, - 0xd3, 0x38, 0x39, 0x39, 0x77, 0xd2, 0x25, 0x39, 0xbc, 0x1f, 0xb5, 0x38, - 0x83, 0x57, 0x81, 0x39, 0xab, 0x6d, 0x30, 0x39, 0xe0, 0x53, 0x30, 0x39, - 0x3b, 0x3b, 0x4f, 0x39, 0xca, 0x35, 0x34, 0x39, 0x0a, 0x49, 0x7b, 0x39, - 0x72, 0xf9, 0x39, 0x39, 0x57, 0xeb, 0x5b, 0x39, 0x3a, 0x56, 0xf8, 0x38, - 0x15, 0x2b, 0x0f, 0x39, 0x14, 0xfa, 0xb2, 0x39, 0x92, 0x4c, 0x1e, 0x39, - 0x87, 0x4c, 0x2e, 0x39, 0x51, 0xcf, 0x2b, 0x39, 0x06, 0x2d, 0x51, 0x39, - 0xdb, 0xd2, 0x15, 0x39, 0x26, 0xa2, 0x5c, 0x39, 0x6f, 0x8f, 0x07, 0x39, - 0x04, 0x31, 0x50, 0x39, 0xcc, 0x78, 0x47, 0x39, 0xee, 0x86, 0x29, 0x39, - 0xe9, 0x03, 0x2f, 0x39, 0x7e, 0xc4, 0x24, 0x39, 0xfd, 0xbf, 0x25, 0x39, - 0x75, 0x12, 0x38, 0x39, 0xe1, 0xad, 0x31, 0x39, 0xc0, 0xcd, 0x2b, 0x39, - 0x44, 0x3f, 0x3f, 0x39, 0x60, 0xbf, 0x0b, 0x39, 0xbf, 0xe8, 0x0e, 0x39, - 0x39, 0x44, 0x79, 0x39, 0x9d, 0x5a, 0x0b, 0x39, 0x5b, 0xe1, 0x2f, 0x39, - 0x17, 0x8d, 0x10, 0x39, 0xb3, 0x9b, 0x2c, 0x39, 0xfe, 0xd5, 0x28, 0x39, - 0xda, 0x21, 0x2b, 0x39, 0x2b, 0xb7, 0xe1, 0x38, 0xa5, 0x0a, 0xc9, 0x38, - 0x69, 0x67, 0x14, 0x39, 0xba, 0x6d, 0x9c, 0x39, 0x21, 0x71, 0x21, 0x39, - 0xa7, 0x0d, 0x0b, 0x39, 0xbe, 0x89, 0x39, 0x39, 0xa4, 0xfe, 0x51, 0x39, - 0x9b, 0xcf, 0x04, 0x39, 0x46, 0x3b, 0x0c, 0x39, 0x26, 0x1c, 0x38, 0x39, - 0x32, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, - 0x61, 0x6e, 0x74, 0x5f, 0x62, 0x61, 0x74, 0x63, 0x68, 0x5f, 0x6e, 0x6f, - 0x72, 0x6d, 0x61, 0x6c, 0x69, 0x7a, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x5f, - 0x33, 0x2f, 0x46, 0x75, 0x73, 0x65, 0x64, 0x42, 0x61, 0x74, 0x63, 0x68, - 0x4e, 0x6f, 0x72, 0x6d, 0x56, 0x33, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x40, 0x00, 0x00, 0x00, 0xfe, 0xba, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, - 0x14, 0x00, 0x00, 0x00, 0x28, 0x03, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x09, 0x84, 0x03, 0x00, 0x00, 0x6c, 0xba, 0xff, 0xff, - 0x08, 0x00, 0x00, 0x00, 0x0c, 0x02, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x40, 0x00, 0x00, 0x00, 0xe0, 0x53, 0xed, 0x3b, 0xfe, 0x2b, 0xd5, 0x3b, - 0x2c, 0x5e, 0xd6, 0x3b, 0x64, 0x56, 0x95, 0x3b, 0xc8, 0xc6, 0x17, 0x3c, - 0x31, 0xe1, 0xc5, 0x3b, 0x2c, 0xed, 0xaa, 0x3b, 0xf0, 0xc7, 0xbd, 0x3b, - 0xc9, 0xb9, 0xdd, 0x3b, 0x30, 0x33, 0x05, 0x3c, 0x1b, 0xd5, 0x02, 0x3c, - 0xcf, 0x74, 0xad, 0x3b, 0xbf, 0x97, 0xef, 0x3b, 0xa1, 0x3f, 0xe8, 0x3b, - 0x57, 0xec, 0xcf, 0x3b, 0x2e, 0x1c, 0x63, 0x3b, 0x4b, 0x2e, 0x22, 0x3c, - 0xeb, 0x38, 0xdd, 0x3b, 0x93, 0x18, 0xdd, 0x3b, 0x49, 0xec, 0x01, 0x3c, - 0xd7, 0xf6, 0xe1, 0x3b, 0xde, 0x8a, 0x1d, 0x3c, 0x27, 0x31, 0xe9, 0x3b, - 0xad, 0xe0, 0x09, 0x3c, 0xa4, 0xb1, 0x9b, 0x3b, 0x89, 0x84, 0xb3, 0x3b, - 0xf9, 0x6a, 0x60, 0x3c, 0x7a, 0x7d, 0xc6, 0x3b, 0x5f, 0x8d, 0xda, 0x3b, - 0x61, 0x6e, 0xd7, 0x3b, 0x60, 0x24, 0x03, 0x3c, 0xe3, 0xdc, 0xbb, 0x3b, - 0x4a, 0x53, 0x0a, 0x3c, 0x65, 0xfa, 0xa9, 0x3b, 0x61, 0x86, 0x02, 0x3c, - 0xcb, 0x1d, 0xfa, 0x3b, 0x9e, 0x91, 0xd4, 0x3b, 0x50, 0x73, 0xdb, 0x3b, - 0xd4, 0x99, 0xce, 0x3b, 0x2e, 0xd5, 0xcf, 0x3b, 0x86, 0xce, 0xe6, 0x3b, - 0x6e, 0xca, 0xde, 0x3b, 0x6a, 0x6c, 0xd7, 0x3b, 0xaf, 0xcd, 0xef, 0x3b, - 0x7f, 0x3a, 0xaf, 0x3b, 0x5c, 0x31, 0xb3, 0x3b, 0xda, 0x46, 0x1c, 0x3c, - 0x26, 0xbc, 0xae, 0x3b, 0xfb, 0x88, 0xdc, 0x3b, 0x6c, 0x40, 0xb5, 0x3b, - 0xa7, 0x6e, 0xd8, 0x3b, 0xc2, 0xb3, 0xd3, 0x3b, 0xde, 0x94, 0xd6, 0x3b, - 0xf5, 0x82, 0x8d, 0x3b, 0xab, 0x15, 0x7c, 0x3b, 0x2b, 0x15, 0xba, 0x3b, - 0x10, 0x25, 0x44, 0x3c, 0x50, 0x6e, 0xca, 0x3b, 0xa7, 0x5b, 0xae, 0x3b, - 0x17, 0xa5, 0xe8, 0x3b, 0xcb, 0xa7, 0x03, 0x3c, 0xdf, 0x87, 0xa6, 0x3b, - 0xd9, 0xd5, 0xaf, 0x3b, 0xad, 0xda, 0xe6, 0x3b, 0x61, 0x00, 0x00, 0x00, - 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, - 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, 0x5f, 0x33, 0x2f, 0x43, 0x6f, 0x6e, - 0x76, 0x32, 0x44, 0x3b, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, - 0x61, 0x6e, 0x74, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, 0x5f, 0x33, - 0x2f, 0x4c, 0x61, 0x73, 0x74, 0x56, 0x61, 0x6c, 0x75, 0x65, 0x51, 0x75, - 0x61, 0x6e, 0x74, 0x2f, 0x46, 0x61, 0x6b, 0x65, 0x51, 0x75, 0x61, 0x6e, - 0x74, 0x57, 0x69, 0x74, 0x68, 0x4d, 0x69, 0x6e, 0x4d, 0x61, 0x78, 0x56, - 0x61, 0x72, 0x73, 0x50, 0x65, 0x72, 0x43, 0x68, 0x61, 0x6e, 0x6e, 0x65, - 0x6c, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, - 0x4a, 0xbe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x00, - 0x28, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x09, 0x68, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0xff, 0xff, 0xff, 0xff, 0x13, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x40, 0x00, 0x00, 0x00, 0x34, 0xbe, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, - 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x05, 0x2a, 0xcc, 0x3c, - 0x28, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, - 0x61, 0x6e, 0x74, 0x5f, 0x64, 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, - 0x65, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, 0x5f, 0x33, 0x2f, 0x64, - 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, 0x65, 0x00, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x46, 0xbf, 0xff, 0xff, - 0x00, 0x00, 0x00, 0x01, 0x14, 0x00, 0x00, 0x00, 0x28, 0x03, 0x00, 0x00, - 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x4c, 0x03, 0x00, 0x00, - 0xb4, 0xbe, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, 0x0c, 0x02, 0x00, 0x00, - 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x8d, 0xd6, 0x0d, 0x38, - 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, - 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, - 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, - 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, - 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, - 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, - 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, - 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, - 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, - 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, - 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, - 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, - 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, - 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, - 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, - 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, - 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, - 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, - 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, - 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, - 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, 0x8d, 0xd6, 0x0d, 0x38, - 0x29, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, - 0x61, 0x6e, 0x74, 0x5f, 0x64, 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, - 0x65, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, 0x5f, 0x34, 0x2f, 0x64, - 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, 0x65, 0x31, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0xb2, 0xc2, 0xff, 0xff, - 0x00, 0x00, 0x00, 0x01, 0x14, 0x00, 0x00, 0x00, 0x2c, 0x03, 0x00, 0x00, - 0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0xa0, 0x03, 0x00, 0x00, - 0x6a, 0xc5, 0xff, 0xff, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, - 0x0c, 0x02, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, - 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, - 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, - 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, - 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, - 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, - 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, - 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, - 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, - 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, - 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, - 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, - 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, - 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, - 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, - 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, - 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, - 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, - 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, - 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, - 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, - 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, 0xfb, 0xb6, 0xb4, 0x3a, - 0xfb, 0xb6, 0xb4, 0x3a, 0x78, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, - 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x64, 0x65, 0x70, 0x74, - 0x68, 0x77, 0x69, 0x73, 0x65, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, - 0x5f, 0x33, 0x2f, 0x64, 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, 0x65, - 0x3b, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, - 0x5f, 0x64, 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, 0x65, 0x5f, 0x63, - 0x6f, 0x6e, 0x76, 0x32, 0x64, 0x5f, 0x33, 0x2f, 0x4c, 0x61, 0x73, 0x74, - 0x56, 0x61, 0x6c, 0x75, 0x65, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x2f, 0x46, - 0x61, 0x6b, 0x65, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x57, 0x69, 0x74, 0x68, - 0x4d, 0x69, 0x6e, 0x4d, 0x61, 0x78, 0x56, 0x61, 0x72, 0x73, 0x50, 0x65, - 0x72, 0x43, 0x68, 0x61, 0x6e, 0x6e, 0x65, 0x6c, 0x00, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x1a, 0xc6, 0xff, 0xff, - 0x00, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, - 0x48, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, - 0xd8, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, - 0x1f, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, - 0x04, 0xc6, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x98, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x6b, 0xed, 0xc8, 0x3c, - 0x95, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, - 0x61, 0x6e, 0x74, 0x5f, 0x61, 0x63, 0x74, 0x69, 0x76, 0x61, 0x74, 0x69, - 0x6f, 0x6e, 0x5f, 0x32, 0x2f, 0x52, 0x65, 0x6c, 0x75, 0x3b, 0x6d, 0x6f, - 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x62, 0x61, - 0x74, 0x63, 0x68, 0x5f, 0x6e, 0x6f, 0x72, 0x6d, 0x61, 0x6c, 0x69, 0x7a, - 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x5f, 0x32, 0x2f, 0x46, 0x75, 0x73, 0x65, - 0x64, 0x42, 0x61, 0x74, 0x63, 0x68, 0x4e, 0x6f, 0x72, 0x6d, 0x56, 0x33, - 0x3b, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, - 0x5f, 0x64, 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, 0x65, 0x5f, 0x63, - 0x6f, 0x6e, 0x76, 0x32, 0x64, 0x5f, 0x34, 0x2f, 0x64, 0x65, 0x70, 0x74, - 0x68, 0x77, 0x69, 0x73, 0x65, 0x3b, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, - 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, - 0x5f, 0x32, 0x2f, 0x43, 0x6f, 0x6e, 0x76, 0x32, 0x44, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x86, 0xc7, 0xff, 0xff, - 0x00, 0x00, 0x00, 0x01, 0x14, 0x00, 0x00, 0x00, 0x24, 0x03, 0x00, 0x00, - 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x50, 0x03, 0x00, 0x00, - 0xf4, 0xc6, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, 0x08, 0x02, 0x00, 0x00, - 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x40, 0x00, 0x00, 0x00, 0x1a, 0x2a, 0x04, 0x39, 0x44, 0x18, 0x1a, 0x39, - 0x24, 0x37, 0xff, 0x38, 0xa9, 0x73, 0x45, 0x39, 0xe3, 0xf9, 0x4a, 0x39, - 0x8e, 0x3b, 0xea, 0x38, 0x24, 0x14, 0xfd, 0x38, 0xd0, 0x17, 0xfd, 0x38, - 0x7c, 0x47, 0x4d, 0x39, 0x52, 0xc4, 0x8b, 0x39, 0xd1, 0xe9, 0xcf, 0x38, - 0xcf, 0x4a, 0x0d, 0x39, 0xdb, 0x1c, 0x84, 0x39, 0xda, 0xe4, 0x2b, 0x39, - 0x83, 0x6a, 0x25, 0x39, 0x3c, 0x94, 0x59, 0x39, 0x9f, 0xef, 0xfb, 0x38, - 0x9d, 0xe4, 0xf8, 0x38, 0xc3, 0x06, 0x4a, 0x39, 0x59, 0x7f, 0x63, 0x39, - 0x02, 0x58, 0x8f, 0x39, 0x38, 0xe2, 0xca, 0x38, 0x28, 0x31, 0x24, 0x39, - 0x05, 0x09, 0xed, 0x38, 0x39, 0x53, 0x46, 0x39, 0x1e, 0x5b, 0x19, 0x39, - 0x2f, 0x40, 0x2d, 0x39, 0x89, 0x97, 0x3d, 0x39, 0x55, 0x58, 0x42, 0x39, - 0x4e, 0xab, 0x41, 0x39, 0xf7, 0x90, 0x0c, 0x39, 0x84, 0x1b, 0x36, 0x39, - 0x02, 0x44, 0xfd, 0x38, 0xa1, 0x9d, 0x57, 0x39, 0x83, 0xf8, 0x3a, 0x39, - 0xbb, 0xd5, 0x41, 0x39, 0x8f, 0x03, 0x32, 0x39, 0x7d, 0x96, 0x53, 0x39, - 0x94, 0x26, 0x62, 0x39, 0x70, 0x05, 0x34, 0x39, 0xa4, 0x2a, 0x67, 0x39, - 0x6f, 0xfb, 0x34, 0x39, 0xdb, 0xf8, 0x3c, 0x39, 0xa3, 0xbe, 0x5b, 0x39, - 0x26, 0x1a, 0xe5, 0x38, 0xe7, 0x4c, 0x14, 0x39, 0x44, 0x5f, 0x09, 0x39, - 0xda, 0x9d, 0x19, 0x39, 0x5e, 0x73, 0x0e, 0x39, 0xc7, 0xc2, 0x55, 0x39, - 0x5b, 0x41, 0xb9, 0x38, 0x8f, 0x1a, 0x75, 0x39, 0x12, 0x26, 0x3b, 0x39, - 0x96, 0x5a, 0x89, 0x39, 0x2c, 0x26, 0x52, 0x39, 0xba, 0x1e, 0xb4, 0x38, - 0x04, 0x01, 0x18, 0x39, 0x6a, 0x48, 0xa8, 0x39, 0x36, 0x89, 0x09, 0x39, - 0xb8, 0x5c, 0x1c, 0x39, 0x46, 0xce, 0x7a, 0x39, 0x69, 0x03, 0x5c, 0x39, - 0xa5, 0x6b, 0x64, 0x39, 0xf2, 0x89, 0x50, 0x39, 0x32, 0x00, 0x00, 0x00, - 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, - 0x62, 0x61, 0x74, 0x63, 0x68, 0x5f, 0x6e, 0x6f, 0x72, 0x6d, 0x61, 0x6c, - 0x69, 0x7a, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x5f, 0x32, 0x2f, 0x46, 0x75, - 0x73, 0x65, 0x64, 0x42, 0x61, 0x74, 0x63, 0x68, 0x4e, 0x6f, 0x72, 0x6d, - 0x56, 0x33, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, - 0xf6, 0xca, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x14, 0x00, 0x00, 0x00, - 0x28, 0x03, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, - 0x84, 0x03, 0x00, 0x00, 0x64, 0xca, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, - 0x0c, 0x02, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, - 0x76, 0x88, 0xbb, 0x3b, 0x9c, 0xa6, 0xda, 0x3b, 0x3b, 0x11, 0xb5, 0x3b, - 0xfa, 0x15, 0x0c, 0x3c, 0x54, 0x01, 0x10, 0x3c, 0x42, 0x2e, 0xa6, 0x3b, - 0x27, 0x8d, 0xb3, 0x3b, 0xc2, 0x8f, 0xb3, 0x3b, 0xa0, 0xa3, 0x11, 0x3c, - 0x07, 0x52, 0x46, 0x3c, 0x0b, 0x82, 0x93, 0x3b, 0x1b, 0x7c, 0xc8, 0x3b, - 0xab, 0x75, 0x3b, 0x3c, 0x1e, 0xe8, 0xf3, 0x3b, 0x0a, 0xb7, 0xea, 0x3b, - 0x91, 0x5d, 0x1a, 0x3c, 0x9e, 0xbd, 0xb2, 0x3b, 0xf0, 0x94, 0xb0, 0x3b, - 0xd6, 0x54, 0x0f, 0x3c, 0xfd, 0x66, 0x21, 0x3c, 0x55, 0x65, 0x4b, 0x3c, - 0x89, 0xf0, 0x8f, 0x3b, 0x68, 0xfa, 0xe8, 0x3b, 0x47, 0x2b, 0xa8, 0x3b, - 0x96, 0xb4, 0x0c, 0x3c, 0x39, 0x9a, 0xd9, 0x3b, 0xf6, 0xd4, 0xf5, 0x3b, - 0x70, 0x82, 0x06, 0x3c, 0xb7, 0xe1, 0x09, 0x3c, 0xf5, 0x66, 0x09, 0x3c, - 0x68, 0x74, 0xc7, 0x3b, 0x15, 0x33, 0x01, 0x3c, 0x1c, 0xaf, 0xb3, 0x3b, - 0xfc, 0xf8, 0x18, 0x3c, 0x5e, 0xa6, 0x04, 0x3c, 0x0f, 0x85, 0x09, 0x3c, - 0x2d, 0x97, 0xfc, 0x3b, 0x6c, 0x1d, 0x16, 0x3c, 0x62, 0x72, 0x20, 0x3c, - 0x57, 0x70, 0xff, 0x3b, 0x63, 0x01, 0x24, 0x3c, 0xb2, 0x66, 0x00, 0x3c, - 0xdc, 0x11, 0x06, 0x3c, 0xe6, 0xe6, 0x1b, 0x3c, 0x70, 0x8a, 0xa2, 0x3b, - 0xd0, 0x6d, 0xd2, 0x3b, 0x23, 0xec, 0xc2, 0x3b, 0xe9, 0xf8, 0xd9, 0x3b, - 0xe7, 0x20, 0xca, 0x3b, 0x18, 0xa8, 0x17, 0x3c, 0xcd, 0x6e, 0x83, 0x3b, - 0xb6, 0xe4, 0x2d, 0x3c, 0xb1, 0xc6, 0x04, 0x3c, 0x80, 0xe5, 0x42, 0x3c, - 0x1d, 0x18, 0x15, 0x3c, 0x39, 0x94, 0x7f, 0x3b, 0x20, 0xaf, 0xd7, 0x3b, - 0x67, 0xc8, 0x6e, 0x3c, 0xa8, 0x27, 0xc3, 0x3b, 0x3c, 0xde, 0xdd, 0x3b, - 0x56, 0xf0, 0x31, 0x3c, 0xb1, 0x17, 0x1c, 0x3c, 0xa2, 0x0e, 0x22, 0x3c, - 0xa7, 0xf3, 0x13, 0x3c, 0x61, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, - 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x63, 0x6f, 0x6e, 0x76, - 0x32, 0x64, 0x5f, 0x32, 0x2f, 0x43, 0x6f, 0x6e, 0x76, 0x32, 0x44, 0x3b, - 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, - 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, 0x5f, 0x32, 0x2f, 0x4c, 0x61, 0x73, - 0x74, 0x56, 0x61, 0x6c, 0x75, 0x65, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x2f, - 0x46, 0x61, 0x6b, 0x65, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x57, 0x69, 0x74, - 0x68, 0x4d, 0x69, 0x6e, 0x4d, 0x61, 0x78, 0x56, 0x61, 0x72, 0x73, 0x50, - 0x65, 0x72, 0x43, 0x68, 0x61, 0x6e, 0x6e, 0x65, 0x6c, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x42, 0xce, 0xff, 0xff, - 0x00, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, - 0x44, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, - 0x68, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, - 0x1f, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, - 0x2c, 0xce, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0xaf, 0x6a, 0xb4, 0x3c, 0x28, 0x00, 0x00, 0x00, - 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, - 0x64, 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, 0x65, 0x5f, 0x63, 0x6f, - 0x6e, 0x76, 0x32, 0x64, 0x5f, 0x32, 0x2f, 0x64, 0x65, 0x70, 0x74, 0x68, - 0x77, 0x69, 0x73, 0x65, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x40, 0x00, 0x00, 0x00, 0x3e, 0xcf, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, - 0x14, 0x00, 0x00, 0x00, 0x28, 0x03, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x02, 0x4c, 0x03, 0x00, 0x00, 0xac, 0xce, 0xff, 0xff, - 0x08, 0x00, 0x00, 0x00, 0x0c, 0x02, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x40, 0x00, 0x00, 0x00, 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, - 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, - 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, - 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, - 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, - 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, - 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, - 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, - 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, - 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, - 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, - 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, - 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, - 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, - 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, - 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, - 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, - 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, - 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, - 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, - 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, - 0x1d, 0x22, 0x1b, 0x38, 0x1d, 0x22, 0x1b, 0x38, 0x28, 0x00, 0x00, 0x00, - 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, - 0x64, 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, 0x65, 0x5f, 0x63, 0x6f, - 0x6e, 0x76, 0x32, 0x64, 0x5f, 0x34, 0x2f, 0x64, 0x65, 0x70, 0x74, 0x68, - 0x77, 0x69, 0x73, 0x65, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x40, 0x00, 0x00, 0x00, 0xaa, 0xd2, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, - 0x14, 0x00, 0x00, 0x00, 0x2c, 0x03, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x09, 0xa0, 0x03, 0x00, 0x00, 0x62, 0xd5, 0xff, 0xff, - 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x0c, 0x02, 0x00, 0x00, - 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0xc5, 0x2c, 0xc8, 0x3a, - 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, - 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, - 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, - 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, - 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, - 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, - 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, - 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, - 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, - 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, - 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, - 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, - 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, - 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, - 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, - 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, - 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, - 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, - 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, - 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, - 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, 0xc5, 0x2c, 0xc8, 0x3a, - 0x78, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, - 0x61, 0x6e, 0x74, 0x5f, 0x64, 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, - 0x65, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, 0x5f, 0x32, 0x2f, 0x64, - 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, 0x65, 0x3b, 0x6d, 0x6f, 0x64, - 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x64, 0x65, 0x70, - 0x74, 0x68, 0x77, 0x69, 0x73, 0x65, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, - 0x64, 0x5f, 0x32, 0x2f, 0x4c, 0x61, 0x73, 0x74, 0x56, 0x61, 0x6c, 0x75, - 0x65, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x2f, 0x46, 0x61, 0x6b, 0x65, 0x51, - 0x75, 0x61, 0x6e, 0x74, 0x57, 0x69, 0x74, 0x68, 0x4d, 0x69, 0x6e, 0x4d, - 0x61, 0x78, 0x56, 0x61, 0x72, 0x73, 0x50, 0x65, 0x72, 0x43, 0x68, 0x61, - 0x6e, 0x6e, 0x65, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x40, 0x00, 0x00, 0x00, 0x12, 0xd6, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, - 0x18, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, - 0x0e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0xd8, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0x29, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0xfc, 0xd5, 0xff, 0xff, - 0x08, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x99, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0xa8, 0x65, 0xc6, 0x3c, 0x95, 0x00, 0x00, 0x00, - 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, - 0x61, 0x63, 0x74, 0x69, 0x76, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x5f, 0x31, - 0x2f, 0x52, 0x65, 0x6c, 0x75, 0x3b, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, - 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x62, 0x61, 0x74, 0x63, 0x68, 0x5f, - 0x6e, 0x6f, 0x72, 0x6d, 0x61, 0x6c, 0x69, 0x7a, 0x61, 0x74, 0x69, 0x6f, - 0x6e, 0x5f, 0x31, 0x2f, 0x46, 0x75, 0x73, 0x65, 0x64, 0x42, 0x61, 0x74, - 0x63, 0x68, 0x4e, 0x6f, 0x72, 0x6d, 0x56, 0x33, 0x3b, 0x6d, 0x6f, 0x64, - 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x64, 0x65, 0x70, - 0x74, 0x68, 0x77, 0x69, 0x73, 0x65, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, - 0x64, 0x5f, 0x34, 0x2f, 0x64, 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, - 0x65, 0x3b, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, - 0x74, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, 0x5f, 0x31, 0x2f, 0x43, - 0x6f, 0x6e, 0x76, 0x32, 0x44, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x29, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x40, 0x00, 0x00, 0x00, 0x7e, 0xd7, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, - 0x14, 0x00, 0x00, 0x00, 0x24, 0x03, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x02, 0x50, 0x03, 0x00, 0x00, 0xec, 0xd6, 0xff, 0xff, - 0x08, 0x00, 0x00, 0x00, 0x08, 0x02, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, - 0x9f, 0xb1, 0xb0, 0x38, 0x72, 0x68, 0x93, 0x38, 0x34, 0xb8, 0x48, 0x39, - 0x27, 0x1e, 0xbd, 0x38, 0x07, 0x18, 0xd5, 0x38, 0x2c, 0x83, 0x1b, 0x39, - 0x08, 0x67, 0x4d, 0x39, 0x71, 0x19, 0x9c, 0x38, 0x10, 0xd0, 0x0c, 0x39, - 0x2a, 0xa8, 0xee, 0x38, 0x06, 0xfd, 0x3e, 0x39, 0xcf, 0x96, 0x31, 0x39, - 0xb6, 0x9f, 0x28, 0x39, 0x11, 0x28, 0x1e, 0x39, 0x11, 0x1c, 0x44, 0x39, - 0x6f, 0xae, 0xf8, 0x38, 0x6a, 0xd6, 0x0d, 0x39, 0xe5, 0xeb, 0x2b, 0x39, - 0xf2, 0xe5, 0xe7, 0x38, 0x0f, 0x9c, 0x47, 0x39, 0x4a, 0xe1, 0x2a, 0x39, - 0xba, 0xb8, 0x8d, 0x38, 0x44, 0x67, 0x1e, 0x39, 0x46, 0x2d, 0x3e, 0x39, - 0x3f, 0x41, 0x0c, 0x39, 0xbf, 0x5b, 0xe9, 0x38, 0xd5, 0xc5, 0xdf, 0x38, - 0xae, 0x5c, 0x4b, 0x39, 0xdf, 0x69, 0x00, 0x39, 0x20, 0x27, 0xef, 0x38, - 0xc8, 0x05, 0x1f, 0x39, 0xa8, 0xb9, 0x45, 0x39, 0x94, 0x3a, 0xac, 0x38, - 0xb8, 0x03, 0xd0, 0x38, 0xa7, 0xad, 0x27, 0x39, 0x9a, 0x95, 0x89, 0x39, - 0x38, 0xe9, 0x1a, 0x39, 0x69, 0xc3, 0x96, 0x38, 0xaf, 0x9a, 0xa8, 0x38, - 0x8f, 0x78, 0x71, 0x39, 0x1a, 0x97, 0x12, 0x39, 0xfb, 0xd9, 0xff, 0x38, - 0x48, 0x5c, 0x99, 0x38, 0xcc, 0x56, 0xc2, 0x38, 0xc5, 0x6f, 0x08, 0x39, - 0x94, 0x74, 0x11, 0x39, 0xcd, 0x83, 0x20, 0x39, 0x16, 0x93, 0x58, 0x39, - 0xd6, 0x01, 0x48, 0x39, 0x1b, 0x9e, 0x0e, 0x39, 0x02, 0x1c, 0x7b, 0x39, - 0xfb, 0x71, 0x5a, 0x39, 0x63, 0xdd, 0x74, 0x39, 0x05, 0x54, 0x27, 0x39, - 0x26, 0x3b, 0x0e, 0x39, 0x1c, 0xce, 0x36, 0x39, 0xb1, 0xd4, 0xf8, 0x38, - 0xbc, 0x0d, 0xde, 0x38, 0xa3, 0xca, 0xc7, 0x38, 0xaa, 0xbf, 0x38, 0x39, - 0x66, 0x6a, 0x1e, 0x39, 0xf1, 0xde, 0xe4, 0x38, 0xb6, 0xbf, 0x24, 0x39, - 0xc9, 0xd2, 0x44, 0x39, 0x32, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, - 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x62, 0x61, 0x74, 0x63, - 0x68, 0x5f, 0x6e, 0x6f, 0x72, 0x6d, 0x61, 0x6c, 0x69, 0x7a, 0x61, 0x74, - 0x69, 0x6f, 0x6e, 0x5f, 0x31, 0x2f, 0x46, 0x75, 0x73, 0x65, 0x64, 0x42, - 0x61, 0x74, 0x63, 0x68, 0x4e, 0x6f, 0x72, 0x6d, 0x56, 0x33, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0xee, 0xda, 0xff, 0xff, - 0x00, 0x00, 0x00, 0x01, 0x14, 0x00, 0x00, 0x00, 0x28, 0x03, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x84, 0x03, 0x00, 0x00, - 0x5c, 0xda, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, 0x0c, 0x02, 0x00, 0x00, - 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0xb8, 0xef, 0xc3, 0x3b, - 0x14, 0x76, 0xa3, 0x3b, 0x1f, 0x94, 0x5e, 0x3c, 0x9f, 0xb6, 0xd1, 0x3b, - 0xef, 0x4c, 0xec, 0x3b, 0xc0, 0x72, 0x2c, 0x3c, 0x81, 0xc5, 0x63, 0x3c, - 0x62, 0x19, 0xad, 0x3b, 0xd3, 0x25, 0x1c, 0x3c, 0xe0, 0x52, 0x04, 0x3c, - 0xa5, 0xc9, 0x53, 0x3c, 0xde, 0xed, 0x44, 0x3c, 0xd4, 0xfc, 0x3a, 0x3c, - 0x5c, 0x61, 0x2f, 0x3c, 0x77, 0x77, 0x59, 0x3c, 0xbf, 0xe1, 0x09, 0x3c, - 0xbe, 0x48, 0x1d, 0x3c, 0xf2, 0xa4, 0x3e, 0x3c, 0x8d, 0x93, 0x00, 0x3c, - 0x08, 0x59, 0x5d, 0x3c, 0x4e, 0x7d, 0x3d, 0x3c, 0xd3, 0x27, 0x9d, 0x3b, - 0x70, 0xa7, 0x2f, 0x3c, 0x45, 0xe3, 0x52, 0x3c, 0x74, 0x87, 0x1b, 0x3c, - 0xce, 0x62, 0x01, 0x3c, 0x76, 0x24, 0xf8, 0x3b, 0x45, 0x82, 0x61, 0x3c, - 0xf4, 0x65, 0x0e, 0x3c, 0x45, 0x99, 0x04, 0x3c, 0x38, 0x57, 0x30, 0x3c, - 0x18, 0x42, 0x5b, 0x3c, 0x32, 0xfc, 0xbe, 0x3b, 0x05, 0xab, 0xe6, 0x3b, - 0x68, 0xf0, 0x39, 0x3c, 0x5b, 0x91, 0x98, 0x3c, 0x07, 0xc8, 0x2b, 0x3c, - 0x95, 0x2e, 0xa7, 0x3b, 0x40, 0xf7, 0xba, 0x3b, 0x4c, 0xe2, 0x85, 0x3c, - 0xef, 0x8d, 0x22, 0x3c, 0x78, 0xdb, 0x0d, 0x3c, 0xdd, 0x0f, 0xaa, 0x3b, - 0xd5, 0x80, 0xd7, 0x3b, 0x86, 0x4b, 0x17, 0x3c, 0xc6, 0x4b, 0x21, 0x3c, - 0xd8, 0xfe, 0x31, 0x3c, 0x07, 0x29, 0x70, 0x3c, 0xe5, 0xc9, 0x5d, 0x3c, - 0x2f, 0x26, 0x1e, 0x3c, 0x61, 0x3a, 0x8b, 0x3c, 0x14, 0x3c, 0x72, 0x3c, - 0x06, 0xc4, 0x87, 0x3c, 0x03, 0x8d, 0x39, 0x3c, 0x73, 0xb8, 0x1d, 0x3c, - 0x96, 0xb6, 0x4a, 0x3c, 0xf6, 0xf6, 0x09, 0x3c, 0x6f, 0x3c, 0xf6, 0x3b, - 0xaf, 0x8c, 0xdd, 0x3b, 0x53, 0xde, 0x4c, 0x3c, 0xea, 0xaa, 0x2f, 0x3c, - 0xb3, 0xcb, 0xfd, 0x3b, 0xcb, 0xb0, 0x36, 0x3c, 0x15, 0x42, 0x5a, 0x3c, - 0x61, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, - 0x61, 0x6e, 0x74, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, 0x5f, 0x31, - 0x2f, 0x43, 0x6f, 0x6e, 0x76, 0x32, 0x44, 0x3b, 0x6d, 0x6f, 0x64, 0x65, - 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x63, 0x6f, 0x6e, 0x76, - 0x32, 0x64, 0x5f, 0x31, 0x2f, 0x4c, 0x61, 0x73, 0x74, 0x56, 0x61, 0x6c, - 0x75, 0x65, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x2f, 0x46, 0x61, 0x6b, 0x65, - 0x51, 0x75, 0x61, 0x6e, 0x74, 0x57, 0x69, 0x74, 0x68, 0x4d, 0x69, 0x6e, - 0x4d, 0x61, 0x78, 0x56, 0x61, 0x72, 0x73, 0x50, 0x65, 0x72, 0x43, 0x68, - 0x61, 0x6e, 0x6e, 0x65, 0x6c, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x40, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x3a, 0xde, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, - 0x18, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, - 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x68, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0x29, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x24, 0xde, 0xff, 0xff, - 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0xeb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, - 0xd3, 0xdb, 0x66, 0x3c, 0x28, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, - 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x64, 0x65, 0x70, 0x74, - 0x68, 0x77, 0x69, 0x73, 0x65, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, - 0x5f, 0x31, 0x2f, 0x64, 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, 0x65, - 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x29, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, - 0x36, 0xdf, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x14, 0x00, 0x00, 0x00, - 0x28, 0x06, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, - 0x3c, 0x06, 0x00, 0x00, 0xa4, 0xde, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, - 0x0c, 0x04, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, 0x0f, 0xc0, 0xd7, 0x37, - 0x0f, 0xc0, 0xd7, 0x37, 0x1b, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, - 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x63, 0x6f, 0x6e, 0x76, - 0x32, 0x64, 0x5f, 0x34, 0x2f, 0x43, 0x6f, 0x6e, 0x76, 0x32, 0x44, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x92, 0xe5, 0xff, 0xff, - 0x00, 0x00, 0x00, 0x01, 0x14, 0x00, 0x00, 0x00, 0x2c, 0x06, 0x00, 0x00, - 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0xa0, 0x06, 0x00, 0x00, - 0x4a, 0xe8, 0xff, 0xff, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, - 0x0c, 0x04, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, 0xb1, 0x2c, 0xc8, 0x3a, - 0xb1, 0x2c, 0xc8, 0x3a, 0x78, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, - 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x64, 0x65, 0x70, 0x74, - 0x68, 0x77, 0x69, 0x73, 0x65, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, - 0x5f, 0x31, 0x2f, 0x64, 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, 0x65, - 0x3b, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, - 0x5f, 0x64, 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, 0x65, 0x5f, 0x63, - 0x6f, 0x6e, 0x76, 0x32, 0x64, 0x5f, 0x31, 0x2f, 0x4c, 0x61, 0x73, 0x74, - 0x56, 0x61, 0x6c, 0x75, 0x65, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x2f, 0x46, - 0x61, 0x6b, 0x65, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x57, 0x69, 0x74, 0x68, - 0x4d, 0x69, 0x6e, 0x4d, 0x61, 0x78, 0x56, 0x61, 0x72, 0x73, 0x50, 0x65, - 0x72, 0x43, 0x68, 0x61, 0x6e, 0x6e, 0x65, 0x6c, 0x00, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0xfa, 0xeb, 0xff, 0xff, - 0x00, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, - 0x44, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, - 0xc0, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, - 0x2d, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, - 0xe4, 0xeb, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0xa3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0x01, 0x00, 0x00, 0x00, 0xb0, 0xf5, 0x89, 0x3c, 0x82, 0x00, 0x00, 0x00, - 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, - 0x61, 0x63, 0x74, 0x69, 0x76, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x52, - 0x65, 0x6c, 0x75, 0x3b, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, - 0x61, 0x6e, 0x74, 0x5f, 0x62, 0x61, 0x74, 0x63, 0x68, 0x5f, 0x6e, 0x6f, - 0x72, 0x6d, 0x61, 0x6c, 0x69, 0x7a, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, - 0x46, 0x75, 0x73, 0x65, 0x64, 0x42, 0x61, 0x74, 0x63, 0x68, 0x4e, 0x6f, - 0x72, 0x6d, 0x56, 0x33, 0x3b, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, - 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, 0x5f, - 0x34, 0x2f, 0x43, 0x6f, 0x6e, 0x76, 0x32, 0x44, 0x3b, 0x6d, 0x6f, 0x64, - 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x63, 0x6f, 0x6e, - 0x76, 0x32, 0x64, 0x2f, 0x43, 0x6f, 0x6e, 0x76, 0x32, 0x44, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x2d, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x4e, 0xed, 0xff, 0xff, - 0x00, 0x00, 0x00, 0x01, 0x14, 0x00, 0x00, 0x00, 0x24, 0x06, 0x00, 0x00, - 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x50, 0x06, 0x00, 0x00, - 0xbc, 0xec, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, 0x08, 0x04, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, - 0x6f, 0xcc, 0x40, 0x39, 0x6a, 0x09, 0xad, 0x39, 0xff, 0x39, 0xa7, 0x39, - 0x69, 0x9b, 0xb3, 0x39, 0x95, 0xca, 0x8d, 0x39, 0xdf, 0xb5, 0x71, 0x39, - 0x9e, 0x41, 0x7e, 0x39, 0x5e, 0x8c, 0xa2, 0x39, 0x2b, 0xc7, 0xc1, 0x39, - 0x95, 0xc9, 0x84, 0x39, 0xb6, 0xaf, 0xa6, 0x39, 0x9e, 0xf6, 0x82, 0x39, - 0x5a, 0x3a, 0x0f, 0x39, 0xe0, 0x00, 0xfe, 0x39, 0x3d, 0xd6, 0xc2, 0x39, - 0x54, 0xe9, 0xa6, 0x39, 0x38, 0x21, 0x60, 0x39, 0x7f, 0x3c, 0x85, 0x39, - 0x29, 0xfd, 0x6d, 0x39, 0xe7, 0x38, 0x3f, 0x39, 0xa6, 0xe4, 0xe9, 0x39, - 0x01, 0xab, 0xde, 0x39, 0x24, 0x4e, 0x9a, 0x39, 0x6f, 0x14, 0x44, 0x39, - 0x50, 0xc2, 0x81, 0x39, 0x32, 0xe1, 0x0b, 0x3a, 0xf7, 0xcb, 0xa2, 0x39, - 0x0c, 0x45, 0xab, 0x39, 0x91, 0xd4, 0xfb, 0x39, 0x50, 0x40, 0x79, 0x39, - 0x0b, 0xbd, 0xa6, 0x39, 0xe2, 0x17, 0xb1, 0x39, 0x34, 0x16, 0x9e, 0x39, - 0xff, 0xc5, 0xb1, 0x39, 0x40, 0x9c, 0xa2, 0x39, 0xb8, 0x52, 0xc4, 0x39, - 0x7c, 0x32, 0xc8, 0x39, 0x6b, 0xc1, 0x83, 0x39, 0x5e, 0x62, 0x7c, 0x39, - 0xf1, 0x08, 0xd4, 0x39, 0xa7, 0xbb, 0xe1, 0x39, 0x0b, 0x1a, 0x9d, 0x39, - 0x0c, 0xd6, 0x8c, 0x39, 0xcf, 0xa9, 0x7c, 0x39, 0x42, 0xea, 0xa3, 0x39, - 0xa3, 0x97, 0xb8, 0x39, 0x28, 0x40, 0xbd, 0x39, 0xad, 0x12, 0x0b, 0x3a, - 0x43, 0x0e, 0x87, 0x39, 0x65, 0xfa, 0x8f, 0x39, 0x7e, 0x0d, 0x80, 0x39, - 0x4f, 0x31, 0xa2, 0x39, 0x2f, 0x46, 0x94, 0x39, 0x55, 0x66, 0xab, 0x39, - 0xa4, 0x2c, 0xea, 0x39, 0xaa, 0x08, 0xe9, 0x38, 0xbf, 0x9f, 0x5b, 0x39, - 0xf6, 0xbd, 0x12, 0x39, 0x12, 0xaf, 0x8f, 0x39, 0x5f, 0x16, 0xf1, 0x38, - 0xe3, 0x08, 0xb9, 0x39, 0x81, 0x51, 0x5f, 0x39, 0x96, 0x8c, 0x89, 0x39, - 0x9b, 0x44, 0xbc, 0x39, 0xcf, 0x03, 0xc5, 0x39, 0xae, 0x09, 0xe5, 0x38, - 0xdc, 0x12, 0x9a, 0x39, 0x9d, 0x52, 0x81, 0x39, 0x08, 0xb3, 0xaf, 0x39, - 0x33, 0xdc, 0xe5, 0x39, 0xfe, 0x39, 0x9a, 0x39, 0xc4, 0x64, 0xdd, 0x39, - 0xf5, 0x3f, 0xda, 0x39, 0x61, 0x6e, 0x9e, 0x39, 0xcd, 0x28, 0x39, 0x39, - 0xc1, 0x64, 0x8c, 0x39, 0x45, 0x02, 0xce, 0x39, 0xac, 0xf3, 0xa6, 0x39, - 0xed, 0x02, 0xc2, 0x39, 0x07, 0x23, 0x68, 0x39, 0x9c, 0x06, 0xdd, 0x39, - 0x27, 0x20, 0x01, 0x39, 0xa9, 0xe3, 0xcb, 0x39, 0x9c, 0xe2, 0x9d, 0x39, - 0x47, 0xc9, 0xb2, 0x39, 0x0e, 0x56, 0xb1, 0x39, 0xd6, 0xbe, 0x92, 0x39, - 0x8e, 0x83, 0x87, 0x39, 0xa3, 0x0a, 0x94, 0x39, 0x6f, 0x35, 0xdc, 0x39, - 0xf9, 0x92, 0x81, 0x39, 0x5e, 0x90, 0x83, 0x39, 0x13, 0xeb, 0x95, 0x39, - 0xf0, 0x38, 0xb1, 0x39, 0x6c, 0xe2, 0xac, 0x39, 0x0d, 0x65, 0xb3, 0x39, - 0xb0, 0x7a, 0xd4, 0x39, 0xe4, 0xc3, 0xb4, 0x39, 0x7b, 0x84, 0xb4, 0x39, - 0xa0, 0xab, 0x97, 0x39, 0xdc, 0xf6, 0xb9, 0x39, 0xea, 0x9e, 0x9b, 0x39, - 0xce, 0x32, 0xd0, 0x39, 0x6d, 0xc4, 0x60, 0x39, 0x18, 0x55, 0xaf, 0x39, - 0xc1, 0x39, 0xb6, 0x39, 0xdc, 0xf8, 0x28, 0x39, 0xc2, 0x22, 0x76, 0x39, - 0xd4, 0xfb, 0xef, 0x39, 0x2b, 0x42, 0xc2, 0x39, 0x3f, 0x05, 0xe4, 0x39, - 0xe1, 0x41, 0x97, 0x39, 0xd5, 0x06, 0x52, 0x39, 0x84, 0x5d, 0xb5, 0x39, - 0x9d, 0x98, 0xcd, 0x39, 0x7d, 0xd3, 0xb7, 0x38, 0x7c, 0xfd, 0xad, 0x39, - 0x5d, 0xaf, 0x91, 0x39, 0x07, 0x98, 0x7c, 0x39, 0xed, 0x51, 0x5b, 0x39, - 0x0f, 0x5f, 0x97, 0x39, 0xd9, 0xf6, 0x05, 0x3a, 0x72, 0xbc, 0xb0, 0x39, - 0x55, 0x01, 0x82, 0x39, 0x9c, 0xf8, 0xf0, 0x38, 0x28, 0x55, 0xdf, 0x39, - 0x36, 0xbf, 0x8d, 0x39, 0x3b, 0x23, 0x5c, 0x39, 0x30, 0x00, 0x00, 0x00, - 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, - 0x62, 0x61, 0x74, 0x63, 0x68, 0x5f, 0x6e, 0x6f, 0x72, 0x6d, 0x61, 0x6c, - 0x69, 0x7a, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x46, 0x75, 0x73, 0x65, - 0x64, 0x42, 0x61, 0x74, 0x63, 0x68, 0x4e, 0x6f, 0x72, 0x6d, 0x56, 0x33, - 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, - 0xbe, 0xf3, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x14, 0x00, 0x00, 0x00, - 0x24, 0x06, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, - 0x7c, 0x06, 0x00, 0x00, 0x2c, 0xf3, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, - 0x08, 0x04, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0xf7, 0xbc, 0xb8, 0x3c, 0x73, 0xcd, 0x25, 0x3d, - 0x37, 0x3c, 0x20, 0x3d, 0x20, 0x19, 0x2c, 0x3d, 0x07, 0xdd, 0x07, 0x3d, - 0xea, 0x9a, 0xe7, 0x3c, 0x62, 0xa0, 0xf3, 0x3c, 0xa8, 0xc0, 0x1b, 0x3d, - 0x37, 0xad, 0x39, 0x3d, 0xca, 0x78, 0xfe, 0x3c, 0xb6, 0xb7, 0x1f, 0x3d, - 0xe9, 0xf9, 0xfa, 0x3c, 0x6c, 0x3d, 0x89, 0x3c, 0x59, 0x62, 0x73, 0x3d, - 0xf4, 0xb0, 0x3a, 0x3d, 0xec, 0xee, 0x1f, 0x3d, 0x6c, 0xc2, 0xd6, 0x3c, - 0x03, 0x55, 0xff, 0x3c, 0x08, 0x0a, 0xe4, 0x3c, 0x4e, 0x3a, 0xb7, 0x3c, - 0x5b, 0x1d, 0x60, 0x3d, 0xda, 0x5b, 0x55, 0x3d, 0xa8, 0xda, 0x13, 0x3d, - 0xd9, 0xe1, 0xbb, 0x3c, 0x14, 0xab, 0xf8, 0x3c, 0x1a, 0x08, 0x86, 0x3d, - 0x99, 0xfd, 0x1b, 0x3d, 0xfe, 0x1b, 0x24, 0x3d, 0x4c, 0x4d, 0x71, 0x3d, - 0xa5, 0xd4, 0xee, 0x3c, 0x7d, 0xc4, 0x1f, 0x3d, 0x80, 0xb0, 0x29, 0x3d, - 0x3e, 0x7a, 0x17, 0x3d, 0x56, 0x57, 0x2a, 0x3d, 0xe1, 0xcf, 0x1b, 0x3d, - 0x87, 0x1d, 0x3c, 0x3d, 0xd4, 0xd3, 0x3f, 0x3d, 0x8c, 0x7e, 0xfc, 0x3c, - 0x2b, 0xd5, 0xf1, 0x3c, 0x97, 0x2b, 0x4b, 0x3d, 0xb2, 0x4b, 0x58, 0x3d, - 0xa0, 0x88, 0x16, 0x3d, 0xb8, 0xf2, 0x06, 0x3d, 0x9f, 0x19, 0xf2, 0x3c, - 0xec, 0x0f, 0x1d, 0x3d, 0xff, 0xdf, 0x30, 0x3d, 0xa9, 0x56, 0x35, 0x3d, - 0x37, 0x42, 0x85, 0x3d, 0xcc, 0x68, 0x01, 0x3d, 0x70, 0xf5, 0x09, 0x3d, - 0xf6, 0x65, 0xf5, 0x3c, 0x68, 0x69, 0x1b, 0x3d, 0x3f, 0x13, 0x0e, 0x3d, - 0xe3, 0x3b, 0x24, 0x3d, 0x56, 0x62, 0x60, 0x3d, 0x92, 0x4a, 0x5f, 0x3c, - 0x2c, 0x71, 0xd2, 0x3c, 0x6c, 0x9b, 0x8c, 0x3c, 0x43, 0xad, 0x09, 0x3d, - 0x15, 0x02, 0x67, 0x3c, 0x83, 0x4c, 0x31, 0x3d, 0x64, 0xfb, 0xd5, 0x3c, - 0x70, 0xcc, 0x03, 0x3d, 0xa0, 0x65, 0x34, 0x3d, 0x37, 0xc7, 0x3c, 0x3d, - 0x5a, 0x76, 0x5b, 0x3c, 0xda, 0xa1, 0x13, 0x3d, 0x04, 0xd5, 0xf7, 0x3c, - 0x92, 0x5a, 0x28, 0x3d, 0x12, 0x40, 0x5c, 0x3d, 0x59, 0xc7, 0x13, 0x3d, - 0x40, 0x23, 0x54, 0x3d, 0x17, 0x20, 0x51, 0x3d, 0xbc, 0xce, 0x17, 0x3d, - 0x17, 0x6b, 0xb1, 0x3c, 0x29, 0x86, 0x06, 0x3d, 0x6a, 0x65, 0x45, 0x3d, - 0xd5, 0xf8, 0x1f, 0x3d, 0x7a, 0xe6, 0x39, 0x3d, 0x88, 0x6e, 0xde, 0x3c, - 0x08, 0xc9, 0x53, 0x3d, 0x50, 0x74, 0x77, 0x3c, 0x7e, 0x5d, 0x43, 0x3d, - 0xcf, 0x48, 0x17, 0x3d, 0xc7, 0x4f, 0x2b, 0x3d, 0x13, 0xec, 0x29, 0x3d, - 0x43, 0x9c, 0x0c, 0x3d, 0x30, 0xd9, 0x01, 0x3d, 0x30, 0xda, 0x0d, 0x3d, - 0x9a, 0x00, 0x53, 0x3d, 0x5b, 0x50, 0xf8, 0x3c, 0x8d, 0x20, 0xfc, 0x3c, - 0x8a, 0xa6, 0x0f, 0x3d, 0x2d, 0xd0, 0x29, 0x3d, 0x16, 0xa8, 0x25, 0x3d, - 0x0a, 0xe5, 0x2b, 0x3d, 0x95, 0x98, 0x4b, 0x3d, 0x36, 0x35, 0x2d, 0x3d, - 0x74, 0xf8, 0x2c, 0x3d, 0x57, 0x54, 0x11, 0x3d, 0x89, 0x30, 0x32, 0x3d, - 0x59, 0x1d, 0x15, 0x3d, 0x83, 0x7e, 0x47, 0x3d, 0xce, 0x5e, 0xd7, 0x3c, - 0x8f, 0x00, 0x28, 0x3d, 0x72, 0x9b, 0x2e, 0x3d, 0x66, 0xe8, 0xa1, 0x3c, - 0x6f, 0xd8, 0xeb, 0x3c, 0x59, 0xf3, 0x65, 0x3d, 0x13, 0x23, 0x3a, 0x3d, - 0xce, 0x7c, 0x5a, 0x3d, 0x03, 0xef, 0x10, 0x3d, 0xf9, 0x3e, 0xc9, 0x3c, - 0x69, 0xc8, 0x2d, 0x3d, 0x2c, 0x00, 0x45, 0x3d, 0x0d, 0x24, 0x30, 0x3c, - 0x50, 0xb7, 0x26, 0x3d, 0x24, 0x98, 0x0b, 0x3d, 0x96, 0x08, 0xf2, 0x3c, - 0x9b, 0x26, 0xd2, 0x3c, 0xf9, 0x0a, 0x11, 0x3d, 0x11, 0x5d, 0x80, 0x3d, - 0xe3, 0x58, 0x29, 0x3d, 0xd8, 0x23, 0xf9, 0x3c, 0x8f, 0xe5, 0x66, 0x3c, - 0xe3, 0xfe, 0x55, 0x3d, 0x22, 0xd2, 0x07, 0x3d, 0x28, 0xef, 0xd2, 0x3c, - 0x5d, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, - 0x61, 0x6e, 0x74, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, 0x2f, 0x43, - 0x6f, 0x6e, 0x76, 0x32, 0x44, 0x3b, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, - 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, - 0x2f, 0x4c, 0x61, 0x73, 0x74, 0x56, 0x61, 0x6c, 0x75, 0x65, 0x51, 0x75, - 0x61, 0x6e, 0x74, 0x2f, 0x46, 0x61, 0x6b, 0x65, 0x51, 0x75, 0x61, 0x6e, - 0x74, 0x57, 0x69, 0x74, 0x68, 0x4d, 0x69, 0x6e, 0x4d, 0x61, 0x78, 0x56, - 0x61, 0x72, 0x73, 0x50, 0x65, 0x72, 0x43, 0x68, 0x61, 0x6e, 0x6e, 0x65, - 0x6c, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, - 0x02, 0xfa, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x00, - 0x28, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x09, 0x68, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0xff, 0xff, 0xff, 0xff, 0x2d, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x28, 0x00, 0x00, 0x00, 0xec, 0xf9, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, - 0x14, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0xb9, 0x95, 0x05, 0x3c, 0x27, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, - 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x64, 0x65, 0x70, 0x74, - 0x68, 0x77, 0x69, 0x73, 0x65, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, - 0x2f, 0x64, 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, 0x65, 0x31, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x2d, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0xfe, 0xfa, 0xff, 0xff, - 0x00, 0x00, 0x00, 0x01, 0x14, 0x00, 0x00, 0x00, 0x08, 0x02, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x28, 0x02, 0x00, 0x00, - 0x6c, 0xfa, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, 0x4c, 0x01, 0x00, 0x00, - 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0xc3, 0x4c, 0xff, 0x36, - 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, - 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, - 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, - 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, - 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, - 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, - 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, - 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, - 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, - 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, - 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, - 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, - 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, 0xc3, 0x4c, 0xff, 0x36, - 0x26, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, - 0x61, 0x6e, 0x74, 0x5f, 0x64, 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, - 0x65, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, 0x2f, 0x64, 0x65, 0x70, - 0x74, 0x68, 0x77, 0x69, 0x73, 0x65, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x28, 0x00, 0x00, 0x00, 0x46, 0xfd, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, - 0x28, 0x00, 0x00, 0x00, 0x1c, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x09, 0x8c, 0x02, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00, - 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x08, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x04, 0x00, 0x12, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x08, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, - 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, - 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, - 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, - 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, - 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, - 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, - 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, - 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, - 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, - 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, - 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, - 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, - 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, 0x76, 0x4d, 0xfe, 0x3a, - 0x76, 0x4d, 0xfe, 0x3a, 0x74, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, - 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x64, 0x65, 0x70, 0x74, - 0x68, 0x77, 0x69, 0x73, 0x65, 0x5f, 0x63, 0x6f, 0x6e, 0x76, 0x32, 0x64, - 0x2f, 0x64, 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, 0x65, 0x3b, 0x6d, - 0x6f, 0x64, 0x65, 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x64, - 0x65, 0x70, 0x74, 0x68, 0x77, 0x69, 0x73, 0x65, 0x5f, 0x63, 0x6f, 0x6e, - 0x76, 0x32, 0x64, 0x2f, 0x4c, 0x61, 0x73, 0x74, 0x56, 0x61, 0x6c, 0x75, - 0x65, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x2f, 0x46, 0x61, 0x6b, 0x65, 0x51, - 0x75, 0x61, 0x6e, 0x74, 0x57, 0x69, 0x74, 0x68, 0x4d, 0x69, 0x6e, 0x4d, - 0x61, 0x78, 0x56, 0x61, 0x72, 0x73, 0x50, 0x65, 0x72, 0x43, 0x68, 0x61, - 0x6e, 0x6e, 0x65, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0x00, 0x1c, 0x00, 0x18, 0x00, - 0x17, 0x00, 0x10, 0x00, 0x0c, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x07, 0x00, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, - 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x02, 0x2c, 0x00, 0x00, 0x00, 0x04, 0x00, 0x04, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x64, 0x65, - 0x6c, 0x2f, 0x71, 0x75, 0x61, 0x6e, 0x74, 0x5f, 0x66, 0x6c, 0x61, 0x74, - 0x74, 0x65, 0x6e, 0x2f, 0x43, 0x6f, 0x6e, 0x73, 0x74, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0x00, - 0x20, 0x00, 0x1c, 0x00, 0x1b, 0x00, 0x14, 0x00, 0x10, 0x00, 0x0c, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x16, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, - 0x50, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, - 0x64, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, - 0x31, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, - 0x0c, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0x01, 0x00, 0x00, 0x00, 0x81, 0x80, 0x80, 0x3b, 0x19, 0x00, 0x00, 0x00, - 0x73, 0x65, 0x72, 0x76, 0x69, 0x6e, 0x67, 0x5f, 0x64, 0x65, 0x66, 0x61, - 0x75, 0x6c, 0x74, 0x5f, 0x69, 0x6e, 0x70, 0x75, 0x74, 0x5f, 0x31, 0x3a, - 0x30, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x31, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, - 0x06, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x58, 0x00, 0x00, 0x00, - 0x44, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0xac, 0xff, 0xff, 0xff, 0x09, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0xf4, 0xff, 0xff, 0xff, - 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0x0c, 0x00, 0x0c, 0x00, - 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x0c, 0x00, 0x00, 0x00, - 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x72, 0xe0, 0xff, 0xff, 0xff, - 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, - 0xf0, 0xff, 0xff, 0xff, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x03, 0x0c, 0x00, 0x10, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x08, 0x00, 0x04, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04 -}; -const unsigned int g_strww_model_data_len = 63992; diff --git a/benchmark/reference_submissions/streaming_wakeword/submitter_implemented.cpp b/benchmark/reference_submissions/streaming_wakeword/submitter_implemented.cpp deleted file mode 100644 index ef275e69..00000000 --- a/benchmark/reference_submissions/streaming_wakeword/submitter_implemented.cpp +++ /dev/null @@ -1,184 +0,0 @@ -/* -Copyright 2020 EEMBC and The MLPerf Authors. All Rights Reserved. -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - http://www.apache.org/licenses/LICENSE-2.0 -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -This file reflects a modified version of th_lib from EEMBC. The reporting logic -in th_results is copied from the original in EEMBC. -==============================================================================*/ -/// \file -/// \brief C++ implementations of submitter_implemented.h - -#include "api/submitter_implemented.h" - -#include -#include -#include -#include - -#include "api/internally_implemented.h" -#include "mbed.h" -#include "tensorflow/lite/micro/kernels/micro_ops.h" -#include "tensorflow/lite/micro/micro_error_reporter.h" -#include "tensorflow/lite/micro/micro_interpreter.h" -#include "tensorflow/lite/micro/micro_mutable_op_resolver.h" -#include "tensorflow/lite/schema/schema_generated.h" -#include "util/quantization_helpers.h" -#include "util/tf_micro_model_runner.h" -#include "str_ww/strww_input_data.h" -#include "str_ww/strww_model_data.h" -#include "str_ww/strww_model_settings.h" - -UnbufferedSerial pc(USBTX, USBRX); -DigitalOut timestampPin(D7); - -constexpr int kTensorArenaSize = 200 * 1024; -alignas(16) uint8_t tensor_arena[kTensorArenaSize]; - -tflite::MicroModelRunner *runner; - -// Implement this method to prepare for inference and preprocess inputs. -void th_load_tensor() { - int8_t input[kStrwwInputSize]; - - size_t bytes = ee_get_buffer(reinterpret_cast(input), - kStrwwInputSize * sizeof(int8_t)); - if (bytes / sizeof(int8_t) != kStrwwInputSize) { - th_printf("Input db has %d elemented, expected %d\n", bytes / sizeof(int8_t), - kStrwwInputSize); - return; - } - runner->SetInput(input); -} - - -// Add to this method to return real inference results. -void th_results() { - /** - * The results need to be printed back in exactly this format; if easier - * to just modify this loop than copy to results[] above, do that. - */ - th_printf("m-results-["); - int kCategoryCount = 12; - - for (size_t i = 0; i < kCategoryCount; i++) { - float converted = - DequantizeInt8ToFloat(runner->GetOutput()[i], runner->output_scale(), - runner->output_zero_point()); - - // Some platforms don't implement floating point formatting. - th_printf("0.%d", static_cast(converted * 10)); - th_printf("%d", static_cast(converted * 100) % 10); - th_printf("%d", static_cast(converted * 1000) % 10); - - if (i < (kCategoryCount - 1)) { - th_printf(","); - } - } - th_printf("]\r\n"); -} - -// Implement this method with the logic to perform one inference cycle. -void th_infer() { runner->Invoke(); } - -/// \brief optional API. -void th_final_initialize(void) { - static tflite::MicroMutableOpResolver<6> resolver; - resolver.AddFullyConnected(); - resolver.AddConv2D(); - resolver.AddDepthwiseConv2D(); - resolver.AddReshape(); - resolver.AddSoftmax(); - resolver.AddAveragePool2D(); - - static tflite::MicroModelRunner model_runner( - g_strww_model_data, resolver, tensor_arena, kTensorArenaSize); - runner = &model_runner; -} - -void th_pre() {} -void th_post() {} - -void th_command_ready(char volatile *p_command) { - p_command = p_command; - ee_serial_command_parser_callback((char *)p_command); -} - -// th_libc implementations. -int th_strncmp(const char *str1, const char *str2, size_t n) { - return strncmp(str1, str2, n); -} - -char *th_strncpy(char *dest, const char *src, size_t n) { - return strncpy(dest, src, n); -} - -size_t th_strnlen(const char *str, size_t maxlen) { - return strnlen(str, maxlen); -} - -char *th_strcat(char *dest, const char *src) { return strcat(dest, src); } - -char *th_strtok(char *str1, const char *sep) { return strtok(str1, sep); } - -int th_atoi(const char *str) { return atoi(str); } - -void *th_memset(void *b, int c, size_t len) { return memset(b, c, len); } - -void *th_memcpy(void *dst, const void *src, size_t n) { - return memcpy(dst, src, n); -} - -/* N.B.: Many embedded *printf SDKs do not support all format specifiers. */ -int th_vprintf(const char *format, va_list ap) { return vprintf(format, ap); } -void th_printf(const char *p_fmt, ...) { - va_list args; - va_start(args, p_fmt); - (void)th_vprintf(p_fmt, args); /* ignore return */ - va_end(args); -} - -char th_getchar() { return getchar(); } - -void th_serialport_initialize(void) { -# if EE_CFG_ENERGY_MODE==1 - pc.baud(9600); -# else - pc.baud(115200); -# endif -} - -void th_timestamp(void) { -# if EE_CFG_ENERGY_MODE==1 - timestampPin = 0; - for (int i=0; i<100'000; ++i) { - asm("nop"); - } - timestampPin = 1; -# else - unsigned long microSeconds = 0ul; - /* USER CODE 2 BEGIN */ - microSeconds = us_ticker_read(); - /* USER CODE 2 END */ - /* This message must NOT be changed. */ - th_printf(EE_MSG_TIMESTAMP, microSeconds); -# endif -} - -void th_timestamp_initialize(void) { - /* USER CODE 1 BEGIN */ - // Setting up BOTH perf and energy here - /* USER CODE 1 END */ - /* This message must NOT be changed. */ - th_printf(EE_MSG_TIMESTAMP_MODE); - /* Always call the timestamp on initialize so that the open-drain output - is set to "1" (so that we catch a falling edge) */ - th_timestamp(); -} diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.ai/.ldupdatedone b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/.ai/.ldupdatedone similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.ai/.ldupdatedone rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/.ai/.ldupdatedone diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.ai/sww_model_strm_ww_int8.tflite_c_graph.json b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/.ai/sww_model_strm_ww_int8.tflite_c_graph.json similarity index 99% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.ai/sww_model_strm_ww_int8.tflite_c_graph.json rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/.ai/sww_model_strm_ww_int8.tflite_c_graph.json index 31a86081..184fa27b 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.ai/sww_model_strm_ww_int8.tflite_c_graph.json +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/.ai/sww_model_strm_ww_int8.tflite_c_graph.json @@ -117,7 +117,7 @@ } }, "activations_alignment": 4, - "arguments": "generate --target stm32l4 --name sww_model -m /Users/jeremy/dev/tiny_mlperf/tiny_jhsyn/benchmark/training/streaming_wakeword/trained_models/strm_ww_int8.tflite --compression none --verbosity 1 --allocate-inputs --allocate-outputs --workspace /var/folders/qb/jcjkm0nx4878vyqfjy786xdh0000gn/T/mxAI_workspace20582448339648752323913053637901544 --output /Users/jeremy/.stm32cubemx/sww_model_output", + "arguments": "generate --target stm32l4 --name sww_model -m /Users/jeremy/dev/tiny_mlperf/tiny_main/benchmark/training/streaming_wakeword/trained_models/strm_ww_int8.tflite --compression none --verbosity 1 --allocate-inputs --allocate-outputs --workspace /var/folders/qb/jcjkm0nx4878vyqfjy786xdh0000gn/T/mxAI_workspace22421878873072086813923037304615305 --output /Users/jeremy/.stm32cubemx/sww_model_output", "c_activations_count": 1, "c_arrays": [ { @@ -2685,7 +2685,7 @@ ] }, "data_alignment": 4, - "date_time": "2025-01-10T17:46:50-0500", + "date_time": "2025-05-21T13:28:40-0700", "inputs": [ "serving_default_input_10_output" ], diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.ai/sww_model_strm_ww_int8.tflite_c_info.json b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/.ai/sww_model_strm_ww_int8.tflite_c_info.json similarity index 98% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.ai/sww_model_strm_ww_int8.tflite_c_info.json rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/.ai/sww_model_strm_ww_int8.tflite_c_info.json index 8762c024..1338725e 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.ai/sww_model_strm_ww_int8.tflite_c_info.json +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/.ai/sww_model_strm_ww_int8.tflite_c_info.json @@ -2531,35 +2531,35 @@ "environment": { "device": null, "generated_model": { - "generated_time": "2025-01-10T17:46:50-0500", + "generated_time": "2025-05-21T13:28:40-0700", "model_files": [ { "name": "sww_model_data_params.h", - "signature": "0xa9c0ba7dc1fd3c9bf8e61bf9eb3b73f5" + "signature": "0x4c169e939ff061b9012f98a375f56664" }, { "name": "sww_model_data_params.c", - "signature": "0xd34308a274c1786cf88a83e488c19237" + "signature": "0xf781e20a3c640513dde2c31684ade494" }, { "name": "sww_model_data.h", - "signature": "0x0e38f39eeb1e49f96309b37806340ba5" + "signature": "0x6556ef7eb307247c2bca219d6d822691" }, { "name": "sww_model_data.c", - "signature": "0xbd4f1394448334aaa648465a697ff248" + "signature": "0x6af81592a99418ba884b3750555bd56f" }, { "name": "sww_model_config.h", - "signature": "0x1e006f0178a528d9e6ef9c9c8008112a" + "signature": "0x15a07c18a2a7ebd115b256ae8252287f" }, { "name": "sww_model.h", - "signature": "0x4f931a14da2e772d872c18a3fae4a9b1" + "signature": "0xe6ae3a87fcf601fcf9173a9abfb03154" }, { "name": "sww_model.c", - "signature": "0x25447f215967cf35cfc7f43963a21a83" + "signature": "0x01fb4b63b6794479684750d4b213926d" } ], "n_params": null, @@ -2567,11 +2567,11 @@ "size": null, "type": null }, - "network_signature": "0x4bb178e311161751", + "network_signature": "0x5f4f4fd08eb2617e", "test_name": "", "tools": [ { - "arguments": "generate --target stm32l4 --name sww_model -m /Users/jeremy/dev/tiny_mlperf/tiny_jhsyn/benchmark/training/streaming_wakeword/trained_models/strm_ww_int8.tflite --compression none --verbosity 1 --allocate-inputs --allocate-outputs --workspace /var/folders/qb/jcjkm0nx4878vyqfjy786xdh0000gn/T/mxAI_workspace20582448339648752323913053637901544 --output /Users/jeremy/.stm32cubemx/sww_model_output", + "arguments": "generate --target stm32l4 --name sww_model -m /Users/jeremy/dev/tiny_mlperf/tiny_main/benchmark/training/streaming_wakeword/trained_models/strm_ww_int8.tflite --compression none --verbosity 1 --allocate-inputs --allocate-outputs --workspace /var/folders/qb/jcjkm0nx4878vyqfjy786xdh0000gn/T/mxAI_workspace22421878873072086813923037304615305 --output /Users/jeremy/.stm32cubemx/sww_model_output", "environment": [ "STATS_TYPE=X-CUBE-AI" ], diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.ai/sww_model_strm_ww_int8.tflite_report.json b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/.ai/sww_model_strm_ww_int8.tflite_report.json similarity index 95% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.ai/sww_model_strm_ww_int8.tflite_report.json rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/.ai/sww_model_strm_ww_int8.tflite_report.json index dbb1030c..e6e88132 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.ai/sww_model_strm_ww_int8.tflite_report.json +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/.ai/sww_model_strm_ww_int8.tflite_report.json @@ -1,7 +1,7 @@ { "_allocate_inputs": 4, "_allocate_outputs": 4, - "cli_parameters": "generate --target stm32l4 --name sww_model -m /Users/jeremy/dev/tiny_mlperf/tiny_jhsyn/benchmark/training/streaming_wakeword/trained_models/strm_ww_int8.tflite --compression none --verbosity 1 --allocate-inputs --allocate-outputs --workspace /var/folders/qb/jcjkm0nx4878vyqfjy786xdh0000gn/T/mxAI_workspace20582448339648752323913053637901544 --output /Users/jeremy/.stm32cubemx/sww_model_output", + "cli_parameters": "generate --target stm32l4 --name sww_model -m /Users/jeremy/dev/tiny_mlperf/tiny_main/benchmark/training/streaming_wakeword/trained_models/strm_ww_int8.tflite --compression none --verbosity 1 --allocate-inputs --allocate-outputs --workspace /var/folders/qb/jcjkm0nx4878vyqfjy786xdh0000gn/T/mxAI_workspace22421878873072086813923037304615305 --output /Users/jeremy/.stm32cubemx/sww_model_output", "cli_version": { "extra": "19899", "major": 1, @@ -11,7 +11,7 @@ "cli_version_str": "1.0.0-19899", "code_size": 0, "compression": [], - "date_time": "2025-01-10T17:46:50-0500", + "date_time": "2025-05-21T13:28:40-0700", "error": 0, "error_str": [], "exec_cmd": "generate", @@ -444,7 +444,7 @@ } ], "model_files": [ - "/Users/jeremy/dev/tiny_mlperf/tiny_jhsyn/benchmark/training/streaming_wakeword/trained_models/strm_ww_int8.tflite" + "/Users/jeremy/dev/tiny_mlperf/tiny_main/benchmark/training/streaming_wakeword/trained_models/strm_ww_int8.tflite" ], "model_n_params": 46883, "model_name": "strm_ww_int8", diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.cproject b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/.cproject similarity index 61% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.cproject rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/.cproject index 7c9a0dbd..ea3f32b6 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.cproject +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/.cproject @@ -1,8 +1,8 @@ - - + + @@ -14,76 +14,75 @@ - - - - - - + + @@ -108,67 +107,67 @@ - - - - + - + - - + - + - - - - - - - - + \ No newline at end of file diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.mxproject b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/.mxproject similarity index 55% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.mxproject rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/.mxproject index e230059c..02c7d722 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.mxproject +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/.mxproject @@ -1,5 +1,5 @@ [PreviousLibFiles] -LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lpuart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lpuart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r5xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_cm35p.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_armv81mml.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/cmsis_armclang_ltm.h; +LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lpuart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lpuart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r5xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_cm35p.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_armv81mml.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/cmsis_armclang_ltm.h; [PreviousUsedCubeIDEFiles] SourceFiles=Core/Src/main.c;Core/Src/stm32l4xx_it.c;Core/Src/stm32l4xx_hal_msp.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Core/Src/system_stm32l4xx.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Core/Src/system_stm32l4xx.c;Middlewares/ST/AI/Lib/NetworkRuntime910_CM4_GCC.a;X-CUBE-AI/App/sww_model_generate_report.txt;;../X-CUBE-AI/App/sww_model_data.c;../X-CUBE-AI/App/sww_model_data_params.c;../X-CUBE-AI/App/sww_model.c;; diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.project b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/.project similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.project rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/.project index 51baeaea..2a1b0ec8 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.project +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/.project @@ -1,6 +1,6 @@ - sww_testing_l4r5zi + sww_ref_l4r5zi diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Inc/arm_math_memory.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Inc/arm_math_memory.h similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Inc/arm_math_memory.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Inc/arm_math_memory.h diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Inc/arm_math_types.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Inc/arm_math_types.h similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Inc/arm_math_types.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Inc/arm_math_types.h diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Inc/feature_extraction.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Inc/feature_extraction.h similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Inc/feature_extraction.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Inc/feature_extraction.h diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Inc/model_test_inputs.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Inc/fixed_data.h similarity index 52% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Inc/model_test_inputs.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Inc/fixed_data.h index f8127de4..ccc87c47 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Inc/model_test_inputs.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Inc/fixed_data.h @@ -17,5 +17,17 @@ extern const int8_t test_input_class2[1200]; extern const float32_t sine_fs16k_7992[2048]; extern const float32_t sine_fs16k_200[2048]; +extern const float32_t hamm_win_1024[1024]; +extern const float32_t hamm_win_512[512]; + +extern const int16_t test_wav_marvin[16000]; +extern const int16_t test_wav_backward[16000]; + +extern const float lin2mel_packed_513x40[987]; +extern const int lin2mel_513x40_filter_starts[40]; +extern const int lin2mel_513x40_filter_lens[40]; + +extern const int16_t test_wav_long[]; +extern const unsigned int test_wav_long_len; #endif /* MODEL_TEST_INPUTS_H_ */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Inc/main.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Inc/main.h similarity index 90% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Inc/main.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Inc/main.h index aedd5a9b..a671b46e 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Inc/main.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Inc/main.h @@ -59,6 +59,10 @@ void Error_Handler(void); /* Private defines -----------------------------------------------------------*/ #define B1_Pin GPIO_PIN_13 #define B1_GPIO_Port GPIOC +#define timestamp_Pin GPIO_PIN_13 +#define timestamp_GPIO_Port GPIOF +#define Processing_Pin GPIO_PIN_9 +#define Processing_GPIO_Port GPIOE #define LD3_Pin GPIO_PIN_14 #define LD3_GPIO_Port GPIOB #define STLK_RX_Pin GPIO_PIN_8 @@ -91,8 +95,8 @@ void Error_Handler(void); #define SWO_GPIO_Port GPIOB #define LD2_Pin GPIO_PIN_7 #define LD2_GPIO_Port GPIOB -#define PIN_WW_DETECTED_Pin GPIO_PIN_8 -#define PIN_WW_DETECTED_GPIO_Port GPIOB +#define WW_DETECTED_Pin GPIO_PIN_8 +#define WW_DETECTED_GPIO_Port GPIOB /* USER CODE BEGIN Private defines */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Inc/stm32l4xx_hal_conf.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Inc/stm32l4xx_hal_conf.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Inc/stm32l4xx_hal_conf.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Inc/stm32l4xx_hal_conf.h index fe199c90..8ed3820e 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Inc/stm32l4xx_hal_conf.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Inc/stm32l4xx_hal_conf.h @@ -77,7 +77,7 @@ /*#define HAL_SPI_MODULE_ENABLED */ /*#define HAL_SRAM_MODULE_ENABLED */ /*#define HAL_SWPMI_MODULE_ENABLED */ -/*#define HAL_TIM_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED /*#define HAL_TSC_MODULE_ENABLED */ #define HAL_UART_MODULE_ENABLED /*#define HAL_USART_MODULE_ENABLED */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Inc/stm32l4xx_it.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Inc/stm32l4xx_it.h similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Inc/stm32l4xx_it.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Inc/stm32l4xx_it.h diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Inc/sww_ref_util.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Inc/sww_ref_util.h new file mode 100644 index 00000000..da904fdf --- /dev/null +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Inc/sww_ref_util.h @@ -0,0 +1,99 @@ +/* + * sww_util.h + * + * Created on: Jan 16, 2025 + * Author: jeremy + */ + +#ifndef INC_SWW_UTIL_H_ +#define INC_SWW_UTIL_H_ + +#include +#include +#include +#include +#include +#include "sww_model.h" + + +#define EE_FW_VERSION "MLPerf Tiny Firmware V0.1.0" + +/* Version 1.0 of the benchmark only supports these models */ +#define EE_MODEL_VERSION_KWS01 "kws01" +#define EE_MODEL_VERSION_VWW01 "vww01" +#define EE_MODEL_VERSION_AD01 "ad01" +#define EE_MODEL_VERSION_IC01 "ic01" +#define EE_MODEL_VERSION_SWW01 "sww01" + + + + + +#define TH_MODEL_VERSION EE_MODEL_VERSION_SWW01 + + +typedef enum { EE_ARG_CLAIMED, EE_ARG_UNCLAIMED } arg_claimed_t; +typedef enum { EE_STATUS_OK = 0, EE_STATUS_ERROR } ee_status_t; + +#define EE_DEVICE_NAME "dut" + +#define EE_CMD_SIZE 1028u +#define EE_CMD_DELIMITER " " +#define EE_CMD_TERMINATOR '%' + +#define EE_CMD_NAME "name" +#define EE_CMD_TIMESTAMP "timestamp" + +#define EE_MSG_READY "m-ready\r\n" +#define EE_MSG_INIT_DONE "m-init-done\r\n" +#define EE_MSG_NAME "m-name-%s-[%s]\r\n" +#define EE_MSG_TIMESTAMP "m-lap-us-%lu\r\n" + +#define EE_ERR_CMD "e-[Unknown command: %s]\r\n" + +#define TH_VENDOR_NAME_STRING "ML Commons" + + +#define SWW_WINLEN_SAMPLES 1024 +#define SWW_WINSTRIDE_SAMPLES 512 +#define SWW_MODEL_INPUT_SIZE 1200 +#define NUM_MEL_FILTERS 40 +#define DETECT_THRESHOLD 115 + +// struct for a log we can write to without the delay of printing to UART +#define LOG_BUFFER_SIZE 8192 +typedef struct { + char buffer[LOG_BUFFER_SIZE]; + size_t current_pos; +} LogBuffer; + + + +typedef enum { + Idle, + FileCapture, // capture a block of a pre-determined size, then stop + Streaming, // continually capture blocks of "window_step" size, then + // extract features and run NN + Stopping // command received to stop streaming detection, but not processed yet + +} i2s_state_t; + + +void print_vals_int16(const int16_t *buffer, uint32_t num_vals); +void print_bytes(const uint8_t *buffer, uint32_t num_bytes); +void print_vals_float(const float *buffer, uint32_t num_vals); +void log_printf(LogBuffer *log, const char *format, ...); + +void process_command(char *full_command); +void ee_serial_callback(char c); +void th_timestamp(void); +void set_processing_pin_high(void); +void set_processing_pin_low(void); +void infer_static_wav(char *cmd_args[]); + +ai_error aiInit(void); +void setup_i2s_buffers(); +void compute_lfbe_f32(const int16_t *pSrc, float32_t *pDst, float32_t *pTmp); +void extract_features_on_chunk(char *cmd_args[]); + +#endif /* INC_SWW_UTIL_H_ */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Src/feature_extraction.c b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Src/feature_extraction.c similarity index 98% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Src/feature_extraction.c rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Src/feature_extraction.c index 2830fe9c..7825390c 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Src/feature_extraction.c +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Src/feature_extraction.c @@ -49,8 +49,8 @@ #include "arm_math.h" #include "arm_const_structs.h" -#include "model_test_inputs.h" -#include "sww_util.h" +#include "fixed_data.h" +#include "sww_ref_util.h" #include diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Src/fixed_data.c b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Src/fixed_data.c new file mode 100644 index 00000000..ce25f91a --- /dev/null +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Src/fixed_data.c @@ -0,0 +1,19789 @@ +/* + * model_test_inputs.c + * + * Created on: Jan 12, 2025 + * Author: jeremy + */ +#include +#include "arm_math.h" + +const int8_t test_input_class0[1200] = { +-125, -128, -128, -124, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -109, -128, -128, -113, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-98, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -119, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -127, -128, -128, -110, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -121, -32, -44, -48, -11, -74, -71, -97, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -105, -87, -9, -32, -16, 19, -36, -5, +-23, 14, -7, -6, -26, -22, -7, 16, 9, -43, -38, -97, -111, -122, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-111, -88, -9, -31, -8, 25, -40, 4, 0, 93, 67, 59, 61, 65, 78, 88, +72, 23, 29, -52, -68, -76, -65, -60, -62, -53, -55, -55, -48, -52, -45, -47, +-43, -45, -47, -46, -48, -51, -53, -56, -128, -102, -37, -70, 3, 24, -30, 25, +39, 98, 55, 69, 102, 91, 79, 32, 25, 12, -2, -28, -26, -21, -13, -4, +0, 0, -5, -12, -20, -15, -4, 0, -8, -28, -36, -32, -32, -35, -27, -31, +-128, -125, -71, -95, 5, 14, -28, 8, 58, 85, 64, 66, 97, 65, 50, 17, +-15, -34, -48, -59, -56, -52, -48, -48, -48, -44, -46, -45, -50, -47, -48, -49, +-53, -57, -60, -60, -61, -60, -58, -58, -118, -115, -92, -105, 11, 16, -27, -13, +57, 69, 82, 77, 88, 36, 30, -12, -45, -92, -109, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-124, -117, -89, -94, 18, 19, -25, -13, 35, 43, 64, 53, 33, -8, -22, -60, +-81, -105, -113, -119, -124, -127, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -93, -115, 9, 11, -23, -13, +18, 33, 45, 32, -19, -60, -72, -95, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128 +}; + +const int8_t test_input_class1[1200] = { +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -126, -114, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -127, -114, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-101, -80, -61, -31, -38, -46, -41, -24, -22, -15, 5, 10, 2, -1, 19, 14, +13, 42, 44, 29, 32, 43, 55, 53, 65, 42, 57, 62, 67, 80, 80, 84, +80, 85, 86, 85, 95, 97, 103, 94, -77, -47, -46, -39, -45, -21, -36, -8, +1, 0, 14, 27, 29, 20, 31, 39, 31, 36, 44, 57, 56, 60, 74, 68, +70, 78, 83, 86, 96, 98, 101, 101, 105, 101, 115, 110, 108, 109, 115, 112, +-65, -75, -65, -46, -28, -17, -29, -10, 6, 5, 18, 23, 18, 17, 27, 36, +41, 48, 50, 52, 55, 68, 74, 67, 65, 75, 86, 87, 93, 95, 97, 102, +102, 100, 107, 111, 110, 114, 116, 114, -70, -51, -31, -39, -36, -21, -12, -12, +0, 3, 2, 14, 19, 28, 38, 36, 25, 39, 42, 52, 59, 60, 72, 71, +71, 83, 85, 82, 83, 94, 99, 102, 102, 107, 113, 107, 106, 112, 118, 121, +-80, -29, 0, -58, -17, -10, -8, -7, -14, 1, 10, 22, 18, 23, 35, 45, +38, 46, 44, 50, 66, 62, 63, 64, 74, 72, 76, 92, 83, 91, 94, 97, +108, 109, 110, 107, 108, 113, 118, 118, -60, -22, 0, -50, -15, -19, -8, -7, +-9, 11, 26, 27, 25, 25, 32, 18, 36, 34, 43, 59, 58, 62, 61, 70, +63, 76, 78, 80, 83, 92, 87, 93, 94, 108, 104, 110, 110, 113, 114, 111, +-58, -21, -3, -34, -27, -27, -11, -8, -2, 4, 19, 30, 24, 20, 26, 43, +48, 40, 50, 61, 60, 66, 62, 60, 55, 71, 78, 89, 92, 92, 94, 101, +102, 103, 105, 109, 107, 111, 109, 113, -74, -34, -31, -53, -38, -25, -16, -12, +6, 13, 3, 18, 12, 26, 32, 40, 38, 32, 52, 57, 62, 56, 61, 64, +68, 61, 77, 85, 88, 85, 95, 96, 93, 99, 100, 109, 117, 113, 119, 125, +-73, -26, -7, -56, -38, -8, 14, 0, 19, 31, 39, 20, 24, 34, 33, 47, +43, 39, 58, 53, 68, 74, 64, 65, 69, 86, 84, 80, 87, 84, 92, 97, +93, 97, 103, 104, 105, 113, 120, 119, -75, -14, 4, -41, -5, -26, -19, -9, +13, 33, 40, 34, 28, 33, 26, 28, 53, 41, 48, 54, 59, 67, 61, 59, +59, 81, 84, 78, 90, 97, 104, 93, 100, 106, 110, 104, 110, 114, 116, 118, +-56, -19, -3, -24, -3, -36, -37, -22, 0, 14, 15, 12, 16, 29, 24, 37, +47, 45, 46, 52, 56, 61, 77, 71, 69, 74, 84, 78, 85, 90, 96, 101, +97, 101, 109, 105, 120, 116, 116, 113, -73, -14, -6, -32, -27, -13, -6, -26, +-15, -4, 3, 10, 10, 25, 22, 26, 41, 45, 51, 61, 54, 51, 65, 74, +76, 78, 85, 87, 90, 94, 86, 88, 100, 103, 114, 112, 114, 114, 117, 117, +-87, -41, -36, -29, -15, -10, -9, -16, 0, 0, 10, 20, 17, 24, 25, 43, +33, 45, 58, 55, 46, 52, 61, 69, 70, 71, 82, 93, 91, 95, 93, 87, +92, 97, 105, 109, 111, 116, 116, 114, -74, -58, -46, -25, -20, -19, -2, -10, +0, 9, -6, 16, 22, 26, 23, 23, 40, 57, 58, 57, 63, 68, 75, 71, +78, 82, 83, 88, 89, 97, 88, 87, 95, 100, 108, 115, 110, 107, 115, 120, +-72, -49, -31, -36, -29, -7, -12, 3, 6, 12, 1, 16, 26, 26, 22, 31, +41, 40, 44, 33, 49, 57, 53, 62, 67, 82, 74, 83, 86, 93, 95, 99, +100, 99, 102, 110, 115, 114, 111, 114, -87, -30, -12, -46, -22, -18, -9, 18, +20, 8, 14, 25, 21, 32, 24, 24, 30, 44, 37, 51, 60, 58, 69, 65, +76, 76, 71, 88, 86, 84, 98, 106, 107, 101, 104, 109, 110, 109, 115, 123, +-89, -40, -40, -33, -23, -34, -8, 2, 4, -6, -1, 6, 18, 23, 32, 35, +33, 52, 59, 44, 56, 58, 59, 62, 66, 72, 80, 89, 91, 97, 93, 89, +97, 101, 108, 106, 108, 110, 113, 113, -71, -16, -10, -23, -14, -16, -1, 4, +14, 11, 10, 13, 12, 18, 31, 32, 32, 48, 59, 53, 52, 60, 73, 71, +72, 82, 75, 77, 89, 91, 90, 96, 98, 103, 103, 110, 111, 112, 117, 114, +-65, -10, -7, -38, -9, -4, -1, 6, 6, 19, 16, 20, 28, 20, 5, 30, +33, 51, 48, 38, 43, 52, 62, 65, 73, 70, 87, 80, 80, 91, 100, 100, +99, 99, 101, 108, 112, 112, 114, 122, -64, -19, -11, -12, -2, -8, -18, -15, +-32, -7, 22, 21, 19, 33, 38, 35, 43, 35, 46, 43, 55, 69, 66, 54, +70, 79, 88, 84, 85, 90, 89, 97, 102, 99, 104, 105, 105, 109, 115, 115, +-54, -40, -25, -36, -19, -13, -21, 0, -8, -9, 21, 19, 18, 27, 14, 32, +47, 52, 52, 51, 47, 61, 67, 67, 69, 81, 90, 86, 86, 86, 87, 88, +96, 101, 105, 110, 110, 110, 114, 118, -65, -66, -68, -50, -22, -13, -26, -14, +3, 5, 5, 19, 16, 23, 38, 30, 39, 44, 45, 55, 55, 61, 61, 65, +64, 77, 79, 75, 77, 83, 97, 106, 102, 109, 110, 107, 102, 107, 120, 119, +-64, -54, -72, -43, -25, -23, -17, -10, -17, -6, 9, 13, 26, 32, 32, 34, +39, 35, 48, 52, 51, 62, 71, 60, 83, 71, 69, 76, 82, 95, 100, 95, +102, 106, 114, 107, 107, 111, 115, 115, -93, -84, -51, -55, -30, -17, -8, 1, +-8, 7, 21, 29, 24, 21, 33, 37, 52, 36, 44, 49, 57, 56, 63, 59, +70, 80, 84, 86, 85, 92, 98, 104, 101, 101, 105, 101, 106, 114, 112, 118, +-85, -76, -51, -47, -33, -19, -17, -7, 3, 7, 19, 15, 15, 26, 21, 34, +44, 48, 36, 51, 64, 58, 68, 65, 79, 83, 73, 86, 93, 87, 91, 97, +104, 114, 111, 108, 107, 119, 123, 115, -87, -73, -67, -51, -47, -27, -3, 1, +2, 4, 17, 20, 25, 17, 26, 19, 44, 49, 38, 47, 62, 64, 70, 69, +71, 80, 82, 86, 96, 86, 91, 98, 102, 104, 112, 112, 114, 121, 114, 115, +-87, -65, -45, -19, -22, -17, -9, -3, -2, 11, 5, 13, 30, 13, 16, 38, +46, 51, 52, 58, 67, 55, 58, 63, 72, 81, 85, 80, 87, 89, 94, 96, +107, 102, 109, 110, 115, 117, 108, 115, -87, -52, -12, 31, 0, -24, 24, 15, +-14, 0, 9, 16, 7, 22, 29, 35, 40, 43, 53, 47, 54, 46, 57, 63, +80, 78, 74, 78, 86, 95, 90, 101, 96, 103, 112, 106, 113, 121, 117, 114 +}; + +const int8_t test_input_class2[1200] = { +-128, -99, -13, -36, -13, 25, -25, -6, -31, -40, -58, -92, -94, -88, -107, -105, +-85, -60, -33, -14, -45, -56, -68, -94, -103, -87, -104, -112, -110, -99, -100, -123, +-124, -123, -126, -125, -85, -76, -96, -120, -128, -98, -18, -48, -11, 15, -57, 0, +-34, -30, -49, -43, -46, -45, -35, -30, -35, -30, -18, -16, -43, -52, -65, -89, +-81, -69, -107, -128, -128, -127, -128, -128, -128, -128, -128, -125, -97, -76, -94, -128, +-128, -99, -18, -47, -13, 13, -40, 8, -27, 2, -23, -15, -20, -14, 6, -10, +-8, -8, -16, -18, -31, -63, -80, -91, -82, -81, -113, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -90, -81, -89, -121, -128, -105, -13, -34, -25, 19, -48, 4, +-12, 32, 14, 1, -20, -12, -1, -5, 13, 27, 25, 29, 13, 1, -29, -63, +-69, -60, -75, -111, -128, -128, -128, -128, -128, -128, -128, -124, -79, -84, -60, -97, +-128, -103, -16, -37, -27, 5, -35, 8, -4, 49, 24, 20, -11, -7, -12, -13, +7, 26, 40, 13, 4, 3, -7, -49, -63, -50, -35, -60, -94, -122, -128, -128, +-128, -128, -128, -101, -64, -74, -67, -89, -128, -128, -58, -57, -57, -65, -50, -47, +-45, -27, -62, -64, -82, -91, -81, -75, -51, -51, -59, -86, -108, -103, -107, -120, +-128, -128, -127, -116, -125, -128, -128, -128, -128, -128, -128, -128, -116, -114, -128, -128, +-128, -128, -123, -128, -97, -47, -15, -12, -27, -42, -48, -40, -30, -14, -22, -55, +-4, 2, -11, -5, 5, 0, -18, -11, -29, 7, -11, -10, -12, -9, -26, -30, +-27, -14, -21, -24, -22, -31, -35, -45, -128, -128, -101, -65, -61, -73, -53, -52, +-60, -60, -60, -80, -87, -75, -73, -70, -67, -59, -53, -59, -45, -56, -65, -77, +-67, -45, -29, -45, -43, -18, -43, -40, -57, -55, -51, -64, -63, -58, -83, -91, +-128, -128, -36, 15, 3, -23, 31, 32, 20, 55, 40, 39, 6, 12, 22, 29, +-5, -21, -35, -54, -70, -75, -78, -82, -71, -43, -18, -37, -55, -26, -40, -94, +-94, -80, -32, -14, -27, -90, -101, -58, -128, -128, -25, 3, -63, -16, 32, -34, +22, 34, 38, 75, 29, 48, 52, 59, 65, 44, 22, 1, -8, -22, -28, -37, +-31, -4, 27, -4, -30, -10, -18, -61, -62, -48, -25, 12, -2, -46, -57, -69, +-128, -100, -22, -4, -70, -6, 18, -36, 8, 0, 43, 52, 57, 61, 58, 50, +68, 66, 50, 16, 3, -3, -20, -23, -6, 26, 38, 3, -21, -19, -37, -31, +-16, 0, 0, -10, -24, -29, -56, -93, -107, -22, -15, -9, 3, 2, 16, 27, +45, 78, 80, 69, 44, 50, 58, 62, 46, 55, 44, 24, 9, 8, -3, 7, +5, 20, 36, 14, -9, -7, -29, -26, -8, 13, 11, -2, -14, -20, -35, -52, +-128, -33, -25, 0, 0, -8, -13, 17, 31, 47, 83, 86, 70, 49, 51, 65, +79, 54, 33, 29, 5, -1, 2, 9, 16, 14, 33, 9, 11, 0, 0, -9, +-12, 5, 18, 11, 1, -17, -23, -24, -99, -43, -51, -18, -12, -6, -21, -2, +28, 40, 63, 101, 64, 61, 57, 42, 62, 56, 53, 41, 41, 15, 0, 16, +5, 18, 27, -6, -4, -15, -14, -7, -5, 15, 25, 3, -8, -24, -35, -36, +-128, -36, -47, -6, -23, -3, -15, -1, 32, 50, 85, 86, 59, 57, 31, 6, +6, 24, 39, 40, 36, 36, -2, 10, 2, 5, 15, -7, -4, 2, -3, -19, +-5, 18, 14, -6, -11, -13, -48, -53, -105, -28, -31, 7, -21, -16, 2, 30, +65, 76, 71, 29, 11, 2, -8, -20, -10, -12, -10, 5, 25, 26, 8, -6, +12, 17, 14, 0, -4, 6, -4, -35, -1, 18, -4, -27, -12, -3, -33, -82, +-79, -26, -11, 10, -34, -5, 21, 49, 64, 50, 8, 6, -23, -32, -22, -26, +-20, -42, -30, -33, -13, 15, 13, 5, 6, 20, 8, -6, -6, 0, -14, -46, +-17, 14, -7, -41, -35, -45, -54, -65, -82, -57, -25, -27, -52, 6, 27, 29, +17, -15, -25, -14, -34, -38, -49, -49, -40, -53, -56, -60, -54, -20, 2, 9, +16, 15, -5, -20, -4, -6, -18, -44, -29, -10, -38, -57, -56, -92, -93, -108, +-90, -65, -39, -56, -33, -6, -2, -13, -32, -51, -44, -29, -62, -75, -65, -65, +-58, -67, -76, -67, -56, -40, -35, -23, -38, -43, -61, -65, -50, -55, -75, -85, +-60, -66, -87, -91, -82, -86, -114, -128, -106, -78, -66, -57, -80, -60, -47, -37, +-62, -84, -62, -50, -72, -78, -85, -79, -67, -76, -66, -79, -73, -72, -70, -83, +-60, -60, -55, -66, -55, -61, -63, -66, -47, -48, -57, -53, -50, -62, -90, -128, +-128, -118, -117, -128, -117, -97, -81, -66, -71, -73, -74, -79, -74, -65, -67, -66, +-60, -48, -56, -51, -40, -37, -47, -49, -40, -36, -33, -27, -16, -19, -19, -29, +-26, -26, -40, -32, -26, -35, -52, -107, -128, -106, -125, -128, -128, -128, -107, -100, +-117, -104, -111, -81, -96, -87, -75, -58, -37, -31, -36, -30, -32, -32, -49, -38, +-14, -10, -28, -25, -18, -22, -22, -28, -27, -21, -24, -28, -15, -13, -35, -75, +-128, -128, -128, -128, -128, -128, -126, -124, -110, -109, -111, -70, -73, -57, -59, -59, +-42, -40, -28, -33, -35, -37, -48, -26, -6, -1, -12, -4, -2, -7, -13, -15, +-3, -8, -8, -10, -6, 1, -20, -65, -128, -128, -128, -128, -128, -128, -128, -110, +-90, -93, -85, -82, -68, -78, -83, -42, -29, -35, -32, -28, -18, -24, -30, -10, +-3, -2, -6, 1, 0, 2, -7, -16, 3, 4, -4, -8, -6, 5, -19, -71, +-128, -128, -128, -128, -128, -128, -128, -90, -72, -73, -80, -82, -88, -68, -57, -59, +-36, -33, -20, -37, -39, -33, -42, -15, -8, -13, -21, -13, -4, -8, -18, -24, +-1, -7, -7, -7, -4, -4, -25, -83, -128, -128, -128, -128, -128, -128, -128, -77, +-64, -98, -90, -65, -82, -108, -81, -56, -25, -34, -34, -36, -54, -51, -55, -40, +-23, -31, -35, -26, -29, -29, -35, -34, -12, -15, -17, -17, -18, -14, -40, -93, +-128, -128, -128, -128, -128, -128, -128, -128, -118, -123, -116, -107, -121, -127, -87, -62, +-54, -57, -64, -69, -75, -62, -75, -65, -44, -54, -71, -41, -25, -57, -58, -50, +-46, -39, -55, -50, -56, -56, -79, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -121, -128, -128, -126, -88, -86, -97, -91, -110, -122, -109, -124, -109, +-104, -92, -89, -87, -67, -89, -102, -98, -88, -76, -93, -101, -105, -104, -127, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-121, -128, -128, -128, -128, -128, -128, -128, -128, -119, -125, -120, -104, -111, -128, -128, +-127, -122, -128, -122, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, +-128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128 +}; + + + +const float32_t sine_fs16k_7992[2048] = { + 0.0, 0.0, 0.003142, 0.0, -0.006283, 0.0, 0.009425, 0.0, + -0.01257, 0.0, 0.01571, 0.0, -0.01885, 0.0, 0.02199, 0.0, + -0.02513, 0.0, 0.02827, 0.0, -0.03141, 0.0, 0.03455, 0.0, + -0.03769, 0.0, 0.04083, 0.0, -0.04397, 0.0, 0.04711, 0.0, + -0.05024, 0.0, 0.05338, 0.0, -0.05652, 0.0, 0.05965, 0.0, + -0.06279, 0.0, 0.06593, 0.0, -0.06906, 0.0, 0.07219, 0.0, + -0.07533, 0.0, 0.07846, 0.0, -0.08159, 0.0, 0.08472, 0.0, + -0.08785, 0.0, 0.09098, 0.0, -0.09411, 0.0, 0.09724, 0.0, + -0.1004, 0.0, 0.1035, 0.0, -0.1066, 0.0, 0.1097, 0.0, + -0.1129, 0.0, 0.116, 0.0, -0.1191, 0.0, 0.1222, 0.0, + -0.1253, 0.0, 0.1284, 0.0, -0.1316, 0.0, 0.1347, 0.0, + -0.1378, 0.0, 0.1409, 0.0, -0.144, 0.0, 0.1471, 0.0, + -0.1502, 0.0, 0.1533, 0.0, -0.1564, 0.0, 0.1595, 0.0, + -0.1626, 0.0, 0.1657, 0.0, -0.1688, 0.0, 0.1719, 0.0, + -0.175, 0.0, 0.1781, 0.0, -0.1812, 0.0, 0.1843, 0.0, + -0.1874, 0.0, 0.1905, 0.0, -0.1935, 0.0, 0.1966, 0.0, + -0.1997, 0.0, 0.2028, 0.0, -0.2059, 0.0, 0.2089, 0.0, + -0.212, 0.0, 0.2151, 0.0, -0.2181, 0.0, 0.2212, 0.0, + -0.2243, 0.0, 0.2273, 0.0, -0.2304, 0.0, 0.2334, 0.0, + -0.2365, 0.0, 0.2396, 0.0, -0.2426, 0.0, 0.2456, 0.0, + -0.2487, 0.0, 0.2517, 0.0, -0.2548, 0.0, 0.2578, 0.0, + -0.2608, 0.0, 0.2639, 0.0, -0.2669, 0.0, 0.2699, 0.0, + -0.273, 0.0, 0.276, 0.0, -0.279, 0.0, 0.282, 0.0, + -0.285, 0.0, 0.288, 0.0, -0.291, 0.0, 0.294, 0.0, + -0.297, 0.0, 0.3, 0.0, -0.303, 0.0, 0.306, 0.0, + -0.309, 0.0, 0.312, 0.0, -0.315, 0.0, 0.318, 0.0, + -0.3209, 0.0, 0.3239, 0.0, -0.3269, 0.0, 0.3299, 0.0, + -0.3328, 0.0, 0.3358, 0.0, -0.3387, 0.0, 0.3417, 0.0, + -0.3446, 0.0, 0.3476, 0.0, -0.3505, 0.0, 0.3535, 0.0, + -0.3564, 0.0, 0.3593, 0.0, -0.3623, 0.0, 0.3652, 0.0, + -0.3681, 0.0, 0.371, 0.0, -0.374, 0.0, 0.3769, 0.0, + -0.3798, 0.0, 0.3827, 0.0, -0.3856, 0.0, 0.3885, 0.0, + -0.3914, 0.0, 0.3943, 0.0, -0.3971, 0.0, 0.4, 0.0, + -0.4029, 0.0, 0.4058, 0.0, -0.4086, 0.0, 0.4115, 0.0, + -0.4144, 0.0, 0.4172, 0.0, -0.4201, 0.0, 0.4229, 0.0, + -0.4258, 0.0, 0.4286, 0.0, -0.4315, 0.0, 0.4343, 0.0, + -0.4371, 0.0, 0.4399, 0.0, -0.4428, 0.0, 0.4456, 0.0, + -0.4484, 0.0, 0.4512, 0.0, -0.454, 0.0, 0.4568, 0.0, + -0.4596, 0.0, 0.4624, 0.0, -0.4652, 0.0, 0.4679, 0.0, + -0.4707, 0.0, 0.4735, 0.0, -0.4762, 0.0, 0.479, 0.0, + -0.4818, 0.0, 0.4845, 0.0, -0.4873, 0.0, 0.49, 0.0, + -0.4927, 0.0, 0.4955, 0.0, -0.4982, 0.0, 0.5009, 0.0, + -0.5036, 0.0, 0.5063, 0.0, -0.509, 0.0, 0.5117, 0.0, + -0.5144, 0.0, 0.5171, 0.0, -0.5198, 0.0, 0.5225, 0.0, + -0.5252, 0.0, 0.5278, 0.0, -0.5305, 0.0, 0.5332, 0.0, + -0.5358, 0.0, 0.5385, 0.0, -0.5411, 0.0, 0.5438, 0.0, + -0.5464, 0.0, 0.549, 0.0, -0.5516, 0.0, 0.5543, 0.0, + -0.5569, 0.0, 0.5595, 0.0, -0.5621, 0.0, 0.5647, 0.0, + -0.5673, 0.0, 0.5699, 0.0, -0.5724, 0.0, 0.575, 0.0, + -0.5776, 0.0, 0.5801, 0.0, -0.5827, 0.0, 0.5852, 0.0, + -0.5878, 0.0, 0.5903, 0.0, -0.5929, 0.0, 0.5954, 0.0, + -0.5979, 0.0, 0.6004, 0.0, -0.6029, 0.0, 0.6054, 0.0, + -0.6079, 0.0, 0.6104, 0.0, -0.6129, 0.0, 0.6154, 0.0, + -0.6179, 0.0, 0.6203, 0.0, -0.6228, 0.0, 0.6252, 0.0, + -0.6277, 0.0, 0.6301, 0.0, -0.6326, 0.0, 0.635, 0.0, + -0.6374, 0.0, 0.6398, 0.0, -0.6423, 0.0, 0.6447, 0.0, + -0.6471, 0.0, 0.6494, 0.0, -0.6518, 0.0, 0.6542, 0.0, + -0.6566, 0.0, 0.659, 0.0, -0.6613, 0.0, 0.6637, 0.0, + -0.666, 0.0, 0.6684, 0.0, -0.6707, 0.0, 0.673, 0.0, + -0.6753, 0.0, 0.6776, 0.0, -0.68, 0.0, 0.6823, 0.0, + -0.6845, 0.0, 0.6868, 0.0, -0.6891, 0.0, 0.6914, 0.0, + -0.6937, 0.0, 0.6959, 0.0, -0.6982, 0.0, 0.7004, 0.0, + -0.7026, 0.0, 0.7049, 0.0, -0.7071, 0.0, 0.7093, 0.0, + -0.7115, 0.0, 0.7137, 0.0, -0.7159, 0.0, 0.7181, 0.0, + -0.7203, 0.0, 0.7225, 0.0, -0.7247, 0.0, 0.7268, 0.0, + -0.729, 0.0, 0.7311, 0.0, -0.7333, 0.0, 0.7354, 0.0, + -0.7375, 0.0, 0.7396, 0.0, -0.7417, 0.0, 0.7438, 0.0, + -0.7459, 0.0, 0.748, 0.0, -0.7501, 0.0, 0.7522, 0.0, + -0.7543, 0.0, 0.7563, 0.0, -0.7584, 0.0, 0.7604, 0.0, + -0.7624, 0.0, 0.7645, 0.0, -0.7665, 0.0, 0.7685, 0.0, + -0.7705, 0.0, 0.7725, 0.0, -0.7745, 0.0, 0.7765, 0.0, + -0.7785, 0.0, 0.7804, 0.0, -0.7824, 0.0, 0.7843, 0.0, + -0.7863, 0.0, 0.7882, 0.0, -0.7902, 0.0, 0.7921, 0.0, + -0.794, 0.0, 0.7959, 0.0, -0.7978, 0.0, 0.7997, 0.0, + -0.8016, 0.0, 0.8034, 0.0, -0.8053, 0.0, 0.8072, 0.0, + -0.809, 0.0, 0.8109, 0.0, -0.8127, 0.0, 0.8145, 0.0, + -0.8163, 0.0, 0.8181, 0.0, -0.82, 0.0, 0.8217, 0.0, + -0.8235, 0.0, 0.8253, 0.0, -0.8271, 0.0, 0.8288, 0.0, + -0.8306, 0.0, 0.8323, 0.0, -0.8341, 0.0, 0.8358, 0.0, + -0.8375, 0.0, 0.8392, 0.0, -0.8409, 0.0, 0.8426, 0.0, + -0.8443, 0.0, 0.846, 0.0, -0.8477, 0.0, 0.8493, 0.0, + -0.851, 0.0, 0.8526, 0.0, -0.8543, 0.0, 0.8559, 0.0, + -0.8575, 0.0, 0.8591, 0.0, -0.8607, 0.0, 0.8623, 0.0, + -0.8639, 0.0, 0.8655, 0.0, -0.8671, 0.0, 0.8686, 0.0, + -0.8702, 0.0, 0.8717, 0.0, -0.8733, 0.0, 0.8748, 0.0, + -0.8763, 0.0, 0.8778, 0.0, -0.8793, 0.0, 0.8808, 0.0, + -0.8823, 0.0, 0.8838, 0.0, -0.8852, 0.0, 0.8867, 0.0, + -0.8881, 0.0, 0.8896, 0.0, -0.891, 0.0, 0.8924, 0.0, + -0.8938, 0.0, 0.8952, 0.0, -0.8966, 0.0, 0.898, 0.0, + -0.8994, 0.0, 0.9008, 0.0, -0.9021, 0.0, 0.9035, 0.0, + -0.9048, 0.0, 0.9062, 0.0, -0.9075, 0.0, 0.9088, 0.0, + -0.9101, 0.0, 0.9114, 0.0, -0.9127, 0.0, 0.914, 0.0, + -0.9152, 0.0, 0.9165, 0.0, -0.9178, 0.0, 0.919, 0.0, + -0.9202, 0.0, 0.9215, 0.0, -0.9227, 0.0, 0.9239, 0.0, + -0.9251, 0.0, 0.9263, 0.0, -0.9274, 0.0, 0.9286, 0.0, + -0.9298, 0.0, 0.9309, 0.0, -0.9321, 0.0, 0.9332, 0.0, + -0.9343, 0.0, 0.9354, 0.0, -0.9365, 0.0, 0.9376, 0.0, + -0.9387, 0.0, 0.9398, 0.0, -0.9409, 0.0, 0.9419, 0.0, + -0.943, 0.0, 0.944, 0.0, -0.9451, 0.0, 0.9461, 0.0, + -0.9471, 0.0, 0.9481, 0.0, -0.9491, 0.0, 0.9501, 0.0, + -0.9511, 0.0, 0.952, 0.0, -0.953, 0.0, 0.9539, 0.0, + -0.9549, 0.0, 0.9558, 0.0, -0.9567, 0.0, 0.9576, 0.0, + -0.9585, 0.0, 0.9594, 0.0, -0.9603, 0.0, 0.9612, 0.0, + -0.962, 0.0, 0.9629, 0.0, -0.9637, 0.0, 0.9646, 0.0, + -0.9654, 0.0, 0.9662, 0.0, -0.967, 0.0, 0.9678, 0.0, + -0.9686, 0.0, 0.9694, 0.0, -0.9701, 0.0, 0.9709, 0.0, + -0.9716, 0.0, 0.9724, 0.0, -0.9731, 0.0, 0.9738, 0.0, + -0.9745, 0.0, 0.9752, 0.0, -0.9759, 0.0, 0.9766, 0.0, + -0.9773, 0.0, 0.9779, 0.0, -0.9786, 0.0, 0.9792, 0.0, + -0.9799, 0.0, 0.9805, 0.0, -0.9811, 0.0, 0.9817, 0.0, + -0.9823, 0.0, 0.9829, 0.0, -0.9834, 0.0, 0.984, 0.0, + -0.9846, 0.0, 0.9851, 0.0, -0.9856, 0.0, 0.9862, 0.0, + -0.9867, 0.0, 0.9872, 0.0, -0.9877, 0.0, 0.9882, 0.0, + -0.9887, 0.0, 0.9891, 0.0, -0.9896, 0.0, 0.99, 0.0, + -0.9905, 0.0, 0.9909, 0.0, -0.9913, 0.0, 0.9917, 0.0, + -0.9921, 0.0, 0.9925, 0.0, -0.9929, 0.0, 0.9933, 0.0, + -0.9936, 0.0, 0.994, 0.0, -0.9943, 0.0, 0.9946, 0.0, + -0.995, 0.0, 0.9953, 0.0, -0.9956, 0.0, 0.9959, 0.0, + -0.9961, 0.0, 0.9964, 0.0, -0.9967, 0.0, 0.9969, 0.0, + -0.9972, 0.0, 0.9974, 0.0, -0.9976, 0.0, 0.9978, 0.0, + -0.998, 0.0, 0.9982, 0.0, -0.9984, 0.0, 0.9986, 0.0, + -0.9987, 0.0, 0.9989, 0.0, -0.999, 0.0, 0.9992, 0.0, + -0.9993, 0.0, 0.9994, 0.0, -0.9995, 0.0, 0.9996, 0.0, + -0.9997, 0.0, 0.9998, 0.0, -0.9998, 0.0, 0.9999, 0.0, + -0.9999, 0.0, 1.0, 0.0, -1.0, 0.0, 1.0, 0.0, + -1.0, 0.0, 1.0, 0.0, -1.0, 0.0, 1.0, 0.0, + -0.9999, 0.0, 0.9999, 0.0, -0.9998, 0.0, 0.9998, 0.0, + -0.9997, 0.0, 0.9996, 0.0, -0.9995, 0.0, 0.9994, 0.0, + -0.9993, 0.0, 0.9992, 0.0, -0.999, 0.0, 0.9989, 0.0, + -0.9987, 0.0, 0.9986, 0.0, -0.9984, 0.0, 0.9982, 0.0, + -0.998, 0.0, 0.9978, 0.0, -0.9976, 0.0, 0.9974, 0.0, + -0.9972, 0.0, 0.9969, 0.0, -0.9967, 0.0, 0.9964, 0.0, + -0.9961, 0.0, 0.9959, 0.0, -0.9956, 0.0, 0.9953, 0.0, + -0.995, 0.0, 0.9946, 0.0, -0.9943, 0.0, 0.994, 0.0, + -0.9936, 0.0, 0.9933, 0.0, -0.9929, 0.0, 0.9925, 0.0, + -0.9921, 0.0, 0.9917, 0.0, -0.9913, 0.0, 0.9909, 0.0, + -0.9905, 0.0, 0.99, 0.0, -0.9896, 0.0, 0.9891, 0.0, + -0.9887, 0.0, 0.9882, 0.0, -0.9877, 0.0, 0.9872, 0.0, + -0.9867, 0.0, 0.9862, 0.0, -0.9856, 0.0, 0.9851, 0.0, + -0.9846, 0.0, 0.984, 0.0, -0.9834, 0.0, 0.9829, 0.0, + -0.9823, 0.0, 0.9817, 0.0, -0.9811, 0.0, 0.9805, 0.0, + -0.9799, 0.0, 0.9792, 0.0, -0.9786, 0.0, 0.9779, 0.0, + -0.9773, 0.0, 0.9766, 0.0, -0.9759, 0.0, 0.9752, 0.0, + -0.9745, 0.0, 0.9738, 0.0, -0.9731, 0.0, 0.9724, 0.0, + -0.9716, 0.0, 0.9709, 0.0, -0.9701, 0.0, 0.9694, 0.0, + -0.9686, 0.0, 0.9678, 0.0, -0.967, 0.0, 0.9662, 0.0, + -0.9654, 0.0, 0.9646, 0.0, -0.9637, 0.0, 0.9629, 0.0, + -0.962, 0.0, 0.9612, 0.0, -0.9603, 0.0, 0.9594, 0.0, + -0.9585, 0.0, 0.9576, 0.0, -0.9567, 0.0, 0.9558, 0.0, + -0.9549, 0.0, 0.9539, 0.0, -0.953, 0.0, 0.952, 0.0, + -0.9511, 0.0, 0.9501, 0.0, -0.9491, 0.0, 0.9481, 0.0, + -0.9471, 0.0, 0.9461, 0.0, -0.9451, 0.0, 0.944, 0.0, + -0.943, 0.0, 0.9419, 0.0, -0.9409, 0.0, 0.9398, 0.0, + -0.9387, 0.0, 0.9376, 0.0, -0.9365, 0.0, 0.9354, 0.0, + -0.9343, 0.0, 0.9332, 0.0, -0.9321, 0.0, 0.9309, 0.0, + -0.9298, 0.0, 0.9286, 0.0, -0.9274, 0.0, 0.9263, 0.0, + -0.9251, 0.0, 0.9239, 0.0, -0.9227, 0.0, 0.9215, 0.0, + -0.9202, 0.0, 0.919, 0.0, -0.9178, 0.0, 0.9165, 0.0, + -0.9152, 0.0, 0.914, 0.0, -0.9127, 0.0, 0.9114, 0.0, + -0.9101, 0.0, 0.9088, 0.0, -0.9075, 0.0, 0.9062, 0.0, + -0.9048, 0.0, 0.9035, 0.0, -0.9021, 0.0, 0.9008, 0.0, + -0.8994, 0.0, 0.898, 0.0, -0.8966, 0.0, 0.8952, 0.0, + -0.8938, 0.0, 0.8924, 0.0, -0.891, 0.0, 0.8896, 0.0, + -0.8881, 0.0, 0.8867, 0.0, -0.8852, 0.0, 0.8838, 0.0, + -0.8823, 0.0, 0.8808, 0.0, -0.8793, 0.0, 0.8778, 0.0, + -0.8763, 0.0, 0.8748, 0.0, -0.8733, 0.0, 0.8717, 0.0, + -0.8702, 0.0, 0.8686, 0.0, -0.8671, 0.0, 0.8655, 0.0, + -0.8639, 0.0, 0.8623, 0.0, -0.8607, 0.0, 0.8591, 0.0, + -0.8575, 0.0, 0.8559, 0.0, -0.8543, 0.0, 0.8526, 0.0, + -0.851, 0.0, 0.8493, 0.0, -0.8477, 0.0, 0.846, 0.0, + -0.8443, 0.0, 0.8426, 0.0, -0.8409, 0.0, 0.8392, 0.0, + -0.8375, 0.0, 0.8358, 0.0, -0.8341, 0.0, 0.8323, 0.0, + -0.8306, 0.0, 0.8288, 0.0, -0.8271, 0.0, 0.8253, 0.0, + -0.8235, 0.0, 0.8217, 0.0, -0.82, 0.0, 0.8181, 0.0, + -0.8163, 0.0, 0.8145, 0.0, -0.8127, 0.0, 0.8109, 0.0, + -0.809, 0.0, 0.8072, 0.0, -0.8053, 0.0, 0.8034, 0.0, + -0.8016, 0.0, 0.7997, 0.0, -0.7978, 0.0, 0.7959, 0.0, + -0.794, 0.0, 0.7921, 0.0, -0.7902, 0.0, 0.7882, 0.0, + -0.7863, 0.0, 0.7843, 0.0, -0.7824, 0.0, 0.7804, 0.0, + -0.7785, 0.0, 0.7765, 0.0, -0.7745, 0.0, 0.7725, 0.0, + -0.7705, 0.0, 0.7685, 0.0, -0.7665, 0.0, 0.7645, 0.0, + -0.7624, 0.0, 0.7604, 0.0, -0.7584, 0.0, 0.7563, 0.0, + -0.7543, 0.0, 0.7522, 0.0, -0.7501, 0.0, 0.748, 0.0, + -0.7459, 0.0, 0.7438, 0.0, -0.7417, 0.0, 0.7396, 0.0, + -0.7375, 0.0, 0.7354, 0.0, -0.7333, 0.0, 0.7311, 0.0, + -0.729, 0.0, 0.7268, 0.0, -0.7247, 0.0, 0.7225, 0.0, + -0.7203, 0.0, 0.7181, 0.0, -0.7159, 0.0, 0.7137, 0.0, + -0.7115, 0.0, 0.7093, 0.0, -0.7071, 0.0, 0.7049, 0.0, + -0.7026, 0.0, 0.7004, 0.0, -0.6982, 0.0, 0.6959, 0.0, + -0.6937, 0.0, 0.6914, 0.0, -0.6891, 0.0, 0.6868, 0.0, + -0.6845, 0.0, 0.6823, 0.0, -0.68, 0.0, 0.6776, 0.0, + -0.6753, 0.0, 0.673, 0.0, -0.6707, 0.0, 0.6684, 0.0, + -0.666, 0.0, 0.6637, 0.0, -0.6613, 0.0, 0.659, 0.0, + -0.6566, 0.0, 0.6542, 0.0, -0.6518, 0.0, 0.6494, 0.0, + -0.6471, 0.0, 0.6447, 0.0, -0.6423, 0.0, 0.6398, 0.0, + -0.6374, 0.0, 0.635, 0.0, -0.6326, 0.0, 0.6301, 0.0, + -0.6277, 0.0, 0.6252, 0.0, -0.6228, 0.0, 0.6203, 0.0, + -0.6179, 0.0, 0.6154, 0.0, -0.6129, 0.0, 0.6104, 0.0, + -0.6079, 0.0, 0.6054, 0.0, -0.6029, 0.0, 0.6004, 0.0, + -0.5979, 0.0, 0.5954, 0.0, -0.5929, 0.0, 0.5903, 0.0, + -0.5878, 0.0, 0.5852, 0.0, -0.5827, 0.0, 0.5801, 0.0, + -0.5776, 0.0, 0.575, 0.0, -0.5724, 0.0, 0.5699, 0.0, + -0.5673, 0.0, 0.5647, 0.0, -0.5621, 0.0, 0.5595, 0.0, + -0.5569, 0.0, 0.5543, 0.0, -0.5516, 0.0, 0.549, 0.0, + -0.5464, 0.0, 0.5438, 0.0, -0.5411, 0.0, 0.5385, 0.0, + -0.5358, 0.0, 0.5332, 0.0, -0.5305, 0.0, 0.5278, 0.0, + -0.5252, 0.0, 0.5225, 0.0, -0.5198, 0.0, 0.5171, 0.0, + -0.5144, 0.0, 0.5117, 0.0, -0.509, 0.0, 0.5063, 0.0, + -0.5036, 0.0, 0.5009, 0.0, -0.4982, 0.0, 0.4955, 0.0, + -0.4927, 0.0, 0.49, 0.0, -0.4873, 0.0, 0.4845, 0.0, + -0.4818, 0.0, 0.479, 0.0, -0.4762, 0.0, 0.4735, 0.0, + -0.4707, 0.0, 0.4679, 0.0, -0.4652, 0.0, 0.4624, 0.0, + -0.4596, 0.0, 0.4568, 0.0, -0.454, 0.0, 0.4512, 0.0, + -0.4484, 0.0, 0.4456, 0.0, -0.4428, 0.0, 0.4399, 0.0, + -0.4371, 0.0, 0.4343, 0.0, -0.4315, 0.0, 0.4286, 0.0, + -0.4258, 0.0, 0.4229, 0.0, -0.4201, 0.0, 0.4172, 0.0, + -0.4144, 0.0, 0.4115, 0.0, -0.4086, 0.0, 0.4058, 0.0, + -0.4029, 0.0, 0.4, 0.0, -0.3971, 0.0, 0.3943, 0.0, + -0.3914, 0.0, 0.3885, 0.0, -0.3856, 0.0, 0.3827, 0.0, + -0.3798, 0.0, 0.3769, 0.0, -0.374, 0.0, 0.371, 0.0, + -0.3681, 0.0, 0.3652, 0.0, -0.3623, 0.0, 0.3593, 0.0, + -0.3564, 0.0, 0.3535, 0.0, -0.3505, 0.0, 0.3476, 0.0, + -0.3446, 0.0, 0.3417, 0.0, -0.3387, 0.0, 0.3358, 0.0, + -0.3328, 0.0, 0.3299, 0.0, -0.3269, 0.0, 0.3239, 0.0, + -0.3209, 0.0, 0.318, 0.0, -0.315, 0.0, 0.312, 0.0, + -0.309, 0.0, 0.306, 0.0, -0.303, 0.0, 0.3, 0.0, + -0.297, 0.0, 0.294, 0.0, -0.291, 0.0, 0.288, 0.0, + -0.285, 0.0, 0.282, 0.0, -0.279, 0.0, 0.276, 0.0, + -0.273, 0.0, 0.2699, 0.0, -0.2669, 0.0, 0.2639, 0.0, + -0.2608, 0.0, 0.2578, 0.0, -0.2548, 0.0, 0.2517, 0.0, + -0.2487, 0.0, 0.2456, 0.0, -0.2426, 0.0, 0.2396, 0.0, + -0.2365, 0.0, 0.2334, 0.0, -0.2304, 0.0, 0.2273, 0.0, + -0.2243, 0.0, 0.2212, 0.0, -0.2181, 0.0, 0.2151, 0.0, + -0.212, 0.0, 0.2089, 0.0, -0.2059, 0.0, 0.2028, 0.0, + -0.1997, 0.0, 0.1966, 0.0, -0.1935, 0.0, 0.1905, 0.0, + -0.1874, 0.0, 0.1843, 0.0, -0.1812, 0.0, 0.1781, 0.0, + -0.175, 0.0, 0.1719, 0.0, -0.1688, 0.0, 0.1657, 0.0, + -0.1626, 0.0, 0.1595, 0.0, -0.1564, 0.0, 0.1533, 0.0, + -0.1502, 0.0, 0.1471, 0.0, -0.144, 0.0, 0.1409, 0.0, + -0.1378, 0.0, 0.1347, 0.0, -0.1316, 0.0, 0.1284, 0.0, + -0.1253, 0.0, 0.1222, 0.0, -0.1191, 0.0, 0.116, 0.0, + -0.1129, 0.0, 0.1097, 0.0, -0.1066, 0.0, 0.1035, 0.0, + -0.1004, 0.0, 0.09724, 0.0, -0.09411, 0.0, 0.09098, 0.0, + -0.08785, 0.0, 0.08472, 0.0, -0.08159, 0.0, 0.07846, 0.0, + -0.07533, 0.0, 0.07219, 0.0, -0.06906, 0.0, 0.06593, 0.0, + -0.06279, 0.0, 0.05965, 0.0, -0.05652, 0.0, 0.05338, 0.0, + -0.05024, 0.0, 0.04711, 0.0, -0.04397, 0.0, 0.04083, 0.0, + -0.03769, 0.0, 0.03455, 0.0, -0.03141, 0.0, 0.02827, 0.0, + -0.02513, 0.0, 0.02199, 0.0, -0.01885, 0.0, 0.01571, 0.0, + -0.01257, 0.0, 0.009425, 0.0, -0.006283, 0.0, 0.003142, 0.0, + 1.969e-13, 0.0, -0.003142, 0.0, 0.006283, 0.0, -0.009425, 0.0, + 0.01257, 0.0, -0.01571, 0.0, 0.01885, 0.0, -0.02199, 0.0, + 0.02513, 0.0, -0.02827, 0.0, 0.03141, 0.0, -0.03455, 0.0, + 0.03769, 0.0, -0.04083, 0.0, 0.04397, 0.0, -0.04711, 0.0, + 0.05024, 0.0, -0.05338, 0.0, 0.05652, 0.0, -0.05965, 0.0, + 0.06279, 0.0, -0.06593, 0.0, 0.06906, 0.0, -0.07219, 0.0 + }; + + + +const float32_t sine_fs16k_200[2048] = { + 0.0, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, + 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, + 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, + 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, + 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, + 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, + 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, + 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, + 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, + 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, + 1.225e-16, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, + -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, + -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, + -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, + -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, + -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, + -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, + -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, + -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, + -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, + -2.449e-16, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, + 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, + 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, + 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, + 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, + 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, + 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, + 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, + 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, + 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, + 3.674e-16, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, + -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, + -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, + -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, + -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, + -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, + -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, + -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, + -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, + -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, + -4.899e-16, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, + 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, + 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, + 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, + 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, + 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, + 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, + 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, + 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, + 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, + -1.164e-15, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, + -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, + -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, + -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, + -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, + -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, + -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, + -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, + -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, + -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, + -7.348e-16, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, + 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, + 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, + 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, + 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, + 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, + 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, + 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, + 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, + 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, + -2.695e-15, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, + -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, + -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, + -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, + -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, + -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, + -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, + -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, + -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, + -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, + -9.797e-16, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, + 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, + 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, + 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, + 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, + 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, + 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, + 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, + 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, + 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, + 1.102e-15, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, + -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, + -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, + -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, + -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, + -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, + -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, + -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, + -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, + -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, + 2.328e-15, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, + 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, + 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, + 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, + 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, + 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, + 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, + 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, + 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, + 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, + -2.206e-15, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, + -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, + -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, + -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, + -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, + -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, + -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, + -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, + -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, + -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, + -1.47e-15, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, + 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, + 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, + 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, + 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, + 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, + 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, + 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, + 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, + 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, + -1.961e-15, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, + -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, + -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, + -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, + -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, + -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, + -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, + -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, + -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, + -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, + 5.391e-15, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, + 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, + 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, + 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, + 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, + 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, + 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, + 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, + 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, + 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, + -1.716e-15, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, + -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, + -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, + -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, + -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, + -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, + -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, + -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, + -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, + -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, + -1.959e-15, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, + 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, + 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, + 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, + 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, + 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, + 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, + 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, + 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, + 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, + -1.471e-15, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, + -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, + -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, + -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, + -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, + -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, + -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, + -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, + -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, + -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, + -2.204e-15, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, + 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, + 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, + 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, + 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, + 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, + 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, + 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, + 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, + 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, + -1.226e-15, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, + -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, + -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, + -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, + -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, + -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, + -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, + -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, + -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, + -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, + 4.656e-15, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, + 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, + 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, + 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, + 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, + 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, + 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, + 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, + 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, + 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, + -9.81e-16, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, + -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, + -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, + -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, + -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, + -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, + -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, + -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, + -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, + -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, + 4.411e-15, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, + 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, + 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, + 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, + 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, + 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, + 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, + 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, + 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, + 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, + -7.841e-15, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, + -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, + -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, + -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, + -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, + -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, + -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, + -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, + -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, + -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, + -2.939e-15, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, + 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, + 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, + 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, + 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, + 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, + 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, + 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, + 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, + 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, + -4.911e-16, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, + -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, + -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, + -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, + -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, + -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0 + }; + + +const float32_t hamm_win_1024[1024] = { + 0.08000001, 0.08000869, 0.08003464, 0.08007795, 0.08013856, 0.08021647, 0.08031172, 0.08042425, + 0.08055410, 0.08070126, 0.08086568, 0.08104742, 0.08124641, 0.08146268, 0.08169621, 0.08194700, + 0.08221504, 0.08250031, 0.08280280, 0.08312252, 0.08345941, 0.08381352, 0.08418480, 0.08457324, + 0.08497882, 0.08540154, 0.08584136, 0.08629829, 0.08677229, 0.08726338, 0.08777151, 0.08829662, + 0.08883879, 0.08939791, 0.08997402, 0.09056708, 0.09117705, 0.09180391, 0.09244764, 0.09310821, + 0.09378564, 0.09447986, 0.09519085, 0.09591857, 0.09666303, 0.09742415, 0.09820199, 0.09899643, + 0.09980744, 0.10063508, 0.10147923, 0.10233989, 0.10321707, 0.10411066, 0.10502064, 0.10594702, + 0.10688975, 0.10784879, 0.10882407, 0.10981560, 0.11082330, 0.11184722, 0.11288723, 0.11394331, + 0.11501545, 0.11610356, 0.11720765, 0.11832768, 0.11946353, 0.12061524, 0.12178272, 0.12296599, + 0.12416494, 0.12537956, 0.12660977, 0.12785554, 0.12911683, 0.13039359, 0.13168579, 0.13299334, + 0.13431624, 0.13565439, 0.13700777, 0.13837633, 0.13976002, 0.14115876, 0.14257249, 0.14400125, + 0.14544487, 0.14690334, 0.14837661, 0.14986467, 0.15136737, 0.15288472, 0.15441665, 0.15596312, + 0.15752399, 0.15909931, 0.16068897, 0.16229287, 0.16391101, 0.16554332, 0.16718972, 0.16885012, + 0.17052457, 0.17221287, 0.17391503, 0.17563099, 0.17736065, 0.17910397, 0.18086091, 0.18263134, + 0.18441522, 0.18621248, 0.18802309, 0.18984693, 0.19168392, 0.19353411, 0.19539729, 0.19727343, + 0.19916251, 0.20106441, 0.20297906, 0.20490640, 0.20684636, 0.20879889, 0.21076384, 0.21274120, + 0.21473089, 0.21673286, 0.21874696, 0.22077316, 0.22281137, 0.22486153, 0.22692358, 0.22899738, + 0.23108292, 0.23318008, 0.23528877, 0.23740897, 0.23954052, 0.24168339, 0.24383754, 0.24600279, + 0.24817911, 0.25036645, 0.25256467, 0.25477371, 0.25699350, 0.25922394, 0.26146495, 0.26371646, + 0.26597837, 0.26825058, 0.27053300, 0.27282560, 0.27512825, 0.27744091, 0.27976340, 0.28209570, + 0.28443775, 0.28678936, 0.28915054, 0.29152113, 0.29390109, 0.29629037, 0.29868877, 0.30109626, + 0.30351278, 0.30593818, 0.30837238, 0.31081527, 0.31326687, 0.31572697, 0.31819552, 0.32067239, + 0.32315755, 0.32565081, 0.32815221, 0.33066157, 0.33317882, 0.33570385, 0.33823657, 0.34077689, + 0.34332466, 0.34587988, 0.34844244, 0.35101217, 0.35358903, 0.35617292, 0.35876369, 0.36136129, + 0.36396563, 0.36657661, 0.36919412, 0.37181807, 0.37444833, 0.37708482, 0.37972742, 0.38237607, + 0.38503069, 0.38769114, 0.39035732, 0.39302909, 0.39570647, 0.39838916, 0.40107727, 0.40377063, + 0.40646908, 0.40917256, 0.41188097, 0.41459423, 0.41731215, 0.42003471, 0.42276183, 0.42549333, + 0.42822915, 0.43096918, 0.43371329, 0.43646142, 0.43921345, 0.44196928, 0.44472879, 0.44749191, + 0.45025852, 0.45302844, 0.45580167, 0.45857808, 0.46135756, 0.46414000, 0.46692532, 0.46971336, + 0.47250399, 0.47529721, 0.47809291, 0.48089090, 0.48369113, 0.48649347, 0.48929784, 0.49210405, + 0.49491215, 0.49772191, 0.50053328, 0.50334615, 0.50616038, 0.50897586, 0.51179248, 0.51461023, + 0.51742887, 0.52024841, 0.52306873, 0.52588964, 0.52871108, 0.53153294, 0.53435510, 0.53717750, + 0.54000002, 0.54282254, 0.54564494, 0.54846716, 0.55128896, 0.55411041, 0.55693138, 0.55975163, + 0.56257117, 0.56538987, 0.56820762, 0.57102424, 0.57383972, 0.57665396, 0.57946682, 0.58227819, + 0.58508795, 0.58789605, 0.59070224, 0.59350657, 0.59630895, 0.59910917, 0.60190719, 0.60470283, + 0.60749608, 0.61028671, 0.61307478, 0.61586010, 0.61864251, 0.62142199, 0.62419844, 0.62697166, + 0.62974155, 0.63250816, 0.63527125, 0.63803077, 0.64078665, 0.64353865, 0.64628679, 0.64903086, + 0.65177095, 0.65450674, 0.65723825, 0.65996534, 0.66268796, 0.66540587, 0.66811907, 0.67082751, + 0.67353100, 0.67622948, 0.67892277, 0.68161088, 0.68429363, 0.68697095, 0.68964279, 0.69230890, + 0.69496936, 0.69762397, 0.70027268, 0.70291525, 0.70555174, 0.70818198, 0.71080595, 0.71342349, + 0.71603441, 0.71863878, 0.72123635, 0.72382712, 0.72641104, 0.72898787, 0.73155761, 0.73412013, + 0.73667538, 0.73922318, 0.74176347, 0.74429619, 0.74682128, 0.74933851, 0.75184786, 0.75434923, + 0.75684255, 0.75932771, 0.76180464, 0.76427317, 0.76673317, 0.76918477, 0.77162766, 0.77406192, + 0.77648729, 0.77890378, 0.78131127, 0.78370970, 0.78609896, 0.78847897, 0.79084957, 0.79321074, + 0.79556239, 0.79790437, 0.80023664, 0.80255914, 0.80487180, 0.80717444, 0.80946708, 0.81174952, + 0.81402171, 0.81628364, 0.81853515, 0.82077616, 0.82300663, 0.82522643, 0.82743549, 0.82963359, + 0.83182096, 0.83399725, 0.83616257, 0.83831668, 0.84045953, 0.84259117, 0.84471130, 0.84682000, + 0.84891719, 0.85100269, 0.85307658, 0.85513854, 0.85718870, 0.85922688, 0.86125308, 0.86326718, + 0.86526918, 0.86725885, 0.86923623, 0.87120116, 0.87315369, 0.87509370, 0.87702101, 0.87893569, + 0.88083756, 0.88272667, 0.88460279, 0.88646591, 0.88831609, 0.89015311, 0.89197695, 0.89378756, + 0.89558482, 0.89736873, 0.89913917, 0.90089607, 0.90263939, 0.90436912, 0.90608501, 0.90778720, + 0.90947556, 0.91114986, 0.91281033, 0.91445673, 0.91608906, 0.91770720, 0.91931111, 0.92090076, + 0.92247605, 0.92403698, 0.92558342, 0.92711532, 0.92863274, 0.93013543, 0.93162346, 0.93309665, + 0.93455517, 0.93599880, 0.93742752, 0.93884128, 0.94024003, 0.94162369, 0.94299233, 0.94434571, + 0.94568384, 0.94700670, 0.94831431, 0.94960648, 0.95088321, 0.95214450, 0.95339024, 0.95462048, + 0.95583510, 0.95703405, 0.95821732, 0.95938480, 0.96053654, 0.96167243, 0.96279240, 0.96389651, + 0.96498466, 0.96605682, 0.96711278, 0.96815282, 0.96917677, 0.97018445, 0.97117597, 0.97215128, + 0.97311032, 0.97405303, 0.97497940, 0.97588944, 0.97678304, 0.97766018, 0.97852087, 0.97936499, + 0.98019260, 0.98100364, 0.98179805, 0.98257589, 0.98333704, 0.98408151, 0.98480916, 0.98552024, + 0.98621440, 0.98689187, 0.98755240, 0.98819613, 0.98882306, 0.98943299, 0.99002600, 0.99060214, + 0.99116129, 0.99170339, 0.99222851, 0.99273670, 0.99322772, 0.99370176, 0.99415869, 0.99459851, + 0.99502122, 0.99542683, 0.99581528, 0.99618649, 0.99654061, 0.99687755, 0.99719727, 0.99749970, + 0.99778497, 0.99805307, 0.99830383, 0.99853742, 0.99875367, 0.99895263, 0.99913436, 0.99929881, + 0.99944592, 0.99957579, 0.99968833, 0.99978358, 0.99986148, 0.99992210, 0.99996543, 0.99999136, + 1.00000000, 0.99999136, 0.99996543, 0.99992210, 0.99986148, 0.99978358, 0.99968833, 0.99957579, + 0.99944592, 0.99929881, 0.99913436, 0.99895263, 0.99875367, 0.99853736, 0.99830383, 0.99805307, + 0.99778497, 0.99749970, 0.99719727, 0.99687755, 0.99654061, 0.99618649, 0.99581528, 0.99542677, + 0.99502122, 0.99459851, 0.99415869, 0.99370176, 0.99322772, 0.99273670, 0.99222851, 0.99170339, + 0.99116123, 0.99060214, 0.99002600, 0.98943293, 0.98882300, 0.98819613, 0.98755240, 0.98689181, + 0.98621440, 0.98552018, 0.98480916, 0.98408151, 0.98333704, 0.98257589, 0.98179805, 0.98100358, + 0.98019254, 0.97936499, 0.97852081, 0.97766018, 0.97678298, 0.97588938, 0.97497940, 0.97405303, + 0.97311032, 0.97215128, 0.97117591, 0.97018445, 0.96917671, 0.96815276, 0.96711278, 0.96605670, + 0.96498460, 0.96389651, 0.96279240, 0.96167237, 0.96053648, 0.95938480, 0.95821726, 0.95703399, + 0.95583510, 0.95462048, 0.95339024, 0.95214450, 0.95088315, 0.94960642, 0.94831425, 0.94700670, + 0.94568384, 0.94434559, 0.94299227, 0.94162369, 0.94024003, 0.93884128, 0.93742752, 0.93599880, + 0.93455517, 0.93309665, 0.93162346, 0.93013537, 0.92863268, 0.92711532, 0.92558336, 0.92403692, + 0.92247605, 0.92090070, 0.91931105, 0.91770715, 0.91608906, 0.91445673, 0.91281033, 0.91114986, + 0.90947551, 0.90778720, 0.90608501, 0.90436906, 0.90263939, 0.90089607, 0.89913917, 0.89736867, + 0.89558482, 0.89378750, 0.89197695, 0.89015305, 0.88831604, 0.88646591, 0.88460279, 0.88272661, + 0.88083756, 0.87893564, 0.87702096, 0.87509364, 0.87315369, 0.87120116, 0.86923623, 0.86725879, + 0.86526912, 0.86326718, 0.86125302, 0.85922682, 0.85718870, 0.85513854, 0.85307646, 0.85100269, + 0.84891713, 0.84682000, 0.84471124, 0.84259105, 0.84045959, 0.83831668, 0.83616257, 0.83399731, + 0.83182096, 0.82963359, 0.82743537, 0.82522631, 0.82300651, 0.82077610, 0.81853509, 0.81628358, + 0.81402171, 0.81174946, 0.80946696, 0.80717438, 0.80487174, 0.80255908, 0.80023658, 0.79790425, + 0.79556227, 0.79321063, 0.79084945, 0.78847879, 0.78609884, 0.78370953, 0.78131115, 0.77890384, + 0.77648735, 0.77406192, 0.77162772, 0.76918477, 0.76673323, 0.76427311, 0.76180458, 0.75932765, + 0.75684249, 0.75434917, 0.75184780, 0.74933845, 0.74682117, 0.74429613, 0.74176341, 0.73922312, + 0.73667526, 0.73412007, 0.73155755, 0.72898781, 0.72641093, 0.72382706, 0.72123623, 0.71863860, + 0.71603429, 0.71342325, 0.71080601, 0.70818204, 0.70555174, 0.70291531, 0.70027268, 0.69762397, + 0.69496936, 0.69230890, 0.68964279, 0.68697095, 0.68429363, 0.68161082, 0.67892271, 0.67622936, + 0.67353094, 0.67082745, 0.66811901, 0.66540575, 0.66268778, 0.65996522, 0.65723813, 0.65450662, + 0.65177077, 0.64903075, 0.64628661, 0.64353848, 0.64078641, 0.63803059, 0.63527131, 0.63250822, + 0.62974161, 0.62697160, 0.62419838, 0.62142199, 0.61864251, 0.61586004, 0.61307478, 0.61028671, + 0.60749602, 0.60470277, 0.60190707, 0.59910911, 0.59630889, 0.59350652, 0.59070218, 0.58789587, + 0.58508778, 0.58227801, 0.57946670, 0.57665384, 0.57383960, 0.57102406, 0.56820744, 0.56538969, + 0.56257099, 0.55975145, 0.55693138, 0.55411047, 0.55128902, 0.54846716, 0.54564494, 0.54282254, + 0.54000002, 0.53717750, 0.53435510, 0.53153288, 0.52871102, 0.52588958, 0.52306867, 0.52024835, + 0.51742882, 0.51461011, 0.51179242, 0.50897574, 0.50616020, 0.50334597, 0.50053316, 0.49772179, + 0.49491200, 0.49210393, 0.48929766, 0.48649329, 0.48369095, 0.48089093, 0.47809294, 0.47529727, + 0.47250402, 0.46971333, 0.46692526, 0.46413997, 0.46135753, 0.45857805, 0.45580164, 0.45302841, + 0.45025843, 0.44749182, 0.44472873, 0.44196922, 0.43921337, 0.43646133, 0.43371320, 0.43096906, + 0.42822903, 0.42549321, 0.42276171, 0.42003462, 0.41731203, 0.41459405, 0.41188082, 0.40917242, + 0.40646893, 0.40377066, 0.40107733, 0.39838922, 0.39570644, 0.39302909, 0.39035729, 0.38769114, + 0.38503069, 0.38237607, 0.37972739, 0.37708476, 0.37444827, 0.37181801, 0.36919406, 0.36657655, + 0.36396557, 0.36136121, 0.35876361, 0.35617280, 0.35358894, 0.35101205, 0.34844232, 0.34587979, + 0.34332454, 0.34077674, 0.33823639, 0.33570367, 0.33317864, 0.33066159, 0.32815224, 0.32565087, + 0.32315755, 0.32067239, 0.31819549, 0.31572694, 0.31326681, 0.31081527, 0.30837232, 0.30593812, + 0.30351272, 0.30109623, 0.29868871, 0.29629028, 0.29390103, 0.29152107, 0.28915045, 0.28678927, + 0.28443763, 0.28209558, 0.27976328, 0.27744076, 0.27512813, 0.27282548, 0.27053288, 0.26825041, + 0.26597837, 0.26371649, 0.26146495, 0.25922394, 0.25699350, 0.25477371, 0.25256464, 0.25036642, + 0.24817908, 0.24600273, 0.24383748, 0.24168336, 0.23954049, 0.23740888, 0.23528871, 0.23317999, + 0.23108283, 0.22899729, 0.22692350, 0.22486147, 0.22281131, 0.22077307, 0.21874687, 0.21673274, + 0.21473080, 0.21274108, 0.21076372, 0.20879874, 0.20684639, 0.20490640, 0.20297906, 0.20106441, + 0.19916251, 0.19727343, 0.19539726, 0.19353408, 0.19168392, 0.18984687, 0.18802303, 0.18621245, + 0.18441516, 0.18263128, 0.18086085, 0.17910391, 0.17736059, 0.17563093, 0.17391497, 0.17221281, + 0.17052448, 0.16885003, 0.16718963, 0.16554320, 0.16391090, 0.16229275, 0.16068885, 0.15909919, + 0.15752399, 0.15596312, 0.15441665, 0.15288472, 0.15136737, 0.14986467, 0.14837661, 0.14690331, + 0.14544484, 0.14400122, 0.14257249, 0.14115873, 0.13975996, 0.13837630, 0.13700771, 0.13565433, + 0.13431621, 0.13299328, 0.13168573, 0.13039353, 0.12911677, 0.12785548, 0.12660968, 0.12537947, + 0.12416488, 0.12296590, 0.12178269, 0.12061527, 0.11946353, 0.11832768, 0.11720765, 0.11610356, + 0.11501542, 0.11394328, 0.11288723, 0.11184719, 0.11082330, 0.10981560, 0.10882404, 0.10784876, + 0.10688972, 0.10594699, 0.10502061, 0.10411063, 0.10321701, 0.10233986, 0.10147920, 0.10063505, + 0.09980741, 0.09899637, 0.09820193, 0.09742412, 0.09666297, 0.09591851, 0.09519079, 0.09447986, + 0.09378564, 0.09310821, 0.09244764, 0.09180391, 0.09117705, 0.09056708, 0.08997402, 0.08939791, + 0.08883876, 0.08829662, 0.08777148, 0.08726335, 0.08677229, 0.08629826, 0.08584133, 0.08540154, + 0.08497879, 0.08457321, 0.08418480, 0.08381352, 0.08345941, 0.08312249, 0.08280277, 0.08250031, + 0.08221501, 0.08194697, 0.08169621, 0.08146268, 0.08124641, 0.08104742, 0.08086568, 0.08070123, + 0.08055410, 0.08042425, 0.08031172, 0.08021647, 0.08013856, 0.08007795, 0.08003464, 0.08000869 +}; + +const float32_t hamm_win_512[512] = { + 0.08000001, 0.08003464, 0.08013856, 0.08031172, 0.08055410, 0.08086568, 0.08124641, 0.08169621, + 0.08221504, 0.08280280, 0.08345941, 0.08418480, 0.08497882, 0.08584136, 0.08677229, 0.08777151, + 0.08883879, 0.08997402, 0.09117705, 0.09244764, 0.09378564, 0.09519085, 0.09666303, 0.09820199, + 0.09980744, 0.10147923, 0.10321707, 0.10502064, 0.10688975, 0.10882407, 0.11082330, 0.11288723, + 0.11501545, 0.11720765, 0.11946353, 0.12178272, 0.12416494, 0.12660977, 0.12911683, 0.13168579, + 0.13431624, 0.13700777, 0.13976002, 0.14257249, 0.14544487, 0.14837661, 0.15136737, 0.15441665, + 0.15752399, 0.16068897, 0.16391101, 0.16718972, 0.17052457, 0.17391503, 0.17736065, 0.18086091, + 0.18441522, 0.18802309, 0.19168392, 0.19539729, 0.19916251, 0.20297906, 0.20684636, 0.21076384, + 0.21473089, 0.21874696, 0.22281137, 0.22692358, 0.23108292, 0.23528877, 0.23954052, 0.24383754, + 0.24817911, 0.25256467, 0.25699350, 0.26146495, 0.26597837, 0.27053300, 0.27512825, 0.27976340, + 0.28443775, 0.28915054, 0.29390109, 0.29868877, 0.30351278, 0.30837238, 0.31326687, 0.31819552, + 0.32315755, 0.32815221, 0.33317882, 0.33823657, 0.34332466, 0.34844244, 0.35358903, 0.35876369, + 0.36396563, 0.36919412, 0.37444833, 0.37972742, 0.38503069, 0.39035732, 0.39570647, 0.40107727, + 0.40646908, 0.41188097, 0.41731215, 0.42276183, 0.42822915, 0.43371329, 0.43921345, 0.44472879, + 0.45025852, 0.45580167, 0.46135756, 0.46692532, 0.47250399, 0.47809291, 0.48369113, 0.48929784, + 0.49491215, 0.50053328, 0.50616038, 0.51179248, 0.51742887, 0.52306873, 0.52871108, 0.53435510, + 0.54000002, 0.54564494, 0.55128896, 0.55693138, 0.56257117, 0.56820762, 0.57383972, 0.57946682, + 0.58508795, 0.59070224, 0.59630895, 0.60190719, 0.60749608, 0.61307478, 0.61864251, 0.62419844, + 0.62974155, 0.63527125, 0.64078665, 0.64628679, 0.65177095, 0.65723825, 0.66268796, 0.66811907, + 0.67353100, 0.67892277, 0.68429363, 0.68964279, 0.69496936, 0.70027268, 0.70555174, 0.71080595, + 0.71603441, 0.72123635, 0.72641104, 0.73155761, 0.73667538, 0.74176347, 0.74682128, 0.75184786, + 0.75684255, 0.76180464, 0.76673317, 0.77162766, 0.77648729, 0.78131127, 0.78609896, 0.79084957, + 0.79556239, 0.80023664, 0.80487180, 0.80946708, 0.81402171, 0.81853515, 0.82300663, 0.82743549, + 0.83182096, 0.83616257, 0.84045953, 0.84471130, 0.84891719, 0.85307658, 0.85718870, 0.86125308, + 0.86526918, 0.86923623, 0.87315369, 0.87702101, 0.88083756, 0.88460279, 0.88831609, 0.89197695, + 0.89558482, 0.89913917, 0.90263939, 0.90608501, 0.90947556, 0.91281033, 0.91608906, 0.91931111, + 0.92247605, 0.92558342, 0.92863274, 0.93162346, 0.93455517, 0.93742752, 0.94024003, 0.94299233, + 0.94568384, 0.94831431, 0.95088321, 0.95339024, 0.95583510, 0.95821732, 0.96053654, 0.96279240, + 0.96498466, 0.96711278, 0.96917677, 0.97117597, 0.97311032, 0.97497940, 0.97678304, 0.97852087, + 0.98019260, 0.98179805, 0.98333704, 0.98480916, 0.98621440, 0.98755240, 0.98882306, 0.99002600, + 0.99116129, 0.99222851, 0.99322772, 0.99415869, 0.99502122, 0.99581528, 0.99654061, 0.99719727, + 0.99778497, 0.99830383, 0.99875367, 0.99913436, 0.99944592, 0.99968833, 0.99986148, 0.99996543, + 1.00000000, 0.99996543, 0.99986148, 0.99968833, 0.99944592, 0.99913436, 0.99875367, 0.99830383, + 0.99778497, 0.99719727, 0.99654061, 0.99581528, 0.99502122, 0.99415869, 0.99322772, 0.99222851, + 0.99116123, 0.99002600, 0.98882300, 0.98755240, 0.98621440, 0.98480916, 0.98333704, 0.98179805, + 0.98019254, 0.97852081, 0.97678298, 0.97497940, 0.97311032, 0.97117591, 0.96917671, 0.96711278, + 0.96498460, 0.96279240, 0.96053648, 0.95821726, 0.95583510, 0.95339024, 0.95088315, 0.94831425, + 0.94568384, 0.94299227, 0.94024003, 0.93742752, 0.93455517, 0.93162346, 0.92863268, 0.92558336, + 0.92247605, 0.91931105, 0.91608906, 0.91281033, 0.90947551, 0.90608501, 0.90263939, 0.89913917, + 0.89558482, 0.89197695, 0.88831604, 0.88460279, 0.88083756, 0.87702096, 0.87315369, 0.86923623, + 0.86526912, 0.86125302, 0.85718870, 0.85307646, 0.84891713, 0.84471124, 0.84045959, 0.83616257, + 0.83182096, 0.82743537, 0.82300651, 0.81853509, 0.81402171, 0.80946696, 0.80487174, 0.80023658, + 0.79556227, 0.79084945, 0.78609884, 0.78131115, 0.77648735, 0.77162772, 0.76673323, 0.76180458, + 0.75684249, 0.75184780, 0.74682117, 0.74176341, 0.73667526, 0.73155755, 0.72641093, 0.72123623, + 0.71603429, 0.71080601, 0.70555174, 0.70027268, 0.69496936, 0.68964279, 0.68429363, 0.67892271, + 0.67353094, 0.66811901, 0.66268778, 0.65723813, 0.65177077, 0.64628661, 0.64078641, 0.63527131, + 0.62974161, 0.62419838, 0.61864251, 0.61307478, 0.60749602, 0.60190707, 0.59630889, 0.59070218, + 0.58508778, 0.57946670, 0.57383960, 0.56820744, 0.56257099, 0.55693138, 0.55128902, 0.54564494, + 0.54000002, 0.53435510, 0.52871102, 0.52306867, 0.51742882, 0.51179242, 0.50616020, 0.50053316, + 0.49491200, 0.48929766, 0.48369095, 0.47809294, 0.47250402, 0.46692526, 0.46135753, 0.45580164, + 0.45025843, 0.44472873, 0.43921337, 0.43371320, 0.42822903, 0.42276171, 0.41731203, 0.41188082, + 0.40646893, 0.40107733, 0.39570644, 0.39035729, 0.38503069, 0.37972739, 0.37444827, 0.36919406, + 0.36396557, 0.35876361, 0.35358894, 0.34844232, 0.34332454, 0.33823639, 0.33317864, 0.32815224, + 0.32315755, 0.31819549, 0.31326681, 0.30837232, 0.30351272, 0.29868871, 0.29390103, 0.28915045, + 0.28443763, 0.27976328, 0.27512813, 0.27053288, 0.26597837, 0.26146495, 0.25699350, 0.25256464, + 0.24817908, 0.24383748, 0.23954049, 0.23528871, 0.23108283, 0.22692350, 0.22281131, 0.21874687, + 0.21473080, 0.21076372, 0.20684639, 0.20297906, 0.19916251, 0.19539726, 0.19168392, 0.18802303, + 0.18441516, 0.18086085, 0.17736059, 0.17391497, 0.17052448, 0.16718963, 0.16391090, 0.16068885, + 0.15752399, 0.15441665, 0.15136737, 0.14837661, 0.14544484, 0.14257249, 0.13975996, 0.13700771, + 0.13431621, 0.13168573, 0.12911677, 0.12660968, 0.12416488, 0.12178269, 0.11946353, 0.11720765, + 0.11501542, 0.11288723, 0.11082330, 0.10882404, 0.10688972, 0.10502061, 0.10321701, 0.10147920, + 0.09980741, 0.09820193, 0.09666297, 0.09519079, 0.09378564, 0.09244764, 0.09117705, 0.08997402, + 0.08883876, 0.08777148, 0.08677229, 0.08584133, 0.08497879, 0.08418480, 0.08345941, 0.08280277, + 0.08221501, 0.08169621, 0.08124641, 0.08086568, 0.08055410, 0.08031172, 0.08013856, 0.08003464, +}; + +// taken from speech_commands_v0.02/marvin/d0426d63_nohash_0.wav +const int16_t test_wav_marvin[] = +{ + 67, 78, 67, 22, -6, -25, -12, 34, 46, 54, 60, 45, + 45, 56, 43, 10, -2, -10, -31, -42, -42, -52, -67, -73, + -66, -66, -46, -1, 9, 20, 21, -15, -25, -17, 3, 32, + 50, 68, 84, 64, 39, 42, 11, -31, -18, -1, 13, 49, + 53, 38, 39, 25, 10, 28, 40, 39, 33, 9, 9, 13, + 5, 7, -7, -25, -30, -31, -14, 15, 32, 38, 31, 9, + 0, 14, 11, -11, -23, -41, -68, -75, -66, -44, -14, 1, + 9, 21, 29, 32, 25, -4, -17, -23, -45, -38, -45, -57, + -38, -34, -15, -3, -20, -23, -32, -49, -56, -71, -89, -75, + -45, -25, 33, 65, 43, 48, 31, -7, 0, 16, 17, 12, + -1, 4, 20, 14, -7, -24, -35, -34, 0, 28, 29, 71, + 100, 79, 67, 54, 61, 61, 20, 6, -9, -39, -51, -96, + -92, -56, -64, -14, 22, 14, 53, 64, 47, 44, 16, -22, + -38, -41, -34, -17, -17, -42, -60, -64, -56, -22, -3, 5, + 35, 48, 24, 14, 27, 22, 31, 45, 17, 7, 12, 20, + 57, 52, 27, 35, 36, 20, -4, -28, -38, -39, -27, -20, + -19, -3, 15, 35, 50, 45, 42, 38, 27, 16, -5, -30, + -46, -53, -68, -71, -65, -52, -17, 10, 28, 40, 38, 48, + 72, 48, 14, 12, -26, -52, -61, -70, -63, -63, -22, 15, + 10, 34, 62, 41, 5, 32, 34, 8, 78, 86, -1, 11, + 36, -73, -71, -54, -123, -23, -33, 1, 37, -156, 87, 172, +-161, 68, 142, -99, 168, 164, -112, 49, 87, -46, -3, 76, + 72, -5, 24, 19, -42, -47, -30, 137, 35, -147, 118, 51, +-108, 152, -1, -164, 56, 54, -14, -43, -32, 43, -30, -56, + -42, -166, -150, -37, -104, -177, -50, 22, -60, 25, 84, -9, + 50, 53, 2, 73, 21, -16, 79, 51, -10, 1, -20, -38, + -10, 34, 30, -7, 26, 35, -31, -20, 50, 28, -2, 34, + 0, -25, 52, 32, -42, -4, 2, -49, -57, -85, -130, -135, +-118, -77, -49, -46, -10, 6, -10, -3, -3, 3, -2, -11, + 18, -2, -23, -1, -35, -37, 0, -27, -35, -24, -39, -47, + -48, -20, -22, -49, -16, 3, 20, 54, 31, 17, 24, 12, + 34, 42, 21, 14, 0, 6, -23, -36, 25, -36, -52, 60, + -7, -10, 115, 62, 48, 100, 88, 57, 34, 119, 78, 11, + 120, 44, -15, 41, -42, -43, -3, 14, 52, 36, 78, 92, + 49, 66, 46, 16, 15, 4, -24, -24, 17, -24, -22, 32, + -31, -39, -32, -73, -23, -28, -60, -7, 8, -1, -4, -17, + -2, 19, 11, -21, -8, 38, 13, 16, 56, 29, 17, 1, + -17, -2, -7, 33, 34, -10, 32, 25, 3, 42, 19, 16, + 26, 10, 9, -17, -30, -53, -59, -11, -38, -53, -31, -73, + -68, -55, -85, -45, 12, 8, 7, 24, 24, 16, -7, -36, + -41, -33, -24, 10, 30, 5, -6, 3, -14, -43, -53, -38, + -23, -14, 0, -3, -6, 6, 19, 38, 39, 30, 32, 27, + 14, -16, -20, 9, -6, -17, 4, -1, -13, -26, -32, 3, + 30, 71, 99, 35, 2, 8, -6, 4, 13, 35, 54, 53, + 78, 67, 46, 74, 73, 16, -19, -17, -41, -47, -26, -29, + -11, 3, -14, -9, -8, -24, -24, -46, -67, -46, -17, -24, + -39, -10, -34, -67, -13, -41, -92, -52, -42, -43, -30, -12, + -21, -48, -10, -4, -18, 22, 38, 51, 74, 72, 94, 128, + 117, 82, 48, 7, -6, 2, -3, -17, -39, -31, -6, -13, + 0, 41, 36, 34, 47, 31, 45, 66, 54, 57, 56, 30, + 18, 16, 1, -21, -23, -10, -11, 11, 20, -8, 6, 20, + 13, -3, -12, 27, 38, 41, 72, 43, 4, 20, 0, -42, + -27, -19, -38, -59, -74, -42, -27, -35, -10, 0, -1, 9, + 3, -19, -27, -2, -10, -27, 0, 5, -7, -19, -13, -10, + -22, -1, -4, -17, 4, 14, 32, 33, 10, 6, 2, 0, + 8, -4, -16, 2, 9, 31, 38, 27, 47, 46, 37, 7, + -35, -32, -27, -7, 6, -10, 1, -7, -35, -57, -77, -78, + -92, -88, -74, -69, -13, -6, -27, 9, -3, -27, -16, -38, + -39, 0, 14, -10, -53, -67, -43, -25, 14, 56, 57, 90, + 121, 88, 66, 38, -10, -10, -13, -44, -50, -35, -21, -2, + 23, 15, 6, 14, 10, -1, -13, -23, -25, -5, 0, -13, + -5, 5, -1, -2, 1, -6, -14, -26, -24, -7, 18, 55, + 50, 37, 37, 20, 24, 34, 36, 38, 22, 10, -6, -27, + -39, -46, -39, -52, -59, -56, -68, -37, -11, -21, -25, -27, + -13, -13, -17, -5, -28, -30, -9, -19, -24, -14, -2, 13, + 28, 34, 29, 46, 55, 47, 56, 43, 29, 23, 1, -6, + -9, -19, -7, 11, 28, 52, 57, 43, 8, -11, 7, 25, + 61, 74, 60, 46, 4, -36, -65, -67, -52, -63, -68, -65, + -46, -21, -23, -40, -49, -31, -18, -15, -11, -21, -29, -39, + -39, -24, -7, 15, 11, -2, -13, -35, -35, -31, -22, 2, + 0, 4, 7, -6, 3, 10, 13, 17, 8, 24, 27, -3, + -3, -14, -32, -10, -17, -24, 0, 0, -3, 7, 15, 24, + 41, 49, 32, 22, 60, 84, 57, 41, 14, -22, -35, -49, + -36, -14, -32, -35, -22, -30, -15, 24, 49, 61, 49, 23, + 10, -6, -8, -6, -12, -6, -3, 7, 14, 15, 29, 27, + 18, 0, -29, -23, -11, -21, -28, -24, -3, 5, 3, 2, + 6, 20, 7, -9, -16, -31, -30, -26, -6, 23, 17, 23, + 26, 19, 41, 49, 52, 71, 98, 109, 82, 71, 71, 53, + 45, 49, 56, 39, 12, -3, -46, -77, -52, -49, -52, -24, + -29, -46, -55, -53, -44, -46, -24, -27, -57, -40, -27, -41, + -73, -114, -107, -61, -39, -37, -13, 10, 7, 9, 21, 44, + 69, 87, 97, 57, 17, 23, 2, -14, -17, -43, -56, -55, + -35, 3, 25, 44, 75, 80, 61, 49, 30, -4, -31, -48, + -56, -74, -77, -54, -47, -20, -11, -18, 20, 58, 85, 92, + 75, 52, 22, -1, -30, -46, -48, -60, -50, -24, 5, 25, + 43, 55, 32, 23, 41, 32, 7, -3, -19, -34, -21, 2, + 27, 45, 24, -4, -28, -44, -33, -27, -28, -45, -76, -75, + -46, -28, -7, 25, 15, -7, 0, -20, -19, 14, 9, -4, + -19, -31, -31, -27, -10, 3, 5, 22, 46, 65, 82, 85, + 87, 74, 49, 30, 1, 6, 24, 20, 20, 13, 3, -4, + 9, 34, 24, 5, -6, -35, -56, -34, -23, -21, -13, -20, + -27, -49, -60, -43, -17, 15, 18, 22, 32, 31, 28, 11, + 26, 60, 64, 63, 45, 18, 17, 16, 27, 41, 24, 4, + -6, -18, -23, -28, -56, -66, -43, -23, -11, -12, -14, -14, + -23, -18, -5, -16, -11, 0, 0, 0, -12, 4, 6, -20, + -18, -21, -24, -19, -7, 18, 30, 39, 56, 47, 22, 1, + -42, -82, -62, -32, -10, 30, 40, 36, 36, 13, -2, -5, + -16, -42, -82, -96, -90, -63, -13, 1, 26, 63, 39, 13, + -5, -28, -33, -40, -34, -20, -14, -13, -24, -33, -39, -46, + -37, -18, 1, 26, 46, 44, 37, 33, 31, 45, 49, 55, + 67, 53, 42, 42, 46, 35, 7, -13, -38, -56, -59, -54, + -46, -28, -14, -18, -6, 7, -17, -41, -40, -22, 16, 40, + 42, 21, -9, -13, -25, -41, -39, -35, -17, -3, 9, 43, + 58, 55, 66, 70, 45, 17, 9, 14, 3, -9, -6, -6, + -4, 6, 4, -12, -24, -23, -8, 10, 30, 32, 13, -4, + -24, -25, -17, -33, -50, -39, -12, 4, 5, 3, -8, -13, + 7, 27, 53, 73, 64, 66, 78, 64, 41, 27, 3, -8, + -2, 0, -10, -19, -17, -12, 11, 20, 13, 17, 32, 45, + 36, 13, -6, -28, -47, -49, -53, -59, -51, -35, -13, -9, + -17, -10, 2, 18, 29, 20, 14, 6, -15, -32, -53, -55, + -46, -53, -26, 0, 19, 48, 53, 55, 56, 57, 66, 61, + 48, 32, 24, 25, 4, -7, 4, -12, -22, 2, 20, 32, + 31, 14, -2, -36, -73, -95, -105, -100, -84, -51, -23, -9, + 3, -4, -17, -22, -13, 1, -10, -24, -42, -67, -56, -39, + -23, 27, 70, 73, 72, 70, 45, 22, 8, 2, 7, -6, + -23, -10, 2, -9, -20, -18, -12, -2, 9, 7, -5, -13, + -6, -6, -10, -4, -3, 2, 5, 0, 6, 17, 17, 18, + 13, 3, 7, 28, 39, 34, 41, 30, -11, -35, -43, -31, + 4, 24, 35, 61, 69, 63, 49, 15, -15, -19, -9, -20, + -36, -31, -15, -2, 10, 17, 18, 37, 61, 58, 42, 18, + -10, -4, 9, 10, 6, -17, -18, -20, -28, -30, -49, -48, + -35, -21, -1, 7, 0, -6, -2, 4, 30, 49, 60, 63, + 39, 24, 8, 0, 5, 25, 45, 49, 71, 64, 50, 40, + 11, -11, -31, -20, -5, -7, -3, -15, -16, -21, -39, -21, + -8, -20, -16, 0, 9, 10, 2, -13, -20, -9, -4, -24, + -25, -16, -31, -38, -35, -20, 2, 12, 12, 4, 1, 9, + 13, 8, 2, 9, 14, 10, 4, -1, 7, 15, 17, 12, + 0, -16, -14, -10, -20, -16, -10, -6, 6, 7, 4, 1, + -3, -15, -34, -50, -64, -64, -53, -54, -44, -16, -1, 5, + 9, 2, 0, 2, -9, -22, -25, -15, 2, 6, 7, 14, + 4, -8, -16, -34, -38, -31, -35, -16, -2, -2, -4, -28, + -38, -50, -53, -28, -25, -20, 15, 32, 17, -9, -36, -49, + -63, -77, -74, -64, -47, -12, 49, 89, 99, 107, 96, 86, + 61, 28, 11, 1, 24, 47, 58, 71, 67, 62, 66, 67, + 56, 42, 36, 24, 6, 10, 14, 0, -3, -17, -31, -33, + -45, -57, -80, -99, -89, -67, -45, -16, 10, 31, 50, 50, + 32, 12, 11, 12, 10, 29, 45, 39, 28, 31, 27, 6, + -18, -27, -11, 4, 17, 24, 20, 28, 27, 6, -15, -22, + -30, -30, -23, -30, -28, -25, -34, -29, -22, -11, 0, 0, + 6, 16, 14, 11, 24, 39, 48, 62, 64, 49, 40, 22, + -22, -26, -2, -1, -5, -31, -60, -63, -49, 4, 47, 58, + 69, 49, 23, 8, -14, -21, -26, -21, -12, -20, -20, -23, + -38, -59, -73, -77, -73, -46, -20, -6, 9, 32, 30, 20, + 19, -9, -39, -67, -86, -85, -74, -54, -41, -20, 14, 51, + 78, 67, 56, 59, 43, 28, 34, 51, 55, 53, 64, 79, + 75, 61, 42, 10, -4, 11, 21, 23, 21, -11, -30, -43, + -72, -86, -110, -107, -81, -66, -54, -64, -46, -32, -32, -22, + -29, -12, 6, 6, 7, 4, -2, 4, 29, 43, 46, 41, + 20, 9, 23, 44, 41, 28, 35, 49, 39, 18, 11, 3, + -9, -13, 3, 32, 39, 38, 37, 40, 56, 60, 60, 62, + 46, 17, -8, -21, -26, -14, 2, 3, 15, 12, -1, 0, + -11, -9, 11, 25, 28, 21, 0, -33, -47, -41, -17, 14, + 23, 24, 29, 32, 14, -2, 6, 4, -13, -39, -57, -45, + -28, -34, -44, -35, -29, -7, 12, 3, 9, 1, -22, -38, + -57, -53, -32, -23, -6, 3, -8, -13, -18, -30, -31, -33, + -32, -4, 35, 60, 88, 93, 71, 67, 51, 10, -10, -14, + -16, -13, -6, 11, -3, -34, -29, -30, -27, -13, -17, -34, + -60, -63, -41, -24, -7, 11, 12, -11, -49, -78, -91, -71, + -22, 22, 26, 14, -10, -41, -26, 4, 27, 45, 43, 46, + 46, 41, 45, 49, 34, 17, 24, 29, 23, 34, 42, 20, + -30, -63, -77, -102, -89, -46, -32, -31, -17, 2, 20, 22, + 3, -10, -13, -13, -9, 5, 9, 11, 17, 5, 1, 1, + -3, -3, 6, 31, 45, 42, 27, 12, 14, 19, 7, -22, + -28, -10, 12, 23, 27, 30, 10, -16, -39, -53, -50, -41, + -29, -28, -17, 0, 12, 37, 50, 46, 42, 25, 2, -24, + -39, -33, -34, -30, -11, 2, 20, 38, 38, 41, 42, 44, + 45, 25, 5, 0, 1, -3, -12, -8, -2, -5, -7, -3, + -7, -13, -14, -18, -7, 3, -4, -12, 2, 27, 38, 21, + -13, -26, -34, -34, -28, -19, -11, -29, -47, -67, -65, -44, + -39, -22, -18, -29, -5, 24, 35, 36, 22, 23, 20, 6, + 13, 30, 47, 45, 27, 32, 45, 24, -14, -25, -26, -21, + -9, -17, -17, -14, -15, 7, 16, 13, 20, 17, -10, -50, + -56, -49, -46, -25, -21, -18, -9, -28, -35, -11, -3, -7, + 17, 45, 46, 31, 3, -29, -37, -28, -21, -9, -2, -6, + -20, -14, 10, 16, 22, 17, -20, -42, -42, -59, -59, -48, + -46, -11, 20, 27, 42, 45, 42, 32, 4, -31, -48, -52, + -56, -38, -24, -20, 7, 37, 42, 31, 24, 25, 29, 23, + 22, 24, 18, 21, 25, 33, 25, 13, 17, 17, 24, 32, + 37, 35, 39, 52, 52, 47, 40, 31, 8, 1, 3, -24, + -40, -48, -45, -13, 18, 27, 16, -3, -23, -27, -17, -7, + -2, 13, 31, 30, 24, 10, 0, 3, 12, 17, 17, 36, + 62, 71, 66, 70, 61, 34, 23, 26, 39, 57, 64, 58, + 52, 36, 0, -21, -17, -5, 7, 7, 1, -4, -13, -21, + -34, -39, -48, -63, -71, -80, -79, -53, -9, 1, -2, 5, + -1, 4, 28, 45, 35, 16, 16, 16, 12, 3, 0, 9, + 4, -18, -45, -57, -60, -56, -42, -45, -39, -11, 2, -6, + 3, 13, -2, -17, -39, -47, -24, 15, 39, 33, 34, 25, + 5, 1, -21, -53, -51, -28, -18, -1, 34, 56, 53, 40, + 31, 25, 13, 10, 17, 15, 19, 23, 21, 31, 28, 10, + -14, -24, -14, -16, -25, -32, -26, -9, -3, -9, -8, -1, + -1, -10, -28, -38, -38, -38, -31, -9, 10, 6, -1, -6, + -23, -38, -49, -51, -33, -23, -9, 10, 5, 10, 23, 24, + 14, 12, 31, 38, 42, 49, 21, -8, -26, -31, 3, 24, + 21, 19, 9, 1, -3, 6, 28, 56, 69, 48, 22, -6, + -30, -38, -37, -28, -10, 9, 25, 40, 37, 21, 16, 11, + 11, 20, 35, 40, 31, 17, -14, -32, -24, -10, 9, 25, + 44, 54, 46, 35, 21, 2, -6, -8, -17, -27, -38, -31, + -9, 9, 39, 56, 33, 14, 11, 6, 6, 7, 2, 17, + 31, 10, -14, -22, -15, -15, -14, 9, 17, 11, 2, 4, + 21, 11, 5, 1, -17, -21, -39, -55, -39, -18, -5, -6, + -16, -21, -35, -34, -18, -10, 3, 21, 18, 14, 29, 28, + 31, 26, -21, -61, -91, -118, -120, -107, -83, -63, -60, -58, + -56, -53, -40, -27, -27, -19, 16, 47, 64, 64, 49, 21, + -6, -17, -34, -55, -50, -39, -24, -7, 0, 29, 45, 31, + 27, 13, -14, -32, -41, -32, -3, 17, 14, 9, 7, 10, + 4, -5, -5, 5, 31, 49, 53, 45, 31, 38, 35, 9, + -13, -34, -38, -28, -34, -27, 7, 15, 14, 24, 2, -15, + -2, 3, 2, 7, 12, 34, 56, 53, 42, 24, 9, -6, + -34, -35, -21, -13, 17, 51, 67, 69, 65, 59, 35, 17, + 11, 3, 4, 6, -10, -16, -22, -38, -28, -9, -6, -4, + 13, 30, 32, 23, 3, -8, -2, 12, 27, 31, 38, 31, + 8, 14, 31, 50, 64, 60, 62, 67, 56, 45, 34, 11, + -10, -21, -39, -38, -21, -25, -41, -55, -60, -60, -59, -53, + -54, -52, -35, -31, -41, -19, 5, 11, 31, 45, 43, 36, + 21, 12, 18, 5, -16, -25, -34, -32, -11, 30, 64, 70, + 57, 35, 25, 6, -19, -18, -17, -11, -20, -56, -74, -76, + -59, -51, -56, -38, -31, -29, -28, -15, 9, 20, 39, 42, + 27, 31, 21, 2, 3, -7, -19, -10, -25, -44, -35, -29, + -21, -31, -51, -61, -64, -63, -64, -57, -60, -52, -15, 17, + 50, 72, 75, 63, 33, 16, -7, -20, -21, -53, -56, -44, + -45, -29, -10, 16, 33, 36, 51, 41, 16, 17, 11, -4, + 0, 21, 28, 5, -2, 1, -13, -20, -6, 26, 53, 61, + 66, 67, 56, 41, 38, 60, 60, 38, 30, 17, 21, 38, + 35, 38, 44, 30, 4, -11, -19, -18, -21, -40, -32, -21, + -27, -20, -23, -17, -18, -32, -4, 19, 32, 45, 45, 41, + 36, 32, 31, 56, 67, 53, 25, 0, 3, -3, -3, -2, + -17, -6, 15, 33, 47, 35, 17, 20, 27, 29, 38, 28, + -10, -54, -97, -116, -110, -87, -61, -53, -45, -32, -35, -22, + 3, 2, 1, 16, 25, 14, 1, -6, -14, 0, 10, -1, + -3, -3, -10, -41, -67, -60, -64, -67, -56, -38, -6, 6, + 2, -2, -12, 0, 10, 4, 8, 13, 20, 6, -16, -28, + -46, -45, -26, -10, 2, -8, -20, -21, -28, -27, -32, -40, + -40, -48, -41, -42, -33, 2, 7, 5, -3, -24, -25, -10, + 5, 26, 51, 61, 70, 66, 42, 24, 7, 6, -8, -25, + -14, -7, 6, 20, 20, 19, 15, 10, -1, 4, -7, -28, + -17, -19, -14, 0, -15, -40, -62, -68, -65, -56, -35, -10, + 8, 28, 49, 66, 84, 97, 101, 97, 96, 84, 48, 23, + 26, 45, 50, 50, 57, 53, 38, 17, -14, -45, -52, -41, + -18, 1, 9, 12, -1, -20, -30, -24, -5, -14, -37, -29, + -24, -34, -31, -27, -25, -12, -6, 7, 29, 31, 35, 28, + 28, 38, 41, 63, 58, 49, 49, 27, 13, -8, -27, -34, + -45, -45, -52, -46, -6, 27, 59, 71, 57, 63, 53, 9, + -18, -32, -46, -50, -52, -40, -18, -4, -13, -38, -39, -31, + -28, -31, -39, -24, -6, 4, 23, 26, 24, 22, 8, -10, + -34, -37, -10, 1, -3, 13, 25, 18, 17, 15, 6, -10, + -22, -17, -6, 9, 6, -11, -24, -52, -69, -53, -32, -26, + -30, -35, -34, -21, -14, -32, -45, -39, -27, -21, -18, -3, + 4, -2, 11, 21, 24, 37, 49, 59, 59, 48, 30, 20, + 33, 29, 14, 14, 12, 6, -11, -20, -6, 9, 27, 35, + 17, 5, 14, 29, 48, 67, 52, 28, 0, -33, -34, -50, + -67, -65, -79, -92, -87, -55, -22, -12, -6, 7, 24, 46, + 60, 70, 84, 60, 13, -13, -26, -23, -14, -1, -8, -28, + -21, -29, -42, -28, -17, -6, 13, 21, 31, 57, 66, 61, + 60, 64, 46, 11, -4, -17, -26, -49, -61, -45, -48, -32, + -1, 5, -4, -4, -2, -13, -9, 1, -8, -17, -16, -24, + -24, 17, 53, 69, 84, 82, 84, 76, 52, 49, 41, 27, + 36, 53, 60, 56, 29, -17, -54, -69, -73, -68, -37, -6, + 2, 10, 15, 3, -14, -14, -8, -11, -13, -13, -16, -27, + -38, -38, -38, -17, 3, 2, 21, 30, 51, 98, 99, 93, + 95, 77, 63, 42, 32, 38, 31, 21, 6, -17, -37, -47, + -35, -14, -6, -24, -38, -48, -63, -44, -28, -29, -24, -32, + -46, -55, -62, -67, -66, -56, -49, -47, -57, -67, -68, -73, + -64, -41, -21, 7, 37, 43, 16, -23, -53, -68, -45, -9, + 6, 10, -3, -7, 3, -4, -22, -38, -51, -38, -14, -2, + 24, 21, -7, -5, -10, -12, -4, 2, 20, 27, 18, -1, + -10, -6, -7, -3, -2, 9, 17, 19, 38, 51, 67, 66, + 47, 28, 6, -6, -8, 1, 9, -1, -2, 0, 2, 15, + 21, 20, 24, 7, -8, -16, -42, -33, -15, -20, -5, 15, + 7, -13, -31, -39, -31, -20, -9, -6, 1, 9, -6, 0, + 9, -10, -14, -9, -8, 23, 59, 75, 96, 109, 101, 73, + 54, 34, -7, -23, -31, -55, -71, -60, -18, 13, 26, 32, + 21, 9, 0, -13, -31, -41, -40, -28, -6, 6, 20, 26, + 6, -4, -14, -9, 16, 19, 0, -6, 13, 11, 3, 18, + 21, 13, -3, -9, -6, -12, -6, 5, 13, 33, 42, 24, + 10, 3, -20, -41, -49, -45, -19, -6, -6, 8, 6, 3, + 12, 0, -17, -20, -20, -8, 1, -3, 21, 38, 20, -1, + -24, -25, -17, -21, -3, 6, -3, -9, -28, -29, -20, -11, + 17, 11, -5, -14, -27, -8, 12, 11, -5, -12, -3, 1, + 22, 42, 41, 49, 47, 21, -3, -20, -30, -38, -46, -39, + -23, -14, -7, 4, 9, 9, 5, -9, -19, -27, -35, -26, + -13, -6, -2, -10, -8, -3, -6, -1, -5, -11, -6, 15, + 37, 56, 76, 69, 55, 61, 51, 31, 40, 43, 32, 35, + 16, -10, -28, -34, -31, -26, -7, 0, 6, 25, 28, 24, + 20, 10, 0, 2, 0, -27, -54, -59, -61, -56, -41, -16, + 5, 6, 15, 21, 14, 23, 16, 5, 10, 10, 18, 21, + 23, 27, 12, 3, 18, 37, 53, 59, 42, 14, -3, -7, + 6, 25, 24, 0, -24, -46, -57, -45, -31, -26, -24, -18, + -5, -7, -23, -31, -17, 3, 8, 20, 23, 11, 9, 9, + 6, -3, 0, 5, -6, -3, 3, 3, 13, 30, 59, 65, + 43, 32, 21, 3, -2, 10, 14, 17, 19, -5, -23, -28, + -45, -64, -69, -59, -51, -41, -50, -57, -40, -45, -38, -14, + -8, -1, 4, 8, -1, 3, -6, -60, -56, -33, -26, -12, + -14, -35, -39, 0, 19, 22, 23, 2, -21, -37, -43, -22, + -11, -13, -4, -22, -42, -49, -62, -43, -25, -21, -5, 8, + 28, 39, 17, -3, 0, -1, -2, -2, -9, -28, -58, -65, + -56, -42, 0, 52, 80, 76, 55, 23, -3, -12, -12, 3, + 4, -9, -8, -4, -2, -10, -21, -31, -35, -20, -3, 8, + 14, 11, 9, 13, 16, 8, 9, 7, 10, 24, 21, 15, + 4, -17, -38, -52, -55, -62, -56, -29, -35, -38, -22, -21, + -24, -38, -46, -43, -16, 33, 61, 82, 95, 93, 80, 53, + 28, 7, -10, -23, -47, -59, -47, -34, -27, -18, -6, -9, + 5, 27, 14, 14, 0, -14, 6, 7, -3, -35, -77, -83, + -75, -60, -37, -31, -35, -45, -61, -54, -30, -1, 34, 52, + 50, 42, 24, 21, 22, 21, 37, 30, 20, 25, 24, 25, + 10, -24, -48, -48, -41, -18, -3, -18, -28, -46, -51, -31, + -8, 9, 9, 17, 10, -20, -31, -25, -24, -21, -25, -39, + -27, -4, 15, 32, 32, 40, 26, 9, 14, 3, 1, -3, + -17, 8, 32, 33, 54, 52, 9, -13, -23, -32, -24, -8, + 11, 20, 25, 13, -10, -13, -21, -21, -19, -37, -28, -10, + -14, -5, 3, 3, 5, 1, 0, 9, 35, 45, 35, 23, + 3, -23, -48, -50, -39, -20, 10, 43, 67, 60, 57, 56, + 48, 37, 25, 29, 16, 10, 14, 3, -2, 2, 10, 0, + -4, 1, -20, -37, -35, -31, -24, -15, -16, -31, -45, -42, + -45, -54, -45, -43, -36, -14, 1, 18, 16, 3, 9, 10, + 9, 16, 24, 45, 64, 74, 78, 68, 50, 32, 37, 32, + 17, 26, 32, 21, 4, -3, 4, 23, 42, 46, 39, 31, + 18, -9, -27, -21, -14, -21, -22, -16, -31, -49, -52, -48, + -10, 27, 43, 46, 46, 59, 51, 32, 9, 6, 31, 33, + 20, -14, -41, -56, -79, -71, -50, -38, -15, 5, 2, 0, + -8, -29, -39, -49, -42, -21, -17, -17, -3, -3, -14, -1, + 7, 6, 8, 13, 4, -27, -46, -57, -64, -57, -48, -30, + -8, 1, 9, 9, -4, -10, -17, -7, 20, 16, 11, 13, + 10, 0, -16, -10, -12, -11, -12, -24, -31, -24, 12, 18, + 16, 42, 41, 34, 31, 3, -6, -11, -27, -16, -9, -9, + -9, -27, -22, 1, 6, 1, 5, 27, 48, 53, 32, -1, + -3, -3, -17, -22, -9, 12, 22, 45, 61, 75, 110, 120, + 106, 100, 81, 58, 54, 30, 3, -4, -6, -1, 0, 11, + 21, 25, 28, 25, 41, 42, 35, 25, -4, -38, -65, -60, + -43, -32, -38, -54, -41, -20, -14, 3, 6, 0, 13, 19, + 17, 13, 7, -18, -45, -55, -67, -58, -27, 3, 24, 28, + 10, -6, -20, -35, -24, -4, 3, -10, -26, -42, -55, -46, + -36, -40, -39, -23, -18, -6, 13, 11, 20, 28, 17, 13, + 14, 19, 27, 26, 4, -8, -9, -19, -6, 21, 41, 46, + 27, -4, -23, -24, -11, 14, 23, 35, 58, 61, 53, 28, + -12, -44, -53, -50, -56, -63, -90, -104, -75, -60, -54, -39, + -43, -50, -42, -27, -17, 1, 28, 27, 14, 14, 18, 3, + -21, -36, -45, -20, 10, 35, 59, 56, 56, 40, 6, 0, + 10, 14, 20, 36, 30, 4, 13, 44, 52, 49, 49, 36, + 24, 14, 5, -4, -27, -35, -38, -46, -43, -27, -4, 4, + 19, 33, 36, 24, 4, 3, -2, -14, -25, -29, -41, -64, + -70, -71, -62, -28, 17, 52, 54, 38, 38, 47, 46, 34, + 23, 42, 67, 59, 42, 23, 5, -10, -39, -61, -57, -50, + -35, -6, -2, -12, 3, 14, 14, 10, 4, 15, 41, 52, + 35, 29, 36, 47, 67, 65, 27, -2, -6, -18, -14, -6, + 3, 36, 45, 48, 52, 19, 0, -2, -1, 16, 22, 42, + 65, 60, 49, 35, -9, -63, -86, -96, -86, -63, -54, -47, + -48, -48, -29, -24, -23, -29, -41, -36, -38, -28, 2, 19, + 20, 6, -6, -3, 20, 44, 38, 33, 45, 39, 19, 0, + -9, 3, -1, 0, 18, 14, 23, 24, 10, 14, 20, 48, + 58, 45, 34, 8, -13, -39, -60, -64, -54, -22, -2, 18, + 39, 28, 7, -1, -10, -26, -28, -39, -49, -56, -64, -57, + -40, -17, -7, 3, 4, 0, 0, 2, 20, 32, 24, 2, + -20, -39, -49, -66, -77, -53, -41, -21, 1, 1, 21, 22, + 5, 14, 11, 6, 13, 8, 9, 6, -14, -28, -39, -26, + 0, 3, 2, 0, -8, -10, -9, -9, 0, 9, 14, 10, + 22, 56, 63, 59, 58, 35, 7, 6, 33, 53, 54, 27, + 0, -11, -24, -25, -12, -11, -24, -25, -13, -16, -13, -6, + -15, -17, -29, -41, -28, -15, 14, 16, -16, -25, -33, -14, + 7, 11, 12, 10, 19, 25, 31, 35, 42, 56, 49, 28, + 11, 17, 39, 57, 52, 37, 39, 50, 38, 21, 24, 28, + 31, 24, 8, -10, -26, -10, 17, 11, -4, 3, 3, -2, + 3, 16, 42, 29, -1, -16, -31, -31, -35, -60, -68, -47, + -24, -4, 0, -3, -21, -56, -53, -41, -50, -40, -34, -52, + -54, -57, -75, -60, -35, -24, -11, -7, 0, -10, -27, -12, + -5, -4, -14, -33, -32, -12, 20, 41, 56, 53, 32, 25, + -8, -32, -28, -43, -54, -61, -59, -35, -28, -31, -18, -10, + -3, 21, 32, 25, 20, 25, 26, 13, -2, -24, -28, -22, + -25, -16, 3, 23, 28, 36, 45, 35, 30, 27, 30, 26, + 21, 6, -31, -42, -49, -50, -39, -42, -29, -22, -30, -30, + -26, -10, 7, 7, 6, 24, 40, 47, 47, 30, 13, -7, + -11, 22, 54, 84, 94, 74, 71, 54, 30, 28, 16, 19, + 13, -1, 4, 1, 19, 31, 16, 3, -10, -9, -13, -18, + -13, -21, -29, -42, -60, -52, -28, -4, 10, 9, 10, 4, + -3, 3, -4, -14, -21, -36, -55, -56, -32, 2, 38, 48, + 35, 37, 44, 50, 53, 49, 31, -1, -17, -16, 1, 27, + 25, 10, -21, -62, -73, -49, -18, 4, 13, -10, -46, -41, + -11, 4, 22, 34, 27, 17, 3, -6, -13, -4, 3, -5, + -9, -14, -3, 10, 17, 25, 9, -9, 0, 27, 36, 30, + 27, 23, 20, 14, 14, 6, 4, 6, -25, -39, -44, -55, + -60, -56, -47, -48, -40, -34, -28, -18, -19, -28, -43, -40, + -35, -40, -39, -24, -1, 15, 34, 45, 54, 74, 77, 64, + 35, 12, 14, 16, 5, -6, 0, 16, 29, 27, 7, 4, + 7, 0, 0, 2, -19, -27, -21, -31, -32, -45, -39, -17, + -33, -42, -22, 1, 13, 10, -3, -10, -28, -31, -10, 8, + 37, 51, 41, 28, 24, 17, 2, 0, 1, -3, 9, 17, + 19, 42, 49, 53, 57, 43, 49, 53, 42, 42, 42, 35, + 29, 22, 17, 21, 6, -17, -8, 0, 3, 37, 65, 59, + 37, 14, 1, -30, -45, -39, -44, -34, -18, -14, -24, -32, + -30, -16, -2, 20, 60, 73, 81, 96, 73, 53, 45, 28, + 5, -12, -7, -8, -8, -2, -24, -39, -28, -19, -3, 24, + 33, 45, 59, 41, 12, -14, -40, -35, -31, -48, -61, -65, + -69, -70, -59, -45, -24, -7, -9, -3, 23, 46, 49, 48, + 19, -2, 6, 24, 27, 9, -1, -34, -64, -80, -90, -68, + -49, -38, -23, -9, 15, 32, 38, 44, 27, -13, -39, -56, + -60, -52, -52, -32, -14, -14, 4, 3, -15, -22, -42, -57, + -65, -68, -60, -49, -18, 23, 31, 29, 35, 17, 0, -2, + -2, -4, -13, -10, -8, -10, -10, -14, -24, -31, -23, -14, + 7, 16, 11, 23, 24, 27, 17, -15, -17, 1, -2, -30, + -51, -63, -69, -57, -45, -25, 2, 21, 28, 25, 25, 37, + 55, 59, 52, 49, 47, 44, 36, 21, 13, 12, 9, 13, + 17, 30, 52, 61, 62, 70, 86, 81, 63, 53, 34, 12, + 6, -3, -20, -32, -57, -84, -93, -85, -49, -15, 2, 20, + 36, 34, 17, 26, 32, 23, 28, 12, -20, -35, -28, -17, + 3, 43, 52, 52, 60, 45, 26, 6, -1, 3, 3, 20, + 28, 28, 20, 15, 26, 18, 17, 9, -13, -20, -24, -23, + -18, -18, -31, -53, -67, -59, -40, -28, -17, -11, -27, -44, + -14, 17, 21, 25, 11, -15, -32, -43, -31, -11, -14, -6, + -12, -39, -45, -60, -52, -27, -24, -11, 4, 20, 39, 26, + 1, -2, 0, -3, -1, -6, -20, -49, -66, -58, -49, -17, + 35, 75, 80, 63, 35, 4, -10, -14, -3, 6, -6, -10, + -5, -2, -6, -18, -28, -36, -26, -8, 5, 13, 13, 9, + 10, 16, 10, 8, 9, 7, 21, 23, 16, 9, -10, -32, + -49, -54, -60, -61, -38, -20, -11, -12, -20, -17, 0, 14, + 7, 14, 32, 16, -4, -2, -13, -28, -20, -1, 1, 2, + 6, 3, 27, 56, 65, 71, 80, 75, 64, 60, 32, 6, + 2, 10, 17, 12, 8, 11, 24, 22, -7, -12, 2, 18, + 33, 35, 44, 57, 67, 57, 35, 24, 6, -12, -29, -30, + -32, -50, -31, -9, 16, 52, 60, 54, 47, 38, 23, 9, + 5, 2, -1, 6, 9, -20, -38, -34, -31, -15, 4, 7, + 4, 9, 13, 32, 42, 25, 8, -9, -41, -71, -68, -45, + -25, -13, -13, -1, 13, 19, 42, 48, 42, 34, -3, -38, + -54, -54, -57, -52, -28, -13, 12, 31, 30, 20, 3, 18, + 41, 56, 75, 69, 48, 16, -20, -35, -41, -39, -20, -14, + -10, -10, -23, -23, -30, -31, -42, -75, -78, -69, -63, -48, + -53, -55, -54, -70, -42, -5, 2, -10, -28, -25, -31, -27, + -8, -8, -10, -8, -10, 6, 27, 38, 52, 42, 23, 21, + 24, 23, 18, 17, 13, 16, 17, 11, 20, 23, 17, 17, + 23, 13, -13, -13, -9, -9, -6, -3, 3, -2, -2, 6, + 7, -5, 5, 23, 10, 2, 6, -4, -17, -17, -24, -25, + -10, -9, 6, 25, 45, 79, 89, 89, 81, 60, 38, 11, + -14, -32, -34, -23, -20, -16, -6, 13, 31, 38, 35, 17, + -10, -44, -60, -60, -52, -25, -10, -5, -11, -25, -30, -38, + -44, -45, -34, -13, 25, 52, 50, 59, 53, 30, 31, 42, + 59, 82, 78, 68, 39, -2, -6, -10, -7, 6, 13, 25, + 28, 27, 22, 19, 28, 35, 34, 29, 20, -9, -46, -74, +-114, -146, -144, -117, -89, -63, -32, -12, -3, -9, -17, -13, + -11, -4, 0, 0, -19, -43, -39, -28, -10, 6, 7, 21, + 46, 61, 77, 85, 83, 71, 55, 50, 27, -13, -45, -59, + -59, -46, -25, -16, -10, 7, 26, 34, 31, 17, -1, -14, + -22, -32, -31, -17, -32, -59, -54, -43, -30, -11, -13, -16, + -18, -13, 3, -7, -38, -57, -62, -71, -71, -46, -13, 2, + 7, 14, 30, 38, 23, 9, -1, -15, -30, -41, -50, -70, + -78, -71, -56, -35, -23, -2, 34, 61, 73, 77, 74, 59, + 45, 32, 4, -6, 2, -10, -24, -16, -1, 9, 21, 35, + 46, 67, 81, 61, 44, 34, 20, 41, 57, 68, 84, 71, + 60, 42, 20, 12, -2, -9, 5, 27, 32, 34, 29, 3, + -6, -10, -20, -25, -41, -41, -21, -12, -25, -42, -28, -14, + -16, -11, 3, 7, 10, 38, 62, 70, 65, 59, 53, 39, + 30, 34, 35, 28, 17, 7, 14, 28, 20, 15, 5, -1, + -7, -19, -21, -24, -19, -21, -28, -27, -41, -36, -3, 9, + 5, 9, 6, 2, 3, 2, 0, 2, -2, -4, 14, 21, + 23, 19, 4, -18, -53, -65, -61, -53, -27, 7, 13, -10, + -17, -17, -13, 13, 13, 16, 28, 6, -6, -25, -45, -47, + -49, -35, -12, -8, -16, -18, -23, -17, -14, -22, -12, -2, + -8, -6, -1, -10, -13, -14, -24, -29, -31, -25, -6, 23, + 39, 50, 61, 36, 13, 17, 28, 17, 0, -6, -15, -6, + -5, -18, -27, -43, -36, -7, 6, 11, 16, 16, 4, -14, + -42, -62, -46, -45, -57, -79, -98, -86, -71, -60, -45, -9, + 27, 43, 59, 57, 48, 53, 63, 53, 34, 51, 61, 45, + 50, 48, 31, 36, 44, 39, 39, 33, 9, 2, 13, 16, + 46, 64, 51, 49, 43, 36, 26, 9, -10, -34, -46, -35, + -12, 8, 19, 7, 0, 5, -7, -7, 4, 30, 60, 62, + 56, 46, 39, 42, 42, 39, 31, 11, -11, -39, -63, -65, + -61, -52, -48, -49, -38, -38, -45, -45, -34, -21, -6, 4, + 1, 10, 10, 3, 2, -24, -44, -49, -53, -71, -78, -45, + -10, -3, 7, 30, 26, 28, 27, -3, -2, 15, 24, 34, + 39, 31, 12, 6, 9, -1, -17, -18, -12, -13, -8, 10, + 10, 1, 13, 14, 1, -9, -20, -31, -38, -42, -52, -45, + -39, -47, -51, -59, -56, -46, -32, -24, -34, -30, -22, -9, + 11, 17, 6, -11, -7, 1, -1, 7, 34, 50, 26, 7, + -6, -13, -2, -13, -34, -45, -38, -18, -3, 10, 13, 2, + -12, -5, 4, 5, 7, -7, -26, -43, -52, -39, -10, 18, + 42, 59, 43, 22, 12, 13, 21, -1, -29, -28, -14, -5, + 2, 14, 28, 31, 41, 63, 68, 74, 77, 55, 27, 2, + -23, -45, -53, -60, -75, -56, -31, -38, -34, -11, 5, 24, + 39, 34, 31, 25, 1, 3, 7, -2, 11, 19, 24, 20, + 3, -3, 10, 27, 31, 34, 47, 58, 59, 63, 63, 42, + 28, 14, -5, -6, -6, 7, 31, 39, 37, 26, 8, 3, + 15, 27, 30, 38, 42, 41, 30, 16, 9, 1, -4, -9, + -18, -25, -40, -49, -28, -1, 1, 1, 6, 0, -18, -36, + -48, -52, -36, -20, -13, -11, -19, -7, 10, 19, 12, -3, + -15, -29, -19, -3, 11, 23, 29, 28, 4, -9, -22, -39, + -35, -39, -41, -42, -41, -25, -16, -1, 4, 2, -3, -18, + -20, -23, -25, -40, -57, -43, -33, -24, -7, -11, -17, -18, + -21, -7, 6, 2, 0, 2, 3, -2, -4, -17, -41, -49, + -44, -37, -35, -30, -22, -12, 6, 16, 38, 74, 81, 64, + 36, 9, -18, -32, -27, -16, -3, 2, 1, -17, -30, -34, + -32, -18, -4, 16, 31, 37, 50, 48, 35, 42, 42, 25, + 18, 10, 8, 31, 45, 42, 51, 66, 64, 50, 39, 24, + 5, 4, 21, 32, 17, 0, 7, 29, 52, 54, 34, 7, + -13, -24, -38, -46, -43, -20, 5, 17, 20, 8, -2, -8, + -14, -18, -7, 18, 41, 51, 41, 36, 14, 3, 20, 13, + 19, 41, 37, 27, 31, 33, 36, 39, 21, 13, -1, -16, + -22, -38, -31, -22, -4, 15, 0, -25, -34, -5, 7, 2, + 1, -14, -15, -5, 0, -6, -14, -17, -42, -61, -38, -15, + -6, 5, 14, 9, -9, -14, -16, -28, -42, -46, -47, -60, + -52, -35, -27, -6, -1, -13, -27, -33, -43, -45, -25, -38, + -62, -57, -42, -20, 4, 34, 50, 56, 52, 34, 30, 11, + -17, -39, -44, -42, -50, -41, -47, -74, -96, -96, -73, -38, + 8, 43, 47, 30, 16, 4, 5, 16, 12, -5, -29, -37, + -28, -4, 17, 2, 7, 28, 20, 24, 47, 42, 19, 16, + 13, 3, 0, -3, -17, -34, -48, -60, -49, -10, 23, 24, + 13, -4, -27, -33, -39, -28, -14, -16, -2, 14, 32, 32, + 36, 53, 57, 74, 89, 96, 87, 65, 50, 21, 3, 1, + 0, -4, -20, -35, -39, -10, 39, 52, 45, 35, 31, 41, + 28, 10, 11, -3, -34, -45, -35, -24, -3, 7, -5, 9, + 26, 37, 57, 47, 35, 14, -20, -46, -66, -57, -35, -15, + -24, -33, -11, -2, 0, 0, 0, -1, 9, 12, -11, -24, + -32, -17, -7, -9, -4, -16, -17, -28, -32, -18, -27, -13, + 9, 17, 23, 12, 1, 6, 0, -24, -41, -36, -25, -26, + -18, -3, -3, -3, 11, 23, 27, 43, 36, 29, 49, 53, + 57, 52, 28, 4, -13, 8, 24, 16, 11, -8, -17, -12, + 1, 28, 27, 9, 1, -18, -41, -48, -50, -56, -53, -62, + -85, -100, -107, -101, -78, -41, -9, 20, 50, 66, 66, 57, + 38, 24, 24, 16, 14, 9, -6, 0, -6, -8, 4, -7, + -1, 25, 36, 33, 30, 25, 26, 31, 23, 7, -4, -6, + -15, -25, -20, -26, -29, -3, 23, 27, 38, 59, 64, 67, + 75, 66, 45, 29, 22, 14, -3, -20, -31, -47, -46, -31, + -19, 11, 48, 67, 70, 59, 35, 0, -24, -26, -14, 1, + 1, -12, -13, -17, -24, -19, -13, -1, 11, 20, 38, 49, + 45, 46, 35, 16, 12, 0, -18, -17, -13, -15, -18, -14, + -17, -28, -13, 10, 17, 9, 0, -10, -13, -3, 11, 30, + 37, 43, 38, 22, 16, 4, -1, 19, 34, 29, 21, 8, + -9, -21, -37, -41, -34, -28, -31, -53, -69, -61, -45, -45, + -54, -44, -49, -60, -53, -43, -39, -42, -23, -9, -13, -10, + -17, -17, -3, 0, 1, 10, 4, -2, 14, 20, 31, 53, + 82, 103, 96, 84, 62, 43, 25, 3, -19, -52, -57, -43, + -49, -31, -6, 9, 28, 31, 32, 34, 26, 26, 32, 35, + 28, 9, -14, -25, -14, -5, -1, -4, -30, -36, -31, -20, + 5, -2, -21, -31, -42, -46, -41, -31, -26, -23, -30, -38, + -28, -23, -11, 10, 21, 12, 0, 3, -3, -11, -24, -52, + -67, -57, -33, -19, 4, 36, 33, 17, 0, -16, -17, -10, + 7, 28, 33, 31, 38, 35, 27, 32, 35, 34, 30, 25, + 18, 8, 6, -8, -28, -19, -15, -10, 10, 18, 30, 45, + 59, 65, 38, 18, 27, 23, 9, -8, -31, -30, -29, -36, + -38, -56, -63, -46, -36, -32, -11, -3, -28, -33, -35, -60, + -64, -32, -2, 10, 21, 29, 32, 38, 53, 58, 39, 31, + 28, 32, 46, 38, 29, 20, 17, 15, 17, 40, 54, 47, + 23, -3, -21, -14, -2, -13, -17, -17, -10, -13, -13, 6, + -3, -21, -29, -34, -38, -42, -43, -41, -32, -30, -42, -44, + -36, -34, -20, -13, -22, -24, -27, -32, -49, -53, -39, -38, + -34, -31, -52, -67, -49, -35, -18, 17, 45, 55, 62, 53, + 17, 13, 19, 7, -6, -28, -22, -9, -24, -52, -82, -79, + -44, -10, 10, 32, 56, 64, 56, 31, 6, 13, 30, 29, + 27, 20, 21, 49, 77, 70, 56, 65, 77, 84, 87, 77, + 53, 13, -20, -39, -61, -78, -82, -87, -88, -70, -38, 0, + 34, 42, 37, 28, 3, -25, -53, -64, -59, -62, -56, -41, + -32, -17, 7, 37, 45, 24, 12, 8, 12, 19, 28, 49, + 54, 42, 50, 53, 53, 59, 31, 8, -6, -23, 0, 17, + 7, 30, 60, 62, 53, 43, 38, 27, 30, 39, 31, 25, + 24, 24, 8, -10, -12, -35, -58, -45, -26, -10, 13, 28, + 45, 67, 67, 43, 16, -19, -45, -42, -46, -47, -41, -45, + -46, -43, -23, -1, -1, -2, 2, -14, -38, -38, -20, -4, + 6, 3, -1, 4, 5, 4, 12, 21, 19, 13, 6, 0, + 13, 28, 17, -16, -39, -32, -36, -36, -32, -41, -28, 10, + 53, 86, 92, 69, 50, 49, 44, 42, 40, 40, 42, 23, + 1, -18, -39, -27, -13, -32, -35, -26, -28, -26, -10, 1, + -15, -41, -61, -70, -86, -101, -90, -77, -54, -36, -49, -41, + -32, -40, -43, -50, -47, -30, -7, 14, 35, 52, 48, 45, + 49, 49, 53, 59, 50, 21, 0, -10, -18, -14, -1, 19, + 34, 40, 33, 14, 4, -3, -6, 3, 13, 28, 27, 21, + 35, 41, 38, 34, 24, 7, -13, -21, -28, -16, -1, 11, + 27, 26, 24, 32, 43, 42, 43, 38, 40, 49, 34, 31, + 23, 4, -5, -16, -36, -60, -59, -38, -24, -7, 4, -10, + -32, -46, -51, -59, -56, -36, -23, 4, 31, 29, 12, -2, + -9, -27, -35, -27, -37, -42, -28, -16, 0, 18, 29, 31, + 32, 23, 1, -3, 1, 0, 7, 31, 70, 95, 88, 73, + 50, 17, 1, -4, -17, -22, -17, -5, 21, 32, 39, 44, + 33, 30, 11, -24, -36, -46, -64, -65, -59, -64, -53, -25, + -10, -2, -9, -45, -78, -78, -63, -38, -6, -7, -11, 5, + 2, -10, -17, -21, -38, -43, -36, -29, -1, 4, -10, -3, + -1, -9, -11, -21, -29, -23, -20, -7, 17, 16, -6, -14, + -25, -37, -19, -7, 3, 26, 27, 38, 55, 42, 20, -10, + -39, -46, -43, -41, -30, -4, 24, 43, 48, 45, 41, 31, + 25, 17, 20, 35, 43, 49, 21, -16, -34, -60, -56, -32, + -31, -27, -23, -5, 23, 21, 28, 25, 7, 13, 7, -11, + -10, 1, 7, 17, 21, 18, 14, 14, 24, 24, 10, 4, + 9, 14, 25, 25, 20, 39, 39, 21, 30, 30, 34, 35, + 23, 40, 58, 66, 81, 77, 60, 45, 24, 3, -6, -2, + -12, -23, -31, -47, -39, -24, -27, -10, 1, -21, -48, -71, + -64, -30, -4, 16, 23, 14, 13, 4, -19, -36, -38, -33, + -29, -24, -23, -11, 1, 3, 21, 28, 20, 30, 57, 85, + 84, 66, 42, -2, -27, -25, -27, -11, 17, 10, -1, -14, + -38, -26, -20, -28, -9, -5, -3, 8, -2, -9, -6, -3, + -23, -50, -46, -24, -9, -4, -3, -19, -26, 3, 11, -18, + -35, -47, -56, -48, -46, -18, 14, 14, 28, 38, 25, 17, + 10, 16, 24, 20, 9, -2, 3, -4, -11, 6, 20, 31, + 43, 49, 46, 47, 54, 62, 56, 36, 25, 7, 13, 30, + 24, 39, 51, 51, 26, 1, 2, -11, -22, -38, -69, -81, + -78, -79, -70, -64, -49, -8, -16, -25, -6, -32, -52, -60, + -80, -81, -79, -74, -57, -48, -49, -48, -57, -68, -66, -75, + -81, -70, -48, -24, 1, 27, 38, 67, 85, 76, 84, 78, + 71, 58, 52, 63, 60, 81, 102, 92, 97, 96, 86, 78, + 66, 88, 104, 98, 100, 96, 118, 131, 123, 129, 124, 122, + 120, 112, 97, 64, 31, 3, -16, -20, -16, 0, 17, 7, + -4, -6, -4, -1, -3, 3, -3, -17, -28, -52, -74, -100, +-134, -153, -182, -203, -197, -179, -160, -160, -159, -150, -151, -151, +-149, -171, -199, -208, -204, -190, -174, -167, -172, -181, -201, -221, +-217, -200, -165, -110, -79, -61, -34, -19, -9, 16, 54, 95, + 139, 170, 181, 204, 236, 271, 334, 394, 426, 458, 482, 498, + 504, 495, 512, 536, 553, 566, 562, 515, 450, 411, 354, 307, + 280, 219, 155, 92, 22, -59, -152, -237, -298, -336, -371, -413, +-473, -507, -508, -538, -591, -639, -676, -691, -687, -681, -684, -695, +-723, -741, -728, -711, -674, -649, -644, -602, -554, -486, -400, -325, +-246, -181, -129, -74, -13, 42, 103, 170, 223, 273, 340, 430, + 523, 608, 677, 737, 796, 831, 871, 908, 913, 947, 1000, 1028, +1033, 1024, 1000, 957, 907, 853, 793, 740, 676, 573, 465, 361, + 251, 149, 57, -25, -127, -214, -288, -391, -465, -526, -600, -681, +-759, -820, -881, -922, -970, -1027, -1054, -1070, -1055, -1006, -954, -905, +-852, -801, -762, -702, -613, -527, -460, -399, -322, -239, -143, -46, + 34, 96, 150, 207, 258, 309, 356, 407, 473, 526, 577, 618, + 621, 620, 634, 639, 640, 638, 633, 652, 662, 635, 583, 534, + 494, 432, 400, 399, 397, 403, 391, 367, 350, 333, 298, 239, + 181, 117, 42, -31, -101, -188, -275, -331, -360, -360, -340, -305, +-276, -287, -318, -371, -438, -488, -524, -544, -560, -568, -555, -543, +-497, -423, -404, -398, -384, -401, -398, -386, -380, -301, -189, -75, + 51, 151, 238, 299, 343, 374, 379, 396, 417, 428, 428, 400, + 371, 349, 314, 289, 267, 264, 282, 272, 241, 180, 88, -31, +-173, -301, -415, -504, -543, -537, -505, -450, -375, -318, -287, -275, +-295, -304, -292, -259, -181, -74, 42, 164, 302, 406, 473, 549, + 587, 561, 509, 435, 378, 373, 388, 398, 407, 435, 439, 405, + 370, 319, 267, 245, 202, 132, 80, 29, -14, -63, -133, -209, +-286, -336, -351, -381, -429, -448, -441, -438, -413, -381, -357, -285, +-189, -111, -33, 53, 135, 196, 217, 235, 262, 261, 255, 236, + 207, 199, 180, 136, 89, 37, -24, -63, -114, -196, -225, -217, +-221, -260, -359, -468, -581, -696, -772, -815, -790, -695, -583, -454, +-335, -222, -105, -15, 20, -10, -32, 38, 183, 347, 524, 701, + 874, 1016, 1071, 1053, 1007, 963, 891, 757, 597, 456, 409, 462, + 513, 501, 446, 395, 343, 283, 199, 75, -40, -146, -268, -383, +-483, -539, -547, -557, -601, -648, -657, -641, -644, -671, -693, -697, +-656, -576, -493, -375, -218, -70, 54, 134, 174, 227, 269, 258, + 229, 209, 205, 253, 326, 368, 409, 436, 407, 345, 246, 108, + -27, -132, -214, -265, -278, -250, -225, -247, -299, -396, -514, -619, +-726, -760, -700, -608, -514, -435, -312, -135, 15, 79, 27, -62, + -79, -9, 96, 231, 415, 622, 798, 880, 892, 882, 884, 875, + 753, 554, 376, 294, 338, 411, 453, 447, 388, 330, 285, 232, + 191, 158, 94, -36, -224, -389, -447, -418, -386, -407, -477, -562, +-637, -671, -662, -623, -572, -554, -558, -540, -436, -242, -56, 50, + 79, 72, 60, 74, 104, 118, 153, 243, 342, 421, 533, 655, + 718, 692, 534, 295, 82, -56, -159, -286, -410, -436, -321, -161, + -72, -80, -181, -356, -555, -751, -905, -906, -758, -586, -473, -422, +-326, -119, 115, 215, 107, -81, -196, -173, -44, 135, 378, 668, + 915, 1064, 1113, 1107, 1134, 1146, 1002, 683, 293, 28, -27, 39, + 123, 168, 232, 353, 468, 540, 558, 490, 337, 89, -274, -620, +-829, -890, -838, -793, -783, -743, -624, -452, -318, -255, -271, -319, +-346, -328, -244, -94, 101, 259, 352, 364, 336, 334, 292, 176, + 16, -122, -175, -148, -27, 138, 265, 332, 248, 3, -288, -589, +-847, -1063, -1286, -1420, -1312, -883, -277, 230, 493, 519, 372, 115, +-134, -240, -74, 388, 964, 1466, 1832, 2128, 2414, 2542, 2271, 1477, + 330, -779, -1567, -2018, -2221, -2184, -1922, -1533, -1165, -879, -598, -253, + 125, 338, 242, 51, 93, 450, 982, 1435, 1593, 1507, 1341, 1143, + 843, 398, -123, -700, -1325, -1919, -2327, -2373, -2026, -1466, -969, -623, +-270, 209, 753, 1216, 1458, 1474, 1410, 1386, 1442, 1561, 1745, 1928, +1957, 1777, 1455, 1129, 828, 468, 1, -582, -1143, -1503, -1633, -1542, +-1292, -1043, -912, -916, -977, -1001, -979, -978, -1032, -1110, -1129, -1057, +-966, -871, -699, -408, -49, 257, 351, 183, -95, -340, -501, -498, +-178, 540, 1481, 2332, 2828, 2886, 2691, 2366, 1766, 757, -549, -1814, +-2676, -2936, -2671, -2084, -1324, -538, 49, 324, 431, 563, 835, 1174, +1347, 1321, 1317, 1548, 2005, 2331, 2154, 1418, 311, -858, -1845, -2551, +-2971, -3100, -2985, -2704, -2202, -1376, -218, 1026, 2045, 2712, 2993, 3035, +2982, 2786, 2384, 1766, 999, 168, -628, -1231, -1563, -1636, -1545, -1442, +-1392, -1346, -1215, -1037, -885, -677, -363, 36, 452, 772, 978, 1088, +1115, 1005, 648, 138, -394, -925, -1418, -1848, -2174, -2277, -2152, -2016, +-1976, -1822, -1206, -68, 1159, 2001, 2246, 1994, 1493, 845, 187, -169, + 122, 1055, 2074, 2606, 2530, 2110, 1675, 1127, 89, -1481, -3108, -4091, +-4145, -3490, -2433, -1204, 68, 1105, 1569, 1507, 1388, 1698, 2346, 2794, +2739, 2382, 2191, 2278, 2225, 1513, 38, -1731, -3263, -4296, -4713, -4478, +-3644, -2445, -1276, -381, 386, 1304, 2344, 3117, 3312, 3007, 2558, 2248, +1999, 1539, 788, -148, -1172, -2187, -2988, -3300, -2966, -2071, -983, -147, + 336, 711, 1138, 1508, 1639, 1527, 1345, 1211, 1088, 876, 571, 292, + 30, -383, -1035, -1766, -2257, -2368, -2172, -1795, -1355, -830, -211, 271, + 420, 349, 413, 784, 1131, 991, 309, -551, -1266, -1808, -2111, -1847, +-669, 1323, 3295, 4329, 4211, 3422, 2513, 1535, 150, -1747, -3583, -4536, +-4355, -3410, -2185, -888, 366, 1260, 1488, 1139, 853, 1278, 2333, 3304, +3577, 3253, 2855, 2577, 2032, 705, -1374, -3593, -5223, -5932, -5759, -4778, +-3197, -1421, 74, 1030, 1641, 2280, 3057, 3628, 3636, 3163, 2537, 1975, +1430, 714, -256, -1369, -2486, -3498, -4161, -4121, -3169, -1552, 134, 1342, +1983, 2343, 2573, 2590, 2306, 1829, 1375, 1047, 745, 341, -95, -465, +-777, -1184, -1825, -2493, -2805, -2608, -2032, -1291, -551, 98, 599, 779, + 498, -16, -283, -82, 247, 299, 65, -278, -607, -883, -983, -575, + 631, 2370, 3727, 3974, 3220, 2076, 1049, 148, -956, -2378, -3687, -4200, +-3729, -2638, -1289, 174, 1520, 2292, 2278, 1749, 1388, 1801, 2745, 3349, +3129, 2376, 1557, 753, -259, -1734, -3592, -5240, -6082, -5969, -5004, -3320, +-1236, 733, 2154, 2841, 2980, 3008, 3153, 3235, 2982, 2437, 1788, 1069, + 303, -515, -1438, -2352, -3114, -3604, -3577, -2809, -1317, 549, 2267, 3368, +3648, 3300, 2627, 1846, 1121, 610, 329, 41, -376, -855, -1290, -1538, +-1603, -1660, -1853, -2063, -2015, -1615, -871, 134, 1045, 1448, 1199, 395, +-616, -1165, -884, -251, 59, -148, -680, -1222, -1477, -1242, -429, 1081, +3082, 4704, 5101, 4213, 2698, 1158, -249, -1635, -3123, -4350, -4657, -3881, +-2495, -1024, 372, 1581, 2316, 2313, 1673, 995, 1014, 1825, 2675, 2872, +2424, 1650, 686, -602, -2322, -4195, -5607, -6035, -5429, -4078, -2228, -190, +1647, 2937, 3433, 3242, 2769, 2405, 2215, 2020, 1789, 1526, 1101, 385, +-647, -1822, -2800, -3291, -3292, -2876, -1919, -390, 1426, 3064, 4068, 4163, +3408, 2155, 795, -333, -893, -792, -399, -218, -507, -1157, -1797, -2070, +-1932, -1652, -1368, -987, -459, 166, 789, 1251, 1319, 795, -355, -1871, +-3038, -3022, -1813, -297, 633, 697, 192, -431, -775, -543, 521, 2556, +4937, 6377, 6097, 4357, 2048, -97, -1964, -3711, -5279, -6129, -5680, -4107, +-2107, -190, 1442, 2611, 3037, 2581, 1634, 1154, 1771, 3035, 3881, 3674, +2599, 1130, -504, -2349, -4303, -5867, -6451, -5830, -4283, -2264, -128, 1800, +3121, 3516, 3026, 2205, 1734, 1817, 2181, 2463, 2433, 1986, 1080, -270, +-1846, -3120, -3671, -3494, -2806, -1754, -345, 1359, 2995, 3957, 3873, 2904, +1527, 169, -881, -1369, -1180, -527, 78, 116, -519, -1456, -2110, -2149, +-1689, -1048, -462, 78, 572, 884, 926, 655, 43, -887, -2060, -3235, +-3754, -2943, -995, 1040, 2174, 2178, 1359, 206, -705, -831, 288, 2673, +5375, 6860, 6260, 3960, 1002, -1747, -3890, -5394, -6236, -6105, -4784, -2698, +-555, 1297, 2700, 3388, 3149, 2056, 749, 238, 1041, 2559, 3641, 3668, +2688, 989, -1142, -3444, -5518, -6733, -6552, -5060, -2903, -695, 1224, 2600, +3233, 3053, 2232, 1357, 1035, 1354, 1984, 2558, 2788, 2395, 1215, -579, +-2496, -3877, -4267, -3675, -2453, -941, 694, 2220, 3326, 3735, 3335, 2290, + 949, -317, -1223, -1494, -1025, -179, 404, 257, -617, -1740, -2438, -2335, +-1585, -613, 272, 870, 1023, 790, 381, -121, -788, -1612, -2489, -2992, +-2413, -731, 1173, 2309, 2258, 1246, -199, -1335, -1372, 186, 3155, 6325, +7954, 7085, 4222, 683, -2459, -4764, -6144, -6614, -6123, -4686, -2693, -720, + 929, 2192, 2819, 2572, 1644, 676, 518, 1550, 3146, 4183, 4053, 2859, + 939, -1408, -3867, -5910, -6906, -6480, -4790, -2482, -236, 1546, 2637, 2885, +2424, 1659, 1084, 1108, 1727, 2540, 3126, 3306, 2899, 1650, -358, -2557, +-4177, -4673, -4001, -2544, -749, 1055, 2539, 3339, 3311, 2664, 1701, 671, +-208, -805, -976, -563, 224, 767, 573, -370, -1665, -2688, -2909, -2246, +-1040, 269, 1282, 1686, 1398, 647, -240, -1099, -1944, -2769, -3355, -3144, +-1759, 285, 1955, 2582, 2111, 859, -646, -1664, -1318, 919, 4437, 7448, +8198, 6293, 2705, -1170, -4416, -6585, -7330, -6639, -4890, -2707, -799, 526, +1449, 2065, 2166, 1658, 891, 612, 1334, 2760, 4061, 4511, 3853, 2243, + -51, -2735, -5218, -6718, -6750, -5371, -3104, -739, 1039, 1984, 2148, 1673, + 944, 517, 760, 1710, 2987, 4010, 4411, 4046, 2838, 811, -1661, -3841, +-5057, -5006, -3849, -2065, -114, 1654, 2867, 3229, 2759, 1823, 876, 159, +-217, -199, 181, 803, 1272, 1075, 50, -1429, -2732, -3327, -2915, -1667, +-178, 971, 1433, 1213, 543, -218, -769, -1129, -1487, -2000, -2591, -2687, +-1705, 94, 1796, 2664, 2506, 1459, -160, -1655, -1995, -401, 2866, 6245, +7796, 6673, 3561, -230, -3657, -6021, -6831, -6010, -3983, -1577, 184, 865, + 884, 739, 518, 188, -42, 254, 1310, 2825, 4139, 4624, 4105, 2761, + 759, -1654, -4037, -5748, -6233, -5348, -3459, -1343, 254, 1022, 1054, 593, + 73, 34, 748, 2077, 3552, 4593, 4816, 4113, 2553, 449, -1738, -3454, +-4238, -4056, -3130, -1814, -463, 722, 1552, 1930, 1887, 1573, 1214, 916, + 725, 745, 1000, 1359, 1459, 880, -363, -1863, -3097, -3567, -3048, -1732, +-205, 884, 1210, 829, 39, -710, -1136, -1303, -1348, -1422, -1453, -1008, + 75, 1279, 1850, 1468, 328, -1137, -2388, -2712, -1381, 1695, 5460, 8019, +7900, 5220, 1350, -2288, -4879, -5987, -5475, -3689, -1440, 164, 482, -105, +-760, -1038, -1053, -877, -274, 949, 2563, 3950, 4582, 4345, 3411, 1934, + -29, -2225, -4075, -5041, -4910, -3825, -2300, -941, -155, -46, -403, -847, +-912, -249, 1102, 2805, 4351, 5250, 5285, 4423, 2725, 523, -1596, -3083, +-3657, -3400, -2626, -1645, -686, 147, 722, 941, 938, 916, 974, 1079, +1216, 1460, 1843, 2175, 2038, 1133, -361, -1901, -2992, -3368, -2964, -1987, +-887, -99, 168, -23, -383, -582, -522, -332, -233, -414, -893, -1388, +-1389, -589, 717, 1826, 2172, 1564, 187, -1461, -2620, -2319, -35, 3503, +6497, 7257, 5491, 2289, -1035, -3622, -4949, -4655, -2900, -689, 626, 367, +-918, -2108, -2630, -2627, -2224, -1213, 517, 2592, 4285, 5103, 5084, 4441, +3232, 1431, -713, -2578, -3658, -3888, -3558, -3072, -2676, -2490, -2559, -2674, +-2451, -1575, 20, 2067, 4118, 5681, 6321, 5866, 4492, 2653, 810, -756, +-1867, -2482, -2741, -2820, -2778, -2564, -2052, -1190, -191, 667, 1242, 1578, +1816, 1974, 2104, 2285, 2351, 2048, 1204, -104, -1461, -2351, -2561, -2270, +-1788, -1433, -1428, -1760, -2179, -2304, -1899, -1051, -19, 813, 1145, 1104, +1084, 1291, 1482, 1308, 645, -351, -1326, -2064, -2207, -1165, 1208, 4045, +5750, 5280, 3025, 335, -1716, -2863, -3080, -2260, -659, 774, 905, -505, +-2403, -3526, -3566, -3010, -2207, -989, 761, 2577, 3752, 4079, 3989, 3822, +3328, 2146, 447, -1149, -2170, -2636, -2805, -2867, -2869, -2859, -2957, -3054, +-2765, -1806, -193, 1715, 3526, 4975, 5766, 5694, 4737, 3140, 1375, -109, +-1101, -1622, -1821, -1908, -2019, -2164, -2199, -1917, -1308, -526, 241, 859, +1367, 1808, 2180, 2521, 2714, 2508, 1726, 459, -848, -1806, -2290, -2378, +-2259, -2096, -1990, -2025, -2151, -2074, -1644, -1003, -386, 50, 378, 782, +1378, 1951, 2100, 1633, 646, -531, -1585, -2141, -1663, 108, 2740, 5014, +5617, 4205, 1619, -861, -2511, -3184, -2772, -1395, 314, 1343, 899, -793, +-2643, -3666, -3771, -3362, -2472, -936, 1064, 2874, 3867, 4066, 3925, 3669, +3062, 1848, 354, -809, -1453, -1877, -2396, -2977, -3482, -3925, -4307, -4425, +-3825, -2254, -19, 2284, 4161, 5394, 5916, 5638, 4606, 3163, 1726, 598, +-179, -818, -1442, -1968, -2329, -2515, -2491, -2216, -1734, -1181, -678, -216, + 351, 1131, 2053, 2889, 3360, 3244, 2448, 1122, -277, -1291, -1779, -1878, +-1849, -1895, -2084, -2380, -2648, -2637, -2179, -1344, -421, 198, 344, 122, + -49, 338, 1309, 2401, 2947, 2519, 1233, -537, -2190, -2868, -1906, 665, +3771, 5721, 5405, 3178, 446, -1672, -2840, -2984, -2097, -530, 828, 894, +-635, -2804, -4331, -4712, -4305, -3370, -1628, 945, 3629, 5427, 5884, 5363, +4489, 3443, 2023, 408, -836, -1458, -1761, -2197, -2935, -3758, -4421, -4813, +-4761, -4021, -2373, -32, 2327, 4128, 5090, 5229, 4678, 3692, 2739, 2103, +1714, 1291, 532, -581, -1779, -2759, -3296, -3266, -2669, -1750, -979, -550, +-264, 106, 680, 1426, 2203, 2781, 2936, 2546, 1615, 420, -609, -1259, +-1644, -1979, -2358, -2767, -3143, -3351, -3281, -2923, -2263, -1264, 83, 1694, +3201, 3936, 3438, 1953, 191, -1191, -1675, -881, 1229, 4046, 6211, 6272, +3848, 143, -2984, -4502, -4468, -3319, -1506, 367, 1419, 943, -876, -2872, +-3745, -3226, -2059, -832, 487, 1919, 3083, 3490, 3054, 2361, 2052, 2058, +1818, 1043, 70, -722, -1409, -2127, -2814, -3325, -3557, -3567, -3447, -3088, +-2247, -929, 513, 1791, 2860, 3731, 4281, 4315, 3781, 2826, 1730, 798, + 154, -251, -425, -452, -587, -1004, -1616, -2205, -2562, -2575, -2232, -1527, +-452, 895, 2171, 2952, 3008, 2334, 1160, -91, -922, -1046, -612, -86, + 50, -449, -1437, -2545, -3513, -4039, -3822, -2806, -1135, 808, 2419, 3054, +2410, 836, -863, -1851, -1578, 102, 2855, 5809, 7672, 7272, 4470, 563, +-2594, -3965, -3759, -2732, -1480, -405, 65, -468, -1901, -3242, -3430, -2486, +-1272, -411, 318, 1370, 2535, 3172, 2975, 2367, 2039, 2024, 1775, 1060, + 250, -279, -633, -1135, -1882, -2563, -2922, -3093, -3318, -3566, -3439, -2649, +-1347, 174, 1764, 3353, 4631, 5123, 4616, 3318, 1834, 788, 391, 523, + 930, 1262, 1140, 335, -1015, -2447, -3478, -3801, -3431, -2566, -1336, 45, +1296, 2149, 2369, 1990, 1242, 409, -198, -382, -142, 331, 636, 371, +-583, -1991, -3428, -4478, -4772, -4017, -2197, 187, 2116, 2626, 1607, -120, +-1474, -1719, -591, 1793, 4902, 7620, 8456, 6611, 2878, -807, -2857, -3125, +-2370, -1348, -502, -166, -820, -2500, -4251, -4749, -3518, -1444, 210, 1124, +1753, 2361, 2687, 2413, 1825, 1600, 1916, 2187, 1780, 800, -137, -748, +-1292, -2001, -2626, -2796, -2564, -2304, -2327, -2511, -2404, -1834, -1002, -45, +1140, 2588, 3855, 4311, 3753, 2521, 1267, 408, 9, 95, 680, 1553, +2108, 1790, 630, -877, -2197, -3032, -3307, -2975, -1983, -587, 617, 1120, + 872, 234, -402, -816, -864, -487, 180, 794, 899, 325, -680, -1791, +-2683, -3046, -2622, -1281, 443, 1486, 1195, -201, -1825, -2721, -2310, -527, +2330, 5567, 7921, 8000, 5518, 1802, -1229, -2449, -2046, -854, 423, 1314, +1314, -80, -2665, -5110, -5942, -4829, -2611, -355, 1450, 2759, 3365, 2950, +1654, 332, -22, 700, 1685, 2109, 1775, 971, -82, -1303, -2509, -3263, +-3161, -2332, -1423, -987, -937, -942, -890, -795, -605, -79, 906, 2046, +2767, 2701, 2071, 1350, 826, 578, 634, 1034, 1672, 2176, 2090, 1351, + 328, -574, -1221, -1696, -1916, -1694, -1071, -442, -246, -550, -1119, -1599, +-1774, -1626, -1169, -512, 103, 410, 267, -181, -632, -925, -967, -645, + 40, 815, 1149, 633, -636, -2033, -2845, -2693, -1494, 583, 3066, 5110, +5736, 4591, 2407, 477, -380, -222, 426, 1097, 1531, 1445, 488, -1301, +-3201, -4259, -4111, -3225, -2161, -1018, 260, 1448, 2024, 1755, 1041, 609, + 766, 1144, 1295, 1148, 869, 438, -297, -1270, -2069, -2312, -2067, -1693, +-1496, -1408, -1166, -727, -260, 134, 604, 1233, 1797, 1940, 1495, 722, + 108, -50, 177, 600, 1127, 1665, 1992, 1818, 1135, 316, -234, -356, +-212, -42, 127, 370, 549, 313, -431, -1385, -2157, -2501, -2451, -2164, +-1759, -1296, -918, -851, -1100, -1366, -1385, -1046, -307, 715, 1741, 2329, +2095, 1049, -411, -1693, -2261, -1894, -673, 1158, 3071, 4251, 4136, 2908, +1309, 84, -398, -188, 482, 1376, 2115, 2158, 1188, -490, -2071, -2969, +-3180, -2912, -2301, -1398, -317, 625, 1043, 905, 622, 522, 542, 461, + 307, 292, 399, 388, 61, -520, -1053, -1319, -1391, -1451, -1499, -1331, +-862, -284, 225, 640, 1040, 1398, 1505, 1246, 741, 296, 157, 241, + 349, 462, 668, 940, 1130, 1074, 756, 348, -4, -301, -528, -506, + -90, 582, 1134, 1223, 737, -133, -1044, -1735, -2105, -2142, -1879, -1491, +-1230, -1245, -1452, -1596, -1480, -995, -217, 596, 1253, 1579, 1431, 864, + 110, -516, -828, -788, -400, 265, 1004, 1547, 1668, 1313, 716, 216, + 18, 186, 660, 1287, 1809, 1942, 1552, 734, -180, -878, -1258, -1336, +-1203, -953, -693, -546, -528, -556, -474, -205, 127, 338, 326, 91, +-289, -689, -959, -981, -725, -293, 114, 290, 225, 36, -168, -261, +-175, 114, 565, 1013, 1283, 1261, 973, 541, 65, -334, -574, -540, +-163, 359, 793, 980, 822, 362, -271, -871, -1220, -1111, -476, 452, +1337, 1840, 1741, 1150, 331, -476, -1064, -1325, -1257, -1013, -815, -761, +-858, -994, -940, -616, -152, 242, 433, 435, 302, 112, -42, -135, +-143, -85, -48, -90, -245, -428, -491, -436, -303, -115, 116, 429, + 803, 1107, 1211, 1152, 1038, 909, 782, 655, 554, 486, 393, 186, +-191, -640, -974, -1068, -918, -628, -268, 52, 159, 20, -304, -611, +-705, -589, -322, 11, 324, 563, 638, 527, 291, 28, -140, -158, + -54, 125, 339, 517, 570, 439, 196, -7, -115, -97, 61, 253, + 376, 380, 214, -129, -543, -883, -1066, -996, -656, -176, 296, 664, + 875, 876, 726, 499, 205, -77, -304, -440, -456, -396, -277, -148, + -44, 40, 61, 19, -70, -194, -288, -312, -279, -229, -170, -123, +-130, -224, -398, -571, -653, -600, -432, -207, 4, 170, 274, 303, + 303, 298, 327, 415, 540, 698, 837, 881, 761, 461, 74, -316, +-597, -672, -563, -334, -69, 107, 108, -35, -259, -449, -533, -503, +-347, -115, 131, 319, 433, 465, 365, 205, 42, -96, -154, -106, + 12, 118, 179, 160, 55, -60, -144, -171, -112, 27, 203, 315, + 270, 97, -155, -413, -552, -568, -455, -233, 35, 342, 595, 734, + 752, 633, 391, 76, -190, -324, -289, -95, 160, 384, 499, 463, + 295, 40, -234, -444, -534, -476, -258, 7, 193, 257, 149, -89, +-353, -568, -663, -601, -378, -56, 212, 316, 250, 57, -145, -251, +-227, -54, 231, 562, 821, 830, 563, 165, -231, -523, -665, -648, +-428, -109, 117, 158, 26, -181, -328, -358, -294, -135, 105, 321, + 426, 401, 269, 113, 49, 69, 131, 231, 339, 422, 393, 243, + 38, -131, -190, -168, -102, -21, 63, 123, 104, -6, -152, -271, +-358, -411, -436, -425, -333, -174, -14, 97, 180, 239, 260, 234, + 145, 53, 8, -4, 6, 33, 99, 221, 363, 416, 336, 140, +-129, -371, -516, -522, -397, -194, 34, 203, 236, 125, -54, -208, +-307, -316, -229, -84, 82, 207, 247, 174, 27, -100, -182, -172, + -31, 178, 393, 514, 453, 232, -65, -317, -443, -410, -239, -32, + 79, 22, -138, -312, -433, -441, -337, -153, 28, 156, 193, 78, +-113, -249, -259, -156, 3, 178, 323, 412, 419, 333, 214, 120, + 77, 78, 111, 153, 160, 141, 113, 69, 1, -85, -163, -224, +-253, -219, -161, -118, -65, 26, 125, 193, 221, 209, 186, 154, + 109, 68, 57, 112, 207, 277, 265, 186, 79, -32, -124, -204, +-244, -201, -85, 40, 97, 95, 69, 32, 20, 16, 30, 69, + 151, 275, 319, 299, 260, 178, 89, -11, -125, -196, -182, -131, +-104, -72, -55, -103, -180, -265, -329, -305, -192, -58, 50, 121, + 144, 99, -40, -204, -268, -242, -167, -100, -102, -132, -173, -192, +-164, -113, -12, 122, 234, 281, 296, 321, 336, 308, 207, 82, + -27, -89, -104, -99, -40, 14, -1, -109, -290, -417, -454, -381, +-190, -10, 166, 286, 289, 246, 159, 81, 62, 72, 71, 59, + 86, 146, 185, 145, 38, -103, -247, -301, -270, -207, -100, 13, + 85, 73, -2, -77, -135, -127, -36, 64, 124, 170, 230, 289, + 292, 214, 106, 14, -42, -66, -71, -64, -50, -32, -52, -138, +-183, -121, -25, 62, 113, 80, 10, -56, -117, -122, -74, 7, + 42, -24, -102, -189, -275, -298, -276, -179, -49, 41, 89, 60, + 59, 109, 102, 82, 120, 230, 336, 393, 365, 210, 84, 38, + 10, -10, -9, 42, 50, -13, -127, -288, -382, -393, -346, -251, +-124, 8, 86, 129, 129, 89, 63, 64, 97, 174, 289, 380, + 386, 276, 115, 0, -95, -175, -232, -274, -248, -139, -30, -10, + -30, -45, -93, -122, -96, -24, 85, 228, 345, 329, 223, 128, + 67, 47, 66, 59, -26, -149, -238, -249, -228, -196, -186, -164, + -64, 58, 188, 238, 202, 184, 124, 56, 20, -3, 42, 84, + 31, -148, -404, -550, -533, -414, -205, -32, 9, -6, -31, -71, + -56, 30, 140, 289, 411, 412, 307, 180, 106, 25, -79, -166, +-217, -197, -134, -77, -122, -242, -326, -368, -330, -182, 63, 291, + 372, 318, 163, -6, -68, 6, 138, 264, 352, 360, 265, 93, + -63, -173, -233, -229, -194, -148, -100, -24, 22, -6, -31, -61, + -88, -33, 110, 319, 515, 545, 365, 99, -97, -178, -192, -120, + 3, 141, 245, 136, -155, -425, -529, -466, -346, -227, -147, -7, + 180, 220, 96, -92, -153, -47, 118, 285, 376, 379, 299, 119, +-128, -362, -450, -356, -205, -129, -122, -174, -252, -256, -192, -63, + 104, 220, 259, 260, 301, 329, 285, 196, 71, -14, -56, -121, +-203, -286, -308, -266, -270, -295, -250, -120, 50, 169, 210, 159, + 92, 66, 41, 78, 164, 207, 227, 233, 200, 107, 15, -47, + -80, -37, 29, 89, 129, 157, 221, 270, 273, 271, 293, 324, + 325, 279, 179, 68, 27, 50, 65, 59, 29, -21, -76, -124, +-171, -199, -164, -70, 37, 110, 164, 213, 211, 128, 31, -54, +-118, -67, 65, 135, 119, 43, -135, -361, -512, -577, -558, -458, +-345, -289, -268, -246, -231, -204, -153, -114, -104, -71, 0, 65, + 98, 81, 31, -38, -104, -147, -171, -178, -177, -189, -243, -314, +-336, -314, -246, -142, -84, -109, -131, -138, -156, -106, -13, 78, + 200, 279, 317, 365, 404, 456, 506, 522, 543, 578, 579, 538, + 471, 403, 325, 263, 239, 215, 228, 251, 227, 175, 133, 127, + 133, 128, 107, 59, 3, -47, -97, -153, -200, -236, -286, -370, +-429, -401, -342, -286, -202, -137, -126, -114, -93, -79, -39, 31, + 88, 72, 10, -51, -123, -176, -185, -202, -235, -241, -239, -265, +-322, -346, -309, -267, -228, -203, -218, -282, -400, -531, -594, -479, +-191, 120, 273, 202, -25, -301, -483, -465, -189, 330, 906, 1278, +1335, 1186, 1019, 917, 851, 768, 690, 682, 705, 671, 502, 216, + -77, -361, -582, -693, -696, -497, -183, 25, 81, 14, -54, 24, + 212, 364, 444, 467, 374, 203, 46, -77, -143, -185, -297, -498, +-712, -845, -872, -831, -708, -497, -283, -146, -127, -183, -258, -334, +-368, -308, -127, 130, 381, 508, 481, 396, 273, 135, 79, 115, + 196, 259, 239, 138, -41, -316, -662, -985, -1137, -1022, -708, -440, +-406, -560, -735, -808, -729, -401, 226, 1062, 1838, 2191, 2031, 1542, +1066, 866, 832, 793, 736, 732, 696, 424, -105, -737, -1226, -1397, +-1309, -1086, -753, -355, -20, 97, -47, -192, -81, 262, 719, 1083, +1188, 1016, 619, 186, -140, -311, -336, -369, -459, -534, -620, -777, +-1025, -1216, -1173, -925, -560, -185, 78, 218, 210, 49, -135, -176, + -6, 341, 734, 988, 1035, 872, 551, 219, -4, -89, -93, -77, + -97, -189, -450, -975, -1486, -1521, -988, -314, -58, -392, -947, -1208, +-1052, -666, -94, 871, 2121, 3012, 3007, 2205, 1337, 1045, 1195, 1257, +1091, 984, 1147, 1242, 723, -340, -1374, -1888, -1882, -1707, -1448, -1014, +-492, -151, -202, -412, -367, 36, 570, 939, 1053, 968, 725, 378, + 94, 10, -7, -176, -551, -937, -1078, -1037, -1086, -1248, -1287, -1012, +-542, -186, -48, -19, -6, 41, 128, 259, 503, 814, 982, 956, + 908, 890, 785, 524, 222, -3, -167, -264, -288, -348, -567, -1086, +-1913, -2393, -1703, -213, 551, -173, -1442, -2055, -1880, -1419, -881, 121, +2031, 4173, 4709, 2987, 911, 568, 1656, 2404, 2081, 1504, 1552, 1973, +1571, -255, -2344, -3031, -2411, -1913, -1918, -1639, -914, -476, -705, -1191, +-1244, -358, 1119, 2070, 2053, 1604, 1053, 355, -140, 26, 500, 496, +-147, -891, -1261, -1302, -1403, -1729, -1943, -1540, -606, 26, -25, -282, +-413, -448, -319, 71, 595, 999, 1133, 1016, 871, 931, 1047, 838, + 395, 130, 51, -103, -337, -374, -220, -218, -512, -1032, -1489, -1489, +-1057, -659, -476, -234, 104, 331, 490, 738, 1027, 1244, 1503, 1860, +2159, 2279, 2082, 1441, 620, 188, 328, 592, 528, 81, -613, -1292, +-1630, -1530, -1258, -1063, -889, -656, -399, -98, 157, 142, -25, 34, + 433, 928, 1181, 1038, 413, -504, -1234, -1541, -1413, -946, -466, -331, +-573, -898, -1092, -1148, -1088, -876, -487, 41, 606, 971, 914, 542, + 177, -3, 49, 301, 567, 622, 463, 324, 219, -52, -457, -694, +-578, -230, 133, 186, -225, -666, -660, -315, 7, 348, 795, 1023, + 870, 647, 686, 1040, 1538, 1782, 1383, 650, 398, 708, 820, 336, +-371, -824, -825, -463, -225, -549, -1049, -1030, -532, -91, 120, 281, + 313, 178, 165, 311, 443, 548, 609, 438, 22, -278, -383, -619, +-965, -1139, -1154, -1159, -1152, -1105, -1085, -1057, -901, -673, -434, -106, + 257, 336, 62, -176, -128, 184, 586, 779, 640, 333, 103, -13, +-164, -394, -607, -639, -340, 134, 329, 121, -130, -188, -207, -383, +-515, -189, 690, 1696, 2136, 1791, 1244, 1140, 1349, 1356, 1151, 1085, +1180, 1034, 437, -296, -765, -835, -753, -953, -1392, -1534, -1120, -572, +-424, -534, -454, -33, 599, 1142, 1297, 1037, 645, 346, 140, 79, + 213, 303, 25, -530, -990, -1258, -1387, -1370, -1280, -1190, -1030, -722, +-447, -384, -451, -495, -363, -15, 396, 651, 653, 484, 275, 134, + 122, 253, 479, 702, 741, 490, -10, -679, -1350, -1688, -1312, -317, + 660, 1050, 729, -81, -990, -1498, -1338, -609, 525, 1785, 2596, 2525, +1853, 1215, 882, 893, 1243, 1670, 1827, 1623, 1171, 484, -375, -1029, +-1261, -1200, -988, -814, -899, -1227, -1467, -1359, -1003, -539, 38, 709, +1185, 1147, 597, -106, -453, -216, 355, 679, 443, -141, -797, -1332, +-1620, -1615, -1410, -1147, -828, -502, -319, -325, -447, -511, -356, -6, + 349, 491, 455, 478, 634, 833, 945, 905, 756, 567, 356, 43, +-422, -970, -1415, -1370, -570, 451, 579, -439, -1509, -1675, -1185, -809, +-678, -103, 1405, 3124, 3427, 1812, 91, 312, 2164, 3455, 2884, 1313, + 333, 427, 699, 206, -782, -1160, -651, -247, -714, -1619, -2045, -1692, +-929, -214, 196, 366, 494, 610, 509, 69, -414, -450, 192, 1116, +1470, 686, -842, -1951, -2019, -1482, -1040, -898, -753, -445, -197, -318, +-764, -1027, -729, -46, 528, 697, 550, 333, 205, 303, 637, 871, + 743, 446, 319, 349, 165, -409, -1098, -1367, -766, 440, 1120, 455, +-983, -1887, -1680, -892, -304, 2, 659, 1906, 2819, 2296, 650, -400, + 378, 2235, 3307, 2607, 920, -225, -386, -371, -751, -1100, -823, -175, + 87, -382, -1178, -1504, -1045, -213, 418, 695, 845, 937, 788, 294, +-358, -741, -472, 406, 1177, 1020, -122, -1482, -2187, -2029, -1415, -876, +-657, -548, -366, -298, -563, -1029, -1196, -710, 209, 972, 1084, 604, + 80, -59, 168, 545, 891, 1010, 810, 487, 265, 29, -407, -803, +-893, -796, -492, 251, 1043, 816, -543, -1659, -1641, -1117, -870, -587, + 375, 1921, 3092, 2592, 548, -874, 126, 2389, 3129, 1789, 291, 200, +1051, 1125, -324, -2011, -2062, -555, 370, -524, -1940, -2093, -901, 354, + 621, 28, -343, 379, 1491, 1529, 359, -735, -767, 125, 1056, 923, +-479, -1977, -2270, -1540, -1017, -1171, -1441, -1140, -278, 421, 282, -468, +-752, -40, 962, 1248, 707, -3, -237, 134, 558, 581, 295, 16, + -75, -58, -212, -820, -1526, -1323, 122, 1481, 1269, -97, -1047, -922, +-294, 210, 528, 1038, 1835, 2121, 1111, -448, -855, 232, 1477, 1737, +1188, 632, 356, 136, -362, -1015, -1025, -57, 1037, 1196, 352, -680, +-1100, -705, 97, 650, 695, 667, 904, 955, 289, -719, -1210, -788, + 257, 1026, 700, -544, -1729, -2153, -1945, -1589, -1296, -953, -417, 147, + 273, -206, -715, -608, 44, 710, 1057, 987, 591, 220, 98, 100, + 49, -3, -43, -197, -533, -1266, -2211, -1997, 118, 2108, 1598, -535, +-1630, -1147, -586, -579, -379, 888, 3135, 4536, 3184, 221, -900, 755, +2391, 1897, 345, -287, 326, 887, -85, -2396, -3671, -2286, 3, 481, +-791, -1631, -959, 462, 1468, 1413, 799, 1039, 2467, 3328, 2086, -322, +-1722, -1165, 374, 1065, 30, -1731, -2607, -2330, -2085, -2672, -3260, -2605, +-769, 830, 976, 37, -669, -275, 845, 1563, 1417, 893, 702, 954, +1081, 683, -42, -534, -469, -121, -103, -712, -1488, -1731, -1322, -730, +-291, 42, 322, 529, 712, 812, 605, 136, -165, 162, 1171, 2272, +2644, 1978, 931, 505, 782, 808, -67, -1114, -1240, -591, -279, -800, +-1453, -1465, -946, -531, -530, -589, -117, 936, 1816, 1797, 1236, 1105, +1553, 1789, 1235, 224, -516, -601, -213, 12, -333, -1026, -1624, -1914, +-1980, -1910, -1686, -1266, -633, 11, 385, 379, 213, 256, 608, 990, +1072, 876, 669, 562, 350, -108, -551, -752, -840, -1098, -1542, -1585, +-752, 240, 252, -647, -1278, -1063, -525, -107, 259, 887, 2026, 3095, +2934, 1472, 275, 676, 1916, 2223, 1158, -42, -94, 663, 638, -887, +-2638, -2834, -1565, -574, -762, -1224, -753, 579, 1629, 1536, 660, 305, +1234, 2571, 2756, 1490, 81, -259, 211, 367, -320, -1352, -1995, -2006, +-1728, -1693, -1974, -2051, -1545, -822, -429, -372, -348, -131, 374, 925, +1079, 733, 308, 295, 711, 1124, 1008, 318, -367, -617, -685, -1039, +-1663, -2072, -1769, -731, 312, 574, 203, -5, 235, 387, 116, -161, + 123, 1160, 2394, 2770, 1871, 610, 217, 629, 867, 524, 89, 56, + 163, -174, -983, -1563, -1292, -568, -305, -554, -543, -2, 528, 741, + 910, 1141, 1277, 1334, 1326, 1083, 548, -89, -599, -851, -785, -520, +-402, -676, -1204, -1634, -1806, -1749, -1460, -1003, -516, -133, 81, 124, + 0, -59, 199, 589, 755, 707, 710, 709, 527, 325, 285, 168, +-274, -808, -1219, -1463, -1203, -265, 627, 587, -253, -948, -893, -383, + 0, 168, 808, 2259, 3332, 2667, 717, -457, 318, 1766, 1955, 848, + 183, 826, 1429, 356, -2006, -3414, -2554, -760, -88, -805, -1380, -674, + 576, 953, 247, -197, 792, 2536, 3308, 2296, 451, -661, -516, 76, + 29, -684, -1302, -1361, -1121, -1233, -1894, -2553, -2402, -1292, -51, 397, + 2, -431, -246, 327, 610, 397, 182, 455, 1040, 1301, 890, 92, +-482, -544, -327, -256, -532, -894, -1053, -827, -175, 489, 683, 326, + -96, -116, 89, 98, -132, 9, 888, 1737, 1560, 462, -349, 33, +1150, 1786, 1407, 645, 424, 737, 667, -246, -1242, -1296, -595, -270, +-796, -1473, -1440, -725, -58, 37, -203, -66, 750, 1585, 1542, 720, + 68, 99, 431, 554, 361, -42, -518, -947, -1330, -1644, -1707, -1370, +-800, -426, -403, -551, -657, -560, -228, 197, 467, 523, 525, 525, + 423, 207, 1, -227, -579, -756, -312, 431, 588, -10, -603, -522, + -72, 39, -151, 61, 1117, 2337, 2426, 1117, -248, -150, 1076, 1686, + 926, -100, 1, 1006, 1435, 445, -1059, -1437, -478, 338, -160, -1197, +-1081, 279, 1189, 480, -910, -1156, 99, 1420, 1417, 348, -388, -84, + 526, 301, -733, -1398, -1036, -317, -284, -1013, -1626, -1500, -905, -492, +-491, -582, -439, -84, 113, -105, -445, -482, -105, 414, 682, 660, + 557, 557, 604, 465, 226, 185, 357, 490, 493, 484, 473, 368, + 182, 113, 232, 314, 152, -159, -296, -158, -9, -53, -181, -210, + -88, 69, 47, -130, -126, 236, 618, 593, 282, 172, 408, 626, + 475, 1, -427, -553, -479, -403, -434, -503, -385, -82, 56, -221, +-579, -477, 72, 534, 579, 352, 115, 67, 210, 227, -97, -496, +-576, -347, -104, -25, -102, -248, -335, -345, -392, -492, -487, -264, + 36, 173, 99, -68, -222, -278, -187, -85, -130, -204, -78, 138, + 136, -119, -466, -682, -570, -150, 282, 361, 136, -5, 19, 2, + -87, -10, 339, 648, 649, 484, 424, 562, 809, 1007, 1077, 1055, +1034, 1065, 992, 706, 438, 423, 527, 473, 300, 193, 147, 101, + 28, -110, -344, -561, -569, -401, -339, -534, -800, -885, -788, -719, +-778, -799, -689, -572, -580, -693, -755, -728, -648, -562, -555, -588, +-576, -520, -483, -462, -385, -243, -147, -195, -292, -266, -42, 218, + 336, 411, 507, 573, 598, 634, 748, 852, 866, 816, 692, 534, + 435, 508, 695, 790, 784, 750, 689, 605, 634, 816, 942, 967, + 971, 944, 844, 667, 425, 151, -46, -166, -302, -431, -508, -589, +-726, -933, -1137, -1174, -1031, -805, -599, -440, -280, -237, -446, -743, +-883, -846, -785, -746, -708, -755, -853, -839, -731, -672, -708, -753, +-705, -557, -344, -171, -110, -77, 7, 89, 118, 210, 423, 618, + 681, 627, 548, 476, 466, 565, 659, 664, 656, 789, 991, 1025, + 856, 698, 767, 942, 1018, 965, 909, 999, 1110, 1022, 697, 349, + 240, 323, 364, 174, -136, -271, -235, -243, -415, -622, -669, -633, +-704, -877, -1025, -1006, -807, -658, -738, -948, -1039, -925, -778, -731, +-750, -717, -593, -472, -462, -544, -589, -529, -381, -274, -335, -466, +-482, -354, -228, -221, -221, -134, 16, 158, 193, 132, 82, 186, + 406, 573, 728, 903, 1036, 1091, 1042, 957, 934, 1053, 1224, 1237, +1081, 896, 792, 699, 600, 627, 746, 763, 606, 443, 394, 398, + 368, 271, 170, 124, 89, -5, -140, -297, -467, -642, -787, -844, +-849, -852, -898, -1026, -1182, -1246, -1153, -985, -855, -783, -706, -634, +-612, -603, -573, -491, -370, -262, -188, -174, -225, -312, -323, -210, +-101, -86, -119, -131, -91, -22, 61, 135, 160, 181, 239, 339, + 430, 442, 445, 554, 742, 855, 855, 843, 881, 964, 1050, 1067, + 984, 879, 902, 1043, 1088, 965, 799, 660, 557, 494, 462, 416, + 328, 249, 161, 19, -143, -254, -272, -271, -325, -448, -639, -795, +-842, -815, -785, -841, -969, -1091, -1142, -1093, -1042, -1045, -1015, -914, +-823, -798, -746, -586, -445, -416, -412, -371, -288, -204, -185, -236, +-303, -355, -394, -399, -299, -109, 40, 74, 40, 25, 33, 127, + 333, 519, 696, 892, 1036, 1125, 1181, 1259, 1329, 1320, 1285, 1273, +1297, 1316, 1273, 1176, 1037, 870, 683, 506, 382, 304, 260, 240, + 196, 90, -49, -153, -179, -200, -267, -371, -518, -697, -851, -901, +-893, -946, -1037, -1097, -1117, -1149, -1193, -1179, -1128, -1097, -1060, -986, +-885, -738, -549, -409, -376, -435, -469, -408, -287, -140, -41, -46, +-115, -142, -83, 16, 118, 207, 253, 260, 301, 422, 574, 718, + 869, 1011, 1103, 1147, 1209, 1283, 1287, 1235, 1230, 1273, 1269, 1235, +1195, 1127, 1025, 906, 827, 739, 563, 329, 122, -3, -111, -225, +-272, -257, -293, -411, -534, -635, -716, -767, -795, -839, -922, -959, +-915, -871, -907, -1001, -1057, -1038, -957, -860, -801, -778, -790, -808, +-804, -768, -680, -549, -415, -398, -462, -441, -353, -247, -141, -52, + 20, 48, 100, 208, 291, 290, 250, 240, 283, 405, 577, 730, + 806, 834, 878, 955, 1046, 1134, 1258, 1350, 1331, 1285, 1255, 1236, +1250, 1242, 1136, 917, 662, 480, 357, 215, 50, -90, -185, -292, +-460, -637, -754, -794, -801, -780, -738, -741, -746, -724, -747, -802, +-859, -866, -827, -825, -828, -824, -853, -911, -921, -829, -752, -664, +-545, -500, -491, -482, -476, -490, -463, -345, -224, -154, -121, -85, + -15, 112, 273, 384, 421, 444, 514, 616, 706, 770, 817, 851, + 897, 973, 1036, 1082, 1137, 1210, 1282, 1293, 1226, 1159, 1159, 1170, +1117, 969, 767, 598, 473, 351, 186, 13, -134, -229, -298, -425, +-598, -791, -918, -1009, -1144, -1208, -1178, -1079, -962, -943, -980, -988, +-942, -857, -761, -661, -606, -606, -607, -598, -598, -584, -530, -451, +-404, -432, -490, -473, -341, -174, -31, 31, 1, 22, 127, 216, + 283, 378, 483, 568, 659, 776, 860, 877, 901, 939, 962, 1004, +1061, 1122, 1163, 1139, 1070, 972, 878, 902, 982, 962, 881, 769, + 602, 433, 292, 192, 102, -22, -143, -282, -477, -663, -795, -876, +-925, -962, -999, -1043, -1087, -1117, -1124, -1081, -1006, -976, -956, -884, +-809, -770, -724, -644, -595, -592, -553, -433, -311, -294, -357, -417, +-436, -414, -358, -267, -129, 33, 134, 132, 110, 156, 282, 434, + 580, 712, 790, 864, 990, 1109, 1145, 1103, 1075, 1116, 1163, 1136, +1078, 1046, 1026, 992, 907, 798, 732, 690, 605, 481, 370, 274, + 211, 205, 174, 74, -61, -221, -405, -597, -756, -834, -857, -881, +-914, -978, -1078, -1170, -1257, -1331, -1367, -1350, -1272, -1183, -1114, -1026, +-905, -771, -676, -626, -546, -408, -269, -160, -81, -31, 17, 83, + 152, 208, 259, 324, 419, 535, 642, 717, 768, 853, 967, 1032, +1049, 1088, 1187, 1315, 1394, 1394, 1326, 1250, 1212, 1157, 1043, 873, + 706, 601, 524, 419, 280, 158, 72, -39, -188, -331, -409, -430, +-436, -433, -494, -606, -682, -744, -813, -890, -951, -961, -965, -999, +-1054, -1088, -1086, -1082, -1092, -1113, -1090, -1003, -913, -845, -769, -657, +-529, -390, -270, -193, -129, -51, 59, 157, 219, 296, 393, 495, + 600, 682, 724, 736, 761, 824, 917, 1028, 1124, 1220, 1308, 1325, +1275, 1210, 1208, 1250, 1240, 1153, 996, 824, 697, 606, 507, 360, + 198, 57, -79, -261, -472, -600, -636, -659, -710, -801, -885, -922, +-949, -1000, -1073, -1142, -1149, -1103, -1052, -1019, -1008, -974, -963, -1026, +-1067, -1021, -920, -831, -791, -755, -676, -573, -465, -354, -254, -142, + -18, 104, 239, 398, 558, 692, 799, 858, 897, 946, 1041, 1169, +1230, 1232, 1222, 1240, 1268, 1217, 1108, 1028, 1010, 1022, 985, 904, + 803, 699, 653, 599, 473, 331, 237, 217, 167, 6, -175, -305, +-404, -525, -697, -867, -970, -1015, -1045, -1089, -1124, -1137, -1136, -1135, +-1151, -1171, -1165, -1093, -975, -857, -771, -752, -752, -734, -725, -728, +-691, -589, -457, -335, -243, -135, -10, 114, 226, 284, 326, 407, + 547, 708, 877, 1070, 1235, 1329, 1351, 1364, 1354, 1278, 1230, 1214, +1195, 1198, 1207, 1214, 1179, 1074, 929, 754, 559, 396, 298, 267, + 251, 181, 69, -77, -220, -340, -468, -568, -669, -777, -843, -905, +-969, -999, -1000, -1010, -1046, -1101, -1151, -1182, -1194, -1186, -1164, -1115, +-1057, -993, -952, -954, -931, -861, -747, -619, -473, -293, -129, -14, + 75, 191, 307, 434, 598, 727, 833, 945, 1042, 1076, 1040, 1023, +1075, 1154, 1205, 1236, 1249, 1246, 1212, 1122, 1026, 940, 856, 795, + 723, 611, 504, 429, 361, 269, 128, -30, -159, -296, -426, -507, +-568, -634, -705, -744, -759, -800, -870, -937, -972, -995, -990, -960, +-928, -869, -836, -865, -927, -973, -973, -974, -968, -931, -866, -742, +-584, -433, -291, -172, -71, 15, 104, 224, 389, 575, 730, 867, + 989, 1077, 1120, 1125, 1126, 1111, 1076, 1075, 1123, 1185, 1207, 1169, +1098, 1011, 899, 765, 649, 568, 490, 414, 354, 287, 198, 103, + 25, -95, -285, -475, -604, -647, -665, -682, -684, -710, -742, -794, +-867, -931, -1003, -1032, -1006, -972, -942, -913, -866, -794, -730, -739, +-789, -778, -671, -499, -346, -239, -135, -55, 29, 145, 223, 301, + 414, 534, 633, 695, 778, 867, 946, 1002, 1016, 1036, 1050, 1056, +1097, 1126, 1086, 1004, 914, 837, 747, 647, 566, 471, 375, 285, + 180, 69, -47, -147, -242, -339, -427, -496, -537, -579, -634, -684, +-744, -820, -881, -906, -878, -846, -831, -803, -762, -721, -712, -710, +-706, -704, -662, -596, -531, -458, -378, -296, -203, -84, 13, 50, + 78, 138, 246, 375, 487, 592, 686, 781, 867, 878, 831, 790, + 777, 773, 756, 720, 704, 742, 782, 771, 698, 620, 568, 516, + 464, 376, 276, 213, 145, 75, -15, -120, -208, -311, -406, -485, +-577, -659, -705, -736, -754, -755, -758, -744, -737, -749, -777, -827, +-826, -762, -706, -668, -624, -587, -549, -494, -430, -342, -243, -150, + -62, 7, 80, 187, 300, 390, 482, 569, 650, 726, 777, 835, + 877, 872, 858, 829, 791, 787, 813, 815, 792, 753, 693, 641, + 584, 508, 422, 336, 260, 166, 64, -27, -134, -260, -388, -505, +-586, -629, -639, -637, -658, -697, -737, -757, -759, -770, -782, -798, +-802, -785, -751, -695, -657, -624, -572, -516, -464, -407, -329, -242, +-156, -55, 59, 171, 275, 365, 433, 482, 532, 581, 622, 685, + 770, 845, 895, 912, 913, 885, 846, 822, 776, 759, 762, 708, + 630, 545, 451, 372, 289, 204, 110, 38, 3, -72, -153, -218, +-304, -392, -473, -538, -602, -658, -694, -719, -744, -769, -815, -890, +-923, -910, -892, -859, -788, -698, -643, -630, -597, -543, -497, -429, +-358, -292, -197, -89, 3, 68, 117, 154, 211, 286, 346, 422, + 505, 579, 660, 748, 819, 860, 899, 906, 863, 819, 775, 761, + 791, 828, 838, 797, 720, 605, 474, 366, 276, 201, 128, 34, + -72, -163, -242, -310, -376, -468, -558, -626, -690, -745, -769, -767, +-770, -778, -785, -805, -809, -806, -814, -832, -870, -861, -781, -674, +-565, -485, -425, -359, -285, -211, -120, -15, 84, 189, 264, 336, + 451, 552, 657, 764, 808, 805, 800, 830, 887, 939, 982, 1014, +1038, 1043, 1007, 948, 871, 764, 648, 559, 494, 424, 372, 318, + 214, 87, -35, -147, -255, -357, -440, -507, -566, -630, -691, -722, +-752, -795, -830, -862, -878, -864, -818, -774, -770, -778, -773, -760, +-725, -686, -651, -580, -485, -376, -275, -189, -99, -21, 47, 103, + 151, 221, 312, 399, 470, 513, 542, 584, 640, 703, 738, 761, + 818, 873, 917, 933, 913, 902, 867, 816, 766, 698, 637, 577, + 522, 461, 400, 357, 304, 219, 91, -44, -163, -268, -362, -455, +-548, -622, -678, -722, -759, -807, -852, -880, -892, -885, -864, -820, +-777, -765, -765, -767, -757, -713, -670, -623, -544, -458, -375, -291, +-207, -114, -5, 84, 110, 132, 197, 268, 358, 466, 560, 631, + 692, 746, 771, 788, 802, 801, 800, 812, 830, 831, 827, 820, + 786, 719, 633, 548, 487, 453, 417, 355, 264, 166, 93, 28, + -52, -125, -203, -295, -379, -450, -508, -546, -583, -633, -694, -756, +-798, -821, -813, -799, -788, -756, -734, -706, -650, -599, -552, -502, +-444, -370, -282, -207, -160, -111, -53, 21, 107, 163, 221, 299, + 358, 415, 460, 486, 530, 582, 642, 683, 688, 699, 728, 765, + 773, 751, 731, 696, 638, 578, 525, 466, 401, 317, 222, 151, + 113, 76, 38, 14, -39, -124, -192, -235, -258, -288, -344, -406, +-462, -511, -562, -590, -594, -606, -619, -618, -598, -576, -551, -515, +-478, -455, -441, -416, -372, -330, -286, -228, -184, -149, -88, -11, + 60, 112, 164, 211, 237, 267, 306, 337, 350, 370, 403, 409, + 414, 444, 469, 468, 444, 423, 410, 396, 373, 346, 328, 302, + 281, 257, 203, 126, 50, 2, -33, -65, -81, -106, -134, -157, +-190, -217, -246, -279, -312, -346, -363, -376, -367, -343, -340, -344, +-334, -312, -288, -261, -233, -222, -219, -204, -182, -164, -136, -104, + -84, -71, -67, -55, -26, -10, -2, 22, 25, 38, 79, 110, + 160, 199, 222, 253, 265, 263, 261, 267, 266, 243, 215, 195, + 193, 197, 192, 182, 174, 150, 125, 120, 108, 100, 87, 68, + 53, 15, -42, -66, -52, -53, -73, -104, -118, -79, -41, -48, + -74, -94, -112, -116, -110, -121, -114, -97, -96, -96, -94, -85, + -71, -61, -65, -96, -128, -131, -122, -118, -94, -61, -34, 0, + 19, -1, -38, -42, -13, -3, 17, 54, 61, 86, 128, 145, + 143, 132, 136, 132, 107, 89, 92, 113, 165, 199, 186, 178, + 151, 125, 109, 59, 23, 6, -9, -3, 4, 10, 11, -27, + -85, -128, -157, -170, -171, -164, -135, -110, -121, -141, -158, -171, +-157, -136, -124, -115, -106, -71, -35, -31, -29, -30, -45, -60, + -70, -74, -70, -36, 13, 39, 63, 84, 98, 109, 120, 140, + 131, 107, 103, 107, 93, 55, 34, 24, 13, -1, -10, -3, + -10, 1, 27, 34, 32, 28, 50, 56, 40, 37, 10, -6, + -8, -27, -36, -46, -79, -110, -116, -112, -128, -124, -91, -82, + -67, -50, -47, -23, 4, 34, 50, 35, 6, -25, -11, 24, + 41, 59, 73, 52, 32, 22, -1, 3, 18, 27, 38, 51, + 67, 81, 99, 81, 49, 46, 52, 73, 96, 112, 114, 99, + 92, 84, 70, 53, 48, 57, 39, 15, 1, -12, -15, -24, + -31, -21, -15, -9, 15, 38, 31, 4, -11, -10, -35, -71, + -85, -95, -87, -60, -42, -34, -44, -58, -72, -86, -88, -73, + -42, -16, 7, 19, 10, 10, 4, -7, 6, 40, 73, 81, + 74, 53, 52, 71, 70, 75, 77, 70, 75, 86, 107, 120, + 114, 103, 92, 82, 70, 49, 29, 7, -27, -43, -50, -63, + -55, -24, -3, -18, -35, -50, -79, -92, -107, -111, -108, -118, +-121, -120, -104, -99, -91, -67, -60, -41, -33, -51, -55, -66, + -77, -75, -88, -93, -77, -49, -28, -35, -25, -4, 6, 38, + 74, 85, 70, 60, 63, 57, 45, 32, 42, 60, 56, 57, + 44, 4, -5, 4, 11, 46, 74, 71, 59, 56, 76, 104, + 110, 104, 96, 74, 44, 3, -15, -10, -12, 7, 17, 3, + -11, -26, -43, -51, -56, -70, -63, -64, -81, -81, -86, -82, + -75, -100, -120, -146, -167, -150, -125, -107, -94, -61, -36, -45, + -44, -42, -44, -41, -50, -56, -38, 0, 49, 104, 131, 127, + 134, 145, 148, 156, 150, 143, 131, 108, 102, 103, 103, 100, + 102, 95, 62, 49, 68, 89, 90, 83, 58, 28, 32, 24, + -7, -40, -92, -117, -102, -98, -80, -53, -52, -65, -84, -93, + -88, -93, -94, -71, -51, -31, 3, 6, -14, -41, -74, -88, + -92, -99, -96, -82, -82, -67, -41, -53, -63, -47, -27, -1, + 11, 18, 32, 33, 34, 63, 107, 133, 145, 143, 121, 90, + 74, 66, 46, 52, 80, 92, 108, 103, 59, 25, 10, 1, + 13, 25, -2, -27, -17, -28, -39, -27, -36, -34, -16, -12, + -16, -38, -67, -74, -66, -64, -60, -46, -54, -78, -103, -128, +-132, -153, -174, -166, -145, -123, -135, -129, -113, -112, -89, -88, + -76, -50, -25, 8, 27, 56, 67, 67, 83, 96, 105, 104, + 98, 93, 95, 109, 114, 122, 150, 161, 154, 153, 160, 163, + 164, 155, 128, 107, 95, 77, 65, 44, 8, -42, -81, -104, +-124, -117, -102, -85, -67, -69, -68, -69, -84, -92, -104, -121, +-125, -120, -107, -97, -91, -88, -89, -86, -89, -81, -63, -61, + -43, -10, 7, 10, 14, 27, 25, 23, 24, 23, 43, 53, + 61, 72, 64, 63, 65, 81, 96, 96, 107, 107, 96, 105, + 108, 94, 79, 63, 61, 78, 85, 97, 126, 141, 128, 96, + 71, 62, 53, 42, 31, 14, -4, -8, -6, -10, -25, -36, + -25, -24, -36, -25, -21, -47, -83, -100, -111, -122, -107, -86, + -79, -74, -84, -110, -110, -95, -85, -73, -72, -78, -91, -109, +-101, -75, -71, -67, -39, -19, -3, 27, 58, 83, 100, 114, + 114, 90, 90, 114, 128, 140, 154, 142, 124, 130, 129, 107, + 86, 73, 52, 23, 19, 39, 54, 68, 69, 49, 20, -6, + -12, -26, -39, -33, -39, -67, -77, -70, -91, -109, -113, -129, +-142, -151, -152, -154, -156, -150, -144, -136, -125, -132, -152, -137, +-109, -89, -49, -33, -47, -41, -36, -42, -40, -34, -35, -31, + -15, -1, 28, 70, 87, 93, 105, 104, 83, 58, 64, 99, + 112, 132, 171, 157, 117, 92, 66, 57, 65, 66, 60, 42, + 42, 67, 63, 42, 35, 30, 14, -11, -25, -26, -20, -14, + -13, -9, -6, 0, 2, -8, -31, -65, -71, -69, -80, -60, + -37, -37, -52, -82, -107, -107, -89, -75, -70, -66, -70, -77, + -64, -44, -20, 14, 30, 39, 37, 39, 64, 89, 101, 104, + 103, 87, 92, 97, 93, 99, 86, 89, 94, 98, 124, 142, + 147, 137, 117, 95, 63, 43, 46, 51, 35, 6, 0, -15, + -35, -42, -63, -64, -55, -55, -45, -41, -49, -65, -84, -93, +-110, -125, -106, -106, -125, -139, -178, -202, -179, -143, -107, -76, + -67, -67, -68, -58, -49, -54, -63, -69, -59, -42, -39, -50, + -45, -29, -33, -34, -10, 17, 25, 31, 41, 53, 56, 35, + 35, 64, 90, 103, 110, 96, 94, 101, 76, 74, 86, 78, + 69, 56, 42, 25, 2, 0, 23, 62, 89, 78, 57, 25, + -7, -15, -21, -11, -10, -30, -29, -31, -41, -41, -46, -56, + -72, -92, -99, -86, -67, -50, -46, -73, -102, -102, -95, -93, + -88, -76, -55, -20, 20, 49, 55, 47, 32, 10, 4, 21, + 59, 111, 141, 159, 163, 138, 118, 110, 111, 113, 100, 78, + 66, 75, 84, 87, 89, 86, 87, 88, 91, 88, 52, 6, + -18, -19, -31, -51, -44, -35, -45, -42, -44, -63, -67, -55, + -45, -30, -32, -53, -72, -75, -70, -71, -71, -86, -74, -48, + -50, -54, -63, -56, -38, -30, -47, -70, -58, -52, -37, -15, + -7, 3, 0, -4, -14, -17, 7, 31, 45, 61, 68, 54, + 36, 38, 49, 60, 68, 59, 47, 39, 27, 23, 26, 42, + 54, 64, 66, 47, 53, 59, 57, 70, 82, 85, 82, 95, + 97, 77, 49, 21, 13, 13, 18, 25, 21, 4, -7, -7, + -21, -24, -16, -27, -37, -40, -49, -64, -67, -54, -49, -79, +-114, -117, -130, -153, -161, -159, -152, -143, -128, -120, -99, -59, + -36, -22, -5, -6, -14, -12, -20, -14, 31, 61, 64, 61, + 42, 42, 56, 60, 71, 77, 86, 99, 92, 83, 88, 89, + 91, 92, 96, 86, 56, 45, 52, 48, 24, 16, 21, 6, + 4, 9, 6, 5, -3, 1, 8, 3, -11, -27, -35, -49, + -63, -62, -70, -78, -67, -63, -58, -47, -45, -36, -38, -49, + -52, -47, -52, -63, -64, -71, -53, -3, 43, 63, 57, 41, + 30, 10, -12, -9, -2, 9, 38, 56, 49, 54, 84, 104, + 103, 96, 86, 84, 82, 65, 52, 51, 59, 54, 29, 25, + 38, 53, 55, 45, 40, 18, 8, 29, 62, 95, 102, 91, + 71, 46, 23, -4, -15, -28, -62, -63, -50, -47, -47, -55, + -57, -63, -88, -109, -124, -150, -152, -140, -144, -117, -93, -97, + -88, -86, -96, -110, -125, -128, -127, -96, -39, -12, -14, -24, + -27, -35, -49, -37, -7, 23, 45, 54, 46, 56, 59, 36, + 31, 32, 49, 63, 68, 68, 52, 49, 48, 46, 44, 56, + 68, 51, 42, 52, 45, 26, 31, 36, 24, 17, 11, 15, + 1, -26, -44, -59, -52, -35, -38, -55, -61, -59, -52, -49, + -57, -32, -7, -6, -12, -25, -40, -50, -44, -42, -53, -63, + -63, -55, -60, -70, -70, -64, -59, -48, -14, 25, 50, 63, + 63, 64, 49, 21, 13, 15, 37, 54, 48, 60, 81, 103, + 102, 86, 81, 76, 78, 88, 106, 118, 102, 70, 43, 31, + 23, 32, 41, 23, 13, 14, 13, 10, 4, -7, -14, -26, + -52, -59, -61, -75, -83, -89, -77, -69, -92, -92, -92, -92, + -60, -67, -82, -79, -85, -66, -43, -26, -16, -18, -10, -13, + -17, -5, -2, 15, 48, 56, 48, 43, 42, 55, 72, 64, + 43, 34, 37, 32, 17, 20, 24, 26, 39, 54, 67, 79, + 84, 79, 71, 64, 53, 27, 31, 49, 49, 41, 24, 5, + 5, 16, 23, 46, 49, 32, 17, -13, -27, -28, -35, -48, + -56, -42, -36, -43, -48, -56, -67, -84, -110, -135, -123, -98, + -85, -39, -9, -13, -7, -18, -29, -37, -57, -41, -19, -17, + -10, -24, -41, -29, -16, 8, 29, 36, 33, 20, 33, 38, + 26, 57, 88, 86, 78, 75, 70, 78, 96, 91, 85, 77, + 64, 64, 68, 57, 29, 16, 18, 27, 46, 46, 29, -2, + -47, -85, -95, -72, -52, -67, -92, -110, -117, -101, -78, -68, + -70, -59, -53, -68, -67, -57, -42, -13, 2, 6, 7, 3, + 5, 0, -7, -6, -2, 4, 14, 45, 79, 103, 115, 113, + 114, 100, 74, 40, 31, 62, 60, 48, 53, 31, -7, -28, + -22, -10, -9, 3, 5, 4, 24, 48, 71, 70, 56, 39, + 9, 9, 13, -9, 11, 20, -1, 21, 34, 15, 0, -22, + -36, -41, -41, -29, -19, -2, 1, -11, -6, -12, -21, -20, + -13, 13, 20, -4, -31, -49, -53, -47, -35, -25, -25, -35, + -46, -50, -42, -36, -27, -10, 1, -11, -35, -50, -56, -50, + -37, -14, 15, 31, 43, 49, 49, 52, 57, 71, 94, 121, + 131, 118, 96, 66, 56, 49, 23, 7, -5, -16, -34, -55, + -65, -66, -45, -39, -34, -22, -29, -22, -38, -82, -116, -132, +-138, -132, -106, -77, -50, -50, -64, -74, -102, -112, -91, -57, + -10, 27, 37, 20, 3, -5, -5, 7, 23, 39, 41, 32, + 25, -7, -30, -25, -15, 6, 25, 46, 57, 56, 70, 60, + 28, 24, 38, 52, 66, 52, 28, 24, 42, 56, 49, 38, + 14, -11, -22, -8, 13, 13, 27, 32, 25, 36, 42, 40, + 38, 39, 37, 35, 27, 7, -4, -8, -9, -5, -15, -30, + -44, -62, -64, -62, -51, -41, -48, -42, -41, -60, -64, -48, + -17, 15, 36, 47, 30, 1, -3, -12, -23, -20, -14, -1, + 8, 12, 14, 14, 15, 7, 3, 0, -3, 2, 10, 38, + 66, 64, 68, 84, 92, 96, 93, 74, 47, 29, 8, -18, + -30, -35, -31, -24, -30, -29, -29, -34, -21, -18, -41, -57, + -63, -67, -61, -47, -39, -53, -68, -69, -73, -67, -36, 0, + 14, 12, 6, -4, -3, 27, 52, 61, 64, 48, 16, -17, + -23, -20, -18, -21, -45, -49, -20, 17, 21, 1, -5, -5, + -1, 4, 18, 29, 22, 0, -24, -20, -8, 21, 66, 63, + 38, 14, -14, -29, -40, -31, -14, -14, -1, 20, 16, 12, + 13, 7, -13, -38, -43, -29, -18, 1, 9, -15, -34, -52, + -66, -54, -44, -54, -63, -62, -69, -58, -28, -9, 14, 40, + 59, 57, 53, 61, 49, 46, 38, 20, 13, 3, -7, -16, + -11, -3, -3, 1, 17, 51, 73, 78, 92, 108, 98, 77, + 81, 90, 93, 92, +}; + +const int16_t test_wav_backward[] = +{ + -14, -15, -13, -11, -11, -10, -6, -11, -6, -6, -5, -3, + 1, 1, 0, 1, -1, -2, -4, -4, -6, -8, -7, -13, + -14, -12, -11, -17, -22, -17, -25, -24, -27, -34, -34, -38, + -42, -47, -49, -48, -48, -43, -42, -38, -43, -43, -36, -39, + -33, -33, -29, -25, -19, -14, -12, -10, -10, -12, -11, -12, + -9, -2, -1, 2, 8, 8, 12, 15, 16, 25, 22, 23, + 27, 30, 32, 31, 33, 35, 36, 33, 32, 31, 29, 29, + 30, 27, 33, 35, 35, 32, 34, 35, 31, 35, 36, 40, + 42, 43, 41, 40, 36, 35, 33, 25, 24, 25, 17, 18, + 19, 20, 23, 23, 22, 19, 21, 18, 15, 12, 14, 9, + 7, 4, 2, 1, -2, 5, 2, 2, 2, 3, 5, 6, + 5, 4, 4, 2, 2, 2, -4, -8, -9, -9, -7, -10, + -11, -10, -14, -15, -12, -11, -9, -7, -8, -8, -8, -7, + -6, -5, -6, -5, -3, 0, 1, 4, 3, 2, 9, 7, + 10, 10, 10, 5, 9, 9, 8, 9, 4, 8, 6, 6, + 6, 10, 10, 10, 18, 19, 15, 14, 14, 17, 18, 18, + 15, 17, 14, 19, 19, 15, 18, 19, 22, 25, 25, 23, + 25, 26, 27, 29, 34, 35, 35, 37, 31, 28, 24, 23, + 19, 21, 12, 10, 7, 6, 8, 0, 4, 5, 7, 10, + 11, 9, 2, 2, -1, -5, -3, -6, -7, -15, -17, -21, + -19, -19, -19, -18, -23, -23, -23, -20, -19, -20, -22, -23, + -23, -28, -34, -36, -38, -43, -40, -37, -39, -35, -31, -23, + -19, -15, -17, -21, -15, -19, -17, -16, -19, -23, -25, -30, + -34, -39, -37, -30, -23, -16, -4, 0, -2, 1, 0, -1, + 0, 4, 7, 7, 8, 9, 6, 1, 0, -2, -1, -2, + -4, -3, -5, -6, -6, -12, -16, -15, -18, -16, -14, -9, + -4, -6, -1, -4, -3, 1, 0, 7, 10, 14, 20, 17, + 22, 21, 9, 2, 2, 8, 28, 45, 48, 45, 40, 39, + 35, 34, 34, 29, 31, 29, 35, 32, 35, 31, 20, 13, + 6, 5, 8, 13, 9, 3, -1, -4, 0, 1, 6, 6, + -2, -8, -2, 3, 6, 8, 8, -2, -10, -9, -2, -6, + -8, -7, -14, -18, -24, -22, -22, -22, -23, -27, -22, -24, + -28, -25, -28, -33, -27, -25, -26, -31, -32, -33, -36, -39, + -36, -32, -33, -32, -34, -34, -31, -30, -24, -17, -15, -16, + -13, -9, 1, 12, 16, 19, 16, 9, 7, 11, 18, 17, + 16, 15, 8, -1, 1, 6, 10, 13, 21, 21, 15, 13, + 9, 11, 14, 18, 23, 26, 19, 14, 11, 8, 17, 19, + 17, 15, 11, 12, 32, 43, 43, 33, 24, 21, 28, 41, + 54, 58, 54, 55, 50, 51, 44, 37, 38, 41, 50, 61, + 61, 51, 32, 11, 3, 2, 14, 25, 26, 14, 1, -10, + -11, -4, 4, -8, -22, -29, -17, 16, 59, 57, 19, -24, + -52, -45, 3, 42, 39, -8, -53, -67, -41, -7, 0, -34, + -87, -130, -134, -90, -40, -29, -49, -93, -128, -122, -85, -44, + -24, -37, -63, -77, -74, -54, -33, -27, -41, -72, -83, -74, + -51, -28, -18, -30, -53, -58, -42, -21, -1, 3, -6, -23, + -28, -18, -1, 7, 3, 1, 3, 6, 21, 24, 25, 28, + 25, 28, 36, 41, 47, 53, 55, 53, 46, 41, 42, 48, + 46, 47, 43, 35, 34, 30, 25, 19, 7, 1, 1, 11, + 24, 23, 17, 7, -5, -6, -8, -6, -5, 2, 12, 27, + 37, 33, 15, -6, -20, -17, 5, 18, 24, 21, 8, -1, + 1, -1, -4, -3, -19, -21, -3, 12, 16, 12, -5, -22, + -36, -25, -2, 11, 6, -9, -24, -31, -25, -16, -16, -22, + -30, -28, -17, 0, 9, -1, -22, -38, -46, -41, -28, -17, + -24, -40, -59, -73, -76, -66, -48, -36, -30, -28, -39, -52, + -54, -43, -36, -36, -43, -58, -60, -50, -35, -18, -14, -25, + -36, -39, -37, -23, -7, 2, 0, -3, -2, 5, 12, 22, + 35, 40, 35, 39, 43, 50, 55, 59, 54, 51, 49, 52, + 60, 62, 58, 62, 66, 68, 65, 54, 42, 41, 49, 55, + 64, 65, 54, 44, 33, 32, 45, 55, 60, 63, 53, 49, + 47, 47, 43, 33, 19, 8, 10, 14, 26, 24, 9, 2, + -14, -17, -11, 0, -7, -23, -43, -48, -41, -35, -25, -24, + -36, -47, -44, -34, -17, -5, -13, -20, -35, -34, -20, -8, + -1, -3, -7, -4, 4, 2, -1, -11, -25, -25, -18, -14, + -12, -14, -20, -32, -24, -18, -3, 5, -2, -10, -18, -13, + 2, 21, 25, 29, 20, 19, 27, 33, 33, 31, 18, 1, + -3, 8, 20, 29, 24, 10, -6, -7, 0, 14, 23, 19, + 9, -9, -5, 6, 19, 18, 11, 3, -6, 7, 24, 36, + 40, 34, 22, 14, 17, 20, 28, 27, 24, 14, 4, 3, + 8, 16, 23, 20, 17, 5, -8, -11, -4, 12, 23, 24, + 15, 7, 8, 10, 19, 24, 13, 8, 2, 11, 18, 15, + 9, -11, -22, -18, -8, 9, 16, 11, 4, 2, 9, 8, + 8, 9, 13, 15, 19, 21, 17, 6, -9, -17, -15, -10, + -5, -12, -31, -45, -50, -50, -34, -29, -38, -44, -49, -40, + -31, -22, -18, -17, -24, -25, -20, -12, 0, 5, 3, 0, + -6, -6, -1, 7, 15, 18, 16, 15, 13, 11, 13, 16, + 16, 20, 29, 34, 34, 33, 35, 36, 34, 31, 23, 19, + 20, 22, 28, 29, 28, 26, 22, 21, 27, 32, 37, 38, + 24, 18, 17, 22, 36, 40, 36, 25, 19, 21, 28, 34, + 35, 36, 35, 30, 26, 32, 24, 22, 19, 16, 16, 16, + 16, 17, 16, 3, -5, -10, -13, -17, -17, -19, -21, -24, + -22, -17, -19, -25, -29, -28, -30, -30, -22, -13, -11, -7, + -7, -7, -4, -1, 3, 8, 8, 4, 2, 3, 4, -4, + -9, -12, -16, -21, -18, -17, -21, -22, -25, -26, -25, -25, + -22, -18, -18, -25, -30, -27, -26, -20, -9, -2, -6, -5, + -4, 1, 6, 5, 5, 4, 5, 9, 13, 24, 26, 22, + 20, 16, 15, 20, 23, 20, 16, 8, 3, 6, 8, 9, + 9, 9, 8, 9, 9, 9, 7, 5, -2, -9, -15, -23, + -23, -20, -18, -14, -11, -15, -21, -28, -28, -27, -24, -16, + -11, -11, -13, -17, -14, -13, -11, -8, -16, -18, -18, -11, + -9, -9, -8, -9, -8, -6, -4, -5, -5, -12, -17, -16, + -21, -19, -18, -15, -20, -24, -24, -26, -31, -37, -39, -41, + -44, -51, -46, -45, -43, -42, -43, -42, -41, -36, -30, -27, + -26, -27, -24, -25, -28, -28, -26, -22, -17, -17, -16, -13, + -10, -17, -13, -13, -15, -16, -14, -15, -15, -16, -18, -14, + -19, -17, -12, -15, -15, -17, -21, -25, -20, -16, -12, -7, + -11, -13, -14, -7, -4, -2, 3, 5, 3, 3, 5, 11, + 14, 10, 9, 9, 7, 13, 17, 19, 17, 20, 17, 20, + 20, 18, 16, 11, 14, 15, 18, 20, 16, 15, 16, 17, + 19, 24, 20, 15, 10, 8, 7, 3, -3, -4, -10, -12, + -7, -5, -4, -2, -5, -3, 2, 6, 13, 8, 6, 10, + 12, 17, 16, 14, 12, 11, 9, 9, 10, 6, 3, 3, + -5, -6, -4, -8, -9, -10, -12, -10, -8, -3, -5, -9, + -5, -7, -5, -6, -6, -6, -6, -9, -5, -3, -1, 6, + 4, 10, 18, 21, 26, 25, 26, 27, 34, 33, 36, 40, + 40, 38, 44, 44, 41, 41, 40, 38, 39, 40, 38, 38, + 40, 42, 37, 35, 36, 36, 39, 36, 38, 39, 36, 31, + 36, 40, 44, 49, 51, 51, 49, 50, 53, 51, 53, 53, + 53, 60, 60, 63, 61, 55, 53, 55, 60, 59, 59, 57, + 59, 59, 54, 50, 47, 38, 36, 32, 29, 29, 27, 18, + 12, 5, 5, 5, 1, -4, -12, -20, -24, -32, -36, -38, + -42, -37, -43, -43, -41, -37, -38, -35, -33, -31, -25, -26, + -24, -28, -23, -18, -16, -18, -19, -14, -20, -19, -13, -11, + -14, -14, -18, -19, -17, -18, -23, -24, -27, -28, -31, -36, + -37, -38, -39, -42, -38, -36, -40, -38, -35, -36, -37, -36, + -31, -27, -23, -17, -11, -7, 5, 9, 13, 19, 17, 20, + 19, 22, 30, 27, 25, 22, 18, 17, 20, 18, 16, 16, + 11, 14, 17, 18, 18, 11, 16, 16, 13, 12, 15, 16, + 12, 10, 8, 4, 10, 13, 14, 16, 17, 21, 28, 33, + 32, 31, 32, 39, 44, 47, 53, 50, 55, 59, 61, 65, + 65, 64, 58, 53, 56, 52, 48, 46, 38, 33, 31, 26, + 23, 18, 17, 9, 4, -3, -7, -9, -14, -20, -26, -26, + -27, -30, -35, -38, -35, -33, -34, -28, -25, -22, -19, -20, + -20, -16, -17, -19, -17, -19, -21, -18, -18, -18, -25, -30, + -35, -33, -33, -26, -23, -21, -15, -11, -5, 1, 3, 1, + 5, 9, 7, 9, 14, 12, 11, 9, 9, 9, 8, 13, + 14, 22, 26, 30, 36, 33, 38, 40, 46, 51, 54, 50, + 46, 48, 41, 36, 39, 38, 36, 30, 29, 26, 17, 16, + 13, 11, 10, 11, 8, 3, 7, 8, 8, 12, 9, 7, + 8, 8, 8, 9, 14, 8, 9, 10, 9, 6, 8, 6, + 3, 1, 3, 1, 2, 7, 5, 1, 1, 1, -4, -5, + -8, -12, -20, -20, -29, -36, -34, -40, -41, -43, -40, -42, + -45, -45, -50, -56, -57, -59, -61, -71, -73, -74, -86, -89, + -91, -92, -94, -90, -88, -93, -86, -87, -86, -85, -81, -78, + -77, -73, -72, -70, -67, -65, -64, -62, -61, -61, -60, -60, + -65, -66, -63, -68, -69, -72, -69, -73, -78, -71, -71, -68, + -70, -63, -58, -57, -56, -56, -54, -45, -38, -25, -19, -16, + -12, -16, -16, -12, -11, -8, -2, -6, -6, -4, -9, -11, + -10, -7, -8, -8, -3, -5, -10, -11, -9, -10, -11, -13, + -18, -27, -24, -29, -28, -28, -31, -29, -29, -23, -23, -18, + -17, -12, -9, -6, -7, -10, -10, -11, -12, -13, -9, -14, + -17, -19, -21, -22, -19, -20, -27, -24, -31, -40, -43, -44, + -46, -53, -48, -45, -50, -47, -51, -40, -37, -35, -31, -29, + -27, -29, -26, -23, -18, -11, -6, -4, 0, 1, 3, 3, + 2, 1, 1, 5, 1, 5, 3, 4, 6, 6, 6, 8, + 10, 10, 13, 15, 20, 23, 28, 30, 31, 31, 37, 37, + 35, 39, 32, 30, 28, 27, 27, 27, 25, 25, 27, 27, + 33, 39, 40, 42, 46, 49, 57, 70, 74, 80, 78, 79, + 79, 80, 79, 76, 73, 73, 71, 69, 68, 60, 59, 60, + 55, 55, 56, 49, 52, 49, 47, 50, 47, 44, 39, 39, + 37, 34, 32, 29, 29, 21, 22, 19, 8, 11, 7, 5, + 4, 7, 4, -2, -4, -10, -3, -3, -2, 3, 3, 1, + 1, 0, -3, -2, 5, 2, 1, 4, 3, 2, 2, 3, + 6, 5, 5, 7, 9, 8, 9, 10, 4, 3, 5, 1, + 2, 3, 2, 4, 3, 5, 8, 21, 26, 35, 45, 47, + 53, 58, 63, 67, 71, 72, 70, 70, 65, 55, 52, 49, + 45, 40, 29, 29, 25, 25, 27, 25, 22, 24, 24, 22, + 26, 27, 31, 31, 23, 29, 33, 34, 35, 34, 34, 32, + 30, 28, 30, 30, 25, 28, 30, 30, 31, 32, 29, 29, + 30, 32, 31, 33, 30, 30, 27, 25, 16, 15, 20, 16, + 20, 16, 15, 15, 10, 6, 5, 8, 2, 6, 3, -4, + -7, -16, -25, -25, -24, -31, -40, -42, -41, -38, -36, -36, + -32, -30, -31, -23, -15, -10, -7, -7, -5, -4, -3, -2, + -4, -1, 0, -3, -4, -5, -6, -6, -4, -6, -8, -5, + -6, -7, -5, -6, -6, -4, -2, 2, 7, 12, 19, 27, + 33, 33, 37, 41, 41, 47, 48, 41, 41, 39, 37, 36, + 34, 34, 27, 24, 22, 19, 17, 17, 13, 5, 5, 7, + 11, 13, 18, 18, 18, 19, 14, 13, 10, 4, -1, -5, + -12, -15, -20, -26, -29, -28, -33, -26, -23, -23, -21, -19, + -11, -7, -1, 8, 15, 21, 20, 22, 24, 19, 24, 26, + 27, 27, 32, 27, 23, 23, 23, 25, 24, 24, 16, 11, + 6, 3, 8, 0, -4, -9, -14, -17, -20, -20, -24, -29, + -36, -34, -31, -37, -38, -40, -41, -44, -44, -42, -41, -42, + -42, -39, -38, -37, -36, -37, -38, -41, -43, -44, -41, -38, + -37, -38, -41, -41, -44, -41, -39, -42, -41, -38, -41, -40, + -43, -48, -43, -46, -50, -46, -42, -36, -35, -33, -26, -18, + -16, -12, -10, -7, 0, 3, 6, 7, 7, 7, 12, 20, + 21, 26, 28, 32, 32, 34, 38, 34, 37, 32, 35, 31, + 26, 25, 18, 17, 13, 10, 2, -2, -3, -6, -4, -4, + -2, -1, -8, -11, -12, -8, -7, -4, -2, 2, 2, -3, + -1, -1, -6, -15, -15, -21, -22, -25, -25, -27, -30, -33, + -30, -27, -27, -27, -30, -32, -32, -34, -33, -32, -36, -37, + -46, -51, -54, -61, -65, -67, -72, -76, -77, -79, -75, -76, + -77, -72, -68, -64, -59, -56, -58, -53, -48, -47, -51, -50, + -49, -41, -39, -41, -40, -37, -39, -40, -38, -36, -31, -23, + -15, -15, -17, -16, -15, -18, -14, -19, -17, -17, -22, -21, + -24, -25, -26, -25, -25, -19, -19, -19, -13, -9, 0, 5, + 13, 18, 16, 16, 17, 15, 22, 26, 27, 28, 30, 30, + 29, 27, 31, 33, 32, 34, 35, 35, 42, 44, 44, 48, + 47, 46, 45, 43, 42, 44, 42, 37, 33, 31, 26, 27, + 18, 17, 13, 6, 0, -4, -5, -5, -4, -4, -7, -12, + -14, -17, -19, -19, -25, -28, -26, -28, -27, -29, -32, -28, + -30, -25, -23, -22, -19, -20, -15, -16, -18, -11, -5, -3, + -6, -10, -10, -14, -12, -9, -8, -7, -9, -8, -6, -10, + -10, -6, -6, 4, 2, 0, 2, 7, 8, 9, 11, 7, + 10, 8, 9, 5, 6, 3, 3, 5, 4, 6, 10, 16, + 18, 16, 19, 24, 25, 32, 32, 35, 30, 29, 27, 25, + 24, 24, 25, 25, 23, 19, 20, 17, 20, 20, 23, 28, + 29, 29, 29, 32, 34, 33, 31, 31, 29, 27, 23, 20, + 15, 11, 9, 8, 11, 7, 10, 8, 10, 10, 9, 12, + 15, 16, 15, 18, 15, 11, 7, 4, -2, -6, -5, -7, + -12, -16, -16, -21, -20, -24, -25, -22, -20, -25, -23, -22, + -28, -30, -30, -31, -32, -35, -37, -35, -36, -31, -38, -41, + -40, -41, -41, -41, -38, -37, -35, -33, -38, -38, -39, -34, + -33, -39, -37, -34, -28, -23, -24, -24, -19, -19, -18, -15, + -13, -16, -13, -12, -13, -14, -18, -19, -14, -15, -18, -23, + -24, -18, -19, -16, -15, -14, -15, -8, -1, -6, 1, 2, + 5, 3, 4, 4, 7, 12, 11, 13, 16, 20, 20, 22, + 28, 30, 30, 31, 29, 27, 27, 22, 24, 25, 25, 23, + 19, 22, 18, 19, 18, 14, 11, 9, 9, 10, 10, 13, + 12, 14, 10, 7, 3, 1, 2, 0, 2, 3, 5, -2, + -2, 0, -1, 0, -1, -5, -10, -11, -14, -15, -15, -17, + -22, -26, -30, -33, -33, -34, -35, -34, -32, -30, -28, -25, + -22, -19, -9, -9, -10, -5, 1, 1, 3, 8, 9, 14, + 12, 14, 17, 16, 19, 19, 17, 16, 15, 13, 12, 13, + 16, 17, 15, 14, 12, 14, 14, 14, 17, 20, 23, 26, + 30, 33, 43, 48, 45, 44, 42, 41, 36, 34, 32, 28, + 25, 23, 25, 26, 25, 18, 12, 16, 18, 18, 22, 27, + 30, 33, 34, 35, 34, 34, 36, 38, 38, 35, 32, 34, + 37, 38, 42, 45, 47, 48, 46, 46, 43, 43, 45, 41, + 33, 31, 30, 28, 24, 20, 15, 10, 16, 19, 18, 22, + 22, 24, 18, 14, 10, 8, 12, 9, 11, 3, 1, -6, + -13, -19, -30, -37, -43, -48, -53, -53, -57, -59, -54, -61, + -63, -65, -66, -71, -70, -65, -68, -70, -70, -66, -69, -71, + -69, -67, -62, -64, -60, -58, -58, -56, -50, -45, -47, -41, + -34, -32, -29, -26, -22, -25, -20, -21, -25, -27, -30, -32, + -28, -25, -21, -15, -12, -9, -5, -5, -1, 3, 5, 8, + 12, 17, 25, 28, 22, 20, 18, 10, 10, 15, 16, 18, + 17, 24, 25, 26, 29, 26, 28, 24, 23, 20, 19, 18, + 15, 13, 11, 4, 1, -5, -9, -11, -11, -12, -14, -14, + -18, -19, -22, -26, -24, -27, -25, -22, -19, -27, -29, -29, + -31, -32, -37, -39, -38, -35, -41, -35, -28, -35, -29, -27, + -28, -32, -32, -31, -35, -33, -32, -31, -32, -31, -33, -35, + -35, -38, -36, -33, -29, -25, -23, -20, -19, -16, -14, -9, + -8, -6, -4, -2, 2, 2, 4, 3, 3, 3, 2, 3, + 3, 4, 2, 3, 9, 7, 14, 18, 19, 17, 28, 28, + 24, 26, 18, 22, 21, 18, 19, 19, 18, 15, 22, 19, + 16, 17, 13, 18, 12, 12, 19, 18, 20, 22, 23, 23, + 24, 23, 19, 17, 12, 13, 12, 14, 16, 16, 15, 15, + 19, 16, 10, 8, 4, 1, 5, 2, 4, 1, -4, -10, + -13, -7, -10, -7, -4, -4, -2, 3, 8, 7, 10, 7, + 3, 5, 8, 6, 7, 9, 4, -3, -9, -8, -9, -11, + -13, -20, -21, -27, -25, -30, -28, -26, -31, -23, -18, -19, + -10, -9, -9, -11, -11, -9, -9, -8, -14, -13, -15, -17, + -18, -21, -24, -26, -28, -30, -30, -29, -29, -30, -30, -31, + -35, -38, -34, -31, -33, -32, -36, -37, -43, -38, -39, -40, + -33, -30, -24, -25, -18, -18, -15, -11, -7, -3, -6, -1, + 2, 3, 8, 4, 4, 6, 2, 0, -1, 4, 1, 4, + 6, 10, 14, 20, 23, 22, 25, 26, 32, 34, 37, 40, + 40, 42, 44, 43, 49, 49, 47, 45, 46, 46, 41, 44, + 42, 42, 39, 38, 39, 34, 32, 28, 21, 18, 14, 14, + 10, 11, 13, 6, 6, 2, 4, 2, -6, -12, -15, -19, + -20, -18, -17, -18, -19, -20, -22, -21, -24, -25, -23, -31, + -32, -36, -33, -33, -34, -37, -38, -37, -41, -39, -36, -35, + -33, -31, -26, -26, -24, -21, -19, -18, -17, -16, -14, -14, + -7, -9, -4, -2, 1, 1, 0, 5, 3, 8, 16, 23, + 27, 30, 32, 33, 37, 37, 39, 36, 35, 36, 35, 33, + 26, 24, 17, 14, 14, 16, 19, 25, 30, 29, 28, 32, + 36, 38, 43, 44, 40, 37, 37, 35, 32, 29, 25, 24, + 21, 23, 27, 28, 26, 28, 28, 31, 32, 34, 36, 36, + 36, 31, 33, 29, 23, 23, 19, 12, 11, 8, 5, 1, + 1, 2, -1, -1, 1, 1, 1, 2, 2, -2, 0, 1, + 2, -4, -9, -7, -12, -12, -10, -12, -14, -12, -10, -11, + -12, -9, -9, -13, -14, -14, -18, -24, -23, -23, -26, -26, + -23, -23, -26, -20, -14, -15, -10, -3, 2, 4, 7, 9, + 11, 11, 13, 15, 17, 15, 14, 15, 14, 12, 9, 9, + 9, 8, 10, 12, 8, 8, 10, 8, 9, 13, 15, 13, + 13, 10, 11, 14, 11, 10, 7, 8, 3, 2, 4, 2, + 2, 2, 5, 3, 3, 6, 10, 6, 6, 3, 3, 4, + 6, 9, 5, 8, 9, 8, 9, 7, 9, 7, 8, 5, + 2, 4, 5, 3, 5, 6, 0, -1, -8, -8, -13, -8, + -10, -16, -15, -16, -12, -12, -17, -15, -17, -15, -16, -17, + -19, -19, -21, -18, -22, -21, -21, -28, -29, -32, -31, -36, + -34, -36, -40, -41, -42, -39, -42, -38, -37, -39, -35, -34, + -34, -34, -33, -35, -34, -33, -29, -24, -24, -19, -23, -20, + -16, -17, -14, -11, -15, -13, -13, -13, -9, -10, -7, -10, + -8, -9, -7, -8, -10, -7, -8, -4, -5, 0, 1, 1, + 1, 6, 8, 11, 13, 13, 15, 19, 19, 22, 19, 20, + 21, 17, 15, 17, 16, 17, 18, 16, 17, 14, 12, 13, + 11, 3, 0, 0, -2, -2, -5, -4, -6, -8, -4, -3, + -6, -2, -2, -1, -1, -3, -1, -2, -1, -2, 0, 1, + -4, -5, -8, -8, -11, -13, -11, -11, -9, -6, -4, -3, + 1, 2, 4, 3, 3, 7, 10, 4, -1, 1, -1, 1, + 1, -1, -3, -5, -2, -7, -13, -16, -15, -9, -10, -9, + -6, -8, -4, -9, -12, -13, -16, -23, -27, -25, -25, -23, + -21, -19, -17, -17, -17, -13, -14, -10, -8, -7, -11, -6, + -5, -3, -2, -4, -5, -8, 1, 3, 2, 5, 6, 8, + 7, 10, 11, 10, 14, 18, 18, 18, 21, 22, 18, 21, + 18, 22, 22, 23, 24, 21, 20, 23, 20, 25, 23, 25, + 26, 26, 22, 23, 19, 19, 23, 24, 23, 22, 24, 22, + 26, 19, 13, 12, 12, 9, 9, 4, 0, -9, -12, -17, + -11, -10, -7, -6, -11, -5, -8, -5, -7, -7, -10, -13, + -16, -15, -21, -22, -27, -31, -35, -35, -34, -35, -37, -38, + -37, -34, -33, -32, -32, -36, -32, -33, -35, -35, -36, -38, + -40, -43, -41, -39, -41, -44, -44, -42, -40, -36, -39, -38, + -39, -36, -32, -27, -24, -21, -20, -16, -17, -11, -6, -5, + -10, -9, -8, -1, 3, 6, 8, 9, 13, 14, 20, 15, + 20, 22, 24, 23, 25, 32, 33, 37, 39, 39, 37, 39, + 38, 40, 45, 44, 46, 46, 48, 47, 46, 47, 48, 47, + 45, 43, 44, 44, 45, 39, 38, 35, 29, 31, 22, 20, + 17, 19, 18, 18, 20, 19, 19, 16, 20, 18, 16, 15, + 14, 14, 11, 14, 9, 10, 9, 7, 6, -1, 3, -3, + -4, -10, -6, -2, -6, -4, -7, -6, -6, -8, -5, -5, + -6, -9, -17, -22, -23, -25, -24, -22, -23, -26, -24, -21, + -18, -16, -8, -5, -4, 0, 4, 13, 14, 23, 29, 28, + 33, 30, 37, 36, 39, 39, 36, 38, 37, 40, 40, 41, + 39, 35, 39, 33, 35, 37, 35, 32, 26, 26, 20, 19, + 25, 22, 23, 26, 24, 18, 19, 22, 25, 26, 23, 31, + 30, 33, 40, 38, 39, 39, 40, 39, 44, 44, 42, 39, + 36, 34, 32, 30, 27, 25, 25, 25, 24, 18, 23, 27, + 25, 26, 23, 20, 20, 25, 26, 28, 26, 25, 18, 13, + 14, 7, 3, 2, -3, -8, -7, -9, -12, -10, -10, -8, + -13, -16, -15, -16, -15, -19, -19, -18, -26, -24, -25, -28, + -25, -26, -28, -25, -23, -24, -21, -20, -16, -20, -24, -24, + -30, -26, -32, -31, -32, -33, -40, -37, -35, -42, -39, -46, + -46, -44, -41, -39, -39, -34, -37, -31, -27, -25, -26, -24, + -24, -24, -21, -15, -13, -12, -13, -14, -18, -17, -17, -19, + -15, -12, -10, -11, -6, -5, -5, -6, 1, 2, 7, 6, + 2, 2, 6, 7, 3, 7, 3, 5, 9, 7, 11, 12, + 13, 15, 21, 24, 26, 29, 32, 36, 35, 37, 34, 25, + 20, 13, 10, 5, 4, -3, -10, -16, -19, -21, -27, -26, + -26, -29, -29, -24, -26, -26, -22, -30, -28, -24, -23, -18, + -18, -23, -31, -33, -36, -39, -43, -47, -42, -44, -40, -38, + -33, -29, -32, -29, -28, -29, -27, -22, -21, -19, -16, -24, + -23, -18, -20, -23, -22, -22, -26, -28, -20, -15, -11, -7, + -8, -7, -5, -6, -5, -10, -13, -14, -15, -18, -22, -21, + -23, -27, -33, -34, -33, -34, -28, -21, -20, -21, -20, -18, + -14, -8, -2, 5, 9, 15, 16, 26, 30, 35, 38, 43, + 48, 56, 60, 63, 70, 74, 75, 74, 80, 79, 78, 80, + 79, 69, 59, 52, 46, 39, 36, 40, 31, 23, 15, 5, + -2, -2, 2, 8, 14, 11, 8, 12, 14, 21, 29, 29, + 33, 35, 40, 46, 51, 60, 62, 66, 69, 65, 67, 69, + 69, 76, 79, 73, 65, 60, 54, 48, 43, 34, 25, 14, + 4, -3, -14, -18, -33, -44, -50, -61, -75, -82, -86, -97, + -101, -104, -113, -113, -113, -110, -112, -108, -104, -96, -95, -85, + -68, -61, -54, -41, -26, -18, -11, 0, 5, 16, 26, 33, + 33, 39, 44, 49, 57, 57, 59, 54, 54, 58, 56, 52, + 55, 52, 50, 49, 49, 50, 45, 44, 43, 41, 42, 38, + 40, 43, 45, 49, 51, 55, 54, 58, 54, 61, 66, 69, + 73, 76, 83, 89, 98, 109, 116, 123, 127, 132, 137, 139, + 141, 143, 143, 143, 146, 142, 133, 130, 125, 118, 114, 108, + 98, 89, 74, 56, 40, 26, 15, 3, -17, -59, -107, -161, + -201, -230, -252, -287, -335, -396, -467, -522, -560, -576, -584, -600, + -641, -676, -693, -676, -618, -545, -486, -446, -413, -374, -306, -208, + -97, 12, 88, 136, 164, 211, 280, 356, 420, 455, 455, 426, + 400, 394, 403, 410, 393, 355, 299, 239, 199, 183, 179, 162, + 126, 84, 38, 4, -7, -1, 3, -8, -34, -63, -72, -68, + -54, -27, -7, 3, 7, 11, 30, 59, 95, 121, 137, 153, + 170, 188, 208, 233, 249, 261, 266, 264, 262, 256, 255, 248, + 231, 210, 185, 153, 117, 78, 33, 3, -28, -66, -93, -132, + -178, -220, -254, -281, -296, -308, -328, -351, -369, -385, -387, -372, + -338, -310, -289, -270, -245, -216, -172, -121, -77, -34, -1, 27, + 64, 116, 180, 242, 295, 339, 366, 395, 424, 454, 481, 493, + 492, 474, 440, 398, 355, 306, 249, 190, 119, 51, -14, -81, + -152, -221, -289, -346, -381, -407, -428, -455, -485, -511, -529, -523, + -505, -480, -458, -450, -441, -429, -396, -353, -293, -248, -226, -207, + -191, -169, -120, -57, -5, 37, 62, 77, 93, 129, 176, 218, + 248, 261, 261, 262, 271, 289, 316, 330, 339, 335, 323, 315, + 310, 319, 320, 312, 295, 279, 263, 248, 254, 267, 281, 291, + 300, 311, 326, 341, 366, 399, 429, 452, 468, 467, 456, 441, + 425, 423, 410, 388, 352, 306, 247, 189, 137, 84, 25, -35, + -116, -207, -286, -352, -403, -449, -495, -551, -608, -658, -685, -685, + -667, -641, -637, -638, -646, -651, -624, -582, -535, -499, -481, -476, + -479, -466, -427, -377, -354, -339, -344, -365, -363, -344, -316, -279, + -252, -253, -255, -243, -209, -153, -83, -20, 14, 37, 60, 95, + 144, 221, 279, 307, 325, 319, 330, 352, 385, 414, 423, 408, + 394, 380, 390, 416, 431, 441, 422, 401, 384, 384, 391, 411, + 418, 408, 397, 374, 358, 361, 372, 366, 355, 325, 289, 265, + 241, 223, 202, 172, 156, 122, 95, 67, 38, 14, -16, -51, + -77, -100, -129, -153, -183, -208, -218, -228, -230, -232, -232, -231, + -243, -251, -256, -260, -253, -251, -258, -265, -271, -279, -273, -257, + -243, -225, -211, -190, -173, -149, -116, -83, -58, -35, -13, -2, + 21, 47, 73, 100, 116, 120, 127, 131, 138, 140, 135, 117, + 93, 62, 31, 10, -12, -41, -72, -103, -141, -172, -191, -206, + -218, -242, -270, -298, -319, -328, -331, -328, -312, -298, -293, -277, + -255, -220, -175, -135, -106, -77, -46, -15, 13, 51, 73, 85, + 96, 101, 106, 110, 116, 115, 95, 77, 52, 29, 23, 14, + 10, 9, 8, 9, 10, 33, 61, 105, 136, 167, 194, 222, + 249, 277, 303, 323, 354, 370, 375, 396, 419, 447, 483, 514, + 526, 534, 545, 547, 539, 529, 529, 514, 485, 453, 412, 376, + 341, 301, 271, 240, 195, 148, 106, 55, -1, -30, -56, -80, + -99, -108, -117, -126, -123, -90, -49, -5, 38, 77, 108, 134, + 168, 206, 238, 246, 225, 148, 34, -79, -172, -267, -382, -520, + -715, -958, -1219, -1436, -1597, -1750, -1924, -2134, -2352, -2556, -2711, -2755, +-2690, -2612, -2553, -2514, -2461, -2362, -2179, -1891, -1578, -1297, -1096, -927, + -742, -527, -241, 84, 365, 558, 689, 773, 881, 1051, 1264, 1440, + 1542, 1567, 1543, 1519, 1546, 1624, 1715, 1756, 1732, 1673, 1616, 1595, + 1606, 1654, 1679, 1619, 1500, 1384, 1284, 1215, 1189, 1172, 1123, 1016, + 904, 814, 750, 724, 718, 693, 640, 558, 469, 408, 383, 382, + 400, 406, 376, 340, 316, 299, 302, 322, 349, 331, 271, 193, + 115, 33, -37, -99, -160, -264, -391, -527, -669, -791, -888, -979, +-1085, -1214, -1351, -1496, -1627, -1721, -1765, -1789, -1820, -1838, -1840, -1820, +-1767, -1669, -1538, -1400, -1278, -1158, -1025, -871, -700, -514, -333, -153, + 27, 186, 354, 540, 726, 896, 1065, 1202, 1320, 1425, 1534, 1616, + 1669, 1708, 1706, 1702, 1683, 1657, 1622, 1575, 1514, 1429, 1334, 1228, + 1136, 1063, 975, 880, 777, 689, 600, 526, 488, 474, 465, 464, + 463, 462, 458, 478, 515, 535, 529, 507, 459, 378, 276, 168, + 42, -124, -316, -506, -712, -943, -1181, -1420, -1675, -1953, -2211, -2432, +-2656, -2886, -3078, -3192, -3268, -3303, -3253, -3119, -2987, -2847, -2651, -2402, +-2148, -1862, -1540, -1225, -938, -673, -399, -115, 159, 435, 708, 941, + 1145, 1327, 1499, 1652, 1796, 1938, 2035, 2088, 2129, 2158, 2194, 2228, + 2293, 2344, 2364, 2378, 2383, 2389, 2386, 2378, 2366, 2321, 2224, 2107, + 1990, 1879, 1769, 1669, 1567, 1427, 1255, 1088, 937, 785, 618, 454, + 273, 46, -195, -403, -565, -716, -852, -982, -1114, -1282, -1438, -1527, +-1612, -1697, -1804, -1914, -2040, -2190, -2310, -2392, -2425, -2468, -2507, -2547, +-2593, -2616, -2609, -2571, -2527, -2477, -2428, -2417, -2429, -2416, -2364, -2267, +-2142, -1995, -1807, -1600, -1384, -1115, -795, -459, -119, 222, 550, 853, + 1129, 1418, 1726, 2008, 2263, 2509, 2744, 2955, 3153, 3364, 3582, 3762, + 3884, 3975, 4043, 4079, 4069, 4030, 3962, 3827, 3633, 3409, 3197, 2987, + 2779, 2560, 2337, 2091, 1830, 1564, 1314, 1112, 922, 722, 518, 328, + 137, -4, -102, -140, -156, -186, -233, -324, -442, -576, -735, -948, +-1192, -1491, -1838, -2227, -2608, -2987, -3355, -3679, -3995, -4297, -4577, -4846, +-5092, -5284, -5423, -5490, -5476, -5394, -5240, -5040, -4753, -4386, -3959, -3467, +-2971, -2478, -2031, -1608, -1219, -869, -532, -193, 102, 351, 619, 915, + 1173, 1400, 1649, 1921, 2164, 2374, 2620, 2897, 3156, 3404, 3673, 3961, + 4216, 4455, 4718, 5030, 5316, 5549, 5803, 6053, 6218, 6293, 6320, 6267, + 6124, 5854, 5491, 5039, 4502, 3895, 3241, 2582, 1900, 1177, 387, -434, +-1258, -2051, -2786, -3451, -4002, -4473, -4885, -5171, -5306, -5302, -5195, -4987, +-4727, -4464, -4215, -3965, -3699, -3452, -3242, -2999, -2739, -2589, -2545, -2508, +-2479, -2466, -2477, -2479, -2553, -2701, -2876, -3069, -3229, -3267, -3142, -3023, +-2904, -2701, -2408, -2078, -1699, -1199, -674, -197, 283, 792, 1288, 1793, + 2363, 2929, 3392, 3814, 4262, 4673, 5000, 5327, 5714, 6052, 6273, 6472, + 6681, 6820, 6883, 6952, 7001, 6946, 6836, 6688, 6512, 6340, 6273, 6373, + 6477, 6456, 6345, 6130, 5819, 5412, 4903, 4154, 3095, 1619, -422, -2967, +-5332, -7146, -8759, -10624, -12578, -14126, -15457, -16774, -17585, -17429, -16696, -15883, +-14865, -13205, -10816, -7765, -4193, -514, 2918, 5934, 8325, 9855, 10774, 11443, +11594, 10909, 9449, 7686, 5572, 3109, 727, -1532, -3898, -6361, -8588, -10424, +-11873, -12688, -12576, -11741, -10492, -8732, -6366, -3666, -971, 1811, 4593, 7048, + 9079, 10782, 12173, 13154, 13825, 14248, 14215, 13623, 12593, 11156, 9141, 6630, + 4033, 1503, -1006, -3341, -5167, -6417, -7147, -7242, -6784, -5890, -4719, -3310, +-1902, -552, 909, 2536, 4155, 5639, 6995, 8105, 8745, 8865, 8521, 7699, + 6308, 4303, 1901, -816, -3625, -6226, -8397, -10012, -11192, -11930, -12134, -12016, +-11615, -10858, -9811, -8635, -7206, -5500, -3818, -2231, -553, 1196, 2641, 3572, + 4128, 4310, 3973, 3221, 2145, 841, -394, -1302, -2045, -2834, -3442, -3735, +-3910, -4131, -3985, -3354, -2581, -1708, -540, 992, 2664, 4383, 5952, 7016, + 7559, 7710, 7362, 6533, 5502, 4578, 3588, 2363, 1218, 397, -155, -557, + -790, -826, -630, -74, 872, 2276, 4067, 6060, 7851, 9089, 9716, 9906, + 9912, 9667, 8972, 7897, 6796, 5680, 4443, 3238, 1961, 203, -2327, -5758, +-10042, -14129, -16640, -17820, -19003, -20149, -19905, -18712, -17862, -16673, -14027, -10674, +-7929, -5557, -2630, 925, 4952, 9226, 12993, 15802, 17621, 18177, 16909, 14461, +11929, 9055, 5027, 367, -3755, -7409, -10971, -13810, -15525, -16664, -17358, -16975, +-15378, -13055, -9919, -5692, -924, 3522, 7796, 12179, 16035, 18746, 20434, 21359, +21013, 19196, 16561, 13482, 9772, 5501, 1211, -2930, -6953, -10361, -12716, -14259, +-15246, -15280, -14255, -12546, -10100, -6781, -2851, 1132, 5147, 9265, 13025, 16203, +18736, 20461, 20810, 19732, 17654, 14680, 10846, 6485, 2118, -2224, -6693, -10970, +-14609, -17470, -19580, -20868, -21312, -21005, -19853, -17727, -14745, -11039, -6421, -1119, + 3898, 8150, 11791, 14591, 15879, 15840, 15087, 13382, 10303, 6487, 3027, -249, +-3909, -7394, -10221, -12638, -14937, -16695, -17185, -16628, -15127, -12911, -10324, -7022, +-3043, 1078, 4575, 7482, 10172, 11923, 12422, 12357, 12421, 12148, 10812, 8825, + 6722, 4638, 2480, 654, -504, -1418, -2222, -2780, -2810, -2349, -1610, -416, + 938, 2100, 3169, 4442, 5998, 7452, 8930, 10465, 11522, 11552, 10802, 9873, + 8648, 7117, 5674, 4394, 3370, 2605, 1935, 822, -751, -2710, -6177, -11050, +-14738, -15996, -16935, -18986, -20355, -19576, -18381, -17682, -15449, -11544, -7986, -5650, +-3321, 313, 4861, 9740, 14019, 17052, 18809, 18977, 17236, 14015, 10887, 7897, + 3444, -2222, -7328, -11180, -14784, -18025, -19285, -19018, -18699, -17969, -15623, -11786, +-7563, -3020, 2288, 7195, 10895, 14162, 16973, 18433, 18218, 17124, 15380, 12373, + 8767, 5335, 1792, -1928, -5292, -8098, -10880, -12900, -13217, -12468, -11215, -9036, +-5317, -992, 3138, 7664, 12084, 15465, 17730, 19152, 19649, 19057, 17873, 16052, +13221, 9620, 5667, 1397, -3273, -7712, -11713, -15434, -18364, -20028, -20189, -19045, +-16752, -13399, -9619, -5824, -2033, 1582, 4560, 6690, 8055, 9057, 9728, 9439, + 8515, 7350, 5341, 2287, -893, -3359, -5716, -8385, -10454, -11543, -12476, -12953, +-11753, -9385, -6741, -4349, -2091, 70, 1758, 3347, 4141, 4043, 4132, 4206, + 4053, 3874, 4545, 5354, 4871, 3829, 3042, 2434, 1416, 395, 95, -45, + -141, 89, 1099, 2508, 3243, 3510, 3370, 2971, 2520, 2331, 2993, 3837, + 4476, 5287, 6330, 7326, 8310, 9637, 11004, 11816, 11794, 11004, 9460, 7612, + 6049, 4242, 2129, 449, -646, -2406, -5109, -7244, -8862, -12158, -17039, -19924, +-19406, -18417, -18741, -18752, -16848, -14506, -13175, -11043, -7499, -3996, -1619, 186, + 2915, 6596, 10674, 13913, 15536, 16050, 15491, 13227, 9304, 5916, 3646, 504, +-4226, -8472, -10949, -13542, -16620, -18234, -18057, -17417, -16586, -13903, -9002, -3348, + 2394, 8182, 13219, 16820, 19332, 20654, 20511, 19273, 17223, 14239, 10163, 5701, + 1377, -2843, -6645, -9629, -11770, -13414, -14134, -13644, -12183, -9506, -5600, -568, + 4964, 10343, 15294, 19251, 22077, 23660, 23683, 22212, 19625, 16179, 11855, 7111, + 2533, -1610, -5401, -8919, -12111, -15053, -17375, -18784, -19062, -18177, -16197, -13233, +-9991, -6602, -3344, -512, 2067, 4102, 5351, 5542, 5385, 5464, 4981, 4043, + 2744, 966, -1256, -3329, -4411, -5352, -6241, -6412, -6015, -5882, -6607, -6630, +-5818, -4866, -3840, -3286, -2623, -1973, -1774, -2006, -2539, -2101, -1258, -1034, + -969, -291, 1195, 2507, 3621, 4855, 5749, 6162, 5915, 5442, 4797, 4205, + 3973, 3665, 3239, 2587, 1761, 935, -38, -831, -950, -266, 741, 1619, + 2359, 3503, 5157, 6911, 8925, 11048, 12975, 14034, 13429, 11640, 9535, 7885, + 6274, 4098, 1823, 111, -1423, -3716, -5770, -6853, -8208, -11839, -16949, -19391, +-18575, -17362, -16808, -15680, -12701, -10005, -8624, -6425, -3286, -305, 1267, 2203, + 4179, 7213, 10944, 13750, 15091, 15220, 13766, 10148, 5000, 694, -2777, -6909, +-11043, -13586, -14676, -15862, -16695, -15762, -13907, -12568, -10682, -6994, -1982, 3001, + 7780, 12897, 17289, 19860, 20718, 20347, 18940, 15802, 11242, 6292, 1189, -3919, +-8915, -12955, -15578, -16909, -17404, -17164, -15619, -12875, -9303, -5340, -357, 6177, +12904, 18619, 23047, 26591, 28430, 27728, 25371, 21978, 17813, 12527, 6738, 1395, +-3509, -7885, -11473, -14258, -16454, -18149, -18891, -18623, -17369, -14863, -11378, -7474, +-3644, -253, 2319, 4100, 5643, 6532, 6179, 5207, 4488, 3730, 2059, 176, +-1328, -3177, -5806, -8076, -9102, -9613, -10033, -9841, -8340, -6056, -3637, -861, + 1704, 3778, 5341, 5954, 5726, 5084, 4773, 3910, 1941, 290, -719, -1981, +-3475, -4285, -4134, -4306, -4527, -3420, -1536, 395, 2422, 4650, 6508, 7649, + 8598, 9017, 8259, 6639, 4828, 3009, 818, -810, -1195, -1000, -1095, -1392, + -999, 261, 1814, 3964, 7134, 10656, 13946, 16135, 16585, 15596, 13684, 11585, + 8842, 5148, 1619, -1424, -4419, -7219, -8976, -9562, -9961, -10741, -12324, -15040, +-17809, -17768, -14861, -11769, -9149, -6558, -3863, -3033, -3411, -2580, -1339, -641, + -889, -1012, -238, 1657, 4674, 6964, 7839, 7786, 6797, 3766, -656, -3429, +-4378, -5405, -7049, -8251, -8486, -9137, -10352, -10855, -10604, -9639, -8349, -6997, +-5110, -2199, 1958, 6278, 9574, 12091, 13941, 14199, 12316, 9623, 7288, 5017, + 2148, -614, -2817, -4900, -6699, -7738, -7956, -7890, -7096, -5238, -2561, 796, + 5003, 10089, 14817, 18638, 20959, 21758, 21611, 20368, 18212, 15300, 12606, 9974, + 6635, 2670, -1285, -4876, -8777, -12560, -15318, -17001, -17701, -17579, -16413, -14346, +-11815, -9034, -6481, -4241, -2167, -308, 1379, 3034, 5008, 6816, 8193, 9015, + 8967, 8014, 5654, 2088, -2149, -5856, -8539, -10715, -12142, -12254, -10843, -9147, +-7589, -5591, -3664, -1941, -875, -254, 534, 1386, 2760, 3736, 4304, 4900, + 4358, 2802, 812, -741, -1804, -2945, -3313, -2151, 19, 2391, 4664, 6627, + 7981, 7704, 5912, 3689, 1498, -661, -2846, -4174, -4198, -3700, -2979, -2037, + -927, -14, 1037, 2972, 5372, 8569, 12879, 17325, 20387, 21419, 21016, 18619, +14135, 8955, 3909, -1077, -5667, -9076, -11465, -12834, -12676, -11358, -10369, -9845, +-9163, -9438, -11164, -11887, -8865, -3972, -322, 2061, 3262, 2732, -236, -3494, +-5099, -6219, -7450, -8643, -8885, -7600, -4814, -969, 2524, 4896, 6262, 6034, + 3920, 1370, 394, 471, -207, -1254, -2015, -3096, -5325, -7772, -9318, -10710, +-11666, -11688, -10937, -9048, -5091, 1114, 7105, 11457, 15087, 17610, 17611, 15423, +13002, 11066, 8417, 4757, 781, -3097, -6275, -8322, -9398, -9788, -9090, -7436, +-5658, -3717, -443, 4444, 9767, 14764, 19125, 22597, 24606, 25061, 24617, 23086, +20248, 16086, 10780, 4600, -1938, -7699, -12575, -16642, -19830, -21865, -22772, -23283, +-23030, -21438, -18736, -15010, -10587, -6015, -1624, 2208, 5917, 9310, 11894, 13881, +15026, 14599, 12032, 8267, 4195, -305, -5197, -9737, -12788, -15011, -17283, -18731, +-18700, -17149, -15187, -13209, -10483, -7044, -3126, 480, 3515, 6804, 10275, 12913, +13510, 12732, 11453, 8704, 4803, 1323, -336, -1092, -1988, -1831, -680, 781, + 2149, 3544, 4102, 3225, 2244, 1404, 456, -132, 188, 1296, 2001, 2185, + 2459, 2554, 2764, 3460, 4522, 5746, 7761, 10626, 13470, 15620, 16883, 17134, +15467, 11529, 6397, 1048, -4010, -8386, -11502, -12650, -12227, -11272, -9845, -7503, +-4597, -2154, -446, 1215, 3397, 4855, 4544, 3909, 4849, 6643, 6266, 2709, +-2514, -8098, -14616, -21106, -24703, -25243, -24232, -23122, -21104, -17261, -12231, -6587, +-1162, 3921, 8079, 10606, 11262, 11241, 12352, 13681, 13656, 12190, 9595, 5448, + -692, -7199, -12202, -15952, -18423, -19070, -17827, -15183, -11576, -6818, -1444, 3694, + 7806, 10572, 12276, 12895, 12847, 12781, 13035, 13312, 12989, 12073, 10697, 8710, + 6529, 4204, 1508, -817, -2272, -2744, -2424, -700, 2720, 6444, 9470, 11430, +12575, 12557, 11657, 10634, 9043, 7266, 5495, 3452, 767, -2414, -4940, -7000, +-9018, -10897, -12409, -13522, -14249, -14140, -13183, -11331, -8549, -5741, -3730, -2516, +-1531, -230, 1105, 2574, 4038, 5004, 4974, 4232, 3068, 1328, -576, -2414, +-3731, -5275, -7438, -9144, -9981, -9775, -9258, -8720, -7923, -7051, -5594, -3923, +-2244, -322, 1822, 4041, 5033, 5169, 5569, 5792, 5534, 5118, 5483, 6564, + 7140, 7417, 7380, 7126, 6891, 6229, 5044, 3360, 1969, 878, -514, -1665, +-2089, -1656, -849, -105, 1112, 2846, 4923, 6963, 8526, 10081, 11654, 12639, +12724, 12011, 10984, 9220, 6019, 1527, -3449, -7806, -11264, -13730, -14808, -13993, +-11467, -8552, -5590, -2003, 2141, 5907, 8234, 9471, 10407, 10583, 9143, 6180, + 3778, 2638, 576, -3435, -8759, -13848, -18835, -23767, -26459, -26548, -24792, -22172, +-18691, -14332, -9710, -4218, 1740, 6950, 10835, 13690, 15447, 15826, 15728, 15893, +15740, 14450, 11763, 7294, 1003, -5632, -11087, -15203, -17930, -18652, -17648, -16147, +-14272, -11004, -6299, -1287, 3363, 7594, 11069, 13625, 15624, 17814, 20431, 22822, +24056, 23502, 21240, 17606, 12908, 7922, 3406, -200, -3203, -5799, -7776, -8723, +-8515, -7635, -6359, -4839, -3281, -1938, -750, 808, 2772, 4952, 7026, 8506, + 8865, 8173, 7109, 5597, 3474, 1095, -1172, -3701, -6615, -9417, -11976, -14055, +-15453, -16222, -17004, -18045, -18178, -17030, -15048, -12288, -8616, -4233, -214, 2927, + 5463, 7401, 8639, 9383, 9965, 10102, 9074, 7357, 5377, 3233, 568, -2521, +-5175, -7859, -10740, -13289, -14978, -14848, -13081, -10301, -7491, -5076, -2233, 611, + 3240, 6092, 9632, 13675, 16529, 18240, 19396, 19866, 19719, 18213, 15584, 12042, + 7843, 3975, 51, -3323, -5200, -6019, -6273, -6590, -6269, -5224, -3859, -1940, + 113, 2252, 4533, 6783, 8493, 9244, 9843, 10278, 9228, 6612, 3279, 168, +-2860, -5614, -6836, -6459, -5070, -3413, -1993, -631, 478, 1270, 1602, 1496, + 1461, 1071, -327, -2772, -5091, -6033, -6641, -8239, -10915, -13747, -15893, -17655, +-17929, -15732, -12088, -8454, -5526, -2840, -1038, -164, 1315, 3100, 4146, 3883, + 3496, 3488, 2400, 1311, 1549, 2208, 1881, 109, -2041, -4405, -6334, -6358, +-4799, -2376, 511, 3333, 5204, 5770, 6444, 7705, 8673, 9069, 9206, 9035, + 7995, 6598, 6026, 5975, 5550, 4851, 4274, 3603, 2294, 1217, 1390, 2430, + 3516, 4646, 5989, 6777, 7114, 7333, 7398, 7197, 6420, 5592, 4107, 2026, + 646, -219, -1204, -2798, -4532, -6398, -9003, -11447, -12978, -13622, -13801, -13379, +-12112, -11096, -10184, -8676, -6741, -4776, -3299, -2025, -1041, -231, 1117, 2586, + 3727, 4474, 4966, 4646, 2944, 715, -1309, -3116, -4923, -6456, -7366, -7955, +-8162, -8046, -7903, -8026, -8220, -8167, -7962, -7097, -5237, -2282, 1169, 4484, + 7793, 10342, 11751, 12505, 13099, 14088, 14866, 15384, 15745, 15392, 14492, 12913, +11094, 8933, 5992, 2709, -659, -3687, -6048, -7294, -7299, -6511, -5249, -3964, +-2735, -1618, -291, 1383, 3030, 4553, 5998, 7461, 8476, 8632, 8287, 7686, + 6474, 4304, 1459, -1572, -4498, -6894, -8245, -8467, -7896, -6770, -5457, -4602, +-4395, -4154, -3708, -3426, -3183, -2712, -2058, -1811, -2307, -3164, -4244, -5243, +-6139, -7279, -8223, -8511, -7853, -6686, -5475, -4022, -3055, -2968, -3736, -5080, +-6435, -7498, -7593, -7315, -7295, -7142, -6745, -6296, -6210, -5538, -3815, -1920, + -190, 1644, 3867, 6164, 8718, 11934, 15034, 17044, 18168, 18704, 18157, 16538, +14998, 13921, 12471, 10185, 7531, 4681, 1387, -1735, -3908, -5421, -6522, -6966, +-7028, -7044, -6665, -5021, -2489, -259, 1967, 4366, 6137, 6885, 7324, 8468, + 9620, 9999, 9933, 9524, 8739, 7331, 5786, 4320, 2570, 465, -2420, -5696, +-8953, -11749, -13512, -14723, -15167, -15020, -14775, -14541, -14348, -13533, -12292, -10918, +-9278, -7384, -5177, -2823, -369, 2074, 4128, 5627, 6236, 5953, 5092, 4054, + 2879, 1549, 465, -369, -1168, -2031, -2797, -3275, -3618, -4022, -4373, -4375, +-3875, -2790, -1112, 1245, 4058, 6588, 8310, 9237, 9776, 10148, 10412, 10652, +10899, 11107, 10785, 9778, 8409, 7186, 6260, 5068, 3894, 2923, 2007, 1308, + 872, 1354, 2304, 2951, 3185, 2913, 2312, 1260, -43, -994, -1635, -2171, +-3067, -4503, -6161, -7540, -8047, -8147, -7984, -7228, -6043, -5074, -4652, -3817, +-2103, -104, 1826, 3466, 4573, 4788, 4420, 3790, 2730, 1491, 295, -1070, +-3126, -5653, -7915, -9875, -11366, -12078, -11926, -11172, -10154, -8711, -7010, -5200, +-3104, -957, 698, 1836, 3030, 4351, 5200, 5683, 6227, 6486, 5893, 4614, + 3506, 2869, 2460, 2294, 2253, 1849, 1109, 190, -742, -1478, -1581, -1120, + -938, -901, -645, -145, 512, 1554, 3370, 5228, 6673, 7969, 9038, 9935, +11009, 12741, 14420, 15240, 15367, 14816, 13342, 10725, 7621, 4586, 1552, -1604, +-4901, -7871, -10063, -11193, -11529, -11428, -10675, -9491, -8338, -7373, -6003, -3752, +-1335, 670, 2173, 3083, 3097, 2089, 672, -951, -2815, -4770, -6927, -9146, +-11001, -11985, -12253, -12297, -11869, -10866, -9722, -8653, -7243, -5274, -3148, -1121, + 644, 1894, 2664, 3134, 3242, 2799, 2171, 1877, 1709, 1278, 923, 1184, + 1821, 2247, 2400, 2790, 3369, 3836, 4233, 4837, 5653, 6384, 6940, 7307, + 7608, 7942, 8198, 8125, 7694, 7125, 6279, 4697, 2823, 1402, 478, -257, + -683, -435, 164, 560, 691, 798, 1140, 1720, 2481, 3310, 4235, 5256, + 5724, 5297, 4421, 3328, 1810, -509, -3073, -5243, -7071, -8670, -9939, -10435, +-10083, -9245, -8370, -7573, -6360, -4775, -3332, -2044, -466, 1458, 3122, 4030, + 4383, 4372, 4009, 3205, 1770, -322, -2740, -5246, -7777, -10093, -11408, -11528, +-11170, -10765, -10024, -8663, -7090, -5489, -3530, -1155, 1369, 3557, 5384, 6900, + 8181, 9225, 9554, 9128, 8300, 7409, 6258, 4747, 3431, 2299, 877, -943, +-2890, -4507, -5767, -6318, -6025, -5201, -3723, -1802, 346, 2462, 4551, 6802, + 8667, 10001, 11045, 12045, 13053, 13889, 14620, 14801, 13867, 11904, 8956, 5366, + 1658, -1501, -3815, -5665, -7082, -7814, -7953, -7826, -7314, -6109, -4568, -3246, +-2069, -884, 188, 1071, 1747, 2078, 1722, 615, -1188, -3678, -6222, -8369, +-10234, -11837, -12859, -13053, -12815, -12298, -11053, -9225, -7205, -5170, -2968, -621, + 1728, 4364, 6894, 8866, 10205, 10603, 9878, 7983, 5676, 3466, 1165, -868, +-2495, -3780, -4757, -5414, -5487, -5226, -4398, -2940, -1337, 185, 1640, 3412, + 5343, 7114, 8954, 10589, 11752, 12005, 11336, 10209, 8658, 7016, 5358, 3659, + 2001, 340, -1117, -2494, -3765, -4622, -5363, -6001, -6472, -6349, -5366, -3794, +-1413, 1504, 4275, 6447, 7708, 8074, 7614, 6611, 5355, 3599, 1601, -371, +-2294, -4188, -6028, -7296, -8343, -9618, -10835, -11873, -12465, -12383, -11288, -9200, +-6603, -3624, -782, 1483, 3214, 4548, 5507, 5733, 5519, 5052, 4141, 2919, + 1709, 878, 47, -1150, -2610, -4172, -5647, -6887, -7501, -7164, -5980, -4210, +-2260, -396, 1334, 2959, 4403, 5535, 6292, 6774, 6878, 6554, 6068, 5718, + 5431, 4770, 3464, 1562, -769, -3109, -4938, -5913, -5818, -4861, -3342, -1624, + 264, 2483, 4847, 7109, 8973, 10330, 11073, 11209, 11170, 11177, 11137, 10850, + 9867, 8034, 5232, 1868, -1597, -4763, -7279, -9080, -10039, -10301, -10002, -9221, +-8118, -6535, -4664, -2950, -1533, -373, 670, 1508, 2096, 2358, 2033, 1098, + -490, -2681, -5116, -7414, -9316, -10845, -11934, -12410, -12510, -12352, -11788, -10510, +-8661, -6444, -3785, -927, 1929, 4662, 7243, 9475, 11053, 11863, 11721, 10438, + 8209, 5705, 3299, 1170, -342, -1356, -2224, -3225, -4227, -4894, -5202, -4940, +-3986, -2617, -1158, 242, 1875, 3701, 5533, 7304, 8766, 9683, 9845, 9403, + 8617, 7779, 7281, 6831, 5983, 4748, 3300, 1636, -391, -2300, -3520, -4338, +-4993, -5346, -5131, -4386, -3288, -1707, -16, 1324, 2247, 2781, 2987, 3037, + 3105, 2918, 2306, 1386, 48, -1745, -3793, -5460, -6709, -8077, -9311, -9863, +-9718, -9046, -7774, -5649, -3242, -1051, 853, 2330, 3435, 4236, 4902, 5320, + 5231, 4838, 4154, 3102, 1875, 683, -356, -1565, -2854, -3920, -4848, -5537, +-5779, -5387, -4586, -3731, -2709, -1457, -257, 830, 1998, 3193, 4164, 4815, + 5191, 5345, 5325, 5274, 5240, 4973, 4341, 3310, 1857, 292, -972, -1748, +-2068, -1955, -1415, -728, -169, 468, 1409, 2430, 3268, 3883, 4376, 4713, + 4849, 4890, 4973, 5093, 5056, 4546, 3303, 1583, -202, -1941, -3546, -4724, +-5351, -5718, -6144, -6625, -6946, -6959, -6553, -5622, -4318, -2968, -1592, -322, + 665, 1412, 1966, 2207, 1773, 702, -534, -1822, -3125, -4204, -4907, -5406, +-6207, -7247, -8204, -8794, -8764, -8054, -6661, -4674, -2365, -52, 2038, 4018, + 5984, 7575, 8471, 8719, 8575, 8137, 7567, 7169, 7197, 7405, 7164, 6198, + 4638, 2763, 894, -738, -1755, -2125, -2204, -2216, -2160, -1776, -1028, -14, + 1072, 1942, 2512, 2784, 2850, 3017, 3549, 4508, 5431, 5815, 5532, 4424, + 2573, 404, -1505, -2953, -4080, -4710, -4737, -4451, -3982, -3117, -1819, -553, + 289, 723, 981, 1174, 1282, 1338, 1390, 1334, 994, 86, -1348, -2946, +-4489, -6116, -7766, -8957, -9465, -9470, -9066, -8015, -6261, -4328, -2550, -1012, + 286, 1250, 1830, 2335, 2879, 3353, 3660, 3628, 3286, 2667, 1814, 864, + -184, -1191, -2141, -2853, -3096, -2845, -1966, -641, 809, 2043, 2828, 3304, + 3534, 3630, 3781, 4023, 4185, 4071, 3760, 3284, 2529, 1635, 739, -182, +-1251, -2355, -3076, -3331, -3020, -2074, -688, 954, 2507, 3798, 4619, 5016, + 5414, 5801, 6040, 6169, 6398, 6680, 6592, 6158, 5580, 4832, 3650, 1807, + -316, -2461, -4480, -6189, -7395, -7933, -7963, -7735, -7550, -7425, -7185, -6734, +-6036, -5178, -4133, -2808, -1585, -565, 320, 1079, 1601, 1559, 1146, 517, + -291, -1116, -1774, -2137, -2420, -2774, -3136, -3568, -3914, -3990, -3758, -3343, +-2819, -1984, -962, 107, 1232, 2311, 3194, 3799, 4165, 4264, 4188, 4280, + 4523, 4616, 4499, 4321, 4046, 3463, 2811, 2299, 1937, 1707, 1506, 1361, + 1335, 1638, 2239, 2759, 3234, 3731, 3921, 3546, 2916, 2615, 2546, 2426, + 2300, 2151, 1633, 613, -751, -2134, -3271, -3997, -4405, -4700, -4716, -4215, +-3339, -2250, -996, 407, 1565, 2067, 2078, 1950, 1817, 1666, 1394, 931, + 152, -984, -2436, -4106, -5748, -7125, -8060, -8595, -8762, -8451, -7594, -6291, +-4716, -2984, -1152, 647, 2194, 3385, 4312, 5109, 5728, 6003, 5853, 5346, + 4388, 3021, 1397, -222, -1549, -2559, -3290, -3793, -3912, -3492, -2615, -1450, + -54, 1487, 2827, 3831, 4651, 5383, 5996, 6473, 6778, 6611, 5826, 4668, + 3279, 1770, 321, -768, -1484, -2032, -2449, -2682, -2733, -2601, -2273, -1785, +-1235, -633, 34, 677, 1290, 1951, 2733, 3518, 3997, 4105, 3941, 3505, + 2802, 1885, 970, 56, -985, -2012, -2942, -3775, -4360, -4590, -4631, -4718, +-4730, -4593, -4506, -4460, -4065, -3201, -2261, -1391, -553, 43, 308, 238, + -45, -513, -1136, -1707, -2338, -2951, -3362, -3587, -3681, -3889, -4094, -4192, +-4183, -3835, -3151, -2048, -688, 768, 2223, 3399, 4406, 5177, 5657, 5954, + 5974, 5887, 5719, 5494, 5229, 4754, 4119, 3246, 2082, 740, -499, -1312, +-1777, -1876, -1555, -879, 54, 1065, 2222, 3490, 4632, 5523, 6023, 6125, + 5905, 5607, 5310, 4775, 3924, 2871, 1499, -256, -2267, -4128, -5651, -6893, +-7742, -8204, -8325, -8025, -7293, -6255, -5049, -3623, -2003, -576, 654, 1876, + 3133, 4155, 4665, 4757, 4411, 3574, 2310, 783, -809, -2356, -3735, -4939, +-5950, -6620, -6909, -6891, -6684, -6291, -5613, -4682, -3598, -2365, -1004, 372, + 1611, 2588, 3271, 3682, 3914, 3977, 3771, 3304, 2798, 2326, 1854, 1406, + 1197, 1271, 1456, 1561, 1664, 1808, 1825, 1705, 1545, 1480, 1454, 1394, + 1381, 1384, 1327, 1202, 960, 652, 391, 288, 302, 388, 686, 1127, + 1463, 1574, 1631, 1721, 1627, 1368, 1047, 639, 192, -251, -567, -765, + -886, -895, -942, -1082, -1145, -1096, -935, -724, -435, -47, 288, 581, + 780, 910, 964, 858, 530, -17, -681, -1359, -2068, -2732, -3260, -3613, +-3994, -4546, -5082, -5450, -5507, -5281, -4777, -3947, -2994, -2071, -1237, -489, + 340, 1160, 1808, 2187, 2388, 2587, 2679, 2777, 2943, 3099, 3055, 2661, + 2083, 1458, 939, 667, 598, 775, 1089, 1480, 1873, 2080, 2208, 2212, + 2043, 1745, 1366, 1189, 1327, 1663, 2041, 2229, 2236, 2090, 1747, 1385, + 1137, 1093, 1109, 1034, 919, 846, 833, 742, 550, 355, 78, -311, + -798, -1252, -1555, -1760, -1893, -2089, -2396, -2765, -3224, -3764, -4265, -4576, +-4617, -4488, -4240, -3907, -3523, -3112, -2735, -2382, -2011, -1597, -1135, -769, + -453, -115, 313, 760, 1032, 1182, 1195, 1075, 844, 552, 451, 498, + 552, 530, 402, 223, 5, -116, -113, 25, 333, 695, 962, 1089, + 1242, 1521, 1815, 2161, 2547, 2838, 2965, 2908, 2802, 2643, 2421, 2268, + 2057, 1749, 1389, 1025, 708, 422, 232, 52, -239, -528, -689, -617, + -288, 223, 787, 1204, 1399, 1377, 1193, 971, 776, 554, 200, -305, + -870, -1470, -2031, -2520, -2946, -3204, -3354, -3414, -3299, -2887, -2196, -1421, + -622, 117, 646, 976, 1135, 1110, 858, 446, -19, -656, -1418, -2179, +-2944, -3715, -4407, -4919, -5272, -5372, -4977, -4145, -3018, -1591, 78, 1694, + 2982, 3996, 4676, 4948, 4883, 4598, 4177, 3579, 2904, 2150, 1241, 273, + -613, -1453, -2240, -2916, -3334, -3526, -3504, -3094, -2214, -974, 461, 1925, + 3348, 4553, 5377, 5846, 6044, 6026, 5765, 5336, 4789, 4208, 3498, 2569, + 1376, 28, -1287, -2432, -3320, -3784, -3782, -3476, -3130, -2782, -2321, -1753, +-1159, -534, 69, 551, 848, 1017, 1104, 1092, 958, 739, 449, -65, + -824, -1710, -2563, -3315, -3963, -4396, -4544, -4479, -4255, -3928, -3489, -2912, +-2180, -1393, -699, -92, 559, 1195, 1681, 2100, 2574, 3019, 3248, 3238, + 3094, 2865, 2569, 2251, 1894, 1532, 1141, 663, 72, -517, -887, -1088, +-1157, -1048, -802, -518, -337, -146, 169, 551, 929, 1258, 1593, 1916, + 2137, 2281, 2389, 2516, 2544, 2324, 1943, 1480, 947, 368, -211, -702, +-1091, -1400, -1620, -1734, -1724, -1619, -1481, -1250, -950, -679, -509, -329, + -85, 139, 220, 255, 319, 319, 207, 14, -244, -582, -934, -1353, +-1754, -2031, -2111, -2082, -2035, -1880, -1646, -1509, -1491, -1516, -1569, -1649, +-1635, -1474, -1210, -884, -536, -231, 6, 177, 323, 422, 548, 725, + 852, 950, 1131, 1393, 1601, 1696, 1721, 1634, 1332, 964, 626, 352, + 164, 68, 19, -6, 107, 365, 600, 826, 1097, 1332, 1388, 1368, + 1472, 1669, 1874, 2124, 2404, 2627, 2616, 2384, 1975, 1445, 930, 460, + 32, -264, -389, -401, -459, -622, -764, -890, -991, -1091, -1102, -949, + -684, -395, -132, 50, 135, 46, -292, -833, -1422, -1925, -2265, -2480, +-2560, -2483, -2281, -2044, -1882, -1850, -1884, -1932, -2055, -2240, -2291, -2067, +-1646, -1230, -831, -391, -17, 131, 102, 71, 130, 183, 184, 298, + 654, 1164, 1598, 1912, 2216, 2508, 2594, 2515, 2461, 2545, 2602, 2489, + 2279, 2073, 1828, 1434, 922, 428, 27, -385, -919, -1385, -1635, -1636, +-1512, -1315, -966, -490, 11, 514, 1055, 1686, 2397, 3057, 3509, 3681, + 3552, 3140, 2437, 1502, 491, -456, -1385, -2313, -3190, -3912, -4434, -4759, +-4839, -4665, -4266, -3698, -2976, -2173, -1295, -332, 700, 1636, 2371, 2867, + 3059, 2884, 2379, 1677, 900, 105, -649, -1281, -1764, -2100, -2273, -2309, +-2231, -2070, -1811, -1514, -1206, -805, -270, 398, 1105, 1804, 2418, 2840, + 2992, 2852, 2463, 1926, 1343, 800, 338, 43, -111, -204, -314, -483, + -748, -1120, -1512, -1809, -1959, -2005, -1911, -1591, -1121, -632, -167, 322, + 777, 1064, 1122, 1088, 1095, 1143, 1118, 1032, 984, 911, 682, 274, + -133, -379, -532, -622, -489, -41, 635, 1312, 1917, 2456, 2872, 3084, + 3106, 3052, 2986, 2890, 2648, 2201, 1575, 777, -207, -1326, -2495, -3576, +-4526, -5257, -5690, -5782, -5567, -5089, -4442, -3745, -3096, -2432, -1755, -1141, + -533, 82, 688, 1217, 1648, 1961, 2084, 1994, 1718, 1337, 906, 589, + 409, 299, 262, 361, 543, 717, 915, 1216, 1561, 1819, 1948, 1990, + 2006, 1936, 1752, 1477, 1199, 929, 597, 186, -210, -424, -483, -464, + -394, -210, 115, 455, 732, 984, 1319, 1682, 1973, 2227, 2509, 2812, + 2966, 2922, 2699, 2309, 1718, 894, -32, -890, -1598, -2149, -2520, -2695, +-2719, -2668, -2602, -2476, -2322, -2111, -1826, -1517, -1211, -948, -646, -312, + 54, 437, 769, 935, 874, 610, 216, -240, -618, -832, -900, -835, + -636, -408, -333, -493, -771, -1129, -1595, -2184, -2808, -3427, -4054, -4579, +-4985, -5259, -5365, -5311, -5158, -5017, -4849, -4475, -3796, -2833, -1583, 14, + 1805, 3484, 4827, 5828, 6531, 6861, 6884, 6742, 6539, 6289, 5931, 5479, + 4960, 4509, 4119, 3660, 3060, 2378, 1728, 1064, 382, -137, -471, -746, +-1043, -1326, -1579, -1897, -2254, -2579, -2855, -3103, -3302, -3334, -3138, -2722, +-2090, -1276, -400, 419, 1106, 1666, 2141, 2534, 2866, 3148, 3354, 3463, + 3450, 3289, 2950, 2509, 1988, 1355, 654, -23, -610, -1155, -1644, -1996, +-2260, -2539, -2833, -3093, -3323, -3573, -3786, -3827, -3728, -3476, -3102, -2684, +-2303, -1960, -1624, -1254, -818, -350, 109, 445, 667, 816, 880, 897, + 913, 958, 979, 927, 819, 703, 650, 602, 576, 627, 710, 796, + 916, 1108, 1344, 1601, 1883, 2162, 2378, 2538, 2627, 2613, 2539, 2426, + 2254, 2057, 1838, 1639, 1399, 1080, 777, 460, 82, -374, -801, -1215, +-1601, -1905, -2044, -2018, -1898, -1782, -1702, -1611, -1474, -1284, -1129, -968, + -751, -577, -506, -455, -291, -97, 44, 131, 201, 213, 162, 129, + 195, 408, 741, 1163, 1546, 1857, 2026, 1995, 1767, 1379, 860, 146, + -842, -1988, -3173, -4318, -5391, -6303, -7021, -7590, -7977, -8105, -7956, -7559, +-6909, -5890, -4540, -2975, -1277, 539, 2375, 4018, 5397, 6428, 7132, 7541, + 7701, 7620, 7332, 6943, 6542, 6104, 5650, 5262, 4893, 4471, 3928, 3358, + 2810, 2276, 1749, 1241, 702, 46, -766, -1785, -2995, -4340, -5605, -6661, +-7442, -7903, -7948, -7572, -6934, -6080, -5048, -3910, -2634, -1298, -20, 1168, + 2235, 3189, 3958, 4539, 4965, 5196, 5198, 4904, 4369, 3666, 2888, 2199, + 1662, 1308, 1096, 969, 827, 562, 220, -169, -607, -1084, -1626, -2181, +-2663, -3122, -3542, -3929, -4258, -4550, -4836, -5034, -5034, -4769, -4237, -3426, +-2349, -1087, 243, 1583, 2821, 3967, 4995, 5807, 6343, 6589, 6668, 6554, + 6181, 5602, 4904, 4069, 3104, 2049, 1025, 134, -617, -1242, -1718, -2044, +-2236, -2297, -2245, -2048, -1738, -1316, -879, -391, 184, 852, 1506, 2103, + 2607, 2913, 2937, 2700, 2372, 2004, 1630, 1165, 571, -114, -916, -1717, +-2424, -2967, -3337, -3596, -3725, -3721, -3546, -3129, -2446, -1551, -520, 489, + 1319, 1934, 2276, 2406, 2371, 2195, 1933, 1572, 1118, 652, 255, -22, + -244, -451, -677, -917, -1250, -1702, -2139, -2462, -2643, -2845, -3241, -3798, +-4411, -4979, -5549, -6131, -6624, -6943, -7060, -6954, -6525, -5636, -4396, -2995, +-1509, -20, 1390, 2771, 4117, 5461, 6726, 7816, 8687, 9228, 9450, 9417, + 9175, 8745, 8095, 7255, 6303, 5324, 4366, 3420, 2509, 1706, 1034, 330, + -556, -1543, -2511, -3437, -4303, -5054, -5656, -6109, -6441, -6631, -6594, -6297, +-5678, -4788, -3682, -2423, -1148, 97, 1271, 2417, 3514, 4502, 5316, 5854, + 6037, 5923, 5616, 5226, 4730, 4116, 3434, 2694, 1912, 1113, 310, -429, +-1134, -1890, -2731, -3575, -4343, -5041, -5637, -6152, -6614, -7071, -7506, -7761, +-7687, -7212, -6390, -5301, -3989, -2531, -953, 713, 2472, 4293, 6051, 7580, + 8671, 9270, 9453, 9248, 8735, 7910, 6798, 5372, 3679, 1930, 320, -1005, +-2072, -2906, -3574, -4076, -4358, -4330, -4023, -3527, -2903, -2243, -1606, -1064, + -540, -26, 439, 836, 1172, 1432, 1592, 1707, 1825, 1948, 2096, 2228, + 2244, 2166, 1970, 1677, 1317, 924, 537, 170, -243, -676, -1064, -1352, +-1513, -1512, -1318, -1062, -824, -626, -483, -401, -363, -392, -505, -740, + -966, -1177, -1368, -1459, -1412, -1206, -874, -408, 271, 1023, 1788, 2579, + 3334, 4003, 4439, 4597, 4443, 3981, 3296, 2349, 1040, -687, -2684, -4735, +-6773, -8557, -9891, -10790, -11329, -11502, -11150, -10307, -9086, -7491, -5575, -3413, +-1082, 1261, 3417, 5386, 7160, 8623, 9721, 10338, 10441, 10085, 9286, 8292, + 7236, 6158, 5126, 4146, 3250, 2334, 1411, 582, -142, -834, -1530, -2186, +-2826, -3489, -4180, -4819, -5347, -5701, -5901, -6053, -6064, -5891, -5553, -5004, +-4199, -3058, -1750, -369, 939, 2158, 3287, 4264, 5059, 5614, 5897, 5926, + 5743, 5334, 4737, 3984, 3171, 2283, 1308, 264, -851, -1934, -2962, -3938, +-4748, -5356, -5764, -6000, -6112, -5986, -5688, -5314, -4966, -4553, -3948, -3135, +-2238, -1230, -187, 880, 1964, 3022, 4049, 4977, 5768, 6415, 6865, 7118, + 7079, 6789, 6261, 5648, 4995, 4196, 3319, 2409, 1467, 499, -408, -1240, +-2015, -2695, -3196, -3542, -3784, -3948, -4086, -4130, -4030, -3781, -3420, -2935, +-2253, -1317, -265, 861, 2042, 3171, 4200, 5050, 5726, 6157, 6227, 5907, + 5155, 4067, 2713, 1168, -492, -2143, -3605, -4820, -5767, -6345, -6523, -6293, +-5741, -4945, -3907, -2802, -1758, -757, 170, 934, 1535, 1944, 2159, 2077, + 1766, 1345, 897, 566, 383, 427, 713, 1281, 2053, 2936, 3895, 4879, + 5765, 6414, 6753, 6799, 6462, 5651, 4379, 2811, 1092, -795, -2825, -4970, +-7257, -9503, -11488, -13035, -13960, -14282, -14106, -13487, -12396, -10852, -8944, -6850, +-4602, -2302, -27, 2095, 4052, 5797, 7313, 8605, 9687, 10587, 11205, 11438, +11297, 10868, 10249, 9562, 8764, 7831, 6741, 5552, 4238, 2781, 1249, -414, +-2185, -3989, -5674, -7155, -8403, -9394, -10014, -10287, -10289, -9953, -9288, -8314, +-7060, -5556, -3887, -2173, -431, 1204, 2693, 4085, 5355, 6418, 7154, 7583, + 7736, 7660, 7404, 7033, 6588, 6049, 5356, 4469, 3337, 2039, 660, -740, +-2133, -3461, -4708, -5760, -6601, -7180, -7419, -7360, -6965, -6316, -5489, -4568, +-3535, -2390, -1236, -108, 914, 1855, 2703, 3418, 4027, 4464, 4680, 4646, + 4400, 4072, 3709, 3339, 2955, 2497, 2072, 1677, 1262, 841, 489, 97, + -310, -711, -1175, -1664, -2165, -2497, -2656, -2709, -2678, -2588, -2404, -2132, +-1686, -1056, -247, 679, 1621, 2461, 3149, 3656, 3944, 4050, 3934, 3624, + 3054, 2153, 1019, -263, -1548, -2784, -3847, -4605, -5114, -5284, -5114, -4661, +-3890, -2847, -1582, -267, 977, 2022, 2726, 3003, 2933, 2670, 2262, 1747, + 1108, 452, -145, -525, -601, -338, 226, 981, 1818, 2660, 3467, 4129, + 4590, 4848, 4943, 4831, 4466, 3866, 3118, 2290, 1212, -153, -1655, -3128, +-4392, -5438, -6279, -7040, -7783, -8489, -9101, -9480, -9697, -9736, -9598, -9196, +-8408, -7246, -5851, -4284, -2576, -780, 1122, 3117, 5146, 6998, 8626, 9962, +11083, 11911, 12412, 12563, 12293, 11641, 10691, 9502, 8028, 6339, 4510, 2568, + 620, -1285, -3096, -4822, -6430, -7851, -8950, -9768, -10321, -10574, -10552, -10222, +-9593, -8616, -7359, -5924, -4395, -2726, -926, 984, 2881, 4661, 6304, 7803, + 9118, 10160, 10922, 11454, 11636, 11413, 10831, 9937, 8703, 7101, 5141, 2923, + 587, -1744, -4069, -6322, -8338, -9931, -11033, -11599, -11576, -11048, -10184, -9074, +-7772, -6359, -4946, -3632, -2399, -1291, -279, 604, 1388, 2140, 2982, 3877, + 4802, 5715, 6588, 7345, 7949, 8329, 8434, 8237, 7614, 6536, 5107, 3438, + 1591, -253, -1946, -3441, -4660, -5621, -6370, -6845, -7007, -6859, -6439, -5777, +-4960, -4119, -3301, -2528, -1727, -885, -92, 646, 1396, 2110, 2808, 3606, + 4375, 5092, 5586, 5743, 5615, 5174, 4457, 3544, 2492, 1392, 302, -758, +-1774, -2581, -3032, -3095, -2743, -2065, -1188, -347, 231, 591, 703, 616, + 356, 12, -383, -829, -1275, -1667, -1904, -2028, -1994, -1797, -1399, -811, + -103, 603, 1240, 1821, 2351, 2844, 3260, 3626, 3949, 4195, 4395, 4494, + 4323, 3756, 2751, 1466, 128, -1181, -2455, -3856, -5391, -7050, -8642, -10008, +-10989, -11546, -11765, -11577, -10913, -9726, -8147, -6381, -4511, -2546, -537, 1525, + 3542, 5482, 7282, 8920, 10391, 11733, 12829, 13539, 13659, 13176, 12305, 11136, + 9660, 7899, 5874, 3635, 1203, -1272, -3640, -5830, -7727, -9303, -10496, -11295, +-11670, -11695, -11384, -10826, -9954, -8780, -7251, -5392, -3319, -1090, 1198, 3471, + 5619, 7560, 9130, 10264, 10932, 11150, 10957, 10438, 9641, 8573, 7229, 5731, + 4162, 2555, 967, -609, -2100, -3446, -4679, -5795, -6861, -7745, -8498, -9130, +-9531, -9599, -9273, -8730, -8063, -7338, -6519, -5696, -4740, -3521, -1966, -102, + 1991, 4135, 6223, 8096, 9521, 10533, 11100, 11314, 11224, 10770, 9900, 8611, + 6898, 4781, 2413, -66, -2444, -4581, -6325, -7555, -8273, -8556, -8540, -8340, +-8055, -7723, -7287, -6643, -5754, -4577, -3115, -1387, 479, 2345, 4152, 5735, + 7050, 8089, 8795, 9246, 9437, 9355, 8947, 8132, 6944, 5372, 3582, 1740, + -20, -1536, -2821, -3898, -4775, -5396, -5780, -5928, -5757, -5251, -4486, -3609, +-2840, -2272, -1964, -1884, -2002, -2188, -2256, -2170, -1919, -1548, -1009, -364, + 299, 955, 1622, 2418, 3326, 4310, 5293, 6192, 6968, 7429, 7576, 7399, + 6986, 6429, 5788, 5144, 4395, 3364, 1966, 150, -1935, -4024, -5974, -7717, +-9281, -10691, -11951, -12976, -13640, -13940, -13958, -13696, -12972, -11669, -9805, -7456, +-4727, -1751, 1213, 4026, 6641, 8998, 10993, 12558, 13809, 14818, 15560, 15870, +15566, 14586, 12991, 10893, 8416, 5807, 3217, 727, -1614, -3797, -5630, -7159, +-8524, -9758, -10698, -11237, -11291, -10795, -9845, -8576, -7211, -5826, -4466, -3187, +-1926, -637, 763, 2260, 3832, 5290, 6433, 7124, 7387, 7305, 7036, 6809, + 6649, 6524, 6312, 5950, 5347, 4385, 3019, 1342, -494, -2385, -4187, -5707, +-6925, -7840, -8544, -9064, -9352, -9356, -9044, -8394, -7330, -5862, -4146, -2456, + -905, 489, 1660, 2644, 3540, 4527, 5663, 6862, 8001, 8877, 9363, 9357, + 8797, 7827, 6591, 5222, 3802, 2361, 903, -579, -2069, -3512, -4788, -5754, +-6333, -6452, -6111, -5462, -4648, -3859, -3154, -2547, -2021, -1460, -676, 379, + 1619, 3015, 4366, 5539, 6393, 6734, 6690, 6338, 5858, 5327, 4825, 4337, + 3716, 2818, 1616, 235, -1241, -2650, -3839, -4745, -5370, -5788, -6073, -6269, +-6437, -6499, -6349, -5927, -5312, -4516, -3604, -2721, -1919, -1186, -464, 204, + 874, 1546, 2273, 3106, 3994, 4864, 5630, 6240, 6653, 6858, 6848, 6716, + 6419, 5952, 5353, 4633, 3795, 2829, 1728, 545, -562, -1489, -2188, -2719, +-3256, -4010, -4975, -6056, -7137, -8145, -9060, -9732, -10071, -10065, -9698, -9050, +-8253, -7504, -6820, -6034, -4900, -3369, -1498, 592, 2781, 4897, 6752, 8228, + 9372, 10217, 10767, 11136, 11507, 11832, 11858, 11347, 10117, 8211, 5839, 3234, + 708, -1501, -3272, -4577, -5451, -5940, -6265, -6623, -6950, -7204, -7255, -6996, +-6370, -5546, -4643, -3779, -2966, -2264, -1579, -871, -40, 1022, 2312, 3798, + 5243, 6369, 7018, 7119, 6749, 6131, 5457, 4831, 4272, 3769, 3243, 2546, + 1600, 349, -1129, -2663, -4072, -5139, -5769, -6041, -5985, -5738, -5430, -5114, +-4762, -4255, -3623, -2836, -1885, -765, 379, 1416, 2248, 2846, 3274, 3596, + 3959, 4463, 5021, 5528, 5778, 5595, 4931, 3833, 2415, 844, -643, -1829, +-2720, -3282, -3621, -3794, -3929, -4030, -3990, -3800, -3342, -2615, -1649, -618, + 354, 1169, 1774, 2132, 2346, 2487, 2674, 2916, 3216, 3546, 3697, 3548, + 3039, 2288, 1445, 757, 319, 163, 137, 112, -48, -501, -1195, -2141, +-3259, -4372, -5318, -5956, -6252, -6256, -5995, -5495, -4839, -3936, -2816, -1474, + 17, 1545, 3056, 4394, 5430, 6022, 6161, 5943, 5532, 5070, 4740, 4558, + 4464, 4308, 3995, 3455, 2675, 1679, 538, -531, -1419, -2017, -2315, -2441, +-2510, -2570, -2632, -2553, -2270, -1746, -1047, -368, 161, 392, 177, -553, +-1642, -2811, -3817, -4378, -4394, -3952, -3284, -2686, -2313, -2236, -2437, -2858, +-3259, -3418, -3195, -2553, -1610, -499, 598, 1571, 2406, 3204, 4038, 4940, + 5785, 6480, 6950, 7064, 6697, 5865, 4704, 3418, 2177, 1107, 374, -82, + -403, -721, -1134, -1674, -2364, -3146, -3900, -4516, -4937, -5085, -5010, -4842, +-4692, -4598, -4496, -4284, -3817, -2993, -1904, -680, 581, 1667, 2504, 3055, + 3383, 3612, 3828, 4183, 4680, 5151, 5397, 5355, 4918, 4097, 2971, 1687, + 438, -700, -1617, -2227, -2584, -2723, -2726, -2652, -2566, -2493, -2339, -2118, +-1886, -1588, -1260, -959, -790, -749, -831, -988, -1117, -1115, -900, -511, + -26, 415, 749, 974, 1104, 1257, 1491, 1823, 2288, 2767, 3130, 3285, + 3216, 2954, 2563, 2176, 1902, 1736, 1637, 1479, 1144, 646, 5, -676, +-1260, -1685, -1883, -1895, -1801, -1702, -1670, -1716, -1905, -2150, -2383, -2483, +-2419, -2170, -1727, -1202, -684, -312, -119, -73, -147, -213, -150, 95, + 545, 1143, 1719, 2172, 2457, 2521, 2501, 2456, 2494, 2667, 2865, 3003, + 2930, 2573, 1912, 1032, 111, -700, -1272, -1526, -1517, -1417, -1410, -1670, +-2259, -3087, -3978, -4703, -5071, -5031, -4617, -3920, -3064, -2199, -1383, -666, + 36, 791, 1566, 2371, 3106, 3702, 4099, 4312, 4408, 4446, 4466, 4430, + 4280, 4008, 3525, 2841, 1878, 672, -664, -2059, -3356, -4429, -5187, -5623, +-5785, -5760, -5597, -5356, -5125, -4862, -4547, -4100, -3411, -2513, -1391, -137, + 1134, 2373, 3479, 4475, 5352, 6078, 6617, 6984, 7092, 6846, 6213, 5175, + 3824, 2259, 731, -551, -1512, -2170, -2611, -2930, -3204, -3519, -3884, -4238, +-4507, -4620, -4546, -4274, -3830, -3277, -2695, -2115, -1484, -768, 0, 797, + 1572, 2256, 2750, 3016, 3057, 2891, 2545, 2069, 1602, 1214, 970, 866, + 868, 909, 936, 900, 793, 674, 470, 192, -171, -640, -1215, -1899, +-2588, -3207, -3626, -3836, -3762, -3400, -2823, -2120, -1418, -759, -171, 348, + 796, 1230, 1666, 2122, 2560, 2968, 3335, 3647, 3852, 3912, 3846, 3656, + 3329, 2882, 2329, 1716, 1090, 465, -139, -685, -1192, -1657, -2052, -2407, +-2736, -3044, -3320, -3564, -3714, -3727, -3553, -3176, -2598, -1890, -1103, -290, + 485, 1207, 1839, 2364, 2793, 3139, 3394, 3555, 3676, 3700, 3635, 3487, + 3312, 3145, 2935, 2698, 2385, 1944, 1344, 585, -317, -1284, -2243, -3085, +-3693, -4043, -4125, -4004, -3749, -3426, -3071, -2724, -2431, -2166, -1933, -1688, +-1374, -987, -514, 23, 560, 1108, 1625, 2080, 2453, 2748, 3007, 3253, + 3522, 3800, 4089, 4322, 4412, 4333, 4045, 3487, 2676, 1641, 487, -709, +-1866, -2937, -3961, -4978, -5962, -6871, -7587, -8009, -8073, -7809, -7274, -6529, +-5658, -4735, -3763, -2720, -1572, -319, 1035, 2439, 3820, 5079, 6095, 6831, + 7296, 7501, 7440, 7218, 6870, 6397, 5842, 5195, 4467, 3612, 2649, 1588, + 470, -640, -1714, -2712, -3632, -4480, -5223, -5858, -6353, -6700, -6861, -6790, +-6441, -5776, -4851, -3704, -2409, -1091, 134, 1192, 2031, 2683, 3194, 3653, + 4143, 4681, 5222, 5631, 5835, 5787, 5472, 4947, 4279, 3543, 2786, 1987, + 1104, 85, -1060, -2323, -3657, -4937, -6020, -6810, -7259, -7329, -7099, -6678, +-6115, -5467, -4735, -3899, -2937, -1847, -630, 623, 1854, 2977, 3922, 4679, + 5227, 5619, 5880, 6045, 6065, 5923, 5623, 5175, 4617, 3976, 3287, 2575, + 1837, 1075, 305, -481, -1273, -2078, -2859, -3573, -4174, -4649, -4994, -5208, +-5274, -5151, -4850, -4330, -3618, -2706, -1655, -508, 683, 1818, 2818, 3577, + 4067, 4322, 4371, 4253, 4035, 3756, 3488, 3241, 3071, 2969, 2857, 2673, + 2359, 1880, 1252, 465, -426, -1374, -2319, -3219, -4021, -4698, -5204, -5501, +-5568, -5360, -4946, -4369, -3709, -3091, -2529, -2023, -1545, -1011, -392, 308, + 1074, 1833, 2533, 3080, 3390, 3482, 3417, 3219, 2957, 2717, 2544, 2446, + 2386, 2308, 2178, 1961, 1651, 1249, 802, 359, -41, -383, -685, -921, +-1083, -1191, -1220, -1134, -984, -763, -509, -265, -55, 94, 171, 154, + 68, -63, -189, -282, -330, -359, -365, -366, -391, -401, -423, -406, + -339, -184, 26, 248, 458, 599, 685, 721, 743, 809, 932, 1109, + 1281, 1436, 1473, 1352, 1059, 621, 106, -412, -821, -1076, -1184, -1178, +-1133, -1149, -1280, -1503, -1819, -2152, -2398, -2471, -2319, -1975, -1487, -948, + -480, -183, -67, -107, -235, -380, -482, -481, -378, -204, 24, 269, + 493, 649, 712, 700, 659, 618, 601, 630, 751, 979, 1288, 1652, + 2037, 2378, 2638, 2755, 2717, 2537, 2239, 1833, 1396, 999, 674, 436, + 252, 64, -145, -373, -645, -928, -1199, -1426, -1616, -1769, -1891, -1978, +-2038, -2049, -2001, -1872, -1631, -1320, -969, -629, -332, -92, 105, 299, + 490, 694, 963, 1300, 1669, 2003, 2241, 2348, 2326, 2220, 2082, 1986, + 1946, 1972, 2010, 1997, 1888, 1617, 1147, 503, -234, -957, -1595, -2105, +-2453, -2665, -2797, -2897, -2998, -3076, -3114, -3062, -2866, -2524, -2073, -1573, +-1132, -799, -573, -384, -172, 156, 665, 1358, 2180, 3032, 3795, 4362, + 4661, 4667, 4406, 3948, 3361, 2691, 1986, 1292, 627, 15, -552, -1133, +-1749, -2388, -3088, -3848, -4624, -5410, -6120, -6652, -6986, -7039, -6741, -6141, +-5266, -4197, -3027, -1888, -842, 65, 856, 1579, 2337, 3174, 4105, 5064, + 5969, 6725, 7212, 7374, 7198, 6722, 6035, 5216, 4333, 3463, 2590, 1709, + 801, -148, -1072, -1940, -2655, -3180, -3463, -3528, -3444, -3310, -3202, -3172, +-3241, -3357, -3480, -3522, -3472, -3303, -3029, -2657, -2219, -1751, -1244, -735, + -226, 291, 769, 1203, 1583, 1948, 2246, 2522, 2795, 3070, 3367, 3626, + 3851, 3979, 3961, 3774, 3438, 2964, 2423, 1867, 1296, 721, 101, -562, +-1303, -2106, -2896, -3633, -4215, -4608, -4778, -4739, -4539, -4226, -3883, -3535, +-3173, -2775, -2261, -1620, -803, 131, 1115, 2046, 2813, 3358, 3701, 3882, + 3967, 4031, 4069, 4088, 4035, 3853, 3482, 2935, 2269, 1565, 888, 321, + -124, -440, -691, -984, -1327, -1767, -2254, -2752, -3174, -3414, -3408, -3194, +-2839, -2445, -2126, -1937, -1871, -1898, -1896, -1772, -1458, -901, -173, 663, + 1497, 2243, 2834, 3270, 3582, 3783, 3899, 3914, 3860, 3719, 3458, 3104, + 2638, 2115, 1540, 919, 243, -505, -1377, -2354, -3396, -4435, -5323, -5965, +-6295, -6287, -5989, -5490, -4854, -4178, -3514, -2858, -2187, -1459, -664, 232, + 1205, 2203, 3170, 4066, 4820, 5419, 5841, 6060, 6130, 6075, 5959, 5769, + 5510, 5146, 4651, 4026, 3267, 2393, 1446, 460, -533, -1503, -2445, -3322, +-4141, -4861, -5481, -5911, -6107, -6108, -5849, -5414, -4842, -4163, -3408, -2621, +-1810, -973, -155, 618, 1309, 1903, 2346, 2639, 2823, 2942, 3043, 3161, + 3299, 3453, 3558, 3582, 3492, 3248, 2857, 2334, 1713, 1069, 456, -102, + -571, -988, -1394, -1830, -2325, -2878, -3451, -4001, -4484, -4830, -5025, -5048, +-4934, -4712, -4394, -3998, -3497, -2846, -2035, -1072, 8, 1136, 2207, 3132, + 3880, 4423, 4785, 5021, 5188, 5346, 5498, 5612, 5636, 5494, 5143, 4529, + 3675, 2613, 1422, 232, -863, -1787, -2517, -3073, -3500, -3867, -4247, -4626, +-4959, -5186, -5221, -4991, -4528, -3827, -2949, -2016, -1080, -192, 638, 1432, + 2164, 2876, 3544, 4136, 4593, 4878, 4967, 4849, 4518, 3985, 3337, 2607, + 1848, 1110, 422, -194, -714, -1147, -1490, -1771, -2020, -2264, -2521, -2790, +-3023, -3173, -3151, -2926, -2473, -1882, -1224, -648, -240, -40, -70, -226, + -426, -546, -502, -237, 217, 782, 1365, 1855, 2191, 2327, 2282, 2103, + 1851, 1601, 1374, 1198, 1056, 899, 689, 394, 11, -420, -876, -1336, +-1753, -2114, -2386, -2574, -2694, -2742, -2726, -2626, -2417, -2069, -1583, -973, + -278, 433, 1106, 1686, 2116, 2415, 2566, 2586, 2515, 2345, 2096, 1792, + 1444, 1096, 783, 530, 352, 231, 121, -33, -258, -560, -921, -1274, +-1550, -1695, -1681, -1518, -1259, -959, -707, -543, -438, -387, -318, -215, + -33, 220, 486, 743, 947, 1050, 1043, 937, 769, 563, 348, 161, + -17, -164, -301, -440, -560, -643, -666, -626, -531, -397, -265, -178, + -154, -197, -303, -436, -555, -631, -645, -584, -453, -268, -53, 184, + 428, 667, 902, 1113, 1329, 1520, 1694, 1823, 1894, 1896, 1803, 1636, + 1414, 1159, 896, 642, 393, 140, -146, -480, -877, -1345, -1854, -2350, +-2769, -3063, -3170, -3103, -2846, -2447, -1953, -1397, -834, -256, 323, 859, + 1362, 1817, 2206, 2508, 2737, 2883, 2947, 2917, 2808, 2599, 2293, 1906, + 1468, 997, 522, 77, -335, -729, -1118, -1524, -1925, -2306, -2631, -2862, +-2979, -2975, -2838, -2597, -2278, -1919, -1546, -1172, -838, -552, -301, -114, + 19, 119, 229, 365, 579, 890, 1276, 1711, 2139, 2487, 2717, 2796, + 2745, 2582, 2352, 2106, 1881, 1676, 1467, 1232, 942, 581, 178, -266, + -705, -1125, -1512, -1887, -2237, -2565, -2874, -3139, -3327, -3422, -3384, -3212, +-2925, -2522, -2045, -1499, -901, -283, 372, 1020, 1647, 2199, 2649, 2969, + 3134, 3172, 3093, 2954, 2818, 2708, 2645, 2612, 2545, 2393, 2112, 1674, + 1096, 400, -328, -1019, -1622, -2094, -2436, -2676, -2852, -2996, -3168, -3371, +-3578, -3760, -3860, -3823, -3586, -3136, -2501, -1707, -852, -32, 665, 1197, + 1528, 1682, 1732, 1739, 1772, 1861, 2019, 2219, 2398, 2503, 2518, 2404, + 2180, 1872, 1527, 1175, 834, 507, 194, -113, -409, -696, -954, -1171, +-1342, -1472, -1543, -1571, -1570, -1515, -1439, -1359, -1266, -1190, -1107, -1020, + -883, -690, -456, -166, 161, 525, 894, 1242, 1569, 1834, 2019, 2097, + 2060, 1901, 1660, 1370, 1086, 842, 687, 582, 500, 416, 280, 67, + -206, -539, -883, -1172, -1367, -1418, -1319, -1109, -834, -585, -393, -292, + -314, -406, -535, -644, -671, -601, -417, -167, 142, 451, 726, 964, + 1149, 1271, 1340, 1343, 1320, 1278, 1218, 1156, 1093, 1021, 950, 868, + 770, 645, 490, 278, -16, -376, -760, -1146, -1479, -1692, -1774, -1725, +-1578, -1393, -1214, -1058, -940, -835, -724, -585, -439, -317, -249, -256, + -337, -441, -534, -576, -522, -348, -85, 210, 496, 719, 829, 829, + 742, 634, 549, 536, 595, 711, 858, 972, 993, 910, 696, 367, + -45, -507, -960, -1336, -1603, -1735, -1733, -1622, -1415, -1178, -958, -769, + -626, -512, -434, -361, -306, -262, -202, -118, 5, 180, 415, 678, + 946, 1187, 1382, 1499, 1541, 1496, 1376, 1165, 907, 628, 339, 98, + -81, -165, -167, -111, -24, 53, 82, 51, -24, -143, -299, -451, + -588, -674, -672, -596, -457, -293, -134, -29, 11, -24, -122, -251, + -381, -473, -493, -429, -270, -48, 215, 482, 708, 859, 936, 950, + 893, 830, 749, 661, 560, 440, 306, 145, -15, -151, -253, -315, + -336, -333, -325, -341, -387, -462, -583, -705, -818, -857, -798, -651, + -419, -136, 121, 340, 499, 564, 566, 533, 485, 456, 436, 445, + 479, 521, 560, 559, 514, 396, 177, -110, -436, -745, -983, -1092, +-1076, -954, -748, -488, -247, -28, 145, 260, 335, 389, 431, 470, + 495, 501, 470, 402, 314, 217, 153, 155, 223, 341, 469, 534, + 525, 384, 150, -127, -403, -607, -697, -669, -550, -382, -207, -64, + 37, 80, 81, 70, 79, 102, 160, 233, 273, 291, 260, 199, + 146, 124, 171, 268, 392, 491, 532, 504, 382, 196, -15, -207, + -341, -394, -373, -295, -197, -134, -140, -237, -405, -633, -832, -963, + -976, -855, -642, -391, -154, 21, 140, 197, 230, 289, 391, 536, + 712, 896, 1071, 1211, 1301, 1341, 1320, 1278, 1201, 1080, 899, 667, + 373, 36, -320, -650, -933, -1143, -1266, -1345, -1399, -1455, -1570, -1720, +-1877, -2017, -2080, -2039, -1887, -1603, -1215, -760, -264, 254, 756, 1195, + 1547, 1807, 1968, 2015, 1953, 1810, 1616, 1384, 1175, 968, 785, 631, + 480, 345, 202, 65, -57, -187, -327, -483, -688, -927, -1188, -1456, +-1675, -1807, -1810, -1698, -1488, -1202, -906, -621, -369, -151, 50, 262, + 491, 744, 998, 1230, 1427, 1556, 1620, 1627, 1585, 1526, 1482, 1458, + 1464, 1478, 1448, 1348, 1162, 887, 516, 102, -321, -710, -1036, -1291, +-1470, -1592, -1672, -1733, -1773, -1798, -1783, -1691, -1527, -1273, -935, -530, + -112, 290, 647, 924, 1121, 1244, 1329, 1377, 1405, 1438, 1452, 1466, + 1483, 1490, 1481, 1432, 1323, 1143, 893, 574, 230, -115, -409, -630, + -774, -841, -887, -926, -1001, -1120, -1285, -1455, -1570, -1593, -1531, -1393, +-1208, -1027, -889, -812, -778, -716, -582, -322, 53, 516, 1025, 1460, + 1773, 1909, 1855, 1647, 1325, 981, 660, 429, 287, 221, 191, 137, + 6, -206, -503, -871, -1232, -1566, -1803, -1927, -1938, -1852, -1675, -1447, +-1184, -893, -615, -345, -77, 195, 453, 705, 952, 1180, 1382, 1550, + 1687, 1793, 1849, 1852, 1775, 1616, 1399, 1120, 808, 480, 150, -158, + -441, -698, -935, -1143, -1316, -1447, -1549, -1613, -1652, -1642, -1588, -1479, +-1312, -1100, -848, -560, -254, 64, 372, 647, 892, 1092, 1219, 1278, + 1295, 1294, 1288, 1273, 1254, 1224, 1161, 1050, 893, 683, 422, 148, + -142, -425, -672, -861, -1004, -1100, -1153, -1177, -1181, -1173, -1139, -1066, + -954, -787, -578, -354, -124, 96, 304, 488, 672, 842, 998, 1144, + 1253, 1339, 1395, 1431, 1431, 1402, 1344, 1244, 1103, 925, 714, 481, + 236, -21, -282, -539, -763, -968, -1143, -1276, -1360, -1387, -1363, -1271, +-1138, -964, -771, -594, -441, -323, -230, -162, -65, 73, 243, 459, + 699, 942, 1141, 1297, 1390, 1409, 1369, 1251, 1066, 817, 547, 277, + 21, -196, -379, -528, -670, -796, -917, -1035, -1133, -1195, -1208, -1170, +-1070, -911, -728, -519, -314, -118, 53, 197, 331, 462, 601, 734, + 846, 921, 944, 910, 824, 701, 561, 423, 289, 162, 37, -88, + -211, -327, -435, -544, -636, -698, -719, -712, -661, -588, -500, -426, + -377, -362, -371, -374, -350, -274, -128, 71, 316, 571, 803, 981, + 1087, 1126, 1105, 1049, 997, 954, 941, 933, 928, 873, 764, 593, + 363, 98, -204, -499, -800, -1077, -1316, -1512, -1674, -1790, -1849, -1861, +-1831, -1747, -1618, -1457, -1244, -992, -691, -357, -2, 365, 714, 1031, + 1292, 1480, 1586, 1620, 1605, 1547, 1476, 1411, 1325, 1215, 1074, 891, + 662, 384, 71, -266, -596, -896, -1152, -1343, -1460, -1508, -1489, -1444, +-1374, -1308, -1237, -1150, -1034, -865, -639, -347, -4, 364, 699, 978, + 1193, 1338, 1420, 1477, 1533, 1613, 1692, 1769, 1811, 1780, 1662, 1456, + 1184, 872, 562, 276, 9, -243, -485, -753, -1053, -1365, -1686, -1983, +-2197, -2315, -2347, -2252, -2065, -1824, -1544, -1255, -960, -656, -342, -14, + 338, 698, 1073, 1426, 1723, 1947, 2074, 2090, 2004, 1834, 1588, 1306, + 983, 646, 319, 0, -302, -573, -827, -1042, -1221, -1347, -1406, -1408, +-1344, -1224, -1069, -896, -702, -515, -319, -139, 31, 200, 369, 539, + 716, 881, 1009, 1079, 1104, 1067, 978, 857, 733, 624, 520, 430, + 344, 241, 108, -47, -231, -410, -561, -685, -748, -767, -746, -704, + -650, -606, -558, -510, -452, -378, -269, -139, -7, 127, 272, 417, + 567, 713, 854, 957, 1010, 1008, 934, 805, 637, 441, 256, 96, + -39, -160, -278, -404, -548, -710, -868, -993, -1080, -1120, -1096, -1034, + -936, -834, -728, -634, -539, -413, -250, -46, 209, 490, 784, 1057, + 1297, 1476, 1577, 1606, 1571, 1498, 1393, 1275, 1148, 994, 837, 653, + 429, 171, -114, -409, -699, -940, -1137, -1262, -1321, -1323, -1280, -1208, +-1104, -991, -865, -734, -561, -373, -168, 45, 255, 433, 577, 670, + 707, 704, 659, 595, 518, 459, 410, 382, 351, 332, 297, 244, + 186, 106, 15, -80, -167, -267, -356, -455, -569, -677, -778, -846, + -877, -872, -833, -759, -669, -553, -424, -284, -145, 4, 183, 365, + 533, 696, 859, 989, 1097, 1177, 1211, 1207, 1162, 1074, 951, 783, + 576, 334, 74, -171, -386, -567, -705, -784, -829, -848, -852, -811, + -745, -657, -551, -424, -292, -134, 41, 207, 376, 528, 658, 750, + 821, 853, 874, 877, 871, 847, 812, 752, 670, 566, 440, 309, + 163, 34, -77, -155, -226, -296, -376, -485, -611, -746, -881, -1007, +-1075, -1112, -1104, -1047, -966, -867, -771, -680, -592, -500, -386, -234, + -49, 138, 313, 466, 600, 685, 732, 760, 766, 745, 700, 626, + 528, 398, 252, 96, -57, -170, -266, -343, -391, -418, -449, -486, + -510, -541, -542, -537, -522, -484, -437, -366, -295, -212, -110, 6, + 103, 205, 288, 336, 350, 332, 297, 253, 210, 160, 136, 99, + 76, 60, 46, 63, 91, 139, 186, 245, 276, 286, 278, 235, + 183, 132, 83, 62, 49, 47, 52, 53, 47, 41, 30, 24, + 7, 3, -11, -9, -16, -10, -4, 15, 54, 91, 147, 206, + 241, 254, 241, 219, 178, 133, 100, 79, 67, 59, 64, 76, + 73, 87, 90, 116, 147, 181, 207, 230, 235, 203, 155, 93, + 45, 2, -22, -22, -20, -34, -63, -109, -172, -233, -306, -373, + -443, -492, -522, -525, -525, -509, -477, -441, -405, -338, -267, -192, + -111, -45, 2, 35, 46, 46, 35, 23, 8, 15, 28, 38, + 64, 83, 101, 118, 141, 157, 178, 191, 181, 153, 109, 20, + -79, -197, -322, -443, -563, -664, -762, -812, -840, -827, -805, -778, + -727, -660, -578, -465, -314, -133, 79, 290, 498, 674, 826, 911, + 933, 908, 843, 746, 613, 470, 309, 142, -26, -186, -317, -414, + -480, -514, -528, -530, -522, -524, -523, -511, -484, -446, -377, -270, + -161, -20, 123, 276, 414, 521, 608, 644, 648, 619, 566, 499, + 447, 395, 372, 379, 411, 453, 489, 502, 479, 452, 376, 286, + 188, 84, -11, -96, -164, -224, -268, -304, -334, -368, -395, -411, + -422, -428, -406, -390, -360, -325, -301, -243, -172, -105, -41, 20, + 73, 97, 103, 91, 51, -6, -92, -159, -230, -289, -319, -339, + -321, -268, -196, -105, -11, 75, 115, 115, 65, -9, -90, -172, + -233, -270, -263, -234, -183, -117, -47, 5, 50, 51, 45, 32, + 9, -11, -12, -5, -6, 7, 31, 47, 87, 143, 198, 248, + 282, 298, 295, 264, 221, 170, 135, 95, 71, 49, 36, 26, + 0, -35, -70, -105, -148, -177, -207, -234, -255, -251, -241, -218, + -184, -133, -71, -25, 42, 106, 173, 249, 314, 380, 430, 496, + 528, 554, 580, 588, 580, 551, 517, 462, 401, 320, 230, 119, + 13, -79, -149, -184, -192, -164, -150, -134, -143, -173, -209, -241, + -263, -270, -241, -201, -152, -106, -50, 6, 58, 90, 122, 147, + 161, 168, 156, 142, 112, 107, 97, 96, 103, 104, 89, 57, + 7, -48, -106, -160, -193, -226, -249, -263, -262, -243, -218, -167, + -120, -62, 13, 104, 194, 297, 397, 480, 536, 565, 571, 543, + 488, 427, 363, 283, 212, 151, 76, -4, -97, -193, -290, -358, + -399, -424, -418, -382, -349, -313, -260, -211, -165, -128, -90, -67, + -48, -25, -6, 7, 7, 23, 25, 27, 38, 47, 43, 35, + 29, 28, 41, 76, 121, 150, 169, 164, 141, 91, 40, -4, + -33, -38, -26, 8, 43, 72, 85, 69, 35, 2, -29, -55, + -51, -22, 11, 70, 142, 199, 255, 302, 324, 321, 322, 324, + 340, 358, 372, 399, 397, 359, 287, 172, 25, -117, -253, -365, + -458, -515, -558, -598, -652, -699, -736, -775, -769, -731, -653, -529, + -378, -216, -55, 94, 203, 286, 342, 380, 399, 423, 437, 445, + 437, 419, 387, 329, 259, 189, 118, 34, -34, -98, -148, -185, + -214, -228, -223, -201, -172, -131, -89, -49, -5, 17, 26, 21, + 13, 2, -12, -9, 3, 26, 77, 122, 171, 205, 237, 254, + 257, 254, 231, 187, 138, 59, -10, -89, -170, -247, -321, -384, + -436, -460, -477, -475, -463, -446, -433, -409, -386, -359, -319, -264, + -198, -128, -48, 26, 95, 165, 237, 307, 375, 435, 481, 512, + 518, 494, 447, 395, 336, 287, 241, 195, 141, 58, -51, -175, + -308, -443, -546, -613, -652, -649, -608, -538, -450, -365, -277, -195, + -108, -20, 75, 179, 270, 369, 461, 523, 570, 604, 615, 616, + 605, 586, 552, 510, 439, 337, 205, 43, -127, -282, -412, -503, + -558, -560, -534, -503, -466, -441, -430, -435, -440, -432, -419, -390, + -336, -251, -155, -63, 42, 150, 246, 353, 445, 535, 622, 692, + 745, 774, 761, 708, 636, 538, 434, 339, 236, 154, 53, -63, + -200, -354, -518, -668, -790, -870, -898, -876, -814, -722, -625, -537, + -445, -375, -296, -209, -106, 25, 168, 319, 452, 583, 667, 714, + 717, 700, 659, 589, 517, 443, 366, 275, 153, 9, -146, -298, + -455, -609, -736, -830, -896, -924, -917, -891, -842, -755, -639, -510, + -361, -186, -10, 155, 317, 460, 578, 667, 745, 815, 868, 903, + 912, 894, 855, 788, 675, 540, 383, 196, 20, -156, -342, -503, + -643, -755, -831, -883, -887, -870, -828, -761, -679, -601, -526, -437, + -352, -271, -190, -100, 1, 115, 238, 366, 488, 600, 679, 728, + 757, 755, 734, 699, 656, 590, 510, 423, 312, 186, 42, -106, + -241, -380, -503, -603, -683, -750, -800, -815, -817, -798, -745, -660, + -551, -406, -227, -47, 133, 302, 443, 561, 643, 705, 745, 764, + 769, 769, 739, 700, 661, 601, 517, 418, 308, 164, 23, -123, + -280, -419, -529, -614, -674, -699, -690, -661, -611, -540, -466, -385, + -311, -240, -182, -130, -72, -23, 41, 121, 216, 327, 432, 527, + 589, 616, 610, 571, 500, 407, 314, 212, 102, -3, -105, -196, + -267, -322, -359, -383, -400, -402, -401, -398, -391, -377, -346, -305, + -237, -153, -70, 33, 129, 215, 285, 342, 365, 374, 372, 355, + 344, 328, 320, 299, 258, 231, 194, 137, 94, 44, -21, -87, + -156, -230, -293, -333, -365, -371, -352, -301, -235, -169, -87, -1, + 67, 126, 177, 220, 269, 316, 358, 401, 437, 465, 487, 495, + 484, 462, 416, 364, 306, 229, 149, 63, -36, -116, -203, -298, + -373, -447, -495, -532, -554, -552, -528, -489, -444, -386, -326, -259, + -182, -84, 17, 115, 220, 320, 400, 474, 539, 569, 605, 633, + 647, 643, 621, 577, 503, 412, 293, 161, 23, -103, -226, -352, + -463, -558, -648, -718, -758, -787, -785, -744, -675, -598, -508, -408, + -324, -237, -138, -28, 97, 250, 408, 564, 705, 814, 888, 907, + 895, 846, 765, 662, 556, 456, 340, 240, 133, 16, -99, -211, + -332, -441, -519, -584, -636, -677, -693, -694, -684, -663, -625, -560, + -480, -379, -259, -129, 1, 131, 241, 336, 415, 480, 532, 581, + 619, 648, 674, 686, 669, 634, 570, 484, 380, 257, 125, -10, + -138, -266, -374, -460, -527, -555, -565, -543, -504, -451, -388, -336, + -287, -251, -209, -175, -143, -105, -60, -14, 45, 105, 163, 225, + 282, 338, 379, 414, 434, 438, 431, 407, 370, 326, 279, 230, + 186, 138, 94, 38, -32, -112, -196, -269, -347, -402, -438, -464, + -457, -439, -408, -355, -297, -226, -142, -59, 19, 73, 121, 146, + 158, 159, 155, 166, 175, 195, 224, 223, 196, 146, 66, -20, + -108, -185, -243, -286, -303, -303, -300, -286, -266, -240, -218, -183, + -144, -110, -73, -39, -24, -13, 4, 15, 34, 63, 101, 129, + 150, 158, 142, 109, 74, 48, 24, 2, -13, -30, -49, -73, + -100, -132, -159, -182, -189, -191, -176, -146, -109, -78, -32, 14, + 45, 94, 142, 185, 211, 230, 236, 226, 215, 196, 183, 172, + 168, 170, 169, 170, 152, 120, 83, 35, -25, -83, -142, -179, + -211, -226, -227, -228, -236, -243, -238, -231, -221, -194, -140, -88, + -20, 51, 111, 160, 198, 229, 249, 270, 288, 305, 314, 296, + 265, 223, 169, 114, 63, 10, -17, -38, -56, -78, -99, -130, + -176, -202, -228, -246, -253, -241, -232, -232, -210, -186, -157, -115, + -59, -10, 42, 88, 132, 153, 165, 178, 172, 173, 179, 183, + 195, 205, 214, 204, 177, 130, 60, -13, -77, -146, -200, -252, + -286, -311, -330, -339, -335, -324, -298, -263, -222, -177, -143, -113, + -94, -81, -62, -48, -18, 20, 79, 133, 184, 223, 245, 245, + 235, 223, 204, 183, 164, 153, 138, 110, 90, 57, 24, -10, + -49, -89, -122, -168, -207, -236, -261, -273, -269, -245, -214, -191, + -163, -141, -114, -90, -66, -36, -3, 31, 84, 139, 195, 240, + 287, 320, 332, 343, 334, 302, 266, 223, 172, 118, 65, 15, + -28, -67, -98, -127, -147, -159, -163, -172, -181, -182, -184, -188, + -176, -160, -128, -93, -52, -11, 23, 49, 50, 55, 42, 30, + 27, 14, 14, 11, 14, 23, 29, 40, 43, 47, 52, 56, + 49, 53, 38, 0, -36, -78, -110, -137, -133, -119, -94, -64, + -47, -32, -50, -61, -75, -94, -98, -107, -100, -95, -83, -73, + -62, -46, -34, -10, 18, 38, 54, 64, 62, 55, 35, 22, + 17, 29, 46, 82, 116, 145, 163, 175, 184, 190, 189, 182, + 183, 163, 143, 122, 93, 63, 42, 22, 11, 6, 9, 16, + 15, 5, -15, -47, -73, -100, -110, -109, -94, -79, -67, -45, + -45, -43, -42, -48, -52, -51, -50, -49, -33, -32, -26, -9, + 9, 40, 73, 104, 141, 168, 170, 160, 135, 107, 79, 47, + 30, 13, -6, -17, -35, -58, -88, -120, -155, -179, -197, -204, + -186, -160, -129, -80, -49, -16, 6, 24, 41, 59, 73, 87, + 101, 116, 116, 111, 106, 101, 86, 79, 88, 75, 76, 74, + 68, 53, 54, 49, 34, 32, 29, 22, 17, 15, 3, -3, + -9, -24, -25, -26, -25, -18, -18, -19, -29, -32, -37, -30, + -10, 3, 26, 48, 72, 95, 97, 106, 100, 94, 94, 90, + 89, 83, 74, 45, 17, -13, -40, -61, -69, -66, -69, -66, + -60, -58, -66, -80, -91, -109, -119, -120, -100, -85, -73, -59, + -58, -58, -55, -48, -35, -12, 15, 32, 50, 68, 65, 62, + 72, 72, 90, 106, 134, 144, 147, 147, 140, 112, 82, 51, + 9, -33, -71, -110, -155, -197, -239, -266, -281, -283, -269, -244, + -212, -181, -155, -126, -107, -86, -64, -43, -9, 31, 64, 100, + 134, 157, 167, 172, 169, 167, 165, 161, 148, 124, 114, 97, + 75, 64, 48, 32, 19, 3, -9, -30, -54, -77, -100, -122, + -135, -141, -152, -155, -159, -161, -163, -152, -141, -130, -113, -85, + -59, -25, 18, 68, 100, 135, 171, 187, 201, 213, 226, 226, + 231, 225, 207, 178, 139, 96, 42, 4, -35, -71, -94, -112, + -126, -129, -132, -130, -131, -130, -126, -117, -99, -85, -66, -51, + -31, -22, -10, -3, 1, 14, 11, 14, 10, 7, 10, 14, + 11, 22, 32, 36, 40, 35, 25, 15, 2, -6, -10, -17, + -25, -40, -56, -88, -117, -148, -167, -183, -194, -182, -165, -139, + -105, -74, -38, -7, 24, 47, 74, 98, 116, 123, 123, 124, + 114, 112, 108, 92, 80, 58, 39, 25, 0, -20, -42, -65, + -71, -77, -81, -72, -59, -36, -12, 23, 66, 95, 125, 155, + 167, 171, 175, 149, 134, 124, 114, 108, 118, 132, 150, 159, + 164, 157, 137, 114, 86, 48, 11, -16, -40, -56, -62, -70, + -78, -91, -92, -100, -106, -110, -121, -124, -120, -107, -103, -81, + -57, -26, 11, 51, 90, 111, 133, 154, 162, 170, 167, 157, + 148, 135, 120, 100, 71, 45, 12, -26, -61, -107, -147, -184, + -210, -242, -272, -284, -297, -290, -276, -252, -229, -197, -158, -127, + -93, -63, -39, -7, 23, 54, 85, 117, 147, 158, 178, 185, + 179, 165, 144, 122, 92, 68, 33, 3, -24, -65, -99, -131, + -154, -178, -195, -200, -206, -222, -217, -218, -219, -204, -188, -170, + -139, -107, -67, -29, 20, 59, 92, 128, 159, 183, 204, 222, + 226, 228, 222, 210, 196, 174, 159, 132, 101, 66, 33, -9, + -53, -78, -103, -118, -124, -120, -114, -101, -83, -77, -64, -48, + -37, -30, -11, 12, 21, 51, 82, 103, 135, 158, 172, 171, + 172, 165, 148, 139, 125, 105, 92, 83, 65, 56, 55, 46, + 30, 18, -2, -40, -75, -110, -148, -184, -207, -226, -241, -243, + -231, -214, -191, -160, -136, -109, -78, -56, -40, -27, -12, -3, + 9, 37, 57, 86, 115, 139, 155, 150, 145, 113, 73, 26, + -27, -71, -100, -112, -120, -112, -90, -67, -51, -35, -32, -45, + -60, -67, -74, -68, -46, -18, 11, 55, 88, 116, 136, 148, + 153, 142, 133, 116, 90, 78, 65, 61, 62, 58, 55, 52, + 45, 26, 15, -6, -32, -56, -81, -93, -107, -113, -106, -95, + -71, -47, -19, 17, 55, 85, 115, 137, 146, 149, 152, 150, + 139, 144, 146, 145, 145, 146, 145, 133, 111, 79, 32, -15, + -59, -103, -144, -171, -199, -213, -215, -220, -201, -191, -184, -176, + -175, -165, -157, -144, -127, -101, -72, -41, -12, 22, 56, 80, + 103, 111, 112, 97, 86, 70, 42, 17, 6, -16, -31, -39, + -49, -62, -66, -72, -87, -102, -120, -129, -141, -141, -124, -101, + -78, -53, -26, 0, 32, 53, 66, 84, 105, 117, 122, 133, + 148, 154, 169, 178, 184, 180, 175, 157, 128, 97, 61, 29, + -15, -49, -83, -109, -114, -125, -123, -107, -90, -78, -71, -54, + -46, -40, -27, -23, -18, -6, 14, 35, 57, 86, 108, 130, + 142, 151, 148, 135, 126, 105, 88, 78, 58, 41, 31, 25, + 26, 9, 0, -20, -41, -59, -83, -103, -123, -134, -143, -149, + -145, -130, -117, -95, -78, -54, -42, -32, -15, 0, 20, 37, + 57, 80, 103, 126, 139, 149, 146, 132, 109, 88, 66, 37, + 16, -7, -30, -48, -65, -82, -95, -103, -112, -116, -117, -118, + -115, -100, -77, -53, -29, 4, 30, 56, 84, 107, 122, 127, + 124, 110, 95, 80, 67, 63, 53, 48, 45, 43, 50, 53, + 55, 56, 43, 34, 11, -15, -43, -72, -84, -92, -109, -111, + -109, -106, -101, -86, -78, -78, -73, -73, -69, -59, -37, -14, + 20, 54, 76, 103, 117, 126, 128, 124, 120, 102, 83, 67, + 42, 26, 6, -10, -24, -30, -44, -56, -58, -59, -54, -42, + -31, -35, -24, -16, -10, 5, 23, 39, 52, 63, 70, 71, + 65, 74, 77, 72, 78, 70, 54, 44, 26, 15, -4, -18, + -32, -45, -58, -64, -67, -67, -56, -49, -45, -34, -20, -12, + -12, -3, 7, 11, 17, 19, 26, 29, 31, 30, 37, 42, + 45, 46, 45, 46, 38, 28, 32, 21, 8, 2, -13, -24, + -31, -37, -42, -45, -50, -44, -41, -31, -17, -13, 6, 13, + 15, 25, 21, 14, 9, -3, -10, -27, -45, -49, -56, -49, + -43, -39, -26, -23, -13, -3, 0, 16, 36, 47, 58, 63, + 63, 69, 61, 50, 47, 34, 18, -2, -14, -21, -32, -37, + -37, -37, -37, -39, -36, -24, -13, -10, 10, 14, 15, 19, + 25, 18, 15, 11, 9, -4, -21, -26, -36, -39, -37, -33, + -26, -31, -34, -33, -39, -40, -43, -51, -57, -66, -75, -77, + -85, -87, -79, -74, -66, -64, -59, -48, -42, -30, -22, -14, + -3, -1, 3, 7, 0, 0, 6, 3, 1, -9, -22, -33, + -43, -45, -50, -59, -62, -66, -69, -65, -60, -54, -52, -46, + -42, -38, -28, -10, 3, 23, 41, 50, 64, 63, 67, 72, + 68, 64, 54, 45, 34, 23, 12, 8, 7, 8, 7, 1, + -7, -20, -31, -35, -37, -32, -33, -28, -25, -17, -10, -5, + 4, -6, -15, -25, -44, -53, -66, -72, -70, -56, -40, -32, + -5, 21, 50, 79, 102, 118, 126, 135, 137, 135, 129, 121, + 114, 98, 83, 59, 35, 24, 0, -14, -26, -41, -45, -52, + -55, -55, -58, -59, -67, -61, -53, -51, -45, -43, -37, -34, + -34, -34, -41, -46, -50, -52, -52, -55, -56, -59, -58, -61, + -56, -59, -55, -48, -46, -45, -43, -40, -44, -38, -41, -36, + -30, -30, -21, -18, -13, -6, -7, -2, -2, -3, -3, -5, + -5, -1, 2, 10, 23, 32, 40, 47, 54, 58, 55, 58, + 60, 53, 54, 55, 52, 59, 52, 47, 46, 34, 32, 22, + 12, 8, -4, 6, 6, 9, 17, 15, 19, 24, 15, 20, + 19, 21, 21, 19, 19, 20, 24, 24, 26, 26, 29, 32, + 31, 28, 32, 40, 38, 34, 33, 27, 23, 21, 23, 23, + 26, 24, 21, 31, 27, 27, 27, 22, 21, 15, 11, 12, + 18, 22, 33, 26, 23, 17, 8, -3, -12, -16, -16, -24, + -23, -18, -22, -14, -17, -15, -11, -18, -17, -20, -23, -19, + -26, -27, -27, -40, -43, -48, -57, -56, -61, -63, -60, -66, + -54, -53, -53, -49, -45, -41, -37, -34, -28, -24, -28, -26, + -26, -31, -32, -25, -22, -18, -19, -9, -5, 5, 16, 24, + 35, 37, 45, 54, 58, 56, 57, 57, 61, 59, 56, 53, + 48, 42, 36, 32, 28, 25, 26, 19, 17, 18, 13, 19, + 19, 21, 26, 23, 27, 25, 27, 34, 32, 36, 39, 33, + 37, 30, 24, 30, 21, 23, 33, 27, 27, 19, 16, 14, + 1, -5, -7, -13, -13, -15, -12, -7, -6, 5, 13, 17, + 32, 35, 38, 41, 36, 42, 38, 39, 32, 25, 23, 23, + 29, 37, 37, 44, 50, 40, 40, 26, 24, 16, 2, -1, + -14, -20, -24, -34, -37, -43, -49, -55, -65, -66, -69, -79, + -75, -73, -70, -62, -60, -50, -48, -43, -43, -47, -46, -50, + -51, -48, -51, -53, -43, -45, -38, -37, -36, -33, -32, -31, + -34, -32, -28, -28, -24, -22, -24, -19, -16, -11, -6, -5, + 3, 15, 23, 34, 34, 44, 61, 66, 81, 92, 97, 100, + 102, 109, 110, 103, 97, 97, 95, 96, 99, 102, 100, 98, + 94, 85, 79, 71, 64, 58, 46, 32, 19, 9, 5, -9, + -14, -19, -32, -39, -42, -47, -56, -56, -64, -69, -68, -70, + -64, -53, -40, -25, -21, -17, -9, -4, -3, 3, 5, 6, + 9, 12, 21, 23, 28, 28, 29, 33, 24, 23, 11, 5, + 0, -4, -13, -19, -30, -30, -28, -33, -29, -26, -26, -21, + -22, -18, -19, -18, -17, -14, -11, -9, -10, -11, -14, -25, + -37, -47, -55, -66, -75, -80, -92, -96, -98, -102, -96, -99, + -97, -91, -90, -87, -88, -94, -90, -93, -92, -85, -77, -67, + -60, -46, -35, -22, -4, 10, 21, 38, 53, 66, 75, 85, + 91, 94, 95, 93, 100, 99, 95, 91, 87, 81, 73, 65, + 63, 60, 58, 46, 40, 33, 21, 16, 3, 2, -4, -15, + -16, -15, -18, -19, -14, -8, -6, -3, 4, 8, 10, 17, + 17, 21, 18, 13, 13, -2, -18, -34, -42, -55, -62, -67, + -79, -79, -84, -85, -85, -84, -91, -94, -93, -93, -93, -89, + -82, -76, -65, -56, -51, -42, -33, -18, -4, 1, 8, 18, + 26, 39, 53, 60, 72, 84, 90, 95, 96, 84, 78, 64, + 64, 56, 47, 40, 33, 26, 19, 13, 1, -12, -19, -31, + -40, -48, -59, -64, -64, -72, -64, -54, -52, -41, -27, -19, + -12, -7, 6, 21, 34, 40, 52, 65, 71, 82, 91, 89, + 82, 79, 70, 57, 46, 37, 24, 16, 5, -4, -10, -14, + -17, -23, -21, -25, -33, -30, -31, -28, -21, -14, -5, 7, + 25, 45, 57, 68, 87, 98, 98, 106, 101, 94, 93, 84, + 74, 61, 48, 27, 7, -14, -34, -61, -88, -104, -116, -133, + -140, -135, -138, -130, -119, -113, -100, -83, -64, -42, -30, -11, + 2, 14, 28, 41, 52, 60, 66, 64, 72, 72, 67, 65, + 66, 63, 53, 45, 31, 27, 10, -3, -17, -42, -54, -67, + -70, -70, -75, -75, -71, -62, -48, -44, -29, -15, 2, 18, + 34, 46, 57, 76, 93, 104, 121, 128, 128, 128, 123, 114, + 98, 73, 57, 41, 27, 12, -12, -27, -44, -60, -64, -77, + -85, -89, -87, -91, -84, -80, -73, -55, -33, -10, 9, 34, + 49, 70, 81, 89, +}; + + +const float lin2mel_packed_513x40[987] = { + 0.359173, 0.710586, 0.945429, 0.608567, 0.278538, 0.054571, 0.391433, 0.721462, + 0.955072, 0.637910, 0.326813, 0.021555, 0.044928, 0.362090, 0.673187, 0.978445, + 0.721917, 0.427698, 0.138706, 0.278083, 0.572302, 0.861294, 0.854757, 0.575678, + 0.301306, 0.031485, 0.145243, 0.424322, 0.698694, 0.968515, 0.766066, 0.504907, + 0.247875, 0.233934, 0.495093, 0.752125, 0.994839, 0.745678, 0.500275, 0.258519, + 0.020304, 0.005161, 0.254322, 0.499725, 0.741481, 0.979696, 0.785526, 0.554088, + 0.325895, 0.100859, 0.214474, 0.445912, 0.674105, 0.899141, 0.878892, 0.659914, + 0.443845, 0.230606, 0.020127, 0.121108, 0.340086, 0.556155, 0.769394, 0.979873, + 0.812335, 0.607163, 0.404548, 0.204424, 0.006733, 0.187665, 0.392837, 0.595452, + 0.795576, 0.993267, 0.811414, 0.618412, 0.427673, 0.239145, 0.052775, 0.188586, + 0.381588, 0.572327, 0.760855, 0.947225, 0.868516, 0.686323, 0.506142, 0.327940, + 0.151667, 0.131484, 0.313677, 0.493858, 0.672060, 0.848333, 0.977283, 0.804747, + 0.634023, 0.465073, 0.297857, 0.132345, 0.022717, 0.195253, 0.365977, 0.534927, + 0.702143, 0.867655, 0.968497, 0.806285, 0.645672, 0.486630, 0.329129, 0.173135, + 0.018626, 0.031503, 0.193715, 0.354328, 0.513370, 0.670871, 0.826865, 0.981374, + 0.865570, 0.713938, 0.563707, 0.414851, 0.267346, 0.121164, 0.134430, 0.286062, + 0.436293, 0.585149, 0.732654, 0.878836, 0.976285, 0.832684, 0.690339, 0.549230, + 0.409333, 0.270630, 0.133098, 0.023715, 0.167316, 0.309661, 0.450770, 0.590667, + 0.729370, 0.866902, 0.996720, 0.861476, 0.727345, 0.594310, 0.462357, 0.331465, + 0.201617, 0.072797, 0.003280, 0.138524, 0.272655, 0.405690, 0.537643, 0.668535, + 0.798383, 0.927203, 0.944989, 0.818177, 0.692345, 0.567482, 0.443567, 0.320588, + 0.198536, 0.077390, 0.055011, 0.181823, 0.307655, 0.432518, 0.556433, 0.679412, + 0.801464, 0.922610, 0.957138, 0.837770, 0.719270, 0.601627, 0.484831, 0.368866, + 0.253720, 0.139386, 0.025849, 0.042862, 0.162230, 0.280730, 0.398373, 0.515169, + 0.631134, 0.746280, 0.860614, 0.974151, 0.913096, 0.801122, 0.689915, 0.579458, + 0.469751, 0.360775, 0.252526, 0.144991, 0.038163, 0.086904, 0.198878, 0.310085, + 0.420542, 0.530249, 0.639225, 0.747474, 0.855008, 0.961837, 0.932033, 0.826588, + 0.721825, 0.617730, 0.514300, 0.411520, 0.309384, 0.207890, 0.107022, 0.006776, + 0.067967, 0.173412, 0.278175, 0.382270, 0.485700, 0.588480, 0.690616, 0.792110, + 0.892978, 0.993224, 0.907145, 0.808118, 0.709693, 0.611858, 0.514607, 0.417937, + 0.321836, 0.226299, 0.131318, 0.036891, 0.092855, 0.191882, 0.290307, 0.388142, + 0.485393, 0.582063, 0.678164, 0.773701, 0.868682, 0.963109, 0.943007, 0.849663, + 0.756852, 0.664568, 0.572802, 0.481552, 0.390811, 0.300573, 0.210833, 0.121584, + 0.032824, 0.056993, 0.150337, 0.243148, 0.335432, 0.427198, 0.518448, 0.609189, + 0.699427, 0.789167, 0.878416, 0.967176, 0.944545, 0.856741, 0.769408, 0.682545, + 0.596139, 0.510192, 0.424698, 0.339648, 0.255038, 0.170871, 0.087135, 0.003828, + 0.055455, 0.143259, 0.230592, 0.317455, 0.403861, 0.489808, 0.575302, 0.660352, + 0.744962, 0.829129, 0.912865, 0.996172, 0.920945, 0.838484, 0.756435, 0.674798, + 0.593574, 0.512750, 0.432324, 0.352296, 0.272660, 0.193410, 0.114541, 0.036059, + 0.079055, 0.161516, 0.243565, 0.325202, 0.406426, 0.487250, 0.567676, 0.647704, + 0.727340, 0.806590, 0.885459, 0.963941, 0.957951, 0.880216, 0.802852, 0.725852, + 0.649217, 0.572937, 0.497017, 0.421450, 0.346230, 0.271358, 0.196829, 0.122637, + 0.048783, 0.042049, 0.119784, 0.197148, 0.274148, 0.350783, 0.427063, 0.502983, + 0.578550, 0.653770, 0.728642, 0.803171, 0.877363, 0.951217, 0.975265, 0.902075, + 0.829214, 0.756678, 0.684464, 0.612568, 0.540990, 0.469724, 0.398771, 0.328122, + 0.257783, 0.187744, 0.118006, 0.048568, 0.024735, 0.097925, 0.170786, 0.243322, + 0.315536, 0.387432, 0.459010, 0.530276, 0.601229, 0.671878, 0.742217, 0.812256, + 0.881994, 0.951432, 0.979420, 0.910569, 0.842006, 0.773731, 0.705741, 0.638033, + 0.570609, 0.503462, 0.436589, 0.369992, 0.303666, 0.237607, 0.171819, 0.106294, + 0.041031, 0.020580, 0.089431, 0.157994, 0.226269, 0.294259, 0.361967, 0.429391, + 0.496538, 0.563411, 0.630008, 0.696334, 0.762393, 0.828181, 0.893706, 0.958969, + 0.976030, 0.911284, 0.846800, 0.782567, 0.718590, 0.654862, 0.591382, 0.528149, + 0.465160, 0.402415, 0.339911, 0.277645, 0.215619, 0.153826, 0.092268, 0.030940, + 0.023970, 0.088716, 0.153200, 0.217433, 0.281410, 0.345138, 0.408618, 0.471851, + 0.534840, 0.597585, 0.660089, 0.722355, 0.784381, 0.846174, 0.907732, 0.969060, + 0.969846, 0.908978, 0.848337, 0.787923, 0.727731, 0.667760, 0.608011, 0.548480, + 0.489164, 0.430068, 0.371181, 0.312508, 0.254047, 0.195794, 0.137752, 0.079911, + 0.022278, 0.030154, 0.091022, 0.151663, 0.212077, 0.272269, 0.332240, 0.391989, + 0.451520, 0.510836, 0.569932, 0.628819, 0.687492, 0.745953, 0.804206, 0.862248, + 0.920089, 0.977722, 0.964850, 0.907622, 0.850595, 0.793766, 0.737137, 0.680703, + 0.624462, 0.568418, 0.512565, 0.456902, 0.401430, 0.346147, 0.291052, 0.236140, + 0.181418, 0.126876, 0.072514, 0.018335, 0.035150, 0.092378, 0.149405, 0.206234, + 0.262863, 0.319297, 0.375538, 0.431582, 0.487435, 0.543098, 0.598570, 0.653853, + 0.708948, 0.763860, 0.818582, 0.873124, 0.927486, 0.981665, 0.964335, 0.910516, + 0.856873, 0.803406, 0.750115, 0.697001, 0.644056, 0.591280, 0.538680, 0.486246, + 0.433981, 0.381885, 0.329955, 0.278190, 0.226588, 0.175151, 0.123876, 0.072760, + 0.021803, 0.035665, 0.089484, 0.143127, 0.196594, 0.249885, 0.302999, 0.355944, + 0.408720, 0.461320, 0.513754, 0.566019, 0.618115, 0.670045, 0.721810, 0.773412, + 0.824849, 0.876124, 0.927240, 0.978197, 0.971011, 0.920371, 0.869893, 0.819566, + 0.769398, 0.719382, 0.669520, 0.619811, 0.570252, 0.520846, 0.471587, 0.422477, + 0.373521, 0.324703, 0.276036, 0.227514, 0.179133, 0.130900, 0.082801, 0.034854, + 0.028989, 0.079629, 0.130107, 0.180434, 0.230602, 0.280618, 0.330480, 0.380189, + 0.429748, 0.479154, 0.528413, 0.577523, 0.626479, 0.675297, 0.723963, 0.772485, + 0.820867, 0.869099, 0.917199, 0.965146, 0.987044, 0.939371, 0.891843, 0.844449, + 0.797192, 0.750076, 0.703094, 0.656249, 0.609535, 0.562955, 0.516509, 0.470197, + 0.424015, 0.377967, 0.332042, 0.286248, 0.240584, 0.195051, 0.149644, 0.104361, + 0.059205, 0.014172, 0.012956, 0.060629, 0.108157, 0.155551, 0.202808, 0.249924, + 0.296906, 0.343751, 0.390465, 0.437045, 0.483491, 0.529803, 0.575985, 0.622033, + 0.667958, 0.713752, 0.759416, 0.804949, 0.850356, 0.895639, 0.940795, 0.985828, + 0.969266, 0.924480, 0.879821, 0.835282, 0.790866, 0.746570, 0.702390, 0.658337, + 0.614400, 0.570587, 0.526880, 0.483299, 0.439831, 0.396480, 0.353244, 0.310122, + 0.267112, 0.224219, 0.181438, 0.138767, 0.096209, 0.053763, 0.011426, 0.030734, + 0.075520, 0.120179, 0.164718, 0.209134, 0.253430, 0.297610, 0.341663, 0.385600, + 0.429413, 0.473120, 0.516701, 0.560169, 0.603520, 0.646756, 0.689878, 0.732888, + 0.775781, 0.818561, 0.861233, 0.903791, 0.946237, 0.988574, 0.969199, 0.927085, + 0.885076, 0.843173, 0.801383, 0.759699, 0.718120, 0.676647, 0.635276, 0.594018, + 0.552855, 0.511802, 0.470854, 0.430005, 0.389258, 0.348613, 0.308071, 0.267627, + 0.227285, 0.187042, 0.146902, 0.106856, 0.066913, 0.027065, 0.030801, 0.072915, + 0.114924, 0.156827, 0.198617, 0.240301, 0.281880, 0.323353, 0.364724, 0.405982, + 0.447145, 0.488198, 0.529146, 0.569995, 0.610742, 0.651387, 0.691929, 0.732373, + 0.772715, 0.812958, 0.853098, 0.893144, 0.933087, 0.972935, 0.987312, 0.947661, + 0.908102, 0.868641, 0.829276, 0.790006, 0.750827, 0.711748, 0.672759, 0.633863, + 0.595061, 0.556352, 0.517734, 0.479207, 0.440769, 0.402426, 0.364170, 0.326004, + 0.287928, 0.249944, 0.212045, 0.174234, 0.136512, 0.098873, 0.061327, 0.023861, + 0.012688, 0.052339, 0.091898, 0.131359, 0.170724, 0.209994, 0.249173, 0.288252, + 0.327241, 0.366137, 0.404939, 0.443648, 0.482266, 0.520793, 0.559231, 0.597574, + 0.635830, 0.673997, 0.712072, 0.750055, 0.787955, 0.825766, 0.863488, 0.901127, + 0.938673, 0.976139, 0.986487, 0.949197, 0.911989, 0.874872, 0.837837, 0.800882, + 0.764015, 0.727233, 0.690529, 0.653909, 0.617374, 0.580920, 0.544543, 0.508251, + 0.472040, 0.435906, 0.399858, 0.363886, 0.327992, 0.292180, 0.256448, 0.220790, + 0.185214, 0.149711, 0.114290, 0.078942, 0.043669, 0.008480, 0.013513, 0.050803, + 0.088011, 0.125128, 0.162163, 0.199118, 0.235985, 0.272767, 0.309471, 0.346091, + 0.382626, 0.419080, 0.455457, 0.491749, 0.527960, 0.564094, 0.600142, 0.636114, + 0.672008, 0.707820, 0.743552, 0.779209, 0.814786, 0.850289, 0.885710, 0.921058, + 0.956331, 0.991520, 0.973362, 0.938321, 0.903354, 0.868462, 0.833643, 0.798902, + 0.764231, 0.729638, 0.695119, 0.660670, 0.626296, 0.591992, 0.557765, 0.523602, + 0.489516, 0.455501, 0.421557, 0.387679, 0.353879, 0.320142, 0.286480, 0.252884, + 0.219359, 0.185901, 0.152516, 0.119196, 0.085945, 0.052758, 0.019646, 0.026638, + 0.061679, 0.096646, 0.131538, 0.166357, 0.201098, 0.235769, 0.270362, 0.304881, + 0.339330, 0.373704, 0.408008, 0.442235, 0.476398, 0.510484, 0.544499, 0.578443, + 0.612321, 0.646121, 0.679858, 0.713520, 0.747116, 0.780641, 0.814099, 0.847484, + 0.880804, 0.914055, 0.947242, 0.980354, 0.986596, 0.953617, 0.920698, 0.887850, + 0.855068, 0.822354, 0.789703, 0.757115, 0.724598, 0.692141, 0.659750, 0.627424, + 0.595164, 0.562964, 0.530827, 0.498758, 0.466751, 0.434802, 0.402923, 0.371096, + 0.339340, 0.307644, 0.276012, 0.244436, 0.212923, 0.181470, 0.150081, 0.118751, + 0.087482, 0.056272, 0.025123, 0.013404, 0.046383, 0.079302, 0.112150, 0.144932, + 0.177646, 0.210297, 0.242885, 0.275402, 0.307859, 0.340250, 0.372576, 0.404836, + 0.437036, 0.469173, 0.501242, 0.533248, 0.565198, 0.597077, 0.628904, 0.660660, + 0.692356, 0.723988, 0.755564, 0.787077, 0.818530, 0.849919, 0.881249, 0.912518, + 0.943728, 0.974877, 0.994029, 0.962996, 0.932026, 0.901112, 0.870255, 0.839461, + 0.808724, 0.778043, 0.747418, 0.716850, 0.686345, 0.655893, 0.625501, 0.595162, + 0.564883, 0.534657, 0.504490, 0.474377, 0.444316, 0.414319, 0.384371, 0.354479, + 0.324641, 0.294862, 0.265133, 0.235460, 0.205843, 0.176276, 0.146765, 0.117307, + 0.087898, 0.058546, 0.029247 +}; + +const int lin2mel_513x40_filter_starts[40] = { + 1, 3, 6, 10, 13, 17, 20, 25, 29, 34, + 39, 44, 49, 55, 62, 68, 75, 83, 91, 100, + 109, 119, 129, 140, 152, 164, 177, 191, 206, 222, + 239, 257, 276, 296, 318, 341, 365, 391, 419, 448 +}; + +const int lin2mel_513x40_filter_lens[40] = { + 5, 7, 7, 7, 7, 8, 9, 9, 10, 10, + 10, 11, 13, 13, 13, 15, 16, 17, 18, 19, + 20, 21, 23, 24, 25, 27, 29, 31, 33, 35, + 37, 39, 42, 45, 47, 50, 54, 57, 60, 64 + }; + + +const int16_t test_wav_long[160000] = { +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +573, 642, 705, 763, 800, 821, 834, 840, 858, 874, +879, 891, 888, 855, 814, 770, 728, 699, 671, 635, +585, 523, 458, 382, 301, 239, 189, 156, 128, 87, +40, -8, -50, -79, -108, -136, -164, -200, -238, -265, +-280, -270, -238, -213, -200, -215, -240, -255, -265, -265, +-249, -230, -191, -141, -116, -105, -101, -108, -104, -82, +-65, -48, -40, -44, -44, -43, -26, 8, 18, 5, +-22, -58, -64, -39, 1, 25, 13, -20, -57, -85, +-93, -94, -105, -123, -155, -184, -199, -200, -194, -204, +-233, -272, -302, -299, -279, -261, -249, -245, -252, -252, +-235, -214, -194, -172, -150, -130, -104, -74, -35, -7, +1, 8, 18, 34, 72, 117, 154, 198, 243, 277, +292, 280, 253, 223, 203, 204, 227, 246, 247, 243, +229, 202, 188, 181, 166, 143, 118, 94, 86, 101, +123, 128, 99, 49, 6, -22, -34, -32, -34, -47, +-59, -67, -67, -59, -50, -44, -54, -77, -98, -105, +-94, -84, -84, -97, -119, -133, -128, -125, -133, -138, +-138, -128, -101, -76, -59, -54, -72, -82, -82, -81, +-52, -22, -18, -20, -22, -12, 3, 25, 48, 42, +20, 13, 23, 47, 72, 90, 104, 106, 101, 107, +110, 104, 111, 121, 123, 121, 122, 124, 123, 121, +110, 98, 97, 103, 107, 99, 82, 68, 64, 66, +63, 46, 25, 5, -13, -30, -44, -48, -49, -52, +-65, -81, -93, -98, -94, -91, -103, -125, -134, -134, +-130, -122, -115, -111, -117, -124, -122, -125, -113, -87, +-75, -76, -84, -89, -78, -58, -44, -33, -33, -32, +-17, -15, -19, -10, -8, -7, -1, 0, 4, 11, +5, -6, -23, -35, -24, -11, -14, -23, -32, -45, +-42, -34, -35, -39, -60, -84, -94, -99, -84, -71, +-86, -106, -121, -136, -129, -111, -106, -106, -113, -125, +-126, -119, -100, -81, -82, -88, -92, -94, -74, -51, +-40, -32, -38, -56, -59, -52, -28, 8, 29, 45, +43, 25, 35, 49, 59, 97, 109, 94, 99, 85, +77, 116, 148, 171, 176, 150, 137, 137, 147, 172, +177, 166, 159, 138, 133, 150, 156, 159, 147, 111, +84, 71, 69, 80, 66, 47, 44, 28, 29, 42, +29, 10, -13, -40, -37, -16, -5, 4, -5, -38, +-64, -79, -77, -59, -49, -40, -40, -59, -59, -44, +-33, -31, -40, -56, -65, -60, -47, -32, -30, -31, +-33, -49, -54, -52, -49, -36, -33, -34, -19, -9, +-9, -13, -38, -67, -78, -85, -77, -74, -94, -115, +-140, -172, -194, -210, -230, -250, -283, -326, -365, -392, +-408, -420, -447, -485, -526, -560, -577, -587, -605, -626, +-646, -668, -687, -703, -712, -714, -716, -717, -719, -716, +-699, -667, -633, -601, -567, -537, -501, -458, -423, -394, +-365, -329, -285, -230, -167, -106, -48, 9, 60, 108, +162, 219, 266, 309, 348, 386, 436, 496, 556, 606, +633, 656, 674, 697, 749, 809, 858, 891, 905, 902, +903, 922, 950, 982, 1005, 1007, 999, 988, 991, 1012, +1015, 979, 919, 844, 787, 779, 803, 825, 818, 763, +672, 584, 527, 526, 552, 551, 504, 406, 296, 225, +208, 226, 234, 209, 153, 94, 60, 71, 111, 138, +120, 49, -44, -127, -177, -198, -215, -245, -296, -351, +-391, -400, -376, -356, -369, -413, -480, -535, -572, -601, +-662, -831, -1027, -1192, -1322, -1340, -1285, -1253, -1245, -1269, +-1321, -1363, -1392, -1374, -1332, -1366, -1472, -1593, -1700, -1718, +-1640, -1557, -1515, -1518, -1540, -1508, -1417, -1298, -1165, -1074, +-1046, -1049, -1057, -1034, -947, -830, -726, -657, -617, -549, +-425, -269, -110, 1, 55, 93, 142, 223, 335, 457, +570, 658, 716, 767, 840, 947, 1074, 1175, 1237, 1281, +1317, 1380, 1476, 1556, 1615, 1647, 1647, 1652, 1683, 1740, +1822, 1889, 1926, 1932, 1895, 1859, 1847, 1832, 1831, 1833, +1791, 1735, 1679, 1610, 1564, 1534, 1472, 1391, 1275, 1122, +968, 812, 655, 519, 387, 248, 112, -40, -192, -309, +-416, -518, -623, -755, -886, -1012, -1134, -1236, -1325, -1409, +-1478, -1543, -1595, -1618, -1608, -1559, -1491, -1424, -1360, -1304, +-1242, -1163, -1081, -997, -917, -848, -784, -711, -632, -543, +-448, -374, -288, -209, -176, -213, -347, -484, -541, -526, +-418, -303, -281, -325, -431, -587, -731, -819, -838, -842, +-933, -1120, -1336, -1505, -1537, -1454, -1391, -1428, -1542, -1667, +-1717, -1657, -1525, -1373, -1280, -1283, -1339, -1386, -1342, -1163, +-916, -699, -574, -528, -460, -297, -50, 220, 414, 509, +564, 621, 758, 978, 1225, 1466, 1630, 1696, 1727, 1764, +1854, 2023, 2189, 2283, 2318, 2313, 2331, 2409, 2519, 2612, +2660, 2656, 2631, 2589, 2548, 2539, 2539, 2531, 2499, 2417, +2314, 2218, 2123, 2028, 1889, 1701, 1496, 1281, 1069, 879, +689, 492, 299, 106, -81, -262, -450, -644, -833, -1025, +-1208, -1378, -1545, -1692, -1816, -1923, -2003, -2060, -2077, -2057, +-2009, -1959, -1905, -1853, -1860, -1860, -1793, -1691, -1580, -1474, +-1348, -1209, -1056, -883, -707, -526, -371, -264, -240, -289, +-338, -370, -361, -303, -264, -270, -311, -408, -551, -709, +-866, -990, -1104, -1266, -1454, -1665, -1855, -1950, -1982, -1994, +-2006, -2039, -2065, -2040, -1960, -1823, -1652, -1479, -1323, -1195, +-1086, -938, -731, -473, -187, 56, 247, 415, 578, 769, +970, 1130, 1232, 1268, 1256, 1237, 1227, 1252, 1330, 1426, +1545, 1656, 1693, 1725, 1756, 1772, 1857, 1974, 2077, 2201, +2321, 2440, 2576, 2692, 2843, 3028, 3161, 3302, 3391, 3385, +3378, 3332, 3242, 3140, 2954, 2673, 2324, 1869, 1368, 865, +339, -150, -612, -1086, -1521, -1911, -2244, -2460, -2576, -2633, +-2648, -2661, -2651, -2560, -2404, -2187, -1933, -1691, -1449, -1187, +-921, -638, -331, -32, 237, 440, 568, 645, 684, 702, +707, 659, 555, 410, 240, 86, -42, -160, -277, -404, +-549, -689, -859, -1126, -1536, -2099, -2656, -3096, -3385, -3460, +-3429, -3410, -3335, -3227, -3112, -2947, -2740, -2474, -2177, -1968, +-1835, -1764, -1734, -1596, -1381, -1213, -1111, -1104, -1153, -1149, +-1100, -1017, -907, -855, -856, -892, -981, -1019, -925, -726, +-436, -145, 66, 237, 425, 650, 910, 1126, 1232, 1245, +1185, 1129, 1164, 1300, 1549, 1881, 2189, 2416, 2551, 2631, +2746, 2929, 3095, 3190, 3198, 3139, 3106, 3108, 3142, 3191, +3219, 3283, 3383, 3430, 3439, 3422, 3361, 3295, 3178, 2919, +2540, 2053, 1485, 908, 279, -391, -1028, -1621, -2108, -2442, +-2697, -2850, -2870, -2797, -2602, -2326, -2038, -1683, -1280, -874, +-448, -75, 221, 504, 747, 931, 1058, 1076, 1015, 916, +749, 528, 257, -81, -417, -723, -1014, -1263, -1466, -1608, +-1650, -1615, -1539, -1422, -1289, -1113, -907, -790, -844, -1125, +-1586, -2063, -2463, -2749, -2884, -2929, -2907, -2780, -2619, -2469, +-2309, -2138, -1943, -1774, -1701, -1691, -1728, -1744, -1657, -1538, +-1470, -1450, -1483, -1534, -1559, -1561, -1532, -1470, -1393, -1302, +-1205, -1118, -970, -709, -361, 45, 425, 712, 934, 1118, +1280, 1406, 1458, 1436, 1352, 1227, 1148, 1173, 1324, 1605, +1935, 2242, 2487, 2626, 2717, 2786, 2829, 2906, 2994, 3066, +3166, 3252, 3363, 3532, 3688, 3861, 4016, 4102, 4194, 4267, +4275, 4211, 3998, 3647, 3218, 2700, 2108, 1400, 495, -535, +-1610, -2620, -3391, -3886, -4125, -4085, -3840, -3435, -2873, -2236, +-1525, -746, -12, 633, 1121, 1393, 1539, 1618, 1660, 1675, +1598, 1391, 1088, 686, 220, -255, -746, -1225, -1657, -2075, +-2438, -2692, -2807, -2692, -2368, -1926, -1410, -912, -476, -55, +307, 499, 436, -20, -833, -1772, -2643, -3186, -3315, -3232, +-3041, -2868, -2853, -2865, -2858, -2836, -2710, -2572, -2467, -2381, +-2361, -2280, -2051, -1755, -1420, -1169, -1148, -1273, -1459, -1630, +-1663, -1584, -1456, -1291, -1161, -1049, -860, -589, -208, 263, +679, 944, 1034, 958, 846, 800, 812, 860, 885, 861, +856, 895, 1048, 1358, 1775, 2284, 2751, 3084, 3293, 3379, +3424, 3504, 3573, 3639, 3660, 3614, 3563, 3485, 3434, 3431, +3417, 3417, 3384, 3266, 3162, 3065, 2990, 2942, 2840, 2601, +2208, 1709, 1153, 558, -37, -643, -1254, -1792, -2230, -2538, +-2695, -2700, -2571, -2349, -2058, -1689, -1203, -590, 72, 697, +1148, 1378, 1459, 1415, 1280, 1087, 811, 467, 73, -366, +-812, -1239, -1588, -1816, -1955, -2043, -2100, -2128, -2086, -1906, +-1590, -1185, -760, -356, -12, 289, 502, 514, 240, -521, +-1695, -3021, -4221, -4854, -4880, -4532, -3936, -3479, -3215, -2942, +-2773, -2553, -2212, -1930, -1655, -1498, -1520, -1544, -1554, -1461, +-1242, -1160, -1304, -1600, -2020, -2329, -2355, -2182, -1845, -1458, +-1148, -870, -634, -379, 23, 501, 968, 1338, 1450, 1312, +1055, 787, 615, 569, 601, 684, 763, 829, 938, 1126, +1418, 1820, 2284, 2652, 2832, 2880, 2832, 2816, 3024, 3383, +3747, 4006, 3996, 3781, 3438, 3073, 2867, 2734, 2668, 2807, +3063, 3428, 3948, 4523, 5099, 5602, 5953, 6009, 5557, 4561, +3023, 1026, -1120, -3102, -4669, -5652, -6034, -5892, -5359, -4583, +-3632, -2597, -1581, -634, 191, 844, 1303, 1652, 1969, 2292, +2633, 2926, 3052, 2895, 2427, 1664, 649, -493, -1625, -2660, +-3517, -4125, -4431, -4409, -4069, -3428, -2585, -1701, -885, -225, +200, 345, 124, -461, -1271, -2050, -2506, -2606, -2492, -2303, +-2231, -2291, -2406, -2642, -2973, -3322, -3631, -3769, -3725, -3564, +-3272, -2882, -2392, -1838, -1430, -1278, -1348, -1575, -1768, -1803, +-1718, -1534, -1261, -946, -611, -317, -126, -1, 97, 184, +246, 206, 64, -76, -111, -6, 176, 357, 486, 561, +653, 782, 894, 1009, 1079, 1092, 1133, 1178, 1351, 1742, +2289, 2981, 3621, 4008, 4133, 3976, 3646, 3281, 2879, 2526, +2284, 2150, 2199, 2443, 2761, 3113, 3447, 3619, 3642, 3531, +3250, 2900, 2521, 2214, 2223, 2643, 3488, 4605, 5478, 5655, +4908, 3218, 961, -1343, -3251, -4450, -4989, -4956, -4437, -3708, +-2810, -1784, -822, 67, 771, 1132, 1152, 870, 548, 457, +667, 1146, 1667, 1942, 1850, 1403, 658, -279, -1264, -2197, +-3005, -3660, -4127, -4357, -4299, -3864, -3019, -1967, -1076, -652, +-895, -1659, -2517, -3105, -3208, -2915, -2473, -1996, -1622, -1385, +-1251, -1302, -1495, -1782, -2214, -2762, -3406, -4012, -4319, -4192, +-3669, -2971, -2384, -2065, -1987, -2021, -2057, -2024, -1894, -1662, +-1342, -1004, -690, -407, -116, 255, 651, 927, 946, 647, +166, -289, -569, -586, -385, -49, 347, 731, 1034, 1215, +1304, 1312, 1254, 1175, 1021, 862, 846, 1009, 1457, 2163, +2895, 3579, 4040, 4150, 4043, 3694, 3218, 2859, 2595, 2548, +2761, 3075, 3510, 3950, 4320, 4646, 4836, 4951, 5018, 5033, +5082, 5113, 5098, 5066, 5064, 5034, 4754, 3938, 2313, -52, +-2693, -5054, -6586, -7123, -6826, -5883, -4615, -3234, -1864, -674, +335, 1228, 1972, 2474, 2634, 2443, 2033, 1679, 1547, 1587, +1608, 1360, 739, -221, -1430, -2688, -3808, -4618, -4956, -4837, +-4422, -3847, -3176, -2384, -1421, -380, 535, 1078, 1036, 337, +-865, -2233, -3437, -4103, -4143, -3789, -3229, -2804, -2694, -2768, +-3060, -3384, -3550, -3694, -3657, -3422, -3142, -2685, -2148, -1657, +-1188, -935, -977, -1267, -1801, -2310, -2555, -2533, -2175, -1588, +-1031, -553, -223, -93, -45, -35, -20, 30, 18, -43, +-126, -223, -201, -38, 196, 445, 602, 633, 556, 444, +411, 509, 738, 1051, 1392, 1742, 2075, 2458, 2916, 3386, +3908, 4356, 4586, 4558, 4199, 3605, 2953, 2412, 2102, 2004, +2036, 2175, 2429, 2787, 3267, 3794, 4244, 4567, 4782, 4890, +4964, 5107, 5313, 5524, 5704, 5833, 5762, 5294, 4182, 2204, +-478, -3362, -5824, -7300, -7690, -7172, -5990, -4575, -3154, -1819, +-778, 32, 751, 1373, 1917, 2287, 2378, 2260, 2069, 1942, +1897, 1754, 1334, 603, -429, -1678, -2929, -4051, -4872, -5169, +-4961, -4412, -3713, -3017, -2324, -1588, -880, -436, -482, -1071, +-1984, -2844, -3408, -3506, -3196, -2727, -2226, -1871, -1848, -2133, +-2603, -3020, -3218, -3159, -2924, -2752, -2677, -2602, -2490, -2291, +-2099, -1996, -1999, -2125, -2260, -2380, -2481, -2367, -1946, -1306, +-569, 47, 401, 547, 593, 653, 685, 629, 525, 373, +201, 74, 31, 111, 325, 610, 833, 868, 710, 477, +311, 309, 540, 944, 1403, 1938, 2543, 3118, 3638, 3974, +4080, 4031, 3860, 3737, 3690, 3663, 3728, 3740, 3599, 3385, +3095, 2893, 2890, 3054, 3403, 3760, 4116, 4563, 4992, 5454, +5887, 6167, 6304, 6239, 5909, 5137, 3740, 1717, -748, -3233, +-5270, -6520, -6924, -6630, -5777, -4646, -3498, -2406, -1479, -690, +76, 821, 1510, 2016, 2295, 2405, 2364, 2241, 2042, 1681, +1097, 311, -608, -1652, -2731, -3679, -4365, -4651, -4495, -4030, +-3428, -2809, -2191, -1589, -1102, -855, -1021, -1655, -2569, -3456, +-3999, -3991, -3430, -2529, -1669, -1150, -1124, -1623, -2428, -3168, +-3599, -3633, -3330, -2915, -2606, -2494, -2560, -2707, -2876, -2988, +-2978, -2911, -2800, -2622, -2392, -2046, -1521, -843, -138, 412, +719, 746, 566, 365, 240, 204, 245, 290, 273, 183, +40, -77, -98, -30, 139, 358, 499, 575, 601, 612, +767, 1042, 1420, 1928, 2403, 2849, 3242, 3479, 3676, 3809, +3854, 3907, 3843, 3716, 3666, 3588, 3611, 3752, 3788, 3784, +3708, 3505, 3382, 3344, 3454, 3879, 4464, 5209, 6031, 6596, +6949, 7086, 6837, 6051, 4371, 1583, -1968, -5504, -8129, -9266, +-8902, -7453, -5480, -3524, -2023, -1122, -752, -673, -409, 285, +1286, 2358, 3147, 3441, 3354, 3040, 2573, 1992, 1203, 151, +-1076, -2447, -3872, -5121, -5923, -5988, -5246, -4035, -2822, -1920, +-1476, -1429, -1637, -2085, -2639, -3014, -3090, -2823, -2340, -1949, +-1703, -1594, -1672, -1856, -2211, -2734, -3208, -3532, -3594, -3445, +-3268, -3067, -2919, -2843, -2741, -2730, -2839, -2929, -2935, -2762, +-2414, -2031, -1649, -1274, -863, -374, 60, 360, 558, 668, +733, 755, 632, 363, 96, -71, -113, -37, 78, 203, +342, 481, 574, 516, 370, 272, 257, 445, 835, 1322, +1911, 2556, 3218, 3829, 4262, 4576, 4769, 4808, 4854, 4766, +4329, 3691, 2928, 2213, 1818, 1723, 1908, 2287, 2751, 3349, +3877, 4216, 4597, 5026, 5611, 6509, 7427, 8146, 8656, 8845, +8380, 6896, 4185, 321, -3974, -7582, -9706, -10185, -9341, -7617, +-5585, -3802, -2407, -1515, -1168, -830, -98, 985, 2291, 3470, +4177, 4372, 4243, 3915, 3297, 2325, 1102, -286, -1758, -3181, +-4536, -5703, -6307, -6080, -5219, -4152, -3176, -2587, -2462, -2561, +-2799, -3137, -3316, -3091, -2511, -1808, -1161, -831, -959, -1307, +-1709, -2127, -2483, -2743, -2866, -2965, -3074, -3119, -3300, -3522, +-3505, -3376, -3187, -2963, -2872, -2863, -2797, -2568, -2182, -1755, +-1247, -669, -159, 297, 623, 756, 837, 932, 1026, 1014, +832, 555, 233, -5, -60, -34, 45, 217, 365, 436, +404, 277, 199, 274, 594, 1127, 1706, 2295, 2806, 3108, +3233, 3228, 3157, 3119, 3212, 3465, 3743, 3950, 4053, 4025, +3892, 3777, 3735, 3637, 3564, 3588, 3611, 3694, 3871, 4122, +4490, 4992, 5598, 6189, 6654, 7082, 7477, 7426, 6544, 4546, +1234, -2701, -6212, -8618, -9360, -8579, -6834, -4641, -2785, -1606, +-1127, -1327, -1522, -1161, -287, 1137, 2717, 3821, 4397, 4470, +4042, 3308, 2346, 1206, 27, -1162, -2397, -3689, -4927, -5757, +-5848, -5286, -4397, -3510, -3072, -3195, -3586, -4212, -4842, -4913, +-4323, -3173, -1686, -457, 109, -13, -618, -1410, -2172, -2614, +-2671, -2576, -2426, -2421, -2800, -3439, -4052, -4439, -4499, -4210, +-3723, -3301, -3017, -2756, -2493, -2179, -1681, -1033, -357, 311, +884, 1182, 1209, 1154, 1071, 984, 915, 744, 433, 103, +-132, -259, -279, -132, 174, 536, 855, 949, 742, 421, +221, 324, 811, 1587, 2498, 3325, 3826, 3955, 3720, 3261, +2896, 2805, 3021, 3452, 3826, 3960, 3860, 3551, 3233, 3091, +3084, 3325, 3795, 4226, 4601, 4788, 4676, 4602, 4719, 5073, +5757, 6507, 7183, 7779, 7825, 6891, 4734, 1217, -2871, -6466, +-8866, -9475, -8592, -6834, -4609, -2732, -1581, -1104, -1310, -1603, +-1347, -479, 973, 2651, 3968, 4724, 4927, 4592, 3815, 2693, +1346, -66, -1402, -2653, -3884, -4986, -5714, -5804, -5239, -4422, +-3720, -3385, -3587, -4102, -4691, -5222, -5223, -4404, -3000, -1326, +50, 608, 395, -348, -1330, -2167, -2651, -2702, -2416, -2119, +-2066, -2427, -3219, -4067, -4634, -4819, -4522, -3938, -3363, -2867, +-2487, -2194, -1884, -1488, -913, -206, 490, 1079, 1358, 1297, +1142, 997, 885, 837, 733, 519, 267, 16, -208, -363, +-327, -52, 364, 731, 870, 711, 349, 128, 248, 693, +1461, 2346, 3079, 3540, 3639, 3409, 2997, 2651, 2621, 2819, +3121, 3534, 3793, 3795, 3792, 3699, 3569, 3688, 3925, 4227, +4470, 4493, 4337, 4018, 3937, 4307, 4964, 5980, 7140, 8063, +8795, 8958, 7815, 5261, 1385, -3181, -7067, -9428, -9897, -8676, +-6487, -3962, -2061, -1246, -1308, -2113, -2814, -2627, -1550, 356, +2626, 4545, 5765, 6116, 5652, 4593, 3088, 1485, 50, -1272, +-2441, -3521, -4571, -5322, -5491, -5142, -4587, -4065, -3847, -4079, +-4569, -5109, -5558, -5501, -4583, -3105, -1491, -190, 274, 5, +-701, -1615, -2301, -2651, -2596, -2160, -1864, -1922, -2375, -3280, +-4159, -4667, -4803, -4515, -3994, -3487, -3074, -2851, -2715, -2519, +-2191, -1573, -751, 82, 803, 1235, 1380, 1356, 1267, 1164, +1031, 850, 631, 441, 312, 220, 184, 239, 377, 535, +584, 429, 194, 35, 79, 463, 1016, 1582, 2104, 2406, +2546, 2583, 2560, 2698, 2959, 3316, 3759, 4036, 4136, 4144, +4031, 3936, 3980, 4153, 4450, 4783, 5017, 5135, 5056, 4824, +4705, 4717, 4942, 5538, 6216, 6854, 7410, 7307, 6141, 3738, +147, -3842, -7269, -9280, -9467, -8154, -5810, -3281, -1466, -585, +-674, -1449, -2118, -2090, -1187, 493, 2536, 4279, 5275, 5476, +4904, 3662, 2105, 530, -891, -2023, -2953, -3793, -4549, -5085, +-5154, -4848, -4355, -3773, -3367, -3263, -3372, -3681, -4089, -4258, +-3927, -3153, -2165, -1267, -772, -792, -1253, -1991, -2766, -3378, +-3590, -3340, -2969, -2677, -2565, -2837, -3309, -3699, -3995, -4087, +-3896, -3544, -3159, -2829, -2544, -2292, -2031, -1588, -998, -408, +154, 565, 741, 792, 778, 715, 667, 660, 670, 635, +524, 357, 135, -15, 34, 197, 406, 633, 739, 728, +710, 702, 809, 1115, 1623, 2302, 2963, 3471, 3742, 3706, +3511, 3273, 3007, 2883, 2959, 3148, 3440, 3666, 3749, 3789, +3785, 3826, 3961, 4118, 4326, 4610, 4966, 5493, 6174, 6920, +7680, 8315, 8792, 8766, 7700, 5418, 1808, -2583, -6548, -9277, +-10244, -9430, -7445, -5091, -3216, -2218, -2202, -2956, -3583, -3409, +-2270, -90, 2601, 4904, 6409, 6943, 6436, 5129, 3422, 1676, +147, -946, -1721, -2517, -3396, -4238, -4874, -5199, -5253, -5141, +-5026, -4991, -4967, -5101, -5420, -5439, -4971, -3995, -2507, -1061, +-134, 220, -43, -809, -1755, -2531, -2849, -2687, -2229, -1813, +-1837, -2386, -3246, -4181, -4929, -5205, -4986, -4466, -3788, -3150, +-2742, -2511, -2301, -1973, -1446, -719, 45, 610, 919, 1018, +956, 838, 749, 728, 758, 802, 770, 561, 290, 128, +151, 407, 766, 1004, 1068, 950, 686, 445, 391, 684, +1273, 2049, 2849, 3288, 3386, 3252, 2931, 2704, 2641, 2848, +3294, 3796, 4358, 4634, 4539, 4368, 4141, 4129, 4472, 4973, +5596, 6113, 6466, 6744, 6898, 7115, 7539, 7925, 7788, 6719, +4295, 545, -3679, -7403, -9767, -10202, -8846, -6388, -3830, -1991, +-1294, -1808, -2885, -3623, -3423, -1960, 559, 3334, 5527, 6768, +6862, 5824, 4116, 2223, 529, -578, -1129, -1542, -2093, -2890, +-3802, -4602, -5176, -5381, -5271, -5047, -4835, -4783, -5001, -5180, +-4883, -4069, -2786, -1307, -167, 363, 175, -691, -1874, -2982, +-3579, -3395, -2752, -2027, -1586, -1837, -2698, -3840, -4922, -5523, +-5446, -4747, -3677, -2665, -1991, -1774, -1964, -2223, -2272, -1994, +-1391, -648, 9, 482, 721, 729, 611, 518, 546, 662, +817, 904, 839, 761, 745, 809, 986, 1142, 1208, 1173, +977, 697, 498, 556, 998, 1762, 2620, 3248, 3451, 3356, +3029, 2624, 2481, 2597, 2988, 3733, 4544, 5179, 5534, 5618, +5465, 5127, 4893, 4859, 4993, 5497, 6282, 7094, 7921, 8657, +9123, 8912, 7726, 5411, 1786, -2477, -6348, -9181, -10264, -9405, +-7278, -4765, -2726, -1703, -1910, -2957, -3937, -4205, -3242, -878, +2198, 5049, 7083, 7924, 7413, 5841, 3724, 1566, -126, -1031, +-1396, -1695, -2109, -2730, -3577, -4488, -5268, -5828, -6074, -5945, +-5654, -5457, -5245, -4819, -4127, -3059, -1782, -694, 9, 221, +-159, -1027, -2029, -2826, -3174, -2975, -2446, -2006, -1908, -2275, +-3124, -4172, -5048, -5481, -5337, -4683, -3732, -2807, -2159, -1848, +-1837, -1935, -1903, -1665, -1242, -720, -208, 254, 592, 767, +821, 818, 836, 860, 829, 738, 603, 538, 594, 728, +899, 1034, 1154, 1234, 1235, 1245, 1233, 1266, 1477, 1722, +2101, 2650, 3206, 3827, 4270, 4380, 4208, 3765, 3325, 3082, +3173, 3689, 4449, 5332, 6125, 6553, 6677, 6539, 6328, 6308, +6554, 7109, 7902, 8777, 9111, 8339, 6189, 2475, -2098, -6351, +-9386, -10540, -9746, -7617, -5119, -3200, -2300, -2572, -3610, -4437, +-4401, -3108, -584, 2500, 5273, 7131, 7869, 7455, 6097, 4295, +2530, 1117, 242, -326, -987, -1885, -2954, -4031, -5023, -5768, +-6204, -6346, -6219, -6048, -5945, -5834, -5455, -4517, -3114, -1563, +-193, 653, 829, 320, -684, -1805, -2699, -2971, -2643, -2165, +-1827, -1902, -2558, -3591, -4673, -5495, -5787, -5454, -4611, -3601, +-2747, -2166, -1953, -1987, -1978, -1840, -1570, -1185, -791, -455, +-194, 7, 171, 307, 510, 743, 839, 789, 625, 440, +426, 640, 961, 1267, 1491, 1530, 1314, 906, 514, 358, +550, 1219, 2103, 2790, 3315, 3502, 3286, 2965, 2722, 2729, +3065, 3865, 4900, 5647, 6192, 6428, 6211, 5970, 5831, 5818, +6071, 6644, 7452, 8187, 8789, 9339, 9358, 8419, 6458, 3133, +-1279, -5590, -8871, -10575, -10382, -8491, -5897, -3710, -2340, -2169, +-3227, -4433, -4866, -4168, -2024, 1237, 4547, 7040, 8413, 8478, +7231, 5234, 3168, 1425, 321, -104, -379, -978, -1836, -2881, +-4166, -5389, -6245, -6749, -6810, -6402, -5830, -5441, -4985, -4151, +-3247, -2181, -945, -106, 303, 338, -157, -1021, -1920, -2393, +-2448, -2374, -2093, -2050, -2564, -3238, -4069, -4988, -5498, -5435, +-4910, -4119, -3290, -2610, -2326, -2295, -2234, -2207, -2069, -1654, +-1173, -737, -325, -33, 90, 153, 272, 429, 563, 704, +792, 802, 875, 1011, 1121, 1193, 1226, 1139, 909, 631, +311, 126, 280, 731, 1392, 2067, 2648, 3045, 3142, 3160, +3202, 3281, 3710, 4399, 5069, 5717, 6154, 6200, 6035, 5785, +5500, 5324, 5376, 5663, 5996, 6319, 6564, 6503, 6227, 6028, +5613, 4655, 3303, 1234, -1503, -4061, -6043, -7206, -7196, -6107, +-4544, -3224, -2336, -2126, -2751, -3356, -3357, -2672, -1092, 1170, +3388, 4947, 5744, 5687, 4715, 3334, 2098, 1118, 483, 207, +-106, -765, -1632, -2591, -3701, -4671, -5228, -5460, -5398, -5077, +-4708, -4508, -4286, -3836, -3356, -2756, -1944, -1317, -987, -912, +-1220, -1811, -2389, -2675, -2757, -2782, -2640, -2620, -2968, -3415, +-3942, -4554, -4857, -4699, -4295, -3772, -3210, -2796, -2643, -2609, +-2545, -2474, -2299, -1910, -1482, -1114, -743, -428, -188, 59, +350, 612, 800, 944, 988, 955, 945, 918, 931, 1032, +1139, 1248, 1286, 1187, 1044, 961, 1037, 1310, 1779, 2390, +2964, 3377, 3588, 3596, 3543, 3590, 3786, 4128, 4546, 4954, +5317, 5625, 5848, 6021, 6275, 6568, 6945, 7461, 7980, 8411, +8827, 9025, 8435, 6976, 4504, 949, -2838, -5986, -8041, -8658, +-7907, -6358, -4861, -3968, -3754, -4408, -5354, -5598, -4827, -2980, +-235, 2756, 5186, 6710, 7264, 6757, 5476, 4070, 2931, 2138, +1681, 1314, 717, -187, -1296, -2589, -3975, -5124, -5858, -6238, +-6304, -6121, -5799, -5331, -4637, -3810, -3044, -2331, -1693, -1276, +-1046, -960, -958, -967, -964, -912, -1048, -1488, -2042, -2791, +-3608, -4210, -4639, -4847, -4811, -4631, -4417, -4316, -4219, -4069, +-3866, -3427, -2859, -2319, -1788, -1358, -1088, -966, -941, -912, +-821, -583, -226, 67, 310, 547, 712, 804, 891, 953, +1019, 1115, 1207, 1254, 1190, 1176, 1241, 1302, 1435, 1613, +1847, 2111, 2403, 2718, 2869, 2997, 3234, 3478, 3869, 4425, +5057, 5740, 6336, 6793, 7033, 6979, 6878, 6810, 6797, 7020, +7484, 8107, 8886, 9534, 9319, 7850, 4956, 746, -3789, -7481, +-9615, -9836, -8379, -6082, -4001, -2942, -3138, -4371, -5887, -6601, +-5838, -3642, -454, 3001, 5784, 7374, 7756, 7017, 5539, 4067, +3022, 2412, 2140, 1838, 1212, 247, -1034, -2478, -3887, -5090, +-5897, -6365, -6683, -6838, -6743, -6260, -5240, -3851, -2472, -1334, +-726, -748, -1165, -1812, -2307, -2249, -1691, -918, -345, -325, +-1048, -2402, -3903, -5157, -5857, -5762, -5066, -4168, -3449, -3152, +-3266, -3628, -3911, -3861, -3508, -2932, -2263, -1702, -1354, -1177, +-1076, -952, -704, -357, -40, 151, 211, 240, 348, 604, +1022, 1515, 1945, 2166, 2067, 1650, 1057, 514, 243, 371, +859, 1547, 2256, 2775, 2986, 2949, 2826, 2786, 2941, 3381, +4010, 4587, 5195, 5789, 6180, 6505, 6785, 6984, 7130, 7389, +7696, 7968, 8400, 8988, 9584, 9614, 8608, 6269, 2407, -2142, +-6181, -8894, -9763, -8792, -6724, -4698, -3484, -3506, -4785, -6481, +-7535, -7132, -5042, -1783, 1828, 4932, 6852, 7435, 6897, 5562, +4125, 3202, 2873, 2917, 2947, 2634, 1820, 592, -896, -2450, +-3827, -4868, -5559, -6047, -6430, -6639, -6466, -5762, -4542, -3117, +-1886, -1136, -1065, -1519, -2212, -2787, -2819, -2230, -1230, -282, +99, -277, -1439, -3016, -4455, -5422, -5616, -5095, -4242, -3432, +-3015, -3093, -3472, -3878, -4036, -3861, -3450, -2914, -2424, -2082, +-1863, -1728, -1572, -1316, -969, -641, -442, -358, -304, -157, +225, 793, 1413, 1975, 2269, 2213, 1881, 1421, 1074, 1014, +1267, 1720, 2113, 2301, 2292, 2100, 1943, 2031, 2451, 3232, +4172, 5044, 5646, 5796, 5725, 5657, 5708, 6106, 6717, 7364, +7973, 8357, 8607, 8767, 8980, 9494, 9649, 8967, 7098, 3564, +-910, -5188, -8219, -9319, -8596, -6618, -4587, -3499, -3692, -5197, +-7214, -8482, -8043, -5707, -2132, 1704, 4780, 6468, 6783, 6007, +4642, 3466, 3019, 3323, 3964, 4295, 3952, 2872, 1280, -437, +-2001, -3224, -4060, -4599, -5020, -5523, -6041, -6289, -5985, -5027, +-3659, -2255, -1380, -1288, -1802, -2804, -3700, -3885, -3187, -1715, +-108, 944, 960, -191, -2021, -3962, -5430, -5902, -5384, -4258, +-3070, -2362, -2409, -3090, -4002, -4700, -4901, -4594, -3918, -3090, +-2328, -1761, -1430, -1283, -1196, -1098, -973, -860, -799, -703, +-452, 10, 616, 1236, 1720, 1928, 1866, 1573, 1155, 855, +831, 1134, 1695, 2312, 2792, 3009, 3005, 2885, 2729, 2684, +2861, 3196, 3654, 4217, 4742, 5241, 5752, 6225, 6608, 6872, +7006, 7069, 7247, 7594, 8192, 9022, 9936, 10423, 9831, 7828, +4207, -413, -4711, -7560, -8425, -7578, -5796, -4116, -3442, -4053, +-5739, -7721, -8900, -8392, -6089, -2765, 642, 3349, 4936, 5423, +5103, 4402, 3775, 3565, 3777, 4107, 4150, 3720, 2926, 1976, +1010, 59, -956, -2136, -3441, -4738, -5858, -6550, -6557, -5795, +-4473, -3072, -2091, -1831, -2392, -3442, -4451, -5057, -4858, -3759, +-2172, -636, 274, 253, -643, -2075, -3427, -4316, -4585, -4165, +-3349, -2524, -1979, -1925, -2310, -2948, -3609, -4058, -4276, -4255, +-3946, -3421, -2765, -2117, -1631, -1366, -1343, -1482, -1627, -1666, +-1432, -806, 120, 1127, 1949, 2380, 2358, 1999, 1493, 1085, +969, 1176, 1632, 2163, 2560, 2700, 2692, 2670, 2650, 2766, +3046, 3372, 3772, 4251, 4651, 4941, 5247, 5552, 5911, 6331, +6717, 7045, 7291, 7520, 7819, 8160, 8608, 9099, 9063, 8087, +5879, 2435, -1445, -4642, -6367, -6539, -5619, -4370, -3608, -3802, +-5006, -6785, -8314, -8712, -7438, -4829, -1774, 933, 2792, 3677, +3829, 3587, 3260, 3168, 3427, 3862, 4177, 4087, 3588, 2919, +2270, 1648, 910, -113, -1475, -2982, -4353, -5323, -5676, -5366, +-4512, -3450, -2705, -2549, -2919, -3615, -4211, -4429, -4206, -3575, +-2758, -1893, -1241, -1103, -1417, -2018, -2719, -3304, -3679, -3858, +-3853, -3622, -3174, -2700, -2426, -2401, -2612, -2996, -3388, -3675, +-3760, -3542, -3026, -2352, -1807, -1601, -1717, -1981, -2184, -2169, +-1856, -1300, -595, 148, 777, 1193, 1368, 1396, 1463, 1557, +1670, 1792, 1881, 1963, 2086, 2290, 2526, 2768, 2979, 3124, +3158, 3128, 3171, 3458, 4017, 4656, 5292, 5689, 5766, 5741, +5731, 5842, 6187, 6739, 7462, 8199, 8815, 9336, 9315, 8385, +6466, 3523, 136, -2753, -4470, -4864, -4356, -3588, -3119, -3445, +-4681, -6358, -7795, -8400, -7633, -5598, -3060, -705, 1085, 2180, +2667, 2770, 2717, 2729, 2866, 3070, 3300, 3393, 3279, 3154, +3043, 2778, 2180, 1093, -413, -2047, -3440, -4248, -4341, -3881, +-3148, -2485, -2281, -2672, -3412, -4252, -4866, -4986, -4724, -4146, +-3364, -2585, -1919, -1566, -1581, -1857, -2341, -2875, -3303, -3564, +-3565, -3231, -2643, -2060, -1751, -1835, -2252, -2851, -3383, -3606, +-3466, -2994, -2304, -1667, -1320, -1373, -1715, -2054, -2228, -2131, +-1753, -1263, -755, -303, 29, 281, 467, 655, 933, 1210, +1385, 1479, 1547, 1622, 1766, 2034, 2318, 2584, 2795, 2938, +2970, 2846, 2795, 2882, 3196, 3760, 4339, 4846, 5184, 5383, +5538, 5667, 5774, 5948, 6322, 6811, 7421, 8015, 8593, 8892, +8399, 6944, 4364, 1194, -1593, -3297, -3683, -3234, -2636, -2369, +-2782, -3928, -5531, -6884, -7399, -6763, -5070, -3081, -1358, -83, +772, 1429, 1907, 2185, 2372, 2471, 2499, 2467, 2396, 2380, +2542, 2852, 2951, 2509, 1425, -96, -1581, -2632, -3081, -2956, +-2507, -2011, -1730, -1891, -2438, -3080, -3447, -3459, -3337, -3249, +-3378, -3584, -3556, -3251, -2758, -2309, -2081, -2133, -2527, -3112, +-3613, -3726, -3293, -2492, -1672, -1223, -1263, -1588, -1979, -2255, +-2307, -2168, -1904, -1635, -1477, -1460, -1527, -1518, -1355, -1156, +-1054, -1082, -1122, -1027, -743, -284, 257, 701, 919, 978, +928, 761, 625, 677, 909, 1195, 1465, 1655, 1766, 1822, +1860, 2040, 2242, 2375, 2610, 2903, 3179, 3401, 3525, 3688, +3872, 4023, 4168, 4251, 4314, 4333, 4339, 4412, 4523, 4764, +5118, 5509, 5801, 5668, 4949, 3592, 1803, 118, -1029, -1434, +-1199, -763, -538, -794, -1561, -2616, -3588, -4061, -3903, -3263, +-2433, -1737, -1262, -936, -676, -365, -49, 194, 317, 257, +96, -37, -31, 184, 540, 836, 865, 555, -1, -622, +-1100, -1324, -1320, -1170, -1009, -950, -989, -1105, -1217, -1260, +-1265, -1276, -1441, -1771, -2120, -2373, -2394, -2213, -2009, -1942, +-2157, -2571, -3002, -3329, -3359, -3064, -2604, -2204, -2028, -2039, +-2155, -2316, -2301, -2072, -1829, -1644, -1513, -1428, -1461, -1524, +-1491, -1404, -1383, -1363, -1393, -1523, -1490, -1278, -1024, -751, +-452, -334, -407, -446, -388, -264, -102, 91, 227, 293, +340, 397, 474, 630, 861, 1076, 1229, 1332, 1444, 1571, +1734, 1917, 2050, 2162, 2255, 2292, 2345, 2385, 2437, 2533, +2664, 2904, 3207, 3534, 3881, 4179, 4462, 4712, 4941, 5164, +5073, 4539, 3574, 2349, 1286, 607, 370, 421, 438, 278, +-155, -912, -1779, -2483, -2814, -2783, -2577, -2325, -2150, -1965, +-1632, -1234, -840, -550, -441, -502, -705, -854, -767, -469, +-27, 397, 580, 426, 13, -455, -828, -977, -869, -643, +-437, -363, -428, -554, -660, -672, -640, -654, -735, -877, +-1050, -1175, -1281, -1441, -1650, -1960, -2282, -2523, -2607, -2519, +-2415, -2280, -2153, -2144, -2174, -2149, -2062, -1926, -1757, -1596, +-1522, -1488, -1423, -1358, -1335, -1336, -1259, -1162, -1163, -1219, +-1148, -953, -831, -800, -819, -807, -713, -650, -634, -463, +-209, -58, -84, -76, 57, 229, 460, 599, 811, 1002, +914, 849, 872, 940, 1057, 1161, 1389, 1502, 1455, 1369, +1271, 1347, 1498, 1645, 1689, 1658, 1760, 1943, 2148, 2362, +2542, 2637, 2704, 2870, 3142, 3483, 3791, 4013, 4189, 4277, +4069, 3498, 2681, 1816, 1141, 770, 682, 717, 713, 560, +162, -456, -1093, -1522, -1696, -1717, -1645, -1510, -1334, -1102, +-839, -634, -511, -491, -645, -890, -1071, -1077, -898, -624, +-382, -297, -349, -518, -744, -933, -1048, -1093, -1083, -1034, +-1028, -1060, -1088, -1090, -1048, -1023, -1025, -1026, -1070, -1122, +-1102, -990, -834, -744, -780, -979, -1300, -1568, -1729, -1760, +-1634, -1485, -1434, -1553, -1768, -1921, -1955, -1855, -1659, -1523, +-1511, -1519, -1472, -1391, -1329, -1286, -1262, -1278, -1314, -1207, +-1105, -937, -615, -444, -441, -508, -436, -243, -121, 38, +75, -109, -174, -137, -25, 147, 232, 213, 168, 206, +282, 372, 509, 547, 471, 641, 907, 977, 1102, 1244, +1278, 1297, 1342, 1487, 1667, 1827, 1977, 2027, 2070, 2184, +2293, 2378, 2461, 2551, 2639, 2722, 2807, 2930, 3105, 3317, +3473, 3371, 2897, 2134, 1334, 764, 559, 645, 784, 862, +806, 536, 84, -402, -719, -846, -880, -876, -839, -779, +-685, -596, -590, -632, -725, -941, -1222, -1402, -1404, -1256, +-1066, -969, -1000, -1092, -1264, -1489, -1622, -1631, -1523, -1431, +-1402, -1293, -1132, -977, -877, -824, -768, -758, -756, -741, +-699, -595, -501, -438, -404, -471, -619, -838, -1078, -1251, +-1339, -1360, -1347, -1297, -1290, -1309, -1378, -1433, -1423, -1393, +-1245, -1129, -1061, -936, -803, -717, -628, -521, -440, -438, +-445, -370, -270, -181, -192, -187, -138, -61, -57, -258, +-478, -638, -666, -634, -612, -605, -577, -472, -333, -87, +32, 64, 316, 548, 694, 890, 1074, 1291, 1429, 1493, +1522, 1403, 1311, 1258, 1252, 1315, 1292, 1283, 1306, 1293, +1339, 1430, 1561, 1740, 1981, 2211, 2321, 2446, 2592, 2753, +2961, 3232, 3472, 3338, 2777, 2045, 1403, 1015, 924, 964, +955, 876, 658, 277, -143, -481, -673, -788, -892, -968, +-970, -894, -779, -718, -792, -930, -1119, -1381, -1569, -1603, +-1498, -1354, -1303, -1331, -1342, -1329, -1362, -1363, -1315, -1266, +-1180, -1082, -924, -762, -692, -604, -553, -586, -609, -628, +-692, -737, -732, -723, -715, -709, -696, -672, -657, -706, +-828, -963, -1039, -1051, -1018, -904, -767, -753, -825, -906, +-969, -964, -888, -844, -851, -839, -782, -689, -671, -632, +-602, -629, -607, -695, -711, -543, -383, -354, -405, -287, +-232, -192, -91, -44, 6, -18, 47, 85, 81, 120, +34, -35, 51, 184, 309, 407, 497, 634, 672, 701, +785, 825, 834, 900, 1065, 1161, 1173, 1150, 1126, 1141, +1159, 1222, 1307, 1385, 1502, 1638, 1823, 2012, 2143, 2277, +2428, 2633, 2865, 3059, 3058, 2712, 2160, 1599, 1146, 938, +919, 873, 744, 513, 132, -302, -666, -916, -1065, -1174, +-1275, -1340, -1307, -1153, -977, -905, -929, -1029, -1216, -1381, +-1397, -1288, -1083, -895, -856, -927, -1070, -1211, -1281, -1216, +-1076, -1000, -968, -946, -870, -743, -616, -547, -557, -584, +-612, -596, -501, -382, -343, -407, -491, -525, -459, -361, +-363, -493, -750, -968, -1041, -1000, -873, -767, -706, -747, +-898, -1049, -1088, -1049, -1049, -1046, -1002, -938, -882, -866, +-879, -871, -828, -807, -769, -687, -584, -458, -423, -458, +-424, -310, -201, -135, 30, 193, 261, 311, 402, 557, +569, 592, 712, 721, 638, 417, 231, 182, 213, 329, +335, 307, 389, 498, 555, 675, 887, 912, 930, 1160, +1439, 1620, 1656, 1674, 1754, 1873, 1996, 2105, 2204, 2252, +2280, 2375, 2528, 2701, 2661, 2228, 1615, 1067, 707, 602, +673, 715, 628, 390, -27, -473, -792, -967, -1037, -1092, +-1151, -1175, -1150, -1061, -950, -930, -992, -1136, -1363, -1468, +-1370, -1154, -880, -709, -711, -800, -944, -1078, -1124, -1049, +-957, -912, -895, -848, -741, -611, -475, -389, -364, -370, +-343, -355, -337, -199, -77, 11, 38, -23, -98, -209, +-408, -646, -876, -1073, -1148, -1106, -1046, -1066, -1203, -1332, +-1442, -1515, -1436, -1255, -1082, -966, -917, -905, -856, -734, +-629, -654, -675, -585, -503, -472, -465, -430, -448, -530, +-604, -585, -428, -348, -240, -108, -72, -22, 50, 128, +177, 254, 355, 455, 572, 734, 867, 873, 788, 709, +822, 1021, 1192, 1214, 1142, 1178, 1263, 1413, 1548, 1653, +1724, 1815, 1992, 2213, 2428, 2562, 2677, 2831, 2982, 3131, +3303, 3239, 2704, 1929, 1178, 628, 496, 645, 708, 640, +413, -79, -613, -969, -1132, -1153, -1134, -1153, -1164, -1099, +-942, -811, -849, -969, -1187, -1496, -1649, -1549, -1297, -991, +-789, -823, -956, -1063, -1142, -1124, -1016, -891, -829, -816, +-741, -571, -396, -292, -312, -445, -548, -575, -536, -355, +-106, 28, 44, -25, -128, -242, -406, -596, -846, -1104, +-1217, -1219, -1176, -1083, -1107, -1308, -1509, -1622, -1590, -1464, +-1337, -1193, -1073, -961, -860, -841, -829, -850, -949, -991, +-946, -876, -738, -559, -487, -498, -533, -536, -487, -544, +-558, -383, -150, -90, -187, -105, 86, 239, 353, 350, +355, 423, 555, 795, 1021, 1170, 1249, 1315, 1380, 1409, +1414, 1500, 1621, 1696, 1798, 1943, 2092, 2225, 2411, 2568, +2676, 2859, 3096, 3356, 3603, 3881, 3966, 3465, 2595, 1735, +1085, 868, 991, 1036, 890, 551, -125, -903, -1435, -1692, +-1778, -1818, -1856, -1808, -1618, -1336, -1094, -1067, -1182, -1374, +-1634, -1671, -1369, -958, -575, -340, -396, -586, -739, -870, +-911, -844, -778, -746, -712, -595, -417, -322, -330, -449, +-631, -707, -645, -511, -289, -79, -18, -60, -165, -289, +-395, -624, -1095, -1525, -1726, -1833, -1732, -1455, -1398, -1618, +-1893, -2144, -2248, -2079, -1754, -1491, -1338, -1220, -1156, -1123, +-1102, -1083, -1093, -1134, -1139, -1117, -901, -612, -552, -632, +-714, -749, -756, -622, -413, -255, -142, -84, -6, 103, +267, 299, 305, 448, 589, 841, 1026, 975, 892, 959, +1124, 1339, 1588, 1776, 1935, 2072, 2189, 2336, 2565, 2800, +3000, 3294, 3659, 3992, 4278, 4529, 4693, 4881, 4978, 4397, +3346, 2408, 1602, 1153, 1193, 1209, 909, 382, -519, -1584, +-2317, -2676, -2810, -2828, -2761, -2646, -2473, -2165, -1830, -1727, +-1765, -1800, -1864, -1656, -1059, -435, 77, 407, 357, 96, +-91, -194, -233, -184, -114, -84, -85, -49, -4, -77, +-242, -484, -785, -900, -765, -577, -365, -201, -242, -387, +-530, -687, -970, -1406, -1757, -1986, -2106, -1959, -1764, -1839, +-2104, -2439, -2717, -2757, -2514, -2095, -1708, -1486, -1419, -1424, +-1381, -1280, -1192, -1137, -1070, -981, -927, -866, -809, -790, +-821, -890, -925, -883, -670, -397, -196, -81, -43, 19, +125, 286, 571, 819, 851, 821, 926, 1219, 1577, 1755, +1867, 2030, 2132, 2238, 2446, 2758, 3038, 3281, 3562, 3893, +4329, 4742, 5091, 5413, 5741, 6031, 6312, 6553, 6007, 4638, +3242, 2035, 1307, 1290, 1339, 883, 40, -1227, -2740, -3772, +-4150, -4130, -4012, -3879, -3652, -3300, -2741, -2143, -1871, -1884, +-1863, -1782, -1359, -352, 687, 1356, 1667, 1499, 1068, 814, +706, 612, 574, 507, 393, 296, 253, 155, -213, -799, +-1408, -1872, -1876, -1420, -971, -715, -693, -958, -1253, -1295, +-1320, -1618, -1932, -2269, -2640, -2602, -2310, -2346, -2753, -3301, +-3911, -4221, -3919, -3276, -2717, -2360, -2215, -2249, -2154, -1891, +-1684, -1529, -1367, -1228, -1019, -724, -570, -665, -894, -1141, +-1304, -1182, -772, -382, -161, -38, 20, 129, 390, 714, +995, 1308, 1596, 1847, 2230, 2651, 2932, 3037, 3099, 3333, +3764, 4253, 4727, 5177, 5582, 6024, 6461, 6882, 7291, 7634, +8009, 8400, 8779, 7988, 5438, 2764, 840, -154, 30, 330, +-468, -2125, -4214, -6395, -7441, -7257, -6766, -6134, -5289, -4160, +-2894, -1747, -963, -797, -899, -487, 631, 2254, 4050, 5010, +4707, 3860, 2792, 1800, 1376, 1153, 688, 172, -328, -789, +-1134, -1737, -2787, -3982, -4790, -4722, -3883, -2666, -1567, -1212, +-1513, -1811, -1765, -1295, -668, -423, -494, -554, -669, -759, +-839, -1358, -2401, -3501, -4163, -4178, -3761, -3414, -3539, -4029, +-4441, -4517, -4203, -3574, -2954, -2582, -2310, -1953, -1535, -1229, +-1208, -1422, -1565, -1378, -872, -299, 40, 21, -221, -410, +-202, 401, 944, 1372, 1640, 1764, 2150, 2685, 3077, 3213, +3161, 3242, 3586, 4190, 5029, 5721, 5974, 6138, 6470, 6895, +7464, 8088, 8647, 9113, 9550, 9142, 6686, 3364, 780, -877, +-1168, -595, -817, -2275, -4381, -6821, -8568, -8749, -8163, -7250, +-5824, -4075, -2406, -1089, -233, -32, -228, 55, 1321, 3197, +5109, 6262, 5980, 4841, 3501, 2043, 1005, 528, 62, -460, +-856, -1250, -1781, -2672, -4063, -5408, -5957, -5408, -4014, -2389, +-1066, -510, -726, -1007, -864, -369, 159, 242, 126, 406, +653, 480, -49, -1336, -3213, -4606, -4952, -4450, -3647, -3330, +-3828, -4596, -4983, -4891, -4439, -3737, -3088, -2569, -1940, -1225, +-725, -686, -1154, -1755, -1798, -1086, -135, 510, 562, 62, +-576, -780, -279, 609, 1263, 1576, 1757, 1771, 2109, 2697, +2923, 3039, 3206, 3522, 4118, 4849, 5512, 5763, 5794, 6001, +6519, 7199, 7823, 8347, 8639, 8991, 9489, 8767, 5913, 2421, +-238, -1635, -1356, -543, -952, -2711, -5267, -7775, -8988, -8595, +-7596, -6434, -4833, -2977, -1303, -101, 450, 275, -15, 623, +2375, 4593, 6326, 6657, 5506, 3804, 2289, 1113, 484, 149, +-367, -962, -1374, -1701, -2291, -3428, -4923, -5942, -5713, -4268, +-2337, -769, -16, -165, -694, -924, -662, 95, 495, 379, +709, 1036, 744, -39, -1408, -3153, -4590, -4986, -4416, -3686, +-3421, -3896, -4787, -5346, -5230, -4682, -3913, -3086, -2411, -1798, +-1240, -878, -873, -1209, -1488, -1364, -667, 226, 638, 439, +-108, -627, -714, -184, 615, 1173, 1432, 1583, 1705, 1867, +2087, 2321, 2509, 2753, 3388, 4207, 4699, 5007, 5254, 5411, +5893, 6794, 7556, 7960, 8209, 8414, 8756, 9325, 8878, 5948, +2119, -469, -1755, -1644, -934, -1551, -3699, -6205, -8227, -9028, +-8402, -7469, -6619, -5123, -3003, -1032, 186, 597, 296, -45, +779, 2873, 5107, 6394, 6192, 4690, 2956, 1766, 889, 259, +-230, -895, -1513, -1771, -1888, -2462, -3722, -5179, -5834, -5062, +-3278, -1441, -312, 4, -274, -606, -441, 47, 588, 704, +536, 817, 1039, 574, -621, -2346, -3945, -4916, -4922, -4264, +-3888, -4165, -4886, -5510, -5507, -4927, -4231, -3575, -2857, -2150, +-1494, -1047, -949, -1156, -1484, -1427, -829, -59, 395, 203, +-410, -900, -939, -533, 153, 770, 1039, 1097, 1276, 1628, +1888, 1928, 2056, 2465, 2977, 3869, 4766, 4869, 4761, 4804, +5081, 5938, 6954, 7597, 7833, 7931, 8188, 8626, 9094, 8759, +6097, 2050, -575, -1429, -1246, -621, -1306, -3742, -6360, -8164, +-8804, -8146, -7188, -6500, -5148, -3005, -1015, 101, 161, -285, +-428, 613, 2965, 5281, 6241, 5633, 4004, 2341, 1452, 923, +266, -318, -903, -1377, -1513, -1703, -2516, -3967, -5321, -5500, +-4185, -2260, -739, -138, -241, -454, -423, 74, 712, 1021, +838, 644, 977, 1148, 484, -980, -2785, -4117, -4606, -4356, +-3951, -4109, -4805, -5530, -5726, -5276, -4560, -3957, -3495, -2858, +-2001, -1236, -866, -938, -1216, -1358, -948, -170, 395, 451, +-43, -681, -905, -663, -265, 157, 479, 701, 952, 1221, +1432, 1471, 1500, 1761, 2318, 3189, 4014, 4151, 3964, 4096, +4436, 5142, 6187, 6876, 7131, 7301, 7503, 8012, 8700, 8964, +8856, 7782, 4723, 1485, -194, -963, -1161, -1437, -2773, -4672, +-6433, -7817, -8422, -8216, -7616, -6407, -4379, -2170, -661, -320, +-550, -560, 55, 1660, 3732, 5103, 5324, 4607, 3432, 2357, +1498, 546, -311, -768, -951, -1012, -1219, -1889, -3104, -4456, +-5080, -4502, -3139, -1738, -837, -498, -365, -269, -160, 119, +294, 180, 213, 558, 839, 643, -326, -1871, -3251, -3962, +-4116, -4051, -4034, -4299, -4730, -4882, -4718, -4481, -4196, -3843, +-3314, -2468, -1608, -1154, -1136, -1344, -1487, -1288, -775, -305, +-129, -292, -595, -754, -671, -440, -211, 77, 514, 1043, +1463, 1713, 1764, 1732, 2088, 2739, 3291, 3654, 3791, 3833, +3990, 4416, 5052, 5576, 5948, 6290, 6712, 7199, 7656, 8124, +8473, 8733, 8911, 7602, 4340, 1275, -561, -1452, -1293, -1226, +-2495, -4554, -6595, -8056, -8386, -7914, -7209, -5903, -3870, -1871, +-636, -332, -561, -753, -258, 1413, 3554, 4900, 4979, 4048, +2761, 1705, 871, 39, -530, -777, -902, -929, -1078, -1748, +-3037, -4361, -4785, -3974, -2510, -1211, -471, -232, -242, -328, +-284, 76, 342, 327, 285, 372, 519, 18, -1198, -2423, +-3568, -4387, -4460, -4213, -4165, -4390, -4700, -4842, -4680, -4276, +-3840, -3349, -2630, -1837, -1291, -1011, -996, -1247, -1392, -1206, +-773, -387, -302, -477, -767, -910, -848, -633, -225, 316, +858, 1293, 1517, 1632, 1689, 1776, 2248, 2900, 3303, 3682, +4135, 4181, 4236, 4658, 5002, 5416, 6013, 6713, 7141, 7210, +7399, 7618, 7936, 8452, 8654, 7460, 4432, 1363, -509, -1340, +-1338, -1576, -2770, -4507, -6214, -7365, -7714, -7496, -7053, -5895, +-3813, -1737, -457, -262, -629, -812, -222, 1407, 3318, 4470, +4438, 3594, 2550, 1666, 872, -72, -821, -1083, -1033, -902, +-1013, -1705, -2995, -4182, -4441, -3662, -2389, -1332, -723, -386, +-171, -51, -13, 76, -247, -731, -337, 330, 538, 253, +-900, -2545, -3690, -4004, -3900, -3860, -3933, -4171, -4398, -4261, +-4069, -4139, -4175, -3875, -3159, -2117, -1252, -1067, -1344, -1676, +-1713, -1292, -736, -405, -384, -493, -507, -429, -410, -410, +-323, -11, 653, 1360, 1691, 1717, 1579, 1576, 2060, 2792, +3357, 3720, 3980, 4168, 4384, 4754, 5244, 5635, 6097, 6742, +7251, 7585, 7802, 7845, 7902, 8197, 8291, 6956, 4057, 1316, +-387, -1247, -1337, -1617, -2899, -4633, -6155, -7073, -7232, -7010, +-6600, -5423, -3454, -1608, -567, -392, -690, -822, -142, 1471, +3220, 4113, 3936, 3137, 2297, 1601, 835, -25, -656, -910, +-892, -749, -894, -1689, -2940, -3962, -4055, -3222, -2141, -1352, +-880, -563, -319, -177, -113, -309, -1076, -1470, -777, -16, +235, -95, -1371, -2975, -3880, -4057, -3994, -3947, -3839, -3653, +-3479, -3341, -3469, -3939, -4204, -3792, -2783, -1554, -806, -912, +-1451, -1904, -1956, -1635, -1176, -789, -546, -294, -27, 25, +-154, -314, -213, 370, 1361, 2305, 2726, 2603, 2392, 2316, +2473, 2919, 3370, 3688, 4050, 4462, 4908, 5317, 5506, 5657, +5923, 6341, 7061, 7799, 8306, 8665, 8833, 8530, 6593, 3360, +941, -337, -839, -623, -887, -2352, -4332, -6178, -7367, -7563, +-7294, -6553, -4773, -2622, -1095, -589, -955, -1474, -1485, -435, +1654, 3576, 4310, 3945, 3067, 2130, 1285, 402, -323, -531, +-463, -253, -110, -554, -1720, -3204, -4140, -3931, -2942, -1937, +-1175, -650, -406, -352, -467, -640, -1082, -1761, -1565, -569, +125, 242, -480, -1993, -3312, -3839, -3952, -3958, -3884, -3822, +-3658, -3393, -3376, -3799, -4345, -4403, -3687, -2419, -1215, -762, +-1050, -1525, -1729, -1483, -991, -559, -261, 0, 257, 435, +363, 38, -158, 98, 814, 1733, 2355, 2426, 2274, 2124, +2218, 2769, 3169, 3412, 3983, 4552, 5057, 5538, 5760, 5780, +6007, 6585, 7293, 8095, 8701, 8905, 8934, 8383, 6155, 3034, +839, -458, -1029, -859, -1196, -2616, -4471, -6199, -7287, -7540, +-7262, -6361, -4553, -2492, -1138, -772, -1114, -1551, -1479, -377, +1630, 3307, 3911, 3657, 2948, 2101, 1221, 313, -399, -594, +-488, -276, -116, -538, -1671, -3031, -3875, -3752, -2980, -2109, +-1335, -702, -310, -250, -397, -826, -1469, -1771, -1585, -918, +-199, -256, -1142, -2295, -3250, -3835, -4084, -4079, -4029, -3970, +-3699, -3412, -3479, -3830, -4178, -4131, -3405, -2294, -1385, -1000, +-1125, -1411, -1454, -1217, -830, -462, -110, 291, 597, 692, +548, 257, 74, 382, 1193, 1979, 2442, 2516, 2349, 2288, +2558, 3072, 3468, 3891, 4427, 4953, 5554, 6099, 6416, 6506, +6703, 7250, 7890, 8574, 9077, 9146, 8080, 5337, 2602, 848, +-441, -987, -1110, -1737, -2932, -4368, -5779, -6834, -7434, -7513, +-6334, -4140, -2176, -1108, -1026, -1435, -1722, -1400, -83, 1692, +2880, 3251, 3204, 2889, 2186, 1193, 113, -557, -615, -378, +-69, -87, -760, -1936, -2970, -3357, -3213, -2841, -2312, -1567, +-792, -216, -39, -399, -1332, -2412, -2467, -1539, -651, -35, +-179, -1389, -2734, -3506, -3884, -4033, -3900, -3527, -3056, -2767, +-2914, -3534, -4317, -4622, -4087, -2901, -1634, -1000, -1109, -1496, +-1814, -1812, -1501, -1018, -426, 235, 853, 1145, 977, 508, +131, 211, 901, 1874, 2609, 2943, 2917, 2793, 2758, 2835, +3102, 3500, 4174, 5023, 5636, 6109, 6362, 6285, 6368, 6858, +7452, 8080, 8687, 9050, 8309, 5794, 3034, 1119, -364, -1049, +-1036, -1461, -2499, -3751, -5103, -6175, -6903, -7304, -6511, -4527, +-2602, -1410, -1007, -1259, -1692, -1678, -694, 895, 2090, 2634, +2843, 2778, 2248, 1327, 287, -458, -725, -622, -214, 33, +-359, -1310, -2322, -2924, -3053, -2884, -2469, -1722, -909, -318, +-55, -309, -1117, -2272, -2832, -2278, -1440, -800, -543, -1072, +-2158, -3178, -3833, -4248, -4455, -4177, -3428, -2755, -2588, -2920, +-3646, -4343, -4343, -3552, -2384, -1368, -886, -858, -1041, -1222, +-1336, -1271, -817, -65, 772, 1451, 1618, 1234, 709, 468, +729, 1390, 2128, 2698, 3009, 3215, 3336, 3293, 3342, 3543, +3951, 4786, 5825, 6674, 7156, 7271, 7264, 7418, 7746, 8234, +8752, 8302, 6299, 3992, 2153, 538, -549, -1133, -1822, -2721, +-3666, -4589, -5438, -6323, -6964, -6521, -5005, -3362, -2237, -1760, +-1681, -1667, -1413, -543, 660, 1451, 1840, 2182, 2426, 2324, +1738, 844, 116, -265, -390, -231, -151, -535, -1218, -1895, +-2345, -2565, -2719, -2679, -2213, -1496, -806, -387, -459, -1134, +-2143, -2571, -2299, -1854, -1259, -913, -1210, -1780, -2363, -3042, +-3701, -4034, -3870, -3344, -2780, -2510, -2755, -3355, -3843, -3918, +-3522, -2790, -2119, -1671, -1315, -1126, -1115, -1180, -1182, -907, +-281, 543, 1273, 1656, 1576, 1310, 1243, 1374, 1677, 2157, +2572, 2917, 3265, 3451, 3489, 3459, 3523, 3954, 4738, 5602, +6360, 6906, 7173, 7355, 7674, 8056, 8416, 8415, 7199, 5108, +3315, 1788, 516, -147, -717, -1617, -2613, -3632, -4685, -5679, +-6485, -6531, -5481, -4005, -2855, -2258, -2155, -2214, -2025, -1305, +-98, 935, 1473, 1898, 2289, 2343, 2004, 1392, 692, 245, +103, 177, 328, 149, -445, -1114, -1682, -2160, -2514, -2662, +-2418, -1776, -1062, -541, -431, -844, -1640, -2431, -2655, -2356, +-1945, -1473, -1181, -1434, -2069, -2755, -3430, -3948, -3989, -3525, +-2870, -2378, -2253, -2529, -3047, -3476, -3547, -3176, -2537, -1918, +-1408, -1047, -960, -1104, -1247, -1188, -800, -106, 745, 1456, +1850, 1876, 1669, 1590, 1586, 1726, 2134, 2561, 2960, 3372, +3619, 3680, 3688, 3747, 4092, 4712, 5441, 6252, 6923, 7379, +7687, 7860, 7990, 7924, 7047, 5330, 3727, 2433, 1245, 516, +-40, -982, -2145, -3285, -4309, -5179, -5899, -6116, -5462, -4305, +-3306, -2690, -2499, -2590, -2524, -1948, -850, 280, 1012, 1498, +1893, 2076, 1941, 1569, 1075, 625, 416, 457, 609, 566, +165, -406, -993, -1552, -2011, -2300, -2335, -2031, -1437, -855, +-606, -838, -1627, -2563, -2981, -2960, -2706, -2138, -1725, -1818, +-2092, -2438, -3009, -3655, -3954, -3704, -3156, -2598, -2179, -2130, +-2536, -3012, -3224, -3169, -2869, -2447, -1951, -1388, -988, -863, +-904, -971, -903, -513, 206, 1012, 1615, 1916, 2020, 2021, +2009, 2043, 2184, 2529, 2973, 3362, 3745, 4032, 4015, 3996, +4302, 4742, 5313, 6091, 6807, 7326, 7741, 8035, 8043, 7220, +5471, 3760, 2462, 1349, 738, 472, -135, -1134, -2333, -3606, +-4763, -5757, -6235, -5672, -4484, -3456, -2781, -2551, -2778, -3004, +-2759, -1913, -843, -42, 624, 1300, 1725, 1746, 1479, 1036, +567, 331, 431, 753, 943, 790, 429, -59, -655, -1265, +-1774, -2027, -1903, -1426, -808, -439, -548, -1141, -2103, -2836, +-3003, -2981, -2720, -2160, -1878, -1993, -2252, -2734, -3460, -4060, +-4069, -3526, -2899, -2394, -2075, -2177, -2597, -2917, -2985, -2837, +-2580, -2223, -1650, -1120, -876, -811, -863, -919, -773, -329, +352, 1010, 1461, 1794, 2031, 2072, 2015, 2059, 2217, 2494, +3003, 3611, 3963, 4046, 4106, 4199, 4372, 4770, 5337, 5894, +6404, 6884, 7269, 7442, 7194, 6241, 4819, 3486, 2302, 1355, +853, 489, -52, -793, -1737, -2863, -4088, -5058, -5354, -4904, +-4096, -3332, -2824, -2729, -2896, -2968, -2741, -2213, -1578, -935, +-210, 480, 937, 1098, 1005, 712, 379, 230, 316, 521, +722, 884, 919, 699, 264, -299, -875, -1244, -1238, -894, +-452, -208, -330, -780, -1486, -2230, -2734, -2971, -2926, -2673, +-2456, -2339, -2464, -2899, -3385, -3750, -3826, -3585, -3192, -2741, +-2385, -2232, -2219, -2267, -2342, -2402, -2303, -2033, -1632, -1133, +-717, -428, -257, -162, -42, 165, 496, 886, 1291, 1676, +1992, 2201, 2292, 2365, 2482, 2669, 2969, 3307, 3632, 3877, +4058, 4286, 4524, 4836, 5266, 5673, 6077, 6400, 6466, 6221, +5554, 4589, 3624, 2792, 2112, 1651, 1269, 748, 54, -820, +-1760, -2547, -3141, -3428, -3340, -3187, -3102, -3028, -3022, -3027, +-2953, -2816, -2583, -2311, -2030, -1645, -1170, -760, -452, -209, +-91, -60, -67, -79, -8, 149, 360, 597, 740, 711, +563, 348, 133, 0, -52, -43, -3, -33, -192, -495, +-955, -1509, -1995, -2297, -2397, -2378, -2370, -2459, -2672, -2952, +-3190, -3322, -3340, -3254, -3085, -2839, -2561, -2326, -2169, -2067, +-1991, -1928, -1833, -1654, -1405, -1127, -816, -497, -238, -82, +-5, 72, 242, 501, 814, 1159, 1421, 1584, 1752, 1947, +2140, 2366, 2639, 2941, 3279, 3640, 3984, 4238, 4402, 4526, +4683, 4875, 5088, 5264, 5274, 5057, 4596, 4025, 3462, 3023, +2779, 2660, 2482, 2055, 1405, 688, 45, -442, -751, -956, +-1204, -1544, -1876, -2150, -2392, -2641, -2888, -3103, -3284, -3367, +-3299, -3122, -2932, -2744, -2534, -2360, -2275, -2221, -2108, -1916, +-1625, -1232, -829, -531, -357, -216, -55, 111, 243, 355, +437, 480, 489, 447, 359, 170, -59, -224, -358, -565, +-911, -1302, -1626, -1878, -2012, -2031, -2116, -2358, -2650, -2832, +-2907, -2966, -2985, -2909, -2829, -2754, -2561, -2316, -2150, -2055, +-1906, -1643, -1361, -1101, -770, -403, -88, 262, 677, 1017, +1258, 1500, 1850, 2298, 2731, 3140, 3505, 3782, 4016, 4333, +4740, 5117, 5409, 5650, 5888, 6073, 6141, 6064, 5710, 5056, +4333, 3766, 3440, 3196, 2857, 2289, 1443, 511, -257, -781, +-1186, -1559, -1882, -2155, -2386, -2583, -2783, -3029, -3332, -3558, +-3616, -3574, -3482, -3326, -3096, -2794, -2463, -2201, -2082, -2109, +-2153, -2035, -1702, -1253, -806, -431, -152, 71, 272, 442, +519, 497, 491, 575, 724, 848, 831, 642, 338, 22, +-230, -450, -725, -1088, -1438, -1673, -1799, -1890, -2025, -2245, +-2539, -2812, -2945, -2977, -2997, -2984, -2892, -2739, -2566, -2379, +-2192, -2031, -1855, -1558, -1167, -821, -550, -284, -9, 282, +641, 1015, 1341, 1627, 1940, 2309, 2675, 3010, 3334, 3664, +4030, 4434, 4858, 5240, 5534, 5786, 6019, 6218, 6280, 6105, +5625, 4958, 4306, 3779, 3453, 3183, 2730, 1987, 1070, 211, +-487, -1052, -1485, -1830, -2152, -2437, -2624, -2787, -3017, -3281, +-3505, -3603, -3611, -3564, -3436, -3232, -2967, -2635, -2303, -2091, +-2042, -2064, -1994, -1762, -1387, -927, -496, -179, 56, 270, +440, 537, 565, 573, 640, 779, 945, 1039, 936, 616, +203, -175, -479, -692, -887, -1151, -1466, -1735, -1931, -2125, +-2322, -2495, -2676, -2810, -2830, -2800, -2805, -2808, -2713, -2563, +-2410, -2214, -1987, -1771, -1543, -1220, -834, -515, -257, 23, +333, 657, 1013, 1396, 1750, 2046, 2362, 2721, 3037, 3291, +3561, 3865, 4175, 4511, 4843, 5112, 5313, 5478, 5646, 5784, +5759, 5545, 5107, 4500, 3909, 3441, 3104, 2754, 2267, 1562, +722, -70, -721, -1236, -1662, -2020, -2314, -2562, -2765, -2930, +-3117, -3323, -3487, -3543, -3513, -3422, -3267, -3047, -2755, -2433, +-2148, -1948, -1855, -1814, -1706, -1464, -1097, -673, -285, 8, +218, 371, 474, 533, 556, 558, 607, 682, 685, 578, +369, 111, -130, -304, -475, -758, -1174, -1598, -1898, -2087, +-2186, -2235, -2357, -2593, -2815, -2936, -2986, -3020, -2975, -2804, +-2586, -2358, -2072, -1780, -1566, -1346, -1021, -656, -348, -71, +235, 565, 919, 1339, 1760, 2064, 2274, 2506, 2793, 3095, +3399, 3689, 3947, 4167, 4398, 4676, 4922, 5087, 5188, 5259, +5272, 5166, 4924, 4486, 3931, 3411, 3025, 2766, 2445, 1930, +1202, 387, -314, -834, -1221, -1566, -1915, -2254, -2551, -2756, +-2930, -3141, -3359, -3505, -3522, -3428, -3282, -3125, -2936, -2694, +-2403, -2106, -1898, -1818, -1761, -1615, -1330, -929, -529, -206, +25, 194, 353, 499, 582, 589, 583, 602, 607, 557, +398, 161, -63, -220, -338, -534, -890, -1330, -1708, -1957, +-2068, -2108, -2214, -2453, -2715, -2904, -3018, -3088, -3118, -3082, +-2970, -2768, -2481, -2163, -1893, -1635, -1326, -971, -608, -262, +82, 469, 914, 1416, 1902, 2272, 2529, 2748, 3017, 3356, +3721, 4062, 4362, 4615, 4850, 5066, 5225, 5312, 5345, 5369, +5357, 5208, 4785, 4164, 3519, 2989, 2661, 2424, 2086, 1484, +673, -94, -654, -1065, -1413, -1728, -2059, -2389, -2603, -2712, +-2853, -3051, -3247, -3349, -3357, -3289, -3163, -3003, -2814, -2552, +-2225, -1973, -1896, -1906, -1842, -1617, -1239, -785, -378, -96, +98, 290, 500, 645, 680, 665, 679, 720, 753, 709, +500, 195, -100, -300, -443, -679, -1052, -1462, -1783, -1974, +-2052, -2111, -2255, -2487, -2705, -2815, -2837, -2866, -2887, -2852, +-2733, -2533, -2266, -1986, -1760, -1529, -1220, -848, -475, -128, +219, 592, 1020, 1498, 1948, 2302, 2579, 2857, 3207, 3616, +4014, 4363, 4651, 4894, 5125, 5320, 5461, 5542, 5596, 5620, +5557, 5262, 4643, 3881, 3159, 2632, 2330, 2079, 1641, 926, +94, -596, -1086, -1478, -1813, -2121, -2437, -2680, -2754, -2788, +-2898, -3073, -3190, -3207, -3185, -3118, -2970, -2763, -2514, -2183, +-1835, -1630, -1621, -1660, -1579, -1316, -940, -547, -235, -43, +106, 285, 464, 550, 525, 487, 503, 496, 423, 289, +72, -157, -287, -347, -522, -916, -1411, -1803, -2030, -2101, +-2075, -2146, -2384, -2611, -2713, -2737, -2761, -2796, -2771, -2682, +-2509, -2203, -1876, -1662, -1491, -1250, -958, -671, -402, -108, +229, 639, 1158, 1668, 2011, 2222, 2421, 2706, 3091, 3522, +3918, 4234, 4477, 4680, 4886, 5052, 5151, 5196, 5235, 5254, +5157, 4845, 4277, 3606, 2988, 2534, 2231, 1914, 1393, 666, +-93, -719, -1196, -1590, -1934, -2279, -2597, -2812, -2895, -2976, +-3103, -3232, -3292, -3269, -3202, -3090, -2944, -2769, -2518, -2163, +-1833, -1656, -1606, -1541, -1373, -1098, -758, -428, -179, -17, +132, 294, 423, 445, 399, 343, 240, 81, -90, -270, +-450, -563, -636, -804, -1153, -1597, -1991, -2230, -2304, -2269, +-2263, -2385, -2548, -2661, -2708, -2726, -2720, -2686, -2607, -2445, +-2190, -1886, -1607, -1362, -1095, -804, -523, -250, 22, 327, +709, 1154, 1595, 1955, 2205, 2434, 2725, 3089, 3491, 3858, +4172, 4433, 4652, 4869, 5068, 5206, 5289, 5335, 5281, 5060, +4603, 3966, 3325, 2795, 2436, 2152, 1762, 1152, 396, -323, +-871, -1275, -1618, -1944, -2267, -2569, -2767, -2865, -2960, -3078, +-3181, -3213, -3181, -3110, -3009, -2853, -2651, -2389, -2078, -1835, +-1731, -1683, -1582, -1363, -1029, -665, -339, -108, 62, 245, +432, 553, 587, 568, 511, 458, 350, 136, -117, -369, +-559, -675, -831, -1147, -1617, -2061, -2317, -2427, -2448, -2440, +-2512, -2682, -2795, -2782, -2742, -2723, -2651, -2455, -2221, -1961, +-1633, -1330, -1119, -877, -529, -164, 131, 396, 731, 1115, +1501, 1913, 2296, 2545, 2732, 2984, 3308, 3618, 3876, 4124, +4348, 4514, 4666, 4834, 4963, 5040, 5074, 5036, 4787, 4236, +3558, 2961, 2546, 2293, 2084, 1723, 1093, 310, -352, -807, +-1165, -1487, -1762, -2042, -2313, -2466, -2530, -2620, -2787, -2902, +-2904, -2887, -2876, -2793, -2627, -2406, -2114, -1804, -1608, -1593, +-1624, -1535, -1293, -966, -604, -296, -96, 37, 193, 347, +408, 374, 320, 282, 149, -45, -215, -379, -517, -572, +-651, -945, -1437, -1872, -2108, -2212, -2170, -2058, -2091, -2304, +-2471, -2521, -2564, -2607, -2543, -2391, -2245, -2017, -1690, -1431, +-1287, -1092, -789, -487, -226, 76, 435, 812, 1230, 1688, +2058, 2268, 2451, 2733, 3107, 3483, 3820, 4090, 4253, 4338, +4453, 4601, 4713, 4754, 4773, 4763, 4613, 4296, 3814, 3229, +2645, 2179, 1876, 1594, 1189, 648, 49, -491, -914, -1257, +-1566, -1869, -2139, -2325, -2394, -2434, -2512, -2602, -2656, -2656, +-2634, -2577, -2477, -2348, -2166, -1901, -1620, -1437, -1381, -1356, +-1280, -1112, -866, -597, -371, -210, -55, 111, 241, 269, +193, -8, -295, -536, -701, -801, -847, -909, -1079, -1392, +-1749, -2050, -2313, -2452, -2420, -2337, -2301, -2292, -2289, -2345, +-2408, -2360, -2217, -2097, -1943, -1690, -1440, -1220, -967, -693, +-469, -296, -67, 239, 548, 882, 1267, 1627, 1890, 2126, +2399, 2678, 2926, 3198, 3514, 3796, 4004, 4206, 4384, 4476, +4548, 4689, 4853, 4877, 4712, 4321, 3699, 3010, 2475, 2147, +1903, 1575, 1109, 504, -160, -723, -1132, -1452, -1745, -1983, +-2173, -2333, -2463, -2568, -2638, -2677, -2682, -2647, -2604, -2566, +-2468, -2263, -1966, -1668, -1446, -1344, -1323, -1291, -1157, -906, +-624, -370, -162, 11, 142, 240, 295, 274, 134, -111, +-362, -570, -727, -799, -826, -941, -1234, -1608, -1928, -2201, +-2372, -2366, -2274, -2243, -2258, -2236, -2253, -2336, -2365, -2273, +-2166, -2055, -1833, -1549, -1320, -1105, -844, -594, -410, -211, +74, 375, 684, 1089, 1540, 1886, 2115, 2305, 2487, 2642, +2839, 3152, 3464, 3674, 3842, 4004, 4099, 4144, 4249, 4395, +4485, 4512, 4468, 4307, 3920, 3367, 2853, 2401, 2003, 1691, +1401, 970, 391, -160, -584, -937, -1269, -1545, -1763, -1999, +-2188, -2241, -2261, -2340, -2420, -2419, -2397, -2401, -2348, -2201, +-2021, -1834, -1596, -1353, -1243, -1225, -1152, -987, -776, -543, +-280, -68, 60, 160, 259, 259, 62, -192, -396, -572, +-675, -711, -805, -1040, -1336, -1560, -1754, -1945, -2070, -2143, +-2209, -2226, -2150, -2114, -2162, -2209, -2199, -2155, -2074, -1915, +-1722, -1543, -1322, -1041, -775, -570, -380, -145, 116, 430, +797, 1171, 1492, 1780, 2053, 2301, 2509, 2680, 2873, 3097, +3329, 3558, 3752, 3877, 3963, 4046, 4153, 4260, 4316, 4306, +4229, 4090, 3804, 3330, 2781, 2256, 1815, 1517, 1309, 1008, +502, -72, -528, -875, -1154, -1353, -1510, -1725, -1928, -1993, +-2001, -2077, -2167, -2175, -2150, -2141, -2085, -1957, -1857, -1755, +-1557, -1328, -1215, -1202, -1172, -1077, -921, -695, -423, -228, +-141, -89, -28, -55, -233, -457, -648, -797, -885, -934, +-1038, -1253, -1475, -1615, -1732, -1863, -1989, -2074, -2126, -2102, +-2004, -1949, -1990, -2067, -2099, -2087, -2018, -1898, -1768, -1639, +-1470, -1247, -1033, -873, -711, -507, -238, 98, 460, 795, +1090, 1390, 1696, 1990, 2239, 2427, 2585, 2770, 3010, 3265, +3482, 3647, 3764, 3853, 3955, 4075, 4178, 4245, 4302, 4317, +4268, 4121, 3723, 3019, 2194, 1483, 1019, 807, 665, 352, +-218, -848, -1296, -1536, -1684, -1783, -1874, -1977, -1996, -1898, +-1802, -1805, -1849, -1848, -1803, -1770, -1732, -1675, -1590, -1417, +-1136, -887, -818, -908, -1002, -968, -791, -531, -297, -167, +-194, -338, -465, -590, -779, -944, -1041, -1138, -1295, -1453, +-1575, -1726, -1870, -1925, -1954, -2084, -2235, -2268, -2239, -2176, +-2050, -1926, -1918, -1977, -1952, -1838, -1715, -1568, -1374, -1191, +-1043, -864, -648, -457, -270, -18, 282, 559, 804, 1047, +1298, 1517, 1724, 1943, 2126, 2260, 2406, 2602, 2800, 2968, +3129, 3286, 3429, 3557, 3701, 3851, 3945, 3996, 4021, 4018, +3982, 3790, 3387, 2872, 2318, 1831, 1518, 1337, 1091, 661, +144, -321, -729, -1075, -1298, -1430, -1601, -1753, -1795, -1833, +-1953, -2060, -2074, -2072, -2098, -2089, -2028, -1959, -1854, -1644, +-1398, -1283, -1268, -1248, -1182, -1072, -890, -682, -550, -579, +-696, -777, -895, -1075, -1200, -1276, -1388, -1500, -1535, -1567, +-1691, -1794, -1796, -1789, -1840, -1849, -1829, -1869, -1891, -1828, +-1766, -1801, -1843, -1812, -1752, -1668, -1512, -1323, -1175, -1038, +-838, -615, -418, -210, 55, 348, 633, 914, 1190, 1413, +1574, 1749, 1948, 2121, 2277, 2453, 2649, 2829, 2993, 3169, +3322, 3440, 3574, 3762, 3951, 4085, 4172, 4206, 4150, 3892, +3434, 2891, 2331, 1857, 1581, 1413, 1136, 656, 110, -372, +-782, -1098, -1280, -1407, -1590, -1721, -1736, -1761, -1873, -1987, +-2033, -2065, -2104, -2079, -1996, -1931, -1848, -1646, -1427, -1342, +-1348, -1339, -1274, -1138, -987, -916, -958, -1134, -1272, -1223, +-1114, -1097, -1183, -1310, -1449, -1583, -1608, -1534, -1488, -1492, +-1425, -1354, -1443, -1608, -1719, -1788, -1825, -1766, -1644, -1601, +-1639, -1602, -1467, -1349, -1281, -1193, -1080, -953, -741, -430, +-128, 86, 267, 475, 679, 839, 1001, 1193, 1375, 1559, +1784, 2003, 2123, 2169, 2257, 2412, 2590, 2787, 2995, 3169, +3315, 3485, 3694, 3854, 3916, 3935, 3936, 3804, 3454, 2971, +2451, 1967, 1635, 1473, 1285, 875, 316, -171, -543, -828, +-994, -1083, -1225, -1397, -1464, -1461, -1539, -1687, -1788, -1849, +-1918, -1948, -1906, -1874, -1857, -1744, -1552, -1433, -1452, -1507, +-1578, -1781, -2003, -2081, -2059, -1928, -1646, -1359, -1302, -1485, +-1693, -1807, -1813, -1659, -1389, -1185, -1107, -1036, -999, -1088, +-1248, -1390, -1517, -1594, -1551, -1420, -1300, -1210, -1115, -1036, +-1021, -1032, -1020, -953, -767, -443, -69, 235, 427, 533, +598, 667, 764, 912, 1100, 1311, 1551, 1765, 1898, 1959, +1999, 2079, 2213, 2396, 2599, 2770, 2917, 3073, 3234, 3375, +3491, 3576, 3640, 3689, 3654, 3498, 3183, 2716, 2240, 1860, +1581, 1368, 1133, 809, 409, 8, -333, -601, -822, -992, +-1086, -1152, -1209, -1254, -1336, -1459, -1573, -1645, -1693, -1742, +-1783, -1779, -1735, -1683, -1627, -1681, -1954, -2299, -2538, -2607, +-2467, -2172, -1906, -1806, -1805, -1782, -1733, -1676, -1559, -1394, +-1264, -1144, -1004, -937, -976, -1031, -1053, -1077, -1112, -1120, +-1110, -1078, -963, -768, -596, -516, -490, -460, -397, -267, +-71, 145, 335, 474, 590, 667, 673, 665, 710, 816, +963, 1144, 1312, 1403, 1468, 1580, 1715, 1821, 1918, 2018, +2108, 2225, 2406, 2610, 2767, 2875, 2963, 3023, 3046, 3081, +3159, 3215, 3167, 3020, 2749, 2328, 1876, 1530, 1281, 1055, +809, 533, 195, -170, -442, -604, -751, -908, -1028, -1138, +-1275, -1381, -1434, -1482, -1557, -1620, -1660, -1739, -1860, -1961, +-2043, -2170, -2302, -2369, -2393, -2371, -2280, -2167, -2101, -2071, +-2004, -1871, -1696, -1490, -1280, -1114, -1005, -929, -888, -888, +-912, -939, -950, -943, -907, -857, -809, -758, -703, -648, +-599, -543, -470, -369, -221, -53, 91, 192, 259, 313, +353, 396, 448, 492, 540, 629, 751, 862, 957, 1039, +1102, 1161, 1220, 1290, 1354, 1423, 1533, 1659, 1763, 1839, +1888, 1912, 1957, 2049, 2148, 2218, 2257, 2279, 2304, 2346, +2413, 2442, 2381, 2280, 2199, 2045, 1764, 1419, 1044, 687, +438, 311, 172, -106, -457, -772, -1042, -1265, -1385, -1431, +-1488, -1507, -1456, -1428, -1505, -1656, -1801, -1936, -2056, -2121, +-2128, -2133, -2137, -2063, -1974, -1971, -2036, -2086, -2067, -1981, +-1808, -1566, -1351, -1215, -1097, -975, -916, -923, -919, -873, +-809, -718, -596, -509, -495, -497, -467, -430, -423, -416, +-379, -316, -228, -114, 1, 62, 79, 108, 157, 191, +206, 238, 291, 364, 458, 556, 629, 654, 672, 735, +832, 924, 1019, 1117, 1203, 1285, 1369, 1437, 1468, 1479, +1520, 1593, 1637, 1650, 1652, 1649, 1662, 1699, 1748, 1760, +1729, 1698, 1708, 1762, 1823, 1801, 1618, 1329, 1026, 756, +578, 474, 352, 162, -50, -265, -507, -749, -926, -1032, +-1111, -1141, -1141, -1207, -1348, -1478, -1553, -1642, -1739, -1796, +-1849, -1909, -1916, -1862, -1832, -1860, -1879, -1862, -1845, -1825, +-1757, -1659, -1569, -1445, -1288, -1155, -1088, -1053, -1004, -939, +-869, -787, -711, -665, -629, -574, -506, -461, -453, -448, +-427, -395, -340, -269, -204, -154, -117, -74, -38, -23, +-3, 44, 112, 194, 272, 334, 394, 448, 502, 583, +657, 702, 749, 814, 887, 946, 985, 1012, 1028, 1053, +1111, 1190, 1244, 1285, 1312, 1307, 1293, 1282, 1281, 1303, +1332, 1358, 1373, 1374, 1369, 1391, 1434, 1441, 1354, 1160, +923, 712, 575, 540, 532, 441, 259, 38, -192, -413, +-577, -670, -733, -789, -819, -848, -924, -1035, -1122, -1182, +-1261, -1338, -1398, -1464, -1511, -1486, -1407, -1345, -1337, -1366, +-1406, -1442, -1439, -1385, -1320, -1243, -1134, -1011, -905, -846, +-815, -784, -736, -663, -583, -515, -470, -428, -373, -318, +-288, -283, -299, -311, -289, -240, -176, -114, -60, -11, +43, 104, 150, 182, 226, 294, 374, 443, 492, 514, +523, 546, 589, 641, 692, 733, 763, 793, 814, 833, +872, 927, 973, 1006, 1032, 1041, 1048, 1073, 1109, 1136, +1134, 1100, 1051, 997, 966, 966, 973, 975, 971, 974, +999, 1024, 1017, 980, 912, 809, 715, 646, 574, 491, +396, 292, 171, 18, -148, -312, -460, -545, -562, -549, +-535, -528, -537, -569, -628, -687, -739, -801, -850, -865, +-856, -850, -859, -879, -914, -979, -1057, -1106, -1120, -1098, +-1036, -956, -878, -822, -789, -760, -734, -704, -661, -614, +-560, -501, -451, -414, -388, -388, -403, -403, -379, -345, +-301, -255, -197, -125, -55, 16, 74, 116, 165, 216, +279, 346, 400, 443, 457, 458, 466, 470, 477, 506, +536, 550, 575, 603, 626, 653, 689, 713, 722, 738, +753, 758, 755, 749, 729, 683, 612, 536, 478, 462, +492, 524, 522, 492, 455, 437, 458, 509, 583, 649, +679, 663, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +2398, 4241, 1822, -104, -2974, -3969, -1015, 2534, 5246, 2125, +-408, -963, -1874, 2241, 5812, 2911, 879, -1120, -2932, -167, +3413, 5843, 2167, -1350, -2209, -3612, 1120, 4346, 2953, 733, +-2387, -1968, -41, 2461, 3675, 450, -1487, -2492, -2115, 513, +994, 1162, -20, -1801, -1434, -1350, 104, 230, -1487, -743, +-1633, -1298, -408, -2031, -1078, -1204, 450, 1623, -1895, -2366, +-2670, -1979, 502, 251, -1267, -3351, -3351, -52, 481, 387, +670, -2146, -1905, -921, -377, 1162, 1434, 869, -1141, -1968, +-984, 10, 1769, 1455, -1382, -952, 240, 1099, 1811, 523, +-575, -261, 2303, 3005, 157, -596, -94, -209, 1706, 2481, +157, -1361, -219, 984, 408, 2565, 2754, -1885, -1675, -20, +198, 1947, 3319, -188, -4775, -1696, 848, 879, 3235, 1015, +-4702, -4272, -387, 418, 1005, 1853, -1026, -4524, -2324, -272, +-1015, 1361, 1277, -2523, -3152, -1602, -638, -94, 1403, -544, +-3183, -1801, -1392, -1047, -52, 586, -471, -900, -356, -2042, +-1602, 1371, 2188, 952, -848, -2481, -2199, 1340, 6168, 4670, +-261, -3099, -5435, -2597, 3717, 6817, 4241, -932, -2324, -3005, +-272, 7016, 5843, 712, -2335, -4743, -1916, 3665, 7498, 3916, +-2691, -3811, -3330, 335, 5309, 4000, -377, -3340, -3309, -555, +2618, 4346, 1570, -2911, -3759, -2691, 52, 2607, 1706, -1183, +-3204, -1748, 62, 1225, 1508, -1235, -2649, -1822, -356, 565, +198, -136, -1350, -1183, 178, 188, -251, -366, -1005, -1162, +-219, 73, 136, -146, 104, 251, 282, 1026, 617, 136, +-157, 356, 1518, 1528, 1120, 293, -62, 649, 1256, 1392, +1120, 481, 178, 481, 1057, 1288, 848, 586, 240, 230, +617, 523, 397, -31, -272, -115, 10, 429, 261, -356, +-733, -659, -492, -879, -1267, -1706, -1843, -1151, -858, -1382, +-2010, -2565, -2659, -2199, -1811, -1989, -2188, -2199, -2104, -1968, +-1916, -1309, -1748, -2544, -2324, -2544, -2000, -1560, -1843, -2199, +-2345, -1298, -879, -952, -911, -1549, -1455, -261, 743, 879, +125, -397, 31, 544, 1759, 2094, 1277, 1015, 890, 1864, +2534, 3424, 3592, 2345, 1885, 2345, 3330, 3728, 3969, 3256, +2398, 2628, 3560, 3895, 3675, 3424, 2282, 2345, 3110, 3194, +3131, 2733, 2241, 1801, 2136, 2282, 1759, 1434, 848, 429, +575, 973, 691, 83, -481, -837, -921, -963, -942, -1853, +-2356, -2513, -2628, -2523, -2775, -2995, -3665, -3853, -3665, -4126, +-4199, -4366, -4482, -3654, -2481, -1497, -1780, -3958, -5801, -5141, +-3434, -2167, -2146, -3550, -5456, -4880, -2534, -1539, -1329, -1298, +-2230, -3361, -2136, 439, 1350, 1235, 1256, -774, -1926, -31, +2125, 2639, 1371, 115, -1026, -261, 2680, 4251, 3571, 2597, +1905, 1717, 2712, 4346, 4890, 3487, 2534, 2324, 2597, 3958, +4513, 3906, 3078, 2408, 1675, 1581, 1570, 1905, 2806, 3738, +3916, 2178, 1696, 2199, 1926, 2670, 2419, 251, -356, -10, +565, 848, 1026, 1078, -1026, -1738, -513, -806, -324, 492, +-1110, -2440, -2199, -1005, -251, -460, -1141, -3455, -4942, -4084, +-2921, -2199, -2303, -3141, -4346, -4628, -3822, -3068, -2879, -3696, +-4754, -4670, -3529, -2010, -691, -837, -2241, -3675, -3686, -2869, +-2733, -2230, -2345, -4000, -3853, -2262, -1644, -1455, -1047, -649, +-1225, -764, 481, 544, 523, 1151, 921, -10, 460, 1246, +816, 628, 1015, 418, 366, 1434, 2230, 2576, 2440, 2502, +2565, 2461, 3675, 3770, 2879, 2743, 2324, 2848, 3267, 3707, +3749, 2230, 1895, 3152, 4723, 3183, 1508, 1005, -157, 1748, +4461, 5340, 2314, 83, 1120, 879, 3141, 5508, 1958, -1267, +-1246, -1256, 984, 3581, 3225, -157, -2586, -1780, -1141, 1926, +3382, 104, -2649, -4021, -2461, 513, 2597, 1392, -2858, -5194, +-5424, -3393, -586, -209, -2230, -4628, -5047, -3539, -1686, -764, +-2324, -5278, -5655, -3623, -1539, 377, 649, -1487, -3057, -3382, +-2722, -2356, -2775, -3099, -3927, -3633, -2251, -2073, -1926, -921, +-1487, -586, 670, -125, 167, -366, 0, 1235, 1403, 2178, +523, -1319, -387, -83, 1110, 2691, 1717, 1110, 555, 1172, +3382, 3790, 4366, 2932, 952, 1424, 2282, 4178, 4356, 3330, +1968, 942, 1958, 3089, 3623, 3057, 1665, 764, 1309, 1769, +3057, 3675, 4209, 4838, 1706, 963, -136, -397, 3089, 4325, +4534, 837, -1769, -565, -1193, 1665, 4377, 785, -125, -429, +-1926, 712, 2984, 3623, 418, -2796, -3235, -4230, -209, 2858, +827, -1340, -3738, -4021, -2335, -94, 219, -2356, -4262, -4743, +-3770, -1497, -513, -1811, -4241, -5655, -4220, -2461, 0, 2021, +-209, -2869, -4503, -4649, -3267, -1895, -523, -2387, -4597, -3801, +-2775, -1864, -115, 534, -932, -2282, -1466, 397, 994, 1822, +1853, -565, -2094, -356, 1068, 932, 1790, 1277, -680, -209, +2042, 2838, 2785, 3173, 2680, 1036, 1508, 3665, 3393, 3194, +3288, 2104, 1790, 2817, 4440, 3843, 2408, 2115, 1864, 2450, +3529, 3267, 1895, 1790, 2262, 2858, 3162, 4440, 6398, 3361, +198, -1193, -2073, 1602, 5885, 5874, 1288, -2607, -1696, -356, +2209, 5550, 1790, -1727, -1089, -1371, 544, 3194, 3539, 272, +-3476, -4084, -3235, 178, 3508, 1748, -2733, -5340, -4639, -1413, +1309, 858, -2293, -4880, -4984, -3738, -2063, -1801, -3194, -4377, +-4157, -2314, -324, 1633, 1675, -2387, -5581, -5120, -2900, -806, +41, -1958, -5508, -5047, -1905, 890, 952, -575, -1612, -2785, +-1183, 1623, 1968, 1267, 1256, 691, -670, -691, 1110, 1445, +754, 555, -481, -513, 1518, 3560, 3225, 1905, 2125, 1864, +2251, 3267, 2712, 2963, 2827, 2607, 2921, 2199, 2534, 3466, +3319, 2628, 1445, 1172, 2073, 2136, 2754, 2680, 1968, 2555, +2618, 2377, 1947, 2251, 2303, 4419, 5927, 1455, -1225, -2858, +-2817, 764, 4764, 5571, 146, -1822, -921, -2021, 1979, 5895, +1340, -1759, -2429, -3906, -1267, 2502, 3790, -418, -4042, -3895, +-4010, -481, 2031, -387, -3822, -5131, -4000, -2534, 261, 356, +-3277, -6042, -6786, -5581, -2775, 492, 125, -1916, -1476, -764, +-1738, -2188, -2461, -5299, -5110, -1843, -1727, -3518, -3403, -2701, +-2995, -743, 1277, -62, -2387, -2209, -743, -785, 1518, 3026, +754, -869, -1319, -984, -94, 1246, 1706, -261, -1036, 816, +2000, 2827, 3738, 2701, 1120, 701, 1780, 2785, 3372, 4105, +3204, 1508, 596, 1885, 3225, 3885, 4000, 1853, 20, -230, +1413, 3612, 4220, 3874, 2586, 837, 1120, 2628, 3319, 6440, +5864, -73, -2241, -3916, -2167, 3152, 6461, 4565, -2052, -2670, +-1068, -1151, 4021, 5173, -1350, -2356, -2157, -2890, 240, 2775, +1612, -3057, -4052, -3277, -2963, 502, 1036, -2356, -4848, -4010, +-2586, -2167, -743, -2010, -4649, -5183, -5089, -4576, -4272, -2125, +-1151, -2251, -523, -712, -2785, -2858, -3550, -5079, -5068, -3068, +-2419, -4555, -3633, -2104, -3047, -1015, -397, -1591, -2398, -2398, +460, 314, -272, 733, -157, -649, -136, 1047, 586, -1078, +-335, 240, -188, 1162, 2754, 2586, 1665, 1832, 2188, 1549, +2262, 3068, 2241, 1706, 2042, 3183, 2597, 1895, 3309, 2921, +2712, 2974, 1508, 921, 1162, 2858, 3602, 1727, 2063, 2450, +2743, 5309, 5225, 2345, -387, -1277, -1068, 565, 4241, 4335, +628, -795, -827, -1633, 1508, 5120, 2241, -1267, -1288, -1717, +-492, 3194, 2932, -1298, -3969, -3749, -2513, -219, 2220, 586, +-3529, -4806, -4094, -2419, -41, -303, -3141, -5623, -6032, -3927, +-2083, -2659, -3728, -4408, -3885, -1612, 377, 324, -2125, -4094, +-4576, -4628, -4010, -2628, -2743, -4199, -3382, -3497, -3036, -785, +-858, -628, -1329, -1686, -335, 52, 1141, 1172, -198, 146, +240, -628, -83, -146, 115, 1434, 1989, 1706, 450, 785, +2199, 3351, 4084, 3215, 1497, 680, 1497, 2282, 3822, 4922, +3110, 1078, 1120, 2104, 2921, 3948, 3382, 1131, -345, 544, +2450, 3382, 4565, 3612, 1623, 1235, 1832, 2314, 3801, 7864, +4188, -1686, -3340, -4492, -565, 5445, 8891, 2607, -4063, -1905, +-1696, 743, 7100, 4325, -2492, -3728, -3623, -2356, 1267, 4513, +1602, -4115, -4733, -4576, -2272, 2000, 1717, -2481, -6073, -5644, +-3906, -942, 596, -1738, -5110, -8032, -7330, -3969, 83, 2042, +1277, -963, -3665, -4325, -3309, -1466, -2775, -4346, -3581, -4639, +-4419, -2618, -1675, -1361, -774, 282, -1843, -3403, -659, 1769, +2303, 1759, 104, -2377, -2104, 1895, 3434, 764, -994, -1759, +-1644, 973, 4031, 5152, 2356, 670, 1068, 460, 2932, 5602, +4733, 1979, 418, 1853, 2775, 4366, 5969, 3183, 335, 649, +1769, 2659, 3518, 3403, 2125, 1036, 1822, 3225, 3476, 3602, +3623, 3215, 3874, 3319, 911, -617, -1309, 471, 2963, 4471, +2199, -1864, -1895, -471, 1424, 3937, 2754, -754, -1885, -1612, +0, 1602, 2125, -125, -3874, -4136, -2513, 429, 2230, 303, +-3445, -5990, -4283, -1445, 492, -136, -3612, -5874, -6220, -4555, +-2921, -2555, -2125, -2764, -3445, -1424, 314, -481, -1382, -3707, +-5602, -4974, -2911, -670, -2565, -4105, -4031, -4199, -1235, -230, +-754, -1005, -2481, -1382, 418, 774, 1319, 806, 146, -272, +-754, 136, 125, -293, 345, 1047, 1204, 1099, 2115, 1853, +869, 2104, 2743, 2680, 2188, 2262, 3110, 2272, 3466, 4387, +2209, 2021, 2838, 2827, 2513, 2262, 2775, 1099, 565, 2764, +2879, 3173, 3874, 3330, 1644, 785, 2220, 2272, 1665, 2324, +1424, 2942, 5068, 2052, -1225, -3717, -2597, 1288, 5267, 6094, +-345, -3194, -1612, -1350, 2586, 4440, 146, -3141, -4366, -3455, +-1172, 1738, 3183, -293, -3811, -5110, -4775, -1528, 795, -272, +-3497, -5372, -4524, -2911, -994, -1570, -4398, -6199, -5885, -3089, +209, 2167, 1214, -3152, -4304, -3162, -3141, -1644, -2157, -3832, +-4984, -4000, -1696, -2345, -2471, -555, -1005, -1675, -52, -251, +-565, -94, 1141, 911, -764, 733, 1120, -52, -125, 41, +-219, -73, 1832, 2083, 733, 1350, 2303, 2188, 2733, 2701, +1885, 1466, 1832, 3089, 3267, 3989, 3340, 1696, 1926, 1832, +2743, 2900, 2042, 1403, 795, 1706, 3068, 3246, 2534, 2680, +2293, 2555, 2628, 3340, 5183, 2282, 628, -659, -2262, 314, +4293, 5948, 1131, -1780, -1120, -2063, 1047, 5550, 2398, -2000, +-1403, -1466, -1811, 1015, 2502, -1110, -3895, -3811, -3550, -1246, +1623, 1361, -2419, -4963, -4387, -3319, -1078, -450, -2764, -5016, +-5676, -4660, -3874, -2607, -1466, -1036, -62, -345, -2251, -4010, +-2806, -2094, -2628, -1455, -2523, -4262, -4691, -3749, -1811, -649, +439, -251, -3036, -3822, -1277, 1874, 3089, 2199, 303, -1591, +-1445, 1424, 2712, 858, -565, -911, -733, 1015, 3340, 3246, +2125, 1644, 890, 1183, 2691, 4031, 3759, 2408, 2083, 2398, +3099, 4031, 3602, 2502, 2356, 2199, 1958, 1204, 649, 1686, +2440, 3738, 3497, 1727, 1623, 1759, 2754, 3277, 2398, 1539, +1078, 4126, 4482, 733, -62, -1560, -2398, 649, 4524, 3235, +-565, 460, -387, -2869, 1602, 4398, 240, -1570, -1811, -3916, +-2576, 2063, 2000, -2282, -3298, -2858, -3173, -1172, 20, -2272, +-4534, -3267, -1979, -2659, -1748, -2618, -5801, -6608, -4492, -2366, +-596, 2544, 1686, -3372, -4314, -2450, -2869, -2230, -921, -2984, +-5152, -3717, -1874, -2754, -2199, -492, -2021, -2932, -1591, -209, +282, 586, 1570, 94, -1047, 691, 1319, 1068, 125, -869, +-932, -638, 963, 2607, 2398, 2115, 1392, 471, 1591, 2377, +3078, 2879, 1633, 1759, 2618, 3696, 4021, 3560, 2440, 1183, +1131, 1937, 2199, 2157, 2356, 2042, 2345, 2534, 2241, 2136, +2230, 2838, 2010, 1717, 1612, 932, 2890, 4052, 2544, 146, +-2419, -2639, 31, 3686, 4461, 1256, -1298, -2303, -2345, 1288, +3843, 1717, -460, -2523, -3874, -1947, 1026, 1476, -649, -2618, +-3497, -3120, -1183, 178, -1141, -3068, -3581, -3717, -2806, -1445, +-2063, -4272, -6178, -6712, -4848, -680, 2649, 2942, -649, -4565, +-5215, -3969, -356, 1591, -900, -3623, -5874, -6073, -3424, -994, +785, -62, -2869, -4188, -3916, -209, 3675, 3885, 2042, -1403, +-3235, -1277, 2251, 3665, 1832, -638, -2911, -2712, 1141, 4105, +5079, 3162, -31, -638, -62, 2513, 5110, 4461, 2607, 879, +900, 2890, 4754, 5120, 3361, 1434, 816, 1172, 2387, 2858, +2377, 1916, 1937, 2042, 2115, 2796, 2764, 1979, 3235, 4429, +2157, 921, 408, 596, 1874, 2848, 3183, -471, -1968, -219, +471, 2366, 3623, 1487, -1204, -2000, -649, 816, 1277, 1246, +-1570, -4063, -3571, -1487, 1141, 1665, -387, -3958, -5456, -3790, +-1340, 670, -293, -3204, -5330, -5990, -4733, -4010, -3759, -2188, +-94, 1466, -20, -2419, -4241, -4356, -1204, 638, -1057, -3937, +-5225, -5340, -3770, -764, 83, -2293, -2890, -2618, -2806, 827, +3382, 2502, -167, -1225, -743, -523, 3026, 3675, -596, -2806, +-1979, -31, 1508, 3560, 3110, 62, -198, 1780, 3256, 3309, +3864, 2984, 502, 1309, 3581, 3749, 3361, 3319, 1822, 1005, +2555, 3424, 1748, 670, 1968, 2063, 2607, 3497, 1916, 837, +1874, 3707, 3288, 1717, 2241, 2649, 1811, 2461, 1759, -534, +-83, 2377, 3592, 1382, -272, 83, -900, -41, 3434, 2125, +-586, -94, -806, -1581, -261, 1204, -366, -2471, -2272, -2188, +-1455, 73, -774, -3445, -4084, -2251, -1256, -827, -1518, -4555, +-6691, -6262, -4565, -3403, -1727, 1309, 2146, -659, -2701, -4042, +-4545, -1434, 733, -596, -4052, -5361, -4356, -3487, -1570, -1193, +-1759, -3215, -3434, -1696, -764, 1350, 3120, 2534, 125, -1298, +-136, 1665, 1989, 1089, -963, -3099, -1602, 1392, 3204, 3110, +1968, 1298, 198, 1612, 3078, 2712, 2806, 2167, 2073, 2314, +3330, 4220, 3110, 2063, 1329, 1843, 3016, 2157, 921, 523, +973, 3215, 4796, 3686, 1193, 52, 1790, 3340, 3225, 5058, +4073, -125, -534, 73, 198, 1151, 4230, 2984, -2670, -2157, +356, -209, 2052, 3864, -617, -3089, -785, 659, 0, 513, +-157, -3822, -3937, -1528, -879, -764, -345, -2481, -5351, -4272, +-1937, -1057, -1131, -2911, -6115, -8294, -6503, -2817, 41, 2817, +2345, -1141, -5037, -5990, -3351, -1099, 1319, 157, -4188, -7204, +-6712, -2555, 209, 827, -481, -4136, -5801, -2209, 2314, 4272, +3948, 1371, -2104, -2785, 230, 3235, 3895, 1099, -1853, -3403, +-3110, 2481, 5780, 4272, 2136, -1225, -1591, 952, 4419, 6126, +3057, 1015, 890, 754, 3518, 5257, 4471, 2890, 513, 502, +1015, 2262, 3497, 2209, 1078, 1131, 1759, 2523, 3047, 2869, +2178, 1748, 1549, 2063, 3822, 3518, 2104, 586, -795, -1026, +94, 2974, 2157, -157, 188, -1141, -1727, 1193, 2094, 492, +-1047, -1340, -2199, -2827, -157, 439, -1015, -1350, -2597, -3948, +-3927, -2031, -1162, -1864, -1843, -3277, -4681, -4262, -4021, -4974, +-5958, -5058, -2701, 324, 2670, 1036, -3005, -5204, -4764, -1989, +555, 73, -3277, -6157, -6367, -4230, -963, 52, -1581, -3246, +-4063, -3665, 73, 3466, 2785, 1151, -607, -1612, -157, 2712, +3110, 178, -2618, -2618, -1068, 942, 3707, 2879, 460, 83, +387, 2083, 2817, 3623, 2932, 366, 1623, 3152, 3141, 3382, +3016, 2262, 1602, 2544, 2607, 324, 219, 1633, 2083, 2712, +3466, 1989, -198, 1183, 4042, 3832, 2680, 2167, -10, -1403, +596, 3979, 3225, 377, -282, -2722, -2586, 2104, 4356, 2031, +-1591, -2555, -2481, -659, 3654, 3393, -1309, -3445, -4115, -3424, +-41, 2220, 272, -3675, -4911, -4859, -3330, 62, 680, -2282, +-5613, -6691, -6409, -5319, -3078, -1759, -848, 1151, 890, -2052, +-4262, -4796, -3194, 115, 1424, -2063, -6712, -7393, -4618, -1434, +1193, 324, -4534, -6555, -3874, -136, 2995, 4335, 2293, -1518, +-2785, -481, 2775, 3539, 2555, -513, -4492, -2796, 774, 3162, +4754, 2063, -565, -994, 492, 3749, 4356, 3853, 2712, 356, +1350, 3309, 3790, 4366, 3434, 1476, 397, 1225, 2513, 2272, +2282, 1979, 1151, 2335, 3885, 3319, 1958, 1497, 1633, 1204, +2178, 2712, 816, 356, 1235, 3874, 3434, 418, -460, -3005, +-2492, 1895, 4743, 3288, -471, -1005, -2094, -2042, 2408, 2115, +-1633, -2775, -3759, -3361, -209, 2858, 1214, -3539, -5288, -5445, +-3246, 691, 984, -2513, -6869, -7613, -5906, -3455, -900, -722, +-837, -932, -1340, -1581, -2042, -2398, -2251, -1392, -806, -2073, +-3979, -4115, -4555, -4565, -2188, -680, -1801, -3016, -2879, -1686, +565, 3026, 4408, 1853, -1748, -1361, 324, 1989, 2775, 1005, +-1047, -1905, -146, 2419, 2900, 2544, 1508, 575, 806, 1706, +2932, 3937, 3759, 3110, 2701, 2073, 2586, 3989, 3822, 2775, +2157, 1329, 659, 1183, 2827, 2555, 2220, 3309, 1874, 1340, +2586, 3057, 2565, 1654, 2104, 1864, 1780, 2806, 1497, 104, +1047, 994, 460, 272, 125, -20, 20, 1633, 1015, -701, +240, 10, -1036, -659, -1214, -1947, -994, -167, -1151, -2995, +-3665, -3581, -2670, -952, -1466, -3330, -4094, -4691, -5236, -4890, +-4157, -3330, -1350, 932, 827, -1686, -2701, -2293, -1445, -1172, +-1979, -2251, -3906, -3298, -722, -1068, -3131, -3811, -3162, -3068, +-1675, 198, 586, 52, 879, 2115, 1790, 1612, 1686, 1246, +366, -104, -188, -125, 219, 1371, 1612, 869, 1235, 1277, +1214, 1497, 2209, 2754, 2440, 3099, 3246, 2586, 3382, 3780, +3110, 2262, 1738, 1434, 1162, 2083, 2701, 2356, 2345, 2241, +1864, 2209, 3057, 3330, 2733, 1717, 1151, 1078, 2042, 2827, +2303, 1036, 638, 1267, 785, 743, 586, -502, -335, 952, +1455, 471, 41, -10, -1057, -754, -429, -2010, -1727, -733, +-816, -1235, -1717, -2701, -3948, -3099, -1801, -1748, -2366, -3173, +-4398, -5288, -3989, -3612, -4387, -2670, 94, 2262, 1350, -816, +-3382, -5854, -2775, 1256, 1288, -1518, -4597, -6482, -6000, -1759, +1769, 450, -2942, -4901, -5204, -2523, 2502, 5414, 3696, 670, +-1885, -2555, 1256, 4230, 3864, 481, -3235, -3152, -1026, 2890, +5508, 2450, -848, -1047, 10, 3445, 4859, 4157, 1864, 146, +2607, 3372, 3550, 4586, 3330, 764, -125, 0, 1183, 2262, +2031, 1581, -251, 575, 2502, 2984, 2492, 1277, 523, -471, +471, 2241, 3288, 2848, 1246, -240, -774, 1654, 4031, 3466, +1078, -1497, -2146, 125, 3162, 3005, 722, -1895, -3927, -3476, +-1727, -1277, -2848, -3455, -3539, -3937, -3361, -2858, -2796, -3298, +-3508, -3665, -3215, -1759, -1989, -3330, -4230, -5079, -3633, 932, +6063, 8943, 5372, -324, -1403, 680, 4000, 4398, 1350, -1947, +-5791, -5236, -2335, -3644, -4806, -5655, -7383, -7571, -6440, -2042, +1727, 1769, 1822, 586, 324, 3633, 7581, 8608, 4743, 2042, +2953, 4461, 6786, 7864, 5958, 2063, -251, -481, -659, 387, +167, -2408, -3853, -4094, -2440, -397, -240, -73, -1633, -1591, +932, 911, 1602, 2649, 2974, 3529, 3183, 3654, 4471, 3979, +3895, 2597, 94, -586, -240, 1131, -146, -2419, -2953, -3644, +-1508, -314, -2806, -4880, -5047, -2576, 62, 2314, 2398, -125, +0, 827, 397, 1089, 1288, 20, -858, -282, 1120, 743, +219, -1151, -3455, -2712, -1172, -450, -1183, -2974, -4754, -5299, +-3644, -2806, -2890, -1350, 3288, 8503, 7068, 2649, -774, -2293, +1958, 5634, 5215, -921, -7561, -6398, -4691, -3979, -1727, -2817, +-4942, -5843, -3927, -73, 1633, 6388, 7267, 2513, 1267, 2146, +4859, 5518, 3434, 1057, -2942, -2282, 1256, 1141, 617, -932, +-1476, -1068, -984, 879, 994, 1947, 3361, 2649, 2356, 1853, +3204, 4953, 3728, 1623, 157, 282, 1319, 1089, -492, -1340, +-1036, 575, 1905, 984, 73, -73, 1539, 2712, 1811, 1696, +1885, 1246, 816, 240, -523, 1183, 1528, -890, -3309, -4649, +-2649, -178, 1445, -31, -2974, -1885, 272, 523, 219, 83, +146, 1623, 3026, 942, -2146, -2440, -1361, -219, -712, -3068, +-4702, -4628, -4230, -4147, -4565, -4293, -1968, 1895, 6649, 8671, +6744, 2900, 104, -827, 136, 2838, 1277, -4681, -9247, -9048, +-7225, -4723, -638, -178, -4178, -6189, -1193, 3518, 6073, 8629, +5979, 879, -377, 1455, 2817, 1885, 439, -1549, -4838, -4105, +-251, 2021, 3267, 2251, -293, -1926, -1047, 2188, 3424, 2544, +1057, -492, -754, 1089, 3529, 3393, 1141, -439, -575, -52, +1602, 2942, 2178, -513, -1141, 774, 1549, 2387, 1738, -282, +-1487, -1350, 1068, 2356, 1329, 837, 722, -439, -691, -513, +-1141, -1591, -1256, -575, -1319, -816, 502, -429, -1235, -774, +-1110, -1455, -471, 261, 513, 722, 754, -848, -2796, -2209, +-1727, -1361, -952, -3225, -5948, -6534, -4702, -2806, -3110, -3256, +-209, 5812, 10618, 8713, 2827, -429, -691, 1570, 1319, -2659, +-6775, -9686, -6545, -5246, -6608, -3047, -1968, -1801, -638, -157, +3330, 6032, 7990, 6995, 575, -1047, 921, 2167, 1769, -3089, +-4660, -3445, -837, 3204, 1528, 240, 1560, 1748, 1623, 366, +460, 596, 460, 1309, -125, -1298, 345, 2471, 2209, 1298, +1392, 1204, 2021, 2932, 1926, -125, -73, 712, -387, -492, +219, -1089, -1497, -73, -638, -502, 1843, 2785, 638, -1015, +1141, 911, -356, 10, -2963, -4335, -1686, 1340, 942, -1476, +-1141, -2010, -2513, 314, 335, -1340, -240, 366, -272, -534, +188, -837, -2827, -2628, -4796, -5864, -3560, -2838, -3696, -4534, +-3550, -3194, -1591, 4283, 9613, 10535, 6011, 691, -2104, -1885, +1853, 2209, -3330, -9173, -11854, -8608, -4545, -1926, 167, -1937, +-2754, -1403, 1570, 6304, 7362, 5833, 2722, -1256, -2063, 94, +1591, 733, -1979, -3372, -2104, 565, 3612, 4230, 2356, 984, +272, 345, 1560, 722, -492, -377, -1256, -481, 994, 1267, +2209, 1633, 1560, 2419, 1759, 2136, 1916, 1068, 890, 146, +701, 345, -272, 219, -795, -617, 136, 565, 1089, 1267, +2146, 1937, 513, 858, 1371, 659, 136, -2345, -4241, -3592, +-1225, 1099, 701, -146, -1403, -2241, -1329, 261, 921, 712, +1717, 1382, -345, -240, -555, -1497, -1675, -2282, -3277, -3843, +-3215, -3215, -4230, -2534, -1026, -2073, -1675, 827, 7927, 13341, +9603, 2628, -4419, -5728, -2701, 303, 1225, -6147, -10388, -8199, +-7173, -3372, 1727, 4492, 1801, -2722, -377, 2607, 5246, 9561, +5874, -1413, -4513, -3131, 565, 1099, 1183, -879, -3330, 52, +2440, 3675, 4387, 3497, 2324, -1298, -1549, -481, -1256, 1183, +1256, -1309, -513, 1654, 3361, 3288, 2869, 3633, 1989, 1528, +2293, -167, -219, 1633, 575, -1560, -2366, -879, 1068, 2220, +2659, 178, -2146, 952, 3780, 3571, 2827, -314, -3204, -2063, +397, 335, -1319, -2911, -3853, -3612, -659, 2324, 1780, 1193, +408, -2419, -2722, 167, 1214, 2115, 1570, -1727, -3654, -3256, +-638, -240, -1665, -3016, -5236, -4335, -2010, -1947, -1602, -1528, +-2806, -1717, 2220, 8891, 12472, 7791, 418, -5979, -6063, -1696, +806, -1131, -6953, -10587, -9110, -4513, -743, 2157, 3204, 1172, +-1937, -1235, 3152, 6398, 7006, 4063, -1612, -5843, -3036, 1947, +2230, 450, -1727, -2125, -251, 3738, 6314, 3623, 1434, -837, +-2890, -2094, -879, 523, -73, -1350, -1068, -1277, 2104, 6681, +5414, 2911, 816, 261, 1822, 2345, 1916, -523, -2565, -1696, +-1005, -952, 680, 2136, 1727, 534, -994, 0, 2995, 3811, +2785, -471, -2031, 366, 62, -1350, -3173, -5016, -2628, -418, +827, 31, -1801, 282, 586, 10, 743, -837, 52, 1769, +816, -754, -2199, -1340, -1319, -2293, -3162, -5487, -4450, -2094, +-1979, -2670, -3434, -2932, -2324, -617, 3267, 9592, 13006, 7927, +-261, -6702, -7466, -1309, 4178, 963, -8011, -14368, -11362, -4366, +1487, 6105, 2743, -2670, -3508, -1905, 3445, 8744, 9131, 4576, +-3277, -7414, -4817, 1204, 5508, 3906, -1057, -4649, -3592, 1885, +7037, 7435, 2848, -2461, -5456, -4021, 481, 3173, 2869, -890, +-3152, -1214, 2408, 7550, 8074, 3529, 963, -754, -198, 2188, +1947, 607, -2251, -3225, -1937, -932, 2178, 3078, 1989, 1288, +869, 2356, 2282, 2188, 1235, -1445, -1455, -701, 691, 282, +-2178, -2680, -3372, -1654, 1466, 1518, 1225, 52, -1036, -544, +-701, 460, 230, -1214, 125, -209, -104, 83, -879, -523, +-1424, -1131, -1937, -4157, -3592, -3361, -2251, -1204, -2481, -2911, +-1581, 2513, 9341, 13750, 10608, 1602, -5696, -4869, -1413, 1183, +240, -8534, -13781, -10995, -4691, 1403, 4524, 4524, 125, -3235, +-1057, 3267, 8524, 10262, 4524, -3989, -8377, -5539, 879, 5822, +5288, -251, -4325, -3686, 1225, 7728, 9592, 6000, -1099, -6838, +-6231, -1874, 3277, 4063, -157, -3885, -2932, 2523, 7843, 9718, +6073, 952, -837, -733, 303, 1424, 377, -2429, -3487, -2000, +-586, 1026, 3476, 3215, 1885, 2502, 3005, 2314, 1110, 670, +-1162, -2167, -366, -1078, -1801, -1455, -1926, -1518, -659, 890, +1057, 523, 429, -827, -408, 1487, 1151, -617, -1748, -1675, +104, 1864, 1937, -492, -3361, -3403, -1654, 0, 303, -1015, +-3571, -5005, -4220, -2796, -712, -83, 356, 4115, 8723, 10692, +8733, 2167, -3696, -6105, -7257, -4586, -2356, -3099, -4031, -7225, +-6765, -1979, 1392, 6555, 6011, -198, -795, -586, 1738, 5948, +4052, 544, -4147, -5791, -1403, 1131, 4220, 4639, 806, -188, +178, 2000, 4157, 4094, 1476, -3717, -5927, -4031, -1518, 1853, +3948, 2576, 1403, 2031, 3351, 5361, 5602, 3382, 157, -2743, +-3016, -1769, -523, -83, 73, 450, 429, 932, 1811, 2785, +3235, 3612, 2900, -565, -3298, -2764, -1874, -94, 1068, -649, +-1162, -2178, -1832, -387, 31, 2115, 1518, 178, -743, -2513, +-1068, -20, -439, -1267, -2900, -1696, 544, 1832, 2303, -198, +-2052, -2115, -2125, -1874, -2775, -2838, -3633, -4639, -3969, -3309, +-1089, 1675, 4335, 8838, 10723, 7697, 2764, -2890, -4880, -5665, +-3581, -1748, -5278, -6660, -6691, -6053, -3497, 115, 3550, 4649, +2576, 617, -1329, -764, 2272, 3110, 2199, -2356, -5016, -3340, +-230, 3361, 4021, 3235, 1801, -136, 942, 1832, 1466, 712, +-2083, -4346, -5120, -2869, 115, 1801, 3895, 3759, 2471, 3372, +4440, 3969, 3246, 1570, -1382, -3602, -2827, -1780, -1717, 303, +1665, 1162, 1455, 2754, 1885, 638, 1979, 2377, 701, 31, +-890, -3382, -3204, -1434, -1120, -230, 1497, 439, -1497, -1288, +-890, -335, 743, 628, -2241, -3696, -2220, -1602, -764, 649, +785, 680, 900, 366, -1277, -2125, -1853, -2282, -1905, -2440, +-4063, -3780, -3445, -2879, -2356, -2618, -1319, 2104, 7403, 11844, +10262, 4743, -1466, -6471, -6450, -4733, -4188, -3969, -4503, -4419, +-3885, -4325, -2555, 1204, 3696, 6042, 3539, -1769, -3780, -3036, +1099, 3560, 2042, -1120, -3319, -2785, 209, 3183, 4712, 4524, +2063, 356, -1162, -1926, -1162, -565, -1277, -2513, -3204, -2995, +-293, 2942, 5257, 5529, 4398, 3319, 1068, 617, 1434, -240, +-1267, -2146, -3529, -2900, -1392, 555, 1937, 2659, 3131, 2052, +1193, 1623, 952, 418, 178, -1780, -4052, -4450, -3204, -1361, +1204, 2000, 408, -1162, -879, 471, 1026, 1183, -52, -2680, +-3895, -3131, -2377, -1225, 366, 125, -879, 188, 1288, 1005, +1131, -607, -3843, -4733, -3696, -2680, -1434, -125, -628, -2146, +-2125, -2356, -3099, -973, 2890, 7163, 10535, 10074, 5330, -2199, +-7236, -8587, -7906, -2701, 345, -1905, -4586, -6744, -6251, -2303, +4052, 7938, 4534, -827, -3592, -5518, -2303, 3466, 5152, 3194, +-806, -3644, -3099, 795, 5110, 6911, 4963, 1068, -1696, -2995, +-1508, 209, 31, 83, -1811, -3665, -2387, 324, 4272, 6524, +5780, 3958, 879, 178, 1277, 2042, 2743, 1172, -1602, -2984, +-3717, -2754, 230, 3110, 4167, 3393, 2115, 41, -785, 62, +1654, 1434, -261, -1193, -3225, -3497, -806, 356, 2073, 2586, +429, -712, -3110, -2272, -492, -450, 1508, -52, -1916, -1843, +-2461, -1120, 680, 1487, 2220, 1267, -502, -2262, -3434, -2272, +-858, 261, 10, -1696, -2513, -2649, -2639, -2429, -2921, -2199, +-219, 3780, 11006, 13132, 10022, 3194, -5948, -10325, -9906, -4639, +827, -178, -2220, -4167, -7152, -4377, -104, 3895, 6566, 3110, +62, -3005, -5319, -1612, 2513, 4649, 4304, 1141, -1015, -1581, +733, 3948, 5351, 4377, 1539, -806, -2555, -2963, -3036, -2377, +-230, 261, 366, 973, 722, 3078, 5812, 5969, 5497, 2209, +-733, -1885, -2188, -492, -73, 534, 617, -952, -984, -261, +1361, 3895, 5330, 4660, 1068, -2293, -4167, -4178, -429, 2136, +2220, 1277, -1256, -2115, -1665, 73, 2104, 1309, 1979, 1466, +-1246, -1864, -2775, -2754, -1120, 764, 1256, -638, -1644, -1120, +-418, 2125, 3424, 1895, 460, -1885, -3780, -4063, -2157, -209, +240, 848, -240, -1654, -1256, -911, -963, -377, 2042, 6827, +9341, 9770, 6974, 335, -5539, -9090, -8451, -6534, -3413, 513, +2628, 1110, -1623, -2764, -1968, 1057, 3016, 3665, 900, -2534, +-3162, -2356, -209, 2241, 4555, 4764, 3780, 2314, 1015, 806, +1141, 2429, 2303, 754, -1539, -4304, -5236, -3696, -408, 3194, +4848, 4942, 3989, 2565, 2251, 2618, 2942, 2565, 1738, -209, +-1905, -2293, -1371, 670, 2125, 2911, 2125, 994, 733, 1204, +1864, 2073, 1141, -387, -1277, -2094, -1832, -1382, -450, 869, +1518, 2188, 1329, 356, -680, -1759, -408, 460, 198, -324, +-2230, -3246, -2492, -555, 1748, 2241, 1696, 20, -2282, -1811, +-429, 492, 1801, 1141, -911, -2188, -2513, -1811, -366, 869, +638, -890, -2188, -3602, -4565, -3508, 282, 7456, 13226, 13446, +7393, -1769, -8377, -10535, -6765, -1581, 198, 209, -1110, -3120, +-4503, -4157, -754, 2513, 3550, 3466, 73, -4147, -4785, -2481, +2209, 4660, 5257, 4890, 1968, 555, 62, 754, 2115, 2932, +2827, 136, -2879, -5204, -5309, -2607, 1015, 4052, 4733, 4052, +2701, 1769, 2565, 3487, 3644, 3351, 1686, -387, -1225, -2094, +-1151, 1078, 2398, 3152, 2597, 1591, 167, -345, 282, 0, +-167, 450, 890, 1131, 1246, 1015, 555, 0, 314, 335, +-418, -1141, -2010, -1602, -1193, 73, 1623, 1518, 1193, -450, +-1549, -1214, -1549, -1623, -733, -659, -806, -219, 575, 1769, +2398, 2429, 1214, -670, -2031, -2995, -2712, -1769, -869, -1350, +-1989, -2649, -4010, -2879, -1235, 1947, 8168, 12891, 14001, 8974, +-188, -8597, -13519, -12137, -6461, -2021, 1204, 2534, 607, -1780, +-3256, -2743, -460, 1968, 2680, 1267, -2282, -5068, -4220, -1256, +3120, 6974, 7843, 6503, 3707, -167, -2345, -3057, -2733, -691, +219, -178, -1466, -3277, -2199, 607, 2932, 5141, 5068, 3581, +1958, -492, -1078, -335, 167, 2000, 2869, 1675, 481, -984, +-1099, 167, 1172, 2377, 1717, -20, -984, -2241, -2523, -733, +1288, 2995, 4283, 2722, -272, -2366, -3183, -2230, -691, -83, +-764, -1790, -1717, -764, -41, 450, 439, -62, -293, -314, +-1120, -1759, -1602, -1246, -345, 303, -209, 83, 701, 858, +1183, -20, -1466, -2314, -2576, -1748, -1780, -2178, -1288, -1466, +-1487, -1780, -3288, -2094, 1413, 7833, 13708, 13247, 7634, -492, +-9100, -12577, -9906, -5990, -1288, 1476, 2670, 1895, -1947, -3434, +-3749, -3068, 418, 2513, 1612, -366, -3120, -3686, -733, 1759, +5456, 8252, 6681, 4105, 52, -3592, -4524, -4042, -314, 2534, +1874, 879, -1539, -3078, -1382, 1382, 3382, 4283, 3717, 2743, +1361, -523, -1036, -754, 837, 3068, 3372, 3141, 1727, -1089, +-2063, -1434, -408, 890, 1424, 1047, -94, -1581, -1717, -1141, +41, 1979, 2440, 1822, 1371, -387, -1885, -2712, -3330, -3016, +-2324, -680, 345, 523, 754, 335, -188, 240, 460, -450, +-743, -1727, -3005, -2764, -2440, -1602, -429, 607, 1476, 1581, +952, -167, -1591, -2565, -2733, -2712, -1874, -659, 146, 774, +178, -994, -2440, -3393, -2932, -335, 4922, 9341, 10587, 7456, +1026, -6105, -10388, -9676, -6985, -3340, 136, 3026, 2911, 806, +-1905, -5037, -5361, -3895, -764, 795, -125, -1654, -1790, -219, +1382, 3675, 5141, 4932, 3424, 1005, -1727, -4084, -3675, -1466, +397, 2262, 1916, 240, -942, -1727, -1110, -293, 900, 2858, +3057, 2974, 1759, -1424, -1623, -555, 1151, 3330, 3152, 2387, +324, -1686, -1727, -1937, -638, 858, 890, 1015, 377, -848, +-1424, -1204, -492, 397, 513, 607, -20, -795, -513, -1246, +-1654, -1560, -1979, -1183, -62, 670, 596, 219, -104, -764, +-1623, -2272, -2649, -2597, -1476, -764, -83, 377, 680, 890, +911, 670, -607, -1497, -2387, -2534, -2094, -1340, -219, 188, +492, 272, -272, -1665, -4241, -6503, -5539, -1455, 6000, 13781, +15111, 10838, 1686, -7990, -12545, -12503, -8503, -3057, 1424, 5330, +5487, 1916, -1843, -7016, -8315, -4838, -2345, 62, -20, -1706, +-1780, -879, 1832, 4545, 6367, 7163, 5791, 1591, -3036, -6126, +-7006, -3843, 387, 3005, 4063, 2565, 733, -596, -2366, -2639, +-2230, -397, 2628, 4461, 3916, 1602, -869, -1623, 523, 3173, +4838, 3937, 774, -1916, -3026, -3256, -2241, -240, 911, 2251, +2356, 596, -1298, -2953, -2220, -513, 659, 1413, 869, -586, +-209, -167, -1235, -1549, -2461, -1885, -439, 136, 83, -806, +-450, 1256, 1089, 1602, 544, -2649, -3016, -2366, -1141, 303, +586, 911, 785, 900, 1193, -575, -1801, -2303, -2534, -1005, +293, 848, 1057, 1036, 628, -513, -1371, -2471, -3550, -3612, +-2282, 1288, 7184, 12336, 12702, 7152, -1539, -9582, -13027, -10744, +-6492, -1717, 2419, 6084, 7267, 4702, -638, -7665, -11362, -9456, +-4555, 157, 2858, 2597, 2796, 3969, 4031, 3592, 2461, 1759, +1225, 52, -1057, -2921, -3853, -1738, 1675, 4419, 5267, 4105, +1151, -1445, -3340, -5089, -5100, -2827, 1518, 5990, 8126, 6660, +2932, 387, -52, -324, -146, -617, -1874, -1361, 209, 1706, +1570, 1214, 1539, 1288, 1256, 240, -1926, -3393, -3047, -1361, +230, 1047, 1528, 1549, 1727, 1539, -366, -2544, -3780, -3790, +-2345, -743, 198, 1843, 3036, 3466, 2440, -314, -2659, -3927, +-3455, -1759, -544, 272, 1005, 1151, 1288, 1005, 240, -62, +178, 429, 261, -565, -1644, -1811, -764, 1151, 2827, 2890, +1717, -282, -2670, -4555, -5833, -4942, -1340, 5759, 12860, 13928, +10765, 3351, -6712, -11959, -12996, -10870, -4775, 2523, 9917, 12650, +8901, 1874, -8042, -14305, -13645, -10095, -3330, 2921, 6513, 9006, +8147, 4911, 1560, -1371, -1989, -429, 984, 1340, 691, -94, +858, 2492, 2817, 3937, 3036, 314, -1424, -4492, -5874, -5068, +-2461, 2963, 7288, 9247, 8692, 4084, -617, -3675, -5372, -3518, +-1057, 2000, 4995, 5812, 4942, 2083, -586, -2366, -3225, -2324, +-1015, -607, -837, -806, -219, -62, 586, 1560, 1371, 973, +408, -638, -2021, -2419, -2481, -2167, -167, 1612, 2125, 1717, +649, -471, -324, -52, -471, -1958, -3340, -3215, -2220, 680, +2408, 2104, 1675, 62, -1015, -1832, -2785, -2691, -1644, 785, +3215, 4241, 3550, 1319, -1570, -3434, -3330, -2241, -1141, -377, +-1403, -3351, -3633, -157, 6545, 12922, 14462, 8524, -1602, -12106, +-17122, -14964, -7885, 1570, 9864, 15017, 14085, 6534, -5497, -17363, +-23416, -19939, -9163, 3654, 12650, 14954, 12346, 5874, -1256, -6450, +-8692, -6911, -2178, 3434, 6639, 6566, 4346, 1665, 418, -188, +-942, -2083, -3246, -3057, -2858, -2377, -1277, 565, 4890, 7843, +8335, 5340, -1256, -5487, -6513, -4597, -314, 3005, 6136, 7445, +5958, 3497, -1916, -6555, -7644, -6461, -2094, 1968, 3979, 4188, +2471, 869, -628, -2450, -3455, -3424, -2806, -1015, 52, -429, +-471, -335, 638, 2262, 2398, 722, -2576, -5403, -5927, -4094, +-418, 3194, 5644, 6126, 3864, 31, -4545, -8315, -8534, -5445, +-754, 3916, 7236, 7655, 4932, 774, -3654, -6702, -6691, -3612, +439, 4115, 5990, 5173, 2576, -764, -3256, -4995, -5937, -5539, +-4356, -1497, 3215, 9498, 12786, 10608, 5299, -2502, -9215, -11938, +-11153, -7068, -125, 7529, 12587, 11174, 4618, -4785, -14200, -17897, +-14776, -7037, 2167, 9351, 12451, 10964, 5717, -806, -6346, -8482, +-6073, -952, 4639, 8419, 9456, 7456, 3853, 502, -2440, -3811, +-3445, -1644, 534, 1895, 2209, 1738, 1497, 2083, 2953, 2879, +1340, -492, -1727, -1654, 303, 2188, 3728, 4838, 4901, 4209, +1759, -1434, -3832, -4450, -2743, -52, 2995, 4576, 4031, 2649, +146, -2838, -4681, -5016, -3738, -1267, 1518, 2754, 2220, 1246, +-712, -1979, -1843, -1193, 209, 1581, 2146, 1361, -356, -1329, +-984, 1110, 3989, 4597, 2303, -2073, -5676, -6807, -5236, -1110, +3057, 6063, 6880, 5005, 858, -4314, -7634, -7498, -3131, 3225, +8116, 9864, 7110, 1518, -4220, -7718, -8105, -5707, -942, 3581, +5791, 4922, 1780, -722, -83, 3036, 5110, 4293, 774, -3194, +-5445, -4670, -2471, 20, 3686, 6042, 6084, 1801, -6168, -13760, +-17258, -13226, -3759, 6210, 12399, 12828, 7718, 282, -6199, -10231, +-9550, -4346, 3969, 11791, 14985, 12284, 5079, -2555, -7571, -8576, +-6251, -2083, 3225, 6995, 7676, 5278, 230, -4419, -5435, -2890, +827, 3529, 3822, 2481, 1057, 617, 1005, 911, 837, 1288, +1748, 1790, 282, -1916, -2848, -1612, 1371, 3539, 3801, 1738, +-1759, -3906, -4419, -3770, -2398, -911, 743, 2010, 2293, 795, +-2052, -4377, -5351, -4272, -1204, 2241, 4513, 5173, 3843, 764, +-2607, -4827, -4021, -848, 3099, 5812, 5068, 2314, -1392, -4869, +-4942, -2953, 52, 3194, 4042, 2921, -575, -4178, -5079, -3372, +743, 5058, 6890, 5110, 754, -3403, -5644, -4869, -1717, 2000, +4723, 5340, 3602, -460, -4932, -7100, -7068, -4272, 1036, 6168, +9823, 10304, 6587, 575, -5299, -9456, -9456, -6367, -1361, 4356, +7979, 8231, 4325, -2094, -8807, -13027, -13132, -8566, -1277, 5477, +10241, 10273, 6136, 607, -4953, -8430, -7833, -3141, 3215, 9278, +11770, 10252, 6157, -83, -4471, -6555, -5895, -1738, 2262, 5686, +7540, 5539, 2125, -848, -3298, -3738, -2523, -1131, 701, 2911, +4241, 4241, 3026, 1110, -523, -1434, -1539, -848, -408, 1151, +3194, 3340, 3539, 2377, -41, -1497, -2953, -3539, -3110, -1811, +471, 2272, 2754, 1570, -858, -3152, -3822, -3508, -2461, -219, +1885, 3487, 4262, 3005, 356, -1424, -2377, -1738, 963, 2942, +4042, 3675, 1528, -1141, -3707, -4419, -2701, 911, 3969, 4848, +2953, -1267, -4932, -6388, -4199, 481, 4890, 7299, 6157, 2314, +-1895, -4754, -5005, -2848, 754, 4513, 5885, 3801, 10, -4450, +-6817, -5162, -1780, 1455, 3487, 5016, 6241, 6388, 4115, -146, +-4806, -7351, -5833, -2586, 1267, 4440, 5424, 4513, 1853, -3183, +-9184, -12336, -10859, -4953, 2335, 7330, 8241, 5068, 544, -3120, +-5550, -5780, -3047, 1686, 6911, 10419, 9749, 5110, -10, -3005, +-3560, -1298, 1549, 3005, 3832, 3916, 2764, 513, -1843, -2722, +-1382, 900, 2722, 2565, 680, -555, -670, 20, 984, 1560, +1455, 1508, 1591, 555, -125, -481, -377, 1539, 2827, 2083, +-52, -2461, -3424, -2199, 0, 1141, 921, -230, -1277, -2429, +-3256, -3612, -3330, -1162, 1696, 3654, 2743, -377, -3675, -5131, +-3372, -178, 2900, 4524, 3728, 1434, -1026, -2743, -3026, -1895, +-198, 1277, 1748, 879, -659, -2010, -2555, -1947, -1057, -41, +921, 1225, 1099, -293, -2450, -3623, -3141, -251, 3141, 4010, +2125, -1822, -5456, -6262, -4419, -1445, 1371, 3445, 3413, 1183, +-2890, -6649, -5089, 764, 6985, 9812, 6241, -1183, -7728, -9854, +-7110, -1947, 3131, 6597, 6210, 1905, -4764, -12085, -14944, -10995, +-2942, 5351, 9645, 7540, 1319, -4356, -7707, -7529, -3969, 1005, +6817, 10378, 9676, 5529, -649, -4817, -4639, -1455, 2670, 5309, +5016, 3110, 1204, -774, -2398, -3036, -2178, -188, 1371, 1350, +198, -984, -900, 733, 1665, 1089, -136, -1560, -1947, -439, +1560, 2869, 3487, 2879, 827, -1225, -2974, -4063, -3005, -806, +2293, 2827, 2984, -680, -3120, -6189, -5958, 1298, -7948, -251, +4565, 198, 5100, 303, -932, -4880, -7131, -2921, 575, 3811, +12085, -377, -5131, -2251, -7110, 4325, 6859, 6073, -157, -6838, +-5885, -3539, 1256, 5068, 6827, 2618, -1005, -4922, -5613, -1989, +-2607, 816, 4649, 3696, 1131, -1937, -2188, -1947, -1570, -397, +125, -858, -921, 502, 1183, -1151, -4419, -4178, -1309, 921, +879, 188, 450, 2241, 3885, 3571, -492, -5236, -7498, -5110, +607, 4167, 5047, 3351, 879, -3686, -8137, -9990, -8932, -3969, +2031, 6335, 6094, 1445, -4733, -7592, -6251, -3016, 1089, 4283, +6419, 6461, 3853, 911, -1026, -1633, -10, 3235, 4607, 2995, +534, -544, 628, 2104, 2146, 890, -628, -1895, -2712, -2471, +-1288, -52, 2010, 3969, 3550, 534, -3633, -5246, -3571, 188, +3885, 5382, 4021, 932, -1591, -2921, -3393, -2921, -691, 2272, +4314, 3487, 41, -3633, -5885, -5340, -2293, 680, 1769, 1214, +-534, -2251, -3372, -4052, -4167, -2597, 251, 2701, 3424, 921, +-2282, -3707, -2722, 188, 2031, 1717, 293, 586, 2167, 2586, +1581, -1340, -3843, -3351, -795, 1256, 1497, 596, 104, 513, +450, -1340, -4021, -5414, -3403, 1110, 4597, 4932, 1738, -1706, +-3393, -3592, -3005, -2817, -1853, 230, 2785, 3633, 1162, -3644, +-7026, -5990, -2450, 1497, 3843, 4293, 3529, 2010, 314, -2356, +-4607, -4963, -1968, 2754, 5571, 5204, 774, -3937, -5979, -5854, +-4586, -2513, -408, 1350, 2345, 921, -2188, -4628, -4105, -743, +3434, 5288, 3979, 984, -858, 178, 1675, 2953, 4010, 3571, +3476, 2838, 816, -942, -1267, 544, 2450, 3853, 2932, 20, +-1748, -2052, -921, 377, 1026, 1131, 607, 73, -387, -1162, +-1361, -670, 869, 2502, 2461, 712, -1298, -1686, -555, 1047, +1947, 1214, -303, -1120, -1225, -523, -10, -136, 20, -94, +-1361, -3267, -4115, -2848, 251, 2576, 2775, 921, -1780, -2953, +-2555, -1780, -523, 1790, 4461, 5738, 4073, -481, -4869, -4953, +-1256, 4073, 7529, 5948, 2136, -1518, -3487, -2984, -1214, 1047, +3099, 4419, 3686, 869, -2251, -4325, -3434, -52, 2754, 3539, +1989, -418, -1382, -638, 209, 240, -377, -1319, -1204, -230, +314, 607, 607, -178, -743, -1633, -3749, -4356, -2052, 3141, +9226, 10262, 5403, -2450, -9571, -10105, -3749, 4136, 9477, 9749, +5194, 10, -4272, -7958, -8995, -5581, 41, 5299, 7215, 3948, +-1131, -4618, -4461, -1958, 136, 1225, 1958, 2984, 4346, 4723, +3204, 1508, 1193, 1696, 2314, 2534, 1005, 607, 3204, 5655, +6126, 3738, -795, -3749, -3016, -136, 2398, 3434, 3173, 2021, +1413, 324, -2157, -3696, -3330, -94, 3843, 4859, 3309, 219, +-2094, -1979, -1183, -555, 345, 911, 1581, 2670, 2293, -94, +-2178, -2900, -2220, -397, 345, -31, 104, 188, -356, -1413, +-2733, -2900, -1120, 1151, 1581, 429, -1141, -1131, 1172, 2440, +1329, -1246, -2377, -282, 3319, 4984, 2775, -1193, -3550, -2031, +1706, 4042, 3717, 1204, -1047, -1864, -1780, -1068, 41, 1937, +3173, 2481, -837, -4681, -5267, -2628, 1644, 3969, 2481, -596, +-2461, -2125, -691, 450, -293, -1738, -1864, -1204, -670, -460, +-712, -397, 94, -774, -3194, -5204, -2942, 2356, 7519, 8356, +2471, -4576, -7414, -4618, 1340, 5393, 4869, 1885, -429, -1078, +-1235, -2272, -3895, -4126, -1864, 335, 837, 0, -1151, -984, +-146, 20, -649, -2052, -1926, 366, 2796, 4272, 4293, 3183, +1843, 1026, -104, -984, -293, 2010, 5162, 6964, 5466, 1256, +-2659, -3832, -1665, 1644, 3424, 3036, 1644, 377, -733, -1885, +-2848, -2796, -1487, 764, 1926, 1068, -523, -1612, -1623, -722, +31, -534, -816, -282, 596, 1560, 1256, -125, -1445, -1801, +-1214, -41, 450, -460, -1193, -1256, -712, 41, -178, -1319, +-1947, -1497, -324, 544, -701, -2178, -1455, 1172, 4052, 3811, +-439, -5183, -6105, -2136, 3686, 7246, 6356, 2146, -2303, -4974, +-4817, -2502, 1151, 5393, 6953, 4178, -911, -5979, -7215, -3183, +2031, 4660, 3560, -314, -3518, -3979, -3424, -2042, 83, 1727, +2743, 1602, -1518, -4607, -5696, -3235, 994, 4021, 3445, 178, +-3162, -5456, -5497, -3340, 1172, 6513, 8566, 5655, -1225, -8325, +-10472, -5665, 2701, 8796, 9613, 4492, -3183, -7623, -8262, -5958, +-1319, 2995, 4230, 2419, -911, -5037, -6084, -3131, 377, 2900, +2398, -575, -2796, -2199, 617, 3120, 4356, 3853, 1801, -638, +-2052, -1717, 439, 3790, 6492, 5225, 2900, -2628, -4775, -3853, +607, 7529, 3131, 3937, -1068, -4335, -2900, -2419, 2911, -178, +1445, 293, -921, -2167, -4147, -115, 1235, 2429, -1162, -3508, +-2817, -2188, 1644, 3895, 2848, -806, -4105, -3602, -1874, -1686, +-743, 795, 2900, 1895, -1319, -3989, -6450, -4272, -691, 3340, +4817, 1434, -1885, -3361, -2031, -1434, -1277, -230, 418, 1811, +2440, 2398, 806, -2419, -3969, -2272, 555, 2471, 4084, 4010, +2042, -1120, -4398, -4241, -1403, 1591, 3612, 3078, 377, -3036, +-4199, -2691, -356, 1151, 439, -429, -973, -1581, -973, 471, +1225, 293, -1350, -2481, -2712, -1958, -733, 837, 1047, -1131, +-2125, -1926, -1853, -973, -293, 481, 1350, 1434, 722, -188, +-869, -1518, -1382, 0, 869, 1392, 1989, 1853, 555, -2199, +-4461, -4513, -1434, 2136, 3215, 1926, -1696, -4356, -3989, -1340, +1466, 2303, 2178, 1403, 136, -502, -649, -198, 1172, 2450, +2743, 1958, 858, 146, 513, 2188, 2649, 1811, 1057, 178, +272, 1644, 2628, 2125, 1256, 481, -586, -701, -670, -733, +649, 1612, 1466, 439, -1413, -2586, -1905, -62, 1403, 1769, +764, -879, -1382, -795, 115, 1015, 513, 20, 136, -534, +-848, -848, -1005, -251, 952, 1350, 680, -754, -1822, -1466, +-261, 502, 1057, 1518, 1204, 523, -1078, -2335, -827, 1665, +3476, 3529, 816, -2576, -2963, 62, 3623, 4995, 3235, 492, +-1424, -2000, -565, 2303, 3989, 3969, 2335, -1026, -3309, -2586, +743, 4220, 4942, 1769, -2450, -4408, -3351, 115, 3089, 3612, +1905, -1235, -3508, -3026, -136, 2366, 2743, 1298, -1099, -2838, +-3078, -1759, 314, 2042, 2429, 680, -2094, -3057, -1706, 764, +2691, 2429, 544, -1947, -3089, -1403, 1476, 3225, 2858, 324, +-2408, -3225, -2021, 178, 1958, 2900, 1612, -858, -2869, -3853, +-1644, 1172, 2104, 2241, 125, -272, -1214, -1466, 178, 900, +2796, 932, 942, 198, 827, 2387, 1256, 1811, -481, -450, +20, 1612, 2450, 2188, 3110, 1214, -94, -2083, -1487, 1015, +2513, 3235, 1843, 471, -1057, -1015, 429, 785, 324, -335, +-94, 1057, 1497, 858, -230, -1288, -1675, -1288, -209, 1089, +1392, 816, -136, -1099, -1602, -1570, -146, 1131, 900, -94, +-1487, -1686, -733, 984, 2387, 1235, -1371, -3518, -2827, -345, +2021, 3518, 2785, 890, -1591, -3319, -2534, -450, 2157, 4398, +4230, 1068, -2911, -4314, -2387, 1340, 3895, 3372, 1131, -952, +-1706, -617, 848, 1466, 1015, 397, 649, 1246, 837, 272, +377, 219, -94, 136, 282, -157, 418, 1204, 1298, 230, +-1078, -555, 167, -41, -209, 52, 439, 481, -73, -502, +-921, -1099, -701, 261, 607, -324, -743, -1026, -942, -942, +-806, 31, 743, 1141, 408, -450, -1256, -1382, -701, -450, +-41, 293, 575, 774, 366, -628, -1832, -2063, -1256, 52, +994, 848, 638, 460, -188, -1591, -2440, -1822, -439, 1413, +2094, 1665, 397, -932, -1110, -837, 94, 806, 837, 1068, +1047, 586, 94, 0, 261, 743, 712, -20, 10, 272, +973, 1267, 408, -345, -932, -314, 418, 670, 240, -261, +115, 303, 586, -125, -1078, -1131, -429, 219, 324, 450, +188, -219, -994, -1623, -1214, 251, 848, 492, -429, -1068, +-1151, -1340, -1382, -1225, 20, 418, 649, 104, -1120, -1466, +-1602, -827, 115, 701, 638, -125, -1099, -1172, 397, 848, +272, -471, -754, -94, 146, 869, 785, 335, 73, -62, +31, -774, -198, 1204, 1864, 1047, -198, -617, -586, 366, +1487, 1801, 1277, 460, -596, -649, -10, 1141, 1811, 1455, +649, 10, -198, -607, -534, 125, 293, 303, 513, 492, +-104, -952, -743, -52, 293, 10, -314, -565, -900, -596, +-198, 146, 397, -387, -1434, -1686, -890, 94, 429, 178, +-366, -869, -1078, -1110, -1078, -596, -20, 188, -534, -1141, +-1078, -963, -418, -324, -555, -1036, -900, -418, -691, -984, +-1099, -471, -429, -638, -638, -806, -827, -911, -492, 115, +-20, -973, -1225, -942, -806, -649, 115, 837, 167, -450, +-555, -911, -1413, -869, 52, -198, 52, 240, -178, -806, +-659, -251, -680, -712, -272, 418, -188, -73, 240, -575, +-806, -1151, -837, -575, -418, -94, -712, -628, -534, -952, +-1005, -1403, -722, 157, 20, -481, -1371, -1162, -303, -52, +-188, -272, -701, -555, -418, -377, -565, -848, 62, -178, +-115, -125, -806, -502, -890, -628, -575, -261, 544, -31, +62, -565, -565, -900, -544, 534, 41, 136, -251, 356, +219, -303, 167, -356, -335, -167, 198, 198, 115, 555, +219, -10, -408, 73, 408, 188, 293, 418, 1026, 1078, +617, -136, 31, 178, 293, 795, 837, 785, 439, -10, +-418, -115, 575, 754, 638, 429, -324, -418, -94, 429, +492, 345, 565, 377, 52, -377, -104, -219, 73, 638, +691, 628, 481, 345, -240, -115, 136, 335, 240, 104, +596, 52, -293, -198, 83, 261, 41, 429, 136, -52, +-10, -115, 157, 303, 219, 146, 198, 167, -230, -387, +-439, -104, -167, -198, 251, -209, -450, -356, -638, -534, +83, 209, -240, -628, -596, -345, -209, -178, -20, -230, +-523, -932, -586, 356, 198, -408, -607, -314, -555, -754, +-167, 240, 345, -293, -774, -565, -429, 83, 387, 10, +-659, -157, 534, 366, -136, -136, 83, -272, -617, -20, +460, 439, 712, 209, 125, -429, -167, 429, 335, 617, +10, 73, 136, -10, -73, -52, 83, -240, 230, 565, +575, 104, -167, 628, 198, 136, 774, 481, 272, 167, +890, 701, -83, 136, 178, 387, 52, -146, 293, 429, +314, 73, 167, -167, 167, 638, 869, 366, 83, 691, +52, -10, 282, 418, 534, 303, 104, 62, -62, 115, +73, -324, 41, 272, -94, -178, -146, -460, -230, 104, +293, -314, -345, -10, -303, -366, -513, -303, 157, -115, +-125, -41, -335, 62, -356, -691, -932, -513, 157, -335, +-408, -314, -586, -1078, -659, -146, -209, -659, -869, -146, +-356, -251, -240, -607, -596, -502, 0, 0, -272, -377, +-272, -513, -502, -157, -178, 272, 261, -104, -272, -848, +-408, -178, 219, 429, 41, 125, -366, -377, 377, 785, +471, -408, -408, 293, 240, 513, -125, -555, -136, 586, +890, -219, -157, -188, -73, 209, 345, 795, -20, -230, +240, -20, 146, 73, 10, 20, -20, 335, -136, -460, +596, 251, -219, -125, -73, 198, -429, -251, 73, 251, +-136, -492, 31, -10, -146, -429, -261, 303, 628, 387, +-282, -73, -230, -230, 146, 198, 230, -20, -41, -272, +-418, -157, 62, -125, -356, 0, 31, -230, -293, -209, +-335, 20, 303, -408, -188, 387, -31, -240, -83, -125, +-240, -125, 157, 251, -146, -628, -335, -94, 272, 335, +429, -125, -774, -356, -209, -31, -460, -272, -282, -136, +146, -251, -429, -324, 20, -41, -198, -377, -314, -230, +-83, -83, 167, 397, 178, -712, -408, 94, 167, 502, +-157, -209, -575, 10, 52, -450, 460, 31, -272, -513, +-900, 136, 324, 167, 303, -418, -534, -282, 387, 293, +-41, 178, -617, -460, -52, 209, 324, 73, -198, -230, +104, 136, 272, -62, -10, -31, 178, -209, -52, 439, +52, 104, -115, 513, 575, 314, -230, -345, 230, 659, +858, 52, 52, 335, 429, 83, 0, 450, 324, 94, +-146, 209, 167, 230, 272, 10, 157, -62, 230, 230, +293, 649, 167, -157, -31, 377, 513, 272, 471, 345, +188, 136, -523, -240, 555, 534, 607, -41, -366, -198, +-83, 397, 324, 20, -659, -272, 240, -104, -198, 41, +324, 366, 0, -178, -293, -282, 272, 188, 324, 408, +345, -377, -460, 0, -219, 261, -52, -712, -418, 146, +73, -387, -502, -62, 188, 52, -41, -471, -701, -429, +-125, 94, -62, 146, -293, -586, -596, -198, 575, -240, +-240, -240, 10, 188, 115, 31, -345, -481, -712, -293, +41, 659, 282, -324, -743, -502, 272, -219, 0, 10, +-73, -62, -73, 314, 41, -324, -670, -596, -377, 125, +418, 73, -157, -460, -722, -628, -481, -167, 146, -230, +-596, -816, 429, 429, -712, -387, 31, 146, 167, -73, +-617, -366, -272, 198, -94, -523, -125, -94, 471, -62, +-429, -272, 83, -20, -20, 691, -293, -282, -240, -439, +-188, 178, 701, 230, -335, -733, -41, 52, 0, -41, +251, 439, -345, -408, -314, 188, 439, 628, 219, 0, +-471, -712, -94, 314, 628, 20, 356, -230, -492, -115, +0, 680, -31, -52, 52, 534, 492, -83, 219, 418, +219, 157, 146, -52, -20, 178, 858, 10, -314, -178, +-303, -52, 104, 607, 366, 83, -52, -104, 83, 921, +607, 31, -324, 41, 638, 115, 261, -31, 638, 670, +408, 544, -251, -125, -209, 272, 691, 691, 680, -460, +-481, -293, 324, 816, 523, 146, -785, -167, 523, 596, +471, 178, -345, -879, 20, 638, 806, 743, -492, -617, +167, 837, 691, 377, 314, -240, -282, -115, 230, 743, +795, -20, -617, -387, 565, 701, 502, 125, -439, 502, +-198, -680, 324, 911, 1141, 314, -94, -41, 387, 900, +555, -31, -146, 209, 754, 1298, 973, -167, -555, 157, +963, 680, 83, 62, 115, 638, 691, 167, -94, 534, +628, -41, 31, 502, 555, 31, 303, 607, 544, 219, +-20, 115, 638, 418, -83, 397, 534, 722, 0, 209, +722, 0, -555, -272, 963, 1151, 324, -471, -282, 146, +492, 104, -293, 251, 460, 607, 366, -136, 261, 198, +-303, 10, 240, 324, 178, 188, 167, 471, 314, -198, +31, 73, -293, 387, 649, 219, 178, 272, 439, -230, +-240, 219, 628, 188, 429, 439, 94, -303, -523, 659, +450, 125, 115, 73, -251, -481, 314, 261, -20, 377, +418, -282, -303, 680, 806, -366, -617, 10, 167, 649, +994, 827, -31, -774, -659, -94, 827, 806, -219, -628, +-764, -31, 408, 188, 670, 62, -848, -293, 377, 523, +795, 0, -387, -188, -41, 649, 261, 62, 115, 502, +617, -104, -10, -314, 167, 743, 680, 104, -418, -240, +167, 607, -41, -104, 0, 649, 62, -586, 607, 848, +471, -743, -670, 261, 555, 795, 178, -83, 10, 136, +146, -230, 429, 858, 502, -125, -94, -94, -555, 879, +837, -397, -261, 565, 502, -104, -31, -481, -188, 450, +754, 324, -240, -230, -115, -146, -31, 188, -555, -575, +-460, -649, 219, 429, 345, -230, -471, -481, -900, 544, +596, 492, -209, -1570, -397, 869, 492, -670, -628, -900, +-848, 722, 1078, -52, -1078, -1288, -879, -649, 848, 1110, +408, -1026, -1623, -544, 356, 1204, -408, -1036, -219, 555, +366, -481, -596, -293, 900, 586, -712, -733, 219, 397, +52, 492, -523, -596, 774, 282, -272, -41, 125, 104, +-94, 586, 858, -387, -387, -303, 115, 41, 492, 743, +-335, -544, -1110, 345, 513, 104, 335, -356, -125, -209, +-146, -62, -377, 198, 219, -439, 240, -356, -397, 178, +-481, -10, -335, -52, 10, 10, 0, 293, 104, -1329, +-73, 178, -764, 314, 858, -481, -1424, -628, 345, 523, +261, -146, -366, -900, -335, 115, -125, -387, 335, -209, +-31, 1225, -408, -1654, -1340, 1225, 1026, -638, -534, 83, +513, -1078, -230, 198, -335, 83, -230, 188, -691, -219, +240, -544, -450, -282, 973, 816, -607, -1602, -973, 219, +670, 429, 62, -984, -1015, 324, 230, 649, -230, -890, +-209, 73, 146, 219, 167, -324, 0, 73, -575, -879, +41, 523, -31, -261, -157, 83, -377, 41, 324, -366, +-324, -869, 146, 387, -397, -20, -544, -418, -785, -188, +712, -83, -670, -1089, -942, -764, -41, 1329, 722, -251, +-848, -1392, -1151, -356, 963, 701, -575, -387, -20, -617, +-659, 272, 502, -481, -1005, -293, 240, 125, 146, -335, +-785, -649, -31, -387, -251, 1120, 303, -1508, -1235, 73, +502, 366, 136, 104, -502, -785, -774, -83, 303, 408, +827, 83, -471, -1539, -1057, 513, 1591, 774, -1392, -1675, +-921, 94, 670, 1277, 1288, 774, -754, -1748, -921, 795, +2220, 1131, -607, -1392, -418, 827, 1015, 272, -680, -701, +-837, -586, 345, 1151, 890, -324, -1246, -1455, 397, 1581, +345, -837, -879, 73, 157, -230, -125, -73, -418, -701, +-356, -230, 575, 1277, 439, -942, -1968, -1288, 575, 1895, +900, -785, -1528, -1131, 219, 1089, 858, -565, -1560, -858, +167, 596, 785, 219, -1015, -1612, -1193, 136, 1633, 1853, +-104, -1864, -1612, -460, 900, 900, 272, -691, -1476, -377, +1068, 1686, 481, -1623, -2115, -1497, 0, 1445, 1769, 261, +-1874, -2303, -1476, 429, 1654, 1340, 198, -1120, -1172, -345, +0, -293, -586, -41, 743, 544, 31, -575, -649, -439, +-282, 198, -20, 345, 764, 209, -691, -1078, -282, 94, +62, -136, 272, 638, 198, 20, -555, -722, -324, 125, +1005, 1256, 942, -471, -1654, -911, 869, 2387, 1246, -1214, +-2178, -1047, 1172, 1769, 324, -942, -1026, 356, 1288, 1005, +638, 209, 492, -460, -785, 136, 1005, 1769, 408, -607, +-1120, -418, 1172, 1476, 1057, -1235, -1487, -408, 774, 1424, +-62, -680, -1633, -1110, 555, 1832, 1769, -167, -1445, -2220, +-754, 1246, 2042, 848, -1267, -1204, -366, 942, 1110, -52, +-1455, -2157, -345, 2157, 3319, 1623, -1832, -3581, -2817, 544, +3036, 2879, 1193, -628, -1528, -1717, -230, 1005, 1570, 345, +-2094, -2272, 387, 2565, 2063, 198, -2408, -2827, -911, 628, +1361, 2063, 481, -774, -952, -942, 2272, 3288, 1298, -1214, +-2104, -1068, 1968, 4618, 2555, 1120, -994, -2104, -125, 858, +2272, 2199, 848, -345, 104, 1089, 722, 837, -198, 178, +1476, 1183, 1120, 397, -198, -523, -523, 178, 984, 1267, +10, -607, -366, 209, 1120, 303, -1246, -2094, -963, 691, +879, 178, -1602, -2083, -2796, -2900, -1706, -1183, -83, -2324, +-4440, -5225, -4419, -2220, 1686, 11865, 15855, 9676, -6985, -23615, +-19426, -984, 17855, 23468, 14734, -1487, -13142, -13907, -11352, -1979, +3298, 1340, 397, 879, 4963, 5958, -1602, -14336, -17782, -9456, +4806, 18462, 17227, 7026, -3675, -11886, -10367, -2251, 7068, 12032, +9655, 3581, 52, 984, 575, -1361, -5581, -5801, 2125, 9079, +12294, 6639, -4356, -11854, -11603, -4387, 5110, 9948, 5152, -324, +-4618, -4251, 366, 628, -1382, -3057, -1822, 2167, 7875, 7529, +1413, -4042, -10346, -7026, 2345, 8231, 9540, 2942, -5204, -8042, +-4576, -2858, -1246, 2345, 1466, 2303, -460, -4869, -2701, -994, +-377, -1686, -1518, 1036, 4984, 5466, 31, -2031, -3267, -1759, +607, 439, 4576, 6629, 4670, -83, -4963, -3770, 911, 4827, +3508, 198, -450, 1476, 3330, 659, -1665, -2440, -2576, 1099, +2576, 3340, 3916, 1340, -984, -2754, -2534, -429, 2628, 4565, +4126, 2722, 0, -764, -942, -1612, -282, 1068, 3843, 3612, +-115, -2628, -2691, 586, 2209, 62, -2471, -1937, 471, 2324, +2094, 575, -31, -1686, -3832, -2858, 2618, 7215, 5361, -2324, +-8388, -4743, 2659, 7508, 4733, -1026, -1015, -1099, -1591, -3738, +-3654, 994, 4702, 4723, 534, -1204, -4775, -6807, -5686, -3068, +3529, 5246, 1874, -3057, -4649, -4984, -3162, -3110, -3413, 1392, +9896, 19258, 9969, -1979, -15792, -19164, -921, 10817, 17656, 13184, +3529, -9268, -11854, -7068, -8011, 2921, 764, -1832, 5267, 1403, +-73, -4157, -12305, -12242, -377, 6649, 10409, 12441, 261, -3413, +-2869, -5120, 1769, 5424, 4869, 7026, 7864, 4314, 1047, -3633, +-9006, -3131, 3738, 5759, 7843, 2628, -2817, -5183, -7100, -5047, +701, 4901, 2984, 1277, -418, -1748, -20, -1570, -2796, 188, +2733, 4911, 5278, 2188, -2031, -4398, -2586, 649, 3738, 3550, +125, -335, -879, -1612, -2775, -4890, -2649, 670, 3539, 1329, +-3592, -4859, -4052, 345, 1895, 324, -523, -680, 429, 806, +1036, 1413, 900, -942, -1696, 115, 3277, 4304, 2440, 31, +-1141, -1015, -1131, -523, 1162, 2921, 3057, 680, -1738, -2911, +-1455, 1110, 701, -324, -83, 1267, 2241, 858, -1822, -1706, +-555, 335, 984, 1371, 3110, 2199, -303, -2178, -1267, 1581, +1811, 1445, 4346, 4346, 586, -6388, -9969, -1769, 7445, 9592, +1570, -6482, -8985, -4963, 1790, 3141, 4063, 1665, -2293, -3298, +-1968, 1172, 2544, 397, -2031, 555, 3696, 3413, 408, -4178, +-4366, -1644, 167, 837, 513, -377, -1916, -3099, -4440, -3152, +-3235, -3424, -1958, -2670, -869, -5487, 6430, 25563, 18462, -1979, +-32642, -32569, -837, 29573, -32768, 11174, -1853, -19688, -17949, -10409, +-8178, 7707, 5100, 1455, 3078, 3560, 303, -13017, -20839, -16933, +6314, 20232, 16064, 8283, -5372, -7561, -6063, -5665, 1288, 8911, +12901, 11174, 8137, 1706, -4901, -11687, -12514, 911, 13153, 16127, +6566, -3979, -6178, -7330, -7508, -8922, -1026, 10734, 13635, 7990, +-3036, -7309, -9247, -7634, -1288, 7152, 16054, 11802, -617, -7644, +-7278, -2827, 209, 471, 2932, 7498, 5979, -1015, -6503, -9226, +-8042, -4230, -167, 5173, 7383, 1151, -7058, -9645, -6974, -1089, +1057, 1141, 4691, 6272, 3235, -3267, -6786, -4000, 1298, 4691, +4387, 4817, 4052, 366, -4157, -5833, -1508, 2670, 3256, 1350, +1455, 2827, 994, -4115, -8063, -4115, 2743, 7739, 6430, 1099, +-1623, -4366, -4429, -2324, 2429, 6807, 6147, 2817, -1623, -1424, +-785, -1675, -2659, -1476, 3749, 6629, 5100, -900, -6000, -7466, +-5330, -680, 3885, 5812, 3571, -890, -4534, -5288, -5131, -3141, +659, 5215, 7089, 3131, -2963, -7393, -6126, -1225, 1947, 3455, +3068, 1131, -1350, -2775, -2869, -2471, -2366, -2869, -921, 2136, +2984, -1099, -5267, -7163, -5173, 439, -1968, -4304, -5812, 6608, +25039, 17111, -5518, -31731, -27573, 1235, 24358, 28055, 9519, -3183, +-15813, -17488, -9383, -2869, 6042, 3864, 471, 2366, 3099, -3948, +-15614, -18106, -6293, 11749, 16179, 7498, -1466, -5969, -3476, -1759, +-1015, 1926, 5874, 9069, 9194, 6890, -1686, -9812, -13310, -4880, +11781, 15687, 9194, -4325, -11257, -6178, -3183, -722, 146, 2785, +5225, 5257, 2492, -4000, -7780, -10126, -3801, 7623, 14305, 11320, +20, -9823, -11613, -3351, 4031, 7173, 5655, 2146, 1623, -1183, +-4817, -8367, -7791, -1204, 4880, 6974, 3277, -3057, -8116, -8419, +-5382, -607, 3183, 3518, 3110, 2502, 439, -3979, -6911, -5466, +1120, 8388, 9268, 4314, -2523, -6419, -4681, -10, 3602, 3497, +1790, 1413, 1424, 450, -2230, -4304, -3099, 1193, 5005, 6105, +3937, -1549, -6115, -5236, 167, 5288, 6492, 2073, -2712, -2670, +-157, 1497, 1926, 586, -816, 73, 586, 1466, 1706, -1508, +-2963, -1633, 1403, 3005, 335, -2324, -3560, 136, 1455, -62, +-1172, -3078, -607, 785, 1508, 31, -2000, -2314, -1099, 2701, +2042, -932, -4649, -4031, 1361, 4670, 3445, -2879, -6765, -5152, +-157, 3623, 2471, -1916, -5623, -5361, -2639, 356, 754, -1246, +-2921, -41, 8262, 10419, 1811, -10660, -15886, -3906, 11917, 16242, +8116, -4346, -9760, -9152, -3602, 408, 1183, 1267, -1131, 345, +1225, -2942, -8566, -10084, -2230, 8178, 10618, 3759, -3026, -4963, +-2408, 1570, 2806, 3298, 3319, 3654, 4429, 4482, 293, -6848, +-7215, -335, 9477, 9613, 513, -6251, -6126, -219, 1403, -1214, +-3780, -492, 5424, 7100, 1686, -7299, -10535, -5351, 5152, 10577, +7749, -62, -6199, -4513, 680, 3068, 701, -2440, -272, 5319, +7634, 2188, -7948, -11194, -4974, 4408, 8514, 3864, -3675, -7655, +-4995, -638, 1748, 774, -1612, -1005, 2345, 3424, 1319, -2785, +-5131, -1979, 3455, 7801, 5299, -377, -4754, -3110, 2586, 3330, +115, -2775, -754, 4733, 5906, 1110, -5539, -8828, -3906, 4419, +9205, 5916, -1738, -5571, -3215, 1497, 1686, -1298, 20, 4126, +5780, 3141, -5141, -6681, -2806, 2387, 6147, 3665, 1162, -3717, +-3162, -1120, -31, 450, -2356, -314, 3036, 4283, -345, -5634, +-6513, -3047, 2817, 3351, 2722, 0, -2450, -2555, -2974, -1193, +-1455, -1036, 680, 1780, 1434, -2639, -5550, -6335, -2555, 1822, +1696, -544, -3937, -3539, -2691, 12985, 14546, -2471, -13132, -18755, +2890, 15404, 15027, 1246, -7079, -1916, -8901, -2890, -4262, -1832, +3895, 1958, 2764, -2555, -6754, -13216, -7320, 4796, 9205, 8346, +-2764, -4199, -712, 460, 1748, -136, 3309, 4618, 5665, 5225, +1445, -3036, -9393, -5037, 3906, 10419, 8231, -2461, -5770, -4691, +-1686, -701, -1717, 1549, 3906, 4262, 2419, -1602, -6011, -7508, +-2639, 5550, 10598, 6241, -2680, -5445, -1329, 1696, 219, -1329, +418, 4817, 6304, 1570, -4136, -8325, -7728, -544, 6356, 7739, +188, -6660, -6440, -2157, 1235, -2188, -3644, 104, 6430, 6901, +-324, -7058, -8419, -1644, 5655, 9718, 5676, -1256, -5152, -4513, +1926, 2827, -555, -2523, 754, 4901, 4869, 963, -4869, -5487, +-3675, 94, 5937, 8953, 3843, -3686, -6702, -2953, 2513, 2806, +1455, 1350, 4492, 3215, -1015, -3403, -3361, 251, 2565, 5833, +5089, 607, -4346, -5131, -450, 1225, 534, -1131, 2104, 4712, +1790, -4513, -8859, -4209, 2377, 6000, 4953, -293, -4712, -5016, +-1623, 2607, 2701, -345, -2565, -1350, 994, -188, -2974, -4513, +-2743, 397, 2324, -272, -4157, -5738, -5246, -2523, -743, 11739, +16336, 4262, -11969, -22588, -7623, 9550, 16724, 10629, 1874, -2544, +-10451, -11645, -7791, -146, 4859, 6304, 4545, 408, -6869, -14326, +-11561, -408, 9655, 10273, 3686, -1277, -2387, -3361, -2932, -1445, +3330, 7131, 7655, 7110, 2324, -3717, -9665, -7341, 2021, 9655, +10461, 3403, -3916, -6985, -5665, -2178, 670, 1696, 4052, 4723, +4157, -366, -7278, -8775, -3801, 5382, 10346, 8095, 502, -4534, +-4775, -3717, -1309, 1822, 4942, 6367, 3256, -2010, -5759, -6974, +-4209, 377, 4398, 3843, 282, -3372, -4775, -3895, -3539, -272, +680, 3497, 3958, 387, -1340, -5005, -2817, -1047, 3832, 5916, +2974, 1162, -3036, -1686, -1958, -115, 1874, 2995, 2838, -1068, +-534, -1382, -973, -1413, -1853, 1267, 3162, 4461, 293, -2324, +-2754, -2607, 1570, 3811, 5717, 1654, -1214, -984, -586, 1329, +293, 2576, 3529, 2157, -1455, -3319, -439, 1602, 848, -1120, +-764, 680, 900, -10, -2649, -2492, -869, 10, 3298, 2513, +481, -2440, -3277, -230, 2471, 3665, 575, -1361, -1382, 0, +1214, 523, -879, -1623, -932, -429, 481, -523, -2042, -2136, +-1706, -1015, -1214, -2345, -2429, -377, -513, -1644, -4052, -3811, +-2094, 8461, 16692, 3152, -9781, -19949, -5738, 13582, 15666, 7079, +-5759, -2094, -5393, -5634, -4408, -2356, 2722, 2858, 4796, 481, +-4450, -13216, -10671, 2827, 10451, 9812, -754, -3288, 178, 680, +-345, -1654, 2471, 7184, 7885, 6430, 1225, -4094, -7519, -4262, +4094, 7843, 5581, 837, -2523, -2419, -2461, -3612, -1654, 1235, +3989, 5215, 4461, -722, -5833, -7089, -2052, 5927, 7927, 5414, +387, -1225, -1162, -2680, -1288, 408, 2733, 4524, 2639, 1602, +-2932, -5833, -6147, -1644, 4440, 3047, 1131, -3675, -2125, -1644, +-2157, -1581, -1686, 4304, 4157, 2659, -2659, -3204, -261, 607, +1958, 10, 2429, 1654, 1340, 544, -481, -544, -2879, -628, +3277, 4618, 963, -2858, -1497, 722, 1403, -83, -858, 827, +1612, 1434, 1204, 1026, -1162, -1581, 921, 3749, 3099, -481, +-523, 555, 2932, -198, -3497, 240, 3372, 6231, 471, -2879, +-3361, -3790, 62, 2230, 5948, 2953, -1748, -5529, -3749, 0, +502, 2398, 4272, 4670, -1560, -5623, -5696, 20, 4660, 5131, +3298, -303, -2963, -5874, -3298, 816, 3780, 2879, 1026, -1005, +-3749, -4911, -4785, -534, 2010, 942, -712, -2419, -2869, -3675, +-4073, -921, 1256, 2146, 8974, 3508, -3424, -8157, -9383, 5466, +7362, 7812, 1602, -2052, -1319, -8430, -5393, -3424, 1696, 4440, +3141, 408, -5037, -8304, -8964, -1382, 4618, 6157, 3256, -303, +157, -1350, -1633, -2408, 722, 5990, 8000, 7435, 1612, -3424, +-6021, -3665, 3508, 6210, 4545, 1811, -282, -429, -2670, -4408, +-2607, 2021, 4681, 3497, 2324, 136, -2440, -5340, -3288, 2450, +5979, 6199, 1853, -240, -377, -1832, -2021, 167, 2879, 3780, +4157, 2377, -1487, -5644, -7152, -1497, 5665, 5969, -481, -5403, +-3738, -345, -743, -2838, -2345, 1560, 4984, 2942, -617, -4094, +-6094, -2764, 2963, 7466, 5330, -1120, -3361, -1968, -335, -785, +-1340, 1612, 4806, 4607, 890, -4010, -6964, -4513, 1089, 7299, +6482, -460, -4157, -3413, 586, -1455, -1665, 1508, 5791, 6576, +-104, -4105, -5267, -2335, 1392, 5068, 6733, 2282, -4052, -5257, +-2167, 2125, 2963, 1319, 178, -1162, -1131, -1759, 219, 1099, +481, 397, -1225, -1172, -1989, -1665, 1738, 2974, 837, -3434, +-5340, -1895, 1811, 2146, -125, -3120, -3497, -2576, -1518, 41, +-1288, -2450, -2167, -2429, -1455, -3581, -3372, -2649, 2419, 9519, +712, -3120, -9938, -6377, 5319, 2817, 6796, 450, -251, -2953, +-8126, -3235, -3508, 1612, 2639, 1623, -921, -5456, -7958, -4859, +2220, 2544, 2094, 324, 230, 1235, -617, -932, -397, 1508, +2806, 3016, 4094, 2963, -167, -2775, -1612, 1832, 2775, 2272, +1549, 1591, 795, -2827, -2377, -104, 2000, 1801, -513, 1340, +439, -492, -2345, -1790, 827, 450, 2125, 2440, 2492, -450, +-3131, -1518, 1099, 2534, 754, 439, 1267, 198, -1120, -3235, +-2796, -429, 743, 2230, 764, -2461, -4681, -3612, 575, 2010, +-83, -2115, -921, 1015, 848, -1026, -2775, -1235, 20, 2838, +3529, 408, -2345, -3560, 303, 2021, 1706, -198, -356, 3162, +2178, -157, -3790, -3686, 848, 4565, 6409, 649, -3937, -3518, +-1151, 3487, 2743, 125, 136, 2010, 3843, 1162, -2241, -3654, +-1162, 4084, 5456, 2953, -869, -3550, -2984, 481, 2303, 1141, +-272, -628, 1539, 1277, -973, -2471, -2063, 628, 1706, 1497, +31, -1455, -1696, -607, 858, 125, -2073, -2659, -774, 1644, +879, -2115, -3969, -3529, -1005, 806, 397, -1717, -3989, -4283, +-1120, 837, 4806, 3204, -2586, -4387, -5895, 837, 3612, 3351, +2911, -377, -942, -4440, -5299, -890, 575, 1853, 628, -2712, +-2083, -3361, -2366, -816, 555, 952, -670, 596, 1549, 2010, +1508, -136, -942, 125, 2209, 3194, 3235, 2796, 125, -911, +-806, -251, 2481, 3351, 2502, 1225, 272, -188, -115, 41, +795, 1005, 1549, 2251, 1445, 188, -1633, -1235, 115, 2303, +2796, 1214, 858, 198, 397, -41, -293, 167, -198, 1089, +1633, 638, -628, -3016, -2565, 230, 1413, 795, -1727, -2492, +-335, 712, 932, -1005, -1581, -628, -858, 356, 534, 942, +303, -1277, -806, -293, 534, 83, 73, 1508, 1078, 314, +-827, -733, 1047, 1078, 1246, 1099, 125, 20, 670, 1885, +2220, 628, -1696, -994, 1518, 3361, 2911, 617, -73, -911, +31, 1413, 2241, 2272, 1047, 62, -157, 513, -41, 607, +303, 1371, 1078, -649, -209, -251, 816, 188, 167, 293, +712, 596, 230, 377, 125, 439, -649, 565, 963, 774, +712, -209, -240, -324, -691, -219, 460, -136, -575, -1183, +-1068, -1089, -1759, -2073, -1612, -1225, -1455, -2000, -2890, -2586, +-2555, -2555, -1204, -1612, -2031, -2701, -2995, -1162, -10, -167, +-628, -1539, -2136, -1340, -1644, 356, -282, -1120, -471, -1654, +136, -10, -869, -659, -1162, -418, 314, 471, 502, 20, +345, 492, 408, 963, 733, 795, 869, 921, 1193, 1329, +1329, 1361, 1696, 1298, 1455, 1937, 2387, 2639, 1937, 1717, +1937, 1979, 2366, 1979, 2104, 1738, 1036, 1403, 1319, 1309, +754, 837, 1455, 1256, 418, -83, 83, 712, 628, -73, +-209, -397, -104, -31, 345, -157, -764, -837, -471, 670, +471, -324, -691, -377, 146, 209, -575, -408, -900, -534, +429, 408, -408, -1905, -1644, -607, 1298, 963, 188, -565, +-1497, -178, 198, 1183, 1141, 670, 712, -157, -41, 303, +1110, 1822, 1769, 429, -157, -167, 1078, 2513, 2659, 1644, +-240, 52, 377, 2136, 2953, 1382, 1015, -314, 146, 921, +251, 1267, 754, -31, 219, -827, -157, -10, -492, -94, +-712, -1162, -1298, -1015, -827, -1026, -1874, -2125, -2345, -2597, +-2157, -2628, -2251, -2251, -2262, -2241, -2691, -2607, -3162, -2125, +-1277, -1057, -1141, -2262, -1937, -1162, -1487, -733, -1560, -1905, +-764, -1403, -638, -1183, -1654, -1047, -1424, -1026, -795, -617, +240, 115, 52, 52, -921, -492, 104, 1141, 1937, 1340, +806, 345, 806, 1246, 1686, 1759, 2052, 1832, 1581, 2178, +1916, 2272, 1549, 1717, 2303, 2251, 2419, 1455, 1581, 1403, +1665, 1822, 1476, 1246, 157, 942, 1172, 1811, 1403, -62, +-115, -293, 638, 471, 764, -41, -230, -125, -450, 261, +-408, -178, -994, -345, 397, 188, -83, -963, -764, -1047, +-502, -335, 408, 293, -942, -1717, -1434, -20, 858, 1036, +-314, -198, -555, -659, 994, 1371, 1350, 125, -963, 83, +701, 1057, 1267, 869, 973, 869, -356, 617, 1120, 890, +1602, 1141, 1874, 890, -10, -115, 617, 1015, 471, 219, +-335, 659, -418, -565, -816, -1528, -1015, -1413, -680, -911, +-1487, -2398, -2659, -2576, -2680, -2701, -2576, -1717, -1162, -1309, +-2523, -3351, -3707, -2565, -1047, -10, 377, -439, -1864, -2754, +-2628, -1392, 20, -240, -41, -827, -1413, -1549, -1508, -617, +-722, -1183, -1298, 261, 513, -10, 52, -586, -837, -1131, +-795, 984, 2000, 1916, 586, -774, -544, -366, 1298, 2733, +2879, 2178, 534, 429, 1057, 2021, 2199, 1445, 1518, 1570, +1476, 1340, 1455, 1309, 1151, 712, 963, 1654, 984, 492, +10, 335, 366, 146, 125, 795, 1026, 219, -806, -1497, +-869, -10, 1319, 1382, 492, -1937, -2764, -1382, 555, 2052, +774, -513, -2052, -2136, -911, 335, 869, 471, -680, -1602, +-942, -722, 73, -240, -293, -596, -900, 345, 481, 1309, +408, -523, -659, -502, 596, 1581, 1937, 1518, 733, -429, +272, 240, 827, 1162, 1131, 1686, 743, 900, 167, 52, +-31, -565, 0, 125, 575, 125, -555, -952, -1811, -1759, +-1298, -1298, -1162, -1560, -2146, -2314, -2241, -2293, -2377, -2387, +-2534, -1382, -1267, -1560, -2199, -2534, -1895, -1602, -670, -104, +-439, -1329, -1528, -1832, -188, 219, -366, -649, -1947, -1214, +-722, -481, 628, -324, -1801, -1371, -1015, 795, 1277, 670, +366, -827, -324, 680, 942, 1528, 1644, 1172, 1162, 104, +628, 1811, 1591, 2073, 1403, 1246, 1497, 1026, 1895, 2083, +1591, 502, -41, 1298, 2827, 2544, 1497, 94, -890, 356, +795, 1759, 1717, 314, -52, -136, 890, 827, 157, -83, +-418, 314, 293, 345, 429, -230, -198, -680, -712, -387, +-104, 722, 837, 335, -565, -1340, -1015, -157, 691, 806, +377, -670, -691, -628, -104, 31, -544, 52, 460, 1214, +450, 20, -565, -701, 41, 806, 1811, 1895, 994, 94, +429, 565, 827, 628, 1434, 1790, 973, 848, 837, 806, +115, -575, -282, 712, 544, 837, 1036, -73, -1183, -2241, +-1424, -104, 314, -62, -596, -1403, -2649, -2502, -1832, -1371, +-1361, -2387, -2754, -2282, -1696, -785, -1424, -2492, -2942, -2827, +-743, 617, 722, -471, -2523, -2659, -1738, -439, 209, -272, +-1078, -1413, -1026, -628, -691, -1382, -1916, -1633, -282, 680, +1099, 575, 115, -544, -1382, -701, 890, 2356, 2900, 1560, +502, -230, -994, 691, 2639, 3560, 2419, 722, 481, 1214, +1885, 1706, 1581, 1549, 1487, 1696, 2220, 2031, 1350, 450, +104, 1026, 1424, 1937, 1591, 1225, 869, -293, -125, -471, +534, 1748, 1717, 1172, -670, -1686, -1382, 73, 1309, 1612, +691, -1057, -1759, -1131, -565, 230, 73, 387, 460, -450, +-450, -963, -827, -733, -900, 324, 1528, 471, 62, -1183, +-1885, -1078, -1047, 1748, 2890, 1958, 418, -1759, -1099, 261, +1131, 2618, 2293, 1089, 387, -31, 1089, 1309, 356, 52, +377, 1591, 2136, 1193, 167, -691, -1214, -816, 408, 1183, +973, -31, -1445, -1864, -1591, -1309, -785, -544, -607, -1277, +-2094, -2209, -2031, -2073, -2010, -2031, -2335, -2209, -2502, -2241, +-1131, -1727, -2869, -3948, -3393, -1089, 366, 502, -754, -2429, +-3623, -2492, -439, 1937, 240, -2440, -2440, -1864, 52, -104, +-607, -932, -1382, -1131, -387, 890, 1110, 73, -523, 335, +125, -481, 41, 1445, 3173, 2628, 1078, -596, -1183, -167, +1623, 4115, 4419, 2492, -198, -1539, -52, 1644, 2963, 3057, +2094, 1288, 418, 198, 523, 1047, 1298, 1361, 492, 806, +1057, 973, 932, -460, -869, -1193, -377, 1434, 2502, 1654, +-418, -2063, -2450, -670, 764, 1110, 848, -282, -1047, -764, +-240, -20, -806, -1560, -534, 617, 1602, 1801, 83, -2000, +-2921, -1874, 293, 2262, 2241, 1801, 62, -2188, -1686, -555, +1528, 2398, 1738, 1110, -125, -377, 209, 1036, 1277, 178, +-764, -62, 1885, 2272, 1487, 586, -1036, -1769, -1413, 397, +1958, 1727, 157, -1487, -2125, -1947, -1361, -848, 73, -115, +-858, -1193, -1434, -1738, -2607, -2691, -1916, -1392, -1403, -1549, +-1968, -2398, -2984, -3183, -1937, -1089, -900, -1476, -1696, -1256, +-1476, -1549, -1204, -932, -973, -879, -439, 701, -10, -1319, +-1256, -586, 10, 52, 198, 596, 502, -209, 251, 827, +879, 272, 481, 1612, 1926, 1329, 754, 973, 994, 1183, +1476, 1885, 2021, 785, 607, 1979, 2984, 2586, 1047, 303, +712, 1487, 2157, 3267, 3246, 1057, -1036, -1487, 397, 2639, +3057, 2607, 1329, -377, -1162, -240, 1665, 2649, 1392, -502, +-1078, -240, 973, 1392, 1120, -429, -2146, -2230, 94, 2167, +2419, 209, -2335, -2618, -1864, -83, 1288, 2063, 1036, -722, +-1853, -1623, 157, 1047, 816, 471, 282, -314, -125, 408, +1246, 858, -764, -733, 429, 1968, 1811, 659, -41, -890, +-963, -167, 1612, 2544, 1309, -366, -879, -293, -146, 324, +743, 806, 104, -1151, -994, -408, -136, -712, -858, -607, +-858, -1277, -1131, -471, -1078, -2419, -2733, -2000, -1476, -1193, +-1581, -1309, -1371, -3204, -3256, -2220, -251, 62, -1476, -1665, +-2146, -2125, -973, 408, 607, -1141, -3225, -2241, 146, 1947, +1717, -795, -1968, -2576, -1738, 827, 2775, 2199, 167, -1350, +-1832, -31, 795, 2042, 2104, 628, 555, 115, 973, 2000, +1916, 1958, 1089, 649, 1790, 2398, 2806, 2335, 879, 136, +261, 1644, 3298, 3508, 1905, -73, -649, 439, 1738, 2188, +2492, 1508, -198, -879, -586, 1078, 1853, 1528, 397, -534, +-534, -282, 869, 1204, 575, -649, -1403, -795, 41, 1015, +1434, -125, -1654, -2293, -1644, 534, 1214, 890, -198, -1476, +-1434, -816, 293, 670, -272, -848, -1026, -848, -261, -167, +-104, -513, -1068, -1424, -575, 335, 136, -230, -1141, -1424, +-1047, -261, 377, 104, -722, -1696, -1623, -932, 41, 157, +-691, -942, -984, -942, -869, -701, -617, -1172, -1466, -680, +366, 785, -230, -1686, -1675, -1235, -691, 575, 1099, 869, +-62, -1193, -1717, -1371, 73, 628, 1214, 1047, 827, 41, +-743, -534, -712, 816, 1288, 1539, 1319, 638, 157, 10, +701, 565, 649, 952, 1151, 722, 1036, 973, 240, 104, +-10, 1089, 1989, 1706, 1026, 1193, 586, 314, 911, 1256, +1602, 83, 314, 963, 869, 869, 555, 848, 219, -523, +-356, 911, 1141, 555, 41, -366, -691, -722, 157, 806, +1099, 188, -691, -795, -73, 450, 377, 471, -178, -555, +-460, -125, 157, 439, 136, -408, -282, 146, 596, 94, +-272, -178, 10, -41, -73, 230, 450, 146, -387, -397, +-209, 52, -146, -62, 83, -73, -439, -471, -20, -188, +-502, -691, -303, -356, -261, -303, -575, -439, -1172, -1036, +-188, -136, -785, -827, -481, -219, -712, -1099, -806, -806, +-544, -1005, -659, -209, -429, -324, -356, -471, -869, -377, +115, -272, -377, -733, -628, -261, -272, 858, 816, -596, +-984, -397, 1005, 932, 481, 743, 460, -167, -219, 544, +1151, 439, -387, 638, 1560, 1508, 303, -62, -31, 62, +439, 1099, 1717, 1026, -523, -921, 502, 1078, 1706, 848, +-366, -638, -911, -20, 774, 1434, 879, -879, -1256, -188, +712, 900, 397, 83, -104, -314, -10, 523, 900, -167, +-1172, -733, 230, 460, -104, 10, 366, -20, -408, -293, +-125, -115, -125, 62, 774, 932, 198, -649, -764, -387, +10, 806, 1288, 1162, 324, -617, -596, 125, 544, 712, +754, 607, 324, -167, 83, 418, 115, -513, -942, -136, +774, 900, 230, -911, -1329, -1382, -513, 890, 1204, 617, +-952, -1759, -1455, -921, -62, 104, 167, -198, -963, -1120, +-1005, -377, -492, -617, -136, 240, 513, -125, -471, -324, +-366, -481, -240, 324, 251, -240, -492, -712, -607, -157, +-94, -41, -52, -188, 52, 324, 303, 356, 272, -62, +104, 335, 806, 1371, 984, 178, -146, -167, -146, 502, +858, 670, 429, 94, 314, 795, 492, -125, -104, 492, +764, 282, 471, 596, -188, -670, -240, 754, 827, 387, +115, 198, 62, -272, 178, 607, 617, 387, 209, 429, +377, -219, -345, 52, 481, 240, 20, 691, 408, -198, +-429, 0, 691, 240, 136, 418, 848, 596, 20, 387, +439, -146, -575, -188, 670, 1110, 743, 314, 83, -272, +-387, 345, 1141, 952, 293, -335, -188, -10, 83, 261, +272, 219, -209, -198, -20, 0, 20, -335, -502, -52, +701, 387, -219, -178, -345, -544, -324, 418, 502, -41, +-565, -586, -167, 73, 157, 10, -41, -293, -293, 282, +596, 429, -188, -345, -20, 628, 628, -198, -314, -272, +-20, 209, 198, 178, -94, -157, -188, 0, 502, 345, +-481, -303, 10, 251, 293, 125, 41, -450, -94, -52, +282, 544, 261, -62, -282, 125, -219, -188, -94, 0, +439, -20, -251, 83, 188, -324, -293, 387, 429, 62, +-10, 157, -41, -52, -272, -481, -324, -31, 293, 492, +429, 83, -188, -628, -356, 104, 659, 952, 900, 544, +-555, -345, 219, 324, 429, 356, 439, 198, 136, 397, +408, 157, -408, -136, 596, 555, 335, 534, 586, -115, +-890, -282, 1047, 1214, 670, 335, -20, -502, -544, 429, +1392, 1089, 544, 52, -460, -680, -638, 125, 146, -293, +-146, 157, 722, 387, -638, -502, -10, 94, 513, 774, +513, 41, -209, -230, -481, -534, 20, -41, -62, 209, +230, -73, -460, -429, -335, 73, 146, 209, 261, 188, +314, -314, -848, -513, 115, 534, 314, -20, -418, -565, +-115, 293, -104, -544, -52, 94, 429, 659, -167, -555, +-450, -324, 0, 439, 188, -94, -31, -293, -544, -408, +-219, -115, 795, 900, -62, -366, -251, -188, -356, -125, +157, 178, 481, 795, 994, -31, -848, -439, 20, 408, +439, 806, 942, 125, -638, -649, -387, -764, -638, 429, +754, -282, -963, -439, 293, 387, -146, -104, 439, -303, +-649, 471, 670, 188, -157, -586, -356, -104, -209, -230, +-188, 198, -397, -617, -178, -303, -62, 209, 136, -73, +-136, -62, 429, 638, 272, -52, 178, -41, -481, 157, +659, 942, 628, 10, -62, -10, 10, 314, 1026, 963, +31, -733, -544, 314, 617, 41, -136, -52, -387, -198, +157, 377, 293, -387, -513, -167, 314, 806, 754, 429, +-157, -869, -712, 314, 1141, 1392, 806, -303, -1162, -1204, +41, 932, 712, 638, 188, -544, -754, -10, 869, 345, +-827, -523, 733, 680, 439, 649, 481, -596, -1089, 188, +1623, 1403, 115, -261, -94, -230, -680, 544, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, -1, -1, -1, -1, -1, +0, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, 0, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, 0, -1, -1, -1, -1, -1, -1, -1, +0, -1, -1, 0, 0, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, 0, 0, 0, -1, -1, -1, -1, +0, -1, 0, -1, -1, -1, 0, -1, 0, -1, +0, -1, -1, -1, -1, 0, -1, 0, -1, -1, +0, 0, -1, 0, -1, -1, -1, -1, -1, -1, +-1, -1, 0, 0, 0, 0, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +0, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, 0, -1, -1, -1, -1, -1, 0, +-1, -1, 0, -1, -1, -1, -1, -1, -1, 0, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, 0, -1, -1, +-1, -1, 0, -1, -1, 0, 0, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, 0, +-1, -1, 0, -1, 0, -1, 0, -1, -1, -1, +-1, -1, -1, 0, -1, -1, -1, -1, 0, 0, +-1, 0, 0, -1, -1, 0, 0, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, 0, -1, -1, +-1, 0, -1, 0, -1, -1, -1, -1, -1, -1, +-1, -1, -1, 0, -1, -1, -1, -1, 0, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, 0, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, 0, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, 0, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -2, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, 0, -1, +0, -1, -1, -1, -1, -1, -1, -1, 0, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, 0, -1, -1, 0, -1, 0, 0, -1, +0, 0, 0, -1, -1, 0, -1, -1, -1, 0, +-1, -1, -1, 0, -1, 0, -1, -1, 0, -1, +-1, 0, -1, -1, 0, -1, -1, 0, -1, -1, +-1, -1, 0, -1, -1, -1, -1, -1, -1, 0, +-1, -1, -1, 0, -1, -1, -1, -1, -1, 0, +0, -1, -1, -1, -1, -1, -1, -1, -1, 0, +0, -1, 0, -1, -1, -1, -1, -1, 0, -1, +-1, -1, 0, 0, -1, -1, 0, 0, -1, 0, +0, -1, 0, -1, -1, 0, 0, 0, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, 0, -1, -1, -1, 0, 0, 0, -1, +0, 0, 0, 0, 0, 0, 0, 0, 0, -1, +-1, -1, 0, 0, -1, 0, -1, 0, 0, -1, +0, 0, -1, 0, -1, 0, 0, -1, -1, -1, +0, 0, 0, 0, -1, 0, 0, 0, 0, 0, +-1, 0, 0, -1, -1, -1, -1, -1, -1, -1, +-1, -1, 0, -1, -1, -1, -1, 0, 0, -1, +-1, -1, 0, 0, 0, -1, -1, 0, -1, -1, +-1, 0, -1, -1, -1, -1, -1, 0, -1, -1, +0, 0, 0, -1, -1, -1, -1, 0, 0, -1, +0, -1, 0, -1, 0, 0, 0, 0, 0, 0, +0, 0, 0, -1, -1, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +-1, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, -1, 0, -1, -1, -1, -1, 0, +-1, 0, -1, 0, -1, -1, 0, -1, 0, -1, +-1, -1, -1, -1, -1, -1, -1, 0, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, -1, -1, -1, -1, 0, -1, -1, -1, +-1, -1, -1, 0, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, 0, -1, -1, -1, +0, -1, -1, -1, 0, 0, 0, 0, 0, 0, +-1, -1, 0, -1, -1, 0, -1, -1, 0, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, 0, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, 0, 0, -1, -1, +-1, -1, -1, -1, 0, -1, -1, -1, 0, 0, +-1, -1, -1, -1, 0, -1, -1, 0, 0, -1, +-1, -1, -1, 0, -1, -1, -1, -1, -1, 0, +-1, -1, -1, 0, 0, -1, 0, -1, 0, -1, +0, 0, 0, 0, 0, 0, -1, -1, -1, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, 0, +-1, -1, -1, -1, -1, -1, -1, 0, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, 0, 0, -1, 0, -1, -1, +-1, -1, -1, 0, -1, 0, 0, -1, -1, -1, +0, 0, 0, 0, -1, 0, 0, 0, 0, 0, +-1, 0, 0, 0, -1, 0, 0, -1, 0, 0, +0, 0, -1, 0, 0, 0, -1, 0, -1, -1, +0, 0, 0, 0, -1, -1, 0, 0, -1, 0, +0, 0, 0, 0, 0, 0, 0, -1, -1, 0, +-1, -1, 0, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, 0, 0, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, 0, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, 0, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, 0, -1, 0, -1, +-1, 0, 0, 0, -1, 0, 0, 0, 0, 0, +0, 0, -1, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +-1, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, -1, 0, 0, 0, 0, -1, -1, -1, +0, 0, 0, 0, 0, -1, 0, 0, 0, 0, +-1, 0, 0, 0, 0, 0, -1, -1, 0, 0, +0, -1, 0, 0, 0, 0, -1, 0, 0, -1, +-1, 0, 0, 0, 0, 0, 0, 0, 0, -1, +0, 0, 0, 0, 0, -1, 0, 0, 0, 0, +0, 0, -1, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, -1, 0, 0, 0, +0, 0, -1, -1, -1, -1, -1, -1, 0, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, -1, -1, +0, 0, -1, 0, 0, -1, 0, 0, -1, -1, +-1, -1, -1, 0, 0, -1, 0, -1, 0, -1, +0, 0, -1, 0, 0, 0, 0, 0, 0, -1, +-1, 0, -1, 0, -1, 0, 0, 0, 0, 0, +-1, 0, -1, -1, 0, 0, -1, 0, 0, 0, +0, -1, -1, -1, 0, -1, -1, -1, -1, -1, +0, -1, -1, 0, 0, 0, 0, 0, -1, -1, +0, -1, -1, -1, -1, 0, 0, -1, -1, 0, +0, 0, 0, -1, -1, 0, 0, 0, -1, 0, +0, 0, 0, -1, -1, 0, -1, 0, 0, 0, +-1, 0, 0, 0, 0, -1, -1, 0, -1, -1, +0, -1, -1, -1, 0, 0, -1, 0, -1, 0, +0, -1, 0, -1, 0, 0, -1, 0, 0, 0, +0, 0, 0, -1, 0, -1, 0, 0, 0, 0, +-1, 0, 0, 0, -1, 0, 0, -1, 0, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, 0, +-1, -1, 0, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, 0, 0, -1, +-1, -1, -1, -1, -1, -1, -1, 0, -1, 0, +-1, -1, 0, -1, -1, -1, -1, 0, 0, -1, +0, 0, 0, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, 0, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, 0, -1, -1, 0, -1, -1, -1, +0, -1, -1, -1, -1, -1, -1, -1, 0, -1, +-1, 0, -1, 0, -1, 0, -1, -1, -1, 0, +0, 0, -1, -1, -1, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, -1, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, -1, 0, 0, 0, -1, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, -1, 0, 0, 0, 0, 0, +0, 0, 0, -1, -1, 0, 0, 0, 0, -1, +0, 0, 0, 0, 0, 0, 0, 0, 0, -1, +0, 0, 0, -1, -1, 0, 0, 0, 0, -1, +-1, 0, 0, 0, -1, 0, 0, -1, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, -1, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, -1, 0, 0, +0, 0, 0, 0, -1, 0, 0, -1, 0, 0, +0, -1, -1, 0, -1, 0, -1, 0, -1, 0, +-1, -1, -1, -1, 0, -1, -1, 0, 0, 0, +-1, -1, 0, -1, -1, -1, -1, -1, 0, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, 0, -1, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, -1, -1, +0, 0, -1, 0, -1, -1, 0, -1, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, -1, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, -1, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, -1, 0, 0, +0, 0, 0, -1, 0, 0, 0, 0, 0, -1, +0, 0, 0, 0, -1, -1, 0, 0, 0, 0, +0, 0, 0, -1, 0, 0, 0, 0, -1, -1, +-1, -1, -1, 0, -1, -1, -1, -1, -1, 0, +0, 0, -1, 0, -1, -1, -1, -1, 0, 0, +-1, -1, 0, 0, 0, -1, -1, -1, -1, -1, +0, -1, 0, -1, -1, -1, -1, -1, -1, -1, +-1, -1, 0, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, 0, -1, -1, -1, -1, -1, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, 0, +0, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, 0, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, -1, 0, +-1, -1, -1, -1, -1, -1, -1, -1, -1, 0, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, 0, 0, -1, -1, -1, -1, -1, +-1, -1, -1, 0, -1, -1, 0, 0, -1, -1, +0, -1, -1, -1, 0, 0, 0, 0, 0, 0, +0, -1, 0, 0, 0, 0, -1, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, -1, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, -1, 0, +0, 0, -1, -1, 0, -1, -1, 0, 0, -1, +0, -1, 0, 0, 0, -1, -1, -1, 0, -1, +-1, -1, 0, -1, -1, -1, -1, 0, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, -1, -1, -1, -1, -1, -1, 0, -1, +-1, 0, -1, 0, -1, -1, 0, -1, -1, -1, +-1, 0, -1, 0, -1, 0, 0, 0, 0, -1, +0, 0, 0, -1, 0, 0, 0, 0, 0, -1, +-1, -1, -1, 0, -1, 0, 0, -1, 0, 0, +-1, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, -1, -1, -1, -1, 0, +-1, -1, -1, -1, 0, 0, -1, -1, -1, 0, +-1, -1, 0, -1, 0, -1, 0, -1, 0, 0, +0, 0, 0, 0, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, 0, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, -1, 0, +0, -1, -1, 0, 0, -1, -1, -1, -1, 0, +0, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, 0, -1, -1, 0, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, 0, -1, 0, 0, +-1, 0, 0, 0, -1, -1, 0, -1, 0, 0, +-1, 0, 0, 0, 0, 0, 0, 0, -1, -1, +0, 0, -1, -1, 0, -1, 0, -1, 0, 0, +-1, -1, -1, 0, -1, -1, 0, 0, 0, -1, +-1, 0, -1, 0, 0, 0, 0, 0, 0, -1, +-1, -1, -1, 0, -1, 0, -1, 0, 0, -1, +0, -1, 0, -1, -1, 0, 0, 0, -1, 0, +0, -1, 0, 0, 0, 0, -1, -1, -1, 0, +0, 0, -1, 0, 0, 0, 0, -1, -1, -1, +0, -1, -1, -1, -1, -1, 0, -1, -1, -1, +-1, 0, 0, 0, 0, 0, -1, 0, 0, 0, +0, 0, -1, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, -1, 0, 0, 0, 0, 0, +0, 0, 0, -1, 0, -1, -1, 0, 0, 0, +0, -1, 0, 0, 0, 0, -1, 0, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, 0, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, 0, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, -1, -1, 0, -1, -1, 0, -1, -1, +-1, -1, 0, -1, -1, -1, -1, 0, -1, -1, +-1, -1, 0, -1, -1, -1, -1, 0, -1, -1, +-1, -1, 0, -1, 0, -1, -1, -1, -1, 0, +-1, 0, -1, -1, 0, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, 0, -1, +-1, -1, 0, 0, 0, -1, 0, -1, -1, 0, +-1, 0, -1, -1, 0, 0, -1, 0, -1, 0, +0, -1, -1, -1, 0, -1, 0, 0, -1, -1, +-1, -1, -1, 0, -1, -1, -1, -1, 0, -1, +0, -1, 0, 0, -1, -1, -1, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, -1, 0, 0, -1, -1, 0, 0, -1, -1, +-1, 0, -1, -1, 0, 0, -1, -1, 0, -1, +0, 0, 0, 0, -1, 0, -1, -1, 0, -1, +0, -1, 0, -1, -1, 0, -1, 0, 0, 0, +-1, -1, 0, -1, 0, -1, 0, 0, -1, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, -1, -1, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, -1, 0, 0, 0, 0, +0, 0, 0, 0, -1, 0, 0, 0, 0, 0, +0, 0, 0, 0, -1, -1, -1, -1, 0, 0, +-1, -1, 0, -1, -1, 0, -1, -1, 0, -1, +0, 0, -1, 0, -1, 0, -1, 0, -1, -1, +0, -1, -1, 0, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, 0, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, 0, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +0, -1, -1, -1, -1, -1, 0, -1, -1, -1, +-1, -1, -1, 0, -1, -1, 0, -1, 0, -1, +0, 0, -1, -1, 0, 0, -1, 0, -1, -1, +-1, -1, -1, -1, 0, 0, -1, -1, -1, -1, +0, -1, 0, -1, -1, -1, 0, 0, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, 0, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, 0, -1, -1, -1, -1, -1, -1, 0, +-1, -1, 0, -1, 0, -1, -1, 0, 0, 0, +-1, -1, 0, -1, -1, 0, -1, 0, -1, -1, +0, 0, 0, -1, 0, -1, 0, -1, 0, 0, +-1, 0, -1, -1, -1, 0, -1, -1, -1, 0, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, -1, 0, -1, -1, -1, -1, 0, -1, +0, 0, -1, -1, 0, 0, 0, -1, 0, -1, +0, 0, 0, 0, 0, 0, 0, 0, -1, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, -1, -1, 0, 0, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, 0, -1, +-1, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, -1, -1, +0, 0, 0, 0, 0, 0, 0, 0, 0, -1, +0, 0, 0, 0, 0, -1, 0, 0, 0, -1, +0, -1, 0, 0, 0, 0, 0, -1, -1, 0, +0, 0, 0, 0, -1, 0, -1, 0, 0, -1, +0, 0, 0, -1, 0, 0, -1, 0, 0, 0, +0, -1, -1, -1, 0, 0, 0, 0, -1, -1, +-1, 0, 0, -1, -1, 0, 0, 0, 0, -1, +0, 0, 0, -1, 0, 0, 0, 0, 0, -1, +0, -1, -1, 0, -1, 0, 0, 0, 0, 0, +0, -1, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, -1, +0, 0, -1, 0, 0, 0, 0, -1, 0, 0, +0, -1, -1, -1, -1, 0, 0, -1, -1, -1, +-1, -1, 0, -1, -1, -1, 0, -1, -1, 0, +0, 0, -1, -1, 0, -1, -1, -1, -1, -1, +-1, 0, 0, -1, 0, -1, -1, 0, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, 0, -1, -1, 0, -1, 0, -1, 0, +0, -1, 0, -1, 0, 0, 0, 0, 0, -1, +0, 0, -1, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, -1, 0, 0, +-1, 0, -1, -1, 0, -1, 0, 0, -1, 0, +0, 0, 0, 0, -1, 0, 0, -1, -1, 0, +0, 0, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +0, -1, -1, -1, 0, -1, -1, -1, 0, -1, +0, -1, -1, 0, 0, 0, -1, 0, 0, 0, +0, 0, 0, 0, 0, -1, -1, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, -1, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, -1, 0, 0, 0, -1, 0, 0, -1, 0, +0, 0, 0, 0, -1, -1, 0, 0, 0, -1, +0, -1, 0, 0, -1, -1, -1, 0, -1, -1, +-1, -1, -1, -1, -1, -1, 0, -1, -1, -1, +-1, -1, -1, 0, -1, -1, -1, 0, -1, -1, +0, -1, -1, 0, 0, 0, 0, 0, -1, -1, +0, 0, 0, 0, 0, 0, -1, -1, 0, 0, +0, -1, 0, 0, 0, -1, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, -1, 0, 0, 0, +0, 0, -1, -1, 0, -1, 0, 0, -1, 0, +-1, 0, -1, 0, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, 0, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, 0, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, 0, 0, -1, +-1, -1, -1, -1, 0, -1, 0, 0, 0, 0, +0, 0, -1, -1, 0, -1, 0, 0, -1, 0, +0, 0, 0, 0, 0, 0, 0, -1, -1, 0, +-1, 0, 0, -1, 0, 0, -1, 0, -1, -1, +-1, -1, 0, -1, -1, 0, -1, -1, -1, -1, +0, -1, -1, -1, 0, -1, -1, -1, 0, 0, +-1, 0, -1, -1, 0, -1, -1, 0, -1, -1, +-1, 0, 0, -1, -1, 0, -1, 0, 0, 0, +-1, -1, -1, -1, 0, -1, 0, 0, -1, 0, +-1, 0, 0, -1, 0, 0, 0, 0, 0, -1, +0, 0, -1, 0, -1, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, -1, 0, 0, +0, 0, 0, -1, 0, 0, 0, 0, -1, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, -1, 0, 0, -1, -1, 0, -1, -1, -1, +-1, -1, 0, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, 0, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, 0, -1, -1, -1, +-1, 0, -1, -1, -1, 0, -1, -1, -1, -1, +-1, -1, -1, -1, -1, 0, 0, 0, -1, -1, +0, -1, 0, -1, -1, 0, 0, 0, 0, 0, +-1, -1, 0, 0, 0, 0, -1, 0, -1, -1, +-1, 0, 0, -1, 0, -1, 0, -1, 0, -1, +0, 0, -1, 0, -1, -1, 0, 0, 0, 0, +0, 0, 0, 0, -1, -1, 0, 0, 0, 0, +0, -1, -1, -1, 0, 0, 0, 0, -1, -1, +-1, -1, 0, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +0, -1, -1, -1, -1, 0, 0, -1, 0, 0, +-1, -1, 0, 0, -1, 0, 0, 0, -1, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, -1, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, -1, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, -1, 0, 0, 0, 0, -1, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +-1, 0, 0, 0, 0, -1, 0, -1, -1, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, -1, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, -1, -1, -1, 0, -1, 0, -1, +-1, 0, -1, 0, 0, -1, 0, -1, 0, 0, +0, 0, 0, 0, 0, 0, 0, -1, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, -1, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, -1, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, -1, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, -1, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, -1, 0, -1, -1, +0, -1, 0, -1, -1, -1, 0, -1, -1, 0, +-1, -1, 0, -1, -1, -1, -1, -1, -1, -1, +0, -1, 0, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, 0, -1, -1, 0, -1, 0, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, 0, -1, 0, -1, -1, 0, +0, 0, -1, 0, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, 0, -1, 0, -1, +-1, -1, -1, 0, -1, 0, -1, 0, -1, 0, +0, -1, -1, 0, 0, -1, -1, -1, 0, 0, +-1, -1, 0, -1, 0, -1, 0, 0, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, 0, +-1, -1, -1, -1, 0, -1, -1, -1, 0, -1, +-1, 0, -1, 0, 0, -1, -1, 0, 0, -1, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, -1, 0, -1, 0, 0, 0, 0, +0, -1, -1, 0, 0, 0, 0, 0, 0, -1, +0, 0, 0, 0, 0, 0, -1, 0, -1, -1, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, -1, 0, 0, 0, 0, -1, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, -1, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, -1, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, -1, +-1, 0, 0, 0, 0, 0, 0, 0, 0, 0, +-1, 0, 0, 0, 0, 0, 0, 0, 0, 0, +-1, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, -1, 0, +0, -1, 0, 0, 0, 0, 0, 0, -1, -1, +0, 0, 0, 0, -1, -1, 0, 0, -1, 0, +0, 0, 0, 0, 0, -1, 0, 0, 0, 0, +-1, 0, 0, 0, -1, -1, -1, 0, -1, -1, +-1, -1, 0, -1, 0, 0, -1, 0, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, 0, +-1, -1, -1, -1, -1, -1, 0, -1, -1, 0, +0, 0, 0, -1, 0, 0, 0, 0, -1, 0, +0, 0, 0, 0, 0, 0, -1, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, -1, +0, 0, -1, 0, -1, 0, 0, 0, 0, -1, +-1, 0, 0, 0, 0, 0, 0, 0, 0, -1, +0, 0, 0, 0, 0, 0, 0, 0, -1, 0, +0, -1, -1, 0, 0, 0, -1, -1, 0, -1, +-1, -1, -1, -1, -1, 0, -1, -1, 0, 0, +-1, -1, 0, -1, 0, 0, 0, 0, -1, -1, +0, -1, 0, 0, 0, 0, 0, 0, -1, 0, +0, 0, 0, -1, 0, 0, -1, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, -1, +0, 0, 0, 0, 0, 0, 0, 0, 0, -1, +0, -1, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, -1, -1, 0, -1, -1, 0, -1, +0, 0, -1, 0, 0, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, 0, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, 0, -1, -1, +0, -1, -1, 0, -1, -1, -1, -1, -1, -1, +0, -1, 0, -1, -1, -1, 0, 0, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, 0, -1, -1, 0, 0, -1, +-1, 0, 0, 0, -1, -1, 0, 0, -1, -1, +-1, -1, -1, -1, 0, -1, 0, 0, -1, 0, +-1, 0, -1, -1, -1, -1, 0, -1, -1, -1, +-1, -1, -1, -1, 0, -1, -1, 0, 0, -1, +-1, -1, -1, 0, 0, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, -1, 0, -1, -1, -1, 0, 0, 0, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, 0, -1, -1, 0, 0, 0, 0, -1, +-1, -1, 0, -1, 0, 0, 0, 0, 0, 0, +-1, 0, 0, 0, -1, -1, 0, 0, 0, 0, +0, -1, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, -1, 0, 0, 0, 0, -1, -1, -1, +-1, 0, -1, -1, -1, -1, 0, -1, -1, -1, +-1, -1, 0, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, 0, -1, +-1, -1, -1, -1, -1, -1, -1, 0, -1, -1, +0, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, 0, 0, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +0, -1, -1, -1, -1, 0, -1, -1, -1, -1, +0, -1, -1, -1, 0, -1, -1, 0, -1, -1, +0, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, -1, 0, +0, -1, 0, 0, 0, -1, -1, 0, 0, 0, +-1, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, -1, 0, 0, -1, 0, +0, 0, 0, 0, 0, -1, 0, 0, 0, 0, +0, 0, 0, 0, 0, -1, 0, 0, 0, 0, +-1, 0, 0, 0, 0, -1, 0, 0, 0, -1, +0, 0, -1, 0, 0, 0, 0, -1, 0, -1, +0, 0, -1, 0, 0, -1, 0, 0, 0, 0, +0, 0, -1, 0, 0, 0, 0, -1, 0, 0, +0, 0, -1, 0, -1, 0, -1, -1, -1, -1, +0, 0, 0, 0, 0, 0, -1, -1, 0, 0, +0, 0, 0, -1, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, -1, 0, 0, -1, 0, 0, 0, -1, 0, +0, 0, 0, 0, 0, 0, 0, -1, 0, 0, +0, -1, 0, 0, 0, -1, -1, 0, -1, 0, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, 0, -1, -1, +-1, -1, -1, -1, 0, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, 0, -1, -1, -1, -1, 0, -1, 0, +-1, -1, 0, 0, 0, -1, -1, -1, -1, -1, +-1, 0, 0, 0, -1, -1, -1, -1, -1, -1, +0, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, 0, -1, -1, -1, -1, -1, -1, +0, 0, -1, 0, -1, -1, -1, -1, -1, -1, +-1, 0, -1, -1, -1, -1, 0, -1, -1, 0, +0, -1, 0, -1, -1, -1, 0, -1, -1, -1, +-1, -1, -1, -1, -1, 0, 0, 0, 0, 0, +0, 0, 0, -1, -1, 0, 0, -1, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, -1, 0, +0, -1, 0, 0, 0, 0, 0, 0, 0, 0, +0, -1, 0, 0, 0, 0, 0, 0, 0, 0, +-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, +0, -1, 0, 0, -1, 0, -1, 0, -1, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, 0, +-1, -1, -1, -1, 0, 0, 0, -1, -1, 0, +0, 0, 0, -1, 0, -1, -1, 0, 0, 0, +0, -1, 0, 0, 0, -1, 0, 0, 0, 0, +-1, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, -1, -1, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, -1, 0, 0, +0, 0, 0, 0, 0, 0, 0, -1, -1, 0, +-1, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, -1, 0, 0, 0, 0, 0, 0, +-1, 0, 0, -1, 0, -1, -1, 0, -1, 0, +-1, 0, 0, 0, -1, 0, -1, 0, 0, 0, +0, 0, 0, -1, 0, 0, 0, 0, 0, 0, +-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, -1, 0, -1, 0, 0, +0, -1, -1, 0, -1, -1, -1, -1, -1, 0, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, 0, -1, -1, -1, -1, -1, -1, +-1, -1, 0, -1, 0, -1, 0, -1, -1, 0, +0, -1, -1, -1, -1, 0, -1, -1, 0, 0, +-1, 0, -1, 0, 0, -1, 0, 0, 0, 0, +-1, 0, 0, -1, 0, 0, 0, -1, -1, -1, +0, 0, -1, 0, 0, 0, 0, 0, 0, 0, +-1, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, -1, -1, -1, -1, 0, 0, 0, 0, +-1, 0, -1, -1, -1, 0, -1, 0, 0, -1, +0, 0, 0, -1, -1, -1, -1, -1, 0, -1, +0, 0, -1, 0, 0, 0, 0, 0, -1, 0, +-1, 0, 0, -1, 0, -1, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, -1, 0, 0, -1, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, -1, 0, 0, -1, 0, 0, -1, 0, +0, 0, -1, 0, 0, -1, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, -1, 0, -1, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, -1, 0, 0, 0, 0, 0, +-1, 0, 0, 0, 0, 0, 0, 0, 0, 0, +-1, 0, 0, 0, 0, 0, 0, 0, -1, -1, +0, -1, -1, 0, -1, 0, -1, 0, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, 0, -1, -1, +-1, 0, 0, -1, 0, -1, -1, -1, -1, -1, +-1, -1, -1, -1, 0, -1, -1, -1, 0, -1, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, -1, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, -1, 0, 0, 0, 0, 0, 0, +-1, 0, 0, -1, 0, -1, 0, 0, 0, 0, +-1, -1, 0, 0, -1, -1, -1, -1, -1, 0, +-1, -1, -1, 0, -1, -1, -1, 0, 0, 0, +-1, 0, 0, -1, 0, -1, 0, 0, 0, 0, +0, 0, 0, 0, 0, -1, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, -1, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, -1, 0, -1, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, -1, 0, 0, -1, -1, 0, 0, -1, 0, +0, -1, -1, 0, 0, -1, 0, -1, 0, 0, +0, 0, -1, -1, 0, 0, -1, 0, 0, -1, +0, 0, -1, -1, -1, 0, 0, 0, 0, -1, +0, -1, 0, 0, -1, 0, -1, 0, 0, 0, +-1, 0, 0, 0, 0, 0, 0, -1, 0, 0, +-1, 0, 0, 0, 0, 0, 0, -1, 0, 0, +0, 0, 0, 0, 0, -1, 0, 0, 0, 0, +0, 0, -1, 0, 0, -1, 0, -1, -1, 0, +0, 0, 0, 0, -1, -1, -1, -1, -1, -1, +0, 0, -1, 0, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, -1, -1, +-1, -1, 0, -1, -1, 0, -1, -1, -1, -1, +-1, 0, 0, 0, 0, -1, -1, 0, 0, -1, +-1, 0, 0, 0, -1, -1, 0, 0, 0, 0, +0, -1, 0, -1, -1, 0, 0, 0, -1, 0, +0, -1, -1, 0, -1, -1, -1, -1, 0, 0, +0, -1, 0, -1, -1, 0, -1, 0, -1, -1, +0, 0, 0, -1, -1, -1, -1, -1, -1, 0, +-1, -1, 0, -1, -1, -1, -1, -1, -1, 0, +-1, -1, -1, 0, 0, 0, -1, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, -1, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, -1, +-1, 0, -1, -1, 0, 0, 0, 0, 0, 0, +0, 0, 0, -1, 0, -1, 0, -1, 0, 0, +-1, -1, 0, -1, 0, 0, -1, 0, -1, -1, +-1, -1, -1, 0, 0, -1, -1, -1, -1, -1, +-1, -1, 0, 0, 0, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, 0, 0, +-1, -1, 0, 0, 0, 0, -1, 0, -1, -1, +0, -1, -1, 0, 0, 0, -1, 0, -1, -1, +-1, -1, 0, -1, -1, -1, -1, 0, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +0, -1, -1, -1, -1, -1, -1, -1, 0, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, 0, -1, +-1, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, -1, 0, +0, 0, 0, 0, 0, 0, 0, 0, -1, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, -1, 0, 0, 0, -1, 0, 0, +-1, 0, 0, 0, -1, -1, -1, -1, -1, 0, +-1, -1, -1, -1, -1, -1, -1, -1, -1, 0, +0, -1, 0, -1, -1, 0, -1, -1, -1, -1, +0, -1, -1, -1, 0, 0, 0, 0, 0, 0, +0, 0, 0, -1, 0, 0, 0, 0, -1, 0, +0, 0, -1, 0, 0, -1, 0, -1, -1, 0, +-1, -1, -1, -1, -1, -1, -1, 0, -1, -1, +-1, -1, -1, -1, -1, -1, 0, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, 0, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, 0, -1, -1, 0, -1, -1, -1, +-1, -1, -1, -1, 0, -1, -1, 0, 0, -1, +0, -1, -1, 0, -1, -1, 0, 0, -1, 0, +0, -1, 0, 0, 0, 0, -1, 0, 0, 0, +0, -1, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, -1, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, -1, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, -1, 0, 0, -1, 0, -1, 0, +0, -1, -1, 0, 0, 0, -1, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, -1, -1, 0, +0, 0, 0, 0, -1, 0, 0, 0, -1, 0, +0, -1, -1, 0, 0, 0, 0, 0, 0, 0, +0, -1, -1, 0, 0, -1, 0, 0, 0, 0, +0, -1, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, -1, 0, -1, +-1, -1, -1, 0, -1, 0, 0, 0, 0, -1, +0, -1, 0, -1, 0, 0, 0, 0, 0, -1, +-1, -1, -1, 0, 0, 0, -1, -1, -1, -1, +-1, -1, 0, -1, -1, -1, 0, 0, -1, -1, +0, -1, 0, 0, 0, 0, 0, -1, -1, 0, +-1, 0, 0, 0, 0, 0, -1, -1, -1, -1, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, -1, 0, 0, 0, -1, 0, 0, +-1, 0, 0, 0, 0, 0, 0, 0, -1, -1, +0, -1, 0, -1, 0, 0, -1, 0, -1, 0, +0, -1, 0, -1, 0, 0, 0, 0, -1, 0, +-1, -1, -1, -1, -1, -1, -1, 0, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, 0, -1, +-1, -1, -1, -1, -1, -1, -1, 0, -1, -1, +-1, -1, -1, -1, 0, -1, 0, -1, 0, 0, +0, 0, 0, 0, -1, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, -1, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, -1, +0, 0, 0, 0, 0, 0, 0, 0, -1, 0, +0, 0, 0, -1, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, -1, -1, 0, 0, +0, 0, 0, 0, 0, 0, 0, -1, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, -1, 0, 0, 0, 0, 0, -1, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, -1, 0, 0, 0, 0, 0, 0, 0, 0, +0, -1, 0, 0, 0, 0, -1, -1, -1, 0, +-1, -1, -1, -1, 0, -1, -1, 0, 0, -1, +-1, -1, 0, 0, -1, -1, -1, -1, -1, -1, +-1, -1, -1, 0, -1, -1, 0, -1, -1, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +-1, 0, 0, 0, 0, -1, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, -1, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, -1, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, -1, 0, -1, -1, 0, 0, 0, 0, 0, +0, -1, -1, 0, 0, 0, -1, 0, 0, 0, +-1, -1, 0, -1, -1, 0, -1, 0, -1, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, 0, -1, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, -1, 0, 0, -1, -1, +-1, 0, 0, 0, 0, 0, 0, -1, -1, 0, +-1, -1, 0, 0, 0, 0, -1, -1, -1, 0, +0, 0, -1, -1, 0, -1, 0, 0, -1, -1, +0, -1, -1, -1, 0, 0, 0, -1, -1, 0, +0, 0, 0, -1, -1, 0, -1, -1, 0, -1, +-1, -1, -1, -1, -1, -1, -1, -1, 0, 0, +-1, -1, 0, 0, -1, -1, -1, -1, -1, 0, +-1, -1, -1, -1, -1, -1, 0, -1, -1, -1, +-1, 0, -1, -1, -1, -1, 0, 0, 0, 0, +0, -1, -1, 0, 0, 0, 0, 0, 0, 0, +0, -1, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, -1, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, -1, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, -1, 0, 0, 0, 0, 0, 0, +0, 0, -1, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, -1, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, -1, -1, 0, 0, 0, +-1, -1, 0, 0, 0, 0, -1, -1, -1, -1, +-1, 0, -1, 0, -1, -1, -1, -1, -1, -1, +0, 0, -1, -1, -1, -1, -1, 0, -1, 0, +0, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, -1, -1, -1, 0, -1, 0, 0, 0, +-1, -1, 0, -1, -1, 0, 0, -1, 0, 0, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, -1, -1, -1, -1, 0, 0, 0, 0, +-1, -1, -1, -1, -1, -1, -1, 0, -1, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, -1, -1, +-1, -1, -1, 0, -1, -1, -1, -1, -1, -1, +0, -1, -1, -1, 0, -1, -1, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, -1, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, -1, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, -1, -1, 0, +0, -1, 0, 0, -1, -1, -1, -1, -1, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, 0, +-1, -1, -1, -1, -1, -1, -1, 0, -1, 0, +-1, -1, -1, -1, -1, -1, 0, -1, -1, -1, +-1, 0, -1, -1, 0, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, 0, -1, +-1, 0, -1, -1, -1, 0, 0, -1, 0, 0, +-1, 0, 0, -1, 0, 0, 0, -1, -1, 0, +-1, -1, -1, -1, 0, -1, -1, -1, -1, 0, +-1, -1, -1, -1, 0, -1, -1, -1, -1, -1, +-1, -1, 0, 0, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, 0, +-1, 0, -1, -1, -1, -1, 0, -1, -1, 0, +-1, -1, -1, 0, -1, -1, 0, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, 0, -1, -1, -1, +-1, -1, -1, -1, 0, 0, -1, -1, -1, -1, +-1, -1, -1, -1, 0, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, -1, -1, +-1, -1, -1, -1, 0, -1, -1, -1, -1, -1, +-1, -1, 0, -1, -1, -1, -1, -1, 0, -1, +-1, -1, -1, 0, 0, -1, -1, 0, -1, -1, +0, 0, -1, -1, -1, -1, 0, 0, 0, 0, +0, -1, -1, -1, -1, -1, -1, 0, 0, 0, +0, -1, -1, -1, -1, -1, -1, -1, 0, -1, +0, 0, -1, 0, 0, -1, -1, 0, 0, -1, +-1, -1, -1, -1, -1, -1, 0, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, 0, -1, +-1, 0, -1, -1, -1, 0, 0, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, 0, -1, -1, -1, -1, -1, -1, +-1, 0, -1, -1, -1, -1, 0, -1, -1, -1, +0, -1, -1, -1, -1, 0, -1, -1, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, 0, 0, +-1, -1, -1, -1, -1, -1, -1, 0, 0, -1, +-1, 0, 0, -1, -1, 0, 0, 0, -1, 0, +0, -1, -1, 0, 0, 0, 0, 0, 0, -1, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +-1, 0, 0, 0, 0, 0, 0, 0, -1, 0, +0, 0, 0, -1, 0, -1, -1, 0, 0, 0, +0, 0, 0, 0, 0, 0, -1, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, -1, 0, 0, -1, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, -1, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, -1, -1, -1, 0, 0, -1, -1, -1, -1, +-1, -1, -1, -1, 0, -1, -1, -1, -1, 0, +-1, -1, -1, -1, 0, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, 0, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, 0, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, 0, -1, +-1, -1, 0, -1, -1, -1, 0, -1, -1, -1, +-1, 0, -1, 0, 0, 0, -1, -1, -1, 0, +0, 0, -1, -1, 0, 0, 0, -1, -1, -1, +-1, -1, -1, 0, -1, -1, -1, -1, 0, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, 0, +0, 0, -1, -1, -1, -1, -1, -1, 0, -1, +-1, 0, 0, 0, 0, 0, 0, 0, -1, 0, +0, 0, -1, -1, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, -1, 0, -1, -1, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, -1, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, -1, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, -1, 0, -1, 0, 0, 0, +0, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, 0, -1, +-1, -1, -1, 0, 0, -1, -1, -1, 0, 0, +-1, -1, -1, -1, -1, -1, -1, -1, 0, -1, +-1, -1, -1, -1, -1, -1, -1, 0, 0, -1, +-1, -1, -1, 0, -1, 0, -1, 0, -1, -1, +-1, -1, 0, -1, -1, -1, -1, -1, -1, -1, +-1, -1, 0, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +0, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, 0, -1, -1, -1, +0, 0, -1, -1, -1, -1, -1, -1, 0, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -2, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, 0, -1, +-1, -1, -1, -1, -1, -1, -1, -1, 0, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, 0, -1, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, 0, +-1, -1, 0, 0, -1, -1, -1, 0, -1, -1, +0, 0, 0, -1, -1, -1, 0, 0, -1, -1, +0, 0, 0, -1, 0, 0, 0, -1, 0, 0, +-1, 0, 0, 0, 0, 0, 0, -1, 0, 0, +0, -1, 0, 0, 0, 0, 0, 0, 0, -1, +-1, -1, -1, 0, 0, 0, 0, 0, -1, 0, +0, 0, 0, 0, 0, -1, 0, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, 0, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, 0, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, 0, 0, -1, +0, 0, 0, -1, 0, 0, -1, -1, 0, 0, +-1, 0, -1, 0, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, 0, -1, 0, -1, -1, 0, +0, 0, -1, 0, 0, 0, 0, 0, 0, 0, +0, 0, -1, 0, -1, 0, 0, 0, 0, 0, +0, 0, -1, -1, 0, 0, -1, -1, -1, -1, +0, -1, -1, -1, -1, -1, -1, -1, 0, 0, +-1, 0, -1, -1, 0, -1, -1, 0, -1, -1, +0, 0, -1, -1, 0, -1, -1, 0, -1, 0, +0, 0, -1, 0, 0, 0, -1, -1, 0, 0, +0, 0, 0, 0, 0, -1, -1, 0, -1, -1, +0, -1, 0, -1, 0, 0, 0, 0, 0, 0, +-1, 0, -1, 0, 0, 0, 0, 0, 0, -1, +0, 0, -1, 0, -1, 0, -1, -1, -1, 0, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, 0, -1, 0, +0, -1, 0, -1, 0, 0, 0, 0, 0, 0, +-1, 0, 0, 0, 0, -1, 0, 0, 0, 0, +0, 0, 0, 0, -1, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, -1, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, -1, +0, -1, 0, 0, 0, 0, -1, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +-1, -1, -1, -1, 0, -1, 0, 0, -1, 0, +-1, 0, -1, -1, 0, 0, -1, 0, 0, -1, +0, 0, -1, 0, 0, 0, 0, -1, -1, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +-1, 0, 0, -1, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, -1, -1, 0, 0, 0, 0, 0, 0, 0, +0, -1, 0, 0, -1, 0, -1, -1, 0, 0, +-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, 0, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, 0, -1, -1, -1, +-1, -1, -1, -1, -1, 0, 0, 0, -1, 0, +0, 0, 0, -1, 0, 0, 0, 0, -1, 0, +0, -1, -1, 0, 0, 0, 0, -1, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, -1, +0, 0, 0, 0, -1, 0, 0, -1, 0, 0, +-1, -1, 0, 0, -1, 0, 0, -1, 0, 0, +-1, -1, -1, 0, -1, -1, 0, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, 0, -1, -1, 0, +-1, -1, 0, 0, -1, -1, -1, -1, 0, 0, +-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, +-1, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, -1, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, -1, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, -1, 0, 0, -1, 0, 0, 0, -1, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +-1, 0, 0, 0, 0, 0, 0, -1, -1, -1, +-1, 0, -1, 0, 0, 0, 0, -1, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, -1, 0, +0, 0, 0, 0, 0, 0, 0, -1, -1, 0, +0, -1, 0, 0, 0, 0, 0, 0, 0, -1, +-1, 0, 0, -1, -1, 0, 0, 0, 0, 0, +0, 0, -1, 0, -1, -1, 0, -1, 0, 0, +0, 0, 0, 0, 0, -1, 0, -1, 0, -1, +0, 0, -1, 0, -1, 0, 0, -1, 0, 0, +0, 0, -1, 0, -1, 0, 0, 0, -1, 0, +-1, 0, -1, -1, 0, -1, 0, -1, 0, -1, +-1, 0, -1, 0, -1, -1, -1, -1, -1, 0, +-1, -1, -1, -1, -1, -1, 0, -1, -1, -1, +-1, 0, -1, -1, -1, -1, 0, -1, -1, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, 0, -1, -1, -1, -1, -1, -1, +-1, 0, -1, -1, -1, -1, 0, -1, -1, -1, +-1, -1, -1, -1, 0, 0, -1, -1, -1, 0, +-1, -1, -1, -1, -1, 0, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, 0, 0, -1, 0, 0, 0, -1, 0, +-1, -1, 0, -1, -1, -1, -1, -1, -1, -1, +0, -1, 0, 0, -1, 0, -1, 0, 0, 0, +-1, 0, 0, 0, -1, 0, 0, 0, 0, -1, +-1, -1, 0, 0, -1, -1, 0, -1, 0, -1, +-1, 0, 0, 0, 0, 0, -1, -1, 0, 0, +-1, -1, -1, -1, -1, 0, -1, -1, 0, -1, +-1, -1, 0, 0, -1, 0, -1, -1, 0, -1, +-1, 0, -1, -1, -1, -1, 0, 0, 0, -1, +0, 0, 0, -1, -1, 0, 0, 0, -1, -1, +-1, 0, -1, -1, 0, -1, -1, 0, -1, -1, +-1, -1, 0, 0, -1, 0, 0, -1, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, -1, 0, +0, 0, 0, 0, 0, -1, 0, 0, 0, 0, +-1, -1, 0, -1, -1, -1, 0, 0, 0, 0, +0, 0, 0, 0, -1, 0, -1, -1, -1, -1, +-1, -1, 0, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, 0, -1, +-1, 0, 0, 0, -1, 0, 0, 0, 0, 0, +0, -1, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, -1, 0, 0, 0, 0, -1, +0, 0, 0, 0, 0, 0, 0, 0, 0, -1, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, -1, 0, 0, 0, +0, 0, 0, -1, 0, -1, 0, 0, -1, 0, +0, 0, 0, 0, -1, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, -1, -1, 0, -1, 0, 0, 0, +0, 0, 0, 0, 0, 0, -1, 0, -1, -1, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, -1, 0, 0, 0, -1, -1, 0, +-1, 0, -1, -1, -1, -1, 0, -1, 0, -1, +-1, -1, -1, 0, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, 0, -1, -1, -1, -1, -1, +0, -1, 0, 0, 0, 0, 0, -1, -1, -1, +0, -1, -1, 0, -1, -1, 0, 0, -1, 0, +-1, 0, -1, 0, 0, -1, -1, -1, 0, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, 0, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, -1, -1, -1, -1, 0, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, 0, -1, 0, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, 0, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, 0, 0, 0, -1, 0, -1, +-1, 0, 0, 0, 0, 0, 0, -1, 0, 0, +0, 0, -1, 0, -1, 0, 0, 0, 0, -1, +-1, 0, 0, 0, -1, 0, 0, -1, 0, -1, +0, -1, 0, 0, 0, 0, 0, 0, 0, -1, +-1, 0, -1, 0, 0, -1, 0, 0, 0, 0, +0, 0, -1, 0, -1, -1, 0, 0, 0, 0, +0, 0, -1, -1, 0, 0, -1, 0, -1, -1, +0, 0, -1, -1, 0, -1, -1, 0, 0, -1, +-1, 0, 0, 0, -1, -1, 0, 0, 0, 0, +-1, 0, 0, 0, -1, -1, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, -1, 0, 0, 0, 0, 0, 0, 0, +0, -1, -1, 0, 0, 0, 0, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, 0, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, -1, -1, +-1, -1, -1, -1, 0, -1, -1, -1, 0, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +0, -1, -1, -1, -1, -1, 0, -1, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, -1, -1, 0, -1, -1, 0, 0, -1, +-1, 0, 0, 0, -1, -1, -1, -1, 0, -1, +-1, -1, -1, 0, 0, 0, 0, -1, -1, 0, +-1, 0, 0, -1, -1, 0, -1, 0, -1, -1, +-1, -1, -1, -1, -1, -1, 0, -1, -1, -1, +0, 0, 0, 0, -1, -1, 0, -1, 0, 0, +0, 0, -1, -1, -1, 0, 0, 0, -1, 0, +-1, -1, -1, -1, 0, -1, -1, -1, 0, 0, +-1, 0, 0, -1, 0, -1, 0, 0, 0, 0, +0, -1, 0, 0, 0, 0, 0, -1, -1, 0, +0, 0, 0, 0, 0, 0, -1, 0, 0, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, 0, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, 0, +-1, -1, -1, -1, -1, -1, -1, -1, 0, -1, +-1, -1, -1, -1, -1, 0, -1, -1, 0, -1, +-1, -1, -1, -1, -1, 0, 0, -1, -1, 0, +0, 0, 0, -1, 0, 0, -1, -1, 0, 0, +0, 0, -1, -1, 0, -1, 0, 0, -1, -1, +-1, -1, -1, -1, 0, -1, -1, -1, -1, 0, +-1, -1, -1, -1, -1, 0, -1, 0, 0, -1, +0, 0, -1, -1, -1, -1, 0, -1, -1, 0, +-1, -1, -1, -1, -1, -1, -1, 0, -1, 0, +-1, -1, -1, -1, 0, 0, -1, -1, -1, 0, +0, -1, 0, -1, 0, 0, 0, -1, 0, 0, +-1, -1, -1, 0, -1, 0, -1, 0, 0, -1, +-1, -1, -1, 0, -1, 0, -1, -1, 0, 0, +-1, 0, 0, 0, 0, 0, 0, 0, 0, -1, +-1, 0, 0, -1, 0, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, 0, 0, -1, -1, -1, -1, 0, 0, -1, +0, -1, -1, 0, 0, -1, -1, 0, -1, 0, +-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, -1, 0, 0, -1, 0, -1, 0, -1, +0, 0, -1, -1, -1, -1, -1, -1, -1, 0, +-1, 0, -1, -1, 0, 0, -1, 0, 0, -1, +-1, 0, -1, -1, 0, -1, 0, 0, 0, -1, +-1, -1, 0, -1, -1, -1, -1, -1, -1, 0, +-1, -1, 0, 0, -1, -1, -1, -1, -1, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, 0, +0, 0, 0, 0, 0, 0, 0, 0, -1, -1, +0, -1, -1, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, -1, 0, +0, 0, -1, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, -1, 0, 0, 0, -1, -1, -1, -1, +0, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, 0, +0, 0, 0, -1, -1, 0, 0, -1, -1, -1, +0, 0, -1, -1, -1, -1, -1, -1, 0, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, 0, -1, -1, -1, -1, +-1, -1, -1, -1, 0, 0, -1, 0, -1, -1, +-1, -1, -1, -1, 0, -1, -1, -1, -1, -1, +-1, -1, 0, -1, -1, -1, -1, 0, 0, -1, +0, -1, 0, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, 0, -1, -1, -1, +0, -1, -1, 0, -1, -1, -1, -1, -1, 0, +0, 0, -1, -1, 0, 0, 0, 0, -1, 0, +0, 0, 0, 0, 0, 0, -1, 0, -1, 0, +0, 0, 0, -1, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, -1, 0, -1, 0, 0, +-1, 0, -1, -1, -1, 0, 0, 0, -1, 0, +-1, 0, 0, -1, -1, 0, 0, -1, -1, 0, +-1, 0, 0, -1, 0, -1, -1, -1, 0, 0, +-1, -1, -1, 0, -1, 0, 0, 0, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, 0, -1, -1, -1, -1, -1, +-1, 0, -1, -1, 0, 0, -1, 0, -1, 0, +0, -1, -1, -1, 0, 0, -1, 0, 0, -1, +-1, 0, 0, -1, -1, -1, 0, 0, 0, -1, +-1, -1, -1, -1, -1, 0, 0, 0, 0, -1, +-1, 0, -1, 0, 0, 0, 0, -1, -1, -1, +-1, 0, -1, -1, 0, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, 0, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +-1, -1, -1, 0, -1, 0, 0, -1, 0, -1, +-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +0, 0, -1, 0, 0, -1, -1, -1, -1, -1, +-1, -1, 0, 0, -1, -1, -1, -1, -1, 0, +-1, 0, 0, 0, 0, -1, -1, -1, -1, -1, +-1, 0, -1, -1, -1, -1, -1, -1, -1, 0, +-1, -1, -1, -1, -1, -1, -1, -2, -2, 7, +13, 13, 15, 10, 0, -7, -7, -3, 0, 1, +2, 1, -2, -7, -11, -12, -12, -13, -14, -19, +-23, -21, -16, -16, -18, -19, -18, -19, -22, -23, +-21, -19, -18, -20, -20, -10, 12, 24, 13, -19, +-72, -130, -187, -252, -325, -366, -353, -283, -170, -50, +55, 134, 165, 146, 98, 44, 7, 9, 42, 71, +112, 180, 248, 291, 308, 306, 282, 256, 244, 206, +109, -1, -119, -252, -328, -274, -96, 100, 224, 281, +315, 345, 363, 357, 327, 271, 198, 134, 124, 187, +279, 365, 391, 330, 229, 125, 27, -61, -122, -163, +-220, -292, -357, -412, -430, -428, -410, -399, -428, -497, +-578, -599, -535, -388, -206, -77, -42, -51, -63, -62, +-40, -19, 3, 2, -26, -49, -97, -208, -315, -335, +-275, -192, -105, -13, 48, 34, -34, -98, -156, -187, +-149, -64, 14, 90, 212, 382, 501, 535, 527, 510, +494, 466, 425, 350, 239, 106, -13, -97, -141, -140, +-112, -62, -8, 9, -40, -83, -50, 43, 152, 203, +154, 17, -178, -354, -428, -421, -377, -282, -156, -90, +-116, -186, -247, -286, -323, -332, -254, -98, 92, 302, +493, 634, 708, 759, 794, 799, 774, 762, 788, 790, +717, 589, 459, 346, 277, 258, 248, 196, 119, 57, +4, -54, -120, -160, -118, -28, 25, 20, -18, -52, +-62, -53, -48, -65, -145, -294, -442, -553, -636, -655, +-580, -443, -317, -290, -362, -501, -699, -911, -1053, -1079, +-1031, -917, -739, -562, -439, -359, -282, -223, -200, -198, +-162, -51, 121, 305, 456, 569, 657, 726, 764, 768, +745, 653, 493, 324, 146, -55, -218, -259, -165, 3, +171, 312, 426, 474, 450, 414, 388, 354, 288, 201, +133, 63, -14, -25, 62, 175, 201, 125, -16, -207, +-424, -634, -815, -956, -1004, -929, -756, -560, -402, -306, +-264, -269, -320, -375, -371, -255, -60, 134, 290, 406, +453, 433, 388, 344, 282, 210, 167, 155, 151, 140, +165, 255, 350, 407, 432, 402, 292, 107, -79, -210, +-301, -354, -346, -270, -192, -144, -87, 13, 137, 239, +298, 279, 175, 7, -187, -372, -485, -487, -387, -229, +-88, 5, 61, 94, 93, 28, -113, -252, -296, -220, +-29, 247, 525, 713, 780, 750, 665, 540, 383, 234, +90, -73, -225, -325, -349, -319, -249, -119, 34, 153, +225, 303, 404, 480, 510, 535, 556, 541, 492, 442, +413, 401, 407, 417, 400, 354, 295, 225, 120, -11, +-128, -198, -222, -208, -167, -101, 10, 150, 228, 210, +139, 66, 30, 63, 166, 294, 365, 358, 321, 225, +50, -146, -292, -362, -384, -368, -328, -286, -265, -244, +-196, -157, -191, -297, -417, -509, -573, -607, -593, -548, +-512, -519, -552, -559, -511, -393, -223, -67, 9, 6, +-43, -115, -196, -278, -346, -375, -394, -444, -498, -512, +-476, -401, -325, -279, -280, -347, -404, -366, -241, -88, +67, 240, 386, 450, 445, 422, 399, 340, 224, 83, +-72, -240, -371, -425, -423, -422, -422, -393, -331, -253, +-181, -110, -41, -5, -33, -121, -236, -338, -377, -331, +-202, -20, 145, 253, 308, 294, 196, 83, 0, -49, +-78, -87, -31, 75, 203, 357, 521, 623, 622, 585, +598, 661, 719, 742, 742, 757, 782, 807, 828, 830, +790, 709, 617, 512, 394, 291, 233, 229, 249, 270, +299, 326, 316, 271, 228, 210, 213, 184, 67, -125, +-318, -446, -488, -411, -249, -51, 134, 250, 266, 164, +-3, -166, -302, -429, -521, -531, -472, -380, -252, -101, +1, 20, -29, -80, -98, -84, -41, 32, 142, 269, +393, 478, 501, 474, 427, 346, 201, -10, -258, -460, +-552, -544, -468, -351, -209, -69, 36, 83, 98, 124, +127, 99, 42, -47, -140, -220, -279, -319, -316, -230, +-87, 13, -12, -155, -328, -487, -625, -716, -760, -767, +-731, -635, -485, -337, -267, -298, -378, -462, -520, -517, +-429, -265, -63, 145, 307, 387, 402, 403, 435, 463, +427, 309, 175, 91, 88, 157, 248, 360, 456, 469, +381, 220, 27, -131, -213, -244, -295, -389, -461, -465, +-409, -320, -177, 7, 147, 189, 164, 114, 39, -54, +-145, -225, -287, -314, -276, -164, -37, 10, -48, -164, +-289, -389, -432, -401, -298, -153, 19, 195, 319, 340, +303, 283, 276, 249, 158, 15, -125, -250, -359, -422, +-422, -355, -230, -66, 95, 202, 278, 378, 516, 625, +658, 648, 622, 544, 406, 283, 229, 239, 296, 391, +492, 549, 539, 490, 437, 376, 275, 165, 103, 113, +181, 271, 354, 394, 386, 337, 294, 277, 282, 335, +416, 467, 441, 323, 183, 98, 59, 28, -8, -53, +-103, -157, -195, -216, -229, -234, -220, -217, -257, -316, +-330, -284, -250, -268, -311, -366, -427, -476, -486, -441, +-351, -248, -163, -88, -31, 1, 18, 17, -35, -176, +-370, -554, -650, -637, -534, -387, -271, -216, -208, -241, +-310, -380, -420, -384, -277, -144, -30, 57, 143, 235, +321, 366, 339, 224, 41, -173, -391, -585, -711, -728, +-682, -642, -594, -489, -330, -173, -51, 16, 10, -70, +-214, -372, -485, -503, -424, -270, -82, 80, 201, 284, +346, 384, 372, 320, 262, 207, 179, 214, 306, 437, +568, 681, 754, 749, 659, 545, 485, 500, 556, 617, +672, 723, 783, 859, 922, 929, 846, 702, 560, 430, +310, 233, 230, 263, 274, 263, 263, 304, 343, 337, +279, 180, 36, -162, -371, -538, -624, -605, -487, -310, +-137, -34, 2, -12, -86, -200, -327, -448, -556, -645, +-698, -684, -601, -477, -331, -195, -114, -120, -182, -237, +-247, -218, -165, -82, 28, 143, 267, 380, 430, 378, +259, 105, -95, -324, -522, -606, -571, -468, -366, -295, +-238, -194, -148, -79, 20, 121, 165, 113, 1, -134, +-246, -274, -228, -166, -140, -145, -167, -197, -231, -261, +-289, -336, -399, -448, -450, -406, -344, -281, -241, -229, +-251, -295, -318, -298, -234, -142, -25, 84, 176, 288, +423, 546, 620, 651, 642, 572, 447, 329, 292, 353, +440, 489, 474, 396, 304, 212, 129, 67, 20, -25, +-57, -81, -128, -193, -240, -238, -182, -89, 22, 123, +182, 188, 160, 130, 89, 29, -40, -111, -169, -218, +-252, -276, -284, -293, -302, -298, -289, -248, -154, -40, +22, 24, 9, 14, 53, 122, 211, 311, 358, 291, +128, -67, -220, -297, -309, -271, -200, -141, -115, -87, +-15, 119, 330, 585, 800, 880, 801, 617, 411, 258, +166, 135, 141, 182, 258, 368, 493, 582, 598, 524, +406, 289, 187, 119, 87, 79, 91, 127, 164, 169, +167, 207, 273, 316, 296, 221, 137, 54, -16, -41, +-1, 75, 138, 132, 56, -49, -163, -255, -298, -304, +-301, -306, -305, -308, -320, -320, -301, -263, -234, -235, +-269, -319, -373, -413, -409, -360, -269, -153, -24, 102, +184, 177, 83, -75, -280, -488, -637, -694, -669, -562, +-413, -288, -245, -282, -325, -316, -278, -264, -274, -282, +-274, -241, -168, -26, 171, 348, 434, 401, 249, 1, +-276, -518, -697, -800, -832, -788, -696, -599, -524, -449, +-350, -247, -182, -180, -239, -334, -426, -475, -461, -408, +-342, -249, -99, 92, 277, 421, 483, 463, 397, 323, +280, 283, 335, 433, 540, 593, 571, 509, 452, 422, +398, 377, 393, 457, 545, 614, 677, 754, 838, 920, +968, 951, 848, 679, 482, 304, 177, 113, 118, 162, +208, 230, 222, 204, 189, 149, 57, -81, -224, -337, +-390, -376, -330, -280, -227, -170, -107, -35, 28, 59, +35, -42, -161, -321, -501, -615, -609, -493, -335, -213, +-150, -126, -106, -85, -54, 2, 68, 121, 147, 164, +187, 230, 292, 342, 335, 260, 147, 32, -72, -161, +-227, -272, -286, -277, -253, -227, -190, -136, -67, 12, +73, 93, 91, 90, 82, 44, -22, -100, -181, -254, +-295, -280, -231, -163, -98, -64, -75, -137, -217, -276, +-279, -255, -259, -283, -290, -278, -272, -279, -285, -273, +-229, -138, -6, 136, 270, 393, 497, 587, 667, 721, +741, 730, 691, 615, 516, 437, 383, 324, 240, 135, +36, -8, 17, 68, 89, 54, -19, -101, -177, -213, +-207, -189, -172, -157, -134, -93, -11, 98, 193, 230, +171, 22, -165, -333, -460, -559, -627, -647, -622, -568, +-504, -423, -343, -285, -265, -295, -352, -383, -345, -236, +-87, 46, 112, 106, 68, 32, -4, -59, -127, -198, +-257, -304, -339, -329, -239, -52, 188, 419, 599, 710, +730, 660, 536, 389, 249, 146, 93, 96, 150, 237, +351, 484, 608, 667, 635, 539, 418, 292, 166, 73, +32, 32, 53, 80, 111, 145, 171, 167, 110, 20, +-64, -122, -123, -57, 41, 131, 210, 264, 271, 217, +105, -19, -111, -142, -136, -157, -226, -294, -311, -271, +-181, -66, 21, 48, 20, -33, -79, -91, -69, -39, +8, 83, 171, 260, 342, 394, 367, 240, 65, -102, +-248, -365, -441, -468, -453, -402, -336, -274, -222, -185, +-192, -249, -323, -406, -473, -482, -419, -290, -123, 54, +199, 256, 191, 22, -201, -419, -569, -648, -700, -733, +-743, -723, -672, -588, -475, -354, -244, -169, -155, -194, +-269, -362, -446, -485, -457, -378, -264, -119, 48, 207, +326, 410, 459, 473, 463, 450, 447, 461, 473, 442, +377, 299, 228, 185, 185, 214, 238, 249, 258, 290, +365, 481, 625, 764, 865, 909, 872, 766, 636, 517, +426, 364, 331, 306, 274, 226, 160, 92, 52, 37, +23, -2, -20, -27, -39, -58, -82, -109, -143, -162, +-131, -36, 82, 170, 181, 108, -7, -138, -261, -336, +-360, -372, -387, -379, -341, -286, -214, -118, -7, 89, +152, 171, 149, 114, 85, 58, 43, 57, 97, 123, +110, 57, -34, -136, -201, -227, -237, -255, -286, -336, +-378, -376, -325, -247, -156, -39, 92, 199, 242, 219, +140, 11, -141, -288, -386, -393, -322, -213, -88, 24, +68, 23, -69, -154, -204, -222, -220, -225, -276, -365, +-455, -498, -468, -388, -308, -261, -229, -188, -131, -41, +90, 251, 426, 591, 720, 787, 790, 746, 671, 573, +456, 324, 194, 94, 35, 17, 9, 0, 12, 46, +83, 101, 91, 64, 24, -40, -131, -209, -225, -171, +-55, 96, 241, 320, 300, 200, 44, -139, -320, -477, +-589, -644, -632, -573, -495, -412, -350, -327, -328, -330, +-330, -335, -342, -343, -324, -264, -153, -20, 90, 150, +152, 118, 64, -3, -96, -217, -321, -348, -286, -157, +11, 192, 361, 494, 568, 579, 560, 522, 446, 319, +177, 72, 28, 70, 206, 395, 573, 695, 746, 710, +603, 477, 364, 286, 246, 224, 199, 177, 169, 160, +136, 92, 35, -32, -95, -122, -104, -51, 21, 104, +179, 227, 254, 257, 226, 176, 117, 38, -64, -168, +-243, -281, -293, -293, -271, -209, -118, -43, -15, -11, +-2, 12, 33, 67, 110, 146, 171, 191, 203, 217, +227, 214, 165, 73, -65, -219, -335, -397, -422, -429, +-407, -347, -274, -220, -217, -264, -333, -398, -436, -443, +-417, -352, -258, -143, -26, 45, 25, -70, -190, -288, +-346, -390, -462, -568, -677, -763, -809, -789, -694, -570, +-475, -430, -416, -409, -395, -378, -385, -429, -481, -508, +-501, -437, -309, -151, 14, 184, 348, 487, 590, 670, +721, 713, 640, 528, 421, 338, 281, 238, 199, 182, +205, 245, 277, 317, 368, 428, 516, 640, 762, 836, +848, 825, 806, 805, 805, 777, 722, 654, 564, 430, +267, 120, 13, -42, -43, 0, 55, 100, 115, 95, +60, 27, 2, -20, -40, -51, -49, -23, 31, 91, +122, 103, 52, -10, -88, -181, -272, -348, -388, -371, +-311, -222, -100, 43, 165, 232, 230, 169, 82, 13, +-7, 17, 57, 67, 34, -14, -38, -33, -19, -3, +1, -37, -149, -307, -450, -528, -519, -448, -347, -223, +-87, 42, 144, 198, 172, 43, -152, -345, -478, -520, +-471, -355, -230, -149, -113, -88, -57, -21, 4, -12, +-79, -167, -264, -364, -444, -485, -488, -463, -416, -371, +-356, -365, -372, -340, -230, -34, 190, 392, 551, 665, +721, 712, 668, 613, 549, 466, 351, 210, 78, -8, +-57, -77, -63, -23, 26, 75, 109, 100, 38, -53, +-137, -206, -255, -252, -172, -34, 117, 235, 267, 205, +84, -63, -212, -332, -408, -459, -502, -534, -540, -511, +-449, -371, -303, -267, -281, -354, -455, -520, -503, -426, +-321, -204, -80, 33, 111, 144, 141, 123, 98, 56, +5, -29, -40, -23, 26, 98, 169, 233, 308, 404, +486, 512, 478, 395, 272, 138, 41, 24, 108, 264, +426, 537, 595, 622, 627, 614, 596, 576, 556, 535, +494, 423, 324, 201, 68, -40, -81, -71, -72, -114, +-181, -228, -216, -134, -10, 114, 207, 242, 212, 159, +124, 100, 63, 10, -49, -110, -152, -156, -129, -115, +-137, -159, -142, -71, 48, 190, 312, 389, 405, 358, +278, 225, 232, 271, 307, 322, 294, 214, 97, -22, +-113, -160, -171, -173, -184, -201, -225, -255, -280, -286, +-280, -282, -301, -322, -326, -307, -277, -259, -258, -264, +-266, -257, -235, -216, -228, -287, -373, -455, -528, -587, +-618, -632, -652, -680, -703, -708, -681, -616, -526, -429, +-339, -288, -311, -400, -510, -586, -588, -504, -342, -134, +82, 279, 438, 558, 643, 686, 680, 634, 557, 451, +309, 150, 24, -28, -9, 45, 102, 144, 166, 169, +178, 222, 302, 378, 431, 479, 547, 634, 728, 818, +854, 790, 636, 448, 285, 169, 92, 26, -37, -91, +-120, -108, -37, 81, 193, 243, 211, 112, -24, -145, +-204, -191, -121, -20, 85, 167, 210, 209, 158, 67, +-39, -121, -161, -169, -152, -103, -10, 119, 237, 301, +311, 285, 224, 140, 62, 0, -67, -140, -173, -152, +-86, 6, 106, 181, 205, 164, 62, -66, -191, -298, +-381, -415, -373, -275, -166, -64, 21, 75, 90, 65, +-3, -118, -258, -387, -475, -503, -470, -393, -293, -187, +-89, -23, 1, -10, -45, -94, -159, -240, -320, -361, +-356, -338, -340, -362, -403, -458, -491, -460, -354, -194, +-4, 187, 355, 483, 579, 655, 717, 754, 729, 620, +460, 307, 198, 141, 131, 143, 143, 127, 117, 126, +159, 203, 223, 193, 117, 24, -40, -58, -30, 22, +73, 109, 129, 140, 137, 100, 15, -91, -195, -288, +-381, -460, -486, -463, -419, -365, -311, -282, -300, -364, +-448, -523, -558, -535, -460, -356, -260, -193, -146, -82, +11, 110, 191, 248, 274, 266, 234, 198, 163, 135, +129, 147, 180, 216, 254, 294, 325, 330, 305, 252, +185, 131, 119, 156, 214, 264, 301, 339, 391, 457, +552, 672, 763, 761, 657, 499, 341, 211, 119, 51, +-18, -105, -210, -311, -383, -409, -379, -308, -211, -122, +-73, -63, -61, -48, -36, -34, -36, -31, -26, -25, +-33, -64, -119, -185, -241, -278, -267, -187, -36, 145, +306, 418, 461, 447, 404, 364, 336, 300, 239, 175, +140, 126, 110, 86, 71, 62, 49, 29, -7, -74, +-174, -285, -368, -388, -342, -261, -193, -178, -226, -318, +-404, -433, -419, -406, -420, -446, -466, -474, -463, -434, +-402, -376, -355, -356, -393, -457, -534, -624, -732, -832, +-877, -836, -717, -557, -404, -302, -285, -347, -440, -509, +-535, -508, -409, -244, -60, 104, 255, 417, 593, 751, +858, 881, 805, 649, 460, 300, 207, 176, 177, 197, +228, 255, 257, 244, 234, 227, 217, 225, 279, 378, +509, 647, 761, 825, 838, 819, 770, 691, 590, 477, +354, 212, 55, -78, -148, -136, -49, 83, 213, 288, +282, 219, 126, 17, -86, -144, -128, -58, 25, 91, +132, 151, 151, 135, 109, 88, 62, 22, -19, -36, +-19, 34, 117, 215, 288, 296, 245, 161, 69, -11, +-76, -125, -156, -162, -131, -65, 19, 93, 131, 118, +58, -21, -86, -127, -163, -206, -254, -298, -329, -323, +-266, -180, -108, -81, -95, -148, -239, -357, -465, -528, +-528, -481, -420, -361, -301, -244, -199, -158, -120, -107, +-129, -175, -230, -291, -353, -398, -427, -455, -484, -495, +-474, -422, -341, -238, -120, 4, 139, 279, 415, 526, +596, 620, 598, 539, 460, 394, 355, 327, 299, 265, +212, 127, 25, -47, -56, -19, 35, 93, 143, 170, +156, 105, 45, 13, 8, 14, 26, 35, 24, -14, +-61, -97, -134, -185, -247, -316, -388, -455, -484, -469, +-433, -399, -383, -391, -410, -423, -418, -400, -391, -397, +-410, -406, -363, -265, -117, 47, 192, 295, 365, 414, +446, 461, 452, 401, 296, 160, 49, 8, 35, 100, +164, 222, 284, 339, 366, 361, 325, 254, 164, 95, +84, 130, 224, 358, 506, 629, 707, 739, 723, 655, +550, 425, 294, 166, 46, -66, -168, -242, -278, -268, +-218, -155, -109, -91, -95, -107, -116, -108, -78, -37, +14, 73, 119, 130, 108, 75, 31, -33, -112, -187, +-231, -220, -152, -44, 100, 268, 420, 513, 539, 508, +441, 362, 295, 242, 182, 123, 97, 110, 143, 178, +194, 167, 76, -60, -206, -317, -356, -324, -256, -195, +-167, -173, -194, -213, -232, -262, -310, -378, -453, -516, +-549, -548, -525, -475, -399, -319, -257, -222, -215, -236, +-303, -431, -595, -740, -815, -816, -766, -685, -600, -534, +-495, -466, -440, -427, -425, -426, -424, -412, -356, -231, +-46, 161, 357, 520, 641, 707, 698, 610, 467, 323, +221, 179, 187, 208, 215, 196, 152, 96, 45, 22, +31, 67, 130, 213, 304, 397, 488, 573, 647, 701, +717, 697, 655, 585, 460, 278, 87, -63, -153, -175, +-127, -38, 56, 138, 193, 201, 157, 90, 35, 1, +-12, -15, -16, -18, -18, -3, 28, 84, 154, 204, +205, 160, 106, 79, 94, 148, 216, 278, 326, 341, +319, 266, 196, 122, 55, 7, -14, -12, 2, 16, +25, 37, 48, 52, 60, 93, 141, 166, 143, 77, +-17, -124, -214, -267, -283, -273, -243, -207, -191, -212, +-255, -296, -327, -344, -354, -367, -380, -382, -373, -357, +-328, -270, -184, -94, -32, -24, -73, -154, -247, -331, +-385, -410, -426, -455, -488, -500, -469, -393, -284, -152, +-8, 128, 240, 325, 388, 411, 383, 335, 315, 345, +412, 488, 532, 503, 393, 237, 82, -41, -107, -98, +-25, 71, 154, 202, 212, 198, 178, 151, 110, 60, +4, -63, -136, -198, -231, -224, -179, -134, -123, -154, +-209, -277, -351, -413, -456, -476, -477, -461, -426, -390, +-377, -407, -465, -515, -539, -541, -512, -443, -351, -255, +-147, -9, 153, 324, 481, 596, 640, 605, 516, 387, +233, 82, -30, -73, -29, 90, 239, 362, 434, 441, +378, 274, 175, 102, 67, 66, 91, 145, 240, 381, +536, 672, 759, 782, 738, 630, 482, 321, 170, 36, +-78, -160, -193, -189, -164, -128, -87, -71, -100, -146, +-169, -150, -97, -36, 5, 16, 18, 40, 85, 129, +146, 121, 53, -39, -126, -179, -173, -87, 59, 225, +376, 497, 570, 587, 552, 474, 377, 288, 218, 173, +159, 172, 201, 225, 220, 179, 114, 38, -41, -120, +-179, -207, -214, -217, -209, -185, -165, -165, -187, -229, +-299, -397, -502, -593, -649, -660, -632, -580, -516, -441, +-358, -287, -251, -254, -295, -353, -404, -463, -552, -657, +-739, -774, -753, -689, -603, -522, -457, -423, -415, -409, +-387, -346, -290, -225, -141, -25, 114, 259, 380, 458, +488, 473, 430, 391, 378, 377, 370, 344, 295, 220, +134, 63, 22, 9, 18, 38, 64, 102, 163, 256, +358, 450, 528, 584, 623, 652, 657, 619, 547, 457, +351, 236, 125, 35, -15, -30, -25, -14, 5, 40, +87, 122, 131, 117, 90, 53, 7, -37, -69, -81, +-69, -32, 34, 121, 197, 247, 281, 309, 330, 350, +378, 394, 374, 314, 230, 156, 112, 105, 125, 139, +132, 102, 55, 5, -35, -72, -103, -110, -80, -27, +32, 92, 141, 168, 160, 115, 37, -64, -167, -259, +-332, -383, -405, -402, -381, -348, -308, -263, -230, -240, +-303, -397, -485, -540, -545, -488, -388, -292, -224, -184, +-168, -171, -192, -217, -240, -270, -311, -370, -430, -465, +-458, -412, -326, -200, -56, 79, 192, 263, 270, 232, +195, 199, 250, 328, 412, 478, 513, 504, 445, 343, +215, 90, -8, -67, -81, -53, 1, 66, 127, 176, +215, 235, 223, 171, 91, -11, -131, -238, -297, -291, +-231, -150, -82, -56, -84, -160, -256, -334, -371, -373, +-373, -389, -410, -422, -420, -405, -400, -426, -475, -519, +-538, -530, -493, -423, -310, -159, 19, 214, 414, 606, +760, 833, 800, 665, 472, 277, 128, 49, 43, 91, +161, 221, 258, 278, 279, 264, 243, 214, 165, 89, +13, -16, 27, 142, 298, 451, 573, 656, 692, 665, +587, 476, 346, 218, 112, 35, -13, -42, -63, -92, +-133, -167, -164, -121, -65, -26, -21, -43, -67, -73, +-57, -22, 26, 81, 124, 140, 127, 89, 38, -4, +-29, -15, 55, 172, 303, 414, 480, 493, 459, 412, +386, 383, 382, 360, 314, 257, 209, 170, 131, 101, +77, 48, 1, -55, -104, -133, -138, -128, -124, -137, +-161, -184, -207, -253, -333, -440, -552, -639, -686, -693, +-671, -634, -603, -590, -586, -568, -520, -437, -344, -281, +-268, -303, -378, -484, -603, -701, -760, -775, -751, -706, +-660, -624, -586, -537, -471, -392, -316, -258, -202, -137, +-73, -12, 52, 123, 196, 267, 331, 388, 437, 475, +483, 440, 354, 259, 180, 119, 69, 20, -21, -38, +-14, 42, 115, 193, 266, 331, 386, 427, 443, 443, +444, 454, 470, 487, 500, 485, 419, 306, 180, 66, +-3, -17, 6, 42, 71, 90, 106, 127, 150, 147, +109, 57, 6, -35, -59, -54, -18, 39, 116, 210, +309, 412, 518, 599, 623, 576, 483, 385, 312, 271, +249, 235, 235, 234, 213, 166, 101, 38, -12, -53, +-100, -157, -201, -207, -160, -76, 30, 143, 232, 273, +252, 165, 28, -132, -287, -411, -481, -502, -489, -453, +-397, -335, -291, -276, -289, -324, -377, -430, -464, -465, +-427, -365, -305, -267, -242, -210, -165, -117, -89, -104, +-153, -213, -267, -302, -304, -261, -177, -69, 35, 111, +150, 162, 161, 153, 143, 156, 201, 264, 327, 381, +426, 460, 482, 470, 408, 301, 167, 43, -34, -51, +-24, 17, 62, 118, 179, 224, 234, 191, 92, -40, +-167, -256, -289, -265, -207, -161, -151, -171, -195, -198, +-179, -163, -177, -218, -270, -317, -346, -351, -343, -344, +-370, -417, -481, -551, -603, -628, -627, -600, -531, -413, +-252, -64, 129, 306, 453, 552, 585, 560, 490, 393, +282, 181, 112, 71, 41, 24, 23, 41, 71, 101, +122, 124, 110, 77, 27, -16, -18, 38, 149, 283, +395, 457, 478, 483, 486, 489, 488, 472, 423, 338, +230, 117, 18, -49, -86, -102, -101, -86, -66, -53, +-48, -54, -66, -76, -78, -73, -59, -27, 16, 57, +89, 115, 129, 133, 143, 170, 216, 261, 287, 278, +247, 226, 234, 269, 326, 388, 426, 420, 377, 316, +266, 238, 223, 193, 133, 63, 7, -15, -5, 24, +54, 77, 99, 112, 100, 54, -21, -125, -244, -356, +-446, -507, -544, -564, -581, -600, -620, -643, -662, -660, +-626, -566, -488, -397, -312, -263, -269, -330, -428, -526, +-598, -651, -704, -758, -790, -785, -730, -628, -494, -350, +-219, -129, -95, -104, -120, -115, -87, -37, 24, 93, +169, 261, 360, 438, 484, 499, 482, 435, 363, 279, +195, 118, 52, 4, -11, 18, 85, 167, 241, 283, +278, 236, 194, 181, 201, 250, 319, 397, 464, 496, +471, 388, 282, 183, 105, 49, 9, -17, -26, -17, +0, 18, 41, 77, 110, 110, 64, -10, -84, -133, +-133, -85, 0, 122, 277, 442, 582, 662, 673, 633, +570, 509, 456, 419, 396, 371, 334, 290, 249, 213, +177, 141, 97, 35, -40, -120, -189, -234, -239, -196, +-92, 61, 219, 316, 324, 247, 117, -27, -163, -278, +-378, -455, -499, -516, -515, -492, -443, -385, -348, -343, +-366, -397, -414, -409, -403, -412, -430, -438, -419, -367, +-293, -223, -173, -149, -151, -172, -188, -178, -143, -93, +-43, -6, 7, 4, 6, 23, 55, 92, 120, 133, +140, 142, 152, 186, 252, 333, 394, 417, 397, 344, +269, 187, 111, 55, 44, 84, 141, 183, 203, 198, +174, 137, 94, 41, -13, -54, -85, -122, -167, -215, +-250, -259, -249, -233, -222, -209, -200, -205, -227, -248, +-255, -253, -252, -264, -301, -362, -433, -508, -568, -600, +-603, -571, -499, -392, -274, -167, -71, 30, 152, 286, +412, 499, 529, 516, 468, 385, 285, 199, 135, 79, +24, -18, -39, -28, 12, 55, 72, 67, 63, 80, +117, 158, 182, 183, 172, 164, 167, 195, 265, 362, +445, 481, 463, 401, 322, 239, 157, 81, 17, -35, +-70, -85, -79, -61, -40, -21, -9, -14, -43, -90, +-141, -173, -165, -120, -60, 13, 110, 224, 326, 396, +426, 421, 397, 368, 340, 317, 311, 326, 357, 392, +421, 442, 457, 467, 464, 437, 383, 315, 233, 138, +56, 10, 14, 64, 137, 205, 249, 256, 220, 150, +61, -31, -121, -201, -269, -325, -375, -420, -457, -496, +-541, -587, -634, -677, -700, -681, -622, -544, -461, -385, +-332, -316, -341, -411, -514, -633, -752, -858, -932, -951, +-901, -785, -631, -475, -352, -272, -214, -171, -144, -124, +-110, -104, -104, -97, -69, -10, 71, 155, 229, 290, +330, 340, 317, 268, 203, 135, 85, 72, 94, 132, +169, 192, 190, 172, 156, 138, 114, 94, 94, 122, +177, 250, 325, 381, 403, 389, 339, 273, 209, 155, +107, 56, 5, -36, -53, -30, 18, 65, 88, 79, +36, -31, -100, -144, -141, -88, 3, 117, 235, 344, +437, 509, 564, 603, 616, 605, 576, 544, 510, 475, +435, 388, 352, 335, 324, 302, 269, 221, 149, 56, +-36, -99, -111, -65, 21, 122, 210, 275, 311, 308, +265, 187, 81, -38, -161, -283, -397, -484, -531, -548, +-543, -526, -503, -474, -440, -404, -371, -353, -357, -382, +-418, -452, -476, -489, -490, -475, -449, -413, -359, -285, +-197, -103, -18, 33, 48, 47, 50, 50, 45, 46, +65, 105, 147, 171, 170, 155, 149, 167, 211, 274, +342, 391, 401, 373, 316, 256, 223, 227, 245, 250, +233, 201, 163, 124, 91, 67, 47, 25, -2, -34, +-70, -116, -171, -219, -247, -258, -259, -253, -247, -249, +-255, -260, -260, -250, -229, -209, -215, -249, -305, -375, +-451, -528, -585, -598, -553, -467, -377, -309, -266, -231, +-188, -127, -34, 83, 213, 342, 454, 524, 545, 525, +483, 421, 338, 240, 141, 53, -19, -75, -108, -111, +-84, -33, 39, 120, 182, 202, 178, 126, 66, 17, +-3, 6, 51, 124, 196, 245, 271, 280, 274, 244, +191, 130, 69, 11, -42, -91, -123, -123, -88, -38, +3, 19, -7, -79, -175, -257, -294, -265, -164, -15, +137, 260, 349, 415, 464, 491, 488, 457, 412, 372, +344, 332, 330, 332, 339, 358, 392, 433, 463, 460, +411, 325, 224, 129, 63, 45, 77, 134, 185, 216, +234, 238, 217, 166, 91, 10, -60, -123, -195, -275, +-347, -402, -441, -465, -481, -508, -554, -615, -673, -721, +-738, -700, -609, -489, -378, -302, -275, -303, -382, -498, +-619, -716, -770, -773, -734, -666, -587, -507, -429, -356, +-285, -221, -168, -127, -98, -85, -92, -111, -116, -89, +-31, 37, 103, 157, 193, 207, 190, 147, 110, 108, +137, 176, 209, 226, 228, 217, 200, 178, 144, 103, +64, 30, 1, -15, -2, 52, 137, 221, 284, 326, +354, 371, 367, 339, 285, 212, 140, 90, 74, 90, +119, 128, 105, 56, 0, -47, -72, -61, -22, 28, +81, 145, 225, 314, 396, 462, 513, 566, 621, 657, +655, 624, 585, 550, 525, 508, 488, 453, 401, 338, +268, 193, 130, 89, 68, 49, 21, -8, -17, 9, +60, 112, 150, 172, 179, 169, 135, 74, -9, -107, +-208, -304, -388, -461, -524, -572, -595, -587, -560, -516, +-454, -389, -345, -332, -353, -401, -460, -526, -595, -648, +-653, -597, -502, -393, -281, -173, -83, -18, 20, 34, +28, 17, 13, 16, 18, 24, 38, 63, 86, 90, +76, 62, 61, 73, 87, 95, 100, 109, 133, 177, +239, 304, 353, 367, 339, 282, 215, 148, 96, 68, +51, 30, 2, -27, -52, -68, -85, -118, -159, -189, +-204, -222, -252, -276, -279, -259, -223, -179, -144, -131, +-144, -187, -258, -338, -406, -447, -459, -445, -411, -358, +-287, -221, -181, -168, -162, -144, -99, -28, 60, 160, +263, 362, 446, 507, 550, 564, 529, 445, 329, 195, +63, -47, -120, -145, -119, -54, 28, 114, 187, 225, +211, 156, 94, 44, 5, -23, -35, -23, 18, 85, +157, 206, 228, 232, 220, 190, 142, 81, 21, -20, +-39, -37, -12, 28, 63, 60, 5, -95, -210, -304, +-347, -327, -255, -145, -19, 99, 207, 309, 403, 479, +530, 551, 540, 503, 445, 381, 333, 317, 331, 355, +384, 415, 435, 422, 376, 314, 257, 215, 193, 184, +180, 185, 203, 224, 239, 238, 221, 194, 163, 127, +79, 22, -40, -110, -194, -280, -348, -384, -397, -415, +-461, -541, -633, -708, -735, -695, -600, -497, -424, -389, +-387, -410, -452, -505, -558, -593, -606, -603, -595, -576, +-545, -511, -482, -448, -393, -319, -241, -183, -160, -168, +-182, -176, -151, -115, -76, -46, -28, -20, -23, -30, +-30, -12, 26, 80, 139, 194, 234, 249, 238, 205, +171, 149, 135, 115, 87, 52, 12, -23, -39, -23, +12, 59, 110, 164, 213, 250, 264, 267, 275, 294, +303, 285, 251, 209, 158, 92, 18, -49, -92, -100, +-75, -33, 17, 71, 125, 171, 207, 238, 277, 336, +413, 488, 546, 580, 600, 619, 636, 654, 668, 665, +632, 556, 442, 324, 230, 179, 170, 189, 210, 205, +171, 124, 86, 68, 67, 73, 83, 100, 115, 116, +106, 101, 98, 78, 22, -60, -155, -256, -365, -483, +-591, -655, -651, -585, -486, -385, -305, -267, -280, -343, +-447, -571, -675, -729, -730, -688, -612, -510, -391, -272, +-166, -79, 0, 66, 106, 107, 79, 44, 21, 26, +58, 99, 127, 132, 118, 94, 70, 42, 1, -38, +-47, -15, 43, 116, 197, 277, 339, 367, 361, 332, +302, 272, 227, 161, 90, 35, -4, -36, -65, -88, +-102, -106, -110, -133, -179, -228, -258, -257, -229, -186, +-139, -98, -81, -105, -167, -236, -286, -315, -334, -349, +-362, -367, -349, -304, -240, -174, -128, -114, -120, -128, +-129, -121, -88, -17, 84, 199, 313, 424, 526, 603, +626, 574, 456, 316, 186, 81, 0, -55, -77, -65, +-26, 22, 63, 93, 115, 119, 96, 43, -28, -94, +-135, -146, -135, -102, -44, 24, 78, 102, 105, 99, +91, 84, 77, 66, 59, 55, 50, 45, 35, 2, +-61, -141, -211, -259, -283, -279, -248, -196, -132, -63, +16, 124, 260, 395, 491, 535, 545, 538, 521, 500, +474, 445, 425, 415, 404, 381, 347, 315, 301, 301, +304, 296, 283, 276, 275, 266, 254, 247, 244, 236, +219, 202, 187, 173, 147, 102, 41, -29, -104, -176, +-231, -264, -298, -349, -420, -495, -556, -591, -595, -572, +-534, -500, -489, -509, -544, -569, -571, -561, -541, -518, +-495, -476, -468, -476, -489, -488, -466, -428, -389, -359, +-334, -305, -259, -205, -157, -115, -75, -42, -31, -46, +-78, -108, -129, -139, -134, -111, -64, -1, 67, 141, +212, 253, 256, 234, 209, 192, 172, 140, 90, 30, +-27, -76, -112, -128, -121, -107, -97, -84, -58, -9, +60, 143, 223, 292, 343, 368, 355, 298, 209, 103, +5, -67, -111, -130, -121, -82, -29, 25, 76, 129, +186, 240, 291, 339, 387, 435, 475, 506, 544, 599, +665, 732, 783, 795, 746, 636, 499, 379, 306, 286, +292, 296, 291, 276, 244, 197, 149, 112, 87, 68, +48, 27, 10, 0, 4, 15, 36, 61, 70, 50, +-12, -123, -271, -418, -532, -600, -620, -593, -522, -433, +-356, -313, -313, -350, -418, -501, -576, -626, -646, -645, +-624, -573, -491, -390, -277, -156, -36, 64, 127, 147, +135, 121, 121, 134, 158, 193, 226, 235, 206, 143, +66, -6, -65, -107, -128, -116, -67, 4, 81, 150, +199, 229, 252, 270, 273, 256, 219, 173, 117, 53, +-7, -54, -81, -90, -97, -110, -133, -171, -218, -256, +-259, -223, -166, -109, -68, -60, -93, -154, -218, -259, +-267, -262, -270, -294, -308, -296, -259, -206, -137, -70, +-24, -13, -35, -72, -105, -124, -132, -119, -69, 19, +134, 250, 344, 397, 411, 407, 388, 343, 271, 189, +112, 45, -9, -49, -68, -58, -24, 17, 56, 83, +85, 54, 0, -58, -106, -136, -143, -129, -105, -84, +-78, -82, -74, -38, 19, 78, 123, 158, 180, 179, +154, 110, 64, 23, -16, -66, -115, -148, -163, -172, +-176, -170, -145, -94, -15, 78, 165, 238, 305, 372, +432, 482, 523, 561, 587, 584, 540, 467, 389, 315, +250, 207, 195, 209, 240, 279, 314, 335, 337, 326, +312, 303, 300, 285, 250, 209, 179, 162, 149, 131, +108, 77, 40, -10, -77, -146, -204, -256, -309, -354, +-380, -386, -384, -386, -411, -467, -534, -587, -621, -637, +-637, -618, -579, -530, -483, -444, -404, -359, -322, -307, +-311, -321, -342, -365, -372, -351, -295, -212, -123, -48, +-1, 11, -12, -61, -110, -144, -175, -210, -235, -236, +-207, -150, -77, 0, 76, 149, 202, 226, 229, 225, +211, 182, 143, 99, 56, 23, -3, -38, -93, -157, +-205, -228, -221, -186, -118, -17, 99, 201, 264, 288, +280, 239, 173, 98, 27, -37, -90, -127, -137, -116, +-69, -6, 63, 137, 207, 258, 284, 298, 313, 337, +367, 408, 466, 548, 637, 705, 732, 723, 680, 607, +516, 436, 383, 360, 355, 356, 347, 329, 312, 304, +294, 265, 211, 144, 76, 12, -48, -92, -99, -65, +-8, 50, 93, 105, 72, -3, -110, -221, -317, -384, +-427, -451, -455, -449, -442, -432, -411, -391, -394, -430, +-487, -541, -571, -575, -567, -549, -510, -443, -364, -283, +-196, -110, -42, 6, 40, 71, 112, 165, 221, 263, +275, 261, 229, 185, 131, 64, -4, -55, -83, -94, +-94, -76, -35, 15, 66, 114, 157, 189, 208, 211, +197, 171, 137, 92, 51, 20, -5, -41, -92, -145, +-185, -208, -213, -202, -169, -113, -55, -27, -38, -75, +-125, -183, -240, -285, -313, -328, -330, -322, -308, -285, +-241, -173, -94, -31, 0, 2, -9, -29, -57, -80, +-82, -61, -26, 15, 61, 110, 157, 200, 238, 271, +300, 317, 314, 295, 262, 215, 156, 97, 53, 28, +19, 18, 19, 25, 35, 34, 10, -22, -40, -44, +-50, -71, -108, -156, -208, -245, -247, -208, -130, -32, +60, 123, 150, 145, 123, 97, 63, 15, -36, -74, +-94, -104, -109, -104, -88, -60, -23, 16, 49, 75, +91, 106, 140, 203, 290, 386, 483, 567, 622, 637, +614, 559, 486, 403, 318, 239, 190, 189, 219, 254, +284, 312, 340, 363, 380, 388, 380, 353, 306, 247, +192, 160, 155, 167, 174, 153, 101, 32, -34, -96, +-153, -197, -217, -218, -213, -210, -222, -254, -306, -380, +-467, -550, -617, -666, -695, -699, -678, -638, -579, -504, +-420, -339, -279, -255, -271, -308, -345, -377, -399, -390, +-339, -261, -184, -125, -89, -76, -81, -98, -122, -145, +-166, -195, -233, -273, -301, -299, -255, -179, -93, -22, +33, 78, 105, 106, 94, 82, 82, 92, 93, 76, +39, -18, -99, -188, -258, -290, -280, -235, -164, -77, +13, 96, 159, 197, 212, 205, 174, 125, 79, 46, +14, -24, -55, -58, -30, 21, 84, 142, 187, 214, +227, 235, 253, 290, 347, 417, 492, 557, 604, 638, +661, 663, 637, 592, 546, 512, 484, 455, 426, 407, +399, 395, 393, 394, 394, 382, 345, 284, 204, 117, +38, -20, -47, -42, -21, -5, -4, -9, -15, -30, +-54, -74, -90, -117, -166, -236, -311, -373, -413, -436, +-450, -462, -479, -503, -528, -543, -546, -536, -510, -469, +-431, -405, -384, -357, -316, -269, -217, -157, -83, 0, +78, 145, 199, 237, 251, 246, 227, 197, 156, 106, +51, 4, -27, -47, -59, -59, -38, 2, 44, 83, +124, 159, 174, 171, 170, 185, 217, 240, 233, 187, +110, 20, -66, -134, -171, -183, -180, -166, -146, -125, +-102, -74, -57, -67, -108, -169, -231, -282, -320, -353, +-377, -383, -362, -320, -258, -186, -121, -72, -43, -30, +-26, -21, -14, -8, -1, 8, 15, 7, -6, -6, +6, 24, 50, 93, 152, 207, 236, 240, 233, 231, +233, 220, 193, 160, 128, 94, 62, 34, 11, 1, +3, 7, 1, -17, -43, -73, -113, -167, -228, -272, +-279, -247, -187, -110, -33, 26, 61, 73, 68, 51, +26, -6, -45, -84, -116, -138, -143, -118, -60, 2, +38, 44, 35, 23, 13, 15, 43, 106, 196, 291, +377, 458, 541, 610, 647, 641, 593, 515, 427, 348, +288, 250, 237, 246, 267, 291, 315, 342, 373, 401, +404, 372, 321, 272, 239, 226, 222, 214, 193, 154, +101, 41, -16, -59, -90, -113, -120, -108, -97, -104, +-124, -152, -196, -264, -351, -439, -522, -602, -680, -740, +-755, -717, -641, -552, -461, -376, -309, -264, -244, -246, +-260, -272, -273, -262, -239, -208, -173, -141, -127, -136, +-154, -162, -152, -137, -133, -146, -176, -214, -243, -255, +-245, -213, -164, -114, -80, -61, -49, -41, -26, 11, +69, 120, 138, 116, 67, 3, -66, -138, -201, -240, +-252, -246, -224, -179, -110, -37, 19, 54, 66, 66, +59, 50, 36, 15, -11, -37, -49, -40, -7, 45, +108, 153, 164, 149, 134, 142, 181, 243, 319, 396, +467, 525, 564, 587, 605, 616, 611, 592, 571, 554, +531, 499, 466, 442, 430, 425, 429, 440, 453, 451, +420, 364, 304, 247, 187, 121, 51, -14, -73, -120, +-151, -162, -150, -118, -76, -35, -11, -12, -43, -100, +-180, -267, -343, -395, -431, -469, -516, -559, -585, -582, +-547, -494, -436, -383, -348, -344, -361, -374, -363, -328, +-274, -200, -113, -29, 44, 110, 171, 225, 261, 268, +253, 236, 217, 186, 146, 107, 78, 55, 35, 23, +22, 34, 49, 55, 44, 26, 19, 38, 83, 139, +187, 212, 204, 158, 80, -5, -78, -128, -158, -175, +-186, -192, -186, -168, -144, -119, -96, -86, -100, -139, +-190, -248, -310, -362, -387, -372, -324, -264, -211, -166, +-125, -93, -76, -62, -33, 13, 62, 106, 138, 158, +162, 145, 105, 55, 11, -11, -6, 19, 54, 89, +122, 156, 192, 226, 259, 284, 281, 240, 168, 86, +20, -10, -9, 3, 11, 7, -18, -65, -119, -165, +-201, -235, -264, -276, -266, -237, -201, -164, -121, -70, +-26, -4, 4, 6, -9, -52, -110, -158, -176, -158, +-113, -53, 11, 66, 101, 110, 96, 68, 43, 36, +53, 91, 143, 214, 300, 390, 472, 540, 592, 620, +615, 570, 492, 406, 337, 288, 259, 250, 261, 279, +294, 302, 309, 315, 317, 317, 321, 332, 342, 333, +300, 260, 223, 178, 118, 57, 11, -14, -29, -39, +-46, -48, -51, -60, -79, -103, -129, -162, -212, -291, +-396, -512, -608, -665, -685, -671, -630, -572, -507, -446, +-395, -348, -301, -254, -221, -206, -195, -176, -153, -135, +-128, -134, -151, -175, -194, -199, -190, -175, -171, -182, +-191, -190, -189, -190, -186, -179, -178, -192, -213, -218, +-194, -145, -88, -35, 8, 42, 57, 47, 18, -20, +-59, -90, -117, -147, -176, -191, -187, -167, -138, -107, +-80, -57, -41, -35, -35, -26, -7, 8, 8, 2, +4, 17, 42, 76, 110, 137, 146, 139, 131, 143, +181, 231, 287, 354, 427, 487, 526, 550, 571, 588, +594, 588, 573, 559, 552, 544, 531, 517, 505, 496, +483, 458, 425, 399, 391, 397, 401, 390, 353, 289, +200, 98, -8, -107, -176, -210, -214, -193, -147, -79, +-14, 23, 22, -13, -73, -144, -221, -298, -373, -453, +-542, -618, -650, -630, -577, -510, -442, -384, -355, -356, +-372, -379, -365, -335, -296, -251, -194, -125, -49, 24, +86, 130, 161, 180, 186, 177, 159, 140, 125, 116, +108, 101, 95, 94, 89, 72, 39, 5, -20, -36, +-35, -13, 31, 85, 132, 155, 150, 123, 79, 24, +-19, -41, -52, -72, -102, -128, -143, -150, -149, -137, +-117, -101, -107, -140, -190, -243, -284, -311, -324, -320, +-300, -270, -234, -200, -174, -152, -130, -104, -70, -24, +33, 101, 170, 222, 240, 224, 187, 142, 91, 43, +5, -19, -33, -34, -15, 32, 110, 195, 261, 296, +294, 253, 184, 117, 77, 64, 61, 56, 45, 22, +-20, -84, -155, -215, -251, -267, -269, -262, -247, -228, +-209, -191, -172, -147, -115, -86, -77, -94, -131, -173, +-206, -223, -222, -205, -168, -108, -40, 17, 59, 87, +101, 105, 100, 94, 98, 120, 146, 173, 211, 271, +351, 439, 524, 590, 613, 585, 525, 464, 421, 397, +387, 384, 380, 362, 326, 279, 244, 238, 256, 286, +318, 342, 355, 354, 331, 284, 219, 151, 94, 51, +22, 9, 7, 16, 30, 39, 35, 28, 26, 20, +-1, -51, -126, -213, -304, -395, -475, -533, -562, -571, +-574, -569, -549, -519, -482, -432, -372, -308, -252, -204, +-158, -114, -82, -70, -71, -77, -83, -100, -128, -163, +-195, -215, -221, -208, -180, -141, -107, -91, -107, -148, +-198, -240, -260, -257, -236, -205, -163, -117, -82, -68, +-74, -92, -105, -111, -116, -121, -122, -123, -133, -151, +-162, -157, -147, -144, -153, -169, -193, -214, -221, -200, +-158, -113, -79, -52, -27, -2, 20, 43, 72, 104, +128, 141, 148, 159, 182, 220, 270, 324, 379, 434, +480, 510, 525, 527, 523, 521, 524, 533, 548, 570, +588, 595, 580, 542, 492, 449, 424, 418, 433, 468, +510, 531, 511, 452, 364, 253, 125, 0, -105, -180, +-224, -234, -208, -148, -75, -12, 30, 50, 40, -7, +-90, -192, -299, -401, -486, -548, -581, -584, -561, -528, +-491, -452, -414, -380, -353, -337, -329, -317, -293, -257, +-216, -172, -125, -70, -8, 50, 95, 121, 131, 126, +109, 96, 107, 144, 185, 211, 215, 200, 170, 128, +83, 45, 17, -4, -19, -19, 1, 32, 53, 57, +47, 28, 4, -18, -37, -48, -51, -51, -59, -73, +-85, -93, -99, -109, -128, -155, -181, -204, -224, -244, +-262, -273, -271, -262, -251, -243, -233, -217, -200, -187, +-169, -133, -79, -17, 48, 121, 197, 264, 315, 344, +346, 315, 246, 153, 63, -3, -47, -68, -61, -21, +38, 99, 146, 172, 180, 175, 161, 137, 115, 109, +115, 116, 97, 53, -7, -73, -135, -189, -232, -261, +-273, -272, -265, -255, -241, -217, -185, -155, -144, -155, +-177, -205, -234, -260, -271, -272, -267, -253, -222, -169, +-104, -37, 23, 81, 128, 158, 171, 181, 193, 201, +194, 184, 191, 229, 291, 359, 413, 449, 469, 474, +468, 458, 455, 456, 458, 445, 411, 364, 313, 269, +240, 226, 231, 256, 293, 330, 348, 338, 305, 261, +212, 159, 110, 71, 40, 16, 2, 5, 22, 43, +57, 61, 58, 44, 15, -21, -61, -103, -160, -228, +-294, -343, -378, -405, -438, -475, -506, -520, -514, -485, +-431, -357, -281, -220, -177, -144, -109, -67, -32, -15, +-24, -58, -110, -168, -221, -257, -263, -235, -181, -130, +-104, -103, -121, -153, -194, -234, -258, -263, -258, -250, +-243, -237, -236, -241, -247, -243, -232, -220, -206, -185, +-158, -138, -126, -114, -95, -72, -60, -77, -124, -186, +-242, -277, -288, -273, -235, -185, -140, -107, -88, -70, +-45, -9, 34, 81, 126, 169, 205, 231, 240, 246, +267, 312, 368, 419, 453, 470, 470, 454, 433, 425, +440, 472, 509, 543, 571, 582, 565, 524, 471, 417, +376, 363, 388, 440, 500, 538, 538, 503, 446, 372, +278, 167, 50, -53, -140, -199, -219, -193, -123, -34, +43, 84, 82, 44, -18, -95, -178, -263, -338, -395, +-434, -464, -488, -498, -486, -460, -429, -395, -356, -313, +-271, -239, -216, -193, -169, -146, -116, -75, -32, 0, +17, 22, 19, 12, 9, 18, 49, 98, 146, 175, +179, 169, 155, 134, 108, 82, 61, 44, 28, 8, +-11, -24, -31, -38, -48, -63, -80, -94, -99, -92, +-77, -54, -20, 16, 35, 25, -12, -62, -112, -157, +-196, -224, -240, -248, -255, -251, -232, -211, -200, -199, +-200, -196, -185, -167, -146, -121, -95, -70, -39, 16, +105, 209, 298, 349, 360, 335, 284, 221, 158, 105, +65, 34, 14, 7, 17, 41, 74, 106, 130, 142, +146, 151, 159, 166, 164, 153, 131, 95, 40, -28, +-97, -157, -208, -251, -276, -273, -253, -224, -190, -160, +-140, -140, -160, -193, -229, -259, -280, -290, -285, -269, +-257, -259, -269, -267, -243, -197, -132, -53, 30, 105, +161, 198, 222, 242, 259, 270, 278, 282, 284, 290, +302, 319, 333, 346, 366, 392, 418, 436, 445, 449, +444, 420, 377, 329, 292, 266, 255, 260, 276, 288, +288, 277, 260, 241, 214, 175, 127, 79, 43, 23, +22, 46, 87, 120, 123, 98, 60, 24, -3, -27, +-53, -84, -114, -141, -168, -194, -221, -254, -295, -341, +-384, -418, -432, -420, -386, -346, -305, -258, -198, -128, +-63, -11, 29, 52, 47, 11, -43, -106, -162, -200, +-210, -199, -183, -175, -178, -185, -189, -186, -183, -181, +-178, -178, -193, -225, -260, -284, -293, -298, -310, -331, +-352, -361, -354, -331, -288, -228, -160, -95, -47, -23, +-26, -55, -103, -164, -232, -288, -316, -307, -271, -229, +-193, -166, -148, -137, -119, -80, -19, 49, 114, 164, +199, 221, 239, 266, 305, 351, 389, 407, 406, 398, +390, 380, 373, 382, 408, 442, 475, 502, 521, 534, +535, 514, 473, 425, 389, 375, 384, 413, 448, 475, +485, 478, 455, 414, 354, 279, 187, 84, -15, -91, +-127, -120, -85, -33, 23, 63, 70, 43, -2, -53, +-103, -146, -185, -225, -271, -326, -384, -436, -465, -470, +-457, -432, -394, -349, -304, -260, -215, -171, -129, -99, +-84, -78, -72, -63, -58, -60, -63, -62, -53, -32, +0, 35, 66, 84, 89, 85, 80, 80, 92, 111, +122, 111, 85, 53, 20, -13, -41, -61, -79, -112, +-157, -200, -221, -205, -154, -83, -11, 45, 73, 66, +31, -16, -72, -133, -189, -230, -251, -256, -249, -239, +-224, -206, -194, -191, -191, -182, -162, -138, -118, -103, +-89, -69, -36, 14, 80, 149, 212, 261, 291, 299, +290, 279, 270, 251, 214, 162, 107, 59, 19, -5, +-8, 8, 39, 72, 98, 118, 134, 146, 151, 151, +146, 127, 84, 17, -63, -145, -219, -273, -297, -289, +-259, -223, -190, -161, -136, -130, -156, -208, -265, -305, +-317, -306, -285, -271, -274, -291, -310, -319, -311, -278, +-219, -146, -75, -17, 42, 114, 195, 270, 323, 347, +340, 311, 275, 247, 235, 244, 267, 296, 328, 360, +384, 398, 407, 415, 419, 415, 403, 389, 374, 355, +328, 294, 269, 262, 264, 261, 247, 226, 195, 152, +102, 58, 34, 34, 59, 100, 142, 166, 163, 140, +102, 56, 11, -22, -42, -58, -76, -97, -114, -127, +-137, -149, -167, -197, -238, -285, -330, -360, -366, -351, +-322, -277, -222, -166, -118, -76, -39, -12, 0, -4, +-22, -44, -68, -97, -132, -164, -190, -214, -238, -253, +-245, -213, -168, -128, -106, -108, -133, -165, -191, -210, +-230, -261, -305, -362, -421, -465, -478, -453, -399, -326, +-244, -163, -92, -44, -28, -47, -90, -145, -203, -258, +-295, -311, -312, -306, -294, -277, -257, -235, -209, -177, +-137, -91, -42, 11, 77, 151, 219, 271, 312, 342, +357, 352, 334, 318, 315, 324, 341, 359, 374, 386, +400, 421, 448, 475, 496, 510, 510, 494, 466, 436, +421, 422, 432, 443, 448, 452, 450, 433, 400, 352, +293, 226, 155, 93, 45, 15, 2, 3, 9, 9, +-2, -28, -61, -87, -105, -121, -141, -163, -189, -224, +-268, -311, -344, -366, -385, -402, -408, -391, -347, -281, +-203, -129, -71, -36, -20, -19, -28, -39, -44, -40, +-34, -30, -28, -22, -6, 7, 12, 8, 8, 19, +44, 80, 120, 154, 173, 179, 174, 158, 131, 93, +41, -20, -84, -149, -211, -260, -277, -259, -214, -153, +-80, -7, 43, 58, 38, -2, -53, -106, -158, -208, +-249, -281, -297, -295, -276, -247, -217, -191, -174, -165, +-157, -143, -120, -89, -58, -30, -1, 33, 75, 113, +148, 179, 206, 232, 259, 287, 308, 314, 297, 254, +192, 125, 60, 9, -15, -9, 12, 32, 46, 61, +81, 100, 112, 118, 116, 99, 61, 6, -55, -116, +-165, -201, -221, -227, -223, -210, -190, -172, -166, -181, +-216, -261, -300, -321, -321, -305, -285, -276, -280, -291, +-299, -307, -314, -313, -300, -275, -235, -175, -92, 14, +134, 245, 327, 374, 389, 373, 334, 290, 259, 249, +256, 275, 301, 324, 334, 330, 325, 333, 355, 380, +397, 401, 399, 393, 384, 372, 357, 338, 311, 278, +241, 202, 161, 122, 89, 66, 54, 59, 90, 140, +191, 220, 221, 196, 153, 105, 60, 18, -18, -54, +-86, -111, -118, -107, -88, -73, -65, -69, -94, -140, +-196, -241, -265, -268, -256, -227, -185, -138, -98, -69, +-47, -23, 1, 23, 38, 47, 48, 40, 16, -28, +-89, -154, -207, -235, -233, -212, -180, -145, -115, -101, +-104, -114, -126, -143, -169, -212, -278, -355, -429, -485, +-513, -506, -469, -412, -347, -280, -218, -178, -161, -160, +-165, -177, -208, -255, -303, -337, -355, -358, -351, -330, +-301, -275, -262, -258, -253, -232, -186, -118, -35, 50, +136, 216, 284, 333, 355, 355, 344, 335, 330, 333, +343, 351, 352, 344, 337, 338, 354, 391, 436, 476, +503, 513, 506, 489, 475, 464, 449, 428, 407, 392, +378, 358, 338, 323, 312, 296, 269, 231, 193, 156, +117, 74, 31, -3, -29, -51, -72, -90, -108, -121, +-129, -132, -136, -144, -156, -172, -198, -236, -285, -332, +-364, -370, -342, -280, -199, -119, -55, -20, -11, -18, +-31, -40, -39, -22, 1, 21, 27, 22, 10, -7, +-28, -42, -42, -28, -9, 15, 49, 96, 144, 178, +190, 186, 164, 125, 70, 3, -66, -136, -198, -246, +-272, -268, -236, -187, -132, -86, -58, -42, -33, -31, +-40, -62, -97, -146, -202, -253, -284, -287, -266, -233, +-210, -202, -208, -216, -220, -205, -166, -109, -53, -9, +22, 46, 61, 67, 70, 80, 107, 149, 197, 247, +294, 323, 324, 299, 258, 209, 155, 99, 49, 15, +3, 9, 25, 46, 67, 84, 95, 97, 83, 53, +15, -24, -61, -94, -117, -128, -128, -122, -118, -123, +-131, -139, -149, -167, -197, -233, -269, -302, -327, -333, +-321, -298, -276, -263, -263, -275, -297, -325, -344, -344, +-325, -286, -220, -120, 3, 129, 235, 305, 339, 344, +330, 309, 294, 290, 296, 303, 304, 293, 278, 273, +280, 296, 314, 329, 341, 353, 369, 386, 404, 418, +425, 412, 372, 314, 250, 192, 143, 104, 81, 72, +73, 84, 104, 130, 156, 174, 180, 178, 167, 143, +102, 53, 7, -30, -62, -84, -91, -82, -61, -40, +-26, -26, -37, -60, -89, -120, -148, -167, -169, -156, +-136, -122, -116, -114, -106, -87, -57, -23, 11, 39, +53, 52, 38, 15, -20, -70, -130, -180, -211, -219, +-204, -171, -129, -96, -83, -88, -102, -120, -148, -196, +-259, -327, -392, -447, -480, -485, -467, -434, -398, -362, +-325, -287, -251, -219, -197, -191, -205, -237, -275, -309, +-329, -333, -325, -313, -306, -311, -324, -334, -330, -307, +-265, -202, -124, -42, 33, 102, 168, 226, 271, 302, +325, 344, 358, 363, 361, 353, 340, 320, 300, 287, +290, 305, 331, 367, 412, 458, 494, 514, 518, 509, +486, 448, 401, 355, 314, 286, 277, 289, 317, 348, +372, 373, 347, 299, 237, 177, 125, 81, 38, -6, +-48, -85, -117, -139, -143, -132, -119, -113, -119, -134, +-158, -188, -226, -267, -301, -315, -305, -266, -206, -140, +-88, -57, -43, -37, -34, -27, -13, 6, 25, 32, +25, 12, 2, -3, -11, -24, -39, -51, -52, -37, +-5, 43, 100, 159, 207, 232, 225, 187, 131, 69, +10, -47, -101, -142, -166, -178, -183, -182, -176, -167, +-156, -144, -129, -109, -94, -94, -113, -146, -184, -221, +-243, -248, -242, -238, -243, -251, -255, -254, -244, -219, +-175, -110, -41, 13, 45, 57, 57, 57, 64, 79, +102, 132, 168, 208, 249, 286, 316, 337, 342, 323, +276, 214, 157, 119, 99, 94, 97, 103, 107, 104, +93, 72, 42, 3, -44, -91, -124, -137, -134, -119, +-99, -88, -93, -110, -126, -134, -143, -165, -204, -254, +-306, -351, -383, -392, -378, -350, -323, -305, -299, -306, +-320, -337, -353, -363, -361, -338, -290, -217, -127, -28, +70, 163, 243, 301, 337, 357, 369, 374, 370, 357, +337, 314, 293, 276, 269, 272, 279, 284, 290, 307, +332, 363, 397, 427, 442, 426, 379, 310, 237, 178, +136, 113, 104, 105, 107, 105, 103, 105, 115, 130, +146, 154, 149, 129, 95, 57, 22, -4, -27, -46, +-61, -75, -85, -85, -71, -47, -24, -12, -9, -10, +-7, -1, 3, 5, 0, -16, -38, -52, -49, -36, +-23, -13, -1, 12, 27, 41, 49, 46, 23, -19, +-73, -121, -151, -163, -158, -138, -111, -87, -77, -81, +-93, -114, -144, -186, -237, -292, -344, -388, -419, -438, +-450, -455, -455, -447, -431, -414, -395, -367, -334, -306, +-292, -294, -300, -301, -296, -291, -289, -292, -304, -323, +-339, -345, -334, -303, -255, -197, -140, -91, -48, -1, +60, 129, 195, 250, 296, 336, 366, 382, 387, 384, +370, 342, 302, 260, 229, 221, 240, 281, 334, 391, +445, 493, 529, 544, 527, 480, 410, 329, 247, 182, +148, 158, 207, 272, 329, 367, 381, 371, 343, 304, +253, 191, 119, 43, -23, -74, -104, -115, -112, -104, +-101, -107, -117, -124, -131, -148, -174, -200, -212, -209, +-193, -170, -143, -112, -83, -61, -44, -31, -16, 0, +20, 40, 54, 58, 55, 45, 31, 11, -12, -37, +-60, -81, -102, -113, -103, -65, -8, 53, 109, 145, +152, 130, 90, 44, 0, -39, -72, -98, -119, -138, +-155, -165, -163, -158, -158, -160, -157, -146, -134, -128, +-129, -139, -154, -174, -193, -206, -213, -223, -244, -277, +-307, -318, -301, -251, -180, -103, -37, 9, 38, 55, +69, 84, 103, 125, 140, 143, 141, 151, 177, 212, +249, 280, 299, 301, 282, 250, 217, 192, 179, 174, +174, 175, 169, 150, 121, 85, 39, -17, -73, -115, +-136, -139, -132, -122, -109, -95, -85, -81, -81, -82, +-90, -111, -148, -198, -253, -304, -343, -365, -367, -354, +-333, -313, -302, -304, -317, -330, -331, -322, -312, -303, +-292, -271, -236, -183, -113, -24, 71, 160, 232, 288, +331, 361, 375, 374, 361, 336, 304, 276, 259, 250, +243, 235, 236, 252, 286, 332, 381, 423, 444, 431, +381, 313, 245, 193, 162, 143, 127, 109, 89, 73, +67, 76, 95, 115, 130, 136, 126, 103, 78, 61, +53, 45, 30, 7, -23, -56, -88, -113, -121, -107, +-78, -41, 2, 46, 81, 101, 111, 114, 107, 88, +63, 42, 30, 26, 25, 26, 33, 47, 66, 86, +103, 107, 93, 59, 13, -33, -70, -88, -84, -64, +-38, -24, -30, -53, -87, -125, -164, -199, -230, -259, +-290, -322, -356, -384, -402, -409, -409, -407, -411, -425, +-441, -448, -442, -433, -423, -409, -386, -358, -335, -319, +-311, -313, -326, -350, -368, -367, -340, -297, -252, -212, +-184, -165, -144, -109, -55, 7, 71, 129, 183, 235, +283, 327, 366, 394, 400, 378, 334, 279, 226, 189, +176, 189, 229, 290, 363, 438, 499, 534, 532, 495, +434, 358, 276, 203, 158, 146, 158, 188, 232, 286, +340, 381, 395, 384, 355, 307, 236, 152, 70, 5, +-38, -63, -71, -73, -78, -91, -109, -122, -123, -112, +-98, -89, -86, -92, -102, -104, -92, -73, -52, -35, +-22, -13, -4, 6, 21, 38, 51, 55, 51, 43, +33, 18, 0, -17, -34, -57, -81, -94, -87, -63, +-30, 0, 22, 33, 29, 14, 1, 0, 0, -8, +-31, -62, -88, -101, -106, -109, -117, -130, -153, -183, +-211, -228, -232, -225, -209, -195, -187, -184, -184, -182, +-188, -205, -232, -258, -271, -270, -256, -227, -183, -131, +-81, -36, 3, 38, 68, 95, 122, 144, 156, 160, +160, 164, 174, 184, 195, 209, 226, 235, 233, 227, +230, 247, 271, 288, 288, 268, 233, 187, 138, 90, +47, 3, -40, -83, -122, -148, -157, -145, -121, -97, +-83, -80, -82, -86, -96, -118, -147, -184, -226, -270, +-309, -334, -346, -355, -364, -372, -377, -375, -360, -332, +-300, -272, -258, -257, -261, -263, -260, -246, -212, -157, +-88, -13, 61, 137, 213, 280, 331, 357, 359, 343, +314, 279, 248, 225, 212, 208, 215, 235, 264, 300, +337, 364, 372, 357, 323, 285, 251, 222, 194, 169, +151, 139, 129, 123, 122, 123, 122, 116, 105, 88, +64, 40, 26, 31, 53, 75, 85, 73, 40, -7, +-60, -100, -117, -110, -85, -49, -8, 36, 83, 126, +162, 187, 199, 194, 176, 156, 139, 127, 118, 109, +101, 96, 95, 92, 90, 86, 73, 51, 24, 2, +-12, -18, -12, 0, 7, -4, -35, -76, -115, -147, +-173, -196, -217, -236, -259, -285, -308, -324, -332, -334, +-336, -343, -362, -393, -429, -463, -486, -498, -496, -481, +-451, -414, -382, -364, -360, -365, -374, -381, -378, -361, +-328, -287, -245, -212, -190, -177, -165, -143, -109, -68, +-24, 25, 84, 144, 201, 258, 313, 362, 393, 396, +370, 323, 267, 215, 182, 180, 209, 258, 315, 370, +414, 442, 453, 446, 423, 380, 317, 246, 181, 140, +125, 131, 153, 187, 231, 279, 322, 350, 354, 331, +282, 219, 156, 105, 62, 28, 0, -32, -72, -115, +-145, -153, -145, -127, -105, -85, -68, -61, -62, -63, +-57, -45, -32, -18, -3, 8, 17, 31, 52, 77, +96, 102, 96, 83, 66, 46, 22, 1, -9, -8, +-2, 4, 7, 5, -4, -17, -29, -43, -55, -65, +-69, -66, -60, -56, -56, -53, -47, -43, -43, -45, +-52, -70, -105, -150, -197, -236, -258, -260, -242, -215, +-192, -180, -179, -183, -193, -209, -225, -235, -240, -243, +-242, -232, -206, -167, -121, -76, -35, 1, 36, 71, +107, 141, 167, 183, 191, 195, 197, 198, 195, 188, +178, 165, 158, 167, 200, 248, 291, 317, 319, 298, +257, 208, 162, 121, 82, 38, -10, -58, -98, -124, +-136, -132, -117, -100, -90, -85, -84, -88, -100, -115, +-129, -143, -159, -183, -215, -252, -290, -327, -360, -384, +-393, -386, -365, -332, -291, -248, -211, -188, -178, -179, +-188, -198, -202, -190, -161, -120, -66, 2, 78, 151, +216, 269, 303, 310, 290, 254, 217, 192, 186, 197, +221, 248, 268, 278, 283, 288, 288, 280, 264, 242, +218, 194, 173, 159, 151, 147, 146, 152, 164, 171, +167, 144, 108, 67, 31, 5, -3, 9, 38, 66, +80, 76, 56, 26, -7, -35, -54, -65, -69, -63, +-41, -5, 39, 89, 142, 190, 223, 236, 230, 220, +211, 201, 190, 179, 170, 158, 141, 117, 87, 58, +34, 23, 25, 34, 47, 58, 69, 76, 71, 47, +5, -43, -90, -132, -169, -197, -217, -230, -244, -262, +-278, -285, -284, -281, -282, -295, -327, -373, -419, -454, +-475, -486, -488, -481, -472, -465, -463, -461, -453, -441, +-429, -420, -407, -385, -354, -315, -274, -235, -206, -187, +-175, -165, -153, -138, -116, -81, -34, 19, 78, 143, +212, 275, 317, 327, 312, 283, 252, 226, 211, 208, +216, 229, 245, 266, 291, 314, 333, 347, 354, 345, +318, 276, 231, 190, 159, 142, 142, 162, 193, 226, +256, 283, 304, 315, 312, 299, 275, 240, 197, 150, +99, 46, -7, -53, -82, -94, -93, -84, -69, -50, +-30, -13, -3, 1, 4, 6, 10, 16, 26, 37, +48, 64, 90, 123, 151, 159, 145, 110, 63, 18, +-11, -16, -2, 20, 40, 53, 57, 52, 35, 11, +-17, -54, -95, -131, -149, -150, -140, -123, -102, -78, +-55, -36, -21, -13, -16, -37, -74, -121, -170, -212, +-241, -255, -256, -254, -255, -258, -260, -256, -251, -248, +-246, -242, -237, -235, -235, -228, -209, -183, -152, -120, +-87, -57, -31, -5, 26, 65, 106, 146, 183, 213, +225, 214, 186, 155, 130, 116, 117, 140, 182, 231, +277, 312, 331, 330, 309, 272, 226, 178, 130, 81, +33, -11, -50, -81, -100, -104, -97, -92, -95, -107, +-119, -128, -133, -130, -120, -109, -110, -127, -159, -198, +-240, -279, -312, -338, -358, -374, -383, -374, -345, -304, +-261, -224, -195, -181, -180, -185, -186, -183, -176, -163, +-136, -88, -19, 61, 139, 199, 233, 240, 229, 214, +204, 203, 210, 225, 244, 264, 276, 279, 275, 269, +261, 247, 228, 206, 180, 151, 127, 117, 125, 146, +171, 190, 199, 194, 177, 152, 125, 99, 70, 40, +20, 10, 8, 8, 9, 11, 10, 5, -2, -10, +-18, -26, -31, -34, -32, -21, 2, 42, 98, 160, +215, 252, 271, 281, 288, 297, 304, 309, 305, 284, +243, 190, 138, 97, 67, 53, 52, 60, 70, 81, +95, 108, 112, 96, 59, 7, -47, -101, -146, -177, +-193, -204, -216, -227, -234, -237, -240, -244, -254, -274, +-305, -338, -368, -390, -408, -426, -449, -475, -501, -523, +-534, -530, -511, -488, -469, -456, -440, -414, -381, -345, +-305, -263, -225, -198, -182, -173, -170, -168, -159, -134, +-94, -46, -1, 40, 84, 128, 167, 199, 226, 243, +248, 244, 240, 240, 242, 243, 242, 239, 234, 232, +238, 250, 261, 260, 246, 224, 203, 189, 180, 172, +165, 158, 150, 148, 157, 183, 221, 264, 300, 323, +328, 308, 269, 222, 175, 129, 79, 27, -16, -45, +-57, -54, -42, -23, -4, 8, 16, 23, 31, 36, +41, 45, 48, 54, 70, 100, 142, 179, 195, 188, +161, 119, 72, 29, 0, -10, -2, 16, 40, 65, +85, 97, 95, 78, 44, -6, -68, -126, -166, -185, +-188, -175, -147, -108, -67, -37, -20, -12, -9, -13, +-27, -49, -76, -105, -136, -169, -200, -231, -259, -280, +-294, -303, -307, -303, -285, -257, -233, -222, -219, -215, +-205, -188, -164, -137, -110, -87, -66, -40, -3, 43, +94, 142, 180, 199, 198, 179, 153, 129, 106, 85, +72, 80, 113, 160, 211, 258, 295, 317, 317, 298, +265, 228, 188, 143, 99, 61, 29, 5, -6, -11, +-18, -38, -68, -102, -133, -156, -164, -156, -137, -122, +-119, -130, -151, -179, -214, -253, -290, -323, -350, -372, +-385, -382, -367, -340, -307, -271, -236, -208, -192, -182, +-175, -167, -159, -149, -133, -105, -69, -26, 19, 64, +103, 126, 134, 139, 153, 178, 211, 244, 272, 288, +291, 285, 277, 267, 253, 233, 205, 172, 135, 104, +91, 102, 126, 151, 170, 179, 179, 172, 160, 148, +138, 127, 110, 84, 55, 30, 8, -11, -28, -41, +-48, -50, -46, -33, -19, -12, -17, -30, -39, -39, +-26, 0, 39, 89, 137, 180, 221, 264, 310, 353, +389, 411, 413, 391, 347, 291, 232, 179, 140, 121, +116, 119, 126, 138, 156, 172, 176, 162, 128, 77, +12, -59, -124, -170, -193, -197, -193, -185, -179, -181, +-193, -215, -243, -269, -292, -311, -322, -331, -342, -362, +-394, -432, -475, -519, -557, -575, -571, -555, -535, -519, +-503, -485, -462, -426, -378, -327, -282, -248, -221, -200, +-177, -150, -115, -80, -54, -42, -39, -32, -14, 12, +45, 83, 123, 159, 187, 210, 232, 252, 268, 273, +267, 252, 234, 216, 202, 192, 184, 177, 170, 171, +187, 211, 231, 237, 225, 194, 155, 120, 105, 115, +143, 179, 215, 245, 263, 265, 253, 231, 202, 166, +126, 86, 52, 22, -2, -20, -24, -16, -3, 11, +25, 37, 45, 51, 59, 74, 95, 118, 143, 171, +200, 222, 227, 215, 192, 163, 129, 96, 68, 52, +46, 48, 58, 76, 101, 124, 138, 135, 106, 48, +-26, -98, -153, -185, -194, -182, -154, -125, -104, -94, +-88, -77, -65, -54, -47, -48, -57, -75, -101, -131, +-164, -202, -243, -281, -311, -330, -335, -327, -307, -281, +-261, -251, -243, -230, -211, -192, -178, -164, -145, -120, +-89, -51, -5, 40, 81, 116, 143, 161, 169, 174, +177, 176, 165, 146, 129, 122, 129, 150, 181, 219, +256, 282, 289, 280, 257, 223, 182, 141, 111, 93, +81, 72, 62, 49, 25, -10, -51, -91, -123, -146, +-159, -159, -148, -135, -130, -137, -154, -175, -200, -226, +-251, -277, -307, -339, -361, -365, -351, -327, -302, -278, +-258, -239, -216, -185, -147, -111, -85, -70, -62, -58, +-55, -48, -33, -11, 10, 26, 42, 66, 96, 126, +157, 191, 224, 252, 269, 275, 275, 270, 255, 227, +192, 153, 120, 96, 88, 96, 110, 121, 128, 133, +137, 139, 140, 143, 151, 157, 151, 133, 104, 69, +29, -11, -46, -75, -93, -98, -86, -59, -27, 0, +19, 30, 33, 25, 10, -1, 2, 23, 58, 109, +175, 250, 321, 379, 421, 445, 448, 428, 389, 342, +295, 253, 217, 188, 170, 162, 162, 170, 186, 203, +211, 203, 174, 124, 58, -13, -74, -113, -133, -141, +-145, -147, -150, -158, -170, -186, -206, -228, -252, -269, +-277, -279, -287, -304, -332, -369, -416, -466, -507, -533, +-548, -557, -561, -556, -539, -512, -483, -453, -423, -394, +-367, -340, -307, -263, -210, -155, -103, -60, -35, -27, +-35, -49, -62, -68, -64, -45, -13, 26, 73, 124, +178, 228, 265, 288, 299, 295, 275, 240, 197, 155, +121, 98, 92, 106, 136, 170, 197, 213, 216, 201, +172, 135, 103, 85, 84, 98, 124, 154, 181, 200, +210, 213, 209, 194, 165, 129, 91, 58, 34, 22, +24, 35, 46, 53, 52, 49, 48, 54, 71, 97, +126, 154, 179, 202, 220, 227, 226, 221, 214, 201, +179, 152, 126, 104, 81, 63, 57, 69, 94, 124, +146, 150, 131, 87, 29, -30, -84, -126, -154, -169, +-174, -173, -169, -162, -149, -129, -108, -92, -79, -68, +-60, -59, -67, -84, -110, -144, -185, -227, -269, -306, +-333, -343, -332, -306, -280, -258, -240, -227, -218, -212, +-205, -189, -165, -133, -93, -44, 6, 50, 83, 101, +109, 110, 110, 115, 128, 144, 155, 157, 153, 150, +153, 162, 179, 203, 228, 243, 245, 232, 211, 188, +166, 151, 142, 134, 127, 121, 118, 115, 100, 70, +30, -11, -48, -81, -109, -128, -141, -150, -158, -164, +-168, -176, -191, -212, -233, -255, -272, -283, -285, -281, +-280, -287, -297, -305, -307, -299, -280, -246, -198, -144, +-95, -58, -36, -29, -37, -52, -67, -77, -81, -78, +-62, -34, 0, 37, 79, 128, 179, 222, 248, 257, +254, 241, 219, 192, 166, 140, 116, 97, 87, 84, +86, 87, 88, 89, 86, 81, 82, 91, 108, 124, +132, 129, 116, 94, 63, 25, -17, -63, -107, -138, +-147, -129, -90, -44, -2, 27, 38, 28, 6, -13, +-20, -10, 16, 61, 122, 192, 261, 322, 372, 407, +424, 424, 412, 392, 367, 336, 303, 276, 256, 245, +242, 247, 256, 260, 253, 234, 204, 163, 111, 55, +0, -43, -75, -96, -106, -109, -110, -115, -128, -147, +-168, -190, -212, -229, -242, -255, -270, -289, -309, -331, +-363, -406, -455, -500, -534, -554, -557, -548, -532, -516, +-502, -488, -473, -460, -445, -422, -382, -327, -260, -188, +-116, -52, -8, 9, 2, -21, -53, -83, -103, -105, +-90, -62, -26, 18, 74, 138, 200, 248, 275, 281, +264, 230, 190, 151, 116, 87, 70, 66, 76, 97, +127, 159, 184, 193, 185, 161, 132, 104, 83, 73, +74, 84, 95, 106, 119, 133, 144, 147, 142, 134, +123, 110, 99, 93, 91, 89, 82, 71, 61, 55, +57, 71, 97, 132, 168, 199, 221, 233, 235, 229, +218, 208, 203, 199, 193, 182, 167, 152, 138, 128, +125, 124, 122, 118, 113, 106, 93, 70, 41, 10, +-22, -59, -95, -124, -143, -157, -171, -181, -185, -178, +-164, -143, -120, -98, -84, -78, -78, -84, -98, -122, +-159, -203, -248, -288, -316, -326, -317, -297, -277, -262, +-251, -244, -241, -241, -236, -221, -190, -147, -95, -41, +9, 51, 80, 100, 105, 100, 89, 85, 91, 103, +117, 129, 143, 158, 173, 183, 193, 204, 214, 220, +217, 204, 184, 162, 144, 133, 129, 126, 122, 115, +108, 100, 94, 91, 89, 79, 55, 15, -33, -76, +-107, -130, -149, -167, -182, -198, -212, -224, -232, -236, +-236, -233, -229, -229, -234, -247, -263, -277, -291, -298, +-293, -266, -219, -159, -99, -46, -9, 5, 0, -16, +-36, -55, -72, -85, -90, -83, -61, -25, 22, 74, +121, 159, 184, 195, 194, 185, 170, 157, 147, 136, +123, 107, 95, 87, 77, 65, 54, 49, 49, 52, +58, 68, 81, 94, 104, 111, 115, 113, 100, 74, +38, -8, -58, -104, -132, -138, -122, -89, -47, -7, +16, 16, 3, -8, -11, 1, 29, 70, 120, 172, +222, 265, 305, 340, 372, 397, 411, 411, 399, 381, +364, 352, 342, 330, 317, 306, 296, 283, 265, 242, +215, 183, 143, 97, 54, 21, -2, -22, -42, -63, +-85, -104, -115, -120, -125, -138, -158, -184, -213, -243, +-271, -293, -307, -318, -338, -371, -414, -457, -491, -509, +-512, -502, -488, -479, -479, -487, -497, -504, -503, -487, +-453, -402, -337, -260, -176, -98, -38, -3, 5, -6, +-33, -68, -101, -124, -131, -119, -89, -42, 16, 78, +135, 180, 209, 220, 215, 198, 177, 155, 134, 111, +87, 65, 50, 42, 47, 64, 89, 113, 127, 129, +119, 100, 80, 64, 57, 56, 56, 56, 55, 59, +67, 77, 88, 100, 111, 122, 132, 140, 144, 141, +128, 108, 87, 71, 68, 82, 116, 159, 202, 232, +249, 256, 255, 251, 246, 243, 240, 235, 230, 226, +226, 231, 238, 242, 238, 221, 193, 159, 124, 95, +74, 58, 45, 31, 14, -8, -36, -64, -89, -111, +-132, -150, -163, -173, -180, -180, -172, -155, -134, -117, +-105, -99, -102, -115, -139, -173, -213, -253, -283, -295, +-289, -276, -265, -259, -257, -260, -264, -264, -254, -232, +-198, -158, -110, -58, -6, 43, 83, 109, 116, 107, +86, 64, 52, 53, 71, 99, 131, 158, 174, 182, +190, 199, 205, 202, 187, 168, 149, 134, 125, 117, +109, 97, 83, 74, 75, 86, 101, 116, 125, 119, +96, 59, 17, -21, -56, -89, -121, -153, -183, -209, +-227, -233, -227, -217, -204, -193, -187, -185, -189, -199, +-212, -228, -245, -259, -264, -253, -225, -185, -137, -88, +-43, -14, -4, -11, -29, -53, -80, -102, -113, -109, +-91, -60, -16, 34, 80, 112, 127, 130, 124, 118, +113, 112, 113, 111, 106, 99, 88, 74, 59, 49, +45, 45, 43, 38, 35, 40, 51, 63, 72, 78, +83, 87, 87, 77, 57, 25, -11, -50, -82, -104, +-110, -99, -73, -46, -29, -24, -24, -21, -8, 13, +41, 77, 119, 160, 196, 230, 266, 303, 335, 355, +362, 362, 363, 374, 391, 409, 419, 423, 419, 406, +382, 348, 310, 274, 244, 216, 188, 160, 135, 111, +83, 47, 8, -26, -50, -65, -72, -74, -77, -84, +-99, -121, -150, -182, -211, -237, -261, -288, -322, -359, +-398, -430, -453, -463, -460, -451, -445, -452, -470, -487, +-497, -498, -494, -483, -463, -431, -384, -322, -246, -164, +-88, -32, -1, 1, -16, -45, -77, -107, -125, -124, +-100, -60, -11, 34, 72, 100, 120, 131, 133, 131, +129, 123, 115, 103, 88, 72, 54, 35, 23, 26, +41, 60, 77, 89, 94, 95, 93, 87, 78, 65, +43, 14, -9, -21, -19, -2, 19, 45, 73, 98, +121, 138, 150, 151, 140, 118, 97, 86, 92, 114, +145, 181, 217, 250, 277, 296, 300, 293, 277, 256, +234, 212, 169, 126, 130, 182, 252, 305, 331, 333, +311, 262, 192, 107, 33, -6, -6, 12, 31, 53, +57, 29, -37, -138, -214, -222, -176, -115, -64, -30, +-30, -42, -46, -72, -125, -190, -262, -311, -323, -321, +-307, -249, -156, -101, -109, -147, -180, -215, -291, -411, +-508, -538, -509, -416, -262, -79, 89, 217, 298, 318, +272, 186, 60, -97, -233, -313, -293, -143, 60, 220, +341, 449, 525, 540, 457, 267, 41, -140, -255, -284, +-202, -46, 116, 233, 286, 323, 369, 380, 302, 127, +-80, -246, -320, -280, -140, 45, 200, 288, 321, 308, +247, 121, -79, -306, -514, -648, -639, -481, -251, -60, +42, 94, 139, 161, 103, -48, -239, -424, -566, -600, +-484, -247, 8, 188, 277, 309, 295, 207, 36, -168, +-352, -489, -551, -495, -314, -72, 138, 266, 316, 321, +286, 206, 83, -76, -245, -362, -367, -237, -8, 226, +383, 456, 470, 425, 316, 167, -5, -187, -342, -407, +-343, -171, 43, 221, 347, 419, 427, 364, 224, 33, +-179, -389, -539, -569, -457, -252, -36, 141, 269, 347, +358, 299, 188, 31, -164, -353, -463, -429, -244, 33, +319, 547, 692, 747, 715, 617, 463, 266, 64, -84, +-107, 19, 244, 476, 659, 781, 835, 807, 717, 575, +372, 133, -105, -283, -336, -267, -128, 24, 166, 274, +311, 286, 218, 112, -41, -244, -444, -554, -530, -410, +-264, -135, -42, 12, 31, 7, -67, -207, -409, -626, +-788, -838, -776, -648, -485, -325, -206, -149, -144, -169, +-228, -340, -508, -654, -684, -571, -376, -169, 7, 135, +214, 245, 230, 166, 45, -121, -286, -388, -392, -304, +-153, 37, 228, 366, 429, 429, 384, 289, 117, -117, +-328, -428, -392, -256, -72, 117, 287, 419, 489, 479, +394, 235, 10, -221, -398, -478, -450, -328, -140, 60, +230, 338, 390, 393, 322, 158, -62, -258, -361, -349, +-243, -77, 106, 272, 397, 485, 549, 565, 491, 325, +134, -13, -86, -74, 9, 139, 290, 420, 513, 590, +642, 615, 467, 240, 19, -124, -166, -124, -27, 102, +228, 311, 344, 335, 277, 149, -38, -235, -389, -459, +-431, -329, -189, -58, 30, 87, 131, 136, 62, -92, +-292, -473, -576, -582, -494, -337, -158, -22, 49, 88, +95, 42, -83, -260, -438, -563, -609, -571, -454, -284, +-113, 25, 147, 260, 329, 308, 183, 1, -170, -283, +-311, -245, -88, 110, 291, 430, 529, 574, 539, 417, +232, 38, -108, -190, -190, -104, 31, 166, 278, 370, +435, 442, 360, 198, 8, -145, -231, -237, -157, -18, +125, 232, 300, 334, 323, 247, 101, -92, -284, -436, +-518, -509, -416, -294, -185, -94, -4, 78, 111, 64, +-57, -212, -361, -473, -509, -442, -296, -130, 18, 150, +266, 339, 326, 215, 44, -134, -287, -381, -387, -306, +-176, -33, 104, 235, 342, 381, 325, 191, 19, -150, +-280, -328, -285, -181, -54, 74, 202, 320, 386, 356, +238, 76, -91, -232, -313, -318, -262, -176, -80, 28, +155, 271, 326, 291, 186, 33, -140, -291, -374, -376, +-318, -231, -130, -1, 143, 257, 289, 242, 135, 2, +-109, -163, -147, -77, 15, 115, 234, 374, 498, 555, +539, 461, 339, 208, 119, 103, 157, 243, 324, 399, +487, 575, 617, 586, 482, 322, 133, -37, -147, -178, +-152, -105, -48, 32, 132, 212, 238, 203, 107, -41, +-213, -361, -446, -459, -422, -361, -270, -152, -47, 1, +-20, -113, -264, -442, -600, -695, -712, -673, -607, -509, +-372, -227, -122, -83, -112, -195, -314, -435, -516, -525, +-474, -394, -293, -154, 11, 165, 272, 308, 262, 145, +-10, -155, -237, -249, -219, -162, -61, 85, 244, 372, +439, 431, 345, 195, 19, -125, -203, -226, -212, -153, +-37, 118, 274, 388, 429, 381, 243, 48, -142, -274, +-341, -363, -341, -257, -117, 48, 194, 284, 299, 230, +91, -67, -183, -232, -230, -185, -87, 61, 246, 428, +569, 640, 622, 515, 350, 196, 95, 41, 24, 54, +138, 271, 419, 551, 635, 653, 584, 440, 275, 143, +49, -15, -48, -31, 39, 145, 253, 328, 352, 302, +172, 4, -143, -249, -319, -353, -333, -250, -114, 35, +155, 220, 199, 73, -116, -303, -437, -513, -541, -521, +-447, -316, -160, -17, 85, 122, 62, -84, -261, -408, +-504, -551, -548, -484, -352, -175, 8, 171, 286, 316, +245, 111, -25, -133, -201, -232, -218, -143, -9, 147, +298, 420, 474, 434, 316, 172, 43, -57, -140, -195, +-198, -135, -25, 104, 229, 311, 308, 218, 84, -43, +-134, -187, -213, -202, -142, -47, 62, 173, 260, 276, +201, 63, -91, -224, -328, -413, -465, -460, -399, -298, +-169, -34, 62, 86, 35, -57, -151, -225, -283, -321, +-318, -261, -163, -32, 113, 233, 281, 243, 144, 30, +-71, -157, -230, -270, -255, -189, -76, 70, 219, 314, +323, 247, 126, 4, -106, -205, -274, -293, -264, -189, +-66, 86, 223, 292, 276, 202, 112, 28, -61, -145, +-205, -227, -210, -147, -38, 91, 199, 245, 219, 153, +72, -19, -114, -194, -241, -248, -204, -105, 27, 147, +215, 221, 194, 160, 118, 64, 7, -34, -52, -31, +44, 175, 328, 445, 486, 469, 426, 380, 327, 277, +241, 220, 223, 263, 350, 470, 571, 599, 552, 461, +355, 242, 131, 33, -46, -101, -119, -86, 7, 130, +225, 255, 229, 166, 70, -44, -158, -260, -336, -375, +-360, -281, -166, -68, -35, -60, -119, -201, -301, -405, +-499, -574, -619, -615, -544, -408, -254, -148, -110, -124, +-169, -230, -296, -360, -413, -453, -461, -407, -276, -97, +63, 161, 194, 169, 104, 18, -69, -144, -202, -245, +-254, -193, -68, 70, 173, 225, 226, 183, 105, 11, +-83, -160, -213, -229, -178, -54, 100, 225, 291, 294, +248, 165, 60, -53, -158, -251, -322, -337, -266, -131, +15, 126, 184, 189, 153, 90, 16, -53, -117, -173, +-189, -125, 19, 202, 366, 478, 526, 517, 459, 371, +283, 203, 122, 53, 37, 98, 218, 350, 456, 519, +539, 516, 456, 376, 289, 189, 82, 2, -11, 40, +123, 195, 233, 233, 194, 123, 38, -40, -118, -202, +-271, -287, -236, -142, -52, 2, 14, -14, -77, -153, +-223, -290, -369, -451, -496, -473, -384, -267, -163, -93, +-69, -94, -153, -214, -260, -308, -363, -400, -383, -297, +-166, -31, 79, 151, 172, 148, 103, 61, 12, -47, +-104, -121, -71, 33, 156, 265, 338, 361, 327, 260, +190, 120, 35, -62, -139, -156, -105, -14, 83, 161, +199, 187, 143, 97, 60, 16, -47, -114, -150, -129, +-59, 31, 122, 188, 200, 159, 90, 19, -55, -148, +-254, -343, -375, -344, -272, -178, -85, -20, 4, 3, +-2, -16, -53, -117, -182, -211, -184, -114, -20, 81, +162, 197, 192, 169, 138, 90, 8, -94, -173, -190, +-145, -56, 49, 142, 187, 182, 151, 113, 62, -20, +-137, -255, -330, -338, -279, -171, -39, 74, 140, 163, +162, 147, 104, 13, -106, -213, -274, -274, -212, -105, +5, 82, 114, 117, 105, 73, 5, -91, -185, -242, +-254, -216, -135, -31, 60, 121, 155, 182, 197, 175, +109, 23, -44, -72, -45, 36, 153, 268, 351, 400, +432, 452, 447, 403, 330, 258, 213, 211, 258, 341, +432, 494, 514, 505, 481, 439, 354, 232, 101, -8, +-76, -83, -28, 65, 155, 211, 229, 224, 194, 121, +8, -119, -233, -307, -327, -288, -208, -124, -72, -62, +-77, -102, -152, -246, -369, -492, -585, -623, -589, -492, +-364, -247, -165, -117, -93, -98, -146, -234, -340, -435, +-492, -485, -405, -271, -128, -18, 52, 98, 122, 109, +52, -38, -144, -243, -305, -311, -254, -164, -77, -10, +43, 85, 97, 66, 0, -84, -165, -221, -233, -182, +-84, 16, 89, 136, 169, 185, 166, 106, 9, -108, +-221, -294, -302, -248, -163, -79, -14, 41, 84, 104, +93, 49, -13, -84, -137, -140, -72, 46, 173, 278, +359, 416, 447, 445, 411, 350, 265, 169, 97, 84, +134, 216, 304, 391, 470, 527, 546, 520, 455, 362, +251, 141, 65, 44, 63, 95, 126, 154, 176, 183, +167, 126, 61, -25, -118, -187, -208, -192, -158, -122, +-83, -42, -16, -19, -54, -117, -206, -312, -405, -448, +-434, -382, -321, -259, -197, -141, -102, -85, -93, -125, +-185, -252, -290, -280, -231, -167, -96, -20, 53, 111, +143, 146, 121, 65, -10, -70, -79, -34, 40, 123, +201, 266, 311, 328, 316, 274, 197, 85, -31, -112, +-141, -125, -82, -19, 54, 127, 185, 220, 228, 200, +124, 13, -90, -147, -147, -103, -33, 47, 120, 166, +180, 168, 129, 53, -59, -179, -274, -330, -349, -335, +-284, -201, -106, -21, 46, 89, 92, 47, -31, -108, +-151, -152, -121, -63, 9, 87, 152, 198, 222, 210, +150, 56, -36, -100, -126, -120, -89, -36, 26, 80, +119, 139, 131, 78, -27, -160, -274, -338, -345, -304, +-223, -118, -11, 77, 145, 180, 166, 93, -21, -139, +-225, -264, -262, -221, -154, -79, -13, 43, 91, 112, +88, 14, -88, -183, -241, -256, -226, -156, -63, 31, +119, 198, 254, 261, 209, 115, 20, -45, -70, -53, +1, 79, 164, 245, 324, 400, 455, 462, 411, 327, +245, 191, 175, 200, 257, 322, 378, 422, 453, 459, +422, 334, 219, 106, 19, -29, -36, -5, 43, 91, +133, 170, 196, 193, 138, 35, -87, -196, -268, -296, +-279, -233, -182, -138, -102, -75, -74, -119, -210, -322, +-424, -494, -518, -488, -416, -326, -239, -164, -96, -47, +-42, -95, -193, -302, -394, -446, -444, -389, -296, -192, +-86, 19, 114, 172, 167, 101, 0, -108, -198, -250, +-262, -238, -194, -142, -82, -13, 51, 83, 64, 5, +-69, -134, -172, -172, -139, -91, -40, 16, 85, 155, +192, 172, 99, -5, -117, -212, -267, -277, -256, -223, +-184, -129, -52, 24, 70, 70, 31, -23, -70, -86, +-58, 2, 77, 153, 234, 328, 420, 482, 493, 452, +375, 288, 220, 189, 198, 235, 274, 313, 366, 436, +501, 532, 516, 452, 357, 255, 173, 123, 101, 88, +78, 85, 119, 166, 203, 210, 178, 109, 21, -63, +-122, -148, -155, -154, -145, -116, -70, -24, -1, -15, +-69, -152, -245, -318, -359, -371, -368, -349, -304, -235, +-158, -96, -63, -62, -88, -132, -176, -199, -197, -185, +-166, -133, -76, -1, 67, 109, 113, 84, 35, -11, +-33, -23, 3, 36, 76, 133, 202, 265, 302, 297, +247, 159, 53, -44, -109, -141, -150, -139, -101, -33, +52, 130, 173, 167, 114, 27, -63, -129, -159, -165, +-151, -118, -60, 14, 89, 140, 154, 122, 43, -61, +-164, -244, -301, -336, -344, -312, -236, -129, -21, 63, +104, 90, 35, -28, -71, -90, -92, -83, -57, -10, +57, 131, 196, 234, 231, 181, 103, 25, -31, -63, +-77, -74, -49, -2, 53, 100, 122, 103, 35, -67, +-174, -258, -308, -322, -302, -245, -159, -62, 25, 87, +110, 86, 23, -55, -122, -166, -191, -207, -208, -186, +-139, -79, -16, 28, 35, -1, -65, -130, -177, -199, +-203, -184, -138, -67, 17, 104, 178, 219, 213, 169, +109, 64, 40, 32, 31, 44, 77, 133, 206, 290, +363, 404, 404, 371, 331, 298, 272, 255, 252, 267, +299, 336, 372, 395, 390, 351, 287, 225, 183, 160, +141, 121, 107, 107, 123, 156, 191, 202, 173, 104, +21, -46, -87, -109, -120, -124, -123, -115, -99, -76, +-59, -72, -125, -209, -291, -344, -362, -355, -333, -300, +-259, -210, -152, -93, -53, -55, -101, -172, -243, -300, +-335, -342, -319, -270, -203, -122, -35, 39, 79, 71, +27, -26, -75, -115, -152, -187, -213, -227, -218, -182, +-127, -74, -47, -47, -62, -79, -93, -105, -113, -118, +-114, -95, -58, -2, 57, 93, 90, 53, 3, -45, +-88, -129, -166, -198, -218, -217, -185, -126, -67, -23, +-3, 0, -5, -14, -19, -15, 4, 43, 96, 163, +241, 312, 355, 367, 356, 340, 326, 313, 295, 275, +261, 262, 291, 347, 412, 460, 474, 459, 425, 382, +332, 276, 216, 159, 110, 83, 92, 134, 183, 208, +196, 156, 106, 56, 9, -39, -90, -140, -179, -185, +-154, -104, -58, -39, -52, -94, -155, -227, -295, -353, +-397, -424, -421, -378, -301, -217, -155, -123, -115, -120, +-133, -149, -167, -185, -201, -202, -172, -111, -36, 23, +55, 61, 53, 39, 27, 22, 25, 27, 34, 58, +110, 181, 247, 281, 268, 215, 136, 53, -18, -74, +-118, -146, -145, -107, -39, 35, 95, 126, 124, 88, +24, -46, -106, -150, -181, -192, -168, -104, -16, 64, +114, 125, 100, 45, -29, -112, -195, -268, -319, -329, +-285, -196, -91, -1, 59, 87, 85, 64, 35, 7, +-21, -52, -74, -65, -14, 68, 154, 219, 250, 246, +214, 164, 107, 46, -15, -67, -95, -83, -37, 22, +74, 99, 86, 35, -40, -119, -188, -245, -284, -297, +-273, -210, -128, -50, 6, 34, 34, 9, -30, -78, +-134, -192, -243, -265, -245, -191, -125, -66, -28, -21, +-43, -77, -107, -127, -144, -157, -159, -130, -68, 15, +102, 175, 220, 235, 225, 198, 164, 124, 80, 42, +28, 52, 111, 193, 281, 356, 400, 409, 391, 360, +324, 286, 248, 222, 220, 244, 282, 322, 353, 368, +363, 343, 311, 273, 226, 171, 127, 107, 113, 137, +166, 189, 190, 164, 120, 74, 35, 0, -40, -86, +-123, -138, -131, -109, -85, -70, -77, -106, -147, -188, +-223, -258, -292, -314, -312, -282, -230, -164, -100, -61, +-56, -84, -129, -177, -227, -278, -319, -332, -309, -257, +-187, -109, -37, 14, 36, 37, 25, -7, -70, -158, +1296, 1643, 2051, 2479, 2833, 3135, 3304, 3301, 3194, 3036, +2895, 2752, 2630, 2571, 2555, 2571, 2601, 2596, 2546, 2396, +2101, 1640, 1067, 443, -225, -921, -1622, -2259, -2818, -3270, +-3610, -3816, -3900, -3905, -3877, -3830, -3751, -3657, -3595, -3548, +-3494, -3406, -3279, -3138, -2948, -2701, -2421, -2145, -1856, -1499, +-1084, -630, -182, 242, 657, 1029, 1325, 1551, 1711, 1819, +1825, 1723, 1579, 1432, 1311, 1214, 1147, 1147, 1205, 1286, +1356, 1403, 1423, 1394, 1284, 1113, 940, 765, 574, 350, +108, -117, -333, -525, -685, -785, -826, -833, -820, -789, +-718, -626, -540, -492, -453, -422, -413, -455, -534, -641, +-747, -837, -907, -911, -849, -720, -558, -387, -212, -32, +137, 267, 383, 477, 487, 422, 370, 375, 417, 479, +545, 616, 667, 687, 677, 666, 646, 571, 438, 276, +126, -9, -148, -272, -345, -374, -395, -414, -412, -332, +-193, -85, -18, 56, 119, 174, 213, 309, 550, 907, +1378, 1974, 2622, 3233, 3621, 3695, 3564, 3329, 3041, 2742, +2521, 2493, 2614, 2803, 3048, 3352, 3689, 3899, 3887, 3655, +3186, 2496, 1553, 528, -392, -1210, -1950, -2666, -3227, -3575, +-3812, -3955, -4040, -4025, -3943, -3972, -4106, -4294, -4472, -4637, +-4842, -4948, -4900, -4798, -4690, -4562, -4351, -4014, -3560, -3009, +-2343, -1586, -899, -346, 166, 666, 1019, 1083, 943, 798, +704, 592, 438, 402, 536, 812, 1092, 1329, 1545, 1690, +1707, 1484, 1139, 739, 288, -126, -499, -785, -976, -1092, +-1115, -979, -684, -289, 77, 383, 666, 862, 927, 865, +708, 526, 338, 102, -188, -367, -397, -316, -102, 262, +740, 1173, 1464, 1581, 1710, 1826, 1696, 1325, 861, 471, +244, 92, -23, -25, 75, 168, 177, 116, -7, -277, +-708, -1117, -1228, -878, -39, 1396, 3500, 6064, 8761, 11318, +13568, 15299, 16101, 15684, 14162, 11970, 9327, 6305, 3135, 172, +-2252, -4087, -5504, -6460, -6810, -6756, -6649, -6648, -6631, -6488, +-6508, -6904, -7498, -7936, -8118, -8228, -8248, -7831, -6715, -5170, +-3480, -1660, 352, 2244, 3517, 4016, 3888, 3287, 2012, 51, +-2101, -3863, -5060, -5892, -6240, -5814, -4610, -2981, -1335, 222, +1553, 2384, 2456, 1853, 875, -270, -1525, -2725, -3401, -3346, +-2634, -1590, -404, 869, 1990, 2659, 2657, 2047, 950, -581, +-2320, -3791, -4615, -4602, -3896, -2702, -1006, 1070, 3135, 4806, +5991, 6655, 6756, 6194, 5048, 3742, 2572, 1622, 833, 310, +240, 556, 1038, 1435, 1720, 1898, 1744, 1100, 94, -1013, +-2020, -2914, -3524, -3540, -2827, -1649, -465, 561, 1502, 2273, +2650, 2364, 1405, 79, -1375, -2784, -3916, -4517, -4518, -3944, +-2889, -1494, 72, 1555, 2774, 3642, 4135, 4092, 3402, 2229, +889, -195, -794, -830, -442, 142, 789, 1457, 2238, 2885, +3082, 2751, 1915, 777, -396, -1271, -1678, -1737, -1703, -1665, +-1275, -289, 975, 1895, 2245, 2410, 3010, 4493, 6998, 10421, +14004, 16521, 17008, 15522, 12989, 10076, 6692, 2641, -1845, -6066, +-9397, -11633, -12618, -12272, -10866, -9147, -7824, -6935, -6261, -5802, +-5776, -6195, -6604, -6716, -6597, -6425, -5956, -4703, -2764, -748, +656, 1392, 1575, 1066, -332, -2444, -4623, -6503, -7967, -8853, +-8779, -7474, -5325, -2943, -719, 1253, 2899, 3863, 4050, 3636, +2805, 1609, 323, -296, 122, 1142, 1914, 2204, 2591, 3351, +4023, 3997, 3243, 2097, 698, -1017, -2841, -4034, -4147, -3313, +-1855, 22, 2207, 4165, 5391, 5915, 6048, 5765, 4674, 2790, +772, -605, -1230, -1461, -1416, -763, 449, 1677, 2496, 2940, +3306, 3486, 3174, 2327, 1333, 528, -101, -725, -1224, -1257, +-767, -15, 697, 1233, 1494, 1410, 1008, 439, -25, -412, +-815, -1185, -1487, -1738, -2216, -3036, -3928, -4572, -4951, -5259, +-5474, -5202, -4046, -2233, -218, 1952, 4749, 8530, 12925, 17203, +20727, 23187, 24160, 22777, 18611, 12443, 5685, -603, -6213, -11037, +-14636, -16530, -16708, -15668, -13861, -11556, -8999, -6924, -5834, -5459, +-5282, -5050, -4791, -4306, -3189, -1335, 693, 2391, 3922, 5361, +6281, 5892, 3877, 899, -2368, -5729, -8936, -11265, -11930, -10784, +-8530, -5696, -2269, 1515, 4898, 7031, 7686, 7244, 6086, 4157, +1733, -462, -1912, -2556, -2689, -2339, -1349, -85, 706, 705, +-25, -1236, -2743, -4614, -6395, -7582, -7890, -7141, -5170, -1770, +2677, 7024, 10224, 12019, 12705, 12464, 11158, 8746, 5827, 3069, +720, -1233, -2609, -3053, -2620, -1732, -931, -288, 260, 482, +216, -379, -835, -887, -764, -644, -365, 281, 1034, 1323, +948, 165, -729, -1744, -2877, -3906, -4537, -4654, -4425, -3799, +-2647, -1220, -33, 533, 702, 866, 1106, 1174, 1053, 1010, +1237, 1615, 1887, 2075, 2254, 2446, 2444, 2041, 1516, 1113, +900, 771, 538, 234, -109, -562, -1311, -2431, -3845, -5363, +-6720, -7595, -7761, -7300, -6305, -4649, -1826, 2506, 7972, 13647, +18835, 23319, 26393, 26816, 23769, 17736, 10443, 3412, -2829, -8290, +-12484, -14702, -14936, -13794, -11897, -9439, -6870, -5176, -5016, -6118, +-7499, -8411, -8759, -8502, -7120, -4319, -698, 2738, 5403, 7344, +8364, 7859, 5398, 1308, -3456, -8180, -12220, -14902, -15405, -13447, +-9750, -5248, -458, 4374, 8489, 10807, 10916, 9391, 7051, 4297, +1381, -1032, -2140, -1863, -819, 427, 1923, 3618, 4747, 4429, +2631, 176, -2435, -5163, -7556, -8330, -6525, -3066, 134, 2323, +4242, 6554, 8595, 9270, 8425, 6640, 4265, 1269, -1950, -4042, +-4239, -3136, -1771, -576, 887, 2621, 3882, 4178, 3820, 3203, +2188, 643, -1086, -2200, -2397, -2237, -2025, -1693, -1309, -1178, +-1599, -2355, -2889, -3091, -3387, -3883, -4204, -3994, -3311, -2536, +-1881, -1213, -527, -19, 173, 113, 100, 185, 93, -256, +-582, -610, -200, 469, 1088, 1702, 2401, 2905, 2772, 1850, +398, -863, -1663, -2317, -2831, -3103, -2931, -1907, 257, 3865, +8927, 14578, 19663, 23387, 25174, 24542, 20981, 14556, 6854, -98, +-5465, -9498, -12560, -14442, -14519, -12938, -10737, -8633, -6887, -5757, +-5679, -6711, -8064, -8651, -8125, -6763, -4649, -1717, 1759, 4920, +6824, 7414, 7129, 5794, 2932, -1317, -5844, -9342, -11405, -12174, +-11422, -8793, -4837, -779, 2337, 4241, 5168, 5036, 3680, 1509, +-622, -2063, -2747, -2788, -1952, -145, 1997, 3745, 4863, 5302, +4878, 3246, 407, -2809, -5345, -6894, -7625, -7501, -6248, -3699, +-275, 3294, 6704, 9783, 11862, 12318, 10912, 8042, 4763, 1715, +-892, -2804, -3791, -3947, -3663, -3380, -3121, -2518, -1692, -1066, +-788, -647, -200, 799, 1973, 3035, 3942, 4524, 4539, 3697, +2162, 493, -962, -2184, -3060, -3504, -3563, -3266, -2901, -2564, +-2076, -1462, -680, 288, 1196, 1675, 1559, 876, 132, -249, +-546, -928, -1302, -1459, -1248, -884, -649, -520, -489, -807, +-1363, -1781, -1742, -1133, -650, -806, -1335, -1954, -2460, -3107, +-3995, -4550, -4412, -3538, -2107, 135, 3793, 8734, 14181, 19147, +22969, 24977, 24234, 20224, 13588, 6332, 98, -4776, -8613, -11448, +-12766, -12508, -11140, -9221, -7094, -5169, -4269, -4927, -6627, -8160, +-8663, -7981, -6201, -3296, 419, 4044, 6704, 8074, 8494, 8040, +6204, 2821, -1483, -5690, -9127, -11388, -12121, -10900, -7753, -3705, +131, 3124, 5096, 5917, 5469, 4053, 2411, 1112, 109, -546, +-597, 260, 1912, 3598, 4624, 4745, 3838, 1811, -1266, -4770, +-7731, -9607, -10326, -10067, -8751, -5958, -1645, 3439, 7835, 10077, +9768, 7520, 4588, 2064, 197, -1198, -2384, -3322, -3745, -3417, +-2347, -920, 316, 1046, 1057, 408, -536, -1347, -1484, -739, +664, 2349, 3745, 4488, 4547, 4077, 3277, 2226, 1027, -176, +-1262, -2185, -2981, -3441, -3406, -2766, -1791, -965, -316, 189, +604, 830, 812, 870, 1086, 1082, 652, -162, -895, -1145, +-1041, -685, -256, 277, 704, 758, 546, 213, -101, -559, +-1201, -1800, -2285, -2769, -3378, -3807, -3664, -2777, -1450, 85, +2324, 5841, 10842, 16633, 22100, 26088, 27469, 25338, 19704, 11869, +3770, -2921, -8024, -11872, -14488, -15641, -15144, -13537, -11441, -9319, +-7391, -6189, -6185, -6908, -7666, -7571, -6253, -3835, -520, 3081, +6059, 7597, 7623, 6721, 5362, 3331, 415, -2917, -6065, -8455, +-10018, -10606, -9725, -7440, -4426, -1799, -160, 536, 667, 503, +215, 259, 853, 1991, 3331, 4451, 5301, 5778, 5672, 4827, +3326, 1308, -1110, -3771, -6317, -8033, -8488, -7750, -6305, -4510, +-2597, -750, 991, 2594, 4158, 5717, 6930, 7242, 6545, 5177, +3703, 2682, 1895, 1262, 502, -718, -2187, -3855, -5103, -5504, +-5059, -3968, -2750, -1543, -190, 1453, 3209, 4710, 5725, 5949, +5410, 4261, 2638, 1000, -343, -1117, -1309, -1174, -876, -645, +-549, -605, -820, -1020, -1150, -1083, -759, -266, 266, 718, +1122, 1291, 996, 280, -559, -1184, -1425, -1347, -964, -121, +931, 1934, 2513, 2533, 2289, 1829, 1121, 175, -863, -1830, +-2626, -3195, -3497, -3240, -2332, -1109, 217, 1574, 2984, 4422, +5654, 6809, 8611, 11821, 15948, 19056, 19149, 15576, 9780, 3962, +-793, -4336, -7098, -9189, -10674, -11783, -12413, -12376, -11328, -9826, +-8693, -8074, -7862, -7626, -7249, -6587, -5008, -2331, 934, 3808, +5591, 6321, 6108, 4896, 2923, 786, -1127, -2844, -4833, -6939, +-8252, -8252, -7059, -5113, -2980, -1056, 269, 586, 267, -6, +-74, 237, 1014, 2089, 3356, 4224, 3976, 3139, 2365, 1690, +1105, 111, -1597, -3341, -4574, -4650, -2814, 195, 2918, 4463, +4362, 3508, 2944, 2198, 1323, 601, -55, -269, -598, -1246, +-1264, -484, 708, 1827, 2195, 1971, 1651, 1118, 987, 1826, +2923, 3810, 3953, 3153, 2428, 1689, 557, -282, -621, -382, +233, 356, 119, 175, 427, 1007, 1886, 2574, 2837, 2213, +336, -1951, -3775, -4853, -4943, -4494, -3807, -3101, -2791, -2653, +-2312, -1606, -654, 74, 357, 312, 166, 299, 826, 1559, +2235, 2339, 1685, 513, -979, -2440, -3557, -4094, -3946, -3212, +-1907, 450, 4592, 10495, 17210, 23111, 26436, 26240, 22371, 15564, +7536, 130, -5281, -8506, -10062, -10346, -9974, -9359, -8938, -9021, +-9159, -9304, -9817, -10970, -12565, -13496, -12711, -9924, -5490, -45, +5450, 9425, 10885, 9866, 7182, 4089, 1114, -1553, -3622, -5135, +-6349, -7268, -7341, -6067, -3460, -648, 966, 1231, 431, -1016, +-2454, -3166, -2295, 235, 3317, 5788, 7305, 7902, 7628, 6454, +4465, 2241, 114, -2118, -4438, -6473, -7583, -7305, -6073, -4453, +-2639, -1148, -157, 484, 855, 1668, 2864, 3632, 3961, 3679, +2958, 2259, 1322, 290, -512, -1308, -1992, -2623, -3492, -4086, +-4006, -3359, -2034, -384, 882, 1920, 2581, 2744, 2936, 3024, +3291, 4045, 4629, 4942, 4893, 4402, 3955, 3416, 2556, 1498, +214, -1134, -2152, -2718, -2555, -1561, -324, 898, 1892, 2269, +2213, 1720, 833, 48, -872, -2074, -3139, -3943, -3989, -3259, +-2432, -1511, -439, 560, 1356, 1537, 1037, 317, -500, -1272, +-1846, -2196, -2191, -2057, -2114, -2137, -1795, -1022, 199, 1664, +3149, 4682, 5847, 6382, 6650, 7155, 8892, 12032, 15108, 16459, +14946, 10774, 5570, 678, -3396, -6522, -8617, -9788, -10212, -10372, +-10686, -10654, -10122, -9147, -7744, -6388, -5226, -4406, -3994, -3443, +-2035, 356, 3250, 5796, 7184, 7206, 5733, 3037, 124, -2255, +-3735, -4522, -5220, -5758, -5868, -5596, -4829, -3528, -1848, -65, +855, 472, -627, -1774, -2189, -1460, 152, 2180, 3785, 4142, +3427, 2344, 1557, 1386, 1272, 868, 447, 197, 132, 208, +68, -265, -644, -1466, -2442, -3535, -4551, -4723, -4195, -2936, +-1152, 414, 1331, 1633, 1501, 1069, 540, -257, -763, -458, +393, 1716, 2990, 4051, 5007, 5581, 5657, 5242, 4443, 3470, +2576, 1950, 1765, 2049, 2539, 3009, 3274, 3181, 2730, 1825, +608, -538, -1572, -2323, -2751, -2887, -2543, -2001, -1562, -1373, +-1375, -1354, -1390, -1588, -2062, -2584, -2890, -3029, -2966, -2561, +-1752, -744, 108, 539, 571, 151, -741, -1720, -2296, -2140, +-1405, -418, 932, 2929, 5750, 9166, 12815, 16191, 18447, 18648, +16134, 11395, 5530, -26, -4322, -7155, -8317, -8245, -7641, -7173, +-7393, -8198, -9134, -9932, -10488, -10815, -10934, -10610, -9704, -8009, +-5221, -1498, 2537, 5803, 7621, 7898, 6920, 5224, 3258, 1621, +614, 240, 170, 187, 292, 318, 282, 112, -238, -714, +-1533, -2719, -3889, -4478, -3968, -2462, -360, 1938, 3891, 5080, +5245, 4397, 3025, 1725, 845, 449, 418, 413, 178, -289, +-901, -1421, -1789, -2151, -2460, -2730, -2929, -2908, -2700, -2242, +-1447, -540, 139, 408, 177, -384, -1111, -1817, -2150, -2108, +-1802, -1445, -1125, -617, 230, 1291, 2297, 3256, 4025, 4532, +4604, 4045, 3285, 2584, 2181, 2255, 2551, 2941, 3177, 2801, +1776, 436, -730, -1367, -1620, -1819, -2040, -2209, -2280, -2261, +-2116, -1744, -1074, -340, 128, 194, -157, -507, -661, -671, +-472, -296, -235, -271, -297, -201, 133, 553, 633, 268, +-524, -1483, -2083, -2172, -1752, -964, -168, 524, 1223, 1846, +2490, 3192, 3731, 4408, 5420, 6875, 8869, 10837, 12023, 11843, +9949, 6777, 3310, 48, -2565, -4405, -5756, -6638, -7191, -7662, +-8011, -8239, -8455, -8500, -8388, -8229, -7999, -7797, -7204, -5825, +-3570, -629, 2301, 4866, 6855, 7932, 7910, 6915, 5316, 3443, +1617, -19, -1279, -1949, -2149, -1998, -1689, -1331, -1007, -914, +-1258, -2031, -2880, -3583, -3838, -3260, -1897, -169, 1405, 2549, +3690, 5215, 6590, 6968, 5795, 3492, 1236, -413, -1499, -2131, +-2442, -2290, -1768, -1452, -1772, -2840, -4507, -6076, -6832, -6783, +-6248, -5728, -5240, -4284, -2664, -589, 1494, 3212, 4507, 5224, +5081, 4114, 2794, 1848, 1676, 2158, 2885, 3486, 3766, 3708, +3336, 2765, 2243, 1864, 1518, 958, 79, -880, -1493, -1537, +-1122, -591, -187, 5, -134, -683, -1537, -2434, -2991, -2953, +-2478, -1874, -1472, -1320, -1201, -973, -584, -282, -277, -566, +-1103, -1729, -2291, -2630, -2536, -1862, -630, 986, 2898, 5004, +7290, 9591, 11621, 13469, 14919, 15680, 15357, 13594, 10729, 7198, +3657, 618, -1729, -3347, -4455, -5264, -6066, -6987, -8233, -9806, +-11356, -12598, -13192, -13121, -12543, -11601, -10246, -8349, -5958, -3218, +-488, 1942, 3848, 4999, 5415, 5213, 4723, 4338, 4137, 4086, +4135, 4211, 4243, 4130, 3684, 2887, 1777, 304, -1362, -3158, +-4874, -6085, -6638, -6482, -5595, -4200, -2538, -824, 634, 1780, +2729, 3613, 4389, 4774, 4659, 4164, 3540, 2841, 2087, 1392, +718, 17, -922, -2094, -3314, -4470, -5300, -5589, -5358, -4820, +-4316, -3990, -3717, -3234, -2654, -2175, -1827, -1552, -1246, -995, +-677, -209, 424, 1149, 1905, 2758, 3635, 4388, 4890, 5203, +5424, 5510, 5396, 5030, 4438, 3708, 3117, 2714, 2259, 1674, +877, 48, -571, -1012, -1388, -1777, -2081, -2134, -2054, -1884, +-1572, -1167, -631, 43, 807, 1567, 2136, 2383, 2334, 2086, +1706, 1200, 499, -431, -1423, -2368, -3127, -3542, -3518, -3061, +-2397, -1737, -1208, -848, -614, -412, -215, 22, 488, 1165, +1956, 2826, 3788, 4835, 5990, 7315, 8784, 10052, 10494, 9747, +7897, 5484, 3003, 619, -1493, -3170, -4385, -5112, -5539, -5981, +-6465, -7074, -7781, -8448, -8951, -9202, -9251, -9049, -8414, -7175, +-5373, -3189, -775, 1643, 3783, 5235, 5711, 5374, 4641, 3723, +2756, 1901, 1277, 1015, 1037, 1145, 1298, 1433, 1399, 1079, +356, -688, -1962, -3334, -4327, -4701, -4535, -3918, -2851, -1133, +1197, 3429, 4794, 5099, 4558, 3646, 2632, 1646, 770, -32, +-630, -992, -1209, -1396, -1906, -2773, -3507, -3918, -4184, -4625, +-5350, -5934, -5923, -5254, -4026, -2469, -856, 694, 2080, 3121, +3806, 4104, 4181, 4221, 4235, 4332, 4481, 4620, 4722, 4886, +5097, 5311, 5397, 5086, 4386, 3346, 2070, 777, -320, -1116, +-1618, -1995, -2406, -2724, -2934, -3121, -3229, -3210, -2936, -2444, +-1983, -1705, -1533, -1346, -1044, -639, -221, 172, 475, 574, +558, 574, 578, 428, 86, -263, -382, -326, -259, -213, +-72, 354, 1093, 2108, 3431, 5202, 7153, 8712, 9547, 9425, +8371, 6507, 4055, 1597, -299, -1466, -2056, -2448, -2878, -3324, +-3815, -4371, -4938, -5577, -6267, -6989, -7769, -8383, -8702, -8789, +-8433, -7462, -5962, -4182, -2418, -916, 253, 1140, 1785, 2314, +2783, 3203, 3661, 4081, 4290, 4391, 4406, 4445, 4494, 4280, +3678, 2728, 1664, 590, -478, -1455, -2199, -2643, -2859, -2925, +-2884, -2661, -2228, -1645, -986, -298, 425, 1138, 1743, 2126, +2112, 1655, 859, -19, -712, -1167, -1425, -1459, -1356, -1220, +-1206, -1410, -1649, -1825, -1992, -2221, -2596, -3024, -3383, -3622, +-3567, -3107, -2262, -1118, 123, 1227, 2100, 2691, 2989, 3183, +3380, 3582, 3823, 4183, 4672, 5206, 5668, 5889, 5922, 5798, +5406, 4648, 3483, 2132, 784, -478, -1450, -2007, -2293, -2374, +-2438, -2526, -2439, -2230, -1823, -1224, -616, -88, 236, 416, +639, 818, 799, 645, 397, 57, -357, -867, -1329, -1592, +-1688, -1687, -1571, -1336, -1074, -839, -653, -547, -513, -569, +-683, -722, -650, -481, -262, 1, 343, 653, 907, 1133, +1382, 1662, 1847, 1945, 2071, 2244, 2396, 2431, 2280, 1931, +1457, 973, 495, -19, -679, -1521, -2408, -3173, -3699, -3903, +-3759, -3400, -2879, -2335, -1904, -1609, -1557, -1668, -1734, -1721, +-1699, -1621, -1373, -880, -229, 358, 845, 1279, 1669, 1912, +1879, 1557, 1051, 474, -74, -468, -612, -483, -215, 91, +304, 273, 49, -386, -961, -1471, -1876, -2197, -2386, -2430, +-2351, -2184, -1984, -1767, -1556, -1428, -1428, -1489, -1580, -1676, +-1623, -1368, -824, 8, 953, 1831, 2497, 3006, 3427, 3668, +3719, 3756, 3823, 3884, 3861, 3708, 3589, 3586, 3585, 3535, +3393, 3140, 2861, 2483, 2019, 1485, 918, 436, 73, -151, +-307, -479, -626, -657, -591, -551, -564, -605, -585, -549, +-589, -653, -734, -832, -795, -728, -709, -725, -777, -769, +-767, -867, -1038, -1108, -1043, -962, -950, -996, -902, -625, +-293, 29, 340, 662, 984, 1283, 1596, 1887, 2094, 2142, +1978, 1631, 1166, 592, -77, -699, -1174, -1502, -1659, -1727, +-1769, -1829, -1974, -2134, -2284, -2466, -2630, -2688, -2689, -2740, +-2751, -2633, -2422, -2144, -1858, -1569, -1269, -1047, -915, -843, +-744, -519, -235, 112, 514, 906, 1328, 1770, 2236, 2682, +2970, 2954, 2704, 2379, 2005, 1612, 1226, 900, 693, 539, +348, 125, -119, -391, -649, -900, -1066, -1113, -1135, -1166, +-1098, -874, -569, -322, -259, -275, -210, -185, -192, -125, +21, 233, 414, 466, 445, 459, 455, 334, 186, 47, +-82, -294, -591, -726, -511, -8, 514, 869, 1183, 1584, +1989, 2245, 2434, 2691, 3017, 3315, 3412, 3322, 3154, 2896, +2470, 1956, 1425, 872, 349, -185, -652, -1052, -1435, -1696, +-1854, -1964, -2029, -2140, -2227, -2100, -1839, -1509, -1200, -943, +-591, -238, -4, 115, 179, 187, 113, -29, -296, -572, +-713, -794, -831, -825, -765, -606, -521, -489, -419, -323, +-114, 114, 250, 347, 465, 560, 588, 555, 486, 497, +657, 850, 1035, 1101, 996, 892, 754, 594, 427, 155, +-175, -492, -807, -1117, -1360, -1526, -1550, -1451, -1391, -1416, +-1495, -1610, -1699, -1741, -1728, -1582, -1277, -865, -435, -55, +284, 600, 788, 845, 880, 946, 1097, 1236, 1369, 1582, +1864, 2110, 2174, 2004, 1682, 1299, 867, 471, 142, -175, +-465, -704, -901, -1047, -1144, -1249, -1357, -1552, -1846, -2122, +-2313, -2350, -2285, -2249, -2301, -2408, -2369, -2194, -1999, -1710, +-1457, -1201, -851, -566, -275, 9, 286, 559, 772, 973, +1154, 1351, 1541, 1757, 1952, 2102, 2288, 2389, 2358, 2296, +2231, 2170, 2123, 2084, 2110, 2143, 2043, 1880, 1678, 1452, +1274, 1074, 764, 320, -179, -583, -872, -1029, -1010, -778, +-434, -119, 217, 527, 869, 1196, 1367, 1446, 1562, 1736, +1935, 2098, 2169, 2297, 2466, 2550, 2520, 2300, 1919, 1450, +941, 456, 6, -453, -942, -1450, -2016, -2655, -3233, -3671, +-3921, -4114, -4387, -4652, -4852, -4895, -4729, -4480, -4200, -3782, +-3217, -2594, -1952, -1292, -627, 17, 523, 898, 1139, 1213, +1202, 1078, 819, 516, 270, 143, 98, 91, 126, 106, +2, -105, -210, -294, -353, -396, -398, -349, -217, 26, +286, 576, 833, 929, 932, 855, 718, 535, 326, 176, +61, 11, -26, -64, -62, -12, 114, 229, 319, 425, +425, 354, 342, 408, 599, 833, 1071, 1343, 1620, 1793, +1787, 1651, 1456, 1336, 1283, 1179, 990, 746, 523, 303, +42, -219, -440, -585, -691, -862, -996, -977, -831, -596, +-329, -140, -27, 26, 79, 186, 289, 346, 381, 430, +608, 820, 929, 933, 858, 723, 526, 306, 123, -49, +-198, -355, -462, -481, -484, -389, -241, -159, -147, -205, +-250, -189, -40, 64, 83, 60, 16, -27, -92, -163, +-197, -192, -107, 39, 226, 387, 547, 709, 812, 825, +797, 804, 786, 632, 380, 57, -280, -597, -894, -1089, +-1205, -1278, -1365, -1519, -1706, -1848, -1879, -1823, -1682, -1515, +-1353, -1215, -1086, -945, -785, -569, -376, -240, -155, -175, +-280, -409, -544, -654, -707, -725, -720, -647, -502, -389, +-354, -344, -323, -268, -221, -237, -223, -120, 42, 220, +420, 602, 735, 783, 659, 488, 369, 289, 270, 241, +128, -29, -189, -286, -267, -155, 33, 264, 492, 627, +635, 597, 587, 687, 862, 996, 1055, 1034, 914, 783, +628, 455, 341, 303, 348, 400, 448, 563, 814, 1105, +1326, 1437, 1432, 1417, 1431, 1486, 1618, 1812, 1970, 1936, +1697, 1344, 963, 689, 641, 895, 1378, 1834, 2123, 2203, +2174, 2151, 2197, 2357, 2530, 2612, 2516, 2187, 1777, 1323, +850, 376, -117, -664, -1323, -2070, -2841, -3628, -4298, -4850, +-5322, -5642, -5922, -6194, -6336, -6313, -6099, -5720, -5244, -4678, +-4048, -3473, -2938, -2334, -1610, -714, 269, 1223, 1976, 2433, +2660, 2736, 2770, 2811, 2884, 2936, 2876, 2605, 2086, 1421, +741, 139, -313, -651, -873, -1064, -1295, -1533, -1792, -2035, +-2157, -2114, -1931, -1758, -1614, -1498, -1390, -1215, -1024, -767, +-420, 4, 453, 828, 1108, 1336, 1583, 1911, 2291, 2629, +2896, 3055, 3134, 3174, 3145, 3103, 3106, 3160, 3179, 3064, +2740, 2260, 1721, 1202, 845, 656, 551, 417, 237, 2, +-281, -509, -597, -546, -419, -369, -500, -714, -946, -1159, +-1322, -1434, -1498, -1512, -1483, -1480, -1555, -1710, -1835, -1831, +-1764, -1686, -1541, -1258, -820, -331, 123, 544, 912, 1252, +1558, 1803, 2016, 2188, 2336, 2479, 2597, 2675, 2690, 2632, +2513, 2361, 2178, 1995, 1812, 1547, 1167, 744, 328, -70, +-437, -731, -863, -819, -648, -464, -345, -333, -433, -620, +-855, -1164, -1465, -1679, -1775, -1829, -1885, -1949, -2071, -2225, +-2396, -2523, -2539, -2477, -2463, -2506, -2475, -2248, -1823, -1295, +-760, -300, 31, 137, 40, -179, -366, -396, -373, -379, +-463, -640, -814, -918, -932, -873, -768, -653, -609, -694, +-860, -1021, -1053, -940, -761, -563, -384, -240, -175, -206, +-253, -297, -292, -295, -341, -409, -349, -83, 251, 580, +782, 910, 1043, 1147, 1279, 1514, 1883, 2373, 2824, 3110, +3177, 3022, 2742, 2423, 2208, 2180, 2196, 2163, 2065, 1923, +1815, 1697, 1551, 1400, 1233, 1053, 840, 589, 392, 314, +314, 335, 298, 191, 5, -293, -667, -968, -983, -587, +146, 1008, 1838, 2576, 3246, 3882, 4480, 5055, 5597, 6033, +6205, 5940, 5199, 4152, 3096, 2142, 1235, 303, -711, -1800, +-2935, -4103, -5211, -6178, -6978, -7587, -7970, -8117, -8105, -7958, +-7596, -6954, -6191, -5519, -5031, -4589, -3930, -3012, -1941, -815, +307, 1403, 2353, 3054, 3505, 3719, 3741, 3610, 3328, 2927, +2452, 1989, 1562, 1056, 283, -772, -1907, -2775, -3216, -3285, +-3057, -2712, -2424, -2284, -2289, -2368, -2400, -2199, -1734, -1156, +-613, -270, -83, 51, 190, 330, 373, 357, 306, 264, +305, 447, 644, 787, 850, 855, 833, 801, 841, 990, +1212, 1345, 1335, 1338, 1437, 1622, 1791, 1946, 2183, 2486, +2739, 2857, 2950, 3036, 3024, 2832, 2493, 2187, 1978, 1895, +1867, 1712, 1346, 843, 452, 269, 101, -201, -618, -1016, +-1415, -1830, -2206, -2349, -2100, -1545, -834, -257, -46, -208, +-433, -417, -168, 124, 308, 475, 741, 1081, 1375, 1549, +1590, 1467, 1232, 975, 773, 646, 610, 721, 877, 882, +597, 166, -142, -193, -31, 235, 477, 551, 427, 199, +11, -75, -108, -74, 86, 389, 701, 863, 812, 612, +336, -9, -422, -922, -1431, -1809, -1927, -1881, -1897, -2047, +-2279, -2511, -2766, -3094, -3403, -3525, -3376, -2929, -2369, -1937, +-1811, -1900, -1932, -1809, -1659, -1638, -1635, -1507, -1294, -1207, +-1385, -1673, -1918, -2046, -2125, -2231, -2300, -2179, -1803, -1300, +-913, -799, -856, -901, -840, -669, -430, -144, 177, 557, +981, 1306, 1385, 1191, 924, 859, 969, 1053, 1046, 1111, +1407, 1798, 2014, 1936, 1758, 1748, 1912, 2183, 2431, 2592, +2716, 2805, 2799, 2586, 2197, 1731, 1299, 969, 752, 759, +925, 1085, 1113, 989, 816, 710, 691, 797, 1031, 1303, +1585, 1838, 1995, 1942, 1656, 1272, 924, 641, 354, 53, +-235, -487, -697, -769, -574, -134, 438, 1086, 1771, 2478, +3114, 3600, 4052, 4630, 5402, 6187, 6563, 6139, 4885, 3246, +1726, 540, -405, -1330, -2220, -3065, -3981, -5117, -6417, -7649, +-8614, -9226, -9505, -9497, -9264, -8771, -7997, -7069, -6256, -5741, +-5335, -4744, -3867, -2731, -1415, 80, 1492, 2475, 2925, 2995, +2948, 2879, 2794, 2731, 2736, 2859, 3059, 3108, 2739, 1834, +696, -188, -594, -696, -764, -685, -313, 198, 469, 296, +-223, -827, -1277, -1489, -1482, -1302, -1043, -821, -762, -924, +-1254, -1581, -1782, -1828, -1725, -1378, -773, -101, 337, 412, +231, -10, -92, 146, 710, 1366, 1844, 2154, 2502, 3000, +3398, 3538, 3531, 3538, 3669, 3829, 3948, 4038, 3997, 3778, +3402, 2880, 2211, 1414, 671, 139, -250, -587, -900, -1114, +-1332, -1765, -2292, -2568, -2419, -2152, -2014, -1888, -1441, -675, +23, 421, 516, 574, 729, 1012, 1353, 1680, 1972, 2168, +2238, 2111, 1802, 1394, 964, 578, 289, 203, 206, 115, +-183, -617, -915, -983, -992, -1084, -1153, -1052, -695, -277, +-5, 115, 159, 230, 305, 271, 60, -209, -326, -128, +329, 732, 768, 401, -98, -495, -824, -1199, -1629, -1917, +-2003, -2099, -2323, -2556, -2615, -2585, -2638, -2788, -2902, -2859, +-2709, -2461, -2036, -1618, -1418, -1426, -1432, -1219, -860, -534, +-273, -95, -55, -117, -136, -118, -129, -220, -335, -376, +-422, -461, -396, -275, -257, -468, -825, -1112, -1289, -1341, +-1188, -823, -416, -142, 17, 217, 516, 799, 972, 1164, +1455, 1825, 2180, 2361, 2428, 2513, 2734, 3015, 2952, 2339, +1443, 807, 716, 886, 894, 644, 324, 64, -111, -231, +-314, -335, -303, -240, -122, 90, 402, 726, 888, 910, +1009, 1362, 1858, 2143, 2026, 1710, 1471, 1339, 1161, 757, +213, -187, -365, -371, -456, -739, -998, -1098, -1021, -930, +-1043, -1341, -1598, -1548, -1126, -398, 549, 1571, 2626, 3500, +3927, 4015, 4084, 4373, 4771, 5090, 5234, 5124, 4602, 3556, +2285, 1155, 280, -493, -1383, -2373, -3376, -4409, -5505, -6562, +-7440, -8092, -8486, -8538, -8257, -7707, -6965, -6163, -5348, -4600, +-3978, -3459, -2964, -2374, -1553, -445, 770, 1849, 2612, 3012, +3179, 3112, 2838, 2466, 2182, 2184, 2395, 2532, 2345, 1766, +1029, 438, 57, -158, -212, -69, 197, 396, 336, -8, +-450, -798, -893, -737, -533, -387, -303, -207, -111, -211, +-557, -993, -1389, -1632, -1631, -1348, -838, -350, -115, -163, +-272, -252, -85, 240, 667, 1111, 1495, 1831, 2212, 2535, +2649, 2536, 2427, 2444, 2463, 2418, 2426, 2520, 2514, 2227, +1802, 1510, 1370, 1198, 925, 681, 494, 291, 41, -150, +-208, -279, -464, -643, -691, -604, -440, -221, -10, 139, +228, 321, 435, 460, 354, 236, 296, 462, 576, 591, +557, 477, 245, -75, -313, -411, -431, -468, -537, -551, +-594, -781, -978, -1072, -1061, -1068, -1175, -1216, -1060, -773, +-518, -431, -398, -338, -243, -88, 73, 209, 278, 305, +362, 443, 428, 354, 346, 414, 413, 193, -98, -228, +-260, -438, -817, -1145, -1268, -1315, -1409, -1481, -1437, -1386, +-1532, -1834, -2111, -2221, -2072, -1653, -1086, -600, -411, -402, +-328, -119, 27, 29, 103, 321, 526, 569, 502, 438, +344, 172, -96, -356, -499, -521, -382, -217, -232, -390, +-548, -517, -382, -304, -257, -159, -32, 32, 43, -20, +-160, -376, -592, -650, -521, -269, -35, 149, 305, 383, +455, 672, 1047, 1430, 1634, 1714, 1826, 1956, 2016, 1962, +1823, 1670, 1515, 1405, 1426, 1531, 1573, 1459, 1298, 1245, +1282, 1291, 1225, 1127, 1063, 1106, 1195, 1193, 1067, 877, +584, 161, -240, -464, -511, -615, -910, -1224, -1318, -1174, +-992, -728, -162, 596, 1172, 1413, 1559, 1893, 2385, 2843, +3173, 3291, 3054, 2480, 1872, 1515, 1347, 1058, 492, -178, +-869, -1670, -2494, -3106, -3495, -3913, -4451, -4896, -5068, -5016, +-4951, -4857, -4642, -4447, -4401, -4410, -4192, -3730, -3232, -2713, +-2105, -1385, -719, -168, 429, 1000, 1335, 1442, 1636, 2074, +2556, 2790, 2711, 2394, 1884, 1305, 973, 1020, 1095, 909, +602, 339, 81, -252, -618, -775, -754, -837, -1034, -1094, +-842, -549, -523, -700, -793, -750, -671, -562, -386, -169, +42, 244, 469, 707, 857, 965, 1169, 1426, 1664, 1866, +2103, 2328, 2379, 2283, 2207, 2216, 2186, 2033, 1862, 1750, +1645, 1476, 1336, 1283, 1162, 866, 539, 313, 179, 44, +-191, -400, -525, -730, -1077, -1448, -1713, -1831, -1877, -1914, +-1965, -2035, -2088, -2069, -1991, -1876, -1679, -1393, -1011, -584, +-225, 6, 160, 326, 545, 774, 935, 1019, 1080, 1122, +1134, 1080, 904, 721, 651, 614, 501, 318, 150, 8, +-167, -379, -532, -587, -603, -656, -712, -695, -574, -392, +-172, 52, 191, 244, 283, 394, 559, 721, 874, 1011, +1053, 944, 763, 619, 540, 475, 441, 434, 425, 333, +130, -33, -128, -202, -316, -489, -609, -633, -650, -691, +-699, -692, -735, -818, -888, -955, -944, -879, -832, -744, +-660, -670, -821, -1036, -1131, -988, -727, -555, -611, -777, +-891, -985, -1112, -1280, -1389, -1377, -1292, -1142, -952, -732, +-572, -596, -649, -606, -505, -402, -346, -263, -114, 50, +189, 308, 330, 262, 173, 156, 236, 279, 273, 320, +396, 391, 281, 151, 160, 312, 491, 616, 705, 789, +871, 931, 943, 963, 1047, 1077, 1085, 1193, 1328, 1429, +1442, 1407, 1358, 1302, 1227, 1192, 1185, 1072, 865, 616, +428, 349, 266, 134, -6, -123, -187, -201, -136, 20, +177, 309, 389, 504, 745, 1107, 1465, 1658, 1682, 1611, +1575, 1644, 1739, 1785, 1760, 1666, 1528, 1397, 1262, 1089, +861, 585, 297, -5, -321, -544, -702, -929, -1258, -1637, +-1997, -2266, -2457, -2658, -2855, -3005, -3082, -3084, -3049, -3020, +-2985, -2901, -2745, -2485, -2199, -1930, -1688, -1514, -1410, -1324, +-1142, -828, -414, 1, 321, 525, 604, 597, 539, 543, +606, 633, 605, 520, 390, 256, 170, 104, 23, -108, +-322, -503, -617, -695, -747, -782, -748, -657, -598, -618, +-646, -626, -553, -415, -224, -34, 156, 321, 474, 675, +884, 1052, 1145, 1220, 1349, 1486, 1576, 1635, 1624, 1510, +1338, 1178, 1120, 1121, 1079, 942, 747, 511, 236, -24, +-240, -423, -594, -745, -830, -850, -810, -777, -731, -616, +-519, -499, -509, -447, -295, -82, 169, 459, 799, 1164, +1514, 1776, 1919, 1949, 1919, 1891, 1842, 1870, 1961, 2059, +2149, 2165, 2152, 2144, 2083, 2011, 1986, 1897, 1724, 1547, +1390, 1282, 1245, 1275, 1295, 1250, 1076, 783, 550, 411, +280, 65, -237, -525, -726, -909, -1114, -1322, -1578, -1889, +-2222, -2495, -2698, -2904, -3081, -3212, -3268, -3210, -3083, -2903, +-2709, -2563, -2474, -2336, -2077, -1802, -1601, -1454, -1330, -1193, +-1111, -1113, -1041, -887, -769, -735, -714, -672, -611, -549, +-506, -412, -305, -305, -353, -388, -426, -458, -455, -366, +-202, -47, 59, 102, 109, 111, 107, 142, 201, 230, +253, 304, 406, 476, 487, 510, 560, 641, 657, 588, +534, 513, 574, 688, 771, 871, 998, 1110, 1215, 1255, +1289, 1364, 1460, 1551, 1605, 1623, 1574, 1486, 1440, 1385, +1360, 1383, 1325, 1172, 1003, 839, 728, 690, 604, 463, +298, 158, 127, 186, 240, 261, 279, 325, 366, 406, +407, 382, 386, 397, 418, 433, 416, 377, 348, 384, +425, 399, 336, 287, 228, 176, 161, 82, -39, -103, +-64, 76, 295, 485, 597, 594, 517, 425, 341, 331, +323, 224, 49, -119, -176, -218, -306, -429, -618, -860, +-1072, -1269, -1406, -1454, -1526, -1584, -1629, -1647, -1649, -1667, +-1673, -1713, -1823, -1928, -1990, -1955, -1830, -1726, -1714, -1757, +-1748, -1640, -1474, -1274, -1129, -1069, -1029, -996, -929, -834, +-760, -696, -575, -407, -239, -99, -22, 5, 12, 7, +10, -15, -64, -82, -39, 40, 122, 208, 267, 277, +244, 189, 147, 155, 175, 220, 312, 472, 619, 660, +667, 716, 817, 918, 1045, 1155, 1208, 1198, 1141, 1162, +1216, 1266, 1324, 1385, 1425, 1427, 1376, 1301, 1281, 1323, +1365, 1389, 1408, 1353, 1272, 1240, 1217, 1146, 1071, 1041, +1006, 997, 966, 903, 859, 784, 697, 660, 634, 603, +601, 591, 559, 487, 372, 256, 186, 232, 307, 302, +209, 104, 53, 90, 135, 156, 194, 211, 235, 280, +321, 347, 313, 260, 230, 181, 87, -74, -230, -354, +-440, -479, -506, -541, -632, -770, -961, -1173, -1373, -1564, +-1719, -1892, -2062, -2142, -2148, -2098, -2024, -1975, -1959, -1978, +-2015, -2036, -2036, -1944, -1796, -1646, -1520, -1414, -1282, -1139, +-923, -699, -588, -583, -613, -609, -584, -557, -563, -534, +-446, -319, -199, -120, -39, 4, -20, -62, -59, -30, +-1, 17, 58, 141, 223, 306, 401, 481, 546, 610, +655, 693, 740, 741, 743, 785, 860, 955, 979, 981, +995, 1009, 1026, 997, 914, 826, 777, 787, 817, 834, +883, 922, 992, 1118, 1229, 1313, 1318, 1278, 1272, 1298, +1352, 1382, 1412, 1456, 1478, 1491, 1507, 1506, 1492, 1441, +1345, 1265, 1234, 1178, 1053, 910, 749, 636, 584, 542, +505, 408, 231, 27, -141, -189, -165, -131, -103, -127, +-127, -137, -173, -182, -238, -262, -198, -87, 14, 93, +94, 31, -10, -54, -88, -184, -345, -488, -599, -649, +-709, -818, -954, -1122, -1248, -1336, -1445, -1529, -1601, -1621, +-1621, -1704, -1773, -1852, -1915, -1928, -1903, -1860, -1855, -1884, +-1909, -1923, -1911, -1911, -1928, -1881, -1761, -1624, -1503, -1370, +-1211, -1055, -912, -804, -706, -614, -519, -420, -285, -124, +-13, 57, 86, 128, 205, 270, 321, 313, 283, 242, +225, 244, 309, 372, 426, 500, 530, 536, 551, 559, +590, 629, 652, 699, 754, 802, 845, 880, 914, 972, +1061, 1172, 1256, 1297, 1330, 1374, 1445, 1523, 1597, 1684, +1759, 1838, 1933, 2014, 2061, 2041, 1982, 1986, 2023, 2067, +2128, 2089, 1986, 1835, 1682, 1558, 1433, 1306, 1144, 970, +778, 615, 491, 379, 252, 67, -101, -218, -290, -359, +-479, -607, -708, -769, -816, -841, -835, -803, -748, -727, +-736, -762, -808, -815, -785, -783, -803, -827, -817, -815, +-838, -859, -880, -861, -866, -926, -1011, -1077, -1093, -1091, +-1107, -1152, -1174, -1210, -1250, -1337, -1467, -1577, -1672, -1748, +-1778, -1760, -1706, -1643, -1579, -1548, -1508, -1424, -1299, -1153, +-1010, -925, -852, -717, -565, -378, -231, -124, 4, 119, +233, 334, 403, 431, 465, 486, 445, 433, 419, 387, +374, 323, 254, 189, 148, 122, 89, 56, -1, -69, +-121, -152, -138, -131, -111, -66, -27, 13, 36, 74, +135, 197, 284, 372, 479, 601, 699, 814, 912, 963, +998, 1069, 1120, 1153, 1217, 1283, 1349, 1403, 1454, 1461, +1408, 1373, 1316, 1273, 1251, 1222, 1214, 1207, 1155, 1073, +1015, 943, 865, 811, 740, 635, 564, 477, 376, 298, +238, 157, 72, 38, 21, 16, 27, 28, 37, 39, +45, 113, 184, 232, 249, 274, 351, 435, 474, 488, +491, 457, 419, 399, 376, 355, 331, 315, 291, 256, +227, 126, -4, -143, -310, -469, -631, -762, -874, -968, +-1037, -1134, -1272, -1411, -1516, -1647, -1745, -1813, -1942, -2057, +-2116, -2116, -2097, -2059, -1993, -1910, -1814, -1723, -1651, -1590, +-1500, -1390, -1283, -1191, -1097, -993, -869, -756, -708, -623, +-529, -442, -346, -318, -333, -360, -356, -324, -287, -271, +-286, -282, -242, -192, -171, -179, -210, -239, -237, -196, +-169, -103, 3, 60, 137, 227, 315, 421, 536, 678, +781, 870, 966, 1063, 1186, 1307, 1383, 1459, 1560, 1636, +1684, 1742, 1784, 1848, 1896, 1915, 1922, 1868, 1818, 1798, +1788, 1759, 1749, 1713, 1643, 1584, 1539, 1455, 1296, 1146, +997, 880, 809, 741, 654, 568, 498, 407, 305, 186, +49, -67, -173, -251, -328, -358, -404, -450, -478, -535, +-553, -548, -526, -512, -531, -526, -484, -409, -353, -291, +-245, -195, -130, -110, -104, -114, -108, -113, -123, -137, +-203, -289, -372, -439, -488, -516, -573, -670, -773, -887, +-1002, -1111, -1207, -1304, -1396, -1478, -1540, -1581, -1604, -1623, +-1630, -1616, -1615, -1603, -1546, -1493, -1451, -1405, -1366, -1297, +-1211, -1094, -932, -785, -648, -503, -374, -286, -188, -93, +-71, -56, -29, -16, -8, 32, 52, 81, 119, 115, +101, 90, 80, 75, 77, 56, -11, -61, -66, -32, +13, 73, 166, 229, 285, 371, 441, 499, 557, 593, +657, 746, 852, 965, 1077, 1183, 1278, 1376, 1436, 1470, +1481, 1472, 1472, 1480, 1503, 1514, 1514, 1476, 1450, 1432, +1399, 1372, 1322, 1224, 1095, 1031, 985, 872, 753, 686, +606, 538, 512, 457, 390, 312, 223, 145, 94, 49, +11, -14, -40, -56, -85, -80, -14, 42, 95, 118, +115, 114, 93, 41, 0, -26, -52, -57, -79, -115, +-150, -212, -272, -327, -390, -489, -597, -673, -734, -808, +-881, -947, -1020, -1071, -1120, -1155, -1198, -1275, -1326, -1363, +-1416, -1480, -1526, -1552, -1569, -1576, -1579, -1554, -1531, -1500, +-1450, -1388, -1305, -1209, -1121, -1039, -964, -869, -774, -698, +-614, -526, -477, -445, -401, -341, -264, -192, -131, -56, +-12, 8, 65, 109, 141, 179, 181, 170, 174, 182, +172, 180, 213, 248, 272, 302, 337, 365, 407, 451, +493, 535, 567, 601, 635, 684, 742, 792, 857, 924, +963, 1017, 1114, 1203, 1262, 1328, 1362, 1379, 1400, 1383, +1380, 1383, 1368, 1398, 1431, 1445, 1471, 1461, 39, 36, +24, 5, -19, -45, -67, -80, -85, -78, -58, -36, +-18, -10, -11, -21, -32, -43, -50, -55, -58, -59, +-54, -35, -4, 27, 49, 53, 41, 16, -16, -50, +-80, -104, -124, -140, -149, -148, -136, -117, -99, -86, +-84, -88, -97, -106, -111, -113, -107, -91, -64, -29, +2, 24, 31, 22, 0, -29, -58, -80, -91, -91, +-79, -54, -22, 10, 36, 49, 47, 33, 13, -5, +-18, -25, -24, -13, 14, 60, 115, 168, 208, 232, +241, 238, 229, 218, 211, 206, 203, 202, 207, 219, +235, 248, 254, 248, 231, 206, 179, 154, 134, 120, +115, 122, 140, 161, 176, 181, 175, 158, 134, 106, +78, 52, 31, 15, 9, 11, 17, 21, 14, -5, +-38, -79, -121, -155, -179, -196, -207, -208, -193, -165, +-133, -109, -100, -110, -138, -178, -219, -251, -269, -275, +-274, -264, -246, -220, -192, -169, -152, -143, -141, -139, +-136, -129, -121, -114, -103, -82, -51, -14, 19, 42, +50, 40, 17, -11, -37, -56, -69, -73, -68, -52, +-30, -9, 4, 6, -6, -26, -45, -56, -64, -75, +-89, -97, -93, -74, -44, -10, 17, 33, 29, 10, +-10, -22, -23, -19, -11, -1, 11, 27, 43, 57, +66, 70, 68, 65, 65, 68, 75, 86, 103, 130, +162, 196, 228, 254, 272, 278, 272, 258, 238, 215, +193, 175, 165, 163, 166, 170, 171, 162, 142, 116, +90, 65, 37, 6, -21, -38, -43, -36, -20, -1, +16, 24, 21, 5, -15, -40, -70, -106, -143, -176, +-199, -212, -213, -207, -199, -192, -187, -181, -173, -169, +-168, -168, -167, -160, -147, -126, -100, -72, -46, -26, +-12, -3, 1, 2, 3, 9, 23, 48, 78, 110, +133, 141, 133, 119, 104, 91, 77, 60, 44, 35, +38, 52, 78, 108, 131, 139, 129, 105, 76, 44, +12, -15, -34, -41, -37, -22, 1, 22, 33, 30, +17, -2, -26, -54, -82, -105, -117, -116, -99, -68, +-29, 8, 37, 54, 58, 48, 26, -6, -40, -68, +-84, -83, -66, -38, -9, 12, 26, 33, 36, 30, +13, -11, -39, -60, -68, -59, -32, 2, 34, 51, +55, 47, 31, 6, -25, -59, -93, -124, -143, -148, +-140, -125, -113, -107, -105, -108, -114, -124, -136, -145, +-149, -144, -128, -102, -73, -46, -28, -19, -21, -33, +-51, -73, -92, -105, -106, -90, -60, -22, 9, 29, +38, 37, 27, 9, -14, -37, -52, -54, -37, 0, +50, 105, 154, 190, 216, 233, 241, 242, 236, 225, +210, 197, 192, 199, 216, 233, 243, 245, 239, 225, +206, 183, 159, 139, 125, 120, 122, 130, 141, 151, +156, 158, 155, 145, 131, 112, 88, 63, 43, 33, +31, 29, 21, 6, -11, -31, -54, -82, -110, -136, +-158, -172, -173, -161, -140, -121, -113, -115, -127, -146, +-167, -186, -202, -216, -226, -230, -225, -212, -195, -180, +-166, -154, -143, -135, -133, -136, -139, -141, -138, -127, +-107, -80, -52, -26, -8, 1, 1, -4, -15, -32, +-52, -69, -76, -72, -60, -50, -42, -33, -21, -11, +-7, -14, -32, -60, -94, -124, -139, -134, -111, -81, +-53, -32, -18, -8, 0, 6, 9, 4, -4, -13, +-16, -11, -2, 10, 24, 41, 58, 73, 85, 91, +92, 89, 89, 97, 115, 141, 172, 205, 232, 251, +264, 270, 270, 260, 240, 216, 195, 180, 170, 164, +161, 161, 161, 156, 146, 132, 110, 79, 39, 1, +-25, -38, -37, -27, -13, 0, 7, 11, 9, 0, +-20, -51, -88, -125, -157, -182, -197, -202, -198, -188, +-178, -167, -158, -155, -159, -169, -180, -186, -185, -172, +-147, -116, -81, -48, -18, 5, 19, 21, 16, 14, +20, 33, 49, 66, 85, 102, 115, 124, 127, 123, +107, 79, 46, 18, 3, 6, 24, 51, 80, 102, +112, 109, 97, 78, 52, 24, 0, -15, -23, -23, +-16, -4, 8, 16, 16, 10, -3, -24, -52, -82, +-108, -124, -124, -105, -72, -31, 6, 38, 60, 69, +61, 39, 8, -21, -47, -65, -71, -62, -40, -9, +24, 55, 79, 90, 84, 60, 26, -8, -35, -48, +-44, -26, -3, 19, 36, 47, 50, 40, 17, -14, +-49, -80, -106, -125, -134, -137, -136, -132, -125, -119, +-118, -123, -134, -149, -161, -166, -162, -149, -129, -110, +-93, -77, -63, -54, -56, -67, -82, -95, -101, -98, +-83, -57, -30, -6, 9, 19, 23, 20, 7, -12, +-32, -45, -47, -32, -1, 38, 81, 123, 163, 199, +227, 243, 247, 240, 230, 220, 214, 214, 220, 228, +232, 233, 228, 219, 206, 191, 173, 154, 134, 118, +108, 107, 110, 115, 124, 135, 148, 156, 154, 143, +124, 101, 76, 56, 43, 35, 28, 19, 10, 2, +-4, -14, -28, -47, -71, -93, -110, -118, -117, -112, +-110, -109, -110, -112, -115, -119, -125, -134, -147, -160, +-170, -172, -167, -159, -150, -141, -134, -128, -125, -126, +-133, -145, -156, -161, -154, -138, -120, -103, -86, -67, +-50, -37, -30, -28, -34, -47, -66, -84, -94, -95, +-88, -71, -50, -27, -10, -6, -15, -36, -66, -99, +-125, -141, -145, -140, -127, -104, -74, -42, -10, 14, +30, 34, 27, 13, -1, -14, -23, -25, -17, 0, +23, 49, 73, 92, 103, 109, 113, 119, 126, 133, +139, 149, 167, 191, 217, 240, 258, 266, 262, 245, +221, 197, 178, 163, 153, 147, 147, 150, 155, 156, +148, 128, 96, 60, 28, 3, -13, -22, -23, -16, +-5, 6, 15, 17, 10, -7, -34, -66, -99, -126, +-146, -158, -160, -158, -150, -139, -130, -129, -139, -158, +-179, -195, -203, -202, -191, -169, -139, -104, -68, -34, +-3, 18, 28, 29, 27, 25, 27, 34, 47, 66, +90, 115, 135, 144, 137, 113, 78, 42, 16, 2, +1, 11, 29, 49, 67, 79, 83, 80, 70, 55, +36, 16, 0, -11, -15, -14, -9, -2, 4, 8, +4, -10, -36, -64, -86, -98, -100, -92, -75, -54, +-32, -10, 9, 27, 41, 46, 39, 24, 3, -19, +-36, -43, -37, -18, 9, 41, 71, 96, 106, 100, +81, 58, 34, 12, -4, -12, -12, -5, 5, 18, +29, 36, 37, 29, 12, -13, -42, -73, -101, -123, +-137, -141, -138, -131, -126, -129, -135, -143, -150, -156, +-162, -167, -170, -169, -164, -153, -137, -119, -104, -94, +-89, -86, -83, -79, -73, -66, -58, -49, -38, -24, +-8, 4, 7, 2, -7, -18, -26, -29, -21, -1, +27, 62, 101, 139, 173, 201, 220, 228, 230, 228, +224, 219, 214, 207, 201, 200, 204, 210, 212, 207, +197, 183, 165, 144, 122, 103, 90, 84, 85, 94, +108, 123, 136, 141, 142, 136, 124, 106, 83, 59, +34, 13, 2, 1, 6, 11, 11, 6, -3, -15, +-31, -50, -69, -85, -98, -107, -110, -109, -104, -98, +-94, -91, -92, -94, -98, -105, -114, -123, -128, -124, +-115, -105, -100, -103, -111, -121, -132, -141, -146, -146, +-145, -145, -140, -128, -108, -81, -57, -42, -38, -48, +-66, -85, -100, -110, -113, -109, -94, -70, -45, -25, +-16, -20, -35, -62, -95, -128, -155, -169, -170, -158, +-133, -97, -56, -19, 9, 25, 27, 18, 3, -12, +-25, -33, -33, -22, -3, 17, 40, 62, 84, 103, +117, 125, 129, 128, 126, 127, 135, 153, 177, 204, +226, 241, 246, 240, 230, 217, 205, 192, 177, 163, +153, 147, 144, 141, 137, 131, 121, 104, 80, 55, +30, 11, -3, -11, -12, -6, 0, 0, -4, -17, +-33, -52, -70, -90, -108, -120, -125, -120, -113, -108, +-111, -123, -141, -161, -180, -193, -202, -205, -202, -194, +-175, -147, -114, -81, -50, -24, -6, 5, 14, 21, +29, 38, 48, 63, 84, 104, 120, 125, 121, 108, +88, 65, 45, 30, 21, 19, 19, 23, 30, 41, +50, 57, 58, 56, 50, 41, 32, 20, 11, 7, +8, 13, 16, 13, 0, -19, -42, -63, -75, -76, +-69, -59, -52, -48, -44, -35, -20, -1, 15, 24, +22, 14, 4, 0, -3, -4, -1, 7, 22, 42, +63, 83, 98, 103, 100, 90, 78, 66, 54, 40, +26, 14, 9, 8, 12, 17, 18, 15, 6, -7, +-25, -45, -65, -83, -97, -107, -114, -119, -124, -131, +-139, -146, -151, -152, -154, -157, -165, -174, -180, -181, +-174, -163, -151, -141, -131, -119, -102, -83, -69, -60, +-55, -52, -49, -45, -40, -32, -24, -21, -22, -24, +-23, -19, -10, 2, 19, 41, 66, 93, 121, 145, +165, 182, 197, 210, 219, 221, 217, 211, 206, 204, +206, 210, 212, 209, 198, 183, 167, 153, 141, 127, +113, 101, 93, 92, 98, 111, 124, 132, 135, 133, +126, 113, 95, 72, 50, 30, 16, 9, 13, 25, +38, 42, 38, 27, 12, -5, -27, -50, -71, -89, +-101, -105, -103, -97, -88, -78, -68, -63, -66, -75, +-86, -94, -95, -90, -83, -75, -74, -79, -89, -101, +-111, -119, -129, -142, -155, -166, -170, -163, -144, -121, +-100, -88, -82, -82, -86, -94, -105, -116, -123, -124, +-119, -103, -80, -55, -39, -34, -41, -57, -81, -111, +-143, -168, -182, -180, -161, -129, -90, -55, -27, -8, +0, 0, -7, -19, -32, -41, -43, -38, -23, 0, +25, 50, 72, 92, 109, 122, 129, 131, 129, 126, +127, 139, 159, 182, 201, 213, 221, 226, 226, 222, +214, 203, 188, 170, 155, 146, 144, 145, 146, 144, +140, 131, 117, 98, 78, 55, 33, 13, 2, -2, +-2, -1, -3, -8, -18, -31, -47, -61, -73, -81, +-83, -79, -70, -63, -66, -80, -100, -123, -144, -162, +-175, -188, -200, -206, -201, -181, -151, -118, -87, -61, +-39, -22, -9, 0, 12, 23, 32, 38, 47, 61, +76, 89, 97, 98, 94, 85, 70, 53, 33, 13, +-1, -8, -6, 1, 12, 23, 34, 43, 45, 41, +33, 24, 16, 9, 7, 7, 4, -3, -17, -33, +-45, -50, -49, -44, -39, -38, -44, -51, -51, -44, +-32, -20, -8, 1, 9, 13, 14, 14, 14, 14, +13, 14, 21, 34, 49, 65, 81, 97, 111, 122, +127, 123, 108, 81, 51, 26, 9, 0, -1, 2, +11, 18, 19, 14, 2, -15, -36, -55, -70, -80, +-89, -100, -113, -123, -130, -133, -131, -126, -127, -138, +-159, -184, -205, -218, -225, -224, -215, -199, -179, -157, +-132, -107, -87, -78, -76, -78, -80, -79, -74, -67, +-57, -45, -33, -19, -5, 5, 10, 12, 14, 20, +29, 43, 62, 89, 118, 148, 173, 192, 203, 205, +200, 193, 191, 195, 200, 203, 202, 196, 187, 180, +177, 173, 162, 143, 120, 99, 84, 76, 74, 81, +94, 110, 122, 130, 131, 125, 109, 85, 62, 43, +31, 26, 28, 34, 42, 49, 56, 63, 66, 60, +42, 16, -14, -46, -73, -91, -95, -87, -71, -53, +-38, -30, -28, -33, -40, -44, -45, -43, -41, -41, +-45, -54, -63, -70, -75, -81, -94, -112, -131, -148, +-162, -171, -173, -167, -155, -142, -130, -119, -110, -106, +-109, -117, -125, -130, -129, -122, -108, -91, -75, -64, +-59, -61, -73, -94, -120, -144, -162, -172, -171, -158, +-137, -109, -79, -50, -28, -15, -14, -22, -32, -41, +-45, -42, -32, -16, 1, 18, 37, 58, 79, 96, +107, 115, 122, 127, 131, 134, 139, 145, 151, 157, +165, 177, 192, 202, 205, 202, 194, 183, 170, 158, +146, 136, 128, 125, 128, 133, 134, 129, 120, 107, +91, 71, 50, 30, 12, -2, -12, -17, -20, -25, +-32, -39, -44, -45, -41, -33, -25, -23, -30, -44, +-60, -75, -92, -111, -133, -154, -171, -182, -185, -179, +-163, -143, -122, -100, -77, -54, -34, -18, -6, 3, +10, 19, 29, 41, 53, 65, 75, 86, 94, 98, +94, 84, 67, 44, 18, -3, -17, -19, -14, -4, +7, 19, 28, 33, 34, 34, 30, 23, 15, 6, +-3, -17, -33, -43, -46, -42, -35, -27, -22, -20, +-25, -34, -43, -48, -47, -45, -41, -35, -27, -18, +-9, 0, 8, 17, 22, 26, 30, 32, 33, 38, +52, 75, 103, 129, 147, 153, 144, 122, 92, 63, +39, 24, 15, 13, 17, 22, 26, 24, 17, 4, +-13, -32, -46, -57, -66, -77, -86, -89, -86, -84, +-85, -90, -103, -124, -152, -181, -204, -219, -228, -231, +-227, -215, -198, -178, -156, -134, -118, -109, -106, -106, +-108, -110, -111, -106, -93, -74, -52, -30, -12, 0, +4, 1, -3, -6, -3, 7, 27, 55, 87, 116, +140, 157, 166, 168, 166, 167, 173, 180, 186, 188, +190, 191, 192, 189, 186, 181, 169, 150, 127, 107, +92, 85, 85, 91, 102, 113, 120, 121, 117, 106, +90, 71, 58, 50, 49, 48, 48, 49, 55, 65, +78, 93, 100, 96, 77, 47, 14, -16, -37, -48, +-49, -44, -36, -29, -22, -17, -18, -24, -31, -32, +-27, -18, -11, -7, -6, -7, -14, -21, -29, -39, +-55, -78, -105, -129, -147, -160, -167, -167, -165, -161, +-157, -152, -146, -142, -141, -143, -142, -140, -136, -130, +-123, -114, -104, -95, -88, -84, -85, -94, -108, -125, +-142, -155, -161, -157, -145, -127, -107, -85, -65, -52, +-49, -54, -62, -67, -67, -61, -48, -31, -10, 9, +27, 43, 60, 77, 91, 103, 112, 120, 127, 133, +138, 142, 146, 149, 154, 164, 175, 185, 190, 192, +190, 185, 176, 164, 149, 135, 123, 115, 113, 117, +124, 129, 130, 124, 112, 96, 78, 60, 39, 18, +-1, -17, -27, -35, -43, -47, -47, -41, -32, -21, +-10, -4, -3, -11, -24, -40, -57, -76, -98, -120, +-139, -153, -161, -161, -155, -145, -131, -115, -96, -75, +-58, -45, -36, -26, -14, -1, 11, 23, 31, 39, +49, 62, 76, 89, 95, 90, 74, 53, 31, 12, +-2, -12, -19, -20, -16, -5, 8, 20, 28, 33, +33, 28, 18, 7, -5, -18, -33, -46, -53, -49, +-39, -27, -17, -12, -11, -13, -17, -22, -29, -38, +-49, -55, -55, -47, -34, -18, 0, 17, 33, 44, +48, 48, 46, 46, 53, 68, 92, 117, 139, 152, +155, 148, 135, 121, 106, 88, 68, 49, 37, 30, +26, 23, 18, 9, -3, -19, -35, -47, -55, -62, +-68, -71, -71, -71, -72, -80, -93, -113, -136, -160, +-184, -202, -218, -229, -236, -235, -227, -211, -192, -173, +-154, -141, -132, -129, -130, -132, -134, -134, -128, -113, +-90, -64, -40, -24, -14, -9, -6, -2, 1, 6, +13, 26, 46, 71, 94, 111, 124, 132, 137, 141, +147, 154, 159, 160, 160, 162, 167, 173, 176, 174, +166, 152, 135, 118, 105, 97, 97, 101, 107, 112, +112, 106, 94, 80, 69, 63, 60, 60, 58, 54, +48, 43, 46, 59, 80, 101, 115, 116, 105, 86, +64, 43, 24, 8, -4, -12, -15, -15, -13, -11, +-8, -6, -4, 0, 4, 11, 15, 15, 11, 7, +6, 6, 5, 0, -9, -27, -50, -75, -96, -115, +-131, -146, -159, -169, -176, -180, -180, -177, -170, -159, +-148, -138, -133, -131, -133, -136, -136, -133, -127, -120, +-113, -110, -110, -113, -117, -123, -129, -135, -139, -137, +-130, -119, -105, -92, -82, -79, -79, -77, -71, -60, +-50, -42, -34, -26, -14, 0, 20, 42, 66, 87, +105, 122, 135, 143, 144, 141, 137, 133, 131, 129, +129, 133, 142, 155, 169, 182, 187, 182, 166, 143, +120, 103, 96, 99, 110, 122, 132, 139, 140, 136, +123, 102, 76, 49, 24, 2, -15, -27, -35, -39, +-39, -32, -20, -6, 2, 7, 6, -1, -12, -26, +-37, -45, -53, -64, -77, -92, -107, -120, -128, -129, +-125, -118, -110, -102, -92, -78, -62, -44, -26, -9, +2, 8, 10, 11, 15, 24, 38, 53, 64, 70, +70, 68, 61, 49, 29, 8, -11, -25, -31, -30, +-21, -9, 2, 11, 17, 20, 19, 12, 0, -17, +-35, -50, -60, -59, -49, -35, -21, -9, 1, 8, +10, 5, -5, -19, -36, -52, -64, -68, -62, -49, +-31, -9, 13, 32, 45, 50, 50, 50, 53, 61, +75, 91, 108, 123, 138, 152, 161, 161, 151, 133, +110, 85, 63, 47, 40, 36, 31, 21, 7, -6, +-20, -32, -41, -47, -53, -56, -58, -58, -60, -67, +-78, -90, -103, -120, -140, -163, -185, -203, -216, -223, +-224, -219, -210, -200, -187, -172, -157, -145, -140, -140, +-145, -147, -145, -136, -121, -103, -85, -66, -47, -27, +-7, 9, 22, 31, 34, 34, 36, 45, 59, 74, +87, 98, 109, 120, 131, 143, 151, 156, 155, 152, +152, 153, 152, 147, 138, 128, 120, 114, 113, 118, +127, 132, 131, 123, 109, 91, 71, 54, 44, 42, +45, 50, 54, 55, 55, 58, 66, 80, 92, 99, +98, 92, 84, 75, 68, 63, 59, 54, 44, 33, +22, 14, 8, 3, 1, 4, 10, 17, 24, 31, +36, 37, 35, 34, 36, 37, 34, 27, 16, 5, +-7, -22, -36, -49, -67, -90, -116, -141, -163, -181, +-195, -201, -196, -183, -166, -148, -135, -131, -136, -144, +-152, -156, -158, -159, -159, -156, -149, -139, -127, -113, +-103, -100, -104, -110, -114, -117, -120, -122, -121, -118, +-111, -100, -85, -69, -56, -49, -45, -41, -33, -22, +-8, 8, 28, 47, 66, 85, 105, 124, 137, 144, +145, 141, 133, 121, 108, 102, 105, 116, 134, 151, +163, 163, 152, 135, 118, 105, 97, 93, 95, 101, +109, 120, 133, 141, 141, 126, 101, 72, 46, 24, +5, -8, -19, -25, -26, -20, -9, 0, 2, -2, +-10, -15, -16, -15, -12, -12, -17, -28, -41, -54, +-65, -74, -81, -86, -88, -87, -85, -81, -76, -70, +-61, -51, -39, -28, -20, -18, -18, -17, -11, -1, +12, 27, 41, 50, 53, 53, 51, 45, 32, 13, +-6, -22, -32, -35, -31, -21, -11, -4, 1, 5, +7, 0, -14, -34, -53, -66, -73, -71, -61, -48, +-33, -22, -11, -2, 4, 4, -1, -12, -26, -39, +-52, -61, -65, -63, -54, -38, -16, 5, 23, 35, +43, 51, 59, 67, 77, 88, 99, 110, 123, 140, +156, 164, 163, 153, 139, 124, 110, 98, 88, 77, +61, 41, 22, 7, -4, -16, -28, -39, -46, -50, +-51, -48, -45, -47, -56, -70, -86, -103, -120, -140, +-159, -175, -186, -193, -194, -195, -196, -198, -197, -190, +-180, -170, -165, -163, -164, -163, -159, -151, -139, -126, +-113, -98, -77, -53, -28, -6, 9, 19, 26, 31, +35, 43, 51, 59, 66, 75, 88, 104, 115, 120, +118, 114, 110, 110, 114, 120, 126, 127, 125, 122, +121, 123, 125, 127, 127, 125, 120, 112, 102, 89, +74, 59, 50, 45, 42, 38, 33, 31, 31, 36, +45, 57, 70, 78, 80, 80, 81, 85, 90, 93, +93, 87, 76, 63, 51, 41, 33, 27, 24, 29, +39, 50, 58, 61, 58, 53, 47, 42, 40, 42, +42, 40, 37, 33, 29, 23, 13, -3, -25, -52, +-82, -112, -140, -163, -182, -192, -193, -186, -174, -163, +-156, -156, -163, -174, -184, -191, -195, -198, -198, -192, +-178, -158, -136, -118, -106, -104, -111, -120, -127, -132, +-136, -138, -135, -127, -114, -100, -90, -84, -82, -83, +-84, -80, -69, -53, -34, -15, 6, 30, 55, 79, +100, 115, 125, 130, 132, 130, 126, 119, 113, 112, +119, 131, 142, 149, 148, 138, 125, 110, 101, 96, +95, 95, 97, 104, 114, 127, 138, 144, 143, 132, +113, 89, 63, 38, 18, 6, 4, 10, 19, 26, +28, 23, 11, -5, -19, -27, -28, -24, -20, -15, +-9, -4, -1, -2, -8, -18, -30, -43, -56, -65, +-72, -75, -73, -65, -51, -34, -20, -13, -17, -29, +-41, -48, -45, -33, -16, 0, 14, 24, 30, 36, +42, 45, 41, 29, 12, -4, -16, -24, -26, -25, +-20, -12, -3, 1, 1, -7, -23, -44, -64, -74, +-74, -67, -57, -46, -32, -15, 0, 12, 19, 17, +10, 0, -9, -17, -22, -27, -29, -30, -26, -18, +-8, 2, 11, 17, 23, 31, 41, 52, 64, 82, +100, 117, 134, 149, 159, 164, 164, 159, 153, 149, +145, 137, 124, 105, 84, 63, 42, 23, 7, -8, +-23, -35, -41, -45, -48, -51, -53, -53, -55, -59, +-65, -74, -88, -102, -112, -115, -114, -113, -125, -154, +-194, -237, -288, -357, -432, -488, -506, -483, -423, -340, +-257, -192, -149, -132, -133, -134, -111, -62, -1, 57, +105, 144, 179, 219, 255, 252, 187, 85, -28, -120, +-137, -71, 19, 72, 90, 122, 175, 235, 291, 325, +315, 267, 216, 211, 279, 404, 529, 596, 577, 495, +386, 271, 173, 104, 54, 8, -42, -79, -85, -64, +-19, 38, 75, 67, 11, -71, -150, -195, -198, -179, +-169, -173, -169, -133, -70, 0, 59, 88, 69, 10, +-64, -142, -219, -258, -216, -106, 19, 137, 250, 336, +362, 335, 286, 234, 168, 92, 25, -16, -6, 81, +220, 346, 407, 396, 331, 218, 86, -28, -125, -202, +-245, -259, -273, -299, -313, -303, -291, -310, -362, -437, +-513, -541, -502, -434, -374, -336, -326, -346, -378, -393, +-403, -445, -515, -585, -657, -743, -816, -825, -761, -659, +-544, -415, -284, -185, -123, -75, -7, 104, 239, 368, +484, 601, 739, 896, 1045, 1148, 1167, 1096, 961, 795, +616, 450, 335, 293, 310, 361, 414, 452, 476, 498, +519, 509, 440, 344, 274, 239, 224, 241, 292, 331, +314, 254, 186, 105, 9, -68, -119, -180, -293, -446, +-578, -659, -689, -659, -590, -526, -499, -516, -554, -590, +-603, -573, -515, -467, -427, -355, -221, -34, 173, 348, +456, 500, 507, 492, 460, 426, 402, 369, 315, 245, +153, 44, -49, -101, -144, -230, -332, -393, -404, -376, +-285, -118, 63, 180, 220, 218, 201, 179, 172, 200, +228, 203, 111, -12, -120, -199, -267, -330, -384, -440, +-511, -587, -645, -661, -627, -556, -462, -364, -271, -172, +-47, 104, 248, 342, 374, 352, 279, 184, 99, 25, +-57, -139, -195, -222, -233, -202, -98, 48, 178, 276, +354, 394, 391, 382, 407, 452, 468, 446, 402, 331, +244, 180, 180, 249, 345, 404, 388, 296, 151, -25, +-205, -342, -412, -433, -450, -471, -472, -428, -335, -214, +-108, -64, -80, -102, -95, -63, -14, 51, 116, 161, +200, 251, 291, 283, 224, 131, 5, -150, -294, -391, +-453, -482, -470, -425, -391, -403, -429, -418, -352, -239, +-96, 55, 185, 266, 293, 297, 329, 399, 472, 511, +492, 421, 311, 175, 46, -44, -87, -94, -77, -40, +8, 66, 133, 195, 225, 228, 247, 302, 384, 501, +658, 818, 931, 982, 985, 922, 790, 630, 467, 287, +83, -104, -237, -315, -337, -283, -163, -45, 2, -41, +-144, -252, -333, -375, -376, -338, -283, -242, -213, -161, +-63, 59, 176, 256, 277, 233, 145, 43, -52, -136, +-192, -206, -200, -206, -221, -221, -217, -237, -286, -349, +-409, -440, -389, -228, -14, 183, 343, 457, 506, 483, +420, 341, 231, 79, -86, -232, -346, -439, -504, -530, +-532, -550, -613, -709, -812, -894, -939, -926, -847, -725, +-607, -528, -480, -445, -413, -383, -361, -355, -387, -449, +-512, -565, -613, -645, -644, -638, -646, -645, -596, -494, +-367, -224, -84, 18, 96, 205, 371, 565, 750, 923, +1066, 1140, 1120, 1024, 894, 766, 663, 593, 546, 510, +471, 445, 469, 550, 651, 716, 724, 679, 599, 503, +426, 401, 421, 447, 446, 416, 369, 312, 256, 218, +197, 177, 158, 137, 103, 58, 23, 14, 2, -54, +-147, -245, -327, -378, -379, -334, -287, -266, -246, -201, +-135, -51, 68, 232, 408, 555, 651, 701, 724, 734, +731, 703, 634, 518, 375, 239, 125, 19, -102, -227, +-331, -409, -475, -520, -515, -457, -373, -296, -235, -202, +-196, -192, -180, -156, -115, -56, 1, 15, -35, -112, +-181, -254, -353, -477, -606, -722, -804, -818, -764, -686, +-621, -570, -520, -469, -413, -339, -222, -66, 99, 245, +350, 400, 389, 334, 264, 190, 99, -4, -86, -114, +-96, -52, 17, 110, 205, 261, 269, 250, 229, 212, +188, 133, 33, -93, -198, -237, -214, -139, -11, 143, +261, 288, 243, 160, 54, -65, -182, -288, -400, -510, +-579, -584, -537, -462, -391, -335, -316, -355, -428, -480, +-466, -380, -243, -71, 116, 283, 405, 484, 520, 486, +370, 204, 40, -83, -161, -184, -163, -132, -126, -160, +-218, -266, -278, -233, -139, -41, 31, 84, 129, 157, +173, 218, 307, 398, 435, 409, 339, 243, 151, 96, +79, 77, 70, 64, 79, 114, 146, 156, 155, 152, +150, 156, 186, 256, 364, 495, 643, 789, 899, 949, +934, 863, 735, 553, 344, 144, -17, -120, -148, -97, +6, 106, 155, 132, 39, -94, -218, -306, -358, -378, +-369, -347, -347, -362, -345, -257, -110, 48, 178, 255, +281, 263, 225, 188, 163, 143, 115, 79, 30, -41, +-128, -209, -264, -310, -360, -405, -432, -425, -365, -237, +-58, 121, 256, 342, 394, 426, 432, 397, 320, 206, +66, -76, -191, -264, -308, -355, -435, -568, -731, -872, +-952, -961, -901, -779, -635, -535, -510, -541, -581, -593, +-574, -530, -476, -422, -381, -360, -349, -345, -350, -369, +-393, -403, -403, -385, -333, -247, -153, -77, -8, 76, +181, 307, 454, 606, 735, 819, 861, 887, 915, 939, +948, 923, 856, 757, 647, 551, 484, 469, 512, 584, +632, 626, 578, 508, 429, 364, 341, 357, 363, 317, +210, 72, -59, -158, -200, -179, -108, -25, 39, 88, +124, 132, 98, 21, -92, -231, -369, -463, -494, -479, +-449, -416, -388, -370, -359, -336, -270, -155, -13, 127, +258, 380, 499, 621, 733, 810, 828, 767, 625, 412, +186, 6, -109, -190, -264, -336, -410, -487, -554, -585, +-564, -500, -423, -371, -361, -384, -422, -450, -432, -363, +-270, -187, -132, -104, -116, -171, -262, -372, -492, -600, +-670, -689, -660, -600, -528, -460, -421, -429, -470, -494, +-462, -365, -226, -72, 76, 209, 328, 421, 477, 499, +486, 434, 332, 214, 129, 108, 149, 233, 347, 463, +544, 561, 520, 451, 390, 335, 265, 172, 63, -37, +-94, -76, 12, 132, 233, 298, 338, 358, 359, 336, +282, 183, 39, -117, -244, -315, -333, -308, -263, -237, +-264, -349, -456, -543, -574, -532, -433, -299, -138, 34, +185, 289, 352, 387, 380, 311, 188, 55, -51, -115, +-144, -152, -152, -164, -211, -281, -336, -342, -299, -220, +-122, -29, 36, 73, 102, 133, 158, 171, 170, 161, +137, 102, 70, 62, 75, 95, 111, 119, 108, 70, +27, 10, 22, 42, 47, 31, 11, 18, 79, 186, +317, 457, 585, 678, 714, 700, 664, 610, 522, 402, +271, 169, 117, 106, 118, 141, 160, 150, 100, 17, +-70, -142, -184, -189, -177, -186, -231, -281, -294, -249, +-151, -25, 100, 192, 255, 315, 393, 479, 540, 555, +509, 402, 249, 84, -53, -148, -202, -237, -277, -327, +-369, -384, -369, -330, -269, -181, -81, 9, 82, 152, +232, 310, 349, 332, 271, 183, 71, -59, -190, -313, +-442, -590, -752, -903, -1012, -1042, -980, -852, -720, -645, +-637, -676, -727, -762, -768, -741, -692, -635, -578, -522, +-472, -437, -406, -375, -359, -370, -410, -469, -509, -492, +-408, -289, -173, -69, 23, 94, 140, 173, 209, 262, +332, 417, 518, 642, 773, 868, 897, 871, 813, 732, +643, 577, 544, 536, 536, 529, 509, 471, 428, 409, +423, 455, 463, 413, 301, 147, -15, -148, -212, -196, +-125, -26, 74, 164, 232, 282, 308, 304, 260, 167, +33, -108, -214, -267, -286, -286, -273, -243, -206, -182, +-170, -152, -102, -19, 84, 209, 369, 556, 736, 881, +970, 982, 906, 760, 584, 423, 306, 234, 184, 121, +16, -128, -269, -359, -377, -344, -302, -286, -315, -378, +-436, -450, -410, -330, -237, -160, -107, -78, -81, -122, +-190, -264, -341, -425, -505, -557, -565, -548, -528, -527, +-538, -556, -580, -607, -616, -576, -499, -423, -352, -257, +-113, 71, 267, 436, 543, 568, 527, 453, 380, 331, +322, 358, 424, 493, 533, 533, 504, 455, 397, 347, +315, 282, 229, 152, 69, 3, -20, 7, 68, 146, +230, 300, 334, 328, 308, 283, 231, 135, 7, -120, +-218, -291, -359, -434, -510, -593, -690, -777, -812, -780, +-708, -621, -529, -429, -317, -191, -59, 61, 153, 205, +208, 159, 69, -30, -100, -112, -88, -86, -134, -224, +-321, -382, -379, -301, -176, -51, 41, 87, 106, 120, +126, 109, 75, 41, 19, 15, 28, 66, 129, 197, +241, 238, 202, 162, 127, 86, 39, -4, -50, -102, +-143, -146, -102, -20, 76, 164, 228, 263, 286, 310, +346, 388, 427, 458, 472, 452, 394, 323, 273, 256, +254, 246, 213, 156, 92, 27, -35, -84, -104, -109, +-119, -133, -141, -144, -143, -127, -79, 11, 137, 278, +421, 562, 688, 763, 749, 656, 514, 347, 175, 29, +-69, -137, -204, -277, -345, -389, -403, -391, -366, -341, +-322, -301, -253, -165, -44, 88, 217, 331, 406, 417, +356, 237, 86, -69, -220, -375, -528, -666, -775, -833, +-825, -761, -673, -606, -580, -592, -616, -637, -654, -669, +-678, -676, -660, -623, -544, -420, -290, -200, -166, -168, +-199, -252, -301, -311, -272, -203, -130, -72, -32, -17, +-21, -31, -30, -11, 27, 96, 193, 308, 428, 548, +665, 767, 830, 831, 771, 682, 601, 544, 518, 518, +523, 517, 501, 491, 494, 496, 471, 406, 303, 182, +69, -26, -93, -118, -99, -61, -23, 27, 109, 212, +310, 386, 421, 391, 291, 144, -7, -121, -188, -225, +-250, -273, -292, -300, -291, -263, -222, -175, -115, -20, +115, 279, 442, 584, 688, 747, 756, 722, 665, 601, +532, 459, 385, 302, 202, 81, -37, -131, -197, -245, +-289, -335, -374, -401, -419, -427, -407, -351, -292, -264, +-261, -269, -279, -291, -307, -325, -343, -359, -372, -383, +-396, -418, -456, -502, -543, -568, -590, -617, -647, -674, +-691, -682, -632, -535, -413, -283, -149, 0, 163, 316, +430, 489, 504, 493, 490, 516, 561, 591, 579, 522, +445, 380, 339, 312, 290, 274, 255, 213, 150, 96, +73, 75, 84, 90, 103, 137, 191, 252, 315, 375, +425, 442, 410, 329, 206, 55, -105, -258, -400, -529, +-632, -693, -704, -683, -659, -641, -617, -570, -501, -413, +-304, -182, -72, 7, 56, 80, 92, 105, 120, 133, +131, 96, 19, -88, -187, -256, -290, -274, -194, -68, +54, 136, 173, 180, 167, 127, 60, -18, -84, -126, +-145, -136, -86, 0, 99, 183, 233, 239, 201, 130, +45, -43, -126, -188, -208, -180, -125, -72, -35, -7, +15, 21, 10, -1, 12, 73, 174, 291, 391, 448, +455, 424, 388, 376, 384, 383, 353, 295, 219, 132, +54, 13, 18, 41, 47, 22, -14, -46, -71, -91, +-86, -28, 86, 240, 409, 574, 716, 813, 852, 838, +777, 676, 544, 402, 260, 123, -1, -93, -143, -168, +-195, -231, -274, -317, -362, -410, -449, -450, -386, -256, +-86, 84, 225, 306, 313, 259, 167, 49, -90, -235, +-367, -478, -578, -676, -759, -798, -781, -727, -673, -635, +-617, -626, -666, -722, -765, -785, -787, -773, -732, -655, +-549, -437, -341, -278, -250, -244, -233, -197, -149, -111, +-90, -82, -89, -113, -145, -168, -173, -161, -141, -117, +-83, -19, 77, 200, 350, 517, 657, 732, 737, 696, +642, 595, 573, 581, 606, 632, 636, 607, 558, 508, +452, 381, 301, 233, 186, 148, 112, 74, 32, -9, +-35, -26, 25, 108, 200, 282, 340, 363, 347, 301, +244, 178, 102, 23, -49, -110, -162, -210, -248, -257, +-223, -152, -65, 28, 118, 190, 245, 304, 387, 480, +552, 586, 587, 567, 538, 506, 470, 438, 403, 342, +244, 123, 5, -103, -201, -275, -314, -324, -319, -304, +-279, -249, -229, -238, -283, -350, -424, -478, -485, -445, +-388, -347, -325, -315, -301, -285, -278, -295, -336, -396, +-473, -554, -619, -658, -681, -692, -686, -660, -624, -579, +-507, -390, -228, -47, 122, 267, 393, 501, 582, 628, +652, 660, 643, 587, 507, 422, 339, 261, 203, 175, +172, 176, 178, 180, 180, 163, 118, 54, -4, -38, +-31, 27, 138, 278, 412, 508, 550, 529, 443, 295, +113, -70, -230, -362, -469, -555, -630, -701, -750, -753, +-712, -659, -624, -609, -592, -546, -469, -377, -283, -183, +-76, 19, 86, 134, 170, 184, 157, 93, 15, -50, +-90, -96, -63, -1, 69, 132, 183, 221, 238, 225, +185, 123, 37, -59, -139, -168, -128, -35, 72, 170, +245, 285, 287, 258, 217, 169, 115, 63, 31, 22, +18, 9, -2, -18, -46, -92, -153, -201, -200, -140, +-49, 45, 142, 236, 312, 358, 386, 414, 445, 464, +454, 409, 339, 259, 186, 140, 122, 115, 98, 62, +14, -38, -79, -89, -56, 12, 96, 182, 275, 386, +507, 619, 704, 758, 777, 752, 691, 604, 504, 392, +281, 191, 123, 65, -2, -87, -174, -240, -291, -352, +-424, -473, -463, -393, -281, -146, -12, 86, 128, 130, +117, 102, 80, 30, -55, -169, -295, -414, -504, -556, +-582, -592, -594, -594, -599, -616, -645, -674, -696, -717, +-743, -761, -753, -719, -672, -618, -550, -464, -363, -256, +-150, -55, 16, 59, 66, 45, 6, -50, -129, -208, +-261, -287, -308, -336, -352, -329, -265, -167, -36, 115, +261, 367, 418, 433, 442, 468, 514, 579, 648, 696, +700, 655, 573, 475, 381, 312, 272, 242, 199, 139, +85, 56, 43, 19, -18, -49, -61, -53, -23, 29, +97, 167, 232, 285, 323, 349, 355, 326, 263, 175, +65, -52, -149, -184, -145, -64, 17, 78, 115, 125, +121, 124, 160, 226, 294, 333, 340, 340, 361, 412, +487, 567, 618, 611, 552, 456, 334, 193, 49, -67, +-141, -178, -189, -176, -145, -128, -154, -225, -312, -389, +-450, -495, -531, -556, -564, -546, -500, -429, -346, -272, +-225, -208, -212, -246, -324, -435, -540, -607, -632, -635, +-629, -625, -633, -657, -681, -667, -584, -430, -236, -31, +160, 325, 456, 560, 646, 710, 735, 717, 658, 568, +453, 335, 254, 230, 247, 268, 283, 296, 298, 278, +227, 150, 56, -30, -82, -70, 18, 163, 314, 418, +467, 475, 453, 399, 321, 233, 135, 9, -148, -320, +-471, -573, -620, -622, -599, -572, -573, -614, -672, -712, +-712, -661, -566, -444, -318, -207, -109, -19, 62, 129, +176, 214, 248, 259, 242, 216, 206, 212, 226, 246, +276, 311, 334, 328, 276, 185, 76, -33, -124, -177, +-175, -131, -70, -2, 76, 148, 191, 201, 203, 220, +251, 273, 260, 209, 135, 52, -27, -85, -124, -169, +-239, -325, -400, -441, -436, -374, -266, -144, -38, 43, +120, 200, 264, 300, 314, 315, 304, 284, 271, 268, +260, 228, 168, 99, 42, 11, 6, 17, 39, 70, +101, 128, 165, 231, 322, 418, 500, 565, 609, 623, +603, 567, 544, 537, 522, 476, 403, 315, 213, 98, +-13, -110, -190, -256, -308, -347, -380, -411, -427, -406, +-353, -293, -242, -194, -150, -122, -112, -104, -97, -104, +-141, -202, -273, -337, -389, -436, -486, -536, -579, -612, +-634, -638, -628, -624, -646, -689, -733, -763, -776, -770, +-734, -651, -526, -389, -258, -128, 3, 124, 208, 249, +240, 178, 73, -46, -148, -219, -261, -286, -300, -311, +-312, -282, -206, -100, -4, 57, 96, 139, 203, 296, +416, 549, 667, 737, 749, 717, 668, 614, 548, 467, +379, 297, 228, 179, 162, 174, 191, 183, 146, 96, +51, 11, -26, -45, -28, 30, 111, 196, 283, 369, +438, 470, 455, 397, 310, 215, 138, 97, 91, 108, +143, 196, 245, 269, 262, 237, 204, 164, 128, 114, +126, 157, 203, 264, 350, 462, 575, 645, 650, 594, +498, 381, 267, 179, 117, 66, 17, -28, -64, -86, +-111, -160, -233, -313, -402, -507, -619, -703, -738, -729, +-689, -622, -532, -435, -351, -294, -266, -270, -311, -373, +-434, -480, -518, -546, -563, -586, -639, -715, -777, -794, +-754, -662, -529, -370, -201, -32, 130, 286, 437, 564, +641, 659, 633, 577, 503, 430, 367, 326, 306, 307, +322, 341, 353, 334, 264, 157, 59, 1, -19, -15, +12, 62, 124, 176, 215, 244, 262, 271, 271, 261, +225, 143, 21, -114, -240, -344, -408, -426, -419, -422, +-460, -528, -609, -675, -712, -712, -671, -598, -518, -455, +-406, -345, -255, -132, 6, 139, 242, 305, 333, 343, +352, 364, 367, 348, 322, 306, 302, 289, 256, 210, +158, 100, 38, -12, -41, -55, -74, -104, -127, -130, +-106, -43, 55, 165, 252, 305, 323, 307, 253, 173, +87, 4, -76, -161, -252, -337, -404, -452, -480, -471, +-409, -309, -199, -104, -31, 23, 70, 119, 176, 242, +311, 369, 401, 403, 380, 331, 259, 186, 142, 129, +130, 129, 136, 164, 208, 256, 304, 350, 387, 411, +426, 441, 452, 451, 445, 457, 500, 565, 635, 682, +676, 594, 451, 292, 163, 83, 37, 1, -38, -87, +-152, -229, -299, -341, -355, -354, -352, -351, -345, -325, +-289, -242, -187, -127, -77, -51, -51, -70, -110, -185, +-286, -384, -455, -495, -512, -510, -495, -488, -509, -554, +-605, -653, -695, -722, -723, -701, -661, -596, -490, -344, +-175, -5, 139, 238, 276, 242, 155, 43, -66, -163, +-240, -284, -292, -286, -288, -308, -338, -359, -356, -325, +-271, -195, -96, 14, 126, 239, 357, 468, 551, 597, +611, 594, 537, 441, 328, 232, 167, 133, 130, 151, +179, 194, 191, 172, 131, 68, 0, -53, -77, -70, +-38, 12, 73, 138, 202, 267, 335, 394, 416, 390, +330, 265, 220, 214, 251, 316, 375, 398, 373, 314, +243, 179, 121, 67, 28, 25, 63, 131, 220, 320, +410, 470, 496, 509, 525, 537, 525, 487, 430, 361, +283, 207, 140, 83, 28, -26, -85, -164, -268, -387, +-498, -583, -636, -662, -661, -637, -595, -546, -496, -438, +-371, -309, -263, -235, -228, -247, -295, -364, -436, -501, +-559, -619, -681, -732, -756, -745, -696, -597, -453, -285, +-120, 34, 186, 332, 448, 512, 531, 525, 505, 481, +462, 457, 463, 465, 456, 432, 385, 322, 257, 205, +171, 147, 125, 107, 100, 102, 103, 102, 106, 114, +118, 117, 124, 142, 159, 161, 138, 86, 14, -65, +-145, -214, -268, -318, -380, -452, -514, -555, -581, -605, +-628, -648, -665, -682, -689, -658, -576, -460, -334, -205, +-67, 73, 203, 314, 399, 454, 482, 492, 483, 449, +388, 313, 251, 218, 215, 223, 226, 214, 170, 88, +-15, -108, -173, -210, -218, -191, -127, -30, 87, 206, +300, 350, 351, 308, 234, 146, 54, -46, -155, -260, +-349, -415, -461, -473, -444, -382, -320, -280, -251, -211, +-157, -90, -9, 84, 179, 261, 322, 357, 370, 365, +351, 329, 301, 265, 229, 214, 232, 275, 321, 367, +419, 470, 500, 498, 467, 415, 353, 301, 277, 298, +364, 456, 548, 613, 636, 610, 539, 442, 345, 268, +214, 175, 144, 110, 60, -9, -90, -161, -215, -272, +-348, -433, -500, -540, -546, -520, -457, -362, -254, -158, +-96, -81, -110, -164, -221, -263, -293, -323, -357, -392, +-428, -465, -494, -511, -529, -566, -624, -690, -737, -751, +-731, -686, -618, -520, -387, -230, -69, 74, 172, 204, +169, 92, 6, -62, -106, -126, -134, -151, -199, -275, +-347, -392, -407, -404, -383, -342, -280, -205, -116, -7, +120, 251, 368, 456, 503, 503, 462, 399, 332, 270, +218, 191, 194, 214, 233, 244, 244, 229, 200, 163, +125, 93, 67, 39, 5, -29, -43, -26, 19, 85, +162, 248, 326, 376, 391, 384, 378, 383, 410, 463, +530, 573, 563, 505, 420, 327, 237, 163, 118, 100, +97, 100, 106, 120, 140, 169, 210, 268, 337, 402, +457, 494, 503, 481, 440, 391, 335, 267, 191, 107, +16, -81, -188, -297, -395, -468, -513, -543, -569, -601, +-640, -680, -704, -686, -612, -495, -375, -290, -246, -238, +-259, -297, -338, -376, -419, -478, -549, -618, -672, -700, +-693, -645, -557, -439, -305, -165, -34, 72, 148, 203, +248, 287, 319, 349, 379, 404, 423, 432, 432, 415, +377, 323, 264, 219, 194, 182, 173, 164, 157, 154, +149, 139, 122, 98, 59, 5, -45, -65, -40, 12, +72, 124, 149, 125, 52, -47, -140, -203, -239, -260, +-283, -313, -352, -396, -438, -482, -535, -596, -647, -672, +-666, -625, -544, -430, -295, -146, 11, 176, 339, 484, +583, 621, 598, 530, 443, 366, 325, 323, 342, 356, +345, 310, 255, 188, 109, 23, -59, -140, -219, -284, +-301, -255, -157, -27, 111, 233, 312, 332, 294, 220, +132, 41, -51, -142, -222, -286, -328, -349, -361, -379, +-399, -404, -383, -343, -297, -248, -191, -125, -50, 26, +97, 160, 212, 252, 286, 315, 338, 343, 331, 311, +304, 331, 393, 474, 548, 594, 599, 558, 491, 429, +384, 351, 323, 307, 309, 330, 362, 404, 455, 503, +526, 511, 464, 408, 360, 326, 304, 282, 248, 201, +146, 80, -7, -121, -253, -386, -508, -602, -653, -651, +-602, -532, -469, -424, -388, -350, -301, -246, -197, -170, +-170, -197, -244, -299, -345, -379, -412, -450, -490, -530, +-572, -608, -629, -631, -622, -605, -577, -526, -452, -366, +-274, -175, -76, 5, 55, 75, 76, 68, 55, 35, +-3, -68, -149, -222, -278, -322, -359, -391, -409, -411, +-396, -364, -308, -222, -119, -14, 78, 151, 197, 216, +215, 207, 209, 229, 258, 273, 262, 235, 204, 181, +180, 201, 227, 240, 232, 213, 190, 163, 123, 69, +12, -35, -65, -66, -27, 52, 152, 247, 329, 399, +462, 527, 595, 653, 685, 684, 658, 616, 562, 496, +424, 361, 311, 263, 208, 150, 95, 53, 23, 8, +12, 43, 101, 180, 267, 356, 442, 511, 549, 550, +520, 460, 371, 260, 139, 22, -81, -165, -226, -261, +-290, -333, -400, -480, -560, -635, -692, -717, -701, -641, +-546, -440, -347, -278, -236, -213, -212, -232, -269, -318, +-370, -421, -469, -507, -519, -500, -454, -394, -332, -271, +-209, -143, -78, -15, 49, 118, 182, 229, 269, 313, +360, 401, 429, 436, 416, 376, 327, 285, 264, 259, +256, 250, 244, 244, 245, 235, 205, 145, 54, -55, +-152, -205, -198, -141, -61, 4, 40, 49, 42, 24, +-4, -47, -94, -132, -153, -166, -184, -218, -270, -340, +-419, -499, -575, -638, -687, -721, -732, -700, -607, -457, +-270, -70, 125, 295, 415, 476, 490, 477, 449, 418, +393, 381, 380, 373, 355, 328, 298, 261, 209, 145, +71, -12, -105, -199, -278, -321, -307, -232, -112, 19, +129, 194, 209, 183, 132, 76, 30, -4, -42, -92, +-162, -239, -306, -354, -387, -410, -419, -415, -399, -372, +-330, -275, -219, -173, -133, -86, -21, 57, 132, 195, +244, 286, 321, 357, 408, 477, 551, 606, 632, 629, +603, 566, 533, 511, 498, 482, 450, 398, 337, 286, +266, 279, 312, 347, 375, 396, 410, 415, 411, 403, +398, 405, 424, 440, 429, 375, 270, 120, -53, -216, +-346, -441, -508, -553, -579, -588, -583, -566, -536, -487, +-423, -354, -286, -218, -159, -124, -121, -146, -183, -223, +-260, -298, -345, -405, -466, -517, -545, -539, -497, -434, +-374, -342, -339, -350, -352, -330, -281, -204, -109, -16, +56, 98, 107, 90, 60, 28, -8, -54, -109, -171, +-238, -308, -372, -421, -445, -437, -396, -323, -234, -153, +-104, -89, -87, -78, -55, -10, 55, 127, 185, 214, +212, 190, 164, 147, 144, 154, 171, 193, 213, 227, +233, 231, 223, 204, 161, 88, 2, -76, -126, -135, +-95, -8, 116, 262, 408, 533, 626, 685, 713, 713, +695, 672, 649, 621, 586, 542, 491, 443, 389, 322, +244, 164, 86, 14, -40, -68, -65, -36, 20, 112, +240, 387, 518, 602, 619, 573, 483, 370, 257, 156, +69, -6, -74, -137, -194, -240, -280, -325, -391, -479, +-576, -659, -710, -721, -698, -645, -565, -474, -391, -327, +-286, -276, -297, -336, -374, -395, -391, -371, -343, -317, +-295, -285, -288, -292, -278, -243, -194, -141, -85, -32, +16, 61, 105, 156, 212, 267, 308, 331, 335, 324, +298, 268, 240, 230, 245, 278, 315, 340, 347, 332, +296, 240, 162, 64, -37, -122, -180, -204, -192, -150, +-94, -46, -18, -15, -31, -50, -64, -71, -70, -64, +-62, -77, -105, -140, -186, -256, -351, -461, -571, -662, +-717, -719, -658, -544, -400, -252, -115, 8, 124, 230, +320, 390, 434, 454, 451, 432, 410, 396, 382, 361, +331, 296, 264, 237, 205, 149, 63, -38, -130, -194, +-222, -215, -185, -143, -96, -51, -12, 20, 48, 63, +58, 37, 8, -28, -77, -135, -197, -260, -318, -365, +-391, -396, -383, -361, -338, -313, -288, -265, -249, -240, +-230, -206, -163, -101, -20, 82, 205, 331, 444, 536, +602, 645, 665, 666, 654, 637, 628, 634, 642, 641, +621, 580, 522, 451, 378, 317, 286, 289, 309, 324, +331, 340, 357, 390, 442, 506, 561, 586, 569, 512, +423, 312, 191, 74, -35, -137, -238, -336, -426, -499, +-552, -593, -622, -636, -623, -577, -510, -433, -351, -268, +-199, -157, -148, -167, -205, -250, -305, -372, -443, -492, +-497, -454, -378, -299, -242, -223, -238, -280, -334, -374, +-377, -341, -282, -209, -133, -67, -21, 3, 15, 20, +16, 0, -34, -89, -164, -249, -324, -369, -380, -367, +-348, -334, -322, -311, -299, -295, -296, -291, -272, -235, +-183, -120, -57, -4, 30, 41, 34, 25, 33, 61, +95, 124, 145, 167, 196, 235, 267, 276, 251, 189, +90, -32, -145, -211, -212, -149, -37, 102, 242, 364, +462, 542, 610, 669, 711, 730, 730, 720, 706, 687, +661, 631, 592, 538, 461, 367, 266, 163, 59, -34, +-104, -135, -119, -59, 35, 148, 263, 360, 423, 445, +434, 404, 362, 312, 250, 173, 87, 4, -65, -125, +-173, -208, -237, -282, -350, -436, -524, -599, -650, -663, +-636, -577, -508, -453, -425, -419, -419, -408, -375, -321, +-255, -192, -150, -136, -143, -158, -172, -181, -183, -172, +-147, -111, -70, -36, -13, 0, 8, 23, 53, 105, +166, 212, 228, 218, 199, 193, 218, 268, 324, 363, +383, 380, 360, 333, 309, 291, 259, 202, 118, 24, +-62, -132, -181, -212, -220, -210, -193, -175, -155, -132, +-106, -82, -59, -34, -11, 0, -1, -22, -61, -128, +-222, -331, -436, -517, -562, -566, -542, -501, -446, -381, +-309, -228, -135, -27, 87, 197, 291, 355, 391, 409, +418, 421, 422, 419, 408, 377, 326, 265, 207, 167, +142, 122, 97, 58, 1, -72, -147, -200, -218, -207, +-182, -151, -119, -91, -70, -56, -45, -43, -58, -100, +-161, -224, -275, -312, -340, -361, -371, -367, -348, -313, +-278, -254, -257, -295, -352, -401, -414, -368, -262, -116, +34, 170, 291, 402, 501, 583, 640, 667, 669, 659, +651, 657, 677, 700, 708, 694, 658, 601, 525, 439, +357, 288, 238, 204, 190, 201, 239, 296, 359, 420, +477, 519, 533, 514, 468, 407, 332, 244, 142, 31, +-75, -177, -271, -356, -431, -497, -554, -600, -635, -654, +-646, -599, -514, -412, -315, -240, -197, -188, -207, -247, +-293, -337, -371, -392, -391, -360, -304, -238, -176, -130, +-115, -140, -195, -257, -298, -309, -295, -263, -222, -176, +-130, -88, -51, -21, -2, -5, -34, -84, -134, -169, +-189, -203, -216, -228, -241, -256, -275, -294, -315, -332, +-344, -351, -356, -351, -325, -277, -219, -163, -122, -90, +-63, -36, -9, 21, 58, 96, 131, 168, 215, 264, +303, 317, 304, 265, 203, 124, 41, -24, -60, -61, +-25, 43, 138, 242, 337, 418, 491, 564, 637, 696, +730, 741, 739, 735, 730, 724, 711, 679, 621, 536, +429, 313, 207, 120, 50, -5, -47, -64, -47, 5, +79, 153, 215, 264, 299, 322, 337, 343, 331, 288, +213, 122, 34, -38, -90, -125, -147, -171, -213, -279, +-358, -431, -483, -512, -524, -531, -545, -575, -616, -644, +-638, -586, -501, -400, -300, -208, -136, -91, -77, -86, +-108, -127, -139, -144, -140, -128, -107, -83, -62, -53, +-50, -42, -26, -11, -5, -8, -6, 9, 40, 89, +152, 220, 277, 314, 327, 325, 315, 299, 282, 268, +251, 223, 177, 114, 43, -31, -106, -175, -225, -248, +-247, -236, -226, -218, -203, -174, -130, -76, -25, 11, +22, 2, -44, -106, -167, -223, -274, -322, -361, -382, +-379, -363, -350, -349, -345, -321, -269, -188, -87, 22, +119, 191, 242, 289, 343, 400, 440, 449, 424, 372, +305, 244, 211, 215, 241, 266, 270, 247, 195, 118, +23, -70, -147, -197, -225, -237, -236, -225, -201, -168, +-133, -108, -98, -103, -124, -161, -211, -265, -309, -329, +-322, -294, -256, -215, -191, -202, -251, -322, -392, -446, +-468, -446, -372, -259, -128, 0, 123, 243, 358, 459, +543, 610, 658, 686, 693, 691, 696, 714, 741, 762, +764, 737, 678, 587, 482, 382, 305, 258, 234, 226, +234, 258, 297, 341, 385, 424, 452, 465, 461, 441, +407, 360, 305, 233, 141, 35, -64, -145, -214, -287, +-373, -470, -562, -631, -661, -639, -571, -487, -416, -371, +-346, -337, -340, -349, -359, -363, -360, -349, -327, -293, +-249, -202, -160, -125, -95, -76, -75, -103, -152, -202, +-236, -243, -230, -204, -173, -146, -130, -128, -133, -139, +-143, -144, -145, -147, -147, -144, -142, -151, -179, -221, +-262, -293, -312, -326, -340, -357, -381, -407, -422, -410, +-373, -325, -279, -241, -214, -197, -184, -159, -110, -39, +37, 104, 156, 193, 214, 212, 192, 163, 134, 107, +85, 66, 53, 51, 61, 81, 110, 151, 208, 281, +365, 444, 508, 560, 607, 652, 694, 728, 755, 774, +774, 744, 685, 609, 529, 453, 387, 328, 274, 216, +153, 93, 49, 25, 16, 20, 38, 74, 121, 172, +219, 259, 286, 291, 266, 218, 163, 109, 53, -4, +-62, -113, -149, -173, -190, -205, -226, -259, -307, -376, +-463, -558, -645, -703, -719, -688, -608, -491, -356, -232, +-141, -82, -43, -16, -2, -6, -23, -44, -62, -70, +-57, -22, 17, 40, 34, 6, -32, -76, -118, -145, +-146, -120, -74, -20, 40, 104, 167, 218, 249, 262, +259, 245, 225, 206, 197, 193, 187, 166, 122, 61, +-4, -67, -123, -174, -224, -267, -294, -294, -266, -218, +-159, -98, -50, -24, -23, -40, -66, -98, -135, -168, +-190, -202, -206, -206, -201, -198, -206, -226, -248, -258, +-248, -224, -185, -127, -54, 28, 108, 186, 258, 317, +351, 355, 332, 297, 262, 239, 229, 236, 258, 289, +316, 324, 303, 252, 179, 92, 2, -80, -149, -202, +-242, -273, -290, -285, -253, -203, -158, -139, -149, -178, +-214, -243, -256, -253, -235, -215, -197, -186, -187, -208, +-253, -317, -383, -435, -465, -467, -437, -375, -289, -191, +-88, 23, 141, 256, 356, 438, 503, 557, 600, 636, +668, 699, 728, 752, 760, 740, 691, 621, 541, 466, +402, 353, 319, 299, 285, 271, 259, 257, 274, 303, +334, 363, 387, 401, 403, 393, 371, 337, 288, 227, +156, 77, -7, -103, -203, -295, -370, -426, -463, -477, +-470, -450, -432, -426, -433, -444, -452, -452, -439, -411, +-370, -323, -278, -239, -204, -164, -116, -64, -21, 0, +-6, -27, -51, -69, -83, -93, -95, -96, -109, -140, +-179, -213, -234, -240, -232, -214, -191, -164, -136, -110, +-95, -101, -132, -178, -222, -255, -282, -309, -340, -375, +-413, -449, -470, -468, -445, -418, -401, -401, -410, -415, +-403, -364, -298, -208, -108, -16, 52, 87, 89, 76, +61, 59, 72, 92, 113, 129, 136, 132, 129, 139, +168, 208, 246, 277, 307, 342, 390, 454, 528, 607, +680, 740, 786, 813, 818, 798, 752, 695, 636, 582, +538, 500, 465, 424, 370, 299, 216, 135, 69, 23, +2, 1, 17, 42, 70, 102, 135, 172, 203, 214, +196, 150, 82, 9, -47, -80, -90, -82, -63, -50, +-59, -96, -157, -239, -342, -460, -576, -667, -719, -724, +-689, -618, -523, -414, -304, -198, -105, -28, 19, 34, +23, -2, -23, -28, -10, 26, 60, 70, 45, -9, +-76, -134, -170, -183, -180, -167, -146, -122, -92, -55, +-9, 41, 94, 143, 179, 194, 192, 180, 165, 150, +142, 144, 147, 131, 89, 25, -49, -120, -180, -225, +-250, -249, -229, -199, -164, -129, -101, -95, -109, -128, +-138, -134, -119, -99, -81, -68, -61, -54, -45, -31, +-21, -24, -47, -84, -124, -154, -162, -140, -89, -18, +57, 122, 166, 187, 194, 196, 203, 210, 211, 207, +207, 217, 235, 258, 282, 303, 310, 300, 272, 232, +177, 104, 14, -83, -172, -243, -292, -316, -316, -302, +-291, -294, -304, -308, -298, -273, -243, -215, -191, -177, +-180, -200, -228, -255, -280, -309, -345, -387, -427, -456, +-460, -435, -380, -304, -218, -126, -37, 43, 121, 209, +305, 403, 498, 583, 651, 697, 720, 726, 722, 708, +677, 635, 589, 552, 524, 500, 477, 451, 411, 356, +301, 264, 253, 263, 280, 294, 306, 322, 347, 377, +402, 415, 406, 369, 299, 207, 116, 39, -23, -76, +-128, -180, -230, -276, -319, -362, -409, -455, -495, -527, +-547, -553, -535, -494, -436, -373, -312, -254, -200, -154, +-113, -75, -38, -11, 4, 17, 34, 53, 71, 81, +81, 60, 9, -65, -148, -221, -274, -304, -311, -295, +-258, -213, -168, -134, -111, -97, -94, -106, -130, -162, +-197, -237, -279, -320, -358, -390, -417, -442, -470, -498, +-518, -529, -531, -527, -513, -478, -416, -334, -246, -172, +-120, -93, -89, -95, -96, -77, -41, 1, 44, 82, +113, 145, 180, 221, 258, 279, 278, 263, 254, 265, +303, 363, 438, 518, 591, 645, 679, 701, 719, 724, +708, 675, 637, 607, 593, 590, 589, 576, 544, 491, +417, 329, 232, 145, 79, 34, 5, -9, -11, 4, +35, 71, 101, 122, 126, 107, 67, 20, -19, -41, +-45, -32, -10, 7, 10, -7, -44, -96, -167, -260, +-370, -482, -572, -630, -654, -645, -602, -528, -430, -324, +-218, -121, -48, -3, 14, 23, 35, 59, 90, 117, +130, 120, 90, 40, -23, -92, -150, -185, -195, -190, +-184, -181, -176, -164, -143, -113, -68, -15, 30, 57, +67, 71, 80, 97, 119, 137, 144, 130, 88, 26, +-38, -89, -122, -143, -155, -156, -149, -140, -135, -138, +-148, -167, -194, -219, -231, -223, -197, -159, -118, -78, +-39, 3, 50, 89, 113, 116, 95, 56, 9, -35, +-61, -59, -33, 5, 42, 72, 90, 89, 76, 64, +65, 83, 109, 133, 156, 180, 204, 228, 251, 277, +306, 325, 322, 296, 257, 212, 160, 96, 22, -54, +-129, -198, -254, -300, -340, -374, -396, -395, -366, -314, +-252, -196, -161, -151, -164, -190, -217, -241, -264, -285, +-307, -335, -369, -400, -411, -394, -355, -303, -249, -199, +-157, -117, -67, 5, 104, 218, 332, 436, 526, 597, +643, 662, 660, 645, 624, 600, 579, 568, 570, 574, +569, 551, 518, 477, 431, 385, 340, 294, 249, 211, +194, 206, 245, 300, 351, 383, 383, 351, 298, 238, +183, 138, 107, 90, 78, 55, 14, -41, -110, -186, +-265, -340, -407, -467, -521, -564, -588, -582, -544, -478, +-393, -302, -222, -164, -128, -103, -74, -35, 3, 37, +68, 98, 130, 157, 170, 156, 110, 34, -57, -147, +-217, -263, -289, -302, -306, -301, -281, -244, -199, -159, +-137, -137, -154, -182, -217, -250, -272, -284, -297, -323, +-364, -419, -481, -542, -590, -617, -622, -606, -573, -529, +-477, -426, -381, -345, -312, -283, -260, -244, -230, -207, +-173, -131, -85, -31, 36, 115, 194, 258, 293, 300, +289, 273, 269, 285, 320, 369, 420, 467, 507, 539, +566, 591, 611, 618, 612, 599, 585, 576, 577, 597, +633, 668, 687, 675, 627, 549, 451, 346, 256, 187, +137, 100, 68, 42, 21, 6, -3, -4, 0, 5, +5, 0, 2, 15, 37, 57, 69, 68, 60, 45, +24, -3, -44, -103, -183, -277, -373, -451, -501, -520, +-510, -483, -447, -403, -347, -281, -210, -141, -73, -11, +40, 82, 114, 134, 144, 139, 118, 82, 38, -12, +-65, -108, -136, -148, -148, -144, -136, -129, -123, -119, +-114, -103, -86, -69, -51, -27, 7, 50, 89, 111, +109, 83, 42, -3, -42, -64, -69, -67, -62, -58, +-59, -66, -81, -102, -135, -179, -227, -268, -297, -314, +-314, -291, -245, -181, -111, -44, 14, 61, 96, 118, +129, 130, 120, 104, 91, 89, 98, 115, 129, 131, +117, 88, 51, 17, 1, 8, 28, 52, 75, 101, +133, 170, 206, 235, 255, 264, 262, 254, 249, 244, +234, 213, 176, 118, 36, -59, -159, -254, -339, -402, +-434, -435, -411, -373, -329, -288, -258, -245, -248, -259, +-271, -283, -300, -317, -333, -345, -349, -346, -334, -314, +-289, -261, -232, -203, -177, -154, -129, -85, -14, 82, +191, 296, 387, 458, 506, 531, 539, 541, 537, 529, +521, 518, 526, 545, 572, 600, 612, 600, 565, 513, +450, 379, 308, 249, 214, 208, 223, 250, 276, 290, +281, 248, 204, 163, 134, 123, 131, 154, 176, 182, +160, 114, 52, -16, -88, -163, -238, -314, -392, -465, +-520, -544, -531, -488, -432, -372, -312, -257, -208, -165, +-125, -87, -48, -4, 47, 102, 152, 192, 213, 210, +181, 131, 71, 9, -51, -110, -168, -217, -250, -268, +-272, -261, -242, -226, -217, -213, -213, -214, -220, -228, +-235, -239, -250, -279, -330, -396, -467, -534, -586, -613, +-609, -579, -540, -505, -482, -467, -456, -446, -433, -418, +-405, -398, -391, -378, -351, -308, -245, -166, -77, 12, +94, 165, 221, 258, 282, 299, 320, 350, 384, 419, +455, 485, 504, 513, 517, 522, 529, 531, 524, 513, +503, 499, 505, 531, 578, 637, 689, 715, 706, 661, +589, 503, 422, 363, 326, 292, 245, 182, 108, 37, +-22, -62, -78, -75, -57, -30, 2, 33, 55, 65, +65, 55, 38, 23, 13, 6, -6, -34, -77, -127, +-175, -220, -262, -299, -330, -354, -375, -387, -379, -350, +-297, -225, -139, -51, 25, 80, 111, 126, 133, 131, +117, 92, 62, 25, -18, -67, -105, -122, -118, -102, +-86, -78, -85, -107, -138, -168, -189, -191, -172, -136, +-94, -57, -33, -24, -32, -57, -92, -124, -137, -129, +-108, -83, -61, -44, -35, -33, -39, -52, -79, -124, +-184, -247, -302, -343, -363, -356, -319, -262, -201, -147, +-99, -53, -5, 40, 84, 129, 173, 208, 228, 235, +234, 229, 220, 203, 178, 141, 97, 49, 8, -21, +-34, -31, -13, 16, 52, 86, 112, 130, 136, 134, +134, 145, 172, 206, 237, 256, 252, 215, 145, 52, +-46, -138, -213, -267, -300, -314, -317, -317, -312, -301, +-285, -273, -277, -296, -324, -350, -371, -382, -374, -350, +-320, -293, -272, -254, -233, -210, -187, -169, -155, -142, +-122, -88, -33, 38, 118, 196, 266, 323, 368, 403, +428, 443, 442, 431, 421, 421, 436, 469, 515, 564, +602, 616, 602, 562, 506, 443, 381, 330, 294, 273, +256, 238, 217, 197, 174, 145, 117, 100, 96, 102, +114, 135, 163, 192, 210, 207, 179, 127, 56, -25, +-109, -190, -264, -330, -382, -414, -426, -419, -398, -368, +-337, -307, -271, -223, -165, -100, -35, 25, 80, 127, +166, 197, 222, 236, 232, 208, 165, 114, 59, 6, +-40, -78, -108, -137, -172, -209, -239, -262, -279, -290, +-289, -277, -259, -243, -230, -220, -219, -238, -284, -355, +-437, -512, -566, -587, -580, -555, -527, -504, -487, -477, +-471, -465, -462, -468, -487, -513, -534, -535, -512, -464, +-394, -311, -225, -144, -72, -6, 59, 123, 185, 244, +301, 354, 397, 433, 463, 488, 505, 510, 504, 499, +494, 484, 464, 439, 420, 413, 423, 448, 489, 540, +587, 617, 622, 607, 579, 550, 527, 506, 479, 435, +371, 289, 194, 93, 2, -69, -113, -130, -123, -98, +-61, -19, 15, 37, 45, 38, 16, -13, -40, -58, +-68, -76, -85, -91, -96, -105, -125, -152, -183, -216, +-254, -294, -320, -320, -291, -235, -163, -81, -5, 53, +88, 105, 112, 118, 122, 122, 109, 78, 34, -9, +-40, -50, -45, -34, -30, -44, -74, -114, -151, -176, +-188, -189, -181, -164, -144, -126, -116, -115, -123, -139, +-160, -177, -179, -165, -142, -116, -87, -54, -23, -2, +3, -1, -21, -61, -118, -183, -241, -285, -311, -314, +-296, -262, -225, -193, -165, -132, -86, -26, 48, 126, +193, 244, 276, 292, 297, 295, 288, 274, 250, 212, +161, 108, 63, 32, 12, 3, 3, 11, 21, 27, +29, 27, 23, 19, 22, 42, 85, 142, 197, 237, +252, 233, 179, 102, 20, -51, -111, -162, -206, -239, +-258, -265, -263, -256, -248, -248, -264, -296, -338, -382, +-412, -420, -403, -370, -333, -300, -274, -256, -244, -233, +-218, -197, -172, -146, -116, -81, -36, 13, 66, 118, +167, 211, 249, 281, 310, 332, 341, 337, 333, 341, +362, 396, 437, 481, 520, 542, 539, 518, 492, 470, +456, 444, 429, 402, 356, 295, 227, 165, 118, 89, +76, 71, 69, 72, 87, 119, 167, 217, 251, 258, +234, 183, 117, 50, -9, -59, -104, -147, -186, -221, +-254, -286, -313, -332, -341, -336, -313, -266, -201, -131, +-70, -21, 23, 68, 113, 152, 186, 208, 211, 195, +166, 138, 120, 111, 105, 95, 72, 29, -29, -99, +-165, -222, -259, -273, -268, -252, -236, -224, -217, -217, +-227, -251, -290, -340, -399, -462, -515, -548, -560, -557, +-542, -523, -502, -484, -474, -476, -488, -511, -547, -585, +-608, -605, -577, -533, -483, -430, -374, -319, -263, -197, +-114, -18, 79, 170, 250, 316, 369, 413, 452, 489, +521, 544, 554, 547, 524, 493, 462, 442, 436, 437, +443, 453, 466, 483, 500, 520, 541, 562, 577, 589, +598, 602, 595, 567, 512, 434, 337, 231, 127, 39, +-25, -69, -97, -105, -88, -53, -14, 15, 26, 17, +-11, -55, -96, -120, -120, -104, -82, -61, -46, -41, +-44, -56, -76, -105, -140, -174, -203, -219, -216, -190, +-144, -86, -29, 15, 48, 73, 91, 105, 113, 116, +111, 94, 67, 36, 13, 0, -3, -7, -18, -38, +-69, -105, -134, -152, -160, -165, -174, -184, -194, -206, +-221, -231, -233, -235, -239, -247, -250, -242, -221, -190, +-154, -118, -86, -61, -49, -50, -63, -87, -116, -148, +-180, -211, -236, -251, -255, -254, -253, -250, -237, -207, +-156, -84, 1, 93, 178, 246, 295, 327, 350, 364, +366, 357, 335, 298, 250, 201, 162, 134, 112, 90, +70, 53, 36, 14, -10, -34, -49, -52, -41, -12, +27, 74, 116, 147, 160, 155, 133, 97, 51, 1, +-51, -99, -134, -154, -164, -172, -180, -193, -212, -237, +-271, -313, -356, -397, -426, -435, -422, -390, -353, -322, +-296, -278, -264, -250, -227, -190, -145, -104, -70, -40, +-9, 20, 48, 73, 100, 128, 154, 178, 197, 214, +229, 244, 264, 288, 315, 342, 367, 388, 407, 420, +431, 445, 462, 478, 493, 499, 492, 468, 421, 356, +283, 213, 155, 109, 77, 55, 41, 36, 45, 76, +126, 182, 225, 245, 241, 211, 164, 113, 70, 39, +12, -15, -46, -79, -117, -160, -204, -244, -270, -277, +-267, -238, -196, -150, -105, -62, -17, 27, 72, 111, +139, 150, 146, 134, 123, 119, 121, 126, 132, 132, +119, 88, 34, -33, -105, -168, -215, -244, -252, -251, +-248, -248, -253, -258, -267, -282, -308, -343, -387, -435, +-480, -511, -524, -525, -516, -498, -473, -448, -435, -441, +-466, -502, -542, -578, -604, -613, -604, -583, -555, -523, +-489, -451, -402, -336, -252, -155, -50, 53, 147, 225, +285, 336, 385, 437, 485, 519, 532, 525, 505, 483, +466, 460, 464, 468, 462, 444, 418, 396, 384, 391, +417, 453, 488, 520, 549, 575, 592, 589, 564, 517, +453, 370, 272, 172, 84, 16, -26, -41, -31, -6, +21, 40, 39, 17, -22, -68, -109, -140, -157, -157, +-140, -110, -78, -50, -35, -28, -24, -20, -22, -31, +-46, -64, -78, -83, -72, -46, -12, 20, 44, 57, +62, 63, 64, 73, 86, 95, 96, 90, 81, 68, +47, 19, -12, -38, -56, -68, -74, -74, -76, -86, +-105, -133, -165, -199, -229, -256, -282, -305, -322, -331, +-330, -315, -285, -245, -196, -150, -119, -109, -118, -135, +-152, -160, -158, -149, -141, -144, -160, -184, -207, -223, +-231, -233, -224, -204, -173, -129, -71, 0, 75, 149, +218, 279, 331, 367, 383, 382, 366, 341, 312, 285, +266, 255, 244, 226, 197, 157, 109, 62, 23, 0, +-12, -14, -12, -9, -5, 0, 8, 24, 41, 51, +48, 32, 3, -31, -64, -86, -90, -81, -72, -75, +-95, -127, -167, -212, -259, -308, -353, -396, -430, -452, +-456, -444, -424, -403, -379, -351, -320, -286, -247, -203, +-158, -111, -62, -14, 28, 64, 91, 108, 115, 119, +123, 129, 140, 155, 175, 196, 218, 237, 248, 253, +255, 260, 272, 291, 318, 352, 390, 423, 450, 469, +478, 472, 445, 397, 338, 275, 212, 154, 105, 69, +46, 34, 37, 56, 89, 124, 149, 160, 155, 140, +119, 99, 86, 80, 78, 73, 59, 33, 0, -36, +-66, -92, -114, -132, -143, -143, -130, -104, -66, -22, +23, 61, 86, 97, 97, 93, 91, 95, 105, 118, +131, 142, 151, 157, 153, 133, 96, 50, 2, -43, +-86, -124, -150, -169, -191, -220, -251, -281, -306, -329, +-353, -380, -409, -437, -457, -468, -469, -464, -455, -448, +-444, -444, -446, -452, -463, -480, -504, -527, -544, -552, +-554, -553, -550, -548, -543, -532, -510, -472, -415, -337, +-241, -134, -22, 82, 172, 247, 309, 363, 404, 431, +449, 463, 476, 485, 494, 503, 509, 503, 475, 432, +382, 338, 311, 303, 314, 341, 380, 424, 468, 507, +539, 562, 569, 555, 514, 450, 371, 291, 221, 164, +126, 105, 97, 97, 97, 90, 74, 49, 11, -36, +-87, -131, -164, -180, -177, -158, -131, -106, -87, -71, +-52, -30, -11, 3, 15, 22, 24, 25, 33, 50, +70, 80, 74, 55, 30, 11, 5, 14, 33, 59, +79, 89, 82, 61, 33, 3, -23, -44, -55, -55, +-43, -30, -23, -27, -43, -71, -109, -154, -205, -257, +-302, -339, -366, -379, -377, -358, -326, -288, -247, -210, +-188, -182, -191, -204, -212, -211, -195, -166, -134, -111, +-106, -117, -135, -150, -162, -173, -182, -186, -179, -159, +-122, -68, 2, 81, 158, 223, 273, 309, 334, 350, +355, 353, 349, 350, 354, 355, 348, 326, 291, 245, +193, 139, 91, 55, 33, 18, 4, -9, -25, -40, +-52, -56, -53, -49, -51, -62, -77, -91, -99, -94, +-73, -45, -20, -12, -26, -56, -93, -132, -173, -220, +-270, -320, -366, -403, -432, -447, -449, -439, -423, -404, +-379, -346, -304, -255, -201, -143, -82, -21, 36, 82, +112, 126, 128, 122, 113, 108, 114, 132, 159, 187, +210, 220, 211, 187, 161, 147, 154, 178, 215, 260, +305, 347, 381, 410, 434, 450, 448, 420, 369, 307, +247, 198, 162, 137, 119, 106, 101, 102, 108, 114, +115, 107, 90, 70, 57, 56, 66, 81, 93, 97, +93, 84, 71, 58, 45, 32, 16, -2, -21, -33, +-32, -19, 7, 42, 79, 102, 102, 84, 62, 49, +52, 67, 90, 110, 123, 125, 120, 113, 108, 106, +99, 82, 56, 28, 0, -24, -49, -78, -115, -161, +-213, -268, -321, -367, -405, -433, -451, -460, -460, -457, +-449, -440, -435, -433, -439, -453, -474, -496, -511, -519, +-523, -527, -530, -534, -541, -549, -557, -560, -561, -563, +-564, -553, -521, -460, -372, -264, -149, -38, 56, 129, +184, 230, 271, 311, 346, 375, 400, 427, 456, 484, +502, 504, 484, 445, 398, 356, 326, 310, 304, 307, +316, 333, 361, 398, 439, 474, 495, 500, 485, 453, +408, 362, 322, 290, 266, 247, 231, 210, 184, 153, +123, 96, 64, 24, -23, -72, -115, -147, -167, -171, +-160, -139, -116, -94, -71, -43, -9, 28, 64, 95, +121, 143, 160, 172, 174, 165, 140, 106, 68, 38, +24, 28, 46, 66, 77, 75, 61, 40, 17, -4, +-21, -31, -36, -37, -34, -26, -15, -7, -7, -20, +-53, -105, -169, -230, -279, -315, -340, -359, -367, -358, +-336, -306, -276, -252, -241, -243, -257, -273, -278, -266, +-240, -210, -186, -167, -155, -145, -137, -130, -127, -129, +-134, -142, -146, -139, -113, -68, -10, 45, 94, 134, +168, 197, 224, 249, 274, 296, 318, 338, 353, 358, +350, 329, 302, 272, 241, 209, 180, 157, 139, 121, +97, 67, 31, -5, -42, -76, -100, -114, -121, -128, +-139, -149, -145, -124, -88, -47, -15, -2, -12, -38, +-69, -100, -125, -149, -178, -217, -266, -316, -358, -387, +-406, -418, -427, -433, -433, -422, -393, -343, -276, -201, +-126, -57, 0, 45, 73, 88, 93, 91, 88, 88, +99, 125, 159, 191, 210, 212, 197, 168, 136, 112, +103, 113, 137, 169, 206, 244, 284, 321, 352, 375, +381, 367, 336, 292, 246, 207, 183, 175, 175, 179, +183, 183, 175, 155, 125, 90, 58, 37, 27, 29, +37, 49, 58, 62, 65, 70, 78, 87, 93, 95, +92, 84, 74, 70, 77, 95, 119, 141, 157, 163, +155, 136, 113, 99, 101, 115, 131, 140, 134, 119, +101, 90, 88, 96, 108, 115, 113, 100, 82, 65, +53, 39, 13, -32, -96, -170, -241, -305, -355, -389, +-411, -422, -424, -419, -411, -404, -403, -411, -430, -458, +-491, -521, -541, -550, -553, -555, -558, -557, -550, -539, +-531, -529, -533, -542, -553, -560, -552, -518, -455, -368, +-269, -169, -82, -11, 43, 85, 121, 156, 195, 240, +288, 332, 368, 396, 416, 431, 436, 434, 425, 409, +389, 367, 344, 322, 301, 288, 288, 298, 316, 335, +351, 360, 360, 352, 333, 312, 300, 297, 297, 293, +278, 254, 222, 190, 164, 146, 133, 115, 81, 33, +-21, -73, -113, -134, -140, -138, -134, -128, -119, -100, +-71, -29, 21, 78, 133, 183, 222, 248, 258, 251, +229, 199, 170, 148, 139, 140, 142, 138, 126, 105, +85, 66, 48, 30, 10, -7, -22, -32, -37, -32, +-21, -9, -5, -16, -42, -87, -146, -211, -268, -309, +-332, -340, -339, -334, -329, -323, -316, -305, -297, -295, +-304, -317, -329, -331, -322, -301, -276, -252, -231, -215, +-200, -186, -174, -161, -148, -132, -113, -88, -56, -16, +24, 62, 93, 117, 136, 154, 172, 194, 223, 258, +289, 310, 320, 320, 315, 307, 298, 285, 269, 251, +232, 218, 212, 208, 197, 175, 140, 92, 36, -24, +-81, -130, -167, -194, -208, -208, -194, -169, -135, -101, +-75, -62, -61, -63, -68, -75, -86, -106, -133, -166, +-198, -226, -251, -275, -302, -336, -371, -401, -420, -423, +-405, -363, -302, -229, -154, -88, -35, 3, 26, 39, +50, 63, 78, 91, 101, 110, 124, 143, 161, 172, +169, 149, 119, 90, 74, 74, 90, 116, 146, 175, +200, 221, 238, 251, 254, 245, 225, 199, 179, 170, +172, 179, 187, 191, 191, 189, 182, 169, 147, 121, +94, 72, 53, 34, 19, 14, 17, 24, 33, 40, +46, 51, 56, 67, 83, 107, 135, 163, 189, 211, +227, 237, 241, 234, 217, 198, 181, 176, 179, 183, +182, 171, 150, 124, 99, 81, 71, 71, 76, 82, +89, 98, 111, 126, 136, 132, 105, 56, -10, -84, +-160, -231, -291, -334, -358, -368, -374, -381, -386, -391, +-394, -402, -417, -439, -465, -495, -524, -549, -564, -568, +-563, -556, -548, -546, -547, -549, -550, -553, -561, -567, +-561, -534, -482, -409, -326, -248, -184, -134, -94, -56, +-10, 43, 105, 168, 224, 269, 303, 330, 352, 368, +380, 388, 397, 403, 405, 400, 389, 374, 356, 335, +313, 292, 275, 263, 254, 249, 248, 254, 265, 281, +299, 319, 331, 335, 326, 306, 278, 249, 224, 206, +190, 171, 143, 105, 58, 8, -37, -76, -107, -132, +-157, -175, -179, -165, -129, -74, -4, 73, 146, 205, +246, 269, 276, 273, 263, 255, 247, 236, 222, 208, +198, 192, 184, 166, 141, 109, 73, 37, 9, -6, +-11, -9, -7, -5, -5, -4, -8, -21, -49, -94, +-149, -202, -244, -270, -281, -283, -283, -285, -294, -306, +-316, -319, -318, -321, -332, -350, -368, -382, -385, -375, +-353, -327, -302, -282, -266, -251, -235, -214, -186, -148, +-104, -58, -13, 31, 69, 95, 108, 112, 118, 130, +148, 171, 200, 232, 264, 290, 307, 310, 303, 292, +282, 275, 270, 267, 268, 272, 279, 282, 279, 266, +235, 183, 112, 29, -51, -119, -168, -197, -210, -212, +-209, -202, -188, -167, -142, -118, -100, -90, -86, -91, +-105, -122, -139, -151, -163, -176, -191, -211, -238, -273, +-315, -358, -393, -410, -402, -368, -311, -245, -179, -124, +-84, -54, -29, -4, 22, 50, 74, 90, 101, 111, +124, 142, 160, 171, 167, 145, 115, 84, 63, 55, +61, 77, 99, 117, 126, 127, 129, 134, 139, 142, +141, 140, 140, 143, 150, 160, 173, 184, 192, 193, +188, 178, 162, 142, 117, 88, 55, 25, 2, -7, +-9, -7, -4, -2, -2, 0, 8, 27, 63, 114, +174, 233, 278, 306, 317, 318, 314, 309, 300, 290, +281, 273, 266, 257, 245, 229, 210, 180, 140, 98, +64, 43, 36, 39, 55, 81, 112, 141, 164, 171, +156, 115, 53, -20, -97, -167, -223, -262, -286, -305, +-325, -346, -366, -379, -384, -387, -393, -408, -435, -472, +-511, -542, -563, -570, -566, -558, -551, -548, -548, -546, +-543, -540, -538, -533, -521, -497, -460, -413, -359, -306, +-261, -226, -195, -158, -112, -57, 2, 62, 117, 160, +190, 209, 226, 242, 261, 279, 296, 313, 330, 350, +369, 384, 389, 379, 350, 304, 249, 193, 150, 128, +126, 140, 162, 189, 218, 248, 275, 295, 306, 304, +291, 269, 245, 224, 210, 200, 189, 171, 143, 103, +59, 19, -15, -53, -97, -144, -177, -185, -162, -113, +-43, 34, 109, 170, 217, 252, 279, 300, 313, 314, +307, 295, 280, 266, 253, 239, 220, 195, 163, 125, +84, 47, 20, 7, 5, 9, 14, 17, 14, 4, +-12, -34, -64, -100, -137, -170, -195, -214, -227, -237, +-247, -260, -275, -291, -300, -302, -301, -308, -326, -349, +-369, -383, -387, -381, -367, -348, -330, -319, -313, -308, +-294, -263, -217, -162, -107, -56, -11, 28, 64, 94, +115, 127, 131, 128, 126, 134, 157, 191, 227, 257, +272, 272, 260, 246, 238, 236, 239, 243, 249, 261, +280, 305, 325, 332, 314, 265, 187, 96, 13, -49, +-93, -124, -151, -176, -199, -215, -217, -206, -185, -163, +-146, -137, -135, -139, -145, -150, -151, -148, -144, -142, +-147, -162, -187, -220, -257, -293, -320, -335, -331, -312, +-282, -244, -202, -158, -114, -71, -35, -4, 24, 49, +69, 83, 93, 104, 116, 129, 139, 143, 137, 120, +95, 72, 61, 65, 79, 96, 108, 107, 94, 74, +55, 43, 39, 41, 48, 59, 74, 89, 105, 121, +137, 152, 161, 164, 160, 154, 148, 142, 134, 117, +90, 58, 26, 2, -15, -26, -36, -46, -56, -64, +-59, -30, 24, 95, 168, 233, 283, 315, 333, 346, +357, 368, 372, 368, 361, 354, 347, 339, 329, 313, +289, 251, 200, 143, 91, 52, 29, 24, 36, 64, +101, 140, 170, 182, 170, 136, 88, 34, -22, -75, +-122, -162, -197, -231, -267, -300, -328, -348, -359, -364, +-366, -373, -391, -420, -454, -486, -513, -531, -542, -548, +-552, -559, -567, -567, -553, -531, -506, -485, -467, -448, +-425, -397, -365, -331, -301, -275, -251, -226, -195, -153, +-99, -39, 18, 63, 95, 114, 126, 137, 148, 165, +187, 218, 258, 304, 352, 394, 420, 421, 393, 339, +271, 200, 142, 106, 90, 87, 92, 106, 130, 163, +199, 231, 252, 263, 262, 250, 237, 227, 223, 223, +221, 214, 200, 179, 153, 119, 76, 26, -24, -67, +-96, -108, -102, -82, -46, 0, 53, 105, 154, 198, +238, 275, 306, 329, 344, 350, 347, 339, 327, 311, +289, 257, 217, 172, 125, 86, 62, 58, 66, 78, +84, 76, 55, 22, -15, -51, -81, -107, -131, -156, +-177, -192, -201, -204, -209, -219, -236, -258, -277, -290, +-299, -308, -320, -338, -356, -374, -387, -396, -403, -408, +-414, -418, -415, -400, -373, -334, -286, -231, -175, -120, +-67, -17, 29, 69, 99, 118, 127, 128, 129, 136, +153, 176, 200, 219, 228, 225, 212, 194, 176, 165, +163, 172, 193, 226, 267, 308, 337, 348, 337, 300, +244, 176, 110, 51, 3, -35, -68, -99, -128, -156, +-177, -190, -195, -194, -192, -189, -189, -190, -188, -180, +-165, -147, -137, -139, -152, -172, -191, -206, -214, -217, +-219, -224, -231, -234, -231, -218, -196, -166, -133, -99, +-66, -35, -3, 26, 50, 68, 81, 91, 99, 103, +104, 100, 90, 77, 64, 59, 65, 83, 106, 128, +137, 129, 104, 69, 32, 0, -24, -39, -45, -39, +-23, 0, 24, 51, 75, 95, 107, 114, 117, 116, +114, 116, 119, 121, 116, 103, 84, 60, 32, 3, +-24, -47, -63, -71, -68, -47, -8, 45, 106, 166, +217, 256, 290, 322, 356, 386, 410, 425, 433, 437, +437, 433, 428, 418, 399, 365, 313, 249, 183, 127, +89, 71, 70, 83, 101, 120, 134, 138, 131, 113, +88, 55, 15, -27, -68, -101, -125, -147, -173, -203, +-233, -259, -280, -297, -310, -324, -341, -363, -389, -417, +-446, -473, -502, -532, -564, -591, -605, -600, -577, -543, +-510, -479, -451, -425, -400, -374, -348, -323, -301, -284, +-270, -252, -227, -192, -147, -99, -53, -16, 12, 30, +40, 41, 39, 39, 50, 77, 119, 172, 231, 287, +333, 360, 363, 340, 295, 233, 167, 110, 68, 45, +39, 45, 60, 81, 107, 135, 160, 178, 184, 179, +172, 170, 178, 194, 211, 222, 221, 204, 179, 150, +121, 94, 67, 41, 16, -4, -21, -28, -23, -5, +22, 56, 93, 134, 179, 226, 272, 312, 340, 358, +364, 364, 362, 356, 344, 320, 286, 242, 197, 161, +141, 139, 145, 147, 136, 111, 78, 41, 3, -33, +-68, -102, -132, -156, -172, -183, -188, -192, -196, -202, +-212, -226, -242, -257, -270, -280, -286, -287, -289, -295, +-311, -337, -371, -405, -433, -449, -449, -435, -407, -367, +-321, -270, -220, -171, -125, -79, -32, 12, 58, 101, +136, 160, 172, 178, 184, 198, 218, 238, 247, 238, +213, 181, 154, 139, 140, 152, 171, 196, 225, 254, +279, 296, 300, 288, 262, 222, 178, 138, 103, 74, +46, 13, -25, -67, -106, -137, -159, -175, -190, -200, +-206, -208, -204, -194, -181, -172, -172, -183, -199, -215, +-224, -222, -208, -187, -167, -155, -155, -162, -173, -179, +-175, -162, -142, -121, -99, -75, -46, -12, 19, 45, +62, 71, 75, 74, 68, 56, 43, 35, 39, 53, +74, 97, 117, 131, 136, 130, 111, 79, 39, -4, +-46, -78, -96, -99, -91, -75, -53, -25, 4, 30, +48, 55, 53, 48, 48, 57, 76, 98, 115, 120, +113, 92, 61, 28, 0, -22, -38, -47, -52, -47, +-28, 4, 49, 97, 145, 190, 235, 280, 325, 366, +401, 429, 449, 463, 470, 473, 476, 477, 467, 440, +396, 343, 289, 240, 199, 171, 153, 142, 134, 128, +122, 116, 110, 103, 90, 67, 37, 4, -27, -53, +-72, -89, -108, -133, -164, -199, -235, -267, -288, -299, +-304, -309, -321, -342, -374, -416, -464, -515, -561, -596, +-613, -611, -591, -562, -524, -482, -442, -408, -384, -364, +-345, -326, -307, -289, -270, -251, -229, -204, -172, -135, +-97, -67, -51, -49, -56, -63, -63, -50, -24, 7, +44, 83, 127, 178, 232, 280, 311, 317, 294, 252, +202, 152, 110, 76, 52, 40, 39, 49, 65, 82, +96, 107, 112, 115, 121, 133, 153, 174, 193, 203, +201, 187, 170, 154, 142, 132, 127, 124, 121, 114, +101, 83, 66, 53, 46, 46, 55, 79, 118, 169, +224, 277, 323, 363, 393, 406, 399, 375, 343, 312, +284, 257, 231, 208, 194, 192, 198, 202, 198, 181, +151, 108, 58, 7, -38, -77, -109, -135, -156, -169, +-172, -166, -156, -154, -166, -193, -226, -256, -277, -285, +-282, -272, -266, -271, -293, -327, -365, -402, -432, -454, +-468, -469, -455, -424, -381, -333, -286, -244, -205, -166, +-123, -76, -27, 21, 66, 105, 137, 163, 187, 207, +221, 225, 219, 205, 182, 158, 138, 127, 125, 128, +137, 151, 171, 194, 216, 233, 242, 241, 231, 213, +191, 165, 141, 118, 97, 77, 53, 23, -13, -52, +-93, -131, -165, -193, -211, -219, -217, -210, -202, -198, +-202, -218, -240, -261, -273, -270, -248, -212, -172, -141, +-125, -122, -127, -134, -137, -134, -125, -114, -102, -83, +-56, -22, 16, 52, 78, 90, 85, 68, 46, 28, +19, 19, 25, 35, 49, 65, 85, 106, 121, 126, +117, 95, 63, 23, -20, -62, -96, -119, -127, -121, +-102, -74, -43, -14, 6, 16, 17, 14, 14, 23, +41, 63, 83, 93, 90, 76, 55, 31, 9, -7, +-21, -31, -36, -32, -21, -3, 19, 48, 81, 118, +160, 203, 250, 300, 351, 402, 449, 485, 507, 513, +509, 499, 485, 467, 442, 411, 377, 342, 308, 274, +241, 207, 173, 140, 112, 89, 73, 61, 50, 34, +13, -11, -33, -47, -50, -51, -58, -78, -116, -165, +-213, -247, -264, -266, -262, -259, -266, -285, -314, -353, +-399, -448, -497, -540, -571, -584, -580, -561, -531, -495, +-457, -422, -391, -364, -340, -318, -298, -281, -267, -249, +-225, -194, -161, -133, -116, -111, -113, -119, -122, -119, +-109, -93, -72, -47, -23, 0, 25, 57, 98, 143, +184, 209, 214, 199, 170, 136, 104, 78, 59, 46, +39, 35, 32, 32, 37, 45, 56, 67, 80, 97, +117, 136, 151, 159, 162, 159, 149, 136, 128, 130, +144, 165, 185, 193, 189, 175, 158, 144, 131, 118, +107, 104, 115, 145, 196, 259, 324, 377, 410, 419, +406, 384, 361, 339, 319, 295, 268, 244, 229, 226, +230, 232, 227, 211, 184, 146, 103, 58, 14, -28, +-67, -102, -128, -141, -142, -135, -129, -132, -146, -170, +-198, -223, -239, -245, -241, -232, -227, -232, -251, -280, +-315, -350, -381, -407, -426, -438, -439, -427, -400, -360, +-314, -269, -229, -195, -165, -131, -90, -39, 17, 71, +114, 147, 169, 180, 184, 182, 179, 173, 164, 154, +145, 141, 142, 146, 152, 155, 158, 161, 165, 172, +182, 190, 193, 187, 176, 162, 151, 143, 138, 130, +115, 93, 62, 27, -9, -46, -80, -109, -134, -156, +-176, -191, -201, -208, -216, -232, -254, -277, -290, -288, +-267, -232, -194, -162, -139, -125, -118, -115, -114, -114, +-114, -110, -97, -74, -39, 3, 43, 73, 88, 89, +76, 56, 33, 15, 9, 15, 28, 41, 51, 58, +67, 78, 92, 101, 100, 87, 62, 29, -9, -47, +-78, -100, -114, -121, -124, -122, -111, -93, -73, -55, +-43, -36, -29, -19, -5, 11, 24, 30, 26, 11, +-7, -25, -38, -43, -41, -39, -38, -34, -23, -5, +15, 37, 57, 77, 100, 132, 175, 231, 297, 365, +425, 469, 493, 499, 496, 488, 480, 470, 461, 453, +446, 437, 423, 400, 369, 332, 289, 240, 191, 149, +114, 86, 61, 40, 20, 7, 4, 9, 16, 17, +6, -20, -62, -113, -165, -207, -235, -244, -244, -243, +-246, -256, -275, -303, -340, -382, -427, -468, -503, -530, +-547, -548, -532, -501, -462, -425, -398, -380, -366, -349, +-326, -298, -265, -230, -196, -166, -144, -130, -125, -128, +-138, -152, -163, -163, -149, -124, -97, -76, -65, -60, +-52, -34, -7, 25, 56, 79, 93, 95, 91, 84, +78, 75, 70, 61, 47, 29, 11, 0, -4, 0, +7, 16, 24, 34, 45, 58, 71, 78, 79, 74, +65, 58, 60, 71, 93, 123, 158, 194, 223, 241, +246, 237, 217, 190, 166, 150, 149, 166, 199, 246, +298, 345, 380, 396, 395, 383, 367, 354, 345, 336, +326, 315, 304, 294, 285, 274, 261, 243, 218, 184, +142, 96, 52, 16, -12, -35, -58, -80, -99, -114, +-124, -131, -141, -156, -173, -187, -196, -198, -195, -193, +-196, -210, -235, -265, -296, -324, -348, -371, -393, -410, +-418, -413, -393, -361, -327, -297, -274, -255, -233, -202, +-156, -95, -27, 36, 88, 124, 147, 160, 164, 160, +153, 145, 140, 138, 140, 146, 154, 163, 168, 167, +158, 142, 123, 107, 99, 96, 97, 100, 106, 116, +126, 133, 135, 131, 123, 108, 88, 63, 36, 9, +-15, -38, -60, -84, -111, -137, -162, -186, -211, -238, +-263, -284, -297, -299, -285, -255, -213, -168, -131, -107, +-96, -93, -93, -91, -87, -78, -63, -38, -4, 33, +67, 91, 99, 94, 76, 49, 24, 7, 2, 5, +11, 18, 26, 37, 50, 62, 70, 69, 60, 44, +22, -1, -23, -43, -60, -76, -96, -122, -148, -166, +-172, -168, -157, -143, -124, -103, -79, -58, -41, -31, +-25, -25, -28, -34, -42, -48, -49, -45, -38, -28, +-16, -1, 14, 30, 42, 50, 57, 64, 74, 94, +130, 184, 251, 321, 384, 431, 460, 472, 471, 465, +460, 459, 464, 473, 482, 488, 489, 487, 478, 458, +423, 370, 309, 246, 187, 136, 95, 65, 48, 40, +39, 42, 46, 48, 43, 26, -2, -39, -77, -109, +-132, -147, -160, -175, -194, -214, -238, -261, -284, -309, +-340, -377, -418, -455, -479, -488, -483, -471, -453, -433, +-413, -393, -373, -351, -324, -290, -249, -207, -170, -142, +-124, -116, -119, -132, -152, -172, -185, -187, -179, -165, +-146, -127, -115, -107, -104, -98, -90, -79, -67, -55, +-41, -25, -5, 15, 32, 39, 37, 27, 12, -7, +-29, -46, -52, -45, -31, -14, 0, 8, 11, 9, +4, 1, 1, 3, 3, 1, 3, 14, 40, 81, +130, 175, 208, 231, 244, 250, 250, 245, 238, 234, +235, 242, 256, 279, 307, 333, 351, 357, 356, 353, +351, 353, 356, 359, 360, 360, 358, 354, 346, 332, +313, 288, 255, 213, 169, 128, 96, 70, 44, 18, +-9, -36, -62, -89, -114, -136, -154, -166, -172, -174, +-175, -178, -182, -189, -201, -218, -240, -262, -283, -302, +-320, -337, -350, -358, -361, -360, -355, -345, -332, -321, +-311, -299, -281, -250, -203, -141, -71, -4, 52, 92, +116, 125, 127, 128, 130, 133, 135, 135, 137, 145, +160, 179, 196, 204, 196, 171, 135, 96, 64, 44, +38, 44, 58, 73, 85, 95, 102, 106, 107, 102, +93, 80, 69, 61, 54, 44, 28, 0, -35, -74, +-111, -146, -181, -216, -250, -276, -292, -294, -284, -262, +-232, -197, -160, -127, -103, -89, -80, -73, -60, -41, +-14, 14, 42, 65, 81, 91, 97, 97, 89, 72, +50, 28, 12, 4, 5, 12, 23, 35, 45, 50, +48, 40, 27, 13, -2, -17, -31, -41, -46, -50, +-62, -86, -121, -159, -189, -204, -203, -189, -169, -150, +-134, -122, -114, -107, -101, -97, -97, -102, -109, -115, +-112, -99, -76, -50, -28, -12, -1, 5, 13, 22, +32, 41, 54, 75, 108, 154, 210, 266, 320, 366, +399, 417, 425, 428, 432, 438, 447, 456, 465, 476, +490, 507, 522, 525, 506, 466, 407, 339, 269, 205, +154, 116, 89, 72, 61, 54, 50, 46, 42, 35, +26, 14, -3, -24, -49, -76, -104, -131, -157, -183, +-210, -237, -263, -286, -306, -324, -341, -359, -377, -399, +-419, -432, -436, -432, -422, -408, -385, -355, -316, -272, +-228, -188, -155, -134, -125, -124, -129, -136, -145, -154, +-165, -174, -179, -173, -156, -133, -111, -99, -99, -109, +-124, -141, -149, -147, -133, -112, -87, -59, -32, -9, +5, 8, -3, -25, -49, -67, -73, -68, -57, -45, +-36, -31, -33, -39, -46, -51, -54, -60, -69, -74, +-69, -48, -14, 28, 74, 117, 152, 180, 205, 228, +249, 272, 295, 314, 327, 334, 337, 340, 342, 342, +341, 341, 342, 344, 347, 350, 357, 367, 381, 395, +401, 400, 391, 376, 357, 331, 298, 258, 218, 182, +152, 126, 104, 81, 57, 25, -14, -56, -94, -120, +-132, -135, -136, -138, -144, -152, -160, -169, -181, -198, +-222, -251, -280, -304, -318, -322, -319, -315, -313, -315, +-320, -327, -337, -345, -348, -338, -315, -276, -225, -165, +-101, -41, 8, 43, 65, 78, 86, 91, 92, 90, +87, 84, 89, 103, 127, 155, 182, 196, 192, 169, +133, 94, 59, 32, 13, 5, 4, 11, 20, 28, +36, 45, 56, 68, 78, 82, 82, 80, 79, 77, +71, 56, 30, -3, -43, -85, -128, -167, -199, -225, +-248, -263, -268, -260, -239, -213, -186, -162, -141, -119, +-91, -59, -25, 7, 36, 58, 73, 80, 83, 86, +91, 97, 97, 90, 77, 62, 52, 48, 49, 52, +53, 52, 48, 39, 27, 14, 2, -9, -20, -30, +-35, -34, -28, -26, -37, -62, -96, -132, -163, -186, +-197, -194, -181, -162, -146, -135, -128, -126, -127, -132, +-141, -154, -165, -168, -160, -140, -112, -81, -53, -31, +-17, -11, -8, -3, 7, 24, 47, 76, 110, 148, +189, 232, 273, 306, 329, 342, 346, 348, 353, 365, +385, 409, 433, 457, 479, 500, 517, 526, 523, 504, +470, 423, 366, 308, 253, 207, 169, 135, 105, 77, +54, 39, 31, 32, 34, 34, 28, 18, 4, -11, +-32, -59, -95, -137, -182, -223, -256, -276, -285, -286, +-283, -285, -294, -311, -333, -355, -373, -387, -396, -398, +-388, -362, -320, -268, -213, -168, -141, -132, -133, -140, +-146, -154, -163, -173, -180, -182, -176, -162, -144, -124, +-110, -105, -112, -129, -155, -182, -201, -210, -205, -189, +-165, -137, -109, -88, -74, -71, -75, -85, -96, -105, +-106, -101, -89, -72, -57, -45, -40, -43, -54, -71, +-91, -110, -123, -126, -116, -93, -60, -20, 18, 50, +74, 91, 111, 140, 182, 233, 286, 333, 366, 385, +390, 388, 381, 372, 363, 351, 336, 322, 313, 315, +330, 354, 379, 399, 411, 414, 409, 396, 377, 350, +318, 283, 248, 217, 192, 172, 152, 131, 103, 70, +35, 3, -21, -41, -56, -67, -78, -90, -102, -114, +-124, -135, -150, -172, -201, -235, -267, -291, -305, -304, +-293, -277, -264, -259, -265, -281, -300, -316, -321, -314, +-292, -261, -219, -171, -123, -79, -41, -10, 15, 34, +46, 53, 55, 55, 56, 60, 66, 80, 102, 131, +159, 177, 179, 163, 135, 105, 79, 61, 48, 36, +20, -1, -21, -32, -29, -16, 1, 16, 25, 31, +38, 48, 60, 69, 72, 65, 50, 27, -3, -41, +-79, -115, -144, -169, -191, -208, -219, -223, -223, -222, +-220, -215, -202, -175, -136, -90, -42, 2, 39, 66, +81, 84, 81, 76, 72, 69, 65, 61, 59, 59, +63, 69, 77, 83, 83, 73, 54, 33, 12, -6, +-21, -33, -43, -52, -60, -65, -66, -69, -75, -86, +-103, -122, -143, -163, -177, -184, -183, -179, -173, -169, +-166, -163, -164, -169, -181, -197, -210, -212, -199, -174, +-142, -109, -83, -66, -58, -56, -54, -45, -26, 0, +32, 69, 109, 149, 190, 230, 266, 293, 306, 308, +304, 305, 314, 332, 357, 383, 409, 430, 449, 466, +482, 494, 499, 496, 485, 463, 436, 402, 364, 320, +272, 223, 175, 131, 96, 72, 59, 54, 55, 56, +58, 59, 57, 50, 35, 9, -28, -80, -139, -192, +-231, -252, -258, -254, -247, -242, -241, -248, -262, -284, +-308, -334, -356, -368, -367, -348, -314, -268, -218, -169, +-129, -103, -92, -96, -113, -137, -160, -179, -190, -189, +-178, -159, -136, -115, -99, -95, -104, -127, -160, -196, +-230, -255, -268, -267, -256, -236, -212, -186, -157, -131, +-110, -99, -96, -101, -111, -118, -121, -114, -101, -86, +-74, -69, -69, -76, -86, -100, -116, -130, -138, -135, +-119, -94, -65, -36, -8, 18, 48, 83, 126, 180, +239, 298, 348, 385, 410, 420, 418, 405, 386, 364, +342, 325, 317, 321, 337, 361, 382, 399, 407, 406, +398, 384, 365, 345, 322, 297, 271, 242, 213, 183, +156, 129, 102, 74, 46, 21, 0, -16, -30, -44, +-60, -78, -94, -106, -113, -119, -129, -147, -173, -205, +-238, -266, -282, -283, -272, -256, -244, -242, -252, -267, +-279, -285, -282, -275, -267, -270, -272, -247, -190, -119, +-57, -10, 25, 56, 75, 77, 60, 33, 16, 24, +52, 95, 149, 186, 188, 149, 81, 31, 33, 79, +138, 184, 205, 182, 130, 74, 16, -42, -97, -145, +-170, -159, -127, -82, -9, 85, 154, 168, 148, 123, +91, 22, -85, -194, -265, -287, -254, -168, -55, 41, +98, 109, 71, -7, -108, -220, -331, -409, -437, -387, +-238, -35, 143, 275, 370, 421, 424, 358, 211, 23, +-145, -257, -287, -218, -80, 72, 192, 262, 306, 341, +339, 262, 104, -87, -257, -357, -360, -271, -135, -7, +80, 132, 164, 169, 121, 0, -166, -334, -460, -486, +-397, -238, -84, 12, 56, 78, 84, 35, -82, -233, +-381, -493, -521, -437, -261, -67, 73, 141, 160, 151, +97, -9, -139, -255, -330, -345, -273, -102, 127, 334, +460, 504, 499, 463, 396, 300, 180, 58, -24, -19, +97, 303, 518, 670, 745, 767, 746, 678, 570, 432, +283, 148, 64, 64, 143, 261, 365, 435, 467, 447, +369, 240, 82, -82, -234, -341, -361, -277, -122, 46, +182, 262, 285, 247, 150, 11, -158, -356, -549, -678, +-695, -590, -406, -210, -45, 69, 119, 92, -2, -144, +-317, -485, -604, -626, -523, -324, -102, 80, 215, 293, +304, 257, 154, 0, -185, -363, -490, -519, -437, -293, +-136, 5, 105, 139, 114, 41, -73, -226, -407, -571, +-651, -612, -480, -304, -122, 31, 139, 193, 196, 149, +46, -109, -290, -437, -494, -450, -336, -184, -28, 96, +166, 179, 144, 60, -78, -265, -441, -532, -504, -378, +-200, -12, 161, 308, 418, 488, 514, 483, 389, 264, +165, 130, 165, 247, 359, 478, 574, 629, 643, 624, +566, 450, 278, 107, 10, 17, 108, 246, 394, 526, +619, 653, 618, 518, 354, 136, -86, -254, -332, -311, +-208, -57, 102, 233, 312, 337, 311, 216, 44, -176, +-378, -503, -536, -489, -384, -251, -126, -33, 22, 53, +45, -32, -185, -364, -503, -569, -552, -466, -331, -176, +-38, 61, 129, 169, 156, 64, -86, -240, -343, -364, +-302, -177, -13, 147, 271, 348, 376, 346, 243, 85, +-83, -213, -271, -248, -156, -28, 91, 169, 211, 232, +219, 145, 8, -154, -290, -365, -369, -301, -170, -9, +131, 224, 282, 311, 289, 199, 53, -110, -243, -317, +-323, -263, -160, -57, 13, 58, 89, 91, 35, -86, +-241, -371, -441, -434, -346, -180, 23, 210, 353, 451, +495, 469, 366, 201, 23, -119, -195, -191, -105, 31, +173, 291, 380, 436, 436, 358, 207, 26, -135, -246, +-292, -272, -203, -117, -40, 30, 95, 140, 137, 68, +-50, -185, -300, -371, -377, -321, -236, -158, -94, -34, +18, 35, -9, -114, -247, -377, -476, -516, -482, -388, +-270, -151, -34, 82, 176, 209, 165, 66, -50, -153, +-212, -199, -115, 10, 149, 281, 403, 502, 545, 508, +404, 272, 145, 55, 30, 78, 175, 287, 396, 499, +599, 674, 686, 625, 508, 362, 223, 126, 90, 106, +151, 203, 259, 318, 367, 377, 331, 241, 119, -14, +-128, -187, -184, -138, -76, -8, 67, 143, 189, 174, +96, -34, -196, -354, -465, -505, -473, -396, -294, -177, +-58, 29, 51, 8, -81, -198, -315, -395, -417, -378, +-302, -213, -119, -14, 85, 142, 134, 65, -49, -190, +-318, -395, -403, -360, -293, -218, -129, -33, 39, 56, +9, -97, -248, -413, -550, -622, -618, -555, -455, -322, +-166, -16, 90, 130, 94, -10, -162, -317, -431, -477, +-463, -404, -306, -172, -30, 78, 128, 108, 20, -116, +-265, -380, -428, -411, -350, -253, -111, 65, 248, 410, +520, 562, 534, 448, 343, 264, 228, 227, 250, 309, +408, 526, 633, 702, 712, 655, 538, 390, 259, 183, +159, 177, 234, 329, 444, 548, 612, 616, 550, 418, +239, 57, -78, -155, -183, -161, -81, 41, 174, 274, +315, 284, 181, 23, -149, -287, -369, -406, -403, -357, +-263, -142, -26, 56, 84, 45, -59, -201, -328, -404, +-431, -420, -371, -280, -156, -24, 87, 158, 173, 119, +8, -116, -212, -268, -286, -262, -189, -69, 74, 212, +315, 365, 345, 253, 120, -6, -102, -165, -193, -172, +-96, 21, 147, 248, 299, 277, 172, 12, -147, -263, +-328, -347, -321, -246, -125, 15, 144, 237, 273, 233, +124, -12, -133, -217, -268, -288, -268, -205, -112, -11, +78, 137, 137, 65, -51, -171, -263, -317, -331, -298, +-207, -69, 89, 241, 362, 422, 399, 303, 176, 56, +-42, -117, -161, -154, -88, 19, 146, 269, 352, 363, +295, 174, 36, -90, -198, -282, -329, -322, -268, -179, +-70, 31, 86, 71, 0, -93, -179, -248, -309, -354, +-366, -340, -282, -197, -101, -23, 3, -32, -112, -209, +-301, -385, -451, -475, -444, -365, -244, -98, 40, 134, +162, 130, 70, 9, -48, -97, -119, -97, -28, 80, +218, 356, 453, 481, 445, 375, 301, 234, 172, 124, +105, 122, 178, 276, 406, 531, 606, 607, 551, 472, +391, 312, 238, 180, 144, 133, 157, 218, 300, 368, +391, 362, 300, 222, 135, 43, -38, -95, -120, -101, +-32, 71, 174, 229, 214, 141, 37, -82, -204, -311, +-385, -419, -402, -330, -212, -77, 28, 75, 64, 15, +-52, -130, -204, -261, -297, -302, -265, -179, -59, 56, +122, 125, 81, 9, -77, -165, -241, -296, -326, -323, +-278, -193, -91, -15, 6, -22, -90, -188, -301, -410, +-500, -558, -572, -527, -416, -258, -102, 6, 54, 46, +-12, -107, -219, -327, -412, -457, -448, -375, -250, -114, +-14, 27, 19, -26, -94, -170, -240, -299, -341, -351, +-304, -185, -13, 162, 304, 400, 445, 447, 418, 372, +322, 276, 240, 230, 269, 356, 462, 549, 600, 610, +578, 512, 426, 335, 251, 181, 142, 157, 233, 341, +439, 499, 511, 476, 399, 294, 179, 67, -28, -97, +-115, -66, 31, 135, 210, 236, 214, 150, 60, -40, +-136, -229, -315, -371, -370, -307, -210, -116, -52, -27, +-43, -89, -151, -212, -264, -311, -342, -336, -274, -171, +-58, 35, 94, 112, 91, 41, -21, -85, -151, -211, +-239, -209, -123, -6, 108, 195, 242, 243, 200, 127, +42, -49, -143, -214, -230, -183, -93, 1, 72, 103, +89, 42, -21, -83, -142, -206, -270, -305, -289, -221, +-126, -32, 37, 71, 68, 34, -10, -55, -108, -171, +-226, -243, -212, -141, -56, 17, 64, 72, 46, 1, +-45, -95, -148, -192, -203, -159, -64, 56, 175, 271, +325, 332, 302, 250, 184, 99, 5, -67, -90, -48, +40, 148, 245, 304, 310, 271, 205, 124, 29, -79, +-186, -263, -284, -251, -182, -99, -23, 23, 34, 22, +-2, -42, -108, -194, -279, -332, -336, -299, -231, -153, +-92, -65, -72, -103, -154, -227, -319, -408, -461, -457, +-395, -291, -165, -44, 45, 98, 123, 127, 108, 62, +0, -50, -62, -25, 54, 161, 268, 347, 386, 394, +383, 354, 303, 232, 161, 117, 118, 163, 239, 332, +411, 460, 477, 473, 455, 416, 348, 264, 188, 142, +137, 174, 244, 317, 368, 384, 370, 332, 269, 176, +60, -49, -122, -139, -101, -24, 66, 138, 171, 164, +130, 72, -14, -129, -251, -346, -390, -371, -289, -169, +-47, 44, 91, 101, 83, 39, -36, -130, -218, -273, +-278, -227, -136, -34, 47, 93, 108, 101, 73, 13, +-75, -174, -258, -310, -313, -268, -192, -115, -62, -43, +-52, -90, -162, -268, -393, -509, -585, -598, -542, -431, +-300, -184, -103, -57, -41, -60, -124, -222, -331, -421, +-468, -456, -387, -284, -180, -100, -51, -28, -31, -66, +-132, -216, -298, -351, -353, -295, -185, -53, 71, 174, +256, 320, 355, 356, 326, 277, 228, 196, 199, 242, +314, 389, 452, 502, 538, 548, 520, 455, 363, 264, +183, 140, 149, 202, 272, 334, 380, 410, 420, 399, +342, 254, 149, 47, -27, -56, -32, 23, 81, 124, +150, 161, 148, 108, 39, -47, -139, -219, -266, -270, +-237, -192, -152, -120, -97, -83, -83, -98, -128, -171, +-217, -250, -252, -217, -160, -98, -36, 21, 71, 101, +99, 62, -3, -85, -162, -203, -191, -135, -57, 23, +97, 159, 196, 199, 166, 100, 6, -97, -181, -216, +-198, -146, -85, -28, 18, 50, 61, 47, 8, -53, +-134, -214, -264, -271, -237, -181, -115, -49, 7, 48, +68, 64, 31, -30, -109, -174, -204, -194, -157, -102, +-40, 22, 76, 110, 117, 94, 40, -34, -107, -144, +-132, -78, 2, 97, 196, 284, 348, 380, 371, 316, +216, 99, 7, -32, -18, 34, 106, 182, 248, 292, +303, 279, 217, 117, -7, -130, -220, -263, -262, -231, +-177, -110, -42, 13, 49, 54, 13, -71, -178, -273, +-333, -355, -346, -311, -254, -186, -122, -75, -60, -91, +-171, -283, -390, -457, -469, -436, -366, -271, -161, -49, +55, 144, 195, 188, 127, 39, -34, -67, -55, -4, +72, 163, 248, 317, 366, 389, 376, 321, 239, 159, +108, 96, 117, 164, 225, 288, 342, 385, 411, 411, +372, 302, 223, 163, 132, 132, 158, 206, 264, 316, +354, 372, 360, 304, 209, 94, -6, -69, -91, -77, +-36, 20, 79, 130, 170, 183, 152, 66, -59, -190, +-288, -334, -322, -259, -164, -60, 29, 97, 139, 146, +108, 25, -75, -163, -218, -233, -212, -160, -93, -26, +35, 84, 111, 98, 37, -57, -161, -246, -300, -320, +-304, -266, -219, -172, -132, -104, -109, -161, -256, -367, +-464, -526, -546, -524, -470, -399, -322, -241, -159, -95, +-76, -114, -195, -291, -376, -428, -434, -399, -335, -265, +-195, -128, -72, -44, -63, -120, -192, -253, -286, -281, +-238, -167, -83, 3, 96, 191, 275, 327, 338, 317, +279, 245, 228, 238, 272, 321, 376, 439, 509, 572, +601, 579, 512, 422, 329, 254, 210, 198, 208, 228, +256, 301, 361, 413, 430, 397, 319, 216, 113, 36, +-1, -2, 18, 47, 81, 125, 165, 179, 151, 88, +1, -90, -167, -214, -227, -218, -201, -179, -144, -101, +-60, -35, -34, -55, -89, -123, -145, -148, -136, -115, +-85, -37, 25, 86, 121, 118, 78, 13, -58, -116, +-141, -133, -106, -71, -22, 43, 118, 177, 199, 175, +108, 16, -77, -148, -182, -185, -170, -140, -91, -28, +31, 67, 68, 31, -34, -114, -182, -221, -230, -222, +-201, -166, -113, -53, -2, 23, 15, -22, -82, -142, +-182, -200, -199, -185, -151, -93, -14, 64, 122, 146, +129, 73, 0, -62, -94, -96, -78, -40, 22, 110, +208, 292, 343, 346, 302, 223, 134, 64, 24, 11, +20, 51, 103, 165, 221, 252, 247, 197, 107, -4, +-109, -188, -239, -264, -258, -219, -155, -83, -21, 11, +8, -33, -102, -179, -246, -298, -334, -347, -326, -270, +-195, -126, -84, -81, -126, -208, -298, -367, -407, -423, +-419, -389, -320, -215, -90, 27, 116, 158, 148, 102, +48, 9, -8, -9, 6, 44, 106, 181, 255, 315, +344, 331, 284, 230, 188, 164, 150, 143, 148, 171, +210, 256, 299, 325, 321, 287, 240, 203, 186, 183, +187, 199, 220, 251, 286, 317, 334, 321, 270, 196, +122, 66, 30, 2, -15, -16, 4, 48, 102, 149, +166, 136, 61, -32, -113, -160, -174, -162, -129, -80, +-21, 41, 104, 150, 163, 134, 73, 7, -45, -79, +-99, -102, -87, -56, -14, 34, 79, 102, 90, 44, +-16, -75, -121, -160, -192, -211, -217, -210, -190, -162, +-143, -152, -198, -264, -330, -383, -422, -451, -468, -468, +-446, -401, -332, -255, -194, -169, -184, -224, -269, -310, +-341, -358, -360, -349, -323, -282, -230, -181, -153, -152, +-166, -180, -187, -187, -183, -173, -153, -118, -65, 5, +84, 154, 200, 223, 236, 244, 252, 257, 263, 275, +298, 335, 389, 452, 502, 519, 503, 465, 422, 376, +325, 269, 216, 177, 163, 183, 238, 311, 369, 390, +374, 334, 281, 224, 171, 124, 86, 59, 50, 64, +96, 122, 127, 106, 70, 29, -15, -61, -110, -158, +-200, -226, -227, -194, -143, -94, -59, -40, -32, -31, +-38, -49, -63, -77, -84, -70, -29, 26, 73, 95, +89, 67, 38, 7, -23, -53, -79, -98, -100, -70, +-10, 58, 110, 128, 111, 66, 5, -59, -117, -162, +-191, -201, -183, -133, -67, -10, 18, 16, -9, -53, +-106, -158, -203, -236, -254, -249, -215, -160, -102, -63, +-49, -58, -83, -118, -157, -193, -222, -241, -235, -193, +-114, -21, 59, 110, 130, 125, 103, 71, 33, -4, +-41, -67, -61, -10, 78, 178, 264, 314, 325, 302, +258, 205, 152, 102, 60, 39, 51, 94, 150, 195, +211, 194, 146, 80, 9, -55, -113, -165, -204, -219, +-201, -156, -102, -55, -29, -27, -50, -91, -141, -194, +-248, -294, -318, -308, -266, -210, -164, -139, -142, -170, +-215, -263, -309, -352, -390, -411, -398, -340, -246, -136, +-32, 48, 96, 109, 98, 75, 49, 22, 1, -1, +23, 76, 143, 208, 259, 286, 289, 277, 257, 232, +201, 167, 138, 125, 133, 155, 183, 210, 228, 235, +232, 228, 225, 216, 198, 173, 159, 168, 199, 239, +276, 300, 302, 283, 248, 206, 160, 109, 57, 14, +-2, 10, 44, 86, 121, 136, 126, 95, 56, 20, +-13, -46, -73, -78, -54, -4, 58, 120, 164, 182, +173, 143, 100, 53, 7, -34, -61, -65, -46, -9, +35, 73, 92, 89, 69, 39, 0, -53, -121, -189, +-240, -264, -259, -233, -197, -167, -155, -163, -185, -217, +-263, -326, -398, -463, -501, -502, -464, -397, -320, -254, +-215, -201, -205, -222, -257, -308, -364, -408, -425, -411, +-370, -311, -248, -195, -157, -131, -115, -113, -125, -149, +-172, -182, -167, -123, -55, 21, 88, 137, 172, 200, +220, 229, 225, 217, 213, 224, 254, 303, 361, 413, +449, 465, 460, 434, 386, 319, 242, 171, 119, 102, +124, 180, 250, 310, 348, 364, 359, 331, 281, 217, +150, 93, 56, 43, 53, 78, 103, 120, 126, 118, +93, 46, -18, -92, -162, -216, -241, -232, -195, -145, +-97, -56, -19, 10, 25, 20, -2, -32, -59, -72, +-63, -35, 1, 35, 60, 77, 88, 91, 77, 46, +2, -44, -78, -87, -66, -25, 17, 46, 57, 52, +33, 2, -39, -90, -142, -182, -198, -183, -144, -94, +-49, -19, -6, -9, -27, -58, -99, -148, -196, -231, +-241, -221, -183, -143, -112, -94, -88, -96, -116, -146, +-178, -206, -222, -213, -173, -107, -31, 40, 101, 149, +181, 194, 183, 150, 100, 43, -2, -18, 3, 55, +120, 184, 241, 285, 310, 312, 291, 251, 198, 145, +105, 86, 87, 96, 108, 115, 118, 115, 102, 76, +34, -25, -93, -152, -187, -194, -182, -162, -138, -115, +-96, -86, -89, -104, -134, -175, -217, -248, -260, -259, +-252, -246, -239, -228, -214, -203, -201, -215, -248, -291, +-324, -330, -304, -253, -189, -119, -48, 17, 74, 114, +133, 128, 103, 72, 52, 51, 70, 101, 137, 177, +216, 255, 290, 310, 307, 274, 220, 163, 118, 90, +78, 76, 85, 103, 129, 160, 191, 212, 213, 194, +167, 145, 138, 145, 161, 179, 197, 214, 229, 243, +248, 234, 194, 136, 73, 23, -7, -19, -14, 4, +31, 60, 88, 107, 110, 91, 58, 20, -5, -13, +-1, 26, 61, 97, 129, 155, 173, 174, 153, 111, +56, 6, -28, -44, -40, -20, 10, 44, 73, 92, +91, 65, 10, -65, -145, -211, -257, -282, -284, -269, +-242, -209, -175, -152, -151, -179, -238, -314, -388, -445, +-480, -488, -470, -430, -375, -311, -251, -208, -195, -216, +-264, -322, -375, -415, -432, -423, -391, -337, -266, -185, +-110, -57, -39, -54, -84, -114, -133, -137, -127, -103, +-67, -18, 43, 113, 180, 226, 241, 232, 214, 201, +202, 220, 253, 293, 335, 375, 412, 440, 445, 417, +356, 278, 200, 139, 103, 97, 117, 154, 201, 251, +298, 330, 335, 308, 255, 188, 121, 68, 38, 32, +43, 67, 98, 129, 149, 143, 107, 45, -27, -97, +-152, -184, -190, -174, -140, -93, -36, 23, 74, 101, +101, 79, 46, 13, -10, -19, -13, 5, 31, 64, +100, 132, 146, 135, 105, 64, 23, -11, -36, -48, +-51, -44, -30, -9, 11, 21, 12, -14, -52, -94, +-130, -153, -160, -158, -147, -128, -100, -67, -40, -34, +-49, -81, -119, -153, -177, -189, -194, -194, -193, -187, +-170, -148, -134, -135, -150, -173, -194, -202, -191, -159, +-113, -63, -9, 49, 109, 158, 186, 185, 160, 120, +76, 41, 22, 20, 34, 61, 103, 157, 213, 260, +289, 297, 280, 244, 198, 149, 105, 66, 39, 32, +47, 77, 104, 114, 100, 63, 11, -43, -93, -132, +-161, -184, -196, -192, -173, -147, -122, -108, -106, -118, +-139, -167, -197, -230, -265, -297, -313, -306, -277, -237, +-202, -183, -182, -197, -221, -245, -262, -270, -266, -243, +-197, -134, -62, 7, 64, 104, 123, 126, 119, 104, +83, 60, 49, 62, 101, 158, 220, 269, 297, 300, +281, 247, 206, 157, 100, 48, 13, 5, 24, 64, +110, 151, 177, 187, 185, 176, 165, 148, 126, 109, +106, 124, 163, 209, 247, 266, 260, 232, 190, 141, +87, 36, -4, -24, -17, 13, 60, 110, 150, 169, +165, 148, 125, 100, 73, 50, 39, 49, 82, 129, +177, 213, 223, 207, 172, 132, 93, 58, 29, 9, +3, 14, 39, 69, 93, 98, 74, 21, -47, -118, +-181, -232, -270, -292, -293, -271, -233, -187, -150, -137, +-155, -203, -271, -348, -422, -480, -511, -511, -481, -428, +-361, -295, -245, -223, -231, -262, -310, -367, -421, -458, +-465, -435, -370, -284, -192, -112, -56, -27, -20, -32, +-59, -95, -130, -150, -147, -118, -64, 5, 78, 138, +177, 195, 199, 197, 193, 189, 186, 195, 216, 251, +295, 337, 365, 372, 359, 328, 285, 237, 188, 147, +124, 118, 132, 166, 213, 258, 288, 297, 288, 263, +227, 182, 134, 91, 65, 60, 74, 100, 125, 137, +131, 108, 72, 31, -12, -54, -89, -113, -122, -111, +-75, -22, 35, 80, 105, 107, 95, 76, 56, 38, +25, 18, 17, 24, 42, 69, 97, 121, 133, 131, +115, 88, 55, 17, -20, -53, -75, -80, -70, -55, +-44, -41, -48, -63, -87, -115, -142, -164, -175, -173, +-159, -135, -109, -89, -79, -78, -83, -95, -112, -134, +-162, -193, -220, -236, -236, -221, -199, -181, -172, -173, +-180, -188, -189, -182, -166, -140, -105, -58, 0, 62, +120, 166, 191, 195, 178, 148, 112, 75, 45, 28, +32, 61, 113, 175, 236, 285, 314, 313, 284, 231, +164, 96, 41, 10, 7, 26, 54, 81, 97, 102, +91, 66, 28, -20, -78, -137, -188, -219, -222, -201, +-168, -130, -98, -82, -83, -102, -138, -184, -235, -282, +-314, -324, -311, -281, -242, -203, -173, -156, -152, -158, +-174, -198, -224, -242, -240, -215, -168, -106, -37, 27, +77, 106, 114, 104, 81, 54, 33, 30, 51, 90, +139, 188, 227, 251, 254, 239, 206, 161, 108, 54, +10, -12, -11, 10, 47, 88, 122, 142, 147, 141, +128, 112, 97, 87, 87, 99, 123, 157, 197, 231, +251, 252, 232, 196, 148, 96, 48, 16, 1, 4, +24, 59, 100, 142, 176, 194, 195, 181, 152, 120, +97, 91, 103, 129, 160, 190, 213, 223, 220, 205, +181, 150, 113, 80, 57, 50, 55, 68, 78, 79, +66, 40, 2, -43, -94, -147, -198, -239, -264, -270, +-257, -233, -207, -190, -189, -204, -231, -266, -310, -356, +-399, -431, -449, -447, -427, -393, -354, -321, -301, -298, +-309, -337, -373, -406, -426, -427, -404, -360, -297, -227, +-159, -106, -70, -49, -42, -48, -65, -85, -101, -105, +-92, -62, -20, 27, 71, 107, 133, 151, 160, 164, +166, 166, 168, 174, 187, 210, 241, 270, 290, 297, +288, 268, 237, 202, 168, 138, 116, 108, 116, 139, +172, 209, 242, 263, 268, 253, 223, 186, 149, 117, +93, 81, 81, 89, 97, 102, 99, 87, 64, 33, +-2, -37, -62, -71, -61, -35, 0, 35, 65, 89, +105, 114, 116, 107, 91, 70, 48, 33, 32, 48, +74, 107, 138, 160, 169, 162, 138, 99, 50, -2, +-50, -84, -100, -101, -92, -80, -67, -60, -61, -71, +-90, -112, -135, -157, -173, -177, -168, -149, -123, -96, +-73, -60, -61, -77, -106, -141, -177, -204, -216, -216, +-207, -196, -185, -178, -174, -173, -171, -167, -160, -151, +-135, -106, -62, -6, 51, 105, 149, 180, 196, 196, +181, 154, 119, 84, 60, 58, 81, 125, 181, 236, +278, 297, 288, 256, 207, 150, 93, 46, 18, 15, +31, 59, 87, 108, 120, 116, 96, 57, 1, -64, +-128, -180, -209, -211, -190, -154, -119, -95, -87, -94, +-115, -148, -190, -237, -278, -304, -311, -299, -276, -246, +-210, -173, -141, -118, -111, -123, -148, -178, -201, -208, +-195, -165, -122, -72, -20, 24, 56, 75, 81, 78, +69, 62, 65, 79, 102, 127, 152, 174, 191, 197, +189, 164, 126, 83, 43, 15, 5, 12, 31, 53, +70, 78, 77, 72, 67, 63, 59, 55, 58, 73, +99, 130, 161, 186, 201, 205, 201, 189, 169, 140, +105, 70, 42, 29, 33, 53, 87, 126, 158, 180, +190, 191, 188, 180, 170, 166, 172, 186, 203, 218, +229, 236, 236, 230, 217, 202, 186, 169, 154, 142, +134, 129, 123, 113, 96, 68, 31, -11, -57, -103, +-146, -181, -199, -205, -204, -202, -202, -204, -207, -211, +-218, -230, -250, -281, -319, -357, -388, -408, -417, -417, +-407, -392, -374, -360, -353, -356, -370, -391, -407, -409, +-392, -361, -320, -276, -230, -184, -140, -100, -69, -50, +-49, -61, -75, -84, -83, -72, -55, -33, -7, 21, +51, 81, 105, 120, 128, 134, 143, 153, 165, 174, +180, 184, 188, 197, 215, 234, 245, 242, 225, 199, +169, 140, 117, 104, 104, 117, 140, 172, 207, 233, +243, 235, 214, 187, 161, 137, 119, 105, 94, 84, +77, 73, 69, 63, 52, 37, 23, 14, 11, 13, +19, 29, 40, 54, 73, 92, 107, 112, 109, 101, +93, 85, 80, 82, 89, 102, 117, 134, 151, 161, +159, 141, 110, 70, 26, -16, -56, -87, -110, -122, +-123, -113, -97, -86, -86, -97, -117, -140, -162, -176, +-178, -170, -155, -136, -113, -92, -78, -77, -88, -108, +-132, -155, -176, -190, -195, -196, -194, -190, -186, -183, +-182, -182, -179, -171, -154, -130, -99, -64, -26, 11, +54, 100, 142, 171, 183, 177, 159, 136, 114, 100, +100, 115, 140, 171, 204, 234, 253, 252, 230, 191, +146, 104, 69, 49, 41, 42, 51, 67, 86, 100, +102, 84, 50, 5, -41, -84, -114, -128, -129, -125, +-117, -109, -104, -107, -120, -142, -168, -197, -223, -246, +-262, -271, -274, -268, -249, -217, -181, -150, -130, -122, +-122, -128, -137, -143, -146, -144, -140, -129, -107, -76, +-40, -7, 20, 43, 60, 72, 81, 91, 100, 109, +119, 129, 140, 144, 138, 122, 100, 78, 61, 51, +47, 46, 44, 41, 36, 31, 25, 16, 6, 0, +-2, 3, 19, 43, 67, 86, 98, 108, 122, 136, +147, 150, 146, 135, 119, 101, 89, 84, 88, 93, +100, 110, 126, 146, 165, 181, 193, 201, 206, 209, +213, 218, 221, 223, 225, 229, 235, 240, 242, 245, +244, 238, 226, 212, 199, 185, 168, 145, 117, 85, +47, 7, -31, -63, -86, -101, -111, -121, -137, -158, +-181, -201, -215, -223, -227, -225, -221, -221, -231, -251, +-276, -304, -333, -362, -384, -399, -410, -418, -423, -424, +-418, -408, -395, -383, -372, -362, -349, -330, -300, -263, +-224, -183, -142, -104, -74, -56, -51, -54, -62, -71, +-72, -62, -43, -20, 0, 17, 36, 56, 76, 96, +112, 120, 115, 101, 87, 79, 83, 98, 124, 158, +193, 220, 233, 232, 217, 190, 154, 118, 91, 80, +85, 103, 131, 166, 199, 224, 237, 235, 219, 191, +159, 129, 104, 86, 74, 72, 79, 93, 106, 115, +118, 112, 99, 84, 71, 66, 66, 71, 77, 85, +93, 99, 107, 116, 122, 121, 112, 100, 94, 95, +103, 116, 132, 147, 155, 152, 139, 117, 84, 42, +-5, -49, -82, -102, -111, -111, -106, -101, -101, -107, +-119, -137, -157, -175, -186, -188, -183, -171, -155, -133, +-109, -91, -80, -81, -98, -127, -159, -184, -196, -199, +-196, -191, -187, -184, -182, -177, -168, -155, -143, -132, +-122, -106, -83, -53, -18, 19, 59, 95, 124, 146, +160, 165, 160, 149, 138, 136, 142, 152, 164, 176, +185, 189, 184, 172, 151, 124, 94, 68, 51, 43, +45, 56, 71, 84, 91, 88, 76, 53, 21, -13, +-45, -70, -87, -98, -103, -105, -106, -111, -119, -129, +-140, -155, -176, -201, -225, -245, -258, -263, -257, -240, +-215, -186, -155, -123, -93, -71, -63, -67, -79, -97, +-120, -142, -155, -153, -132, -96, -50, -3, 34, 59, +72, 77, 80, 81, 79, 74, 68, 63, 63, 69, +79, 86, 87, 81, 71, 61, 50, 38, 24, 8, +-12, -32, -44, -42, -28, -9, 9, 23, 34, 42, +49, 57, 63, 67, 69, 70, 76, 88, 101, 112, +118, 119, 116, 108, 100, 99, 106, 123, 146, 173, +203, 231, 250, 258, 258, 251, 239, 224, 215, 213, +223, 240, 264, 286, 303, 309, 302, 288, 266, 240, +209, 175, 141, 109, 79, 53, 34, 23, 17, 7, +-10, -38, -76, -122, -167, -206, -234, -248, -248, -234, +-212, -190, -174, -170, -178, -200, -238, -287, -341, -391, +-430, -454, -460, -448, -422, -391, -365, -347, -340, -343, +-351, -358, -355, -339, -308, -261, -200, -138, -85, -50, +-33, -32, -42, -57, -71, -77, -74, -65, -51, -27, +4, 42, 76, 99, 106, 97, 74, 42, 11, -11, +-21, -14, 10, 51, 102, 154, 197, 221, 224, 204, +166, 118, 73, 39, 22, 25, 49, 91, 139, 183, +214, 226, 218, 193, 157, 118, 83, 57, 45, 54, +79, 113, 146, 171, 183, 181, 165, 143, 123, 109, +98, 89, 83, 86, 97, 115, 133, 148, 155, 152, +141, 127, 114, 106, 104, 105, 113, 126, 142, 158, +168, 166, 147, 110, 62, 12, -33, -70, -97, -113, +-119, -117, -112, -107, -106, -112, -127, -151, -178, -201, +-216, -218, -205, -179, -146, -115, -91, -80, -84, -102, +-130, -157, -178, -192, -202, -207, -204, -194, -177, -158, +-137, -117, -102, -94, -94, -98, -101, -99, -90, -70, +-40, 0, 47, 95, 139, 172, 192, 197, 193, 183, +169, 153, 139, 132, 135, 144, 154, 162, 165, 158, +143, 121, 95, 70, 46, 30, 23, 28, 42, 62, +82, 96, 96, 80, 52, 23, -3, -31, -61, -88, +-109, -123, -132, -135, -135, -135, -141, -156, -177, -201, +-224, -245, -260, -269, -266, -249, -216, -170, -116, -65, +-27, -9, -13, -34, -68, -109, -144, -166, -168, -151, +-118, -72, -23, 22, 59, 85, 94, 86, 64, 36, +9, -8, -14, -5, 18, 48, 76, 96, 107, 109, +98, 74, 40, 4, -26, -49, -59, -58, -47, -32, +-16, 0, 15, 29, 36, 33, 20, 4, -9, -13, +-1, 23, 56, 91, 119, 139, 149, 147, 138, 125, +112, 106, 111, 131, 161, 196, 226, 246, 254, 253, +245, 232, 217, 208, 206, 214, 236, 268, 306, 339, +361, 368, 359, 336, 298, 250, 197, 144, 98, 66, +50, 50, 58, 64, 58, 38, 5, -39, -93, -150, +-205, -249, -276, -281, -265, -234, -195, -161, -139, -136, +-155, -196, -252, -317, -379, -431, -461, -465, -445, -410, +-374, -343, -324, -318, -325, -339, -351, -355, -345, -320, +-279, -227, -173, -123, -85, -56, -40, -35, -38, -46, +-54, -59, -56, -43, -17, 15, 48, 72, 83, 79, +63, 36, 5, -23, -45, -55, -51, -31, 3, 48, +94, 135, 163, 174, 167, 144, 114, 81, 53, 36, +34, 48, 76, 112, 146, 173, 186, 182, 163, 134, +103, 75, 54, 46, 52, 70, 96, 124, 152, 175, +191, 198, 198, 191, 177, 159, 141, 128, 122, 123, +128, 135, 144, 152, 161, 170, 176, 179, 175, 164, +151, 139, 132, 127, 121, 115, 107, 100, 93, 84, +69, 44, 8, -31, -70, -100, -119, -129, -134, -140, +-150, -164, -177, -186, -190, -191, -189, -184, -175, -164, +-155, -148, -147, -149, -152, -153, -151, -149, -151, -159, +-168, -174, -174, -166, -148, -126, -102, -85, -77, -75, +-77, -82, -88, -94, -92, -79, -54, -19, 24, 71, +116, 157, 190, 211, 218, 208, 185, 154, 125, 103, +91, 92, 101, 113, 120, 119, 113, 104, 89, 70, +48, 29, 18, 16, 22, 34, 47, 57, 62, 64, +61, 51, 34, 7, -26, -62, -94, -120, -135, -143, +-146, -146, -147, -147, -148, -156, -174, -200, -224, -237, +-232, -207, -167, -121, -77, -41, -18, -10, -17, -40, +-71, -104, -132, -146, -142, -116, -76, -29, 13, 46, +66, 72, 62, 39, 9, -20, -43, -55, -51, -32, +-5, 24, 49, 66, 72, 67, 51, 28, 0, -26, +-49, -66, -72, -65, -48, -26, -3, 15, 25, 23, +11, -5, -19, -30, -34, -31, -20, 0, 27, 60, +94, 122, 141, 150, 154, 156, 158, 163, 174, 189, +205, 220, 231, 239, 245, 246, 244, 241, 241, 245, +256, 275, 299, 324, 346, 360, 363, 355, 336, 304, +265, 222, 180, 144, 118, 101, 91, 83, 72, 55, +33, 6, -27, -70, -116, -158, -192, -215, -225, -222, +-209, -190, -170, -156, -152, -162, -188, -227, -274, -321, +-361, -390, -403, -403, -396, -386, -377, -368, -360, -351, +-341, -331, -321, -308, -293, -271, -243, -211, -178, -147, +-119, -94, -73, -57, -45, -34, -24, -12, 0, 12, +21, 25, 22, 16, 8, -2, -16, -31, -47, -61, +-70, -71, -61, -40, -12, 17, 45, 69, 86, 93, +92, 86, 76, 63, 53, 50, 58, 74, 92, 109, +122, 130, 134, 134, 129, 118, 101, 80, 62, 55, +62, 82, 111, 145, 179, 210, 233, 247, 251, 244, +226, 200, 172, 149, 132, 126, 131, 147, 170, 196, +218, 235, 243, 238, 220, 190, 155, 119, 89, 71, +65, 70, 81, 91, 95, 89, 71, 39, 1, -38, +-74, -106, -133, -154, -168, -178, -182, -180, -174, -167, +-166, -169, -175, -181, -187, -192, -194, -190, -179, -164, +-151, -142, -139, -144, -152, -159, -159, -151, -137, -117, +-97, -77, -62, -54, -51, -54, -62, -74, -85, -90, +-87, -73, -47, -7, 43, 98, 152, 195, 222, 227, +211, 179, 143, 112, 91, 80, 79, 85, 94, 102, +110, 115, 112, 97, 71, 40, 12, -7, -18, -18, +-5, 17, 46, 73, 95, 105, 99, 77, 42, 0, +-38, -75, -105, -126, -133, -132, -124, -116, -112, -116, +-130, -150, -170, -185, -193, -190, -178, -156, -124, -87, +-49, -17, 0, -1, -21, -51, -80, -100, -107, -100, +-82, -56, -27, 1, 29, 48, 52, 37, 8, -24, +-53, -70, -75, -70, -56, -37, -15, 7, 30, 44, +44, 29, 4, -23, -46, -63, -69, -65, -54, -38, +-21, -6, 4, 7, 0, -13, -30, -46, -58, -65, +-63, -53, -34, -8, 25, 65, 102, 130, 149, 159, +167, 176, 187, 198, 206, 211, 213, 216, 224, 234, +243, 249, 254, 260, 269, 281, 295, 311, 323, 331, +333, 332, 328, 316, 296, 268, 239, 211, 186, 165, +147, 132, 116, 98, 78, 55, 27, -5, -42, -79, +-114, -145, -169, -185, -192, -190, -184, -174, -161, -154, +-159, -178, -209, -245, -281, -311, -336, -353, -367, -374, +-374, -364, -345, -325, -310, -300, -297, -297, -296, -292, +-282, -265, -243, -218, -187, -151, -115, -80, -50, -23, +-2, 12, 18, 18, 12, 2, -7, -14, -15, -15, +-17, -26, -38, -54, -69, -82, -91, -95, -95, -91, +-78, -54, -21, 11, 38, 55, 63, 65, 63, 61, +59, 55, 47, 41, 44, 57, 77, 96, 106, 104, +94, 79, 66, 60, 64, 76, 93, 116, 147, 185, +224, 257, 277, 282, 273, 255, 231, 206, 184, 165, +154, 156, 171, 199, 231, 262, 281, 284, 269, 240, +203, 162, 123, 90, 69, 64, 71, 84, 95, 98, +91, 75, 51, 24, -5, -40, -77, -112, -136, -148, +-148, -142, -134, -130, -136, -151, -170, -189, -205, -217, +-223, -219, -205, -185, -165, -151, -144, -146, -152, -155, +-151, -139, -120, -100, -79, -56, -35, -18, -8, -9, +-19, -39, -63, -84, -99, -103, -93, -66, -22, 34, +95, 150, 190, 209, 207, 188, 163, 140, 120, 103, +89, 81, 80, 85, 94, 104, 107, 97, 72, 37, +2, -23, -40, -46, -41, -24, 2, 32, 61, 83, +94, 89, 68, 37, 3, -30, -59, -81, -93, -98, +-98, -97, -95, -95, -100, -110, -125, -141, -154, -163, +-164, -155, -135, -107, -78, -52, -33, -25, -28, -35, +-44, -50, -55, -57, -54, -44, -27, -9, 10, 23, +26, 16, -5, -30, -53, -72, -88, -98, -99, -91, +-74, -52, -30, -14, -9, -15, -28, -40, -51, -58, +-63, -63, -59, -53, -48, -42, -37, -34, -35, -41, +-50, -62, -76, -90, -102, -107, -102, -85, -55, -17, +22, 57, 86, 113, 140, 164, 184, 196, 202, 201, +197, 194, 197, 206, 218, 231, 243, 258, 274, 288, +298, 306, 310, 311, 310, 310, 311, 309, 302, 289, +275, 258, 241, 222, 203, 184, 162, 137, 111, 87, +66, 44, 21, -3, -30, -60, -90, -117, -138, -152, +-161, -163, -159, -153, -153, -161, -176, -194, -213, -237, +-262, -286, -308, -327, -338, -338, -327, -309, -290, -277, +-270, -267, -269, -275, -280, -281, -277, -268, -249, -219, +-177, -129, -80, -37, -6, 11, 14, 9, 2, -4, +-11, -18, -23, -26, -26, -25, -25, -29, -40, -58, +-79, -100, -119, -133, -139, -135, -118, -92, -60, -25, +9, 38, 55, 59, 52, 40, 27, 17, 13, 18, +30, 43, 54, 65, 72, 75, 72, 66, 61, 60, +66, 81, 107, 142, 181, 219, 253, 278, 289, 284, +268, 245, 220, 199, 185, 180, 189, 209, 235, 262, +282, 291, 285, 265, 235, 198, 159, 120, 91, 74, +69, 71, 78, 84, 89, 87, 76, 57, 33, 2, +-32, -67, -93, -108, -113, -111, -107, -106, -112, -129, +-154, -184, -210, -230, -241, -242, -234, -221, -208, -196, +-186, -178, -172, -168, -162, -152, -138, -120, -98, -72, +-44, -19, 0, 8, 4, -12, -41, -72, -98, -112, +-109, -88, -51, -3, 44, 86, 116, 135, 142, 140, +130, 117, 101, 85, 72, 67, 73, 87, 101, 110, +108, 95, 70, 38, 7, -20, -42, -57, -60, -48, +-23, 8, 42, 70, 89, 95, 86, 68, 44, 16, +-12, -40, -63, -77, -81, -76, -65, -56, -53, -59, +-72, -87, -100, -111, -119, -122, -117, -107, -94, -81, +-68, -56, -48, -43, -38, -32, -24, -14, -5, 2, +9, 12, 14, 13, 8, 0, -16, -37, -59, -79, +-97, -108, -110, -102, -89, -76, -65, -59, -57, -60, +-66, -71, -74, -73, -69, -63, -55, -47, -39, -32, +-26, -21, -23, -30, -40, -53, -70, -88, -104, -112, +-109, -96, -75, -48, -18, 12, 42, 73, 106, 138, +163, 179, 188, 193, 197, 202, 209, 219, 232, 246, +260, 273, 282, 286, 284, 281, 280, 284, 291, 299, +308, 312, 310, 302, 289, 277, 264, 248, 229, 207, +184, 162, 143, 128, 118, 107, 92, 71, 45, 13, +-24, -63, -100, -128, -147, -156, -155, -149, -142, -142, +-148, -160, -175, -196, -222, -252, -277, -294, -300, -294, +-280, -262, -246, -233, -226, -224, -232, -251, -279, -307, +-328, -333, -320, -286, -235, -179, -124, -78, -42, -18, +-7, -8, -18, -33, -48, -57, -55, -42, -26, -12, +-6, -9, -22, -43, -71, -102, -133, -160, -180, -186, +-177, -151, -114, -74, -38, -11, 6, 13, 10, 2, +-5, -12, -14, -11, -1, 12, 27, 42, 55, 61, +58, 48, 35, 27, 25, 34, 56, 91, 137, 184, +226, 258, 277, 283, 276, 260, 241, 222, 208, 205, +214, 235, 261, 288, 309, 321, 320, 305, 279, 244, +207, 169, 135, 110, 97, 94, 95, 97, 97, 95, +88, 73, 51, 26, -2, -30, -55, -73, -82, -86, +-87, -87, -89, -97, -115, -138, -164, -192, -217, -236, +-246, -245, -236, -224, -211, -197, -183, -171, -159, -147, +-136, -125, -113, -96, -71, -42, -14, 5, 14, 12, +0, -20, -38, -52, -58, -57, -48, -32, -6, 22, +52, 81, 105, 120, 124, 117, 105, 91, 76, 64, +59, 62, 69, 76, 81, 82, 78, 66, 45, 18, +-10, -38, -62, -75, -77, -66, -44, -16, 16, 48, +73, 87, 87, 71, 42, 5, -31, -58, -73, -77, +-72, -62, -48, -34, -23, -15, -13, -19, -35, -57, +-81, -100, -112, -115, -109, -94, -72, -48, -24, 0, +18, 29, 28, 19, 7, -3, -12, -18, -19, -17, +-18, -23, -32, -45, -61, -82, -104, -124, -138, -146, +-150, -148, -139, -126, -109, -91, -74, -60, -56, -58, +-67, -74, -78, -77, -70, -60, -48, -40, -38, -40, +-46, -57, -72, -90, -105, -114, -117, -109, -90, -59, +-22, 20, 65, 108, 144, 164, 170, 166, 157, 149, +149, 160, 185, 219, 254, 285, 308, 322, 325, 319, +305, 288, 272, 259, 252, 252, 260, 273, 287, 303, +313, 311, 293, 262, 226, 188, 155, 132, 123, 124, +128, 129, 123, 110, 87, 55, 18, -22, -62, -98, +-127, -143, -149, -149, -147, -148, -152, -160, -174, -192, +-211, -229, -245, -258, -262, -254, -235, -210, -188, -175, +-175, -191, -219, -252, -283, -307, -320, -317, -296, -259, +-211, -157, -105, -60, -30, -19, -27, -44, -63, -80, +-91, -94, -85, -67, -47, -29, -17, -15, -27, -53, +-89, -127, -163, -189, -201, -198, -183, -161, -134, -104, +-74, -48, -30, -19, -15, -17, -27, -38, -46, -43, +-31, -14, 5, 25, 41, 50, 53, 53, 52, 52, +58, 71, 91, 118, 148, 179, 209, 234, 251, 259, +261, 258, 254, 250, 250, 258, 272, 287, 300, 310, +314, 311, 299, 280, 257, 231, 203, 175, 150, 129, +111, 97, 86, 78, 69, 58, 47, 37, 26, 12, +-5, -25, -42, -53, -60, -64, -67, -72, -83, -98, +-119, -141, -164, -189, -212, -233, -249, -259, -260, -250, +-231, -208, -185, -162, -141, -121, -104, -86, -67, -49, +-36, -27, -21, -15, -8, -2, 1, 3, 2, 0, +-4, -3, 1, 10, 19, 27, 36, 45, 52, 59, +67, 75, 82, 83, 78, 70, 62, 55, 50, 47, +48, 49, 49, 46, 39, 25, 5, -19, -42, -59, +-66, -61, -42, -14, 16, 43, 62, 73, 70, 56, +32, 5, -20, -41, -55, -61, -55, -37, -11, 15, +38, 51, 52, 36, 9, -23, -58, -88, -109, -116, +-107, -84, -54, -19, 16, 45, 63, 66, 56, 38, +17, -3, -20, -30, -33, -31, -28, -24, -24, -32, +-49, -75, -107, -141, -174, -198, -207, -201, -183, -158, +-130, -105, -88, -81, -82, -86, -91, -96, -100, -101, +-96, -86, -74, -61, -51, -47, -53, -66, -83, -100, +-116, -124, -123, -107, -77, -38, 4, 46, 82, 107, +119, 122, 120, 118, 120, 129, 148, 176, 208, 244, +279, 309, 330, 337, 332, 316, 291, 262, 235, 217, +214, 226, 249, 277, 303, 316, 310, 288, 257, 224, +194, 167, 147, 135, 130, 131, 136, 140, 139, 126, +99, 63, 22, -17, -53, -84, -108, -126, -139, -147, +-150, -148, -149, -155, -168, -185, -202, -215, -219, -212, +-197, -179, -165, -157, -155, -160, -174, -196, -224, -254, +-280, -298, -300, -286, -258, -220, -178, -136, -100, -75, +-64, -64, -71, -82, -94, -102, -100, -90, -72, -51, +-32, -21, -21, -35, -59, -88, -119, -150, -177, -197, +-206, -203, -191, -170, -142, -110, -81, -58, -44, -38, +-41, -50, -58, -64, -65, -60, -49, -32, -12, 6, +24, 41, 56, 68, 74, 77, 79, 83, 89, 100, +120, 148, 177, 205, 228, 246, 260, 271, 279, 286, +291, 294, 297, 300, 304, 307, 305, 299, 291, 280, +266, 248, 224, 196, 165, 133, 102, 77, 61, 52, +47, 42, 34, 22, 7, -7, -18, -26, -33, -40, +-47, -53, -57, -62, -68, -78, -95, -120, -152, -186, +-217, -242, -258, -263, -257, -242, -221, -195, -168, -140, +-115, -94, -78, -67, -60, -55, -50, -38, -22, -5, +9, 20, 30, 39, 43, 42, 38, 30, 19, 7, +0, -3, 1, 12, 28, 45, 58, 66, 67, 62, +53, 39, 25, 15, 13, 15, 22, 30, 35, 33, +23, 1, -25, -52, -76, -92, -99, -93, -74, -46, +-15, 15, 39, 52, 51, 39, 17, -9, -35, -55, +-59, -45, -19, 13, 45, 72, 88, 91, 78, 53, +19, -19, -56, -85, -99, -95, -74, -40, 0, 40, +70, 85, 86, 73, 50, 22, -4, -25, -37, -40, +-34, -21, -8, 0, -4, -21, -51, -90, -132, -172, +-202, -218, -221, -213, -195, -172, -147, -126, -111, -101, +-95, -94, -98, -101, -102, -99, -95, -89, -80, -70, +-61, -58, -63, -72, -85, -98, -105, -102, -87, -63, +-33, 0, 31, 57, 76, 88, 95, 98, 102, 110, +126, 149, 178, 210, 245, 281, 315, 340, 349, 342, +319, 285, 247, 216, 199, 196, 206, 223, 242, 259, +270, 274, 270, 257, 233, 202, 169, 144, 129, 123, +124, 128, 136, 142, 144, 138, 123, 100, 66, 24, +-20, -61, -94, -116, -129, -135, -139, -141, -139, -134, +-129, -127, -129, -135, -140, -145, -147, -146, -141, -136, +-135, -140, -151, -167, -186, -207, -227, -242, -249, -244, +-228, -201, -169, -138, -113, -96, -86, -85, -92, -103, +-112, -117, -115, -109, -100, -88, -74, -62, -56, -59, +-71, -92, -122, -155, -186, -210, -223, -220, -203, -176, +-143, -112, -84, -66, -57, -59, -69, -83, -99, -111, +-117, -113, -96, -66, -26, 18, 60, 93, 110, 108, +95, 76, 60, 52, 56, 72, 99, 134, 173, 215, +253, 283, 302, 311, 314, 311, 305, 296, 287, 281, +281, 288, 300, 313, 321, 316, 295, 260, 216, 170, +130, 99, 78, 66, 59, 56, 54, 52, 46, 36, +22, 4, -14, -31, -44, -48, -46, -41, -34, -30, +-33, -48, -78, -119, -167, -212, -249, -271, -274, -261, +-235, -202, -165, -129, -101, -88, -88, -96, -105, -111, +-110, -101, -82, -56, -24, 11, 48, 80, 100, 104, +92, 68, 37, 7, -17, -30, -32, -22, -4, 19, +42, 61, 71, 68, 52, 27, 0, -23, -36, -37, +-27, -12, 7, 26, 39, 42, 31, 9, -22, -56, +-86, -104, -107, -96, -74, -43, -10, 20, 38, 41, +28, 5, -20, -41, -50, -45, -27, 2, 37, 74, +106, 128, 133, 120, 90, 49, 6, -32, -56, -64, +-55, -31, 0, 36, 67, 90, 98, 91, 69, 39, +5, -22, -39, -44, -39, -26, -10, 4, 12, 7, +-12, -48, -94, -144, -187, -218, -234, -240, -235, -220, +-195, -166, -140, -121, -112, -112, -118, -128, -136, -141, +-142, -138, -129, -116, -99, -81, -67, -59, -58, -63, +-71, -76, -76, -67, -54, -37, -17, 2, 23, 42, +59, 72, 79, 83, 86, 95, 113, 142, 180, 223, +264, 297, 319, 327, 322, 304, 278, 248, 222, 205, +196, 195, 202, 216, 234, 248, 254, 247, 231, 209, +183, 159, 140, 128, 124, 127, 135, 148, 160, 167, +166, 153, 130, 96, 57, 17, -20, -55, -87, -110, +-124, -126, -118, -104, -90, -82, -82, -90, -100, -109, +-114, -116, -115, -113, -109, -105, -103, -105, -113, -130, +-153, -174, -189, -196, -198, -196, -190, -178, -161, -141, +-123, -110, -104, -107, -116, -125, -131, -135, -134, -130, +-119, -103, -86, -73, -68, -76, -98, -131, -166, -196, +-218, -228, -227, -216, -196, -172, -145, -119, -99, -89, +-91, -105, -125, -146, -161, -166, -155, -127, -82, -29, +26, 74, 106, 118, 113, 97, 76, 55, 40, 35, +44, 69, 105, 149, 196, 241, 279, 305, 318, 318, +308, 290, 270, 256, 253, 262, 282, 304, 321, 326, +317, 295, 264, 229, 193, 157, 125, 98, 77, 62, +54, 51, 50, 46, 36, 21, 4, -13, -26, -34, +-35, -32, -25, -17, -12, -16, -35, -67, -107, -148, +-185, -214, -232, -236, -225, -204, -176, -148, -124, -108, +-104, -109, -118, -127, -132, -131, -120, -97, -64, -22, +21, 63, 94, 108, 107, 93, 71, 45, 19, -1, +-14, -16, -8, 6, 26, 43, 53, 50, 38, 20, +-1, -23, -41, -51, -52, -42, -23, 3, 31, 51, +54, 40, 15, -15, -49, -81, -103, -112, -106, -90, +-67, -43, -24, -14, -13, -17, -21, -25, -28, -27, +-18, -2, 22, 53, 86, 115, 132, 133, 119, 94, +65, 36, 11, -3, -5, 3, 18, 39, 59, 74, +81, 77, 66, 49, 28, 7, -10, -22, -27, -26, +-19, -7, 2, 4, -4, -25, -55, -90, -127, -160, +-188, -209, -222, -227, -222, -208, -192, -178, -167, -157, +-150, -145, -145, -149, -154, -159, -160, -153, -137, -117, +-100, -86, -76, -66, -56, -47, -40, -35, -34, -35, +-34, -28, -17, -3, 11, 23, 34, 44, 57, 74, +97, 123, 149, 175, 205, 237, 267, 289, 299, 300, +291, 275, 256, 238, 222, 209, 200, 197, 201, 207, +210, 209, 204, 196, 185, 171, 156, 143, 132, 125, +125, 133, 147, 163, 174, 179, 176, 161, 136, 100, +58, 13, -29, -64, -84, -90, -84, -74, -63, -54, +-49, -51, -57, -67, -79, -95, -110, -117, -113, -102, +-90, -80, -75, -76, -83, -96, -115, -138, -162, -185, +-200, -204, -198, -185, -171, -158, -147, -141, -141, -147, +-156, -166, -177, -181, -173, -156, -132, -110, -95, -89, +-92, -105, -125, -148, -171, -193, -210, -218, -212, -195, +-170, -143, -120, -107, -107, -120, -139, -162, -182, -197, +-200, -183, -145, -91, -33, 20, 63, 91, 103, 100, +88, 70, 48, 28, 18, 22, 42, 78, 123, 173, +221, 261, 288, 301, 299, 285, 264, 247, 242, 251, +269, 289, 306, 316, 318, 311, 299, 281, 256, 223, +186, 150, 120, 99, 86, 81, 77, 70, 56, 40, +25, 10, -5, -19, -27, -25, -18, -8, -3, -5, +-18, -43, -74, -107, -136, -158, -175, -184, -184, -175, +-160, -143, -127, -116, -113, -117, -126, -136, -144, -148, +-146, -131, -104, -65, -22, 21, 59, 86, 98, 99, +90, 74, 52, 29, 11, 0, -2, 2, 12, 23, +30, 29, 20, 8, -7, -28, -51, -73, -86, -87, +-76, -53, -24, 2, 21, 28, 24, 12, -4, -27, +-50, -71, -88, -98, -101, -96, -83, -69, -56, -44, +-32, -21, -14, -12, -12, -6, 6, 26, 53, 80, +102, 114, 116, 111, 102, 91, 80, 69, 61, 57, +56, 61, 71, 82, 87, 86, 81, 74, 62, 45, +25, 5, -9, -19, -23, -19, -11, -6, -8, -16, +-30, -47, -69, -97, -126, -155, -184, -208, -225, -232, +-228, -218, -203, -183, -164, -151, -149, -157, -169, -181, +-190, -193, -187, -176, -162, -142, -117, -87, -55, -29, +-13, -7, -11, -20, -31, -35, -33, -29, -23, -13, +4, 27, 50, 70, 86, 98, 105, 114, 130, 155, +185, 213, 235, 251, 263, 269, 267, 259, 245, 225, +203, 184, 174, 172, 171, 170, 169, 167, 166, 164, +161, 155, 146, 132, 119, 112, 116, 129, 147, 163, +176, 181, 174, 156, 129, 93, 51, 9, -22, -39, +-44, -40, -34, -24, -13, -4, -2, -5, -17, -38, +-64, -89, -103, -104, -94, -78, -59, -41, -27, -22, +-25, -38, -60, -92, -127, -156, -176, -184, -183, -175, +-161, -147, -136, -132, -136, -146, -160, -176, -188, -191, +-187, -176, -160, -142, -124, -113, -108, -110, -120, -139, +-164, -188, -204, -207, -200, -185, -168, -151, -139, -135, +-140, -153, -171, -189, -201, -201, -184, -154, -114, -68, +-22, 19, 53, 77, 91, 94, 84, 65, 43, 25, +19, 27, 52, 89, 136, 182, 220, 249, 265, 269, +264, 253, 241, 232, 228, 230, 240, 255, 273, 289, +299, 302, 292, 269, 236, 200, 168, 143, 122, 105, +90, 75, 62, 51, 43, 34, 23, 9, -3, -11, +-14, -15, -17, -22, -30, -40, -51, -60, -67, -75, +-87, -100, -110, -116, -117, -114, -112, -110, -112, -118, +-126, -133, -138, -141, -141, -135, -122, -103, -76, -44, +-9, 23, 50, 70, 84, 91, 86, 71, 50, 29, +12, 1, -2, 0, 5, 12, 17, 18, 12, -3, +-27, -57, -83, -100, -105, -99, -84, -63, -42, -20, +-1, 16, 27, 27, 14, -8, -38, -71, -102, -125, +-138, -137, -124, -101, -73, -45, -22, -4, 6, 13, +19, 25, 32, 41, 51, 62, 73, 88, 107, 125, +136, 138, 132, 120, 106, 95, 86, 82, 82, 84, +89, 94, 96, 90, 74, 51, 27, 7, -6, -15, +-21, -27, -34, -38, -37, -33, -29, -34, -51, -80, +-117, -156, -192, -218, -231, -233, -225, -210, -190, -172, +-159, -154, -160, -175, -195, -214, -227, -230, -221, -201, +-169, -129, -84, -43, -13, 2, 6, -1, -17, -35, +-49, -56, -55, -42, -18, 12, 43, 67, 81, 87, +88, 88, 91, 99, 112, 128, 149, 174, 204, 233, +256, 268, 268, 259, 243, 221, 197, 174, 153, 137, +130, 131, 140, 150, 158, 159, 152, 139, 124, 113, +110, 113, 122, 135, 151, 168, 182, 185, 175, 153, +122, 85, 52, 27, 11, 3, 3, 10, 24, 41, +52, 52, 36, 9, -24, -55, -78, -90, -91, -83, +-68, -47, -23, 0, 15, 17, 4, -20, -56, -93, +-127, -154, -173, -185, -188, -182, -170, -156, -147, -148, +-160, -181, -203, -222, -232, -236, -232, -221, -203, -178, +-152, -130, -118, -119, -133, -154, -174, -190, -199, -204, +-203, -197, -185, -171, -161, -159, -166, -179, -193, -200, +-198, -186, -168, -145, -114, -75, -28, 19, 60, 88, +96, 89, 71, 53, 41, 37, 43, 58, 80, 110, +146, 184, 219, 245, 258, 260, 252, 240, 226, 214, +207, 210, 222, 243, 265, 284, 292, 288, 270, 244, +214, 183, 153, 124, 101, 87, 81, 81, 84, 85, +81, 71, 57, 41, 25, 6, -13, -33, -47, -53, +-52, -46, -39, -35, -33, -34, -37, -40, -46, -55, +-69, -86, -102, -114, -118, -115, -112, -109, -109, -109, +-108, -104, -95, -83, -67, -46, -20, 9, 41, 68, +85, 88, 80, 64, 46, 28, 11, -1, -6, -5, +2, 10, 17, 15, 3, -17, -43, -69, -92, -110, +-122, -127, -120, -101, -68, -29, 8, 36, 47, 38, +12, -24, -65, -105, -136, -155, -158, -143, -114, -76, +-36, -2, 21, 37, 42, 40, 31, 19, 9, 7, +18, 44, 79, 118, 149, 171, 181, 181, 172, 156, +136, 116, 101, 94, 94, 100, 107, 109, 106, 96, +82, 67, 47, 19, -13, -45, -69, -79, -76, -61, +-44, -32, -32, -44, -65, -92, -122, -152, -179, -200, +-213, -214, -205, -190, -177, -171, -174, -184, -200, -219, +-240, -256, -264, -259, -239, -202, -152, -99, -51, -16, +1, 3, -7, -26, -46, -61, -65, -58, -40, -12, +20, 50, 73, 87, 93, 93, 88, 82, 77, 78, +86, 104, 131, 166, 201, 231, 250, 258, 253, 240, +219, 193, 166, 141, 123, 115, 117, 126, 134, 140, +141, 138, 132, 124, 116, 110, 107, 107, 113, 125, +139, 150, 156, 152, 141, 124, 104, 83, 64, 52, +48, 54, 67, 81, 90, 89, 78, 60, 38, 16, +-5, -26, -43, -54, -57, -49, -30, -5, 17, 33, +39, 34, 18, -5, -35, -69, -101, -128, -146, -155, +-156, -156, -157, -161, -167, -175, -187, -203, -221, -240, +-256, -264, -262, -249, -227, -201, -177, -158, -147, -144, +-149, -161, -177, -192, -205, -212, -212, -207, -202, -200, +-197, -194, -188, -181, -175, -171, -169, -164, -154, -134, +-103, -65, -27, 5, 30, 48, 61, 68, 71, 69, +64, 59, 60, 72, 95, 125, 157, 186, 208, 224, +234, 236, 231, 220, 206, 196, 193, 201, 215, 231, +246, 255, 258, 253, 241, 224, 200, 173, 144, 119, +105, 99, 99, 100, 101, 98, 91, 78, 60, 36, +9, -18, -42, -58, -65, -64, -56, -44, -28, -11, +4, 13, 14, 4, -15, -39, -61, -80, -93, -100, +-101, -97, -91, -85, -79, -76, -78, -82, -86, -82, +-69, -47, -19, 8, 36, 59, 74, 80, 75, 62, +41, 18, -2, -14, -15, -11, -5, -1, -2, -9, +-23, -43, -68, -96, -124, -146, -155, -146, -122, -88, +-51, -17, 5, 15, 11, -4, -30, -64, -100, -130, +-150, -155, -144, -119, -84, -46, -11, 16, 35, 41, +33, 15, -3, -15, -15, 0, 28, 67, 108, 145, +170, 185, 189, 183, 171, 155, 140, 129, 123, 120, +121, 126, 130, 134, 132, 122, 101, 68, 28, -10, +-41, -59, -65, -62, -53, -44, -39, -38, -43, -53, +-71, -95, -122, -147, -168, -182, -190, -191, -188, -186, +-184, -186, -191, -204, -224, -248, -268, -276, -269, -245, +-207, -161, -116, -77, -47, -29, -21, -25, -38, -53, +-65, -67, -58, -38, -11, 19, 46, 69, 85, 94, +94, 87, 75, 63, 56, 57, 69, 93, 123, 155, +184, 208, 224, 231, 226, 210, 186, 159, 134, 114, +103, 100, 102, 108, 114, 122, 129, 131, 127, 117, +105, 91, 82, 80, 86, 97, 111, 121, 126, 127, +124, 117, 106, 98, 94, 95, 101, 108, 115, 119, +116, 109, 98, 84, 65, 42, 18, -2, -17, -23, +-15, 1, 24, 44, 58, 64, 62, 50, 30, 6, +-20, -49, -75, -97, -114, -126, -135, -142, -147, -151, +-157, -170, -190, -217, -248, -275, -293, -295, -281, -255, +-224, -195, -170, -151, -142, -142, -150, -163, -180, -199, +-215, -226, -229, -223, -212, -195, -177, -161, -152, -149, +-151, -158, -164, -165, -158, -142, -118, -88, -52, -14, +21, 48, 67, 75, 75, 69, 64, 63, 69, 79, +94, 115, 141, 169, 194, 212, 220, 217, 205, 191, +180, 176, 179, 185, 194, 205, 218, 228, 230, 225, +212, 191, 168, 147, 132, 124, 122, 123, 125, 127, +126, 121, 109, 89, 60, 24, -11, -42, -62, -71, +-70, -58, -39, -15, 9, 30, 43, 46, 37, 18, +-3, -25, -44, -59, -71, -76, -75, -69, -63, -57, +-57, -64, -77, -90, -96, -91, -77, -55, -27, 2, +29, 48, 58, 58, 51, 36, 17, 0, -13, -19, +-19, -15, -9, -3, -3, -11, -28, -54, -86, -117, +-142, -154, -151, -136, -111, -83, -53, -28, -12, -6, +-13, -32, -60, -91, -116, -131, -134, -126, -107, -79, +-45, -11, 15, 32, 35, 25, 7, -7, -15, -11, +1, 24, 53, 85, 115, 144, 169, 188, 197, 192, +179, 162, 146, 135, 131, 132, 138, 144, 147, 144, +134, 114, 85, 51, 18, -12, -39, -58, -72, -78, +-80, -78, -73, -66, -60, -61, -68, -81, -99, -121, +-144, -165, -181, -192, -198, -202, -204, -210, -220, -233, +-245, -251, -250, -241, -224, -201, -174, -146, -120, -96, +-76, -62, -55, -54, -54, -52, -47, -38, -23, -4, +17, 40, 61, 79, 90, 92, 85, 74, 61, 50, +45, 47, 56, 72, 92, 115, 140, 162, 178, 185, +183, 174, 158, 138, 114, 94, 79, 72, 76, 88, +106, 123, 133, 134, 128, 116, 102, 88, 77, 70, +67, 67, 72, 83, 99, 115, 130, 141, 148, 152, +150, 145, 139, 133, 130, 129, 131, 132, 127, 115, +97, 75, 53, 36, 26, 23, 25, 31, 39, 49, +59, 67, 69, 65, 55, 39, 16, -11, -43, -76, +-104, -125, -136, -138, -137, -141, -156, -182, -214, -247, +-274, -291, -295, -290, -277, -258, -233, -206, -179, -158, +-147, -147, -159, -180, -206, -230, -245, -251, -245, -227, +-200, -169, -141, -122, -114, -118, -131, -148, -162, -170, +-169, -157, -135, -104, -67, -28, 8, 39, 63, 75, +77, 71, 62, 55, 53, 61, 79, 107, 139, 167, +187, 197, 198, 190, 177, 163, 153, 147, 145, 150, +161, 174, 185, 191, 191, 186, 177, 166, 157, 149, +144, 141, 139, 139, 142, 142, 137, 124, 103, 74, +42, 11, -16, -37, -49, -48, -37, -16, 7, 29, +46, 55, 56, 51, 40, 25, 8, -10, -28, -41, +-44, -39, -31, -25, -25, -32, -44, -60, -74, -81, +-82, -76, -64, -45, -24, -3, 13, 24, 30, 28, +20, 9, -2, -13, -20, -22, -21, -17, -14, -14, +-20, -33, -50, -71, -92, -110, -121, -125, -120, -107, +-89, -72, -58, -51, -50, -55, -63, -74, -84, -93, +-100, -102, -97, -82, -60, -35, -14, 0, 5, 3, +-1, -5, -6, -2, 3, 12, 23, 41, 65, 94, +123, 149, 167, 175, 176, 172, 166, 160, 155, 151, +150, 152, 153, 154, 150, 139, 123, 101, 76, 49, +22, -5, -33, -58, -77, -88, -89, -83, -74, -65, +-60, -59, -62, -70, -85, -106, -131, -155, -176, -193, +-206, -216, -223, -227, -229, -228, -222, -215, -208, -202, +-192, -179, -163, -145, -127, -111, -97, -87, -79, -69, +-59, -46, -31, -14, 4, 24, 43, 60, 73, 81, +82, 79, 73, 65, 57, 51, 47, 48, 55, 68, +85, 103, 120, 133, 142, 146, 144, 135, 119, 101, +86, 76, 75, 80, 91, 103, 111, 115, 114, 111, +104, 93, 79, 63, 48, 38, 34, 40, 56, 79, +103, 126, 143, 153, 158, 158, 156, 154, 154, 155, +157, 159, 157, 148, 135, 119, 104, 92, 81, 71, +62, 55, 50, 48, 50, 56, 62, 66, 67, 62, +48, 25, -2, -32, -57, -75, -86, -93, -99, -112, +-133, -162, -193, -221, -246, -268, -286, -299, -302, -295, +-277, -251, -221, -195, -179, -173, -177, -189, -208, -229, +-247, -258, -257, -242, -215, -183, -152, -129, -116, -111, +-113, -122, -136, -152, -165, -172, -169, -153, -124, -88, +-51, -16, 15, 38, 54, 60, 60, 55, 50, 49, +57, 75, 99, 122, 140, 151, 158, 161, 160, 156, +151, 145, 139, 135, 135, 139, 144, 148, 150, 149, +148, 147, 145, 145, 146, 148, 153, 159, 167, 172, +171, 160, 140, 113, 82, 50, 23, 3, -8, -13, +-9, 0, 13, 28, 41, 53, 62, 67, 66, 58, +46, 32, 20, 13, 13, 20, 27, 30, 25, 15, +1, -15, -32, -48, -60, -68, -72, -68, -57, -40, +-21, -7, 2, 6, 5, 1, -6, -16, -27, -37, +-44, -43, -37, -29, -26, -28, -36, -48, -63, -77, +-89, -101, -112, -120, -123, -121, -115, -108, -101, -94, +-88, -85, -83, -83, -83, -83, -82, -77, -67, -54, +-43, -33, -24, -16, -9, -5, -3, -1, 0, 0, +4, 13, 30, 52, 75, 97, 119, 138, 153, 164, +169, 168, 164, 157, 153, 154, 157, 160, 163, 163, +159, 150, 135, 112, 83, 46, 6, -31, -62, -82, +-93, -94, -87, -75, -61, -49, -43, -43, -53, -73, +-98, -125, -150, -170, -186, -196, -199, -198, -194, -190, +-187, -187, -190, -196, -201, -199, -191, -179, -163, -147, +-129, -111, -93, -75, -59, -48, -40, -33, -26, -15, +-1, 16, 36, 57, 75, 89, 97, 97, 88, 73, +54, 39, 30, 30, 37, 50, 66, 82, 97, 110, +118, 119, 112, 98, 84, 73, 70, 72, 78, 87, +98, 108, 115, 118, 115, 103, 81, 54, 29, 12, +5, 10, 24, 46, 72, 98, 122, 141, 152, 156, +155, 153, 152, 156, 163, 170, 177, 182, 182, 179, +175, 167, 155, 137, 117, 97, 81, 69, 65, 68, +75, 83, 89, 88, 81, 65, 44, 22, 3, -11, +-24, -38, -54, -71, -90, -112, -135, -159, -186, -217, +-247, -274, -292, -298, -291, -275, -251, -227, -207, -194, +-190, -197, -213, -236, -257, -271, -272, -262, -241, -213, +-182, -150, -122, -99, -85, -83, -96, -119, -146, -168, +-182, -183, -170, -146, -114, -79, -43, -10, 17, 35, +44, 48, 49, 49, 52, 58, 67, 78, 90, 103, +117, 131, 142, 146, 145, 138, 127, 116, 107, 101, +99, 98, 99, 104, 112, 121, 127, 132, 136, 142, +149, 158, 166, 169, 165, 155, 140, 124, 108, 91, +75, 60, 48, 38, 29, 24, 23, 26, 33, 42, +52, 61, 64, 61, 56, 53, 51, 53, 56, 60, +61, 59, 54, 47, 41, 32, 20, 3, -14, -33, +-50, -63, -71, -72, -66, -54, -39, -23, -11, -7, +-12, -24, -38, -51, -60, -63, -62, -59, -55, -50, +-44, -36, -29, -27, -29, -39, -57, -81, -105, -126, +-140, -147, -147, -140, -127, -110, -94, -78, -65, -54, +-47, -43, -41, -39, -38, -38, -35, -29, -19, -8, +1, 9, 14, 15, 14, 13, 15, 19, 28, 43, +63, 87, 111, 131, 145, 152, 153, 151, 148, 145, +144, 144, 147, 154, 162, 167, 165, 156, 136, 107, +71, 32, -4, -35, -60, -77, -83, -78, -64, -48, +-35, -29, -32, -45, -66, -90, -115, -136, -153, -164, +-168, -166, -160, -154, -152, -153, -160, -170, -181, -189, +-194, -197, -196, -189, -175, -156, -133, -113, -97, -87, +-80, -76, -70, -59, -44, -27, -5, 17, 40, 59, +72, 77, 76, 68, 55, 41, 30, 22, 17, 18, +26, 38, 51, 60, 66, 67, 65, 60, 55, 54, +55, 60, 68, 79, 93, 107, 118, 123, 120, 107, +87, 62, 39, 22, 11, 9, 17, 34, 58, 84, +110, 129, 139, 142, 139, 136, 138, 143, 151, 161, +172, 183, 195, 207, 216, 219, 213, 196, 173, 150, +131, 118, 110, 106, 106, 106, 105, 101, 95, 86, +74, 61, 48, 35, 21, 6, -10, -29, -49, -71, +-94, -117, -143, -171, -202, -230, -252, -267, -273, -270, +-261, -250, -240, -235, -235, -239, -248, -260, -272, -282, +-286, -283, -272, -251, -223, -192, -160, -132, -110, -97, +-97, -106, -121, -136, -149, -158, -160, -154, -141, -121, +-97, -70, -44, -21, -4, 9, 20, 29, 36, 42, +47, 54, 64, 75, 88, 100, 109, 116, 119, 120, +119, 115, 108, 99, 88, 80, 73, 71, 74, 81, +89, 98, 107, 119, 130, 140, 146, 148, 145, 138, +129, 122, 117, 114, 109, 103, 96, 89, 82, 76, +72, 70, 68, 67, 66, 64, 62, 59, 57, 57, +61, 68, 76, 82, 85, 85, 82, 79, 77, 74, +69, 56, 37, 14, -9, -32, -50, -62, -67, -65, +-57, -46, -37, -34, -37, -45, -55, -64, -71, -77, +-82, -88, -91, -88, -77, -58, -36, -19, -11, -15, +-27, -48, -72, -96, -117, -134, -145, -151, -151, -144, +-133, -120, -105, -89, -71, -56, -43, -36, -33, -35, +-38, -39, -34, -24, -12, -2, 4, 8, 10, 12, +14, 18, 22, 30, 43, 59, 78, 96, 110, 120, +126, 130, 133, 136, 139, 142, 144, 146, 152, 160, +167, 169, 162, 145, 119, 88, 54, 23, -3, -26, +-42, -50, -51, -45, -38, -34, -35, -42, -54, -72, +-91, -110, -126, -138, -145, -145, -141, -134, -126, -122, +-121, -125, -133, -146, -160, -174, -185, -189, -185, -173, +-157, -140, -126, -115, -106, -97, -87, -76, -64, -53, +-41, -27, -7, 15, 37, 55, 67, 70, 66, 58, +48, 39, 30, 21, 14, 10, 10, 11, 12, 13, +13, 15, 18, 25, 34, 45, 56, 67, 79, 90, +100, 105, 103, 95, 83, 67, 50, 34, 22, 16, +17, 27, 43, 63, 81, 95, 104, 112, 119, 126, +133, 139, 143, 147, 153, 164, 182, 201, 218, 229, +233, 230, 220, 208, 195, 181, 168, 154, 141, 130, +121, 113, 105, 98, 91, 83, 76, 68, 59, 47, +28, 6, -15, -36, -54, -74, -97, -120, -143, -165, +-185, -200, -213, -224, -234, -243, -250, -255, -259, -263, +-267, -271, -275, -276, -276, -272, -266, -257, -243, -223, +-199, -173, -148, -127, -112, -105, -105, -108, -111, -115, +-121, -127, -131, -130, -123, -110, -91, -69, -47, -27, +-10, 4, 16, 24, 28, 30, 35, 42, 51, 62, +73, 85, 96, 103, 108, 108, 103, 93, 80, 65, +53, 44, 39, 41, 48, 60, 76, 96, 115, 127, +131, 125, 116, 106, 99, 97, 98, 102, 105, 108, +111, 115, 119, 120, 117, 112, 104, 95, 83, 73, +65, 61, 61, 64, 72, 81, 89, 95, 97, 99, +100, 101, 103, 105, 106, 103, 94, 78, 57, 32, +7, -14, -31, -42, -48, -49, -47, -43, -41, -42, +-47, -54, -66, -85, -106, -126, -137, -135, -121, -96, +-66, -38, -19, -11, -12, -21, -39, -63, -90, -114, +-136, -153, -163, -164, -156, -142, -123, -101, -77, -57, +-43, -38, -39, -44, -49, -51, -48, -38, -25, -12, +0, 11, 21, 27, 30, 31, 31, 33, 36, 41, +49, 60, 71, 83, 97, 113, 126, 133, 134, 132, +128, 124, 125, 131, 140, 146, 147, 141, 130, 115, +96, 74, 52, 31, 12, -1, -12, -19, -24, -31, +-39, -47, -55, -64, -77, -92, -106, -119, -128, -132, +-130, -122, -112, -102, -92, -85, -85, -93, -108, -125, +-141, -153, -159, -159, -154, -148, -140, -129, -115, -100, +-89, -80, -75, -72, -70, -65, -53, -33, -10, 11, +30, 46, 59, 66, 67, 64, 57, 46, 31, 15, +1, -11, -23, -33, -39, -36, -26, -12, 4, 21, +36, 47, 54, 60, 65, 69, 70, 68, 64, 58, +50, 44, 39, 36, 35, 37, 43, 51, 59, 67, +75, 85, 97, 110, 122, 131, 136, 139, 142, 148, +160, 177, 194, 209, 222, 233, 240, 243, 243, 240, +233, 221, 204, 186, 168, 149, 130, 114, 104, 101, +101, 100, 97, 88, 72, 50, 24, 0, -27, -52, +-77, -97, -114, -125, -131, -137, -144, -157, -175, -196, +-217, -236, -256, -274, -287, -294, -293, -288, -279, -269, +-259, -252, -245, -235, -223, -208, -193, -175, -156, -136, +-116, -99, -85, -77, -77, -84, -95, -104, -111, -114, +-112, -103, -88, -70, -50, -29, -10, 5, 14, 19, +22, 22, 23, 24, 29, 39, 52, 66, 81, 94, +102, 100, 90, 75, 57, 39, 24, 17, 20, 30, +47, 66, 85, 100, 107, 105, 97, 87, 79, 72, +69, 68, 70, 77, 89, 106, 126, 142, 150, 150, +145, 134, 119, 101, 82, 67, 57, 54, 60, 70, +80, 87, 90, 95, 103, 113, 122, 127, 127, 123, +115, 104, 91, 76, 58, 38, 19, 2, -11, -23, +-33, -41, -46, -50, -56, -65, -79, -99, -124, -148, +-162, -165, -156, -136, -109, -80, -57, -42, -36, -37, +-45, -60, -80, -103, -125, -144, -159, -164, -159, -147, +-130, -113, -95, -79, -66, -59, -56, -54, -51, -46, +-39, -30, -21, -12, -4, 5, 16, 24, 28, 34, +39, 41, 44, 47, 50, 55, 62, 73, 88, 102, +113, 119, 117, 110, 103, 100, 100, 105, 112, 117, +117, 114, 111, 107, 98, 86, 71, 58, 45, 37, +32, 31, 28, 20, 8, 0, -2, -5, -23, -55, +-98, -148, -204, -261, -318, -364, -388, -376, -325, -253, +-180, -121, -83, -68, -72, -89, -112, -125, -123, -105, +-75, -33, 22, 69, 70, 19, -58, -130, -164, -151, +-113, -87, -77, -54, -11, 40, 101, 167, 214, 219, +192, 170, 180, 226, 286, 326, 318, 270, 209, 152, +102, 59, 23, -5, -28, -45, -49, -41, -13, 38, +95, 124, 105, 50, -13, -66, -93, -101, -114, -156, +-221, -270, -273, -226, -141, -51, 15, 43, 32, -6, +-76, -161, -207, -179, -90, 33, 178, 325, 439, 504, +538, 561, 563, 526, 455, 364, 279, 238, 250, 294, +348, 392, 413, 388, 314, 221, 128, 32, -58, -122, +-151, -159, -153, -133, -109, -103, -120, -157, -202, -234, +-236, -224, -226, -257, -323, -416, -513, -572, -571, -535, +-496, -476, -495, -578, -713, -843, -915, -913, -854, -753, +-625, -494, -377, -269, -156, -37, 80, 178, 263, 345, +437, 547, 663, 762, 816, 809, 747, 651, 535, 406, +277, 163, 74, 27, 33, 85, 154, 219, 278, 320, +318, 272, 223, 203, 214, 250, 305, 351, 353, 310, +266, 241, 215, 175, 125, 51, -74, -258, -462, -636, +-755, -808, -783, -693, -575, -470, -402, -369, -351, -326, +-284, -241, -212, -178, -117, -15, 121, 266, 387, 468, +509, 515, 487, 434, 371, 306, 242, 201, 189, 180, +164, 156, 161, 151, 111, 56, 2, -43, -63, -29, +46, 119, 156, 154, 117, 64, 25, 34, 87, 131, +115, 23, -109, -235, -329, -387, -414, -415, -409, -411, +-426, -438, -427, -386, -327, -262, -196, -118, -10, 119, +237, 309, 323, 294, 227, 132, 35, -43, -110, -169, +-197, -191, -170, -146, -101, -35, 27, 73, 111, 133, +118, 87, 79, 109, 156, 203, 245, 266, 247, 200, +165, 173, 215, 254, 249, 189, 83, -48, -183, -292, +-348, -345, -310, -277, -257, -242, -208, -139, -52, 16, +38, 30, 28, 48, 93, 167, 247, 293, 291, 259, +222, 180, 137, 98, 46, -42, -166, -287, -384, -446, +-465, -445, -407, -384, -373, -350, -297, -219, -129, -38, +40, 93, 118, 134, 175, 251, 342, 411, 438, 426, +373, 273, 131, -18, -149, -245, -303, -329, -321, -269, +-164, -21, 113, 207, 271, 327, 387, 455, 539, 626, +685, 699, 679, 629, 543, 444, 356, 278, 189, 85, +-23, -129, -219, -259, -228, -151, -77, -37, -35, -59, +-94, -126, -149, -160, -173, -200, -235, -248, -205, -112, +-6, 75, 107, 81, 0, -105, -197, -248, -247, -211, +-173, -155, -139, -86, 8, 103, 163, 172, 131, 55, +-17, -30, 38, 169, 337, 499, 608, 632, 586, 512, +430, 335, 224, 104, -14, -126, -212, -247, -241, -222, +-228, -267, -328, -402, -488, -569, -627, -658, -679, -708, +-727, -706, -638, -536, -426, -335, -293, -314, -391, -502, +-624, -721, -763, -766, -764, -764, -738, -664, -558, -437, +-301, -169, -67, 7, 84, 184, 308, 448, 593, 707, +761, 746, 678, 579, 463, 349, 259, 205, 183, 181, +202, 258, 341, 416, 453, 454, 424, 366, 299, 260, +269, 304, 330, 336, 335, 340, 362, 394, 424, 426, +385, 296, 164, 10, -128, -213, -243, -259, -292, -333, +-364, -372, -347, -283, -199, -126, -78, -45, -9, 46, +134, 258, 400, 533, 643, 722, 767, 780, 766, 730, +679, 606, 507, 394, 300, 240, 194, 140, 71, 0, +-65, -115, -133, -112, -65, -23, -6, -17, -52, -92, +-120, -127, -112, -78, -37, -25, -74, -168, -258, -321, +-369, -418, -479, -559, -653, -729, -758, -729, -661, -569, +-470, -375, -289, -206, -115, -11, 86, 158, 197, 202, +175, 124, 72, 31, -13, -79, -153, -195, -181, -118, +-27, 64, 134, 167, 158, 129, 99, 81, 78, 76, +49, -21, -118, -195, -223, -199, -116, 11, 131, 184, +162, 104, 37, -38, -127, -222, -319, -406, -461, -462, +-412, -339, -270, -217, -185, -184, -213, -248, -263, -250, +-215, -153, -61, 44, 140, 224, 297, 332, 299, 199, +64, -64, -169, -239, -263, -244, -205, -166, -143, -138, +-140, -122, -66, 8, 69, 104, 120, 123, 118, 133, +200, 312, 427, 500, 511, 461, 358, 226, 93, -22, +-117, -191, -233, -235, -200, -131, -36, 63, 142, 183, +205, 239, 299, 381, 475, 567, 632, 658, 653, 637, +617, 566, 458, 298, 117, -47, -165, -215, -196, -128, +-42, 29, 57, 32, -23, -77, -120, -158, -191, -214, +-233, -254, -262, -229, -149, -44, 49, 105, 121, 109, +88, 69, 41, -3, -60, -101, -99, -56, 8, 71, +114, 113, 64, -1, -52, -71, -51, 12, 124, 266, +401, 502, 566, 601, 610, 580, 507, 391, 245, 90, +-39, -128, -174, -178, -162, -163, -211, -296, -390, -476, +-552, -598, -605, -598, -602, -622, -641, -635, -593, -521, +-441, -384, -362, -367, -376, -387, -412, -460, -519, -567, +-591, -591, -556, -478, -375, -272, -183, -107, -39, 30, +122, 251, 403, 537, 615, 631, 604, 564, 528, 496, +451, 384, 308, 242, 202, 193, 222, 281, 341, 370, +363, 325, 267, 202, 150, 128, 133, 144, 143, 122, +94, 71, 63, 65, 64, 49, 20, 0, 1, 2, +-23, -89, -186, -300, -415, -503, -535, -507, -444, -375, +-314, -270, -248, -233, -195, -110, 11, 152, 294, 426, +539, 637, 722, 787, 823, 823, 780, 682, 536, 383, +256, 162, 87, 23, -33, -79, -107, -105, -71, -18, +24, 32, -4, -72, -148, -206, -227, -212, -186, -173, +-165, -145, -120, -112, -135, -192, -288, -421, -565, -682, +-743, -740, -684, -595, -498, -419, -365, -325, -282, -227, +-159, -84, -9, 57, 112, 156, 184, 191, 183, 164, +129, 79, 39, 33, 61, 109, 162, 219, 277, 330, +362, 364, 341, 297, 235, 155, 61, -39, -125, -163, +-135, -56, 39, 130, 212, 269, 283, 253, 192, 107, +-2, -131, -257, -354, -400, -386, -316, -223, -150, -126, +-155, -224, -303, -358, -370, -337, -265, -156, -22, 111, +227, 314, 357, 335, 243, 114, -10, -104, -161, -189, +-202, -207, -218, -239, -250, -231, -172, -83, 7, 63, +62, 22, -2, 28, 108, 202, 281, 328, 344, 332, +296, 241, 170, 83, -15, -112, -194, -249, -269, -252, +-204, -139, -70, -8, 36, 66, 100, 151, 211, 277, +357, 444, 525, 584, 615, 612, 562, 462, 327, 186, +72, 2, -21, -3, 42, 90, 109, 90, 43, -16, +-68, -88, -76, -62, -79, -116, -151, -162, -141, -89, +-6, 86, 162, 205, 221, 222, 219, 215, 209, 191, +154, 102, 50, 12, -8, -18, -37, -74, -119, -144, +-133, -92, -33, 39, 120, 206, 288, 367, 438, 494, +510, 469, 378, 259, 138, 32, -42, -86, -120, -175, +-261, -371, -493, -602, -662, -653, -599, -550, -543, -578, +-632, -678, -695, -673, -623, -563, -507, -457, -412, -380, +-368, -374, -403, -445, -491, -537, -575, -591, -570, -514, +-440, -354, -255, -150, -55, 24, 88, 142, 189, 225, +253, 285, 333, 391, 440, 461, 449, 407, 348, 299, +280, 293, 322, 349, 352, 310, 227, 138, 85, 93, +144, 202, 229, 211, 155, 80, 13, -27, -37, -8, +53, 129, 196, 235, 240, 204, 130, 29, -95, -227, +-337, -388, -382, -348, -311, -279, -242, -195, -141, -78, +-4, 75, 148, 219, 310, 442, 610, 784, 933, 1028, +1047, 990, 880, 742, 592, 447, 329, 244, 177, 112, +48, 4, 0, 37, 98, 153, 174, 149, 84, 0, +-86, -155, -188, -179, -138, -82, -34, -10, -22, -68, +-148, -267, -412, -554, -657, -703, -696, -665, -630, -589, +-546, -512, -491, -462, -407, -335, -267, -208, -151, -88, +-17, 69, 164, 242, 280, 270, 222, 156, 102, 96, +155, 259, 357, 411, 416, 393, 357, 320, 280, 226, +151, 64, -19, -83, -111, -98, -46, 33, 132, 232, +315, 365, 376, 345, 260, 122, -42, -189, -286, -325, +-328, -315, -305, -312, -354, -434, -522, -583, -602, -587, +-546, -480, -388, -267, -125, 15, 129, 199, 225, 214, +171, 98, 6, -77, -133, -165, -186, -207, -232, -250, +-252, -225, -171, -99, -26, 32, 74, 105, 134, 163, +191, 218, 238, 248, 246, 244, 248, 250, 230, 169, +76, -23, -111, -180, -227, -241, -228, -210, -205, -203, +-183, -136, -68, 9, 89, 166, 238, 303, 356, 389, +397, 385, 358, 311, 239, 158, 97, 79, 104, 143, +161, 137, 83, 23, -18, -32, -23, -16, -27, -50, +-65, -64, -49, -26, 6, 48, 100, 159, 225, 299, +377, 444, 473, 451, 389, 300, 191, 79, -11, -66, +-100, -130, -162, -187, -195, -183, -153, -114, -67, -13, +48, 120, 198, 276, 348, 408, 445, 444, 400, 325, +240, 158, 77, -13, -124, -248, -370, -465, -514, -512, +-476, -438, -421, -428, -458, -501, -544, -570, -569, -540, +-501, -471, -444, -399, -331, -259, -208, -192, -215, -283, +-378, -464, -508, -502, -459, -392, -311, -223, -142, -75, +-30, -3, 11, 25, 50, 89, 139, 200, 274, 352, +415, 446, 436, 403, 373, 361, 365, 373, 364, 324, +253, 180, 139, 142, 176, 207, 205, 162, 90, 7, +-69, -116, -116, -80, -31, 23, 91, 164, 221, 244, +236, 201, 136, 34, -93, -225, -332, -399, -424, -408, +-366, -318, -273, -229, -181, -134, -88, -31, 49, 164, +313, 489, 675, 846, 963, 1000, 960, 868, 750, 628, +522, 433, 347, 247, 145, 65, 30, 46, 91, 134, +156, 149, 110, 42, -31, -80, -98, -100, -96, -86, +-69, -55, -57, -79, -122, -185, -267, -359, -444, -511, +-560, -602, -643, -676, -692, -681, -637, -569, -503, -461, +-441, -422, -385, -323, -237, -124, 7, 128, 213, 245, +236, 205, 180, 190, 245, 330, 408, 449, 442, 405, +359, 310, 261, 219, 183, 137, 69, -4, -59, -76, +-57, -10, 54, 131, 208, 271, 309, 317, 296, 254, +196, 128, 54, -24, -105, -186, -266, -346, -425, -496, +-552, -589, -608, -607, -585, -548, -509, -471, -414, -316, +-179, -32, 91, 163, 173, 136, 81, 37, 21, 24, +13, -29, -93, -153, -198, -220, -203, -136, -37, 57, +128, 173, 198, 204, 191, 164, 134, 111, 101, 106, +129, 166, 200, 211, 192, 144, 73, -4, -75, -143, +-220, -306, -379, -406, -377, -303, -207, -108, -25, 25, +43, 46, 56, 89, 143, 208, 269, 309, 317, 293, +252, 225, 223, 233, 231, 212, 177, 123, 52, -15, +-47, -34, 1, 32, 45, 49, 53, 58, 64, 79, +113, 164, 235, 327, 436, 541, 619, 655, 640, 576, +475, 363, 256, 150, 40, -65, -146, -192, -211, -207, +-179, -133, -83, -50, -45, -55, -56, -23, 55, 170, +299, 404, 450, 432, 373, 297, 204, 93, -28, -149, +-258, -353, -428, -471, -479, -460, -440, -432, -433, -438, +-456, -494, -545, -593, -628, -638, -615, -558, -473, -371, +-273, -202, -177, -202, -253, -302, -337, -361, -377, -376, +-354, -317, -278, -240, -201, -167, -146, -144, -153, -154, +-131, -82, -1, 106, 223, 317, 372, 399, 408, 409, +401, 387, 374, 358, 333, 293, 252, 228, 229, 234, +220, 181, 119, 48, -13, -52, -59, -44, -24, -5, +20, 63, 133, 225, 313, 356, 333, 255, 150, 42, +-62, -162, -247, -304, -332, -341, -338, -322, -288, -240, +-185, -125, -54, 28, 123, 233, 369, 522, 665, 768, +818, 821, 790, 736, 665, 587, 509, 426, 334, 242, +172, 137, 126, 121, 114, 108, 102, 96, 91, 84, +70, 45, 13, -21, -59, -101, -136, -158, -169, -177, +-186, -200, -222, -262, -329, -415, -497, -561, -607, -640, +-661, -660, -640, -613, -584, -545, -498, -447, -387, -311, +-212, -100, 0, 74, 121, 161, 206, 262, 330, 407, +475, 508, 493, 449, 397, 348, 305, 266, 224, 173, +110, 45, -4, -26, -18, 8, 37, 55, 62, 75, +114, 180, 250, 299, 318, 313, 288, 236, 150, 32, +-105, -247, -384, -494, -565, -604, -629, -647, -657, -659, +-658, -651, -630, -580, -491, -378, -268, -176, -100, -37, +12, 54, 96, 131, 138, 102, 27, -61, -133, -168, +-153, -96, -17, 66, 142, 205, 247, 264, 254, 222, +173, 115, 63, 34, 40, 77, 130, 192, 260, 322, +351, 324, 249, 142, 18, -102, -199, -257, -275, -256, +-212, -153, -98, -66, -76, -119, -157, -153, -101, -25, +50, 107, 142, 161, 179, 212, 261, 312, 341, 331, +280, 200, 113, 43, 8, 10, 30, 52, 67, 68, +57, 40, 34, 49, 79, 122, 180, 258, 357, 459, +545, 610, 654, 665, 638, 577, 494, 388, 261, 126, +6, -76, -119, -129, -118, -93, -71, -72, -109, -161, +-195, -187, -131, -29, 105, 242, 347, 399, 401, 369, +319, 265, 207, 136, 43, -71, -191, -287, -341, -355, +-345, -325, -310, -316, -349, -401, -459, -514, -563, -598, +-603, -570, -513, -449, -386, -328, -276, -235, -202, -175, +-154, -145, -152, -171, -192, -215, -244, -276, -295, -293, +-285, -294, -325, -360, -376, -357, -296, -193, -69, 42, +121, 167, 199, 227, 255, 284, 314, 338, 346, 338, +319, 289, 243, 185, 128, 85, 49, 7, -39, -80, +-110, -138, -163, -170, -147, -95, -20, 64, 139, 188, +209, 206, 187, 160, 124, 75, 14, -53, -123, -196, +-266, -307, -300, -249, -180, -114, -58, -11, 32, 79, +142, 234, 347, 461, 552, 613, 641, 640, 628, 623, +627, 622, 594, 544, 480, 403, 317, 238, 185, 154, +134, 123, 134, 164, 188, 180, 134, 58, -30, -114, +-180, -220, -237, -240, -233, -224, -215, -213, -226, -251, +-283, -324, -389, -482, -583, -661, -698, -694, -663, -619, +-570, -528, -497, -467, -423, -352, -259, -155, -51, 45, +136, 229, 329, 428, 505, 544, 552, 542, 517, 469, +399, 323, 251, 187, 136, 109, 103, 108, 108, 95, +70, 42, 21, 14, 30, 77, 146, 223, 293, 348, +379, 369, 316, 234, 139, 30, -98, -239, -371, -477, +-554, -602, -623, -622, -616, -622, -642, -660, -667, -650, +-602, -520, -413, -299, -186, -73, 32, 116, 164, 183, +180, 158, 119, 80, 63, 76, 110, 153, 198, 242, +285, 321, 339, 321, 266, 183, 91, 11, -28, -19, +31, 106, 199, 292, 361, 383, 353, 285, 199, 106, +14, -63, -117, -154, -184, -205, -217, -225, -242, -272, +-308, -335, -350, -346, -317, -268, -211, -150, -78, 9, +102, 179, 228, 247, 234, 191, 133, 86, 63, 59, +61, 57, 45, 31, 23, 22, 31, 52, 82, 117, +158, 208, 267, 333, 403, 478, 554, 615, 643, 627, +579, 515, 441, 353, 259, 169, 92, 35, 0, -13, +-24, -53, -108, -175, -231, -261, -257, -216, -144, -65, +1, 54, 102, 142, 166, 176, 173, 148, 96, 20, +-64, -136, -185, -213, -234, -255, -277, -306, -345, -388, +-427, -462, -499, -535, -562, -577, -582, -577, -556, -507, +-426, -330, -233, -144, -65, -2, 34, 47, 41, 16, +-29, -89, -150, -203, -247, -284, -311, -333, -351, -363, +-351, -302, -225, -145, -77, -25, 13, 48, 97, 170, +262, 351, 415, 443, 440, 418, 380, 329, 270, 210, +149, 87, 27, -23, -60, -90, -112, -123, -117, -99, +-81, -65, -42, 0, 56, 114, 167, 213, 247, 258, +246, 210, 150, 65, -29, -102, -133, -125, -92, -46, +-3, 20, 26, 33, 59, 108, 168, 227, 280, 326, +373, 424, 488, 565, 646, 706, 728, 712, 661, 583, +484, 384, 300, 241, 208, 197, 205, 223, 234, 223, +186, 130, 59, -29, -132, -232, -306, -349, -363, -352, +-318, -268, -219, -187, -177, -198, -259, -356, -466, -565, +-639, -680, -685, -661, -630, -613, -612, -613, -603, -568, +-503, -409, -299, -189, -87, 7, 109, 225, 341, 438, +504, 533, 526, 488, 436, 381, 331, 285, 246, 221, +214, 217, 204, 163, 105, 49, 3, -30, -43, -24, +24, 85, 143, 196, 237, 260, 265, 255, 228, 172, +80, -41, -179, -315, -425, -485, -494, -480, -477, -503, +-555, -620, -678, -714, -715, -676, -606, -521, -428, -323, +-208, -97, 0, 78, 137, 177, 196, 200, 194, 189, +189, 195, 213, 246, 290, 325, 333, 315, 279, 226, +152, 67, -3, -34, -18, 36, 110, 180, 227, 246, +250, 252, 250, 239, 215, 169, 92, -6, -106, -182, +-226, -247, -262, -286, -321, -368, -422, -464, -470, -434, +-372, -296, -215, -131, -49, 29, 99, 154, 190, 207, +211, 211, 215, 217, 199, 157, 108, 72, 56, 57, +71, 103, 149, 196, 237, 273, 311, 351, 393, 438, +480, 512, 528, 532, 527, 513, 498, 484, 465, 429, +364, 275, 178, 95, 31, -16, -54, -87, -120, -156, +-188, -204, -199, -178, -150, -117, -77, -29, 18, 54, +70, 71, 60, 42, 28, 25, 27, 11, -31, -93, +-155, -209, -257, -298, -324, -332, -335, -348, -380, -431, +-489, -536, -549, -523, -472, -405, -329, -247, -162, -70, +26, 122, 193, 212, 170, 82, -24, -131, -225, -297, +-343, -365, -375, -380, -377, -365, -348, -330, -314, -296, +-266, -216, -146, -60, 37, 135, 214, 267, 304, 330, +337, 315, 261, 192, 115, 32, -47, -109, -139, -140, +-125, -106, -96, -102, -119, -133, -132, -114, -79, -25, +45, 118, 180, 226, 256, 266, 248, 199, 130, 62, +5, -34, -48, -30, 14, 63, 102, 122, 127, 125, +117, 103, 88, 88, 114, 167, 248, 357, 475, 576, +641, 670, 672, 649, 601, 532, 461, 403, 357, 319, +285, 261, 249, 248, 253, 247, 213, 142, 37, -84, +-203, -296, -346, -351, -326, -288, -247, -201, -150, -113, +-111, -149, -217, -302, -389, -467, -522, -553, -568, -583, +-604, -623, -625, -605, -569, -520, -453, -368, -274, -173, +-60, 65, 189, 290, 361, 408, 434, 439, 426, 408, +395, 389, 382, 366, 336, 290, 239, 190, 147, 107, +68, 40, 27, 29, 40, 57, 82, 111, 135, 156, +179, 205, 217, 203, 153, 74, -21, -121, -207, -273, +-315, -336, -355, -391, -450, -521, -591, -651, -692, -707, +-693, -661, -625, -578, -505, -407, -299, -195, -100, -10, +69, 139, 202, 254, 294, 321, 341, 355, 359, 353, +338, 317, 288, 244, 192, 144, 106, 76, 53, 42, +43, 47, 50, 59, 87, 139, 203, 267, 310, 317, +281, 206, 109, 15, -57, -114, -170, -238, -313, -383, +-444, -487, -500, -479, -436, -390, -345, -294, -236, -178, +-121, -61, 7, 78, 147, 205, 246, 264, 261, 243, +216, 184, 149, 121, 111, 123, 157, 209, 273, 341, +399, 442, 471, 489, 493, 477, 448, 419, 408, 421, +457, 501, 538, 548, 514, 433, 327, 226, 150, 99, +64, 36, 6, -34, -86, -135, -163, -171, -172, -178, +-182, -182, -180, -177, -171, -158, -133, -94, -43, 9, +50, 66, 51, 8, -52, -118, -172, -204, -216, -227, +-246, -274, -309, -354, -404, -451, -482, -496, -499, -492, +-475, -436, -364, -258, -126, 18, 151, 237, 252, 198, +100, -6, -104, -182, -232, -255, -264, -279, -304, -331, +-355, -380, -401, -410, -397, -357, -297, -230, -164, -100, +-27, 57, 152, 239, 299, 322, 305, 254, 179, 98, +36, 0, -15, -18, -15, -15, -25, -51, -91, -131, +-153, -150, -131, -106, -77, -45, -8, 35, 90, 155, +216, 253, 252, 218, 172, 127, 98, 98, 136, 196, +251, 279, 274, 242, 189, 125, 65, 22, 11, 36, +92, 166, 241, 309, 370, 428, 478, 514, 539, 553, +549, 516, 460, 400, 354, 330, 328, 335, 340, 329, +288, 210, 104, -6, -104, -180, -233, -268, -290, -301, +-306, -301, -275, -226, -173, -138, -132, -156, -210, -286, +-365, -430, -474, -508, -543, -578, -601, -605, -590, -562, +-524, -473, -399, -296, -173, -52, 48, 120, 167, 197, +217, 242, 282, 334, 385, 421, 436, 429, 398, 347, +282, 218, 170, 136, 110, 82, 53, 28, 16, 19, +36, 59, 78, 81, 66, 47, 39, 41, 45, 46, +40, 23, -10, -59, -113, -159, -199, -241, -293, -349, +-405, -460, -515, -572, -623, -660, -672, -656, -622, -576, +-516, -439, -345, -242, -131, -11, 112, 229, 329, 405, +458, 488, 490, 463, 420, 376, 340, 312, 287, 262, +236, 206, 166, 116, 68, 29, 0, -17, -17, 7, +56, 121, 192, 262, 314, 330, 304, 239, 154, 63, +-33, -134, -235, -327, -396, -436, -449, -449, -444, -438, +-428, -416, -399, -371, -327, -271, -209, -145, -75, 3, +83, 153, 204, 237, 252, 248, 221, 182, 150, 145, +173, 225, 292, 365, 436, 488, 514, 516, 502, 470, +422, 370, 339, 340, 371, 426, 486, 533, 546, 516, +454, 382, 317, 263, 217, 173, 126, 80, 39, 5, +-26, -64, -104, -146, -191, -242, -298, -346, -375, -376, +-346, -288, -211, -131, -70, -36, -22, -16, -13, -18, +-39, -74, -115, -153, -191, -228, -263, -292, -317, -347, +-376, -403, -426, -450, -472, -472, -433, -351, -232, -93, +44, 158, 224, 233, 196, 133, 64, 4, -42, -84, +-126, -175, -227, -282, -338, -388, -425, -446, -454, -453, +-443, -419, -377, -317, -243, -154, -60, 22, 81, 114, +126, 127, 120, 106, 89, 73, 58, 42, 21, -2, +-24, -49, -75, -102, -122, -127, -121, -111, -106, -103, +-96, -76, -34, 33, 120, 200, 252, 266, 249, 227, +228, 260, 318, 377, 419, 432, 412, 360, 286, 207, +138, 91, 65, 55, 56, 61, 70, 87, 121, 177, +254, 334, 403, 452, 484, 504, 511, 509, 503, 494, +481, 456, 420, 370, 307, 229, 146, 73, 19, -20, +-60, -110, -174, -245, -310, -351, -355, -323, -260, -186, +-123, -91, -93, -124, -169, -222, -275, -325, -370, -413, +-459, -508, -547, -561, -541, -484, -400, -304, -213, -137, +-81, -45, -23, -1, 30, 74, 130, 199, 276, 347, +400, 428, 434, 418, 383, 336, 283, 233, 186, 141, +106, 90, 96, 116, 139, 155, 150, 114, 50, -25, +-84, -103, -77, -24, 25, 48, 40, 11, -25, -61, +-94, -125, -155, -190, -237, -297, -364, -430, -492, -547, +-593, -632, -656, -667, -666, -648, -602, -522, -409, -271, +-119, 36, 181, 302, 390, 439, 454, 437, 403, 372, +357, 355, 350, 329, 294, 251, 204, 158, 117, 77, +33, -17, -72, -114, -121, -76, 16, 132, 242, 322, +359, 348, 289, 193, 80, -26, -113, -180, -234, -285, +-334, -377, -413, -441, -458, -461, -455, -449, -440, -427, +-401, -361, -304, -231, -146, -53, 37, 117, 176, 210, +214, 194, 171, 168, 196, 252, 323, 395, 454, 491, +504, 498, 482, 466, 452, 435, 409, 379, 360, 366, +396, 437, 473, 494, 493, 469, 425, 373, 326, 287, +258, 236, 213, 189, 158, 114, 51, -28, -115, -200, +-279, -344, -387, -405, -396, -368, -329, -283, -237, -194, +-151, -105, -55, -12, 9, 6, -15, -44, -74, -102, +-127, -153, -186, -227, -274, -317, -344, -351, -340, -325, +-309, -285, -240, -170, -85, 2, 78, 136, 174, 192, +193, 177, 149, 108, 57, -4, -71, -135, -197, -260, +-321, -373, -414, -442, -458, -456, -431, -382, -322, -264, +-218, -185, -160, -139, -108, -64, -19, 15, 35, 41, +40, 35, 25, 9, -12, -34, -55, -74, -90, -97, +-94, -87, -87, -99, -118, -129, -123, -100, -59, -7, +49, 108, 168, 225, 283, 343, 404, 459, 493, 498, +477, 435, 381, 326, 279, 241, 207, 166, 115, 63, +24, 2, 0, 18, 55, 101, 149, 200, 258, 325, +400, 471, 529, 558, 551, 513, 454, 386, 323, 268, +215, 161, 109, 67, 36, 3, -47, -123, -212, -298, +-357, -377, -357, -310, -252, -198, -158, -134, -122, -123, +-141, -179, -233, -298, -363, -417, -456, -472, -457, -410, +-344, -275, -216, -171, -145, -134, -126, -111, -87, -55, +-18, 27, 86, 159, 238, 308, 361, 386, 384, 360, +319, 271, 224, 185, 158, 150, 163, 190, 215, 221, +197, 140, 62, -19, -85, -125, -134, -117, -86, -55, +-35, -28, -31, -39, -48, -61, -76, -96, -126, -166, +-216, -266, -312, -360, -416, -478, -544, -611, -669, -707, +-711, -673, -591, -473, -334, -186, -42, 87, 194, 274, +330, 370, 398, 415, 424, 425, 417, 396, 366, 329, +294, 262, 232, 197, 143, 68, -20, -99, -147, -145, +-94, -5, 95, 185, 244, 266, 255, 215, 155, 84, +18, -42, -103, -167, -233, -294, -349, -393, -419, -430, +-433, -440, -455, -473, -483, -476, -448, -403, -344, -276, +-198, -118, -47, 10, 55, 95, 137, 188, 253, 326, +395, 446, 476, 488, 496, 512, 537, 560, 568, 555, +521, 476, 434, 404, 393, 401, 421, 439, 446, 441, +427, 404, 384, 376, 381, 388, 387, 372, 340, 289, +222, 140, 50, -40, -129, -212, -284, -339, -374, -395, +-410, -419, -416, -391, -345, -283, -216, -155, -107, -73, +-50, -36, -29, -30, -45, -79, -133, -192, -241, -268, +-269, -252, -227, -204, -190, -186, -191, -194, -183, -153, +-105, -43, 24, 87, 131, 155, 160, 152, 133, 103, +60, 1, -70, -154, -246, -331, -392, -422, -426, -417, +-403, -389, -374, -365, -363, -366, -370, -366, -349, -315, +-263, -200, -140, -92, -62, -46, -32, -16, -5, -9, +-32, -65, -97, -115, -117, -107, -96, -90, -96, -115, +-138, -155, -160, -151, -118, -57, 28, 128, 228, 321, +399, 457, 496, 515, 519, 513, 499, 475, 440, 400, +359, 315, 263, 206, 151, 102, 60, 21, -14, -38, +-39, -8, 54, 146, 255, 362, 449, 501, 515, 501, +471, 431, 386, 335, 280, 228, 185, 153, 123, 93, +60, 17, -40, -111, -186, -255, -311, -341, -338, -305, +-254, -201, -160, -134, -125, -135, -166, -210, -256, -295, +-320, -330, -318, -285, -239, -195, -163, -142, -124, -109, +-96, -86, -78, -69, -61, -49, -28, 15, 84, 165, +239, 290, 311, 308, 294, 282, 275, 270, 268, 269, +273, 273, 268, 255, 229, 183, 123, 58, -2, -55, +-100, -134, -154, -158, -149, -132, -110, -89, -75, -72, +-80, -90, -97, -104, -117, -139, -168, -204, -254, -324, +-410, -500, -581, -642, -670, -657, -606, -527, -440, -354, +-267, -174, -72, 32, 132, 218, 285, 338, 379, 406, +419, 419, 413, 399, 374, 341, 300, 248, 185, 114, +46, -6, -38, -48, -38, -11, 24, 62, 91, 109, +115, 111, 100, 82, 56, 22, -25, -88, -161, -227, +-278, -315, -345, -375, -403, -432, -457, -478, -491, -490, +-475, -456, -438, -421, -400, -368, -317, -248, -167, -78, +16, 116, 211, 291, 355, 402, 435, 458, 473, 491, +514, 539, 558, 565, 562, 552, 533, 507, 478, 446, +414, 381, 353, 331, 322, 323, 334, 357, 390, 424, +447, 445, 417, 366, 298, 220, 137, 54, -22, -98, +-173, -245, -305, -351, -384, -411, -434, -454, -465, -452, +-412, -349, -278, -208, -145, -93, -54, -32, -33, -55, +-98, -147, -190, -208, -197, -165, -126, -89, -64, -59, +-74, -102, -126, -130, -111, -76, -33, 10, 51, 89, +124, 158, 185, 196, 180, 129, 51, -38, -123, -192, +-240, -266, -280, -292, -302, -310, -317, -329, -349, -378, +-410, -438, -448, -435, -402, -360, -313, -264, -213, -163, +-116, -75, -42, -22, -20, -32, -47, -56, -57, -52, +-45, -41, -47, -68, -103, -143, -173, -180, -158, -105, +-28, 65, 161, 249, 320, 375, 424, 468, 505, 530, +541, 540, 526, 506, 486, 466, 438, 397, 337, 258, +170, 84, 8, -48, -79, -82, -49, 15, 104, 199, +283, 347, 385, 398, 394, 384, 371, 350, 315, 271, +225, 185, 151, 127, 109, 91, 62, 14, -51, -126, +-199, -259, -295, -301, -282, -251, -225, -215, -218, -226, +-230, -229, -226, -222, -219, -213, -203, -194, -187, -177, +-163, -143, -119, -95, -74, -58, -52, -57, -69, -79, +-75, -51, -14, 24, 57, 78, 91, 101, 118, 146, +183, 223, 260, 290, 306, 301, 274, 236, 203, 177, +155, 126, 85, 33, -27, -90, -142, -171, -175, -166, +-157, -155, -156, -159, -158, -147, -126, -102, -78, -60, +-59, -83, -133, -205, -287, -372, -448, -503, -526, -518, +-493, -464, -440, -413, -372, -312, -233, -142, -51, 27, +94, 156, 221, 288, 354, 407, 441, 449, 430, 385, +324, 258, 199, 148, 108, 82, 70, 66, 61, 48, +32, 20, 15, 18, 26, 39, 51, 60, 59, 44, +17, -21, -67, -118, -170, -220, -264, -302, -335, -365, +-393, -410, -411, -402, -400, -414, -443, -477, -503, -509, +-482, -420, -329, -222, -111, -5, 92, 181, 260, 332, +399, 452, 488, 506, 512, 518, 530, 555, 589, 624, +644, 636, 594, 531, 462, 402, 354, 316, 293, 288, +306, 345, 393, 439, 471, 480, 467, 436, 395, 345, +290, 228, 155, 72, -12, -85, -138, -178, -218, -266, +-326, -391, -452, -494, -500, -468, -405, -330, -256, -192, +-146, -119, -111, -116, -127, -139, -143, -135, -114, -85, +-54, -26, -1, 14, 17, 8, -9, -28, -44, -53, +-56, -48, -26, 11, 58, 105, 141, 159, 151, 119, +67, 1, -64, -117, -148, -164, -178, -198, -225, -253, +-278, -302, -328, -362, -402, -447, -489, -516, -521, -505, +-475, -437, -396, -354, -315, -276, -237, -196, -154, -114, +-80, -53, -38, -36, -45, -58, -75, -99, -130, -163, +-185, -185, -159, -111, -51, 11, 73, 134, 196, 262, +328, 390, 443, 483, 510, 528, 545, 566, 586, 592, +572, 524, 454, 370, 283, 198, 117, 45, -13, -53, +-64, -48, -7, 47, 104, 158, 203, 239, 263, 282, +297, 306, 306, 295, 275, 251, 227, 202, 178, 152, +123, 88, 42, -8, -57, -101, -135, -159, -179, -198, +-221, -249, -273, -284, -276, -245, -200, -152, -115, -93, +-84, -80, -76, -72, -69, -68, -68, -66, -56, -37, +-16, -5, -9, -25, -40, -50, -54, -54, -56, -60, +-65, -63, -43, 2, 74, 154, 225, 272, 291, 287, +268, 242, 216, 192, 167, 137, 99, 54, 5, -40, +-76, -103, -127, -154, -185, -217, -242, -254, -247, -217, +-171, -119, -76, -47, -39, -54, -89, -139, -196, -253, +-305, -347, -369, -374, -372, -374, -380, -380, -367, -341, +-304, -260, -209, -153, -92, -26, 48, 133, 223, 309, +380, 423, 435, 413, 366, 308, 257, 222, 205, 197, +188, 171, 144, 112, 79, 47, 18, -4, -21, -32, +-40, -41, -33, -17, 0, 8, 0, -21, -52, -94, +-143, -192, -237, -275, -303, -313, -308, -301, -311, -351, +-416, -488, -546, -577, -570, -526, -456, -376, -297, -217, +-129, -25, 88, 199, 296, 368, 413, 437, 448, 459, +481, 520, 570, 617, 647, 648, 619, 566, 499, 429, +369, 328, 304, 291, 282, 281, 296, 325, 361, 394, +418, 429, 420, 392, 346, 287, 219, 150, 88, 41, +7, -25, -70, -135, -212, -293, -367, -420, -443, -435, +-407, -373, -344, -323, -307, -292, -273, -246, -208, -162, +-115, -74, -46, -28, -11, 14, 49, 83, 106, 110, +96, 69, 37, 7, -11, -10, 5, 27, 50, 72, +89, 96, 89, 72, 51, 33, 21, 16, 11, -2, +-31, -75, -121, -161, -191, -217, -247, -286, -339, -405, +-473, -526, -552, -551, -535, -519, -509, -502, -491, -470, +-432, -375, -304, -227, -156, -102, -71, -66, -81, -105, +-131, -151, -165, -171, -171, -167, -159, -139, -100, -42, +21, 85, 144, 197, 243, 286, 327, 370, 417, 468, +523, 582, 637, 669, 670, 635, 575, 500, 421, 347, +280, 220, 161, 103, 52, 18, 6, 16, 38, 65, +91, 114, 131, 144, 155, 170, 192, 215, 236, 245, +240, 218, 186, 149, 115, 86, 64, 50, 39, 23, +0, -33, -81, -142, -211, -273, -313, -325, -310, -275, +-226, -172, -121, -77, -36, 0, 26, 32, 20, -1, +-22, -31, -25, -2, 29, 59, 76, 75, 55, 22, +-19, -66, -113, -154, -179, -184, -166, -127, -72, -6, +62, 126, 179, 213, 226, 220, 197, 163, 126, 93, +71, 55, 37, 15, -10, -39, -71, -110, -155, -198, +-233, -251, -248, -223, -183, -145, -119, -106, -101, -97, +-94, -97, -108, -128, -157, -187, -209, -217, -211, -202, +-201, -213, -235, -256, -268, -265, -247, -215, -173, -122, +-63, 2, 75, 147, 213, 265, 296, 307, 300, 285, +267, 251, 241, 237, 235, 226, 209, 185, 158, 123, +79, 27, -24, -67, -95, -106, -98, -74, -48, -31, +-28, -38, -58, -85, -116, -148, -174, -190, -198, -203, +-214, -236, -275, -330, -395, -454, -499, -524, -531, -522, +-496, -455, -398, -327, -243, -155, -65, 23, 107, 185, +252, 306, 352, 396, 440, 487, 537, 581, 609, 610, +585, 546, 502, 459, 422, 392, 367, 339, 309, 285, +278, 291, 318, 346, 371, 387, 394, 389, 374, 351, +322, 286, 245, 204, 164, 125, 79, 18, -56, -136, +-213, -275, -316, -338, -348, -358, -374, -393, -414, -426, +-420, -392, -344, -283, -217, -153, -95, -45, -3, 36, +81, 125, 156, 170, 165, 147, 122, 100, 91, 94, +102, 105, 97, 79, 57, 35, 14, -2, -9, -5, +3, 11, 15, 13, 3, -11, -31, -54, -81, -112, +-154, -208, -269, -333, -392, -441, -475, -499, -518, -535, +-557, -582, -607, -621, -607, -558, -477, -379, -283, -207, +-163, -150, -158, -169, -176, -182, -188, -193, -192, -183, +-164, -129, -83, -29, 20, 62, 98, 129, 161, 192, +224, 260, 307, 367, 435, 507, 574, 624, 646, 637, +604, 563, 519, 476, 430, 377, 314, 248, 188, 140, +105, 81, 66, 56, 48, 37, 22, 11, 10, 23, +48, 83, 122, 155, 169, 163, 141, 117, 102, 102, +119, 143, 156, 145, 110, 58, 0, -60, -126, -194, +-255, -298, -319, -315, -285, -234, -171, -107, -50, -2, +35, 57, 62, 50, 32, 17, 16, 35, 70, 108, +137, 147, 135, 99, 46, -14, -68, -111, -143, -171, +-193, -199, -185, -148, -90, -18, 50, 104, 135, 143, +135, 118, 99, 86, 80, 76, 67, 50, 25, -2, +-32, -68, -108, -145, -169, -179, -182, -187, -197, -209, +-220, -223, -216, -197, -173, -152, -138, -130, -123, -113, +-94, -70, -49, -39, -45, -66, -98, -138, -177, -203, +-209, -194, -169, -138, -107, -78, -51, -23, 12, 58, +109, 157, 193, 217, 230, 235, 243, 258, 278, 292, +289, 267, 233, 193, 150, 103, 51, 2, -38, -68, +-85, -89, -84, -81, -87, -104, -125, -140, -142, -133, +-118, -106, -104, -114, -136, -170, -213, -262, -312, -362, +-409, -453, -485, -493, -478, -443, -396, -343, -288, -236, +-188, -139, -81, -12, 65, 148, 231, 310, 379, 439, +491, 531, 556, 561, 550, 530, 513, 499, 484, 465, +443, 421, 399, 379, 367, 360, 355, 346, 334, 320, +310, 306, 306, 305, 299, 285, 266, 241, 210, 171, +128, 87, 52, 16, -24, -69, -113, -158, -203, -250, +-300, -351, -403, -450, -485, -497, -479, -429, -357, -273, +-189, -111, -45, 12, 64, 111, 146, 165, 172, 175, +181, 192, 206, 218, 221, 207, 174, 129, 82, 41, +10, -14, -32, -43, -47, -41, -24, 0, 22, 36, +37, 21, -13, -62, -117, -169, -217, -262, -303, -338, +-367, -396, -432, -478, -530, -581, -626, -655, -662, -643, +-601, -543, -476, -411, -354, -311, -285, -271, -262, -259, +-259, -258, -249, -224, -186, -134, -78, -24, 21, 55, +75, 90, 105, 123, 150, 188, 239, 297, 353, 404, +444, 472, 488, 498, 503, 502, 490, 473, 452, 433, +411, 383, 349, 307, 258, 208, 162, 124, 94, 64, +31, -1, -22, -23, -4, 27, 62, 85, 88, 74, +56, 55, 75, 110, 147, 174, 187, 189, 180, 163, +137, 94, 32, -45, -128, -200, -248, -265, -253, -217, +-169, -118, -69, -25, 7, 24, 28, 25, 22, 27, +45, 76, 117, 154, 179, 188, 181, 159, 124, 79, +32, -11, -53, -92, -126, -147, -154, -145, -125, -92, +-50, -9, 19, 34, 40, 44, 51, 60, 70, 76, +71, 54, 26, -4, -28, -44, -52, -55, -60, -74, +-97, -121, -145, -172, -199, -226, -246, -261, -268, -263, +-246, -219, -186, -150, -110, -64, -20, 14, 30, 25, +0, -41, -85, -113, -116, -95, -68, -48, -44, -54, +-73, -89, -91, -72, -40, -8, 18, 43, 75, 117, +168, 217, 255, 277, 282, 273, 255, 230, 196, 155, +111, 67, 28, -3, -25, -41, -62, -93, -128, -157, +-174, -179, -174, -162, -144, -129, -121, -123, -135, -156, +-186, -223, -262, -302, -341, -379, -409, -425, -420, -395, +-357, -313, -271, -240, -224, -215, -195, -150, -82, 1, +90, 177, 257, 326, 381, 425, 456, 471, 474, 468, +461, 459, 463, 473, 482, 480, 466, 445, 424, 402, +378, 350, 319, 291, 268, 253, 247, 249, 251, 243, +224, 195, 166, 142, 129, 125, 127, 125, 111, 84, +48, 6, -37, -89, -149, -217, -292, -368, -438, -485, +-500, -480, -434, -370, -295, -216, -142, -79, -26, 13, +44, 70, 99, 133, 175, 220, 261, 290, 300, 286, +255, 216, 172, 126, 79, 36, 0, -28, -48, -56, +-47, -26, 0, 22, 33, 26, 0, -42, -91, -134, +-164, -185, -206, -234, -273, -324, -381, -435, -478, -507, +-529, -552, -575, -591, -595, -586, -565, -536, -504, -475, +-451, -428, -405, -381, -357, -332, -303, -268, -223, -167, +-104, -45, -1, 25, 40, 55, 77, 109, 152, 201, +249, 288, 317, 342, 367, 390, 407, 417, 422, 426, +429, 434, 442, 456, 466, 464, 449, 422, 385, 338, +281, 222, 167, 119, 79, 47, 26, 11, -2, -18, +-35, -48, -56, -52, -35, -6, 27, 61, 92, 119, +141, 157, 167, 172, 163, 135, 88, 29, -32, -88, +-131, -151, -147, -121, -86, -51, -23, -4, 6, 12, +19, 34, 58, 85, 111, 134, 158, 185, 210, 226, +231, 218, 190, 146, 98, 55, 21, -7, -38, -68, +-96, -116, -126, -126, -121, -121, -124, -125, -114, -89, +-51, -9, 21, 32, 15, -17, -50, -69, -73, -66, +-54, -41, -35, -37, -47, -63, -87, -119, -163, -211, +-258, -298, -328, -344, -339, -312, -265, -206, -143, -80, +-25, 13, 33, 39, 38, 36, 33, 32, 35, 43, +50, 51, 43, 22, -7, -40, -70, -92, -107, -113, +-109, -92, -61, -17, 37, 99, 157, 201, 224, 228, +221, 207, 189, 168, 146, 120, 89, 51, 10, -27, +-62, -95, -123, -145, -158, -166, -169, -165, -152, -135, +-125, -126, -138, -155, -176, -201, -225, -247, -272, -300, +-325, -339, -336, -316, -286, -256, -235, -229, -229, -224, +-205, -169, -121, -65, -4, 59, 122, 186, 249, 305, +342, 358, 359, 356, 359, 370, 389, 415, 442, 465, +479, 479, 467, 445, 411, 369, 329, 299, 278, 263, +247, 231, 213, 192, 168, 147, 131, 119, 110, 106, +112, 126, 138, 141, 129, 100, 58, 7, -46, -105, +-171, -244, -317, -377, -418, -432, -418, -381, -332, -284, +-240, -194, -143, -88, -34, 16, 65, 115, 166, 217, +266, 308, 336, 343, 329, 301, 267, 229, 188, 145, +102, 62, 27, 5, 1, 13, 31, 41, 37, 21, +-2, -28, -49, -64, -76, -91, -116, -155, -207, -264, +-318, -363, -398, -426, -456, -484, -509, -532, -555, -573, +-585, -592, -594, -595, -591, -576, -553, -522, -483, -437, +-380, -319, -257, -200, -149, -106, -73, -45, -16, 16, +56, 101, 148, 199, 248, 290, 318, 334, 341, 344, +346, 350, 357, 365, 374, 384, 398, 421, 450, 481, +499, 494, 461, 403, 336, 276, 231, 196, 168, 138, +100, 52, 0, -49, -86, -112, -129, -136, -129, -106, +-73, -37, -1, 28, 53, 71, 84, 95, 102, 97, +76, 39, -1, -38, -64, -74, -68, -50, -33, -23, +-20, -16, -5, 16, 45, 77, 109, 135, 155, 172, +189, 206, 221, 234, 242, 238, 219, 188, 154, 120, +90, 66, 48, 34, 18, -7, -42, -81, -120, -154, +-178, -186, -174, -147, -116, -90, -74, -72, -82, -99, +-113, -118, -111, -96, -75, -52, -31, -17, -12, -14, +-23, -40, -71, -118, -178, -242, -300, -337, -345, -321, +-273, -214, -155, -107, -71, -44, -16, 17, 52, 79, +97, 109, 120, 132, 144, 153, 155, 144, 114, 71, +21, -28, -75, -117, -145, -154, -139, -104, -55, -2, +45, 80, 100, 115, 129, 144, 157, 162, 157, 139, +108, 67, 24, -14, -47, -73, -96, -116, -130, -139, +-140, -135, -124, -112, -104, -104, -115, -140, -175, -212, +-240, -258, -266, -268, -268, -266, -264, -262, -260, -254, +-246, -236, -228, -218, -202, -180, -150, -113, -69, -19, +33, 88, 141, 188, 223, 241, 242, 239, 239, 251, +279, 321, 371, 416, 444, 450, 439, 418, 396, 376, +362, 351, 337, 316, 286, 251, 216, 186, 162, 142, +123, 104, 90, 87, 100, 123, 149, 171, 182, 179, +158, 120, 69, 8, -58, -126, -188, -237, -269, -287, +-297, -301, -301, -298, -287, -264, -225, -177, -125, -70, +-15, 44, 107, 168, 225, 274, 314, 338, 345, 335, +311, 276, 233, 190, 154, 130, 114, 103, 88, 68, +45, 24, 10, 4, 0, -4, -15, -29, -49, -75, +-106, -143, -184, -231, -280, -325, -356, -375, -388, -400, +-416, -436, -462, -490, -521, -553, -589, -627, -662, -681, +-679, -652, -606, -546, -480, -416, -359, -309, -263, -217, +-176, -139, -104, -66, -21, 32, 95, 162, 225, 278, +317, 339, 345, 341, 330, 315, 302, 292, 289, 300, +328, 370, 414, 452, 474, 478, 462, 432, 396, 363, +338, 314, 285, 248, 205, 154, 97, 40, -12, -55, +-88, -111, -123, -124, -117, -105, -87, -61, -31, -3, +17, 29, 32, 28, 19, 13, 9, 7, 2, -4, +-13, -20, -22, -17, -8, 0, 7, 17, 35, 66, +107, 148, 183, 209, 225, 234, 241, 250, 257, 256, +238, 206, 171, 145, 133, 134, 138, 137, 120, 84, +34, -19, -67, -108, -140, -163, -175, -177, -172, -166, +-162, -164, -175, -192, -206, -210, -202, -182, -154, -127, +-100, -77, -56, -39, -29, -32, -53, -92, -145, -205, +-262, -303, -320, -312, -289, -256, -220, -184, -150, -117, +-79, -35, 14, 63, 106, 141, 170, 194, 213, 231, +246, 252, 238, 200, 143, 78, 13, -41, -80, -100, +-104, -102, -97, -90, -78, -57, -27, 9, 45, 77, +101, 117, 121, 115, 95, 64, 27, -11, -45, -73, +-91, -100, -106, -115, -123, -127, -123, -114, -108, -115, +-139, -177, -220, -255, -273, -269, -253, -236, -224, -218, +-217, -217, -216, -207, -194, -181, -171, -162, -148, -127, +-103, -79, -53, -23, 11, 50, 86, 115, 132, 139, +139, 139, 150, 177, 219, 270, 319, 357, 377, 383, +384, 381, 379, 379, 381, 379, 368, 344, 308, 267, +225, 189, 157, 131, 108, 85, 66, 55, 62, 84, +118, 154, 184, 198, 188, 154, 107, 57, 11, -29, +-67, -98, -126, -152, -177, -202, -227, -248, -263, -269, +-262, -238, -199, -149, -91, -32, 27, 87, 150, 214, +270, 311, 330, 328, 307, 278, 252, 239, 234, 229, +213, 180, 136, 91, 52, 28, 18, 18, 16, 9, +-6, -24, -42, -62, -85, -113, -146, -184, -224, -259, +-285, -302, -311, -317, -320, -322, -331, -353, -394, -450, +-517, -583, -642, -684, -703, -699, -673, -632, -580, -523, +-467, -411, -358, -311, -268, -225, -181, -137, -92, -45, +10, 78, 156, 232, 293, 334, 348, 338, 309, 278, +256, 245, 245, 254, 270, 292, 318, 348, 381, 409, +427, 432, 425, 413, 398, 378, 349, 311, 264, 213, +158, 102, 50, 6, -32, -67, -95, -114, -123, -116, +-98, -79, -68, -69, -77, -87, -91, -85, -67, -42, +-15, 3, 12, 14, 17, 21, 25, 26, 24, 21, +20, 25, 40, 67, 102, 138, 171, 198, 219, 234, +241, 244, 241, 230, 214, 195, 180, 174, 176, 179, +178, 174, 164, 148, 125, 97, 63, 23, -18, -60, +-100, -136, -167, -192, -212, -230, -246, -256, -261, -259, +-252, -239, -216, -183, -145, -109, -82, -65, -58, -62, +-73, -89, -112, -141, -177, -211, -235, -245, -241, -232, +-222, -214, -204, -188, -161, -118, -62, -4, 48, 95, +142, 193, 245, 292, 325, 334, 315, 276, 226, 177, +137, 104, 74, 39, -1, -43, -79, -102, -110, -105, +-89, -65, -35, -4, 24, 48, 64, 71, 64, 45, +17, -13, -42, -67, -84, -91, -91, -89, -85, -83, +-81, -87, -103, -131, -170, -212, -253, -287, -304, -302, +-283, -256, -232, -213, -203, -200, -200, -196, -187, -172, +-153, -132, -112, -92, -68, -39, -6, 25, 52, 70, +78, 76, 66, 55, 49, 54, 69, 92, 122, 159, +198, 234, 262, 283, 298, 311, 322, 335, 351, 364, +366, 351, 322, 286, 248, 213, 179, 146, 111, 74, +39, 18, 18, 40, 72, 102, 122, 126, 119, 107, +93, 79, 64, 47, 30, 12, -3, -17, -32, -50, +-74, -105, -136, -161, -175, -178, -170, -149, -114, -69, +-15, 42, 101, 155, 202, 234, 252, 261, 263, 263, +264, 268, 272, 271, 258, 231, 194, 153, 115, 85, +64, 53, 43, 26, 1, -28, -58, -85, -106, -128, +-153, -182, -213, -246, -272, -286, -285, -270, -253, -241, +-245, -267, -304, -354, -414, -480, -543, -596, -633, -653, +-655, -641, -616, -584, -549, -511, -467, -417, -363, -309, +-258, -212, -167, -121, -64, 8, 91, 172, 237, 279, +300, 301, 291, 278, 269, 264, 258, 250, 238, 229, +229, 239, 258, 281, 307, 332, 358, 380, 395, 397, +385, 360, 325, 281, 234, 186, 141, 95, 51, 14, +-10, -24, -30, -32, -38, -49, -71, -102, -134, -161, +-175, -174, -156, -122, -77, -35, -4, 14, 26, 38, +51, 62, 67, 65, 57, 51, 54, 74, 112, 160, +209, 244, 261, 261, 248, 231, 215, 202, 193, 187, +181, 177, 172, 170, 170, 173, 174, 173, 168, 159, +143, 115, 79, 36, -10, -58, -107, -151, -188, -221, +-252, -280, -302, -314, -313, -299, -271, -232, -191, -160, +-143, -135, -132, -129, -126, -124, -125, -131, -140, -154, +-168, -177, -182, -186, -190, -195, -198, -193, -182, -164, +-137, -100, -51, 10, 82, 154, 220, 272, 304, 315, +308, 293, 277, 264, 251, 232, 203, 166, 120, 68, +15, -31, -67, -88, -97, -97, -89, -79, -68, -55, +-38, -19, -6, -4, -17, -42, -71, -96, -109, -106, +-88, -65, -46, -37, -40, -51, -71, -102, -143, -190, +-235, -270, -289, -293, -282, -267, -251, -237, -226, -215, +-201, -185, -169, -156, -147, -135, -115, -86, -51, -12, +24, 57, 79, 88, 85, 75, 63, 55, 50, 49, +48, 47, 49, 58, 77, 105, 137, 169, 200, 228, +253, 274, 291, 303, 310, 307, 293, 269, 241, 211, +183, 157, 133, 111, 94, 82, 76, 75, 76, 78, +76, 71, 62, 52, 46, 46, 51, 56, 61, 63, +64, 62, 57, 48, 37, 22, 0, -27, -59, -88, +-108, -113, -98, -66, -25, 14, 51, 84, 114, 140, +164, 185, 206, 227, 246, 264, 277, 284, 279, 260, +231, 197, 166, 142, 123, 106, 85, 58, 27, -5, +-35, -62, -90, -122, -161, -202, -239, -266, -278, -274, +-259, -239, -221, -210, -211, -227, -256, -294, -340, -392, +-445, -496, -541, -578, -605, -620, -621, -609, -589, -563, +-533, -498, -458, -415, -368, -315, -259, -200, -137, -68, +2, 71, 131, 178, 210, 233, 247, 257, 264, 268, +266, 256, 238, 215, 193, 179, 176, 187, 209, 236, +266, 293, 316, 331, 336, 334, 320, 293, 253, 207, +162, 125, 98, 81, 72, 70, 68, 63, 50, 28, +-4, -47, -97, -145, -182, -203, -202, -183, -148, -106, +-63, -24, 8, 37, 62, 78, 83, 79, 72, 72, +86, 116, 161, 212, 257, 288, 301, 299, 289, 276, +264, 252, 236, 217, 198, 181, 168, 159, 156, 158, +164, 173, 181, 184, 180, 166, 143, 113, 78, 36, +-12, -67, -122, -174, -221, -260, -289, -306, -310, -303, +-288, -270, -250, -232, -219, -215, -219, -223, -222, -212, +-195, -179, -167, -161, -158, -156, -152, -146, -143, -145, +-151, -162, -171, -173, -162, -136, -94, -40, 19, 79, +133, 179, 215, 239, 253, 260, 266, 271, 275, 272, +260, 237, 204, 161, 112, 66, 28, -1, -25, -49, +-71, -89, -102, -105, -100, -90, -78, -74, -80, -97, +-116, -127, -125, -110, -87, -64, -47, -38, -38, -47, +-66, -92, -124, -158, -192, -223, -247, -262, -268, -265, +-256, -247, -237, -227, -215, -201, -187, -174, -161, -142, +-113, -78, -39, 0, 39, 74, 102, 118, 121, 116, +109, 103, 95, 86, 74, 60, 42, 24, 16, 23, +47, 84, 122, 156, 182, 201, 219, 237, 251, 257, +251, 235, 212, 187, 167, 155, 151, 151, 151, 149, +145, 136, 123, 103, 78, 48, 18, -6, -19, -20, +-11, 2, 19, 39, 57, 73, 84, 94, 97, 93, +78, 53, 27, 5, -2, 1, 16, 38, 59, 75, +83, 85, 89, 98, 114, 134, 156, 178, 199, 218, +233, 245, 251, 252, 247, 237, 223, 207, 191, 175, +157, 134, 105, 72, 35, -3, -47, -94, -142, -187, +-226, -252, -263, -259, -246, -230, -216, -212, -222, -245, +-272, -298, -319, -341, -368, -401, -439, -478, -512, -537, +-547, -547, -543, -541, -543, -541, -527, -494, -444, -381, +-317, -255, -196, -141, -89, -37, 11, 60, 104, 142, +175, 205, 233, 254, 263, 258, 243, 224, 208, 196, +191, 190, 191, 195, 203, 217, 234, 250, 264, 269, +263, 242, 208, 166, 127, 106, 101, 109, 123, 135, +140, 130, 106, 73, 33, -9, -57, -107, -157, -200, +-228, -235, -221, -189, -147, -102, -60, -23, 3, 20, +31, 39, 48, 64, 91, 130, 177, 224, 264, 293, +309, 315, 315, 314, 314, 311, 298, 275, 243, 209, +179, 158, 148, 150, 160, 171, 175, 175, 174, 175, +175, 169, 152, 117, 65, 0, -70, -136, -188, -227, +-255, -271, -278, -276, -270, -261, -254, -254, -263, -278, +-291, -297, -293, -277, -255, -232, -212, -195, -178, -157, +-136, -117, -105, -103, -112, -127, -141, -145, -134, -111, +-78, -40, 2, 45, 85, 119, 150, 178, 204, 224, +239, 250, 259, 266, 269, 268, 260, 243, 216, 179, +138, 97, 60, 27, -1, -29, -58, -84, -110, -132, +-150, -165, -178, -191, -199, -198, -182, -153, -120, -92, +-72, -62, -60, -65, -77, -92, -111, -133, -157, -181, +-200, -211, -213, -211, -207, -204, -205, -211, -220, -223, +-216, -197, -170, -139, -108, -75, -41, -6, 27, 58, +84, 102, 114, 121, 124, 126, 126, 121, 108, 87, +62, 37, 18, 8, 8, 17, 32, 50, 70, 95, +123, 151, 170, 176, 169, 150, 126, 105, 91, 93, +107, 127, 147, 161, 169, 167, 156, 134, 105, 70, +33, -4, -37, -59, -66, -58, -39, -13, 14, 41, +64, 82, 95, 104, 108, 108, 103, 97, 96, 104, +120, 137, 146, 142, 130, 114, 101, 97, 101, 111, +122, 131, 137, 145, 160, 181, 204, 223, 235, 238, +232, 221, 212, 204, 197, 183, 162, 135, 103, 64, +18, -31, -79, -122, -158, -184, -199, -200, -193, -187, +-188, -199, -217, -238, -257, -273, -287, -300, -315, -333, +-355, -378, -400, -417, -433, -451, -475, -502, -526, -540, +-537, -514, -473, -422, -368, -319, -275, -234, -193, -151, +-103, -53, -2, 43, 79, 110, 138, 165, 187, 203, +211, 213, 210, 202, 190, 179, 171, 168, 168, 171, +179, 190, 200, 204, 198, 179, 151, 121, 99, 89, +94, 112, 135, 154, 162, 157, 144, 123, 98, 67, +28, -21, -79, -139, -189, -217, -221, -206, -179, -148, +-119, -92, -69, -48, -26, 0, 31, 63, 97, 132, +170, 206, 238, 266, 290, 315, 336, 354, 366, 369, +360, 337, 302, 263, 229, 204, 190, 183, 178, 173, +167, 164, 166, 174, 187, 196, 194, 171, 127, 68, +2, -59, -110, -146, -168, -183, -195, -204, -212, -218, +-226, -240, -261, -288, -315, -336, -347, -345, -329, -303, +-272, -242, -212, -184, -160, -144, -139, -140, -142, -141, +-133, -117, -94, -64, -34, -8, 10, 25, 41, 64, +93, 125, 158, 186, 207, 220, 228, 237, 249, 265, +277, 279, 269, 248, 221, 192, 165, 138, 109, 76, +35, -12, -63, -112, -156, -190, -214, -228, -233, -229, +-217, -194, -164, -134, -111, -96, -87, -83, -89, -107, +-136, -166, -191, -207, -213, -209, -199, -188, -185, -194, +-214, -238, -256, -260, -248, -222, -185, -144, -105, -73, +-49, -26, 0, 30, 64, 95, 119, 136, 146, 150, +152, 150, 142, 127, 103, 77, 51, 28, 11, 3, +5, 16, 33, 55, 78, 100, 112, 109, 91, 67, +48, 38, 38, 46, 65, 90, 116, 138, 155, 163, +164, 155, 133, 96, 48, -2, -47, -77, -90, -84, +-64, -36, -9, 11, 25, 38, 51, 67, 87, 108, +128, 149, 169, 188, 207, 221, 227, 225, 216, 204, +190, 178, 168, 160, 152, 143, 132, 125, 129, 144, +163, 182, 196, 207, 217, 226, 232, 233, 229, 215, +191, 157, 115, 68, 24, -17, -55, -89, -116, -138, +-153, -164, -172, -178, -183, -193, -211, -236, -264, -288, +-307, -317, -318, -315, -312, -313, -321, -334, -353, -379, +-411, -448, -482, -503, -506, -489, -455, -411, -368, -332, +-304, -278, -249, -216, -179, -138, -94, -49, -7, 31, +66, 97, 123, 144, 161, 173, 180, 183, 182, 176, +167, 159, 152, 146, 139, 133, 127, 122, 117, 108, +94, 78, 67, 65, 73, 89, 109, 130, 147, 158, +161, 159, 149, 130, 98, 53, 0, -54, -101, -136, +-155, -161, -161, -160, -158, -152, -140, -120, -91, -51, +-4, 45, 93, 135, 171, 199, 222, 243, 264, 288, +314, 340, 363, 377, 379, 369, 348, 317, 281, 246, +216, 195, 182, 172, 165, 163, 164, 170, 179, 187, +187, 173, 142, 96, 43, -7, -50, -82, -103, -115, +-123, -132, -141, -152, -166, -187, -220, -262, -308, -349, +-380, -395, -394, -376, -345, -306, -266, -232, -207, -188, +-175, -164, -151, -134, -113, -87, -58, -29, -5, 14, +29, 41, 53, 66, 83, 103, 123, 142, 157, 167, +174, 182, 198, 220, 243, 261, 270, 271, 270, 268, +262, 250, 229, 195, 146, 83, 13, -55, -114, -161, +-196, -221, -236, -241, -238, -225, -207, -184, -159, -134, +-116, -110, -117, -134, -155, -174, -186, -191, -188, -180, +-169, -162, -162, -172, -192, -216, -234, -239, -229, -204, +-170, -133, -100, -75, -56, -39, -17, 12, 45, 76, +102, 121, 134, 143, 151, 159, 164, 162, 148, 122, +91, 63, 42, 32, 30, 35, 44, 52, 54, 50, +37, 19, 1, -13, -22, -23, -18, -7, 11, 34, +59, 85, 110, 129, 142, 144, 133, 107, 68, 23, +-20, -56, -77, -83, -76, -62, -48, -38, -31, -25, +-11, 11, 41, 77, 114, 151, 183, 212, 236, 259, +279, 291, 294, 288, 276, 261, 245, 226, 206, 185, +163, 141, 124, 113, 112, 119, 136, 158, 185, 213, +236, 251, 253, 242, 218, 181, 137, 90, 46, 12, +-13, -32, -50, -71, -93, -113, -126, -136, -144, -158, +-181, -216, -256, -295, -326, -343, -344, -329, -307, -289, +-282, -286, -299, -319, -347, -379, -409, -431, -438, -429, +-409, -382, -351, -322, -297, -276, -258, -239, -214, -183, +-150, -118, -87, -56, -25, 5, 34, 58, 76, 88, +100, 113, 129, 147, 165, 175, 176, 165, 144, 116, +87, 62, 43, 29, 19, 13, 14, 19, 29, 44, +63, 84, 102, 116, 123, 126, 126, 123, 111, 90, +61, 29, -2, -31, -56, -79, -101, -124, -145, -161, +-168, -161, -137, -97, -49, 1, 52, 98, 138, 172, +201, 227, 251, 272, 292, 309, 326, 343, 359, 372, +378, 370, 345, 308, 267, 231, 205, 189, 180, 178, +179, 179, 176, 169, 158, 142, 119, 90, 58, 28, +2, -17, -33, -48, -62, -74, -85, -94, -104, -122, +-151, -194, -245, -297, -341, -369, -378, -369, -348, -324, +-303, -289, -278, -268, -253, -232, -207, -180, -151, -119, +-86, -53, -22, 5, 30, 48, 62, 73, 83, 92, +104, 115, 126, 136, 141, 144, 147, 153, 163, 177, +193, 210, 231, 254, 274, 286, 282, 258, 211, 147, +75, 6, -50, -95, -129, -158, -184, -206, -222, -230, +-227, -214, -196, -179, -168, -168, -178, -193, -205, -212, +-209, -201, -189, -179, -172, -171, -174, -180, -190, -201, +-211, -215, -209, -192, -166, -136, -108, -85, -68, -52, +-33, -7, 20, 45, 63, 77, 90, 108, 131, 155, +173, 180, 171, 151, 125, 101, 85, 80, 81, 82, +79, 66, 45, 20, -5, -27, -43, -53, -59, -61, +-61, -58, -50, -35, -14, 11, 40, 67, 86, 97, +98, 90, 73, 49, 23, 0, -18, -30, -36, -40, +-46, -54, -65, -70, -63, -41, -6, 35, 77, 116, +154, 191, 229, 266, 301, 328, 346, 351, 349, 342, +333, 324, 311, 292, 263, 223, 181, 143, 117, 107, +110, 125, 148, 175, 200, 218, 224, 216, 196, 165, +126, 84, 45, 16, 0, -8, -15, -23, -32, -41, +-49, -59, -73, -94, -125, -170, -222, -272, -311, -330, +-333, -325, -314, -304, -298, -293, -290, -289, -292, -303, +-319, -337, -350, -356, -353, -341, -320, -292, -265, -244, +-231, -222, -214, -201, -182, -158, -134, -108, -85, -65, +-49, -34, -17, 2, 25, 47, 73, 102, 132, 156, +165, 159, 138, 105, 67, 30, 0, -19, -29, -35, +-38, -35, -24, -6, 14, 33, 44, 47, 45, 43, +44, 51, 61, 68, 71, 68, 57, 42, 21, -4, +-32, -62, -93, -121, -142, -151, -145, -124, -92, -55, +-15, 27, 70, 113, 151, 185, 215, 240, 259, 277, +296, 321, 347, 370, 384, 385, 373, 351, 324, 298, +280, 267, 256, 243, 223, 200, 175, 151, 129, 108, +88, 66, 44, 23, 4, -8, -14, -17, -18, -21, +-27, -37, -51, -72, -101, -137, -177, -220, -260, -292, +-317, -332, -340, -343, -342, -340, -335, -325, -306, -278, +-244, -211, -181, -151, -119, -82, -42, -2, 34, 65, +86, 98, 106, 117, 132, 147, 157, 157, 147, 133, +119, 108, 102, 103, 115, 140, 175, 217, 258, 289, +304, 298, 269, 220, 161, 100, 47, 5, -27, -56, +-86, -114, -140, -160, -174, -182, -189, -196, -205, -217, +-231, -241, -244, -237, -225, -215, -207, -201, -196, -192, +-189, -186, -182, -176, -172, -170, -168, -160, -146, -127, +-106, -86, -67, -48, -28, -7, 11, 27, 39, 49, +62, 78, 98, 119, 136, 145, 145, 139, 130, 124, +124, 128, 133, 132, 119, 93, 58, 21, -12, -41, +-63, -78, -92, -103, -111, -110, -97, -75, -50, -30, +-17, -9, -6, -5, -3, 1, 9, 16, 20, 18, +10, 0, -12, -28, -48, -68, -86, -95, -92, -76, +-50, -19, 12, 47, 86, 129, 177, 224, 266, 298, +324, 343, 360, 375, 389, 399, 401, 390, 363, 321, +270, 219, 175, 145, 132, 134, 147, 165, 185, 202, +212, 211, 197, 170, 135, 96, 59, 30, 10, 0, +-1, 1, 6, 8, 7, -1, -18, -47, -86, -134, +-184, -232, -273, -302, -319, -326, -327, -326, -324, -318, +-307, -292, -278, -270, -271, -281, -296, -307, -308, -296, +-275, -251, -230, -215, -206, -199, -192, -182, -167, -150, +-135, -124, -116, -111, -106, -98, -86, -69, -46, -18, +14, 51, 89, 121, 139, 141, 126, 99, 64, 28, +-4, -31, -48, -56, -54, -44, -26, -5, 13, 22, +20, 7, -10, -22, -24, -14, 3, 26, 47, 64, +73, 74, 68, 56, 38, 14, -15, -48, -77, -101, +-113, -111, -97, -73, -42, -6, 33, 75, 115, 152, +182, 208, 230, 248, 267, 287, 309, 328, 342, 346, +342, 334, 325, 323, 324, 324, 318, 302, 276, 242, +206, 169, 134, 102, 71, 42, 17, -1, -10, -12, +-5, 4, 11, 11, 3, -11, -31, -56, -83, -110, +-136, -161, -188, -216, -242, -266, -287, -307, -328, -343, +-347, -342, -326, -306, -282, -256, -229, -200, -169, -135, +-98, -57, -15, 22, 52, 73, 90, 109, 132, 155, +170, 173, 163, 144, 121, 99, 83, 77, 83, 101, +130, 165, 202, 237, 264, 274, 266, 239, 200, 154, +107, 63, 22, -9, -35, -55, -74, -94, -115, -138, +-163, -188, -214, -238, -255, -263, -261, -252, -241, -233, +-230, -231, -233, -234, -229, -219, -206, -196, -191, -190, +-189, -183, -168, -148, -123, -97, -71, -48, -25, -2, +17, 35, 50, 61, 69, 78, 88, 100, 110, 117, +118, 119, 122, 130, 140, 151, 159, 159, 149, 127, +97, 62, 25, -11, -48, -83, -111, -131, -138, -132, +-116, -93, -71, -55, -49, -52, -60, -68, -68, -59, +-44, -27, -13, -4, 0, -4, -13, -25, -38, -49, +-59, -70, -76, -77, -71, -57, -37, -11, 20, 59, +104, 153, 201, 247, 289, 329, 364, 395, 419, 437, +447, 444, 424, 389, 344, 297, 254, 220, 196, 181, +175, 173, 174, 176, 177, 176, 172, 160, 139, 106, +67, 31, 8, 0, 2, 10, 15, 15, 10, -1, +-17, -37, -63, -92, -125, -157, -188, -216, -244, -271, +-296, -315, -324, -321, -308, -289, -270, -255, -246, -245, +-249, -254, -256, -250, -237, -221, -206, -193, -181, -167, +-151, -133, -114, -100, -95, -100, -115, -133, -147, -152, +-143, -123, -98, -70, -45, -19, 8, 35, 58, 71, +72, 57, 27, -10, -48, -77, -94, -97, -87, -68, +-44, -24, -10, -8, -19, -40, -63, -80, -86, -80, +-63, -38, -10, 13, 31, 42, 49, 53, 54, 50, +38, 20, -2, -25, -44, -55, -56, -48, -33, -11, +16, 48, 85, 125, 165, 204, 237, 261, 276, 284, +289, 291, 293, 294, 295, 298, 301, 309, 318, 326, +329, 325, 312, 288, 256, 219, 178, 137, 97, 59, +29, 9, 2, 7, 20, 35, 47, 49, 39, 20, +-2, -25, -45, -61, -74, -86, -103, -126, -151, -177, +-202, -229, -255, -279, -299, -310, -313, -305, -288, -265, +-240, -214, -189, -161, -130, -95, -57, -20, 14, 45, +73, 101, 125, 144, 156, 161, 157, 143, 123, 101, +83, 72, 70, 76, 88, 105, 127, 153, 179, 201, +208, 200, 176, 145, 113, 84, 63, 49, 41, 34, +22, 3, -23, -57, -96, -138, -179, -214, -239, -256, +-262, -260, -253, -245, -239, -237, -239, -241, -240, -235, +-225, -214, -205, -197, -188, -178, -166, -149, -128, -103, +-76, -49, -22, 4, 29, 52, 70, 83, 89, 87, +77, 67, 62, 65, 75, 90, 106, 122, 136, 145, +153, 155, 150, 136, 114, 84, 48, 7, -33, -69, +-96, -114, -122, -123, -115, -102, -88, -80, -82, -95, +-114, -129, -132, -124, -107, -86, -67, -52, -43, -39, +-40, -40, -40, -43, -50, -59, -66, -69, -65, -55, +-41, -21, 2, 27, 55, 87, 127, 174, 226, 279, +328, 368, 400, 425, 443, 451, 446, 430, 406, 381, +356, 331, 304, 280, 256, 234, 213, 196, 181, 169, +160, 147, 128, 101, 71, 47, 32, 27, 28, 32, +33, 29, 15, -4, -26, -45, -58, -69, -82, -97, +-118, -145, -177, -213, -247, -276, -298, -311, -315, -311, +-300, -284, -266, -248, -234, -223, -216, -209, -201, -193, +-185, -174, -159, -138, -113, -87, -63, -49, -48, -64, +-92, -124, -149, -162, -159, -146, -129, -112, -96, -78, +-56, -32, -7, 11, 19, 8, -18, -55, -91, -118, +-130, -129, -115, -94, -72, -55, -48, -50, -60, -78, +-98, -118, -134, -142, -139, -127, -106, -81, -54, -30, +-7, 13, 30, 42, 46, 44, 36, 25, 15, 7, +4, 3, 4, 4, 5, 16, 40, 82, 134, 188, +234, 265, 278, 279, 271, 264, 263, 268, 278, 288, +298, 309, 323, 336, 345, 349, 344, 328, 301, 262, +218, 172, 126, 82, 44, 16, 2, 2, 12, 26, +35, 34, 24, 6, -13, -32, -48, -58, -66, -74, +-83, -96, -109, -123, -137, -154, -176, -203, -235, -265, +-285, -291, -283, -265, -243, -219, -198, -179, -159, -132, +-97, -57, -15, 24, 63, 96, 122, 139, 147, 150, +151, 151, 147, 140, 128, 116, 103, 93, 88, 89, +96, 108, 120, 128, 130, 123, 110, 93, 76, 64, +58, 58, 61, 61, 54, 37, 12, -15, -44, -72, +-104, -140, -178, -213, -241, -256, -261, -259, -254, -251, +-253, -259, -261, -254, -236, -213, -193, -180, -173, -170, +-167, -161, -149, -133, -111, -84, -50, -12, 28, 67, +96, 111, 109, 93, 68, 45, 30, 27, 34, 48, +65, 83, 101, 120, 136, 146, 148, 138, 119, 90, +54, 17, -14, -41, -63, -83, -96, -101, -100, -93, +-88, -87, -94, -106, -120, -133, -139, -138, -132, -125, +-115, -106, -94, -81, -68, -57, -49, -46, -49, -53, +-54, -50, -41, -28, -15, -3, 5, 12, 21, 37, +65, 105, 157, 214, 269, 315, 350, 374, 389, 399, +406, 410, 411, 406, 399, 390, 382, 372, 356, 330, +297, 260, 223, 191, 163, 139, 115, 91, 70, 54, +49, 52, 59, 65, 63, 53, 34, 12, -9, -25, +-34, -41, -49, -60, -77, -97, -121, -145, -171, -199, +-228, -257, -279, -293, -294, -283, -263, -238, -214, -195, +-183, -176, -172, -169, -162, -149, -129, -103, -72, -41, +-16, -2, -4, -20, -46, -75, -102, -122, -132, -135, +-132, -128, -121, -109, -90, -67, -46, -31, -29, -40, +-62, -90, -117, -137, -146, -145, -135, -122, -110, -100, +-91, -83, -80, -83, -97, -118, -143, -166, -181, -186, +-178, -161, -138, -113, -85, -59, -34, -9, 12, 29, +41, 47, 50, 54, 57, 57, 51, 44, 39, 43, +60, 91, 134, 180, 220, 247, 260, 263, 261, 257, +255, 255, 256, 260, 269, 282, 302, 326, 348, 363, +367, 355, 325, 284, 236, 189, 147, 113, 86, 64, +47, 34, 26, 21, 16, 11, 3, -7, -19, -32, +-44, -55, -64, -72, -81, -88, -92, -94, -98, -109, +-125, -148, -174, -200, -222, -235, -237, -232, -224, -217, +-212, -203, -188, -164, -129, -86, -41, 0, 35, 62, +83, 99, 113, 126, 136, 139, 137, 132, 128, 128, +130, 131, 129, 122, 110, 96, 81, 66, 52, 40, +34, 32, 34, 42, 54, 70, 81, 84, 74, 57, +39, 21, 6, -10, -32, -63, -101, -141, -177, -203, +-220, -231, -239, -250, -262, -271, -273, -265, -247, -224, +-201, -182, -168, -160, -156, -154, -151, -143, -128, -102, +-67, -24, 21, 63, 96, 117, 123, 115, 98, 76, +54, 36, 26, 27, 40, 63, 89, 115, 136, 149, +149, 135, 109, 76, 40, 7, -18, -35, -45, -53, +-62, -73, -84, -92, -98, -102, -107, -115, -126, -139, +-152, -164, -171, -172, -169, -161, -153, -143, -132, -119, +-105, -90, -78, -69, -60, -52, -42, -30, -20, -14, +-13, -13, -8, 4, 29, 65, 108, 153, 195, 232, +263, 293, 320, 344, 364, 378, 389, 399, 407, 416, +425, 432, 432, 418, 390, 348, 298, 248, 200, 158, +122, 94, 76, 68, 70, 76, 83, 87, 83, 71, +51, 28, 7, -8, -17, -24, -29, -37, -49, -62, +-78, -95, -116, -141, -168, -197, -226, -251, -270, -277, +-271, -255, -235, -216, -200, -188, -176, -166, -153, -136, +-115, -92, -68, -45, -25, -10, -3, -5, -17, -36, +-57, -76, -89, -98, -103, -105, -103, -98, -89, -79, +-72, -70, -74, -85, -99, -114, -126, -134, -137, -139, +-141, -143, -142, -138, -129, -117, -107, -101, -103, -111, +-127, -147, -170, -189, -202, -208, -207, -197, -178, -153, +-123, -90, -57, -26, 0, 23, 40, 51, 57, 57, +55, 53, 54, 62, 77, 101, 130, 162, 192, 218, +238, 250, 253, 252, 248, 246, 245, 247, 255, 267, +287, 310, 334, 351, 358, 348, 323, 287, 248, 210, +176, 151, 133, 119, 102, 84, 63, 44, 28, 14, +4, -5, -15, -28, -40, -51, -60, -69, -79, -89, +-97, -103, -107, -111, -116, -125, -137, -150, -162, -171, +-177, -185, -193, -203, -209, -209, -198, -173, -135, -90, +-46, -9, 19, 38, 54, 67, 80, 93, 103, 108, +111, 113, 118, 127, 139, 151, 159, 159, 148, 127, +96, 59, 23, -4, -22, -27, -20, -5, 14, 33, +48, 57, 59, 57, 51, 43, 32, 19, 1, -21, +-50, -79, -106, -132, -158, -183, -208, -231, -251, -265, +-270, -265, -250, -228, -203, -181, -167, -160, -159, -157, +-151, -138, -118, -94, -65, -35, -1, 34, 71, 105, +129, 139, 131, 110, 84, 60, 45, 42, 50, 66, +86, 106, 122, 133, 135, 125, 104, 72, 37, 7, +-11, -19, -21, -24, -31, -42, -54, -66, -75, -84, +-94, -107, -123, -142, -158, -171, -180, -185, -190, -196, +-201, -202, -196, -184, -167, -146, -125, -101, -78, -60, +-48, -43, -41, -38, -30, -17, 0, 24, 50, 79, +106, 130, 152, 174, 199, 225, 250, 272, 290, 306, +320, 337, 356, 381, 408, 434, 451, 453, 437, 404, +359, 309, 258, 209, 167, 134, 110, 94, 86, 84, +89, 98, 103, 98, 82, 59, 35, 12, -6, -22, +-35, -45, -54, -61, -69, -80, -93, -110, -129, -148, +-167, -185, -201, -214, -222, -224, -222, -215, -207, -196, +-183, -169, -151, -128, -103, -80, -62, -48, -37, -27, +-16, -7, -1, -2, -10, -23, -37, -47, -49, -47, +-47, -53, -69, -90, -113, -133, -146, -154, -159, -163, +-167, -173, -179, -180, -181, -181, -182, -192, -209, -218, +-206, -177, -147, -123, -107, -98, -100, -117, -152, -198, +-240, -263, -262, -240, -193, -135, -86, -62, -68, -83, +-77, -41, 12, 67, 116, 148, 159, 166, 168, 158, +138, 112, 94, 97, 117, 144, 187, 252, 312, 334, +320, 296, 277, 253, 210, 162, 136, 139, 173, 233, +310, 381, 426, 442, 425, 375, 296, 195, 77, -36, +-124, -163, -129, -34, 70, 149, 205, 240, 249, 215, +120, -23, -174, -296, -367, -366, -300, -198, -99, -27, +28, 81, 120, 106, 14, -134, -294, -419, -470, -433, +-323, -184, -56, 48, 133, 195, 214, 166, 62, -63, +-173, -223, -182, -64, 79, 193, 268, 324, 375, 397, +356, 254, 114, -33, -143, -172, -110, 5, 111, 172, +193, 188, 156, 85, -17, -126, -218, -277, -281, -213, +-86, 47, 141, 180, 182, 160, 108, 19, -108, -261, +-406, -496, -497, -405, -257, -114, -13, 45, 62, 32, +-40, -145, -267, -382, -453, -447, -357, -211, -55, 79, +188, 261, 287, 262, 189, 75, -67, -208, -296, -289, +-187, -34, 120, 251, 345, 394, 390, 334, 231, 78, +-106, -276, -375, -368, -263, -105, 54, 186, 270, 293, +250, 148, -5, -187, -359, -474, -489, -402, -256, -98, +39, 137, 181, 168, 102, -13, -164, -327, -462, -522, +-482, -365, -210, -55, 72, 150, 179, 171, 135, 69, +-29, -144, -227, -229, -142, -1, 156, 297, 402, 467, +492, 480, 427, 326, 191, 70, 13, 47, 154, 300, +453, 582, 663, 686, 656, 576, 442, 255, 48, -120, +-201, -181, -87, 43, 179, 290, 358, 377, 346, 263, +130, -30, -175, -264, -278, -224, -127, -11, 88, 147, +163, 148, 102, 11, -133, -303, -434, -486, -454, -361, +-237, -107, 4, 82, 119, 115, 67, -31, -160, -279, +-346, -345, -281, -169, -32, 100, 203, 263, 280, 249, +156, 10, -149, -274, -331, -322, -258, -163, -67, 8, +54, 77, 75, 28, -77, -221, -354, -440, -462, -424, +-342, -235, -130, -47, 12, 53, 59, 3, -112, -254, +-377, -444, -442, -384, -292, -194, -112, -54, -11, 10, +-6, -74, -178, -282, -348, -351, -286, -167, -27, 102, +204, 284, 339, 348, 297, 197, 77, -18, -63, -47, +28, 144, 265, 361, 426, 469, 483, 451, 368, 253, +140, 58, 22, 38, 100, 183, 256, 311, 354, 380, +369, 301, 182, 41, -77, -145, -148, -86, 14, 115, +191, 244, 274, 272, 217, 108, -34, -180, -297, -362, +-353, -272, -150, -22, 89, 175, 219, 202, 116, -16, +-161, -280, -352, -360, -304, -203, -86, 29, 136, 221, +262, 239, 160, 50, -58, -139, -172, -147, -75, 17, +114, 213, 310, 382, 397, 341, 228, 87, -48, -148, +-186, -161, -100, -33, 30, 97, 158, 191, 172, 104, +6, -102, -198, -254, -250, -191, -99, 4, 108, 201, +256, 244, 158, 19, -143, -295, -401, -437, -405, -328, +-233, -134, -37, 35, 59, 21, -64, -174, -281, -356, +-375, -335, -253, -151, -40, 76, 188, 266, 285, 238, +143, 22, -89, -156, -161, -111, -32, 53, 141, 228, +297, 322, 292, 211, 89, -49, -172, -248, -263, -228, +-163, -76, 25, 119, 172, 164, 96, -16, -149, -270, +-346, -364, -335, -278, -208, -125, -40, 16, 22, -24, +-115, -230, -340, -414, -431, -395, -330, -256, -172, -75, +18, 83, 104, 79, 15, -68, -140, -173, -154, -94, +-14, 78, 181, 281, 354, 386, 371, 313, 227, 136, +70, 52, 84, 149, 239, 352, 475, 578, 633, 623, +549, 419, 257, 104, -8, -66, -76, -46, 24, 129, +243, 336, 380, 362, 284, 163, 30, -76, -137, -157, +-152, -121, -57, 30, 121, 191, 219, 191, 106, -19, +-147, -240, -288, -302, -284, -233, -153, -57, 32, 97, +124, 102, 34, -52, -126, -168, -182, -173, -134, -61, +35, 133, 212, 251, 239, 174, 72, -31, -111, -164, +-194, -195, -162, -96, -17, 51, 88, 80, 18, -84, +-194, -277, -325, -346, -343, -311, -246, -163, -79, -16, +10, -13, -90, -193, -287, -353, -394, -413, -402, -357, +-281, -189, -103, -40, -18, -50, -124, -209, -277, -316, +-324, -293, -215, -91, 59, 206, 325, 393, 396, 335, +239, 143, 63, 3, -26, -13, 51, 161, 290, 411, +494, 515, 464, 363, 251, 154, 81, 33, 18, 43, +108, 196, 288, 366, 402, 376, 291, 179, 72, -13, +-74, -109, -111, -76, -11, 66, 144, 201, 209, 157, +59, -56, -167, -260, -327, -353, -327, -253, -147, -28, +79, 141, 137, 74, -22, -124, -214, -285, -323, -312, +-249, -146, -16, 113, 210, 245, 214, 137, 46, -37, +-107, -155, -165, -129, -48, 65, 197, 312, 376, 369, +302, 204, 102, 8, -73, -135, -164, -158, -117, -47, +36, 105, 134, 114, 57, -14, -88, -157, -211, -232, +-211, -149, -51, 60, 153, 195, 175, 105, 13, -83, +-176, -258, -317, -342, -328, -275, -188, -91, -16, 11, +-8, -55, -108, -158, -202, -232, -237, -213, -154, -61, +52, 155, 214, 219, 181, 128, 73, 27, -8, -25, +-24, 0, 52, 129, 212, 272, 284, 249, 182, 97, +5, -81, -151, -196, -210, -186, -120, -26, 61, 109, +107, 67, 6, -64, -138, -203, -253, -281, -281, -245, +-177, -100, -45, -32, -55, -102, -162, -224, -278, -317, +-339, -337, -300, -221, -113, -9, 60, 89, 87, 66, +36, 8, -10, -20, -18, 2, 50, 124, 207, 273, +310, 321, 311, 283, 244, 203, 166, 140, 137, 174, +252, 356, 449, 502, 508, 474, 408, 324, 235, 149, +73, 17, -2, 23, 93, 177, 244, 281, 284, 254, +199, 126, 43, -41, -119, -172, -179, -129, -42, 45, +108, 134, 119, 71, 2, -73, -147, -212, -262, -278, +-246, -175, -88, -8, 51, 89, 103, 96, 67, 20, +-40, -108, -160, -166, -118, -31, 64, 143, 191, 204, +185, 143, 83, 10, -70, -147, -191, -189, -147, -89, +-38, -13, -19, -50, -99, -152, -205, -263, -324, -366, +-366, -320, -243, -164, -105, -78, -86, -126, -182, -242, +-300, -357, -401, -414, -386, -322, -244, -173, -126, -107, +-116, -146, -182, -221, -265, -301, -307, -263, -168, -43, +84, 191, 263, 293, 284, 248, 195, 129, 56, 0, +-10, 34, 126, 238, 336, 403, 425, 406, 363, 309, +248, 176, 104, 55, 48, 86, 149, 217, 269, 291, +277, 236, 183, 127, 63, -3, -56, -76, -53, 1, +68, 122, 150, 143, 105, 52, -6, -74, -153, -229, +-277, -275, -226, -143, -51, 27, 72, 78, 54, 16, +-32, -92, -154, -196, -196, -143, -52, 54, 149, 211, +228, 208, 170, 125, 71, 8, -46, -73, -55, 3, +89, 182, 257, 296, 293, 260, 210, 146, 66, -20, +-96, -138, -139, -106, -52, 3, 42, 57, 54, 38, +11, -35, -99, -163, -202, -201, -163, -98, -25, 33, +62, 65, 51, 27, -15, -83, -168, -247, -293, -295, +-256, -188, -116, -63, -36, -26, -24, -28, -45, -75, +-105, -117, -102, -60, 2, 71, 123, 149, 151, 144, +131, 107, 68, 22, -11, -18, 6, 58, 124, 180, +210, 210, 190, 155, 102, 27, -59, -141, -196, -213, +-189, -133, -66, -10, 20, 32, 31, 14, -26, -95, +-177, -250, -294, -296, -257, -193, -128, -84, -63, -59, +-70, -101, -157, -229, -296, -341, -348, -310, -236, -147, +-69, -13, 27, 59, 78, 77, 56, 24, -4, -15, +-1, 40, 98, 157, 206, 245, 278, 300, 295, 257, +197, 132, 85, 75, 111, 183, 264, 332, 375, 399, +406, 389, 340, 263, 171, 81, 17, -5, 17, 73, +138, 191, 229, 251, 246, 208, 136, 43, -54, -133, +-177, -173, -129, -67, -8, 35, 66, 78, 63, 19, +-46, -123, -192, -239, -250, -222, -169, -104, -36, 35, +102, 150, 161, 129, 64, -19, -96, -143, -145, -107, +-49, 14, 80, 144, 194, 216, 200, 145, 62, -30, +-112, -161, -171, -156, -132, -104, -77, -55, -52, -74, +-125, -196, -274, -340, -373, -365, -325, -276, -228, -188, +-156, -141, -148, -179, -229, -291, -351, -390, -392, -361, +-314, -264, -217, -172, -136, -117, -122, -152, -202, -259, +-300, -300, -250, -162, -58, 46, 140, 217, 267, 287, +274, 232, 166, 95, 46, 39, 75, 139, 217, 293, +358, 403, 420, 406, 364, 296, 211, 131, 80, 67, +86, 126, 176, 225, 261, 275, 264, 229, 176, 109, +45, 2, -11, 0, 23, 51, 81, 111, 133, 137, +119, 74, 0, -88, -169, -218, -226, -199, -152, -92, +-30, 24, 65, 87, 86, 56, 2, -55, -95, -100, +-72, -22, 39, 104, 160, 200, 218, 215, 185, 130, +60, 0, -29, -24, 8, 60, 120, 179, 225, 252, +256, 232, 177, 97, 10, -60, -100, -114, -108, -88, +-58, -24, 6, 32, 44, 30, -15, -82, -150, -198, +-217, -209, -180, -135, -83, -32, 13, 47, 54, 21, +-47, -133, -208, -255, -270, -254, -216, -168, -122, -82, +-47, -19, -11, -28, -60, -93, -112, -111, -90, -52, +-4, 44, 87, 121, 145, 148, 127, 85, 42, 14, +8, 21, 48, 83, 115, 140, 156, 164, 154, 115, +46, -40, -122, -185, -218, -219, -193, -149, -98, -47, +0, 31, 30, -12, -91, -181, -260, -313, -331, -311, +-264, -207, -153, -106, -71, -61, -85, -140, -211, -278, +-324, -342, -329, -287, -226, -153, -72, 9, 78, 117, +117, 85, 40, 0, -22, -22, 2, 45, 100, 161, +227, 288, 324, 321, 279, 215, 151, 104, 84, 94, +124, 165, 213, 268, 327, 374, 386, 351, 280, 192, +108, 48, 27, 44, 87, 139, 192, 243, 278, 281, +242, 167, 74, -14, -80, -113, -111, -83, -43, 2, +54, 104, 136, 133, 90, 18, -62, -132, -177, -186, +-163, -119, -63, 4, 80, 149, 190, 191, 151, 82, +6, -55, -87, -90, -72, -41, 3, 63, 133, 192, +220, 206, 153, 72, -16, -91, -137, -155, -152, -137, +-111, -78, -51, -43, -64, -110, -170, -229, -275, -298, +-297, -285, -268, -246, -215, -183, -166, -172, -202, -246, +-295, -334, -354, -351, -332, -307, -275, -234, -188, -150, +-133, -144, -180, -226, -263, -275, -256, -212, -154, -89, +-17, 63, 144, 207, 240, 238, 207, 158, 113, 90, +95, 122, 163, 215, 275, 336, 382, 399, 381, 330, +257, 179, 116, 79, 67, 72, 91, 123, 164, 203, +225, 225, 203, 163, 114, 68, 35, 13, -1, -9, +-3, 23, 65, 105, 125, 113, 70, 5, -65, -122, +-160, -180, -190, -186, -164, -120, -61, -4, 38, 54, +40, 6, -28, -49, -56, -49, -31, 1, 48, 103, +153, 187, 196, 177, 135, 84, 42, 18, 10, 15, +33, 68, 112, 153, 179, 183, 162, 116, 59, 4, +-40, -75, -106, -125, -123, -96, -53, -5, 28, 38, +18, -28, -85, -136, -174, -203, -221, -222, -197, -148, +-84, -21, 23, 36, 15, -29, -81, -128, -168, -201, +-218, -212, -182, -132, -73, -16, 24, 36, 22, -1, +-24, -39, -49, -49, -33, 0, 44, 90, 129, 148, +143, 120, 93, 74, 65, 58, 49, 44, 47, 63, +88, 116, 132, 124, 85, 25, -37, -87, -124, -152, +-169, -169, -150, -112, -63, -17, 6, -5, -50, -112, +-170, -215, -244, -258, -255, -237, -205, -163, -118, -82, +-71, -92, -136, -186, -230, -261, -276, -271, -243, -195, +-132, -60, 7, 56, 75, 69, 52, 34, 22, 14, +14, 28, 59, 107, 167, 229, 279, 300, 287, 252, +210, 171, 137, 109, 92, 93, 116, 159, 216, 273, +307, 306, 272, 222, 170, 126, 94, 77, 77, 94, +124, 164, 204, 229, 224, 188, 134, 78, 27, -13, +-42, -56, -52, -30, 6, 53, 92, 106, 88, 45, +-1, -42, -71, -88, -94, -87, -67, -31, 22, 84, +136, 162, 161, 141, 114, 88, 61, 36, 15, 1, +4, 29, 75, 128, 165, 172, 151, 111, 64, 16, +-28, -69, -104, -134, -150, -149, -135, -120, -116, -125, +-144, -167, -192, -217, -239, -258, -272, -276, -266, -244, +-222, -214, -224, -247, -272, -292, -304, -308, -306, -300, +-291, -275, -247, -217, -197, -194, -205, -219, -228, -227, +-217, -199, -178, -152, -115, -58, 13, 85, 139, 167, +169, 155, 134, 115, 105, 106, 116, 137, 174, 225, +278, 317, 332, 320, 288, 242, 192, 144, 103, 70, +47, 43, 63, 101, 144, 178, 194, 190, 169, 134, +93, 52, 12, -20, -37, -30, 0, 42, 77, 94, +92, 73, 43, 5, -34, -79, -129, -173, -196, -185, +-144, -85, -26, 19, 45, 51, 42, 26, 8, -9, +-22, -21, 0, 43, 95, 143, 176, 192, 189, 171, +146, 118, 90, 64, 44, 42, 61, 95, 130, 156, +165, 152, 121, 77, 27, -21, -70, -110, -132, -127, +-96, -53, -13, 13, 19, 5, -23, -61, -105, -153, +-202, -239, -249, -223, -169, -102, -40, 3, 21, 14, +-11, -50, -97, -148, -194, -221, -217, -182, -125, -59, +1, 44, 64, 64, 49, 25, 0, -26, -38, -30, +0, 44, 92, 132, 158, 166, 158, 144, 124, 99, +68, 38, 20, 22, 45, 77, 107, 123, 118, 91, +51, 7, -35, -80, -121, -148, -152, -130, -91, -48, +-14, -2, -15, -48, -92, -140, -187, -231, -263, -271, +-253, -213, -162, -114, -83, -76, -94, -127, -165, -201, +-233, -254, -255, -231, -181, -115, -42, 20, 63, 81, +79, 69, 57, 40, 23, 13, 18, 45, 92, 152, +213, 259, 279, 273, 249, 217, 176, 127, 78, 41, +24, 35, 70, 121, 171, 207, 222, 217, 201, 177, +146, 112, 82, 64, 63, 78, 107, 141, 168, 179, +170, 147, 114, 74, 28, -12, -40, -51, -40, -13, +20, 50, 63, 59, 45, 28, 10, -7, -26, -41, +-48, -42, -18, 20, 64, 105, 133, 149, 154, 149, +129, 99, 65, 35, 18, 20, 40, 72, 103, 124, +133, 132, 120, 96, 56, 4, -52, -105, -145, -167, +-171, -163, -153, -144, -137, -133, -137, -153, -183, -221, +-258, -285, -295, -286, -267, -249, -244, -246, -251, -254, +-256, -262, -274, -291, -307, -314, -308, -288, -261, -237, +-217, -198, -179, -161, -149, -147, -151, -156, -152, -130, +-88, -32, 24, 73, 113, 143, 162, 170, 166, 154, +138, 127, 127, 145, 175, 210, 240, 264, 280, 285, +274, 245, 200, 143, 85, 42, 29, 47, 85, 127, +160, 180, 189, 186, 169, 139, 97, 46, -2, -36, +-46, -32, -7, 22, 51, 76, 92, 94, 77, 39, +-18, -87, -148, -183, -185, -157, -112, -60, -9, 34, +67, 86, 89, 77, 54, 28, 11, 10, 24, 51, +86, 126, 164, 194, 210, 207, 184, 144, 97, 59, +42, 47, 66, 88, 105, 114, 116, 109, 92, 66, +27, -18, -63, -93, -104, -98, -84, -64, -43, -24, +-11, -8, -20, -51, -101, -159, -207, -230, -226, -201, +-161, -113, -67, -27, -1, 5, -8, -44, -91, -136, +-164, -169, -152, -121, -80, -34, 10, 50, 78, 91, +82, 54, 17, -10, -20, -8, 18, 50, 84, 114, +139, 158, 168, 163, 140, 102, 61, 29, 12, 8, +13, 22, 31, 38, 44, 47, 41, 22, -13, -56, +-96, -124, -137, -136, -127, -114, -102, -96, -96, -106, +-127, -158, -192, -220, -236, -239, -231, -217, -198, -175, +-154, -135, -124, -126, -144, -174, -202, -215, -206, -179, +-138, -90, -42, 1, 39, 69, 87, 88, 74, 52, +35, 34, 49, 77, 111, 146, 178, 207, 231, 248, +248, 226, 184, 129, 78, 38, 14, 10, 24, 52, +88, 129, 167, 193, 199, 183, 153, 120, 93, 75, +68, 68, 75, 87, 104, 125, 145, 152, 138, 106, +63, 23, -7, -27, -35, -34, -27, -11, 11, 41, +69, 83, 79, 59, 32, 9, -3, -2, 9, 29, +55, 85, 118, 152, 175, 181, 169, 144, 114, 85, +63, 51, 50, 58, 76, 102, 128, 145, 139, 108, +56, -7, -70, -125, -163, -182, -184, -170, -143, -109, +-81, -71, -86, -120, -164, -210, -248, -273, -287, -292, +-290, -279, -258, -231, -208, -202, -215, -243, -279, -313, +-337, -345, -338, -319, -289, -249, -201, -153, -116, -98, +-96, -108, -124, -137, -138, -124, -96, -57, -10, 43, +95, 137, 162, 171, 168, 156, 142, 131, 127, 131, +144, 168, 202, 237, 259, 256, 227, 178, 121, 73, +44, 36, 45, 64, 87, 115, 146, 172, 185, 178, +149, 104, 52, 5, -27, -41, -40, -28, -4, 30, +68, 98, 106, 90, 51, -2, -58, -103, -131, -141, +-135, -112, -74, -23, 30, 76, 106, 116, 107, 84, +55, 32, 20, 21, 38, 72, 121, 175, 219, 242, +239, 213, 173, 132, 99, 75, 58, 45, 36, 37, +48, 65, 79, 81, 68, 42, 5, -30, -59, -81, +-97, -103, -99, -84, -64, -46, -38, -43, -64, -98, +-134, -166, -191, -208, -213, -202, -176, -139, -101, -70, +-50, -44, -51, -67, -86, -103, -119, -128, -125, -103, +-63, -13, 35, 70, 84, 77, 58, 40, 30, 29, +32, 37, 49, 70, 102, 136, 166, 180, 176, 155, +125, 93, 62, 32, 3, -19, -30, -26, -9, 14, +34, 43, 36, 16, -10, -39, -70, -100, -125, -142, +-149, -145, -134, -125, -118, -121, -131, -146, -166, -189, +-213, -235, -248, -246, -228, -197, -163, -136, -124, -129, +-141, -154, -160, -159, -154, -141, -117, -81, -38, 8, +51, 81, 97, 98, 92, 84, 75, 68, 66, 74, +95, 127, 168, 211, 242, 252, 239, 202, 149, 86, +25, -24, -52, -51, -25, 18, 72, 123, 163, 184, +187, 173, 145, 108, 67, 32, 11, 11, 32, 70, +115, 153, 172, 170, 147, 110, 64, 14, -29, -61, +-72, -59, -26, 19, 66, 105, 127, 133, 127, 112, +91, 66, 41, 24, 21, 35, 69, 114, 159, 193, +210, 209, 192, 163, 124, 87, 57, 43, 44, 61, +89, 115, 130, 128, 107, 70, 20, -34, -91, -141, +-176, -189, -179, -151, -118, -93, -86, -99, -125, -161, +-202, -243, -280, -307, -322, -319, -299, -268, -236, -213, +-208, -217, -238, -264, -290, -311, -327, -332, -322, -294, +-249, -197, -147, -108, -86, -80, -88, -103, -119, -128, +-127, -113, -86, -45, 5, 57, 103, 136, 156, 161, +154, 138, 118, 101, 92, 97, 116, 145, 173, 192, +195, 183, 159, 126, 90, 58, 34, 21, 22, 39, +68, 104, 134, 150, 148, 128, 97, 60, 25, -4, +-26, -37, -33, -14, 16, 50, 76, 88, 86, 66, +34, -2, -40, -72, -96, -104, -93, -61, -16, 32, +75, 104, 117, 115, 103, 84, 64, 48, 43, 53, +80, 119, 161, 197, 220, 226, 220, 204, 180, 151, +115, 76, 41, 18, 13, 23, 41, 58, 65, 60, +45, 24, 0, -25, -50, -73, -90, -96, -93, -83, +-71, -63, -63, -72, -88, -109, -132, -155, -179, -197, +-204, -197, -177, -150, -118, -89, -67, -54, -51, -58, +-70, -82, -88, -82, -65, -38, -6, 25, 53, 72, +84, 89, 89, 85, 76, 67, 62, 69, 86, 111, +138, 161, 174, 176, 166, 146, 116, 80, 39, 3, +-24, -39, -42, -33, -17, 0, 13, 21, 20, 13, +-2, -30, -64, -101, -132, -152, -159, -154, -139, -122, +-110, -106, -114, -134, -167, -203, -235, -254, -255, -240, +-215, -187, -160, -141, -129, -121, -116, -115, -118, -121, +-121, -113, -93, -61, -23, 16, 51, 75, 87, 90, +84, 73, 64, 61, 69, 90, 121, 159, 193, 215, +218, 200, 166, 121, 70, 21, -19, -46, -57, -49, +-22, 19, 67, 109, 138, 151, 146, 123, 88, 47, +12, -6, -2, 22, 62, 108, 146, 169, 173, 157, +125, 80, 33, -8, -37, -47, -37, -8, 34, 80, +122, 152, 168, 170, 156, 131, 100, 71, 50, 43, +55, 82, 121, 164, 202, 228, 235, 225, 204, 175, +145, 118, 96, 82, 77, 80, 87, 91, 88, 76, +53, 17, -28, -76, -119, -151, -166, -163, -148, -128, +-111, -103, -108, -128, -158, -194, -231, -261, -280, -286, +-281, -266, -248, -232, -222, -220, -226, -239, -259, -284, +-307, -321, -323, -308, -277, -236, -190, -148, -115, -96, +-88, -90, -99, -108, -115, -116, -107, -84, -49, -8, +33, 70, 99, 120, 133, 135, 128, 113, 97, 83, +80, 90, 110, 134, 151, 156, 147, 128, 104, 80, +58, 41, 31, 32, 46, 69, 95, 115, 124, 121, +106, 84, 57, 32, 12, -2, -10, -11, -1, 17, +40, 59, 69, 69, 59, 40, 16, -9, -35, -52, +-56, -44, -18, 14, 48, 78, 100, 112, 113, 105, +90, 73, 57, 48, 52, 72, 106, 147, 187, 220, +240, 244, 229, 198, 154, 104, 57, 21, 2, 0, +6, 19, 35, 47, 53, 50, 40, 22, -2, -32, +-64, -91, -108, -113, -109, -99, -85, -73, -67, -68, +-79, -101, -134, -169, -198, -214, -214, -201, -180, -153, +-126, -101, -81, -66, -58, -58, -64, -73, -76, -68, +-47, -18, 14, 46, 72, 90, 98, 97, 89, 75, +63, 59, 66, 85, 110, 139, 164, 178, 177, 159, +129, 92, 54, 17, -12, -33, -45, -48, -43, -30, +-14, 1, 14, 18, 11, -8, -40, -77, -110, -135, +-149, -150, -141, -128, -117, -113, -117, -131, -154, -184, +-214, -237, -247, -245, -232, -213, -188, -162, -138, -118, +-106, -101, -105, -115, -122, -120, -108, -84, -52, -12, +25, 57, 78, 87, 86, 78, 66, 59, 64, 80, +104, 131, 155, 174, 183, 182, 168, 142, 105, 59, +12, -26, -49, -53, -42, -17, 13, 45, 70, 87, +93, 85, 62, 30, -2, -24, -28, -15, 11, 45, +80, 109, 129, 134, 124, 99, 63, 25, -6, -25, +-29, -16, 11, 47, 84, 117, 146, 166, 173, 166, +150, 131, 115, 105, 104, 110, 124, 143, 164, 187, +210, 228, 235, 230, 214, 193, 169, 146, 127, 111, +97, 84, 72, 63, 55, 42, 20, -11, -45, -75, +-96, -107, -112, -113, -115, -122, -133, -147, -166, -187, +-209, -230, -247, -259, -264, -261, -252, -239, -229, -223, +-226, -236, -254, -275, -293, -303, -302, -289, -267, -239, +-210, -183, -160, -139, -122, -109, -102, -98, -97, -93, +-88, -80, -68, -52, -32, -7, 23, 58, 90, 111, +118, 112, 98, 82, 69, 63, 63, 67, 73, 80, +87, 93, 94, 89, 77, 63, 49, 38, 33, 34, +41, 50, 60, 67, 72, 72, 67, 57, 45, 34, +25, 18, 15, 17, 21, 26, 33, 42, 50, 55, +51, 43, 32, 24, 19, 18, 20, 24, 30, 41, +59, 81, 103, 121, 129, 127, 117, 105, 97, 98, +109, 129, 154, 182, 208, 224, 226, 214, 190, 158, +120, 82, 48, 22, 5, -2, -1, 7, 19, 29, +32, 29, 18, 0, -26, -53, -77, -97, -112, -119, +-116, -103, -88, -79, -79, -87, -101, -121, -142, -162, +-182, -197, -205, -204, -188, -162, -128, -96, -69, -53, +-48, -51, -55, -56, -52, -41, -24, 0, 27, 51, +69, 82, 87, 86, 82, 79, 81, 89, 101, 115, +130, 142, 145, 140, 126, 109, 86, 60, 32, 7, +-16, -36, -49, -50, -40, -23, -8, 0, 0, -8, +-25, -47, -68, -85, -99, -110, -118, -120, -120, -120, +-122, -127, -137, -152, -171, -192, -212, -227, -235, -234, +-221, -198, -170, -144, -122, -107, -101, -101, -106, -108, +-105, -93, -70, -41, -7, 22, 44, 59, 68, 73, +78, 84, 90, 98, 107, 114, 123, 135, 147, 151, +144, 128, 104, 75, 44, 17, -4, -19, -27, -28, +-23, -13, -2, 9, 18, 25, 27, 24, 17, 8, +0, -3, -2, 8, 28, 54, 78, 94, 103, 104, +96, 81, 61, 40, 23, 14, 18, 34, 59, 87, +114, 138, 159, 175, 187, 196, 198, 193, 179, 162, +149, 146, 152, 166, 187, 210, 231, 247, 254, 253, +243, 223, 195, 162, 128, 97, 72, 53, 42, 35, +30, 24, 16, 5, -12, -35, -60, -86, -109, -130, +-146, -155, -159, -160, -164, -173, -187, -206, -226, -240, +-246, -244, -240, -239, -244, -253, -263, -271, -272, -267, +-260, -251, -245, -237, -229, -218, -206, -189, -168, -144, +-120, -98, -81, -72, -70, -73, -76, -76, -69, -55, +-35, -10, 16, 41, 61, 75, 79, 72, 54, 32, +13, 0, -5, -3, 7, 23, 43, 63, 79, 85, +79, 60, 35, 13, 1, 0, 6, 19, 33, 47, +57, 64, 70, 73, 68, 56, 39, 24, 13, 6, +5, 11, 21, 35, 48, 61, 72, 78, 76, 67, +53, 38, 27, 24, 32, 51, 76, 103, 127, 143, +147, 139, 124, 110, 101, 102, 112, 131, 155, 179, +200, 212, 215, 202, 172, 129, 81, 35, 0, -22, +-30, -24, -9, 11, 33, 51, 62, 57, 37, 5, +-30, -64, -92, -110, -118, -115, -105, -93, -78, -66, +-58, -63, -80, -108, -144, -178, -206, -221, -220, -204, +-174, -136, -94, -58, -33, -23, -25, -34, -42, -47, +-43, -30, -10, 13, 40, 67, 90, 106, 110, 107, +101, 95, 92, 93, 99, 105, 111, 114, 114, 111, +103, 90, 70, 45, 17, -10, -31, -41, -41, -34, +-22, -10, 0, 4, 1, -9, -26, -47, -71, -94, +-113, -125, -130, -127, -120, -111, -102, -99, -109, -130, +-159, -192, -221, -239, -242, -229, -203, -169, -131, -96, +-71, -59, -59, -66, -76, -84, -85, -79, -64, -42, +-16, 13, 46, 77, 103, 121, 128, 126, 116, 105, +96, 92, 93, 95, 97, 98, 96, 92, 84, 72, +58, 39, 18, -5, -27, -46, -57, -58, -46, -26, +-2, 17, 27, 27, 15, -2, -21, -33, -34, -25, +-7, 18, 47, 76, 96, 104, 99, 85, 65, 44, +27, 16, 13, 20, 38, 67, 107, 152, 194, 227, +243, 241, 224, 198, 171, 149, 136, 134, 145, 170, +203, 239, 270, 288, 291, 275, 242, 198, 148, 98, +53, 19, 1, 2, 18, 42, 63, 72, 63, 34, +-7, -57, -104, -143, -166, -174, -168, -155, -142, -133, +-134, -145, -164, -188, -212, -233, -252, -269, -280, -283, +-277, -262, -241, -219, -202, -195, -197, -207, -221, -232, +-237, -229, -208, -175, -136, -99, -67, -45, -34, -34, +-44, -57, -69, -77, -78, -68, -46, -13, 25, 61, +87, 95, 83, 54, 15, -25, -62, -84, -88, -70, +-35, 7, 48, 78, 91, 86, 66, 37, 6, -20, +-40, -51, -48, -30, 0, 36, 71, 97, 108, 104, +86, 61, 31, 1, -20, -31, -27, -8, 21, 56, +89, 113, 124, 122, 108, 89, 68, 49, 37, 36, +49, 75, 109, 144, 173, 186, 185, 172, 152, 130, +112, 103, 107, 125, 153, 185, 210, 221, 213, 185, +141, 89, 37, -7, -41, -60, -61, -46, -19, 12, +39, 57, 60, 49, 26, -6, -43, -80, -110, -128, +-132, -122, -101, -74, -50, -35, -36, -52, -78, -111, +-148, -181, -206, -219, -213, -190, -152, -106, -63, -30, +-9, -1, -2, -11, -22, -33, -36, -30, -13, 13, +45, 77, 102, 119, 128, 132, 133, 128, 119, 107, +94, 85, 79, 78, 79, 78, 73, 66, 54, 40, +23, 6, -11, -27, -40, -47, -47, -39, -30, -25, +-24, -30, -39, -52, -69, -89, -109, -125, -133, -132, +-122, -110, -101, -102, -112, -130, -152, -177, -199, -214, +-219, -212, -192, -159, -121, -85, -59, -45, -43, -49, +-62, -77, -89, -94, -88, -70, -40, -1, 39, 77, +106, 126, 136, 136, 126, 111, 89, 65, 43, 29, +25, 34, 51, 68, 82, 86, 77, 54, 21, -16, +-54, -82, -96, -93, -75, -50, -22, 0, 14, 17, +10, -4, -21, -38, -52, -55, -45, -21, 11, 45, +76, 97, 105, 100, 82, 57, 32, 11, 3, 12, +40, 82, 133, 181, 219, 245, 256, 253, 239, 217, +192, 169, 155, 156, 173, 203, 240, 275, 300, 310, +303, 276, 232, 176, 114, 58, 19, 3, 9, 30, +56, 77, 84, 75, 50, 13, -30, -76, -120, -155, +-176, -181, -175, -162, -148, -139, -137, -144, -159, -182, +-210, -243, -273, -295, -302, -294, -274, -247, -220, -199, +-187, -182, -184, -188, -193, -196, -194, -186, -171, -148, +-120, -91, -64, -43, -29, -23, -25, -34, -46, -55, +-55, -43, -20, 6, 32, 48, 50, 36, 11, -20, +-51, -76, -93, -96, -85, -61, -31, 0, 28, 46, +50, 41, 22, -4, -33, -62, -81, -85, -72, -45, +-10, 25, 55, 74, 81, 75, 60, 40, 18, -1, +-13, -14, -4, 15, 43, 72, 99, 119, 132, 138, +133, 119, 98, 78, 66, 65, 77, 100, 127, 153, +171, 181, 183, 179, 170, 158, 147, 139, 138, 142, +150, 159, 164, 160, 145, 123, 96, 67, 36, 6, +-17, -33, -37, -32, -18, -2, 13, 24, 24, 16, +0, -21, -44, -66, -82, -90, -92, -87, -77, -67, +-59, -54, -53, -59, -74, -99, -129, -158, -179, -188, +-180, -157, -123, -86, -52, -24, -6, 2, 2, -4, +-13, -18, -18, -10, 5, 27, 52, 78, 104, 129, +147, 155, 150, 133, 108, 80, 51, 30, 19, 17, +23, 33, 44, 53, 56, 50, 35, 14, -7, -27, +-45, -57, -64, -67, -63, -53, -40, -28, -24, -29, +-45, -66, -89, -110, -123, -128, -127, -124, -119, -117, +-118, -125, -142, -162, -182, -194, -196, -186, -165, -137, +-109, -84, -65, -53, -47, -48, -53, -60, -64, -63, +-55, -39, -16, 12, 43, 73, 102, 122, 130, 124, +104, 77, 47, 23, 10, 8, 14, 26, 42, 57, +69, 72, 63, 43, 15, -16, -48, -73, -86, -88, +-80, -67, -49, -30, -14, -5, -7, -19, -39, -59, +-71, -70, -53, -25, 7, 40, 67, 84, 89, 83, +70, 55, 40, 30, 29, 43, 69, 105, 144, 184, +219, 242, 254, 254, 245, 230, 215, 205, 203, 212, +228, 250, 275, 295, 305, 298, 275, 237, 187, 133, +86, 51, 33, 31, 39, 54, 69, 79, 80, 69, +46, 12, -29, -74, -115, -146, -163, -167, -161, -149, +-134, -125, -124, -135, -156, -185, -218, -248, -270, -283, +-285, -278, -263, -243, -221, -200, -181, -166, -158, -158, +-161, -165, -167, -164, -157, -141, -118, -90, -61, -35, +-16, -5, -3, -7, -10, -9, -3, 2, 5, 5, +0, -7, -17, -27, -38, -52, -69, -84, -92, -90, +-78, -58, -34, -13, 2, 8, 6, -3, -19, -38, +-56, -69, -74, -70, -60, -44, -24, -4, 15, 31, +42, 46, 41, 30, 17, 6, 0, 2, 11, 29, +55, 85, 116, 143, 162, 169, 160, 143, 125, 111, +104, 104, 112, 126, 146, 169, 192, 212, 224, 224, +211, 192, 171, 153, 139, 129, 125, 122, 121, 120, +118, 110, 94, 68, 37, 5, -22, -41, -52, -53, +-48, -40, -28, -16, -7, -6, -15, -30, -50, -70, +-88, -102, -111, -111, -104, -88, -68, -48, -37, -42, +-63, -95, -127, -152, -164, -162, -147, -123, -94, -63, +-30, 0, 19, 26, 22, 10, -3, -16, -21, -16, +0, 27, 62, 103, 141, 169, 178, 166, 136, 95, +51, 13, -14, -28, -30, -19, 0, 23, 44, 55, +55, 43, 23, -4, -34, -64, -89, -105, -109, -99, +-76, -48, -26, -14, -17, -31, -52, -75, -95, -109, +-117, -120, -118, -110, -99, -91, -91, -100, -115, -131, +-144, -151, -149, -138, -121, -101, -80, -58, -41, -32, +-30, -34, -42, -50, -56, -55, -47, -29, -3, 28, +62, 92, 109, 109, 95, 71, 43, 17, -3, -17, +-23, -20, -7, 13, 39, 60, 69, 63, 43, 13, +-21, -55, -83, -101, -109, -106, -88, -61, -32, -11 + +}; + +const unsigned int test_wav_long_len = 160000; diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Src/main.c b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Src/main.c similarity index 82% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Src/main.c rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Src/main.c index 23396224..f2b9042a 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Src/main.c +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Src/main.c @@ -30,16 +30,15 @@ // needed for running the model and/or initializing inference setup #include "sww_model.h" #include "sww_model_data.h" -#include "model_test_inputs.h" +#include "fixed_data.h" -#include "sww_util.h" +#include "sww_ref_util.h" /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN PTD */ - /* USER CODE END PTD */ /* Private define ------------------------------------------------------------*/ @@ -59,6 +58,8 @@ UART_HandleTypeDef huart3; SAI_HandleTypeDef hsai_BlockA1; DMA_HandleTypeDef hdma_sai1_a; +TIM_HandleTypeDef htim16; + PCD_HandleTypeDef hpcd_USB_OTG_FS; /* USER CODE BEGIN PV */ @@ -73,12 +74,14 @@ static void MX_LPUART1_UART_Init(void); static void MX_USART3_UART_Init(void); static void MX_USB_OTG_FS_PCD_Init(void); static void MX_SAI1_Init(void); +static void MX_TIM16_Init(void); /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ + // These defines and this function are to get printf() working #ifdef __GNUC__ #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) @@ -93,7 +96,6 @@ PUTCHAR_PROTOTYPE return ch; } - /* USER CODE END 0 */ /** @@ -108,6 +110,7 @@ int main(void) uint32_t uart_timeout_ms = 200; uint32_t uart_status; + /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ @@ -133,9 +136,11 @@ int main(void) MX_USART3_UART_Init(); MX_USB_OTG_FS_PCD_Init(); MX_SAI1_Init(); - + MX_TIM16_Init(); /* USER CODE BEGIN 2 */ setup_i2s_buffers(); // allocate memory for I2S reception + HAL_TIM_Base_Start(&htim16); // start timer + th_timestamp(); // Toggle D7 pin on startup /* USER CODE END 2 */ /* Infinite loop */ @@ -143,6 +148,7 @@ int main(void) aiInit(); char ch_from_uart= (char) 0; + while (1) { uart_status = HAL_UART_Receive(&hlpuart1, (uint8_t *)&ch_from_uart, 1, uart_timeout_ms); @@ -224,7 +230,7 @@ static void MX_LPUART1_UART_Init(void) hlpuart1.Instance = LPUART1; hlpuart1.Init.BaudRate = 115200; hlpuart1.Init.WordLength = UART_WORDLENGTH_8B; - hlpuart1.Init.StopBits = UART_STOPBITS_2; + hlpuart1.Init.StopBits = UART_STOPBITS_1; hlpuart1.Init.Parity = UART_PARITY_NONE; hlpuart1.Init.Mode = UART_MODE_TX_RX; hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; @@ -336,6 +342,38 @@ static void MX_SAI1_Init(void) } +/** + * @brief TIM16 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM16_Init(void) +{ + + /* USER CODE BEGIN TIM16_Init 0 */ + + /* USER CODE END TIM16_Init 0 */ + + /* USER CODE BEGIN TIM16_Init 1 */ + + /* USER CODE END TIM16_Init 1 */ + htim16.Instance = TIM16; + htim16.Init.Prescaler = 120-1; + htim16.Init.CounterMode = TIM_COUNTERMODE_UP; + htim16.Init.Period = 65535; + htim16.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim16.Init.RepetitionCounter = 0; + htim16.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim16) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM16_Init 2 */ + HAL_TIM_Base_MspInit(&htim16); + /* USER CODE END TIM16_Init 2 */ + +} + /** * @brief USB_OTG_FS Initialization Function * @param None @@ -403,6 +441,7 @@ static void MX_GPIO_Init(void) __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); @@ -410,19 +449,42 @@ static void MX_GPIO_Init(void) __HAL_RCC_GPIOA_CLK_ENABLE(); /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOB, LD3_Pin|LD2_Pin|PIN_WW_DETECTED_Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(timestamp_GPIO_Port, timestamp_Pin, GPIO_PIN_SET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(Processing_GPIO_Port, Processing_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, LD3_Pin|LD2_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(USB_PowerSwitchOn_GPIO_Port, USB_PowerSwitchOn_Pin, GPIO_PIN_RESET); + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(WW_DETECTED_GPIO_Port, WW_DETECTED_Pin, GPIO_PIN_SET); + /*Configure GPIO pin : B1_Pin */ GPIO_InitStruct.Pin = B1_Pin; GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); - /*Configure GPIO pins : LD3_Pin LD2_Pin PIN_WW_DETECTED_Pin */ - GPIO_InitStruct.Pin = LD3_Pin|LD2_Pin|PIN_WW_DETECTED_Pin; + /*Configure GPIO pin : timestamp_Pin */ + GPIO_InitStruct.Pin = timestamp_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; + HAL_GPIO_Init(timestamp_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : Processing_Pin */ + GPIO_InitStruct.Pin = Processing_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; + HAL_GPIO_Init(Processing_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : LD3_Pin LD2_Pin WW_DETECTED_Pin */ + GPIO_InitStruct.Pin = LD3_Pin|LD2_Pin|WW_DETECTED_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Src/stm32l4xx_hal_msp.c b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Src/stm32l4xx_hal_msp.c similarity index 88% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Src/stm32l4xx_hal_msp.c rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Src/stm32l4xx_hal_msp.c index f14eb313..b32348be 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Src/stm32l4xx_hal_msp.c +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Src/stm32l4xx_hal_msp.c @@ -207,6 +207,51 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) } +/** +* @brief TIM_Base MSP Initialization +* This function configures the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM16) + { + /* USER CODE BEGIN TIM16_MspInit 0 */ + + /* USER CODE END TIM16_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM16_CLK_ENABLE(); + /* USER CODE BEGIN TIM16_MspInit 1 */ + + /* USER CODE END TIM16_MspInit 1 */ + + } + +} + +/** +* @brief TIM_Base MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM16) + { + /* USER CODE BEGIN TIM16_MspDeInit 0 */ + + /* USER CODE END TIM16_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM16_CLK_DISABLE(); + /* USER CODE BEGIN TIM16_MspDeInit 1 */ + + /* USER CODE END TIM16_MspDeInit 1 */ + } + +} + /** * @brief PCD MSP Initialization * This function configures the hardware resources used in this example diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Src/stm32l4xx_it.c b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Src/stm32l4xx_it.c similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Src/stm32l4xx_it.c rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Src/stm32l4xx_it.c diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Src/sww_ref_util.c b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Src/sww_ref_util.c new file mode 100644 index 00000000..ea9fdcff --- /dev/null +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Src/sww_ref_util.c @@ -0,0 +1,1080 @@ +/* + * sww_util.c + * + * Created on: Jan 16, 2025 + * Author: jeremy + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "stm32l4xx_hal.h" +#include "arm_math.h" + + +#include "sww_ref_util.h" +#include "feature_extraction.h" +#include "main.h" + +// needed for running the model and/or initializing inference setup +#include "sww_model.h" +#include "sww_model_data.h" +#include "fixed_data.h" + +// I don't want to move the main declaration out of main.c because it is auto-generated by CubeMX +extern SAI_HandleTypeDef hsai_BlockA1; +extern TIM_HandleTypeDef htim16; + +#define MAX_CMD_TOKENS 8 // maximum number of tokens in a command, including the command and arguments +// Command buffer (incoming commands from host) +char g_cmd_buf[EE_CMD_SIZE + 1]; +size_t g_cmd_pos = 0u; + +// variables for I2S receive +uint32_t g_int16s_read = 0; +// chunk should be a 'window-stride' long = 32ms stride * 16kS/s * 2B/sample = 1024 +// then double because we receive stereo (2 samples per time point) +uint32_t g_i2s_chunk_size_bytes = 2048; +uint32_t g_i2s_status = HAL_OK; +// two ping-pong byte buffers for DMA transfers from I2S port. +int16_t *g_i2s_buffer0 = NULL; +int16_t *g_i2s_buffer1 = NULL; +int16_t *g_i2s_current_buff = NULL; // will be either g_i2s_buffer0 or g_i2s_buffer1 +int g_i2s_buff_sel = 0; // 0 for buffer0, 1 for buffer1 +uint8_t *g_gp_buffer = NULL; // general-purpose buffer; for capturing a waveform or activations. +uint32_t g_gp_buff_bytes = 64000; +int16_t *g_wav_record = NULL; // buffer to store complete waveform +int8_t *g_act_buff = NULL; // jhdbg +int8_t *g_model_input; + +int g_buffer_alloc_success=0; + +// length in (16b) samples, but I2S receives stereo, so actual length in time will be 1/2 this +uint32_t g_i2s_wav_len = 0; +uint32_t g_first_frame = 1; + + +int16_t *g_wav_block_buff = NULL; // hold most recent SWW_WINLEN_SAMPLES for feature extraction +LogBuffer g_log = { .buffer = {0}, .current_pos = 0 }; +i2s_state_t g_i2s_state = Idle; + + +uint32_t g_act_idx = 0; +#define ACT_BUFF_LEN 40000 + +void setup_i2s_buffers() { + // set up variables for I2S receiving + g_i2s_buffer0 = (int16_t *)malloc(g_i2s_chunk_size_bytes); + g_i2s_buffer1 = (int16_t *)malloc(g_i2s_chunk_size_bytes); + g_i2s_current_buff = g_i2s_buffer0; + + g_wav_block_buff =(int16_t *)malloc(SWW_WINLEN_SAMPLES * sizeof(int16_t)); + g_model_input = (int8_t *)malloc(SWW_MODEL_INPUT_SIZE * sizeof(int8_t)); + + g_gp_buffer = malloc(g_gp_buff_bytes); + + if (!g_i2s_buffer0 || !g_i2s_buffer1 || !g_wav_block_buff || !g_model_input){ + g_buffer_alloc_success = 0; + printf("ERROR: Buffer allocation failed. Many operationw will fail.\r\n"); + } + else { + g_buffer_alloc_success = 1; + } + if( !g_gp_buff_bytes) { + printf("WARNING: general-purpose buffer allocation failed. Wav and activation capture will fail.\r\n"); + } +} + +void delay_us(int delay_len_us) { + // there may be a better way to implement this + // this will not give an accurate 1us delay, but + // for longer delays it should be accurate to within 1us. + int delay_start = __HAL_TIM_GET_COUNTER(&htim16); + while(__HAL_TIM_GET_COUNTER(&htim16) < delay_start + 1 ){ + ; + } +} + +void print_vals_int16(const int16_t *buffer, uint32_t num_vals) +{ + const int vals_per_line = 16; + char end_char; + + printf("["); + for(uint32_t i=0;i= num_vals) + { + break; + } + printf("%d%c ", buffer[i+j], end_char); + } + printf("\r\n"); + } +} + + +void print_vals_int8(const int8_t *buffer, uint32_t num_vals) +{ + const int vals_per_line = 16; + char end_char; + + printf("["); + for(uint32_t i=0;i= num_vals) + { + break; + } + printf("%d%c ", buffer[i+j], end_char); + } + printf("\r\n"); + } + printf("]\r\n"); + // printf("]\r\n==== Done ====\r\n"); +} + +void print_bytes(const uint8_t *buffer, uint32_t num_bytes) +{ + const int vals_per_line = 16; + printf("["); + for(uint32_t i=0;i= num_bytes) + { + break; + } + printf("0x%X, ", buffer[i+j]); + } + printf("\r\n"); + } + printf("]\r\n==== Done ====\r\n"); +} + + +void print_vals_float(const float *buffer, uint32_t num_vals) +{ + const int vals_per_line = 8; + char end_char; // don't add a ',' after the last value, because it breaks JSON + printf("["); + for(uint32_t i=0;i= num_vals) + { + break; + } + printf("%3.5e%c ", buffer[i+j], end_char); + } + printf("\r\n"); + } + // printf("]\r\n==== Done ====\r\n"); + printf("]\r\n\r\n"); +} +void log_printf(LogBuffer *log, const char *format, ...) { + va_list args; + char temp_buffer[LOG_BUFFER_SIZE]; + int written; + + // Initialize the variable argument list + va_start(args, format); + + // Write formatted output to a temporary buffer + written = vsnprintf(temp_buffer, sizeof(temp_buffer), format, args); + + // End the variable argument list + va_end(args); + + // Check if the formatted string fits in the remaining buffer + if (log->current_pos + written >= LOG_BUFFER_SIZE) { + // Buffer overflow: Zero out and reset to the beginning + memset(log->buffer, 0, LOG_BUFFER_SIZE); + log->current_pos = 0; + } + + // Copy the formatted string to the log buffer + if (written > 0) { + size_t bytes_to_copy = (written < LOG_BUFFER_SIZE) ? written : LOG_BUFFER_SIZE - 1; + strncpy(&log->buffer[log->current_pos], temp_buffer, bytes_to_copy); + log->current_pos += bytes_to_copy; + } +} + + +/** + * This function assembles a command string from the UART. It should be called + * from the UART ISR for each new character received. When the parser sees the + * termination character, the user-defined th_command_ready() command is called. + * It is up to the application to then dispatch this command outside the ISR + * as soon as possible by calling ee_serial_command_parser_callback(), below. + */ +void ee_serial_callback(char c) { + if (c == EE_CMD_TERMINATOR) { + g_cmd_buf[g_cmd_pos] = (char)0; + process_command(g_cmd_buf); + g_cmd_pos = 0; + } else { + g_cmd_buf[g_cmd_pos] = c; + g_cmd_pos = g_cmd_pos >= EE_CMD_SIZE ? EE_CMD_SIZE : g_cmd_pos + 1; + } +} + + + + +/* Global handle to reference the instantiated C-model */ +static ai_handle sww_model = AI_HANDLE_NULL; + +/* Global c-array to handle the activations buffer */ +AI_ALIGNED(32) +static ai_i8 activations[AI_SWW_MODEL_DATA_ACTIVATIONS_SIZE]; + +/* Array to store the data of the input tensor */ +AI_ALIGNED(32) +static ai_i8 in_data[AI_SWW_MODEL_IN_1_SIZE]; +/* or static ai_i8 in_data[AI_SWW_MODEL_DATA_IN_1_SIZE_BYTES]; */ + +/* c-array to store the data of the output tensor */ +AI_ALIGNED(32) +static ai_i8 out_data[AI_SWW_MODEL_OUT_1_SIZE]; +/* static ai_i8 out_data[AI_SWW_MODEL_DATA_OUT_1_SIZE_BYTES]; */ + +/* Array of pointer to manage the model's input/output tensors */ +static ai_buffer *ai_input; +static ai_buffer *ai_output; + + +/* + * Bootstrap inference framework + */ +ai_error aiInit(void) { + ai_error err; + + /* Create and initialize the c-model */ + const ai_handle acts[] = { activations }; + err = ai_sww_model_create_and_init(&sww_model, acts, NULL); + + if (err.type != AI_ERROR_NONE) { + ; + }; + + /* Reteive pointers to the model's input/output tensors */ + ai_input = ai_sww_model_inputs_get(sww_model, NULL); + ai_output = ai_sww_model_outputs_get(sww_model, NULL); + + return err; +} + + + +/* + * Run inference + */ +ai_error aiRun(const void *in_data, void *out_data) { + ai_i32 n_batch; + ai_error err; + + /* 1 - Update IO handlers with the data payload */ + ai_input[0].data = AI_HANDLE_PTR(in_data); + ai_output[0].data = AI_HANDLE_PTR(out_data); + + /* 2 - Perform the inference */ + n_batch = ai_sww_model_run(sww_model, &ai_input[0], &ai_output[0]); + if (n_batch != 1) { + err = ai_sww_model_get_error(sww_model); + + }; + + return err; +} + +void run_model_on_test_data(char *cmd_args[]) { +// acquire_and_process_data(in_data); + const int8_t *input_source=NULL; + uint16_t timer_start, timer_stop, timer_diff; + + printf("In run_model. about to run model\r\n"); + if (strcmp(cmd_args[1], "class0") == 0) { + input_source = test_input_class0; + } + else if (strcmp(cmd_args[1], "class1") == 0) { + input_source = test_input_class1; + } + else if (strcmp(cmd_args[1], "class2") == 0) { + input_source = test_input_class2; + } + else { + printf("Unknown input tensor name, defaulting to test_input_class0\r\n"); + input_source = test_input_class0; + } + for(int i=0;i'; 'db print [Nbytes]', 'db '\r\n"); + } + else if (strcmp(cmd_args[1], "load") == 0) { + transfer_size = atoi(cmd_args[2]); + if (transfer_size == 0) { + printf("Error: Transfer size (%s) must be valid int; greater than 0.\r\n", cmd_args[2]); + printf("Usage: 'db load N'; N>0\r\n"); + db_state = 0; + return; + } + db_state = 1; + bytes_loaded = 0; + printf("Expecting %d bytes\r\n", transfer_size); + return; + } + else if (isxdigit((int)cmd_args[1][0])) { // e.g. `db ff001234` actually loads the data` + int num_chars = strlen(cmd_args[1]); + uint8_t next_byte = 0; + + if (db_state != 1) { + printf("Error: Must issue db load command before transmitting data.\r\n"); + return; + } + if (num_chars % 2 != 0) { + printf("Error: number of hex digits in data string must be even. Received %d\r\n", num_chars); + printf("Still waiting for data\r\n"); + return; + } + char tmp_str[3] = {'\0', '\0', '\0'}; + + for (int i=0;i= buff_size || bytes_loaded >= transfer_size) { + db_state = 0; + printf("m-load-done\r\n"); + return; + } + } + printf("%d bytes received\r\n", bytes_loaded); + } + else if (strcmp(cmd_args[1], "getptr") == 0) { + printf("m-buff-ptr-%d\r\n", bytes_loaded); + } + else if (strcmp(cmd_args[1], "setptr") == 0) { + if (cmd_args[2] != NULL) { + bytes_loaded = atoi(cmd_args[2]); + } + else { + printf("Error: setptr requires a numeric argument: 'db setptr 123%%'"); + } + } + else if (strcmp(cmd_args[1], "print") == 0) { + int bytes_to_print = 0; + if (cmd_args[2] != NULL) { + bytes_to_print = atoi(cmd_args[2]); + } + if (bytes_to_print <= 0 || bytes_to_print > buff_size) { + bytes_to_print = buff_size; + } + printf("m-buffer-"); + for(int i=0; i buff_size/2) { + vals_to_print = buff_size/2; + } + print_vals_int16((int16_t *)byte_buff, vals_to_print); + } + else { + printf("Error: db: Unrecognized sub-command %s\r\n", cmd_args[1]); + } +} +void run_extraction(char *cmd_args[]) { + + // Feature extraction work + float32_t test_out[1024] = {0.0}; + float32_t dsp_buff[1024] = {0.0}; + // this will only operate on the first block_size (1024) elements of the input wav + + uint32_t timer_start, timer_stop; + char *endptr; + uint32_t offset; + + // Optional offset arg. "extract 1024", if cmd_arg[1] is present, convert to long + if (cmd_args[1] != NULL && *cmd_args[1] != '\0') { + offset = strtol(cmd_args[1], &endptr, 10); + } + else { + offset = 0; + } + timer_start = __HAL_TIM_GET_COUNTER(&htim16); + compute_lfbe_f32(test_wav_marvin+offset, test_out, dsp_buff); + timer_stop = __HAL_TIM_GET_COUNTER(&htim16); + + printf("TIM16: compute_lfbe_f32 took (%lu : %lu) = %lu TIM16 cycles\r\n", timer_start, timer_stop, timer_stop-timer_start); + printf("\r\n{\r\n"); + printf("\"Input\": "); + print_vals_int16(test_wav_marvin+offset, 1024); + printf(",\r\n \"Output\": "); + print_vals_float(test_out, 40); + printf("}\r\n"); +} + +void stop_detection(char *cmd_args[]) { + switch(g_i2s_state) { + // the stopping/idle combination may not be necessary, but it was originally set up + // to go to Stopping then wait for the current transaction to complete before Idle. + // But sometimes the current transaction never completes, leaving the program hung. + case Streaming: + g_i2s_state = Stopping; + g_i2s_status = HAL_SAI_DMAStop(&hsai_BlockA1); + g_i2s_state = Idle; + th_timestamp(); // this timestamp will stop the measurement of power + printf("Streaming stopped.\r\n"); + + printf("target activations: \r\n"); + print_vals_int8(g_act_buff, g_act_idx); // jhdbg + g_act_buff = NULL; + break; + case FileCapture: + g_i2s_state = Stopping; + g_i2s_status = HAL_SAI_DMAStop(&hsai_BlockA1); + g_i2s_state = Idle; + free(g_wav_record); + g_wav_record = NULL; + printf("Wav capture stopped.\r\n"); + break; + case Idle: + printf("I2S is already idle. Ignoring stop request\r\n"); + break; + case Stopping: + printf("Stop already requested.\r\n"); + break; + default: + printf("Unknown state %d detected. Requesting stop.\r\n", g_i2s_state); + g_i2s_state = Stopping; + } +} + +void start_detection(char *cmd_args[]) { + if(g_i2s_state != Idle) { + printf("I2S Rx currently in progress. Ignoring request\r\n"); + } + else { + g_i2s_state = Streaming; + + g_act_buff = (int8_t *)g_gp_buffer; + if( !g_act_buff ) { + printf("WARNING: Activation buffer malloc failed. Activation logging will not work.\r\n"); + } + g_int16s_read = 0; // jhdbg -- only needed when we're capturing the waveform in addition to detecting + g_first_frame = 1; // on the first frame of a recording we pulse the detection GPIO to synchronize timing. + + memset(g_act_buff, 0, g_gp_buff_bytes); + g_act_idx = 0; + + printf("Listening for I2S data ... \r\n"); + + // these memsets are not really needed, but they make it easier to tell + // if the write never happened. + memset(g_i2s_buffer0, 0xFF, g_i2s_chunk_size_bytes); + memset(g_i2s_buffer1, 0xFF, g_i2s_chunk_size_bytes); + + // first several cycles won't fully populate g_model_input, so initialize + // it with 0s to avoid unpredictable detections at the beginning + memset(g_model_input, 0x00, SWW_MODEL_INPUT_SIZE*sizeof(int8_t)); + memset(g_wav_block_buff, 0x00, SWW_WINLEN_SAMPLES*sizeof(int16_t)); + + th_timestamp(); // this timestamp will start the measurement of power + set_processing_pin_low(); // end of processing, used for duty cycle measurement + // pulse processing pin for 1us to align the duty cycle, energy measurements, and detections + set_processing_pin_high(); // end of processing, used for duty cycle measurement + delay_us(1); + set_processing_pin_low(); // end of processing, used for duty cycle measurement + + + g_i2s_status = HAL_SAI_Receive_DMA(&hsai_BlockA1, (uint8_t *)g_i2s_current_buff, g_i2s_chunk_size_bytes/2); + printf("DMA receive initiated.\r\n"); + } +} + +void i2s_capture(char *cmd_args[]) { + if(g_i2s_state != Idle ) { + printf("I2S Rx currently in progress. Ignoring request\r\n"); + return; + } + + if (cmd_args[1]) { + g_i2s_wav_len = atoi(cmd_args[1]); + if( g_i2s_wav_len > g_gp_buff_bytes/2) { + printf("Requested length %lu exceeds available memory. Capturing %lu samples\r\n", + g_i2s_wav_len, g_gp_buff_bytes/2); + g_i2s_wav_len = g_gp_buff_bytes/4; + } + } + else { + g_i2s_wav_len = g_gp_buff_bytes/2; // 2 bytes/sample + printf("No length specified. Capturing %lu samples\r\n", g_i2s_wav_len); + } + + g_i2s_state = FileCapture; + g_int16s_read = 0; + g_wav_record = (int16_t *)g_gp_buffer; // g_gp_buff_bytes bytes + if( !g_wav_record ) { + printf("WARNING: Recording buffer has no allocated memory. I2S Capture will fail.\r\n"); + } + printf("Listening for I2S data ... \r\n"); + memset(g_wav_record, 0, g_gp_buff_bytes); // *2 b/c wav_len is int16s + // these memsets are not really needed, but they make it easier to tell + // if the write never happened. + memset(g_i2s_buffer0, 0xFF, g_i2s_chunk_size_bytes); + memset(g_i2s_buffer1, 0xFF, g_i2s_chunk_size_bytes); + + g_i2s_status = HAL_SAI_Receive_DMA(&hsai_BlockA1, (uint8_t *)g_i2s_current_buff, g_i2s_chunk_size_bytes/2); + // you can also check hsai->State + printf("DMA receive initiated. status=%lu, state=%d\r\n", g_i2s_status, hsai_BlockA1.State); + printf(" Status: 0=OK, 1=Error, 2=Busy, 3=Timeout; State: 0=Reset, 1=Ready, 2=Busy (internal process), 18=Busy (Tx), 34=Busy (Rx)\r\n"); +} + +void print_help(char *cmd_args[]) { + char help_message[] = + "name -- print out an identifying message\r\n" + "run_model -- run the NN model. An optional argument class0, class1, or class2 runs the model\r\n" + " on a selected input that is expected to return 0 (WW), 1 (silent), or 2(other)\r\n" + "extract -- run the feature extractor on the first block of a predefined wav form (test_wav_marvin)\r\n" + "i2scap -- Captures about 1s of stereo audio over an I2S link\r\n" + "start -- Start wakeword detection. Repeatedly runs feature extraction and model on incoming I2S wav data" + "stop -- Stop wakeword detection" + "state -- print out the current operating mode (as int) and status of the I2S link" + "log -- The I2S capture function can write debug messages to a log. Prints and clears that log.\r\n" + "help -- Print this help message\r\n%" + ; + + printf(help_message); +} + +void print_and_clear_log(char *cmd_args[]) { + printf("Log contents[cp=%u]:\r\n<%s>\r\n", g_log.current_pos, g_log.buffer); + memset(g_log.buffer, 0, LOG_BUFFER_SIZE); + g_log.current_pos = 0; +} + +void print_state(char *cmd_args[]) { + printf("g_i2s_status=%lu, SAI state=%d\r\n", g_i2s_status, hsai_BlockA1.State); + printf(" Status: 0=OK, 1=Error, 2=Busy, 3=Timeout; State: 0=Reset, 1=Ready, 2=Busy (internal process), 18=Busy (Tx), 34=Busy (Rx)\r\n"); + printf("g_i2s_state = %d, g_int16s_read=%lu\r\n", g_i2s_state, g_int16s_read); +} + +void process_command(char *full_command) { + char *cmd_args[MAX_CMD_TOKENS] = {NULL}; + + printf("Received command: %s\r\n", full_command); + + // Split the command on spaces, so cmd_args[0] is the command itself + char* token = strtok(full_command, " "); + cmd_args[0] = token; + + // and cmd_args[1:] are the arguments + for(int i=1;i%s\r\n", i, (void *)cmd_args[i], cmd_args[i]); + // } + + // full_command should be " " (command and args delimited by spaces) + // put the command and arguments into the array cmd_arg[] + if (strcmp(cmd_args[0], "name") == 0) { + printf(EE_MSG_NAME, EE_DEVICE_NAME, TH_VENDOR_NAME_STRING); + } + else if (strcmp(cmd_args[0], "profile") == 0) { + printf("m-profile-[%s]\r\n", EE_FW_VERSION); + printf("m-model-[%s]\r\n", TH_MODEL_VERSION); + } + else if(strcmp(cmd_args[0], "run_model") == 0) { + run_model_on_test_data(cmd_args); + } + else if(strcmp(cmd_args[0], "extract") == 0) { + run_extraction(cmd_args); + } + else if(strcmp(cmd_args[0], "i2scap") == 0) { + i2s_capture(cmd_args); + } + else if(strcmp(cmd_args[0], "log") == 0) { + print_and_clear_log(cmd_args); + } + else if(strcmp(cmd_args[0], "start") == 0) { + start_detection(cmd_args); + } + else if(strcmp(cmd_args[0], "stop") == 0) { + stop_detection(cmd_args); + } + else if(strcmp(cmd_args[0], "state") == 0) { + print_state(cmd_args); + } + else if(strcmp(cmd_args[0], "db") == 0) { + load_or_print_buff(cmd_args); + } + else if(strcmp(cmd_args[0], "help") == 0) { + print_help(cmd_args); + } + else if(strcmp(cmd_args[0], "timestamp") == 0) { + th_timestamp(); // mostly useful for testing the timestamp code + } + // These next two are mostly useful for testing + else if(strcmp(cmd_args[0], "proc_hi") == 0) { + set_processing_pin_high(); + } + else if(strcmp(cmd_args[0], "proc_lo") == 0) { + set_processing_pin_low(); + } + else if(strcmp(cmd_args[0], "infer_wav") == 0) { + infer_static_wav(cmd_args); + } + else if(strcmp(cmd_args[0], "extract_uart_stream") == 0) { + extract_features_on_chunk(cmd_args); + } + else if(cmd_args[0] == 0) { + printf("Empty command (only a %% read). Type 'help%%' for help\r\n"); // %% => % + } + else { + printf("Unrecognized command %s\r\n", full_command); + } + printf(EE_MSG_READY); +} + +void th_timestamp(void) { + HAL_GPIO_WritePin(timestamp_GPIO_Port, timestamp_Pin, GPIO_PIN_RESET); + delay_us(1); + HAL_GPIO_WritePin(timestamp_GPIO_Port, timestamp_Pin, GPIO_PIN_SET); + + // unsigned long microSeconds = 0ul; + // microSeconds = us_ticker_read(); + // th_printf(EE_MSG_TIMESTAMP, microSeconds); +} + +void set_processing_pin_high(void) { + HAL_GPIO_WritePin(Processing_GPIO_Port, Processing_Pin, GPIO_PIN_SET); +} + +void set_processing_pin_low(void) { + HAL_GPIO_WritePin(Processing_GPIO_Port, Processing_Pin, GPIO_PIN_RESET); +} + +void infer_static_wav(char *cmd_args[]) { + // feature_buff is used internally as a 2nd internal scratch space, + // in the FFT domain, so it needs to be winlen_samples long, even though + // ultimately it will only hold NUM_MEL_FILTERS values. This can probably + // be improved with a refactored compute_lfbe_f32(). + static float32_t feature_buff[SWW_WINLEN_SAMPLES]; + static float32_t dsp_buff[SWW_WINLEN_SAMPLES]; + int num_steps; // jhdbg + int offset; + uint32_t wav_len=0; + const int16_t *wav_ptr=NULL; + + offset = atoi(cmd_args[1]); + wav_ptr = test_wav_long + offset; + wav_len = test_wav_long_len-offset; + printf("Infering on static wav with offset = %d\r\n", offset); + + num_steps = (wav_len - (SWW_WINLEN_SAMPLES - SWW_WINSTRIDE_SAMPLES))/SWW_WINSTRIDE_SAMPLES; + + // extract the input scale factor from the (file-global) ai_input + float32_t input_scale_factor = *(ai_input[0].meta_info->intq_info->info->scale); + + // initialize model input buffer to 0s. + for(int i=0;i DETECT_THRESHOLD || g_first_frame) { + printf("[%d]: Detection (%d). g_first_frame=%lu\r\n", idx_step, out_data[0], g_first_frame); + log_printf(&g_log, "[%d]: Detection (%d). g_first_frame=%lu\r\n", idx_step, out_data[0], g_first_frame); + g_first_frame = 0; + } + else if( out_data[0] > 100) { + printf("[%d]: Near miss (%d). \r\n", idx_step, out_data[0]); + } + + printf("%d), \r\n", out_data[0]); + } +} +void process_chunk_and_cont_capture(SAI_HandleTypeDef *hsai) { + int reading_complete=0; + + g_int16s_read += g_i2s_chunk_size_bytes/2; + + // idle_buffer is the one that will be idle after we switch + int16_t* idle_buffer = g_i2s_buff_sel ? g_i2s_buffer1 : g_i2s_buffer0; + g_i2s_buff_sel = g_i2s_buff_sel ^ 1; // toggle between 0/1 => g_i2s_buffer0/1 + g_i2s_current_buff = g_i2s_buff_sel ? g_i2s_buffer1 : g_i2s_buffer0; + + if(g_int16s_read + g_i2s_chunk_size_bytes/2 <= g_i2s_wav_len){ + // there is space left for a full chunk + g_i2s_status = HAL_SAI_Receive_DMA(hsai, (uint8_t *)g_i2s_current_buff, g_i2s_chunk_size_bytes/2); + } + else { + // if there is only space for a partial read + // i.e. (g_int16s_read < g_i2s_wav_len < g_int16s_read + g_i2s_chunk_size_bytes/2) + // don't start the read, b/c you'll overflow the allocated buffer + // that means you'll read less than requested, but avoid a seg-fault. + reading_complete = 1; + } + + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_8, GPIO_PIN_SET); + + // for 1024 bytes, this memcpy takes about 50 us. + memcpy((uint8_t*)(g_wav_record+g_int16s_read-g_i2s_chunk_size_bytes/2), idle_buffer, g_i2s_chunk_size_bytes); + + if( reading_complete ){ + printf("DMA Receive completed %lu int16s read out of %lu requested\r\n", g_int16s_read, g_i2s_wav_len); + print_vals_int16(g_wav_record, g_int16s_read); + g_wav_record = NULL; + g_i2s_state = Idle; + } + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_8, GPIO_PIN_RESET); +} + + +void extract_features_on_chunk(char *cmd_args[]) { + + + + // feature_buff is used internally as a 2nd internal scratch space, + // in the FFT domain, so it needs to be winlen_samples long, even though + // ultimately it will only hold NUM_MEL_FILTERS values. This can probably + // be improved with a refactored compute_lfbe_f32(). + static float32_t feature_buff[SWW_WINLEN_SAMPLES]; + static float32_t dsp_buff[SWW_WINLEN_SAMPLES]; + static int num_calls=0; + + // extract the input scale factor from the (file-global) ai_input + float32_t input_scale_factor = *(ai_input[0].meta_info->intq_info->info->scale); + + + if( num_calls == 0) { + for(int i=0;i] are old samples to be + // shifted to the beginning of the clip. After this block, + // g_wav_block_buff[0:(winlen-winstride)] is populated + for(int i=SWW_WINSTRIDE_SAMPLES;iintq_info->info->scale); + + // idle_buffer is the one that will be idle after we switch + int16_t *idle_buffer = g_i2s_buff_sel ? g_i2s_buffer1 : g_i2s_buffer0; + g_i2s_buff_sel = g_i2s_buff_sel ^ 1; // toggle between 0/1 => g_i2s_buffer0/1 + g_i2s_current_buff = g_i2s_buff_sel ? g_i2s_buffer1 : g_i2s_buffer0; + + g_i2s_status = HAL_SAI_Receive_DMA(hsai, (uint8_t *)g_i2s_current_buff, g_i2s_chunk_size_bytes/2); + + // g_wav_block_buff[SWW_WINSTRIDE_SAMPLES:] are old samples to be + // shifted to the beginning of the clip. After this block, + // g_wav_block_buff[0:(winlen-winstride)] is populated + for(int i=SWW_WINSTRIDE_SAMPLES;i DETECT_THRESHOLD || g_first_frame) { + HAL_GPIO_WritePin(WW_DETECTED_GPIO_Port, WW_DETECTED_Pin, GPIO_PIN_RESET); + delay_us(1); + HAL_GPIO_WritePin(WW_DETECTED_GPIO_Port, WW_DETECTED_Pin, GPIO_PIN_SET); + g_first_frame = 0; + } + + if ( g_act_idx < (g_gp_buff_bytes/sizeof(g_act_buff[0])) ) { + g_act_buff[g_act_idx++] = out_data[0]; + } + + num_calls++; + set_processing_pin_low(); // end of processing, used for duty cycle measurement +} + +void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) { + if( g_i2s_state == FileCapture) { + process_chunk_and_cont_capture(hsai); + } + else if( g_i2s_state == Streaming) { + process_chunk_and_cont_streaming(hsai); + } + else if( g_i2s_state == Stopping) { + printf("Streaming stopped\r\n"); + g_i2s_state = Idle; + } +} + +void compute_lfbe_f32(const int16_t *pSrc, float32_t *pDst, float32_t *pTmp) +{ + const uint32_t block_length=SWW_WINLEN_SAMPLES; + const float32_t inv_block_length=1.0/SWW_WINLEN_SAMPLES; + const uint32_t spec_len = SWW_WINLEN_SAMPLES/2+1; + const float32_t preemphasis_coef = 0.96875; // 1.0 - 2.0 ** -5; + const float32_t power_offset = 52.0; + const uint32_t num_filters = 40; + int i; // for looping + // to maintain continuity in pre-emphasis over segment boundaries + static float32_t last_value = 0.0; + arm_status op_result = ARM_MATH_SUCCESS; + + // convert int16_t pSrc to float32_t. range [-32768:32767] => [-1.0,1.0) + // WINLEN - WINSTRIDE of these have already been converted once, so a little speedup + // could probably be gained by factoring this out into process_chunk_and_continue_streaming + for(i=0;i pDst[1:] + arm_sub_f32 (pDst+1, pTmp, pDst+1, block_length-1); + + // apply hamming window to pDst and put results in pTmp. + arm_mult_f32(pDst, hamm_win_1024, pTmp, block_length); + + + /* RFFT based implementation */ + arm_rfft_fast_instance_f32 rfft_s; + op_result = arm_rfft_fast_init_f32(&rfft_s, block_length); + if (op_result != ARM_MATH_SUCCESS) { + printf("Error %d in arm_rfft_fast_init_f32", op_result); + } + arm_rfft_fast_f32(&rfft_s,pTmp,pDst,0); // use config rfft_s; FFT(pTmp) => pDst, ifft=0 + + // Now we need to take the magnitude of the spectrum. For block_length=1024, it will be 513 elements + // we'll use pTmp as an array of block_length/2+1 real values. + // the N/2th element is real and stuck in pDst[1] (where fft[0].imag=0 should be) + // move that to pTmp[block_length/2] + pTmp[block_length/2] = pDst[1]; // real value corresponding to fsamp/2 + pDst[1] = 0; // so now pDst[0,1] = real,imag elements at f=0 (always real, so imag=0) + arm_cmplx_mag_f32(pDst,pTmp,block_length/2); // mag(pDst) => pTmp. pTmp[512] already set. + + // powspec = (1 / data_config['window_size_samples']) * tf.square(magspec) + arm_mult_f32(pTmp, pTmp,pDst, spec_len); // pDst[0:513] = pTmp[0:513]^2 + arm_scale_f32(pDst, inv_block_length, pTmp, spec_len); + + + // The original lin2mel matrix is spec_len x num_filters, where each column holds one mel filter, + // lin2mel_packed_x has all the non-zero elements packed together in one 1D array + // _filter_starts are the locations in each *original* column where the non-zero elements start + // _filter_lens is how many non-zero elements are in each original column + // So the i_th filter start in lin2mel_packed at sum(_filter_lens[:i]) + // And the corresponding spectrum segment starts at linear_spectrum[_filter_starts[i]] + int lin2mel_coeff_idx = 0; + /* Apply MEL filters; linear spectrum is now in pTmp[0:spec_len], put mel spectrum in pDst[0:num_filters] */ + for(i=0; i 1e-30) ? pDst[i] : 1e-30; + } + + for(i=0; i 1.0) ? 1.0 : pTmp[i]); + } +} + + diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Src/syscalls.c b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Src/syscalls.c similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Src/syscalls.c rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Core/Src/syscalls.c diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Src/sysmem.c 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a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Device/ST/STM32L4xx/License.md b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Device/ST/STM32L4xx/License.md similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Device/ST/STM32L4xx/License.md rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Device/ST/STM32L4xx/License.md diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/cmsis_armcc.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/cmsis_armcc.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/cmsis_armcc.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/cmsis_armcc.h index da9d654e..59f173ac 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/cmsis_armcc.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/cmsis_armcc.h @@ -1,894 +1,894 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file - * @version V5.1.0 - * @date 08. May 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use Arm Compiler Toolchain V4.0.677 or later!" -#endif - -/* CMSIS compiler control architecture macros */ -#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ - (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) - #define __ARM_ARCH_6M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) - #define __ARM_ARCH_7M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) - #define __ARM_ARCH_7EM__ 1 -#endif - - /* __ARM_ARCH_8M_BASE__ not applicable */ - /* __ARM_ARCH_8M_MAIN__ not applicable */ - -/* CMSIS compiler control DSP macros */ -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - #define __ARM_FEATURE_DSP 1 -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE static __forceinline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __declspec(noreturn) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed)) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT __packed struct -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION __packed union -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __memory_changed() -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START -#define __PROGRAM_START __main -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) -#endif - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1U); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#else - (void)fpscr; -#endif -} - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0U) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return result; -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/cmsis_armclang.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/cmsis_armclang.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/cmsis_armclang.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/cmsis_armclang.h index 478f75bb..e917f357 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/cmsis_armclang.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/cmsis_armclang.h @@ -1,1444 +1,1444 @@ -/**************************************************************************//** - * @file cmsis_armclang.h - * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V5.2.0 - * @date 08. May 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ - -#ifndef __CMSIS_ARMCLANG_H -#define __CMSIS_ARMCLANG_H - -#pragma clang system_header /* treat file as system include file */ - -#ifndef __ARM_COMPAT_H -#include /* Compatibility header for Arm Compiler 5 intrinsics */ -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START -#define __PROGRAM_START __main -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) -#endif - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); see arm_compat.h */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); see arm_compat.h */ - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr -#else -#define __get_FPSCR() ((uint32_t)0U) -#endif - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __set_FPSCR __builtin_arm_set_fpscr -#else -#define __set_FPSCR(x) ((void)(x)) -#endif - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF) - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV(value) __builtin_bswap32(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16(value) __ROR(__REV(value), 16) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REVSH(value) (int16_t)__builtin_bswap16(value) - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __builtin_arm_rbit - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __builtin_arm_ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -#define __SADD8 __builtin_arm_sadd8 -#define __QADD8 __builtin_arm_qadd8 -#define __SHADD8 __builtin_arm_shadd8 -#define __UADD8 __builtin_arm_uadd8 -#define __UQADD8 __builtin_arm_uqadd8 -#define __UHADD8 __builtin_arm_uhadd8 -#define __SSUB8 __builtin_arm_ssub8 -#define __QSUB8 __builtin_arm_qsub8 -#define __SHSUB8 __builtin_arm_shsub8 -#define __USUB8 __builtin_arm_usub8 -#define __UQSUB8 __builtin_arm_uqsub8 -#define __UHSUB8 __builtin_arm_uhsub8 -#define __SADD16 __builtin_arm_sadd16 -#define __QADD16 __builtin_arm_qadd16 -#define __SHADD16 __builtin_arm_shadd16 -#define __UADD16 __builtin_arm_uadd16 -#define __UQADD16 __builtin_arm_uqadd16 -#define __UHADD16 __builtin_arm_uhadd16 -#define __SSUB16 __builtin_arm_ssub16 -#define __QSUB16 __builtin_arm_qsub16 -#define __SHSUB16 __builtin_arm_shsub16 -#define __USUB16 __builtin_arm_usub16 -#define __UQSUB16 __builtin_arm_uqsub16 -#define __UHSUB16 __builtin_arm_uhsub16 -#define __SASX __builtin_arm_sasx -#define __QASX __builtin_arm_qasx -#define __SHASX __builtin_arm_shasx -#define __UASX __builtin_arm_uasx -#define __UQASX __builtin_arm_uqasx -#define __UHASX __builtin_arm_uhasx -#define __SSAX __builtin_arm_ssax -#define __QSAX __builtin_arm_qsax -#define __SHSAX __builtin_arm_shsax -#define __USAX __builtin_arm_usax -#define __UQSAX __builtin_arm_uqsax -#define __UHSAX __builtin_arm_uhsax -#define __USAD8 __builtin_arm_usad8 -#define __USADA8 __builtin_arm_usada8 -#define __SSAT16 __builtin_arm_ssat16 -#define __USAT16 __builtin_arm_usat16 -#define __UXTB16 __builtin_arm_uxtb16 -#define __UXTAB16 __builtin_arm_uxtab16 -#define __SXTB16 __builtin_arm_sxtb16 -#define __SXTAB16 __builtin_arm_sxtab16 -#define __SMUAD __builtin_arm_smuad -#define __SMUADX __builtin_arm_smuadx -#define __SMLAD __builtin_arm_smlad -#define __SMLADX __builtin_arm_smladx -#define __SMLALD __builtin_arm_smlald -#define __SMLALDX __builtin_arm_smlaldx -#define __SMUSD __builtin_arm_smusd -#define __SMUSDX __builtin_arm_smusdx -#define __SMLSD __builtin_arm_smlsd -#define __SMLSDX __builtin_arm_smlsdx -#define __SMLSLD __builtin_arm_smlsld -#define __SMLSLDX __builtin_arm_smlsldx -#define __SEL __builtin_arm_sel -#define __QADD __builtin_arm_qadd -#define __QSUB __builtin_arm_qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCLANG_H */ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/cmsis_armclang_ltm.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/cmsis_armclang_ltm.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/cmsis_armclang_ltm.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/cmsis_armclang_ltm.h index 1b5a9652..feec3240 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/cmsis_armclang_ltm.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/cmsis_armclang_ltm.h @@ -1,1891 +1,1891 @@ -/**************************************************************************//** - * @file cmsis_armclang_ltm.h - * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V1.2.0 - * @date 08. May 2019 - ******************************************************************************/ -/* - * Copyright (c) 2018-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ - -#ifndef __CMSIS_ARMCLANG_H -#define __CMSIS_ARMCLANG_H - -#pragma clang system_header /* treat file as system include file */ - -#ifndef __ARM_COMPAT_H -#include /* Compatibility header for Arm Compiler 5 intrinsics */ -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START -#define __PROGRAM_START __main -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); see arm_compat.h */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); see arm_compat.h */ - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr -#else -#define __get_FPSCR() ((uint32_t)0U) -#endif - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __set_FPSCR __builtin_arm_set_fpscr -#else -#define __set_FPSCR(x) ((void)(x)) -#endif - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF) - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV(value) __builtin_bswap32(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16(value) __ROR(__REV(value), 16) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REVSH(value) (int16_t)__builtin_bswap16(value) - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __builtin_arm_rbit - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __builtin_arm_ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCLANG_H */ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/cmsis_compiler.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 00000000..adbf296f --- /dev/null +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/cmsis_gcc.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/cmsis_gcc.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/cmsis_gcc.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/cmsis_gcc.h index 1e08e7e8..3ddcc58b 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/cmsis_gcc.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/cmsis_gcc.h @@ -1,2168 +1,2168 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS compiler GCC header file - * @version V5.2.0 - * @date 08. May 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -/* Fallback for __has_builtin */ -#ifndef __has_builtin - #define __has_builtin(x) (0) -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START - -/** - \brief Initializes data and bss sections - \details This default implementations initialized all data and additional bss - sections relying on .copy.table and .zero.table specified properly - in the used linker script. - - */ -__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) -{ - extern void _start(void) __NO_RETURN; - - typedef struct { - uint32_t const* src; - uint32_t* dest; - uint32_t wlen; - } __copy_table_t; - - typedef struct { - uint32_t* dest; - uint32_t wlen; - } __zero_table_t; - - extern const __copy_table_t __copy_table_start__; - extern const __copy_table_t __copy_table_end__; - extern const __zero_table_t __zero_table_start__; - extern const __zero_table_t __zero_table_end__; - - for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { - for(uint32_t i=0u; iwlen; ++i) { - pTable->dest[i] = pTable->src[i]; - } - } - - for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { - for(uint32_t i=0u; iwlen; ++i) { - pTable->dest[i] = 0u; - } - } - - _start(); -} - -#define __PROGRAM_START __cmsis_start -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP __StackTop -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT __StackLimit -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) -#endif - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_get_fpscr) -// Re-enable using built-in when GCC has been fixed -// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - return __builtin_arm_get_fpscr(); -#else - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#endif -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_set_fpscr) -// Re-enable using built-in when GCC has been fixed -// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - __builtin_arm_set_fpscr(fpscr); -#else - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); -#endif -#else - (void)fpscr; -#endif -} - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __ASM volatile ("nop") - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __ASM volatile ("wfi") - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __ASM volatile ("wfe") - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __ASM volatile ("sev") - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__STATIC_FORCEINLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__STATIC_FORCEINLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__STATIC_FORCEINLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (int16_t)__builtin_bswap16(value); -#else - int16_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return result; -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__STATIC_FORCEINLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ - __extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#pragma GCC diagnostic pop - -#endif /* __CMSIS_GCC_H */ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/cmsis_iccarm.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/cmsis_iccarm.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/cmsis_iccarm.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/cmsis_iccarm.h index 7af75628..12d68fd9 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/cmsis_iccarm.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/cmsis_iccarm.h @@ -1,964 +1,964 @@ -/**************************************************************************//** - * @file cmsis_iccarm.h - * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.1.0 - * @date 08. May 2019 - ******************************************************************************/ - -//------------------------------------------------------------------------------ -// -// Copyright (c) 2017-2019 IAR Systems -// Copyright (c) 2017-2019 Arm Limited. All rights reserved. -// -// Licensed under the Apache License, Version 2.0 (the "License") -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -//------------------------------------------------------------------------------ - - -#ifndef __CMSIS_ICCARM_H__ -#define __CMSIS_ICCARM_H__ - -#ifndef __ICCARM__ - #error This file should only be compiled by ICCARM -#endif - -#pragma system_include - -#define __IAR_FT _Pragma("inline=forced") __intrinsic - -#if (__VER__ >= 8000000) - #define __ICCARM_V8 1 -#else - #define __ICCARM_V8 0 -#endif - -#ifndef __ALIGNED - #if __ICCARM_V8 - #define __ALIGNED(x) __attribute__((aligned(x))) - #elif (__VER__ >= 7080000) - /* Needs IAR language extensions */ - #define __ALIGNED(x) __attribute__((aligned(x))) - #else - #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. - #define __ALIGNED(x) - #endif -#endif - - -/* Define compiler macros for CPU architecture, used in CMSIS 5. - */ -#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ -/* Macros already defined */ -#else - #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' - #if __ARM_ARCH == 6 - #define __ARM_ARCH_6M__ 1 - #elif __ARM_ARCH == 7 - #if __ARM_FEATURE_DSP - #define __ARM_ARCH_7EM__ 1 - #else - #define __ARM_ARCH_7M__ 1 - #endif - #endif /* __ARM_ARCH */ - #endif /* __ARM_ARCH_PROFILE == 'M' */ -#endif - -/* Alternativ core deduction for older ICCARM's */ -#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ - !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) - #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) - #define __ARM_ARCH_6M__ 1 - #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) - #define __ARM_ARCH_7M__ 1 - #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) - #define __ARM_ARCH_7EM__ 1 - #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #else - #error "Unknown target." - #endif -#endif - - - -#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 - #define __IAR_M0_FAMILY 1 -#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 - #define __IAR_M0_FAMILY 1 -#else - #define __IAR_M0_FAMILY 0 -#endif - - -#ifndef __ASM - #define __ASM __asm -#endif - -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -#ifndef __INLINE - #define __INLINE inline -#endif - -#ifndef __NO_RETURN - #if __ICCARM_V8 - #define __NO_RETURN __attribute__((__noreturn__)) - #else - #define __NO_RETURN _Pragma("object_attribute=__noreturn") - #endif -#endif - -#ifndef __PACKED - #if __ICCARM_V8 - #define __PACKED __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED __packed - #endif -#endif - -#ifndef __PACKED_STRUCT - #if __ICCARM_V8 - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_STRUCT __packed struct - #endif -#endif - -#ifndef __PACKED_UNION - #if __ICCARM_V8 - #define __PACKED_UNION union __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_UNION __packed union - #endif -#endif - -#ifndef __RESTRICT - #if __ICCARM_V8 - #define __RESTRICT __restrict - #else - /* Needs IAR language extensions */ - #define __RESTRICT restrict - #endif -#endif - -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif - -#ifndef __FORCEINLINE - #define __FORCEINLINE _Pragma("inline=forced") -#endif - -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE -#endif - -#ifndef __UNALIGNED_UINT16_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint16_t __iar_uint16_read(void const *ptr) -{ - return *(__packed uint16_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) -#endif - - -#ifndef __UNALIGNED_UINT16_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) -{ - *(__packed uint16_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint32_t __iar_uint32_read(void const *ptr) -{ - return *(__packed uint32_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) -#endif - -#ifndef __UNALIGNED_UINT32_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) -{ - *(__packed uint32_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32 /* deprecated */ -#pragma language=save -#pragma language=extended -__packed struct __iar_u32 { uint32_t v; }; -#pragma language=restore -#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) -#endif - -#ifndef __USED - #if __ICCARM_V8 - #define __USED __attribute__((used)) - #else - #define __USED _Pragma("__root") - #endif -#endif - -#ifndef __WEAK - #if __ICCARM_V8 - #define __WEAK __attribute__((weak)) - #else - #define __WEAK _Pragma("__weak") - #endif -#endif - -#ifndef __PROGRAM_START -#define __PROGRAM_START __iar_program_start -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP CSTACK$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT CSTACK$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __vector_table -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE @".intvec" -#endif - -#ifndef __ICCARM_INTRINSICS_VERSION__ - #define __ICCARM_INTRINSICS_VERSION__ 0 -#endif - -#if __ICCARM_INTRINSICS_VERSION__ == 2 - - #if defined(__CLZ) - #undef __CLZ - #endif - #if defined(__REVSH) - #undef __REVSH - #endif - #if defined(__RBIT) - #undef __RBIT - #endif - #if defined(__SSAT) - #undef __SSAT - #endif - #if defined(__USAT) - #undef __USAT - #endif - - #include "iccarm_builtin.h" - - #define __disable_fault_irq __iar_builtin_disable_fiq - #define __disable_irq __iar_builtin_disable_interrupt - #define __enable_fault_irq __iar_builtin_enable_fiq - #define __enable_irq __iar_builtin_enable_interrupt - #define __arm_rsr __iar_builtin_rsr - #define __arm_wsr __iar_builtin_wsr - - - #define __get_APSR() (__arm_rsr("APSR")) - #define __get_BASEPRI() (__arm_rsr("BASEPRI")) - #define __get_CONTROL() (__arm_rsr("CONTROL")) - #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) - - #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - #define __get_FPSCR() (__arm_rsr("FPSCR")) - #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) - #else - #define __get_FPSCR() ( 0 ) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #define __get_IPSR() (__arm_rsr("IPSR")) - #define __get_MSP() (__arm_rsr("MSP")) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __get_MSPLIM() (0U) - #else - #define __get_MSPLIM() (__arm_rsr("MSPLIM")) - #endif - #define __get_PRIMASK() (__arm_rsr("PRIMASK")) - #define __get_PSP() (__arm_rsr("PSP")) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __get_PSPLIM() (0U) - #else - #define __get_PSPLIM() (__arm_rsr("PSPLIM")) - #endif - - #define __get_xPSR() (__arm_rsr("xPSR")) - - #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) - #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) - #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) - #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) - #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __set_MSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) - #endif - #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) - #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __set_PSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) - #endif - - #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) - #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) - #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) - #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) - #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) - #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) - #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) - #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) - #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) - #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) - #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) - #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) - #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) - #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __TZ_get_PSPLIM_NS() (0U) - #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) - #else - #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) - #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) - #endif - - #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) - #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) - - #define __NOP __iar_builtin_no_operation - - #define __CLZ __iar_builtin_CLZ - #define __CLREX __iar_builtin_CLREX - - #define __DMB __iar_builtin_DMB - #define __DSB __iar_builtin_DSB - #define __ISB __iar_builtin_ISB - - #define __LDREXB __iar_builtin_LDREXB - #define __LDREXH __iar_builtin_LDREXH - #define __LDREXW __iar_builtin_LDREX - - #define __RBIT __iar_builtin_RBIT - #define __REV __iar_builtin_REV - #define __REV16 __iar_builtin_REV16 - - __IAR_FT int16_t __REVSH(int16_t val) - { - return (int16_t) __iar_builtin_REVSH(val); - } - - #define __ROR __iar_builtin_ROR - #define __RRX __iar_builtin_RRX - - #define __SEV __iar_builtin_SEV - - #if !__IAR_M0_FAMILY - #define __SSAT __iar_builtin_SSAT - #endif - - #define __STREXB __iar_builtin_STREXB - #define __STREXH __iar_builtin_STREXH - #define __STREXW __iar_builtin_STREX - - #if !__IAR_M0_FAMILY - #define __USAT __iar_builtin_USAT - #endif - - #define __WFE __iar_builtin_WFE - #define __WFI __iar_builtin_WFI - - #if __ARM_MEDIA__ - #define __SADD8 __iar_builtin_SADD8 - #define __QADD8 __iar_builtin_QADD8 - #define __SHADD8 __iar_builtin_SHADD8 - #define __UADD8 __iar_builtin_UADD8 - #define __UQADD8 __iar_builtin_UQADD8 - #define __UHADD8 __iar_builtin_UHADD8 - #define __SSUB8 __iar_builtin_SSUB8 - #define __QSUB8 __iar_builtin_QSUB8 - #define __SHSUB8 __iar_builtin_SHSUB8 - #define __USUB8 __iar_builtin_USUB8 - #define __UQSUB8 __iar_builtin_UQSUB8 - #define __UHSUB8 __iar_builtin_UHSUB8 - #define __SADD16 __iar_builtin_SADD16 - #define __QADD16 __iar_builtin_QADD16 - #define __SHADD16 __iar_builtin_SHADD16 - #define __UADD16 __iar_builtin_UADD16 - #define __UQADD16 __iar_builtin_UQADD16 - #define __UHADD16 __iar_builtin_UHADD16 - #define __SSUB16 __iar_builtin_SSUB16 - #define __QSUB16 __iar_builtin_QSUB16 - #define __SHSUB16 __iar_builtin_SHSUB16 - #define __USUB16 __iar_builtin_USUB16 - #define __UQSUB16 __iar_builtin_UQSUB16 - #define __UHSUB16 __iar_builtin_UHSUB16 - #define __SASX __iar_builtin_SASX - #define __QASX __iar_builtin_QASX - #define __SHASX __iar_builtin_SHASX - #define __UASX __iar_builtin_UASX - #define __UQASX __iar_builtin_UQASX - #define __UHASX __iar_builtin_UHASX - #define __SSAX __iar_builtin_SSAX - #define __QSAX __iar_builtin_QSAX - #define __SHSAX __iar_builtin_SHSAX - #define __USAX __iar_builtin_USAX - #define __UQSAX __iar_builtin_UQSAX - #define __UHSAX __iar_builtin_UHSAX - #define __USAD8 __iar_builtin_USAD8 - #define __USADA8 __iar_builtin_USADA8 - #define __SSAT16 __iar_builtin_SSAT16 - #define __USAT16 __iar_builtin_USAT16 - #define __UXTB16 __iar_builtin_UXTB16 - #define __UXTAB16 __iar_builtin_UXTAB16 - #define __SXTB16 __iar_builtin_SXTB16 - #define __SXTAB16 __iar_builtin_SXTAB16 - #define __SMUAD __iar_builtin_SMUAD - #define __SMUADX __iar_builtin_SMUADX - #define __SMMLA __iar_builtin_SMMLA - #define __SMLAD __iar_builtin_SMLAD - #define __SMLADX __iar_builtin_SMLADX - #define __SMLALD __iar_builtin_SMLALD - #define __SMLALDX __iar_builtin_SMLALDX - #define __SMUSD __iar_builtin_SMUSD - #define __SMUSDX __iar_builtin_SMUSDX - #define __SMLSD __iar_builtin_SMLSD - #define __SMLSDX __iar_builtin_SMLSDX - #define __SMLSLD __iar_builtin_SMLSLD - #define __SMLSLDX __iar_builtin_SMLSLDX - #define __SEL __iar_builtin_SEL - #define __QADD __iar_builtin_QADD - #define __QSUB __iar_builtin_QSUB - #define __PKHBT __iar_builtin_PKHBT - #define __PKHTB __iar_builtin_PKHTB - #endif - -#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #define __CLZ __cmsis_iar_clz_not_active - #define __SSAT __cmsis_iar_ssat_not_active - #define __USAT __cmsis_iar_usat_not_active - #define __RBIT __cmsis_iar_rbit_not_active - #define __get_APSR __cmsis_iar_get_APSR_not_active - #endif - - - #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) - #define __get_FPSCR __cmsis_iar_get_FPSR_not_active - #define __set_FPSCR __cmsis_iar_set_FPSR_not_active - #endif - - #ifdef __INTRINSICS_INCLUDED - #error intrinsics.h is already included previously! - #endif - - #include - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #undef __CLZ - #undef __SSAT - #undef __USAT - #undef __RBIT - #undef __get_APSR - - __STATIC_INLINE uint8_t __CLZ(uint32_t data) - { - if (data == 0U) { return 32U; } - - uint32_t count = 0U; - uint32_t mask = 0x80000000U; - - while ((data & mask) == 0U) - { - count += 1U; - mask = mask >> 1U; - } - return count; - } - - __STATIC_INLINE uint32_t __RBIT(uint32_t v) - { - uint8_t sc = 31U; - uint32_t r = v; - for (v >>= 1U; v; v >>= 1U) - { - r <<= 1U; - r |= v & 1U; - sc--; - } - return (r << sc); - } - - __STATIC_INLINE uint32_t __get_APSR(void) - { - uint32_t res; - __asm("MRS %0,APSR" : "=r" (res)); - return res; - } - - #endif - - #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) - #undef __get_FPSCR - #undef __set_FPSCR - #define __get_FPSCR() (0) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #pragma diag_suppress=Pe940 - #pragma diag_suppress=Pe177 - - #define __enable_irq __enable_interrupt - #define __disable_irq __disable_interrupt - #define __NOP __no_operation - - #define __get_xPSR __get_PSR - - #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) - - __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) - { - return __LDREX((unsigned long *)ptr); - } - - __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) - { - return __STREX(value, (unsigned long *)ptr); - } - #endif - - - /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - #if (__CORTEX_M >= 0x03) - - __IAR_FT uint32_t __RRX(uint32_t value) - { - uint32_t result; - __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); - return(result); - } - - __IAR_FT void __set_BASEPRI_MAX(uint32_t value) - { - __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); - } - - - #define __enable_fault_irq __enable_fiq - #define __disable_fault_irq __disable_fiq - - - #endif /* (__CORTEX_M >= 0x03) */ - - __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) - { - return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); - } - - #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - __IAR_FT uint32_t __get_MSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,MSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_MSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR MSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __get_PSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,PSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_PSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR PSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) - { - __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PSP_NS(uint32_t value) - { - __asm volatile("MSR PSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_MSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSP_NS(uint32_t value) - { - __asm volatile("MSR MSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_SP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,SP_NS" : "=r" (res)); - return res; - } - __IAR_FT void __TZ_set_SP_NS(uint32_t value) - { - __asm volatile("MSR SP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) - { - __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) - { - __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) - { - __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) - { - __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); - } - - #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ - -#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - -#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) - -#if __IAR_M0_FAMILY - __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) - { - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; - } - - __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) - { - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; - } -#endif - -#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - - __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) - { - uint32_t res; - __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) - { - uint32_t res; - __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) - { - uint32_t res; - __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return res; - } - - __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) - { - __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) - { - __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) - { - __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); - } - -#endif /* (__CORTEX_M >= 0x03) */ - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - - __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return res; - } - - __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) - { - __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) - { - __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) - { - __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - -#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ - -#undef __IAR_FT -#undef __IAR_M0_FAMILY -#undef __ICCARM_V8 - -#pragma diag_default=Pe940 -#pragma diag_default=Pe177 - -#endif /* __CMSIS_ICCARM_H__ */ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/cmsis_version.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/cmsis_version.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/cmsis_version.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/cmsis_version.h index 3174cf60..f2e27466 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/cmsis_version.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/cmsis_version.h @@ -1,39 +1,39 @@ -/**************************************************************************//** - * @file cmsis_version.h - * @brief CMSIS Core(M) Version definitions - * @version V5.0.3 - * @date 24. June 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CMSIS_VERSION_H -#define __CMSIS_VERSION_H - -/* CMSIS Version definitions */ -#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ -#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ - __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ -#endif +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_armv81mml.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_armv81mml.h similarity index 98% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_armv81mml.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_armv81mml.h index 8cee9306..8441e57f 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_armv81mml.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_armv81mml.h @@ -1,2968 +1,2968 @@ -/**************************************************************************//** - * @file core_armv81mml.h - * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File - * @version V1.0.0 - * @date 15. March 2019 - ******************************************************************************/ -/* - * Copyright (c) 2018-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_ARMV81MML_H_GENERIC -#define __CORE_ARMV81MML_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMV81MML - @{ - */ - -#include "cmsis_version.h" - -#define __ARM_ARCH_8M_MAIN__ 1 // patching for now -/* CMSIS ARMV81MML definitions */ -#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (81U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV81MML_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV81MML_H_DEPENDANT -#define __CORE_ARMV81MML_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __ARMv81MML_REV - #define __ARMv81MML_REV 0x0000U - #warning "__ARMv81MML_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv81MML */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ -#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV81MML_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +#define __ARM_ARCH_8M_MAIN__ 1 // patching for now +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_armv8mbl.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_armv8mbl.h similarity index 98% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_armv8mbl.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_armv8mbl.h index 266f180a..344dca51 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_armv8mbl.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_armv8mbl.h @@ -1,1921 +1,1921 @@ -/**************************************************************************//** - * @file core_armv8mbl.h - * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File - * @version V5.0.8 - * @date 12. November 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_ARMV8MBL_H_GENERIC -#define __CORE_ARMV8MBL_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MBL - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS definitions */ -#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MBL_H_DEPENDANT -#define __CORE_ARMV8MBL_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __ARMv8MBL_REV - #define __ARMv8MBL_REV 0x0000U - #warning "__ARMv8MBL_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif - - #ifndef __ETM_PRESENT - #define __ETM_PRESENT 0U - #warning "__ETM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MTB_PRESENT - #define __MTB_PRESENT 0U - #warning "__MTB_PRESENT not defined in device header file; using default!" - #endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MBL */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[809U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ - uint32_t RESERVED4[4U]; - __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI Periodic Synchronization Control Register Definitions */ -#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ -#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ - -/* TPI Software Lock Status Register Definitions */ -#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ -#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ - -#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ -#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ - -#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ -#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_armv8mml.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_armv8mml.h similarity index 98% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_armv8mml.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_armv8mml.h index ba5d83ff..5ddb8aed 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_armv8mml.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_armv8mml.h @@ -1,2835 +1,2835 @@ -/**************************************************************************//** - * @file core_armv8mml.h - * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File - * @version V5.1.0 - * @date 12. September 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_ARMV8MML_H_GENERIC -#define __CORE_ARMV8MML_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MML - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS Armv8MML definitions */ -#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (81U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MML_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MML_H_DEPENDANT -#define __CORE_ARMV8MML_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __ARMv8MML_REV - #define __ARMv8MML_REV 0x0000U - #warning "__ARMv8MML_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MML */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[809U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ - uint32_t RESERVED4[4U]; - __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI Periodic Synchronization Control Register Definitions */ -#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ -#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ - -/* TPI Software Lock Status Register Definitions */ -#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ -#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ - -#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ -#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ - -#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ -#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MML_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. September 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm0.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm0.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm0.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm0.h index 70e45053..cafae5a0 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm0.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm0.h @@ -1,952 +1,952 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V5.0.6 - * @date 13. March 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M0 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000U - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - Address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t vectors = 0x0U; - (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; - /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t vectors = 0x0U; - return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm0plus.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm0plus.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm0plus.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm0plus.h index fe7b424e..d104965d 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm0plus.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm0plus.h @@ -1,1085 +1,1085 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V5.0.7 - * @date 13. March 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex-M0+ - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000U - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0+ header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t vectors = SCB->VTOR; -#else - uint32_t vectors = 0x0U; -#endif - (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; - /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t vectors = SCB->VTOR; -#else - uint32_t vectors = 0x0U; -#endif - return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm1.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm1.h new file mode 100644 index 00000000..76b45697 --- /dev/null +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm23.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm23.h similarity index 98% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm23.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm23.h index 49f4a5b0..b79c6af0 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm23.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm23.h @@ -1,1996 +1,1996 @@ -/**************************************************************************//** - * @file core_cm23.h - * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File - * @version V5.0.8 - * @date 12. November 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM23_H_GENERIC -#define __CORE_CM23_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M23 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS definitions */ -#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ - __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (23U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM23_H_DEPENDANT -#define __CORE_CM23_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM23_REV - #define __CM23_REV 0x0000U - #warning "__CM23_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif - - #ifndef __ETM_PRESENT - #define __ETM_PRESENT 0U - #warning "__ETM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MTB_PRESENT - #define __MTB_PRESENT 0U - #warning "__MTB_PRESENT not defined in device header file; using default!" - #endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M23 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ - __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ - __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration Test FIFO Test Data 0 Register Definitions */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ -#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ -#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ -#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ - -/* TPI Integration Test ATB Control Register 2 Register Definitions */ -#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ -#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ - -#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ -#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ - -#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ -#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ - -#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ -#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ - -/* TPI Integration Test FIFO Test Data 1 Register Definitions */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ -#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ -#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ -#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ - -/* TPI Integration Test ATB Control Register 0 Definitions */ -#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ -#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ - -#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ -#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ - -#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ -#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ - -#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ -#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm3.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm3.h similarity index 98% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm3.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm3.h index 1f69e8bd..8157ca78 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm3.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm3.h @@ -1,1937 +1,1937 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V5.1.0 - * @date 13. March 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M3 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (3U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200U - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1U]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ -#endif - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ -#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ - -#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ -#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ -#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ - -#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ -#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t vectors = (uint32_t )SCB->VTOR; - (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; - /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t vectors = (uint32_t )SCB->VTOR; - return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm33.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm33.h similarity index 98% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm33.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm33.h index 2f1d98e2..7fed59a8 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm33.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm33.h @@ -1,2910 +1,2910 @@ -/**************************************************************************//** - * @file core_cm33.h - * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File - * @version V5.1.0 - * @date 12. November 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM33_H_GENERIC -#define __CORE_CM33_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M33 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM33 definitions */ -#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ - __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (33U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined (__TARGET_FPU_VFP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined (__ARM_FP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined (__ARMVFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined (__TI_VFP_SUPPORT__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined (__FPU_VFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM33_H_DEPENDANT -#define __CORE_CM33_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM33_REV - #define __CM33_REV 0x0000U - #warning "__CM33_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M33 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ - __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ - __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration Test FIFO Test Data 0 Register Definitions */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ -#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ -#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ -#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ - -/* TPI Integration Test ATB Control Register 2 Register Definitions */ -#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ -#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ - -#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ -#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ - -#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ -#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ - -#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ -#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ - -/* TPI Integration Test FIFO Test Data 1 Register Definitions */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ -#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ -#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ -#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ - -/* TPI Integration Test ATB Control Register 0 Definitions */ -#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ -#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ - -#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ -#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ - -#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ -#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ - -#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ -#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm35p.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm35p.h similarity index 98% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm35p.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm35p.h index 7d343679..5579c823 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm35p.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm35p.h @@ -1,2910 +1,2910 @@ -/**************************************************************************//** - * @file core_cm35p.h - * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File - * @version V1.0.0 - * @date 12. November 2018 - ******************************************************************************/ -/* - * Copyright (c) 2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM35P_H_GENERIC -#define __CORE_CM35P_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M35P - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM35P definitions */ -#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ - __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (35U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined (__TARGET_FPU_VFP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined (__ARM_FP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined (__ARMVFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined (__TI_VFP_SUPPORT__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined (__FPU_VFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM35P_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM35P_H_DEPENDANT -#define __CORE_CM35P_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM35P_REV - #define __CM35P_REV 0x0000U - #warning "__CM35P_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M35P */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ - __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ - __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration Test FIFO Test Data 0 Register Definitions */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ -#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ -#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ -#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ - -/* TPI Integration Test ATB Control Register 2 Register Definitions */ -#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ -#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ - -#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ -#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ - -#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ -#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ - -#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ -#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ - -/* TPI Integration Test FIFO Test Data 1 Register Definitions */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ -#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ -#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ -#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ - -/* TPI Integration Test ATB Control Register 0 Definitions */ -#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ -#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ - -#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ -#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ - -#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ -#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ - -#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ -#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM35P_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm4.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm4.h similarity index 98% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm4.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm4.h index 90c2a72d..12c023b8 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm4.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm4.h @@ -1,2124 +1,2124 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V5.1.0 - * @date 13. March 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M4 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (4U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000U - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ -#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ - -#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ -#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ -#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ - -#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ -#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 Definitions */ - -#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ -#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ -#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ -#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ -#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t vectors = (uint32_t )SCB->VTOR; - (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; - /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t vectors = (uint32_t )SCB->VTOR; - return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm7.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm7.h similarity index 98% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm7.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm7.h index 3da3c43e..c4515d8f 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_cm7.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_cm7.h @@ -1,2725 +1,2725 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V5.1.1 - * @date 28. March 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M7 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (7U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000U - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0U - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1U]; - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ -#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ - -#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ -#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ - -#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ -#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ - -#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ -#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ - -#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ -#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ - -#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ -#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ - -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ -#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ - -#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ -#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ -#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ - -#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ -#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 Definitions */ - -#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ -#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ -#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ -#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ -#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t vectors = (uint32_t )SCB->VTOR; - (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t vectors = (uint32_t )SCB->VTOR; - return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = SCB->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## Cache functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - -#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ -#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_FORCEINLINE void SCB_EnableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ - - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_FORCEINLINE void SCB_DisableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_FORCEINLINE void SCB_InvalidateICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief I-Cache Invalidate by address - \details Invalidates I-Cache for the given address. - I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. - I-Cache memory blocks which are part of given address + given size are invalidated. - \param[in] addr address - \param[in] isize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - if ( isize > 0 ) { - int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_ICACHE_LINE_SIZE; - op_size -= __SCB_ICACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_FORCEINLINE void SCB_EnableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_FORCEINLINE void SCB_DisableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_FORCEINLINE void SCB_CleanDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address. - D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are invalidated. - \param[in] addr address - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are cleaned. - \param[in] addr address - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - -/*@} end of CMSIS_Core_CacheFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 28. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_sc000.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_sc000.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_sc000.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_sc000.h index f315013b..cf92577b 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_sc000.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_sc000.h @@ -1,1025 +1,1025 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V5.0.6 - * @date 12. November 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC000 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_SC (000U) /*!< Cortex secure core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000U - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the SC000 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_sc300.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_sc300.h similarity index 98% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_sc300.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_sc300.h index ad031f23..40f3af81 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/core_sc300.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/core_sc300.h @@ -1,1912 +1,1912 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V5.0.8 - * @date 31. May 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC3000 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_SC (300U) /*!< Cortex secure core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000U - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED1[129U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ -#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ - -#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ -#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ -#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ - -#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ -#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t vectors = (uint32_t )SCB->VTOR; - (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; - /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t vectors = (uint32_t )SCB->VTOR; - return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 31. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/mpu_armv7.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/mpu_armv7.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/mpu_armv7.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/mpu_armv7.h index 337eb655..66ef59b4 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/mpu_armv7.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/mpu_armv7.h @@ -1,272 +1,272 @@ -/****************************************************************************** - * @file mpu_armv7.h - * @brief CMSIS MPU API for Armv7-M MPU - * @version V5.1.0 - * @date 08. March 2019 - ******************************************************************************/ -/* - * Copyright (c) 2017-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_MPU_ARMV7_H -#define ARM_MPU_ARMV7_H - -#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes -#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes -#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes -#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes -#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes -#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte -#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes -#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes -#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes -#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes -#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes -#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes -#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes -#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes -#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes -#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte -#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes -#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes -#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes -#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes -#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes -#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes -#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes -#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes -#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes -#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte -#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes -#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes - -#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access -#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only -#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only -#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access -#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only -#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access - -/** MPU Region Base Address Register Value -* -* \param Region The region to be configured, number 0 to 15. -* \param BaseAddress The base address for the region. -*/ -#define ARM_MPU_RBAR(Region, BaseAddress) \ - (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ - ((Region) & MPU_RBAR_REGION_Msk) | \ - (MPU_RBAR_VALID_Msk)) - -/** -* MPU Memory Access Attributes -* -* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. -* \param IsShareable Region is shareable between multiple bus masters. -* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. -* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -*/ -#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ - ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ - (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ - (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ - (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) - -/** -* MPU Region Attribute and Size Register Value -* -* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. -* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. -* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. -* \param SubRegionDisable Sub-region disable field. -* \param Size Region size of the region to be configured, for example 4K, 8K. -*/ -#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ - ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ - (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ - (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ - (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ - (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ - (((MPU_RASR_ENABLE_Msk)))) - -/** -* MPU Region Attribute and Size Register Value -* -* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. -* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. -* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. -* \param IsShareable Region is shareable between multiple bus masters. -* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. -* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -* \param SubRegionDisable Sub-region disable field. -* \param Size Region size of the region to be configured, for example 4K, 8K. -*/ -#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ - ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) - -/** -* MPU Memory Access Attribute for strongly ordered memory. -* - TEX: 000b -* - Shareable -* - Non-cacheable -* - Non-bufferable -*/ -#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) - -/** -* MPU Memory Access Attribute for device memory. -* - TEX: 000b (if shareable) or 010b (if non-shareable) -* - Shareable or non-shareable -* - Non-cacheable -* - Bufferable (if shareable) or non-bufferable (if non-shareable) -* -* \param IsShareable Configures the device memory as shareable or non-shareable. -*/ -#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) - -/** -* MPU Memory Access Attribute for normal memory. -* - TEX: 1BBb (reflecting outer cacheability rules) -* - Shareable or non-shareable -* - Cacheable or non-cacheable (reflecting inner cacheability rules) -* - Bufferable or non-bufferable (reflecting inner cacheability rules) -* -* \param OuterCp Configures the outer cache policy. -* \param InnerCp Configures the inner cache policy. -* \param IsShareable Configures the memory as shareable or non-shareable. -*/ -#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) - -/** -* MPU Memory Access Attribute non-cacheable policy. -*/ -#define ARM_MPU_CACHEP_NOCACHE 0U - -/** -* MPU Memory Access Attribute write-back, write and read allocate policy. -*/ -#define ARM_MPU_CACHEP_WB_WRA 1U - -/** -* MPU Memory Access Attribute write-through, no write allocate policy. -*/ -#define ARM_MPU_CACHEP_WT_NWA 2U - -/** -* MPU Memory Access Attribute write-back, no write allocate policy. -*/ -#define ARM_MPU_CACHEP_WB_NWA 3U - - -/** -* Struct for a single MPU Region -*/ -typedef struct { - uint32_t RBAR; //!< The region base address register value (RBAR) - uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR -} ARM_MPU_Region_t; - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - MPU->RNR = rnr; - MPU->RASR = 0U; -} - -/** Configure an MPU region. -* \param rbar Value for RBAR register. -* \param rsar Value for RSAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) -{ - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rsar Value for RSAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) -{ - MPU->RNR = rnr; - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Memcopy with strictly ordered memory access, e.g. for register targets. -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0U; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) -{ - const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - while (cnt > MPU_TYPE_RALIASES) { - ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); - table += MPU_TYPE_RALIASES; - cnt -= MPU_TYPE_RALIASES; - } - ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); -} - -#endif +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/mpu_armv8.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/mpu_armv8.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/mpu_armv8.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/mpu_armv8.h index 2fe28b68..0041d4dc 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Include/mpu_armv8.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/mpu_armv8.h @@ -1,346 +1,346 @@ -/****************************************************************************** - * @file mpu_armv8.h - * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU - * @version V5.1.0 - * @date 08. March 2019 - ******************************************************************************/ -/* - * Copyright (c) 2017-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_MPU_ARMV8_H -#define ARM_MPU_ARMV8_H - -/** \brief Attribute for device memory (outer only) */ -#define ARM_MPU_ATTR_DEVICE ( 0U ) - -/** \brief Attribute for non-cacheable, normal memory */ -#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) - -/** \brief Attribute for normal memory (outer and inner) -* \param NT Non-Transient: Set to 1 for non-transient data. -* \param WB Write-Back: Set to 1 to use write-back update policy. -* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. -* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. -*/ -#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ - (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) - -/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) - -/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) - -/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGRE (2U) - -/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_GRE (3U) - -/** \brief Memory Attribute -* \param O Outer memory attributes -* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes -*/ -#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) - -/** \brief Normal memory non-shareable */ -#define ARM_MPU_SH_NON (0U) - -/** \brief Normal memory outer shareable */ -#define ARM_MPU_SH_OUTER (2U) - -/** \brief Normal memory inner shareable */ -#define ARM_MPU_SH_INNER (3U) - -/** \brief Memory access permissions -* \param RO Read-Only: Set to 1 for read-only memory. -* \param NP Non-Privileged: Set to 1 for non-privileged memory. -*/ -#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) - -/** \brief Region Base Address Register value -* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. -* \param SH Defines the Shareability domain for this memory region. -* \param RO Read-Only: Set to 1 for a read-only memory region. -* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. -* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. -*/ -#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ - ((BASE & MPU_RBAR_BASE_Msk) | \ - ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ - ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ - ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) - -/** \brief Region Limit Address Register value -* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -* \param IDX The attribute index to be associated with this memory region. -*/ -#define ARM_MPU_RLAR(LIMIT, IDX) \ - ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ - ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ - (MPU_RLAR_EN_Msk)) - -#if defined(MPU_RLAR_PXN_Pos) - -/** \brief Region Limit Address Register with PXN value -* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. -* \param IDX The attribute index to be associated with this memory region. -*/ -#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ - ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ - ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ - ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ - (MPU_RLAR_EN_Msk)) - -#endif - -/** -* Struct for a single MPU Region -*/ -typedef struct { - uint32_t RBAR; /*!< Region Base Address Register value */ - uint32_t RLAR; /*!< Region Limit Address Register value */ -} ARM_MPU_Region_t; - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; -} - -#ifdef MPU_NS -/** Enable the Non-secure MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) -{ - MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the Non-secure MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable_NS(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; -} -#endif - -/** Set the memory attribute encoding to the given MPU. -* \param mpu Pointer to the MPU to be configured. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) -{ - const uint8_t reg = idx / 4U; - const uint32_t pos = ((idx % 4U) * 8U); - const uint32_t mask = 0xFFU << pos; - - if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { - return; // invalid index - } - - mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); -} - -/** Set the memory attribute encoding. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU, idx, attr); -} - -#ifdef MPU_NS -/** Set the memory attribute encoding to the Non-secure MPU. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); -} -#endif - -/** Clear and disable the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) -{ - mpu->RNR = rnr; - mpu->RLAR = 0U; -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU, rnr); -} - -#ifdef MPU_NS -/** Clear and disable the given Non-secure MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU_NS, rnr); -} -#endif - -/** Configure the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - mpu->RNR = rnr; - mpu->RBAR = rbar; - mpu->RLAR = rlar; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); -} - -#ifdef MPU_NS -/** Configure the given Non-secure MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); -} -#endif - -/** Memcopy with strictly ordered memory access, e.g. for register targets. -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0U; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table to the given MPU. -* \param mpu Pointer to the MPU registers to be used. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - if (cnt == 1U) { - mpu->RNR = rnr; - ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); - } else { - uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); - uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; - - mpu->RNR = rnrBase; - while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { - uint32_t c = MPU_TYPE_RALIASES - rnrOffset; - ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); - table += c; - cnt -= c; - rnrOffset = 0U; - rnrBase += MPU_TYPE_RALIASES; - mpu->RNR = rnrBase; - } - - ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); - } -} - -/** Load the given number of MPU regions from a table. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU, rnr, table, cnt); -} - -#ifdef MPU_NS -/** Load the given number of MPU regions from a table to the Non-secure MPU. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); -} -#endif - -#endif - +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/tz_context.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/tz_context.h new file mode 100644 index 00000000..0d09749f --- /dev/null +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/LICENSE.txt b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/LICENSE.txt similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/LICENSE.txt rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/LICENSE.txt diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Lib/ARM/arm_cortexM4b_math.lib b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Lib/ARM/arm_cortexM4b_math.lib similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Lib/ARM/arm_cortexM4b_math.lib rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Lib/ARM/arm_cortexM4b_math.lib diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Lib/ARM/arm_cortexM4bf_math.lib b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Lib/ARM/arm_cortexM4bf_math.lib similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Lib/ARM/arm_cortexM4bf_math.lib rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Lib/ARM/arm_cortexM4bf_math.lib diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Lib/ARM/arm_cortexM4l_math.lib b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Lib/ARM/arm_cortexM4l_math.lib similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Lib/ARM/arm_cortexM4l_math.lib rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Lib/ARM/arm_cortexM4l_math.lib diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Lib/ARM/arm_cortexM4lf_math.lib b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/CMSIS/Lib/ARM/arm_cortexM4lf_math.lib similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/CMSIS/Lib/ARM/arm_cortexM4lf_math.lib rename to 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b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h rename to 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b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h rename to 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b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h rename to 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****************************************************************************** + * @file stm32l4xx_ll_tim.h + * @author MCD Application Team + * @brief Header file of TIM LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_LL_TIM_H +#define __STM32L4xx_LL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx.h" + +/** @addtogroup STM32L4xx_LL_Driver + * @{ + */ + +#if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7) + +/** @defgroup TIM_LL TIM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Variables TIM Private Variables + * @{ + */ +static const uint8_t OFFSET_TAB_CCMRx[] = +{ + 0x00U, /* 0: TIMx_CH1 */ + 0x00U, /* 1: TIMx_CH1N */ + 0x00U, /* 2: TIMx_CH2 */ + 0x00U, /* 3: TIMx_CH2N */ + 0x04U, /* 4: TIMx_CH3 */ + 0x04U, /* 5: TIMx_CH3N */ + 0x04U, /* 6: TIMx_CH4 */ + 0x3CU, /* 7: TIMx_CH5 */ + 0x3CU /* 8: TIMx_CH6 */ +}; + +static const uint8_t SHIFT_TAB_OCxx[] = +{ + 0U, /* 0: OC1M, OC1FE, OC1PE */ + 0U, /* 1: - NA */ + 8U, /* 2: OC2M, OC2FE, OC2PE */ + 0U, /* 3: - NA */ + 0U, /* 4: OC3M, OC3FE, OC3PE */ + 0U, /* 5: - NA */ + 8U, /* 6: OC4M, OC4FE, OC4PE */ + 0U, /* 7: OC5M, OC5FE, OC5PE */ + 8U /* 8: OC6M, OC6FE, OC6PE */ +}; + +static const uint8_t SHIFT_TAB_ICxx[] = +{ + 0U, /* 0: CC1S, IC1PSC, IC1F */ + 0U, /* 1: - NA */ + 8U, /* 2: CC2S, IC2PSC, IC2F */ + 0U, /* 3: - NA */ + 0U, /* 4: CC3S, IC3PSC, IC3F */ + 0U, /* 5: - NA */ + 8U, /* 6: CC4S, IC4PSC, IC4F */ + 0U, /* 7: - NA */ + 0U /* 8: - NA */ +}; + +static const uint8_t SHIFT_TAB_CCxP[] = +{ + 0U, /* 0: CC1P */ + 2U, /* 1: CC1NP */ + 4U, /* 2: CC2P */ + 6U, /* 3: CC2NP */ + 8U, /* 4: CC3P */ + 10U, /* 5: CC3NP */ + 12U, /* 6: CC4P */ + 16U, /* 7: CC5P */ + 20U /* 8: CC6P */ +}; + +static const uint8_t SHIFT_TAB_OISx[] = +{ + 0U, /* 0: OIS1 */ + 1U, /* 1: OIS1N */ + 2U, /* 2: OIS2 */ + 3U, /* 3: OIS2N */ + 4U, /* 4: OIS3 */ + 5U, /* 5: OIS3N */ + 6U, /* 6: OIS4 */ + 8U, /* 7: OIS5 */ + 10U /* 8: OIS6 */ +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Constants TIM Private Constants + * @{ + */ + +/* Defines used for the bit position in the register and perform offsets */ +#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) + +/* Generic bit definitions for TIMx_OR2 register */ +#define TIMx_OR2_BKINP TIM1_OR2_BKINP /*!< BRK BKIN input polarity */ +#define TIMx_OR2_ETRSEL TIM1_OR2_ETRSEL /*!< TIMx ETR source selection */ + +/* Remap mask definitions */ +#define TIMx_OR1_RMP_SHIFT 16U +#define TIMx_OR1_RMP_MASK 0x0000FFFFU +#if defined(ADC3) +#define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT) +#else +#define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT) +#endif /* ADC3 */ +#define TIM2_OR1_RMP_MASK ((TIM2_OR1_TI4_RMP | TIM2_OR1_ETR1_RMP | TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT) +#define TIM3_OR1_RMP_MASK (TIM3_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) +#if defined(ADC2) && defined(ADC3) +#define TIM8_OR1_RMP_MASK ((TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT) +#else +#define TIM8_OR1_RMP_MASK (TIM8_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) +#endif /* ADC2 & ADC3 */ +#define TIM15_OR1_RMP_MASK (TIM15_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) +#define TIM16_OR1_RMP_MASK (TIM16_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) +#define TIM17_OR1_RMP_MASK (TIM17_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) + +/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ +#define DT_DELAY_1 ((uint8_t)0x7F) +#define DT_DELAY_2 ((uint8_t)0x3F) +#define DT_DELAY_3 ((uint8_t)0x1F) +#define DT_DELAY_4 ((uint8_t)0x1F) + +/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ +#define DT_RANGE_1 ((uint8_t)0x00) +#define DT_RANGE_2 ((uint8_t)0x80) +#define DT_RANGE_3 ((uint8_t)0xC0) +#define DT_RANGE_4 ((uint8_t)0xE0) + +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#if defined(DFSDM1_Channel0) +#define TIMx_OR2_BKDFBK0E TIMx_OR2_BKDF1BK0E +#define TIMx_OR3_BK2DFBK1E TIMx_OR3_BK2DF1BK1E +#endif /* DFSDM1_Channel0 */ +/** +@endcond + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Macros TIM Private Macros + * @{ + */ +/** @brief Convert channel id into channel index. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval none + */ +#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ + (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) + +/** @brief Calculate the deadtime sampling period(in ps). + * @param __TIMCLK__ timer input clock frequency (in Hz). + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval none + */ +#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ + (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ + ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ + ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure + * @{ + */ + +/** + * @brief TIM Time Base configuration structure definition. + */ +typedef struct +{ + uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetPrescaler().*/ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetCounterMode().*/ + + uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + Some timer instances may support 32 bits counters. In that case this parameter must + be a number between 0x0000 and 0xFFFFFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetAutoReload().*/ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetClockDivision().*/ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetRepetitionCounter().*/ +} LL_TIM_InitTypeDef; + +/** + * @brief TIM Output Compare configuration structure definition. + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the output mode. + This parameter can be a value of @ref TIM_LL_EC_OCMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetMode().*/ + + uint32_t OCState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function + LL_TIM_OC_SetCompareCHx (x=1..6).*/ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ +} LL_TIM_OC_InitTypeDef; + +/** + * @brief TIM Input Capture configuration structure definition. + */ + +typedef struct +{ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t ICActiveInput; /*!< Specifies the input. + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ +} LL_TIM_IC_InitTypeDef; + + +/** + * @brief TIM Encoder interface configuration structure definition. + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). + This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetEncoderMode().*/ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + + uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC2Filter; /*!< Specifies the TI2 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + +} LL_TIM_ENCODER_InitTypeDef; + +/** + * @brief TIM Hall sensor interface configuration structure definition. + */ +typedef struct +{ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + Prescaler must be set to get a maximum counter period longer than the + time interval between 2 consecutive changes on the Hall inputs. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of + @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + + uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. + A positive pulse (TRGO event) is generated with a programmable delay every time + a change occurs on the Hall inputs. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetCompareCH2().*/ +} LL_TIM_HALLSENSOR_InitTypeDef; + +/** + * @brief BDTR (Break and Dead Time) structure definition + */ +typedef struct +{ + uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_LL_EC_OSSR + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ + + uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_LL_EC_OSSI + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ + + uint32_t LockLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL + + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR + register has been written, their content is frozen until the next reset.*/ + + uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetDeadTime() + + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been + programmed. */ + + uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. + This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ +} LL_TIM_BDTR_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_TIM_ReadReg function. + * @{ + */ +#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ +#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ +#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ +#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ +#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ +#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */ +#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */ +#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ +#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ +#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ +#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */ +#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ +#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ +#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ +#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ +#define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable + * @{ + */ +#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ +#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable + * @{ + */ +#define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ +#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable + * @{ + */ +#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup TIM_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. + * @{ + */ +#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ +#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ +#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ +#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ +#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ +#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ +#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ +#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source + * @{ + */ +#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ +#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode + * @{ + */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode + * @{ + */ +#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */ +#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ +#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ +#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ +#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division + * @{ + */ +#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ +#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ +#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction + * @{ + */ +#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ +#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source + * @{ + */ +#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */ +#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request + * @{ + */ +#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ +#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level + * @{ + */ +#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */ +#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CHANNEL Channel + * @{ + */ +#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ +#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ +#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ +#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ +#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ +#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ +#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ +#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ +#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State + * @{ + */ +#define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ +#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1 +#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2 +/** +@endcond + */ + +/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode + * @{ + */ +#define LL_TIM_OCMODE_FROZEN 0x00000000U /*!TIMx_CCRy else active.*/ +#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/ +#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!__REG__, (__VALUE__)) + +/** + * @brief Read a value in TIM register. + * @param __INSTANCE__ TIM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) +/** + * @} + */ + +/** + * @brief HELPER macro retrieving the UIFCPY flag from the counter value. + * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); + * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied + * to TIMx_CNT register bit 31) + * @param __CNT__ Counter value + * @retval UIF status bit + */ +#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ + (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) + +/** + * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. + * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @param __DT__ deadtime duration (in ns) + * @retval DTG[0:7] + */ +#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ + ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ + (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ + 0U) + +/** + * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. + * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CNTCLK__ counter clock frequency (in Hz) + * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ + (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. + * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __FREQ__ output signal frequency (in Hz) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ + ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the compare value required to achieve the required timer output compare + * active/inactive delay. + * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @retval Compare value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ + ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration + * (when the timer operates in one pulse mode). + * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @param __PULSE__ pulse duration (in us) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ + ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) + +/** + * @brief HELPER macro retrieving the ratio of the input capture prescaler + * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); + * @param __ICPSC__ This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval Input capture prescaler ratio (1, 2, 4 or 8) + */ +#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ + ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_LL_EF_Time_Base Time Base configuration + * @{ + */ +/** + * @brief Enable timer counter. + * @rmtoll CR1 CEN LL_TIM_EnableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Disable timer counter. + * @rmtoll CR1 CEN LL_TIM_DisableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Indicates whether the timer counter is enabled. + * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable update event generation. + * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Disable update event generation. + * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Indicates whether update event generation is enabled. + * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent + * @param TIMx Timer instance + * @retval Inverted state of bit (0 or 1). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); +} + +/** + * @brief Set update event source + * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events + * generate an update interrupt or DMA request if enabled: + * - Counter overflow/underflow + * - Setting the UG bit + * - Update generation through the slave mode controller + * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter + * overflow/underflow generates an update interrupt or DMA request if enabled. + * @rmtoll CR1 URS LL_TIM_SetUpdateSource + * @param TIMx Timer instance + * @param UpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); +} + +/** + * @brief Get actual event update source + * @rmtoll CR1 URS LL_TIM_GetUpdateSource + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + */ +__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); +} + +/** + * @brief Set one pulse mode (one shot v.s. repetitive). + * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode + * @param TIMx Timer instance + * @param OnePulseMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); +} + +/** + * @brief Get actual one pulse mode. + * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + */ +__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); +} + +/** + * @brief Set the timer counter counting mode. + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n + * CR1 CMS LL_TIM_SetCounterMode + * @param TIMx Timer instance + * @param CounterMode This parameter can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) +{ + MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); +} + +/** + * @brief Get actual counter mode. + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n + * CR1 CMS LL_TIM_GetCounterMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) +{ + uint32_t counter_mode; + + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); + + if (counter_mode == 0U) + { + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); + } + + return counter_mode; +} + +/** + * @brief Enable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Disable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Indicates whether auto-reload (ARR) preload is enabled. + * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); +} + +/** + * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators + * (when supported) and the digital filters. + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_SetClockDivision + * @param TIMx Timer instance + * @param ClockDivision This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); +} + +/** + * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time + * generators (when supported) and the digital filters. + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_GetClockDivision + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + */ +__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); +} + +/** + * @brief Set the counter value. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @rmtoll CNT CNT LL_TIM_SetCounter + * @param TIMx Timer instance + * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) +{ + WRITE_REG(TIMx->CNT, Counter); +} + +/** + * @brief Get the counter value. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @rmtoll CNT CNT LL_TIM_GetCounter + * @param TIMx Timer instance + * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CNT)); +} + +/** + * @brief Get the current direction of the counter + * @rmtoll CR1 DIR LL_TIM_GetDirection + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERDIRECTION_UP + * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); +} + +/** + * @brief Set the prescaler value. + * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). + * @note The prescaler can be changed on the fly as this control register is buffered. The new + * prescaler ratio is taken into account at the next update event. + * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter + * @rmtoll PSC PSC LL_TIM_SetPrescaler + * @param TIMx Timer instance + * @param Prescaler between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) +{ + WRITE_REG(TIMx->PSC, Prescaler); +} + +/** + * @brief Get the prescaler value. + * @rmtoll PSC PSC LL_TIM_GetPrescaler + * @param TIMx Timer instance + * @retval Prescaler value between Min_Data=0 and Max_Data=65535 + */ +__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->PSC)); +} + +/** + * @brief Set the auto-reload value. + * @note The counter is blocked while the auto-reload value is null. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter + * @rmtoll ARR ARR LL_TIM_SetAutoReload + * @param TIMx Timer instance + * @param AutoReload between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) +{ + WRITE_REG(TIMx->ARR, AutoReload); +} + +/** + * @brief Get the auto-reload value. + * @rmtoll ARR ARR LL_TIM_GetAutoReload + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @param TIMx Timer instance + * @retval Auto-reload value + */ +__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->ARR)); +} + +/** + * @brief Set the repetition counter value. + * @note For advanced timer instances RepetitionCounter can be up to 65535. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_SetRepetitionCounter + * @param TIMx Timer instance + * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) +{ + WRITE_REG(TIMx->RCR, RepetitionCounter); +} + +/** + * @brief Get the repetition counter value. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_GetRepetitionCounter + * @param TIMx Timer instance + * @retval Repetition counter value + */ +__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->RCR)); +} + +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. + * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); +} + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); +} + +/** + * @brief Indicate whether update interrupt flag (UIF) copy is set. + * @param Counter Counter value + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter) +{ + return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration + * @{ + */ +/** + * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, + * they are updated only when a commutation event (COM) occurs. + * @note Only on channels that have a complementary output. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled. + * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); +} + +/** + * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate + * @param TIMx Timer instance + * @param CCUpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); +} + +/** + * @brief Set the trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger + * @param TIMx Timer instance + * @param DMAReqTrigger This parameter can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); +} + +/** + * @brief Get actual trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + */ +__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); +} + +/** + * @brief Set the lock level to freeze the + * configuration of several capture/compare parameters. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * the lock mechanism is supported by a timer instance. + * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel + * @param TIMx Timer instance + * @param LockLevel This parameter can be one of the following values: + * @arg @ref LL_TIM_LOCKLEVEL_OFF + * @arg @ref LL_TIM_LOCKLEVEL_1 + * @arg @ref LL_TIM_LOCKLEVEL_2 + * @arg @ref LL_TIM_LOCKLEVEL_3 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); +} + +/** + * @brief Enable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n + * CCER CC1NE LL_TIM_CC_EnableChannel\n + * CCER CC2E LL_TIM_CC_EnableChannel\n + * CCER CC2NE LL_TIM_CC_EnableChannel\n + * CCER CC3E LL_TIM_CC_EnableChannel\n + * CCER CC3NE LL_TIM_CC_EnableChannel\n + * CCER CC4E LL_TIM_CC_EnableChannel\n + * CCER CC5E LL_TIM_CC_EnableChannel\n + * CCER CC6E LL_TIM_CC_EnableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + SET_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Disable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n + * CCER CC1NE LL_TIM_CC_DisableChannel\n + * CCER CC2E LL_TIM_CC_DisableChannel\n + * CCER CC2NE LL_TIM_CC_DisableChannel\n + * CCER CC3E LL_TIM_CC_DisableChannel\n + * CCER CC3NE LL_TIM_CC_DisableChannel\n + * CCER CC4E LL_TIM_CC_DisableChannel\n + * CCER CC5E LL_TIM_CC_DisableChannel\n + * CCER CC6E LL_TIM_CC_DisableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + CLEAR_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Indicate whether channel(s) is(are) enabled. + * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n + * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC2E LL_TIM_CC_IsEnabledChannel\n + * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC3E LL_TIM_CC_IsEnabledChannel\n + * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC4E LL_TIM_CC_IsEnabledChannel\n + * CCER CC5E LL_TIM_CC_IsEnabledChannel\n + * CCER CC6E LL_TIM_CC_IsEnabledChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) +{ + return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration + * @{ + */ +/** + * @brief Configure an output channel. + * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n + * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n + * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n + * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n + * CCER CC1P LL_TIM_OC_ConfigOutput\n + * CCER CC2P LL_TIM_OC_ConfigOutput\n + * CCER CC3P LL_TIM_OC_ConfigOutput\n + * CCER CC4P LL_TIM_OC_ConfigOutput\n + * CCER CC5P LL_TIM_OC_ConfigOutput\n + * CCER CC6P LL_TIM_OC_ConfigOutput\n + * CR2 OIS1 LL_TIM_OC_ConfigOutput\n + * CR2 OIS2 LL_TIM_OC_ConfigOutput\n + * CR2 OIS3 LL_TIM_OC_ConfigOutput\n + * CR2 OIS4 LL_TIM_OC_ConfigOutput\n + * CR2 OIS5 LL_TIM_OC_ConfigOutput\n + * CR2 OIS6 LL_TIM_OC_ConfigOutput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW + * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), + (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), + (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Define the behavior of the output reference signal OCxREF from which + * OCx and OCxN (when relevant) are derived. + * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n + * CCMR1 OC2M LL_TIM_OC_SetMode\n + * CCMR2 OC3M LL_TIM_OC_SetMode\n + * CCMR2 OC4M LL_TIM_OC_SetMode\n + * CCMR3 OC5M LL_TIM_OC_SetMode\n + * CCMR3 OC6M LL_TIM_OC_SetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Get the output compare mode of an output channel. + * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n + * CCMR1 OC2M LL_TIM_OC_GetMode\n + * CCMR2 OC3M LL_TIM_OC_GetMode\n + * CCMR2 OC4M LL_TIM_OC_GetMode\n + * CCMR3 OC5M LL_TIM_OC_GetMode\n + * CCMR3 OC6M LL_TIM_OC_GetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Set the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n + * CCER CC1NP LL_TIM_OC_SetPolarity\n + * CCER CC2P LL_TIM_OC_SetPolarity\n + * CCER CC2NP LL_TIM_OC_SetPolarity\n + * CCER CC3P LL_TIM_OC_SetPolarity\n + * CCER CC3NP LL_TIM_OC_SetPolarity\n + * CCER CC4P LL_TIM_OC_SetPolarity\n + * CCER CC5P LL_TIM_OC_SetPolarity\n + * CCER CC6P LL_TIM_OC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n + * CCER CC1NP LL_TIM_OC_GetPolarity\n + * CCER CC2P LL_TIM_OC_GetPolarity\n + * CCER CC2NP LL_TIM_OC_GetPolarity\n + * CCER CC3P LL_TIM_OC_GetPolarity\n + * CCER CC3NP LL_TIM_OC_GetPolarity\n + * CCER CC4P LL_TIM_OC_GetPolarity\n + * CCER CC5P LL_TIM_OC_GetPolarity\n + * CCER CC6P LL_TIM_OC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the IDLE state of an output channel + * @note This function is significant only for the timer instances + * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) + * can be used to check whether or not a timer instance provides + * a break input. + * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n + * CR2 OIS2N LL_TIM_OC_SetIdleState\n + * CR2 OIS2 LL_TIM_OC_SetIdleState\n + * CR2 OIS2N LL_TIM_OC_SetIdleState\n + * CR2 OIS3 LL_TIM_OC_SetIdleState\n + * CR2 OIS3N LL_TIM_OC_SetIdleState\n + * CR2 OIS4 LL_TIM_OC_SetIdleState\n + * CR2 OIS5 LL_TIM_OC_SetIdleState\n + * CR2 OIS6 LL_TIM_OC_SetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param IdleState This parameter can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Get the IDLE state of an output channel + * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n + * CR2 OIS2N LL_TIM_OC_GetIdleState\n + * CR2 OIS2 LL_TIM_OC_GetIdleState\n + * CR2 OIS2N LL_TIM_OC_GetIdleState\n + * CR2 OIS3 LL_TIM_OC_GetIdleState\n + * CR2 OIS3N LL_TIM_OC_GetIdleState\n + * CR2 OIS4 LL_TIM_OC_GetIdleState\n + * CR2 OIS5 LL_TIM_OC_GetIdleState\n + * CR2 OIS6 LL_TIM_OC_GetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Enable fast mode for the output channel. + * @note Acts only if the channel is configured in PWM1 or PWM2 mode. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n + * CCMR1 OC2FE LL_TIM_OC_EnableFast\n + * CCMR2 OC3FE LL_TIM_OC_EnableFast\n + * CCMR2 OC4FE LL_TIM_OC_EnableFast\n + * CCMR3 OC5FE LL_TIM_OC_EnableFast\n + * CCMR3 OC6FE LL_TIM_OC_EnableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Disable fast mode for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n + * CCMR1 OC2FE LL_TIM_OC_DisableFast\n + * CCMR2 OC3FE LL_TIM_OC_DisableFast\n + * CCMR2 OC4FE LL_TIM_OC_DisableFast\n + * CCMR3 OC5FE LL_TIM_OC_DisableFast\n + * CCMR3 OC6FE LL_TIM_OC_DisableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Indicates whether fast mode is enabled for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n + * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n + * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n + * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n + * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n + * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n + * CCMR3 OC6PE LL_TIM_OC_EnablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n + * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n + * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n + * CCMR3 OC6PE LL_TIM_OC_DisablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n + * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n + * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n + * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n + * CCMR1 OC2CE LL_TIM_OC_EnableClear\n + * CCMR2 OC3CE LL_TIM_OC_EnableClear\n + * CCMR2 OC4CE LL_TIM_OC_EnableClear\n + * CCMR3 OC5CE LL_TIM_OC_EnableClear\n + * CCMR3 OC6CE LL_TIM_OC_EnableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable clearing the output channel on an external event. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n + * CCMR1 OC2CE LL_TIM_OC_DisableClear\n + * CCMR2 OC3CE LL_TIM_OC_DisableClear\n + * CCMR2 OC4CE LL_TIM_OC_DisableClear\n + * CCMR3 OC5CE LL_TIM_OC_DisableClear\n + * CCMR3 OC6CE LL_TIM_OC_DisableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates clearing the output channel on an external event is enabled for the output channel. + * @note This function enables clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n + * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n + * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n + * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of + * the Ocx and OCxN signals). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * dead-time insertion feature is supported by a timer instance. + * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter + * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime + * @param TIMx Timer instance + * @param DeadTime between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); +} + +/** + * @brief Set compare value for output channel 1 (TIMx_CCR1). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR1, CompareValue); +} + +/** + * @brief Set compare value for output channel 2 (TIMx_CCR2). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR2, CompareValue); +} + +/** + * @brief Set compare value for output channel 3 (TIMx_CCR3). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR3, CompareValue); +} + +/** + * @brief Set compare value for output channel 4 (TIMx_CCR4). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR4, CompareValue); +} + +/** + * @brief Set compare value for output channel 5 (TIMx_CCR5). + * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * output channel 5 is supported by a timer instance. + * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); +} + +/** + * @brief Set compare value for output channel 6 (TIMx_CCR6). + * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * output channel 6 is supported by a timer instance. + * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR6, CompareValue); +} + +/** + * @brief Get compare value (TIMx_CCR1) set for output channel 1. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get compare value (TIMx_CCR2) set for output channel 2. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get compare value (TIMx_CCR3) set for output channel 3. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel 3 is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get compare value (TIMx_CCR4) set for output channel 4. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @brief Get compare value (TIMx_CCR5) set for output channel 5. + * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * output channel 5 is supported by a timer instance. + * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); +} + +/** + * @brief Get compare value (TIMx_CCR6) set for output channel 6. + * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * output channel 6 is supported by a timer instance. + * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR6)); +} + +/** + * @brief Select on which reference signal the OC5REF is combined to. + * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the combined 3-phase PWM mode. + * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n + * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n + * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels + * @param TIMx Timer instance + * @param GroupCH5 This parameter can be a combination of the following values: + * @arg @ref LL_TIM_GROUPCH5_NONE + * @arg @ref LL_TIM_GROUPCH5_OC1REFC + * @arg @ref LL_TIM_GROUPCH5_OC2REFC + * @arg @ref LL_TIM_GROUPCH5_OC3REFC + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) +{ + MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration + * @{ + */ +/** + * @brief Configure input channel. + * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n + * CCMR1 IC1PSC LL_TIM_IC_Config\n + * CCMR1 IC1F LL_TIM_IC_Config\n + * CCMR1 CC2S LL_TIM_IC_Config\n + * CCMR1 IC2PSC LL_TIM_IC_Config\n + * CCMR1 IC2F LL_TIM_IC_Config\n + * CCMR2 CC3S LL_TIM_IC_Config\n + * CCMR2 IC3PSC LL_TIM_IC_Config\n + * CCMR2 IC3F LL_TIM_IC_Config\n + * CCMR2 CC4S LL_TIM_IC_Config\n + * CCMR2 IC4PSC LL_TIM_IC_Config\n + * CCMR2 IC4F LL_TIM_IC_Config\n + * CCER CC1P LL_TIM_IC_Config\n + * CCER CC1NP LL_TIM_IC_Config\n + * CCER CC2P LL_TIM_IC_Config\n + * CCER CC2NP LL_TIM_IC_Config\n + * CCER CC3P LL_TIM_IC_Config\n + * CCER CC3NP LL_TIM_IC_Config\n + * CCER CC4P LL_TIM_IC_Config\n + * CCER CC4NP LL_TIM_IC_Config + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC + * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 + * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), + ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ + << SHIFT_TAB_ICxx[iChannel]); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_SetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICActiveInput This parameter can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_GetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the prescaler of input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current prescaler value acting on an input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n + * CCMR1 IC2F LL_TIM_IC_SetFilter\n + * CCMR2 IC3F LL_TIM_IC_SetFilter\n + * CCMR2 IC4F LL_TIM_IC_SetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n + * CCMR1 IC2F LL_TIM_IC_GetFilter\n + * CCMR2 IC3F LL_TIM_IC_GetFilter\n + * CCMR2 IC4F LL_TIM_IC_GetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n + * CCER CC1NP LL_TIM_IC_SetPolarity\n + * CCER CC2P LL_TIM_IC_SetPolarity\n + * CCER CC2NP LL_TIM_IC_SetPolarity\n + * CCER CC3P LL_TIM_IC_SetPolarity\n + * CCER CC3NP LL_TIM_IC_SetPolarity\n + * CCER CC4P LL_TIM_IC_SetPolarity\n + * CCER CC4NP LL_TIM_IC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + ICPolarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the current input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n + * CCER CC1NP LL_TIM_IC_GetPolarity\n + * CCER CC2P LL_TIM_IC_GetPolarity\n + * CCER CC2NP LL_TIM_IC_GetPolarity\n + * CCER CC3P LL_TIM_IC_GetPolarity\n + * CCER CC3NP LL_TIM_IC_GetPolarity\n + * CCER CC4P LL_TIM_IC_GetPolarity\n + * CCER CC4NP LL_TIM_IC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> + SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); +} + +/** + * @brief Get captured value for input channel 1. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * input channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get captured value for input channel 2. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * input channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get captured value for input channel 3. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * input channel 3 is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get captured value for input channel 4. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * input channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection + * @{ + */ +/** + * @brief Enable external clock mode 2. + * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_EnableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Disable external clock mode 2. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_DisableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Indicate whether external clock mode 2 is enabled. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); +} + +/** + * @brief Set the clock source of the counter clock. + * @note when selected clock source is external clock mode 1, the timer input + * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() + * function. This timer input must be configured by calling + * the @ref LL_TIM_IC_Config() function. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode1. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR SMS LL_TIM_SetClockSource\n + * SMCR ECE LL_TIM_SetClockSource + * @param TIMx Timer instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); +} + +/** + * @brief Set the encoder interface mode. + * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the encoder mode. + * @rmtoll SMCR SMS LL_TIM_SetEncoderMode + * @param TIMx Timer instance + * @param EncoderMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 + * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 + * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration + * @{ + */ +/** + * @brief Set the trigger output (TRGO) used for timer synchronization . + * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance can operate as a master timer. + * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput + * @param TIMx Timer instance + * @param TimerSynchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO_RESET + * @arg @ref LL_TIM_TRGO_ENABLE + * @arg @ref LL_TIM_TRGO_UPDATE + * @arg @ref LL_TIM_TRGO_CC1IF + * @arg @ref LL_TIM_TRGO_OC1REF + * @arg @ref LL_TIM_TRGO_OC2REF + * @arg @ref LL_TIM_TRGO_OC3REF + * @arg @ref LL_TIM_TRGO_OC4REF + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); +} + +/** + * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . + * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance can be used for ADC synchronization. + * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 + * @param TIMx Timer Instance + * @param ADCSynchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO2_RESET + * @arg @ref LL_TIM_TRGO2_ENABLE + * @arg @ref LL_TIM_TRGO2_UPDATE + * @arg @ref LL_TIM_TRGO2_CC1F + * @arg @ref LL_TIM_TRGO2_OC1 + * @arg @ref LL_TIM_TRGO2_OC2 + * @arg @ref LL_TIM_TRGO2_OC3 + * @arg @ref LL_TIM_TRGO2_OC4 + * @arg @ref LL_TIM_TRGO2_OC5 + * @arg @ref LL_TIM_TRGO2_OC6 + * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING + * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); +} + +/** + * @brief Set the synchronization mode of a slave timer. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR SMS LL_TIM_SetSlaveMode + * @param TIMx Timer instance + * @param SlaveMode This parameter can be one of the following values: + * @arg @ref LL_TIM_SLAVEMODE_DISABLED + * @arg @ref LL_TIM_SLAVEMODE_RESET + * @arg @ref LL_TIM_SLAVEMODE_GATED + * @arg @ref LL_TIM_SLAVEMODE_TRIGGER + * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); +} + +/** + * @brief Set the selects the trigger input to be used to synchronize the counter. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR TS LL_TIM_SetTriggerInput + * @param TIMx Timer instance + * @param TriggerInput This parameter can be one of the following values: + * @arg @ref LL_TIM_TS_ITR0 + * @arg @ref LL_TIM_TS_ITR1 + * @arg @ref LL_TIM_TS_ITR2 + * @arg @ref LL_TIM_TS_ITR3 + * @arg @ref LL_TIM_TS_TI1F_ED + * @arg @ref LL_TIM_TS_TI1FP1 + * @arg @ref LL_TIM_TS_TI2FP2 + * @arg @ref LL_TIM_TS_ETRF + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); +} + +/** + * @brief Enable the Master/Slave mode. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Disable the Master/Slave mode. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Indicates whether the Master/Slave mode is enabled. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); +} + +/** + * @brief Configure the external trigger (ETR) input. + * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an external trigger input. + * @rmtoll SMCR ETP LL_TIM_ConfigETR\n + * SMCR ETPS LL_TIM_ConfigETR\n + * SMCR ETF LL_TIM_ConfigETR + * @param TIMx Timer instance + * @param ETRPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED + * @arg @ref LL_TIM_ETR_POLARITY_INVERTED + * @param ETRPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 + * @param ETRFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_FILTER_FDIV1 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, + uint32_t ETRFilter) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); +} + +/** + * @brief Select the external trigger (ETR) input source. + * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or + * not a timer instance supports ETR source selection. + * @rmtoll OR2 ETRSEL LL_TIM_SetETRSource + * @param TIMx Timer instance + * @param ETRSource This parameter can be one of the following values: + * @arg @ref LL_TIM_ETRSOURCE_LEGACY + * @arg @ref LL_TIM_ETRSOURCE_COMP1 + * @arg @ref LL_TIM_ETRSOURCE_COMP2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource) +{ + MODIFY_REG(TIMx->OR2, TIMx_OR2_ETRSEL, ETRSource); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Break_Function Break function configuration + * @{ + */ +/** + * @brief Enable the break function. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR BKE LL_TIM_EnableBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); +} + +/** + * @brief Disable the break function. + * @rmtoll BDTR BKE LL_TIM_DisableBRK + * @param TIMx Timer instance + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); +} + +/** + * @brief Configure the break input. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n + * BDTR BKF LL_TIM_ConfigBRK + * @param TIMx Timer instance + * @param BreakPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_POLARITY_LOW + * @arg @ref LL_TIM_BREAK_POLARITY_HIGH + * @param BreakFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, + uint32_t BreakFilter) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); +} + +/** + * @brief Enable the break 2 function. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); +} + +/** + * @brief Disable the break 2 function. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); +} + +/** + * @brief Configure the break 2 input. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n + * BDTR BK2F LL_TIM_ConfigBRK2 + * @param TIMx Timer instance + * @param Break2Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_POLARITY_LOW + * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH + * @param Break2Filter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); +} + +/** + * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n + * BDTR OSSR LL_TIM_SetOffStates + * @param TIMx Timer instance + * @param OffStateIdle This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSI_DISABLE + * @arg @ref LL_TIM_OSSI_ENABLE + * @param OffStateRun This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSR_DISABLE + * @arg @ref LL_TIM_OSSR_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); +} + +/** + * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Disable automatic output (MOE can be set only by software). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Indicate whether automatic output is enabled. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Indicates whether outputs are enabled. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the signals connected to the designated timer break input. + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll OR2 BKINE LL_TIM_EnableBreakInputSource\n + * OR2 BKCMP1E LL_TIM_EnableBreakInputSource\n + * OR2 BKCMP2E LL_TIM_EnableBreakInputSource\n + * OR2 BKDF1BK0E LL_TIM_EnableBreakInputSource\n + * OR3 BK2INE LL_TIM_EnableBreakInputSource\n + * OR3 BK2CMP1E LL_TIM_EnableBreakInputSource\n + * OR3 BK2CMP2E LL_TIM_EnableBreakInputSource\n + * OR3 BK2DF1BK1E LL_TIM_EnableBreakInputSource + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 + * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); + SET_BIT(*pReg, Source); +} + +/** + * @brief Disable the signals connected to the designated timer break input. + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll OR2 BKINE LL_TIM_DisableBreakInputSource\n + * OR2 BKCMP1E LL_TIM_DisableBreakInputSource\n + * OR2 BKCMP2E LL_TIM_DisableBreakInputSource\n + * OR2 BKDF1BK0E LL_TIM_DisableBreakInputSource\n + * OR3 BK2INE LL_TIM_DisableBreakInputSource\n + * OR3 BK2CMP1E LL_TIM_DisableBreakInputSource\n + * OR3 BK2CMP2E LL_TIM_DisableBreakInputSource\n + * OR3 BK2DF1BK1E LL_TIM_DisableBreakInputSource + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 + * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); + CLEAR_BIT(*pReg, Source); +} + +/** + * @brief Set the polarity of the break signal for the timer break input. + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll OR2 BKINP LL_TIM_SetBreakInputSourcePolarity\n + * OR2 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n + * OR2 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n + * OR3 BK2INP LL_TIM_SetBreakInputSourcePolarity\n + * OR3 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n + * OR3 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_POLARITY_LOW + * @arg @ref LL_TIM_BKIN_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, + uint32_t Polarity) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); + MODIFY_REG(*pReg, (TIMx_OR2_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE)); +} +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration + * @{ + */ +/** + * @brief Configures the timer DMA burst feature. + * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or + * not a timer instance supports the DMA burst mode. + * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n + * DCR DBA LL_TIM_ConfigDMABurst + * @param TIMx Timer instance + * @param DMABurstBaseAddress This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER + * @arg @ref LL_TIM_DMABURST_BASEADDR_SR + * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER + * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT + * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC + * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR + * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 + * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR + * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 + * @arg @ref LL_TIM_DMABURST_BASEADDR_OR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_OR3 + * @param DMABurstLength This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER + * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) +{ + MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping + * @{ + */ +/** + * @brief Remap TIM inputs (input channel, internal/external triggers). + * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not + * a some timer inputs can be remapped. + @if STM32L486xx + * @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n + * TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n + * TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n + * TIM8_OR1 ETR_ADC2_RMP LL_TIM_SetRemap\n + * TIM8_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n + * TIM8_OR1 TI1_RMP LL_TIM_SetRemap\n + * TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n + * TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n + * TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n + * TIM3_OR1 TI1_RMP LL_TIM_SetRemap\n + * TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n + * TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n + * TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n + * TIM17_OR1 TI1_RMP LL_TIM_SetRemap + @endif + @if STM32L443xx + * @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n + * TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n + * TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n + * TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n + * TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n + * TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n + * TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n + * TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n + * TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n + @endif + * @param TIMx Timer instance + * @param Remap Remap param depends on the TIMx. Description available only + * in CHM version of the User Manual (not in .pdf). + * Otherwise see Reference Manual description of OR registers. + * + * Below description summarizes "Timer Instance" and "Remap" param combinations: + * + @if STM32L486xx + * TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where + * + * . . ADC1_RMP can be one of the following values + * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC + * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 + * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 + * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 + * + * . . ADC3_RMP can be one of the following values + * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC + * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 + * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 + * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 + * + * . . TI1_RMP can be one of the following values + * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1 + * + * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where + * + * ITR1_RMP can be one of the following values + * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO + * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF + * + * . . ETR1_RMP can be one of the following values + * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO + * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE + * + * . . TI4_RMP can be one of the following values + * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO + * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1 + * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2 + * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 + * + * TIM3: one of the following values + * + * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1 + * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2 + * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 + * + * TIM8: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where + * + * . . ADC1_RMP can be one of the following values + * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC + * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 + * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 + * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 + * + * . . ADC3_RMP can be one of the following values + * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC + * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 + * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 + * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 + * + * . . TI1_RMP can be one of the following values + * @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2 + * + * TIM15: any combination of TI1_RMP, ENCODER_MODE where + * + * . . TI1_RMP can be one of the following values + * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE + * + * . . ENCODER_MODE can be one of the following values + * @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION + * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2 + * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3 + * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4 + * + * TIM16: one of the following values + * + * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI + * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE + * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC + * @arg @ref LL_TIM_TIM16_TI1_RMP_MSI + * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32 + * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO + * + * TIM17: one of the following values + * + * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM17_TI1_RMP_MSI + * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32 + * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO + @endif + @if STM32L443xx + * TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where + * + * . . ADC1_RMP can be one of the following values + * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC + * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 + * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 + * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 + * + * . . TI1_RMP can be one of the following values + * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1 + * + * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where + * + * ITR1_RMP can be one of the following values + * @arg @ref LL_TIM_TIM2_ITR1_RMP_NONE + * @arg @ref LL_TIM_TIM2_ITR1_RMP_USB_SOF + * + * . . ETR1_RMP can be one of the following values + * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO + * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE + * + * . . TI4_RMP can be one of the following values + * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO + * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1 + * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2 + * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 + * + * TIM15: any combination of TI1_RMP, ENCODER_MODE where + * + * . . TI1_RMP can be one of the following values + * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE + * + * . . ENCODER_MODE can be one of the following values + * @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION + * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2 + * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3 + * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4 + * + * TIM16: one of the following values + * + * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI + * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE + * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC + * @arg @ref LL_TIM_TIM16_TI1_RMP_MSI + * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32 + * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO + @endif + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) +{ + MODIFY_REG(TIMx->OR1, (Remap >> TIMx_OR1_RMP_SHIFT), (Remap & TIMx_OR1_RMP_MASK)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management + * @{ + */ +/** + * @brief Set the OCREF clear input source + * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT + * @note This function can only be used in Output compare and PWM modes. + * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource + * @param TIMx Timer instance + * @param OCRefClearInputSource This parameter can be one of the following values: + * @arg @ref LL_TIM_OCREF_CLR_INT_NC + * @arg @ref LL_TIM_OCREF_CLR_INT_ETR + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource); +} +/** + * @} + */ + +/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management + * @{ + */ +/** + * @brief Clear the update interrupt flag (UIF). + * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); +} + +/** + * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). + * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). + * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). + * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). + * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). + * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). + * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). + * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). + * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). + * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); +} + +/** + * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending). + * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). + * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); +} + +/** + * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending). + * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the commutation interrupt flag (COMIF). + * @rmtoll SR COMIF LL_TIM_ClearFlag_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); +} + +/** + * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). + * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the trigger interrupt flag (TIF). + * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); +} + +/** + * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). + * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the break interrupt flag (BIF). + * @rmtoll SR BIF LL_TIM_ClearFlag_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); +} + +/** + * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). + * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the break 2 interrupt flag (B2IF). + * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); +} + +/** + * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). + * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). + * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set + * (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). + * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set + * (Capture/Compare 2 over-capture interrupt is pending). + * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). + * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set + * (Capture/Compare 3 over-capture interrupt is pending). + * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). + * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set + * (Capture/Compare 4 over-capture interrupt is pending). + * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the system break interrupt flag (SBIF). + * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); +} + +/** + * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending). + * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_IT_Management IT-Management + * @{ + */ +/** + * @brief Enable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Disable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Indicates whether the update interrupt (UIE) is enabled. + * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Disable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. + * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Disable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. + * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Disable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. + * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Disable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. + * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_EnableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Disable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_DisableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Indicates whether the commutation interrupt (COMIE) is enabled. + * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Disable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Indicates whether the trigger interrupt (TIE) is enabled. + * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_EnableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Disable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_DisableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Indicates whether the break interrupt (BIE) is enabled. + * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Management DMA Management + * @{ + */ +/** + * @brief Enable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Disable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Indicates whether the update DMA request (UDE) is enabled. + * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Disable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. + * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Disable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. + * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Disable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. + * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Disable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. + * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Disable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Indicates whether the commutation DMA request (COMDE) is enabled. + * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Disable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Indicates whether the trigger interrupt (TDE) is enabled. + * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management + * @{ + */ +/** + * @brief Generate an update event. + * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_UG); +} + +/** + * @brief Generate Capture/Compare 1 event. + * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC1G); +} + +/** + * @brief Generate Capture/Compare 2 event. + * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC2G); +} + +/** + * @brief Generate Capture/Compare 3 event. + * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC3G); +} + +/** + * @brief Generate Capture/Compare 4 event. + * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC4G); +} + +/** + * @brief Generate commutation event. + * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_COMG); +} + +/** + * @brief Generate trigger event. + * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_TG); +} + +/** + * @brief Generate break event. + * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_BG); +} + +/** + * @brief Generate break 2 event. + * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_B2G); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions + * @{ + */ + +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx); +void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); +void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); +void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_LL_TIM_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/LICENSE.txt b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/LICENSE.txt similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/LICENSE.txt rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/LICENSE.txt diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c diff --git 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a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c rename to 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b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c rename to 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benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_common_config.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_common_config.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_common_config.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_common_config.h index 05a449cf..d403df0a 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_common_config.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_common_config.h @@ -1,31 +1,31 @@ -/** - ****************************************************************************** - * @file ai_common_config.h - * @author AST Embedded Analytics Research Platform - * @brief header file of AI platform common compile configuration defines - ****************************************************************************** - * @attention - * - * Copyright (c) 2018 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef AI_COMMON_CONFIG_H -#define AI_COMMON_CONFIG_H - -/*! - * @defgroup layers Layers Compilation Config Definitions - * @brief definition - * - */ - -#define HAS_PROFILE_FLOAT -#define HAS_PROFILE_FIXED - - -#endif /*AI_COMMON_CONFIG_H*/ +/** + ****************************************************************************** + * @file ai_common_config.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform common compile configuration defines + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef AI_COMMON_CONFIG_H +#define AI_COMMON_CONFIG_H + +/*! + * @defgroup layers Layers Compilation Config Definitions + * @brief definition + * + */ + +#define HAS_PROFILE_FLOAT +#define HAS_PROFILE_FIXED + + +#endif /*AI_COMMON_CONFIG_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes.h index 342d8ca9..42104186 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes.h @@ -1,71 +1,71 @@ - -#ifndef AI_DATATYPES_H -#define AI_DATATYPES_H -/** - ****************************************************************************** - * @file ai_datatypes.h - * @author AST Embedded Analytics Research Platform - * @brief Definitions of AI platform private APIs types - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#include -#include "ai_platform.h" -#include "ai_platform_interface.h" - -/*! - * @defgroup datatypes Platform Interface Datatypes - * @brief Data structures used by AI platform to implement neural networks - * - */ - -/** Count Variable Number of Arguments (up to 64 elements) *******************/ -#define AI_NUMARGS(...) \ - PP_NARG_(__VA_ARGS__,PP_RSEQ_N()) -#define PP_NARG_(...) \ - PP_ARG_N(__VA_ARGS__) -#define PP_ARG_N( \ - _1, _2, _3, _4, _5, _6, _7, _8, _9,_10, \ - _11,_12,_13,_14,_15,_16,_17,_18,_19,_20, \ - _21,_22,_23,_24,_25,_26,_27,_28,_29,_30, \ - _31,_32,_33,_34,_35,_36,_37,_38,_39,_40, \ - _41,_42,_43,_44,_45,_46,_47,_48,_49,_50, \ - _51,_52,_53,_54,_55,_56,_57,_58,_59,_60, \ - _61,_62,_63,N,...) N -#define PP_RSEQ_N() \ - 63,62,61,60, \ - 59,58,57,56,55,54,53,52,51,50, \ - 49,48,47,46,45,44,43,42,41,40, \ - 39,38,37,36,35,34,33,32,31,30, \ - 29,28,27,26,25,24,23,22,21,20, \ - 19,18,17,16,15,14,13,12,11,10, \ - 9,8,7,6,5,4,3,2,1,0 - - -/*****************************************************************************/ -#define AI_PTR_ALIGN(ptr, alignment) \ - ((((ai_uptr)(ptr))+((ai_uptr)(alignment)-1))&(~((ai_uptr)(alignment)-1))) - - -/*! - * @typedef ai_offset - * @ingroup ai_datatypes_internal - * @brief Generic index offset type - */ -typedef int32_t ai_offset; - - -AI_API_DECLARE_BEGIN - -AI_API_DECLARE_END - -#endif /* AI_DATATYPES_H */ + +#ifndef AI_DATATYPES_H +#define AI_DATATYPES_H +/** + ****************************************************************************** + * @file ai_datatypes.h + * @author AST Embedded Analytics Research Platform + * @brief Definitions of AI platform private APIs types + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#include +#include "ai_platform.h" +#include "ai_platform_interface.h" + +/*! + * @defgroup datatypes Platform Interface Datatypes + * @brief Data structures used by AI platform to implement neural networks + * + */ + +/** Count Variable Number of Arguments (up to 64 elements) *******************/ +#define AI_NUMARGS(...) \ + PP_NARG_(__VA_ARGS__,PP_RSEQ_N()) +#define PP_NARG_(...) \ + PP_ARG_N(__VA_ARGS__) +#define PP_ARG_N( \ + _1, _2, _3, _4, _5, _6, _7, _8, _9,_10, \ + _11,_12,_13,_14,_15,_16,_17,_18,_19,_20, \ + _21,_22,_23,_24,_25,_26,_27,_28,_29,_30, \ + _31,_32,_33,_34,_35,_36,_37,_38,_39,_40, \ + _41,_42,_43,_44,_45,_46,_47,_48,_49,_50, \ + _51,_52,_53,_54,_55,_56,_57,_58,_59,_60, \ + _61,_62,_63,N,...) N +#define PP_RSEQ_N() \ + 63,62,61,60, \ + 59,58,57,56,55,54,53,52,51,50, \ + 49,48,47,46,45,44,43,42,41,40, \ + 39,38,37,36,35,34,33,32,31,30, \ + 29,28,27,26,25,24,23,22,21,20, \ + 19,18,17,16,15,14,13,12,11,10, \ + 9,8,7,6,5,4,3,2,1,0 + + +/*****************************************************************************/ +#define AI_PTR_ALIGN(ptr, alignment) \ + ((((ai_uptr)(ptr))+((ai_uptr)(alignment)-1))&(~((ai_uptr)(alignment)-1))) + + +/*! + * @typedef ai_offset + * @ingroup ai_datatypes_internal + * @brief Generic index offset type + */ +typedef int32_t ai_offset; + + +AI_API_DECLARE_BEGIN + +AI_API_DECLARE_END + +#endif /* AI_DATATYPES_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes_defines.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes_defines.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes_defines.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes_defines.h index 1e388be7..fa0469d2 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes_defines.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes_defines.h @@ -1,153 +1,153 @@ -/** - ****************************************************************************** - * @file ai_datatypes_defines.h - * @author AST Embedded Analytics Research Platform - * @brief Definitions of AI platform private APIs types - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef AI_DATATYPES_DEFINES_H -#define AI_DATATYPES_DEFINES_H - -#include "ai_platform.h" -#include "core_assert.h" - - -/*! - * @defgroup datatypes_defines Internal Datatypes Defines Header - * @brief Data structures used internally to implement neural networks - * - */ - -/* define to track datatypes used by codegen */ -#define AI_INTERFACE_TYPE /* AI_INTERFACE_TYPE */ - -#define AI_INTERNAL_API /* AI_INTERNAL_API */ - -#define AI_CONST const -#define AI_STATIC static -#define AI_STATIC_CONST static const - -/******************************************************************************/ -/* NOP operation used by codegen */ -#define AI_NOP /* NOP */ - -#define AI_WRAP_FUNC(fn_) do { fn_ } while (0); - -#define AI_CAT(a, ...) AI_PRIMITIVE_CAT(a, __VA_ARGS__) -#define AI_PRIMITIVE_CAT(a, ...) a ## __VA_ARGS__ - -/******************************************************************************/ -#define AI_ASSERT(expr) \ - CORE_ASSERT(expr) - - -/******************************************************************************/ -#define AI_NO_PACKED_STRUCTS - -/* Macro for defining packed structures (compiler dependent). - * This just reduces memory requirements, but is not required. - */ -#if defined(AI_NO_PACKED_STRUCTS) - /* Disable struct packing */ - #define AI_PACKED_STRUCT_START /* AI_PACKED_STRUCT_START */ - #define AI_PACKED_STRUCT_END /* AI_PACKED_STRUCT_END */ - #define AI_PACKED /* AI_PACKED */ -#elif defined(__GNUC__) || defined(__clang__) - /* For GCC and clang */ - #define AI_PACKED_STRUCT_START /* AI_PACKED_STRUCT_START */ - #define AI_PACKED_STRUCT_END /* AI_PACKED_STRUCT_END */ - #define AI_PACKED __attribute__((packed)) -#elif defined(__ICCARM__) || defined (__IAR_SYSTEMS_ICC__) || defined(__CC_ARM) - /* For IAR ARM and Keil MDK-ARM compilers */ - #define AI_PACKED_STRUCT_START _Pragma("pack(push, 1)") - #define AI_PACKED_STRUCT_END _Pragma("pack(pop)") - #define AI_PACKED /* AI_PACKED */ -#elif defined(_MSC_VER) && (_MSC_VER >= 1500) - /* For Microsoft Visual C++ */ - #define AI_PACKED_STRUCT_START __pragma(pack(push, 1)) - #define AI_PACKED_STRUCT_END __pragma(pack(pop)) - #define AI_PACKED /* AI_PACKED */ -#else - /* Unknown compiler */ - #define AI_PACKED_STRUCT_START /* AI_PACKED_STRUCT_START */ - #define AI_PACKED_STRUCT_END /* AI_PACKED_STRUCT_END */ - #define AI_PACKED /* AI_PACKED */ -#endif /* AI_NO_PACKED_STRUCTS */ - -/******************************************************************************/ -#define AI_STRINGIFY_ARG(contents) # contents -#define AI_STRINGIFY(macro_or_string) AI_STRINGIFY_ARG (macro_or_string) - -/******************************************************************************/ -#if defined(_MSC_VER) - #define AI_DECLARE_STATIC static __inline - // #define AI_FORCE_INLINE static __forceinline - #define AI_FORCE_INLINE static __inline - #define AI_HINT_INLINE static __inline - #define AI_ALIGNED_TYPE(type, x) type __declspec(align(x)) - #define AI_INTERFACE_ENTRY __declspec(dllexport) -#elif defined(__ICCARM__) || defined (__IAR_SYSTEMS_ICC__) - #define AI_DECLARE_STATIC static inline - // #define AI_FORCE_INLINE static _Pragma("inline=forced") // TODO: check this definition! - #define AI_FORCE_INLINE static inline - #define AI_HINT_INLINE static inline - #define AI_ALIGNED_TYPE(type, x) type - #define AI_INTERFACE_ENTRY /* AI_INTERFACE_ENTRY */ -#elif defined(__GNUC__) - #define AI_DECLARE_STATIC static __inline - #define AI_FORCE_INLINE static __inline - #define AI_HINT_INLINE static __inline - #define AI_ALIGNED_TYPE(type, x) type __attribute__ ((aligned(x))) - #define AI_INTERFACE_ENTRY /* AI_INTERFACE_ENTRY */ -#else /* _MSC_VER */ - #define AI_DECLARE_STATIC static __inline - // #define AI_FORCE_INLINE static __forceinline - #define AI_FORCE_INLINE static __inline - #define AI_HINT_INLINE static __inline - #define AI_ALIGNED_TYPE(type, x) type __attribute__ ((aligned(x))) - #define AI_INTERFACE_ENTRY __attribute__((visibility("default"))) -#endif /* _MSC_VER */ - -/******************************************************************************/ -#define AI_ALIGN_MASKED(value, mask) ( ((value)+(mask))&(~(mask)) ) - -#define AI_GET_VERSION_STRING(major, minor, micro) \ - AI_STRINGIFY_ARG(major) "." \ - AI_STRINGIFY_ARG(minor) "." \ - AI_STRINGIFY_ARG(micro) \ - - -#define AI_PACK_TENSORS_PTR(...) \ - AI_PACK(__VA_ARGS__) - -#define AI_PACK_INFO(size_) (ai_tensor_info[1]) { { \ - .buffer = (ai_buffer[size_])AI_STRUCT_INIT, \ - .state = (ai_tensor_state[size_])AI_STRUCT_INIT, \ -} } - -#define AI_CR "\r\n" - -#if (defined HAS_AI_DEBUG || defined HAS_DEBUG_LIB) -#include -#define AI_DEBUG(...) __VA_ARGS__ -#define AI_DEBUG_PRINT(fmt, ...) { printf(fmt, ##__VA_ARGS__); } -#else -#define AI_DEBUG(...) AI_WRAP_FUNC(/*AI_DEBUG*/) -#define AI_DEBUG_PRINT(fmt, ...) AI_WRAP_FUNC(/*AI_DEBUG_PRINT*/) -#endif - -#define AI_FLAG_SET(mask, flag) (mask) |= (flag) -#define AI_FLAG_UNSET(mask, flag) (mask) &= (~(flag)) -#define AI_FLAG_IS_SET(mask, flag) ((flag)==((mask)&(flag))) - -#endif /*AI_DATATYPES_DEFINES_H*/ +/** + ****************************************************************************** + * @file ai_datatypes_defines.h + * @author AST Embedded Analytics Research Platform + * @brief Definitions of AI platform private APIs types + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef AI_DATATYPES_DEFINES_H +#define AI_DATATYPES_DEFINES_H + +#include "ai_platform.h" +#include "core_assert.h" + + +/*! + * @defgroup datatypes_defines Internal Datatypes Defines Header + * @brief Data structures used internally to implement neural networks + * + */ + +/* define to track datatypes used by codegen */ +#define AI_INTERFACE_TYPE /* AI_INTERFACE_TYPE */ + +#define AI_INTERNAL_API /* AI_INTERNAL_API */ + +#define AI_CONST const +#define AI_STATIC static +#define AI_STATIC_CONST static const + +/******************************************************************************/ +/* NOP operation used by codegen */ +#define AI_NOP /* NOP */ + +#define AI_WRAP_FUNC(fn_) do { fn_ } while (0); + +#define AI_CAT(a, ...) AI_PRIMITIVE_CAT(a, __VA_ARGS__) +#define AI_PRIMITIVE_CAT(a, ...) a ## __VA_ARGS__ + +/******************************************************************************/ +#define AI_ASSERT(expr) \ + CORE_ASSERT(expr) + + +/******************************************************************************/ +#define AI_NO_PACKED_STRUCTS + +/* Macro for defining packed structures (compiler dependent). + * This just reduces memory requirements, but is not required. + */ +#if defined(AI_NO_PACKED_STRUCTS) + /* Disable struct packing */ + #define AI_PACKED_STRUCT_START /* AI_PACKED_STRUCT_START */ + #define AI_PACKED_STRUCT_END /* AI_PACKED_STRUCT_END */ + #define AI_PACKED /* AI_PACKED */ +#elif defined(__GNUC__) || defined(__clang__) + /* For GCC and clang */ + #define AI_PACKED_STRUCT_START /* AI_PACKED_STRUCT_START */ + #define AI_PACKED_STRUCT_END /* AI_PACKED_STRUCT_END */ + #define AI_PACKED __attribute__((packed)) +#elif defined(__ICCARM__) || defined (__IAR_SYSTEMS_ICC__) || defined(__CC_ARM) + /* For IAR ARM and Keil MDK-ARM compilers */ + #define AI_PACKED_STRUCT_START _Pragma("pack(push, 1)") + #define AI_PACKED_STRUCT_END _Pragma("pack(pop)") + #define AI_PACKED /* AI_PACKED */ +#elif defined(_MSC_VER) && (_MSC_VER >= 1500) + /* For Microsoft Visual C++ */ + #define AI_PACKED_STRUCT_START __pragma(pack(push, 1)) + #define AI_PACKED_STRUCT_END __pragma(pack(pop)) + #define AI_PACKED /* AI_PACKED */ +#else + /* Unknown compiler */ + #define AI_PACKED_STRUCT_START /* AI_PACKED_STRUCT_START */ + #define AI_PACKED_STRUCT_END /* AI_PACKED_STRUCT_END */ + #define AI_PACKED /* AI_PACKED */ +#endif /* AI_NO_PACKED_STRUCTS */ + +/******************************************************************************/ +#define AI_STRINGIFY_ARG(contents) # contents +#define AI_STRINGIFY(macro_or_string) AI_STRINGIFY_ARG (macro_or_string) + +/******************************************************************************/ +#if defined(_MSC_VER) + #define AI_DECLARE_STATIC static __inline + // #define AI_FORCE_INLINE static __forceinline + #define AI_FORCE_INLINE static __inline + #define AI_HINT_INLINE static __inline + #define AI_ALIGNED_TYPE(type, x) type __declspec(align(x)) + #define AI_INTERFACE_ENTRY __declspec(dllexport) +#elif defined(__ICCARM__) || defined (__IAR_SYSTEMS_ICC__) + #define AI_DECLARE_STATIC static inline + // #define AI_FORCE_INLINE static _Pragma("inline=forced") // TODO: check this definition! + #define AI_FORCE_INLINE static inline + #define AI_HINT_INLINE static inline + #define AI_ALIGNED_TYPE(type, x) type + #define AI_INTERFACE_ENTRY /* AI_INTERFACE_ENTRY */ +#elif defined(__GNUC__) + #define AI_DECLARE_STATIC static __inline + #define AI_FORCE_INLINE static __inline + #define AI_HINT_INLINE static __inline + #define AI_ALIGNED_TYPE(type, x) type __attribute__ ((aligned(x))) + #define AI_INTERFACE_ENTRY /* AI_INTERFACE_ENTRY */ +#else /* _MSC_VER */ + #define AI_DECLARE_STATIC static __inline + // #define AI_FORCE_INLINE static __forceinline + #define AI_FORCE_INLINE static __inline + #define AI_HINT_INLINE static __inline + #define AI_ALIGNED_TYPE(type, x) type __attribute__ ((aligned(x))) + #define AI_INTERFACE_ENTRY __attribute__((visibility("default"))) +#endif /* _MSC_VER */ + +/******************************************************************************/ +#define AI_ALIGN_MASKED(value, mask) ( ((value)+(mask))&(~(mask)) ) + +#define AI_GET_VERSION_STRING(major, minor, micro) \ + AI_STRINGIFY_ARG(major) "." \ + AI_STRINGIFY_ARG(minor) "." \ + AI_STRINGIFY_ARG(micro) \ + + +#define AI_PACK_TENSORS_PTR(...) \ + AI_PACK(__VA_ARGS__) + +#define AI_PACK_INFO(size_) (ai_tensor_info[1]) { { \ + .buffer = (ai_buffer[size_])AI_STRUCT_INIT, \ + .state = (ai_tensor_state[size_])AI_STRUCT_INIT, \ +} } + +#define AI_CR "\r\n" + +#if (defined HAS_AI_DEBUG || defined HAS_DEBUG_LIB) +#include +#define AI_DEBUG(...) __VA_ARGS__ +#define AI_DEBUG_PRINT(fmt, ...) { printf(fmt, ##__VA_ARGS__); } +#else +#define AI_DEBUG(...) AI_WRAP_FUNC(/*AI_DEBUG*/) +#define AI_DEBUG_PRINT(fmt, ...) AI_WRAP_FUNC(/*AI_DEBUG_PRINT*/) +#endif + +#define AI_FLAG_SET(mask, flag) (mask) |= (flag) +#define AI_FLAG_UNSET(mask, flag) (mask) &= (~(flag)) +#define AI_FLAG_IS_SET(mask, flag) ((flag)==((mask)&(flag))) + +#endif /*AI_DATATYPES_DEFINES_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes_format.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes_format.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes_format.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes_format.h index 014fb033..f5e003e2 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes_format.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes_format.h @@ -1,484 +1,484 @@ -/** - ****************************************************************************** - * @file ai_datatypes_format.h - * @author AST Embedded Analytics Research Platform - * @brief Definitions of AI platform private format handling routines - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef AI_DATATYPES_FORMAT_H -#define AI_DATATYPES_FORMAT_H - -#include "ai_platform.h" -#include "ai_datatypes_defines.h" - - -/*! - * @defgroup ai_datatypes_format Definiton and Macro of array and buffer formats - * @brief Type definition and implementation of internal @ref ai_array and - * @ref ai_buffer formats. - * @details The library handles 2 different kind of formats: an internal format - * that is part of the @ref ai_array struct that is a packed 32bit representation - * of the format attributes, and a public format (used in public APIs) associated - * with @ref ai_buffer struct , defined as enum in @ref ai_platform.h, - * that is just an enum type. Converters are provided in this header file to - * convert from one format representation to another. - * Some MSB bits are reserved in both formats to code some bit flag useful to - * declare some special attribute. Three flags are actually implemented in both - * formats: the @ref AI_BUFFER_FMT_FLAG_CONST and @ref AI_FMT_FLAG_CONST used - * to tag read-only memory buffers, @ref AI_BUFFER_FMT_FLAG_STATIC and - * @ref AI_FMT_FLAG_STATIC to mark statically allocated memory buffers and - * @ref AI_FMT_FLAG_SCRATCH_BUFFER to tag temporary scratch buffers. - * All the formats are declared in a proper tuple organize table header named - * @ref format_lists.h that enumerates all the formats available for the library. - * A new format could be added easily by adding a new FMY_ENTRY() as required. - * The preprocessor automatically generates the code for the handling of the - * format according to this tuples entry. A rational for the methodology could - * be found here: - * - https://codecraft.co/2012/10/29/how-enums-spread-disease-and-how-to-cure-it/ - * - * The 32bits internal format fields are organized as follows: - * - * MSB LSB - * 31 25 24 23 21 17 14 7 0 - * /---------------------------------------------------------------------------/ - * / ATTR. FLAGS | FLOAT | SIGN | LDIV | TYPE | PMASK | BITS | FBITS / - * /---------------------------------------------------------------------------/ - * Where: - * - FLAGS: is the reserved bits to store additional format attributes (e.g. - * I/O / STATIC flags. etc.) - * - FLOAT: 1 bit mark the format as floating point type - * - SIGN : 1 bit mark the format as signed type - * - LDIV : 2 bits is a log2 value that is used to compute elements size - * with some special format such as the compressed ones. It is a shift - * factor usually set to zero - * - TYPE : 4 bits mark the format "family" type. Actually 5 families are coded, - * @ref AI_FMT_FLOAT (float types) - * @ref AI_FMT_Q (fixed-point types in Qm.n format) - * @ref AI_FMT_BOOL (boolean type) - * @ref AI_FMT_LUT4 (compressed lookup 16 formats) - * @ref AI_FMT_LUT8 (compressed lookup 256 formats) - * - PMASK 3 bits padding mask used to set the optional dimension for padding - * to handle special aligned formats/ E.g. a 1 bit format - * Usually this is set to 0x0 - * - BITS 7 bits set the total number of bits of the element, padding bits - * excluded. The bits are thus = sign bit + fractional bits + integer bits - * The number of integer bits could thus be known using the @ref - * AI_FMT_GET_IBITS() macro. - * - FBITS 7 bits set the number of fractional bits in the format - * - * - * A reference code snippet for usage is the test unit that uses this header: - * - * \include test/test_lcut_formats.cpp - * - */ - -/*! - * Format bitfields definition. NOTE: 7 MSB are masked off - * for (optional) atributes setting using flags. see @ref AI_FMT_FLAG_CONST that - * is used for marking a data as constant readonly - */ - -/* 1 bit field to identify floating point values*/ -#define _FMT_FLOAT_MASK (0x1) -#define _FMT_FLOAT_BITS (24) - -/*! 1 bit sign info */ -#define _FMT_SIGN_MASK (0x1) -#define _FMT_SIGN_BITS (23) - -/*! fractional bits field (i.e. for Q formats see @ref AI_FMT_Q) */ -#define _FMT_FBITS_MASK (0x7F) -#define _FMT_FBITS_BITS (0) -#define _FMT_FBITS_BIAS ((_FMT_FBITS_MASK+1) >> 1) - -/*! TOTAL number of bits (fractional+integer+sign) (excluded padding ones) */ -#define _FMT_BITS_MASK (0x7F) -#define _FMT_BITS_BITS (7) -#define _FMT_BITS_BIAS (0) - -/*! Padding bits for handling formats not aligned to multiples of 8 bits */ -#define _FMT_PMASK_MASK (0x7) -#define _FMT_PMASK_BITS (14) - -/*! bits reserved for identifying the family format, e.g. float, fixed-point..*/ -#define _FMT_TYPE_MASK (0xF) -#define _FMT_TYPE_BITS (17) - -#define _FMT_LDIV_MASK (0x3) -#define _FMT_LDIV_BITS (21) - - -/******************************************************************************/ -#define AI_FMT_OBJ(fmt_) ((ai_array_format)(fmt_)) - -/*! - * Only 25 LSB bits are used for storing actual format bits. 7 bits are reserved - * for format attributes, see @ref AI_FMT_FLAG_CONST flag - */ -#define AI_FMT_FLAG_BITS (25) -#define AI_FMT_MASK ((0x1<> AI_FMT_FLAG_BITS ) - -#define AI_FMT_SAME(fmt1_, fmt2_) \ - ( AI_FMT_GET(fmt1_) == AI_FMT_GET(fmt2_) ) - -#define _FMT_SET(val, mask, bits) AI_FMT_OBJ(((val)&(mask))<<(bits)) -#define _FMT_GET(fmt, mask, bits) ((AI_FMT_OBJ(fmt)>>(bits))&(mask)) - -#define AI_FMT_SET_FLOAT(val) _FMT_SET(val, _FMT_FLOAT_MASK, _FMT_FLOAT_BITS) -#define AI_FMT_GET_FLOAT(fmt) _FMT_GET(fmt, _FMT_FLOAT_MASK, _FMT_FLOAT_BITS) -#define AI_FMT_SET_SIGN(val) _FMT_SET(val, _FMT_SIGN_MASK, _FMT_SIGN_BITS) -#define AI_FMT_GET_SIGN(fmt) _FMT_GET(fmt, _FMT_SIGN_MASK, _FMT_SIGN_BITS) -#define AI_FMT_SET_PMASK(val) _FMT_SET(val, _FMT_PMASK_MASK, _FMT_PMASK_BITS) -#define AI_FMT_GET_PMASK(fmt) _FMT_GET(fmt, _FMT_PMASK_MASK, _FMT_PMASK_BITS) -#define AI_FMT_SET_TYPE(val) _FMT_SET(val, _FMT_TYPE_MASK, _FMT_TYPE_BITS) -#define AI_FMT_GET_TYPE(fmt) _FMT_GET(fmt, _FMT_TYPE_MASK, _FMT_TYPE_BITS) -#define AI_FMT_SET_LDIV(val) _FMT_SET(val, _FMT_LDIV_MASK, _FMT_LDIV_BITS) -#define AI_FMT_GET_LDIV(fmt) _FMT_GET(fmt, _FMT_LDIV_MASK, _FMT_LDIV_BITS) - -#define AI_FMT_SET_BITS(val) \ - _FMT_SET((val) + _FMT_BITS_BIAS, _FMT_BITS_MASK, _FMT_BITS_BITS) -#define AI_FMT_GET_BITS(fmt) \ - ((ai_i8)_FMT_GET(fmt, _FMT_BITS_MASK, _FMT_BITS_BITS) - _FMT_BITS_BIAS) -#define AI_FMT_SET_FBITS(val) \ - _FMT_SET((val) + _FMT_FBITS_BIAS, _FMT_FBITS_MASK, _FMT_FBITS_BITS) -#define AI_FMT_GET_FBITS(fmt) \ - ((ai_i8)_FMT_GET(fmt, _FMT_FBITS_MASK, _FMT_FBITS_BITS) - _FMT_FBITS_BIAS) - -/*! - * The total number of bits for a given format is supposed to be the sum of the - * bits + padding bits. This means that the number of integer bits is derived - * as follow: int_bits = bits - fbits (fractional bits) - 1 (for the sign) - */ -#define AI_FMT_GET_BITS_SIZE(fmt_) \ - AI_FMT_GET_BITS(fmt_) - -/*! Macro used to compute the integer bits for a format */ -#define AI_FMT_GET_IBITS(fmt_) \ - ((ai_i16)AI_FMT_GET_BITS(fmt_)-AI_FMT_GET_FBITS(fmt_)-AI_FMT_GET_SIGN(fmt_)) - -/*! ai_buffer format handlers section *****************************************/ - -#define AI_BUFFER_FMT_MASK_Q(fmt_) \ - ( AI_BUFFER_FMT_OBJ(fmt_) & 0xFFFFC000 ) - -#define AI_BUFFER_FMT_GET_Q(fmt_) \ - ( AI_BUFFER_FMT_MASK_Q(fmt_) | AI_BUFFER_FMT_SET_FBITS(0) | \ - AI_BUFFER_FMT_SET_FBITS(0) ) - -#define AI_BUFFER_FMT_SET_Q(bits_, fbits_) \ - AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, bits_, fbits_) - -#define AI_BUFFER_FMT_IS_Q(fmt_) \ - ( (AI_BUFFER_FMT_TYPE_Q==AI_BUFFER_FMT_GET_TYPE(fmt_)) && \ - (1==AI_BUFFER_FMT_GET_SIGN(fmt_)) ) - -#define AI_BUFFER_FMT_SET_UQ(bits_, fbits_) \ - AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, bits_, fbits_) - -#define AI_BUFFER_FMT_IS_UQ(fmt_) \ - ( (AI_BUFFER_FMT_TYPE_Q==AI_BUFFER_FMT_GET_TYPE(fmt_)) && \ - (0==AI_BUFFER_FMT_GET_SIGN(fmt_)) ) - -/*! Q ai_array format handlers ************************************************/ -#define AI_ARRAY_FMT_Q(bits_, fbits_) \ - ( AI_FMT_MASK_Q(AI_ARRAY_FORMAT_Q) | AI_FMT_SET_BITS(bits_) | AI_FMT_SET_FBITS(fbits_) ) - -#define AI_ARRAY_FMT_SET_Q(bits_, fbits_) \ - AI_ARRAY_FMT_Q(bits_, fbits_) - -#define AI_ARRAY_FMT_IS_Q(fmt_) \ - ( AI_FMT_GET(AI_FMT_MASK_Q(AI_ARRAY_FORMAT_Q))==AI_FMT_GET(AI_FMT_MASK_Q(fmt_)) ) - -#define AI_ARRAY_FMT_UQ(bits_, fbits_) \ - ( AI_FMT_MASK_Q(AI_ARRAY_FORMAT_UQ) | AI_FMT_SET_BITS(bits_) | AI_FMT_SET_FBITS(fbits_) ) - -#define AI_ARRAY_FMT_SET_UQ(bits_, fbits_) \ - AI_ARRAY_FMT_UQ(bits_, fbits_) - -#define AI_ARRAY_FMT_IS_UQ(fmt_) \ - ( AI_FMT_GET(AI_FMT_MASK_Q(AI_ARRAY_FORMAT_UQ))==AI_FMT_GET(AI_FMT_MASK_Q(fmt_)) ) - -AI_DEPRECATED -/* Alias for AI_ARRAY_FMT_SET_Q */ -#define AI_ARRAY_FMT_SET_SQ(bits_, fbits_) \ - AI_ARRAY_FMT_SET_Q(bits_, fbits_) - -AI_DEPRECATED -/* Alias for AI_ARRAY_FMT_IS_Q */ -#define AI_ARRAY_FMT_IS_SQ(fmt_) \ - AI_ARRAY_FMT_IS_Q(fmt_) - -/*! ai_array section **********************************************************/ -#define AI_ARRAY_FMT_ENTRY(name_) \ - AI_CONCAT(AI_ARRAY_FORMAT_, name_) - -#define AI_ARRAY_FMT_NAME(fmt_) \ - ai_array_fmt_name(fmt_) - -#define AI_ARRAY_FMT_VALID(fmt_) \ - ai_array_fmt_valid(fmt_) - -#define AI_ARRAY_FMT_EXPORTED(fmt_) \ - ai_array_fmt_exported(fmt_) - -#define AI_ARRAY_FMT_GET_FORMATS(formats_) \ - ai_array_fmt_get_formats(formats_) - -#define AI_ARRAY_TO_BUFFER_FMT(fmt_) \ - ai_array_to_buffer_fmt(fmt_) - -#define AI_ARRAY_GET_BYTE_SIZE(fmt_, count_) \ - ai_array_get_byte_size(fmt_, count_) - -#define AI_ARRAY_GET_DATA_BYTE_SIZE(fmt_, count_) \ - ai_array_get_data_byte_size(fmt_, count_) - -#define AI_ARRAY_GET_ELEMS_FROM_SIZE(fmt_, size_) \ - ai_array_get_elems_from_size(fmt_, size_) - - -AI_API_DECLARE_BEGIN - -/*! - * @typedef ai_array_format - * @ingroup ai_datatypes_format - * @brief Generic Data Format Specifier for @ref ai_array (32bits packed info) - */ -typedef int32_t ai_array_format; - -/*! - * @enum internal data format enums - * @ingroup ai_datatypes_format - * @brief Generic Data Format Specifier (32bits packed info) - */ -typedef enum { -#define FMT_ENTRY(exp_, name_, type_id_, sign_bit_, float_bit_, \ - pmask_, bits_, fbits_, ldiv_bits_) \ - AI_ARRAY_FMT_ENTRY(name_) = (AI_FMT_SET_FLOAT(float_bit_) | \ - AI_FMT_SET_SIGN(sign_bit_) | \ - AI_FMT_SET_BITS(bits_) | \ - AI_FMT_SET_FBITS(fbits_) | \ - AI_FMT_SET_PMASK(pmask_) | \ - AI_FMT_SET_TYPE(type_id_) | \ - AI_FMT_SET_LDIV(ldiv_bits_)), -#include "formats_list.h" -} ai_array_format_entry; - -/*! - * @brief Get a human readable string from the format ID value - * @ingroup ai_datatypes_format - * @param[in] type the @ref ai_array_format to print out - * @return a string with a human readable name of the format - */ -AI_INTERNAL_API -const char* ai_array_fmt_name(const ai_array_format type); - -/*! - * @brief Check if @ref ai_array_format is a exportable to an @ref ai_buffer_format - * @ingroup ai_datatypes_format - * @param[in] type the ai_array_format to check - * @return true if the format is exported, false otherwise - */ -AI_INTERNAL_API -ai_bool ai_array_fmt_exported(const ai_array_format type); - -/*! - * @brief Check if @ref ai_array_format is a valid format present in the list of - * supported formats - * @ingroup ai_datatypes_format - * @param[in] type the ai_array_format to check - * @return true if the format is valid, false otherwise - */ -AI_INTERNAL_API -ai_bool ai_array_fmt_valid(const ai_array_format type); - -/*! - * @brief Get the complete list of supported @ref ai_array_format formats - * @ingroup ai_datatypes_format - * @param[out] formats a pointer to an array withj all supported formats listed - * @return the number of supported formats - */ -AI_INTERNAL_API -ai_size ai_array_fmt_get_formats(const ai_array_format** formats); - -/*! ai_buffer section ********************************************************* - * Only 25 LSB bits are used for storing actual format bits. 7 bits are reserved - * for format atrtributes, see @ref AI_FMT_FLAG_CONST flag - */ - -#define AI_BUFFER_FMT_ENTRY(name_) \ - AI_CONCAT(AI_BUFFER_FORMAT_, name_) - -#define AI_BUFFER_FMT_NAME(type_) \ - ai_buffer_fmt_name(type_) - -#define AI_BUFFER_FMT_VALID(type_) \ - ai_buffer_fmt_valid(type_) - -#define AI_BUFFER_FMT_GET_FORMATS(formats_) \ - ai_buffer_fmt_get_formats(formats_) - -#define AI_BUFFER_TO_ARRAY_FMT(fmt_) \ - ai_buffer_to_array_fmt(fmt_) - -#define AI_BUFFER_GET_BITS_SIZE(fmt) \ - AI_ARRAY_GET_BITS_SIZE(AI_BUFFER_TO_ARRAY_FMT(fmt)) - - -/*! - * @brief Get a human readable string from the format ID value - * @ingroup ai_datatypes_format - * @param[in] type the @ref ai_buffer_format to print out - * @return a string with a human readable name of the format - */ -AI_INTERNAL_API -const char* ai_buffer_fmt_name( - const ai_buffer_format type); - -/*! - * @brief Check if @ref ai_buffer_format is a valid format present in the list - * of supported formats - * @ingroup ai_datatypes_format - * @param[in] type the @ref ai_buffer_format to check - * @return true if the format is valid, false otherwise - */ -AI_INTERNAL_API -ai_bool ai_buffer_fmt_valid( - const ai_buffer_format type); - -/*! - * @brief Get the complete list of supported @ref ai_buffer_format formats - * @ingroup ai_datatypes_format - * @param[out] formats a pointer to an array with all supported formats listed - * @return the number of supported formats - */ -AI_INTERNAL_API -ai_size ai_buffer_fmt_get_formats( - const ai_buffer_format** formats); - -/*! Conversions section *******************************************************/ -/*! - * @brief Convert from ai_array_format to ai_buffer_format. - * @ingroup ai_datatypes_format - * @param fmt the input ai_array_format to convert - * @return the converted format as a ai_buffer_format - */ -AI_INTERNAL_API -ai_buffer_format ai_array_to_buffer_fmt( - const ai_array_format fmt); - -/*! - * @brief Convert from ai_buffer_format to ai_array_format. - * @ingroup ai_datatypes_format - * @param fmt the input ai_buffer_format to convert - * @return the converted format as a ai_array_format - */ -AI_INTERNAL_API -ai_array_format ai_buffer_to_array_fmt( - const ai_buffer_format fmt); - -/** helpers section ***********************************************************/ -/*! - * @brief Computes the size in bytes given an ai_array_format and number of - * array elements. - * @details This routine computes from the number of elements of the array its - * size in bytes. If the array is referred by a tensor structure, it is the task - * of the latter to handle per-dimension padding (e.g. to align odd rows in a - * 4-bit matrix. At array level the padding elements MUST be included in the - * number of elements. - * @ingroup ai_datatypes_format - * @param[in] fmt the input array format as an ai_array_format - * @param[in] count the number of elements stored in the data array - * @return the size in bytes of the array given the specific format and number - * of elements (including padding elements) - */ -AI_INTERNAL_API -ai_size ai_array_get_byte_size( - const ai_array_format fmt, const ai_size count); - -/*! - * @brief Computes the size in bytes given an ai_array_format and number of - * array elements of the data fields (e.g. LUT table size excluded). - * @details This routine computes from the number of elements of the array its - * size in bytes. If the array is referred by a tensor structure, it is the task - * of the latter to handle per-dimension padding (e.g. to align odd rows in a - * 4-bit matrix. At array level the padding elements MUST be included in the - * number of elements. - * @ingroup ai_datatypes_format - * @param[in] fmt the input array format as an ai_array_format - * @param[in] count the number of elements stored in the data array - * @return the size in bytes of the array given the specific format and number - * of elements (including padding elements) - */ -AI_INTERNAL_API -ai_size ai_array_get_data_byte_size( - const ai_array_format fmt, const ai_size count); - -/*! - * @brief Computes the number of elements from ai_array_format and - * the size in byte of the array. - * @ingroup ai_datatypes_format - * @param fmt the input array format as an ai_array_format - * @param size the size in bytes of the array - * @return the number of elements that could be stored given the format - */ -AI_INTERNAL_API -ai_size ai_array_get_elems_from_size( - const ai_array_format fmt, const ai_size byte_size); - -AI_API_DECLARE_END - -#endif /*AI_DATATYPES_FORMAT_H*/ +/** + ****************************************************************************** + * @file ai_datatypes_format.h + * @author AST Embedded Analytics Research Platform + * @brief Definitions of AI platform private format handling routines + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef AI_DATATYPES_FORMAT_H +#define AI_DATATYPES_FORMAT_H + +#include "ai_platform.h" +#include "ai_datatypes_defines.h" + + +/*! + * @defgroup ai_datatypes_format Definiton and Macro of array and buffer formats + * @brief Type definition and implementation of internal @ref ai_array and + * @ref ai_buffer formats. + * @details The library handles 2 different kind of formats: an internal format + * that is part of the @ref ai_array struct that is a packed 32bit representation + * of the format attributes, and a public format (used in public APIs) associated + * with @ref ai_buffer struct , defined as enum in @ref ai_platform.h, + * that is just an enum type. Converters are provided in this header file to + * convert from one format representation to another. + * Some MSB bits are reserved in both formats to code some bit flag useful to + * declare some special attribute. Three flags are actually implemented in both + * formats: the @ref AI_BUFFER_FMT_FLAG_CONST and @ref AI_FMT_FLAG_CONST used + * to tag read-only memory buffers, @ref AI_BUFFER_FMT_FLAG_STATIC and + * @ref AI_FMT_FLAG_STATIC to mark statically allocated memory buffers and + * @ref AI_FMT_FLAG_SCRATCH_BUFFER to tag temporary scratch buffers. + * All the formats are declared in a proper tuple organize table header named + * @ref format_lists.h that enumerates all the formats available for the library. + * A new format could be added easily by adding a new FMY_ENTRY() as required. + * The preprocessor automatically generates the code for the handling of the + * format according to this tuples entry. A rational for the methodology could + * be found here: + * - https://codecraft.co/2012/10/29/how-enums-spread-disease-and-how-to-cure-it/ + * + * The 32bits internal format fields are organized as follows: + * + * MSB LSB + * 31 25 24 23 21 17 14 7 0 + * /---------------------------------------------------------------------------/ + * / ATTR. FLAGS | FLOAT | SIGN | LDIV | TYPE | PMASK | BITS | FBITS / + * /---------------------------------------------------------------------------/ + * Where: + * - FLAGS: is the reserved bits to store additional format attributes (e.g. + * I/O / STATIC flags. etc.) + * - FLOAT: 1 bit mark the format as floating point type + * - SIGN : 1 bit mark the format as signed type + * - LDIV : 2 bits is a log2 value that is used to compute elements size + * with some special format such as the compressed ones. It is a shift + * factor usually set to zero + * - TYPE : 4 bits mark the format "family" type. Actually 5 families are coded, + * @ref AI_FMT_FLOAT (float types) + * @ref AI_FMT_Q (fixed-point types in Qm.n format) + * @ref AI_FMT_BOOL (boolean type) + * @ref AI_FMT_LUT4 (compressed lookup 16 formats) + * @ref AI_FMT_LUT8 (compressed lookup 256 formats) + * - PMASK 3 bits padding mask used to set the optional dimension for padding + * to handle special aligned formats/ E.g. a 1 bit format + * Usually this is set to 0x0 + * - BITS 7 bits set the total number of bits of the element, padding bits + * excluded. The bits are thus = sign bit + fractional bits + integer bits + * The number of integer bits could thus be known using the @ref + * AI_FMT_GET_IBITS() macro. + * - FBITS 7 bits set the number of fractional bits in the format + * + * + * A reference code snippet for usage is the test unit that uses this header: + * + * \include test/test_lcut_formats.cpp + * + */ + +/*! + * Format bitfields definition. NOTE: 7 MSB are masked off + * for (optional) atributes setting using flags. see @ref AI_FMT_FLAG_CONST that + * is used for marking a data as constant readonly + */ + +/* 1 bit field to identify floating point values*/ +#define _FMT_FLOAT_MASK (0x1) +#define _FMT_FLOAT_BITS (24) + +/*! 1 bit sign info */ +#define _FMT_SIGN_MASK (0x1) +#define _FMT_SIGN_BITS (23) + +/*! fractional bits field (i.e. for Q formats see @ref AI_FMT_Q) */ +#define _FMT_FBITS_MASK (0x7F) +#define _FMT_FBITS_BITS (0) +#define _FMT_FBITS_BIAS ((_FMT_FBITS_MASK+1) >> 1) + +/*! TOTAL number of bits (fractional+integer+sign) (excluded padding ones) */ +#define _FMT_BITS_MASK (0x7F) +#define _FMT_BITS_BITS (7) +#define _FMT_BITS_BIAS (0) + +/*! Padding bits for handling formats not aligned to multiples of 8 bits */ +#define _FMT_PMASK_MASK (0x7) +#define _FMT_PMASK_BITS (14) + +/*! bits reserved for identifying the family format, e.g. float, fixed-point..*/ +#define _FMT_TYPE_MASK (0xF) +#define _FMT_TYPE_BITS (17) + +#define _FMT_LDIV_MASK (0x3) +#define _FMT_LDIV_BITS (21) + + +/******************************************************************************/ +#define AI_FMT_OBJ(fmt_) ((ai_array_format)(fmt_)) + +/*! + * Only 25 LSB bits are used for storing actual format bits. 7 bits are reserved + * for format attributes, see @ref AI_FMT_FLAG_CONST flag + */ +#define AI_FMT_FLAG_BITS (25) +#define AI_FMT_MASK ((0x1<> AI_FMT_FLAG_BITS ) + +#define AI_FMT_SAME(fmt1_, fmt2_) \ + ( AI_FMT_GET(fmt1_) == AI_FMT_GET(fmt2_) ) + +#define _FMT_SET(val, mask, bits) AI_FMT_OBJ(((val)&(mask))<<(bits)) +#define _FMT_GET(fmt, mask, bits) ((AI_FMT_OBJ(fmt)>>(bits))&(mask)) + +#define AI_FMT_SET_FLOAT(val) _FMT_SET(val, _FMT_FLOAT_MASK, _FMT_FLOAT_BITS) +#define AI_FMT_GET_FLOAT(fmt) _FMT_GET(fmt, _FMT_FLOAT_MASK, _FMT_FLOAT_BITS) +#define AI_FMT_SET_SIGN(val) _FMT_SET(val, _FMT_SIGN_MASK, _FMT_SIGN_BITS) +#define AI_FMT_GET_SIGN(fmt) _FMT_GET(fmt, _FMT_SIGN_MASK, _FMT_SIGN_BITS) +#define AI_FMT_SET_PMASK(val) _FMT_SET(val, _FMT_PMASK_MASK, _FMT_PMASK_BITS) +#define AI_FMT_GET_PMASK(fmt) _FMT_GET(fmt, _FMT_PMASK_MASK, _FMT_PMASK_BITS) +#define AI_FMT_SET_TYPE(val) _FMT_SET(val, _FMT_TYPE_MASK, _FMT_TYPE_BITS) +#define AI_FMT_GET_TYPE(fmt) _FMT_GET(fmt, _FMT_TYPE_MASK, _FMT_TYPE_BITS) +#define AI_FMT_SET_LDIV(val) _FMT_SET(val, _FMT_LDIV_MASK, _FMT_LDIV_BITS) +#define AI_FMT_GET_LDIV(fmt) _FMT_GET(fmt, _FMT_LDIV_MASK, _FMT_LDIV_BITS) + +#define AI_FMT_SET_BITS(val) \ + _FMT_SET((val) + _FMT_BITS_BIAS, _FMT_BITS_MASK, _FMT_BITS_BITS) +#define AI_FMT_GET_BITS(fmt) \ + ((ai_i8)_FMT_GET(fmt, _FMT_BITS_MASK, _FMT_BITS_BITS) - _FMT_BITS_BIAS) +#define AI_FMT_SET_FBITS(val) \ + _FMT_SET((val) + _FMT_FBITS_BIAS, _FMT_FBITS_MASK, _FMT_FBITS_BITS) +#define AI_FMT_GET_FBITS(fmt) \ + ((ai_i8)_FMT_GET(fmt, _FMT_FBITS_MASK, _FMT_FBITS_BITS) - _FMT_FBITS_BIAS) + +/*! + * The total number of bits for a given format is supposed to be the sum of the + * bits + padding bits. This means that the number of integer bits is derived + * as follow: int_bits = bits - fbits (fractional bits) - 1 (for the sign) + */ +#define AI_FMT_GET_BITS_SIZE(fmt_) \ + AI_FMT_GET_BITS(fmt_) + +/*! Macro used to compute the integer bits for a format */ +#define AI_FMT_GET_IBITS(fmt_) \ + ((ai_i16)AI_FMT_GET_BITS(fmt_)-AI_FMT_GET_FBITS(fmt_)-AI_FMT_GET_SIGN(fmt_)) + +/*! ai_buffer format handlers section *****************************************/ + +#define AI_BUFFER_FMT_MASK_Q(fmt_) \ + ( AI_BUFFER_FMT_OBJ(fmt_) & 0xFFFFC000 ) + +#define AI_BUFFER_FMT_GET_Q(fmt_) \ + ( AI_BUFFER_FMT_MASK_Q(fmt_) | AI_BUFFER_FMT_SET_FBITS(0) | \ + AI_BUFFER_FMT_SET_FBITS(0) ) + +#define AI_BUFFER_FMT_SET_Q(bits_, fbits_) \ + AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, bits_, fbits_) + +#define AI_BUFFER_FMT_IS_Q(fmt_) \ + ( (AI_BUFFER_FMT_TYPE_Q==AI_BUFFER_FMT_GET_TYPE(fmt_)) && \ + (1==AI_BUFFER_FMT_GET_SIGN(fmt_)) ) + +#define AI_BUFFER_FMT_SET_UQ(bits_, fbits_) \ + AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, bits_, fbits_) + +#define AI_BUFFER_FMT_IS_UQ(fmt_) \ + ( (AI_BUFFER_FMT_TYPE_Q==AI_BUFFER_FMT_GET_TYPE(fmt_)) && \ + (0==AI_BUFFER_FMT_GET_SIGN(fmt_)) ) + +/*! Q ai_array format handlers ************************************************/ +#define AI_ARRAY_FMT_Q(bits_, fbits_) \ + ( AI_FMT_MASK_Q(AI_ARRAY_FORMAT_Q) | AI_FMT_SET_BITS(bits_) | AI_FMT_SET_FBITS(fbits_) ) + +#define AI_ARRAY_FMT_SET_Q(bits_, fbits_) \ + AI_ARRAY_FMT_Q(bits_, fbits_) + +#define AI_ARRAY_FMT_IS_Q(fmt_) \ + ( AI_FMT_GET(AI_FMT_MASK_Q(AI_ARRAY_FORMAT_Q))==AI_FMT_GET(AI_FMT_MASK_Q(fmt_)) ) + +#define AI_ARRAY_FMT_UQ(bits_, fbits_) \ + ( AI_FMT_MASK_Q(AI_ARRAY_FORMAT_UQ) | AI_FMT_SET_BITS(bits_) | AI_FMT_SET_FBITS(fbits_) ) + +#define AI_ARRAY_FMT_SET_UQ(bits_, fbits_) \ + AI_ARRAY_FMT_UQ(bits_, fbits_) + +#define AI_ARRAY_FMT_IS_UQ(fmt_) \ + ( AI_FMT_GET(AI_FMT_MASK_Q(AI_ARRAY_FORMAT_UQ))==AI_FMT_GET(AI_FMT_MASK_Q(fmt_)) ) + +AI_DEPRECATED +/* Alias for AI_ARRAY_FMT_SET_Q */ +#define AI_ARRAY_FMT_SET_SQ(bits_, fbits_) \ + AI_ARRAY_FMT_SET_Q(bits_, fbits_) + +AI_DEPRECATED +/* Alias for AI_ARRAY_FMT_IS_Q */ +#define AI_ARRAY_FMT_IS_SQ(fmt_) \ + AI_ARRAY_FMT_IS_Q(fmt_) + +/*! ai_array section **********************************************************/ +#define AI_ARRAY_FMT_ENTRY(name_) \ + AI_CONCAT(AI_ARRAY_FORMAT_, name_) + +#define AI_ARRAY_FMT_NAME(fmt_) \ + ai_array_fmt_name(fmt_) + +#define AI_ARRAY_FMT_VALID(fmt_) \ + ai_array_fmt_valid(fmt_) + +#define AI_ARRAY_FMT_EXPORTED(fmt_) \ + ai_array_fmt_exported(fmt_) + +#define AI_ARRAY_FMT_GET_FORMATS(formats_) \ + ai_array_fmt_get_formats(formats_) + +#define AI_ARRAY_TO_BUFFER_FMT(fmt_) \ + ai_array_to_buffer_fmt(fmt_) + +#define AI_ARRAY_GET_BYTE_SIZE(fmt_, count_) \ + ai_array_get_byte_size(fmt_, count_) + +#define AI_ARRAY_GET_DATA_BYTE_SIZE(fmt_, count_) \ + ai_array_get_data_byte_size(fmt_, count_) + +#define AI_ARRAY_GET_ELEMS_FROM_SIZE(fmt_, size_) \ + ai_array_get_elems_from_size(fmt_, size_) + + +AI_API_DECLARE_BEGIN + +/*! + * @typedef ai_array_format + * @ingroup ai_datatypes_format + * @brief Generic Data Format Specifier for @ref ai_array (32bits packed info) + */ +typedef int32_t ai_array_format; + +/*! + * @enum internal data format enums + * @ingroup ai_datatypes_format + * @brief Generic Data Format Specifier (32bits packed info) + */ +typedef enum { +#define FMT_ENTRY(exp_, name_, type_id_, sign_bit_, float_bit_, \ + pmask_, bits_, fbits_, ldiv_bits_) \ + AI_ARRAY_FMT_ENTRY(name_) = (AI_FMT_SET_FLOAT(float_bit_) | \ + AI_FMT_SET_SIGN(sign_bit_) | \ + AI_FMT_SET_BITS(bits_) | \ + AI_FMT_SET_FBITS(fbits_) | \ + AI_FMT_SET_PMASK(pmask_) | \ + AI_FMT_SET_TYPE(type_id_) | \ + AI_FMT_SET_LDIV(ldiv_bits_)), +#include "formats_list.h" +} ai_array_format_entry; + +/*! + * @brief Get a human readable string from the format ID value + * @ingroup ai_datatypes_format + * @param[in] type the @ref ai_array_format to print out + * @return a string with a human readable name of the format + */ +AI_INTERNAL_API +const char* ai_array_fmt_name(const ai_array_format type); + +/*! + * @brief Check if @ref ai_array_format is a exportable to an @ref ai_buffer_format + * @ingroup ai_datatypes_format + * @param[in] type the ai_array_format to check + * @return true if the format is exported, false otherwise + */ +AI_INTERNAL_API +ai_bool ai_array_fmt_exported(const ai_array_format type); + +/*! + * @brief Check if @ref ai_array_format is a valid format present in the list of + * supported formats + * @ingroup ai_datatypes_format + * @param[in] type the ai_array_format to check + * @return true if the format is valid, false otherwise + */ +AI_INTERNAL_API +ai_bool ai_array_fmt_valid(const ai_array_format type); + +/*! + * @brief Get the complete list of supported @ref ai_array_format formats + * @ingroup ai_datatypes_format + * @param[out] formats a pointer to an array withj all supported formats listed + * @return the number of supported formats + */ +AI_INTERNAL_API +ai_size ai_array_fmt_get_formats(const ai_array_format** formats); + +/*! ai_buffer section ********************************************************* + * Only 25 LSB bits are used for storing actual format bits. 7 bits are reserved + * for format atrtributes, see @ref AI_FMT_FLAG_CONST flag + */ + +#define AI_BUFFER_FMT_ENTRY(name_) \ + AI_CONCAT(AI_BUFFER_FORMAT_, name_) + +#define AI_BUFFER_FMT_NAME(type_) \ + ai_buffer_fmt_name(type_) + +#define AI_BUFFER_FMT_VALID(type_) \ + ai_buffer_fmt_valid(type_) + +#define AI_BUFFER_FMT_GET_FORMATS(formats_) \ + ai_buffer_fmt_get_formats(formats_) + +#define AI_BUFFER_TO_ARRAY_FMT(fmt_) \ + ai_buffer_to_array_fmt(fmt_) + +#define AI_BUFFER_GET_BITS_SIZE(fmt) \ + AI_ARRAY_GET_BITS_SIZE(AI_BUFFER_TO_ARRAY_FMT(fmt)) + + +/*! + * @brief Get a human readable string from the format ID value + * @ingroup ai_datatypes_format + * @param[in] type the @ref ai_buffer_format to print out + * @return a string with a human readable name of the format + */ +AI_INTERNAL_API +const char* ai_buffer_fmt_name( + const ai_buffer_format type); + +/*! + * @brief Check if @ref ai_buffer_format is a valid format present in the list + * of supported formats + * @ingroup ai_datatypes_format + * @param[in] type the @ref ai_buffer_format to check + * @return true if the format is valid, false otherwise + */ +AI_INTERNAL_API +ai_bool ai_buffer_fmt_valid( + const ai_buffer_format type); + +/*! + * @brief Get the complete list of supported @ref ai_buffer_format formats + * @ingroup ai_datatypes_format + * @param[out] formats a pointer to an array with all supported formats listed + * @return the number of supported formats + */ +AI_INTERNAL_API +ai_size ai_buffer_fmt_get_formats( + const ai_buffer_format** formats); + +/*! Conversions section *******************************************************/ +/*! + * @brief Convert from ai_array_format to ai_buffer_format. + * @ingroup ai_datatypes_format + * @param fmt the input ai_array_format to convert + * @return the converted format as a ai_buffer_format + */ +AI_INTERNAL_API +ai_buffer_format ai_array_to_buffer_fmt( + const ai_array_format fmt); + +/*! + * @brief Convert from ai_buffer_format to ai_array_format. + * @ingroup ai_datatypes_format + * @param fmt the input ai_buffer_format to convert + * @return the converted format as a ai_array_format + */ +AI_INTERNAL_API +ai_array_format ai_buffer_to_array_fmt( + const ai_buffer_format fmt); + +/** helpers section ***********************************************************/ +/*! + * @brief Computes the size in bytes given an ai_array_format and number of + * array elements. + * @details This routine computes from the number of elements of the array its + * size in bytes. If the array is referred by a tensor structure, it is the task + * of the latter to handle per-dimension padding (e.g. to align odd rows in a + * 4-bit matrix. At array level the padding elements MUST be included in the + * number of elements. + * @ingroup ai_datatypes_format + * @param[in] fmt the input array format as an ai_array_format + * @param[in] count the number of elements stored in the data array + * @return the size in bytes of the array given the specific format and number + * of elements (including padding elements) + */ +AI_INTERNAL_API +ai_size ai_array_get_byte_size( + const ai_array_format fmt, const ai_size count); + +/*! + * @brief Computes the size in bytes given an ai_array_format and number of + * array elements of the data fields (e.g. LUT table size excluded). + * @details This routine computes from the number of elements of the array its + * size in bytes. If the array is referred by a tensor structure, it is the task + * of the latter to handle per-dimension padding (e.g. to align odd rows in a + * 4-bit matrix. At array level the padding elements MUST be included in the + * number of elements. + * @ingroup ai_datatypes_format + * @param[in] fmt the input array format as an ai_array_format + * @param[in] count the number of elements stored in the data array + * @return the size in bytes of the array given the specific format and number + * of elements (including padding elements) + */ +AI_INTERNAL_API +ai_size ai_array_get_data_byte_size( + const ai_array_format fmt, const ai_size count); + +/*! + * @brief Computes the number of elements from ai_array_format and + * the size in byte of the array. + * @ingroup ai_datatypes_format + * @param fmt the input array format as an ai_array_format + * @param size the size in bytes of the array + * @return the number of elements that could be stored given the format + */ +AI_INTERNAL_API +ai_size ai_array_get_elems_from_size( + const ai_array_format fmt, const ai_size byte_size); + +AI_API_DECLARE_END + +#endif /*AI_DATATYPES_FORMAT_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes_internal.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes_internal.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes_internal.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes_internal.h index 16ecc714..a115b559 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes_internal.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_datatypes_internal.h @@ -1,417 +1,417 @@ -/** - ****************************************************************************** - * @file ai_datatypes_internal.h - * @author AST Embedded Analytics Research Platform - * @brief Definitions of AI platform private APIs types - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef AI_DATATYPES_INTERNAL_H -#define AI_DATATYPES_INTERNAL_H - -#include "ai_datatypes.h" -#include "ai_datatypes_defines.h" - -/*! - * @defgroup datatypes_internal Internal Datatypes - * @brief Data structures used internally to implement neural networks - * - * The layers are defined as structs; a generic layer type defines the basic - * layer parameters and type-specific parameters are handled by specializations - * implemented as a C union. The layers keep also a pointer to the parent - * network and the next layer in the network. - * The input, output and parameters are tensor with an hard-coded maximum - * dimension of 4. Tensors are floating point arrays with a notion of size. - * The network is a linked list of layers, and thus it stores only the pointer - * to the first layer. - */ - -/*! - * @section Offsets - * @ingroup datatypes_internal - * Macros to handle (byte) stride addressing on tensors. The `AI_PTR` macro - * is used to always cast a pointer to byte array. The macros `AI_OFFSET_X` are - * used to compute (byte) offsets of respectively adjacents row elements, col - * elements, channel elements and `channel_in` elements. - * @{ - */ - -/*! AI_STORAGE_KLASS SECTION ************************************/ -#define AI_STORAGE_KLASS_TYPE(s_) \ - ( (s_)->type ) - -#define AI_STORAGE_KLASS_SIZE(s_) \ - ( (s_)->size ) - -#define AI_STORAGE_KLASS_DATA(s_, type_) \ - ( (type_*)((s_)->data) ) - -#define AI_STORAGE_KLASS_COPY(dst_, dst_type_, src_, src_type_) \ -{ \ - AI_ASSERT(AI_STORAGE_KLASS_SIZE(src_)>=AI_STORAGE_KLASS_SIZE(dst_)) \ - AI_STORAGE_KLASS_SIZE(dst_) = AI_STORAGE_KLASS_SIZE(src_); \ - for (ai_size i=0; i AI_SHAPE_DEPTH) \ - ? AI_SHAPE_ELEM((shape_), AI_SHAPE_DEPTH) : 1) -#define AI_SHAPE_E(shape_) ((AI_SHAPE_SIZE((shape_)) > AI_SHAPE_EXTENSION) \ - ? AI_SHAPE_ELEM((shape_), AI_SHAPE_EXTENSION) : 1) -#define AI_SHAPE_T(shape_) AI_SHAPE_ELEM((shape_), AI_SHAPE_TIME) - -#define AI_CONV_SHAPE_H AI_SHAPE_W -#define AI_CONV_SHAPE_W AI_SHAPE_CH -#define AI_CONV_SHAPE_CH AI_SHAPE_H -#define AI_CONV_SHAPE_IN_CH AI_SHAPE_IN_CH - -/*! AI_STRIDES SECTION ***********************************/ -#define AI_STRIDE_2D_H(stride_) \ - AI_STRIDE_ELEM((stride_), AI_SHAPE_2D_HEIGHT) - -#define AI_STRIDE_2D_W(stride_) \ - AI_STRIDE_ELEM((stride_), AI_SHAPE_2D_WIDTH) - -#define AI_STRIDE_ELEM(stride_, pos_) \ - AI_STORAGE_KLASS_DATA(stride_, ai_stride_dimension)[pos_] - -#define AI_STRIDE_GET_ELEM(stride_, pos_) \ - (((pos_) < AI_STRIDE_SIZE(stride_)) ? AI_STRIDE_ELEM(stride_, pos_) : 0) - -#define AI_STRIDE_SET_ELEM(stride_, pos_, val_) \ - if ((pos_) < AI_STRIDE_SIZE(stride_)) AI_STRIDE_ELEM(stride_, pos_) = (val_); - -#define AI_STRIDE_TYPE(stride_) \ - AI_STORAGE_KLASS_TYPE(stride_) - -#define AI_STRIDE_SIZE(stride_) \ - AI_STORAGE_KLASS_SIZE(stride_) - -#define AI_STRIDE_CLONE(dst_, src_) \ - AI_STORAGE_KLASS_COPY(dst_, ai_stride_dimension, src_, ai_stride_dimension) - -#define AI_STRIDE_BCAST_CLONE(dst_, src_) \ -{ \ - for (ai_size i=0; i= 5) ? AI_STRIDE_ELEM((stride), AI_SHAPE_DEPTH) : 0) -#define AI_STRIDE_E(stride) ((AI_STRIDE_SIZE((stride)) == 6) ? AI_STRIDE_ELEM((stride), AI_SHAPE_EXTENSION) : 0) -#define AI_STRIDE_T(stride) AI_STRIDE_ELEM((stride), AI_SHAPE_TIME) - -#define AI_STRIDE_SET_H(stride, val) AI_STRIDE_SET_ELEM((stride), AI_SHAPE_HEIGHT, val) -#define AI_STRIDE_SET_W(stride, val) AI_STRIDE_SET_ELEM((stride), AI_SHAPE_WIDTH, val) -#define AI_STRIDE_SET_CH(stride, val) AI_STRIDE_SET_ELEM((stride), AI_SHAPE_CHANNEL, val) -#define AI_STRIDE_SET_IN_CH(stride, val) AI_STRIDE_SET_ELEM((stride), AI_SHAPE_IN_CHANNEL, val) -#define AI_STRIDE_SET_D(stride, val) if (AI_STRIDE_SIZE((stride)) >= 5) AI_STRIDE_SET_ELEM((stride), AI_SHAPE_DEPTH, val) -#define AI_STRIDE_SET_E(stride, val) if (AI_STRIDE_SIZE((stride)) == 6) AI_STRIDE_SET_ELEM((stride), AI_SHAPE_EXTENSION, val) - -/*! AI_TENSORS SECTION ***********************************/ -#define AI_TENSOR_KLASS(tensor_) \ - ((tensor_) ? (tensor_)->klass : NULL) - -#define AI_TENSOR_SHAPE(tensor_) \ - (&((tensor_)->shape)) - -#define AI_TENSOR_STRIDE(tensor_) \ - (&((tensor_)->stride)) - -#define AI_TENSOR_INFO(tensor_) \ - (&((tensor_)->info)) - -#define AI_TENSOR_ARRAY(tensor_) \ - ((tensor_) ? (tensor_)->data : NULL) - -#define AI_TENSOR_ID(tensor_) \ - ((tensor_) ? AI_TENSOR_INFO(tensor_)->id : 0) - -#define AI_TENSOR_FLAGS(tensor_) \ - ((tensor_) ? AI_TENSOR_INFO(tensor_)->flags : 0) - -#define AI_TENSOR_DATA_SIZE(tensor_) \ - ((tensor_) ? AI_TENSOR_INFO(tensor_)->data_size : 0) - -/*! AI_OFFSETS SECTION ***********************************/ -//#define AI_OFFSET_BATCH(b, stride) ((ai_ptr_offset)(b) * AI_STRIDE_BATCH(stride)) -#define AI_OFFSET_H(y, stride) ((ai_ptr_offset)(y) * AI_STRIDE_H(stride)) -#define AI_OFFSET_W(x, stride) ((ai_ptr_offset)(x) * AI_STRIDE_W(stride)) -#define AI_OFFSET_CH(ch, stride) ((ai_ptr_offset)(ch) * AI_STRIDE_CH(stride)) -#define AI_OFFSET_IN_CH(in_ch, stride) ((ai_ptr_offset)(in_ch) * \ - AI_STRIDE_IN_CH(stride)) -#define AI_OFFSET_D(d, stride) ((ai_ptr_offset)(d) * AI_STRIDE_D(stride)) -#define AI_OFFSET_E(e, stride) ((ai_ptr_offset)(e) * AI_STRIDE_E(stride)) - -#define AI_OFFSET_5D(y, x, d, e, ch, stride) ( \ - AI_OFFSET_H((y), (stride)) + AI_OFFSET_W((x), (stride)) + \ - AI_OFFSET_D((d), (stride)) + AI_OFFSET_E((e), (stride)) + \ - AI_OFFSET_CH((ch), (stride)) ) - -#define AI_OFFSET(y, x, ch, z, stride) ( \ - AI_OFFSET_H((y), (stride)) + AI_OFFSET_W((x), (stride)) + \ - AI_OFFSET_CH((ch), (stride)) + \ - ((AI_STRIDE_SIZE((stride)) == 4) ? AI_OFFSET_IN_CH((z), (stride)) : AI_OFFSET_D((z), (stride))) ) - -/*! @} */ - -#define AI_GET_CONV_OUT_SIZE(in_size, filt_size, pad_l, pad_r, filt_stride) \ - ((((in_size) - (filt_size) + (pad_l) + (pad_r)) / (filt_stride)) + 1) - - -/** Tensors datatypes defines handlers ****************************************/ -#define AI_TENSOR_SIZE(tensor_) \ - get_tensor_size(tensor_, true) - -#define AI_TENSOR_SIZE_UNPAD(tensor_) \ - get_tensor_size(tensor_, false) - -#define AI_TENSOR_BYTE_SIZE(tensor_) \ - get_tensor_byte_size(tensor_) - - -/******************************************************************************/ -#define AI_PLATFORM_VERSION_INIT(major_, minor_, micro_) \ - { .major = (major_), .minor = (minor_), .micro = (micro_), .reserved = 0x0 } - - -/** Integer tensor info extraction ********************************************/ -#define AI_INTQ_INFO_LIST_SCALE_ARRAY(list_, type_) \ - ( ((list_) && (list_)->info) \ - ? ((type_*)((list_)->info->scale)) : NULL ) - -#define AI_INTQ_INFO_LIST_ZEROPOINT_ARRAY(list_, type_) \ - ( ((list_) && (list_)->info) \ - ? ((type_*)((list_)->info->zeropoint)) : NULL ) - -#define AI_KLASS_GET_INTQ_INFO_LIST(tensor_) \ - ((ai_intq_info_list*)((tensor_)->klass)) - - -AI_API_DECLARE_BEGIN - -/*! - * @brief Check whether 2 shapes have identical dimensions. - * @ingroup datatypes_internal - * @param shape0 the 1st tensor shape to compare - * @param shape1 the 2nd tensor shape to compare - * @return true if shape0 and shape1 have same dimensions. false otherwise - */ -AI_DECLARE_STATIC -ai_bool ai_shape_is_same( - const ai_shape* shape0, const ai_shape* shape1) -{ - AI_ASSERT(shape0 && shape1) - if (AI_SHAPE_SIZE(shape0) != AI_SHAPE_SIZE(shape1)) - return false; - ai_size dim = AI_SHAPE_SIZE(shape0); - while ( dim>0 ) { - dim--; - if ( AI_SHAPE_ELEM(shape0, dim)!=AI_SHAPE_ELEM(shape1, dim) ) - return false; - } - return true; -} - - -/*! - * @brief Check whether the shapes is 1*1*1... for a scalar value content. - * @ingroup datatypes_internal - * @param shape the tensor shape to evaluate - * @return true if shape0 is scalar false otherwise - */ -AI_DECLARE_STATIC -ai_bool ai_shape_is_scalar( - const ai_shape* shape0) -{ - ai_size dim = AI_SHAPE_SIZE(shape0); - while (dim>0) { - dim--; - if (AI_SHAPE_ELEM(shape0, dim) != 1) - return false; - } - return true; -} - - -/*! - * @brief Check if shape0 is a subshape of shape1 - * @ingroup datatypes_internal - * @param shape0 the 1st tensor shape to compare - * @param shape1 the 2nd tensor shape to compare - * @return true if shape0 is a subshape of shape1 (all shape0 dimensions are -* smallers or equal of the shape1 ones). false otherwise - */ -AI_DECLARE_STATIC -ai_bool ai_shape_is_subshape( - const ai_shape* shape0, const ai_shape* shape1) -{ - AI_ASSERT(shape0 && shape1) - AI_ASSERT(AI_SHAPE_SIZE(shape0)==AI_SHAPE_SIZE(shape1)) - ai_size dim = AI_SHAPE_SIZE(shape0); - while (dim) { - dim--; - if ( AI_SHAPE_ELEM(shape0, dim)>AI_SHAPE_ELEM(shape1, dim) ) - return false; - } - return true; -} - -/*! - * @brief Computes the total size of a tensor given its dimensions. - * @ingroup datatypes_internal - * @param shape the tensor shape - */ -AI_DECLARE_STATIC -ai_size ai_shape_get_size(const ai_shape* shape) -{ - AI_ASSERT(shape) - ai_size dim = AI_SHAPE_SIZE(shape); - AI_ASSERT(dim > 0) - ai_size size = 1; - while (dim>0) { - dim--; - size *= AI_SHAPE_ELEM(shape, dim); - } - return size; -} - -/*! - * @brief Computes the size of the input image discarding the channels. - * @ingroup datatypes_internal - * @param shape the tensor shape - */ -AI_DECLARE_STATIC -ai_size ai_shape_get_npixels(const ai_shape* shape) -{ - AI_ASSERT(shape) - const ai_size npixels = AI_SHAPE_W(shape) * AI_SHAPE_H(shape); - return npixels; -} - -/** APIs Section *************************************************************/ -/*! - * @brief Get packed version from major, minor, micro representaion. - * @ingroup datatypes_internal - * @param major major version value - * @param minor minor version value - * @param micro micro version value - * @return a packed version info obtained serializing input values - */ -AI_INTERNAL_API -ai_version ai_version_get(const ai_u8 major, const ai_u8 minor, const ai_u8 micro); - -/*! - * @brief Get un-packed version from packed version representaion. - * @ingroup datatypes_internal - * @param version a packed varsion info - * @return struct with de-serialized major, minor, micro values - */ -AI_INTERNAL_API -ai_platform_version ai_platform_version_get(const ai_version version); - -/*! - * @brief Map from ai_buffer data struct to ai_array data struct. - * @ingroup datatypes_internal - * @param buf a pointer to the ai_buffer to be mapped to ai_array - * @return an initialized @ref ai_array struct representing same data - */ -AI_INTERNAL_API -ai_array ai_from_buffer_to_array(const ai_buffer* buf); - -/*! - * @brief Map from ai_array data struct to ai_buffer data struct. - * @ingroup datatypes_internal - * @param array a pointer to the ai_array to be mapped to ai_buffer - * @return an initialized @ref ai_buffer struct representing same data - */ -AI_INTERNAL_API -ai_buffer ai_from_array_to_buffer(const ai_array* array); - -/*! - * @brief get the total number of elements of a n-dimensional tensor. - * @ingroup datatypes_internal - * @param t a pointer to an @ref ai_tensor - * @param with_padding when true it considers also padded elements - * @return the number of elements of the tensor (with/without padded ones) - */ -AI_INTERNAL_API -ai_size get_tensor_size(const ai_tensor* t, const ai_bool with_padding); - -/*! - * @brief get the total size in bytes of elements of a n-dimensional tensor (excluding padded ones). - * @ingroup datatypes_internal - * @param t a pointer to an @ref ai_tensor - * @return the total size in bytes of elements of the tensor (excluding padded ones) - */ -AI_INTERNAL_API -ai_size get_tensor_byte_size(const ai_tensor* t); - - -AI_API_DECLARE_END - -#endif /*AI_DATATYPES_INTERNAL_H*/ +/** + ****************************************************************************** + * @file ai_datatypes_internal.h + * @author AST Embedded Analytics Research Platform + * @brief Definitions of AI platform private APIs types + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef AI_DATATYPES_INTERNAL_H +#define AI_DATATYPES_INTERNAL_H + +#include "ai_datatypes.h" +#include "ai_datatypes_defines.h" + +/*! + * @defgroup datatypes_internal Internal Datatypes + * @brief Data structures used internally to implement neural networks + * + * The layers are defined as structs; a generic layer type defines the basic + * layer parameters and type-specific parameters are handled by specializations + * implemented as a C union. The layers keep also a pointer to the parent + * network and the next layer in the network. + * The input, output and parameters are tensor with an hard-coded maximum + * dimension of 4. Tensors are floating point arrays with a notion of size. + * The network is a linked list of layers, and thus it stores only the pointer + * to the first layer. + */ + +/*! + * @section Offsets + * @ingroup datatypes_internal + * Macros to handle (byte) stride addressing on tensors. The `AI_PTR` macro + * is used to always cast a pointer to byte array. The macros `AI_OFFSET_X` are + * used to compute (byte) offsets of respectively adjacents row elements, col + * elements, channel elements and `channel_in` elements. + * @{ + */ + +/*! AI_STORAGE_KLASS SECTION ************************************/ +#define AI_STORAGE_KLASS_TYPE(s_) \ + ( (s_)->type ) + +#define AI_STORAGE_KLASS_SIZE(s_) \ + ( (s_)->size ) + +#define AI_STORAGE_KLASS_DATA(s_, type_) \ + ( (type_*)((s_)->data) ) + +#define AI_STORAGE_KLASS_COPY(dst_, dst_type_, src_, src_type_) \ +{ \ + AI_ASSERT(AI_STORAGE_KLASS_SIZE(src_)>=AI_STORAGE_KLASS_SIZE(dst_)) \ + AI_STORAGE_KLASS_SIZE(dst_) = AI_STORAGE_KLASS_SIZE(src_); \ + for (ai_size i=0; i AI_SHAPE_DEPTH) \ + ? AI_SHAPE_ELEM((shape_), AI_SHAPE_DEPTH) : 1) +#define AI_SHAPE_E(shape_) ((AI_SHAPE_SIZE((shape_)) > AI_SHAPE_EXTENSION) \ + ? AI_SHAPE_ELEM((shape_), AI_SHAPE_EXTENSION) : 1) +#define AI_SHAPE_T(shape_) AI_SHAPE_ELEM((shape_), AI_SHAPE_TIME) + +#define AI_CONV_SHAPE_H AI_SHAPE_W +#define AI_CONV_SHAPE_W AI_SHAPE_CH +#define AI_CONV_SHAPE_CH AI_SHAPE_H +#define AI_CONV_SHAPE_IN_CH AI_SHAPE_IN_CH + +/*! AI_STRIDES SECTION ***********************************/ +#define AI_STRIDE_2D_H(stride_) \ + AI_STRIDE_ELEM((stride_), AI_SHAPE_2D_HEIGHT) + +#define AI_STRIDE_2D_W(stride_) \ + AI_STRIDE_ELEM((stride_), AI_SHAPE_2D_WIDTH) + +#define AI_STRIDE_ELEM(stride_, pos_) \ + AI_STORAGE_KLASS_DATA(stride_, ai_stride_dimension)[pos_] + +#define AI_STRIDE_GET_ELEM(stride_, pos_) \ + (((pos_) < AI_STRIDE_SIZE(stride_)) ? AI_STRIDE_ELEM(stride_, pos_) : 0) + +#define AI_STRIDE_SET_ELEM(stride_, pos_, val_) \ + if ((pos_) < AI_STRIDE_SIZE(stride_)) AI_STRIDE_ELEM(stride_, pos_) = (val_); + +#define AI_STRIDE_TYPE(stride_) \ + AI_STORAGE_KLASS_TYPE(stride_) + +#define AI_STRIDE_SIZE(stride_) \ + AI_STORAGE_KLASS_SIZE(stride_) + +#define AI_STRIDE_CLONE(dst_, src_) \ + AI_STORAGE_KLASS_COPY(dst_, ai_stride_dimension, src_, ai_stride_dimension) + +#define AI_STRIDE_BCAST_CLONE(dst_, src_) \ +{ \ + for (ai_size i=0; i= 5) ? AI_STRIDE_ELEM((stride), AI_SHAPE_DEPTH) : 0) +#define AI_STRIDE_E(stride) ((AI_STRIDE_SIZE((stride)) == 6) ? AI_STRIDE_ELEM((stride), AI_SHAPE_EXTENSION) : 0) +#define AI_STRIDE_T(stride) AI_STRIDE_ELEM((stride), AI_SHAPE_TIME) + +#define AI_STRIDE_SET_H(stride, val) AI_STRIDE_SET_ELEM((stride), AI_SHAPE_HEIGHT, val) +#define AI_STRIDE_SET_W(stride, val) AI_STRIDE_SET_ELEM((stride), AI_SHAPE_WIDTH, val) +#define AI_STRIDE_SET_CH(stride, val) AI_STRIDE_SET_ELEM((stride), AI_SHAPE_CHANNEL, val) +#define AI_STRIDE_SET_IN_CH(stride, val) AI_STRIDE_SET_ELEM((stride), AI_SHAPE_IN_CHANNEL, val) +#define AI_STRIDE_SET_D(stride, val) if (AI_STRIDE_SIZE((stride)) >= 5) AI_STRIDE_SET_ELEM((stride), AI_SHAPE_DEPTH, val) +#define AI_STRIDE_SET_E(stride, val) if (AI_STRIDE_SIZE((stride)) == 6) AI_STRIDE_SET_ELEM((stride), AI_SHAPE_EXTENSION, val) + +/*! AI_TENSORS SECTION ***********************************/ +#define AI_TENSOR_KLASS(tensor_) \ + ((tensor_) ? (tensor_)->klass : NULL) + +#define AI_TENSOR_SHAPE(tensor_) \ + (&((tensor_)->shape)) + +#define AI_TENSOR_STRIDE(tensor_) \ + (&((tensor_)->stride)) + +#define AI_TENSOR_INFO(tensor_) \ + (&((tensor_)->info)) + +#define AI_TENSOR_ARRAY(tensor_) \ + ((tensor_) ? (tensor_)->data : NULL) + +#define AI_TENSOR_ID(tensor_) \ + ((tensor_) ? AI_TENSOR_INFO(tensor_)->id : 0) + +#define AI_TENSOR_FLAGS(tensor_) \ + ((tensor_) ? AI_TENSOR_INFO(tensor_)->flags : 0) + +#define AI_TENSOR_DATA_SIZE(tensor_) \ + ((tensor_) ? AI_TENSOR_INFO(tensor_)->data_size : 0) + +/*! AI_OFFSETS SECTION ***********************************/ +//#define AI_OFFSET_BATCH(b, stride) ((ai_ptr_offset)(b) * AI_STRIDE_BATCH(stride)) +#define AI_OFFSET_H(y, stride) ((ai_ptr_offset)(y) * AI_STRIDE_H(stride)) +#define AI_OFFSET_W(x, stride) ((ai_ptr_offset)(x) * AI_STRIDE_W(stride)) +#define AI_OFFSET_CH(ch, stride) ((ai_ptr_offset)(ch) * AI_STRIDE_CH(stride)) +#define AI_OFFSET_IN_CH(in_ch, stride) ((ai_ptr_offset)(in_ch) * \ + AI_STRIDE_IN_CH(stride)) +#define AI_OFFSET_D(d, stride) ((ai_ptr_offset)(d) * AI_STRIDE_D(stride)) +#define AI_OFFSET_E(e, stride) ((ai_ptr_offset)(e) * AI_STRIDE_E(stride)) + +#define AI_OFFSET_5D(y, x, d, e, ch, stride) ( \ + AI_OFFSET_H((y), (stride)) + AI_OFFSET_W((x), (stride)) + \ + AI_OFFSET_D((d), (stride)) + AI_OFFSET_E((e), (stride)) + \ + AI_OFFSET_CH((ch), (stride)) ) + +#define AI_OFFSET(y, x, ch, z, stride) ( \ + AI_OFFSET_H((y), (stride)) + AI_OFFSET_W((x), (stride)) + \ + AI_OFFSET_CH((ch), (stride)) + \ + ((AI_STRIDE_SIZE((stride)) == 4) ? AI_OFFSET_IN_CH((z), (stride)) : AI_OFFSET_D((z), (stride))) ) + +/*! @} */ + +#define AI_GET_CONV_OUT_SIZE(in_size, filt_size, pad_l, pad_r, filt_stride) \ + ((((in_size) - (filt_size) + (pad_l) + (pad_r)) / (filt_stride)) + 1) + + +/** Tensors datatypes defines handlers ****************************************/ +#define AI_TENSOR_SIZE(tensor_) \ + get_tensor_size(tensor_, true) + +#define AI_TENSOR_SIZE_UNPAD(tensor_) \ + get_tensor_size(tensor_, false) + +#define AI_TENSOR_BYTE_SIZE(tensor_) \ + get_tensor_byte_size(tensor_) + + +/******************************************************************************/ +#define AI_PLATFORM_VERSION_INIT(major_, minor_, micro_) \ + { .major = (major_), .minor = (minor_), .micro = (micro_), .reserved = 0x0 } + + +/** Integer tensor info extraction ********************************************/ +#define AI_INTQ_INFO_LIST_SCALE_ARRAY(list_, type_) \ + ( ((list_) && (list_)->info) \ + ? ((type_*)((list_)->info->scale)) : NULL ) + +#define AI_INTQ_INFO_LIST_ZEROPOINT_ARRAY(list_, type_) \ + ( ((list_) && (list_)->info) \ + ? ((type_*)((list_)->info->zeropoint)) : NULL ) + +#define AI_KLASS_GET_INTQ_INFO_LIST(tensor_) \ + ((ai_intq_info_list*)((tensor_)->klass)) + + +AI_API_DECLARE_BEGIN + +/*! + * @brief Check whether 2 shapes have identical dimensions. + * @ingroup datatypes_internal + * @param shape0 the 1st tensor shape to compare + * @param shape1 the 2nd tensor shape to compare + * @return true if shape0 and shape1 have same dimensions. false otherwise + */ +AI_DECLARE_STATIC +ai_bool ai_shape_is_same( + const ai_shape* shape0, const ai_shape* shape1) +{ + AI_ASSERT(shape0 && shape1) + if (AI_SHAPE_SIZE(shape0) != AI_SHAPE_SIZE(shape1)) + return false; + ai_size dim = AI_SHAPE_SIZE(shape0); + while ( dim>0 ) { + dim--; + if ( AI_SHAPE_ELEM(shape0, dim)!=AI_SHAPE_ELEM(shape1, dim) ) + return false; + } + return true; +} + + +/*! + * @brief Check whether the shapes is 1*1*1... for a scalar value content. + * @ingroup datatypes_internal + * @param shape the tensor shape to evaluate + * @return true if shape0 is scalar false otherwise + */ +AI_DECLARE_STATIC +ai_bool ai_shape_is_scalar( + const ai_shape* shape0) +{ + ai_size dim = AI_SHAPE_SIZE(shape0); + while (dim>0) { + dim--; + if (AI_SHAPE_ELEM(shape0, dim) != 1) + return false; + } + return true; +} + + +/*! + * @brief Check if shape0 is a subshape of shape1 + * @ingroup datatypes_internal + * @param shape0 the 1st tensor shape to compare + * @param shape1 the 2nd tensor shape to compare + * @return true if shape0 is a subshape of shape1 (all shape0 dimensions are +* smallers or equal of the shape1 ones). false otherwise + */ +AI_DECLARE_STATIC +ai_bool ai_shape_is_subshape( + const ai_shape* shape0, const ai_shape* shape1) +{ + AI_ASSERT(shape0 && shape1) + AI_ASSERT(AI_SHAPE_SIZE(shape0)==AI_SHAPE_SIZE(shape1)) + ai_size dim = AI_SHAPE_SIZE(shape0); + while (dim) { + dim--; + if ( AI_SHAPE_ELEM(shape0, dim)>AI_SHAPE_ELEM(shape1, dim) ) + return false; + } + return true; +} + +/*! + * @brief Computes the total size of a tensor given its dimensions. + * @ingroup datatypes_internal + * @param shape the tensor shape + */ +AI_DECLARE_STATIC +ai_size ai_shape_get_size(const ai_shape* shape) +{ + AI_ASSERT(shape) + ai_size dim = AI_SHAPE_SIZE(shape); + AI_ASSERT(dim > 0) + ai_size size = 1; + while (dim>0) { + dim--; + size *= AI_SHAPE_ELEM(shape, dim); + } + return size; +} + +/*! + * @brief Computes the size of the input image discarding the channels. + * @ingroup datatypes_internal + * @param shape the tensor shape + */ +AI_DECLARE_STATIC +ai_size ai_shape_get_npixels(const ai_shape* shape) +{ + AI_ASSERT(shape) + const ai_size npixels = AI_SHAPE_W(shape) * AI_SHAPE_H(shape); + return npixels; +} + +/** APIs Section *************************************************************/ +/*! + * @brief Get packed version from major, minor, micro representaion. + * @ingroup datatypes_internal + * @param major major version value + * @param minor minor version value + * @param micro micro version value + * @return a packed version info obtained serializing input values + */ +AI_INTERNAL_API +ai_version ai_version_get(const ai_u8 major, const ai_u8 minor, const ai_u8 micro); + +/*! + * @brief Get un-packed version from packed version representaion. + * @ingroup datatypes_internal + * @param version a packed varsion info + * @return struct with de-serialized major, minor, micro values + */ +AI_INTERNAL_API +ai_platform_version ai_platform_version_get(const ai_version version); + +/*! + * @brief Map from ai_buffer data struct to ai_array data struct. + * @ingroup datatypes_internal + * @param buf a pointer to the ai_buffer to be mapped to ai_array + * @return an initialized @ref ai_array struct representing same data + */ +AI_INTERNAL_API +ai_array ai_from_buffer_to_array(const ai_buffer* buf); + +/*! + * @brief Map from ai_array data struct to ai_buffer data struct. + * @ingroup datatypes_internal + * @param array a pointer to the ai_array to be mapped to ai_buffer + * @return an initialized @ref ai_buffer struct representing same data + */ +AI_INTERNAL_API +ai_buffer ai_from_array_to_buffer(const ai_array* array); + +/*! + * @brief get the total number of elements of a n-dimensional tensor. + * @ingroup datatypes_internal + * @param t a pointer to an @ref ai_tensor + * @param with_padding when true it considers also padded elements + * @return the number of elements of the tensor (with/without padded ones) + */ +AI_INTERNAL_API +ai_size get_tensor_size(const ai_tensor* t, const ai_bool with_padding); + +/*! + * @brief get the total size in bytes of elements of a n-dimensional tensor (excluding padded ones). + * @ingroup datatypes_internal + * @param t a pointer to an @ref ai_tensor + * @return the total size in bytes of elements of the tensor (excluding padded ones) + */ +AI_INTERNAL_API +ai_size get_tensor_byte_size(const ai_tensor* t); + + +AI_API_DECLARE_END + +#endif /*AI_DATATYPES_INTERNAL_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_layer_custom_interface.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_layer_custom_interface.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_layer_custom_interface.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_layer_custom_interface.h index 75c2e88e..ce430106 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_layer_custom_interface.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_layer_custom_interface.h @@ -1,262 +1,262 @@ -/** - ****************************************************************************** - * @file ai_layer_custom_interface.h - * @author AST Embedded Analytics Research Platform - * @brief Definitions of AI platform custom layers interface APIs - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef AI_LAYER_CUSTOM_INTERFACE_H -#define AI_LAYER_CUSTOM_INTERFACE_H - -#include "ai_platform.h" -#include "ai_platform_interface.h" - -#include "layers_custom.h" - -#define INTQ_SCALE_FLOAT (AI_BUFFER_META_FLAG_SCALE_FLOAT) -#define INTQ_ZEROPOINT_U8 (AI_BUFFER_META_FLAG_ZEROPOINT_U8) -#define INTQ_ZEROPOINT_S8 (AI_BUFFER_META_FLAG_ZEROPOINT_S8) -#define INTQ_ZEROPOINT_U16 (AI_BUFFER_META_FLAG_ZEROPOINT_U16) -#define INTQ_ZEROPOINT_S16 (AI_BUFFER_META_FLAG_ZEROPOINT_S16) - -#define AI_TENSOR_HEIGHT (3) -#define AI_TENSOR_WIDTH (2) -#define AI_TENSOR_CHANNEL (1) -#define AI_TENSOR_IN_CHANNEL (0) - - -AI_API_DECLARE_BEGIN - -typedef enum { - TYPE_NONE = 0x0, - TYPE_FLOAT, - TYPE_BOOL, - TYPE_INTEGER, - TYPE_SIGNED, - TYPE_UNSIGNED, -} ai_tensor_type; - -typedef struct { - ai_tensor_type type; - ai_i8 bits; - ai_i8 fbits; -} ai_tensor_format; - -typedef struct { - ai_u16 flags; /*!< optional flags to store intq info attributes */ - ai_u16 size; /*!< number of elements in the the intq_info list */ - ai_float* scale; /*!< array of scales factors */ - union { - ai_u8* zeropoint_u8; /*!< array of zeropoints as unsigned */ - ai_i8* zeropoint_s8; /*!< array of zeropoints as signed */ - }; -} ai_tensor_intq_info; - - -/**************************************************************************** - ** Layer Custom Interface APIs - ****************************************************************************/ -/*! - * @brief acquire the custom layer from its handle - * @ingroup ai_layer_custom_interface - * @param layer an opaque handler to the custom layer - * @return a pointer to ai_layer_custom if found and valid, else NULL - */ -AI_INTERFACE_TYPE -ai_layer_custom* ai_layer_custom_get( - ai_layer* layer); - -/*! - * @brief release the custom layer provided its handle - * @ingroup ai_layer_custom_interface - * @param layer an opaque handler to the custom layer to release - */ -AI_INTERFACE_TYPE -void ai_layer_custom_release( - ai_layer* layer); - -/*! - * @brief get the number of inputs tensors of a custom layer - * @ingroup ai_layer_custom_interface - * @param layer an opaque handler to the custom layer - * @return the number of input tensors of the layer. 0 if no input tensors or error - */ -AI_INTERFACE_TYPE -ai_size ai_layer_get_tensor_in_size( - const ai_layer* layer); - -/*! - * @brief get the number of outputs tensors of a custom layer - * @ingroup ai_layer_custom_interface - * @param layer an opaque handler to the custom layer - * @return the number of outputs tensors of the layer. 0 if no outputs tensors or error - */ -AI_INTERFACE_TYPE -ai_size ai_layer_get_tensor_out_size( - const ai_layer* layer); - - -/*! - * @brief get the number of weights tensors of a custom layer - * @ingroup ai_layer_custom_interface - * @param layer an opaque handler to the custom layer - * @return the number of weights tensors of the layer. 0 if no weights tensors or error - */ -AI_INTERFACE_TYPE -ai_size ai_layer_get_tensor_weights_size( - const ai_layer* layer); - - -/*! - * @brief get the n-th (at index pos) input tensor pointer from a layer - * @ingroup ai_layer_custom_interface - * @param layer an opaque handler to the layer - * @param pos the index position in the tensor list - * @return a pointer to a tensor if found, else, if invalid or out-of-range NULL - */ -AI_INTERFACE_TYPE -ai_tensor* ai_layer_get_tensor_in( - const ai_layer* layer, const ai_u16 pos); - -/*! - * @brief get the n-th (at index pos) output tensor pointer from a layer - * @ingroup ai_layer_custom_interface - * @param layer an opaque handler to the layer - * @param pos the index position in the tensor list - * @return a pointer to a tensor if found, else, if invalid or out-of-range NULL - */ -AI_INTERFACE_TYPE -ai_tensor* ai_layer_get_tensor_out( - const ai_layer* layer, const ai_u16 pos); - - -/*! - * @brief get the n-th (at index pos) weight tensor pointer from a layer - * @ingroup ai_layer_custom_interface - * @param layer an opaque handler to the layer - * @param pos the index position in the tensor list - * @return a pointer to a tensor if found, else, if invalid or out-of-range NULL - */ -AI_INTERFACE_TYPE -ai_tensor* ai_layer_get_tensor_weights( - const ai_layer* layer, const ai_u16 pos); - - -/**** Layer Tensors APIs ***************************************************/ -/*! - * @brief check if the tensor has integer quantization informations @ref ai_tensor_intq_info - * @ingroup ai_layer_custom_interface - * @param tensor a pointer to the tensor - * @return true if tensot has integer quantization informations, false otherwise - */ -AI_INTERFACE_TYPE -ai_bool ai_tensor_has_intq( - const ai_tensor* t); - -/*! - * @brief get the tensor integer quantization informations @ref ai_tensor_intq_info - * @ingroup ai_layer_custom_interface - * @param tensor a pointer to the tensor - * @return the integer quantization informations as a struct @ref ai_tensor_intq_info - */ -AI_INTERFACE_TYPE -ai_tensor_intq_info ai_tensor_get_intq( - const ai_tensor* t); - -/*! - * @brief get the format of the tensor see @ref ai_tensor_format - * @ingroup ai_layer_custom_interface - * @param tensor a pointer to the tensor - * @return the tensor format - */ -AI_INTERFACE_TYPE -ai_tensor_format ai_tensor_get_format( - const ai_tensor* t); - -/**** Shapes Getters ****/ -/*! - * @brief get the dimensionality of the tensor shapes - * @ingroup ai_layer_custom_interface - * @param tensor a pointer to the tensor - * @return the dimensionality of the tensor shape - */ -AI_INTERFACE_TYPE -ai_size ai_tensor_get_shape_size( - const ai_tensor* t); - -/*! - * @brief get the value of the shape dimensionality pos - * @ingroup ai_layer_custom_interface - * @param tensor a pointer to the tensor - * @return the value of the shape dimensionality at pos of the tensor - */ -AI_INTERFACE_TYPE -ai_shape_dimension ai_tensor_get_shape( - const ai_tensor* t, const ai_u16 pos); - -/**** Strides Getters ****/ -/*! - * @brief get the dimensionality of the tensor strides - * @ingroup ai_layer_custom_interface - * @param tensor a pointer to the tensor - * @return the dimensionality of the tensor strides @ref ai_stride - */ -AI_INTERFACE_TYPE -ai_size ai_tensor_get_stride_size( - const ai_tensor* t); - -/*! - * @brief get the value of the stride dimensionality pos - * @ingroup ai_layer_custom_interface - * @param tensor a pointer to the tensor - * @return the value of the stride dimensionality at pos of the tensor - */ -AI_INTERFACE_TYPE -ai_stride_dimension ai_tensor_get_stride( - const ai_tensor* t, const ai_u16 pos); - -/**** Data Storage Getters ****/ -/*! - * @brief get tensor storage data buffer pointer - * @ingroup ai_layer_custom_interface - * @param tensor a pointer to the tensor - * @return a pointer to the tensor data buffer, set to NULL if error - */ -AI_INTERFACE_TYPE -ai_any_ptr ai_tensor_get_data( - const ai_tensor* t); - -/*! - * @brief get number of tensor elements - * @ingroup ai_layer_custom_interface - * @param tensor a pointer to the tensor - * @return the number of tensor elements or 0 if error - */ -AI_INTERFACE_TYPE -ai_size ai_tensor_get_data_size( - const ai_tensor* t); - -/*! - * @brief get the size in bytes of the tensor data buffer - * @ingroup ai_layer_custom_interface - * @param tensor a pointer to the tensor - * @return the size in bytes of the tensor data buffer. 0 if error - */ -AI_INTERFACE_TYPE -ai_size ai_tensor_get_data_byte_size( - const ai_tensor* t); - - -AI_API_DECLARE_END - -#endif /*AI_LAYER_CUSTOM_INTERFACE_H*/ +/** + ****************************************************************************** + * @file ai_layer_custom_interface.h + * @author AST Embedded Analytics Research Platform + * @brief Definitions of AI platform custom layers interface APIs + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef AI_LAYER_CUSTOM_INTERFACE_H +#define AI_LAYER_CUSTOM_INTERFACE_H + +#include "ai_platform.h" +#include "ai_platform_interface.h" + +#include "layers_custom.h" + +#define INTQ_SCALE_FLOAT (AI_BUFFER_META_FLAG_SCALE_FLOAT) +#define INTQ_ZEROPOINT_U8 (AI_BUFFER_META_FLAG_ZEROPOINT_U8) +#define INTQ_ZEROPOINT_S8 (AI_BUFFER_META_FLAG_ZEROPOINT_S8) +#define INTQ_ZEROPOINT_U16 (AI_BUFFER_META_FLAG_ZEROPOINT_U16) +#define INTQ_ZEROPOINT_S16 (AI_BUFFER_META_FLAG_ZEROPOINT_S16) + +#define AI_TENSOR_HEIGHT (3) +#define AI_TENSOR_WIDTH (2) +#define AI_TENSOR_CHANNEL (1) +#define AI_TENSOR_IN_CHANNEL (0) + + +AI_API_DECLARE_BEGIN + +typedef enum { + TYPE_NONE = 0x0, + TYPE_FLOAT, + TYPE_BOOL, + TYPE_INTEGER, + TYPE_SIGNED, + TYPE_UNSIGNED, +} ai_tensor_type; + +typedef struct { + ai_tensor_type type; + ai_i8 bits; + ai_i8 fbits; +} ai_tensor_format; + +typedef struct { + ai_u16 flags; /*!< optional flags to store intq info attributes */ + ai_u16 size; /*!< number of elements in the the intq_info list */ + ai_float* scale; /*!< array of scales factors */ + union { + ai_u8* zeropoint_u8; /*!< array of zeropoints as unsigned */ + ai_i8* zeropoint_s8; /*!< array of zeropoints as signed */ + }; +} ai_tensor_intq_info; + + +/**************************************************************************** + ** Layer Custom Interface APIs + ****************************************************************************/ +/*! + * @brief acquire the custom layer from its handle + * @ingroup ai_layer_custom_interface + * @param layer an opaque handler to the custom layer + * @return a pointer to ai_layer_custom if found and valid, else NULL + */ +AI_INTERFACE_TYPE +ai_layer_custom* ai_layer_custom_get( + ai_layer* layer); + +/*! + * @brief release the custom layer provided its handle + * @ingroup ai_layer_custom_interface + * @param layer an opaque handler to the custom layer to release + */ +AI_INTERFACE_TYPE +void ai_layer_custom_release( + ai_layer* layer); + +/*! + * @brief get the number of inputs tensors of a custom layer + * @ingroup ai_layer_custom_interface + * @param layer an opaque handler to the custom layer + * @return the number of input tensors of the layer. 0 if no input tensors or error + */ +AI_INTERFACE_TYPE +ai_size ai_layer_get_tensor_in_size( + const ai_layer* layer); + +/*! + * @brief get the number of outputs tensors of a custom layer + * @ingroup ai_layer_custom_interface + * @param layer an opaque handler to the custom layer + * @return the number of outputs tensors of the layer. 0 if no outputs tensors or error + */ +AI_INTERFACE_TYPE +ai_size ai_layer_get_tensor_out_size( + const ai_layer* layer); + + +/*! + * @brief get the number of weights tensors of a custom layer + * @ingroup ai_layer_custom_interface + * @param layer an opaque handler to the custom layer + * @return the number of weights tensors of the layer. 0 if no weights tensors or error + */ +AI_INTERFACE_TYPE +ai_size ai_layer_get_tensor_weights_size( + const ai_layer* layer); + + +/*! + * @brief get the n-th (at index pos) input tensor pointer from a layer + * @ingroup ai_layer_custom_interface + * @param layer an opaque handler to the layer + * @param pos the index position in the tensor list + * @return a pointer to a tensor if found, else, if invalid or out-of-range NULL + */ +AI_INTERFACE_TYPE +ai_tensor* ai_layer_get_tensor_in( + const ai_layer* layer, const ai_u16 pos); + +/*! + * @brief get the n-th (at index pos) output tensor pointer from a layer + * @ingroup ai_layer_custom_interface + * @param layer an opaque handler to the layer + * @param pos the index position in the tensor list + * @return a pointer to a tensor if found, else, if invalid or out-of-range NULL + */ +AI_INTERFACE_TYPE +ai_tensor* ai_layer_get_tensor_out( + const ai_layer* layer, const ai_u16 pos); + + +/*! + * @brief get the n-th (at index pos) weight tensor pointer from a layer + * @ingroup ai_layer_custom_interface + * @param layer an opaque handler to the layer + * @param pos the index position in the tensor list + * @return a pointer to a tensor if found, else, if invalid or out-of-range NULL + */ +AI_INTERFACE_TYPE +ai_tensor* ai_layer_get_tensor_weights( + const ai_layer* layer, const ai_u16 pos); + + +/**** Layer Tensors APIs ***************************************************/ +/*! + * @brief check if the tensor has integer quantization informations @ref ai_tensor_intq_info + * @ingroup ai_layer_custom_interface + * @param tensor a pointer to the tensor + * @return true if tensot has integer quantization informations, false otherwise + */ +AI_INTERFACE_TYPE +ai_bool ai_tensor_has_intq( + const ai_tensor* t); + +/*! + * @brief get the tensor integer quantization informations @ref ai_tensor_intq_info + * @ingroup ai_layer_custom_interface + * @param tensor a pointer to the tensor + * @return the integer quantization informations as a struct @ref ai_tensor_intq_info + */ +AI_INTERFACE_TYPE +ai_tensor_intq_info ai_tensor_get_intq( + const ai_tensor* t); + +/*! + * @brief get the format of the tensor see @ref ai_tensor_format + * @ingroup ai_layer_custom_interface + * @param tensor a pointer to the tensor + * @return the tensor format + */ +AI_INTERFACE_TYPE +ai_tensor_format ai_tensor_get_format( + const ai_tensor* t); + +/**** Shapes Getters ****/ +/*! + * @brief get the dimensionality of the tensor shapes + * @ingroup ai_layer_custom_interface + * @param tensor a pointer to the tensor + * @return the dimensionality of the tensor shape + */ +AI_INTERFACE_TYPE +ai_size ai_tensor_get_shape_size( + const ai_tensor* t); + +/*! + * @brief get the value of the shape dimensionality pos + * @ingroup ai_layer_custom_interface + * @param tensor a pointer to the tensor + * @return the value of the shape dimensionality at pos of the tensor + */ +AI_INTERFACE_TYPE +ai_shape_dimension ai_tensor_get_shape( + const ai_tensor* t, const ai_u16 pos); + +/**** Strides Getters ****/ +/*! + * @brief get the dimensionality of the tensor strides + * @ingroup ai_layer_custom_interface + * @param tensor a pointer to the tensor + * @return the dimensionality of the tensor strides @ref ai_stride + */ +AI_INTERFACE_TYPE +ai_size ai_tensor_get_stride_size( + const ai_tensor* t); + +/*! + * @brief get the value of the stride dimensionality pos + * @ingroup ai_layer_custom_interface + * @param tensor a pointer to the tensor + * @return the value of the stride dimensionality at pos of the tensor + */ +AI_INTERFACE_TYPE +ai_stride_dimension ai_tensor_get_stride( + const ai_tensor* t, const ai_u16 pos); + +/**** Data Storage Getters ****/ +/*! + * @brief get tensor storage data buffer pointer + * @ingroup ai_layer_custom_interface + * @param tensor a pointer to the tensor + * @return a pointer to the tensor data buffer, set to NULL if error + */ +AI_INTERFACE_TYPE +ai_any_ptr ai_tensor_get_data( + const ai_tensor* t); + +/*! + * @brief get number of tensor elements + * @ingroup ai_layer_custom_interface + * @param tensor a pointer to the tensor + * @return the number of tensor elements or 0 if error + */ +AI_INTERFACE_TYPE +ai_size ai_tensor_get_data_size( + const ai_tensor* t); + +/*! + * @brief get the size in bytes of the tensor data buffer + * @ingroup ai_layer_custom_interface + * @param tensor a pointer to the tensor + * @return the size in bytes of the tensor data buffer. 0 if error + */ +AI_INTERFACE_TYPE +ai_size ai_tensor_get_data_byte_size( + const ai_tensor* t); + + +AI_API_DECLARE_END + +#endif /*AI_LAYER_CUSTOM_INTERFACE_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_lite.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_lite.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_lite.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_lite.h index fdf56c75..1ad075e6 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_lite.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_lite.h @@ -1,62 +1,62 @@ -/** - ****************************************************************************** - * @file ai_lite.h - * @author STMicroelectronics - * @brief Definitions and implementations of runtime-lite public APIs - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef AI_LITE_H -#define AI_LITE_H - -#include "ai_platform.h" -#include "stai.h" - -#define LITE_API_ENTRY \ - /* LITE_API_ENTRY */ - -#define LITE_GRAPH_INIT(_inputs, _outputs, _activations, _weights, _cb, _cb_cookie) { \ - .inputs = (stai_ptr*)(_inputs), \ - .outputs = (stai_ptr*)(_outputs), \ - .activations = (stai_ptr*)(_activations), \ - .weights = (const stai_ptr*)(_weights), \ - .cb = (_cb), \ - .cb_cookie = (_cb_cookie), \ -} - - -STAI_API_DECLARE_BEGIN - -typedef enum { - LITE_OK = 0x0, - LITE_KO_INPUTS = (0x1 << 0), - LITE_KO_OUTPUTS = (0x1 << 1), - LITE_KO_WEIGHTS = (0x1 << 2), - LITE_KO_ACTIVATIONS = (0x1 << 3), - LITE_KO_GRAPH = (0x1 << 4), - LITE_KO_API = (0x1 << 5), -} lite_result; - - -typedef struct { - stai_ptr* inputs; - stai_ptr* outputs; - stai_ptr* activations; - const stai_ptr* weights; - const stai_event_cb cb; - void* cb_cookie; -} lite_graph; - - -STAI_API_DECLARE_END - -#endif /* AI_LITE_H */ +/** + ****************************************************************************** + * @file ai_lite.h + * @author STMicroelectronics + * @brief Definitions and implementations of runtime-lite public APIs + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef AI_LITE_H +#define AI_LITE_H + +#include "ai_platform.h" +#include "stai.h" + +#define LITE_API_ENTRY \ + /* LITE_API_ENTRY */ + +#define LITE_GRAPH_INIT(_inputs, _outputs, _activations, _weights, _cb, _cb_cookie) { \ + .inputs = (stai_ptr*)(_inputs), \ + .outputs = (stai_ptr*)(_outputs), \ + .activations = (stai_ptr*)(_activations), \ + .weights = (const stai_ptr*)(_weights), \ + .cb = (_cb), \ + .cb_cookie = (_cb_cookie), \ +} + + +STAI_API_DECLARE_BEGIN + +typedef enum { + LITE_OK = 0x0, + LITE_KO_INPUTS = (0x1 << 0), + LITE_KO_OUTPUTS = (0x1 << 1), + LITE_KO_WEIGHTS = (0x1 << 2), + LITE_KO_ACTIVATIONS = (0x1 << 3), + LITE_KO_GRAPH = (0x1 << 4), + LITE_KO_API = (0x1 << 5), +} lite_result; + + +typedef struct { + stai_ptr* inputs; + stai_ptr* outputs; + stai_ptr* activations; + const stai_ptr* weights; + const stai_event_cb cb; + void* cb_cookie; +} lite_graph; + + +STAI_API_DECLARE_END + +#endif /* AI_LITE_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_lite_inspect.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_lite_inspect.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_lite_inspect.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_lite_inspect.h index f61400ad..68036dc4 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_lite_inspect.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_lite_inspect.h @@ -1,44 +1,44 @@ -/** - ****************************************************************************** - * @file ai_lite_inspect.h - * @author STMicroelectronics - * @brief Definitions and implementations of runtime-lite inspection routines - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef AI_LITE_INSPECT_H -#define AI_LITE_INSPECT_H -#include "ai_platform.h" - -// #define HAS_LITE_INSPECT - -#ifdef HAS_LITE_INSPECT -#include "stai_debug.h" - -#define LITE_INSPECT_CB(flags, node_id, data_ptr, data_size, data_fmt, data_id, data_pos) { \ - if (graph->cb) { \ - graph->cb((const void*)(graph->cb_cookie), \ - (const stai_flags)(flags), \ - (const int32_t)(node_id), (const void*)(data_ptr), (const int32_t)(data_size), \ - (const int32_t)(data_fmt), (const int32_t)(data_id), (const int32_t)(data_pos)); \ - } \ -} - -#else - -#define LITE_INSPECT_CB(flags, node_id, data_ptr, data_size, data_fmt, data_id, data_pos) { \ - do { /* LITE_INSPECT_CB() */ } while (0); \ -} - -#endif /* HAS_LITE_INSPECT */ - -#endif /* AI_LITE_INSPECT_H */ +/** + ****************************************************************************** + * @file ai_lite_inspect.h + * @author STMicroelectronics + * @brief Definitions and implementations of runtime-lite inspection routines + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef AI_LITE_INSPECT_H +#define AI_LITE_INSPECT_H +#include "ai_platform.h" + +// #define HAS_LITE_INSPECT + +#ifdef HAS_LITE_INSPECT +#include "stai_debug.h" + +#define LITE_INSPECT_CB(flags, node_id, data_ptr, data_size, data_fmt, data_id, data_pos) { \ + if (graph->cb) { \ + graph->cb((const void*)(graph->cb_cookie), \ + (const stai_flags)(flags), \ + (const int32_t)(node_id), (const void*)(data_ptr), (const int32_t)(data_size), \ + (const int32_t)(data_fmt), (const int32_t)(data_id), (const int32_t)(data_pos)); \ + } \ +} + +#else + +#define LITE_INSPECT_CB(flags, node_id, data_ptr, data_size, data_fmt, data_id, data_pos) { \ + do { /* LITE_INSPECT_CB() */ } while (0); \ +} + +#endif /* HAS_LITE_INSPECT */ + +#endif /* AI_LITE_INSPECT_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_lite_interface.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_lite_interface.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_lite_interface.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_lite_interface.h index 7214683f..82fd300f 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_lite_interface.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_lite_interface.h @@ -1,125 +1,125 @@ -/** - ****************************************************************************** - * @file ai_lite_interface.h - * @author STMicroelectronics - * @brief Definitions and implementations of runtime-lite codegen APIs - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef AI_LITE_INTERFACE_H -#define AI_LITE_INTERFACE_H - -#include "ai_lite.h" -#include "core_assert.h" - - -/*****************************************************************************/ -/* Generic Codegen Section */ -// #ifdef HAS_LOG -#if 0 -#include "core_log.h" - -#define LITE_GRAPH_START(_graph_name) \ - AI_LOG_DEBUG("[LITE GRAPH START] : " _graph_name) - -#define LITE_GRAPH_END(_graph_name) \ - AI_LOG_DEBUG("[LITE GRAPH END] : " _graph_name) - -#else - -#define LITE_GRAPH_START(_graph_name) \ - /* LITE_GRAPH_START() */ - -#define LITE_GRAPH_END(_graph_name) \ - /* LITE_GRAPH_END() */ - -#endif /* HAS_LOG */ - -#define LITE_ASSERT(expr) \ - CORE_ASSERT(expr) - - -/*****************************************************************************/ -#if defined(_MSC_VER) - #define LITE_DECLARE_STATIC static __inline - #define LITE_HINT_INLINE static __inline - #define LITE_FORCE_INLINE static __inline -#elif defined(__ICCARM__) || defined (__IAR_SYSTEMS_ICC__) - #define LITE_DECLARE_STATIC static inline - #define LITE_HINT_INLINE static inline - #define LITE_FORCE_INLINE static inline -#elif defined(__GNUC__) - #define LITE_DECLARE_STATIC static __inline - #define LITE_HINT_INLINE static __inline - #define LITE_FORCE_INLINE static __inline -#else - #define LITE_DECLARE_STATIC static __inline - #define LITE_HINT_INLINE static __inline - #define LITE_FORCE_INLINE static __inline -#endif /* _MSC_VER */ - -#define LITE_API_ENTRY /* LITE_API_ENTRY */ - -#define LITE_PACK(...) \ - __VA_ARGS__ - -#define LITE_UNUSED(_elem) \ - ((void)(_elem)); - - -/*****************************************************************************/ -/* Arrays Section */ - -#define LITE_ARRAY_VALUES(...) \ - { LITE_PACK(__VA_ARGS__) } - -#define LITE_ARRAY_DATA(_array, _type) \ - ((_type*)(_array)->data) - -#define LITE_ARRAY_DATA_START(_array, _type) \ - ((_type*)(_array)->data_start) - -/*****************************************************************************/ -/* Tensors Section */ - -#define LITE_TENSOR_ARRAY(_tensor, _pos) \ - (((_tensor)->data) + (_pos)) - -/*****************************************************************************/ -/* Tensors List Section */ - -#define LITE_TENSOR_LIST(_chain, _pos) \ - (&(_chain)->chain[_pos]) - -#define LITE_TENSOR_IN(_chain, _pos) \ - (LITE_TENSOR_LIST(_chain, 0)->tensor[_pos]) - -#define LITE_TENSOR_OUT(_chain, _pos) \ - (LITE_TENSOR_LIST(_chain, 1)->tensor[_pos]) - -#define LITE_TENSOR_WEIGHTS(_chain, _pos) \ - (LITE_TENSOR_LIST(_chain, 2)->tensor[_pos]) - -#define LITE_TENSOR_SCRATCHS(_chain, _pos) \ - (LITE_TENSOR_LIST(_chain, 3)->tensor[_pos]) - -/*****************************************************************************/ -#define LITE_LAYER_ACQUIRE(name_, cast_type_, ptr_) \ - LITE_ASSERT(ptr_) \ - AI_CONCAT(ai_layer_, cast_type_)* name_ = \ - (AI_CONCAT(ai_layer_, cast_type_)*)(ptr_); - -#define LITE_LAYER_RELEASE(name_, cast_type_) \ - /* LITE_LAYER_RELEASE() */ - - -#endif /* AI_LITE_INTERFACE_H */ +/** + ****************************************************************************** + * @file ai_lite_interface.h + * @author STMicroelectronics + * @brief Definitions and implementations of runtime-lite codegen APIs + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef AI_LITE_INTERFACE_H +#define AI_LITE_INTERFACE_H + +#include "ai_lite.h" +#include "core_assert.h" + + +/*****************************************************************************/ +/* Generic Codegen Section */ +// #ifdef HAS_LOG +#if 0 +#include "core_log.h" + +#define LITE_GRAPH_START(_graph_name) \ + AI_LOG_DEBUG("[LITE GRAPH START] : " _graph_name) + +#define LITE_GRAPH_END(_graph_name) \ + AI_LOG_DEBUG("[LITE GRAPH END] : " _graph_name) + +#else + +#define LITE_GRAPH_START(_graph_name) \ + /* LITE_GRAPH_START() */ + +#define LITE_GRAPH_END(_graph_name) \ + /* LITE_GRAPH_END() */ + +#endif /* HAS_LOG */ + +#define LITE_ASSERT(expr) \ + CORE_ASSERT(expr) + + +/*****************************************************************************/ +#if defined(_MSC_VER) + #define LITE_DECLARE_STATIC static __inline + #define LITE_HINT_INLINE static __inline + #define LITE_FORCE_INLINE static __inline +#elif defined(__ICCARM__) || defined (__IAR_SYSTEMS_ICC__) + #define LITE_DECLARE_STATIC static inline + #define LITE_HINT_INLINE static inline + #define LITE_FORCE_INLINE static inline +#elif defined(__GNUC__) + #define LITE_DECLARE_STATIC static __inline + #define LITE_HINT_INLINE static __inline + #define LITE_FORCE_INLINE static __inline +#else + #define LITE_DECLARE_STATIC static __inline + #define LITE_HINT_INLINE static __inline + #define LITE_FORCE_INLINE static __inline +#endif /* _MSC_VER */ + +#define LITE_API_ENTRY /* LITE_API_ENTRY */ + +#define LITE_PACK(...) \ + __VA_ARGS__ + +#define LITE_UNUSED(_elem) \ + ((void)(_elem)); + + +/*****************************************************************************/ +/* Arrays Section */ + +#define LITE_ARRAY_VALUES(...) \ + { LITE_PACK(__VA_ARGS__) } + +#define LITE_ARRAY_DATA(_array, _type) \ + ((_type*)(_array)->data) + +#define LITE_ARRAY_DATA_START(_array, _type) \ + ((_type*)(_array)->data_start) + +/*****************************************************************************/ +/* Tensors Section */ + +#define LITE_TENSOR_ARRAY(_tensor, _pos) \ + (((_tensor)->data) + (_pos)) + +/*****************************************************************************/ +/* Tensors List Section */ + +#define LITE_TENSOR_LIST(_chain, _pos) \ + (&(_chain)->chain[_pos]) + +#define LITE_TENSOR_IN(_chain, _pos) \ + (LITE_TENSOR_LIST(_chain, 0)->tensor[_pos]) + +#define LITE_TENSOR_OUT(_chain, _pos) \ + (LITE_TENSOR_LIST(_chain, 1)->tensor[_pos]) + +#define LITE_TENSOR_WEIGHTS(_chain, _pos) \ + (LITE_TENSOR_LIST(_chain, 2)->tensor[_pos]) + +#define LITE_TENSOR_SCRATCHS(_chain, _pos) \ + (LITE_TENSOR_LIST(_chain, 3)->tensor[_pos]) + +/*****************************************************************************/ +#define LITE_LAYER_ACQUIRE(name_, cast_type_, ptr_) \ + LITE_ASSERT(ptr_) \ + AI_CONCAT(ai_layer_, cast_type_)* name_ = \ + (AI_CONCAT(ai_layer_, cast_type_)*)(ptr_); + +#define LITE_LAYER_RELEASE(name_, cast_type_) \ + /* LITE_LAYER_RELEASE() */ + + +#endif /* AI_LITE_INTERFACE_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_lite_math_helpers.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_lite_math_helpers.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_lite_math_helpers.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_lite_math_helpers.h index a66d8d39..e8d4ad7c 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_lite_math_helpers.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_lite_math_helpers.h @@ -1,247 +1,247 @@ -#ifndef AI_LITE_MATH_HELPERS_H -#define AI_LITE_MATH_HELPERS_H -/** - ****************************************************************************** - * @file ai_lite_math_helpers.h - * @author STMicroelectronics - * @brief Math helpers routines header file for lite APIs. - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#include - -#include "ai_platform.h" -#include "ai_platform_interface.h" -#include "ai_datatypes_defines.h" - -#define AI_FLOAT_TOLERANCE (6.19209290e-5F) /* Used for small calculation - noise issues */ -#define AI_FLOAT_EPSILON (1.19209290e-7F) -#define AI_I8_EPSILON (0.00787401F) /* 1/(2^7 - 1) */ -#define AI_I16_EPSILON (3.051851e-5F) /* 1/(2^15 - 1) */ - -#define AI_FLT_MAX (3.40282346638528859812e+38f) - -#define AI_MIN(x,y) ( ((x)<(y)) ? (x) : (y) ) -#define AI_MAX(x,y) ( ((x)>(y)) ? (x) : (y) ) -#define AI_SIGN(x) (((x)>0) ? 1 : -1) -#define AI_CLAMP(x, min, max) AI_MIN(AI_MAX(x,min), max) -#define AI_ABS(x) fabsf(x) -#define AI_ABS_DIFF(x, y) ( ((x)>(y)) ? ((x)-(y)) : ((y)-(x)) ) -#define AI_NEG(x) ( -1 * (x) ) -#define AI_NOT(x) ( ((x)==true) ? false : true) -#define AI_RECIPROCAL(x) ( 1.0f / (x) ) -#define AI_CEIL(x) ceilf(x) -#define AI_FLOOR(x) floorf(x) -#define AI_FLOOR_DIV(x, y) AI_FLOOR((x)/(y)) /* floor division: x // y */ -#define AI_FLOOR_MOD(x, y) fmodf(x, y) -#define AI_ROUND(x) roundf(x) -#define AI_POW(x,y) powf(x, y) - -#define AI_SQUARED_DIFF(x, y) (((x)-(y)) * ((x)-(y))) - -#define AI_FLOAT_NEGATIVE_HALF (-0.5f + AI_FLOAT_EPSILON) -#define AI_FLOAT_POSITIVE_HALF (0.5f) - - -#define AI_MATH_ACOS(x) acosf(x) -#define AI_MATH_ACOSH(x) acoshf(x) -#define AI_MATH_ASIN(x) asinf(x) -#define AI_MATH_ASINH(x) asinhf(x) -#define AI_MATH_ATAN(x) atanf(x) -#define AI_MATH_ATANH(x) atanhf(x) -#define AI_MATH_COS(x) cosf(x) -#define AI_MATH_COSH(x) coshf(x) -#define AI_MATH_ERF(x) erff(x) -#define AI_MATH_EXP(x) expf(x) -#define AI_MATH_LOG(x) logf(x) -#define AI_MATH_POW(x, e) powf((x), (e)) -#define AI_MATH_RSQRT(x) (1.0f / AI_MATH_SQRT(x)) -#define AI_MATH_SIN(x) sinf(x) -#define AI_MATH_SINH(x) sinhf(x) -#define AI_MATH_SQRT(x) ai_math_sqrt(x) -#define AI_MATH_TAN(x) tanf(x) -#define AI_MATH_TANH(x) tanhf(x) -#define AI_MATH_SQUARE(x) AI_MATH_POW(x, 2.0f) - -#define AI_MATH_ACOS(x) acosf(x) -#define AI_MATH_ACOSH(x) acoshf(x) -#define AI_MATH_ASIN(x) asinf(x) -#define AI_MATH_ASINH(x) asinhf(x) -#define AI_MATH_ATAN(x) atanf(x) -#define AI_MATH_ATANH(x) atanhf(x) -#define AI_MATH_COS(x) cosf(x) -#define AI_MATH_COSH(x) coshf(x) -#define AI_MATH_ERF(x) erff(x) -#define AI_MATH_EXP(x) expf(x) -#define AI_MATH_LOG(x) logf(x) -#define AI_MATH_POW(x, e) powf((x), (e)) -#define AI_MATH_RSQRT(x) (1.0f / AI_MATH_SQRT(x)) -#define AI_MATH_SIN(x) sinf(x) -#define AI_MATH_SINH(x) sinhf(x) -#define AI_MATH_SQRT(x) ai_math_sqrt(x) -#define AI_MATH_TAN(x) tanf(x) -#define AI_MATH_TANH(x) tanhf(x) -#define AI_MATH_SQUARE(x) AI_MATH_POW(x, 2.0f) -#define AI_MATH_RELU_TEST(x, thr, min, max) \ - (((x)<=(thr)) ? (min) : (max)) - -#define AI_MATH_CLIP_LINEAR_REMAP(x, alpha, beta) \ - (AI_MAX(0, AI_MIN(1, ((x) * (alpha) + (beta))))) - -#define AI_MATH_RELU_GENERIC(x, thr, alpha, max) \ - AI_MATH_RELU_TEST(x, max, AI_MATH_RELU_GENERIC_NO_MAX(x, thr, alpha), max) - -#define AI_MATH_RELU_GENERIC_NO_MAX(x, thr, alpha) \ - AI_MATH_RELU_TEST(x, thr, ((alpha)*((x)-(thr))), x) - -#define AI_MATH_RELU_THRESHOLDED(x, thr) \ - AI_MATH_RELU_TEST(x, thr, 0, (x)) - -#define AI_MATH_LEAKY_RELU(x, neg_slope, pos_slope) \ - AI_MATH_RELU_TEST(x, 0, (x)*(neg_slope), (x)*(pos_slope)) -// ( ((x)>0) ? (x)*(pos_slope) : (x)*(neg_slope) ) - -#define AI_MATH_PRELU(x, slope) \ - AI_MATH_RELU_TEST(x, 0, (x)*(slope), (x)) -// AI_MATH_LEAKY_RELU(x, slope, 1) - -#define AI_MATH_RELU(x) \ - AI_MATH_RELU_TEST(x, 0, 0, x) -// AI_MAX(x, 0) - -#define AI_MATH_ELU(x, alpha) \ - (AI_MAX(0.0f, (x)) + AI_MIN(0.0f, (alpha) * (AI_MATH_EXP(x)-1.0f))) - -#define AI_MATH_SELU(x, alpha, scale) \ - ((scale)*AI_MATH_ELU(x, alpha)) - -#define AI_MATH_SCALED_TANH(x, alpha, beta) \ - ((alpha)*AI_MATH_TANH((beta)*(x))) - -#define AI_MATH_SIGMOID(x) \ - (1.0f / (1.0f + AI_MATH_EXP(-(x)))) - -#define AI_MATH_LOGISTIC(x)\ - (x < 0) ? (1.0f -(1.0f / (1.0f + AI_MATH_EXP(-AI_ABS(x))))) :\ - (1.0f / (1.0f + AI_MATH_EXP(-AI_ABS(x)))) - -#define AI_MATH_HARD_SIGMOID(x, alpha, beta) \ - AI_MATH_CLIP_LINEAR_REMAP(x, alpha, beta) - -#define AI_MATH_GELU_NO_APPROXIMATE(x) \ - ((x / 2.0f) * (1.0f + AI_MATH_ERF(x/AI_MATH_SQRT(2.0f)))) - -#define AI_MATH_GELU_APPROXIMATE(x) \ - ((x / 2.0f) * (1.0f + AI_MATH_TANH(AI_MATH_SQRT(2.0f/PI)*(x + 0.044715f * AI_MATH_POW(x, 3.0f))))) - -#define AI_MATH_GELU(x, approximate) \ - (((bool)approximate) ? AI_MATH_GELU_APPROXIMATE(x) : AI_MATH_GELU_NO_APPROXIMATE(x)) - - - - -/* Formula with higher accuracy */ -#define AI_MATH_SWISH(x) \ - ((x) * AI_MATH_SIGMOID(x)) - -#define AI_MATH_HARD_SWISH(x) \ - ((x) * AI_MATH_CLIP_LINEAR_REMAP(x, 1.0f/6, 0.5f)) - -#define AI_MATH_SOFT_PLUS(x) \ - AI_MATH_LOG(1.0f + AI_MATH_EXP(x)) - -#define AI_MATH_SOFT_SIGN(x) \ - ((x) / (1.0f + AI_ABS(x))) - - -AI_API_DECLARE_BEGIN - -/*! - * @typedef ai_vec4_float - * @ingroup ai_datatypes_internal - * @brief 32bit X 4 float (optimization for embedded MCU) - */ -typedef struct { - ai_float a1; - ai_float a2; - ai_float a3; - ai_float a4; -} ai_vec4_float; - - -#define AI_VEC4_FLOAT(ptr_) \ - _get_vec4_float((ai_handle)(ptr_)) - - -AI_DECLARE_STATIC -ai_vec4_float _get_vec4_float(const ai_handle fptr) -{ - return *((const ai_vec4_float*)fptr); -} - -/*****************************************************************************/ -typedef struct { - ai_u16 numRows; /**< number of rows of the matrix. */ - ai_u16 numCols; /**< number of columns of the matrix. */ - ai_float *pData; /**< points to the data of the matrix. */ -} ai_matrix_f32; - -/*! - * @brief general 2D matrix initialization - * @ingroup ai_lite_math_helpers - * @param S pointer to S matrix - * @param nRows number of rows of S matrix - * @param nColumns number of columns of S matrix - * @param pData pointer to S matrix data - */ -AI_INTERFACE_ENTRY -void st_mat_init_f32(ai_matrix_f32* S, - const uint16_t nRows, - const uint16_t nColumns, - float* pData); - - -/*! - * @brief general 2D matrix multiplication on float values - * @ingroup ai_lite_math_helpers - * @param pSrcA pointer to A matrix - * @param pSrcB pointer to B matrix - * @param pSrcC pointer to C matrix/array - * @param alpha multiplier of A*B product - * @param beta multiplier of C - * @param tA flag for A transpose - * @param tB flag for B transpose - * @param pDstY matrix result - * @return ARM_MATH_SUCCESS in case of success, ARM_MATH_SIZE_MISMATCH else - */ -AI_INTERFACE_ENTRY -uint32_t st_mat_gemm_f32(const ai_matrix_f32* pSrcA, - const ai_matrix_f32* pSrcB, - const ai_matrix_f32* pSrcC, - const float alpha, const float beta, - const int8_t tA, const int8_t tB, - ai_matrix_f32 * pDstY); - -/*! - * @brief platform optimized square root on a float value - * @ingroup ai_lite_math_helpers - * @param x input value - * @return square root of the value - */ -AI_INTERFACE_ENTRY -float ai_math_sqrt(const float x); - - -AI_API_DECLARE_END - -#endif /*AI_LITE_MATH_HELPERS_H*/ +#ifndef AI_LITE_MATH_HELPERS_H +#define AI_LITE_MATH_HELPERS_H +/** + ****************************************************************************** + * @file ai_lite_math_helpers.h + * @author STMicroelectronics + * @brief Math helpers routines header file for lite APIs. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#include + +#include "ai_platform.h" +#include "ai_platform_interface.h" +#include "ai_datatypes_defines.h" + +#define AI_FLOAT_TOLERANCE (6.19209290e-5F) /* Used for small calculation + noise issues */ +#define AI_FLOAT_EPSILON (1.19209290e-7F) +#define AI_I8_EPSILON (0.00787401F) /* 1/(2^7 - 1) */ +#define AI_I16_EPSILON (3.051851e-5F) /* 1/(2^15 - 1) */ + +#define AI_FLT_MAX (3.40282346638528859812e+38f) + +#define AI_MIN(x,y) ( ((x)<(y)) ? (x) : (y) ) +#define AI_MAX(x,y) ( ((x)>(y)) ? (x) : (y) ) +#define AI_SIGN(x) (((x)>0) ? 1 : -1) +#define AI_CLAMP(x, min, max) AI_MIN(AI_MAX(x,min), max) +#define AI_ABS(x) fabsf(x) +#define AI_ABS_DIFF(x, y) ( ((x)>(y)) ? ((x)-(y)) : ((y)-(x)) ) +#define AI_NEG(x) ( -1 * (x) ) +#define AI_NOT(x) ( ((x)==true) ? false : true) +#define AI_RECIPROCAL(x) ( 1.0f / (x) ) +#define AI_CEIL(x) ceilf(x) +#define AI_FLOOR(x) floorf(x) +#define AI_FLOOR_DIV(x, y) AI_FLOOR((x)/(y)) /* floor division: x // y */ +#define AI_FLOOR_MOD(x, y) fmodf(x, y) +#define AI_ROUND(x) roundf(x) +#define AI_POW(x,y) powf(x, y) + +#define AI_SQUARED_DIFF(x, y) (((x)-(y)) * ((x)-(y))) + +#define AI_FLOAT_NEGATIVE_HALF (-0.5f + AI_FLOAT_EPSILON) +#define AI_FLOAT_POSITIVE_HALF (0.5f) + + +#define AI_MATH_ACOS(x) acosf(x) +#define AI_MATH_ACOSH(x) acoshf(x) +#define AI_MATH_ASIN(x) asinf(x) +#define AI_MATH_ASINH(x) asinhf(x) +#define AI_MATH_ATAN(x) atanf(x) +#define AI_MATH_ATANH(x) atanhf(x) +#define AI_MATH_COS(x) cosf(x) +#define AI_MATH_COSH(x) coshf(x) +#define AI_MATH_ERF(x) erff(x) +#define AI_MATH_EXP(x) expf(x) +#define AI_MATH_LOG(x) logf(x) +#define AI_MATH_POW(x, e) powf((x), (e)) +#define AI_MATH_RSQRT(x) (1.0f / AI_MATH_SQRT(x)) +#define AI_MATH_SIN(x) sinf(x) +#define AI_MATH_SINH(x) sinhf(x) +#define AI_MATH_SQRT(x) ai_math_sqrt(x) +#define AI_MATH_TAN(x) tanf(x) +#define AI_MATH_TANH(x) tanhf(x) +#define AI_MATH_SQUARE(x) AI_MATH_POW(x, 2.0f) + +#define AI_MATH_ACOS(x) acosf(x) +#define AI_MATH_ACOSH(x) acoshf(x) +#define AI_MATH_ASIN(x) asinf(x) +#define AI_MATH_ASINH(x) asinhf(x) +#define AI_MATH_ATAN(x) atanf(x) +#define AI_MATH_ATANH(x) atanhf(x) +#define AI_MATH_COS(x) cosf(x) +#define AI_MATH_COSH(x) coshf(x) +#define AI_MATH_ERF(x) erff(x) +#define AI_MATH_EXP(x) expf(x) +#define AI_MATH_LOG(x) logf(x) +#define AI_MATH_POW(x, e) powf((x), (e)) +#define AI_MATH_RSQRT(x) (1.0f / AI_MATH_SQRT(x)) +#define AI_MATH_SIN(x) sinf(x) +#define AI_MATH_SINH(x) sinhf(x) +#define AI_MATH_SQRT(x) ai_math_sqrt(x) +#define AI_MATH_TAN(x) tanf(x) +#define AI_MATH_TANH(x) tanhf(x) +#define AI_MATH_SQUARE(x) AI_MATH_POW(x, 2.0f) +#define AI_MATH_RELU_TEST(x, thr, min, max) \ + (((x)<=(thr)) ? (min) : (max)) + +#define AI_MATH_CLIP_LINEAR_REMAP(x, alpha, beta) \ + (AI_MAX(0, AI_MIN(1, ((x) * (alpha) + (beta))))) + +#define AI_MATH_RELU_GENERIC(x, thr, alpha, max) \ + AI_MATH_RELU_TEST(x, max, AI_MATH_RELU_GENERIC_NO_MAX(x, thr, alpha), max) + +#define AI_MATH_RELU_GENERIC_NO_MAX(x, thr, alpha) \ + AI_MATH_RELU_TEST(x, thr, ((alpha)*((x)-(thr))), x) + +#define AI_MATH_RELU_THRESHOLDED(x, thr) \ + AI_MATH_RELU_TEST(x, thr, 0, (x)) + +#define AI_MATH_LEAKY_RELU(x, neg_slope, pos_slope) \ + AI_MATH_RELU_TEST(x, 0, (x)*(neg_slope), (x)*(pos_slope)) +// ( ((x)>0) ? (x)*(pos_slope) : (x)*(neg_slope) ) + +#define AI_MATH_PRELU(x, slope) \ + AI_MATH_RELU_TEST(x, 0, (x)*(slope), (x)) +// AI_MATH_LEAKY_RELU(x, slope, 1) + +#define AI_MATH_RELU(x) \ + AI_MATH_RELU_TEST(x, 0, 0, x) +// AI_MAX(x, 0) + +#define AI_MATH_ELU(x, alpha) \ + (AI_MAX(0.0f, (x)) + AI_MIN(0.0f, (alpha) * (AI_MATH_EXP(x)-1.0f))) + +#define AI_MATH_SELU(x, alpha, scale) \ + ((scale)*AI_MATH_ELU(x, alpha)) + +#define AI_MATH_SCALED_TANH(x, alpha, beta) \ + ((alpha)*AI_MATH_TANH((beta)*(x))) + +#define AI_MATH_SIGMOID(x) \ + (1.0f / (1.0f + AI_MATH_EXP(-(x)))) + +#define AI_MATH_LOGISTIC(x)\ + (x < 0) ? (1.0f -(1.0f / (1.0f + AI_MATH_EXP(-AI_ABS(x))))) :\ + (1.0f / (1.0f + AI_MATH_EXP(-AI_ABS(x)))) + +#define AI_MATH_HARD_SIGMOID(x, alpha, beta) \ + AI_MATH_CLIP_LINEAR_REMAP(x, alpha, beta) + +#define AI_MATH_GELU_NO_APPROXIMATE(x) \ + ((x / 2.0f) * (1.0f + AI_MATH_ERF(x/AI_MATH_SQRT(2.0f)))) + +#define AI_MATH_GELU_APPROXIMATE(x) \ + ((x / 2.0f) * (1.0f + AI_MATH_TANH(AI_MATH_SQRT(2.0f/PI)*(x + 0.044715f * AI_MATH_POW(x, 3.0f))))) + +#define AI_MATH_GELU(x, approximate) \ + (((bool)approximate) ? AI_MATH_GELU_APPROXIMATE(x) : AI_MATH_GELU_NO_APPROXIMATE(x)) + + + + +/* Formula with higher accuracy */ +#define AI_MATH_SWISH(x) \ + ((x) * AI_MATH_SIGMOID(x)) + +#define AI_MATH_HARD_SWISH(x) \ + ((x) * AI_MATH_CLIP_LINEAR_REMAP(x, 1.0f/6, 0.5f)) + +#define AI_MATH_SOFT_PLUS(x) \ + AI_MATH_LOG(1.0f + AI_MATH_EXP(x)) + +#define AI_MATH_SOFT_SIGN(x) \ + ((x) / (1.0f + AI_ABS(x))) + + +AI_API_DECLARE_BEGIN + +/*! + * @typedef ai_vec4_float + * @ingroup ai_datatypes_internal + * @brief 32bit X 4 float (optimization for embedded MCU) + */ +typedef struct { + ai_float a1; + ai_float a2; + ai_float a3; + ai_float a4; +} ai_vec4_float; + + +#define AI_VEC4_FLOAT(ptr_) \ + _get_vec4_float((ai_handle)(ptr_)) + + +AI_DECLARE_STATIC +ai_vec4_float _get_vec4_float(const ai_handle fptr) +{ + return *((const ai_vec4_float*)fptr); +} + +/*****************************************************************************/ +typedef struct { + ai_u16 numRows; /**< number of rows of the matrix. */ + ai_u16 numCols; /**< number of columns of the matrix. */ + ai_float *pData; /**< points to the data of the matrix. */ +} ai_matrix_f32; + +/*! + * @brief general 2D matrix initialization + * @ingroup ai_lite_math_helpers + * @param S pointer to S matrix + * @param nRows number of rows of S matrix + * @param nColumns number of columns of S matrix + * @param pData pointer to S matrix data + */ +AI_INTERFACE_ENTRY +void st_mat_init_f32(ai_matrix_f32* S, + const uint16_t nRows, + const uint16_t nColumns, + float* pData); + + +/*! + * @brief general 2D matrix multiplication on float values + * @ingroup ai_lite_math_helpers + * @param pSrcA pointer to A matrix + * @param pSrcB pointer to B matrix + * @param pSrcC pointer to C matrix/array + * @param alpha multiplier of A*B product + * @param beta multiplier of C + * @param tA flag for A transpose + * @param tB flag for B transpose + * @param pDstY matrix result + * @return ARM_MATH_SUCCESS in case of success, ARM_MATH_SIZE_MISMATCH else + */ +AI_INTERFACE_ENTRY +uint32_t st_mat_gemm_f32(const ai_matrix_f32* pSrcA, + const ai_matrix_f32* pSrcB, + const ai_matrix_f32* pSrcC, + const float alpha, const float beta, + const int8_t tA, const int8_t tB, + ai_matrix_f32 * pDstY); + +/*! + * @brief platform optimized square root on a float value + * @ingroup ai_lite_math_helpers + * @param x input value + * @return square root of the value + */ +AI_INTERFACE_ENTRY +float ai_math_sqrt(const float x); + + +AI_API_DECLARE_END + +#endif /*AI_LITE_MATH_HELPERS_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_math_helpers.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_math_helpers.h similarity index 98% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_math_helpers.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_math_helpers.h index f4ca8941..1972e573 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_math_helpers.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_math_helpers.h @@ -1,569 +1,569 @@ -#ifndef AI_MATH_HELPERS_H -#define AI_MATH_HELPERS_H -/** - ****************************************************************************** - * @file ai_math_helpers.h - * @author AST Embedded Analytics Research Platform - * @brief Math helpers routines header file. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#include "ai_lite_math_helpers.h" - -//#if defined(HAS_X86) || defined(__CC_ARM) || defined(CM4) || defined(CM7) -#define _AI_CONV_2D_LOOP_UNROLLING_OPTIM -//#endif - -#define STM32_DOT_INLINE_OPTIM - -/* Modes for element wise integer optimized implementation */ -#define AI_ELTWISE_NO_SCALAR (0) -#define AI_ELTWISE_SCALAR1 (1) -#define AI_ELTWISE_SCALAR2 (2) -#define AI_ELTWISE_SCALAR_CH1 (3) -#define AI_ELTWISE_SCALAR_CH2 (4) - - -AI_API_DECLARE_BEGIN - -#if defined(STM32_DOT_INLINE_OPTIM) - -AI_DECLARE_STATIC -void __ai_math_dot_array( - ai_float* out, - const ai_float* data0, - const ai_float* data1, - ai_size data_size) -{ - register ai_float sum = 0.0f; /* Temporary result storage */ - - /* Run the below code for Cortex-M4 and Cortex-M3 */ - -#if defined(_AI_CONV_2D_LOOP_UNROLLING_OPTIM) - /* First part of the processing with loop unrolling. Compute 16 outputs at a time. - ** a second loop below computes the remaining 1 to 15 samples. */ - while (data_size >= 16u) { - register ai_vec4_float ch_in_f = AI_VEC4_FLOAT(data1); - register ai_vec4_float weights_in_f = AI_VEC4_FLOAT(data0); - sum += weights_in_f.a1 * ch_in_f.a1; - sum += weights_in_f.a2 * ch_in_f.a2; - sum += weights_in_f.a3 * ch_in_f.a3; - sum += weights_in_f.a4 * ch_in_f.a4; - data1 += 4; - data0 += 4; - - ch_in_f = AI_VEC4_FLOAT(data1); - weights_in_f = AI_VEC4_FLOAT(data0); - sum += weights_in_f.a1 * ch_in_f.a1; - sum += weights_in_f.a2 * ch_in_f.a2; - sum += weights_in_f.a3 * ch_in_f.a3; - sum += weights_in_f.a4 * ch_in_f.a4; - data1 += 4; - data0 += 4; - - ch_in_f = AI_VEC4_FLOAT(data1); - weights_in_f = AI_VEC4_FLOAT(data0); - sum += weights_in_f.a1 * ch_in_f.a1; - sum += weights_in_f.a2 * ch_in_f.a2; - sum += weights_in_f.a3 * ch_in_f.a3; - sum += weights_in_f.a4 * ch_in_f.a4; - data1 += 4; - data0 += 4; - - ch_in_f = AI_VEC4_FLOAT(data1); - weights_in_f = AI_VEC4_FLOAT(data0); - sum += weights_in_f.a1 * ch_in_f.a1; - sum += weights_in_f.a2 * ch_in_f.a2; - sum += weights_in_f.a3 * ch_in_f.a3; - sum += weights_in_f.a4 * ch_in_f.a4; - data1 += 4; - data0 += 4; - data_size -= 16u; - } - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while (data_size >= 4u) { - /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ - /* Calculate dot product and then store the result in a temporary buffer */ - sum += (*data0++) * (*data1++); - sum += (*data0++) * (*data1++); - sum += (*data0++) * (*data1++); - sum += (*data0++) * (*data1++); - - /* Decrement the loop counter */ - data_size -= 4u; - } -#endif - while (data_size > 0u) { - /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ - /* Calculate dot product and then store the result in a temporary buffer. */ - sum += (*data0++) * (*data1++); - - /* Decrement the loop counter */ - data_size--; - } - - /* Directly accumulate the result back in the destination buffer */ - *out += sum; -} - - -#undef AI_MATH_DOT_ARRAY -#define AI_MATH_DOT_ARRAY(dst, src0, src1, size) \ - { __ai_math_dot_array(dst, src0, src1, size); } - -#else /* STM32_DOT_INLINE_OPTIM */ - -#undef AI_MATH_DOT_ARRAY -#define AI_MATH_DOT_ARRAY(dst, src0, src1, size) \ - { ai_math_dot_array(dst, src0, src1, size); } - -#endif - - -/*! - * @defgroup math_helpers Math helpers - * @brief Common math functions - * - * Math functions are mapped to the underlying platform through those utility - * functions. On x86 and ARM v7 they are mapped to the float math functions in - * the C99 standard library; on MCUs they are mapped to the ARM DSP functions. - */ - -/*! - * @brief platform optimized dot product of float vectors - * - * Computes the dot product between vectors and adds the result to out. - * @ingroup math_helpers - * @param out scalar result of the dot product - * @param data0 the first float vector - * @param data1 the second float vector - * @param data_size the size of both vectors - */ -AI_INTERFACE_ENTRY -void ai_math_dot_array( - ai_float* out, - const ai_float* data0, - const ai_float* data1, - const ai_size data_size); -/*! - * @brief ErfInv a float value - * @ingroup math_helpers - * @param x input value - * @return square root of the value - */ -AI_INTERFACE_ENTRY ai_float ai_math_erfinv(const ai_float x); - -/*! - * @brief platform optimized exponential on a float value - * @ingroup math_helpers - * @param x input value - * @return exponential of the value - */ -AI_INTERFACE_ENTRY ai_float ai_math_exp(const ai_float x); - -/*! - * @brief platform logical not - * @ingroup math_helpers - * @param x input value - * @return not of the value - */ -AI_INTERFACE_ENTRY ai_bool ai_logical_not(const ai_bool x); - -/*! - * @brief platform optimized pow on a float value - * @ingroup math_helpers - * @param x input value - * @param e input value - * @return pow of the value ^ e - */ -AI_INTERFACE_ENTRY ai_float ai_math_pow(const ai_float x, const ai_float e); - -/*! - * @brief platform optimized tangent on a float value - * @ingroup math_helpers - * @param x input value - * @return hyperbolic tangent of the value - */ -AI_INTERFACE_ENTRY ai_float ai_math_tanh(const ai_float x); - -/*! - * @brief platform optimized relu on a float value - * @ingroup math_helpers - * @param x input value - * @return relu of the value ( x if x>0 else 0) - */ -AI_INTERFACE_ENTRY ai_float ai_math_relu(const ai_float x); - -/*! - * @brief platform optimized parametric relu on a float value - * @ingroup math_helpers - * @param x input value - * @param slope input value - * @return parametric relu of the value - */ -AI_INTERFACE_ENTRY ai_float ai_math_prelu(const ai_float x, const ai_float slope); - -/*! - * @brief platform optimized parametric sigmoid on a float value - * @ingroup math_helpers - * @param x input value - * @return sigmoid of the value - */ -AI_INTERFACE_ENTRY ai_float ai_math_sigmoid(const ai_float x); - -/*! - * @brief platform optimized parametric hard sigmoid on a float value - * @ingroup math_helpers - * @param x input value - * @return hard sigmoid of the value - */ -AI_INTERFACE_ENTRY ai_float ai_math_hard_sigmoid(const ai_float x); // const ai_float alpha, const ai_float beta); - -/*! - * @brief platform optimized parametric swish on a float value - * @ingroup math_helpers - * @param x input value - * @return swish of the value - */ -AI_INTERFACE_ENTRY ai_float ai_math_swish(const ai_float x); - -/*! - * @brief platform optimized parametric hard_swish on a float value - * @ingroup math_helpers - * @param x input value - * @return hard_swish of the value - */ -AI_INTERFACE_ENTRY ai_float ai_math_hard_swish(const ai_float x); - -/*! - * @brief platform optimized parametric gelu on a float value - * @ingroup math_helpers - * @param x input value - * @param aaproximate input value - * @return gelu of the value - */ -AI_INTERFACE_ENTRY ai_float ai_math_gelu(const ai_float x, const ai_bool approximate); - -/*! - * @brief platform optimized parametric sign function on a float value - * @ingroup math_helpers - * @param x input value - * @return sign of the value - */ -AI_INTERFACE_ENTRY ai_float ai_math_sign(const ai_float x); - -/*! - * @brief optimized parametric rectified linear unit on a float value - * @ingroup math_helpers - * @param x input value - * @param slope parameter value - * @return x if x is positive and x*slope otherwise - */ -AI_INTERFACE_ENTRY ai_float ai_fast_prelu(const ai_float x, const ai_float slope); - -AI_INTERFACE_ENTRY void ai_div(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_div_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_div_f32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_div_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_div_s32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_div_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_div_s16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_div_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_div_s8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_div_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_div_u32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_div_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_div_u16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_div_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_div_u8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_div_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_div_buffer_INT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, - const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, - const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); -AI_INTERFACE_ENTRY void ai_div_buffer_UINT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, - const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, - const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); - -AI_INTERFACE_ENTRY void ai_bitshift_right(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_bitshift_right_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_bitshift_right_u32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_bitshift_right_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_bitshift_right_u16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_bitshift_right_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_bitshift_right_u8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_bitshift_right_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_bitshift_left(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_bitshift_left_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_bitshift_left_u32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_bitshift_left_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_bitshift_left_u16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_bitshift_left_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_bitshift_left_u8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_bitshift_left_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); - -AI_INTERFACE_ENTRY void ai_floor_div(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_floor_div_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_floor_mod(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_floor_mod_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); - -AI_INTERFACE_ENTRY void ai_mod(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_mod_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_mod_f32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_mod_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_mod_s32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_mod_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_mod_s16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_mod_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_mod_s8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_mod_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_mod_u32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_mod_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_mod_u16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_mod_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_mod_u8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_mod_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); - -AI_INTERFACE_ENTRY void ai_max(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_max_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_max_f32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_max_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_max_s32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_max_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_max_s16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_max_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_max_s8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_max_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_max_u32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_max_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_max_u16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_max_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_max_u8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_max_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_max_buffer_INT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, - const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, - const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); -AI_INTERFACE_ENTRY void ai_max_buffer_UINT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, - const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, - const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); - -AI_INTERFACE_ENTRY void ai_min(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_min_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_min_f32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_min_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_min_s32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_min_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_min_s16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_min_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_min_s8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_min_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_min_u32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_min_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_min_u16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_min_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_min_u8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_min_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_min_buffer_INT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, - const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, - const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); -AI_INTERFACE_ENTRY void ai_min_buffer_UINT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, - const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, - const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); - -AI_INTERFACE_ENTRY void ai_mul(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_mul_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_mul_f32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_mul_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_mul_s32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_mul_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_mul_s16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_mul_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_mul_s8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_mul_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_mul_u32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_mul_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_mul_u16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_mul_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_mul_u8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_mul_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_mul_buffer_INT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, - const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, - const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); -AI_INTERFACE_ENTRY void ai_mul_buffer_UINT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, - const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, - const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); - -AI_INTERFACE_ENTRY void ai_pow(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_pow_buffer(ai_handle out, const ai_handle b, const ai_handle e, const ai_size loop); - -AI_INTERFACE_ENTRY void ai_sub(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_sub_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_sub_f32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_sub_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_sub_s32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_sub_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_sub_s16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_sub_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_sub_s8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_sub_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_sub_u32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_sub_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_sub_u16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_sub_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_sub_u8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_sub_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_sub_buffer_INT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, - const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, - const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); -AI_INTERFACE_ENTRY void ai_sub_buffer_UINT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, - const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, - const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); - -AI_INTERFACE_ENTRY void ai_sum(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_sum_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_sum_f32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_sum_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_sum_s32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_sum_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_sum_s16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_sum_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_sum_s8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_sum_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_sum_u32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_sum_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_sum_u16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_sum_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_sum_u8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_sum_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_sum_buffer_INT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, - const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, - const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); -AI_INTERFACE_ENTRY void ai_sum_buffer_UINT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, - const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, - const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); - -AI_INTERFACE_ENTRY void ai_and(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_and_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_or(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_or_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_xor(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_xor_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); - -AI_INTERFACE_ENTRY void ai_greater(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_greater_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_greater_f32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_greater_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_greater_s32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_greater_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_greater_s16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_greater_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_greater_s8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_greater_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_greater_u32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_greater_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_greater_u16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_greater_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_greater_u8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_greater_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); - -AI_INTERFACE_ENTRY void ai_greater_or_equal(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_greater_or_equal_f32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_greater_or_equal_s32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_greater_or_equal_s16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_greater_or_equal_s8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_greater_or_equal_u32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_greater_or_equal_u16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_greater_or_equal_u8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); - -AI_INTERFACE_ENTRY void ai_less(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_less_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_less_f32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_less_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_less_s32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_less_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_less_s16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_less_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_less_s8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_less_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_less_u32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_less_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_less_u16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_less_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_less_u8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_less_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); - -AI_INTERFACE_ENTRY void ai_less_or_equal(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_less_or_equal_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_less_or_equal_f32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_less_or_equal_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_less_or_equal_s32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_less_or_equal_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_less_or_equal_s16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_less_or_equal_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_less_or_equal_s8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_less_or_equal_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_less_or_equal_u32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_less_or_equal_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_less_or_equal_u16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_less_or_equal_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_less_or_equal_u8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_less_or_equal_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); - -AI_INTERFACE_ENTRY void ai_equal(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_equal_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_equal_f32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_equal_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_equal_s32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_equal_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_equal_s16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_equal_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_equal_s8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_equal_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_equal_u32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_equal_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_equal_u16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_equal_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_equal_u8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_equal_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); - -AI_INTERFACE_ENTRY void ai_not_equal(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_not_equal_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_not_equal_f32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_not_equal_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_not_equal_s32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_not_equal_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_not_equal_s16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_not_equal_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_not_equal_s8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_not_equal_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_not_equal_u32(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_not_equal_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_not_equal_u16(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_not_equal_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); -AI_INTERFACE_ENTRY void ai_not_equal_u8(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_not_equal_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); - -AI_INTERFACE_ENTRY void ai_squared_diff(ai_handle out, const ai_handle a, const ai_handle b); -AI_INTERFACE_ENTRY void ai_squared_diff_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); - -AI_API_DECLARE_END - -#endif /* AI_MATH_HELPERS_H */ +#ifndef AI_MATH_HELPERS_H +#define AI_MATH_HELPERS_H +/** + ****************************************************************************** + * @file ai_math_helpers.h + * @author AST Embedded Analytics Research Platform + * @brief Math helpers routines header file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#include "ai_lite_math_helpers.h" + +//#if defined(HAS_X86) || defined(__CC_ARM) || defined(CM4) || defined(CM7) +#define _AI_CONV_2D_LOOP_UNROLLING_OPTIM +//#endif + +#define STM32_DOT_INLINE_OPTIM + +/* Modes for element wise integer optimized implementation */ +#define AI_ELTWISE_NO_SCALAR (0) +#define AI_ELTWISE_SCALAR1 (1) +#define AI_ELTWISE_SCALAR2 (2) +#define AI_ELTWISE_SCALAR_CH1 (3) +#define AI_ELTWISE_SCALAR_CH2 (4) + + +AI_API_DECLARE_BEGIN + +#if defined(STM32_DOT_INLINE_OPTIM) + +AI_DECLARE_STATIC +void __ai_math_dot_array( + ai_float* out, + const ai_float* data0, + const ai_float* data1, + ai_size data_size) +{ + register ai_float sum = 0.0f; /* Temporary result storage */ + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + +#if defined(_AI_CONV_2D_LOOP_UNROLLING_OPTIM) + /* First part of the processing with loop unrolling. Compute 16 outputs at a time. + ** a second loop below computes the remaining 1 to 15 samples. */ + while (data_size >= 16u) { + register ai_vec4_float ch_in_f = AI_VEC4_FLOAT(data1); + register ai_vec4_float weights_in_f = AI_VEC4_FLOAT(data0); + sum += weights_in_f.a1 * ch_in_f.a1; + sum += weights_in_f.a2 * ch_in_f.a2; + sum += weights_in_f.a3 * ch_in_f.a3; + sum += weights_in_f.a4 * ch_in_f.a4; + data1 += 4; + data0 += 4; + + ch_in_f = AI_VEC4_FLOAT(data1); + weights_in_f = AI_VEC4_FLOAT(data0); + sum += weights_in_f.a1 * ch_in_f.a1; + sum += weights_in_f.a2 * ch_in_f.a2; + sum += weights_in_f.a3 * ch_in_f.a3; + sum += weights_in_f.a4 * ch_in_f.a4; + data1 += 4; + data0 += 4; + + ch_in_f = AI_VEC4_FLOAT(data1); + weights_in_f = AI_VEC4_FLOAT(data0); + sum += weights_in_f.a1 * ch_in_f.a1; + sum += weights_in_f.a2 * ch_in_f.a2; + sum += weights_in_f.a3 * ch_in_f.a3; + sum += weights_in_f.a4 * ch_in_f.a4; + data1 += 4; + data0 += 4; + + ch_in_f = AI_VEC4_FLOAT(data1); + weights_in_f = AI_VEC4_FLOAT(data0); + sum += weights_in_f.a1 * ch_in_f.a1; + sum += weights_in_f.a2 * ch_in_f.a2; + sum += weights_in_f.a3 * ch_in_f.a3; + sum += weights_in_f.a4 * ch_in_f.a4; + data1 += 4; + data0 += 4; + data_size -= 16u; + } + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (data_size >= 4u) { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer */ + sum += (*data0++) * (*data1++); + sum += (*data0++) * (*data1++); + sum += (*data0++) * (*data1++); + sum += (*data0++) * (*data1++); + + /* Decrement the loop counter */ + data_size -= 4u; + } +#endif + while (data_size > 0u) { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer. */ + sum += (*data0++) * (*data1++); + + /* Decrement the loop counter */ + data_size--; + } + + /* Directly accumulate the result back in the destination buffer */ + *out += sum; +} + + +#undef AI_MATH_DOT_ARRAY +#define AI_MATH_DOT_ARRAY(dst, src0, src1, size) \ + { __ai_math_dot_array(dst, src0, src1, size); } + +#else /* STM32_DOT_INLINE_OPTIM */ + +#undef AI_MATH_DOT_ARRAY +#define AI_MATH_DOT_ARRAY(dst, src0, src1, size) \ + { ai_math_dot_array(dst, src0, src1, size); } + +#endif + + +/*! + * @defgroup math_helpers Math helpers + * @brief Common math functions + * + * Math functions are mapped to the underlying platform through those utility + * functions. On x86 and ARM v7 they are mapped to the float math functions in + * the C99 standard library; on MCUs they are mapped to the ARM DSP functions. + */ + +/*! + * @brief platform optimized dot product of float vectors + * + * Computes the dot product between vectors and adds the result to out. + * @ingroup math_helpers + * @param out scalar result of the dot product + * @param data0 the first float vector + * @param data1 the second float vector + * @param data_size the size of both vectors + */ +AI_INTERFACE_ENTRY +void ai_math_dot_array( + ai_float* out, + const ai_float* data0, + const ai_float* data1, + const ai_size data_size); +/*! + * @brief ErfInv a float value + * @ingroup math_helpers + * @param x input value + * @return square root of the value + */ +AI_INTERFACE_ENTRY ai_float ai_math_erfinv(const ai_float x); + +/*! + * @brief platform optimized exponential on a float value + * @ingroup math_helpers + * @param x input value + * @return exponential of the value + */ +AI_INTERFACE_ENTRY ai_float ai_math_exp(const ai_float x); + +/*! + * @brief platform logical not + * @ingroup math_helpers + * @param x input value + * @return not of the value + */ +AI_INTERFACE_ENTRY ai_bool ai_logical_not(const ai_bool x); + +/*! + * @brief platform optimized pow on a float value + * @ingroup math_helpers + * @param x input value + * @param e input value + * @return pow of the value ^ e + */ +AI_INTERFACE_ENTRY ai_float ai_math_pow(const ai_float x, const ai_float e); + +/*! + * @brief platform optimized tangent on a float value + * @ingroup math_helpers + * @param x input value + * @return hyperbolic tangent of the value + */ +AI_INTERFACE_ENTRY ai_float ai_math_tanh(const ai_float x); + +/*! + * @brief platform optimized relu on a float value + * @ingroup math_helpers + * @param x input value + * @return relu of the value ( x if x>0 else 0) + */ +AI_INTERFACE_ENTRY ai_float ai_math_relu(const ai_float x); + +/*! + * @brief platform optimized parametric relu on a float value + * @ingroup math_helpers + * @param x input value + * @param slope input value + * @return parametric relu of the value + */ +AI_INTERFACE_ENTRY ai_float ai_math_prelu(const ai_float x, const ai_float slope); + +/*! + * @brief platform optimized parametric sigmoid on a float value + * @ingroup math_helpers + * @param x input value + * @return sigmoid of the value + */ +AI_INTERFACE_ENTRY ai_float ai_math_sigmoid(const ai_float x); + +/*! + * @brief platform optimized parametric hard sigmoid on a float value + * @ingroup math_helpers + * @param x input value + * @return hard sigmoid of the value + */ +AI_INTERFACE_ENTRY ai_float ai_math_hard_sigmoid(const ai_float x); // const ai_float alpha, const ai_float beta); + +/*! + * @brief platform optimized parametric swish on a float value + * @ingroup math_helpers + * @param x input value + * @return swish of the value + */ +AI_INTERFACE_ENTRY ai_float ai_math_swish(const ai_float x); + +/*! + * @brief platform optimized parametric hard_swish on a float value + * @ingroup math_helpers + * @param x input value + * @return hard_swish of the value + */ +AI_INTERFACE_ENTRY ai_float ai_math_hard_swish(const ai_float x); + +/*! + * @brief platform optimized parametric gelu on a float value + * @ingroup math_helpers + * @param x input value + * @param aaproximate input value + * @return gelu of the value + */ +AI_INTERFACE_ENTRY ai_float ai_math_gelu(const ai_float x, const ai_bool approximate); + +/*! + * @brief platform optimized parametric sign function on a float value + * @ingroup math_helpers + * @param x input value + * @return sign of the value + */ +AI_INTERFACE_ENTRY ai_float ai_math_sign(const ai_float x); + +/*! + * @brief optimized parametric rectified linear unit on a float value + * @ingroup math_helpers + * @param x input value + * @param slope parameter value + * @return x if x is positive and x*slope otherwise + */ +AI_INTERFACE_ENTRY ai_float ai_fast_prelu(const ai_float x, const ai_float slope); + +AI_INTERFACE_ENTRY void ai_div(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_div_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_div_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_div_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_div_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_div_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_div_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_div_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_div_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_div_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_div_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_div_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_div_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_div_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_div_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_div_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_div_buffer_INT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); +AI_INTERFACE_ENTRY void ai_div_buffer_UINT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); + +AI_INTERFACE_ENTRY void ai_bitshift_right(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_bitshift_right_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_bitshift_right_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_bitshift_right_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_bitshift_right_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_bitshift_right_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_bitshift_right_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_bitshift_right_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_bitshift_left(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_bitshift_left_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_bitshift_left_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_bitshift_left_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_bitshift_left_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_bitshift_left_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_bitshift_left_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_bitshift_left_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_floor_div(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_floor_div_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_floor_mod(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_floor_mod_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_mod(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mod_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mod_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mod_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mod_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mod_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mod_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mod_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mod_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mod_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mod_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mod_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mod_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mod_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mod_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mod_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_max(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_max_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_max_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_max_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_max_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_max_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_max_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_max_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_max_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_max_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_max_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_max_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_max_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_max_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_max_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_max_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_max_buffer_INT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); +AI_INTERFACE_ENTRY void ai_max_buffer_UINT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); + +AI_INTERFACE_ENTRY void ai_min(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_min_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_min_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_min_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_min_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_min_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_min_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_min_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_min_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_min_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_min_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_min_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_min_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_min_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_min_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_min_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_min_buffer_INT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); +AI_INTERFACE_ENTRY void ai_min_buffer_UINT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); + +AI_INTERFACE_ENTRY void ai_mul(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mul_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mul_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mul_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mul_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mul_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mul_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mul_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mul_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mul_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mul_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mul_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mul_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mul_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mul_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_mul_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_mul_buffer_INT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); +AI_INTERFACE_ENTRY void ai_mul_buffer_UINT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); + +AI_INTERFACE_ENTRY void ai_pow(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_pow_buffer(ai_handle out, const ai_handle b, const ai_handle e, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_sub(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sub_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sub_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sub_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sub_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sub_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sub_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sub_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sub_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sub_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sub_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sub_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sub_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sub_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sub_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sub_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sub_buffer_INT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); +AI_INTERFACE_ENTRY void ai_sub_buffer_UINT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); + +AI_INTERFACE_ENTRY void ai_sum(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sum_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sum_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sum_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sum_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sum_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sum_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sum_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sum_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sum_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sum_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sum_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sum_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sum_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sum_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_sum_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_sum_buffer_INT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); +AI_INTERFACE_ENTRY void ai_sum_buffer_UINT8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle pScale1, const ai_handle pZp1, const ai_handle pScale2, const ai_handle pZp2, + const ai_handle pScaleout, const ai_handle pZpout, const ai_i32 scalar_op); + +AI_INTERFACE_ENTRY void ai_and(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_and_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_or(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_or_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_xor(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_xor_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_greater(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_greater_or_equal(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_or_equal_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_or_equal_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_or_equal_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_or_equal_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_or_equal_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_or_equal_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_greater_or_equal_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_greater_or_equal_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_less(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_less_or_equal(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_or_equal_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_or_equal_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_or_equal_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_or_equal_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_or_equal_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_or_equal_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_or_equal_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_or_equal_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_or_equal_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_or_equal_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_or_equal_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_or_equal_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_or_equal_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_less_or_equal_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_less_or_equal_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_equal(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_equal_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_equal_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_equal_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_equal_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_equal_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_equal_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_equal_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_equal_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_equal_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_equal_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_equal_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_equal_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_equal_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_equal_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_equal_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_not_equal(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_not_equal_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_not_equal_f32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_not_equal_buffer_f32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_not_equal_s32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_not_equal_buffer_s32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_not_equal_s16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_not_equal_buffer_s16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_not_equal_s8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_not_equal_buffer_s8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_not_equal_u32(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_not_equal_buffer_u32(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_not_equal_u16(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_not_equal_buffer_u16(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); +AI_INTERFACE_ENTRY void ai_not_equal_u8(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_not_equal_buffer_u8(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_INTERFACE_ENTRY void ai_squared_diff(ai_handle out, const ai_handle a, const ai_handle b); +AI_INTERFACE_ENTRY void ai_squared_diff_buffer(ai_handle out, const ai_handle a, const ai_handle b, const ai_size loop); + +AI_API_DECLARE_END + +#endif /* AI_MATH_HELPERS_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_platform.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_platform.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_platform.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_platform.h index 33528e2e..cc7ed014 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_platform.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_platform.h @@ -1,961 +1,961 @@ -/** - ****************************************************************************** - * @file ai_platform.h - * @author AST Embedded Analytics Research Platform - * @brief Definitions of AI platform public APIs types - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef AI_PLATFORM_H -#define AI_PLATFORM_H - -#include -#include - -#define __STDC_FORMAT_MACROS 1 -#include - -#ifndef AI_PLATFORM_API_MAJOR -#define AI_PLATFORM_API_MAJOR (1) -#endif -#ifndef AI_PLATFORM_API_MINOR -#define AI_PLATFORM_API_MINOR (2) -#endif -#ifndef AI_PLATFORM_API_MICRO -#define AI_PLATFORM_API_MICRO (0) -#endif - -#define AI_PLATFORM_API_VERSION \ - AI_VERSION(AI_PLATFORM_API_MAJOR, \ - AI_PLATFORM_API_MINOR, \ - AI_PLATFORM_API_MICRO) - - -#ifndef AI_TOOLS_API_VERSION_MAJOR -#define AI_TOOLS_API_VERSION_MAJOR (1) -#endif -#ifndef AI_TOOLS_API_VERSION_MINOR -#define AI_TOOLS_API_VERSION_MINOR (5) -#endif -#ifndef AI_TOOLS_API_VERSION_MICRO -#define AI_TOOLS_API_VERSION_MICRO (0) -#endif - -/*****************************************************************************/ -#define AI_TOOLS_API_VERSION \ - AI_VERSION(AI_TOOLS_API_VERSION_MAJOR, \ - AI_TOOLS_API_VERSION_MINOR, \ - AI_TOOLS_API_VERSION_MICRO) - -#define AI_TOOLS_API_VERSION_1_3 \ - AI_VERSION(1, 3, 0) - -#define AI_TOOLS_API_VERSION_1_4 \ - AI_VERSION(1, 4, 0) - -#define AI_TOOLS_API_VERSION_1_5 \ - AI_VERSION(1, 5, 0) - -/*****************************************************************************/ -#ifdef __cplusplus -#define AI_API_DECLARE_BEGIN extern "C" { -#define AI_API_DECLARE_END } -#else -#include -#define AI_API_DECLARE_BEGIN /* AI_API_DECLARE_BEGIN */ -#define AI_API_DECLARE_END /* AI_API_DECLARE_END */ -#endif - -/*****************************************************************************/ -#define AI_FLAG_NONE (0x0) - -/*****************************************************************************/ -AI_API_DECLARE_BEGIN - -/*! - * @typedef ai_flags - * @ingroup ai_platform - * @brief bitmask for flags management - */ -typedef uint32_t ai_flags; - -/*****************************************************************************/ -#define AI_CONCAT_ARG(a, b) a ## b -#define AI_CONCAT(a, b) AI_CONCAT_ARG(a, b) - -/*! AI_CAST SECTION ***********************************/ -#define AI_CAST(type_, expr_) ((type_)(expr_)) - -/*****************************************************************************/ -#define AI_MAGIC_SIGNATURE \ - (0xa1facade) - -#define AI_PACK(...) \ - __VA_ARGS__ - -/*****************************************************************************/ -#define AI_SHAPE_BCWH (0x01u) - -/*! - * @typedef ai_shape_dimension - * @ingroup ai_platform - * @brief shape dimension type to be used in shape related structs @ref ai_buffer_shape - */ -typedef uint32_t ai_shape_dimension; - -/*****************************************************************************/ -#if defined(_MSC_VER) - #define AI_API_ENTRY __declspec(dllexport) - #define AI_ALIGNED(x) /* AI_ALIGNED(x) */ -#elif defined(__ICCARM__) || defined (__IAR_SYSTEMS_ICC__) - #define AI_API_ENTRY /* AI_API_ENTRY */ - #define AI_ALIGNED(x) AI_CONCAT(AI_ALIGNED_,x) - #define AI_ALIGNED_1 _Pragma("data_alignment = 1") - #define AI_ALIGNED_2 _Pragma("data_alignment = 2") - #define AI_ALIGNED_4 _Pragma("data_alignment = 4") - #define AI_ALIGNED_8 _Pragma("data_alignment = 8") - #define AI_ALIGNED_16 _Pragma("data_alignment = 16") - #define AI_ALIGNED_32 _Pragma("data_alignment = 32") -#elif defined(__CC_ARM) - #define AI_API_ENTRY __attribute__((visibility("default"))) - #define AI_ALIGNED(x) __attribute__((aligned (x))) - /* Keil disallows anonymous union initialization by default */ - #pragma anon_unions -#elif defined(__GNUC__) - //#define AI_API_ENTRY __attribute__((visibility("default"))) - #define AI_API_ENTRY /* AI_API_ENTRY */ - #define AI_ALIGNED(x) __attribute__((aligned(x))) -#else - /* Dynamic libraries are not supported by the compiler */ - #define AI_API_ENTRY /* AI_API_ENTRY */ - #define AI_ALIGNED(x) /* AI_ALIGNED(x) */ -#endif - -#define AI_HANDLE_PTR(ptr_) ((ai_handle)(ptr_)) -#define AI_HANDLE_NULL AI_HANDLE_PTR(NULL) - -#define AI_HANDLE_FUNC_PTR(func) ((ai_handle_func)(func)) - -#define AI_UNUSED(x) (void)(x); - -#define AI_DEPRECATED /* AI_DEPRECATED */ - -#define AI_LEGACY /* AI_LEGACY */ - -#define AI_MAGIC_MARKER (0xA1FACADE) - - -#if defined(__cplusplus) - #define AI_STRUCT_INIT {} - #define AI_C_ARRAY_INIT {} -#else - #define AI_STRUCT_INIT {0} - #define AI_C_ARRAY_INIT {0} -#endif - -#define AI_ERROR_FMT AIU32_FMT - -#define AI_IS_UNSIGNED(type) \ - ((((type)0) - 1) > 0) - -#define AI_CUSTOM_SIZE(type) \ - (ai_custom_type_signature)((AI_IS_UNSIGNED(type)) \ - ? (0x80|(sizeof(type)&0x7f)) : (sizeof(type)&0x7f)) - -/*! network buffers struct handlers *******************************************/ -#ifdef __cplusplus - -#define AI_NETWORK_PARAMS_INIT(params_, activations_) \ -{ \ - {{ params_, activations_ }} \ -} - -#define AI_NETWORK_BUFFERS_INIT(weights_buffers_, activations_buffers_) \ -{ \ - AI_MAGIC_SIGNATURE, AI_PACK(weights_buffers_), AI_PACK(activations_buffers_) \ -} - -#else - -#define AI_NETWORK_PARAMS_INIT(params_, activations_) \ -{ \ - .params = params_, \ - .activations = activations_ \ -} - -#define AI_NETWORK_BUFFERS_INIT(weights_buffers_, activations_buffers_) \ -{ \ - .map_signature = AI_MAGIC_SIGNATURE, \ - .map_weights = AI_PACK(weights_buffers_), \ - .map_activations = AI_PACK(activations_buffers_) \ -} - -#endif // __cplusplus - - -/*! binary padded bits macro helpers *****************************************/ -#define AI_PBITS_MASK \ - (0x1F) - -#define AI_PBITS_SHIFTS \ - (5) - -#define AI_PBITS_PADDED_BYTES_COUNT(bits_) \ - (((ai_u32)(bits_) + 7) >> 3) - -#define AI_PBITS_PADDED_WORDS_COUNT(bits_) \ - (((ai_size)(bits_) + AI_PBITS_MASK) >> AI_PBITS_SHIFTS) - -#define AI_PBITS_GET_WORD(word_ptr_, bits_) \ - (((ai_pbits*)(word_ptr_)) + ((bits_) >> AI_PBITS_SHIFTS)) - -#define AI_PAD_CHANNELS(format_, channels_) \ - ((AI_BUFFER_FMT_GET_BITS(format_)==1) ? (AI_PBITS_PADDED_WORDS_COUNT(channels_) << AI_PBITS_SHIFTS) : (channels_)) - - -/*! ai_intq_info struct handlers *********************************************/ -#define INTQ_CONST const -// #define INTQ_CONST - -#define AI_INTQ_INFO_LIST(list_) \ - ((list_)->info) - -#define AI_INTQ_INFO_LIST_FLAGS(list_) \ - ((list_) ? (list_)->flags : 0) - -#define AI_INTQ_INFO_LIST_SIZE(list_) \ - ((list_) ? (list_)->size : 0) - -#define AI_HAS_INTQ_INFO_LIST(list_) \ - ((list_) ? (((list_)->info) && ((list_)->size>0)) : false) - -#define AI_INTQ_INFO_LIST_SCALE(list_, type_, pos_) \ - (((list_) && (list_)->info && ((pos_)<(list_)->size)) \ - ? ((type_*)((list_)->info->scale))[(pos_)] : 0) - -#define AI_INTQ_INFO_LIST_ZEROPOINT(list_, type_, pos_) \ - (((list_) && (list_)->info && ((pos_)<(list_)->size)) \ - ? ((type_*)((list_)->info->zeropoint))[(pos_)] : 0) - -/*! ai_buffer format handlers ************************************************/ - -/*! - * @enum buffer format definition - * @ingroup ai_platform - * - * 32 bit signed format list. - */ -typedef int32_t ai_buffer_format; - -/*! ai_buffer_meta flags & macros ********************************************/ -#define AI_BUFFER_META_HAS_INTQ_INFO (0x1U << 0) -#define AI_BUFFER_META_FLAG_SCALE_FLOAT (0x1U << 0) -#define AI_BUFFER_META_FLAG_ZEROPOINT_U8 (0x1U << 1) -#define AI_BUFFER_META_FLAG_ZEROPOINT_S8 (0x1U << 2) -#define AI_BUFFER_META_FLAG_ZEROPOINT_U16 (0x1U << 3) -#define AI_BUFFER_META_FLAG_ZEROPOINT_S16 (0x1U << 4) - -/*! ai_buffer format variable flags & macros *********************************/ -#define AI_BUFFER_FMT_TYPE_NONE (0x0) -#define AI_BUFFER_FMT_TYPE_FLOAT (0x1) -#define AI_BUFFER_FMT_TYPE_Q (0x2) -#define AI_BUFFER_FMT_TYPE_BOOL (0x3) - -#define AI_BUFFER_FMT_FLAG_CONST (0x1U<<30) -#define AI_BUFFER_FMT_FLAG_STATIC (0x1U<<29) -#define AI_BUFFER_FMT_FLAG_IS_IO (0x1U<<27) -#define AI_BUFFER_FMT_FLAG_PERSISTENT (0x1U<<29) - - -#define AI_BUFFER_FMT_PACK(value_, mask_, bits_) \ - ( ((value_) & (mask_)) << (bits_) ) - -#define AI_BUFFER_FMT_UNPACK(fmt_, mask_, bits_) \ - ( (AI_BUFFER_FMT_OBJ(fmt_) >> (bits_)) & (mask_) ) - -#define AI_BUFFER_FMT_OBJ(fmt_) \ - ((ai_buffer_format)(fmt_)) - -#define AI_BUFFER_FMT_GET_FLOAT(fmt_) \ - AI_BUFFER_FMT_UNPACK(fmt_, 0x1, 24) - -#define AI_BUFFER_FMT_GET_SIGN(fmt_) \ - AI_BUFFER_FMT_UNPACK(fmt_, 0x1, 23) - -#define AI_BUFFER_FMT_GET_TYPE(fmt_) \ - AI_BUFFER_FMT_UNPACK(fmt_, 0xF, 17) - -#define AI_BUFFER_FMT_GET_BITS(fmt_) \ - AI_BUFFER_FMT_UNPACK(fmt_, 0x7F, 7) - -#define AI_BUFFER_FMT_SET_BITS(bits_) \ - AI_BUFFER_FMT_PACK((bits_), 0x7F, 7) - -#define AI_BUFFER_FMT_GET_FBITS(fmt_) \ - ( (ai_i8)AI_BUFFER_FMT_UNPACK(fmt_, 0x7F, 0) - 64 ) - -#define AI_BUFFER_FMT_SET_FBITS(fbits_) \ - AI_BUFFER_FMT_PACK((fbits_)+64, 0x7F, 0) - -#define AI_BUFFER_FMT_SET(type_id_, sign_bit_, float_bit_, bits_, fbits_) \ - AI_BUFFER_FMT_OBJ( \ - AI_BUFFER_FMT_PACK(float_bit_, 0x1, 24) | \ - AI_BUFFER_FMT_PACK(sign_bit_, 0x1, 23) | \ - AI_BUFFER_FMT_PACK(0, 0x3, 21) | \ - AI_BUFFER_FMT_PACK(type_id_, 0xF, 17) | \ - AI_BUFFER_FMT_PACK(0, 0x7, 14) | \ - AI_BUFFER_FMT_SET_BITS(bits_) | \ - AI_BUFFER_FMT_SET_FBITS(fbits_) \ - ) - -#define AI_BUFFER_FMT_SAME(fmt1_, fmt2_) \ - ( AI_BUFFER_FMT_GET(fmt1_) == AI_BUFFER_FMT_GET(fmt2_) ) - -#define AI_BUFFER_FMT_GET(fmt_) \ - (AI_BUFFER_FMT_OBJ(fmt_) & 0x01FFFFFF) - -#define AI_BUFFER_FORMAT(buf_) \ - AI_BUFFER_FMT_GET((buf_)->format) - - -/*! - * @define shape type index - * @ingroup ai_platform - * @brief positional ID for generic shapes C structs - */ -#define AI_SHAPE_EXTENSION (0x5) -#define AI_SHAPE_DEPTH (0x4) -#define AI_SHAPE_HEIGHT (0x3) -#define AI_SHAPE_WIDTH (0x2) -#define AI_SHAPE_CHANNEL (0x1) -#define AI_SHAPE_IN_CHANNEL (0x0) -#define AI_SHAPE_BATCH (0x0) -#define AI_SHAPE_TIME (0x0) - - -AI_DEPRECATED -#define AI_BUFFER_WIDTH(buf_) \ - ((buf_)->shape.data[AI_SHAPE_WIDTH]) - -AI_DEPRECATED -#define AI_BUFFER_HEIGHT(buf_) \ - ((buf_)->shape.data[AI_SHAPE_HEIGHT]) - -AI_DEPRECATED -#define AI_BUFFER_CHANNELS(buf_) \ - ((buf_)->shape.data[AI_SHAPE_CHANNEL]) - -AI_DEPRECATED -#define AI_BUFFER_N_BATCHES(buf_) \ - ((buf_)->shape.data[AI_SHAPE_BATCH]) - -#define AI_BUFFER_DATA(buf_, type_) \ - ((type_*)((buf_)->data)) - -#define AI_BUFFER_META_INFO(buf_) \ - ((buf_)->meta_info) - -#define AI_BUFFER_META_INFO_INTQ(meta_) \ - ((meta_) && ((meta_)->flags & AI_BUFFER_META_HAS_INTQ_INFO)) \ - ? ((meta_)->intq_info) : NULL - -#define AI_BUFFER_META_INFO_INTQ_GET_SIZE(meta_) \ - ( (AI_BUFFER_META_INFO_INTQ(meta_)) \ - ? AI_INTQ_INFO_LIST_SIZE(AI_BUFFER_META_INFO_INTQ(meta_)) \ - : 0 ) - -#define AI_BUFFER_META_INFO_INTQ_GET_SCALE(meta_, pos_) \ - ( (AI_BUFFER_META_INFO_INTQ(meta_)) \ - ? AI_INTQ_INFO_LIST_SCALE(AI_BUFFER_META_INFO_INTQ(meta_), ai_float, pos_) \ - : 0 ) - -#define AI_BUFFER_META_INFO_INTQ_GET_ZEROPOINT(meta_, pos_) \ - ( (AI_BUFFER_META_INFO_INTQ(meta_)) \ - ? ((AI_INTQ_INFO_LIST_FLAGS(AI_BUFFER_META_INFO_INTQ(meta_))&AI_BUFFER_META_FLAG_ZEROPOINT_U8) \ - ? AI_INTQ_INFO_LIST_ZEROPOINT(AI_BUFFER_META_INFO_INTQ(meta_), ai_u8, pos_) \ - : AI_INTQ_INFO_LIST_ZEROPOINT(AI_BUFFER_META_INFO_INTQ(meta_), ai_i8, pos_) ) \ - : 0 ) - -#define AI_BUFFER_META_INFO_INIT(flags_, intq_info_) { \ - .flags = (flags_), \ - .intq_info = AI_PACK(intq_info_) \ -} - -#define AI_BUFFER_SIZE(buf_) \ - ai_buffer_get_size(buf_, true) - -#define AI_BUFFER_SIZE_UNPAD(buf_) \ - ai_buffer_get_size(buf_, false) - -#define AI_BUFFER_BYTE_SIZE(count_, fmt_) \ - ai_buffer_get_byte_size(count_, fmt_) - -#define AI_BUFFER_FLAGS(buf_) \ - ((buf_) ? (buf_)->flags : 0x0) - -#define AI_BUFFER_SHAPE_INIT(type_, size_, ...) \ -{ \ - .type = (type_), \ - .size = (size_), \ - .data = (ai_shape_dimension[]){ __VA_ARGS__ } \ -} - -#define AI_BUFFER_SHAPE_INIT_FROM_ARRAY(type_, size_, array_ptr_) \ -{ \ - .type = (type_), \ - .size = (size_), \ - .data = (ai_shape_dimension*)(array_ptr_) \ -} - -#define AI_BUFFER_SHAPE_SIZE(buf_) \ - ((buf_) ? (buf_)->shape.size : 0) - -#define AI_BUFFER_SHAPE_TYPE(buf_) \ - ((buf_) ? (buf_)->shape.type : 0) - -#if defined(HAS_AI_ASSERT) && defined(AI_ASSERT) - -#define AI_BUFFER_SET_SHAPE_ELEM(buf_, pos_, value_) { \ - AI_ASSERT(buf_) \ - (buf_)->shape.data[pos_] = (value_); \ -} - -#define AI_BUFFER_SHAPE_ELEM(buf_, pos_) \ - (((pos_)shape.data[pos_] : 0) - -#else - -#define AI_BUFFER_SET_SHAPE_ELEM(buf_, pos_, value_) { \ - (buf_)->shape.data[pos_] = (value_); \ -} - -#define AI_BUFFER_SHAPE_ELEM(buf_, pos_) \ - (buf_)->shape.data[pos_] - -#endif - - -AI_DEPRECATED -#define AI_BUFFER_OBJ_INIT(format_, h_, w_, ch_, n_batches_, data_) \ -{ .format = (ai_buffer_format)(format_), \ - .data = (ai_handle)(data_), \ - .meta_info = NULL, \ - .flags = AI_FLAG_NONE, \ - .size = (h_) * (w_) * AI_PAD_CHANNELS(format_, ch_), \ - .shape = AI_BUFFER_SHAPE_INIT(AI_SHAPE_BCWH, 4, (n_batches_), (ch_), (w_), (h_)), \ -} - -/* 7.1 new macro API */ -#define AI_BUFFER_INIT(flags_, format_, shape_, size_, meta_info_, data_) \ -{ .format = (ai_buffer_format)(format_), \ - .data = (ai_handle)(data_), \ - .meta_info = (meta_info_), \ - .flags = (flags_), \ - .size = (size_), \ - .shape = AI_PACK(shape_) \ -} - -/* 7.1 new macro API */ -#define AI_BUFFER_INIT_STATIC(type_, flags_, format_, shape_, size_, meta_info_, ...) \ -{ .format = (ai_buffer_format)(format_), \ - .data = (ai_handle)((type_[]){__VA_ARGS__}), \ - .meta_info = (meta_info_), \ - .flags = (flags_), \ - .size = (size_), \ - .shape = AI_PACK(shape_) \ -} - -/*****************************************************************************/ -#define AI_NETWORK_BUFFERS_FIELD_DECLARE \ - ai_signature map_signature; /*! structure signature (required!) */ \ - ai_buffer_array map_weights; /*! info about weights array buffers (required!) */ \ - ai_buffer_array map_activations; /*! info about activations array buffers (required!) */ - -#define AI_NETWORK_PARAMS_FIELDS_DECLARE \ -union { \ - struct { \ - ai_buffer params; /*! info about params buffer(required!) */ \ - ai_buffer activations; /*! info about activations buffer (required!) */ \ - }; \ - struct { \ - AI_NETWORK_BUFFERS_FIELD_DECLARE \ - }; \ -}; - -/*****************************************************************************/ -#define AI_BUFFER_ARRAY_OBJ_INIT(flags_, size_, buffer_array_) \ -{ \ - .flags = (ai_u16)(flags_), \ - .size = (ai_u16)(size_), \ - .buffer = (ai_buffer*)(buffer_array_) \ -} - -#define AI_BUFFER_ARRAY_OBJ_INIT_STATIC(flags_, size_, ...) \ -{ \ - .flags = (ai_u16)(flags_), \ - .size = (ai_u16)(size_), \ - .buffer = (ai_buffer*)((ai_buffer[]){__VA_ARGS__}) \ -} - -#define AI_BUFFER_ARRAY_SANE(buf_array_) \ - ai_buffer_array_sane(buf_array_) - -#define AI_BUFFER_ARRAY_FLAGS(buf_array_) \ - ((AI_BUFFER_ARRAY_SANE(buf_array_)) ? (buf_array_)->flags : AI_FLAG_NONE) - -#define AI_BUFFER_ARRAY_SIZE(buf_array_) \ - ((AI_BUFFER_ARRAY_SANE(buf_array_)) ? (buf_array_)->size : 0) - -#define AI_BUFFER_ARRAY_ITEM(buf_array_, pos_) \ - ((AI_BUFFER_ARRAY_SANE(buf_array_)) ? ((buf_array_)->buffer + (pos_)) : NULL) - -#define AI_BUFFER_ARRAY_ITEM_SET_ADDRESS(buf_array_, pos_, address_) \ - ai_buffer_array_item_set_address(buf_array_, pos_, address_) - - -/*! - * @enum buffer formats enum list - * @ingroup ai_platform - * - * List of supported ai_buffer format types. - */ -enum { - AI_BUFFER_FORMAT_NONE = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_NONE, 0, 0, 0, 0), - AI_BUFFER_FORMAT_FLOAT = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_FLOAT, 1, 1, 32, 0), - - AI_BUFFER_FORMAT_U1 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, 1, 0), - AI_BUFFER_FORMAT_U8 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, 8, 0), - AI_BUFFER_FORMAT_U16 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, 16, 0), - AI_BUFFER_FORMAT_U32 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, 32, 0), - - AI_BUFFER_FORMAT_S1 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, 1, 0), - AI_BUFFER_FORMAT_S8 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, 8, 0), - AI_BUFFER_FORMAT_S16 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, 16, 0), - AI_BUFFER_FORMAT_S32 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, 32, 0), - - AI_BUFFER_FORMAT_Q = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, 0, 0), - AI_BUFFER_FORMAT_Q7 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, 8, 7), - AI_BUFFER_FORMAT_Q15 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, 16, 15), - - AI_BUFFER_FORMAT_UQ = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, 0, 0), - AI_BUFFER_FORMAT_UQ7 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, 8, 7), - AI_BUFFER_FORMAT_UQ15 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, 16, 15), - - AI_BUFFER_FORMAT_BOOL = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_BOOL, 0, 0, 8, 0), -}; - -/*****************************************************************************/ -#define AI_ERROR_INIT(type_, code_) { \ - .type = AI_ERROR_##type_, \ - .code = AI_ERROR_CODE_##code_ \ -} - -/* printf formats */ -#define SSIZET_FMT "%" PRIu32 -#define AII32_FMT "%" PRId32 -#define AIU32_FMT "%" PRIu32 -#define AII64_FMT "%" PRId64 -#define AIU64_FMT "%" PRIu64 - - -#define AI_VERSION(major_, minor_, micro_) \ - (((major_)<<24) | ((minor_)<<16) | ((micro_)<<8)) - - -typedef uint8_t ai_custom_type_signature; - -typedef void* ai_handle; -typedef const void* ai_handle_const; - -typedef float ai_float; -typedef double ai_double; - -typedef bool ai_bool; - -typedef char ai_char; - -typedef uint32_t ai_size; -typedef int16_t ai_short_size; - -typedef uintptr_t ai_uptr; - -typedef unsigned int ai_uint; -typedef uint8_t ai_u8; -typedef uint16_t ai_u16; -typedef uint32_t ai_u32; -typedef uint64_t ai_u64; - -typedef int ai_int; -typedef int8_t ai_i8; -typedef int16_t ai_i16; -typedef int32_t ai_i32; -typedef int64_t ai_i64; - -typedef uint64_t ai_macc; - -typedef int32_t ai_pbits; - -typedef uint32_t ai_signature; - -typedef void (*ai_handle_func)(ai_handle); - -/*****************************************************************************/ -/*! - * @struct ai_error - * @ingroup ai_platform - * @brief Structure encoding details about the last error. - */ -typedef struct ai_error_ { - ai_u32 type : 8; /*!< Error type represented by @ref ai_error_type */ - ai_u32 code : 24; /*!< Error code represented by @ref ai_error_code */ -} ai_error; - -/*****************************************************************************/ -/*! - * @struct ai_intq_info - * @ingroup ai_platform - * @brief an element of the ai_intq_info_list entry. It reports an array for the - * scale and zeropoint values for each buffer. Optional flags are also present - */ -typedef struct ai_intq_info_ { - INTQ_CONST ai_float* scale; - INTQ_CONST ai_handle zeropoint; -} ai_intq_info; - -/*! - * @struct ai_intq_info_list - * @ingroup ai_platform - * @brief list reporting meta info for quantized networks integer support - * when size > 1 it means a per channel out quantization - */ -typedef struct ai_intq_info_list_ { - ai_u16 flags; /*!< optional flags to store intq info attributes */ - ai_u16 size; /*!< number of elements in the the intq_info list */ - INTQ_CONST ai_intq_info* info; /*!< pointer to an array of metainfo - * associated to the intq_info list */ -} ai_intq_info_list; - -/*****************************************************************************/ -/*! - * @struct ai_buffer_meta_info - * @ingroup ai_platform - * @brief Optional meta attributes associated with the I/O buffer. - * This datastruct is used also for network querying, where the data field may - * may be NULL. - */ -typedef struct ai_buffer_meta_info_ { - ai_u32 flags; /*!< meta info flags */ - ai_intq_info_list* intq_info; /*!< meta info related to integer format */ -} ai_buffer_meta_info; - -/*! - * @struct ai_buffer_shape - * @ingroup ai_platform - * @brief Memory buffer shape datatype definition. - */ -typedef struct ai_buffer_shape_ { - ai_u32 type : 8; /*!< shape type: reserved for compatibility */ - ai_u32 size : 24; /*!< size: shape cardinality */ - ai_shape_dimension* data; /*!< pointer to shape tuple array */ -} ai_buffer_shape; - -/*! - * @struct ai_buffer - * @ingroup ai_platform - * @brief Memory buffer storing data (optional) with a shape, size and type. - * This datastruct is used also for network querying, where the data field may - * may be NULL. - */ -typedef struct ai_buffer_ { - ai_buffer_format format; /*!< buffer format */ - ai_handle data; /*!< pointer to buffer data */ - ai_buffer_meta_info* meta_info; /*!< pointer to buffer metadata info */ - /* New 7.1 fields */ - ai_flags flags; /*!< shape optional flags */ - ai_size size; /*!< number of elements of the buffer (including optional padding) */ - ai_buffer_shape shape; /*!< n-dimensional shape info */ -} ai_buffer; - -/*! - * @struct ai_buffer_array - * @ingroup ai_platform - * @brief Array of @ref ai_buffer. - */ -typedef struct ai_buffer_array_ { - ai_u16 flags; /*!< buffer array flags */ - ai_u16 size; /*!< buffer array size */ - ai_buffer* buffer; /*!< buffer array buffers pointer */ -} ai_buffer_array; - -/* enums section */ - -/*! - * @enum ai_error_type - * @ingroup ai_platform - * - * Generic enum to list network error types. - */ -typedef enum { - AI_ERROR_NONE = 0x00, /*!< No error */ - AI_ERROR_TOOL_PLATFORM_API_MISMATCH = 0x01, - AI_ERROR_TYPES_MISMATCH = 0x02, - AI_ERROR_INVALID_HANDLE = 0x10, - AI_ERROR_INVALID_STATE = 0x11, - AI_ERROR_INVALID_INPUT = 0x12, - AI_ERROR_INVALID_OUTPUT = 0x13, - AI_ERROR_INVALID_PARAM = 0x14, - AI_ERROR_INVALID_SIGNATURE = 0x15, - AI_ERROR_INVALID_SIZE = 0x16, - AI_ERROR_INVALID_VALUE = 0x17, - AI_ERROR_INIT_FAILED = 0x30, - AI_ERROR_ALLOCATION_FAILED = 0x31, - AI_ERROR_DEALLOCATION_FAILED = 0x32, - AI_ERROR_CREATE_FAILED = 0x33, -} ai_error_type; - -/*! - * @enum ai_error_code - * @ingroup ai_platform - * - * Generic enum to list network error codes. - */ -typedef enum { - AI_ERROR_CODE_NONE = 0x0000, /*!< No error */ - AI_ERROR_CODE_NETWORK = 0x0010, - AI_ERROR_CODE_NETWORK_PARAMS = 0x0011, - AI_ERROR_CODE_NETWORK_WEIGHTS = 0x0012, - AI_ERROR_CODE_NETWORK_ACTIVATIONS = 0x0013, - AI_ERROR_CODE_LAYER = 0x0014, - AI_ERROR_CODE_TENSOR = 0x0015, - AI_ERROR_CODE_ARRAY = 0x0016, - AI_ERROR_CODE_INVALID_PTR = 0x0017, - AI_ERROR_CODE_INVALID_SIZE = 0x0018, - AI_ERROR_CODE_INVALID_FORMAT = 0x0019, - AI_ERROR_CODE_OUT_OF_RANGE = 0x0020, - AI_ERROR_CODE_INVALID_BATCH = 0x0021, - AI_ERROR_CODE_MISSED_INIT = 0x0030, - AI_ERROR_CODE_IN_USE = 0x0040, - AI_ERROR_CODE_LOCK = 0x0041, -} ai_error_code; - -/*! - * @struct ai_platform_version - * @ingroup ai_platform - * @brief Datastruct storing platform version info - */ -typedef struct ai_platform_version_ { - ai_u8 major; - ai_u8 minor; - ai_u8 micro; - ai_u8 reserved; -} ai_platform_version; - -/*! - * @struct ai_network_params - * @ingroup ai_platform - * - * Datastructure to pass parameters during network initialization. - */ -typedef struct ai_network_params_ { - AI_NETWORK_PARAMS_FIELDS_DECLARE -} ai_network_params; - -/*! - * @struct ai_network_buffers - * @ingroup ai_platform - * - * Datastructure to pass network buffers during network initialization. - */ -typedef struct ai_network_buffers_ { - AI_NETWORK_BUFFERS_FIELD_DECLARE -} ai_network_buffers; - -/*! - * @struct ai_network_report - * @ingroup ai_platform - * - * Datastructure to query a network report with some relevant network detail. - */ -typedef struct ai_network_report_ { - const char* model_name; - const char* model_signature; - const char* model_datetime; - - const char* compile_datetime; - - const char* runtime_revision; - ai_platform_version runtime_version; - - const char* tool_revision; - ai_platform_version tool_version; - ai_platform_version tool_api_version; - - ai_platform_version api_version; - ai_platform_version interface_api_version; - - ai_macc n_macc; - - ai_u16 n_inputs; - ai_u16 n_outputs; - ai_buffer* inputs; - ai_buffer* outputs; - - AI_NETWORK_PARAMS_FIELDS_DECLARE - - ai_u32 n_nodes; - - ai_signature signature; -} ai_network_report; - -/*! - * @enum ai_upsample_mode - * @ingroup ai_platform - * @brief allowed mode in upsample layer - */ -typedef enum { - AI_UPSAMPLE_ZEROS = 0x0, - AI_UPSAMPLE_NEAREST, - AI_UPSAMPLE_BILINEAR, - AI_UPSAMPLE_TRILINEAR -} ai_upsample_mode; - -/*! - * @enum ai_resize_mode - * @ingroup ai_platform - * @brief allowed mode in resize layer - */ -typedef enum { - AI_RESIZE_ZEROS = 0x0, - AI_RESIZE_NEAREST, - AI_RESIZE_LINEAR, - AI_RESIZE_CUBIC -} ai_resize_mode; - -/*! - * @enum ai_coord_transf_mode - * @ingroup ai_platform - * @brief coordinate_transformation_mode in resize layer - */ -typedef enum { - AI_HALF_PIXEL = 0x0, - AI_PYTORCH_HALF_PIXEL, - AI_ALIGN_CORNERS, - AI_ASYMMETRIC, - AI_TF_HALF_PIXEL_FOR_NN, - AI_TF_CROP_AND_RESIZE -} ai_coord_transf_mode; - -typedef enum { - AI_ROUND_PREFER_FLOOR = 0x0, - AI_ROUND_PREFER_CEIL, - AI_ROUND_FLOOR, - AI_ROUND_CEIL -} ai_nearest_mode; - -typedef enum { - AI_PAD_CONSTANT = 0x0, - AI_PAD_REFLECT, - AI_PAD_EDGE, - AI_PAD_8BIT_CH1ST_CONSTANT, -} ai_pad_mode; - -#define OUTPUT_PADDING_FLAG (1 << 0) -#define CHANNEL_FIRST_FLAG (1 << 1) -/* Padding pattern supported: */ -/* 0 = (1, 1, 1,1), 1 = (0, 0, 2, 2) */ -#define CHANNEL_PADDING_PATTERN (1 << 2) -/* Carefull when changing those definitions - bit0 shall always select output padding (Valid vs Same) - bit1 shall always select Channel first /channel lst format - bit2 shall always select padding pattern (1, 1, 1, 1) (stride1) or (0, 0, 2, 2) (stride2) -*/ -typedef enum { - AI_LAYER_FORMAT_CHANNEL_LAST_VALID = 0x0, - AI_LAYER_FORMAT_CHANNEL_LAST_SAME = 0x1, - AI_LAYER_FORMAT_CHANNEL_FIRST_VALID = 0x2, - AI_LAYER_FORMAT_CHANNEL_FIRST_SAME = 0x3, - AI_LAYER_FORMAT_CHANNEL_FIRST_SAME2 = 0x7, -} ai_layer_format_type; - -/*! ai_platform public APIs **************************************************/ - -/*! - * @brief get the total number of elements of an ai_buffer. - * @ingroup ai_platform - * @param buffer a pointer to an @ref ai_buffer - * @param with_padding when true it considers also padded elements - * @return the number of elements of the buffer (with/without padded ones) - */ -AI_API_ENTRY -ai_size ai_buffer_get_size(const ai_buffer* buffer, const ai_bool with_padding); - -/*! - * @brief get the size in bytes of an ai_buffer (given the number of elements and format). - * @ingroup ai_platform - * @param count the number of elements composing the buffer - * @param fmt the format of the ai_buffer - * @return the size in bytes of the buffer - */ -AI_API_ENTRY -ai_size ai_buffer_get_byte_size(const ai_size count, const ai_buffer_format fmt); - -/*! - * @brief get total size in bytes of a buffer array. - * @ingroup ai_platform - * @param barray a pointer to the buffer array - * @return the total size in bytes of all the buffer arrays - */ -AI_API_ENTRY -ai_bool ai_buffer_array_is_empty(const ai_buffer_array* barray); - -/*! - * @brief get total size in bytes of a buffer array. - * @ingroup ai_platform - * @param barray a pointer to the buffer array - * @return the total size in bytes of all the buffer arrays - */ -AI_API_ENTRY -ai_bool ai_buffer_array_is_valid(const ai_buffer_array* barray); - -/*! - * @brief check if a buffer array is valid - i.e. not empty. - * @ingroup ai_platform - * @param barray a pointer to the buffer array - * @return true if the array is consistent and not empty, false otherwise - */ -AI_API_ENTRY -ai_bool ai_buffer_array_sane(const ai_buffer_array* barray); - -/*! - * @brief get total size in bytes of a buffer array. - * @ingroup ai_platform - * @param barray a pointer to the buffer array - * @return the total size in bytes of all the buffer arrays - */ -AI_API_ENTRY -ai_size ai_buffer_array_get_byte_size(const ai_buffer_array* barray); - -/*! - * @brief set the address of buffer array item @pos - * @ingroup ai_platform - * @param barray a pointer to the buffer array - * @param pos the index of the element in the array - * @param address the address to set - * @return true if successful, false otherwise - */ -AI_API_ENTRY -ai_bool ai_buffer_array_item_set_address( - ai_buffer_array* barray, const ai_u32 pos, ai_handle address); - -AI_API_DECLARE_END - -#endif /*AI_PLATFORM_H*/ +/** + ****************************************************************************** + * @file ai_platform.h + * @author AST Embedded Analytics Research Platform + * @brief Definitions of AI platform public APIs types + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef AI_PLATFORM_H +#define AI_PLATFORM_H + +#include +#include + +#define __STDC_FORMAT_MACROS 1 +#include + +#ifndef AI_PLATFORM_API_MAJOR +#define AI_PLATFORM_API_MAJOR (1) +#endif +#ifndef AI_PLATFORM_API_MINOR +#define AI_PLATFORM_API_MINOR (2) +#endif +#ifndef AI_PLATFORM_API_MICRO +#define AI_PLATFORM_API_MICRO (0) +#endif + +#define AI_PLATFORM_API_VERSION \ + AI_VERSION(AI_PLATFORM_API_MAJOR, \ + AI_PLATFORM_API_MINOR, \ + AI_PLATFORM_API_MICRO) + + +#ifndef AI_TOOLS_API_VERSION_MAJOR +#define AI_TOOLS_API_VERSION_MAJOR (1) +#endif +#ifndef AI_TOOLS_API_VERSION_MINOR +#define AI_TOOLS_API_VERSION_MINOR (5) +#endif +#ifndef AI_TOOLS_API_VERSION_MICRO +#define AI_TOOLS_API_VERSION_MICRO (0) +#endif + +/*****************************************************************************/ +#define AI_TOOLS_API_VERSION \ + AI_VERSION(AI_TOOLS_API_VERSION_MAJOR, \ + AI_TOOLS_API_VERSION_MINOR, \ + AI_TOOLS_API_VERSION_MICRO) + +#define AI_TOOLS_API_VERSION_1_3 \ + AI_VERSION(1, 3, 0) + +#define AI_TOOLS_API_VERSION_1_4 \ + AI_VERSION(1, 4, 0) + +#define AI_TOOLS_API_VERSION_1_5 \ + AI_VERSION(1, 5, 0) + +/*****************************************************************************/ +#ifdef __cplusplus +#define AI_API_DECLARE_BEGIN extern "C" { +#define AI_API_DECLARE_END } +#else +#include +#define AI_API_DECLARE_BEGIN /* AI_API_DECLARE_BEGIN */ +#define AI_API_DECLARE_END /* AI_API_DECLARE_END */ +#endif + +/*****************************************************************************/ +#define AI_FLAG_NONE (0x0) + +/*****************************************************************************/ +AI_API_DECLARE_BEGIN + +/*! + * @typedef ai_flags + * @ingroup ai_platform + * @brief bitmask for flags management + */ +typedef uint32_t ai_flags; + +/*****************************************************************************/ +#define AI_CONCAT_ARG(a, b) a ## b +#define AI_CONCAT(a, b) AI_CONCAT_ARG(a, b) + +/*! AI_CAST SECTION ***********************************/ +#define AI_CAST(type_, expr_) ((type_)(expr_)) + +/*****************************************************************************/ +#define AI_MAGIC_SIGNATURE \ + (0xa1facade) + +#define AI_PACK(...) \ + __VA_ARGS__ + +/*****************************************************************************/ +#define AI_SHAPE_BCWH (0x01u) + +/*! + * @typedef ai_shape_dimension + * @ingroup ai_platform + * @brief shape dimension type to be used in shape related structs @ref ai_buffer_shape + */ +typedef uint32_t ai_shape_dimension; + +/*****************************************************************************/ +#if defined(_MSC_VER) + #define AI_API_ENTRY __declspec(dllexport) + #define AI_ALIGNED(x) /* AI_ALIGNED(x) */ +#elif defined(__ICCARM__) || defined (__IAR_SYSTEMS_ICC__) + #define AI_API_ENTRY /* AI_API_ENTRY */ + #define AI_ALIGNED(x) AI_CONCAT(AI_ALIGNED_,x) + #define AI_ALIGNED_1 _Pragma("data_alignment = 1") + #define AI_ALIGNED_2 _Pragma("data_alignment = 2") + #define AI_ALIGNED_4 _Pragma("data_alignment = 4") + #define AI_ALIGNED_8 _Pragma("data_alignment = 8") + #define AI_ALIGNED_16 _Pragma("data_alignment = 16") + #define AI_ALIGNED_32 _Pragma("data_alignment = 32") +#elif defined(__CC_ARM) + #define AI_API_ENTRY __attribute__((visibility("default"))) + #define AI_ALIGNED(x) __attribute__((aligned (x))) + /* Keil disallows anonymous union initialization by default */ + #pragma anon_unions +#elif defined(__GNUC__) + //#define AI_API_ENTRY __attribute__((visibility("default"))) + #define AI_API_ENTRY /* AI_API_ENTRY */ + #define AI_ALIGNED(x) __attribute__((aligned(x))) +#else + /* Dynamic libraries are not supported by the compiler */ + #define AI_API_ENTRY /* AI_API_ENTRY */ + #define AI_ALIGNED(x) /* AI_ALIGNED(x) */ +#endif + +#define AI_HANDLE_PTR(ptr_) ((ai_handle)(ptr_)) +#define AI_HANDLE_NULL AI_HANDLE_PTR(NULL) + +#define AI_HANDLE_FUNC_PTR(func) ((ai_handle_func)(func)) + +#define AI_UNUSED(x) (void)(x); + +#define AI_DEPRECATED /* AI_DEPRECATED */ + +#define AI_LEGACY /* AI_LEGACY */ + +#define AI_MAGIC_MARKER (0xA1FACADE) + + +#if defined(__cplusplus) + #define AI_STRUCT_INIT {} + #define AI_C_ARRAY_INIT {} +#else + #define AI_STRUCT_INIT {0} + #define AI_C_ARRAY_INIT {0} +#endif + +#define AI_ERROR_FMT AIU32_FMT + +#define AI_IS_UNSIGNED(type) \ + ((((type)0) - 1) > 0) + +#define AI_CUSTOM_SIZE(type) \ + (ai_custom_type_signature)((AI_IS_UNSIGNED(type)) \ + ? (0x80|(sizeof(type)&0x7f)) : (sizeof(type)&0x7f)) + +/*! network buffers struct handlers *******************************************/ +#ifdef __cplusplus + +#define AI_NETWORK_PARAMS_INIT(params_, activations_) \ +{ \ + {{ params_, activations_ }} \ +} + +#define AI_NETWORK_BUFFERS_INIT(weights_buffers_, activations_buffers_) \ +{ \ + AI_MAGIC_SIGNATURE, AI_PACK(weights_buffers_), AI_PACK(activations_buffers_) \ +} + +#else + +#define AI_NETWORK_PARAMS_INIT(params_, activations_) \ +{ \ + .params = params_, \ + .activations = activations_ \ +} + +#define AI_NETWORK_BUFFERS_INIT(weights_buffers_, activations_buffers_) \ +{ \ + .map_signature = AI_MAGIC_SIGNATURE, \ + .map_weights = AI_PACK(weights_buffers_), \ + .map_activations = AI_PACK(activations_buffers_) \ +} + +#endif // __cplusplus + + +/*! binary padded bits macro helpers *****************************************/ +#define AI_PBITS_MASK \ + (0x1F) + +#define AI_PBITS_SHIFTS \ + (5) + +#define AI_PBITS_PADDED_BYTES_COUNT(bits_) \ + (((ai_u32)(bits_) + 7) >> 3) + +#define AI_PBITS_PADDED_WORDS_COUNT(bits_) \ + (((ai_size)(bits_) + AI_PBITS_MASK) >> AI_PBITS_SHIFTS) + +#define AI_PBITS_GET_WORD(word_ptr_, bits_) \ + (((ai_pbits*)(word_ptr_)) + ((bits_) >> AI_PBITS_SHIFTS)) + +#define AI_PAD_CHANNELS(format_, channels_) \ + ((AI_BUFFER_FMT_GET_BITS(format_)==1) ? (AI_PBITS_PADDED_WORDS_COUNT(channels_) << AI_PBITS_SHIFTS) : (channels_)) + + +/*! ai_intq_info struct handlers *********************************************/ +#define INTQ_CONST const +// #define INTQ_CONST + +#define AI_INTQ_INFO_LIST(list_) \ + ((list_)->info) + +#define AI_INTQ_INFO_LIST_FLAGS(list_) \ + ((list_) ? (list_)->flags : 0) + +#define AI_INTQ_INFO_LIST_SIZE(list_) \ + ((list_) ? (list_)->size : 0) + +#define AI_HAS_INTQ_INFO_LIST(list_) \ + ((list_) ? (((list_)->info) && ((list_)->size>0)) : false) + +#define AI_INTQ_INFO_LIST_SCALE(list_, type_, pos_) \ + (((list_) && (list_)->info && ((pos_)<(list_)->size)) \ + ? ((type_*)((list_)->info->scale))[(pos_)] : 0) + +#define AI_INTQ_INFO_LIST_ZEROPOINT(list_, type_, pos_) \ + (((list_) && (list_)->info && ((pos_)<(list_)->size)) \ + ? ((type_*)((list_)->info->zeropoint))[(pos_)] : 0) + +/*! ai_buffer format handlers ************************************************/ + +/*! + * @enum buffer format definition + * @ingroup ai_platform + * + * 32 bit signed format list. + */ +typedef int32_t ai_buffer_format; + +/*! ai_buffer_meta flags & macros ********************************************/ +#define AI_BUFFER_META_HAS_INTQ_INFO (0x1U << 0) +#define AI_BUFFER_META_FLAG_SCALE_FLOAT (0x1U << 0) +#define AI_BUFFER_META_FLAG_ZEROPOINT_U8 (0x1U << 1) +#define AI_BUFFER_META_FLAG_ZEROPOINT_S8 (0x1U << 2) +#define AI_BUFFER_META_FLAG_ZEROPOINT_U16 (0x1U << 3) +#define AI_BUFFER_META_FLAG_ZEROPOINT_S16 (0x1U << 4) + +/*! ai_buffer format variable flags & macros *********************************/ +#define AI_BUFFER_FMT_TYPE_NONE (0x0) +#define AI_BUFFER_FMT_TYPE_FLOAT (0x1) +#define AI_BUFFER_FMT_TYPE_Q (0x2) +#define AI_BUFFER_FMT_TYPE_BOOL (0x3) + +#define AI_BUFFER_FMT_FLAG_CONST (0x1U<<30) +#define AI_BUFFER_FMT_FLAG_STATIC (0x1U<<29) +#define AI_BUFFER_FMT_FLAG_IS_IO (0x1U<<27) +#define AI_BUFFER_FMT_FLAG_PERSISTENT (0x1U<<29) + + +#define AI_BUFFER_FMT_PACK(value_, mask_, bits_) \ + ( ((value_) & (mask_)) << (bits_) ) + +#define AI_BUFFER_FMT_UNPACK(fmt_, mask_, bits_) \ + ( (AI_BUFFER_FMT_OBJ(fmt_) >> (bits_)) & (mask_) ) + +#define AI_BUFFER_FMT_OBJ(fmt_) \ + ((ai_buffer_format)(fmt_)) + +#define AI_BUFFER_FMT_GET_FLOAT(fmt_) \ + AI_BUFFER_FMT_UNPACK(fmt_, 0x1, 24) + +#define AI_BUFFER_FMT_GET_SIGN(fmt_) \ + AI_BUFFER_FMT_UNPACK(fmt_, 0x1, 23) + +#define AI_BUFFER_FMT_GET_TYPE(fmt_) \ + AI_BUFFER_FMT_UNPACK(fmt_, 0xF, 17) + +#define AI_BUFFER_FMT_GET_BITS(fmt_) \ + AI_BUFFER_FMT_UNPACK(fmt_, 0x7F, 7) + +#define AI_BUFFER_FMT_SET_BITS(bits_) \ + AI_BUFFER_FMT_PACK((bits_), 0x7F, 7) + +#define AI_BUFFER_FMT_GET_FBITS(fmt_) \ + ( (ai_i8)AI_BUFFER_FMT_UNPACK(fmt_, 0x7F, 0) - 64 ) + +#define AI_BUFFER_FMT_SET_FBITS(fbits_) \ + AI_BUFFER_FMT_PACK((fbits_)+64, 0x7F, 0) + +#define AI_BUFFER_FMT_SET(type_id_, sign_bit_, float_bit_, bits_, fbits_) \ + AI_BUFFER_FMT_OBJ( \ + AI_BUFFER_FMT_PACK(float_bit_, 0x1, 24) | \ + AI_BUFFER_FMT_PACK(sign_bit_, 0x1, 23) | \ + AI_BUFFER_FMT_PACK(0, 0x3, 21) | \ + AI_BUFFER_FMT_PACK(type_id_, 0xF, 17) | \ + AI_BUFFER_FMT_PACK(0, 0x7, 14) | \ + AI_BUFFER_FMT_SET_BITS(bits_) | \ + AI_BUFFER_FMT_SET_FBITS(fbits_) \ + ) + +#define AI_BUFFER_FMT_SAME(fmt1_, fmt2_) \ + ( AI_BUFFER_FMT_GET(fmt1_) == AI_BUFFER_FMT_GET(fmt2_) ) + +#define AI_BUFFER_FMT_GET(fmt_) \ + (AI_BUFFER_FMT_OBJ(fmt_) & 0x01FFFFFF) + +#define AI_BUFFER_FORMAT(buf_) \ + AI_BUFFER_FMT_GET((buf_)->format) + + +/*! + * @define shape type index + * @ingroup ai_platform + * @brief positional ID for generic shapes C structs + */ +#define AI_SHAPE_EXTENSION (0x5) +#define AI_SHAPE_DEPTH (0x4) +#define AI_SHAPE_HEIGHT (0x3) +#define AI_SHAPE_WIDTH (0x2) +#define AI_SHAPE_CHANNEL (0x1) +#define AI_SHAPE_IN_CHANNEL (0x0) +#define AI_SHAPE_BATCH (0x0) +#define AI_SHAPE_TIME (0x0) + + +AI_DEPRECATED +#define AI_BUFFER_WIDTH(buf_) \ + ((buf_)->shape.data[AI_SHAPE_WIDTH]) + +AI_DEPRECATED +#define AI_BUFFER_HEIGHT(buf_) \ + ((buf_)->shape.data[AI_SHAPE_HEIGHT]) + +AI_DEPRECATED +#define AI_BUFFER_CHANNELS(buf_) \ + ((buf_)->shape.data[AI_SHAPE_CHANNEL]) + +AI_DEPRECATED +#define AI_BUFFER_N_BATCHES(buf_) \ + ((buf_)->shape.data[AI_SHAPE_BATCH]) + +#define AI_BUFFER_DATA(buf_, type_) \ + ((type_*)((buf_)->data)) + +#define AI_BUFFER_META_INFO(buf_) \ + ((buf_)->meta_info) + +#define AI_BUFFER_META_INFO_INTQ(meta_) \ + ((meta_) && ((meta_)->flags & AI_BUFFER_META_HAS_INTQ_INFO)) \ + ? ((meta_)->intq_info) : NULL + +#define AI_BUFFER_META_INFO_INTQ_GET_SIZE(meta_) \ + ( (AI_BUFFER_META_INFO_INTQ(meta_)) \ + ? AI_INTQ_INFO_LIST_SIZE(AI_BUFFER_META_INFO_INTQ(meta_)) \ + : 0 ) + +#define AI_BUFFER_META_INFO_INTQ_GET_SCALE(meta_, pos_) \ + ( (AI_BUFFER_META_INFO_INTQ(meta_)) \ + ? AI_INTQ_INFO_LIST_SCALE(AI_BUFFER_META_INFO_INTQ(meta_), ai_float, pos_) \ + : 0 ) + +#define AI_BUFFER_META_INFO_INTQ_GET_ZEROPOINT(meta_, pos_) \ + ( (AI_BUFFER_META_INFO_INTQ(meta_)) \ + ? ((AI_INTQ_INFO_LIST_FLAGS(AI_BUFFER_META_INFO_INTQ(meta_))&AI_BUFFER_META_FLAG_ZEROPOINT_U8) \ + ? AI_INTQ_INFO_LIST_ZEROPOINT(AI_BUFFER_META_INFO_INTQ(meta_), ai_u8, pos_) \ + : AI_INTQ_INFO_LIST_ZEROPOINT(AI_BUFFER_META_INFO_INTQ(meta_), ai_i8, pos_) ) \ + : 0 ) + +#define AI_BUFFER_META_INFO_INIT(flags_, intq_info_) { \ + .flags = (flags_), \ + .intq_info = AI_PACK(intq_info_) \ +} + +#define AI_BUFFER_SIZE(buf_) \ + ai_buffer_get_size(buf_, true) + +#define AI_BUFFER_SIZE_UNPAD(buf_) \ + ai_buffer_get_size(buf_, false) + +#define AI_BUFFER_BYTE_SIZE(count_, fmt_) \ + ai_buffer_get_byte_size(count_, fmt_) + +#define AI_BUFFER_FLAGS(buf_) \ + ((buf_) ? (buf_)->flags : 0x0) + +#define AI_BUFFER_SHAPE_INIT(type_, size_, ...) \ +{ \ + .type = (type_), \ + .size = (size_), \ + .data = (ai_shape_dimension[]){ __VA_ARGS__ } \ +} + +#define AI_BUFFER_SHAPE_INIT_FROM_ARRAY(type_, size_, array_ptr_) \ +{ \ + .type = (type_), \ + .size = (size_), \ + .data = (ai_shape_dimension*)(array_ptr_) \ +} + +#define AI_BUFFER_SHAPE_SIZE(buf_) \ + ((buf_) ? (buf_)->shape.size : 0) + +#define AI_BUFFER_SHAPE_TYPE(buf_) \ + ((buf_) ? (buf_)->shape.type : 0) + +#if defined(HAS_AI_ASSERT) && defined(AI_ASSERT) + +#define AI_BUFFER_SET_SHAPE_ELEM(buf_, pos_, value_) { \ + AI_ASSERT(buf_) \ + (buf_)->shape.data[pos_] = (value_); \ +} + +#define AI_BUFFER_SHAPE_ELEM(buf_, pos_) \ + (((pos_)shape.data[pos_] : 0) + +#else + +#define AI_BUFFER_SET_SHAPE_ELEM(buf_, pos_, value_) { \ + (buf_)->shape.data[pos_] = (value_); \ +} + +#define AI_BUFFER_SHAPE_ELEM(buf_, pos_) \ + (buf_)->shape.data[pos_] + +#endif + + +AI_DEPRECATED +#define AI_BUFFER_OBJ_INIT(format_, h_, w_, ch_, n_batches_, data_) \ +{ .format = (ai_buffer_format)(format_), \ + .data = (ai_handle)(data_), \ + .meta_info = NULL, \ + .flags = AI_FLAG_NONE, \ + .size = (h_) * (w_) * AI_PAD_CHANNELS(format_, ch_), \ + .shape = AI_BUFFER_SHAPE_INIT(AI_SHAPE_BCWH, 4, (n_batches_), (ch_), (w_), (h_)), \ +} + +/* 7.1 new macro API */ +#define AI_BUFFER_INIT(flags_, format_, shape_, size_, meta_info_, data_) \ +{ .format = (ai_buffer_format)(format_), \ + .data = (ai_handle)(data_), \ + .meta_info = (meta_info_), \ + .flags = (flags_), \ + .size = (size_), \ + .shape = AI_PACK(shape_) \ +} + +/* 7.1 new macro API */ +#define AI_BUFFER_INIT_STATIC(type_, flags_, format_, shape_, size_, meta_info_, ...) \ +{ .format = (ai_buffer_format)(format_), \ + .data = (ai_handle)((type_[]){__VA_ARGS__}), \ + .meta_info = (meta_info_), \ + .flags = (flags_), \ + .size = (size_), \ + .shape = AI_PACK(shape_) \ +} + +/*****************************************************************************/ +#define AI_NETWORK_BUFFERS_FIELD_DECLARE \ + ai_signature map_signature; /*! structure signature (required!) */ \ + ai_buffer_array map_weights; /*! info about weights array buffers (required!) */ \ + ai_buffer_array map_activations; /*! info about activations array buffers (required!) */ + +#define AI_NETWORK_PARAMS_FIELDS_DECLARE \ +union { \ + struct { \ + ai_buffer params; /*! info about params buffer(required!) */ \ + ai_buffer activations; /*! info about activations buffer (required!) */ \ + }; \ + struct { \ + AI_NETWORK_BUFFERS_FIELD_DECLARE \ + }; \ +}; + +/*****************************************************************************/ +#define AI_BUFFER_ARRAY_OBJ_INIT(flags_, size_, buffer_array_) \ +{ \ + .flags = (ai_u16)(flags_), \ + .size = (ai_u16)(size_), \ + .buffer = (ai_buffer*)(buffer_array_) \ +} + +#define AI_BUFFER_ARRAY_OBJ_INIT_STATIC(flags_, size_, ...) \ +{ \ + .flags = (ai_u16)(flags_), \ + .size = (ai_u16)(size_), \ + .buffer = (ai_buffer*)((ai_buffer[]){__VA_ARGS__}) \ +} + +#define AI_BUFFER_ARRAY_SANE(buf_array_) \ + ai_buffer_array_sane(buf_array_) + +#define AI_BUFFER_ARRAY_FLAGS(buf_array_) \ + ((AI_BUFFER_ARRAY_SANE(buf_array_)) ? (buf_array_)->flags : AI_FLAG_NONE) + +#define AI_BUFFER_ARRAY_SIZE(buf_array_) \ + ((AI_BUFFER_ARRAY_SANE(buf_array_)) ? (buf_array_)->size : 0) + +#define AI_BUFFER_ARRAY_ITEM(buf_array_, pos_) \ + ((AI_BUFFER_ARRAY_SANE(buf_array_)) ? ((buf_array_)->buffer + (pos_)) : NULL) + +#define AI_BUFFER_ARRAY_ITEM_SET_ADDRESS(buf_array_, pos_, address_) \ + ai_buffer_array_item_set_address(buf_array_, pos_, address_) + + +/*! + * @enum buffer formats enum list + * @ingroup ai_platform + * + * List of supported ai_buffer format types. + */ +enum { + AI_BUFFER_FORMAT_NONE = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_NONE, 0, 0, 0, 0), + AI_BUFFER_FORMAT_FLOAT = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_FLOAT, 1, 1, 32, 0), + + AI_BUFFER_FORMAT_U1 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, 1, 0), + AI_BUFFER_FORMAT_U8 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, 8, 0), + AI_BUFFER_FORMAT_U16 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, 16, 0), + AI_BUFFER_FORMAT_U32 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, 32, 0), + + AI_BUFFER_FORMAT_S1 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, 1, 0), + AI_BUFFER_FORMAT_S8 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, 8, 0), + AI_BUFFER_FORMAT_S16 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, 16, 0), + AI_BUFFER_FORMAT_S32 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, 32, 0), + + AI_BUFFER_FORMAT_Q = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, 0, 0), + AI_BUFFER_FORMAT_Q7 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, 8, 7), + AI_BUFFER_FORMAT_Q15 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 1, 0, 16, 15), + + AI_BUFFER_FORMAT_UQ = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, 0, 0), + AI_BUFFER_FORMAT_UQ7 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, 8, 7), + AI_BUFFER_FORMAT_UQ15 = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_Q, 0, 0, 16, 15), + + AI_BUFFER_FORMAT_BOOL = AI_BUFFER_FMT_SET(AI_BUFFER_FMT_TYPE_BOOL, 0, 0, 8, 0), +}; + +/*****************************************************************************/ +#define AI_ERROR_INIT(type_, code_) { \ + .type = AI_ERROR_##type_, \ + .code = AI_ERROR_CODE_##code_ \ +} + +/* printf formats */ +#define SSIZET_FMT "%" PRIu32 +#define AII32_FMT "%" PRId32 +#define AIU32_FMT "%" PRIu32 +#define AII64_FMT "%" PRId64 +#define AIU64_FMT "%" PRIu64 + + +#define AI_VERSION(major_, minor_, micro_) \ + (((major_)<<24) | ((minor_)<<16) | ((micro_)<<8)) + + +typedef uint8_t ai_custom_type_signature; + +typedef void* ai_handle; +typedef const void* ai_handle_const; + +typedef float ai_float; +typedef double ai_double; + +typedef bool ai_bool; + +typedef char ai_char; + +typedef uint32_t ai_size; +typedef int16_t ai_short_size; + +typedef uintptr_t ai_uptr; + +typedef unsigned int ai_uint; +typedef uint8_t ai_u8; +typedef uint16_t ai_u16; +typedef uint32_t ai_u32; +typedef uint64_t ai_u64; + +typedef int ai_int; +typedef int8_t ai_i8; +typedef int16_t ai_i16; +typedef int32_t ai_i32; +typedef int64_t ai_i64; + +typedef uint64_t ai_macc; + +typedef int32_t ai_pbits; + +typedef uint32_t ai_signature; + +typedef void (*ai_handle_func)(ai_handle); + +/*****************************************************************************/ +/*! + * @struct ai_error + * @ingroup ai_platform + * @brief Structure encoding details about the last error. + */ +typedef struct ai_error_ { + ai_u32 type : 8; /*!< Error type represented by @ref ai_error_type */ + ai_u32 code : 24; /*!< Error code represented by @ref ai_error_code */ +} ai_error; + +/*****************************************************************************/ +/*! + * @struct ai_intq_info + * @ingroup ai_platform + * @brief an element of the ai_intq_info_list entry. It reports an array for the + * scale and zeropoint values for each buffer. Optional flags are also present + */ +typedef struct ai_intq_info_ { + INTQ_CONST ai_float* scale; + INTQ_CONST ai_handle zeropoint; +} ai_intq_info; + +/*! + * @struct ai_intq_info_list + * @ingroup ai_platform + * @brief list reporting meta info for quantized networks integer support + * when size > 1 it means a per channel out quantization + */ +typedef struct ai_intq_info_list_ { + ai_u16 flags; /*!< optional flags to store intq info attributes */ + ai_u16 size; /*!< number of elements in the the intq_info list */ + INTQ_CONST ai_intq_info* info; /*!< pointer to an array of metainfo + * associated to the intq_info list */ +} ai_intq_info_list; + +/*****************************************************************************/ +/*! + * @struct ai_buffer_meta_info + * @ingroup ai_platform + * @brief Optional meta attributes associated with the I/O buffer. + * This datastruct is used also for network querying, where the data field may + * may be NULL. + */ +typedef struct ai_buffer_meta_info_ { + ai_u32 flags; /*!< meta info flags */ + ai_intq_info_list* intq_info; /*!< meta info related to integer format */ +} ai_buffer_meta_info; + +/*! + * @struct ai_buffer_shape + * @ingroup ai_platform + * @brief Memory buffer shape datatype definition. + */ +typedef struct ai_buffer_shape_ { + ai_u32 type : 8; /*!< shape type: reserved for compatibility */ + ai_u32 size : 24; /*!< size: shape cardinality */ + ai_shape_dimension* data; /*!< pointer to shape tuple array */ +} ai_buffer_shape; + +/*! + * @struct ai_buffer + * @ingroup ai_platform + * @brief Memory buffer storing data (optional) with a shape, size and type. + * This datastruct is used also for network querying, where the data field may + * may be NULL. + */ +typedef struct ai_buffer_ { + ai_buffer_format format; /*!< buffer format */ + ai_handle data; /*!< pointer to buffer data */ + ai_buffer_meta_info* meta_info; /*!< pointer to buffer metadata info */ + /* New 7.1 fields */ + ai_flags flags; /*!< shape optional flags */ + ai_size size; /*!< number of elements of the buffer (including optional padding) */ + ai_buffer_shape shape; /*!< n-dimensional shape info */ +} ai_buffer; + +/*! + * @struct ai_buffer_array + * @ingroup ai_platform + * @brief Array of @ref ai_buffer. + */ +typedef struct ai_buffer_array_ { + ai_u16 flags; /*!< buffer array flags */ + ai_u16 size; /*!< buffer array size */ + ai_buffer* buffer; /*!< buffer array buffers pointer */ +} ai_buffer_array; + +/* enums section */ + +/*! + * @enum ai_error_type + * @ingroup ai_platform + * + * Generic enum to list network error types. + */ +typedef enum { + AI_ERROR_NONE = 0x00, /*!< No error */ + AI_ERROR_TOOL_PLATFORM_API_MISMATCH = 0x01, + AI_ERROR_TYPES_MISMATCH = 0x02, + AI_ERROR_INVALID_HANDLE = 0x10, + AI_ERROR_INVALID_STATE = 0x11, + AI_ERROR_INVALID_INPUT = 0x12, + AI_ERROR_INVALID_OUTPUT = 0x13, + AI_ERROR_INVALID_PARAM = 0x14, + AI_ERROR_INVALID_SIGNATURE = 0x15, + AI_ERROR_INVALID_SIZE = 0x16, + AI_ERROR_INVALID_VALUE = 0x17, + AI_ERROR_INIT_FAILED = 0x30, + AI_ERROR_ALLOCATION_FAILED = 0x31, + AI_ERROR_DEALLOCATION_FAILED = 0x32, + AI_ERROR_CREATE_FAILED = 0x33, +} ai_error_type; + +/*! + * @enum ai_error_code + * @ingroup ai_platform + * + * Generic enum to list network error codes. + */ +typedef enum { + AI_ERROR_CODE_NONE = 0x0000, /*!< No error */ + AI_ERROR_CODE_NETWORK = 0x0010, + AI_ERROR_CODE_NETWORK_PARAMS = 0x0011, + AI_ERROR_CODE_NETWORK_WEIGHTS = 0x0012, + AI_ERROR_CODE_NETWORK_ACTIVATIONS = 0x0013, + AI_ERROR_CODE_LAYER = 0x0014, + AI_ERROR_CODE_TENSOR = 0x0015, + AI_ERROR_CODE_ARRAY = 0x0016, + AI_ERROR_CODE_INVALID_PTR = 0x0017, + AI_ERROR_CODE_INVALID_SIZE = 0x0018, + AI_ERROR_CODE_INVALID_FORMAT = 0x0019, + AI_ERROR_CODE_OUT_OF_RANGE = 0x0020, + AI_ERROR_CODE_INVALID_BATCH = 0x0021, + AI_ERROR_CODE_MISSED_INIT = 0x0030, + AI_ERROR_CODE_IN_USE = 0x0040, + AI_ERROR_CODE_LOCK = 0x0041, +} ai_error_code; + +/*! + * @struct ai_platform_version + * @ingroup ai_platform + * @brief Datastruct storing platform version info + */ +typedef struct ai_platform_version_ { + ai_u8 major; + ai_u8 minor; + ai_u8 micro; + ai_u8 reserved; +} ai_platform_version; + +/*! + * @struct ai_network_params + * @ingroup ai_platform + * + * Datastructure to pass parameters during network initialization. + */ +typedef struct ai_network_params_ { + AI_NETWORK_PARAMS_FIELDS_DECLARE +} ai_network_params; + +/*! + * @struct ai_network_buffers + * @ingroup ai_platform + * + * Datastructure to pass network buffers during network initialization. + */ +typedef struct ai_network_buffers_ { + AI_NETWORK_BUFFERS_FIELD_DECLARE +} ai_network_buffers; + +/*! + * @struct ai_network_report + * @ingroup ai_platform + * + * Datastructure to query a network report with some relevant network detail. + */ +typedef struct ai_network_report_ { + const char* model_name; + const char* model_signature; + const char* model_datetime; + + const char* compile_datetime; + + const char* runtime_revision; + ai_platform_version runtime_version; + + const char* tool_revision; + ai_platform_version tool_version; + ai_platform_version tool_api_version; + + ai_platform_version api_version; + ai_platform_version interface_api_version; + + ai_macc n_macc; + + ai_u16 n_inputs; + ai_u16 n_outputs; + ai_buffer* inputs; + ai_buffer* outputs; + + AI_NETWORK_PARAMS_FIELDS_DECLARE + + ai_u32 n_nodes; + + ai_signature signature; +} ai_network_report; + +/*! + * @enum ai_upsample_mode + * @ingroup ai_platform + * @brief allowed mode in upsample layer + */ +typedef enum { + AI_UPSAMPLE_ZEROS = 0x0, + AI_UPSAMPLE_NEAREST, + AI_UPSAMPLE_BILINEAR, + AI_UPSAMPLE_TRILINEAR +} ai_upsample_mode; + +/*! + * @enum ai_resize_mode + * @ingroup ai_platform + * @brief allowed mode in resize layer + */ +typedef enum { + AI_RESIZE_ZEROS = 0x0, + AI_RESIZE_NEAREST, + AI_RESIZE_LINEAR, + AI_RESIZE_CUBIC +} ai_resize_mode; + +/*! + * @enum ai_coord_transf_mode + * @ingroup ai_platform + * @brief coordinate_transformation_mode in resize layer + */ +typedef enum { + AI_HALF_PIXEL = 0x0, + AI_PYTORCH_HALF_PIXEL, + AI_ALIGN_CORNERS, + AI_ASYMMETRIC, + AI_TF_HALF_PIXEL_FOR_NN, + AI_TF_CROP_AND_RESIZE +} ai_coord_transf_mode; + +typedef enum { + AI_ROUND_PREFER_FLOOR = 0x0, + AI_ROUND_PREFER_CEIL, + AI_ROUND_FLOOR, + AI_ROUND_CEIL +} ai_nearest_mode; + +typedef enum { + AI_PAD_CONSTANT = 0x0, + AI_PAD_REFLECT, + AI_PAD_EDGE, + AI_PAD_8BIT_CH1ST_CONSTANT, +} ai_pad_mode; + +#define OUTPUT_PADDING_FLAG (1 << 0) +#define CHANNEL_FIRST_FLAG (1 << 1) +/* Padding pattern supported: */ +/* 0 = (1, 1, 1,1), 1 = (0, 0, 2, 2) */ +#define CHANNEL_PADDING_PATTERN (1 << 2) +/* Carefull when changing those definitions + bit0 shall always select output padding (Valid vs Same) + bit1 shall always select Channel first /channel lst format + bit2 shall always select padding pattern (1, 1, 1, 1) (stride1) or (0, 0, 2, 2) (stride2) +*/ +typedef enum { + AI_LAYER_FORMAT_CHANNEL_LAST_VALID = 0x0, + AI_LAYER_FORMAT_CHANNEL_LAST_SAME = 0x1, + AI_LAYER_FORMAT_CHANNEL_FIRST_VALID = 0x2, + AI_LAYER_FORMAT_CHANNEL_FIRST_SAME = 0x3, + AI_LAYER_FORMAT_CHANNEL_FIRST_SAME2 = 0x7, +} ai_layer_format_type; + +/*! ai_platform public APIs **************************************************/ + +/*! + * @brief get the total number of elements of an ai_buffer. + * @ingroup ai_platform + * @param buffer a pointer to an @ref ai_buffer + * @param with_padding when true it considers also padded elements + * @return the number of elements of the buffer (with/without padded ones) + */ +AI_API_ENTRY +ai_size ai_buffer_get_size(const ai_buffer* buffer, const ai_bool with_padding); + +/*! + * @brief get the size in bytes of an ai_buffer (given the number of elements and format). + * @ingroup ai_platform + * @param count the number of elements composing the buffer + * @param fmt the format of the ai_buffer + * @return the size in bytes of the buffer + */ +AI_API_ENTRY +ai_size ai_buffer_get_byte_size(const ai_size count, const ai_buffer_format fmt); + +/*! + * @brief get total size in bytes of a buffer array. + * @ingroup ai_platform + * @param barray a pointer to the buffer array + * @return the total size in bytes of all the buffer arrays + */ +AI_API_ENTRY +ai_bool ai_buffer_array_is_empty(const ai_buffer_array* barray); + +/*! + * @brief get total size in bytes of a buffer array. + * @ingroup ai_platform + * @param barray a pointer to the buffer array + * @return the total size in bytes of all the buffer arrays + */ +AI_API_ENTRY +ai_bool ai_buffer_array_is_valid(const ai_buffer_array* barray); + +/*! + * @brief check if a buffer array is valid - i.e. not empty. + * @ingroup ai_platform + * @param barray a pointer to the buffer array + * @return true if the array is consistent and not empty, false otherwise + */ +AI_API_ENTRY +ai_bool ai_buffer_array_sane(const ai_buffer_array* barray); + +/*! + * @brief get total size in bytes of a buffer array. + * @ingroup ai_platform + * @param barray a pointer to the buffer array + * @return the total size in bytes of all the buffer arrays + */ +AI_API_ENTRY +ai_size ai_buffer_array_get_byte_size(const ai_buffer_array* barray); + +/*! + * @brief set the address of buffer array item @pos + * @ingroup ai_platform + * @param barray a pointer to the buffer array + * @param pos the index of the element in the array + * @param address the address to set + * @return true if successful, false otherwise + */ +AI_API_ENTRY +ai_bool ai_buffer_array_item_set_address( + ai_buffer_array* barray, const ai_u32 pos, ai_handle address); + +AI_API_DECLARE_END + +#endif /*AI_PLATFORM_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_platform_interface.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_platform_interface.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_platform_interface.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_platform_interface.h index 4013015b..4076169e 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/ai_platform_interface.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/ai_platform_interface.h @@ -1,1087 +1,1087 @@ -/** - ****************************************************************************** - * @file ai_platform_interface.h - * @author AST Embedded Analytics Research Platform - * @brief Definitions of AI platform interface APIs types - ****************************************************************************** - * @attention - * - * Copyright (c) 2018 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef AI_PLATFORM_INTERFACE_H -#define AI_PLATFORM_INTERFACE_H - -#include "ai_platform.h" -#include "datatypes_network.h" -#include "ai_datatypes.h" -#include "ai_datatypes_defines.h" -#include "ai_datatypes_format.h" - -#include "stai.h" - -/*! - * @defgroup datatypes_interface Interface Datatypes - * @brief Data structures and defines used to implement neural networks - */ - -#define AI_MAGIC_LEGACY_TOKEN (0xA1C00103) - -#define AI_MAGIC_CONTEXT_TOKEN (0xA1C00100) /*!< Network Context Magic Token */ - -#define AI_MAGIC_INSPECTOR_TOKEN (0xB1C00100) /*!< Inspector Magic Token */ - - -/******************************************************************************/ -#define AI_ERROR_TRAP(net_, type_, code_) \ - ai_platform_network_set_error(AI_CONTEXT_OBJ(net_), AI_CONCAT(AI_ERROR_,type_), \ - AI_CONCAT(AI_ERROR_CODE_,code_)) - -/*! AI_PTR HANDLERS SECTION ************************************/ - -#define AI_PTR(ptr_) AI_CAST(ai_ptr, ptr_) -#define AI_PTR_CONST(ptr_) AI_CAST(ai_ptr_const, ptr_) - -/*! STATIC ARRAYS ALLOCATOR SECTION ************************************/ -#define AI_PACK_STORAGE_ARRAY(type_, dim_, ...) \ - (type_[dim_]) { AI_PACK(__VA_ARGS__) } - -/*! AI_STORAGE_KLASS SECTION ************************************/ -#define AI_STORAGE_KLASS_PACK(type_, dim_, ...) \ - AI_PACK_STORAGE_ARRAY(type_, dim_, __VA_ARGS__) - -#define AI_STORAGE_KLASS_INIT(type_, size_, data_) \ -{ \ - .type = (type_), \ - .size = (size_), \ - .data = (ai_handle)(data_), \ -} - -/*! - * @enum ai_storage_klass_type - * @ingroup ai_platform_interface - * @brief @ref ai_storage_class types enum - */ -typedef enum { - AI_STORAGE_KLASS_NONE = 0x00, - AI_STORAGE_KLASS_SHAPE = 0x01, - AI_STORAGE_KLASS_STRIDE = 0x02, -} ai_storage_klass_type; - -/*! - * @struct ai_storage_klass - * @ingroup ai_platform_interface - * @brief Generic "Template" klass for generic storage arrays containers - * from this klass several typed containers are derived (see e.g. @ref ai_shape) - */ -AI_PACKED_STRUCT_START -typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_storage_klass_s { - ai_u32 type : 8; - ai_u32 size : 24; - ai_handle data; -} ai_storage_klass; -AI_PACKED_STRUCT_END - -/*! AI_SHAPES SECTION ************************************/ -#define AI_SHAPE_MAX_DIMENSION (6) - - -#define AI_SHAPE_2D_INIT(w_, h_) \ - { .data = { (w_), (h_) } } - -#define AI_SHAPE_INIT(dim_, ...) \ - AI_STORAGE_KLASS_INIT( \ - AI_STORAGE_KLASS_SHAPE, \ - dim_, \ - AI_STORAGE_KLASS_PACK(ai_shape_dimension, dim_, ## __VA_ARGS__)) - -#define AI_SHAPE_INIT_FROM_BUFFER(dim_, buffer_) \ - AI_STORAGE_KLASS_INIT( \ - AI_STORAGE_KLASS_SHAPE, \ - dim_, \ - buffer_) - -#define AI_SHAPE_ALLOCATE_STATIC(num_dim_) \ - AI_SHAPE_INIT((num_dim_), 0) - - -typedef ai_u8 ai_shape_idx; - -/*! - * @struct ai_shape - * @ingroup ai_platform_interface - * @brief Dimensions for generic 4D tensors - */ -typedef ai_storage_klass ai_shape; - - -/*! AI_STRIDES HANDLERS SECTION ************************************/ -#define AI_STRIDE_INIT(dim_, ...) \ - AI_STORAGE_KLASS_INIT( \ - AI_STORAGE_KLASS_STRIDE, \ - dim_, \ - AI_STORAGE_KLASS_PACK(ai_stride_dimension, dim_, ## __VA_ARGS__)) - - -#define AI_STRIDE_INIT_FROM_BUFFER(dim_, buffer_) \ - AI_STORAGE_KLASS_INIT( \ - AI_STORAGE_KLASS_STRIDE, \ - dim_, \ - buffer_) - -#define AI_STRIDE_ALLOCATE_STATIC(num_dims_) \ - AI_STRIDE_INIT((num_dims_), 0) - - -/*! - * @struct ai_stride - * @ingroup ai_platform_interface - * @brief Stride dimensions for generic 4D tensors (in number of elements) - */ -typedef ai_storage_klass ai_stride; - -/*! BASIC_TYPES HANDLERS SECTION ************************************/ -#define AI_SIZE(value_) \ - AI_CAST(ai_size, value_) - -/*! AI_KLASS_OBJ HANDLERS SECTION ************************************/ -#define AI_KLASS_OBJ(obj_) \ - AI_CAST(ai_klass_obj, obj_) - -/*! GENERIC HANDLERS SECTION ************************************/ -#define AI_OBJ_DATA(obj_, type_) \ - AI_CAST(type_, (obj_)->data) - -/*! AI_BUFFER HANDLERS SECTION ************************************/ -#define AI_BUFFER_OBJ(ptr_) \ - AI_CAST(ai_buffer*, ptr_) - -/*! AI_ARRAY HANDLERS SECTION ************************************/ -#define AI_ARRAY_OBJ(ptr_) \ - AI_CAST(ai_array*, ptr_) - -#define AI_ARRAY_OBJ_INIT_STATIC(type_, format_, size_, ...) { \ - .format = AI_FMT_OBJ(format_), \ - .size = (ai_array_size)(size_), \ - .data = (ai_ptr)((type_[]){ __VA_ARGS__ }), \ - .data_start = AI_PTR(0), \ -} - -#define AI_ARRAY_OBJ_INIT(format_, data_, data_start_, size_) { \ - .format = AI_FMT_OBJ(format_), \ - .size = AI_CAST(ai_array_size, size_), \ - .data = AI_PTR(data_), \ - .data_start = AI_PTR(data_start_) } - -#define AI_ARRAY_OBJ_DECLARE_STATIC(name_, type_, format_, attr_, size_, ...) \ - AI_ALIGNED(4) \ - attr_ ai_array name_ = AI_ARRAY_OBJ_INIT_STATIC(type_, format_, size_, __VA_ARGS__); - - -#define AI_ARRAY_OBJ_DECLARE(name_, format_, data_, data_start_, size_, attr_) \ - AI_ALIGNED(4) \ - attr_ ai_array name_ = AI_ARRAY_OBJ_INIT(format_, data_, data_start_, size_); - - -/********************************* ai_array macros ***************************/ -#define AI_PACK_ARRAYS(...) \ - (ai_array[]) { AI_PACK(__VA_ARGS__) } - -#define AI_ARRAY_LIST_OBJ_INIT(arrays_ptr_) \ - ((ai_array*)(arrays_ptr_)) - -#define AI_ARRAY_LIST_FLAGS(list_) \ - ((list_) ? (list_)->flags : 0x0) - -#define AI_ARRAY_LIST_SIZE(list_) \ - ((list_) ? (list_)->size : 0) - -#define AI_ARRAY_LIST_DATA(list_, pos_) \ - ((list_) ? &((list_)->data[pos_]) : NULL) - - -/********************************* ai_tensor macros **************************/ -#define AI_TENSOR_OBJ(obj_) \ - AI_CAST(ai_tensor*, obj_) - -#define AI_TENSOR_INFO_OBJ_INIT(id_, flags_, data_size_) { \ - .id = (id_), \ - .flags = (flags_), \ - .data_size = (data_size_) \ -} - -#define AI_TENSOR_OBJ_INIT(id_, flags_, shape_, stride_, arrays_size_, arrays_ptr_, klass_obj_) { \ - .klass = (ai_klass_obj)(klass_obj_), \ - .info = AI_TENSOR_INFO_OBJ_INIT(id_, flags_, arrays_size_), \ - .shape = shape_, \ - .stride = stride_, \ - .data = AI_ARRAY_LIST_OBJ_INIT(AI_PACK(arrays_ptr_)), \ -} - -#define AI_TENSOR_OBJ_DECLARE(name_, attr_, id_, flags_, shape_, stride_, \ - arrays_size_, arrays_ptr_, klass_obj_) \ - AI_ALIGNED(4) \ - attr_ ai_tensor name_ = AI_TENSOR_OBJ_INIT(id_, flags_, AI_PACK(shape_), AI_PACK(stride_), \ - arrays_size_, AI_PACK(arrays_ptr_), AI_PACK(klass_obj_)); - - -/********************************* TENSOR STATE MACROS ***********************/ -#define AI_TENSOR_STATE_OBJ_INIT(end_ptr_ , curr_ptr_, stride_, size_) \ - { (end_ptr_), (curr_ptr_), (stride_), (size_) } - -/********************************* TENSOR LIST MACROS ************************/ -#if (AI_TOOLS_API_VERSION <= AI_TOOLS_API_VERSION_1_3) -#pragma message ("Including deprecated AI_TENSOR_LIST_ENTRY, AI_TENSOR_LIST_EMPTY, AI_TENSOR_LIST_IO_ENTRY") - -AI_DEPRECATED -#define AI_TENSOR_LIST_EMPTY \ - AI_TENSOR_LIST_OBJ_EMPTY - -AI_DEPRECATED -#define AI_TENSOR_LIST_ENTRY(...) \ - AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, AI_NUMARGS(__VA_ARGS__), __VA_ARGS__) - -AI_DEPRECATED -#define AI_TENSOR_LIST_IO_ENTRY(flags_, size_, ...) \ - AI_TENSOR_LIST_IO_OBJ_INIT(flags_, size_, __VA_ARGS__) - -#endif /* AI_TOOLS_API_VERSION_1_3 */ - -#define AI_TENSOR_LIST_OBJ_INIT(flags_, size_, ...) \ - { .size = (size_), .flags = (flags_), \ - .tensor = (ai_tensor*[]) { __VA_ARGS__ }, .info = NULL \ - } - -#define AI_TENSOR_LIST_OBJ_EMPTY \ - { .size = 0, .flags = AI_FLAG_NONE, \ - .tensor = (ai_tensor*[]) { NULL }, .info = NULL \ - } - -#define AI_TENSOR_LIST_OBJ_DECLARE(name_, attr_, flags_, size_, ...) \ - AI_ALIGNED(4) \ - attr_ ai_tensor_list name_ = AI_TENSOR_LIST_OBJ_INIT( \ - flags_, size_, __VA_ARGS__); - -/********************************* TENSOR LIST I/O MACROS ********************/ - -#define AI_TENSOR_LIST_IO_OBJ_INIT(flags_, size_, ...) \ - { .size = (size_), .flags = (flags_), \ - .tensor = (ai_tensor*[]) { __VA_ARGS__ }, \ - .info = (ai_tensor_list_info[1]) { { \ - .buffer = (ai_buffer[size_]){AI_STRUCT_INIT}, \ - .state = (ai_tensor_state[size_]){AI_STRUCT_INIT}, \ - .meta = (ai_buffer_meta_info[size_]){AI_STRUCT_INIT} \ - } } \ - } - -/********************************* TENSOR CHAIN MACROS ***********************/ -#define AI_TENSOR_CHAIN_OBJ_INIT(flags_, size_, ...) \ - { .size = (size_), .flags = (flags_), \ - .chain = (ai_tensor_list[]){ __VA_ARGS__ } } - -#define AI_TENSOR_CHAIN_OBJ_DECLARE(name_, attr_, size_, ...) \ - AI_ALIGNED(4) \ - attr_ ai_tensor_chain name_ = \ - AI_TENSOR_CHAIN_OBJ_INIT(AI_FLAG_NONE, size_, __VA_ARGS__); - - -/********************************* TENSOR CHAIN I/O MACROS *******************/ -#define AI_TENSOR_CHAIN_IO_OBJ_INIT(flags_, in_tensor_list_, out_tensor_list_) \ - { .chain = (ai_tensor_list[]){ in_tensor_list_, out_tensor_list_ }, \ - .size = 2, .flags = (flags_) } - -#define AI_TENSOR_CHAIN_IO_OBJ_DECLARE( \ - name_, attr_, flags_, in_tensor_list_, out_tensor_list_) \ - AI_ALIGNED(4) \ - attr_ ai_tensor_chain_io name_ = \ - AI_TENSOR_CHAIN_IO_OBJ_INIT(flags_, in_tensor_list_, out_tensor_list_); - -/******************************* NETWORK SECTION ****************************/ -#define AI_NETWORK_OBJ(obj_) \ - ((ai_network*)(obj_)) - - -#if (AI_TOOLS_API_VERSION < AI_TOOLS_API_VERSION_1_5) - -AI_DEPRECATED -#define AI_NETWORK_OBJ_INIT( \ - weights_buffer_, activations_buffer_, \ - in_tensor_list_ptr_, out_tensor_list_ptr_, \ - in_node_ptr_, signature_, klass_obj_) { \ - .magic = AI_MAGIC_CONTEXT_TOKEN, \ - .signature = signature_, \ - .tool_api_version = 0x0, \ - .error = AI_ERROR_INIT(NONE, NONE), \ - .flags = AI_FLAG_NONE, \ - .klass = AI_KLASS_OBJ(klass_obj_), \ - .n_batches = 0, \ - .batch_id = 0, \ - .buffers = AI_NETWORK_BUFFERS_INIT( \ - AI_BUFFER_ARRAY_OBJ_INIT_STATIC(AI_FLAG_NONE, 1, AI_PACK(weights_buffer_)), \ - AI_BUFFER_ARRAY_OBJ_INIT_STATIC(AI_FLAG_NONE, 1, AI_PACK(activations_buffer_))), \ - .tensors = AI_TENSOR_CHAIN_IO_OBJ_INIT(AI_FLAG_NONE, \ - AI_PACK(in_tensor_list_ptr_), \ - AI_PACK(out_tensor_list_ptr_)), \ - .input_node = AI_NODE_OBJ(in_node_ptr_), \ - .current_node = AI_NODE_OBJ(NULL), \ - .on_node_exec = NULL, \ - .data_exec = NULL, \ - .lite_cb = NULL, \ -} - -#else - -#define AI_NETWORK_OBJ_INIT( \ - weights_buffer_, activations_buffer_, \ - in_tensor_list_ptr_, out_tensor_list_ptr_, \ - in_node_ptr_, signature_, klass_obj_) { \ - .magic = AI_MAGIC_CONTEXT_TOKEN, \ - .signature = signature_, \ - .tool_api_version = 0x0, \ - .error = AI_ERROR_INIT(NONE, NONE), \ - .klass = AI_KLASS_OBJ(klass_obj_), \ - .flags = AI_FLAG_NONE, \ - .n_batches = 0, \ - .batch_id = 0, \ - .buffers = AI_NETWORK_BUFFERS_INIT(AI_PACK(weights_buffer_), \ - AI_PACK(activations_buffer_)), \ - .tensors = AI_TENSOR_CHAIN_IO_OBJ_INIT(AI_FLAG_NONE, \ - AI_PACK(in_tensor_list_ptr_), \ - AI_PACK(out_tensor_list_ptr_)), \ - .input_node = AI_NODE_OBJ(in_node_ptr_), \ - .current_node = AI_NODE_OBJ(NULL), \ - .on_node_exec = NULL, \ - .data_exec = NULL, \ - .lite_cb = NULL, \ -} - -#endif // AI_TOOLS_API_VERSION - - -#define AI_NETWORK_OBJ_DECLARE( \ - name_, attr_, \ - weights_buffer_, activations_buffer_, \ - in_tensor_list_ptr_, out_tensor_list_ptr_, \ - in_node_ptr_, signature_, klass_obj_) \ - AI_ALIGNED(4) \ - attr_ ai_network name_ = AI_NETWORK_OBJ_INIT( \ - AI_PACK(weights_buffer_), \ - AI_PACK(activations_buffer_), \ - AI_PACK(in_tensor_list_ptr_), \ - AI_PACK(out_tensor_list_ptr_), \ - (in_node_ptr_), (signature_), (klass_obj_)); - -#define AI_NETWORK_ACQUIRE_CTX(handle_) \ - AI_NETWORK_OBJ(ai_platform_context_acquire(handle_)) - -/******************************************************************************/ -AI_API_DECLARE_BEGIN - -/*! - * @typedef ai_version - * @ingroup ai_platform_interface - * @brief Packed representation for @ref ai_platform_version - */ -typedef uint32_t ai_version; - -/*! - * @typedef ai_klass_obj - * @ingroup ai_platform_interface - * @brief handler to (private) generic subclass derivatives implementation - */ -typedef void* ai_klass_obj; - -/*! - * @typedef ai_ptr - * @ingroup ai_platform_interface - * @brief Byte pointer data addressing - */ -typedef uint8_t* ai_ptr; - -/*! - * @typedef ai_ptr_const - * @ingroup ai_platform_interface - * @brief Constant byte pointer data addressing - */ -typedef const uint8_t* ai_ptr_const; - -/*! - * @typedef ai_ptr_offset - * @ingroup ai_platform_interface - * @brief byte offset for computing strides - */ -typedef int32_t ai_ptr_offset; - -/*! - * @typedef ai_magic - * @ingroup ai_platform_interface - * @brief magic field to mark internal datatstructures - */ -typedef uint32_t ai_magic; - -/*! - * @typedef ai_any_ptr - * @ingroup ai_platform_interface - * @brief union for defining any pointer - */ -typedef union { - ai_handle handle; - ai_ptr ptr; - ai_float* float32; - ai_double* float64; - ai_u8* u8; - ai_i8* s8; - ai_u16* u16; - ai_i16* s16; - ai_u32* u32; - ai_i32* s32; - ai_u64* u64; - ai_i64* s64; -} ai_any_ptr; - -#define AI_ANY_PTR_INIT(ptr_) \ - { .handle = (ai_handle)(ptr_) } - -#define AI_CONTEXT_FIELDS \ - ai_magic magic; /*!< magic word to mark valid contexts datastructs*/ \ - ai_signature signature; /*!< 32bit signature for network consistency checks */ \ - ai_version tool_api_version; /*! Tools Codegen API version */ \ - ai_error error; /*!< track 1st error code in the network */ \ - ai_flags flags; /*!< bitflags mask to track some network state info */ - -#define AI_CONTEXT_OBJ(obj) ((ai_context*)(obj)) - -/*! - * @typedef ai_context - * @ingroup ai_platform_interface - * @brief Abstract internal context header exposed to codegen interface - */ -AI_PACKED_STRUCT_START -typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED { - AI_CONTEXT_FIELDS -} ai_context; -AI_PACKED_STRUCT_END - -/*! - * @enum ai_shape_2d_type - * @ingroup ai_platform_interface - * @brief Codes for the 2D tensor dimensions - */ -typedef enum { - AI_SHAPE_2D_MAX_DIMENSION = 0x2, - AI_SHAPE_2D_HEIGHT = 0x1, - AI_SHAPE_2D_WIDTH = 0x0, -} ai_shape_2d_type; - - -/*! - * @struct ai_shape_2d - * @ingroup ai_platform_interface - * @brief Dimensions for generic 2D tensors - */ -AI_PACKED_STRUCT_START -typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_shape_2d_s { - ai_shape_dimension data[AI_SHAPE_2D_MAX_DIMENSION]; /*!< 2D tensor dimensions */ -} ai_shape_2d; -AI_PACKED_STRUCT_END - - -/*! - * @struct ai_array - * @ingroup ai_platform_interface - * @brief Generic flattened array with size - * and (byte) stride of each item - */ -AI_PACKED_STRUCT_START -typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_array_s { - ai_array_format format; /*!< array format (see @ref ai_array_format) */ - ai_array_size size; /*!< number of elements in the array (NOT number - of bytes!). The size of the array could be - determine using @ref AI_ARRAY_GET_BYTE_SIZE - macro */ - ai_ptr data; /*!< pointer to data */ - ai_ptr data_start; /*!< pointer to parent's data start address */ -} ai_array; -AI_PACKED_STRUCT_END - -/*! - * @struct ai_tensor_info - * @ingroup ai_platform_interface - * @brief ai_tensor_info info structure for storing size of the array list, - * tensor dimensionality, etc. - * - */ -AI_PACKED_STRUCT_START -typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_tensor_info_s { - ai_u16 id; - ai_u8 flags; - ai_u8 data_size; -} ai_tensor_info; -AI_PACKED_STRUCT_END - -/*! - * @struct ai_tensor - * @ingroup ai_platform_interface - * @brief Generic tensor structure for storing parameters and activations - * - * The data is stored in a flattened array with an implicit order given by the - * reverse order in @ref ai_shape_dimension: - * in_channels, channels, width, height. - */ -AI_PACKED_STRUCT_START -typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_tensor_s { - ai_klass_obj klass; /*!< opaque pointer to klass context */ - ai_tensor_info info; /*!< tensor info metadata see @ref ai_tensor_info)*/ - ai_shape shape; /*!< tensor shape see @ref ai_shape */ - ai_stride stride; /*!< tensor stride see @ref ai_stride */ - ai_array* data; /*!< flattened array pointer to tensor data */ -} ai_tensor; -AI_PACKED_STRUCT_END - -/*! - * @struct ai_tensor_state - * @ingroup ai_platform_interface - * @brief state context for tensor management (used for I/O network tensors) - */ -AI_PACKED_STRUCT_START -typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_tensor_state_s { - ai_ptr end_ptr; /*!< end address of the I/O tensor data buffer */ - ai_ptr curr_ptr; /*!< current address of the I/O tensor data buffer (for batching) */ - ai_ptr_offset stride; /*!< single batch buffer size (in bytes) */ - ai_size size; /*!< total size in bytes of the I/O tensor buffer */ -} ai_tensor_state; -AI_PACKED_STRUCT_END - -/*! - * @struct ai_tensor_list_info - * @ingroup ai_platform_interface - * @brief info metadata for tensor list management (used for I/O network tensors) - */ -AI_PACKED_STRUCT_START -typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_tensor_list_info_s { - ai_tensor_state* state; /*!< I/O buffer internal pointers state */ - ai_buffer* buffer; /*!< I/O buffer pointer */ - ai_buffer_meta_info* meta; /*!< I/O buffer meta informations */ -} ai_tensor_list_info; -AI_PACKED_STRUCT_END - -/********************************* INTEGER QUANTIZATION DATATYPES ************/ - -#define AI_INTQ_INFO_OBJ_INIT(flags_, scale_ , zeropoint_) { \ - .scale = (scale_), \ - .zeropoint = (ai_handle)(zeropoint_), \ - .flags = (flags_), \ -} - - -#define AI_PACK_INTQ_INFO_LIST(...) \ - (ai_intq_info_list[]) { AI_PACK(__VA_ARGS__) } - -#define AI_PACK_INTQ_INFO(scale_, zp_) \ - (INTQ_CONST ai_intq_info[1]) { { \ - .scale = (INTQ_CONST ai_float*) AI_PACK(scale_), \ - .zeropoint = (ai_handle) AI_PACK(zp_) \ - } } - -#define AI_PACK_INTQ_SCALE(...) \ - (INTQ_CONST ai_float[]) { AI_PACK(__VA_ARGS__) } - -#define AI_PACK_INTQ_ZP(...) \ - (INTQ_CONST ai_i8[]) { AI_PACK(__VA_ARGS__) } - -#define AI_PACK_UINTQ_ZP(...) \ - (INTQ_CONST ai_u8[]) { AI_PACK(__VA_ARGS__) } - -#define AI_PACK_INTQ_ZP16(...) \ - (INTQ_CONST ai_i16[]) { AI_PACK(__VA_ARGS__) } - -#define AI_PACK_UINTQ_ZP16(...) \ - (INTQ_CONST ai_u16[]) { AI_PACK(__VA_ARGS__) } - -#define AI_INTQ_INFO_LIST_OBJ_INIT(flags_, size_, info_) \ -{ \ - .flags = (flags_), \ - .size = (size_), \ - .info = (info_), \ -} - -#define AI_INTQ_INFO_LIST_OBJ_EMPTY { 0 } - -#define AI_INTQ_INFO_LIST_OBJ_DECLARE(name_, attr_, flags_, size_, info_) \ - AI_ALIGNED(4) \ - attr_ ai_intq_info_list name_ = \ - AI_INTQ_INFO_LIST_OBJ_INIT(flags_, size_, AI_PACK(info_)); - -#define AI_INTQ_INFO_LIST_OBJ_DECLARE_EMPTY(name_, attr_) \ - AI_ALIGNED(4) \ - attr_ ai_intq_info_list name_ = AI_INTQ_INFO_LIST_OBJ_EMPTY; - -/********************************* TENSOR CHAINS DATATYPES *******************/ -/*! - * @enum ai_tensor_chain_type - * @ingroup ai_platform_interface - * @brief Enum for the different tensor chains supported in the library - */ -typedef enum { - AI_TENSOR_CHAIN_INPUT = 0x0, - AI_TENSOR_CHAIN_OUTPUT = 0x1, - AI_TENSOR_CHAIN_WEIGHTS = 0x2, - AI_TENSOR_CHAIN_SCRATCH = 0x3, - AI_TENSOR_CHAIN_SIZE -} ai_tensor_chain_type; - -/*! - * @struct ai_tensor_list - * @ingroup ai_platform_interface - * @brief list (in form of arrays) of internal nodes tensor pointers - */ -AI_PACKED_STRUCT_START -typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_tensor_list_s { - ai_u16 size; /*!< number of elements in the the tensor list */ - ai_u16 flags; /*!< optional flags to store tensor list attributes */ - ai_tensor** tensor; /*!< array of linked tensor pointer */ - ai_tensor_list_info* info; /*!< pointer to an array of metainfo associated to the tensors */ -} ai_tensor_list; -AI_PACKED_STRUCT_END - - -/*! - * @struct ai_tensor_chain - * @ingroup ai_platform_interface - * @brief tensor chain datastruct for internal network nodes - */ -AI_PACKED_STRUCT_START -typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_tensor_chain_s { - ai_u16 size; - ai_u16 flags; - ai_tensor_list* chain; /*!< pointer to a 4 sized array see @ref ai_tensor_chain_type */ -} ai_tensor_chain; -AI_PACKED_STRUCT_END - -/************************************** LAYER DATATYPES *******************/ - -/*! - * @struct ai_layer - * @ingroup ai_platform_interface - * @brief Structure encoding a generic opaque layer in the network - * - */ -typedef void ai_layer; - - -/************************************** OBSERVER DATATYPES *******************/ - -/* forward function */ -struct ai_node_s; - -/*! - * @struct ai_observer_node - * @ingroup ai_observer_interface - * @brief observer node data struct for internal network nodes - */ -AI_PACKED_STRUCT_START -typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_observer_node_s { - ai_u16 c_idx; /*!< node index (position in the execution list) */ - ai_u16 type; /*!< node type info @see ai_node datastruct */ - ai_u16 id; /*!< node id assigned by codegen tool to identify the model layer*/ - ai_u16 unused; /*!< unused field for alignment */ - const ai_tensor_chain* inner_tensors; /*!< pointer to the inner tensor if available */ - const ai_tensor_chain* tensors; /*!< pointer to a 4 sized array see @ref ai_tensor_chain_type */ -} ai_observer_node; -AI_PACKED_STRUCT_END - -#define AI_OBSERVER_NONE_EVT (0) /*!< No event */ -#define AI_OBSERVER_INIT_EVT (1 << 0) /*!< called at the end of the init function */ -#define AI_OBSERVER_PRE_EVT (1 << 1) /*!< before c-node execution */ -#define AI_OBSERVER_POST_EVT (1 << 2) /*!< after c-node execution */ - -#define AI_OBSERVER_FIRST_EVT (1 << 8) /*!< indicate the first c-node */ -#define AI_OBSERVER_LAST_EVT (1 << 9) /*!< indicate the last c-node */ - -#define AI_OBSERVER_REGISTERED (1 << 24) /*!< internal flag */ - -#define AI_OBSERVER_MASK_EVT (0xFF) /*!< mask for requested user event */ - -/* Client callback definition */ -typedef ai_u32 (*ai_observer_node_cb)( - const ai_handle cookie, - const ai_u32 flags, - const ai_observer_node *node); - -AI_PACKED_STRUCT_START -typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_observer_exec_ctx_s { - ai_observer_node_cb on_node; /*!< registered user observer call-back function */ - ai_handle cookie; /*!< reference of the user context */ - ai_u32 flags; /*!< flags definition */ - ai_u16 c_idx; /*!< store/indicate the index of the current c_node */ - ai_u16 n_nodes; /*!< total number of c_node */ - struct ai_node_s *cur; /*!< pointer of the current node (pre or post) */ -} ai_observer_exec_ctx; -AI_PACKED_STRUCT_END - -typedef enum { - AI_NODE_EXEC_INIT = 0x0, - AI_NODE_EXEC_START = 0x1, - AI_NODE_EXEC_PRE = 0x2, - AI_NODE_EXEC_POST = 0x3, -} ai_node_exec_state; - -/* Internal/private definition of node execution callback */ -typedef ai_u32 (*ai_node_exec_cb)( - const ai_node_exec_state state, - struct ai_node_s *cur, - const ai_handle ctx); - - -/********************************* NETWORK DATATYPES *************************/ - -/*! - * @struct ai_network - * @ingroup layers - * @brief Structure encoding a sequential neural network - */ -AI_PACKED_STRUCT_START -typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED { - AI_CONTEXT_FIELDS - ai_klass_obj klass; /*!< opaque handler to specific network implementations */ - - ai_u16 n_batches; /*!< number of batches to process */ - ai_u16 batch_id; /*!< current batch to to process btw [0, n_batches)*/ - - // New 6.1 context storing explicitly network buffers. This allow also management of network persistent state now - ai_network_buffers buffers; /*!< network buffers datastruct */ - - ai_tensor_chain tensors; /*!< I/O tensor chain list see @ref ai_tensor_list */ - - struct ai_node_s* input_node; /*!< first node to execute */ - struct ai_node_s* current_node; /*!< current node to execute */ - - ai_node_exec_cb on_node_exec; /*!< registered call-back function called when - a node/operator is scheduled */ - ai_handle data_exec; /*!< private reference for the runtime context */ - ai_handle lite_cb; /*!< registered opaque call-back handler for lite APIs */ -} ai_network; -AI_PACKED_STRUCT_END - -/*! - * @struct ai_network - * @ingroup layers - * @brief Structure encoding a sequential neural network - */ -AI_PACKED_STRUCT_START -typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED { - AI_CONTEXT_FIELDS - // ai_klass_obj klass; /*!< opaque handler to specific network implementations */ - - // ai_u16 n_batches; /*!< number of batches to process */ - // ai_u16 batch_id; /*!< current batch to to process btw [0, n_batches)*/ - - ai_buffer* _inputs; - ai_buffer* _outputs; - ai_buffer_array _map_weights; - ai_buffer_array _map_activations; - ai_u64* _ctx; -} ai_network_context; -AI_PACKED_STRUCT_END - -/*! - * @brief Get platform runtime lib revision version as string. - * @ingroup ai_platform_interface - * @return a string containing the revision of the runtime library - */ -AI_INTERFACE_TYPE -const char* ai_platform_runtime_get_revision(void); - -/*! - * @brief Get platform runtime lib version as datastruct. - * @ingroup ai_platform_interface - * @return a datastruct containing the version of the runtime library - */ -AI_INTERFACE_TYPE -ai_platform_version ai_platform_runtime_get_version(void); - -/*! - * @brief Get platform public APIs version as datastruct. - * @ingroup ai_platform_interface - * @return a datastruct containing the version of the public APIs - */ -AI_INTERFACE_TYPE -ai_platform_version ai_platform_api_get_version(void); - -/*! - * @brief Get platform interface private APIs version as datastruct. - * @ingroup ai_platform_interface - * @return a datastruct containing the version of the interface private APIs - */ -AI_INTERFACE_TYPE -ai_platform_version ai_platform_interface_api_get_version(void); - - -/**************************************************************************** - ** Context APIs - ****************************************************************************/ -/*! - * @brief Get platform context. - * @ingroup ai_platform_interface - * @return a valid context handle or NULL otherwise - */ -AI_INTERFACE_TYPE -ai_context* ai_platform_context_acquire(const ai_handle handle); - -/*! - * @brief Release platform context. - * @ingroup ai_platform_interface - * @return an opaque handle to the released object - */ -AI_INTERFACE_TYPE -ai_handle ai_platform_context_release(ai_context* ctx); - - -/**************************************************************************** - ** Platform Network Params APIs - ****************************************************************************/ -/*! - * @brief get the weights map from user provided network params info - * @ingroup ai_platform_interface - * @param params a pointer to ai_network_params struct - * @param map table pointer to the table map to initialize - * @param map_size the number of entries of the table to initialize - * @return true if initialization succeeded, false otherwise - */ -AI_INTERFACE_TYPE -ai_bool ai_platform_get_weights_map( - ai_ptr* map, const ai_size map_size, const ai_network_params* params); - -/*! - * @brief get the activations map from user provided network params info - * @ingroup ai_platform_interface - * @param params a pointer to ai_network_params struct - * @param map table pointer to the table map to initialize - * @param map_size the number of entries of the table to initialize - * @return true if initialization succeeded, false otherwise - */ -AI_INTERFACE_TYPE -ai_bool ai_platform_get_activations_map( - ai_ptr* map, const ai_size map_size, const ai_network_params* params); - -/*! - * @brief bind code generated weights and activations map arrays to ai_netwoek_params - * @ingroup ai_platform_interface - * @param[out] params the network params struct reporting binded params - * @param[in] map_weights pointer to the codegened weights map array to be bound - * @param[in] map_activations pointer to the codegened activation map array to be bound - * @return true if network parameters binding succeed, false otherwise - */ -AI_INTERFACE_TYPE -ai_bool ai_platform_bind_network_params( - ai_network_params* params, - const ai_buffer_array* map_weights, const ai_buffer_array* map_activations); - -/**************************************************************************** - ** Platform Network APIs - ****************************************************************************/ -/*! - * @brief get **first** error tracked when using the network - * @ingroup ai_platform_interface - * @param network an opaque handler to the network context - * @return ai_error the FIRST error generated during network processing - */ -AI_INTERFACE_TYPE -ai_error ai_platform_network_get_error(ai_handle network); - - -/*! - * @brief Set specific error code of the network. if an error is already present - * keep it - * @ingroup ai_platform_interface - * @param net_ctx a pointer to the network context - * @param type error type as defined in @ref ai_error_type - * @param code error code as defined in @ref ai_error_code - * @return true if no previous errors where recorded, false if a previous error - * is present or context is invalid - */ -AI_INTERFACE_TYPE -ai_bool ai_platform_network_set_error( - ai_context* net_ctx, const ai_error_type type, const ai_error_code code); - -/*! - * @brief Finalize network report datastruct with I/O buffer infos - * @ingroup ai_platform_interface - * @return bool if the report has been finalized correctly. false otherwise - */ -AI_INTERFACE_TYPE -ai_bool ai_platform_api_get_network_report( - ai_handle network, ai_network_report* r); - - -/*! - * @brief Get network inputs array pointer as a ai_buffer array pointer. - * @ingroup network - * @param network an opaque handler to the network context - * @param n_buffer optional parameter to return the number of inputs - * @return a ai_buffer pointer to the inputs arrays - */ -AI_INTERFACE_TYPE -ai_buffer* ai_platform_inputs_get(ai_handle network, ai_u16 *n_buffer); - -/*! - * @brief Get network outputs array pointer as a ai_buffer array pointer. - * @ingroup network - * @param network an opaque handler to the network context - * @param n_buffer optional parameter to return the number of outputs - * @return a ai_buffer pointer to the inputs arrays - */ -AI_INTERFACE_TYPE -ai_buffer* ai_platform_outputs_get(ai_handle network, ai_u16 *n_buffer); - - -/*! - * @brief create a network context with some error check - * @ingroup ai_platform_interface - * @param a pointer to an opaque handle of the network context - * @param an (optional) pointer to the network config buffer info - * @param net_ctx a pointer to the network context structure to initialize - * @param tool_major major version id of the tool used to generate the network - * @param tool_minor minor version id of the tool used to generate the network - * @param tool_micro micro version id of the tool used to generate the network - * @return the error during network creation or error none if ok - */ -AI_INTERFACE_TYPE -ai_error ai_platform_network_create( - ai_handle* network, const ai_buffer* network_config, - ai_context* net_ctx, - const ai_u8 tool_major, const ai_u8 tool_minor, const ai_u8 tool_micro); - -/*! - * @brief destroy a network context - * @ingroup ai_platform_interface - * @param network a pointer to an opaque handle of the network context - * @return AI_HANDLE_NULL if deallocation OK, same network handle if failed - */ -AI_INTERFACE_TYPE -ai_handle ai_platform_network_destroy(ai_handle network); - -/*! - * @brief initialize the network context - * @ingroup ai_platform_interface - * @param network a pointer to an opaque handle of the network context - * @return a valid network context, NULL if initialization failed - */ -AI_INTERFACE_TYPE -ai_context* ai_platform_network_init( - ai_handle network, const ai_network_params* params); - -/*! - * @brief post-initialize of the network context. - * @ingroup ai_platform_interface - * @param network a pointer to an opaque handle of the network context - * @return a valid network context, NULL if initialization failed - */ -AI_INTERFACE_TYPE -ai_bool ai_platform_network_post_init(ai_handle network); - -/*! - * @brief main platform runtime execute of a network - * @ingroup ai_platform_interface - * @param network an opaque handler to the network context - * @param input a pointer to the input buffer data to process - * @param output a pointer to the output buffer - * @return the number of batches processed from the input. A result <=0 in case - * of error - */ -AI_INTERFACE_TYPE -ai_i32 ai_platform_network_process( - ai_handle network, const ai_buffer* input, ai_buffer* output); - - -/**************************************************************************** - ** ST.AI Wrapper APIs - ****************************************************************************/ -AI_INTERFACE_TYPE -void ai_platform_stai_handle_error( - ai_error* dst_error, - const stai_return_code code); - - -AI_INTERFACE_TYPE -ai_buffer* ai_platform_stai_bind_io( - ai_u16* n_buffer, - ai_buffer* dst_io_buffers, - const stai_ptr* src_io_buffers, - const stai_size src_io_buffers_size); - - -AI_INTERFACE_TYPE -ai_bool ai_platform_stai_update_io( - ai_i32* batch_id, - stai_ptr* dst_inputs, stai_ptr* dst_outputs, - const ai_buffer* src_inputs, const ai_buffer* src_outputs, - const ai_size n_inputs, const ai_size n_outputs); - -/**************************************************************************** - ** Observer APIs - ****************************************************************************/ - -/*! - * @brief Return the info of a requested c-node (defined by the - * c_idx field). Should be called after the initialization phase. - * @ingroup ai_platform_observer - * @param network a pointer to an opaque handle of the network context - * @param node_info a pointer to a reference of the node description - * @return true if the node_info->c_idx designates a valid index else - * false (network error is updated). - */ -AI_INTERFACE_TYPE -ai_bool ai_platform_observer_node_info( - ai_handle network, ai_observer_node *node_info); - -/*! - * @brief Register an observer context. Allows to register a client CB which - * will be called before or/and after the execution of a c-node with - * the references of the used tensors (see @ref ai_observer_node). - * @ingroup ai_platform_observer - * @param network a pointer to an opaque handle of the network context - * @param cb reference of the user callback function - * @param cookie reference of a user object/ctx - * @param flags indicate expected events (see AI_OBSERVER_XX_EVT flag definition) - * @return false if the registration has failed (network error is updated) else true - * of error. - */ -AI_INTERFACE_TYPE -ai_bool ai_platform_observer_register( - ai_handle network, - ai_observer_node_cb cb, - ai_handle cookie, - ai_u32 flags); - -AI_INTERFACE_TYPE -ai_bool ai_platform_observer_register_s(ai_handle network, - ai_observer_exec_ctx *ctx); - -/*! - * @brief un-register the observer context. - * @ingroup ai_platform_observer - * @param network a pointer to an opaque handle of the network context - * @param ctx a pointer to a reference of the registered platform observer context - * @param cb reference of the registered user callback function - * @param cookie reference of the registered user object/ctx - * @return false if the un-registration has failed (network error is updated) else true - * of error. - */ -AI_INTERFACE_TYPE -ai_bool ai_platform_observer_unregister(ai_handle network, - ai_observer_node_cb cb, ai_handle cookie); - -AI_INTERFACE_TYPE -ai_bool ai_platform_observer_unregister_s(ai_handle network, - ai_observer_exec_ctx *ctx); - -AI_API_DECLARE_END - -#endif /*AI_PLATFORM_INTERFACE_H*/ +/** + ****************************************************************************** + * @file ai_platform_interface.h + * @author AST Embedded Analytics Research Platform + * @brief Definitions of AI platform interface APIs types + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef AI_PLATFORM_INTERFACE_H +#define AI_PLATFORM_INTERFACE_H + +#include "ai_platform.h" +#include "datatypes_network.h" +#include "ai_datatypes.h" +#include "ai_datatypes_defines.h" +#include "ai_datatypes_format.h" + +#include "stai.h" + +/*! + * @defgroup datatypes_interface Interface Datatypes + * @brief Data structures and defines used to implement neural networks + */ + +#define AI_MAGIC_LEGACY_TOKEN (0xA1C00103) + +#define AI_MAGIC_CONTEXT_TOKEN (0xA1C00100) /*!< Network Context Magic Token */ + +#define AI_MAGIC_INSPECTOR_TOKEN (0xB1C00100) /*!< Inspector Magic Token */ + + +/******************************************************************************/ +#define AI_ERROR_TRAP(net_, type_, code_) \ + ai_platform_network_set_error(AI_CONTEXT_OBJ(net_), AI_CONCAT(AI_ERROR_,type_), \ + AI_CONCAT(AI_ERROR_CODE_,code_)) + +/*! AI_PTR HANDLERS SECTION ************************************/ + +#define AI_PTR(ptr_) AI_CAST(ai_ptr, ptr_) +#define AI_PTR_CONST(ptr_) AI_CAST(ai_ptr_const, ptr_) + +/*! STATIC ARRAYS ALLOCATOR SECTION ************************************/ +#define AI_PACK_STORAGE_ARRAY(type_, dim_, ...) \ + (type_[dim_]) { AI_PACK(__VA_ARGS__) } + +/*! AI_STORAGE_KLASS SECTION ************************************/ +#define AI_STORAGE_KLASS_PACK(type_, dim_, ...) \ + AI_PACK_STORAGE_ARRAY(type_, dim_, __VA_ARGS__) + +#define AI_STORAGE_KLASS_INIT(type_, size_, data_) \ +{ \ + .type = (type_), \ + .size = (size_), \ + .data = (ai_handle)(data_), \ +} + +/*! + * @enum ai_storage_klass_type + * @ingroup ai_platform_interface + * @brief @ref ai_storage_class types enum + */ +typedef enum { + AI_STORAGE_KLASS_NONE = 0x00, + AI_STORAGE_KLASS_SHAPE = 0x01, + AI_STORAGE_KLASS_STRIDE = 0x02, +} ai_storage_klass_type; + +/*! + * @struct ai_storage_klass + * @ingroup ai_platform_interface + * @brief Generic "Template" klass for generic storage arrays containers + * from this klass several typed containers are derived (see e.g. @ref ai_shape) + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_storage_klass_s { + ai_u32 type : 8; + ai_u32 size : 24; + ai_handle data; +} ai_storage_klass; +AI_PACKED_STRUCT_END + +/*! AI_SHAPES SECTION ************************************/ +#define AI_SHAPE_MAX_DIMENSION (6) + + +#define AI_SHAPE_2D_INIT(w_, h_) \ + { .data = { (w_), (h_) } } + +#define AI_SHAPE_INIT(dim_, ...) \ + AI_STORAGE_KLASS_INIT( \ + AI_STORAGE_KLASS_SHAPE, \ + dim_, \ + AI_STORAGE_KLASS_PACK(ai_shape_dimension, dim_, ## __VA_ARGS__)) + +#define AI_SHAPE_INIT_FROM_BUFFER(dim_, buffer_) \ + AI_STORAGE_KLASS_INIT( \ + AI_STORAGE_KLASS_SHAPE, \ + dim_, \ + buffer_) + +#define AI_SHAPE_ALLOCATE_STATIC(num_dim_) \ + AI_SHAPE_INIT((num_dim_), 0) + + +typedef ai_u8 ai_shape_idx; + +/*! + * @struct ai_shape + * @ingroup ai_platform_interface + * @brief Dimensions for generic 4D tensors + */ +typedef ai_storage_klass ai_shape; + + +/*! AI_STRIDES HANDLERS SECTION ************************************/ +#define AI_STRIDE_INIT(dim_, ...) \ + AI_STORAGE_KLASS_INIT( \ + AI_STORAGE_KLASS_STRIDE, \ + dim_, \ + AI_STORAGE_KLASS_PACK(ai_stride_dimension, dim_, ## __VA_ARGS__)) + + +#define AI_STRIDE_INIT_FROM_BUFFER(dim_, buffer_) \ + AI_STORAGE_KLASS_INIT( \ + AI_STORAGE_KLASS_STRIDE, \ + dim_, \ + buffer_) + +#define AI_STRIDE_ALLOCATE_STATIC(num_dims_) \ + AI_STRIDE_INIT((num_dims_), 0) + + +/*! + * @struct ai_stride + * @ingroup ai_platform_interface + * @brief Stride dimensions for generic 4D tensors (in number of elements) + */ +typedef ai_storage_klass ai_stride; + +/*! BASIC_TYPES HANDLERS SECTION ************************************/ +#define AI_SIZE(value_) \ + AI_CAST(ai_size, value_) + +/*! AI_KLASS_OBJ HANDLERS SECTION ************************************/ +#define AI_KLASS_OBJ(obj_) \ + AI_CAST(ai_klass_obj, obj_) + +/*! GENERIC HANDLERS SECTION ************************************/ +#define AI_OBJ_DATA(obj_, type_) \ + AI_CAST(type_, (obj_)->data) + +/*! AI_BUFFER HANDLERS SECTION ************************************/ +#define AI_BUFFER_OBJ(ptr_) \ + AI_CAST(ai_buffer*, ptr_) + +/*! AI_ARRAY HANDLERS SECTION ************************************/ +#define AI_ARRAY_OBJ(ptr_) \ + AI_CAST(ai_array*, ptr_) + +#define AI_ARRAY_OBJ_INIT_STATIC(type_, format_, size_, ...) { \ + .format = AI_FMT_OBJ(format_), \ + .size = (ai_array_size)(size_), \ + .data = (ai_ptr)((type_[]){ __VA_ARGS__ }), \ + .data_start = AI_PTR(0), \ +} + +#define AI_ARRAY_OBJ_INIT(format_, data_, data_start_, size_) { \ + .format = AI_FMT_OBJ(format_), \ + .size = AI_CAST(ai_array_size, size_), \ + .data = AI_PTR(data_), \ + .data_start = AI_PTR(data_start_) } + +#define AI_ARRAY_OBJ_DECLARE_STATIC(name_, type_, format_, attr_, size_, ...) \ + AI_ALIGNED(4) \ + attr_ ai_array name_ = AI_ARRAY_OBJ_INIT_STATIC(type_, format_, size_, __VA_ARGS__); + + +#define AI_ARRAY_OBJ_DECLARE(name_, format_, data_, data_start_, size_, attr_) \ + AI_ALIGNED(4) \ + attr_ ai_array name_ = AI_ARRAY_OBJ_INIT(format_, data_, data_start_, size_); + + +/********************************* ai_array macros ***************************/ +#define AI_PACK_ARRAYS(...) \ + (ai_array[]) { AI_PACK(__VA_ARGS__) } + +#define AI_ARRAY_LIST_OBJ_INIT(arrays_ptr_) \ + ((ai_array*)(arrays_ptr_)) + +#define AI_ARRAY_LIST_FLAGS(list_) \ + ((list_) ? (list_)->flags : 0x0) + +#define AI_ARRAY_LIST_SIZE(list_) \ + ((list_) ? (list_)->size : 0) + +#define AI_ARRAY_LIST_DATA(list_, pos_) \ + ((list_) ? &((list_)->data[pos_]) : NULL) + + +/********************************* ai_tensor macros **************************/ +#define AI_TENSOR_OBJ(obj_) \ + AI_CAST(ai_tensor*, obj_) + +#define AI_TENSOR_INFO_OBJ_INIT(id_, flags_, data_size_) { \ + .id = (id_), \ + .flags = (flags_), \ + .data_size = (data_size_) \ +} + +#define AI_TENSOR_OBJ_INIT(id_, flags_, shape_, stride_, arrays_size_, arrays_ptr_, klass_obj_) { \ + .klass = (ai_klass_obj)(klass_obj_), \ + .info = AI_TENSOR_INFO_OBJ_INIT(id_, flags_, arrays_size_), \ + .shape = shape_, \ + .stride = stride_, \ + .data = AI_ARRAY_LIST_OBJ_INIT(AI_PACK(arrays_ptr_)), \ +} + +#define AI_TENSOR_OBJ_DECLARE(name_, attr_, id_, flags_, shape_, stride_, \ + arrays_size_, arrays_ptr_, klass_obj_) \ + AI_ALIGNED(4) \ + attr_ ai_tensor name_ = AI_TENSOR_OBJ_INIT(id_, flags_, AI_PACK(shape_), AI_PACK(stride_), \ + arrays_size_, AI_PACK(arrays_ptr_), AI_PACK(klass_obj_)); + + +/********************************* TENSOR STATE MACROS ***********************/ +#define AI_TENSOR_STATE_OBJ_INIT(end_ptr_ , curr_ptr_, stride_, size_) \ + { (end_ptr_), (curr_ptr_), (stride_), (size_) } + +/********************************* TENSOR LIST MACROS ************************/ +#if (AI_TOOLS_API_VERSION <= AI_TOOLS_API_VERSION_1_3) +#pragma message ("Including deprecated AI_TENSOR_LIST_ENTRY, AI_TENSOR_LIST_EMPTY, AI_TENSOR_LIST_IO_ENTRY") + +AI_DEPRECATED +#define AI_TENSOR_LIST_EMPTY \ + AI_TENSOR_LIST_OBJ_EMPTY + +AI_DEPRECATED +#define AI_TENSOR_LIST_ENTRY(...) \ + AI_TENSOR_LIST_OBJ_INIT(AI_FLAG_NONE, AI_NUMARGS(__VA_ARGS__), __VA_ARGS__) + +AI_DEPRECATED +#define AI_TENSOR_LIST_IO_ENTRY(flags_, size_, ...) \ + AI_TENSOR_LIST_IO_OBJ_INIT(flags_, size_, __VA_ARGS__) + +#endif /* AI_TOOLS_API_VERSION_1_3 */ + +#define AI_TENSOR_LIST_OBJ_INIT(flags_, size_, ...) \ + { .size = (size_), .flags = (flags_), \ + .tensor = (ai_tensor*[]) { __VA_ARGS__ }, .info = NULL \ + } + +#define AI_TENSOR_LIST_OBJ_EMPTY \ + { .size = 0, .flags = AI_FLAG_NONE, \ + .tensor = (ai_tensor*[]) { NULL }, .info = NULL \ + } + +#define AI_TENSOR_LIST_OBJ_DECLARE(name_, attr_, flags_, size_, ...) \ + AI_ALIGNED(4) \ + attr_ ai_tensor_list name_ = AI_TENSOR_LIST_OBJ_INIT( \ + flags_, size_, __VA_ARGS__); + +/********************************* TENSOR LIST I/O MACROS ********************/ + +#define AI_TENSOR_LIST_IO_OBJ_INIT(flags_, size_, ...) \ + { .size = (size_), .flags = (flags_), \ + .tensor = (ai_tensor*[]) { __VA_ARGS__ }, \ + .info = (ai_tensor_list_info[1]) { { \ + .buffer = (ai_buffer[size_]){AI_STRUCT_INIT}, \ + .state = (ai_tensor_state[size_]){AI_STRUCT_INIT}, \ + .meta = (ai_buffer_meta_info[size_]){AI_STRUCT_INIT} \ + } } \ + } + +/********************************* TENSOR CHAIN MACROS ***********************/ +#define AI_TENSOR_CHAIN_OBJ_INIT(flags_, size_, ...) \ + { .size = (size_), .flags = (flags_), \ + .chain = (ai_tensor_list[]){ __VA_ARGS__ } } + +#define AI_TENSOR_CHAIN_OBJ_DECLARE(name_, attr_, size_, ...) \ + AI_ALIGNED(4) \ + attr_ ai_tensor_chain name_ = \ + AI_TENSOR_CHAIN_OBJ_INIT(AI_FLAG_NONE, size_, __VA_ARGS__); + + +/********************************* TENSOR CHAIN I/O MACROS *******************/ +#define AI_TENSOR_CHAIN_IO_OBJ_INIT(flags_, in_tensor_list_, out_tensor_list_) \ + { .chain = (ai_tensor_list[]){ in_tensor_list_, out_tensor_list_ }, \ + .size = 2, .flags = (flags_) } + +#define AI_TENSOR_CHAIN_IO_OBJ_DECLARE( \ + name_, attr_, flags_, in_tensor_list_, out_tensor_list_) \ + AI_ALIGNED(4) \ + attr_ ai_tensor_chain_io name_ = \ + AI_TENSOR_CHAIN_IO_OBJ_INIT(flags_, in_tensor_list_, out_tensor_list_); + +/******************************* NETWORK SECTION ****************************/ +#define AI_NETWORK_OBJ(obj_) \ + ((ai_network*)(obj_)) + + +#if (AI_TOOLS_API_VERSION < AI_TOOLS_API_VERSION_1_5) + +AI_DEPRECATED +#define AI_NETWORK_OBJ_INIT( \ + weights_buffer_, activations_buffer_, \ + in_tensor_list_ptr_, out_tensor_list_ptr_, \ + in_node_ptr_, signature_, klass_obj_) { \ + .magic = AI_MAGIC_CONTEXT_TOKEN, \ + .signature = signature_, \ + .tool_api_version = 0x0, \ + .error = AI_ERROR_INIT(NONE, NONE), \ + .flags = AI_FLAG_NONE, \ + .klass = AI_KLASS_OBJ(klass_obj_), \ + .n_batches = 0, \ + .batch_id = 0, \ + .buffers = AI_NETWORK_BUFFERS_INIT( \ + AI_BUFFER_ARRAY_OBJ_INIT_STATIC(AI_FLAG_NONE, 1, AI_PACK(weights_buffer_)), \ + AI_BUFFER_ARRAY_OBJ_INIT_STATIC(AI_FLAG_NONE, 1, AI_PACK(activations_buffer_))), \ + .tensors = AI_TENSOR_CHAIN_IO_OBJ_INIT(AI_FLAG_NONE, \ + AI_PACK(in_tensor_list_ptr_), \ + AI_PACK(out_tensor_list_ptr_)), \ + .input_node = AI_NODE_OBJ(in_node_ptr_), \ + .current_node = AI_NODE_OBJ(NULL), \ + .on_node_exec = NULL, \ + .data_exec = NULL, \ + .lite_cb = NULL, \ +} + +#else + +#define AI_NETWORK_OBJ_INIT( \ + weights_buffer_, activations_buffer_, \ + in_tensor_list_ptr_, out_tensor_list_ptr_, \ + in_node_ptr_, signature_, klass_obj_) { \ + .magic = AI_MAGIC_CONTEXT_TOKEN, \ + .signature = signature_, \ + .tool_api_version = 0x0, \ + .error = AI_ERROR_INIT(NONE, NONE), \ + .klass = AI_KLASS_OBJ(klass_obj_), \ + .flags = AI_FLAG_NONE, \ + .n_batches = 0, \ + .batch_id = 0, \ + .buffers = AI_NETWORK_BUFFERS_INIT(AI_PACK(weights_buffer_), \ + AI_PACK(activations_buffer_)), \ + .tensors = AI_TENSOR_CHAIN_IO_OBJ_INIT(AI_FLAG_NONE, \ + AI_PACK(in_tensor_list_ptr_), \ + AI_PACK(out_tensor_list_ptr_)), \ + .input_node = AI_NODE_OBJ(in_node_ptr_), \ + .current_node = AI_NODE_OBJ(NULL), \ + .on_node_exec = NULL, \ + .data_exec = NULL, \ + .lite_cb = NULL, \ +} + +#endif // AI_TOOLS_API_VERSION + + +#define AI_NETWORK_OBJ_DECLARE( \ + name_, attr_, \ + weights_buffer_, activations_buffer_, \ + in_tensor_list_ptr_, out_tensor_list_ptr_, \ + in_node_ptr_, signature_, klass_obj_) \ + AI_ALIGNED(4) \ + attr_ ai_network name_ = AI_NETWORK_OBJ_INIT( \ + AI_PACK(weights_buffer_), \ + AI_PACK(activations_buffer_), \ + AI_PACK(in_tensor_list_ptr_), \ + AI_PACK(out_tensor_list_ptr_), \ + (in_node_ptr_), (signature_), (klass_obj_)); + +#define AI_NETWORK_ACQUIRE_CTX(handle_) \ + AI_NETWORK_OBJ(ai_platform_context_acquire(handle_)) + +/******************************************************************************/ +AI_API_DECLARE_BEGIN + +/*! + * @typedef ai_version + * @ingroup ai_platform_interface + * @brief Packed representation for @ref ai_platform_version + */ +typedef uint32_t ai_version; + +/*! + * @typedef ai_klass_obj + * @ingroup ai_platform_interface + * @brief handler to (private) generic subclass derivatives implementation + */ +typedef void* ai_klass_obj; + +/*! + * @typedef ai_ptr + * @ingroup ai_platform_interface + * @brief Byte pointer data addressing + */ +typedef uint8_t* ai_ptr; + +/*! + * @typedef ai_ptr_const + * @ingroup ai_platform_interface + * @brief Constant byte pointer data addressing + */ +typedef const uint8_t* ai_ptr_const; + +/*! + * @typedef ai_ptr_offset + * @ingroup ai_platform_interface + * @brief byte offset for computing strides + */ +typedef int32_t ai_ptr_offset; + +/*! + * @typedef ai_magic + * @ingroup ai_platform_interface + * @brief magic field to mark internal datatstructures + */ +typedef uint32_t ai_magic; + +/*! + * @typedef ai_any_ptr + * @ingroup ai_platform_interface + * @brief union for defining any pointer + */ +typedef union { + ai_handle handle; + ai_ptr ptr; + ai_float* float32; + ai_double* float64; + ai_u8* u8; + ai_i8* s8; + ai_u16* u16; + ai_i16* s16; + ai_u32* u32; + ai_i32* s32; + ai_u64* u64; + ai_i64* s64; +} ai_any_ptr; + +#define AI_ANY_PTR_INIT(ptr_) \ + { .handle = (ai_handle)(ptr_) } + +#define AI_CONTEXT_FIELDS \ + ai_magic magic; /*!< magic word to mark valid contexts datastructs*/ \ + ai_signature signature; /*!< 32bit signature for network consistency checks */ \ + ai_version tool_api_version; /*! Tools Codegen API version */ \ + ai_error error; /*!< track 1st error code in the network */ \ + ai_flags flags; /*!< bitflags mask to track some network state info */ + +#define AI_CONTEXT_OBJ(obj) ((ai_context*)(obj)) + +/*! + * @typedef ai_context + * @ingroup ai_platform_interface + * @brief Abstract internal context header exposed to codegen interface + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED { + AI_CONTEXT_FIELDS +} ai_context; +AI_PACKED_STRUCT_END + +/*! + * @enum ai_shape_2d_type + * @ingroup ai_platform_interface + * @brief Codes for the 2D tensor dimensions + */ +typedef enum { + AI_SHAPE_2D_MAX_DIMENSION = 0x2, + AI_SHAPE_2D_HEIGHT = 0x1, + AI_SHAPE_2D_WIDTH = 0x0, +} ai_shape_2d_type; + + +/*! + * @struct ai_shape_2d + * @ingroup ai_platform_interface + * @brief Dimensions for generic 2D tensors + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_shape_2d_s { + ai_shape_dimension data[AI_SHAPE_2D_MAX_DIMENSION]; /*!< 2D tensor dimensions */ +} ai_shape_2d; +AI_PACKED_STRUCT_END + + +/*! + * @struct ai_array + * @ingroup ai_platform_interface + * @brief Generic flattened array with size + * and (byte) stride of each item + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_array_s { + ai_array_format format; /*!< array format (see @ref ai_array_format) */ + ai_array_size size; /*!< number of elements in the array (NOT number + of bytes!). The size of the array could be + determine using @ref AI_ARRAY_GET_BYTE_SIZE + macro */ + ai_ptr data; /*!< pointer to data */ + ai_ptr data_start; /*!< pointer to parent's data start address */ +} ai_array; +AI_PACKED_STRUCT_END + +/*! + * @struct ai_tensor_info + * @ingroup ai_platform_interface + * @brief ai_tensor_info info structure for storing size of the array list, + * tensor dimensionality, etc. + * + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_tensor_info_s { + ai_u16 id; + ai_u8 flags; + ai_u8 data_size; +} ai_tensor_info; +AI_PACKED_STRUCT_END + +/*! + * @struct ai_tensor + * @ingroup ai_platform_interface + * @brief Generic tensor structure for storing parameters and activations + * + * The data is stored in a flattened array with an implicit order given by the + * reverse order in @ref ai_shape_dimension: + * in_channels, channels, width, height. + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_tensor_s { + ai_klass_obj klass; /*!< opaque pointer to klass context */ + ai_tensor_info info; /*!< tensor info metadata see @ref ai_tensor_info)*/ + ai_shape shape; /*!< tensor shape see @ref ai_shape */ + ai_stride stride; /*!< tensor stride see @ref ai_stride */ + ai_array* data; /*!< flattened array pointer to tensor data */ +} ai_tensor; +AI_PACKED_STRUCT_END + +/*! + * @struct ai_tensor_state + * @ingroup ai_platform_interface + * @brief state context for tensor management (used for I/O network tensors) + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_tensor_state_s { + ai_ptr end_ptr; /*!< end address of the I/O tensor data buffer */ + ai_ptr curr_ptr; /*!< current address of the I/O tensor data buffer (for batching) */ + ai_ptr_offset stride; /*!< single batch buffer size (in bytes) */ + ai_size size; /*!< total size in bytes of the I/O tensor buffer */ +} ai_tensor_state; +AI_PACKED_STRUCT_END + +/*! + * @struct ai_tensor_list_info + * @ingroup ai_platform_interface + * @brief info metadata for tensor list management (used for I/O network tensors) + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_tensor_list_info_s { + ai_tensor_state* state; /*!< I/O buffer internal pointers state */ + ai_buffer* buffer; /*!< I/O buffer pointer */ + ai_buffer_meta_info* meta; /*!< I/O buffer meta informations */ +} ai_tensor_list_info; +AI_PACKED_STRUCT_END + +/********************************* INTEGER QUANTIZATION DATATYPES ************/ + +#define AI_INTQ_INFO_OBJ_INIT(flags_, scale_ , zeropoint_) { \ + .scale = (scale_), \ + .zeropoint = (ai_handle)(zeropoint_), \ + .flags = (flags_), \ +} + + +#define AI_PACK_INTQ_INFO_LIST(...) \ + (ai_intq_info_list[]) { AI_PACK(__VA_ARGS__) } + +#define AI_PACK_INTQ_INFO(scale_, zp_) \ + (INTQ_CONST ai_intq_info[1]) { { \ + .scale = (INTQ_CONST ai_float*) AI_PACK(scale_), \ + .zeropoint = (ai_handle) AI_PACK(zp_) \ + } } + +#define AI_PACK_INTQ_SCALE(...) \ + (INTQ_CONST ai_float[]) { AI_PACK(__VA_ARGS__) } + +#define AI_PACK_INTQ_ZP(...) \ + (INTQ_CONST ai_i8[]) { AI_PACK(__VA_ARGS__) } + +#define AI_PACK_UINTQ_ZP(...) \ + (INTQ_CONST ai_u8[]) { AI_PACK(__VA_ARGS__) } + +#define AI_PACK_INTQ_ZP16(...) \ + (INTQ_CONST ai_i16[]) { AI_PACK(__VA_ARGS__) } + +#define AI_PACK_UINTQ_ZP16(...) \ + (INTQ_CONST ai_u16[]) { AI_PACK(__VA_ARGS__) } + +#define AI_INTQ_INFO_LIST_OBJ_INIT(flags_, size_, info_) \ +{ \ + .flags = (flags_), \ + .size = (size_), \ + .info = (info_), \ +} + +#define AI_INTQ_INFO_LIST_OBJ_EMPTY { 0 } + +#define AI_INTQ_INFO_LIST_OBJ_DECLARE(name_, attr_, flags_, size_, info_) \ + AI_ALIGNED(4) \ + attr_ ai_intq_info_list name_ = \ + AI_INTQ_INFO_LIST_OBJ_INIT(flags_, size_, AI_PACK(info_)); + +#define AI_INTQ_INFO_LIST_OBJ_DECLARE_EMPTY(name_, attr_) \ + AI_ALIGNED(4) \ + attr_ ai_intq_info_list name_ = AI_INTQ_INFO_LIST_OBJ_EMPTY; + +/********************************* TENSOR CHAINS DATATYPES *******************/ +/*! + * @enum ai_tensor_chain_type + * @ingroup ai_platform_interface + * @brief Enum for the different tensor chains supported in the library + */ +typedef enum { + AI_TENSOR_CHAIN_INPUT = 0x0, + AI_TENSOR_CHAIN_OUTPUT = 0x1, + AI_TENSOR_CHAIN_WEIGHTS = 0x2, + AI_TENSOR_CHAIN_SCRATCH = 0x3, + AI_TENSOR_CHAIN_SIZE +} ai_tensor_chain_type; + +/*! + * @struct ai_tensor_list + * @ingroup ai_platform_interface + * @brief list (in form of arrays) of internal nodes tensor pointers + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_tensor_list_s { + ai_u16 size; /*!< number of elements in the the tensor list */ + ai_u16 flags; /*!< optional flags to store tensor list attributes */ + ai_tensor** tensor; /*!< array of linked tensor pointer */ + ai_tensor_list_info* info; /*!< pointer to an array of metainfo associated to the tensors */ +} ai_tensor_list; +AI_PACKED_STRUCT_END + + +/*! + * @struct ai_tensor_chain + * @ingroup ai_platform_interface + * @brief tensor chain datastruct for internal network nodes + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_tensor_chain_s { + ai_u16 size; + ai_u16 flags; + ai_tensor_list* chain; /*!< pointer to a 4 sized array see @ref ai_tensor_chain_type */ +} ai_tensor_chain; +AI_PACKED_STRUCT_END + +/************************************** LAYER DATATYPES *******************/ + +/*! + * @struct ai_layer + * @ingroup ai_platform_interface + * @brief Structure encoding a generic opaque layer in the network + * + */ +typedef void ai_layer; + + +/************************************** OBSERVER DATATYPES *******************/ + +/* forward function */ +struct ai_node_s; + +/*! + * @struct ai_observer_node + * @ingroup ai_observer_interface + * @brief observer node data struct for internal network nodes + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_observer_node_s { + ai_u16 c_idx; /*!< node index (position in the execution list) */ + ai_u16 type; /*!< node type info @see ai_node datastruct */ + ai_u16 id; /*!< node id assigned by codegen tool to identify the model layer*/ + ai_u16 unused; /*!< unused field for alignment */ + const ai_tensor_chain* inner_tensors; /*!< pointer to the inner tensor if available */ + const ai_tensor_chain* tensors; /*!< pointer to a 4 sized array see @ref ai_tensor_chain_type */ +} ai_observer_node; +AI_PACKED_STRUCT_END + +#define AI_OBSERVER_NONE_EVT (0) /*!< No event */ +#define AI_OBSERVER_INIT_EVT (1 << 0) /*!< called at the end of the init function */ +#define AI_OBSERVER_PRE_EVT (1 << 1) /*!< before c-node execution */ +#define AI_OBSERVER_POST_EVT (1 << 2) /*!< after c-node execution */ + +#define AI_OBSERVER_FIRST_EVT (1 << 8) /*!< indicate the first c-node */ +#define AI_OBSERVER_LAST_EVT (1 << 9) /*!< indicate the last c-node */ + +#define AI_OBSERVER_REGISTERED (1 << 24) /*!< internal flag */ + +#define AI_OBSERVER_MASK_EVT (0xFF) /*!< mask for requested user event */ + +/* Client callback definition */ +typedef ai_u32 (*ai_observer_node_cb)( + const ai_handle cookie, + const ai_u32 flags, + const ai_observer_node *node); + +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED ai_observer_exec_ctx_s { + ai_observer_node_cb on_node; /*!< registered user observer call-back function */ + ai_handle cookie; /*!< reference of the user context */ + ai_u32 flags; /*!< flags definition */ + ai_u16 c_idx; /*!< store/indicate the index of the current c_node */ + ai_u16 n_nodes; /*!< total number of c_node */ + struct ai_node_s *cur; /*!< pointer of the current node (pre or post) */ +} ai_observer_exec_ctx; +AI_PACKED_STRUCT_END + +typedef enum { + AI_NODE_EXEC_INIT = 0x0, + AI_NODE_EXEC_START = 0x1, + AI_NODE_EXEC_PRE = 0x2, + AI_NODE_EXEC_POST = 0x3, +} ai_node_exec_state; + +/* Internal/private definition of node execution callback */ +typedef ai_u32 (*ai_node_exec_cb)( + const ai_node_exec_state state, + struct ai_node_s *cur, + const ai_handle ctx); + + +/********************************* NETWORK DATATYPES *************************/ + +/*! + * @struct ai_network + * @ingroup layers + * @brief Structure encoding a sequential neural network + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED { + AI_CONTEXT_FIELDS + ai_klass_obj klass; /*!< opaque handler to specific network implementations */ + + ai_u16 n_batches; /*!< number of batches to process */ + ai_u16 batch_id; /*!< current batch to to process btw [0, n_batches)*/ + + // New 6.1 context storing explicitly network buffers. This allow also management of network persistent state now + ai_network_buffers buffers; /*!< network buffers datastruct */ + + ai_tensor_chain tensors; /*!< I/O tensor chain list see @ref ai_tensor_list */ + + struct ai_node_s* input_node; /*!< first node to execute */ + struct ai_node_s* current_node; /*!< current node to execute */ + + ai_node_exec_cb on_node_exec; /*!< registered call-back function called when + a node/operator is scheduled */ + ai_handle data_exec; /*!< private reference for the runtime context */ + ai_handle lite_cb; /*!< registered opaque call-back handler for lite APIs */ +} ai_network; +AI_PACKED_STRUCT_END + +/*! + * @struct ai_network + * @ingroup layers + * @brief Structure encoding a sequential neural network + */ +AI_PACKED_STRUCT_START +typedef AI_ALIGNED_TYPE(struct, 4) AI_PACKED { + AI_CONTEXT_FIELDS + // ai_klass_obj klass; /*!< opaque handler to specific network implementations */ + + // ai_u16 n_batches; /*!< number of batches to process */ + // ai_u16 batch_id; /*!< current batch to to process btw [0, n_batches)*/ + + ai_buffer* _inputs; + ai_buffer* _outputs; + ai_buffer_array _map_weights; + ai_buffer_array _map_activations; + ai_u64* _ctx; +} ai_network_context; +AI_PACKED_STRUCT_END + +/*! + * @brief Get platform runtime lib revision version as string. + * @ingroup ai_platform_interface + * @return a string containing the revision of the runtime library + */ +AI_INTERFACE_TYPE +const char* ai_platform_runtime_get_revision(void); + +/*! + * @brief Get platform runtime lib version as datastruct. + * @ingroup ai_platform_interface + * @return a datastruct containing the version of the runtime library + */ +AI_INTERFACE_TYPE +ai_platform_version ai_platform_runtime_get_version(void); + +/*! + * @brief Get platform public APIs version as datastruct. + * @ingroup ai_platform_interface + * @return a datastruct containing the version of the public APIs + */ +AI_INTERFACE_TYPE +ai_platform_version ai_platform_api_get_version(void); + +/*! + * @brief Get platform interface private APIs version as datastruct. + * @ingroup ai_platform_interface + * @return a datastruct containing the version of the interface private APIs + */ +AI_INTERFACE_TYPE +ai_platform_version ai_platform_interface_api_get_version(void); + + +/**************************************************************************** + ** Context APIs + ****************************************************************************/ +/*! + * @brief Get platform context. + * @ingroup ai_platform_interface + * @return a valid context handle or NULL otherwise + */ +AI_INTERFACE_TYPE +ai_context* ai_platform_context_acquire(const ai_handle handle); + +/*! + * @brief Release platform context. + * @ingroup ai_platform_interface + * @return an opaque handle to the released object + */ +AI_INTERFACE_TYPE +ai_handle ai_platform_context_release(ai_context* ctx); + + +/**************************************************************************** + ** Platform Network Params APIs + ****************************************************************************/ +/*! + * @brief get the weights map from user provided network params info + * @ingroup ai_platform_interface + * @param params a pointer to ai_network_params struct + * @param map table pointer to the table map to initialize + * @param map_size the number of entries of the table to initialize + * @return true if initialization succeeded, false otherwise + */ +AI_INTERFACE_TYPE +ai_bool ai_platform_get_weights_map( + ai_ptr* map, const ai_size map_size, const ai_network_params* params); + +/*! + * @brief get the activations map from user provided network params info + * @ingroup ai_platform_interface + * @param params a pointer to ai_network_params struct + * @param map table pointer to the table map to initialize + * @param map_size the number of entries of the table to initialize + * @return true if initialization succeeded, false otherwise + */ +AI_INTERFACE_TYPE +ai_bool ai_platform_get_activations_map( + ai_ptr* map, const ai_size map_size, const ai_network_params* params); + +/*! + * @brief bind code generated weights and activations map arrays to ai_netwoek_params + * @ingroup ai_platform_interface + * @param[out] params the network params struct reporting binded params + * @param[in] map_weights pointer to the codegened weights map array to be bound + * @param[in] map_activations pointer to the codegened activation map array to be bound + * @return true if network parameters binding succeed, false otherwise + */ +AI_INTERFACE_TYPE +ai_bool ai_platform_bind_network_params( + ai_network_params* params, + const ai_buffer_array* map_weights, const ai_buffer_array* map_activations); + +/**************************************************************************** + ** Platform Network APIs + ****************************************************************************/ +/*! + * @brief get **first** error tracked when using the network + * @ingroup ai_platform_interface + * @param network an opaque handler to the network context + * @return ai_error the FIRST error generated during network processing + */ +AI_INTERFACE_TYPE +ai_error ai_platform_network_get_error(ai_handle network); + + +/*! + * @brief Set specific error code of the network. if an error is already present + * keep it + * @ingroup ai_platform_interface + * @param net_ctx a pointer to the network context + * @param type error type as defined in @ref ai_error_type + * @param code error code as defined in @ref ai_error_code + * @return true if no previous errors where recorded, false if a previous error + * is present or context is invalid + */ +AI_INTERFACE_TYPE +ai_bool ai_platform_network_set_error( + ai_context* net_ctx, const ai_error_type type, const ai_error_code code); + +/*! + * @brief Finalize network report datastruct with I/O buffer infos + * @ingroup ai_platform_interface + * @return bool if the report has been finalized correctly. false otherwise + */ +AI_INTERFACE_TYPE +ai_bool ai_platform_api_get_network_report( + ai_handle network, ai_network_report* r); + + +/*! + * @brief Get network inputs array pointer as a ai_buffer array pointer. + * @ingroup network + * @param network an opaque handler to the network context + * @param n_buffer optional parameter to return the number of inputs + * @return a ai_buffer pointer to the inputs arrays + */ +AI_INTERFACE_TYPE +ai_buffer* ai_platform_inputs_get(ai_handle network, ai_u16 *n_buffer); + +/*! + * @brief Get network outputs array pointer as a ai_buffer array pointer. + * @ingroup network + * @param network an opaque handler to the network context + * @param n_buffer optional parameter to return the number of outputs + * @return a ai_buffer pointer to the inputs arrays + */ +AI_INTERFACE_TYPE +ai_buffer* ai_platform_outputs_get(ai_handle network, ai_u16 *n_buffer); + + +/*! + * @brief create a network context with some error check + * @ingroup ai_platform_interface + * @param a pointer to an opaque handle of the network context + * @param an (optional) pointer to the network config buffer info + * @param net_ctx a pointer to the network context structure to initialize + * @param tool_major major version id of the tool used to generate the network + * @param tool_minor minor version id of the tool used to generate the network + * @param tool_micro micro version id of the tool used to generate the network + * @return the error during network creation or error none if ok + */ +AI_INTERFACE_TYPE +ai_error ai_platform_network_create( + ai_handle* network, const ai_buffer* network_config, + ai_context* net_ctx, + const ai_u8 tool_major, const ai_u8 tool_minor, const ai_u8 tool_micro); + +/*! + * @brief destroy a network context + * @ingroup ai_platform_interface + * @param network a pointer to an opaque handle of the network context + * @return AI_HANDLE_NULL if deallocation OK, same network handle if failed + */ +AI_INTERFACE_TYPE +ai_handle ai_platform_network_destroy(ai_handle network); + +/*! + * @brief initialize the network context + * @ingroup ai_platform_interface + * @param network a pointer to an opaque handle of the network context + * @return a valid network context, NULL if initialization failed + */ +AI_INTERFACE_TYPE +ai_context* ai_platform_network_init( + ai_handle network, const ai_network_params* params); + +/*! + * @brief post-initialize of the network context. + * @ingroup ai_platform_interface + * @param network a pointer to an opaque handle of the network context + * @return a valid network context, NULL if initialization failed + */ +AI_INTERFACE_TYPE +ai_bool ai_platform_network_post_init(ai_handle network); + +/*! + * @brief main platform runtime execute of a network + * @ingroup ai_platform_interface + * @param network an opaque handler to the network context + * @param input a pointer to the input buffer data to process + * @param output a pointer to the output buffer + * @return the number of batches processed from the input. A result <=0 in case + * of error + */ +AI_INTERFACE_TYPE +ai_i32 ai_platform_network_process( + ai_handle network, const ai_buffer* input, ai_buffer* output); + + +/**************************************************************************** + ** ST.AI Wrapper APIs + ****************************************************************************/ +AI_INTERFACE_TYPE +void ai_platform_stai_handle_error( + ai_error* dst_error, + const stai_return_code code); + + +AI_INTERFACE_TYPE +ai_buffer* ai_platform_stai_bind_io( + ai_u16* n_buffer, + ai_buffer* dst_io_buffers, + const stai_ptr* src_io_buffers, + const stai_size src_io_buffers_size); + + +AI_INTERFACE_TYPE +ai_bool ai_platform_stai_update_io( + ai_i32* batch_id, + stai_ptr* dst_inputs, stai_ptr* dst_outputs, + const ai_buffer* src_inputs, const ai_buffer* src_outputs, + const ai_size n_inputs, const ai_size n_outputs); + +/**************************************************************************** + ** Observer APIs + ****************************************************************************/ + +/*! + * @brief Return the info of a requested c-node (defined by the + * c_idx field). Should be called after the initialization phase. + * @ingroup ai_platform_observer + * @param network a pointer to an opaque handle of the network context + * @param node_info a pointer to a reference of the node description + * @return true if the node_info->c_idx designates a valid index else + * false (network error is updated). + */ +AI_INTERFACE_TYPE +ai_bool ai_platform_observer_node_info( + ai_handle network, ai_observer_node *node_info); + +/*! + * @brief Register an observer context. Allows to register a client CB which + * will be called before or/and after the execution of a c-node with + * the references of the used tensors (see @ref ai_observer_node). + * @ingroup ai_platform_observer + * @param network a pointer to an opaque handle of the network context + * @param cb reference of the user callback function + * @param cookie reference of a user object/ctx + * @param flags indicate expected events (see AI_OBSERVER_XX_EVT flag definition) + * @return false if the registration has failed (network error is updated) else true + * of error. + */ +AI_INTERFACE_TYPE +ai_bool ai_platform_observer_register( + ai_handle network, + ai_observer_node_cb cb, + ai_handle cookie, + ai_u32 flags); + +AI_INTERFACE_TYPE +ai_bool ai_platform_observer_register_s(ai_handle network, + ai_observer_exec_ctx *ctx); + +/*! + * @brief un-register the observer context. + * @ingroup ai_platform_observer + * @param network a pointer to an opaque handle of the network context + * @param ctx a pointer to a reference of the registered platform observer context + * @param cb reference of the registered user callback function + * @param cookie reference of the registered user object/ctx + * @return false if the un-registration has failed (network error is updated) else true + * of error. + */ +AI_INTERFACE_TYPE +ai_bool ai_platform_observer_unregister(ai_handle network, + ai_observer_node_cb cb, ai_handle cookie); + +AI_INTERFACE_TYPE +ai_bool ai_platform_observer_unregister_s(ai_handle network, + ai_observer_exec_ctx *ctx); + +AI_API_DECLARE_END + +#endif /*AI_PLATFORM_INTERFACE_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_assert.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_assert.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_assert.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_assert.h index 6becee03..4dd9cf4c 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_assert.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_assert.h @@ -1,37 +1,37 @@ -/** - ****************************************************************************** - * @file core_assert.h - * @author AST Embedded Analytics Research Platform - * @brief header file of core assert routine - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef CORE_ASSERT_H -#define CORE_ASSERT_H - -#ifdef HAS_AI_ASSERT -// Override __FILE__ macro to disable full path asserts() -// Need to add during build also -Wbuiltin-macro-redefined options to avoid warnings -#undef __FILE__ -#define __FILE__ (__builtin_strrchr("/" __BASE_FILE__, '/') + 1) - -#include -#define CORE_ASSERT(expr) \ - assert(expr); /* CORE_ASSERT */ - -#else -#define CORE_ASSERT(expr) \ - (void)0; /* CORE_ASSERT */ - -#endif /* HAS_AI_ASSERT */ - -#endif /* CORE_ASSERT_H */ +/** + ****************************************************************************** + * @file core_assert.h + * @author AST Embedded Analytics Research Platform + * @brief header file of core assert routine + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef CORE_ASSERT_H +#define CORE_ASSERT_H + +#ifdef HAS_AI_ASSERT +// Override __FILE__ macro to disable full path asserts() +// Need to add during build also -Wbuiltin-macro-redefined options to avoid warnings +#undef __FILE__ +#define __FILE__ (__builtin_strrchr("/" __BASE_FILE__, '/') + 1) + +#include +#define CORE_ASSERT(expr) \ + assert(expr); /* CORE_ASSERT */ + +#else +#define CORE_ASSERT(expr) \ + (void)0; /* CORE_ASSERT */ + +#endif /* HAS_AI_ASSERT */ + +#endif /* CORE_ASSERT_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_common.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_common.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_common.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_common.h index 8011bd2f..3b9974c3 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_common.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_common.h @@ -1,273 +1,273 @@ -#ifndef CORE_COMMON_H -#define CORE_COMMON_H -/** - ****************************************************************************** - * @file core_common.h - * @author AST Embedded Analytics Research Platform - * @brief header file of common core datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2018 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#include "ai_platform.h" -#include "ai_platform_interface.h" -#include "core_datatypes.h" - -/*! - * @defgroup core_common Common Core Library Routines - * @brief Common macros, datatypes and routines of core common module - * @details This module contains the definitons and handling of the @ref ai_node - * datastructures. An ai_node is a generic abstraction for a network node that - * could be either a fixed function layer or an operator. Ideally the platform - * interface defined in api module should handle an process generic nodes in the - * network, not relying on the fact that they are layers or operators datastructs - * Specific implementative details should be kept inside layers and operators - * modules. The core module implements additionally common routines used in the - * layers and operators modules. - */ - -/******************************************************************************/ -#ifdef HAS_AI_ASSERT - #define ASSERT_ARRAY_SANITY(a_) \ - AI_ASSERT((a_) && (a_)->size>0) - - #define ASSERT_ARRAY_DATA_SANITY(a_) \ - ASSERT_ARRAY_SANITY(a_) \ - AI_ASSERT((a_)->data && (a_)->data_start) - - #define ASSERT_TENSOR_SANITY(t_) \ - AI_ASSERT((t_) && (t_)->data) \ - AI_ASSERT(CORE_TENSOR_GET_SHAPE_SIZE(t_)>0) \ - ASSERT_ARRAY_SANITY((t_)->data) - - #define ASSERT_TENSOR_LIST_SANITY(tlist_) \ - AI_ASSERT((tlist_) && (GET_TENSOR_LIST_SIZE(tlist_)>0)) \ - - #define ASSERT_TENSOR_DATA_SANITY(t_) \ - ASSERT_TENSOR_SANITY(t_) \ - ASSERT_ARRAY_DATA_SANITY((t_)->data) - - #define ASSERT_NODE_SANITY(node_) \ - do { \ - AI_ASSERT(AI_NODE_OBJ(node_)->tensors && AI_NODE_OBJ(node_)->tensors->chain) \ - ASSERT_TENSOR_SANITY(GET_TENSOR_IN(AI_NODE_OBJ(node_)->tensors, 0)) \ - ASSERT_TENSOR_SANITY(GET_TENSOR_OUT(AI_NODE_OBJ(node_)->tensors, 0)) \ - } while (0); -#else - #define ASSERT_ARRAY_SANITY(a_) /* ASSERT_ARRAY_SANITY */ - #define ASSERT_ARRAY_DATA_SANITY(a_) /* ASSERT_ARRAY_DATA_SANITY */ - #define ASSERT_TENSOR_SANITY(t_) /* ASSERT_TENSOR_SANITY */ - #define ASSERT_TENSOR_LIST_SANITY(tlist_) /* ASSERT_TENSOR_LIST_SANITY */ - #define ASSERT_TENSOR_DATA_SANITY(t_) /* ASSERT_TENSOR_DATA_SANITY */ - #define ASSERT_NODE_SANITY(node_) /* ASSERT_NODE_SANITY */ -#endif /*HAS_AI_ASSERT*/ - - -#if defined(__GNUC__) || defined(__clang__) - /* Suppress unused function warnings */ - #define AI_UNUSED_FUNCTION __attribute__((unused)) - /* Manage false positives in address sanitizer */ - #define AI_NO_SANITIZE_ADDRESS __attribute__((no_sanitize_address)) -#else - #define AI_UNUSED_FUNCTION /* AI_UNUSED_FUNCTION */ - #define AI_NO_SANITIZE_ADDRESS /* AI_NO_SANITIZE_ADDRESS */ -#endif - - -/******************************************************************************/ -#define AI_NODE_TYPE(type_) \ - ((ai_node_type)((ai_u32)(type_)&0xFFFF)) - -#define AI_NODE_OBJ(obj_) \ - ((ai_node*)(obj_)) - -#define AI_NODE_FUNC(func_) \ - ((node_func)(func_)) - -#define AI_NODE_COMMON_FIELDS_DECLARE \ - ai_node_type type; /*!< node type id (see @ref ai_node_type) */ \ - ai_id_obj id; /*!< node object instance id (see @ref ai_id_obj) */ \ - ai_flags flags; /*!< node object flags */ \ - ai_klass_obj klass; /*!< opaque handler to specific layer implementations */ \ - ai_network* network; /*!< handle to global network context */ \ - struct ai_node_s* next; /*!< the next node object in the sequence */ \ - node_func forward; /*!< forward function for the node */ \ - AI_CONST ai_tensor_chain* tensors; /*!< pointer to node tensor chain */ - -#define AI_NODE_STATEFUL_FIELDS_DECLARE \ - AI_NODE_COMMON_FIELDS_DECLARE \ - ai_handle state; \ - node_func init; \ - node_func update; \ - node_func destroy; - -#define AI_NODE_COMMON_INIT(type_, id_, flags_, klass_, network_, next_, forward_) \ - .type = AI_NODE_TYPE(type_), \ - .id = AI_ID_OBJ(id_), \ - .flags = (flags_), \ - .klass = AI_KLASS_OBJ(klass_), \ - .network = AI_NETWORK_OBJ(network_), \ - .next = AI_NODE_OBJ(next_), \ - .forward = AI_NODE_FUNC(forward_) - -/*****************************************************************************/ -/** Network Tensors Chains / Lists Handlers **/ -/*****************************************************************************/ -#define AI_FOR_EACH_TENSOR_CHAIN_DO(tlist_ptr_, chain_) \ - ai_tensor_list* tlist_ptr_ = (chain_)->chain; \ - for (; tlist_ptr_<(((chain_)->chain)+((chain_)->size)); tlist_ptr_++) - -#define AI_FOR_EACH_TENSOR_LIST_DO(idx_, t_ptr_, tlist_ptr_) \ - ai_tensor* t_ptr_ = NULL; \ - for (ai_size idx_ = 0; (idx_ < GET_TENSOR_LIST_SIZE(tlist_ptr_)) && \ - ((t_ptr_ = GET_TENSOR_LIST_ITEM(tlist_ptr_, idx_)) != NULL); ++idx_) - - -#define GET_TENSOR_LIST_INFO(list_) \ - ((list_)->info) - -#define GET_TENSOR_LIST_META(list_, pos_) \ - (&(GET_TENSOR_LIST_INFO(list_)->meta[pos_])) - -#define GET_TENSOR_LIST_STATE(list_, pos_) \ - (&(GET_TENSOR_LIST_INFO(list_)->state[pos_])) - -#define GET_TENSOR_LIST_BUFFER(list_, pos_) \ - (&(GET_TENSOR_LIST_INFO(list_)->buffer[pos_])) - -#define GET_TENSOR_LIST_ITEM(list_, pos_) \ - ((NULL!=GET_TENSOR_LIST_ITEMS(list_)) \ - ? GET_TENSOR_LIST_ITEMS(list_)[(pos_)] : NULL) - -#define GET_TENSOR_LIST_ITEMS(list_) \ - ((list_)->tensor) - -#define GET_TENSOR_LIST_SIZE(list_) \ - ((NULL!=(list_)) ? (list_)->size : 0) - -#define GET_TENSOR_CHAIN_SIZE(chain_) \ - ((NULL!=(chain_)) ? (chain_)->size : 0) - -#define GET_TENSOR_LIST(chain_, type_) \ - ((AI_CONCAT(AI_TENSOR_CHAIN_, type_)<(chain_)->size) \ - ? &(chain_)->chain[AI_CONCAT(AI_TENSOR_CHAIN_, type_)] : NULL) - -#define GET_TENSOR_LIST_IN(chain_) \ - (GET_TENSOR_LIST(chain_, INPUT)) - -#define GET_TENSOR_LIST_OUT(chain_) \ - (GET_TENSOR_LIST(chain_, OUTPUT)) - -#define GET_TENSOR_LIST_WEIGTHS(chain_) \ - (GET_TENSOR_LIST(chain_, WEIGHTS)) - -#define GET_TENSOR_LIST_SCRATCH(chain_) \ - (GET_TENSOR_LIST(chain_, SCRATCH)) - -#define GET_TENSOR_IN(chain_, pos_) \ - (GET_TENSOR_LIST_ITEM(GET_TENSOR_LIST_IN(chain_), (pos_))) - -#define GET_TENSOR_OUT(chain_, pos_) \ - (GET_TENSOR_LIST_ITEM(GET_TENSOR_LIST_OUT(chain_), (pos_))) - -#define GET_TENSOR_WEIGHTS(chain_, pos_) \ - (GET_TENSOR_LIST_ITEM(GET_TENSOR_LIST_WEIGTHS(chain_), (pos_))) - -#define GET_TENSOR_SCRATCH(chain_, pos_) \ - (GET_TENSOR_LIST_ITEM(GET_TENSOR_LIST_SCRATCH(chain_), (pos_))) - -/******************************************************************************/ - -AI_API_DECLARE_BEGIN - -/*! - * @struct ai_node_type - * @ingroup core_common - * @brief generic network node numeric type ID - * - */ -typedef uint16_t ai_node_type; - -/*! - * @typedef void (*node_func)(struct ai_node_s* node) - * @ingroup core_common - * @brief Callback signatures for all forward functions - */ -typedef void (*node_func)(struct ai_node_s* node); - -/*! - * @typedef ai_float (*func_nl_el)(const ai_float x) - * @ingroup core_common - * @brief Fuction pointer for generic elementwise transforms - * - * This function pointer abstracts a generic nonlinear function applied to a - * single element. See @ref ai_math_sqrt in @ref math_helpers as examples. - */ -typedef ai_float (*func_nl_el)(const ai_float x); - -/*! - * @struct ai_node - * @ingroup core_common - * @brief Structure encoding a generic node of the network - * - * The node struct includes information about the network it belong to, the - * next node in a sequential network and the forward function. The forward - * functions are implemented in the @ref layers module. - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_node_s { - AI_NODE_COMMON_FIELDS_DECLARE -} ai_node; - -/*! - * @struct ai_node_stateful - * @ingroup core_common - * @brief Structure encoding a stateful node of the network - * - * The node struct includes information about the network it belong to, the - * next node in a sequential network and the init, update and forward functions. - * The node functions are implemented in the @ref layers module. - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_node_stateful_s { - AI_NODE_STATEFUL_FIELDS_DECLARE -} ai_node_stateful; - -/*! - * @brief initialize core module - * @ingroup core_common - * @return false if initialization fails, false otherwise - */ -AI_INTERNAL_API -ai_bool core_init(void); - -/*! - * @brief get 1st error raised during processing - * @ingroup core_common - * @param[out] error the @ref ai_error recorded during processing - * @return the 1st error generated during processing. If no errors AI_ERROR_NONE - */ -AI_INTERNAL_API -ai_error core_get_error(ai_error* error); - -/*! - * @brief set error recorded during processing - * @ingroup core_common - * @param[out] error the @ref ai_error to set - * @param[in] type the specific error type to set - * @param[in] code the specific error code to set - * @return true if the error is set, false in case a precedent error was already - */ -AI_INTERNAL_API -ai_bool core_set_error( - ai_error* error, const ai_error_type type, const ai_error_code code); - -AI_API_DECLARE_END - -#endif /*CORE_COMMON_H*/ +#ifndef CORE_COMMON_H +#define CORE_COMMON_H +/** + ****************************************************************************** + * @file core_common.h + * @author AST Embedded Analytics Research Platform + * @brief header file of common core datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#include "ai_platform.h" +#include "ai_platform_interface.h" +#include "core_datatypes.h" + +/*! + * @defgroup core_common Common Core Library Routines + * @brief Common macros, datatypes and routines of core common module + * @details This module contains the definitons and handling of the @ref ai_node + * datastructures. An ai_node is a generic abstraction for a network node that + * could be either a fixed function layer or an operator. Ideally the platform + * interface defined in api module should handle an process generic nodes in the + * network, not relying on the fact that they are layers or operators datastructs + * Specific implementative details should be kept inside layers and operators + * modules. The core module implements additionally common routines used in the + * layers and operators modules. + */ + +/******************************************************************************/ +#ifdef HAS_AI_ASSERT + #define ASSERT_ARRAY_SANITY(a_) \ + AI_ASSERT((a_) && (a_)->size>0) + + #define ASSERT_ARRAY_DATA_SANITY(a_) \ + ASSERT_ARRAY_SANITY(a_) \ + AI_ASSERT((a_)->data && (a_)->data_start) + + #define ASSERT_TENSOR_SANITY(t_) \ + AI_ASSERT((t_) && (t_)->data) \ + AI_ASSERT(CORE_TENSOR_GET_SHAPE_SIZE(t_)>0) \ + ASSERT_ARRAY_SANITY((t_)->data) + + #define ASSERT_TENSOR_LIST_SANITY(tlist_) \ + AI_ASSERT((tlist_) && (GET_TENSOR_LIST_SIZE(tlist_)>0)) \ + + #define ASSERT_TENSOR_DATA_SANITY(t_) \ + ASSERT_TENSOR_SANITY(t_) \ + ASSERT_ARRAY_DATA_SANITY((t_)->data) + + #define ASSERT_NODE_SANITY(node_) \ + do { \ + AI_ASSERT(AI_NODE_OBJ(node_)->tensors && AI_NODE_OBJ(node_)->tensors->chain) \ + ASSERT_TENSOR_SANITY(GET_TENSOR_IN(AI_NODE_OBJ(node_)->tensors, 0)) \ + ASSERT_TENSOR_SANITY(GET_TENSOR_OUT(AI_NODE_OBJ(node_)->tensors, 0)) \ + } while (0); +#else + #define ASSERT_ARRAY_SANITY(a_) /* ASSERT_ARRAY_SANITY */ + #define ASSERT_ARRAY_DATA_SANITY(a_) /* ASSERT_ARRAY_DATA_SANITY */ + #define ASSERT_TENSOR_SANITY(t_) /* ASSERT_TENSOR_SANITY */ + #define ASSERT_TENSOR_LIST_SANITY(tlist_) /* ASSERT_TENSOR_LIST_SANITY */ + #define ASSERT_TENSOR_DATA_SANITY(t_) /* ASSERT_TENSOR_DATA_SANITY */ + #define ASSERT_NODE_SANITY(node_) /* ASSERT_NODE_SANITY */ +#endif /*HAS_AI_ASSERT*/ + + +#if defined(__GNUC__) || defined(__clang__) + /* Suppress unused function warnings */ + #define AI_UNUSED_FUNCTION __attribute__((unused)) + /* Manage false positives in address sanitizer */ + #define AI_NO_SANITIZE_ADDRESS __attribute__((no_sanitize_address)) +#else + #define AI_UNUSED_FUNCTION /* AI_UNUSED_FUNCTION */ + #define AI_NO_SANITIZE_ADDRESS /* AI_NO_SANITIZE_ADDRESS */ +#endif + + +/******************************************************************************/ +#define AI_NODE_TYPE(type_) \ + ((ai_node_type)((ai_u32)(type_)&0xFFFF)) + +#define AI_NODE_OBJ(obj_) \ + ((ai_node*)(obj_)) + +#define AI_NODE_FUNC(func_) \ + ((node_func)(func_)) + +#define AI_NODE_COMMON_FIELDS_DECLARE \ + ai_node_type type; /*!< node type id (see @ref ai_node_type) */ \ + ai_id_obj id; /*!< node object instance id (see @ref ai_id_obj) */ \ + ai_flags flags; /*!< node object flags */ \ + ai_klass_obj klass; /*!< opaque handler to specific layer implementations */ \ + ai_network* network; /*!< handle to global network context */ \ + struct ai_node_s* next; /*!< the next node object in the sequence */ \ + node_func forward; /*!< forward function for the node */ \ + AI_CONST ai_tensor_chain* tensors; /*!< pointer to node tensor chain */ + +#define AI_NODE_STATEFUL_FIELDS_DECLARE \ + AI_NODE_COMMON_FIELDS_DECLARE \ + ai_handle state; \ + node_func init; \ + node_func update; \ + node_func destroy; + +#define AI_NODE_COMMON_INIT(type_, id_, flags_, klass_, network_, next_, forward_) \ + .type = AI_NODE_TYPE(type_), \ + .id = AI_ID_OBJ(id_), \ + .flags = (flags_), \ + .klass = AI_KLASS_OBJ(klass_), \ + .network = AI_NETWORK_OBJ(network_), \ + .next = AI_NODE_OBJ(next_), \ + .forward = AI_NODE_FUNC(forward_) + +/*****************************************************************************/ +/** Network Tensors Chains / Lists Handlers **/ +/*****************************************************************************/ +#define AI_FOR_EACH_TENSOR_CHAIN_DO(tlist_ptr_, chain_) \ + ai_tensor_list* tlist_ptr_ = (chain_)->chain; \ + for (; tlist_ptr_<(((chain_)->chain)+((chain_)->size)); tlist_ptr_++) + +#define AI_FOR_EACH_TENSOR_LIST_DO(idx_, t_ptr_, tlist_ptr_) \ + ai_tensor* t_ptr_ = NULL; \ + for (ai_size idx_ = 0; (idx_ < GET_TENSOR_LIST_SIZE(tlist_ptr_)) && \ + ((t_ptr_ = GET_TENSOR_LIST_ITEM(tlist_ptr_, idx_)) != NULL); ++idx_) + + +#define GET_TENSOR_LIST_INFO(list_) \ + ((list_)->info) + +#define GET_TENSOR_LIST_META(list_, pos_) \ + (&(GET_TENSOR_LIST_INFO(list_)->meta[pos_])) + +#define GET_TENSOR_LIST_STATE(list_, pos_) \ + (&(GET_TENSOR_LIST_INFO(list_)->state[pos_])) + +#define GET_TENSOR_LIST_BUFFER(list_, pos_) \ + (&(GET_TENSOR_LIST_INFO(list_)->buffer[pos_])) + +#define GET_TENSOR_LIST_ITEM(list_, pos_) \ + ((NULL!=GET_TENSOR_LIST_ITEMS(list_)) \ + ? GET_TENSOR_LIST_ITEMS(list_)[(pos_)] : NULL) + +#define GET_TENSOR_LIST_ITEMS(list_) \ + ((list_)->tensor) + +#define GET_TENSOR_LIST_SIZE(list_) \ + ((NULL!=(list_)) ? (list_)->size : 0) + +#define GET_TENSOR_CHAIN_SIZE(chain_) \ + ((NULL!=(chain_)) ? (chain_)->size : 0) + +#define GET_TENSOR_LIST(chain_, type_) \ + ((AI_CONCAT(AI_TENSOR_CHAIN_, type_)<(chain_)->size) \ + ? &(chain_)->chain[AI_CONCAT(AI_TENSOR_CHAIN_, type_)] : NULL) + +#define GET_TENSOR_LIST_IN(chain_) \ + (GET_TENSOR_LIST(chain_, INPUT)) + +#define GET_TENSOR_LIST_OUT(chain_) \ + (GET_TENSOR_LIST(chain_, OUTPUT)) + +#define GET_TENSOR_LIST_WEIGTHS(chain_) \ + (GET_TENSOR_LIST(chain_, WEIGHTS)) + +#define GET_TENSOR_LIST_SCRATCH(chain_) \ + (GET_TENSOR_LIST(chain_, SCRATCH)) + +#define GET_TENSOR_IN(chain_, pos_) \ + (GET_TENSOR_LIST_ITEM(GET_TENSOR_LIST_IN(chain_), (pos_))) + +#define GET_TENSOR_OUT(chain_, pos_) \ + (GET_TENSOR_LIST_ITEM(GET_TENSOR_LIST_OUT(chain_), (pos_))) + +#define GET_TENSOR_WEIGHTS(chain_, pos_) \ + (GET_TENSOR_LIST_ITEM(GET_TENSOR_LIST_WEIGTHS(chain_), (pos_))) + +#define GET_TENSOR_SCRATCH(chain_, pos_) \ + (GET_TENSOR_LIST_ITEM(GET_TENSOR_LIST_SCRATCH(chain_), (pos_))) + +/******************************************************************************/ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_node_type + * @ingroup core_common + * @brief generic network node numeric type ID + * + */ +typedef uint16_t ai_node_type; + +/*! + * @typedef void (*node_func)(struct ai_node_s* node) + * @ingroup core_common + * @brief Callback signatures for all forward functions + */ +typedef void (*node_func)(struct ai_node_s* node); + +/*! + * @typedef ai_float (*func_nl_el)(const ai_float x) + * @ingroup core_common + * @brief Fuction pointer for generic elementwise transforms + * + * This function pointer abstracts a generic nonlinear function applied to a + * single element. See @ref ai_math_sqrt in @ref math_helpers as examples. + */ +typedef ai_float (*func_nl_el)(const ai_float x); + +/*! + * @struct ai_node + * @ingroup core_common + * @brief Structure encoding a generic node of the network + * + * The node struct includes information about the network it belong to, the + * next node in a sequential network and the forward function. The forward + * functions are implemented in the @ref layers module. + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_node_s { + AI_NODE_COMMON_FIELDS_DECLARE +} ai_node; + +/*! + * @struct ai_node_stateful + * @ingroup core_common + * @brief Structure encoding a stateful node of the network + * + * The node struct includes information about the network it belong to, the + * next node in a sequential network and the init, update and forward functions. + * The node functions are implemented in the @ref layers module. + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_node_stateful_s { + AI_NODE_STATEFUL_FIELDS_DECLARE +} ai_node_stateful; + +/*! + * @brief initialize core module + * @ingroup core_common + * @return false if initialization fails, false otherwise + */ +AI_INTERNAL_API +ai_bool core_init(void); + +/*! + * @brief get 1st error raised during processing + * @ingroup core_common + * @param[out] error the @ref ai_error recorded during processing + * @return the 1st error generated during processing. If no errors AI_ERROR_NONE + */ +AI_INTERNAL_API +ai_error core_get_error(ai_error* error); + +/*! + * @brief set error recorded during processing + * @ingroup core_common + * @param[out] error the @ref ai_error to set + * @param[in] type the specific error type to set + * @param[in] code the specific error code to set + * @return true if the error is set, false in case a precedent error was already + */ +AI_INTERNAL_API +ai_bool core_set_error( + ai_error* error, const ai_error_type type, const ai_error_code code); + +AI_API_DECLARE_END + +#endif /*CORE_COMMON_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_convert.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_convert.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_convert.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_convert.h index 4153e8fc..721549e0 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_convert.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_convert.h @@ -1,159 +1,159 @@ -/** - ****************************************************************************** - * @file core_convert.h - * @author AST Embedded Analytics Research Platform - * @brief header file of core utils routines - ****************************************************************************** - * @attention - * - * Copyright (c) 2018 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef CORE_CONVERT_H -#define CORE_CONVERT_H - -#include "ai_platform.h" -#include "ai_platform_interface.h" - -#include "core_common.h" - -AI_API_DECLARE_BEGIN - -/*! - * @defgroup core_convert Core Convert Routines - * @brief Implementation of core node format convertion routines - * (Q7 to float, ... etc.) - */ - - -/*! - * @brief Convert tensors from float to quantized or viceversa - * @ingroup core_convert - * @param[in] pNode in a handler to node (layer or operator) - */ -AI_INTERNAL_API -void node_convert(ai_node *pNode); - -/*! - * @brief Convert integer tensors between QM.N formats (8/16 bits) - * @ingroup core_convert - * @param[in] pNode in a handler to node (layer or operator) - */ -AI_INTERNAL_API -void node_convert_fixed(ai_node *pNode); - -/*! - * @brief Convert integer tensors between signed and usigned (int8/uint8) formats - * @ingroup core_convert - * @param[in] pNode in a handler to node (layer or operator) - */ -AI_INTERNAL_API -void node_convert_integer(ai_node *pNode); - -/*! - * @brief Convert float tensor to binary - * @ingroup core_convert - * @param[in] pNode in a handler to node (layer or operator) - */ -AI_INTERNAL_API -void node_convert_if32os1(ai_node *pNode); - - -/*! - * @brief Convert binary tensor to float - * @ingroup core_convert - * @param[in] pNode in a handler to node (layer or operator) - */ -AI_INTERNAL_API -void node_convert_is8os1(ai_node *pNode); - - -/*! - * @brief Convert binary tensor to signed int 8 bit - * @ingroup core_convert - * @param[in] pNode in a handler to node (layer or operator) - */ -AI_INTERNAL_API -void node_convert_is1os8(ai_node *pNode); - - -/*! - * @brief Convert binary tensor to signed int 16 bit - * @ingroup core_convert - * @param[in] pNode in a handler to node (layer or operator) - */ -AI_INTERNAL_API -void node_convert_is1os16(ai_node *pNode); - - -/*! - * @brief Convert binary tensor to float - * @ingroup core_convert - * @param[in] pNode in a handler to node (layer or operator) - */ -AI_INTERNAL_API -void node_convert_is1of32(ai_node *pNode); - - -/*! - * @brief Convert signed int 16 bit tensor to float - * @ingroup core_convert - * @param[in] pNode in a handler to node (layer or operator) - */ -AI_INTERNAL_API -void node_convert_is16of32(ai_node *pNode); - - -/*! - * @brief Convert unsigned int 16 bit tensor to float - * @ingroup core_convert - * @param[in] pNode in a handler to node (layer or operator) - */ -AI_INTERNAL_API -void node_convert_iu16of32(ai_node *pNode); - - -/*! - * @brief Convert float tensor to signed int 16 bit - * @ingroup core_convert - * @param[in] pNode in a handler to node (layer or operator) - */ -AI_INTERNAL_API -void node_convert_if32os16(ai_node *pNode); - - -/*! - * @brief Convert float tensor to unsigned int 16 bit - * @ingroup core_convert - * @param[in] pNode in a handler to node (layer or operator) - */ -AI_INTERNAL_API -void node_convert_if32ou16(ai_node *pNode); - - -/*! - * @brief Convert signed int 16 bit tensor to unsigned int 16 bit - * @ingroup core_convert - * @param[in] pNode in a handler to node (layer or operator) - */ -AI_INTERNAL_API -void node_convert_is16ou16(ai_node *pNode); - - -/*! - * @brief Convert a shape struct into a stride struct - * @ingroup core_convert - * @param[in] in a pointer to a shape to convert - * @return a condverted stride datastruct - */ -AI_INTERNAL_API -void core_shape_to_stride(ai_stride* out, const ai_shape* in); - - -#endif /*CORE_CONVERT_H*/ +/** + ****************************************************************************** + * @file core_convert.h + * @author AST Embedded Analytics Research Platform + * @brief header file of core utils routines + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef CORE_CONVERT_H +#define CORE_CONVERT_H + +#include "ai_platform.h" +#include "ai_platform_interface.h" + +#include "core_common.h" + +AI_API_DECLARE_BEGIN + +/*! + * @defgroup core_convert Core Convert Routines + * @brief Implementation of core node format convertion routines + * (Q7 to float, ... etc.) + */ + + +/*! + * @brief Convert tensors from float to quantized or viceversa + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert(ai_node *pNode); + +/*! + * @brief Convert integer tensors between QM.N formats (8/16 bits) + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_fixed(ai_node *pNode); + +/*! + * @brief Convert integer tensors between signed and usigned (int8/uint8) formats + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_integer(ai_node *pNode); + +/*! + * @brief Convert float tensor to binary + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_if32os1(ai_node *pNode); + + +/*! + * @brief Convert binary tensor to float + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_is8os1(ai_node *pNode); + + +/*! + * @brief Convert binary tensor to signed int 8 bit + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_is1os8(ai_node *pNode); + + +/*! + * @brief Convert binary tensor to signed int 16 bit + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_is1os16(ai_node *pNode); + + +/*! + * @brief Convert binary tensor to float + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_is1of32(ai_node *pNode); + + +/*! + * @brief Convert signed int 16 bit tensor to float + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_is16of32(ai_node *pNode); + + +/*! + * @brief Convert unsigned int 16 bit tensor to float + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_iu16of32(ai_node *pNode); + + +/*! + * @brief Convert float tensor to signed int 16 bit + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_if32os16(ai_node *pNode); + + +/*! + * @brief Convert float tensor to unsigned int 16 bit + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_if32ou16(ai_node *pNode); + + +/*! + * @brief Convert signed int 16 bit tensor to unsigned int 16 bit + * @ingroup core_convert + * @param[in] pNode in a handler to node (layer or operator) + */ +AI_INTERNAL_API +void node_convert_is16ou16(ai_node *pNode); + + +/*! + * @brief Convert a shape struct into a stride struct + * @ingroup core_convert + * @param[in] in a pointer to a shape to convert + * @return a condverted stride datastruct + */ +AI_INTERNAL_API +void core_shape_to_stride(ai_stride* out, const ai_shape* in); + + +#endif /*CORE_CONVERT_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_datatypes.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_datatypes.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_datatypes.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_datatypes.h index 6d20982e..64c1fe55 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_datatypes.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_datatypes.h @@ -1,62 +1,62 @@ -/** - ****************************************************************************** - * @file core_datatypes.h - * @author AST Embedded Analytics Research Platform - * @brief header file of core module private defines and datatypes - * to public nor codegen tool - ****************************************************************************** - * @attention - * - * Copyright (c) 2018 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef AI_CORE_DATATYPES_H -#define AI_CORE_DATATYPES_H - -#include - -/*! - * @defgroup Core Module Datatypes - * @brief Data structures and defines used by core module - */ - -/*! - * @brief platform runtime core library version - */ -#ifndef AI_PLATFORM_RUNTIME_MAJOR -#define AI_PLATFORM_RUNTIME_MAJOR (9) -#endif -#ifndef AI_PLATFORM_RUNTIME_MINOR -#define AI_PLATFORM_RUNTIME_MINOR (1) -#endif -#ifndef AI_PLATFORM_RUNTIME_MICRO -#define AI_PLATFORM_RUNTIME_MICRO (0) -#endif - - -#define AI_ID_OBJ(id) \ - ((ai_id_obj)(id)) - -#define AI_C_ARRAY_COUNT(array_) \ - ( sizeof(array_) / sizeof((array_)[0]) ) - -#define AI_C_ARRAY_BYTE_SIZE(array_) \ - ( sizeof(array_) ) - - -/*! - * @typedef ai_id_obj - * @ingroup core_datatypes - * @brief numeric identifier for generic object instances (e.g. layers, - * operators, etc.) It is used by codegen tool to keep tracks of specific - * instances created - */ -typedef uint16_t ai_id_obj; - -#endif /*AI_CORE_DATATYPES_H*/ +/** + ****************************************************************************** + * @file core_datatypes.h + * @author AST Embedded Analytics Research Platform + * @brief header file of core module private defines and datatypes + * to public nor codegen tool + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef AI_CORE_DATATYPES_H +#define AI_CORE_DATATYPES_H + +#include + +/*! + * @defgroup Core Module Datatypes + * @brief Data structures and defines used by core module + */ + +/*! + * @brief platform runtime core library version + */ +#ifndef AI_PLATFORM_RUNTIME_MAJOR +#define AI_PLATFORM_RUNTIME_MAJOR (9) +#endif +#ifndef AI_PLATFORM_RUNTIME_MINOR +#define AI_PLATFORM_RUNTIME_MINOR (1) +#endif +#ifndef AI_PLATFORM_RUNTIME_MICRO +#define AI_PLATFORM_RUNTIME_MICRO (0) +#endif + + +#define AI_ID_OBJ(id) \ + ((ai_id_obj)(id)) + +#define AI_C_ARRAY_COUNT(array_) \ + ( sizeof(array_) / sizeof((array_)[0]) ) + +#define AI_C_ARRAY_BYTE_SIZE(array_) \ + ( sizeof(array_) ) + + +/*! + * @typedef ai_id_obj + * @ingroup core_datatypes + * @brief numeric identifier for generic object instances (e.g. layers, + * operators, etc.) It is used by codegen tool to keep tracks of specific + * instances created + */ +typedef uint16_t ai_id_obj; + +#endif /*AI_CORE_DATATYPES_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_log.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_log.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_log.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_log.h index e4c232d2..652e68a5 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_log.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_log.h @@ -1,130 +1,130 @@ -/** - ****************************************************************************** - * @file core_log.h - * @author AST Embedded Analytics Research Platform - * @brief header file of core log interfaces - ****************************************************************************** - * @attention - * - * Copyright (c) 2018 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef CORE_LOG_H -#define CORE_LOG_H - -#include "ai_platform.h" -#include "ai_datatypes_defines.h" - -/*! - * @defgroup core_log Logger core routines wrapper interface - * @brief Common macros, datatypes and routines of ai logger module - * @details This header defines the wrapping macros interfaces to handle the - * global logger module. These macro are defined when the macro HAS_LOG is - * defined, otherwise they are all set to NOP routines and no logger code is - * compiled at all. When the macro HAS_LOG is defined, only the log messages - * having an enum id >= the value of the macro are compiled. Thus to include in - * compilation only log messages up to the error level the value of HAS_LOG must - * be equal the the enum value of LOG_ERROR macro (i.e. 3). a value of 6 means - * to include all log messages up to the lower LOG_TRACE level. - */ - -#if defined HAS_LOG && (HAS_LOG>=0) -#include "ai_log.h" - #define AI_LOG_SECTION(...) \ - { __VA_ARGS__ } - - #define AI_LOG_ACQUIRE() \ - ai_log_acquire() - #define AI_LOG_SET_LEVEL(level_) \ - AI_WRAP_FUNC(ai_log_set_level(level_);) - #define AI_LOG_SET_QUIET(onoff_) \ - AI_WRAP_FUNC(ai_log_set_quiet(onoff_);) - #define AI_LOG_SET_LOCK_FN(fn_, udata_) \ - AI_WRAP_FUNC(ai_log_set_lock(fn_, udata_);) - #define AI_LOG_CHANNEL_PUSH(level_, fn_, udata_) \ - AI_WRAP_FUNC(ai_log_channel_push(level_, fn_, udata_);) - #define AI_LOG_CHANNEL_POP(fn_, udata_) \ - AI_WRAP_FUNC(ai_log_channel_pop(fn_, udata_);) - #ifdef LOG_USE_FILE - #define AI_LOG_SET_FILE_POINTER(fp_) \ - AI_WRAP_FUNC(ai_log_set_fp(fp_);) - #else - #define AI_LOG_SET_FILE_POINTER(fp_) \ - AI_WRAP_FUNC(/*AI_LOG_SET_FILE_POINTER()*/) - #endif -#else - #define AI_LOG_SECTION(...) AI_WRAP_FUNC(/*AI_LOG_SECTION()*/) - - #define AI_LOG_ACQUIRE() (NULL) - #define AI_LOG_SET_LEVEL(level_) AI_WRAP_FUNC(/*AI_LOG_SET_LEVEL()*/) - #define AI_LOG_SET_QUIET(onoff_) AI_WRAP_FUNC(/*AI_LOG_SET_QUIET()*/) - #define AI_LOG_SET_LOCK_FN(fn_, udata_) AI_WRAP_FUNC(/*AI_LOG_SET_LOCK_FN()*/) - #define AI_LOG_CHANNEL_PUSH(level_, fn_, udata_) AI_WRAP_FUNC(/*AI_LOG_CHANNEL_PUSH()*/) - #define AI_LOG_CHANNEL_POP(fn_, udata_) AI_WRAP_FUNC(/*AI_LOG_CHANNEL_POP()*/) - #define AI_LOG_SET_FILE_POINTER(fp_) AI_WRAP_FUNC(/*AI_LOG_SET_FILE_POINTER()*/) -#endif - -#if defined HAS_LOG - #define AI_LOG_PRINT(level, fmt, ...) \ - AI_WRAP_FUNC(ai_log_print(level, fmt, ##__VA_ARGS__);) -#else - #define AI_LOG_PRINT(level, fmt, ...) \ - AI_WRAP_FUNC(/*AI_LOG_PRINT(...)*/) -#endif - -#if defined HAS_LOG && (HAS_LOG>=LOG_SUDO) - #define AI_LOG_SUDO(fmt, ...) \ - AI_WRAP_FUNC(ai_log_log(LOG_SUDO, __FILE__, __LINE__, fmt LOG_CR, ##__VA_ARGS__);) -#else - #define AI_LOG_SUDO(fmt, ...) AI_WRAP_FUNC(/*AI_LOG_SUDO()*/) -#endif - -#if defined HAS_LOG && (HAS_LOG>=LOG_TRACE) - #define AI_LOG_TRACE(fmt, ...) \ - AI_WRAP_FUNC(ai_log_log(LOG_TRACE, __FILE__, __LINE__, fmt LOG_CR, ##__VA_ARGS__);) -#else - #define AI_LOG_TRACE(fmt, ...) AI_WRAP_FUNC(/*AI_LOG_TRACE()*/) -#endif - -#if defined HAS_LOG && (HAS_LOG>=LOG_DEBUG) - #define AI_LOG_DEBUG(fmt, ...) \ - AI_WRAP_FUNC(ai_log_log(LOG_DEBUG, __FILE__, __LINE__, fmt LOG_CR, ##__VA_ARGS__);) -#else - #define AI_LOG_DEBUG(fmt, ...) AI_WRAP_FUNC(/*AI_LOG_DEBUG()*/) -#endif - -#if defined HAS_LOG && (HAS_LOG>=LOG_INFO) - #define AI_LOG_INFO(fmt, ...) \ - AI_WRAP_FUNC(ai_log_log(LOG_INFO, __FILE__, __LINE__, fmt LOG_CR, ##__VA_ARGS__);) -#else - #define AI_LOG_INFO(fmt, ...) AI_WRAP_FUNC(/*AI_LOG_INFO()*/) -#endif - -#if defined HAS_LOG && (HAS_LOG>=LOG_WARN) - #define AI_LOG_WARN(fmt, ...) \ - AI_WRAP_FUNC(ai_log_log(LOG_WARN, __FILE__, __LINE__, fmt LOG_CR, ##__VA_ARGS__);) -#else - #define AI_LOG_WARN(fmt, ...) AI_WRAP_FUNC(/*AI_LOG_WARN()*/) -#endif - -#if defined HAS_LOG && (HAS_LOG>=LOG_ERROR) - #define AI_LOG_ERROR(fmt, ...) \ - AI_WRAP_FUNC(ai_log_log(LOG_ERROR, __FILE__, __LINE__, fmt LOG_CR, ##__VA_ARGS__);) -#else - #define AI_LOG_ERROR(fmt, ...) AI_WRAP_FUNC(/*AI_LOG_ERROR()*/) -#endif - -#if defined HAS_LOG && (HAS_LOG>=LOG_FATAL) - #define AI_LOG_FATAL(fmt, ...) \ - AI_WRAP_FUNC(ai_log_log(LOG_FATAL, __FILE__, __LINE__, fmt LOG_CR, ##__VA_ARGS__);) -#else - #define AI_LOG_FATAL(fmt, ...) AI_WRAP_FUNC(/*AI_LOG_FATAL()*/) -#endif - -#endif /*CORE_LOG_H*/ +/** + ****************************************************************************** + * @file core_log.h + * @author AST Embedded Analytics Research Platform + * @brief header file of core log interfaces + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef CORE_LOG_H +#define CORE_LOG_H + +#include "ai_platform.h" +#include "ai_datatypes_defines.h" + +/*! + * @defgroup core_log Logger core routines wrapper interface + * @brief Common macros, datatypes and routines of ai logger module + * @details This header defines the wrapping macros interfaces to handle the + * global logger module. These macro are defined when the macro HAS_LOG is + * defined, otherwise they are all set to NOP routines and no logger code is + * compiled at all. When the macro HAS_LOG is defined, only the log messages + * having an enum id >= the value of the macro are compiled. Thus to include in + * compilation only log messages up to the error level the value of HAS_LOG must + * be equal the the enum value of LOG_ERROR macro (i.e. 3). a value of 6 means + * to include all log messages up to the lower LOG_TRACE level. + */ + +#if defined HAS_LOG && (HAS_LOG>=0) +#include "ai_log.h" + #define AI_LOG_SECTION(...) \ + { __VA_ARGS__ } + + #define AI_LOG_ACQUIRE() \ + ai_log_acquire() + #define AI_LOG_SET_LEVEL(level_) \ + AI_WRAP_FUNC(ai_log_set_level(level_);) + #define AI_LOG_SET_QUIET(onoff_) \ + AI_WRAP_FUNC(ai_log_set_quiet(onoff_);) + #define AI_LOG_SET_LOCK_FN(fn_, udata_) \ + AI_WRAP_FUNC(ai_log_set_lock(fn_, udata_);) + #define AI_LOG_CHANNEL_PUSH(level_, fn_, udata_) \ + AI_WRAP_FUNC(ai_log_channel_push(level_, fn_, udata_);) + #define AI_LOG_CHANNEL_POP(fn_, udata_) \ + AI_WRAP_FUNC(ai_log_channel_pop(fn_, udata_);) + #ifdef LOG_USE_FILE + #define AI_LOG_SET_FILE_POINTER(fp_) \ + AI_WRAP_FUNC(ai_log_set_fp(fp_);) + #else + #define AI_LOG_SET_FILE_POINTER(fp_) \ + AI_WRAP_FUNC(/*AI_LOG_SET_FILE_POINTER()*/) + #endif +#else + #define AI_LOG_SECTION(...) AI_WRAP_FUNC(/*AI_LOG_SECTION()*/) + + #define AI_LOG_ACQUIRE() (NULL) + #define AI_LOG_SET_LEVEL(level_) AI_WRAP_FUNC(/*AI_LOG_SET_LEVEL()*/) + #define AI_LOG_SET_QUIET(onoff_) AI_WRAP_FUNC(/*AI_LOG_SET_QUIET()*/) + #define AI_LOG_SET_LOCK_FN(fn_, udata_) AI_WRAP_FUNC(/*AI_LOG_SET_LOCK_FN()*/) + #define AI_LOG_CHANNEL_PUSH(level_, fn_, udata_) AI_WRAP_FUNC(/*AI_LOG_CHANNEL_PUSH()*/) + #define AI_LOG_CHANNEL_POP(fn_, udata_) AI_WRAP_FUNC(/*AI_LOG_CHANNEL_POP()*/) + #define AI_LOG_SET_FILE_POINTER(fp_) AI_WRAP_FUNC(/*AI_LOG_SET_FILE_POINTER()*/) +#endif + +#if defined HAS_LOG + #define AI_LOG_PRINT(level, fmt, ...) \ + AI_WRAP_FUNC(ai_log_print(level, fmt, ##__VA_ARGS__);) +#else + #define AI_LOG_PRINT(level, fmt, ...) \ + AI_WRAP_FUNC(/*AI_LOG_PRINT(...)*/) +#endif + +#if defined HAS_LOG && (HAS_LOG>=LOG_SUDO) + #define AI_LOG_SUDO(fmt, ...) \ + AI_WRAP_FUNC(ai_log_log(LOG_SUDO, __FILE__, __LINE__, fmt LOG_CR, ##__VA_ARGS__);) +#else + #define AI_LOG_SUDO(fmt, ...) AI_WRAP_FUNC(/*AI_LOG_SUDO()*/) +#endif + +#if defined HAS_LOG && (HAS_LOG>=LOG_TRACE) + #define AI_LOG_TRACE(fmt, ...) \ + AI_WRAP_FUNC(ai_log_log(LOG_TRACE, __FILE__, __LINE__, fmt LOG_CR, ##__VA_ARGS__);) +#else + #define AI_LOG_TRACE(fmt, ...) AI_WRAP_FUNC(/*AI_LOG_TRACE()*/) +#endif + +#if defined HAS_LOG && (HAS_LOG>=LOG_DEBUG) + #define AI_LOG_DEBUG(fmt, ...) \ + AI_WRAP_FUNC(ai_log_log(LOG_DEBUG, __FILE__, __LINE__, fmt LOG_CR, ##__VA_ARGS__);) +#else + #define AI_LOG_DEBUG(fmt, ...) AI_WRAP_FUNC(/*AI_LOG_DEBUG()*/) +#endif + +#if defined HAS_LOG && (HAS_LOG>=LOG_INFO) + #define AI_LOG_INFO(fmt, ...) \ + AI_WRAP_FUNC(ai_log_log(LOG_INFO, __FILE__, __LINE__, fmt LOG_CR, ##__VA_ARGS__);) +#else + #define AI_LOG_INFO(fmt, ...) AI_WRAP_FUNC(/*AI_LOG_INFO()*/) +#endif + +#if defined HAS_LOG && (HAS_LOG>=LOG_WARN) + #define AI_LOG_WARN(fmt, ...) \ + AI_WRAP_FUNC(ai_log_log(LOG_WARN, __FILE__, __LINE__, fmt LOG_CR, ##__VA_ARGS__);) +#else + #define AI_LOG_WARN(fmt, ...) AI_WRAP_FUNC(/*AI_LOG_WARN()*/) +#endif + +#if defined HAS_LOG && (HAS_LOG>=LOG_ERROR) + #define AI_LOG_ERROR(fmt, ...) \ + AI_WRAP_FUNC(ai_log_log(LOG_ERROR, __FILE__, __LINE__, fmt LOG_CR, ##__VA_ARGS__);) +#else + #define AI_LOG_ERROR(fmt, ...) AI_WRAP_FUNC(/*AI_LOG_ERROR()*/) +#endif + +#if defined HAS_LOG && (HAS_LOG>=LOG_FATAL) + #define AI_LOG_FATAL(fmt, ...) \ + AI_WRAP_FUNC(ai_log_log(LOG_FATAL, __FILE__, __LINE__, fmt LOG_CR, ##__VA_ARGS__);) +#else + #define AI_LOG_FATAL(fmt, ...) AI_WRAP_FUNC(/*AI_LOG_FATAL()*/) +#endif + +#endif /*CORE_LOG_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_net_inspect.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_net_inspect.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_net_inspect.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_net_inspect.h index 721d38a9..c9c210a4 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_net_inspect.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_net_inspect.h @@ -1,92 +1,92 @@ -/** - ****************************************************************************** - * @file core_net_inspect.h - * @author AST Embedded Analytics Research Platform - * @brief header file of core network inspection APIs - ****************************************************************************** - * @attention - * - * Copyright (c) 2018 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef CORE_NET_INSPECT_H -#define CORE_NET_INSPECT_H - -#include "core_net_inspect_interface.h" - -#include "core_common.h" -#include "layers_common.h" - -/*! - * @defgroup core_net_inspect Core Network Inspection routines - * @brief Implementation of core network inspection routines that allows to - * inspect on a node basis a generated network model - * @details A network context @ref ai_network basically contains a chained list - * of nodes @ref ai_node that have an associated forward function. - * Each ai)network context and ai_node datastructs have as a required member - * field an opaque handler (i.e. a void pointer) to a klass object. - * This handler is intended to be used as a platform specific node context - * that implements specific target platform routines. - * The inspector module basically acts as a plugin that exploiting these features - * by temporary creating an hidden inspection context (see - * @ref ai_core_inspect_net_klass) associated to the network and - * linking it by re-routing the klass field to this inspection context. The - * inspection context saves as part of its state (by a stack push operation), the - * internal state of the network (all node / network klass pointers and actual - * forward functions). - * Thus, for each node it re-routes all node's forward functions to a dedicated - * inspection forward function (see @ref _forward_inspect_validate() routine) - * This routine is the core of the mechanism and it allows to inspect a network - * node by node. Some additional inspection could thus be done inside the - * _forward_inspect_validate() routine before and after the actual node - * forward function is called; - * - */ - -AI_API_DECLARE_BEGIN - -/*! - * @defgroup core_net_inspect Network Inspection Core - * @brief Implementation of the validation network routines - */ - -/*! - * @brief Initialize the network inspection context on a given network - * @ingroup core net inspect - * @param network opaque handler to the network instance - * @param cfg a pointer to the inspector configuration we want to use - * @return true if execution of the API is fine, false otherwise - */ -AI_API_ENTRY -ai_bool ai_network_inspect_init( - ai_handle network, const ai_inspect_config* cfg); - -/*! - * @brief Get a summary report from the inspected network - * @ingroup core net inspect - * @param network opaque handler to the network instance - * @param report a pointer to the report provided back by the inspection - * @return true if execution of the API is fine, false otherwise - */ -AI_API_ENTRY -ai_bool ai_network_inspect_get_report( - ai_handle network, ai_inspect_net_report* report); - -/*! - * @brief Destroy the network inspection context on a given network - * @ingroup core net inspect - * @param network opaque handler to the network instance - * @return true if execution of the API is fine, false otherwise - */ -AI_API_ENTRY -ai_bool ai_network_inspect_destroy(ai_handle network); - -AI_API_DECLARE_END - -#endif /* CORE_NET_INSPECT_H */ +/** + ****************************************************************************** + * @file core_net_inspect.h + * @author AST Embedded Analytics Research Platform + * @brief header file of core network inspection APIs + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef CORE_NET_INSPECT_H +#define CORE_NET_INSPECT_H + +#include "core_net_inspect_interface.h" + +#include "core_common.h" +#include "layers_common.h" + +/*! + * @defgroup core_net_inspect Core Network Inspection routines + * @brief Implementation of core network inspection routines that allows to + * inspect on a node basis a generated network model + * @details A network context @ref ai_network basically contains a chained list + * of nodes @ref ai_node that have an associated forward function. + * Each ai)network context and ai_node datastructs have as a required member + * field an opaque handler (i.e. a void pointer) to a klass object. + * This handler is intended to be used as a platform specific node context + * that implements specific target platform routines. + * The inspector module basically acts as a plugin that exploiting these features + * by temporary creating an hidden inspection context (see + * @ref ai_core_inspect_net_klass) associated to the network and + * linking it by re-routing the klass field to this inspection context. The + * inspection context saves as part of its state (by a stack push operation), the + * internal state of the network (all node / network klass pointers and actual + * forward functions). + * Thus, for each node it re-routes all node's forward functions to a dedicated + * inspection forward function (see @ref _forward_inspect_validate() routine) + * This routine is the core of the mechanism and it allows to inspect a network + * node by node. Some additional inspection could thus be done inside the + * _forward_inspect_validate() routine before and after the actual node + * forward function is called; + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @defgroup core_net_inspect Network Inspection Core + * @brief Implementation of the validation network routines + */ + +/*! + * @brief Initialize the network inspection context on a given network + * @ingroup core net inspect + * @param network opaque handler to the network instance + * @param cfg a pointer to the inspector configuration we want to use + * @return true if execution of the API is fine, false otherwise + */ +AI_API_ENTRY +ai_bool ai_network_inspect_init( + ai_handle network, const ai_inspect_config* cfg); + +/*! + * @brief Get a summary report from the inspected network + * @ingroup core net inspect + * @param network opaque handler to the network instance + * @param report a pointer to the report provided back by the inspection + * @return true if execution of the API is fine, false otherwise + */ +AI_API_ENTRY +ai_bool ai_network_inspect_get_report( + ai_handle network, ai_inspect_net_report* report); + +/*! + * @brief Destroy the network inspection context on a given network + * @ingroup core net inspect + * @param network opaque handler to the network instance + * @return true if execution of the API is fine, false otherwise + */ +AI_API_ENTRY +ai_bool ai_network_inspect_destroy(ai_handle network); + +AI_API_DECLARE_END + +#endif /* CORE_NET_INSPECT_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_net_inspect_interface.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_net_inspect_interface.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_net_inspect_interface.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_net_inspect_interface.h index e4be3351..c5bbbb9c 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_net_inspect_interface.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_net_inspect_interface.h @@ -1,117 +1,117 @@ -/** - ****************************************************************************** - * @file core_net_inspect_interface.h - * @author AST Embedded Analytics Research Platform - * @brief header file of core network inspection interface APIs - ****************************************************************************** - * @attention - * - * Copyright (c) 2018 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef CORE_NET_INSPECT_INTERFACE_H -#define CORE_NET_INSPECT_INTERFACE_H - -#include "ai_platform.h" - -AI_API_DECLARE_BEGIN - -/*! - * @defgroup core_validation Validation Core - * @brief Implementation of the validation network interface headers - */ - - -/*! - * @struct ai_inspect_node_info - * @brief network node inspection context: there is one of this datastruct - * for each node of the network - */ -typedef struct ai_inspect_node_info_s { - ai_u16 type; /*!< node type info @see ai_node datastruct */ - ai_u16 id; /*!< node id assigned by codegen tool to identify - the specific node instance */ - ai_u16 batch_id; /*!< current node batch processed */ - ai_u16 n_batches; /*!< total number of node batches to process */ - ai_float elapsed_ms; /*!< node performance analysys: time in - milliseconds to execute the node forward - function */ - ai_u16 in_size; /*!< number of node's input activation buffers */ - ai_u16 out_size; /*!< number of node's output activation buffers */ - ai_buffer* in; /*!< input node activation buffer see @ref ai_buffer */ - ai_buffer* out; /*!< output node activation buffer see @ref ai_buffer */ -} ai_inspect_node_info; - -/*! - * @struct ai_inspect_net_report - * @brief network inspection report context - */ -typedef struct ai_inspect_net_report_s { - ai_u32 id; /*!< id of the report */ - ai_signature signature; /*!< network identification checksum */ - ai_u32 num_inferences; /*!< total number of inferences processed - during the inspection */ - ai_u32 n_nodes; /*!< number of nodes in the network */ - ai_float elapsed_ms; /*!< network total time (in ms) for processing - num_inferences inferences */ - ai_inspect_node_info* node; /*!< pointer to the array of size n_nodes where - a single node report is reported. see @ref - ai_inspect_node_info datastruct */ -} ai_inspect_net_report; - -/*! - * @enum net inspector inspection mode - * @brief configuration flags to set net inspection mode - */ -typedef enum { - VALIDATION_INSPECT = (0x1<<0), /**< Network validation inspection mode */ - STORE_ALL_IO_ACTIVATIONS = (0x1<<7), /**< Store all I/O activations on snapshot datastruct */ -} ai_inspect_mode; - -typedef enum { - AI_NODE_EXEC_PRE_FORWARD_STAGE = 0x0, - AI_NODE_EXEC_POST_FORWARD_STAGE = 0x1, -} ai_node_exec_stage; - -/*! - * @brief function pointer to callback report - */ -typedef void (*ai_inspect_report_cb_func)( - const ai_handle cookie, - const ai_inspect_net_report* report); - -/*! - * @brief function pointer to node execute - */ -typedef void (*ai_inspect_exec_node_cb_func)( - const ai_handle cookie, - const ai_inspect_node_info* node_info, - const ai_node_exec_stage stage); - -/*! - * @struct ai_inspect_config - * @brief inspection config datastruct - */ -typedef struct ai_inspect_config_s { - ai_u8 validation_mode; /*!< validation mode flags - see @ref ai_inspect_mode */ - ai_u8 log_level; /*!< log class level see @ref LOG_SUDO */ - ai_bool log_quiet; /*!< log class quiet mode */ - ai_inspect_report_cb_func on_report_destroy; /*!< callback function - called when a report datastruct - is released from memory */ - ai_inspect_exec_node_cb_func on_exec_node; /*!< callback function - called when a node is executed (pre & post) */ - ai_handle cookie; -} ai_inspect_config; - - -AI_API_DECLARE_END - -#endif /* CORE_NET_INSPECT_INTERFACE_H */ +/** + ****************************************************************************** + * @file core_net_inspect_interface.h + * @author AST Embedded Analytics Research Platform + * @brief header file of core network inspection interface APIs + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef CORE_NET_INSPECT_INTERFACE_H +#define CORE_NET_INSPECT_INTERFACE_H + +#include "ai_platform.h" + +AI_API_DECLARE_BEGIN + +/*! + * @defgroup core_validation Validation Core + * @brief Implementation of the validation network interface headers + */ + + +/*! + * @struct ai_inspect_node_info + * @brief network node inspection context: there is one of this datastruct + * for each node of the network + */ +typedef struct ai_inspect_node_info_s { + ai_u16 type; /*!< node type info @see ai_node datastruct */ + ai_u16 id; /*!< node id assigned by codegen tool to identify + the specific node instance */ + ai_u16 batch_id; /*!< current node batch processed */ + ai_u16 n_batches; /*!< total number of node batches to process */ + ai_float elapsed_ms; /*!< node performance analysys: time in + milliseconds to execute the node forward + function */ + ai_u16 in_size; /*!< number of node's input activation buffers */ + ai_u16 out_size; /*!< number of node's output activation buffers */ + ai_buffer* in; /*!< input node activation buffer see @ref ai_buffer */ + ai_buffer* out; /*!< output node activation buffer see @ref ai_buffer */ +} ai_inspect_node_info; + +/*! + * @struct ai_inspect_net_report + * @brief network inspection report context + */ +typedef struct ai_inspect_net_report_s { + ai_u32 id; /*!< id of the report */ + ai_signature signature; /*!< network identification checksum */ + ai_u32 num_inferences; /*!< total number of inferences processed + during the inspection */ + ai_u32 n_nodes; /*!< number of nodes in the network */ + ai_float elapsed_ms; /*!< network total time (in ms) for processing + num_inferences inferences */ + ai_inspect_node_info* node; /*!< pointer to the array of size n_nodes where + a single node report is reported. see @ref + ai_inspect_node_info datastruct */ +} ai_inspect_net_report; + +/*! + * @enum net inspector inspection mode + * @brief configuration flags to set net inspection mode + */ +typedef enum { + VALIDATION_INSPECT = (0x1<<0), /**< Network validation inspection mode */ + STORE_ALL_IO_ACTIVATIONS = (0x1<<7), /**< Store all I/O activations on snapshot datastruct */ +} ai_inspect_mode; + +typedef enum { + AI_NODE_EXEC_PRE_FORWARD_STAGE = 0x0, + AI_NODE_EXEC_POST_FORWARD_STAGE = 0x1, +} ai_node_exec_stage; + +/*! + * @brief function pointer to callback report + */ +typedef void (*ai_inspect_report_cb_func)( + const ai_handle cookie, + const ai_inspect_net_report* report); + +/*! + * @brief function pointer to node execute + */ +typedef void (*ai_inspect_exec_node_cb_func)( + const ai_handle cookie, + const ai_inspect_node_info* node_info, + const ai_node_exec_stage stage); + +/*! + * @struct ai_inspect_config + * @brief inspection config datastruct + */ +typedef struct ai_inspect_config_s { + ai_u8 validation_mode; /*!< validation mode flags + see @ref ai_inspect_mode */ + ai_u8 log_level; /*!< log class level see @ref LOG_SUDO */ + ai_bool log_quiet; /*!< log class quiet mode */ + ai_inspect_report_cb_func on_report_destroy; /*!< callback function + called when a report datastruct + is released from memory */ + ai_inspect_exec_node_cb_func on_exec_node; /*!< callback function + called when a node is executed (pre & post) */ + ai_handle cookie; +} ai_inspect_config; + + +AI_API_DECLARE_END + +#endif /* CORE_NET_INSPECT_INTERFACE_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_private.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_private.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_private.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_private.h index 57f8205b..1a3637ec 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/core_private.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/core_private.h @@ -1,364 +1,364 @@ -/** - ****************************************************************************** - * @file core_private.h - * @author AST Embedded Analytics Research Platform - * @brief private header file of common private core module defines - ****************************************************************************** - * @attention - * - * Copyright (c) 2019 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef CORE_PRIVATE_H -#define CORE_PRIVATE_H - -#include "ai_datatypes_format.h" -#include "ai_datatypes_internal.h" -#include "ai_math_helpers.h" - -#include "core_log.h" - -/*! - * @defgroup core_private Core Library Private macros and datatypes - * @brief Common macros, datatypes and routines for core private rounites - * @details This module contains the definitons and implementations of some - * internal routines and datatypes that are supposed to not be exposed as - * public headers. So usually this file should be include only on .c files or - * headers that are private as well - */ - -/*** Foreground Colors ****************************************************/ -#define CORE_COLOR_BLACK "\x1b[30m" -#define CORE_COLOR_RED "\x1b[31m" -#define CORE_COLOR_GREEN "\x1b[32m" -#define CORE_COLOR_YELLOW "\x1b[33m" -#define CORE_COLOR_BLUE "\x1b[94m" -#define CORE_COLOR_MAGENTA "\x1b[35m" -#define CORE_COLOR_CYAN "\x1b[36m" -#define CORE_COLOR_WHYTE "\x1b[37m" -#define CORE_COLOR_DEFAULT "\x1b[39m" -#define CORE_COLOR_LGRAY "\x1b[90m" -#define CORE_COLOR_LRED "\x1b[91m" -#define CORE_COLOR_LGREEN "\x1b[92m" -#define CORE_COLOR_LYELLOW "\x1b[93m" -#define CORE_COLOR_LBLUE "\x1b[94m" -#define CORE_COLOR_LMAGENTA "\x1b[95m" -#define CORE_COLOR_LCYAN "\x1b[96m" -#define CORE_COLOR_LWHITE "\x1b[97m" - -/*** Text Attributes Colors *********************************************/ -#define CORE_COLOR_OFF "\x1b[0m" -#define CORE_COLOR_BOLD "\x1b[1m" -#define CORE_COLOR_UNDERLINE "\x1b[4m" -#define CORE_COLOR_BLINK "\x1b[5m" -#define CORE_COLOR_BOLD_OFF "\x1b[21m" -#define CORE_COLOR_UNDERLINE_OFF "\x1b[24m" -#define CORE_COLOR_BLINK_OFF "\x1b[25m" - -/*** Background Colors ****************************************************/ -#define CORE_COLOR_BG_BLACK "\x1b[40m" -#define CORE_COLOR_BG_RED "\x1b[41m" -#define CORE_COLOR_BG_GREEN "\x1b[42m" -#define CORE_COLOR_BG_YELLOW "\x1b[43m" -#define CORE_COLOR_BG_BLUE "\x1b[44m" -#define CORE_COLOR_BG_MAGENTA "\x1b[45m" -#define CORE_COLOR_BG_CYAN "\x1b[46m" -#define CORE_COLOR_BG_WHITE "\x1b[47m" -#define CORE_COLOR_BG_DEFAULT "\x1b[49m" -#define CORE_COLOR_BG_LGRAY "\x1b[100m" -#define CORE_COLOR_BG_LRED "\x1b[101m" -#define CORE_COLOR_BG_LGREEN "\x1b[102m" -#define CORE_COLOR_BG_LYELLOW "\x1b[103m" -#define CORE_COLOR_BG_LBLUE "\x1b[104m" -#define CORE_COLOR_BG_LMAGENTA "\x1b[105m" -#define CORE_COLOR_BG_LCYAN "\x1b[106m" -#define CORE_COLOR_BG_LWHITE "\x1b[107m" - - -/*****************************************************************************/ -#define CORE_ADDRESS_RANGE_INIT(start_, end_) \ - core_address_range_init(start_, end_) - -#define CORE_GET_BUFFER_META_INFO(meta_info_, tensor_ptr_) \ - core_get_buffer_meta_info(meta_info_, tensor_ptr_) - -#define CORE_ADDRESS_RANGE_END(range_) \ - ( (ai_ptr)(((range_)->start)+((range_)->size)) ) - -#define CORE_ADDRESS_RANGE_OVERLAP(overlap_) \ - ( ((overlap_)->start) && (((overlap_)->size)>0) ) - -#define CORE_ADDRESS_RANGE_OVERLAP_PARTIAL(overlap_, ref_) \ - ( ((overlap_)->start) && (((overlap_)->size)<((ref_)->size)) ) - -#define CORE_MEMORY_OVERLAP_INIT(partial_, range_, chain_id_, tensor_id_) { \ - .partial = (partial_), .range = AI_PACK(range_), \ - .chain_id = (chain_id_), .tensor_id = (tensor_id_) \ -} - -#define CORE_OFFSET(offset_, max_) \ - ((ai_i32)(((offset_)<0) ? AI_MAX((max_) - (offset_), 0) : AI_MIN(offset_, max_))) - -/*****************************************************************************/ -/** Network Context Handlers **/ -/*****************************************************************************/ - -/*****************************************************************************/ -/** Network Tensors Handlers **/ -/*****************************************************************************/ -#define AI_TENSOR_HAS_INTQ_INFO \ - AI_BUFFER_META_HAS_INTQ_INFO - -#define CORE_TENSOR_GET_SHAPE_SIZE(tensor_) \ - ai_shape_get_size(AI_TENSOR_SHAPE(tensor_)) - - -#define CORE_ASSERT_SHAPE_MATCH(x, y) \ -do { \ - AI_ASSERT(AI_SHAPE_H(y) == 1 || AI_SHAPE_H(x)==1 || AI_SHAPE_H(y)==AI_SHAPE_H(x)) \ - AI_ASSERT(AI_SHAPE_W(y) == 1 || AI_SHAPE_W(x)==1 || AI_SHAPE_W(y)==AI_SHAPE_W(x)) \ - AI_ASSERT(AI_SHAPE_D(y) == 1 || AI_SHAPE_D(x)==1 || AI_SHAPE_D(y)==AI_SHAPE_D(x)) \ - AI_ASSERT(AI_SHAPE_E(y) == 1 || AI_SHAPE_E(x)==1 || AI_SHAPE_E(y)==AI_SHAPE_E(x)) \ - AI_ASSERT(AI_SHAPE_CH(y) == 1 || AI_SHAPE_CH(x)==1|| AI_SHAPE_CH(y)==AI_SHAPE_CH(x)) \ - AI_ASSERT(AI_SHAPE_IN_CH(y) == 1 || AI_SHAPE_IN_CH(x)==1|| AI_SHAPE_IN_CH(y)==AI_SHAPE_IN_CH(x)) \ -} while(0); - - -#define AI_TENSOR_ARRAY_BYTE_SIZE(t_) \ - AI_ARRAY_OBJ_BYTE_SIZE(AI_ARRAY_OBJ(t_->data)) - -#define AI_TENSOR_ARRAY_GET_DATA_ADDR(t_) \ - AI_HANDLE_PTR(AI_ARRAY_OBJ_DATA_START(t_->data, void)) - -#define AI_TENSOR_ARRAY_UPDATE_DATA_ADDR(t_, addr_) \ - { ai_array *arr_ = AI_ARRAY_OBJ(t_->data); \ - const uintptr_t off_ = (uintptr_t)arr_->data - (uintptr_t)arr_->data_start; \ - arr_->data_start = AI_PTR(addr_); \ - arr_->data = AI_PTR((uintptr_t)addr_ + off_); \ - } - -#define AI_TENSOR_INTEGER_GET_SIZE(t_) \ - ((t_->klass) ? (AI_KLASS_GET_INTQ_INFO_LIST(t_))->size : 0) - -#define AI_TENSOR_INTEGER_GET_SCALE(t_, idx_) \ - AI_INTQ_INFO_LIST_SCALE(AI_KLASS_GET_INTQ_INFO_LIST(t_), ai_float, idx_) - -#define AI_TENSOR_INTEGER_GET_ZEROPOINT_I8(t_, idx_) \ - AI_INTQ_INFO_LIST_ZEROPOINT(AI_KLASS_GET_INTQ_INFO_LIST(t_), ai_i8, idx_) - -#define AI_TENSOR_INTEGER_GET_ZEROPOINT_U8(t_, idx_) \ - AI_INTQ_INFO_LIST_ZEROPOINT(AI_KLASS_GET_INTQ_INFO_LIST(t_), ai_u8, idx_) - -#define AI_TENSOR_FMT_GET_SIGN(t_) \ - AI_BUFFER_FMT_GET_SIGN(AI_ARRAY_OBJ(t_->data)->format) - -#define AI_TENSOR_FMT_GET_BITS(t_) \ - AI_BUFFER_FMT_GET_BITS(AI_ARRAY_OBJ(t_->data)->format) - -#define AI_TENSOR_FMT_GET_FBITS(t_) \ - AI_BUFFER_FMT_GET_FBITS(AI_ARRAY_OBJ(t_->data)->format) - -#define AI_TENSOR_FMT_GET_TYPE(t_) \ - AI_BUFFER_FMT_GET_TYPE(AI_ARRAY_OBJ(t_->data)->format) - -#define AI_TENSOR_GET_FMT(t_) \ - AI_FMT_OBJ(AI_ARRAY_OBJ(t_->data)->format) - - -/*****************************************************************************/ -/** Network Buffers Handlers **/ -/*****************************************************************************/ -#define AI_FOR_EACH_BUFFER_ARRAY_ITEM(buffer_ptr_, buffer_array_ptr_, start_pos_, end_pos_) \ - ai_buffer* buffer_ptr_ = AI_BUFFER_ARRAY_ITEM(buffer_array_ptr_, \ - CORE_OFFSET(end_pos_, AI_BUFFER_ARRAY_SIZE(buffer_array_ptr_))); \ - for ( ; buffer_ptr_ && AI_BUFFER_ARRAY_SIZE(buffer_array_ptr_) && \ - (buffer_ptr_>=AI_BUFFER_ARRAY_ITEM(buffer_array_ptr_, \ - CORE_OFFSET(start_pos_, AI_BUFFER_ARRAY_SIZE(buffer_array_ptr_)))); buffer_ptr_--) - -/*****************************************************************************/ -/** Network Arrays Handlers **/ -/*****************************************************************************/ -#define AI_ARRAY_OBJ_FMT(array_) \ - AI_FMT_OBJ(AI_ARRAY_OBJ(array_)->format) - -#define AI_ARRAY_OBJ_FMT_GET(array_) \ - AI_FMT_GET(AI_FMT_OBJ(AI_ARRAY_OBJ(array_)->format)) - -#define AI_ARRAY_OBJ_SIZE(array_) \ - (AI_ARRAY_OBJ(array_)->size) - -#define AI_ARRAY_OBJ_BYTE_SIZE(array_) \ - AI_SIZE(AI_ARRAY_GET_BYTE_SIZE(AI_ARRAY_OBJ_FMT(array_), \ - AI_ARRAY_OBJ_SIZE(array_))) - -#define AI_ARRAY_OBJ_DATA_SIZE(array_) \ - AI_ARRAY_GET_DATA_BYTE_SIZE(AI_ARRAY_OBJ_FMT(array_), \ - AI_ARRAY_OBJ_SIZE(array_)) - -#define AI_ARRAY_OBJ_DATA(array_, type_) \ - AI_CAST(type_*, AI_ARRAY_OBJ(array_)->data) - -#define AI_ARRAY_OBJ_DATA_START(array_, type_) \ - AI_CAST(type_*, AI_ARRAY_OBJ(array_)->data_start) - -#define AI_ARRAY_OBJ_ELEM(array_, type_, pos_) \ - AI_ARRAY_OBJ_DATA(array_, type_)[(pos_)] - - -/*****************************************************************************/ -/** Network Tensors Chains / Lists Handlers **/ -/*****************************************************************************/ -#define SET_TENSOR_IN(chain_, pos_) \ - (GET_TENSOR_LIST_IN(chain_)->tensor[(pos_)]) - -#define SET_TENSOR_OUT(chain_, pos_) \ - (GET_TENSOR_LIST_OUT(chain_)->tensor[(pos_)]) - -#define AI_NODE_IO_GET(node_, in_, out_) \ - ASSERT_NODE_SANITY(node_) \ - ai_tensor* in_ = GET_TENSOR_IN((node_)->tensors, 0); \ - ai_tensor* out_ = GET_TENSOR_OUT((node_)->tensors, 0); \ - ASSERT_TENSOR_SANITY(in_) \ - ASSERT_TENSOR_SANITY(out_) - - -/*****************************************************************************/ -#define AI_BITS_TO_BYTES(bits_) \ - (((bits_)+0x7) >> 3) - -#define AI_BYTES_TO_BITS(bytes_) \ - ((bytes_) << 3) - - -/*****************************************************************************/ -/** Network Nodes Handlers **/ -/*****************************************************************************/ -#define AI_NODE_IS_FIRST(node) \ - (AI_NODE_OBJ(node)==AI_NODE_OBJ(AI_NODE_OBJ(node)->network->input_node)) - -#define AI_NODE_IS_LAST(node_) \ - ((AI_NODE_OBJ(node_)==AI_NODE_OBJ(node_)->next) || \ - (AI_NODE_OBJ(node_)->next==NULL)) - -#define AI_FOR_EACH_NODE_DO(node_, nodes_) \ - for (ai_node* node_ = AI_NODE_OBJ(nodes_); (node_); \ - node_ = ((AI_NODE_IS_LAST(node_)) ? NULL : (node_)->next)) - -/*****************************************************************************/ -typedef struct { - ai_ptr start; - ai_size size; -} ai_address_range; - -typedef struct { - ai_address_range range; - ai_u16 chain_id; - ai_u16 tensor_id; - ai_bool partial; -} ai_memory_overlap; - -/*****************************************************************************/ -AI_DECLARE_STATIC -ai_address_range core_address_range_init( - const ai_handle start, const ai_handle end) -{ - ai_address_range r; - - r.start = (startdata) - ai_bool ok; - - meta->flags = 0x0; - meta->intq_info = AI_KLASS_GET_INTQ_INFO_LIST(t); - ok = (meta->intq_info && (meta->intq_info->size>0)); - meta->flags |= (ok) ? AI_BUFFER_META_HAS_INTQ_INFO : 0x0; - return (ok) ? meta : NULL; -} - - -#if 0 -#include -#include - -AI_DECLARE_STATIC -void _dump_file_print( - const char* fname, const char* fmt, ...) -{ - static FILE* fp = NULL; - if (fname) { - if (!fp) { - fp = fopen(fname, "a"); - } - } - - if (fp) { - va_list args; - va_start(args, fmt); - vfprintf(fp, fmt, args); - va_end(args); - fflush(fp); - } -} - - -AI_DECLARE_STATIC -void _dump_bytearray( - const char* fname, - const ai_handle src, const ai_size src_size, const ai_u8 src_id, - const char* name) -{ - static FILE* fp = NULL; - if (fname && src && (src_size>0)) { - if (!fp) { - fp = fopen(fname, "a"); - } - } - - if (fp) { - switch (src_id) { - case 1: - { - const ai_float* src_value = (const ai_float*)src; - fprintf(fp, "ai_float %s[%u] = {%f", name, src_size, src_value[0]); - for (ai_size i=1; istart)+((range_)->size)) ) + +#define CORE_ADDRESS_RANGE_OVERLAP(overlap_) \ + ( ((overlap_)->start) && (((overlap_)->size)>0) ) + +#define CORE_ADDRESS_RANGE_OVERLAP_PARTIAL(overlap_, ref_) \ + ( ((overlap_)->start) && (((overlap_)->size)<((ref_)->size)) ) + +#define CORE_MEMORY_OVERLAP_INIT(partial_, range_, chain_id_, tensor_id_) { \ + .partial = (partial_), .range = AI_PACK(range_), \ + .chain_id = (chain_id_), .tensor_id = (tensor_id_) \ +} + +#define CORE_OFFSET(offset_, max_) \ + ((ai_i32)(((offset_)<0) ? AI_MAX((max_) - (offset_), 0) : AI_MIN(offset_, max_))) + +/*****************************************************************************/ +/** Network Context Handlers **/ +/*****************************************************************************/ + +/*****************************************************************************/ +/** Network Tensors Handlers **/ +/*****************************************************************************/ +#define AI_TENSOR_HAS_INTQ_INFO \ + AI_BUFFER_META_HAS_INTQ_INFO + +#define CORE_TENSOR_GET_SHAPE_SIZE(tensor_) \ + ai_shape_get_size(AI_TENSOR_SHAPE(tensor_)) + + +#define CORE_ASSERT_SHAPE_MATCH(x, y) \ +do { \ + AI_ASSERT(AI_SHAPE_H(y) == 1 || AI_SHAPE_H(x)==1 || AI_SHAPE_H(y)==AI_SHAPE_H(x)) \ + AI_ASSERT(AI_SHAPE_W(y) == 1 || AI_SHAPE_W(x)==1 || AI_SHAPE_W(y)==AI_SHAPE_W(x)) \ + AI_ASSERT(AI_SHAPE_D(y) == 1 || AI_SHAPE_D(x)==1 || AI_SHAPE_D(y)==AI_SHAPE_D(x)) \ + AI_ASSERT(AI_SHAPE_E(y) == 1 || AI_SHAPE_E(x)==1 || AI_SHAPE_E(y)==AI_SHAPE_E(x)) \ + AI_ASSERT(AI_SHAPE_CH(y) == 1 || AI_SHAPE_CH(x)==1|| AI_SHAPE_CH(y)==AI_SHAPE_CH(x)) \ + AI_ASSERT(AI_SHAPE_IN_CH(y) == 1 || AI_SHAPE_IN_CH(x)==1|| AI_SHAPE_IN_CH(y)==AI_SHAPE_IN_CH(x)) \ +} while(0); + + +#define AI_TENSOR_ARRAY_BYTE_SIZE(t_) \ + AI_ARRAY_OBJ_BYTE_SIZE(AI_ARRAY_OBJ(t_->data)) + +#define AI_TENSOR_ARRAY_GET_DATA_ADDR(t_) \ + AI_HANDLE_PTR(AI_ARRAY_OBJ_DATA_START(t_->data, void)) + +#define AI_TENSOR_ARRAY_UPDATE_DATA_ADDR(t_, addr_) \ + { ai_array *arr_ = AI_ARRAY_OBJ(t_->data); \ + const uintptr_t off_ = (uintptr_t)arr_->data - (uintptr_t)arr_->data_start; \ + arr_->data_start = AI_PTR(addr_); \ + arr_->data = AI_PTR((uintptr_t)addr_ + off_); \ + } + +#define AI_TENSOR_INTEGER_GET_SIZE(t_) \ + ((t_->klass) ? (AI_KLASS_GET_INTQ_INFO_LIST(t_))->size : 0) + +#define AI_TENSOR_INTEGER_GET_SCALE(t_, idx_) \ + AI_INTQ_INFO_LIST_SCALE(AI_KLASS_GET_INTQ_INFO_LIST(t_), ai_float, idx_) + +#define AI_TENSOR_INTEGER_GET_ZEROPOINT_I8(t_, idx_) \ + AI_INTQ_INFO_LIST_ZEROPOINT(AI_KLASS_GET_INTQ_INFO_LIST(t_), ai_i8, idx_) + +#define AI_TENSOR_INTEGER_GET_ZEROPOINT_U8(t_, idx_) \ + AI_INTQ_INFO_LIST_ZEROPOINT(AI_KLASS_GET_INTQ_INFO_LIST(t_), ai_u8, idx_) + +#define AI_TENSOR_FMT_GET_SIGN(t_) \ + AI_BUFFER_FMT_GET_SIGN(AI_ARRAY_OBJ(t_->data)->format) + +#define AI_TENSOR_FMT_GET_BITS(t_) \ + AI_BUFFER_FMT_GET_BITS(AI_ARRAY_OBJ(t_->data)->format) + +#define AI_TENSOR_FMT_GET_FBITS(t_) \ + AI_BUFFER_FMT_GET_FBITS(AI_ARRAY_OBJ(t_->data)->format) + +#define AI_TENSOR_FMT_GET_TYPE(t_) \ + AI_BUFFER_FMT_GET_TYPE(AI_ARRAY_OBJ(t_->data)->format) + +#define AI_TENSOR_GET_FMT(t_) \ + AI_FMT_OBJ(AI_ARRAY_OBJ(t_->data)->format) + + +/*****************************************************************************/ +/** Network Buffers Handlers **/ +/*****************************************************************************/ +#define AI_FOR_EACH_BUFFER_ARRAY_ITEM(buffer_ptr_, buffer_array_ptr_, start_pos_, end_pos_) \ + ai_buffer* buffer_ptr_ = AI_BUFFER_ARRAY_ITEM(buffer_array_ptr_, \ + CORE_OFFSET(end_pos_, AI_BUFFER_ARRAY_SIZE(buffer_array_ptr_))); \ + for ( ; buffer_ptr_ && AI_BUFFER_ARRAY_SIZE(buffer_array_ptr_) && \ + (buffer_ptr_>=AI_BUFFER_ARRAY_ITEM(buffer_array_ptr_, \ + CORE_OFFSET(start_pos_, AI_BUFFER_ARRAY_SIZE(buffer_array_ptr_)))); buffer_ptr_--) + +/*****************************************************************************/ +/** Network Arrays Handlers **/ +/*****************************************************************************/ +#define AI_ARRAY_OBJ_FMT(array_) \ + AI_FMT_OBJ(AI_ARRAY_OBJ(array_)->format) + +#define AI_ARRAY_OBJ_FMT_GET(array_) \ + AI_FMT_GET(AI_FMT_OBJ(AI_ARRAY_OBJ(array_)->format)) + +#define AI_ARRAY_OBJ_SIZE(array_) \ + (AI_ARRAY_OBJ(array_)->size) + +#define AI_ARRAY_OBJ_BYTE_SIZE(array_) \ + AI_SIZE(AI_ARRAY_GET_BYTE_SIZE(AI_ARRAY_OBJ_FMT(array_), \ + AI_ARRAY_OBJ_SIZE(array_))) + +#define AI_ARRAY_OBJ_DATA_SIZE(array_) \ + AI_ARRAY_GET_DATA_BYTE_SIZE(AI_ARRAY_OBJ_FMT(array_), \ + AI_ARRAY_OBJ_SIZE(array_)) + +#define AI_ARRAY_OBJ_DATA(array_, type_) \ + AI_CAST(type_*, AI_ARRAY_OBJ(array_)->data) + +#define AI_ARRAY_OBJ_DATA_START(array_, type_) \ + AI_CAST(type_*, AI_ARRAY_OBJ(array_)->data_start) + +#define AI_ARRAY_OBJ_ELEM(array_, type_, pos_) \ + AI_ARRAY_OBJ_DATA(array_, type_)[(pos_)] + + +/*****************************************************************************/ +/** Network Tensors Chains / Lists Handlers **/ +/*****************************************************************************/ +#define SET_TENSOR_IN(chain_, pos_) \ + (GET_TENSOR_LIST_IN(chain_)->tensor[(pos_)]) + +#define SET_TENSOR_OUT(chain_, pos_) \ + (GET_TENSOR_LIST_OUT(chain_)->tensor[(pos_)]) + +#define AI_NODE_IO_GET(node_, in_, out_) \ + ASSERT_NODE_SANITY(node_) \ + ai_tensor* in_ = GET_TENSOR_IN((node_)->tensors, 0); \ + ai_tensor* out_ = GET_TENSOR_OUT((node_)->tensors, 0); \ + ASSERT_TENSOR_SANITY(in_) \ + ASSERT_TENSOR_SANITY(out_) + + +/*****************************************************************************/ +#define AI_BITS_TO_BYTES(bits_) \ + (((bits_)+0x7) >> 3) + +#define AI_BYTES_TO_BITS(bytes_) \ + ((bytes_) << 3) + + +/*****************************************************************************/ +/** Network Nodes Handlers **/ +/*****************************************************************************/ +#define AI_NODE_IS_FIRST(node) \ + (AI_NODE_OBJ(node)==AI_NODE_OBJ(AI_NODE_OBJ(node)->network->input_node)) + +#define AI_NODE_IS_LAST(node_) \ + ((AI_NODE_OBJ(node_)==AI_NODE_OBJ(node_)->next) || \ + (AI_NODE_OBJ(node_)->next==NULL)) + +#define AI_FOR_EACH_NODE_DO(node_, nodes_) \ + for (ai_node* node_ = AI_NODE_OBJ(nodes_); (node_); \ + node_ = ((AI_NODE_IS_LAST(node_)) ? NULL : (node_)->next)) + +/*****************************************************************************/ +typedef struct { + ai_ptr start; + ai_size size; +} ai_address_range; + +typedef struct { + ai_address_range range; + ai_u16 chain_id; + ai_u16 tensor_id; + ai_bool partial; +} ai_memory_overlap; + +/*****************************************************************************/ +AI_DECLARE_STATIC +ai_address_range core_address_range_init( + const ai_handle start, const ai_handle end) +{ + ai_address_range r; + + r.start = (startdata) + ai_bool ok; + + meta->flags = 0x0; + meta->intq_info = AI_KLASS_GET_INTQ_INFO_LIST(t); + ok = (meta->intq_info && (meta->intq_info->size>0)); + meta->flags |= (ok) ? AI_BUFFER_META_HAS_INTQ_INFO : 0x0; + return (ok) ? meta : NULL; +} + + +#if 0 +#include +#include + +AI_DECLARE_STATIC +void _dump_file_print( + const char* fname, const char* fmt, ...) +{ + static FILE* fp = NULL; + if (fname) { + if (!fp) { + fp = fopen(fname, "a"); + } + } + + if (fp) { + va_list args; + va_start(args, fmt); + vfprintf(fp, fmt, args); + va_end(args); + fflush(fp); + } +} + + +AI_DECLARE_STATIC +void _dump_bytearray( + const char* fname, + const ai_handle src, const ai_size src_size, const ai_u8 src_id, + const char* name) +{ + static FILE* fp = NULL; + if (fname && src && (src_size>0)) { + if (!fp) { + fp = fopen(fname, "a"); + } + } + + if (fp) { + switch (src_id) { + case 1: + { + const ai_float* src_value = (const ai_float*)src; + fprintf(fp, "ai_float %s[%u] = {%f", name, src_size, src_value[0]); + for (ai_size i=1; i the include directories are searched in the order - * specified in the compiler - * To enable the override, put the generated path before the API path - */ - -#include "ai_platform.h" - -AI_API_DECLARE_BEGIN - -#ifdef AI_OVERRIDE_CUSTOM_TYPES -#warning "Warning: Custom Types have been already defined!\n" -#endif - -#define AI_CUSTOM_TYPES_COUNT (3) - -#define AI_CUSTOM_TYPES_SIGNATURE_DECLARE(name) \ - const ai_custom_type_signature name[AI_CUSTOM_TYPES_COUNT+1] = { \ - AI_CUSTOM_TYPES_COUNT, \ - AI_CUSTOM_SIZE(ai_shape_dimension), \ - AI_CUSTOM_SIZE(ai_stride_dimension), \ - AI_CUSTOM_SIZE(ai_array_size), \ - }; - - -typedef ai_i32 ai_stride_dimension; -typedef ai_u32 ai_array_size; - - -AI_API_DECLARE_END - -#endif /* DATATYPES_NETWORK_H */ +/** + ****************************************************************************** + * @file datatypes_network.h + * @author AST Embedded Analytics Research Platform + * @brief Definitions of code generated network types + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef DATATYPES_NETWORK_H +#define DATATYPES_NETWORK_H + +/* + * Header to be overriden by the generated version + * by including with <> the include directories are searched in the order + * specified in the compiler + * To enable the override, put the generated path before the API path + */ + +#include "ai_platform.h" + +AI_API_DECLARE_BEGIN + +#ifdef AI_OVERRIDE_CUSTOM_TYPES +#warning "Warning: Custom Types have been already defined!\n" +#endif + +#define AI_CUSTOM_TYPES_COUNT (3) + +#define AI_CUSTOM_TYPES_SIGNATURE_DECLARE(name) \ + const ai_custom_type_signature name[AI_CUSTOM_TYPES_COUNT+1] = { \ + AI_CUSTOM_TYPES_COUNT, \ + AI_CUSTOM_SIZE(ai_shape_dimension), \ + AI_CUSTOM_SIZE(ai_stride_dimension), \ + AI_CUSTOM_SIZE(ai_array_size), \ + }; + + +typedef ai_i32 ai_stride_dimension; +typedef ai_u32 ai_array_size; + + +AI_API_DECLARE_END + +#endif /* DATATYPES_NETWORK_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/formats_list.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/formats_list.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/formats_list.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/formats_list.h index ac5f955c..e8416816 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/formats_list.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/formats_list.h @@ -1,88 +1,88 @@ -/** - ****************************************************************************** - * @file format_list.h - * @author AST Embedded Analytics Research Platform - * @brief Definitions of AI platform public APIs types - ****************************************************************************** - * @attention - * - * Copyright (c) 2019 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* FMT_ENTRY( exp_(0/1 only), name_, type_id_, - * sign_bit_, float_bit_, pmask_, bits_, fbits_, ldiv_bits_) - * Specifications (in order of the bit fields, little endian): - - name_ : it is the enum used to define both the ai_array_format and - ai_buffer_format. - - exp_ (1bit) : it is a boolean flag (0 or 1) indicating whether the format - is available as a public APIs ai_buffer format. in this case the field - exp_name_ indicates the enum name of the ai_buffer format - - (7 bits): reserved for flags - - sign_bit_ (1bit) : codes whether or not the format is of a signed type - - float_bit_ (1bit) : codes if the format is float - - ldiv_bits (2 bits) : right shift value for computing the byte size of the - format - - type_id_ (4bits) : it is used to define the "family" of the format: - see @ref AI_FMT_Q as an example. Currently supported types are: - AI_FMT_Q (fixed point types), AI_FMT_FLOAT (floating point values), - AI_FMT_LUT4 or AI_FMT_LUT8 (compressed formats) - - pmask_ (3bits) : padding mask bits for the format - - bits_ (7bits) : size in bits of the format (NB: integer+fractional bits) - - fbits_ (7bits) : number of fractional bits for the format - (for AI_FMT_Q only) - - */ - -/* Format none entry */ -FMT_ENTRY(1, NONE, AI_FMT_NONE, 0, 0, 0x0, 0, 0, 0) - -/* Floating point formats */ -FMT_ENTRY(1, FLOAT, AI_FMT_FLOAT, 1, 1, 0x0, 32, 0, 0) -FMT_ENTRY(0, FLOAT64, AI_FMT_FLOAT, 1, 1, 0x0, 64, 0, 0) -FMT_ENTRY(0, FLOAT16, AI_FMT_FLOAT, 1, 1, 0x0, 16, 0, 0) - -/* Integer formats (i.e. fractional bits = 0!) */ -FMT_ENTRY(1, U8, AI_FMT_Q, 0, 0, 0x0, 8, 0, 0) -FMT_ENTRY(1, U16, AI_FMT_Q, 0, 0, 0x0, 16, 0, 0) -FMT_ENTRY(1, U32, AI_FMT_Q, 0, 0, 0x0, 32, 0, 0) -FMT_ENTRY(0, U64, AI_FMT_Q, 0, 0, 0x0, 64, 0, 0) -FMT_ENTRY(1, U1, AI_FMT_Q, 0, 0, 0x0, 1, 0, 0) -FMT_ENTRY(0, U4, AI_FMT_Q, 0, 0, 0x0, 4, 0, 0) - -FMT_ENTRY(1, S8, AI_FMT_Q, 1, 0, 0x0, 8, 0, 0) -FMT_ENTRY(1, S16, AI_FMT_Q, 1, 0, 0x0, 16, 0, 0) -FMT_ENTRY(1, S32, AI_FMT_Q, 1, 0, 0x0, 32, 0, 0) -FMT_ENTRY(0, S64, AI_FMT_Q, 1, 0, 0x0, 64, 0, 0) -FMT_ENTRY(1, S1, AI_FMT_Q, 1, 0, 0x0, 1, 0, 0) -FMT_ENTRY(0, S4, AI_FMT_Q, 1, 0, 0x0, 4, 0, 0) - -/* Fixed-point formats including ARM CMSIS Q7, Q15, Q31 ones */ -FMT_ENTRY(1, Q, AI_FMT_Q, 1, 0, 0x0, 0, 0, 0) -FMT_ENTRY(1, Q7, AI_FMT_Q, 1, 0, 0x0, 8, 7, 0) -FMT_ENTRY(1, Q15, AI_FMT_Q, 1, 0, 0x0, 16, 15, 0) -FMT_ENTRY(0, Q31, AI_FMT_Q, 1, 0, 0x0, 32, 31, 0) - -FMT_ENTRY(1, UQ, AI_FMT_Q, 0, 0, 0x0, 0, 0, 0) -FMT_ENTRY(1, UQ7, AI_FMT_Q, 0, 0, 0x0, 8, 7, 0) -FMT_ENTRY(1, UQ15, AI_FMT_Q, 0, 0, 0x0, 16, 15, 0) -FMT_ENTRY(0, UQ31, AI_FMT_Q, 0, 0, 0x0, 32, 31, 0) - -/* Compressed formats */ -FMT_ENTRY(0, LUT4_FLOAT, AI_FMT_LUT4, 1, 1, 0x0, 32, 0, 3) -FMT_ENTRY(0, LUT8_FLOAT, AI_FMT_LUT8, 1, 1, 0x0, 32, 0, 2) -FMT_ENTRY(0, LUT4_Q15, AI_FMT_LUT4, 1, 0, 0x0, 16, 15, 2) -FMT_ENTRY(0, LUT8_Q15, AI_FMT_LUT8, 1, 0, 0x0, 16, 15, 1) -FMT_ENTRY(0, LUT4_UQ15, AI_FMT_LUT4, 0, 0, 0x0, 16, 15, 2) -FMT_ENTRY(0, LUT8_UQ15, AI_FMT_LUT8, 0, 0, 0x0, 16, 15, 1) - -/* Boolean format */ -FMT_ENTRY(1, BOOL, AI_FMT_BOOL, 0, 0, 0x0, 8, 0, 0) - -#undef FMT_ENTRY +/** + ****************************************************************************** + * @file format_list.h + * @author AST Embedded Analytics Research Platform + * @brief Definitions of AI platform public APIs types + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* FMT_ENTRY( exp_(0/1 only), name_, type_id_, + * sign_bit_, float_bit_, pmask_, bits_, fbits_, ldiv_bits_) + * Specifications (in order of the bit fields, little endian): + - name_ : it is the enum used to define both the ai_array_format and + ai_buffer_format. + - exp_ (1bit) : it is a boolean flag (0 or 1) indicating whether the format + is available as a public APIs ai_buffer format. in this case the field + exp_name_ indicates the enum name of the ai_buffer format + - (7 bits): reserved for flags + - sign_bit_ (1bit) : codes whether or not the format is of a signed type + - float_bit_ (1bit) : codes if the format is float + - ldiv_bits (2 bits) : right shift value for computing the byte size of the + format + - type_id_ (4bits) : it is used to define the "family" of the format: + see @ref AI_FMT_Q as an example. Currently supported types are: + AI_FMT_Q (fixed point types), AI_FMT_FLOAT (floating point values), + AI_FMT_LUT4 or AI_FMT_LUT8 (compressed formats) + - pmask_ (3bits) : padding mask bits for the format + - bits_ (7bits) : size in bits of the format (NB: integer+fractional bits) + - fbits_ (7bits) : number of fractional bits for the format + (for AI_FMT_Q only) + + */ + +/* Format none entry */ +FMT_ENTRY(1, NONE, AI_FMT_NONE, 0, 0, 0x0, 0, 0, 0) + +/* Floating point formats */ +FMT_ENTRY(1, FLOAT, AI_FMT_FLOAT, 1, 1, 0x0, 32, 0, 0) +FMT_ENTRY(0, FLOAT64, AI_FMT_FLOAT, 1, 1, 0x0, 64, 0, 0) +FMT_ENTRY(0, FLOAT16, AI_FMT_FLOAT, 1, 1, 0x0, 16, 0, 0) + +/* Integer formats (i.e. fractional bits = 0!) */ +FMT_ENTRY(1, U8, AI_FMT_Q, 0, 0, 0x0, 8, 0, 0) +FMT_ENTRY(1, U16, AI_FMT_Q, 0, 0, 0x0, 16, 0, 0) +FMT_ENTRY(1, U32, AI_FMT_Q, 0, 0, 0x0, 32, 0, 0) +FMT_ENTRY(0, U64, AI_FMT_Q, 0, 0, 0x0, 64, 0, 0) +FMT_ENTRY(1, U1, AI_FMT_Q, 0, 0, 0x0, 1, 0, 0) +FMT_ENTRY(0, U4, AI_FMT_Q, 0, 0, 0x0, 4, 0, 0) + +FMT_ENTRY(1, S8, AI_FMT_Q, 1, 0, 0x0, 8, 0, 0) +FMT_ENTRY(1, S16, AI_FMT_Q, 1, 0, 0x0, 16, 0, 0) +FMT_ENTRY(1, S32, AI_FMT_Q, 1, 0, 0x0, 32, 0, 0) +FMT_ENTRY(0, S64, AI_FMT_Q, 1, 0, 0x0, 64, 0, 0) +FMT_ENTRY(1, S1, AI_FMT_Q, 1, 0, 0x0, 1, 0, 0) +FMT_ENTRY(0, S4, AI_FMT_Q, 1, 0, 0x0, 4, 0, 0) + +/* Fixed-point formats including ARM CMSIS Q7, Q15, Q31 ones */ +FMT_ENTRY(1, Q, AI_FMT_Q, 1, 0, 0x0, 0, 0, 0) +FMT_ENTRY(1, Q7, AI_FMT_Q, 1, 0, 0x0, 8, 7, 0) +FMT_ENTRY(1, Q15, AI_FMT_Q, 1, 0, 0x0, 16, 15, 0) +FMT_ENTRY(0, Q31, AI_FMT_Q, 1, 0, 0x0, 32, 31, 0) + +FMT_ENTRY(1, UQ, AI_FMT_Q, 0, 0, 0x0, 0, 0, 0) +FMT_ENTRY(1, UQ7, AI_FMT_Q, 0, 0, 0x0, 8, 7, 0) +FMT_ENTRY(1, UQ15, AI_FMT_Q, 0, 0, 0x0, 16, 15, 0) +FMT_ENTRY(0, UQ31, AI_FMT_Q, 0, 0, 0x0, 32, 31, 0) + +/* Compressed formats */ +FMT_ENTRY(0, LUT4_FLOAT, AI_FMT_LUT4, 1, 1, 0x0, 32, 0, 3) +FMT_ENTRY(0, LUT8_FLOAT, AI_FMT_LUT8, 1, 1, 0x0, 32, 0, 2) +FMT_ENTRY(0, LUT4_Q15, AI_FMT_LUT4, 1, 0, 0x0, 16, 15, 2) +FMT_ENTRY(0, LUT8_Q15, AI_FMT_LUT8, 1, 0, 0x0, 16, 15, 1) +FMT_ENTRY(0, LUT4_UQ15, AI_FMT_LUT4, 0, 0, 0x0, 16, 15, 2) +FMT_ENTRY(0, LUT8_UQ15, AI_FMT_LUT8, 0, 0, 0x0, 16, 15, 1) + +/* Boolean format */ +FMT_ENTRY(1, BOOL, AI_FMT_BOOL, 0, 0, 0x0, 8, 0, 0) + +#undef FMT_ENTRY diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers.h index 345c9f33..41d7d0d6 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers.h @@ -1,75 +1,75 @@ -/** - ****************************************************************************** - * @file layers.h - * @author STMicroelectronics - * @brief header file of AI platform layers datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -#ifndef LAYERS_H -#define LAYERS_H - -#include "layers_common.h" -#include "layers_conv2d.h" -#include "layers_custom.h" -#include "layers_dense.h" -#include "layers_formats_converters.h" -#include "layers_generic.h" -#include "layers_lite_graph.h" -#include "layers_nl.h" -#include "layers_norm.h" -#include "layers_pad_dqnn.h" -#include "layers_pad_generic.h" -#include "layers_pool.h" -#include "layers_rnn.h" -#include "layers_sm.h" -#include "layers_ml.h" -#include "layers_ml_iforest.h" -#include "layers_ml_svc.h" -#include "layers_ml.h" -#include "layers_ml_linearclassifier.h" -#include "layers_ml_treeensembleclassifier.h" -#include "layers_ml_treeensembleregressor.h" -#include "layers_ml_svmregressor.h" - -#include "layers_conv2d_dqnn.h" -#include "layers_dense_dqnn.h" -#include "layers_pool_dqnn.h" -#include "layers_generic_dqnn.h" -#include "layers_upsample_generic.h" -#include "layers_upsample.h" -#include "layers_resize.h" -#include "layers_argminmax.h" -#include "ai_math_helpers.h" - - -AI_API_DECLARE_BEGIN - -/*! - * @struct ai_any_layer_ptr - * @ingroup layers - * @brief Generic union for typed layers pointers - */ -typedef struct { - ai_layer_type type; /*!< layer type id (see @ref ai_layer_type) */ - union { -#define LAYER_ENTRY(type_, id_, struct_, forward_func_, init_func_, destroy_func_) \ - AI_CONCAT(ai_layer_, struct_)* struct_; -#include "layers_list.h" - }; -} ai_any_layer_ptr; - - -AI_API_DECLARE_END - -#endif /*LAYERS_H*/ +/** + ****************************************************************************** + * @file layers.h + * @author STMicroelectronics + * @brief header file of AI platform layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef LAYERS_H +#define LAYERS_H + +#include "layers_common.h" +#include "layers_conv2d.h" +#include "layers_custom.h" +#include "layers_dense.h" +#include "layers_formats_converters.h" +#include "layers_generic.h" +#include "layers_lite_graph.h" +#include "layers_nl.h" +#include "layers_norm.h" +#include "layers_pad_dqnn.h" +#include "layers_pad_generic.h" +#include "layers_pool.h" +#include "layers_rnn.h" +#include "layers_sm.h" +#include "layers_ml.h" +#include "layers_ml_iforest.h" +#include "layers_ml_svc.h" +#include "layers_ml.h" +#include "layers_ml_linearclassifier.h" +#include "layers_ml_treeensembleclassifier.h" +#include "layers_ml_treeensembleregressor.h" +#include "layers_ml_svmregressor.h" + +#include "layers_conv2d_dqnn.h" +#include "layers_dense_dqnn.h" +#include "layers_pool_dqnn.h" +#include "layers_generic_dqnn.h" +#include "layers_upsample_generic.h" +#include "layers_upsample.h" +#include "layers_resize.h" +#include "layers_argminmax.h" +#include "ai_math_helpers.h" + + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_any_layer_ptr + * @ingroup layers + * @brief Generic union for typed layers pointers + */ +typedef struct { + ai_layer_type type; /*!< layer type id (see @ref ai_layer_type) */ + union { +#define LAYER_ENTRY(type_, id_, struct_, forward_func_, init_func_, destroy_func_) \ + AI_CONCAT(ai_layer_, struct_)* struct_; +#include "layers_list.h" + }; +} ai_any_layer_ptr; + + +AI_API_DECLARE_END + +#endif /*LAYERS_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_argminmax.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_argminmax.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_argminmax.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_argminmax.h index 175bdd34..23624253 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_argminmax.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_argminmax.h @@ -1,49 +1,49 @@ - -/** - ****************************************************************************** - * @file layers_arminmax.h - * @author AIS - * @brief header file of AI platform generic layers datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LAYERS_ARGMINMAX_H -#define LAYERS_ARGMINMAX_H - -#include "layers_generic.h" - - -AI_API_DECLARE_BEGIN - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Compute the indices of the max elements of the input tensor's element along the provided axis. - * @ingroup layers_generic - * @param layer argminmax layer - */ -AI_INTERNAL_API -void forward_argmax_is8(ai_layer* layer); - -/*! - * @brief Compute the indices of the max elements of the input tensor's element along the provided axis. - * @ingroup layers_generic - * @param layer argminmax layer - */ -AI_INTERNAL_API -void forward_argmin_is8(ai_layer* layer); - -AI_API_DECLARE_END - -#endif /*LAYERS_ARGMINMAX_H*/ + +/** + ****************************************************************************** + * @file layers_arminmax.h + * @author AIS + * @brief header file of AI platform generic layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_ARGMINMAX_H +#define LAYERS_ARGMINMAX_H + +#include "layers_generic.h" + + +AI_API_DECLARE_BEGIN + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Compute the indices of the max elements of the input tensor's element along the provided axis. + * @ingroup layers_generic + * @param layer argminmax layer + */ +AI_INTERNAL_API +void forward_argmax_is8(ai_layer* layer); + +/*! + * @brief Compute the indices of the max elements of the input tensor's element along the provided axis. + * @ingroup layers_generic + * @param layer argminmax layer + */ +AI_INTERNAL_API +void forward_argmin_is8(ai_layer* layer); + +AI_API_DECLARE_END + +#endif /*LAYERS_ARGMINMAX_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_common.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_common.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_common.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_common.h index 80e0c19c..ddad47a7 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_common.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_common.h @@ -1,283 +1,283 @@ -/** - ****************************************************************************** - * @file layers_common.h - * @author AST Embedded Analytics Research Platform - * @brief header file of AI platform layers datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LAYERS_COMMON_H -#define LAYERS_COMMON_H - -#ifdef USE_CYCLE_MEASUREMENTS - #include "layers_cycles_estimation.h" -#endif -#include "ai_platform.h" -#include "ai_common_config.h" - -#include "core_common.h" - -/* optimizations */ -#define AI_OPTIM_FUNC_MP_ARRAY_F32 (0) - - -#define AI_LAYER_OBJ(obj_) \ - ((ai_layer_base*)(obj_)) - -#define AI_LAYER_FUNC(func_) \ - ((layer_func)(func_)) - -#define AI_LAYER_TYPE(type_) \ - ( (ai_layer_type)((ai_u32)(type_)&0xFFFF) ) - -#define AI_LAYER_TYPE_ENTRY(type_) \ - AI_CONCAT(AI_CONCAT(AI_LAYER_, type_), _TYPE) - -#define AI_LAYER_TYPE_NAME(type_) \ - ai_layer_type_name(AI_LAYER_TYPE(type_)) - - -#if (AI_TOOLS_API_VERSION <= AI_TOOLS_API_VERSION_1_3) -#pragma message ("Including deprecated AI_LAYER_OBJ_INIT, AI_LAYER_OBJ_DECLARE") - -AI_DEPRECATED -#define AI_LAYER_OBJ_INIT(type_, id_, network_, \ - next_, forward_, ...) \ - { \ - AI_NODE_COMMON_INIT(AI_CONCAT(AI_LAYER_, type_), id_, 0x0, \ - NULL, network_, next_, forward_), \ - ## __VA_ARGS__ \ - } - -AI_DEPRECATED -#define AI_LAYER_OBJ_DECLARE(varname_, id_, type_, struct_, forward_func_, \ - network_, next_, attr_, ...) \ - AI_ALIGNED(4) \ - attr_ AI_CONCAT(ai_layer_, struct_) varname_ = \ - AI_LAYER_OBJ_INIT(type_, id_, network_, \ - next_, forward_func_, \ - ## __VA_ARGS__); - -#else - -#define AI_LAYER_OBJ_INIT(type_, id_, flags_, klass_, network_, \ - next_, forward_, tensors_, ...) \ - { \ - AI_NODE_COMMON_INIT(AI_CONCAT(AI_LAYER_, type_), id_, flags_, \ - klass_, network_, next_, forward_), \ - .tensors = (tensors_), \ - ## __VA_ARGS__ \ - } - -#define AI_LAYER_OBJ_DECLARE( \ - varname_, id_, \ - type_, flags_, klass_obj_, \ - struct_, forward_func_, \ - tensors_chain_, \ - network_, next_, attr_, ...) \ - AI_ALIGNED(4) \ - attr_ AI_CONCAT(ai_layer_, struct_) varname_ = \ - AI_LAYER_OBJ_INIT(type_, id_, flags_, klass_obj_, network_, \ - next_, forward_func_, tensors_chain_, ## __VA_ARGS__); - -#endif /* AI_TOOLS_API_VERSION_1_3 */ - -#ifdef HAS_AI_ASSERT - #define AI_LAYER_IO_GET(layer_, in_, out_) \ - ASSERT_LAYER_SANITY(layer_) \ - const ai_tensor* in_ = GET_TENSOR_IN((layer_)->tensors, 0); \ - ai_tensor* out_ = GET_TENSOR_OUT((layer_)->tensors, 0); \ - ASSERT_TENSOR_DATA_SANITY(in_) \ - ASSERT_TENSOR_DATA_SANITY(out_) - - #define AI_LAYER_TENSOR_LIST_IO_GET(layer_, tlist_in_, tlist_out_) \ - ASSERT_LAYER_SANITY(layer_) \ - const ai_tensor_list* tlist_in_ = GET_TENSOR_LIST_IN((layer_)->tensors); \ - ai_tensor_list* tlist_out_ = GET_TENSOR_LIST_OUT((layer_)->tensors); \ - ASSERT_TENSOR_LIST_SANITY(tlist_in_) \ - ASSERT_TENSOR_LIST_SANITY(tlist_out_) - - #define AI_LAYER_WEIGHTS_GET(layer_, weights_, bias_) \ - const ai_tensor* weights_ = GET_TENSOR_WEIGHTS((layer_)->tensors, 0); \ - const ai_tensor* bias_ = (GET_TENSOR_LIST_SIZE(GET_TENSOR_LIST_WEIGTHS((layer_)->tensors))>1) \ - ? GET_TENSOR_WEIGHTS((layer_)->tensors, 1) \ - : NULL; \ - ASSERT_TENSOR_DATA_SANITY(weights_) \ - if (bias_) { ASSERT_TENSOR_DATA_SANITY(bias_) } -#else - #define AI_LAYER_IO_GET(layer_, in_, out_) \ - const ai_tensor* in_ = GET_TENSOR_IN((layer_)->tensors, 0); \ - ai_tensor* out_ = GET_TENSOR_OUT((layer_)->tensors, 0); - - #define AI_LAYER_TENSOR_LIST_IO_GET(layer_, tlist_in_, tlist_out_) \ - const ai_tensor_list* tlist_in_ = GET_TENSOR_LIST_IN((layer_)->tensors); \ - ai_tensor_list* tlist_out_ = GET_TENSOR_LIST_OUT((layer_)->tensors); - - #define AI_LAYER_WEIGHTS_GET(layer_, weights_, bias_) \ - const ai_tensor* weights_ = GET_TENSOR_WEIGHTS((layer_)->tensors, 0); \ - const ai_tensor* bias_ = (GET_TENSOR_LIST_SIZE(GET_TENSOR_LIST_WEIGTHS((layer_)->tensors))>1) \ - ? GET_TENSOR_WEIGHTS((layer_)->tensors, 1) \ - : NULL; \ - -#endif /*HAS_AI_ASSERT*/ - - -AI_API_DECLARE_BEGIN - -/*! - * @defgroup layers_common Layers Common - * @brief Implementation of the common layers datastructures - * This header enumerates the layers specific definition implemented in the - * library toghether with the macros and datatypes used to manipulate them. - */ - -/*! - * @typedef (*func_copy_tensor) - * @ingroup layers_common - * @brief Fuction pointer for generic tensor copy routines - * this function pointer abstracts a generic tensor copy routine. - */ -typedef ai_bool (*func_copy_tensor)(ai_tensor* dst, const ai_tensor* src); - -/*! - * @enum ai_layer_type - * @ingroup layers_common - * @brief ai_tools supported layers type id - */ -typedef enum { -#define LAYER_ENTRY(type_, id_, struct_, forward_func_, init_func_, destroy_func_) \ - AI_LAYER_TYPE_ENTRY(type_) = id_, -#include "layers_list.h" -} ai_layer_type; - -#define AI_LAYER_COMMON_FIELDS_DECLARE \ - AI_NODE_COMMON_FIELDS_DECLARE - -#define AI_LAYER_STATEFUL_FIELDS_DECLARE \ - AI_NODE_STATEFUL_FIELDS_DECLARE - - -/*! - * @typedef void (*layer_func)(struct ai_layer_* layer) - * @ingroup layers_common - * @brief Callback signatures for all layers forward functions - */ -typedef node_func layer_func; - -/*! - * @struct ai_layer_base - * @ingroup layers_common - * @brief Structure encoding a base layer in the network - * - */ -typedef ai_node ai_layer_base; - -/*! - * @struct ai_layer_stateful - * @ingroup layers_common - * @brief Structure encoding a stateful layer in the network - * - */ -typedef ai_node_stateful ai_layer_stateful; - -/*! - * @brief Check the custom network types against the internally compiled ones - * Helper function to check if the private APIs where compiled with a different - * `datatypes_network.h` than the one provided to the caller. - * @ingroup layers_common - * @param signatures list of type sizes signatures (first element is the number of types) - * @return false if there is a type size mismatch - */ -AI_INTERNAL_API -ai_bool ai_check_custom_types(const ai_custom_type_signature* signatures); - -/*! - * @brief Helper API to retrieve a human readable layer type from enum - * @ingroup layers_common - * @param type in type of layer - * @return string defining the type of the layer - */ -AI_INTERNAL_API -const char* ai_layer_type_name(const ai_layer_type type); - -/*! - * @brief Helper API to check if a node is a valid layer type - * @ingroup layers_common - * @param type in type of layer - * @return true if the layer is one of the ones listed in the enum, - * false otherwise - */ -AI_INTERNAL_API -ai_bool ai_layer_type_is_valid(const ai_layer_type type); - -#ifdef HAS_AI_ASSERT - -/*! - * @brief check scratch size computed with actual scratch buffer size - * @ingroup layers - * @param layer_type the layer type - * @param fmt buffers format - * @param filt_width filter width (when relevant) - * @param filt_height filter height (when relevant) - * @param n_channel_in the number of channels in - * @param n_channel_out the number of channels out - * @param is_pointwise is pointwise convulation (conv2d) - * @param is_rgb is rgb convolution (conv2d) - * @param is depthwise is depthwise convolution (conv2d) - * @param is_ch_wise has weights per channel - * @param is_sssa is signed - * @param p_tensor_scratch the scratch tensor - * @param p_function_name the name of the function - * @param line_nb the the line of the function - */ -AI_INTERNAL_API -void ai_layer_check_scratch_size( ai_layer_type layer_type, ai_array_format fmt, - ai_size filt_width, ai_size filt_height, - ai_u16 n_channel_in, ai_u16 n_channel_out, - ai_bool is_pointwise, ai_bool is_rgb, - ai_bool is_depthwise, ai_bool is_ch1st, ai_bool is_ch_wise, - ai_bool is_sssa, ai_u32 tensor_scratch_size_bytes, - const char *p_function_name, const int line_nb); - -#define CHECK_SCRATCH_BUFFER_SIZE( layer_type, fmt, \ - filt_width, filt_height, \ - n_channel_in, n_channel_out, \ - is_pointwise, is_rgb, \ - is_depthwise, is_ch1st, is_ch_wise, \ - is_sssa_ch, tensor_scratch_size_bytes) \ - ai_layer_check_scratch_size( layer_type, fmt, \ - filt_width, filt_height, \ - n_channel_in, n_channel_out, \ - is_pointwise, is_rgb, \ - is_depthwise, is_ch1st, is_ch_wise, \ - is_sssa_ch, tensor_scratch_size_bytes, \ - __FUNCTION__, __LINE__); - -#define IS_PW 1 -#define IS_RGB 1 -#define IS_DW 1 -#define IS_CH1ST 1 -#define IS_CH_WISE 1 -#define IS_SSSA_CH 1 - -#define NOT_PW 0 -#define NOT_RGB 0 -#define NOT_DW 0 -#define NOT_CH1ST 0 -#define NOT_CH_WISE 0 -#define NOT_SSSA_CH 0 - -#endif - -AI_API_DECLARE_END - -#endif /*LAYERS_COMMON_H*/ +/** + ****************************************************************************** + * @file layers_common.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_COMMON_H +#define LAYERS_COMMON_H + +#ifdef USE_CYCLE_MEASUREMENTS + #include "layers_cycles_estimation.h" +#endif +#include "ai_platform.h" +#include "ai_common_config.h" + +#include "core_common.h" + +/* optimizations */ +#define AI_OPTIM_FUNC_MP_ARRAY_F32 (0) + + +#define AI_LAYER_OBJ(obj_) \ + ((ai_layer_base*)(obj_)) + +#define AI_LAYER_FUNC(func_) \ + ((layer_func)(func_)) + +#define AI_LAYER_TYPE(type_) \ + ( (ai_layer_type)((ai_u32)(type_)&0xFFFF) ) + +#define AI_LAYER_TYPE_ENTRY(type_) \ + AI_CONCAT(AI_CONCAT(AI_LAYER_, type_), _TYPE) + +#define AI_LAYER_TYPE_NAME(type_) \ + ai_layer_type_name(AI_LAYER_TYPE(type_)) + + +#if (AI_TOOLS_API_VERSION <= AI_TOOLS_API_VERSION_1_3) +#pragma message ("Including deprecated AI_LAYER_OBJ_INIT, AI_LAYER_OBJ_DECLARE") + +AI_DEPRECATED +#define AI_LAYER_OBJ_INIT(type_, id_, network_, \ + next_, forward_, ...) \ + { \ + AI_NODE_COMMON_INIT(AI_CONCAT(AI_LAYER_, type_), id_, 0x0, \ + NULL, network_, next_, forward_), \ + ## __VA_ARGS__ \ + } + +AI_DEPRECATED +#define AI_LAYER_OBJ_DECLARE(varname_, id_, type_, struct_, forward_func_, \ + network_, next_, attr_, ...) \ + AI_ALIGNED(4) \ + attr_ AI_CONCAT(ai_layer_, struct_) varname_ = \ + AI_LAYER_OBJ_INIT(type_, id_, network_, \ + next_, forward_func_, \ + ## __VA_ARGS__); + +#else + +#define AI_LAYER_OBJ_INIT(type_, id_, flags_, klass_, network_, \ + next_, forward_, tensors_, ...) \ + { \ + AI_NODE_COMMON_INIT(AI_CONCAT(AI_LAYER_, type_), id_, flags_, \ + klass_, network_, next_, forward_), \ + .tensors = (tensors_), \ + ## __VA_ARGS__ \ + } + +#define AI_LAYER_OBJ_DECLARE( \ + varname_, id_, \ + type_, flags_, klass_obj_, \ + struct_, forward_func_, \ + tensors_chain_, \ + network_, next_, attr_, ...) \ + AI_ALIGNED(4) \ + attr_ AI_CONCAT(ai_layer_, struct_) varname_ = \ + AI_LAYER_OBJ_INIT(type_, id_, flags_, klass_obj_, network_, \ + next_, forward_func_, tensors_chain_, ## __VA_ARGS__); + +#endif /* AI_TOOLS_API_VERSION_1_3 */ + +#ifdef HAS_AI_ASSERT + #define AI_LAYER_IO_GET(layer_, in_, out_) \ + ASSERT_LAYER_SANITY(layer_) \ + const ai_tensor* in_ = GET_TENSOR_IN((layer_)->tensors, 0); \ + ai_tensor* out_ = GET_TENSOR_OUT((layer_)->tensors, 0); \ + ASSERT_TENSOR_DATA_SANITY(in_) \ + ASSERT_TENSOR_DATA_SANITY(out_) + + #define AI_LAYER_TENSOR_LIST_IO_GET(layer_, tlist_in_, tlist_out_) \ + ASSERT_LAYER_SANITY(layer_) \ + const ai_tensor_list* tlist_in_ = GET_TENSOR_LIST_IN((layer_)->tensors); \ + ai_tensor_list* tlist_out_ = GET_TENSOR_LIST_OUT((layer_)->tensors); \ + ASSERT_TENSOR_LIST_SANITY(tlist_in_) \ + ASSERT_TENSOR_LIST_SANITY(tlist_out_) + + #define AI_LAYER_WEIGHTS_GET(layer_, weights_, bias_) \ + const ai_tensor* weights_ = GET_TENSOR_WEIGHTS((layer_)->tensors, 0); \ + const ai_tensor* bias_ = (GET_TENSOR_LIST_SIZE(GET_TENSOR_LIST_WEIGTHS((layer_)->tensors))>1) \ + ? GET_TENSOR_WEIGHTS((layer_)->tensors, 1) \ + : NULL; \ + ASSERT_TENSOR_DATA_SANITY(weights_) \ + if (bias_) { ASSERT_TENSOR_DATA_SANITY(bias_) } +#else + #define AI_LAYER_IO_GET(layer_, in_, out_) \ + const ai_tensor* in_ = GET_TENSOR_IN((layer_)->tensors, 0); \ + ai_tensor* out_ = GET_TENSOR_OUT((layer_)->tensors, 0); + + #define AI_LAYER_TENSOR_LIST_IO_GET(layer_, tlist_in_, tlist_out_) \ + const ai_tensor_list* tlist_in_ = GET_TENSOR_LIST_IN((layer_)->tensors); \ + ai_tensor_list* tlist_out_ = GET_TENSOR_LIST_OUT((layer_)->tensors); + + #define AI_LAYER_WEIGHTS_GET(layer_, weights_, bias_) \ + const ai_tensor* weights_ = GET_TENSOR_WEIGHTS((layer_)->tensors, 0); \ + const ai_tensor* bias_ = (GET_TENSOR_LIST_SIZE(GET_TENSOR_LIST_WEIGTHS((layer_)->tensors))>1) \ + ? GET_TENSOR_WEIGHTS((layer_)->tensors, 1) \ + : NULL; \ + +#endif /*HAS_AI_ASSERT*/ + + +AI_API_DECLARE_BEGIN + +/*! + * @defgroup layers_common Layers Common + * @brief Implementation of the common layers datastructures + * This header enumerates the layers specific definition implemented in the + * library toghether with the macros and datatypes used to manipulate them. + */ + +/*! + * @typedef (*func_copy_tensor) + * @ingroup layers_common + * @brief Fuction pointer for generic tensor copy routines + * this function pointer abstracts a generic tensor copy routine. + */ +typedef ai_bool (*func_copy_tensor)(ai_tensor* dst, const ai_tensor* src); + +/*! + * @enum ai_layer_type + * @ingroup layers_common + * @brief ai_tools supported layers type id + */ +typedef enum { +#define LAYER_ENTRY(type_, id_, struct_, forward_func_, init_func_, destroy_func_) \ + AI_LAYER_TYPE_ENTRY(type_) = id_, +#include "layers_list.h" +} ai_layer_type; + +#define AI_LAYER_COMMON_FIELDS_DECLARE \ + AI_NODE_COMMON_FIELDS_DECLARE + +#define AI_LAYER_STATEFUL_FIELDS_DECLARE \ + AI_NODE_STATEFUL_FIELDS_DECLARE + + +/*! + * @typedef void (*layer_func)(struct ai_layer_* layer) + * @ingroup layers_common + * @brief Callback signatures for all layers forward functions + */ +typedef node_func layer_func; + +/*! + * @struct ai_layer_base + * @ingroup layers_common + * @brief Structure encoding a base layer in the network + * + */ +typedef ai_node ai_layer_base; + +/*! + * @struct ai_layer_stateful + * @ingroup layers_common + * @brief Structure encoding a stateful layer in the network + * + */ +typedef ai_node_stateful ai_layer_stateful; + +/*! + * @brief Check the custom network types against the internally compiled ones + * Helper function to check if the private APIs where compiled with a different + * `datatypes_network.h` than the one provided to the caller. + * @ingroup layers_common + * @param signatures list of type sizes signatures (first element is the number of types) + * @return false if there is a type size mismatch + */ +AI_INTERNAL_API +ai_bool ai_check_custom_types(const ai_custom_type_signature* signatures); + +/*! + * @brief Helper API to retrieve a human readable layer type from enum + * @ingroup layers_common + * @param type in type of layer + * @return string defining the type of the layer + */ +AI_INTERNAL_API +const char* ai_layer_type_name(const ai_layer_type type); + +/*! + * @brief Helper API to check if a node is a valid layer type + * @ingroup layers_common + * @param type in type of layer + * @return true if the layer is one of the ones listed in the enum, + * false otherwise + */ +AI_INTERNAL_API +ai_bool ai_layer_type_is_valid(const ai_layer_type type); + +#ifdef HAS_AI_ASSERT + +/*! + * @brief check scratch size computed with actual scratch buffer size + * @ingroup layers + * @param layer_type the layer type + * @param fmt buffers format + * @param filt_width filter width (when relevant) + * @param filt_height filter height (when relevant) + * @param n_channel_in the number of channels in + * @param n_channel_out the number of channels out + * @param is_pointwise is pointwise convulation (conv2d) + * @param is_rgb is rgb convolution (conv2d) + * @param is depthwise is depthwise convolution (conv2d) + * @param is_ch_wise has weights per channel + * @param is_sssa is signed + * @param p_tensor_scratch the scratch tensor + * @param p_function_name the name of the function + * @param line_nb the the line of the function + */ +AI_INTERNAL_API +void ai_layer_check_scratch_size( ai_layer_type layer_type, ai_array_format fmt, + ai_size filt_width, ai_size filt_height, + ai_u16 n_channel_in, ai_u16 n_channel_out, + ai_bool is_pointwise, ai_bool is_rgb, + ai_bool is_depthwise, ai_bool is_ch1st, ai_bool is_ch_wise, + ai_bool is_sssa, ai_u32 tensor_scratch_size_bytes, + const char *p_function_name, const int line_nb); + +#define CHECK_SCRATCH_BUFFER_SIZE( layer_type, fmt, \ + filt_width, filt_height, \ + n_channel_in, n_channel_out, \ + is_pointwise, is_rgb, \ + is_depthwise, is_ch1st, is_ch_wise, \ + is_sssa_ch, tensor_scratch_size_bytes) \ + ai_layer_check_scratch_size( layer_type, fmt, \ + filt_width, filt_height, \ + n_channel_in, n_channel_out, \ + is_pointwise, is_rgb, \ + is_depthwise, is_ch1st, is_ch_wise, \ + is_sssa_ch, tensor_scratch_size_bytes, \ + __FUNCTION__, __LINE__); + +#define IS_PW 1 +#define IS_RGB 1 +#define IS_DW 1 +#define IS_CH1ST 1 +#define IS_CH_WISE 1 +#define IS_SSSA_CH 1 + +#define NOT_PW 0 +#define NOT_RGB 0 +#define NOT_DW 0 +#define NOT_CH1ST 0 +#define NOT_CH_WISE 0 +#define NOT_SSSA_CH 0 + +#endif + +AI_API_DECLARE_END + +#endif /*LAYERS_COMMON_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_conv2d.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_conv2d.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_conv2d.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_conv2d.h index 714ccbab..f2a34274 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_conv2d.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_conv2d.h @@ -1,623 +1,623 @@ -/** - ****************************************************************************** - * @file layers_conv2d.h - * @author AST Embedded Analytics Research Platform - * @brief header file of AI platform conv2d layers datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2018 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LAYERS_CONV2D_H -#define LAYERS_CONV2D_H - -#include "layers_nl.h" -#include "layers_pool.h" - - - - -#define AI_LAYER_CONV2D_FIELDS_DECLARE \ - AI_LAYER_COMMON_FIELDS_DECLARE \ - ai_u32 groups; /*!< groups for separable convolution */ \ - AI_CONST ai_array* nl_params; /*!< array pointer to non linear parameters */ \ - ai_handle nl_func; /*!< function pointer to non linear transform */ \ - ai_shape_2d filter_stride; /*!< filter stride, how much the filter moves */ \ - ai_shape_2d dilation; /*!< dilation value along axis of the filter */ \ - ai_shape filter_pad; /*!< filter pad 4d */ \ - ai_layer_format_type in_ch_format; /*!< Input format (Channel 1st vs Channel last */ \ - ai_layer_format_type out_ch_format; /*!< Output format (Channel 1st vs Channel last */ - - - -/*! - * @defgroup layers_conv2d Convolutive Layers Definitions - * @brief definition - * - */ - -AI_API_DECLARE_BEGIN - -/*! - * @struct ai_layer_dense - * @ingroup layers_conv2d - * @brief Dense (fully connected) layer - */ -typedef ai_layer_base ai_layer_dense; - -/*! - * @struct ai_layer_gemm - * @ingroup layers_conv2d - * @brief layer for General Matrix Multiplication - * - * Layer for General Matrix Multiplication (GEMM): - * \f{equation}{ Y = \alpha A \cdot B + \beta C \f} - * \f$\alpha\f$ and \f$\beta\f$ are paramaters, A and B are matrices, - * C is a matrix or an array. Size checks for A, B, C, and Y are performed and - * broadcast is applied on C if necessary. - * This is a sequential layer (see @ref ai_layer). - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_gemm_ { - AI_LAYER_COMMON_FIELDS_DECLARE - ai_float alpha; /*!< alpha coefficient */ - ai_float beta; /*!< beta coefficient */ - ai_u8 tA; /*!< transpose A flag */ - ai_u8 tB; /*!< transpose B flag */ -} ai_layer_gemm; - -/*! - * @struct ai_layer_conv2d - * @ingroup layers_conv2d - * @brief 2D convolutional layer with strides and pads - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_conv2d_ { - AI_LAYER_CONV2D_FIELDS_DECLARE -} ai_layer_conv2d; - -/*! - * @struct ai_layer_conv2d_nl_pool - * @ingroup layers_conv2d - * @brief 2D convolutional layer + nl + pooling with strides and pads - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_conv2d_nl_pool_ { - AI_LAYER_CONV2D_FIELDS_DECLARE - - ai_shape_2d pool_size; /*!< pooling size */ - ai_shape_2d pool_stride; /*!< pooling stride */ - ai_shape pool_pad; /*!< pooling pad */ - - ai_handle pool_func; /*!< function pointer to pooling transform */ -} ai_layer_conv2d_nl_pool; - - -/* -AI_INTERNAL_API -void ai_dict8_dot_array_f32(ai_handle out, ai_ptr_const data0, ai_ptr_const lut, - const ai_float* data1, const ai_size data_size); - -AI_INTERNAL_API -void ai_dict4_dot_array_f32(ai_handle out, ai_ptr_const data0, ai_ptr_const lut, - const ai_float* data1, const ai_size data_size); -*/ - - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Computes the activations of a floating point 32 2D convolutional layer. - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_if32of32wf32(ai_layer* layer); - -/*! - * @brief Computes the activations of a floating point 32 2D dw layer. - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_dw_if32of32wf32(ai_layer* layer); - -/*! - * @brief Computes the activations of a floating point 32 2D convolutional group layer. - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_if32of32wf32_group(ai_layer* layer); - -/*! - * @brief Computes the activations of a 2D floating point 32 pool fused convolutional layer. - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_if32of32wf32_nl_pool(ai_layer* layer); - -/*! - * @brief Computes the activations of a 2D floating point 32 pool fused dw layer. - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_dw_if32of32wf32_nl_pool(ai_layer* layer); - -/*! - * @brief Computes the activations of a 2D floating point 32 pool fused convolutional group layer. - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_if32of32wf32_group_nl_pool(ai_layer* layer); - -/*! - * @brief Computes the activations of a GEMM layer. - * @ingroup layers - * @param layer the layer including output and input tensors - */ -AI_INTERNAL_API -void forward_gemm(ai_layer* layer); - -/*! - * @brief Computes matmul layer, intended as numpy.matmul(A,B). - * @ingroup layers - * @param layer the layer including output and input tensors - */ -AI_INTERNAL_API -void forward_matmul(ai_layer* layer); - -/*! - * @brief Computes the activations of a dense (fully connected) layer. - * @ingroup layers_conv2d - * @param layer the dense layer - */ -AI_INTERNAL_API -void forward_dense(ai_layer* layer); - - -/*! - * @brief Computes the activations of a fixed point 2D convolutional layer. - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_fixed(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a fixed point @ref ai_layer_conv2d_nl_pool - * layer. - * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear - * layer + optional pooling / nonlinearity (average, max) - * @ingroup layers_conv2d - * @param layer see @ai_layer_conv2d_nl_pool - */ -AI_INTERNAL_API -void forward_conv2d_nl_pool_fixed(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a integer quantized 2D convolutional layer. - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_integer(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a integer quantized 2D convolutional layer - * for SSSA per layer quantized scheme - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_integer_SSSA(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a integer quantized 2D convolutional layer - * for SSSA per channel quantized scheme - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_is8os8ws8_sssa_ch(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a int8 quantized DW layer - * for SSSA per channel quantized scheme - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_dw_sssa8_ch(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a int8 quantized DW layer - * for SSSA per channel quantized scheme, with 3x3 kernels - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_dw_3x3_sssa8_ch(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a int8 quantized DW layer - * for SSSA per channel quantized scheme, with 3x3 kernels and input are - * channel first - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_dw_3x3_ch1st_sssa8_ch(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a int8 quantized DW layer - * for SSSA per channel quantized scheme with depth multiplier > 1 - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_dw_dm_sssa8_ch(ai_layer *pLayer); - -/*! - * @brief Computes the activations of int8 quantized DW layers. - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_dw_all_sssa8_ch(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a int8 quantized PW layer - * for SSSA per channel quantized scheme - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_pw_sssa8_ch(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a int8 quantized dilated Conv2d layer - * for SSSA per channel quantized scheme (valid padding) - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_dilated_sssa8_ch(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a int8 non dilated Conv2d layer - * for SSSA per channel quantized scheme (valid padding) - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_deep_sssa8_ch(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a int8 non dilated Conv2d layer - * for SSSA per channel quantized scheme (valid padding) - * number of output channel is greater than 8 - * Kernels shall be 3x3 and stride is (1,1) - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_deep_3x3_sssa8_ch(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a int8 non dilated Conv2d layer - * for SSSA per channel quantized scheme (valid or same padding) - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_sssa8_ch(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a int8 quantized Conv2d layer - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_all_sssa8_ch(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a int8 quantized RGB Conv2d layer - * for SSSA per channel quantized scheme - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_rgb_sssa8_ch(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a int8 quantized DW layer - * for SSSA per channel quantized scheme with pooling fused - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_dw_sssa8_ch_nl_pool(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a int8 quantized DW layer - * for SSSA per channel quantized scheme, with 3x3 kernels, - * with pooling fused - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_dw_3x3_sssa8_ch_nl_pool(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a int8 quantized DW layer - * for SSSA per channel quantized scheme, with 3x3 kernels, - * with pooling fused - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_dw_3x3_ch1st_sssa8_ch_nl_pool(ai_layer *pLayer); - - -/*! - * @brief Computes the activations of a int8 quantized DW layer - * for SSSA per channel quantized scheme with depth multiplier > 1 - * with pooling fused - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_dw_dm_sssa8_ch_nl_pool(ai_layer *pLayer); - -/*! - * @brief Computes the activations of int8 quantized DW layers, with pooling fused - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_dw_all_sssa8_ch_nl_pool(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a int8 quantized PW layer, - * with pooling fused - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_pw_sssa8_ch_nl_pool(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a int8 quantized dilated Conv2d layer - * for SSSA per channel quantized scheme (valid padding) and pooling fused - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_dilated_sssa8_ch_nl_pool(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a int8 quantized non dilated Conv2d layer - * for SSSA per channel quantized scheme (valid padding) and pooling fused - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_deep_sssa8_ch_nl_pool(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a int8 non dilated Conv2d layer - * for SSSA per channel quantized scheme (valid padding) and pooling fused - * number of output channel is greater than 8 - * Kernels shall be 3x3 and stride is (1,1) - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_deep_3x3_sssa8_ch_nl_pool(ai_layer *pLayer); - - -/*! - * @brief Computes the activations of a int8 quantized non dilated Conv2d layer - * for SSSA per channel quantized scheme (valid or same padding) and pooling fused - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_sssa8_ch_nl_pool(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a int8 quantized Conv2d layer and pooling fused - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_all_sssa8_ch_nl_pool(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a integer quantized 2D convolutional layer - * for SSUA per layer quantized scheme - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_integer_SSUA(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a integer quantized 2D convolutional layer - * for SSUA per channel quantized scheme - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_integer_SSUA_ch(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a integer quantized 2D convolutional layer - * for UAUA per layer quantized scheme - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_integer_UAUA(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a integer quantized 2D convolutional layer - * for UAUA per channel quantized scheme - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_integer_UAUA_ch(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a integer @ref ai_layer_conv2d_nl_pool layer. - * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear - * layer + optional pooling / nonlinearity (average, max) - * @ingroup layers_conv2d - * @param layer see @ai_layer_conv2d_nl_pool - */ -AI_INTERNAL_API -void forward_conv2d_nl_pool_integer(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a integer @ref ai_layer_conv2d_nl_pool layer - * for SSSA per layer quantized scheme - * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear - * layer + optional pooling / nonlinearity (average, max) - * @ingroup layers_conv2d - * @param layer see @ai_layer_conv2d_nl_pool - */ -AI_INTERNAL_API -void forward_conv2d_nl_pool_integer_SSSA(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a integer @ref ai_layer_conv2d_nl_pool layer - * for SSSA per channel quantized scheme - * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear - * layer + optional pooling / nonlinearity (average, max) - * @ingroup layers_conv2d - * @param layer see @ai_layer_conv2d_nl_pool - */ -AI_INTERNAL_API -void forward_conv2d_nl_pool_integer_SSSA_ch(ai_layer *pLayer); - - -/*! - * @brief Computes the activations of a integer @ref ai_layer_conv2d_nl_pool layer - * for SSUA per layer quantized scheme - * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear - * layer + optional pooling / nonlinearity (average, max) - * @ingroup layers_conv2d - * @param layer see @ai_layer_conv2d_nl_pool - */ -AI_INTERNAL_API -void forward_conv2d_nl_pool_integer_SSUA(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a integer @ref ai_layer_conv2d_nl_pool layer - * for SSUA per channel quantized scheme - * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear - * layer + optional pooling / nonlinearity (average, max) - * @ingroup layers_conv2d - * @param layer see @ai_layer_conv2d_nl_pool - */ -AI_INTERNAL_API -void forward_conv2d_nl_pool_integer_SSUA_ch(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a integer @ref ai_layer_conv2d_nl_pool layer - * for UAUA per layer quantized scheme - * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear - * layer + optional pooling / nonlinearity (average, max) - * @ingroup layers_conv2d - * @param layer see @ai_layer_conv2d_nl_pool - */ -AI_INTERNAL_API -void forward_conv2d_nl_pool_integer_UAUA(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a integer @ref ai_layer_conv2d_nl_pool layer - * for UAUA per channel quantized scheme - * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear - * layer + optional pooling / nonlinearity (average, max) - * @ingroup layers_conv2d - * @param layer see @ai_layer_conv2d_nl_pool - */ -AI_INTERNAL_API -void forward_conv2d_nl_pool_integer_UAUA_ch(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a integer dense (fully connected) layer. - * @ingroup layers_dense - * @param layer the dense layer - */ -AI_INTERNAL_API -void forward_dense_integer(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a integer dense (fully connected) layer - * for SSSA per layer quantized scheme - * @ingroup layers_dense - * @param layer the dense layer - */ -AI_INTERNAL_API -void forward_dense_integer_SSSA(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a integer dense (fully connected) layer - * for SSSA per channel quantized scheme - * @ingroup layers_dense - * @param layer the dense layer - */ -AI_INTERNAL_API -void forward_dense_integer_SSSA_ch(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a integer dense (fully connected) layer - * for SSUA per layer quantized scheme - * @ingroup layers_dense - * @param layer the dense layer - */ -AI_INTERNAL_API -void forward_dense_integer_SSUA(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a integer dense (fully connected) layer - * for SSUA per channel quantized scheme - * @ingroup layers_dense - * @param layer the dense layer - */ -AI_INTERNAL_API -void forward_dense_integer_SSUA_ch(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a integer dense (fully connected) layer - * for UAUA per layer quantized scheme - * @ingroup layers_dense - * @param layer the dense layer - */ -AI_INTERNAL_API -void forward_dense_integer_UAUA(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a integer dense (fully connected) layer - * for UAUA per channel quantized scheme - * @ingroup layers_dense - * @param layer the dense layer - */ -AI_INTERNAL_API -void forward_dense_integer_UAUA_ch(ai_layer *pLayer); - -AI_API_DECLARE_END - -#endif /*LAYERS_CONV2D_H*/ +/** + ****************************************************************************** + * @file layers_conv2d.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform conv2d layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_CONV2D_H +#define LAYERS_CONV2D_H + +#include "layers_nl.h" +#include "layers_pool.h" + + + + +#define AI_LAYER_CONV2D_FIELDS_DECLARE \ + AI_LAYER_COMMON_FIELDS_DECLARE \ + ai_u32 groups; /*!< groups for separable convolution */ \ + AI_CONST ai_array* nl_params; /*!< array pointer to non linear parameters */ \ + ai_handle nl_func; /*!< function pointer to non linear transform */ \ + ai_shape_2d filter_stride; /*!< filter stride, how much the filter moves */ \ + ai_shape_2d dilation; /*!< dilation value along axis of the filter */ \ + ai_shape filter_pad; /*!< filter pad 4d */ \ + ai_layer_format_type in_ch_format; /*!< Input format (Channel 1st vs Channel last */ \ + ai_layer_format_type out_ch_format; /*!< Output format (Channel 1st vs Channel last */ + + + +/*! + * @defgroup layers_conv2d Convolutive Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_dense + * @ingroup layers_conv2d + * @brief Dense (fully connected) layer + */ +typedef ai_layer_base ai_layer_dense; + +/*! + * @struct ai_layer_gemm + * @ingroup layers_conv2d + * @brief layer for General Matrix Multiplication + * + * Layer for General Matrix Multiplication (GEMM): + * \f{equation}{ Y = \alpha A \cdot B + \beta C \f} + * \f$\alpha\f$ and \f$\beta\f$ are paramaters, A and B are matrices, + * C is a matrix or an array. Size checks for A, B, C, and Y are performed and + * broadcast is applied on C if necessary. + * This is a sequential layer (see @ref ai_layer). + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_gemm_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_float alpha; /*!< alpha coefficient */ + ai_float beta; /*!< beta coefficient */ + ai_u8 tA; /*!< transpose A flag */ + ai_u8 tB; /*!< transpose B flag */ +} ai_layer_gemm; + +/*! + * @struct ai_layer_conv2d + * @ingroup layers_conv2d + * @brief 2D convolutional layer with strides and pads + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_conv2d_ { + AI_LAYER_CONV2D_FIELDS_DECLARE +} ai_layer_conv2d; + +/*! + * @struct ai_layer_conv2d_nl_pool + * @ingroup layers_conv2d + * @brief 2D convolutional layer + nl + pooling with strides and pads + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_conv2d_nl_pool_ { + AI_LAYER_CONV2D_FIELDS_DECLARE + + ai_shape_2d pool_size; /*!< pooling size */ + ai_shape_2d pool_stride; /*!< pooling stride */ + ai_shape pool_pad; /*!< pooling pad */ + + ai_handle pool_func; /*!< function pointer to pooling transform */ +} ai_layer_conv2d_nl_pool; + + +/* +AI_INTERNAL_API +void ai_dict8_dot_array_f32(ai_handle out, ai_ptr_const data0, ai_ptr_const lut, + const ai_float* data1, const ai_size data_size); + +AI_INTERNAL_API +void ai_dict4_dot_array_f32(ai_handle out, ai_ptr_const data0, ai_ptr_const lut, + const ai_float* data1, const ai_size data_size); +*/ + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Computes the activations of a floating point 32 2D convolutional layer. + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_if32of32wf32(ai_layer* layer); + +/*! + * @brief Computes the activations of a floating point 32 2D dw layer. + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_if32of32wf32(ai_layer* layer); + +/*! + * @brief Computes the activations of a floating point 32 2D convolutional group layer. + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_if32of32wf32_group(ai_layer* layer); + +/*! + * @brief Computes the activations of a 2D floating point 32 pool fused convolutional layer. + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_if32of32wf32_nl_pool(ai_layer* layer); + +/*! + * @brief Computes the activations of a 2D floating point 32 pool fused dw layer. + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_if32of32wf32_nl_pool(ai_layer* layer); + +/*! + * @brief Computes the activations of a 2D floating point 32 pool fused convolutional group layer. + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_if32of32wf32_group_nl_pool(ai_layer* layer); + +/*! + * @brief Computes the activations of a GEMM layer. + * @ingroup layers + * @param layer the layer including output and input tensors + */ +AI_INTERNAL_API +void forward_gemm(ai_layer* layer); + +/*! + * @brief Computes matmul layer, intended as numpy.matmul(A,B). + * @ingroup layers + * @param layer the layer including output and input tensors + */ +AI_INTERNAL_API +void forward_matmul(ai_layer* layer); + +/*! + * @brief Computes the activations of a dense (fully connected) layer. + * @ingroup layers_conv2d + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense(ai_layer* layer); + + +/*! + * @brief Computes the activations of a fixed point 2D convolutional layer. + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_fixed(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a fixed point @ref ai_layer_conv2d_nl_pool + * layer. + * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear + * layer + optional pooling / nonlinearity (average, max) + * @ingroup layers_conv2d + * @param layer see @ai_layer_conv2d_nl_pool + */ +AI_INTERNAL_API +void forward_conv2d_nl_pool_fixed(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer quantized 2D convolutional layer. + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_integer(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer quantized 2D convolutional layer + * for SSSA per layer quantized scheme + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_integer_SSSA(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer quantized 2D convolutional layer + * for SSSA per channel quantized scheme + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_is8os8ws8_sssa_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized DW layer + * for SSSA per channel quantized scheme + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized DW layer + * for SSSA per channel quantized scheme, with 3x3 kernels + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_3x3_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized DW layer + * for SSSA per channel quantized scheme, with 3x3 kernels and input are + * channel first + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_3x3_ch1st_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized DW layer + * for SSSA per channel quantized scheme with depth multiplier > 1 + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_dm_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of int8 quantized DW layers. + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_all_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized PW layer + * for SSSA per channel quantized scheme + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_pw_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized dilated Conv2d layer + * for SSSA per channel quantized scheme (valid padding) + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_dilated_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 non dilated Conv2d layer + * for SSSA per channel quantized scheme (valid padding) + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_deep_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 non dilated Conv2d layer + * for SSSA per channel quantized scheme (valid padding) + * number of output channel is greater than 8 + * Kernels shall be 3x3 and stride is (1,1) + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_deep_3x3_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 non dilated Conv2d layer + * for SSSA per channel quantized scheme (valid or same padding) + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized Conv2d layer + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_all_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized RGB Conv2d layer + * for SSSA per channel quantized scheme + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_rgb_sssa8_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized DW layer + * for SSSA per channel quantized scheme with pooling fused + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_sssa8_ch_nl_pool(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized DW layer + * for SSSA per channel quantized scheme, with 3x3 kernels, + * with pooling fused + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_3x3_sssa8_ch_nl_pool(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized DW layer + * for SSSA per channel quantized scheme, with 3x3 kernels, + * with pooling fused + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_3x3_ch1st_sssa8_ch_nl_pool(ai_layer *pLayer); + + +/*! + * @brief Computes the activations of a int8 quantized DW layer + * for SSSA per channel quantized scheme with depth multiplier > 1 + * with pooling fused + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_dm_sssa8_ch_nl_pool(ai_layer *pLayer); + +/*! + * @brief Computes the activations of int8 quantized DW layers, with pooling fused + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_all_sssa8_ch_nl_pool(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized PW layer, + * with pooling fused + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_pw_sssa8_ch_nl_pool(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized dilated Conv2d layer + * for SSSA per channel quantized scheme (valid padding) and pooling fused + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_dilated_sssa8_ch_nl_pool(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized non dilated Conv2d layer + * for SSSA per channel quantized scheme (valid padding) and pooling fused + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_deep_sssa8_ch_nl_pool(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 non dilated Conv2d layer + * for SSSA per channel quantized scheme (valid padding) and pooling fused + * number of output channel is greater than 8 + * Kernels shall be 3x3 and stride is (1,1) + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_deep_3x3_sssa8_ch_nl_pool(ai_layer *pLayer); + + +/*! + * @brief Computes the activations of a int8 quantized non dilated Conv2d layer + * for SSSA per channel quantized scheme (valid or same padding) and pooling fused + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_sssa8_ch_nl_pool(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a int8 quantized Conv2d layer and pooling fused + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_all_sssa8_ch_nl_pool(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer quantized 2D convolutional layer + * for SSUA per layer quantized scheme + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_integer_SSUA(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer quantized 2D convolutional layer + * for SSUA per channel quantized scheme + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_integer_SSUA_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer quantized 2D convolutional layer + * for UAUA per layer quantized scheme + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_integer_UAUA(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer quantized 2D convolutional layer + * for UAUA per channel quantized scheme + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_integer_UAUA_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer @ref ai_layer_conv2d_nl_pool layer. + * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear + * layer + optional pooling / nonlinearity (average, max) + * @ingroup layers_conv2d + * @param layer see @ai_layer_conv2d_nl_pool + */ +AI_INTERNAL_API +void forward_conv2d_nl_pool_integer(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer @ref ai_layer_conv2d_nl_pool layer + * for SSSA per layer quantized scheme + * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear + * layer + optional pooling / nonlinearity (average, max) + * @ingroup layers_conv2d + * @param layer see @ai_layer_conv2d_nl_pool + */ +AI_INTERNAL_API +void forward_conv2d_nl_pool_integer_SSSA(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer @ref ai_layer_conv2d_nl_pool layer + * for SSSA per channel quantized scheme + * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear + * layer + optional pooling / nonlinearity (average, max) + * @ingroup layers_conv2d + * @param layer see @ai_layer_conv2d_nl_pool + */ +AI_INTERNAL_API +void forward_conv2d_nl_pool_integer_SSSA_ch(ai_layer *pLayer); + + +/*! + * @brief Computes the activations of a integer @ref ai_layer_conv2d_nl_pool layer + * for SSUA per layer quantized scheme + * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear + * layer + optional pooling / nonlinearity (average, max) + * @ingroup layers_conv2d + * @param layer see @ai_layer_conv2d_nl_pool + */ +AI_INTERNAL_API +void forward_conv2d_nl_pool_integer_SSUA(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer @ref ai_layer_conv2d_nl_pool layer + * for SSUA per channel quantized scheme + * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear + * layer + optional pooling / nonlinearity (average, max) + * @ingroup layers_conv2d + * @param layer see @ai_layer_conv2d_nl_pool + */ +AI_INTERNAL_API +void forward_conv2d_nl_pool_integer_SSUA_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer @ref ai_layer_conv2d_nl_pool layer + * for UAUA per layer quantized scheme + * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear + * layer + optional pooling / nonlinearity (average, max) + * @ingroup layers_conv2d + * @param layer see @ai_layer_conv2d_nl_pool + */ +AI_INTERNAL_API +void forward_conv2d_nl_pool_integer_UAUA(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer @ref ai_layer_conv2d_nl_pool layer + * for UAUA per channel quantized scheme + * The @ref ai_layer_conv2d_nl_pool is a fused conv2D + optional nonlinear + * layer + optional pooling / nonlinearity (average, max) + * @ingroup layers_conv2d + * @param layer see @ai_layer_conv2d_nl_pool + */ +AI_INTERNAL_API +void forward_conv2d_nl_pool_integer_UAUA_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer. + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_integer(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer + * for SSSA per layer quantized scheme + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_integer_SSSA(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer + * for SSSA per channel quantized scheme + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_integer_SSSA_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer + * for SSUA per layer quantized scheme + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_integer_SSUA(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer + * for SSUA per channel quantized scheme + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_integer_SSUA_ch(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer + * for UAUA per layer quantized scheme + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_integer_UAUA(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer dense (fully connected) layer + * for UAUA per channel quantized scheme + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_integer_UAUA_ch(ai_layer *pLayer); + +AI_API_DECLARE_END + +#endif /*LAYERS_CONV2D_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_conv2d_dqnn.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_conv2d_dqnn.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_conv2d_dqnn.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_conv2d_dqnn.h index 96ab8ed5..411eea77 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_conv2d_dqnn.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_conv2d_dqnn.h @@ -1,488 +1,488 @@ -/** - ****************************************************************************** - * @file layers_conv2d_dqnn.h - * @author AIS - * @brief header file of AI platform DQNN conv datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LAYERS_CONV2D_DQNN_H -#define LAYERS_CONV2D_DQNN_H - -#include "layers_common.h" -#include "layers_conv2d.h" - -/*! - * @defgroup layers_conv2d_dqnn Layers Definitions - * @brief definition - * - */ - -AI_API_DECLARE_BEGIN - - -#define AI_DQNN_PAD_1_KEY (1) -#define AI_DQNN_PAD_M1_KEY (-1) -#define AI_DQNN_PAD_0_KEY (0) -#define AI_DQNN_PAD_1_VALUE (0x0) -#define AI_DQNN_PAD_M1_VALUE (0xFFFFFFFF) -#define AI_DQNN_PAD_0_VALUE (0x2) - - -/*! - * @struct ai_layer_conv2d_dqnn - * @ingroup layers_conv2d_dqnn - * @brief conv2d_dqnn layer - * - * @ref forward_conv2d_is1os1ws1 - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_conv2d_dqnn_ { - AI_LAYER_CONV2D_FIELDS_DECLARE - ai_i32 pad_value; -} ai_layer_conv2d_dqnn; - - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Handles point wise convolution with binary input, binary output and - * binary weights - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_pw_is1os1ws1_bn(ai_layer *pLayer); - -/*! - * @brief Handles point wise convolution with binary input, binary output and - * binary weights - Optimized thanks to Optim2 assumptions - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_pw_is1os1ws1_bn_optim2(ai_layer *pLayer); - -/*! - * @brief Handles point wise convolution with binary input, 8-bits output and - * binary weights - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_pw_is1os8ws1_bn(ai_layer *pLayer); - -/*! - * @brief Handles point wise convolution with binary input, 8-bits output and - * binary weights - Optimized thanks to Optim1 assumptions - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_pw_is1os8ws1_bn_optim1(ai_layer *pLayer); - -/*! - * @brief Handles point-wise convolution with binary input, float32 output - * and binary weights - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_pw_is1of32ws1_bn(ai_layer *pLayer); - -/*! - * @brief Handles point-wise convolution with binary input, float32 output - * and binary weights - Optimized thanks to Optim1 assumptions - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_pw_is1of32ws1_bn_optim1(ai_layer *pLayer); - -/*! - * @brief Handles 2D convolution with binary input, binary output and - * binary weights - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_conv2d_is1os1ws1_bn(ai_layer *pLayer); - -/*! - * @brief Handles 2D convolution with binary input, binary output and - * binary weights - Optimized thanks to Optim2 assumptions - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_conv2d_is1os1ws1_bn_optim2(ai_layer *pLayer); - -/*! - * @brief Handles 2D convolution with binary input, 8-bits output and - * binary weights - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_conv2d_is1os8ws1_bn(ai_layer *pLayer); - -/*! - * @brief Handles 2D convolution with binary input, 8-bits output and - * binary weights - Optimized thanks to Optim1 assumptions - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_conv2d_is1os8ws1_bn_optim1(ai_layer *pLayer); - -/*! - * @brief Handles 2D convolution with binary input, binary output and - * binary weights - with 0 padding (QKeras like) - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_conv2d_is1os1ws1_bn_pad0(ai_layer *pLayer); - -/*! - * @brief Handles 2D convolution with binary input, binary output and - * binary weights - with 0 padding (QKeras like) - Optimized thanks to - * Optim0 assumptions - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_conv2d_is1os1ws1_bn_pad0_optim0(ai_layer *pLayer); - -/*! - * @brief Handles 2D convolution with binary input, 8-bits output and - * binary weights - with 0 padding (QKeras like) - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_conv2d_is1os8ws1_bn_pad0(ai_layer *pLayer); - -/*! - * @brief Handles 2D convolution with binary input, binary output and - * binary weights - with +1/-1 padding (Larq like) - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_conv2d_is1os1ws1_bn_pad1(ai_layer *pLayer); - -/*! - * @brief Handles 2D convolution with binary input, binary output and - * binary weights - with +1/-1 padding (Larq like) - Optimized thanks - * to Optim2 assumptions - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_conv2d_is1os1ws1_bn_pad1_optim2(ai_layer *pLayer); - -/*! - * @brief Handles 2D convolution with binary input, 8-bits output and - * binary weights - with +1/-1 padding (Larq like) - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_conv2d_is1os8ws1_bn_pad1(ai_layer *pLayer); - -/*! - * @brief Handles 2D convolution with binary input, 8-bits output and - * binary weights - with +1/-1 padding (Larq like) - Optimized thanks - * to Optim1 assumptions - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_conv2d_is1os8ws1_bn_pad1_optim1(ai_layer *pLayer); - -/*! - * @brief Handles 2D convolution with 8-bits quantized Input and weights and - * binary output - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_conv2d_is8os1ws8(ai_layer *pLayer); - -/*! - * @brief Handles 2D convolution with 8-bits quantized Input and weights and - * binary output - Optimized thanks to Optim2 assumptions - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_conv2d_is8os1ws8_optim2(ai_layer *pLayer); - -/*! - * @brief Handles 2D convolution with 8-bits quantized Input and weights and - * binary output - quantized with DoReFa SotA quantizer - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_conv2d_dorefa_is8os1ws8(ai_layer *pLayer); - -/*! - * @brief Handles 2D convolution with 16-bits quantized input, binary weights - and binary output - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_conv2d_is16os1ws1_bn_fxp(ai_layer *pLayer); - -/*! - * @brief Handles 2D convolution with 16-bits quantized input, binary weights - and 16-bits quantized output - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_conv2d_is16os16ws1_fxp(ai_layer *pLayer); - -/*! - * @brief Handles depth-wise convolution with binary input, binary output and - * binary weights - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_dw_is1os1ws1_bn(ai_layer *pLayer); - -/*! - * @brief Handles depth-wise convolution with binary input, binary output and - * binary weights - Optimized thanks to Optim3 assumptions - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_dw_is1os1ws1_bn_optim3(ai_layer *pLayer); - -/*! - * @brief Handles depth-wise convolution with binary input, binary output and - * binary weights - with 0 padding (QKeras like) - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_dw_is1os1ws1_bn_pad0(ai_layer *pLayer); - -/*! - * @brief Handles depth-wise convolution with binary input, binary output and - * binary weights - with 0 padding (QKeras like) - Optimized thanks to - * Optim3 assumptions - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_dw_is1os1ws1_bn_pad0_optim3(ai_layer *pLayer); - -/*! - * @brief Handles depth-wise convolution with binary input, binary output and - * binary weights - with +1/-1 padding (Larq like) - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_dw_is1os1ws1_bn_pad1(ai_layer *pLayer); - -/*! - * @brief Handles depth-wise convolution with binary input, binary output and - * binary weights - with +1/-1 padding (Larq like) - Optimized thanks to - * Optim3 assumptions - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_dw_is1os1ws1_bn_pad1_optim3(ai_layer *pLayer); - -/*! - * @brief Handles 2D convolution with 8-bits quantized Input and output and - * binary weights - * @ingroup layers_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -AI_INTERNAL_API -void forward_conv2d_is8os8ws1(ai_layer *pLayer); - -/** - * @brief Handles 2D convolution with binary input, fixed point 16-bits output and - * binary weights - with 0 padding (QKeras like) - Lite I/F - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_is1os16ws1_bn_pad0_fxp(ai_layer *pLayer); - -/*! - * @brief Handles 2D convolution with binary input, fixed point 16-bits output and - * binary weights - with +1/-1 padding (Larq like) - Lite I/F - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_is1os16ws1_bn_pad1_fxp(ai_layer *pLayer); - -/*! - * @brief Handles 2D convolution with binary input, fixed point 16-bits output and - * binary weights - with +1/-1 padding (Larq like) - Lite I/F - * - Optimized thanks to Optim1 assumptions - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_is1os16ws1_bn_pad1_optim1_fxp(ai_layer *pLayer); - -/*! - * @brief Handles 2D convolution with binary input, fixed point 16-bits unsigned output and - * binary weights - with 0 padding (QKeras like) - Lite I/F - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_is1ou16ws1_bn_pad0_fxp(ai_layer *pLayer); - -/*! - * @brief Handles 2D convolution with binary input, fixed point 16-bits unsigned output and - * binary weights - with +1/-1 padding (Larq like) - Lite I/F - * @ingroup lite_conv2d_dqnn - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_is1ou16ws1_bn_pad1_fxp(ai_layer *pLayer); - -/*! - * @brief Handles 2D convolution with binary input, fixed point 16-bits unsiged output and - * binary weights - with +1/-1 padding (Larq like) - Lite I/F - * - Optimized thanks to Optim1 assumptions - * @ingroup lite_conv2d_dqnn - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_is1ou16ws1_bn_pad1_optim1_fxp(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a integer quantized 2D convolutional layer - * for SSSA per channel quantized RGB scheme using n_channel_in = 3 - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_conv2d_is8os8ws8_sssa_ch_rgb(const ai_i8 *pData_in, - ai_i8 *pData_out, - const ai_i8 *pWeights, - const ai_i32 *pBias, - ai_u16 *pBuffer_a, - const ai_size width_in, - const ai_size height_in, - const ai_size width_out, - const ai_size height_out, - const ai_u16 n_channel_in, - const ai_u16 n_channel_out, - const ai_size filt_width, - const ai_size filt_height, - const ai_u16 filt_pad_x, - const ai_u16 filt_pad_y, - const ai_u16 filt_stride_x, - const ai_u16 filt_stride_y, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - const ai_i8 in_zeropoint, - const ai_i8 out_zeropoint, - const ai_bool out_ch_format, - ai_i16 *p_out_r_shift, - ai_i32 *p_out_factor); - -/*! - * @brief Computes the activations of a point-wise integer quantized convolution - for SSSA per channel quantized scheme - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_pw_is8os8ws8_sssa_ch(const ai_i8 *pData_in, - ai_i8 *pData_out, - const ai_i8 *pWeights, - const ai_i32 *pBias, - ai_u16 *pBuffer_a, - const ai_size width_in, - const ai_size height_in, - const ai_size width_out, - const ai_size height_out, - const ai_u16 n_channel_in, - const ai_u16 n_channel_out, - const ai_size filt_width, - const ai_size filt_height, - const ai_u16 filt_pad_x, - const ai_u16 filt_pad_y, - const ai_u16 filt_stride_x, - const ai_u16 filt_stride_y, - const ai_u16 dilation_x, - const ai_u16 dilation_y, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - const ai_i8 in_zeropoint, - const ai_i8 out_zeropoint, - ai_i16 *p_out_r_shift, - ai_i32 *p_out_factor, - ai_i32 AI_PWOverlay, - ai_i16 *bufferA, - ai_i32 scratch_size); - // st_nn_context_t context); - -/*! - * @brief Computes the activations of a depth-wise integer quantized convolution - for SSSA per channel quantized scheme - * @ingroup layers_conv2d - * @param layer the convolutional (conv) layer - */ -AI_INTERNAL_API -void forward_dw_is8os8ws8_sssa_ch(const ai_i8 *pData_in, - ai_i8 *pData_out, - const ai_i8 *pWeights, - const ai_i32 *pBias, - ai_u16 *pBuffer_a, - const ai_size width_in, - const ai_size height_in, - const ai_size width_out, - const ai_size height_out, - const ai_u16 n_channel_in, - const ai_u16 n_channel_out, - const ai_size filt_width, - const ai_size filt_height, - const ai_u16 filt_pad_x, - const ai_u16 filt_pad_y, - const ai_u16 filt_stride_x, - const ai_u16 filt_stride_y, - const ai_u16 dilation_x, - const ai_u16 dilation_y, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - const ai_i8 in_zeropoint, - const ai_i8 out_zeropoint, - ai_i16 *p_out_r_shift, - ai_i32 *p_out_factor); - - -AI_API_DECLARE_END - -#endif /*LAYERS_CONV2D_DQNN_H*/ +/** + ****************************************************************************** + * @file layers_conv2d_dqnn.h + * @author AIS + * @brief header file of AI platform DQNN conv datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_CONV2D_DQNN_H +#define LAYERS_CONV2D_DQNN_H + +#include "layers_common.h" +#include "layers_conv2d.h" + +/*! + * @defgroup layers_conv2d_dqnn Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + + +#define AI_DQNN_PAD_1_KEY (1) +#define AI_DQNN_PAD_M1_KEY (-1) +#define AI_DQNN_PAD_0_KEY (0) +#define AI_DQNN_PAD_1_VALUE (0x0) +#define AI_DQNN_PAD_M1_VALUE (0xFFFFFFFF) +#define AI_DQNN_PAD_0_VALUE (0x2) + + +/*! + * @struct ai_layer_conv2d_dqnn + * @ingroup layers_conv2d_dqnn + * @brief conv2d_dqnn layer + * + * @ref forward_conv2d_is1os1ws1 + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_conv2d_dqnn_ { + AI_LAYER_CONV2D_FIELDS_DECLARE + ai_i32 pad_value; +} ai_layer_conv2d_dqnn; + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles point wise convolution with binary input, binary output and + * binary weights + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_pw_is1os1ws1_bn(ai_layer *pLayer); + +/*! + * @brief Handles point wise convolution with binary input, binary output and + * binary weights - Optimized thanks to Optim2 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_pw_is1os1ws1_bn_optim2(ai_layer *pLayer); + +/*! + * @brief Handles point wise convolution with binary input, 8-bits output and + * binary weights + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_pw_is1os8ws1_bn(ai_layer *pLayer); + +/*! + * @brief Handles point wise convolution with binary input, 8-bits output and + * binary weights - Optimized thanks to Optim1 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_pw_is1os8ws1_bn_optim1(ai_layer *pLayer); + +/*! + * @brief Handles point-wise convolution with binary input, float32 output + * and binary weights + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_pw_is1of32ws1_bn(ai_layer *pLayer); + +/*! + * @brief Handles point-wise convolution with binary input, float32 output + * and binary weights - Optimized thanks to Optim1 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_pw_is1of32ws1_bn_optim1(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os1ws1_bn(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - Optimized thanks to Optim2 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os1ws1_bn_optim2(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, 8-bits output and + * binary weights + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os8ws1_bn(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, 8-bits output and + * binary weights - Optimized thanks to Optim1 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os8ws1_bn_optim1(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with 0 padding (QKeras like) + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os1ws1_bn_pad0(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with 0 padding (QKeras like) - Optimized thanks to + * Optim0 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os1ws1_bn_pad0_optim0(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, 8-bits output and + * binary weights - with 0 padding (QKeras like) + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os8ws1_bn_pad0(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with +1/-1 padding (Larq like) + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os1ws1_bn_pad1(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with +1/-1 padding (Larq like) - Optimized thanks + * to Optim2 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os1ws1_bn_pad1_optim2(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, 8-bits output and + * binary weights - with +1/-1 padding (Larq like) + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os8ws1_bn_pad1(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, 8-bits output and + * binary weights - with +1/-1 padding (Larq like) - Optimized thanks + * to Optim1 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os8ws1_bn_pad1_optim1(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with 8-bits quantized Input and weights and + * binary output + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is8os1ws8(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with 8-bits quantized Input and weights and + * binary output - Optimized thanks to Optim2 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is8os1ws8_optim2(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with 8-bits quantized Input and weights and + * binary output - quantized with DoReFa SotA quantizer + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_dorefa_is8os1ws8(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with 16-bits quantized input, binary weights + and binary output + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is16os1ws1_bn_fxp(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with 16-bits quantized input, binary weights + and 16-bits quantized output + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is16os16ws1_fxp(ai_layer *pLayer); + +/*! + * @brief Handles depth-wise convolution with binary input, binary output and + * binary weights + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_dw_is1os1ws1_bn(ai_layer *pLayer); + +/*! + * @brief Handles depth-wise convolution with binary input, binary output and + * binary weights - Optimized thanks to Optim3 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_dw_is1os1ws1_bn_optim3(ai_layer *pLayer); + +/*! + * @brief Handles depth-wise convolution with binary input, binary output and + * binary weights - with 0 padding (QKeras like) + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_dw_is1os1ws1_bn_pad0(ai_layer *pLayer); + +/*! + * @brief Handles depth-wise convolution with binary input, binary output and + * binary weights - with 0 padding (QKeras like) - Optimized thanks to + * Optim3 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_dw_is1os1ws1_bn_pad0_optim3(ai_layer *pLayer); + +/*! + * @brief Handles depth-wise convolution with binary input, binary output and + * binary weights - with +1/-1 padding (Larq like) + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_dw_is1os1ws1_bn_pad1(ai_layer *pLayer); + +/*! + * @brief Handles depth-wise convolution with binary input, binary output and + * binary weights - with +1/-1 padding (Larq like) - Optimized thanks to + * Optim3 assumptions + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_dw_is1os1ws1_bn_pad1_optim3(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with 8-bits quantized Input and output and + * binary weights + * @ingroup layers_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +AI_INTERNAL_API +void forward_conv2d_is8os8ws1(ai_layer *pLayer); + +/** + * @brief Handles 2D convolution with binary input, fixed point 16-bits output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os16ws1_bn_pad0_fxp(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, fixed point 16-bits output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os16ws1_bn_pad1_fxp(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, fixed point 16-bits output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * - Optimized thanks to Optim1 assumptions + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_is1os16ws1_bn_pad1_optim1_fxp(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, fixed point 16-bits unsigned output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_is1ou16ws1_bn_pad0_fxp(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, fixed point 16-bits unsigned output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * @ingroup lite_conv2d_dqnn + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_is1ou16ws1_bn_pad1_fxp(ai_layer *pLayer); + +/*! + * @brief Handles 2D convolution with binary input, fixed point 16-bits unsiged output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * - Optimized thanks to Optim1 assumptions + * @ingroup lite_conv2d_dqnn + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_is1ou16ws1_bn_pad1_optim1_fxp(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer quantized 2D convolutional layer + * for SSSA per channel quantized RGB scheme using n_channel_in = 3 + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_conv2d_is8os8ws8_sssa_ch_rgb(const ai_i8 *pData_in, + ai_i8 *pData_out, + const ai_i8 *pWeights, + const ai_i32 *pBias, + ai_u16 *pBuffer_a, + const ai_size width_in, + const ai_size height_in, + const ai_size width_out, + const ai_size height_out, + const ai_u16 n_channel_in, + const ai_u16 n_channel_out, + const ai_size filt_width, + const ai_size filt_height, + const ai_u16 filt_pad_x, + const ai_u16 filt_pad_y, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_bool out_ch_format, + ai_i16 *p_out_r_shift, + ai_i32 *p_out_factor); + +/*! + * @brief Computes the activations of a point-wise integer quantized convolution + for SSSA per channel quantized scheme + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_pw_is8os8ws8_sssa_ch(const ai_i8 *pData_in, + ai_i8 *pData_out, + const ai_i8 *pWeights, + const ai_i32 *pBias, + ai_u16 *pBuffer_a, + const ai_size width_in, + const ai_size height_in, + const ai_size width_out, + const ai_size height_out, + const ai_u16 n_channel_in, + const ai_u16 n_channel_out, + const ai_size filt_width, + const ai_size filt_height, + const ai_u16 filt_pad_x, + const ai_u16 filt_pad_y, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_u16 dilation_x, + const ai_u16 dilation_y, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + ai_i16 *p_out_r_shift, + ai_i32 *p_out_factor, + ai_i32 AI_PWOverlay, + ai_i16 *bufferA, + ai_i32 scratch_size); + // st_nn_context_t context); + +/*! + * @brief Computes the activations of a depth-wise integer quantized convolution + for SSSA per channel quantized scheme + * @ingroup layers_conv2d + * @param layer the convolutional (conv) layer + */ +AI_INTERNAL_API +void forward_dw_is8os8ws8_sssa_ch(const ai_i8 *pData_in, + ai_i8 *pData_out, + const ai_i8 *pWeights, + const ai_i32 *pBias, + ai_u16 *pBuffer_a, + const ai_size width_in, + const ai_size height_in, + const ai_size width_out, + const ai_size height_out, + const ai_u16 n_channel_in, + const ai_u16 n_channel_out, + const ai_size filt_width, + const ai_size filt_height, + const ai_u16 filt_pad_x, + const ai_u16 filt_pad_y, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_u16 dilation_x, + const ai_u16 dilation_y, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + ai_i16 *p_out_r_shift, + ai_i32 *p_out_factor); + + +AI_API_DECLARE_END + +#endif /*LAYERS_CONV2D_DQNN_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_custom.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_custom.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_custom.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_custom.h index 675db622..5abde392 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_custom.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_custom.h @@ -1,41 +1,41 @@ -#ifndef LAYERS_CUSTOM_H -#define LAYERS_CUSTOM_H -/** - ****************************************************************************** - * @file layers_custom.h - * @author STMicroelectronics - * @brief header file of AI platform custom layers datatype - ****************************************************************************** - * @attention - * - * Copyright (c) 2020 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#include "layers_common.h" - -/*! - * @defgroup layers_custom Custom layer definitions - * @brief Definition of structures custom layers - */ - -AI_API_DECLARE_BEGIN - -/*! - * @struct ai_layer_custom - * @ingroup layers_custom - * @brief Custom layer wrapper - * - * The custom layer wrapper - */ -typedef ai_layer_stateful ai_layer_custom; - - -AI_API_DECLARE_END - -#endif /* LAYERS_CUSTOM_H */ +#ifndef LAYERS_CUSTOM_H +#define LAYERS_CUSTOM_H +/** + ****************************************************************************** + * @file layers_custom.h + * @author STMicroelectronics + * @brief header file of AI platform custom layers datatype + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#include "layers_common.h" + +/*! + * @defgroup layers_custom Custom layer definitions + * @brief Definition of structures custom layers + */ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_custom + * @ingroup layers_custom + * @brief Custom layer wrapper + * + * The custom layer wrapper + */ +typedef ai_layer_stateful ai_layer_custom; + + +AI_API_DECLARE_END + +#endif /* LAYERS_CUSTOM_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_dense.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_dense.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_dense.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_dense.h index 9833afca..28086914 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_dense.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_dense.h @@ -1,43 +1,43 @@ -#ifndef LAYERS_DENSE_H -#define LAYERS_DENSE_H -/** - ****************************************************************************** - * @file layers_dense.h - * @author AST Embedded Analytics Research Platform - * @brief header file of AI platform dense layers datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2018 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -#include "layers_common.h" - - -/*! - * @defgroup layers Normalization Layers Definitions - * @brief definition - * - */ - -AI_API_DECLARE_BEGIN - -/*! - * @brief Computes the activations of a fixed point dense (fully connected) layer. - * @ingroup layers_dense - * @param layer the dense layer - */ -AI_INTERNAL_API -void forward_dense_fixed(ai_layer *pLayer); - -AI_API_DECLARE_END - -#endif /*LAYERS_DENSE_H*/ - +#ifndef LAYERS_DENSE_H +#define LAYERS_DENSE_H +/** + ****************************************************************************** + * @file layers_dense.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform dense layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#include "layers_common.h" + + +/*! + * @defgroup layers Normalization Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @brief Computes the activations of a fixed point dense (fully connected) layer. + * @ingroup layers_dense + * @param layer the dense layer + */ +AI_INTERNAL_API +void forward_dense_fixed(ai_layer *pLayer); + +AI_API_DECLARE_END + +#endif /*LAYERS_DENSE_H*/ + diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_dense_dqnn.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_dense_dqnn.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_dense_dqnn.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_dense_dqnn.h index 44a8a561..6ff4638d 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_dense_dqnn.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_dense_dqnn.h @@ -1,394 +1,394 @@ -/** - ****************************************************************************** - * @file layers_dense_dqnn.h - * @author AST Embedded Analytics Research Platform - * @brief header file of deeply quantized dense layers. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LAYERS_DENSE_DQNN_H -#define LAYERS_DENSE_DQNN_H - -#include "layers_common.h" - -/*! - * @defgroup layers_dense_dqnn Quantized Dense Layers definition. - * @brief Implements the kernels and the forward functions to implement - * dense layers with quantized inputs, weights, or outputs. - */ - -AI_API_DECLARE_BEGIN - -/*! - * @struct ai_layer_dense_dqnn - * @ingroup layers_dense_dqnn - * @brief Specific instance of deeply quantized dense layers. - */ -typedef ai_layer_base ai_layer_dense_dqnn; - -/*****************************************************************************/ -/* Forward Functions Section */ -/*****************************************************************************/ - -/*! - * @brief Forward function for a dense layer with signed binary input, - * signed binary output, and signed binary weights. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is1os1ws1(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed binary input, - * signed binary output, and signed binary weights. - * The BN is fused, i.e., the layer requires weights, scale, and offset, where - * weights are those of the dense layer, scale is that of the BN, and the offset - * corresponds to dense bias * bn scale + bn offset. If the parameters do not - * agree with such convention, the behavior is undefined. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is1os1ws1_bn(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed binary input, - * 8-bit signed output, and signed binary weights. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is1os8ws1(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed binary input, - * 8-bit signed output, and signed binary weights. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is1os16ws1(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed binary input, - * 32-bit floating point output, and signed binary weights. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is1of32ws1(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed binary input, - * 32-bit floating point output, and signed binary weights. - * The BN is fused, i.e., the layer requires weights, scale, and offset, where - * weights are those of the dense layer, scale is that of the BN, and the offset - * corresponds to dense bias * bn scale + bn offset. If the parameters do not - * agree with such convention, the behavior is undefined. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is1of32ws1_bn(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed binary input, - * 32-bit floating point output, and 32-bit floating point weights. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is1of32wf32(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed binary input, - * 32-bit floating point output, and 32-bit floating point weights. - * The BN is fused, i.e., the layer requires weights, scale, and offset, where - * weights are those of the dense layer, scale is that of the BN, and the offset - * corresponds to dense bias * bn scale + bn offset. If the parameters do not - * agree with such convention, the behavior is undefined. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is1of32wf32_bn(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed binary input, - * 32-bit floating point output, and 8-bit signed weights. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is1of32ws8(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed binary input, - * 32-bit floating point output, and 8-bit signed weights. - * The BN is fused, i.e., the layer requires weights, scale, and offset, where - * weights are those of the dense layer, scale is that of the BN, and the offset - * corresponds to dense bias * bn scale + bn offset. If the parameters do not - * agree with such convention, the behavior is undefined. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is1of32ws8_bn(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed binary input, - * binary output, and 8-bit signed weights. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is1os1ws8(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed binary input, - * binary output, and 8-bit signed weights. - * The BN is fused, i.e., the layer requires weights, scale, and offset, where - * weights are those of the dense layer, scale is that of the BN, and the offset - * corresponds to dense bias * bn scale + bn offset. If the parameters do not - * agree with such convention, the behavior is undefined. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is1os1ws8_bn(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed binary input, - * 8-bit signed output, and 8-bit signed weights. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is1os8ws8(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed binary input, - * 16-bit signed output, and 8-bit signed weights. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is1os16ws8(ai_layer* layer); - - -/*! - * @brief Forward function for a dense layer with signed 8-bit input, - * float output, and binary weights. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is8of32ws1(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed 8-bit input, - * float output, and binary weights. - * The BN is fused, i.e., the layer requires weights, scale, and offset, where - * weights are those of the dense layer, scale is that of the BN, and the offset - * corresponds to dense bias * bn scale + bn offset. If the parameters do not - * agree with such convention, the behavior is undefined. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is8of32ws1_bn(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed 8-bit input, - * 1-bit signed output, and binary weights. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is8os1ws1(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed 8-bit input, - * 1-bit signed output, and binary weights. - * The BN is fused, i.e., the layer requires weights, scale, and offset, where - * weights are those of the dense layer, scale is that of the BN, and the offset - * corresponds to dense bias * bn scale + bn offset. If the parameters do not - * agree with such convention, the behavior is undefined. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is8os1ws1_bn(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed 8-bit input, - * binary weights and binary output. - * The BN is fused, i.e., the layer requires weights, scale, and offset, where - * weights are those of the dense layer, scale is that of the BN, and the offset - * corresponds to dense bias * bn scale + bn offset. If the parameters do not - * agree with such convention, the behavior is undefined. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is8os1ws1_bn_fxp(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed 8-bit input, - * 8-bit signed output, and binary weights. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is8os8ws1(ai_layer* layer); - - -/*! - * @brief Forward function for a dense layer with signed 8-bit input, - * 16-bit signed output, and binary weights. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is8os16ws1(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed 16-bit input, - * 1-bit signed output, and binary weights. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is16os1ws1(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed 16-bit input, - * 1-bit signed output, and binary weights. - * The BN is fused, i.e., the layer requires weights, scale, and offset, where - * weights are those of the dense layer, scale is that of the BN, and the offset - * corresponds to dense bias * bn scale + bn offset. If the parameters do not - * agree with such convention, the behavior is undefined. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is16os1ws1_bn(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed 16-bit input, - * 8-bit signed output, and binary weights. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is16os8ws1(ai_layer* layer); - - -/*! - * @brief Forward function for a dense layer with signed 16-bit input, - * 16-bit signed output, and binary weights. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is16os16ws1(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed 16-bit input, - * f32 output, and binary weights. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is16of32ws1(ai_layer* layer); - - -/*! - * @brief Forward function for a dense layer with signed 16-bit input, - * f32 output, and binary weights. - * The BN is fused, i.e., the layer requires weights, scale, and offset, where - * weights are those of the dense layer, scale is that of the BN, and the offset - * corresponds to dense bias * bn scale + bn offset. If the parameters do not - * agree with such convention, the behavior is undefined. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_is16of32ws1_bn(ai_layer* layer); - - -/*! - * @brief Forward function for a dense layer with signed f32 input, - * 1-bit signed output, and binary weights. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_if32os1ws1(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed f32 input, - * 1-bit signed output, and binary weights. - * The BN is fused, i.e., the layer requires weights, scale, and offset, where - * weights are those of the dense layer, scale is that of the BN, and the offset - * corresponds to dense bias * bn scale + bn offset. If the parameters do not - * agree with such convention, the behavior is undefined. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_if32os1ws1_bn(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed f32 input, - * 8-bit signed output, and binary weights. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_if32os8ws1(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed f32 input, - * 16-bit signed output, and binary weights. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_if32os16ws1(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed f32 input, - * f32 output, and binary weights. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_if32of32ws1(ai_layer* layer); - -/*! - * @brief Forward function for a dense layer with signed f32 input, - * f32 output, and binary weights. - * The BN is fused, i.e., the layer requires weights, scale, and offset, where - * weights are those of the dense layer, scale is that of the BN, and the offset - * corresponds to dense bias * bn scale + bn offset. If the parameters do not - * agree with such convention, the behavior is undefined. - * @ingroup layers_dense_dqnn - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_dense_if32of32ws1_bn(ai_layer* layer); - -AI_API_DECLARE_END - -#endif /*LAYERS_DENSE_DQNN_H*/ +/** + ****************************************************************************** + * @file layers_dense_dqnn.h + * @author AST Embedded Analytics Research Platform + * @brief header file of deeply quantized dense layers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_DENSE_DQNN_H +#define LAYERS_DENSE_DQNN_H + +#include "layers_common.h" + +/*! + * @defgroup layers_dense_dqnn Quantized Dense Layers definition. + * @brief Implements the kernels and the forward functions to implement + * dense layers with quantized inputs, weights, or outputs. + */ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_dense_dqnn + * @ingroup layers_dense_dqnn + * @brief Specific instance of deeply quantized dense layers. + */ +typedef ai_layer_base ai_layer_dense_dqnn; + +/*****************************************************************************/ +/* Forward Functions Section */ +/*****************************************************************************/ + +/*! + * @brief Forward function for a dense layer with signed binary input, + * signed binary output, and signed binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1os1ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * signed binary output, and signed binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1os1ws1_bn(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * 8-bit signed output, and signed binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1os8ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * 8-bit signed output, and signed binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1os16ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * 32-bit floating point output, and signed binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1of32ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * 32-bit floating point output, and signed binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1of32ws1_bn(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * 32-bit floating point output, and 32-bit floating point weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1of32wf32(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * 32-bit floating point output, and 32-bit floating point weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1of32wf32_bn(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * 32-bit floating point output, and 8-bit signed weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1of32ws8(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * 32-bit floating point output, and 8-bit signed weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1of32ws8_bn(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * binary output, and 8-bit signed weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1os1ws8(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * binary output, and 8-bit signed weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1os1ws8_bn(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * 8-bit signed output, and 8-bit signed weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1os8ws8(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * 16-bit signed output, and 8-bit signed weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is1os16ws8(ai_layer* layer); + + +/*! + * @brief Forward function for a dense layer with signed 8-bit input, + * float output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is8of32ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed 8-bit input, + * float output, and binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is8of32ws1_bn(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed 8-bit input, + * 1-bit signed output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is8os1ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed 8-bit input, + * 1-bit signed output, and binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is8os1ws1_bn(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed 8-bit input, + * binary weights and binary output. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is8os1ws1_bn_fxp(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed 8-bit input, + * 8-bit signed output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is8os8ws1(ai_layer* layer); + + +/*! + * @brief Forward function for a dense layer with signed 8-bit input, + * 16-bit signed output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is8os16ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed 16-bit input, + * 1-bit signed output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is16os1ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed 16-bit input, + * 1-bit signed output, and binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is16os1ws1_bn(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed 16-bit input, + * 8-bit signed output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is16os8ws1(ai_layer* layer); + + +/*! + * @brief Forward function for a dense layer with signed 16-bit input, + * 16-bit signed output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is16os16ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed 16-bit input, + * f32 output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is16of32ws1(ai_layer* layer); + + +/*! + * @brief Forward function for a dense layer with signed 16-bit input, + * f32 output, and binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_is16of32ws1_bn(ai_layer* layer); + + +/*! + * @brief Forward function for a dense layer with signed f32 input, + * 1-bit signed output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_if32os1ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed f32 input, + * 1-bit signed output, and binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_if32os1ws1_bn(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed f32 input, + * 8-bit signed output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_if32os8ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed f32 input, + * 16-bit signed output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_if32os16ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed f32 input, + * f32 output, and binary weights. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_if32of32ws1(ai_layer* layer); + +/*! + * @brief Forward function for a dense layer with signed f32 input, + * f32 output, and binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup layers_dense_dqnn + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_dense_if32of32ws1_bn(ai_layer* layer); + +AI_API_DECLARE_END + +#endif /*LAYERS_DENSE_DQNN_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_formats_converters.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_formats_converters.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_formats_converters.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_formats_converters.h index da0630fb..99ab4df8 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_formats_converters.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_formats_converters.h @@ -1,57 +1,57 @@ -/** - ****************************************************************************** - * @file layers_formats_converters.h - * @author AST Embedded Analytics Research Platform - * @brief header file of formats converters layers - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LAYERS_FORMATS_CONVERTERS_H -#define LAYERS_FORMATS_CONVERTERS_H - -#include "layers_common.h" - -/*! - * @defgroup layers_formats_converters Formats Converters Layers Definition - * @brief this group implements formats converter layers (cast, etc.) - * - */ - -AI_API_DECLARE_BEGIN - -/*! - * @struct ai_layer_cast - * @ingroup layers_formats_converters - * @brief C Implementation of cast layer - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_cast_ { - AI_LAYER_COMMON_FIELDS_DECLARE - ai_array_format to_format; /*!< cast output format */ -} ai_layer_cast; - - -/*****************************************************************************/ -/* Forward Functions Section */ -/*****************************************************************************/ - -/*! - * @brief forward function for cast layer. - * @ingroup layers_ - * @param layer template layer as an opaque pointer - */ -AI_INTERNAL_API -void forward_cast(ai_layer* layer); - - -AI_API_DECLARE_END - -#endif /*LAYERS_FORMATS_CONVERTERS_H*/ +/** + ****************************************************************************** + * @file layers_formats_converters.h + * @author AST Embedded Analytics Research Platform + * @brief header file of formats converters layers + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_FORMATS_CONVERTERS_H +#define LAYERS_FORMATS_CONVERTERS_H + +#include "layers_common.h" + +/*! + * @defgroup layers_formats_converters Formats Converters Layers Definition + * @brief this group implements formats converter layers (cast, etc.) + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_cast + * @ingroup layers_formats_converters + * @brief C Implementation of cast layer + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_cast_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_array_format to_format; /*!< cast output format */ +} ai_layer_cast; + + +/*****************************************************************************/ +/* Forward Functions Section */ +/*****************************************************************************/ + +/*! + * @brief forward function for cast layer. + * @ingroup layers_ + * @param layer template layer as an opaque pointer + */ +AI_INTERNAL_API +void forward_cast(ai_layer* layer); + + +AI_API_DECLARE_END + +#endif /*LAYERS_FORMATS_CONVERTERS_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_generic.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_generic.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_generic.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_generic.h index f5e679d9..f680498e 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_generic.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_generic.h @@ -1,757 +1,757 @@ - -/** - ****************************************************************************** - * @file layers_generic.h - * @author AST Embedded Analytics Research Platform - * @brief header file of AI platform generic layers datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2018 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LAYERS_GENERIC_H -#define LAYERS_GENERIC_H - -#include "layers_common.h" - -typedef enum { - KTfLiteNone = 0, - KTfLiteActRelu, - KTfLiteActRelu1, - KTfLiteActRelu6, - KTfLiteActTanh, - KTfLiteActSignBit, - KTfLiteActSigmoid -} ai_tflitefused_activation; - -/*! - * @defgroup layers_generic Generic Layers Definitions - * @brief definition - * - */ - -AI_API_DECLARE_BEGIN - -/*! - * @struct ai_layer_time_delay - * @ingroup layers_generic - * @brief TimeDelay layer with sparse kernel - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_time_delay_ { - AI_LAYER_COMMON_FIELDS_DECLARE - AI_CONST ai_array* mask; /*!< sparse filter mask */ -} ai_layer_time_delay; - -/*! - * @struct ai_layer_split - * @ingroup layers_generic - * @brief Split layer definition - * - * This layer defines the params of a splitting layer. It is intended to be used - * by his associated forward function @ref forward_split - */ - -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_split_ { - AI_LAYER_COMMON_FIELDS_DECLARE - const ai_i32 outer_elems; - const ai_i32 outer_elems_stride; -} ai_layer_split; - - -/*! - * @struct ai_layer_topK - * @ingroup layers_generic - * @brief topK layer definition - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_topK_{ - AI_LAYER_COMMON_FIELDS_DECLARE - ai_i16 axis; - ai_i16 largest; -} ai_layer_topK; - -typedef AI_ALIGNED_TYPE(struct,4)ai_layer_svdf_{ - AI_LAYER_COMMON_FIELDS_DECLARE - ai_size rank; - ai_tflitefused_activation activation; - -} ai_layer_svdf; - - -/*! - * @struct ai_layer_slice - * @ingroup layers_generic - * @brief Slice layer definition - * - * This layer defines the params of a slicing layer. It is intended to be used - * by his associated forward function @ref forward_slice - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_slice_ { - AI_LAYER_COMMON_FIELDS_DECLARE - AI_CONST ai_array* axes; /*!< Axes that 'starts' and 'ends' apply to. It's optional*/ - AI_CONST ai_array* starts; /*!< Starting indices of corrisponding axis in axes*/ - AI_CONST ai_array* ends; /*!< Ending indices (exclusive) of corrisponding axis in axes*/ -} ai_layer_slice; - -/*! - * @struct ai_layer_gather - * @ingroup layers_generic - * @brief Gather layer definition - * - * This layer defines the params of a gathering layer. It is intended to be used - * by his associated forward function @ref forward_gather - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_gather_ { - AI_LAYER_COMMON_FIELDS_DECLARE - ai_i16 axis; /*!< Which axis to gather on It's optional*/ - ai_tensor* indices; /*!< Indices of corrisponding axis in axes*/ - } ai_layer_gather; - -/*! - * @struct ai_layer_tile - * @ingroup layers generic - * @brief Tile layer definition - * - * This layer defines the param of an tile layer. It constructs a tensor by tiling a - * given tensor. It is intended to be used by its associated forward function - * @ref forward_upsample - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_tile_{ - AI_LAYER_COMMON_FIELDS_DECLARE - AI_CONST ai_array* repeats; /*!< numbers of repeated copies along each dimension */ -} ai_layer_tile; - - -/*! - * @struct ai_layer_shape - * @ingroup layers generic - * @brief Shape layer definition - * - * This layer defines the param of a shape layer. It returns the shape of the - * input tensor. It is intended to be used by its associated forward function - * @ref forward_shape - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_shape_{ - AI_LAYER_COMMON_FIELDS_DECLARE -} ai_layer_shape; - - -/*! - * @struct ai_layer_upsample - * @ingroup layers generic - * @brief Upsample layer definition - * - * This layer defines the param of an upsampling layer. It overloads its params - * to allow zeros upsampling, helpful traspose convolutions, for instance. - * It is intended to be used by its associated forward function @ref forward_upsample - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_upsample_{ - AI_LAYER_COMMON_FIELDS_DECLARE - ai_upsample_mode mode; /*!< upsample mode */ - ai_bool center; /*!< center pixels */ - AI_CONST ai_array* scales; /*!< scale array along each dimension */ - ai_nearest_mode nearest_mode; /*!< used in nearest mode */ -} ai_layer_upsample; - -/*! - * @struct ai_layer_resize - * @ingroup layers generic - * @brief Resize layer definition - * - * This layer defines the param of a resize layer. - * It is intended to be used by its associated forward function @ref forward_resize - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_resize_{ - AI_LAYER_COMMON_FIELDS_DECLARE - - ai_coord_transf_mode coord_transf_mode; /*!< coordinate tranformation mode */ - ai_float cubic_coeff_a; /*!< the coefficient 'a' used in cubic interpolation */ - ai_bool exclude_outside; /*!< exclude outside pixels flag */ - ai_float extrapol_val; /*!< used in tf_crop_and_resize cas */ - ai_resize_mode mode; /*!< resize mode */ - ai_nearest_mode nearest_mode; /*!< used in nearest mode */ - AI_CONST ai_array* scales; /*!< scale array along each dimension */ - AI_CONST ai_array* roi; /*!< roi array, used in tf_crop_and_resize case */ -} ai_layer_resize; - -/*! - * @struct ai_layer_instanceNormalization - * @ingroup layers generic - * @brief instance normalization layer definition - * - * This layer defines the params of an instance normalization layer. - * It is intended to be used by its associated forward function @ref forward_instanceNormalization - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_instanceNormaization_{ - AI_LAYER_COMMON_FIELDS_DECLARE - ai_float eps; /*!< epsilon value, to avoid by zero division */ -} ai_layer_instanceNormalization; - -/*! - * @struct ai_layer_mode - * @ingroup layers generic - * @brief Pad layer definition - * - * This layer defines the param of an pad layer. It pad a tensor. - * It is intended to be used by its associated forward function @ref forward_pad - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_pad_{ - AI_LAYER_COMMON_FIELDS_DECLARE - ai_pad_mode mode; /*!< pad mode */ - ai_shape pads; /*!< Number of padding to add or remove at the beginning and end of each axis */ - const ai_array* value; /*!< Indicates the value to be filled */ -} ai_layer_pad; - -/*! - * @struct ai_layer_mode - * @ingroup layers generic - * @brief ConstantOfShape layer definition - * - * This layer defines the param of an constantofshape layer. It constantofshape a tensor. - * It is intended to be used by its associated forward function @ref forward_constantofshape - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_constantofshape_{ - AI_LAYER_COMMON_FIELDS_DECLARE - const ai_array* value; /*!< Indicates the value to be filled */ -} ai_layer_constantofshape; -/*! - * @struct ai_layer_add - * @ingroup layers_generic - * @brief Add layer definition - * - * This layer defines the params of an add layer. - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_add_ { - AI_LAYER_COMMON_FIELDS_DECLARE - ai_u16 in_layers_count; /*!< number of input layers to concat */ - ai_u16 in_layer_curr; /*!< current layer to concat */ - ai_tensor** in_tensors; /*!< input tensors list (if NULL==no copy) */ - ai_tensor* out_tensor; /*!< output tensor (if NULL==no copy) */ - func_copy_tensor copy_to_out_tensor; /*!< pointer to copy tensor func - (NULL = no copy) */ - ai_layer_base* split_layer; /*!< pointer to associated split layer */ - ai_layer_base* next_layer; /*!< pointer to next layer to process */ -} ai_layer_add; - -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_argminmax_ { - AI_LAYER_COMMON_FIELDS_DECLARE - ai_i16 axis; - ai_i16 select_last_index; -} ai_layer_argminmax; - -/*! - * @struct ai_layer_transpose - * @ingroup layers_generic - * @brief Transpose layer datastruct declaration. This defines the params of a - * transpose layer. It is intended to be used by his associated forward function - * @ref forward_transpose - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_transpose_ { - AI_LAYER_COMMON_FIELDS_DECLARE - ai_shape out_mapping; /*!< transpose output mapping order. I.e. tt is a - permutation of the input tensor shape */ -} ai_layer_transpose; - -/*! - * @struct ai_layer_transpose_batch - * @ingroup layers_generic - * @brief Transpose batch layer datastruct declaration. This defines the params of a - * transpose layer. It is intended to be used by his associated forward function - * @ref forward_transpose_batch - */ -typedef ai_layer_base ai_layer_transpose_batch; - - -#define AI_TIME_DISTRIBUTED_AXIS (AI_SHAPE_HEIGHT) - -/*! - * @struct ai_layer_time_distributed - * @ingroup layers_generic - * @brief Time distributed layer datastruct declaration. This defines the params - * of a time distributed layer. It is intended to be used by his associated - * forward function @ref forward_time_distributed - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_time_distributed_ { - AI_LAYER_COMMON_FIELDS_DECLARE - ai_layer_base* inner_layer; /*!< inner layer to process */ -} ai_layer_time_distributed; - -/*! - * @struct ai_layer_concat - * @ingroup layers_generic - * @brief Concatenation layer - * - * Concat Layer. - * It is a sequential layer. see @ref ai_layer_sequential - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_concat_ { - AI_LAYER_COMMON_FIELDS_DECLARE - ai_shape_dimension axis; /*!< which axis to concatenate on */ -} ai_layer_concat; - -/*! - * @struct ai_layer_pack - * @ingroup layers_generic - * @brief pack layer - * - * Pack Layer. - * It is a sequential layer. see @ref ai_layer_sequential - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_pack_ { - AI_LAYER_COMMON_FIELDS_DECLARE - ai_shape_dimension axis; /*!< which axis to concatenate on */ -} ai_layer_pack; - -/*! - * @struct ai_layer_unpack - * @ingroup layers_generic - * @brief unpack layer - * - * Unpack Layer. - * It is a sequential layer. see @ref ai_layer_sequential - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_unpack_ { - AI_LAYER_COMMON_FIELDS_DECLARE - ai_shape_dimension axis; /*!< which axis to concatenate on */ -} ai_layer_unpack; - -typedef void (*func_binary)(ai_handle out,const ai_handle a, const ai_handle b); -typedef void (*func_buffer_binary)(ai_handle out,const ai_handle a, const ai_handle b, const ai_size loop); -typedef void (*func_buffer_binary_integer)(ai_handle out,const ai_handle a, const ai_handle b, const ai_size loop, - const ai_handle scale1, const ai_handle zp1, const ai_handle scale2, const ai_handle zp2, - const ai_handle scaleout, const ai_handle zpout, const ai_i32 scalar_op); - -/*! - * @struct ai_layer_eltwise - * @ingroup layers_generic - * @brief General element-wise transformation layer - * - * Elementwise Layer. - * It is a sequential layer. see @ref ai_layer_sequential - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_eltwise_ { - AI_LAYER_COMMON_FIELDS_DECLARE - func_binary operation; /*!< operation to apply elementwise */ - func_buffer_binary buffer_operation; /*!< operation to apply elementwise */ -} ai_layer_eltwise; - -/*! - * @struct ai_layer_eltwise_integer - * @ingroup layers_generic - * @brief General element-wise transformation layer for integer data - * - * Elementwise Layer. - * It is a sequential layer. see @ref ai_layer_sequential - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_eltwise_integer_ { - AI_LAYER_COMMON_FIELDS_DECLARE - func_binary operation; /*!< operation to apply elementwise */ - func_buffer_binary_integer buffer_operation; /*!< operation to apply elementwise */ -} ai_layer_eltwise_integer; - -/*! - * @struct ai_layer_reduce - * @ingroup layers_generic - * @brief General dimension reduction layer - * - * reduction Layer. - * It is a sequential layer. see @ref ai_layer_sequential - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_reduce_ { - AI_LAYER_COMMON_FIELDS_DECLARE - const ai_array* neutral_value; /*!< Initialization value for operation */ - func_binary operation; /*!< operation to apply elementwise */ -} ai_layer_reduce; - -/*! - * @struct ai_layer_reduce_log_sum_exp - * @ingroup layers_generic - * @brief General dimension reduction layer - * - * reduction Layer. - * It is a sequential layer. see @ref ai_layer_sequential - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_reduce_log_sum_exp_ { - AI_LAYER_COMMON_FIELDS_DECLARE - ai_shape_dimension axis; -} ai_layer_reduce_log_sum_exp; - -/*! - * @struct ai_layer_reduce l1 - * @ingroup layers_generic - * @brief General dimension reduction layer - * - * reduction Layer. - * It is a sequential layer. see @ref ai_layer_sequential - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_reduce_l1_ { - AI_LAYER_COMMON_FIELDS_DECLARE - AI_CONST ai_array* axes; -} ai_layer_reduce_l1; - - -/*! - * @struct ai_layer_reduce l2 - * @ingroup layers_generic - * @brief General dimension reduction layer - * - * reduction Layer. - * It is a sequential layer. see @ref ai_layer_sequential - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_reduce_l2_ { - AI_LAYER_COMMON_FIELDS_DECLARE - AI_CONST ai_array* axes; -} ai_layer_reduce_l2; - - -/*! - * @struct ai_layer_where - * @ingroup layers generic - * @brief Where layer definition - * - * This layer operates on 3 input tensors: condition, X and Y. - * It return elements, either from X or Y, depending on condition - * (with Numpy-style broadcasting support). - * @ref forward_where - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_where_ { - AI_LAYER_COMMON_FIELDS_DECLARE - const ai_array *shapes_len; - ai_bool channel_first; -} ai_layer_where; - - -/*! - * @struct ai_layer_reverse - * @ingroup layers_reverse - * @brief Reverse layer - * - * The type of reverse function is handled by the specific forward function - * @ref forward_svm_regressor - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_reverse_ { - AI_LAYER_COMMON_FIELDS_DECLARE - ai_i32 axis; /*!< selected axis to perform the operation */ -} ai_layer_reverse; - - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Dummy forward routine with no processing. - * @ingroup layers_generic - * @param generic layer handle - */ -AI_INTERNAL_API -void forward_nop(ai_layer* layer); - -/*! - * @brief Computes the activations of a TimeDelay layer. - * @ingroup layers_generic - * @param layer the time delay layer - */ -AI_INTERNAL_API -void forward_time_delay(ai_layer* layer); - -/*! - * @brief Split network computation in N parallel branches. - * @ingroup layers_generic - * @param layer the split layer - */ -AI_INTERNAL_API -void forward_split(ai_layer* layer); - -/*! - * @brief Add network computation from N parallel branches. - * @ingroup layers_generic - * @param layer the add layer - */ -AI_INTERNAL_API -void forward_add(ai_layer* layer); - -/*! - * @brief Compute the indices of the max elements of the input tensor's element along the provided axis. - * @ingroup layers_generic - * @param layer argminmax layer - */ -AI_INTERNAL_API -void forward_argmax(ai_layer* layer); - -/*! - * @brief Compute the indices of the min elements of the input tensor's element along the provided axis. - * @ingroup layers_generic - * @param layer argminmax layer - */ -AI_INTERNAL_API -void forward_argmin(ai_layer* layer); - -/*! - * @brief Svdf layer. - * @ingroup layers_generic - * @param layer svdf layer - */ -AI_INTERNAL_API -void forward_svdf(ai_layer* layer); - -/*! - * @brief Transpose a tensor along a pivot and save transposed values into an output - * tensor - * @ingroup layers_generic - * @param layer the transpose layer - */ -AI_INTERNAL_API -void forward_transpose(ai_layer* layer); - -/*! - * @brief Transpose batch and save transposed values of a determinate batch into an output - * tensor - * @ingroup layers_generic - * @param layer the transpose batch layer - */ -AI_INTERNAL_API -void forward_transpose_batch(ai_layer* layer); - -/*! - * @brief TimeDistrubuted forward layer function. This forward function - * implements the timedistributed layer. - * @ingroup layers_generic - * @param layer the time distributed layer - */ -AI_INTERNAL_API -void forward_time_distributed(ai_layer* layer); - -/*! - * @brief Packing a list of tensors in a single tensor - * @ingroup layers generic - * @param layer the packing layer - */ -AI_INTERNAL_API -void forward_pack(ai_layer* layer); - -/*! - * @brief Unpacking a single of tensors in a list tensor - * @ingroup layers generic - * @param layer the unpacking layer - */ -AI_INTERNAL_API -void forward_unpack(ai_layer* layer); - -/*! - * @brief Concatenates a list of tensors into a single tensor. - * @ingroup layers_generic - * @param layer the concatenation layer - */ -AI_INTERNAL_API -void forward_concat(ai_layer* layer); - -/*! - * @brief Gather an input tensor - * @ingroup layers_generic - * @param layer the gathered layer - */ -AI_INTERNAL_API -void forward_gather(ai_layer* layer); - -/*! - * @brief Slice an input tensors - * @ingroup layers_generic - * @param layer the sliced layer - */ -AI_INTERNAL_API -void forward_slice(ai_layer* layer); - -/*! - * @brief Tile an input tensors - * @ingroup layers_generic - * @param layer the tiled layer - */ -AI_INTERNAL_API -void forward_tile(ai_layer* layer); - -/*! - * @brief Returns the shape of an input tensors - * @ingroup layers_generic - * @param layer the Shape layer - */ -AI_INTERNAL_API -void forward_shape(ai_layer* layer); - -/*! - * @brief TopK an input tensors - * @ingroup layers_generic - * @param layer the Topked layer - */ -AI_INTERNAL_API -void forward_topK(ai_layer* layer); - -/*! - * @brief Pad an input tensors - * @ingroup layers_generic - * @param layer the pad layer - */ -AI_INTERNAL_API -void forward_pad(ai_layer* layer); - -/*! - * @brief ConstantofShape an input tensors - * @ingroup layers_generic - * @param layer the constantofshape layer - */ -AI_INTERNAL_API -void forward_constantofshape(ai_layer* layer); - -/*! - * @brief Upsample an input tensors - * @ingroup layers_generic - * @param layer the upsampled layer - */ -AI_INTERNAL_API -void forward_upsample(ai_layer* layer); - -/*! - * @brief Resize an input tensors - * @ingroup layers_generic - * @param layer the resized layer - */ -AI_INTERNAL_API -void forward_resize(ai_layer* layer); - -/*! - * @brief Instance Normalization on an input tensors - * @ingroup layers_generic - * @param layer the instance normalization layer - */ -AI_INTERNAL_API -void forward_instanceNormalization(ai_layer* layer); - -/*! - * @brief Apply an elementwise transformation to the input tensors - * @ingroup layers_generic - * @param layer the elementwise layer - */ -AI_INTERNAL_API -void forward_eltwise(ai_layer* layer); - -/*! - * @brief Apply an elementwise transformation to the integer input tensors - * @ingroup layers_generic - * @param layer the elementwise layer - */ -AI_INTERNAL_API -void forward_eltwise_integer(ai_layer* layer); - -/*! - * @brief Apply an elementwise transformation to the signed integer input tensors - * @ingroup layers_generic - * @param layer the elementwise layer - */ -AI_INTERNAL_API -void forward_eltwise_integer_INT8(ai_layer* layer); - -/*! - * @brief Apply an elementwise transformation to the unsigned integer input tensors - * @ingroup layers_generic - * @param layer the elementwise layer - */ -AI_INTERNAL_API -void forward_eltwise_integer_UINT8(ai_layer* layer); - -/*! - * @brief Apply a reduce transformation to the input tensors - * @ingroup layers_generic - * @param layer the reduce layer - */ -AI_INTERNAL_API -void forward_reduce(ai_layer* layer); - -/*! - * @brief Apply a reduce transformation to the input tensors - * @ingroup layers_generic - * @param layer the reduce layer - */ -AI_INTERNAL_API -void forward_reduce_log_sum_exp(ai_layer* layer); - -/*! - * @brief Apply a reduce transformation to the input tensors - * @ingroup layers_generic - * @param layer the reduce layer - */ -AI_INTERNAL_API -void forward_reduce_l1(ai_layer* layer); - -/*! - * @brief Apply a reduce transformation to the input tensors - * @ingroup layers_generic - * @param layer the reduce layer - */ -AI_INTERNAL_API -void forward_reduce_l2(ai_layer* layer); - - -/*! - * @brief Behave like numpy.where with Numpy-style broadcasting support - * @ingroup layers_generic - * @param layer the where layer - */ -AI_INTERNAL_API -void forward_where(ai_layer* layer); - -/*! - * @brief Apply an elementwise addition to the input tensors - * @ingroup layers_generic - * @param layer the elementwise layer - */ -AI_INTERNAL_API -void forward_add_integer(ai_layer* layer); - -/*! - * @brief Apply an elementwise addition to the input tensors - * with int8 I/O - * @ingroup layers_generic - * @param layer the elementwise layer - */ -AI_INTERNAL_API -void forward_add_integer_INT8(ai_layer* layer); - -/*! - * @brief Apply an elementwise addition to the input tensors - * with uint8 I/O - * @ingroup layers_generic - * @param layer the elementwise layer - */ -AI_INTERNAL_API -void forward_add_integer_UINT8(ai_layer* layer); - - -/*! - * @brief Reverse layer. - * @ingroup layers_generic - * @param layer reverse layer - */ -AI_INTERNAL_API -void forward_reverse(ai_layer *pLayer); - - -/*! - * @brief Upsample an input tensors with unsigned 8-bit integer input,. - * It is to be used also for other formats, since the function only - * performs memory copy. - * @ingroup layers_generic - * @param layer the upsampled layer - */ -AI_INTERNAL_API -void forward_upsample_generic(ai_layer* layer); - - -AI_API_DECLARE_END - -#endif /*LAYERS_GENERIC_H*/ + +/** + ****************************************************************************** + * @file layers_generic.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform generic layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_GENERIC_H +#define LAYERS_GENERIC_H + +#include "layers_common.h" + +typedef enum { + KTfLiteNone = 0, + KTfLiteActRelu, + KTfLiteActRelu1, + KTfLiteActRelu6, + KTfLiteActTanh, + KTfLiteActSignBit, + KTfLiteActSigmoid +} ai_tflitefused_activation; + +/*! + * @defgroup layers_generic Generic Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_time_delay + * @ingroup layers_generic + * @brief TimeDelay layer with sparse kernel + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_time_delay_ { + AI_LAYER_COMMON_FIELDS_DECLARE + AI_CONST ai_array* mask; /*!< sparse filter mask */ +} ai_layer_time_delay; + +/*! + * @struct ai_layer_split + * @ingroup layers_generic + * @brief Split layer definition + * + * This layer defines the params of a splitting layer. It is intended to be used + * by his associated forward function @ref forward_split + */ + +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_split_ { + AI_LAYER_COMMON_FIELDS_DECLARE + const ai_i32 outer_elems; + const ai_i32 outer_elems_stride; +} ai_layer_split; + + +/*! + * @struct ai_layer_topK + * @ingroup layers_generic + * @brief topK layer definition + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_topK_{ + AI_LAYER_COMMON_FIELDS_DECLARE + ai_i16 axis; + ai_i16 largest; +} ai_layer_topK; + +typedef AI_ALIGNED_TYPE(struct,4)ai_layer_svdf_{ + AI_LAYER_COMMON_FIELDS_DECLARE + ai_size rank; + ai_tflitefused_activation activation; + +} ai_layer_svdf; + + +/*! + * @struct ai_layer_slice + * @ingroup layers_generic + * @brief Slice layer definition + * + * This layer defines the params of a slicing layer. It is intended to be used + * by his associated forward function @ref forward_slice + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_slice_ { + AI_LAYER_COMMON_FIELDS_DECLARE + AI_CONST ai_array* axes; /*!< Axes that 'starts' and 'ends' apply to. It's optional*/ + AI_CONST ai_array* starts; /*!< Starting indices of corrisponding axis in axes*/ + AI_CONST ai_array* ends; /*!< Ending indices (exclusive) of corrisponding axis in axes*/ +} ai_layer_slice; + +/*! + * @struct ai_layer_gather + * @ingroup layers_generic + * @brief Gather layer definition + * + * This layer defines the params of a gathering layer. It is intended to be used + * by his associated forward function @ref forward_gather + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_gather_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_i16 axis; /*!< Which axis to gather on It's optional*/ + ai_tensor* indices; /*!< Indices of corrisponding axis in axes*/ + } ai_layer_gather; + +/*! + * @struct ai_layer_tile + * @ingroup layers generic + * @brief Tile layer definition + * + * This layer defines the param of an tile layer. It constructs a tensor by tiling a + * given tensor. It is intended to be used by its associated forward function + * @ref forward_upsample + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_tile_{ + AI_LAYER_COMMON_FIELDS_DECLARE + AI_CONST ai_array* repeats; /*!< numbers of repeated copies along each dimension */ +} ai_layer_tile; + + +/*! + * @struct ai_layer_shape + * @ingroup layers generic + * @brief Shape layer definition + * + * This layer defines the param of a shape layer. It returns the shape of the + * input tensor. It is intended to be used by its associated forward function + * @ref forward_shape + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_shape_{ + AI_LAYER_COMMON_FIELDS_DECLARE +} ai_layer_shape; + + +/*! + * @struct ai_layer_upsample + * @ingroup layers generic + * @brief Upsample layer definition + * + * This layer defines the param of an upsampling layer. It overloads its params + * to allow zeros upsampling, helpful traspose convolutions, for instance. + * It is intended to be used by its associated forward function @ref forward_upsample + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_upsample_{ + AI_LAYER_COMMON_FIELDS_DECLARE + ai_upsample_mode mode; /*!< upsample mode */ + ai_bool center; /*!< center pixels */ + AI_CONST ai_array* scales; /*!< scale array along each dimension */ + ai_nearest_mode nearest_mode; /*!< used in nearest mode */ +} ai_layer_upsample; + +/*! + * @struct ai_layer_resize + * @ingroup layers generic + * @brief Resize layer definition + * + * This layer defines the param of a resize layer. + * It is intended to be used by its associated forward function @ref forward_resize + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_resize_{ + AI_LAYER_COMMON_FIELDS_DECLARE + + ai_coord_transf_mode coord_transf_mode; /*!< coordinate tranformation mode */ + ai_float cubic_coeff_a; /*!< the coefficient 'a' used in cubic interpolation */ + ai_bool exclude_outside; /*!< exclude outside pixels flag */ + ai_float extrapol_val; /*!< used in tf_crop_and_resize cas */ + ai_resize_mode mode; /*!< resize mode */ + ai_nearest_mode nearest_mode; /*!< used in nearest mode */ + AI_CONST ai_array* scales; /*!< scale array along each dimension */ + AI_CONST ai_array* roi; /*!< roi array, used in tf_crop_and_resize case */ +} ai_layer_resize; + +/*! + * @struct ai_layer_instanceNormalization + * @ingroup layers generic + * @brief instance normalization layer definition + * + * This layer defines the params of an instance normalization layer. + * It is intended to be used by its associated forward function @ref forward_instanceNormalization + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_instanceNormaization_{ + AI_LAYER_COMMON_FIELDS_DECLARE + ai_float eps; /*!< epsilon value, to avoid by zero division */ +} ai_layer_instanceNormalization; + +/*! + * @struct ai_layer_mode + * @ingroup layers generic + * @brief Pad layer definition + * + * This layer defines the param of an pad layer. It pad a tensor. + * It is intended to be used by its associated forward function @ref forward_pad + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_pad_{ + AI_LAYER_COMMON_FIELDS_DECLARE + ai_pad_mode mode; /*!< pad mode */ + ai_shape pads; /*!< Number of padding to add or remove at the beginning and end of each axis */ + const ai_array* value; /*!< Indicates the value to be filled */ +} ai_layer_pad; + +/*! + * @struct ai_layer_mode + * @ingroup layers generic + * @brief ConstantOfShape layer definition + * + * This layer defines the param of an constantofshape layer. It constantofshape a tensor. + * It is intended to be used by its associated forward function @ref forward_constantofshape + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_constantofshape_{ + AI_LAYER_COMMON_FIELDS_DECLARE + const ai_array* value; /*!< Indicates the value to be filled */ +} ai_layer_constantofshape; +/*! + * @struct ai_layer_add + * @ingroup layers_generic + * @brief Add layer definition + * + * This layer defines the params of an add layer. + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_add_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_u16 in_layers_count; /*!< number of input layers to concat */ + ai_u16 in_layer_curr; /*!< current layer to concat */ + ai_tensor** in_tensors; /*!< input tensors list (if NULL==no copy) */ + ai_tensor* out_tensor; /*!< output tensor (if NULL==no copy) */ + func_copy_tensor copy_to_out_tensor; /*!< pointer to copy tensor func + (NULL = no copy) */ + ai_layer_base* split_layer; /*!< pointer to associated split layer */ + ai_layer_base* next_layer; /*!< pointer to next layer to process */ +} ai_layer_add; + +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_argminmax_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_i16 axis; + ai_i16 select_last_index; +} ai_layer_argminmax; + +/*! + * @struct ai_layer_transpose + * @ingroup layers_generic + * @brief Transpose layer datastruct declaration. This defines the params of a + * transpose layer. It is intended to be used by his associated forward function + * @ref forward_transpose + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_transpose_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_shape out_mapping; /*!< transpose output mapping order. I.e. tt is a + permutation of the input tensor shape */ +} ai_layer_transpose; + +/*! + * @struct ai_layer_transpose_batch + * @ingroup layers_generic + * @brief Transpose batch layer datastruct declaration. This defines the params of a + * transpose layer. It is intended to be used by his associated forward function + * @ref forward_transpose_batch + */ +typedef ai_layer_base ai_layer_transpose_batch; + + +#define AI_TIME_DISTRIBUTED_AXIS (AI_SHAPE_HEIGHT) + +/*! + * @struct ai_layer_time_distributed + * @ingroup layers_generic + * @brief Time distributed layer datastruct declaration. This defines the params + * of a time distributed layer. It is intended to be used by his associated + * forward function @ref forward_time_distributed + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_time_distributed_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_layer_base* inner_layer; /*!< inner layer to process */ +} ai_layer_time_distributed; + +/*! + * @struct ai_layer_concat + * @ingroup layers_generic + * @brief Concatenation layer + * + * Concat Layer. + * It is a sequential layer. see @ref ai_layer_sequential + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_concat_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_shape_dimension axis; /*!< which axis to concatenate on */ +} ai_layer_concat; + +/*! + * @struct ai_layer_pack + * @ingroup layers_generic + * @brief pack layer + * + * Pack Layer. + * It is a sequential layer. see @ref ai_layer_sequential + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_pack_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_shape_dimension axis; /*!< which axis to concatenate on */ +} ai_layer_pack; + +/*! + * @struct ai_layer_unpack + * @ingroup layers_generic + * @brief unpack layer + * + * Unpack Layer. + * It is a sequential layer. see @ref ai_layer_sequential + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_unpack_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_shape_dimension axis; /*!< which axis to concatenate on */ +} ai_layer_unpack; + +typedef void (*func_binary)(ai_handle out,const ai_handle a, const ai_handle b); +typedef void (*func_buffer_binary)(ai_handle out,const ai_handle a, const ai_handle b, const ai_size loop); +typedef void (*func_buffer_binary_integer)(ai_handle out,const ai_handle a, const ai_handle b, const ai_size loop, + const ai_handle scale1, const ai_handle zp1, const ai_handle scale2, const ai_handle zp2, + const ai_handle scaleout, const ai_handle zpout, const ai_i32 scalar_op); + +/*! + * @struct ai_layer_eltwise + * @ingroup layers_generic + * @brief General element-wise transformation layer + * + * Elementwise Layer. + * It is a sequential layer. see @ref ai_layer_sequential + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_eltwise_ { + AI_LAYER_COMMON_FIELDS_DECLARE + func_binary operation; /*!< operation to apply elementwise */ + func_buffer_binary buffer_operation; /*!< operation to apply elementwise */ +} ai_layer_eltwise; + +/*! + * @struct ai_layer_eltwise_integer + * @ingroup layers_generic + * @brief General element-wise transformation layer for integer data + * + * Elementwise Layer. + * It is a sequential layer. see @ref ai_layer_sequential + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_eltwise_integer_ { + AI_LAYER_COMMON_FIELDS_DECLARE + func_binary operation; /*!< operation to apply elementwise */ + func_buffer_binary_integer buffer_operation; /*!< operation to apply elementwise */ +} ai_layer_eltwise_integer; + +/*! + * @struct ai_layer_reduce + * @ingroup layers_generic + * @brief General dimension reduction layer + * + * reduction Layer. + * It is a sequential layer. see @ref ai_layer_sequential + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_reduce_ { + AI_LAYER_COMMON_FIELDS_DECLARE + const ai_array* neutral_value; /*!< Initialization value for operation */ + func_binary operation; /*!< operation to apply elementwise */ +} ai_layer_reduce; + +/*! + * @struct ai_layer_reduce_log_sum_exp + * @ingroup layers_generic + * @brief General dimension reduction layer + * + * reduction Layer. + * It is a sequential layer. see @ref ai_layer_sequential + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_reduce_log_sum_exp_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_shape_dimension axis; +} ai_layer_reduce_log_sum_exp; + +/*! + * @struct ai_layer_reduce l1 + * @ingroup layers_generic + * @brief General dimension reduction layer + * + * reduction Layer. + * It is a sequential layer. see @ref ai_layer_sequential + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_reduce_l1_ { + AI_LAYER_COMMON_FIELDS_DECLARE + AI_CONST ai_array* axes; +} ai_layer_reduce_l1; + + +/*! + * @struct ai_layer_reduce l2 + * @ingroup layers_generic + * @brief General dimension reduction layer + * + * reduction Layer. + * It is a sequential layer. see @ref ai_layer_sequential + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_reduce_l2_ { + AI_LAYER_COMMON_FIELDS_DECLARE + AI_CONST ai_array* axes; +} ai_layer_reduce_l2; + + +/*! + * @struct ai_layer_where + * @ingroup layers generic + * @brief Where layer definition + * + * This layer operates on 3 input tensors: condition, X and Y. + * It return elements, either from X or Y, depending on condition + * (with Numpy-style broadcasting support). + * @ref forward_where + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_where_ { + AI_LAYER_COMMON_FIELDS_DECLARE + const ai_array *shapes_len; + ai_bool channel_first; +} ai_layer_where; + + +/*! + * @struct ai_layer_reverse + * @ingroup layers_reverse + * @brief Reverse layer + * + * The type of reverse function is handled by the specific forward function + * @ref forward_svm_regressor + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_reverse_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_i32 axis; /*!< selected axis to perform the operation */ +} ai_layer_reverse; + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Dummy forward routine with no processing. + * @ingroup layers_generic + * @param generic layer handle + */ +AI_INTERNAL_API +void forward_nop(ai_layer* layer); + +/*! + * @brief Computes the activations of a TimeDelay layer. + * @ingroup layers_generic + * @param layer the time delay layer + */ +AI_INTERNAL_API +void forward_time_delay(ai_layer* layer); + +/*! + * @brief Split network computation in N parallel branches. + * @ingroup layers_generic + * @param layer the split layer + */ +AI_INTERNAL_API +void forward_split(ai_layer* layer); + +/*! + * @brief Add network computation from N parallel branches. + * @ingroup layers_generic + * @param layer the add layer + */ +AI_INTERNAL_API +void forward_add(ai_layer* layer); + +/*! + * @brief Compute the indices of the max elements of the input tensor's element along the provided axis. + * @ingroup layers_generic + * @param layer argminmax layer + */ +AI_INTERNAL_API +void forward_argmax(ai_layer* layer); + +/*! + * @brief Compute the indices of the min elements of the input tensor's element along the provided axis. + * @ingroup layers_generic + * @param layer argminmax layer + */ +AI_INTERNAL_API +void forward_argmin(ai_layer* layer); + +/*! + * @brief Svdf layer. + * @ingroup layers_generic + * @param layer svdf layer + */ +AI_INTERNAL_API +void forward_svdf(ai_layer* layer); + +/*! + * @brief Transpose a tensor along a pivot and save transposed values into an output + * tensor + * @ingroup layers_generic + * @param layer the transpose layer + */ +AI_INTERNAL_API +void forward_transpose(ai_layer* layer); + +/*! + * @brief Transpose batch and save transposed values of a determinate batch into an output + * tensor + * @ingroup layers_generic + * @param layer the transpose batch layer + */ +AI_INTERNAL_API +void forward_transpose_batch(ai_layer* layer); + +/*! + * @brief TimeDistrubuted forward layer function. This forward function + * implements the timedistributed layer. + * @ingroup layers_generic + * @param layer the time distributed layer + */ +AI_INTERNAL_API +void forward_time_distributed(ai_layer* layer); + +/*! + * @brief Packing a list of tensors in a single tensor + * @ingroup layers generic + * @param layer the packing layer + */ +AI_INTERNAL_API +void forward_pack(ai_layer* layer); + +/*! + * @brief Unpacking a single of tensors in a list tensor + * @ingroup layers generic + * @param layer the unpacking layer + */ +AI_INTERNAL_API +void forward_unpack(ai_layer* layer); + +/*! + * @brief Concatenates a list of tensors into a single tensor. + * @ingroup layers_generic + * @param layer the concatenation layer + */ +AI_INTERNAL_API +void forward_concat(ai_layer* layer); + +/*! + * @brief Gather an input tensor + * @ingroup layers_generic + * @param layer the gathered layer + */ +AI_INTERNAL_API +void forward_gather(ai_layer* layer); + +/*! + * @brief Slice an input tensors + * @ingroup layers_generic + * @param layer the sliced layer + */ +AI_INTERNAL_API +void forward_slice(ai_layer* layer); + +/*! + * @brief Tile an input tensors + * @ingroup layers_generic + * @param layer the tiled layer + */ +AI_INTERNAL_API +void forward_tile(ai_layer* layer); + +/*! + * @brief Returns the shape of an input tensors + * @ingroup layers_generic + * @param layer the Shape layer + */ +AI_INTERNAL_API +void forward_shape(ai_layer* layer); + +/*! + * @brief TopK an input tensors + * @ingroup layers_generic + * @param layer the Topked layer + */ +AI_INTERNAL_API +void forward_topK(ai_layer* layer); + +/*! + * @brief Pad an input tensors + * @ingroup layers_generic + * @param layer the pad layer + */ +AI_INTERNAL_API +void forward_pad(ai_layer* layer); + +/*! + * @brief ConstantofShape an input tensors + * @ingroup layers_generic + * @param layer the constantofshape layer + */ +AI_INTERNAL_API +void forward_constantofshape(ai_layer* layer); + +/*! + * @brief Upsample an input tensors + * @ingroup layers_generic + * @param layer the upsampled layer + */ +AI_INTERNAL_API +void forward_upsample(ai_layer* layer); + +/*! + * @brief Resize an input tensors + * @ingroup layers_generic + * @param layer the resized layer + */ +AI_INTERNAL_API +void forward_resize(ai_layer* layer); + +/*! + * @brief Instance Normalization on an input tensors + * @ingroup layers_generic + * @param layer the instance normalization layer + */ +AI_INTERNAL_API +void forward_instanceNormalization(ai_layer* layer); + +/*! + * @brief Apply an elementwise transformation to the input tensors + * @ingroup layers_generic + * @param layer the elementwise layer + */ +AI_INTERNAL_API +void forward_eltwise(ai_layer* layer); + +/*! + * @brief Apply an elementwise transformation to the integer input tensors + * @ingroup layers_generic + * @param layer the elementwise layer + */ +AI_INTERNAL_API +void forward_eltwise_integer(ai_layer* layer); + +/*! + * @brief Apply an elementwise transformation to the signed integer input tensors + * @ingroup layers_generic + * @param layer the elementwise layer + */ +AI_INTERNAL_API +void forward_eltwise_integer_INT8(ai_layer* layer); + +/*! + * @brief Apply an elementwise transformation to the unsigned integer input tensors + * @ingroup layers_generic + * @param layer the elementwise layer + */ +AI_INTERNAL_API +void forward_eltwise_integer_UINT8(ai_layer* layer); + +/*! + * @brief Apply a reduce transformation to the input tensors + * @ingroup layers_generic + * @param layer the reduce layer + */ +AI_INTERNAL_API +void forward_reduce(ai_layer* layer); + +/*! + * @brief Apply a reduce transformation to the input tensors + * @ingroup layers_generic + * @param layer the reduce layer + */ +AI_INTERNAL_API +void forward_reduce_log_sum_exp(ai_layer* layer); + +/*! + * @brief Apply a reduce transformation to the input tensors + * @ingroup layers_generic + * @param layer the reduce layer + */ +AI_INTERNAL_API +void forward_reduce_l1(ai_layer* layer); + +/*! + * @brief Apply a reduce transformation to the input tensors + * @ingroup layers_generic + * @param layer the reduce layer + */ +AI_INTERNAL_API +void forward_reduce_l2(ai_layer* layer); + + +/*! + * @brief Behave like numpy.where with Numpy-style broadcasting support + * @ingroup layers_generic + * @param layer the where layer + */ +AI_INTERNAL_API +void forward_where(ai_layer* layer); + +/*! + * @brief Apply an elementwise addition to the input tensors + * @ingroup layers_generic + * @param layer the elementwise layer + */ +AI_INTERNAL_API +void forward_add_integer(ai_layer* layer); + +/*! + * @brief Apply an elementwise addition to the input tensors + * with int8 I/O + * @ingroup layers_generic + * @param layer the elementwise layer + */ +AI_INTERNAL_API +void forward_add_integer_INT8(ai_layer* layer); + +/*! + * @brief Apply an elementwise addition to the input tensors + * with uint8 I/O + * @ingroup layers_generic + * @param layer the elementwise layer + */ +AI_INTERNAL_API +void forward_add_integer_UINT8(ai_layer* layer); + + +/*! + * @brief Reverse layer. + * @ingroup layers_generic + * @param layer reverse layer + */ +AI_INTERNAL_API +void forward_reverse(ai_layer *pLayer); + + +/*! + * @brief Upsample an input tensors with unsigned 8-bit integer input,. + * It is to be used also for other formats, since the function only + * performs memory copy. + * @ingroup layers_generic + * @param layer the upsampled layer + */ +AI_INTERNAL_API +void forward_upsample_generic(ai_layer* layer); + + +AI_API_DECLARE_END + +#endif /*LAYERS_GENERIC_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_generic_dqnn.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_generic_dqnn.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_generic_dqnn.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_generic_dqnn.h index 54e1b420..d71078dd 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_generic_dqnn.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_generic_dqnn.h @@ -1,51 +1,51 @@ -/** - ****************************************************************************** - * @file layers_generic_dqnn.h - * @author AIS - * @brief header file of AI platform DQNN generic datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LAYERS_GENERIC_DQNN_H -#define LAYERS_GENERIC_DQNN_H - -#include "layers_common.h" -#include "layers_generic.h" - -/*! - * @defgroup layers_generic_dqnn Layers Definitions - * @brief definition - * - */ - -AI_API_DECLARE_BEGIN - - - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Handles concat with binary input, binary output and - * binary weights - * @ingroup layers_generic_dqnn - * @param layer concat layer - */ -AI_INTERNAL_API -void forward_concat_is1os1(ai_layer *pLayer); - - - -AI_API_DECLARE_END - -#endif /*LAYERS_GENERIC_DQNN_H*/ +/** + ****************************************************************************** + * @file layers_generic_dqnn.h + * @author AIS + * @brief header file of AI platform DQNN generic datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_GENERIC_DQNN_H +#define LAYERS_GENERIC_DQNN_H + +#include "layers_common.h" +#include "layers_generic.h" + +/*! + * @defgroup layers_generic_dqnn Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles concat with binary input, binary output and + * binary weights + * @ingroup layers_generic_dqnn + * @param layer concat layer + */ +AI_INTERNAL_API +void forward_concat_is1os1(ai_layer *pLayer); + + + +AI_API_DECLARE_END + +#endif /*LAYERS_GENERIC_DQNN_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_list.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_list.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_list.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_list.h index ceecbe28..b16bbfd1 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_list.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_list.h @@ -1,161 +1,161 @@ -/** - ****************************************************************************** - * @file layers_list.h - * @author AST Embedded Analytics Research Platform - * @brief header file of AI platform layers datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2018-2024 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - - -/* No sentry. This is deliberate!! */ -/* Template: LAYER_ENTRY(type_, id_, struct_, forward_func_, init_func_, destroy_func_) - * Where: - * - type_ is the (enum) type name of the layer. to have the complete enum - * value you should use the macro @ref AI_LAYER_TYPE_ENTRY(type_) that adds - * the specific prefix and postfix tokens to the type_ - * - id_ is the numeric id of the layer - * - struct_ is the name of the datastruct of the layer without the ai_layer_ - * prefix - * - forward_func_ is the forward function name of the routine implementing - * actual layer processing - * - init_func_ is the init function name of the routine implementing - * actual layer initialization - * - destroy_func_ is the destroy function name of the routine implementing - * actual layer de-initialization - */ - -/* Layer IDs for stateless layers (bit 8 set) */ -#define LAYER_ID(id_) \ - (0x100 + (id_)) -/* Layer IDs for stateful layers (bits 7 and 8 set) */ -#define LAYER_STATEFUL_ID(id_) \ - (0x180 + (id_)) - -/*!< Base layer */ -LAYER_ENTRY(BASE, LAYER_ID(0), base, NULL, NULL, NULL) -/*!< Elementwise addition layer */ -LAYER_ENTRY(ADD, LAYER_ID(1), add, forward_add, NULL, NULL) - /*!< Batch normalization layer */ -LAYER_ENTRY(BN, LAYER_ID(2), bn, forward_bn, NULL, NULL) -/*!< 2D Convolutional layer */ -LAYER_ENTRY(CONV2D, LAYER_ID(3), conv2d, forward_conv2d, NULL, NULL) -/*!< Dense layer */ -LAYER_ENTRY(DENSE, LAYER_ID(4), dense, forward_dense, NULL, NULL) -/*!< Local Response Normalization layer */ -LAYER_ENTRY(LRN, LAYER_ID(6), lrn, forward_lrn, NULL, NULL) -/*!< Nonlinearity layer */ -LAYER_ENTRY(NL, LAYER_ID(7), nl, NULL, NULL, NULL) -/*!< Normalization layer */ -LAYER_ENTRY(NORM, LAYER_ID(8), norm, forward_norm, NULL, NULL) -/*!< Merged Conv2d / Pool layer */ -LAYER_ENTRY(OPTIMIZED_CONV2D, LAYER_ID(9), conv2d_nl_pool, forward_conv2d_nl_pool, NULL, NULL) -/*!< Transpose Tensor layer */ -LAYER_ENTRY(TRANSPOSE, LAYER_ID(10), transpose, forward_transpose, NULL, NULL) -/*!< Pooling layer */ -LAYER_ENTRY(POOL, LAYER_ID(11), pool, forward_pool, NULL, NULL) -/*!< Softmax layer */ -LAYER_ENTRY(SM, LAYER_ID(12), sm, forward_sm, NULL, NULL) -/*!< Split layer */ -LAYER_ENTRY(SPLIT, LAYER_ID(13), split, forward_split, NULL, NULL) -/*!< TimeDelay layer */ -LAYER_ENTRY(TIME_DELAY, LAYER_ID(14), time_delay, forward_time_delay, NULL, NULL) -/*!< TimeDistributed layer */ -LAYER_ENTRY(TIME_DISTRIBUTED, LAYER_ID(15), time_distributed, forward_time_distributed, NULL, NULL) -/*!< Concat Tensor layer */ -LAYER_ENTRY(CONCAT, LAYER_ID(16), concat, forward_concat, NULL, NULL) -/*!< GEMM layer */ -LAYER_ENTRY(GEMM, LAYER_ID(17), gemm, forward_gemm, NULL, NULL) -/*!< Upsample layer */ -LAYER_ENTRY(UPSAMPLE, LAYER_ID(18), upsample, forward_upsample, NULL, NULL) -/*!< Container layer for eltwise operations */ -LAYER_ENTRY(ELTWISE, LAYER_ID(19), eltwise, forward_eltwise, NULL, NULL) -/*!< Container layer for eltwise integer operations */ -LAYER_ENTRY(ELTWISE_INTEGER, LAYER_ID(20), eltwise_integer, NULL, NULL, NULL) -/*!< InstanceNormalization layer */ -LAYER_ENTRY(INSTANCENORMALIZATION, LAYER_ID(21), instanceNormalization, forward_instanceNormalization, NULL, NULL) -/*!< Pad layer */ -LAYER_ENTRY(PAD, LAYER_ID(22), pad, forward_pad, NULL, NULL) -/*!< Slice layer */ -LAYER_ENTRY(SLICE, LAYER_ID(23), slice, forward_slice, NULL, NULL) -/*!< Tile layer */ -LAYER_ENTRY(TILE, LAYER_ID(24), tile, forward_tile, NULL, NULL) -/*!< Container layer for reduce operations */ -LAYER_ENTRY(REDUCE, LAYER_ID(25), reduce, forward_reduce, NULL, NULL) -/*!< Recurrent Neural Network layer */ -LAYER_ENTRY(RNN, LAYER_ID(26), rnn, forward_rnn, NULL, NULL) -/*!< Resize layer */ -LAYER_ENTRY(RESIZE, LAYER_ID(27), resize, forward_resize, NULL, NULL) -/*!< Gather layer */ -LAYER_ENTRY(GATHER, LAYER_ID(28), gather, forward_gather, NULL, NULL) -/*!< Pack layer */ -LAYER_ENTRY(PACK, LAYER_ID(29), pack, forward_pack, NULL, NULL) -/*!< Unpack layer */ -LAYER_ENTRY(UNPACK, LAYER_ID(30), unpack, forward_unpack, NULL, NULL) -/*!< ArgMin & ArgMax layers */ -LAYER_ENTRY(ARGMINMAX, LAYER_ID(31), argminmax, NULL, NULL, NULL) -/*!< Cast Neural Network Layer */ -LAYER_ENTRY(CAST, LAYER_ID(33), cast, forward_cast, NULL, NULL) -/*!< iForest layer */ -LAYER_ENTRY(IFOREST, LAYER_ID(34), iforest, forward_iforest, NULL, NULL) -/*!< SVM Regressor layer */ -LAYER_ENTRY(SVMREG, LAYER_ID(35), svmreg, forward_svm_regressor, NULL, NULL) -/*!< ArrayFeatureExtractor layer */ -LAYER_ENTRY(ARRAYFEATUREEXTRACTOR, LAYER_ID(36), arrayfeatureextractor, forward_arrayfeatureextractor, NULL, NULL) -/*!< SVM Classifier (SVC) layer */ -LAYER_ENTRY(SVC, LAYER_ID(37), svc, forward_svc, NULL, NULL) -/*!< ZipMap layer */ -LAYER_ENTRY(ZIPMAP, LAYER_ID(38), zipmap, forward_zipmap, NULL, NULL) -/*!< Where layer */ -LAYER_ENTRY(WHERE, LAYER_ID(39), where, forward_where, NULL, NULL) -/*!< LinearClassifier layer */ -LAYER_ENTRY(LINEARCLASSIFIER, LAYER_ID(42), linearclassifier, forward_linearclassifier, NULL, NULL) -/*!< TreeEnsembleClassifier layer */ -LAYER_ENTRY(TREE_ENSEMBLE_CLASSIFIER, LAYER_ID(43), tree_ensemble_classifier, forward_tree_ensemble_classifier, NULL, NULL) -/*!< TopK layer */ -LAYER_ENTRY(TOPK, LAYER_ID(45), topK, forward_topK, NULL, NULL) -/*!< ReduceLogSumExp layer */ -LAYER_ENTRY(REDUCE_LOG_SUM_EXP, LAYER_ID(51), reduce_log_sum_exp, forward_reduce_log_sum_exp, NULL, NULL) -/*!< ReduceL1 layer */ -LAYER_ENTRY(REDUCE_L1, LAYER_ID(52), reduce_l1, forward_reduce_l1, NULL, NULL) -/*!< Runtime Lite Graph Wrapper layer */ -LAYER_ENTRY(LITE_GRAPH, LAYER_ID(63), lite_graph, NULL, NULL, NULL) -/*!< TreeEnsembleRegressor layer */ -LAYER_ENTRY(TREE_ENSEMBLE_REGRESSOR, LAYER_ID(66), tree_ensemble_regressor, forward_tree_ensemble_regressor, NULL, NULL) - -/*!< Deeply Quantized Dense Layers */ -LAYER_ENTRY(CONV2D_DQNN, LAYER_ID(40), conv2d_dqnn, forward_pw_is1os1ws1_bn, NULL, NULL) -LAYER_ENTRY(POOL_DQNN, LAYER_ID(41), pool_dqnn, forward_maxpool_is1os1, NULL, NULL) - -LAYER_ENTRY(DENSE_DQNN, LAYER_ID(44), dense_dqnn, forward_dense_is1os1ws1, NULL, NULL) -/*!< Reverse layer */ -LAYER_ENTRY(REVERSE, LAYER_ID(50), reverse, forward_reverse, NULL, NULL) - - -/*****************************************************************************/ -/*!< Base Stateful Layer type */ -LAYER_ENTRY(STATEFUL, LAYER_STATEFUL_ID(0), stateful, NULL, NULL, NULL) -/*!< Long Short Time Memory layer */ -LAYER_ENTRY(LSTM, LAYER_STATEFUL_ID(1), lstm, forward_lstm, init_lstm, destroy_lstm) -/*!< Custom layer */ -LAYER_ENTRY(CUSTOM, LAYER_STATEFUL_ID(2), custom, NULL, NULL, NULL) -/*!< Gated Recurrent Unit layer */ -LAYER_ENTRY(GRU, LAYER_STATEFUL_ID(3), gru, forward_gru, init_gru, destroy_gru) - -/*!< Stateless Template layer declaration */ -/* LAYER_ENTRY(TEMPLATE, LAYER_ID(XX), template, forward_template, NULL, NULL) */ -/*!< Stateful Template layer declaration */ -/* LAYER_ENTRY(TEMPLATE, LAYER_STATEFUL_ID(XX), template, forward_template, init_template, destroy_template) */ - -#undef LAYER_ENTRY -#undef LAYER_ID -#undef LAYER_STATEFUL_ID +/** + ****************************************************************************** + * @file layers_list.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2018-2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + +/* No sentry. This is deliberate!! */ +/* Template: LAYER_ENTRY(type_, id_, struct_, forward_func_, init_func_, destroy_func_) + * Where: + * - type_ is the (enum) type name of the layer. to have the complete enum + * value you should use the macro @ref AI_LAYER_TYPE_ENTRY(type_) that adds + * the specific prefix and postfix tokens to the type_ + * - id_ is the numeric id of the layer + * - struct_ is the name of the datastruct of the layer without the ai_layer_ + * prefix + * - forward_func_ is the forward function name of the routine implementing + * actual layer processing + * - init_func_ is the init function name of the routine implementing + * actual layer initialization + * - destroy_func_ is the destroy function name of the routine implementing + * actual layer de-initialization + */ + +/* Layer IDs for stateless layers (bit 8 set) */ +#define LAYER_ID(id_) \ + (0x100 + (id_)) +/* Layer IDs for stateful layers (bits 7 and 8 set) */ +#define LAYER_STATEFUL_ID(id_) \ + (0x180 + (id_)) + +/*!< Base layer */ +LAYER_ENTRY(BASE, LAYER_ID(0), base, NULL, NULL, NULL) +/*!< Elementwise addition layer */ +LAYER_ENTRY(ADD, LAYER_ID(1), add, forward_add, NULL, NULL) + /*!< Batch normalization layer */ +LAYER_ENTRY(BN, LAYER_ID(2), bn, forward_bn, NULL, NULL) +/*!< 2D Convolutional layer */ +LAYER_ENTRY(CONV2D, LAYER_ID(3), conv2d, forward_conv2d, NULL, NULL) +/*!< Dense layer */ +LAYER_ENTRY(DENSE, LAYER_ID(4), dense, forward_dense, NULL, NULL) +/*!< Local Response Normalization layer */ +LAYER_ENTRY(LRN, LAYER_ID(6), lrn, forward_lrn, NULL, NULL) +/*!< Nonlinearity layer */ +LAYER_ENTRY(NL, LAYER_ID(7), nl, NULL, NULL, NULL) +/*!< Normalization layer */ +LAYER_ENTRY(NORM, LAYER_ID(8), norm, forward_norm, NULL, NULL) +/*!< Merged Conv2d / Pool layer */ +LAYER_ENTRY(OPTIMIZED_CONV2D, LAYER_ID(9), conv2d_nl_pool, forward_conv2d_nl_pool, NULL, NULL) +/*!< Transpose Tensor layer */ +LAYER_ENTRY(TRANSPOSE, LAYER_ID(10), transpose, forward_transpose, NULL, NULL) +/*!< Pooling layer */ +LAYER_ENTRY(POOL, LAYER_ID(11), pool, forward_pool, NULL, NULL) +/*!< Softmax layer */ +LAYER_ENTRY(SM, LAYER_ID(12), sm, forward_sm, NULL, NULL) +/*!< Split layer */ +LAYER_ENTRY(SPLIT, LAYER_ID(13), split, forward_split, NULL, NULL) +/*!< TimeDelay layer */ +LAYER_ENTRY(TIME_DELAY, LAYER_ID(14), time_delay, forward_time_delay, NULL, NULL) +/*!< TimeDistributed layer */ +LAYER_ENTRY(TIME_DISTRIBUTED, LAYER_ID(15), time_distributed, forward_time_distributed, NULL, NULL) +/*!< Concat Tensor layer */ +LAYER_ENTRY(CONCAT, LAYER_ID(16), concat, forward_concat, NULL, NULL) +/*!< GEMM layer */ +LAYER_ENTRY(GEMM, LAYER_ID(17), gemm, forward_gemm, NULL, NULL) +/*!< Upsample layer */ +LAYER_ENTRY(UPSAMPLE, LAYER_ID(18), upsample, forward_upsample, NULL, NULL) +/*!< Container layer for eltwise operations */ +LAYER_ENTRY(ELTWISE, LAYER_ID(19), eltwise, forward_eltwise, NULL, NULL) +/*!< Container layer for eltwise integer operations */ +LAYER_ENTRY(ELTWISE_INTEGER, LAYER_ID(20), eltwise_integer, NULL, NULL, NULL) +/*!< InstanceNormalization layer */ +LAYER_ENTRY(INSTANCENORMALIZATION, LAYER_ID(21), instanceNormalization, forward_instanceNormalization, NULL, NULL) +/*!< Pad layer */ +LAYER_ENTRY(PAD, LAYER_ID(22), pad, forward_pad, NULL, NULL) +/*!< Slice layer */ +LAYER_ENTRY(SLICE, LAYER_ID(23), slice, forward_slice, NULL, NULL) +/*!< Tile layer */ +LAYER_ENTRY(TILE, LAYER_ID(24), tile, forward_tile, NULL, NULL) +/*!< Container layer for reduce operations */ +LAYER_ENTRY(REDUCE, LAYER_ID(25), reduce, forward_reduce, NULL, NULL) +/*!< Recurrent Neural Network layer */ +LAYER_ENTRY(RNN, LAYER_ID(26), rnn, forward_rnn, NULL, NULL) +/*!< Resize layer */ +LAYER_ENTRY(RESIZE, LAYER_ID(27), resize, forward_resize, NULL, NULL) +/*!< Gather layer */ +LAYER_ENTRY(GATHER, LAYER_ID(28), gather, forward_gather, NULL, NULL) +/*!< Pack layer */ +LAYER_ENTRY(PACK, LAYER_ID(29), pack, forward_pack, NULL, NULL) +/*!< Unpack layer */ +LAYER_ENTRY(UNPACK, LAYER_ID(30), unpack, forward_unpack, NULL, NULL) +/*!< ArgMin & ArgMax layers */ +LAYER_ENTRY(ARGMINMAX, LAYER_ID(31), argminmax, NULL, NULL, NULL) +/*!< Cast Neural Network Layer */ +LAYER_ENTRY(CAST, LAYER_ID(33), cast, forward_cast, NULL, NULL) +/*!< iForest layer */ +LAYER_ENTRY(IFOREST, LAYER_ID(34), iforest, forward_iforest, NULL, NULL) +/*!< SVM Regressor layer */ +LAYER_ENTRY(SVMREG, LAYER_ID(35), svmreg, forward_svm_regressor, NULL, NULL) +/*!< ArrayFeatureExtractor layer */ +LAYER_ENTRY(ARRAYFEATUREEXTRACTOR, LAYER_ID(36), arrayfeatureextractor, forward_arrayfeatureextractor, NULL, NULL) +/*!< SVM Classifier (SVC) layer */ +LAYER_ENTRY(SVC, LAYER_ID(37), svc, forward_svc, NULL, NULL) +/*!< ZipMap layer */ +LAYER_ENTRY(ZIPMAP, LAYER_ID(38), zipmap, forward_zipmap, NULL, NULL) +/*!< Where layer */ +LAYER_ENTRY(WHERE, LAYER_ID(39), where, forward_where, NULL, NULL) +/*!< LinearClassifier layer */ +LAYER_ENTRY(LINEARCLASSIFIER, LAYER_ID(42), linearclassifier, forward_linearclassifier, NULL, NULL) +/*!< TreeEnsembleClassifier layer */ +LAYER_ENTRY(TREE_ENSEMBLE_CLASSIFIER, LAYER_ID(43), tree_ensemble_classifier, forward_tree_ensemble_classifier, NULL, NULL) +/*!< TopK layer */ +LAYER_ENTRY(TOPK, LAYER_ID(45), topK, forward_topK, NULL, NULL) +/*!< ReduceLogSumExp layer */ +LAYER_ENTRY(REDUCE_LOG_SUM_EXP, LAYER_ID(51), reduce_log_sum_exp, forward_reduce_log_sum_exp, NULL, NULL) +/*!< ReduceL1 layer */ +LAYER_ENTRY(REDUCE_L1, LAYER_ID(52), reduce_l1, forward_reduce_l1, NULL, NULL) +/*!< Runtime Lite Graph Wrapper layer */ +LAYER_ENTRY(LITE_GRAPH, LAYER_ID(63), lite_graph, NULL, NULL, NULL) +/*!< TreeEnsembleRegressor layer */ +LAYER_ENTRY(TREE_ENSEMBLE_REGRESSOR, LAYER_ID(66), tree_ensemble_regressor, forward_tree_ensemble_regressor, NULL, NULL) + +/*!< Deeply Quantized Dense Layers */ +LAYER_ENTRY(CONV2D_DQNN, LAYER_ID(40), conv2d_dqnn, forward_pw_is1os1ws1_bn, NULL, NULL) +LAYER_ENTRY(POOL_DQNN, LAYER_ID(41), pool_dqnn, forward_maxpool_is1os1, NULL, NULL) + +LAYER_ENTRY(DENSE_DQNN, LAYER_ID(44), dense_dqnn, forward_dense_is1os1ws1, NULL, NULL) +/*!< Reverse layer */ +LAYER_ENTRY(REVERSE, LAYER_ID(50), reverse, forward_reverse, NULL, NULL) + + +/*****************************************************************************/ +/*!< Base Stateful Layer type */ +LAYER_ENTRY(STATEFUL, LAYER_STATEFUL_ID(0), stateful, NULL, NULL, NULL) +/*!< Long Short Time Memory layer */ +LAYER_ENTRY(LSTM, LAYER_STATEFUL_ID(1), lstm, forward_lstm, init_lstm, destroy_lstm) +/*!< Custom layer */ +LAYER_ENTRY(CUSTOM, LAYER_STATEFUL_ID(2), custom, NULL, NULL, NULL) +/*!< Gated Recurrent Unit layer */ +LAYER_ENTRY(GRU, LAYER_STATEFUL_ID(3), gru, forward_gru, init_gru, destroy_gru) + +/*!< Stateless Template layer declaration */ +/* LAYER_ENTRY(TEMPLATE, LAYER_ID(XX), template, forward_template, NULL, NULL) */ +/*!< Stateful Template layer declaration */ +/* LAYER_ENTRY(TEMPLATE, LAYER_STATEFUL_ID(XX), template, forward_template, init_template, destroy_template) */ + +#undef LAYER_ENTRY +#undef LAYER_ID +#undef LAYER_STATEFUL_ID diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_lite_graph.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_lite_graph.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_lite_graph.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_lite_graph.h index 3b27c32b..4df0bd88 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_lite_graph.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_lite_graph.h @@ -1,48 +1,48 @@ -/** - ****************************************************************************** - * @file layers_lite_graph.h - * @author AST Embedded Analytics Research Platform - * @brief header file of AI platform lite graph layers wrapper interface - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -#ifndef LAYERS_LITE_GRAPH_H -#define LAYERS_LITE_GRAPH_H - -#include "core_common.h" - -/*! - * @defgroup layers_lite_graph Lite Graph Wrapper Definitions - * @brief definition - * - */ - -AI_API_DECLARE_BEGIN - -/*! - * @struct ai_layer_lite_graph - * @ingroup layers_lite_graph - * @brief Generic Lite Graph Layer Wrapper - * - * The type of lite graph is handled by the specific forward lite graph function. - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_lite_graph_ { - AI_NODE_COMMON_FIELDS_DECLARE - ai_handle* activations_map; /*!< array of pointers to shared activations memory pools */ - ai_handle* weights_map; /*!< array of pointers to shared weights memory pools */ -} ai_layer_lite_graph; - - -AI_API_DECLARE_END - -#endif /*LAYERS_LITE_GRAPH_H*/ +/** + ****************************************************************************** + * @file layers_lite_graph.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform lite graph layers wrapper interface + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef LAYERS_LITE_GRAPH_H +#define LAYERS_LITE_GRAPH_H + +#include "core_common.h" + +/*! + * @defgroup layers_lite_graph Lite Graph Wrapper Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_lite_graph + * @ingroup layers_lite_graph + * @brief Generic Lite Graph Layer Wrapper + * + * The type of lite graph is handled by the specific forward lite graph function. + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_lite_graph_ { + AI_NODE_COMMON_FIELDS_DECLARE + ai_handle* activations_map; /*!< array of pointers to shared activations memory pools */ + ai_handle* weights_map; /*!< array of pointers to shared weights memory pools */ +} ai_layer_lite_graph; + + +AI_API_DECLARE_END + +#endif /*LAYERS_LITE_GRAPH_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_ml.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_ml.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_ml.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_ml.h index 71bac1b2..792add9b 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_ml.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_ml.h @@ -1,89 +1,89 @@ -/** - ****************************************************************************** - * @file layers_ml.h - * @author AST Embedded Analytics Research Platform - * @brief header file of AI platform ml layers datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LAYERS_ML_H -#define LAYERS_ML_H - -#include "layers_common.h" - -/*! - * @defgroup layers_generic ML Layers Definitions - * @brief definition - * - */ - -AI_API_DECLARE_BEGIN - -/*! - * @struct ai_layer_ArrayFeatureExtractor - * @ingroup layers_ml - * @brief ai_layer_ArrayFeatureExtractor layer definition - * - * This layer select elements of the input tensor based on the indices passed. It is intended to be used - * by his associated forward function @ref forward_arrayfeatureextractor - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_arrayfeatureextractor_ { - AI_LAYER_COMMON_FIELDS_DECLARE - ai_tensor* indices; /*!< Indices of corrisponding axis in axes*/ -} ai_layer_arrayfeatureextractor; - - -/*! - * @struct ai_layer_ZipMap - * @ingroup layers_ml - * @brief ai_layer_ZipMap layer definition - * - * This layer creates a map from the input and the attributes. - * The values are provided by the input tensor, while the keys are specified by the attributes. - * The user must provide keys in either classlabels_strings or classlabels_int64s (but not both). - * The columns of the tensor correspond one-by-one to the keys specified by the attributes. - * There must be as many columns as keys. - * It is intended to be used by his associated forward function @ref forward_zipmap. - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_zipmap_ { - AI_LAYER_COMMON_FIELDS_DECLARE - ai_bool has_classlabels_int; -} ai_layer_zipmap; - - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - - -/*! - * @brief select elements of the input tensor based on the indices passed. - * @ingroup layers_ml - * @param layer array feture extractor - */ -AI_INTERNAL_API -void forward_arrayfeatureextractor(ai_layer* layer); - - -/*! - * @brief creates a map from the inputs and the attributes - * @ingroup layers_ml - * @param layer zipmap - */ -AI_INTERNAL_API -void forward_zipmap(ai_layer* layer); - - - -AI_API_DECLARE_END - -#endif /*LAYERS_ML_H*/ +/** + ****************************************************************************** + * @file layers_ml.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform ml layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_ML_H +#define LAYERS_ML_H + +#include "layers_common.h" + +/*! + * @defgroup layers_generic ML Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_ArrayFeatureExtractor + * @ingroup layers_ml + * @brief ai_layer_ArrayFeatureExtractor layer definition + * + * This layer select elements of the input tensor based on the indices passed. It is intended to be used + * by his associated forward function @ref forward_arrayfeatureextractor + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_arrayfeatureextractor_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_tensor* indices; /*!< Indices of corrisponding axis in axes*/ +} ai_layer_arrayfeatureextractor; + + +/*! + * @struct ai_layer_ZipMap + * @ingroup layers_ml + * @brief ai_layer_ZipMap layer definition + * + * This layer creates a map from the input and the attributes. + * The values are provided by the input tensor, while the keys are specified by the attributes. + * The user must provide keys in either classlabels_strings or classlabels_int64s (but not both). + * The columns of the tensor correspond one-by-one to the keys specified by the attributes. + * There must be as many columns as keys. + * It is intended to be used by his associated forward function @ref forward_zipmap. + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_zipmap_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_bool has_classlabels_int; +} ai_layer_zipmap; + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + + +/*! + * @brief select elements of the input tensor based on the indices passed. + * @ingroup layers_ml + * @param layer array feture extractor + */ +AI_INTERNAL_API +void forward_arrayfeatureextractor(ai_layer* layer); + + +/*! + * @brief creates a map from the inputs and the attributes + * @ingroup layers_ml + * @param layer zipmap + */ +AI_INTERNAL_API +void forward_zipmap(ai_layer* layer); + + + +AI_API_DECLARE_END + +#endif /*LAYERS_ML_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_iforest.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_iforest.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_iforest.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_iforest.h index f4beec2c..787c737f 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_iforest.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_iforest.h @@ -1,75 +1,75 @@ -/** - ****************************************************************************** - * @file layers_iforest.h - * @author AIS - * @brief header file of AI platform iForest layers datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -#ifndef LAYERS_IFOREST_H -#define LAYERS_IFOREST_H - -#include "layers_common.h" - -/*! - * @defgroup layers_ml Layers Definitions - * @brief definition - * - */ - -AI_API_DECLARE_BEGIN - - -/* Allowed tests branch in the iTrees */ -typedef enum -{ - AI_IFOREST_BRANCH_LT_IDX = 0, - AI_IFOREST_BRANCH_LEQ_IDX, - AI_IFOREST_BRANCH_EQ_IDX, - AI_IFOREST_BRANCH_END, -} ai_iforest_branch_e; - - -/*! - * @struct ai_layer_iforest - * @ingroup layers_iforest - * @brief iForest layer - * - * The type of iforest function is handled by the specific forward function - * @ref forward_iforest - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_iforest_ { - AI_LAYER_COMMON_FIELDS_DECLARE - ai_float global_average_path_length; /*!< global average path length used to normalized average path length*/ - ai_float score_threshold; /*!< score threshold used to center the score around 0 */ -} ai_layer_iforest; - - - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Decodes the iforest ML algorithm. - * @ingroup layers_iforest - * @param layer iforest layer - */ -AI_INTERNAL_API -void forward_iforest(ai_layer *pLayer); - - - -AI_API_DECLARE_END - -#endif /*LAYERS_IFOREST_H*/ +/** + ****************************************************************************** + * @file layers_iforest.h + * @author AIS + * @brief header file of AI platform iForest layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef LAYERS_IFOREST_H +#define LAYERS_IFOREST_H + +#include "layers_common.h" + +/*! + * @defgroup layers_ml Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + + +/* Allowed tests branch in the iTrees */ +typedef enum +{ + AI_IFOREST_BRANCH_LT_IDX = 0, + AI_IFOREST_BRANCH_LEQ_IDX, + AI_IFOREST_BRANCH_EQ_IDX, + AI_IFOREST_BRANCH_END, +} ai_iforest_branch_e; + + +/*! + * @struct ai_layer_iforest + * @ingroup layers_iforest + * @brief iForest layer + * + * The type of iforest function is handled by the specific forward function + * @ref forward_iforest + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_iforest_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_float global_average_path_length; /*!< global average path length used to normalized average path length*/ + ai_float score_threshold; /*!< score threshold used to center the score around 0 */ +} ai_layer_iforest; + + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Decodes the iforest ML algorithm. + * @ingroup layers_iforest + * @param layer iforest layer + */ +AI_INTERNAL_API +void forward_iforest(ai_layer *pLayer); + + + +AI_API_DECLARE_END + +#endif /*LAYERS_IFOREST_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_linearclassifier.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_linearclassifier.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_linearclassifier.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_linearclassifier.h index df34a9bc..6312e9e5 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_linearclassifier.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_linearclassifier.h @@ -1,66 +1,66 @@ -/** - ****************************************************************************** - * @file layers_ml_linearclassifier.h - * @author SRA - * @brief header file of AI platform LinearClassifier datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LAYERS_LINEARCLASSIFIER_H -#define LAYERS_LINEARCLASSIFIER_H - -#include "layers_common.h" -#include "layers_nl.h" - -/*! - * @defgroup layers_linearclassifier Layers Definitions - * @brief definition - * - */ - -AI_API_DECLARE_BEGIN - - -/*! - * @struct ai_layer_linearclassifier - * @ingroup layers_linearclassifier - * @brief Linearclassifier layer - * - * The type of svmreg function is handled by the specific forward function - * @ref forward_linearclassifier - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_linearclassifier_ { - AI_LAYER_COMMON_FIELDS_DECLARE - func_nl nl_func; /*!< function pointer to non linear transform */ \ - ai_bool multi_class; /*!< Indicates whether to do OvR or multinomial */ - ai_bool has_classlabels_int; /*!< if True, LinearClassifier returns classlabels int, else classlabels string */ - -} ai_layer_linearclassifier; - - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Decodes the LinearClassifier ML operator. - * @ingroup layers_linaerclassifier - * @param layer linear classifier layer - */ -AI_INTERNAL_API -void forward_linearclassifier(ai_layer *pLayer); - - - -AI_API_DECLARE_END - -#endif /*LAYERS_LINEARCLASSIFIER_H*/ +/** + ****************************************************************************** + * @file layers_ml_linearclassifier.h + * @author SRA + * @brief header file of AI platform LinearClassifier datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_LINEARCLASSIFIER_H +#define LAYERS_LINEARCLASSIFIER_H + +#include "layers_common.h" +#include "layers_nl.h" + +/*! + * @defgroup layers_linearclassifier Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + + +/*! + * @struct ai_layer_linearclassifier + * @ingroup layers_linearclassifier + * @brief Linearclassifier layer + * + * The type of svmreg function is handled by the specific forward function + * @ref forward_linearclassifier + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_linearclassifier_ { + AI_LAYER_COMMON_FIELDS_DECLARE + func_nl nl_func; /*!< function pointer to non linear transform */ \ + ai_bool multi_class; /*!< Indicates whether to do OvR or multinomial */ + ai_bool has_classlabels_int; /*!< if True, LinearClassifier returns classlabels int, else classlabels string */ + +} ai_layer_linearclassifier; + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Decodes the LinearClassifier ML operator. + * @ingroup layers_linaerclassifier + * @param layer linear classifier layer + */ +AI_INTERNAL_API +void forward_linearclassifier(ai_layer *pLayer); + + + +AI_API_DECLARE_END + +#endif /*LAYERS_LINEARCLASSIFIER_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_svc.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_svc.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_svc.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_svc.h index b61b4eb8..8cc742f9 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_svc.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_svc.h @@ -1,77 +1,77 @@ -/** - ****************************************************************************** - * @file layers_svc.h - * @author AST Embedded Analytics Research Platform - * @brief header file of AI platform SVM Classifier (SVC) datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -#ifndef LAYERS_SVC_H -#define LAYERS_SVC_H - -#include "layers_common.h" - -/*! - * @defgroup layers_svc Layers Definitions - * @brief definition - * - */ - -AI_API_DECLARE_BEGIN - - -/* SVM classifier (SVC) kernel types */ -typedef enum ai_svc_kernel_e_ { - AI_SVC_KERNEL_LINEAR = 0, - AI_SVC_KERNEL_POLYNOMIAL, - AI_SVC_KERNEL_RBF, - AI_SVC_KERNEL_SIGMOID, - AI_SVC_KERNEL_UNSUPPORTED -} ai_svc_kernel_e; - - -/*! - * @struct ai_layer_svc - * @ingroup layers_svc - * @brief SVM Classifier (SVC) layer - * - * The type of svc function is handled by the specific forward function - * @ref forward_svc - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_svc_ { - AI_LAYER_COMMON_FIELDS_DECLARE - ai_float gamma; /*!< kernel coefficient for rbf, polynomial and sigmoid functions */ - ai_float coef0; /*!< term in polynomial and sigmoid functions */ - ai_u32 degree; /*!< polynomial function degree */ - ai_svc_kernel_e kernel_type; /*!< kernel type : see ai_svm_kernel_e */ - ai_bool proba_support; /*!< whether or not use the parameters learned in Platt scaling */ - ai_bool has_classlabels_int; /*!< if True, SVC returns classlabels int, else classlabels string */ -} ai_layer_svc; - - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Decodes the SVM Classifier ML operator. - * @ingroup layers_svc - * @param layer svm classifier layer - */ -AI_INTERNAL_API -void forward_svc(ai_layer *pLayer); - - -AI_API_DECLARE_END - -#endif /*LAYERS_SVC_H*/ +/** + ****************************************************************************** + * @file layers_svc.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform SVM Classifier (SVC) datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef LAYERS_SVC_H +#define LAYERS_SVC_H + +#include "layers_common.h" + +/*! + * @defgroup layers_svc Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + + +/* SVM classifier (SVC) kernel types */ +typedef enum ai_svc_kernel_e_ { + AI_SVC_KERNEL_LINEAR = 0, + AI_SVC_KERNEL_POLYNOMIAL, + AI_SVC_KERNEL_RBF, + AI_SVC_KERNEL_SIGMOID, + AI_SVC_KERNEL_UNSUPPORTED +} ai_svc_kernel_e; + + +/*! + * @struct ai_layer_svc + * @ingroup layers_svc + * @brief SVM Classifier (SVC) layer + * + * The type of svc function is handled by the specific forward function + * @ref forward_svc + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_svc_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_float gamma; /*!< kernel coefficient for rbf, polynomial and sigmoid functions */ + ai_float coef0; /*!< term in polynomial and sigmoid functions */ + ai_u32 degree; /*!< polynomial function degree */ + ai_svc_kernel_e kernel_type; /*!< kernel type : see ai_svm_kernel_e */ + ai_bool proba_support; /*!< whether or not use the parameters learned in Platt scaling */ + ai_bool has_classlabels_int; /*!< if True, SVC returns classlabels int, else classlabels string */ +} ai_layer_svc; + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Decodes the SVM Classifier ML operator. + * @ingroup layers_svc + * @param layer svm classifier layer + */ +AI_INTERNAL_API +void forward_svc(ai_layer *pLayer); + + +AI_API_DECLARE_END + +#endif /*LAYERS_SVC_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_svmregressor.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_svmregressor.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_svmregressor.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_svmregressor.h index 887f0b4f..7f78d198 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_svmregressor.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_svmregressor.h @@ -1,78 +1,78 @@ -/** - ****************************************************************************** - * @file layers_svmregressor.h - * @author AIS - * @brief header file of AI platform SVM Regressor datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -#ifndef LAYERS_SVMREGRESSOR_H -#define LAYERS_SVMREGRESSOR_H - -#include "layers_common.h" - -/*! - * @defgroup layers_svmreg Layers Definitions - * @brief definition - * - */ - -AI_API_DECLARE_BEGIN - - -/* SVM regressor kernel types */ -typedef enum ai_svm_kernel_e_ { - AI_SVMREG_KERNEL_LINEAR = 0, - AI_SVMREG_KERNEL_POLYNOMIAL, - AI_SVMREG_KERNEL_RBF, - AI_SVMREG_KERNEL_SIGMOID, - AI_SVMREG_KERNEL_UNSUPPORTED, -} ai_svm_kernel_e; - - -/*! - * @struct ai_layer_svmreg - * @ingroup layers_svmreg - * @brief SVM Regressor layer - * - * The type of svmreg function is handled by the specific forward function - * @ref forward_svm_regressor - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_svmreg_ { - AI_LAYER_COMMON_FIELDS_DECLARE - ai_float intercept; /*!< constant used in the decision function */ - ai_float gamma; /*!< kernel coefficient for rbf, polynomial and sigmoid functions */ - ai_float coef0; /*!< term in polynomial and sigmoid functions */ - ai_u32 degree; /*!< polynomial function degree */ - ai_svm_kernel_e kernel_type; /*!< kernel type : see ai_svm_kernel_e */ -} ai_layer_svmreg; - - - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Decodes the SVM Regressor ML operator. - * @ingroup layers_svmreg - * @param layer svm regressor layer - */ -AI_INTERNAL_API -void forward_svm_regressor(ai_layer *pLayer); - - - -AI_API_DECLARE_END - -#endif /*LAYERS_SVMREGRESSOR_H*/ +/** + ****************************************************************************** + * @file layers_svmregressor.h + * @author AIS + * @brief header file of AI platform SVM Regressor datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef LAYERS_SVMREGRESSOR_H +#define LAYERS_SVMREGRESSOR_H + +#include "layers_common.h" + +/*! + * @defgroup layers_svmreg Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + + +/* SVM regressor kernel types */ +typedef enum ai_svm_kernel_e_ { + AI_SVMREG_KERNEL_LINEAR = 0, + AI_SVMREG_KERNEL_POLYNOMIAL, + AI_SVMREG_KERNEL_RBF, + AI_SVMREG_KERNEL_SIGMOID, + AI_SVMREG_KERNEL_UNSUPPORTED, +} ai_svm_kernel_e; + + +/*! + * @struct ai_layer_svmreg + * @ingroup layers_svmreg + * @brief SVM Regressor layer + * + * The type of svmreg function is handled by the specific forward function + * @ref forward_svm_regressor + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_svmreg_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_float intercept; /*!< constant used in the decision function */ + ai_float gamma; /*!< kernel coefficient for rbf, polynomial and sigmoid functions */ + ai_float coef0; /*!< term in polynomial and sigmoid functions */ + ai_u32 degree; /*!< polynomial function degree */ + ai_svm_kernel_e kernel_type; /*!< kernel type : see ai_svm_kernel_e */ +} ai_layer_svmreg; + + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Decodes the SVM Regressor ML operator. + * @ingroup layers_svmreg + * @param layer svm regressor layer + */ +AI_INTERNAL_API +void forward_svm_regressor(ai_layer *pLayer); + + + +AI_API_DECLARE_END + +#endif /*LAYERS_SVMREGRESSOR_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_treeensembleclassifier.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_treeensembleclassifier.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_treeensembleclassifier.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_treeensembleclassifier.h index efd00645..a6d4e7be 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_treeensembleclassifier.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_treeensembleclassifier.h @@ -1,108 +1,108 @@ -/** - ****************************************************************************** - * @file layers_ml_treeensembleclassifier.h - * @author AIS - * @brief header file of AI platform TreeEnsembleClassifier datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021-2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -#ifndef LAYERS_TREE_ENSEMBLE_CLASSIFIER_H -#define LAYERS_TREE_ENSEMBLE_CLASSIFIER_H - -#include "layers_common.h" -#include "layers_nl.h" - - - -/*! - * @defgroup layers_ml_treensembleclassifier Layers Definitions - * @brief definition - * - */ - -AI_API_DECLARE_BEGIN - -/* Error return codes */ -#define AI_TREE_ENSEMBLE_CLASSIFIER_ERROR_NO 0 -#define AI_TREE_ENSEMBLE_CLASSIFIER_ERROR_WRONG_IDX_FMT -1 -#define AI_TREE_ENSEMBLE_CLASSIFIER_ERROR_UNFOUND_LEAF -2 -#define AI_TREE_ENSEMBLE_CLASSIFIER_ERROR_UNSUPPORTED_BRANCH -3 -#define AI_TREE_ENSEMBLE_CLASSIFIER_ERROR_UNSUPPORTED_FEATURE -4 - -#define AI_TREE_ENSEMBLE_CLASSIFIER_DEPTH_MAX 10000 - - -/* Type of condition in the TreeEnsembleClassifier*/ -typedef enum -{ - AI_TREE_ENSEMBLE_CLASSIFIER_BRANCH_LT_IDX = 0, - AI_TREE_ENSEMBLE_CLASSIFIER_BRANCH_LEQ_IDX, - AI_TREE_ENSEMBLE_CLASSIFIER_BRANCH_EQ_IDX, - AI_TREE_ENSEMBLE_CLASSIFIER_BRANCH_END, -} ai_tree_ensenble_classifier_branch_e; - -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_tree_ensemble_classifier_ { - AI_LAYER_COMMON_FIELDS_DECLARE - func_nl nl_func; - uint8_t all_weights_are_positive; - ai_float nodes_values_scale; - ai_float nodes_values_offset; - ai_float class_weights_scale; - ai_float class_weights_offset; -} ai_layer_tree_ensemble_classifier; - - - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Decodes the TreeEnsembleClassifier ML operator. - * @ingroup layers_svmreg - * @param layer tree ensemble classifier layer - */ -AI_INTERNAL_API -void forward_tree_ensemble_classifier(ai_layer *pLayer); - -AI_INTERNAL_API -ai_i32 decodeEstimator_LEQ_8Bits(const ai_float *pDataIn, - ai_float *pOutDataScores, - const ai_u8 *pFeatureIdxForEstimator, - const ai_float *pValuesForEstimator, - const ai_u8 *pTrueIdxForEstimator, - const ai_u8 *pFalseIdxForEstimator, - const ai_handle pClassWeightsForEstimator, - const ai_array_format classWeightsFormat, - const ai_u8 *pClassNodeIdsForEstimator, - const ai_u16 nbClassWithCurrentEstimator, - const ai_u8 *pClassIdsForEstimator); - -AI_INTERNAL_API -ai_i32 decodeEstimator_LEQ_16Bits(const ai_float *pDataIn, - ai_float *pOutDataScores, - const ai_u8 *pFeatureIdxForEstimator, - const ai_float *pValuesForEstimator, - const ai_u16 *pTrueIdxForEstimator, - const ai_u16 *pFalseIdxForEstimator, - ai_handle pClassWeightsForEstimator, - const ai_array_format classWeightsFormat, - const ai_u16 *pClassNodeIdsForEstimator, - const ai_u16 nbClassWithCurrentEstimator, - const ai_u16 *pClassIdsForEstimator); - - - -AI_API_DECLARE_END - -#endif /*LAYERS_TREE_ENSEMBLE_CLASSIFIER_H*/ +/** + ****************************************************************************** + * @file layers_ml_treeensembleclassifier.h + * @author AIS + * @brief header file of AI platform TreeEnsembleClassifier datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021-2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef LAYERS_TREE_ENSEMBLE_CLASSIFIER_H +#define LAYERS_TREE_ENSEMBLE_CLASSIFIER_H + +#include "layers_common.h" +#include "layers_nl.h" + + + +/*! + * @defgroup layers_ml_treensembleclassifier Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +/* Error return codes */ +#define AI_TREE_ENSEMBLE_CLASSIFIER_ERROR_NO 0 +#define AI_TREE_ENSEMBLE_CLASSIFIER_ERROR_WRONG_IDX_FMT -1 +#define AI_TREE_ENSEMBLE_CLASSIFIER_ERROR_UNFOUND_LEAF -2 +#define AI_TREE_ENSEMBLE_CLASSIFIER_ERROR_UNSUPPORTED_BRANCH -3 +#define AI_TREE_ENSEMBLE_CLASSIFIER_ERROR_UNSUPPORTED_FEATURE -4 + +#define AI_TREE_ENSEMBLE_CLASSIFIER_DEPTH_MAX 10000 + + +/* Type of condition in the TreeEnsembleClassifier*/ +typedef enum +{ + AI_TREE_ENSEMBLE_CLASSIFIER_BRANCH_LT_IDX = 0, + AI_TREE_ENSEMBLE_CLASSIFIER_BRANCH_LEQ_IDX, + AI_TREE_ENSEMBLE_CLASSIFIER_BRANCH_EQ_IDX, + AI_TREE_ENSEMBLE_CLASSIFIER_BRANCH_END, +} ai_tree_ensenble_classifier_branch_e; + +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_tree_ensemble_classifier_ { + AI_LAYER_COMMON_FIELDS_DECLARE + func_nl nl_func; + uint8_t all_weights_are_positive; + ai_float nodes_values_scale; + ai_float nodes_values_offset; + ai_float class_weights_scale; + ai_float class_weights_offset; +} ai_layer_tree_ensemble_classifier; + + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Decodes the TreeEnsembleClassifier ML operator. + * @ingroup layers_svmreg + * @param layer tree ensemble classifier layer + */ +AI_INTERNAL_API +void forward_tree_ensemble_classifier(ai_layer *pLayer); + +AI_INTERNAL_API +ai_i32 decodeEstimator_LEQ_8Bits(const ai_float *pDataIn, + ai_float *pOutDataScores, + const ai_u8 *pFeatureIdxForEstimator, + const ai_float *pValuesForEstimator, + const ai_u8 *pTrueIdxForEstimator, + const ai_u8 *pFalseIdxForEstimator, + const ai_handle pClassWeightsForEstimator, + const ai_array_format classWeightsFormat, + const ai_u8 *pClassNodeIdsForEstimator, + const ai_u16 nbClassWithCurrentEstimator, + const ai_u8 *pClassIdsForEstimator); + +AI_INTERNAL_API +ai_i32 decodeEstimator_LEQ_16Bits(const ai_float *pDataIn, + ai_float *pOutDataScores, + const ai_u8 *pFeatureIdxForEstimator, + const ai_float *pValuesForEstimator, + const ai_u16 *pTrueIdxForEstimator, + const ai_u16 *pFalseIdxForEstimator, + ai_handle pClassWeightsForEstimator, + const ai_array_format classWeightsFormat, + const ai_u16 *pClassNodeIdsForEstimator, + const ai_u16 nbClassWithCurrentEstimator, + const ai_u16 *pClassIdsForEstimator); + + + +AI_API_DECLARE_END + +#endif /*LAYERS_TREE_ENSEMBLE_CLASSIFIER_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_treeensembleregressor.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_treeensembleregressor.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_treeensembleregressor.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_treeensembleregressor.h index 605ba2b5..6515de87 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_treeensembleregressor.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_ml_treeensembleregressor.h @@ -1,59 +1,59 @@ -/** - ****************************************************************************** - * @file layers_svmregressor.h - * @author AIS - * @brief header file of AI platform SVM Regressor datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -#ifndef LAYERS_TREE_ENSEMBLE_REGRESSOR_H -#define LAYERS_TREE_ENSEMBLE_REGRESSOR_H - -#include "layers_common.h" -#include "layers_ml_treeensembleclassifier.h" -#include "layers_nl.h" - -/*! - * @defgroup layers_svmreg Layers Definitions - * @brief definition - * - */ - -AI_API_DECLARE_BEGIN - -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_tree_ensemble_regressor_ { - AI_LAYER_COMMON_FIELDS_DECLARE - func_nl nl_func; - uint8_t all_weights_are_positive; - ai_float nodes_values_offset; - ai_float nodes_values_scale; - ai_float target_weights_offset; - ai_float target_weights_scale; -} ai_layer_tree_ensemble_regressor; - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Decodes the TreeEnsembleRegressor ML operator. - * @ingroup layers_svmreg - * @param layer tree ensemble regressor layer - */ -AI_INTERNAL_API -void forward_tree_ensemble_regressor(ai_layer *pLayer); - - -AI_API_DECLARE_END - -#endif /*LAYERS_SVMREGRESSOR_H*/ +/** + ****************************************************************************** + * @file layers_svmregressor.h + * @author AIS + * @brief header file of AI platform SVM Regressor datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef LAYERS_TREE_ENSEMBLE_REGRESSOR_H +#define LAYERS_TREE_ENSEMBLE_REGRESSOR_H + +#include "layers_common.h" +#include "layers_ml_treeensembleclassifier.h" +#include "layers_nl.h" + +/*! + * @defgroup layers_svmreg Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_tree_ensemble_regressor_ { + AI_LAYER_COMMON_FIELDS_DECLARE + func_nl nl_func; + uint8_t all_weights_are_positive; + ai_float nodes_values_offset; + ai_float nodes_values_scale; + ai_float target_weights_offset; + ai_float target_weights_scale; +} ai_layer_tree_ensemble_regressor; + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Decodes the TreeEnsembleRegressor ML operator. + * @ingroup layers_svmreg + * @param layer tree ensemble regressor layer + */ +AI_INTERNAL_API +void forward_tree_ensemble_regressor(ai_layer *pLayer); + + +AI_API_DECLARE_END + +#endif /*LAYERS_SVMREGRESSOR_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_nl.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_nl.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_nl.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_nl.h index 124203a7..3cd12830 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_nl.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_nl.h @@ -1,1126 +1,1126 @@ -/** - ****************************************************************************** - * @file layers_nl.h - * @author AST Embedded Analytics Research Platform - * @brief header file of AI platform nonlinearity layers datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2018 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LAYERS_NL_H -#define LAYERS_NL_H - -#include "layers_common.h" -#include "lite_internal_apis.h" - -/*! - * @defgroup layers_nl Normalization Layers Definitions - * @brief definition - * - */ - -AI_API_DECLARE_BEGIN - -/*! - * @struct ai_layer_nl - * @ingroup layers_nl - * @brief Generic Nonlinearity layer - * - * The type of nonlinearity is handled by the specific forward function. - * It is a sequential layer. see @ref ai_layer - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_nl_ { - AI_LAYER_COMMON_FIELDS_DECLARE - AI_CONST ai_array* nl_params; /*!< associated parameters array */ -} ai_layer_nl; - -/*! - * @struct ai_layer_sm - * @ingroup layers_nl - * @brief Softmax Nonlinearity layer - * - * It is a sequential layer. see @ref ai_layer - */ -typedef ai_layer_nl ai_layer_sm; - -/*! - * @typedef (*func_nl) - * @ingroup layers_nl - * @brief Fuction pointer for generic non linear transform - * this function pointer abstracts a generic non linear layer. - * see @ref nl_func_tanh_array_f32 and similar as examples. - */ -//typedef void (*func_nl)(ai_array *out, const ai_array *in, -// const ai_size size, const ai_handle params); -typedef void (*func_nl)(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Softmax pooling computed on a single float channel - * @ingroup layers_nl - * @param out opaque handler to float output channel - * @param in opaque handler to float input channel - * @param channel_size number of elements of the input channel - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_sm_channel_f32(ai_tensor *out, const ai_tensor *in, - const ai_size channel_size, const ai_handle params); - -/*! - * @brief Softmax normalization computed on an array of float channels - * @ingroup layers_nl - * @param out opaque handler to float output channel array - * @param in opaque handler to float input channel array - * @param in_size total size (number of elements) to process on the input - * @param channel_size number of elements of the input channel - * @param in_channel_step number of elements to move to next input element - * @param out_channel_step number of elements to move to next output element - */ -AI_INTERNAL_API -void nl_func_sm_array_f32(ai_tensor *out, ai_tensor *in, - const ai_size in_size, - const ai_size channel_size, - const ai_size in_channel_step, - const ai_size out_channel_step); - -/*! - * @brief Softmax zero pooling computed on a single float channel - * @ingroup layers_nl - * @param out opaque handler to float output channel - * @param in opaque handler to float input channel - * @param channel_size number of elements of the input channel - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_sm_zero_channel_f32(ai_tensor *out, const ai_tensor *in, - const ai_size channel_size, const ai_handle params); - -/*! - * @brief Probit non linearity - * @ingroup layers_nl - * @param out opaque handler to float output channel - * @param in opaque handler to float input channel - * @param channel_size number of elements of the input channel - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_probit_f32(ai_tensor *out, const ai_tensor *in, - const ai_size channel_size, const ai_handle params); - - -/*! - * @brief Computes the tanh function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_tanh_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the tanh function on a fixed point data array - * @ingroup layers_nl - * @param in opaque handler to input elements to process - * @param out opaque handler to output elements - * @param size total size (number of elements) to process on the input - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_tanh_array_fixed(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - - -/*! - * @brief Computes the sigmoid function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_sigmoid_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the sigmoid function on a fixed point data array - * @ingroup layers_nl - * @param in opaque handler to input elements to process - * @param out opaque handler to output elements - * @param size total size (number of elements) to process on the input - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_sigmoid_array_fixed(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - - -/*! - * @brief Computes the hard sigmoid function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_hard_sigmoid_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); -/*! - * @brief Computes the logistic function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_logistic_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); -/*! - * @brief Computes the swish function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_swish_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the hard swish function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_hard_swish_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the gelu function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_gelu_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the absolute value function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_abs_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the cosine function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_cos_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the inverse cosine function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_acos_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the hyperbolic cosine function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_cosh_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the inverse hyperbolic cosine function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_acosh_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the sine function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_sin_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the inverse sine function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_asin_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the hyperbolic sine function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_sinh_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the inverse hyperbolic sine function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_asinh_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the tangent function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_tan_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the inverse tangent function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_atan_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the inverse hyperbolic tangent function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_atanh_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the error function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_erf_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the natural logarithm function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_log_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the reciprocal square root function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_rsqrt_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the squarefunction on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_square_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the floor function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_floor_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the ceil function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_ceil_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the rounding function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_round_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the exponential function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_exp_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the sign negation function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_neg_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the sign negation function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_not_array_bool(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - - -/*! - * @brief Computes the reciprocal function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_reciprocal_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the square root function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_sqrt_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the soft plus function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - */ -AI_INTERNAL_API -void nl_func_soft_plus_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the soft sign function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_soft_sign_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the sign function on a single float element. - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - */ -AI_INTERNAL_API -void nl_func_sign_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the clip function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_clip_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the hardmax function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param axis direction of the max index to be searched - */ -AI_INTERNAL_API -void nl_func_hardmax_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_shape *shape, const ai_handle params); - -/*! - * @brief Computes the generic relu function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_relu_generic_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the thresholded relu function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_relu_thresholded_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the relu function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_relu_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the relu function on a fixed point data array - * @ingroup layers_nl - * @param in opaque handler to input elements to process - * @param out opaque handler to output elements - * @param size total size (number of elements) to process on the input - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_relu_array_fixed(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the relu function on an integer-quantized data array - * @ingroup layers_nl - * @param in opaque handler to input elements to process - * @param out opaque handler to output elements - * @param size total size (number of elements) to process on the input - * @param params opaque handler to optional nl parameters - */ -void nl_func_relu_array_integer(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the clip function on an integer-quantized data array - * @ingroup layers_nl - * @param in opaque handler to input elements to process - * @param out opaque handler to output elements - * @param size total size (number of elements) to process on the input - * @param params opaque handler to optional nl parameters - */ -void nl_func_clip_array_integer(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the activation function on an integer-quantized data array - * @ingroup layers_nl - * @param in opaque handler to input elements to process - * @param out opaque handler to output elements - * @param size total size (number of elements) to process on the input - * @param params opaque handler to generated and used LUT - */ -void nl_func_array_integer(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the elu function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_elu_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the max relu function on a fixed point data array - * @ingroup layers_nl - * @param in opaque handler to input elements to process - * @param out opaque handler to output elements - * @param size total size (number of elements) to process on the input - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_relu_max_array_fixed(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the selu function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size number of elements in the input buffer - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_selu_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the prelu function on a float data array - * @ingroup layers_nl - * @param in opaque handler to float, size should be 1 - * @param slope opaque handler to float, size should be 1 - * @param out opaque handler to float output elem - * @param size size of the input data in bytes - * @param params opaque handler to optional nl parameters - */ -AI_INTERNAL_API -void nl_func_prelu_array_f32(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/*! - * @brief Computes the prelu function on an integer-quantized data array - * @ingroup layers_nl - * @param in opaque handler to input elements to process - * @param out opaque handler to output elements - * @param size total size (number of elements) to process on the input - * @param params opaque handler to optional nl parameters - */ -void nl_func_prelu_array_integer(ai_tensor *out, const ai_tensor *in, - const ai_size size, const ai_handle params); - -/******************************************************************************/ -/** Forward Functions Section **/ -/******************************************************************************/ - -/*! - * @brief Computes the activations of a ReLU nonlinear layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_relu(ai_layer* layer); - -/*! - * @brief Computes the activations of a fixed point ReLU nonlinear layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_relu_fixed(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a integer-quantized ReLU nonlinear layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_relu_integer(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a clip integer-quantized nonlinear layer. - * @ingroup layers_nl - * @param pLayer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_clip_integer(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a ReLU6 nonlinear layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_relu_thresholded(ai_layer* layer); - -/*! - * @brief Computes the activations of a fixed point max ReLU layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_relu_max_fixed(ai_layer *pLayer); - - -/*! - * @brief Computes the activations of a ELU nonlinear layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_elu(ai_layer* layer); - -/*! - * @brief Computes the activations of a SELU nonlinear layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_selu(ai_layer* layer); - -/*! - * @brief Computes the activations of a PRELU nonlinear layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_prelu(ai_layer* layer); - -/*! - * @brief Computes the activations of a binary tanh (sign) nonlinear layer. - * @ingroup layers - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_sign(ai_layer* layer); - -/*! - * @brief Computes the activations of a clip nonlinear layer. - * @ingroup layers - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_clip(ai_layer* layer); - -/*! - * @brief Computes the activations of a sigmoid nonlinear layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_sigmoid(ai_layer* layer); - -/*! - * @brief Computes the activations of a fixed point sigmoid nonlinear layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_sigmoid_fixed(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a hard sigmoid nonlinear layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_hard_sigmoid(ai_layer* layer); - -/*! - * @brief Computes the activations of a swish nonlinear layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_swish(ai_layer* layer); - -/*! - * @brief Computes the activations of a hard swish nonlinear layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_hard_swish(ai_layer* layer); - -/*! - * @brief Computes the activations of a gelu nonlinear layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_gelu(ai_layer* layer); - -/*! - * @brief Computes the activations of an exponential nonlinear layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_exp(ai_layer* layer); - -/*! - * @brief Computes the activations of an square root nonlinear layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_sqrt(ai_layer* layer); - -/*! - * @brief Computes the activations of a soft plus nonlinear layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_soft_plus(ai_layer* layer); - -/*! - * @brief Computes the activations of a soft sign nonlinear layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_soft_sign(ai_layer* layer); - -/*! - * @brief Computes the activations of a cosine (cos) layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_cos(ai_layer* layer); - -/*! - * @brief Computes the activations of a inverse cosine (acos) layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_acos(ai_layer* layer); - -/*! - * @brief Computes the activations of a hyperbolic cosine (cosh) layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_cosh(ai_layer* layer); - -/*! - * @brief Computes the activations of a inverse hyperbolic cosine (acosh) layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_acosh(ai_layer* layer); - -/*! - * @brief Computes the activations of a sine (sin) layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_sin(ai_layer* layer); - -/*! - * @brief Computes the activations of a inverse sine (asin) layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_asin(ai_layer* layer); - -/*! - * @brief Computes the activations of a hyperbolic sine (sinh) layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_sinh(ai_layer* layer); - -/*! - * @brief Computes the activations of a inverse hyperbolic sine (asinh) layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_asinh(ai_layer* layer); - -/*! - * @brief Computes the activations of a tangent (tan) layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_tan(ai_layer* layer); - -/*! - * @brief Computes the activations of a inverse tangent (atan) layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_atan(ai_layer* layer); - -/*! - * @brief Computes the activations of a hyperbolic tangent (tanh) layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_tanh(ai_layer* layer); - -/*! - * @brief Computes the activations of a inverse hyperbolic tangent (atanh) layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_atanh(ai_layer* layer); - -/*! - * @brief Computes the activations of a fixed point tanh nonlinear layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_tanh_fixed(ai_layer *pLayer); - -/*! - * @brief Computes the activations of a error function (erf) layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_erf(ai_layer* layer); - -/*! - * @brief Computes the activations of a natural logarithm (log) layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_log(ai_layer* layer); - -/*! - * @brief Computes the activations of a reciprocal square root (rsqrt) layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_rsqrt(ai_layer* layer); - -/*! - * @brief Computes the activations of a square layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_square(ai_layer* layer); - -/*! - * @brief Computes the activations of an absolute value (abs) layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_abs(ai_layer* layer); - -/*! - * @brief Computes the activations of a ceil layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_ceil(ai_layer* layer); - -/*! - * @brief Computes the activations of a floor layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_floor(ai_layer* layer); - -/*! - * @brief Computes the activations of a rounding layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_round(ai_layer* layer); - -/*! - * @brief Computes the activations of a sign negation (neg) layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_neg(ai_layer* layer); -/*! - * @brief Computes the activations of a sign negation (not) layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_not(ai_layer* layer); - - -/*! - * @brief Computes the activations of a reciprocal layer. - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_reciprocal(ai_layer* layer); - -/*! - * @brief Hardmax on an input tensors - * @ingroup layers_generic - * @param layer the hardmax layer - */ -AI_INTERNAL_API -void forward_hardmax(ai_layer* layer); - -/*! - * @brief Computes the activations of a softmax nonlinear layer. - * @ingroup layers_nl - * @param layer the softmax (sm) layer - */ -AI_INTERNAL_API -void forward_sm(ai_layer* layer); - -/*! - * @brief Computes the activations of a softmax nonlinear layer (integer version). - * @ingroup layers_nl - * @param layer the softmax (sm) layer - */ -AI_INTERNAL_API -void forward_sm_integer(ai_layer* layer); - -/*! - * @brief Computes the activations of an integer quantized nonlinear layer. - * Non linear operation is function of used LUT defined through - * (pLayer->nl_params->data) - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_nl_integer(ai_layer *pLayer); - -/*! - * @brief Computes the activations of an integer quantized PReLu. - * Slope params are located like weights, not params because they are - * quantized - * @ingroup layers_nl - * @param layer the nonlinear (nl) layer - */ -AI_INTERNAL_API -void forward_prelu_integer(ai_layer *pLayer); - -AI_API_DECLARE_END - -#endif /*LAYERS_NL_H*/ +/** + ****************************************************************************** + * @file layers_nl.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform nonlinearity layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_NL_H +#define LAYERS_NL_H + +#include "layers_common.h" +#include "lite_internal_apis.h" + +/*! + * @defgroup layers_nl Normalization Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_nl + * @ingroup layers_nl + * @brief Generic Nonlinearity layer + * + * The type of nonlinearity is handled by the specific forward function. + * It is a sequential layer. see @ref ai_layer + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_nl_ { + AI_LAYER_COMMON_FIELDS_DECLARE + AI_CONST ai_array* nl_params; /*!< associated parameters array */ +} ai_layer_nl; + +/*! + * @struct ai_layer_sm + * @ingroup layers_nl + * @brief Softmax Nonlinearity layer + * + * It is a sequential layer. see @ref ai_layer + */ +typedef ai_layer_nl ai_layer_sm; + +/*! + * @typedef (*func_nl) + * @ingroup layers_nl + * @brief Fuction pointer for generic non linear transform + * this function pointer abstracts a generic non linear layer. + * see @ref nl_func_tanh_array_f32 and similar as examples. + */ +//typedef void (*func_nl)(ai_array *out, const ai_array *in, +// const ai_size size, const ai_handle params); +typedef void (*func_nl)(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Softmax pooling computed on a single float channel + * @ingroup layers_nl + * @param out opaque handler to float output channel + * @param in opaque handler to float input channel + * @param channel_size number of elements of the input channel + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_sm_channel_f32(ai_tensor *out, const ai_tensor *in, + const ai_size channel_size, const ai_handle params); + +/*! + * @brief Softmax normalization computed on an array of float channels + * @ingroup layers_nl + * @param out opaque handler to float output channel array + * @param in opaque handler to float input channel array + * @param in_size total size (number of elements) to process on the input + * @param channel_size number of elements of the input channel + * @param in_channel_step number of elements to move to next input element + * @param out_channel_step number of elements to move to next output element + */ +AI_INTERNAL_API +void nl_func_sm_array_f32(ai_tensor *out, ai_tensor *in, + const ai_size in_size, + const ai_size channel_size, + const ai_size in_channel_step, + const ai_size out_channel_step); + +/*! + * @brief Softmax zero pooling computed on a single float channel + * @ingroup layers_nl + * @param out opaque handler to float output channel + * @param in opaque handler to float input channel + * @param channel_size number of elements of the input channel + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_sm_zero_channel_f32(ai_tensor *out, const ai_tensor *in, + const ai_size channel_size, const ai_handle params); + +/*! + * @brief Probit non linearity + * @ingroup layers_nl + * @param out opaque handler to float output channel + * @param in opaque handler to float input channel + * @param channel_size number of elements of the input channel + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_probit_f32(ai_tensor *out, const ai_tensor *in, + const ai_size channel_size, const ai_handle params); + + +/*! + * @brief Computes the tanh function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_tanh_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the tanh function on a fixed point data array + * @ingroup layers_nl + * @param in opaque handler to input elements to process + * @param out opaque handler to output elements + * @param size total size (number of elements) to process on the input + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_tanh_array_fixed(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + + +/*! + * @brief Computes the sigmoid function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_sigmoid_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the sigmoid function on a fixed point data array + * @ingroup layers_nl + * @param in opaque handler to input elements to process + * @param out opaque handler to output elements + * @param size total size (number of elements) to process on the input + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_sigmoid_array_fixed(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + + +/*! + * @brief Computes the hard sigmoid function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_hard_sigmoid_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); +/*! + * @brief Computes the logistic function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_logistic_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); +/*! + * @brief Computes the swish function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_swish_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the hard swish function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_hard_swish_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the gelu function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_gelu_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the absolute value function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_abs_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the cosine function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_cos_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the inverse cosine function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_acos_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the hyperbolic cosine function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_cosh_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the inverse hyperbolic cosine function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_acosh_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the sine function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_sin_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the inverse sine function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_asin_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the hyperbolic sine function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_sinh_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the inverse hyperbolic sine function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_asinh_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the tangent function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_tan_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the inverse tangent function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_atan_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the inverse hyperbolic tangent function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_atanh_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the error function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_erf_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the natural logarithm function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_log_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the reciprocal square root function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_rsqrt_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the squarefunction on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_square_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the floor function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_floor_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the ceil function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_ceil_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the rounding function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_round_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the exponential function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_exp_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the sign negation function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_neg_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the sign negation function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_not_array_bool(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + + +/*! + * @brief Computes the reciprocal function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_reciprocal_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the square root function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_sqrt_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the soft plus function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + */ +AI_INTERNAL_API +void nl_func_soft_plus_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the soft sign function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_soft_sign_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the sign function on a single float element. + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + */ +AI_INTERNAL_API +void nl_func_sign_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the clip function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_clip_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the hardmax function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param axis direction of the max index to be searched + */ +AI_INTERNAL_API +void nl_func_hardmax_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_shape *shape, const ai_handle params); + +/*! + * @brief Computes the generic relu function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_relu_generic_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the thresholded relu function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_relu_thresholded_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the relu function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_relu_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the relu function on a fixed point data array + * @ingroup layers_nl + * @param in opaque handler to input elements to process + * @param out opaque handler to output elements + * @param size total size (number of elements) to process on the input + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_relu_array_fixed(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the relu function on an integer-quantized data array + * @ingroup layers_nl + * @param in opaque handler to input elements to process + * @param out opaque handler to output elements + * @param size total size (number of elements) to process on the input + * @param params opaque handler to optional nl parameters + */ +void nl_func_relu_array_integer(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the clip function on an integer-quantized data array + * @ingroup layers_nl + * @param in opaque handler to input elements to process + * @param out opaque handler to output elements + * @param size total size (number of elements) to process on the input + * @param params opaque handler to optional nl parameters + */ +void nl_func_clip_array_integer(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the activation function on an integer-quantized data array + * @ingroup layers_nl + * @param in opaque handler to input elements to process + * @param out opaque handler to output elements + * @param size total size (number of elements) to process on the input + * @param params opaque handler to generated and used LUT + */ +void nl_func_array_integer(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the elu function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_elu_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the max relu function on a fixed point data array + * @ingroup layers_nl + * @param in opaque handler to input elements to process + * @param out opaque handler to output elements + * @param size total size (number of elements) to process on the input + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_relu_max_array_fixed(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the selu function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size number of elements in the input buffer + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_selu_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the prelu function on a float data array + * @ingroup layers_nl + * @param in opaque handler to float, size should be 1 + * @param slope opaque handler to float, size should be 1 + * @param out opaque handler to float output elem + * @param size size of the input data in bytes + * @param params opaque handler to optional nl parameters + */ +AI_INTERNAL_API +void nl_func_prelu_array_f32(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/*! + * @brief Computes the prelu function on an integer-quantized data array + * @ingroup layers_nl + * @param in opaque handler to input elements to process + * @param out opaque handler to output elements + * @param size total size (number of elements) to process on the input + * @param params opaque handler to optional nl parameters + */ +void nl_func_prelu_array_integer(ai_tensor *out, const ai_tensor *in, + const ai_size size, const ai_handle params); + +/******************************************************************************/ +/** Forward Functions Section **/ +/******************************************************************************/ + +/*! + * @brief Computes the activations of a ReLU nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_relu(ai_layer* layer); + +/*! + * @brief Computes the activations of a fixed point ReLU nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_relu_fixed(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a integer-quantized ReLU nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_relu_integer(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a clip integer-quantized nonlinear layer. + * @ingroup layers_nl + * @param pLayer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_clip_integer(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a ReLU6 nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_relu_thresholded(ai_layer* layer); + +/*! + * @brief Computes the activations of a fixed point max ReLU layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_relu_max_fixed(ai_layer *pLayer); + + +/*! + * @brief Computes the activations of a ELU nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_elu(ai_layer* layer); + +/*! + * @brief Computes the activations of a SELU nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_selu(ai_layer* layer); + +/*! + * @brief Computes the activations of a PRELU nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_prelu(ai_layer* layer); + +/*! + * @brief Computes the activations of a binary tanh (sign) nonlinear layer. + * @ingroup layers + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_sign(ai_layer* layer); + +/*! + * @brief Computes the activations of a clip nonlinear layer. + * @ingroup layers + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_clip(ai_layer* layer); + +/*! + * @brief Computes the activations of a sigmoid nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_sigmoid(ai_layer* layer); + +/*! + * @brief Computes the activations of a fixed point sigmoid nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_sigmoid_fixed(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a hard sigmoid nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_hard_sigmoid(ai_layer* layer); + +/*! + * @brief Computes the activations of a swish nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_swish(ai_layer* layer); + +/*! + * @brief Computes the activations of a hard swish nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_hard_swish(ai_layer* layer); + +/*! + * @brief Computes the activations of a gelu nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_gelu(ai_layer* layer); + +/*! + * @brief Computes the activations of an exponential nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_exp(ai_layer* layer); + +/*! + * @brief Computes the activations of an square root nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_sqrt(ai_layer* layer); + +/*! + * @brief Computes the activations of a soft plus nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_soft_plus(ai_layer* layer); + +/*! + * @brief Computes the activations of a soft sign nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_soft_sign(ai_layer* layer); + +/*! + * @brief Computes the activations of a cosine (cos) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_cos(ai_layer* layer); + +/*! + * @brief Computes the activations of a inverse cosine (acos) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_acos(ai_layer* layer); + +/*! + * @brief Computes the activations of a hyperbolic cosine (cosh) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_cosh(ai_layer* layer); + +/*! + * @brief Computes the activations of a inverse hyperbolic cosine (acosh) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_acosh(ai_layer* layer); + +/*! + * @brief Computes the activations of a sine (sin) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_sin(ai_layer* layer); + +/*! + * @brief Computes the activations of a inverse sine (asin) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_asin(ai_layer* layer); + +/*! + * @brief Computes the activations of a hyperbolic sine (sinh) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_sinh(ai_layer* layer); + +/*! + * @brief Computes the activations of a inverse hyperbolic sine (asinh) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_asinh(ai_layer* layer); + +/*! + * @brief Computes the activations of a tangent (tan) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_tan(ai_layer* layer); + +/*! + * @brief Computes the activations of a inverse tangent (atan) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_atan(ai_layer* layer); + +/*! + * @brief Computes the activations of a hyperbolic tangent (tanh) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_tanh(ai_layer* layer); + +/*! + * @brief Computes the activations of a inverse hyperbolic tangent (atanh) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_atanh(ai_layer* layer); + +/*! + * @brief Computes the activations of a fixed point tanh nonlinear layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_tanh_fixed(ai_layer *pLayer); + +/*! + * @brief Computes the activations of a error function (erf) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_erf(ai_layer* layer); + +/*! + * @brief Computes the activations of a natural logarithm (log) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_log(ai_layer* layer); + +/*! + * @brief Computes the activations of a reciprocal square root (rsqrt) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_rsqrt(ai_layer* layer); + +/*! + * @brief Computes the activations of a square layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_square(ai_layer* layer); + +/*! + * @brief Computes the activations of an absolute value (abs) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_abs(ai_layer* layer); + +/*! + * @brief Computes the activations of a ceil layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_ceil(ai_layer* layer); + +/*! + * @brief Computes the activations of a floor layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_floor(ai_layer* layer); + +/*! + * @brief Computes the activations of a rounding layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_round(ai_layer* layer); + +/*! + * @brief Computes the activations of a sign negation (neg) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_neg(ai_layer* layer); +/*! + * @brief Computes the activations of a sign negation (not) layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_not(ai_layer* layer); + + +/*! + * @brief Computes the activations of a reciprocal layer. + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_reciprocal(ai_layer* layer); + +/*! + * @brief Hardmax on an input tensors + * @ingroup layers_generic + * @param layer the hardmax layer + */ +AI_INTERNAL_API +void forward_hardmax(ai_layer* layer); + +/*! + * @brief Computes the activations of a softmax nonlinear layer. + * @ingroup layers_nl + * @param layer the softmax (sm) layer + */ +AI_INTERNAL_API +void forward_sm(ai_layer* layer); + +/*! + * @brief Computes the activations of a softmax nonlinear layer (integer version). + * @ingroup layers_nl + * @param layer the softmax (sm) layer + */ +AI_INTERNAL_API +void forward_sm_integer(ai_layer* layer); + +/*! + * @brief Computes the activations of an integer quantized nonlinear layer. + * Non linear operation is function of used LUT defined through + * (pLayer->nl_params->data) + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_nl_integer(ai_layer *pLayer); + +/*! + * @brief Computes the activations of an integer quantized PReLu. + * Slope params are located like weights, not params because they are + * quantized + * @ingroup layers_nl + * @param layer the nonlinear (nl) layer + */ +AI_INTERNAL_API +void forward_prelu_integer(ai_layer *pLayer); + +AI_API_DECLARE_END + +#endif /*LAYERS_NL_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_norm.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_norm.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_norm.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_norm.h index f6095032..4d88cbb8 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_norm.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_norm.h @@ -1,205 +1,205 @@ -/** - ****************************************************************************** - * @file layers_norm.h - * @author AST Embedded Analytics Research Platform - * @brief header file of AI platform normalization layers datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2018 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LAYERS_NORM_H -#define LAYERS_NORM_H - -#include "layers_common.h" - -/*! - * @defgroup layers_norm Normalization Layers Definitions - * @brief definition - * - */ - -AI_API_DECLARE_BEGIN - -/*! - * @struct ai_layer_bn - * @ingroup layers_norm - * @brief Batch normalization (scale with bias) layer - */ -typedef ai_layer_base ai_layer_bn; - -/*! - * @struct ai_layer_lrn - * @ingroup layers_norm - * @brief Local Response Normalization layer - * - * Divides each element by a scale factor computed - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_lrn_ { - AI_LAYER_COMMON_FIELDS_DECLARE - ai_u32 local_size; /*!< size of the normalization window */ - ai_float k; /*!< bias term */ - ai_float alpha; /*!< input scale */ - ai_float beta; /*!< scale exponent */ -} ai_layer_lrn; - -/*! - * @enum ai_norm_type_e - * @ingroup layers_norm - * @brief store the type of normalization algorithm to apply -*/ -typedef enum ai_norm_type_ { - NONE = 0, - L1 = 1, - L2 = 2, - MAX = 3, -} ai_norm_type_e; - -/*! - * @struct ai_layer_norm - * @ingroup layers_norm - * @brief Lp Normalization layer - * - * Normalizes the tensor along the 'axis' direction using the Lp norm. - * Optionally divides the result by the number of the elements. - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_norm_ { - AI_LAYER_COMMON_FIELDS_DECLARE - ai_shape_idx axis; /*! normalization axis */ - ai_float exponent; /*!< normalization exponent p */ - ai_bool scale; /*!< multiplies by the pth root of the number of elements */ - ai_norm_type_e norm_type; -} ai_layer_norm; - - -/*! - * @brief Local response normalization computed on a float array - * @ingroup layers_norm - * @param out opaque handler to float output channel - * @param in opaque handler to float input channel - * @param pad amount of padding for the channels - */ -AI_INTERNAL_API -void func_lrn_array_f32(ai_handle out, const ai_handle in, - const ai_size in_size, const ai_size channel_size, - const ai_i32 pad, const ai_float k, - const ai_float alpha, const ai_float beta); - -/*! - * @brief Lp normalization computed on a float array - * @ingroup layers_norm - * @param out opaque handler to float output channel - * @param in opaque handler to float input channel - * @param exponent p exponent for the Lp normalization - * @param axis_stride stride (in array elements) of the normalization axis - * @param axis_size size of the normalization axis - * @param outer_size number of tensor slices (including the normalization axis) - * on which compute the normalization - */ -AI_INTERNAL_API -void func_norm_array_f32(ai_handle out, const ai_handle in, - const ai_float exponent, - const ai_float norm, - const ai_size axis_stride, - const ai_size axis_size, - const ai_size outer_size); - -/*! - * @brief Max normalization computed on float array - * @ingroup layers_norm - * @param out opaque handler to float output channel - * @param in opaque handler to float input channel - * @param axis_stride stride (in array elements) of the normalization axis - * @param axis_size size of the normalization axis - * @param outer_size number of tensor slices (including the normalization axis) - */ -AI_INTERNAL_API -void func_norm_max_array_f32(ai_handle out, const ai_handle in, - const ai_float norm, - const ai_size axis_size, - const ai_size n_el); - -/*! - * @brief Fast L2 normalization computed on a float array - * @ingroup layers_norm - * @param out opaque handler to float output channel - * @param in opaque handler to float input channel - * @param axis_size size of the normalization axis - * @param n_el total number of elements in the tensor - */ -AI_INTERNAL_API -void func_norm_l2_fast_array_f32(ai_handle out, const ai_handle in, - const ai_float norm, - const ai_size axis_size, - const ai_size outer_size); - -/*! - * @brief Fast L1 normalization computed on a float array - * @ingroup layers_norm - * @param out opaque handler to float output channel - * @param in opaque handler to float input channel - * @param axis_size size of the normalization axis - * @param n_el total number of elements in the tensor - */ -AI_INTERNAL_API -void func_norm_l1_fast_array_f32(ai_handle out, const ai_handle in, - const ai_float norm, - const ai_size axis_size, - const ai_size n_el); - - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Computes the activations of a batchnorm (scale + bias) layer. - * @ingroup layers_norm - * @param layer the batch normalization (bn) layer - */ -AI_INTERNAL_API -void forward_bn(ai_layer* layer); - -/*! - * @brief Computes the activations of a batchnorm (scale + bias) layer with - * integer format - * @ingroup layers_norm - * @param layer the batch normalization (bn) layer - */ -AI_INTERNAL_API -void forward_bn_integer(ai_layer* layer); - -/*! - * @brief Computes the activations of a Local Response Normalization Layer. - * @ingroup layers_norm - * @param layer the local response normalization (lrn) layer - */ -AI_INTERNAL_API -void forward_lrn(ai_layer* layer); - -/*! - * @brief Computes the activations of a normalization layer. - * @ingroup layers_norm - * @param layer the normalization (norm) layer - */ -AI_INTERNAL_API -void forward_norm(ai_layer* layer); - -/*! - * @brief Batch Normalization with 16-bit input, 16-bit threshold and binary output. - * It is implemented using a threshold, and this is possible because the output is binary. - * @param layer the batch normalization layer - */ -AI_INTERNAL_API -void forward_bn_is16os1ws16(ai_layer *pLayer); - -AI_API_DECLARE_END - -#endif /*LAYERS_NORM_H*/ +/** + ****************************************************************************** + * @file layers_norm.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform normalization layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_NORM_H +#define LAYERS_NORM_H + +#include "layers_common.h" + +/*! + * @defgroup layers_norm Normalization Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_bn + * @ingroup layers_norm + * @brief Batch normalization (scale with bias) layer + */ +typedef ai_layer_base ai_layer_bn; + +/*! + * @struct ai_layer_lrn + * @ingroup layers_norm + * @brief Local Response Normalization layer + * + * Divides each element by a scale factor computed + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_lrn_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_u32 local_size; /*!< size of the normalization window */ + ai_float k; /*!< bias term */ + ai_float alpha; /*!< input scale */ + ai_float beta; /*!< scale exponent */ +} ai_layer_lrn; + +/*! + * @enum ai_norm_type_e + * @ingroup layers_norm + * @brief store the type of normalization algorithm to apply +*/ +typedef enum ai_norm_type_ { + NONE = 0, + L1 = 1, + L2 = 2, + MAX = 3, +} ai_norm_type_e; + +/*! + * @struct ai_layer_norm + * @ingroup layers_norm + * @brief Lp Normalization layer + * + * Normalizes the tensor along the 'axis' direction using the Lp norm. + * Optionally divides the result by the number of the elements. + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_norm_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_shape_idx axis; /*! normalization axis */ + ai_float exponent; /*!< normalization exponent p */ + ai_bool scale; /*!< multiplies by the pth root of the number of elements */ + ai_norm_type_e norm_type; +} ai_layer_norm; + + +/*! + * @brief Local response normalization computed on a float array + * @ingroup layers_norm + * @param out opaque handler to float output channel + * @param in opaque handler to float input channel + * @param pad amount of padding for the channels + */ +AI_INTERNAL_API +void func_lrn_array_f32(ai_handle out, const ai_handle in, + const ai_size in_size, const ai_size channel_size, + const ai_i32 pad, const ai_float k, + const ai_float alpha, const ai_float beta); + +/*! + * @brief Lp normalization computed on a float array + * @ingroup layers_norm + * @param out opaque handler to float output channel + * @param in opaque handler to float input channel + * @param exponent p exponent for the Lp normalization + * @param axis_stride stride (in array elements) of the normalization axis + * @param axis_size size of the normalization axis + * @param outer_size number of tensor slices (including the normalization axis) + * on which compute the normalization + */ +AI_INTERNAL_API +void func_norm_array_f32(ai_handle out, const ai_handle in, + const ai_float exponent, + const ai_float norm, + const ai_size axis_stride, + const ai_size axis_size, + const ai_size outer_size); + +/*! + * @brief Max normalization computed on float array + * @ingroup layers_norm + * @param out opaque handler to float output channel + * @param in opaque handler to float input channel + * @param axis_stride stride (in array elements) of the normalization axis + * @param axis_size size of the normalization axis + * @param outer_size number of tensor slices (including the normalization axis) + */ +AI_INTERNAL_API +void func_norm_max_array_f32(ai_handle out, const ai_handle in, + const ai_float norm, + const ai_size axis_size, + const ai_size n_el); + +/*! + * @brief Fast L2 normalization computed on a float array + * @ingroup layers_norm + * @param out opaque handler to float output channel + * @param in opaque handler to float input channel + * @param axis_size size of the normalization axis + * @param n_el total number of elements in the tensor + */ +AI_INTERNAL_API +void func_norm_l2_fast_array_f32(ai_handle out, const ai_handle in, + const ai_float norm, + const ai_size axis_size, + const ai_size outer_size); + +/*! + * @brief Fast L1 normalization computed on a float array + * @ingroup layers_norm + * @param out opaque handler to float output channel + * @param in opaque handler to float input channel + * @param axis_size size of the normalization axis + * @param n_el total number of elements in the tensor + */ +AI_INTERNAL_API +void func_norm_l1_fast_array_f32(ai_handle out, const ai_handle in, + const ai_float norm, + const ai_size axis_size, + const ai_size n_el); + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Computes the activations of a batchnorm (scale + bias) layer. + * @ingroup layers_norm + * @param layer the batch normalization (bn) layer + */ +AI_INTERNAL_API +void forward_bn(ai_layer* layer); + +/*! + * @brief Computes the activations of a batchnorm (scale + bias) layer with + * integer format + * @ingroup layers_norm + * @param layer the batch normalization (bn) layer + */ +AI_INTERNAL_API +void forward_bn_integer(ai_layer* layer); + +/*! + * @brief Computes the activations of a Local Response Normalization Layer. + * @ingroup layers_norm + * @param layer the local response normalization (lrn) layer + */ +AI_INTERNAL_API +void forward_lrn(ai_layer* layer); + +/*! + * @brief Computes the activations of a normalization layer. + * @ingroup layers_norm + * @param layer the normalization (norm) layer + */ +AI_INTERNAL_API +void forward_norm(ai_layer* layer); + +/*! + * @brief Batch Normalization with 16-bit input, 16-bit threshold and binary output. + * It is implemented using a threshold, and this is possible because the output is binary. + * @param layer the batch normalization layer + */ +AI_INTERNAL_API +void forward_bn_is16os1ws16(ai_layer *pLayer); + +AI_API_DECLARE_END + +#endif /*LAYERS_NORM_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_pad_dqnn.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_pad_dqnn.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_pad_dqnn.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_pad_dqnn.h index 04392479..29354d23 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_pad_dqnn.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_pad_dqnn.h @@ -1,49 +1,49 @@ -/** - ****************************************************************************** - * @file layers_pad_dqnn.h - * @author AIS - * @brief header file of AI platform DQNN padding datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LAYERS_PADDING_DQNN_H -#define LAYERS_PADDING_DQNN_H - -#include "layers_common.h" -#include "layers_generic.h" - -/*! - * @defgroup layers_generic_dqnn Layers Definitions - * @brief definition - * - */ - -AI_API_DECLARE_BEGIN - - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - - -/*! - * @brief Handles padding with binary input and binary output - * @ingroup layers_generic_dqnn - * @param layer pad layer - */ -AI_INTERNAL_API -void forward_pad_is1os1(ai_layer *pLayer); - - -AI_API_DECLARE_END - -#endif /*LAYERS_PADDING_DQNN_H*/ +/** + ****************************************************************************** + * @file layers_pad_dqnn.h + * @author AIS + * @brief header file of AI platform DQNN padding datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_PADDING_DQNN_H +#define LAYERS_PADDING_DQNN_H + +#include "layers_common.h" +#include "layers_generic.h" + +/*! + * @defgroup layers_generic_dqnn Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + + +/*! + * @brief Handles padding with binary input and binary output + * @ingroup layers_generic_dqnn + * @param layer pad layer + */ +AI_INTERNAL_API +void forward_pad_is1os1(ai_layer *pLayer); + + +AI_API_DECLARE_END + +#endif /*LAYERS_PADDING_DQNN_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_pad_generic.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_pad_generic.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_pad_generic.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_pad_generic.h index 32a9f4d5..6eeff1d6 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_pad_generic.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_pad_generic.h @@ -1,71 +1,71 @@ -/** - ****************************************************************************** - * @file layers_pad_generic.h - * @author AIS - * @brief header file of AI platform padding generic datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LAYERS_PADDING_DQNN_H -#define LAYERS_PADDING_DQNN_H - -#include "layers_generic.h" - -/*! - * @defgroup layers_pad_generic Layers Definitions - * @brief definition - * - */ -AI_API_DECLARE_BEGIN - - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Handles generic padding in constant mode - * @ingroup layers_generic_dqnn - * @param layer pad layer - */ -AI_INTERNAL_API -void forward_pad_constant(ai_layer *pLayer); - -/*! - * @brief Handles generic padding in edge mode - * @ingroup layers_generic_dqnn - * @param layer pad layer - */ -AI_INTERNAL_API -void forward_pad_edge(ai_layer *pLayer); - -/*! - * @brief Handles generic padding in reflect mode - * @ingroup layers_generic_dqnn - * @param layer pad layer - */ -AI_INTERNAL_API -void forward_pad_reflect(ai_layer *pLayer); - - -/*! - * @brief Handles generic padding in constant mode Channel 1st 8bit - * @ingroup layers_generic_dqnn - * @param layer pad layer - */ -AI_INTERNAL_API -void forward_pad_8bit_ch1st_3x3_constant(ai_layer* pLayer); - - -AI_API_DECLARE_END - -#endif /*LAYERS_PAD_GENERIC_H*/ +/** + ****************************************************************************** + * @file layers_pad_generic.h + * @author AIS + * @brief header file of AI platform padding generic datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_PADDING_DQNN_H +#define LAYERS_PADDING_DQNN_H + +#include "layers_generic.h" + +/*! + * @defgroup layers_pad_generic Layers Definitions + * @brief definition + * + */ +AI_API_DECLARE_BEGIN + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles generic padding in constant mode + * @ingroup layers_generic_dqnn + * @param layer pad layer + */ +AI_INTERNAL_API +void forward_pad_constant(ai_layer *pLayer); + +/*! + * @brief Handles generic padding in edge mode + * @ingroup layers_generic_dqnn + * @param layer pad layer + */ +AI_INTERNAL_API +void forward_pad_edge(ai_layer *pLayer); + +/*! + * @brief Handles generic padding in reflect mode + * @ingroup layers_generic_dqnn + * @param layer pad layer + */ +AI_INTERNAL_API +void forward_pad_reflect(ai_layer *pLayer); + + +/*! + * @brief Handles generic padding in constant mode Channel 1st 8bit + * @ingroup layers_generic_dqnn + * @param layer pad layer + */ +AI_INTERNAL_API +void forward_pad_8bit_ch1st_3x3_constant(ai_layer* pLayer); + + +AI_API_DECLARE_END + +#endif /*LAYERS_PAD_GENERIC_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_pool.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_pool.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_pool.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_pool.h index c03ed203..329fc081 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_pool.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_pool.h @@ -1,375 +1,375 @@ -/** - ****************************************************************************** - * @file layers_pool.h - * @author AST Embedded Analytics Research Platform - * @brief header file of AI platform pooling layers datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2018 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LAYERS_POOL_H -#define LAYERS_POOL_H - -#include "layers_common.h" -#include "lite_maxpool_dqnn.h" -#include "lite_pool_f32.h" - -/*! - * @defgroup layers_pool Pooling Layers Definitions - * @brief definition - * - */ - -AI_API_DECLARE_BEGIN - -/*! - * @struct ai_layer_pool - * @ingroup layers_pool - * @brief Pooling layer - * - * The type of pooling function is handled by the specific forward function - * @ref forward_pool - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_pool_ { - AI_LAYER_COMMON_FIELDS_DECLARE - ai_shape_2d pool_size; /*!< pooling size */ - ai_shape_2d pool_stride; /*!< pooling stride */ - ai_shape pool_pad; /*!< pooling pad, y,x border sizes */ - ai_u8 count_include_pad; /*!< include pad flag */ -} ai_layer_pool; - - - -/*! - * @brief Max Pooling on a 8/16 bits fixed point data array - * @ingroup layers_pool - * @param in opaque handler to input data to process - * @param dim_im_in_x input feature map width - * @param dim_im_in_y input feature map height - * @param ch_im_in number of input channels - * @param dim_kernel_x kernel width - * @param dim_kernel_y kernel height - * @param padding_x right padding value - * @param padding_y top padding value - * @param stride_x stride value on x dimension - * @param stride_y stride value on y dimension - * @param dim_im_out_x output feature map width - * @param dim_im_out_y output feature map height - * @param out opaque handler to output data - */ -AI_INTERNAL_API -void pool_func_mp_array_fixed(ai_handle in, - const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, - const ai_u16 padding_x, const ai_u16 padding_y, - const ai_u16 stride_x, const ai_u16 stride_y, - const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, - ai_handle out); - -/*! - * @brief Max Pooling on a 8-bits integer quantized data array - * @ingroup layers_pool - * @param in opaque handler to input data to process - * @param dim_im_in_x input feature map width - * @param dim_im_in_y input feature map height - * @param ch_im_in number of input channels - * @param dim_kernel_x kernel width - * @param dim_kernel_y kernel height - * @param padding_x right padding value - * @param padding_y top padding value - * @param stride_x stride value on x dimension - * @param stride_y stride value on y dimension - * @param dim_im_out_x output feature map width - * @param dim_im_out_y output feature map height - * @param out opaque handler to output data - */ -AI_INTERNAL_API -void pool_func_mp_array_integer(ai_handle in, - const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, - const ai_u16 padding_x, const ai_u16 padding_y, - const ai_u16 stride_x, const ai_u16 stride_y, - const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, - ai_handle out); - -/*! - * @brief Max Pooling on a signed 8-bits integer quantized data array - * @ingroup layers_pool - * @param in opaque handler to input data to process - * @param dim_im_in_x input feature map width - * @param dim_im_in_y input feature map height - * @param ch_im_in number of input channels - * @param dim_kernel_x kernel width - * @param dim_kernel_y kernel height - * @param padding_x right padding value - * @param padding_y top padding value - * @param stride_x stride value on x dimension - * @param stride_y stride value on y dimension - * @param dim_im_out_x output feature map width - * @param dim_im_out_y output feature map height - * @param out opaque handler to output data - */ -AI_INTERNAL_API -void pool_func_mp_array_integer_INT8(ai_handle in, - const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, - const ai_u16 padding_x, const ai_u16 padding_y, - const ai_u16 stride_x, const ai_u16 stride_y, - const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, - ai_handle out); - -/*! - * @brief Max Pooling on a unsigned 8-bits integer quantized data array - * @ingroup layers_pool - * @param in opaque handler to input data to process - * @param dim_im_in_x input feature map width - * @param dim_im_in_y input feature map height - * @param ch_im_in number of input channels - * @param dim_kernel_x kernel width - * @param dim_kernel_y kernel height - * @param padding_x right padding value - * @param padding_y top padding value - * @param stride_x stride value on x dimension - * @param stride_y stride value on y dimension - * @param dim_im_out_x output feature map width - * @param dim_im_out_y output feature map height - * @param out opaque handler to output data - */ -AI_INTERNAL_API -void pool_func_mp_array_integer_UINT8(ai_handle in, - const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, - const ai_u16 padding_x, const ai_u16 padding_y, - const ai_u16 stride_x, const ai_u16 stride_y, - const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, - ai_handle out); - -/*! - * @brief Average Pooling on a 8/16 bits fixed point data array - * @ingroup layers_pool - * @param in opaque handler to input data to process - * @param dim_im_in_x input feature map width - * @param dim_im_in_y input feature map height - * @param ch_im_in number of input channels - * @param dim_kernel_x kernel width - * @param dim_kernel_y kernel height - * @param padding_x right padding value - * @param padding_y top padding value - * @param stride_x stride value on x dimension - * @param stride_y stride value on y dimension - * @param dim_im_out_x output feature map width - * @param dim_im_out_y output feature map height - * @param out opaque handler to scratch memory - */ -AI_INTERNAL_API -void pool_func_ap_array_fixed(ai_handle in, - const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, - const ai_u16 padding_x, const ai_u16 padding_y, - const ai_u16 stride_x, const ai_u16 stride_y, - const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, - ai_handle out); - - /*! - * @brief Average Pooling on a 8-bits integer quantized data array - * @ingroup layers_pool - * @param in opaque handler to input data to process - * @param dim_im_in_x input feature map width - * @param dim_im_in_y input feature map height - * @param ch_im_in number of input channels - * @param dim_kernel_x kernel width - * @param dim_kernel_y kernel height - * @param padding_x right padding value - * @param padding_y top padding value - * @param stride_x stride value on x dimension - * @param stride_y stride value on y dimension - * @param dim_im_out_x output feature map width - * @param dim_im_out_y output feature map height - * @param out opaque handler to scratch memory - */ -AI_INTERNAL_API -void pool_func_ap_array_integer(ai_handle in, - const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, - const ai_u16 padding_x, const ai_u16 padding_y, - const ai_u16 stride_x, const ai_u16 stride_y, - const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, - ai_handle out); - - /*! - * @brief Average Pooling on a signed 8-bits integer quantized data array - * @ingroup layers_pool - * @param in opaque handler to input data to process - * @param dim_im_in_x input feature map width - * @param dim_im_in_y input feature map height - * @param ch_im_in number of input channels - * @param dim_kernel_x kernel width - * @param dim_kernel_y kernel height - * @param padding_x right padding value - * @param padding_y top padding value - * @param stride_x stride value on x dimension - * @param stride_y stride value on y dimension - * @param dim_im_out_x output feature map width - * @param dim_im_out_y output feature map height - * @param out opaque handler to scratch memory - */ -AI_INTERNAL_API -void pool_func_ap_array_integer_INT8(ai_handle in, - const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, - const ai_u16 padding_x, const ai_u16 padding_y, - const ai_u16 stride_x, const ai_u16 stride_y, - const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, - ai_handle out); - - /*! - * @brief Average Pooling on a unsigned 8-bits integer quantized data array - * @ingroup layers_pool - * @param in opaque handler to input data to process - * @param dim_im_in_x input feature map width - * @param dim_im_in_y input feature map height - * @param ch_im_in number of input channels - * @param dim_kernel_x kernel width - * @param dim_kernel_y kernel height - * @param padding_x right padding value - * @param padding_y top padding value - * @param stride_x stride value on x dimension - * @param stride_y stride value on y dimension - * @param dim_im_out_x output feature map width - * @param dim_im_out_y output feature map height - * @param out opaque handler to scratch memory - */ -AI_INTERNAL_API -void pool_func_ap_array_integer_UINT8(ai_handle in, - const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, - const ai_u16 padding_x, const ai_u16 padding_y, - const ai_u16 stride_x, const ai_u16 stride_y, - const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, - ai_handle out); - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Computes the activations of a max pooling layer. - * @ingroup layers_pool - * @param layer the pooling (pool) layer - */ -AI_INTERNAL_API -void forward_mp(ai_layer* layer); - -/*! - * @brief Computes the activations of a fixed point max pooling layer. - * @ingroup layers_pool - * @param layer the pooling (pool) layer - */ -AI_INTERNAL_API -void forward_mp_fixed(ai_layer *pLayer); - -/*! - * @brief Computes the activations of an integer-quantized max pooling layer. - * @ingroup layers_pool - * @param layer the pooling (pool) layer - */ -AI_INTERNAL_API -void forward_mp_integer(ai_layer *pLayer); - -/*! - * @brief Computes the activations of an integer-quantized max pooling layer - * with int8 I/O - * @ingroup layers_pool - * @param layer the pooling (pool) layer - */ -AI_INTERNAL_API -void forward_mp_integer_INT8(ai_layer *pLayer); - -/*! - * @brief Computes the activations of an integer-quantized max pooling layer - * with uint8 I/O - * @ingroup layers_pool - * @param layer the pooling (pool) layer - */ -AI_INTERNAL_API -void forward_mp_integer_UINT8(ai_layer *pLayer); - -/*! - * @brief Computes the activations of an integer-quantized max pooling layer - * with int16 I/O - * @ingroup layers_pool - * @param layer the pooling (pool) layer - */ -AI_INTERNAL_API -void forward_mp_integer_INT16(ai_layer *pLayer); - -/*! - * @brief Computes the activations of an integer-quantized max pooling layer - * with uint16 I/O - * @ingroup layers_pool - * @param layer the pooling (pool) layer - */ -AI_INTERNAL_API -void forward_mp_integer_UINT16(ai_layer *pLayer); - -/*! - * @brief Computes the activations of an average pooling layer. - * @ingroup layers_pool - * @param layer the pooling (pool) layer - */ -AI_INTERNAL_API -void forward_ap(ai_layer* layer); - -/*! - * @brief Computes the activations of a fixed point average pooling layer. - * @ingroup layers_pool - * @param layer the pooling (pool) layer - */ -AI_INTERNAL_API -void forward_ap_fixed(ai_layer *pLayer); - -/*! - * @brief Computes the activations of an integer-quantized average pooling layer. - * @ingroup layers_pool - * @param layer the pooling (pool) layer - */ -AI_INTERNAL_API -void forward_ap_integer(ai_layer *pLayer); - -/*! - * @brief Computes the activations of an integer-quantized average pooling layer - * with int8 I/O - * @ingroup layers_pool - * @param layer the pooling (pool) layer - */ -AI_INTERNAL_API -void forward_ap_integer_INT8(ai_layer *pLayer); - -/*! - * @brief Computes the activations of an integer-quantized average pooling layer - * with uint8 I/O - * @ingroup layers_pool - * @param layer the pooling (pool) layer - */ -AI_INTERNAL_API -void forward_ap_integer_UINT8(ai_layer *pLayer); - -AI_API_DECLARE_END - -#endif /*LAYERS_POOL_H*/ +/** + ****************************************************************************** + * @file layers_pool.h + * @author AST Embedded Analytics Research Platform + * @brief header file of AI platform pooling layers datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_POOL_H +#define LAYERS_POOL_H + +#include "layers_common.h" +#include "lite_maxpool_dqnn.h" +#include "lite_pool_f32.h" + +/*! + * @defgroup layers_pool Pooling Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_pool + * @ingroup layers_pool + * @brief Pooling layer + * + * The type of pooling function is handled by the specific forward function + * @ref forward_pool + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_pool_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_shape_2d pool_size; /*!< pooling size */ + ai_shape_2d pool_stride; /*!< pooling stride */ + ai_shape pool_pad; /*!< pooling pad, y,x border sizes */ + ai_u8 count_include_pad; /*!< include pad flag */ +} ai_layer_pool; + + + +/*! + * @brief Max Pooling on a 8/16 bits fixed point data array + * @ingroup layers_pool + * @param in opaque handler to input data to process + * @param dim_im_in_x input feature map width + * @param dim_im_in_y input feature map height + * @param ch_im_in number of input channels + * @param dim_kernel_x kernel width + * @param dim_kernel_y kernel height + * @param padding_x right padding value + * @param padding_y top padding value + * @param stride_x stride value on x dimension + * @param stride_y stride value on y dimension + * @param dim_im_out_x output feature map width + * @param dim_im_out_y output feature map height + * @param out opaque handler to output data + */ +AI_INTERNAL_API +void pool_func_mp_array_fixed(ai_handle in, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + ai_handle out); + +/*! + * @brief Max Pooling on a 8-bits integer quantized data array + * @ingroup layers_pool + * @param in opaque handler to input data to process + * @param dim_im_in_x input feature map width + * @param dim_im_in_y input feature map height + * @param ch_im_in number of input channels + * @param dim_kernel_x kernel width + * @param dim_kernel_y kernel height + * @param padding_x right padding value + * @param padding_y top padding value + * @param stride_x stride value on x dimension + * @param stride_y stride value on y dimension + * @param dim_im_out_x output feature map width + * @param dim_im_out_y output feature map height + * @param out opaque handler to output data + */ +AI_INTERNAL_API +void pool_func_mp_array_integer(ai_handle in, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + ai_handle out); + +/*! + * @brief Max Pooling on a signed 8-bits integer quantized data array + * @ingroup layers_pool + * @param in opaque handler to input data to process + * @param dim_im_in_x input feature map width + * @param dim_im_in_y input feature map height + * @param ch_im_in number of input channels + * @param dim_kernel_x kernel width + * @param dim_kernel_y kernel height + * @param padding_x right padding value + * @param padding_y top padding value + * @param stride_x stride value on x dimension + * @param stride_y stride value on y dimension + * @param dim_im_out_x output feature map width + * @param dim_im_out_y output feature map height + * @param out opaque handler to output data + */ +AI_INTERNAL_API +void pool_func_mp_array_integer_INT8(ai_handle in, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + ai_handle out); + +/*! + * @brief Max Pooling on a unsigned 8-bits integer quantized data array + * @ingroup layers_pool + * @param in opaque handler to input data to process + * @param dim_im_in_x input feature map width + * @param dim_im_in_y input feature map height + * @param ch_im_in number of input channels + * @param dim_kernel_x kernel width + * @param dim_kernel_y kernel height + * @param padding_x right padding value + * @param padding_y top padding value + * @param stride_x stride value on x dimension + * @param stride_y stride value on y dimension + * @param dim_im_out_x output feature map width + * @param dim_im_out_y output feature map height + * @param out opaque handler to output data + */ +AI_INTERNAL_API +void pool_func_mp_array_integer_UINT8(ai_handle in, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + ai_handle out); + +/*! + * @brief Average Pooling on a 8/16 bits fixed point data array + * @ingroup layers_pool + * @param in opaque handler to input data to process + * @param dim_im_in_x input feature map width + * @param dim_im_in_y input feature map height + * @param ch_im_in number of input channels + * @param dim_kernel_x kernel width + * @param dim_kernel_y kernel height + * @param padding_x right padding value + * @param padding_y top padding value + * @param stride_x stride value on x dimension + * @param stride_y stride value on y dimension + * @param dim_im_out_x output feature map width + * @param dim_im_out_y output feature map height + * @param out opaque handler to scratch memory + */ +AI_INTERNAL_API +void pool_func_ap_array_fixed(ai_handle in, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + ai_handle out); + + /*! + * @brief Average Pooling on a 8-bits integer quantized data array + * @ingroup layers_pool + * @param in opaque handler to input data to process + * @param dim_im_in_x input feature map width + * @param dim_im_in_y input feature map height + * @param ch_im_in number of input channels + * @param dim_kernel_x kernel width + * @param dim_kernel_y kernel height + * @param padding_x right padding value + * @param padding_y top padding value + * @param stride_x stride value on x dimension + * @param stride_y stride value on y dimension + * @param dim_im_out_x output feature map width + * @param dim_im_out_y output feature map height + * @param out opaque handler to scratch memory + */ +AI_INTERNAL_API +void pool_func_ap_array_integer(ai_handle in, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + ai_handle out); + + /*! + * @brief Average Pooling on a signed 8-bits integer quantized data array + * @ingroup layers_pool + * @param in opaque handler to input data to process + * @param dim_im_in_x input feature map width + * @param dim_im_in_y input feature map height + * @param ch_im_in number of input channels + * @param dim_kernel_x kernel width + * @param dim_kernel_y kernel height + * @param padding_x right padding value + * @param padding_y top padding value + * @param stride_x stride value on x dimension + * @param stride_y stride value on y dimension + * @param dim_im_out_x output feature map width + * @param dim_im_out_y output feature map height + * @param out opaque handler to scratch memory + */ +AI_INTERNAL_API +void pool_func_ap_array_integer_INT8(ai_handle in, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + ai_handle out); + + /*! + * @brief Average Pooling on a unsigned 8-bits integer quantized data array + * @ingroup layers_pool + * @param in opaque handler to input data to process + * @param dim_im_in_x input feature map width + * @param dim_im_in_y input feature map height + * @param ch_im_in number of input channels + * @param dim_kernel_x kernel width + * @param dim_kernel_y kernel height + * @param padding_x right padding value + * @param padding_y top padding value + * @param stride_x stride value on x dimension + * @param stride_y stride value on y dimension + * @param dim_im_out_x output feature map width + * @param dim_im_out_y output feature map height + * @param out opaque handler to scratch memory + */ +AI_INTERNAL_API +void pool_func_ap_array_integer_UINT8(ai_handle in, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + ai_handle out); + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Computes the activations of a max pooling layer. + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_mp(ai_layer* layer); + +/*! + * @brief Computes the activations of a fixed point max pooling layer. + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_mp_fixed(ai_layer *pLayer); + +/*! + * @brief Computes the activations of an integer-quantized max pooling layer. + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_mp_integer(ai_layer *pLayer); + +/*! + * @brief Computes the activations of an integer-quantized max pooling layer + * with int8 I/O + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_mp_integer_INT8(ai_layer *pLayer); + +/*! + * @brief Computes the activations of an integer-quantized max pooling layer + * with uint8 I/O + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_mp_integer_UINT8(ai_layer *pLayer); + +/*! + * @brief Computes the activations of an integer-quantized max pooling layer + * with int16 I/O + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_mp_integer_INT16(ai_layer *pLayer); + +/*! + * @brief Computes the activations of an integer-quantized max pooling layer + * with uint16 I/O + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_mp_integer_UINT16(ai_layer *pLayer); + +/*! + * @brief Computes the activations of an average pooling layer. + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_ap(ai_layer* layer); + +/*! + * @brief Computes the activations of a fixed point average pooling layer. + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_ap_fixed(ai_layer *pLayer); + +/*! + * @brief Computes the activations of an integer-quantized average pooling layer. + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_ap_integer(ai_layer *pLayer); + +/*! + * @brief Computes the activations of an integer-quantized average pooling layer + * with int8 I/O + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_ap_integer_INT8(ai_layer *pLayer); + +/*! + * @brief Computes the activations of an integer-quantized average pooling layer + * with uint8 I/O + * @ingroup layers_pool + * @param layer the pooling (pool) layer + */ +AI_INTERNAL_API +void forward_ap_integer_UINT8(ai_layer *pLayer); + +AI_API_DECLARE_END + +#endif /*LAYERS_POOL_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_pool_dqnn.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_pool_dqnn.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_pool_dqnn.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_pool_dqnn.h index 7936abe5..9a59d43d 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_pool_dqnn.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_pool_dqnn.h @@ -1,68 +1,68 @@ -/** - ****************************************************************************** - * @file layers_conv2d_dqnn.h - * @author AIS - * @brief header file of AI platform DQNN pool datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -#ifndef LAYERS_POOL_DQNN_H -#define LAYERS_POOL_DQNN_H - -#include "layers_common.h" -#include "layers_pool.h" - -/*! - * @defgroup layers_pool_dqnn Layers Definitions - * @brief definition - * - */ - -AI_API_DECLARE_BEGIN - - - -/*! - * @struct ai_layer_pool_dqnn - * @ingroup layers_pool_dqnn - * @brief pool_dqnn layer - * - * @ref forward_maxpool_is1os1 - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_pool_dqnn_ { - AI_LAYER_COMMON_FIELDS_DECLARE - ai_shape_2d pool_size; /*!< pooling size */ - ai_shape_2d pool_stride; /*!< pooling stride */ - ai_shape pool_pad; /*!< pooling pad, y,x border sizes */ -// ai_u32 pad_value; /*!< pooling pad value */ -} ai_layer_pool_dqnn; - - - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Handles max pooling with binary input and binary output - * @ingroup layers_pool_dqnn - * @param layer conv2d_pool layer - */ -AI_INTERNAL_API -void forward_maxpool_is1os1(ai_layer *pLayer); - - - -AI_API_DECLARE_END - -#endif /*LAYERS_POOL_DQNN_H*/ +/** + ****************************************************************************** + * @file layers_conv2d_dqnn.h + * @author AIS + * @brief header file of AI platform DQNN pool datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef LAYERS_POOL_DQNN_H +#define LAYERS_POOL_DQNN_H + +#include "layers_common.h" +#include "layers_pool.h" + +/*! + * @defgroup layers_pool_dqnn Layers Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + + + +/*! + * @struct ai_layer_pool_dqnn + * @ingroup layers_pool_dqnn + * @brief pool_dqnn layer + * + * @ref forward_maxpool_is1os1 + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_pool_dqnn_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_shape_2d pool_size; /*!< pooling size */ + ai_shape_2d pool_stride; /*!< pooling stride */ + ai_shape pool_pad; /*!< pooling pad, y,x border sizes */ +// ai_u32 pad_value; /*!< pooling pad value */ +} ai_layer_pool_dqnn; + + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles max pooling with binary input and binary output + * @ingroup layers_pool_dqnn + * @param layer conv2d_pool layer + */ +AI_INTERNAL_API +void forward_maxpool_is1os1(ai_layer *pLayer); + + + +AI_API_DECLARE_END + +#endif /*LAYERS_POOL_DQNN_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_resize.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_resize.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_resize.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_resize.h index cc8fb0d6..820158d4 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_resize.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_resize.h @@ -1,94 +1,94 @@ -/** - ****************************************************************************** - * @file layers_resize.h - * @author STMicroelectronics - * @brief header file of AI platform padding generic datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LAYERS_RESIZE_H -#define LAYERS_RESIZE_H - -#include "layers_generic.h" - -/*! - * @defgroup layers_pad_generic Layers Definitions - * @brief definition - * - */ -AI_API_DECLARE_BEGIN - - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Handles generic resizing in nearest mode - * @ingroup layers_generic - * @param layer resize layer - */ -AI_INTERNAL_API -void forward_resize_if32of32(ai_layer* layer); - -/*! - * @brief Handles generic resizing in bilinear mode - * @ingroup layers_generic - * @param layer resize layer - */ -AI_INTERNAL_API -void forward_resize_bilinear_if32of32(ai_layer *pLayer); - -/*! - * @brief Handles generic resizing in bilinear mode - * @ingroup layers_generic - * @param layer resize layer - */ -AI_INTERNAL_API -void forward_resize_nearest_if32of32(ai_layer *pLayer); - -/*! - * @brief Handles generic resizing in bilinear mode - * @ingroup layers_generic - * @param layer resize layer - */ -AI_INTERNAL_API -void forward_resize_bilinear_is16os16(ai_layer *pLayer); - -/*! - * @brief Handles generic resizing in bilinear mode - * @ingroup layers_generic - * @param layer resize layer - */ -AI_INTERNAL_API -void forward_resize_nearest_is16os16(ai_layer *pLayer); - -/*! - * @brief Handles generic resizing in bilinear mode - * @ingroup layers_generic - * @param layer resize layer - */ -AI_INTERNAL_API -void forward_resize_bilinear_is8os8(ai_layer *pLayer); - -/*! - * @brief Handles generic resizing in bilinear mode - * @ingroup layers_generic - * @param layer resize layer - */ -AI_INTERNAL_API -void forward_resize_nearest_is8os8(ai_layer *pLayer); - - -AI_API_DECLARE_END - -#endif /*LAYERS_PAD_GENERIC_H*/ +/** + ****************************************************************************** + * @file layers_resize.h + * @author STMicroelectronics + * @brief header file of AI platform padding generic datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_RESIZE_H +#define LAYERS_RESIZE_H + +#include "layers_generic.h" + +/*! + * @defgroup layers_pad_generic Layers Definitions + * @brief definition + * + */ +AI_API_DECLARE_BEGIN + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles generic resizing in nearest mode + * @ingroup layers_generic + * @param layer resize layer + */ +AI_INTERNAL_API +void forward_resize_if32of32(ai_layer* layer); + +/*! + * @brief Handles generic resizing in bilinear mode + * @ingroup layers_generic + * @param layer resize layer + */ +AI_INTERNAL_API +void forward_resize_bilinear_if32of32(ai_layer *pLayer); + +/*! + * @brief Handles generic resizing in bilinear mode + * @ingroup layers_generic + * @param layer resize layer + */ +AI_INTERNAL_API +void forward_resize_nearest_if32of32(ai_layer *pLayer); + +/*! + * @brief Handles generic resizing in bilinear mode + * @ingroup layers_generic + * @param layer resize layer + */ +AI_INTERNAL_API +void forward_resize_bilinear_is16os16(ai_layer *pLayer); + +/*! + * @brief Handles generic resizing in bilinear mode + * @ingroup layers_generic + * @param layer resize layer + */ +AI_INTERNAL_API +void forward_resize_nearest_is16os16(ai_layer *pLayer); + +/*! + * @brief Handles generic resizing in bilinear mode + * @ingroup layers_generic + * @param layer resize layer + */ +AI_INTERNAL_API +void forward_resize_bilinear_is8os8(ai_layer *pLayer); + +/*! + * @brief Handles generic resizing in bilinear mode + * @ingroup layers_generic + * @param layer resize layer + */ +AI_INTERNAL_API +void forward_resize_nearest_is8os8(ai_layer *pLayer); + + +AI_API_DECLARE_END + +#endif /*LAYERS_PAD_GENERIC_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_rnn.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_rnn.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_rnn.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_rnn.h index 2325a8e9..c3e67974 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_rnn.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_rnn.h @@ -1,201 +1,201 @@ -/** - ****************************************************************************** - * @file layers_rnn.h - * @author AST Embedded Analytics Research Platform - * @brief header file of RNN layers - ****************************************************************************** - * @attention - * - * Copyright (c) 2018 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LAYERS_RNN_H -#define LAYERS_RNN_H - -#include "layers_common.h" -#include "layers_nl.h" - -AI_API_DECLARE_BEGIN - -/*! - * @struct ai_layer_lstm - * @ingroup layers - * @brief LSTM layer with generic nonlinearities and peephole connections - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_lstm_ { - AI_LAYER_STATEFUL_FIELDS_DECLARE - ai_size n_units; /**< size of the hidden RNN state */ - func_nl activation_nl; /**< activation nonlinearity (input to cell) */ - func_nl recurrent_nl; /**< recurrent nonlinearity (hidden to cell) */ - func_nl out_nl; /**< output nonlinearity (cell to hidden) */ - ai_bool go_backwards; /**< process reversed input */ - ai_bool return_state; /**< return state */ - ai_bool reverse_seq; /**< reverse output sequence */ - ai_float cell_clip; /**< cell clip value */ -} ai_layer_lstm; - -/*! - * @struct ai_layer_gru - * @ingroup layers - * @brief Gated Recurrent Unit (GRU) layer with generic nonlinearities - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_gru_ { - AI_LAYER_STATEFUL_FIELDS_DECLARE - ai_size n_units; /**< size of the hidden RNN state */ - func_nl activation_nl; /**< activation nonlinearity (input to cell) */ - func_nl recurrent_nl; /**< recurrent nonlinearity (hidden to cell) */ - ai_bool reset_after; - ai_bool return_state; - ai_bool go_backwards; /**< process reversed input */ - ai_bool reverse_seq; /**< reverse output sequence */ -} ai_layer_gru; - -/*! - * @struct ai_layer_rnn - * @ingroup layers - * @brief Simple Recurrent Neural Network (RNN) layer - */ -typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_rnn_ { - AI_LAYER_COMMON_FIELDS_DECLARE - ai_size n_units; /**< size of the hidden RNN state */ - func_nl activation_nl; /**< activation nonlinearity (input to hidden) */ - ai_bool go_backwards; /**< process reversed input */ - ai_bool reverse_seq; /**< reverse output sequence */ - ai_bool return_state; -} ai_layer_rnn; - - -/*! - * @brief Allocate states for a stateful network. - * @ingroup layers - * - * Function used to allocate states of a stateful network. - */ -void _allocate_states(ai_float **states, ai_u32 size_in_bytes); - - -/*! - * @brief Deallocate states for a stateful network. - * @ingroup layers - * - * Function used to deallocate states of a stateful network. - */ -void _deallocate_states(ai_float **states); - - -/*! - * @brief Initialize a Long-Short Term Memory (LSTM) layer. - * @ingroup layers - * - * Function used to initialize lstm internal state - */ -AI_INTERNAL_API -void init_lstm(ai_layer * layer); - - -/*! - * @brief Destroy a Long-Short Term Memory (LSTM) layer state. - * @ingroup layers - * - * Function used to destroy lstm internal state - */ -AI_INTERNAL_API -void destroy_lstm(ai_layer * layer); - - -/*! - * @brief Computes the activations of a Long-Short Term Memory (LSTM) layer. - * @ingroup layers - * - * Implements a Long-Short Term Layer with peephole connections: - * \f{eqnarray*}{ - * i_t &=& \sigma_a(x_t W_{xi} + h_{t-1} W_{hi} - * + w_{ci} \odot c_{t-1} + b_i)\\ - * f_t &=& \sigma_a(x_t W_{xf} + h_{t-1} W_{hf} - * + w_{cf} \odot c_{t-1} + b_f)\\ - * c_t &=& f_t \odot c_{t - 1} - * + i_t \odot \sigma_r(x_t W_{xc} + h_{t-1} W_{hc} + b_c)\\ - * o_t &=& \sigma_a(x_t W_{xo} + h_{t-1} W_{ho} + w_{co} \odot c_t + b_o)\\ - * h_t &=& o_t \odot \sigma_o(c_t) - * \f} - * where \f$\sigma_a\f$ is the activation nonlinearity, \f$\sigma_r\f$ is the - * recurrent nonlinearity and \f$\sigma_o\f$ is the out nonlinearity. The - * \f$W_x\f$, \f$W_h\f$ and \f$W_c\f$ weights are sliced from the kernel, - * recurrent and peephole weights. - * - * @param layer the LSTM layer - */ -AI_INTERNAL_API -void forward_lstm(ai_layer * layer); - -AI_INTERNAL_API -void forward_lstm_is8os8ws8(ai_layer * layer); - - -/*! - * @brief Initialize a Gated Recurrent Unit (GRU) layer. - * @ingroup layers - * - * Function used to initialize gru internal state - */ -AI_INTERNAL_API -void init_gru(ai_layer * layer); - - -/*! - * @brief Destroy a Gated Recurrent Unit (GRU) layer state. - * @ingroup layers - * - * Function used to destroy gru internal state - */ -AI_INTERNAL_API -void destroy_gru(ai_layer * layer); - -/*! - * @brief Computes the activations of a Gated Recurrent Unit (GRU) layer. - * @ingroup layers - * - * Implements a Gated Recurrent Unit with the formula: - * \f{eqnarray*}{ - * r_t &=& \sigma_a(x_t W_{xr} + h_{t - 1} W_{hr} + b_r) \\ - * z_t &=& \sigma_a(x_t W_{xz} + h_{t - 1} W_{hz} + b_z) \\ - * c_t &=& \sigma_r(x_t W_{xc} + r_t \odot (h_{t - 1} W_{hc} + b_{hc}) + b_c) - * \qquad \textnormal{when reset after is true} \\ - * c_t &=& \sigma_r(x_t W_{xc} + (r_t \odot h_{t - 1}) W_{hc} + b_{hc} + b_c) - * \qquad \textnormal{when reset after is false (default)} \\ - * h_t &=& (1 - z_t) \odot h_{t - 1} + z_t \odot c_t - * \f} - * where \f$\sigma_a\f$ is the activation nonlinearity and \f$\sigma_r\f$ is - * the recurrent nonlinearity. The weights are sliced from the kernel and - * recurrent weights. - * - * @param layer the GRU layer - */ -AI_INTERNAL_API -void forward_gru(ai_layer * layer); - -/*! - * @brief Computes the activations of a Recurrent Neural Network (RNN) layer. - * @ingroup layers - * - * Implements a recurrent layer with the formula: - * \f{eqnarray*}{ - * h_t &=& \sigma_a(x_t W_{xr} + h_{t - 1} W_{hr} + b_r) - * \f} - * where \f$\sigma_a\f$ is the activation nonlinearity. The weights are sliced - * from the kernel and recurrent weights. - * - * @param layer the RNN layer - */ -AI_INTERNAL_API -void forward_rnn(ai_layer * layer); - -AI_API_DECLARE_END - -#endif /* LAYERS_RNN_H */ +/** + ****************************************************************************** + * @file layers_rnn.h + * @author AST Embedded Analytics Research Platform + * @brief header file of RNN layers + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_RNN_H +#define LAYERS_RNN_H + +#include "layers_common.h" +#include "layers_nl.h" + +AI_API_DECLARE_BEGIN + +/*! + * @struct ai_layer_lstm + * @ingroup layers + * @brief LSTM layer with generic nonlinearities and peephole connections + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_lstm_ { + AI_LAYER_STATEFUL_FIELDS_DECLARE + ai_size n_units; /**< size of the hidden RNN state */ + func_nl activation_nl; /**< activation nonlinearity (input to cell) */ + func_nl recurrent_nl; /**< recurrent nonlinearity (hidden to cell) */ + func_nl out_nl; /**< output nonlinearity (cell to hidden) */ + ai_bool go_backwards; /**< process reversed input */ + ai_bool return_state; /**< return state */ + ai_bool reverse_seq; /**< reverse output sequence */ + ai_float cell_clip; /**< cell clip value */ +} ai_layer_lstm; + +/*! + * @struct ai_layer_gru + * @ingroup layers + * @brief Gated Recurrent Unit (GRU) layer with generic nonlinearities + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_gru_ { + AI_LAYER_STATEFUL_FIELDS_DECLARE + ai_size n_units; /**< size of the hidden RNN state */ + func_nl activation_nl; /**< activation nonlinearity (input to cell) */ + func_nl recurrent_nl; /**< recurrent nonlinearity (hidden to cell) */ + ai_bool reset_after; + ai_bool return_state; + ai_bool go_backwards; /**< process reversed input */ + ai_bool reverse_seq; /**< reverse output sequence */ +} ai_layer_gru; + +/*! + * @struct ai_layer_rnn + * @ingroup layers + * @brief Simple Recurrent Neural Network (RNN) layer + */ +typedef AI_ALIGNED_TYPE(struct, 4) ai_layer_rnn_ { + AI_LAYER_COMMON_FIELDS_DECLARE + ai_size n_units; /**< size of the hidden RNN state */ + func_nl activation_nl; /**< activation nonlinearity (input to hidden) */ + ai_bool go_backwards; /**< process reversed input */ + ai_bool reverse_seq; /**< reverse output sequence */ + ai_bool return_state; +} ai_layer_rnn; + + +/*! + * @brief Allocate states for a stateful network. + * @ingroup layers + * + * Function used to allocate states of a stateful network. + */ +void _allocate_states(ai_float **states, ai_u32 size_in_bytes); + + +/*! + * @brief Deallocate states for a stateful network. + * @ingroup layers + * + * Function used to deallocate states of a stateful network. + */ +void _deallocate_states(ai_float **states); + + +/*! + * @brief Initialize a Long-Short Term Memory (LSTM) layer. + * @ingroup layers + * + * Function used to initialize lstm internal state + */ +AI_INTERNAL_API +void init_lstm(ai_layer * layer); + + +/*! + * @brief Destroy a Long-Short Term Memory (LSTM) layer state. + * @ingroup layers + * + * Function used to destroy lstm internal state + */ +AI_INTERNAL_API +void destroy_lstm(ai_layer * layer); + + +/*! + * @brief Computes the activations of a Long-Short Term Memory (LSTM) layer. + * @ingroup layers + * + * Implements a Long-Short Term Layer with peephole connections: + * \f{eqnarray*}{ + * i_t &=& \sigma_a(x_t W_{xi} + h_{t-1} W_{hi} + * + w_{ci} \odot c_{t-1} + b_i)\\ + * f_t &=& \sigma_a(x_t W_{xf} + h_{t-1} W_{hf} + * + w_{cf} \odot c_{t-1} + b_f)\\ + * c_t &=& f_t \odot c_{t - 1} + * + i_t \odot \sigma_r(x_t W_{xc} + h_{t-1} W_{hc} + b_c)\\ + * o_t &=& \sigma_a(x_t W_{xo} + h_{t-1} W_{ho} + w_{co} \odot c_t + b_o)\\ + * h_t &=& o_t \odot \sigma_o(c_t) + * \f} + * where \f$\sigma_a\f$ is the activation nonlinearity, \f$\sigma_r\f$ is the + * recurrent nonlinearity and \f$\sigma_o\f$ is the out nonlinearity. The + * \f$W_x\f$, \f$W_h\f$ and \f$W_c\f$ weights are sliced from the kernel, + * recurrent and peephole weights. + * + * @param layer the LSTM layer + */ +AI_INTERNAL_API +void forward_lstm(ai_layer * layer); + +AI_INTERNAL_API +void forward_lstm_is8os8ws8(ai_layer * layer); + + +/*! + * @brief Initialize a Gated Recurrent Unit (GRU) layer. + * @ingroup layers + * + * Function used to initialize gru internal state + */ +AI_INTERNAL_API +void init_gru(ai_layer * layer); + + +/*! + * @brief Destroy a Gated Recurrent Unit (GRU) layer state. + * @ingroup layers + * + * Function used to destroy gru internal state + */ +AI_INTERNAL_API +void destroy_gru(ai_layer * layer); + +/*! + * @brief Computes the activations of a Gated Recurrent Unit (GRU) layer. + * @ingroup layers + * + * Implements a Gated Recurrent Unit with the formula: + * \f{eqnarray*}{ + * r_t &=& \sigma_a(x_t W_{xr} + h_{t - 1} W_{hr} + b_r) \\ + * z_t &=& \sigma_a(x_t W_{xz} + h_{t - 1} W_{hz} + b_z) \\ + * c_t &=& \sigma_r(x_t W_{xc} + r_t \odot (h_{t - 1} W_{hc} + b_{hc}) + b_c) + * \qquad \textnormal{when reset after is true} \\ + * c_t &=& \sigma_r(x_t W_{xc} + (r_t \odot h_{t - 1}) W_{hc} + b_{hc} + b_c) + * \qquad \textnormal{when reset after is false (default)} \\ + * h_t &=& (1 - z_t) \odot h_{t - 1} + z_t \odot c_t + * \f} + * where \f$\sigma_a\f$ is the activation nonlinearity and \f$\sigma_r\f$ is + * the recurrent nonlinearity. The weights are sliced from the kernel and + * recurrent weights. + * + * @param layer the GRU layer + */ +AI_INTERNAL_API +void forward_gru(ai_layer * layer); + +/*! + * @brief Computes the activations of a Recurrent Neural Network (RNN) layer. + * @ingroup layers + * + * Implements a recurrent layer with the formula: + * \f{eqnarray*}{ + * h_t &=& \sigma_a(x_t W_{xr} + h_{t - 1} W_{hr} + b_r) + * \f} + * where \f$\sigma_a\f$ is the activation nonlinearity. The weights are sliced + * from the kernel and recurrent weights. + * + * @param layer the RNN layer + */ +AI_INTERNAL_API +void forward_rnn(ai_layer * layer); + +AI_API_DECLARE_END + +#endif /* LAYERS_RNN_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_sm.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_sm.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_sm.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_sm.h index 719dde40..3255b6d5 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_sm.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_sm.h @@ -1,60 +1,60 @@ -/** - ****************************************************************************** - * @file layers_sm.h - * @author STMicroelectronics - * @brief header file of AI platform non softmax layer datatype - ****************************************************************************** - * @attention - * - * Copyright (c) 2018 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -#ifndef LAYERS_SM_H -#define LAYERS_SM_H - -#include "layers_common.h" - -/*! - * @defgroup layers SoftMax Layer Definitions - * @brief definition - * - */ - -AI_API_DECLARE_BEGIN - -/*! - * @brief Softmax normalization computed on an array of fixed point channels - * @ingroup layers_sm - * @param out opaque handler to output channel array - * @param in opaque handler to input channel array - * @param in_size total size (number of elements) to process on the input - * @param channel_size number of elements of the input channel - * @param in_channel_step number of elements to move to next input element - * @param out_channel_step number of elements to move to next output element - */ -AI_INTERNAL_API -void sm_func_sm_array_fixed(ai_handle out, const ai_handle in, - const ai_size in_size, - const ai_size channel_size, - const ai_size in_channel_step, - const ai_size out_channel_step); - -/*! - * @brief Computes the activations of a fixed point softmax nonlinear layer. - * @ingroup layers_sm - * @param layer the softmax (sm) layer - */ -AI_INTERNAL_API -void forward_sm_fixed(ai_layer *pLayer); - -AI_API_DECLARE_END - -#endif /*LAYERS_SM_H*/ - +/** + ****************************************************************************** + * @file layers_sm.h + * @author STMicroelectronics + * @brief header file of AI platform non softmax layer datatype + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef LAYERS_SM_H +#define LAYERS_SM_H + +#include "layers_common.h" + +/*! + * @defgroup layers SoftMax Layer Definitions + * @brief definition + * + */ + +AI_API_DECLARE_BEGIN + +/*! + * @brief Softmax normalization computed on an array of fixed point channels + * @ingroup layers_sm + * @param out opaque handler to output channel array + * @param in opaque handler to input channel array + * @param in_size total size (number of elements) to process on the input + * @param channel_size number of elements of the input channel + * @param in_channel_step number of elements to move to next input element + * @param out_channel_step number of elements to move to next output element + */ +AI_INTERNAL_API +void sm_func_sm_array_fixed(ai_handle out, const ai_handle in, + const ai_size in_size, + const ai_size channel_size, + const ai_size in_channel_step, + const ai_size out_channel_step); + +/*! + * @brief Computes the activations of a fixed point softmax nonlinear layer. + * @ingroup layers_sm + * @param layer the softmax (sm) layer + */ +AI_INTERNAL_API +void forward_sm_fixed(ai_layer *pLayer); + +AI_API_DECLARE_END + +#endif /*LAYERS_SM_H*/ + diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_upsample.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_upsample.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_upsample.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_upsample.h index 40be2405..ff906a18 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_upsample.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_upsample.h @@ -1,69 +1,69 @@ -/** - ****************************************************************************** - * @file layers_upsample_generic.h - * @author STMicroelectronics - * @brief header file of AI platform padding generic datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LAYERS_UPSAMPLE_H -#define LAYERS_UPSAMPLE_H - -#include "layers_generic.h" - -/*! - * @defgroup layers_pad_generic Layers Definitions - * @brief definition - * - */ -AI_API_DECLARE_BEGIN - - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - - -/*! - * @brief Handles upsampling in zeros mode - * @ingroup layers_upsample - * @param layer upsample layer - */ -AI_INTERNAL_API -void forward_upsample_zeros_is8os8(ai_layer* layer); - -/*! - * @brief Handles upsampling in bilinear mode - * @ingroup layers_upsample - * @param layer upsample layer - */ -AI_INTERNAL_API -void forward_upsample_bilinear_is8os8(ai_layer* layer); - -/*! - * @brief Handles upsampling in zeros mode - * @ingroup layers_upsample - * @param layer upsample layer - */ -AI_INTERNAL_API -void forward_upsample_zeros_is16os16(ai_layer* layer); - -/*! - * @brief Handles upsampling in bilinear mode - * @ingroup layers_upsample - * @param layer upsample layer - */ -AI_INTERNAL_API -void forward_upsample_bilinear_is16os16(ai_layer* layer); -AI_API_DECLARE_END - -#endif /*LAYERS_UPSAMPLE_H*/ +/** + ****************************************************************************** + * @file layers_upsample_generic.h + * @author STMicroelectronics + * @brief header file of AI platform padding generic datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_UPSAMPLE_H +#define LAYERS_UPSAMPLE_H + +#include "layers_generic.h" + +/*! + * @defgroup layers_pad_generic Layers Definitions + * @brief definition + * + */ +AI_API_DECLARE_BEGIN + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + + +/*! + * @brief Handles upsampling in zeros mode + * @ingroup layers_upsample + * @param layer upsample layer + */ +AI_INTERNAL_API +void forward_upsample_zeros_is8os8(ai_layer* layer); + +/*! + * @brief Handles upsampling in bilinear mode + * @ingroup layers_upsample + * @param layer upsample layer + */ +AI_INTERNAL_API +void forward_upsample_bilinear_is8os8(ai_layer* layer); + +/*! + * @brief Handles upsampling in zeros mode + * @ingroup layers_upsample + * @param layer upsample layer + */ +AI_INTERNAL_API +void forward_upsample_zeros_is16os16(ai_layer* layer); + +/*! + * @brief Handles upsampling in bilinear mode + * @ingroup layers_upsample + * @param layer upsample layer + */ +AI_INTERNAL_API +void forward_upsample_bilinear_is16os16(ai_layer* layer); +AI_API_DECLARE_END + +#endif /*LAYERS_UPSAMPLE_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_upsample_generic.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_upsample_generic.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_upsample_generic.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_upsample_generic.h index 57230e5d..7178d518 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/layers_upsample_generic.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/layers_upsample_generic.h @@ -1,61 +1,61 @@ -/** - ****************************************************************************** - * @file layers_upsample_generic.h - * @author STMicroelectronics - * @brief header file of AI platform padding generic datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LAYERS_UPSAMPLE_GENERIC_H -#define LAYERS_UPSAMPLE_GENERIC_H - -#include "layers_generic.h" - -/*! - * @defgroup layers_pad_generic Layers Definitions - * @brief definition - * - */ -AI_API_DECLARE_BEGIN - - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Handles generic upsampling in nearest mode - * @ingroup layers_generic - * @param layer upsample layer - */ -AI_INTERNAL_API -void forward_upsample_nearest(ai_layer *pLayer); - -/*! - * @brief Handles generic upsampling in zeros mode - * @ingroup layers_generic - * @param layer upsample layer - */ -AI_INTERNAL_API -void forward_upsample_zeros(ai_layer *pLayer); - -/*! - * @brief Handles generic upsampling in bilinear mode - * @ingroup layers_generic - * @param layer upsample layer - */ -AI_INTERNAL_API -void forward_upsample_bilinear(ai_layer *pLayer); - -AI_API_DECLARE_END - -#endif /*LAYERS_UPSAMPLE_GENERIC_H*/ +/** + ****************************************************************************** + * @file layers_upsample_generic.h + * @author STMicroelectronics + * @brief header file of AI platform padding generic datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LAYERS_UPSAMPLE_GENERIC_H +#define LAYERS_UPSAMPLE_GENERIC_H + +#include "layers_generic.h" + +/*! + * @defgroup layers_pad_generic Layers Definitions + * @brief definition + * + */ +AI_API_DECLARE_BEGIN + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles generic upsampling in nearest mode + * @ingroup layers_generic + * @param layer upsample layer + */ +AI_INTERNAL_API +void forward_upsample_nearest(ai_layer *pLayer); + +/*! + * @brief Handles generic upsampling in zeros mode + * @ingroup layers_generic + * @param layer upsample layer + */ +AI_INTERNAL_API +void forward_upsample_zeros(ai_layer *pLayer); + +/*! + * @brief Handles generic upsampling in bilinear mode + * @ingroup layers_generic + * @param layer upsample layer + */ +AI_INTERNAL_API +void forward_upsample_bilinear(ai_layer *pLayer); + +AI_API_DECLARE_END + +#endif /*LAYERS_UPSAMPLE_GENERIC_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_argminmax.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_argminmax.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_argminmax.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_argminmax.h index 2f10d9a1..9a8e59f3 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_argminmax.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_argminmax.h @@ -1,61 +1,61 @@ -/** - ****************************************************************************** - * @file lite_argminmax.h - * @author AIS - * @brief header file of AI platform lite argmin argmax funcions - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_ARGMINMAX_H -#define LITE_ARGMINMAX_H - -#include "ai_lite_interface.h" - - -void forward_lite_argmax_if32( const ai_float* in_data, - ai_u32* dst_out, - const ai_size width_in, - const ai_size height_in, - const ai_size n_channel_in, - const ai_i16 axis, - const ai_i16 select_last_index); -void forward_lite_argmin_if32( const ai_float* in_data, - ai_u32* dst_out, - const ai_size width_in, - const ai_size height_in, - const ai_size n_channel_in, - const ai_i16 axis, - const ai_i16 select_last_index); -void forward_lite_argmax_is8( const ai_i8* in_data, - ai_u32* dst_out, - const ai_size width_in, - const ai_size height_in, - const ai_size n_channel_in, - const ai_i16 axis, - const ai_i16 select_last_index); -void forward_lite_argmax_iu8( const ai_u8* in_data, - ai_u32* dst_out, - const ai_size width_in, - const ai_size height_in, - const ai_size n_channel_in, - const ai_i16 axis, - const ai_i16 select_last_index); -void forward_lite_argmin_is8( const ai_i8* in_data, - ai_u32* dst_out, - const ai_size width_in, - const ai_size height_in, - const ai_size n_channel_in, - const ai_i16 axis, - const ai_i16 select_last_index); - - -#endif /*LITE_ARGMINMAX_H*/ +/** + ****************************************************************************** + * @file lite_argminmax.h + * @author AIS + * @brief header file of AI platform lite argmin argmax funcions + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_ARGMINMAX_H +#define LITE_ARGMINMAX_H + +#include "ai_lite_interface.h" + + +void forward_lite_argmax_if32( const ai_float* in_data, + ai_u32* dst_out, + const ai_size width_in, + const ai_size height_in, + const ai_size n_channel_in, + const ai_i16 axis, + const ai_i16 select_last_index); +void forward_lite_argmin_if32( const ai_float* in_data, + ai_u32* dst_out, + const ai_size width_in, + const ai_size height_in, + const ai_size n_channel_in, + const ai_i16 axis, + const ai_i16 select_last_index); +void forward_lite_argmax_is8( const ai_i8* in_data, + ai_u32* dst_out, + const ai_size width_in, + const ai_size height_in, + const ai_size n_channel_in, + const ai_i16 axis, + const ai_i16 select_last_index); +void forward_lite_argmax_iu8( const ai_u8* in_data, + ai_u32* dst_out, + const ai_size width_in, + const ai_size height_in, + const ai_size n_channel_in, + const ai_i16 axis, + const ai_i16 select_last_index); +void forward_lite_argmin_is8( const ai_i8* in_data, + ai_u32* dst_out, + const ai_size width_in, + const ai_size height_in, + const ai_size n_channel_in, + const ai_i16 axis, + const ai_i16 select_last_index); + + +#endif /*LITE_ARGMINMAX_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_bn_f32.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_bn_f32.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_bn_f32.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_bn_f32.h index 1b3aa62e..b70ab029 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_bn_f32.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_bn_f32.h @@ -1,42 +1,42 @@ -/** - ****************************************************************************** - * @file lite_bnf32.h - * @author AIS - * @brief header file of AI platform lite batch normalization functions - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_BN_F32_H -#define LITE_BN_F32_H - - -#include "ai_lite_interface.h" - -/*! - * @brief Forward function for a batch normalization (BN) layer with - * signed float input, signed float output, and float parameters. - * @ingroup lite_bn_f32 - * @param output The pointer to output buffer. - * @param input The pointer to input buffer. - * @param scale The pointer to BN scale param. - * @param bias The pointer to bias. - * @param n_elements The number of elements in the input tensor. - * @param n_channel_in The number of channel in the input tensor. - */ -LITE_API_ENTRY -void forward_lite_bn_if32of32wf32( - ai_float* output, const ai_float* input, - const ai_float* scale, const ai_float* bias, - const ai_u32 n_elements, const ai_u32 n_channel_in); - - -#endif /* LITE_BN_F32_H */ +/** + ****************************************************************************** + * @file lite_bnf32.h + * @author AIS + * @brief header file of AI platform lite batch normalization functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_BN_F32_H +#define LITE_BN_F32_H + + +#include "ai_lite_interface.h" + +/*! + * @brief Forward function for a batch normalization (BN) layer with + * signed float input, signed float output, and float parameters. + * @ingroup lite_bn_f32 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param scale The pointer to BN scale param. + * @param bias The pointer to bias. + * @param n_elements The number of elements in the input tensor. + * @param n_channel_in The number of channel in the input tensor. + */ +LITE_API_ENTRY +void forward_lite_bn_if32of32wf32( + ai_float* output, const ai_float* input, + const ai_float* scale, const ai_float* bias, + const ai_u32 n_elements, const ai_u32 n_channel_in); + + +#endif /* LITE_BN_F32_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_bn_integer.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_bn_integer.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_bn_integer.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_bn_integer.h index e68ea3f2..fd89fd56 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_bn_integer.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_bn_integer.h @@ -1,216 +1,216 @@ -/** - ****************************************************************************** - * @file lite_bn_integer.h - * @author AIS - * @brief header file of AI platform lite integer batch normalization - * normalization functions - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_BN_INTEGER_H -#define LITE_BN_INTEGER_H - - -#include "ai_lite_interface.h" - -/** - * @brief Batch Normalization with 16-bit input, 16-bit threshold and binary output. - * It is implemented using a threshold, and this is possible because the output is binary. - * - * @param[in] pIn Input data pointer - * @param[out] pOut_32 Output data pointer - * @param[in] pThreshold Thresholds pointer (one per channel) - * @param[in] dim_x X dimension - * @param[in] dim_y Y dimension - * @param[in] channels_num Channels number - */ -LITE_API_ENTRY -void forward_lite_bn_is16os1ws16(const ai_i16 *pIn, - ai_u32 *pOut_32, - const ai_i16 *pThreshold, - const ai_i16 dim_x, - const ai_i16 dim_y, - const ai_i16 channels_num); - - - - - -/** - * @brief Batch Normalization with signed 8-bit input, output. - * - * @param[in] p_in Input data pointer - * @param[out] p_out Output data pointer - * @param[in] n_channel_inout nb channels - * @param[in] n_elements nb elements - * @param[in] in_scale input scale - * @param[in] in_zeropoint input zero point - * @param[in] out_scale output scale - * @param[in] out_zeropoint output zero point - * @param[in] pSc_scale pointer on scale scales - * @param[in] pSc_zeropoint pointer on scale zero_point - * @param[in] pScale_data pointer on scale input - * @param[in] pBias_scale pointer on bias scales - * @param[in] pBias_zeropoint pointer on bias zero_point - * @param[in] pBias_data pointer on bias input - * @param[in] bnl_param_sign sign of BNL parameters (0=unsigned, 1=signed) - * @param[in] pBuffer_a scratch buffer for: - * out factor: nb channels * sizeof(ai_i32) + - * out offset: nb channels * sizeof(ai_i32) + - * out shift: nb channels * sizeof(ai_i16) - */ -void forward_lite_bn_is8os8( const ai_i8 *p_in, - ai_i8 *p_out, - ai_size n_channel_inout, - ai_size n_elements, - ai_float in_scale, - const ai_i32 in_zeropoint, - ai_float out_scale, - const ai_i32 out_zeropoint, - const ai_float *pSc_scale, - const ai_i8 *pSc_zeropoint, - const ai_i8 *pData_scale, - const ai_float *pBias_scale, - const ai_i8 *pBias_zeropoint, - const ai_i8 *pData_bias, - ai_i16 bnl_param_sign, - ai_i32 scratch_size, - ai_i16 *pBuffer_a); - -/** - * @brief Batch Normalization with signed 8-bit input, output - * per channel quantization - * - * - * @param[in] p_in Input data pointer - * @param[out] p_out Output data pointer - * @param[in] n_channel_inout nb channels - * @param[in] n_elements nb elements - * @param[in] in_scale input scale - * @param[in] in_zeropoint input zero point - * @param[in] out_scale output scale - * @param[in] out_zeropoint output zero point - * @param[in] pSc_scale pointer on scale scales - * @param[in] pSc_zeropoint pointer on scale zero_point - * @param[in] pScale_data pointer on scale input - * @param[in] pBias_scale pointer on bias scales - * @param[in] pBias_zeropoint pointer on bias zero_point - * @param[in] pBias_data pointer on bias input - * @param[in] bnl_param_sign sign of BNL parameters (0=unsigned, 1=signed) - * @param[in] pBuffer_a scratch buffer for: - * out factor: nb channels * sizeof(ai_i32) + - * out offset: nb channels * sizeof(ai_i32) + - * out shift: nb channels * sizeof(ai_i16) - */ -void forward_lite_bn_is8os8_ch( const ai_i8 *p_in, - ai_i8 *p_out, - ai_size n_channel_inout, - ai_size n_elements, - ai_float in_scale, - const ai_i32 in_zeropoint, - ai_float out_scale, - const ai_i32 out_zeropoint, - const ai_float *pSc_scale, - const ai_i8 *pSc_zeropoint, - const ai_i8 *pData_scale, - const ai_float *pBias_scale, - const ai_i8 *pBias_zeropoint, - const ai_i8 *pData_bias, - ai_i16 bnl_param_sign, - ai_i32 scratch_size, - ai_i16 *pBuffer_a); - -/** - * @brief Batch Normalization with unsigned 8-bit input, output - * - * - * @param[in] p_in Input data pointer - * @param[out] p_out Output data pointer - * @param[in] n_channel_inout nb channels - * @param[in] n_elements nb elements - * @param[in] in_scale input scale - * @param[in] in_zeropoint input zero point - * @param[in] out_scale output scale - * @param[in] out_zeropoint output zero point - * @param[in] pSc_scale pointer on scale scales - * @param[in] pSc_zeropoint pointer on scale zero_point - * @param[in] pScale_data pointer on scale input - * @param[in] pBias_scale pointer on bias scales - * @param[in] pBias_zeropoint pointer on bias zero_point - * @param[in] pBias_data pointer on bias input - * @param[in] bnl_param_sign sign of BNL parameters (0=unsigned, 1=signed) - * @param[in] pBuffer_a scratch buffer for: - * out factor: nb channels * sizeof(ai_i32) + - * out offset: nb channels * sizeof(ai_i32) + - * out shift: nb channels * sizeof(ai_i16) - */ -void forward_lite_bn_iu8ou8( const ai_u8 *p_in, - ai_u8 *p_out, - ai_size n_channel_inout, - ai_size n_elements, - ai_float in_scale, - const ai_i32 in_zeropoint_32, - ai_float out_scale, - const ai_i32 out_zeropoint_32, - const ai_float *pSc_scale, - const ai_i8 *pSc_zeropoint, - const ai_i8 *pData_scale, - const ai_float *pBias_scale, - const ai_i8 *pBias_zeropoint, - const ai_i8 *pData_bias, - ai_i16 bnl_param_sign, - ai_i32 scratch_size, - ai_i16 *pBuffer_a); - -/** - * @brief Batch Normalization with unsigned 8-bit input, output - * per channel quantization - * - * - * @param[in] p_in Input data pointer - * @param[out] p_out Output data pointer - * @param[in] n_channel_inout nb channels - * @param[in] n_elements nb elements - * @param[in] in_scale input scale - * @param[in] in_zeropoint input zero point - * @param[in] out_scale output scale - * @param[in] out_zeropoint output zero point - * @param[in] pSc_scale pointer on scale scales - * @param[in] pSc_zeropoint pointer on scale zero_point - * @param[in] pScale_data pointer on scale input - * @param[in] pBias_scale pointer on bias scales - * @param[in] pBias_zeropoint pointer on bias zero_point - * @param[in] pBias_data pointer on bias input - * @param[in] bnl_param_sign sign of BNL parameters (0=unsigned, 1=signed) - * @param[in] pBuffer_a scratch buffer for: - * out factor: nb channels * sizeof(ai_i32) + - * out offset: nb channels * sizeof(ai_i32) + - * out shift: nb channels * sizeof(ai_i16) - */ -void forward_lite_bn_iu8ou8_ch( const ai_u8 *p_in, - ai_u8 *p_out, - ai_size n_channel_inout, - ai_size n_elements, - ai_float in_scale, - const ai_i32 in_zeropoint, - ai_float out_scale, - const ai_i32 out_zeropoint, - const ai_float *pSc_scale, - const ai_i8 *pSc_zeropoint, - const ai_i8 *pData_scale, - const ai_float *pBias_scale, - const ai_i8 *pBias_zeropoint, - const ai_i8 *pData_bias, - ai_i16 bnl_param_sign, - ai_i32 scratch_size, - ai_i16 *pBuffer_a); -#endif /* LITE_BN_INTEGER_H */ +/** + ****************************************************************************** + * @file lite_bn_integer.h + * @author AIS + * @brief header file of AI platform lite integer batch normalization + * normalization functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_BN_INTEGER_H +#define LITE_BN_INTEGER_H + + +#include "ai_lite_interface.h" + +/** + * @brief Batch Normalization with 16-bit input, 16-bit threshold and binary output. + * It is implemented using a threshold, and this is possible because the output is binary. + * + * @param[in] pIn Input data pointer + * @param[out] pOut_32 Output data pointer + * @param[in] pThreshold Thresholds pointer (one per channel) + * @param[in] dim_x X dimension + * @param[in] dim_y Y dimension + * @param[in] channels_num Channels number + */ +LITE_API_ENTRY +void forward_lite_bn_is16os1ws16(const ai_i16 *pIn, + ai_u32 *pOut_32, + const ai_i16 *pThreshold, + const ai_i16 dim_x, + const ai_i16 dim_y, + const ai_i16 channels_num); + + + + + +/** + * @brief Batch Normalization with signed 8-bit input, output. + * + * @param[in] p_in Input data pointer + * @param[out] p_out Output data pointer + * @param[in] n_channel_inout nb channels + * @param[in] n_elements nb elements + * @param[in] in_scale input scale + * @param[in] in_zeropoint input zero point + * @param[in] out_scale output scale + * @param[in] out_zeropoint output zero point + * @param[in] pSc_scale pointer on scale scales + * @param[in] pSc_zeropoint pointer on scale zero_point + * @param[in] pScale_data pointer on scale input + * @param[in] pBias_scale pointer on bias scales + * @param[in] pBias_zeropoint pointer on bias zero_point + * @param[in] pBias_data pointer on bias input + * @param[in] bnl_param_sign sign of BNL parameters (0=unsigned, 1=signed) + * @param[in] pBuffer_a scratch buffer for: + * out factor: nb channels * sizeof(ai_i32) + + * out offset: nb channels * sizeof(ai_i32) + + * out shift: nb channels * sizeof(ai_i16) + */ +void forward_lite_bn_is8os8( const ai_i8 *p_in, + ai_i8 *p_out, + ai_size n_channel_inout, + ai_size n_elements, + ai_float in_scale, + const ai_i32 in_zeropoint, + ai_float out_scale, + const ai_i32 out_zeropoint, + const ai_float *pSc_scale, + const ai_i8 *pSc_zeropoint, + const ai_i8 *pData_scale, + const ai_float *pBias_scale, + const ai_i8 *pBias_zeropoint, + const ai_i8 *pData_bias, + ai_i16 bnl_param_sign, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +/** + * @brief Batch Normalization with signed 8-bit input, output + * per channel quantization + * + * + * @param[in] p_in Input data pointer + * @param[out] p_out Output data pointer + * @param[in] n_channel_inout nb channels + * @param[in] n_elements nb elements + * @param[in] in_scale input scale + * @param[in] in_zeropoint input zero point + * @param[in] out_scale output scale + * @param[in] out_zeropoint output zero point + * @param[in] pSc_scale pointer on scale scales + * @param[in] pSc_zeropoint pointer on scale zero_point + * @param[in] pScale_data pointer on scale input + * @param[in] pBias_scale pointer on bias scales + * @param[in] pBias_zeropoint pointer on bias zero_point + * @param[in] pBias_data pointer on bias input + * @param[in] bnl_param_sign sign of BNL parameters (0=unsigned, 1=signed) + * @param[in] pBuffer_a scratch buffer for: + * out factor: nb channels * sizeof(ai_i32) + + * out offset: nb channels * sizeof(ai_i32) + + * out shift: nb channels * sizeof(ai_i16) + */ +void forward_lite_bn_is8os8_ch( const ai_i8 *p_in, + ai_i8 *p_out, + ai_size n_channel_inout, + ai_size n_elements, + ai_float in_scale, + const ai_i32 in_zeropoint, + ai_float out_scale, + const ai_i32 out_zeropoint, + const ai_float *pSc_scale, + const ai_i8 *pSc_zeropoint, + const ai_i8 *pData_scale, + const ai_float *pBias_scale, + const ai_i8 *pBias_zeropoint, + const ai_i8 *pData_bias, + ai_i16 bnl_param_sign, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +/** + * @brief Batch Normalization with unsigned 8-bit input, output + * + * + * @param[in] p_in Input data pointer + * @param[out] p_out Output data pointer + * @param[in] n_channel_inout nb channels + * @param[in] n_elements nb elements + * @param[in] in_scale input scale + * @param[in] in_zeropoint input zero point + * @param[in] out_scale output scale + * @param[in] out_zeropoint output zero point + * @param[in] pSc_scale pointer on scale scales + * @param[in] pSc_zeropoint pointer on scale zero_point + * @param[in] pScale_data pointer on scale input + * @param[in] pBias_scale pointer on bias scales + * @param[in] pBias_zeropoint pointer on bias zero_point + * @param[in] pBias_data pointer on bias input + * @param[in] bnl_param_sign sign of BNL parameters (0=unsigned, 1=signed) + * @param[in] pBuffer_a scratch buffer for: + * out factor: nb channels * sizeof(ai_i32) + + * out offset: nb channels * sizeof(ai_i32) + + * out shift: nb channels * sizeof(ai_i16) + */ +void forward_lite_bn_iu8ou8( const ai_u8 *p_in, + ai_u8 *p_out, + ai_size n_channel_inout, + ai_size n_elements, + ai_float in_scale, + const ai_i32 in_zeropoint_32, + ai_float out_scale, + const ai_i32 out_zeropoint_32, + const ai_float *pSc_scale, + const ai_i8 *pSc_zeropoint, + const ai_i8 *pData_scale, + const ai_float *pBias_scale, + const ai_i8 *pBias_zeropoint, + const ai_i8 *pData_bias, + ai_i16 bnl_param_sign, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +/** + * @brief Batch Normalization with unsigned 8-bit input, output + * per channel quantization + * + * + * @param[in] p_in Input data pointer + * @param[out] p_out Output data pointer + * @param[in] n_channel_inout nb channels + * @param[in] n_elements nb elements + * @param[in] in_scale input scale + * @param[in] in_zeropoint input zero point + * @param[in] out_scale output scale + * @param[in] out_zeropoint output zero point + * @param[in] pSc_scale pointer on scale scales + * @param[in] pSc_zeropoint pointer on scale zero_point + * @param[in] pScale_data pointer on scale input + * @param[in] pBias_scale pointer on bias scales + * @param[in] pBias_zeropoint pointer on bias zero_point + * @param[in] pBias_data pointer on bias input + * @param[in] bnl_param_sign sign of BNL parameters (0=unsigned, 1=signed) + * @param[in] pBuffer_a scratch buffer for: + * out factor: nb channels * sizeof(ai_i32) + + * out offset: nb channels * sizeof(ai_i32) + + * out shift: nb channels * sizeof(ai_i16) + */ +void forward_lite_bn_iu8ou8_ch( const ai_u8 *p_in, + ai_u8 *p_out, + ai_size n_channel_inout, + ai_size n_elements, + ai_float in_scale, + const ai_i32 in_zeropoint, + ai_float out_scale, + const ai_i32 out_zeropoint, + const ai_float *pSc_scale, + const ai_i8 *pSc_zeropoint, + const ai_i8 *pData_scale, + const ai_float *pBias_scale, + const ai_i8 *pBias_zeropoint, + const ai_i8 *pData_bias, + ai_i16 bnl_param_sign, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); +#endif /* LITE_BN_INTEGER_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_conv2d.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_conv2d.h similarity index 98% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_conv2d.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_conv2d.h index 0539eb6c..e8057788 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_conv2d.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_conv2d.h @@ -1,386 +1,386 @@ -/** - ****************************************************************************** - * @file lite_conv2d.h - * @author AIS - * @brief header file of AI platform lite conv2d kernel datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_CONV2D_H -#define LITE_CONV2D_H - -#include "ai_lite_interface.h" -#include "lite_internal_apis.h" - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Handles 2D convolution with float input, float output and - * float weights - * @ingroup lite_conv2d - */ -LITE_API_ENTRY -void forward_lite_conv2d_if32of32wf32(const ai_float *pDataIn_init, - ai_float *pDataOut_init, - const ai_ptr_const pWeights_init, - const ai_ptr_const pBias_init, - ai_float *pWeights_prefetch, - const ai_size n_channel_in, - const ai_size n_channel_out, - const ai_size width_in, - const ai_size height_in, - const ai_size width_out, - const ai_size height_out, - const ai_size filt_width, - const ai_size filt_height, - const ai_u16 filt_pad_x, - const ai_u16 filt_pad_y, - const ai_u16 filt_stride_x, - const ai_u16 filt_stride_y, - const ai_size filt_height_dilated, - const ai_size filt_width_dilated, - const ai_u16 dilation_x, - const ai_u16 dilation_y, - const ai_size n_groups); - -/*! - * @brief Handles 2D depthwise convolution with float input, float output and - * float weights - * @ingroup lite_conv2d - */ -LITE_API_ENTRY -void forward_lite_dw_if32of32wf32(const ai_float *pDataIn_init, - ai_float *pDataOut_init, - const ai_ptr_const pWeights_init, - const ai_ptr_const pBias_init, - const ai_size n_channel_in, - const ai_size n_channel_out, - const ai_size width_in, - const ai_size height_in, - const ai_size width_out, - const ai_size height_out, - const ai_size filt_width, - const ai_size filt_height, - const ai_u16 filt_pad_x, - const ai_u16 filt_pad_y, - const ai_u16 filt_stride_x, - const ai_u16 filt_stride_y, - const ai_size filt_height_dilated, - const ai_size filt_width_dilated, - const ai_u16 dilation_x, - const ai_u16 dilation_y, - const ai_size n_groups); - -/*! - * @brief Handles 2D grouped convolution with float input, float output and - * float weights - * @ingroup lite_conv2d - */ -LITE_API_ENTRY -void forward_lite_conv2d_if32of32wf32_group(const ai_float *pDataIn_init, - ai_float *pDataOut_init, - const ai_ptr_const pWeights_init, - const ai_ptr_const pBias_init, - const ai_size n_channel_in, - const ai_size n_channel_out, - const ai_size width_in, - const ai_size height_in, - const ai_size width_out, - const ai_size height_out, - const ai_size filt_width, - const ai_size filt_height, - const ai_u16 filt_pad_x, - const ai_u16 filt_pad_y, - const ai_u16 filt_stride_x, - const ai_u16 filt_stride_y, - const ai_size filt_height_dilated, - const ai_size filt_width_dilated, - const ai_u16 dilation_x, - const ai_u16 dilation_y, - const ai_size n_groups); - -/*! - * @brief Handles dilated conv2d convolutions (valid padding) - * @ingroup lite_conv2d - */ -LITE_API_ENTRY -void -forward_lite_conv2d_dilated_sssa8_ch(const ai_i8 *pData_in, - const ai_u16 dim_im_in_x, - const ai_u16 dim_im_in_y, - const ai_u16 n_channel_in, - const ai_i8 *pWeights, - const ai_u16 n_channel_out, - const ai_u16 dim_kernel_x, - const ai_u16 dim_kernel_y, - const ai_u16 stride_x, - const ai_u16 stride_y, - const ai_u16 dilation_x, - const ai_u16 dilation_y, - const ai_i32 *pBias, - const ai_i8 in_zeropoint, - const ai_i8 out_zeropoint, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - const ai_layer_format_type out_ch_format, - ai_i8 *pData_out, - const ai_u16 dim_im_out_x, - const ai_u16 dim_im_out_y, - ai_u32 height_loop_cnt, - const ai_u16 weights_prefetch_enabled, - ai_i32 scratch_size, - ai_i16 *pBuffer_a); - -/*! - * @brief Handles conv2d convolutions (valid padding) with number of channels >= 8 - * @ingroup lite_conv2d - */ -LITE_API_ENTRY -void -forward_lite_conv2d_deep_sssa8_ch(const ai_i8 *pData_in, - const ai_u16 dim_im_in_x, - const ai_u16 dim_im_in_y, - const ai_u16 n_channel_in, - const ai_i8 *pWeights, - const ai_u16 n_channel_out, - const ai_u16 dim_kernel_x, - const ai_u16 dim_kernel_y, - const ai_u16 stride_x, - const ai_u16 stride_y, - const ai_i32 *pBias, - const ai_i8 in_zeropoint, - const ai_i8 out_zeropoint, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - const ai_layer_format_type out_ch_format, - ai_i8 *pData_out, - const ai_u16 dim_im_out_x, - const ai_u16 dim_im_out_y, - ai_u32 height_loop_cnt, - const ai_u16 weights_prefetch_enabled, - ai_i32 scratch_size, - ai_i16 *pBuffer_a); -/*! - * @brief Handles conv2d convolutions (valid padding) with number of channels >= 8 - * Special forward function for 3x3 kernels and Stride = 1 - * @ingroup lite_conv2d - */ -LITE_API_ENTRY -void -forward_lite_conv2d_deep_3x3_sssa8_ch(const ai_i8 *pData_in, - const ai_u16 dim_im_in_x, - const ai_u16 dim_im_in_y, - const ai_u16 n_channel_in, - const ai_i8 *pWeights, - const ai_u16 n_channel_out, - const ai_i32 *pBias, - const ai_i8 in_zeropoint, - const ai_i8 out_zeropoint, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - const ai_layer_format_type out_ch_format, - ai_i8 *pData_out, - const ai_u16 dim_im_out_x, - const ai_u16 dim_im_out_y, - ai_u32 height_loop_cnt, - ai_i32 scratch_size, - ai_i16 *pBuffer_a); - -/*! - * @brief Handles conv2d convolutions with same padding or with number of channels < 8 - * @ingroup lite_conv2d - */ -LITE_API_ENTRY -void -forward_lite_conv2d_sssa8_ch(const ai_i8 *pData_in, - const ai_u16 dim_im_in_x, - const ai_u16 dim_im_in_y, - const ai_u16 n_channel_in, - const ai_i8 *pWeights, - const ai_u16 n_channel_out, - const ai_u16 dim_kernel_x, - const ai_u16 dim_kernel_y, - const ai_u16 stride_x, - const ai_u16 stride_y, - const ai_u16 padding_x, - const ai_u16 padding_y, - const ai_i32 *pBias, - const ai_i8 in_zeropoint, - const ai_i8 out_zeropoint, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - const ai_layer_format_type out_ch_format, - ai_i8 *pData_out, - const ai_u16 dim_im_out_x, - const ai_u16 dim_im_out_y, - const ai_u16 weights_prefetch_enabled, - ai_i32 scratch_size, - ai_i16 *pBuffer_a); - -/*! - * @brief Handles rgb conv2d convolutions - * @ingroup lite_conv2d - */ -LITE_API_ENTRY -void -forward_lite_conv2d_rgb_sssa8_ch(const ai_i8 *pData_in, - const ai_u16 dim_im_in, - const ai_i8 *pWeights, - const ai_u16 n_channel_out, - const ai_u16 dim_kernel, - const ai_u16 padding, - const ai_u16 stride, - const ai_i32 *pBias, - const ai_i8 in_zeropoint, - const ai_i8 out_zeropoint, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - const ai_layer_format_type out_ch_format, - ai_i8 *pData_out, - const ai_u16 dim_im_out, - ai_i32 scratch_size, - ai_i16 *pBuffer_a); - -/*! - * @brief Handles 2D convolution with float input, float output and - * float weights with pool fused - * @ingroup lite_conv2d - */ -LITE_API_ENTRY -void forward_lite_conv2d_if32of32wf32_pool(const ai_float *pDataIn_init, - ai_float *pDataOut_init, - const ai_float *pWeights_init, - const ai_float *pBias_init, - ai_float *pScratch_init, - ai_float *pWeights_prefetch, - const ai_short_size n_channel_in, - const ai_short_size n_channel_out, - const ai_short_size width_in, - const ai_short_size height_in, - const ai_short_size width_out, - const ai_short_size height_out, - const ai_short_size filt_width, - const ai_short_size filt_height, - const ai_u16 filt_pad_x, - const ai_u16 filt_pad_y, - const ai_u16 filt_stride_x, - const ai_u16 filt_stride_y, - const ai_short_size filt_height_dilated, - const ai_short_size filt_width_dilated, - const ai_u16 dilation_x, - const ai_u16 dilation_y, - const ai_short_size n_groups, - const ai_short_size width_conv_out, - const ai_short_size height_conv_out, - func_nl_lite nl_func_lite, - ai_ptr_const nl_params, - const ai_ptr_offset nl_params_step, - const ai_ptr_offset nl_params_size, - ai_handle pool_func, - const ai_short_size pool_width, - const ai_short_size pool_height, - const ai_short_size pool_stride_x, - const ai_short_size pool_stride_y, - const ai_short_size pool_pad_x, - const ai_short_size pool_pad_y); - -/*! - * @brief Handles 2D depthwise convolution with float input, float output and - * float weights with pool fused - * @ingroup lite_conv2d - */ -LITE_API_ENTRY -void forward_lite_dw_if32of32wf32_pool(const ai_float *pDataIn_init, - ai_float *pDataOut_init, - const ai_float *pWeights_init, - const ai_float *pBias_init, - ai_float *pScratch_init, - const ai_short_size n_channel_in, - const ai_short_size n_channel_out, - const ai_short_size width_in, - const ai_short_size height_in, - const ai_short_size width_out, - const ai_short_size height_out, - const ai_short_size filt_width, - const ai_short_size filt_height, - const ai_u16 filt_pad_x, - const ai_u16 filt_pad_y, - const ai_u16 filt_stride_x, - const ai_u16 filt_stride_y, - const ai_short_size filt_height_dilated, - const ai_short_size filt_width_dilated, - const ai_u16 dilation_x, - const ai_u16 dilation_y, - const ai_short_size n_groups, - const ai_short_size width_conv_out, - const ai_short_size height_conv_out, - func_nl_lite nl_func_lite, - ai_ptr_const nl_params, - const ai_ptr_offset nl_params_step, - const ai_ptr_offset nl_params_size, - ai_handle pool_func, - const ai_short_size pool_width, - const ai_short_size pool_height, - const ai_short_size pool_stride_x, - const ai_short_size pool_stride_y, - const ai_short_size pool_pad_x, - const ai_short_size pool_pad_y); -/*! - * @brief Handles 2D grouped convolution with float input, float output and - * float weights with pool fused - * @ingroup lite_conv2d - */ -LITE_API_ENTRY -void forward_lite_conv2d_if32of32wf32_group_pool(const ai_float *pDataIn_init, - ai_float *pDataOut_init, - const ai_float *pWeights_init, - const ai_float *pBias_init, - ai_float *pScratch_init, - const ai_short_size n_channel_in, - const ai_short_size n_channel_out, - const ai_short_size width_in, - const ai_short_size height_in, - const ai_short_size width_out, - const ai_short_size height_out, - const ai_short_size filt_width, - const ai_short_size filt_height, - const ai_u16 filt_pad_x, - const ai_u16 filt_pad_y, - const ai_u16 filt_stride_x, - const ai_u16 filt_stride_y, - const ai_short_size filt_height_dilated, - const ai_short_size filt_width_dilated, - const ai_u16 dilation_x, - const ai_u16 dilation_y, - const ai_short_size n_groups, - const ai_short_size width_conv_out, - const ai_short_size height_conv_out, - func_nl_lite nl_func_lite, - ai_ptr_const nl_params, - const ai_ptr_offset nl_params_step, - const ai_ptr_offset nl_params_size, - ai_handle pool_func, - const ai_short_size pool_width, - const ai_short_size pool_height, - const ai_short_size pool_stride_x, - const ai_short_size pool_stride_y, - const ai_short_size pool_pad_x, - const ai_short_size pool_pad_y); - -#endif /*LITE_CONV2D_H*/ +/** + ****************************************************************************** + * @file lite_conv2d.h + * @author AIS + * @brief header file of AI platform lite conv2d kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_CONV2D_H +#define LITE_CONV2D_H + +#include "ai_lite_interface.h" +#include "lite_internal_apis.h" + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles 2D convolution with float input, float output and + * float weights + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void forward_lite_conv2d_if32of32wf32(const ai_float *pDataIn_init, + ai_float *pDataOut_init, + const ai_ptr_const pWeights_init, + const ai_ptr_const pBias_init, + ai_float *pWeights_prefetch, + const ai_size n_channel_in, + const ai_size n_channel_out, + const ai_size width_in, + const ai_size height_in, + const ai_size width_out, + const ai_size height_out, + const ai_size filt_width, + const ai_size filt_height, + const ai_u16 filt_pad_x, + const ai_u16 filt_pad_y, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_size filt_height_dilated, + const ai_size filt_width_dilated, + const ai_u16 dilation_x, + const ai_u16 dilation_y, + const ai_size n_groups); + +/*! + * @brief Handles 2D depthwise convolution with float input, float output and + * float weights + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void forward_lite_dw_if32of32wf32(const ai_float *pDataIn_init, + ai_float *pDataOut_init, + const ai_ptr_const pWeights_init, + const ai_ptr_const pBias_init, + const ai_size n_channel_in, + const ai_size n_channel_out, + const ai_size width_in, + const ai_size height_in, + const ai_size width_out, + const ai_size height_out, + const ai_size filt_width, + const ai_size filt_height, + const ai_u16 filt_pad_x, + const ai_u16 filt_pad_y, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_size filt_height_dilated, + const ai_size filt_width_dilated, + const ai_u16 dilation_x, + const ai_u16 dilation_y, + const ai_size n_groups); + +/*! + * @brief Handles 2D grouped convolution with float input, float output and + * float weights + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void forward_lite_conv2d_if32of32wf32_group(const ai_float *pDataIn_init, + ai_float *pDataOut_init, + const ai_ptr_const pWeights_init, + const ai_ptr_const pBias_init, + const ai_size n_channel_in, + const ai_size n_channel_out, + const ai_size width_in, + const ai_size height_in, + const ai_size width_out, + const ai_size height_out, + const ai_size filt_width, + const ai_size filt_height, + const ai_u16 filt_pad_x, + const ai_u16 filt_pad_y, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_size filt_height_dilated, + const ai_size filt_width_dilated, + const ai_u16 dilation_x, + const ai_u16 dilation_y, + const ai_size n_groups); + +/*! + * @brief Handles dilated conv2d convolutions (valid padding) + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void +forward_lite_conv2d_dilated_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_u16 dilation_x, + const ai_u16 dilation_y, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + ai_u32 height_loop_cnt, + const ai_u16 weights_prefetch_enabled, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +/*! + * @brief Handles conv2d convolutions (valid padding) with number of channels >= 8 + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void +forward_lite_conv2d_deep_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + ai_u32 height_loop_cnt, + const ai_u16 weights_prefetch_enabled, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); +/*! + * @brief Handles conv2d convolutions (valid padding) with number of channels >= 8 + * Special forward function for 3x3 kernels and Stride = 1 + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void +forward_lite_conv2d_deep_3x3_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + ai_u32 height_loop_cnt, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +/*! + * @brief Handles conv2d convolutions with same padding or with number of channels < 8 + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void +forward_lite_conv2d_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_u16 padding_x, + const ai_u16 padding_y, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_u16 weights_prefetch_enabled, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +/*! + * @brief Handles rgb conv2d convolutions + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void +forward_lite_conv2d_rgb_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_u16 dim_kernel, + const ai_u16 padding, + const ai_u16 stride, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +/*! + * @brief Handles 2D convolution with float input, float output and + * float weights with pool fused + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void forward_lite_conv2d_if32of32wf32_pool(const ai_float *pDataIn_init, + ai_float *pDataOut_init, + const ai_float *pWeights_init, + const ai_float *pBias_init, + ai_float *pScratch_init, + ai_float *pWeights_prefetch, + const ai_short_size n_channel_in, + const ai_short_size n_channel_out, + const ai_short_size width_in, + const ai_short_size height_in, + const ai_short_size width_out, + const ai_short_size height_out, + const ai_short_size filt_width, + const ai_short_size filt_height, + const ai_u16 filt_pad_x, + const ai_u16 filt_pad_y, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_short_size filt_height_dilated, + const ai_short_size filt_width_dilated, + const ai_u16 dilation_x, + const ai_u16 dilation_y, + const ai_short_size n_groups, + const ai_short_size width_conv_out, + const ai_short_size height_conv_out, + func_nl_lite nl_func_lite, + ai_ptr_const nl_params, + const ai_ptr_offset nl_params_step, + const ai_ptr_offset nl_params_size, + ai_handle pool_func, + const ai_short_size pool_width, + const ai_short_size pool_height, + const ai_short_size pool_stride_x, + const ai_short_size pool_stride_y, + const ai_short_size pool_pad_x, + const ai_short_size pool_pad_y); + +/*! + * @brief Handles 2D depthwise convolution with float input, float output and + * float weights with pool fused + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void forward_lite_dw_if32of32wf32_pool(const ai_float *pDataIn_init, + ai_float *pDataOut_init, + const ai_float *pWeights_init, + const ai_float *pBias_init, + ai_float *pScratch_init, + const ai_short_size n_channel_in, + const ai_short_size n_channel_out, + const ai_short_size width_in, + const ai_short_size height_in, + const ai_short_size width_out, + const ai_short_size height_out, + const ai_short_size filt_width, + const ai_short_size filt_height, + const ai_u16 filt_pad_x, + const ai_u16 filt_pad_y, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_short_size filt_height_dilated, + const ai_short_size filt_width_dilated, + const ai_u16 dilation_x, + const ai_u16 dilation_y, + const ai_short_size n_groups, + const ai_short_size width_conv_out, + const ai_short_size height_conv_out, + func_nl_lite nl_func_lite, + ai_ptr_const nl_params, + const ai_ptr_offset nl_params_step, + const ai_ptr_offset nl_params_size, + ai_handle pool_func, + const ai_short_size pool_width, + const ai_short_size pool_height, + const ai_short_size pool_stride_x, + const ai_short_size pool_stride_y, + const ai_short_size pool_pad_x, + const ai_short_size pool_pad_y); +/*! + * @brief Handles 2D grouped convolution with float input, float output and + * float weights with pool fused + * @ingroup lite_conv2d + */ +LITE_API_ENTRY +void forward_lite_conv2d_if32of32wf32_group_pool(const ai_float *pDataIn_init, + ai_float *pDataOut_init, + const ai_float *pWeights_init, + const ai_float *pBias_init, + ai_float *pScratch_init, + const ai_short_size n_channel_in, + const ai_short_size n_channel_out, + const ai_short_size width_in, + const ai_short_size height_in, + const ai_short_size width_out, + const ai_short_size height_out, + const ai_short_size filt_width, + const ai_short_size filt_height, + const ai_u16 filt_pad_x, + const ai_u16 filt_pad_y, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_short_size filt_height_dilated, + const ai_short_size filt_width_dilated, + const ai_u16 dilation_x, + const ai_u16 dilation_y, + const ai_short_size n_groups, + const ai_short_size width_conv_out, + const ai_short_size height_conv_out, + func_nl_lite nl_func_lite, + ai_ptr_const nl_params, + const ai_ptr_offset nl_params_step, + const ai_ptr_offset nl_params_size, + ai_handle pool_func, + const ai_short_size pool_width, + const ai_short_size pool_height, + const ai_short_size pool_stride_x, + const ai_short_size pool_stride_y, + const ai_short_size pool_pad_x, + const ai_short_size pool_pad_y); + +#endif /*LITE_CONV2D_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_conv2d_dqnn.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_conv2d_dqnn.h similarity index 98% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_conv2d_dqnn.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_conv2d_dqnn.h index be8067ac..435a865c 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_conv2d_dqnn.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_conv2d_dqnn.h @@ -1,568 +1,568 @@ -/** - ****************************************************************************** - * @file lite_conv2d_dqnn.h - * @author AIS - * @brief header file of AI platform lite dqnn conv kernel datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_CONV2D_DQNN_H -#define LITE_CONV2D_DQNN_H - -#include "ai_lite_interface.h" - -# define AI_16_OVERFLOW_CHECK(val_) (val_ <= 32767) - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -AI_API_DECLARE_BEGIN - -/*! - * @brief Handles 2D convolution with binary input, binary output and - * binary weights - with 0 padding (QKeras like) - Lite I/F - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_conv2d_is1os1ws1_bn_pad0(const ai_u32 *pDataIn_init, - ai_u32 *pDataOut_init, - const ai_u32 *pWeights_init, - ai_float *pScratch_32, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_in, - const ai_i32 height_in, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_i32 filt_width, - const ai_i32 filt_height, - const ai_i32 filt_pad_x, - const ai_i32 filt_pad_y, - const ai_i32 filt_stride_x, - const ai_i32 filt_stride_y, - const ai_i32 *pThreshold); - -/*! - * @brief Handles 2D convolution with binary input, binary output and - * binary weights - with 0 padding (QKeras like) - Lite I/F - * - Optimized thanks to Optim0 assumptions - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_conv2d_is1os1ws1_bn_pad0_optim0(const ai_u32 *pDataIn_init, - ai_u32 *pDataOut_init, - const ai_u32 *pWeights_init, - ai_float *pScratch_32, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_in, - const ai_i32 height_in, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_i32 filt_width, - const ai_i32 filt_height, - const ai_i32 filt_pad_x, - const ai_i32 filt_pad_y, - const ai_i32 filt_stride_x, - const ai_i32 filt_stride_y, - const ai_i32 *pThreshold); - -/*! - * @brief Handles 2D convolution with binary input, 8-bits output and - * binary weights - with 0 padding (QKeras like) - Lite I/F - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_conv2d_is1os8ws1_bn_pad0(const ai_u32 *pDataIn_init, - ai_i8 *pDataOut_init, - const ai_u32 *pWeights_init, - ai_float *pScratch_32, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_in, - const ai_i32 height_in, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_i32 filt_width, - const ai_i32 filt_height, - const ai_i32 filt_pad_x, - const ai_i32 filt_pad_y, - const ai_i32 filt_stride_x, - const ai_i32 filt_stride_y, - const ai_float *pScale, - const ai_float *pOffset); - -/*! - * @brief Handles 2D convolution with binary input, binary output and - * binary weights - with +1/-1 padding (Larq like) - Lite I/F - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_conv2d_is1os1ws1_bn_pad1(const ai_u32 *pDataIn_init, - ai_u32 *pDataOut_init, - const ai_u32 *pWeights_init, - ai_float *pScratch_32, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_in, - const ai_i32 height_in, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_i32 filt_width, - const ai_i32 filt_height, - const ai_i32 filt_pad_x, - const ai_i32 filt_pad_y, - const ai_i32 filt_stride_x, - const ai_i32 filt_stride_y, - const ai_i32 *pThreshold, - const ai_i32 pad_value); - -/*! - * @brief Handles 2D convolution with binary input, binary output and - * binary weights - with +1/-1 padding (Larq like) - Lite I/F - * - Optimized thanks to Optim2 assumptions - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_conv2d_is1os1ws1_bn_pad1_optim2(const ai_u32 *pDataIn_init, - ai_u32 *pDataOut_init, - const ai_u32 *pWeights_init, - ai_float *pScratch_32, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_in, - const ai_i32 height_in, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_i32 filt_width, - const ai_i32 filt_height, - const ai_i32 filt_pad_x, - const ai_i32 filt_pad_y, - const ai_i32 filt_stride_x, - const ai_i32 filt_stride_y, - const ai_i32 *pThreshold, - const ai_i32 pad_value); - -/*! - * @brief Handles 2D convolution with binary input, binary output and - * binary weights - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_conv2d_is1os1ws1_bn(const ai_u32 *pDataIn_init, - ai_u32 * pDataOut_init, - const ai_u32 *pWeights_init, - ai_float *pScratch_32, - const ai_u16 n_channel_in, - const ai_u16 n_channel_out, - const ai_u16 width_in, - const ai_u16 height_in, - const ai_u16 width_out, - const ai_u16 height_out, - const ai_u16 filt_width, - const ai_u16 filt_height, - const ai_u16 filt_pad_x, - const ai_u16 filt_pad_y, - const ai_u16 filt_stride_x, - const ai_u16 filt_stride_y, - const ai_i32 *pThreshold, - const ai_u8 flatten_output); - -/*! - * @brief Handles 2D convolution with binary input, 8-bits output and - * binary weights - with +1/-1 padding (Larq like) - Lite I/F - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_conv2d_is1os8ws1_bn_pad1(const ai_u32 *pDataIn_init, - ai_i8 *pDataOut_init, - const ai_u32 *pWeights_init, - ai_float *pScratch_32, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_in, - const ai_i32 height_in, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_i32 filt_width, - const ai_i32 filt_height, - const ai_i32 filt_pad_x, - const ai_i32 filt_pad_y, - const ai_i32 filt_stride_x, - const ai_i32 filt_stride_y, - const ai_float *pScale, - const ai_float *pOffset, - const ai_i32 pad_value); - -/*! - * @brief Handles 2D convolution with binary input, 8-bits output and - * binary weights - with +1/-1 padding (Larq like) - Lite I/F - * - Optimized thanks to Optim1 assumptions - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_conv2d_is1os8ws1_bn_pad1_optim1(const ai_u32 *pDataIn_init, - ai_i8 *pDataOut_init, - const ai_u32 *pWeights_init, - ai_float *pScratch_32, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_in, - const ai_i32 height_in, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_i32 filt_width, - const ai_i32 filt_height, - const ai_i32 filt_pad_x, - const ai_i32 filt_pad_y, - const ai_i32 filt_stride_x, - const ai_i32 filt_stride_y, - const ai_float *pScale, - const ai_float *pOffset, - const ai_i32 pad_value); - -/** - * @brief Handles 2D convolution with binary input, fixed point 16-bits output and - * binary weights - with 0 padding (QKeras like) - Lite I/F - - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_conv2d_is1os16ws1_bn_pad0_fxp(const ai_u32 *pDataIn_init, - ai_i16 *pDataOut_init, - const ai_u32 *pWeights_init, - ai_float *pScratch_32, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_in, - const ai_i32 height_in, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_i32 filt_width, - const ai_i32 filt_height, - const ai_i32 filt_pad_x, - const ai_i32 filt_pad_y, - const ai_i32 filt_stride_x, - const ai_i32 filt_stride_y, - const ai_float *pScale_init, - const ai_float *pOffset_init); - -/*! - * @brief Handles 2D convolution with binary input, fixed point 16-bits output and - * binary weights - with +1/-1 padding (Larq like) - Lite I/F - * - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_conv2d_is1os16ws1_bn_pad1_fxp(const ai_u32 *pDataIn_init, - ai_i16 *pDataOut_init, - const ai_u32 *pWeights_init, - ai_float *pScratch_32, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_in, - const ai_i32 height_in, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_i32 filt_width, - const ai_i32 filt_height, - const ai_i32 filt_pad_x, - const ai_i32 filt_pad_y, - const ai_i32 filt_stride_x, - const ai_i32 filt_stride_y, - const ai_float *pScale_init, - const ai_float *pOffset_init, - const ai_i32 pad_value); - - -/*! - * @brief Handles 2D convolution with binary input, fixed point 16-bits output and - * binary weights - with +1/-1 padding (Larq like) - Lite I/F - * - Optimized thanks to Optim1 assumptions - * - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_conv2d_is1os16ws1_bn_pad1_optim1_fxp(const ai_u32 *pDataIn_init, - ai_i16 *pDataOut_init, - const ai_u32 *pWeights_init, - ai_float *pScratch_32, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_in, - const ai_i32 height_in, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_i32 filt_width, - const ai_i32 filt_height, - const ai_i32 filt_pad_x, - const ai_i32 filt_pad_y, - const ai_i32 filt_stride_x, - const ai_i32 filt_stride_y, - const ai_float *pScale_init, - const ai_float *pOffset_init, - const ai_i32 pad_value); - - -/** - * @brief Handles 2D convolution with binary input, fixed point 16-bits unsigned output and - * binary weights - with 0 padding (QKeras like) - Lite I/F - * - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_conv2d_is1ou16ws1_bn_pad1_fxp(const ai_u32 *pDataIn_init, - ai_u16 *pDataOut_init, - const ai_u32 *pWeights_init, - ai_float *pScratch_32, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_in, - const ai_i32 height_in, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_i32 filt_width, - const ai_i32 filt_height, - const ai_i32 filt_pad_x, - const ai_i32 filt_pad_y, - const ai_i32 filt_stride_x, - const ai_i32 filt_stride_y, - const ai_float *pScale_init, - const ai_float *pOffset_init, - const ai_i32 pad_value); - - -/*! - * @brief Handles 2D convolution with binary input, fixed point 16-bits unsigned output and - * binary weights - with +1/-1 padding (Larq like) - Lite I/F - * - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_conv2d_is1ou16ws1_bn_pad0_fxp(const ai_u32 *pDataIn_init, - ai_u16 *pDataOut_init, - const ai_u32 *pWeights_init, - ai_float *pScratch_32, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_in, - const ai_i32 height_in, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_i32 filt_width, - const ai_i32 filt_height, - const ai_i32 filt_pad_x, - const ai_i32 filt_pad_y, - const ai_i32 filt_stride_x, - const ai_i32 filt_stride_y, - const ai_float *pScale_init, - const ai_float *pOffset_init); - -/*! - * @brief Handles 2D convolution with binary input, fixed point 16-bits unsigned output and - * binary weights - with +1/-1 padding (Larq like) - Lite I/F. - * - Optimized thanks to Optim1 assumptions - * - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_conv2d_is1ou16ws1_bn_pad1_optim1_fxp(const ai_u32 *pDataIn_init, - ai_u16 *pDataOut_init, - const ai_u32 *pWeights_init, - ai_float *pScratch_32, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_in, - const ai_i32 height_in, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_i32 filt_width, - const ai_i32 filt_height, - const ai_i32 filt_pad_x, - const ai_i32 filt_pad_y, - const ai_i32 filt_stride_x, - const ai_i32 filt_stride_y, - const ai_float *pScale_init, - const ai_float *pOffset_init, - const ai_i32 pad_value); - -/*! - * @brief Handles 2D convolution with 8-bits quantized Input and weights and - * binary output - Lite I/F - * @ingroup lite_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -LITE_API_ENTRY -void forward_lite_conv2d_is8os1ws8(const ai_i8 *pDataIn_init, - ai_u32 *pDataOut_init, - const ai_i8 *pWeights_init, - ai_float *pScratch_32, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_in, - const ai_i32 height_in, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_i32 filt_width, - const ai_i32 filt_height, - const ai_i32 filt_pad_x, - const ai_i32 filt_pad_y, - const ai_i32 filt_stride_x, - const ai_i32 filt_stride_y, - const ai_i32 *pThreshold, - const ai_i8 in_zeropoint); - -/*! - * @brief Handles 2D convolution with 8-bits quantized Input and weights and - * binary output - Lite I/F - Optimized thanks to Optim2 assumptions - * @ingroup lite_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -LITE_API_ENTRY -void forward_lite_conv2d_is8os1ws8_optim2(const ai_i8 *pDataIn_init, - ai_u32 *pDataOut_init, - const ai_i8 *pWeights_init, - ai_float *pScratch_32, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_in, - const ai_i32 height_in, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_i32 filt_width, - const ai_i32 filt_height, - const ai_i32 filt_pad_x, - const ai_i32 filt_pad_y, - const ai_i32 filt_stride_x, - const ai_i32 filt_stride_y, - const ai_i32 *pThreshold, - const ai_i8 in_zeropoint); - -/*! - * @brief Handles 2D convolution with 8-bits quantized Input and weights and - * binary output - quantized with DoReFa SotA quantizer, lite I/F - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_conv2d_dorefa_is8os1ws8(const ai_i8 *pDataIn_init, - ai_u32 *pDataOut_init, - const ai_u8 *pWeights_init, - ai_float *pScratch_32, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_in, - const ai_i32 height_in, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_i32 filt_width, - const ai_i32 filt_height, - const ai_i32 filt_pad_x, - const ai_i32 filt_pad_y, - const ai_i32 filt_stride_x, - const ai_i32 filt_stride_y, - const ai_i32 *pThreshold, - const ai_i8 in_zeropoint); - - -/*! - * @brief Handles 2D convolution with 8-bits quantized input, output and weights - * - quantized with with different quantization for channel - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_conv2d_is8os8ws8_sssa_ch(const ai_i8 *pData_in, - ai_i8 *pData_out, - const ai_i8 *pWeights, - const ai_i32 *pBias, - ai_u16 *pBuffer_a, - const ai_size width_in, - const ai_size height_in, - const ai_size width_out, - const ai_size height_out, - const ai_u16 n_channel_in, - const ai_u16 n_channel_out, - const ai_size filt_width, - const ai_size filt_height, - const ai_u16 filt_pad_x, - const ai_u16 filt_pad_y, - const ai_u16 filt_stride_x, - const ai_u16 filt_stride_y, - const ai_u16 dilation_x, - const ai_u16 dilation_y, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - const ai_i8 in_zeropoint, - const ai_i8 out_zeropoint, - const ai_i32 scratch_size); - -/*! - * @brief Handles 2D convolution with 16-bits quantized inputs, binary outputs and binary weights - Lite I/F. - * Vanilla version. - * @ingroup lite_conv2d_dqnn - * @param layer conv2d_dqnn layer - */ -LITE_API_ENTRY -void forward_lite_conv2d_is16os1ws1_bn_fxp(const ai_i16 *pIn, - ai_u32 *pOut_32, - const ai_u32 *pWeights, - const ai_i32 *pThreshold, - ai_i8 *pBufferA, - const ai_i32 dim_kernel, - const ai_i16 dim_im_in_x, - const ai_i16 dim_im_in_y, - const ai_i16 dim_im_out_x, - const ai_i16 dim_im_out_y, - const ai_i16 ch_im_in, - const ai_i16 ch_im_out, - const ai_i16 dim_kernel_x, - const ai_i16 dim_kernel_y, - const ai_i16 padding_x, - const ai_i16 padding_y, - const ai_i16 stride_x, - const ai_i16 stride_y, - const ai_i16 dilation_x, - const ai_i16 dilation_y, - const ai_i16 in_zeropoint); - - -/** - * @brief Handles 2D convolution with 16-bits quantized inputs, 16-bits quantized outputs and binary weights - Lite I/F - * - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_conv2d_is16os16ws1_fxp(const ai_i16 *pIn, - ai_i16 *pOut, - const ai_u32 *pWeights, - ai_i8 *pBufferA, - const ai_i16 dim_im_in_x, - const ai_i16 dim_im_in_y, - const ai_i16 dim_im_out_x, - const ai_i16 dim_im_out_y, - const ai_i16 ch_im_in, - const ai_i16 ch_im_out, - const ai_u32 dim_kernel, - const ai_i16 dim_kernel_x, - const ai_i16 dim_kernel_y, - const ai_i16 padding_x, - const ai_i16 padding_y, - const ai_i16 stride_x, - const ai_i16 stride_y, - const ai_i16 dilation_x, - const ai_i16 dilation_y, - const ai_i16 in_zeropoint); - -AI_API_DECLARE_END - -#endif /*LITE_CONV2D_DQNN_H*/ +/** + ****************************************************************************** + * @file lite_conv2d_dqnn.h + * @author AIS + * @brief header file of AI platform lite dqnn conv kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_CONV2D_DQNN_H +#define LITE_CONV2D_DQNN_H + +#include "ai_lite_interface.h" + +# define AI_16_OVERFLOW_CHECK(val_) (val_ <= 32767) + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +AI_API_DECLARE_BEGIN + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1os1ws1_bn_pad0(const ai_u32 *pDataIn_init, + ai_u32 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_i32 *pThreshold); + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + * - Optimized thanks to Optim0 assumptions + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1os1ws1_bn_pad0_optim0(const ai_u32 *pDataIn_init, + ai_u32 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_i32 *pThreshold); + +/*! + * @brief Handles 2D convolution with binary input, 8-bits output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1os8ws1_bn_pad0(const ai_u32 *pDataIn_init, + ai_i8 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_float *pScale, + const ai_float *pOffset); + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1os1ws1_bn_pad1(const ai_u32 *pDataIn_init, + ai_u32 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_i32 *pThreshold, + const ai_i32 pad_value); + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * - Optimized thanks to Optim2 assumptions + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1os1ws1_bn_pad1_optim2(const ai_u32 *pDataIn_init, + ai_u32 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_i32 *pThreshold, + const ai_i32 pad_value); + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1os1ws1_bn(const ai_u32 *pDataIn_init, + ai_u32 * pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u16 n_channel_in, + const ai_u16 n_channel_out, + const ai_u16 width_in, + const ai_u16 height_in, + const ai_u16 width_out, + const ai_u16 height_out, + const ai_u16 filt_width, + const ai_u16 filt_height, + const ai_u16 filt_pad_x, + const ai_u16 filt_pad_y, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_i32 *pThreshold, + const ai_u8 flatten_output); + +/*! + * @brief Handles 2D convolution with binary input, 8-bits output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1os8ws1_bn_pad1(const ai_u32 *pDataIn_init, + ai_i8 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_float *pScale, + const ai_float *pOffset, + const ai_i32 pad_value); + +/*! + * @brief Handles 2D convolution with binary input, 8-bits output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * - Optimized thanks to Optim1 assumptions + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1os8ws1_bn_pad1_optim1(const ai_u32 *pDataIn_init, + ai_i8 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_float *pScale, + const ai_float *pOffset, + const ai_i32 pad_value); + +/** + * @brief Handles 2D convolution with binary input, fixed point 16-bits output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1os16ws1_bn_pad0_fxp(const ai_u32 *pDataIn_init, + ai_i16 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_float *pScale_init, + const ai_float *pOffset_init); + +/*! + * @brief Handles 2D convolution with binary input, fixed point 16-bits output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1os16ws1_bn_pad1_fxp(const ai_u32 *pDataIn_init, + ai_i16 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_float *pScale_init, + const ai_float *pOffset_init, + const ai_i32 pad_value); + + +/*! + * @brief Handles 2D convolution with binary input, fixed point 16-bits output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * - Optimized thanks to Optim1 assumptions + * + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1os16ws1_bn_pad1_optim1_fxp(const ai_u32 *pDataIn_init, + ai_i16 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_float *pScale_init, + const ai_float *pOffset_init, + const ai_i32 pad_value); + + +/** + * @brief Handles 2D convolution with binary input, fixed point 16-bits unsigned output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + * + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1ou16ws1_bn_pad1_fxp(const ai_u32 *pDataIn_init, + ai_u16 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_float *pScale_init, + const ai_float *pOffset_init, + const ai_i32 pad_value); + + +/*! + * @brief Handles 2D convolution with binary input, fixed point 16-bits unsigned output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1ou16ws1_bn_pad0_fxp(const ai_u32 *pDataIn_init, + ai_u16 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_float *pScale_init, + const ai_float *pOffset_init); + +/*! + * @brief Handles 2D convolution with binary input, fixed point 16-bits unsigned output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F. + * - Optimized thanks to Optim1 assumptions + * + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is1ou16ws1_bn_pad1_optim1_fxp(const ai_u32 *pDataIn_init, + ai_u16 *pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_float *pScale_init, + const ai_float *pOffset_init, + const ai_i32 pad_value); + +/*! + * @brief Handles 2D convolution with 8-bits quantized Input and weights and + * binary output - Lite I/F + * @ingroup lite_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +LITE_API_ENTRY +void forward_lite_conv2d_is8os1ws8(const ai_i8 *pDataIn_init, + ai_u32 *pDataOut_init, + const ai_i8 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_i32 *pThreshold, + const ai_i8 in_zeropoint); + +/*! + * @brief Handles 2D convolution with 8-bits quantized Input and weights and + * binary output - Lite I/F - Optimized thanks to Optim2 assumptions + * @ingroup lite_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +LITE_API_ENTRY +void forward_lite_conv2d_is8os1ws8_optim2(const ai_i8 *pDataIn_init, + ai_u32 *pDataOut_init, + const ai_i8 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_i32 *pThreshold, + const ai_i8 in_zeropoint); + +/*! + * @brief Handles 2D convolution with 8-bits quantized Input and weights and + * binary output - quantized with DoReFa SotA quantizer, lite I/F + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_dorefa_is8os1ws8(const ai_i8 *pDataIn_init, + ai_u32 *pDataOut_init, + const ai_u8 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_i32 *pThreshold, + const ai_i8 in_zeropoint); + + +/*! + * @brief Handles 2D convolution with 8-bits quantized input, output and weights + * - quantized with with different quantization for channel + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is8os8ws8_sssa_ch(const ai_i8 *pData_in, + ai_i8 *pData_out, + const ai_i8 *pWeights, + const ai_i32 *pBias, + ai_u16 *pBuffer_a, + const ai_size width_in, + const ai_size height_in, + const ai_size width_out, + const ai_size height_out, + const ai_u16 n_channel_in, + const ai_u16 n_channel_out, + const ai_size filt_width, + const ai_size filt_height, + const ai_u16 filt_pad_x, + const ai_u16 filt_pad_y, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_u16 dilation_x, + const ai_u16 dilation_y, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_i32 scratch_size); + +/*! + * @brief Handles 2D convolution with 16-bits quantized inputs, binary outputs and binary weights - Lite I/F. + * Vanilla version. + * @ingroup lite_conv2d_dqnn + * @param layer conv2d_dqnn layer + */ +LITE_API_ENTRY +void forward_lite_conv2d_is16os1ws1_bn_fxp(const ai_i16 *pIn, + ai_u32 *pOut_32, + const ai_u32 *pWeights, + const ai_i32 *pThreshold, + ai_i8 *pBufferA, + const ai_i32 dim_kernel, + const ai_i16 dim_im_in_x, + const ai_i16 dim_im_in_y, + const ai_i16 dim_im_out_x, + const ai_i16 dim_im_out_y, + const ai_i16 ch_im_in, + const ai_i16 ch_im_out, + const ai_i16 dim_kernel_x, + const ai_i16 dim_kernel_y, + const ai_i16 padding_x, + const ai_i16 padding_y, + const ai_i16 stride_x, + const ai_i16 stride_y, + const ai_i16 dilation_x, + const ai_i16 dilation_y, + const ai_i16 in_zeropoint); + + +/** + * @brief Handles 2D convolution with 16-bits quantized inputs, 16-bits quantized outputs and binary weights - Lite I/F + * + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_conv2d_is16os16ws1_fxp(const ai_i16 *pIn, + ai_i16 *pOut, + const ai_u32 *pWeights, + ai_i8 *pBufferA, + const ai_i16 dim_im_in_x, + const ai_i16 dim_im_in_y, + const ai_i16 dim_im_out_x, + const ai_i16 dim_im_out_y, + const ai_i16 ch_im_in, + const ai_i16 ch_im_out, + const ai_u32 dim_kernel, + const ai_i16 dim_kernel_x, + const ai_i16 dim_kernel_y, + const ai_i16 padding_x, + const ai_i16 padding_y, + const ai_i16 stride_x, + const ai_i16 stride_y, + const ai_i16 dilation_x, + const ai_i16 dilation_y, + const ai_i16 in_zeropoint); + +AI_API_DECLARE_END + +#endif /*LITE_CONV2D_DQNN_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_conv2d_sssa8_ch.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_conv2d_sssa8_ch.h similarity index 98% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_conv2d_sssa8_ch.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_conv2d_sssa8_ch.h index 47c469fe..3604bbbf 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_conv2d_sssa8_ch.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_conv2d_sssa8_ch.h @@ -1,253 +1,253 @@ -/** - ****************************************************************************** - * @file lite_conv2d_sssa8_ch.h - * @author AIS - * @brief ST header for signed simmetric signed antisimmetric 8 bits - * layers with channel quantization - ****************************************************************************** - * @attention - * - * Copyright (c) 2021-2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_CONV2D_SSSA8_CH_H -#define LITE_CONV2D_SSSA8_CH_H - -void -forward_lite_conv2d_rgb_sssa8_ch(const ai_i8 *pData_in, - const ai_u16 dim_im_in, - const ai_i8 *pWeights, - const ai_u16 n_channel_out, - const ai_u16 dim_kernel, - const ai_u16 padding, - const ai_u16 stride, - const ai_i32 *pBias, - const ai_i8 in_zeropoint, - const ai_i8 out_zeropoint, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - const ai_layer_format_type out_ch_format, - ai_i8 *pData_out, - const ai_u16 dim_im_out, - ai_i32 scratch_size, - ai_i16 *pBuffer_a); -void -forward_lite_conv2d_sssa8_ch(const ai_i8 *pData_in, - const ai_u16 dim_im_in_x, - const ai_u16 dim_im_in_y, - const ai_u16 n_channel_in, - const ai_i8 *pWeights, - const ai_u16 n_channel_out, - const ai_u16 dim_kernel_x, - const ai_u16 dim_kernel_y, - const ai_u16 stride_x, - const ai_u16 stride_y, - const ai_u16 padding_x, - const ai_u16 padding_y, - const ai_i32 *pBias, - const ai_i8 in_zeropoint, - const ai_i8 out_zeropoint, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - const ai_layer_format_type out_ch_format, - ai_i8 *pData_out, - const ai_u16 dim_im_out_x, - const ai_u16 dim_im_out_y, - const ai_u16 weights_prefetch_enabled, - ai_i32 scratch_size, - ai_i16 *pBuffer_a); -void -forward_lite_conv2d_dilated_sssa8_ch(const ai_i8 *pData_in, - const ai_u16 dim_im_in_x, - const ai_u16 dim_im_in_y, - const ai_u16 n_channel_in, - const ai_i8 *pWeights, - const ai_u16 n_channel_out, - const ai_u16 dim_kernel_x, - const ai_u16 dim_kernel_y, - const ai_u16 stride_x, - const ai_u16 stride_y, - const ai_u16 dilation_x, - const ai_u16 dilation_y, - const ai_i32 *pBias, - const ai_i8 in_zeropoint, - const ai_i8 out_zeropoint, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - const ai_layer_format_type out_ch_format, - ai_i8 *pData_out, - const ai_u16 dim_im_out_x, - const ai_u16 dim_im_out_y, - ai_u32 height_loop_cnt_0, - const ai_u16 weights_prefetch_enabled, - ai_i32 scratch_size, - ai_i16 *pBuffer_a); - -void forward_lite_conv2d_deep_sssa8_ch(const ai_i8 *pData_in, - const ai_u16 dim_im_in_x, - const ai_u16 dim_im_in_y, - const ai_u16 n_channel_in, - const ai_i8 *pWeights, - const ai_u16 n_channel_out, - const ai_u16 dim_kernel_x, - const ai_u16 dim_kernel_y, - const ai_u16 stride_x, - const ai_u16 stride_y, - const ai_i32 *pBias, - const ai_i8 in_zeropoint, - const ai_i8 out_zeropoint, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - const ai_layer_format_type out_ch_format, - ai_i8 *pData_out, - const ai_u16 dim_im_out_x, - const ai_u16 dim_im_out_y, - ai_u32 height_loop_cnt_0, - const ai_u16 weights_prefetch_enabled, - ai_i32 scratch_size, - ai_i16 *pBuffer_a); - -void forward_lite_conv2d_deep_3x3_sssa8_ch(const ai_i8 *pData_in, - const ai_u16 dim_im_in_x, - const ai_u16 dim_im_in_y, - const ai_u16 n_channel_in, - const ai_i8 *pWeights, - const ai_u16 n_channel_out, - const ai_i32 *pBias, - const ai_i8 in_zeropoint, - const ai_i8 out_zeropoint, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - const ai_layer_format_type out_ch_format, - ai_i8 *pData_out, - const ai_u16 dim_im_out_x, - const ai_u16 dim_im_out_y, - ai_u32 height_loop_cnt_0, - ai_i32 scratch_size, - ai_i16 *pBuffer_a); - -void -forward_lite_pw_sssa8_ch(const ai_i8 *pData_in, - const ai_u16 width_in, - const ai_u16 height_in, - const ai_u16 filt_stride_x, - const ai_u16 filt_stride_y, - const ai_u16 n_channel_in, - const ai_i8 *pWeights, - const ai_u16 n_channel_out, - const ai_i32 *pBias, - const ai_i8 in_zeropoint, - const ai_i8 out_zeropoint, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - const ai_layer_format_type out_ch_format, - ai_i8 *pData_out, - ai_u16 weights_prefetch_enabled, - ai_i32 scratch_size, - ai_i16 *pBuffer_a); -void -forward_lite_dw_dm_sssa8_ch(const ai_i8 *Im_in, - const ai_u16 dim_im_in_x, - const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_i8 *wt, - const ai_u16 ch_im_out, - const ai_u16 dim_kernel_x, - const ai_u16 dim_kernel_y, - const ai_u16 padding_x, - const ai_u16 padding_y, - const ai_u16 stride_x, - const ai_u16 stride_y, - const ai_i32 *bias, - const ai_i8 In_ZeroPoint, - const ai_i8 Out_ZeroPoint, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - ai_i8 *Im_out, - const ai_u16 dim_im_out_x, - const ai_u16 dim_im_out_y, - const ai_i32 nl_pool_fused, - const ai_u32 scratch_size, - ai_i16 *bufferA); - -void -forward_lite_dw_sssa8_ch(const ai_i8 *Im_in, - const ai_u16 dim_im_in_x, - const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_i8 *wt, - const ai_u16 dim_kernel_x, - const ai_u16 dim_kernel_y, - const ai_u16 padding_x, - const ai_u16 padding_y, - const ai_u16 stride_x, - const ai_u16 stride_y, - const ai_i32 *bias, - const ai_i8 In_ZeroPoint, - const ai_i8 Out_ZeroPoint, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - ai_i8 *Im_out, - const ai_u16 dim_im_out_x, - const ai_u16 dim_im_out_y, - const ai_i32 nl_pool_fused, - const ai_u32 scratch_size, - ai_i16 *bufferA); - -void -forward_lite_dw_3x3_sssa8_ch(const ai_i8 *Im_in, - const ai_u16 dim_im_in_x, - const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_i8 *wt, - const ai_u16 stride_x, - const ai_u16 stride_y, - const ai_i32 *bias, - const ai_i8 In_ZeroPoint, - const ai_i8 Out_ZeroPoint, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - ai_i8 *Im_out, - const ai_u16 dim_im_out_x, - const ai_u16 dim_im_out_y, - const ai_i32 nl_pool_fused, - const ai_u32 scratch_size, - ai_i16 *bufferA); - -void -forward_lite_dw_3x3_ch1st_sssa8_ch(const ai_i8 *Im_in, - const ai_u16 dim_im_in_x, - const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_i8 *wt, - const ai_u16 stride_x, - const ai_u16 stride_y, - const ai_i32 *bias, - const ai_i8 In_ZeroPoint, - const ai_i8 Out_ZeroPoint, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - ai_i8 *Im_out, - const ai_u16 dim_im_out_x, - const ai_u16 dim_im_out_y, - const ai_i32 nl_pool_fused, - const ai_u32 scratch_size, - ai_i16 *bufferA); - -#endif /* LITE_CONV2D_SSSA8_CH_H */ +/** + ****************************************************************************** + * @file lite_conv2d_sssa8_ch.h + * @author AIS + * @brief ST header for signed simmetric signed antisimmetric 8 bits + * layers with channel quantization + ****************************************************************************** + * @attention + * + * Copyright (c) 2021-2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_CONV2D_SSSA8_CH_H +#define LITE_CONV2D_SSSA8_CH_H + +void +forward_lite_conv2d_rgb_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_u16 dim_kernel, + const ai_u16 padding, + const ai_u16 stride, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); +void +forward_lite_conv2d_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_u16 padding_x, + const ai_u16 padding_y, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_u16 weights_prefetch_enabled, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); +void +forward_lite_conv2d_dilated_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_u16 dilation_x, + const ai_u16 dilation_y, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + ai_u32 height_loop_cnt_0, + const ai_u16 weights_prefetch_enabled, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +void forward_lite_conv2d_deep_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + ai_u32 height_loop_cnt_0, + const ai_u16 weights_prefetch_enabled, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +void forward_lite_conv2d_deep_3x3_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + ai_u32 height_loop_cnt_0, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +void +forward_lite_pw_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 width_in, + const ai_u16 height_in, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + ai_u16 weights_prefetch_enabled, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); +void +forward_lite_dw_dm_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 ch_im_out, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 padding_x, + const ai_u16 padding_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_i32 nl_pool_fused, + const ai_u32 scratch_size, + ai_i16 *bufferA); + +void +forward_lite_dw_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 padding_x, + const ai_u16 padding_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_i32 nl_pool_fused, + const ai_u32 scratch_size, + ai_i16 *bufferA); + +void +forward_lite_dw_3x3_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_i32 nl_pool_fused, + const ai_u32 scratch_size, + ai_i16 *bufferA); + +void +forward_lite_dw_3x3_ch1st_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_i32 nl_pool_fused, + const ai_u32 scratch_size, + ai_i16 *bufferA); + +#endif /* LITE_CONV2D_SSSA8_CH_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_convert_dqnn.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_convert_dqnn.h similarity index 95% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_convert_dqnn.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_convert_dqnn.h index b09caf1b..da22d813 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_convert_dqnn.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_convert_dqnn.h @@ -1,230 +1,230 @@ -/** - ****************************************************************************** - * @file lite_convert_dqnn.h - * @author AIS - * @brief header file of AI platform lite convert kernel datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_CONVERT_DQNN_H -#define LITE_CONVERT_DQNN_H - - -#include "ai_lite_interface.h" - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -LITE_API_ENTRY -void forward_lite_node_convert_is1os8( - const ai_pbits *p_in, - ai_i8 *p_out, - const ai_i32 n_channels, - const ai_i32 n_pixels, - const ai_i8 *n_values); - - -LITE_API_ENTRY -void forward_lite_node_convert_is1os16( - const ai_pbits *p_in, - ai_i16 *p_out, - const ai_i32 n_channels, - const ai_i32 n_pixels, - const ai_i16 *n_values); - - -LITE_API_ENTRY -void forward_lite_node_convert_is1of32( - const ai_pbits *p_in, - ai_float *p_out, - const ai_i32 n_channels, - const ai_i32 n_pixels, - const ai_float *n_values); - - -/*! - * @brief Handles data conversion from 8-bits signed input to signed binary - * outputs - Lite API version - * @ingroup lite_pw_dqnn - */ -LITE_API_ENTRY -void forward_lite_node_convert_is8os1( - const ai_i8 *p_in, - ai_pbits *p_out, - const ai_i32 n_channels, - const ai_i32 n_pixels, - const ai_i8 zp, - const ai_i8 pad); - - -LITE_API_ENTRY -void forward_lite_node_convert_is16os1( - const ai_i16 *p_in, - ai_pbits *p_out, - const ai_i32 n_channels, - const ai_i32 n_pixels, - const ai_i8 zp, - const ai_i8 pad); - - -LITE_API_ENTRY -void forward_lite_node_convert_if32os1( - const ai_float *p_in, - ai_pbits *p_out, - const ai_i32 n_channels, - const ai_i32 n_pixels, - const ai_i8 zp, - const ai_i8 pad); - - -LITE_API_ENTRY -void forward_lite_node_convert_integer_if32os8( - const ai_float *p_in, - ai_i8 *p_out, - const ai_u32 size, - const ai_float out_scale, - const ai_i8 out_zeropoint); - - -LITE_API_ENTRY -void forward_lite_node_convert_integer_if32ou8( - const ai_float *p_in, - ai_u8 *p_out, - const ai_u32 size, - const ai_float out_scale, - const ai_u8 out_zeropoint); - - -LITE_API_ENTRY -void forward_lite_node_convert_integer_is8of32( - const ai_i8 *p_in, - ai_float *p_out, - const ai_u32 size, - const ai_float in_scale, - const ai_i8 in_zeropoint); - - -LITE_API_ENTRY -void forward_lite_node_convert_integer_iu8of32( - const ai_u8 *p_in, - ai_float *p_out, - const ai_u32 size, - const ai_float in_scale, - const ai_u8 in_zeropoint); - - -LITE_API_ENTRY -void forward_lite_node_convert_if32os16( - const ai_float *p_in, - ai_i16 *p_out, - const ai_u32 size, - const ai_float out_scale, - const ai_i16 out_zeropoint); - - -LITE_API_ENTRY -void forward_lite_node_convert_if32ou16( - const ai_float *p_in, - ai_u16 *p_out, - const ai_u32 size, - const ai_float out_scale, - const ai_u16 out_zeropoint); - - -LITE_API_ENTRY -void forward_lite_node_convert_is16of32( - const ai_i16 *p_in, - ai_float *p_out, - const ai_u32 size, - const ai_float in_scale, - const ai_i16 in_zeropoint); - - -LITE_API_ENTRY -void forward_lite_node_convert_iu16of32( - const ai_u16 *p_in, - ai_float *p_out, - const ai_u32 size, - const ai_float in_scale, - const ai_u16 in_zeropoint); - -LITE_API_ENTRY -void forward_lite_node_convert_integer_is8os8( - const ai_i8 *p_in, - ai_i8 *p_out, - const ai_i32 n_elems, - const ai_float scale_ratio, - const ai_i16 in_zp, - const ai_i16 out_zp); - - -LITE_API_ENTRY -void forward_lite_node_convert_integer_iu8ou8( - const ai_u8 *p_in, - ai_u8 *p_out, - const ai_i32 n_elems, - const ai_float scale_ratio, - const ai_u8 in_zp, - const ai_u8 out_zp); - - -LITE_API_ENTRY -void forward_lite_node_convert_integer_iu8os8( - const ai_u8 *p_in, - ai_i8 *p_out, - const ai_i32 n_elems, - const ai_float scale_ratio, - const ai_u8 in_zp, - const ai_i8 out_zp); - - -LITE_API_ENTRY -void forward_lite_node_convert_integer_iu8os8_fast( - const ai_u8 *p_in, - ai_i8 *p_out, - const ai_i32 n_elems, - const ai_float scale_ratio, - const ai_u8 in_zp, - const ai_i8 out_zp); - - -LITE_API_ENTRY -void forward_lite_node_convert_integer_is8ou8( - const ai_i8 *p_in, - ai_u8 *p_out, - const ai_i32 n_elems, - const ai_float scale_ratio, - const ai_i8 in_zp, - const ai_u8 out_zp); - - -LITE_API_ENTRY -void forward_lite_node_convert_integer_is8ou8_fast( - const ai_i8 *p_in, - ai_u8 *p_out, - const ai_i32 n_elems, - const ai_float scale_ratio, - const ai_i8 in_zp, - const ai_u8 out_zp); - - -LITE_API_ENTRY -void forward_lite_node_convert_is16ou16( - const ai_i16 *p_in, - ai_u16 *p_out, - const ai_i32 n_elems, - const ai_float scale_ratio, - const ai_i16 in_zp, - const ai_u16 out_zp); - -#endif /*LITE_CONVERT_DQNN_H*/ +/** + ****************************************************************************** + * @file lite_convert_dqnn.h + * @author AIS + * @brief header file of AI platform lite convert kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_CONVERT_DQNN_H +#define LITE_CONVERT_DQNN_H + + +#include "ai_lite_interface.h" + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +LITE_API_ENTRY +void forward_lite_node_convert_is1os8( + const ai_pbits *p_in, + ai_i8 *p_out, + const ai_i32 n_channels, + const ai_i32 n_pixels, + const ai_i8 *n_values); + + +LITE_API_ENTRY +void forward_lite_node_convert_is1os16( + const ai_pbits *p_in, + ai_i16 *p_out, + const ai_i32 n_channels, + const ai_i32 n_pixels, + const ai_i16 *n_values); + + +LITE_API_ENTRY +void forward_lite_node_convert_is1of32( + const ai_pbits *p_in, + ai_float *p_out, + const ai_i32 n_channels, + const ai_i32 n_pixels, + const ai_float *n_values); + + +/*! + * @brief Handles data conversion from 8-bits signed input to signed binary + * outputs - Lite API version + * @ingroup lite_pw_dqnn + */ +LITE_API_ENTRY +void forward_lite_node_convert_is8os1( + const ai_i8 *p_in, + ai_pbits *p_out, + const ai_i32 n_channels, + const ai_i32 n_pixels, + const ai_i8 zp, + const ai_i8 pad); + + +LITE_API_ENTRY +void forward_lite_node_convert_is16os1( + const ai_i16 *p_in, + ai_pbits *p_out, + const ai_i32 n_channels, + const ai_i32 n_pixels, + const ai_i8 zp, + const ai_i8 pad); + + +LITE_API_ENTRY +void forward_lite_node_convert_if32os1( + const ai_float *p_in, + ai_pbits *p_out, + const ai_i32 n_channels, + const ai_i32 n_pixels, + const ai_i8 zp, + const ai_i8 pad); + + +LITE_API_ENTRY +void forward_lite_node_convert_integer_if32os8( + const ai_float *p_in, + ai_i8 *p_out, + const ai_u32 size, + const ai_float out_scale, + const ai_i8 out_zeropoint); + + +LITE_API_ENTRY +void forward_lite_node_convert_integer_if32ou8( + const ai_float *p_in, + ai_u8 *p_out, + const ai_u32 size, + const ai_float out_scale, + const ai_u8 out_zeropoint); + + +LITE_API_ENTRY +void forward_lite_node_convert_integer_is8of32( + const ai_i8 *p_in, + ai_float *p_out, + const ai_u32 size, + const ai_float in_scale, + const ai_i8 in_zeropoint); + + +LITE_API_ENTRY +void forward_lite_node_convert_integer_iu8of32( + const ai_u8 *p_in, + ai_float *p_out, + const ai_u32 size, + const ai_float in_scale, + const ai_u8 in_zeropoint); + + +LITE_API_ENTRY +void forward_lite_node_convert_if32os16( + const ai_float *p_in, + ai_i16 *p_out, + const ai_u32 size, + const ai_float out_scale, + const ai_i16 out_zeropoint); + + +LITE_API_ENTRY +void forward_lite_node_convert_if32ou16( + const ai_float *p_in, + ai_u16 *p_out, + const ai_u32 size, + const ai_float out_scale, + const ai_u16 out_zeropoint); + + +LITE_API_ENTRY +void forward_lite_node_convert_is16of32( + const ai_i16 *p_in, + ai_float *p_out, + const ai_u32 size, + const ai_float in_scale, + const ai_i16 in_zeropoint); + + +LITE_API_ENTRY +void forward_lite_node_convert_iu16of32( + const ai_u16 *p_in, + ai_float *p_out, + const ai_u32 size, + const ai_float in_scale, + const ai_u16 in_zeropoint); + +LITE_API_ENTRY +void forward_lite_node_convert_integer_is8os8( + const ai_i8 *p_in, + ai_i8 *p_out, + const ai_i32 n_elems, + const ai_float scale_ratio, + const ai_i16 in_zp, + const ai_i16 out_zp); + + +LITE_API_ENTRY +void forward_lite_node_convert_integer_iu8ou8( + const ai_u8 *p_in, + ai_u8 *p_out, + const ai_i32 n_elems, + const ai_float scale_ratio, + const ai_u8 in_zp, + const ai_u8 out_zp); + + +LITE_API_ENTRY +void forward_lite_node_convert_integer_iu8os8( + const ai_u8 *p_in, + ai_i8 *p_out, + const ai_i32 n_elems, + const ai_float scale_ratio, + const ai_u8 in_zp, + const ai_i8 out_zp); + + +LITE_API_ENTRY +void forward_lite_node_convert_integer_iu8os8_fast( + const ai_u8 *p_in, + ai_i8 *p_out, + const ai_i32 n_elems, + const ai_float scale_ratio, + const ai_u8 in_zp, + const ai_i8 out_zp); + + +LITE_API_ENTRY +void forward_lite_node_convert_integer_is8ou8( + const ai_i8 *p_in, + ai_u8 *p_out, + const ai_i32 n_elems, + const ai_float scale_ratio, + const ai_i8 in_zp, + const ai_u8 out_zp); + + +LITE_API_ENTRY +void forward_lite_node_convert_integer_is8ou8_fast( + const ai_i8 *p_in, + ai_u8 *p_out, + const ai_i32 n_elems, + const ai_float scale_ratio, + const ai_i8 in_zp, + const ai_u8 out_zp); + + +LITE_API_ENTRY +void forward_lite_node_convert_is16ou16( + const ai_i16 *p_in, + ai_u16 *p_out, + const ai_i32 n_elems, + const ai_float scale_ratio, + const ai_i16 in_zp, + const ai_u16 out_zp); + +#endif /*LITE_CONVERT_DQNN_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_if32.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_if32.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_if32.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_if32.h index c9b86ac1..b4437656 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_if32.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_if32.h @@ -1,118 +1,118 @@ -/** - ****************************************************************************** - * @file lite_dense_if32.h - * @author STMicroelectronics - * @brief Definitions of runtime-lite dense core kernels (with float f32 input) - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_DENSE_IF32_H -#define LITE_DENSE_IF32_H - -#include "ai_lite_interface.h" - -/*! - * @brief decompress the weights into a scratch buffer - - * @ingroup lite_dense_if32 - * @param out pointer to the scratch buffer data - * @param lut pointer to the compression dictionary - * @param lut_bits bits used for compression (only 4 or 8 supported) - * @param n_in if last dimension is not even, specify its size for padding - * @param n_out: number of elements to be decompressed - */ -LITE_API_ENTRY -const uint8_t* lite_decompress_ilutof32( - float* out, const uint8_t* data0, - const float* lut, const uint16_t lut_bits, - const ai_size n_in, const ai_size n_out); - - -/*! - * @brief C struct for a dense layer with signed float input, signed float output, and float weights. - * @ingroup lite_dense_if32 - * @param output The pointer to output buffer. - * @param input The pointer to input buffer. - * @param weights The pointer to weights. - * @param bias The pointer to bias (NULL if not available). - * @param n_channel_in The number of channels of the input. - * @param n_channel_out The number of channels of the output, i.e., the number of dense hidden neurons. - */ -typedef struct { - ai_float* output; - const ai_float* input; - const ai_float* weights; - const ai_float* bias; - const ai_size n_channel_in; - const ai_size n_channel_out; - const ai_size n_elements; -} forward_lite_dense_if32of32wf32_args; - - -/*! - * @brief Forward function for a dense layer with signed float input, - * signed float output, and float weights. - * @ingroup lite_dense_if32 - * @param args pointer to @ref forward_lite_dense_if32of32wf32_args structure - */ -LITE_API_ENTRY -void forward_lite_dense_if32of32wf32( - forward_lite_dense_if32of32wf32_args* args); - - -/*! - * @brief Forward function for a dense layer with signed float input, - * signed float output, and 4bit LUT compressed weights. - * @ingroup lite_dense_if32 - * @param output The pointer to output buffer. - * @param weights_lut The pointer to compressed weights LUT table (16 entries). - * @param input The pointer to input buffer. - * @param weights_indeces The pointer to compressed weights indeces table (packed 4bits buffer). - * @param scratch_lut The pointer to cache buffer where to prefetch weights_lut values. (optional) - * @param bias The pointer to bias (NULL if not available). - * @param n_channel_in The number of channels of the input. - * @param n_channel_out The number of channels of the output, i.e., the number of dense hidden neurons. - * @param n_elements The number of elements to process - */ -LITE_API_ENTRY -void forward_lite_dense_if32of32wf32_lut4( - ai_float* output, const ai_float* input, - const ai_u8* weights_indeces, const ai_float* weights_lut, ai_float* scratch_lut, - const ai_float* bias, - const ai_size n_channel_in, const ai_size n_channel_out, - const ai_size n_elements); - - -/*! - * @brief Forward function for a dense layer with signed float input, - * signed float output, and 8bit LUT compressed weights. - * @ingroup lite_dense_if32 - * @param output The pointer to output buffer. - * @param input The pointer to input buffer. - * @param weights_indeces The pointer to compressed weights indeces table (8bits buffer). - * @param weights_lut The pointer to compressed weights LUT table (256 entries). - * @param scratch_lut The pointer to cache buffer where to prefetch weights_lut values. (optional) - * @param bias The pointer to bias (NULL if not available). - * @param n_channel_in The number of channels of the input. - * @param n_channel_out The number of channels of the output, i.e., the number of dense hidden neurons. - * @param n_elements The number of elements to process - */ -LITE_API_ENTRY -void forward_lite_dense_if32of32wf32_lut8( - ai_float* output, const ai_float* input, - const ai_u8* weights_indeces, const ai_float* weights_lut, ai_float* scratch_lut, - const ai_float* bias, - const ai_size n_channel_in, const ai_size n_channel_out, - const ai_size n_elements); - - -#endif /* LITE_DENSE_IF32_H */ +/** + ****************************************************************************** + * @file lite_dense_if32.h + * @author STMicroelectronics + * @brief Definitions of runtime-lite dense core kernels (with float f32 input) + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_DENSE_IF32_H +#define LITE_DENSE_IF32_H + +#include "ai_lite_interface.h" + +/*! + * @brief decompress the weights into a scratch buffer + + * @ingroup lite_dense_if32 + * @param out pointer to the scratch buffer data + * @param lut pointer to the compression dictionary + * @param lut_bits bits used for compression (only 4 or 8 supported) + * @param n_in if last dimension is not even, specify its size for padding + * @param n_out: number of elements to be decompressed + */ +LITE_API_ENTRY +const uint8_t* lite_decompress_ilutof32( + float* out, const uint8_t* data0, + const float* lut, const uint16_t lut_bits, + const ai_size n_in, const ai_size n_out); + + +/*! + * @brief C struct for a dense layer with signed float input, signed float output, and float weights. + * @ingroup lite_dense_if32 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param bias The pointer to bias (NULL if not available). + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., the number of dense hidden neurons. + */ +typedef struct { + ai_float* output; + const ai_float* input; + const ai_float* weights; + const ai_float* bias; + const ai_size n_channel_in; + const ai_size n_channel_out; + const ai_size n_elements; +} forward_lite_dense_if32of32wf32_args; + + +/*! + * @brief Forward function for a dense layer with signed float input, + * signed float output, and float weights. + * @ingroup lite_dense_if32 + * @param args pointer to @ref forward_lite_dense_if32of32wf32_args structure + */ +LITE_API_ENTRY +void forward_lite_dense_if32of32wf32( + forward_lite_dense_if32of32wf32_args* args); + + +/*! + * @brief Forward function for a dense layer with signed float input, + * signed float output, and 4bit LUT compressed weights. + * @ingroup lite_dense_if32 + * @param output The pointer to output buffer. + * @param weights_lut The pointer to compressed weights LUT table (16 entries). + * @param input The pointer to input buffer. + * @param weights_indeces The pointer to compressed weights indeces table (packed 4bits buffer). + * @param scratch_lut The pointer to cache buffer where to prefetch weights_lut values. (optional) + * @param bias The pointer to bias (NULL if not available). + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., the number of dense hidden neurons. + * @param n_elements The number of elements to process + */ +LITE_API_ENTRY +void forward_lite_dense_if32of32wf32_lut4( + ai_float* output, const ai_float* input, + const ai_u8* weights_indeces, const ai_float* weights_lut, ai_float* scratch_lut, + const ai_float* bias, + const ai_size n_channel_in, const ai_size n_channel_out, + const ai_size n_elements); + + +/*! + * @brief Forward function for a dense layer with signed float input, + * signed float output, and 8bit LUT compressed weights. + * @ingroup lite_dense_if32 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights_indeces The pointer to compressed weights indeces table (8bits buffer). + * @param weights_lut The pointer to compressed weights LUT table (256 entries). + * @param scratch_lut The pointer to cache buffer where to prefetch weights_lut values. (optional) + * @param bias The pointer to bias (NULL if not available). + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., the number of dense hidden neurons. + * @param n_elements The number of elements to process + */ +LITE_API_ENTRY +void forward_lite_dense_if32of32wf32_lut8( + ai_float* output, const ai_float* input, + const ai_u8* weights_indeces, const ai_float* weights_lut, ai_float* scratch_lut, + const ai_float* bias, + const ai_size n_channel_in, const ai_size n_channel_out, + const ai_size n_elements); + + +#endif /* LITE_DENSE_IF32_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is1.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is1.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is1.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is1.h index b37ab225..afa27a5c 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is1.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is1.h @@ -1,71 +1,71 @@ -/** - ****************************************************************************** - * @file lite_dense_is1.h - * @author AIS - * @brief header file of AI platform lite argmin argmax funcions - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_DENSE_IS1_H -#define LITE_DENSE_IS1_H - - -#include "ai_lite_interface.h" - - -/*! - * @brief Forward function for a dense layer with signed binary input, - * signed float output, and float weights. - * @ingroup lite_dense_is1 - * @param output The pointer to output buffer. - * @param input The pointer to input buffer. - * @param weights The pointer to weights. - * @param bias The pointer to bias (NULL if not available). - * @param scratch The pointer to the scratch buffer (unused). - * @param n_channel_in The number of channels of the input. - * @param n_channel_ouy The number of channels of the output, i.e., - * the number of dense hidden neurons. - */ -LITE_API_ENTRY -void forward_lite_dense_is1of32wf32( - ai_float *output, const ai_pbits *input, const ai_float *weights, - const ai_float *bias, ai_float *scratch, - const ai_u32 n_channel_in, const ai_u32 n_channel_out -); - - -/*! - * @brief Forward function for a dense layer with signed binary input, - * signed float output, and float weights. - * The BN is fused, i.e., the layer requires weights, scale, and offset, where - * weights are those of the dense layer, scale is that of the BN, and the offset - * corresponds to dense bias * bn scale + bn offset. If the parameters do not - * agree with such convention, the behavior is undefined. - * @ingroup lite_dense_is1 - * @param output The pointer to output buffer. - * @param input The pointer to input buffer. - * @param weights The pointer to weights. - * @param scale The pointer to scale. - * @param offset The pointer to offset. - * @param scratch The pointer to the scratch buffer (unused). - * @param n_channel_in The number of channels of the input. - * @param n_channel_ouy The number of channels of the output, i.e., - * the number of dense hidden neurons. - */ -LITE_API_ENTRY -void forward_lite_dense_is1of32wf32_bn( - ai_float *output, const ai_pbits *input, const ai_float *weights, - const ai_float *scale, const ai_float *offset, ai_float *scratch, - const ai_u32 n_channel_in, const ai_u32 n_channel_out -); - -#endif /* LITE_DENSE_IS1_H */ +/** + ****************************************************************************** + * @file lite_dense_is1.h + * @author AIS + * @brief header file of AI platform lite argmin argmax funcions + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_DENSE_IS1_H +#define LITE_DENSE_IS1_H + + +#include "ai_lite_interface.h" + + +/*! + * @brief Forward function for a dense layer with signed binary input, + * signed float output, and float weights. + * @ingroup lite_dense_is1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param bias The pointer to bias (NULL if not available). + * @param scratch The pointer to the scratch buffer (unused). + * @param n_channel_in The number of channels of the input. + * @param n_channel_ouy The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_is1of32wf32( + ai_float *output, const ai_pbits *input, const ai_float *weights, + const ai_float *bias, ai_float *scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out +); + + +/*! + * @brief Forward function for a dense layer with signed binary input, + * signed float output, and float weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup lite_dense_is1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param scale The pointer to scale. + * @param offset The pointer to offset. + * @param scratch The pointer to the scratch buffer (unused). + * @param n_channel_in The number of channels of the input. + * @param n_channel_ouy The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_is1of32wf32_bn( + ai_float *output, const ai_pbits *input, const ai_float *weights, + const ai_float *scale, const ai_float *offset, ai_float *scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out +); + +#endif /* LITE_DENSE_IS1_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is1ws1.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is1ws1.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is1ws1.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is1ws1.h index 3fb756b2..8fcbe7b4 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is1ws1.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is1ws1.h @@ -1,170 +1,170 @@ -/** - ****************************************************************************** - * @file lite_dense_is1ws1.h - * @author AIS - * @brief header file of AI platform lite dense kernel datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_DENSE_IS1WS1_H -#define LITE_DENSE_IS1WS1_H - -#include "stai.h" -#include "ai_lite_interface.h" - -/*! - * @brief Forward function for a dense layer with signed binary input, - * signed binary output, and signed binary weights. - * @ingroup lite_dense_is1ws1 - * @param output The pointer to output buffer. - * @param input The pointer to input buffer. - * @param weights The pointer to weights. - * @param bias The pointer to bias (NULL if not available). - * @param scratch The pointer to the scratch buffer. - * @param n_channel_in The number of channels of the input. - * @param n_channel_ouy The number of channels of the output, i.e., - * the number of dense hidden neurons. - */ -LITE_API_ENTRY -void forward_lite_dense_is1os1ws1( - ai_pbits *output, const ai_pbits *input, const ai_pbits *weights, - const ai_pbits *bias, ai_i32 *scratch, - const ai_u32 n_channel_in, const ai_u32 n_channel_out -); - -/*! - * @brief Forward function for a dense layer with signed binary input, - * signed binary output, and signed binary weights. - * The BN is fused, i.e., the layer requires weights, scale, and offset, where - * weights are those of the dense layer, scale is that of the BN, and the offset - * corresponds to dense bias * bn scale + bn offset. If the parameters do not - * agree with such convention, the behavior is undefined. - * @ingroup lite_dense_is1ws1 - * @param output The pointer to output buffer. - * @param input The pointer to input buffer. - * @param weights The pointer to weights. - * @param scale The pointer to scale. - * @param offset The pointer to offset. - * @param scratch The pointer to the scratch buffer. - * @param n_channel_in The number of channels of the input. - * @param n_channel_ouy The number of channels of the output, i.e., - * the number of dense hidden neurons. - */ -LITE_API_ENTRY -void forward_lite_dense_is1os1ws1_bn( - ai_pbits *output, const ai_pbits *input, const ai_pbits *weights, - const ai_float *scale, const ai_float *offset, ai_i32 *scratch, - const ai_u32 n_channel_in, const ai_u32 n_channel_out -); - - -/*! - * @brief Forward function for a dense layer with signed binary input, - * signed binary output, and signed 16bit weights. - * @ingroup lite_dense_is1ws1 - * @param output The pointer to output buffer. - * @param input The pointer to input buffer. - * @param weights The pointer to weights. - * @param bias The pointer to bias (NULL if not available). - * @param scratch The pointer to the scratch buffer (signed 32bit). - * @param n_channel_in The number of channels of the input. - * @param n_channel_ouy The number of channels of the output, i.e., - * the number of dense hidden neurons. - */ -LITE_API_ENTRY -void forward_lite_dense_is1os16ws1( - ai_i16 *output, const ai_pbits *input, const ai_pbits *weights, - const ai_pbits *bias, ai_i32 *scratch, - const ai_u32 n_channel_in, const ai_u32 n_channel_out); - - -/*! - * @brief Forward function for a dense layer with signed binary input, - * signed binary output, and signed 16bit weights. - * The BN is fused, i.e., the layer requires weights, scale, and offset, where - * weights are those of the dense layer, scale is that of the BN, and the offset - * corresponds to dense bias * bn scale + bn offset. If the parameters do not - * agree with such convention, the behavior is undefined. - * @ingroup lite_dense_is1ws1 - * @param output The pointer to output buffer. - * @param input The pointer to input buffer. - * @param weights The pointer to weights. - * @param bias The pointer to bias (NULL if not available). - * @param scratch The pointer to the scratch buffer (signed 32bit). - * @param n_channel_in The number of channels of the input. - * @param n_channel_ouy The number of channels of the output, i.e., - * the number of dense hidden neurons. - */ -LITE_API_ENTRY -void forward_lite_dense_is1os16ws1_bn( - ai_i16 *output, const ai_pbits *input, const ai_pbits *weights, - const ai_float *scale, const ai_float *offset, ai_i32 *scratch, - const ai_u32 n_channel_in, const ai_u32 n_channel_out); - - -/*! - * @brief Forward function for a dense layer with signed binary input, - * signed float output, and signed binary weights. - * @ingroup lite_dense_is1ws1 - * @param output The pointer to output buffer. - * @param input The pointer to input buffer. - * @param weights The pointer to weights. - * @param bias The pointer to bias (NULL if not available). - * @param scratch The pointer to the scratch buffer (unused). - * @param n_channel_in The number of channels of the input. - * @param n_channel_ouy The number of channels of the output, i.e., - * the number of dense hidden neurons. - */ -LITE_API_ENTRY -void forward_lite_dense_is1of32ws1( - ai_float *output, const ai_pbits *input, const ai_pbits *weights, - const ai_pbits *bias, ai_i32 *scratch, - const ai_u32 n_channel_in, const ai_u32 n_channel_out -); - - -/*! - * @brief C struct for a dense layer with signed binary input, - * signed float output, and signed binary weights. - * The BN is fused, i.e., the layer requires weights, scale, and offset, where - * weights are those of the dense layer, scale is that of the BN, and the offset - * corresponds to dense bias * bn scale + bn offset. If the parameters do not - * agree with such convention, the behavior is undefined. - * @ingroup lite_dense_is1ws1 - * @param output The pointer to output buffer. - * @param input The pointer to input buffer. - * @param weights The pointer to weights. - * @param scale The pointer to scale. - * @param offset The pointer to offset. - * @param scratch The pointer to the scratch buffer (unused). - * @param n_channel_in The number of channels of the input. - * @param n_channel_out The number of channels of the output, i.e., - * the number of dense hidden neurons. - */ -typedef struct { - float* output; - const stai_pbits* input; - const stai_pbits* weights; - const float* scale; - const float* offset; - int32_t* scratch; - const uint32_t n_channel_in; - const uint32_t n_channel_out; -} forward_lite_dense_is1of32ws1_bn_args; - - -LITE_API_ENTRY -void forward_lite_dense_is1of32ws1_bn( - forward_lite_dense_is1of32ws1_bn_args* args); - - -#endif /*LITE_DENSE_IS1WS1_H*/ +/** + ****************************************************************************** + * @file lite_dense_is1ws1.h + * @author AIS + * @brief header file of AI platform lite dense kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_DENSE_IS1WS1_H +#define LITE_DENSE_IS1WS1_H + +#include "stai.h" +#include "ai_lite_interface.h" + +/*! + * @brief Forward function for a dense layer with signed binary input, + * signed binary output, and signed binary weights. + * @ingroup lite_dense_is1ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param bias The pointer to bias (NULL if not available). + * @param scratch The pointer to the scratch buffer. + * @param n_channel_in The number of channels of the input. + * @param n_channel_ouy The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_is1os1ws1( + ai_pbits *output, const ai_pbits *input, const ai_pbits *weights, + const ai_pbits *bias, ai_i32 *scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out +); + +/*! + * @brief Forward function for a dense layer with signed binary input, + * signed binary output, and signed binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup lite_dense_is1ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param scale The pointer to scale. + * @param offset The pointer to offset. + * @param scratch The pointer to the scratch buffer. + * @param n_channel_in The number of channels of the input. + * @param n_channel_ouy The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_is1os1ws1_bn( + ai_pbits *output, const ai_pbits *input, const ai_pbits *weights, + const ai_float *scale, const ai_float *offset, ai_i32 *scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out +); + + +/*! + * @brief Forward function for a dense layer with signed binary input, + * signed binary output, and signed 16bit weights. + * @ingroup lite_dense_is1ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param bias The pointer to bias (NULL if not available). + * @param scratch The pointer to the scratch buffer (signed 32bit). + * @param n_channel_in The number of channels of the input. + * @param n_channel_ouy The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_is1os16ws1( + ai_i16 *output, const ai_pbits *input, const ai_pbits *weights, + const ai_pbits *bias, ai_i32 *scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out); + + +/*! + * @brief Forward function for a dense layer with signed binary input, + * signed binary output, and signed 16bit weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup lite_dense_is1ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param bias The pointer to bias (NULL if not available). + * @param scratch The pointer to the scratch buffer (signed 32bit). + * @param n_channel_in The number of channels of the input. + * @param n_channel_ouy The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_is1os16ws1_bn( + ai_i16 *output, const ai_pbits *input, const ai_pbits *weights, + const ai_float *scale, const ai_float *offset, ai_i32 *scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out); + + +/*! + * @brief Forward function for a dense layer with signed binary input, + * signed float output, and signed binary weights. + * @ingroup lite_dense_is1ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param bias The pointer to bias (NULL if not available). + * @param scratch The pointer to the scratch buffer (unused). + * @param n_channel_in The number of channels of the input. + * @param n_channel_ouy The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_is1of32ws1( + ai_float *output, const ai_pbits *input, const ai_pbits *weights, + const ai_pbits *bias, ai_i32 *scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out +); + + +/*! + * @brief C struct for a dense layer with signed binary input, + * signed float output, and signed binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup lite_dense_is1ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param scale The pointer to scale. + * @param offset The pointer to offset. + * @param scratch The pointer to the scratch buffer (unused). + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +typedef struct { + float* output; + const stai_pbits* input; + const stai_pbits* weights; + const float* scale; + const float* offset; + int32_t* scratch; + const uint32_t n_channel_in; + const uint32_t n_channel_out; +} forward_lite_dense_is1of32ws1_bn_args; + + +LITE_API_ENTRY +void forward_lite_dense_is1of32ws1_bn( + forward_lite_dense_is1of32ws1_bn_args* args); + + +#endif /*LITE_DENSE_IS1WS1_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is8os1ws1.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is8os1ws1.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is8os1ws1.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is8os1ws1.h index 5375fa01..3c9cae19 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is8os1ws1.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is8os1ws1.h @@ -1,53 +1,53 @@ -/** - ****************************************************************************** - * @file lite_dense_is8os1ws1.h - * @author AIS - * @brief header file of AI platform lite dense kernel datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_DENSE_IS8OS1WS1_H -#define LITE_DENSE_IS8OS1WS1_H - - -#include "ai_lite_interface.h" - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Forward function for a dense layer with signed 8 bits input, - * binary weights and binary output. - * @ingroup lite_dense_is8os1ws1 - * @param out_ptr The pointer to output buffer. - *@param data_in_init_ptr The pointer to input buffer. - * @param weights_ptr The pointer to weights. - * @param scratch_ptr The pointer to scratch buffer. - * @param scratch_size The value of scratch tensor size. - * @param n_channel_out The number of channels of the output, i.e., - * the number of dense hidden neurons. - * @param n_channel_in The number of channels of the input. - * @param scale_ptr The pointer to scale buffer of BN. - * @param offset_ptr The pointer to offset buffer of BN. - */ -LITE_API_ENTRY -void forward_lite_dense_is8os1ws1_bn_fxp(ai_pbits *out_ptr, - const ai_i8 *data_in_init_ptr, - const ai_pbits *weights_ptr, - ai_i32 *scratch_ptr, - const ai_u32 scratch_size, - const ai_u32 n_channel_out, - const ai_u32 n_channel_in, - const ai_i32 *threshold_ptr); - -#endif /*LITE_DENSE_IS8OS1WS1_H*/ +/** + ****************************************************************************** + * @file lite_dense_is8os1ws1.h + * @author AIS + * @brief header file of AI platform lite dense kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_DENSE_IS8OS1WS1_H +#define LITE_DENSE_IS8OS1WS1_H + + +#include "ai_lite_interface.h" + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Forward function for a dense layer with signed 8 bits input, + * binary weights and binary output. + * @ingroup lite_dense_is8os1ws1 + * @param out_ptr The pointer to output buffer. + *@param data_in_init_ptr The pointer to input buffer. + * @param weights_ptr The pointer to weights. + * @param scratch_ptr The pointer to scratch buffer. + * @param scratch_size The value of scratch tensor size. + * @param n_channel_out The number of channels of the output, i.e., + * the number of dense hidden neurons. + * @param n_channel_in The number of channels of the input. + * @param scale_ptr The pointer to scale buffer of BN. + * @param offset_ptr The pointer to offset buffer of BN. + */ +LITE_API_ENTRY +void forward_lite_dense_is8os1ws1_bn_fxp(ai_pbits *out_ptr, + const ai_i8 *data_in_init_ptr, + const ai_pbits *weights_ptr, + ai_i32 *scratch_ptr, + const ai_u32 scratch_size, + const ai_u32 n_channel_out, + const ai_u32 n_channel_in, + const ai_i32 *threshold_ptr); + +#endif /*LITE_DENSE_IS8OS1WS1_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is8os8ws8.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is8os8ws8.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is8os8ws8.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is8os8ws8.h index 3a490e76..312622a9 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is8os8ws8.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_is8os8ws8.h @@ -1,71 +1,71 @@ -/** - ****************************************************************************** - * @file lite_dense_is8os8ws8.h - * @author AIS - * @brief header file of AI platform lite dense kernel datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_DENSE_IS8OS8WS8_H -#define LITE_DENSE_IS8OS8WS8_H - -#include "ai_lite_interface.h" - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Forward function for a dense layer with signed input, - * signed output and signed weights all at 8 bits. - * @ingroup lite_dense_is8os8ws8 - * @param input The pointer to input buffer. - * @param output The pointer to output buffer. - * @param weights The pointer to weights. - * @param bias The pointer to bias (NULL if not available). - * @param in_zeropoint The value of the zero point of the input. - * @param out_zeropoint TThe value of the zero point of the output. - * @param n_channel_in The number of channels of the input. - * @param n_channel_out The number of channels of the output, i.e., - * the number of dense hidden neurons. - * @param n_pixels Total number of pixels. - */ -LITE_API_ENTRY -void forward_lite_dense_is8os8ws8(ai_i8 * pDataOut, - const ai_i8 *pDataIn, - const ai_i8 *pWeights, - const ai_i32 *pBias, - const ai_i8 in_zeropoint, - const ai_i8 out_zeropoint, - const ai_u16 n_channel_in, - const ai_u16 n_channel_out, - const ai_size n_pixels, - const ai_float in_scale, - const ai_float out_scale, - const ai_float Wt_scale, - ai_i16 *pBuffer_a); - -void forward_lite_dense_is8os8ws8_ch(ai_i8 * pDataOut, - const ai_i8 *pDataIn, - const ai_i8 *pWeights, - const ai_i32 *pBias, - const ai_i8 in_zeropoint, - const ai_i8 out_zeropoint, - const ai_u16 n_channel_in, - const ai_u16 n_channel_out, - const ai_size n_pixels, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - ai_i16 *pBuffer_a); - -#endif /*LITE_DENSE_IS8OS8WS8_H*/ +/** + ****************************************************************************** + * @file lite_dense_is8os8ws8.h + * @author AIS + * @brief header file of AI platform lite dense kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_DENSE_IS8OS8WS8_H +#define LITE_DENSE_IS8OS8WS8_H + +#include "ai_lite_interface.h" + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Forward function for a dense layer with signed input, + * signed output and signed weights all at 8 bits. + * @ingroup lite_dense_is8os8ws8 + * @param input The pointer to input buffer. + * @param output The pointer to output buffer. + * @param weights The pointer to weights. + * @param bias The pointer to bias (NULL if not available). + * @param in_zeropoint The value of the zero point of the input. + * @param out_zeropoint TThe value of the zero point of the output. + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., + * the number of dense hidden neurons. + * @param n_pixels Total number of pixels. + */ +LITE_API_ENTRY +void forward_lite_dense_is8os8ws8(ai_i8 * pDataOut, + const ai_i8 *pDataIn, + const ai_i8 *pWeights, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_u16 n_channel_in, + const ai_u16 n_channel_out, + const ai_size n_pixels, + const ai_float in_scale, + const ai_float out_scale, + const ai_float Wt_scale, + ai_i16 *pBuffer_a); + +void forward_lite_dense_is8os8ws8_ch(ai_i8 * pDataOut, + const ai_i8 *pDataIn, + const ai_i8 *pWeights, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_u16 n_channel_in, + const ai_u16 n_channel_out, + const ai_size n_pixels, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i16 *pBuffer_a); + +#endif /*LITE_DENSE_IS8OS8WS8_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_ws1.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_ws1.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_ws1.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_ws1.h index 7d3b78a0..69cee29c 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_ws1.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dense_ws1.h @@ -1,171 +1,171 @@ -/** - ****************************************************************************** - * @file lite_dense_ws1.h - * @author AIS - * @brief header file of AI platform lite dense kernel datatypes (1bit weights) - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_DENSE_WS1_H -#define LITE_DENSE_WS1_H - - -#include "stai.h" -#include "ai_lite_interface.h" - - -/*! - * @brief Forward function for a dense layer with signed 16bit input, - * signed 16bit output, binary weights and binary bias. - * @ingroup lite_dense_ws1 - * @param output The pointer to output buffer. - * @param input The pointer to input buffer. - * @param weights The pointer to weights. - * @param bias The pointer to bias. - * @param scratch The pointer to the scratch buffer (unused). - * @param n_channel_in The number of channels of the input. - * @param n_channel_out The number of channels of the output, i.e., - * the number of dense hidden neurons. - */ -LITE_API_ENTRY -void forward_lite_dense_is16os16ws1( - ai_i16* output, const ai_i16* input, - const ai_pbits* weights, - const ai_pbits* bias, ai_i32* scratch, - const ai_u32 n_channel_in, const ai_u32 n_channel_out); - - -/*! - * @brief Forward function for a dense layer with signed 16bit input, - * signed 16bit output, binary weights and binary bias. - * The BN is fused, i.e., the layer requires weights, scale, and offset, where - * weights are those of the dense layer, scale is that of the BN, and the offset - * corresponds to dense bias * bn scale + bn offset. If the parameters do not - * agree with such convention, the behavior is undefined. - * @ingroup lite_dense_ws1 - * @param output The pointer to output buffer. - * @param input The pointer to input buffer. - * @param weights The pointer to weights. - * @param scale The pointer to scale. - * @param offset The pointer to offset. - * @param scratch The pointer to the scratch buffer (unused). - * @param n_channel_in The number of channels of the input. - * @param n_channel_out The number of channels of the output, i.e., - * the number of dense hidden neurons. - */ -LITE_API_ENTRY -void forward_lite_dense_is16os16ws1_bn( - ai_i16* output, const ai_i16* input, - const ai_pbits* weights, - const ai_float *scale, const ai_float *offset, ai_i32* scratch, - const ai_u32 n_channel_in, const ai_u32 n_channel_out); - - -/*! - * @brief Forward function for a dense layer with signed f32 input, - * f32 output, binary weights and binary bias. - * @ingroup lite_dense_ws1 - * @param output The pointer to output buffer. - * @param input The pointer to input buffer. - * @param weights The pointer to weights. - * @param bias The pointer to bias. - * @param scratch The pointer to the scratch buffer (unused). - * @param n_channel_in The number of channels of the input. - * @param n_channel_out The number of channels of the output, i.e., - * the number of dense hidden neurons. - */ -LITE_API_ENTRY -void forward_lite_dense_if32os1ws1( - ai_pbits *output, const ai_float *input, const ai_pbits *weights, - const ai_float *bias, ai_float *scratch, - const ai_u32 n_channel_in, const ai_u32 n_channel_out); - - -/*! - * @brief C struct for a dense layer with signed f32 input, - * f32 output, binary weights. - * The BN is fused, i.e., the layer requires weights, scale, and offset, where - * weights are those of the dense layer, scale is that of the BN, and the offset - * corresponds to dense bias * bn scale + bn offset. If the parameters do not - * agree with such convention, the behavior is undefined. - * @ingroup lite_dense_ws1 - * @param output The pointer to output buffer. - * @param input The pointer to input buffer. - * @param weights The pointer to weights. - * @param scale The pointer to scale. - * @param offset The pointer to offset. - * @param scratch The pointer to the scratch buffer (unused). - * @param n_channel_in The number of channels of the input. - * @param n_channel_out The number of channels of the output, i.e., - * the number of dense hidden neurons. - */ -typedef struct { - stai_pbits* output; - const float* input; - const stai_pbits* weights; - const float* scale; - const float* offset; - float* scratch; - const uint32_t n_channel_in; - const uint32_t n_channel_out; -} forward_lite_dense_if32os1ws1_bn_args; - - -LITE_API_ENTRY -void forward_lite_dense_if32os1ws1_bn(forward_lite_dense_if32os1ws1_bn_args* args); - - -/*! - * @brief Forward function for a dense layer with signed f32 input, - * f32 output, and binary weights. - * @ingroup lite_dense_ws1 - * @param output The pointer to output buffer. - * @param input The pointer to input buffer. - * @param weights The pointer to weights. - * @param bias The pointer to binary bias. - * @param scratch The pointer to the scratch buffer (unused). - * @param n_channel_in The number of channels of the input. - * @param n_channel_out The number of channels of the output, i.e., - * the number of dense hidden neurons. - */ -LITE_API_ENTRY -void forward_lite_dense_if32of32ws1( - ai_float* output, const ai_float* input, - const ai_pbits* weights, - const ai_pbits* bias, ai_float* scratch, - const ai_u32 n_channel_in, const ai_u32 n_channel_out); - -/*! - * @brief Forward function for a dense layer with signed f32 input, - * f32 output, and binary weights. - * The BN is fused, i.e., the layer requires weights, scale, and offset, where - * weights are those of the dense layer, scale is that of the BN, and the offset - * corresponds to dense bias * bn scale + bn offset. If the parameters do not - * agree with such convention, the behavior is undefined. - * @ingroup lite_dense_ws1 - * @param output The pointer to output buffer. - * @param input The pointer to input buffer. - * @param weights The pointer to weights. - * @param scale The pointer to scale. - * @param offset The pointer to offset. - * @param scratch The pointer to the scratch buffer (unused). - * @param n_channel_in The number of channels of the input. - * @param n_channel_out The number of channels of the output, i.e., - * the number of dense hidden neurons. - */ -LITE_API_ENTRY -void forward_lite_dense_if32of32ws1_bn( - ai_float *output, const ai_float *input, const ai_pbits *weights, - const ai_float *scale, const ai_float *offset, ai_float *scratch, - const ai_u32 n_channel_in, const ai_u32 n_channel_out); - -#endif /* LITE_DENSE_IS1WS1_H */ +/** + ****************************************************************************** + * @file lite_dense_ws1.h + * @author AIS + * @brief header file of AI platform lite dense kernel datatypes (1bit weights) + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_DENSE_WS1_H +#define LITE_DENSE_WS1_H + + +#include "stai.h" +#include "ai_lite_interface.h" + + +/*! + * @brief Forward function for a dense layer with signed 16bit input, + * signed 16bit output, binary weights and binary bias. + * @ingroup lite_dense_ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param bias The pointer to bias. + * @param scratch The pointer to the scratch buffer (unused). + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_is16os16ws1( + ai_i16* output, const ai_i16* input, + const ai_pbits* weights, + const ai_pbits* bias, ai_i32* scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out); + + +/*! + * @brief Forward function for a dense layer with signed 16bit input, + * signed 16bit output, binary weights and binary bias. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup lite_dense_ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param scale The pointer to scale. + * @param offset The pointer to offset. + * @param scratch The pointer to the scratch buffer (unused). + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_is16os16ws1_bn( + ai_i16* output, const ai_i16* input, + const ai_pbits* weights, + const ai_float *scale, const ai_float *offset, ai_i32* scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out); + + +/*! + * @brief Forward function for a dense layer with signed f32 input, + * f32 output, binary weights and binary bias. + * @ingroup lite_dense_ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param bias The pointer to bias. + * @param scratch The pointer to the scratch buffer (unused). + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_if32os1ws1( + ai_pbits *output, const ai_float *input, const ai_pbits *weights, + const ai_float *bias, ai_float *scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out); + + +/*! + * @brief C struct for a dense layer with signed f32 input, + * f32 output, binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup lite_dense_ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param scale The pointer to scale. + * @param offset The pointer to offset. + * @param scratch The pointer to the scratch buffer (unused). + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +typedef struct { + stai_pbits* output; + const float* input; + const stai_pbits* weights; + const float* scale; + const float* offset; + float* scratch; + const uint32_t n_channel_in; + const uint32_t n_channel_out; +} forward_lite_dense_if32os1ws1_bn_args; + + +LITE_API_ENTRY +void forward_lite_dense_if32os1ws1_bn(forward_lite_dense_if32os1ws1_bn_args* args); + + +/*! + * @brief Forward function for a dense layer with signed f32 input, + * f32 output, and binary weights. + * @ingroup lite_dense_ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param bias The pointer to binary bias. + * @param scratch The pointer to the scratch buffer (unused). + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_if32of32ws1( + ai_float* output, const ai_float* input, + const ai_pbits* weights, + const ai_pbits* bias, ai_float* scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out); + +/*! + * @brief Forward function for a dense layer with signed f32 input, + * f32 output, and binary weights. + * The BN is fused, i.e., the layer requires weights, scale, and offset, where + * weights are those of the dense layer, scale is that of the BN, and the offset + * corresponds to dense bias * bn scale + bn offset. If the parameters do not + * agree with such convention, the behavior is undefined. + * @ingroup lite_dense_ws1 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param weights The pointer to weights. + * @param scale The pointer to scale. + * @param offset The pointer to offset. + * @param scratch The pointer to the scratch buffer (unused). + * @param n_channel_in The number of channels of the input. + * @param n_channel_out The number of channels of the output, i.e., + * the number of dense hidden neurons. + */ +LITE_API_ENTRY +void forward_lite_dense_if32of32ws1_bn( + ai_float *output, const ai_float *input, const ai_pbits *weights, + const ai_float *scale, const ai_float *offset, ai_float *scratch, + const ai_u32 n_channel_in, const ai_u32 n_channel_out); + +#endif /* LITE_DENSE_IS1WS1_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dw.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dw.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dw.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dw.h index 2f46006c..fa4fb061 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dw.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dw.h @@ -1,145 +1,145 @@ -/** - ****************************************************************************** - * @file lite_dw.h - * @author AIS - * @brief header file of AI platform lite depthwise kernel datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_DW_H -#define LITE_DW_H - - -#include "ai_lite_interface.h" - - - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Handles dw convolutions generic case (supports depth multiplier >= 1) - * @ingroup lite_dw - */ -LITE_API_ENTRY -void -forward_lite_dw_dm_sssa8_ch(const ai_i8 *Im_in, - const ai_u16 dim_im_in_x, - const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_i8 *wt, - const ai_u16 ch_im_out, - const ai_u16 dim_kernel_x, - const ai_u16 dim_kernel_y, - const ai_u16 padding_x, - const ai_u16 padding_y, - const ai_u16 stride_x, - const ai_u16 stride_y, - const ai_i32 *bias, - const ai_i8 In_ZeroPoint, - const ai_i8 Out_ZeroPoint, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - ai_i8 *Im_out, - const ai_u16 dim_im_out_x, - const ai_u16 dim_im_out_y, - const ai_i32 nl_pool_fused, - const ai_u32 scratch_size, - ai_i16 *bufferA); - -/*! - * @brief Handles dw convolutions with depth multiplier = 1 only - * @ingroup lite_dw - */ -LITE_API_ENTRY -void -forward_lite_dw_sssa8_ch(const ai_i8 *Im_in, - const ai_u16 dim_im_in_x, - const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_i8 *wt, - const ai_u16 dim_kernel_x, - const ai_u16 dim_kernel_y, - const ai_u16 padding_x, - const ai_u16 padding_y, - const ai_u16 stride_x, - const ai_u16 stride_y, - const ai_i32 *bias, - const ai_i8 In_ZeroPoint, - const ai_i8 Out_ZeroPoint, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - ai_i8 *Im_out, - const ai_u16 dim_im_out_x, - const ai_u16 dim_im_out_y, - const ai_i32 nl_pool_fused, - const ai_u32 scratch_size, - ai_i16 *bufferA); - -/*! - * @brief Handles dw convolutions with depth multiplier = 1, valid padding - * and 3*3 kernel size - * @ingroup lite_dw - */ -LITE_API_ENTRY -void -forward_lite_dw_3x3_sssa8_ch(const ai_i8 *Im_in, - const ai_u16 dim_im_in_x, - const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_i8 *wt, - const ai_u16 stride_x, - const ai_u16 stride_y, - const ai_i32 *bias, - const ai_i8 In_ZeroPoint, - const ai_i8 Out_ZeroPoint, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - ai_i8 *Im_out, - const ai_u16 dim_im_out_x, - const ai_u16 dim_im_out_y, - const ai_i32 nl_pool_fused, - const ai_u32 scratch_size, - ai_i16 *bufferA); - -/*! - * @brief Handles dw convolutions with depth multiplier = 1, valid padding, - * 3*3 kernel size, stride_x = 1 and weights/input are channel first - * @ingroup lite_dw - */ -LITE_API_ENTRY -void -forward_lite_dw_3x3_ch1st_sssa8_ch(const ai_i8 *Im_in, - const ai_u16 dim_im_in_x, - const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_i8 *wt, - const ai_u16 stride_x, - const ai_u16 stride_y, - const ai_i32 *bias, - const ai_i8 In_ZeroPoint, - const ai_i8 Out_ZeroPoint, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - ai_i8 *Im_out, - const ai_u16 dim_im_out_x, - const ai_u16 dim_im_out_y, - const ai_i32 nl_pool_fused, - const ai_u32 scratch_size, - ai_i16 *bufferA); - -#endif /*LITE_DW_H*/ +/** + ****************************************************************************** + * @file lite_dw.h + * @author AIS + * @brief header file of AI platform lite depthwise kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_DW_H +#define LITE_DW_H + + +#include "ai_lite_interface.h" + + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles dw convolutions generic case (supports depth multiplier >= 1) + * @ingroup lite_dw + */ +LITE_API_ENTRY +void +forward_lite_dw_dm_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 ch_im_out, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 padding_x, + const ai_u16 padding_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_i32 nl_pool_fused, + const ai_u32 scratch_size, + ai_i16 *bufferA); + +/*! + * @brief Handles dw convolutions with depth multiplier = 1 only + * @ingroup lite_dw + */ +LITE_API_ENTRY +void +forward_lite_dw_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 padding_x, + const ai_u16 padding_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_i32 nl_pool_fused, + const ai_u32 scratch_size, + ai_i16 *bufferA); + +/*! + * @brief Handles dw convolutions with depth multiplier = 1, valid padding + * and 3*3 kernel size + * @ingroup lite_dw + */ +LITE_API_ENTRY +void +forward_lite_dw_3x3_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_i32 nl_pool_fused, + const ai_u32 scratch_size, + ai_i16 *bufferA); + +/*! + * @brief Handles dw convolutions with depth multiplier = 1, valid padding, + * 3*3 kernel size, stride_x = 1 and weights/input are channel first + * @ingroup lite_dw + */ +LITE_API_ENTRY +void +forward_lite_dw_3x3_ch1st_sssa8_ch(const ai_i8 *Im_in, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_i8 *wt, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_i32 *bias, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + ai_i8 *Im_out, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_i32 nl_pool_fused, + const ai_u32 scratch_size, + ai_i16 *bufferA); + +#endif /*LITE_DW_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dw_dqnn.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dw_dqnn.h similarity index 98% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dw_dqnn.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dw_dqnn.h index c6b8cff2..7bccd7ed 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_dw_dqnn.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_dw_dqnn.h @@ -1,131 +1,131 @@ -/** - ****************************************************************************** - * @file lite_dw_dqnn.h - * @author AIS - * @brief header file of AI platform lite integer depthwise kernel datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_DW_DQNN_H -#define LITE_DW_DQNN_H - - -#include "ai_lite_interface.h" - - - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Handles 2D DW convolution with binary input, binary output and - * binary weights - with 0 padding (QKeras like) - Lite I/F - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_dw_is1os1ws1_bn_pad0(const ai_u32 *pDataIn_init, - ai_u32 * pDataOut_init, - const ai_u32 *pWeights_init, - ai_float *pScratch_32, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_in, - const ai_i32 height_in, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_i32 filt_width, - const ai_i32 filt_height, - const ai_i32 filt_pad_x, - const ai_i32 filt_pad_y, - const ai_i32 filt_stride_x, - const ai_i32 filt_stride_y, - const ai_i32 *pThreshold); - -/*! - * @brief Handles 2D DW convolution with binary input, binary output and - * binary weights - with 0 padding (QKeras like) - Lite I/F - * - Optimized thanks to Optim3 assumptions - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_dw_is1os1ws1_bn_pad0_optim3(const ai_u32 *pDataIn_init, - ai_u32 * pDataOut_init, - const ai_u32 *pWeights_init, - ai_float *pScratch_32, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_in, - const ai_i32 height_in, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_i32 filt_width, - const ai_i32 filt_height, - const ai_i32 filt_pad_x, - const ai_i32 filt_pad_y, - const ai_i32 filt_stride_x, - const ai_i32 filt_stride_y, - const ai_i32 *pThreshold); - -/*! - * @brief Handles 2D convolution with binary input, binary output and - * binary weights - with +1/-1 padding (Larq like) - Lite I/F - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_dw_is1os1ws1_bn_pad1(const ai_u32 *pDataIn_init, - ai_u32 * pDataOut_init, - const ai_u32 *pWeights_init, - ai_float *pScratch_32, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_in, - const ai_i32 height_in, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_i32 filt_width, - const ai_i32 filt_height, - const ai_i32 filt_pad_x, - const ai_i32 filt_pad_y, - const ai_i32 filt_stride_x, - const ai_i32 filt_stride_y, - const ai_i32 *pThreshold, - const ai_i32 pad_value); - - /*! - * @brief Handles 2D convolution with binary input, binary output and - * binary weights - with +1/-1 padding (Larq like) - Lite I/F - * - Optimized thanks to Optim3 assumptions - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_dw_is1os1ws1_bn_pad1_optim3(const ai_u32 *pDataIn_init, - ai_u32 * pDataOut_init, - const ai_u32 *pWeights_init, - ai_float *pScratch_32, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_in, - const ai_i32 height_in, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_i32 filt_width, - const ai_i32 filt_height, - const ai_i32 filt_pad_x, - const ai_i32 filt_pad_y, - const ai_i32 filt_stride_x, - const ai_i32 filt_stride_y, - const ai_i32 *pThreshold, - const ai_i32 pad_value); - - -#endif /*LITE_DW_DQNN_H*/ +/** + ****************************************************************************** + * @file lite_dw_dqnn.h + * @author AIS + * @brief header file of AI platform lite integer depthwise kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_DW_DQNN_H +#define LITE_DW_DQNN_H + + +#include "ai_lite_interface.h" + + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles 2D DW convolution with binary input, binary output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_dw_is1os1ws1_bn_pad0(const ai_u32 *pDataIn_init, + ai_u32 * pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_i32 *pThreshold); + +/*! + * @brief Handles 2D DW convolution with binary input, binary output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + * - Optimized thanks to Optim3 assumptions + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_dw_is1os1ws1_bn_pad0_optim3(const ai_u32 *pDataIn_init, + ai_u32 * pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_i32 *pThreshold); + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_dw_is1os1ws1_bn_pad1(const ai_u32 *pDataIn_init, + ai_u32 * pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_i32 *pThreshold, + const ai_i32 pad_value); + + /*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with +1/-1 padding (Larq like) - Lite I/F + * - Optimized thanks to Optim3 assumptions + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_dw_is1os1ws1_bn_pad1_optim3(const ai_u32 *pDataIn_init, + ai_u32 * pDataOut_init, + const ai_u32 *pWeights_init, + ai_float *pScratch_32, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_in, + const ai_i32 height_in, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 filt_width, + const ai_i32 filt_height, + const ai_i32 filt_pad_x, + const ai_i32 filt_pad_y, + const ai_i32 filt_stride_x, + const ai_i32 filt_stride_y, + const ai_i32 *pThreshold, + const ai_i32 pad_value); + + +#endif /*LITE_DW_DQNN_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_generic_float.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_generic_float.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_generic_float.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_generic_float.h index ef0216ec..aff42afd 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_generic_float.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_generic_float.h @@ -1,124 +1,124 @@ -/** - ****************************************************************************** - * @file lite_conv2d_dqnn.h - * @author AIS - * @brief header file of AI platform lite conv kernel datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_GENERIC_FLOAT_H -#define LITE_GENERIC_FLOAT_H - -#include "ai_lite_interface.h" - -/*****************************************************************************/ -/* Generic Forward Functions Section */ -/*****************************************************************************/ - -/** Reduce Generic Kernels *************************************************/ -LITE_API_ENTRY -void forward_lite_func_reduce_l1_if32of32( - ai_float* out_ptr, const ai_float* in_ptr, - const ai_size out_size, const ai_size in_step, - const ai_size axis_size, const ai_size axis_step); - - -LITE_API_ENTRY -void forward_lite_func_reduce_l2_if32of32( - ai_float* out_ptr, const ai_float* in_ptr, - const ai_size out_size, const ai_size in_step, - const ai_size axis_size, const ai_size axis_step); - - -/** Split Generic Kernels **************************************************/ - -/*! - * @brief C struct for a generic split layer. - * @ingroup lite_generic - * @param outputs_ptr list of pointers for the outputs buffers. - * @param n_outputs_ptr the number of outputs - * @param n_outer_elems the number of elements to copy in a single split - * @param input_ptr the pointer to input buffer to split. - * @param splits_strides the pointer to array defining outputs split strides. - * @param splits_step the offset between split strides - */ -typedef struct { - stai_ptr* outputs_ptr; - const stai_size n_outputs_ptr; - const stai_size n_outer_elems; - const stai_ptr input_ptr; - const int32_t* splits_strides; - const stai_size splits_step; -} forward_lite_split_generic_args; - - -LITE_API_ENTRY -void forward_lite_split_generic( - forward_lite_split_generic_args* args); - - -/** TopK Generic Kernels ***************************************************/ -/*! - * @brief Handles 2D convolution with binary input, binary output and - * binary weights - with 0 padding (QKeras like) - Lite I/F - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_topK_axis_0_if32of32( - const ai_float *pDataIn_init, - ai_float *pDataOut_values_init, - ai_i32 *pDataOut_index_init, - const ai_size height_in, - const ai_size width_in, - const ai_size n_channel_in, - const ai_size k, ai_i16 largest, - void (*f)(const ai_float* inputs, ai_float* values, ai_i32* indices, ai_size k, ai_size n_elements, ai_i32 stride, ai_i16 largest) -); - - -/*! - * @brief Handles 2D convolution with binary input, binary output and - * binary weights - with 0 padding (QKeras like) - Lite I/F - * - Optimized thanks to Optim0 assumptions - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_topK_axis_1_if32of32( - const ai_float *pDataIn_init, - ai_float *pDataOut_values_init, - ai_i32 *pDataOut_index_init, - const ai_size height_in, - const ai_size width_in, - const ai_size n_channel_in, - const ai_size k, ai_i16 largest, - void (*f)(const ai_float* inputs, ai_float* values, ai_i32* indices, ai_size k, ai_size n_elements, ai_i32 stride, ai_i16 largest) -); - -/*! - * @brief Handles 2D convolution with binary input, 8-bits output and - * binary weights - with 0 padding (QKeras like) - Lite I/F - * @ingroup lite_conv2d_dqnn - */ -LITE_API_ENTRY -void forward_lite_topK_axis_2_if32of32( - const ai_float *pDataIn_init, - ai_float *pDataOut_values_init, - ai_i32 *pDataOut_index_init, - const ai_size height_in, - const ai_size width_in, - const ai_size n_channel_in, - const ai_size k, ai_i16 largest, - void (*f)(const ai_float* inputs, ai_float* values, ai_i32* indices, ai_size k, ai_size n_elements, ai_i32 stride, ai_i16 largest) -); - - -#endif /*LITE_GENERIC_FLOAT_H*/ +/** + ****************************************************************************** + * @file lite_conv2d_dqnn.h + * @author AIS + * @brief header file of AI platform lite conv kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_GENERIC_FLOAT_H +#define LITE_GENERIC_FLOAT_H + +#include "ai_lite_interface.h" + +/*****************************************************************************/ +/* Generic Forward Functions Section */ +/*****************************************************************************/ + +/** Reduce Generic Kernels *************************************************/ +LITE_API_ENTRY +void forward_lite_func_reduce_l1_if32of32( + ai_float* out_ptr, const ai_float* in_ptr, + const ai_size out_size, const ai_size in_step, + const ai_size axis_size, const ai_size axis_step); + + +LITE_API_ENTRY +void forward_lite_func_reduce_l2_if32of32( + ai_float* out_ptr, const ai_float* in_ptr, + const ai_size out_size, const ai_size in_step, + const ai_size axis_size, const ai_size axis_step); + + +/** Split Generic Kernels **************************************************/ + +/*! + * @brief C struct for a generic split layer. + * @ingroup lite_generic + * @param outputs_ptr list of pointers for the outputs buffers. + * @param n_outputs_ptr the number of outputs + * @param n_outer_elems the number of elements to copy in a single split + * @param input_ptr the pointer to input buffer to split. + * @param splits_strides the pointer to array defining outputs split strides. + * @param splits_step the offset between split strides + */ +typedef struct { + stai_ptr* outputs_ptr; + const stai_size n_outputs_ptr; + const stai_size n_outer_elems; + const stai_ptr input_ptr; + const int32_t* splits_strides; + const stai_size splits_step; +} forward_lite_split_generic_args; + + +LITE_API_ENTRY +void forward_lite_split_generic( + forward_lite_split_generic_args* args); + + +/** TopK Generic Kernels ***************************************************/ +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_topK_axis_0_if32of32( + const ai_float *pDataIn_init, + ai_float *pDataOut_values_init, + ai_i32 *pDataOut_index_init, + const ai_size height_in, + const ai_size width_in, + const ai_size n_channel_in, + const ai_size k, ai_i16 largest, + void (*f)(const ai_float* inputs, ai_float* values, ai_i32* indices, ai_size k, ai_size n_elements, ai_i32 stride, ai_i16 largest) +); + + +/*! + * @brief Handles 2D convolution with binary input, binary output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + * - Optimized thanks to Optim0 assumptions + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_topK_axis_1_if32of32( + const ai_float *pDataIn_init, + ai_float *pDataOut_values_init, + ai_i32 *pDataOut_index_init, + const ai_size height_in, + const ai_size width_in, + const ai_size n_channel_in, + const ai_size k, ai_i16 largest, + void (*f)(const ai_float* inputs, ai_float* values, ai_i32* indices, ai_size k, ai_size n_elements, ai_i32 stride, ai_i16 largest) +); + +/*! + * @brief Handles 2D convolution with binary input, 8-bits output and + * binary weights - with 0 padding (QKeras like) - Lite I/F + * @ingroup lite_conv2d_dqnn + */ +LITE_API_ENTRY +void forward_lite_topK_axis_2_if32of32( + const ai_float *pDataIn_init, + ai_float *pDataOut_values_init, + ai_i32 *pDataOut_index_init, + const ai_size height_in, + const ai_size width_in, + const ai_size n_channel_in, + const ai_size k, ai_i16 largest, + void (*f)(const ai_float* inputs, ai_float* values, ai_i32* indices, ai_size k, ai_size n_elements, ai_i32 stride, ai_i16 largest) +); + + +#endif /*LITE_GENERIC_FLOAT_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_gru_f32.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_gru_f32.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_gru_f32.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_gru_f32.h index e4de25b4..537568ba 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_gru_f32.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_gru_f32.h @@ -1,58 +1,58 @@ -/** - ****************************************************************************** - * @file lite_gru_f32.h - * @author AIS - * @brief header file of AI platform lite gru kernel datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_GRU_F32_H -#define LITE_GRU_F32_H - - -#include "ai_lite_interface.h" - -/*! - * @brief Forward function for a stateless GRU (gate recurrent unit) layer with - * signed float input, signed float output, and float parameters. - * @ingroup lite_gru_f32 - * @param output The pointer to output buffer. - * @param input The pointer to input buffer. - * @param gru_kernel The pointer to gru kernel param. - * @param gru_recurrent The pointer to gru recurrent param. - * @param gru_bias The pointer to bias. - * @param gru_scratch The pointer to GRU scratch. - * @param n_units The number of GRU cells (dimensionality of output space). - * @param n_timesteps The number of timesteps of the input sequence. - * @param n_features The number of features of the input sequence. - * @param activation_nl The activation function used to update memory state. - * @param recurrent_nl The activation function to use for the recurrent step. - * @param return_seq If True, returns the full output sequence, else only the last output. - * @param go_backwards If True, process the input sequence backwards. - * @param reverse_seq If True, reverse the input sequence - * @param reset_after Whether to apply reset gate after (True) or before (False) matmul. - * @param activation_param The parameters for activation_nl (can be NULL) - * @param recurrent_param The parameters for recurrent_nl (can be NULL) - * @param initial_hidden Initial state of hidden layer (can be NULL) - */ -LITE_API_ENTRY -void forward_lite_gru_if32of32wf32( - ai_float* output, const ai_float* input, const ai_float* gru_kernel, - const ai_float* gru_recurrent, const ai_float* gru_bias, ai_float* gru_scratch, - const ai_u32 n_units, const ai_size n_timesteps, const ai_size n_features, - ai_handle activation_nl, ai_handle recurrent_nl, ai_bool return_seq, - ai_bool go_backwards, ai_bool reverse_seq, ai_bool reset_after, - const ai_float* activation_param, const ai_float* recurrent_param, - const ai_float* initial_hidden); - - -#endif /* LITE_GRU_F32_H */ +/** + ****************************************************************************** + * @file lite_gru_f32.h + * @author AIS + * @brief header file of AI platform lite gru kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_GRU_F32_H +#define LITE_GRU_F32_H + + +#include "ai_lite_interface.h" + +/*! + * @brief Forward function for a stateless GRU (gate recurrent unit) layer with + * signed float input, signed float output, and float parameters. + * @ingroup lite_gru_f32 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param gru_kernel The pointer to gru kernel param. + * @param gru_recurrent The pointer to gru recurrent param. + * @param gru_bias The pointer to bias. + * @param gru_scratch The pointer to GRU scratch. + * @param n_units The number of GRU cells (dimensionality of output space). + * @param n_timesteps The number of timesteps of the input sequence. + * @param n_features The number of features of the input sequence. + * @param activation_nl The activation function used to update memory state. + * @param recurrent_nl The activation function to use for the recurrent step. + * @param return_seq If True, returns the full output sequence, else only the last output. + * @param go_backwards If True, process the input sequence backwards. + * @param reverse_seq If True, reverse the input sequence + * @param reset_after Whether to apply reset gate after (True) or before (False) matmul. + * @param activation_param The parameters for activation_nl (can be NULL) + * @param recurrent_param The parameters for recurrent_nl (can be NULL) + * @param initial_hidden Initial state of hidden layer (can be NULL) + */ +LITE_API_ENTRY +void forward_lite_gru_if32of32wf32( + ai_float* output, const ai_float* input, const ai_float* gru_kernel, + const ai_float* gru_recurrent, const ai_float* gru_bias, ai_float* gru_scratch, + const ai_u32 n_units, const ai_size n_timesteps, const ai_size n_features, + ai_handle activation_nl, ai_handle recurrent_nl, ai_bool return_seq, + ai_bool go_backwards, ai_bool reverse_seq, ai_bool reset_after, + const ai_float* activation_param, const ai_float* recurrent_param, + const ai_float* initial_hidden); + + +#endif /* LITE_GRU_F32_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_internal_apis.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_internal_apis.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_internal_apis.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_internal_apis.h index d7a83763..f4f86f8c 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_internal_apis.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_internal_apis.h @@ -1,82 +1,82 @@ -/** - ****************************************************************************** - * @file lite_internal_apis.h - * @author STMicroelectronics - * @brief - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -#ifndef LITE_INTERNAL_APIS -#define LITE_INTERNAL_APIS - -#include "ai_platform.h" -#include "ai_lite_interface.h" - -/* lite_nl_generic_float */ -#define LITE_NL_ENTRY(nl_id_, nl_name_, nl_op_, nl_op_args_) \ -/** \ - * @brief lite function for a templated non-linearity nl_op_. \ - * @ingroup lite_nl_generic_float \ - * @param out_ptr The pointer to output buffer. \ - * @param in_ptr The pointer to input buffer. \ - * @param in_size. The size of the input. \ - * @param params opaque handler to optional NL params (not used). \ - */ \ -LITE_API_ENTRY \ -void forward_lite_nl_ ## nl_name_ ## _if32of32( \ - ai_handle out_ptr, const ai_handle in_ptr, const ai_i32 in_size, const ai_handle params); - -#include "lite_nl_list.h" - -/** - * @brief lite function for a float softmax non-linearity where the softmax is applied per channel. - * @ingroup lite_nl_generic_float - * @param output The pointer to output buffer. - * @param input The pointer to input buffer. - * @param in_size. The size of the input. - * @param channel_size The nsize of each channel. - * @param in_channel_step - * @param out_channel_step - */ -LITE_API_ENTRY -void forward_lite_nl_softmax_if32of32( - ai_handle out_ptr, const ai_handle in_ptr, const ai_i32 in_size, const ai_size ch_size, - const ai_i32 in_ch_step, const ai_i32 out_ch_step); - - -/** - * @brief lite function for a float softmax zero channel non-linearity where the softmax is applied per channel. - * @ingroup lite_nl_generic_float - * @param output The pointer to output buffer. - * @param input The pointer to input buffer. - * @param in_size. The size of the input. - * @param channel_size The nsize of each channel. - * @param in_channel_step - * @param out_channel_step - */ -LITE_API_ENTRY -void forward_lite_nl_softmax_zero_channel_if32of32( - ai_handle out_ptr, const ai_handle in_ptr, const ai_i32 in_size, const ai_size ch_size, - const ai_i32 in_ch_step, const ai_i32 out_ch_step); - -/*! - * @typedef (*func_nl_lite) - * @ingroup layers_nl - * @brief Fuction pointer for generic non linear transform - * this function pointer abstracts a generic non linear layer. - * see @ref nl_func_tanh_array_f32 and similar as examples. - */ - typedef void (*func_nl_lite)(ai_handle out_ptr, const ai_handle in_ptr, - const ai_i32 in_size, const ai_handle params); - -#endif /* LITE_INTERNAL_APIS */ +/** + ****************************************************************************** + * @file lite_internal_apis.h + * @author STMicroelectronics + * @brief + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef LITE_INTERNAL_APIS +#define LITE_INTERNAL_APIS + +#include "ai_platform.h" +#include "ai_lite_interface.h" + +/* lite_nl_generic_float */ +#define LITE_NL_ENTRY(nl_id_, nl_name_, nl_op_, nl_op_args_) \ +/** \ + * @brief lite function for a templated non-linearity nl_op_. \ + * @ingroup lite_nl_generic_float \ + * @param out_ptr The pointer to output buffer. \ + * @param in_ptr The pointer to input buffer. \ + * @param in_size. The size of the input. \ + * @param params opaque handler to optional NL params (not used). \ + */ \ +LITE_API_ENTRY \ +void forward_lite_nl_ ## nl_name_ ## _if32of32( \ + ai_handle out_ptr, const ai_handle in_ptr, const ai_i32 in_size, const ai_handle params); + +#include "lite_nl_list.h" + +/** + * @brief lite function for a float softmax non-linearity where the softmax is applied per channel. + * @ingroup lite_nl_generic_float + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param in_size. The size of the input. + * @param channel_size The nsize of each channel. + * @param in_channel_step + * @param out_channel_step + */ +LITE_API_ENTRY +void forward_lite_nl_softmax_if32of32( + ai_handle out_ptr, const ai_handle in_ptr, const ai_i32 in_size, const ai_size ch_size, + const ai_i32 in_ch_step, const ai_i32 out_ch_step); + + +/** + * @brief lite function for a float softmax zero channel non-linearity where the softmax is applied per channel. + * @ingroup lite_nl_generic_float + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param in_size. The size of the input. + * @param channel_size The nsize of each channel. + * @param in_channel_step + * @param out_channel_step + */ +LITE_API_ENTRY +void forward_lite_nl_softmax_zero_channel_if32of32( + ai_handle out_ptr, const ai_handle in_ptr, const ai_i32 in_size, const ai_size ch_size, + const ai_i32 in_ch_step, const ai_i32 out_ch_step); + +/*! + * @typedef (*func_nl_lite) + * @ingroup layers_nl + * @brief Fuction pointer for generic non linear transform + * this function pointer abstracts a generic non linear layer. + * see @ref nl_func_tanh_array_f32 and similar as examples. + */ + typedef void (*func_nl_lite)(ai_handle out_ptr, const ai_handle in_ptr, + const ai_i32 in_size, const ai_handle params); + +#endif /* LITE_INTERNAL_APIS */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_lstm.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_lstm.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_lstm.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_lstm.h index 620c2521..d6632555 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_lstm.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_lstm.h @@ -1,93 +1,93 @@ -/** - ****************************************************************************** - * @file lite_lstm.h - * @author AIS - * @brief header file of AI platform lite lstm kernel - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_LSTM_H -#define LITE_LSTM_H - -#include "ai_lite_interface.h" -#include "ai_math_helpers.h" - -/* TODO CEN: TMP */ -#include "lite_internal_apis.h" - -enum { - AI_LITE_LSTM_INPUT = 0, - AI_LITE_LSTM_FORGET = 1, - AI_LITE_LSTM_CELL = 2, - AI_LITE_LSTM_OUTPUT = 3, - AI_LITE_LSTM_MAX -}; - -void forward_lite_lstm_if32of32wf32( AI_CONST ai_float* kernel, - AI_CONST ai_float* recurrent, - AI_CONST ai_float* bias, - func_nl_lite activation_nl, /**< activation nonlinearity (input to cell) */ - AI_CONST ai_float* activation_param, /**< activation NL parameters */ - func_nl_lite recurrent_nl, /**< recurrent nonlinearity (hidden to cell) */ - AI_CONST ai_float* recurrent_param, /**< activation NL parameters */ - ai_float* hidden, - AI_CONST ai_float* initial_hidden, - ai_float* out_hidden, - ai_u16 n_features, - ai_u16 n_cell, - AI_CONST ai_float* peepholes, - ai_handle state, - ai_float* cell, - AI_CONST ai_float* initial_cell, - func_nl_lite out_nl, - AI_CONST ai_float* out_param, - ai_float cell_clip, - ai_float* data_in, - ai_float** data_out, - ai_ptr_offset *out_offset, - ai_float* gates, - ai_i32 timesteps, - ai_i32 nb_t_out, - ai_bool go_backwards, - ai_bool reverse_seq, - ai_bool stateful, - ai_bool return_state); - - -void forward_lite_lstm_is8os8ws8( AI_CONST ai_i8* kernel[AI_LITE_LSTM_MAX], - AI_CONST ai_i8* recurrent[AI_LITE_LSTM_MAX], - AI_CONST ai_i32* bias[AI_LITE_LSTM_MAX], - AI_CONST ai_i8* initial_hidden, - ai_i8* out_hidden, - ai_u16 n_features, - ai_u16 n_cell, - AI_CONST ai_i16* initial_cell, - ai_i16* out_cell, - ai_i8* data_in, - const ai_i8 in_zeropoint, - const ai_float in_scale, - ai_i8* data_out, - const ai_i8 out_zeropoint, - const ai_float out_scale, - const ai_float kernel_scale[AI_LITE_LSTM_MAX], - const ai_float recurrent_scale[AI_LITE_LSTM_MAX], - ai_i32 timesteps, - ai_i32 nb_t_out, - ai_bool go_backwards, - ai_bool reverse_seq, - ai_bool stateful, - ai_bool return_state, - ai_i32 scratch_size, - ai_i8 *p_scratch_data); - -#endif /* LITE_LSTM_H */ - +/** + ****************************************************************************** + * @file lite_lstm.h + * @author AIS + * @brief header file of AI platform lite lstm kernel + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_LSTM_H +#define LITE_LSTM_H + +#include "ai_lite_interface.h" +#include "ai_math_helpers.h" + +/* TODO CEN: TMP */ +#include "lite_internal_apis.h" + +enum { + AI_LITE_LSTM_INPUT = 0, + AI_LITE_LSTM_FORGET = 1, + AI_LITE_LSTM_CELL = 2, + AI_LITE_LSTM_OUTPUT = 3, + AI_LITE_LSTM_MAX +}; + +void forward_lite_lstm_if32of32wf32( AI_CONST ai_float* kernel, + AI_CONST ai_float* recurrent, + AI_CONST ai_float* bias, + func_nl_lite activation_nl, /**< activation nonlinearity (input to cell) */ + AI_CONST ai_float* activation_param, /**< activation NL parameters */ + func_nl_lite recurrent_nl, /**< recurrent nonlinearity (hidden to cell) */ + AI_CONST ai_float* recurrent_param, /**< activation NL parameters */ + ai_float* hidden, + AI_CONST ai_float* initial_hidden, + ai_float* out_hidden, + ai_u16 n_features, + ai_u16 n_cell, + AI_CONST ai_float* peepholes, + ai_handle state, + ai_float* cell, + AI_CONST ai_float* initial_cell, + func_nl_lite out_nl, + AI_CONST ai_float* out_param, + ai_float cell_clip, + ai_float* data_in, + ai_float** data_out, + ai_ptr_offset *out_offset, + ai_float* gates, + ai_i32 timesteps, + ai_i32 nb_t_out, + ai_bool go_backwards, + ai_bool reverse_seq, + ai_bool stateful, + ai_bool return_state); + + +void forward_lite_lstm_is8os8ws8( AI_CONST ai_i8* kernel[AI_LITE_LSTM_MAX], + AI_CONST ai_i8* recurrent[AI_LITE_LSTM_MAX], + AI_CONST ai_i32* bias[AI_LITE_LSTM_MAX], + AI_CONST ai_i8* initial_hidden, + ai_i8* out_hidden, + ai_u16 n_features, + ai_u16 n_cell, + AI_CONST ai_i16* initial_cell, + ai_i16* out_cell, + ai_i8* data_in, + const ai_i8 in_zeropoint, + const ai_float in_scale, + ai_i8* data_out, + const ai_i8 out_zeropoint, + const ai_float out_scale, + const ai_float kernel_scale[AI_LITE_LSTM_MAX], + const ai_float recurrent_scale[AI_LITE_LSTM_MAX], + ai_i32 timesteps, + ai_i32 nb_t_out, + ai_bool go_backwards, + ai_bool reverse_seq, + ai_bool stateful, + ai_bool return_state, + ai_i32 scratch_size, + ai_i8 *p_scratch_data); + +#endif /* LITE_LSTM_H */ + diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_maxpool_dqnn.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_maxpool_dqnn.h similarity index 98% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_maxpool_dqnn.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_maxpool_dqnn.h index 77b829af..349d2e5b 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_maxpool_dqnn.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_maxpool_dqnn.h @@ -1,157 +1,157 @@ -/** - ****************************************************************************** - * @file lite_maxpool_dqnn.h - * @author AIS - * @brief header file of AI platform lite dqnn maxpool kernel datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_MAXPOOL_DQNN_H -#define LITE_MAXPOOL_DQNN_H - - -#include "ai_lite_interface.h" - - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Handles maxpool with binary input and binary output - Lite I/F - * @ingroup lite_maxpool_dqnn - */ -LITE_API_ENTRY -void forward_lite_maxpool_is1os1(const ai_u32 *pDataIn_init, - ai_u32 *pDataOut_init, - const ai_i32 width_in, - const ai_i32 width_out, - const ai_i32 height_in, - const ai_i32 height_out, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 pool_width, - const ai_i32 pool_height, - const ai_i32 pool_pad_x, - const ai_i32 pool_pad_y, - const ai_i32 pool_stride_x, - const ai_i32 pool_stride_y, - const ai_u32 pool_pad_value, - ai_float *pScratch_32); - - -/*! - * @brief Handles maxpool with 8 bits signed input and output with a positive scale of the input- Lite I/F - * @ingroup lite_maxpool_dqnn - */ -LITE_API_ENTRY -void forward_lite_maxpool_is8os8_scalepos(const ai_i8 *pDataIn, - ai_i8 *pDataOut, - const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, - const ai_u16 padding_x, const ai_u16 padding_y, - const ai_u16 stride_x, const ai_u16 stride_y, - const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, - const ai_float InOut_ScaleRatio, - const ai_i8 In_ZeroPoint, - const ai_i8 Out_ZeroPoint); - - -/*! - * @brief Handles maxpool with 8 bits signed input and output with a negative scale of the input- Lite I/F - * @ingroup lite_maxpool_dqnn - */ -LITE_API_ENTRY -void forward_lite_maxpool_is8os8_scaleneg(const ai_i8 *pDataIn, - ai_i8 *pDataOut, - const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, - const ai_u16 padding_x, const ai_u16 padding_y, - const ai_u16 stride_x, const ai_u16 stride_y, - const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, - const ai_float InOut_ScaleRatio, - const ai_i8 In_ZeroPoint, - const ai_i8 Out_ZeroPoint); - - -/*! - * @brief Handles maxpool with 8 bits unsigned input and output with a positive scale of the input- Lite I/F - * @ingroup lite_maxpool_dqnn - */ -LITE_API_ENTRY -void forward_lite_maxpool_iu8ou8_scalepos(const ai_u8 *pDataIn, - ai_u8 *pDataOut, - const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, - const ai_u16 padding_x, const ai_u16 padding_y, - const ai_u16 stride_x, const ai_u16 stride_y, - const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, - const ai_float InOut_ScaleRatio, - const ai_u8 In_ZeroPoint, - const ai_u8 Out_ZeroPoint); - - -/*! - * @brief Handles maxpool with 8 bits unsigned input and output with a negative scale of the input- Lite I/F - * @ingroup lite_maxpool_dqnn - */ -LITE_API_ENTRY -void forward_lite_maxpool_iu8ou8_scaleneg(const ai_u8 *pDataIn, - ai_u8 *pDataOut, - const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, - const ai_u16 padding_x, const ai_u16 padding_y, - const ai_u16 stride_x, const ai_u16 stride_y, - const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, - const ai_float InOut_ScaleRatio, - const ai_u8 In_ZeroPoint, - const ai_u8 Out_ZeroPoint); - -/*! - * @brief Handles maxpool with 16 bits signed input and output with a positive scale of the input- Lite I/F - * @ingroup lite_maxpool_dqnn - */ -LITE_API_ENTRY -void forward_lite_maxpool_is16os16_scalepos(const ai_i16 *pApInput, - ai_i16 *pApOutput, - const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, - const ai_u16 padding_x, const ai_u16 padding_y, - const ai_u16 stride_x, const ai_u16 stride_y, - const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, - const ai_float InOut_ScaleRatio, - const ai_i16 In_ZeroPoint, - const ai_i16 Out_ZeroPoint); - -/*! - * @brief Handles maxpool with 16 bits unsigned input and output with a positive scale of the input- Lite I/F - * @ingroup lite_maxpool_dqnn - */ -LITE_API_ENTRY -void forward_lite_maxpool_iu16ou16_scalepos(const ai_u16 *pApInput, - ai_u16 *pApOutput, - const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, - const ai_u16 padding_x, const ai_u16 padding_y, - const ai_u16 stride_x, const ai_u16 stride_y, - const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, - const ai_float InOut_ScaleRatio, - const ai_u16 In_ZeroPoint, - const ai_u16 Out_ZeroPoint); - -#endif /*LITE_MAXPOOL_DQNN_H*/ +/** + ****************************************************************************** + * @file lite_maxpool_dqnn.h + * @author AIS + * @brief header file of AI platform lite dqnn maxpool kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_MAXPOOL_DQNN_H +#define LITE_MAXPOOL_DQNN_H + + +#include "ai_lite_interface.h" + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles maxpool with binary input and binary output - Lite I/F + * @ingroup lite_maxpool_dqnn + */ +LITE_API_ENTRY +void forward_lite_maxpool_is1os1(const ai_u32 *pDataIn_init, + ai_u32 *pDataOut_init, + const ai_i32 width_in, + const ai_i32 width_out, + const ai_i32 height_in, + const ai_i32 height_out, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 pool_width, + const ai_i32 pool_height, + const ai_i32 pool_pad_x, + const ai_i32 pool_pad_y, + const ai_i32 pool_stride_x, + const ai_i32 pool_stride_y, + const ai_u32 pool_pad_value, + ai_float *pScratch_32); + + +/*! + * @brief Handles maxpool with 8 bits signed input and output with a positive scale of the input- Lite I/F + * @ingroup lite_maxpool_dqnn + */ +LITE_API_ENTRY +void forward_lite_maxpool_is8os8_scalepos(const ai_i8 *pDataIn, + ai_i8 *pDataOut, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + const ai_float InOut_ScaleRatio, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint); + + +/*! + * @brief Handles maxpool with 8 bits signed input and output with a negative scale of the input- Lite I/F + * @ingroup lite_maxpool_dqnn + */ +LITE_API_ENTRY +void forward_lite_maxpool_is8os8_scaleneg(const ai_i8 *pDataIn, + ai_i8 *pDataOut, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + const ai_float InOut_ScaleRatio, + const ai_i8 In_ZeroPoint, + const ai_i8 Out_ZeroPoint); + + +/*! + * @brief Handles maxpool with 8 bits unsigned input and output with a positive scale of the input- Lite I/F + * @ingroup lite_maxpool_dqnn + */ +LITE_API_ENTRY +void forward_lite_maxpool_iu8ou8_scalepos(const ai_u8 *pDataIn, + ai_u8 *pDataOut, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + const ai_float InOut_ScaleRatio, + const ai_u8 In_ZeroPoint, + const ai_u8 Out_ZeroPoint); + + +/*! + * @brief Handles maxpool with 8 bits unsigned input and output with a negative scale of the input- Lite I/F + * @ingroup lite_maxpool_dqnn + */ +LITE_API_ENTRY +void forward_lite_maxpool_iu8ou8_scaleneg(const ai_u8 *pDataIn, + ai_u8 *pDataOut, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + const ai_float InOut_ScaleRatio, + const ai_u8 In_ZeroPoint, + const ai_u8 Out_ZeroPoint); + +/*! + * @brief Handles maxpool with 16 bits signed input and output with a positive scale of the input- Lite I/F + * @ingroup lite_maxpool_dqnn + */ +LITE_API_ENTRY +void forward_lite_maxpool_is16os16_scalepos(const ai_i16 *pApInput, + ai_i16 *pApOutput, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + const ai_float InOut_ScaleRatio, + const ai_i16 In_ZeroPoint, + const ai_i16 Out_ZeroPoint); + +/*! + * @brief Handles maxpool with 16 bits unsigned input and output with a positive scale of the input- Lite I/F + * @ingroup lite_maxpool_dqnn + */ +LITE_API_ENTRY +void forward_lite_maxpool_iu16ou16_scalepos(const ai_u16 *pApInput, + ai_u16 *pApOutput, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + const ai_float InOut_ScaleRatio, + const ai_u16 In_ZeroPoint, + const ai_u16 Out_ZeroPoint); + +#endif /*LITE_MAXPOOL_DQNN_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_nl_generic_integer.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_nl_generic_integer.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_nl_generic_integer.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_nl_generic_integer.h index 79a132a8..31148df4 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_nl_generic_integer.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_nl_generic_integer.h @@ -1,67 +1,67 @@ -/** - ****************************************************************************** - * @file lite_nl_generic_integer.h - * @author AIS - * @brief header file of AI platform lite integer non linearities - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_NL_GENERIC_INTEGER_H -#define LITE_NL_GENERIC_INTEGER_H - - -#include "ai_lite_interface.h" - -/** - * @brief forward lite function for a s8 softmax non-linearity where the softmax is applied per channel. - * @ingroup lite_nl_generic_integer - * @param output The pointer to output buffer (s8). - * @param input The pointer to input buffer (s8). - * @param in_size. The size of the input (including channels). - * @param ch_size The nsize of each channel. - * @param in_ch_step The step between consecutive elements (inputs) - * @param out_ch_step The step between consecutive elements (outputs) - * @param mult - * @param shift - * @param min_diff - */ -LITE_API_ENTRY -void forward_lite_nl_softmax_is8os8( - ai_i8* out_ptr, const ai_i8* in_ptr, - const ai_size in_size, const ai_size ch_size, - const ai_i32 in_ch_step, const ai_i32 out_ch_step, - const ai_i32 mult, const ai_i32 shift, const ai_i32 min_diff, - ai_i32* scratch); - - -/** - * @brief forward lite function for a u8 softmax non-linearity where the softmax is applied per channel. - * @ingroup lite_nl_generic_integer - * @param output The pointer to output buffer (s8). - * @param input The pointer to input buffer (s8). - * @param in_size. The size of the input (including channels). - * @param ch_size The nsize of each channel. - * @param in_ch_step The step between consecutive elements (inputs) - * @param out_ch_step The step between consecutive elements (outputs) - * @param mult - * @param shift - * @param min_diff - */ -LITE_API_ENTRY -void forward_lite_nl_softmax_iu8ou8( - ai_u8* out_ptr, const ai_u8* in_ptr, - const ai_size in_size, const ai_size ch_size, - const ai_i32 in_ch_step, const ai_i32 out_ch_step, - const ai_i32 mult, const ai_i32 shift, const ai_i32 min_diff, - ai_i32* scratch); - -#endif /* LITE_NL_GENERIC_INTEGER_H */ +/** + ****************************************************************************** + * @file lite_nl_generic_integer.h + * @author AIS + * @brief header file of AI platform lite integer non linearities + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_NL_GENERIC_INTEGER_H +#define LITE_NL_GENERIC_INTEGER_H + + +#include "ai_lite_interface.h" + +/** + * @brief forward lite function for a s8 softmax non-linearity where the softmax is applied per channel. + * @ingroup lite_nl_generic_integer + * @param output The pointer to output buffer (s8). + * @param input The pointer to input buffer (s8). + * @param in_size. The size of the input (including channels). + * @param ch_size The nsize of each channel. + * @param in_ch_step The step between consecutive elements (inputs) + * @param out_ch_step The step between consecutive elements (outputs) + * @param mult + * @param shift + * @param min_diff + */ +LITE_API_ENTRY +void forward_lite_nl_softmax_is8os8( + ai_i8* out_ptr, const ai_i8* in_ptr, + const ai_size in_size, const ai_size ch_size, + const ai_i32 in_ch_step, const ai_i32 out_ch_step, + const ai_i32 mult, const ai_i32 shift, const ai_i32 min_diff, + ai_i32* scratch); + + +/** + * @brief forward lite function for a u8 softmax non-linearity where the softmax is applied per channel. + * @ingroup lite_nl_generic_integer + * @param output The pointer to output buffer (s8). + * @param input The pointer to input buffer (s8). + * @param in_size. The size of the input (including channels). + * @param ch_size The nsize of each channel. + * @param in_ch_step The step between consecutive elements (inputs) + * @param out_ch_step The step between consecutive elements (outputs) + * @param mult + * @param shift + * @param min_diff + */ +LITE_API_ENTRY +void forward_lite_nl_softmax_iu8ou8( + ai_u8* out_ptr, const ai_u8* in_ptr, + const ai_size in_size, const ai_size ch_size, + const ai_i32 in_ch_step, const ai_i32 out_ch_step, + const ai_i32 mult, const ai_i32 shift, const ai_i32 min_diff, + ai_i32* scratch); + +#endif /* LITE_NL_GENERIC_INTEGER_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_nl_list.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_nl_list.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_nl_list.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_nl_list.h index a42c0354..5263872b 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_nl_list.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_nl_list.h @@ -1,75 +1,75 @@ -/** - ****************************************************************************** - * @file lite_nl_list.h - * @author STMicroelectronics - * @brief header file of lite supported non-linearities routines - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -// #define LITE_NL_ENTRY(nl_id_, nl_name_, nl_op_, nl_op_args_) - -/* No sentry. This is deliberate!! */ - -LITE_NL_ENTRY(1, abs, AI_ABS, 1) -LITE_NL_ENTRY(2, acos, AI_MATH_ACOS, 1) -LITE_NL_ENTRY(3, acosh, AI_MATH_ACOSH, 1) -LITE_NL_ENTRY(4, asin, AI_MATH_ASIN, 1) -LITE_NL_ENTRY(5, asinh, AI_MATH_ASINH, 1) -LITE_NL_ENTRY(6, atan, AI_MATH_ATAN, 1) -LITE_NL_ENTRY(7, atanh, AI_MATH_ATANH, 1) -LITE_NL_ENTRY(8, ceil, AI_CEIL, 1) -LITE_NL_ENTRY(9, cos, AI_MATH_COS, 1) -LITE_NL_ENTRY(10, cosh, AI_MATH_COSH, 1) -LITE_NL_ENTRY(11, erf, AI_MATH_ERF, 1) -LITE_NL_ENTRY(12, exp, AI_MATH_EXP, 1) -LITE_NL_ENTRY(13, floor, AI_FLOOR, 1) -LITE_NL_ENTRY(14, hardmax, /**/, 0) -LITE_NL_ENTRY(15, log, AI_MATH_LOG, 1) -LITE_NL_ENTRY(16, logistic, AI_MATH_LOGISTIC, 1) -LITE_NL_ENTRY(17, neg, AI_NEG, 1) -LITE_NL_ENTRY(18, rsqrt, AI_MATH_RSQRT, 1) -LITE_NL_ENTRY(19, sin, AI_MATH_SIN, 1) -LITE_NL_ENTRY(20, sinh, AI_MATH_SINH, 1) -LITE_NL_ENTRY(21, tan, AI_MATH_TAN, 1) -LITE_NL_ENTRY(22, square, AI_MATH_SQUARE, 1) -LITE_NL_ENTRY(23, reciprocal, AI_RECIPROCAL, 1) -LITE_NL_ENTRY(24, round, AI_ROUND, 1) -LITE_NL_ENTRY(25, sigmoid, AI_MATH_SIGMOID, 1) -LITE_NL_ENTRY(26, swish, AI_MATH_SWISH, 1) -LITE_NL_ENTRY(27, hard_swish, AI_MATH_HARD_SWISH, 1) -LITE_NL_ENTRY(28, sign, AI_SIGN, 1) -LITE_NL_ENTRY(29, sqrt, AI_MATH_SQRT, 1) -// LITE_NL_ENTRY(30, softmax, /**/, 0) // for future changes -// LITE_NL_ENTRY(31, softmax_zero_channel, /**/, 0) // for future changes -LITE_NL_ENTRY(32, soft_plus, AI_MATH_SOFT_PLUS, 1) -LITE_NL_ENTRY(33, soft_sign, AI_MATH_SOFT_SIGN, 1) -LITE_NL_ENTRY(34, tanh, AI_MATH_TANH, 1) -LITE_NL_ENTRY(35, prelu, /**/, 0) -LITE_NL_ENTRY(36, relu, AI_MATH_RELU, 1) -LITE_NL_ENTRY(37, relu_generic, /**/, 0) - -LITE_NL_ENTRY(101, elu, AI_MATH_ELU, 2) -LITE_NL_ENTRY(102, relu_thresholded, AI_MATH_RELU_THRESHOLDED, 2) - - -LITE_NL_ENTRY(201, clip, AI_CLAMP, 3) -LITE_NL_ENTRY(202, hard_sigmoid, AI_MATH_HARD_SIGMOID, 3) -LITE_NL_ENTRY(203, selu, AI_MATH_SELU, 3) -LITE_NL_ENTRY(204, gelu, AI_MATH_GELU, 2) - - -#undef LITE_NL_ENTRY -#undef LITE_NL_IIF_0 -#undef LITE_NL_IIF_1 -#undef LITE_NL_IIF_2 -#undef LITE_NL_IIF_3 +/** + ****************************************************************************** + * @file lite_nl_list.h + * @author STMicroelectronics + * @brief header file of lite supported non-linearities routines + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +// #define LITE_NL_ENTRY(nl_id_, nl_name_, nl_op_, nl_op_args_) + +/* No sentry. This is deliberate!! */ + +LITE_NL_ENTRY(1, abs, AI_ABS, 1) +LITE_NL_ENTRY(2, acos, AI_MATH_ACOS, 1) +LITE_NL_ENTRY(3, acosh, AI_MATH_ACOSH, 1) +LITE_NL_ENTRY(4, asin, AI_MATH_ASIN, 1) +LITE_NL_ENTRY(5, asinh, AI_MATH_ASINH, 1) +LITE_NL_ENTRY(6, atan, AI_MATH_ATAN, 1) +LITE_NL_ENTRY(7, atanh, AI_MATH_ATANH, 1) +LITE_NL_ENTRY(8, ceil, AI_CEIL, 1) +LITE_NL_ENTRY(9, cos, AI_MATH_COS, 1) +LITE_NL_ENTRY(10, cosh, AI_MATH_COSH, 1) +LITE_NL_ENTRY(11, erf, AI_MATH_ERF, 1) +LITE_NL_ENTRY(12, exp, AI_MATH_EXP, 1) +LITE_NL_ENTRY(13, floor, AI_FLOOR, 1) +LITE_NL_ENTRY(14, hardmax, /**/, 0) +LITE_NL_ENTRY(15, log, AI_MATH_LOG, 1) +LITE_NL_ENTRY(16, logistic, AI_MATH_LOGISTIC, 1) +LITE_NL_ENTRY(17, neg, AI_NEG, 1) +LITE_NL_ENTRY(18, rsqrt, AI_MATH_RSQRT, 1) +LITE_NL_ENTRY(19, sin, AI_MATH_SIN, 1) +LITE_NL_ENTRY(20, sinh, AI_MATH_SINH, 1) +LITE_NL_ENTRY(21, tan, AI_MATH_TAN, 1) +LITE_NL_ENTRY(22, square, AI_MATH_SQUARE, 1) +LITE_NL_ENTRY(23, reciprocal, AI_RECIPROCAL, 1) +LITE_NL_ENTRY(24, round, AI_ROUND, 1) +LITE_NL_ENTRY(25, sigmoid, AI_MATH_SIGMOID, 1) +LITE_NL_ENTRY(26, swish, AI_MATH_SWISH, 1) +LITE_NL_ENTRY(27, hard_swish, AI_MATH_HARD_SWISH, 1) +LITE_NL_ENTRY(28, sign, AI_SIGN, 1) +LITE_NL_ENTRY(29, sqrt, AI_MATH_SQRT, 1) +// LITE_NL_ENTRY(30, softmax, /**/, 0) // for future changes +// LITE_NL_ENTRY(31, softmax_zero_channel, /**/, 0) // for future changes +LITE_NL_ENTRY(32, soft_plus, AI_MATH_SOFT_PLUS, 1) +LITE_NL_ENTRY(33, soft_sign, AI_MATH_SOFT_SIGN, 1) +LITE_NL_ENTRY(34, tanh, AI_MATH_TANH, 1) +LITE_NL_ENTRY(35, prelu, /**/, 0) +LITE_NL_ENTRY(36, relu, AI_MATH_RELU, 1) +LITE_NL_ENTRY(37, relu_generic, /**/, 0) + +LITE_NL_ENTRY(101, elu, AI_MATH_ELU, 2) +LITE_NL_ENTRY(102, relu_thresholded, AI_MATH_RELU_THRESHOLDED, 2) + + +LITE_NL_ENTRY(201, clip, AI_CLAMP, 3) +LITE_NL_ENTRY(202, hard_sigmoid, AI_MATH_HARD_SIGMOID, 3) +LITE_NL_ENTRY(203, selu, AI_MATH_SELU, 3) +LITE_NL_ENTRY(204, gelu, AI_MATH_GELU, 2) + + +#undef LITE_NL_ENTRY +#undef LITE_NL_IIF_0 +#undef LITE_NL_IIF_1 +#undef LITE_NL_IIF_2 +#undef LITE_NL_IIF_3 diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_norm_f32.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_norm_f32.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_norm_f32.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_norm_f32.h index 1ca9c436..93529008 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_norm_f32.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_norm_f32.h @@ -1,52 +1,52 @@ -/** - ****************************************************************************** - * @file lite_norm_f32.h - * @author AIS - * @brief header file of AI platform norm in lite mode - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_NORM_F32_H -#define LITE_NORM_F32_H -#pragma once - -#include "ai_lite_interface.h" - -enum ai_lite_norm_type_ { - AI_LITE_NORM_NONE = 0, - AI_LITE_NORM_L1 = 1, - AI_LITE_NORM_L2 = 2, - AI_LITE_NORM_MAX = 3, -}; - -/*! - * @brief Forward function for a batch normalization (BN) layer with - * signed float input, signed float output, and float parameters. - * @ingroup lite_norm_f32 - * @param output The pointer to output buffer. - * @param input The pointer to input buffer. - * @param scale The pointer to BN scale param. - * @param bias The pointer to bias. - * @param n_elements The number of elements in the input tensor. - * @param n_channel_in The number of channel in the input tensor. - */ -LITE_API_ENTRY -void forward_lite_norm_if32of32( ai_float* output, - const ai_float* input, - const ai_u32 ai_lite_norm_type, - const ai_float exponent, - const ai_size n_axis, - const ai_size n_axis_stride, - const ai_size n_el, - ai_bool scale); - -#endif /* LITE_NORM_F32_H */ +/** + ****************************************************************************** + * @file lite_norm_f32.h + * @author AIS + * @brief header file of AI platform norm in lite mode + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_NORM_F32_H +#define LITE_NORM_F32_H +#pragma once + +#include "ai_lite_interface.h" + +enum ai_lite_norm_type_ { + AI_LITE_NORM_NONE = 0, + AI_LITE_NORM_L1 = 1, + AI_LITE_NORM_L2 = 2, + AI_LITE_NORM_MAX = 3, +}; + +/*! + * @brief Forward function for a batch normalization (BN) layer with + * signed float input, signed float output, and float parameters. + * @ingroup lite_norm_f32 + * @param output The pointer to output buffer. + * @param input The pointer to input buffer. + * @param scale The pointer to BN scale param. + * @param bias The pointer to bias. + * @param n_elements The number of elements in the input tensor. + * @param n_channel_in The number of channel in the input tensor. + */ +LITE_API_ENTRY +void forward_lite_norm_if32of32( ai_float* output, + const ai_float* input, + const ai_u32 ai_lite_norm_type, + const ai_float exponent, + const ai_size n_axis, + const ai_size n_axis_stride, + const ai_size n_el, + ai_bool scale); + +#endif /* LITE_NORM_F32_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_operators.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_operators.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_operators.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_operators.h index c2d1ff94..2c33b0ad 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_operators.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_operators.h @@ -1,51 +1,51 @@ -/** - ****************************************************************************** - * @file lite_operators.h - * @author AIS - * @brief main header file of AI platform lite operators list - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_OPERATORS_H -#define LITE_OPERATORS_H - -#include "lite_internal_apis.h" - -#include "lite_bn_f32.h" -#include "lite_bn_integer.h" -#include "lite_conv2d.h" -#include "lite_conv2d_dqnn.h" -#include "lite_convert_dqnn.h" -#include "lite_dense_if32.h" -#include "lite_dense_is1.h" -#include "lite_dense_is1ws1.h" -#include "lite_dense_ws1.h" -#include "lite_gru_f32.h" -#include "lite_dw_dqnn.h" -#include "lite_pw_dqnn.h" -#include "lite_conv2d_sssa8_ch.h" - -#include "lite_dense_is8os8ws8.h" -#include "lite_dense_is8os1ws1.h" -#include "lite_generic_float.h" -#include "lite_pool_f32.h" -#include "lite_maxpool_dqnn.h" -#include "lite_nl_generic_integer.h" -#include "lite_pad_generic.h" -#include "lite_pad_dqnn.h" -#include "lite_upsample_generic.h" -#include "lite_resize.h" -#include "lite_lstm.h" -#include "lite_argminmax.h" -#include "lite_pool_is8os8.h" - -#endif /* LITE_OPERATORS_H */ +/** + ****************************************************************************** + * @file lite_operators.h + * @author AIS + * @brief main header file of AI platform lite operators list + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_OPERATORS_H +#define LITE_OPERATORS_H + +#include "lite_internal_apis.h" + +#include "lite_bn_f32.h" +#include "lite_bn_integer.h" +#include "lite_conv2d.h" +#include "lite_conv2d_dqnn.h" +#include "lite_convert_dqnn.h" +#include "lite_dense_if32.h" +#include "lite_dense_is1.h" +#include "lite_dense_is1ws1.h" +#include "lite_dense_ws1.h" +#include "lite_gru_f32.h" +#include "lite_dw_dqnn.h" +#include "lite_pw_dqnn.h" +#include "lite_conv2d_sssa8_ch.h" + +#include "lite_dense_is8os8ws8.h" +#include "lite_dense_is8os1ws1.h" +#include "lite_generic_float.h" +#include "lite_pool_f32.h" +#include "lite_maxpool_dqnn.h" +#include "lite_nl_generic_integer.h" +#include "lite_pad_generic.h" +#include "lite_pad_dqnn.h" +#include "lite_upsample_generic.h" +#include "lite_resize.h" +#include "lite_lstm.h" +#include "lite_argminmax.h" +#include "lite_pool_is8os8.h" + +#endif /* LITE_OPERATORS_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_pad_dqnn.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_pad_dqnn.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_pad_dqnn.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_pad_dqnn.h index dd662f39..afc58513 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_pad_dqnn.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_pad_dqnn.h @@ -1,48 +1,48 @@ -/** - ****************************************************************************** - * @file lite_pad_dqnn.h - * @author AIS - * @brief header file of AI platform lite padding kernel datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_PADDING_DQNN_H -#define LITE_PADDING_DQNN_H - - -#include "ai_lite_interface.h" - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Handles padding with binary input and binary output - Lite I/F - * @ingroup lite_padding_dqnn - */ -LITE_API_ENTRY -void forward_lite_pad_is1os1(const ai_u32 *pDataIn_init, - ai_u32 *pDataOut_init, - const ai_i32 width_in, - const ai_i32 width_out, - const ai_i32 height_in, - const ai_i32 height_out, - const ai_u32 n_channel_out, - const ai_i32 mode, - const ai_u16 pads_x, - const ai_u16 pads_y, - const ai_u16 pads_x_r, - const ai_u16 pads_y_b, - const ai_u32 pad_value); - - -#endif /*LITE_PADDING_DQNN_H*/ +/** + ****************************************************************************** + * @file lite_pad_dqnn.h + * @author AIS + * @brief header file of AI platform lite padding kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_PADDING_DQNN_H +#define LITE_PADDING_DQNN_H + + +#include "ai_lite_interface.h" + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles padding with binary input and binary output - Lite I/F + * @ingroup lite_padding_dqnn + */ +LITE_API_ENTRY +void forward_lite_pad_is1os1(const ai_u32 *pDataIn_init, + ai_u32 *pDataOut_init, + const ai_i32 width_in, + const ai_i32 width_out, + const ai_i32 height_in, + const ai_i32 height_out, + const ai_u32 n_channel_out, + const ai_i32 mode, + const ai_u16 pads_x, + const ai_u16 pads_y, + const ai_u16 pads_x_r, + const ai_u16 pads_y_b, + const ai_u32 pad_value); + + +#endif /*LITE_PADDING_DQNN_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_pad_generic.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_pad_generic.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_pad_generic.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_pad_generic.h index 9745a896..7a15a821 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_pad_generic.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_pad_generic.h @@ -1,111 +1,111 @@ -/** - ****************************************************************************** - * @file lite_pad_generic.h - * @author AIS - * @brief header file of AI platform lite padding kernel datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_PAD_GENERIC_H -#define LITE_PAD_GENERIC_H - - -#include "ai_lite_interface.h" - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Handles padding with 8 bits input/output in constant mode - Lite I/F - * Channel 1st Format Input and Output - * @ingroup lite_padding_dqnn - */ - -/* Variant used for padding pattern = (1, 1, 1, 1) */ -LITE_API_ENTRY -void forward_lite_pad_8bit_ch1st_3x3_constant_P1111(ai_ptr_const in_data_tensor, - ai_ptr out_data_tensor, - const ai_handle fill_value, - const ai_i32 height_in, - const ai_i32 channel_in, - const ai_ptr_offset ch_stride_in, - const ai_ptr_offset h_stride_in, - const ai_ptr_offset h_stride_pad); - -/* Variant used for padding pattern = (0, 0, 2, 2) */ -LITE_API_ENTRY -void forward_lite_pad_8bit_ch1st_3x3_constant_P0022(ai_ptr_const in_data_tensor, - ai_ptr out_data_tensor, - const ai_handle fill_value, - const ai_i32 height_in, - const ai_i32 channel_in, - const ai_ptr_offset ch_stride_in, - const ai_ptr_offset h_stride_in, - const ai_ptr_offset h_stride_pad); - -/*! - * @brief Handles padding with 8 bits input/output in constant mode - Lite I/F - * @ingroup lite_padding_dqnn - */ -LITE_API_ENTRY -void forward_lite_pad_constant(ai_ptr_const in_data, - ai_ptr out_data, - const ai_handle fill_value, - const ai_i16 in_bits, - const ai_i32 height_in, - const ai_ptr_offset ch_stride_in, - const ai_ptr_offset h_stride_in, - const ai_ptr_offset h_stride_pad, - const ai_ptr_offset h_stride_pad_b, - const ai_ptr_offset w_stride_pad, - const ai_ptr_offset w_stride_pad_r); - -/*! - * @brief Handles padding with 8 bits input/output in edge mode - Lite I/F - * @ingroup lite_padding_dqnn - */ -void forward_lite_pad_edge(ai_ptr_const in_data_tensor, - ai_ptr out_data, - const ai_i32 height_in, - const ai_i16 pads_y, - const ai_i16 pads_x_r, - const ai_ptr_offset h_stride_in, - const ai_ptr_offset w_stride_in, - const ai_ptr_offset h_stride_out, - const ai_ptr_offset h_stride_pad, - const ai_ptr_offset w_stride_pad, - const ai_ptr_offset h_stride_pad_b); - -/*! - * @brief Handles padding with 8 bits input/output in reflect mode - Lite I/F - * @ingroup lite_padding_dqnn - */ -void forward_lite_pad_reflect(ai_ptr_const in_data, - ai_ptr out_data, - const ai_i32 depth, - const ai_i32 height_in, - const ai_i32 width_in, - const ai_i32 height_out, - const ai_i32 width_out, - const ai_ptr_offset h_stride_in, - const ai_ptr_offset w_stride_in, - const ai_ptr_offset h_stride_out, - const ai_ptr_offset w_stride_out, - const ai_i16 pads_x, - const ai_i16 pads_y, - const ai_i16 pads_y_b, - const ai_ptr_offset h_stride_pad, - const ai_ptr_offset w_stride_pad, - const ai_ptr_offset w_stride_pad_r); - -#endif /* LITE_PAD_GENERIC_H */ +/** + ****************************************************************************** + * @file lite_pad_generic.h + * @author AIS + * @brief header file of AI platform lite padding kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_PAD_GENERIC_H +#define LITE_PAD_GENERIC_H + + +#include "ai_lite_interface.h" + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles padding with 8 bits input/output in constant mode - Lite I/F + * Channel 1st Format Input and Output + * @ingroup lite_padding_dqnn + */ + +/* Variant used for padding pattern = (1, 1, 1, 1) */ +LITE_API_ENTRY +void forward_lite_pad_8bit_ch1st_3x3_constant_P1111(ai_ptr_const in_data_tensor, + ai_ptr out_data_tensor, + const ai_handle fill_value, + const ai_i32 height_in, + const ai_i32 channel_in, + const ai_ptr_offset ch_stride_in, + const ai_ptr_offset h_stride_in, + const ai_ptr_offset h_stride_pad); + +/* Variant used for padding pattern = (0, 0, 2, 2) */ +LITE_API_ENTRY +void forward_lite_pad_8bit_ch1st_3x3_constant_P0022(ai_ptr_const in_data_tensor, + ai_ptr out_data_tensor, + const ai_handle fill_value, + const ai_i32 height_in, + const ai_i32 channel_in, + const ai_ptr_offset ch_stride_in, + const ai_ptr_offset h_stride_in, + const ai_ptr_offset h_stride_pad); + +/*! + * @brief Handles padding with 8 bits input/output in constant mode - Lite I/F + * @ingroup lite_padding_dqnn + */ +LITE_API_ENTRY +void forward_lite_pad_constant(ai_ptr_const in_data, + ai_ptr out_data, + const ai_handle fill_value, + const ai_i16 in_bits, + const ai_i32 height_in, + const ai_ptr_offset ch_stride_in, + const ai_ptr_offset h_stride_in, + const ai_ptr_offset h_stride_pad, + const ai_ptr_offset h_stride_pad_b, + const ai_ptr_offset w_stride_pad, + const ai_ptr_offset w_stride_pad_r); + +/*! + * @brief Handles padding with 8 bits input/output in edge mode - Lite I/F + * @ingroup lite_padding_dqnn + */ +void forward_lite_pad_edge(ai_ptr_const in_data_tensor, + ai_ptr out_data, + const ai_i32 height_in, + const ai_i16 pads_y, + const ai_i16 pads_x_r, + const ai_ptr_offset h_stride_in, + const ai_ptr_offset w_stride_in, + const ai_ptr_offset h_stride_out, + const ai_ptr_offset h_stride_pad, + const ai_ptr_offset w_stride_pad, + const ai_ptr_offset h_stride_pad_b); + +/*! + * @brief Handles padding with 8 bits input/output in reflect mode - Lite I/F + * @ingroup lite_padding_dqnn + */ +void forward_lite_pad_reflect(ai_ptr_const in_data, + ai_ptr out_data, + const ai_i32 depth, + const ai_i32 height_in, + const ai_i32 width_in, + const ai_i32 height_out, + const ai_i32 width_out, + const ai_ptr_offset h_stride_in, + const ai_ptr_offset w_stride_in, + const ai_ptr_offset h_stride_out, + const ai_ptr_offset w_stride_out, + const ai_i16 pads_x, + const ai_i16 pads_y, + const ai_i16 pads_y_b, + const ai_ptr_offset h_stride_pad, + const ai_ptr_offset w_stride_pad, + const ai_ptr_offset w_stride_pad_r); + +#endif /* LITE_PAD_GENERIC_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_pool_f32.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_pool_f32.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_pool_f32.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_pool_f32.h index fdd2e3ab..97785202 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_pool_f32.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_pool_f32.h @@ -1,69 +1,69 @@ -/** - ****************************************************************************** - * @file lite_maxpool_dqnn.h - * @author AIS - * @brief header file of AI platform lite maxpool kernel datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_POOL_F32_H -#define LITE_POOL_F32_H - -#include "ai_lite_interface.h" - - -#define FUNC_POOL(handle) \ - ((func_pool)(handle)) - - -/*! - * @typedef (*func_pool) - * @ingroup layers_pool - * @brief Fuction pointer for generic pooling transform - * this function pointer abstracts a generic pooling layer. - * see @ref pool_func_ap_array_f32 as examples - */ -typedef void (*func_pool)(ai_float* in, - const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, - const ai_u16 padding_x, const ai_u16 padding_y, - const ai_u16 stride_x, const ai_u16 stride_y, - const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, - ai_float* out); - - -/******************************************************************************/ -/** Conv2d Functions Section **/ -/******************************************************************************/ - -AI_INTERNAL_API -void pool_func_mp_array_f32(ai_float* pData_in, - const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, - const ai_u16 padding_x, const ai_u16 padding_y, - const ai_u16 stride_x, const ai_u16 stride_y, - const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, - ai_float* pData_out); - -AI_INTERNAL_API -void pool_func_ap_array_f32(ai_float *pData_in, - const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, - const ai_u16 padding_x, const ai_u16 padding_y, - const ai_u16 stride_x, const ai_u16 stride_y, - const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, - ai_float *pData_out); - -#endif // LITE_POOL_F32_H_ +/** + ****************************************************************************** + * @file lite_maxpool_dqnn.h + * @author AIS + * @brief header file of AI platform lite maxpool kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_POOL_F32_H +#define LITE_POOL_F32_H + +#include "ai_lite_interface.h" + + +#define FUNC_POOL(handle) \ + ((func_pool)(handle)) + + +/*! + * @typedef (*func_pool) + * @ingroup layers_pool + * @brief Fuction pointer for generic pooling transform + * this function pointer abstracts a generic pooling layer. + * see @ref pool_func_ap_array_f32 as examples + */ +typedef void (*func_pool)(ai_float* in, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + ai_float* out); + + +/******************************************************************************/ +/** Conv2d Functions Section **/ +/******************************************************************************/ + +AI_INTERNAL_API +void pool_func_mp_array_f32(ai_float* pData_in, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + ai_float* pData_out); + +AI_INTERNAL_API +void pool_func_ap_array_f32(ai_float *pData_in, + const ai_u16 dim_im_in_x, const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, const ai_u16 dim_kernel_y, + const ai_u16 padding_x, const ai_u16 padding_y, + const ai_u16 stride_x, const ai_u16 stride_y, + const ai_u16 dim_im_out_x, const ai_u16 dim_im_out_y, + ai_float *pData_out); + +#endif // LITE_POOL_F32_H_ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_pool_is8os8.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_pool_is8os8.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_pool_is8os8.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_pool_is8os8.h index 1791242a..34a2c654 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_pool_is8os8.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_pool_is8os8.h @@ -1,62 +1,62 @@ -/** - ****************************************************************************** - * @file lite_pool_is8os8.h - * @author AIS - * @brief header file of AI platform lite integer pooling function - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_POOL_IS8OS8 -#define LITE_POOL_IS8OS8 - -#include "ai_lite_interface.h" - -/** - * @brief lite function for average pooling. - * @ingroup lite_nl_generic_integer - * @param input The pointer to input buffer. - * @param output The pointer to output buffer. - * @param[in] dim_im_in_x dimension of the input width - * @param[in] dim_im_in_y dimension of the input height - * @param[in] ch_im_in number of the input channel - * @param[in] dim_kernel_x dimension of the kernel width - * @param[in] dim_kernel_y dimension of the kernel height - * @param[in] padding_x first dimension of the padding - * @param[in] padding_y second dimension of the padding - * @param[in] stride_x first dimension of the stride - * @param[in] stride_y second dimension of the stride - * @param[in] dim_im_out_x dimension of the output width - * @param[in] dim_im_out_y dimension of the output height - * @param[in] in_scale input scale - * @param[in] in_zeropoint input zero point - * @param[in] out_scale output scale - * @param[in] out_zeropoint output zero point - */ -void forward_lite_avepool_is8os8( const ai_i8 *pData_in, - ai_i8* pData_out, - const ai_u16 dim_im_in_x, - const ai_u16 dim_im_in_y, - const ai_u16 ch_im_in, - const ai_u16 dim_kernel_x, - const ai_u16 dim_kernel_y, - const ai_u16 padding_x, - const ai_u16 padding_y, - const ai_u16 stride_x, - const ai_u16 stride_y, - const ai_u16 dim_im_out_x, - const ai_u16 dim_im_out_y, - const ai_float in_scale, - const ai_i8 in_zeropoint, - const ai_float out_scale, - const ai_i8 out_zeropoint); -#endif /* LITE_POOL_IS8OS8 */ - +/** + ****************************************************************************** + * @file lite_pool_is8os8.h + * @author AIS + * @brief header file of AI platform lite integer pooling function + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_POOL_IS8OS8 +#define LITE_POOL_IS8OS8 + +#include "ai_lite_interface.h" + +/** + * @brief lite function for average pooling. + * @ingroup lite_nl_generic_integer + * @param input The pointer to input buffer. + * @param output The pointer to output buffer. + * @param[in] dim_im_in_x dimension of the input width + * @param[in] dim_im_in_y dimension of the input height + * @param[in] ch_im_in number of the input channel + * @param[in] dim_kernel_x dimension of the kernel width + * @param[in] dim_kernel_y dimension of the kernel height + * @param[in] padding_x first dimension of the padding + * @param[in] padding_y second dimension of the padding + * @param[in] stride_x first dimension of the stride + * @param[in] stride_y second dimension of the stride + * @param[in] dim_im_out_x dimension of the output width + * @param[in] dim_im_out_y dimension of the output height + * @param[in] in_scale input scale + * @param[in] in_zeropoint input zero point + * @param[in] out_scale output scale + * @param[in] out_zeropoint output zero point + */ +void forward_lite_avepool_is8os8( const ai_i8 *pData_in, + ai_i8* pData_out, + const ai_u16 dim_im_in_x, + const ai_u16 dim_im_in_y, + const ai_u16 ch_im_in, + const ai_u16 dim_kernel_x, + const ai_u16 dim_kernel_y, + const ai_u16 padding_x, + const ai_u16 padding_y, + const ai_u16 stride_x, + const ai_u16 stride_y, + const ai_u16 dim_im_out_x, + const ai_u16 dim_im_out_y, + const ai_float in_scale, + const ai_i8 in_zeropoint, + const ai_float out_scale, + const ai_i8 out_zeropoint); +#endif /* LITE_POOL_IS8OS8 */ + diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_pw.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_pw.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_pw.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_pw.h index 3a33ef90..b0add112 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_pw.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_pw.h @@ -1,56 +1,56 @@ -/** - ****************************************************************************** - * @file lite_pw.h - * @author AIS - * @brief header file of AI platform lite pointwise kernel datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_PW_H -#define LITE_PW_H - - -#include "ai_lite_interface.h" - - - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Handles pw convolutions generic case - * @ingroup lite_pw - */ -LITE_API_ENTRY -void -forward_lite_pw_sssa8_ch(const ai_i8 *pData_in, - const ai_u16 width_in, - const ai_u16 height_in, - const ai_u16 filt_stride_x, - const ai_u16 filt_stride_y, - const ai_u16 n_channel_in, - const ai_i8 *pWeights, - const ai_u16 n_channel_out, - const ai_i32 *pBias, - const ai_i8 in_zeropoint, - const ai_i8 out_zeropoint, - const ai_float in_scale, - const ai_float out_scale, - const ai_float *pWt_scale, - const ai_layer_format_type out_ch_format, - ai_i8 *pData_out, - ai_u16 weights_prefetch_enabled, - ai_i32 scratch_size, - ai_i16 *pBuffer_a); - -#endif /*LITE_PW_H*/ +/** + ****************************************************************************** + * @file lite_pw.h + * @author AIS + * @brief header file of AI platform lite pointwise kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_PW_H +#define LITE_PW_H + + +#include "ai_lite_interface.h" + + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles pw convolutions generic case + * @ingroup lite_pw + */ +LITE_API_ENTRY +void +forward_lite_pw_sssa8_ch(const ai_i8 *pData_in, + const ai_u16 width_in, + const ai_u16 height_in, + const ai_u16 filt_stride_x, + const ai_u16 filt_stride_y, + const ai_u16 n_channel_in, + const ai_i8 *pWeights, + const ai_u16 n_channel_out, + const ai_i32 *pBias, + const ai_i8 in_zeropoint, + const ai_i8 out_zeropoint, + const ai_float in_scale, + const ai_float out_scale, + const ai_float *pWt_scale, + const ai_layer_format_type out_ch_format, + ai_i8 *pData_out, + ai_u16 weights_prefetch_enabled, + ai_i32 scratch_size, + ai_i16 *pBuffer_a); + +#endif /*LITE_PW_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_pw_dqnn.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_pw_dqnn.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_pw_dqnn.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_pw_dqnn.h index 8a89e602..38c11eb5 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_pw_dqnn.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_pw_dqnn.h @@ -1,127 +1,127 @@ -/** - ****************************************************************************** - * @file lite_pw_dqnn.h - * @author AIS - * @brief header file of AI platform lite dqnn pointwise kernel datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_PW_DQNN_H -#define LITE_PW_DQNN_H - - -#include "ai_lite_interface.h" - - -/******************************************************************************/ -/* Forward Functions Section */ -/******************************************************************************/ - -/*! - * @brief Handles point wise convolution with binary input, binary output and - * binary weights - Lite API version - * @ingroup lite_pw_dqnn - */ -LITE_API_ENTRY -void forward_lite_pw_is1os1ws1_bn(const ai_u32 *pDataIn_init, - ai_u32 *pDataOut_init, - const ai_u32 *pWeights_init, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_i32 *pThreshold); - -/*! - * @brief Handles point wise convolution with binary input, binary output and - * binary weights - Lite API version - Optimized thanks to Optim2 - * assumptions - * @ingroup lite_pw_dqnn - */ -LITE_API_ENTRY -void forward_lite_pw_is1os1ws1_bn_optim2(const ai_u32 *pDataIn_init, - ai_u32 *pDataOut_init, - const ai_u32 *pWeights_init, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_i32 *pThreshold); - -/*! - * @brief Handles point wise convolution with binary input, 8-bits output and - * binary weights - Lite API version - * @ingroup lite_pw_dqnn - */ -LITE_API_ENTRY -void forward_lite_pw_is1os8ws1_bn(const ai_u32 *pDataIn_init, - ai_i8 *pDataOut_init, - const ai_u32 *pWeights_init, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_float *pScale, - const ai_float *pOffset); - -/*! - * @brief Handles point wise convolution with binary input, 8-bits output and - * binary weights - Lite API version - Optimized thanks to Optim1 - * assumptions - * @ingroup lite_pw_dqnn - */ -LITE_API_ENTRY -void forward_lite_pw_is1os8ws1_bn_optim1(const ai_u32 *pDataIn_init, - ai_i8 *pDataOut_init, - const ai_u32 *pWeights_init, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_float *pScale, - const ai_float *pOffset); - -/*! - * @brief Handles point-wise convolution with binary input, float32 output - * and binary weights - Lite API version - * @ingroup lite_pw_dqnn - */ -LITE_API_ENTRY -void forward_lite_pw_is1of32ws1_bn(const ai_u32 *pDataIn_init, - ai_float *pDataOut_init, - const ai_u32 *pWeights_init, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_float *pScale, - const ai_float *pOffset); - -/*! - * @brief Handles point-wise convolution with binary input, float32 output - * and binary weights - Lite API version - Optimized thanks to Optim1 - * assumptions - * @ingroup lite_pw_dqnn - */ -LITE_API_ENTRY -void forward_lite_pw_is1of32ws1_bn_optim1(const ai_u32 *pDataIn_init, - ai_float *pDataOut_init, - const ai_u32 *pWeights_init, - const ai_u32 n_channel_in, - const ai_u32 n_channel_out, - const ai_i32 width_out, - const ai_i32 height_out, - const ai_float *pScale, - const ai_float *pOffset); - - -#endif /*LITE_PW_DQNN_H*/ +/** + ****************************************************************************** + * @file lite_pw_dqnn.h + * @author AIS + * @brief header file of AI platform lite dqnn pointwise kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_PW_DQNN_H +#define LITE_PW_DQNN_H + + +#include "ai_lite_interface.h" + + +/******************************************************************************/ +/* Forward Functions Section */ +/******************************************************************************/ + +/*! + * @brief Handles point wise convolution with binary input, binary output and + * binary weights - Lite API version + * @ingroup lite_pw_dqnn + */ +LITE_API_ENTRY +void forward_lite_pw_is1os1ws1_bn(const ai_u32 *pDataIn_init, + ai_u32 *pDataOut_init, + const ai_u32 *pWeights_init, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 *pThreshold); + +/*! + * @brief Handles point wise convolution with binary input, binary output and + * binary weights - Lite API version - Optimized thanks to Optim2 + * assumptions + * @ingroup lite_pw_dqnn + */ +LITE_API_ENTRY +void forward_lite_pw_is1os1ws1_bn_optim2(const ai_u32 *pDataIn_init, + ai_u32 *pDataOut_init, + const ai_u32 *pWeights_init, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_i32 *pThreshold); + +/*! + * @brief Handles point wise convolution with binary input, 8-bits output and + * binary weights - Lite API version + * @ingroup lite_pw_dqnn + */ +LITE_API_ENTRY +void forward_lite_pw_is1os8ws1_bn(const ai_u32 *pDataIn_init, + ai_i8 *pDataOut_init, + const ai_u32 *pWeights_init, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_float *pScale, + const ai_float *pOffset); + +/*! + * @brief Handles point wise convolution with binary input, 8-bits output and + * binary weights - Lite API version - Optimized thanks to Optim1 + * assumptions + * @ingroup lite_pw_dqnn + */ +LITE_API_ENTRY +void forward_lite_pw_is1os8ws1_bn_optim1(const ai_u32 *pDataIn_init, + ai_i8 *pDataOut_init, + const ai_u32 *pWeights_init, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_float *pScale, + const ai_float *pOffset); + +/*! + * @brief Handles point-wise convolution with binary input, float32 output + * and binary weights - Lite API version + * @ingroup lite_pw_dqnn + */ +LITE_API_ENTRY +void forward_lite_pw_is1of32ws1_bn(const ai_u32 *pDataIn_init, + ai_float *pDataOut_init, + const ai_u32 *pWeights_init, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_float *pScale, + const ai_float *pOffset); + +/*! + * @brief Handles point-wise convolution with binary input, float32 output + * and binary weights - Lite API version - Optimized thanks to Optim1 + * assumptions + * @ingroup lite_pw_dqnn + */ +LITE_API_ENTRY +void forward_lite_pw_is1of32ws1_bn_optim1(const ai_u32 *pDataIn_init, + ai_float *pDataOut_init, + const ai_u32 *pWeights_init, + const ai_u32 n_channel_in, + const ai_u32 n_channel_out, + const ai_i32 width_out, + const ai_i32 height_out, + const ai_float *pScale, + const ai_float *pOffset); + + +#endif /*LITE_PW_DQNN_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_resize.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_resize.h similarity index 98% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_resize.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_resize.h index c3b69db7..4203649d 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_resize.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_resize.h @@ -1,79 +1,79 @@ -/** - ****************************************************************************** - * @file lite_resize.h - * @author AIS - * @brief header file of AI platform lite resize kernel datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - - ****************************************************************************** - */ -#ifndef LITE_RESIZE_H -#define LITE_RESIZE_H -#pragma once - -#include "ai_lite_interface.h" - -void forward_lite_resize_nearest(ai_ptr in_data, - ai_ptr out_data, - const ai_size width_in, - const ai_size height_in, - const ai_size n_channel_in, - const ai_ptr_offset stride_ch, - const ai_float width_scale, - const ai_float height_scale, - const ai_size width_out, - const ai_size height_out, - const ai_nearest_mode mode, - const ai_coord_transf_mode coord_transf_mode, - const ai_handle extrapol_val, - const ai_float* roi); - -void forward_lite_resize_bilinear_if32of32( const ai_float* in_data, - ai_float* out_data, - const ai_size width_in, - const ai_size height_in, - const ai_size n_channel_in, - const ai_float width_scale, - const ai_float height_scale, - const ai_size width_out, - const ai_size height_out, - const ai_coord_transf_mode coord_transf_mode, - const ai_handle extrapol_val, - const ai_float* roi); - -void forward_lite_resize_bilinear_is8os8( const ai_i8* in_data, - ai_i8* out_data, - const ai_size width_in, - const ai_size height_in, - const ai_size n_channel_in, - const ai_float width_scale, - const ai_float height_scale, - const ai_size width_out, - const ai_size height_out, - const ai_coord_transf_mode coord_transf_mode, - const ai_handle extrapol_val, - const ai_float* roi); - -void forward_lite_resize_bilinear_is16os16( const ai_i16* in_data, - ai_i16* out_data, - const ai_size width_in, - const ai_size height_in, - const ai_size n_channel_in, - const ai_float width_scale, - const ai_float height_scale, - const ai_size width_out, - const ai_size height_out, - const ai_coord_transf_mode coord_transf_mode, - const ai_handle extrapol_val, - const ai_float* roi); - -#endif /*LITE_RESIZE__H*/ +/** + ****************************************************************************** + * @file lite_resize.h + * @author AIS + * @brief header file of AI platform lite resize kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + + ****************************************************************************** + */ +#ifndef LITE_RESIZE_H +#define LITE_RESIZE_H +#pragma once + +#include "ai_lite_interface.h" + +void forward_lite_resize_nearest(ai_ptr in_data, + ai_ptr out_data, + const ai_size width_in, + const ai_size height_in, + const ai_size n_channel_in, + const ai_ptr_offset stride_ch, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_nearest_mode mode, + const ai_coord_transf_mode coord_transf_mode, + const ai_handle extrapol_val, + const ai_float* roi); + +void forward_lite_resize_bilinear_if32of32( const ai_float* in_data, + ai_float* out_data, + const ai_size width_in, + const ai_size height_in, + const ai_size n_channel_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_coord_transf_mode coord_transf_mode, + const ai_handle extrapol_val, + const ai_float* roi); + +void forward_lite_resize_bilinear_is8os8( const ai_i8* in_data, + ai_i8* out_data, + const ai_size width_in, + const ai_size height_in, + const ai_size n_channel_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_coord_transf_mode coord_transf_mode, + const ai_handle extrapol_val, + const ai_float* roi); + +void forward_lite_resize_bilinear_is16os16( const ai_i16* in_data, + ai_i16* out_data, + const ai_size width_in, + const ai_size height_in, + const ai_size n_channel_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_coord_transf_mode coord_transf_mode, + const ai_handle extrapol_val, + const ai_float* roi); + +#endif /*LITE_RESIZE__H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_upsample.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_upsample.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_upsample.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_upsample.h index 607723dc..094dbcfa 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_upsample.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_upsample.h @@ -1,239 +1,239 @@ -/** - ****************************************************************************** - * @file lite_upsample.h - * @author AIS - * @brief header file of AI platform lite upsample kernel datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_UPSAMPLE_H -#define LITE_UPSAMPLE_H -#pragma once - -#include "ai_lite_interface.h" - - -/** - * @brief Function to upsample in bilinear mode. - * The number of output channels is the same as the number of input channels. - * Input and output types are float. - * - * @param[in] in_data input data, to be upsampled - * @param[out] out_data upsampled output data - * @param[in] width_in input data width - * @param[in] height_in input data height - * @param[in] width_scale width_out/width_in scale ratio - * @param[in] height_scale height_out/height_in scale ratio - * @param[in] width_out output data width - * @param[in] height_out output data height - * @param[in] channel_in input/output channels. - * @param[in] center centered coordinates - */ -void forward_lite_upsample_bilinear_if32of32(const ai_float* in_data, - ai_float* out_data, - const ai_size width_in, - const ai_size height_in, - const ai_float width_scale, - const ai_float height_scale, - const ai_size width_out, - const ai_size height_out, - const ai_size n_channel, - const ai_bool center); - -/** - * @brief Function to upsample in bilinear mode. - * The number of output channels is the same as the number of input channels. - * Input and output types are signed int8. - * - * @param[in] in_data input data, to be upsampled - * @param[out] out_data upsampled output data - * @param[in] width_in input data width - * @param[in] height_in input data height - * @param[in] width_scale width_out/width_in scale ratio - * @param[in] height_scale height_out/height_in scale ratio - * @param[in] width_out output data width - * @param[in] height_out output data height - * @param[in] channel_in input/output channels. - * @param[in] center centered coordinates - */ -void forward_lite_upsample_bilinear_is8os8(const ai_i8* in_data, - ai_i8* out_data, - const ai_size width_in, - const ai_size height_in, - const ai_float width_scale, - const ai_float height_scale, - const ai_size width_out, - const ai_size height_out, - const ai_size n_channel, - const ai_bool center); - -/** - * @brief Function to upsample in bilinear mode. - * The number of output channels is the same as the number of input channels. - * Input and output types are unsinged int8. - * - * @param[in] in_data input data, to be upsampled - * @param[out] out_data upsampled output data - * @param[in] width_in input data width - * @param[in] height_in input data height - * @param[in] width_scale width_out/width_in scale ratio - * @param[in] height_scale height_out/height_in scale ratio - * @param[in] width_out output data width - * @param[in] height_out output data height - * @param[in] channel_in input/output channels. - * @param[in] center centered coordinates - */ -void forward_lite_upsample_bilinear_iu8ou8(const ai_u8* in_data, - ai_u8* out_data, - const ai_size width_in, - const ai_size height_in, - const ai_float width_scale, - const ai_float height_scale, - const ai_size width_out, - const ai_size height_out, - const ai_size n_channel, - const ai_bool center); - -/** - * @brief Function to upsample in bilinear mode. - * The number of output channels is the same as the number of input channels. - * Input and output types are signed int16. - * - * @param[in] in_data input data, to be upsampled - * @param[out] out_data upsampled output data - * @param[in] width_in input data width - * @param[in] height_in input data height - * @param[in] width_scale width_out/width_in scale ratio - * @param[in] height_scale height_out/height_in scale ratio - * @param[in] width_out output data width - * @param[in] height_out output data height - * @param[in] center centered coordinates - * @param[in] channel_in input/output channels. - */ -void forward_lite_upsample_bilinear_is16os16(const ai_i16* in_data, - ai_i16* out_data, - const ai_size width_in, - const ai_size height_in, - const ai_float width_scale, - const ai_float height_scale, - const ai_size width_out, - const ai_size height_out, - const ai_size n_channel, - const ai_bool center); - -/** - * @brief Function to upsample in bilinear mode. - * The number of output channels is the same as the number of input channels. - * Input and output types are unsigned int16. - * - * @param[in] in_data input data, to be upsampled - * @param[out] out_data upsampled output data - * @param[in] width_in input data width - * @param[in] height_in input data height - * @param[in] width_scale width_out/width_in scale ratio - * @param[in] height_scale height_out/height_in scale ratio - * @param[in] width_out output data width - * @param[in] height_out output data height - * @param[in] channel_in input/output channels. - * @param[in] center centered coordinates - */ -void forward_lite_upsample_bilinear_iu16ou16(const ai_u16* in_data, - ai_u16* out_data, - const ai_size width_in, - const ai_size height_in, - const ai_float width_scale, - const ai_float height_scale, - const ai_size width_out, - const ai_size height_out, - const ai_size n_channel, - const ai_bool center); - -/** - * @brief Function to upsample in zero mode. - * The number of output channels is the same as the number of input channels. - * Input and output types are singed int8. - * - * @param[in] in_data input data, to be upsampled - * @param[out] out_data upsampled output data - * @param[in] width_in input data width - * @param[in] height_in input data height - * @param[in] width_scale width_out/width_in scale ratio - * @param[in] height_scale height_out/height_in scale ratio - * @param[in] width_out output data width - * @param[in] height_out output data height - * @param[in] channel_in input/output channels. - * @param[in] zero_s8 out zeropoint value - */ -void forward_lite_upsample_zeros_is8os8( const ai_i8 *in_data, - ai_i8 *out_data, - const ai_size width_in, - const ai_size height_in, - const ai_float width_scale, - const ai_float height_scale, - const ai_size width_out, - const ai_size height_out, - const ai_size channel_in, - const ai_i8 zero_s8); - -/** - * @brief Function to upsample in zero mode. - * The number of output channels is the same as the number of input channels. - * Input and output types are signed int16. - * - * @param[in] in_data input data, to be upsampled - * @param[out] out_data upsampled output data - * @param[in] width_in input data width - * @param[in] height_in input data height - * @param[in] width_scale width_out/width_in scale ratio - * @param[in] height_scale height_out/height_in scale ratio - * @param[in] width_out output data width - * @param[in] height_out output data height - * @param[in] channel_in input/output channels. - * @param[in] zero_s16 out zeropoint value - */ -void forward_lite_upsample_zeros_is16os16( const ai_i16 *in_data, - ai_i16 *out_data, - const ai_size width_in, - const ai_size height_in, - const ai_float width_scale, - const ai_float height_scale, - const ai_size channel_in, - const ai_size width_out, - const ai_size height_out, - const ai_i16 zero_s16); - -/** - * @brief Function to upsample in zero mode. - * The number of output channels is the same as the number of input channels. - * Input and output types are float. - * - * @param[in] in_data input data, to be upsampled - * @param[out] out_data upsampled output data - * @param[in] width_in input data width - * @param[in] height_in input data height - * @param[in] width_scale width_out/width_in scale ratio - * @param[in] height_scale height_out/height_in scale ratio - * @param[in] width_out output data width - * @param[in] height_out output data height - * @param[in] channel_in input/output channels. - */ -void forward_lite_upsample_zeros_if32of32( const ai_float *in_data, - ai_float *out_data, - const ai_size width_in, - const ai_size height_in, - const ai_float width_scale, - const ai_float height_scale, - const ai_size channel_in, - const ai_size width_out, - const ai_size height_out); - -#endif /*LITE_UPSAMPLE__H*/ +/** + ****************************************************************************** + * @file lite_upsample.h + * @author AIS + * @brief header file of AI platform lite upsample kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_UPSAMPLE_H +#define LITE_UPSAMPLE_H +#pragma once + +#include "ai_lite_interface.h" + + +/** + * @brief Function to upsample in bilinear mode. + * The number of output channels is the same as the number of input channels. + * Input and output types are float. + * + * @param[in] in_data input data, to be upsampled + * @param[out] out_data upsampled output data + * @param[in] width_in input data width + * @param[in] height_in input data height + * @param[in] width_scale width_out/width_in scale ratio + * @param[in] height_scale height_out/height_in scale ratio + * @param[in] width_out output data width + * @param[in] height_out output data height + * @param[in] channel_in input/output channels. + * @param[in] center centered coordinates + */ +void forward_lite_upsample_bilinear_if32of32(const ai_float* in_data, + ai_float* out_data, + const ai_size width_in, + const ai_size height_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_size n_channel, + const ai_bool center); + +/** + * @brief Function to upsample in bilinear mode. + * The number of output channels is the same as the number of input channels. + * Input and output types are signed int8. + * + * @param[in] in_data input data, to be upsampled + * @param[out] out_data upsampled output data + * @param[in] width_in input data width + * @param[in] height_in input data height + * @param[in] width_scale width_out/width_in scale ratio + * @param[in] height_scale height_out/height_in scale ratio + * @param[in] width_out output data width + * @param[in] height_out output data height + * @param[in] channel_in input/output channels. + * @param[in] center centered coordinates + */ +void forward_lite_upsample_bilinear_is8os8(const ai_i8* in_data, + ai_i8* out_data, + const ai_size width_in, + const ai_size height_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_size n_channel, + const ai_bool center); + +/** + * @brief Function to upsample in bilinear mode. + * The number of output channels is the same as the number of input channels. + * Input and output types are unsinged int8. + * + * @param[in] in_data input data, to be upsampled + * @param[out] out_data upsampled output data + * @param[in] width_in input data width + * @param[in] height_in input data height + * @param[in] width_scale width_out/width_in scale ratio + * @param[in] height_scale height_out/height_in scale ratio + * @param[in] width_out output data width + * @param[in] height_out output data height + * @param[in] channel_in input/output channels. + * @param[in] center centered coordinates + */ +void forward_lite_upsample_bilinear_iu8ou8(const ai_u8* in_data, + ai_u8* out_data, + const ai_size width_in, + const ai_size height_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_size n_channel, + const ai_bool center); + +/** + * @brief Function to upsample in bilinear mode. + * The number of output channels is the same as the number of input channels. + * Input and output types are signed int16. + * + * @param[in] in_data input data, to be upsampled + * @param[out] out_data upsampled output data + * @param[in] width_in input data width + * @param[in] height_in input data height + * @param[in] width_scale width_out/width_in scale ratio + * @param[in] height_scale height_out/height_in scale ratio + * @param[in] width_out output data width + * @param[in] height_out output data height + * @param[in] center centered coordinates + * @param[in] channel_in input/output channels. + */ +void forward_lite_upsample_bilinear_is16os16(const ai_i16* in_data, + ai_i16* out_data, + const ai_size width_in, + const ai_size height_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_size n_channel, + const ai_bool center); + +/** + * @brief Function to upsample in bilinear mode. + * The number of output channels is the same as the number of input channels. + * Input and output types are unsigned int16. + * + * @param[in] in_data input data, to be upsampled + * @param[out] out_data upsampled output data + * @param[in] width_in input data width + * @param[in] height_in input data height + * @param[in] width_scale width_out/width_in scale ratio + * @param[in] height_scale height_out/height_in scale ratio + * @param[in] width_out output data width + * @param[in] height_out output data height + * @param[in] channel_in input/output channels. + * @param[in] center centered coordinates + */ +void forward_lite_upsample_bilinear_iu16ou16(const ai_u16* in_data, + ai_u16* out_data, + const ai_size width_in, + const ai_size height_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_size n_channel, + const ai_bool center); + +/** + * @brief Function to upsample in zero mode. + * The number of output channels is the same as the number of input channels. + * Input and output types are singed int8. + * + * @param[in] in_data input data, to be upsampled + * @param[out] out_data upsampled output data + * @param[in] width_in input data width + * @param[in] height_in input data height + * @param[in] width_scale width_out/width_in scale ratio + * @param[in] height_scale height_out/height_in scale ratio + * @param[in] width_out output data width + * @param[in] height_out output data height + * @param[in] channel_in input/output channels. + * @param[in] zero_s8 out zeropoint value + */ +void forward_lite_upsample_zeros_is8os8( const ai_i8 *in_data, + ai_i8 *out_data, + const ai_size width_in, + const ai_size height_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_size channel_in, + const ai_i8 zero_s8); + +/** + * @brief Function to upsample in zero mode. + * The number of output channels is the same as the number of input channels. + * Input and output types are signed int16. + * + * @param[in] in_data input data, to be upsampled + * @param[out] out_data upsampled output data + * @param[in] width_in input data width + * @param[in] height_in input data height + * @param[in] width_scale width_out/width_in scale ratio + * @param[in] height_scale height_out/height_in scale ratio + * @param[in] width_out output data width + * @param[in] height_out output data height + * @param[in] channel_in input/output channels. + * @param[in] zero_s16 out zeropoint value + */ +void forward_lite_upsample_zeros_is16os16( const ai_i16 *in_data, + ai_i16 *out_data, + const ai_size width_in, + const ai_size height_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size channel_in, + const ai_size width_out, + const ai_size height_out, + const ai_i16 zero_s16); + +/** + * @brief Function to upsample in zero mode. + * The number of output channels is the same as the number of input channels. + * Input and output types are float. + * + * @param[in] in_data input data, to be upsampled + * @param[out] out_data upsampled output data + * @param[in] width_in input data width + * @param[in] height_in input data height + * @param[in] width_scale width_out/width_in scale ratio + * @param[in] height_scale height_out/height_in scale ratio + * @param[in] width_out output data width + * @param[in] height_out output data height + * @param[in] channel_in input/output channels. + */ +void forward_lite_upsample_zeros_if32of32( const ai_float *in_data, + ai_float *out_data, + const ai_size width_in, + const ai_size height_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size channel_in, + const ai_size width_out, + const ai_size height_out); + +#endif /*LITE_UPSAMPLE__H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_upsample_generic.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_upsample_generic.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_upsample_generic.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_upsample_generic.h index f84ba453..fdf32d6e 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/lite_upsample_generic.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/lite_upsample_generic.h @@ -1,58 +1,58 @@ -/** - ****************************************************************************** - * @file lite_upsample.h - * @author AIS - * @brief header file of AI platform lite upsample kernel datatypes - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef LITE_UPSAMPLE_GENERIC_H -#define LITE_UPSAMPLE_GENERIC_H - - -#include "ai_lite_interface.h" - - -void forward_lite_upsample_generic_nearest(const ai_u8* in_data, - ai_u8* out_data, - const ai_size width_in, - const ai_size width_out, - const ai_float width_scale, - const ai_size height_out, - const ai_float height_scale, - const ai_u32 output_tensor_w_stride, - const ai_float offset_round_coeff); - -void forward_lite_upsample_nearest(ai_ptr in_data, - ai_ptr out_data, - const ai_size width_in, - const ai_size height_in, - const ai_float width_scale, - const ai_float height_scale, - const ai_size width_out, - const ai_size height_out, - const ai_ptr_offset stride_w, - const ai_float offset_round_coeff); - -void forward_lite_upsample_zeros( ai_ptr in_data, - ai_ptr out_data, - const ai_size width_in, - const ai_size height_in, - const ai_float width_scale, - const ai_float height_scale, - const ai_size width_out, - const ai_size height_out, - const ai_ptr_offset stride_ch, - const ai_ptr_offset stride_w, - const ai_handle p_zero_value); - -#endif /*LITE_UPSAMPLE_GENERIC_H*/ +/** + ****************************************************************************** + * @file lite_upsample.h + * @author AIS + * @brief header file of AI platform lite upsample kernel datatypes + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef LITE_UPSAMPLE_GENERIC_H +#define LITE_UPSAMPLE_GENERIC_H + + +#include "ai_lite_interface.h" + + +void forward_lite_upsample_generic_nearest(const ai_u8* in_data, + ai_u8* out_data, + const ai_size width_in, + const ai_size width_out, + const ai_float width_scale, + const ai_size height_out, + const ai_float height_scale, + const ai_u32 output_tensor_w_stride, + const ai_float offset_round_coeff); + +void forward_lite_upsample_nearest(ai_ptr in_data, + ai_ptr out_data, + const ai_size width_in, + const ai_size height_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_ptr_offset stride_w, + const ai_float offset_round_coeff); + +void forward_lite_upsample_zeros( ai_ptr in_data, + ai_ptr out_data, + const ai_size width_in, + const ai_size height_in, + const ai_float width_scale, + const ai_float height_scale, + const ai_size width_out, + const ai_size height_out, + const ai_ptr_offset stride_ch, + const ai_ptr_offset stride_w, + const ai_handle p_zero_value); + +#endif /*LITE_UPSAMPLE_GENERIC_H*/ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/stai.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/stai.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/stai.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/stai.h index 15d970ae..a13677f3 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/stai.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/stai.h @@ -1,468 +1,468 @@ -/** - ****************************************************************************** - * @file stai.h - * @author STMicroelectronics - * @brief Definitions of ST.AI platform public APIs types - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef STAI_H -#define STAI_H - -#include -#include - -#define STAI_API_VERSION_MAJOR (1) -#define STAI_API_VERSION_MINOR (0) -#define STAI_API_VERSION_MICRO (0) - -#define STAI_TOOLS_VERSION_MAJOR (1) -#define STAI_TOOLS_VERSION_MINOR (0) -#define STAI_TOOLS_VERSION_MICRO (0) - -/*****************************************************************************/ -#ifdef __cplusplus -#define STAI_API_DECLARE_BEGIN extern "C" { -#define STAI_API_DECLARE_END } -#else -#include -#define STAI_API_DECLARE_BEGIN /* STAI_API_DECLARE_BEGIN */ -#define STAI_API_DECLARE_END /* STAI_API_DECLARE_END */ -#endif - -/*****************************************************************************/ -#define STAI_PACK(...) \ - __VA_ARGS__ - -#define STAI_UNUSED(x) \ - (void)(x); - -#if defined(_MSC_VER) - #define STAI_API_ENTRY __declspec(dllexport) - #define STAI_ALIGNED(x) __declspec(align(x)) -#elif defined(__ICCARM__) || defined (__IAR_SYSTEMS_ICC__) - #define STAI_API_ENTRY /* STAI_API_ENTRY */ - #define STAI_ALIGNED(x) _STAI_ALIGNED_X(x) - #define _STAI_ALIGNED_XY(x, y) x ## y - #define _STAI_ALIGNED_X(x) _STAI_ALIGNED_XY(_STAI_ALIGNED_,x) - #define _STAI_ALIGNED_1 _Pragma("data_alignment = 1") - #define _STAI_ALIGNED_2 _Pragma("data_alignment = 2") - #define _STAI_ALIGNED_4 _Pragma("data_alignment = 4") - #define _STAI_ALIGNED_8 _Pragma("data_alignment = 8") - #define _STAI_ALIGNED_16 _Pragma("data_alignment = 16") - #define _STAI_ALIGNED_32 _Pragma("data_alignment = 32") - #define _STAI_ALIGNED_64 _Pragma("data_alignment = 64") -#elif defined(__CC_ARM) - #define STAI_API_ENTRY __attribute__((visibility("default"))) - #define STAI_ALIGNED(x) __attribute__((aligned (x))) - /* Keil disallows anonymous union initialization by default */ - #pragma anon_unions -#elif defined(__GNUC__) - // #define STAI_API_ENTRY __attribute__((visibility("default"))) - #define STAI_API_ENTRY /* STAI_API_ENTRY */ - #define STAI_ALIGNED(x) __attribute__((aligned(x))) -#else - /* Dynamic libraries are not supported by the compiler */ - #define STAI_API_ENTRY /* STAI_API_ENTRY */ - #define STAI_ALIGNED(x) /* STAI_ALIGNED(x) */ -#endif - - -/*****************************************************************************/ -/*** Formats field getters/setters Macros Section and family enums ***/ - -typedef enum { - STAI_FORMAT_TYPE_NONE = 0x00, - STAI_FORMAT_TYPE_FLOAT = 0x01, - STAI_FORMAT_TYPE_Q = 0x02, - STAI_FORMAT_TYPE_BOOL = 0x03, -} stai_format_type; - -/* Get format type */ -#define STAI_FORMAT_GET_TYPE(format) \ - ((stai_format_type)(((format)>>17) & 0xF)) - -/* Get format sign : 0 or 1 allowed */ -#define STAI_FORMAT_GET_SIGN(format) \ - (((format)>>23) & 0x1) - -/* Get format bits - including sign, fractional bits. padding bits are not included */ -#define STAI_FORMAT_GET_BITS(format) \ - (((format)>>7) & 0x7F) - -/* Get format integer bits, i.e. integer bits are bits minus sign minus fractional bits */ -#define STAI_FORMAT_GET_IBITS(format) \ - (STAI_FORMAT_GET_BITS(format) - STAI_FORMAT_GET_FBITS(format) - STAI_FORMAT_GET_SIGN(format)) - -/* Get format fractional bits */ -#define STAI_FORMAT_GET_FBITS(format) \ - ((((format)>>0) & 0x7F) - 64) - - -/*****************************************************************************/ -#define STAI_NETWORK_CONTEXT_DECLARE(_context_name, _context_size) \ - STAI_ALIGNED(8) \ - stai_network _context_name[_context_size] = {0}; - - -/*****************************************************************************/ -/** I/O FLAGS Section **/ -#define STAI_FLAG_NONE (0x0) - -/* buffer is preallocated by system */ -#define STAI_FLAG_PREALLOCATED (0x1 << 0) - -/* buffer address field `buffer_descriptor::address` may not be used by the user and functions `get_buffer_address()`, - `set_buffer_address()` must be used instead */ -#define STAI_FLAG_INDIRECT (0x1 << 1) - -/* buffer may be replaced by user */ -#define STAI_FLAG_REPLACEABLE (0x1 << 2) - -/* buffer content may be overridden by network */ -#define STAI_FLAG_OVERRIDE (0x1 << 3) - -#define STAI_FLAG_CHANNEL_FIRST (0x1 << 6) -#define STAI_FLAG_CHANNEL_LAST (0x1 << 7) -#define STAI_FLAG_HAS_BATCH (0x1 << 8) - -/** Network FLAGS Section **/ -#define STAI_FLAG_ACTIVATIONS (0x1 << 26) -#define STAI_FLAG_INPUTS (0x1 << 27) -#define STAI_FLAG_OUTPUTS (0x1 << 28) -#define STAI_FLAG_STATES (0x1 << 29) -#define STAI_FLAG_WEIGHTS (0x1 << 30) - - -/*****************************************************************************/ -STAI_API_DECLARE_BEGIN - -/* STAI Enums Section */ -/* return codes >= STAI_ERROR_GENERIC are errors. - all codes < STAI_ERROR_GENERIC are available for managing extended set of implementation specific return codes - APIs track only 1 error: the 1st one generated while calling the APIs. No multiple error handling considered. - NOTE: need also to provide proper handling of a new return code in stai_get_return_code_name() implementation. -*/ -typedef enum { - STAI_SUCCESS = 0x000000, - STAI_RUNNING_NO_WFE = 0x000010, - STAI_RUNNING_WFE = 0x000011, - STAI_DONE = 0x000012, - STAI_ERROR_GENERIC = 0x020000, - STAI_ERROR_NETWORK_INVALID_API_ARGUMENTS = 0x020001, - STAI_ERROR_NETWORK_INVALID_CONTEXT_HANDLE = 0x030000, - STAI_ERROR_NETWORK_INVALID_CONTEXT_SIZE = 0x030001, - STAI_ERROR_NETWORK_INVALID_CONTEXT_ALIGNMENT = 0x030002, - STAI_ERROR_NETWORK_INVALID_INFO = 0x030010, - STAI_ERROR_NETWORK_INVALID_RUN = 0x030020, - STAI_ERROR_NETWORK_INVALID_RUNTIME = 0x030030, - STAI_ERROR_NETWORK_INVALID_ACTIVATIONS_PTR = 0x040000, - STAI_ERROR_NETWORK_INVALID_ACTIVATIONS_NUM = 0x040001, - STAI_ERROR_NETWORK_INVALID_IN_PTR = 0x040010, - STAI_ERROR_NETWORK_INVALID_IN_NUM = 0x040011, - STAI_ERROR_NETWORK_INVALID_OUT_PTR = 0x040020, - STAI_ERROR_NETWORK_INVALID_OUT_NUM = 0x040021, - STAI_ERROR_NETWORK_INVALID_STATES_PTR = 0x040030, - STAI_ERROR_NETWORK_INVALID_STATES_NUM = 0x040031, - STAI_ERROR_NETWORK_INVALID_WEIGHTS_PTR = 0x040040, - STAI_ERROR_NETWORK_INVALID_WEIGHTS_NUM = 0x040041, - STAI_ERROR_NETWORK_INVALID_CALLBACK = 0x040050, - STAI_ERROR_NOT_IMPLEMENTED = 0x040060, - STAI_ERROR_INVALID_BUFFER_ALIGNMENT = 0x040070, - - /* asynchronous execution errors */ - STAI_ERROR_NETWORK_STILL_RUNNING = 0x050000, - - /* platform (de-)init errors */ - STAI_ERROR_STAI_INIT_FAILED = 0x060000, - STAI_ERROR_STAI_DEINIT_FAILED = 0x060001, -} stai_return_code; - - -/*! - * @enum buffer formats enum list - * @ingroup ai_platform - * - * List of supported ai_buffer format types. - */ -typedef enum { - STAI_FORMAT_NONE = 0x00000040, - - STAI_FORMAT_FLOAT32 = 0x01821040, - STAI_FORMAT_FLOAT64 = 0x01822040, - - STAI_FORMAT_U1 = 0x000400c0, - STAI_FORMAT_U8 = 0x00040440, - STAI_FORMAT_U16 = 0x00040840, - STAI_FORMAT_U32 = 0x00041040, - STAI_FORMAT_U64 = 0x00042040, - - STAI_FORMAT_S1 = 0x008400c0, - STAI_FORMAT_S8 = 0x00840440, - STAI_FORMAT_S16 = 0x00840840, - STAI_FORMAT_S32 = 0x00841040, - STAI_FORMAT_S64 = 0x00842040, - - STAI_FORMAT_Q = 0x00840040, - STAI_FORMAT_Q7 = 0x00840447, - STAI_FORMAT_Q15 = 0x0084084f, - - STAI_FORMAT_UQ = 0x00040040, - STAI_FORMAT_UQ7 = 0x00040447, - STAI_FORMAT_UQ15 = 0x0004084f, - - STAI_FORMAT_BOOL = 0x00060440, -} stai_format; - - -typedef enum { - STAI_MODE_SYNC = 0x01, - STAI_MODE_ASYNC = 0x02, -} stai_run_mode; - - -/*****************************************************************************/ - -/* 32bit mask to code flags about e.g. I/O buffers or network properties */ -typedef int32_t stai_flags; - - -/* Opaque network handler exposed to application */ -/* it is defined as int8 to allow static memory allocation of context on app side - as an opaque uint8_t byte buffer to ensure alignment to 8 bytes */ -typedef uint8_t stai_network; - -/* Generic byte pointer for byte offset addressing */ -typedef uint8_t* stai_ptr; - -/* Generic type size */ -typedef uint32_t stai_size; - -/* Packed bits arrays are padded to 32bits */ -typedef int32_t stai_pbits; - - -/*****************************************************************************/ -typedef struct { - stai_size size; - stai_ptr const * data; -} stai_array_const_ptr; - -typedef struct { - stai_size size; - stai_ptr* data; -} stai_array_ptr; - - -typedef struct { - stai_size size; - const float* data; -} stai_array_f32; - - -typedef struct { - stai_size size; - const int8_t* data; -} stai_array_s8; - - -typedef struct { - stai_size size; - const uint8_t* data; -} stai_array_u8; - - -typedef struct { - stai_size size; - const int16_t* data; -} stai_array_s16; - - -typedef struct { - stai_size size; - const uint16_t* data; -} stai_array_u16; - - -typedef struct { - stai_size size; - const int32_t* data; -} stai_array_s32; - - -typedef struct { - stai_size size; - const uint32_t* data; -} stai_array_u32; - - -typedef struct { - uint8_t major; - uint8_t minor; - uint8_t micro; - uint8_t reserved; -} stai_version; - - -typedef stai_array_s32 stai_shape; - - -typedef struct { - stai_size size; - uintptr_t address; - stai_flags flags; - // stai_format format; -} stai_buffer; - - -typedef struct { - stai_size size_bytes; - stai_flags flags; - stai_format format; - stai_shape shape; - stai_array_f32 scale; - stai_array_s16 zeropoint; - const char* name; -} stai_tensor; - - -/*****************************************************************************/ -typedef struct { - /* Original model signature */ - const char* model_signature; - - /* C generated model info */ - const char* c_compile_datetime; - const char* c_model_name; - const char* c_model_datetime; - uint32_t c_model_signature; - - stai_version runtime_version; - stai_version tool_version; - stai_version api_version; - - /* C model macc operations */ - uint64_t n_macc; - - /* C model graph nodes */ - uint32_t n_nodes; - - /* C model flags */ - int32_t flags; - - /* Number of c model network I/O, Activations, Weights, States */ - uint16_t n_inputs; - uint16_t n_outputs; - uint16_t n_activations; - uint16_t n_weights; - uint16_t n_states; - - /* I/O networks tensors c_model info (as arrays of size n_inputs/n)outputs */ - const stai_tensor* inputs; - const stai_tensor* outputs; - - /* Activations, weights, states info */ - const stai_tensor* activations; - const stai_tensor* weights; - const stai_tensor* states; -} stai_network_info; - - -/*****************************************************************************/ -/* C struct used in file network_details.h to provide info about a node */ -typedef struct { - const int32_t id; - const int16_t type; - const stai_array_s32 input_tensors; - const stai_array_s32 output_tensors; -} stai_node_details; - - -/*****************************************************************************/ -/* C struct used in file network_details.h to provide info about the network */ -typedef struct { - const stai_tensor * const tensors; - const stai_node_details * const nodes; - const uint32_t n_nodes; -} stai_network_details; - - -/* C enum to list supported compilers */ -typedef enum { - STAI_COMPILER_ID_NONE = 0x00, - STAI_COMPILER_ID_GCC = 0x01, - STAI_COMPILER_ID_GHS = 0x10, - STAI_COMPILER_ID_HIGHTECH = 0x20, - STAI_COMPILER_ID_IAR = 0x30, - STAI_COMPILER_ID_KEIL = 0x40, - STAI_COMPILER_ID_KEIL_AC6 = 0x50, -} stai_compiler_id; - - -/* C struct to provide info about ST.AI C runtime */ -typedef struct { - stai_version api_version; /* X.Y.Z version of the ST Edge AI APIs */ - stai_version runtime_version; /* X.Y.Z version of the runtime */ - stai_version tools_version; /* version of the tool compatible with the run-time */ - uint32_t runtime_build; /* 32bit run-time identifier (i.e. build info) */ - stai_compiler_id compiler_id; /* compiler ID enum */ - const char* compiler_desc; /* string with a short description of the compiler */ -} stai_runtime_info; - - -/*****************************************************************************/ -/** STAI event callback and datatypes definition **/ - -#define STAI_EVENT_NONE (0x00) - -typedef int32_t stai_event_type; - -/** - * This is the generic network event callback signature - * @param cb_cookie is the opaque handler provided by caller (i.e. the application) - * @param event_type is the unique event type identifier - * @param event is the the opaque handler to event payload struct (Optional, may be NULL) - **/ -typedef void (*stai_event_cb)( - void* cb_cookie, - const stai_event_type event_type, - const void* event_payload); - - -/*****************************************************************************/ -/** ST.AI Runtime APIs section **/ -/** Initialize ST Edge AI runtime **/ -STAI_API_ENTRY -stai_return_code stai_runtime_init(void); - -/** De-initialize ST Edge AI runtime **/ -STAI_API_ENTRY -stai_return_code stai_runtime_deinit(void); - -/** Get ST Edge AI runtime info (versions, build, compiler, etc.) **/ -STAI_API_ENTRY -stai_return_code stai_runtime_get_info(stai_runtime_info* info); - -/** Set ST Edge AI runtime callback **/ -STAI_API_ENTRY -stai_return_code stai_runtime_set_callback(const stai_event_cb cb, void *cb_cookie); - -/*****************************************************************************/ -/** Helpers routines **/ -/** Helper API to generate a stai_format enum with provided info **/ -STAI_API_ENTRY -stai_format stai_init_format( - const stai_format_type type, const int8_t sign, const int32_t bits, const int32_t fbits); - -STAI_API_DECLARE_END - -#endif /* STAI_H */ +/** + ****************************************************************************** + * @file stai.h + * @author STMicroelectronics + * @brief Definitions of ST.AI platform public APIs types + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef STAI_H +#define STAI_H + +#include +#include + +#define STAI_API_VERSION_MAJOR (1) +#define STAI_API_VERSION_MINOR (0) +#define STAI_API_VERSION_MICRO (0) + +#define STAI_TOOLS_VERSION_MAJOR (1) +#define STAI_TOOLS_VERSION_MINOR (0) +#define STAI_TOOLS_VERSION_MICRO (0) + +/*****************************************************************************/ +#ifdef __cplusplus +#define STAI_API_DECLARE_BEGIN extern "C" { +#define STAI_API_DECLARE_END } +#else +#include +#define STAI_API_DECLARE_BEGIN /* STAI_API_DECLARE_BEGIN */ +#define STAI_API_DECLARE_END /* STAI_API_DECLARE_END */ +#endif + +/*****************************************************************************/ +#define STAI_PACK(...) \ + __VA_ARGS__ + +#define STAI_UNUSED(x) \ + (void)(x); + +#if defined(_MSC_VER) + #define STAI_API_ENTRY __declspec(dllexport) + #define STAI_ALIGNED(x) __declspec(align(x)) +#elif defined(__ICCARM__) || defined (__IAR_SYSTEMS_ICC__) + #define STAI_API_ENTRY /* STAI_API_ENTRY */ + #define STAI_ALIGNED(x) _STAI_ALIGNED_X(x) + #define _STAI_ALIGNED_XY(x, y) x ## y + #define _STAI_ALIGNED_X(x) _STAI_ALIGNED_XY(_STAI_ALIGNED_,x) + #define _STAI_ALIGNED_1 _Pragma("data_alignment = 1") + #define _STAI_ALIGNED_2 _Pragma("data_alignment = 2") + #define _STAI_ALIGNED_4 _Pragma("data_alignment = 4") + #define _STAI_ALIGNED_8 _Pragma("data_alignment = 8") + #define _STAI_ALIGNED_16 _Pragma("data_alignment = 16") + #define _STAI_ALIGNED_32 _Pragma("data_alignment = 32") + #define _STAI_ALIGNED_64 _Pragma("data_alignment = 64") +#elif defined(__CC_ARM) + #define STAI_API_ENTRY __attribute__((visibility("default"))) + #define STAI_ALIGNED(x) __attribute__((aligned (x))) + /* Keil disallows anonymous union initialization by default */ + #pragma anon_unions +#elif defined(__GNUC__) + // #define STAI_API_ENTRY __attribute__((visibility("default"))) + #define STAI_API_ENTRY /* STAI_API_ENTRY */ + #define STAI_ALIGNED(x) __attribute__((aligned(x))) +#else + /* Dynamic libraries are not supported by the compiler */ + #define STAI_API_ENTRY /* STAI_API_ENTRY */ + #define STAI_ALIGNED(x) /* STAI_ALIGNED(x) */ +#endif + + +/*****************************************************************************/ +/*** Formats field getters/setters Macros Section and family enums ***/ + +typedef enum { + STAI_FORMAT_TYPE_NONE = 0x00, + STAI_FORMAT_TYPE_FLOAT = 0x01, + STAI_FORMAT_TYPE_Q = 0x02, + STAI_FORMAT_TYPE_BOOL = 0x03, +} stai_format_type; + +/* Get format type */ +#define STAI_FORMAT_GET_TYPE(format) \ + ((stai_format_type)(((format)>>17) & 0xF)) + +/* Get format sign : 0 or 1 allowed */ +#define STAI_FORMAT_GET_SIGN(format) \ + (((format)>>23) & 0x1) + +/* Get format bits - including sign, fractional bits. padding bits are not included */ +#define STAI_FORMAT_GET_BITS(format) \ + (((format)>>7) & 0x7F) + +/* Get format integer bits, i.e. integer bits are bits minus sign minus fractional bits */ +#define STAI_FORMAT_GET_IBITS(format) \ + (STAI_FORMAT_GET_BITS(format) - STAI_FORMAT_GET_FBITS(format) - STAI_FORMAT_GET_SIGN(format)) + +/* Get format fractional bits */ +#define STAI_FORMAT_GET_FBITS(format) \ + ((((format)>>0) & 0x7F) - 64) + + +/*****************************************************************************/ +#define STAI_NETWORK_CONTEXT_DECLARE(_context_name, _context_size) \ + STAI_ALIGNED(8) \ + stai_network _context_name[_context_size] = {0}; + + +/*****************************************************************************/ +/** I/O FLAGS Section **/ +#define STAI_FLAG_NONE (0x0) + +/* buffer is preallocated by system */ +#define STAI_FLAG_PREALLOCATED (0x1 << 0) + +/* buffer address field `buffer_descriptor::address` may not be used by the user and functions `get_buffer_address()`, + `set_buffer_address()` must be used instead */ +#define STAI_FLAG_INDIRECT (0x1 << 1) + +/* buffer may be replaced by user */ +#define STAI_FLAG_REPLACEABLE (0x1 << 2) + +/* buffer content may be overridden by network */ +#define STAI_FLAG_OVERRIDE (0x1 << 3) + +#define STAI_FLAG_CHANNEL_FIRST (0x1 << 6) +#define STAI_FLAG_CHANNEL_LAST (0x1 << 7) +#define STAI_FLAG_HAS_BATCH (0x1 << 8) + +/** Network FLAGS Section **/ +#define STAI_FLAG_ACTIVATIONS (0x1 << 26) +#define STAI_FLAG_INPUTS (0x1 << 27) +#define STAI_FLAG_OUTPUTS (0x1 << 28) +#define STAI_FLAG_STATES (0x1 << 29) +#define STAI_FLAG_WEIGHTS (0x1 << 30) + + +/*****************************************************************************/ +STAI_API_DECLARE_BEGIN + +/* STAI Enums Section */ +/* return codes >= STAI_ERROR_GENERIC are errors. + all codes < STAI_ERROR_GENERIC are available for managing extended set of implementation specific return codes + APIs track only 1 error: the 1st one generated while calling the APIs. No multiple error handling considered. + NOTE: need also to provide proper handling of a new return code in stai_get_return_code_name() implementation. +*/ +typedef enum { + STAI_SUCCESS = 0x000000, + STAI_RUNNING_NO_WFE = 0x000010, + STAI_RUNNING_WFE = 0x000011, + STAI_DONE = 0x000012, + STAI_ERROR_GENERIC = 0x020000, + STAI_ERROR_NETWORK_INVALID_API_ARGUMENTS = 0x020001, + STAI_ERROR_NETWORK_INVALID_CONTEXT_HANDLE = 0x030000, + STAI_ERROR_NETWORK_INVALID_CONTEXT_SIZE = 0x030001, + STAI_ERROR_NETWORK_INVALID_CONTEXT_ALIGNMENT = 0x030002, + STAI_ERROR_NETWORK_INVALID_INFO = 0x030010, + STAI_ERROR_NETWORK_INVALID_RUN = 0x030020, + STAI_ERROR_NETWORK_INVALID_RUNTIME = 0x030030, + STAI_ERROR_NETWORK_INVALID_ACTIVATIONS_PTR = 0x040000, + STAI_ERROR_NETWORK_INVALID_ACTIVATIONS_NUM = 0x040001, + STAI_ERROR_NETWORK_INVALID_IN_PTR = 0x040010, + STAI_ERROR_NETWORK_INVALID_IN_NUM = 0x040011, + STAI_ERROR_NETWORK_INVALID_OUT_PTR = 0x040020, + STAI_ERROR_NETWORK_INVALID_OUT_NUM = 0x040021, + STAI_ERROR_NETWORK_INVALID_STATES_PTR = 0x040030, + STAI_ERROR_NETWORK_INVALID_STATES_NUM = 0x040031, + STAI_ERROR_NETWORK_INVALID_WEIGHTS_PTR = 0x040040, + STAI_ERROR_NETWORK_INVALID_WEIGHTS_NUM = 0x040041, + STAI_ERROR_NETWORK_INVALID_CALLBACK = 0x040050, + STAI_ERROR_NOT_IMPLEMENTED = 0x040060, + STAI_ERROR_INVALID_BUFFER_ALIGNMENT = 0x040070, + + /* asynchronous execution errors */ + STAI_ERROR_NETWORK_STILL_RUNNING = 0x050000, + + /* platform (de-)init errors */ + STAI_ERROR_STAI_INIT_FAILED = 0x060000, + STAI_ERROR_STAI_DEINIT_FAILED = 0x060001, +} stai_return_code; + + +/*! + * @enum buffer formats enum list + * @ingroup ai_platform + * + * List of supported ai_buffer format types. + */ +typedef enum { + STAI_FORMAT_NONE = 0x00000040, + + STAI_FORMAT_FLOAT32 = 0x01821040, + STAI_FORMAT_FLOAT64 = 0x01822040, + + STAI_FORMAT_U1 = 0x000400c0, + STAI_FORMAT_U8 = 0x00040440, + STAI_FORMAT_U16 = 0x00040840, + STAI_FORMAT_U32 = 0x00041040, + STAI_FORMAT_U64 = 0x00042040, + + STAI_FORMAT_S1 = 0x008400c0, + STAI_FORMAT_S8 = 0x00840440, + STAI_FORMAT_S16 = 0x00840840, + STAI_FORMAT_S32 = 0x00841040, + STAI_FORMAT_S64 = 0x00842040, + + STAI_FORMAT_Q = 0x00840040, + STAI_FORMAT_Q7 = 0x00840447, + STAI_FORMAT_Q15 = 0x0084084f, + + STAI_FORMAT_UQ = 0x00040040, + STAI_FORMAT_UQ7 = 0x00040447, + STAI_FORMAT_UQ15 = 0x0004084f, + + STAI_FORMAT_BOOL = 0x00060440, +} stai_format; + + +typedef enum { + STAI_MODE_SYNC = 0x01, + STAI_MODE_ASYNC = 0x02, +} stai_run_mode; + + +/*****************************************************************************/ + +/* 32bit mask to code flags about e.g. I/O buffers or network properties */ +typedef int32_t stai_flags; + + +/* Opaque network handler exposed to application */ +/* it is defined as int8 to allow static memory allocation of context on app side + as an opaque uint8_t byte buffer to ensure alignment to 8 bytes */ +typedef uint8_t stai_network; + +/* Generic byte pointer for byte offset addressing */ +typedef uint8_t* stai_ptr; + +/* Generic type size */ +typedef uint32_t stai_size; + +/* Packed bits arrays are padded to 32bits */ +typedef int32_t stai_pbits; + + +/*****************************************************************************/ +typedef struct { + stai_size size; + stai_ptr const * data; +} stai_array_const_ptr; + +typedef struct { + stai_size size; + stai_ptr* data; +} stai_array_ptr; + + +typedef struct { + stai_size size; + const float* data; +} stai_array_f32; + + +typedef struct { + stai_size size; + const int8_t* data; +} stai_array_s8; + + +typedef struct { + stai_size size; + const uint8_t* data; +} stai_array_u8; + + +typedef struct { + stai_size size; + const int16_t* data; +} stai_array_s16; + + +typedef struct { + stai_size size; + const uint16_t* data; +} stai_array_u16; + + +typedef struct { + stai_size size; + const int32_t* data; +} stai_array_s32; + + +typedef struct { + stai_size size; + const uint32_t* data; +} stai_array_u32; + + +typedef struct { + uint8_t major; + uint8_t minor; + uint8_t micro; + uint8_t reserved; +} stai_version; + + +typedef stai_array_s32 stai_shape; + + +typedef struct { + stai_size size; + uintptr_t address; + stai_flags flags; + // stai_format format; +} stai_buffer; + + +typedef struct { + stai_size size_bytes; + stai_flags flags; + stai_format format; + stai_shape shape; + stai_array_f32 scale; + stai_array_s16 zeropoint; + const char* name; +} stai_tensor; + + +/*****************************************************************************/ +typedef struct { + /* Original model signature */ + const char* model_signature; + + /* C generated model info */ + const char* c_compile_datetime; + const char* c_model_name; + const char* c_model_datetime; + uint32_t c_model_signature; + + stai_version runtime_version; + stai_version tool_version; + stai_version api_version; + + /* C model macc operations */ + uint64_t n_macc; + + /* C model graph nodes */ + uint32_t n_nodes; + + /* C model flags */ + int32_t flags; + + /* Number of c model network I/O, Activations, Weights, States */ + uint16_t n_inputs; + uint16_t n_outputs; + uint16_t n_activations; + uint16_t n_weights; + uint16_t n_states; + + /* I/O networks tensors c_model info (as arrays of size n_inputs/n)outputs */ + const stai_tensor* inputs; + const stai_tensor* outputs; + + /* Activations, weights, states info */ + const stai_tensor* activations; + const stai_tensor* weights; + const stai_tensor* states; +} stai_network_info; + + +/*****************************************************************************/ +/* C struct used in file network_details.h to provide info about a node */ +typedef struct { + const int32_t id; + const int16_t type; + const stai_array_s32 input_tensors; + const stai_array_s32 output_tensors; +} stai_node_details; + + +/*****************************************************************************/ +/* C struct used in file network_details.h to provide info about the network */ +typedef struct { + const stai_tensor * const tensors; + const stai_node_details * const nodes; + const uint32_t n_nodes; +} stai_network_details; + + +/* C enum to list supported compilers */ +typedef enum { + STAI_COMPILER_ID_NONE = 0x00, + STAI_COMPILER_ID_GCC = 0x01, + STAI_COMPILER_ID_GHS = 0x10, + STAI_COMPILER_ID_HIGHTECH = 0x20, + STAI_COMPILER_ID_IAR = 0x30, + STAI_COMPILER_ID_KEIL = 0x40, + STAI_COMPILER_ID_KEIL_AC6 = 0x50, +} stai_compiler_id; + + +/* C struct to provide info about ST.AI C runtime */ +typedef struct { + stai_version api_version; /* X.Y.Z version of the ST Edge AI APIs */ + stai_version runtime_version; /* X.Y.Z version of the runtime */ + stai_version tools_version; /* version of the tool compatible with the run-time */ + uint32_t runtime_build; /* 32bit run-time identifier (i.e. build info) */ + stai_compiler_id compiler_id; /* compiler ID enum */ + const char* compiler_desc; /* string with a short description of the compiler */ +} stai_runtime_info; + + +/*****************************************************************************/ +/** STAI event callback and datatypes definition **/ + +#define STAI_EVENT_NONE (0x00) + +typedef int32_t stai_event_type; + +/** + * This is the generic network event callback signature + * @param cb_cookie is the opaque handler provided by caller (i.e. the application) + * @param event_type is the unique event type identifier + * @param event is the the opaque handler to event payload struct (Optional, may be NULL) + **/ +typedef void (*stai_event_cb)( + void* cb_cookie, + const stai_event_type event_type, + const void* event_payload); + + +/*****************************************************************************/ +/** ST.AI Runtime APIs section **/ +/** Initialize ST Edge AI runtime **/ +STAI_API_ENTRY +stai_return_code stai_runtime_init(void); + +/** De-initialize ST Edge AI runtime **/ +STAI_API_ENTRY +stai_return_code stai_runtime_deinit(void); + +/** Get ST Edge AI runtime info (versions, build, compiler, etc.) **/ +STAI_API_ENTRY +stai_return_code stai_runtime_get_info(stai_runtime_info* info); + +/** Set ST Edge AI runtime callback **/ +STAI_API_ENTRY +stai_return_code stai_runtime_set_callback(const stai_event_cb cb, void *cb_cookie); + +/*****************************************************************************/ +/** Helpers routines **/ +/** Helper API to generate a stai_format enum with provided info **/ +STAI_API_ENTRY +stai_format stai_init_format( + const stai_format_type type, const int8_t sign, const int32_t bits, const int32_t fbits); + +STAI_API_DECLARE_END + +#endif /* STAI_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/stai_debug.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/stai_debug.h similarity index 96% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/stai_debug.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/stai_debug.h index c24ef6c7..50cb3fbf 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/stai_debug.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/stai_debug.h @@ -1,65 +1,65 @@ -/** - ****************************************************************************** - * @file stai_debug.h - * @author STMicroelectronics - * @brief Definitions of ST.AI platform public APIs types - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef STAI_DEBUG_H -#define STAI_DEBUG_H - -#include "stai.h" - -/*****************************************************************************/ -#ifdef HAS_AI_ASSERT -// Override __FILE__ macro to disable full path asserts() -// Need to add during build also -Wbuiltin-macro-redefined options to avoid warnings -#undef __FILE__ -#define __FILE__ (__builtin_strrchr("/" __BASE_FILE__, '/') + 1) - -#include - -#define STAI_ASSERT(_cond) \ - do { assert(_cond); } while(0); - -#else - -#define STAI_ASSERT(_cond) \ - do { /* STAI_ASSERT() */ } while (0); - -#endif /* HAS_AI_ASSERT */ - -#define STAI_PRINT(_fmt, ...) \ - do { /* STAI_PRINT() */ } while (0); - - -STAI_API_DECLARE_BEGIN - - -/*****************************************************************************/ - -STAI_API_ENTRY -const char* stai_get_return_code_name(const stai_return_code code); - - -STAI_API_ENTRY -const char* stai_get_format_type_name(const stai_format_type fmt_type); - - -STAI_API_ENTRY -const char* stai_get_format_name(const stai_format fmt); - - -STAI_API_DECLARE_END - -#endif /* STAI_DEBUG_H */ +/** + ****************************************************************************** + * @file stai_debug.h + * @author STMicroelectronics + * @brief Definitions of ST.AI platform public APIs types + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef STAI_DEBUG_H +#define STAI_DEBUG_H + +#include "stai.h" + +/*****************************************************************************/ +#ifdef HAS_AI_ASSERT +// Override __FILE__ macro to disable full path asserts() +// Need to add during build also -Wbuiltin-macro-redefined options to avoid warnings +#undef __FILE__ +#define __FILE__ (__builtin_strrchr("/" __BASE_FILE__, '/') + 1) + +#include + +#define STAI_ASSERT(_cond) \ + do { assert(_cond); } while(0); + +#else + +#define STAI_ASSERT(_cond) \ + do { /* STAI_ASSERT() */ } while (0); + +#endif /* HAS_AI_ASSERT */ + +#define STAI_PRINT(_fmt, ...) \ + do { /* STAI_PRINT() */ } while (0); + + +STAI_API_DECLARE_BEGIN + + +/*****************************************************************************/ + +STAI_API_ENTRY +const char* stai_get_return_code_name(const stai_return_code code); + + +STAI_API_ENTRY +const char* stai_get_format_type_name(const stai_format_type fmt_type); + + +STAI_API_ENTRY +const char* stai_get_format_name(const stai_format fmt); + + +STAI_API_DECLARE_END + +#endif /* STAI_DEBUG_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/stai_events.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/stai_events.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/stai_events.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/stai_events.h index a4feecbf..24514298 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Inc/stai_events.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Inc/stai_events.h @@ -1,51 +1,51 @@ -/** - ****************************************************************************** - * @file stai_events.h - * @author AST Embedded Analytics Research Platform - * @brief Definitions of ST.AI registered events - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#ifndef STAI_EVENTS_H -#define STAI_EVENTS_H -#include "stai.h" - - -STAI_API_DECLARE_BEGIN - -/*****************************************************************************/ -/** STAI event IDs definition - * This is the list of stai supported events that could be triggered by network - * callback. Each event has an associated datastruct that provides the payload - * for a give event. All supported payloads are defined int the @ref stai_event union. - * New events could be defined by: - * 1) Add a new entry in stai_event_type with unique type id - * 2) Add a new datastruct definition fpr the new event that specified its payload - * 3) Add a pointer to this payload into stai_event union to make it public - **/ -#define STAI_EVENT_NODE_START (0x01) -#define STAI_EVENT_NODE_STOP (0x02) - - -/*****************************************************************************/ -/** STAI events definitions - * ADD YOUR EVENT HERE AND ADD TO STAI_EVENT if public - **/ -typedef struct { - int32_t node_id; - stai_array_const_ptr buffers; -} stai_event_node_start_stop; - - -STAI_API_DECLARE_END - -#endif /* STAI_EVENTS_H */ +/** + ****************************************************************************** + * @file stai_events.h + * @author AST Embedded Analytics Research Platform + * @brief Definitions of ST.AI registered events + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef STAI_EVENTS_H +#define STAI_EVENTS_H +#include "stai.h" + + +STAI_API_DECLARE_BEGIN + +/*****************************************************************************/ +/** STAI event IDs definition + * This is the list of stai supported events that could be triggered by network + * callback. Each event has an associated datastruct that provides the payload + * for a give event. All supported payloads are defined int the @ref stai_event union. + * New events could be defined by: + * 1) Add a new entry in stai_event_type with unique type id + * 2) Add a new datastruct definition fpr the new event that specified its payload + * 3) Add a pointer to this payload into stai_event union to make it public + **/ +#define STAI_EVENT_NODE_START (0x01) +#define STAI_EVENT_NODE_STOP (0x02) + + +/*****************************************************************************/ +/** STAI events definitions + * ADD YOUR EVENT HERE AND ADD TO STAI_EVENT if public + **/ +typedef struct { + int32_t node_id; + stai_array_const_ptr buffers; +} stai_event_node_start_stop; + + +STAI_API_DECLARE_END + +#endif /* STAI_EVENTS_H */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/LICENSE.txt b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/LICENSE.txt similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/LICENSE.txt rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/LICENSE.txt diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Lib/NetworkRuntime910_CM4_GCC.a b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Lib/NetworkRuntime910_CM4_GCC.a similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Middlewares/ST/AI/Lib/NetworkRuntime910_CM4_GCC.a rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/Middlewares/ST/AI/Lib/NetworkRuntime910_CM4_GCC.a diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/STM32L4R5ZITX_FLASH.ld b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/STM32L4R5ZITX_FLASH.ld similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/STM32L4R5ZITX_FLASH.ld rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/STM32L4R5ZITX_FLASH.ld diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/STM32L4R5ZITX_RAM.ld b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/STM32L4R5ZITX_RAM.ld similarity index 98% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/STM32L4R5ZITX_RAM.ld rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/STM32L4R5ZITX_RAM.ld index 9f2ae87f..390f6d32 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/STM32L4R5ZITX_RAM.ld +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/STM32L4R5ZITX_RAM.ld @@ -40,8 +40,8 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ +_Min_Heap_Size = 0x800; /* required amount of heap */ +_Min_Stack_Size = 0x800; /* required amount of stack */ /* Memories definition */ MEMORY diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model.c b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model.c similarity index 59% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model.c rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model.c index 8b49c4a0..b13b0c91 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model.c +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model.c @@ -2,7 +2,7 @@ ****************************************************************************** * @file sww_model.c * @author AST Embedded Analytics Research Platform - * @date 2025-01-19T06:26:52-0500 + * @date 2025-05-22T12:16:33-0700 * @brief AI Tool Automatic Code Generator for Embedded NN computing ****************************************************************************** * @attention @@ -35,14 +35,14 @@ #define AI_NET_OBJ_INSTANCE g_sww_model #undef AI_SWW_MODEL_MODEL_SIGNATURE -#define AI_SWW_MODEL_MODEL_SIGNATURE "0x11c3f8bb3c26578a427b600d2c3795e0" +#define AI_SWW_MODEL_MODEL_SIGNATURE "0x9643512e0b8a0b6e643e70c2fec496ee" #ifndef AI_TOOLS_REVISION_ID #define AI_TOOLS_REVISION_ID "" #endif #undef AI_TOOLS_DATE_TIME -#define AI_TOOLS_DATE_TIME "2025-01-19T06:26:52-0500" +#define AI_TOOLS_DATE_TIME "2025-05-22T12:16:33-0700" #undef AI_TOOLS_COMPILE_TIME #define AI_TOOLS_COMPILE_TIME __DATE__ " " __TIME__ @@ -69,32 +69,32 @@ AI_ARRAY_OBJ_DECLARE( /* Array#2 */ AI_ARRAY_OBJ_DECLARE( conv2d_1_output_array, AI_ARRAY_FORMAT_S8, - NULL, NULL, 3024, AI_STATIC) + NULL, NULL, 3584, AI_STATIC) /* Array#3 */ AI_ARRAY_OBJ_DECLARE( conv2d_2_output_array, AI_ARRAY_FORMAT_S8, - NULL, NULL, 2592, AI_STATIC) + NULL, NULL, 3072, AI_STATIC) /* Array#4 */ AI_ARRAY_OBJ_DECLARE( conv2d_3_output_array, AI_ARRAY_FORMAT_S8, - NULL, NULL, 1944, AI_STATIC) + NULL, NULL, 3072, AI_STATIC) /* Array#5 */ AI_ARRAY_OBJ_DECLARE( conv2d_4_output_array, AI_ARRAY_FORMAT_S8, - NULL, NULL, 1215, AI_STATIC) + NULL, NULL, 1920, AI_STATIC) /* Array#6 */ AI_ARRAY_OBJ_DECLARE( conv2d_5_output_array, AI_ARRAY_FORMAT_S8, - NULL, NULL, 780, AI_STATIC) + NULL, NULL, 1920, AI_STATIC) /* Array#7 */ AI_ARRAY_OBJ_DECLARE( conv2d_6_output_array, AI_ARRAY_FORMAT_S8, - NULL, NULL, 52, AI_STATIC) + NULL, NULL, 128, AI_STATIC) /* Array#8 */ AI_ARRAY_OBJ_DECLARE( @@ -124,67 +124,67 @@ AI_ARRAY_OBJ_DECLARE( /* Array#13 */ AI_ARRAY_OBJ_DECLARE( conv2d_1_weights_array, AI_ARRAY_FORMAT_S8, - NULL, NULL, 4320, AI_STATIC) + NULL, NULL, 5120, AI_STATIC) /* Array#14 */ AI_ARRAY_OBJ_DECLARE( conv2d_1_bias_array, AI_ARRAY_FORMAT_S32, - NULL, NULL, 108, AI_STATIC) + NULL, NULL, 128, AI_STATIC) /* Array#15 */ AI_ARRAY_OBJ_DECLARE( conv2d_2_weights_array, AI_ARRAY_FORMAT_S8, - NULL, NULL, 540, AI_STATIC) + NULL, NULL, 640, AI_STATIC) /* Array#16 */ AI_ARRAY_OBJ_DECLARE( conv2d_2_bias_array, AI_ARRAY_FORMAT_S32, - NULL, NULL, 108, AI_STATIC) + NULL, NULL, 128, AI_STATIC) /* Array#17 */ AI_ARRAY_OBJ_DECLARE( conv2d_3_weights_array, AI_ARRAY_FORMAT_S8, - NULL, NULL, 8748, AI_STATIC) + NULL, NULL, 16384, AI_STATIC) /* Array#18 */ AI_ARRAY_OBJ_DECLARE( conv2d_3_bias_array, AI_ARRAY_FORMAT_S32, - NULL, NULL, 81, AI_STATIC) + NULL, NULL, 128, AI_STATIC) /* Array#19 */ AI_ARRAY_OBJ_DECLARE( conv2d_4_weights_array, AI_ARRAY_FORMAT_S8, - NULL, NULL, 810, AI_STATIC) + NULL, NULL, 1280, AI_STATIC) /* Array#20 */ AI_ARRAY_OBJ_DECLARE( conv2d_4_bias_array, AI_ARRAY_FORMAT_S32, - NULL, NULL, 81, AI_STATIC) + NULL, NULL, 128, AI_STATIC) /* Array#21 */ AI_ARRAY_OBJ_DECLARE( conv2d_5_weights_array, AI_ARRAY_FORMAT_S8, - NULL, NULL, 4212, AI_STATIC) + NULL, NULL, 16384, AI_STATIC) /* Array#22 */ AI_ARRAY_OBJ_DECLARE( conv2d_5_bias_array, AI_ARRAY_FORMAT_S32, - NULL, NULL, 52, AI_STATIC) + NULL, NULL, 128, AI_STATIC) /* Array#23 */ AI_ARRAY_OBJ_DECLARE( conv2d_6_weights_array, AI_ARRAY_FORMAT_S8, - NULL, NULL, 780, AI_STATIC) + NULL, NULL, 1920, AI_STATIC) /* Array#24 */ AI_ARRAY_OBJ_DECLARE( conv2d_6_bias_array, AI_ARRAY_FORMAT_S32, - NULL, NULL, 52, AI_STATIC) + NULL, NULL, 128, AI_STATIC) /* Array#25 */ AI_ARRAY_OBJ_DECLARE( conv2d_7_weights_array, AI_ARRAY_FORMAT_S8, - NULL, NULL, 1664, AI_STATIC) + NULL, NULL, 4096, AI_STATIC) /* Array#26 */ AI_ARRAY_OBJ_DECLARE( @@ -209,37 +209,37 @@ AI_ARRAY_OBJ_DECLARE( /* Array#30 */ AI_ARRAY_OBJ_DECLARE( conv2d_1_scratch0_array, AI_ARRAY_FORMAT_S8, - NULL, NULL, 1240, AI_STATIC) + NULL, NULL, 1440, AI_STATIC) /* Array#31 */ AI_ARRAY_OBJ_DECLARE( conv2d_2_scratch0_array, AI_ARRAY_FORMAT_S8, - NULL, NULL, 2701, AI_STATIC) + NULL, NULL, 3201, AI_STATIC) /* Array#32 */ AI_ARRAY_OBJ_DECLARE( conv2d_3_scratch0_array, AI_ARRAY_FORMAT_S8, - NULL, NULL, 1242, AI_STATIC) + NULL, NULL, 1792, AI_STATIC) /* Array#33 */ AI_ARRAY_OBJ_DECLARE( conv2d_4_scratch0_array, AI_ARRAY_FORMAT_S8, - NULL, NULL, 3241, AI_STATIC) + NULL, NULL, 5121, AI_STATIC) /* Array#34 */ AI_ARRAY_OBJ_DECLARE( conv2d_5_scratch0_array, AI_ARRAY_FORMAT_S8, - NULL, NULL, 844, AI_STATIC) + NULL, NULL, 1792, AI_STATIC) /* Array#35 */ AI_ARRAY_OBJ_DECLARE( conv2d_6_scratch0_array, AI_ARRAY_FORMAT_S8, - NULL, NULL, 2861, AI_STATIC) + NULL, NULL, 7041, AI_STATIC) /* Array#36 */ AI_ARRAY_OBJ_DECLARE( conv2d_7_scratch0_array, AI_ARRAY_FORMAT_S8, - NULL, NULL, 528, AI_STATIC) + NULL, NULL, 832, AI_STATIC) /* Array#37 */ AI_ARRAY_OBJ_DECLARE( @@ -253,426 +253,426 @@ AI_ARRAY_OBJ_DECLARE( /** Array metadata declarations section *************************************/ /* Int quant #0 */ -AI_INTQ_INFO_LIST_OBJ_DECLARE(conv2d_4_weights_array_intq, AI_STATIC_CONST, - AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 81, - AI_PACK_INTQ_INFO( - AI_PACK_INTQ_SCALE(0.0013209173921495676f, 0.0013699670089408755f, 0.0011900769313797355f, 0.0014234690461307764f, 0.0012966083595529199f, 0.002158000133931637f, 0.0013979612849652767f, 0.0010544935939833522f, 0.0008681811159476638f, 0.0014393681194633245f, 0.0018609057879075408f, 0.0013464994262903929f, 0.0008672561962157488f, 0.001372328493744135f, 0.0013065575622022152f, 0.0015507722273468971f, 0.0015574434073641896f, 0.0016854808200150728f, 0.0012486601481214166f, 0.0021874085068702698f, 0.0014007712015882134f, 0.0017165332101285458f, 0.0020851553417742252f, 0.0020932801999151707f, 0.001796632306650281f, 0.0014638400170952082f, 0.0019234605133533478f, 0.002710780594497919f, 0.0012269431026652455f, 0.0010644309222698212f, 0.0014495650539174676f, 0.0013952819863334298f, 0.0015238363994285464f, 0.0015330613823607564f, 0.001806235290132463f, 0.0015545615460723639f, 0.001962702488526702f, 0.0018692143494263291f, 0.002919284626841545f, 0.0011838754871860147f, 0.0014690218959003687f, 0.001570309977978468f, 0.0016600311500951648f, 0.001322298077866435f, 0.001086729229427874f, 0.00108465610537678f, 0.0016869003884494305f, 0.002073693787679076f, 0.0013331201625987887f, 0.0013437183806672692f, 0.0009963620686903596f, 0.0015516714192926884f, 0.0024561795871704817f, 0.001887949532829225f, 0.0019081522477790713f, 0.0018222932703793049f, 0.0012474765535444021f, 0.001181218191049993f, 0.0011141691356897354f, 0.0026841002982109785f, 0.00209209811873734f, 0.0012199511984363198f, 0.0012844110606238246f, 0.0020877672359347343f, 0.0014856132911518216f, 0.0009970106184482574f, 0.001144768437370658f, 0.0020951591432094574f, 0.0013088099658489227f, 0.0008139606798067689f, 0.0014311781851574779f, 0.0024156002327799797f, 0.0010804146295413375f, 0.001683399430476129f, 0.0019631627947092056f, 0.0013160593807697296f, 0.001466938410885632f, 0.001094481791369617f, 0.0015286278212442994f, 0.0013401331380009651f, 0.0011197495041415095f), - AI_PACK_INTQ_ZP(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0))) - -/* Int quant #1 */ -AI_INTQ_INFO_LIST_OBJ_DECLARE(conv2d_5_weights_array_intq, AI_STATIC_CONST, - AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 52, - AI_PACK_INTQ_INFO( - AI_PACK_INTQ_SCALE(0.015773683786392212f, 0.017180703580379486f, 0.016543541103601456f, 0.012180080637335777f, 0.012121811509132385f, 0.01948302611708641f, 0.01332039199769497f, 0.008291282691061497f, 0.006536763161420822f, 0.01492640282958746f, 0.015078308060765266f, 0.01259052287787199f, 0.014905902557075024f, 0.009477532468736172f, 0.017825616523623466f, 0.0100540891289711f, 0.01577778160572052f, 0.007912426255643368f, 0.013099128380417824f, 0.011292265728116035f, 0.014415361918509007f, 0.01442705001682043f, 0.0154510997235775f, 0.01196146011352539f, 0.011186054907739162f, 0.011584583669900894f, 0.012372108176350594f, 0.009474975988268852f, 0.015400659292936325f, 0.015521892346441746f, 0.009775904938578606f, 0.014177525416016579f, 0.018218280747532845f, 0.012715878896415234f, 0.01842585951089859f, 0.014037981629371643f, 0.012311501428484917f, 0.013712716288864613f, 0.010050556622445583f, 0.011510557495057583f, 0.015110366977751255f, 0.017335738986730576f, 0.011255898512899876f, 0.010579855181276798f, 0.007013300433754921f, 0.00525946170091629f, 0.010228436440229416f, 0.014367306604981422f, 0.012811205349862576f, 0.009629661217331886f, 0.00906060915440321f, 0.013815436512231827f), - AI_PACK_INTQ_ZP(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0))) - -/* Int quant #2 */ -AI_INTQ_INFO_LIST_OBJ_DECLARE(conv2d_6_weights_array_intq, AI_STATIC_CONST, - AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 52, - AI_PACK_INTQ_INFO( - AI_PACK_INTQ_SCALE(0.0012915823608636856f, 0.0012511053355410695f, 0.0011855724733322859f, 0.0025645773857831955f, 0.001079620560631156f, 0.0017146256286650896f, 0.0011722984490916133f, 0.0011089964536949992f, 0.0021147746592760086f, 0.0019927872344851494f, 0.0014550697524100542f, 0.002831965684890747f, 0.0018483612220734358f, 0.0008478033705614507f, 0.0018396616214886308f, 0.0021623552311211824f, 0.0019630850292742252f, 0.0017485704738646746f, 0.0021983326878398657f, 0.0011710221879184246f, 0.002634496660903096f, 0.0015223354566842318f, 0.0019060292979702353f, 0.0017563101137056947f, 0.0020001009106636047f, 0.0017203905154019594f, 0.0009780041873455048f, 0.0009349649189971387f, 0.0010179498931393027f, 0.002921813866123557f, 0.001127480762079358f, 0.002835941733792424f, 0.0025946912355720997f, 0.0017454741755500436f, 0.0021075394470244646f, 0.0013835849240422249f, 0.00247604469768703f, 0.0010387442307546735f, 0.0026010600849986076f, 0.0020862752571702003f, 0.0010696039535105228f, 0.0024096250999718904f, 0.001306817983277142f, 0.0008883686969056726f, 0.0018930664518848062f, 0.0010039584012702107f, 0.0013365934137254953f, 0.0024195443838834763f, 0.0014412919990718365f, 0.001000774442218244f, 0.0019087563268840313f, 0.0025204240810126066f), - AI_PACK_INTQ_ZP(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0))) - -/* Int quant #3 */ -AI_INTQ_INFO_LIST_OBJ_DECLARE(conv2d_7_weights_array_intq, AI_STATIC_CONST, - AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 32, - AI_PACK_INTQ_INFO( - AI_PACK_INTQ_SCALE(0.007534192409366369f, 0.005160065367817879f, 0.00863321591168642f, 0.011691645719110966f, 0.007065467070788145f, 0.013616980984807014f, 0.010354913771152496f, 0.005401516333222389f, 0.00899604894220829f, 0.008329877629876137f, 0.009429126977920532f, 0.00915415771305561f, 0.012206453830003738f, 0.007751247379928827f, 0.008157746866345406f, 0.006608979310840368f, 0.008793451823294163f, 0.00995804462581873f, 0.00625076936557889f, 0.005368341226130724f, 0.009286150336265564f, 0.009581937454640865f, 0.00813126377761364f, 0.007290022913366556f, 0.006840443704277277f, 0.0074807205237448215f, 0.009476734325289726f, 0.008071377873420715f, 0.006180003751069307f, 0.011818638071417809f, 0.008427681401371956f, 0.009211544878780842f), - AI_PACK_INTQ_ZP(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0))) - -/* Int quant #4 */ -AI_INTQ_INFO_LIST_OBJ_DECLARE(gemm_9_weights_array_intq, AI_STATIC_CONST, - AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 1, - AI_PACK_INTQ_INFO( - AI_PACK_INTQ_SCALE(0.01235697977244854f), - AI_PACK_INTQ_ZP(0))) - -/* Int quant #5 */ AI_INTQ_INFO_LIST_OBJ_DECLARE(serving_default_input_10_output_array_intq, AI_STATIC_CONST, AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 1, AI_PACK_INTQ_INFO( AI_PACK_INTQ_SCALE(0.003701042616739869f), AI_PACK_INTQ_ZP(-128))) -/* Int quant #6 */ +/* Int quant #1 */ AI_INTQ_INFO_LIST_OBJ_DECLARE(conv2d_0_output_array_intq, AI_STATIC_CONST, AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 1, AI_PACK_INTQ_INFO( - AI_PACK_INTQ_SCALE(0.0018045719480141997f), + AI_PACK_INTQ_SCALE(0.00201102951541543f), AI_PACK_INTQ_ZP(-3))) -/* Int quant #7 */ +/* Int quant #2 */ AI_INTQ_INFO_LIST_OBJ_DECLARE(conv2d_1_output_array_intq, AI_STATIC_CONST, AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 1, AI_PACK_INTQ_INFO( - AI_PACK_INTQ_SCALE(0.007331364788115025f), + AI_PACK_INTQ_SCALE(0.0156570877879858f), AI_PACK_INTQ_ZP(-128))) -/* Int quant #8 */ +/* Int quant #3 */ AI_INTQ_INFO_LIST_OBJ_DECLARE(conv2d_2_output_array_intq, AI_STATIC_CONST, AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 1, AI_PACK_INTQ_INFO( - AI_PACK_INTQ_SCALE(0.0033829212188720703f), - AI_PACK_INTQ_ZP(4))) + AI_PACK_INTQ_SCALE(0.00660408241674304f), + AI_PACK_INTQ_ZP(-2))) -/* Int quant #9 */ +/* Int quant #4 */ AI_INTQ_INFO_LIST_OBJ_DECLARE(conv2d_3_output_array_intq, AI_STATIC_CONST, AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 1, AI_PACK_INTQ_INFO( - AI_PACK_INTQ_SCALE(0.008522006683051586f), + AI_PACK_INTQ_SCALE(0.021217012777924538f), AI_PACK_INTQ_ZP(-128))) -/* Int quant #10 */ +/* Int quant #5 */ AI_INTQ_INFO_LIST_OBJ_DECLARE(conv2d_4_output_array_intq, AI_STATIC_CONST, AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 1, AI_PACK_INTQ_INFO( - AI_PACK_INTQ_SCALE(0.005995603743940592f), - AI_PACK_INTQ_ZP(17))) + AI_PACK_INTQ_SCALE(0.01422338467091322f), + AI_PACK_INTQ_ZP(11))) -/* Int quant #11 */ +/* Int quant #6 */ AI_INTQ_INFO_LIST_OBJ_DECLARE(conv2d_5_output_array_intq, AI_STATIC_CONST, AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 1, AI_PACK_INTQ_INFO( - AI_PACK_INTQ_SCALE(0.012133517302572727f), + AI_PACK_INTQ_SCALE(0.020943840965628624f), AI_PACK_INTQ_ZP(-128))) -/* Int quant #12 */ +/* Int quant #7 */ AI_INTQ_INFO_LIST_OBJ_DECLARE(conv2d_6_output_array_intq, AI_STATIC_CONST, AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 1, AI_PACK_INTQ_INFO( - AI_PACK_INTQ_SCALE(0.014823319390416145f), - AI_PACK_INTQ_ZP(3))) + AI_PACK_INTQ_SCALE(0.023002251982688904f), + AI_PACK_INTQ_ZP(-5))) -/* Int quant #13 */ +/* Int quant #8 */ AI_INTQ_INFO_LIST_OBJ_DECLARE(conv2d_7_output_array_intq, AI_STATIC_CONST, AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 1, AI_PACK_INTQ_INFO( - AI_PACK_INTQ_SCALE(0.018331341445446014f), + AI_PACK_INTQ_SCALE(0.02659711427986622f), AI_PACK_INTQ_ZP(-128))) -/* Int quant #14 */ +/* Int quant #9 */ AI_INTQ_INFO_LIST_OBJ_DECLARE(gemm_9_output_array_intq, AI_STATIC_CONST, AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 1, AI_PACK_INTQ_INFO( - AI_PACK_INTQ_SCALE(0.14710605144500732f), - AI_PACK_INTQ_ZP(30))) + AI_PACK_INTQ_SCALE(0.1605089008808136f), + AI_PACK_INTQ_ZP(10))) -/* Int quant #15 */ +/* Int quant #10 */ AI_INTQ_INFO_LIST_OBJ_DECLARE(nl_10_output_array_intq, AI_STATIC_CONST, AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 1, AI_PACK_INTQ_INFO( AI_PACK_INTQ_SCALE(0.00390625f), AI_PACK_INTQ_ZP(-128))) -/* Int quant #16 */ +/* Int quant #11 */ AI_INTQ_INFO_LIST_OBJ_DECLARE(conv2d_0_weights_array_intq, AI_STATIC_CONST, AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 40, AI_PACK_INTQ_INFO( - AI_PACK_INTQ_SCALE(0.001642347895540297f, 0.0012464334722608328f, 0.0018808494787663221f, 0.0017687849467620254f, 0.002232156926766038f, 0.0017221078742295504f, 0.0016933622537180781f, 0.001586283789947629f, 0.0019639935344457626f, 0.0017922259867191315f, 0.0018330850871279836f, 0.0015503712929785252f, 0.001953525235876441f, 0.0015549628296867013f, 0.0024999254383146763f, 0.0009487768402323127f, 0.001722460612654686f, 0.0016345441108569503f, 0.0006262531387619674f, 0.002148588187992573f, 0.0017868067370727658f, 0.0016791783273220062f, 0.0007694695959798992f, 0.0016042999923229218f, 0.002147432416677475f, 0.0026659697759896517f, 0.0016246186569333076f, 0.0015353725757449865f, 0.0013496452011168003f, 0.0010453679133206606f, 0.001754468074068427f, 0.0023172975052148104f, 0.0015870793722569942f, 0.0014503091806545854f, 0.0011753877624869347f, 0.0009309005690738559f, 0.0022590768057852983f, 0.0019405314233154058f, 0.0022477428428828716f, 0.0010750620858743787f), + AI_PACK_INTQ_SCALE(0.001254240982234478f, 0.000987853854894638f, 0.0023639246355742216f, 0.002243900438770652f, 0.0017858505016192794f, 0.0011415338376536965f, 0.0017538557294756174f, 0.002023568144068122f, 0.0021016751416027546f, 0.0013468243414536119f, 0.00200396915897727f, 0.002309079049155116f, 0.0017402308294549584f, 0.002304395427927375f, 0.00155027792789042f, 0.0009224143577739596f, 0.0018792665796354413f, 0.0017135005909949541f, 0.0020612196531146765f, 0.0019450961844995618f, 0.0017030887538567185f, 0.0014141489518806338f, 0.001620377297513187f, 0.0015282955719158053f, 0.001365334028378129f, 0.0014392910525202751f, 0.0013374720001593232f, 0.001347132958471775f, 0.0013114564353600144f, 0.0011181841837242246f, 0.002099294913932681f, 0.0014655484119430184f, 0.0012597404420375824f, 0.0015403854195028543f, 0.0009770492324605584f, 0.0006319010863080621f, 0.001912836218252778f, 0.001167225418612361f, 0.0008276058360934258f, 0.0015495851403102279f), AI_PACK_INTQ_ZP(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0))) -/* Int quant #17 */ +/* Int quant #12 */ AI_INTQ_INFO_LIST_OBJ_DECLARE(conv2d_1_weights_array_intq, AI_STATIC_CONST, - AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 108, + AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 128, AI_PACK_INTQ_INFO( - AI_PACK_INTQ_SCALE(0.03843778744339943f, 0.03424474969506264f, 0.017642157152295113f, 0.016672806814312935f, 0.02117191255092621f, 0.030264290049672127f, 0.027997097000479698f, 0.024589020758867264f, 0.013011130504310131f, 0.025482743978500366f, 0.02170688845217228f, 0.020765338093042374f, 0.004156722687184811f, 0.01876024156808853f, 0.028028424829244614f, 0.0335012711584568f, 0.028314050287008286f, 0.02842898666858673f, 0.024900702759623528f, 0.022218992933630943f, 0.028063176199793816f, 0.03321857750415802f, 0.02153550460934639f, 0.03990000858902931f, 0.020548759028315544f, 0.03405828773975372f, 0.02318909764289856f, 0.023638205602765083f, 0.019964933395385742f, 0.03596772626042366f, 0.01502156537026167f, 0.03389132022857666f, 0.022404439747333527f, 0.03430989757180214f, 0.03384352847933769f, 0.027794936671853065f, 0.017100447788834572f, 0.01263357698917389f, 0.040574971586465836f, 0.037140779197216034f, 0.031087808310985565f, 0.04442266374826431f, 0.037988293915987015f, 0.029726577922701836f, 0.031557273119688034f, 0.03631843999028206f, 0.025610091164708138f, 0.018468542024493217f, 0.021165795624256134f, 0.02730490453541279f, 0.012819893658161163f, 0.02316182851791382f, 0.026402035728096962f, 0.02412860468029976f, 0.04931594803929329f, 0.031328584998846054f, 0.02464168332517147f, 0.021940257400274277f, 0.035059619694948196f, 0.037006113678216934f, 0.03842802345752716f, 0.03353657200932503f, 0.026503458619117737f, 0.03792215883731842f, 0.027321206405758858f, 0.029820093885064125f, 0.0310662854462862f, 0.029756441712379456f, 0.024783749133348465f, 0.015829073265194893f, 0.022009551525115967f, 0.03166014701128006f, 0.016863781958818436f, 0.029639851301908493f, 0.03000551462173462f, 0.01928015798330307f, 0.02872774749994278f, 0.03196508064866066f, 0.03661493584513664f, 0.025833558291196823f, 0.03245000168681145f, 0.02557412162423134f, 0.02539031393826008f, 0.03885124996304512f, 0.027298370376229286f, 0.030694743618369102f, 0.023782826960086823f, 0.013601325452327728f, 0.016648098826408386f, 0.019702767953276634f, 0.04989137127995491f, 0.01952550560235977f, 0.011950946412980556f, 0.020136114209890366f, 0.0188601054251194f, 0.031969454139471054f, 0.015985149890184402f, 0.022637400776147842f, 0.0029883950483053923f, 0.009722628630697727f, 0.023238789290189743f, 0.018725885078310966f, 0.03747653216123581f, 0.0312572605907917f, 0.027069244533777237f, 0.019321395084261894f, 0.01773461326956749f, 0.02210475318133831f), - AI_PACK_INTQ_ZP(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0))) + AI_PACK_INTQ_SCALE(0.0557364895939827f, 0.07009103149175644f, 0.07312853634357452f, 0.07519220560789108f, 0.06794387847185135f, 0.04205628111958504f, 0.0562371201813221f, 0.05192823335528374f, 0.06842111796140671f, 0.06204013526439667f, 0.08090592920780182f, 0.08395314961671829f, 0.05494164675474167f, 0.08445177972316742f, 0.046601731330156326f, 0.09875835478305817f, 0.06608492136001587f, 0.062287088483572006f, 0.040040839463472366f, 0.07655619084835052f, 0.049667321145534515f, 0.08540472388267517f, 0.06680362671613693f, 0.06079522892832756f, 0.06035850569605827f, 0.0991595908999443f, 0.06058833748102188f, 0.053274162113666534f, 0.03797821328043938f, 0.03621498867869377f, 0.06712622195482254f, 0.04423489421606064f, 0.05383652448654175f, 0.0625288337469101f, 0.07554386556148529f, 0.08373166620731354f, 0.07192773371934891f, 0.07930143922567368f, 0.0631629005074501f, 0.07137389481067657f, 0.06803224980831146f, 0.07083737105131149f, 0.06082828715443611f, 0.04855984449386597f, 0.072658009827137f, 0.056501202285289764f, 0.0610412172973156f, 0.06590580195188522f, 0.05194118246436119f, 0.07365408539772034f, 0.0694989338517189f, 0.07441677153110504f, 0.08273050934076309f, 0.05379199609160423f, 0.051689691841602325f, 0.045179639011621475f, 0.06800905615091324f, 0.07222118228673935f, 0.029597962275147438f, 0.044567640870809555f, 0.08320189267396927f, 0.05727767571806908f, 0.053610820323228836f, 0.05451217293739319f, 0.055087361484766006f, 0.06034782901406288f, 0.07593630999326706f, 0.05325336381793022f, 0.07666018605232239f, 0.06480028480291367f, 0.07967717200517654f, 0.06565572321414948f, 0.05748875439167023f, 0.05578473582863808f, 0.04856053367257118f, 0.061835724860429764f, 0.056185416877269745f, 0.06835354119539261f, 0.07982499897480011f, 0.05127878487110138f, 0.06645739078521729f, 0.05910467728972435f, 0.07597667723894119f, 0.044447869062423706f, 0.04783950373530388f, 0.05948562175035477f, 0.03321472555398941f, 0.06900342553853989f, 0.057095520198345184f, 0.05819859355688095f, 0.058210767805576324f, 0.05978216230869293f, 0.07817946374416351f, 0.050082650035619736f, 0.07074058055877686f, 0.05369323119521141f, 0.0613066628575325f, 0.04076726734638214f, 0.08337310701608658f, 0.05360524356365204f, 0.07031101733446121f, 0.06139835715293884f, 0.04510099068284035f, 0.07147779315710068f, 0.057549599558115005f, 0.05941694229841232f, 0.0583166740834713f, 0.07551203668117523f, 0.06332285702228546f, 0.06461220979690552f, 0.061315227299928665f, 0.0557643286883831f, 0.07862327247858047f, 0.06502321362495422f, 0.06541603058576584f, 0.05246961489319801f, 0.05109808221459389f, 0.06387913227081299f, 0.04259190708398819f, 0.048779070377349854f, 0.05829177051782608f, 0.0852074846625328f, 0.059691160917282104f, 0.07179801911115646f, 0.07045108824968338f, 0.06907077878713608f, 0.08107734471559525f, 0.056288253515958786f), + AI_PACK_INTQ_ZP(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0))) -/* Int quant #18 */ +/* Int quant #13 */ AI_INTQ_INFO_LIST_OBJ_DECLARE(conv2d_2_weights_array_intq, AI_STATIC_CONST, - AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 108, + AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 128, AI_PACK_INTQ_INFO( - AI_PACK_INTQ_SCALE(0.0012193449074402452f, 0.0011896206997334957f, 0.001150784082710743f, 0.0015751051250845194f, 0.0014076937222853303f, 0.0014134043594822288f, 0.0012166631640866399f, 0.0008614432299509645f, 0.0013119303621351719f, 0.0010421304032206535f, 0.001792778610251844f, 0.0006943026673980057f, 0.0012489653890952468f, 0.0016015503788366914f, 0.0013164817355573177f, 0.0014498716918751597f, 0.0009809196926653385f, 0.0012443828163668513f, 0.0015893805539235473f, 0.0012252413434907794f, 0.00146100006531924f, 0.0012698895297944546f, 0.0009081409662030637f, 0.0011611015070229769f, 0.0014941409463062882f, 0.0014062923146411777f, 0.0014375756727531552f, 0.0011015296913683414f, 0.0011722077615559101f, 0.0017788897966966033f, 0.0015201474307104945f, 0.001466955873183906f, 0.001193762058392167f, 0.0011754519073292613f, 0.0010366021888330579f, 0.0011002852115780115f, 0.0012190159177407622f, 0.0009785162983462214f, 0.0015096979914233088f, 0.0014507253654301167f, 0.001522812177427113f, 0.0011339515913277864f, 0.0012347951997071505f, 0.0017208375502377748f, 0.0012510899687185884f, 0.0011507170274853706f, 0.0015958300791680813f, 0.0011514110956341028f, 0.0014947318704798818f, 0.0015390361659228802f, 0.0009209638810716569f, 0.0016760819125920534f, 0.0009958102600649f, 0.0012021957663819194f, 0.0016008286038413644f, 0.0010758097050711513f, 0.0013621337711811066f, 0.0010371701791882515f, 0.001484634238295257f, 0.0015296931378543377f, 0.0014479142846539617f, 0.0018752461764961481f, 0.0011389135615900159f, 0.0015793287893757224f, 0.0010704681044444442f, 0.0014446311397477984f, 0.001430619740858674f, 0.0011343255173414946f, 0.0014109080657362938f, 0.0011780846398323774f, 0.0013960669748485088f, 0.0012521182652562857f, 0.0012801842531189322f, 0.0010166580323129892f, 0.0011850884184241295f, 0.001457210979424417f, 0.0013643177226185799f, 0.0011476562358438969f, 0.0009190457058139145f, 0.001462473999708891f, 0.0015686636324971914f, 0.000985241960734129f, 0.0012081931345164776f, 0.0012406273745000362f, 0.001423214445821941f, 0.0013334010727703571f, 0.001554172020405531f, 0.0012627579271793365f, 0.0013837196165695786f, 0.0015174734871834517f, 0.0016533306334167719f, 0.0016571376472711563f, 0.0010685668094083667f, 0.0012777920346707106f, 0.0012865728931501508f, 0.0013592647155746818f, 0.0013121356023475528f, 0.0010990258306264877f, 0.0009446862968616188f, 0.0011264465283602476f, 0.0014283916680142283f, 0.0011742946226149797f, 0.001202662126161158f, 0.0012340721441432834f, 0.0010347074130550027f, 0.0010912242578342557f, 0.0016451962292194366f, 0.0012853143271058798f), - AI_PACK_INTQ_ZP(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0))) + AI_PACK_INTQ_SCALE(0.001457194215618074f, 0.0009723921539261937f, 0.0013601945247501135f, 0.0010919407941401005f, 0.0011240930762141943f, 0.0007749227806925774f, 0.0011948911705985665f, 0.0013619126984849572f, 0.0015052009839564562f, 0.0013265281450003386f, 0.0018033514497801661f, 0.0014381217770278454f, 0.0014037148794159293f, 0.0007280678255483508f, 0.0008964194566942751f, 0.0018901232397183776f, 0.001301257754676044f, 0.0009921570308506489f, 0.001112807309255004f, 0.0015667153056710958f, 0.0012362829875200987f, 0.0013835717691108584f, 0.0018188247922807932f, 0.0014296906301751733f, 0.0016897013410925865f, 0.002016243524849415f, 0.0014584207674488425f, 0.0010354607366025448f, 0.0012074884725734591f, 0.0009191667777486145f, 0.0010689138434827328f, 0.0011970116756856441f, 0.001236463780514896f, 0.0007100395741872489f, 0.0014765067026019096f, 0.001199970836751163f, 0.0014740955084562302f, 0.0013169446028769016f, 0.0015439967392012477f, 0.0010305190226063132f, 0.0015230093849822879f, 0.0015533901751041412f, 0.0010137794306501746f, 0.00089537218445912f, 0.0010918447514995933f, 0.0014528129249811172f, 0.0012662803055718541f, 0.001200537895783782f, 0.0012714293552562594f, 0.0009842150611802936f, 0.001062242197804153f, 0.0013996799243614078f, 0.0016503318911418319f, 0.001138547551818192f, 0.0014294023858383298f, 0.0011567275505512953f, 0.0010271449573338032f, 0.0011177746346220374f, 0.0009676266345195472f, 0.0014508026652038097f, 0.0011148808989673853f, 0.0012952603865414858f, 0.0013585408451035619f, 0.001118360087275505f, 0.0009408454643562436f, 0.001091507263481617f, 0.001650888123549521f, 0.0011108191683888435f, 0.0011713849380612373f, 0.0008862194954417646f, 0.001164129818789661f, 0.0012480347650125623f, 0.0010247734608128667f, 0.0008816487388685346f, 0.0011323459912091494f, 0.0010942177614197135f, 0.0010509698186069727f, 0.0013842389453202486f, 0.0014747651293873787f, 0.001593481982126832f, 0.0010891774436458945f, 0.0012570887338370085f, 0.0012310544261708856f, 0.0011031338945031166f, 0.0010200949618592858f, 0.0011984126176685095f, 0.0010176780633628368f, 0.0012454434763640165f, 0.0012019664281979203f, 0.0013115550391376019f, 0.0010792074026539922f, 0.0010111387819051743f, 0.0020363545045256615f, 0.0014258726732805371f, 0.0014970358461141586f, 0.00127586186863482f, 0.0015796208754181862f, 0.0010193175403401256f, 0.0007893570000305772f, 0.00140108831692487f, 0.0011709867976605892f, 0.0015299858059734106f, 0.0008113248040899634f, 0.001614834414795041f, 0.001047957339324057f, 0.0014852990861982107f, 0.0013226664159446955f, 0.0012027606135234237f, 0.00225705374032259f, 0.0013730308273807168f, 0.0017574755474925041f, 0.001117254258133471f, 0.0012049174401909113f, 0.0011757693719118834f, 0.001052318257279694f, 0.0016300027491524816f, 0.0012732358882203698f, 0.00135029514785856f, 0.0012994565768167377f, 0.0009282983373850584f, 0.001250690664164722f, 0.0013516527833417058f, 0.0012642749352380633f, 0.001367756980471313f, 0.001352929975837469f, 0.001103689312003553f, 0.0014360324712470174f, 0.0010408981470391154f), + AI_PACK_INTQ_ZP(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0))) -/* Int quant #19 */ +/* Int quant #14 */ AI_INTQ_INFO_LIST_OBJ_DECLARE(conv2d_3_weights_array_intq, AI_STATIC_CONST, - AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 81, + AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 128, AI_PACK_INTQ_INFO( - AI_PACK_INTQ_SCALE(0.015128846280276775f, 0.015573011711239815f, 0.016271857544779778f, 0.014132648706436157f, 0.018094440922141075f, 0.020049450919032097f, 0.018400095403194427f, 0.017870919778943062f, 0.016350913792848587f, 0.014747311361134052f, 0.017187248915433884f, 0.016289183869957924f, 0.015324003994464874f, 0.02062303200364113f, 0.01638767123222351f, 0.014158428646624088f, 0.01555232796818018f, 0.02522544004023075f, 0.01610005833208561f, 0.02466684952378273f, 0.018511435016989708f, 0.015439994633197784f, 0.012423139996826649f, 0.018430529162287712f, 0.013635613955557346f, 0.013857602141797543f, 0.016926752403378487f, 0.019769813865423203f, 0.026674576103687286f, 0.01582067273557186f, 0.01869085244834423f, 0.016557810828089714f, 0.010478632524609566f, 0.016589654609560966f, 0.017770716920495033f, 0.015888260677456856f, 0.018635224550962448f, 0.016906341537833214f, 0.02251080609858036f, 0.01092725433409214f, 0.018775317817926407f, 0.01914645917713642f, 0.021332694217562675f, 0.011556758545339108f, 0.017348820343613625f, 0.017436355352401733f, 0.01638859696686268f, 0.01837228797376156f, 0.01729300431907177f, 0.015137557871639729f, 0.020055970177054405f, 0.016387302428483963f, 0.015314789488911629f, 0.015308589674532413f, 0.014827247709035873f, 0.016430499032139778f, 0.016709063202142715f, 0.0161450132727623f, 0.0203449334949255f, 0.016926869750022888f, 0.015119430609047413f, 0.013861013576388359f, 0.012870672158896923f, 0.018918493762612343f, 0.015354461036622524f, 0.00960373505949974f, 0.012707964517176151f, 0.015196085907518864f, 0.012715458869934082f, 0.019194994121789932f, 0.014486822299659252f, 0.020452536642551422f, 0.020936153829097748f, 0.016988983377814293f, 0.013276669196784496f, 0.016756894066929817f, 0.01643085852265358f, 0.019164972007274628f, 0.018671797588467598f, 0.014429536648094654f, 0.01753745600581169f), - AI_PACK_INTQ_ZP(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0))) - -/** Tensor declarations section *********************************************/ -/* Tensor #0 */ -AI_TENSOR_OBJ_DECLARE( - conv2d_4_weights, AI_STATIC, - 0, 0x1, - AI_SHAPE_INIT(4, 81, 1, 10, 1), AI_STRIDE_INIT(4, 1, 81, 81, 81), - 1, &conv2d_4_weights_array, &conv2d_4_weights_array_intq) - -/* Tensor #1 */ -AI_TENSOR_OBJ_DECLARE( - conv2d_4_bias, AI_STATIC, - 1, 0x0, - AI_SHAPE_INIT(4, 1, 81, 1, 1), AI_STRIDE_INIT(4, 4, 4, 324, 324), - 1, &conv2d_4_bias_array, NULL) - -/* Tensor #2 */ -AI_TENSOR_OBJ_DECLARE( - conv2d_5_weights, AI_STATIC, - 2, 0x1, - AI_SHAPE_INIT(4, 81, 1, 1, 52), AI_STRIDE_INIT(4, 1, 81, 4212, 4212), - 1, &conv2d_5_weights_array, &conv2d_5_weights_array_intq) - -/* Tensor #3 */ -AI_TENSOR_OBJ_DECLARE( - conv2d_5_bias, AI_STATIC, - 3, 0x0, - AI_SHAPE_INIT(4, 1, 52, 1, 1), AI_STRIDE_INIT(4, 4, 4, 208, 208), - 1, &conv2d_5_bias_array, NULL) + AI_PACK_INTQ_SCALE(0.015435479581356049f, 0.015712741762399673f, 0.01558498851954937f, 0.016315478831529617f, 0.01392341498285532f, 0.013273568823933601f, 0.014436349272727966f, 0.016139496117830276f, 0.013943783938884735f, 0.014968005008995533f, 0.016137033700942993f, 0.018906202167272568f, 0.014906913973391056f, 0.014077719300985336f, 0.013979420997202396f, 0.014923224225640297f, 0.014362655580043793f, 0.012227006256580353f, 0.013939925469458103f, 0.015511170960962772f, 0.016097450628876686f, 0.016307974234223366f, 0.01594250649213791f, 0.016943685710430145f, 0.01947934739291668f, 0.015324920415878296f, 0.01342093851417303f, 0.01737106218934059f, 0.01712331548333168f, 0.01378227211534977f, 0.02059919945895672f, 0.016569236293435097f, 0.018695591017603874f, 0.013657263480126858f, 0.015280283987522125f, 0.0137398112565279f, 0.01404078770428896f, 0.013378037139773369f, 0.01614484004676342f, 0.014124514535069466f, 0.014835270121693611f, 0.01518865767866373f, 0.012940126471221447f, 0.014110173098742962f, 0.014851577579975128f, 0.013032273389399052f, 0.01693967543542385f, 0.01828206144273281f, 0.012893002480268478f, 0.017635837197303772f, 0.013798611238598824f, 0.01650739647448063f, 0.018094396218657494f, 0.015165853314101696f, 0.0182835403829813f, 0.015218982473015785f, 0.018710190430283546f, 0.01615961827337742f, 0.018013417720794678f, 0.014665942639112473f, 0.014946150593459606f, 0.015412447042763233f, 0.019634950906038284f, 0.016949571669101715f, 0.022148821502923965f, 0.014756591990590096f, 0.013131124898791313f, 0.014976650476455688f, 0.017191952094435692f, 0.01771528087556362f, 0.016732702031731606f, 0.0152655690908432f, 0.01618521474301815f, 0.0162675604224205f, 0.0139463534578681f, 0.015391269698739052f, 0.013169356621801853f, 0.01791398972272873f, 0.012500961311161518f, 0.013974775560200214f, 0.017448674887418747f, 0.013807814568281174f, 0.013808023184537888f, 0.015517099760472775f, 0.01541734579950571f, 0.021181931719183922f, 0.019085142761468887f, 0.016049465164542198f, 0.014696359634399414f, 0.012714914046227932f, 0.011776293627917767f, 0.014365089125931263f, 0.014318197965621948f, 0.013566143810749054f, 0.016921816393733025f, 0.016708578914403915f, 0.01362423226237297f, 0.019383680075407028f, 0.012663201428949833f, 0.01339720655232668f, 0.014465484768152237f, 0.015076856128871441f, 0.017618173733353615f, 0.01807669922709465f, 0.01630840077996254f, 0.019920621067285538f, 0.01648368313908577f, 0.015001622959971428f, 0.011919248849153519f, 0.012855609878897667f, 0.016874322667717934f, 0.019298046827316284f, 0.018776752054691315f, 0.014909368939697742f, 0.019307341426610947f, 0.01917709782719612f, 0.016197241842746735f, 0.02055920846760273f, 0.013619495555758476f, 0.013428855687379837f, 0.01383062545210123f, 0.022127848118543625f, 0.01936076581478119f, 0.01475452072918415f, 0.019544588401913643f, 0.014161425642669201f, 0.013420923613011837f, 0.017288679257035255f), + AI_PACK_INTQ_ZP(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0))) -/* Tensor #4 */ -AI_TENSOR_OBJ_DECLARE( - conv2d_6_weights, AI_STATIC, - 4, 0x1, - AI_SHAPE_INIT(4, 52, 1, 15, 1), AI_STRIDE_INIT(4, 1, 52, 52, 52), - 1, &conv2d_6_weights_array, &conv2d_6_weights_array_intq) +/* Int quant #15 */ +AI_INTQ_INFO_LIST_OBJ_DECLARE(conv2d_4_weights_array_intq, AI_STATIC_CONST, + AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 128, + AI_PACK_INTQ_INFO( + AI_PACK_INTQ_SCALE(0.001030951039865613f, 0.0009663183591328561f, 0.0020365288946777582f, 0.001815925701521337f, 0.002145384903997183f, 0.001409777789376676f, 0.001111526507884264f, 0.0015876612160354853f, 0.0016483505023643374f, 0.0013704027514904737f, 0.0009633837034925818f, 0.0015526096103712916f, 0.0009668989223428071f, 0.0015864350134506822f, 0.0010745303006842732f, 0.0015920627629384398f, 0.0015163786010816693f, 0.0016441678162664175f, 0.0013378700241446495f, 0.0012708965223282576f, 0.001072538085281849f, 0.0009703931282274425f, 0.0011450444580987096f, 0.0008802785887382925f, 0.001735459896735847f, 0.0018730739830061793f, 0.0012666027760133147f, 0.001065767602995038f, 0.0014535138616338372f, 0.0011152426013723016f, 0.0009994128486141562f, 0.0013775794068351388f, 0.0016316469991579652f, 0.0012451710645109415f, 0.0008939913823269308f, 0.0016194006893783808f, 0.0008270086254924536f, 0.001675823936238885f, 0.0015909906942397356f, 0.0011504803551360965f, 0.0012560825562104583f, 0.0011987114557996392f, 0.0011585205793380737f, 0.0012363066198304296f, 0.0007800934254191816f, 0.0011687107617035508f, 0.001032490050420165f, 0.0016657221131026745f, 0.0007262459839694202f, 0.0013004018692299724f, 0.0007300545112229884f, 0.0013116539921611547f, 0.0025262972339987755f, 0.0017188400961458683f, 0.0012555615976452827f, 0.001429481664672494f, 0.0020307605154812336f, 0.0019690764602273703f, 0.0010181989055126905f, 0.000716641778126359f, 0.0018956996500492096f, 0.0014258645242080092f, 0.001659393310546875f, 0.0016624624840915203f, 0.0010435179574415088f, 0.0012228030245751143f, 0.0011399780632928014f, 0.0010431609116494656f, 0.0016112205339595675f, 0.0010711067588999867f, 0.0008976454264484346f, 0.0010344804031774402f, 0.0011942260898649693f, 0.001424324233084917f, 0.0015099116135388613f, 0.0012318342924118042f, 0.0009290197631344199f, 0.0011712794657796621f, 0.0010101620573550463f, 0.0012421752326190472f, 0.0015237081097438931f, 0.0017582521541044116f, 0.0010588542791083455f, 0.001220689038746059f, 0.001443062094040215f, 0.0016777722630649805f, 0.0012624131049960852f, 0.0013443867210298777f, 0.0014833963941782713f, 0.0010854167630895972f, 0.0008980169659480453f, 0.00115650100633502f, 0.0008218510774895549f, 0.0011783166555687785f, 0.0010326126357540488f, 0.0017004625406116247f, 0.0010935092577710748f, 0.0011593797244131565f, 0.0009975851280614734f, 0.0010316413827240467f, 0.0007522624218836427f, 0.0014686805661767721f, 0.0012527885846793652f, 0.0010121382074430585f, 0.001075917505659163f, 0.0013335651019588113f, 0.0010061735520139337f, 0.0012432377552613616f, 0.0013508893316611648f, 0.001002717763185501f, 0.001575037487782538f, 0.0009822685969993472f, 0.0011989400954917073f, 0.0016884527867659926f, 0.0013193093473091722f, 0.0008631465025246143f, 0.0019490262493491173f, 0.001037734909914434f, 0.0012790425680577755f, 0.0009759807144291699f, 0.0009371792548336089f, 0.0010544632095843554f, 0.0013089921558275819f, 0.0012187730753794312f, 0.0009693853789940476f, 0.0012472359230741858f, 0.0013540320796892047f, 0.0008517162641510367f), + AI_PACK_INTQ_ZP(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0))) -/* Tensor #5 */ -AI_TENSOR_OBJ_DECLARE( - conv2d_6_bias, AI_STATIC, - 5, 0x0, - AI_SHAPE_INIT(4, 1, 52, 1, 1), AI_STRIDE_INIT(4, 4, 4, 208, 208), - 1, &conv2d_6_bias_array, NULL) +/* Int quant #16 */ +AI_INTQ_INFO_LIST_OBJ_DECLARE(conv2d_5_weights_array_intq, AI_STATIC_CONST, + AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 128, + AI_PACK_INTQ_INFO( + AI_PACK_INTQ_SCALE(0.007209585979580879f, 0.006415214389562607f, 0.00607988191768527f, 0.005748692434281111f, 0.007049835752695799f, 0.007252279203385115f, 0.005640252958983183f, 0.006829830352216959f, 0.007592139765620232f, 0.006421814672648907f, 0.006420675199478865f, 0.007017724681645632f, 0.006551500875502825f, 0.007208232767879963f, 0.006610532756894827f, 0.008200299926102161f, 0.005483574233949184f, 0.006066916976124048f, 0.007451366633176804f, 0.006509835831820965f, 0.00657886965200305f, 0.008137550204992294f, 0.006620629224926233f, 0.005716575775295496f, 0.0054453350603580475f, 0.005314652808010578f, 0.006194647401571274f, 0.010287482291460037f, 0.005030793137848377f, 0.006586421746760607f, 0.006298349238932133f, 0.005491567775607109f, 0.006552122067660093f, 0.007213250733911991f, 0.006862261798232794f, 0.006494763307273388f, 0.00564621714875102f, 0.006661905907094479f, 0.008320951834321022f, 0.008955114521086216f, 0.006754994858056307f, 0.0063271126709878445f, 0.006211801897734404f, 0.007845023646950722f, 0.005333251785486937f, 0.00634790537878871f, 0.005190329160541296f, 0.00598357105627656f, 0.005499877966940403f, 0.008485047146677971f, 0.005036849062889814f, 0.007025523576885462f, 0.006772865075618029f, 0.003883525263518095f, 0.006549316458404064f, 0.005562233738601208f, 0.005905645899474621f, 0.007371734362095594f, 0.006529290694743395f, 0.007813907228410244f, 0.006967909634113312f, 0.00531267374753952f, 0.005333815701305866f, 0.005704888608306646f, 0.007289815228432417f, 0.005414414219558239f, 0.0062111844308674335f, 0.006622885353863239f, 0.009025324136018753f, 0.006490571890026331f, 0.005729694850742817f, 0.006043616682291031f, 0.005855721887201071f, 0.006370865274220705f, 0.006883370224386454f, 0.00662363413721323f, 0.006581841967999935f, 0.00920655857771635f, 0.006404058076441288f, 0.006264722440391779f, 0.0052740988321602345f, 0.006624510046094656f, 0.005534271243959665f, 0.006205209530889988f, 0.005827667191624641f, 0.00663659255951643f, 0.00783818680793047f, 0.00620707031339407f, 0.00552480248734355f, 0.006548302248120308f, 0.0062010702677071095f, 0.005977905821055174f, 0.004715679679065943f, 0.007249973714351654f, 0.007159956265240908f, 0.005635798443108797f, 0.005113867577165365f, 0.005099575500935316f, 0.006965534295886755f, 0.007116126827895641f, 0.0056719789281487465f, 0.006615929771214724f, 0.007543492130935192f, 0.008103973232209682f, 0.006802501622587442f, 0.005448644980788231f, 0.005260723177343607f, 0.006940319202840328f, 0.009157205000519753f, 0.007754559628665447f, 0.004386112093925476f, 0.006252675782889128f, 0.006045639049261808f, 0.007937372662127018f, 0.007713031489402056f, 0.005990542471408844f, 0.006173009984195232f, 0.010135332122445107f, 0.0049782563000917435f, 0.005638512782752514f, 0.005153363104909658f, 0.004725991282612085f, 0.005209297873079777f, 0.007528638932853937f, 0.006604738999158144f, 0.007158681750297546f, 0.00700625404715538f, 0.006421086844056845f), + AI_PACK_INTQ_ZP(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0))) -/* Tensor #6 */ -AI_TENSOR_OBJ_DECLARE( - conv2d_7_weights, AI_STATIC, - 6, 0x1, - AI_SHAPE_INIT(4, 52, 1, 1, 32), AI_STRIDE_INIT(4, 1, 52, 1664, 1664), - 1, &conv2d_7_weights_array, &conv2d_7_weights_array_intq) +/* Int quant #17 */ +AI_INTQ_INFO_LIST_OBJ_DECLARE(conv2d_6_weights_array_intq, AI_STATIC_CONST, + AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 128, + AI_PACK_INTQ_INFO( + AI_PACK_INTQ_SCALE(0.0018557497533038259f, 0.0019697360694408417f, 0.001281700562685728f, 0.0017718970775604248f, 0.0008174406830221415f, 0.0009432075312361121f, 0.0028168591670691967f, 0.001422902219928801f, 0.00219326582737267f, 0.0011972383363172412f, 0.0011589197674766183f, 0.00114688859321177f, 0.0011044482234865427f, 0.0006427131011150777f, 0.000714086287189275f, 0.0015932110836729407f, 0.000740832940209657f, 0.0011661351891234517f, 0.0009347975719720125f, 0.0010847835801541805f, 0.000992193934507668f, 0.00224536145105958f, 0.0012411768548190594f, 0.0006919921142980456f, 0.0009337405790574849f, 0.0018172890413552523f, 0.000772230327129364f, 0.0010150520829483867f, 0.0022945841774344444f, 0.0009880015859380364f, 0.0010042255744338036f, 0.0010933669982478023f, 0.0016199111705645919f, 0.0014156742254272103f, 0.0010755000403150916f, 0.000986542203463614f, 0.0009680194780230522f, 0.0014327361714094877f, 0.0008826737175695598f, 0.001293615554459393f, 0.0015390554908663034f, 0.0011125102173537016f, 0.0013994791079312563f, 0.000994575209915638f, 0.0008563583251088858f, 0.001552322180941701f, 0.0032914995681494474f, 0.001074036001227796f, 0.0015493474202230573f, 0.0011249857489019632f, 0.0022437593434005976f, 0.002379037206992507f, 0.0014761184575036168f, 0.0006319115636870265f, 0.0017460656818002462f, 0.0011261621257290244f, 0.0008294828003272414f, 0.0013167096767574549f, 0.000821223366074264f, 0.0010027452372014523f, 0.0008883592090569437f, 0.002817748812958598f, 0.0007955380133353174f, 0.002286104019731283f, 0.0015461265575140715f, 0.0010549556463956833f, 0.001901863724924624f, 0.0010173603659495711f, 0.0012700108345597982f, 0.0009987149387598038f, 0.0017363181104883552f, 0.0009356207447126508f, 0.001009973930194974f, 0.0012298672227188945f, 0.001345217227935791f, 0.0007689959020353854f, 0.0006722739199176431f, 0.0015942200552672148f, 0.0006541142938658595f, 0.001610899344086647f, 0.0007507021655328572f, 0.0019422005861997604f, 0.0022373127285391092f, 0.001235715695656836f, 0.0010806841310113668f, 0.0018573093693703413f, 0.0009882195154204965f, 0.0007961821393109858f, 0.0031550037674605846f, 0.002170284278690815f, 0.0012784553691744804f, 0.0013613274786621332f, 0.0008890038589015603f, 0.0022124156821519136f, 0.0009517221478745341f, 0.002033513505011797f, 0.0008631952805444598f, 0.0024063969030976295f, 0.0014647538773715496f, 0.001147877424955368f, 0.0013463121140375733f, 0.00084388890536502f, 0.0006916670827195048f, 0.0011224881745874882f, 0.0009460095898248255f, 0.0003961115435231477f, 0.0006100530736148357f, 0.0011333742877468467f, 0.001556956092827022f, 0.00090731744421646f, 0.0005625636549666524f, 0.000868237460963428f, 0.001043749856762588f, 0.0008480066899210215f, 0.0011449101148173213f, 0.0016275998204946518f, 0.0007904162048362195f, 0.0010955852922052145f, 0.0013093671295791864f, 0.0005245301872491837f, 0.0012891024816781282f, 0.001210867310874164f, 0.001898883725516498f, 0.0012688379501923919f, 0.0010299582500010729f, 0.0008273516432382166f, 0.0007908762781880796f, 0.0008760016062296927f), + AI_PACK_INTQ_ZP(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0))) -/* Tensor #7 */ -AI_TENSOR_OBJ_DECLARE( - conv2d_7_bias, AI_STATIC, - 7, 0x0, - AI_SHAPE_INIT(4, 1, 32, 1, 1), AI_STRIDE_INIT(4, 4, 4, 128, 128), - 1, &conv2d_7_bias_array, NULL) +/* Int quant #18 */ +AI_INTQ_INFO_LIST_OBJ_DECLARE(conv2d_7_weights_array_intq, AI_STATIC_CONST, + AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 32, + AI_PACK_INTQ_INFO( + AI_PACK_INTQ_SCALE(0.003594587091356516f, 0.003523685736581683f, 0.004047534428536892f, 0.0036098037380725145f, 0.004552087280899286f, 0.005163373425602913f, 0.005500015337020159f, 0.0034547788091003895f, 0.003286948660388589f, 0.004169492982327938f, 0.004871034529060125f, 0.004883585963398218f, 0.00534831453114748f, 0.005148332100361586f, 0.005452839657664299f, 0.0030656636226922274f, 0.0049522751942276955f, 0.004580425564199686f, 0.005363866686820984f, 0.005863618571311235f, 0.0073571763932704926f, 0.0054327342659235f, 0.0038320329040288925f, 0.0032939650118350983f, 0.0064551024697721004f, 0.00423980550840497f, 0.0026687399949878454f, 0.004822790622711182f, 0.0035204447340220213f, 0.004506547469645739f, 0.005991678684949875f, 0.004921582993119955f), + AI_PACK_INTQ_ZP(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0))) -/* Tensor #8 */ -AI_TENSOR_OBJ_DECLARE( - gemm_9_weights, AI_STATIC, - 8, 0x1, - AI_SHAPE_INIT(4, 32, 3, 1, 1), AI_STRIDE_INIT(4, 1, 32, 96, 96), - 1, &gemm_9_weights_array, &gemm_9_weights_array_intq) +/* Int quant #19 */ +AI_INTQ_INFO_LIST_OBJ_DECLARE(gemm_9_weights_array_intq, AI_STATIC_CONST, + AI_BUFFER_META_FLAG_SCALE_FLOAT|AI_BUFFER_META_FLAG_ZEROPOINT_S8, 1, + AI_PACK_INTQ_INFO( + AI_PACK_INTQ_SCALE(0.01042203139513731f), + AI_PACK_INTQ_ZP(0))) -/* Tensor #9 */ +/** Tensor declarations section *********************************************/ +/* Tensor #0 */ AI_TENSOR_OBJ_DECLARE( gemm_9_bias, AI_STATIC, - 9, 0x0, + 0, 0x0, AI_SHAPE_INIT(4, 1, 3, 1, 1), AI_STRIDE_INIT(4, 4, 4, 12, 12), 1, &gemm_9_bias_array, NULL) -/* Tensor #10 */ +/* Tensor #1 */ AI_TENSOR_OBJ_DECLARE( conv2d_0_scratch0, AI_STATIC, - 10, 0x0, + 1, 0x0, AI_SHAPE_INIT(4, 1, 761, 1, 1), AI_STRIDE_INIT(4, 1, 1, 761, 761), 1, &conv2d_0_scratch0_array, NULL) -/* Tensor #11 */ +/* Tensor #2 */ AI_TENSOR_OBJ_DECLARE( conv2d_1_scratch0, AI_STATIC, - 11, 0x0, - AI_SHAPE_INIT(4, 1, 1240, 1, 1), AI_STRIDE_INIT(4, 1, 1, 1240, 1240), + 2, 0x0, + AI_SHAPE_INIT(4, 1, 1440, 1, 1), AI_STRIDE_INIT(4, 1, 1, 1440, 1440), 1, &conv2d_1_scratch0_array, NULL) -/* Tensor #12 */ +/* Tensor #3 */ AI_TENSOR_OBJ_DECLARE( conv2d_2_scratch0, AI_STATIC, - 12, 0x0, - AI_SHAPE_INIT(4, 1, 2701, 1, 1), AI_STRIDE_INIT(4, 1, 1, 2701, 2701), + 3, 0x0, + AI_SHAPE_INIT(4, 1, 3201, 1, 1), AI_STRIDE_INIT(4, 1, 1, 3201, 3201), 1, &conv2d_2_scratch0_array, NULL) -/* Tensor #13 */ +/* Tensor #4 */ AI_TENSOR_OBJ_DECLARE( conv2d_3_scratch0, AI_STATIC, - 13, 0x0, - AI_SHAPE_INIT(4, 1, 1242, 1, 1), AI_STRIDE_INIT(4, 1, 1, 1242, 1242), + 4, 0x0, + AI_SHAPE_INIT(4, 1, 1792, 1, 1), AI_STRIDE_INIT(4, 1, 1, 1792, 1792), 1, &conv2d_3_scratch0_array, NULL) -/* Tensor #14 */ +/* Tensor #5 */ AI_TENSOR_OBJ_DECLARE( conv2d_4_scratch0, AI_STATIC, - 14, 0x0, - AI_SHAPE_INIT(4, 1, 3241, 1, 1), AI_STRIDE_INIT(4, 1, 1, 3241, 3241), + 5, 0x0, + AI_SHAPE_INIT(4, 1, 5121, 1, 1), AI_STRIDE_INIT(4, 1, 1, 5121, 5121), 1, &conv2d_4_scratch0_array, NULL) -/* Tensor #15 */ +/* Tensor #6 */ AI_TENSOR_OBJ_DECLARE( conv2d_5_scratch0, AI_STATIC, - 15, 0x0, - AI_SHAPE_INIT(4, 1, 844, 1, 1), AI_STRIDE_INIT(4, 1, 1, 844, 844), + 6, 0x0, + AI_SHAPE_INIT(4, 1, 1792, 1, 1), AI_STRIDE_INIT(4, 1, 1, 1792, 1792), 1, &conv2d_5_scratch0_array, NULL) -/* Tensor #16 */ +/* Tensor #7 */ AI_TENSOR_OBJ_DECLARE( conv2d_6_scratch0, AI_STATIC, - 16, 0x0, - AI_SHAPE_INIT(4, 1, 2861, 1, 1), AI_STRIDE_INIT(4, 1, 1, 2861, 2861), + 7, 0x0, + AI_SHAPE_INIT(4, 1, 7041, 1, 1), AI_STRIDE_INIT(4, 1, 1, 7041, 7041), 1, &conv2d_6_scratch0_array, NULL) -/* Tensor #17 */ +/* Tensor #8 */ AI_TENSOR_OBJ_DECLARE( conv2d_7_scratch0, AI_STATIC, - 17, 0x0, - AI_SHAPE_INIT(4, 1, 528, 1, 1), AI_STRIDE_INIT(4, 1, 1, 528, 528), + 8, 0x0, + AI_SHAPE_INIT(4, 1, 832, 1, 1), AI_STRIDE_INIT(4, 1, 1, 832, 832), 1, &conv2d_7_scratch0_array, NULL) -/* Tensor #18 */ +/* Tensor #9 */ AI_TENSOR_OBJ_DECLARE( gemm_9_scratch0, AI_STATIC, - 18, 0x0, + 9, 0x0, AI_SHAPE_INIT(4, 1, 32, 1, 1), AI_STRIDE_INIT(4, 2, 2, 64, 64), 1, &gemm_9_scratch0_array, NULL) -/* Tensor #19 */ +/* Tensor #10 */ AI_TENSOR_OBJ_DECLARE( serving_default_input_10_output, AI_STATIC, - 19, 0x1, + 10, 0x1, AI_SHAPE_INIT(4, 1, 40, 1, 30), AI_STRIDE_INIT(4, 1, 1, 40, 40), 1, &serving_default_input_10_output_array, &serving_default_input_10_output_array_intq) -/* Tensor #20 */ +/* Tensor #11 */ AI_TENSOR_OBJ_DECLARE( conv2d_0_output, AI_STATIC, - 20, 0x1, + 11, 0x1, AI_SHAPE_INIT(4, 1, 40, 1, 28), AI_STRIDE_INIT(4, 1, 1, 40, 40), 1, &conv2d_0_output_array, &conv2d_0_output_array_intq) -/* Tensor #21 */ +/* Tensor #12 */ AI_TENSOR_OBJ_DECLARE( conv2d_1_output, AI_STATIC, - 21, 0x1, - AI_SHAPE_INIT(4, 1, 108, 1, 28), AI_STRIDE_INIT(4, 1, 1, 108, 108), + 12, 0x1, + AI_SHAPE_INIT(4, 1, 128, 1, 28), AI_STRIDE_INIT(4, 1, 1, 128, 128), 1, &conv2d_1_output_array, &conv2d_1_output_array_intq) -/* Tensor #22 */ +/* Tensor #13 */ AI_TENSOR_OBJ_DECLARE( nl_10_scratch0, AI_STATIC, - 22, 0x0, + 13, 0x0, AI_SHAPE_INIT(4, 1, 124, 1, 1), AI_STRIDE_INIT(4, 4, 4, 496, 496), 1, &nl_10_scratch0_array, NULL) -/* Tensor #23 */ +/* Tensor #14 */ AI_TENSOR_OBJ_DECLARE( conv2d_2_output, AI_STATIC, - 23, 0x1, - AI_SHAPE_INIT(4, 1, 108, 1, 24), AI_STRIDE_INIT(4, 1, 1, 108, 108), + 14, 0x1, + AI_SHAPE_INIT(4, 1, 128, 1, 24), AI_STRIDE_INIT(4, 1, 1, 128, 128), 1, &conv2d_2_output_array, &conv2d_2_output_array_intq) -/* Tensor #24 */ +/* Tensor #15 */ AI_TENSOR_OBJ_DECLARE( conv2d_3_output, AI_STATIC, - 24, 0x1, - AI_SHAPE_INIT(4, 1, 81, 1, 24), AI_STRIDE_INIT(4, 1, 1, 81, 81), + 15, 0x1, + AI_SHAPE_INIT(4, 1, 128, 1, 24), AI_STRIDE_INIT(4, 1, 1, 128, 128), 1, &conv2d_3_output_array, &conv2d_3_output_array_intq) -/* Tensor #25 */ +/* Tensor #16 */ AI_TENSOR_OBJ_DECLARE( conv2d_4_output, AI_STATIC, - 25, 0x1, - AI_SHAPE_INIT(4, 1, 81, 1, 15), AI_STRIDE_INIT(4, 1, 1, 81, 81), + 16, 0x1, + AI_SHAPE_INIT(4, 1, 128, 1, 15), AI_STRIDE_INIT(4, 1, 1, 128, 128), 1, &conv2d_4_output_array, &conv2d_4_output_array_intq) -/* Tensor #26 */ +/* Tensor #17 */ AI_TENSOR_OBJ_DECLARE( conv2d_5_output, AI_STATIC, - 26, 0x1, - AI_SHAPE_INIT(4, 1, 52, 1, 15), AI_STRIDE_INIT(4, 1, 1, 52, 52), + 17, 0x1, + AI_SHAPE_INIT(4, 1, 128, 1, 15), AI_STRIDE_INIT(4, 1, 1, 128, 128), 1, &conv2d_5_output_array, &conv2d_5_output_array_intq) -/* Tensor #27 */ +/* Tensor #18 */ AI_TENSOR_OBJ_DECLARE( conv2d_6_output, AI_STATIC, - 27, 0x1, - AI_SHAPE_INIT(4, 1, 52, 1, 1), AI_STRIDE_INIT(4, 1, 1, 52, 52), + 18, 0x1, + AI_SHAPE_INIT(4, 1, 128, 1, 1), AI_STRIDE_INIT(4, 1, 1, 128, 128), 1, &conv2d_6_output_array, &conv2d_6_output_array_intq) -/* Tensor #28 */ +/* Tensor #19 */ AI_TENSOR_OBJ_DECLARE( conv2d_7_output, AI_STATIC, - 28, 0x1, + 19, 0x1, AI_SHAPE_INIT(4, 1, 32, 1, 1), AI_STRIDE_INIT(4, 1, 1, 32, 32), 1, &conv2d_7_output_array, &conv2d_7_output_array_intq) -/* Tensor #29 */ +/* Tensor #20 */ AI_TENSOR_OBJ_DECLARE( gemm_9_output, AI_STATIC, - 29, 0x1, + 20, 0x1, AI_SHAPE_INIT(4, 1, 3, 1, 1), AI_STRIDE_INIT(4, 1, 1, 3, 3), 1, &gemm_9_output_array, &gemm_9_output_array_intq) -/* Tensor #30 */ +/* Tensor #21 */ AI_TENSOR_OBJ_DECLARE( nl_10_output, AI_STATIC, - 30, 0x1, + 21, 0x1, AI_SHAPE_INIT(4, 1, 3, 1, 1), AI_STRIDE_INIT(4, 1, 1, 3, 3), 1, &nl_10_output_array, &nl_10_output_array_intq) -/* Tensor #31 */ +/* Tensor #22 */ AI_TENSOR_OBJ_DECLARE( conv2d_0_weights, AI_STATIC, - 31, 0x1, + 22, 0x1, AI_SHAPE_INIT(4, 40, 1, 3, 1), AI_STRIDE_INIT(4, 1, 40, 40, 40), 1, &conv2d_0_weights_array, &conv2d_0_weights_array_intq) -/* Tensor #32 */ +/* Tensor #23 */ AI_TENSOR_OBJ_DECLARE( conv2d_0_bias, AI_STATIC, - 32, 0x0, + 23, 0x0, AI_SHAPE_INIT(4, 1, 40, 1, 1), AI_STRIDE_INIT(4, 4, 4, 160, 160), 1, &conv2d_0_bias_array, NULL) -/* Tensor #33 */ +/* Tensor #24 */ AI_TENSOR_OBJ_DECLARE( conv2d_1_weights, AI_STATIC, - 33, 0x1, - AI_SHAPE_INIT(4, 40, 1, 1, 108), AI_STRIDE_INIT(4, 1, 40, 4320, 4320), + 24, 0x1, + AI_SHAPE_INIT(4, 40, 1, 1, 128), AI_STRIDE_INIT(4, 1, 40, 5120, 5120), 1, &conv2d_1_weights_array, &conv2d_1_weights_array_intq) -/* Tensor #34 */ +/* Tensor #25 */ AI_TENSOR_OBJ_DECLARE( conv2d_1_bias, AI_STATIC, - 34, 0x0, - AI_SHAPE_INIT(4, 1, 108, 1, 1), AI_STRIDE_INIT(4, 4, 4, 432, 432), + 25, 0x0, + AI_SHAPE_INIT(4, 1, 128, 1, 1), AI_STRIDE_INIT(4, 4, 4, 512, 512), 1, &conv2d_1_bias_array, NULL) -/* Tensor #35 */ +/* Tensor #26 */ AI_TENSOR_OBJ_DECLARE( conv2d_2_weights, AI_STATIC, - 35, 0x1, - AI_SHAPE_INIT(4, 108, 1, 5, 1), AI_STRIDE_INIT(4, 1, 108, 108, 108), + 26, 0x1, + AI_SHAPE_INIT(4, 128, 1, 5, 1), AI_STRIDE_INIT(4, 1, 128, 128, 128), 1, &conv2d_2_weights_array, &conv2d_2_weights_array_intq) -/* Tensor #36 */ +/* Tensor #27 */ AI_TENSOR_OBJ_DECLARE( conv2d_2_bias, AI_STATIC, - 36, 0x0, - AI_SHAPE_INIT(4, 1, 108, 1, 1), AI_STRIDE_INIT(4, 4, 4, 432, 432), + 27, 0x0, + AI_SHAPE_INIT(4, 1, 128, 1, 1), AI_STRIDE_INIT(4, 4, 4, 512, 512), 1, &conv2d_2_bias_array, NULL) -/* Tensor #37 */ +/* Tensor #28 */ AI_TENSOR_OBJ_DECLARE( conv2d_3_weights, AI_STATIC, - 37, 0x1, - AI_SHAPE_INIT(4, 108, 1, 1, 81), AI_STRIDE_INIT(4, 1, 108, 8748, 8748), + 28, 0x1, + AI_SHAPE_INIT(4, 128, 1, 1, 128), AI_STRIDE_INIT(4, 1, 128, 16384, 16384), 1, &conv2d_3_weights_array, &conv2d_3_weights_array_intq) -/* Tensor #38 */ +/* Tensor #29 */ AI_TENSOR_OBJ_DECLARE( conv2d_3_bias, AI_STATIC, - 38, 0x0, - AI_SHAPE_INIT(4, 1, 81, 1, 1), AI_STRIDE_INIT(4, 4, 4, 324, 324), + 29, 0x0, + AI_SHAPE_INIT(4, 1, 128, 1, 1), AI_STRIDE_INIT(4, 4, 4, 512, 512), 1, &conv2d_3_bias_array, NULL) +/* Tensor #30 */ +AI_TENSOR_OBJ_DECLARE( + conv2d_4_weights, AI_STATIC, + 30, 0x1, + AI_SHAPE_INIT(4, 128, 1, 10, 1), AI_STRIDE_INIT(4, 1, 128, 128, 128), + 1, &conv2d_4_weights_array, &conv2d_4_weights_array_intq) + +/* Tensor #31 */ +AI_TENSOR_OBJ_DECLARE( + conv2d_4_bias, AI_STATIC, + 31, 0x0, + AI_SHAPE_INIT(4, 1, 128, 1, 1), AI_STRIDE_INIT(4, 4, 4, 512, 512), + 1, &conv2d_4_bias_array, NULL) + +/* Tensor #32 */ +AI_TENSOR_OBJ_DECLARE( + conv2d_5_weights, AI_STATIC, + 32, 0x1, + AI_SHAPE_INIT(4, 128, 1, 1, 128), AI_STRIDE_INIT(4, 1, 128, 16384, 16384), + 1, &conv2d_5_weights_array, &conv2d_5_weights_array_intq) + +/* Tensor #33 */ +AI_TENSOR_OBJ_DECLARE( + conv2d_5_bias, AI_STATIC, + 33, 0x0, + AI_SHAPE_INIT(4, 1, 128, 1, 1), AI_STRIDE_INIT(4, 4, 4, 512, 512), + 1, &conv2d_5_bias_array, NULL) + +/* Tensor #34 */ +AI_TENSOR_OBJ_DECLARE( + conv2d_6_weights, AI_STATIC, + 34, 0x1, + AI_SHAPE_INIT(4, 128, 1, 15, 1), AI_STRIDE_INIT(4, 1, 128, 128, 128), + 1, &conv2d_6_weights_array, &conv2d_6_weights_array_intq) + +/* Tensor #35 */ +AI_TENSOR_OBJ_DECLARE( + conv2d_6_bias, AI_STATIC, + 35, 0x0, + AI_SHAPE_INIT(4, 1, 128, 1, 1), AI_STRIDE_INIT(4, 4, 4, 512, 512), + 1, &conv2d_6_bias_array, NULL) + +/* Tensor #36 */ +AI_TENSOR_OBJ_DECLARE( + conv2d_7_weights, AI_STATIC, + 36, 0x1, + AI_SHAPE_INIT(4, 128, 1, 1, 32), AI_STRIDE_INIT(4, 1, 128, 4096, 4096), + 1, &conv2d_7_weights_array, &conv2d_7_weights_array_intq) + +/* Tensor #37 */ +AI_TENSOR_OBJ_DECLARE( + conv2d_7_bias, AI_STATIC, + 37, 0x0, + AI_SHAPE_INIT(4, 1, 32, 1, 1), AI_STRIDE_INIT(4, 4, 4, 128, 128), + 1, &conv2d_7_bias_array, NULL) + +/* Tensor #38 */ +AI_TENSOR_OBJ_DECLARE( + gemm_9_weights, AI_STATIC, + 38, 0x1, + AI_SHAPE_INIT(4, 32, 3, 1, 1), AI_STRIDE_INIT(4, 1, 32, 96, 96), + 1, &gemm_9_weights_array, &gemm_9_weights_array_intq) + /** Layer declarations section **********************************************/ -AI_STATIC_CONST ai_i32 nl_10_nl_params_data[] = { 1263631360, 24, -124 }; +AI_STATIC_CONST ai_i32 nl_10_nl_params_data[] = { 1378760960, 24, -124 }; AI_ARRAY_OBJ_DECLARE( nl_10_nl_params, AI_ARRAY_FORMAT_S32, nl_10_nl_params_data, nl_10_nl_params_data, 3, AI_STATIC_CONST) @@ -745,7 +745,7 @@ AI_LAYER_OBJ_DECLARE( conv2d, forward_dw_sssa8_ch, &conv2d_6_chain, NULL, &conv2d_7_layer, AI_STATIC, - .groups = 52, + .groups = 128, .filter_stride = AI_SHAPE_2D_INIT(1, 1), .dilation = AI_SHAPE_2D_INIT(1, 1), .filter_pad = AI_SHAPE_INIT(4, 0, 0, 0, 0), @@ -789,7 +789,7 @@ AI_LAYER_OBJ_DECLARE( conv2d, forward_dw_sssa8_ch, &conv2d_4_chain, NULL, &conv2d_5_layer, AI_STATIC, - .groups = 81, + .groups = 128, .filter_stride = AI_SHAPE_2D_INIT(1, 1), .dilation = AI_SHAPE_2D_INIT(1, 1), .filter_pad = AI_SHAPE_INIT(4, 0, 0, 0, 0), @@ -833,7 +833,7 @@ AI_LAYER_OBJ_DECLARE( conv2d, forward_dw_sssa8_ch, &conv2d_2_chain, NULL, &conv2d_3_layer, AI_STATIC, - .groups = 108, + .groups = 128, .filter_stride = AI_SHAPE_2D_INIT(1, 1), .dilation = AI_SHAPE_2D_INIT(1, 1), .filter_pad = AI_SHAPE_INIT(4, 0, 0, 0, 0), @@ -891,14 +891,14 @@ AI_LAYER_OBJ_DECLARE( AI_NETWORK_OBJ_DECLARE( AI_NET_OBJ_INSTANCE, AI_STATIC, AI_BUFFER_INIT(AI_FLAG_NONE, AI_BUFFER_FORMAT_U8, - AI_BUFFER_SHAPE_INIT(AI_SHAPE_BCWH, 4, 1, 23520, 1, 1), - 23520, NULL, NULL), + AI_BUFFER_SHAPE_INIT(AI_SHAPE_BCWH, 4, 1, 49412, 1, 1), + 49412, NULL, NULL), AI_BUFFER_INIT(AI_FLAG_NONE, AI_BUFFER_FORMAT_U8, - AI_BUFFER_SHAPE_INIT(AI_SHAPE_BCWH, 4, 1, 5836, 1, 1), - 5836, NULL, NULL), + AI_BUFFER_SHAPE_INIT(AI_SHAPE_BCWH, 4, 1, 10116, 1, 1), + 10116, NULL, NULL), AI_TENSOR_LIST_IO_OBJ_INIT(AI_FLAG_NONE, AI_SWW_MODEL_IN_NUM, &serving_default_input_10_output), AI_TENSOR_LIST_IO_OBJ_INIT(AI_FLAG_NONE, AI_SWW_MODEL_OUT_NUM, &nl_10_output), - &conv2d_0_layer, 0x437a6e35, NULL) + &conv2d_0_layer, 0xb09d6657, NULL) #else @@ -907,18 +907,18 @@ AI_NETWORK_OBJ_DECLARE( AI_BUFFER_ARRAY_OBJ_INIT_STATIC( AI_FLAG_NONE, 1, AI_BUFFER_INIT(AI_FLAG_NONE, AI_BUFFER_FORMAT_U8, - AI_BUFFER_SHAPE_INIT(AI_SHAPE_BCWH, 4, 1, 23520, 1, 1), - 23520, NULL, NULL) + AI_BUFFER_SHAPE_INIT(AI_SHAPE_BCWH, 4, 1, 49412, 1, 1), + 49412, NULL, NULL) ), AI_BUFFER_ARRAY_OBJ_INIT_STATIC( AI_FLAG_NONE, 1, AI_BUFFER_INIT(AI_FLAG_NONE, AI_BUFFER_FORMAT_U8, - AI_BUFFER_SHAPE_INIT(AI_SHAPE_BCWH, 4, 1, 5836, 1, 1), - 5836, NULL, NULL) + AI_BUFFER_SHAPE_INIT(AI_SHAPE_BCWH, 4, 1, 10116, 1, 1), + 10116, NULL, NULL) ), AI_TENSOR_LIST_IO_OBJ_INIT(AI_FLAG_NONE, AI_SWW_MODEL_IN_NUM, &serving_default_input_10_output), AI_TENSOR_LIST_IO_OBJ_INIT(AI_FLAG_NONE, AI_SWW_MODEL_OUT_NUM, &nl_10_output), - &conv2d_0_layer, 0x437a6e35, NULL) + &conv2d_0_layer, 0xb09d6657, NULL) #endif /*(AI_TOOLS_API_VERSION < AI_TOOLS_API_VERSION_1_5)*/ @@ -934,40 +934,40 @@ ai_bool sww_model_configure_activations( if (ai_platform_get_activations_map(g_sww_model_activations_map, 1, params)) { /* Updating activations (byte) offsets */ - serving_default_input_10_output_array.data = AI_PTR(g_sww_model_activations_map[0] + 2160); - serving_default_input_10_output_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 2160); - conv2d_0_scratch0_array.data = AI_PTR(g_sww_model_activations_map[0] + 3360); - conv2d_0_scratch0_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 3360); - conv2d_0_output_array.data = AI_PTR(g_sww_model_activations_map[0] + 2120); - conv2d_0_output_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 2120); - conv2d_1_scratch0_array.data = AI_PTR(g_sww_model_activations_map[0] + 3240); - conv2d_1_scratch0_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 3240); - conv2d_1_output_array.data = AI_PTR(g_sww_model_activations_map[0] + 108); - conv2d_1_output_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 108); - conv2d_2_scratch0_array.data = AI_PTR(g_sww_model_activations_map[0] + 3132); - conv2d_2_scratch0_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 3132); - conv2d_2_output_array.data = AI_PTR(g_sww_model_activations_map[0] + 0); - conv2d_2_output_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 0); - conv2d_3_scratch0_array.data = AI_PTR(g_sww_model_activations_map[0] + 2592); - conv2d_3_scratch0_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 2592); - conv2d_3_output_array.data = AI_PTR(g_sww_model_activations_map[0] + 3836); - conv2d_3_output_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 3836); - conv2d_4_scratch0_array.data = AI_PTR(g_sww_model_activations_map[0] + 0); - conv2d_4_scratch0_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 0); - conv2d_4_output_array.data = AI_PTR(g_sww_model_activations_map[0] + 3752); - conv2d_4_output_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 3752); - conv2d_5_scratch0_array.data = AI_PTR(g_sww_model_activations_map[0] + 0); - conv2d_5_scratch0_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 0); - conv2d_5_output_array.data = AI_PTR(g_sww_model_activations_map[0] + 844); - conv2d_5_output_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 844); - conv2d_6_scratch0_array.data = AI_PTR(g_sww_model_activations_map[0] + 1624); - conv2d_6_scratch0_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 1624); - conv2d_6_output_array.data = AI_PTR(g_sww_model_activations_map[0] + 0); - conv2d_6_output_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 0); - conv2d_7_scratch0_array.data = AI_PTR(g_sww_model_activations_map[0] + 52); - conv2d_7_scratch0_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 52); - conv2d_7_output_array.data = AI_PTR(g_sww_model_activations_map[0] + 580); - conv2d_7_output_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 580); + serving_default_input_10_output_array.data = AI_PTR(g_sww_model_activations_map[0] + 1892); + serving_default_input_10_output_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 1892); + conv2d_0_scratch0_array.data = AI_PTR(g_sww_model_activations_map[0] + 3092); + conv2d_0_scratch0_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 3092); + conv2d_0_output_array.data = AI_PTR(g_sww_model_activations_map[0] + 772); + conv2d_0_output_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 772); + conv2d_1_scratch0_array.data = AI_PTR(g_sww_model_activations_map[0] + 1892); + conv2d_1_scratch0_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 1892); + conv2d_1_output_array.data = AI_PTR(g_sww_model_activations_map[0] + 3332); + conv2d_1_output_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 3332); + conv2d_2_scratch0_array.data = AI_PTR(g_sww_model_activations_map[0] + 128); + conv2d_2_scratch0_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 128); + conv2d_2_output_array.data = AI_PTR(g_sww_model_activations_map[0] + 6916); + conv2d_2_output_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 6916); + conv2d_3_scratch0_array.data = AI_PTR(g_sww_model_activations_map[0] + 128); + conv2d_3_scratch0_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 128); + conv2d_3_output_array.data = AI_PTR(g_sww_model_activations_map[0] + 1920); + conv2d_3_output_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 1920); + conv2d_4_scratch0_array.data = AI_PTR(g_sww_model_activations_map[0] + 4992); + conv2d_4_scratch0_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 4992); + conv2d_4_output_array.data = AI_PTR(g_sww_model_activations_map[0] + 0); + conv2d_4_output_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 0); + conv2d_5_scratch0_array.data = AI_PTR(g_sww_model_activations_map[0] + 1920); + conv2d_5_scratch0_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 1920); + conv2d_5_output_array.data = AI_PTR(g_sww_model_activations_map[0] + 8192); + conv2d_5_output_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 8192); + conv2d_6_scratch0_array.data = AI_PTR(g_sww_model_activations_map[0] + 0); + conv2d_6_scratch0_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 0); + conv2d_6_output_array.data = AI_PTR(g_sww_model_activations_map[0] + 7044); + conv2d_6_output_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 7044); + conv2d_7_scratch0_array.data = AI_PTR(g_sww_model_activations_map[0] + 0); + conv2d_7_scratch0_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 0); + conv2d_7_output_array.data = AI_PTR(g_sww_model_activations_map[0] + 832); + conv2d_7_output_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 832); gemm_9_scratch0_array.data = AI_PTR(g_sww_model_activations_map[0] + 0); gemm_9_scratch0_array.data_start = AI_PTR(g_sww_model_activations_map[0] + 0); gemm_9_output_array.data = AI_PTR(g_sww_model_activations_map[0] + 64); @@ -1005,50 +1005,50 @@ ai_bool sww_model_configure_weights( conv2d_1_weights_array.data = AI_PTR(g_sww_model_weights_map[0] + 280); conv2d_1_weights_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 280); conv2d_1_bias_array.format |= AI_FMT_FLAG_CONST; - conv2d_1_bias_array.data = AI_PTR(g_sww_model_weights_map[0] + 4600); - conv2d_1_bias_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 4600); + conv2d_1_bias_array.data = AI_PTR(g_sww_model_weights_map[0] + 5400); + conv2d_1_bias_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 5400); conv2d_2_weights_array.format |= AI_FMT_FLAG_CONST; - conv2d_2_weights_array.data = AI_PTR(g_sww_model_weights_map[0] + 5032); - conv2d_2_weights_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 5032); + conv2d_2_weights_array.data = AI_PTR(g_sww_model_weights_map[0] + 5912); + conv2d_2_weights_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 5912); conv2d_2_bias_array.format |= AI_FMT_FLAG_CONST; - conv2d_2_bias_array.data = AI_PTR(g_sww_model_weights_map[0] + 5572); - conv2d_2_bias_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 5572); + conv2d_2_bias_array.data = AI_PTR(g_sww_model_weights_map[0] + 6552); + conv2d_2_bias_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 6552); conv2d_3_weights_array.format |= AI_FMT_FLAG_CONST; - conv2d_3_weights_array.data = AI_PTR(g_sww_model_weights_map[0] + 6004); - conv2d_3_weights_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 6004); + conv2d_3_weights_array.data = AI_PTR(g_sww_model_weights_map[0] + 7064); + conv2d_3_weights_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 7064); conv2d_3_bias_array.format |= AI_FMT_FLAG_CONST; - conv2d_3_bias_array.data = AI_PTR(g_sww_model_weights_map[0] + 14752); - conv2d_3_bias_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 14752); + conv2d_3_bias_array.data = AI_PTR(g_sww_model_weights_map[0] + 23448); + conv2d_3_bias_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 23448); conv2d_4_weights_array.format |= AI_FMT_FLAG_CONST; - conv2d_4_weights_array.data = AI_PTR(g_sww_model_weights_map[0] + 15076); - conv2d_4_weights_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 15076); + conv2d_4_weights_array.data = AI_PTR(g_sww_model_weights_map[0] + 23960); + conv2d_4_weights_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 23960); conv2d_4_bias_array.format |= AI_FMT_FLAG_CONST; - conv2d_4_bias_array.data = AI_PTR(g_sww_model_weights_map[0] + 15888); - conv2d_4_bias_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 15888); + conv2d_4_bias_array.data = AI_PTR(g_sww_model_weights_map[0] + 25240); + conv2d_4_bias_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 25240); conv2d_5_weights_array.format |= AI_FMT_FLAG_CONST; - conv2d_5_weights_array.data = AI_PTR(g_sww_model_weights_map[0] + 16212); - conv2d_5_weights_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 16212); + conv2d_5_weights_array.data = AI_PTR(g_sww_model_weights_map[0] + 25752); + conv2d_5_weights_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 25752); conv2d_5_bias_array.format |= AI_FMT_FLAG_CONST; - conv2d_5_bias_array.data = AI_PTR(g_sww_model_weights_map[0] + 20424); - conv2d_5_bias_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 20424); + conv2d_5_bias_array.data = AI_PTR(g_sww_model_weights_map[0] + 42136); + conv2d_5_bias_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 42136); conv2d_6_weights_array.format |= AI_FMT_FLAG_CONST; - conv2d_6_weights_array.data = AI_PTR(g_sww_model_weights_map[0] + 20632); - conv2d_6_weights_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 20632); + conv2d_6_weights_array.data = AI_PTR(g_sww_model_weights_map[0] + 42648); + conv2d_6_weights_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 42648); conv2d_6_bias_array.format |= AI_FMT_FLAG_CONST; - conv2d_6_bias_array.data = AI_PTR(g_sww_model_weights_map[0] + 21412); - conv2d_6_bias_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 21412); + conv2d_6_bias_array.data = AI_PTR(g_sww_model_weights_map[0] + 44568); + conv2d_6_bias_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 44568); conv2d_7_weights_array.format |= AI_FMT_FLAG_CONST; - conv2d_7_weights_array.data = AI_PTR(g_sww_model_weights_map[0] + 21620); - conv2d_7_weights_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 21620); + conv2d_7_weights_array.data = AI_PTR(g_sww_model_weights_map[0] + 45080); + conv2d_7_weights_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 45080); conv2d_7_bias_array.format |= AI_FMT_FLAG_CONST; - conv2d_7_bias_array.data = AI_PTR(g_sww_model_weights_map[0] + 23284); - conv2d_7_bias_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 23284); + conv2d_7_bias_array.data = AI_PTR(g_sww_model_weights_map[0] + 49176); + conv2d_7_bias_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 49176); gemm_9_weights_array.format |= AI_FMT_FLAG_CONST; - gemm_9_weights_array.data = AI_PTR(g_sww_model_weights_map[0] + 23412); - gemm_9_weights_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 23412); + gemm_9_weights_array.data = AI_PTR(g_sww_model_weights_map[0] + 49304); + gemm_9_weights_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 49304); gemm_9_bias_array.format |= AI_FMT_FLAG_CONST; - gemm_9_bias_array.data = AI_PTR(g_sww_model_weights_map[0] + 23508); - gemm_9_bias_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 23508); + gemm_9_bias_array.data = AI_PTR(g_sww_model_weights_map[0] + 49400); + gemm_9_bias_array.data_start = AI_PTR(g_sww_model_weights_map[0] + 49400); return true; } AI_ERROR_TRAP(net_ctx, INIT_FAILED, NETWORK_WEIGHTS); @@ -1087,7 +1087,7 @@ ai_bool ai_sww_model_get_info( .api_version = ai_platform_api_get_version(), .interface_api_version = ai_platform_interface_api_get_version(), - .n_macc = 652551, + .n_macc = 827256, .n_inputs = 0, .inputs = NULL, .n_outputs = 0, @@ -1095,7 +1095,7 @@ ai_bool ai_sww_model_get_info( .params = AI_STRUCT_INIT, .activations = AI_STRUCT_INIT, .n_nodes = 0, - .signature = 0x437a6e35, + .signature = 0xb09d6657, }; if (!ai_platform_api_get_network_report(network, &r)) return false; @@ -1134,7 +1134,7 @@ ai_bool ai_sww_model_get_report( .api_version = ai_platform_api_get_version(), .interface_api_version = ai_platform_interface_api_get_version(), - .n_macc = 652551, + .n_macc = 827256, .n_inputs = 0, .inputs = NULL, .n_outputs = 0, @@ -1143,7 +1143,7 @@ ai_bool ai_sww_model_get_report( .map_weights = AI_STRUCT_INIT, .map_activations = AI_STRUCT_INIT, .n_nodes = 0, - .signature = 0x437a6e35, + .signature = 0xb09d6657, }; if (!ai_platform_api_get_network_report(network, &r)) return false; diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model.h similarity index 98% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model.h index 9060d103..6a5a9716 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file sww_model.h * @author AST Embedded Analytics Research Platform - * @date 2025-01-19T06:26:52-0500 + * @date 2025-05-22T12:16:33-0700 * @brief AI Tool Automatic Code Generator for Embedded NN computing ****************************************************************************** * @attention @@ -23,7 +23,7 @@ /******************************************************************************/ #define AI_SWW_MODEL_MODEL_NAME "sww_model" -#define AI_SWW_MODEL_ORIGIN_MODEL_NAME "strm_ww_int8" +#define AI_SWW_MODEL_ORIGIN_MODEL_NAME "str_ww_ref_model" /******************************************************************************/ #define AI_SWW_MODEL_ACTIVATIONS_ALIGNMENT (4) diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model_config.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model_config.h similarity index 97% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model_config.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model_config.h index 92eea111..0c2f520b 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model_config.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model_config.h @@ -3,7 +3,7 @@ ****************************************************************************** * @file sww_model_config.h * @author AST Embedded Analytics Research Platform - * @date 2025-01-19T06:26:52-0500 + * @date 2025-05-22T12:16:33-0700 * @brief AI Tool Automatic Code Generator for Custom Layers Implementation ****************************************************************************** * @attention diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model_data.c b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model_data.c similarity index 92% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model_data.c rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model_data.c index 0b1c4381..52623c60 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model_data.c +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model_data.c @@ -2,7 +2,7 @@ ****************************************************************************** * @file sww_model_data.c * @author AST Embedded Analytics Research Platform - * @date 2025-01-19T06:26:52-0500 + * @date 2025-05-22T12:16:33-0700 * @brief AI Tool Automatic Code Generator for Embedded NN computing ****************************************************************************** * @attention @@ -21,13 +21,13 @@ AI_API_DECLARE_BEGIN ai_buffer g_sww_model_data_map_activations[AI_SWW_MODEL_DATA_ACTIVATIONS_COUNT] = { AI_BUFFER_INIT(AI_FLAG_NONE, AI_BUFFER_FORMAT_U8, - AI_BUFFER_SHAPE_INIT(AI_SHAPE_BCWH, 4, 1, 5836, 1, 1), - 5836, NULL, NULL), /* heap_overlay_pool */ + AI_BUFFER_SHAPE_INIT(AI_SHAPE_BCWH, 4, 1, 10116, 1, 1), + 10116, NULL, NULL), /* heap_overlay_pool */ }; ai_buffer g_sww_model_data_map_weights[AI_SWW_MODEL_DATA_WEIGHTS_COUNT] = { AI_BUFFER_INIT(AI_FLAG_NONE, AI_BUFFER_FORMAT_U8, - AI_BUFFER_SHAPE_INIT(AI_SHAPE_BCWH, 4, 1, 23520, 1, 1), - 23520, NULL, s_sww_model_weights_array_u64), /* weights_array */ + AI_BUFFER_SHAPE_INIT(AI_SHAPE_BCWH, 4, 1, 49412, 1, 1), + 49412, NULL, s_sww_model_weights_array_u64), /* weights_array */ }; diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model_data.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model_data.h similarity index 95% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model_data.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model_data.h index 793c0d1e..449f011b 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model_data.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model_data.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file sww_model_data.h * @author AST Embedded Analytics Research Platform - * @date 2025-01-19T06:26:52-0500 + * @date 2025-05-22T12:16:33-0700 * @brief AI Tool Automatic Code Generator for Embedded NN computing ****************************************************************************** * Copyright (c) 2025 STMicroelectronics. @@ -32,7 +32,7 @@ AI_DEPRECATED AI_API_DECLARE_BEGIN -extern const ai_u64 s_sww_model_weights_array_u64[2940]; +extern const ai_u64 s_sww_model_weights_array_u64[6177]; diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model_data_params.c b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model_data_params.c new file mode 100644 index 00000000..0cfd7e7e --- /dev/null +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model_data_params.c @@ -0,0 +1,1586 @@ +/** + ****************************************************************************** + * @file sww_model_data_params.c + * @author AST Embedded Analytics Research Platform + * @date 2025-05-22T12:16:33-0700 + * @brief AI Tool Automatic Code Generator for Embedded NN computing + ****************************************************************************** + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +#include "sww_model_data_params.h" + + +/** Activations Section ****************************************************/ +ai_handle g_sww_model_activations_table[1 + 2] = { + AI_HANDLE_PTR(AI_MAGIC_MARKER), + AI_HANDLE_PTR(NULL), + AI_HANDLE_PTR(AI_MAGIC_MARKER), +}; + + + + +/** Weights Section ********************************************************/ +AI_ALIGNED(32) +const ai_u64 s_sww_model_weights_array_u64[6177] = { + 0x7f0a2fcd147f997fU, 0x8c6281b2ffbeab1cU, 0x64b444811413ca6dU, 0x7fae7fe622a60216U, + 0xf294c57fb1927f29U, 0x467f7f7f81d6e45bU, 0x817f3a812b818181U, 0xa081ce2a267f93d6U, + 0xca41eaa1e4217f81U, 0x328107ebe426c97fU, 0x88e90527f9c8818bU, 0xae86ea3d815222f3U, + 0x81638160810b7f81U, 0x897f4a7f817fe3ffU, 0x7f757f94817fa2d9U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0xd7b3fa18106f767eU, + 0x2101f9c3e5132cc6U, 0x912cbb95f105433aU, 0x2a81be103eb95ac9U, 0x7ad9a93402cd3300U, + 0xdf122da93b52337fU, 0x28d8d44003c6a1baU, 0xf8ca18270abae7f1U, 0x2af63007c2d7dd2dU, + 0xd14d4fb0ec55162U, 0x13e819d324290026U, 0xed1f81c4305f1232U, 0x290a8736adf93bffU, + 0xb741280839f7e356U, 0xc9e406300bc713f3U, 0xe2e248d1440efe36U, 0xbdc3f90ceef92010U, + 0xb3ca0ca10820f61cU, 0xdbf7cc1927c5f812U, 0xb2a52b81eb33abbdU, 0xdaa2e639a4f815e1U, + 0xdc2eceddeb312f40U, 0xc80db553ffd0d4eaU, 0xd8082ce42681d02fU, 0xe60016e14b37b720U, + 0x22290a814278d2ddU, 0x486864101186d2beU, 0xc862bbe608f9e4edU, 0x8405d84dc6f67f2aU, + 0x15dfcd2331f5d919U, 0xcdcded45bcd70bcfU, 0x30d2f38f4e02ae0U, 0xc92711bc00ea9ef0U, + 0x9b76031a081500b5U, 0xe61da37ff244273cU, 0xaf20db741bddf13cU, 0x1e81353416cdfc47U, + 0xd499f704d43aefb1U, 0x3105c4efd51f19f9U, 0x3564c4c4210ef9fcU, 0xc91f1bed4608ccf0U, + 0xa11fbbf34abdf12U, 0x51cae0dacbb37f94U, 0x15ceed23da550b4dU, 0xf1d93cc9edbed91cU, + 0xd4b1d381503cbd21U, 0xfb484c217c8041cU, 0x52dfdf2d3e8f5cdU, 0xe50e2607e5f4f620U, + 0xe4c45d30c2d14eeU, 0xefe40ed51b7f0743U, 0x3f2f6e608161651U, 0xcf3c11a1905daU, + 0xee0aebd61ce5e00dU, 0x1f04ff27f5f43330U, 0x7e8f53fe1afe2f8U, 0x22ea9b02f3f61d7fU, + 0xf44317f8191dd61cU, 0xf7ea363506cd32feU, 0xd2f32004a9ca0ee6U, 0x10043bd41bc207f2U, + 0x1101df81fad8573cU, 0x77089146911848edU, 0xc1a3cdbfec06e727U, 0xbaf852d1ab37c660U, + 0xffebfd19df2e1efdU, 0xd118ed260142f91bU, 0xe003f9e1fe0c2631U, 0xd0cf0c39f3ddf910U, + 0xef350ac121fb81d1U, 0xfde5200e4ada3d41U, 0x660df1b1c1ecc93eU, 0xa0caf7db73278521U, + 0xd919b61f1227f93U, 0x2bdfa5a2b702e393U, 0xebdd35021a3b07d7U, 0x3bbf21bfc1fef1cU, + 0x1af810ded92beed9U, 0xe029b5f32e0810f5U, 0xe68114fdd032f71dU, 0x7e4ec0d7fe0cf415U, + 0xd3df591700f2d9ffU, 0x4f01f08ff2a1519U, 0x65bf53fdd7db9ce7U, 0xc9e03891f67ff42aU, + 0xe681fc49d8f1c411U, 0x4a05e50039ebafcbU, 0xeae0210f4b70fc0aU, 0xf8db4923fc15f276U, + 0xdf46e80903edd872U, 0xcfede1bb5635efa8U, 0xfb5381c7cacad37dU, 0xd6e445be4ac9fc6aU, + 0xc2d21507f8ca3c91U, 0x2cd13318fa44e93cU, 0x81744ff55e31a25U, 0x81bd6329d9f8eccfU, + 0xecf512360ae7dc20U, 0x19dab1c4b9ec07c8U, 0x1746d1fe1d42c4d9U, 0x1a2e4a3f360dc9bfU, + 0xc9877f4e14f60dc2U, 0xd7d15bd418ea4ac7U, 0x47051fb0de06ebdaU, 0x5e01185bb60a370fU, + 0xcf11e3e2dfe9bdedU, 0x291781cf0fcbe831U, 0x1ed2ea52e4bf1d2fU, 0xe7070efb34dc1be7U, + 0xed13d0fa16f1061eU, 0x38caeff94544e4d0U, 0x3e81f7e1bdcd2559U, 0xa2012c5c02daee4U, + 0xcf030bfbaff202fbU, 0xff3eeca81bdeaecaU, 0xac8d88d72c0ae6fcU, 0x150301d8cfd8a5d3U, + 0x4afc341eca25e9e0U, 0xe7f3ee060dd6cd7fU, 0x5718eeed9aed120fU, 0x874c0513d233032U, + 0x5013c9282eefd4bdU, 0xd6e60c37c8c84c83U, 0xcdaa81bb3edf22ccU, 0x20c44822c51ce542U, + 0xedf8010efafeed0dU, 0x14ecefefede41201U, 0x3426fa2feafdda41U, 0xac7fd1e6ec152bf0U, + 0xdd0a2b4719ae40ebU, 0xf7ffbed731a80b31U, 0xba2acbd4c018d10aU, 0x283c7f92320de908U, + 0x3f0f3747e13bae19U, 0xc0a2aed1ae7bee0U, 0xdd1ceadfe33d1f95U, 0xd07ffffde6e6d748U, + 0xdeef5032e7ed23c6U, 0x5308edef9cb50517U, 0x79ed411952f62ee5U, 0x515d7e7412cf61caU, + 0x410f00eff4ec8f6U, 0x2fe3d86418736e0U, 0x40d8d210f00a0130U, 0xc7cddb638b81eaebU, + 0x44f441d2dce1b70cU, 0x243498a2f70b20eeU, 0x441e56da3a57de7fU, 0x55c94ab42958b647U, + 0xc922b719f6280328U, 0x81cfc105f1e3eef3U, 0xd1a93e117d8f0d8U, 0x8e21407dc2392f5U, + 0x33f02a0a3136e406U, 0xe20402fd3bf9f339U, 0x5b6dc61fd469db7fU, 0xb82f12b51a9c8fcU, + 0xedb11937dfa72818U, 0x62bc0c1e54130536U, 0x57c9293963a539f1U, 0xd9b64f990a5b3a8fU, + 0xa91618227f1533f1U, 0xf5f731f715d0fcafU, 0x2954f9bffa414502U, 0xbf5322d3da1cfa7cU, + 0x7fe60be3e9a2fd08U, 0x10ad481e0c30d5bdU, 0x6350da479b5030eeU, 0x9fe13f8da041836U, + 0xf0a5cefd04d82b14U, 0xcde3172b9412444aU, 0xda01bb38bd1a2e7fU, 0x19d10fe8e0f804e6U, + 0x1fd5ed33d20de1dbU, 0x27282725d82ef8cfU, 0x1600ecd2f9eeff3bU, 0x43811826ddeae32aU, + 0xeee81ed9d766ddaeU, 0xe0928f24226291dU, 0xe60b0b22193d0c0cU, 0xe263d91133af0001U, + 0x97f05bf81f15af89U, 0xf07f4e094bdae60aU, 0x18fd1d0bdbeef13aU, 0x25c82743e5caf1e0U, + 0xdb0bf7d21925d50cU, 0xdc24fa3dc153feceU, 0x260fcce6c40e097fU, 0xc5161d2429388bfdU, + 0xdd88f0ebeb2818f1U, 0x12dac031003207ebU, 0xe8fcce1c18c655d6U, 0x3e8129578cdd05d9U, + 0x2cea2de672b328e8U, 0x5c04f8ce30efe122U, 0xfd27d6e81c0c1807U, 0x17c902f4e3eccccfU, + 0xf5121c3beff2e738U, 0xb77f72c0355e0b49U, 0xbba9381ee20441c9U, 0xe7f7c2193a4e1505U, + 0xde17c9d1de4ce876U, 0x489d84658105b3ddU, 0xe82ed3eb42b4c7e8U, 0x262f43153fb6fdf4U, + 0xe7c0abf11e44eb18U, 0xfcbcfc7d019d83e3U, 0x124135d1355e81c9U, 0xf3e642130e46dc47U, + 0xedd6e10313fb023bU, 0xe9edf9ff97ecae1fU, 0x2111c540037f4cd7U, 0xddc0bfeb18f2e849U, + 0x435bd5f90101a6e4U, 0x271bf0f7cf9303e5U, 0xb0d7dce2c8810c17U, 0x30fbbed920b0215cU, + 0xc3f3278857f9baf7U, 0x8e3e05ee4cbe3cf7U, 0xeb20391f9fff1542U, 0x81e07e6c7231f11U, + 0x323113047fc90807U, 0xf10a0adbfa3eecc8U, 0xeb9ff39ba060c0fU, 0x3e50fc01d201eeb7U, + 0xaf34920de6e6e19fU, 0xe400bb067f24f68fU, 0xcca58cf4e670ee3U, 0x63036e66c23ec860U, + 0x323121017eb43f8U, 0xad63b208dd3627ecU, 0xca5f7f356bcb78d6U, 0x2eadde1a4d26f0faU, + 0x12e2e0360606170bU, 0x27af30510c3b36ecU, 0x2aabce038107d8f3U, 0x19150fd8cee4ae22U, + 0x14bedcff3fa035b6U, 0x2f841010ee5c325U, 0xdb7ac1f9ec431244U, 0x29c8b701b30d3a09U, + 0xe137d2f27fcdd6e8U, 0x3f0bf3d66d39dd29U, 0x2fb1dc30e17a042U, 0xee01290ccbfc3945U, + 0xf8d93f05c81fcf0bU, 0x40adb5e32eb3dd6U, 0xdce0d3fc17e7e5cbU, 0xf046280726a3c73fU, + 0x1d0fca7f562df1e3U, 0xd1d17e3e63ef915U, 0xf72ee0475307ccebU, 0x7fc9ed25c33823adU, + 0x523cb1930dcd13cU, 0x1f4d21f474bfdU, 0x3e29d927f0be72bU, 0x9cdbcd9f50de7eeU, + 0xfdfdd01a11f5eee4U, 0x293833d522052823U, 0xe3be220de6ea1ddeU, 0x28dfc33993d1ed20U, + 0xe4ebec3d04f4027fU, 0xbf2c5db00f616ebU, 0xfa1ff00c1fb82122U, 0x52fd616c7fbf11bU, + 0xf7232715093b5ebfU, 0x2ae57fd6bea7e71dU, 0x64e84abe202cc4f9U, 0xac3099fc16171ca3U, + 0xf020318f087da431U, 0x8cfe056658d03deeU, 0x113ac739070c062fU, 0xf0cecb37c437e8aaU, + 0x20fb7f8a1ae62211U, 0xf0ccd0bd30f015f6U, 0x2e11a0ad93b30d2U, 0xf8ebe325cdcaec1cU, + 0xdd170f0523cc071aU, 0xffaaf7f7d9226112U, 0x917fd22511e75040U, 0xcb15f6e71aec0ff5U, + 0xc2040ae3d2fa3415U, 0xe6ee01d943f31803U, 0x5ffa272beddefdeaU, 0xf5aad37fffdc4afaU, + 0xf2cddf08b37fef0fU, 0xe7b0e4f1cb3ffa35U, 0x11d8f7d45df42abfU, 0xecd5f616c1f75415U, + 0x223f72dc0bc4d4f7U, 0x43e22a06e2c71873U, 0x30dd18ca0df53030U, 0x25110734e3d838cbU, + 0x728ad53adddf39ebU, 0x8738815e1d8530ceU, 0x7fe3deeb1823e535U, 0x1854d9a9ee33fd2bU, + 0xd30c5eb122bb134U, 0x36dc37b233ca3c21U, 0xf4001e0301fc590bU, 0x1b110ce6367f0069U, + 0xecaa023be830d1e1U, 0xd4cddf290bfceed7U, 0x210904e91ff80d4fU, 0xf702d63fdad104e8U, + 0x555541270851487fU, 0x63ca14fa4b4439b3U, 0xf611175ee9350696U, 0x10c7a70cceed1a3aU, + 0x6329c2e6011a18f5U, 0xc467031421d94264U, 0xe0bf6173adbe9ccU, 0xfee22605e4d12ce9U, + 0x749fec1a81f1f7e7U, 0x313db25413a40bb4U, 0x97a0a2e01c7fdc47U, 0xc8eae0054afee1b0U, + 0x406432020143d107U, 0x20ff1650affaf254U, 0x26caaaf62bea44dfU, 0x2406b9f4f6c85201U, + 0x3bbffcdfbaa0926aU, 0xc2d5d7a461a228e3U, 0xbe5f513029121a17U, 0xb781d00c601a0c12U, + 0xf57f45dbf1f592e0U, 0x3c0216f4347d09c5U, 0xf63e16dcd627b8f2U, 0x653ad218520c3a43U, + 0x3e8dd0ec38c923beU, 0xe7b0f702fdede5e4U, 0xff401a1713d9d306U, 0xe0ff3bf11aeabe22U, + 0xcaeece0a11c5fbd2U, 0x1fe74181c045f9fcU, 0x7a3d2bae3688db2dU, 0x9ff86e68185d8187U, + 0xe030e9007c20b4cbU, 0x7e6190620f5ed16U, 0x5dd212b180528beU, 0xcbebe72e04ee0638U, + 0xd37f2409f51a08a9U, 0xadb2f01cad53cf9U, 0xb8401e3c371e194bU, 0xe5d3972d0236e1c9U, + 0xf6d0aee0264c2513U, 0xe91011fc1acf0bd8U, 0x1a1d23559d56fec8U, 0xd81241c05b81dd3dU, + 0x4307fbd813fc08f1U, 0xf04bd18ce60c701U, 0xbcf2ddbfe04463cU, 0xc6fce5c5271b4c81U, + 0x37282310f6b615f3U, 0xcb2d1fe1ec143217U, 0xf140e0990d3cc712U, 0xc8ee62cf172484d4U, + 0x40ab3af028e10eadU, 0xf421060797f9c24cU, 0xfdebf2c303a77f1eU, 0x105e718cab97fU, + 0x2f1bfdb4fb130955U, 0xd822ef69fe30f808U, 0xd79ec79dfbf80af0U, 0xbb4c062b12f400e0U, + 0x33ebe711eac75c5dU, 0xd514b71e58d220ebU, 0x2c0eba58814109daU, 0xf1c3bd9470911d08U, + 0x222908b6f8f9fa29U, 0x13d1fef7397e9b10U, 0x1646eea9e8079081U, 0xc3512540dabe5416U, + 0x1cd33ff5f201f136U, 0x4acb23154bdbb591U, 0x19d9fdffe2e4d648U, 0x3586f44dffbdd727U, + 0xf518e4da0df1c107U, 0x7ff24e19e1fd0445U, 0xd10c54fd0cd718edU, 0x161ddf2cf6cdf2f1U, + 0xf012d2b395ff7622U, 0x1d0baeff5beed114U, 0x20441cd5c7f17fcdU, 0x99c90eebdbe6f2d6U, + 0x10d91dc6eeeb0b5fU, 0x34e9e2059ff14054U, 0xf2c7e7f7a9277819U, 0xce3381dd33f716fcU, + 0xfbb706e80e6a4024U, 0xed8bfd7b4f0fcd6U, 0xf6bf0837dde6c50dU, 0x2df0ebefea1a0d3dU, + 0xf6c7f6ffcdf4edd6U, 0xa7fb3381a3f3564bU, 0x744fdfb12bc1a8e4U, 0x9374284161ddcb23U, + 0xe87fe3df201e4c6fU, 0x56fd20d6f949ed01U, 0x1bdd3a28141c4ce3U, 0x332a2b3ef8fa237fU, + 0x11f7d10632661bf4U, 0x462db445e0ca29dfU, 0x1538c44717e5e5f5U, 0x8273ff3ddf4ed14U, + 0xfbe61de52ef702e0U, 0xf5082d3ddbd2c3f8U, 0xac8750ec2bc9a57fU, 0x8876c1051fe6f1c1U, + 0xd0d3081511ca2b2aU, 0x7f06caf3afe69519U, 0x4bc8e6211b0ef6eaU, 0xfb3fe713fae6f9deU, + 0x270412d31af1e4caU, 0x14530eef1feefa2cU, 0x8a58e854be91fc5fU, 0x492dc9176c3e7154U, + 0xf4daa5afd8bb37e2U, 0x1d0a0bd8d51208deU, 0xdff4b90907d4367fU, 0x5d6cd7eec6bc2d40U, + 0x1518024c812ff1baU, 0x87297e861de4bff3U, 0x355f3690c1e8c87U, 0xde06aba113308ccaU, + 0xf3121dd4f5eabf02U, 0xdb40f19d9e59517fU, 0xe6dda741f61deb65U, 0xe1f2f6d94a0e94adU, + 0xaee526e93139e3f5U, 0xba08cda75481b5b9U, 0xcfe1e50930faca2dU, 0xc3948258a82fe696U, + 0x8e1e43280a19db5dU, 0x750ea1264ad7b996U, 0xe89ebade066bbac8U, 0x5fc134d7bea4bfcaU, + 0xedd3bad2fad90ee0U, 0x2cc4dc4a1bebe7cfU, 0xc950321b8145e042U, 0x21cedff115f02b21U, + 0x1412fe08dad661e1U, 0x17ebfae23f1b1940U, 0xb61633f11f90cc1cU, 0x32e1ec81cc714c40U, + 0xc31d017f19c426e6U, 0x3e99ce3efcd3225U, 0x6b80dd3ebc6efc1U, 0xf9d19ef818d6df4bU, + 0xee28093fe083ff3eU, 0x11d9f43f8134f9eaU, 0x40edfe27b4df13b9U, 0x30cfe1e98225165eU, + 0xc6d9143616a49ff4U, 0xf8f73509dcdbfbcfU, 0xc790906484bddf0U, 0x2e22ea8d161e3fecU, + 0x4ce12c2424b44d81U, 0x117b173bdf4bd427U, 0xd2240de00fcaf8e8U, 0xf82ecd13f91d3f1eU, + 0xf51716f2fe281b14U, 0x15e0ad38e63df346U, 0xd30042491981a52eU, 0x230cd212f6cef32fU, + 0x4e736706e57ffae9U, 0xec95e7584ae91108U, 0x2a412ace17a0a528U, 0xe0123928ea3cf00dU, + 0x3ffa53b5de12cd14U, 0x81f3a3d50ca4ee1eU, 0xcef9f3e7b1d40e0dU, 0xfced10dd17ffe403U, + 0x14eff2f4ca103cddU, 0x4211b5ee31cd25d7U, 0x7ef581c60b0ff413U, 0xf20d8bd53d5e2a7U, + 0xb5fa0ff76d15282aU, 0x1f4eecffb212337U, 0x411ed2e41d272bf7U, 0x13fd09e2f6173125U, + 0x71d21e4daca98142U, 0x20d58a2e07330eebU, 0xeb4aff2435134067U, 0xc1911200d01032c5U, + 0x1022c3ffb02f0923U, 0xfe203f0c797e18cbU, 0xf92beee88c2b53c9U, 0xa92818074c445c0fU, + 0xa17fdee15db296b0U, 0xe3f91c00112edcdeU, 0xf534d20226e1ee10U, 0x1bfc0f14eaef550cU, + 0xccfdd946dac511ffU, 0xb411681f3078ee2U, 0xcfe4da902c46a8d5U, 0xb8d2b8c2e627dc32U, + 0x665c5afd08f081e6U, 0x23532179b3d0d935U, 0xfaf5e4f0182e3e3cU, 0xd02a022401a82c7fU, + 0x124f1e17ffccd0f5U, 0xa8e7fd110ee1673bU, 0x47d62ced32281ef7U, 0x3a5e34521ff9d2eeU, + 0xfb2ff6def4c4e556U, 0x31ef3b544931c681U, 0xea0440371115ea25U, 0xa67dec5f262711f4U, + 0xd50fe728dff8db22U, 0x3170ded1c4a1f29U, 0x29bd0ceac21f3e1U, 0x9b2acb3e17b74c28U, + 0x7fac5fca00f770a8U, 0xdecbcb6834f8744eU, 0x210125d8e5cd28caU, 0x32f74a20c0cdc7ebU, + 0xf004d11e18eb1535U, 0xb824ff11032e1247U, 0xf2dc187fd0bffd1bU, 0x14143e0a5281e803U, + 0x90f8fd74f0bec09fU, 0x495779c3ffad150aU, 0xd110f044c82ac2a1U, 0x339fc210d7fcf397U, + 0xc6ccc9639743cfd9U, 0xffdb1182a42e593dU, 0x37edb23f1adf9d57U, 0x2a9efe04e50104f6U, + 0xff7f583ad703ec1eU, 0x52bebe8393fc549U, 0xda62da42392dfb19U, 0xd244f4f4b2bded7fU, + 0x9a0ad21f050df11cU, 0x2fb8efc4d111a8c3U, 0x8c013eefed2bfe9U, 0x5dde013ec719a3e9U, + 0x1fdfe532a439b66U, 0xd87f02ca10150f3fU, 0xfa2fbaf90daa4ccfU, 0x22511ae3cacdc5f7U, + 0x86a9b19ec05667fU, 0x2509d94ea4e9cec1U, 0xfbcdd2d43203d7d5U, 0x9b153a02b649d15cU, + 0xc50650e6c9c62b37U, 0x7fedf1aa5bccdeffU, 0xe90e78de4cd54c1aU, 0xccfd3716e12be9bfU, + 0xf6221fa4e416db16U, 0xf302e7ff6681ef4dU, 0xe2fde449c0c29814U, 0x2ce068089ad064baU, + 0xe404cbf3f7dd2637U, 0xf5232ad3cf29092cU, 0x40bbf68347c62a1cU, 0x5705e317811fe4f2U, + 0x1930fd0fd2624dc9U, 0xdf1f28a5e0efe045U, 0xdccec2d510fdb551U, 0x101e0d40e11251e3U, + 0xc4f4ebe74d323834U, 0xb24b0ae1201de6d5U, 0x2e2268c5f8fbd011U, 0x21fce4cf7fa9c33eU, + 0x1c222d1cde27f00bU, 0xbc0c12175aec1942U, 0xf49fbe918defc17U, 0xb718b67f05b1e537U, + 0xf6fb6e31b21dc0feU, 0xd791521d03e4d14U, 0xb9e4efd4182d7cdaU, 0x32ca1ab04281198dU, + 0xef708f2ce27ca2fU, 0x2cfac91c0d2fe03aU, 0xbff3d11edaaefe2dU, 0x2f63ee1cdc2537d6U, + 0x1c483d12e2bb0bcaU, 0xf81e28c916060b5eU, 0x538cb97fe024483aU, 0x30a1ead0c8fd2b61U, + 0x16293def7ff4e30eU, 0x37dc3bdaf2c42310U, 0x8d59d623f1babeefU, 0x3e3c43b9c03cf92fU, + 0x79f6e1d0cbd7d6cfU, 0x4ba2b4fd32f64016U, 0x6818d929a06a1edfU, 0x2204e4e996f8a817U, + 0x7ffccf3001d10cd9U, 0x4eb9dab659c0c6d0U, 0xb4ef0ec133aa2401U, 0xc7d406df591dbf7eU, + 0x4417eca3073d7fd5U, 0x1e475602357005a1U, 0x102bdc51ba0e1322U, 0x15cf2f3ba675dedcU, + 0x2dcdfd3423c9ef0eU, 0x697d1e5b3a6cb148U, 0xeb816326b52d732dU, 0x32ff24f5e108f41bU, + 0x4eb01335b06f2fd0U, 0x5f100ef1558238eU, 0xcdefe6004981d7c1U, 0x6de57daca0f0f00U, + 0xcbb00113bffb81f2U, 0x41e3e9ffceec122aU, 0x8e5eb103b14bb57U, 0x16fb100bef15fdfbU, + 0x2440904f00b00f0U, 0x44ca0edb14fbe6U, 0x2c1c0bc9ef337c1U, 0x58cd7fc860d632f2U, + 0x2f5f1e1f0d1c0d11U, 0x28180afd35c99df1U, 0x12f219ab547fd534U, 0xf7b0b605f1e93722U, + 0x2f15fab7f40302d5U, 0x16fa1b19ac240526U, 0xf62504d320fcb006U, 0x48371daf2708ed3aU, + 0xa52a004456f2ed12U, 0xc57f9d011a2b061dU, 0x22c3e0c9cdd50d38U, 0x32f92cddd10fcdd1U, + 0x2e7fe0fc349fbefdU, 0x2d4097e7f6020019U, 0xe2beb3be00afcd6U, 0xf61822e9362dc7f4U, + 0xde1af61d020e0cc6U, 0xd022225a06ba2e10U, 0x1225d1ee0c2f26f8U, 0x21f57ff05314fd1cU, + 0xe4fe27f0c6271436U, 0x261f27ec13efd42bU, 0xb2d1f0e2d22bf8f4U, 0x11a913812f08b1dbU, + 0xa629aa0a9afc172dU, 0xf8cbd9d41bf31be5U, 0x131127020818fffbU, 0x1b3000007efU, + 0xace00000217U, 0xffffe43f000003e7U, 0xffffefd3ffffe9d3U, 0x1154fffff5dcU, + 0x26b000013fcU, 0xb39fffff415U, 0xfffffb3affffeb99U, 0xffffe678ffffe94dU, + 0xfffffa35ffffe857U, 0xfffff8edffffe352U, 0xbad0000096fU, 0xfffff448ffffebb3U, + 0xffffdba4000004dfU, 0xfffff8c70000033dU, 0x3e7ffffea68U, 0xfffff50600000eebU, + 0xfffffab6fffff71bU, 0x553fffffc23U, 0xffffe7edffffec88U, 0xfffffd30fffff1c0U, + 0x6060000040dU, 0xffffed2cfffff329U, 0xfffff6bf000009a6U, 0x177fffffc02U, + 0xe0efffff7e8U, 0xfffff240ffffffadU, 0xb2effffe4bcU, 0xfffff9e5fffffe7cU, + 0xfffff4e200003faeU, 0xfffffceafffff999U, 0x1660000009b5U, 0x3a2fffff8f7U, + 0xfffff1f8000001cbU, 0xfffffd97fffff66fU, 0xfffff27dfffff6c2U, 0xffffef37000016e7U, + 0x1477ffffd3e0U, 0xfffffe91ffffcf29U, 0xffffe66dfffffb27U, 0xfffff4e700000b2bU, + 0x19bafffffe5fU, 0xfffff717ffffe964U, 0xfffffa9affffd1ccU, 0xd6f000008daU, + 0xfffffc43ffffe3f9U, 0xffffed6afffff418U, 0xffffe9eefffff990U, 0x1623ffffe96eU, + 0xdb3fffff903U, 0xfffffc9fffffeccaU, 0xffffeb93ffffe824U, 0xffffffd7fffff5c3U, + 0x8000000b57U, 0x5cfffffedf2U, 0xfffffecbfffffc91U, 0xf16fffff2faU, + 0x16cbfffffe4cU, 0xfffff86300001dfcU, 0xfffffac8ffffe688U, 0xffffff84000007f9U, + 0x719ffffed8aU, 0xffffe6d7ffffed7aU, 0xffffe03ffffff8a1U, 0x17b76c53ca6ec906U, + 0x7f0c5ed04f0dedf1U, 0xb0217f7f7fd77f12U, 0x164b810781811cf4U, 0x817fe8817fde8106U, + 0x7f47d5b0fca3d87fU, 0xce100107f2590d6U, 0x2d81f5180b7f7f60U, 0xe81bf7f48813841U, + 0x810f93c50167d653U, 0x7fc307282832e6edU, 0x5981be817f8abc46U, 0x81be0ec42b8d7f5cU, + 0x717f817f7f81817fU, 0x719d26d7167f7f81U, 0x5fe91d7fe9818b32U, 0x1412b3381b73ce9U, + 0x2cff762b190b8141U, 0xc5c8e860226644d4U, 0xc97fa503aacb4917U, 0x876a38be7c2d8f1bU, + 0x725281ca7f9467e3U, 0x32baf3b831170d28U, 0x44c4aa7fed69724fU, 0x7f9555dfdfd2d77fU, + 0xb5c8aaa53b307c7eU, 0x71b281f80343d062U, 0xe1c848c0478102e3U, 0xd6bf1f444b845709U, + 0xff08ab1c5fbbfc72U, 0x7cb8d286ff5d099eU, 0x25d0d1377fff9500U, 0x7f7fc0e7a8bc0bd5U, + 0xe3537f7f7fd9367fU, 0xfcddb141d87fd7a1U, 0x42df523c0f60a01U, 0xeefd4d0a45e2960cU, + 0xd39beef42a47fa8U, 0xfc28bd81df427334U, 0x14dc8154cdf11c7fU, 0x18e6589b8108382cU, + 0x409e0ba9dfc77f2dU, 0x572e97c6ad46a07fU, 0x81adf5d00ce40f1eU, 0xa03a3152e19817f4U, + 0x81e134f2e8cc5063U, 0x2df0b0d73360c4a0U, 0x3744c5a76517018aU, 0x771752f1581281b2U, + 0xc77f073549117855U, 0x711ec91bdb28ae81U, 0x47f70747e730edc7U, 0x543bff2b4d9c88b3U, + 0xe8af3648482a0cdeU, 0xe03991b4aa7f72ccU, 0x8df7b34e27aadf68U, 0xb5097fbe86f25864U, + 0x35814c81819b50d8U, 0x57215abb5d79c7cU, 0x12e481f79ce0335fU, 0xd67f5d7f81a0c0b9U, + 0xb7c754f996d73cafU, 0x1c7fb829f55ad4d4U, 0x6761b2a12a284e81U, 0x15157f7f4a7f8481U, + 0xba67e8bbfc7f41e9U, 0x7f7fe32215e5ade3U, 0x7ff72b7f9de98181U, 0x7a2e813bc3819081U, + 0xbe811a7f347fce48U, 0x817f8105c0567f81U, 0x8133dd457f8de41dU, 0xa135372bf2e17f62U, + 0x19c47fcda6817881U, 0x997f47818181811bU, 0xc0ea42f9b077f7fU, 0xae5c7fab8b81ea81U, + 0x8c305bf4ab1914b8U, 0x8148817f81f3b217U, 0x7f7f812918647fdaU, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0xcbb10e2ef0d410d5U, + 0xff270b032e3413f4U, 0x23e5efeb0e033727U, 0x42fee0e32c0328f5U, 0xf4ff2ae501104c11U, + 0xe211b2eacf205c4U, 0xeb5052478c15b724U, 0x1c49f82a28e537a8U, 0x280059fd47bec943U, + 0xcc32ee070313041bU, 0x230b39017feb0ee5U, 0xfe0be1094c1ef923U, 0x1d35db2908192ff2U, + 0xfed133023cfc8e0aU, 0x12d62fd9ea5008b8U, 0x149af2d429d2cb71U, 0xfcdbfe321542714bU, + 0xd30be200cafcd712U, 0x8f92b19dcf34311U, 0xec0a20e80a04980bU, 0x207fc60c3821f51dU, + 0x3d0bc6e3f2f84153U, 0x1df1cde4e816f756U, 0xda3ad809bbd9e31cU, 0x4121bc48f943f708U, + 0x560011092205b70cU, 0xeae133d930143402U, 0xe23402f6e8f6e4f6U, 0xcacc061aeb1d2ae4U, + 0x1a042f2f06f9ad00U, 0xf9fade05d9e52bU, 0xe2f204a7da25b5c9U, 0x32ab64016d7cbecU, + 0x14cc1b173acbd8ffU, 0x3bc413fef2fd051aU, 0xd4b5d2d4cdf9253cU, 0xc5f20331939a5d33U, + 0xdc1d22262725f1f1U, 0xe832ebfe120918e1U, 0xf1150fbb10281e34U, 0xe5f015016306cdcdU, + 0x105432dfdfc7ca13U, 0xadfb031a030d6404U, 0x3b201405edc0e9f9U, 0x43d881b91ce117ffU, + 0x1504ebe542fa0722U, 0xebfe2fdff32315f1U, 0xd8d5423ed011f205U, 0xfeefd7391616d11bU, + 0x2e6320f0c552b15U, 0xe5300fe1e51139U, 0xceede92f132e00U, 0x7713d702d9fd3cc3U, + 0x18ac21a5f8f1d5f3U, 0x100100dec9fbc4f7U, 0xf1061d211c0e2cd9U, 0x39fa400e7ff1b1fbU, + 0xe11b00330121fec4U, 0xc834251840404d18U, 0x4b450442050acd35U, 0xf310ec206d70dfeU, + 0xea03051348c3b606U, 0x3dcd34111a0ffa01U, 0x90f1b0500111d22U, 0xb6c51c1ffde3210eU, + 0xe7c21429fd23f613U, 0xc0e5f3981a9adee6U, 0x1fc02c80e500dd3U, 0x2b34ae15cf20511eU, + 0x1c0afbf899eb13fbU, 0xcf28277ffa041612U, 0xda5a26020c3146f0U, 0x1bc5f5e2096426ceU, + 0xfce3081ffc0a0436U, 0x12e6def677df1eb8U, 0xec53bf9f56c5e4deU, 0x206b936def74bedU, + 0x94c9565c1e59ea29U, 0xf6f8f34c401e09d2U, 0x2dfae20851dafa78U, 0x171be7eb22f3f131U, + 0xf6dfe842e907ea40U, 0xe9d0d7b90f7527cbU, 0xf0340d3207cbc4ddU, 0xe4de16f5272210a6U, + 0x577b05ee61e126e7U, 0xedea4820f6b2a6c8U, 0xb754dbc817bdf0b5U, 0xe4ea280bd8fefb30U, + 0x45b9989d5908dd81U, 0xa11e90419a0b306U, 0xd0ca10e6ffcbb6dfU, 0xe41ee543d74d11d4U, + 0x3037c900f3233f0cU, 0x21f1bf4658042fe0U, 0xe66d3b6e7a54e39U, 0x440eafeabbdf1802U, + 0x17e6edede618f4fcU, 0x3cec30191894075fU, 0xd8da0ce341ec24efU, 0x19fb37e8e9f720e6U, + 0x11f143cd14eae3d6U, 0xf93c35fab62efbe4U, 0xe6bf05d5fde6fcfeU, 0x1fbf30f87f20d6daU, + 0x1e003b10d70fcfU, 0xdced0ce8e23c63ebU, 0x7a300c3af0f20601U, 0x3becb7bad638b314U, + 0xfee8f91561ea0e2fU, 0x2c01fa6d310f0dbU, 0x2fff0b131cdcfe1fU, 0xcc204a37e019fa08U, + 0x1aacfdedbbdc1007U, 0x2d4f5dafbdd13d0U, 0x708f0b8eb3a06f4U, 0xcb41df1af11e1642U, + 0xfcd5f710b2f3fcebU, 0x401b0551c119f602U, 0xc8567ede16f1faf5U, 0xe8f4100ade11fffeU, + 0xb2f32be00e6e622U, 0x2719dee249141aa2U, 0x176efc8fad8d4a5U, 0x1809f2f7d2140ce3U, + 0x1f51c364d7fdebcU, 0xe13fdc3a2d100dc3U, 0x11f5cb1ef2e60c25U, 0x29aeed1a1b55ecb3U, + 0x3aea28d601ff3b4eU, 0x72b2ed5178c5b59U, 0xdfcabfb447de3601U, 0x3ddc65e92145d3e6U, + 0x1eaaec162f9dd20dU, 0xbf1444e2da02ef6cU, 0x1aef17eacffdf1c2U, 0xe203351d464fade4U, + 0x212becfc2f1ee6ddU, 0xaa0ebe35da3b6724U, 0x4e050cfddee8106eU, 0x3543c3970d210c23U, + 0xc2de1d69c64432f6U, 0x15bb69fb36fc7f1bU, 0xceb01b7cd09c152U, 0x171f09f70d050a0aU, + 0x4da2cbdc04e0daa9U, 0x63ec30603b9e92cU, 0x35cb41056c29dc49U, 0xddb93ecf2913d706U, + 0xedf5d61e1cfa1cdfU, 0x7e152d4ca0c7030U, 0xf5343e1019dad308U, 0x40d92119d4e07031U, + 0x4e30e248e706ee81U, 0xf71103ef1c0fad1bU, 0xb0c18bc29e4d482U, 0xefdd1de7fd2afeceU, + 0xfe8d9f3df361e47U, 0x2208e1e22e09f8e7U, 0x206d3d888fb1b41U, 0xd709e92af1d5dd3cU, + 0x9be80e04f905f9bfU, 0x3eff20846d7fdf0U, 0x1524f0d941f0a517U, 0x7ff8381add19dc03U, + 0xaf46f1e2dd0494acU, 0xf4c6f73fe7f1e401U, 0xeaf53ee4f519ee11U, 0xda1ee8e02bf4f90fU, + 0xf1d6170bda392c19U, 0x8cf4ad0d0ce61614U, 0x1bfccafbececc5e8U, 0xdaf925ebc6ee1baaU, + 0xc2033c05a3cedad6U, 0xfbc42ce70da93ec5U, 0xcf1aff070904f4e9U, 0xc91e02fefc107ffeU, + 0x3282cd5f9e927e0U, 0xeb041f0dc70a2cfdU, 0xb418e0f60109bd19U, 0x3af637fb0631f0U, + 0xfa0de0da2c010726U, 0x4722eceae205ce40U, 0x51e101f9c929f0faU, 0x2f35f719beea20fdU, + 0x14372cf01bfa03ffU, 0xf7173ef4f90c30f8U, 0xe8e2e7f5ed27b6fcU, 0xd301f301db27e8e8U, + 0xec392bfcc4f9fddfU, 0x1cfa16efd0ed1400U, 0x14fdfacee01efe23U, 0x5c32da810def1b19U, + 0x333ee448e7fbff44U, 0xfbe1eef103d624b8U, 0x407c721fedcb9e3U, 0x263416b11513d06aU, + 0x282cd2f9d410ebbcU, 0x9deaa26ef8d6f4b0U, 0x1be2d71e44f6cc02U, 0x743dc9feeac5ef5aU, + 0x3afdc1adb5300e0fU, 0x35042ae621d3c0ecU, 0x2007d9363ad76d58U, 0xbb5e4d753b9d7e0U, + 0xfe6068db3002cefU, 0x19f5ded4180e4767U, 0x9003fa37f0e64104U, 0x17f5e906fac00030U, + 0x27e3bc1d3ad61402U, 0xf32ce3061b1b4b0eU, 0xe513240146cd1c47U, 0xbddb02c97fe7cbf8U, + 0xfbeff9d2ba020faaU, 0xa2c5b0e065fdce7U, 0x24ff60f806e41913U, 0x19304405032b14ebU, + 0xcce719ecd3f61334U, 0x183a0d2329f762a5U, 0x29eefe1bfe4b35c2U, 0xe3a8a84e084ff5f1U, + 0x3dd9e92134d11e23U, 0x8caca2851ef3b41U, 0xe5f4c40ef2e6d03eU, 0xe595dccc2e1f26cdU, + 0xcd3b002cd204162eU, 0x364a07bcd3d0fd40U, 0xeff6321d3e290e13U, 0xe2f415ff2deedf29U, + 0x710a2001fd4e1698U, 0xa9401500402af6f8U, 0xc2d629eee403f6c6U, 0xffde0ecbf243f4e4U, + 0xe708477fc9183148U, 0x7630da111b21e9ebU, 0x433c8e28e555fecbU, 0xe608e531eedff619U, + 0xcb006618f73ce722U, 0x2acafd1a09c4e142U, 0x6c9f7d11fe9180bU, 0xe0df2af733d5d7f4U, + 0xfc01162312e21033U, 0x2fbbe31a19e0bf3cU, 0x3cd83b2adc3514cdU, 0xbf32f62ccbdd46cfU, + 0x18c52e3cecdcdbd9U, 0x112a1f5ae835180eU, 0xcf231ef5cbd22310U, 0xdced43091fefd2d8U, + 0x200a3cdd0eff242cU, 0x300bef0819ce42afU, 0xe01a39fa30031df3U, 0x512cde7f2f81f01U, + 0xdc98d2e1461bb0baU, 0x2fd8e536d831e3e1U, 0x161015f53fe0837fU, 0xc33a11363a1b5a17U, + 0xf23adb92addf3bebU, 0xd91d1b0ead0401baU, 0x9e02d8d1061ec9dfU, 0xd35d466f5574cd8U, + 0xae1cb1ff3162a24U, 0x3fd9d43aed0bd704U, 0x1e152509c80a220eU, 0x3c01ef43d7c8d6bcU, + 0x40fd1c0048f7bbfdU, 0x1ba0551cde3809efU, 0xd1feb7ee0ae7ff7fU, 0xfa150b26ffc2253bU, + 0xe481e302bf9cb21U, 0xb86f0168b1ac3e11U, 0xd52d298719fdc105U, 0xe4ffddc319010323U, + 0x26e5e80c17edc7c2U, 0x1721febcfbfeebd1U, 0x4d4dfee212fae02fU, 0xd822b4e3ca602223U, + 0x16f3092ef9dd25dcU, 0xcf62a46dae6e804U, 0xcb6d74d839c78303U, 0xc9f4e228da0d5730U, + 0x24ee56b6cce030d9U, 0x2415c7c972052fd9U, 0xf00f2aab01fe03c5U, 0x63faae44cf40ad0eU, + 0x1df80157117ffcd4U, 0xa4eca4f22be633cbU, 0xe21dc1bfcdf223fU, 0xdb4003eca1d5eb3aU, + 0xff00fdaa1f29fa6U, 0xbaec1a4bee0119feU, 0x12e02321d5ede13aU, 0xf003fdf6ee0c1c11U, + 0xdbd1dcdfcfacdcd3U, 0xd910122e080e573eU, 0xf74c264ee581f602U, 0xcd15f6b7e4012539U, + 0x2bbbc32ae7db9799U, 0xf3334eeb0fbfd1aaU, 0xf32212ff31da3e21U, 0xf128b005300b0becU, + 0xfce39bfe1bdfe626U, 0x1afab2b40ce91cbdU, 0xd2e40733b73cf912U, 0xb8da0b84c089cc1aU, + 0x5bfd43f8a79dce12U, 0x172c1cf04605fefbU, 0x6d7f5f4f6fcd85cU, 0x49f9430f2e3dfb16U, + 0xe037ecd40a02ac9eU, 0xe3d4d522eaf42ce6U, 0x170822f91b003808U, 0xfdecdb9f2aca3bf2U, + 0xb3d181d0d357f9eeU, 0xb7fad911ee9bfc0cU, 0x6efe16f2f4ffdf10U, 0xfebff7d15f080aeeU, + 0xf406d3c4cad4ffd8U, 0xf8e1ff007fd03e25U, 0xd5b4184712efe60eU, 0xf3d1180052011c2dU, + 0xb75303d3f7ee49a0U, 0x29eb27c4eee014e4U, 0xc320159ceb571de3U, 0xdbb1fe2830f3f417U, + 0x2ec704f51d56eb0cU, 0xce1081d1405f0U, 0x1c2eddece0ee92f9U, 0x1f9fb18f418e0baU, + 0x1520120b344eda09U, 0x917f70d1cfef7f9U, 0xe4fa11810b05171aU, 0x23d7d719c709b55eU, + 0x83d043d1d1ae6c8U, 0xd32ee8f8efb1fe1aU, 0x2b2215f110ede21bU, 0xeada1f9fe00cf121U, + 0xed0fd0ff2e3b306U, 0x1d1b271508becce4U, 0x4ce0825e4f5dff1U, 0x61fecd4f5f4c6eaU, + 0x8f44be02f71afdf7U, 0x3de80f554842a611U, 0xd7e7e5fc09f30bc8U, 0xe353f2bebe032fdeU, + 0x3549382cec81fbcbU, 0x991526f421da1922U, 0x3fc822c5e119eb30U, 0xceb7d83a1723f13bU, + 0xb592ed05cb1909f1U, 0x9339cbf015212e0U, 0xcc2addcd21df13edU, 0x11d60bfd1f22080fU, + 0xb70cbbdfe6ecae92U, 0xad0aeff4c8c5f907U, 0xd906150b19ef3511U, 0x611cb3681092311U, + 0xf4bdeef0b13e2605U, 0xf7cc1c222c172ef3U, 0xa162fd60a22e7c7U, 0xee2cafded44df3f8U, + 0x2c35151836d63f15U, 0x2bb1c315fa04e4c4U, 0x322f7b615ce1715U, 0x1809c9fefc15b706U, + 0xfe151d4edb52232aU, 0xc011fc0affd10cc7U, 0x3a1001f613c9e529U, 0x4d1ed17e72d1d06U, + 0x4e4c8faf72b3612U, 0xddff03f3ce020565U, 0xeeee8edfa02f50eU, 0x9de0a19f1d946d0U, + 0x2f0b07f7e80a0221U, 0xff122adff6ab2908U, 0xa21f9fcdc0fe7ddU, 0xfbf306187f370e0cU, + 0xd2e9c8e4de43a60aU, 0x22facc3fd5db2fcfU, 0x1af8f835ea0e1003U, 0xecf8ddb0d42adb26U, + 0x27361414e11408d3U, 0xed04141527c411d4U, 0xfee7ff1620124e22U, 0xe5c1ebd63f0a2ff4U, + 0xece0d0dac0eddbd4U, 0x13c7efd7da04fa06U, 0xd301f2f61be6c54eU, 0xef2706fa38f8ff40U, + 0x38cee4ddc220022fU, 0x2ef11509efd0fd4fU, 0xfdff3c81ebbb48U, 0x1d12e248072dd8fbU, + 0xf61ff5f5541fe6daU, 0xd04f6e62f361fe0U, 0x9ff72016e33d03e6U, 0xf71e095a10e8d300U, + 0xd6bff1e20ce5e9d5U, 0xd4cefbd317ddc8cfU, 0xb5e0fc21f101d7d2U, 0xdff7de143141210aU, + 0xb796fbda21f126a6U, 0xe9dc02d3cd623406U, 0xca4deeec0bff2310U, 0x141fb7dda0eefa2dU, + 0x28fce8e8ead41c1aU, 0x73417bce50cc06eU, 0xdf69c2e88fc3160dU, 0xd2adc323023088aU, + 0xfa3308035d47dcd0U, 0x1110de294e247fffU, 0xba32fcebe0fe3ac9U, 0xd1640233f7cefedeU, + 0x37f8e40c14f8e4b0U, 0x181ecf18d3fde6f8U, 0xe5b24d01e7f10e08U, 0xf3fd51c9bdecdf13U, + 0xaca0a0cfd3c2405U, 0x30c7d47f2f5c0305U, 0x37be304882dbf2eaU, 0xfc451b43a5fe340dU, + 0xf3d840f814f8e3f8U, 0xe350f51cf9f52c16U, 0xcd98102af10f26a8U, 0xea3935eeada7ef32U, + 0x40c6fe3a03e2006dU, 0xfe63ea1cdfe00fd0U, 0xd4a5cfd2e1eb4229U, 0xd0b728f4cc69e3d9U, + 0xf314de20188318f2U, 0xfc28aa19cc3853e5U, 0x3a190c1d3450141aU, 0x2ef2f9dcbc44b51eU, + 0xf51020e22d0d3fecU, 0x1feb1efeea2316a9U, 0xe6efd4df2d04261fU, 0xe6abc938661f03c8U, + 0x53cf31b931f43e63U, 0xe9d246d7c9fadef7U, 0x4334fbdd193d1adbU, 0xf3df2d0b3810c2fdU, + 0xbe07e80e33fb291fU, 0xc7e8ca2fc92dfb1dU, 0xd413df4791002803U, 0xd5fbf6c5ec4a0c36U, + 0xecb7ca517f4348d4U, 0x1ea86f1118fb4fcdU, 0x3102d9c6d9e90309U, 0xa50f1f3020a333dU, + 0xff02bcfac7d2d2cbU, 0x99e91934fd07d22eU, 0xbc3601eff4e6054bU, 0xc81bfc1ddddff1eeU, + 0xbaeced08381f3941U, 0xfea2fad049ed31f8U, 0x3810f9a6fe20c0f4U, 0xc728f1e9ebc81912U, + 0x8c726f402e8d625U, 0xacd91a09eeffd12cU, 0xfd0e35aae9e1f0f7U, 0x29e81b0ce13d2a1fU, + 0xe71fc215f50427f1U, 0xc60111d1e507d617U, 0x1147005f54e7fc4U, 0x48d6eeb328dec9d5U, + 0xd848f0eefb0d439cU, 0x132e5a15a918691cU, 0xd28aafc08f12104U, 0xf3dcef5300c125b0U, + 0x3aa1e3010ad823efU, 0xfd372308ac05f3e5U, 0xc932b724e7293a16U, 0xca9f1d7fbcd9f4fcU, + 0x94600f47cc3906d4U, 0x14e24806ec7eb803U, 0xe43fd703d1031cefU, 0x75e5ddd3d32ff55dU, + 0x28e4f02a4446009dU, 0xe011b461720f014U, 0x11f76319400acde9U, 0x63bf3f1e4cc0f17U, + 0x91e09fd0a1de10fU, 0xd6d41cf638d8dbf1U, 0xe704bd25f801f9feU, 0xd3d70522bbf218U, + 0x191bfa430e42e3c5U, 0x2fc1bdf7f21d8d5U, 0x3c9c8182338ebf9U, 0x90df606f1e3c9d5U, + 0x20ed122935de2214U, 0xd5f1f7cae206bafdU, 0xf6af05200622fb41U, 0x1cd521282831edeeU, + 0x481de4d7f827f208U, 0xa71208caf62fe714U, 0x2d1e17df021132ecU, 0xcc1523c1e2d0101dU, + 0xd7f8d34cf6cde91aU, 0xbaf3bf33f8e9d6d1U, 0xf6e7b2fadaf81deaU, 0xe5f5d35fa1d10e19U, + 0x4dde01293919f824U, 0xfaadf73b155523c6U, 0xbe131d2f00fbed25U, 0x17c6c6ef101ae8dbU, + 0x52c56c05071332fcU, 0x240cfeec06cd3881U, 0x145bd2fb3adb0c25U, 0x2426c2ba29b6d42fU, + 0xf9e12e565b23e5cdU, 0xfd171cf4d3c5d91eU, 0xfef0af11b000318U, 0xcfdd1ff1070a5547U, + 0x9f313e8b28108dfU, 0xf99d1ffaf70e1d0fU, 0xb2f4e8caf3bbd320U, 0x30f4f7e20e17dd08U, + 0xda34f1f6e44a0b27U, 0x2ce600e4fd06ef28U, 0x35f1fc029717ecf0U, 0x13bb35fbf32b03U, + 0xed16eff847f7fa18U, 0xeeeb07e7f6fd0805U, 0xf2146f50711ecb9U, 0xbbb07ee3a0912e3U, + 0x23f6cee1ecf7021aU, 0xd201f7c703fd04edU, 0xcce1ffd43bf10b24U, 0xfc52bb7e70fdef0U, + 0xf5f9f6d4c505bd89U, 0x28925b06961264ecU, 0x3bc4061e6f5168faU, 0xcc25eb2c3c181800U, + 0xd4a3e3f4073e31dbU, 0xdebdd21029e823daU, 0x3167dc3edee15bf5U, 0x182f8e5f14321fbU, + 0xf5acdd57fff9a3c4U, 0x9261e1af92fdeacU, 0xe201d0e36c50ceaU, 0x37f0d1fff8452562U, + 0x2cb01ebe0df8eea4U, 0xee22d332f62c20fbU, 0xea7f1604f9eadfU, 0x101a2a053dab7f57U, + 0xef1110a602ff1aceU, 0x290ddd0be40fdcfdU, 0x19e316f905e4711bU, 0x13ff0f5ab2ff1ee7U, + 0x1cd8d8be18e2c015U, 0x1305c315f7c8f613U, 0x14560dfd032511ffU, 0x8d4f347e7cbcbd8U, + 0x26e5e101f21ae73fU, 0xeef44936e5bdd85cU, 0xf4e2e5ea411cb9fcU, 0xc4f832fe07fd2944U, + 0x3ffc35f27fe91deeU, 0x20282b2123bc14f5U, 0xece759fd14d4dfbdU, 0x5bd6152b3890f7f1U, + 0x3cd985252fe534fbU, 0xcc44aff04671cdbeU, 0x35ff3a3f465354e6U, 0xe4ea36c1e602dfbeU, + 0xb536e54b6beee63eU, 0xe6b20fd6dd812d36U, 0xfc34cda79bdff21bU, 0x4aac13393e15380cU, + 0xf907f7c7b778c09dU, 0x16d941da2c14dbc7U, 0x925c0f56302eb2fdU, 0xd4214fc8eac54937U, + 0x3d192bba07b32419U, 0xde14d1f21d99dd3bU, 0x234af7d9162854d8U, 0x25f5f3090d31f54eU, + 0xe6b2a8a0f327ddc2U, 0x98fece1307e21df6U, 0x8f2d406f6e242b7U, 0xd023f1f118df231aU, + 0x2a35241dfa3b3a1bU, 0xf8d242095e154bf8U, 0x76c6f64207fe9a2fU, 0x5b47b02cfcfa9bdbU, + 0x43b54d02c204d402U, 0x28d830e21de427baU, 0x6c422da480a29e9U, 0x5115c5ecfd28fd09U, + 0x2b162c4d3bdbdf5fU, 0x94320541cee5cf03U, 0xc3ac7fc92be7cae1U, 0xcaf833e8d9ead827U, + 0x10fddc42f65aa0e4U, 0xf242b92923e0f2f1U, 0xf903511ce64d54e6U, 0x92a05b1245ee041U, + 0x9d1eea3dff232395U, 0x17032e624de6bdf4U, 0xea0129e321e4d465U, 0xeb6de4d01719d2beU, + 0x6613f80937b1d6d4U, 0xa80701f5f5c4ef38U, 0x24f05ccde40ef035U, 0x812235553413f1b8U, + 0xf3bc7bdcdc2f745U, 0x46120bd043da3e32U, 0xdfc9a7dbfb58feffU, 0x11eac7c5fab12e5eU, + 0x1a542e309f3ff40U, 0x31f9bc553915f9d8U, 0xef220f26db1ee2abU, 0xc12e4edd1c18b7ffU, + 0x4834f5c9110e30a9U, 0xcbdcf00414f7d2e4U, 0xbeec56e8ed0219ddU, 0xf7e059ca0e8dd2b8U, + 0x7fb1e34d0ed7130bU, 0x56d4c748fa07500aU, 0xffda0bce28fcca19U, 0xad1a2d04fb2af9f0U, + 0xb31b29c0bb192940U, 0x32f0a2bbf70b2031U, 0xf5244b0a1f83e811U, 0x27d4dd29e3ead721U, + 0xe00b18291205fa50U, 0x1aeee7a167c8fed8U, 0x1319bad7301427e7U, 0xe7fcfb2cb1182c1bU, + 0xeddffb51a1d3ec1fU, 0xe3ff317f01f62b09U, 0xcf1a41cbe9f1fa58U, 0xf7fd9b4fe445132bU, + 0xfa1a04d2e3cff7f2U, 0x26ddb8e3e5fbbfe0U, 0xd92bedfc2cbfcff9U, 0xc42bfff0cf60ab9U, + 0x1fc724153f2cfbb5U, 0xbe33092f31f1d2efU, 0x7ce4f12d38dcb84eU, 0x3f410bfc4af8ae04U, + 0x69c972c351929fbU, 0xe2ae0f6fb282ab3U, 0x3139b19d2099d514U, 0xd7e9c90e56f4d3ffU, + 0x332f15e607ea5d0eU, 0x7d4eee0aff504f4U, 0x962fa3514c31fc0U, 0x34e91203fe34f049U, + 0x24b4190548e1f1c4U, 0x25191638387fd2fcU, 0xfd20e7ae3efda3ddU, 0x2947c72afd07010fU, + 0x9252c21175025f2U, 0xb1dbd3d3f5ccee6U, 0xca0707ddcfa43f06U, 0xf8d5df091ed72eb2U, + 0x3301283f3121f70bU, 0x4e24ed1d210ecc3cU, 0x2d81371b0f36f7d9U, 0x311ec4ab2db47f2U, + 0xddec67f8d7c293c4U, 0x14326508dc0e1708U, 0xcff514ecbe1228ecU, 0x2bdc38085902fecdU, + 0xac21190704eb24edU, 0x343dd0e02af72507U, 0x221b24e706170d10U, 0x71f0bf30defffae9U, + 0xefc50fdc2603f5a5U, 0x3fe90039502528e3U, 0xfbd41117f6deb352U, 0x22fae5cb3bdd201bU, + 0x813cee0ff22c59e2U, 0x1efbcf1bd920e30cU, 0x9ee3e8d3e6cfd9deU, 0xbed1ebe32a1f04faU, + 0xc9ecfeb66be1b2b4U, 0x76df2d0b79fd21aU, 0xc1e1104d30cc6bcU, 0x2a2b06bee45006daU, + 0xc9fa29100ce8cd0dU, 0xbc18cdffc31842eaU, 0xfa4aba18b6ee16f0U, 0xf5fffb37eac1b3dbU, + 0x96c93c2717f9da35U, 0xae241c19c8fb05e0U, 0xe5ecffb8d8e2ec06U, 0xf108e92c231b25efU, + 0xb31f0b0bf83bf6baU, 0x6d0e2ce0f2f63421U, 0xf3d8d7c96739e91aU, 0xd3edab7addf4ebedU, + 0xced117fef0eeff10U, 0x320cdff5b2e5c9f0U, 0xf228ef05dd0cf800U, 0xebfad70a231ccc09U, + 0xecf63f1614422927U, 0x3ae41323ca7f36eaU, 0x2151ca315a05e7e6U, 0x23fd1bd9ccea2432U, + 0xdc0904212ae2debbU, 0xc4f3de2dd9cf49feU, 0x58fe37073099e1e9U, 0x2231f7e309352c15U, + 0xdcfa0896c03b11d0U, 0xd2f52825ccdc7ab6U, 0xb920bef7f4d7dd13U, 0xa32fdc70e0a1814U, + 0x4ceab5b3fd604057U, 0xfc10e9d70dfdc07cU, 0x7f07d005e8cce1e7U, 0xf84eb108070f00bfU, + 0x1be5df2adaf7e0c4U, 0xcc02fde4ae0f06f1U, 0xe0eafe18c207fe3dU, 0xdce02a023fc9ffU, + 0xfb08ebec33cfdc2bU, 0x66b16d5cb1d0202U, 0xf51305bb31f922b6U, 0xa002f8ff0face9f9U, + 0xdf94a1d40c6235aU, 0x43e6f9defeb6e216U, 0x18b214f209320f89U, 0xf4e3481de85a5ce6U, + 0xdff66d3afb94d58cU, 0xcc091b40cc26f905U, 0xed504a88aae320c1U, 0xdfc5090f4005e712U, + 0xf9f4b7270420f325U, 0x921afeae5190bd1U, 0x602e28b703092c47U, 0xccaae4adbd1e39b0U, + 0x1acf29d52d5c119cU, 0x1ac36ed0800d0caU, 0x18e7f20ade1a8b7fU, 0xf9c3c6f3e1a113dfU, + 0x2bea323128190623U, 0xd119e62334da9302U, 0xf1fef25dbd6dec4U, 0xecb81f19f4032af5U, + 0xdcda01ec09f50bcaU, 0xf435f74725e809e7U, 0x2ae8fc1e181e103fU, 0xbf2ff0dfc9eb1ef3U, + 0x350b2646c6b60b0aU, 0xade0d59bfa02adefU, 0xece40a7ffd46239dU, 0xf3fcf0403205f6e5U, + 0xc0e32cdddbe8e5b6U, 0xfde01f2004ce7eeU, 0xa55ceaeb2a5b10d5U, 0xe5fbf2e7320b224eU, + 0x2be6ab0106efcaecU, 0xacd5251209be09caU, 0x516d7dfe1ddf0faU, 0xc427e308031905f3U, + 0xc15e2e3d2d0f6f3U, 0xf718043820f13310U, 0x213b771506cc0009U, 0xb08f529e70f2813U, + 0x27b814f424e3f218U, 0x2216e72c2604e5U, 0x1830108117bbd4e8U, 0x912c926fdf1c0faU, + 0xe8e6be012d2ee7ebU, 0xed0705f8efc10ec2U, 0x2218c4e4f1b8ff35U, 0xf032dfe2bf174840U, + 0xf8c9d3d6550efc16U, 0xf65cef3a1ed8011eU, 0x32ae98f1ed1e6e7U, 0x1a177841fac4d91cU, + 0x1f92ff1747bf2e31U, 0xb0d5fe2edc01f342U, 0x3419f93a1e07b4f4U, 0x2f103108dac9de40U, + 0x1e211a36faeaf6dbU, 0x724a58eb450df354U, 0x3bfba4ecd1c250e6U, 0xea5627811a87f1dbU, + 0xc7bd421d1bfcd9e8U, 0x2df4ee04ded3ac6fU, 0xc5142ccd14fed59bU, 0xd173d1bc39d2322U, + 0x24a5172b11d82d19U, 0x29d4c5110de2db0dU, 0x4b1736bfd4502054U, 0xd8effcebf30c4a13U, + 0x4e47f35fe5cbcc4U, 0x3d9cf21414fa3dddU, 0xe3ee3df8de1df5f6U, 0xa3cb35bd0f2e41bdU, + 0x70d0900c4ea1035U, 0x36d1cd2bc6e14a23U, 0xfd19e0fefff0e02cU, 0x23d8f5f7f920feefU, + 0x22baf6f60cef37bdU, 0xd10dce1c141515b6U, 0x407fa6c46e1443bU, 0xb498f4f3030bffbfU, + 0xa41faddbe6dbdfc7U, 0xb4f70ec9e7d6f8cfU, 0xeb1e3ff028d87ebdU, 0xd34bfffbc91ff20bU, + 0xd9181a45131038d5U, 0xd03308e6451b05c3U, 0x1ef32ebffcd68103U, 0x3124012a01281e0eU, + 0x9007935ee21d427U, 0x1ec5de26eee519ebU, 0x19231e033809f218U, 0x48e9b334f3fadbdcU, + 0xe50975591ee834f4U, 0xe704105e18e7e014U, 0xc01115c314ac22ffU, 0xff336925a83f5329U, + 0x3df1b800cbddca16U, 0x18b4c23ccdc5f7b6U, 0xe0fef581f3fdcb15U, 0xcfd451b411fe54fU, + 0x94524d10f2745cbU, 0x33c2cf3d09b558d2U, 0x1ff6465d2bf00c05U, 0x111b01c1072a0b16U, + 0xc35debf31e6f5bdU, 0x37fffe2bd7df02ddU, 0xd81002b6ccbbf905U, 0xb9cb121921f18702U, + 0x3f2dbfb49ce2258U, 0x8e0b3002d17010bU, 0xe73bea464414bf15U, 0xfc3fce45d7dafc46U, + 0x33cf0be8fec8eb32U, 0x25bcefe5fdb905fbU, 0xf401f5a9dfffcf37U, 0x3611ebd038cbf544U, + 0xfb1df8e2ec10e1fcU, 0x48c9c6fc22e23ffeU, 0x620d25f1ee3cf5b1U, 0xec10bffb031beff2U, + 0xeb14e0ee160cd423U, 0x1a01ffd90205e7faU, 0xf9281a2dcbf1d8c6U, 0xea81050b56fdede4U, + 0xf2f1cc03ef1c191cU, 0x20bb38d84711442dU, 0x1ccd021ce45e09eaU, 0xe022b8e3e0cac3fcU, + 0x35ecfd0cf2e7ec2eU, 0xaf1fba2b18cad5e5U, 0x38b423e058eed5f8U, 0xd7df27c8f30bc764U, + 0xb112213603e235f9U, 0xc3eaf80024f131c9U, 0x315a1a191ab8f6ebU, 0xf619f8cc15dc280cU, + 0xe3c1c000e406eac0U, 0xf3ce1e5adfddd7f1U, 0xdf34b172f6de2271U, 0xb21cbace400fece2U, + 0x171420cfe3dc080cU, 0x59d5cc4401dbed7fU, 0xc3f74354d6ef1cffU, 0x2ce0f9faf4c9f6fdU, + 0xe3f015f1d60f11c9U, 0xcfeee514400bdee3U, 0x32a27ffb5837df3fU, 0xd702fff30f1fb701U, + 0xc336251df5f037f6U, 0xf3052e1d3be007e5U, 0x3e4334f9fddadcccU, 0x1fedc0dcfa29e4ecU, + 0x3ffd2f0ecddeb30dU, 0xed163f1aeaf6defaU, 0x940f92605fce207U, 0xfd201912260430feU, + 0x28fcf9f6cc000c11U, 0xc111f5f9cfd62750U, 0xfcfe1c0cd3e52b09U, 0xb2d535f83ff2c4efU, + 0xfb12e0f2bb133fdbU, 0xd425160bca34bd15U, 0x18df34e225da0e06U, 0x16180f2bb5521323U, + 0xca3457401014c5e5U, 0xed25f5ea19160f97U, 0xb7c517eb44bcf3e9U, 0xf108051d10bfdb30U, + 0xdc4dbff2f6f9f1cdU, 0xff16ff24c61b14c0U, 0x45dfaa030413fe38U, 0xfedbff01e57fe835U, + 0x21ad508e4cbdae8U, 0xe8ddbff91c041af3U, 0xdec7153614c7ec1aU, 0xacd0f34d035c27d4U, + 0x11fb010df2a7f4ceU, 0xdff22816fa0129e8U, 0xf8092d100bd5b728U, 0x4c1c8ac8b824bf42U, + 0xf220e7e9ef29f029U, 0x7f7142ff701286aU, 0xef1efb189cfb0957U, 0xd324ea53ed250781U, + 0x3d300b1a41e8f109U, 0xd7da47fdfbe8f340U, 0xf20f18fb0604b4ffU, 0xe90b32f223d42fd0U, + 0xf1fb02ebbd0e0edbU, 0xfae227f0080e01f2U, 0xdcf20cbe09e2e122U, 0xd83bfa11ad0edb3eU, + 0x4f3e5d6cbefc0c9U, 0xa5f6202539d8eeccU, 0x53f1f3eb0d1073c9U, 0xfc511446a25fe938U, + 0x9e0217cdd80f10efU, 0x4120003d46150ffaU, 0x1c2e1441282f1b0fU, 0xa6dd0eec8fb0b37U, + 0x2e0550fae8d50cf4U, 0x9ae12b8135b1dc3cU, 0xfd4e04c0f917afcdU, 0xec410fd5ec6c107U, + 0x1c031bdefeb8bdc9U, 0xc060d0f0c0a28fbU, 0x2eef113e6d3ef635U, 0xf4dc0d0451dedddbU, + 0xe524fed12234feb6U, 0xe7c819040906bc1aU, 0x15f21815ea0ae209U, 0xe3d0de5dc6e528e2U, + 0xdee02ff13194172bU, 0x18fbde0ef532cdc8U, 0xe8dfd60ff90d2724U, 0xfd390000b919deb4U, + 0x60ffc2d2fdd3e814U, 0x1f811405d739f6e1U, 0xf3cfd7e54cb61d01U, 0xeadcdaf9f7dffe0dU, + 0x1ffeb32624bff5deU, 0xed03d523cd0d0f5cU, 0xdcec28e7e326fc26U, 0xb595fc14d0bdd83aU, + 0x340f2a714aef0f25U, 0xf058faa3df04290eU, 0xdda0a61c5b640b01U, 0xe8b7090770ef00d8U, + 0x39bf5825efe61686U, 0xa60e69cee1321d29U, 0xe9f6ff3ce1020cf4U, 0x4301261b10f401e4U, + 0x5523f3ddccda075aU, 0x6450f6d81307049aU, 0xbd3dd21cb9203110U, 0x3ffd15dd004921f5U, + 0xf4abe12ed32d3581U, 0x36d2d73ce5fa0dc3U, 0xd9c00f27bcd6b340U, 0xcf4727deb3850340U, + 0x1abd25ec95dd81edU, 0xb4e1192811ff20d5U, 0x31ebf7fafcf5c604U, 0x57094d16d67b275cU, + 0xf75bf6c7d2f1ddaeU, 0xeeee275ef50813f7U, 0x30fd1f050be22c34U, 0xf43ddcbde5d320e7U, + 0x1e5ecfdaa3ec3e8U, 0x931c07e84ec0eed9U, 0x42fad624f707d6e7U, 0xee006c37d10deb8U, + 0xbc5a6f1a2aabbedU, 0xbd620f74ff733dfU, 0xb700da5231f5fa0aU, 0xf9e4e90759060641U, + 0x81050b37e60f4543U, 0x4541fa1ff8f118adU, 0x9c10ad7cc2bcdf1U, 0xb626f238134d09ceU, + 0x1f40e21715d2cb08U, 0xdfdc0f34cf23c613U, 0xc9f6e2110c14eb13U, 0x3607f8f9dfc7f53cU, + 0x18fd21d7f24d1b2dU, 0x61c503f22052da01U, 0xeb5517ff19eeb749U, 0xeafd1f38fac82b13U, + 0xe4f24beede0af7ecU, 0xf0be14b0d08fa01U, 0xf15b0aec05a0dabcU, 0x811535f4bedd1213U, + 0xd5f4ebdc0714fe12U, 0x1832ff4e0afe25e6U, 0xddcb1ef1ed0019d3U, 0x7f60c10130b07cfU, + 0xfbeb04ecc5b0efe1U, 0xb33eb50b917e60fU, 0xdf2c6015fa09242cU, 0x35c440ea24a1fbf3U, + 0x1f10eaef10f10ff7U, 0x3116721b0c190fd1U, 0x4e9d8272ce8cafdU, 0xd9120b10d5e9191aU, + 0xea0809d1410effe9U, 0x53f7fae3f10df80aU, 0x112a02f60e09bf34U, 0xe2ecef09bf10cf2bU, + 0xee693ceeaeecfc8U, 0xd6d0c508e1220516U, 0xe81a2af7e6f2170cU, 0xdfd6051aff0cd7e0U, + 0x230bd602e0e215f4U, 0xe3227f2b0508f619U, 0xf4005850405aac2U, 0xfb01eef0ee152301U, + 0x2cdae0f32aebeaccU, 0x11f5c715ebccfbcaU, 0xe2272f03010003cfU, 0xe4efec161f49b0fbU, + 0x2afb150fc65210dcU, 0x1102ff153deb40b3U, 0xd31ddcebcdec0005U, 0x17131305ed08f70cU, + 0xfaf8e0f60afff0ffU, 0x1c2021a0008051dU, 0xfd1ae2cffd0823c7U, 0xfcccfd1c14ebf339U, + 0xf142e9f017083e0dU, 0x130b370b181007f2U, 0xe10df203fbf304ceU, 0xde10d9130f0afffaU, + 0xe000071ff606fcfaU, 0xeddcef0c03140a25U, 0x1417eff3f6f01c0eU, 0xf00fcdcd247fd83fU, + 0x57fcfc0528002adeU, 0xeefa16e703f80a0dU, 0xc12291ff613d4f4U, 0x2b02d944e1eb1800U, + 0xdde1f5c4bc528fedU, 0x23414aa3f605d12aU, 0x3887040cecc01629U, 0xca2f65ff0bdf9318U, + 0xbe57081f5fe2c9e8U, 0xaffa13e8d31608c5U, 0xe23806322c92ea33U, 0xb71ee4aae0fdc6ebU, + 0xdccb812bac32bedeU, 0xe2c5e71511a11a10U, 0x4a18e32e76f2e12dU, 0xb25fdb538313818U, + 0xdaa1509eada331aU, 0xeeb9f91fdb981d23U, 0xe1c10612cdd92705U, 0xc9fee131101f4063U, + 0x4f63ad240cae6f3U, 0xfcff1c0023e68532U, 0xe6c153aa3317bef4U, 0x7f9e11010b0d00e2U, + 0xf54666fffef0f634U, 0x39e5200c17eaa054U, 0x1de9e8dfe345208bU, 0xacffdb173f02bfc2U, + 0x5a1cda01f9b4c021U, 0xe83601f91ae2660eU, 0xf7d82970d401c82aU, 0x13fe0afbbbc849feU, + 0xc849dad9df16e1feU, 0xb021aaefa0a49fbU, 0x2317e8e5c4f800eeU, 0x449ae91549e47fdfU, + 0x61aee3c311e0e3cU, 0xbd5e2db491413fcU, 0xe327ffeeb33ae311U, 0x8c1dd3de21fdea1bU, + 0x694a1236fa14172cU, 0xf512ffd2ceb74d21U, 0x35dbf4120900ea49U, 0x1c510d4cf9dce129U, + 0x3ff8b5cde4232110U, 0x4ab70e52eceacc36U, 0xb8e7210de6b30318U, 0xe1ff95e7cd9e1c5eU, + 0x3de1ddf631e7fa02U, 0xe130f80ccdf9edf6U, 0xd643ef9a8ef914acU, 0x2ee0ba21a131df2U, + 0xaef811c2b0ad0eeU, 0xccfe1630f015e5ebU, 0xfdfee70f41200cccU, 0xde8b06dd0cf4f91eU, + 0x1ee0ef2e29e607f6U, 0xdcd343f82ffff0dcU, 0x1323faee06c7e0e6U, 0x2a1ee021f91de8e8U, + 0xd5c534d80527e104U, 0x1bfef14802f4dfcbU, 0xfd230347ecf04dfaU, 0xf91ab3bb2b6ae32fU, + 0x21e4e41be33816fdU, 0x1be5000dfe1cf148U, 0xddf43bf1bef608d2U, 0x136e915e61506b7U, + 0x25e9399c003bd9f7U, 0xdbf270c9fdff0820U, 0x2c222337ee04df1dU, 0x152f223d8104ee9U, + 0x27eed1d61856170bU, 0xc806ccfbbbdff544U, 0xf7c60619280d2519U, 0xff0605f4be0cf7c9U, + 0x470adbf1f1f710c1U, 0xc9d67ff2dce32c22U, 0xfd1e24dbecc1cf19U, 0x3e07f04b1fbc0522U, + 0xf63c0eac0acff63bU, 0xc12122c1cda9e9d5U, 0x260335885ae33e2dU, 0xeb07fcf23a2125d5U, + 0xc6f7f8dacfdf1c2dU, 0x23fb09eddc5a24daU, 0x3001c538d6030c49U, 0xf0730eed84ef79eU, + 0x7fa7d020ee19c612U, 0xfa14d332241605a3U, 0x2a2e193c40bb5f41U, 0xf1e4dee70f01c2daU, + 0x2d2d471ee9e0f3beU, 0xed2b621e75524dcU, 0x6c9d3f4fad5e2fbU, 0x3af3040a619ce0fbU, + 0xe5d51521ae02a8eeU, 0xd10dea5133092efbU, 0xf4f60ff328aae6d0U, 0xe21fef38e34697cdU, + 0x2ea52112f16fe8b7U, 0xdd0fc1550d02ea43U, 0x2cf2651dbdaa2001U, 0xfdd6b12bfebf4008U, + 0xdeda4f365107f20fU, 0xcca3ccabdd6944e6U, 0xcd47f65121e7f10cU, 0xafe9eab217dbf9f1U, + 0x7a21bb68edd9dae2U, 0xf3e7dfa2f5450204U, 0x81a1cd0cd31ff7f0U, 0x2c0ae0e23c3915e4U, + 0x30fde0c3b309e50eU, 0x60eb03e63115151eU, 0xa3f81806c42df5d9U, 0x3c1316cef0def1bdU, + 0x7df33e10b213906U, 0x111e051c00404c18U, 0xfe26d628e4da260bU, 0x2ffbe9300ade510aU, + 0x15e40cfe2efd3405U, 0xdc30ea25e6b20a28U, 0xdb2aba33c9d6571aU, 0xfe81d42604e12518U, + 0xc14bf054c025bbffU, 0x5bc90605e115e5d3U, 0xe601d716cffd1a06U, 0x2d0edee22a0f334fU, + 0x6a0e25fb3b3436a0U, 0xe4b8393ff4ecfdf7U, 0x42eb10244a21fc15U, 0xcb2c4148e8d0300aU, + 0xa22755cf1506e1cbU, 0xa01b46f2c2e5fdc2U, 0xf918d5dd04ee1a12U, 0x27eb14012aff0923U, + 0xfdbaf0e74c186a19U, 0x3ae7b8cd3703ea1cU, 0x2600b4dd261641a1U, 0x8ae43bf50eb0d3adU, + 0xce28080436e0e00dU, 0xcb9fd528de33eb2cU, 0x161e0eda90e70752U, 0x4914c5dbf3f90c0fU, + 0x3134a72e0e057fceU, 0xdae205c1b11bab0eU, 0x27710a3bb14912cfU, 0xf33f32f8e41bdc04U, + 0x1a0d4ce9d8260eefU, 0x2edb1d7f604331fbU, 0xd0ea323610c91d25U, 0xfe1d0132002a17c0U, + 0xd8d0d9d429e81fe8U, 0xd5f3fbf2d6d7f1e7U, 0x10c00210db132cefU, 0x1bb838cecd8f0731U, + 0x2cd1d94527cdbcbbU, 0x1ef41dfecefeb5cfU, 0x13e9a6bb27f31029U, 0xde63918f2f74942U, + 0x20fdcbf334ef0938U, 0x3c27cfc0b20f1c9bU, 0x292c472613c108dbU, 0x50d1a323b60aeca0U, + 0x5af336c61eea37b2U, 0xd413f4e20016b9beU, 0xb69c44b42a3ffcc9U, 0xc55da93115c31335U, + 0x71517637ff1fb65U, 0x49e106cb2a9f0e1eU, 0xf037edbe16050033U, 0xdb05b1213705ba30U, + 0x16c6fcf2c6f2e2e1U, 0x26ea191c24112316U, 0xa6523643ff0955f0U, 0xd8f0feb3c0551147U, + 0x1cc132183034ede2U, 0x24d31cfcd3af2b3bU, 0xf2297baab13d0918U, 0x15f505060ed24b3aU, + 0xcbd37ff740161404U, 0x4808df23f11d143eU, 0xd01ed4ecffc5a4ecU, 0x5bcc41b5b566f30cU, + 0x33e4ebd1e1c0c2f8U, 0x23016fcbefff2a5dU, 0xe1c1cb13f51a2b4dU, 0xd11f539f10651afU, + 0xaf300c471b4028f6U, 0xbb485df9d5d1dd0eU, 0xf2f39719cf219b1dU, 0xfcfbf4170e2a12e8U, + 0x9a7b3b9e0d4c3cdU, 0xe9a8f7fb07eabf25U, 0x11214133503d8f5U, 0x1efdfaf40cfc40fdU, + 0xd3bb04fe001007eaU, 0x3a227f1ae9adf003U, 0x3f0608d7311e36f0U, 0xe229ec26e2041602U, + 0xc22bdc4dc0bdfdf0U, 0x1b32171d2330fdf9U, 0xfa030cefe6e2f3ceU, 0x26e70a2ecceb1afaU, + 0xd30a4f69f33911f8U, 0xa183120eff01606U, 0x2a0e1b0435a7f7bbU, 0xdd3ae5d6f5fc1ac3U, + 0xc3fbc5f1f1eff5c2U, 0xfffcaf0cee1931ecU, 0x20de31380cdbc10dU, 0x6a1eeef3fba3c9e9U, + 0x1bd3e43deb5eb895U, 0xcb244432d3e53203U, 0xeef93bf71d58ffU, 0xde070e59f308d0ffU, + 0xe8cc3a4d59c1afccU, 0xfffcb54ef1732b4U, 0xbf24cdfb40e2da00U, 0xdd0964e5e0bcf6eeU, + 0x3daed2088b3fdf37U, 0xafaeb526f4542641U, 0xe0b681dc78156576U, 0xb4020ffed9f637eeU, + 0xdeb9120bcb20efe8U, 0x292fa332ea250ee0U, 0xef3afdbeed1f23c6U, 0x599c6810614e6f4U, + 0x1dd9d60312f540abU, 0x6c662ae4f90a6b04U, 0x1802e8ec231dedeaU, 0xd6aad9f100bbebd3U, + 0xdedeeb16c4fb1009U, 0xd33e31c0d03422e1U, 0xc43eef0730b0e6d5U, 0x10c8394dfcce3d26U, + 0xea00b80f261ac801U, 0xf49043072a1b3a42U, 0x701ceedbce4f6d7U, 0x30bbacd0b173df78U, + 0xd40bfb14f6463007U, 0xaf1cb20fe3f023cU, 0xbccb1131f22deb09U, 0x2802c4fdaae4c7f8U, + 0x5101e4f7372302a6U, 0xc9380bff13d805b4U, 0x4d7eef6befd1d27U, 0xffcedbb5e1e1b253U, + 0xeb00d00adde144abU, 0xc21dec0e00cc6e8U, 0xac16e4d2ffaee5fdU, 0x182313befa1f0423U, + 0xe26f1ff37e72dcdU, 0xa24cd3e0d8f22604U, 0xe107fab54d31fc06U, 0xe5e3cf03e9672029U, + 0xd321b90501f6051cU, 0x5bfbe4812a3ded07U, 0x2da6fa10ede11c09U, 0xbd3a2bb5d894e36cU, + 0x57b63f18ddc0e0e4U, 0xecc0ef1a1deadff8U, 0x240ee38a20d9812aU, 0x4fe027df07382f4dU, + 0xbc3d02b003f321dfU, 0xf90a0759f8d43500U, 0x3919ff0119403009U, 0xcc3cb4be0d1f542dU, + 0x13e7f6f82ffdb10eU, 0xdcfbe2d938b9a8ecU, 0x4e18ee3c092aafddU, 0xe49d1f124ce4f903U, + 0x1b6d8f5b3b7bc00U, 0xf330fbd06cb357f1U, 0xbfe60af70206deU, 0x2f9cc9e9e531f80eU, + 0x31f8fcb906ea29faU, 0xf04a05d20c1be946U, 0xf6d6f53cf54c0634U, 0x3598baea509d0723U, + 0xe81eea2dfe3fdf27U, 0x903e51fcefeb1edbU, 0x2f263d011be51047U, 0xfc20e9e1d31b2614U, + 0x2b2108e01ec9ffb4U, 0x96d7fe3af918f1e3U, 0xde6233edf301d93U, 0xe11cc2d7bf7fe84fU, + 0xecb9da07ccf6621cU, 0xda03171fc011c3faU, 0xa4c9ccfbff5f2a3eU, 0xda12a608e50cf318U, + 0x141416baf929cfe2U, 0x89ce7ffd9bc60faaU, 0xdcfb2417e719eb47U, 0xee2e2229a3f40709U, + 0x1de2d2af380c0c63U, 0x5b8d1de2d02ecfcU, 0x55f142db00f2aafbU, 0x4ccb9006f70108f1U, + 0xfc000c433f36bfe7U, 0xc29909fa05f90313U, 0xd31110652bbe836U, 0xde372d05dddfd419U, + 0xbd43f916e1c91923U, 0xe5371fb60111b419U, 0xf7cf25e002f134e5U, 0xfb33f114d3062f2eU, + 0xa6da1e65fb252b37U, 0x7fbfae2c2f1ccfdeU, 0xdb0b29b42226f2f9U, 0x151f46282d07f2faU, + 0xfb0522d6090143e3U, 0x2af5dd2e22d9f7fcU, 0x29d1230eea370105U, 0xeddc3125d921c306U, + 0xfac56f111b1efd06U, 0x4715f82f15394113U, 0x819d9270a6ac712U, 0xc6030dfdfbceef10U, + 0xe6dd5ca5dab1062cU, 0xdbcb053ddfddfa15U, 0xe34237e035119ce7U, 0xee01010ddd071d2eU, + 0xdee42017cc81f1feU, 0x1adce511f12aecf4U, 0xededf8ca10c4b86cU, 0xfbd6c6b810ee0627U, + 0x8d41ecbf34bca0cU, 0x2ffcd327edc709f5U, 0x3df02b12e9f0e1dfU, 0xe38ed000df030feU, + 0x937d8e4230f0cedU, 0xff10050a2a2b0a14U, 0xc4e23220c007f8c9U, 0x18f10f095d16ac01U, + 0x2122aecfd202edf5U, 0xcf112cde28aae605U, 0xcecee227d72dfee4U, 0x25f8c403daec1b12U, + 0xe0cd2f0f5dd8023bU, 0x19f51defdc0336fdU, 0xf422fd07dcfa4bf2U, 0xede7fa3ac7c648bfU, + 0xffd5d02019dfddfdU, 0xc4eed00c0ae2becfU, 0xfe13149ded2d3d16U, 0x50f34e62ee7c0aeU, + 0xce43ec1f4ebd12ffU, 0x22000ce51b0805deU, 0x4712d516effc1507U, 0x1c0dd9f11202ff1aU, + 0x28bc31ca20ddeac2U, 0x25815802efd91aecU, 0x314c1efd0807e919U, 0xa02dc018264011e0U, + 0xe013f0b1b3d31a96U, 0x9ed242f3def61ae0U, 0xf314eb13fcf7df08U, 0x10490028ec35100dU, + 0x1c94dc0c3d2c507dU, 0x7c7e84116f91f0bU, 0xe6fb2133fce3d0U, 0x3840ba261fe1d5feU, + 0xff381b1d13e3e0efU, 0x1bcb2e0a06ecc6e1U, 0xfcc9a6c032e0033bU, 0x11223e3b2fdcf51aU, + 0xd91824341cdffa1dU, 0x81362207a5c9bc0cU, 0x64f06e641f6e5d1U, 0x1502fee9f2122027U, + 0x3dce5f91448cf0bU, 0xceee01ce36ef21e5U, 0x9b33adb00501d622U, 0x2327e3d008d00624U, + 0x139e8ab013a1a2eU, 0x27dbfae925eb2c7fU, 0x1bee220393e1bae8U, 0xe327da0bf703ebf4U, + 0x28e1fe01e9ecd1fcU, 0xe9f72be4f134e826U, 0xaaf970e2eecceb3aU, 0x25df0bf8df0ac92dU, + 0x44f0c402080eec38U, 0xdaec62d611d9ed18U, 0xf2c816fe14092afdU, 0xc1c3d71233483e18U, + 0xbdf82ac20fff0e18U, 0xe7d6e8e5f91c2107U, 0xa22d06b503ffd231U, 0x4affbc03b9332223U, + 0x2df410c92628f461U, 0x39edfcdfeeffdd56U, 0x16f91ee08110f8f5U, 0x4143fd7f0713fdafU, + 0x533105345e0d0230U, 0xe7cf45d308eb4d1aU, 0xbafb3edacfe512e2U, 0x1121003ef8e7c3f5U, + 0x284152000a11c8afU, 0xb23717c5b7c1d8fcU, 0xf0e323bdd507d8f0U, 0xf0b216c401fe0ac7U, + 0xf40caa070e02bf3bU, 0xe54f0328bbd810f7U, 0x1b0fe3464c19ccb7U, 0xd018b94120e0af50U, + 0x56d4d44ee7c6810aU, 0xf91ff90c1e28b1bdU, 0xeccae43cfef9004fU, 0x3a972bf4a031d934U, + 0x36a73b1c03c63a0fU, 0x5eefe0d50b56d939U, 0xc2571d351e275ccdU, 0xf85232cb251324e1U, + 0xbca289f2a3609918U, 0xcb4284f28d3fdc2aU, 0xf607dbe4f6060cbcU, 0xad281dcdc9c620e1U, + 0x332afcd2fa045f38U, 0x2b26cfff5d1f46faU, 0xe7c0e0cad31bee33U, 0x261606bd1217261eU, + 0x6e3d5e0ceae1126U, 0x1138f7028138c7f4U, 0xe5f9f6da07d62df5U, 0x36df53dbff07fc24U, + 0xfbe8d5d31b0b168dU, 0x2f37c145faadedfU, 0x1d035bc60e38f5cbU, 0x3308e00bc7195c31U, + 0xf5ba15d0ec0eee13U, 0xf5cacf2635f71107U, 0xeec8f4dd0fe71941U, 0x3104e10cc2022ddaU, + 0xc3e62842ea0fa32aU, 0x35e4063731e10199U, 0x2a29f807edc5eee3U, 0xe61a0238fdcaf7e6U, + 0xb2f208f30cf828f3U, 0x3cf7b8226240c3d6U, 0x15eee33311264126U, 0xa1d30a8eac6fb0cU, + 0x64e0c4536be3504U, 0xd3f302c2c9f2e134U, 0x25bcea40de013234U, 0xfbfd0e6024e117f6U, + 0xbbe617d8f6fafc15U, 0x11b2bb0dc23f0556U, 0xb7fe616435402eaU, 0xe4dbedfde2050d1dU, + 0xdc144f430be89d36U, 0xb9e6c1fa6a37d5f1U, 0x95c936a45bf326aaU, 0x28e0b6d809e8e9acU, + 0x162b48e83f25e605U, 0x26d4d2be0d8ed108U, 0x1fded3ddf316d038U, 0xff0a211dd5cc8902U, + 0xf30a0a30fff73d14U, 0xcfb60008d3051249U, 0x3342103e4ce7a654U, 0x3092190d4981ff2bU, + 0x6562effbe2cd1050U, 0x96d64ce6b0de140cU, 0xbd2351cee22c4419U, 0xb3fdf5fa08ddd22cU, + 0x2bee16b5f6ac2f1aU, 0x858f1e7d9f42dU, 0xda170e0d3ac2d929U, 0x60b5ef22f2460111U, + 0xdeecf0a7b4f5b5feU, 0x1e207509bcf0400U, 0x3234e2ee67aafdf4U, 0xf402db0221eed8eaU, + 0xa8008c18e92eb5e2U, 0xccef08c733eaebdaU, 0x7f1ee610db3bef0cU, 0xabb20e62f0be514U, + 0xf20ab9eaaddfe61fU, 0x2ba7344f3cfd5225U, 0x8ef4e766034af035U, 0x8170f160bde150bU, + 0xf8d803fcea0ffb28U, 0xf11a392e1419d300U, 0xfd19f9fbaf7a30f3U, 0xf246c346aad353f4U, + 0x8c22a3f1ed622e2U, 0xf316f624260de543U, 0xfb1e5a13ecfaf6c3U, 0x2b2321c1e8f22cbdU, + 0x47df3224b1c00315U, 0x621800caeb0e4888U, 0x17c2c9bb1fecc448U, 0xcd0fee10f52d1025U, + 0x4a90178020781efU, 0x1355b9e1fcdfc1d0U, 0x131017001de5fd31U, 0x20f5dc0dffdd00a4U, + 0xef4ceb571747c3d0U, 0x160a2f3610c50081U, 0x2dd9e8ab4ffa2ac0U, 0x1121cd080fa5dddaU, + 0x1ada2c4c1a13acd7U, 0xeb17dee22307fbb7U, 0xd40108272622fd1bU, 0x21d813c415cb19b8U, + 0x3730225c3c3d2022U, 0xf20153f4ea451d3dU, 0x4e6f17e04eaa1b66U, 0x2f130dc1212eeccU, + 0xb6a3fc26b0ced818U, 0xfc38ecf2ec1db360U, 0x372c1bf53ca0b6c3U, 0x8dafae4042a14edU, + 0x617d1da4304e510U, 0xe4221107c8e20bf2U, 0x90ffaf022f80f0eU, 0xfb321de0d7e0fdd6U, + 0xef26c923053a120fU, 0xf010fbd2ee0e19f1U, 0xfaf1fa34002c25fdU, 0xeed304e4c3160881U, + 0xeec4240ac741e6d9U, 0xd5cde944fdce29b2U, 0x2e15e4d522000c1aU, 0x481cdd170a34160aU, + 0xd9dfc16f2d42b15U, 0xeb23fc4701f4ecd9U, 0x311024624bf3f0dU, 0x1406c8f6d0ebf632U, + 0x3bdcbbf804ddc29eU, 0xb081ed26c60bd871U, 0x72a3925291c21efU, 0xe3fdce1b0ab5f3fcU, + 0xb0420ae56e07930dU, 0x46126f1f40c91d07U, 0xed03f6510035c20fU, 0xcffb9ec0f233fd19U, + 0xe1ee5ce43cfa1daU, 0xb91e25e8c2f2fa02U, 0x1c184cecbb28d397U, 0xd80eede41e26d9fcU, + 0x53eacf21321bfbf1U, 0xffe50af03ddffb3U, 0xdc9c0ff4c4222b1aU, 0x891b6d6dc1711eaU, + 0xd61c09360421f9e0U, 0xb8f0d0b0a810a12U, 0xb89e0de645ed5cfaU, 0x36d8e92a07d03cdeU, + 0x1ce55f0e98dc9fc3U, 0xfdf31c1cce110305U, 0x2505cbfcee1b3509U, 0x6d730f948e509f9U, + 0xb0480d15ecb0df1aU, 0x5262c1e0c5a1ce7U, 0x70000b4129e12835U, 0x795fcacbdbcf3f1eU, + 0xf8ec500729229ef8U, 0xc2e003cad90aec1dU, 0xf0342fba21fdc636U, 0x1641f0e8e5d615ecU, + 0xef45f92523373830U, 0xe41b001c194b1318U, 0xee4ce7fd03c31accU, 0xdb134ef9f3e419fU, + 0xe2e9adcc36ca4014U, 0xea2c2906c6d8d9daU, 0xfff9eaf7e9e31bf2U, 0x3716bffdbf1b0832U, + 0x9230fdf6f3d3e60cU, 0x48b0c2d3c200e1c0U, 0xc481ae029038ea2aU, 0xed3a2fe1c21af579U, + 0x37111c2c72daf2f5U, 0xecf967f2171017d5U, 0x4e2c2b4e097ff570U, 0xd22133f0615c3d7U, + 0xec0046da141c11d9U, 0xfbfe253a16f7d6c3U, 0xbcb642b2f2c0c43U, 0x1a93f040fb4911b9U, + 0x1afc2919dfd0b3feU, 0x1c28dced59e1a113U, 0x21fb1e253907fb11U, 0xa526b09c0809efccU, + 0x7f152e1de1b3ee45U, 0x22fc33a30efe2ef0U, 0x8acc0a0817d1bbf5U, 0xd1445d0ee5e82906U, + 0xeffdffa628eef9ecU, 0xe111c7eb3cd7f82dU, 0x5139f8f325f7c2e2U, 0x2136251536112a00U, + 0x120c238231d381aU, 0xf45af7dd420cd547U, 0xfbf70d08e4d1bbd9U, 0x103600e30af2e0e8U, + 0x16d4151c030f231fU, 0x1e1cf5d2fab81c15U, 0xc9ea02e7f909cee9U, 0x515704ed46b2d6c3U, + 0x7f40713fc630ff0U, 0x93bdd74ff0631f6U, 0xd3af1e91ab9fd1aU, 0xb2020608f01313acU, + 0x1962dd03f5ec0429U, 0x1d281cb6f4d3fa7fU, 0x41c30f2fb4b648e7U, 0xb9fe27f913a8f212U, + 0x3f90b33eabb1719U, 0x4128eee13cf3000eU, 0xdbd1f2f61014c825U, 0x35d62a21ff2ff7deU, + 0xcb2f6215e9d2819bU, 0x20c2061de43836d0U, 0xc5e3f6dcf6fe1205U, 0xbef1f1093bc1e514U, + 0xa2e2df0ce9061815U, 0xeef5bffd06ddf0f5U, 0x2b0d10f4b9180e33U, 0xdeb7fcb4070b3ee4U, + 0x370ce2f3d7fc4998U, 0xf2dce5ef36db34deU, 0x1cf6267bfce6d2ffU, 0xef51f6ce23ee06f4U, + 0x7fd6dfb1e951e0c8U, 0xfef5451ee9d820eaU, 0xd51e3905fe1114f4U, 0xfbfd14e31a1b02fbU, + 0xbd041319eacdfb1bU, 0xad971b3812ca28ffU, 0xe9540060e7925c1bU, 0xfcbdb6d6d8dd0cd5U, + 0x2993fd09ffd2f3bbU, 0xd810f926e0161ef9U, 0x2fad7c54cee0715U, 0xa12df18d51a2f05U, + 0x5811f927e3a52837U, 0x11dec900ecda35f8U, 0xddee3d1b31cefd1eU, 0x1c2305c6bc152f16U, + 0x12041ff9e3fcdbc8U, 0xebc9272eebcfe6e6U, 0xf29d121210c51e7fU, 0xae20314173b2a33U, + 0xd110080919f121d9U, 0xfb9c2413190d01f2U, 0x2606ee1e02173317U, 0xfbc0f206d1c828c1U, + 0x2bf4b322e404dfecU, 0x19fefe2be60f08d0U, 0x431b7c51c1ee601U, 0xd9f2edf707160b21U, + 0x4eeeff10dcd72211U, 0xbe523002ff1220dU, 0xd9ff2ce938dc1929U, 0xfe26fa00fce53345U, + 0x1d07342c1e0dfc02U, 0x23011a32360dd400U, 0xc0fd1409de9cc3d1U, 0x26d7f2e5d7d816f7U, + 0x34ea33f11f00deefU, 0x38d017c23bf7b00fU, 0x53ebd6d7ac7feed6U, 0xcfe7310bd6dfb7daU, + 0xfb0328fecc012c5cU, 0xb3d7f4ea0cd863d1U, 0x51cbf8f2f51e9910U, 0x2bd1fd08d1ea07e6U, + 0x9052f51cecb0b20U, 0xf1e4d91c0d0efbe3U, 0xdb203fdf1b1b21f4U, 0xf92529188e25e9d6U, + 0x7008e6fef708340dU, 0xdb11d4eb20240840U, 0x320b00eed1da0821U, 0xf9f52cf820e70fe1U, + 0x6e9dbe3201a17eeU, 0xd4fae81912990b08U, 0x817dc0fe3cc151cU, 0xf8c3ce0c3c260405U, + 0xe24e8bede9cdca03U, 0xfd0dedba797e0d0U, 0x4f4bc05da6d25e0U, 0xf1ff09e2fc2f047fU, + 0x50090cea37d802c0U, 0xe61e430004d910e9U, 0x716072af9632d46U, 0x1b04ff16a81be3ecU, + 0x53e0a01042aed5ccU, 0x3713072420cc2b23U, 0xf520f90824eb1227U, 0xbcc1ade62423dfe2U, + 0x2e03e012c0140ae9U, 0xe1dc3ce3de29f506U, 0xa77f63091d9c8322U, 0xf20f39fd093e39eaU, + 0x2efb13c8030a00a0U, 0x27e5e7730f0afdbcU, 0x364b20b70210d7e1U, 0x2618a5f5d05ffce4U, + 0x3d0df618cd6709fbU, 0xf52bd52f62ef2bb0U, 0x5321ee6efed2323U, 0x60c722e5700f6107U, + 0x303326ffd8f6155bU, 0xc53ae13c3a12eee9U, 0xd05a2bece00fdfe8U, 0xecfbfca6e8da41baU, + 0xcd5af1ac3f361ef5U, 0x6b0ccbcf374aed74U, 0x55b4040492478120U, 0xde43f00ed23201c2U, + 0x27d802fb1efc1576U, 0xa1c9de40c04be515U, 0x9bce119bdcffd8f8U, 0x690ae2c426a9ac2eU, + 0x4f24a7d58e04f106U, 0x9c23fd09ac1ef70eU, 0xe1b9d6d4db36dfdfU, 0xf325f11b101f6300U, + 0xfd13fea8c01b0604U, 0xcbe65e3c95fe17e4U, 0xcf02de1aef0dff16U, 0xf946dd22c8bcf6f6U, + 0x1b13d2f9fa32337fU, 0xdcdf0df400da2740U, 0x59f303fefa0cb8f5U, 0x3730d410b01bdeb2U, + 0x66020d130008b10dU, 0x2033efbeafd0615U, 0x142d060e14f1ea1cU, 0xd4bf033090df51aU, + 0x2634e01f0606ec2dU, 0xd74421c5f1a4e82eU, 0x1412f4c00a060dfaU, 0xf9100ad4390cf0e7U, + 0xbdf9ccf80537de0fU, 0xe0c2e31de2907beU, 0x2ef53a36e2fe19eaU, 0xfacef229e80f19c5U, + 0x1fef0c070fdfdc23U, 0x2010dccf151de6d2U, 0x15ee2021091cdf17U, 0x8140c5d5c4dbe415U, + 0x15412de8e5b4d7f3U, 0xfde72d0fb5fff13bU, 0x14c6c654b20faa0eU, 0x2e92af2c517ed2eU, + 0xc8dee1f821fbf9feU, 0xf1a208d1d917eafcU, 0x381c02f8224aede1U, 0xe6f9b813d1db1e6aU, + 0x3481ecdc1fe9cbddU, 0xd4d7e9352aeef8c1U, 0xfed47c4fc14e622U, 0x4ef917e810d7e531U, + 0xc42e06e30af906e3U, 0x151257f8023406f3U, 0xff2e2cd61c23e20aU, 0xd0cb27e611f63f2aU, + 0x4513b8f712e3fcfdU, 0xacdc2416160bf60dU, 0xc60146fc06d5cbc5U, 0xfeceebcc02461acaU, + 0xde12c0cccd060f0dU, 0xf91003d31d28352dU, 0xfff1f7e4c91938e1U, 0xc7e43502dec5d8f2U, + 0x22dd290c4c102920U, 0x2c0506d2d0fecd0dU, 0x29ef15ceed104dbaU, 0x48150137c02261faU, + 0xcd971f9bfe28dc1U, 0x3338e33fd4d5f1deU, 0x242b47c1161a19faU, 0xbf445f36232b9ccU, + 0xf87fe3ffffe5eb52U, 0xf028d50f3e3443c0U, 0x1868682716d1e81fU, 0x562409eb1fce08e0U, + 0xf34822f20004f5b7U, 0x3adef90630164be1U, 0xf24fc092b06c529U, 0xecc2d3d9170634efU, + 0xff5ec06fe18c3f1U, 0xff16f923bfefe4ddU, 0x17e90f2a29f41ad0U, 0xe8cefafb16d9c522U, + 0xbfff72d2dfd01ecU, 0xe5013c2a31f1f9f9U, 0x102af00d00caedefU, 0x151fe1f6e2360a1dU, + 0xae515e7f52c02d7U, 0x304131232f704fbU, 0xf60cf41914f22be0U, 0xfb1cdede157f07fdU, + 0x18d5291cf02513dbU, 0xf602ee0fe42bdbedU, 0xc9eef7ecc2f80900U, 0x290f261423f9eaf9U, + 0x53ce812bc9d613daU, 0xaf3071ce50fff02U, 0xea16f8f3182751eaU, 0xe5b7fdebdbf700feU, + 0xfd04290111eff11fU, 0xe521dcd9f0ec25d8U, 0x1b551dfd01b5dfdfU, 0xf4de87183612fbefU, + 0xc5c4f8d32613d99bU, 0x4514f3fbcd11edbeU, 0xe0dce647edd4faf3U, 0xf22efdfd2b0605e3U, + 0xfde6f406f928c516U, 0x1d07eb34072839cfU, 0x18f83e29ce27fa24U, 0xcdb9f1c70ff31fe8U, + 0xd5f6f23805fac011U, 0xfdf3160011dc0304U, 0x5e21c1e082432dbU, 0x607da09b3083bc7U, + 0xf9d51a18f80bf4dfU, 0xd8dd5b043b071602U, 0xf63e4bc403d41dfaU, 0xf11d1033c11fc27U, + 0xdef3310d0afffd03U, 0xbfbe30345e814c0U, 0x1916dd8b14e820d6U, 0x2ed88100e91b06b3U, + 0x9f033292b512ff2U, 0xfed5ed230828ca06U, 0xe8f43c1d03f3394fU, 0x2e0d1fbf081031aU, + 0xa81c1e1bf4e30be2U, 0x2d0ae1f03528ead8U, 0x6fd0b19d84d0ddeU, 0xcf3a4d06023d0731U, + 0xaeb07e7feebd8bfU, 0x2708ed261afdd720U, 0xdf02404c31cae05U, 0xbf2f260fedc71db1U, + 0x54e61c62e909ee1fU, 0xc8c8d70912051819U, 0xf82dd71e36e7addaU, 0xfb10e12519ef08bcU, + 0xc41ff9d9d8dde712U, 0x1707f6c627c9ff11U, 0xc30c3ac722d7facfU, 0x3f39d7e1173681c9U, + 0x440bc1dc6f5ef2a9U, 0x142df8f1f3141becU, 0x1e43362d21648U, 0xcd1cb9caaae1f6e5U, + 0xd707c8aefdc1bd15U, 0x16f200e0b6e3f9ebU, 0x8bc9fc421db90f7eU, 0xeeee40e23316eed9U, + 0xfa0ef04ac7d347b4U, 0xe30926fba8d3e821U, 0x301614b90dbfbe1aU, 0xe23d00eec0431030U, + 0xf3210bcb2e08e803U, 0x57e8b0c5cb0efe06U, 0x2b55f32e37fc4df3U, 0x18aae0fcf9c7beU, + 0x651d0303eb1c733cU, 0xa277bef84f25ec0eU, 0xe7450a71cb24d0dfU, 0x10dffb81281ad8fbU, + 0xec3090213c3e432eU, 0xb9c3ee14b0e3de32U, 0xb7ecd0e9bab83006U, 0x22cf0fe815f44a0cU, + 0xe427d5e7da9e0427U, 0x2bac9fbbea0e24b3U, 0xa5f3984ed4481f03U, 0x3f410dfea172002U, + 0x49332f1105ef2b00U, 0x1b2623b31bd1fdf1U, 0x163dfafc00250f54U, 0x4414e135b31be5f2U, + 0xf7e8f020b02f53faU, 0xd6aa1becea2b3841U, 0xc513df9af5f82ebfU, 0x1cf45aebe9a727d3U, + 0x341ad9d9430c462dU, 0xf537182ff30b42f0U, 0x141a05d2d9dd4440U, 0xfce202df73eded24U, + 0xd708e617e70b25e0U, 0x23a8b65206080733U, 0x2223d317cd661b0dU, 0x4ececf81d7cc002dU, + 0xff3e36564bd82019U, 0xb8cb75d830e50bf9U, 0x301e31432f09270aU, 0xd5f4e531f627b808U, + 0xede7ce26cfdf0be6U, 0xd6ebc5fd00e3e4e6U, 0xe91dcfaf07ae0e24U, 0x928fe150e17ef0bU, + 0xf8e5e7d6c1d82bfcU, 0xc201ef1de0d1b10U, 0xe3363bf103f4e2d4U, 0xd2ee1f32094940f9U, + 0x10f5eb0b20d51b0fU, 0x34f9f407f723fef1U, 0x2648efe53415d5bfU, 0x3803c9fefe091511U, + 0xe13f267fef1202daU, 0x336f72e212e36e3U, 0xf819f2fa31cd06f2U, 0xdf18fe27e8e8b1f6U, + 0xe8a0451c09100e28U, 0xfff41406f581a009U, 0xfb0b38a4200df58cU, 0x10d72af50bcfdcf6U, + 0xda3a1b3cc6f31804U, 0x40df14500dfd110U, 0xcd0f2814f31d0aa6U, 0x4f040bfa1129e2f1U, + 0x1b221610bb20efedU, 0xbf2ddbde450714b5U, 0xeb0428f32e1fddacU, 0x1ffb032d49c45ac7U, + 0xb2dd37e3fec7d4f4U, 0xecbbb015e3b704c9U, 0xfd21ffe200f504e8U, 0xed2219bbbfdc06feU, + 0x29a9f0b1170601abU, 0xfbbbf23ff62f08d5U, 0xa3fcd6c5c9d6d73eU, 0x50bfca55ae2f7d3U, + 0xca25dfcf25092e13U, 0x16ebe8f0fdce2b2eU, 0x18dd01e7be18ea81U, 0x2041115fafb182eU, + 0xe116e929eef9aa1cU, 0xe713e80ebc12f530U, 0xcdbee8f3c6edf8f6U, 0xc9b242fdfe4f1227U, + 0xf122d8830ee03f1bU, 0xf0e7f3bcf1faee0bU, 0xbd2543eed605f3cdU, 0xeb2a0f261d15210eU, + 0xe9e408c505c31af5U, 0xa06d3f65301d5eeU, 0xe6e42cd50a00fd1aU, 0x33d526f6f9c70e1cU, + 0xdfea15ed04e70f4cU, 0x12e9d1dcf7c2de7fU, 0x2ddfefecf1f0ead3U, 0xbbd5db01e6e4d900U, + 0x1c21fdf405ea0c32U, 0xc70af6e5de0e1a2eU, 0xd3fc2c53ebcee8e5U, 0x510bf306e1fc24efU, + 0x3afb9d22f7285328U, 0x16a3020ef5214424U, 0x55e8fcf9064b07f6U, 0xdcf7f20c571af718U, + 0xeb04cfebd2d6d8f5U, 0xe112efd20eeb2b09U, 0x20f3e1dcf6ec461fU, 0xdf13d041c5394034U, + 0x20b5191afb2a1cbeU, 0x27ef2e2f202108e4U, 0xe01670d5f0fe07f3U, 0xea32de0f1c0a3bcdU, + 0xe30d2b0bfc0e0877U, 0x2c2fb2613ee3681U, 0xc3610e21fe4f702U, 0x4b19ac29ea1eddc2U, + 0x8ea291de105dcf1U, 0xd929ce56fa12dfa4U, 0xfed91e05eab9bf2cU, 0xdff09d81b19afd07U, + 0x9de400f7882fe22bU, 0x2ced18c439f609ffU, 0x30211fef349a0d1U, 0x6c1ab1f30b19531eU, + 0x39301bd6cab4ca84U, 0x242d09ef17a6dac2U, 0x1ae41fac2657e3b8U, 0xf3ffff90a1b3afbU, + 0xa5fcf014e771bd3eU, 0xd614c7274be1de33U, 0x6b11dbd41c4fc744U, 0x52c169cf13e7f03cU, + 0x1e25e5f9ea0cecffU, 0xdcf70a0e04bc1bf3U, 0xd34c100e34feb7d2U, 0xeb19d3d13333291fU, + 0x341346c10223eac9U, 0xfef3051cee1c2504U, 0xd32881b5f412d336U, 0x21010cca0bf1ea0fU, + 0xefcdbef901270b40U, 0xe4e6c7f6f5f3b779U, 0xf3071b2abdec0f92U, 0x10fa11232608e802U, + 0xcfc6c468db0f86cbU, 0xc535d5dc2d6be5f2U, 0xce5fcd9a0f7e8feU, 0xee9ffd2a083306e4U, + 0x1c2ebef40e1c5c0eU, 0xde2915c5044436e1U, 0x1d2b23dc1e071bcfU, 0xffffffe80000036dU, + 0x82400001247U, 0xfffff2b500000fd2U, 0x168d00001a53U, 0x92800001c44U, + 0x2600000006fU, 0x1c32ffffe6b0U, 0xfffffd8e000011bbU, 0x184afffffc5aU, + 0xffffff29000008a2U, 0xfffff73c000017f7U, 0x19cb000019fdU, 0x1ca100001bc0U, + 0xfffffe35ffffc817U, 0xfffff2cdfffffb9fU, 0x70cfffff226U, 0x16ce00001cd9U, + 0xfffff15efffffea1U, 0xfffff80200000f6eU, 0x4e4ffffebc6U, 0xcc9fffff158U, + 0x7ba00000504U, 0xc42fffff728U, 0xd29ffffe09aU, 0xfffffd7effffde7cU, + 0xffffed6100001b3aU, 0xffffff0e000013efU, 0xb0400001cdcU, 0xfb00000f64U, + 0x8dbfffff702U, 0xffffdd0700000470U, 0x2218fffff758U, 0x22a00000872U, + 0xffffe34300001908U, 0xffffed6500001918U, 0xffffea02fffff2eaU, 0xffffec60ffffe9daU, + 0x12feffffc57eU, 0x374fffffd46U, 0x521ffffcc97U, 0xadfffffef6fU, + 0x11600001a38U, 0x1cddffffefecU, 0xfffff2670000030dU, 0x1a8100000197U, + 0x813ffffd6cdU, 0xfffffe59ffffbf98U, 0xffffef6e0000295dU, 0x1a2ffffd70cU, + 0x1b250000229eU, 0xffffec53ffffda0fU, 0x14dfffff630U, 0xac7fffffd4eU, + 0xfffff032fffffbfdU, 0xfffff66a00001965U, 0xffffe66dfffffb9eU, 0x9f90000153cU, + 0xc5500000e9cU, 0x9d8000023c2U, 0xffffd38fffffc7beU, 0x454fffff5acU, + 0xfffff1a600000dcbU, 0x2536ffffff3bU, 0x23b0000140fU, 0x7f17317fb81f6e66U, + 0xa1367f4bfa707f81U, 0x85817f35107f7f4eU, 0x81a8818de08c7f7fU, 0x7f818100810c81a5U, + 0x7f815b81bdb18a81U, 0x8181810c7bd24c5eU, 0xc84a133ac37fc5daU, 0x86c812bc3c7fdb41U, + 0xf27f44e6a37f4ff4U, 0x7fca2c77817f01d5U, 0x81f781c43e15be7fU, 0xbe5037d2816940b0U, + 0x687f557f81af5e82U, 0xe32149816e134399U, 0x8b6249d33dcd7f27U, 0x19f33a1cdbec3b7fU, + 0xef2c1400186d69d9U, 0xa8b348da1e683821U, 0xde9fa7a487c46023U, 0x63fad271033894d8U, + 0x2ac830a204bcc2a6U, 0xe9c8cff540ae417fU, 0xc32071f776bf9feU, 0xe02eea0a5020df07U, + 0x74ba5dd481edcU, 0x48db062ab306fa17U, 0xdbdca3d52ac6d67bU, 0x932ff809c06c09dfU, + 0x6a63e461b5902cb9U, 0x9b065acd5e201be1U, 0xba1312a911e6f0c3U, 0x1dfd0d1fef04457aU, + 0xe13cc7091c735addU, 0x81b7298112562317U, 0x19d2d1c681d82511U, 0x31e9f82ee838900cU, + 0x11b1628dedeabab6U, 0xcabbf5f228b27547U, 0xfc3210395575f115U, 0x27124e142f4e3dfU, + 0xe5ca54b9ec290e41U, 0x4ca5cc19c2f80107U, 0xcf9fd7b5aabfb069U, 0x815df6fa247f069eU, + 0x2c51812ec48113a0U, 0x81f54ce67f0217efU, 0x9115f4817a0f01c5U, 0xcf5311efc004578U, + 0xf10cca3b2e6655f2U, 0x93af41ad0b090b22U, 0x18c5ac0ce2c20308U, 0x3fe0f36cfe05bffbU, + 0x5a23a9ffe1e98f9U, 0xf6d420fad7a016c9U, 0xee3701367b040d09U, 0x7a40ebd72bddb1b1U, + 0xdc84730b41312250U, 0x2b0c517f1f0e2d9U, 0xd781b28389108160U, 0xae7f34584b663ca0U, + 0x4b25930ba4af0c97U, 0xc3fe7f0f5d001bc8U, 0x81e8b79f3320df05U, 0xc9011202fb4967U, + 0xf4c7e6d63b2242f8U, 0xd1c96fbdcd34e2edU, 0x1bbbb3ec4e07fbeaU, 0x1acaf05ef5fbc11cU, + 0x1ac048afbf2cafccU, 0xed1f28fdc681004eU, 0xddffeb342be40e09U, 0x7f7f99d2adcf9b90U, + 0x22ab7ffb79291f6bU, 0xf2e0d92a00aa07ffU, 0xb2e1d89a8133aa3eU, 0xa9371b7628647f81U, + 0x482c8519b9c3fef0U, 0xacb53e2d18caececU, 0xc32b83963c57e905U, 0xf9950300ecec4c2eU, + 0xe6aeeec96544ff10U, 0xa5194ddf8132e3caU, 0x9818f15022cffd2U, 0xefe1ed7f14860527U, + 0x1fa73a92e10aa7fbU, 0xe8352e0fe69d0753U, 0xeeeb4726761813fcU, 0x1a4081e993b1c5aaU, + 0x37c3093e5642f97fU, 0xcc2df721c8e740d2U, 0xc02c02aad273a526U, 0xc73bfe724f2e49b4U, + 0xf921b62ed90aecedU, 0xb199061cf981e82bU, 0xbb3a81c7271e93dfU, 0x19902e640f9d6d2U, + 0xdda90dba7f56f3f0U, 0xb96c424f8a6cf59dU, 0xf5bd88173d120ed7U, 0x15c4e64f3106fef9U, + 0x24f633b9c40ecd00U, 0xea2e2d0bb0d1c24fU, 0x1ed025217ff3fee2U, 0xf01bb81c8182eb81U, + 0x401c1e67515c0346U, 0xe1fbf61fe4bc38bcU, 0xcc492081277f4f31U, 0x833704496859230aU, + 0xc132d02ef427a643U, 0xda9fda0edc87c940U, 0xca17bdd21fe5a5b3U, 0xf381deee13fea6f6U, + 0xd7812581057f0700U, 0xf34d1765a029f781U, 0xfed9d22013eafff1U, 0xe603f64249b8ead0U, + 0xb0245ee9b47fc0bU, 0x1d4f2f0ae99dbf43U, 0x1cda32d0ced0f9f9U, 0xaafcc43cc58c1b9bU, + 0x5400de7e1835eb38U, 0xcb54f60dcca344d5U, 0xb25331d71266501fU, 0xd31ccb60353d1dc5U, + 0x82351de6ec03815cU, 0xeb91d1f399d3d17fU, 0xffd7ffd028a7c681U, 0xd494e90136ba81caU, + 0xb8d5fed2e74cfc2aU, 0xacf3d21ca638e0a1U, 0xadfdf34f30a2efeeU, 0xefdcd3681c8109c4U, + 0xdbf05ec4d42d3722U, 0x2015002cb59bbf0fU, 0x65c742c4891b37efU, 0x964eae50e6aa4cb2U, + 0x7d47077ecb0fb337U, 0xb7491b48a9a847f1U, 0xabcf25b4f516592cU, 0xdb0b9a7f0d232da3U, + 0xce3a5c03e1aaaa5eU, 0xad81c9cbe724b55aU, 0xccacffe72881c69dU, 0x85da81f37f8188c9U, + 0x8104ec3ede483149U, 0xa8efee28ad22a8b8U, 0xc6f3da7f5481e3bbU, 0x4f2bf7930aa4c81U, + 0xd2d27fe1817f7f45U, 0xe8ec2e7f81da81e0U, 0x7f817f8190eb7f81U, 0xd73a8f7f1d927fccU, + 0x7f7bcf7f810e8121U, 0xa87f7f7fefb27f81U, 0xdf8a21b3bf1f5339U, 0x14c781651fdd2ad7U, + 0x811527ebea909f7fU, 0x9eeb8abe834b812eU, 0xb981e6a67fcef191U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0xe8f900e7d646fb16U, + 0x43f647f90132a8f7U, 0xcbce1f52c18d7aaU, 0x1dd0072313cbe90eU, 0x110d0ace383f4f04U, + 0xd0d3d217cb3ee317U, 0xadf7edfad11013e0U, 0xe3d6fbcfe7cb3bcdU, 0xf307edbdf4b5eb61U, + 0xf71ce31021f80e0eU, 0x2f9113bde223115U, 0x302af6fe5afa0fc8U, 0x937dc13de37e1fbU, + 0x81e30b07f9c611efU, 0xe10e24b135f9f3U, 0xfbb0f2faeb2252e9U, 0x381413e8182cd8bbU, + 0x24e4480d45c75e6aU, 0x2508f00f334d0de8U, 0xe2ffe22e81f921e1U, 0xfeaca1069b7b133aU, + 0x72d1f6232d20759dU, 0x3338f0f837230e02U, 0x242a293f2602f5d0U, 0x333c5fd2b3a704eU, + 0x2afde9d058d0f6f3U, 0xc7ce10f360f50bacU, 0x28e2cb04dbfe0490U, 0x2d06f82aedfeb319U, + 0xdbcc242ad21b24d1U, 0x1be73de537332685U, 0x7e6f051c1222bccU, 0xf4f2e11fd6cbe637U, + 0xbad5c1bd38ee2438U, 0xea16228be245a245U, 0xe67f0eefd6b80ac5U, 0xb51dc3de0013c709U, + 0xe22a083f241ebf01U, 0xbfc0effc2415ea40U, 0x5f25f443160111e5U, 0x8b181f5432263bU, + 0xc3fe26b45c462707U, 0x5f440ff408fb2903U, 0xe7fe381acd1f0bc2U, 0x5503625c0d3f639U, + 0x6244d2d584e2984U, 0xca1ff7f33ff2b9cfU, 0x3b601c50c99d19f8U, 0x13332e0e27b601bcU, + 0x140df2ba22f1542bU, 0xf3dfe510db4bf7beU, 0xc371bee16afe1a8U, 0xfe9abe52dd1c022aU, + 0x55c350daf2cb4bccU, 0xd8e7fea72ee12e0bU, 0xeffa202512e1c505U, 0xfdcaf3e81c4432edU, + 0x25d239e0e7210decU, 0xe43ff4061ad5cb94U, 0x1617d003e80454cbU, 0xf01c0bdd0b16cb21U, + 0x40fc5909e51a60bfU, 0xf1fe7be32fb9c981U, 0xec08cd49e84623e0U, 0xae19031f17c4db19U, + 0xfd142231d6fb1ddcU, 0x2618191f3517c0edU, 0xbaf30363e3c94e09U, 0xce08a3a9f6f705e7U, + 0xb720ce160eeb5910U, 0x2208dbf5f0100ffeU, 0x2a90013f23eaf69cU, 0xbf1ffbd021c9d5f0U, + 0xf7064bf2d333f211U, 0xf4560b2f2cdddcd6U, 0x2ec4040ad01cb5e4U, 0xfd2109db16ffd3eeU, + 0x142e2eb201fbdbf7U, 0xd9f80f0e110281e4U, 0x2d2b3b1f0708e833U, 0xdc8dbc20dc91bcaU, + 0x77021d18f1212717U, 0xfdedea00d421ed44U, 0x52dad2d0d028f23cU, 0xd710fdc1b73dbcfcU, + 0xcaf5d02ffccf17e9U, 0xf9f933f02d4b1c09U, 0x44d829aabbdf0585U, 0xdd0cfa28e8fbc40fU, + 0x47b50c1fd5180cfbU, 0x29f55002d1014b06U, 0x13e922231281e3f2U, 0x2314e7e1265405fdU, + 0xf49865fafeede136U, 0x3ee4350ff633ee1eU, 0x2ef80fecf437fc19U, 0xeb070a1cabf1b93dU, + 0xfabdbf6813097dd2U, 0x2ceedf3dd8efc1c1U, 0x231a4ce0cbf8f7cdU, 0xffc10df6e1ccffc2U, + 0xe90448df57ccc10eU, 0x54dfee09cd42981aU, 0xcb04e6b50f5a19c1U, 0xb4fcf9bd51425943U, + 0x8155ca1cbe5238a8U, 0xa0912e21d92f22f0U, 0xafa1be17f3d94c04U, 0xffa36e8f5cd134eU, + 0x27eb25df5ca3ec50U, 0x6d9e25efc032dc2U, 0xebd2beec5d6ed558U, 0xf9c0c0d9d23a221cU, + 0x29bbabfce1bfd1f6U, 0xdd3cfeebf3f5f74cU, 0xd4c4cca6c3e6e81dU, 0xb80abbefc632e9b5U, + 0x1b3e18e6dfd0ca3eU, 0xae8fbb5fc46e80aU, 0xdc00dfb2cb0322e7U, 0x5a1edc9fc7c13011U, + 0x1cd7b8e638ebf903U, 0x2c04e4a8ee5ffceaU, 0x20a93334fffd465dU, 0x3d2dc1ee2655a5e9U, + 0x633102ac93b52e2U, 0x280add3ae9d4c5ecU, 0xbdb337fd423c4beU, 0xefc1f1123e8dbc5U, + 0xc3d0e8ece6ad3d2aU, 0xeed437c2162213deU, 0xed66ffe6fe0502dbU, 0x34c9d811fc3c0bf0U, + 0x3208f6effdee18beU, 0x18eef1e67fabf5faU, 0xc0fff608d9d0cccbU, 0xdaf6fa1020c84bd9U, + 0x244be3f2db00ecc3U, 0xe4ebf6022ee7d2dbU, 0xd915def5125245a9U, 0x2f16131cff2cf6e0U, + 0x37e84452e50a19f0U, 0x3bcf13c118fce6c6U, 0x1ce9c63fd01a10efU, 0xdc033e05c641d3c2U, + 0x4d7d5e5f7573fcdU, 0x4b32cc1fed36d5f7U, 0x1215291c134ab9c6U, 0x4159cfb3bfe1816U, + 0x2a2deaf535c5270fU, 0x7f365918eefef02cU, 0xc3d13dc08f732b4U, 0xbfcb1e43431e21f4U, + 0xf110c4e1013441fbU, 0xca41731b70762feU, 0xf4ccae31f82c43ddU, 0xa93e3a1019240bebU, + 0xdb17d42bd8e20f21U, 0xcb3d0cfdd761f69eU, 0xe2d9061b2cede612U, 0x31ff4ee33afdfb1dU, + 0x7fb307c9d83752cfU, 0xc13bef955200ad8U, 0x1612cfe6dfc4b30dU, 0xfaf63209fc16fce8U, + 0x2028e814bb015cdcU, 0xd02e5ccbf070f51U, 0xf2cf681a28dae6b5U, 0x180f4dfae61badc9U, + 0xf34712ca2d29b84bU, 0xd30dc11eb843fbccU, 0x2816a6003c151709U, 0xae5c644f42df6a3U, + 0x7f6001dc426d102U, 0xc308285f35bd35daU, 0xe6f0dbfad6d434f3U, 0x3bab2b4b6a01370bU, + 0xce61e47fec6334dU, 0xe9e211e543b83511U, 0x10102307102ad3e5U, 0xb5bf091518d00330U, + 0xe3f275e28d11aa2U, 0xac1a68d01fa271fU, 0xe10b5fe8f334f22bU, 0xe4f7eee927f91bc0U, + 0xdd5ce51607d612c9U, 0xcc4667190206b416U, 0x27dac8e6a5bc7dc5U, 0x321c15ecff570f8fU, + 0x35e24919042ec930U, 0x41e12dc225e9c4f5U, 0x1204f6f286244681U, 0xfab8191d08af190bU, + 0xeae8bc45ebea3a5aU, 0x19f2c9d00d38da34U, 0xe82e32f9f318e2feU, 0xd681d90fc033da14U, + 0xf2ff484826d7f3bfU, 0x370bf90a56d10d4dU, 0x4a7af8370f26d7ceU, 0xffba3056200d2518U, + 0xf8fa17ff193c1fdbU, 0x5f31e44619be09b3U, 0xbdd5cfeff4e7010aU, 0xfd451c28f247e502U, + 0x27fb4724052b05b4U, 0xef240a1c2a35fbfcU, 0x6041d007cbe4ebbcU, 0x263d1dcd2ae9050eU, + 0x3ee409e41ad5ca5dU, 0x3af0f9e0e7312713U, 0x46ffe2f80daaa4c5U, 0xe1e7bad6e44fac1aU, + 0xe60de7142bc34947U, 0xf3c9c203e50b8db0U, 0xe7fbeec6c615ae7fU, 0xcbc254f8d9f83c1fU, + 0xec1044c0f0f1eef2U, 0x3a071511e300db2dU, 0x13bd2be0c50b07bbU, 0xffc9effe132324c5U, + 0x6ed34f2ede91c02U, 0xff08cbd6e5faa5e3U, 0x170909b5ff2bfe6cU, 0x6cdbd3553f33830U, + 0x4ad105ec2d25b0e7U, 0xfddf853ce4d32d1bU, 0x38423f2c2b6212f9U, 0xc816c7dce814d2fcU, + 0xef1c53021608ebb4U, 0x7f3dec8f7274a70U, 0x192b1af70afb12bbU, 0xa31fc209e800812aU, + 0xc5a9359fc0f054c7U, 0x14913808de3e084bU, 0x61c1f3b2714c41eU, 0xfeb4633e3ce3fdc3U, + 0x4cd849680c193201U, 0x1f2455bd35311a1eU, 0x1504df41b8f04a34U, 0xa9d8291bc9ceca2eU, + 0xc8d913431d04fbcdU, 0xfb4d0223cfc6c3c4U, 0x9e2414ccb00ffc4U, 0xdf0d260332c01accU, + 0xda0e1f1f25bd3c27U, 0x1517ff2de1f2ace4U, 0xf3ebe8b20f2e15ebU, 0xa4f1e6f4fa2a31e0U, + 0x8103d513ce4f1c1fU, 0xec051614e35417dfU, 0xf4c1b7e0f3d1464aU, 0x1bf938ff2334ebfaU, + 0x50e1f023e7c430fdU, 0x1cb2032d210cdc01U, 0x2dfcd8e52856fe08U, 0x69ca4608e23cf6ecU, + 0xd602fd29634e2029U, 0x1db0a032f2e418e1U, 0xbc473767291dc83bU, 0x4410aee91b2b41e7U, + 0x2baa250681c207f4U, 0x9f2b2caaebfd401cU, 0x85c368fc0936f490U, 0xe82a9fd63001fd13U, + 0xc8d60bdae95bc720U, 0x24fef913df1027edU, 0xbe1ba1d67907f63fU, 0xd4d0b000c314aa0dU, + 0x8f01ff04c70b460cU, 0xe8e2d2faf9573c4eU, 0x2012d63f47641bc2U, 0xe3e20d7c642a78d1U, + 0xf4d29fac717ef2aU, 0x9315118e7b5039bU, 0x1ff2ff0ef21d2d1cU, 0x1ddfda12cec433c9U, + 0xa1f6e1ddb803e1d2U, 0x24413342c9064c1U, 0xd7d56b35a6d233d1U, 0xc9015d5b6443dcb9U, + 0x430b06c135cf29efU, 0x8fbc47f91342b681U, 0xf64182a971b9de0eU, 0x2b79e8330dd224daU, + 0x8205cf9d8850e4bU, 0x4128360db0c6ed5cU, 0x4f39989cd58c4d0U, 0xd11481cf1a00efd8U, + 0x31cdefe142a1416U, 0xf12710ffccf8f1d8U, 0xb4d9e2daf7d702beU, 0x272afecec4dafb56U, + 0xd20a1f0fe7fa2525U, 0xe8f41ccff9fe25deU, 0x3c37de2fe41b1b31U, 0x180454123746c6dcU, + 0x102228db0d115f05U, 0xe30614e2e7e10596U, 0xed4e0d8b7e6f0caU, 0x273d0d02f1fb16e6U, + 0x5709c72cce16d3e8U, 0xcc210e5418c0f04cU, 0x1c2811042519dcefU, 0x4a4b7b353bd25cfaU, + 0xdeb6bbe1d6dd3c3bU, 0x7fd719fbe31d0bf6U, 0x56e0413f0ee8dbd8U, 0x26f0041f2d2d0bfbU, + 0x5717e919643073f4U, 0x304a4d4a794ab347U, 0xb6f61c15fb1bf6ceU, 0x1b033becfdb429b1U, + 0x13e6faf6cec71608U, 0x2b41e51b2116e938U, 0xd044e84be42623e3U, 0x4adfc6baadf6c9ffU, + 0xa6283539b9161e6dU, 0x9fe6fb0b89b910e0U, 0xf00d197f3e71dddbU, 0xb558e181debed188U, + 0xb012adf18e2de906U, 0x6331c07e9ec005bU, 0xdd1e7aea3722012aU, 0xf5ead4d1b7083600U, + 0x420c4948e9cd5c08U, 0xfbcd3d042b000226U, 0x1c2dd7fad117f81dU, 0xa1f23fd48fe17dcU, + 0x5efc5f6c01737b1U, 0x2cc8b6215af7fcf0U, 0xf13724cf150fe7e3U, 0xa33decabed32c0bU, + 0x54f0b517f5ec1afcU, 0xd62f3fb5e124c340U, 0xf8fe132fbd24dd00U, 0xb828dfeec4ae48e0U, + 0xe741c9ecdbcbfab2U, 0x2d22f9dcf193bae6U, 0x2dedf8662dc3f6efU, 0xfdede2291b582cefU, + 0xea5459dc249b73e4U, 0xc1af85cece38112U, 0xd6c72e480d0f0ef0U, 0xdedbc71c20f7f801U, + 0xb8fb0dc6eb1ca7d2U, 0xfce5e9dfd702e6dfU, 0xf258e92b20f10bf8U, 0x2ec41fc02f9073bU, + 0x1d2521d709f527deU, 0x3f15d2211f279d25U, 0xf91bd3d405d6f1e9U, 0x263eda4b04f9d638U, + 0xe1fd04c8d0cb1625U, 0xf72723ff7f32d2d4U, 0xfc3fff44f1f4a9cbU, 0x6e8c052ef051d0eU, + 0x151425cc31fadaU, 0xcee5f5d12aef1233U, 0x43224152d427cee6U, 0xe51bece90f0935bdU, + 0xf509dfef0b40d2b9U, 0x1e57e6d2f3f5c116U, 0xe232eee3ea122aacU, 0x4e1e041cfce5ea24U, + 0x3be23f0e2a203eebU, 0x1edff128389fd9e0U, 0x20eaba33d4d6eed1U, 0xf9aee44f72e23f9U, + 0x91ba18e4b3b5fcf1U, 0x23cd0c30f3b30da6U, 0x2be72207fd1dad9aU, 0xc90e7d0ba93756ffU, + 0x5f37fcf7192fe3deU, 0x1ccfe0884da46c1eU, 0xc608568a35e91e3eU, 0xe1292481f752f3acU, + 0xf4f8033ebb5f12b8U, 0xfcc6ffb4fafa313bU, 0xd6911ed5e748efedU, 0x10ce3a083bc6d043U, + 0x1b522d2115182201U, 0x73896bd0102fad1U, 0x38d7e31fc61dde25U, 0x3e513509cf0efef9U, + 0xcdcb2acbec8eeb71U, 0xf021ebda7f06f8dcU, 0x1d74fbd79cb3f897U, 0xdeed1e023f3f5ecU, + 0x3a5a0ffb14e5efdbU, 0x24d3029f4918eb0dU, 0x4128fbfbef34e947U, 0xa3f200e900f265bcU, + 0x37d329c30413dcb2U, 0x635270b5ac6ace4U, 0xda130350b1ee5b86U, 0x1521dabd1b0232e2U, + 0xac04b4aea4ff5c8U, 0xc31511b83feee924U, 0x15e11b350406fb40U, 0x1a7fd04afbf74dcfU, + 0xa23f1c5284812c6U, 0x77e2bdc9bbf3113eU, 0xc3345ac7e8d9ffa0U, 0xf8ea335e2b49556bU, + 0xbfd13bd1709f60bU, 0x1c283fd914d93a05U, 0xff2217d5da11341eU, 0x18d83c5bd629f036U, + 0xdbcff2f2481401cbU, 0x6bfdc92ea9ddfa23U, 0xed02f5c828f7bfddU, 0xadbe1ccdbbb9caf1U, + 0x1120efea3205cc18U, 0x32f62bd1a1374236U, 0x2c5c221918ef2ef1U, 0xcde200b1ffe0a4d3U, + 0xe1b4e359fdd1f4fU, 0xb14afa122905e226U, 0x1bc80c0304e928b0U, 0xe94be5f3e9fe071dU, + 0x82e0b84603ff772bU, 0xb18581fbeffac0e2U, 0x3627c1feca4df5faU, 0x12ad29f2816072dU, + 0x190cc00d2f392dfaU, 0x9edccda12e5a3cfU, 0x10fdc8faf5ec03f6U, 0x29143b5ff6500419U, + 0x2dd90333cd18ef03U, 0xd0b707fa2b0b01daU, 0xe63addd6d122cdbaU, 0xd4c410a8ff1dee1aU, + 0xaf3391813f6d101U, 0xffe746052bc3dfe7U, 0x1dd3ec3a1f150a12U, 0x81e8d8dee20bed1fU, + 0xc20bf702103b0220U, 0xc3fbbdf71cf4c5eeU, 0xf2e7e435161e0101U, 0x30ffe9c343edfc0dU, + 0xe71b0f00f811f603U, 0xed2526143021f0dbU, 0x2b2c1cce2dcd1fbeU, 0x170f0d0be80ee7fbU, + 0xeed90dd6061eea18U, 0x1f272f5420070df6U, 0xf009094e182513d4U, 0x6304476b00fc27f5U, + 0x8108169e41f7a722U, 0x11acd300cb461d25U, 0xb44f35fb56011c07U, 0x15e024f320eb5041U, + 0x677cf028301e0c1aU, 0xfc474ada280b0517U, 0xdb4e04e2dc0d00fbU, 0x462822109707eac9U, + 0x20bdef2e26af2c3cU, 0x1bbfc2d2c59de439U, 0xb11a63733323c2faU, 0xf4b125158a81e153U, + 0xdb43e6102a0be931U, 0xeef8d6c926ef370cU, 0xd1cbe52fefe7501fU, 0x8bbdd69a09d5afeeU, + 0xfff41b5693f9d8c6U, 0xff1cfef0f8b1e6b1U, 0xc0fcc74a14e2f704U, 0x8cfec614d9b5e4dfU, + 0x990df320010422f5U, 0xaad2810d01ee9511U, 0x3eb8fc2b3707b013U, 0xa10cc5a52d2a29ccU, + 0xfa45e7d1db2cd3e2U, 0xa23c63cf1b14e7d6U, 0xe40ee328f102e11bU, 0x2b0f17260828c605U, + 0xeedf25c6239e2c03U, 0xf6100c46eb23c747U, 0x151c1ad22300f9c6U, 0x70041be5af1c9cdU, + 0x3d041121a7f11034U, 0x2416f3e73e58f5f3U, 0x143cc40a0ef1dd13U, 0xe735b02ba0ca03f8U, + 0xfb2ae40bdb11e7c3U, 0x9fb8f9bc52fee9d1U, 0x1f1c46670b3d084fU, 0xc234271aab7e1febU, + 0xef4a20b996e8291fU, 0x2fe13724cdd4deU, 0x16f01714ae19f1efU, 0x30f17247e36b9c12U, + 0x1081efb9eb290a09U, 0x2007f245340b2fc9U, 0x4ff5da4d8fc13743U, 0xbbe70340e0b71effU, + 0x827bd74f27f80a1cU, 0xdf0a30ae58dd0272U, 0xbb4b0713201e2836U, 0x84b19381f7c691e4U, + 0xb1c846e0ccdd8487U, 0x17dc084cb0f22d6aU, 0x466d33687a1691a0U, 0xc25de186232e08d6U, + 0x8910093662f95266U, 0x6bd0ec2ac5b042edU, 0xf01ba9ea4a882aeU, 0xce3600dfcceb4d02U, + 0x4d59faf60b25f9ccU, 0x14163542003b473dU, 0x19570b16edbd2d04U, 0xeff9f0f0eaf71127U, + 0x20c0f30cd63c071dU, 0xd44e0f90e33b94bU, 0xf20ff3e804dce939U, 0x818eecfff7b8db42U, + 0xef0184d09c723ebU, 0xdc0725cafed3170fU, 0x2652ff29fb07de27U, 0x42c82a76046495fcU, + 0x14eae1e1f90f17e5U, 0xef21e43a12a510ecU, 0xe0e8f316e4b4d9cbU, 0xed5c4e1fe90a18f7U, + 0xf7d633061afd18deU, 0x161541f6fe1b20ebU, 0x251ed6f128facef8U, 0xf6411902d00116efU, + 0xd33601e61d100b14U, 0x8c1ddd5e4261b1aU, 0xf4f624e038d5bfbdU, 0x1e0122faff13377fU, + 0xf50f2cef23fef6f9U, 0xf32a3007f0e43dfcU, 0x160dc9f0d7e6fd26U, 0x3bf8173bd51cf3caU, + 0xe0d0ced909f2e2c3U, 0x2840db2ef02639fdU, 0xef65e9222bd0f2dbU, 0xe6f323d1b3ede917U, + 0x170ad50a06e225f4U, 0x461603a8d154e237U, 0xfe0f261a08ad2319U, 0xd4b52eac3eb5f829U, + 0x3c1111d2f5da3112U, 0xcb33f9213c09ffdbU, 0x7c0b0cb3f715071eU, 0x1ee6ef0d1b2806f4U, + 0xdd8f750f3ea513fU, 0x10aa63b664d0c55fU, 0x32a1450be92e852U, 0x9801e97ffa4ddd08U, + 0x1a63f3ccb6dc0818U, 0xddf31cfdc6e8e9fcU, 0xfdd39a170ae0a11dU, 0xd90739f5c9e1001cU, + 0xe2e762d132a35802U, 0xbe41ffbbfff122b5U, 0x3706f7301afd56e3U, 0xd7db20fdd2300a4aU, + 0x5bdfbafa0c5972a8U, 0xc114ca5bd8104efaU, 0xd2f8f44f31e55012U, 0xe3b7eb0795ef2930U, + 0x5051dca71612e6d7U, 0xd181f92eab1a1227U, 0x1005a6c0cbee4988U, 0xf7931dbabe3dc36U, + 0xf4d12bf1c6fa15c6U, 0x970b39eefe1b121cU, 0x160c2b3507261434U, 0xbd73cdb0e10efd2bU, + 0x85c2edba39d4bca2U, 0xc37f3d66ee2d890U, 0xc9f0dcc646253e19U, 0x4e6f118d9f6fb2fU, + 0x1805e2262717f9c4U, 0x2af0bfc2995429f0U, 0x304cb156c5f02b6U, 0xf7cf4e0104eec2c3U, + 0x13b610ef1ba0b9cdU, 0xe2f6780a0fdde624U, 0xf036a23249bc20c6U, 0xf0f6ccf0c4502f00U, + 0xfbb513011d5e30e5U, 0x8f21c28cec230adU, 0xc4fe0b45f60151e8U, 0x810fdc32d352b6dcU, + 0xc80a032ceadce22fU, 0xf2bf712d09d4fd17U, 0xb42d69c1eb0f3a18U, 0xe13e09d7c33cd1d4U, + 0x4f0ddf0e392e301dU, 0x254b0ef4ce55eb15U, 0xf2004b505217f81eU, 0xf00483cb34f650c9U, + 0x52d91011fecebedU, 0x373729eef17d01e6U, 0xfd0ff5e8f301ffbeU, 0x21a51c50ee371a5eU, + 0x14fa09bf26edf609U, 0xfac9064c2ce7337fU, 0xe9f8a40319f1e1ceU, 0x9d3005e5ab1bf47cU, + 0xb407c1bd3dfc38efU, 0x1e2338eefbdbe0deU, 0xe61318290efd160fU, 0xc212f0816401203U, + 0x3ce82be813de4defU, 0xe6edbf1d1bfdfea5U, 0xc9e10d97fa0333ecU, 0xd310280c34c64ef7U, + 0x1f02d6dc37262022U, 0x2208d8d54db31901U, 0xdd415429f1cde721U, 0x7fe3fdf3e3eac8dfU, + 0xfb2e16d7d3f70f00U, 0xda06f4d8fc17abcdU, 0xdaece6e8d215ff43U, 0xf81fed2afee4d8edU, + 0xd0d1ff590515f0ebU, 0xe121e9ea22c11c1fU, 0x26c1ebe9f22a14d3U, 0x34d1ca38020ab629U, + 0xd1e615e814f506f0U, 0xede046ec81f626e4U, 0x924100216ec2214U, 0x2a204604ea16fafcU, + 0xf5c35fd39ebe7cfU, 0xff3f17ecfffeb8bcU, 0x2bc9d4de2c23c924U, 0xf7f222f4be0efc15U, + 0xcf05090bddf203bfU, 0xf6c1f5dbecf82bf6U, 0xcc0b2919f50f120dU, 0xbae10fd6fd1d24ecU, + 0xef27fcd1271edf2eU, 0x442800be0fdef4c7U, 0xe9c0e90ae1d229e3U, 0x811fee1d90936e1U, + 0xec39ea4d7feecdd3U, 0x1c0203c7fc27ff28U, 0x13e7d2ffe3104d37U, 0xff2406a1d6d4c2e9U, + 0xc8eaded0f700f709U, 0xe6e9202cc411f0e6U, 0xa04f3cb1ef05bfcU, 0xb4fcf34a6a07fc4eU, + 0x4efdffe6f40b26f7U, 0xfdd0f823eefd16b8U, 0xdceebdf636e3d616U, 0xddfbdd29f002d003U, + 0xee4fd1abfddcd13cU, 0xde31141e9424b2cU, 0xe7326d1b2a0e19e9U, 0x23a7f20bcff5c2fdU, + 0xaba5e5f201811911U, 0x1bcc34e705b12eaeU, 0x2bd4fbf5e7d34c0aU, 0xecbcd1edbaead5f3U, + 0x53910056eb9af2eU, 0x1aa0c1171af41eaeU, 0xbb5822ab0d02ffdbU, 0x19bf150df6ecfdccU, + 0x369f00f1281b0cc1U, 0xd4e00094e01b07e0U, 0xdac16322d9432d44U, 0xf3d0f134cec33b3aU, + 0xd44fbaec0a301401U, 0xfdde9d80cefefccU, 0xd6e3fef9db062301U, 0xf32e3ce53cb2cdb3U, + 0xe3ee4b07cabc9d0eU, 0xe0112abc130b382aU, 0xb9f1f57421a1e6e4U, 0xfec937e65b4b1415U, + 0x32f9e8f45bec67d4U, 0xd7682110450f0107U, 0xee7e176dfd5d042U, 0x20f07f0fe8f312a5U, + 0xa4fc11c40add5U, 0x2950bfe1dd370bd2U, 0xf814694aed03b91bU, 0xf21ce406ee0fe80bU, + 0xf30f01cf12dd38d2U, 0x23423ad3c4c7b943U, 0xc3583ef01ff841daU, 0xea47350ae98c0201U, + 0x6410cecf3fd12f7U, 0x4414d5d1160811e3U, 0xc60a23f30def81fbU, 0x191a01eb2df711efU, + 0xeef2cca1d9045d21U, 0x14d950effd04b7f1U, 0xefdef90111192308U, 0xef3540f310b4f503U, + 0x1c07c5ec241915e1U, 0x15f7f831dc76c730U, 0x260701fa5020bc22U, 0x38e3093cfb06e3e5U, + 0xebe5b621e3a6eb1aU, 0xe6be04f4e001fb3cU, 0xe50e5dbc3b2fd2ddU, 0xe3f3f385aa1a01fdU, + 0xd412b9f517d7efa5U, 0xe7fb41ff1c4806f7U, 0x23ba080cecc3f60bU, 0x55db0fc8f0dc5819U, + 0xf1accefbf2e0660U, 0xc6e8069dce42beceU, 0xe6b447a90713284fU, 0xb5d852d7130b4865U, + 0xca1fff1b0209f4fdU, 0x32f3193a3081cd10U, 0xa3bb17f9fb264b8aU, 0x1213c6d7f3ecb25fU, + 0xf4e4f3bd00f5ee5eU, 0xdc57b13f22f33037U, 0xf92270080fe349ddU, 0xbb32c90bc25dfd0cU, + 0x247fca4207d8f204U, 0xd2eeae4e603b9f2U, 0x3b1646f33dc107fdU, 0xeae0f3e3f9fce433U, + 0xe74bd90507550f38U, 0xf4f3bd07262015ceU, 0x49e7e939c8e00155U, 0xb9ec3d43255ade48U, + 0x27d628b03d35041aU, 0xbdf174908f31406U, 0xe71900f2cfc0e2daU, 0x52cf328f7dfabf1U, + 0x25e6040cf3ba1f18U, 0x27335128e9074b27U, 0x351625d0fe2ba6d0U, 0x5a68024b52f752afU, + 0xcd20b7eb303a0e12U, 0x15d2cf2b22214824U, 0xc27f6fe529cb1115U, 0xee217486cdc4819U, + 0x536433d1f32c9e06U, 0x103b5beef3c54b53U, 0x26e24f4ae72e13f6U, 0xf308fe40fa3ab409U, + 0x1be3c4e542ebd1ddU, 0x3223b00bb2a60e1fU, 0x96fd61085d11ec0cU, 0x18e7a8c6ade60df9U, + 0xa6580fd92e35fae0U, 0x2036ec9d0bd72115U, 0xff246dfadc5611U, 0x523d2e6a26d8eb41U, + 0x39cfdccdec11aafcU, 0x47c4ea095aec56c0U, 0x36f503250bb3c2f5U, 0x53e4d208fbd92c15U, + 0x22e205bddffdf5f9U, 0xfc8d4aafae6fcedU, 0x91f644f71e22fa9eU, 0xd10adae6b11008feU, + 0x180aca1bf6fdb3f6U, 0xe9230b18cde7812bU, 0xb30b0dd04fa5223aU, 0x45dbf8daeb0be4e8U, + 0x42eaeb1c5be2400U, 0x6053e212e91a57feU, 0xd3e3dc26462b65efU, 0xe1a50dda28a3bbf5U, + 0xe5fd23eb07b6f1f1U, 0xcdda69c9fc0b0501U, 0x7db6fd5342950fe1U, 0xf0841c041fddf841U, + 0x9a5260bcfc2bfceaU, 0xaa41fa2c17432ae0U, 0xb2da222081031c2eU, 0xf543252425051c9eU, + 0xd0463bbfe262c009U, 0xd459db2eee4f01beU, 0xe80637ebd3c211b7U, 0x1724efe9f1dbdc11U, + 0xd0c0ee6fe85e5e3U, 0x13752550f3ea04cU, 0xf8293df558e834b3U, 0xe9630128d1f5fb00U, + 0x1104fd1fccf6121bU, 0xe4fdf00a2dfefae8U, 0xef320f1d02c1d11bU, 0xfde513e824ee2f03U, + 0xfaf6d0423bfe150cU, 0xf2bd08ec0aea1a1cU, 0x1926254bbbd22004U, 0x20ec344a040ff2f7U, + 0x23ff17be1dede50eU, 0xaf2d4433ef9f9fbU, 0xd10afbdbdafc1b81U, 0x5a16ec1cd5f7f530U, + 0x22c8300afe1331d3U, 0x1a014310d603191eU, 0x450dc902fe2bc809U, 0x1e740160f629640cU, + 0xe7289db41e4f060dU, 0x2ab681f8aa1b0650U, 0xdf29583101c021d5U, 0x2a230b3434256934U, + 0x345f5e0013f1a4deU, 0xe50c3b08d00c5c49U, 0xff290ee53018fd0bU, 0x20f8f807dc28b11eU, + 0x2ac4bdb92019e3d7U, 0x27c19d4caec00df8U, 0xcf195af12734ade1U, 0xf8d5fb9ef4a3e5e6U, + 0xe072c7097842f56bU, 0x3f0eccb8d90c77edU, 0xc2dae47a3219014aU, 0x4137f5007f443598U, + 0x17c6ff10ca56f83fU, 0x17dff5f447375d28U, 0xfb472bff3dce1a47U, 0xc5ba111439261a2cU, + 0x3a000f00c5eff90cU, 0xdbf938b126e64a59U, 0x8e0fe63e9efb843U, 0xf00751501bf3de0aU, + 0x21dfff0a3913e9fbU, 0x3047e631eac01346U, 0xe9d648fef0f8b7e6U, 0xd102d81929e20c1dU, + 0x271bef04173414efU, 0x2c5901d805f0181cU, 0xfd3f3b35fefa59faU, 0x6823370ed0b9af0eU, + 0x18f20afc37b510f8U, 0xffb4f2e614e93581U, 0xec142917b8c4c7dbU, 0x31feaf303e2ccc9U, + 0x541cecd2f41a56edU, 0xfe2a01b4e725c9e2U, 0xaad80e9b19e388c8U, 0xf706feba439e3a0aU, + 0xeafae2edc33df0f9U, 0xc121fe1bcaabccd3U, 0xf65426db14102e0eU, 0x46ad300525eff309U, + 0xdf2132330b2e0b18U, 0xe1f1c1ce1adcf1f9U, 0xf20ceb3731ce32b7U, 0x2a2eb712c20cba17U, + 0xf4712e056448d6d4U, 0x1f5c6bc61024b4d8U, 0x422a0454eecc1af7U, 0x22fff6247f2ce2e2U, + 0x1cf74df92c9ecee3U, 0xd8ca08f9c03b4311U, 0xe605b4a516c1bdeeU, 0xdf2e4702c3470059U, + 0xffbdd4cc172168c1U, 0x36e00a6c35ce65eaU, 0xc660c1e35f03199fU, 0xd6f1cb99bef4a523U, + 0x3df225b2ecfc4216U, 0x20d75ab7d7373eeaU, 0xcc3767e15edc053dU, 0x73ff163f122b04d4U, + 0x2bf53c2c21f22b29U, 0x39901d29dab713efU, 0x1050c4f9003423b1U, 0xf0e2d359b2efe318U, + 0x562ad06bfbbb52b2U, 0xd0fc95571545e9U, 0xd7e83e9507c3b4f1U, 0xf431d8acf8075ae5U, + 0xff040e3d72403ccU, 0xb1f90afe0fc8e6c8U, 0xbf00cb55b41c23eeU, 0x4e141320164b14e1U, + 0x3c813a6ff30ff8c4U, 0x2e2bdcc84005ebc4U, 0x68f3dd6ef2fb39d8U, 0x1ac727d6125d3e92U, + 0x635e62a173e1768U, 0x1019303dbd48ea34U, 0x7f38e1c454e86803U, 0xc53291fac4cbd0f2U, + 0xdad99ffcc7031ec1U, 0xd8ea0127dbc112d8U, 0x67d5fe25e1fcbfc0U, 0xd40002da14f9b5c9U, + 0x5bc26d3f521ec20U, 0x25ca33c5af373c93U, 0xdef9d1ef3bc3005dU, 0x41bccffad1296c5U, + 0x4a0f5c080c46eac5U, 0x3313fd314992c412U, 0xfdc1e55f773e9da8U, 0x25f6fc0d0e13ebb9U, + 0xda49beae4827ddfeU, 0x6d2a33321349a7e4U, 0x11d7dc4635e7302aU, 0xfc50ea1d7f3f998U, + 0x9882afe82b200fedU, 0xdeaaf1f803f0bbe8U, 0xd120b24d1cf903f0U, 0xe81cfc4afc6ee03aU, + 0xb61ac81dd3e0ad15U, 0x16fb11fd194b1f1eU, 0xc4f6d7862156d4edU, 0x95cbf25abeed814aU, + 0xa72babc3cbe3f720U, 0x1140230eb8153bdaU, 0xb0404503200ded56U, 0x1a06112f0fe00643U, + 0xbfe604f50cf72335U, 0xe9053f3e7fc337f7U, 0x1d06280618c3d1e1U, 0xfbc1514cefda4824U, + 0xb03384be8ecf9d4U, 0x14b6ea941dd5240bU, 0x32264e19c60dd02aU, 0xe8154727e62bdeceU, + 0xe40f26d20afed4f2U, 0xe230dc30f904b5eeU, 0xc80dedefc1dc1dc7U, 0x204efede2cf24cbU, + 0x32d76cf6f3f43701U, 0x385834f9d2f611d6U, 0xfcd9c0e8e83bdcc9U, 0xb831994ecb09d802U, + 0xfe28eac52cd8feddU, 0xd13d5c15141ba96dU, 0xdbdb61e1cbfbbff0U, 0x792a021734e20508U, + 0x11fd1c4c72e01eb1U, 0xd6c827bfc6aaa028U, 0x7f0accd9481008e7U, 0xf72830e6c2d50a21U, + 0xd178cb1c08c2e6e0U, 0xd4faa1ed01b2172dU, 0xf63ff2c4254498c4U, 0xece34de12f2261e9U, + 0x4442e740a6e3df2bU, 0x40261fb7e02da2f0U, 0xbcbebad0e0b00828U, 0xed0c01c738e51bbdU, + 0x532203ddc1f50df1U, 0x1319cc0f382bdf44U, 0x121dd42410f43229U, 0xdad2be10fe4cee39U, + 0x121cdf04debe7fceU, 0xe92dccff0f1718e5U, 0xc001447ba1ed65aU, 0xe73d41eb00f9c6dbU, + 0x191d1fc82837d119U, 0xd53cf8f4e6ecd803U, 0x26bde7d3d212fbb1U, 0xf30e02f131d1ab9U, + 0x2ad0c709da4913c1U, 0xe547281e10da0e4bU, 0x38fff0301bdc0ce9U, 0x316dce02b3aebd7U, + 0x5abee10fdf12f0ebU, 0xca30ee39fe002662U, 0x1fbf2fb9e712afaeU, 0xb36353e8f2c22fbU, + 0xf814d80e1cf0f2b8U, 0xf00ff3d2eedfefb4U, 0xfd083ab0d246feecU, 0xf026cf1207b3f841U, + 0x260d1338ef34ded6U, 0x3ac8cc1dea14db0bU, 0x51b4b3344d13e1fdU, 0xcf453ce31440bcf4U, + 0x1f093efa084f11eaU, 0xc92b3959560a6a50U, 0x3b282038d2087fe3U, 0xa0ef6fbd407b11aU, + 0x9c1fe10b34000eccU, 0x5c11ba00b8e401c5U, 0xe70a32dbd2dad1cfU, 0x1703272f08311c0dU, + 0xf37266e02f4ea118U, 0xdfc2342212feeecdU, 0xf8e8d7bd37ed14deU, 0xfa37e31426432d24U, + 0xca0abbd900d83689U, 0xeef146f3dd211a2dU, 0x9333dd6508b01239U, 0xacc8668313f5c33fU, + 0xcf50dbf77ff20e09U, 0x73efff2bf12301c8U, 0xf8dbf1db5fdbdc3dU, 0xd733e7c62ee40ddbU, + 0x51e34d207d73926U, 0xf13f1503f33e53c3U, 0xba3c0a3bfed4130eU, 0x16761c1c04eaad27U, + 0xe22e2e12b66a424eU, 0xe72dcaead5e9e8ebU, 0xd38119b638d3e8c9U, 0x9e7a08dc231264d8U, + 0x95ce4e41b19cdbdU, 0xd91cf8eade25f942U, 0xd6f21c1e580417c7U, 0xc7f8187dd5d1e708U, + 0xcd2e55e4b755ff24U, 0xebf5d2f7135fefc8U, 0xb40a610942a1b425U, 0x3c0405152bfc51ecU, + 0xefbf04e1f729f768U, 0x1caac8e20e3a1405U, 0xed4bf5f52ead280fU, 0x29cb2e0ef8571854U, + 0x34540eded602f7e0U, 0xef275cf5f8d46ff8U, 0xdc2cf018eae2f528U, 0x4bf944300a0be411U, + 0x32c2f8ee1be5d0c1U, 0x3941e104c1d73548U, 0xe81d30554ff5d003U, 0xd7d5e8ccc781d93dU, + 0xdf07e8164b071409U, 0x483befc7ec01490fU, 0xc5e8ec6c18fe1d12U, 0xfd25cd1d4914d43fU, + 0x2e23eebd12d4fdfeU, 0xe9224b360ef31dU, 0x1dc7ced88e11fd34U, 0x359ed03e9eff1d40U, + 0x29f1fcf73bfa47afU, 0x4c1f13240cabb31aU, 0x9eaf30f6d2cdf600U, 0x4555372218f17f0aU, + 0xd718cb0eb321c5d5U, 0xcf24fbd33602e0e4U, 0x5fa9e411141e20efU, 0xd5ccc2df350808daU, + 0x97bde9690619bf6bU, 0x52cb4050ae2d501U, 0x13150152ea0f221fU, 0x3bef811ef09dd10U, + 0x18fd25f226c9bddbU, 0xf0202438ff9bc1eeU, 0x68c72d3e0c15d40dU, 0x180a4c2bc1ba55baU, + 0xea23350ce9c1af5aU, 0xaec0ca48e51206bfU, 0x2b34f3993e057fbcU, 0xeaf4c69c4a0400e9U, + 0x8aea0a390dbaeef2U, 0xa2529dcfa530051U, 0xf71d2d2bf8f7533eU, 0xfbe6f3e2441f0f14U, + 0x12d837bc5fdaca2fU, 0x200af34deffe3febU, 0xfbb0fc011c4b0bfaU, 0xf9db006cde221d5dU, + 0xb629dfef4c92af09U, 0x31d1e3de22b0be5dU, 0xceecbdb466d3e01fU, 0x25df260d5a0d390fU, + 0x23ede3e548e79833U, 0xe921e3ebc329bae1U, 0x232bc6160bd90c12U, 0x360c460c0d271df8U, + 0xf8ab19f1f8813cdbU, 0x4c4c18b28e0203efU, 0xc8ee750213bfdc0fU, 0xdcadec07c20cfe09U, + 0xec74379b0b30f548U, 0x65a8b9274ecf5b1eU, 0xa905f7fcc72762efU, 0x6112c7f412011be2U, + 0x78e45a2335e4ba0cU, 0x2f05e01f02435540U, 0x2523b03b2ae6c1faU, 0xdff50cf330ab05U, + 0x16f00325f80248eaU, 0xee3a0112e921ff0aU, 0x1dcf2fb01a2530efU, 0xe8efafeae84a0330U, + 0xe6d53012b8342d1aU, 0xd4e42cd40ea12ea2U, 0x34242bf6d8b0e8e6U, 0x1c1af772291fcc0bU, + 0xb7a4ea7f0651bd13U, 0xddf7cf2b552ad42dU, 0xebc8e81c237c680dU, 0x405f1cc2afaf9dfU, + 0x1ff30e04f1e7f61aU, 0xf0f12315541a0ef6U, 0xf219170e0bc83528U, 0xde5c704ec051a21U, + 0x10cf637e5f47ffbU, 0xfde2f5c83804e01bU, 0xfcc52c4f1b02eb0aU, 0xe1e0f1409e5e6edU, + 0x3a341ef4101adeeeU, 0xed34c7061ad3a8eaU, 0xfdcfbe3f901f3e0U, 0x280f060aff320ef8U, + 0xf5c812eff22834ebU, 0x26342a0cb4c90dU, 0x3efbe12601200602U, 0xba4bd69da70c0aabU, + 0xec140927da15ffceU, 0xf555ed26bf37f402U, 0x4efe4f2205e7e2f2U, 0xd9f3d3ffc3d01b46U, + 0xb8d5f1130500ebf4U, 0xa6b3d842cc380334U, 0x7f9ea02cf2f1a3bU, 0x259bc6bb0b052c2dU, + 0x4ea3e1410301200U, 0x55d2ff0a7fd9e92dU, 0x10032f36f7c1f6afU, 0x1f260fa3d90fb9faU, + 0x34cfe6b521f104f7U, 0x140c4cf2032f364eU, 0xc72d2b3ce8f6d846U, 0x1716e963db3ef557U, + 0xff340ae7f5ebdf00U, 0x71e3c824d0e8ebe5U, 0xb8f25797d016ceeaU, 0x2fc3f0af6d91d0dU, + 0xd76a6edf6904d3d3U, 0x6df11f40df628f3U, 0x90ae3d3051626e5U, 0x2fe3f8ed02703a23U, + 0x22481f7fccd2ac9U, 0x28fbfaaae019c2c2U, 0xb8121b52df043f48U, 0xf6b00bd316e7cd3eU, + 0xff0a7cc474e7ac59U, 0x1419f1fde71554d5U, 0xe6cdd9fb1818d127U, 0xfe19a811151ae6edU, + 0x44fd961df754aa31U, 0xd25517462fbf01f7U, 0x47dc081ec728b212U, 0xea508fae0f45352U, + 0x1b1bb4e1b41d38ffU, 0xe4d1ca8c2720dfd1U, 0x102cda45c3ec1c5cU, 0xeda7e0a4dad51a68U, + 0x2747bee4efe2a3ccU, 0xe1e4d258e23afde8U, 0x7f0903b36d3fcdfcU, 0x24026d52d30f8f6U, + 0x1ecebeee1bc126c0U, 0xe0022a2c0e161a3eU, 0xf10c2fd2f258b7d7U, 0x29ea132fe42ef70fU, + 0x243925f824bb13d2U, 0x9cf8d63ad98cb54bU, 0x59f30cd9e9ddf818U, 0xad55f8e8531744f1U, + 0x14e34f527b5bf3aU, 0xc6f7f747fdfe5d43U, 0x1f1edf1b0a7ff98dU, 0xdaf7ff07cd1fb8b3U, + 0xfbee21fc06a9da56U, 0x1f3a00ef44f28815U, 0xefe10e4ac1381a0bU, 0x2ce1e32604d93de4U, + 0x30fe3c2b1347e769U, 0xe0f4ecfeced24db6U, 0xfff1f2c0fa3bcdf2U, 0x1ed3df13e9b5e1d4U, + 0x2bf9fbb6de30a8faU, 0xc808c3d315012a56U, 0xdc3e201b26cf0a30U, 0xd0dc083e16146668U, + 0x3470cb2540df541dU, 0x921febea359bfdefU, 0xffc7c16bb56ee250U, 0x1c4a0b4d0ae3e01fU, + 0x20e32ceb7f1ed010U, 0x6379d635eb0bf6f8U, 0xee1f360edcecd4ebU, 0xfa2f31d20ff6d9e2U, + 0x190fd71f0efd5be8U, 0xfb463dcea1cfa93aU, 0x2d51440f0fd6480eU, 0x130d653811f2e33cU, + 0x1ed102887b75554U, 0xdbd50010491ce0c0U, 0xbb64fcf506efbbc6U, 0x2c2cfc2b19153411U, + 0x2d50176fc20030dfU, 0x29ebf1f7003727bbU, 0xcc86564417cdef38U, 0xc7fbf431333c25f3U, + 0xc9c434afdd5ee918U, 0xbf10d73344fce93aU, 0xd46881133618769fU, 0x45c3c00be7f9bbf9U, + 0xd39c3d3f050f2167U, 0x201de957dbae2bd8U, 0x4cb0071bc23dd104U, 0x4ae01630d6480a75U, + 0x30f9f90804c9b5bbU, 0xeee82bedc2c21337U, 0x2ccd0201cfdbd816U, 0x1cff122125192edfU, + 0x3cddfdea0847eeU, 0xfc22540b12defccfU, 0x816eede6e7b0c738U, 0xcd844ec0ff431efU, + 0xffeb4f29e2ebeef9U, 0x2ee33782e33502dbU, 0xd8fa0a468dd221d4U, 0xec15080fb32055dcU, + 0x2626cdfe174bf414U, 0xddfbfac60ded42cbU, 0x12f5d735175b5ef0U, 0x2913f3ee492ad495U, + 0x1409193b052b2834U, 0xe4ee1823231d4b28U, 0x3a16f93a0529b9f5U, 0xe357bef7f5e90ecbU, + 0x7bdaaf8e2ec1dc2U, 0xf3ee05e00a51de23U, 0xcbc7d0f6ebe2ff09U, 0xf51017f932fb1b2bU, + 0xebcb13eff9c9cc18U, 0x40c701c30312cc32U, 0x4104d4f5103118c3U, 0x45f6cf2719ecef21U, + 0xf7ed1e11fe5d81f2U, 0x271bd2e3461b15d5U, 0xae611e0d641fc41U, 0xf808ec2eeb11e820U, + 0xefc707061a2754d0U, 0x30d91331cd060beaU, 0xedf409d91ce339f7U, 0x1cdae8d5262424bcU, + 0xfe0206d31d00cdfdU, 0x22cdf401cf08d23fU, 0x1f330db5023e1fc5U, 0xe82ec0d606061d37U, + 0x2ffe13ff61621b2U, 0xe48146d0eeca1d0aU, 0xf2bcd818f2e10508U, 0xb8c239f607e41ff6U, + 0x431f8110e02e3c3U, 0xe2cccc23f21a08b3U, 0xdaec03000c2ae81dU, 0x2bf332ff90ef71bU, + 0xe5e610077b1d4deaU, 0x4e9a4edb2216252eU, 0xdc935e6f0c7e9f3U, 0x2b4cff05091413aaU, + 0xcfbae8bd7f2e4cd2U, 0x3e0e14eb15cdaf2eU, 0x1caefdbb1c004ff0U, 0xe7ebd2bb25013e1cU, + 0x2ff73720cd362dd7U, 0x32f82e44cf60060dU, 0xea2120c408d2f3a2U, 0xe5f5171606eeb235U, + 0x1245e1f517038f05U, 0xdcd706dcc8f0c227U, 0x5b2518f0fc2dddecU, 0xa41619d2f71ffca0U, + 0xbf9cf17e0431ffcU, 0x3af3220ed33e81cfU, 0x24f6260906d620f8U, 0x9cda194804eb110aU, + 0x2518b542eede4360U, 0xf6ec67cb5627211eU, 0xf206b37306fbfa40U, 0xeaaf1d55cb77ed0eU, + 0x4ff72cd3c8161ae0U, 0xba0fe72d0fb5450fU, 0xeac9d41c3334a890U, 0x173a28f1e8e0a7f6U, + 0x14f91ff404dee3ffU, 0x11ebf8e916b20af4U, 0x69dce738f9310538U, 0x29e8c7cf3913f340U, + 0xf2c710f5e51a3c06U, 0xdc8126ec34d9fdb2U, 0xe17d6341a6809b2U, 0x18283bdf2cd3fb1bU, + 0xe447f33ddb162800U, 0x56eb24bb01f9e3baU, 0xfee65ffa15f1d60eU, 0x2fe82b0b0d262b23U, + 0x2d63f3017b3dde4U, 0x34f5b601e436fa03U, 0x60fced1cfbe50fe5U, 0x1ef8dae53effe394U, + 0x220dea1ff93ffd09U, 0x46f6fdebe3b6ee35U, 0xf8070032ef163932U, 0x83e700d1439edaffU, + 0xa934effcddd2c70cU, 0x240e3695e7de9407U, 0xe2f02ce9ebc2f7aeU, 0xef3ae72e04f72fc8U, + 0xb11f3be176c31203U, 0xc2febd5c1737d1ceU, 0x45c1b30be111d8cfU, 0xe83ee6dcfefbe8e4U, + 0xbc15eaf32de7efebU, 0x230ad9fc40fec22cU, 0xc9f5e7e5edb21d0bU, 0x2115f5f1df22afe4U, + 0x3037c4c61b007fc6U, 0xcd4fe2fd720c906U, 0xd01508ce0edbf4e9U, 0xf7311524ab45e621U, + 0xd5fbdf17201f3be0U, 0x68fbc8ddde1410c9U, 0x2a1653b7f1cd9ebbU, 0x25ed36f7be0b2b1dU, + 0xe30d38c94717d6e8U, 0x609262ecfeef0ffU, 0xef12fcc342110b00U, 0xe3e80f04df6e3b17U, + 0xa532a832b0144f81U, 0xfbdb38fbe2174142U, 0xba19fa4e1fb636e0U, 0xcbca67d1c6a1de4fU, + 0x532190729e7bf39U, 0x482eebf5e35f2dd7U, 0xd1bde7291dee0142U, 0x957123512281f38U, + 0xe8293bc54bddaf0fU, 0x29b1e6e3dc532252U, 0xc73142b514f9b4baU, 0x3f12f1413016570U, + 0x1030fa1726e12603U, 0xbc5219f1eb1a2e3aU, 0xc850e39ded3b080cU, 0x7f42163dd60cf311U, + 0x15a5f1f61812320fU, 0x420cda38dd292e0fU, 0x776eeee3aeed8a9U, 0x9280d19acc82409U, + 0x561cf71f070fed0aU, 0x5e7f8940a2630e4U, 0xf4d4e34cf2d31e45U, 0x24f3141720ea10f7U, + 0x29c239cdf1c5a60cU, 0xdbeb43ea5033331dU, 0x2719fcd32db5431eU, 0xd29101313007eb31U, + 0x360c21bee52910fcU, 0xf33bfbc9fdfef4f0U, 0xbd1f2237f8fad14bU, 0xd1ddfc2304d6b61fU, + 0x24f41ee82e32fd0cU, 0xdb3394fb26ab0839U, 0x94e5321bfdc40017U, 0xe6fcfdd4f5110f7fU, + 0xfe39030dfdd91208U, 0xe00904f2cfff020fU, 0x95ef372603f12d2fU, 0xf5e49f16154600c3U, + 0x64bd5135fe37e8f5U, 0xdee0092cca21e00bU, 0x68da0cc0e33dfb02U, 0xd4c30dce120026f7U, + 0xc5c2fcfdc1e1fa18U, 0x24160902c2d83621U, 0x4035bdaa3fe851e1U, 0x39b115ecf3c2cc20U, + 0xefbb3708c4e342e1U, 0x29f8e14bb9ec37ebU, 0xff8f3147fd70de0U, 0x1e52efd4242db0cbU, + 0x36a2dac406b7f725U, 0xf63a3b3dd8de10f9U, 0xfce1291301ed16eaU, 0xf42f46373605ddbbU, + 0xc820020bcd421acaU, 0x2ffc0e2c7f1de205U, 0xf6f01d44f333fafbU, 0x4f0b50fc19b0b839U, + 0xd3c03cd1cff00417U, 0x23ed0c41a033dd2bU, 0x194ad45c46f6ed31U, 0xf52d67ef32c61dc8U, + 0x56341b0b492a12ceU, 0x35f6ed49c60210e8U, 0x43ecd018e2cbd8b6U, 0x22c79f322ace0de0U, + 0xe0a32e42f3f6d5eeU, 0xfcf119050bcd0223U, 0xbbca050725fd3304U, 0xe74fe4e5fb64ca11U, + 0xfe5029c726420a0eU, 0x28fc4c0ed1f12bbbU, 0x3db62343eff7b801U, 0xe625b32538ab61fdU, + 0x23ebd61238dd540cU, 0xce60e10f21fbe71dU, 0xfc10ad694c1d7f9eU, 0xa4a72b1b40750f04U, + 0xa54cc7d9b117f8ddU, 0xf7d93611ef1b2518U, 0xb40c6fd22c318f3U, 0x38f310e1fff2c539U, + 0x3bc0f6221a0e3903U, 0x1fe32417c815412dU, 0xf0d222021a21102eU, 0x88f626bad68c89ecU, + 0xef5ce947bdd0ffbcU, 0xf02af7deede4d1e7U, 0x3ae80e47e6280cd5U, 0xfafa0634ff060dafU, + 0xf533462270890d49U, 0xfad1f77bceee9c4aU, 0x6aeee301603c2d9U, 0xd80ae9ef32ccded5U, + 0x9fd7c1a0031bb89fU, 0xdacb431b1a5cd309U, 0x9f14bb3ad7ef1356U, 0x1d025ef50e3dd7c3U, + 0x393adccaf5d97fb1U, 0x25ffee61aa398c0bU, 0xc170d5a025eddbebU, 0x926d8390cf3ffc9U, + 0xcfbdc0507d8c448U, 0x24e014ed2cf3173fU, 0x864df4dc11d4ff03U, 0x26f515ff02e2280eU, + 0x3807f6c4f8f0c2faU, 0xcf23ffc2fd1006f9U, 0x37dfdc59cb01fd35U, 0x1f03301610e40dc4U, + 0x360f0fbe45212b04U, 0x1c57a2bbaefdeb22U, 0xab042614f7dfce08U, 0xd3dacc001df9047fU, + 0xfc32eecc12d321e7U, 0xf1a270be4de090cU, 0x9a1e772226d11d2bU, 0x412f216f13a04d5U, + 0x5c2e653c0427aa00U, 0xdfdfdd06e8f7e781U, 0x10f9281de21a1e35U, 0xe9600c1119d6fe1cU, + 0xfae7d2eccb19191eU, 0xfae7190bb7d0eab0U, 0x18d12cc1fe100939U, 0x201a2ec3f0fd0146U, + 0xf6ddcccb67cf0725U, 0xc7fbe646080413f3U, 0x3d1c10b845c6b6f0U, 0xf6ebca19e124f903U, + 0xfb0c71ff1a2e12bU, 0xe117e73af8223848U, 0x2bf03c3d0d55ded7U, 0x11e31395ac6c007U, + 0xcad4ee0adccdd72bU, 0xdfd6563f472301e4U, 0x11564afc039f81ebU, 0x170f411146333a13U, + 0xd1812e3e9e33708U, 0xf314b918f5362bU, 0xc3cc6e3cd3b6d8faU, 0xf308204ea3f346cbU, + 0x1c44c901b8200ed5U, 0xaceee31f071cc145U, 0xc627190bec2d3a8fU, 0x56be13dfd94b3031U, + 0x16aa112c19fc4e07U, 0x4df6ee1ca4d806f5U, 0x1ee5e7ff4039c71dU, 0x49f057a7c6ce5c32U, + 0xbbe1754d05873e0U, 0xfef0f314d001e0f9U, 0xe5d617d10aef3100U, 0xd88fbad04fd4d134U, + 0x2fff0943e4dfa409U, 0x64dd5dd9013b55U, 0xa451ddb4213510caU, 0xedf7f52dd2eed9faU, + 0x34f00320767f1535U, 0xd13d043e92b3f0b8U, 0xe35db4e426272d21U, 0x2222e80e1e186031U, + 0x20ea2a4fb305b0caU, 0xf9ef0c3cebf26530U, 0x9c23eaf420260111U, 0x26dc551b29ce0af1U, + 0xf5f61a1e0dd8fd22U, 0x208f4f314fe5eebU, 0xe0df019f5f6081aU, 0x5ad60446c1fe3703U, + 0xaf2e6fe2edb1cb0U, 0xa0bdaac2df30bf2U, 0xc5de16de06ca99f9U, 0xc73deff804214e0aU, + 0xf4dc06d0a53af317U, 0xe4ec15c9131681d8U, 0xc900fb0908180ed4U, 0x4b1a20fb1d02fbf9U, + 0x3af1f73de4cfca53U, 0x3afd3312f42122faU, 0xe5c8e532163508fdU, 0xe1a2ca823113d731U, + 0x13e02843d4edf212U, 0x2435262b0ce5f1b5U, 0xfe1e37f1d2b504f3U, 0xbffdef0de5f9a3e8U, + 0xe103e5f30af43131U, 0xbca6bb8130d8e7baU, 0x39ec12fa2b1cdfe2U, 0xd912b9bd57fc2af7U, + 0x2573a1801094cd0U, 0xa4e7fedc3c47c611U, 0xec09d5e5c12cfd07U, 0x2119eb21611dec4dU, + 0xfeee1f0102f5d9fcU, 0xfdf902ec33b5f0c0U, 0xff3cf70b0ef70705U, 0x17de9fdead4c3becU, + 0xf6ff00b064399afcU, 0xb9de695bb0f4f8c7U, 0xd20bfd0236a85100U, 0xb6fcdfcd20f4d6f3U, + 0xd7ebf3d9f53cbd7bU, 0xf9f7d805973531ceU, 0xffd830adf8d9654dU, 0x7d9312dbc18c827U, + 0x41dbddf1e351ca02U, 0x104bff30a304507U, 0xd2c84209fd2ac11cU, 0xd6c716e0c6e0dd68U, + 0xd6e7d1b32b95f718U, 0xec34f0d4c5ed15d6U, 0xb7327fcf2602251bU, 0xee1aacddfdf7032cU, + 0x620dd2f1d84738b6U, 0x3a08e5c9d43ff8e7U, 0x4f300ac4d5390a08U, 0x3731f908c306ff43U, + 0xe1e322fac91a1416U, 0xf1c32318f300cf0fU, 0xc5bcf0e4110f1cd5U, 0x3ed2231be0eff9faU, + 0x9e92cfd3ea3f3f2U, 0xb20a6e92a06f0bcU, 0x7f0713d434ebeeeaU, 0x481f052c36f3e2ddU, + 0xaac9f7ef43292cdfU, 0xb60f09fb0e95d105U, 0x3a182c26b5050f0cU, 0x2c62f051d3111e2dU, + 0xb6ebb1e42d16efa1U, 0x51d0b501c7190e0bU, 0xde47659709fdf8d1U, 0x2830161133074cf5U, + 0x422735da341dd6deU, 0x20f36fbbecb0527U, 0x4406cfeb341decU, 0xeff4143fea4a1d59U, + 0xce129b13e5dd2abbU, 0x16e9daf0e1e1030dU, 0xadff086ae404121bU, 0xcfc828adb69e027fU, + 0x1b4201444934cb55U, 0x2125dce4ef0b39b0U, 0x4cdc11a2e03f462U, 0xf54d0e5fbe08330eU, + 0x19fe2efb6dfa270bU, 0x17cbf300fb300434U, 0xb7e02a07f6de4813U, 0x30ec8b08762bdcddU, + 0x9080fb75705b906U, 0x2d7f0ed1a2ec2b1aU, 0x18ded902e73e3136U, 0xccf72cf922340ffcU, + 0xa02d1d94c0c2024U, 0x41e61e24dafc4de2U, 0x2d09f0ce1202da4aU, 0xe1271de1f5fa0b19U, + 0x975210d803d823faU, 0xc128ffd38ee70325U, 0x4f31326e9ed352aU, 0x6c0b0f42d954501cU, + 0xde9a0c3449b010c6U, 0x1ce6314c6fbfc4aU, 0xe20d6ab27fe9ed11U, 0xeccb602716f7dcd0U, + 0x311665b5f407a1c7U, 0xcea13ddf57bb6298U, 0xaf0420e7bd6be7e0U, 0x2891defd0715dafdU, + 0xfa5649c7e23f4bb9U, 0xf1f4f7e4ac3ed0dfU, 0x13ff3526e0ca2178U, 0x3b28dfd0174435b2U, + 0x5f6144bc5be1faccU, 0x1d2b3cea29c22fd5U, 0xf0e1f4d4eeb82ffeU, 0xbb13c2eebcf823a7U, + 0x3d22a148301006e9U, 0x26680703fd5db522U, 0xd310ebc51ac52403U, 0xd60f2ab3bbdfe6cdU, + 0xd0feb545e1361747U, 0x2470103e50bf9U, 0x1efc160902b33de8U, 0xd39a336f2167ec31U, + 0x36fff281d2392f17U, 0x36dfe84fe4db4fd4U, 0xf4cec61630ccdedbU, 0x25f800e9eb4ac0e6U, + 0xd1f9e2e100b00043U, 0xf69f2214a1fb4262U, 0x5b5b163ae0f5b5ffU, 0x4be439dd552fec4dU, + 0xbb3d2d0bdaf1df2fU, 0x47d3ddcd35eac6f7U, 0x4931e61e38d8f693U, 0xf4f008e8efcc1708U, + 0xb877efd9054df338U, 0xd11f50dc4635d8U, 0x940e2f9ea0000de4U, 0x78f8260801ffd0e3U, + 0xfbc2d404bf3f15e9U, 0x23db4c1e3cbb36daU, 0xd63b2e0312fa1a81U, 0x20de1b4ec08e035aU, + 0xe4a4282c2cff4a1fU, 0xef20296f0325927U, 0x2fbddb05254f3314U, 0xefcf2121f9b65551U, + 0xf64c0815dce3ed4aU, 0xfdf20efc21ba3dcaU, 0xcffceeccfd0b00b3U, 0x293c38c8c4f3c4fdU, + 0x3ee0ab02f3e4c8daU, 0x54d845c54a177d67U, 0xa5527f301bbd01c7U, 0xea5515b14305514eU, + 0x2bd111fd090a62caU, 0x41082efb2cbef5d3U, 0xc9d1f6014599bae5U, 0x19e8220e1df0fed3U, + 0x680520d7be1b07c5U, 0x13cd0b0d10d6d6b8U, 0x2ef42db11833701cU, 0xd0cdd41bdf56342bU, + 0x16230adb2e26dcefU, 0xf622e22b32d29f14U, 0xf51107b44fcdb541U, 0x35b715a6d8d4292bU, + 0xe0b3ef26e614ef27U, 0xfb04c2e3f82b0beeU, 0x9d0014dddea1c6bU, 0xe5df7ff20b04cd15U, + 0xfacd0cccd90a0ff0U, 0xffd5051c111a1aecU, 0xe8a4f20ad3c0f30bU, 0xee0105e1f4ecf136U, + 0xbdafad5a0eed5fcU, 0xe6220a01cc1c144cU, 0x291d02e507dce1f4U, 0xee25cafe00363bc0U, + 0xf1cdd2b7f28f8daU, 0x1527255eab5cb3e2U, 0xdf18cfff40143aa4U, 0xd9e703af49ed07efU, + 0xd30625eac9e9ea7eU, 0xe350331bb6809ffU, 0xcfc30317bced501eU, 0xcad02f11e314e961U, + 0xe6f5f5bc0c114224U, 0xde07e231162139f0U, 0xffd910362bc5e903U, 0xd2e4ef4fffe39bf8U, + 0xb030ede0edf8e302U, 0xf1cc0d08e71614dfU, 0xd01046ef180cf6d3U, 0xc51803d2ec20f4b7U, + 0xdcffd4211c4f0404U, 0xe0f222def7cccb33U, 0xf50dfc4fee0d4212U, 0x311888e9ca2c441cU, + 0xd626b9e1f61d2450U, 0xf1c513fa0a4906d7U, 0xee2e395b61627cdU, 0xa81aeff13711d52dU, + 0x3cfedaf07e10bb9U, 0x2d09676db3ea1ce5U, 0xef3f010f01e2dbe3U, 0x400cd9a0553606bdU, + 0xd7f120b506e48121U, 0xd2f719edacffed76U, 0x5e6e02c32b31052fU, 0x8af202f1f8f819eaU, + 0xf3d2dcd32d4ac3f3U, 0xd61907dac2f9dd26U, 0xb1da1e591cfdde32U, 0x19e8a1b50eff16caU, + 0xf71dadea0951df6eU, 0x732272668700103cU, 0xd12ee3cd01e940e2U, 0x9233143f30151d4fU, + 0xf6f4bbc2dddc15dfU, 0x22c60dee8d1130f0U, 0x40caf22624b7976eU, 0x2252f04d6ec81d0U, + 0xd278f08cdfc8e4daU, 0x1ab100dbde330cf4U, 0xdff236142e160c25U, 0xedb10f06c4d42325U, + 0xddd092e33e3cc39U, 0x170d6224e0050330U, 0x13eec9f00e0626efU, 0xcc02b116042eea24U, + 0xefbbd903fda0dbe3U, 0x8135e126e32505c7U, 0xddbcf5c9cf34b008U, 0x94fbedd70ceb20e0U, + 0xf7354bbcfa36a80aU, 0xb2f04111ccaeba1U, 0x20d00cbe41b1e203U, 0x41383b25a91395a8U, + 0x3cadc1c53beb26a8U, 0xf2491e2ee4e9ef24U, 0xd4015115100538c6U, 0xe5d3cef4b29ef319U, + 0xddf024fdfa1137b6U, 0x17f332dd3ae5e612U, 0x38f73f30350945ceU, 0xfac02bf8cfe4e8d8U, + 0xfe0f55f91b814308U, 0x20fff74233d624d0U, 0xdad1001914df0fb8U, 0xe612d3ccf9dbb4d6U, + 0xd1a1fc21e904bbe2U, 0x1e07201e16e1ce34U, 0xb2be5f700f9e0feU, 0x3f0e45f82a223e29U, + 0x361bf9eef5112ab5U, 0x15b30b35fa149b47U, 0xaa51d49ef9d2cff4U, 0x22041bd72543f52bU, + 0x12e4c52ffffa2df1U, 0xe866e45108ffceccU, 0x3e09e110f6faf840U, 0x6eeefe2c0fdd1a9U, + 0xe50bfaeefe0c1ceaU, 0xeeddcedceb04bc2fU, 0xc90ef4cd2df50e0aU, 0xf9d7dbe80e12582eU, + 0xfb37f414bf00fdd2U, 0xcfb638f90d00e5ffU, 0xe9cdd91ac62961e8U, 0x4c538130508fdd6U, + 0xaad5cf1dd02d21fU, 0x30f9f37f30b442f3U, 0x5dcd81f0a4f02c7U, 0xb02d16808237f01U, + 0xd2241954e77be13bU, 0x530777dcdefe3001U, 0xe92a1436baaff04fU, 0x35aca202f1072729U, + 0xf927a3cf1c021810U, 0xedc5d330c9bee5fbU, 0xead3aa05ffb6ef12U, 0xb41e246848214724U, + 0xc0f036fb214eec29U, 0xe3fbd114ab2f54c5U, 0x25f7afa199ee37e4U, 0x912f855f5fd4bafU, + 0xc7c4a9f4ac14d750U, 0xdfcffbd5eeecd8b9U, 0x9402e1034e6142dU, 0xf5f3ff30013716f8U, + 0x1d3fcdddfa30e0e3U, 0xea0b05edbc28ccfbU, 0xf6f70218cb032ec6U, 0xdb50324210000feU, + 0xc019fdf0cc0ee447U, 0xf6256defcdedf31cU, 0xb08f8f709d37fdeU, 0xfbf52b1b1023de21U, + 0xf0e50fdbd7fc2817U, 0x513c444d303facaU, 0x1cf5f7e42111c806U, 0xb55fb04063acdc1U, + 0xef0627fc060ddef9U, 0xe5f240f9e5d1f90eU, 0xd9cd07272dd024edU, 0x323731ea50f9b7f4U, + 0x12a8db1b3357c122U, 0x5702c4d15933dd15U, 0x58dc40e5dfe4384cU, 0x1fbee16f244eb40U, + 0xce160a3dbef57f51U, 0x2d0b13eec9072973U, 0xadb4192ec63ba83dU, 0x15affb0512e03506U, + 0x2038d7b86c070cdbU, 0x77180ef6cf321e20U, 0x1fd65dc5f4e624afU, 0xa0c29d5e2a51e13U, + 0x9ce7dbcbf8bdc036U, 0x32704118d14bf130U, 0xd72868e2e1aa3027U, 0x6773140c0ae2ee40U, + 0xcfe1cdb14da3222U, 0x50380e41c94b12feU, 0xbc06da3733f51fbbU, 0xe3dacc002ff0f5d9U, + 0x22d805d92c47d70eU, 0x2e1f3c352a3f03aeU, 0xc2e3f9d0cedddd36U, 0xf93cea1cee083b08U, + 0x7f0a00d343fad9edU, 0xfbfa45bcd41d3433U, 0x1c3633ad00b21ee3U, 0x794dc81d042106f1U, + 0xb0d9e9cda94d1bfdU, 0x8ec29caef02d505U, 0xd8c9020df7491745U, 0x27ee7c1bcbdaf5f9U, + 0x3426140d5ce66515U, 0x7f031acb16214bafU, 0x30318eb26e8f21cU, 0xa0afa0cd0342dcfU, + 0x4afacd9cd926e524U, 0x90ba2ca18ed0f37U, 0xd0c8f9d2e205cd24U, 0xf12d1baef32b2443U, + 0xe107f89eee43f745U, 0xcaf112ecd82ce4b7U, 0xe45472dd2dcaff5U, 0x169f2040ef32cff9U, + 0xf24dfef20a0bfee3U, 0xdf4a8f0cd190e07U, 0xbe1e1fbc1ffbe21eU, 0xf9fb07dd0705da0cU, + 0x1adac5ca0e102656U, 0x30f30be51547f2e3U, 0x9e4c2cbb6ce11efU, 0x3eb4f31bf8efec2aU, + 0xff41ce70efbfd03U, 0xbcb4e9e83566f7c0U, 0xc91ed60ed4ebdd0fU, 0xb9fd160058280dabU, + 0x3fb0410bb6b1fd0U, 0x10ef0f2f17cedda0U, 0xcd075f1fd6f71e0bU, 0xe208cbe2c8e69f7fU, + 0xeeeef8f9deb665b4U, 0xdf482c2e581325d9U, 0xdd0b3d1844cb6114U, 0xf0852bac7ced21aU, + 0xdba6fef40a0c063dU, 0x2af2e837270afc1eU, 0x2cb4bacaceab368fU, 0x3fd340f0b026ebcfU, + 0x2c18351569efcc0dU, 0xdca005ab52244c9U, 0xa64b23b4d8ecd742U, 0xd3543ac4b7b2051aU, + 0x60e62fbd53a5325U, 0x449fb8b0cf10d026U, 0xab0b01d22209f060U, 0xbeece1c435fcedc0U, + 0xbb06efe6c2a1af81U, 0xb33de724fcca5dceU, 0x3d1f02a53319e600U, 0xb4edec08e0de0df8U, + 0x20fdcfd0d60030cfU, 0xf4bf46f524e8fb04U, 0xc9f10c42e1fe1009U, 0xeec5ec353f37ebcdU, + 0x1001d9b6fbef0a20U, 0x1c16d87fe73fc717U, 0xf0ad25152e09e4beU, 0xc4402ff3caf8040bU, + 0xbb240acd2cf9e2c9U, 0xf8324c270300262fU, 0xfb00240a3cc913faU, 0x616181131e41ad0U, + 0x715f2c8fc00fa1eU, 0xb9ff0d01ebf6b40eU, 0x80706e20726e51aU, 0xc8d2bf23c651fdfbU, + 0xf26b1f1c33f3d6d2U, 0xe1312cf7f963c413U, 0x121c3b0dd9256223U, 0xcdc22881f8d5f7fcU, + 0x9be1ccecd010e664U, 0xb7121c1d8c1b1ffaU, 0x4ec4e0c1f80971ebU, 0xc700420420ddcc2aU, + 0x280ee7ee46f533ebU, 0x21092b51f50a701aU, 0xcfe6b21d4026c1fcU, 0xa05bebe7efcbec3aU, + 0xa00d169ffbc20235U, 0x288ec739a3085324U, 0xca1d7d3b3ce803f6U, 0xe0695006d600fedeU, + 0x2d2af2caf0924e60U, 0x31ade5130e46ccfbU, 0xd021e7e0aedae4ecU, 0xd0a4c2b9bf383ea3U, + 0xba10deb771e2320cU, 0xb00ab2f95dbaf0f5U, 0x6eece48bf503de9U, 0xf6c91bd329c5d201U, + 0x1e1099e174f27c5U, 0x1dc61895f5284739U, 0x67bedd2a12301b40U, 0xdb5bc1ccb0305044U, + 0xf48676feede704fbU, 0xdc32acbdedfd3babU, 0x4c3f57fe11dec25U, 0x3d0bb942813ac822U, + 0xcd24af190d5209e2U, 0x5914c113b10f00fcU, 0xf7e25486b12ac7e4U, 0x24df26ebcbef53fcU, + 0xef3431182b2ff0e1U, 0x59d13dfbe0a730e6U, 0x104d0dcc26f11901U, 0xe3adb8140d762560U, + 0xb13881e38ffd64b7U, 0x26c158ecc9e81ef5U, 0x981fb245b3b5492fU, 0xac906ce6c80f38fdU, + 0x5804311e550fc526U, 0x6215ab1efd4a5cd3U, 0xe6ceb0082c14e722U, 0xba159b09cb575b20U, + 0xfe44bafd0ff4e7c1U, 0xba2614152644de2dU, 0xbf527e8ee1a2462U, 0x170a57bfd516163dU, + 0xd53124e2d708ea10U, 0xc3fc17ca384e1d16U, 0x611be83af2fd032fU, 0xe3e77e53122de816U, + 0x26b756e3a34b24c1U, 0x33cad61f0aed3ebaU, 0xc6d3b6f3efdfc1faU, 0x172c56cfb1df82feU, + 0x55bad481d607eed6U, 0xe321310d0130351bU, 0x52a22a9f01ab0f0U, 0x334a2937c2df432cU, + 0xa7313bd944fbc8feU, 0x14be03aebb1b1912U, 0x3c2e2cd353c8cac9U, 0xfe8534226db5673U, + 0x4c65ab245ec50cU, 0xe83a3f25dcff551dU, 0xfc09d6c520e4051dU, 0x3fe41b37be31052aU, + 0xdec4fc0dbb5b01b7U, 0x2416d14bfaeb31d7U, 0xd8580b4c332b13e5U, 0xd0e822c2a0eb282cU, + 0xa15f80b37e30aeeU, 0x3829e1c2e0581923U, 0x5c11b7f57f12304U, 0x1938dc2fd5285308U, + 0x2b214bf11308f1d2U, 0x5bbf5ef01202381U, 0x4d51617f3d50aeaU, 0x140e2c0411e417c0U, + 0x1fad5ebfd15011bU, 0xfbd92a06cbce2724U, 0xa6b34dde1d0e3501U, 0x4208ddaae2cdf743U, + 0xf306cfd4f62bd1faU, 0xc01be5113f02ded9U, 0xde3623dc22fc080eU, 0xdabd1c24142aca2dU, + 0xd9fd0835ea060107U, 0xf738d1101ce23bfaU, 0x1d110e144dc25f8U, 0xae3106b82a1cff3cU, + 0x1109ebb89d07d600U, 0xc750fd295f03db48U, 0x7231f9421de7211cU, 0xe9f404d4e819b411U, + 0xca1bf243ccd010feU, 0x41f2c7d5410c4b25U, 0x7173505ff806fbe4U, 0x15ad5219051f6e42U, + 0x24cb3381080aeb10U, 0x44fce906719e21a6U, 0x12b40cd7acdecf91U, 0x616cd10d324c1d7U, + 0x1d9deb3614d92835U, 0xdcc4601f22a212bU, 0x772437388bd9c33dU, 0xf264520faecab2aU, + 0x980814faef34d969U, 0x2ceb15284024d903U, 0xa20efa18ea131817U, 0xf2baeaa1f9e1f219U, + 0xdc0a1a00f9f3f7f4U, 0x21ad1ee23a3a503eU, 0xdf170e0a2f0abcefU, 0x18316fdf0cb7fdd9U, + 0xf81a0d0fe544ccfcU, 0x7fd0fa79fb02cfe8U, 0xfe0baaf0f5331ebeU, 0xe122ca12cf1601efU, + 0x8c826c51103380cU, 0xb82758d7d4fad727U, 0xc72db0190b16f0f5U, 0x16c2b708bce7d029U, + 0x1fd02c4d2a1cd82eU, 0xe6e62febe22509f4U, 0x281602e8351b02c7U, 0x4bcf274b24010efdU, + 0xde0e31f3cfebd40fU, 0xf9e6d4e72ed92910U, 0x1e56007ff229b71dU, 0xd15f1fa02eb1b13U, + 0x6d93a090237e0d6U, 0xf1b213030ba7c2e6U, 0xc422332bffb22e0bU, 0x49ded7c6cff0db4cU, + 0xc25072f0f1de005U, 0x1fae4250e4268f5U, 0xd4f9392832151f1bU, 0xead42ba9e866b7ddU, + 0x3ed4f8f8ecefc2e2U, 0x6e6a222a00460d0fU, 0xdce5643d58eb30c2U, 0x818eb13351d8e4dcU, + 0x1bfafcb7ece94c46U, 0xfb2bf13d2227dfd3U, 0xf841da083805f7f0U, 0xa399e7cfd21892ecU, + 0xdecf02c42a06f5b5U, 0x35efe647081435ddU, 0x64e175a1558f6cbU, 0x32d82fe69ced11e5U, + 0x61d403ec23e433d1U, 0xab1f2eadb0b0d1cU, 0xf2d52c68da9afc00U, 0xe8d0000038fU, + 0xffffe8a0fffffed4U, 0xfffffc36ffffef07U, 0x1100ffffe6e6U, 0xffffe998fffff064U, + 0xa31ffffe0bcU, 0x12e2ffffe64aU, 0xffffeac900001835U, 0xffffdb61ffffdaacU, + 0xf77ffffe769U, 0x8bf00001a95U, 0x11b5fffffb3aU, 0x50500000ff0U, + 0x16efffffff9eU, 0xfffff57600000560U, 0xffffcd4d000017d0U, 0x199ffffeeaeU, + 0xffffdab8ffffff35U, 0x19d1ffffc2fcU, 0x38fffffab2U, 0xffffff1cffffead2U, + 0xfffffb4300000437U, 0xe160000095eU, 0xfffff519ffffe165U, 0x100affffd152U, + 0xfffff4dbfffff33eU, 0xfffff3dafffff8dcU, 0xffffd243ffffff62U, 0xfffff14dfffff6c2U, + 0xfffff9b4ffffea8dU, 0xfffffbc2000013e1U, 0x3efffff746U, 0x176f0000009dU, + 0xfffff98100001f04U, 0x1dfdfffffa68U, 0x120300001abeU, 0xfffffe9c00000ac7U, + 0x135900002083U, 0xffffdad200002478U, 0x860ffffe380U, 0xfffff60a00001420U, + 0x5bb000008b3U, 0xfffff950ffffe0b1U, 0x181effffea0dU, 0xfffffcddffffe2c6U, + 0xa3100000735U, 0xfffff606ffffa9a3U, 0xffffe2e6fffff9e5U, 0xffffff4000001730U, + 0xffffe495ffffe8e3U, 0x1e62fffff70aU, 0x769fffffd5dU, 0xfffff8e3fffff3c9U, + 0xffffecffffffefc1U, 0xfffffbcaffffe795U, 0xffffd4b6ffffc569U, 0xfffffc8400001752U, + 0xffffeae3fffff940U, 0xffffea8affffd0b6U, 0x15bcffffee47U, 0xfffffbebfffff84cU, + 0xffffed3efffff70fU, 0xffffe65f0000183eU, 0xda4fffff188U, 0xccd4dcc181488104U, + 0x1957d1977f48bb81U, 0x7f450ce3cce01653U, 0x5d4c4d7f547f8153U, 0x7fd7812d5c0d647fU, + 0x1d81e8ac556a8128U, 0xad81a97f7f8152d1U, 0x81dd3faba6e4e87fU, 0xd27f81107f7f587fU, + 0x812fedb481589b81U, 0xd273fc814e3b1e9aU, 0xd37f81ef4af87f08U, 0x304c5caf987f7fe4U, + 0x1e0641e87f8dd681U, 0x4743c4457f3b3ce9U, 0xf5d87f01e47f227aU, 0xe7f6eff3d256e3f5U, + 0x1b4f81cf5852d9caU, 0x141411ccebe13006U, 0x5d4d36414745bb47U, 0x6b55a5e2ed094d3eU, + 0xf8cf06b00609c52bU, 0x8184fe4746cb44c6U, 0xc00418aaa7f0c930U, 0xf04ff1f43e2a3118U, + 0xbdf0e8a3082ae5d3U, 0xa207ffa1241b16c0U, 0xd718bd3a25ee4101U, 0xcd8140b4ff393781U, + 0x4b0346e5ed0ba7a1U, 0x8f2019123e4b5a00U, 0xfb8477fcf631ec3cU, 0xeeec6d1bd237fe12U, + 0x2532bdcd2a64e8d6U, 0xd432f8e03bfa2700U, 0x2e700d3b5150c449U, 0x417fe68111e43f41U, + 0xfeea0211500bcb0cU, 0xbece81371bcd43bfU, 0xdf1a11be81ddac2bU, 0xaf3004ea100f25f3U, + 0xd43e0ba40a35ff05U, 0xff33ed9b401b0ea9U, 0xe70ec3f020f610f8U, 0xe0d840c3293839b5U, + 0x1bd062ea10d013c9U, 0x892008f746477fe9U, 0x7f86126064a1357U, 0x3cdd2d24ed610307U, + 0x2b0e55cb2a7fbdd7U, 0xe5230af509c6e91aU, 0x222f2f3c5631de2fU, 0x2233c5ddfa105032U, + 0x1f0e5fa4b14e713U, 0xede4b9260ef019c3U, 0xf50b11f795fdc259U, 0xd21f05d552181ff0U, + 0xd70605810627d037U, 0xb7ffeaa95a1606b8U, 0xdb37d3112ec42501U, 0x17923fd8ec1b38a9U, + 0x1bb44afc1bc669a5U, 0x1f2222af4d23def5U, 0xc2f9590fed2f0d67U, 0xae1e371f637e804U, + 0x1e3610c1055fcbf5U, 0x100f80c0ad71b38U, 0x49ff30145d50e62aU, 0x644dcaad84d531dU, + 0xd5e6d7cbf91c0733U, 0xfef6ef391be038cdU, 0xe5cd120a8e50ce52U, 0xdb2fb6a639036504U, + 0xbf81131c24f2bbfdU, 0x81f6e8c6601e05f2U, 0xc75accf63bcb2e03U, 0x2a76ccc191c341cU, + 0xe63477180091f39aU, 0xd32f3c8138411c35U, 0xd033520ad91bf138U, 0xe8defe3bdd47e504U, + 0x150d2981ba58f1e1U, 0xb4fdfec911e31006U, 0x37ce2c267f60d56bU, 0xefcf05e7e77f4a31U, + 0xceea1953f9f5fc16U, 0xbee501302bf069beU, 0xe09814fada20c11bU, 0x1c36bed000097ffbU, + 0xdfd203125518c7e6U, 0x2033d8ec68251a23U, 0xd929ca1c7cf61e02U, 0xe5887fdb0d0725cfU, + 0xb01c6012398387a9U, 0xf2293fe52f100bf9U, 0x540f607fda2c3750U, 0xb3e1b3ead44de004U, + 0x344ae9b3b65ef5deU, 0xc5df0ad24bd7efd9U, 0x40d2491a5d51ce3dU, 0x2101f105f45c501bU, + 0xedea0f0ee209151dU, 0xd8dc452830eb4df2U, 0xdfbc1920a3aad0eeU, 0x313ee781f50b5e06U, + 0xebeb0d1a2bc0d4d4U, 0x333b03ff7f2e242cU, 0xf62dd93458d90107U, 0xcca174c435e818f3U, + 0x14fc4ce0f99207f6U, 0xe231cb61b7ff759U, 0x3308017ee339222bU, 0xf0ddbef8fa5b03f6U, + 0x3236c5a1dde7f4fdU, 0xc411fdee152fdad8U, 0x20cb52152747e93dU, 0x1a2215ffc81f4f3fU, + 0xecf7d726f919fb33U, 0x2bdbe64208ed1ee0U, 0xe18113efd886c0b9U, 0x312efcaec40a27e4U, + 0xdf3a344f6bd1e4c8U, 0xd913f4ef772d1337U, 0xe0f6d8f450b9f511U, 0xd6b101c4301b22dfU, + 0xe9a87ff4020cb699U, 0x2e3e55ed283117cbU, 0x7fea0f30ec40035cU, 0x15df091ef77f00e0U, + 0x3217a3d4be1326dfU, 0xc9e5f7fc225c81e7U, 0xf6e33e0e2b5cd722U, 0x1c3606d91c206014U, + 0xe3f5ced20d4b093cU, 0x7e6ee2e10e847d8U, 0xefe809e0ad88ae49U, 0x4f210c91f1152300U, + 0xc8c338524efbdd1fU, 0x1ad0efaf5c3523fbU, 0xcc2cd0f726c8fc0aU, 0xecd3fdcc0f15111dU, + 0x2322401bfbe0ffafU, 0x2f3b01b737110281U, 0x16f50345c6353d49U, 0xe8dd0d2ef54eeeedU, + 0x1b2b9cc7fa1f08d7U, 0xbbc70227e67fbbd0U, 0x18e6440e4346cb36U, 0x11710c1dbe1d5d14U, + 0xdefccf07074b3223U, 0xfef1ec1525e067c8U, 0xe71307fbb58197dfU, 0xd91b16a618080dedU, + 0xc6dc3fec61c7bafbU, 0xe64ae8ed592e00e7U, 0xcb24e2e14c220d00U, 0x8efbbdbc12041bccU, + 0x15816bff3b8150a3U, 0xb93416ae20186c16U, 0x654eff57c3221c57U, 0x2cdf54ad638f3f1U, + 0x474f03d7df0721e5U, 0xadcdfa2415749eecU, 0x14d47f1b216de554U, 0xc3f52be7c20b640aU, + 0xc6f4d0ba813c170cU, 0x2604fd041eeb38d6U, 0xdb061081c1d6a0e0U, 0xb101508ef106e805U, + 0xd81224343ec3bb38U, 0x17bef3fb5e492204U, 0xcc06e9062c1e1013U, 0x81da16b74314211dU, + 0x22d14bf42ad47fb9U, 0x60d51912547f000U, 0x1bd99d52a32e4e6aU, 0xfcf9b36da441ed9U, + 0x42c4edd0a8de5bf2U, 0xabc90d122940e3e4U, 0x1bbc5d0cf725ec7fU, 0xade0e3181205c10U, + 0xa1fbc6d5d7304f26U, 0x9f931280aed71d2U, 0xedd81794aebcb0f3U, 0x81fe1aa5f5f4e725U, + 0xf0e234bb76d2df08U, 0x4481ed0e673530d0U, 0xcb6eecbb36eb1f10U, 0x890f16a834f319fcU, + 0x3c62c2306b5ffb4U, 0x4d3c3a190d332a08U, 0x3931ed66af143f52U, 0xfd2b051ec4c0bd2U, + 0x42bc53cac51654eeU, 0xfdbb03557f37c799U, 0x7fd52a14e237dbdeU, 0x292b18a18d27582fU, + 0x81f4c8901a2eee2bU, 0x5b25241713f645b8U, 0xee1518d3e9a5886eU, 0xdced43b7d40eeaeaU, + 0xdfc616ea75b7d848U, 0x1bfdd1f6423838ddU, 0xd63be9812af00c20U, 0xab21119741cf27ecU, + 0xf4da60faf36e5803U, 0x7f4c19731317fd08U, 0x4eb1023f812e5323U, 0xfcc8a57fe335f8ccU, + 0x457f63d2e6004ef7U, 0xf9c0d41d1fd8d38eU, 0x62ce3207ee28bee3U, 0xe22506fee6093c34U, + 0x8703b4bae543604aU, 0x4d2165341103729dU, 0xf2614c29e7dba305U, 0xd8f732c5bbf6e4e2U, + 0xa6930d654e1c429U, 0xdd30bfea385459e9U, 0xbe4eedac1fdb0e36U, 0xa83feb9f2bea22c9U, + 0x5a868390c6191bfU, 0x3a593c771505f40cU, 0x468136139e296c43U, 0x7f81814bba51fa81U, + 0x7f3244c1b0de7fe8U, 0x6b81817f0709da81U, 0x20817e10f740bccbU, 0xbe19461950347f50U, + 0x82f18181b07f307fU, 0x292a463026d97f81U, 0xf0d37fab99f48179U, 0xc9347f9ff3fac20fU, + 0xdf247fbdfe8181fcU, 0xe609819c277f7f81U, 0x8164e2d17f81097fU, 0xa74cf8817fb139beU, + 0x7fc94f7f393904b4U, 0x417f7f433421f8e7U, 0x5282bce9c537f7fU, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x0U, + 0x0U, 0x0U, 0x0U, 0x2a4d20fbed321164U, + 0x9fd030aea048e9e3U, 0xc3f40fe04c7a1d26U, 0xed13f088d147c006U, 0xa94496e452418833U, + 0xf8010fdb17086d60U, 0x13e2243fcf250710U, 0x3cbdc6d3d2f5c811U, 0xfcfe508f2eb81eeU, + 0xa6d8241a33074332U, 0xc8162556cfa40dd4U, 0x1f13172955edf9d5U, 0x33d215c16c24e442U, + 0xd7e1b635ecabdecaU, 0xc604a71045f8d112U, 0xe6d4005432ca3a4eU, 0xe535f22aad33ddeaU, + 0xe931f9c9d839f2dfU, 0xe12847e9e11ae5daU, 0x42af8c0cce7c82bU, 0xef1f02b4f3f9fff6U, + 0xbc36c70b1ef1f048U, 0x37072733cc60ff20U, 0x4f1cc401df01f34fU, 0xb5eefcefdafffa3aU, + 0xc9f9f7ddf6ddd9c9U, 0x1d0bf83cc181b104U, 0xcc0cebe9f5a797d7U, 0xdcfeefd92e38a424U, + 0x48fc28ee19cfdb0dU, 0xc42ce7df0015dd0fU, 0xc5072fedc2bc1991U, 0x2d6df4c0d0eac809U, + 0xbd1de2cddc5228fcU, 0x29ca2022dd14becbU, 0x2d3ca85e30219e3U, 0xf21922002f16e3f4U, + 0xfb5bcc01efe3fd35U, 0xd6031afcf3f53611U, 0xeae0e2a60c27deddU, 0x17a2dbf7e6b92204U, + 0xcaf9f540e022bbf3U, 0xde21e8118ce8951bU, 0xe13ec7110406c581U, 0x10d2e9e32910afd3U, + 0x4bd31bb2d00f24c4U, 0x1c25f2e9253c1b14U, 0xe81bf0da01e23cbbU, 0x3516f0b49f35875dU, + 0x91025093d7eb27d3U, 0xf1302febe1e6f8f2U, 0x4939f4c2a3135818U, 0xbc06ce363cd4816aU, + 0xef234b2335343afeU, 0x1dd73130e45ada1aU, 0x37b7a9a93e53e447U, 0x21aec44657bd88e8U, + 0xac114cdd3971ff37U, 0xee3ac0bdeacff4e2U, 0x3adad2e15fe2e8afU, 0x2fb60af35ff6fccaU, + 0x2600ea45d9cfbe42U, 0xeec39e0a6029f7f5U, 0x26212355ff1ccd1eU, 0xe342f6da1a530d0eU, + 0x9fa30bd1d440fefU, 0x37f9fe3ddf1af62dU, 0x1ddfe1eca6c6dcf5U, 0x58d9ecd5f51b22f0U, + 0x196cf9011ecf1df2U, 0x36d7da37c936284fU, 0x4101e707f4f30919U, 0xb89e1cde3022202aU, + 0xe2f5eceeb903feebU, 0x1503a517cea4bad4U, 0xa7bd0ce935140fb5U, 0xbec414e01f24810bU, + 0xe72a1c290dd51fb0U, 0x390cf1cdff4419eaU, 0xe708e8deefe009c1U, 0xdf4fca03d91c18e3U, + 0xf62538b9e8d51690U, 0x1f81f401434e1008U, 0x4f06a30ed6db1600U, 0xee622c2ff1dee221U, + 0xf0f173f2cd2e417U, 0x24cb18359b674d45U, 0x51ebd0d530eb81f4U, 0xaed15d4ada16c53eU, + 0x1c04d9b8f930582bU, 0xda3ea5cab0ea0811U, 0xf6d8d44a11f213e7U, 0xcff621f636cfecd1U, + 0x803b6f8e5243aafU, 0xdd4accc7b31b220aU, 0xe6bcc72b25a81bc8U, 0x3b2034e0aa132d0aU, + 0x89df3c37b4cfffffU, 0x8b1e7c1e0ecff04U, 0xd5c2dfe0283d480eU, 0xc393e23b3232c813U, + 0xbbf2a5ee2af1181bU, 0xcb4bfefeb0520ab3U, 0x1d07f31c55c7d001U, 0xdfded51803d20606U, + 0xf0c381c9eabd701eU, 0xea2c16e0fa0b1a01U, 0xe642fd1329b34006U, 0x94302e4d09fd0ae9U, + 0xe82caec6e2c9e2ffU, 0x100db4b91209ed06U, 0x1cb8e75b1a191b07U, 0x41193ddc0f321ed0U, + 0xe252f6a3d351c1cbU, 0x984606993451ca0fU, 0x4531093ab7462364U, 0xfd26e3e46c07816dU, + 0xce6acebbeeb32ce9U, 0x4c9a3b58e96516e7U, 0x329785a5cb148fc8U, 0xf50ac02139fcc52bU, + 0x16532c9ed3431c0bU, 0xf1458466bbadb711U, 0x3ce6ceed06e6a396U, 0xb7b7cab64ec9d5ecU, + 0xd8ac190de539d61bU, 0x472910eaf82ddda5U, 0x21d51935c1ab2308U, 0x390f33df120ddefeU, + 0xb4420309e917e50cU, 0xe5d221b32c1b3a4bU, 0xbdeed00c2eea7f3cU, 0x87e8c308fee6fddfU, + 0xbceb691cf3628f4U, 0xe611e6109a2304ecU, 0xf9ec150647fbfc41U, 0x17e1f1212a29e8d7U, + 0xbdfc05d824f4355dU, 0x3b0c0dba155b0a07U, 0xbf39f91c2ef13407U, 0xf50f2c2e15da3bb9U, + 0xf30f8116180ef200U, 0x2af797f452e9fcf8U, 0x25c85c06e14adb04U, 0xde628fa1fa8333bU, + 0xc0f3441fa14f93bU, 0x3431c831dd40fa63U, 0xb23a2810f52a9cccU, 0x90849d53e224bc9U, + 0xeea10182f1ee8baU, 0xea37f59f30db9e9fU, 0x912c57d3a11b4fc5U, 0x1319fd95aefe4b12U, + 0xfdc74d103bf0c041U, 0x17b739b7302155eaU, 0xe05142e4e1fa4a1aU, 0x4d15f94409cf28f3U, + 0x300910f6ff26cf7fU, 0xf6cfe40224f0af0cU, 0x28dcc704f04ac738U, 0x1cfb17c2ea33c5c9U, + 0xb7fe161d5bc5df9cU, 0x2f641eddfab4184bU, 0x38f13b1dbf522ddcU, 0x37a76ffac046b25cU, + 0xc554cfc9e505fdddU, 0xdddaee22c357d1e8U, 0x1af9dbf10f632f1eU, 0xdbb3e3243dba2c31U, + 0x1ce0b010296c02a1U, 0x24eae7aec6c6a0f7U, 0xc228ae2062af08beU, 0xbf2f1a490fbad848U, + 0xdf1ede9fe1fdffbeU, 0x3cff81337926f037U, 0xbd335f3101c14aeU, 0xc613e5f1172243bcU, + 0xf8e91c11bc2bc0eeU, 0x3bc62b02c927b9f6U, 0x1bdbff8100f8abceU, 0x6c01be1c06311518U, + 0xdc03b4f6ecec904dU, 0xfe7b08f3bcd92e2cU, 0x67b1cad217f9c41bU, 0xfd33beeb01a38cdU, + 0xcb0899edaec4fefeU, 0x174ef85aa4c7c3aeU, 0xecbafa3e2ac92401U, 0xd31c91a50859da11U, + 0x3426d9d9eed7ffc9U, 0xe100fee9d913d4cdU, 0x4910301eb5e473d2U, 0xfb3113d1c90526beU, + 0xa2219fd040bef0aU, 0xf5db61f00cfc08f7U, 0xd7b11da212f6f2f0U, 0xe8240cd5074b0835U, + 0xb358c9e7e4a62e19U, 0xfbf4ef2e1d4a0231U, 0x1e1418e8f12ae0ffU, 0xf5ec16f2c0d71edcU, + 0xb41cb509d402fadeU, 0x1e0d4da96a992e1U, 0xac1df0cb1fe7d1adU, 0x30d3d6bad00381c4U, + 0x5cceedff603caf1U, 0x33e502db0cb3fbd2U, 0x31d4f4e4cfe801f6U, 0x2f54f3c2c71105d9U, + 0xf90028d79c3efdf9U, 0xcdc83cb4f74fbc0bU, 0xbfed1a922804431bU, 0x10d044c3b3abd58U, + 0xc53c09e20dd8dff2U, 0xeb1df91de749534bU, 0x3128decadbf8b3fcU, 0xf0a5e9f11ae724d0U, + 0x42aa73812c726e9U, 0x3bfb06e281e3d0f8U, 0xd710e34743dbc1dfU, 0xc5f2cbd221bef8c5U, + 0xf33af5d4b5f906ceU, 0xfc06c7f805f9d212U, 0xe034c62bcb051af8U, 0xd604ec0914254407U, + 0xffcc2d3d39e4b2c9U, 0x5bebfd1f0cfec5e1U, 0xbfd4afb701bbf9d2U, 0x17e6031700093fbcU, + 0x12f2e8b6d70ef237U, 0x2446d1d5f41332d3U, 0x690439fb3ff1073eU, 0xcd405efb03b1952U, + 0xea368f1faaab34caU, 0x203a3ce4e7cce5d8U, 0xe617152b27c218b8U, 0xfe271bf4e208acdbU, + 0xe1dde3d6c0c6d0e5U, 0xe8440bcd2c18c123U, 0xf7d11313c1330c81U, 0xfaec0894f8d33bU, + 0x8afffff2b8def9fbU, 0x24c9d804b7eb023aU, 0xd909e0b0f422112fU, 0xa58d0038e64413feU, + 0xf503acfcf30f3729U, 0xb41d4ebcc0debcaU, 0xcf0100f2a9fe535U, 0x117de2df1563ae0U, + 0xa7a7ddda14cb3321U, 0x3207f1bd9027250dU, 0x8145e8d82c2c6625U, 0xf237115113d6fafdU, + 0xc7f5fccbcf1fe751U, 0xec18d6f012f9b3f1U, 0xde0d2035f067712bU, 0xce33a405fe002d0fU, + 0xf82bf6334306d516U, 0x1fb62a2de81af6faU, 0xbc89121602db1ad4U, 0x27e3f838f3ecf81bU, + 0xac58d0e3e1f6ce13U, 0x245426e5f1271cf3U, 0x2beef2f23239ddcbU, 0xd3c45b3d33ec1f02U, + 0x432ad5199ebd0212U, 0xc608dcc3e2febfc5U, 0xa8d8c75a4bb428d5U, 0xc73b17ea9ae5e0eeU, + 0xc80ce6bce00128e0U, 0xa1b10f83721f4fdU, 0x7f0bda3b7102881U, 0x13c143092df3f5f2U, + 0x36f80340d9276119U, 0x3c1d67d5d0182323U, 0xbcbf12fdf739d3bcU, 0x31e2a2e190548ecU, + 0x42df21de3eff1af6U, 0xa1c28a950c6b018U, 0xbf217f05eec91107U, 0xe141dcccf0120fcdU, + 0x1feeb12de27f7e0U, 0xedd0f1bd025cdb31U, 0xe44a0413cdd50dedU, 0x15302639e011381fU, + 0xeee63fc3c2101678U, 0xfc9eedbf05f51024U, 0xc420cfd32e4332f9U, 0x3dfdda8ac045efe9U, + 0x850ad944b51cdff2U, 0xf131fcb005da28adU, 0xf4deed922a174116U, 0xf2a9a7e23858bb12U, + 0xfc4f1da01de401e8U, 0x341f0ab2c024fbe6U, 0x2fc22095f7fd748U, 0xd9040831daefa767U, + 0xbee8383f17bb0e0bU, 0x1f1f2fa788d60f0dU, 0xfaeaa23c62f8d4d9U, 0x5c06d80b09d7bbbcU, + 0xdacc3089f9fcadf9U, 0xc12affb74efcde8U, 0x2c19c8e8123518eeU, 0xdac138ee1ee3213cU, + 0x22fd2f1302f0180cU, 0xe511e7d5eade33dbU, 0xda1864e31f52b1beU, 0xede829fa14ed66e4U, + 0x45163b3a3436e9b1U, 0x95fafaba4ad2ea00U, 0xb0117f1289f15abdU, 0xf235bc82290e17f8U, + 0x150e130a3226abedU, 0xbe80f02095814ebU, 0x5d4228dce420cf13U, 0x34dff94ad82928bcU, + 0xe31c7914eb2418ebU, 0x4cf60f1df2de1e04U, 0x190206e62633fb0cU, 0x1519b324cf25d708U, + 0xfdcf9052fd3edbdU, 0xbbe32a021f16bfc0U, 0xeeea5170e2b16f1U, 0xe21ee802d80fa64cU, + 0xf22ceff002defdfaU, 0x16ee1035de1a373eU, 0xf9d9c5ed0af1e10cU, 0xe3161c7f210efcfbU, + 0x2f1bcfe52bcb1beeU, 0x25d9fbeceecf0ac5U, 0x2c5cb150fbee7f3U, 0xcc10f803ed30060cU, + 0x1104b4deeafcfac6U, 0x140c28d6c60eeefdU, 0xfa220cfebbae0ec0U, 0x26cbcb3df2df00f4U, + 0x320bebf62bf54e0aU, 0x622e1cc3affeb12U, 0xccc862d31858a5deU, 0xeed909d9d22416caU, + 0x27ef3b1fb51bf1c6U, 0xa11abc965fb49e53U, 0x98fc4e3bfd354007U, 0xfa11c781bd25ebd0U, + 0x5e1716402b3ac0cU, 0xdc1406401c291608U, 0x3bf716ffce40f220U, 0x530ce250f6c40522U, + 0xd4433f08cfc1b51cU, 0xf5db2302c2cd3629U, 0xea0ccc1d321fae3fU, 0xf08d332259c2275fU, + 0x460bf11e044c4f5eU, 0x10332cf5ef1f4731U, 0x5d02dfc2d4bcbe2U, 0xd7d335d9f73b74f6U, + 0x4f8241f4151123a5U, 0xb728f401141a8e04U, 0xadcc7e03cb0f3ca9U, 0x3839e2c1fa3416c0U, + 0x2508d704c52eb61eU, 0x3ad013f7127fe4f4U, 0x361141aabbe6660eU, 0x3310053306e3152bU, + 0xf4e035dd08c5f059U, 0xda91e3382ce8b83eU, 0xcfe898131a7aa02bU, 0x91ac515c42bfeafU, + 0xe2bd0b31f63d0c7U, 0xe3ed7f08a6eaed6cU, 0x4f8e8aa0509f136U, 0x165ebbc0f6e89707U, + 0x25febc85dcd4a1fU, 0xe8c93bf70620eb3cU, 0x812afb5203226d7U, 0xbfcb4d142cc0df32U, + 0xb5ef3f1d1a4b0ddbU, 0xa02a139138acad8U, 0xd22c8bddf1e99dabU, 0x1bccf9950fcdcebcU, + 0x4a00d1e5d52b42f9U, 0x3818cbd0035a0318U, 0x91022e4bede0186U, 0x4906ebb6b546bec0U, + 0xf02a1c211919bedbU, 0x75d320ef3dc2fd8U, 0xedf2c7edeac25b3cU, 0x1bbed112051af2f0U, + 0xf65fdbb4e61409dfU, 0x3c8fe16e31403e9U, 0x1fe6cc0c2952d3faU, 0xeec6024cf4ceea25U, + 0x25051e38e3053dedU, 0xbf5c1030ce8d81fU, 0xb4e0b512f2e71adbU, 0x2f135540c498bb15U, + 0x1fbaf1e5d438c8d8U, 0xfa3fe9cd1d0ef0f4U, 0xf6d6f0ccc9f9e481U, 0xdb0ed9341809fed2U, + 0xd6e3c43c418d58eeU, 0xe04d408fbfc08c6U, 0x2c11f363b7104417U, 0x9f1f93d21cdb5abU, + 0xddf22a40aa18e5ecU, 0xffe1263dc939297fU, 0xdd0eea2057d1081eU, 0x25e73450d7eae5deU, + 0xacb34f7dcf45a1fU, 0xd8dcd70b60f255d4U, 0x27ebf831e7f3c723U, 0x3211d7cec0322cdaU, + 0xb2f204f2e8efd71aU, 0xd3183f1793bd08f5U, 0xd117dfd10bfaae0eU, 0x6f02413fbf7c4dbU, + 0xe4111d34d9fab510U, 0x13d3ccfd02312038U, 0x7cb20affffc4ee2U, 0xf1f8f5d9f94d1827U, + 0x1efaab1e64ef8e6U, 0x21edcc04d3e9d8a5U, 0xf0dc141e11ecd924U, 0x928d0ed281a1845U, + 0xfe031535d83b0f1dU, 0xfe0a1a91f02ed618U, 0x8117e223290628e1U, 0xca04d52a08ec23eaU, + 0x2ed2e2272b03082dU, 0xcf3eccfa4fd3f63eU, 0xf72e1637345317edU, 0x11df4322cdd8f124U, + 0x4449da40ce310a6bU, 0xe312faffb8e9e91eU, 0x92d8372e24e2b903U, 0xcf939643e3459c3U, + 0x4fe831efd437c4caU, 0xdf0525b740c689f3U, 0xce387ff0c62b39c2U, 0x18262eb30efae1fbU, + 0x3aede3f32307d8cbU, 0x4e1930e5057e26feU, 0xf5484011d735095fU, 0xaf71d37251505dfU, + 0x2306540042ed1443U, 0x23abf9edf8e3ab47U, 0x1e1820473446b340U, 0x239e0cd0f1c35b37U, + 0xcf04c2ad5432a71U, 0xd8d60009b5030b3bU, 0x9ed70a450946f8c5U, 0xe9342144f71e7ed6U, + 0xfc9a63bfee031db9U, 0xb11af8b165ae9fd2U, 0xf1fb20c5e0122b02U, 0x1835cea82f0f25f5U, + 0x46e811b9fd30bdb8U, 0x1fdd2dec2e6d0bfeU, 0xe206525bac46a79U, 0x34ec23e5c6ad05e6U, + 0xb293cefe16e0c16U, 0x29a0ca23d2c6a828U, 0xb5ffb20e477fb642U, 0xf670e61019269617U, + 0xf1e03ed0d6e5b3caU, 0xf8cdfc8df61eecffU, 0x2e25bad8d2254d04U, 0x20f9c8e8fc2bde4dU, + 0x24244684ace5427U, 0x35170ef1fd1a132cU, 0x4346ac1521ef8158U, 0x901af2be5d1f922U, + 0xb8c0b7f2f1d61500U, 0x3a05fc32cbd2cae3U, 0xe5f0ac090dbd1895U, 0xe8fc09e31b38bdc8U, + 0x57f8d650f8b3b0e2U, 0xcf1e3e15ebcefd15U, 0x70e9145490b852d1U, 0x21d912fe4aab3a28U, + 0x714825ed1c69f303U, 0x3a26ff54aebcc8c8U, 0x4e74ce13401bfb6U, 0x2dd60e49271043e7U, + 0xf8a814fbfd0654cbU, 0xf5f51eda78bbbdbbU, 0xe5e701aeaa1e0f12U, 0x1c1bede9fccc3101U, + 0x24e1fd0028f089c1U, 0xe5de0f324823ee0dU, 0x3d1a4eb781edea3fU, 0x37260d520c2e6de7U, + 0x2cc072f8311d2a06U, 0xd9bbe444faf1202fU, 0x142bbbecd4e80551U, 0x4957030ed735efd8U, + 0xce46e2f2f5ec57f7U, 0xd0fe901de490436U, 0xffd42102e80d081dU, 0xc7255700f6de8133U, + 0xd225b70a32b0e800U, 0x18e2001dc2503df9U, 0xf5d8a2fbf22fd3efU, 0xca001f2df6e0dc1fU, + 0xd425fbb12a0eef05U, 0x47e4d7fdf6bee70fU, 0xe109f2529d6c6aaU, 0x12b7c7b326cfcbfcU, + 0xcaf9d9d223eb4324U, 0x3222d002c6061c05U, 0x70e43a500c1902f9U, 0x8a8ffffffe4U, + 0x8b300000b8dU, 0x1c8b00000c75U, 0xffffff71000004c2U, 0xfffffa54ffffeddbU, + 0xffffff700000077eU, 0x7000000661U, 0xffffdb9d00000c0fU, 0xfffffeea00000bfeU, + 0xfffff75f00000e01U, 0x1e6300001478U, 0x7880000060eU, 0x59de00001806U, + 0xfffffa19ffffcbf3U, 0xe26ffffff73U, 0x39dfffffcddU, 0xfe7b1e8d5d3e6e7U, + 0x9d0786c7f6ac22f8U, 0xbf231b43e3bc15deU, 0x322be5eebdbac9bdU, 0xd51c21352bad3bdbU, + 0xd4e493b0f0302f2cU, 0xdc37810d0ecb14bfU, 0xe0a0c1e0d4211a30U, 0x30d9353737363d3dU, + 0xdd071f2721fac208U, 0x3feb273602ede21eU, 0x1e0c3ddfcee711f6U, 0xfffff5c0000000d2U, + 0x2c5U, +}; + + +ai_handle g_sww_model_weights_table[1 + 2] = { + AI_HANDLE_PTR(AI_MAGIC_MARKER), + AI_HANDLE_PTR(s_sww_model_weights_array_u64), + AI_HANDLE_PTR(AI_MAGIC_MARKER), +}; + diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model_data_params.h b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model_data_params.h similarity index 83% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model_data_params.h rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model_data_params.h index 7660e01e..159ff204 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model_data_params.h +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model_data_params.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file sww_model_data_params.h * @author AST Embedded Analytics Research Platform - * @date 2025-01-19T06:26:52-0500 + * @date 2025-05-22T12:16:33-0700 * @brief AI Tool Automatic Code Generator for Embedded NN computing ****************************************************************************** * Copyright (c) 2025 STMicroelectronics. @@ -28,18 +28,18 @@ #define AI_SWW_MODEL_DATA_ACTIVATIONS_SIZES \ - { 5836, } -#define AI_SWW_MODEL_DATA_ACTIVATIONS_SIZE (5836) + { 10116, } +#define AI_SWW_MODEL_DATA_ACTIVATIONS_SIZE (10116) #define AI_SWW_MODEL_DATA_ACTIVATIONS_COUNT (1) -#define AI_SWW_MODEL_DATA_ACTIVATION_1_SIZE (5836) +#define AI_SWW_MODEL_DATA_ACTIVATION_1_SIZE (10116) #define AI_SWW_MODEL_DATA_WEIGHTS_SIZES \ - { 23520, } -#define AI_SWW_MODEL_DATA_WEIGHTS_SIZE (23520) + { 49412, } +#define AI_SWW_MODEL_DATA_WEIGHTS_SIZE (49412) #define AI_SWW_MODEL_DATA_WEIGHTS_COUNT (1) -#define AI_SWW_MODEL_DATA_WEIGHT_1_SIZE (23520) +#define AI_SWW_MODEL_DATA_WEIGHT_1_SIZE (49412) diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model_generate_report.txt b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model_generate_report.txt new file mode 100644 index 00000000..bc2ee81a --- /dev/null +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/App/sww_model_generate_report.txt @@ -0,0 +1,240 @@ +ST Edge AI Core v1.0.0-19899 +Created date : 2025-05-22 12:16:33 +Parameters : generate --target stm32l4 --name sww_model -m /Users/jeremy/dev/tiny_mlperf/tiny_main/benchmark/training/streaming_wakeword/trained_models/str_ww_ref_model.tflite --compression none --verbosity 1 --allocate-inputs -O time --allocate-outputs --workspace /var/folders/qb/jcjkm0nx4878vyqfjy786xdh0000gn/T/mxAI_workspace2020273003412510607421672881177677 --output /Users/jeremy/.stm32cubemx/sww_model_output + +Exec/report summary (generate) +---------------------------------------------------------------------------------------------------------------------------------------------- +model file : /Users/jeremy/dev/tiny_mlperf/tiny_main/benchmark/training/streaming_wakeword/trained_models/str_ww_ref_model.tflite +type : tflite +c_name : sww_model +compression : none +options : allocate-inputs, allocate-outputs +optimization : time +target/series : stm32l4 +workspace dir : /var/folders/qb/jcjkm0nx4878vyqfjy786xdh0000gn/T/mxAI_workspace2020273003412510607421672881177677 +output dir : /Users/jeremy/.stm32cubemx/sww_model_output +model_fmt : ss/sa per channel +model_name : str_ww_ref_model +model_hash : 0x9643512e0b8a0b6e643e70c2fec496ee +params # : 46,883 items (48.25 KiB) +---------------------------------------------------------------------------------------------------------------------------------------------- +input 1/1 : 'serving_default_input_10', int8(1x30x1x40), 1.17 KBytes, QLinear(0.003701043,-128,int8), activations +output 1/1 : 'nl_10', int8(1x3), 3 Bytes, QLinear(0.003906250,-128,int8), activations +macc : 827,256 +weights (ro) : 49,412 B (48.25 KiB) (1 segment) / -138,120(-73.7%) vs float model +activations (rw) : 10,116 B (9.88 KiB) (1 segment) * +ram (total) : 10,116 B (9.88 KiB) = 10,116 + 0 + 0 +---------------------------------------------------------------------------------------------------------------------------------------------- +(*) 'input'/'output' buffers can be used from the activations buffer + +Model name - str_ww_ref_model +------ ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- --------------- ----------------- --------------------- +m_id layer (type,original) oshape param/size macc connected to | c_size c_macc c_type +------ ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- --------------- ----------------- --------------------- +0 serving_default_input_10 (Input, ) [b:1,h:30,w:1,c:40] | +280(+100.0%) +3,400(+100.0%) Conv2D_[0] + conv2d_0 (Conv2D, DEPTHWISE_CONV_2D) [b:1,h:28,w:1,c:40] 160/280 3,400 serving_default_input_10 | -280(-100.0%) -3,400(-100.0%) +------ ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- --------------- ----------------- --------------------- +1 conv2d_1 (Conv2D, CONV_2D) [b:1,h:28,w:1,c:128] 5,248/5,632 143,488 conv2d_0 | Conv2D_[1] + nl_1_nl (Nonlinearity, CONV_2D) [b:1,h:28,w:1,c:128] 3,584 conv2d_1 | -3,584(-100.0%) +------ ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- --------------- ----------------- --------------------- +2 conv2d_2 (Conv2D, DEPTHWISE_CONV_2D) [b:1,h:24,w:1,c:128] 768/1,152 15,488 nl_1_nl | Conv2D_[2] +------ ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- --------------- ----------------- --------------------- +3 conv2d_3 (Conv2D, CONV_2D) [b:1,h:24,w:1,c:128] 16,512/16,896 393,344 conv2d_2 | Conv2D_[3] + nl_3_nl (Nonlinearity, CONV_2D) [b:1,h:24,w:1,c:128] 3,072 conv2d_3 | -3,072(-100.0%) +------ ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- --------------- ----------------- --------------------- +4 conv2d_4 (Conv2D, DEPTHWISE_CONV_2D) [b:1,h:15,w:1,c:128] 1,408/1,792 19,328 nl_3_nl | Conv2D_[4] +------ ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- --------------- ----------------- --------------------- +5 conv2d_5 (Conv2D, CONV_2D) [b:1,h:15,w:1,c:128] 16,512/16,896 245,888 conv2d_4 | Conv2D_[5] + nl_5_nl (Nonlinearity, CONV_2D) [b:1,h:15,w:1,c:128] 1,920 conv2d_5 | -1,920(-100.0%) +------ ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- --------------- ----------------- --------------------- +6 conv2d_6 (Conv2D, DEPTHWISE_CONV_2D) [b:1,h:1,w:1,c:128] 2,048/2,432 2,048 nl_5_nl | Conv2D_[6] +------ ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- --------------- ----------------- --------------------- +7 conv2d_7 (Conv2D, CONV_2D) [b:1,h:1,w:1,c:32] 4,128/4,224 4,128 conv2d_6 | Conv2D_[7] + nl_7_nl (Nonlinearity, CONV_2D) [b:1,h:1,w:1,c:32] 32 conv2d_7 | -32(-100.0%) +------ ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- --------------- ----------------- --------------------- +8 reshape_8 (Reshape, RESHAPE) [b:1,c:32] nl_7_nl | +------ ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- --------------- ----------------- --------------------- +9 model_dense_MatMul (Placeholder, ) [h:3,c:32] 96/96 | +12(+12.5%) +99(+100.0%) Dense_[8] + model_dense_BiasAdd_ReadVariableOp (Placeholder, ) [c:3] 3/12 | -12(-100.0%) + gemm_9 (Gemm, FULLY_CONNECTED) [b:1,c:3] 99 reshape_8 | -99(-100.0%) + model_dense_MatMul | + model_dense_BiasAdd_ReadVariableOp | +------ ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- --------------- ----------------- --------------------- +10 nl_10 (Nonlinearity, SOFTMAX) [b:1,c:3] 45 gemm_9 | Nonlinearity_[o][9] +------ ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- --------------- ----------------- --------------------- +model/c-model: macc=835,864/827,256 -8,608(-1.0%) weights=49,412/49,412 activations=--/10,116 io=--/0 + + + +Generated C-graph summary +------------------------------------------------------------------------------------------------------------------------ +model name : str_ww_ref_model +c-name : sww_model +c-node # : 10 +c-array # : 39 +activations size : 10116 (1 segment) +weights size : 49412 (1 segment) +macc : 827256 +inputs : ['serving_default_input_10_output'] +outputs : ['nl_10_output'] + +C-Arrays (39) +------ --------------------------------- ------------- ------------------------- ----------- --------- +c_id name (*_array) item/size domain/mem-pool c-type comment +------ --------------------------------- ------------- ------------------------- ----------- --------- +0 conv2d_0_bias 40/160 weights/weights const s32 +1 conv2d_0_output 1120/1120 activations/**default** s8 +2 conv2d_0_scratch0 761/761 activations/**default** s8 +3 conv2d_0_weights 120/120 weights/weights const s8 +4 conv2d_1_bias 128/512 weights/weights const s32 +5 conv2d_1_output 3584/3584 activations/**default** s8 +6 conv2d_1_scratch0 1440/1440 activations/**default** s8 +7 conv2d_1_weights 5120/5120 weights/weights const s8 +8 conv2d_2_bias 128/512 weights/weights const s32 +9 conv2d_2_output 3072/3072 activations/**default** s8 +10 conv2d_2_scratch0 3201/3201 activations/**default** s8 +11 conv2d_2_weights 640/640 weights/weights const s8 +12 conv2d_3_bias 128/512 weights/weights const s32 +13 conv2d_3_output 3072/3072 activations/**default** s8 +14 conv2d_3_scratch0 1792/1792 activations/**default** s8 +15 conv2d_3_weights 16384/16384 weights/weights const s8 +16 conv2d_4_bias 128/512 weights/weights const s32 +17 conv2d_4_output 1920/1920 activations/**default** s8 +18 conv2d_4_scratch0 5121/5121 activations/**default** s8 +19 conv2d_4_weights 1280/1280 weights/weights const s8 +20 conv2d_5_bias 128/512 weights/weights const s32 +21 conv2d_5_output 1920/1920 activations/**default** s8 +22 conv2d_5_scratch0 1792/1792 activations/**default** s8 +23 conv2d_5_weights 16384/16384 weights/weights const s8 +24 conv2d_6_bias 128/512 weights/weights const s32 +25 conv2d_6_output 128/128 activations/**default** s8 +26 conv2d_6_scratch0 7041/7041 activations/**default** s8 +27 conv2d_6_weights 1920/1920 weights/weights const s8 +28 conv2d_7_bias 32/128 weights/weights const s32 +29 conv2d_7_output 32/32 activations/**default** s8 +30 conv2d_7_scratch0 832/832 activations/**default** s8 +31 conv2d_7_weights 4096/4096 weights/weights const s8 +32 gemm_9_bias 3/12 weights/weights const s32 +33 gemm_9_output 3/3 activations/**default** s8 +34 gemm_9_scratch0 32/64 activations/**default** s16 +35 gemm_9_weights 96/96 weights/weights const s8 +36 nl_10_output 3/3 activations/**default** s8 /output +37 nl_10_scratch0 124/496 activations/**default** s32 +38 serving_default_input_10_output 1200/1200 activations/**default** s8 /input +------ --------------------------------- ------------- ------------------------- ----------- --------- + +C-Layers (10) +------ ---------------- ---- --------------- -------- ------- ------------------------------------ ------------------------ +c_id name (*_layer) id layer_type macc rom tensors shape (array id) +------ ---------------- ---- --------------- -------- ------- ------------------------------------ ------------------------ +0 conv2d_0 0 Conv2D 3400 280 I: serving_default_input_10_output int8(1x30x1x40) (38) + S: conv2d_0_scratch0 + W: conv2d_0_weights int8(1x3x1x40) (3) + W: conv2d_0_bias int32(40) (0) + O: conv2d_0_output int8(1x28x1x40) (1) +------ ---------------- ---- --------------- -------- ------- ------------------------------------ ------------------------ +1 conv2d_1 1 Conv2D 143488 5632 I: conv2d_0_output int8(1x28x1x40) (1) + S: conv2d_1_scratch0 + W: conv2d_1_weights int8(128x1x1x40) (7) + W: conv2d_1_bias int32(128) (4) + O: conv2d_1_output int8(1x28x1x128) (5) +------ ---------------- ---- --------------- -------- ------- ------------------------------------ ------------------------ +2 conv2d_2 2 Conv2D 15488 1152 I: conv2d_1_output int8(1x28x1x128) (5) + S: conv2d_2_scratch0 + W: conv2d_2_weights int8(1x5x1x128) (11) + W: conv2d_2_bias int32(128) (8) + O: conv2d_2_output int8(1x24x1x128) (9) +------ ---------------- ---- --------------- -------- ------- ------------------------------------ ------------------------ +3 conv2d_3 3 Conv2D 393344 16896 I: conv2d_2_output int8(1x24x1x128) (9) + S: conv2d_3_scratch0 + W: conv2d_3_weights int8(128x1x1x128) (15) + W: conv2d_3_bias int32(128) (12) + O: conv2d_3_output int8(1x24x1x128) (13) +------ ---------------- ---- --------------- -------- ------- ------------------------------------ ------------------------ +4 conv2d_4 4 Conv2D 19328 1792 I: conv2d_3_output int8(1x24x1x128) (13) + S: conv2d_4_scratch0 + W: conv2d_4_weights int8(1x10x1x128) (19) + W: conv2d_4_bias int32(128) (16) + O: conv2d_4_output int8(1x15x1x128) (17) +------ ---------------- ---- --------------- -------- ------- ------------------------------------ ------------------------ +5 conv2d_5 5 Conv2D 245888 16896 I: conv2d_4_output int8(1x15x1x128) (17) + S: conv2d_5_scratch0 + W: conv2d_5_weights int8(128x1x1x128) (23) + W: conv2d_5_bias int32(128) (20) + O: conv2d_5_output int8(1x15x1x128) (21) +------ ---------------- ---- --------------- -------- ------- ------------------------------------ ------------------------ +6 conv2d_6 6 Conv2D 2048 2432 I: conv2d_5_output int8(1x15x1x128) (21) + S: conv2d_6_scratch0 + W: conv2d_6_weights int8(1x15x1x128) (27) + W: conv2d_6_bias int32(128) (24) + O: conv2d_6_output int8(1x1x1x128) (25) +------ ---------------- ---- --------------- -------- ------- ------------------------------------ ------------------------ +7 conv2d_7 7 Conv2D 4128 4224 I: conv2d_6_output int8(1x1x1x128) (25) + S: conv2d_7_scratch0 + W: conv2d_7_weights int8(32x1x1x128) (31) + W: conv2d_7_bias int32(32) (28) + O: conv2d_7_output int8(1x1x1x32) (29) +------ ---------------- ---- --------------- -------- ------- ------------------------------------ ------------------------ +8 gemm_9 9 Dense 99 108 I: conv2d_7_output int8(1x1x1x32) (29) + S: gemm_9_scratch0 + W: gemm_9_weights int8(3x32) (35) + W: gemm_9_bias int32(3) (32) + O: gemm_9_output int8(1x3) (33) +------ ---------------- ---- --------------- -------- ------- ------------------------------------ ------------------------ +9 nl_10 10 Nonlinearity 45 0 I: gemm_9_output int8(1x3) (33) + S: nl_10_scratch0 + O: nl_10_output int8(1x3) (36) +------ ---------------- ---- --------------- -------- ------- ------------------------------------ ------------------------ + + + +Number of operations per c-layer +------- ------ ---------------------- --------- ------------ +c_id m_id name (type) #op type +------- ------ ---------------------- --------- ------------ +0 0 conv2d_0 (Conv2D) 3,400 smul_s8_s8 +1 1 conv2d_1 (Conv2D) 143,488 smul_s8_s8 +2 2 conv2d_2 (Conv2D) 15,488 smul_s8_s8 +3 3 conv2d_3 (Conv2D) 393,344 smul_s8_s8 +4 4 conv2d_4 (Conv2D) 19,328 smul_s8_s8 +5 5 conv2d_5 (Conv2D) 245,888 smul_s8_s8 +6 6 conv2d_6 (Conv2D) 2,048 smul_s8_s8 +7 7 conv2d_7 (Conv2D) 4,128 smul_s8_s8 +8 9 gemm_9 (Dense) 99 smul_s8_s8 +9 10 nl_10 (Nonlinearity) 45 op_s8_s8 +------- ------ ---------------------- --------- ------------ +total 827,256 + +Number of operation types +---------------- --------- ----------- +operation type # % +---------------- --------- ----------- +smul_s8_s8 827,211 100.0% +op_s8_s8 45 0.0% + +Complexity report (model) +------ -------------------------- ------------------------- ------------------------- ------ +m_id name c_macc c_rom c_id +------ -------------------------- ------------------------- ------------------------- ------ +0 serving_default_input_10 | 0.4% | 0.6% [0] +1 conv2d_1 |||||| 17.3% |||||| 11.4% [1] +2 conv2d_2 | 1.9% || 2.3% [2] +3 conv2d_3 |||||||||||||||| 47.5% |||||||||||||||| 34.2% [3] +4 conv2d_4 | 2.3% || 3.6% [4] +5 conv2d_5 |||||||||| 29.7% |||||||||||||||| 34.2% [5] +6 conv2d_6 | 0.2% ||| 4.9% [6] +7 conv2d_7 | 0.5% |||| 8.5% [7] +9 model_dense_MatMul | 0.0% | 0.2% [8] +10 nl_10 | 0.0% | 0.0% [9] +------ -------------------------- ------------------------- ------------------------- ------ +macc=827,256 weights=49,412 act=10,116 ram_io=0 + +Generated files (7) +--------------------------------------------------------------------- +/Users/jeremy/.stm32cubemx/sww_model_output/sww_model_data_params.h +/Users/jeremy/.stm32cubemx/sww_model_output/sww_model_data_params.c +/Users/jeremy/.stm32cubemx/sww_model_output/sww_model_data.h +/Users/jeremy/.stm32cubemx/sww_model_output/sww_model_data.c +/Users/jeremy/.stm32cubemx/sww_model_output/sww_model_config.h +/Users/jeremy/.stm32cubemx/sww_model_output/sww_model.h +/Users/jeremy/.stm32cubemx/sww_model_output/sww_model.c diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/LICENSE.txt b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/LICENSE.txt similarity index 100% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/LICENSE.txt rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/X-CUBE-AI/LICENSE.txt diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/sww_testing_l4r5zi.launch b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/sww_ref_l4r5zi Debug.launch similarity index 92% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/sww_testing_l4r5zi.launch rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/sww_ref_l4r5zi Debug.launch index ac9e3e16..f013a7e5 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/sww_testing_l4r5zi.launch +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/sww_ref_l4r5zi Debug.launch @@ -2,19 +2,17 @@ - - - + @@ -34,7 +32,7 @@ - + @@ -69,13 +67,13 @@ - - + + - + - + diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/sww_testing_l4r5zi.ioc b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/sww_ref_l4r5zi.ioc similarity index 81% rename from benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/sww_testing_l4r5zi.ioc rename to benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/sww_ref_l4r5zi.ioc index 476c0c87..6d6b1a30 100644 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/sww_testing_l4r5zi.ioc +++ b/benchmark/reference_submissions/streaming_wakeword/sww_ref_l4r5zi/sww_ref_l4r5zi.ioc @@ -26,7 +26,7 @@ GPIO.groupedBy=Group By Peripherals KeepUserPlacement=false LPUART1.BaudRate=115200 LPUART1.IPParameters=BaudRate,WordLength,StopBits -LPUART1.StopBits=UART_STOPBITS_2 +LPUART1.StopBits=UART_STOPBITS_1 LPUART1.WordLength=UART_WORDLENGTH_8B Mcu.CPN=STM32L4R5ZIT6 Mcu.Family=STM32L4 @@ -36,40 +36,44 @@ Mcu.IP2=NVIC Mcu.IP3=RCC Mcu.IP4=SAI1 Mcu.IP5=SYS -Mcu.IP6=USART3 -Mcu.IP7=USB_OTG_FS -Mcu.IPNb=8 +Mcu.IP6=TIM16 +Mcu.IP7=USART3 +Mcu.IP8=USB_OTG_FS +Mcu.IPNb=9 Mcu.Name=STM32L4R5Z(G-I)Tx Mcu.Package=LQFP144 Mcu.Pin0=PE4 Mcu.Pin1=PE5 -Mcu.Pin10=PD9 -Mcu.Pin11=PG5 -Mcu.Pin12=PG6 -Mcu.Pin13=PG7 -Mcu.Pin14=PG8 -Mcu.Pin15=PA8 -Mcu.Pin16=PA9 -Mcu.Pin17=PA10 -Mcu.Pin18=PA11 -Mcu.Pin19=PA12 +Mcu.Pin10=PB14 +Mcu.Pin11=PD8 +Mcu.Pin12=PD9 +Mcu.Pin13=PG5 +Mcu.Pin14=PG6 +Mcu.Pin15=PG7 +Mcu.Pin16=PG8 +Mcu.Pin17=PA8 +Mcu.Pin18=PA9 +Mcu.Pin19=PA10 Mcu.Pin2=PE6 -Mcu.Pin20=PA13 (JTMS/SWDIO) -Mcu.Pin21=PA14 (JTCK/SWCLK) -Mcu.Pin22=PB3 (JTDO/TRACESWO) -Mcu.Pin23=PB7 -Mcu.Pin24=PB8 -Mcu.Pin25=VP_SAI1_VP_$IpInstance_SAIA_SAI_BASIC -Mcu.Pin26=VP_SYS_VS_Systick -Mcu.Pin27=VP_STMicroelectronics.X-CUBE-AI_VS_ArtificialOoIntelligenceJjXAaCUBEAaAI_9.1.0 +Mcu.Pin20=PA11 +Mcu.Pin21=PA12 +Mcu.Pin22=PA13 (JTMS/SWDIO) +Mcu.Pin23=PA14 (JTCK/SWCLK) +Mcu.Pin24=PB3 (JTDO/TRACESWO) +Mcu.Pin25=PB7 +Mcu.Pin26=PB8 +Mcu.Pin27=VP_SAI1_VP_$IpInstance_SAIA_SAI_BASIC +Mcu.Pin28=VP_SYS_VS_Systick +Mcu.Pin29=VP_TIM16_VS_ClockSourceINT Mcu.Pin3=PC13 +Mcu.Pin30=VP_STMicroelectronics.X-CUBE-AI_VS_ArtificialOoIntelligenceJjXAaCUBEAaAI_9.1.0 Mcu.Pin4=PC14-OSC32_IN (PC14) Mcu.Pin5=PC15-OSC32_OUT (PC15) Mcu.Pin6=PH0-OSC_IN (PH0) Mcu.Pin7=PH1-OSC_OUT (PH1) -Mcu.Pin8=PB14 -Mcu.Pin9=PD8 -Mcu.PinsNb=28 +Mcu.Pin8=PF13 +Mcu.Pin9=PE9 +Mcu.PinsNb=31 Mcu.ThirdParty0=STMicroelectronics.X-CUBE-AI.9.1.0 Mcu.ThirdPartyNb=1 Mcu.UserConstants= @@ -136,9 +140,10 @@ PB7.GPIOParameters=GPIO_Label PB7.GPIO_Label=LD2 [Blue] PB7.Locked=true PB7.Signal=GPIO_Output -PB8.GPIOParameters=GPIO_Label -PB8.GPIO_Label=PIN_WW_DETECTED +PB8.GPIOParameters=PinState,GPIO_Label +PB8.GPIO_Label=WW_DETECTED PB8.Locked=true +PB8.PinState=GPIO_PIN_SET PB8.Signal=GPIO_Output PC13.GPIOParameters=GPIO_Label PC13.GPIO_Label=B1 @@ -172,6 +177,19 @@ PE6.GPIOParameters=GPIO_PuPd PE6.GPIO_PuPd=GPIO_PULLUP PE6.Mode=SAI_A_AsyncSlave PE6.Signal=SAI1_SD_A +PE9.GPIOParameters=GPIO_Speed,PinState,GPIO_Label,GPIO_ModeDefaultOutputPP +PE9.GPIO_Label=Processing +PE9.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_PP +PE9.GPIO_Speed=GPIO_SPEED_FREQ_MEDIUM +PE9.Locked=true +PE9.PinState=GPIO_PIN_RESET +PE9.Signal=GPIO_Output +PF13.GPIOParameters=GPIO_Speed,PinState,GPIO_Label +PF13.GPIO_Label=timestamp +PF13.GPIO_Speed=GPIO_SPEED_FREQ_MEDIUM +PF13.Locked=true +PF13.PinState=GPIO_PIN_SET +PF13.Signal=GPIO_Output PG5.GPIOParameters=GPIO_Label PG5.GPIO_Label=USB_OverCurrent [STMPS2151STR_FAULT] PG5.Locked=true @@ -213,10 +231,10 @@ ProjectManager.LastFirmware=true ProjectManager.LibraryCopy=1 ProjectManager.MainLocation=Core/Src ProjectManager.NoMain=false -ProjectManager.PreviousToolchain= +ProjectManager.PreviousToolchain=STM32CubeIDE ProjectManager.ProjectBuild=false -ProjectManager.ProjectFileName=sww_testing_l4r5zi.ioc -ProjectManager.ProjectName=sww_testing_l4r5zi +ProjectManager.ProjectFileName=sww_ref_l4r5zi.ioc +ProjectManager.ProjectName=sww_ref_l4r5zi ProjectManager.ProjectStructure= ProjectManager.RegisterCallBack= ProjectManager.StackSize=0x800 @@ -225,7 +243,7 @@ ProjectManager.ToolChainLocation= ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_LPUART1_UART_Init-LPUART1-false-HAL-true,5-MX_USART3_UART_Init-USART3-false-HAL-true,6-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,7-MX_SAI1_Init-SAI1-false-HAL-true +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_LPUART1_UART_Init-LPUART1-false-HAL-true,5-MX_USART3_UART_Init-USART3-false-HAL-true,6-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,7-MX_SAI1_Init-SAI1-false-HAL-true,8-MX_TIM16_Init-TIM16-false-HAL-true RCC.48MHZClocksFreq_Value=24000000 RCC.ADC12outputFreq_Value=72000000 RCC.ADC34outputFreq_Value=72000000 @@ -345,32 +363,33 @@ SAI1.VirtualMode-SAI_A_AsyncSlave=VM_SLAVE SAI1.VirtualProtocol-SAI_A_BASIC=VM_BASIC_PROTOCOL SH.GPXTI13.0=GPIO_EXTI13 SH.GPXTI13.ConfNb=1 -STMicroelectronics.X-CUBE-AI.9.1.0.ActivationBufferSizeList=5836 +STMicroelectronics.X-CUBE-AI.9.1.0.ActivationBufferSizeList=10116 STMicroelectronics.X-CUBE-AI.9.1.0.ActivationBuffers=pool0 STMicroelectronics.X-CUBE-AI.9.1.0.ActivationNames=pool0 STMicroelectronics.X-CUBE-AI.9.1.0.ActivationSizes=AI_SWW_MODEL_DATA_ACTIVATION_1_SIZE STMicroelectronics.X-CUBE-AI.9.1.0.ArtificialOoIntelligenceJjXAaCUBEAaAI_Checked=true STMicroelectronics.X-CUBE-AI.9.1.0.HeapSize=0x800 -STMicroelectronics.X-CUBE-AI.9.1.0.IPParameters=HeapSize,StackSize,ReadyForCodeGeneration,ModelName-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,ModelKind-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,ModelCompression-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,ModelHashList,ModelNameList,WorkingBufferStartAddrList,LatestDirectoryUsed-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,ModelStructureFile-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,ModelActualCompression-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,ModelFlashOccupation-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,ModelMacc-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,ModelRamOccupation-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,ModelType-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,copyWeightToRam,outputDirectory,useInputAllocation,useOutputAllocation,customLayerConfigEnabled,noOnnxIoTranspose,ActivationBuffers,ActivationSizes,ActivationNames,InternalRamActivationBufferMaxSize,ActivationBufferSizeList,MaximumNumberOfInputLayer,MaximumNumberOfOutputLayer,MaximumSizeOfInputLayer,MaximumSizeOfOutputLayer,copyWeightToRam-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,useInputAllocation-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,useOutputAllocation-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,customLayerConfigEnabled-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,noOnnxIoTranspose-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,XAaCUBEAaAICcArtificialOoIntelligenceJjCore +STMicroelectronics.X-CUBE-AI.9.1.0.IPParameters=HeapSize,StackSize,ReadyForCodeGeneration,ModelName-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,ModelKind-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,ModelCompression-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,ModelHashList,ModelNameList,WorkingBufferStartAddrList,LatestDirectoryUsed-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,ModelActualCompression-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,ModelFlashOccupation-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,ModelMacc-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,ModelRamOccupation-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,ModelType-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,copyWeightToRam,outputDirectory,useInputAllocation,useOutputAllocation,customLayerConfigEnabled,noOnnxIoTranspose,ActivationBuffers,ActivationSizes,ActivationNames,InternalRamActivationBufferMaxSize,ActivationBufferSizeList,MaximumNumberOfInputLayer,MaximumNumberOfOutputLayer,MaximumSizeOfInputLayer,MaximumSizeOfOutputLayer,copyWeightToRam-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,useInputAllocation-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,useOutputAllocation-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,customLayerConfigEnabled-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,noOnnxIoTranspose-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,ValidationInputFileHistory-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,ModelStructureFile-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,optimization-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284,XAaCUBEAaAICcArtificialOoIntelligenceJjCore STMicroelectronics.X-CUBE-AI.9.1.0.InternalRamActivationBufferMaxSize=AI_SWW_MODEL_DATA_ACTIVATIONS_SIZE -STMicroelectronics.X-CUBE-AI.9.1.0.LatestDirectoryUsed-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284=/Users/jeremy/dev/tiny_mlperf/tiny_jhsyn/benchmark/training/streaming_wakeword/trained_models +STMicroelectronics.X-CUBE-AI.9.1.0.LatestDirectoryUsed-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284=/Users/jeremy/dev/tiny_mlperf/tiny_main/benchmark/training/streaming_wakeword/trained_models STMicroelectronics.X-CUBE-AI.9.1.0.MaximumNumberOfInputLayer=1 STMicroelectronics.X-CUBE-AI.9.1.0.MaximumNumberOfOutputLayer=1 STMicroelectronics.X-CUBE-AI.9.1.0.MaximumSizeOfInputLayer=1 STMicroelectronics.X-CUBE-AI.9.1.0.MaximumSizeOfOutputLayer=1 STMicroelectronics.X-CUBE-AI.9.1.0.ModelActualCompression-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284=0.0 STMicroelectronics.X-CUBE-AI.9.1.0.ModelCompression-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284=None -STMicroelectronics.X-CUBE-AI.9.1.0.ModelFlashOccupation-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284=23520 +STMicroelectronics.X-CUBE-AI.9.1.0.ModelFlashOccupation-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284=49412 STMicroelectronics.X-CUBE-AI.9.1.0.ModelHashList=2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284 STMicroelectronics.X-CUBE-AI.9.1.0.ModelKind-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284=TFLITE -STMicroelectronics.X-CUBE-AI.9.1.0.ModelMacc-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284=652551 +STMicroelectronics.X-CUBE-AI.9.1.0.ModelMacc-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284=827256 STMicroelectronics.X-CUBE-AI.9.1.0.ModelName-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284=sww_model STMicroelectronics.X-CUBE-AI.9.1.0.ModelNameList=sww_model -STMicroelectronics.X-CUBE-AI.9.1.0.ModelRamOccupation-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284=5836 -STMicroelectronics.X-CUBE-AI.9.1.0.ModelStructureFile-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284=/Users/jeremy/dev/tiny_mlperf/tiny_jhsyn/benchmark/training/streaming_wakeword/trained_models/strm_ww_int8.tflite +STMicroelectronics.X-CUBE-AI.9.1.0.ModelRamOccupation-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284=10116 +STMicroelectronics.X-CUBE-AI.9.1.0.ModelStructureFile-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284=/Users/jeremy/dev/tiny_mlperf/tiny_main/benchmark/training/streaming_wakeword/trained_models/str_ww_ref_model.tflite STMicroelectronics.X-CUBE-AI.9.1.0.ModelType-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284=STM32Cube.AI MCU runtime STMicroelectronics.X-CUBE-AI.9.1.0.ReadyForCodeGeneration=true STMicroelectronics.X-CUBE-AI.9.1.0.StackSize=0x800 +STMicroelectronics.X-CUBE-AI.9.1.0.ValidationInputFileHistory-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284=/Users/jeremy/dev/tiny_mlperf/tiny_main/benchmark/training/streaming_wakeword/med_wav_2m_8p_specgram.npz STMicroelectronics.X-CUBE-AI.9.1.0.WorkingBufferStartAddrList=0xFFFFFFFF STMicroelectronics.X-CUBE-AI.9.1.0.XAaCUBEAaAICcArtificialOoIntelligenceJjCore=true STMicroelectronics.X-CUBE-AI.9.1.0.copyWeightToRam=false @@ -379,12 +398,15 @@ STMicroelectronics.X-CUBE-AI.9.1.0.customLayerConfigEnabled=false STMicroelectronics.X-CUBE-AI.9.1.0.customLayerConfigEnabled-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284=false STMicroelectronics.X-CUBE-AI.9.1.0.noOnnxIoTranspose=false STMicroelectronics.X-CUBE-AI.9.1.0.noOnnxIoTranspose-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284=false +STMicroelectronics.X-CUBE-AI.9.1.0.optimization-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284=time STMicroelectronics.X-CUBE-AI.9.1.0.outputDirectory=/Users/jeremy/.stm32cubemx/sww_model_output STMicroelectronics.X-CUBE-AI.9.1.0.useInputAllocation=true STMicroelectronics.X-CUBE-AI.9.1.0.useInputAllocation-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284=true STMicroelectronics.X-CUBE-AI.9.1.0.useOutputAllocation=true STMicroelectronics.X-CUBE-AI.9.1.0.useOutputAllocation-2c55a473fe2cb7c748ffe10757a75eb16c549e0110a52bf4822234593712c284=true STMicroelectronics.X-CUBE-AI.9.1.0_SwParameter=XAaCUBEAaAICcArtificialOoIntelligenceJjCore\:true; +TIM16.IPParameters=Prescaler +TIM16.Prescaler=120-1 USART3.IPParameters=VirtualMode-Asynchronous USART3.VirtualMode-Asynchronous=VM_ASYNC USB_OTG_FS.IPParameters=VirtualMode @@ -395,6 +417,8 @@ VP_STMicroelectronics.X-CUBE-AI_VS_ArtificialOoIntelligenceJjXAaCUBEAaAI_9.1.0.M VP_STMicroelectronics.X-CUBE-AI_VS_ArtificialOoIntelligenceJjXAaCUBEAaAI_9.1.0.Signal=STMicroelectronics.X-CUBE-AI_VS_ArtificialOoIntelligenceJjXAaCUBEAaAI_9.1.0 VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_TIM16_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM16_VS_ClockSourceINT.Signal=TIM16_VS_ClockSourceINT board=NUCLEO-L4R5ZI boardIOC=true isbadioc=false diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.ai/sww_model_null_c_graph.json b/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.ai/sww_model_null_c_graph.json deleted file mode 100644 index 613d1d86..00000000 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.ai/sww_model_null_c_graph.json +++ /dev/null @@ -1,2812 +0,0 @@ -{ - "activations": { - "heap_overlay_pool": { - "activation_alignment": 4, - "buffer_data_size": 0, - "buffer_offsets": [ - { - "buffer_name": "serving_default_input_10_output_array", - "offset": 2160, - "size": 1200 - }, - { - "buffer_name": "conv2d_0_output_array", - "offset": 2120, - "size": 1120 - }, - { - "buffer_name": "conv2d_1_output_array", - "offset": 108, - "size": 3024 - }, - { - "buffer_name": "conv2d_2_output_array", - "offset": 0, - "size": 2592 - }, - { - "buffer_name": "conv2d_3_output_array", - "offset": 3836, - "size": 1944 - }, - { - "buffer_name": "conv2d_4_output_array", - "offset": 3752, - "size": 1215 - }, - { - "buffer_name": "conv2d_5_output_array", - "offset": 844, - "size": 780 - }, - { - "buffer_name": "conv2d_6_output_array", - "offset": 0, - "size": 52 - }, - { - "buffer_name": "conv2d_7_output_array", - "offset": 580, - "size": 32 - }, - { - "buffer_name": "gemm_9_output_array", - "offset": 64, - "size": 3 - }, - { - "buffer_name": "nl_10_output_array", - "offset": 0, - "size": 3 - }, - { - "buffer_name": "conv2d_0_scratch0_array", - "offset": 3360, - "size": 761 - }, - { - "buffer_name": "conv2d_1_scratch0_array", - "offset": 3240, - "size": 1240 - }, - { - "buffer_name": "conv2d_2_scratch0_array", - "offset": 3132, - "size": 2701 - }, - { - "buffer_name": "conv2d_3_scratch0_array", - "offset": 2592, - "size": 1242 - }, - { - "buffer_name": "conv2d_4_scratch0_array", - "offset": 0, - "size": 3241 - }, - { - "buffer_name": "conv2d_5_scratch0_array", - "offset": 0, - "size": 844 - }, - { - "buffer_name": "conv2d_6_scratch0_array", - "offset": 1624, - "size": 2861 - }, - { - "buffer_name": "conv2d_7_scratch0_array", - "offset": 52, - "size": 528 - }, - { - "buffer_name": "gemm_9_scratch0_array", - "offset": 0, - "size": 64 - }, - { - "buffer_name": "nl_10_scratch0_array", - "offset": 68, - "size": 496 - } - ], - "data_alignment": 4, - "pool_id": 0, - "pool_size": -1, - "used_size": 5836 - } - }, - "activations_alignment": 4, - "arguments": "generate --target stm32l4 --name sww_model -m /Users/jeremy/dev/tiny_mlperf/tiny_jhsyn/benchmark/training/streaming_wakeword/trained_models/strm_ww_int8.tflite --compression none --verbosity 1 --allocate-inputs --allocate-outputs --workspace /var/folders/qb/jcjkm0nx4878vyqfjy786xdh0000gn/T/mxAI_workspace27583291741674848973423960786911 --output /Users/jeremy/.stm32cubemx/sww_model_output", - "c_activations_count": 1, - "c_arrays": [ - { - "c_bits": 32, - "c_id": 0, - "c_mem_pool": "weights", - "c_size_in_byte": 160, - "c_type": "const s32", - "format": "s32", - "is_const": true, - "mem_pool": "weights", - "n_items": 40, - "name": "conv2d_0_bias_array", - "offset": 120, - "scale": [], - "size": 40, - "tensors": [ - { - "name": "conv2d_0_bias", - "shape": [ - 40 - ] - } - ], - "zeropoint": [], - "zeros": 0 - }, - { - "c_bits": 8, - "c_id": 1, - "c_mem_pool": "**default**", - "c_size_in_byte": 1120, - "c_type": "s8", - "format": "s8", - "is_const": false, - "mem_pool": "activations", - "n_items": 1120, - "name": "conv2d_0_output_array", - "offset": 2120, - "scale": [ - 0.0018045719480141997 - ], - "size": 1120, - "tensors": [ - { - "name": "conv2d_0_output", - "shape": [ - 28, - 1, - 40 - ] - } - ], - "zeropoint": [ - -3 - ] - }, - { - "c_bits": 8, - "c_id": 2, - "c_mem_pool": "**default**", - "c_size_in_byte": 761, - "c_type": "s8", - "format": "s8", - "is_const": false, - "mem_pool": "activations", - "n_items": 761, - "name": "conv2d_0_scratch0_array", - "offset": 3360, - "scale": [], - "size": 761, - "tensors": [ - { - "name": "conv2d_0_scratch0", - "shape": [ - 1, - 1, - 761, - 1 - ] - } - ], - "zeropoint": [] - }, - { - "c_bits": 8, - "c_id": 3, - "c_mem_pool": "weights", - "c_size_in_byte": 120, - "c_type": "const s8", - "format": "s8", - "is_const": true, - "mem_pool": "weights", - "n_items": 120, - "name": "conv2d_0_weights_array", - "offset": 0, - "scale": [ - 0.001642347895540297, - 0.0012464334722608328, - 0.0018808494787663221, - 0.0017687849467620254, - 0.002232156926766038, - 0.0017221078742295504, - 0.0016933622537180781, - 0.001586283789947629, - 0.0019639935344457626, - 0.0017922259867191315, - 0.0018330850871279836, - 0.0015503712929785252, - 0.001953525235876441, - 0.0015549628296867013, - 0.0024999254383146763, - 0.0009487768402323127, - 0.001722460612654686, - 0.0016345441108569503, - 0.0006262531387619674, - 0.002148588187992573, - 0.0017868067370727658, - 0.0016791783273220062, - 0.0007694695959798992, - 0.0016042999923229218, - 0.002147432416677475, - 0.0026659697759896517, - 0.0016246186569333076, - 0.0015353725757449865, - 0.0013496452011168003, - 0.0010453679133206606, - 0.001754468074068427, - 0.0023172975052148104, - 0.0015870793722569942, - 0.0014503091806545854, - 0.0011753877624869347, - 0.0009309005690738559, - 0.0022590768057852983, - 0.0019405314233154058, - 0.0022477428428828716, - 0.0010750620858743787 - ], - "size": 120, - "tensors": [ - { - "name": "conv2d_0_weights", - "shape": [ - 1, - 3, - 1, - 40 - ] - } - ], - "zeropoint": [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0 - ], - "zeros": 0 - }, - { - "c_bits": 32, - "c_id": 4, - "c_mem_pool": "weights", - "c_size_in_byte": 432, - "c_type": "const s32", - "format": "s32", - "is_const": true, - "mem_pool": "weights", - "n_items": 108, - "name": "conv2d_1_bias_array", - "offset": 4600, - "scale": [], - "size": 108, - "tensors": [ - { - "name": "conv2d_1_bias", - "shape": [ - 108 - ] - } - ], - "zeropoint": [], - "zeros": 0 - }, - { - "c_bits": 8, - "c_id": 5, - "c_mem_pool": "**default**", - "c_size_in_byte": 3024, - "c_type": "s8", - "format": "s8", - "is_const": false, - "mem_pool": "activations", - "n_items": 3024, - "name": "conv2d_1_output_array", - "offset": 108, - "scale": [ - 0.007331364788115025 - ], - "size": 3024, - "tensors": [ - { - "name": "conv2d_1_output", - "shape": [ - 28, - 1, - 108 - ] - } - ], - "zeropoint": [ - -128 - ] - }, - { - "c_bits": 8, - "c_id": 6, - "c_mem_pool": "**default**", - "c_size_in_byte": 1240, - "c_type": "s8", - "format": "s8", - "is_const": false, - "mem_pool": "activations", - "n_items": 1240, - "name": "conv2d_1_scratch0_array", - "offset": 3240, - "scale": [], - "size": 1240, - "tensors": [ - { - "name": "conv2d_1_scratch0", - "shape": [ - 1, - 1, - 1240, - 1 - ] - } - ], - "zeropoint": [] - }, - { - "c_bits": 8, - "c_id": 7, - "c_mem_pool": "weights", - "c_size_in_byte": 4320, - "c_type": "const s8", - "format": "s8", - "is_const": true, - "mem_pool": "weights", - "n_items": 4320, - "name": "conv2d_1_weights_array", - "offset": 280, - "scale": [ - 0.03843778744339943, - 0.03424474969506264, - 0.017642157152295113, - 0.016672806814312935, - 0.02117191255092621, - 0.030264290049672127, - 0.027997097000479698, - 0.024589020758867264, - 0.013011130504310131, - 0.025482743978500366, - 0.02170688845217228, - 0.020765338093042374, - 0.004156722687184811, - 0.01876024156808853, - 0.028028424829244614, - 0.0335012711584568, - 0.028314050287008286, - 0.02842898666858673, - 0.024900702759623528, - 0.022218992933630943, - 0.028063176199793816, - 0.03321857750415802, - 0.02153550460934639, - 0.03990000858902931, - 0.020548759028315544, - 0.03405828773975372, - 0.02318909764289856, - 0.023638205602765083, - 0.019964933395385742, - 0.03596772626042366, - 0.01502156537026167, - 0.03389132022857666, - 0.022404439747333527, - 0.03430989757180214, - 0.03384352847933769, - 0.027794936671853065, - 0.017100447788834572, - 0.01263357698917389, - 0.040574971586465836, - 0.037140779197216034, - 0.031087808310985565, - 0.04442266374826431, - 0.037988293915987015, - 0.029726577922701836, - 0.031557273119688034, - 0.03631843999028206, - 0.025610091164708138, - 0.018468542024493217, - 0.021165795624256134, - 0.02730490453541279, - 0.012819893658161163, - 0.02316182851791382, - 0.026402035728096962, - 0.02412860468029976, - 0.04931594803929329, - 0.031328584998846054, - 0.02464168332517147, - 0.021940257400274277, - 0.035059619694948196, - 0.037006113678216934, - 0.03842802345752716, - 0.03353657200932503, - 0.026503458619117737, - 0.03792215883731842, - 0.027321206405758858, - 0.029820093885064125, - 0.0310662854462862, - 0.029756441712379456, - 0.024783749133348465, - 0.015829073265194893, - 0.022009551525115967, - 0.03166014701128006, - 0.016863781958818436, - 0.029639851301908493, - 0.03000551462173462, - 0.01928015798330307, - 0.02872774749994278, - 0.03196508064866066, - 0.03661493584513664, - 0.025833558291196823, - 0.03245000168681145, - 0.02557412162423134, - 0.02539031393826008, - 0.03885124996304512, - 0.027298370376229286, - 0.030694743618369102, - 0.023782826960086823, - 0.013601325452327728, - 0.016648098826408386, - 0.019702767953276634, - 0.04989137127995491, - 0.01952550560235977, - 0.011950946412980556, - 0.020136114209890366, - 0.0188601054251194, - 0.031969454139471054, - 0.015985149890184402, - 0.022637400776147842, - 0.0029883950483053923, - 0.009722628630697727, - 0.023238789290189743, - 0.018725885078310966, - 0.03747653216123581, - 0.0312572605907917, - 0.027069244533777237, - 0.019321395084261894, - 0.01773461326956749, - 0.02210475318133831 - ], - "size": 4320, - "tensors": [ - { - "name": "conv2d_1_weights", - "shape": [ - 108, - 1, - 1, - 40 - ] - } - ], - "zeropoint": [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0 - ], - "zeros": 0 - }, - { - "c_bits": 32, - "c_id": 8, - "c_mem_pool": "weights", - "c_size_in_byte": 432, - "c_type": "const s32", - "format": "s32", - "is_const": true, - "mem_pool": "weights", - "n_items": 108, - "name": "conv2d_2_bias_array", - "offset": 5572, - "scale": [], - "size": 108, - "tensors": [ - { - "name": "conv2d_2_bias", - "shape": [ - 108 - ] - } - ], - "zeropoint": [], - "zeros": 0 - }, - { - "c_bits": 8, - "c_id": 9, - "c_mem_pool": "**default**", - "c_size_in_byte": 2592, - "c_type": "s8", - "format": "s8", - "is_const": false, - "mem_pool": "activations", - "n_items": 2592, - "name": "conv2d_2_output_array", - "offset": 0, - "scale": [ - 0.0033829212188720703 - ], - "size": 2592, - "tensors": [ - { - "name": "conv2d_2_output", - "shape": [ - 24, - 1, - 108 - ] - } - ], - "zeropoint": [ - 4 - ] - }, - { - "c_bits": 8, - "c_id": 10, - "c_mem_pool": "**default**", - "c_size_in_byte": 2701, - "c_type": "s8", - "format": "s8", - "is_const": false, - "mem_pool": "activations", - "n_items": 2701, - "name": "conv2d_2_scratch0_array", - "offset": 3132, - "scale": [], - "size": 2701, - "tensors": [ - { - "name": "conv2d_2_scratch0", - "shape": [ - 1, - 1, - 2701, - 1 - ] - } - ], - "zeropoint": [] - }, - { - "c_bits": 8, - "c_id": 11, - "c_mem_pool": "weights", - "c_size_in_byte": 540, - "c_type": "const s8", - "format": "s8", - "is_const": true, - "mem_pool": "weights", - "n_items": 540, - "name": "conv2d_2_weights_array", - "offset": 5032, - "scale": [ - 0.0012193449074402452, - 0.0011896206997334957, - 0.001150784082710743, - 0.0015751051250845194, - 0.0014076937222853303, - 0.0014134043594822288, - 0.0012166631640866399, - 0.0008614432299509645, - 0.0013119303621351719, - 0.0010421304032206535, - 0.001792778610251844, - 0.0006943026673980057, - 0.0012489653890952468, - 0.0016015503788366914, - 0.0013164817355573177, - 0.0014498716918751597, - 0.0009809196926653385, - 0.0012443828163668513, - 0.0015893805539235473, - 0.0012252413434907794, - 0.00146100006531924, - 0.0012698895297944546, - 0.0009081409662030637, - 0.0011611015070229769, - 0.0014941409463062882, - 0.0014062923146411777, - 0.0014375756727531552, - 0.0011015296913683414, - 0.0011722077615559101, - 0.0017788897966966033, - 0.0015201474307104945, - 0.001466955873183906, - 0.001193762058392167, - 0.0011754519073292613, - 0.0010366021888330579, - 0.0011002852115780115, - 0.0012190159177407622, - 0.0009785162983462214, - 0.0015096979914233088, - 0.0014507253654301167, - 0.001522812177427113, - 0.0011339515913277864, - 0.0012347951997071505, - 0.0017208375502377748, - 0.0012510899687185884, - 0.0011507170274853706, - 0.0015958300791680813, - 0.0011514110956341028, - 0.0014947318704798818, - 0.0015390361659228802, - 0.0009209638810716569, - 0.0016760819125920534, - 0.0009958102600649, - 0.0012021957663819194, - 0.0016008286038413644, - 0.0010758097050711513, - 0.0013621337711811066, - 0.0010371701791882515, - 0.001484634238295257, - 0.0015296931378543377, - 0.0014479142846539617, - 0.0018752461764961481, - 0.0011389135615900159, - 0.0015793287893757224, - 0.0010704681044444442, - 0.0014446311397477984, - 0.001430619740858674, - 0.0011343255173414946, - 0.0014109080657362938, - 0.0011780846398323774, - 0.0013960669748485088, - 0.0012521182652562857, - 0.0012801842531189322, - 0.0010166580323129892, - 0.0011850884184241295, - 0.001457210979424417, - 0.0013643177226185799, - 0.0011476562358438969, - 0.0009190457058139145, - 0.001462473999708891, - 0.0015686636324971914, - 0.000985241960734129, - 0.0012081931345164776, - 0.0012406273745000362, - 0.001423214445821941, - 0.0013334010727703571, - 0.001554172020405531, - 0.0012627579271793365, - 0.0013837196165695786, - 0.0015174734871834517, - 0.0016533306334167719, - 0.0016571376472711563, - 0.0010685668094083667, - 0.0012777920346707106, - 0.0012865728931501508, - 0.0013592647155746818, - 0.0013121356023475528, - 0.0010990258306264877, - 0.0009446862968616188, - 0.0011264465283602476, - 0.0014283916680142283, - 0.0011742946226149797, - 0.001202662126161158, - 0.0012340721441432834, - 0.0010347074130550027, - 0.0010912242578342557, - 0.0016451962292194366, - 0.0012853143271058798 - ], - "size": 540, - "tensors": [ - { - "name": "conv2d_2_weights", - "shape": [ - 1, - 5, - 1, - 108 - ] - } - ], - "zeropoint": [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0 - ], - "zeros": 0 - }, - { - "c_bits": 32, - "c_id": 12, - "c_mem_pool": "weights", - "c_size_in_byte": 324, - "c_type": "const s32", - "format": "s32", - "is_const": true, - "mem_pool": "weights", - "n_items": 81, - "name": "conv2d_3_bias_array", - "offset": 14752, - "scale": [], - "size": 81, - "tensors": [ - { - "name": "conv2d_3_bias", - "shape": [ - 81 - ] - } - ], - "zeropoint": [], - "zeros": 0 - }, - { - "c_bits": 8, - "c_id": 13, - "c_mem_pool": "**default**", - "c_size_in_byte": 1944, - "c_type": "s8", - "format": "s8", - "is_const": false, - "mem_pool": "activations", - "n_items": 1944, - "name": "conv2d_3_output_array", - "offset": 3836, - "scale": [ - 0.008522006683051586 - ], - "size": 1944, - "tensors": [ - { - "name": "conv2d_3_output", - "shape": [ - 24, - 1, - 81 - ] - } - ], - "zeropoint": [ - -128 - ] - }, - { - "c_bits": 8, - "c_id": 14, - "c_mem_pool": "**default**", - "c_size_in_byte": 1242, - "c_type": "s8", - "format": "s8", - "is_const": false, - "mem_pool": "activations", - "n_items": 1242, - "name": "conv2d_3_scratch0_array", - "offset": 2592, - "scale": [], - "size": 1242, - "tensors": [ - { - "name": "conv2d_3_scratch0", - "shape": [ - 1, - 1, - 1242, - 1 - ] - } - ], - "zeropoint": [] - }, - { - "c_bits": 8, - "c_id": 15, - "c_mem_pool": "weights", - "c_size_in_byte": 8748, - "c_type": "const s8", - "format": "s8", - "is_const": true, - "mem_pool": "weights", - "n_items": 8748, - "name": "conv2d_3_weights_array", - "offset": 6004, - "scale": [ - 0.015128846280276775, - 0.015573011711239815, - 0.016271857544779778, - 0.014132648706436157, - 0.018094440922141075, - 0.020049450919032097, - 0.018400095403194427, - 0.017870919778943062, - 0.016350913792848587, - 0.014747311361134052, - 0.017187248915433884, - 0.016289183869957924, - 0.015324003994464874, - 0.02062303200364113, - 0.01638767123222351, - 0.014158428646624088, - 0.01555232796818018, - 0.02522544004023075, - 0.01610005833208561, - 0.02466684952378273, - 0.018511435016989708, - 0.015439994633197784, - 0.012423139996826649, - 0.018430529162287712, - 0.013635613955557346, - 0.013857602141797543, - 0.016926752403378487, - 0.019769813865423203, - 0.026674576103687286, - 0.01582067273557186, - 0.01869085244834423, - 0.016557810828089714, - 0.010478632524609566, - 0.016589654609560966, - 0.017770716920495033, - 0.015888260677456856, - 0.018635224550962448, - 0.016906341537833214, - 0.02251080609858036, - 0.01092725433409214, - 0.018775317817926407, - 0.01914645917713642, - 0.021332694217562675, - 0.011556758545339108, - 0.017348820343613625, - 0.017436355352401733, - 0.01638859696686268, - 0.01837228797376156, - 0.01729300431907177, - 0.015137557871639729, - 0.020055970177054405, - 0.016387302428483963, - 0.015314789488911629, - 0.015308589674532413, - 0.014827247709035873, - 0.016430499032139778, - 0.016709063202142715, - 0.0161450132727623, - 0.0203449334949255, - 0.016926869750022888, - 0.015119430609047413, - 0.013861013576388359, - 0.012870672158896923, - 0.018918493762612343, - 0.015354461036622524, - 0.00960373505949974, - 0.012707964517176151, - 0.015196085907518864, - 0.012715458869934082, - 0.019194994121789932, - 0.014486822299659252, - 0.020452536642551422, - 0.020936153829097748, - 0.016988983377814293, - 0.013276669196784496, - 0.016756894066929817, - 0.01643085852265358, - 0.019164972007274628, - 0.018671797588467598, - 0.014429536648094654, - 0.01753745600581169 - ], - "size": 8748, - "tensors": [ - { - "name": "conv2d_3_weights", - "shape": [ - 81, - 1, - 1, - 108 - ] - } - ], - "zeropoint": [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0 - ], - "zeros": 0 - }, - { - "c_bits": 32, - "c_id": 16, - "c_mem_pool": "weights", - "c_size_in_byte": 324, - "c_type": "const s32", - "format": "s32", - "is_const": true, - "mem_pool": "weights", - "n_items": 81, - "name": "conv2d_4_bias_array", - "offset": 15888, - "scale": [], - "size": 81, - "tensors": [ - { - "name": "conv2d_4_bias", - "shape": [ - 81 - ] - } - ], - "zeropoint": [], - "zeros": 0 - }, - { - "c_bits": 8, - "c_id": 17, - "c_mem_pool": "**default**", - "c_size_in_byte": 1215, - "c_type": "s8", - "format": "s8", - "is_const": false, - "mem_pool": "activations", - "n_items": 1215, - "name": "conv2d_4_output_array", - "offset": 3752, - "scale": [ - 0.005995603743940592 - ], - "size": 1215, - "tensors": [ - { - "name": "conv2d_4_output", - "shape": [ - 15, - 1, - 81 - ] - } - ], - "zeropoint": [ - 17 - ] - }, - { - "c_bits": 8, - "c_id": 18, - "c_mem_pool": "**default**", - "c_size_in_byte": 3241, - "c_type": "s8", - "format": "s8", - "is_const": false, - "mem_pool": "activations", - "n_items": 3241, - "name": "conv2d_4_scratch0_array", - "offset": 0, - "scale": [], - "size": 3241, - "tensors": [ - { - "name": "conv2d_4_scratch0", - "shape": [ - 1, - 1, - 3241, - 1 - ] - } - ], - "zeropoint": [] - }, - { - "c_bits": 8, - "c_id": 19, - "c_mem_pool": "weights", - "c_size_in_byte": 810, - "c_type": "const s8", - "format": "s8", - "is_const": true, - "mem_pool": "weights", - "n_items": 810, - "name": "conv2d_4_weights_array", - "offset": 15076, - "scale": [ - 0.0013209173921495676, - 0.0013699670089408755, - 0.0011900769313797355, - 0.0014234690461307764, - 0.0012966083595529199, - 0.002158000133931637, - 0.0013979612849652767, - 0.0010544935939833522, - 0.0008681811159476638, - 0.0014393681194633245, - 0.0018609057879075408, - 0.0013464994262903929, - 0.0008672561962157488, - 0.001372328493744135, - 0.0013065575622022152, - 0.0015507722273468971, - 0.0015574434073641896, - 0.0016854808200150728, - 0.0012486601481214166, - 0.0021874085068702698, - 0.0014007712015882134, - 0.0017165332101285458, - 0.0020851553417742252, - 0.0020932801999151707, - 0.001796632306650281, - 0.0014638400170952082, - 0.0019234605133533478, - 0.002710780594497919, - 0.0012269431026652455, - 0.0010644309222698212, - 0.0014495650539174676, - 0.0013952819863334298, - 0.0015238363994285464, - 0.0015330613823607564, - 0.001806235290132463, - 0.0015545615460723639, - 0.001962702488526702, - 0.0018692143494263291, - 0.002919284626841545, - 0.0011838754871860147, - 0.0014690218959003687, - 0.001570309977978468, - 0.0016600311500951648, - 0.001322298077866435, - 0.001086729229427874, - 0.00108465610537678, - 0.0016869003884494305, - 0.002073693787679076, - 0.0013331201625987887, - 0.0013437183806672692, - 0.0009963620686903596, - 0.0015516714192926884, - 0.0024561795871704817, - 0.001887949532829225, - 0.0019081522477790713, - 0.0018222932703793049, - 0.0012474765535444021, - 0.001181218191049993, - 0.0011141691356897354, - 0.0026841002982109785, - 0.00209209811873734, - 0.0012199511984363198, - 0.0012844110606238246, - 0.0020877672359347343, - 0.0014856132911518216, - 0.0009970106184482574, - 0.001144768437370658, - 0.0020951591432094574, - 0.0013088099658489227, - 0.0008139606798067689, - 0.0014311781851574779, - 0.0024156002327799797, - 0.0010804146295413375, - 0.001683399430476129, - 0.0019631627947092056, - 0.0013160593807697296, - 0.001466938410885632, - 0.001094481791369617, - 0.0015286278212442994, - 0.0013401331380009651, - 0.0011197495041415095 - ], - "size": 810, - "tensors": [ - { - "name": "conv2d_4_weights", - "shape": [ - 1, - 10, - 1, - 81 - ] - } - ], - "zeropoint": [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0 - ], - "zeros": 0 - }, - { - "c_bits": 32, - "c_id": 20, - "c_mem_pool": "weights", - "c_size_in_byte": 208, - "c_type": "const s32", - "format": "s32", - "is_const": true, - "mem_pool": "weights", - "n_items": 52, - "name": "conv2d_5_bias_array", - "offset": 20424, - "scale": [], - "size": 52, - "tensors": [ - { - "name": "conv2d_5_bias", - "shape": [ - 52 - ] - } - ], - "zeropoint": [], - "zeros": 0 - }, - { - "c_bits": 8, - "c_id": 21, - "c_mem_pool": "**default**", - "c_size_in_byte": 780, - "c_type": "s8", - "format": "s8", - "is_const": false, - "mem_pool": "activations", - "n_items": 780, - "name": "conv2d_5_output_array", - "offset": 844, - "scale": [ - 0.012133517302572727 - ], - "size": 780, - "tensors": [ - { - "name": "conv2d_5_output", - "shape": [ - 15, - 1, - 52 - ] - } - ], - "zeropoint": [ - -128 - ] - }, - { - "c_bits": 8, - "c_id": 22, - "c_mem_pool": "**default**", - "c_size_in_byte": 844, - "c_type": "s8", - "format": "s8", - "is_const": false, - "mem_pool": "activations", - "n_items": 844, - "name": "conv2d_5_scratch0_array", - "offset": 0, - "scale": [], - "size": 844, - "tensors": [ - { - "name": "conv2d_5_scratch0", - "shape": [ - 1, - 1, - 844, - 1 - ] - } - ], - "zeropoint": [] - }, - { - "c_bits": 8, - "c_id": 23, - "c_mem_pool": "weights", - "c_size_in_byte": 4212, - "c_type": "const s8", - "format": "s8", - "is_const": true, - "mem_pool": "weights", - "n_items": 4212, - "name": "conv2d_5_weights_array", - "offset": 16212, - "scale": [ - 0.015773683786392212, - 0.017180703580379486, - 0.016543541103601456, - 0.012180080637335777, - 0.012121811509132385, - 0.01948302611708641, - 0.01332039199769497, - 0.008291282691061497, - 0.006536763161420822, - 0.01492640282958746, - 0.015078308060765266, - 0.01259052287787199, - 0.014905902557075024, - 0.009477532468736172, - 0.017825616523623466, - 0.0100540891289711, - 0.01577778160572052, - 0.007912426255643368, - 0.013099128380417824, - 0.011292265728116035, - 0.014415361918509007, - 0.01442705001682043, - 0.0154510997235775, - 0.01196146011352539, - 0.011186054907739162, - 0.011584583669900894, - 0.012372108176350594, - 0.009474975988268852, - 0.015400659292936325, - 0.015521892346441746, - 0.009775904938578606, - 0.014177525416016579, - 0.018218280747532845, - 0.012715878896415234, - 0.01842585951089859, - 0.014037981629371643, - 0.012311501428484917, - 0.013712716288864613, - 0.010050556622445583, - 0.011510557495057583, - 0.015110366977751255, - 0.017335738986730576, - 0.011255898512899876, - 0.010579855181276798, - 0.007013300433754921, - 0.00525946170091629, - 0.010228436440229416, - 0.014367306604981422, - 0.012811205349862576, - 0.009629661217331886, - 0.00906060915440321, - 0.013815436512231827 - ], - "size": 4212, - "tensors": [ - { - "name": "conv2d_5_weights", - "shape": [ - 52, - 1, - 1, - 81 - ] - } - ], - "zeropoint": [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0 - ], - "zeros": 0 - }, - { - "c_bits": 32, - "c_id": 24, - "c_mem_pool": "weights", - "c_size_in_byte": 208, - "c_type": "const s32", - "format": "s32", - "is_const": true, - "mem_pool": "weights", - "n_items": 52, - "name": "conv2d_6_bias_array", - "offset": 21412, - "scale": [], - "size": 52, - "tensors": [ - { - "name": "conv2d_6_bias", - "shape": [ - 52 - ] - } - ], - "zeropoint": [], - "zeros": 0 - }, - { - "c_bits": 8, - "c_id": 25, - "c_mem_pool": "**default**", - "c_size_in_byte": 52, - "c_type": "s8", - "format": "s8", - "is_const": false, - "mem_pool": "activations", - "n_items": 52, - "name": "conv2d_6_output_array", - "offset": 0, - "scale": [ - 0.014823319390416145 - ], - "size": 52, - "tensors": [ - { - "name": "conv2d_6_output", - "shape": [ - 1, - 1, - 52 - ] - } - ], - "zeropoint": [ - 3 - ] - }, - { - "c_bits": 8, - "c_id": 26, - "c_mem_pool": "**default**", - "c_size_in_byte": 2861, - "c_type": "s8", - "format": "s8", - "is_const": false, - "mem_pool": "activations", - "n_items": 2861, - "name": "conv2d_6_scratch0_array", - "offset": 1624, - "scale": [], - "size": 2861, - "tensors": [ - { - "name": "conv2d_6_scratch0", - "shape": [ - 1, - 1, - 2861, - 1 - ] - } - ], - "zeropoint": [] - }, - { - "c_bits": 8, - "c_id": 27, - "c_mem_pool": "weights", - "c_size_in_byte": 780, - "c_type": "const s8", - "format": "s8", - "is_const": true, - "mem_pool": "weights", - "n_items": 780, - "name": "conv2d_6_weights_array", - "offset": 20632, - "scale": [ - 0.0012915823608636856, - 0.0012511053355410695, - 0.0011855724733322859, - 0.0025645773857831955, - 0.001079620560631156, - 0.0017146256286650896, - 0.0011722984490916133, - 0.0011089964536949992, - 0.0021147746592760086, - 0.0019927872344851494, - 0.0014550697524100542, - 0.002831965684890747, - 0.0018483612220734358, - 0.0008478033705614507, - 0.0018396616214886308, - 0.0021623552311211824, - 0.0019630850292742252, - 0.0017485704738646746, - 0.0021983326878398657, - 0.0011710221879184246, - 0.002634496660903096, - 0.0015223354566842318, - 0.0019060292979702353, - 0.0017563101137056947, - 0.0020001009106636047, - 0.0017203905154019594, - 0.0009780041873455048, - 0.0009349649189971387, - 0.0010179498931393027, - 0.002921813866123557, - 0.001127480762079358, - 0.002835941733792424, - 0.0025946912355720997, - 0.0017454741755500436, - 0.0021075394470244646, - 0.0013835849240422249, - 0.00247604469768703, - 0.0010387442307546735, - 0.0026010600849986076, - 0.0020862752571702003, - 0.0010696039535105228, - 0.0024096250999718904, - 0.001306817983277142, - 0.0008883686969056726, - 0.0018930664518848062, - 0.0010039584012702107, - 0.0013365934137254953, - 0.0024195443838834763, - 0.0014412919990718365, - 0.001000774442218244, - 0.0019087563268840313, - 0.0025204240810126066 - ], - "size": 780, - "tensors": [ - { - "name": "conv2d_6_weights", - "shape": [ - 1, - 15, - 1, - 52 - ] - } - ], - "zeropoint": [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0 - ], - "zeros": 0 - }, - { - "c_bits": 32, - "c_id": 28, - "c_mem_pool": "weights", - "c_size_in_byte": 128, - "c_type": "const s32", - "format": "s32", - "is_const": true, - "mem_pool": "weights", - "n_items": 32, - "name": "conv2d_7_bias_array", - "offset": 23284, - "scale": [], - "size": 32, - "tensors": [ - { - "name": "conv2d_7_bias", - "shape": [ - 32 - ] - } - ], - "zeropoint": [], - "zeros": 0 - }, - { - "c_bits": 8, - "c_id": 29, - "c_mem_pool": "**default**", - "c_size_in_byte": 32, - "c_type": "s8", - "format": "s8", - "is_const": false, - "mem_pool": "activations", - "n_items": 32, - "name": "conv2d_7_output_array", - "offset": 580, - "scale": [ - 0.018331341445446014 - ], - "size": 32, - "tensors": [ - { - "name": "conv2d_7_output", - "shape": [ - 1, - 1, - 32 - ] - } - ], - "zeropoint": [ - -128 - ] - }, - { - "c_bits": 8, - "c_id": 30, - "c_mem_pool": "**default**", - "c_size_in_byte": 528, - "c_type": "s8", - "format": "s8", - "is_const": false, - "mem_pool": "activations", - "n_items": 528, - "name": "conv2d_7_scratch0_array", - "offset": 52, - "scale": [], - "size": 528, - "tensors": [ - { - "name": "conv2d_7_scratch0", - "shape": [ - 1, - 1, - 528, - 1 - ] - } - ], - "zeropoint": [] - }, - { - "c_bits": 8, - "c_id": 31, - "c_mem_pool": "weights", - "c_size_in_byte": 1664, - "c_type": "const s8", - "format": "s8", - "is_const": true, - "mem_pool": "weights", - "n_items": 1664, - "name": "conv2d_7_weights_array", - "offset": 21620, - "scale": [ - 0.007534192409366369, - 0.005160065367817879, - 0.00863321591168642, - 0.011691645719110966, - 0.007065467070788145, - 0.013616980984807014, - 0.010354913771152496, - 0.005401516333222389, - 0.00899604894220829, - 0.008329877629876137, - 0.009429126977920532, - 0.00915415771305561, - 0.012206453830003738, - 0.007751247379928827, - 0.008157746866345406, - 0.006608979310840368, - 0.008793451823294163, - 0.00995804462581873, - 0.00625076936557889, - 0.005368341226130724, - 0.009286150336265564, - 0.009581937454640865, - 0.00813126377761364, - 0.007290022913366556, - 0.006840443704277277, - 0.0074807205237448215, - 0.009476734325289726, - 0.008071377873420715, - 0.006180003751069307, - 0.011818638071417809, - 0.008427681401371956, - 0.009211544878780842 - ], - "size": 1664, - "tensors": [ - { - "name": "conv2d_7_weights", - "shape": [ - 32, - 1, - 1, - 52 - ] - } - ], - "zeropoint": [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0 - ], - "zeros": 0 - }, - { - "c_bits": 32, - "c_id": 32, - "c_mem_pool": "weights", - "c_size_in_byte": 12, - "c_type": "const s32", - "format": "s32", - "is_const": true, - "mem_pool": "weights", - "n_items": 3, - "name": "gemm_9_bias_array", - "offset": 23508, - "scale": [], - "size": 3, - "tensors": [ - { - "name": "gemm_9_bias", - "shape": [ - 3 - ] - } - ], - "zeropoint": [], - "zeros": 0 - }, - { - "c_bits": 8, - "c_id": 33, - "c_mem_pool": "**default**", - "c_size_in_byte": 3, - "c_type": "s8", - "format": "s8", - "is_const": false, - "mem_pool": "activations", - "n_items": 3, - "name": "gemm_9_output_array", - "offset": 64, - "scale": [ - 0.14710605144500732 - ], - "size": 3, - "tensors": [ - { - "name": "gemm_9_output", - "shape": [ - 3 - ] - } - ], - "zeropoint": [ - 30 - ] - }, - { - "c_bits": 16, - "c_id": 34, - "c_mem_pool": "**default**", - "c_size_in_byte": 64, - "c_type": "s16", - "format": "s16", - "is_const": false, - "mem_pool": "activations", - "n_items": 32, - "name": "gemm_9_scratch0_array", - "offset": 0, - "scale": [], - "size": 32, - "tensors": [ - { - "name": "gemm_9_scratch0", - "shape": [ - 1, - 1, - 32, - 1 - ] - } - ], - "zeropoint": [] - }, - { - "c_bits": 8, - "c_id": 35, - "c_mem_pool": "weights", - "c_size_in_byte": 96, - "c_type": "const s8", - "format": "s8", - "is_const": true, - "mem_pool": "weights", - "n_items": 96, - "name": "gemm_9_weights_array", - "offset": 23412, - "scale": [ - 0.01235697977244854 - ], - "size": 96, - "tensors": [ - { - "name": "gemm_9_weights", - "shape": [ - 3, - 32 - ] - } - ], - "zeropoint": [ - 0 - ], - "zeros": 0 - }, - { - "c_bits": 8, - "c_id": 36, - "c_mem_pool": "**default**", - "c_size_in_byte": 3, - "c_type": "s8", - "format": "s8", - "io_type": "output", - "is_const": false, - "mem_pool": "activations", - "n_items": 3, - "name": "nl_10_output_array", - "offset": 0, - "scale": [ - 0.00390625 - ], - "size": 3, - "tensors": [ - { - "name": "nl_10_output", - "shape": [ - 3 - ] - } - ], - "zeropoint": [ - -128 - ] - }, - { - "c_bits": 32, - "c_id": 37, - "c_mem_pool": "**default**", - "c_size_in_byte": 496, - "c_type": "s32", - "format": "s32", - "is_const": false, - "mem_pool": "activations", - "n_items": 124, - "name": "nl_10_scratch0_array", - "offset": 68, - "scale": [], - "size": 124, - "tensors": [ - { - "name": "nl_10_scratch0", - "shape": [ - 1, - 1, - 124, - 1 - ] - } - ], - "zeropoint": [] - }, - { - "c_bits": 8, - "c_id": 38, - "c_mem_pool": "**default**", - "c_size_in_byte": 1200, - "c_type": "s8", - "format": "s8", - "io_type": "input", - "is_const": false, - "mem_pool": "activations", - "n_items": 1200, - "name": "serving_default_input_10_output_array", - "offset": 2160, - "scale": [ - 0.003701042616739869 - ], - "size": 1200, - "tensors": [ - { - "name": "serving_default_input_10_output", - "shape": [ - 30, - 1, - 40 - ] - } - ], - "zeropoint": [ - -128 - ] - } - ], - "c_arrays_n": 39, - "c_layers": [ - { - "c_forward": [ - "forward_dw_sssa8_ch" - ], - "c_id": 0, - "is_wrapped": "", - "layer_type": "Conv2D", - "m_id": 0, - "macc": 3400, - "name": "conv2d_0", - "op_by_type": { - "smul_s8_s8": 3400 - }, - "rom": 280, - "tensors": { - "inputs": [ - "serving_default_input_10_output" - ], - "outputs": [ - "conv2d_0_output" - ], - "scratchs": [ - "conv2d_0_scratch0" - ], - "weights": [ - "conv2d_0_weights", - "conv2d_0_bias" - ] - }, - "weight_sparsity": [ - 0.0, - 160, - 0 - ] - }, - { - "c_forward": [ - "forward_pw_sssa8_ch" - ], - "c_id": 1, - "is_wrapped": "", - "layer_type": "Conv2D", - "m_id": 1, - "macc": 141246, - "name": "conv2d_1", - "op_by_type": { - "smul_s8_s8": 141246 - }, - "rom": 4752, - "tensors": { - "inputs": [ - "conv2d_0_output" - ], - "outputs": [ - "conv2d_1_output" - ], - "scratchs": [ - "conv2d_1_scratch0" - ], - "weights": [ - "conv2d_1_weights", - "conv2d_1_bias" - ] - }, - "weight_sparsity": [ - 0.0, - 4428, - 0 - ] - }, - { - "c_forward": [ - "forward_dw_sssa8_ch" - ], - "c_id": 2, - "is_wrapped": "", - "layer_type": "Conv2D", - "m_id": 2, - "macc": 13068, - "name": "conv2d_2", - "op_by_type": { - "smul_s8_s8": 13068 - }, - "rom": 972, - "tensors": { - "inputs": [ - "conv2d_1_output" - ], - "outputs": [ - "conv2d_2_output" - ], - "scratchs": [ - "conv2d_2_scratch0" - ], - "weights": [ - "conv2d_2_weights", - "conv2d_2_bias" - ] - }, - "weight_sparsity": [ - 0.0, - 648, - 0 - ] - }, - { - "c_forward": [ - "forward_pw_sssa8_ch" - ], - "c_id": 3, - "is_wrapped": "", - "layer_type": "Conv2D", - "m_id": 3, - "macc": 326718, - "name": "conv2d_3", - "op_by_type": { - "smul_s8_s8": 326718 - }, - "rom": 9072, - "tensors": { - "inputs": [ - "conv2d_2_output" - ], - "outputs": [ - "conv2d_3_output" - ], - "scratchs": [ - "conv2d_3_scratch0" - ], - "weights": [ - "conv2d_3_weights", - "conv2d_3_bias" - ] - }, - "weight_sparsity": [ - 0.0, - 8829, - 0 - ] - }, - { - "c_forward": [ - "forward_dw_sssa8_ch" - ], - "c_id": 4, - "is_wrapped": "", - "layer_type": "Conv2D", - "m_id": 4, - "macc": 12231, - "name": "conv2d_4", - "op_by_type": { - "smul_s8_s8": 12231 - }, - "rom": 1134, - "tensors": { - "inputs": [ - "conv2d_3_output" - ], - "outputs": [ - "conv2d_4_output" - ], - "scratchs": [ - "conv2d_4_scratch0" - ], - "weights": [ - "conv2d_4_weights", - "conv2d_4_bias" - ] - }, - "weight_sparsity": [ - 0.0, - 891, - 0 - ] - }, - { - "c_forward": [ - "forward_pw_sssa8_ch" - ], - "c_id": 5, - "is_wrapped": "", - "layer_type": "Conv2D", - "m_id": 5, - "macc": 153216, - "name": "conv2d_5", - "op_by_type": { - "smul_s8_s8": 153216 - }, - "rom": 4420, - "tensors": { - "inputs": [ - "conv2d_4_output" - ], - "outputs": [ - "conv2d_5_output" - ], - "scratchs": [ - "conv2d_5_scratch0" - ], - "weights": [ - "conv2d_5_weights", - "conv2d_5_bias" - ] - }, - "weight_sparsity": [ - 0.0, - 4264, - 0 - ] - }, - { - "c_forward": [ - "forward_dw_sssa8_ch" - ], - "c_id": 6, - "is_wrapped": "", - "layer_type": "Conv2D", - "m_id": 6, - "macc": 832, - "name": "conv2d_6", - "op_by_type": { - "smul_s8_s8": 832 - }, - "rom": 988, - "tensors": { - "inputs": [ - "conv2d_5_output" - ], - "outputs": [ - "conv2d_6_output" - ], - "scratchs": [ - "conv2d_6_scratch0" - ], - "weights": [ - "conv2d_6_weights", - "conv2d_6_bias" - ] - }, - "weight_sparsity": [ - 0.0, - 832, - 0 - ] - }, - { - "c_forward": [ - "forward_pw_sssa8_ch" - ], - "c_id": 7, - "is_wrapped": "", - "layer_type": "Conv2D", - "m_id": 7, - "macc": 1696, - "name": "conv2d_7", - "op_by_type": { - "smul_s8_s8": 1696 - }, - "rom": 1792, - "tensors": { - "inputs": [ - "conv2d_6_output" - ], - "outputs": [ - "conv2d_7_output" - ], - "scratchs": [ - "conv2d_7_scratch0" - ], - "weights": [ - "conv2d_7_weights", - "conv2d_7_bias" - ] - }, - "weight_sparsity": [ - 0.0, - 1696, - 0 - ] - }, - { - "c_forward": [ - "forward_dense_integer_SSSA" - ], - "c_id": 8, - "is_wrapped": "", - "layer_type": "Dense", - "m_id": 9, - "macc": 99, - "name": "gemm_9", - "op_by_type": { - "smul_s8_s8": 99 - }, - "rom": 108, - "tensors": { - "inputs": [ - "conv2d_7_output" - ], - "outputs": [ - "gemm_9_output" - ], - "scratchs": [ - "gemm_9_scratch0" - ], - "weights": [ - "gemm_9_weights", - "gemm_9_bias" - ] - }, - "weight_sparsity": [ - 0.0, - 99, - 0 - ] - }, - { - "c_forward": [ - "forward_sm_integer" - ], - "c_id": 9, - "is_wrapped": "", - "layer_type": "Nonlinearity", - "m_id": 10, - "macc": 45, - "name": "nl_10", - "op_by_type": { - "op_s8_s8": 45 - }, - "rom": 0, - "tensors": { - "inputs": [ - "gemm_9_output" - ], - "outputs": [ - "nl_10_output" - ], - "scratchs": [ - "nl_10_scratch0" - ], - "weights": [] - }, - "weight_sparsity": [ - 0.0, - 1, - 0 - ] - } - ], - "c_name": "sww_model", - "c_nodes_n": 10, - "c_weights_count": 1, - "c_weights_header": 0, - "compilation_options": { - "compression": "none", - "optimization": "balanced", - "options": [ - "allocate-inputs", - "allocate-outputs" - ] - }, - "data_alignment": 4, - "date_time": "2025-01-19T06:26:52-0500", - "inputs": [ - "serving_default_input_10_output" - ], - "macc": 652551, - "memory_footprint": { - "activations": 5836, - "io": [ - 0, - 0 - ], - "series": "generic", - "weights": 23520 - }, - "memory_pools": [], - "model_fmt": "ss/sa per channel", - "model_name": "strm_ww_int8", - "model_signature": "0x11c3f8bb3c26578a427b600d2c3795e0", - "outputs": [ - "nl_10_output" - ], - "st_ai_version": "1.0.0-19899", - "tool_version": "1.0.0-19899", - "type": "tflite", - "version": "1.2", - "weights": { - "weights_array": { - "buffer_data_size": 23520, - "buffer_offsets": [ - { - "buffer_name": "conv2d_0_weights_array", - "offset": 0, - "size": 120 - }, - { - "buffer_name": "conv2d_0_bias_array", - "offset": 120, - "size": 160 - }, - { - "buffer_name": "conv2d_1_weights_array", - "offset": 280, - "size": 4320 - }, - { - "buffer_name": "conv2d_1_bias_array", - "offset": 4600, - "size": 432 - }, - { - "buffer_name": "conv2d_2_weights_array", - "offset": 5032, - "size": 540 - }, - { - "buffer_name": "conv2d_2_bias_array", - "offset": 5572, - "size": 432 - }, - { - "buffer_name": "conv2d_3_weights_array", - "offset": 6004, - "size": 8748 - }, - { - "buffer_name": "conv2d_3_bias_array", - "offset": 14752, - "size": 324 - }, - { - "buffer_name": "conv2d_4_weights_array", - "offset": 15076, - "size": 810 - }, - { - "buffer_name": "conv2d_4_bias_array", - "offset": 15888, - "size": 324 - }, - { - "buffer_name": "conv2d_5_weights_array", - "offset": 16212, - "size": 4212 - }, - { - "buffer_name": "conv2d_5_bias_array", - "offset": 20424, - "size": 208 - }, - { - "buffer_name": "conv2d_6_weights_array", - "offset": 20632, - "size": 780 - }, - { - "buffer_name": "conv2d_6_bias_array", - "offset": 21412, - "size": 208 - }, - { - "buffer_name": "conv2d_7_weights_array", - "offset": 21620, - "size": 1664 - }, - { - "buffer_name": "conv2d_7_bias_array", - "offset": 23284, - "size": 128 - }, - { - "buffer_name": "gemm_9_weights_array", - "offset": 23412, - "size": 96 - }, - { - "buffer_name": "gemm_9_bias_array", - "offset": 23508, - "size": 12 - } - ], - "pool_size": -1, - "used_size": 23520 - } - } -} \ No newline at end of file diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.ai/sww_model_null_c_info.json b/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.ai/sww_model_null_c_info.json deleted file mode 100644 index 01d41d54..00000000 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.ai/sww_model_null_c_info.json +++ /dev/null @@ -1,3304 +0,0 @@ -{ - "buffers": [ - { - "alignment": 4, - "batch": 0, - "channel_first": true, - "channel_last": true, - "epochs": { - "end": 1, - "start": 0 - }, - "flags": "STAI_FLAG_WEIGHTS|STAI_FLAG_CONST|STAI_FLAG_PREALLOCATED", - "format": "STAI_FORMAT_S32", - "id": 236, - "intq": { - "axis": null, - "offsets": [], - "scales": [] - }, - "is_param": true, - "mpool_id": 1, - "name": "conv2d_0_bias_array", - "nbits": 32, - "offset_start": 120, - "qmn": {}, - "shape": [ - 40 - ], - "shape_map": [ - "CH" - ], - "size_bytes": 160 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": false, - "channel_last": true, - "epochs": { - "end": 9, - "start": 4 - }, - "flags": "STAI_FLAG_PREALLOCATED|STAI_FLAG_ACTIVATIONS", - "format": "STAI_FORMAT_S8", - "id": 213, - "intq": { - "axis": 2, - "offsets": [ - -3 - ], - "scales": [ - 0.0018045719480141997 - ] - }, - "is_param": false, - "mpool_id": 0, - "name": "conv2d_0_output_array", - "nbits": 8, - "offset_start": 2120, - "qmn": {}, - "shape": [ - 28, - 1, - 40 - ], - "shape_map": [ - "H", - "W", - "CH" - ], - "size_bytes": 1120 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": false, - "channel_last": true, - "epochs": { - "end": 6, - "start": 3 - }, - "flags": "STAI_FLAG_PREALLOCATED|STAI_FLAG_ACTIVATIONS|STAI_FLAG_SCRATCHS", - "format": "STAI_FORMAT_S8", - "id": 290, - "intq": { - "axis": null, - "offsets": [], - "scales": [] - }, - "is_param": false, - "mpool_id": 0, - "name": "conv2d_0_scratch0_array", - "nbits": 8, - "offset_start": 3360, - "qmn": {}, - "shape": [ - 1, - 1, - 761, - 1 - ], - "shape_map": [ - "H", - "W", - "CH", - "CH_IN" - ], - "size_bytes": 761 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": true, - "channel_last": false, - "epochs": { - "end": 1, - "start": 0 - }, - "flags": "STAI_FLAG_WEIGHTS|STAI_FLAG_CONST|STAI_FLAG_PREALLOCATED", - "format": "STAI_FORMAT_S8", - "id": 233, - "intq": { - "axis": 3, - "offsets": [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0 - ], - "scales": [ - 0.001642347895540297, - 0.0012464334722608328, - 0.0018808494787663221, - 0.0017687849467620254, - 0.002232156926766038, - 0.0017221078742295504, - 0.0016933622537180781, - 0.001586283789947629, - 0.0019639935344457626, - 0.0017922259867191315, - 0.0018330850871279836, - 0.0015503712929785252, - 0.001953525235876441, - 0.0015549628296867013, - 0.0024999254383146763, - 0.0009487768402323127, - 0.001722460612654686, - 0.0016345441108569503, - 0.0006262531387619674, - 0.002148588187992573, - 0.0017868067370727658, - 0.0016791783273220062, - 0.0007694695959798992, - 0.0016042999923229218, - 0.002147432416677475, - 0.0026659697759896517, - 0.0016246186569333076, - 0.0015353725757449865, - 0.0013496452011168003, - 0.0010453679133206606, - 0.001754468074068427, - 0.0023172975052148104, - 0.0015870793722569942, - 0.0014503091806545854, - 0.0011753877624869347, - 0.0009309005690738559, - 0.0022590768057852983, - 0.0019405314233154058, - 0.0022477428428828716, - 0.0010750620858743787 - ] - }, - "is_param": true, - "mpool_id": 1, - "name": "conv2d_0_weights_array", - "nbits": 8, - "offset_start": 0, - "qmn": {}, - "shape": [ - 1, - 3, - 1, - 40 - ], - "shape_map": [ - "CH", - "H", - "W", - "CH_IN" - ], - "size_bytes": 120 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": true, - "channel_last": true, - "epochs": { - "end": 1, - "start": 0 - }, - "flags": "STAI_FLAG_WEIGHTS|STAI_FLAG_CONST|STAI_FLAG_PREALLOCATED", - "format": "STAI_FORMAT_S32", - "id": 242, - "intq": { - "axis": null, - "offsets": [], - "scales": [] - }, - "is_param": true, - "mpool_id": 1, - "name": "conv2d_1_bias_array", - "nbits": 32, - "offset_start": 4600, - "qmn": {}, - "shape": [ - 108 - ], - "shape_map": [ - "CH" - ], - "size_bytes": 432 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": false, - "channel_last": true, - "epochs": { - "end": 13, - "start": 8 - }, - "flags": "STAI_FLAG_PREALLOCATED|STAI_FLAG_ACTIVATIONS", - "format": "STAI_FORMAT_S8", - "id": 215, - "intq": { - "axis": 2, - "offsets": [ - -128 - ], - "scales": [ - 0.007331364788115025 - ] - }, - "is_param": false, - "mpool_id": 0, - "name": "conv2d_1_output_array", - "nbits": 8, - "offset_start": 108, - "qmn": {}, - "shape": [ - 28, - 1, - 108 - ], - "shape_map": [ - "H", - "W", - "CH" - ], - "size_bytes": 3024 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": false, - "channel_last": true, - "epochs": { - "end": 10, - "start": 7 - }, - "flags": "STAI_FLAG_PREALLOCATED|STAI_FLAG_ACTIVATIONS|STAI_FLAG_SCRATCHS", - "format": "STAI_FORMAT_S8", - "id": 296, - "intq": { - "axis": null, - "offsets": [], - "scales": [] - }, - "is_param": false, - "mpool_id": 0, - "name": "conv2d_1_scratch0_array", - "nbits": 8, - "offset_start": 3240, - "qmn": {}, - "shape": [ - 1, - 1, - 1240, - 1 - ], - "shape_map": [ - "H", - "W", - "CH", - "CH_IN" - ], - "size_bytes": 1240 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": true, - "channel_last": false, - "epochs": { - "end": 1, - "start": 0 - }, - "flags": "STAI_FLAG_WEIGHTS|STAI_FLAG_CONST|STAI_FLAG_PREALLOCATED", - "format": "STAI_FORMAT_S8", - "id": 239, - "intq": { - "axis": 3, - "offsets": [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0 - ], - "scales": [ - 0.03843778744339943, - 0.03424474969506264, - 0.017642157152295113, - 0.016672806814312935, - 0.02117191255092621, - 0.030264290049672127, - 0.027997097000479698, - 0.024589020758867264, - 0.013011130504310131, - 0.025482743978500366, - 0.02170688845217228, - 0.020765338093042374, - 0.004156722687184811, - 0.01876024156808853, - 0.028028424829244614, - 0.0335012711584568, - 0.028314050287008286, - 0.02842898666858673, - 0.024900702759623528, - 0.022218992933630943, - 0.028063176199793816, - 0.03321857750415802, - 0.02153550460934639, - 0.03990000858902931, - 0.020548759028315544, - 0.03405828773975372, - 0.02318909764289856, - 0.023638205602765083, - 0.019964933395385742, - 0.03596772626042366, - 0.01502156537026167, - 0.03389132022857666, - 0.022404439747333527, - 0.03430989757180214, - 0.03384352847933769, - 0.027794936671853065, - 0.017100447788834572, - 0.01263357698917389, - 0.040574971586465836, - 0.037140779197216034, - 0.031087808310985565, - 0.04442266374826431, - 0.037988293915987015, - 0.029726577922701836, - 0.031557273119688034, - 0.03631843999028206, - 0.025610091164708138, - 0.018468542024493217, - 0.021165795624256134, - 0.02730490453541279, - 0.012819893658161163, - 0.02316182851791382, - 0.026402035728096962, - 0.02412860468029976, - 0.04931594803929329, - 0.031328584998846054, - 0.02464168332517147, - 0.021940257400274277, - 0.035059619694948196, - 0.037006113678216934, - 0.03842802345752716, - 0.03353657200932503, - 0.026503458619117737, - 0.03792215883731842, - 0.027321206405758858, - 0.029820093885064125, - 0.0310662854462862, - 0.029756441712379456, - 0.024783749133348465, - 0.015829073265194893, - 0.022009551525115967, - 0.03166014701128006, - 0.016863781958818436, - 0.029639851301908493, - 0.03000551462173462, - 0.01928015798330307, - 0.02872774749994278, - 0.03196508064866066, - 0.03661493584513664, - 0.025833558291196823, - 0.03245000168681145, - 0.02557412162423134, - 0.02539031393826008, - 0.03885124996304512, - 0.027298370376229286, - 0.030694743618369102, - 0.023782826960086823, - 0.013601325452327728, - 0.016648098826408386, - 0.019702767953276634, - 0.04989137127995491, - 0.01952550560235977, - 0.011950946412980556, - 0.020136114209890366, - 0.0188601054251194, - 0.031969454139471054, - 0.015985149890184402, - 0.022637400776147842, - 0.0029883950483053923, - 0.009722628630697727, - 0.023238789290189743, - 0.018725885078310966, - 0.03747653216123581, - 0.0312572605907917, - 0.027069244533777237, - 0.019321395084261894, - 0.01773461326956749, - 0.02210475318133831 - ] - }, - "is_param": true, - "mpool_id": 1, - "name": "conv2d_1_weights_array", - "nbits": 8, - "offset_start": 280, - "qmn": {}, - "shape": [ - 108, - 1, - 1, - 40 - ], - "shape_map": [ - "CH", - "H", - "W", - "CH_IN" - ], - "size_bytes": 4320 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": true, - "channel_last": true, - "epochs": { - "end": 1, - "start": 0 - }, - "flags": "STAI_FLAG_WEIGHTS|STAI_FLAG_CONST|STAI_FLAG_PREALLOCATED", - "format": "STAI_FORMAT_S32", - "id": 248, - "intq": { - "axis": null, - "offsets": [], - "scales": [] - }, - "is_param": true, - "mpool_id": 1, - "name": "conv2d_2_bias_array", - "nbits": 32, - "offset_start": 5572, - "qmn": {}, - "shape": [ - 108 - ], - "shape_map": [ - "CH" - ], - "size_bytes": 432 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": false, - "channel_last": true, - "epochs": { - "end": 17, - "start": 12 - }, - "flags": "STAI_FLAG_PREALLOCATED|STAI_FLAG_ACTIVATIONS", - "format": "STAI_FORMAT_S8", - "id": 217, - "intq": { - "axis": 2, - "offsets": [ - 4 - ], - "scales": [ - 0.0033829212188720703 - ] - }, - "is_param": false, - "mpool_id": 0, - "name": "conv2d_2_output_array", - "nbits": 8, - "offset_start": 0, - "qmn": {}, - "shape": [ - 24, - 1, - 108 - ], - "shape_map": [ - "H", - "W", - "CH" - ], - "size_bytes": 2592 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": false, - "channel_last": true, - "epochs": { - "end": 14, - "start": 11 - }, - "flags": "STAI_FLAG_PREALLOCATED|STAI_FLAG_ACTIVATIONS|STAI_FLAG_SCRATCHS", - "format": "STAI_FORMAT_S8", - "id": 302, - "intq": { - "axis": null, - "offsets": [], - "scales": [] - }, - "is_param": false, - "mpool_id": 0, - "name": "conv2d_2_scratch0_array", - "nbits": 8, - "offset_start": 3132, - "qmn": {}, - "shape": [ - 1, - 1, - 2701, - 1 - ], - "shape_map": [ - "H", - "W", - "CH", - "CH_IN" - ], - "size_bytes": 2701 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": true, - "channel_last": false, - "epochs": { - "end": 1, - "start": 0 - }, - "flags": "STAI_FLAG_WEIGHTS|STAI_FLAG_CONST|STAI_FLAG_PREALLOCATED", - "format": "STAI_FORMAT_S8", - "id": 245, - "intq": { - "axis": 3, - "offsets": [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0 - ], - "scales": [ - 0.0012193449074402452, - 0.0011896206997334957, - 0.001150784082710743, - 0.0015751051250845194, - 0.0014076937222853303, - 0.0014134043594822288, - 0.0012166631640866399, - 0.0008614432299509645, - 0.0013119303621351719, - 0.0010421304032206535, - 0.001792778610251844, - 0.0006943026673980057, - 0.0012489653890952468, - 0.0016015503788366914, - 0.0013164817355573177, - 0.0014498716918751597, - 0.0009809196926653385, - 0.0012443828163668513, - 0.0015893805539235473, - 0.0012252413434907794, - 0.00146100006531924, - 0.0012698895297944546, - 0.0009081409662030637, - 0.0011611015070229769, - 0.0014941409463062882, - 0.0014062923146411777, - 0.0014375756727531552, - 0.0011015296913683414, - 0.0011722077615559101, - 0.0017788897966966033, - 0.0015201474307104945, - 0.001466955873183906, - 0.001193762058392167, - 0.0011754519073292613, - 0.0010366021888330579, - 0.0011002852115780115, - 0.0012190159177407622, - 0.0009785162983462214, - 0.0015096979914233088, - 0.0014507253654301167, - 0.001522812177427113, - 0.0011339515913277864, - 0.0012347951997071505, - 0.0017208375502377748, - 0.0012510899687185884, - 0.0011507170274853706, - 0.0015958300791680813, - 0.0011514110956341028, - 0.0014947318704798818, - 0.0015390361659228802, - 0.0009209638810716569, - 0.0016760819125920534, - 0.0009958102600649, - 0.0012021957663819194, - 0.0016008286038413644, - 0.0010758097050711513, - 0.0013621337711811066, - 0.0010371701791882515, - 0.001484634238295257, - 0.0015296931378543377, - 0.0014479142846539617, - 0.0018752461764961481, - 0.0011389135615900159, - 0.0015793287893757224, - 0.0010704681044444442, - 0.0014446311397477984, - 0.001430619740858674, - 0.0011343255173414946, - 0.0014109080657362938, - 0.0011780846398323774, - 0.0013960669748485088, - 0.0012521182652562857, - 0.0012801842531189322, - 0.0010166580323129892, - 0.0011850884184241295, - 0.001457210979424417, - 0.0013643177226185799, - 0.0011476562358438969, - 0.0009190457058139145, - 0.001462473999708891, - 0.0015686636324971914, - 0.000985241960734129, - 0.0012081931345164776, - 0.0012406273745000362, - 0.001423214445821941, - 0.0013334010727703571, - 0.001554172020405531, - 0.0012627579271793365, - 0.0013837196165695786, - 0.0015174734871834517, - 0.0016533306334167719, - 0.0016571376472711563, - 0.0010685668094083667, - 0.0012777920346707106, - 0.0012865728931501508, - 0.0013592647155746818, - 0.0013121356023475528, - 0.0010990258306264877, - 0.0009446862968616188, - 0.0011264465283602476, - 0.0014283916680142283, - 0.0011742946226149797, - 0.001202662126161158, - 0.0012340721441432834, - 0.0010347074130550027, - 0.0010912242578342557, - 0.0016451962292194366, - 0.0012853143271058798 - ] - }, - "is_param": true, - "mpool_id": 1, - "name": "conv2d_2_weights_array", - "nbits": 8, - "offset_start": 5032, - "qmn": {}, - "shape": [ - 1, - 5, - 1, - 108 - ], - "shape_map": [ - "CH", - "H", - "W", - "CH_IN" - ], - "size_bytes": 540 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": true, - "channel_last": true, - "epochs": { - "end": 1, - "start": 0 - }, - "flags": "STAI_FLAG_WEIGHTS|STAI_FLAG_CONST|STAI_FLAG_PREALLOCATED", - "format": "STAI_FORMAT_S32", - "id": 254, - "intq": { - "axis": null, - "offsets": [], - "scales": [] - }, - "is_param": true, - "mpool_id": 1, - "name": "conv2d_3_bias_array", - "nbits": 32, - "offset_start": 14752, - "qmn": {}, - "shape": [ - 81 - ], - "shape_map": [ - "CH" - ], - "size_bytes": 324 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": false, - "channel_last": true, - "epochs": { - "end": 21, - "start": 16 - }, - "flags": "STAI_FLAG_PREALLOCATED|STAI_FLAG_ACTIVATIONS", - "format": "STAI_FORMAT_S8", - "id": 219, - "intq": { - "axis": 2, - "offsets": [ - -128 - ], - "scales": [ - 0.008522006683051586 - ] - }, - "is_param": false, - "mpool_id": 0, - "name": "conv2d_3_output_array", - "nbits": 8, - "offset_start": 3836, - "qmn": {}, - "shape": [ - 24, - 1, - 81 - ], - "shape_map": [ - "H", - "W", - "CH" - ], - "size_bytes": 1944 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": false, - "channel_last": true, - "epochs": { - "end": 18, - "start": 15 - }, - "flags": "STAI_FLAG_PREALLOCATED|STAI_FLAG_ACTIVATIONS|STAI_FLAG_SCRATCHS", - "format": "STAI_FORMAT_S8", - "id": 308, - "intq": { - "axis": null, - "offsets": [], - "scales": [] - }, - "is_param": false, - "mpool_id": 0, - "name": "conv2d_3_scratch0_array", - "nbits": 8, - "offset_start": 2592, - "qmn": {}, - "shape": [ - 1, - 1, - 1242, - 1 - ], - "shape_map": [ - "H", - "W", - "CH", - "CH_IN" - ], - "size_bytes": 1242 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": true, - "channel_last": false, - "epochs": { - "end": 1, - "start": 0 - }, - "flags": "STAI_FLAG_WEIGHTS|STAI_FLAG_CONST|STAI_FLAG_PREALLOCATED", - "format": "STAI_FORMAT_S8", - "id": 251, - "intq": { - "axis": 3, - "offsets": [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0 - ], - "scales": [ - 0.015128846280276775, - 0.015573011711239815, - 0.016271857544779778, - 0.014132648706436157, - 0.018094440922141075, - 0.020049450919032097, - 0.018400095403194427, - 0.017870919778943062, - 0.016350913792848587, - 0.014747311361134052, - 0.017187248915433884, - 0.016289183869957924, - 0.015324003994464874, - 0.02062303200364113, - 0.01638767123222351, - 0.014158428646624088, - 0.01555232796818018, - 0.02522544004023075, - 0.01610005833208561, - 0.02466684952378273, - 0.018511435016989708, - 0.015439994633197784, - 0.012423139996826649, - 0.018430529162287712, - 0.013635613955557346, - 0.013857602141797543, - 0.016926752403378487, - 0.019769813865423203, - 0.026674576103687286, - 0.01582067273557186, - 0.01869085244834423, - 0.016557810828089714, - 0.010478632524609566, - 0.016589654609560966, - 0.017770716920495033, - 0.015888260677456856, - 0.018635224550962448, - 0.016906341537833214, - 0.02251080609858036, - 0.01092725433409214, - 0.018775317817926407, - 0.01914645917713642, - 0.021332694217562675, - 0.011556758545339108, - 0.017348820343613625, - 0.017436355352401733, - 0.01638859696686268, - 0.01837228797376156, - 0.01729300431907177, - 0.015137557871639729, - 0.020055970177054405, - 0.016387302428483963, - 0.015314789488911629, - 0.015308589674532413, - 0.014827247709035873, - 0.016430499032139778, - 0.016709063202142715, - 0.0161450132727623, - 0.0203449334949255, - 0.016926869750022888, - 0.015119430609047413, - 0.013861013576388359, - 0.012870672158896923, - 0.018918493762612343, - 0.015354461036622524, - 0.00960373505949974, - 0.012707964517176151, - 0.015196085907518864, - 0.012715458869934082, - 0.019194994121789932, - 0.014486822299659252, - 0.020452536642551422, - 0.020936153829097748, - 0.016988983377814293, - 0.013276669196784496, - 0.016756894066929817, - 0.01643085852265358, - 0.019164972007274628, - 0.018671797588467598, - 0.014429536648094654, - 0.01753745600581169 - ] - }, - "is_param": true, - "mpool_id": 1, - "name": "conv2d_3_weights_array", - "nbits": 8, - "offset_start": 6004, - "qmn": {}, - "shape": [ - 81, - 1, - 1, - 108 - ], - "shape_map": [ - "CH", - "H", - "W", - "CH_IN" - ], - "size_bytes": 8748 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": true, - "channel_last": true, - "epochs": { - "end": 1, - "start": 0 - }, - "flags": "STAI_FLAG_WEIGHTS|STAI_FLAG_CONST|STAI_FLAG_PREALLOCATED", - "format": "STAI_FORMAT_S32", - "id": 260, - "intq": { - "axis": null, - "offsets": [], - "scales": [] - }, - "is_param": true, - "mpool_id": 1, - "name": "conv2d_4_bias_array", - "nbits": 32, - "offset_start": 15888, - "qmn": {}, - "shape": [ - 81 - ], - "shape_map": [ - "CH" - ], - "size_bytes": 324 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": false, - "channel_last": true, - "epochs": { - "end": 25, - "start": 20 - }, - "flags": "STAI_FLAG_PREALLOCATED|STAI_FLAG_ACTIVATIONS", - "format": "STAI_FORMAT_S8", - "id": 221, - "intq": { - "axis": 2, - "offsets": [ - 17 - ], - "scales": [ - 0.005995603743940592 - ] - }, - "is_param": false, - "mpool_id": 0, - "name": "conv2d_4_output_array", - "nbits": 8, - "offset_start": 3752, - "qmn": {}, - "shape": [ - 15, - 1, - 81 - ], - "shape_map": [ - "H", - "W", - "CH" - ], - "size_bytes": 1215 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": false, - "channel_last": true, - "epochs": { - "end": 22, - "start": 19 - }, - "flags": "STAI_FLAG_PREALLOCATED|STAI_FLAG_ACTIVATIONS|STAI_FLAG_SCRATCHS", - "format": "STAI_FORMAT_S8", - "id": 314, - "intq": { - "axis": null, - "offsets": [], - "scales": [] - }, - "is_param": false, - "mpool_id": 0, - "name": "conv2d_4_scratch0_array", - "nbits": 8, - "offset_start": 0, - "qmn": {}, - "shape": [ - 1, - 1, - 3241, - 1 - ], - "shape_map": [ - "H", - "W", - "CH", - "CH_IN" - ], - "size_bytes": 3241 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": true, - "channel_last": false, - "epochs": { - "end": 1, - "start": 0 - }, - "flags": "STAI_FLAG_WEIGHTS|STAI_FLAG_CONST|STAI_FLAG_PREALLOCATED", - "format": "STAI_FORMAT_S8", - "id": 257, - "intq": { - "axis": 3, - "offsets": [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0 - ], - "scales": [ - 0.0013209173921495676, - 0.0013699670089408755, - 0.0011900769313797355, - 0.0014234690461307764, - 0.0012966083595529199, - 0.002158000133931637, - 0.0013979612849652767, - 0.0010544935939833522, - 0.0008681811159476638, - 0.0014393681194633245, - 0.0018609057879075408, - 0.0013464994262903929, - 0.0008672561962157488, - 0.001372328493744135, - 0.0013065575622022152, - 0.0015507722273468971, - 0.0015574434073641896, - 0.0016854808200150728, - 0.0012486601481214166, - 0.0021874085068702698, - 0.0014007712015882134, - 0.0017165332101285458, - 0.0020851553417742252, - 0.0020932801999151707, - 0.001796632306650281, - 0.0014638400170952082, - 0.0019234605133533478, - 0.002710780594497919, - 0.0012269431026652455, - 0.0010644309222698212, - 0.0014495650539174676, - 0.0013952819863334298, - 0.0015238363994285464, - 0.0015330613823607564, - 0.001806235290132463, - 0.0015545615460723639, - 0.001962702488526702, - 0.0018692143494263291, - 0.002919284626841545, - 0.0011838754871860147, - 0.0014690218959003687, - 0.001570309977978468, - 0.0016600311500951648, - 0.001322298077866435, - 0.001086729229427874, - 0.00108465610537678, - 0.0016869003884494305, - 0.002073693787679076, - 0.0013331201625987887, - 0.0013437183806672692, - 0.0009963620686903596, - 0.0015516714192926884, - 0.0024561795871704817, - 0.001887949532829225, - 0.0019081522477790713, - 0.0018222932703793049, - 0.0012474765535444021, - 0.001181218191049993, - 0.0011141691356897354, - 0.0026841002982109785, - 0.00209209811873734, - 0.0012199511984363198, - 0.0012844110606238246, - 0.0020877672359347343, - 0.0014856132911518216, - 0.0009970106184482574, - 0.001144768437370658, - 0.0020951591432094574, - 0.0013088099658489227, - 0.0008139606798067689, - 0.0014311781851574779, - 0.0024156002327799797, - 0.0010804146295413375, - 0.001683399430476129, - 0.0019631627947092056, - 0.0013160593807697296, - 0.001466938410885632, - 0.001094481791369617, - 0.0015286278212442994, - 0.0013401331380009651, - 0.0011197495041415095 - ] - }, - "is_param": true, - "mpool_id": 1, - "name": "conv2d_4_weights_array", - "nbits": 8, - "offset_start": 15076, - "qmn": {}, - "shape": [ - 1, - 10, - 1, - 81 - ], - "shape_map": [ - "CH", - "H", - "W", - "CH_IN" - ], - "size_bytes": 810 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": true, - "channel_last": true, - "epochs": { - "end": 1, - "start": 0 - }, - "flags": "STAI_FLAG_WEIGHTS|STAI_FLAG_CONST|STAI_FLAG_PREALLOCATED", - "format": "STAI_FORMAT_S32", - "id": 266, - "intq": { - "axis": null, - "offsets": [], - "scales": [] - }, - "is_param": true, - "mpool_id": 1, - "name": "conv2d_5_bias_array", - "nbits": 32, - "offset_start": 20424, - "qmn": {}, - "shape": [ - 52 - ], - "shape_map": [ - "CH" - ], - "size_bytes": 208 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": false, - "channel_last": true, - "epochs": { - "end": 29, - "start": 24 - }, - "flags": "STAI_FLAG_PREALLOCATED|STAI_FLAG_ACTIVATIONS", - "format": "STAI_FORMAT_S8", - "id": 223, - "intq": { - "axis": 2, - "offsets": [ - -128 - ], - "scales": [ - 0.012133517302572727 - ] - }, - "is_param": false, - "mpool_id": 0, - "name": "conv2d_5_output_array", - "nbits": 8, - "offset_start": 844, - "qmn": {}, - "shape": [ - 15, - 1, - 52 - ], - "shape_map": [ - "H", - "W", - "CH" - ], - "size_bytes": 780 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": false, - "channel_last": true, - "epochs": { - "end": 26, - "start": 23 - }, - "flags": "STAI_FLAG_PREALLOCATED|STAI_FLAG_ACTIVATIONS|STAI_FLAG_SCRATCHS", - "format": "STAI_FORMAT_S8", - "id": 320, - "intq": { - "axis": null, - "offsets": [], - "scales": [] - }, - "is_param": false, - "mpool_id": 0, - "name": "conv2d_5_scratch0_array", - "nbits": 8, - "offset_start": 0, - "qmn": {}, - "shape": [ - 1, - 1, - 844, - 1 - ], - "shape_map": [ - "H", - "W", - "CH", - "CH_IN" - ], - "size_bytes": 844 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": true, - "channel_last": false, - "epochs": { - "end": 1, - "start": 0 - }, - "flags": "STAI_FLAG_WEIGHTS|STAI_FLAG_CONST|STAI_FLAG_PREALLOCATED", - "format": "STAI_FORMAT_S8", - "id": 263, - "intq": { - "axis": 3, - "offsets": [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0 - ], - "scales": [ - 0.015773683786392212, - 0.017180703580379486, - 0.016543541103601456, - 0.012180080637335777, - 0.012121811509132385, - 0.01948302611708641, - 0.01332039199769497, - 0.008291282691061497, - 0.006536763161420822, - 0.01492640282958746, - 0.015078308060765266, - 0.01259052287787199, - 0.014905902557075024, - 0.009477532468736172, - 0.017825616523623466, - 0.0100540891289711, - 0.01577778160572052, - 0.007912426255643368, - 0.013099128380417824, - 0.011292265728116035, - 0.014415361918509007, - 0.01442705001682043, - 0.0154510997235775, - 0.01196146011352539, - 0.011186054907739162, - 0.011584583669900894, - 0.012372108176350594, - 0.009474975988268852, - 0.015400659292936325, - 0.015521892346441746, - 0.009775904938578606, - 0.014177525416016579, - 0.018218280747532845, - 0.012715878896415234, - 0.01842585951089859, - 0.014037981629371643, - 0.012311501428484917, - 0.013712716288864613, - 0.010050556622445583, - 0.011510557495057583, - 0.015110366977751255, - 0.017335738986730576, - 0.011255898512899876, - 0.010579855181276798, - 0.007013300433754921, - 0.00525946170091629, - 0.010228436440229416, - 0.014367306604981422, - 0.012811205349862576, - 0.009629661217331886, - 0.00906060915440321, - 0.013815436512231827 - ] - }, - "is_param": true, - "mpool_id": 1, - "name": "conv2d_5_weights_array", - "nbits": 8, - "offset_start": 16212, - "qmn": {}, - "shape": [ - 52, - 1, - 1, - 81 - ], - "shape_map": [ - "CH", - "H", - "W", - "CH_IN" - ], - "size_bytes": 4212 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": true, - "channel_last": true, - "epochs": { - "end": 1, - "start": 0 - }, - "flags": "STAI_FLAG_WEIGHTS|STAI_FLAG_CONST|STAI_FLAG_PREALLOCATED", - "format": "STAI_FORMAT_S32", - "id": 272, - "intq": { - "axis": null, - "offsets": [], - "scales": [] - }, - "is_param": true, - "mpool_id": 1, - "name": "conv2d_6_bias_array", - "nbits": 32, - "offset_start": 21412, - "qmn": {}, - "shape": [ - 52 - ], - "shape_map": [ - "CH" - ], - "size_bytes": 208 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": false, - "channel_last": true, - "epochs": { - "end": 33, - "start": 28 - }, - "flags": "STAI_FLAG_PREALLOCATED|STAI_FLAG_ACTIVATIONS", - "format": "STAI_FORMAT_S8", - "id": 225, - "intq": { - "axis": 2, - "offsets": [ - 3 - ], - "scales": [ - 0.014823319390416145 - ] - }, - "is_param": false, - "mpool_id": 0, - "name": "conv2d_6_output_array", - "nbits": 8, - "offset_start": 0, - "qmn": {}, - "shape": [ - 1, - 1, - 52 - ], - "shape_map": [ - "H", - "W", - "CH" - ], - "size_bytes": 52 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": false, - "channel_last": true, - "epochs": { - "end": 30, - "start": 27 - }, - "flags": "STAI_FLAG_PREALLOCATED|STAI_FLAG_ACTIVATIONS|STAI_FLAG_SCRATCHS", - "format": "STAI_FORMAT_S8", - "id": 326, - "intq": { - "axis": null, - "offsets": [], - "scales": [] - }, - "is_param": false, - "mpool_id": 0, - "name": "conv2d_6_scratch0_array", - "nbits": 8, - "offset_start": 1624, - "qmn": {}, - "shape": [ - 1, - 1, - 2861, - 1 - ], - "shape_map": [ - "H", - "W", - "CH", - "CH_IN" - ], - "size_bytes": 2861 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": true, - "channel_last": false, - "epochs": { - "end": 1, - "start": 0 - }, - "flags": "STAI_FLAG_WEIGHTS|STAI_FLAG_CONST|STAI_FLAG_PREALLOCATED", - "format": "STAI_FORMAT_S8", - "id": 269, - "intq": { - "axis": 3, - "offsets": [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0 - ], - "scales": [ - 0.0012915823608636856, - 0.0012511053355410695, - 0.0011855724733322859, - 0.0025645773857831955, - 0.001079620560631156, - 0.0017146256286650896, - 0.0011722984490916133, - 0.0011089964536949992, - 0.0021147746592760086, - 0.0019927872344851494, - 0.0014550697524100542, - 0.002831965684890747, - 0.0018483612220734358, - 0.0008478033705614507, - 0.0018396616214886308, - 0.0021623552311211824, - 0.0019630850292742252, - 0.0017485704738646746, - 0.0021983326878398657, - 0.0011710221879184246, - 0.002634496660903096, - 0.0015223354566842318, - 0.0019060292979702353, - 0.0017563101137056947, - 0.0020001009106636047, - 0.0017203905154019594, - 0.0009780041873455048, - 0.0009349649189971387, - 0.0010179498931393027, - 0.002921813866123557, - 0.001127480762079358, - 0.002835941733792424, - 0.0025946912355720997, - 0.0017454741755500436, - 0.0021075394470244646, - 0.0013835849240422249, - 0.00247604469768703, - 0.0010387442307546735, - 0.0026010600849986076, - 0.0020862752571702003, - 0.0010696039535105228, - 0.0024096250999718904, - 0.001306817983277142, - 0.0008883686969056726, - 0.0018930664518848062, - 0.0010039584012702107, - 0.0013365934137254953, - 0.0024195443838834763, - 0.0014412919990718365, - 0.001000774442218244, - 0.0019087563268840313, - 0.0025204240810126066 - ] - }, - "is_param": true, - "mpool_id": 1, - "name": "conv2d_6_weights_array", - "nbits": 8, - "offset_start": 20632, - "qmn": {}, - "shape": [ - 1, - 15, - 1, - 52 - ], - "shape_map": [ - "CH", - "H", - "W", - "CH_IN" - ], - "size_bytes": 780 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": true, - "channel_last": true, - "epochs": { - "end": 1, - "start": 0 - }, - "flags": "STAI_FLAG_WEIGHTS|STAI_FLAG_CONST|STAI_FLAG_PREALLOCATED", - "format": "STAI_FORMAT_S32", - "id": 278, - "intq": { - "axis": null, - "offsets": [], - "scales": [] - }, - "is_param": true, - "mpool_id": 1, - "name": "conv2d_7_bias_array", - "nbits": 32, - "offset_start": 23284, - "qmn": {}, - "shape": [ - 32 - ], - "shape_map": [ - "CH" - ], - "size_bytes": 128 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": false, - "channel_last": true, - "epochs": { - "end": 37, - "start": 32 - }, - "flags": "STAI_FLAG_PREALLOCATED|STAI_FLAG_ACTIVATIONS", - "format": "STAI_FORMAT_S8", - "id": 227, - "intq": { - "axis": 2, - "offsets": [ - -128 - ], - "scales": [ - 0.018331341445446014 - ] - }, - "is_param": false, - "mpool_id": 0, - "name": "conv2d_7_output_array", - "nbits": 8, - "offset_start": 580, - "qmn": {}, - "shape": [ - 1, - 1, - 32 - ], - "shape_map": [ - "H", - "W", - "CH" - ], - "size_bytes": 32 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": false, - "channel_last": true, - "epochs": { - "end": 34, - "start": 31 - }, - "flags": "STAI_FLAG_PREALLOCATED|STAI_FLAG_ACTIVATIONS|STAI_FLAG_SCRATCHS", - "format": "STAI_FORMAT_S8", - "id": 332, - "intq": { - "axis": null, - "offsets": [], - "scales": [] - }, - "is_param": false, - "mpool_id": 0, - "name": "conv2d_7_scratch0_array", - "nbits": 8, - "offset_start": 52, - "qmn": {}, - "shape": [ - 1, - 1, - 528, - 1 - ], - "shape_map": [ - "H", - "W", - "CH", - "CH_IN" - ], - "size_bytes": 528 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": true, - "channel_last": false, - "epochs": { - "end": 1, - "start": 0 - }, - "flags": "STAI_FLAG_WEIGHTS|STAI_FLAG_CONST|STAI_FLAG_PREALLOCATED", - "format": "STAI_FORMAT_S8", - "id": 275, - "intq": { - "axis": 3, - "offsets": [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0 - ], - "scales": [ - 0.007534192409366369, - 0.005160065367817879, - 0.00863321591168642, - 0.011691645719110966, - 0.007065467070788145, - 0.013616980984807014, - 0.010354913771152496, - 0.005401516333222389, - 0.00899604894220829, - 0.008329877629876137, - 0.009429126977920532, - 0.00915415771305561, - 0.012206453830003738, - 0.007751247379928827, - 0.008157746866345406, - 0.006608979310840368, - 0.008793451823294163, - 0.00995804462581873, - 0.00625076936557889, - 0.005368341226130724, - 0.009286150336265564, - 0.009581937454640865, - 0.00813126377761364, - 0.007290022913366556, - 0.006840443704277277, - 0.0074807205237448215, - 0.009476734325289726, - 0.008071377873420715, - 0.006180003751069307, - 0.011818638071417809, - 0.008427681401371956, - 0.009211544878780842 - ] - }, - "is_param": true, - "mpool_id": 1, - "name": "conv2d_7_weights_array", - "nbits": 8, - "offset_start": 21620, - "qmn": {}, - "shape": [ - 32, - 1, - 1, - 52 - ], - "shape_map": [ - "CH", - "H", - "W", - "CH_IN" - ], - "size_bytes": 1664 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": true, - "channel_last": true, - "epochs": { - "end": 1, - "start": 0 - }, - "flags": "STAI_FLAG_WEIGHTS|STAI_FLAG_CONST|STAI_FLAG_PREALLOCATED", - "format": "STAI_FORMAT_S32", - "id": 284, - "intq": { - "axis": null, - "offsets": [], - "scales": [] - }, - "is_param": true, - "mpool_id": 1, - "name": "gemm_9_bias_array", - "nbits": 32, - "offset_start": 23508, - "qmn": {}, - "shape": [ - 3 - ], - "shape_map": [ - "CH" - ], - "size_bytes": 12 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": true, - "channel_last": true, - "epochs": { - "end": 41, - "start": 36 - }, - "flags": "STAI_FLAG_PREALLOCATED|STAI_FLAG_ACTIVATIONS", - "format": "STAI_FORMAT_S8", - "id": 229, - "intq": { - "axis": 0, - "offsets": [ - 30 - ], - "scales": [ - 0.14710605144500732 - ] - }, - "is_param": false, - "mpool_id": 0, - "name": "gemm_9_output_array", - "nbits": 8, - "offset_start": 64, - "qmn": {}, - "shape": [ - 3 - ], - "shape_map": [ - "CH" - ], - "size_bytes": 3 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": false, - "channel_last": true, - "epochs": { - "end": 38, - "start": 35 - }, - "flags": "STAI_FLAG_PREALLOCATED|STAI_FLAG_ACTIVATIONS|STAI_FLAG_SCRATCHS", - "format": "STAI_FORMAT_S16", - "id": 338, - "intq": { - "axis": null, - "offsets": [], - "scales": [] - }, - "is_param": false, - "mpool_id": 0, - "name": "gemm_9_scratch0_array", - "nbits": 16, - "offset_start": 0, - "qmn": {}, - "shape": [ - 1, - 1, - 32, - 1 - ], - "shape_map": [ - "H", - "W", - "CH", - "CH_IN" - ], - "size_bytes": 64 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": true, - "channel_last": true, - "epochs": { - "end": 1, - "start": 0 - }, - "flags": "STAI_FLAG_WEIGHTS|STAI_FLAG_CONST|STAI_FLAG_PREALLOCATED", - "format": "STAI_FORMAT_S8", - "id": 281, - "intq": { - "axis": 1, - "offsets": [ - 0 - ], - "scales": [ - 0.01235697977244854 - ] - }, - "is_param": true, - "mpool_id": 1, - "name": "gemm_9_weights_array", - "nbits": 8, - "offset_start": 23412, - "qmn": {}, - "shape": [ - 3, - 32 - ], - "shape_map": [ - "CH", - "CH_IN" - ], - "size_bytes": 96 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": true, - "channel_last": true, - "epochs": { - "end": 43, - "start": 40 - }, - "flags": "STAI_FLAG_OUTPUTS|STAI_FLAG_PREALLOCATED|STAI_FLAG_ACTIVATIONS", - "format": "STAI_FORMAT_S8", - "id": 231, - "intq": { - "axis": 0, - "offsets": [ - -128 - ], - "scales": [ - 0.00390625 - ] - }, - "is_param": false, - "mpool_id": 0, - "name": "nl_10_output_array", - "nbits": 8, - "offset_start": 0, - "qmn": {}, - "shape": [ - 3 - ], - "shape_map": [ - "CH" - ], - "size_bytes": 3 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": false, - "channel_last": true, - "epochs": { - "end": 42, - "start": 39 - }, - "flags": "STAI_FLAG_PREALLOCATED|STAI_FLAG_ACTIVATIONS|STAI_FLAG_SCRATCHS", - "format": "STAI_FORMAT_S32", - "id": 344, - "intq": { - "axis": null, - "offsets": [], - "scales": [] - }, - "is_param": false, - "mpool_id": 0, - "name": "nl_10_scratch0_array", - "nbits": 32, - "offset_start": 68, - "qmn": {}, - "shape": [ - 1, - 1, - 124, - 1 - ], - "shape_map": [ - "H", - "W", - "CH", - "CH_IN" - ], - "size_bytes": 496 - }, - { - "alignment": 4, - "batch": 0, - "channel_first": false, - "channel_last": true, - "epochs": { - "end": 5, - "start": 2 - }, - "flags": "STAI_FLAG_INPUTS|STAI_FLAG_PREALLOCATED|STAI_FLAG_ACTIVATIONS", - "format": "STAI_FORMAT_S8", - "id": 211, - "intq": { - "axis": 2, - "offsets": [ - -128 - ], - "scales": [ - 0.003701042616739869 - ] - }, - "is_param": false, - "mpool_id": 0, - "name": "serving_default_input_10_output_array", - "nbits": 8, - "offset_start": 2160, - "qmn": {}, - "shape": [ - 30, - 1, - 40 - ], - "shape_map": [ - "H", - "W", - "CH" - ], - "size_bytes": 1200 - } - ], - "environment": { - "device": null, - "generated_model": { - "generated_time": "2025-01-19T06:26:52-0500", - "model_files": [ - { - "name": "sww_model_data_params.h", - "signature": "0xaef3ce53d71b3b293cb4c3d9826290f7" - }, - { - "name": "sww_model_data_params.c", - "signature": "0xff58f35aeb4dfe94bc5c7084b7ccc0e3" - }, - { - "name": "sww_model_data.h", - "signature": "0xa222057d1fdedcbe750b4d43286d22a7" - }, - { - "name": "sww_model_data.c", - "signature": "0xdf5424159620ba466a89e4f1f7ebc984" - }, - { - "name": "sww_model_config.h", - "signature": "0xa226397aba8aeaa2114c3231a3f2124b" - }, - { - "name": "sww_model.h", - "signature": "0x0c74a6d47c087c72b81921f746a2d357" - }, - { - "name": "sww_model.c", - "signature": "0x0f25c8c5affe8bfde9d7fa441410b03b" - } - ], - "n_params": null, - "name": "sww_model", - "size": null, - "type": null - }, - "network_signature": "0x437a6e35a0b9caad", - "test_name": "", - "tools": [ - { - "arguments": "generate --target stm32l4 --name sww_model -m /Users/jeremy/dev/tiny_mlperf/tiny_jhsyn/benchmark/training/streaming_wakeword/trained_models/strm_ww_int8.tflite --compression none --verbosity 1 --allocate-inputs --allocate-outputs --workspace /var/folders/qb/jcjkm0nx4878vyqfjy786xdh0000gn/T/mxAI_workspace27583291741674848973423960786911 --output /Users/jeremy/.stm32cubemx/sww_model_output", - "environment": [ - "STATS_TYPE=X-CUBE-AI" - ], - "input_model": { - "generated_time": null, - "model_files": [ - { - "name": "strm_ww_int8.tflite", - "signature": "0x11c3f8bb3c26578a427b600d2c3795e0" - } - ], - "n_params": 46883, - "name": "strm_ww_int8", - "size": 49412, - "type": "tflite" - }, - "name": "ST.EdgeAI.Core", - "version": "1.0.0-19899" - } - ] - }, - "graphs": [ - { - "edges": [ - { - "attributes": null, - "buffer": 213, - "edge_kind": 3, - "end": { - "node_id": 30, - "port": 0 - }, - "id": 0, - "name": "n29-p0_n30-p0", - "start": { - "node_id": 29, - "port": 0 - } - }, - { - "attributes": null, - "buffer": 215, - "edge_kind": 3, - "end": { - "node_id": 31, - "port": 0 - }, - "id": 1, - "name": "n30-p0_n31-p0", - "start": { - "node_id": 30, - "port": 0 - } - }, - { - "attributes": null, - "buffer": 217, - "edge_kind": 3, - "end": { - "node_id": 32, - "port": 0 - }, - "id": 2, - "name": "n31-p0_n32-p0", - "start": { - "node_id": 31, - "port": 0 - } - }, - { - "attributes": null, - "buffer": 219, - "edge_kind": 3, - "end": { - "node_id": 33, - "port": 0 - }, - "id": 3, - "name": "n32-p0_n33-p0", - "start": { - "node_id": 32, - "port": 0 - } - }, - { - "attributes": null, - "buffer": 221, - "edge_kind": 3, - "end": { - "node_id": 34, - "port": 0 - }, - "id": 4, - "name": "n33-p0_n34-p0", - "start": { - "node_id": 33, - "port": 0 - } - }, - { - "attributes": null, - "buffer": 223, - "edge_kind": 3, - "end": { - "node_id": 35, - "port": 0 - }, - "id": 5, - "name": "n34-p0_n35-p0", - "start": { - "node_id": 34, - "port": 0 - } - }, - { - "attributes": null, - "buffer": 225, - "edge_kind": 3, - "end": { - "node_id": 36, - "port": 0 - }, - "id": 6, - "name": "n35-p0_n36-p0", - "start": { - "node_id": 35, - "port": 0 - } - }, - { - "attributes": null, - "buffer": 227, - "edge_kind": 3, - "end": { - "node_id": 37, - "port": 0 - }, - "id": 7, - "name": "n36-p0_n37-p0", - "start": { - "node_id": 36, - "port": 0 - } - }, - { - "attributes": null, - "buffer": 229, - "edge_kind": 3, - "end": { - "node_id": 38, - "port": 0 - }, - "id": 8, - "name": "n37-p0_n38-p0", - "start": { - "node_id": 37, - "port": 0 - } - } - ], - "exec_time": { - "counters": [], - "cycles": null, - "cycles_by_macc": null, - "duration_ms": null, - "percentage": null - }, - "id": 0, - "inputs": [ - 211 - ], - "name": "strm_ww_int8", - "nodes": [ - { - "attributes": { - "dilation": "{H: 1, W: 1}", - "filter_size": "(3, 1)", - "groups": "40", - "is_depthwise": "True", - "is_grouped_conv": "False", - "num_filters": "1", - "pad": "{H: (0, 0), W: (0, 0)}", - "stride": "(1, 1)", - "use_bias": "True", - "use_deep_kernels": "False" - }, - "description": "Conv2D", - "exec_time": { - "counters": [], - "cycles": null, - "cycles_by_macc": null, - "duration_ms": null, - "percentage": null - }, - "id": 29, - "inputs": [ - 211, - 233, - 236 - ], - "macc": 3400, - "mapping": "NODE_SW", - "name": "conv2d_0", - "original_nodes": [ - "0" - ], - "outputs": [ - 213 - ], - "scratchs": [ - 290 - ], - "subgraph_nodes": [], - "sw_functions": [ - "forward_dw_sssa8_ch" - ] - }, - { - "attributes": { - "dilation": "{H: 1, W: 1}", - "filter_size": "(1, 1)", - "groups": "1", - "is_depthwise": "False", - "is_grouped_conv": "False", - "num_filters": "126", - "pad": "{H: (0, 0), W: (0, 0)}", - "stride": "(1, 1)", - "use_bias": "True", - "use_deep_kernels": "True" - }, - "description": "Conv2D", - "exec_time": { - "counters": [], - "cycles": null, - "cycles_by_macc": null, - "duration_ms": null, - "percentage": null - }, - "id": 30, - "inputs": [ - 213, - 239, - 242 - ], - "macc": 141246, - "mapping": "NODE_SW", - "name": "conv2d_1", - "original_nodes": [ - "1" - ], - "outputs": [ - 215 - ], - "scratchs": [ - 296 - ], - "subgraph_nodes": [], - "sw_functions": [ - "forward_pw_sssa8_ch" - ] - }, - { - "attributes": { - "dilation": "{H: 1, W: 1}", - "filter_size": "(5, 1)", - "groups": "108", - "is_depthwise": "True", - "is_grouped_conv": "False", - "num_filters": "1", - "pad": "{H: (0, 0), W: (0, 0)}", - "stride": "(1, 1)", - "use_bias": "True", - "use_deep_kernels": "False" - }, - "description": "Conv2D", - "exec_time": { - "counters": [], - "cycles": null, - "cycles_by_macc": null, - "duration_ms": null, - "percentage": null - }, - "id": 31, - "inputs": [ - 215, - 245, - 248 - ], - "macc": 13068, - "mapping": "NODE_SW", - "name": "conv2d_2", - "original_nodes": [ - "2" - ], - "outputs": [ - 217 - ], - "scratchs": [ - 302 - ], - "subgraph_nodes": [], - "sw_functions": [ - "forward_dw_sssa8_ch" - ] - }, - { - "attributes": { - "dilation": "{H: 1, W: 1}", - "filter_size": "(1, 1)", - "groups": "1", - "is_depthwise": "False", - "is_grouped_conv": "False", - "num_filters": "126", - "pad": "{H: (0, 0), W: (0, 0)}", - "stride": "(1, 1)", - "use_bias": "True", - "use_deep_kernels": "True" - }, - "description": "Conv2D", - "exec_time": { - "counters": [], - "cycles": null, - "cycles_by_macc": null, - "duration_ms": null, - "percentage": null - }, - "id": 32, - "inputs": [ - 217, - 251, - 254 - ], - "macc": 326718, - "mapping": "NODE_SW", - "name": "conv2d_3", - "original_nodes": [ - "3" - ], - "outputs": [ - 219 - ], - "scratchs": [ - 308 - ], - "subgraph_nodes": [], - "sw_functions": [ - "forward_pw_sssa8_ch" - ] - }, - { - "attributes": { - "dilation": "{H: 1, W: 1}", - "filter_size": "(10, 1)", - "groups": "81", - "is_depthwise": "True", - "is_grouped_conv": "False", - "num_filters": "1", - "pad": "{H: (0, 0), W: (0, 0)}", - "stride": "(1, 1)", - "use_bias": "True", - "use_deep_kernels": "False" - }, - "description": "Conv2D", - "exec_time": { - "counters": [], - "cycles": null, - "cycles_by_macc": null, - "duration_ms": null, - "percentage": null - }, - "id": 33, - "inputs": [ - 219, - 257, - 260 - ], - "macc": 12231, - "mapping": "NODE_SW", - "name": "conv2d_4", - "original_nodes": [ - "4" - ], - "outputs": [ - 221 - ], - "scratchs": [ - 314 - ], - "subgraph_nodes": [], - "sw_functions": [ - "forward_dw_sssa8_ch" - ] - }, - { - "attributes": { - "dilation": "{H: 1, W: 1}", - "filter_size": "(1, 1)", - "groups": "1", - "is_depthwise": "False", - "is_grouped_conv": "False", - "num_filters": "126", - "pad": "{H: (0, 0), W: (0, 0)}", - "stride": "(1, 1)", - "use_bias": "True", - "use_deep_kernels": "True" - }, - "description": "Conv2D", - "exec_time": { - "counters": [], - "cycles": null, - "cycles_by_macc": null, - "duration_ms": null, - "percentage": null - }, - "id": 34, - "inputs": [ - 221, - 263, - 266 - ], - "macc": 153216, - "mapping": "NODE_SW", - "name": "conv2d_5", - "original_nodes": [ - "5" - ], - "outputs": [ - 223 - ], - "scratchs": [ - 320 - ], - "subgraph_nodes": [], - "sw_functions": [ - "forward_pw_sssa8_ch" - ] - }, - { - "attributes": { - "dilation": "{H: 1, W: 1}", - "filter_size": "(15, 1)", - "groups": "52", - "is_depthwise": "True", - "is_grouped_conv": "False", - "num_filters": "1", - "pad": "{H: (0, 0), W: (0, 0)}", - "stride": "(1, 1)", - "use_bias": "True", - "use_deep_kernels": "False" - }, - "description": "Conv2D", - "exec_time": { - "counters": [], - "cycles": null, - "cycles_by_macc": null, - "duration_ms": null, - "percentage": null - }, - "id": 35, - "inputs": [ - 223, - 269, - 272 - ], - "macc": 832, - "mapping": "NODE_SW", - "name": "conv2d_6", - "original_nodes": [ - "6" - ], - "outputs": [ - 225 - ], - "scratchs": [ - 326 - ], - "subgraph_nodes": [], - "sw_functions": [ - "forward_dw_sssa8_ch" - ] - }, - { - "attributes": { - "dilation": "{H: 1, W: 1}", - "filter_size": "(1, 1)", - "groups": "1", - "is_depthwise": "False", - "is_grouped_conv": "False", - "num_filters": "32", - "pad": "{H: (0, 0), W: (0, 0)}", - "stride": "(1, 1)", - "use_bias": "True", - "use_deep_kernels": "True" - }, - "description": "Conv2D", - "exec_time": { - "counters": [], - "cycles": null, - "cycles_by_macc": null, - "duration_ms": null, - "percentage": null - }, - "id": 36, - "inputs": [ - 225, - 275, - 278 - ], - "macc": 1696, - "mapping": "NODE_SW", - "name": "conv2d_7", - "original_nodes": [ - "7" - ], - "outputs": [ - 227 - ], - "scratchs": [ - 332 - ], - "subgraph_nodes": [], - "sw_functions": [ - "forward_pw_sssa8_ch" - ] - }, - { - "attributes": { - "num_units": "3", - "use_bias": "True" - }, - "description": "Dense", - "exec_time": { - "counters": [], - "cycles": null, - "cycles_by_macc": null, - "duration_ms": null, - "percentage": null - }, - "id": 37, - "inputs": [ - 227, - 281, - 284 - ], - "macc": 99, - "mapping": "NODE_SW", - "name": "gemm_9", - "original_nodes": [ - "9" - ], - "outputs": [ - 229 - ], - "scratchs": [ - 338 - ], - "subgraph_nodes": [], - "sw_functions": [ - "forward_dense_integer_SSSA" - ] - }, - { - "attributes": { - "axis": "CH", - "nonlinearity": "softmax", - "orig_axis": "-1", - "param_fmt": "(SIGNED, 32 bit, C Size: 32 bits)", - "params": "[1263631360, 24, -124]" - }, - "description": "Nonlinearity", - "exec_time": { - "counters": [], - "cycles": null, - "cycles_by_macc": null, - "duration_ms": null, - "percentage": null - }, - "id": 38, - "inputs": [ - 229 - ], - "macc": 45, - "mapping": "NODE_SW", - "name": "nl_10", - "original_nodes": [ - "10" - ], - "outputs": [ - 231 - ], - "scratchs": [ - 344 - ], - "subgraph_nodes": [], - "sw_functions": [ - "forward_sm_integer" - ] - } - ], - "original_inputs": [ - { - "serving_default_input_10": { - "data_type": "int8", - "shape": "(BATCH: 1, H: 30, W: 1, CH: 40)" - } - } - ], - "original_outputs": [ - { - "nl_10": { - "data_type": "int8", - "shape": "(BATCH: 1, CH: 3)" - } - } - ], - "outputs": [ - 231 - ] - } - ], - "json_schema_version": "2.0", - "memory_accesses": [], - "memory_footprint": { - "activations": 5836, - "io": [ - 0, - 0 - ], - "kernel_flash": null, - "kernel_ram": null, - "series": "generic", - "toolchain": null, - "toolchain_flash": null, - "toolchain_ram": null, - "weights": 23520 - }, - "memory_pools": [ - { - "address": "NULL", - "alignment": 4, - "attributes": { - "latency": "HIGH", - "score": 768, - "throughput": "LOW" - }, - "buffers": [ - 211, - 213, - 215, - 217, - 219, - 221, - 223, - 225, - 227, - 229, - 231, - 290, - 296, - 302, - 308, - 314, - 320, - 326, - 332, - 338, - 344 - ], - "cacheable": null, - "id": 0, - "name": "heap_overlay_pool", - "offset_start": 0, - "persistent": false, - "pipelined": null, - "rights": "ACC_WRITE", - "size_bytes": -1, - "subpools": [], - "used_size_bytes": 5836, - "user_allocated": false, - "virtual": false - }, - { - "address": "NULL", - "alignment": 0, - "attributes": { - "latency": "UNDEF", - "score": 0, - "throughput": "UNDEF" - }, - "buffers": [ - 233, - 236, - 239, - 242, - 245, - 248, - 251, - 254, - 257, - 260, - 263, - 266, - 269, - 272, - 275, - 278, - 281, - 284 - ], - "cacheable": null, - "id": 1, - "name": "weights_array", - "offset_start": 0, - "persistent": true, - "pipelined": null, - "rights": "ACC_READ", - "size_bytes": -1, - "subpools": [], - "used_size_bytes": 23520, - "user_allocated": false, - "virtual": false - } - ], - "power_estimates": [], - "validation": { - "val_error": null, - "val_error_desc": null, - "val_metrics": [] - } -} \ No newline at end of file diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.ai/sww_model_null_report.json b/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.ai/sww_model_null_report.json deleted file mode 100644 index 1b8b65a2..00000000 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.ai/sww_model_null_report.json +++ /dev/null @@ -1,487 +0,0 @@ -{ - "_allocate_inputs": 4, - "_allocate_outputs": 4, - "cli_parameters": "generate --target stm32l4 --name sww_model -m /Users/jeremy/dev/tiny_mlperf/tiny_jhsyn/benchmark/training/streaming_wakeword/trained_models/strm_ww_int8.tflite --compression none --verbosity 1 --allocate-inputs --allocate-outputs --workspace /var/folders/qb/jcjkm0nx4878vyqfjy786xdh0000gn/T/mxAI_workspace27583291741674848973423960786911 --output /Users/jeremy/.stm32cubemx/sww_model_output", - "cli_version": { - "extra": "19899", - "major": 1, - "micro": 0, - "minor": 0 - }, - "cli_version_str": "1.0.0-19899", - "code_size": 0, - "compression": [], - "date_time": "2025-01-19T06:26:52-0500", - "error": 0, - "error_str": [], - "exec_cmd": "generate", - "exec_duration": 0.0, - "hash": "0x11c3f8bb3c26578a427b600d2c3795e0", - "inputs": [ - "serving_default_input_10" - ], - "layers": [ - { - "c_id": [ - 0 - ], - "extras": { - "n_macc": 0, - "n_params": 0, - "psize": 0, - "rom_output": { - "c_size": 1200, - "fmt": { - "format": "s8" - }, - "shape": [ - 1, - 40, - 30 - ] - }, - "rom_size": 280 - }, - "id": 0, - "inputs": [], - "name": "serving_default_input_10", - "original": "", - "type": "Input" - }, - { - "c_id": [], - "extras": { - "n_macc": 3400, - "n_params": 160, - "psize": 280, - "rom_output": { - "c_size": 1120, - "fmt": { - "format": "s8" - }, - "shape": [ - 1, - 40, - 28 - ] - }, - "rom_size": 0 - }, - "id": 0, - "inputs": [ - "serving_default_input_10" - ], - "name": "conv2d_0", - "original": "DEPTHWISE_CONV_2D", - "type": "Conv2D" - }, - { - "c_id": [ - 1 - ], - "extras": { - "n_macc": 143488, - "n_params": 5248, - "psize": 5632, - "rom_output": { - "c_size": 3024, - "fmt": { - "format": "s8" - }, - "shape": [ - 1, - 108, - 28 - ] - }, - "rom_size": 4752 - }, - "id": 1, - "inputs": [ - "conv2d_0" - ], - "name": "conv2d_1", - "original": "CONV_2D", - "type": "Conv2D" - }, - { - "c_id": [], - "extras": { - "n_macc": 3584, - "n_params": 0, - "psize": 0, - "rom_size": 0 - }, - "id": 1, - "inputs": [ - "conv2d_1" - ], - "name": "nl_1_nl", - "original": "CONV_2D", - "type": "Nonlinearity" - }, - { - "c_id": [ - 2 - ], - "extras": { - "n_macc": 15488, - "n_params": 768, - "psize": 1152, - "rom_output": { - "c_size": 2592, - "fmt": { - "format": "s8" - }, - "shape": [ - 1, - 108, - 24 - ] - }, - "rom_size": 972 - }, - "id": 2, - "inputs": [ - "nl_1_nl" - ], - "name": "conv2d_2", - "original": "DEPTHWISE_CONV_2D", - "type": "Conv2D" - }, - { - "c_id": [ - 3 - ], - "extras": { - "n_macc": 393344, - "n_params": 16512, - "psize": 16896, - "rom_output": { - "c_size": 1944, - "fmt": { - "format": "s8" - }, - "shape": [ - 1, - 81, - 24 - ] - }, - "rom_size": 9072 - }, - "id": 3, - "inputs": [ - "conv2d_2" - ], - "name": "conv2d_3", - "original": "CONV_2D", - "type": "Conv2D" - }, - { - "c_id": [], - "extras": { - "n_macc": 3072, - "n_params": 0, - "psize": 0, - "rom_size": 0 - }, - "id": 3, - "inputs": [ - "conv2d_3" - ], - "name": "nl_3_nl", - "original": "CONV_2D", - "type": "Nonlinearity" - }, - { - "c_id": [ - 4 - ], - "extras": { - "n_macc": 19328, - "n_params": 1408, - "psize": 1792, - "rom_output": { - "c_size": 1215, - "fmt": { - "format": "s8" - }, - "shape": [ - 1, - 81, - 15 - ] - }, - "rom_size": 1134 - }, - "id": 4, - "inputs": [ - "nl_3_nl" - ], - "name": "conv2d_4", - "original": "DEPTHWISE_CONV_2D", - "type": "Conv2D" - }, - { - "c_id": [ - 5 - ], - "extras": { - "n_macc": 245888, - "n_params": 16512, - "psize": 16896, - "rom_output": { - "c_size": 780, - "fmt": { - "format": "s8" - }, - "shape": [ - 1, - 52, - 15 - ] - }, - "rom_size": 4420 - }, - "id": 5, - "inputs": [ - "conv2d_4" - ], - "name": "conv2d_5", - "original": "CONV_2D", - "type": "Conv2D" - }, - { - "c_id": [], - "extras": { - "n_macc": 1920, - "n_params": 0, - "psize": 0, - "rom_size": 0 - }, - "id": 5, - "inputs": [ - "conv2d_5" - ], - "name": "nl_5_nl", - "original": "CONV_2D", - "type": "Nonlinearity" - }, - { - "c_id": [ - 6 - ], - "extras": { - "n_macc": 2048, - "n_params": 2048, - "psize": 2432, - "rom_output": { - "c_size": 52, - "fmt": { - "format": "s8" - }, - "shape": [ - 1, - 52, - 1 - ] - }, - "rom_size": 988 - }, - "id": 6, - "inputs": [ - "nl_5_nl" - ], - "name": "conv2d_6", - "original": "DEPTHWISE_CONV_2D", - "type": "Conv2D" - }, - { - "c_id": [ - 7 - ], - "extras": { - "n_macc": 4128, - "n_params": 4128, - "psize": 4224, - "rom_output": { - "c_size": 32, - "fmt": { - "format": "s8" - }, - "shape": [ - 1, - 32, - 1 - ] - }, - "rom_size": 1792 - }, - "id": 7, - "inputs": [ - "conv2d_6" - ], - "name": "conv2d_7", - "original": "CONV_2D", - "type": "Conv2D" - }, - { - "c_id": [], - "extras": { - "n_macc": 32, - "n_params": 0, - "psize": 0, - "rom_size": 0 - }, - "id": 7, - "inputs": [ - "conv2d_7" - ], - "name": "nl_7_nl", - "original": "CONV_2D", - "type": "Nonlinearity" - }, - { - "c_id": [], - "extras": { - "n_macc": 0, - "n_params": 0, - "psize": 0, - "rom_size": 0 - }, - "id": 8, - "inputs": [ - "nl_7_nl" - ], - "name": "reshape_8", - "original": "RESHAPE", - "type": "Reshape" - }, - { - "c_id": [ - 8 - ], - "extras": { - "n_macc": 0, - "n_params": 96, - "psize": 96, - "rom_size": 108 - }, - "id": 9, - "inputs": [], - "name": "model_dense_MatMul", - "original": "", - "type": "Placeholder" - }, - { - "c_id": [], - "extras": { - "n_macc": 0, - "n_params": 3, - "psize": 12, - "rom_size": 0 - }, - "id": 9, - "inputs": [], - "name": "model_dense_BiasAdd_ReadVariableOp", - "original": "", - "type": "Placeholder" - }, - { - "c_id": [], - "extras": { - "n_macc": 99, - "n_params": 0, - "psize": 0, - "rom_output": { - "c_size": 3, - "fmt": { - "format": "s8" - }, - "shape": [ - 3 - ] - }, - "rom_size": 0 - }, - "id": 9, - "inputs": [ - "reshape_8", - "model_dense_MatMul", - "model_dense_BiasAdd_ReadVariableOp" - ], - "name": "gemm_9", - "original": "FULLY_CONNECTED", - "type": "Gemm" - }, - { - "c_id": [ - 9 - ], - "extras": { - "n_macc": 45, - "n_params": 0, - "psize": 0, - "rom_output": { - "c_size": 3, - "fmt": { - "format": "s8" - }, - "shape": [ - 3 - ] - }, - "rom_size": 0 - }, - "id": 10, - "inputs": [ - "gemm_9" - ], - "name": "nl_10", - "original": "SOFTMAX", - "type": "Nonlinearity" - } - ], - "model_files": [ - "/Users/jeremy/dev/tiny_mlperf/tiny_jhsyn/benchmark/training/streaming_wakeword/trained_models/strm_ww_int8.tflite" - ], - "model_n_params": 46883, - "model_name": "strm_ww_int8", - "model_size": 49412, - "model_type": "tflite", - "name": "sww_model", - "outputs": [ - "nl_10" - ], - "ram_io_size": [ - 0, - 0 - ], - "ram_size": 5836, - "report_version": 1.1, - "rom_cfact": 1.0, - "rom_heap_inspector": 2048, - "rom_inputs": [ - { - "c_size": 1200, - "c_type": "s8", - "name": "serving_default_input_10" - } - ], - "rom_n_macc": 652551, - "rom_outputs": [ - { - "c_size": 3, - "c_type": "s8", - "name": "nl_10" - } - ], - "rom_size": 23520, - "strategy": "", - "tools_api_version": "1.0.0-19899", - "tools_version": "1.0.0-19899", - "val_error": -1.0, - "val_error_desc": "None (None) #-1", - "val_metrics": [] -} \ No newline at end of file diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs b/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs deleted file mode 100644 index 98a69fc7..00000000 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs +++ /dev/null @@ -1,2 +0,0 @@ -eclipse.preferences.version=1 -sfrviewstate={"fFavorites"\:{"fLists"\:{}},"fProperties"\:{"fNodeProperties"\:{}}} diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.settings/org.eclipse.core.resources.prefs b/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.settings/org.eclipse.core.resources.prefs deleted file mode 100644 index 99f26c02..00000000 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/.settings/org.eclipse.core.resources.prefs +++ /dev/null @@ -1,2 +0,0 @@ -eclipse.preferences.version=1 -encoding/=UTF-8 diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Inc/sww_util.h b/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Inc/sww_util.h deleted file mode 100644 index 2d387acf..00000000 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Inc/sww_util.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * sww_util.h - * - * Created on: Jan 16, 2025 - * Author: jeremy - */ - -#ifndef INC_SWW_UTIL_H_ -#define INC_SWW_UTIL_H_ - -#include -#include -#include -#include -#include - - -#define EE_CMD_SIZE 80u -#define EE_CMD_DELIMITER " " -#define EE_CMD_TERMINATOR '%' - -// struct for a log we can write to without the delay of printing to UART -#define LOG_BUFFER_SIZE 4096 -typedef struct { - char buffer[LOG_BUFFER_SIZE]; - size_t current_pos; -} LogBuffer; - - -void print_vals_int16(int16_t *buffer, uint32_t num_vals); -void print_bytes(uint8_t *buffer, uint32_t num_bytes); -void print_vals_float(float *buffer, uint32_t num_vals); -void log_printf(LogBuffer *log, const char *format, ...); - -void process_command(char *full_command); -void ee_serial_callback(char c); - -int aiInit(void); -void setup_i2s_buffers(); - - -#endif /* INC_SWW_UTIL_H_ */ diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Src/model_test_inputs.c b/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Src/model_test_inputs.c deleted file mode 100644 index ac0182f1..00000000 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Src/model_test_inputs.c +++ /dev/null @@ -1,764 +0,0 @@ -/* - * model_test_inputs.c - * - * Created on: Jan 12, 2025 - * Author: jeremy - */ -#include -#include "arm_math.h" - -const int8_t test_input_class0[1200] = { --125, -128, -128, -124, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -109, -128, -128, -113, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --98, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -119, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -127, -128, -128, -110, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -121, -32, -44, -48, -11, -74, -71, -97, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -105, -87, -9, -32, -16, 19, -36, -5, --23, 14, -7, -6, -26, -22, -7, 16, 9, -43, -38, -97, -111, -122, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --111, -88, -9, -31, -8, 25, -40, 4, 0, 93, 67, 59, 61, 65, 78, 88, -72, 23, 29, -52, -68, -76, -65, -60, -62, -53, -55, -55, -48, -52, -45, -47, --43, -45, -47, -46, -48, -51, -53, -56, -128, -102, -37, -70, 3, 24, -30, 25, -39, 98, 55, 69, 102, 91, 79, 32, 25, 12, -2, -28, -26, -21, -13, -4, -0, 0, -5, -12, -20, -15, -4, 0, -8, -28, -36, -32, -32, -35, -27, -31, --128, -125, -71, -95, 5, 14, -28, 8, 58, 85, 64, 66, 97, 65, 50, 17, --15, -34, -48, -59, -56, -52, -48, -48, -48, -44, -46, -45, -50, -47, -48, -49, --53, -57, -60, -60, -61, -60, -58, -58, -118, -115, -92, -105, 11, 16, -27, -13, -57, 69, 82, 77, 88, 36, 30, -12, -45, -92, -109, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --124, -117, -89, -94, 18, 19, -25, -13, 35, 43, 64, 53, 33, -8, -22, -60, --81, -105, -113, -119, -124, -127, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -93, -115, 9, 11, -23, -13, -18, 33, 45, 32, -19, -60, -72, -95, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128 -}; - -const int8_t test_input_class1[1200] = { --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -126, -114, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -127, -114, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --101, -80, -61, -31, -38, -46, -41, -24, -22, -15, 5, 10, 2, -1, 19, 14, -13, 42, 44, 29, 32, 43, 55, 53, 65, 42, 57, 62, 67, 80, 80, 84, -80, 85, 86, 85, 95, 97, 103, 94, -77, -47, -46, -39, -45, -21, -36, -8, -1, 0, 14, 27, 29, 20, 31, 39, 31, 36, 44, 57, 56, 60, 74, 68, -70, 78, 83, 86, 96, 98, 101, 101, 105, 101, 115, 110, 108, 109, 115, 112, --65, -75, -65, -46, -28, -17, -29, -10, 6, 5, 18, 23, 18, 17, 27, 36, -41, 48, 50, 52, 55, 68, 74, 67, 65, 75, 86, 87, 93, 95, 97, 102, -102, 100, 107, 111, 110, 114, 116, 114, -70, -51, -31, -39, -36, -21, -12, -12, -0, 3, 2, 14, 19, 28, 38, 36, 25, 39, 42, 52, 59, 60, 72, 71, -71, 83, 85, 82, 83, 94, 99, 102, 102, 107, 113, 107, 106, 112, 118, 121, --80, -29, 0, -58, -17, -10, -8, -7, -14, 1, 10, 22, 18, 23, 35, 45, -38, 46, 44, 50, 66, 62, 63, 64, 74, 72, 76, 92, 83, 91, 94, 97, -108, 109, 110, 107, 108, 113, 118, 118, -60, -22, 0, -50, -15, -19, -8, -7, --9, 11, 26, 27, 25, 25, 32, 18, 36, 34, 43, 59, 58, 62, 61, 70, -63, 76, 78, 80, 83, 92, 87, 93, 94, 108, 104, 110, 110, 113, 114, 111, --58, -21, -3, -34, -27, -27, -11, -8, -2, 4, 19, 30, 24, 20, 26, 43, -48, 40, 50, 61, 60, 66, 62, 60, 55, 71, 78, 89, 92, 92, 94, 101, -102, 103, 105, 109, 107, 111, 109, 113, -74, -34, -31, -53, -38, -25, -16, -12, -6, 13, 3, 18, 12, 26, 32, 40, 38, 32, 52, 57, 62, 56, 61, 64, -68, 61, 77, 85, 88, 85, 95, 96, 93, 99, 100, 109, 117, 113, 119, 125, --73, -26, -7, -56, -38, -8, 14, 0, 19, 31, 39, 20, 24, 34, 33, 47, -43, 39, 58, 53, 68, 74, 64, 65, 69, 86, 84, 80, 87, 84, 92, 97, -93, 97, 103, 104, 105, 113, 120, 119, -75, -14, 4, -41, -5, -26, -19, -9, -13, 33, 40, 34, 28, 33, 26, 28, 53, 41, 48, 54, 59, 67, 61, 59, -59, 81, 84, 78, 90, 97, 104, 93, 100, 106, 110, 104, 110, 114, 116, 118, --56, -19, -3, -24, -3, -36, -37, -22, 0, 14, 15, 12, 16, 29, 24, 37, -47, 45, 46, 52, 56, 61, 77, 71, 69, 74, 84, 78, 85, 90, 96, 101, -97, 101, 109, 105, 120, 116, 116, 113, -73, -14, -6, -32, -27, -13, -6, -26, --15, -4, 3, 10, 10, 25, 22, 26, 41, 45, 51, 61, 54, 51, 65, 74, -76, 78, 85, 87, 90, 94, 86, 88, 100, 103, 114, 112, 114, 114, 117, 117, --87, -41, -36, -29, -15, -10, -9, -16, 0, 0, 10, 20, 17, 24, 25, 43, -33, 45, 58, 55, 46, 52, 61, 69, 70, 71, 82, 93, 91, 95, 93, 87, -92, 97, 105, 109, 111, 116, 116, 114, -74, -58, -46, -25, -20, -19, -2, -10, -0, 9, -6, 16, 22, 26, 23, 23, 40, 57, 58, 57, 63, 68, 75, 71, -78, 82, 83, 88, 89, 97, 88, 87, 95, 100, 108, 115, 110, 107, 115, 120, --72, -49, -31, -36, -29, -7, -12, 3, 6, 12, 1, 16, 26, 26, 22, 31, -41, 40, 44, 33, 49, 57, 53, 62, 67, 82, 74, 83, 86, 93, 95, 99, -100, 99, 102, 110, 115, 114, 111, 114, -87, -30, -12, -46, -22, -18, -9, 18, -20, 8, 14, 25, 21, 32, 24, 24, 30, 44, 37, 51, 60, 58, 69, 65, -76, 76, 71, 88, 86, 84, 98, 106, 107, 101, 104, 109, 110, 109, 115, 123, --89, -40, -40, -33, -23, -34, -8, 2, 4, -6, -1, 6, 18, 23, 32, 35, -33, 52, 59, 44, 56, 58, 59, 62, 66, 72, 80, 89, 91, 97, 93, 89, -97, 101, 108, 106, 108, 110, 113, 113, -71, -16, -10, -23, -14, -16, -1, 4, -14, 11, 10, 13, 12, 18, 31, 32, 32, 48, 59, 53, 52, 60, 73, 71, -72, 82, 75, 77, 89, 91, 90, 96, 98, 103, 103, 110, 111, 112, 117, 114, --65, -10, -7, -38, -9, -4, -1, 6, 6, 19, 16, 20, 28, 20, 5, 30, -33, 51, 48, 38, 43, 52, 62, 65, 73, 70, 87, 80, 80, 91, 100, 100, -99, 99, 101, 108, 112, 112, 114, 122, -64, -19, -11, -12, -2, -8, -18, -15, --32, -7, 22, 21, 19, 33, 38, 35, 43, 35, 46, 43, 55, 69, 66, 54, -70, 79, 88, 84, 85, 90, 89, 97, 102, 99, 104, 105, 105, 109, 115, 115, --54, -40, -25, -36, -19, -13, -21, 0, -8, -9, 21, 19, 18, 27, 14, 32, -47, 52, 52, 51, 47, 61, 67, 67, 69, 81, 90, 86, 86, 86, 87, 88, -96, 101, 105, 110, 110, 110, 114, 118, -65, -66, -68, -50, -22, -13, -26, -14, -3, 5, 5, 19, 16, 23, 38, 30, 39, 44, 45, 55, 55, 61, 61, 65, -64, 77, 79, 75, 77, 83, 97, 106, 102, 109, 110, 107, 102, 107, 120, 119, --64, -54, -72, -43, -25, -23, -17, -10, -17, -6, 9, 13, 26, 32, 32, 34, -39, 35, 48, 52, 51, 62, 71, 60, 83, 71, 69, 76, 82, 95, 100, 95, -102, 106, 114, 107, 107, 111, 115, 115, -93, -84, -51, -55, -30, -17, -8, 1, --8, 7, 21, 29, 24, 21, 33, 37, 52, 36, 44, 49, 57, 56, 63, 59, -70, 80, 84, 86, 85, 92, 98, 104, 101, 101, 105, 101, 106, 114, 112, 118, --85, -76, -51, -47, -33, -19, -17, -7, 3, 7, 19, 15, 15, 26, 21, 34, -44, 48, 36, 51, 64, 58, 68, 65, 79, 83, 73, 86, 93, 87, 91, 97, -104, 114, 111, 108, 107, 119, 123, 115, -87, -73, -67, -51, -47, -27, -3, 1, -2, 4, 17, 20, 25, 17, 26, 19, 44, 49, 38, 47, 62, 64, 70, 69, -71, 80, 82, 86, 96, 86, 91, 98, 102, 104, 112, 112, 114, 121, 114, 115, --87, -65, -45, -19, -22, -17, -9, -3, -2, 11, 5, 13, 30, 13, 16, 38, -46, 51, 52, 58, 67, 55, 58, 63, 72, 81, 85, 80, 87, 89, 94, 96, -107, 102, 109, 110, 115, 117, 108, 115, -87, -52, -12, 31, 0, -24, 24, 15, --14, 0, 9, 16, 7, 22, 29, 35, 40, 43, 53, 47, 54, 46, 57, 63, -80, 78, 74, 78, 86, 95, 90, 101, 96, 103, 112, 106, 113, 121, 117, 114 -}; - -const int8_t test_input_class2[1200] = { --128, -99, -13, -36, -13, 25, -25, -6, -31, -40, -58, -92, -94, -88, -107, -105, --85, -60, -33, -14, -45, -56, -68, -94, -103, -87, -104, -112, -110, -99, -100, -123, --124, -123, -126, -125, -85, -76, -96, -120, -128, -98, -18, -48, -11, 15, -57, 0, --34, -30, -49, -43, -46, -45, -35, -30, -35, -30, -18, -16, -43, -52, -65, -89, --81, -69, -107, -128, -128, -127, -128, -128, -128, -128, -128, -125, -97, -76, -94, -128, --128, -99, -18, -47, -13, 13, -40, 8, -27, 2, -23, -15, -20, -14, 6, -10, --8, -8, -16, -18, -31, -63, -80, -91, -82, -81, -113, -128, -128, -128, -128, -128, --128, -128, -128, -128, -90, -81, -89, -121, -128, -105, -13, -34, -25, 19, -48, 4, --12, 32, 14, 1, -20, -12, -1, -5, 13, 27, 25, 29, 13, 1, -29, -63, --69, -60, -75, -111, -128, -128, -128, -128, -128, -128, -128, -124, -79, -84, -60, -97, --128, -103, -16, -37, -27, 5, -35, 8, -4, 49, 24, 20, -11, -7, -12, -13, -7, 26, 40, 13, 4, 3, -7, -49, -63, -50, -35, -60, -94, -122, -128, -128, --128, -128, -128, -101, -64, -74, -67, -89, -128, -128, -58, -57, -57, -65, -50, -47, --45, -27, -62, -64, -82, -91, -81, -75, -51, -51, -59, -86, -108, -103, -107, -120, --128, -128, -127, -116, -125, -128, -128, -128, -128, -128, -128, -128, -116, -114, -128, -128, --128, -128, -123, -128, -97, -47, -15, -12, -27, -42, -48, -40, -30, -14, -22, -55, --4, 2, -11, -5, 5, 0, -18, -11, -29, 7, -11, -10, -12, -9, -26, -30, --27, -14, -21, -24, -22, -31, -35, -45, -128, -128, -101, -65, -61, -73, -53, -52, --60, -60, -60, -80, -87, -75, -73, -70, -67, -59, -53, -59, -45, -56, -65, -77, --67, -45, -29, -45, -43, -18, -43, -40, -57, -55, -51, -64, -63, -58, -83, -91, --128, -128, -36, 15, 3, -23, 31, 32, 20, 55, 40, 39, 6, 12, 22, 29, --5, -21, -35, -54, -70, -75, -78, -82, -71, -43, -18, -37, -55, -26, -40, -94, --94, -80, -32, -14, -27, -90, -101, -58, -128, -128, -25, 3, -63, -16, 32, -34, -22, 34, 38, 75, 29, 48, 52, 59, 65, 44, 22, 1, -8, -22, -28, -37, --31, -4, 27, -4, -30, -10, -18, -61, -62, -48, -25, 12, -2, -46, -57, -69, --128, -100, -22, -4, -70, -6, 18, -36, 8, 0, 43, 52, 57, 61, 58, 50, -68, 66, 50, 16, 3, -3, -20, -23, -6, 26, 38, 3, -21, -19, -37, -31, --16, 0, 0, -10, -24, -29, -56, -93, -107, -22, -15, -9, 3, 2, 16, 27, -45, 78, 80, 69, 44, 50, 58, 62, 46, 55, 44, 24, 9, 8, -3, 7, -5, 20, 36, 14, -9, -7, -29, -26, -8, 13, 11, -2, -14, -20, -35, -52, --128, -33, -25, 0, 0, -8, -13, 17, 31, 47, 83, 86, 70, 49, 51, 65, -79, 54, 33, 29, 5, -1, 2, 9, 16, 14, 33, 9, 11, 0, 0, -9, --12, 5, 18, 11, 1, -17, -23, -24, -99, -43, -51, -18, -12, -6, -21, -2, -28, 40, 63, 101, 64, 61, 57, 42, 62, 56, 53, 41, 41, 15, 0, 16, -5, 18, 27, -6, -4, -15, -14, -7, -5, 15, 25, 3, -8, -24, -35, -36, --128, -36, -47, -6, -23, -3, -15, -1, 32, 50, 85, 86, 59, 57, 31, 6, -6, 24, 39, 40, 36, 36, -2, 10, 2, 5, 15, -7, -4, 2, -3, -19, --5, 18, 14, -6, -11, -13, -48, -53, -105, -28, -31, 7, -21, -16, 2, 30, -65, 76, 71, 29, 11, 2, -8, -20, -10, -12, -10, 5, 25, 26, 8, -6, -12, 17, 14, 0, -4, 6, -4, -35, -1, 18, -4, -27, -12, -3, -33, -82, --79, -26, -11, 10, -34, -5, 21, 49, 64, 50, 8, 6, -23, -32, -22, -26, --20, -42, -30, -33, -13, 15, 13, 5, 6, 20, 8, -6, -6, 0, -14, -46, --17, 14, -7, -41, -35, -45, -54, -65, -82, -57, -25, -27, -52, 6, 27, 29, -17, -15, -25, -14, -34, -38, -49, -49, -40, -53, -56, -60, -54, -20, 2, 9, -16, 15, -5, -20, -4, -6, -18, -44, -29, -10, -38, -57, -56, -92, -93, -108, --90, -65, -39, -56, -33, -6, -2, -13, -32, -51, -44, -29, -62, -75, -65, -65, --58, -67, -76, -67, -56, -40, -35, -23, -38, -43, -61, -65, -50, -55, -75, -85, --60, -66, -87, -91, -82, -86, -114, -128, -106, -78, -66, -57, -80, -60, -47, -37, --62, -84, -62, -50, -72, -78, -85, -79, -67, -76, -66, -79, -73, -72, -70, -83, --60, -60, -55, -66, -55, -61, -63, -66, -47, -48, -57, -53, -50, -62, -90, -128, --128, -118, -117, -128, -117, -97, -81, -66, -71, -73, -74, -79, -74, -65, -67, -66, --60, -48, -56, -51, -40, -37, -47, -49, -40, -36, -33, -27, -16, -19, -19, -29, --26, -26, -40, -32, -26, -35, -52, -107, -128, -106, -125, -128, -128, -128, -107, -100, --117, -104, -111, -81, -96, -87, -75, -58, -37, -31, -36, -30, -32, -32, -49, -38, --14, -10, -28, -25, -18, -22, -22, -28, -27, -21, -24, -28, -15, -13, -35, -75, --128, -128, -128, -128, -128, -128, -126, -124, -110, -109, -111, -70, -73, -57, -59, -59, --42, -40, -28, -33, -35, -37, -48, -26, -6, -1, -12, -4, -2, -7, -13, -15, --3, -8, -8, -10, -6, 1, -20, -65, -128, -128, -128, -128, -128, -128, -128, -110, --90, -93, -85, -82, -68, -78, -83, -42, -29, -35, -32, -28, -18, -24, -30, -10, --3, -2, -6, 1, 0, 2, -7, -16, 3, 4, -4, -8, -6, 5, -19, -71, --128, -128, -128, -128, -128, -128, -128, -90, -72, -73, -80, -82, -88, -68, -57, -59, --36, -33, -20, -37, -39, -33, -42, -15, -8, -13, -21, -13, -4, -8, -18, -24, --1, -7, -7, -7, -4, -4, -25, -83, -128, -128, -128, -128, -128, -128, -128, -77, --64, -98, -90, -65, -82, -108, -81, -56, -25, -34, -34, -36, -54, -51, -55, -40, --23, -31, -35, -26, -29, -29, -35, -34, -12, -15, -17, -17, -18, -14, -40, -93, --128, -128, -128, -128, -128, -128, -128, -128, -118, -123, -116, -107, -121, -127, -87, -62, --54, -57, -64, -69, -75, -62, -75, -65, -44, -54, -71, -41, -25, -57, -58, -50, --46, -39, -55, -50, -56, -56, -79, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -121, -128, -128, -126, -88, -86, -97, -91, -110, -122, -109, -124, -109, --104, -92, -89, -87, -67, -89, -102, -98, -88, -76, -93, -101, -105, -104, -127, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --121, -128, -128, -128, -128, -128, -128, -128, -128, -119, -125, -120, -104, -111, -128, -128, --127, -122, -128, -122, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, --128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128 -}; - - - -const float32_t sine_fs16k_7992[2048] = { - 0.0, 0.0, 0.003142, 0.0, -0.006283, 0.0, 0.009425, 0.0, - -0.01257, 0.0, 0.01571, 0.0, -0.01885, 0.0, 0.02199, 0.0, - -0.02513, 0.0, 0.02827, 0.0, -0.03141, 0.0, 0.03455, 0.0, - -0.03769, 0.0, 0.04083, 0.0, -0.04397, 0.0, 0.04711, 0.0, - -0.05024, 0.0, 0.05338, 0.0, -0.05652, 0.0, 0.05965, 0.0, - -0.06279, 0.0, 0.06593, 0.0, -0.06906, 0.0, 0.07219, 0.0, - -0.07533, 0.0, 0.07846, 0.0, -0.08159, 0.0, 0.08472, 0.0, - -0.08785, 0.0, 0.09098, 0.0, -0.09411, 0.0, 0.09724, 0.0, - -0.1004, 0.0, 0.1035, 0.0, -0.1066, 0.0, 0.1097, 0.0, - -0.1129, 0.0, 0.116, 0.0, -0.1191, 0.0, 0.1222, 0.0, - -0.1253, 0.0, 0.1284, 0.0, -0.1316, 0.0, 0.1347, 0.0, - -0.1378, 0.0, 0.1409, 0.0, -0.144, 0.0, 0.1471, 0.0, - -0.1502, 0.0, 0.1533, 0.0, -0.1564, 0.0, 0.1595, 0.0, - -0.1626, 0.0, 0.1657, 0.0, -0.1688, 0.0, 0.1719, 0.0, - -0.175, 0.0, 0.1781, 0.0, -0.1812, 0.0, 0.1843, 0.0, - -0.1874, 0.0, 0.1905, 0.0, -0.1935, 0.0, 0.1966, 0.0, - -0.1997, 0.0, 0.2028, 0.0, -0.2059, 0.0, 0.2089, 0.0, - -0.212, 0.0, 0.2151, 0.0, -0.2181, 0.0, 0.2212, 0.0, - -0.2243, 0.0, 0.2273, 0.0, -0.2304, 0.0, 0.2334, 0.0, - -0.2365, 0.0, 0.2396, 0.0, -0.2426, 0.0, 0.2456, 0.0, - -0.2487, 0.0, 0.2517, 0.0, -0.2548, 0.0, 0.2578, 0.0, - -0.2608, 0.0, 0.2639, 0.0, -0.2669, 0.0, 0.2699, 0.0, - -0.273, 0.0, 0.276, 0.0, -0.279, 0.0, 0.282, 0.0, - -0.285, 0.0, 0.288, 0.0, -0.291, 0.0, 0.294, 0.0, - -0.297, 0.0, 0.3, 0.0, -0.303, 0.0, 0.306, 0.0, - -0.309, 0.0, 0.312, 0.0, -0.315, 0.0, 0.318, 0.0, - -0.3209, 0.0, 0.3239, 0.0, -0.3269, 0.0, 0.3299, 0.0, - -0.3328, 0.0, 0.3358, 0.0, -0.3387, 0.0, 0.3417, 0.0, - -0.3446, 0.0, 0.3476, 0.0, -0.3505, 0.0, 0.3535, 0.0, - -0.3564, 0.0, 0.3593, 0.0, -0.3623, 0.0, 0.3652, 0.0, - -0.3681, 0.0, 0.371, 0.0, -0.374, 0.0, 0.3769, 0.0, - -0.3798, 0.0, 0.3827, 0.0, -0.3856, 0.0, 0.3885, 0.0, - -0.3914, 0.0, 0.3943, 0.0, -0.3971, 0.0, 0.4, 0.0, - -0.4029, 0.0, 0.4058, 0.0, -0.4086, 0.0, 0.4115, 0.0, - -0.4144, 0.0, 0.4172, 0.0, -0.4201, 0.0, 0.4229, 0.0, - -0.4258, 0.0, 0.4286, 0.0, -0.4315, 0.0, 0.4343, 0.0, - -0.4371, 0.0, 0.4399, 0.0, -0.4428, 0.0, 0.4456, 0.0, - -0.4484, 0.0, 0.4512, 0.0, -0.454, 0.0, 0.4568, 0.0, - -0.4596, 0.0, 0.4624, 0.0, -0.4652, 0.0, 0.4679, 0.0, - -0.4707, 0.0, 0.4735, 0.0, -0.4762, 0.0, 0.479, 0.0, - -0.4818, 0.0, 0.4845, 0.0, -0.4873, 0.0, 0.49, 0.0, - -0.4927, 0.0, 0.4955, 0.0, -0.4982, 0.0, 0.5009, 0.0, - -0.5036, 0.0, 0.5063, 0.0, -0.509, 0.0, 0.5117, 0.0, - -0.5144, 0.0, 0.5171, 0.0, -0.5198, 0.0, 0.5225, 0.0, - -0.5252, 0.0, 0.5278, 0.0, -0.5305, 0.0, 0.5332, 0.0, - -0.5358, 0.0, 0.5385, 0.0, -0.5411, 0.0, 0.5438, 0.0, - -0.5464, 0.0, 0.549, 0.0, -0.5516, 0.0, 0.5543, 0.0, - -0.5569, 0.0, 0.5595, 0.0, -0.5621, 0.0, 0.5647, 0.0, - -0.5673, 0.0, 0.5699, 0.0, -0.5724, 0.0, 0.575, 0.0, - -0.5776, 0.0, 0.5801, 0.0, -0.5827, 0.0, 0.5852, 0.0, - -0.5878, 0.0, 0.5903, 0.0, -0.5929, 0.0, 0.5954, 0.0, - -0.5979, 0.0, 0.6004, 0.0, -0.6029, 0.0, 0.6054, 0.0, - -0.6079, 0.0, 0.6104, 0.0, -0.6129, 0.0, 0.6154, 0.0, - -0.6179, 0.0, 0.6203, 0.0, -0.6228, 0.0, 0.6252, 0.0, - -0.6277, 0.0, 0.6301, 0.0, -0.6326, 0.0, 0.635, 0.0, - -0.6374, 0.0, 0.6398, 0.0, -0.6423, 0.0, 0.6447, 0.0, - -0.6471, 0.0, 0.6494, 0.0, -0.6518, 0.0, 0.6542, 0.0, - -0.6566, 0.0, 0.659, 0.0, -0.6613, 0.0, 0.6637, 0.0, - -0.666, 0.0, 0.6684, 0.0, -0.6707, 0.0, 0.673, 0.0, - -0.6753, 0.0, 0.6776, 0.0, -0.68, 0.0, 0.6823, 0.0, - -0.6845, 0.0, 0.6868, 0.0, -0.6891, 0.0, 0.6914, 0.0, - -0.6937, 0.0, 0.6959, 0.0, -0.6982, 0.0, 0.7004, 0.0, - -0.7026, 0.0, 0.7049, 0.0, -0.7071, 0.0, 0.7093, 0.0, - -0.7115, 0.0, 0.7137, 0.0, -0.7159, 0.0, 0.7181, 0.0, - -0.7203, 0.0, 0.7225, 0.0, -0.7247, 0.0, 0.7268, 0.0, - -0.729, 0.0, 0.7311, 0.0, -0.7333, 0.0, 0.7354, 0.0, - -0.7375, 0.0, 0.7396, 0.0, -0.7417, 0.0, 0.7438, 0.0, - -0.7459, 0.0, 0.748, 0.0, -0.7501, 0.0, 0.7522, 0.0, - -0.7543, 0.0, 0.7563, 0.0, -0.7584, 0.0, 0.7604, 0.0, - -0.7624, 0.0, 0.7645, 0.0, -0.7665, 0.0, 0.7685, 0.0, - -0.7705, 0.0, 0.7725, 0.0, -0.7745, 0.0, 0.7765, 0.0, - -0.7785, 0.0, 0.7804, 0.0, -0.7824, 0.0, 0.7843, 0.0, - -0.7863, 0.0, 0.7882, 0.0, -0.7902, 0.0, 0.7921, 0.0, - -0.794, 0.0, 0.7959, 0.0, -0.7978, 0.0, 0.7997, 0.0, - -0.8016, 0.0, 0.8034, 0.0, -0.8053, 0.0, 0.8072, 0.0, - -0.809, 0.0, 0.8109, 0.0, -0.8127, 0.0, 0.8145, 0.0, - -0.8163, 0.0, 0.8181, 0.0, -0.82, 0.0, 0.8217, 0.0, - -0.8235, 0.0, 0.8253, 0.0, -0.8271, 0.0, 0.8288, 0.0, - -0.8306, 0.0, 0.8323, 0.0, -0.8341, 0.0, 0.8358, 0.0, - -0.8375, 0.0, 0.8392, 0.0, -0.8409, 0.0, 0.8426, 0.0, - -0.8443, 0.0, 0.846, 0.0, -0.8477, 0.0, 0.8493, 0.0, - -0.851, 0.0, 0.8526, 0.0, -0.8543, 0.0, 0.8559, 0.0, - -0.8575, 0.0, 0.8591, 0.0, -0.8607, 0.0, 0.8623, 0.0, - -0.8639, 0.0, 0.8655, 0.0, -0.8671, 0.0, 0.8686, 0.0, - -0.8702, 0.0, 0.8717, 0.0, -0.8733, 0.0, 0.8748, 0.0, - -0.8763, 0.0, 0.8778, 0.0, -0.8793, 0.0, 0.8808, 0.0, - -0.8823, 0.0, 0.8838, 0.0, -0.8852, 0.0, 0.8867, 0.0, - -0.8881, 0.0, 0.8896, 0.0, -0.891, 0.0, 0.8924, 0.0, - -0.8938, 0.0, 0.8952, 0.0, -0.8966, 0.0, 0.898, 0.0, - -0.8994, 0.0, 0.9008, 0.0, -0.9021, 0.0, 0.9035, 0.0, - -0.9048, 0.0, 0.9062, 0.0, -0.9075, 0.0, 0.9088, 0.0, - -0.9101, 0.0, 0.9114, 0.0, -0.9127, 0.0, 0.914, 0.0, - -0.9152, 0.0, 0.9165, 0.0, -0.9178, 0.0, 0.919, 0.0, - -0.9202, 0.0, 0.9215, 0.0, -0.9227, 0.0, 0.9239, 0.0, - -0.9251, 0.0, 0.9263, 0.0, -0.9274, 0.0, 0.9286, 0.0, - -0.9298, 0.0, 0.9309, 0.0, -0.9321, 0.0, 0.9332, 0.0, - -0.9343, 0.0, 0.9354, 0.0, -0.9365, 0.0, 0.9376, 0.0, - -0.9387, 0.0, 0.9398, 0.0, -0.9409, 0.0, 0.9419, 0.0, - -0.943, 0.0, 0.944, 0.0, -0.9451, 0.0, 0.9461, 0.0, - -0.9471, 0.0, 0.9481, 0.0, -0.9491, 0.0, 0.9501, 0.0, - -0.9511, 0.0, 0.952, 0.0, -0.953, 0.0, 0.9539, 0.0, - -0.9549, 0.0, 0.9558, 0.0, -0.9567, 0.0, 0.9576, 0.0, - -0.9585, 0.0, 0.9594, 0.0, -0.9603, 0.0, 0.9612, 0.0, - -0.962, 0.0, 0.9629, 0.0, -0.9637, 0.0, 0.9646, 0.0, - -0.9654, 0.0, 0.9662, 0.0, -0.967, 0.0, 0.9678, 0.0, - -0.9686, 0.0, 0.9694, 0.0, -0.9701, 0.0, 0.9709, 0.0, - -0.9716, 0.0, 0.9724, 0.0, -0.9731, 0.0, 0.9738, 0.0, - -0.9745, 0.0, 0.9752, 0.0, -0.9759, 0.0, 0.9766, 0.0, - -0.9773, 0.0, 0.9779, 0.0, -0.9786, 0.0, 0.9792, 0.0, - -0.9799, 0.0, 0.9805, 0.0, -0.9811, 0.0, 0.9817, 0.0, - -0.9823, 0.0, 0.9829, 0.0, -0.9834, 0.0, 0.984, 0.0, - -0.9846, 0.0, 0.9851, 0.0, -0.9856, 0.0, 0.9862, 0.0, - -0.9867, 0.0, 0.9872, 0.0, -0.9877, 0.0, 0.9882, 0.0, - -0.9887, 0.0, 0.9891, 0.0, -0.9896, 0.0, 0.99, 0.0, - -0.9905, 0.0, 0.9909, 0.0, -0.9913, 0.0, 0.9917, 0.0, - -0.9921, 0.0, 0.9925, 0.0, -0.9929, 0.0, 0.9933, 0.0, - -0.9936, 0.0, 0.994, 0.0, -0.9943, 0.0, 0.9946, 0.0, - -0.995, 0.0, 0.9953, 0.0, -0.9956, 0.0, 0.9959, 0.0, - -0.9961, 0.0, 0.9964, 0.0, -0.9967, 0.0, 0.9969, 0.0, - -0.9972, 0.0, 0.9974, 0.0, -0.9976, 0.0, 0.9978, 0.0, - -0.998, 0.0, 0.9982, 0.0, -0.9984, 0.0, 0.9986, 0.0, - -0.9987, 0.0, 0.9989, 0.0, -0.999, 0.0, 0.9992, 0.0, - -0.9993, 0.0, 0.9994, 0.0, -0.9995, 0.0, 0.9996, 0.0, - -0.9997, 0.0, 0.9998, 0.0, -0.9998, 0.0, 0.9999, 0.0, - -0.9999, 0.0, 1.0, 0.0, -1.0, 0.0, 1.0, 0.0, - -1.0, 0.0, 1.0, 0.0, -1.0, 0.0, 1.0, 0.0, - -0.9999, 0.0, 0.9999, 0.0, -0.9998, 0.0, 0.9998, 0.0, - -0.9997, 0.0, 0.9996, 0.0, -0.9995, 0.0, 0.9994, 0.0, - -0.9993, 0.0, 0.9992, 0.0, -0.999, 0.0, 0.9989, 0.0, - -0.9987, 0.0, 0.9986, 0.0, -0.9984, 0.0, 0.9982, 0.0, - -0.998, 0.0, 0.9978, 0.0, -0.9976, 0.0, 0.9974, 0.0, - -0.9972, 0.0, 0.9969, 0.0, -0.9967, 0.0, 0.9964, 0.0, - -0.9961, 0.0, 0.9959, 0.0, -0.9956, 0.0, 0.9953, 0.0, - -0.995, 0.0, 0.9946, 0.0, -0.9943, 0.0, 0.994, 0.0, - -0.9936, 0.0, 0.9933, 0.0, -0.9929, 0.0, 0.9925, 0.0, - -0.9921, 0.0, 0.9917, 0.0, -0.9913, 0.0, 0.9909, 0.0, - -0.9905, 0.0, 0.99, 0.0, -0.9896, 0.0, 0.9891, 0.0, - -0.9887, 0.0, 0.9882, 0.0, -0.9877, 0.0, 0.9872, 0.0, - -0.9867, 0.0, 0.9862, 0.0, -0.9856, 0.0, 0.9851, 0.0, - -0.9846, 0.0, 0.984, 0.0, -0.9834, 0.0, 0.9829, 0.0, - -0.9823, 0.0, 0.9817, 0.0, -0.9811, 0.0, 0.9805, 0.0, - -0.9799, 0.0, 0.9792, 0.0, -0.9786, 0.0, 0.9779, 0.0, - -0.9773, 0.0, 0.9766, 0.0, -0.9759, 0.0, 0.9752, 0.0, - -0.9745, 0.0, 0.9738, 0.0, -0.9731, 0.0, 0.9724, 0.0, - -0.9716, 0.0, 0.9709, 0.0, -0.9701, 0.0, 0.9694, 0.0, - -0.9686, 0.0, 0.9678, 0.0, -0.967, 0.0, 0.9662, 0.0, - -0.9654, 0.0, 0.9646, 0.0, -0.9637, 0.0, 0.9629, 0.0, - -0.962, 0.0, 0.9612, 0.0, -0.9603, 0.0, 0.9594, 0.0, - -0.9585, 0.0, 0.9576, 0.0, -0.9567, 0.0, 0.9558, 0.0, - -0.9549, 0.0, 0.9539, 0.0, -0.953, 0.0, 0.952, 0.0, - -0.9511, 0.0, 0.9501, 0.0, -0.9491, 0.0, 0.9481, 0.0, - -0.9471, 0.0, 0.9461, 0.0, -0.9451, 0.0, 0.944, 0.0, - -0.943, 0.0, 0.9419, 0.0, -0.9409, 0.0, 0.9398, 0.0, - -0.9387, 0.0, 0.9376, 0.0, -0.9365, 0.0, 0.9354, 0.0, - -0.9343, 0.0, 0.9332, 0.0, -0.9321, 0.0, 0.9309, 0.0, - -0.9298, 0.0, 0.9286, 0.0, -0.9274, 0.0, 0.9263, 0.0, - -0.9251, 0.0, 0.9239, 0.0, -0.9227, 0.0, 0.9215, 0.0, - -0.9202, 0.0, 0.919, 0.0, -0.9178, 0.0, 0.9165, 0.0, - -0.9152, 0.0, 0.914, 0.0, -0.9127, 0.0, 0.9114, 0.0, - -0.9101, 0.0, 0.9088, 0.0, -0.9075, 0.0, 0.9062, 0.0, - -0.9048, 0.0, 0.9035, 0.0, -0.9021, 0.0, 0.9008, 0.0, - -0.8994, 0.0, 0.898, 0.0, -0.8966, 0.0, 0.8952, 0.0, - -0.8938, 0.0, 0.8924, 0.0, -0.891, 0.0, 0.8896, 0.0, - -0.8881, 0.0, 0.8867, 0.0, -0.8852, 0.0, 0.8838, 0.0, - -0.8823, 0.0, 0.8808, 0.0, -0.8793, 0.0, 0.8778, 0.0, - -0.8763, 0.0, 0.8748, 0.0, -0.8733, 0.0, 0.8717, 0.0, - -0.8702, 0.0, 0.8686, 0.0, -0.8671, 0.0, 0.8655, 0.0, - -0.8639, 0.0, 0.8623, 0.0, -0.8607, 0.0, 0.8591, 0.0, - -0.8575, 0.0, 0.8559, 0.0, -0.8543, 0.0, 0.8526, 0.0, - -0.851, 0.0, 0.8493, 0.0, -0.8477, 0.0, 0.846, 0.0, - -0.8443, 0.0, 0.8426, 0.0, -0.8409, 0.0, 0.8392, 0.0, - -0.8375, 0.0, 0.8358, 0.0, -0.8341, 0.0, 0.8323, 0.0, - -0.8306, 0.0, 0.8288, 0.0, -0.8271, 0.0, 0.8253, 0.0, - -0.8235, 0.0, 0.8217, 0.0, -0.82, 0.0, 0.8181, 0.0, - -0.8163, 0.0, 0.8145, 0.0, -0.8127, 0.0, 0.8109, 0.0, - -0.809, 0.0, 0.8072, 0.0, -0.8053, 0.0, 0.8034, 0.0, - -0.8016, 0.0, 0.7997, 0.0, -0.7978, 0.0, 0.7959, 0.0, - -0.794, 0.0, 0.7921, 0.0, -0.7902, 0.0, 0.7882, 0.0, - -0.7863, 0.0, 0.7843, 0.0, -0.7824, 0.0, 0.7804, 0.0, - -0.7785, 0.0, 0.7765, 0.0, -0.7745, 0.0, 0.7725, 0.0, - -0.7705, 0.0, 0.7685, 0.0, -0.7665, 0.0, 0.7645, 0.0, - -0.7624, 0.0, 0.7604, 0.0, -0.7584, 0.0, 0.7563, 0.0, - -0.7543, 0.0, 0.7522, 0.0, -0.7501, 0.0, 0.748, 0.0, - -0.7459, 0.0, 0.7438, 0.0, -0.7417, 0.0, 0.7396, 0.0, - -0.7375, 0.0, 0.7354, 0.0, -0.7333, 0.0, 0.7311, 0.0, - -0.729, 0.0, 0.7268, 0.0, -0.7247, 0.0, 0.7225, 0.0, - -0.7203, 0.0, 0.7181, 0.0, -0.7159, 0.0, 0.7137, 0.0, - -0.7115, 0.0, 0.7093, 0.0, -0.7071, 0.0, 0.7049, 0.0, - -0.7026, 0.0, 0.7004, 0.0, -0.6982, 0.0, 0.6959, 0.0, - -0.6937, 0.0, 0.6914, 0.0, -0.6891, 0.0, 0.6868, 0.0, - -0.6845, 0.0, 0.6823, 0.0, -0.68, 0.0, 0.6776, 0.0, - -0.6753, 0.0, 0.673, 0.0, -0.6707, 0.0, 0.6684, 0.0, - -0.666, 0.0, 0.6637, 0.0, -0.6613, 0.0, 0.659, 0.0, - -0.6566, 0.0, 0.6542, 0.0, -0.6518, 0.0, 0.6494, 0.0, - -0.6471, 0.0, 0.6447, 0.0, -0.6423, 0.0, 0.6398, 0.0, - -0.6374, 0.0, 0.635, 0.0, -0.6326, 0.0, 0.6301, 0.0, - -0.6277, 0.0, 0.6252, 0.0, -0.6228, 0.0, 0.6203, 0.0, - -0.6179, 0.0, 0.6154, 0.0, -0.6129, 0.0, 0.6104, 0.0, - -0.6079, 0.0, 0.6054, 0.0, -0.6029, 0.0, 0.6004, 0.0, - -0.5979, 0.0, 0.5954, 0.0, -0.5929, 0.0, 0.5903, 0.0, - -0.5878, 0.0, 0.5852, 0.0, -0.5827, 0.0, 0.5801, 0.0, - -0.5776, 0.0, 0.575, 0.0, -0.5724, 0.0, 0.5699, 0.0, - -0.5673, 0.0, 0.5647, 0.0, -0.5621, 0.0, 0.5595, 0.0, - -0.5569, 0.0, 0.5543, 0.0, -0.5516, 0.0, 0.549, 0.0, - -0.5464, 0.0, 0.5438, 0.0, -0.5411, 0.0, 0.5385, 0.0, - -0.5358, 0.0, 0.5332, 0.0, -0.5305, 0.0, 0.5278, 0.0, - -0.5252, 0.0, 0.5225, 0.0, -0.5198, 0.0, 0.5171, 0.0, - -0.5144, 0.0, 0.5117, 0.0, -0.509, 0.0, 0.5063, 0.0, - -0.5036, 0.0, 0.5009, 0.0, -0.4982, 0.0, 0.4955, 0.0, - -0.4927, 0.0, 0.49, 0.0, -0.4873, 0.0, 0.4845, 0.0, - -0.4818, 0.0, 0.479, 0.0, -0.4762, 0.0, 0.4735, 0.0, - -0.4707, 0.0, 0.4679, 0.0, -0.4652, 0.0, 0.4624, 0.0, - -0.4596, 0.0, 0.4568, 0.0, -0.454, 0.0, 0.4512, 0.0, - -0.4484, 0.0, 0.4456, 0.0, -0.4428, 0.0, 0.4399, 0.0, - -0.4371, 0.0, 0.4343, 0.0, -0.4315, 0.0, 0.4286, 0.0, - -0.4258, 0.0, 0.4229, 0.0, -0.4201, 0.0, 0.4172, 0.0, - -0.4144, 0.0, 0.4115, 0.0, -0.4086, 0.0, 0.4058, 0.0, - -0.4029, 0.0, 0.4, 0.0, -0.3971, 0.0, 0.3943, 0.0, - -0.3914, 0.0, 0.3885, 0.0, -0.3856, 0.0, 0.3827, 0.0, - -0.3798, 0.0, 0.3769, 0.0, -0.374, 0.0, 0.371, 0.0, - -0.3681, 0.0, 0.3652, 0.0, -0.3623, 0.0, 0.3593, 0.0, - -0.3564, 0.0, 0.3535, 0.0, -0.3505, 0.0, 0.3476, 0.0, - -0.3446, 0.0, 0.3417, 0.0, -0.3387, 0.0, 0.3358, 0.0, - -0.3328, 0.0, 0.3299, 0.0, -0.3269, 0.0, 0.3239, 0.0, - -0.3209, 0.0, 0.318, 0.0, -0.315, 0.0, 0.312, 0.0, - -0.309, 0.0, 0.306, 0.0, -0.303, 0.0, 0.3, 0.0, - -0.297, 0.0, 0.294, 0.0, -0.291, 0.0, 0.288, 0.0, - -0.285, 0.0, 0.282, 0.0, -0.279, 0.0, 0.276, 0.0, - -0.273, 0.0, 0.2699, 0.0, -0.2669, 0.0, 0.2639, 0.0, - -0.2608, 0.0, 0.2578, 0.0, -0.2548, 0.0, 0.2517, 0.0, - -0.2487, 0.0, 0.2456, 0.0, -0.2426, 0.0, 0.2396, 0.0, - -0.2365, 0.0, 0.2334, 0.0, -0.2304, 0.0, 0.2273, 0.0, - -0.2243, 0.0, 0.2212, 0.0, -0.2181, 0.0, 0.2151, 0.0, - -0.212, 0.0, 0.2089, 0.0, -0.2059, 0.0, 0.2028, 0.0, - -0.1997, 0.0, 0.1966, 0.0, -0.1935, 0.0, 0.1905, 0.0, - -0.1874, 0.0, 0.1843, 0.0, -0.1812, 0.0, 0.1781, 0.0, - -0.175, 0.0, 0.1719, 0.0, -0.1688, 0.0, 0.1657, 0.0, - -0.1626, 0.0, 0.1595, 0.0, -0.1564, 0.0, 0.1533, 0.0, - -0.1502, 0.0, 0.1471, 0.0, -0.144, 0.0, 0.1409, 0.0, - -0.1378, 0.0, 0.1347, 0.0, -0.1316, 0.0, 0.1284, 0.0, - -0.1253, 0.0, 0.1222, 0.0, -0.1191, 0.0, 0.116, 0.0, - -0.1129, 0.0, 0.1097, 0.0, -0.1066, 0.0, 0.1035, 0.0, - -0.1004, 0.0, 0.09724, 0.0, -0.09411, 0.0, 0.09098, 0.0, - -0.08785, 0.0, 0.08472, 0.0, -0.08159, 0.0, 0.07846, 0.0, - -0.07533, 0.0, 0.07219, 0.0, -0.06906, 0.0, 0.06593, 0.0, - -0.06279, 0.0, 0.05965, 0.0, -0.05652, 0.0, 0.05338, 0.0, - -0.05024, 0.0, 0.04711, 0.0, -0.04397, 0.0, 0.04083, 0.0, - -0.03769, 0.0, 0.03455, 0.0, -0.03141, 0.0, 0.02827, 0.0, - -0.02513, 0.0, 0.02199, 0.0, -0.01885, 0.0, 0.01571, 0.0, - -0.01257, 0.0, 0.009425, 0.0, -0.006283, 0.0, 0.003142, 0.0, - 1.969e-13, 0.0, -0.003142, 0.0, 0.006283, 0.0, -0.009425, 0.0, - 0.01257, 0.0, -0.01571, 0.0, 0.01885, 0.0, -0.02199, 0.0, - 0.02513, 0.0, -0.02827, 0.0, 0.03141, 0.0, -0.03455, 0.0, - 0.03769, 0.0, -0.04083, 0.0, 0.04397, 0.0, -0.04711, 0.0, - 0.05024, 0.0, -0.05338, 0.0, 0.05652, 0.0, -0.05965, 0.0, - 0.06279, 0.0, -0.06593, 0.0, 0.06906, 0.0, -0.07219, 0.0 - }; - - - -const float32_t sine_fs16k_200[2048] = { - 0.0, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, - 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, - 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, - 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, - 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, - 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, - 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, - 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, - 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, - 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, - 1.225e-16, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, - -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, - -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, - -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, - -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, - -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, - -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, - -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, - -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, - -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, - -2.449e-16, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, - 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, - 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, - 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, - 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, - 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, - 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, - 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, - 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, - 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, - 3.674e-16, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, - -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, - -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, - -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, - -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, - -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, - -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, - -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, - -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, - -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, - -4.899e-16, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, - 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, - 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, - 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, - 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, - 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, - 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, - 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, - 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, - 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, - -1.164e-15, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, - -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, - -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, - -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, - -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, - -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, - -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, - -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, - -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, - -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, - -7.348e-16, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, - 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, - 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, - 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, - 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, - 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, - 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, - 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, - 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, - 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, - -2.695e-15, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, - -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, - -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, - -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, - -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, - -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, - -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, - -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, - -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, - -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, - -9.797e-16, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, - 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, - 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, - 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, - 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, - 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, - 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, - 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, - 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, - 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, - 1.102e-15, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, - -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, - -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, - -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, - -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, - -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, - -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, - -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, - -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, - -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, - 2.328e-15, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, - 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, - 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, - 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, - 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, - 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, - 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, - 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, - 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, - 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, - -2.206e-15, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, - -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, - -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, - -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, - -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, - -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, - -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, - -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, - -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, - -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, - -1.47e-15, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, - 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, - 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, - 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, - 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, - 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, - 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, - 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, - 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, - 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, - -1.961e-15, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, - -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, - -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, - -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, - -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, - -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, - -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, - -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, - -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, - -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, - 5.391e-15, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, - 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, - 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, - 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, - 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, - 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, - 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, - 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, - 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, - 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, - -1.716e-15, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, - -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, - -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, - -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, - -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, - -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, - -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, - -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, - -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, - -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, - -1.959e-15, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, - 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, - 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, - 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, - 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, - 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, - 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, - 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, - 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, - 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, - -1.471e-15, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, - -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, - -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, - -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, - -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, - -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, - -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, - -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, - -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, - -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, - -2.204e-15, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, - 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, - 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, - 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, - 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, - 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, - 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, - 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, - 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, - 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, - -1.226e-15, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, - -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, - -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, - -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, - -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, - -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, - -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, - -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, - -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, - -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, - 4.656e-15, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, - 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, - 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, - 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, - 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, - 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, - 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, - 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, - 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, - 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, - -9.81e-16, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, - -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, - -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, - -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, - -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, - -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, - -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, - -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, - -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, - -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, - 4.411e-15, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, - 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, - 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, - 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, - 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, - 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, - 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, - 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, - 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, - 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, - -7.841e-15, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, - -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, - -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, - -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, - -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, - -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0, - -0.9511, 0.0, -0.9239, 0.0, -0.891, 0.0, -0.8526, 0.0, - -0.809, 0.0, -0.7604, 0.0, -0.7071, 0.0, -0.6494, 0.0, - -0.5878, 0.0, -0.5225, 0.0, -0.454, 0.0, -0.3827, 0.0, - -0.309, 0.0, -0.2334, 0.0, -0.1564, 0.0, -0.07846, 0.0, - -2.939e-15, 0.0, 0.07846, 0.0, 0.1564, 0.0, 0.2334, 0.0, - 0.309, 0.0, 0.3827, 0.0, 0.454, 0.0, 0.5225, 0.0, - 0.5878, 0.0, 0.6494, 0.0, 0.7071, 0.0, 0.7604, 0.0, - 0.809, 0.0, 0.8526, 0.0, 0.891, 0.0, 0.9239, 0.0, - 0.9511, 0.0, 0.9724, 0.0, 0.9877, 0.0, 0.9969, 0.0, - 1.0, 0.0, 0.9969, 0.0, 0.9877, 0.0, 0.9724, 0.0, - 0.9511, 0.0, 0.9239, 0.0, 0.891, 0.0, 0.8526, 0.0, - 0.809, 0.0, 0.7604, 0.0, 0.7071, 0.0, 0.6494, 0.0, - 0.5878, 0.0, 0.5225, 0.0, 0.454, 0.0, 0.3827, 0.0, - 0.309, 0.0, 0.2334, 0.0, 0.1564, 0.0, 0.07846, 0.0, - -4.911e-16, 0.0, -0.07846, 0.0, -0.1564, 0.0, -0.2334, 0.0, - -0.309, 0.0, -0.3827, 0.0, -0.454, 0.0, -0.5225, 0.0, - -0.5878, 0.0, -0.6494, 0.0, -0.7071, 0.0, -0.7604, 0.0, - -0.809, 0.0, -0.8526, 0.0, -0.891, 0.0, -0.9239, 0.0, - -0.9511, 0.0, -0.9724, 0.0, -0.9877, 0.0, -0.9969, 0.0, - -1.0, 0.0, -0.9969, 0.0, -0.9877, 0.0, -0.9724, 0.0 - }; diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Src/sww_util.c b/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Src/sww_util.c deleted file mode 100644 index dfcbfb28..00000000 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/Core/Src/sww_util.c +++ /dev/null @@ -1,402 +0,0 @@ -/* - * sww_util.c - * - * Created on: Jan 16, 2025 - * Author: jeremy - */ - -#include -#include -#include -#include -#include - -#include "stm32l4xx_hal.h" - -#include "sww_util.h" -#include "feature_extraction.h" - -// needed for running the model and/or initializing inference setup -#include "sww_model.h" -#include "sww_model_data.h" -#include "model_test_inputs.h" - -// I don't want to move the main declaration out of main.c because it is auto-generated by CubeMX -extern SAI_HandleTypeDef hsai_BlockA1; - -#define MAX_CMD_TOKENS 8 // maximum number of tokens in a command, including the command and arguments -// Command buffer (incoming commands from host) -char g_cmd_buf[EE_CMD_SIZE + 1]; -size_t g_cmd_pos = 0u; - -// variables for I2S receive -uint32_t g_int16s_read = 0; -uint32_t g_i2s_chunk_size_bytes = 1024; -uint32_t g_i2s_status = HAL_OK; -// two ping-pong byte buffers for DMA transfers from I2S port. -uint8_t *g_i2s_buffer0 = NULL; -uint8_t *g_i2s_buffer1 = NULL; -uint8_t *g_i2s_current_buff = NULL; // will be either g_i2s_buffer0 or g_i2s_buffer1 -int g_i2s_buff_sel = 0; // 0 for buffer0, 1 for buffer1 -int16_t *g_wav_record = NULL; // buffer to store complete waveform -uint32_t g_i2s_wav_len = 32*512; // length in (16b) samples -int g_i2s_rx_in_progess = 0; -LogBuffer g_log = { .buffer = {0}, .current_pos = 0 }; - - -void setup_i2s_buffers() { - // set up variables for I2S receiving - g_i2s_buffer0 = malloc(g_i2s_chunk_size_bytes); - g_i2s_buffer1 = malloc(g_i2s_chunk_size_bytes); - g_i2s_current_buff = g_i2s_buffer0; - g_wav_record = (int16_t *)malloc(g_i2s_wav_len * sizeof(int16_t)); -} - -void print_vals_int16(int16_t *buffer, uint32_t num_vals) -{ - const int vals_per_line = 16; - printf("["); - for(uint32_t i=0;i= num_vals) - { - break; - } - printf("%d, ", buffer[i+j]); - } - printf("\r\n"); - } - printf("]\r\n==== Done ====\r\n"); -} - -void print_bytes(uint8_t *buffer, uint32_t num_bytes) -{ - const int vals_per_line = 16; - printf("["); - for(uint32_t i=0;i= num_bytes) - { - break; - } - printf("0x%X, ", buffer[i+j]); - } - printf("\r\n"); - } - printf("]\r\n==== Done ====\r\n"); -} - - -void print_vals_float(float *buffer, uint32_t num_vals) -{ - const int vals_per_line = 8; - printf("["); - for(uint32_t i=0;i= num_vals) - { - break; - } - printf("%3.4f, ", buffer[i+j]); - } - printf("\r\n"); - } - printf("]\r\n==== Done ====\r\n"); -} -void log_printf(LogBuffer *log, const char *format, ...) { - va_list args; - char temp_buffer[LOG_BUFFER_SIZE]; - int written; - - // Initialize the variable argument list - va_start(args, format); - - // Write formatted output to a temporary buffer - written = vsnprintf(temp_buffer, sizeof(temp_buffer), format, args); - - // End the variable argument list - va_end(args); - - // Check if the formatted string fits in the remaining buffer - if (log->current_pos + written >= LOG_BUFFER_SIZE) { - // Buffer overflow: Zero out and reset to the beginning - memset(log->buffer, 0, LOG_BUFFER_SIZE); - log->current_pos = 0; - } - - // Copy the formatted string to the log buffer - if (written > 0) { - size_t bytes_to_copy = (written < LOG_BUFFER_SIZE) ? written : LOG_BUFFER_SIZE - 1; - strncpy(&log->buffer[log->current_pos], temp_buffer, bytes_to_copy); - log->current_pos += bytes_to_copy; - } -} - - -/** - * This function assembles a command string from the UART. It should be called - * from the UART ISR for each new character received. When the parser sees the - * termination character, the user-defined th_command_ready() command is called. - * It is up to the application to then dispatch this command outside the ISR - * as soon as possible by calling ee_serial_command_parser_callback(), below. - */ -void ee_serial_callback(char c) { - if (c == EE_CMD_TERMINATOR) { - g_cmd_buf[g_cmd_pos] = (char)0; - process_command(g_cmd_buf); - g_cmd_pos = 0; - } else { - g_cmd_buf[g_cmd_pos] = c; - g_cmd_pos = g_cmd_pos >= EE_CMD_SIZE ? EE_CMD_SIZE : g_cmd_pos + 1; - } -} - - - - -/* Global handle to reference the instantiated C-model */ -static ai_handle sww_model = AI_HANDLE_NULL; - -/* Global c-array to handle the activations buffer */ -AI_ALIGNED(32) -static ai_i8 activations[AI_SWW_MODEL_DATA_ACTIVATIONS_SIZE]; - -/* Array to store the data of the input tensor */ -AI_ALIGNED(32) -static ai_i8 in_data[AI_SWW_MODEL_IN_1_SIZE]; -/* or static ai_i8 in_data[AI_SWW_MODEL_DATA_IN_1_SIZE_BYTES]; */ - -/* c-array to store the data of the output tensor */ -AI_ALIGNED(32) -static ai_i8 out_data[AI_SWW_MODEL_OUT_1_SIZE]; -/* static ai_i8 out_data[AI_SWW_MODEL_DATA_OUT_1_SIZE_BYTES]; */ - -/* Array of pointer to manage the model's input/output tensors */ -static ai_buffer *ai_input; -static ai_buffer *ai_output; - - -/* - * Bootstrap inference framework - */ -int aiInit(void) { - ai_error err; - - /* Create and initialize the c-model */ - const ai_handle acts[] = { activations }; - err = ai_sww_model_create_and_init(&sww_model, acts, NULL); - - if (err.type != AI_ERROR_NONE) { - ; - }; - - /* Reteive pointers to the model's input/output tensors */ - ai_input = ai_sww_model_inputs_get(sww_model, NULL); - ai_output = ai_sww_model_outputs_get(sww_model, NULL); - - return 0; -} - - - -/* - * Run inference - */ -int aiRun(const void *in_data, void *out_data) { - ai_i32 n_batch; - ai_error err; - - /* 1 - Update IO handlers with the data payload */ - ai_input[0].data = AI_HANDLE_PTR(in_data); - ai_output[0].data = AI_HANDLE_PTR(out_data); - - /* 2 - Perform the inference */ - n_batch = ai_sww_model_run(sww_model, &ai_input[0], &ai_output[0]); - if (n_batch != 1) { - err = ai_sww_model_get_error(sww_model); - - }; - - return 0; -} - -void run_model(char *cmd_args[]) { -// acquire_and_process_data(in_data); - const int8_t *input_source=NULL; - - printf("In run_model. about to run model\r\n"); - if (strcmp(cmd_args[1], "class0") == 0) { - input_source = test_input_class0; - } - else if (strcmp(cmd_args[1], "class1") == 0) { - input_source = test_input_class1; - } - else if (strcmp(cmd_args[1], "class2") == 0) { - input_source = test_input_class2; - } - else { - printf("Unknown input tensor name, defaulting to test_input_class0\r\n"); - input_source = test_input_class0; - } - for(int i=0;iState - printf("DMA receive initiated. status=%lu, state=%d\r\n", g_i2s_status, hsai_BlockA1.State); - printf(" Status: 0=OK, 1=Error, 2=Busy, 3=Timeout; State: 0=Reset, 1=Ready, 2=Busy (internal process), 18=Busy (Tx), 34=Busy (Rx)\r\n"); - } -} - -void print_and_clear_log(char *cmd_args[]) { - printf("Log contents[cp=%u]:\r\n<%s>\r\n", g_log.current_pos, g_log.buffer); - memset(g_log.buffer, 0, LOG_BUFFER_SIZE); - g_log.current_pos = 0; -} - -void process_command(char *full_command) { - - char *cmd_args[MAX_CMD_TOKENS] = {NULL}; - - printf("Full command: %s\r\n", full_command); - - char* token = strtok(full_command, " "); - cmd_args[0] = token; - - for(int i=1;i%s\r\n", i, (void *)cmd_args[i], cmd_args[i]); - } - - // full_command should be " " (command and args delimited by spaces) - // put the command and arguments into the array cmd_arg[] - if (strcmp(cmd_args[0], "name") == 0) { - printf("streaming wakeword test platform\r\n"); - } - else if(strcmp(cmd_args[0], "run_model") == 0) { - run_model(cmd_args); - } - else if(strcmp(cmd_args[0], "extract") == 0) { - run_extraction(cmd_args); - } - else if(strcmp(cmd_args[0], "i2scap") == 0) { - i2s_capture(cmd_args); - } - else if(strcmp(cmd_args[0], "log") == 0) { - print_and_clear_log(cmd_args); - } - else { - printf("Unrecognized command %s, with arguments %s\r\n", cmd_args[0], full_command); - } -} - - -void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) { - - log_printf(&g_log, "w0=%d\r\n", g_wav_record[0]); - int reading_complete=0; - - g_int16s_read += g_i2s_chunk_size_bytes/2; - - // idle_buffer is the one that will be idle after we switch - uint8_t* idle_buffer = g_i2s_buff_sel ? g_i2s_buffer1 : g_i2s_buffer0; - g_i2s_buff_sel = g_i2s_buff_sel ^ 1; // toggle between 0/1 => g_i2s_buffer0/1 - g_i2s_current_buff = g_i2s_buff_sel ? g_i2s_buffer1 : g_i2s_buffer0; - - if(g_int16s_read + g_i2s_chunk_size_bytes/2 <= g_i2s_wav_len){ - // there is space left for a full chunk - g_i2s_status = HAL_SAI_Receive_DMA(hsai, g_i2s_current_buff, g_i2s_chunk_size_bytes/2); - } - else { - // if there is only space for a partial read - // i.e. (g_int16s_read < g_i2s_wav_len < g_int16s_read + g_i2s_chunk_size_bytes/2) - // don't start the read, b/c you'll overflow the allocated buffer - // that means you'll read less than requested, but avoid a seg-fault. - reading_complete = 1; - } - - HAL_GPIO_WritePin(GPIOB, GPIO_PIN_8, GPIO_PIN_SET); - - // for 1024 bytes, this memcpy takes about 50 us. - // - memcpy((uint8_t*)(g_wav_record+g_int16s_read-g_i2s_chunk_size_bytes/2), idle_buffer, g_i2s_chunk_size_bytes); - - // This block just for debug. - // uint8_t *p_bytes=NULL; - - // p_bytes = (uint8_t*)(g_wav_record+g_int16s_read); - log_printf(&g_log, "cb:%lu,b%d,rs=%d,st=%d.\r\n", g_int16s_read, g_i2s_buff_sel, g_i2s_status, hsai->State); - // log_printf(&g_log, "\t[%8X] [0x%02X, 0x%02X, 0x%02X, 0x%02X]\r\n",p_bytes, p_bytes[0], p_bytes[1], p_bytes[2], p_bytes[3]); - - int16_t *p_int16s=(int16_t*)(g_wav_record); - log_printf(&g_log, "W0:\t[%8X] <= [%d, %d, %d, %d, %d, %d, %d, %d]\r\n",p_int16s, - p_int16s[0], p_int16s[1], p_int16s[2], p_int16s[3], p_int16s[4], p_int16s[5], p_int16s[6], p_int16s[7]); - - p_int16s=(int16_t*)(g_wav_record+g_int16s_read - g_i2s_chunk_size_bytes/2); - log_printf(&g_log, "WV:\t[%8X] <= [%d, %d, %d, %d, %d, %d, %d, %d]\r\n",p_int16s, - p_int16s[0], p_int16s[1], p_int16s[2], p_int16s[3], p_int16s[4], p_int16s[5], p_int16s[6], p_int16s[7]); - - p_int16s=(int16_t*)g_i2s_buffer0; - log_printf(&g_log, "B0\t[%8X] <= [%d, %d, %d, %d, %d, %d, %d, %d]\r\n",p_int16s, - p_int16s[0], p_int16s[1], p_int16s[2], p_int16s[3], p_int16s[4], p_int16s[5], p_int16s[6], p_int16s[7]); - - p_int16s=(int16_t*)g_i2s_buffer1; - log_printf(&g_log, "B1\t[%8X] <= [%d, %d, %d, %d, %d, %d, %d, %d]\r\n",p_int16s, - p_int16s[0], p_int16s[1], p_int16s[2], p_int16s[3], p_int16s[4], p_int16s[5], p_int16s[6], p_int16s[7]); - - // end debug block - - if( reading_complete ){ - printf("DMA Receive completed %lu int16s read out of %lu requested\r\n", g_int16s_read, g_i2s_wav_len); - print_vals_int16(g_wav_record, g_int16s_read); - g_i2s_rx_in_progess = 0; - } - HAL_GPIO_WritePin(GPIOB, GPIO_PIN_8, GPIO_PIN_RESET); - log_printf(&g_log, "w0=%d\r\n", g_wav_record[0]); -} - - diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model_data_params.c b/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model_data_params.c deleted file mode 100644 index fb1903be..00000000 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model_data_params.c +++ /dev/null @@ -1,776 +0,0 @@ -/** - ****************************************************************************** - * @file sww_model_data_params.c - * @author AST Embedded Analytics Research Platform - * @date 2025-01-19T06:26:52-0500 - * @brief AI Tool Automatic Code Generator for Embedded NN computing - ****************************************************************************** - * Copyright (c) 2025 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -#include "sww_model_data_params.h" - - -/** Activations Section ****************************************************/ -ai_handle g_sww_model_activations_table[1 + 2] = { - AI_HANDLE_PTR(AI_MAGIC_MARKER), - AI_HANDLE_PTR(NULL), - AI_HANDLE_PTR(AI_MAGIC_MARKER), -}; - - - - -/** Weights Section ********************************************************/ -AI_ALIGNED(32) -const ai_u64 s_sww_model_weights_array_u64[2940] = { - 0xf542460f8a6f810dU, 0x7f2ae4818c458131U, 0x7f4e7f06c57fdf7fU, 0x65ae41393520d9f7U, - 0xcc817f9f81116a81U, 0xd881dc7f815a9600U, 0x3e347f1fadc7d47fU, 0x40f99581d92c7fdcU, - 0x2d12a9e370df7fddU, 0xd030b801d2814d64U, 0x81da81ce7781577fU, 0x67813af27f8153adU, - 0xd481a5e17f572a99U, 0x817f8181817fbb7fU, 0x811de07f4401816bU, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x40c10da091adf01U, - 0xf00cef81c9d2cce4U, 0xff04161532ddffdaU, 0x22070001dffa10efU, 0xfa1a091b0901fae6U, - 0xeda8b5edf4d7ff1aU, 0xc47bfb182b0bb9f7U, 0xb0fae228ef0b26d6U, 0xe4583c0de47f040bU, - 0x4b318db01dc1106U, 0x403ec8dcc208016cU, 0xd43604d3d47535b2U, 0x5b09545781cc9209U, - 0x72dd452816693b18U, 0xf59c0fc6a3cd69e4U, 0x2a5c0ba5ba042e12U, 0xc71d3a0d44a81f5U, - 0xe5db31edab44e16cU, 0x2a33ea052adbe519U, 0xe201f7430d08ea20U, 0x4eecfe02de1a24faU, - 0xfb2b1b0e0805997fU, 0xc0dff7f5cb20e05bU, 0x106f6ffe6450cU, 0x20fafa2a0d1d3affU, - 0x390816d03dfbf601U, 0x342de59011d20005U, 0xeb0c81d43f0a26daU, 0xafb0e3b1af0b4a7U, - 0xfbf0ef330b340a14U, 0xfa06344da2cd671eU, 0x29f1b8fb81202c17U, 0xeb163596e14f04e4U, - 0x18e705eb86d7bf20U, 0xce61f083f25021aU, 0xab9d5efef2520feU, 0xfb1d61c9ee8b13dbU, - 0x3d03ccf4bed281f4U, 0xd4102d1704e8fcf9U, 0x4cf3fcfedbd4362eU, 0x3c5ac1027fab2a1cU, - 0xe7a5c2390446985eU, 0x4bf6d2ef15edbabfU, 0xad0ddc01bb04c131U, 0xc2f31df2143ebbeeU, - 0xcbaed64e1bf4f9e9U, 0x62bd60b0c1c0317U, 0x8101cf10423d60dU, 0xdf1714f7eb16ec0bU, - 0x8ac61881eb44d4d0U, 0xc236640d3dce0e1dU, 0x2221fa184b374621U, 0xc4d4dd5c1f00290cU, - 0x57d5d9e8ff361902U, 0xedaa3c81c9e37092U, 0xf5cef6f80acede07U, 0xf5feee2828e8ce33U, - 0xc80a3a0ee10e331aU, 0x913f18daf9f3fa0cU, 0x1538906033ed816dU, 0x2dfaf78b12ec3403U, - 0xf38c6816881dfa8U, 0x36efd1b803533171U, 0xde639fc804f6b81fU, 0x5f0e130bf602534eU, - 0x15f7ffb1c61252dU, 0x16d1239ecc3c0221U, 0x281d432209c8ecd7U, 0xb209f5f1f522c5e2U, - 0xee07fe5514facbf5U, 0x21010a3581670b32U, 0x1e121e152bfc5e98U, 0xb23ee00faddecU, - 0xfdf00edfd92024dcU, 0xf641da05e8f5dde8U, 0xdbd63844e22c2025U, 0xe2ec1a426505352eU, - 0xc80e0f1cfbec7b81U, 0xf3ed20e819391c04U, 0x14fb17dad80103e0U, 0x7f68002a30efbcccU, - 0xe45ad6c7a2c49636U, 0xfeffdee7edbad908U, 0xe02d3f2309070669U, 0xe9ed00e8e5e5fd0eU, - 0xbfe8cbd10a27d3eaU, 0xa4ca5e3e85cffadU, 0x14f11c08192c1414U, 0xb5ecfbebfdd6cf11U, - 0xea24bc7f14f8d12bU, 0x130ecf50ebd4150fU, 0xa11358a8ad134381U, 0x3ad5eef6add7c60dU, - 0x6cc5cc06d2d10167U, 0x3611e2f85233e825U, 0xf1c5267f9b0f153aU, 0xd43fef3c3391f3edU, - 0xf4ec3f0fd0faca03U, 0x60e2e0c39006e3ccU, 0xbe27efe502dce8e0U, 0xed2d3afde0c835c9U, - 0x314ee8024e133ce9U, 0xf3001e20f1e20242U, 0x4c1ed209f4ecf9eaU, 0x81f31ac8bbad63fcU, - 0xda080df90d22e1dbU, 0xd523ee2529f07f09U, 0xec1b0cd743f0361fU, 0xf8482b360319010dU, - 0xde204faf2e324ffU, 0x9fe1956815bdf11U, 0xf4fa1ea9e6f223f6U, 0xc1ec1ef7010dbc0eU, - 0x29d6ac1df9cc1304U, 0xc72f00e8244719ecU, 0x6d807120121e9f1U, 0x81b20ed1fddc19f4U, - 0xaf2d9f7ac27d531U, 0xefba1b03d74902f9U, 0x200a070ebd03fb24U, 0x1d2a13bf26c5123dU, - 0xc625d210e5fb3712U, 0x502a41a310294117U, 0xc432f71ff0c35eccU, 0xda21d77f08f31b07U, - 0x2222234581296115U, 0x2c163c324bd619e7U, 0x3d0824091719d90aU, 0xfa04fbc7b407c8e0U, - 0xf10bfaea1aeec2f8U, 0x7749ec53c436d8f0U, 0xe98121ff5af1fbc7U, 0x31f31002ec05d9e7U, - 0xd904ecef02d0f8f0U, 0xde53bc19e5ec0528U, 0xab29f5b258edd23eU, 0x94bfe0d04b8000dU, - 0xf1450aff3b0c54e4U, 0xae677f3c0526ae39U, 0x4d910cd0ff23408U, 0xcdc0b9dc59bcd552U, - 0xb59ae3d11b9eb5aU, 0xf22625a2329400fU, 0x85352ac0bc810649U, 0x10b8332cd7051eb0U, - 0x8881eaf4def2000cU, 0xd43ead24fee6d3f3U, 0x9e929330121d61fU, 0xd9ea05e2fa041dffU, - 0xaee6f904fa1417ceU, 0x7fafdaf7e7e44416U, 0xd6d06e1ecb01b662U, 0xbc0727f1b60fc45eU, - 0xed750ddfd2f76ad7U, 0x569e689fff3535b3U, 0x816da54d31a280eU, 0xe92c7fb802e051aaU, - 0xbeadd3012f1132eU, 0xe7ea131f01d5ead2U, 0xe821f805f9ee110bU, 0x1ec3c6e924eb481cU, - 0x3de81df0a047e303U, 0xa4f17f33da0dd24cU, 0x6fde307bc1e0a31U, 0xf9052237dcff1311U, - 0xdbdc19d5102dd41bU, 0x3bcab00d9dfaf3eeU, 0xc20d7fad1abab89eU, 0x2ad0b0ddde131b22U, - 0x10e1c14d720bdebU, 0xee03e60d7f0104e6U, 0x4ae5ef15f0fb31f8U, 0xde02d405ecfb291cU, - 0x31e5ea0ed5c517cfU, 0xc81d0ed8f80c17fdU, 0xedde02fe9ae13616U, 0x6d50223c611e3eeU, - 0xb3f545abb77ffd39U, 0x480ce6e7fcf91a1eU, 0xfde5061a362ed8dcU, 0x9fa9b1fd45cb033aU, - 0xe290207aadb16dbU, 0xcf2937dd3bea7fbcU, 0x6ee221e1bf90929U, 0xff2a04f203fd0df6U, - 0xf6215703befb05e4U, 0xf82bd9d5dd2a0d18U, 0x2b2043fedd1b013fU, 0x34e5fb0a14e8ecdfU, - 0x81c83ac9c0e73ae2U, 0x92e21cac7ea0d08U, 0xcbbe18251ab8e5feU, 0xf000f0e5c2121ff9U, - 0xf1244041e47f29e3U, 0x36d4092ee9c602faU, 0x140908d4ffee1116U, 0x1263041f08ca8160U, - 0xf4e90243f23026fbU, 0xffa0feaee08ff10U, 0xfb1bedf90f0108e2U, 0x290318f5e82c1753U, - 0x7f4bec04012c6108U, 0x5b17e7c61d0756edU, 0xe4e11923dfdbc5d2U, 0xfb10f61e292330U, - 0x3614fc22f3fb18fcU, 0x16057fe90eed25aaU, 0x1cfbfe17f00e061aU, 0x21ed1d08ff1cf4e5U, - 0x230efc0cf00ef824U, 0x1f0205fed7111d12U, 0x5a33f713f62432f5U, 0xe4ecd3104def7f4dU, - 0xfcfc100917da1600U, 0xb03fd0007ec0afaU, 0x3a7f24e9f115c80aU, 0x1fc34a3fedbf803U, - 0x5106a7232210c4cdU, 0x221613301d01cdb6U, 0x28000a1dd90ff8daU, 0xf0ad61eecf8e7U, - 0x240ad5624abbde7fU, 0xceeb0f04d7396e04U, 0x2cc4feb2fae717eaU, 0x7e71800fe07c7e3U, - 0xf4f4e41af6ff1708U, 0x29f40914e10f07e3U, 0xe40b0bd9fa09cd1aU, 0x7fd6fcfdf703fd01U, - 0x1bd732a9ef0d47adU, 0x63eff7b5eaf5d030U, 0x6ef0e025ed743709U, 0xda2b0b813a4671b4U, - 0x13061e05eb1dfd34U, 0x3e1bfeff022a303aU, 0xd61a2c29e79929b1U, 0x72477fd5c93362d1U, - 0x582ec38f3c53a41cU, 0x38ed665c048903f6U, 0x9bfde11031513116U, 0x3ae71415e21ef0d4U, - 0xfdf47fcbb9c5b323U, 0xc4f0d84413aaf5adU, 0xf7cadbd23312450aU, 0xe42eefeb1e0bdc12U, - 0x1802dd7c810f2911U, 0xf108ea0217f34cdaU, 0xdbe5f43c0407febcU, 0x55cfef0be3e50700U, - 0x845d4e1fbfce8ecU, 0xde12e6e243cbde08U, 0xede2131725f37fb6U, 0xd9dfd03a040bdbU, - 0x3c2187b9d7170a42U, 0xfe33db1803f519ffU, 0x364f012d1dec16b5U, 0x7f02031ac82603eaU, - 0xb02069eaebef3f1dU, 0xf50ae2080be108d3U, 0xae1af846e5d3163aU, 0xc2565aca19bab7eaU, - 0xffc84fc114afdb11U, 0xe4391d0b4ddbf213U, 0x1910fe111ee4f581U, 0xeacf2c14f60b0001U, - 0x271f811360c61921U, 0xfbd0ff33eb64cd34U, 0x1505d7ecc6d6c49dU, 0xcff90d2b14ccf802U, - 0xc2f4fff4fb11ec20U, 0x1b1901ecee200817U, 0xc40501f41a23d912U, 0xca06d281351fdcf9U, - 0x9265921001ef01dU, 0x1af60f0d02f2f31dU, 0xc4183bbffaec26f5U, 0x2b3798ed39e61200U, - 0xfa19e2af721e7f08U, 0xdb9fd1afcbdff88U, 0xa2ff16fd0c0d330cU, 0xcce00c0e2ed7ef00U, - 0xf2ffd4f3310230f2U, 0xea350a855e497fb0U, 0x580b102e1b060cfbU, 0xb0a15051f2407f3U, - 0x57323bffe02dd8f2U, 0xede102c6dbfa03c7U, 0xd53a18bf51307fcaU, 0x1ab02d6bfacbc997U, - 0xfacef0ddf5fc3017U, 0xfa02f4fff31d0cefU, 0x1c7f16f5e74cc007U, 0xeedbca4734e91f0aU, - 0xd50ce4d74a0be410U, 0xdf12e0f21407e00eU, 0x130e03f7ecd72906U, 0xf4002f28f2a5c4f4U, - 0xf5bbbeb6df8114U, 0xcc251e31c67528a5U, 0x28c611dd04c5eb0cU, 0x3a2bd6bd13b8c3ecU, - 0x2214eb0b1d81e61aU, 0xe3fae929c51744efU, 0x11dfedf503031e03U, 0xdbfe00fbfc0c0e21U, - 0xd0b436ff2d44effcU, 0x7fcafc500e33e243U, 0xcbf1c315f610f53aU, 0x140326dbe1d6ffcbU, - 0x6e0330aedeacc0dU, 0xf9680023021bfe34U, 0xa61bd338e611da16U, 0xd4f8fd96003118a9U, - 0x500a2ff4e5ed1919U, 0x7fee0647d08a6b18U, 0x90ff83cf9fffd14U, 0xaacee281c1e116f0U, - 0xbafdf128f4dd2046U, 0xee9f7221d063e47U, 0x221005feeff81d00U, 0xd9e238dd30cdf527U, - 0xe22da42c08a2f3dU, 0x1b0f4c45ff135342U, 0xce3852f824dfe76bU, 0x7f8b4e83da90c055U, - 0xcdcf23af0da8240cU, 0x10e17f0ffde20400U, 0xf114656adf16dc5aU, 0xcd44d3e4f028e5d6U, - 0xfcd52602f6e5f01eU, 0x15141b09d23e1effU, 0x158126304eaf0613U, 0x1e0113c9e143e916U, - 0x17e91d03d2ece5f1U, 0xdc2aedf9faffdadfU, 0xe2125c9f3b11c3faU, 0x30f81ef2b89c3e8U, - 0x3d1dacc83910ebaaU, 0xe0200b5e5413fcdcU, 0x1dcf2911e7142049U, 0x512926fabb541e0bU, - 0x73910f11d10df7fU, 0xc9f1ea0ec507e71dU, 0x1328fcbd220cffd4U, 0xeadc0b48eb48f6ebU, - 0xccb6086fd4ea4713U, 0x33813a607cb420f2U, 0x5102242cc311c7e4U, 0x4dfefacfb9e626f0U, - 0xf53a0ce9faf0e9caU, 0xd3e2c0ce76b1173dU, 0xf0f1f2cce92c0af4U, 0x520c0705ccf8f12dU, - 0x85ca06f8c312e21bU, 0x158d106504a81eaU, 0x29f92b40dff739ffU, 0x3c207fe427ff36a8U, - 0x1202051dc6d7d5f6U, 0x15110c02050ffee9U, 0xa3ef12f31b0cf514U, 0xcefc040d81fa2208U, - 0xdf1c00d5b52484e7U, 0xecf94def55e71ec3U, 0x2900d9f405fb24ecU, 0xc0530c10191fecdcU, - 0xaaee16cf1fd8e610U, 0x137fb90cff0725f7U, 0x30fb1b4aeb0e1124U, 0x9b2e1e0ee801f945U, - 0xd2ebcd18f8d21903U, 0x20e10f29d9075102U, 0x4e107fd00ced38a2U, 0x350be237fee000f2U, - 0xf8240efc0d30efdaU, 0x58f21811f9c6d901U, 0xd8e916ef8113415aU, 0xb60a963bd50535fdU, - 0xf3074714ad04ede9U, 0xbb12011bfd19c815U, 0xa3b92c3e03fee738U, 0x81bd1de2e4331f26U, - 0xf80900ac02f025f1U, 0x36e7dd1901ffbe16U, 0xf5091f17f40900fdU, 0xf01e0ff42018f2d3U, - 0x5ae9e519eec5f1f8U, 0xcb7f5ed5a9e3b6c7U, 0xf2172452381813e4U, 0xe940e2e41e1cfb09U, - 0x45c909daebe80526U, 0x4b3836e50afbd030U, 0x27d3e7fae3c0eee8U, 0x7ff31e5aeef2ed26U, - 0x20ecfeedc106f45fU, 0x2be506f405fe24edU, 0xb7260a8137a7c10fU, 0x62faeb9bf487e4c4U, - 0x343003dc2df0e6baU, 0x100e133705bec02bU, 0x1e09192f0c0b1fe4U, 0x2730f8db21d6cd12U, - 0xe081e61d142db450U, 0xfddb0d2ec92303e1U, 0x1913dfdaec05e931U, 0xde51bf6f943ca0bU, - 0xd33184e814a15ddU, 0xf8e22f9f2fa40ec8U, 0x5217e9ec2ffbd721U, 0xc4ece61fecbcbda9U, - 0x1e29edef441728f5U, 0xe7fce6161815eb04U, 0xce3a08f704e92416U, 0xe5091af2070813fdU, - 0x2fdea102f3fe07d6U, 0x7fd43196f02cf0bfU, 0xe6e4f3d40f25de00U, 0x7f2da5e7fcece8beU, - 0xde1510ecfe23ddcfU, 0xd6190cf8dc03ea14U, 0xe706e9ed08170301U, 0xc20b200f44f5ec08U, - 0xff0ace2c12cdee15U, 0x2d0813310ef5f820U, 0x877f14150bf3d20bU, 0xcfcefbcedccf3ce3U, - 0xc7f62dfe7fc7e6f5U, 0x4101ed2126b7fc04U, 0xf31f2fce0bfd1a07U, 0x43e0e0f2f3ee08f5U, - 0xe7f21cc1e8070ad5U, 0x14eb0b57983e0e28U, 0x84fb8132ec733dc4U, 0x1de0e8e4e74931afU, - 0xfcf0af4db39e831U, 0xed01e724fa42f71dU, 0xf2f1e6ccf00407eaU, 0x1a46458185d6d4e8U, - 0xd5fc07c3391f04eeU, 0x6ee8190ecef2d013U, 0x1eece8fb12eb0509U, 0x67f60f7aa377c2edU, - 0xf0d9fa1b05e6382fU, 0xce0b4614cb33eeb8U, 0xb0eb201e10c5f781U, 0xd92abf2d3630a52eU, - 0xdd8ebde9f9e70233U, 0x811f2198e9b8bf05U, 0x1806bdde0c0c9df5U, 0xd72e7b4733f944ebU, - 0xf21919440a2a740dU, 0x81cbf6b909ecf506U, 0xfe002401162f281aU, 0x26f70c230de8dd2eU, - 0x110f0f0c0000f4U, 0xd0eefdfc131ad7edU, 0xf129c49663952a27U, 0xd7cdc321ce6b8168U, - 0x1af94dc30527ebf4U, 0xc91e0c4b31f1e305U, 0xf3ef33cb042724dcU, 0x30426692598162e7U, - 0x17d01e8a071ab9f7U, 0xbe7180a20fd30e0U, 0xc058bdf0e6c3e7baU, 0x4230e57304030e1aU, - 0x180c40fa837fefc6U, 0x9ef2805eff02987U, 0x1a07292bfff925d7U, 0xb7dbece9db13d0c0U, - 0x595ccf1a1a1cef0dU, 0xfc22cd98aea393bU, 0x893fa61462ea569U, 0x8cd57fc59b270248U, - 0x590f12d5cd426545U, 0x5dc92bdb012c47b2U, 0xe2eceb0f2cf5f027U, 0x1226e61659c60410U, - 0xd05e7f8fb05031bU, 0x815e351bf4e9af18U, 0xf401ddfeeafe1cU, 0xf3580e0d2dbe2dc9U, - 0xb19e5ae5e2aaba26U, 0x1412eb0e1d3d2df1U, 0xcd001313001181fbU, 0x1be32a18fff4f635U, - 0xdbef2a1bf3f507e6U, 0x2ffcd814eb20d318U, 0x5d3032ebf10319deU, 0x8146f1efcf14a3f4U, - 0xef20e4251d12aaecU, 0x96b5a5ee5bd201e7U, 0x4c2141cc1e93e997U, 0x950f7f519bfdea56U, - 0x18b81afdaeb8c81dU, 0x3cf807e10122030aU, 0xf4cd01e40dedc522U, 0x13624bc289e6e26fU, - 0x47f0e1239a211768U, 0x7fe108081ebf1fbaU, 0x188c4d93e10a4783U, 0x37d1da28dd2258e0U, - 0x57f40a5a3372d25cU, 0xe01e7b60fca6b8a4U, 0x1738eaf5014ee93eU, 0x11fd2511a48c577fU, - 0x4b3115977fb74122U, 0x75d30a1b1b10fc35U, 0xd40b14f0ede83cd6U, 0x5bd4c5f3f719330dU, - 0x1420ee13de0203e8U, 0x18101020200606ecU, 0x244003d706ce4ecaU, 0x411581dd23d4e21eU, - 0xf6374e25e826e1ebU, 0x40f51216f3d5f5e4U, 0xd4e4120302db02c6U, 0xdf13b40dcf79001eU, - 0x4afd2f19d0eef0eeU, 0xb5e7f8df22540014U, 0x811df82d1eddbf39U, 0xe00d0bd9e67fc111U, - 0xd0dbe0fedc43ead1U, 0x1fdece8131465afU, 0x14d52a2a07ce229cU, 0xdffef9070a140c0fU, - 0x2033cf2381330410U, 0xd2bcbc01d4fd0ac5U, 0x90f91c30246568caU, 0x2b4b617010df415U, - 0x713934b80c2cd0aaU, 0x13c521f49b503b41U, 0x81ff971bbf164ad9U, 0x21eada9528f004a6U, - 0xeec4382100ed45dcU, 0xffca07160be82622U, 0xc03d7ce45e4f62aU, 0xeae6cd3cdc1219eeU, - 0x13ff2a462de845c3U, 0xab2b04cd21f611cfU, 0xe04ed17f2bc3b878U, 0xffffeca1fffff2a8U, - 0x63f000020c8U, 0xfffff196ffffff05U, 0xffffe008ffffdccbU, 0xffffeaa500000a49U, - 0x3f6fffffd2fU, 0x133ffffaa46U, 0xffffeb07fffffac5U, 0x2b2fffffd40U, - 0xfffffbab00000580U, 0x9a1fffffffcU, 0xfffffabfffffebe2U, 0xffffde7100001c84U, - 0xffffed4a000000feU, 0xffffea2000000114U, 0xffffefc0000015ddU, 0xfffff5cf00000fa7U, - 0xffffd7bd00000a60U, 0xffffe40fffffcedaU, 0xffffe790fffff15dU, 0xfffff68affffde3fU, - 0x1afffffea14U, 0xfffffd6bfffff1e5U, 0xffffd57fffffdbbdU, 0x6c6ffffcaccU, - 0xcb4ffffd5b4U, 0x18bbfffff9adU, 0xffffec02fffff1c8U, 0x182cffffc795U, - 0xffffefd9ffffe447U, 0xffffe29effffeaf1U, 0xfffff72200000099U, 0xffffe5ffffffe58bU, - 0xffffe905ffffdca1U, 0xffffd5a7000004cdU, 0xfffff33b00001127U, 0xa0fffffd35cU, - 0xcb4ffffde1cU, 0xffffdfcbffffe33aU, 0xffffcb7efffff940U, 0xffffd61700000a74U, - 0xffffeed4000006b4U, 0xffffeca5fffff9adU, 0xffffbedcfffffb4bU, 0xffffd8fd00002006U, - 0x19a3ffffec43U, 0xf2f00002a48U, 0xfffff578fffffb13U, 0xffffe286ffffcc8eU, - 0xffffb71800000db5U, 0x1080fffff853U, 0xffffe96c0000008dU, 0x32e00000211U, - 0x5300000cb9U, 0x417687fd7f7fdcb0U, 0x8181ef40240d7f85U, 0xe8a944817f237f3dU, - 0x7ffb7fb7f5b77f31U, 0xdba4c6437e98b318U, 0x81ca7f5081708181U, 0xcd9f939d0547e87fU, - 0xf5c8b3812fc17f5eU, 0x5057f6042102f85U, 0x5b816455810178d6U, 0x7f817f7fb5a67640U, - 0xc767f3981e137caU, 0xf165c97ff9aad27fU, 0x14db9b044b85a52U, 0x7fee6cf5e17f0cb7U, - 0xe7513949c4dbfa0fU, 0x9de24a3181810ab0U, 0x542f81c10c342393U, 0xfa7b87ced1ae9dd4U, - 0x2909cd08ac9c4ffdU, 0x5581f9e18981deddU, 0x7f434ebcfa81ea8bU, 0xaf810a3c500ae5acU, - 0xc3f139f37f816425U, 0x781355005af4e53U, 0xb3100c45111d2fb7U, 0x32c6db6ac6c1985aU, - 0x9b1d7f03bf34daecU, 0xe9fbe9f275c72d37U, 0x8fcec4dd85e04022U, 0xeedaf797040a2c21U, - 0x2e1a81c2d97feb8fU, 0xc6051c8a477fdd12U, 0x81af1d7f187fce0eU, 0x548f4ed57dd5c081U, - 0x7f46aaf10f4f7fc9U, 0x988560522a0c844U, 0xfae423fa33223881U, 0x9d1f08133a52150U, - 0xc6810f055ad2e9a5U, 0xec2f813235189c7fU, 0x4f91e77f81cb5a7fU, 0xd0d9d8430f16ca14U, - 0x7f54431eeb60810bU, 0x81764cd2cabfe924U, 0x75b17437f3bbe7fU, 0xe77cfd062d7f1481U, - 0x5644a0a69ac67f76U, 0x82c057837ff77f18U, 0x49e8ae05573f437fU, 0x474063ddbfb274f0U, - 0x1fabe7f6d2dd0bd1U, 0xf8d8c4f126e20155U, 0x187f814feaee33a7U, 0xcc88fce8255a817fU, - 0xa6981815a81e51fU, 0x7f4eb2786381ce7fU, 0xae7fe07f4e7f7e81U, 0x277f0b3ae64f737fU, - 0xf24408e4fa0b593eU, 0xb514705d81517f1dU, 0x3c00082c7f5499ebU, 0xfc7f6dfe8a816a81U, - 0xf8b37f8121538181U, 0xec21eba77f7f7f6cU, 0x7f7fa56e09938181U, 0x81767f91817f8197U, - 0x7f2e86a6U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x6db12d300000000U, 0x1a3ec105f10733d8U, - 0x29f8ff8fedcb02fcU, 0xfde8031ea8d45fafU, 0x23e54233ff1bcb4fU, 0xf5e70f0bec8e1908U, - 0x14091ed3300189e9U, 0x41e4e4fc67582714U, 0x16f1e3cfd62af347U, 0xf9171d3aa6de2bf9U, - 0x6742c417fa0eb333U, 0xfc4c4232d50da636U, 0x1afd282be6fe26ccU, 0xadf5e7ec7f242dcbU, - 0x1a1e59e31ded642eU, 0xc4a3f1f6fef4da21U, 0x11f6561bfdde4cadU, 0xd1c5f817fdb02bf4U, - 0xc5e3dc0bfd17dff2U, 0x603bb13129eb1942U, 0x270f4633ff00ea17U, 0xe8f5f52ec481c306U, - 0xf1f11e25dc140f78U, 0xd90b100f03dce7efU, 0xd00ab8c9f1cf131eU, 0x27e47a01f61b1f38U, - 0xf470450d1e0f09eeU, 0x50a1cd8fa06ff3fU, 0xef76fa15ecd4cee5U, 0xb9c3f11c2f46bbfeU, - 0x8c0be0c9afcf4003U, 0x47052ecef1f5e7e0U, 0xf044fefa9981fbe7U, 0x1b04661ac6d52344U, - 0x71b7b8f344e51ac9U, 0x6030e0e23f1d42dU, 0x3a0dee02f7e40fe9U, 0xcaf2abe427f8f002U, - 0xc75241e2381cfe08U, 0xe6005122050d8cfeU, 0xf676c302cdfa1abdU, 0xcdd6da2105f7682aU, - 0x2efc4801f307ec2dU, 0x2b3009f9d0f043d3U, 0xd50e28cbfa3fc05aU, 0x16c5011adfb92f2cU, - 0x60eec5e5fb812a43U, 0x24ce01be2c000d96U, 0xefe7b23a40f1f11cU, 0xe3c4f71c42e9ceeaU, - 0xf70f341ddf2f5210U, 0xd7120af4cf1bd2efU, 0xaf5f2e035e42cf9U, 0x4efa18b6fd0459ffU, - 0xffa8152ad8b1dfdbU, 0x727dbf90ec808eaU, 0xaf202fe8dcfc35f7U, 0x4010fe21ee310708U, - 0xefc22f03f6dcd7feU, 0xdd2cf60ddc1d0a21U, 0xf7b7e32a49338b02U, 0xefdfd9101f1ffb36U, - 0xdffe1dffc808f01fU, 0x3dfefcd1dddaecd9U, 0x7c3f6dec51ef2f5U, 0xf37fdb12d909ced2U, - 0x2804f0ff2bc51d11U, 0xecfb15f30a1205d5U, 0x392460dc00d955d5U, 0x5f9c0001ed82205U, - 0xdcdb3749f5b02d09U, 0xf6082dec03dfe9faU, 0xe3120cea0e2ec8f3U, 0x2a23f00708d60d0eU, - 0x1d0d2a46bdf4e306U, 0xe4f70f3ab208c444U, 0xc604f80e040b1e32U, 0xede1307f1cf9eb02U, - 0xff1ceff9e4ce0d0cU, 0xe4e81c3b1d225339U, 0xc91d631606ffd5fcU, 0x19ac26d4f7ec412fU, - 0x3704201631e31d13U, 0xfd0e4103eb034605U, 0x1c0d8b0908d412deU, 0x10bf0d282421ff26U, - 0x18f02f16133c1a00U, 0x16b801f3fe31d302U, 0x30b1672b3cf501d2U, 0xcfd8bee28b50c41fU, - 0xf90edd0ccae11806U, 0xedd29e7f085b060dU, 0xdd0d03fc300df9caU, 0x19050403e56619e0U, - 0x5e918ce0bcc1614U, 0xfde5f112cbf32c0cU, 0xf501120a192f1614U, 0xea1a1cf026e921feU, - 0x110b32c31122e25cU, 0x1e572526de462dddU, 0x250ed5c50de6480fU, 0xc6f1fae7feefe6c9U, - 0xfc17451ff40d35efU, 0xc424edd8eeeffbf5U, 0x17f4f7d6be7f55f4U, 0xf5032d1f1bc4efefU, - 0x1724e4e114d8d7e8U, 0x38c6edfe13fbe2d4U, 0x10cbd020fdf5f8e6U, 0x1a191424eaeb2a08U, - 0x1134fef7dab00216U, 0x2112290c84aaadfcU, 0xe2e9dced283767d8U, 0x22123bf94b3a130bU, - 0x4ec98effd3ffba4U, 0x1d57dedcbaeb3429U, 0xdcfa080d8124242bU, 0xff1cf3d9ace52108U, - 0xda110ddb06eb0d3cU, 0xdad52341e8bddb05U, 0xe2f803d815200405U, 0xdeb054620f02712U, - 0xef08f21611fa0a4cU, 0xd32e01f8a408dbf4U, 0xf6fec1161aeeeae8U, 0xef31cb16cf17fae6U, - 0x20f31fec3feaf406U, 0xec81f3f90528e4bfU, 0xd7ead32c3bf7e7c3U, 0x41be3531d61afb0bU, - 0x17ab071bf5f32515U, 0xe9f9e5042109e713U, 0x118a8f2cc23fd04U, 0xc22cb4e01e241923U, - 0x3e0dcd3df1000cedU, 0x3f153b17bef81b65U, 0x945da25e7ef38f2U, 0x8efe0cfbba7f5e7U, - 0x18ef2de5ecfa52eaU, 0x33c120f01df6a1ecU, 0x332df445a1f005e1U, 0xbf205bd3b37bf3aU, - 0xf9c0d8e527150031U, 0xad41e7593759a26cU, 0x3209101408ddc415U, 0x3b0bfed9bcf18d12U, - 0xc67fedecd173a2cbU, 0x909f9d4133c19ebU, 0x80008d60f48f720U, 0xadf1e96a47f8215eU, - 0xfdd1070002553d28U, 0x25463abd2fe763f9U, 0xdd253bd0a2bb0b24U, 0x40bb0dc5ee11212aU, - 0x21ea14fcd08134eeU, 0x11055ec3c4f438c5U, 0x20b3dba28db27c2U, 0xecc7bc486371ca2cU, - 0xb1e0123dfed6cb9U, 0xd0bebd1ed0e60dc5U, 0xc3f829e61c48dad2U, 0x7ab4e4dc03fc3b11U, - 0xd2d0ddb1e4b3ffe3U, 0xa32a22073320d9ffU, 0xb91dc3ed7f080c0bU, 0x90be25c26ba00cdU, - 0xc006e5962bc4fcfcU, 0xf3e5fdc04810fcdbU, 0x90f27d8c7ccfabaU, 0xec753111292b06b6U, - 0x27ca071be8d657d6U, 0x174edc11cf0f1705U, 0x29e61be12a0b0422U, 0x46d8442214181c01U, - 0x25fe04142896f6e2U, 0x9ae427faba6808ccU, 0x1debfcea05faf60cU, 0xfa252c0481ee2b07U, - 0x2cfb112cf40afbfeU, 0xeb070df40af2d00fU, 0xf7a31d0fe7f34ffdU, 0xdfc18e7f5955441U, - 0x4ae217f718f7f993U, 0x17d1ee101005dac8U, 0xf9d1f90de4d3d11bU, 0xcd32d6b7212e3df1U, - 0xeb1bcb19fa31a8cfU, 0xf705ceed36ec02eeU, 0x6330ff200c0341ebU, 0x11adfae1ca13d7f3U, - 0x3abcc6e23decd506U, 0xd3157ff1f1b11200U, 0xd0cff143fa25ff59U, 0xf90de9123bf3f419U, - 0xb7f6ecd1f929f8d6U, 0x5ae1e7e61dbcb1adU, 0xd6d8f24c1a15ff32U, 0xf8c91508a9ea2963U, - 0x192df7589cb8204bU, 0x2900cd02017bc105U, 0xf41c2319f126a5c9U, 0x8072806f30435b4U, - 0x5811fd08ab0bfaf8U, 0x48c80bafc7efefd2U, 0x531d37052315b9c2U, 0x12a103fd1569e7a2U, - 0x1e0ac22d4025b7ceU, 0xa949f52e2eebf6b9U, 0xdc761a5801cb2de8U, 0x5a38d2b93ef1e9c3U, - 0xe2f9b60bb6d81bf3U, 0xd2be09b4c08c8cfbU, 0xee44150d327fd824U, 0x19f70be6eb29f549U, - 0xdb18f402033b1721U, 0x451aff0d270e0efbU, 0xfb812f08dd46bf20U, 0x35610c1ad402f4fcU, - 0x1ee40a9ff3e11100U, 0x6af17e9d51142daU, 0x30b0b02e3e6ece2U, 0x2f431358daca1003U, - 0xe503f853ea489cf1U, 0x5cc2d2e0bc670505U, 0xcd493adb1361d11fU, 0x17f70805d4dcfcf0U, - 0x1aee11a4f4100103U, 0xe1185026eedeb1faU, 0xd01031fb8e51cd9U, 0xee65ee34e0f1427U, - 0xecf8f30de40e16U, 0xe630f7ff81383b0cU, 0x3e0f12ffadbcef6U, 0xd0604f0f9f1f5U, - 0xe2ee1ff519c00f0aU, 0xffe618f80021e9dfU, 0xfc29f71a1dfa1ac3U, 0xfcfd2e0101e5f2U, - 0xdec0c03fafb0813U, 0xdf1412180ee51712U, 0xf807f90af72ddbecU, 0xbf0ad5faf10232f1U, - 0x3b0af9ff140421f4U, 0x509b3523e527d603U, 0xeb42f6e101f7eea8U, 0x2201abee4c420fbU, - 0xfdc70ddc991a66c2U, 0x2ecc1d13f5e4e222U, 0x322d0d07b3f3e502U, 0x140406f11e08ad26U, - 0xfea4e9fb2846fcfeU, 0xc874f833187fd542U, 0x481a16c6e4e32ad3U, 0xbf5dcf6cff29e13U, - 0xc93df41df430d1ffU, 0xf709040bcce013f8U, 0xcce606ef0236282dU, 0xc0ed50cee95c504U, - 0x7ffc0905db2a1ceaU, 0x2aed0048db1fc5ffU, 0x19c2f5fde5c4e505U, 0x152c20d70710dadbU, - 0xece003f4d6f0e7efU, 0x1c0fe2de33e900eeU, 0xfe05202fe8410520U, 0xe0fdea0d1df0e210U, - 0x83c02f706ff0a1cU, 0x111bf9f208ea1ecaU, 0x1ac2fffc08131c26U, 0xfb3ff3ef2ffee309U, - 0xfcea46e9c7fbfd1bU, 0xf911d10f13fdd405U, 0x7003ee03ef18f8ffU, 0xfb3aff2c5429c4f7U, - 0xef1bdec7ef1c24d9U, 0x14001500d75207e5U, 0x31160c260bbe810eU, 0xe0141d040f33cdcfU, - 0x2daff3282307bddfU, 0xcd084fd306f02b0fU, 0xfbd51aee0d00ee0dU, 0xf7f9e2b11e172cfeU, - 0x1501e3e30b08cac5U, 0xeafc251027ebc70fU, 0xecd8d120b3272b19U, 0xf933ddfc13edc0fdU, - 0x391725dcf820ddf3U, 0xe3fa44d4f504e6fbU, 0xfbbe06fc9b014cbdU, 0xa4a7f0284ac6d40aU, - 0x23e3e9023a02011cU, 0x4b053eaa0016d727U, 0xdd491df81de52e01U, 0x50e12cd10ef0f554U, - 0xd7f507ea4c0ddd19U, 0x44c0b72621812413U, 0x71b232d0cf6e02eU, 0x277fed21bde60917U, - 0xd6dbcf14fe1bdbdeU, 0xff12cdf599d70804U, 0xe80702fe2b175885U, 0xd54f17d4da350704U, - 0x13c80ee40eb2f00eU, 0x519fddeedd817ffU, 0xf251dc05f78d2913U, 0x572ddccee1a707f6U, - 0xc20427f5d590d5f5U, 0xdf3bdef427c60025U, 0xe1201bd1d10e1b5fU, 0xb1fe0c26f420050dU, - 0xcee217cd45cd0f74U, 0x2b0b15abb281e3b2U, 0x460c26fff1df11e7U, 0x25c6f11412480dcdU, - 0x2c392a3f1506dce7U, 0xbc31251011d8dc06U, 0xf004f71144c2fcfdU, 0x35fbf5cd2aeef80cU, - 0xd000fd24bde9120fU, 0xe2e4f2d0e3ede828U, 0x13f0c11d4211746U, 0x16ef13d113fb0a1bU, - 0xa180ae628e81524U, 0xcffbd33010f7c7f6U, 0xe0ee4087c4f23512U, 0xe63bfa372edc0118U, - 0x3faade27ee33f3ffU, 0xbe38fa3f1f2f3a27U, 0xcffbfde781ce40faU, 0xd16f7dd8820a1fc6U, - 0x4de63e28eedfd142U, 0xe5d10350113a18acU, 0x23ddc52cfcf1e796U, 0xb76639d0b9063af9U, - 0xdc9b3d9950bc12e7U, 0xcf20fd0e39ec2406U, 0x1109de3cdbe2d39aU, 0xdfcf0c1f11e0a0e4U, - 0xfbe9efe6e1e6100dU, 0xd91a41f7da081d03U, 0xa015bfaddebe726U, 0x240822eea735b81fU, - 0xfdcaf11c1aac3f12U, 0xc29504d726abc129U, 0x7fcffd09d70450fbU, 0x26e1a00403e2d510U, - 0x1ab4acc1bdce8dbU, 0x16361a5009f0371bU, 0xc26f11fc031cfd7U, 0x9cd3b6f3172867f0U, - 0x3b40d7d614fe620bU, 0x1c0908a9f4e6f1cdU, 0x3001c70a3020e9fbU, 0x1ee2151303d90000U, - 0xb7f9f2efd1e56558U, 0x156aef04fef6d206U, 0xa624e1d1f2010618U, 0xee0807e01e0d2137U, - 0xd9e9531804123c18U, 0xf105919e210ecebU, 0x3060e3091335100bU, 0xf3b6cad7f3f30cd4U, - 0xd0e0843335f1200U, 0x42e39c41d20d3U, 0xdff3710d8d20781U, 0xd27f920210ef141eU, - 0x4909e4fee6fa07d7U, 0x3de5010b0205c605U, 0x2df1748e6092fe8U, 0xf35eeeef4ae4f3feU, - 0xdbe2110c233844d2U, 0x282ae0f4e1021be5U, 0xe4f50a3f2530fc1fU, 0x1085fe451ae1fff9U, - 0x8eaee010d11e424U, 0x53ed000bd622190aU, 0x1028e81f0c37f21aU, 0x201d33f82a081617U, - 0x1103220cd412c927U, 0xb0f0f12c2a0f0bf6U, 0xf3f6ebed19f6e0fcU, 0x9fce707fefdf327U, - 0x253c071ddb1d201aU, 0xd2cf3404d5e017f6U, 0xe91df2c509f8f32fU, 0xb935f8d718ec1909U, - 0xf9e70c7feae30c1fU, 0x1d0c08ede4150401U, 0xf20cd5d20ef4c4eeU, 0xefe0011303ded9e7U, - 0xe70322e3bd10f4e1U, 0xcc06100a1e0828f8U, 0x64d01ddf9260a26U, 0x43d8dafce9b22504U, - 0xe130e12e714b202U, 0xf51a130912e510e3U, 0x1f2bdb32190fee27U, 0x3e12051911d93e36U, - 0x22c20433fc0ae2bfU, 0x8a1260ffb2dc407U, 0xee15fa01f5e526eeU, 0xda22d5dad81d13f2U, - 0x1ead80bf52ff7feU, 0x852211023810715U, 0x1c1d06d4040ddbU, 0x690212f27ce2f16U, - 0x12f8c7e1dfd3ced8U, 0xd2092181e2e9e907U, 0x18e3211b1017e404U, 0xdbedfa04f6f1e4d7U, - 0xec2cdd17e71a122cU, 0x19f6e435180d06f2U, 0xf9f20feae72fd60eU, 0xeee19f82b22fe2fU, - 0x2acd15e627e520dbU, 0x8e24228fa24f8adU, 0xd013f0fffa210cfeU, 0xfffce3e428f1f4feU, - 0xfdf1fecf31fdf10aU, 0x162ee7a1a7b007ceU, 0x34db070c3bfafec9U, 0x32b4d8d8fb3e01ccU, - 0xf24fd44823f1dbdbU, 0xa02ce52936b8f1caU, 0xf81a142b42ea1ae5U, 0x1b32aefd51edc00bU, - 0xcd02c8ec08e8261bU, 0xe356f78142fc3d12U, 0xec221afcfb60e224U, 0x2d2025bce2fff519U, - 0x2f06fee92731f23bU, 0x3632eb48d6f6a8e8U, 0x387f1e05b3d11f24U, 0x1fb31b03d91c350eU, - 0x2a6e4f05cca51000U, 0xf3b110ffd8e4d6b7U, 0x681ee90830124630U, 0xbe3db22315dcb71cU, - 0x3ecd919a65d7706U, 0xf3ee01eebc2817f6U, 0xfb25f037dc3df13bU, 0x14b9011020d41928U, - 0xd6f430f9e1b8bc15U, 0xcff4fa032a1de81fU, 0xecf73e04b70f41ecU, 0x144d2a0fe20cefdbU, - 0xe3ffee1e7f073aedU, 0x1c0805ff2bf904eaU, 0xb5315f11805490eU, 0xee2e19cad0fdebe2U, - 0x16fe1cb6f3e41d0dU, 0x22e3bb20ffc9011fU, 0x72eaf2ec01f420d4U, 0xd82c1eda21d90b22U, - 0xf4e2dd430833dcfcU, 0x24031223cff70be5U, 0xfff5e2d5f34ee3f0U, 0xd83ad60af8d529d8U, - 0xedb5fae0c5ff1a08U, 0x4f40c3cdfeae0a6U, 0xdf002efbfa45f6f6U, 0xcfb3badbcc4e0f02U, - 0xd109fbee1fc72f12U, 0x37fb02eae6f71e10U, 0x14c2bf17f1c402cdU, 0x24fb20d1d9cc7f21U, - 0x40ad90c3cefe21dU, 0x38050ebb3e2fd0f9U, 0xf4cde22a32fc0a1eU, 0xf7ccea2217daf4fbU, - 0xfce3ff0aecf30e21U, 0x407ff66fd0ec517U, 0xfaefdce81501f712U, 0x7e9e21ab8bd0f09U, - 0x1c001302815edc0eU, 0xe0e9100703c9bdffU, 0xfa4cd3261cc7cfc3U, 0x16da1c12f00bfe0dU, - 0x8e5d610324e22e1U, 0xcbe3fdd227ce1747U, 0x731ad91aeaeafd23U, 0xe4a2f10ec721effeU, - 0xec2505e21ee2e4d8U, 0x341f9edc301511cbU, 0x9712f100433bc904U, 0x37d92e090a021730U, - 0xfb927c4dd5319c0U, 0xbdfa2cfee82edf0bU, 0xe0dcb6f07f05ec07U, 0xc2e80bddfac92233U, - 0xdf28c4053fe7d9e2U, 0xaaea1ea4f9fd0610U, 0xe4d9f505c1ac1cdeU, 0xd2430c030316f439U, - 0xf5e30ebd39e91822U, 0x2932eef6db15e7f0U, 0xd06b53ef3539ed12U, 0x11de1bf23c1e0925U, - 0xc6fee0f0cfd02017U, 0xe61d10212c011401U, 0x202db4ffd5ff1906U, 0x21244c0fc0372a22U, - 0x4cef04d618ab17c3U, 0xe7bb5f18e03e272bU, 0x30d601c2d429cccbU, 0xf5a3daaaf1d306e6U, - 0x61228ca3decf5b9U, 0xca12113c8db05ffU, 0xd0e61ad9578b03cbU, 0x3c0ef612e73d4716U, - 0xd8d73cefd13ab5U, 0x2f81fbe62bf32ee4U, 0x4125e6080101e501U, 0x37f304fcdbc427e1U, - 0x114e116dce3f3fbU, 0x10f302f0103eeb01U, 0x2210292927400500U, 0xd31c050287e61dfeU, - 0xe9dc1819e0110ae2U, 0x1dd808282e128125U, 0xdcee2b36242d49b4U, 0xe1070668d72ee815U, - 0xda1e38dacbf21713U, 0x49ab3bfa062b0be5U, 0x11000a23f610f1f6U, 0x2209cdef01fcddfaU, - 0xecd709e00707ef11U, 0xf4e5135b77d87337U, 0x4500f006329faU, 0x420e9c92ecf520cU, - 0xa90024a3d7978121U, 0x47df25ad06ec115bU, 0x2de9e60ad58861ebU, 0x2db54d24d9d376ebU, - 0x9a38ca2750bc3fd9U, 0xd9e6ce6d784ab0dcU, 0x22510b4feaf12eb6U, 0xe5d7e004e91e3514U, - 0xb7e654f44af5e2dcU, 0x66c0f4d5fbff0afeU, 0x4dee280305b7e5b0U, 0xf80391d5fed6e6d1U, - 0xb80fbbb70a011502U, 0xc0babfcaa0939c8U, 0xffd47b733b059237U, 0x7dbe703c9dd0e23U, - 0xd713d5f1332da33eU, 0x1408fe1e4d29cf2aU, 0xdc390cf9c2f4ac30U, 0x120b4e04e1e1841bU, - 0x4f1ddd1bbbf29d06U, 0xd17f0e28d219bd39U, 0x2b07e103f72305efU, 0xbce2fcfe29bb4205U, - 0x2b129b15eab1e7caU, 0x7f0be500b8300bdfU, 0xe5e9e732db1ec3f7U, 0x37c8e122d4c6e3e3U, - 0x242e18cfdbe6c0f6U, 0xce9dbccbbd2dfcaU, 0xe11c9e425ee010eU, 0xc7cb3851d232e5f4U, - 0xcce5ceeb29ecede5U, 0x393cee021400e13eU, 0xe04d7e0fc1602f6U, 0x1eb7011c28203422U, - 0x163600dffdfff73dU, 0x2d2f5f2de1b3f1fU, 0x3218fdfb9e17f625U, 0x20627eb38e237f3U, - 0x5f4c52600313a08U, 0x6cc4c33fdf9eb1eU, 0xf705de0eeefe0913U, 0xef527e217168126U, - 0x53fe3dfe3216f0ebU, 0x8ff9de5e12ff426U, 0xf9e90a03dfeaf21eU, 0x7e6eefbe80db6fbU, - 0x2f3ac705e726da14U, 0x12011b0622f715f4U, 0xf7c5019b3aef1f06U, 0xe829f8320d17a475U, - 0x22c7e30606e1bbcaU, 0x4352fdc8e79e48f1U, 0xe9c4b1f4dc830c38U, 0xfe84e7c01920209fU, - 0xda8b2b0012818f0bU, 0x4225e1ef3be42d9dU, 0xf027190df5f92724U, 0x1b1ee6332d545dc6U, - 0x4817fdbd16e4daf1U, 0xe8f41ef3113fb765U, 0x42043aeb184cb4d0U, 0xeda391ad16faaf3cU, - 0xf502f1d211ba39c7U, 0x3214cc1f39dc1f15U, 0x17d74a0e0b201302U, 0xb12b700fa1df635U, - 0xb7ec261cd8cdcffeU, 0xdd2df2dcd9170e05U, 0xf8f6ec061bff9332U, 0xe6ce122337e726f9U, - 0xcbef0cfdc309e60fU, 0x1b07cbf6d7270bf0U, 0xbba2810af7fa30c6U, 0xf725b51be802c2c5U, - 0x2604fa141cd200d8U, 0x11fe2315f6d11ac6U, 0xf9f50d0429bceb23U, 0xd9b5f00f1222ff0fU, - 0xa1d6df051f27ef22U, 0x153629cd11e32b1fU, 0x3f1e1b1ee006e711U, 0xed1bf98c03fa5ceeU, - 0x96eb4935f8d6ca0bU, 0x811349050874acd2U, 0xf2c9f1fa383b1cf0U, 0x15212a44f51400caU, - 0xefdf051ee20411b3U, 0xd9051de617ef110cU, 0x2dffbf2f5f7fbd6U, 0xbf3106dd17ff0251U, - 0x48fc30090236e6a5U, 0x642ae4f3ef002907U, 0x6ee9d81f2cb5f5baU, 0x13f80f1e3861073cU, - 0x15e519f8b940e140U, 0x22d82d1ff7293b37U, 0x13d8cd3128381a13U, 0x1e24f3b5e31fb411U, - 0xe26ce07af2fdb81U, 0xf6b7da35eae7d316U, 0x380cbcf21e2cf4c3U, 0xb3fae2ce2d62fedfU, - 0xb1d05900331204d5U, 0xc5ff16f0f4e543faU, 0x43433cfeca7f0aeaU, 0x38114e25f1c2d13fU, - 0xd62c30c2ced5a0f0U, 0xafcb4ae2da812a1eU, 0xe51cf21df35a1200U, 0x34f730ebff00300bU, - 0x37fdcf0057f1f805U, 0x29facdd8f0f7f2aaU, 0x50ec5f12e0d41420U, 0xfd17f032f1f63812U, - 0xc9f801fe00ef01e9U, 0x31130f18fa0ff72bU, 0xe31fcef51e0bba35U, 0x252d09dd44813324U, - 0xc8d0130aeed7240aU, 0x3200df40e62ceaa1U, 0xa90e1af20eb4f8ebU, 0x40e04d02082ee233U, - 0x14f201df3c24ffefU, 0xf2fde4dff0f7d326U, 0xee0307f4f5c65412U, 0xf430f501be020adbU, - 0x5c7b90ccdf71deeU, 0xa6bb0a39f022ca02U, 0x18f800cd24d5241aU, 0x121a23ec22401831U, - 0xfde0ea0631ed13fbU, 0xee1c39fa8167e406U, 0x29f2f23cf1dcf9e7U, 0xe70d20d40c23bbfcU, - 0x4fa37101dc8fc06U, 0xda01c211fd15e4U, 0x2451000f091c29aaU, 0x15cc0e51d507dafbU, - 0x7a5fe0fb5f4e7d5U, 0xebf22410291011ffU, 0x1a39efffee33bfbdU, 0xcd12b6e9011e27e4U, - 0x610df6df080b4ff1U, 0xac207feb825b4feU, 0xd74643fd19fffcfeU, 0xfc00e4260bf51402U, - 0x4fd100a06fefdc3U, 0xfc1d07f700e90917U, 0xaf21f0af805eefaU, 0xd90dfceffdfeb711U, - 0xf6180a08bd160001U, 0xe1faf62ef23203b8U, 0xe328de033fe6fe0bU, 0x8f6fe02ee21edf0U, - 0xf6e3fefee90c200aU, 0x110034f503e90004U, 0xcef1130381010610U, 0x1debee03ec17df0aU, - 0xf72016181a2e471aU, 0xab0f25e723152b31U, 0xe31460cbf920f326U, 0x1003070c8ff00accU, - 0xde451fdc130e7f1cU, 0xbcdd2b22fcfef3f0U, 0xc7a50b141cd9e294U, 0xeef711f52e1807d2U, - 0xf70d3b21cd4553f3U, 0xe8e72549eec0e2b5U, 0xef0eeec222e42f26U, 0x13f102230ffbdeffU, - 0xfdb96b2521d2d5f6U, 0xdfadd9e2b9ffebU, 0xce44e29df6f1f7efU, 0x20d74de0f10a2b23U, - 0xf9d2291423ecb60eU, 0xea05e356d61e06f8U, 0xdfdddf0e5e188138U, 0xe21804231058bf03U, - 0xd1028e351778d82bU, 0x3f1725d328c6e6f7U, 0x2ff30c28a75991dfU, 0xe356e712f753bcedU, - 0xe2031cebf3ebcef7U, 0xede2c79a50fdfd26U, 0xcfcb01270a95df3cU, 0xc50506055a57eae1U, - 0xcd1adf15fd271716U, 0xc3c0eed21c3ae83cU, 0x32220a4ec2fd26dbU, 0x412c81142ad74623U, - 0x20e2cac32c53e830U, 0x1a0af6e8e2dc3bf4U, 0xd11a3433d0c516e4U, 0xecce29a6e7070dc1U, - 0xdfee1c0e09c006eaU, 0x4cf41eefd6f0af1fU, 0x2402222132f6c7ccU, 0xe681f1bce5d70dd2U, - 0xfccaf6eae422d186U, 0xe711efc57ed35ffU, 0x58bfb9f534dd0314U, 0x4601ffed2c7e54feU, - 0xe3f51bbea60a2e25U, 0x59d0ca0fce34f51bU, 0xd9f53f1f1512cdcdU, 0x22efd3efd11ecae2U, - 0xd458fdf4e591e8a6U, 0xf7311425107d221fU, 0xcfd1bfd3b4218caU, 0xc7fed1d2eb271109U, - 0xbaf03d031d17f13aU, 0xef1e0c25d319e5d9U, 0x2a0f3201c14f360bU, 0x7f376d606c4f020U, - 0x72d171abd23e80eU, 0xfdfd02fcedbe0af4U, 0xc4d6ec321ef02a19U, 0x7fb11cf5c9ef3e22U, - 0xda12e4552fdd0519U, 0x4c91030cfaece1c7U, 0xe46403d18cd0308U, 0x27220038d42fe6d6U, - 0xacd2100131d72106U, 0x66f40ebbff05341aU, 0xfdbbfc12fedfe4c0U, 0xf513f40f27f813e9U, - 0xdd011b11e71a2301U, 0x212dfd3d113edb07U, 0xc9d62fdde8b02af0U, 0x2100ba25e1130415U, - 0x2613fe255c128102U, 0xf9f3f126301ff8eaU, 0xbae81228de2820d1U, 0x160fddd7c62517c8U, - 0x48abd4eb21110bdbU, 0x4f9d6efd3e228f4U, 0x14fdd5f7228dd4e5U, 0xf1fff2f60f09cad6U, - 0xe11fed1d45d8c04dU, 0xd810d200e41fdb06U, 0x3a062a23bfa4e4fcU, 0x9e7c936e5bfe112U, - 0xd3e4fa09262959f6U, 0xd78d1a5711b190e9U, 0x7f004150390f5af0U, 0xf74a1fbbfecb4a43U, - 0x31460918404046e1U, 0x1ddd25c002bfc414U, 0xead0470e0227bcd1U, 0xd008fcda2af0e9ffU, - 0xf2fab98800012351U, 0xe611b57ff0e215caU, 0xd9b923eeeef9ea0dU, 0xf0ebf7f7e7dcfe0dU, - 0x7a61af72e3b24ddU, 0xea13f51ce50732e7U, 0x3ab024042cd80014U, 0xecf60bbd23b63cf1U, - 0x4444e5cb16a7fd1dU, 0x5a2cdfd8d7e718e5U, 0xa1658e2e90402faU, 0xec290407fb09e3bbU, - 0xeebfaf8b8c63a25U, 0xe3fcc5ed08251c0eU, 0xbdf7f80907fed04aU, 0x6a19ecc818c73bc8U, - 0xe4deaa041123faf7U, 0xadf92e11d142110aU, 0x38f0e3c2d15bdbb3U, 0xfdf91a132d0d0d32U, - 0xa01f615f0c4deeaU, 0x44fa020b870cb9ddU, 0xdae7ce24b9fbfb1aU, 0xc4efe2dc0efb1c17U, - 0xd4ddf8710c10fbdbU, 0x1d1bca16c302c902U, 0xd7ebff2800e25805U, 0x862949b5fbef8115U, - 0xe9d0aa206d1543f8U, 0xb02b3efcf0dbbe23U, 0x1ad6d411c60b090bU, 0xf4aef725545f4717U, - 0xc2df1701b509f7baU, 0x258a3515f8b31c14U, 0x1062dc103e91c06U, 0x4fce09243db4e6e1U, - 0x5322c4cbf9970bcbU, 0xfde752f804f8241dU, 0xe606eebc18374ae3U, 0x20f90fe6e2e2297fU, - 0xafdfafde5030807U, 0xd2e81ebc3a1beb24U, 0x3eed7f0024d576f8U, 0xd399ebedf627a110U, - 0xd012f24427fa9bU, 0x22e9dd4d211824aeU, 0xc1f01e7083526faU, 0x1becdbc86646c60fU, - 0xc441dfe22edaa6d2U, 0x265110541a05e3c8U, 0xdc2d2be9c1ea3b38U, 0xc057001722ebb024U, - 0xd16f8ec4f527ff04U, 0x15cf3d111803e4f8U, 0x28b22036340c39d5U, 0x86ed0fbdf308f1e7U, - 0xeb1e1121c0b23c2fU, 0x7ac4f804063743feU, 0xd73598295a4c2cebU, 0xb6bd67d0ebda12daU, - 0x8d9172f1b0d0116U, 0x1e015b2fe6dd0050U, 0xd7a9db3b4947f8d1U, 0xf9c5d7cc200db9efU, - 0x221c27f6e7c66b00U, 0x81f7f291490a0bebU, 0x30f7308dff2ef60aU, 0x18fb622beaacd092U, - 0xb5d5f7c24ff8dbb5U, 0xefcd11f22e10710aU, 0xfd03dce71cf422efU, 0x541b5e2fe7c2f704U, - 0xc9f5dfebfbed4bfaU, 0xbafc00041402fd15U, 0x410bcc2bf91e2647U, 0xdc38dec3c9cd0440U, - 0xe536e93fbc0f5a7fU, 0x33f004edc0f98d2eU, 0xa40df9ede6084fe8U, 0x1026ec2a41e60affU, - 0x1210e00fc36d0148U, 0xdcfe306020bd2f1U, 0x4aee2a441fdb1cb3U, 0x2410c9ead77fb899U, - 0xd318f31c331e21efU, 0xddf106291bcbd5U, 0x5bdafd0b140f200eU, 0x17fd15c6bd700413U, - 0xea0ec3cafd10ef1cU, 0x25445c5d2040abfcU, 0x1348ccbdeac21615U, 0xa037f8ec0885b29eU, - 0xf8d60eefc93a1f0dU, 0x816cab0235e6fbf3U, 0x1f01fcccfefcdd4fU, 0xe3dc0fe33303e944U, - 0x4319b0fadabcafefU, 0x65d7de03b657dbf1U, 0xdfdd1916b78e990cU, 0x7b999c1e97ddfbc8U, - 0x1a0d2e09d3ef25fcU, 0xc8c4fce9e5cbfd98U, 0xf8180ed40ccf3ef2U, 0xffce2bead26676ddU, - 0xbe00d6042cee23d2U, 0x31503320274ab620U, 0x3527d6d3f82905c5U, 0xc4812a3046084524U, - 0x62614c509ffdc35U, 0x34a94535cf0de4f4U, 0x580ef73709f501dcU, 0x13062414830fc7f5U, - 0x4a3e1be927fd5d1cU, 0xc1094202d79e35d8U, 0x16170a81dbf744U, 0xbf9f9415e5fac26U, - 0xc6ca2628cf165dfcU, 0xd8f700710d01fbc8U, 0xec3d1dbeee4b22fbU, 0x709f31dbd0e414feU, - 0x1d911ebbf0116e9U, 0x29f8c6eb44b8e63eU, 0xfcfcfc2f65423e22U, 0xdd78b29f5a63ed7U, - 0xe9ce01f9f72902feU, 0x1e0b090322e3e1ecU, 0x7f11f334d0da1cddU, 0x9210a0bd72e9619U, - 0xc1a6f7f8a349f1faU, 0xd64de2e8d1fddd34U, 0xc331954eced16ccU, 0xb4d034e80e8ceadeU, - 0x3e6202fd17f4d612U, 0xa32d2faa44935e9U, 0xdfea29e9f21023c0U, 0x3dfb0a14cf052713U, - 0xfdad245df52f66eeU, 0xfa1c080c9eb945a9U, 0x3ae255b043f60805U, 0x7ff41ad6de190c0aU, - 0xf328c934c5d61a11U, 0x2d184452929a2a66U, 0xd9ce3d0b1d077c2cU, 0xfdcd2ac5c81c5137U, - 0x11411e972de2a0e7U, 0x80421e6db27d2e6U, 0xff9eabf4ff50e6feU, 0xea19a120e23525c1U, - 0x15fcc6e12019f5f8U, 0xe1f347b7fdfe1927U, 0xd81634031581f016U, 0xe1ce0502161bd9dbU, - 0x8162d05d52f32fdU, 0xf21c091030c21032U, 0xda5307312df30e1eU, 0x41ceb2128e13107U, - 0xd29cc0023f0c9e1U, 0xa1cdf1b45e3fbefU, 0xef05deecd844de0eU, 0xc52dfde60027ecedU, - 0xe1ee0eba42d7e3fdU, 0x161927fd974ca82bU, 0xf60ffff6050605ebU, 0x8a62cd4c4021bddU, - 0xce0d26fa4b229c31U, 0x9bfccc0b4d030908U, 0xb3d9de015e40fe2cU, 0xc900a8d114b6f6adU, - 0x810604c3064a05b8U, 0xe4de0fc2ecce17bdU, 0xb9526c111640f2ceU, 0x27dc0ae3b3dd6821U, - 0x4efebf13c11ac227U, 0xb4ef54a82d49c012U, 0xe1638f400f4131fU, 0x1b020c18e9a0310cU, - 0xd602f2fa055e2e11U, 0x32aeafbb5b3c205U, 0x6bfb3e0f29120ee5U, 0x11e2f722be28d2deU, - 0x21f6ffff4e07e72dU, 0xe34114072dcfeaefU, 0xedca13df2efbfae2U, 0x2314cb1a51f4d1dcU, - 0xee1d081a18174f4aU, 0xca2cccecf30003e1U, 0xd3652bf90b21d221U, 0xf03f1cb434c5edafU, - 0x4ab114f6a8e4f765U, 0xf67fd9ed30f8e3edU, 0x1b063304edf03e25U, 0x2627cae92d21c909U, - 0xfb217cc0e0cbfe00U, 0xf7e70f4512080f54U, 0xf0cf4fe2806d028U, 0xebdbcef303eff7f2U, - 0xbbfd01e8f2ed26fbU, 0x81230dfc31ded331U, 0xf7e4372093cb4201U, 0x101001e8eddd2100U, - 0xbddcc2f1ddde26c7U, 0xcdf32c2e2cdff2ddU, 0xf2f8e7ea0ef038faU, 0x1cfd49e7bfd103b4U, - 0x1a46008cf8bed6c4U, 0x43f3040538040ddcU, 0x268cde1c0e1de3f5U, 0xf753f5443ed2dc0cU, - 0xa93e062a3fc2f4f2U, 0xc00a09f1ffc61bd2U, 0x6037e6bf53cb17f1U, 0xc710e7fc05195a53U, - 0xb4fcc881215ceae5U, 0x283f3221eb5ed50fU, 0x1c3f0ebf1f08101dU, 0x41140af3fffbf568U, - 0x442ce0ddcf6d4edU, 0x7fcb1eb9c7e12b12U, 0xef2dbcf62964e7a4U, 0x170e31f14ede06f4U, - 0xebdccbfd5b9e5f9U, 0x792109f61827f33bU, 0xf7ef1fe0bc2808fcU, 0x36121ace0cfb0a1dU, - 0x14f83bef1bf40ed7U, 0xf2e4e311d5fcdb2bU, 0xd224f2e2ddb3d610U, 0xf7dce5fa083ce929U, - 0xe14c0ae342caffddU, 0xe3f32204d86d410fU, 0xaffbb5ea22e8180bU, 0xf607c008c99bde03U, - 0x2f6d901e42525dbU, 0x411530dac907e718U, 0x2004d712e0dc09feU, 0x1ef41514d6c42bf6U, - 0xd530f3070e49e21cU, 0x1cdac64aefedef17U, 0x7f0af133f2e3eb0cU, 0x108cfb0fea0007d3U, - 0xdf3b16da33e73d03U, 0x31fcd43216fe130bU, 0xd615eefed34a0905U, 0x9010955effdf4f7U, - 0xc928d0cdfa1006c2U, 0xd5db190b2909cef8U, 0xcb0bc7d856f91a04U, 0xcb8eb4606c007d3U, - 0x4fee8f943fecb1eU, 0xe0d8c50207f9eac8U, 0x39fe0d15f60634afU, 0xb454f5182c1813d7U, - 0xf8f4e918d7f45a1bU, 0xb2dde41ec08def1U, 0x45e132cc26fde32fU, 0x25f73844103adbe1U, - 0x30f7ed1a4fbaedf1U, 0xc4da2f270e7fe3dbU, 0x3e3f22508114c15U, 0x4b70ae523f4f9ecU, - 0xe300345ad31efee1U, 0xecfdd60b01db04ccU, 0xe60d0c1417eaec29U, 0x4431dc3ef91f0c5cU, - 0xf83ad513f6e4c00fU, 0x4b5bcb78c7f01628U, 0x36cdcb09b537da2fU, 0xbd09bde233ea0e1eU, - 0xda6ba9ff2d07f614U, 0xee073009d87fb62aU, 0xfff0330031102d5U, 0x2feb3c2d06021198U, - 0xefd5eff7efc9130eU, 0x9e6e8370b1704feU, 0xf279ecfd1508d8U, 0xf02d421cd2f8e0e9U, - 0xe91dffed24140e07U, 0xe5d0e30511d48127U, 0xc64ce414cb44e9d4U, 0xfbd8c1491a4e01ddU, - 0x40208cc34cf0a2fU, 0x19f829facb32ecbdU, 0xeafd060af802e304U, 0xf8f9f2e1f109c8eeU, - 0xcbebe0b3e1e70df6U, 0x1a8a14caebfa2fd0U, 0xff7ff01ebdcf4ffU, 0xbdf4132ce9321392U, - 0x3315b07fffd20df5U, 0xe797e6e7c9394a6bU, 0xf71b402064fccb1dU, 0xba0401e5f8ec0c0dU, - 0x905ad106d4f3eec9U, 0xc631e206070fc13bU, 0x2037b71d5eb816e4U, 0x43a0f0c5711132bU, - 0x142e27dbfdec6d3bU, 0x18be0e980d07cd11U, 0xeea102ae11d4f00U, 0xfce2421604e92218U, - 0x7e9b40ff3f2d006U, 0xf92f29b3b7c5f3feU, 0xf0bfca0119205405U, 0x18ed021863ff0bf2U, - 0xfcdec70619f614e0U, 0xe93ebff6e4fe4a37U, 0x270ff6e7fa14eae1U, 0xdc02fdf6eafc002cU, - 0xe210242805e80b7fU, 0x15db16f4e7eb0416U, 0xdcf8bdc6fe24dd25U, 0xe20cef0d1bff115cU, - 0x342000009b1U, 0x101cffffebecU, 0xfffff34f00000e89U, 0xfffffd81000007adU, - 0x50dffffdf11U, 0xfffff06a0000029cU, 0xbc3fffffd33U, 0xc6f0000093bU, - 0x36500000441U, 0x6f000011feU, 0xfffff0b8fffff627U, 0x1e0ffffe0e8U, - 0x4eefffff93eU, 0xfffffb8bffffebd3U, 0xffffece8000005e0U, 0xfffff98800000070U, - 0xfffffa8dffffcf6aU, 0xe92fffff2f6U, 0xfffffc67fffff7efU, 0x20f000005f1U, - 0x1d2ffffff05U, 0xffffdad8000012bbU, 0xffffdfea0000038eU, 0xfffffd24ffffe325U, - 0xc21fffff8b9U, 0xffffeba1fffff1b3U, 0xfffff5d000001359U, 0x523fffff9c9U, - 0xffffe81600000ac9U, 0xfffff427ffffe5baU, 0x66afffff5c6U, 0xfffff9bdfffffd53U, - 0x720fffffb77U, 0xfffffb00ffffee3dU, 0x2e1fffff68cU, 0xfffffc36fffff741U, - 0xffffec7cfffff490U, 0x9f4000000f1U, 0xbefffff354U, 0xfffff10dfffffe89U, - 0xdfde2a7fffffe464U, 0x817f31177fa414d0U, 0xc289e27f377fa03cU, 0x8120ca4f4d817f6aU, - 0x8181cc3f1772f890U, 0x4ae25f817913f87fU, 0x8181f76ad2e68191U, 0x25817f81367fe4b2U, - 0x810e695c2ea17f7fU, 0x817fe9120581bb6fU, 0xff0a2c8173e7c5e0U, 0x2224476bb6f1182fU, - 0xd2f5522e10c328baU, 0x24fc271ae4185cd9U, 0xd8cd4419ffb4b6dcU, 0x1459a32f031339c5U, - 0xf71102f0f9cd857dU, 0xbb58b4061ffff5e1U, 0x193a1125cd2317ffU, 0x42061412a7b645e7U, - 0x2364c40dcbb6f8e5U, 0x174f2dcd10676100U, 0xfc2c5602c26710e9U, 0xb71bf21e1753c1a3U, - 0xf42c0503d8c0ee01U, 0x29ae36f42a29d7eaU, 0xa222015b8bf7f16U, 0xf9c40655fc0ecdcaU, - 0x621afee72ee808e0U, 0xcbd80fc3aefd0421U, 0x24e10af6a717d822U, 0x6437d2167f7f41eeU, - 0xd7fad8a2f00c10eU, 0xfeed0fd67fedd7dfU, 0xf0db0efb810aeeceU, 0xb52ce83f3de3f427U, - 0x12140899811214f6U, 0xb62d46180bf6d7eeU, 0x2919c73103fdb71cU, 0xd516cbac06107f6bU, - 0xe13710ba3ad529afU, 0x17cbfd706774ccf4U, 0x74c0817f65c62760U, 0xd714ce2de0cef5ffU, - 0x8101c4a304f3b309U, 0x53f3122a12fc4d06U, 0xc19df86fb0f00c2U, 0x20f1130715c6f6faU, - 0x24ce160c01a706d8U, 0x2cc81e009626630U, 0x3b05a936c809baa8U, 0xf51a311574bc33c0U, - 0xc7af4b7bc14e7f35U, 0x44cc0fcbbaefed0eU, 0xe3e5c80e22e5f9eeU, 0xeef82652f87f6a8eU, - 0x2d96d32104dec856U, 0xbf2d2715fad1160bU, 0x62fedefef723d02eU, 0xa887d30c6205562fU, - 0xf59a56daf1b28df4U, 0x401f047fa03fe231U, 0xe53875d5225b1c17U, 0xc9141606d1050facU, - 0xf3ac02413cc9da12U, 0xf4164ddf4a3492dbU, 0xd5f313caaabe39f4U, 0x2b1c01ee9cda0a2fU, - 0xf2e1e1c341df30aaU, 0xabcff27581284b7cU, 0x942b0d0e9fa5f1f0U, 0xe1e56a9d58c20dd2U, - 0x1d5fe2176f1e0e3fU, 0x9243ece10e7b1f1U, 0xa108313ac1f801eeU, 0xc27f6dd1fc0d16aU, - 0xdf0eafacaecaf93eU, 0x1711d0a8c80c44c1U, 0xe307c356db02ca34U, 0xb7fd7bbb433e62acU, - 0x211d1881abc80095U, 0xdf56ea30c93fde92U, 0x56f6be7eed581de9U, 0x4a31b01df2bd242eU, - 0xfc360fbc4adb062fU, 0x4fdd2d0cac46ed8U, 0x109eb7c7bef023feU, 0x2b2dd9a295dea06U, - 0xcfe13becd6123c27U, 0xcfcd63223288cf9U, 0x261dbb8cbad6b5c4U, 0x50814ddd5bc79c47U, - 0xe781338f7f7fb6b2U, 0x7f811bea964d4523U, 0x7f7f817fbd50677fU, 0x99d8132817fd202U, - 0x81810b81817f0d00U, 0x9681817f7fd64a26U, 0xc772db81297f7f41U, 0x571c7f7f7f82c581U, - 0x39da81811f9e8106U, 0xa27f81817f22U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0xd2e7290e00000000U, 0xc21be5f01afc0af5U, - 0x4dd3e23ebb0e491aU, 0x22e117dc171536c2U, 0x1208db135820f738U, 0x2414bfff23e71145U, - 0xbcb3ec15f881f310U, 0xec1be60b0717f920U, 0xbf5e7c4f721c217U, 0xe7c362ec2d283a3aU, - 0xf653e412dee5e3dcU, 0xcf4ed07e2d316f3U, 0xad13bc8fb14c6cbU, 0x1419dff2f01ca335U, - 0x1701e368000d2c43U, 0xeed0290a14f2f5f0U, 0x7dc3212c30df228U, 0xd81d0e24f6c521e5U, - 0xc3d0abd3feedf63eU, 0xa27fd4353f2f1907U, 0xdecd0ff70127c7e6U, 0x5a01aea0d252f15U, - 0x1c87df08ef2dc9cbU, 0xc33344f52d114216U, 0xe5f373de142ff6e7U, 0xf000fd3ee2b62319U, - 0x12100fda3b19df66U, 0x1315205aeb15e281U, 0xe2fbf6cff7f4fc10U, 0x4516ff2a1c0606ecU, - 0x3c3ce7b32edce819U, 0xf1c95bbb8c9c8948U, 0x3baff92512d2111aU, 0x81d2f5d4fef8153fU, - 0xc7eafecb062ac719U, 0xdd384660bb830ebU, 0x4f0716d31b3aaf12U, 0x4399c6f531fee6f9U, - 0x2eef5719f0193ae3U, 0x1c78f1d7e931b02aU, 0x31c31f33de0fe703U, 0x2c01232010fdfbfaU, - 0xd6aa81f1e2b522bcU, 0x31cb330b5b1c24a5U, 0x12051ed1541bf25aU, 0xe5563405f549bbf5U, - 0xc9ec0cd1c40cbea4U, 0x2368a75e00e3705U, 0x12a0090cd900c708U, 0xf6e52c0310ecee26U, - 0x1619d31622fc13d8U, 0x622c6ddd0fdc1fdU, 0xb9f920f1cd24f6e4U, 0xdc0ad51b3b0ddf0eU, - 0xa12f9cf30cf08edU, 0x70b33bed0f4d4dfU, 0x142bf53242da47ccU, 0xe78123e6b3210ca7U, - 0xd5ae36fa12043e2aU, 0xc690109dd1df8e5U, 0xe21035cc00fee203U, 0x12190fc2edcfe8f9U, - 0x2622335709c7c00dU, 0x50ced4d558f64593U, 0x4a361019100a5104U, 0xdd8126fcd62916f0U, - 0x1eff35c03201f50cU, 0xbaf65897297f2d3U, 0x7395dc3b10dcef2eU, 0xb4e932e72ce6c6e6U, - 0x42d26f15d30a2614U, 0xf6e235fb1effccbcU, 0xa6f7e0ee180afbc4U, 0xe70bfe81de73e227U, - 0x532d0f4f645183fU, 0xcd5e128ee303fe7U, 0xe9f038f7131320c0U, 0xd1e501adff0423b3U, - 0x3d49e5fbf5020aefU, 0x1bfaf8effbf22107U, 0xddc82baccfab56f1U, 0x1006093192151223U, - 0x3128f3ccccbdc4eaU, 0xe508b5e330ebfd17U, 0xc5e908f90ff9ead7U, 0x24e35fefaf7ef17U, - 0xff0e1ad819fd0a53U, 0x2230abd129fc0024U, 0x173ed461207fd9f7U, 0xb0b2272fe9fe16bfU, - 0x2813e74456d8fbe3U, 0x1a092d092a262ee1U, 0xe2c31314fdf92ffbU, 0x9b0330e1385ab8caU, - 0xe608eddd10f74edbU, 0x7f7212f25090f0fU, 0xf236df1df80ae73eU, 0xeafb0b4381ff2808U, - 0xbd6d3ce210604f1U, 0xfaf414e908e33ddeU, 0xdd60eb432ed90ef5U, 0xfcdc24c859e98a0dU, - 0xdcf92bd02bd80826U, 0xe852c9c4eba9a704U, 0xc9e6ffbb1ae1301fU, 0xc9de1f450f0e4736U, - 0xe03010f71a42a5fdU, 0xfc35e3dee4e1346eU, 0x1afd53cf810fac37U, 0xf4ec08e2e266c912U, - 0x29d02e1e522ecbe1U, 0xcbf4e4051400bec5U, 0xb33a18318639dbfaU, 0xdfec19050cc9f6f6U, - 0xca1822d520514f56U, 0xc24cb4c10631f6e9U, 0xde01b755d9f8310bU, 0x4ca1f43d1cfcecf6U, - 0xd145030767f69510U, 0x157f44edd9082ab7U, 0x253a160ba70f1009U, 0x253f97b614440418U, - 0x1de4b12015df12edU, 0xe3292ce9d603cb1dU, 0xe507e01309edd929U, 0x37fe15502de91f18U, - 0x241503c95938080eU, 0x4d81fdfff00af702U, 0x1f00fdd00a2cf06U, 0xf9fbe8da08e4f8ddU, - 0x5214ed490c28fce7U, 0xe01af9a802e151eaU, 0x34d8dec4c516422aU, 0xbf3e20f54e0cfc0aU, - 0x17fd0fd6c4e014dbU, 0x10cf3531d20d02b7U, 0xc803fa9db10f19afU, 0x5a3828bfa315ccf7U, - 0xaf3dce2320c8eef9U, 0x183c583d1ef681c9U, 0x51505e11f22af08U, 0x21c037e0bb4ada49U, - 0xe52917cc15edd516U, 0xf7d73a2f14ece1feU, 0xf3efe3dffeb6f6e8U, 0x3a2531161b24081bU, - 0xe9811259c702fdb9U, 0xf7ccfaec490f05feU, 0x1ad046a82aa0212cU, 0x26a517e319f0d006U, - 0xc1cf060bfeebcfeaU, 0x43f652fc23d0da18U, 0xa3d5b8533df6cee8U, 0x30535bd410981eb9U, - 0xd0e39b003130f853U, 0x7fece1480a992be3U, 0x37b01346dee258feU, 0x6bbad734beeb650aU, - 0x9230af0dec192612U, 0xcf264cb652eab8d6U, 0x11b0943ff2e7503aU, 0x32c29ef367d3d3d6U, - 0xd8f921e1244df7fbU, 0xa2026962223cf2bU, 0x45c34ce3cd0c5b01U, 0x2d9bf968242b1c2dU, - 0x24f8e55e0403ff10U, 0xdb28f4e1b30b28ccU, 0xb0fe680ba9317f20U, 0x53eccebc06ebf813U, - 0xdb0de1db52dce319U, 0x25e50b570e18fae4U, 0xf2b130239d3a43eU, 0x7e0f4e2f0fc2a0bU, - 0xc98627cc094ceb88U, 0xc12b0c1a073fdb05U, 0x137d47f221e5c51U, 0x9efe21408e8fd75U, - 0xfbc70414abd4f9ddU, 0x14bfed2c31f7f8ccU, 0xebcae3e44602d8eeU, 0xfd363b201de358fdU, - 0x442ddfda30f8d2c4U, 0x339ef74cbc2ad6beU, 0x692381d9122014d7U, 0x93c20bc011116edU, - 0xb5a93e16e9501fdeU, 0xe5b3a5523519ef39U, 0x26fce7254ce6bfdaU, 0xe6f9efcbdf061cf1U, - 0xf17636f854fb476aU, 0xd027d6dec7e003f4U, 0xda5f26c3b81dd2f5U, 0xfe23dde0cd1b5335U, - 0xbb400ffbe7e1f4deU, 0x8d0e543e5d840adU, 0x275217e6ee08dd1aU, 0x263b58cfd934f24fU, - 0x49c6d8fdde19521fU, 0x31fc29c1b8c62aadU, 0xfaccfaf71bf0c829U, 0x1e7ffe4a48fab4f8U, - 0xc8ef306c1921dcedU, 0xfa2727c3e523fd13U, 0xfa0d251dc61225b3U, 0xfcedd04145094b08U, - 0x47c4d4eb17fdc897U, 0xf78e7f0bfcad1ff9U, 0xb0e2310f47c1dac5U, 0x2df4ff29eaed0b21U, - 0x782e311544df0ef6U, 0x21fff6d6f631fe42U, 0x39cec11648db3003U, 0xd8f7a8e03319ba02U, - 0x3830440d32faffdaU, 0x56f0ddbd21c9c14bU, 0x16f5eb18c10eaeebU, 0xdfd1d40d1b3605e1U, - 0xb3f5ed2146422c36U, 0x252af42781d51e02U, 0x3f02d80726f2090aU, 0x44d1b00bbf806feU, - 0xae36ee12e8fd2a59U, 0x204e06011f0f17b6U, 0x5ab62420da2047cdU, 0x2b23e3e3110adf1aU, - 0x35ff44151cccd8cdU, 0xe4c52e1ae8fb4460U, 0x10a252d080723U, 0xced6f0b40d203daeU, - 0x3f00c81909b9f8fbU, 0xe22fee0ee6fae602U, 0x1e8811d97fd0684cU, 0x42db4b00b1ca215U, - 0xe1c9b3e9ea1a1afeU, 0xee453f3ee7efba05U, 0x2f33eae75d1cbd5aU, 0xe94213151366eddbU, - 0xf6fcf8e0d5ed43f6U, 0x3beedc140cad003eU, 0x143265ccce2cfad2U, 0x810d15e91a44eaf8U, - 0x1506e9fd12cc3adbU, 0x5d4494d1230abc5U, 0x142fd4dfb8fa9cb3U, 0xddb0c9380ce7510eU, - 0x90c924f8b426f7d0U, 0xe02c38c0fb4de47fU, 0xc31b17b8f6550434U, 0x35eeba042c040e67U, - 0x2c54c46ef9fcd596U, 0xb89d3119d4333cb3U, 0xbcfbd655f1c4f2ffU, 0x748fb4613232021U, - 0x2ecde160c4dd0310U, 0xdefe29a050f4df81U, 0xeffe0dd92ad2fc11U, 0x16f4205234385300U, - 0x33d0f62c21350e38U, 0xd3df21638ed5030fU, 0x2f0f02000cc0fbdbU, 0x1aebf5d5de04f7e3U, - 0xd1732c421ff433fdU, 0xfe05301f2e09edc1U, 0xf3ac3c3aee3af5beU, 0x42d5ad814b38cbe2U, - 0xed5c4caa344257f9U, 0xe14200ada4c1ef7U, 0xd1dcd51424c64221U, 0x1225dbeb35c0dd4cU, - 0x1a2def2cd23be02U, 0xdad102b8193a17ffU, 0x1bf6e81befec1428U, 0xc2b1c0f061cf2ebU, - 0xca25f129e241e722U, 0xbffbe89909d62a0dU, 0x6089df0fc041a51U, 0xd119ed43b92b08f0U, - 0xe7e5bd191df70fe1U, 0xeaf6ee09a5e8c52dU, 0x3a1723373bd01507U, 0x4319fef7f2bd07daU, - 0x9ff917513714cdecU, 0x10d5efea047ff407U, 0xd11702fdf8f316c2U, 0x210abe7117af17fdU, - 0xf400afc5f44a2081U, 0xb6bcfc18c314e5d3U, 0xcf7fe00050c46f5U, 0xed4e4afbf509d927U, - 0x33f7a50611b22f1fU, 0xd3f4c01a1cf80315U, 0xbcf818d657d12418U, 0xe0f04261dc2dab0bU, - 0xca19e95a18effb14U, 0xb9cf08bd13e012d4U, 0x1cdbd9e002c7c323U, 0xf81255cf4cf1f917U, - 0x31be203b19edf92eU, 0xe0ec1df74b34f629U, 0x71dcfbfeef91fc12U, 0xec06c6c80ece7f2fU, - 0xdc0526d0bff62bddU, 0x1949d00f41eabd48U, 0xe33033f9eee909e6U, 0x810002c20802e7ffU, - 0x13fe0ff7facc1dd1U, 0xd908121de0d8edebU, 0x2ce433f81819f9f2U, 0xf4202d4be1ed011U, - 0xb7f2112a09fc26f5U, 0xfb5df0170a09d7d8U, 0xfcfa0ffc11ea22dfU, 0xf9fff9fb150e0914U, - 0xe714fc00ea16dd19U, 0x1cbff001a91e11eaU, 0x3558fd57e5ff201cU, 0x292de8e80535f924U, - 0x2253e13cb36e2baU, 0x2d37f6cceaf5a856U, 0x4cf6ed235481e54bU, 0xf44626b9e034fe10U, - 0x900543082e74270eU, 0x3243f11a1e132e03U, 0x3ae8070b2a5e8bb0U, 0xf8caf8c50217d912U, - 0x2e0d42e3d3d81718U, 0x13e9f5292cb9320bU, 0x201bf40346fdee3dU, 0xe5e5e9d9f4154af5U, - 0xdbfc2711ba1141ceU, 0x362d81061f00eb54U, 0x17f6e64232ef090bU, 0x1af5000adc24e2daU, - 0xf4040d10049dd122U, 0x619dc07f3d62df2U, 0x12a0a37dde33aceU, 0xe5f70bf21d092cdbU, - 0x57f7cf0b81f4141bU, 0xf506ff02b05ee041U, 0xe2f2ee0cff211511U, 0x32fcbadbff492309U, - 0x20fd1a561914d32fU, 0xfff80362f7f8b61dU, 0xdbf221f9f1ce0753U, 0xfdf1ed1613020f01U, - 0x1ff10b810505f41aU, 0xe01cfe0b0c07dff1U, 0xe8f2e12517121627U, 0x16100eebe5e3f1fcU, - 0x2fd3d2060de61a0aU, 0x22c60cf114d507c8U, 0x17e0d5e805f4a122U, 0xf9dfd1fdee1df3e8U, - 0x5111eee728140ef2U, 0xad0260c436e1902aU, 0x5e98d54511dcde29U, 0x2c18ec3a380a8e3eU, - 0xe9015aeb7f21c80cU, 0xa8a94327e3204ad9U, 0xad2122931b142d7U, 0x4d4c7bedffef915U, - 0xfb00f5320e3636eaU, 0x5debc6c8c8cfe1f0U, 0x3c120dfb26d8e602U, 0xaa20b4add1c24848U, - 0x1ef03b14392cddd4U, 0xa90bf7e3eccc2134U, 0xe739e87f08ea4804U, 0xfc532a26e91834d6U, - 0xfa1b4067c1e03dcfU, 0xd5cccba13dc801fdU, 0xf84f1ee63677ac2eU, 0xcfc8ecf9cd9e3cfaU, - 0x4aedf101d6a3c36eU, 0x19b5d8a7ba334254U, 0xdd4a2a3459fc02dbU, 0x12a0e4d21ae81fd3U, - 0x15d457220e2bdadfU, 0x31808c1f803dab0U, 0xdc1bbaf98122c8d2U, 0xb32fdb2bd908150bU, - 0x4417f9322ef5c3adU, 0x10c6faf1d136e1eaU, 0xf60201f9bb1be048U, 0x959411f8365c1e14U, - 0x4afc15428fea9fbdU, 0xc6c8dad304154122U, 0xd77cb8c22012af37U, 0x72ec71522180144U, - 0x5e7ac43952b60e40U, 0xd5b139fdcfcf1b13U, 0x6c50b7fd86bee49U, 0xefdaaa13638d51eU, - 0x214019121060fceeU, 0xd90b2abbf436220aU, 0xc5cecd1de514001aU, 0xb41844812804f8c8U, - 0x3c56dfbdf319c40bU, 0xab3b22ac626173aU, 0xfdf52eea0f1833c2U, 0xe6a0e2e31e00cacfU, - 0x22dad7e1734bb8d8U, 0x3fe7bb030dbce5deU, 0xe0a2fe0810d01454U, 0x38d17b0ff1c70b7fU, - 0x4a08c62a31aae52cU, 0xfff5f500d170dadcU, 0x435626ffc431d4b1U, 0x53432fcaece6151cU, - 0x11d31a0e152d0581U, 0xdbc0f7332922ebd3U, 0x46a9eef81226eaefU, 0x10e1e1c3c5fd49e9U, - 0x1ecf4a25374ad108U, 0x9028220ad7e670eaU, 0xd130db0638d82ad2U, 0xbd4f05a4dd1b310dU, - 0xd50b2418ea08290bU, 0x3bc4eb0424e73714U, 0x31c8b1b6411bdd0fU, 0x812c1ae5092f2ad6U, - 0x48eaecf6f2bacd0dU, 0xeadf27f6d53c0229U, 0xfaea3fd1dcd5dc0dU, 0x2af04224d9fd04cdU, - 0x19c0c93bf017f698U, 0x12e51210f068e6e4U, 0xd6eb162042a3fc05U, 0xffb2f08cd27e4e4U, - 0xff1cdf0cbb0fdeedU, 0xf504f6ca415c16d4U, 0xf8071d13de32f281U, 0x19b3fe06ba19db69U, - 0x283dee062afef0dcU, 0xf70ee8ea2ecfcbe7U, 0xde47311a7203f4fdU, 0xc0aa81180ed8c8f9U, - 0x5849bd2a155fc52dU, 0xfa3906f91e1227f1U, 0xcad90522d94621faU, 0xf7eb0f2ae3ff38c3U, - 0xda0016c612c0042fU, 0xf33bc61336f5d3f6U, 0xb3db2c00d4e623afU, 0xda13cbc042fd1615U, - 0xddae9fd74ff52512U, 0x25f6c6404804f2a0U, 0x17f10dfedadcbdc7U, 0x62d3126192ee0b1bU, - 0x42fc21a004923daU, 0x244a1423e22429cfU, 0x597fb63d13ccadeeU, 0xfed5cfb34462ba6fU, - 0x5d8806bfbec12254U, 0x4ff101f0102ae656U, 0x2579000de2dccd23U, 0x3705daf50b2bd3efU, - 0xd340c4dbfe16f4e0U, 0x3e224023ebeb3812U, 0xccf3bec2102d8d4U, 0x310b3cd8b825161bU, - 0xedd1f31c5839dc25U, 0x81ea20bd369ffe1eU, 0xd12fdc91021fd5e0U, 0x3341ff09ebf62133U, - 0xa5b89bea591821f7U, 0x7f2352371d21c3d7U, 0xb0c6dcc3de040036U, 0xfb1d1ee12dff8a7eU, - 0xf3f0979d3059dc5aU, 0xed09f7def1d2b64dU, 0xb9bd21dd291bf409U, 0x14af3fe8e01aae85U, - 0xd71322ab26f4ea31U, 0xea09f2b5116b51f2U, 0xd80af3264bd6ff14U, 0x2d0d45c6fbab36f9U, - 0xc7cbdf202011e114U, 0x62ce2c38eafc1cedU, 0x49dc2d2518f608eeU, 0x61f6f155c8074c04U, - 0xc831e2e0db0ffb15U, 0xf0cb35c45e044eddU, 0x281c11df5d83821U, 0x1de8da03cccfe2e0U, - 0xafb91b383c45f921U, 0x4e59f6f1caff92cdU, 0xcf14f10501b55d05U, 0x13075515b1eeb3a9U, - 0xbd152fe9c93bd77fU, 0xf89c35ecfa4a293cU, 0x179ae5f326da1ac1U, 0x2428c11dbc92e6b8U, - 0xcd973415f73515d0U, 0xffa813b970c7dd0cU, 0xe55cd740221d21deU, 0x4bfad5e31faf1c21U, - 0xf10ba9e02998fd26U, 0x38f8e21d1c99b135U, 0x2b7fe2e5d9dc2520U, 0xa9d8fb34f4e4cc2fU, - 0xe8fcfb252622edf4U, 0x11e7fd0ef2e4e53dU, 0xd8efc3e60e1cebd7U, 0xd40932a905dadd1dU, - 0xfe0b141110451af6U, 0x45b8b82bfaf90fb8U, 0xea2dedfe012985ddU, 0xa60010e13bb92232U, - 0xdae8170c2407ee26U, 0xd425f408b259a2e5U, 0xfaeed3bd465f29faU, 0x19593de5974008a6U, - 0x2b7f2079f500e36U, 0x18192e4e7f16dcceU, 0x39e1c9ff3900af28U, 0xd2decf00cd13201dU, - 0xaf8f7d6371909b9U, 0x20f2cc0224e5d11bU, 0xd4f1f20214ac0bfaU, 0xb5ffe61213d852f2U, - 0xdc301c273fff197fU, 0x552f3bb10a08bae3U, 0x41d4f8fbddeb2bd6U, 0x1c32c6f6e2d6d507U, - 0x113bc316422a1bd0U, 0xcdb000000daU, 0xffffff830000059aU, 0xffffffbffffffa63U, - 0xffffe8d100000043U, 0xfffff793fffff02aU, 0xfffff4b5fffffda9U, 0xfffff5630000057fU, - 0xfffffbc3fffffb85U, 0x11100000532U, 0x8aafffffaf7U, 0x97fffffed9aU, - 0xfffff7d0fffffeb1U, 0x51000000673U, 0xfffffb65fffff871U, 0xffffed28fffff8f5U, - 0xfffffa20000001e9U, 0xfffff858fffffa94U, 0x8c0fffff705U, 0xfffff841fffffe34U, - 0x37b00000a14U, 0xfffffb260000039bU, 0xffffec650000081dU, 0xb8ffffff4d7U, - 0xfffffbcafffffc57U, 0x372fffff421U, 0xfffff5c80000080aU, 0x7fa67f7ff8a08135U, - 0x7fd72846fe81f27fU, 0xeadbaffdd222b63bU, 0x29881777fd25781U, 0x7f7f21817ae4f10dU, - 0x8181338168814e4cU, 0xf8c5a50f7f81d17fU, 0xf9bcf70270c35850U, 0xe50edc1c3fdd1b31U, - 0x49ec63cff2eada0aU, 0x43f2ea02fe81c07fU, 0xbc9345f38291abbU, 0x32bbce42cce7c3c1U, - 0xfde43574ed9cb73aU, 0x32f044480bca0408U, 0xf5e8e404d814ed29U, 0xff10c75344b641d5U, - 0x212330c344f6eafcU, 0xd8d1f4c044992b7aU, 0x394ac5c10ccd64aU, 0xf9c7e10afebc392dU, - 0xfb1fd92529e63b17U, 0x6f9e30cbf0e5fcffU, 0x43f208f6fd09cf4aU, 0x14be25433f2153cbU, - 0xce1b34adbf9760eU, 0x2d33a2ef9c2d434U, 0x20ed0728f8dccb01U, 0xfe0f9fca413f60cU, - 0xf9f6e93425a9daebU, 0x141c37d83ffa07f4U, 0xf7cccfff11c72f4cU, 0x4c5b454f8cde64eU, - 0x3cabdf31dc6372eU, 0x821cf31c3ae07ff5U, 0x17b7fadd11ded40dU, 0x56f108020001ec3cU, - 0x49de1d43f82044d2U, 0xe8fecb41e6bf3d00U, 0xc6b9342a14b3ba76U, 0x23dd5e38ebb7e30dU, - 0x25e5d306cd1ae622U, 0xbdcf0631d8101d5U, 0x61246df3bf30802U, 0xe3d8390820d72345U, - 0xdb6b361f5eed93aU, 0xf8d6c307b3d03321U, 0xde25ed0c14d51d10U, 0xeca8eed707e0ec06U, - 0x46ec10f7fe12f453U, 0x6deb2350181163d5U, 0xeb09c750e0fd1805U, 0x1f89265a1fc4b724U, - 0x1fcf64eafad0c7f9U, 0x2abcf50fdb34f711U, 0xa35ed3ffe94e5d9U, 0xf90e7bd93ae81ff1U, - 0xf4b41909421a1b4cU, 0x2ec3b949f1f02234U, 0xf9cbdcf839cb2826U, 0xd022fa2817d478edU, - 0xf9ddcd2f6c9e007U, 0x4bf213ee0b02f32bU, 0x5fc22126151367e5U, 0xee04ed30f2cc5af5U, - 0xc7ef242f1bafc245U, 0x15d93ad3efdfdbf4U, 0x24d6e6f5d8214019U, 0x11fef14031accde7U, - 0xee0a62e236f44ddbU, 0xf3c4fe1d5edb2345U, 0xda8bf44e1148140U, 0xe5cdccfedfb71f52U, - 0xe6281f300ec83cd1U, 0x70f1ddeb60c4d614U, 0x2af54dde1030f536U, 0x7ad62628f61b7fedU, - 0xf4f89b62f5b0e813U, 0xdda124381a87b67bU, 0x24d233cde5d2c71aU, 0x48c6cae1be381c2dU, - 0x1f2ff81802c9b6daU, 0xde066be520d32bb4U, 0x1b409d059ce3012U, 0x21c2cd51f7f0de48U, - 0xd3d1c807f1c82331U, 0xa23d282e2fbc089fU, 0xfbc8e0e52fccbbbfU, 0x44c230c731afed12U, - 0xffc4433eddf731e5U, 0xe5f6ad6207aae7f8U, 0x8a811a787f81d87fU, 0x1381318181b68111U, - 0x7f818181817f7f7fU, 0x7fbded5c46a381dbU, 0xd41572cf7f817f81U, 0x288f7fea7f947f7fU, - 0xd7d4c178U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x0U, 0x0U, - 0x0U, 0x0U, 0x2fbe3c9200000000U, 0xb93c4c0ee75d8846U, - 0xb34900453b67f70bU, 0x4ada07d81d64cab7U, 0xff3b06b01119c6beU, 0x71e7fbae62afb9fU, - 0x402a1932d7e7e6e1U, 0x1ba2cd8f781e53bU, 0x704f107dc250500U, 0x5ebba0125f5fc01U, - 0xd0d0efbef260f13U, 0xfd00e4edf1fffffeU, 0x40efeffdf9c6414U, 0xd460d85d18d60afaU, - 0x12aa81fc059bf012U, 0x6da23f6dcb2cfc1U, 0x20109247b2a36529U, 0xf2871135dcd8fccfU, - 0xd605e51f9bdfd715U, 0x15fff7df2736160eU, 0x2d0365ba13ec9e67U, 0xde53cc5f26e6c7f3U, - 0xeaf4b81737cdbdd5U, 0xc2024c24d7df13f5U, 0x49cc8138054c8f37U, 0x2a0a1b37cfb40034U, - 0xc87fcf43a4ae00b0U, 0x38d2bceb243e0ec7U, 0xaa306bcdec3ebd6U, 0xdd28ce20cca04a38U, - 0xd5d70d38c4d96209U, 0xc034ef0f0adec820U, 0xdae6da86484c201eU, 0x1cdef90fdebb0c20U, - 0xe4e5f2c42d2f00eeU, 0xdd050652eaf910b3U, 0xbadb23040250cd56U, 0xeadd1a36812f0b4dU, - 0x37281217b594fe1eU, 0xe2d5d372dcdcdc16U, 0xf0248fff04e9f3aeU, 0x47e530dcd41ce981U, - 0xed1a891dcab8f90dU, 0xfd32f444d5e609f4U, 0xbea22e0cb7e3cb20U, 0xfecfce141240f05U, - 0x2a548cafa93c85fU, 0x6ecef1be9350600U, 0xf1a8043ff3fe03U, 0xfd0f0c08e22c171bU, - 0xfc00e2eff502fb07U, 0x705fdfeda81710fU, 0x5b05368117c009f7U, 0xdd283921e242a053U, - 0xa3500a161a34f710U, 0x4bd715e84021f0ceU, 0x2f2cdb9b4415a2cfU, 0x2d3a53ddec2443bdU, - 0x25311c5fa9c3eec6U, 0x199dc521c123f20cU, 0xe1a8ec8c22d0b7f3U, 0xafb16643f6fc26c9U, - 0xccde15ed0b348145U, 0x92dbf71aa7a12560U, 0x31431911c0e9d45eU, 0x540e1e90f104dae9U, - 0xc6104621d850a95cU, 0x815520401620fa25U, 0x3ec402d6463de1a3U, 0x2c2cf28253079de0U, - 0x3b5628e6f5332aa1U, 0x35411e62a48ce5c1U, 0x27076eeee663b11cU, 0xd7fdce6d11c0fbf3U, - 0x13ef10fb10bfc2c6U, 0xd4f64d2ef6e041f4U, 0x55c4a91307d0810cU, 0x39071b1dded6cc2eU, - 0x22ac523a8bbf5b7U, 0x15b3f3f41d023719U, 0x7d2bbead8dfb253U, 0xfced49ee06cd14f2U, - 0x120d9e1be1ea2528U, 0xff04c94d4edc8108U, 0xa8e9f6dd2bff141dU, 0x241929d1f179be38U, - 0xd9cde70345aecee8U, 0xaac2552f3abafea7U, 0xc6d55926fa19d221U, 0x2ddbbc20ffb4f26cU, - 0x4f401626ca1b0411U, 0xf32d9af1cde5d681U, 0x54ae0ee03a9e5d15U, 0xe1d2bbb1c9aeec52U, - 0xdefa481cf7dd3024U, 0xbdc8aa09b8e23519U, 0xfc09812653c90643U, 0xa1cecfe12310143bU, - 0x31f51521d227b74fU, 0x9da4bb1d4e8193e0U, 0xb8bc3552d4e5d19dU, 0x8ed61a401b309c55U, - 0x1aa8c373d6e3ca46U, 0x5d3c1d35c1149174U, 0x2f966db8affec5d9U, 0x11453722e346b038U, - 0xc14909063e1bfe0eU, 0x25d7f2d63359eb3fU, 0x414c7ef0bfdd382U, 0x3fe7fb8d7302bc2U, - 0x4227175aeadefbdeU, 0x1fa51c2ae0e820b9U, 0xb0c10ad749f411ddU, 0xcfe21452a717eca6U, - 0xa9d7483ce858f46eU, 0x17be294d81a4d018U, 0x2841113ad8dbc621U, 0xb478ed11cfecb5ffU, - 0x5dd5bee22c96522cU, 0x94effcc0948cefbfU, 0x192fa17b9cac3367U, 0x8bd62749b2c02441U, - 0xc8038165eb9df568U, 0xb1f5dc12353d172eU, 0xffb736d3f69cd243U, 0x16fef01ae33c0500U, - 0xfab20532eff3f1U, 0x110f05e93327f9U, 0xb15dde3fbfdfb00U, 0xff0bfe00d5815826U, - 0xf236d3ea19be0cf5U, 0x430327d42cdd602bU, 0xe109db9dbdc6f434U, 0xd85f1c2c01ea1e37U, - 0x81e39808a3d3453fU, 0xc4f8b24555ca2731U, 0xb3c0b7e93e14203dU, 0x9ba012abc52cb42U, - 0xcbccba2044c5aee9U, 0xf4811443aee4eee4U, 0xb8e620e83118f84dU, 0x16aea546e8fde025U, - 0x37f4152cdf10bf3dU, 0x7a2b1eb6b522f92eU, 0xd0595b1ade79015bU, 0xca1d0a5c2374f60cU, - 0x2ab730ad4c66f7b3U, 0x267f389a5e04d748U, 0x3d30cbb5223947f7U, 0x2722e837bbb5e1d4U, - 0x1fb66231e433e0ffU, 0xc0aa00c846c8ece2U, 0xd2ce332bd8e2fcd2U, 0xb6d629390119d44eU, - 0x1fc4075c96c0b626U, 0x17440f33f9f98135U, 0xeb7f816fcad8cdebU, 0x48828cee26073bd2U, - 0x14dff6c0bebdb8b7U, 0xf917bd0bacc04245U, 0xffe1c73aadce4feaU, 0xa2ddb34125d1a93fU, - 0xabd7de9f39271a26U, 0xde6b9a2527a76c87U, 0x3204f6de2f183d1fU, 0x28391340a37f1804U, - 0xdc12b9a2fdc318c0U, 0xcc4f5aa61e1bb806U, 0xc0d2feca1e2770cdU, 0x4ca843ac383d2442U, - 0xba2e5814ed449d23U, 0xcf3bfd1e2d3ef71fU, 0x38edebe6215dd2e9U, 0xf531f4ba17fcc0a4U, - 0x10027fc6ed1f26a9U, 0x3c240d41eaeff0d3U, 0xe355994844cd3181U, 0x1456fb24c1394615U, - 0x324ac8ea9e640d2aU, 0x590ca7ca37ee07cbU, 0xee1d3a9d2440f69fU, 0xd3d2f0d80c4062beU, - 0xc963af2621431377U, 0x4fb2c3ea23e643fbU, 0xd9c4f3d5ca8df315U, 0xf615ea32badf3e4cU, - 0xdad8175bb7d1202dU, 0xc92c814810bbe442U, 0xb8ded9e3523d201eU, 0x30e618e6e0e1ea0eU, - 0xc800f5163c472fddU, 0xeb3ef46bfffaccadU, 0xb1e54d59dd5b6a32U, 0x45c31a2fb2158f13U, - 0x341e1d3ab081ff32U, 0xc141ee11c5b4c2ddU, 0x3ee0bce62bac332bU, 0xb20425c7c89306b3U, - 0x2743c260c0c73761U, 0x81ed0f48c5d21d19U, 0xc7e9a22fe1ce2333U, 0xd803e0092638162fU, - 0x252857b7d0458c5cU, 0xe7fbb71e1baac4f4U, 0xd8b0562649b8dea2U, 0xc6e45ce3050be104U, - 0x20df972334f3ec6fU, 0x55311319a208f53eU, 0x1abbdc8f681U, 0x63bffffe388U, - 0x2af700000597U, 0x53d00000951U, 0xfffffe9bffffe233U, 0xfffffd3500000b1eU, - 0x13900000634U, 0x72c00001d39U, 0xfffffd4200000ca0U, 0x8a100000629U, - 0xa90ffffe4f9U, 0x1fa700000325U, 0x106700000a7fU, 0xfffffe34fffffe8eU, - 0x15f7fffffee2U, 0x74900000c92U, 0xd4d8c82c00001318U, 0xeed6c30427b832c9U, - 0xe51ff52a40323392U, 0xda02ffdfe795b6a5U, 0xc5e8d92bc4e992e2U, 0xfc20e0ea28b9ee22U, - 0x32142906e181dfdaU, 0xf504c003d914c7e5U, 0x304dbedd0dd2590U, 0x1c011b0103f8050eU, - 0xda2129d31132111fU, 0x3c3ed332a163023U, 0xb71634fd1dU, 0x24dfffff2a2U, -}; - - -ai_handle g_sww_model_weights_table[1 + 2] = { - AI_HANDLE_PTR(AI_MAGIC_MARKER), - AI_HANDLE_PTR(s_sww_model_weights_array_u64), - AI_HANDLE_PTR(AI_MAGIC_MARKER), -}; - diff --git a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model_generate_report.txt b/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model_generate_report.txt deleted file mode 100644 index 795716b5..00000000 --- a/benchmark/reference_submissions/streaming_wakeword/sww_testing_l4r5zi/X-CUBE-AI/App/sww_model_generate_report.txt +++ /dev/null @@ -1,240 +0,0 @@ -ST Edge AI Core v1.0.0-19899 -Created date : 2025-01-19 06:26:52 -Parameters : generate --target stm32l4 --name sww_model -m /Users/jeremy/dev/tiny_mlperf/tiny_jhsyn/benchmark/training/streaming_wakeword/trained_models/strm_ww_int8.tflite --compression none --verbosity 1 --allocate-inputs --allocate-outputs --workspace /var/folders/qb/jcjkm0nx4878vyqfjy786xdh0000gn/T/mxAI_workspace27583291741674848973423960786911 --output /Users/jeremy/.stm32cubemx/sww_model_output - -Exec/report summary (generate) -------------------------------------------------------------------------------------------------------------------------------------------- -model file : /Users/jeremy/dev/tiny_mlperf/tiny_jhsyn/benchmark/training/streaming_wakeword/trained_models/strm_ww_int8.tflite -type : tflite -c_name : sww_model -compression : none -options : allocate-inputs, allocate-outputs -optimization : balanced -target/series : stm32l4 -workspace dir : /var/folders/qb/jcjkm0nx4878vyqfjy786xdh0000gn/T/mxAI_workspace27583291741674848973423960786911 -output dir : /Users/jeremy/.stm32cubemx/sww_model_output -model_fmt : ss/sa per channel -model_name : strm_ww_int8 -model_hash : 0x11c3f8bb3c26578a427b600d2c3795e0 -params # : 46,883 items (48.25 KiB) -------------------------------------------------------------------------------------------------------------------------------------------- -input 1/1 : 'serving_default_input_10', int8(1x30x1x40), 1.17 KBytes, QLinear(0.003701043,-128,int8), activations -output 1/1 : 'nl_10', int8(1x3), 3 Bytes, QLinear(0.003906250,-128,int8), activations -macc : 652,551 -weights (ro) : 23,520 B (22.97 KiB) (1 segment) / -164,012(-87.5%) vs float model -activations (rw) : 5,836 B (5.70 KiB) (1 segment) * -ram (total) : 5,836 B (5.70 KiB) = 5,836 + 0 + 0 -------------------------------------------------------------------------------------------------------------------------------------------- -(*) 'input'/'output' buffers can be used from the activations buffer - -Model name - strm_ww_int8 ------- ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- ----------------- ----------------- --------------------- -m_id layer (type,original) oshape param/size macc connected to | c_size c_macc c_type ------- ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- ----------------- ----------------- --------------------- -0 serving_default_input_10 (Input, ) [b:1,h:30,w:1,c:40] | +280(+100.0%) +3,400(+100.0%) Conv2D_[0] - conv2d_0 (Conv2D, DEPTHWISE_CONV_2D) [b:1,h:28,w:1,c:40] 160/280 3,400 serving_default_input_10 | -280(-100.0%) -3,400(-100.0%) ------- ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- ----------------- ----------------- --------------------- -1 conv2d_1 (Conv2D, CONV_2D) [b:1,h:28,w:1,c:128] 5,248/5,632 143,488 conv2d_0 | -880(-15.6%) -2,242(-1.6%) Conv2D_[1] - nl_1_nl (Nonlinearity, CONV_2D) [b:1,h:28,w:1,c:128] 3,584 conv2d_1 | -3,584(-100.0%) ------- ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- ----------------- ----------------- --------------------- -2 conv2d_2 (Conv2D, DEPTHWISE_CONV_2D) [b:1,h:24,w:1,c:128] 768/1,152 15,488 nl_1_nl | -180(-15.6%) -2,420(-15.6%) Conv2D_[2] ------- ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- ----------------- ----------------- --------------------- -3 conv2d_3 (Conv2D, CONV_2D) [b:1,h:24,w:1,c:128] 16,512/16,896 393,344 conv2d_2 | -7,824(-46.3%) -66,626(-16.9%) Conv2D_[3] - nl_3_nl (Nonlinearity, CONV_2D) [b:1,h:24,w:1,c:128] 3,072 conv2d_3 | -3,072(-100.0%) ------- ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- ----------------- ----------------- --------------------- -4 conv2d_4 (Conv2D, DEPTHWISE_CONV_2D) [b:1,h:15,w:1,c:128] 1,408/1,792 19,328 nl_3_nl | -658(-36.7%) -7,097(-36.7%) Conv2D_[4] ------- ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- ----------------- ----------------- --------------------- -5 conv2d_5 (Conv2D, CONV_2D) [b:1,h:15,w:1,c:128] 16,512/16,896 245,888 conv2d_4 | -12,476(-73.8%) -92,672(-37.7%) Conv2D_[5] - nl_5_nl (Nonlinearity, CONV_2D) [b:1,h:15,w:1,c:128] 1,920 conv2d_5 | -1,920(-100.0%) ------- ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- ----------------- ----------------- --------------------- -6 conv2d_6 (Conv2D, DEPTHWISE_CONV_2D) [b:1,h:1,w:1,c:128] 2,048/2,432 2,048 nl_5_nl | -1,444(-59.4%) -1,216(-59.4%) Conv2D_[6] ------- ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- ----------------- ----------------- --------------------- -7 conv2d_7 (Conv2D, CONV_2D) [b:1,h:1,w:1,c:32] 4,128/4,224 4,128 conv2d_6 | -2,432(-57.6%) -2,432(-58.9%) Conv2D_[7] - nl_7_nl (Nonlinearity, CONV_2D) [b:1,h:1,w:1,c:32] 32 conv2d_7 | -32(-100.0%) ------- ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- ----------------- ----------------- --------------------- -8 reshape_8 (Reshape, RESHAPE) [b:1,c:32] nl_7_nl | ------- ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- ----------------- ----------------- --------------------- -9 model_dense_MatMul (Placeholder, ) [h:3,c:32] 96/96 | +12(+12.5%) +99(+100.0%) Dense_[8] - model_dense_BiasAdd_ReadVariableOp (Placeholder, ) [c:3] 3/12 | -12(-100.0%) - gemm_9 (Gemm, FULLY_CONNECTED) [b:1,c:3] 99 reshape_8 | -99(-100.0%) - model_dense_MatMul | - model_dense_BiasAdd_ReadVariableOp | ------- ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- ----------------- ----------------- --------------------- -10 nl_10 (Nonlinearity, SOFTMAX) [b:1,c:3] 45 gemm_9 | Nonlinearity_[o][9] ------- ---------------------------------------------------- ---------------------- --------------- --------- ------------------------------------ --- ----------------- ----------------- --------------------- -model/c-model: macc=835,864/652,551 -183,313(-21.9%) weights=49,412/23,520 -25,892(-52.4%) activations=--/5,836 io=--/0 - - - -Generated C-graph summary ------------------------------------------------------------------------------------------------------------------------- -model name : strm_ww_int8 -c-name : sww_model -c-node # : 10 -c-array # : 39 -activations size : 5836 (1 segment) -weights size : 23520 (1 segment) -macc : 652551 -inputs : ['serving_default_input_10_output'] -outputs : ['nl_10_output'] - -C-Arrays (39) ------- --------------------------------- ----------- ------------------------- ----------- --------- -c_id name (*_array) item/size domain/mem-pool c-type comment ------- --------------------------------- ----------- ------------------------- ----------- --------- -0 conv2d_0_bias 40/160 weights/weights const s32 -1 conv2d_0_output 1120/1120 activations/**default** s8 -2 conv2d_0_scratch0 761/761 activations/**default** s8 -3 conv2d_0_weights 120/120 weights/weights const s8 -4 conv2d_1_bias 108/432 weights/weights const s32 -5 conv2d_1_output 3024/3024 activations/**default** s8 -6 conv2d_1_scratch0 1240/1240 activations/**default** s8 -7 conv2d_1_weights 4320/4320 weights/weights const s8 -8 conv2d_2_bias 108/432 weights/weights const s32 -9 conv2d_2_output 2592/2592 activations/**default** s8 -10 conv2d_2_scratch0 2701/2701 activations/**default** s8 -11 conv2d_2_weights 540/540 weights/weights const s8 -12 conv2d_3_bias 81/324 weights/weights const s32 -13 conv2d_3_output 1944/1944 activations/**default** s8 -14 conv2d_3_scratch0 1242/1242 activations/**default** s8 -15 conv2d_3_weights 8748/8748 weights/weights const s8 -16 conv2d_4_bias 81/324 weights/weights const s32 -17 conv2d_4_output 1215/1215 activations/**default** s8 -18 conv2d_4_scratch0 3241/3241 activations/**default** s8 -19 conv2d_4_weights 810/810 weights/weights const s8 -20 conv2d_5_bias 52/208 weights/weights const s32 -21 conv2d_5_output 780/780 activations/**default** s8 -22 conv2d_5_scratch0 844/844 activations/**default** s8 -23 conv2d_5_weights 4212/4212 weights/weights const s8 -24 conv2d_6_bias 52/208 weights/weights const s32 -25 conv2d_6_output 52/52 activations/**default** s8 -26 conv2d_6_scratch0 2861/2861 activations/**default** s8 -27 conv2d_6_weights 780/780 weights/weights const s8 -28 conv2d_7_bias 32/128 weights/weights const s32 -29 conv2d_7_output 32/32 activations/**default** s8 -30 conv2d_7_scratch0 528/528 activations/**default** s8 -31 conv2d_7_weights 1664/1664 weights/weights const s8 -32 gemm_9_bias 3/12 weights/weights const s32 -33 gemm_9_output 3/3 activations/**default** s8 -34 gemm_9_scratch0 32/64 activations/**default** s16 -35 gemm_9_weights 96/96 weights/weights const s8 -36 nl_10_output 3/3 activations/**default** s8 /output -37 nl_10_scratch0 124/496 activations/**default** s32 -38 serving_default_input_10_output 1200/1200 activations/**default** s8 /input ------- --------------------------------- ----------- ------------------------- ----------- --------- - -C-Layers (10) ------- ---------------- ---- --------------- -------- ------ ------------------------------------ ----------------------- -c_id name (*_layer) id layer_type macc rom tensors shape (array id) ------- ---------------- ---- --------------- -------- ------ ------------------------------------ ----------------------- -0 conv2d_0 0 Conv2D 3400 280 I: serving_default_input_10_output int8(1x30x1x40) (38) - S: conv2d_0_scratch0 - W: conv2d_0_weights int8(1x3x1x40) (3) - W: conv2d_0_bias int32(40) (0) - O: conv2d_0_output int8(1x28x1x40) (1) ------- ---------------- ---- --------------- -------- ------ ------------------------------------ ----------------------- -1 conv2d_1 1 Conv2D 141246 4752 I: conv2d_0_output int8(1x28x1x40) (1) - S: conv2d_1_scratch0 - W: conv2d_1_weights int8(108x1x1x40) (7) - W: conv2d_1_bias int32(108) (4) - O: conv2d_1_output int8(1x28x1x108) (5) ------- ---------------- ---- --------------- -------- ------ ------------------------------------ ----------------------- -2 conv2d_2 2 Conv2D 13068 972 I: conv2d_1_output int8(1x28x1x108) (5) - S: conv2d_2_scratch0 - W: conv2d_2_weights int8(1x5x1x108) (11) - W: conv2d_2_bias int32(108) (8) - O: conv2d_2_output int8(1x24x1x108) (9) ------- ---------------- ---- --------------- -------- ------ ------------------------------------ ----------------------- -3 conv2d_3 3 Conv2D 326718 9072 I: conv2d_2_output int8(1x24x1x108) (9) - S: conv2d_3_scratch0 - W: conv2d_3_weights int8(81x1x1x108) (15) - W: conv2d_3_bias int32(81) (12) - O: conv2d_3_output int8(1x24x1x81) (13) ------- ---------------- ---- --------------- -------- ------ ------------------------------------ ----------------------- -4 conv2d_4 4 Conv2D 12231 1134 I: conv2d_3_output int8(1x24x1x81) (13) - S: conv2d_4_scratch0 - W: conv2d_4_weights int8(1x10x1x81) (19) - W: conv2d_4_bias int32(81) (16) - O: conv2d_4_output int8(1x15x1x81) (17) ------- ---------------- ---- --------------- -------- ------ ------------------------------------ ----------------------- -5 conv2d_5 5 Conv2D 153216 4420 I: conv2d_4_output int8(1x15x1x81) (17) - S: conv2d_5_scratch0 - W: conv2d_5_weights int8(52x1x1x81) (23) - W: conv2d_5_bias int32(52) (20) - O: conv2d_5_output int8(1x15x1x52) (21) ------- ---------------- ---- --------------- -------- ------ ------------------------------------ ----------------------- -6 conv2d_6 6 Conv2D 832 988 I: conv2d_5_output int8(1x15x1x52) (21) - S: conv2d_6_scratch0 - W: conv2d_6_weights int8(1x15x1x52) (27) - W: conv2d_6_bias int32(52) (24) - O: conv2d_6_output int8(1x1x1x52) (25) ------- ---------------- ---- --------------- -------- ------ ------------------------------------ ----------------------- -7 conv2d_7 7 Conv2D 1696 1792 I: conv2d_6_output int8(1x1x1x52) (25) - S: conv2d_7_scratch0 - W: conv2d_7_weights int8(32x1x1x52) (31) - W: conv2d_7_bias int32(32) (28) - O: conv2d_7_output int8(1x1x1x32) (29) ------- ---------------- ---- --------------- -------- ------ ------------------------------------ ----------------------- -8 gemm_9 9 Dense 99 108 I: conv2d_7_output int8(1x1x1x32) (29) - S: gemm_9_scratch0 - W: gemm_9_weights int8(3x32) (35) - W: gemm_9_bias int32(3) (32) - O: gemm_9_output int8(1x3) (33) ------- ---------------- ---- --------------- -------- ------ ------------------------------------ ----------------------- -9 nl_10 10 Nonlinearity 45 0 I: gemm_9_output int8(1x3) (33) - S: nl_10_scratch0 - O: nl_10_output int8(1x3) (36) ------- ---------------- ---- --------------- -------- ------ ------------------------------------ ----------------------- - - - -Number of operations per c-layer -------- ------ ---------------------- --------- ------------ -c_id m_id name (type) #op type -------- ------ ---------------------- --------- ------------ -0 0 conv2d_0 (Conv2D) 3,400 smul_s8_s8 -1 1 conv2d_1 (Conv2D) 141,246 smul_s8_s8 -2 2 conv2d_2 (Conv2D) 13,068 smul_s8_s8 -3 3 conv2d_3 (Conv2D) 326,718 smul_s8_s8 -4 4 conv2d_4 (Conv2D) 12,231 smul_s8_s8 -5 5 conv2d_5 (Conv2D) 153,216 smul_s8_s8 -6 6 conv2d_6 (Conv2D) 832 smul_s8_s8 -7 7 conv2d_7 (Conv2D) 1,696 smul_s8_s8 -8 9 gemm_9 (Dense) 99 smul_s8_s8 -9 10 nl_10 (Nonlinearity) 45 op_s8_s8 -------- ------ ---------------------- --------- ------------ -total 652,551 - -Number of operation types ----------------- --------- ----------- -operation type # % ----------------- --------- ----------- -smul_s8_s8 652,506 100.0% -op_s8_s8 45 0.0% - -Complexity report (model) ------- -------------------------- ------------------------- ------------------------- ------ -m_id name c_macc c_rom c_id ------- -------------------------- ------------------------- ------------------------- ------ -0 serving_default_input_10 | 0.5% | 1.2% [0] -1 conv2d_1 ||||||| 21.6% |||||||| 20.2% [1] -2 conv2d_2 | 2.0% || 4.1% [2] -3 conv2d_3 |||||||||||||||| 50.1% |||||||||||||||| 38.6% [3] -4 conv2d_4 | 1.9% || 4.8% [4] -5 conv2d_5 |||||||| 23.5% |||||||| 18.8% [5] -6 conv2d_6 | 0.1% || 4.2% [6] -7 conv2d_7 | 0.3% ||| 7.6% [7] -9 model_dense_MatMul | 0.0% | 0.5% [8] -10 nl_10 | 0.0% | 0.0% [9] ------- -------------------------- ------------------------- ------------------------- ------ -macc=652,551 weights=23,520 act=5,836 ram_io=0 - -Generated files (7) ---------------------------------------------------------------------- -/Users/jeremy/.stm32cubemx/sww_model_output/sww_model_data_params.h -/Users/jeremy/.stm32cubemx/sww_model_output/sww_model_data_params.c -/Users/jeremy/.stm32cubemx/sww_model_output/sww_model_data.h -/Users/jeremy/.stm32cubemx/sww_model_output/sww_model_data.c -/Users/jeremy/.stm32cubemx/sww_model_output/sww_model_config.h -/Users/jeremy/.stm32cubemx/sww_model_output/sww_model.h -/Users/jeremy/.stm32cubemx/sww_model_output/sww_model.c diff --git a/benchmark/runner/.gitignore b/benchmark/runner/.gitignore index 60bf3bdf..8c028b77 100644 --- a/benchmark/runner/.gitignore +++ b/benchmark/runner/.gitignore @@ -2,3 +2,4 @@ datasets venv +*.log diff --git a/benchmark/runner/README.md b/benchmark/runner/README.md index 18bf2477..86af4b71 100644 --- a/benchmark/runner/README.md +++ b/benchmark/runner/README.md @@ -1,18 +1,135 @@ [[_TOC_]] +## General Operation +The runner software in this directory coordinates the running of the MLPerf Tiny benchmarks. It communicates with the DUT, either directly or through the interface board, as well as with the power monitoring device (e.g. LPM01a, optional except for energy benchmarks) to transmit test data and collect results. The required connections are described below. The outputs are recorded to a directory "./sessions/YYYYMMDD_HHMMSS/", where YYYYMMDD_HHMMSS is a timestamp. Messages to and from the connected devices are recorded to "log.txt" in that directory. The results for submission are in "results.txt" and additional results data is recorded in "results.json" in case additional analysis is desired. + +The main executable is "main.py" and the command line options can be seen by running `main.py --help`. The options are mainly provided through two yaml files, which describe the devices and the test(s) to be run, respectively. + +## Environment +In addition to the python libraries listed in `benchmark/training/streaming_wakeword/requirements.txt`, the runner requires pyusb and libusb. This dependency is required in order to support the JouleScope JS220, whose USB interface does not behave like a virtual serial port, unlike the LPM01a. +* **libusb** is the underlying library used to communicate with USB devices. + * On Windows see [here](https://github.com/pyusb/pyusb/blob/master/docs/faq.rst#how-do-i-install-libusb-on-windows) for installation guidance. + * On a Mac install it with `$ brew install libusb` (if you have homebrew installed). + * pyusb will only work with a native libusb library. So if you have an M1/Mx Mac and you have previously installed an x86 version of libusb under Rosetta (typically in `/usr/local/lib/libusb-x.y.z.dylib`) that appears before the native libraries in python's library search order, it will cause a `No backend available` error. + * STM32 Cube IDE on an M1 Mac installs the Rosetta files, so if you are using that for STM32 development (e.g. if you want to compile the SWW reference or the interface software), you cannot delete the files. It will cause a "No ST-Link found" error. You can direct python to prioritize the native library by running the code with the `DYLD_LIBRARY_PATH` variable set. + `DYLD_LIBRARY_PATH=/opt/homebrew/lib python main.py ...`. + * On Linux it should already be installed with most distributions. +* **pyusb** is a python wrapper to libusb. It should typically install with `python -m pip install pyusb` + * See the package [FAQ](https://github.com/pyusb/pyusb/blob/master/docs/faq.rst) for troubleshooting tips. +* If you are using the JouleScope you will also need to install its python API, pyjoulescope, with `python -m pip install joulescope`. See [this page](https://joulescope.readthedocs.io/en/latest/user/install.html) for more information. + + + +## Configuration Files + +### `devices.yaml` +Specified by the command line option `-d` or `--device_list`, this yaml file lists all of the devices used in the test, specifically the energy monitor board, the DUT, and the interface board. Defaults to `devices.yaml`, which is the default/example file is provided in the repo. Each device has several attributes: +* **name** Largely arbitrary but should be unique within the yaml file. +* **type** Either `interface`, `power`, or `dut`. +* **preference** If there are multiple interface boards connected and specified in the file, the one with the _highest_ preference will be used. +* **echo** Optional, defaults to False. If set to True, all of the commands sent to and received from this device will be printed to the terminal and recorded to the log file. +* **baud** The baud rate between this device and its immediate upstream connection. I.e. for the power manager or the interface board, this is the baud rate of connection between that device and the host. For the DUT, this is the baud rate between the DUT and either the host (for a direct connection) or the interface board (for an indirect connection). +* usb: A pair of hex values specifying the VID and PID of the devices usb connection. + +### `tests.yaml` + + +## Communications +### Host <==> DUT +For performance and accuracy tests, the host can be directly connected to the DUT. The baud rate is configurable by setting the `baud` parameter in the appropriate element in `devices.yaml`. The baud rate can either be a single integer baud rate, which will be used for all tests, or a dictionary with keys `energy`, `performance`, `accuracy`. The default `devices.yaml` included in this repo uses the dictionary for the L4R5zi reference DUT. If you need different baud rates for different benchmarks (e.g. for anomaly detection vs. streaming wakeword) you can use different devices files (e.g. `devices_ad.yaml` and `devices_sww.yaml`) and pass them on the command line using the `--device_list` flag. + +### Host <==> Interface Board +The host communicates with the interface board via a 115200 baud virtual serial port over USB. + +### Interface Board <==> DUT +For the energy mode measurements, the interface board communicates with the DUT over a UART. + +## Performance/Accuracy Metrics +### Device Configurations +Connect just the device (L4R5ZI) to the computer +### Step 1: Update the Baud Rate +Ensure the DUT board has a file attached and note its **BAUD rate**. +In `device_under_test.py`, update **line 9** to reflect this baud rate. + +### Step 2: Run a Test Trial +Each test trial will be stored in a log file in the local folder. + + +#### Run the Test in PowerShell: +```powershell +python main.py --dataset_path=C:\Your\Dataset\Path --mode=p +``` + +Mode for accuracy is a, mode for performance is p. This needs to be lowercase and we default to accuracy. + +The dataset path is the location of the dataset files. If you have used the EEMBC runner previously the dataset files would have a path like `${HOME}$/eembc/runner/benchmarks/ulp-mlperf/datasets`. Under the datasets directory you should have subdirectories for each of the benchmarks: ad01 (anomaly detection), ic01 (image classification), kws01 (keyword spotting), vww01 (visual wakeword), sww01 (streaming wakeword). + +#### Running Specific Benchmarks + +* Image Classification + * Energy: `python main.py --dataset_path=/path/to/datasets/ --test_script=tests_energy.yaml --device_list=devices_kws_ic_vww.yaml --mode=e` + * Performance: `python main.py --dataset_path=/path/to/datasets/ --test_script=tests_performance.yaml --device_list=devices_kws_ic_vww.yaml --mode=p` + * Accuracy: `python main.py --dataset_path=/path/to/datasets/ --test_script=tests_accuracy.yaml --device_list=devices_kws_ic_vww.yaml --mode=a` +* Keyword Spotting + * Energy: `python main.py --dataset_path=/path/to/datasets/ --test_script=tests_energy.yaml --device_list=devices_kws_ic_vww.yaml --mode=e` + * Performance: `python main.py --dataset_path=/path/to/datasets/ --test_script=tests_performance.yaml --device_list=devices_kws_ic_vww.yaml --mode=p` + * Accuracy: `python main.py --dataset_path=/path/to/datasets/ --test_script=tests_accuracy.yaml --device_list=devices_kws_ic_vww.yaml --mode=a` +* Visual Wakewords: + * Energy: `python main.py --dataset_path=/path/to/datasets/ --test_script=tests_energy.yaml --device_list=devices_kws_ic_vww.yaml --mode=e` + * Performance: `python main.py --dataset_path=/path/to/datasets/ --test_script=tests_performance.yaml --device_list=devices_kws_ic_vww.yaml --mode=p` + * Accuracy: `python main.py --dataset_path=/path/to/datasets/ --test_script=tests_accuracy.yaml --device_list=devices_kws_ic_vww.yaml --mode=a` +* Anomaly Detection: + * Energy: `python main.py --dataset_path=/path/to/datasets/ --test_script=tests_energy.yaml --device_list=devices_ad.yaml --mode=e` + * Performance: `python main.py --dataset_path=/path/to/datasets/ --test_script=tests_performance.yaml --device_list=devices_ad.yaml --mode=p` + * Accuracy: `python main.py --dataset_path=/path/to/datasets/ --test_script=tests_accuracy.yaml --device_list=devices_ad.yaml --mode=a` +* Streaming Wakeword + * SWW measures performance, accuracy, and accuracy in one run. It should be run in energy mode. + * Energy: `python main.py --dataset_path=/path/to/datasets/ --test_script=tests_energy.yaml --device_list=devices_sww.yaml --mode=e` + + ## Energy Test Connections +The hardware connections are illustrated here. Not all connections will be needed for every trial. For tests other than the audio streaming benchmark, the I2S connections, "PROCESSING", and "WW_DETECTED" can be omitted. For those tests (KWS, IC, AD, VWW) run in accuracy or performance mode, the interface board can also be removed from the system. In that scenario, the only connection needed is to connect the host to the DUT via USB. If the DUT does not have a USB connection, or you wish to use a UART that is not connected to a USB port, you can use a USB-UART bridge, such as the [FTDI Friend](https://www.adafruit.com/product/284). ### Power Board (LPM01A) -![LPM01A Wiring](img/LPM01A.jpg) +![LPM01A Wiring](img/LPM01A.png) + ### Interface Board (STM32H573I-DK) ![STM32H573I-DK Top Wiring](img/STM32H573I-DK-Top.png) ![STM32H573I-DK Bottom Wiring](img/STM32H573I-DK-Bottom.png) + +The interface board runs at 3.3V, so if the DUT is running at any other supply voltage, the logic levels must be shifted. The TXB0108, available in a [breakout board](https://www.adafruit.com/product/395) from Adafruit, support low-side voltages from 1.2V to 3.6V. + +The STM32H573I-DK board has a slot for a micro-SD card. The contents of the SD card are only required for the streaming test, but a card must be present in the interface board for it to function for any of the benchmarks. Ensure that it is formatted as an MS-DOS (FAT32) disk. A 1GB card is plenty for the current benchmarks. + ### Device Under Test (L4R5ZI) -![DUT Wiring](img/L4R5ZI.png) +![DUT Wiring](img/L4R5Zi.png) + +## Streaming Test +The streaming wakeword test is substantially different than the other benchmarks. It requires the interface board regardless of whether power is being measured in order to deliver the streaming audio over I2S. Power measurements are required for submissions, but for debugging purposes the streaming test can be run without the energy monitor. + +* **SD Card** The SD card stores the wav files that are delivered to the DUT. Copy the contents of `tiny/benchmark/runner/sd_card/` onto the SD card. +* **Data directory** Copy the contents of `tiny/benchmark/runner/sww_data_dir` into the sub-directory `sww01` under the data directory. This directory includes the primary test file `sww_long_test.json` as well as some smaller test files meant for debugging. The test file contains a json list of dicts, where each dict contains the following keys: + * "wav_file" The wav file to play for this test. It should be available on the SD card. + * "sample_rate" Sample rate of the wav file. Currently only 16kS/s has been tested. + * "length_sec" The length in seconds of the wav file. This (plus 10 seconds) sets the timeout length for the runner when it instructs the interface board to play the file. + * "detection_windows": A list of lists. Each inner list contains the starting time and ending time of one occurrence of the wakeword. + * Ex `[[1.0, 1.6476250000000001], [7.0, 7.358625]` indicates that the word is being spoken from 1.0s to 1.65s and from 7.0s to 7.36s. + * For each occurence of the wakeword the admissible detection window is defined as starting at the beginning of the occurrence and ending 1 second after the end of the occurence. Detections made within this time window are counted as true positives. If there is no detection made in this time, it is counted as a false negative (aka false rejection). + * For example, with the detection windows listed above, a detection recorded by the interface board at 2.60 s would count as a true positive, but a detection at 2.8s would count as a false positive. + * This timing was selected because the reference model has a one-second backward-looking receptive field. + * Detections made outside of the admissible detection window count as false positives. False positives are "debounced" with a 1-second interval. So if a single sound triggers multiple consecutive detections, they will collectively only count as one detection if they all occur within a one second interval. + +Steps to run the streaming benchmark: +1. Ensure the power board, the interface board, and the DUT are all connected as shown above. +2. Ensure that the SD card in the interface board holds the wav files in the `runner/sd_card` directory. +3. The json files from the `runner/sww_data_dir` directory are in `DATA_DIRECTORY/sww01`, where `DATA_DIRECTORY` will be specified with the `--dataset_path` on the command line. +4. The test you run will be determined by the `sww01.truth_file` value in `tests.yaml`. It is recommended to start with the the short test (`truth_file: sww_short_test.json`), a 10-second wav file. The current model has 2 true positive and 1 false negatives on this file. +5. Run the test with `main.py --dataset_path=DATA_DIRECTORY --test_script=tests.yaml`. +--- ## Test Runner -The test runner connects to the interface board and the power board and the dut. It will execute test scripts. -Test script is determined by the configuration of the hardware. + +The test runner connects to the **interface board**, **power board**, and **DUT**. It executes test scripts determined by the hardware configuration. ### Test Scripts `tests.yaml` #### Example @@ -28,24 +145,130 @@ Test script is determined by the configuration of the hardware. ``` #### Syntax +The script listed in `tests.yaml` uses a combination of four commands, listed below. Benchmarks will generally include a loop that repeats the test over a number of files. The `model_id` is determined by sending the `profile` command to the DUT and extracting the model string from the DUT's response. The corresponding test is then selected from `tests.yaml`. + +- `download` - Download data to the test device +- `loop` - Run the commands a specified number of times +- `infer` - Run inference for a specified number of cycles +- `stream` - Specific to the streaming benchmark. Plays the wav file listed in `truth_file`, instructs the DUT to detect wake words, and instructs the interface board to record those detections. At the end of the wav file, the interface board will transmit a list of the detection times to the host, which will calculate true positives, false positives, and false negatives. -- `download` Download data to the test device -- `loop` Run the commands a number of time -- `infer` Run inference For a number of cycles +--- ### Device Configuration `devices.yaml` -The device file defines available devices that are automatically detected by the `DeviceManager` +The device file defines available devices that are automatically detected by the `DeviceManager`. -#### `name`: The name of the device -#### `type`: the device type (`interface` or `power`) -#### `preference`: The relative importance if two are detected. Higher numbers are higher preference. -#### `usb`: `dict` where the key is `vid` and the value is a `pid` or list of `pid`s -#### `usb_description`: String to match in the USB description +#### Parameters: +- **`name`**: The name of the device +- **`type`**: The device type (`interface` or `power`) +- **`preference`**: The relative importance if two devices are detected. Higher numbers indicate higher preference. +- **`usb`**: `dict` where the key is `vid` and the value is a `pid` or a list of `pid`s. +- **`usb_description`**: A string used to match the USB description. + +--- ### Device Under Test Configuration `dut.yml` -Optionally define `baud` and `voltage` +The `dut.yml` file has been removed and incorporated into `devices.yaml`. + +--- + +## Running the File +Follow these steps to run tests on the device. + +### Step 1: Update the Baud Rate +Note the **BAUD rate** of the DUT board. +In `device_under_test.py`, update **line 9** to reflect this baud rate. Note: this setting is only respected when the DUT is connected directly to the host. When the interface board is used, the baud rate is set on the interface board. At present, the interface board must be re-compiled to change the baud rate of the interface-DUT connection. See the notes in the `interface` folder for details. + +### Step 2: Configure the Interface Board +If your **interface board** is set up correctly (reference the `interface` folder), you should have **two separate baud rates**: +- One for the DUT board connection. +- One for the computer connection. + +The host-interface baud rate defaults to 115200 but can be set by an optional 'baud' setting in the `devices.yaml` file. +As a last-resort debug method, the host-interface baud rate can also be set by modifying `io_manager.py`; update **line 6** to reflect the **computer → interface** baud rate. + +### Step 3: Verify Wiring +Double-check the wiring as per the beginning of the README. +**Note**: No I2C transmission will be used. + +For **Power Tests**, follow the energy setup images **exactly**. + +For **Accuracy/Energy Tests**: +- TX and RX wiring should be configured identically. +- Ground the interface board to the DUT board. +- Connect the **3.3V** ports of both boards. + +### Step 4: Run a Test Trial +Each test trial will be stored in a log file in the local folder. + + +#### Run the Test in PowerShell: +```powershell +python main.py --dataset_path=C:\Your\Dataset\Path --mode=e +``` + +You must define mode as e and if for some reason the PowerBoard is not detecting it will return a runtime error. +## Troubleshooting Section + +If you encounter errors while running the test, refer to the guide below. + +### General Troubleshooting +* If your device can operate on a 3.3V supply, you may find it helpful to run at 3.3V initially, and omit the level shifters. This will increase the energy consumption, but remove the level shifters as a potential problem. + +### "RuntimeError: No response to command name" +* This typically means that the host or interface board cannot communicate with the DUT, because the "name" command is the first +command sent to the DUT. Make sure that the DUT is correctly powered, the baud rate is correctly specified (noting that you may specify +different baud rates for energy/performance/accuracy modes), and that the UART wires are correctly connected if not connecting directly to the DUT. +If you're using the L4R5zi reference board, remember that the Tx/Rx lines are labeled backwards. + +### **Error: 'NoneType' Appears** +This typically indicates a **UART transmission error**. + +#### **Steps to Resolve:** +1. **Check your wiring** – Ensure all connections are correct. +2. **Run PowerShell as Administrator** – + - On Windows, this error is often caused by restricted access to Serial ports. + - Open **PowerShell** as an **administrator** and retry the test. +3. **Ensure no other application is using the device ports** – + - If another process has locked the ports, the above fixes will not work. This can often happen if you have a terminal (e.g. PuTTY) connected for debug purposes. + +### Error: SerialException or ResourceBusy +The full text of this error (at least on a Mac) is : "Exception has occurred: SerialException +device reports readiness to read but returned no data (device disconnected or multiple access on port?)". +It is typically caused by having a serial terminal (e.g. putty, picocom) open on the power manager. Similarly, if another application +has the DUT or interface board open, you may receive an error like this: "[Errno 16] could not open port /dev/cu.usbmodem1403: [Errno 16] Resource busy: '/dev/cu.usbmodem1403'" + +### Error: Power Manager did not acknowledge. +This will then often be followed with a list of strings, which are messages from the power manager, such as `['33930-08','33340-08','ack']`. If this is the case, it is typically because the power manager had messages in its output queue from a previous run. Those cause the runner to miss the acknowledgement the power manager and fail. Simply run the runner again. + +If there are no messages in the list, then the power manager may be disconnected. Make sure it is connected and powered. You may find it helpful to connect to it with a serial terminal to check that it is present and communicating. + +--- + +## FX Media Open Not Working +If `FX_FAT_READ_ERROR` is triggered, there may be **issues with the SD card or its formatting**. + +### **Formatting the SD Card (Windows)** +1. Open **Command Prompt** and type: + ```powershell + diskpart + ``` +2. This will queue up another terminal for formatting a sd device the run the following commands + ```powershell + list disk + select disk _ // Ensure you select the correct disk + clean + create partition primary + format fs=fat32 quick + assign + exit + ``` + +## I2S Audio Transfer +If the I2S transfer appears not to be working, here are a few things to try. +1. To run a shorter test, change the 'truth_file' value under the sww section to `sww_short_test.json` (10 seconds) or `sww_med_test.json` (2 minutes). +2. To reduce the number of connections, you can run the test without the power board and with the the host connected directly to the DUT's USB virtual UART, although the interface board is still necessary for delivering I2S signals. The runner will detect the connection and issue commands directly to the DUT rather than going through the interface board. This setup will also let you use the step debugger in the DUT. In this arrangement, make sure that the UART wires are disconnected so they don't contend with the USB UART and make sure the IDD jumper is in place, since the DUT is being powered through the USB connection. +3. -## Open Items -- Add start and stop playback to the script -- fix looping -- write the data out in the original format +### Baud Rate for Interface board: +Located in file /application/user/core/usart.c + diff --git a/benchmark/runner/datasets.py b/benchmark/runner/datasets.py index d343ad02..71bbcd7f 100644 --- a/benchmark/runner/datasets.py +++ b/benchmark/runner/datasets.py @@ -1,27 +1,95 @@ import csv import os from random import randrange +import json class DataSet: - def __init__(self, dataset_path, truth_file): + def __init__(self, dataset_path, truth_file, start_index=0): self._dataset_path = dataset_path self._truth_file = truth_file self._truth_data = None + self._current_index = start_index def _read_truth_file(self): if not self._truth_data: with open(os.path.join(self._dataset_path, self._truth_file)) as file: - reader = csv.DictReader(file, fieldnames=["file", "classes", "class"]) + reader = csv.DictReader(file, fieldnames=["file", "classes", "class", "bytes_to_send","stride"]) self._truth_data = [f for f in reader] + def get_num_files(self): + self._read_truth_file() + return len(self._truth_data) + def get_file_by_index(self, index): self._read_truth_file() data = [] - index = index if index is not None else randrange(len(self._truth_data)) + # if an index is not specified, use the object's _current_index and increment it, + # if one is specified, use that and don't increment _current_index + if index is not None: + inc_index = False + else: + index = self._current_index + inc_index = True + truth = None if index < len(self._truth_data): truth = self._truth_data[index] with open(os.path.join(self._dataset_path, truth.get("file")), "rb") as file: data = file.read() + if inc_index: + self._current_index += 1 + return truth, data + + +class StreamingDataSet: + def __init__(self, dataset_path, truth_file, start_index=0): + self._dataset_path = dataset_path + self._truth_file = truth_file + self._truth_data = None + self._current_index = start_index + + def _read_truth_file(self): + if not self._truth_data: + with open(os.path.join(self._dataset_path, self._truth_file)) as file: + self._truth_data = json.load(file) + for entry in self._truth_data: + if "wav_file" not in entry or "detection_windows" not in entry: + raise RuntimeError( + "The SWW truth file ({truth_file_path}) should be a list" + "of dicts, each containing keys 'wav_file' and 'detection_windows'" + ) + + def get_file_by_index(self, index): + """ + returns a dict including a filename, which should be available on the interface + board's SD card, and a list of detection windows. Each detection window is a start/stop + pair of timestamps such that a detection after t_start_i but before t_stop_i counts as + a true detection of the i'th occurence of a wakeword + {"wav_file": "filename.wav", + "detection_windows": [ + [t_start_0, t_stop_0], + [t_start_1, t_stop_1] + ] + } + """ + + self._read_truth_file() + data = [] + # if an index is not specified, use the object's _current_index and increment it, + # if one is specified, use that and don't increment _current_index + if index is not None: + inc_index = False + else: + index = self._current_index + inc_index = True + + truth = None + if index < len(self._truth_data): + truth = self._truth_data[index] # truth is a dict w/ keys "wav_file" and "detection_windows" + + if inc_index: + self._current_index += 1 + + return truth \ No newline at end of file diff --git a/benchmark/runner/device_manager.py b/benchmark/runner/device_manager.py index 0ed4f9c2..b936940c 100644 --- a/benchmark/runner/device_manager.py +++ b/benchmark/runner/device_manager.py @@ -1,76 +1,171 @@ import yaml - from serial.tools import list_ports +import serial, re +import usb.core from device_under_test import DUT from io_manager import IOManager from io_manager_enhanced import IOManagerEnhanced -from power_manager import PowerManager +from power_manager.power_manager import PowerManager +from runner_utils import get_baud_rate + +def precheck_device_name(dev_cfg, serial_device, mode): + """ + Called before constructing a device to check if a potential match provides + the correct name. Mainly used to disambiguate multiple devices with a common + USB vid and pid. If the dev_cfg does not have a "check_name" property, + return True. If the device on does not respond to the + "name%" command, or responds but the name does not match check_name return + False. If the response matches check_name, return True. + Note that this function uses teh 'check_name' property, not 'name', which + is mostly arbitrary + ** Arguments: + - dev_cfg: device configuration dict from devices.yaml + - serial_device: serial port name (e.g. "/dev/cu.usbmodel1103" on a Mac) + - mode: Test mode, "a", "p", or "e". Used to determine correct baud rate. + """ + if "check_name" not in dev_cfg: + # no check_name specified, so skip this test. + return True + baud = get_baud_rate(dev_cfg, mode=mode) + with serial.Serial(serial_device, baud, timeout=1) as port: + port.write("name%".encode()) + response = "" + while True: + # read until there is nothing available or until an undecodable character is received. + raw_char = port.read(1) + if raw_char is None or raw_char == b'': + # nothing available, so break + break + try: + char = raw_char.decode() + except UnicodeDecodeError as e: + print("WARNING: Character decoding error while pre-checking name on {serial_device}") + print(str(e)) + break + response += char + match = re.search(r"m-name-dut-\[(.*)\]", response) + if match: + received_name = match.group(1) + else: + print(f"Device on {serial_device} matches pid/vid to {dev_cfg['name']} but failed to respond to 'name%' command.") + print(f"Will not associate this device. If this is unexpected, check baud rate and connection.") + return False + + if dev_cfg["check_name"] == received_name: + return True + else: + print(f"Device on {serial_device} matches pid/vid to {dev_cfg['name']} but gave non-matching check_name {received_name} (expected {dev_cfg['check_name']}). Will not associate.") + return False class DeviceManager: - """Detects and identifis available devices attached to the host. - """ - - def __init__(self, device_defs): - self._device_defs = device_defs - - def __getitem__(self, item): - return self.__dict__[item] - - def __setitem__(self, key, value): - self.__dict__[key] = value - - def get(self, item, default=None): - return self.__dict__.get(item, default) - - def values(self): - return (a for a in self.__dict__.values() if isinstance(a, dict)) - - def _add_device(self, usb, definition): - type = definition.get("type") - if type and (not self.__dict__.get(type) - or definition.get("preference", 0) > self.__dict__[type].get("preference", 0)): - self.__dict__[type] = {k: v for k, v in definition.items()} - self.__dict__[type]["port"] = usb.device - - def _instantiate(self, definition): - args = { - "port_device": definition.get("port") - } - if definition.get("baud"): - args["baud_rate"] = definition.get("baud") - if definition.get("type") == "interface": - definition["instance"] = IOManagerEnhanced(**args) if definition.get("name") == "stm32h573i-dk" \ - else IOManager(**args) - elif definition.get("type") == "power": - definition["instance"] = PowerManager(**args) - elif definition.get("type") == "dut": - definition["instance"] = DUT(**args) - - def scan(self): - """Scan fpr USB serial devices - This scans the connected usb devices. It compares the device definitions - based on the USB vid and pid primarily and then by the text of the description. - """ - pending = [p for p in list_ports.comports(True) if p.vid] - matched = [] - for p in pending: - for d in self._device_defs: - found = False - for vid, pids in d.get("usb", {}).items(): - for pid in (pids if isinstance(pids, list) else [pids]): - if pid == p.pid and vid == p.vid: - self._add_device(p, d) - matched.append(p) - found = True - break - if found: break - for p in (a for a in pending if a not in matched): - for d in (d1 for d1 in self._device_defs if d1.get("usb_description", "zZzZzZzZ") in p.description): - self._add_device(p, d) - matched.append(p) - break - - for d in self.values(): - self._instantiate(d) + """Detects and identifies available devices attached to the host.""" + + def __init__(self, device_defs, desired_baud, mode): + self._device_defs = device_defs + self._desired_baud = desired_baud + self.mode = mode + + def __getitem__(self, item): + return self.__dict__[item] + + def __setitem__(self, key, value): + self.__dict__[key] = value + + def get(self, item, default=None): + return self.__dict__.get(item, default) + + def values(self): + return (a for a in self.__dict__.values() if isinstance(a, dict)) + + def _add_device(self, dev, definition, non_serial=False): + dev_type = definition.get("type") + if dev_type and ( + not self.__dict__.get(dev_type) + or definition.get("preference", 0) > self.__dict__[dev_type].get("preference", 0) + ): + self.__dict__[dev_type] = {k: v for k, v in definition.items()} + if not non_serial: + self.__dict__[dev_type]["port"] = dev.device + else: + self.__dict__[dev_type]["port"] = None # USB-only devices like JS220 + + def _instantiate(self, definition): + args = {} + if "port" in definition: + args["port_device"] = definition["port"] + if definition.get("baud"): + if definition.get("type") == "dut": + args["baud_rate"] = get_baud_rate(definition, self.mode) + else: + args["baud_rate"] = definition.get("baud") + if definition.get("echo"): + args["echo"] = definition["echo"] + if definition.get("voltage"): + args["voltage"] = definition["voltage"] + + dev_type = definition.get("type") + if dev_type == "interface": + if self._desired_baud: + args["dut_baud_rate"] = self._desired_baud + definition["instance"] = ( + IOManagerEnhanced(**args) if definition.get("name") == "stm32h573i-dk" else IOManager(**args) + ) + elif dev_type == "power": + if definition.get("name") == "js220": + from joulescope import scan + devices = scan() + if not devices: + raise RuntimeError("No JS220 found during instantiation") + js_device = devices[0].open() + args["js_device"] = js_device # 👈 Pass to JS220Commands via PowerManager + definition["instance"] = PowerManager(definition["name"], config=definition, **args) + elif dev_type == "dut": + definition["instance"] = DUT(**args) + + + def scan(self): + """Scan for both serial and USB-only devices and initialize them.""" + pending_serial = [p for p in list_ports.comports(True) if p.vid] + matched = [] + comport_serial_numbers = [] + + for p in pending_serial: + comport_serial_numbers.append(p.serial_number) + for d in self._device_defs: + found = False + for vid, pids in d.get("usb", {}).items(): + for pid in (pids if isinstance(pids, list) else [pids]): + if pid == p.pid and vid == p.vid and precheck_device_name(d, p.device, self.mode): + self._add_device(p, d) + matched.append(p) + found = True + break + if found: + break + + for p in (a for a in pending_serial if a not in matched): + for d in (d1 for d1 in self._device_defs if d1.get("usb_description", "zZzZzZzZ") in p.description): + self._add_device(p, d) + matched.append(p) + break + + # Additional scan for USB-only devices (non-serial) + all_usb = usb.core.find(find_all=True) + for dev in all_usb: + if dev.serial_number in comport_serial_numbers: + # we already handled this device in the loop on list_ports.comports() + continue + vid = dev.idVendor + pid = dev.idProduct + for d in self._device_defs: + for k, v in d.get("usb", {}).items(): + if isinstance(v, list): + if pid in v and vid == k: + self._add_device(dev, d, non_serial=True) + elif pid == v and vid == k: + self._add_device(dev, d, non_serial=True) + + for d in self.values(): + self._instantiate(d) diff --git a/benchmark/runner/device_under_test.py b/benchmark/runner/device_under_test.py index 0ca36e95..c8aab9b9 100644 --- a/benchmark/runner/device_under_test.py +++ b/benchmark/runner/device_under_test.py @@ -6,53 +6,76 @@ class DUT: - def __init__(self, port_device, baud_rate=115200, power_manager=None): + def __init__(self, port_device, baud_rate, power_manager=None, echo=None): interface = port_device + + port_kwargs = {"echo":echo} if echo else {} if not isinstance(port_device, InterfaceDevice): - interface = SerialDevice(port_device, baud_rate, "m-ready", '%') + interface = SerialDevice(port_device, baud_rate, "m-ready", '%', **port_kwargs) self._port = interface self.power_manager = power_manager - self._profile = None - self._model = None - self._name = None + self._profile = None # Device profile + self._model = None # Device model + self._name = None # Device name self._max_bytes = 26 if power_manager else 31 + def __enter__(self): - if self.power_manager: - self.power_manager.__enter__() + #if self.power_manager: + #self.power_manager.__enter__() self._port.__enter__() return self def __exit__(self, *args): self._port.__exit__(*args) - if self.power_manager: - self.power_manager.__exit__(*args) + #if self.power_manager: + #self.power_manager.__exit__(*args) + + def _retry(self, method, retries=3): + for attempt in range(retries): + if method(): + return + if attempt < retries - 1: + print(f"Retrying {method.__name__} ({attempt + 1}/{retries})...") def _get_name(self): + name_retrieved = False for l in self._port.send_command("name"): match = re.match(r'^m-(name)-dut-\[([^]]+)]$', l) if match: self.__setattr__(f"_{match.group(1)}", match.group(2)) + name_retrieved = True + print(f"Device name retrieved: {self._name}") # Print the name when successfully retrieved + if not name_retrieved: + print(f"WARNING: Failed to get name.") + return name_retrieved def get_name(self): if self._name is None: - self._get_name() + self._retry(self._get_name) return self._name def _get_profile(self): + profile_retrieved = False for l in self._port.send_command("profile"): match = re.match(r'^m-(model|profile)-\[([^]]+)]$', l) if match: self.__setattr__(f"_{match.group(1)}", match.group(2)) + profile_retrieved = True + if match.group(1) == "profile": + print(f"Device profile retrieved: {self._profile}") # Print the profile when successfully retrieved + elif match.group(1) == "model": + print(f"Device model retrieved: {self._model}") # Print the model when successfully retrieved + return profile_retrieved def get_model(self): if self._model is None: - self._get_profile() + self._retry(self._get_profile) return self._model def get_profile(self): if self._profile is None: - self._get_profile() + self._retry(self._get_profile) return self._profile def timestamp(self): @@ -72,16 +95,31 @@ def load(self, data): return result def infer(self, number, warmups): - command = f"infer {number}" - if warmups: - command += f" {warmups}" - if self.power_manager: - print(self.power_manager.start()) - result = self._port.send_command(command) - if self.power_manager: - print(self.power_manager.stop()) + # result = self._port.send_command("db print") + + command = f"infer {number} {warmups}" # must include warmups, even if 0, because default warmups=10 + #if self.power_manager: + #print(self.power_manager.start()) + result = self._port.send_command(command, timeout=30.0) + #if self.power_manager: + #print(self.power_manager.stop()) return result + def start_detecting(self): + command = f"start" + self._port.send_command(command) + return + + def stop_detecting(self): + command = f"stop" + response = self._port.send_command(command) + return response + + def print_detections(self): + command = f"print_detections" + self._port.send_command(command) + return + def get_help(self): return self._port.send_command("help") diff --git a/benchmark/runner/devices.yaml b/benchmark/runner/devices.yaml deleted file mode 100644 index 5b317a15..00000000 --- a/benchmark/runner/devices.yaml +++ /dev/null @@ -1,22 +0,0 @@ -- name: stm32h573i-dk - type: interface - preference: 2 - usb: - 0x0483: 0x374E -- name: arduino - type: interface - preference: 1 - usb: - 0x2341: - - 0x0043 - - 0x0001 - 0x2a03: - - 0x0043 - - 0x0243 -- name: lpm01a - usb_description: PowerShield - type: power -- name: l4r5zi - type: dut - usb: - 0x0483: 0x374B diff --git a/benchmark/runner/devices_ad.yaml b/benchmark/runner/devices_ad.yaml new file mode 100644 index 00000000..d0b665ee --- /dev/null +++ b/benchmark/runner/devices_ad.yaml @@ -0,0 +1,41 @@ +- name: stm32h573i-dk + type: interface + preference: 2 + baud: 115200 # Baud Rate for the interface (IO) board + usb: + 0x0483: 0x374E +- name: arduino + type: interface + preference: 1 + baud: 115200 # Baud Rate for the interface board + usb: + 0x2341: + - 0x0043 + - 0x0001 + 0x2a03: + - 0x0043 + - 0x0243 +- name: lpm01a + type: power + baud: 3686400 + echo: False + preference: 2 # set to higher preference thatn js220 to use lpm01a + voltage: 1.8 # <-- Voltage for DUT + usb: + 0x0483: 0x5740 # Ensures detection by VID/PID (1155 / 22336) +- name: l4r5zi + type: dut + baud: + energy: 9600 + performance: 921600 + accuracy: 921600 + usb: + 0x0483: 0x374B +- name: js220 + type: power + preference: 1 # set to higher preference thatn lpm01a to use js220 + raw_sampling_rate: 1000000 + virtual_sampling_rate: 1000 + usb: + 0x16D0: 0x10BA + diff --git a/benchmark/runner/devices_kws_ic_vww.yaml b/benchmark/runner/devices_kws_ic_vww.yaml new file mode 100644 index 00000000..c8c76905 --- /dev/null +++ b/benchmark/runner/devices_kws_ic_vww.yaml @@ -0,0 +1,41 @@ +- name: stm32h573i-dk + type: interface + preference: 2 + baud: 115200 # Baud Rate for the interface (IO) board + usb: + 0x0483: 0x374E +- name: arduino + type: interface + preference: 1 + baud: 115200 # Baud Rate for the interface board + usb: + 0x2341: + - 0x0043 + - 0x0001 + 0x2a03: + - 0x0043 + - 0x0243 +- name: lpm01a + type: power + baud: 3686400 + echo: False + preference: 2 # set to higher preference thatn js220 to use lpm01a + voltage: 1.8 # <-- Voltage for DUT + usb: + 0x0483: 0x5740 # Ensures detection by VID/PID (1155 / 22336) +- name: l4r5zi + type: dut + baud: + energy: 9600 + performance: 115200 + accuracy: 115200 + usb: + 0x0483: 0x374B +- name: js220 + type: power + preference: 1 # set to higher preference thatn lpm01a to use js220 + raw_sampling_rate: 1000000 + virtual_sampling_rate: 1000 + usb: + 0x16D0: 0x10BA + diff --git a/benchmark/runner/devices_sww.yaml b/benchmark/runner/devices_sww.yaml new file mode 100644 index 00000000..f17d69dc --- /dev/null +++ b/benchmark/runner/devices_sww.yaml @@ -0,0 +1,41 @@ +- name: stm32h573i-dk + type: interface + preference: 2 + baud: 115200 # Baud Rate for the interface (IO) board + usb: + 0x0483: 0x374E +- name: arduino + type: interface + preference: 1 + baud: 115200 # Baud Rate for the interface board + usb: + 0x2341: + - 0x0043 + - 0x0001 + 0x2a03: + - 0x0043 + - 0x0243 +- name: lpm01a + type: power + baud: 3686400 + echo: False + preference: 2 # set to higher preference thatn js220 to use lpm01a + voltage: 1.8 # <-- Voltage for DUT + usb: + 0x0483: 0x5740 # Ensures detection by VID/PID (1155 / 22336) +- name: l4r5zi + type: dut + baud: + energy: 115200 + performance: 115200 + accuracy: 115200 + usb: + 0x0483: 0x374B +- name: js220 + type: power + preference: 1 # set to higher preference thatn lpm01a to use js220 + raw_sampling_rate: 1000000 + virtual_sampling_rate: 1000 + usb: + 0x16D0: 0x10BA + diff --git a/benchmark/runner/dut.yaml b/benchmark/runner/dut.yaml deleted file mode 100644 index 292b437d..00000000 --- a/benchmark/runner/dut.yaml +++ /dev/null @@ -1 +0,0 @@ -voltage: 3000m \ No newline at end of file diff --git a/benchmark/runner/img/L4R5ZI.png b/benchmark/runner/img/L4R5ZI.png deleted file mode 100644 index 6a2c37dc..00000000 Binary files a/benchmark/runner/img/L4R5ZI.png and /dev/null differ diff --git a/benchmark/runner/img/L4R5ZI_blank.png b/benchmark/runner/img/L4R5ZI_blank.png new file mode 100644 index 00000000..e9355871 Binary files /dev/null and b/benchmark/runner/img/L4R5ZI_blank.png differ diff --git a/benchmark/runner/img/L4R5Zi.png b/benchmark/runner/img/L4R5Zi.png new file mode 100644 index 00000000..809418cd Binary files /dev/null and b/benchmark/runner/img/L4R5Zi.png differ diff --git a/benchmark/runner/img/LPM01A.jpg b/benchmark/runner/img/LPM01A.jpg deleted file mode 100644 index f31fba78..00000000 Binary files a/benchmark/runner/img/LPM01A.jpg and /dev/null differ diff --git a/benchmark/runner/img/LPM01A.png b/benchmark/runner/img/LPM01A.png new file mode 100644 index 00000000..4ff3d772 Binary files /dev/null and b/benchmark/runner/img/LPM01A.png differ diff --git a/benchmark/runner/img/STM32H573I-DK-Bottom.png b/benchmark/runner/img/STM32H573I-DK-Bottom.png index 9b20a591..9d9db0c4 100644 Binary files a/benchmark/runner/img/STM32H573I-DK-Bottom.png and b/benchmark/runner/img/STM32H573I-DK-Bottom.png differ diff --git a/benchmark/runner/img/STM32H573I-DK-Top.png b/benchmark/runner/img/STM32H573I-DK-Top.png index 0e657763..7b34d467 100644 Binary files a/benchmark/runner/img/STM32H573I-DK-Top.png and b/benchmark/runner/img/STM32H573I-DK-Top.png differ diff --git a/benchmark/runner/interface_device.py b/benchmark/runner/interface_device.py index 8755b25c..23984474 100644 --- a/benchmark/runner/interface_device.py +++ b/benchmark/runner/interface_device.py @@ -1,3 +1,3 @@ class InterfaceDevice: def send_command(self, command, end=None, echo=False): - pass + pass \ No newline at end of file diff --git a/benchmark/runner/io_manager.py b/benchmark/runner/io_manager.py index 088aeeec..e71b3236 100644 --- a/benchmark/runner/io_manager.py +++ b/benchmark/runner/io_manager.py @@ -3,14 +3,21 @@ class IOManager(InterfaceDevice): - def __init__(self, port_device, baud_rate=115200): - self.port = SerialDevice(port_device, baud_rate, "m-ready", '%') + def __init__(self, port_device, baud_rate, dut_baud_rate, echo=None): + port_kwargs = {"end_of_response":"m-ready", + "delimiter":"%" + } + if echo: + port_kwargs["echo"] = echo + + self.port = SerialDevice(port_device, baud_rate, **port_kwargs) self.entry_count = 0 + self.dut_baud_rate = dut_baud_rate def __enter__(self): if not self.entry_count: self.port.__enter__() - self.get_name() + # self.get_name() self.entry_count += 1 return self @@ -21,7 +28,7 @@ def __exit__(self, *args): def get_name(self): return self.port.send_command("name") - + def timestamp(self): return self.port.send_command("timestamp") @@ -34,11 +41,17 @@ def send_data(self, data): def read_line(self): resp = self.port.read_line() - resp = resp.replace("[dut]: ", "") + if resp is not None: + resp = resp.replace("[dut]: ", "") return resp - def send_command(self, command, end=None, echo=False): - resp = self.port.send_command(f"dut {command}") + def send_command(self, command, end=None, echo=False, timeout=None): + if timeout is not None: + port_kw_args = {'timeout':timeout} + else: + port_kw_args = {} + + resp = self.port.send_command(f"dut {command}", **port_kw_args) if len(resp) != 2 or resp[1] != "m-ready": return None resp = None @@ -63,4 +76,4 @@ def send_command(self, command, end=None, echo=False): tm 0=fall/1*=change tp [res] version firmware version - """ + """ \ No newline at end of file diff --git a/benchmark/runner/io_manager_enhanced.py b/benchmark/runner/io_manager_enhanced.py index 1245207e..c7ce785a 100644 --- a/benchmark/runner/io_manager_enhanced.py +++ b/benchmark/runner/io_manager_enhanced.py @@ -1,9 +1,14 @@ from io_manager import IOManager - +import re +import time class IOManagerEnhanced(IOManager): - def __init__(self, port_device, baud_rate=921600): - IOManager.__init__(self, port_device, baud_rate) + def __init__(self, port_device, baud_rate,dut_baud_rate, echo=False): + kw_args = {"baud_rate":baud_rate, + "dut_baud_rate":dut_baud_rate, + "echo":echo + } + IOManager.__init__(self, port_device, **kw_args) def get_files(self): return self.port.send_command('ls') @@ -11,6 +16,22 @@ def get_files(self): def get_waves(self): return [x for x in self.get_files() if x.lower().endswith("wav") or x == "m-ready"] - def play_wave(self, filename=None): + def play_wave(self, filename=None, timeout=10): command = "play" + (f" {filename}" if filename else "") + return self.port.send_command(command, timeout=timeout) # need to set this timeout longer than file length + + def record_detections(self): + command = "record_detections" + return self.port.send_command(command) + + def print_detections(self): + command = "print_detections" + return self.port.send_command(command) + + def print_dutycycle(self): + command = "print_dutycycle" return self.port.send_command(command) + + + def sync_baud(self, baud): + return self.port.send_command(f"setbaud {baud}") diff --git a/benchmark/runner/main.py b/benchmark/runner/main.py index e1036fdf..24f9b531 100644 --- a/benchmark/runner/main.py +++ b/benchmark/runner/main.py @@ -1,125 +1,371 @@ -import argparse -import os -import time -import yaml +import argparse, os, time, yaml, json, io +from datetime import datetime +import numpy as np +from sklearn.metrics import roc_auc_score +from collections import Counter +import matplotlib.pyplot as plt + +from power_manager.power_manager import PowerManager +from datasets import DataSet, StreamingDataSet -from datasets import DataSet from device_manager import DeviceManager from device_under_test import DUT -from script import Script +from script import Script, log_filename +import streaming_ww_utils as sww_util +from runner_utils import get_baud_rate, print_tee """ -Application to execute test scripts to measure power consumption, turn on amd off power, send commands to a device +Application to execute test scripts to measure power consumption, turn on and off power, send commands to a device under test. """ +def init_dut(device): + if device: + with device as dut: + time.sleep(2) + dut.get_name() + dut.get_model() + dut.get_profile() +def identify_dut(manager, desired_baud): + power = manager.get("power", {}).get("instance") + interface = manager.get("interface", {}).get("instance") -def init_dut(device): - if device: - with device as dut: - time.sleep(2) - dut.get_name() - dut.get_model() - dut.get_profile() - - -def identify_dut(manager): - interface = manager.get("interface", {}).get("instance") - power = manager.get("power", {}).get("instance") - if not manager.get("dut") and interface and power: - dut = DUT(interface, power_manager=power) - manager["dut"] = { - "instance": dut - } - else: - dut = manager.get("dut", {}).get("instance") - init_dut(dut) + # Step 2: Instantiate DUT and initialize it + if not manager.get("dut") and interface: + dut = DUT(interface, baud_rate = desired_baud, power_manager=power) + manager["dut"] = {"instance": dut} + else: + dut = manager.get("dut", {}).get("instance") + init_dut(dut) -def run_test(devices_config, dut_config, test_script, dataset_path): - """Run the test - :param devices_config: - :param dut_config: - :param test_script: - :param dataset_path: - """ - manager = DeviceManager(devices_config) - manager.scan() - power = manager.get("power", {}).get("instance") - if power and dut_config and dut_config.get("voltage"): - power.configure_voltage(dut_config["voltage"]) - identify_dut(manager) +def run_test(devices_config, dut_config, test_script, dataset_path,mode): + """Run the test - dut = manager.get("dut", {}).get("instance") - io = manager.get("interface", {}).get("instance") + :param devices_config: + :param dut_config: + :param test_script: + :param dataset_path: + """ + + desired_dut_baud = get_baud_rate(dut_config, mode) + manager = DeviceManager(devices_config, desired_dut_baud, mode) + manager.scan() + + if not any([d['type'] == 'interface' for d in manager.values()]) and not any([d['type'] == 'dut' for d in manager.values()]): + raise RuntimeError("No interface or DUT detected. One must be present to run test") - # with io: - # start_time = time.time() - # io.play_wave("cd16m.wav") - # elapsed = time.time() - start_time + power = manager.get("power", {}).get("instance") + if mode == "e" and power is None: + raise RuntimeError("ERROR: Energy mode selected but no power board was found.") + + if power and dut_config and dut_config.get("voltage"): + power.configure_voltage(dut_config["voltage"]) + if power: + power.power_on() + time.sleep(1) # let the DUT boot up + power.start() # start recording current measurements - script = Script(test_script.get(dut.get_model())) - set = DataSet(os.path.join(dataset_path, script.model), script.truth) + io = manager.get("interface", {}).get("instance") + if io: + io.__enter__() + io.sync_baud(desired_dut_baud) + + identify_dut(manager, desired_dut_baud) + dut = manager.get("dut", {}).get("instance") + dut_config['model'] = dut.get_model() + # with io: + # start_time = time.time() + # io.play_wave("cd16m.wav") + # elapsed = time.time() - start_time + + script = Script(test_script.get(dut.get_model())) + if script.model[:3] == 'sww': + set = StreamingDataSet(os.path.join(dataset_path, script.model), script.truth) + else: + set = DataSet(os.path.join(dataset_path, script.model), script.truth) + result = script.run(io, dut, set, mode) + if io: + io.__exit__() - return script.run(io, dut, set) + if not isinstance(result, list): + # if the test does not contain a loop, then result will just be a dict + # rather than a list of dicts. So make it a list + result = [result] + for r in result: + if 'power' in r: + r['power']['voltage'] = power._voltage + + return result, power def parse_device_config(device_list_file, device_yaml): - """Parsee the device discovery configuration - - :param device_list: device discovery configuration file - :param device_yaml: device description as raw yaml - """ - if device_yaml: - return yaml.load(device_yaml) - else: - with open(device_list_file) as dev_file: - return yaml.load(dev_file, Loader=yaml.CLoader) - - -def parse_dut_config(dut_cfg_file, dut_voltage, dut_baud): - """ Parse the dut configuration file and override values - - :param dut: path to device config file - :param dut_voltage: dut voltage in mV - :param dut_baud: dut baud rate - """ - config = {} - if dut: - with open(dut) as dut_file: - dut_config = yaml.load(dut_file, Loader=yaml.CLoader) - config.update(**dut_config) - if dut_voltage: - config.update(voltage=dut_voltage) - if dut_baud: - config.update(baud=dut_baud) - return config + """Parse the device discovery configuration + :param device_list: device discovery configuration file + :param device_yaml: device description as raw yaml + """ + if device_yaml: + return yaml.load(device_yaml) + else: + with open(device_list_file) as dev_file: + return yaml.load(dev_file, Loader=yaml.CLoader) def parse_test_script(test_script): - """Load the test script + """Load the test script + + :param test_script: The path to the test script definition + """ + with open(test_script) as test_file: + return yaml.load(test_file, Loader=yaml.CLoader) + +# Function to normalize probabilities +def normalize_probabilities(scores): + total = sum(scores) + return [s / total for s in scores] + +def calculate_accuracy(y_pred, labels): + # Check if y_pred has only one value per instance (Anomaly Detection case) + if y_pred.shape[1] == 1: + thresholds = np.amin(y_pred) + np.arange(0.0, 1.0, .01) * (np.amax(y_pred) - np.amin(y_pred)) + accuracy = 0 + n_normal = np.sum(labels == 0) # Assuming normal instances are labeled as 0 + + for threshold in thresholds: + y_pred_binary = (y_pred > threshold).astype(int) # Binarization + + true_negative = np.sum((y_pred_binary[labels == 0] == 0)) + false_positive = np.sum((y_pred_binary[labels == 0] == 1)) + true_positive = np.sum((y_pred_binary[labels == 1] == 1)) + false_negative = np.sum((y_pred_binary[labels == 1] == 0)) + + precision = true_positive / (true_positive + false_positive + 1e-8) # Avoid division by zero + recall = true_positive / (true_positive + false_negative + 1e-8) + + accuracy_tmp = 100 * (precision + recall) / 2 # F1-like accuracy estimation + accuracy = max(accuracy, accuracy_tmp) + return accuracy + + # Normal Classification Case + y_pred_label = np.argmax(y_pred, axis=1) + correct = np.sum(labels == y_pred_label) + accuracy = 100 * correct / len(y_pred) + return accuracy + + +def print_energy_results(l_results, energy_sampling_freq=1000, req_cycles=5, results_file=None): + # Make sure it has a line that matches this regex + # m = re.match(r".* Median energy cost is ([\d\.]+) uJ/inf\..*", line) + if results_file: + results_dir = os.path.dirname(results_file) + else: + results_dir = os.getcwd() + + inf_energies = np.nan*np.zeros(len(l_results)) + inf_times = np.nan*np.zeros(len(l_results)) + + + for inf_num,res in enumerate(l_results): + plt.clf() + energy_samples = res['power']['samples'] # assume 'output type' is set to energy + + # timestamps (or 'events' per LPM01a wording are recorded as + # (counter, num_samples) where + # counter: 0,1,.. for the 1st, 2nd, etc, to test if you lost a timestamp + # num_samples: number of samples captured when the timestamp happened + ts_counters = [int(ts[0]) for ts in res['power']['timestamps']] + ts_samp_nums = np.array([int(ts[1]) for ts in res['power']['timestamps']]) + ts_seconds = ts_samp_nums/energy_sampling_freq + + if np.any(np.diff(ts_counters) != 1): + raise RuntimeError(f"Timestamps are not consecutive:\n{res['power']['timestamps']}") + + t_implicit = np.arange(len(energy_samples))/energy_sampling_freq + plt.plot(t_implicit, energy_samples, 'b') + y_min = np.min(energy_samples) + y_max = np.max(energy_samples) + + for ts in ts_seconds: + plt.plot([ts, ts], [y_min, y_max], 'r') + plt.grid(True) + plt.savefig(os.path.join(results_dir, f"energy_inf_{inf_num:03d}.png")) + + # There is sometimes some extra activity on the timestamp pin at the + # beginning, so take the last two + t_start = ts_seconds[-2] + t_stop = ts_seconds[-1] + idx_start = ts_samp_nums[-2] + idx_stop = ts_samp_nums[-1] - :param test_script: The path to the test script definition - """ - with open(test_script) as test_file: - return yaml.load(test_file, Loader=yaml.CLoader) + elapsed_time = t_stop-t_start + inference_energy_samples = np.array(energy_samples[idx_start:idx_stop]) + total_inference_energy = np.sum(inference_energy_samples) + num_inferences = res['infer']['iterations'] + energy_per_inf = total_inference_energy / num_inferences + latency_per_inf = elapsed_time / num_inferences + inf_energies[inf_num] = energy_per_inf + inf_times[inf_num] = elapsed_time + + time_warning = "" if elapsed_time >= 10.0 else " <<<< below minimum duration" + print_tee(f"Energy data for trial {inf_num}", outfile=results_file) + print_tee(f" Elapsed time : {elapsed_time}{time_warning}", outfile=results_file) + print_tee(f" Inferences : {num_inferences}", outfile=results_file) + print_tee(f" Power : {1e3*total_inference_energy/elapsed_time:5.4f} mW.", outfile=results_file) + print_tee(f" Total Energy : {total_inference_energy*1e6:.3f} uJ", outfile=results_file) + print_tee(f" Energy/Inf : {energy_per_inf*1e6:.3f} uJ/inf", outfile=results_file) + + print_tee("---------------------------------------------------------", outfile=results_file) + print_tee(f"Median energy cost is {1e6*np.median(inf_energies):5.4f} uJ/inf.", outfile=results_file) + print_tee("---------------------------------------------------------", outfile=results_file) + if np.any(inf_times<10.0): + print_tee(f"ERROR: Not valid for submission. All inference times must be at least 10 seconds.") + if len(l_results) != req_cycles: + print_tee(f"ERROR: Not valid for submission. Energy mode must include exactly {req_cycles} measurements.") + +# Summarize results +def summarize_result(result, power, mode, results_file=None): + num_correct_files = 0 + total_files = 0 + y_pred = [] + y_true = [] + throughput_values = [] + + file_infer_results = {} + current_time = datetime.now() + formatted_time = current_time.strftime("%m%d.%H%M%S ") + + # Extract all unique classes + all_classes = sorted(list(set(int(r['class']) for r in result if 'class' in r))) + n_classes = len(all_classes) + + + if power is not None: # If power is present, turn it off. + # this should really be somewhere else + power.power_off() + power.__exit__() # fix this so it only looks for 'ack stop', in case sampling has already stopped + + + if mode == "e": + print_tee("Power Edition Output", outfile=results_file) + print_energy_results(result, energy_sampling_freq=1000, results_file=results_file) + return + + for r in result: + if 'infer' not in r or 'class' not in r or 'file' not in r: + continue # Skip malformed or error-only entries + infer_data = r['infer'] + infer_results = infer_data['results'] + file_name = r['file'] + true_class = int(r['class']) + + errors = r.get('error') # Safe access + if errors: + continue # Skip error entries entirely here + + if 'throughput' in infer_data: + throughput_values.append(infer_data['throughput']) + + if file_name not in file_infer_results: + file_infer_results[file_name] = {'true_class': true_class, 'results': []} + + if len(infer_results) == 1: + file_infer_results[file_name]['results'].append(infer_results) + else: + infer_results = normalize_probabilities(infer_results) + file_infer_results[file_name]['results'].append(infer_results) + + if throughput_values: # <-- NEW: Performance mode detected + has_error_1 = any(r.get("error") == "error 1" for r in result) + has_error_2 = any(r.get("error") == "error 2" for r in result) + if has_error_1: + print_tee(f"{formatted_time}ulp-mlperf: ERROR 1 - loop_count was not exactly 5.", outfile=results_file) + elif has_error_2: + print_tee(f"{formatted_time}ulp-mlperf: ERROR 2 - loop exited before 10 seconds elapsed.", outfile=results_file) + else: + median_throughput = np.median(throughput_values) + print_tee(f"{formatted_time}ulp-mlperf: ---------------------------------------------------------", outfile=results_file) + print_tee(f"{formatted_time}ulp-mlperf: Median throughput is {median_throughput:>10.3f} inf./sec.", outfile=results_file) + print_tee(f"{formatted_time}ulp-mlperf: ---------------------------------------------------------", outfile=results_file) + + else: + for file_name, data in file_infer_results.items(): + true_class = data['true_class'] + results = data['results'] + + class_counts = Counter([np.argmax(res) for res in results]) + majority_class = class_counts.most_common(1)[0][0] + + if majority_class == true_class: + num_correct_files += 1 + + averaged_result = np.mean(results, axis=0) + y_pred.append(averaged_result) + y_true.append(true_class) + + total_files += 1 + + accuracy = calculate_accuracy(np.array(y_pred), np.array(y_true)) + auc = roc_auc_score(np.array(y_true), np.array(y_pred), multi_class='ovr') + + + current_time = datetime.now() + formatted_time = current_time.strftime("%m%d.%H%M%S ") + print_tee(f"{formatted_time}ulp-mlperf: Top 1% = {accuracy:2.1f}", outfile=results_file) + print_tee(f"{formatted_time}ulp-mlperf: AUC = {auc:.3f}", outfile=results_file) + if __name__ == '__main__': - parser = argparse.ArgumentParser(prog="TestRunner", description=__doc__) - parser.add_argument("-d", "--device_list", default="devices.yaml", help="Device definition YAML file") - parser.add_argument("-y", "--device_yaml", required=False, help="Raw YAML to interpret as the target device") - parser.add_argument("-u", "--dut_config", required=False, help="Target device") - parser.add_argument("-v", "--dut_voltage", required=False, help="Voltage set during test") - parser.add_argument("-b", "--dut_baud", required=False, help="Baud rate for device under test") - parser.add_argument("-t", "--test_script", default="tests.yaml", help="File containing test scripts") - parser.add_argument("-s", "--dataset_path", default="datasets") - args = parser.parse_args() - config = { - "devices_config": parse_device_config(args.device_list, args.device_yaml), - "dut_config": parse_dut_config(args.dut, args.dut_voltage, args.dut_baud), - "test_script": parse_test_script(args.test_script), - "dataset_path": args.dataset_path - } - print(run_test(**config)) + parser = argparse.ArgumentParser(prog="TestRunner", description=__doc__) + parser.add_argument("-d", "--device_list", default="devices.yaml", help="Device definition YAML file") + parser.add_argument("-y", "--device_yaml", required=False, help="Raw YAML to interpret as the target device") + parser.add_argument("-t", "--test_script", default=None, help="File containing test scripts") + parser.add_argument("-s", "--dataset_path", default="datasets") + parser.add_argument("-m", "--mode", choices=["e", "p", "a"], default="a", help="Test mode (energy (e), performance (p), accuracy (a))") + args = parser.parse_args() + if args.test_script is not None: + test_script_file=args.test_script + else: + if args.mode == "a": + test_script_file = "tests_accuracy.yaml" # Accuracy test script + elif args.mode == "p": + test_script_file = "tests_performance.yaml" # Performance test script + elif args.mode == "e": + test_script_file = "tests_energy.yaml" # Energy test script + config = { + "devices_config": parse_device_config(args.device_list, args.device_yaml), + "test_script": parse_test_script(test_script_file), + "dataset_path": args.dataset_path, + "mode": args.mode + } + # copy any DUT from the devices_config into the dut_config. The last DUT listed will + # be the one we use. This means that internally we have the DUT info in two + # places (config["devices_config"][i] for some i, and dut_config), but at least + # externally the DUT info is only in one place + for dev in config["devices_config"]: + if dev["type"] == "dut": + config["dut_config"] = dev + + result, power = run_test(**config) # Unpack power from run_test + if isinstance(result, dict): # this is a hack. make the run_test outputs consistent + result = [result] + for r in result: + r["mode"] = config["mode"] + results_file = os.path.join(os.path.dirname(log_filename), "results.txt") + if config['dut_config']['model'] == 'sww01': + if power is not None: # If power is present, turn it off. + # this should really be somewhere else + power.power_off() + power.__exit__() # fix this so it only looks for 'ack stop', in case sampling has already stopped + if config["mode"] == "e": + print_tee("Power Edition Output", outfile=results_file) + print_energy_results(result, energy_sampling_freq=1000, req_cycles=1, results_file=results_file) + sww_util.summarize_sww_result(result, power, results_file=results_file) + else: + summarize_result(result, power, mode=config["mode"], results_file=results_file) + + print(f"Session logged in file {log_filename}") + results_data_file = os.path.join(os.path.dirname(log_filename), "results.json") + with open(results_data_file, 'w') as fpo: + json.dump(result, fpo) \ No newline at end of file diff --git a/benchmark/runner/power_manager.py b/benchmark/runner/power_manager.py deleted file mode 100644 index d12236ea..00000000 --- a/benchmark/runner/power_manager.py +++ /dev/null @@ -1,409 +0,0 @@ -import re -import sys -from queue import Queue -from serial_device import SerialDevice -from threading import Thread - -class PowerManager(SerialDevice): - PROMPT = "PowerShield > " - - def __init__(self, port_device, baud_rate=921600): - self._port = SerialDevice(port_device, baud_rate, "ack|error", "\r\n") - self._voltage = "3000m" - self._board_id = None - self._version = None - self._lcd = [None, None] - self._in_prograss = False - self._data_queue = Queue() - self._message_queue = Queue() - self._read_thread = None - self._running = False - - def __enter__(self): - self._port.__enter__() - self._start_read_thread() - self._setup() - return self - - def __exit__(self, *args): - self._tear_down() - self._stop_read_thread() - self._port.__exit__(*args) - - def _read_loop(self): - while self._running: - line = self._port.read_line(timeout=0.250) - if not line: - continue - if line.startswith("TimeStamp"): - self._data_queue.put(line) - elif re.match("\d\d\d\d[+-]\d\d", line): - line = line.replace('+', 'e').replace('-', "e-") - line = line[:1] + "." + line[1:] - value = float(line) - self._data_queue.put(value) - else: - self._message_queue.put(line) - - def _start_read_thread(self): - self._running = True - self._read_thread = Thread(target=self._read_loop) - self._read_thread.start() - - def _stop_read_thread(self): - self._running = False - self._read_thread.join() - - def _setup(self): - # verify board - self._claim_remote_control() - print(f"LPM01A Power Monitor Board", file=sys.stderr) - print(f"BoardID: {self.get_board_id()}", file=sys.stderr) - print(f"Version: {self.get_version()}", file=sys.stderr) - print(f"Status: {self.get_status()}", file=sys.stderr) - self.set_lcd(" mlperf ", " monitor ") - self.power_off() - # Acquire infinitely - self.configure_trigger('inf', 0, 'd7') - self.configure_output('energy', 'ascii_dec', '1k') - self.set_voltage(self._voltage) - self.power_on() - # self.start() - - def _tear_down(self): - # self.stop() - self._release_remote_control() - - def _claim_remote_control(self): - self._send_command("htc") - - def _release_remote_control(self): - self._send_command("hrc") - - def get_board_id(self): - if not self._board_id: - result, output = self._send_command("powershield", err_message="Error getting BoardId") - self._board_id = output if result else None - return self._board_id - - def get_version(self): - if not self._version: - result, output = self._send_command("version", err_message="Error getting version") - self._version = output[1] if result else None - return self._version - - def get_lcd(self): - return self._lcd - - def set_lcd(self, *args): - for i in range(len(args)): - if args[i] and args[i] != self._lcd[i]: - result, _ = self._send_command(f'lcd {i+1} "{args[i]}"', - err_message=f"Error setting LCD line {i+1} to \"{args[i]}\"") - self._lcd[i] = args[i] if result else self._lcd[i] - return self._lcd - - def configure_trigger(self, acquisition_time, trigger_delay, trigger_source): - self._send_command(f"acqtime {acquisition_time}", - err_message=f"Error setting acquisition_time to {acquisition_time}") - self._send_command(f"trigdelay {trigger_delay}", - err_message="Error setting trigger_delay to {trigger_delay}") - self._send_command(f"trigsrc {trigger_source}", - err_message=f"Error setting trigger_source to {trigger_source}") - - def configure_output(self, output_type, output_format, samples_per_second): - self._send_command(f"output {output_type}", err_message=f"Error setting output_type to {output_type}") - self._send_command(f"format {output_format}", err_message=f"Error setting output_format to {output_format}") - self._send_command(f"freq {samples_per_second}", - err_message=f"Error setting samples_per_second to {samples_per_second}") - - def power_on(self, show_status=False): - self.set_lcd(None, f"{self._voltage : >14}V ") - self._send_command(f"pwr on {'' if show_status else 'no'}status", err_message=f"Error turning on power") - - def power_off(self): - self._send_command("pwr off", err_message=f"Error turning off power") - - def configure_voltage(self, voltage): - self._voltage = voltage - - def set_voltage(self, voltage): - self._send_command(f"volt {voltage}", err_message=f"Error setting voltage to {voltage}V") - - def start(self): - return self._send_command("start") - - def stop(self): - # stop does not ack - print("stop") - self._port.write_line("stop") - lines = [] - line = None - while not line or "Acquisition completed" not in line: - line = self._message_queue.get() - if line: - lines.append(line) - return lines - - def get_results(self): - while not self._data_queue.empty(): - yield self._data_queue.get() - - def get_status(self): - result, output = self._send_command("status", err_message="Error getting status") - return output if result else None - - def get_help(self): - result, output = self._send_command("help", True, err_message="Error getting help") - return output if result else None - - def _read_response(self, command): - out_lines = [] - while True: - line = self._message_queue.get() - temp = line.replace(PowerManager.PROMPT, "").strip() - if temp and command in temp and (temp.startswith('ack') or temp.startswith('error')): - out_lines.extend(r for r in temp.replace(command, "").split(" ", 2) if r) - break - elif temp and not temp.startswith("ack") and not temp.startswith("error"): - out_lines.append(temp) - return out_lines - - def _read_error_output(self): - while True: - line = self._message_queue.get() - line = line.replace(PowerManager.PROMPT, "").strip() - if line.startswith("Error detail"): - return [line.replace("Error detail:", "").strip()] - - def _read_output(self): - while True: - line = self._message_queue.get() - # print(f"OUT: {line}") - if line == PowerManager.PROMPT: - return - line = line.replace(PowerManager.PROMPT, "").strip() - if line: - yield line - - def _purge_messages(self): - while not self._message_queue.empty(): - line = self._message_queue.get() - if line: - print(f"Dropping message: {line}", file=sys.stderr) - - def _send_command(self, command, expect_output=False, err_message=None): - self._purge_messages() - print(f"pwr {command}") - self._port.write_line(command) - lines = self._read_response(command) - result = lines and lines[0] == 'ack' - output = lines[1:] if lines and len(lines) > 1 else [] - if not result: - output = self._read_error_output() - if err_message is not None: - print(f"{err_message}: {output[0]}", file=sys.stderr) - elif expect_output: - output = [l for l in self._read_output()] - return result, output if not output or len(output) != 1 else output[0] - - """ - ################################################################################ - # PowerShield commands # - ################################################################################ - # Command # Description # - ################################################################################ - # Common operation # - ################################################################################ - # help # Displays list of commands. # - # # # - # echo # Loopback to check functionality of communication Rx and Tx. # - # # : String of characters # - # # # - # powershield # Check PowerShield device availability, can be used to scan # - # # on which serial port is connected the PowerShield. # - # # Response: 'PowerShield present' with board unique ID # - # # # - # version # Get PowerShield FW revision. # - # # Response: '
..' # - # # # - # range # Get PowerShield current measurement range. # - # # Response: # - # # # - # status # Get PowerShield status. # - # # Response: 'ok' or 'error: ' # - # # # - # htc # Host take control (go from mode 'standalone' # - # # to mode 'controlled by host') # - # hrc # Host release control (go from mode 'controlled by host' # - # # to mode 'standalone') # - # # # - # lcd # Display a custom string on LCD display when PowerShield is # - # # controlled by host. # - # # : LCD line. Numerical value among list: {1, 2} # - # # : String to be displayed, surrounded by double quotes # - # # and with 16 characters maximum. # - # # Example: lcd 1 " custom display" # - # # # - # psrst # Reset PowerShield (hardware reset, # - # # host communication will have to be restored). # - # # # - ################################################################################ - # Measurement acquisition configuration # - ################################################################################ - # volt # Set or get power supply voltage level, unit: V. # - # # : Set voltage: Numerical value in range [1800m; 3300m] # - # # Default value: 3300m # - # # Get voltage: String 'get' # - # # # - # freq # Set sampling frequency, unit: Hz. # - # # : Numerical value among list: # - # # {100k, 50k, 20k, 10k, 5k, 2k, 1k, 500, 200 # - # # 100, 50, 20, 10, 5, 2, 1} # - # # Default value: 100Hz # - # # # - # acqtime # Set acquisition time, unit: s. # - # # : For limited acquisition duration: # - # # Numerical value in range: [100u; 100] # - # # For infinite acquisition duration: # - # # Numerical value '0' or string 'inf' # - # # Caution: Maximum acquisition time depends on other # - # # parameters. Refer to table below. # - # # Default value: 10s # - # # # - # acqmode # Set acquisition mode: dynamic or static. # - # # dynamic: current can vary, range [100nA; 10mA] # - # # static: current must be constant, range [2nA; 200mA] # - # # : String among list: {'dyn', 'stat'} # - # # Default value: 'dyn' # - # # # - # funcmode # Set optimization of acquisition mode dynamic (applicable # - # # only with command 'output' set to parameter 'current'): # - # # optim: priority on current resolution (100nA-10mA), # - # # max sampling frequency at 100KHz. # - # # high: high current (30uA-10mA), high sampling frequency # - # # (50-100KHz), high resolution. # - # # : String among list: {'optim', 'high'} # - # # Default value: 'optim' # - # # # - # output # Set output type. # - # # current: instantaneous current # - # # energy: integrated energy, reset after each sample sent # - # # (integration time set by param 'freq', # - # # limited at 10kHz max (<=> 100us min)). # - # # : String among list: {'current', 'energy'} # - # # Default value: 'current' # - # # # - # format # Set measurement data format. # - # # Data format 1: ASCII, decimal basis. # - # # Format readable directly, but sampling # - # # frequency limited to 10kHz. # - # # Decoding: 6409-07 <=> 6409 x 10^-7 = 640.9uA # - # # Data format 2: Binary, hexadecimal basis. # - # # Format optimized data stream size. # - # # Decoding: 52A0 <=> (2A0)16 x 16^-5 = 640.9uA # - # # : String among list: {'ascii_dec', 'bin_hexa'} # - # # Caution: Data format depends on other # - # # parameters. Refer to table below. # - # # Default value: 'ascii_dec' # - # # # - # trigsrc # Set trigger source to start measurement acquisition: # - # # trigger source SW (immediate trig after SW start), # - # # trigger from external signal rising or falling edge on # - # # Arduino connector D7 (via solder bridge). # - # # : String among list: {'sw', 'd7'} # - # # Default value: 'sw' # - # # # - # trigdelay # Set trigger delay between target power-up and start # - # # measurement acquisition, unit: s, resolution: 1ms. # - # # : Numerical value in range [0; 30] # - # # Default value: 1m # - # # # - # currthres # Set current threshold to trig an event, unit: A. # - # # Event triggered when threshold exceeded: signal generated # - # # on Arduino connector D2 or D3 (via solder bridge) # - # # and LED4 (blue) turned on. # - # # : Numerical value in range [100n; 50m] # - # # or value '0' for threshold disable # - # # Default value: 1m # - # # # - # pwr # Set target power supply connection. # - # # Automatic: On first run, power-on when acquisition start. # - #() # Then, power state depends on command 'pwrend'. # - # # Manual: Force power state. # - # # Note: Can be used during acquisition. To perform # - # # successive power off and on, it is preferable # - # # to use command 'targrst'. # - # # Optionally, connection status can be sent at the beginning # - # # and end of acquisition data stream. # - # # : Set pwr: String among list: {'auto', 'on', 'off'} # - # # Default value: 'auto' # - # # Get pwr: String 'get' (response: state 'on' or 'off') # - # # : Optional, string among list: {'nostatus', 'status'} # - # # Default value: 'nostatus' # - # # # - # pwrend # Set target power supply connection to be applied after # - # # acquisition: power-on or power-off. # - # # : String among list: {on, off} # - # # Default value: 'on' # - # # # - # # # - ################################################################################ - # Measurement acquisition operation # - ################################################################################ - # start # Start acquisition (measurement of current or energy # - # # depending on configuration). # - # # # - # stop # Stop acquisition. If acquisition is set to a finite duration, # - # # it will stop when reaching the target duration. # - # # # - # targrst # Reset target by disconnecting power supply during # - # # a configurable duration, unit: s. # - # # Note: Can be performed during acquisition to monitor target # - # # transient current consumption during its power-up. # - # # : Numerical value in range [10m; 1] # - # # or value '0' to let target powered-down # - # # # - # temp # Get temperature from temperature sensor on PowerShield board, # - # # on unit: Degree Celsius or Fahrenheit. # - # # : String among list: {degc, degf} # - # # Default value: 'degc' # - # # # - ################################################################################ - # Board state operation # - ################################################################################ - # autotest # Perform board autotest and display autotest results. # - #() # Note: Autotest is done at PowerShield power-up. # - #() # : Optional: string among list: {start, status} # - # # or no argument equivalent to value: 'start' # - # # : Optional: results status all or minimal (ok - not ok) # - # # string among list: {stat_all, stat_min} # - # # # - # calib # Perform board self-calibration. # - # # Note: New calibration should be performed when temperature # - # # shifts of more than 5 degC since the previous # - # # calibration. # - # # Note: Calibration is done at PowerShield power-up # - # # and after each update of power supply voltage level. # - # # # - ################################################################################ - # Note: Numerical values of arguments can be formatted either: # - # - Numerical characters only (possible when numbers are >= 1) # - # - Numerical characters with unit characters 'u', 'm', 'k', 'm' # - # - Numerical characters with power of ten '-xx' or '+xx' # - # (xx: number on 2 digits maximum) # - # Example: Value '2 milliseconds' can be entered with: '2m' or '2-3' # - ################################################################################ - # Table of maximum acquisition time possible in function of # - # sampling frequency and data format, # - # for a baudrate of 3686400 bauds: # - # ______________________________________________________________________ # - # | format freq | acqtime max (corresp. nb of samples) | # - # |____________________________________________________________________| # - # | ascii_dec | <= 5k | unlimited (unlimited) | # - # | ascii_dec | 10k | 1s ( 10 000) | # - # | ascii_dec | 20k | 500ms ( 5 000) | # - # | bin_hexa | <=100k | unlimited (unlimited) | # - # |____________________________________________________________________| # - ################################################################################ - """ diff --git a/benchmark/runner/power_manager/power_manager.py b/benchmark/runner/power_manager/power_manager.py new file mode 100644 index 00000000..90e07c6d --- /dev/null +++ b/benchmark/runner/power_manager/power_manager.py @@ -0,0 +1,77 @@ +# power_manager.py + +import re +import sys +from queue import Queue +from threading import Thread +from serial_device import SerialDevice + + +class PowerManager: + PROMPT = "PowerShield > " + + def __init__(self, device_type, port_device=None, baud_rate=None, voltage=3.3, echo=False, js_device=None, config=None): + self._device_type = device_type + self._voltage = voltage + self._board_id = None + self._version = None + self._lcd = [None, None] + self._in_prograss = False + self._data_queue = Queue() + self._message_queue = Queue() + self._read_thread = None + self._running = False + + if device_type == "lpm01a": + from .power_manager_lpm import LPMCommands # only import this file if we're using this device + self._port = SerialDevice(port_device, baud_rate, "ack|error", "\r\n", echo=echo) + self._commands = LPMCommands(self, self._port) + elif device_type == "js220": + from .power_manager_js220 import JoulescopeCommands + if js_device is None: + from joulescope import scan_require_one + js_device = scan_require_one(config="ignore") + self._commands = JoulescopeCommands(self, js_device=js_device, config=config) + self._port = self._commands.get_port() + else: + raise ValueError(f"Unsupported device type: {device_type}") + + self.__enter__() + + def __enter__(self): + self._port.__enter__() + self._start_read_thread() # ✅ move this up + self._commands.setup() # ✅ now it's safe like the old code + return self + + def __exit__(self, *args): + self._commands.tear_down() + self._stop_read_thread() + self._port.__exit__(*args) + + def _start_read_thread(self): + self._running = True + self._read_thread = Thread(target=self._commands.read_loop) + self._read_thread.start() + + def _stop_read_thread(self): + self._running = False + self._read_thread.join() + + def get_results(self): + while not self._data_queue.empty(): + yield self._data_queue.get() + + def should_stop(self): + return not self._running + + + # Pass-throughs + def power_on(self): return self._commands.power_on() + def power_off(self): return self._commands.power_off() + def start(self): return self._commands.start() + def stop(self): return self._commands.stop() + def get_status(self): return self._commands.get_status() + def get_board_id(self): return self._commands.get_board_id() + def get_version(self): return self._commands.get_version() + def set_lcd(self, *args): return self._commands.set_lcd(*args) diff --git a/benchmark/runner/power_manager/power_manager_js220.py b/benchmark/runner/power_manager/power_manager_js220.py new file mode 100644 index 00000000..67fb936e --- /dev/null +++ b/benchmark/runner/power_manager/power_manager_js220.py @@ -0,0 +1,375 @@ +import time +from joulescope import scan +import numpy as np + +class JS220PortWrapper: + def __init__(self, device): + self._device = device + + def __enter__(self): + return self + + def __exit__(self, *args): + return self + + def close(self): + return self._device.close() + + def write_line(self, line): + pass + + def read_line(self, timeout=None): + return None + + +class JoulescopeCommands: + def __init__(self, manager, js_device, config=None): + self.m = manager + self._device = js_device + self._triggered = False + self._last_sample_id = None + self._last_gpi = None + js_config = config or {} + self.raw_rate = int(js_config.get("raw_sampling_rate", 1000000)) + self.virtual_rate = int(js_config.get("virtual_sampling_rate", 1000)) + self.emit_stride = max(1, self.raw_rate // self.virtual_rate) + + self._device.parameter_set("source", "raw") + self._device.parameter_set("sensor_power", "on") + self._device.parameter_set("sampling_frequency", self.raw_rate) + self._device.parameter_set("io_voltage", "3.3V") + self._device.parameter_set("trigger_source", "gpi0") + self._device.parameter_set("current_lsb", "gpi0") + + try: + self._device.start() + except Exception as e: + print(f"[JS220] Failed to start device: {e}") + + def get_port(self): + return JS220PortWrapper(self._device) + + def setup(self): + pass + + def tear_down(self): + print("[JS220] Shutting down stream...") + self.m._running = False + try: + self._device.stop() + except Exception: + pass + try: + self._device.close() + except Exception: + pass + print("[JS220] Shutdown complete.") + + def read_loop(self): + sb = self._device.stream_buffer + print("[JS220] Stream reading started (trigger mimic)...") + + current_buffer = [] + voltage_buffer = [] + timestamp_buffer = [] + + ts_counter = 0 + last_emit_time = time.time() + event_counter = 0 + + while self.m._running: + + sample_id_range = sb.sample_id_range + if sample_id_range is None: + time.sleep(0.001) + continue + + start_id, end_id = sample_id_range + if self._last_sample_id is None or end_id < self._last_sample_id: + self._last_sample_id = start_id + + if end_id <= self._last_sample_id: + time.sleep(0.001) + continue + + try: + data = sb.samples_get(self._last_sample_id, end_id, fields=["current", "voltage", "current_lsb"]) + except ValueError: + self._last_sample_id = None + continue + + current = data["signals"]["current"]["value"] + voltage = data["signals"]["voltage"]["value"] + gpi0_vals = data["signals"]["current_lsb"]["value"] + t0 = time.time() + count = min(len(current), len(voltage), len(gpi0_vals)) + self._last_sample_id = end_id + + for i in range(count): + current_buffer.append(current[i]) + voltage_buffer.append(voltage[i]) + timestamp_buffer.append(t0) + + gpi = int(gpi0_vals[i] > 0) + if self._last_gpi is None: + self._last_gpi = gpi + continue + + # ✅ Emit event string (on rising edge only) + if self._triggered: + if self._last_gpi == 0 and gpi == 1: + event_line = f"event {event_counter:02} ris" + self.m._data_queue.put(event_line) + event_counter += 1 + self._triggered = False + else: + if self._last_gpi == 1 and gpi == 0: + self._triggered = True + + self._last_gpi = gpi + + if len(current_buffer) >= self.emit_stride: + avg_time = float(np.mean(timestamp_buffer)) + # ✅ Compute energy over 1ms: E = I * V * dt + energy = float(np.mean([i * v * 0.001 for i, v in zip(current_buffer, voltage_buffer)])) + self.m._data_queue.put(energy) + current_buffer.clear() + voltage_buffer.clear() + timestamp_buffer.clear() + + print("[JS220] Stream reading loop exited.") + + + + + def power_on(self): + return True + + def power_off(self): + return True + + def start(self): + return True + + def stop(self): + return True + + def get_board_id(self): + return self._device.device_path() + + def get_version(self): + try: + return self._device.info().get("fw") + except Exception: + return None + + def get_status(self): + return None + + def set_lcd(self, *args): + return [None, None] + + + + +""" +################################################################################ +# Joulescope Commands # +################################################################################ +# Parameter: sensor_power +# Options: +# [0] ('off', 0, []) +# [1] ('on', 1, []) + +# Parameter: source +# Options: +# [0] ('off', 0, []) +# [1] ('raw', 192, ['on']) +# [2] ('pattern_usb', 9, []) +# [3] ('pattern_control', 10, []) +# [4] ('pattern_sensor', 175, []) + +# Parameter: i_range +# Options: +# [0] ('auto', 128, ['on']) +# [1] ('10 A', 1, ['0', 0]) +# [2] ('2 A', 2, ['1', 1]) +# [3] ('180 mA', 4, ['2', 2]) +# [4] ('18 mA', 8, ['3', 3]) +# [5] ('1.8 mA', 16, ['4', 4]) +# [6] ('180 µA', 32, ['5', 5]) +# [7] ('18 µA', 64, ['6', 6]) +# [8] ('off', 0, []) + +# Parameter: v_range +# Options: +# [0] ('15V', 0, ['low', 0]) +# [1] ('5V', 1, ['high', 1]) + +# Parameter: ovr_to_lsb +# Options: +# [0] ('off', 0, []) +# [1] ('on', 1, []) + +# Parameter: trigger_source +# Options: +# [0] ('auto', 0, []) +# [1] ('gpi0', 2, []) +# [2] ('gpi1', 3, []) + +# Parameter: io_voltage +# Options: +# [0] ('1.8V', 1800, []) +# [1] ('2.1V', 2100, []) +# [2] ('2.5V', 2500, []) +# [3] ('2.7V', 2700, []) +# [4] ('3.0V', 3000, []) +# [5] ('3.3V', 3300, []) +# [6] ('3.6V', 3600, []) +# [7] ('5.0V', 5000, []) + +# Parameter: gpo0 +# Options: +# [0] ('0', 0, [0]) +# [1] ('1', 1, [1]) + +# Parameter: gpo1 +# Options: +# [0] ('0', 0, [0]) +# [1] ('1', 1, [1]) + +# Parameter: current_lsb +# Options: +# [0] ('normal', 0, []) +# [1] ('gpi0', 2, []) +# [2] ('gpi1', 3, []) + +# Parameter: voltage_lsb +# Options: +# [0] ('normal', 0, []) +# [1] ('gpi0', 2, []) +# [2] ('gpi1', 3, []) + +# Parameter: control_test_mode +# Options: +# [0] ('normal', 3, []) +# [1] ('usb', 129, []) +# [2] ('fpga', 130, []) +# [3] ('both', 131, []) + +# Parameter: transfer_length +# Options: +# [0] ('1', 1, []) +# [1] ('2', 2, []) +# [2] ('4', 4, []) +# [3] ('8', 8, []) +# [4] ('16', 16, []) +# [5] ('32', 32, []) +# [6] ('64', 64, []) +# [7] ('128', 128, []) +# [8] ('256', 256, []) + +# Parameter: transfer_outstanding +# Options: +# [0] ('1', 1, []) +# [1] ('2', 2, []) +# [2] ('4', 4, []) +# [3] ('8', 8, []) + +# Parameter: current_ranging +# Current Value: interp_1_n_1 + +# Parameter: current_ranging_type +# Options: +# [0] ('off', 'off', []) +# [1] ('mean', 'mean', []) +# [2] ('interp', 'interp', ['interpolate']) +# [3] ('NaN', 'nan', ['nan']) + +# Parameter: current_ranging_samples_pre +# Options: +# [0] ('0', 0, [0]) +# [1] ('1', 1, [1]) +# [2] ('2', 2, [2]) +# [3] ('3', 3, [3]) +# [4] ('4', 4, [4]) +# [5] ('5', 5, [5]) +# [6] ('6', 6, [6]) +# [7] ('7', 7, [7]) +# [8] ('8', 8, [8]) + +# Parameter: current_ranging_samples_window +# Options: +# [0] ('m', 'm', []) +# [1] ('n', 'n', []) +# [2] ('0', 0, [0]) +# [3] ('1', 1, [1]) +# [4] ('2', 2, [2]) +# [5] ('3', 3, [3]) +# [6] ('4', 4, [4]) +# [7] ('5', 5, [5]) +# [8] ('6', 6, [6]) +# [9] ('7', 7, [7]) +# [10] ('8', 8, [8]) +# [11] ('9', 9, [9]) +# [12] ('10', 10, [10]) +# [13] ('11', 11, [11]) +# [14] ('12', 12, [12]) + +# Parameter: current_ranging_samples_post +# Options: +# [0] ('0', 0, [0]) +# [1] ('1', 1, [1]) +# [2] ('2', 2, [2]) +# [3] ('3', 3, [3]) +# [4] ('4', 4, [4]) +# [5] ('5', 5, [5]) +# [6] ('6', 6, [6]) +# [7] ('7', 7, [7]) +# [8] ('8', 8, [8]) + +# Parameter: buffer_duration +# Options: +# [0] ('15 seconds', 15, [15]) +# [1] ('30 seconds', 30, [30]) +# [2] ('1 minute', 60, [60]) +# [3] ('2 minutes', 120, [120]) +# [4] ('5 minutes', 300, [300]) +# [5] ('10 minutes', 600, [600]) +# [6] ('20 minutes', 1200, [1200]) +# [7] ('1 hour', 3600, [3600]) +# [8] ('2 hours', 7200, [7200]) +# [9] ('5 hours', 18000, [18000]) +# [10] ('10 hours', 36000, [36000]) +# [11] ('1 day', 86400, [86400]) + +# Parameter: reduction_frequency +# Options: +# [0] ('100 Hz', 100, [100]) +# [1] ('50 Hz', 50, [50]) +# [2] ('20 Hz', 20, [20]) +# [3] ('10 Hz', 10, [10]) +# [4] ('5 Hz', 5, [5]) +# [5] ('2 Hz', 2, [2]) +# [6] ('1 Hz', 1, [1]) + +# Parameter: sampling_frequency +# Options: +# [0] ('2 MHz', 2000000, [2000000, 'auto', None, 'default']) +# [1] ('1 MHz', 1000000, [1000000]) +# [2] ('500 kHz', 500000, [500000]) +# [3] ('200 kHz', 200000, [200000]) +# [4] ('100 kHz', 100000, [100000]) +# [5] ('50 kHz', 50000, [50000]) +# [6] ('20 kHz', 20000, [20000]) +# [7] ('10 kHz', 10000, [10000]) +# [8] ('5 kHz', 5000, [5000]) +# [9] ('2 kHz', 2000, [2000]) +# [10] ('1 kHz', 1000, [1000]) +# [11] ('500 Hz', 500, [500]) +# [12] ('200 Hz', 200, [200]) +# [13] ('100 Hz', 100, [100]) +# [14] ('50 Hz', 50, [50]) +# [15] ('20 Hz', 20, [20]) +# [16] ('10 Hz', 10, [10]) +""" \ No newline at end of file diff --git a/benchmark/runner/power_manager/power_manager_lpm.py b/benchmark/runner/power_manager/power_manager_lpm.py new file mode 100644 index 00000000..cf936f01 --- /dev/null +++ b/benchmark/runner/power_manager/power_manager_lpm.py @@ -0,0 +1,359 @@ +# power_manager_lpm.py + +import re +import sys + + +class LPMCommands: + def __init__(self, manager, port): + self.m = manager + self._port = port + + def setup(self): + self._send_command("htc") + self.set_lcd("MLPerf Tiny", " monitor ") + self.power_off() + self.configure_trigger("inf", 0, "sw") + self.configure_output("energy", "ascii_dec", "1k") + self.configure_voltage(self.m._voltage) + + def tear_down(self): + self.stop() + self.power_off() + self._send_command("hrc") + + def read_loop(self): + while self.m._running: + line = self._port.read_line(timeout=0.25) + if not line: + continue + if line.startswith("TimeStamp"): + self.m._data_queue.put(line) + elif re.match(r"\d{4}[+-]\d{2}", line): + values = self._extract_current_values(line) + for v in values: + self.m._data_queue.put(v) + elif re.match(r"event \d+ ris", line): + self.m._data_queue.put(line) + else: + self.m._message_queue.put(line) + + def configure_trigger(self, acqtime, trigdelay, trigsrc): + self._send_command(f"acqtime {acqtime}") + self._send_command(f"trigdelay {trigdelay}") + self._send_command(f"trigsrc {trigsrc}") + self._send_command("eventsrc d7 fal") + + def configure_output(self, output_type, output_format, freq): + self._send_command(f"output {output_type}") + self._send_command(f"format {output_format}") + self._send_command(f"freq {freq}") + + def configure_voltage(self, voltage): + self.m._voltage = voltage + self._send_command(f"volt {int(voltage * 1000)}m") + + def power_on(self): + self.set_lcd(None, f"{self.m._voltage: >14}V ") + return self._send_command("pwr on nostatus") + + def power_off(self): + return self._send_command("pwr off") + + def start(self): + return self._send_command("start") + + def stop(self): + self._port.write_line("stop") + while True: + line = self.m._message_queue.get() + if "Acquisition completed" in line: + break + return True + + def get_board_id(self): + if not self.m._board_id: + result, output = self._send_command("powershield") + self.m._board_id = output if result else None + return self.m._board_id + + def get_version(self): + if not self.m._version: + result, output = self._send_command("version") + self.m._version = output[1] if result else None + return self.m._version + + def get_status(self): + result, output = self._send_command("status") + return output if result else None + + def set_lcd(self, *args): + for i in range(len(args)): + if args[i] and args[i] != self.m._lcd[i]: + result, _ = self._send_command(f'lcd {i+1} "{args[i]}"') + if result: + self.m._lcd[i] = args[i] + return self.m._lcd + + # Internal utilities moved from PowerManager + + def _send_command(self, command, expect_output=False, err_message=None): + self._purge_messages() + self._port.write_line(command) + lines = self._read_response(command) + result = lines and lines[0] == 'ack' + output = lines[1:] if lines and len(lines) > 1 else [] + if not result: + print(f"Power Manager did not acknowledge. PM Response:") + print(lines) + output = self._read_error_output() + if err_message: + print(f"{err_message}: {output[0]}", file=sys.stderr) + elif expect_output: + output = list(self._read_output()) + return result, output if not output or len(output) != 1 else output[0] + + def _purge_messages(self): + while not self.m._message_queue.empty(): + self.m._message_queue.get() + + def _read_response(self, command): + out_lines = [] + while True: + line = self.m._message_queue.get() + temp = line.replace(self.m.PROMPT, "").strip() + if temp and command in temp and (temp.startswith("ack") or temp.startswith("error")): + out_lines.extend(r for r in temp.replace(command, "").split(" ", 2) if r) + break + elif temp and not temp.startswith("ack") and not temp.startswith("error"): + out_lines.append(temp) + return out_lines + + def _read_output(self): + while True: + line = self.m._message_queue.get() + if line == self.m.PROMPT: + return + yield line.replace(self.m.PROMPT, "").strip() + + def _read_error_output(self): + while True: + line = self.m._message_queue.get() + line = line.replace(self.m.PROMPT, "").strip() + if line.startswith("Error detail"): + return [line.replace("Error detail:", "").strip()] + + def _extract_current_values(self, line): + pattern = r'\d{4}[-+]\d{2}' + matches = list(re.finditer(pattern, line)) + results = [] + if matches: + if matches[0].start() > 0: + results.append("nan") + results.extend(match.group() for match in matches) + if matches[-1].end() < len(line): + results.append("nan") + return [float(s.replace("+", "e+").replace("-", "e-")) for s in results] + + + +""" +################################################################################ +# PowerShield commands # +################################################################################ +# Command # Description # +################################################################################ +# Common operation # +################################################################################ +# help # Displays list of commands. # +# # # +# echo # Loopback to check functionality of communication Rx and Tx. # +# # : String of characters # +# # # +# powershield # Check PowerShield device availability, can be used to scan # +# # on which serial port is connected the PowerShield. # +# # Response: 'PowerShield present' with board unique ID # +# # # +# version # Get PowerShield FW revision. # +# # Response: '
..' # +# # # +# range # Get PowerShield current measurement range. # +# # Response: # +# # # +# status # Get PowerShield status. # +# # Response: 'ok' or 'error: ' # +# # # +# htc # Host take control (go from mode 'standalone' # +# # to mode 'controlled by host') # +# hrc # Host release control (go from mode 'controlled by host' # +# # to mode 'standalone') # +# # # +# lcd # Display a custom string on LCD display when PowerShield is # +# # controlled by host. # +# # : LCD line. Numerical value among list: {1, 2} # +# # : String to be displayed, surrounded by double quotes # +# # and with 16 characters maximum. # +# # Example: lcd 1 " custom display" # +# # # +# psrst # Reset PowerShield (hardware reset, # +# # host communication will have to be restored). # +# # # +################################################################################ +# Measurement acquisition configuration # +################################################################################ +# volt # Set or get power supply voltage level, unit: V. # +# # : Set voltage: Numerical value in range [1800m; 3300m] # +# # Default value: 3300m # +# # Get voltage: String 'get' # +# # # +# freq # Set sampling frequency, unit: Hz. # +# # : Numerical value among list: # +# # {100k, 50k, 20k, 10k, 5k, 2k, 1k, 500, 200 # +# # 100, 50, 20, 10, 5, 2, 1} # +# # Default value: 100Hz # +# # # +# acqtime # Set acquisition time, unit: s. # +# # : For limited acquisition duration: # +# # Numerical value in range: [100u; 100] # +# # For infinite acquisition duration: # +# # Numerical value '0' or string 'inf' # +# # Caution: Maximum acquisition time depends on other # +# # parameters. Refer to table below. # +# # Default value: 10s # +# # # +# acqmode # Set acquisition mode: dynamic or static. # +# # dynamic: current can vary, range [100nA; 10mA] # +# # static: current must be constant, range [2nA; 200mA] # +# # : String among list: {'dyn', 'stat'} # +# # Default value: 'dyn' # +# # # +# funcmode # Set optimization of acquisition mode dynamic (applicable # +# # only with command 'output' set to parameter 'current'): # +# # optim: priority on current resolution (100nA-10mA), # +# # max sampling frequency at 100KHz. # +# # high: high current (30uA-10mA), high sampling frequency # +# # (50-100KHz), high resolution. # +# # : String among list: {'optim', 'high'} # +# # Default value: 'optim' # +# # # +# output # Set output type. # +# # current: instantaneous current # +# # energy: integrated energy, reset after each sample sent # +# # (integration time set by param 'freq', # +# # limited at 10kHz max (<=> 100us min)). # +# # : String among list: {'current', 'energy'} # +# # Default value: 'current' # +# # # +# format # Set measurement data format. # +# # Data format 1: ASCII, decimal basis. # +# # Format readable directly, but sampling # +# # frequency limited to 10kHz. # +# # Decoding: 6409-07 <=> 6409 x 10^-7 = 640.9uA # +# # Data format 2: Binary, hexadecimal basis. # +# # Format optimized data stream size. # +# # Decoding: 52A0 <=> (2A0)16 x 16^-5 = 640.9uA # +# # : String among list: {'ascii_dec', 'bin_hexa'} # +# # Caution: Data format depends on other # +# # parameters. Refer to table below. # +# # Default value: 'ascii_dec' # +# # # +# trigsrc # Set trigger source to start measurement acquisition: # +# # trigger source SW (immediate trig after SW start), # +# # trigger from external signal rising or falling edge on # +# # Arduino connector D7 (via solder bridge). # +# # : String among list: {'sw', 'd7'} # +# # Default value: 'sw' # +# # # +# trigdelay # Set trigger delay between target power-up and start # +# # measurement acquisition, unit: s, resolution: 1ms. # +# # : Numerical value in range [0; 30] # +# # Default value: 1m # +# # # +# currthres # Set current threshold to trig an event, unit: A. # +# # Event triggered when threshold exceeded: signal generated # +# # on Arduino connector D2 or D3 (via solder bridge) # +# # and LED4 (blue) turned on. # +# # : Numerical value in range [100n; 50m] # +# # or value '0' for threshold disable # +# # Default value: 1m # +# # # +# pwr # Set target power supply connection. # +# # Automatic: On first run, power-on when acquisition start. # +#() # Then, power state depends on command 'pwrend'. # +# # Manual: Force power state. # +# # Note: Can be used during acquisition. To perform # +# # successive power off and on, it is preferable # +# # to use command 'targrst'. # +# # Optionally, connection status can be sent at the beginning # +# # and end of acquisition data stream. # +# # : Set pwr: String among list: {'auto', 'on', 'off'} # +# # Default value: 'auto' # +# # Get pwr: String 'get' (response: state 'on' or 'off') # +# # : Optional, string among list: {'nostatus', 'status'} # +# # Default value: 'nostatus' # +# # # +# pwrend # Set target power supply connection to be applied after # +# # acquisition: power-on or power-off. # +# # : String among list: {on, off} # +# # Default value: 'on' # +# # # +# # # +################################################################################ +# Measurement acquisition operation # +################################################################################ +# start # Start acquisition (measurement of current or energy # +# # depending on configuration). # +# # # +# stop # Stop acquisition. If acquisition is set to a finite duration, # +# # it will stop when reaching the target duration. # +# # # +# targrst # Reset target by disconnecting power supply during # +# # a configurable duration, unit: s. # +# # Note: Can be performed during acquisition to monitor target # +# # transient current consumption during its power-up. # +# # : Numerical value in range [10m; 1] # +# # or value '0' to let target powered-down # +# # # +# temp # Get temperature from temperature sensor on PowerShield board, # +# # on unit: Degree Celsius or Fahrenheit. # +# # : String among list: {degc, degf} # +# # Default value: 'degc' # +# # # +################################################################################ +# Board state operation # +################################################################################ +# autotest # Perform board autotest and display autotest results. # +#() # Note: Autotest is done at PowerShield power-up. # +#() # : Optional: string among list: {start, status} # +# # or no argument equivalent to value: 'start' # +# # : Optional: results status all or minimal (ok - not ok) # +# # string among list: {stat_all, stat_min} # +# # # +# calib # Perform board self-calibration. # +# # Note: New calibration should be performed when temperature # +# # shifts of more than 5 degC since the previous # +# # calibration. # +# # Note: Calibration is done at PowerShield power-up # +# # and after each update of power supply voltage level. # +# # # +################################################################################ +# Note: Numerical values of arguments can be formatted either: # +# - Numerical characters only (possible when numbers are >= 1) # +# - Numerical characters with unit characters 'u', 'm', 'k', 'm' # +# - Numerical characters with power of ten '-xx' or '+xx' # +# (xx: number on 2 digits maximum) # +# Example: Value '2 milliseconds' can be entered with: '2m' or '2-3' # +################################################################################ +# Table of maximum acquisition time possible in function of # +# sampling frequency and data format, # +# for a baudrate of 3686400 bauds: # +# ______________________________________________________________________ # +# | format freq | acqtime max (corresp. nb of samples) | # +# |____________________________________________________________________| # +# | ascii_dec | <= 5k | unlimited (unlimited) | # +# | ascii_dec | 10k | 1s ( 10 000) | # +# | ascii_dec | 20k | 500ms ( 5 000) | # +# | bin_hexa | <=100k | unlimited (unlimited) | # +# |____________________________________________________________________| # +################################################################################ +""" \ No newline at end of file diff --git a/benchmark/runner/runner_utils.py b/benchmark/runner/runner_utils.py new file mode 100644 index 00000000..698ace64 --- /dev/null +++ b/benchmark/runner/runner_utils.py @@ -0,0 +1,32 @@ +import yaml + +def get_baud_rate(dut_config, mode=None): + if "baud" not in dut_config: + raise ValueError(f"No baud rate found for device: {device_name}") + + baud = dut_config["baud"] + if isinstance(baud, dict): + if not mode: + raise ValueError(f"Mode required to resolve baud for device '{device_name}'") + mode_map = {'e': 'energy', 'p': 'performance', 'a': 'accuracy'} + baud_key = mode_map.get(mode.lower()) + if baud_key and baud_key in baud: + return baud[baud_key] + else: + raise ValueError(f"Baud mode '{mode}' not found for device: {device_name}") + return baud + + + +def print_tee(str_to_print, outfile=None, line_end="\n"): + """ + prints str_to_print to the stdout and optionally also to a file + If outfile is a string, it opens that file and writes str_to_print + to it. If outfile is an open filehandle, write str_to_print to the file. + """ + print(str_to_print) + if outfile and isinstance(outfile, str): + with open(outfile, 'a') as fpo: + fpo.write(str_to_print+line_end) + elif outfile and isinstance(outfile, io.IOBase) and not outfile.closed: + outfile.write(str_to_print+line_end) \ No newline at end of file diff --git a/benchmark/runner/script.py b/benchmark/runner/script.py index c8e27fa9..d273db94 100644 --- a/benchmark/runner/script.py +++ b/benchmark/runner/script.py @@ -1,162 +1,466 @@ import re +import numpy as np +from datetime import datetime +from device_under_test import DUT # Import DUT class +global_loop_count = None # This will store the loop count globally +performance_timed_out = False # True when 10 seconds have passed +file_processed = False +import logging +import sys, os +import concurrent.futures +import time +import threading +import streaming_ww_utils as sww_util -class _ScriptStep: - """Base class for script steps - """ - def run(self, io, dut, dataset): - return None +watchdog_flag = {"timeout": False} +watchdog_lock = threading.Lock() +current_time = datetime.now().strftime("%Y%m%d_%H%M%S") +os.makedirs("sessions", exist_ok=True) +os.makedirs(os.path.join("sessions", current_time), exist_ok=True) +log_filename = os.path.join("sessions", current_time, "log.txt") + +# Setup logging to file and console with NO extra formatting +logging.basicConfig( + level=logging.INFO, + format="%(message)s", # Removes timestamp and log level + handlers=[ + logging.FileHandler(log_filename, mode='w'), # Log to file + logging.StreamHandler(sys.stdout) # Print to console + ] +) + +# Redirect print statements to logging +class LoggerWriter: + """Custom writer to redirect stdout/stderr to logging.""" + def __init__(self, level): + self.level = level + + def write(self, message): + if message.strip(): # Avoid logging empty messages + self.level(message.strip()) + + def flush(self): + """Ensure real-time logging output.""" + for handler in logging.getLogger().handlers: + handler.flush() + +# Redirect all standard outputs to logging +sys.stdout = LoggerWriter(logging.info) # Capture stdout +sys.stderr = LoggerWriter(logging.error) # Capture stderr for errors +print(f"Logging initialized. Writing output to {log_filename}") + + +class _ScriptStep: + """Base class for script steps""" + def run(self, io, dut, dataset, mode): + return None class _ScriptDownloadStep(_ScriptStep): - """Step to download a file to the DUT - """ - def __init__(self, index=None): - self._index = None if index is None else int(index) + """Step to download a file to the DUT""" + def __init__(self, index=None, model=None): + self._index = None if index is None else int(index) + self.model = model + self._segments = None + self._current_index = 0 + self._current_segment_index = 0 + self.total_length = 0 - def run(self, io, dut, dataset): - file_truth, data = dataset.get_file_by_index(self._index) - if data: - dut.load(data) - return file_truth + def run(self, io, dut, dataset, mode): + # Fetch the file and data + if(self.model == "ad01" and self.total_length != 0): + if (self._current_segment_index == self.total_length): + self._current_index += 1 + self._current_segment_index = 0 + self._segments = None + file_truth, data = dataset.get_file_by_index(self._current_index) + else: + file_truth, data = dataset.get_file_by_index(self._index) + + # Define the current time for formatted output + current_time = datetime.now() + formatted_time = current_time.strftime("%m%d.%H%M%S") + + if self._segments is None and self.model == "ad01": + total_size = len(data) + segment_size = int(file_truth.get('bytes_to_send')) # Unified variable + stride = int(file_truth.get('stride')) + max_size = total_size + self._segments = [] + start = 0 + while start + segment_size <= max_size: + end = start + segment_size + self._segments.append(data[start:end]) + start = start + stride # Move start by stride to create overlap + self.total_length = len(self._segments) + if mode in ['p', 'e']: + # performance and energy mode use only the 1st segment. Only accuracy + # uses all the segments. It might be marginally faster to conditionally skip + # the segment[] construction, but this is easy. + self._segments = self._segments[:1] + self.total_length = 1 + self._current_segment_index = 0 + + # Conditional print statements based on 'mode' + if data: + print(f"{formatted_time} ulp-mlperf: Loading file {file_truth['file']} segment {self._current_segment_index}") + if(self.model == "ad01"): + segment = self._segments[self._current_segment_index] + dut.load(segment) + self._current_segment_index += 1 + else: + dut.load(data) + formatted_time = datetime.now().strftime("%m%d.%H%M%S") + print(f"{formatted_time} ulp-mlperf: Load complete.") + else: + print(f"WARNING: No data returned from dataset read. Script index = {self._index}, Dataset index = {dataset._current_index}") + file_truth['total_length'] = self.total_length if self.model == "ad01" else None + return file_truth class _ScriptLoopStep(_ScriptStep): - """Step that implements a loop of nested steps - """ - def __init__(self, commands, loop_count=None): - self._commands = [c for c in commands] - self._loop_count = None if loop_count is None else int(loop_count) - - def run(self, io, dut, dataset): - i = 0 - result = None if self._loop_count == 1 else [] - - while self._loop_count is None or i < self._loop_count: - loop_res = {} - for cmd in self._commands: - r = cmd.run(io, dut, dataset) - if r is not None: - loop_res.update(**r) - i += 1 - if self._loop_count != 1: - result.append(loop_res) - else: - result = loop_res - - return result + """Step that implements a loop of nested steps""" + def __init__(self, commands, loop_count=None, model=None): + self._commands = [c for c in commands] + self._loop_count = None if loop_count is None else int(loop_count) + self.model = model + def run(self, io, dut, dataset, mode): + global global_loop_count + # some logic is different for the streaming ww test + is_streaming_test = any([isinstance(c, _ScriptStreamStep) for c in self._commands]) + i = 0 + result = [] + start_time = time.time() if mode == "p" else None + + if self._loop_count is None or self._loop_count < 0: + self._loop_count = dataset.get_num_files() + print(f"No loop count specified. Using full set ({self._loop_count} test files)") + while (self._loop_count is None or i < self._loop_count): + loop_res = {} + with watchdog_lock: + if watchdog_flag["timeout"]: + print("[WATCHDOG] Loop timeout. Restarting current loop iteration.") + watchdog_flag["timeout"] = False # reset for next iteration + r = cmd.run(io, dut, dataset, mode) + for cmd in self._commands: + r = cmd.run(io, dut, dataset, mode) + if r is not None: + loop_res.update(**r) + if self.model == "ad01": + total_length = loop_res.get('total_length', None) + if total_length is not None and self._loop_count is not None and i == 0: + self._loop_count *= total_length + global_loop_count = self._loop_count # Store in global variable + i += 1 + + result.append(loop_res) + + if mode == "p": + # Error 1: Loop count not exactly 5 + if self._loop_count != 5 and not is_streaming_test: + result.append({"error": "error 1"}) + + # Error 2: Loop finished before 10 seconds + duration = time.time() - start_time + if duration < 10.0 and i >= self._loop_count: + result.append({"error": "error 2"}) + return result class _ScriptInferStep(_ScriptStep): - """Step to execute infer on that dut - """ - def __init__(self, iterations=1, warmups=0): - self._iterations = int(iterations) - self._warmups = int(warmups) - self._infer_results = None - self._power_samples = [] - self._power_timestamps = [] - - def run(self, io, dut, dataset): - result = dut.infer(self._iterations, self._warmups) - - infer_results = _ScriptInferStep._gather_infer_results(result) - - result = dict(infer=infer_results) - if dut.power_manager: - timestamps, samples = _ScriptInferStep._gather_power_results(dut.power_manager) - print(f"samples:{len(samples)} timestamps:{len(timestamps)}") - result.update(power=dict(samples=samples, - timestamps=timestamps - ) - ) - return result - - @staticmethod - def _gather_infer_results(cmd_results): - result = {} - for res in cmd_results: - match = re.match(r'^m-results-\[([^]]+)\]$', res) - if match: - result["results"] = [float(x) for x in match.group(1).split(',')] - continue - match = re.match(r'^m-lap-us-([0-9]+)$', res) - if match: - key = "end_time" if "start_time" in result else "start_time" - result[key] = int(match.group(1)) - if "start_time" in result and "end_time" in result: - result["elapsed_time"] = result["end_time"] - result["start_time"] - return result - - @staticmethod - def _gather_power_results(power): - samples = [] - timeStamps = [] - if power: - for x in power.get_results(): - if isinstance(x, str): - match = re.match(r"^TimeStamp: ([0-9]{3})s ([0-9]{3})ms, buff [0-9]{2}%$", x) - ts = float(f"{match.group(1)}.{match.group(2)}") - timeStamps.append((ts, len(samples))) + """Step to execute infer on the DUT""" + def __init__(self, iterations=1, warmups=0, skip_time=0, loop_count=None): + self._iterations = int(iterations) + self._warmups = int(warmups) + self.skip_time = float(skip_time) + self._infer_results = None + self._power_samples = [] + self._power_timestamps = [] + self.throughput_values = [] + self._loop_count = loop_count + + + def run(self, io, dut, dataset, mode): # mode passed to run + raw_result = dut.infer(self._iterations, self._warmups) + print(f"Running inference with {self._warmups}/{self._iterations} (warmup/measured) iterations ... ", end="") + infer_results = _ScriptInferStep._gather_infer_results(raw_result, mode) + print(f" done") + infer_results["iterations"] = self._iterations + infer_results["warmups"] = self._warmups + + result = dict(infer=infer_results) + + if mode == "e": + timestamps, samples = _ScriptInferStep._gather_power_results(dut.power_manager) + print(f" Captured samples:{len(samples)} timestamps:{len(timestamps)}") + # Read power values from the log file using timestamps + power_values = None + + result.update(power=dict(samples=samples, + timestamps=timestamps, + extracted_power=power_values # <-- NEW: Power values from the file + ) + ) + else: + self._print_AP_results(infer_results,mode) + + return result + @staticmethod + def _gather_power_results(power): + # this method should really be done inside the power manager, since + # other emon devices will structure the raw data different + samples = [] + timeStamps = [] # this is what the EEMBC runner calls "timestamps" + clock_ticks = [] # this is what the LPM01a calls "timestamps" + if power: + for x in power.get_results(): + if isinstance(x, str): + if x.startswith("TimeStamp"): + match = re.match(r"^TimeStamp:[ ><]([0-9]{3})s ([0-9]{3})ms, buff [0-9]{2}%$", x) + ts = float(f"{match.group(1)}.{match.group(2)}") + clock_ticks.append((ts, len(samples))) + if len(clock_ticks) > 1 and clock_ticks[-1][1]-clock_ticks[-2][1] != 1000: + expected_samples = clock_ticks[-2][1] + 1000 + print(f"At time {ts}: expected {expected_samples}, but we have {clock_ticks[-1][1]}.") + elif x.startswith("event"): + match = re.match(r"event (\d+) ris", x) + event_num = match.group(1) + timeStamps.append((event_num, len(samples))) + else: + samples.append(x) + return timeStamps, samples + + @staticmethod + def _gather_infer_results(cmd_results, mode): + result = {} + total_inferences = 0 + for res in cmd_results: + if res is None: + continue + match = re.match(r'^m-results-\[([^]]+)\]$', res) + if match: + try: + results = [float(x) for x in match.group(1).split(',') if x.strip()] + result["results"] = results + total_inferences += 1 # this results vector is the output of 1 inference, not a collection of multiple inferences + except ValueError as e: + print(f"ERROR: Failed to parse infer results: {e}. Data: {match.group(1)}") + result["results"] = [] + continue + match = re.match(r'^m-lap-us-([0-9]+)$', res) + if match: + key = "end_time" if "start_time" in result else "start_time" + result[key] = int(match.group(1)) + if mode != "e" and "start_time" in result and "end_time" in result: + result["elapsed_time"] = result["end_time"] - result["start_time"] + elif mode != "e": + print("ERROR: Incomplete time data, missing start_time or end_time.") + result["total_inferences"] = total_inferences + return result + + def _print_AP_results(self, infer_results,mode): + """ + Accumulates throughput values for all loop iterations and calculates median throughput + at the end of all iterations. + """ + global global_loop_count + # Use the total_inferences from _gather_infer_results results + num_inferences = self._iterations + + # Retrieve elapsed time (in microseconds) + elapsed_time_us = infer_results.get("elapsed_time", 0) + + # Get the current time in the desired format + current_time = datetime.now() + formatted_time = current_time.strftime("%m%d.%H%M%S") + + # Calculate throughput + if elapsed_time_us > 0: + elapsed_time_sec = elapsed_time_us / 1_000_000 # Convert to seconds + throughput = num_inferences / elapsed_time_sec # Calculate throughput else: - samples.append(x) - return timeStamps, samples + elapsed_time_sec = 0 + throughput = 0 + if mode == "p": + infer_results["throughput"] = throughput + # Add throughput to the list of throughput values + self.throughput_values.append(throughput) + # Print the old format performance results for each inference (every loop) + print(f"{formatted_time} ulp-mlperf: Performance results for window {len(self.throughput_values)}:") + print(f"{formatted_time} ulp-mlperf: # Inferences : {num_inferences:>13}") + print(f"{formatted_time} ulp-mlperf: Runtime : {elapsed_time_sec:>10.3f} sec.") + print(f"{formatted_time} ulp-mlperf: Throughput : {throughput:>10.3f} inf./sec.") + print(f"{formatted_time} ulp-mlperf: m-results : {infer_results['results']}") class _ScriptStreamStep(_ScriptStep): - """Step to stream audio from an enhanced interface board - """ - def __init__(self, file_name=None): - self._file_name = file_name + """Step to stream audio from an enhanced interface board""" + def __init__(self, index=None): + self._current_index = 0 + self._index = None if index is None else int(index) + + def run(self, io, dut, dataset, mode): + file_truth = dataset.get_file_by_index(self._index) + dut.stop_detecting() # in case it wasn't stopped earlier + dut.start_detecting() # instruct DUT to pulse GPIO when wakeword detected + io.record_detections() # intfc starts recording timestamp of GPIO pulses + time_str = datetime.now().strftime("%H:%M:%S") + print(f"Playing {file_truth['wav_file']} (length = {file_truth['length_sec']}s) at {time_str}... ", end="") + # play_wave is a blocking call, will pause here until wav finishes + io.play_wave(file_truth['wav_file'], timeout=file_truth["length_sec"]+10.0) + + # not sure why this is needed, but apparently the DUT is still occupied with the + # detection task, because w/o this sleep the next DUT command times out. + time.sleep(0.25) + detection_info = dut.stop_detecting() # DUT stops processing audio and toggles D7 to end power measurement + print(" ... done") + try: + activations = sww_util.array_from_strings(detection_info, 'target activations:', end_str='m-ready') + except ValueError as e: + if re.search(r"expected but not found\.", str(e)): + print("No activation data found.") + else: + raise e + activations = [] + + + detected_timestamps = io.print_detections() # intfc prints out WW detection timestamps + detected_timestamps = sww_util.process_timestamps(detected_timestamps) + + dutycycle_response = io.print_dutycycle() # direct the interface board to print out dutycycle timestamps + dutycycle_info = sww_util.process_dutycycle(dutycycle_response) + + infer_results = {} + infer_results.update(file_truth) + infer_results["detections"] = detected_timestamps + infer_results["iterations"] = 1 # always 1, but keep for consistency w/ other tests + infer_results["warmups"] = 0 # same but 0 + + result = dict(infer=infer_results, + dutycycle=dutycycle_info, + activations=activations + ) + + if mode == "e": + timestamps, samples = _ScriptInferStep._gather_power_results(dut.power_manager) + print(f"samples:{len(samples)} timestamps:{len(timestamps)}") + + # Read power values from the log file using timestamps + power_values = None + + result.update(power=dict(samples=samples, + timestamps=timestamps, + extracted_power=power_values + ) + ) + return result - def run(self, io, dut, dataset): - io.play_wave(self._file_name) - return dict(audio_file=self._file_name) +class _WatchdogStep(_ScriptStep): + def __init__(self, timeout): + self.timeout = float(timeout) + self._timer_thread = None + self._last_reset_time = time.time() + def _watchdog_thread(self): + while True: + time.sleep(0.5) + with watchdog_lock: + elapsed = time.time() - self._last_reset_time + if elapsed >= self.timeout: + watchdog_flag["timeout"] = True + print(f"[WATCHDOG] Timeout reached after {elapsed:.2f}s") + break + + def run(self, io, dut, dataset, mode): + with watchdog_lock: + self._last_reset_time = time.time() + watchdog_flag["timeout"] = False + + if self._timer_thread is None or not self._timer_thread.is_alive(): + self._timer_thread = threading.Thread(target=self._watchdog_thread, daemon=True) + self._timer_thread.start() + return {} class Script: - """Script that executes a test - """ - def __init__(self, script): - self.name = script.get("name") - self.model = script.get("model") - self.truth = script.get("truth_file") - self._commands = [s for s in self._parse_steps(script.get("script", []))] - - def _parse_steps(self, steps): - for step in steps: - contents = None - if isinstance(step, dict): - step, contents = list(step.items())[0] - yield self._create_step(step, contents) - - def _create_step(self, step, contents): - parts = step.split(' ') - cmd = parts[0] - args = parts[1:] - if cmd == 'download': - return _ScriptDownloadStep(*args) - if cmd == 'loop': - return _ScriptLoopStep(self._parse_steps(contents), *args) - if cmd == 'infer': - return _ScriptInferStep(*args) - - def run(self, io, dut, dataset): - with io: - with dut: + """Script that executes a test""" + def __init__(self, script): + self.name = script.get("name") + self.model = script.get("model") + self.truth = script.get("truth_file") + self._commands = [s for s in self._parse_steps(script.get("script", []))] + + def _parse_steps(self, steps): + for step in steps: + contents = None + if isinstance(step, dict): + step, contents = list(step.items())[0] + yield self._create_step(step, contents) + + def _create_step(self, step, contents): + parts = step.split(' ') + cmd = parts[0] + args = parts[1:] + if cmd == 'download': + # Pass the model into the download step + return _ScriptDownloadStep(*args, model=self.model) + if cmd == 'loop': + # Pass the model into the loop step and its commands + loop_count = int(args[0]) if args else None + return _ScriptLoopStep(self._parse_steps(contents), loop_count, model=self.model) + if cmd == 'infer': + # Pass the loop_count to the infer step + loop_count = args[-1] if args else None # Assuming loop_count is passed as last argument + return _ScriptInferStep(*args, loop_count=loop_count) + if cmd == 'reset': + #resets the watchdog timer + return _WatchdogStep(*args) + if cmd == 'stream': + # Pass the model into the download step + return _ScriptStreamStep(*args) + + def run(self, io, dut, dataset, mode): result = None - for cmd in self._commands: - r = cmd.run(io, dut, dataset) - if result is None: - result = r - elif isinstance(r, dict): - if isinstance(result, dict): - result.update(**r) + if io != None: + with io: + with dut: + result = None + for cmd in self._commands: + r = cmd.run(io, dut, dataset, mode) # Pass boolean flag + if result is None: + result = r + elif isinstance(r, dict): + if isinstance(result, dict): + result.update(**r) + else: + result.append(r) + else: + if isinstance(result, dict): + result.update(res=r) + else: + result.extend(r) + elif dut != None: # Accuracy or performance mode + with dut: + for cmd in self._commands: + r = cmd.run(io, dut, dataset, mode) + result = self._merge_results(result, r) + else: + raise RuntimeError("Missing required device instance.") + + return result + + def _merge_results(self, current, new): + if current is None: + return new + if isinstance(new, dict): + if isinstance(current, dict): + current.update(**new) else: - result.append(r) - else: - if isinstance(result, dict): - result.update(res=r) + current.append(new) + else: + if isinstance(current, dict): + current.update(res=new) else: - result.extend(r) - return result + current.extend(new) + return current + diff --git a/benchmark/runner/sd_card/long_wav.wav b/benchmark/runner/sd_card/long_wav.wav new file mode 100644 index 00000000..fd888977 Binary files /dev/null and b/benchmark/runner/sd_card/long_wav.wav differ diff --git a/benchmark/runner/sd_card/marvin_617de221_0.wav b/benchmark/runner/sd_card/marvin_617de221_0.wav new file mode 100755 index 00000000..aa288583 Binary files /dev/null and b/benchmark/runner/sd_card/marvin_617de221_0.wav differ diff --git a/benchmark/runner/sd_card/med_wav_2m_8p.wav b/benchmark/runner/sd_card/med_wav_2m_8p.wav new file mode 100644 index 00000000..2344acac Binary files /dev/null and b/benchmark/runner/sd_card/med_wav_2m_8p.wav differ diff --git a/benchmark/runner/sd_card/short_wav_easy10s.wav b/benchmark/runner/sd_card/short_wav_easy10s.wav new file mode 100755 index 00000000..ae40e12b Binary files /dev/null and b/benchmark/runner/sd_card/short_wav_easy10s.wav differ diff --git a/benchmark/runner/serial_device.py b/benchmark/runner/serial_device.py index d78ddd10..b73c4e53 100644 --- a/benchmark/runner/serial_device.py +++ b/benchmark/runner/serial_device.py @@ -2,32 +2,46 @@ from queue import Empty, Queue from threading import Thread -import serial - - +import serial, time + class SerialDevice: - def __init__(self, port_device, baud_rate, end_of_response="", delimiter="\n"): + def __init__(self, port_device, baud_rate, end_of_response="", delimiter="\n", echo=False): + print(f"Initializing SerialDevice on port: {port_device} at {baud_rate} baud") # Debug print self._port = serial.Serial(port_device, baud_rate, timeout=0.1) self._delimiter = delimiter self._end_of_response = end_of_response self._message_queue = Queue() self._read_thread = None self._running = False - self._echo = False + self._echo = echo + self._timeout = 5.0 + self.full_debug = False + self._entry_count = 0 + # self.reset_port() # experimenting with whether or not this improves start-up reliability? def __enter__(self): - self._port.__enter__() - self._start_read_thread() + print(f"SerialDevice entering port {self._port.port}, entry_count (before increment) = {self._entry_count}") + if not self._entry_count: + self._port.__enter__() + self._start_read_thread() + self._entry_count += 1 return self def __exit__(self, *args): - self._stop_read_thread() - self._port.__exit__(*args) + print(f"SerialDevice exiting port {self._port.port}, entry_count (before decrement) = {self._entry_count}") + self._entry_count -= 1 + if not self._entry_count: + self._stop_read_thread() + self._port.__exit__(*args) def _read_loop(self): msg = "" while self._running: - char = self._port.read(1).decode() + try: + raw_char = self._port.read(1) + char = raw_char.decode() + except UnicodeDecodeError: + print(f"WARNING: Ignoring undecodeable byte: {raw_char}") if char and char not in '\n\r\0': msg = msg + char elif char == '\n': @@ -55,20 +69,27 @@ def write_line(self, text): self.write(self._delimiter) def read_line(self, timeout=None): + """ + Read from the serial port. If nothing is available within timeout seconds, returns None. + """ result = None + if timeout is None: + timeout = self._timeout try: result = self._message_queue.get(timeout=timeout) except Empty: pass return result - def send_command(self, command, end=None, echo=True): + def send_command(self, command, end=None, echo=False, timeout=None): if echo or self._echo: print(command + (self._delimiter if '\n' not in self._delimiter else '')) self.write_line(command) lines = [] while True: - resp = self.read_line() + resp = self.read_line(timeout=timeout) + if resp is None: + raise RuntimeError(f"No response to command {command}") end_of_resp = (end if end is not None else self._end_of_response) in resp if resp: lines.append(resp) @@ -76,3 +97,43 @@ def send_command(self, command, end=None, echo=True): break return lines if len(lines) != 1 else lines[0] + + def close_serial(self) -> None: + """Closes the serial communication.""" + if self._port and self._port.is_open: + self._port.close() + print("Serial connection closed.") + + def send_data(self, data: str) -> None: + """Sends the given data to the device.""" + self._port.write((data + "\n").encode()) + + def receive_data(self) -> str: + """Receives data from the device.""" + if not self._port.is_open: + print("Error: Serial port is closed. Attempting to reopen...") + self._port.open() # Reopen the port if needed + + try: + response = self._port.readline().decode().strip() + return response + except serial.SerialException as e: + print(f"SerialException: {e}") + return "" # Return an empty response instead of crashing + + def reset_port(self, timeout=5): + t0 = time.time() + self._port.reset_input_buffer() # flush buffers on host + self._port.reset_output_buffer() + # flush any partial command in progress on DUT, don't compare txd/rxd cmd + + self._port.write(self._delimiter.encode()) + print(f"Flushing port: {self._port}") + while(True): + b0 = self._port.read(1) + if b0 == b'': # nothing more to read + break + else: + print(b0.decode(), end="") + if timeout is not None and time.time() - t0 > timeout: + break \ No newline at end of file diff --git a/benchmark/runner/stream_wav_uart.py b/benchmark/runner/stream_wav_uart.py new file mode 100644 index 00000000..4548c4ed --- /dev/null +++ b/benchmark/runner/stream_wav_uart.py @@ -0,0 +1,264 @@ +import numpy as np +from scipy.io import wavfile +import time, re, argparse +import serial +from serial.tools import list_ports + +import logging +logger = logging.getLogger(__name__) + +def get_response(port, timeout=10): + t0 = time.time() + response = "" + end_str = "m-ready" + + while True: + char = port.read(1).decode() + if char and char not in '\r\0': + response = response + char + if end_str in response: + break + if timeout is not None and time.time() - t0 > timeout: + break + return response + +def get_name(port): + bytes_to_transmit = "name%".encode() + port.write(bytes_to_transmit) + name = get_response(port, timeout=2.0) + print(name) + return name + +def send_cmd_get_resp(cmd, port, timeout=2, check_echo=True, retries=5): + logging.info(f"\n {cmd}") + i_attempt = 0 + successful = False + response = "" + while not successful and i_attempt <= retries: + try: + port.write(cmd.encode()) + response = get_response(port, timeout=timeout) + logging.info(f" {response}") + + if "m-ready" not in response: + err_str = f"m-ready not receved after command '{cmd}'" + logging.error(err_str) + raise RuntimeError(err_str) + if check_echo: + match = re.search(r"Received command:\s*(.+)", response) + if match: + rcvd_cmd = match.group(1).strip() + echo_correct = (rcvd_cmd == cmd.rstrip("%")) + if not echo_correct: + err_str = f"Sent command {cmd}\n. DUT received {rcvd_cmd}" + logging.error(err_str) + raise RuntimeError(err_str) + else: + err_str = "'Received command:' line not found" + logging.error(err_str) + raise ValueError(err_str) + except: + i_attempt += 1 + info_str = f"Error caught on {cmd}, retry {i_attempt}" + logging.warning(f"Error caught on {cmd}, retry {i_attempt}") + print(info_str) + reset_port(port) + else: + successful = True + if not successful: + raise RuntimeError("send_cmd_get_resp failed after {i_attempt} retries") + return response + +def extract_int_array(s, header_str="m-features-"): + match = re.search(fr'{header_str}\[([^\]]+)\]', s) + if not match: + err_str = f"No '{header_str}' found in the input string." + logging.error(err_str) + raise ValueError(err_str) + + # Split the string of numbers, strip spaces, and convert to int + number_strings = match.group(1).split(',') + numbers = [int(n.strip()) for n in number_strings] + + return np.array(numbers, dtype=np.int16) + +def reset_port(port, timeout=5): + t0 = time.time() + port.reset_input_buffer() # flush buffers on host + port.reset_output_buffer() + # flush any partial command in progress on DUT, don't compare txd/rxd cmd + + port.write("%".encode()) + while(True): + b0 = port.read(1) + if b0 == b'': # nothing more to read + break + if timeout is not None and time.time() - t0 > timeout: + break + + +def get_features(wav_data, port, frame_size=512, num_frames=None, offset=0, max_str_len=1028): + # DUT has 80-character input buffer => max_str_len = 80 + error_count = 0 + bytes_per_msg = (max_str_len - 4)//2 # room for "db " + terminating \0; 2 chars/byte + bytes_per_msg = 2*(bytes_per_msg//2) # round down to next even number + sub_frame_len = bytes_per_msg // 2 # number of int16s per "db XXX" msg + + total_samples = len(wav_data) + # as currently written, this means that if you process C chunks starting at + # offset O, you actually need to specify num_chunks=O*chunksize+C + if num_frames is None or num_frames*frame_size > total_samples: + # num_chunks is unspecified or chunk_size*num_chunks requests more data than the wav + num_frames = total_samples // frame_size + elif num_frames*frame_size <= total_samples: + # the wav has more data than chunk_size*num_chunks requests + total_samples = num_frames*frame_size + print(f"Sample rate: {samplerate} Hz, Total samples: {total_samples}") + + # Loop through 512-sample chunks + specgram = None + activations = None + for i in range(offset, total_samples, frame_size): + frame = wav_data[i:i+frame_size] + print(f"\rChunk {i // frame_size} / {num_frames}. ", end="") + bytes_txd_this_frame = 0 + cmd = f"db load {2*len(frame)}%" # 2 bytes / int16 + response = send_cmd_get_resp(cmd, port) + + num_sub_frames = np.ceil(2*len(frame)/bytes_per_msg).astype(int) + for i_sub_frame in range(num_sub_frames): + sub_frame = frame[sub_frame_len*i_sub_frame:sub_frame_len*(i_sub_frame+1)] + out_str = "db " + for j, sample in enumerate(sub_frame): + # we need to transmit the values as + # 00-01-ff-00 => [256, 255] + swapped = ((sample & 0xFF) << 8) | ((sample >> 8) & 0xFF) + out_str += f"{swapped:04x}" + + out_str += "%" + + try: + bytes_txd_this_frame += len(sub_frame)*2 + response = send_cmd_get_resp(out_str, port, retries=0) + + if "m-load-done" in response: + if bytes_txd_this_frame != 2*len(frame): + err_str = "DUT done, but frame Tx not complete." + logging.error(err_str) + raise RuntimeError(err_str) + logging.info(f"DUT done receiving (frame transmission complete).") + else: + re_match = re.search(r'(\d+)\s+bytes received', response) + if re_match: + bytes_rcvd_this_frame = int(re_match.group(1)) + else: + err_str = "'bytes received' not found in response" + logging.error(err_str) + raise ValueError(err_str) + if bytes_rcvd_this_frame != bytes_txd_this_frame: + err_str = "Bytes received {bytes_rcvd_this_frame} != bytes transmitted {bytes_txd_this_frame}" + logging.error(err_str) + raise RuntimeError(err_str) + except (UnicodeDecodeError, RuntimeError, ValueError) as e: + previous_bytes_txd = bytes_txd_this_frame - len(sub_frame)*2 + retry_successful = False + i_attempt = 0 + + while not retry_successful and i_attempt < 5: + i_attempt += 1 + print(f"Caught exception. Re-trying transmission, attempt {i_attempt}") + error_count += 1 + try: + reset_port(port) + + send_cmd_get_resp(f"db setptr {previous_bytes_txd}%", port) + response = send_cmd_get_resp(out_str, port) + if "m-load-done" in response: + if bytes_txd_this_frame != 2*len(frame): + err_str = "DUT done, but frame Tx not complete." + logging.error(err_str) + raise RuntimeError(err_str) + logging.info(f"DUT done receiving (frame transmission complete).") + else: + re_match = re.search(r'(\d+)\s+bytes received', response) + if re_match: + bytes_rcvd_this_frame = int(re_match.group(1)) + else: + err_str = "'bytes received' not found in response" + logging.error(err_str) + raise ValueError(err_str) + if bytes_rcvd_this_frame != bytes_txd_this_frame: + err_str = f"Bytes received {bytes_rcvd_this_frame} != bytes transmitted {bytes_txd_this_frame}" + logging.error(err_str) + raise RuntimeError(err_str) + retry_successful = True + except: + pass + + if "m-load-done" not in response: + err_str = "m-load-done not received after transfer" + logging.error(err_str) + raise RuntimeError(err_str) + out_str = "extract_uart_stream%" + response = send_cmd_get_resp(out_str, port, timeout=10) + + + feature_vec = extract_int_array(response, header_str="m-features-") + output_vec = extract_int_array(response, header_str="m-activations-") + if specgram is None: + specgram = feature_vec.reshape(1, -1) + else: + specgram = np.vstack((specgram, feature_vec)) + + if activations is None: + activations = output_vec.reshape(1, -1) + else: + activations = np.vstack((activations, output_vec)) + + np.savez("temp_spec.npz", specgram=specgram, activations=activations) + print(f"Acquired spectrogram. Caught {error_count} errors") + return dict(specgram=specgram, activations=activations) + + +if __name__ == "__main__": + """ + Takes one positional argument + """ + + parser = argparse.ArgumentParser(prog="stream_wav_uart", description=__doc__) + parser.add_argument("--wav_file", type=str, help="wav file to stream to DUT", default="sd_card/long_wav_2ch.wav") + parser.add_argument("--specfile", type=str, help="npz file to save spectrogram to", default="specgram.npz") + parser.add_argument("--baud", type=int, help="baud rate for communicating with DUT", default=115200) + parser.add_argument("--verbose", help="Print out extra debug messages", action='store_true') + parser.add_argument("--offset", type=int, help="point in wav file to start extracting", default=0) + args = parser.parse_args() + + logging.basicConfig(filename='stream_wav_uart.log', level=logging.INFO) + + # Load WAV file and convert to mono if stereo + samplerate, data = wavfile.read(args.wav_file) + if data.ndim > 1: + print("Stereo detected — taking 1st channel to convert to mono.") + data = data[:,0] + + # find DUT. Assume that it's the only thing connected to a USB port + for p in list_ports.comports(): + if p.vid: + dut_port = serial.Serial(p.device, args.baud, timeout=0.1) + break + + # flush out any unretrieved response from previous commands + reset_port(dut_port) + + ## If you want to check that the DUT is alive, you can do this + # response = send_cmd_get_resp("name%", port) + # print(f"Name: {response}") + t_start = time.time() + print(f"Getting features") + captured_data = get_features(data, dut_port, frame_size=512, offset=args.offset) + t_end = time.time() + np.savez(args.specfile, **captured_data) + + + print(f"Saved spectrogram with shape {captured_data['specgram'].shape} to {args.specfile}") + print(f"Completed spectrogram readout in {t_end-t_start} s") diff --git a/benchmark/runner/streaming_ww_utils.py b/benchmark/runner/streaming_ww_utils.py new file mode 100644 index 00000000..fac3543f --- /dev/null +++ b/benchmark/runner/streaming_ww_utils.py @@ -0,0 +1,198 @@ +import numpy as np +import re + +from runner_utils import print_tee + + +def array_from_strings(raw_info, header_str, end_str='m-ready', data_type=None): + + ## Combine the strings into one long string then split bracketed substrings + raw_info = ''.join(raw_info) + pattern = re.escape(header_str) + r'\s*(\[.*?\])\s*' + re.escape(end_str) + match = re.search(pattern, raw_info, re.DOTALL) + if not match: + raise ValueError(f"Start ({header_str}) or end marker ({end_str}) expected but not found.") + raw_info = match.group(1) + + # split the long string into substrings based on brackets []. + bracket_matches = re.findall(r'\[([^\]]+)\]', raw_info) + array_strings = bracket_matches if bracket_matches else [raw_info] + + + ## Figure out what data type is requested + if data_type is None: # guess based on first value + first_value = array_strings[0].split(',')[0] + if '.' in first_value or 'e' in first_value: + data_type = converter = float + else: + data_type = converter = int + elif data_type in [int, float]: + converter = data_type + elif isinstance(data_type, np.dtype): + if np.issubdtype(dtype, np.integer): + converter = int + else: + converter = float + else: + raise ValueError(f"data_type is {data_type}. Must be either None, int, float, or a numpy dtype") + + + ## Now extract the data + number_lists = [] + for s in array_strings: + for val in s.split(','): + try: + number_lists.append(converter(val)) + except ValueError: + # Just replace an invalid value with the previous value to avoid corrupting the timing + print(f"WARNING: Invalid element '{val}' for conversion to {converter} at element {len(number_lists)}. Replacing with previous value.") + number_lists.append(number_lists[-1]) + + if len(number_lists) == 1: + number_lists = number_lists[0] # only 1 array, don't make it 2D + + return number_lists + +def process_timestamps(raw_result): + if raw_result[0] != 'Detection Timestamps (ms)': + raise ValueError(f"List must start with 'Detection Timestamps (ms)'. First element is {raw_result[0]}") + if raw_result[-1] != 'm-ready': + raise ValueError(f"List must end with 'm-ready'. Last element is {raw_result[-1]}") + + try: + timestamps = [int(value.strip(',')) for value in raw_result[1:-1]] + except ValueError: + raise ValueError("One or more values in the list cannot be converted to an integer") + print(timestamps) + return timestamps # leave as list so we can dump to json later + + +def process_dutycycle(raw_result): + if raw_result[0].find('Duty cycle start times') < 0: + raise ValueError(f"Duty cycle response must start with 'Duty cycle start times (s)'. First element is {raw_result[0]}") + if raw_result[-1].find('m-ready') < 0: + raise ValueError(f"List must end with 'm-ready'. Last element is {raw_result[-1]}") + + proc_start_times = [] + proc_stop_times = [] + + target_list = proc_start_times + # start populating proc_start_times, until we see stop-times message, then populate proc_stop_times + endstr_found = False + for i,line in enumerate(raw_result[1:]): + if endstr_found: + print(f"Warning: Duty cycle response continues beyond 'm-ready'. Ignoring extra content") + break + if line.find('Duty cycle stop times (s)') >= 0: + # end of start-times, beginning of stop-times. + target_list = proc_stop_times + continue + if line.find('m-ready') > 0: + line = line.replace('m-ready', '') + endstr_found = True + + target_list += [int(numstr) for numstr in line.strip().split(',') if numstr] + + proc_start_times = np.array(proc_start_times)*10e-6 + proc_stop_times = np.array(proc_stop_times)*10e-6 + + if len(proc_stop_times) != len(proc_start_times): + err_str = f"Number of start times ({len(proc_start_times)}) and number of " + err_str += f"stop times ({len(proc_stop_times)}) should be equal" + raise RuntimeError(err_str) + on_times = proc_stop_times - proc_start_times + periods = np.diff(proc_start_times) + periods_fractional_var = (np.max(periods) - np.min(periods))/np.mean(periods) + if periods_fractional_var > 0.02: # > 2% variation + print(f"WARNING: Frame period variation exceeds 2%.", + f"Min period = {np.min(periods*1e3):.3f} ms. ", + f"Max period = {np.max(periods*1e3):.3f} ms") + avg_period = np.mean(periods) + avg_on_time = np.mean(on_times) + avg_duty_cycle = avg_on_time / avg_period + + results = {'duty_cycle':avg_duty_cycle, + 'period':avg_period, + 'processing_time':avg_on_time, + 'start_times_s':list(proc_start_times), + 'stop_times_s':list(proc_stop_times) + } + + print(f"Duty cycle = {avg_duty_cycle:.3f}, Period = {avg_period*1e3:.3} ms") + return results + +def calc_detection_stats(measured_timestamps_ms, true_det_windows, + false_pos_suppresion_delay_sec=1.0, + debounce_time_sec=1.0 + ): + + if len(measured_timestamps_ms) == 0: + raise RuntimeError("No detections captured. There should be at least one to mark the" + "beginning of the run" + ) + measured_timestamps_ms = np.array(measured_timestamps_ms) + detection_start = measured_timestamps_ms[0] + fp_timestamps_ms = measured_timestamps_ms[1:] - detection_start + + true_positives = [] + false_negatives = [] + + for i, (t_start, t_stop) in enumerate(true_det_windows): + t_stop += false_pos_suppresion_delay_sec + tp_indices = np.where((fp_timestamps_ms/1000 >= t_start) & + (fp_timestamps_ms/1000 <= t_stop+false_pos_suppresion_delay_sec))[0] + if len(tp_indices) > 0: + true_positives.append(t_start) + fp_timestamps_ms = np.delete(fp_timestamps_ms, tp_indices) + else: + false_negatives.append(t_start) + + i=0 # use while here b/c each loop we remove elements from fp_timestamps_ms + while i < len(fp_timestamps_ms): + current_fp = fp_timestamps_ms[i] + + fp_idxs_to_suppress = np.where((fp_timestamps_ms > current_fp) & + (fp_timestamps_ms <= current_fp+int(debounce_time_sec*1000)))[0] + if len(fp_idxs_to_suppress) > 0: + fp_timestamps_ms = np.delete(fp_timestamps_ms, fp_idxs_to_suppress) + i += 1 + return true_positives, false_negatives, fp_timestamps_ms/1000 + +def replace_env_vars(str_in, env_dict=None): + """ + Replaces any sub-strings enclosed by curly braces in str_in with the value + of the corresponding variable from env_dict. + env_dict: a dict (or dict-like) of the form {'VAR_NAME':'value'} + """ + if env_dict is None: + env_dict = os.environ + + matches = re.findall(r"{(\w+)}", str_in) + new_str = str_in + for env_var_name in matches: + if env_var_name in env_dict: + env_var_value = env_dict[env_var_name] + # Replace the enclosed string and curly braces with the value of the environment variable + new_str = new_str.replace("{" + env_var_name + "}", env_var_value) + else: + raise ValueError(f"Environment variable {env_var_name} not found") + + return new_str + +def summarize_sww_result(results_list, power, results_file=None): + for res in results_list: + inf_res = res["infer"] + true_pos_sec, false_neg_sec, false_pos_sec = calc_detection_stats( + inf_res["detections"], inf_res["detection_windows"]) + print(f"== File {inf_res['wav_file']} ({inf_res['length_sec']:2.1f} s) == ") + with np.printoptions(precision=3): + print_tee(f" True positives: {true_pos_sec}", outfile=results_file) + print_tee(f" False negatives: {false_neg_sec}", outfile=results_file) + print_tee(f" False positives: {false_pos_sec}", outfile=results_file) + print_tee(f"{len(true_pos_sec)} True positives, {len(false_neg_sec)} False negatives, {len(false_pos_sec)} False positives", outfile=results_file) + + if 'dutycycle' in res: + print_tee(f" Average duty cycle: {res['dutycycle'].get('duty_cycle'):1.5}") + print_tee(f" Average period: {res['dutycycle'].get('period'):1.5} s") + else: + print_tee(f"No duty cycle data recorded") \ No newline at end of file diff --git a/benchmark/training/streaming_wakeword/long_wav.wav b/benchmark/runner/sww_data_dir/long_wav.wav similarity index 100% rename from benchmark/training/streaming_wakeword/long_wav.wav rename to benchmark/runner/sww_data_dir/long_wav.wav diff --git a/benchmark/runner/sww_data_dir/short_wav_easy10s.wav b/benchmark/runner/sww_data_dir/short_wav_easy10s.wav new file mode 100644 index 00000000..ae40e12b Binary files /dev/null and b/benchmark/runner/sww_data_dir/short_wav_easy10s.wav differ diff --git a/benchmark/runner/sww_data_dir/sww_long_test.json b/benchmark/runner/sww_data_dir/sww_long_test.json new file mode 100644 index 00000000..442afb12 --- /dev/null +++ b/benchmark/runner/sww_data_dir/sww_long_test.json @@ -0,0 +1,57 @@ +[ + { + "wav_file": "long_wav.wav", + "detection_windows": [[9.457699148021609, 10.105324148021609], + [14.866165678266617, 15.627915678266616], + [29.943786017959138, 30.302411017959137], + [40.32364972086644, 41.22533722086644], + [71.60258229170311, 71.99676979170312], + [75.57735272129615, 76.11847772129614], + [89.17634151240425, 89.62071651240424], + [97.79050346636096, 98.48656596636096], + [110.9397651119379, 111.4783276119379], + [127.87707248408691, 128.76494748408692], + [132.38191493891796, 133.14497743891795], + [141.56004183815355, 142.54929183815355], + [149.32010817301082, 149.83217067301084], + [166.55561403976228, 167.54961403976228], + [178.40966631662045, 178.88360381662045], + [185.4232969562747, 185.8965469562747], + [192.904178291618, 193.482740791618], + [198.48536964291674, 199.36905714291674], + [211.5300562297426, 212.0262437297426], + [233.16532782338965, 233.80657782338966], + [254.19470632991752, 254.95283132991753], + [260.81755774050254, 261.75787024050254], + [266.34809708416185, 267.14253458416187], + [274.67550844370504, 275.29325844370504], + [285.39852514726283, 285.92683764726286], + [292.49966340899624, 293.22185090899626], + [302.3460304056669, 302.87628040566693], + [317.89990745866504, 318.304969958665], + [335.72569960586367, 336.1018871058637], + [339.9323432035216, 340.2247182035216], + [354.18497848970264, 354.78541598970264], + [366.49002026148355, 367.46270776148356], + [373.16182873429506, 373.7099537342951], + [386.9434694621524, 387.7437194621524], + [395.0541728315638, 395.74686033156377], + [399.2932943605985, 400.1296693605985], + [404.3458177829189, 405.3301302829189], + [410.9040638273914, 411.3441888273914], + [418.45050278921127, 418.94656528921126], + [441.25585954785487, 442.10542204785486], + [466.9332413514287, 467.5286163514287], + [481.23043434530354, 481.86305934530355], + [488.29791732445136, 489.25804232445137], + [496.47744390720834, 496.89019390720836], + [502.42084091952097, 503.30884091952095], + [528.0783744201342, 528.4529369201342], + [540.616396347511, 540.990646347511], + [546.8588128048474, 547.4488128048474], + [558.2905924746461, 558.7993424746461], + [570.0, 570.593]], + "length_sec": 1200.0, + "sample_rate": 16000 + } +] diff --git a/benchmark/runner/sww_data_dir/sww_med_test.json b/benchmark/runner/sww_data_dir/sww_med_test.json new file mode 100644 index 00000000..45a0190d --- /dev/null +++ b/benchmark/runner/sww_data_dir/sww_med_test.json @@ -0,0 +1,15 @@ +[ + { + "wav_file": "med_wav_2m_8p.wav", + "detection_windows": [[16.229071575753714, 16.876696575753716], + [20.000302140306424, 20.762052140306423], + [23.97231385867567, 24.33093885867567], + [56.577841864814765, 57.479529364814766], + [63.02169482052869, 63.41588232052869], + [81.38089587308035, 81.92202087308034], + [89.16674123163172, 89.61111623163171], + [101.55999914967485, 102.25606164967485]], + "length_sec": 120.0, + "sample_rate": 16000} +] + diff --git a/benchmark/runner/sww_data_dir/sww_short_test.json b/benchmark/runner/sww_data_dir/sww_short_test.json new file mode 100644 index 00000000..ba8e5101 --- /dev/null +++ b/benchmark/runner/sww_data_dir/sww_short_test.json @@ -0,0 +1,10 @@ +[ + { + "wav_file": "short_wav_easy10s.wav", + "sample_rate": 16000, + "length_sec": 10.0, + "detection_windows": [[1.0, 1.6476250000000001], [4.0, 4.76175], [7.0, 7.358625] + ] + } +] + diff --git a/benchmark/runner/tests.yaml b/benchmark/runner/tests.yaml deleted file mode 100644 index 907b9baf..00000000 --- a/benchmark/runner/tests.yaml +++ /dev/null @@ -1,25 +0,0 @@ -ad01: - name: anomoly_detection - model: ad01 - script: - - download - - a -ic01: - name: image_classification - model: ic01 - truth_file: y_labels.csv - script: - - download - - infer 10 1 -kws01: - name: keyword_spotting - model: kws01 - script: - - download - - a -vww01: - name: person_detection - model: vww01 - script: - - download - - a diff --git a/benchmark/runner/tests_accuracy.yaml b/benchmark/runner/tests_accuracy.yaml new file mode 100644 index 00000000..689ad871 --- /dev/null +++ b/benchmark/runner/tests_accuracy.yaml @@ -0,0 +1,40 @@ +ad01: + name: anomoly_detection + model: ad01 + truth_file: y_labels.csv + script: + - loop: + - download + - infer 1 0 # Infrences, Warmups + - reset 20 +ic01: + name: image_classification + model: ic01 + truth_file: y_labels.csv + script: + - loop: + - download + - infer 1 0 +kws01: + name: keyword_spotting + model: kws01 + truth_file: y_labels.csv + script: + - loop: + - download + - infer 1 0 +vww01: + name: person_detection + model: vww01 + truth_file: y_labels.csv + script: + - loop: + - download + - infer 1 0 +sww01: + name: streaming_wakeword + model: sww01 + truth_file: sww_long_test.json + script: + - loop: + - stream \ No newline at end of file diff --git a/benchmark/runner/tests_energy.yaml b/benchmark/runner/tests_energy.yaml new file mode 100644 index 00000000..44f6560d --- /dev/null +++ b/benchmark/runner/tests_energy.yaml @@ -0,0 +1,38 @@ +ad01: + name: anomoly_detection + model: ad01 + truth_file: y_labels.csv + script: + - loop 5: + - download + - infer 1500 0 +ic01: + name: image_classification + model: ic01 + truth_file: y_labels.csv + script: + - loop 5: + - download + - infer 20 0 +kws01: + name: keyword_spotting + model: kws01 + truth_file: y_labels.csv + script: + - loop 5: + - download + - infer 70 10 +vww01: + name: person_detection + model: vww01 + truth_file: y_labels.csv + script: + - loop 5: + - download + - infer 20 5 +sww01: + name: streaming_wakeword + model: sww01 + truth_file: sww_long_test.json + script: + - stream \ No newline at end of file diff --git a/benchmark/runner/tests_performance.yaml b/benchmark/runner/tests_performance.yaml new file mode 100644 index 00000000..cd66948f --- /dev/null +++ b/benchmark/runner/tests_performance.yaml @@ -0,0 +1,38 @@ +ad01: + name: anomoly_detection + model: ad01 + truth_file: y_labels.csv + script: + - loop 10: + - download + - infer 1500 10 +ic01: + name: image_classification + model: ic01 + truth_file: y_labels.csv + script: + - loop 10: + - download + - infer 20 5 +kws01: + name: keyword_spotting + model: kws01 + truth_file: y_labels.csv + script: + - loop 10: + - download + - infer 70 10 +vww01: + name: person_detection + model: vww01 + truth_file: y_labels.csv + script: + - loop 10: + - download + - infer 20 5 +sww01: + name: streaming_wakeword + model: sww01 + truth_file: sww_short_test.json + script: + - stream \ No newline at end of file diff --git a/benchmark/training/streaming_wakeword/build_long_wav.py b/benchmark/training/streaming_wakeword/build_long_wav.py index 9b96993c..ff8dd44a 100644 --- a/benchmark/training/streaming_wakeword/build_long_wav.py +++ b/benchmark/training/streaming_wakeword/build_long_wav.py @@ -7,9 +7,16 @@ Flags = util.parse_command("build_long_wav") -rel_thresh = 0.05 # trim out leading/trailing space with less than rel_thresh*max(waveform) +# trim out leading/trailing space with less than rel_thresh*max(waveform) +rel_thresh = Flags.rel_thresh samp_freq = Flags.sample_rate -wav_spec_file = "long_wav_spec.json" +wav_spec_file = Flags.wav_spec + +wav_filename = Flags.long_wav_name +specgram_filename = Flags.long_wav_name.rsplit('.',1)[0] # all but extension +specgram_filename += "_specgram.npz" +window_filename = Flags.long_wav_name.rsplit('.',1)[0] # all but extension +window_filename += "_ww_windows.json" try: with open('streaming_config.json', 'r') as fpi: @@ -82,18 +89,24 @@ def trim_and_normalize(wav_in, rel_thresh): # emulate INT16 quantization, dequant, so this spectrogram matches # one from reading the wav file. long_wav_int16 = (long_wav*(2**15)).astype(np.int16) +wavfile.write(wav_filename, 16000, np.stack((long_wav_int16, long_wav_int16), axis=1)) feature_extractor_long = get_dataset.get_lfbe_func(data_config_long) - -wavfile.write('long_wav.wav', 16000, long_wav_int16) - -# the feature extractor needs a label (in 1-hot format), but it doesn't matter what it is -# long_spec = feature_extractor_long({'audio':long_wav_int16/2**15, 'label':[0.0, 0.0, 0.0]})['audio'].numpy() long_spec = feature_extractor_long(long_wav_int16/2**15).numpy() print(f"Long waveform shape = {long_wav.shape}, spectrogram shape = {long_spec.shape}") -np.savez_compressed("long_specgram.npz", specgram=long_spec) +np.savez_compressed(specgram_filename, specgram=long_spec) + +wav_info = { + "length_sec": 10.0, + "detection_windows": ww_windows, + "sample_rate":Flags.sample_rate + } + +pretty_json_str = pprint.pformat(wav_info, compact=True).replace("'","\"") +pretty_json_str = pretty_json_str.replace("(","[").replace(")","]") -pretty_json_str = pprint.pformat(ww_windows, compact=True).replace("(","[").replace(")","]") -with open('long_wav_ww_windows.json', 'w') as fpo: - fpo.write(pretty_json_str) \ No newline at end of file +with open(window_filename, 'w') as fpo: + fpo.write(pretty_json_str) + fpo.write("\n") +print(f"Conversion complete. Wav file stored in {wav_filename}. Window file stored in {window_filename}.") \ No newline at end of file diff --git a/benchmark/training/streaming_wakeword/build_long_wav_def.py b/benchmark/training/streaming_wakeword/build_long_wav_def.py index 05521f10..6846b78c 100644 --- a/benchmark/training/streaming_wakeword/build_long_wav_def.py +++ b/benchmark/training/streaming_wakeword/build_long_wav_def.py @@ -5,7 +5,8 @@ Flags = util.parse_command("build_long_wav_def") long_wav_len_sec = 20*60.0 # 20 minutes -num_targets = 100 +num_targets_init = 100 +num_targets_final = 50 min_ww_ampl = 0.5 max_ww_ampl = 0.75 @@ -20,19 +21,31 @@ ('{musan_path}'+'/speech/librivox/speech-librivox-0164.wav', 100.0, 300.0, 0.05), ('{musan_path}'+'/speech/librivox/speech-librivox-0165.wav', 100.0, 300.0, 0.05), ('{musan_path}'+'/speech/librivox/speech-librivox-0166.wav', 100.0, 300.0, 0.05), - ('{musan_path}'+'/music/hd-classical/music-hd-0002.wav', 300.0, 450.0, 0.5), - ('{musan_path}'+'/music/jamendo/music-jamendo-0000.wav', 450.0, 600.0, 0.5), - ('{musan_path}'+'/speech/librivox/speech-librivox-0052.wav', 600.0, 1200.0, 0.5), + ('{musan_path}'+'/music/hd-classical/music-hd-0002.wav', 300.0, 450.0, 0.5), + ('{musan_path}'+'/music/jamendo/music-jamendo-0000.wav', 450.0, 600.0, 0.5), + ('{musan_path}'+'/speech/librivox/speech-librivox-0052.wav', 600.0, 900.0, 0.75), + ('{musan_path}'+'/music/jamendo/music-jamendo-0001.wav', 750.0, 900.0, 0.5), + ('{musan_path}'+'/speech/librivox/speech-librivox-0121.wav', 900.0, 1200.0, 0.2), + ('{musan_path}'+'/speech/librivox/speech-librivox-0122.wav', 900.0, 1200.0, 0.2), + ('{musan_path}'+'/speech/librivox/speech-librivox-0127.wav', 900.0, 1200.0, 0.2), + ('{musan_path}'+'/speech/librivox/speech-librivox-0133.wav', 900.0, 1200.0, 0.2), + ('{musan_path}'+'/speech/librivox/speech-librivox-0134.wav', 900.0, 1200.0, 0.2), + ('{musan_path}'+'/speech/librivox/speech-librivox-0136.wav', 900.0, 1200.0, 0.2), + ('{musan_path}'+'/speech/librivox/speech-librivox-0137.wav', 900.0, 1200.0, 0.2), ] -intervals = rng.exponential(scale=7.0, size=(num_targets)) +intervals = rng.exponential(scale=7.0, size=(num_targets_init)) # intervals < 3 sec may mess up the counting -intervals = intervals[intervals>3.0] -insertion_secs = np.cumsum(intervals[:50]) +intervals = intervals[intervals>4.0] +insertion_secs = np.cumsum(intervals[:num_targets_final]) # This should spread the words out in time, but if the parameters # are changed, then double check this. # stop the wake words 95% into the 1st half. insertion_secs *= (.475*long_wav_len_sec)/insertion_secs[-1] +if np.min(np.diff(insertion_secs)) < 3.0: + print(f"Warning: Some intervals are less than 3 seconds after time-scaling.") +if len(insertion_secs) < num_targets_final: + print(f"Warning: Only {len(insertion_secs)} target words remain after filtering.") ww_amplitudes = rng.uniform(low=min_ww_ampl, high=max_ww_ampl, size=(len(insertion_secs))) diff --git a/benchmark/training/streaming_wakeword/demo.ipynb b/benchmark/training/streaming_wakeword/demo.ipynb index ff72131d..435cbd7f 100644 --- a/benchmark/training/streaming_wakeword/demo.ipynb +++ b/benchmark/training/streaming_wakeword/demo.ipynb @@ -2,7 +2,7 @@ "cells": [ { "cell_type": "code", - "execution_count": null, + "execution_count": 1, "id": "386153cd-684f-4bca-a6ad-eca4bcccfb89", "metadata": {}, "outputs": [], @@ -36,17 +36,7 @@ }, { "cell_type": "code", - "execution_count": null, - "id": "d6132467-f897-42fe-a324-edd03ba13f0d", - "metadata": {}, - "outputs": [], - "source": [ - "rng = np.random.default_rng(2024)" - ] - }, - { - "cell_type": "code", - "execution_count": null, + "execution_count": 2, "id": "1db02f34-2ff4-43b2-b86d-0b46f3a4d42e", "metadata": {}, "outputs": [], @@ -56,7 +46,7 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 3, "id": "c0df306e-432a-4f12-a73a-cc945341dd40", "metadata": {}, "outputs": [], @@ -70,12 +60,14 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 4, "id": "7b889317-b130-4b06-97a6-93713873e60b", "metadata": {}, "outputs": [], "source": [ "notebook_mode = \"inference\" # \"inference\" OR \"short_training\" OR \"full_training\"\n", + "tfl_file_name = \"trained_models/str_ww_ref_model.tflite\"\n", + "random_seed = 2024\n", "\n", "if notebook_mode == \"inference\": \n", " load_pretrained_model = True\n", @@ -105,7 +97,17 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 5, + "id": "60fd410e-2dfb-4ded-8951-b4df9a6b2fe8", + "metadata": {}, + "outputs": [], + "source": [ + "rng = np.random.default_rng(random_seed)" + ] + }, + { + "cell_type": "code", + "execution_count": 6, "id": "07d86f7b-f4de-4b5e-9aed-85ddd5862714", "metadata": {}, "outputs": [], @@ -125,20 +127,60 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 7, "id": "a2b1aef4-9059-440a-8174-b685ddde8ffe", "metadata": {}, - "outputs": [], + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "About to get val data. " + ] + }, + { + "name": "stderr", + "output_type": "stream", + "text": [ + "2025-05-19 11:33:03.740227: I metal_plugin/src/device/metal_device.cc:1154] Metal device set to: Apple M1\n", + "2025-05-19 11:33:03.740247: I metal_plugin/src/device/metal_device.cc:296] systemMemory: 16.00 GB\n", + "2025-05-19 11:33:03.740253: I metal_plugin/src/device/metal_device.cc:313] maxCacheSize: 5.33 GB\n", + "2025-05-19 11:33:03.740275: I tensorflow/core/common_runtime/pluggable_device/pluggable_device_factory.cc:306] Could not identify NUMA node of platform GPU ID 0, defaulting to 0. Your kernel may not have been built with NUMA support.\n", + "2025-05-19 11:33:03.740288: I tensorflow/core/common_runtime/pluggable_device/pluggable_device_factory.cc:272] Created TensorFlow device (/job:localhost/replica:0/task:0/device:GPU:0 with 0 MB memory) -> physical PluggableDevice (device: 0, name: METAL, pci bus id: )\n" + ] + }, + { + "name": "stdout", + "output_type": "stream", + "text": [ + "Building dataset with 2796 targets, 1398 silent, and 9786 other.\n", + "About to get train data. Building dataset with 400 targets, 200 silent, and 1400 other.\n", + "About to get test data. Building dataset with 3088 targets, 1544 silent, and 10810 other.\n", + "Done building datasets\n" + ] + } + ], "source": [ "ds_train, ds_test, ds_val = get_dataset.get_all_datasets(Flags)" ] }, { "cell_type": "code", - "execution_count": null, + "execution_count": 8, "id": "9dcb33f3-9951-48b3-a54b-e83855c52846", "metadata": {}, - "outputs": [], + "outputs": [ + { + "data": { + "image/png": "iVBORw0KGgoAAAANSUhEUgAAAP4AAAPdCAYAAACqRtVUAAAAOnRFWHRTb2Z0d2FyZQBNYXRwbG90bGliIHZlcnNpb24zLjEwLjAsIGh0dHBzOi8vbWF0cGxvdGxpYi5vcmcvlHJYcgAAAAlwSFlzAAAPYQAAD2EBqD+naQAAmihJREFUeJzt/Xt0VOe57gs+c9ZlVpVUKkkI3YzAigHfiJ3YxizYjiEr22R7Z7sPxxlne8d9MkjS5xwTjDtsuoeHMaPb6rQPop3RDDJ6x2Tk0uDus4l3d4Md9o6TDevYEfEiK2uZBeEWyzfZCJAQupVKpbrPr//AyEjvU6YEUlAx398Y9YdezTm/75s135pVz3wvljHGQFEUT2Hf6AkoivLXRx1fUTyIOr6ieBB1fEXxIOr4iuJB1PEVxYOo4yuKB1HHVxQPoo6vKB5EHV9RPIh/pg788ssv40c/+hF6enpw9913Y8eOHfjKV75y1f1c18X58+cRjUZhWdZMTU9RbjqMMUgkEmhuboZtX+WebmaAV1991QQCAfPzn//cnD592vzgBz8wFRUV5pNPPrnqvt3d3QaAvvSlr2t8dXd3X9XPLGOmP0ln2bJluO+++7Bz585x25133ok1a9agvb39c/eNx+Oorq7Gigefhd/vjNt9//Su2PaD//keegx/Un7aVZyT2936330obMc+mC9sf3P7R8I2kgvRsd/vrZPzCbjC5rry20x2LChshmyHdJFPc798K30VOWELhaVtza3Hha3SlxG23mwVHfp0vFHY3v9E2uyR0r5khi8UWaM8lchVSluhUm4YGJLHnPtneS4i//gBH9v2SRv5VmoFAsJmslm5XRWZeEqecwBwx8akLTE64e88cngbb2B4eBixWIwe5zLT/lU/m83iyJEjeO655ybYV69ejcOHD4vtM5kMMpnPFptIJC5NzO/A7//MuXyWPJl2mDufXZBvsE/6FAIV0siOybYL5MgBAdgRub8vUBA2y5VztE2Jjm+V7vh2RF6svrDc36mU5zfkk/N2snI7APDnHWFj59LOlnbJ+ZzSHd8ll4EJyQ3ZMf0BeX78Fn9vS3Z8mzg+WY5ly3MGm9+HXStPbJPGMZendPWfyNMu7vX396NQKKChoWGCvaGhAb29vWL79vZ2xGKx8VdLS8t0T0lRlEnMmKo/+VPHGEM/iTZv3ox4PD7+6u7unqkpKYryKdP+Vb+urg4+n0/c3fv6+sS3AABwHAeOQ74mZvKwC599vTE5+RupGOxrVfSs/Nr6zx/J3/MV78uvef8QahW2Qpp87QMQ+kTuXyBfwfNhua8zWtpTjECC28lPcgRG5VucvCUibL86sVLY8hE5b9PIf4MyLHKO/LfI36rBoPwaOxohv38BVJ+U6zHkrcjWyrmnbiHj9MrjVVRU0LHdoWFhs8jPGXdEvkFWRJ5z45MXKtMHAAA5qUVcD9N+xw8Gg7j//vtx8ODBCfaDBw9ixYoV0z2coijXwIw8x9+0aRO+/e1v44EHHsDy5cvxs5/9DGfOnMG6detmYjhFUabIjDj+E088gYGBAfzwhz9ET08PlixZgjfeeAMLFiyYieEURZkiMxa5t379eqxfv36mDq8oynUwY45/vRQqArD8nwkdTss8sU31aS5R2FLHQ+hiWu7/D1LEqf5QioiDSanE+TL8eWtwVD4/zkWkaJeLEiGPHNIl71AwwceuPCvFq0y1VL7svBzbLbB4ARIXcJ7HTuRjcmw7J4+Z75EiV5Y8c7dT/L3NkLiUfIWcZ7h5VNiiYSlM9qdkwFX93iQdGy4JxBqV27JgHZvEyVlEsDYuf2+nO85Ok3QUxYOo4yuKB1HHVxQPoo6vKB5k1op7/kQWft9n4lCht09s0/DHKN03HyWRgGNSSKnsIUkkOSng1HbKfV0/j7IztrSHBqUwU3DkdoGEVCXdoPxsNkUC/JiQx6IYAyNyPq5PHjRynkSWEeEUAJIkgcU/Jo8ZHCaCX4RMsoiW5TokAzFDxNP3ZBZhH4lEjH0oxy4Mx+nYll+6ix2V16BhiTsRKRCblBScLR+PCEWhyIm/RvSOrygeRB1fUTyIOr6ieBB1fEXxIOr4iuJBZq2qDwsTyhqxfHzrgzN010BTvbCZ8xeEzam5XR4zK1X99ByZI+1PkhpQACrevSiNpOKpG5VPFArh0ko2+TN8bPZEIltd2lvsBqQS7U+zGGK+f6hfTpTl82dInrxFjsnCfQH+RCM7RyreplLa/CEZVhw8QgojFIGF0xaGhkrbOSPDhX31c+V2ROkHAKOqvqIo14s6vqJ4EHV8RfEg6viK4kFmrbhn5Q0sc4Xqw8Ilq3nTAPdCvzxeS7Owjd4iQ3sjF2RRw+CIFFYCI7z4pxuV+eYWEWZYoUXjL9GW5/Gs/iSpvU5CflmIK0m9R5bUDAiO8rFTJFSZiXtMtPOlS6tNAAA2qRvgIw1GzBwSZk32ZWuk9fMvHUBuGuL1CaYbmxSkddNcCCzpeNczGUVRyhN1fEXxIOr4iuJB1PEVxYPMWnHPjo/Ctj8T2vJ5KVwNrJKdcAAgeYv8PGM56GNNUtjpXSn3DfbL0xQ5xxsrRvplGJo/JW2pWikgVfZIYTEbJTnxlfzz2vXLOUV6pcg1eovcjkXu2US/TDYXG1vaWD5+gWhhqXnyvfVVcfHU9JKmpESsLAyThqhERAwUESsZLB8frPMNi7IjhTpNQhYENTl5Li7ZS+8kVQp6x1cUD6KOrygeRB1fUTyIOr6ieJBZK+6h4AKmSA7op/R/iaduukG5X/OHUsS549vvCVue5MG+88GtwhZbOkDHvviWjBBMNcmxqz6Qcx+skoIU69hDu/AAsEknZdcnj5mtkvun6kmxzR45dlbWsAQAFEgRTMxPCdOiJlk09cKobIl95xy5HQB01dYK2/mPZTec4MUi0XeTCA8QIa7IdcciJk2iSM/ySdBCnSTytFij9MLgsDSSSMJS0Tu+ongQdXxF8SDq+IriQdTxFcWDzFpxr3BxAJZFoqKuhOWSAvAnpUSSiUlbbXBM2P5w7gvCtnh+r7BVBXlKZB/rXBMnNffImWfiHOtcEyRRiACvz5eaS8Ymp9UnS8JREdEv9ToAQGaunGhlWEabsfNWXSsPelsFqV0IIOyTJ6mnr1rYfGl5grPVRCitkOcnNIWW1BZJlzWkvh7DjUth0A4XSfO9DiGPoXd8RfEg6viK4kHU8RXFg6jjK4oHmbXinuX3wbI+m57JkoYapIYaAARGpX2sUW5nk04OiWFZM29BjWya0DfGW3QzkSxAxMboWVKHjyxnrEFGoAXjpYt7/jHSBILoR2Mkco+JgG6Ajx0clPNM5uU5GqkeFrbV9aeF7S/JJjpO2Cevg4AjU1nzFaTeHwvSYwF+pM01wFtYW0EZGUm3Yym9QXKCLX4vZvsbkqpeKnrHVxQPoo6vKB5EHV9RPIg6vqJ4kCk7/qFDh/DYY4+hubkZlmXh9ddfn/B/Ywza2trQ3NyMcDiMVatW4dSpU9M1X0VRpoEpq/rJZBL33nsvvvvd7+Kb3/ym+P9LL72E7du3Y/fu3Vi8eDFefPFFPPLII+js7EQ0ypVwhpscg2t9Fp5pR0iHmiLp+iysNLFQSroZEjfr65Uq7WCjHHsgUUHHDielmhwalDaWZ2/niALvSIXZkK41AOAnx/SnyUkiKeTZKFGNydXhDPGxqz6RCnP/EnmAT26pEbaPq2Q+fTFqAjLM2iKh2zYpwMmS3auPyyc2bpGQXaail5yPT0J7WYcl1lK92NjXw5Qd/9FHH8Wjjz5K/2eMwY4dO7BlyxY8/vjjAIBXXnkFDQ0N2LNnD5566qnrm62iKNPCtP7G7+rqQm9vL1avXj1ucxwHK1euxOHDh+k+mUwGIyMjE16Kosws0+r4vb2XstgaGhom2BsaGsb/N5n29nbEYrHxV0tLy3ROSVEUwoyo+takyCdjjLBdZvPmzYjH4+Ov7u7umZiSoihXMK0hu42Nl+Jie3t70dT0WchlX1+f+BZwGcdx4BDhYzJ2TFZ5ZPnrAA9TtUhnlgspecxAguTy5+VpyvRKwQ8AKsicWJvtZKM8ZnhIbhfpk6JOspHXKWDj2Fkp7qXnyP0DRJR0faQldZYLXyPzSTFJci5GL0pRtLdRvg/+IsrtqYwM5Q07cqAM0c3ylaXn2ZeKFSAhuwHiVuTGZxHB2iST0zKvqzGtd/zW1lY0Njbi4MGD47ZsNouOjg6sWLFiOodSFOU6mPIdf3R0FB988MH4311dXTh27Bhqa2sxf/58bNy4EVu3bsWiRYuwaNEibN26FZFIBE8++eS0TlxRlGtnyo7/zjvv4Ktf/er435s2bQIArF27Frt378azzz6LVCqF9evXY2hoCMuWLcOBAwem9AxfUZSZZcqOv2rVKpjPqUlmWRba2trQ1tZ2PfNSFGUGmbX5+IKQFABDF4t1lCEfTGTT3qT8FpK7W0aGZfMyv9qfKJI3zYKxclKoqjpD8soHZSHKTIMUgOj6ALhBuciKU7IjjfFJoTVTLQU/y2XFKYv1epFk6ojIGpIniAl5FX5esDJAkuozOXkZ03x8Es1nnNI67gA8J95iOfWlRuSRCEx6PACQl+V1oUk6iuJB1PEVxYOo4yuKB1HHVxQPUjbiXqFWtlIuJnKxopX+T2SFyQsZKez4wjJSbqRfRptF+7nIVdkjo8j8SXnMwIW4sI3eXS9sBSLYOcO8qwoT4xJflpFuzpCcY2iIpCiTqD+bpP4CQPw2KUr5xuTc8ySFtsGRiVkpV0bEAUDQlucyFJTrGZojt2t6kwh5Jz+QtmKQIpooseuOycn5sCvIpEvrwnO96B1fUTyIOr6ieBB1fEXxIOr4iuJBykbcG2uRAhtr4wwATYdlmFPBkRFwdX+Wy++/V4pUDunMU3WGC2xMWIwvlGPX5KVwFhiVAlChlqTQjvH6a8lGGd1oF6T4lA/LdQeSJKU3I+doSKouAMQ+kgJbMC7HKZyXc/wvZ5bJAxa7JREtrZKUcJhLNLKqD2R9PN9cWe8vf/YcH5q0vy410dcOSXHZHZYCL436mwH0jq8oHkQdX1E8iDq+ongQdXxF8SBlI+4lSbvoAg/uwvDCsNx/npRhUo1EtLt3QNj6z1YL29jCIt08mPZVkGLcwL+Spz7WIYWvobtJM44U6XMNINIjBw8NkSYdARINGJeiUq6KiIAjXFj0ESHQrpbv2cgt8l7jBkuvhRcclnMPJOXYIVK/sP9LMg071iXPub+IuMfwVcl6gQzTeouw2UTgRXcP3b8wzWXn9Y6vKB5EHV9RPIg6vqJ4EHV8RfEg6viK4kHKRtVnobDF2mS7pF6hnWPtpqWaXOnIsMyRGlkEM5fhp872kzBXlyjRQamOD99B2lw3yPBjt1CkQOQF+TQjS8Ka2XnLVMv10JBol49NamBi5B55LluaB+U4bun3n4tDUpl3AzIkOpmWx7TIAwk3ILezK3gLdBayC9b+2pGPmzJzSNccsuxwnJeht7OyOKubltdlqegdX1E8iDq+ongQdXxF8SDq+IriQWatuGcFgrCsK1Q6ojOlG7i6l5Ep1nAdue0dd8tE7lpHimkDSSnMPHnHO3Ts/WeWCJshyuTQuZiwVbbKsMyaSErYklnebWVwESl4mZRinDMo55OeS87lXCkeuekil4xPCpNfvu2MsK2uO833n0ShyD2pI7pY2N6vmCtsrPtR/rQMr81G5TjhMA+JprnyeaIYVkiRNR+R82Fjh7rlvgDgnpveIpx6x1cUD6KOrygeRB1fUTyIOr6ieJBZK+6ZXBbmiq4rPqJtmGpZ4BEA3IIUr8JdMppq4d9clNv55DEHY1Lc+zdVx+jYb0duE7ZbK2W02t/1SqGJCXn//fw/Cdvx0RY69js+KdBdfE8qnaydtiE58SZJRESHF4MMhKTIlTdS0PrTyBeErcIno9K+EJbvDQD0jZHIPSKe+si5SNVKmy9L1p2R8wEAK0gKQJC21iYp30c7T1qGM226SLFNy0/GyfF5loLe8RXFg6jjK4oHUcdXFA+ijq8oHmTWinu+ujr47M/EFH9KiiPBCBc38jnS8pmIg++NyLbULHJvYVQKTR3JO+jY54ZkRF40QNIniQB5vr9a2Kpbk8L2YPRDOnZ1QM59z/tS3Es3kbbdw1KIy9XI7fxFxL1QWL4X50akgDlAUmjnhuUa3x+R0XgAcI6co0JO3r9qakeFbc6CIWHr/6I8P5X/wKPnkOVissAmYmNGnjeLiJ9uVJ4f4PqEPIbe8RXFg6jjK4oHUcdXFA8yJcdvb2/H0qVLEY1GUV9fjzVr1qCzs3PCNsYYtLW1obm5GeFwGKtWrcKpU6emddKKolwfUxL3Ojo68PTTT2Pp0qXI5/PYsmULVq9ejdOnT6Pi0zplL730ErZv347du3dj8eLFePHFF/HII4+gs7MT0SivJ8Yo9PdPSMs1toyIK3RV0n3DF6W4wmrCfXJogbBVP/KusH2cnCNsf4k30rHzOSnYHPtYRtpFzshTn62R+/7/FjwgbE/U/xMd20dCwcLzZGvoHJljzidrx7FUW7uLC1+jVaT2XI0UpCxS5zARkfumU7xNkmXLNf6bu+WN5Xtz3pbHNPKc/3vfv5WD/JwODXdMiqe2T16DVoC0Wv+L7M4TPEeuX5enmk938+wpOf7vfve7CX/v2rUL9fX1OHLkCB5++GEYY7Bjxw5s2bIFjz/+OADglVdeQUNDA/bs2YOnnnpq+mauKMo1c12/8ePxOACgtrYWANDV1YXe3l6sXr16fBvHcbBy5UocPnyYHiOTyWBkZGTCS1GUmeWaHd8Yg02bNuGhhx7CkiWXqs709vYCABoaGiZs29DQMP6/ybS3tyMWi42/Wlp4AoqiKNPHNTv+hg0bcPz4cfzqV78S/7Osib+xjTHCdpnNmzcjHo+Pv7q7ZTksRVGml2uK3HvmmWewf/9+HDp0CPPmzRu3NzZeErx6e3vR1NQ0bu/r6xPfAi7jOA4c0pTAVz93QuReJkYaJBR4e+XoWSmQDCxh0VTSNpqTczkzXC1sqTEihgEInJKRV7HzpFFGWs4xQTosvPORFCBZairAG1OkkmSeQ1I4s6zSWlVbef4BbpMGFr6AlKQMGSadlmJYbUxG8wHAg/WfCNtDVe8JW8SWUYcRSNvciBxn9N75dOzgoIzANFlScy9DbH4pqBpyM7RJSi8A+JukmOyOTpy7bbKA1HIpU7rjG2OwYcMG7Nu3D2+++SZaW1sn/L+1tRWNjY04ePDguC2bzaKjowMrVqyYylCKoswgU7rjP/3009izZw9+/etfIxqNjv9uj8ViCIfDsCwLGzduxNatW7Fo0SIsWrQIW7duRSQSwZNPPjkjC1AUZepMyfF37twJAFi1atUE+65du/Cd73wHAPDss88ilUph/fr1GBoawrJly3DgwIEpPcNXFGVmmZLjG/YDbRKWZaGtrQ1tbW3XOidFUWYYjdVXFA8ya/PxkU5PqEbI8vFjH/BdcxGplkalGIwU6bjTdaBV2EIDRJXn4jbmnCKqLPmmVIjIU5+aK9V25yPZ1eXiu8107FSTVNErP5Zqso9MkbUWZ92LsjLFHgBQmCNz1Qtx8rSmUm5XEZHFEnIFfk/qTcsJhGLymIsDstV1zsjzUx2UYbj5T4bp2OjpkzYfaRvul++tRVR95OV83CR/muGmrn5duabEegHQO76ieBJ1fEXxIOr4iuJB1PEVxYPMWnHPqq6CZX8mDgVHZYhrYIznLo/VyWUVSOQqqXWIgkOEONJ5hnVGAYBUPRHohmQIpy8lhZ26EzIkNFUnVbeRVjJxAFXvkVbM1XK7sUYiVo7JNbJOLz5SNxQAfANynosfkIpqU1hmXw5kpBAX9JGwVwB5EpY8XJBh0qeyA8IWJUUZ/v5PdwnbbXOKhM26Ug22iEBHi3KyXJVKOW87xEPBMRwXJjdRYnwuQe/4iuJB1PEVxYOo4yuKB1HHVxQPMmvFPTM6BnNFTnWykQhXVVzkSrUQYYjkm4dqpVJVUyGFncERKcLk+3nRyWGpFSH6kRRsXHLm/URTStWTNs5Fcud9ASkgpeukQmfPlevOZMi5JO2n7WF+ydiN8pg2mSezNRDBryclOxIBwNm4tL+OLwvbu1EZ3fhBUnbnIUtEtpoX+vSf7Jf7sw3DMtrSYracvE7dQdntB+CFPq8HveMrigdRx1cUD6KOrygeRB1fUTzI7BX3crmJxQiZCFPDI/esMGnv3CMFtnkLh4XtvlpZ5XfvkBSPvnTPR3Ts072yKGKiiuS8xqXNRwpW2qS9t8u1J7hBIjWRzjWFEVJsMyQj0CIxqTZmQix/F/jbhZ3C1hKSQlWBFBRlHYC6kzV0nJFRKaoe7ZcFSTtjsgV6alReAyYs150mHY0AwBmVKbNWgKTgZlkHIbluUy2rUllFIvfsAknhTRcJoywBveMrigdRx1cUD6KOrygeRB1fUTzIrBX34LoT8kIDo1KkYp1wAMAMSPEqH5b71zgyGurNc4uF7f/45QPCNpjnLbqP/fkLwmaTebKONMZPovR8crvAKF+3GyDiHhHTCpVSTGMFlH2kJfX8+kE69ldjsr14S0Cmxvbmq4WNpdWO5biCaQpk7Tlp8/vk3CuqSMTiuzIS0JcrUk3aJZ2BWJk7IvgZIvjh3AVpYzX8cH1CHkPv+IriQdTxFcWDqOMrigdRx1cUDzJrxT2rYS4s32dRTKw+nj/JRS5fWtqzd8gotH8+0yJsS27pETaWSvrKX5bRsVmEoSFn2WIl5UiOaHCEHZAPbRORKx8htQrjRPAjUZARRwpSt1ZycS9gSeHrVGaesPkgx/kwLaPs+kdlHT4AcFPkZBLBb3RUpsG6Y3LfxuPyZFa/00vHLpB27hSXREsOyPNmR6SoaRUZg217Pam6esdXFA+ijq8oHkQdX1E8iDq+ongQdXxF8SCzVtV3YxG4V6j6LlH1q98nXUwA9N9DPs9IPj5rDX3ClUUahzMyBzwQ4GMXyBOFUL+cDxHBEUiQ4pQkfLTg8KcZeSKEOwNy7GxMHtPNye2qgrIYgFOkw81/6lsqbKM5ec4bwrL7y7tDUtVPDvFipsGL8pLNRUkIMgvtJbUJWEek/Ecf07EppEOOxcJubWmzq2Q+vpvkSj0N+b0O9I6vKB5EHV9RPIg6vqJ4EHV8RfEgs1bcszo/hmV9lpOd+9sviW38pDglADjDJIdd1tDE8F1S2HFCMsF6JC1FqrHzPB8/TMQ0Fp5LOjazZj+8sCbX9ngrcPIO52vkhOrqpOg2mJJhou+9dw8d2ybvhVshF9lVI/PK06NykeGPeD6+Myxt+YgUzvID0lYIyRNc9T5pP01H5tBQ2qQsymlHSxPyLB+/pg0TDPNcaC0FveMrigdRx1cUD6KOrygeZNb9xjefFn/LTypmVsjI34aFLM9PLZAadzbZ1k2T4JgxMg75LeWmeA20Auk6y+qyGfYbn8yRlMyDsfmP/AJpvmHIz0A3JSdUGCM7E4qtGxnyG58IGQVH7u+m5K/qQqbIe0viWArk52+BnDeX5DPnyUlzaSE9jm3khNj+bDuGxd7wIsc0k2x55D61F8nbnjBOKVv9FTl79ixaWmSevKIopdHd3Y1582QthCuZdY7vui7Onz+PaDSKRCKBlpYWdHd3o6qq6kZP7boZGRm5adZzM60FuDnWY4xBIpFAc3MzbNKy60pm3Vd927bHP62sT+Ogq6qqyvbNYNxM67mZ1gKU/3piMVkunKHinqJ4EHV8RfEgs9rxHcfBCy+8AKfUIoeznJtpPTfTWoCbbz1XY9aJe4qizDyz+o6vKMrMoI6vKB5EHV9RPIg6vqJ4EHV8RfEgs9bxX375ZbS2tiIUCuH+++/HH/7whxs9pZI4dOgQHnvsMTQ3N8OyLLz++usT/m+MQVtbG5qbmxEOh7Fq1SqcOnXqxky2BNrb27F06VJEo1HU19djzZo16OzsnLBNuaxp586duOeee8aj85YvX47f/va34/8vl3VMC2YW8uqrr5pAIGB+/vOfm9OnT5sf/OAHpqKiwnzyySc3empX5Y033jBbtmwxe/fuNQDMa6+9NuH/27ZtM9Fo1Ozdu9ecOHHCPPHEE6apqcmMjIzcmAlfha9//etm165d5uTJk+bYsWPmG9/4hpk/f74ZHR0d36Zc1rR//37zm9/8xnR2dprOzk7z/PPPm0AgYE6ePGmMKZ91TAez0vEffPBBs27dugm2O+64wzz33HM3aEbXxmTHd13XNDY2mm3bto3b0um0icVi5qc//ekNmOHU6evrMwBMR0eHMab811RTU2N+8YtflP06psqs+6qfzWZx5MgRrF69eoJ99erVOHz48A2a1fTQ1dWF3t7eCWtzHAcrV64sm7XF45dq1NXW1gIo3zUVCgW8+uqrSCaTWL58edmu41qZdY7f39+PQqGAhoaGCfaGhgb09vK+5eXC5fmX69qMMdi0aRMeeughLFmyBED5renEiROorKyE4zhYt24dXnvtNdx1111lt47rZdal5V7GmtSayBgjbOVKua5tw4YNOH78ON5++23xv3JZ0+23345jx45heHgYe/fuxdq1a9HR0TH+/3JZx/Uy6+74dXV18Pl84lO2r69PfBqXG42NjQBQlmt75plnsH//frz11lsTqruU25qCwSAWLlyIBx54AO3t7bj33nvx4x//uOzWcb3MOscPBoO4//77cfDgwQn2gwcPYsWKFTdoVtNDa2srGhsbJ6wtm82io6Nj1q7NGIMNGzZg3759ePPNN9Ha2jrh/+W4pisxxiCTyZT9OqbMDRQWi3L5cd4vf/lLc/r0abNx40ZTUVFhPv744xs9tauSSCTM0aNHzdGjRw0As337dnP06NHxR5Hbtm0zsVjM7Nu3z5w4ccJ861vfmtWPjL7//e+bWCxmfv/735uenp7x19jY2Pg25bKmzZs3m0OHDpmuri5z/Phx8/zzzxvbts2BAweMMeWzjulgVjq+Mcb85Cc/MQsWLDDBYNDcd99944+PZjtvvfWWASBea9euNcZcevz1wgsvmMbGRuM4jnn44YfNiRMnbuykPwe2FgBm165d49uUy5q+973vjV9Tc+fONV/72tfGnd6Y8lnHdKD5+IriQWbdb3xFUWYedXxF8SDq+IriQdTxFcWDqOMrigdRx1cUD6KOrygeRB1fUTyIOr6ieBB1fEXxIOr4iuJB1PEVxYOo4yuKB1HHVxQPoo6vKB5EHV9RPIg6vqJ4EHV8RfEgM1ZX/+WXX8aPfvQj9PT04O6778aOHTvwla985ar7ua6L8+fPIxqN3pT1zBVlpjDGIJFIoLm5GbZ9lXv6TBTyu56ml93d3UULPOpLX/q6+qu7u/uqfjYjxTaXLVuG++67Dzt37hy33XnnnVizZg3a29s/d994PI7q6mo8hH8NPwLXNL6vukoa/UFhKrTKRgnGJz8p7Uxe2EYXVPCx0/J05irlMXMR+W0m0lcQtmSTT84nR4cGyBcky5W2sQa5oSWXCFeeMqTnkgMC8KflMV05dcCW56dQIdcdiGbpOJZPjh8Mkv190tYUTQhb19/dKmzz3xikYxf+8j61T8a36AvClloQE7ZgXK5xeDG/rhIt7HqZeC4L2TRO/y//VwwPDyMWk+NdybR/1b/c9PK5556bYC/W9DKTySCTyYz/nUgkPp1YAH7rGh3fIlesLW2WPyRs1PHz0tP8AbkvAPgK8sI2AXlMNyjfSH9AXqy+IHH8Yr+ASnR8n0McnzgpPY1h7vg2G7xExzdhuW47wr+q2sTxfUH5qeUjjh+oyMjtHPk++n0OHdsq8Xr0kf395Frz++UafcEi1xV5z3xBfs8u5SfytIt7U2162d7ejlgsNv5qaWmZ7ikpijKJGVP1S20+uHnzZsTj8fFXd3f3TE1JUZRPmfav+lNteuk4DhyHf7W6Gtb9d1N735fkb3z2lTeYlF+VshXywylbHZE7F1FGLPkNEwXy7Y39Tk+S79s2+e3tJzrCpW2lfbRZHpPNMVst97Vz5Csj+aoOAK5PbhsckTZ2LgIJ+RU6k53CPWlIbmu+GBe27uFqYav+UF4YhQryGweAHZKTd9NpuaFfnvPUXOlquUq5Xa6Sf01n10vFhYlvZD5H3tgiTPsd/2ZueqkoNwsz8hx/06ZN+Pa3v40HHngAy5cvx89+9jOcOXMG69atm4nhFEWZIjPi+E888QQGBgbwwx/+ED09PViyZAneeOMNLFiwYCaGUxRlisxY5N769euxfv36mTq8oijXwYw5/l+Dnod4kMLIl+Tz2sj7UkDMpkhQxOoLwtZ/vkYOkucizNK7PxK2Uxcahe2rC94Ttr/7+HZhy2XlW5SPc/GJCY7BASJgNkmlaMH8fmG7p/acsP3ugzvp0PZ7MvAkIONlkJkj52PNlQJZ0xwpzgFA71/qhc2QeIFMp7w2Ckn5ntUMyyAaXzxFxy4wIY+RJ/EYGSKekpgPO8fFUxYgFT4/cZ75fInzgybpKIonUcdXFA+ijq8oHkQdX1E8SFmLezmShAcAVkIuq/EfpOD30b+VqpDjys/CurdlZNnAfTxZ5Z0ji4Ttv33oH4VtUViKiPWLpRrmkJCtd0eb6Njvx+cKW+ELUhRaUtsjbA/HpNg41zcibP8QvZWOPVAloxuj9w0I2y0BuZ57as8LW7LABczcYvme+Wz5XoT8MuRxICnn2D8mhdumAx/QsUul0Cn3ryQ2RkWERIkCcMfGrr6zKZa2KdE7vqJ4EHV8RfEg6viK4kHU8RXFg6jjK4oHKRtV33pgibCZIh9b/lFS4y5K1OCoVEEzOXlKIiTc0ulndaWASA/Z9mGpML89LNX/R+ecELa/pJqFbWlVFx37bLJa2CoC8mlGlV+GdjIF/8/p+XQchhuRYaouiT5trJDjMAX/fJKHY9eGpbodz8g8+XRevo+sDt9U0v7/Kvj4dTXdzLZlK4ryV0AdX1E8iDq+ongQdXxF8SCzVtyz/H5Y1mfTO/+wjM+NLeuj+/YPVwpbb6tUmpY0y3LfvcmosDWt+1DYBnt42OxgoxSaIj6Z850l3SaqfUl5vJzMcx8t8OKk3UPVwhbwS0Gre0SGqdYFRoWtISBz4r/XKnsjAMD/27dM2C4OyXM5FpVCXrogQ6KZEAcAI0TIK5Aw6yDZfzguzyULkE38u7+hY7OCrRZRMEfmy/c2MCq3i1yUB8yHeZ0HX5YopZNM+Vwa+PWv6f6T0Tu+ongQdXxF8SDq+IriQdTxFcWDzFpxz+TzMFe03Jp7TEagdd3LE/JNVoorbkAKKUxga6yQOfFfnSNz1ftTUkAEgMfu/nthW+TI3PsEaSlzdOxWYetLy3HurpL59ADwlflShFwYkQJozpVv+7lMtdyOVLGM2LyL7ZPz/0nYRm+Ra3wvKbsprYjJXPW5fhnhBwAfZWWxzVqfFCb/IbFQ2Pwkb//MF6WYFlopjwcAoykpqmb6iDwYlZGRTlhGicZJIdVCkruk5Uix0hQm3rfdVAEoTdvTO76ieBF1fEXxIOr4iuJB1PEVxYPMWnFvMgVHfkb5HSn4AUAuI0UpQwKfbEsa8yTXN14IC1tzJe/0ErJkCu47yVZh80EKTcdHbhG2oC1FnRq/jPADgADpf72y4l1hSxsZKffHpEwTPjrSImxjeV4Ec15kWNj+JipFuwRpNR31yc41twYG6Th3B6VYOezKOQ0WpChaG5Dn7b9m5b7ZPE+Nra6UKcFVtUPCFg1KcW8oI0XAQVL8MzKHi6fxMXkNJvsmRSJOIcdY7/iK4kHU8RXFg6jjK4oHUcdXFA8ye8U92wdYn4ksLP3RLRSpT0YyGwO9UsTJL5Cfe/Xh0rrZ/E21bIcN8IizPw5/QdgerJZ1806PyFTfIKmZVyx6bpREA94ekGIjIG3vZ+S6bdJ3e47DhcWzY9XS5swRtjvDsmtOyJLnt4KIpAAQs+Wb61jyfHwx1C1sTCD+5wopYL7XI6MDAaC1RgqOj9X/WdiYePrPIwuEbSwnt7stJtuVA0BPQNYgPDspcq8wpm2yFUX5HNTxFcWDqOMrigdRx1cUDzJ7xT23AFiffS7lK1g0Hq/LhoIUgNygFKqqSIRVlV+KaSwibqxI3bssaYgwkpOi21Be1n9jwlmORBL2ZKvp2IyYLSO+GEwMe9sno/lyJJUZAC6OyfX0Vcqae4wVFe8Lm8NLz8FHlNsQ2bZAzhuL5ruYlDafj7dAryRC62CB1PEj4mvYJwXMBVUy6i/ACvsB8BF7JDRxPgWXi74MveMrigdRx1cUD6KOrygeRB1fUTzIlB3/0KFDeOyxx9Dc3AzLsvD6669P+L8xBm1tbWhubkY4HMaqVatw6tSp6ZqvoijTwJRV/WQyiXvvvRff/e538c1vflP8/6WXXsL27duxe/duLF68GC+++CIeeeQRdHZ2IhotTeUFAP/8W+C3P1PODVFu3TRXmAOD0m4vlAUUF0RkCOZwTuZI92VlUc8B0uEGAKI++aSgnyjef3JvFbblc2QY75/jMkf/yDBvX90UljUCjmflfBb65ef9HKJENznyeH8auJWOPThCzgeJfJ0XHBC2L5OnGXEubiPHwojJk4sc5DXwSbZO2Fqr5XzSURlKC3Bl/vSobGNeF5TXmp/UVWDXX4iEhwPARwkZ/pxITnxa5MpyAUWZsuM/+uijePTRR+n/jDHYsWMHtmzZgscffxwA8Morr6ChoQF79uzBU089NdXhFEWZAab1N35XVxd6e3uxevXqcZvjOFi5ciUOH+Y91zKZDEZGRia8FEWZWabV8Xt7LzWhbGiYWDu9oaFh/H+TaW9vRywWG3+1tMhsKUVRppcZUfUta+IPcmOMsF1m8+bNiMfj46/ubhlBpijK9DKtIbuNjY0ALt35m5o+yy3v6+sT3wIu4zgOHEeGv5qRBIz1WUhiPiRFrmIfW4GE/JCJVsqCjseH5DE/uiAFoHxSij2r7z1Jx2a5+3URKV5F/FJMy5AONzESVhy0ea56oyN/Jv2XkXuFrdYvxadbgzIP/EsVnwjbPw/xb2SOI9fdl5Zi7ns+WXMgHvlY2C4WeFHPtJHnyAnKUNqQJd+zI3Epin4crxW2+SSUFgAcct7jGVbUs0i88SRODEthkBWABYAkKQqaG5noN26K78uY1jt+a2srGhsbcfDgwXFbNptFR0cHVqxYMZ1DKYpyHUz5jj86OooPPvisbHJXVxeOHTuG2tpazJ8/Hxs3bsTWrVuxaNEiLFq0CFu3bkUkEsGTTz45rRNXFOXambLjv/POO/jqV786/vemTZsAAGvXrsXu3bvx7LPPIpVKYf369RgaGsKyZctw4MCBKT3DVxRlZpmy469atQqGdaf4FMuy0NbWhra2tuuZl6IoM8iszccvDI/AukKgcf0s6ZqLKEESCsC6owy6MkqvMETy7EmL4rkkOgvgBS87z0ths5CT8soRW4pPX2iWotsoEXoA4J9ycv8lc2VL7QtjMs/+f9Mki0b+d1HZhSfY0kHH/l96/0bYHJ8Uw+oCsqhnjtxHzuWr6Ti3+IfJ/jLML+HKaD7WBSjok+8t63oDAO8NzBU2HxHjzjmyMGbMkSItqwUwNMLHDodJrr1rff7fn4Mm6SiKB1HHVxQPoo6vKB5EHV9RPMisFfcmY0gGbmCATz+YkILLoroLwjaclQJQulkeM0S60bw3yrutXEyR4o1+KSD5A9LWWC1VyQ+75TgVMRmFCABjo1KYPJy4Tdjm1rJuP3K7VZH3hG11mLev7qyWUX4nEjIycq6fdCoimhQrLgkAzT4pcjFxcCAv3weWHs3IpKVACwCjZ2V6tvHLwUcqZRSjO0cuMjEm36/aGO9U1Fgpz9vkJO7CGG8bz9A7vqJ4EHV8RfEg6viK4kHU8RXFg8xacc9XFYXP+izSakRqT8g3czFjbFCKM6xe2oWCzB+oCssIq56+amHzk4gvALhwUUZt3XbLRbldQopPZy7IFFE7IEWuPIlCBAA3IVNRa1uGhY3Vx+vtqRG2/1p1t7B9vZIXTm0KyFTWP2QXClvSlYJWwpX3HybOAcBp0lJ7ji2LzV3IyfchlZXnx2fL8ztKRDcAsLJSoPONyrkX8nK7CyQS0Q7Ka6i/n+e05AtynOTIpJp7XPOl6B1fUTyIOr6ieBB1fEXxIOr4iuJBZq24Z0UrYV3RUCPbIEWdmmoe5ZTxSXHv9JBMjb1wSkbFVS0i9daIaDYc5umTNTUyXTeVk/snR+UczRBJtyWpxxkfT8sNEKFpOC0FQzckBS2LCFJv9t8ubKxeHwD8JSXrx/UkpFD1x5BUae92zgrb2axsIAEAaSPXng7IaMK+nBw74siov75+GY3nZrl4Grkoz2+AnI6xJrldntQK9MXlWgpzuGg8lJfrCfZOvK7c9A2quacoSnmgjq8oHkQdX1E8iDq+ongQdXxF8SCzVtXPn+sBrii26YvIQocOyZMHgOHbZSjvvVGp1veE5DHjcanWG79UwTNJrqz7Se79IAnDDH8kw0Irz0hVNlNDktWL1FSsPCfnObyQKMxheYBCWI49lJb1Ct5JtNKxz45V80lNIlOQl9zO3r8VttEcD5utDMj3tsIvbVnSlWg0LY/pki5JpBP3JTOrCZGUG9fIGqUoBOT7wEoOWO/zJwrGlvbA2MSx86wwQRH0jq8oHkQdX1E8iDq+ongQdXxF8SCzVtybTGFMTrXPleGWxegclEKeCZVWBLPytBS5SFr5JbtP/oMF90YuSCGGiUf+MbmdxaM6ka4m+eKkZIGx5XbZuaSjzKic+Rt9MkcfAGIxmRPvGjkO665TINt9MizrAxTbNkBqI6RJ7n0qSQTVD+R1NXYLL/TJwnPn/kmGCxuLnN8GWQMhMChrP2QaeCh4tkpeHFWd8Ql/5wtabFNRlM9BHV9RPIg6vqJ4EHV8RfEgZSPu+YbJVK0i06+XIkeYRfmRHPQCKWRZ/aHcd/AuPrafFDx0hqVA509Jm0uCyGwyx/htPHTPIU1u/CSyLCNT9OEflutO2VLUDMa4gJRIyvoCNilk+e6QrIGQSMl9o6ToKcDbnWfz8r3IpElkZVye4OoPpTCYr+TRc0xoLZzqpNuKfU9KG4uzC1dxwTockGssDEx8w10ja1YUQ+/4iuJB1PEVxYOo4yuKB1HHVxQPUjbiHotqcyuLhLCRKD/bklLK3D/K7YxNbCTVNkBacQM8Uq5AovyYCGgT/THeKoU8N8DHLoRYuq20BYflvqlGKcQForI4pXG5sOjmyD3EL7eNBKQAFSAiYLZQJD2VRO5l0qRDDnnPCuS8BRJyO9fH74cuWc90UxiRLcxnAr3jK4oHUcdXFA+ijq8oHmRKjt/e3o6lS5ciGo2ivr4ea9asQWfnxAAGYwza2trQ3NyMcDiMVatW4dQp3mFVUZQbw5TEvY6ODjz99NNYunQp8vk8tmzZgtWrV+P06dOoqLiUdvjSSy9h+/bt2L17NxYvXowXX3wRjzzyCDo7OxGN8hbApWDniLCS5AKQQzqenEvKTjq15JChYSk0FYLyeMWEnoIMQoOPdDgZa5DHDF+UY4cG5L426a4DAH6ZGYs8mQ8TGy1yzDxpN27CXFD1h6Qy6RIhMEOi7PpJ2+5ISAqLAOD3EREyKMeurpDq6QjZLjVXRsr5SDtsAEVrHZYjU3L83/3udxP+3rVrF+rr63HkyBE8/PDDMMZgx44d2LJlCx5//HEAwCuvvIKGhgbs2bMHTz311PTNXFGUa+a6fuPH45cKAdTWXgr+7urqQm9vL1avXj2+jeM4WLlyJQ4fPkyPkclkMDIyMuGlKMrMcs2Ob4zBpk2b8NBDD2HJkiUAgN7eXgBAQ8PEr9UNDQ3j/5tMe3s7YrHY+KulpeVap6QoSolcs+Nv2LABx48fx69+9SvxP2tS6SFjjLBdZvPmzYjH4+Ov7u7ua52Soiglck2Re8888wz279+PQ4cOYd68eeP2xsZGAJfu/E1NTeP2vr4+8S3gMo7jwHGKFLC7gpa/Kz3l0MpLQWx4kUzT9GfkdjkS6eYGpC1XyccODcpjhoZIWu4YqRNXK8XKgkM+MHlJOIoTJ8JiI1ljk0yDtX0kDTXNLxkWUcfyTpMZ+T7URKUq6SORlgAwkJBCYGVYhkuyeoHZjIzw89eS1tcJOjQst/SGFbOdKd3xjTHYsGED9u3bhzfffBOtrRO7qrS2tqKxsREHDx4ct2WzWXR0dGDFihXTM2NFUa6bKd3xn376aezZswe//vWvEY1Gx3+3x2IxhMNhWJaFjRs3YuvWrVi0aBEWLVqErVu3IhKJ4Mknn5yRBSiKMnWm5Pg7d+4EAKxatWqCfdeuXfjOd74DAHj22WeRSqWwfv16DA0NYdmyZThw4MB1PcNXFGV6mZLjG3P13ziWZaGtrQ1tbW3XOidFUWYYjdVXFA9SNvn4gQPvCFv2Xy2l2xYi8vOM5skTtZ7l/TtxKaPnihZklLZMlRwnXS33D44y9V8ejyr9APKyNiYNLfaROpZMla+IyA3TRdT26io50Yt9MhyWFcusq0zKObIe0gAKlXKeF4fkz8hQSD4F8pOCq3n5kAAuf2uRvEXaZH+m8kDv+IriQdTxFcWDqOMrigdRx1cUD1I24h4jcuwMtedvleHBYdKWenSBDOtkkae5CpaPz+dkyEdpsEhhzskw3YzZ8ryTMqo+lhuzfHwWgmxIPn42KxcZCvM8+ZCfVApNE5WMNIph7bSHU0R1A5AvkDoGZE5jpCW2m5Lrqe8kXZLuKGu3KAm94yuKB1HHVxQPoo6vKB5EHV9RPEhZqxgmV3qOvusnAp2P5KWTMxLulwJQeg7paQ3AJd2Zw91yngVHzme0mbRCJvUB/LyDNBUWbXKKWF65/6KcuBuWO6dTZIEABojohqCMvvORYpkjaalANkV5CbZEVop2PUNSMWRCnjUmxUZfWr63ESIEA0AgefNU29Q7vqJ4EHV8RfEg6viK4kHU8RXFg5S3uJfiKpdVkOKMZaSoVH18QO48GJe22pgwBeM8sixTI8WvbLU8zYERKSpV9krbaJPcN1fBRSZmrzwvi3qO1cvP+0JEnh+btKpubeynY398YY6wBXulAJow8ry5tbLrTddgLR0nkyHnI0WKaA7I7XwZErFol1YkFAD8Yx4ttqkoys2BOr6ieBB1fEXxIOr4iuJBylvcu7OV2rMxKbCFT54VttSSecIWskmEX4gISpX81BVCUiwaq5PHrCNCXjYo552aK48XGKVD0/TfPJlPNkrq8CXlHO25RBjM8YhFu0sW/LNIR217RJ63sSQpvU66+Fw6qDSFLkoRMnRRbpcjw4TPy5M5dHsNHTpIuhKVK3rHVxQPoo6vKB5EHV9RPIg6vqJ4kLIW99wgnz7rxZC+Wwp5qXopVFmu7H/tH5U13UI9XGEL9UhbcFhGq6UaZSoqiziseV8qZP4kbzbhBokQmJD75yJSRGRRbdmEPBfxIv3Bw6TxR4A0CMmTZiesqQVLJwZAo+pYa/IC0SDZdtZ5GYlofFzcK9LjoyzRO76ieBB1fEXxIOr4iuJB1PEVxYOo4yuKBylrVT9whsRlAvDNkcUXDXkCEKGda4iR5Gwbh4euGlLAMzAqJeo8abPNOtyEBuS+mWo+NiM1V24bGpbytEmwop7SlifFPwHAl5XnjRX/ZDZnQO7LipZe2l+OX2AFTgflGiNn5aMHk0gIW5EHFwgOc3s5ond8RfEg6viK4kHU8RXFg6jjK4oHKWtxL99SR+2FcGnLGp0nVSE7L4Wm6lOyGGRiEen3DMAZJHn2JRbbZN158mEpAgbJvgBgZ6Wgla+QY7OwWUNEzUJQblcsbJXl3lf0SWOmSh4zU0PGIeHLAO90FBoi4qBfioDJFtlfPHZGFlJ1BunQCJIQ5HJF7/iK4kHU8RXFg6jjK4oHmXW/8S//1swjV7SxwTh53lCjkC9tWQUWdEJ+W+YLGWnL8bF9efn7O58jnVvpdvI3sU1sJs9/aNvEzsbO50hdQXLIQlbqC6zmHQCAnEu2nkKWNPMgtmK/8QuGBPDk5ORdIoOwY+ZdmXJdyPD3Nk/GyZvSOzbPNHlcmgvTayZjmVK2+ity9uxZtLS03OhpKErZ0t3djXnzZP2JK5l1ju+6Ls6fP49oNIpEIoGWlhZ0d3ejqoqr6OXEyMjITbOem2ktwM2xHmMMEokEmpubYZNq0Vcy677q27Y9/mllWZe+1lVVVZXtm8G4mdZzM60FKP/1xGLy8SRDxT1F8SDq+IriQWa14zuOgxdeeAGO49zoqUwLN9N6bqa1ADffeq7GrBP3FEWZeWb1HV9RlJlBHV9RPIg6vqJ4EHV8RfEg6viK4kFmreO//PLLaG1tRSgUwv33348//OEPN3pKJXHo0CE89thjaG5uhmVZeP311yf83xiDtrY2NDc3IxwOY9WqVTh16tSNmWwJtLe3Y+nSpYhGo6ivr8eaNWvQ2dk5YZtyWdPOnTtxzz33jEfnLV++HL/97W/H/18u65gWzCzk1VdfNYFAwPz85z83p0+fNj/4wQ9MRUWF+eSTT2701K7KG2+8YbZs2WL27t1rAJjXXnttwv+3bdtmotGo2bt3rzlx4oR54oknTFNTkxkZGbkxE74KX//6182uXbvMyZMnzbFjx8w3vvENM3/+fDM6Ojq+Tbmsaf/+/eY3v/mN6ezsNJ2dneb55583gUDAnDx50hhTPuuYDmal4z/44INm3bp1E2x33HGHee65527QjK6NyY7vuq5pbGw027ZtG7el02kTi8XMT3/60xsww6nT19dnAJiOjg5jTPmvqaamxvziF78o+3VMlVn3VT+bzeLIkSNYvXr1BPvq1atx+PDhGzSr6aGrqwu9vb0T1uY4DlauXFk2a4vH4wCA2tpaAOW7pkKhgFdffRXJZBLLly8v23VcK7PO8fv7+1EoFNDQ0DDB3tDQgN7e3hs0q+nh8vzLdW3GGGzatAkPPfQQlixZAqD81nTixAlUVlbCcRysW7cOr732Gu66666yW8f1MuvSci9zOSX3MsYYYStXynVtGzZswPHjx/H222+L/5XLmm6//XYcO3YMw8PD2Lt3L9auXYuOjo7x/5fLOq6XWXfHr6urg8/nE5+yfX194tO43GhsbASAslzbM888g/379+Ott96aUN2l3NYUDAaxcOFCPPDAA2hvb8e9996LH//4x2W3jutl1jl+MBjE/fffj4MHD06wHzx4ECtWrLhBs5oeWltb0djYOGFt2WwWHR0ds3Ztxhhs2LAB+/btw5tvvonW1tYJ/y/HNV2JMQaZTKbs1zFlbqCwWJTLj/N++ctfmtOnT5uNGzeaiooK8/HHH9/oqV2VRCJhjh49ao4ePWoAmO3bt5ujR4+OP4rctm2bicViZt++febEiRPmW9/61qx+ZPT973/fxGIx8/vf/9709PSMv8bGxsa3KZc1bd682Rw6dMh0dXWZ48ePm+eff97Ytm0OHDhgjCmfdUwHs9LxjTHmJz/5iVmwYIEJBoPmvvvuG398NNt56623DC7VB57wWrt2rTHm0uOvF154wTQ2NhrHcczDDz9sTpw4cWMn/TmwtQAwu3btGt+mXNb0ve99b/yamjt3rvna17427vTGlM86pgPNx1cUDzLrfuMrijLzqOMrigdRx1cUD6KOrygeRB1fUTyIOr6ieBB1fEXxIOr4iuJB1PEVxYOo4yuKB1HHVxQPoo6vKB5EHV9RPIg6vqJ4EHV8RfEg6viK4kHU8RXFg6jjK4oHmbG6+i+//DJ+9KMfoaenB3fffTd27NiBr3zlK1fdz3VdnD9/HtFo9KasZ64oM4UxBolEAs3NzbDtq9zTZ6KQ3/U0vezu7i5a4FFf+tLX1V/d3d1X9bMZKba5bNky3Hfffdi5c+e47c4778SaNWvQ3t7+ufvG43FUV1fjIfxr+BGY7qkpNxjLcYTNZDLTPo6vrq60DQt5aRoaLnkcKxAUNpPLlraz7ZPHs/m3XJOX85xMHjm8jTcwPDyMWCz2udtO+1f9y00vn3vuuQn2Yk0vM5kMMle88YlE4tOJBeC31PFvNizynhrLnfZxfLZ0SIorvxKzORaDr6fEe6lFHL/Iz1tTys9e8/nHuJJpF/em2vSyvb0dsVhs/NXS0jLdU1IUZRIzpuqX2nxw8+bNiMfj46/u7u6ZmpKiKJ8y7V/1p9r00nEcOOR333Rj33OHsJmA/KpViMiviP54StisMz10HCsclsaQXF++6xO6vzyg/LD0VVfTTdnvQCsov4rm75gvbPZYTh7QJ8d2g/KcAYBvlPxOJ8qylZHjWCNJekwGXWNArtGtjcp9g/Jyt0fke+ubW8vHZueyOiRsgb5ESftahYLcjlyTAOAblMfMnz1Hty2Fab/j38xNLxXlZmFGnuNv2rQJ3/72t/HAAw9g+fLl+NnPfoYzZ85g3bp1MzGcoihTZEYc/4knnsDAwAB++MMfoqenB0uWLMEbb7yBBQsWzMRwiqJMkRmL3Fu/fj3Wr18/U4dXFOU6mDHHv5HYkYiwnf1XUrApkEe9ld3yGawzIjes6hvig/uIYDhHCk3+dKOwuSxwhBzPqqrkY6eJwBaTY4PEbNnJtLCNLZLnLFvJxScnLs9RqGdU2NyQ3M5ypPBlx7ngV2iRgTm+ETl3lBoa4JMyVyFGBFoAhZB0l/QcItq58vz6iHjqhuW+mVoudEcSUoS8HjRJR1E8iDq+ongQdXxF8SDq+IriQcpa3LOWfpHaB+6W4ldygYySsqtlFtVwREZixT6Qn4/D//1tdOzad2VkWcWhd4XNzJPins0iwxqq5SBZuRYAsIneaIh4la8kkW6OzOYKXZCCUmCEJ7AwQYtGQQ5IwY8KbLVcwHQdIp7Wy20NyXLzZUikHNlurJmLe3mHHDMr1z3aIvcPJKVoF0jKayVXRDxN3lEvbJHExHNp3CwwQHcX6B1fUTyIOr6ieBB1fEXxIOr4iuJB1PEVxYOUjarPapul66UCDwDpOaT0EKmG1DgnLmznElK1HmmVSmtokA6NTEx+ljpf/IKwDd0ulV9DPoYrz5OnBO9epGMbkvdvDY0IW35xjbAVYnKNkbw8ablKfsn401Ixd1k+P3l6YJOnFFa+SMxtQc4pM1deG7603N/OkWP65UkPDfCaebmIXHumWp43N8DUf2krkCcU/jG+bvbUBJb9+X9/DnrHVxQPoo6vKB5EHV9RPIg6vqJ4kLIR9+ywFPKS9Xz6qQYphMRapJAXT8ljBmtkbncuLMcxAZ43XXlWjn3uYVkfIDWPhN0S/cb1y7H9KV4MMjBIioJm5RptEmbKbOk6kjtfpP9KOkLCgP1S0AokpXjlH5Pb2QUucuVDUhCziQjpDMj3MVMnzwUTAbPV/LpiIbvpWnnvDI7I+eRDcl/LlTZ/iq/bl5LXS+HiRJG3YEjB1CLoHV9RPIg6vqJ4EHV8RfEg6viK4kHKRtwrjMgINLtIA9HwBSmaJFukGJdLSPHqK1/sFLYn5v6jsFXbY3TstqX/jbBdvCgj5f7d7ceErUA+h1+bc6+w+dNSLAQAi6wxMFYlbIYENoYvkg43RMcrEIELAGwSUefLsGgzsjOxsag2AMgQ4S3ZKM9bOFYhbE5cCmfpOilK5sJ8jXl+2uV2JJ0/KBvhUGERLEIPgC8tL3a7auJ7a0wWkG5C0Tu+ongQdXxF8SDq+IriQdTxFcWDlI24x9pFG67/wCYBTIUCadmck7ZKv0zJnOuTysyDpPsLAKyo+0jYMvnFwnZH+LywDRZk0cjKChmBlporhSsAqDxHxKsaknY6VJrIFRyR0WLOMFdUXVIw05DIPSYs+sbkMZOkYCUApObKcbIy0xeBpBwoNCSFM4uIkslmfj/M1MnzZpHTYZOs3sY/yX0Do3LnbDW/rlgXH1/VxC5JlptRcU9RlOKo4yuKB1HHVxQPoo6vKB5k9op7ljVB0PPVyfbIFm8oQ+0mT8Q9Ugct50rFMFhyz2Wgxi/bO7tE0RpzeVrvZOZUyAjBXmsO3XasXq6RCZ0pkkrKovQqzsix3SBXVH05KVSNNck02DyJimPReCzVFgBNXWZrDIwV2X8SbN0u19dQqCDXQUDafMNyPblKco+1SNozERsv2eU4hQualqsoyhRQx1cUD6KOrygeRB1fUTzI7BX3jMGVSo5JStHMz9IaAWSjRIAiKo4JStuFdFTYCiRvtCdP2j0DCFmlCSynx5qF7fGaI8L2hfl9wvZ/+9t/RY85+EfZetsipyjUL20p0oTEfFlGErLacQBQIL1Nomfk4KEBqbwGEvKcFUjzCgBIzSECZoHVrmNRevJ4PlLjLjjCBcwcaZZSiJYmImaqSEONgBzHSXDFOl0vxWD/yolt4vP5NPBWSdPRO76ieBF1fEXxIOr4iuJB1PEVxYNM2fEPHTqExx57DM3NzbAsC6+//vqE/xtj0NbWhubmZoTDYaxatQqnTp2arvkqijINTFnVTyaTuPfee/Hd734X3/zmN8X/X3rpJWzfvh27d+/G4sWL8eKLL+KRRx5BZ2cnolGpmBedWEM9/PZnIY2mRhaNzIf45xbN0x+RcZjGJxXZRJYU5SQH7C7wkNu0keMEfFKpHc7JfPO3kzJv/19Wyg/N//HWt+nYP8dDwnZxWCrzQ4NSgq+ZRzoNJWR1ycgRnifvk2UDECAtn8PdsraBWylDV+0R3qo69rG0JRtJjC15+JCPkCcCpINQ0aKapPMNyDVkkacM7OmKj43t8Gs6GyXHrJl4XRaypYeWT9nxH330UTz66KP0f8YY7NixA1u2bMHjjz8OAHjllVfQ0NCAPXv24KmnnprqcIqizADT+hu/q6sLvb29WL169bjNcRysXLkShw8fpvtkMhmMjIxMeCmKMrNMq+P39vYCABoaGibYGxoaxv83mfb2dsRisfFXS0vLdE5JURTCjKj61qT6eMYYYbvM5s2bEY/Hx1/d3d0zMSVFUa5gWkN2GxsvhYz29vaiqalp3N7X1ye+BVzGcRw4jhTK8hf6AOsz0cYaGpY7PyBz9AEgT2pRmgARYUJSdEvnSW44UWaK5dOzkN1cgYiDo7K7zpmEbH89NlcKXw9WyoKeALDpC38nbG8M3iNsDbeTrkQkpPk/vrNM2IKJ0kJUASDeKs9lvFWukeXTs7x7APDl5D9cchVnYvKcG3KbY7n3RfPx66TgWDNHhm6PXpRrzLKQ3SAJky7ikTlyTU8+b4UMv7kypvWO39raisbGRhw8eHDcls1m0dHRgRUrVkznUIqiXAdTvuOPjo7igw8+GP+7q6sLx44dQ21tLebPn4+NGzdi69atWLRoERYtWoStW7ciEongySefnNaJK4py7UzZ8d955x189atfHf9706ZNAIC1a9di9+7dePbZZ5FKpbB+/XoMDQ1h2bJlOHDgwJSe4SuKMrNM2fFXrVoFY4r/zrMsC21tbWhra7ueeSmKMoPM3nz8SdgtMn+d5YADQKaWtGyuksJMICDFvaYKKXx9OSilkP4Cjzdg0Xc9/bLVS9AhXVQy8u04mL1D2D6q4aLmI7Wnhe0r1e/RbScTtWXo3R7/g8KWiRVpIU3Ep8wckltOdg/E5fn1k044AJBuYNUxpSk4TPYnpky9nKM9xqUvi0Tp+WxpK5A6D6zIKIsw9WXo0HClxovgpEvQ4sGOFE3SURQPoo6vKB5EHV9RPIg6vqJ4kLIR90yIRPcVK/zYIIUqm3SzqQxLJWWOI7vHjBmpmtT7eO7mu6Ok4OUFOfdCs1Sk3LRUewY+kRF+fpLmCwDRuSlhu5CrFraGwLCwBUi/5wW3yKqcw+/cQsdmt5B8WhpdFkFZejYpFf0KRPiyS2xfjYvynLPW1wDg75FqcrxOvrcOmeNkIQ7gXXx8af7EjIl+/klvd4Gk+RZD7/iK4kHU8RXFg6jjK4oHUcdXFA8ya8U9KxCEdWVaLgkTLha5FwzLPM98Xoo4WWKrmqyYAPhtUkYNzvXzyL13zspCIm6IpJJelJP3ZYgY5kjlK5HiCz+ble2zjyXmCdtg5i5hWxi9KGwsRdkZ4kpc3QmpPhlSgyEwKMVT4yMptIHS70m9/0LmgYT65TkPJsnciR7mH+PiaTYmz0dwRK4xelZef9moXA+rSVis9budI12J3rsw4e+8WyTsjx2v5C0VRblpUMdXFA+ijq8oHkQdX1E8yKwV90wuC3NFaBMTipiAAwC5d2UTCWuhFO3yBfm515mQtQEdEgb2LtkOADL9suFEw2E593C/PKZlpLLDasfFvyDTfAHgP4yuEjaTJ00k4vJtfzd/q7AFSASaPZ8ODYc0LGH4xuR26QZ5zjKkJTUARLulgFXznhTT3ABrS03ExlEpmvmTRUL3yDVorNJq+4UG5DF5DUC+bps0yyj0TmyhXjCltWgH9I6vKJ5EHV9RPIg6vqJ4EHV8RfEg6viK4kFmraov6JKttfxfrKabOkPy8yzRL/Omx8JSYf7QJWGzJJf/YlI+OQBA2yYbm6jjebmdPyETxgtBqXg3/YN8QgEAF/Jy22yMtYGWNtbNhrW+9vGhMXAX6UBExPHKClmV05eR84n0coXa9ZPCnCTE1vWRc06Kpgbj8py7DuuzzlX4giPHyZMnKazmgOWWnj/PbtF2eGLotm1soERhX+/4iuJB1PEVxYOo4yuKB1HHVxQPUjbint0wV9hyEV5sc+ROqXDYYak0Nc+NC9v86JCwPVjdJWy3BmUhSgDYaj0qbBcfkHny8bisEOkfI4Ubh6QAVPUxz4ln7Z2zc+S21S3DwjaSkMVDq/6znI8/zceOL5CX0sid8pwnFsl95/yTFNPYugFg6HY5p0wNCYm+IPcPjElbtkoKov5Ukeqf5HIbvYWEBofl/bT2tNzOR4pjFhX8ZBkDWBUT3zPL9QO8TIRA7/iK4kHU8RXFg6jjK4oHUcdXFA9SNuJeoUZGfBWKdNKpqJNKSCYtla/6SELYmkJS8IuQFix3BS8IGwAsrJaiX3KeFPJSMVkwM1OQ60lm5Wdzai5pHQMgNU+KaRX1SWGLhWVIXn3lqLCdWbRA2IKkpTUA5EljoSDpUpOdK6PsBu4nkXcBKeIBQJa06U7fI9/vVJ88v5GzLOqPDGKVvkYm+OWiRESsIJGEJOovNZdf05XniWB4ZtI5mkJHIr3jK4oHUcdXFA+ijq8oHkQdX1E8SNmIe/aYFNgCySJRTqSNdBpS3AuS7WoCUu1habkB1oIFQLogT6nfR1QXm+zvkgi08/J4FeeLjF1PxKKkFAKjc2TByrmOFPc+iMl5B0aLFIMk6aB2Xs7HIjZUSlEyF+WXZq6KpD0TUdT4yXbkkCx6zi3iFSy9Ol9B9g/J88a6BVmkbTeb46U5kTWOTcyRNi7rA87RO76ieBB1fEXxIOr4iuJBpuT47e3tWLp0KaLRKOrr67FmzRp0dnZO2MYYg7a2NjQ3NyMcDmPVqlU4derUtE5aUZTrY0riXkdHB55++mksXboU+XweW7ZswerVq3H69GlUfFpL7aWXXsL27duxe/duLF68GC+++CIeeeQRdHZ2IhqV7YxLxThSnIv08Y4nF0n7a5fUQasNSiGvxi8j3QKkd/FHed7NJp6VaZ7pjJy7Pyjn7o+QVsgX5b5EawQARLvkutNxGcFWdRsppkcoVMs52h/xqEGQQLuADIyExd6boLSxen2XjklErnNyjX6ynTNIWq2T6Dk/Sd8FgOgZ+f4km1kdP+lW4UF5DYV7pcha9TF/c/1Dsthh4cK1d9KZkuP/7ne/m/D3rl27UF9fjyNHjuDhhx+GMQY7duzAli1b8PjjjwMAXnnlFTQ0NGDPnj146qmnpjKcoigzxHX9xo/HL8W119bWAgC6urrQ29uL1atXj2/jOA5WrlyJw4cP02NkMhmMjIxMeCmKMrNcs+MbY7Bp0yY89NBDWLJkCQCgt7cXANDQMLGhZENDw/j/JtPe3o5YLDb+amlpudYpKYpSItfs+Bs2bMDx48fxq1/9SvzPmtRV1BgjbJfZvHkz4vH4+Ku7W9bPVxRlermmyL1nnnkG+/fvx6FDhzBv3rxxe2NjI4BLd/6mpqZxe19fn/gWcBnHceA4PAXzSqysVHsi7w/QbXO5Is0uJrE4Ir+F/HH4NmFjbbJ/nfkSPWbX+TphswalIOZGpNiTD5IIvzr5gVnzHs+/rH2XCEAhKZz9sfIOOUdyyPpjJJJwgAtI2So5TjAh10gDHsk9gUWqAUAwLt+LfFiOXQjJe9rYXGkLDZLoxCI19+ycnHyQtNk2pB9HcFjOmzXuKJCmHwDgl6Ugr4sp3fGNMdiwYQP27duHN998E62trRP+39raisbGRhw8eHDcls1m0dHRgRUrVkzPjBVFuW6mdMd/+umnsWfPHvz6179GNBod/90ei8UQDodhWRY2btyIrVu3YtGiRVi0aBG2bt2KSCSCJ598ckYWoCjK1JmS4+/cuRMAsGrVqgn2Xbt24Tvf+Q4A4Nlnn0UqlcL69esxNDSEZcuW4cCBA9f1DF9RlOllSo5vzNWb/FmWhba2NrS1tV3rnBRFmWE0Vl9RPEjZ5OPjopQ1TbNU0AHAJa2uDQnZHSvIpwlnR6uFLeSXSrYpEjdrxuQpDSRJmGlKbkcig2m+d9V7PMjJkNbQ/vfOCducloVkZ2mqeVfm6OcrSLseAP4UK5hJ2kWT9uC+NInPLfL4lxEelKHXuVpZGdM/JueTqS7dBZiqn6uQx3SG5PVC10i65tgOn4/lTqGSZgnoHV9RPIg6vqJ4EHV8RfEg6viK4kHKR9yrlfnvY/N5bIBtyTxnKyTFldOjTcIWT8nc7oQtQ24zOS5yhXrlKXV9JA88TFokE4GtEJaiTrZW5vwDgNMrE+Bzt98itxuRx0xXk449DXIcX5aLTNmoDD8NjErBz5eT+9tZuV22Vr4PABAYlu+tPUDEzjlS3GNhxeF+KcSxcF8AGJtbmruEe+V6cpXyeimQUONiocpMKHXOT/QJY7LAcElT1Du+ongRdXxF8SDq+IriQdTxFcWDlI24Z43JApFWgecOuGelsOMj9SX/hFvlMT+WgpYhH4+hAS7CzOmSwo4/KQWtVJ089WmSe58Py8EDCZl3DwAmSKIG+6Tgl6mTYiVbIzu/xcQnFsHGIgnHGqTIVUnaV7N1A4BvTApiuQVzhc3OyPfBLpRWuDQQ5zUHchVk7Ig8QCFcmluxvH0WHQgAPrIeTO7O45IDFkHv+IriQdTxFcWDqOMrigdRx1cUD1I24l6++6ywhYfjdNu6mruFjbVDTgxJEbDhiBTOslVSFHIGZAQZAAQ+uShsJiKj0IJxGXUY6ZPjBEak0GR/zEuVo65a2kh6KxOQqj+Q6/EnpM0N8YjFIBHEMrVSRMwSgcw5J99Hu5FHZRYi5JIl6a3BuGwZHRqQNjslIzpZBCUARM5LhThbTQqpBkh7cCKUssKhpkg6si8p5+7GJ0YsulPopKN3fEXxIOr4iuJB1PEVxYOo4yuKBykbcY/hJkgfZgC1Bz4UtvximZ7qy0phxv7DcWGrbGmWg2Sk2HJpTrJOnamvETb/6Y+FzSoiVortWhdQu7k4KI0Nsi5hqI+EMZIKyoUwiXQj6aEAECQpwf4hWQvPn5SinZWVolSgT55HAKDSYp7U+6uukPtelC3QjZ9EDcZ42jNLjQ0m5Nz9cSmK5qqlwGvlZUSnRaIdi2EmiZqlVMG+jN7xFcWDqOMrigdRx1cUD6KOrygepKzFvWIULsroOYvYKkg/P9eVQpEZkqKbVcUjy6zJqZIA7IvDcsOwFJD8FVKQcofkvmaEi5omJUU7e5BExeVlG/Fsc5WwBS5Kcc4qIiC5FbI5iRuU58IiUXZulYygtFJcPC0V34A8R24lEdhyJN11CrfDAhH8crfI99G5KN+bfFSKy4FhIryCn0tMvlYNWUsR9I6vKB5EHV9RPIg6vqJ4EHV8RfEg6viK4kFuSlWfYTlSdbZCpFsLCQMujJBOLcwGwN/UKGymgoSA9svwWndEhqnaYTnHwgAJzQVgk6cUuVsb5DgOUdtJhxsrR3LVSdFTAEBQdjpiHXKYjSnrVpGQ6EJ9tbAxBZ+FVFtx8p7NIeHUQ7yYaaFSXkPGR0J+Sc0BqyDPL+vYY0XlGAAQIHO6nsbZesdXFA+ijq8oHkQdX1E8iDq+ongQz4h7dpUMSWWhvaXiq5tT+sYkbJZhckTQIsIgE/EAwI7JNdoX5Ni5pmph8w+SXHVHXh75Wr5u/0UpnJkIEcNItx+QfPxccy0dJxeTYa5BksNOc92zUqwssFDjEO9I4x+RefYmILcNXSSdk5pIODYpyulLc8mO1Q24HvSOrygeRB1fUTyIOr6ieJBZ9xv/ct2wPHJA6SXErn5cV/5+LkyhAUEpxwN42qkhqb4ipbLIfIyR4xjDfwfaLmny4cpt83kShFMgv19t+fu1kC/yprD9ybJNQf7Otsm+dI4A8iTQyM7L/VnAjFUg55ysx80X6TpbIO+FRboE26TrMWli4oI0O8nL8wMAFju/k66XPHKf2q/uOJaZSoW+vwJnz55FS0vLjZ6GopQt3d3dmDdv3uduM+sc33VdnD9/HtFoFIlEAi0tLeju7kYVUeXLjZGRkZtmPTfTWoCbYz3GGCQSCTQ3N8O2P/9X/Kz7qm/b9vinlfVpH7GqqqqyfTMYN9N6bqa1AOW/nlhM5kwwVNxTFA+ijq8oHmRWO77jOHjhhRfgkJTacuRmWs/NtBbg5lvP1Zh14p6iKDPPrL7jK4oyM6jjK4oHUcdXFA+ijq8oHkQdX1E8yKx1/Jdffhmtra0IhUK4//778Yc//OFGT6kkDh06hMceewzNzc2wLAuvv/76hP8bY9DW1obm5maEw2GsWrUKp06dujGTLYH29nYsXboU0WgU9fX1WLNmDTo7OydsUy5r2rlzJ+65557x6Lzly5fjt7/97fj/y2Ud04KZhbz66qsmEAiYn//85+b06dPmBz/4gamoqDCffPLJjZ7aVXnjjTfMli1bzN69ew0A89prr034/7Zt20w0GjV79+41J06cME888YRpamoyIyMjN2bCV+HrX/+62bVrlzl58qQ5duyY+cY3vmHmz59vRkdHx7cplzXt37/f/OY3vzGdnZ2ms7PTPP/88yYQCJiTJ08aY8pnHdPBrHT8Bx980Kxbt26C7Y477jDPPffcDZrRtTHZ8V3XNY2NjWbbtm3jtnQ6bWKxmPnpT396A2Y4dfr6+gwA09HRYYwp/zXV1NSYX/ziF2W/jqky677qZ7NZHDlyBKtXr55gX716NQ4fPnyDZjU9dHV1obe3d8LaHMfBypUry2Zt8filGn61tZdq4pXrmgqFAl599VUkk0ksX768bNdxrcw6x+/v70ehUEBDw8QOMA0NDejt7b1Bs5oeLs+/XNdmjMGmTZvw0EMPYcmSJQDKb00nTpxAZWUlHMfBunXr8Nprr+Guu+4qu3VcL7MuLfcyl1NyL2OMEbZypVzXtmHDBhw/fhxvv/22+F+5rOn222/HsWPHMDw8jL1792Lt2rXo6OgY/3+5rON6mXV3/Lq6Ovh8PvEp29fXJz6Ny43Gxkt99cpxbc888wz279+Pt956a0J1l3JbUzAYxMKFC/HAAw+gvb0d9957L3784x+X3Tqul1nn+MFgEPfffz8OHjw4wX7w4EGsWLHiBs1qemhtbUVjY+OEtWWzWXR0dMzatRljsGHDBuzbtw9vvvkmWltbJ/y/HNd0JcYYZDKZsl/HlLmBwmJRLj/O++Uvf2lOnz5tNm7caCoqKszHH398o6d2VRKJhDl69Kg5evSoAWC2b99ujh49Ov4octu2bSYWi5l9+/aZEydOmG9961uz+pHR97//fROLxczvf/9709PTM/4aGxsb36Zc1rR582Zz6NAh09XVZY4fP26ef/55Y9u2OXDggDGmfNYxHcxKxzfGmJ/85CdmwYIFJhgMmvvuu2/88dFs56233jK4VB94wmvt2rXGmEuPv1544QXT2NhoHMcxDz/8sDlx4sSNnfTnwNYCwOzatWt8m3JZ0/e+973xa2ru3Lnma1/72rjTG1M+65gONB9fUTzIrPuNryjKzKOOrygeRB1fUTyIOr6ieBB1fEXxIOr4iuJB1PEVxYOo4yuKB1HHVxQPoo6vKB5EHV9RPIg6vqJ4EHV8RfEg6viK4kHU8RXFg6jjK4oHUcdXFA+ijq8oHmTG6uq//PLL+NGPfoSenh7cfffd2LFjB77yla9cdT/XdXH+/HlEo9Gbsp65oswUxhgkEgk0NzfDtq9yT5+JQn7X0/Syu7u7aIFHfelLX1d/dXd3X9XPZqTY5rJly3Dfffdh586d47Y777wTa9asQXt7++fuG4/HUV1djYfwr+FH4HO3/aTtQWr3L0wIW/Q/Vwpb4N/1Cdv/6bb/Imzr3vyOsN11+1k69lhOzvlMb62wzW8cFLZPeuYIW6x6TNhqI9IGAEFfQdh+OH+/sNX7XGHzQX672p+8Vdh+e/GLdOx0Xn55/LhPricfDwpbyxcuClvO5XeswZEKYZsbGxW2i3H5fuM9aWv96XvCVhgcomPPdvLI4W28geHhYcRisc/ddtq/6l9uevncc89NsBdrepnJZJDJZMb/TiQSn04sAL/1+Y5vh0LU7otkpS0ot/VXOMJWEZUXnB2W+wYq5AUMAP6ctNuR0sZm4/gi0pn9FdIGAAFfXtgqyXqiPrkvc/ywJS+PwBhfdz4v3yu2bjsr92fnwhRxfDvPzmVObpeT21nkevHbcj7WVa67Wcunt/BSfiJPu7g31aaX7e3tiMVi46+WlpbpnpKiKJOYMVW/1OaDmzdvRjweH391d3fP1JQURfmUaf+qP9Wml47jwHHkV71S8KX4V5qKkPyqH79Nfsbl/9wobFWLM8L2b5f9o7D9l/8v76c2dqv82tl8UI49//8gf0d+4pe/iX22lGC6jt5Cxy5Uy6/6/807/17YoouGhc1Pfvf398jfiVaa3yusvHwvDNk0NCSN5xJNwpavlWsBAOe8/Bo+lJS/3f3kyrblW4PCgNRavMC03/Fv5qaXinKzMCPP8Tdt2oRvf/vbeOCBB7B8+XL87Gc/w5kzZ7Bu3bqZGE5RlCkyI47/xBNPYGBgAD/84Q/R09ODJUuW4I033sCCBQtmYjhFUabIjEXurV+/HuvXr5+pwyuKch3MmOP/NbD442wkxsjzcKnZIb1Aqj3HM1I4++dB+YhxbB4Xn+wx+ZB8bK6UUg5/0ipszqmwsFnn5Vqq5GYAgHStfCadrZWi3XBvVO5ckOJc7TG5FjfIBVUrL0VIY8ttfTm5nROXtkKABBsAiJ5NSWOhtBi04Cf9wsbfxZsfTdJRFA+ijq8oHkQdX1E8iDq+oniQshH3LBLd5yc6DwAku2UGV22fFIDSdXL5//Hc3wjbh+fmClv4HD912RopprGP11y/VOj8RKMaaZUCWeYWGZkIAJEaeUJMiiTVJEgSCpljQuqP8Cfp0MgRvdCXlrZAQq4nVyFt+SIC5vBi+Q8WkReQCZoILpIibd1/kpF77hjPfryZ0Du+ongQdXxF8SDq+IriQdTxFcWDqOMrigcpG1XfZGTMbXI+UdABfOGL54TtbFwqugVSwur/sfA/CdvL1SuF7c9NPCd+eV2XsL3698uF7X/4yu+F7f95Um53W4MMM32/W9Y1AIAvN8l1NzgjwnaLMyxstX5Zt+5Ecp6wnRxupmMPpiLClhiTT2KSrHRXXD5lsIpE4VokxtY/Jp8KpOWDGBTCpGbA7eTRxdFTfHCC7/aFwpa4S9ZVqHw/LmzW2R5hKwzL7WYCveMrigdRx1cUD6KOrygeRB1fUTzIrBX37EgYtvWZEOSmpbjnhri4N0pqt0c/kWrRFx/5UNi681XCtv/w/cL2v//b/0rH7svK/ecvviBs5zPVwlYYk29H36gsJGlIYUsA+PvO24StoUGKRazxxj2154Xtv619R9jCPhIfC+DjMSlonQ1WC1syIt+bylvke3shTmKAAaT6pIjIagQY0o8gn5Dn140QYZGOzDHd8rxVhkmt/nPyGvhrCXkMveMrigdRx1cUD6KOrygeRB1fUTzIrBX33LEU3CvCtFg+vkUKRAJA7/kaYWtOSiHwRI+MQvv3/f9W2Pyj8vPxl+/x5iCZd2X3mXxECotnbBl9x3odZv5JdtqNFkkXL5AeomMn6oUtRYqU/l2t7Gbz26ovC5sb5oKqj5wjN0jC78itJj5HJu7n+3lD1EgPKwAqt6tdLDvwLojK7kV/7rtT2Ob9PR2aQnP3j50u/QA3CL3jK4oHUcdXFA+ijq8oHkQdX1E8yKwV9ybD0nLnHeS5m/mQXJYvJ0Up3xEZHZYlQlwoTgpEHqumYzukAGjFWbl/cl5p3V8c0sU5mOD7srbU6Tly7AIpZMnSYJ1+ecBsNRdUbSIY2lm5rZ+1Nu+RxVGtMF9jqkG+jybABcfJjOWlCuheW4f2z8X+0l1ynFkm+OkdX1E8iDq+ongQdXxF8SDq+IriQcpG3GNUnpTRWQCQvIN0vumVEVa+lIwOS5HuOpGLMhU1NYefugJJEXVGpPgUPUvEK6J7hfqkqDnWzKPachH5OZ6TWcK0bh3reuOSJTqDRZJWidmQTtdBkomak9oeUET7NA7rVCQ37umV0ZuFenl+fEW6MV0Ps03IY+gdX1E8iDq+ongQdXxF8SDq+IriQcpH3LOlUjS2uI5umqqT2+YqZe06JsT5MlIoit8q67IFR7n6FB6QIWysJlyoX7a6NrbcziYRh5FzRIkDMDpfhuRVfSS3YxF+TEwrkKi2gsPFvYwsuYeA7OUBOycHYpGEdq6IiEiEPDss1cpQRJ7ffzPvpLD9csHDfJybHL3jK4oHUcdXFA+ijq8oHkQdX1E8yJQd/9ChQ3jsscfQ3NwMy7Lw+uuvT/i/MQZtbW1obm5GOBzGqlWrcOpU6d1HFUWZeaas6ieTSdx777347ne/i29+85vi/y+99BK2b9+O3bt3Y/HixXjxxRfxyCOPoLOzE9Eo745SEq5Uy88/xKcfvIPIyf8oi2AGlstk928skB9S//HIMmGLniIVHsEV82STNA4vlB1h6o7L0OBCWD6hCIxIxRoAnLg8R4kWeY4KAamYu/LBBWzSNMcZLvY0Q9qzlXKcPGlVXdkt97XyfJxQP5moxWzyUcH/5/DfCtud/6/3hY2UFrjpmLLjP/roo3j00Ufp/4wx2LFjB7Zs2YLHH38cAPDKK6+goaEBe/bswVNPPXV9s1UUZVqY1t/4XV1d6O3txerVq8dtjuNg5cqVOHz4MN0nk8lgZGRkwktRlJllWh2/t7cXANDQMLFmfENDw/j/JtPe3o5YLDb+amlpmc4pKYpCmBFV35rUGcIYI2yX2bx5M+Lx+Piru7t7JqakKMoVTGvIbmNjI4BLd/6mps86s/T19YlvAZdxHAcO6ZJTCrk5JLEcQC4u89Xnn5Lb/u++83fC5mNVJ3Py8zF5H0/kNselqJRcIOWi8Fkp2vWskG9H3XEZspuplsIgAIw2k3nOk/sHb00IW/ZjGdLsT5ZebJOFJWfq5LoNCblltx+7krfjdjPyvNkjpP01ydv3pchAOS6U3uxM6x2/tbUVjY2NOHjw4Lgtm82io6MDK1bwllOKovz1mfIdf3R0FB988MH4311dXTh27Bhqa2sxf/58bNy4EVu3bsWiRYuwaNEibN26FZFIBE8++eS0TlxRlGtnyo7/zjvv4Ktf/er435s2bQIArF27Frt378azzz6LVCqF9evXY2hoCMuWLcOBAweu7xm+oijTypQdf9WqVTCmeDMIy7LQ1taGtra265mXoigzSPnk4zN8RT6AslK6YHngY6SNSsKVwuBX7n1X2J6Y+4906B/Y/07Y7mjqE7YP5shaAnNiSWFLXiCiaJFU9UytXKOPdK7JfiKFPNbSOjtX5v1HorL4JwD86wV/EbaagCxwOj/YL2yDBTmfuX4pQAJAkrxnB/pl55qQT4q5/WlZ1bP7f7pb2Jpf4jEnNxOapKMoHkQdX1E8iDq+ongQdXxF8SCzV9yzrEuvT/E31Mtt8vxzKzAko7vOkZqKTNz7xal/IWz/ly/9Z2EbyEtBCgCiFVIQOxeXKcFfuVVWwXx3WK4xfqeMfgtdIC1qAGRjRNwjAl1hRKYUV9RLYTHiyKi2gUG+7t+fXyhs3/nCn4TtHuecsJ0ryPOTM/zSvMU/JGwnw7cIm0vyo0dz8v3O8yDImx694yuKB1HHVxQPoo6vKB5EHV9RPMjsFfeMwZXtXfK9F8QmVuFWuqtFiqblK6TwlSjIKL3cBdLWhXAqNY/aK4ggNpQkqboFKbD19kuRyyappIUQj1i0SZZyfky+xcEaKfj5bJnGGvDJE+kL8Ip0dREZpcfOb4wU8usryGMWi9wLQs4zkZfjnBklbbJdEtHJAxFvevSOrygeRB1fUTyIOr6ieBB1fEXxILNX3JuEFZBimFWklbI/SRo5VJKoNksKReyjsDkgo8V6g1KIA4CxrGzukE7JuZ+80CRsZkBGllmkRh1rpw0AvjRps52R8/F/KOeTaJTnIt0oBbsiNVORJ5Fy7wzPF7YVFbKBxReD8vxeKJAmGQAcotzWO1IIrAuOCltXUvbyvkhHufnRO76ieBB1fEXxIOr4iuJB1PEVxYOo4yuKBykbVd+urRY2U0RhzlWRtsvkCUCBKNGGdGCptmWIa7GQ0vhHMlQ0OCzHGauRCj7bLjtHqth2kacZLCzZDcn1RHpI62wydsaRobBWmHcvGk7JbaMBGQ87QoqZNvnlHLsLvJPOh9m5wuYjYbzJggyTHiDFNoOkR6uvTqr/AGBS8jrIf3mRsOWi8olEcESux8qR93asSAehk7Lg6/Wgd3xF8SDq+IriQdTxFcWDqOMrigcpG3HPCkjBxGmWBSIBoLVuQNjePS7DRxc4sqvLv33gn4QtbWRxy4oiidymRubju0kp5LGw4oCMMoWdk2MXwjwfnx0z9Il8iwNJ0jWHtL8ODJKxQ/xeMTRcK2y5BXL/kzUtwvYl54iwDRekSAoAOfJevJuQ3YbOj8qQ6sERWVmzKiPPRaFfXj8AF/3iC6WImCclHXIV8vp1ZeQ0Krv5e1tr3yH3P37tgp/e8RXFg6jjK4oHUcdXFA+ijq8oHqRsxD23Nips6YQUzQBgJCqjw2zSUeZEUhbM/EJYZmj/h96vCVvYxyOs5syRCl3qL6SoZ5RE2fEUdEGkh0fu2VkSsehKmxOXkW75iBTNWN4/K+gJ8GhJWocg0Sxsvw9KMe1slkfPvZuUQt7Rd28VNnuMdBsiull9hyziijtlNB4ADN4v55SYL8/RvI6UHJoUMvCPSiHY109CCQHkPz5D7deK3vEVxYOo4yuKB1HHVxQPoo6vKB6kfMQ9FqVk3U+3DQek8FbxJxm19TvnTmH7H+8YFLa//4e7hO1/+pf/Kx37ni+cFbb/+0f/WthMRKZkFuIkXbZaqmnuWRLyBcCfKi0aMFMlP+99JILNKsjjZepIgVLw9Xx5nmyJ3RSKC9ue88uE7e5YDx1nOCvfR5ulCieluGdn5Xqy86qFrf+LUowFgJHb5Nqbbu8Vtg/nytThW96Ux3M+7BO2fLe8fmYCveMrigdRx1cUD6KOrygeZEqO397ejqVLlyIajaK+vh5r1qxBZ2fnhG2MMWhra0NzczPC4TBWrVqFU6dOTeukFUW5PqYk7nV0dODpp5/G0qVLkc/nsWXLFqxevRqnT59GRcWlemYvvfQStm/fjt27d2Px4sV48cUX8cgjj6CzsxPRqIy+ux7sABeaWIccQ1aaJV1m3onfKmwVrVKQ+nrlSTr2gCvFJxMkwpmfpIPWSJGKddIJ8axR+Em6rT8tbZmY/Ly3zLVHEgJAXYOMOLu7Sgp0Y6Q9+H013cK2OCxFMwA4l64WNh+p2efvl2uM9Mk1jiyQ0Z8ZOcSlcYh46pLCj3atjMgbvEPm6oYGpQho/5XEvSk5/u9+97sJf+/atQv19fU4cuQIHn74YRhjsGPHDmzZsgWPP/44AOCVV15BQ0MD9uzZg6eeemr6Zq4oyjVzXb/x4/FLd8La2ktFGLq6utDb24vVq1ePb+M4DlauXInDhw/TY2QyGYyMjEx4KYoys1yz4xtjsGnTJjz00ENYsmQJAKC399LXs4aGiYkUDQ0N4/+bTHt7O2Kx2PirpUVWaFEUZXq5ZsffsGEDjh8/jl/96lfif9akTCRjjLBdZvPmzYjH4+Ov7m75e09RlOnlmiL3nnnmGezfvx+HDh3CvHmfpbY2NjYCuHTnb2r6rA10X1+f+BZwGcdx4Dg8vfZq+Hxc3BvNyuMxoSoSkXXzhrNShEmNyeOdysr0UgD4r4N3U/tkrGEyISLkBRJEiOPLRiBFBMMgieYbk9vlKknDkRBp0U0adADAEKlnd3RYfnt7sOZjuv9kAqQdNgA0huRPwUJBnqOQzMJG7UnZ9ts/Ijes+yMfO90i6/idy9ULW8WgPJe3/E6mexf+IluG/7WY0h3fGIMNGzZg3759ePPNN9Ha2jrh/62trWhsbMTBgwfHbdlsFh0dHVixYsX0zFhRlOtmSnf8p59+Gnv27MGvf/1rRKPR8d/tsVgM4XAYlmVh48aN2Lp1KxYtWoRFixZh69atiEQiePLJJ2dkAYqiTJ0pOf7OnTsBAKtWrZpg37VrF77zne8AAJ599lmkUimsX78eQ0NDWLZsGQ4cODDtz/AVRbl2puT4hgR5TMayLLS1taGtre1a56QoygyjsfqK4kHKJh/frpAtjl2Xf25dGKwSNqtaflv5VutxYRvNSwW/6TapJFf7eBeff+xeIGyRuXLb3Ptyjrk6GbJrxuQa8zxdHIkWuW2ATDNXKW0uuRLo04MiTxTcvBx7XmRY2LrTskNOT0qq5fEoaUcD4IOEDHMNfiC3nXtUPrGx/vhnYeP6PSeclk8porfKgq3Rs7IexI1U8Bl6x1cUD6KOrygeRB1fUTyIOr6ieJCyEffcpFSpCmnSLQWA5ZNC3pz35Hajj0gh78NRKR4d//gWYetuqeZjn5bxCgUSiks/cUlud81puiEdu6JXikr+UdLxh+RNpBrkuUjMk+c3afFLxhqS9j+cvE/YWHfxAtHx3ou0SiN4Tnz9SSmK+t+Urbevl/wnMo+k4bdSHszdKsN4/fPkNZQ/K4uR/rXQO76ieBB1fEXxIOr4iuJB1PEVxYOUjbhHIZ1eAMDkSvs860nLiLGLKRkhWHVEhsqdeU9G6AGAIU1uKkmHY5b/buwS344iKRO+DIlDI0Jeuk5OkuXtE60Rkd4iLbpJMxs7R+oLkIKg+TA5Zj8dBv40Kaw5Vlr8nb3kDmFzT5IOTTYXjXN/+yVhe+8Jea3VkMKj8bgU/MKn5DU0/9cybx+Y/sg/veMrigdRx1cUD6KOrygeRB1fUTxI2Yh7vsW3CVuki7d6sUmwWsGRotIf3/uC3JcUwXRI8SDD9R8YEqVXcKR4FRyR21Wek8JVupak5Ua4wObLkSKjReY5mWyUtMSuldtZRYTFbJWcO2uzHemV68nKDGVa6BMA7Jw85vAiuW6zarncl8ynpepeYbv4JSnwAkCiVc7pb794QtgWV1wQthy5YP7XxtuFrW+AF3Gtq5QCs/knOXap6B1fUTyIOr6ieBB1fEXxIOr4iuJBykbcK7z3obC1/J3s3gIAmVop9viTMrQsNFSkeN0kAmTf/iX81AXjJLX2fdk2OROTYk+mSn4O23JXxC6QMDkAdoZExVWwmn1cHJxM62vDwnb2kWq6bbqRiHt5JhjK+eQqSdoyXyJyYdLdx5Fj2xFSvzAuIxaH7pDXUOOhQTq28Um18+NRaatzRoUtT+pDZgsk7bm5SDSqJQsl1v0T3bQk9I6vKB5EHV9RPIg6vqJ4EHV8RfEgZSPuMXw9XITxR2QKZGBQtkiOBJjwJQWXQlhuV/Vxkc4SBCsvBSl/Wtp8WZle6iOCnZXnYxsfqaVHxLRMrdwu3CfHGfiSTFsukLTjS4NLky8px2YReSwa0BS5JVk1Uu1kcph9Tgq3NSQDt+6/yGKMhf4BOnZ1y1JhGxqTBQPfyiwStkhAhpP2fCDrO1Zf4BGLtX8hfb+vA73jK4oHUcdXFA+ijq8oHkQdX1E8iDq+oniQslb13TkkkRuAIQUmjV9+xrlE1WdUfiiLJ45+gY89NlceM1UnQ4idOMnbJ+UFDHmHomd5POvwF+QB6NODlNw32US0cXJ68hGuOluu3N9ZJM+bS7ZLxaUC7wsXCUu25RMN1i49SMZO3EaecFTLnPjGHYfp2IFROaehAdJznEEqlwZGybxH+fkNDJBOUqWNTNE7vqJ4EHV8RfEg6viK4kHU8RXFg5S1uFdMYOu/R4bd2lkpIEV6pZCSrZYizLlV1SXPieXPs5hU2kmHvBthEsKZruEVNENDRPgiYbw+0kY8OU8ez0fWYmeL5PJHZUgqE+IWzpFh1ifSssCkOyQFUQCouEWKdumMFDVtUvQ0l5X3ueoPiiT+E+yclNMsW54Pf1BuV8gzcVm+4VYRxc51eGHZa0Xv+IriQdTxFcWDqOMrigeZdb/xjbn02yyPXNGusJfJ53iqYiEtfwMb1mQjS4JoMvI3m0uCYIpCf+OTsck4hvy+Y3O0ia0Y7Dc+KfUGl5xKi62F1NEDADclD1DwZ4QtF5QHdcfkvibFU48LY/KYLukSXMhLm5uWtjzp6JtnFwsA5OU83ZR0IZeNTX7jW+S6KhQbuiDXbSbNM4/cp/arXx+WKWWrvyJnz55FS0vLjZ6GopQt3d3dmDePqLVXMOsc33VdnD9/HtFoFIlEAi0tLeju7kZVFVfwy4mRkZGbZj0301qAm2M9xhgkEgk0NzfDtj//V/ys+6pv2/b4p5X1acx9VVVV2b4ZjJtpPTfTWoDyX08sJqsmMVTcUxQPoo6vKB5kVju+4zh44YUX4Dg8iqvcuJnWczOtBbj51nM1Zp24pyjKzDOr7/iKoswM6viK4kHU8RXFg6jjK4oHUcdXFA8yax3/5ZdfRmtrK0KhEO6//3784Q9/uNFTKolDhw7hscceQ3NzMyzLwuuvvz7h/8YYtLW1obm5GeFwGKtWrcKpU6duzGRLoL29HUuXLkU0GkV9fT3WrFmDzs7OCduUy5p27tyJe+65Zzw6b/ny5fjtb387/v9yWce0YGYhr776qgkEAubnP/+5OX36tPnBD35gKioqzCeffHKjp3ZV3njjDbNlyxazd+9eA8C89tprE/6/bds2E41Gzd69e82JEyfME088YZqamszIyMiNmfBV+PrXv2527dplTp48aY4dO2a+8Y1vmPnz55vR0dHxbcplTfv37ze/+c1vTGdnp+ns7DTPP/+8CQQC5uTJk8aY8lnHdDArHf/BBx8069atm2C74447zHPPPXeDZnRtTHZ813VNY2Oj2bZt27gtnU6bWCxmfvrTn96AGU6dvr4+A8B0dHQYY8p/TTU1NeYXv/hF2a9jqsy6r/rZbBZHjhzB6tWrJ9hXr16Nw4d5o4NyoaurC729vRPW5jgOVq5cWTZri8fjAIDa2loA5bumQqGAV199FclkEsuXLy/bdVwrs87x+/v7USgU0NDQMMHe0NCA3t7eGzSr6eHy/Mt1bcYYbNq0CQ899BCWLFkCoPzWdOLECVRWVsJxHKxbtw6vvfYa7rrrrrJbx/Uy69JyL2NNaoNljBG2cqVc17ZhwwYcP34cb7/9tvhfuazp9ttvx7FjxzA8PIy9e/di7dq16OjoGP9/uazjepl1d/y6ujr4fD7xKdvX1yc+jcuNxsZGACjLtT3zzDPYv38/3nrrrQnVXcptTcFgEAsXLsQDDzyA9vZ23Hvvvfjxj39cduu4Xmad4weDQdx///04ePDgBPvBgwexYsWKGzSr6aG1tRWNjY0T1pbNZtHR0TFr12aMwYYNG7Bv3z68+eabaG1tnfD/clzTlRhjkMlkyn4dU+YGCotFufw475e//KU5ffq02bhxo6moqDAff/zxjZ7aVUkkEubo0aPm6NGjBoDZvn27OXr06PijyG3btplYLGb27dtnTpw4Yb71rW/N6kdG3//+900sFjO///3vTU9Pz/hrbGxsfJtyWdPmzZvNoUOHTFdXlzl+/Lh5/vnnjW3b5sCBA8aY8lnHdDArHd8YY37yk5+YBQsWmGAwaO67777xx0eznbfeesvgUn3gCa+1a9caYy49/nrhhRdMY2OjcRzHPPzww+bEiRM3dtKfA1sLALNr167xbcplTd/73vfGr6m5c+ear33ta+NOb0z5rGM60Hx8RfEgs+43vqIoM486vqJ4EHV8RfEg6viK4kHU8RXFg6jjK4oHUcdXFA+ijq8oHkQdX1E8iDq+ongQdXxF8SDq+IriQdTxFcWDqOMrigdRx1cUD6KOrygeRB1fUTyIOr6ieJAZq6v/8ssv40c/+hF6enpw9913Y8eOHfjKV75y1f1c18X58+cRjUZvynrmijJTGGOQSCTQ3NwM277KPX0mCvldT9PL7u7uogUe9aUvfV391d3dfVU/m5Fim8uWLcN9992HnTt3jtvuvPNOrFmzBu3t7Z+7bzweR3V1NRb/D/9n+IKhcbsvK6fpDPGp1/zDWWlky3SJLRQUpuy8GmGzsi4d23V8ctuCHGd4YUjYKi7khc2Qbz3pWjlGMSyyRJucS5BD5h05tlUofRyLnN9cBfkWx94aP/+2l4tKm50j21VImz9FxgnQYSgu+X5s/HLyVp6cN3K5uI7c187ydQdGpG3OXzIT/s7nM/iHt7dheHgYsViMHucy0/5V/3LTy+eee26CvVjTy0wmg0zmswUkEgkAgC8Ygs+5wvHJ1eEPcMf324400s838m6QfV2/dFLLLeL4fuL4xCuu/FC7jD9QmuP7gtfn+D5yLgw5pAlOv+O75JjM8a0iju+St5Z9q3Xl6YWPvGXWFBzfIt7ikmvQZo7PzluIXBdFft76yLr9Rc5RKT+Rp13cm2rTy/b2dsRisfFXS0vLdE9JUZRJzJiqX2rzwc2bNyMej4+/uru7Z2pKiqJ8yrR/1Z9q00vHceA48ntMPgKYK8yBhByL/e4HAJNOS1vzXGGzegakLSe/bgff6xG2XCtvpJipld8dg8PymNGz8oepG5Cfw25AfliGB/n37QL5Gs32t4nmkCfbhYbkd+Oxen6vYL/JfRm5Hfs9bsvTg1yEv7fs93O2qrRxcpXS5h8j21XxsX1j5Cu8T9qMT+5fIF/V3SD5yVXsVuwSrWfOxGstnyvyO4ww7Xf8m7nppaLcLMzIc/xNmzbh29/+Nh544AEsX74cP/vZz3DmzBmsW7duJoZTFGWKzIjjP/HEExgYGMAPf/hD9PT0YMmSJXjjjTewYMGCmRhOUZQpMmORe+vXr8f69etn6vCKolwHM+b414svMzGmhAZaFHtcWT9HmNyIDMyxhoaEzb79Nnk88szeN0bUIwC+tBzHl5bqlRuQC2KBPk5S7pur4G8be5Ye/SgpbOn6MN1/Mqk6KQGFBnn8Qi5SmlzE5shgwiDA4w1somnZWWlj4p4r3y4aqAMARMejIqJVICJrlDzvz7ED8rGZffL1wq6fYmiSjqJ4EHV8RfEg6viK4kHU8RXFg8xacS980cB3RWQTizbLVvLPLSstlR0ficiz5tbJncdk1J8bk6le2TlcIAsQMS5wpl/uf0+znA9bY0y+RcWENH9a7p9qlvPMheX+VDSjWW987GyURe6RzDWiPxVI1CAT3QAe2WZY1hybJtHSLBI1GBrgqnGevOV0PizrjozDYMIgwMXOyRl/LAOwGHrHVxQPoo6vKB5EHV9RPIg6vqJ4EHV8RfEgs1bVj70/Cr//Myk0OT8itimmYppBGYprVZAibGFZn8nYJOe6R6rypn4+H5yEimYWytz9QIKE4lbKtyOQkPGoTIkGAH9Kbsty/AMjUq5P1csQYpco/QVS0grgpaVYmS12zFJz54uNw/bPs3kyVZ9cQ1kSXgsAhoSNW6y+AAnFpTX3SD5+IczHZse08+Zz//489I6vKB5EHV9RPIg6vqJ4EHV8RfEgs1bcG2uOwB/4TKFhohurxw4A7m3zhM0+e1FumJS56la1bERQaKkXNh8R0gDADcrPUn+SFNb0k7BZUrAyTQS/YkVGE/NknCsLKfXlSmt0wcJEXZaUXmRObGz2NtJxSBgvwEN+WSgta57BYKHK/iKFHlyWe09EuwKpl88OyYROX6bIupk4OOl6cU3pLef0jq8oHkQdX1E8iDq+ongQdXxF8SCzVtwbWuyD74rOs5ELpGkmyT8HAF+/bC1q8iTczSfVFTMcFzY7wBK+eT6+S5phpuukzc5Jtaby2Hm572IZ9Zds4p0eWc0Ci0QSBlJybMslYiPRigJSDwVQetdZGuFXeg9QBEZJtFuIheRJU4Hk+Jda/BMo0iCzxCg9di4tWjOgSOQe6aKrkXuKokwJdXxF8SDq+IriQdTxFcWDzFpxzxmeVGyTaHPFosgKc2X0nR2U6lPhgy5h80WjcpyYTAkuhPip8ydIoc8x+fmaqZN9kxP3yQKcNomyCxVrkx2S47D9WbHOXJiIVEQrKtbGmUXAMSEvV0kiBIlIG0hyoSpTw/aX2zGxkXXcKZDtaOQd+PnwEfG0YJHW2awlNktRJq24AZ56LCJXpyBU6h1fUTyIOr6ieBB1fEXxIOr4iuJBZq24N7oAsK8IeJtzQioXleeIsgKgEJaKjZ2USor/Fimm5RbMlccLyX3HSI06AEjXyM/SNGnYw1JRK8/JkC+WLpuNcQGI1YqLXJDbRs+y1ttyjUxgKzilp35mquW2LIU2T4RF974EPaYhAla2V4qvJizPZbBXXu52nomFRVKPicDGogELrJMOq5lHFlOsRXeelIycXNPQJaJiMfSOrygeRB1fUTyIOr6ieBB1fEXxILNW3Av1WfBdISRliKBlLBn9BgCRPqnC5OfLaD5fRkbpZWqlaJeuJpF3JIIMAJK3SFHJzJEiZCQq1b0LfVLBYW2TfTVEGQRQXTUmbP3n5brdgFxj5VkZ1pZskoIfi8YDgJw8lchUS/EqX0tCMG253f920TE6zplUjbC9Y8vmJg0xKQ5+bGTtRLjk/FYVEY3jUslzLhLROEWuVVZ/kKTaTuVW7MtMvNYMSfUuht7xFcWDqOMrigdRx1cUD6KOrygeZMqOf+jQITz22GNobm6GZVl4/fXXJ/zfGIO2tjY0NzcjHA5j1apVOHXq1HTNV1GUaWDKqn4ymcS9996L7373u/jmN78p/v/SSy9h+/bt2L17NxYvXowXX3wRjzzyCDo7OxElue7FMP5Lr8sEBkrrTgIA/rSUnn1jUk32ke467hdlF57JHUuA4i26E7fJfzQ3DAtbOidPfbZaJpbnRqWS7BIlGgDGMlKtj9aPClumt1rYnEHWAYio8iSEuBihQbltMkyeFNTKpxRRlmQPYCwvz4dFEuX9NgnZvUjO+Vx5XSxsJF2XALyXk4VP86S2gV8+XKHFNsHCfYnt0jFJWPOkbkNuMYdgxyt5y0959NFH8eijj9L/GWOwY8cObNmyBY8//jgA4JVXXkFDQwP27NmDp556aqrDKYoyA0zrb/yuri709vZi9erV4zbHcbBy5UocPnyY7pPJZDAyMjLhpSjKzDKtjt/b2wsAaGiY+JWooaFh/H+TaW9vRywWG3+1tLRM55QURSHMiKpvTUoPNMYI22U2b96MeDw+/uru7p6JKSmKcgXTGrLb2NgI4NKdv6mpadze19cnvgVcxnEcOA4JvXU/fX0KK0zICiUCgJ2Sgk3BIaJSQ62w0Y4nrhSP0rX8M9M/Isfp+7Ncu8uKL9bKUNFABQk/HpCdeQAgFJNtbvIF0i2ITL1A3gJ2zlk+PQAEpIaIsQbS2Yd10snJgf4wsJCO0zUg37OxITmpT7Ly0vaTPHsm+HX6moQNAOy43NYlufdZYgsOkveBVMcsomkWDZW+Vqb1jt/a2orGxkYcPHhw3JbNZtHR0YEVK1ZM51CKolwHU77jj46O4oMPPhj/u6urC8eOHUNtbS3mz5+PjRs3YuvWrVi0aBEWLVqErVu3IhKJ4Mknn5zWiSuKcu1M2fHfeecdfPWrXx3/e9OmTQCAtWvXYvfu3Xj22WeRSqWwfv16DA0NYdmyZThw4MCUnuErijKzTNnxV61aBcMKn32KZVloa2tDW1vb9cxLUZQZZNbm47sBwLpCvBtcIj9sWpbwR4TvLZPVLQMRKZzFKqUIODAgI77mN/UL21PzjtCx73Bkq2vGW4m7hC1H1LSedJWwfemLZ+kx5wUHhG33uX8hbO8HqoUtvpgU1qwiEZAVJJ8ewBgpWokRqb6akDy/VbVSlKwM8JoD7OFQVZ3c3ybRfKkvyrGzCalq2g5X0lwSpUfb65AaCkzMZUU5jZ/fVP2jcuzB2ye6byFTujtrko6ieBB1fEXxIOr4iuJB1PEVxYPMWnHPPwb4rtBYTECKHnVhEi4GoOecjLxa9XVZE2AgI4tbkiA95F35+fh0NQ8tzhkpDAUsKdpVWMeErZaEbf2Hi6uE7dHKk3RsHxGa7o71CFtnM4+inExNTOaXhoOsXzPPkB6JSeHM8cvzc+ccKdI+VP2BsAHA+VFZPLQyKIXAVF4Ki05ACpMZR66nOpKiYw9Uyo49oyMyapClCecjct304ViGhEsCKIRJ9OikJbqk3Xgx9I6vKB5EHV9RPIg6vqJ4EHV8RfEgs1fcyxj4rlA/IrdIIa8/VUn3zd8qRbJkXgpN7w/IltiP3SqFs4tZOc5fsqSwGoCEkaLSkoAUdl6+8C+F7baIjBC8NSSj8f45w4uVfJCWot2xIVlD0BTk573zkTw/8VppGwoWKTZI7BaJQgvNlRWWHFuen/dTXICMp2RKcn9CirQ26c6TjJN05rQU0+Jh0pMagMnJ82ZlpY2KduS0sRbdxWo5so5Kof6JtkJG22QrivI5qOMrigdRx1cUD6KOrygeZNaKe7404LtC6MiflOmp3UWKezgD8vPs8OAdwsaElP94frmwBYalAHQwdg8d24RJSicRcfxD8tT/PUnT9JFGCiyKCwBMjYxCC5yVHRoqh+QxbRKQV/Wx3C4f4pFlgLSzRiSZoBRU/75S2lhdQACwSVawj3S1LhAdL8IENrKvG+BukasiNQTJMV1yinwlCm8sfRcAAiNy/8qzEwcvaJtsRVE+D3V8RfEg6viK4kHU8RXFg6jjK4oHmbWqfrLJgs/5TMkMk7qaMZ6yjTnvyNDXCw/NEbbAGOv0QsJZR6SUHL+Vt/FxA1LSTZGOMuFeUpDRIWGZF1mrav557UtJBZ8p3nZeqr+5SvL0gHTXyUW5Oh0cKa2NeaSPFLxMyQ2Lqfr5MCtkSYZmHXvIekgzG/rkoNgxmaofKHE9uSq5c4AU1QQAEtWMYGLi/nlV9RVF+TzU8RXFg6jjK4oHUcdXFA8ya8W9qjMufIHPxIrIBRKOOlSkpzCh/k/DwmaPyJz60btlHni4OyFsmVg1HceXJUJePwl9ZUITqR1a9YlU57LV/G2Lt0phMTTAwoClLXBRCkOZqDyeU+AhpUwQc+LymIl5JKedCWxElAQAZ0huzARHJkwymOhWPFyYqJUsZJeE3VosbJuEYxeDCYuTGy+Z0rU9veMrihdRx1cUD6KOrygeRB1fUTzIrBX38o4FE/xM/BhYItWawCgJ2QIw9+0+YbPTUi0qnJfhgJWkD3OuQXZvyUW4MOPLkAKTA1KZYYJWupZE/dXLCMFiBRkreuQ/TIn6kUXEOZsIebkKfsACeSuylSQKkohzmVp5zLTsdH5pTlm5bVBqrxQWxZgj9VoLRbzCJp27WdQg6XZO6x2YUt+cIth587l/f+6+1zWyoihliTq+ongQdXxF8SDq+IriQWatuDfWMDEt1xmWwkVwlIsZuXpZhHN0vqy+OHpLs7CxIo0BElFXcZ4rbOE+IiI68vM12SxVIRZtFhqU44zV889rP+nuzMRGJg4aciUw7Skb44JULirH8SfldgWSVksLVpIuPJ9uLSxMCPSTRkfs/Lqk/Xp2bpG8XLKtPSxPXHBYvj8FUki1ECotlRkAXB+LTpw4TsEu/T6ud3xF8SDq+IriQdTxFcWDTMnx29vbsXTpUkSjUdTX12PNmjXo7OycsI0xBm1tbWhubkY4HMaqVatw6tSpaZ20oijXx5TEvY6ODjz99NNYunQp8vk8tmzZgtWrV+P06dOoqLjUWvill17C9u3bsXv3bixevBgvvvgiHnnkEXR2diJapPNNKTABKHyR524GBqWyYxZI1S7AxEGiaIX6S4+IykXlKc1Uy1Cu0VtIl5laktLbRzrU8HJ/VLxiqaS+FBFKk6S2X4hEybHaeuAppnnSbZpFtflIRByLbLw0DrERUZNFEuZjpb2P/ngRt2CdeEhEHr2dkqF9aVI/sMh7a+dIHT/r8//+PKbk+L/73e8m/L1r1y7U19fjyJEjePjhh2GMwY4dO7BlyxY8/vjjAIBXXnkFDQ0N2LNnD5566qmpDKcoygxxXb/x4/E4AKC2thYA0NXVhd7eXqxevXp8G8dxsHLlShw+fJgeI5PJYGRkZMJLUZSZ5Zod3xiDTZs24aGHHsKSJUsAAL29l5JeGhomVrFpaGgY/99k2tvbEYvFxl8tLS3XOiVFUUrkmh1/w4YNOH78OH71q1+J/1mTMtyMMcJ2mc2bNyMej4+/uru7r3VKiqKUyDVF7j3zzDPYv38/Dh06hHnz5o3bGxsbAVy68zc1NY3b+/r6xLeAyziOA8eRqlRwBPBdIdCESDpnsomn5fpHpEISPSMVJP8Iqdln5DjpZilKFkjzCwDIh+Vn6eTGBwDgkFbVOaJ90oYNJJIQAPxEtGOiEhPy0tVMaJI2FkEJAFkyd2eQRPORU56tkuOwttAAaGRbRmZNwxmSthCpfcgE0WIiWT7CoiCvLroBgCGiHa3tVyTlmp03cS6mIO5N6Y5vjMGGDRuwb98+vPnmm2htbZ3w/9bWVjQ2NuLgwYPjtmw2i46ODqxYsWIqQymKMoNM6Y7/9NNPY8+ePfj1r3+NaDQ6/rs9FoshHA7Dsixs3LgRW7duxaJFi7Bo0SJs3boVkUgETz755IwsQFGUqTMlx9+5cycAYNWqVRPsu3btwne+8x0AwLPPPotUKoX169djaGgIy5Ytw4EDB67rGb6iKNPLlBzfkN+/k7EsC21tbWhra7vWOSmKMsNorL6ieJBZm48fGp7YSSdLijz6Sa45AKqMWgVptIelPF6orZKH8xPFm9gAIDQgYzjzYRmnWvOeDDf2kzbXFvmWFUhy6ZcVt2TFIFlRxspe0r6atONO1xZp45wj+ebkyYdFCnj6SWcfYxd7aiJtTPH2kfmwWgK5KtJpiLS5Brgy7yOFPmmefYndglhdBADIknmKY5YeWa53fEXxIur4iuJB1PEVxYOo4yuKB5m14l681YbvimKCFeelclFxnufj+3r6pS1CVCFSnNDOSHGOiWHOEB97rEnGgBZI6GuYtK+O9JMij0THy0eKCGxEOAuR9td5UvwzEy3tHlCsiw8T8phQ5bJ22iQMOF+sUxER8lje/1gDi5uVJhYaXCwnPhAnaySnzS6QY9pycDZOsdbZbN3+sUlvRq70Ptl6x1cUD6KOrygeRB1fUTyIOr6ieJBZK+45wxPz8S3ZaRrZaj79YGVE2NxqqQDZH54TNlMh6wYEB6Wy4hsmVR8BVGakeuUGZeSe8bFuK1LtGauX+4YHyckA4MRJlN+onI+pIaoSWQ4ttpng4WHpOSSykkTksWKZedJdp1gUGhMMQ0QoZaJbcp602RkWXcjHtok9FyaiHZkjOybtaOQrvYOQG5xoc4sUu2HoHV9RPIg6vqJ4EHV8RfEg6viK4kFmrbiXjwDmiiA4KgqFinxuMZGDRLW5X5BtslnaqJ2W0XysFTcAgLQzzoflaQ7EZeRfICGFOClT8vRbgBf1HLib9P0molJFn1SfmJiVqeJj865E0sRSqVN18pjFCl4GiLiYJynbLOU1OEwOSMZxSbcfALBI1CETEd1gae2v/aMkjZq00wZAxdfJxVDdKVTb1Du+ongQdXxF8SDq+IriQdTxFcWDzFpxr6LHhS/4mQrlI6JQYHJa4qdYWSnG+fpk9J0Zk/2VLZK+m76jSdiCF5J07Pwcub8/JVUhOyeVs2y1LJBHa/sV6/RCIuAiffIcsRbSiRbSjpuIXCw6EACcYTkOEwJHbiWdhsgxJ0elXYbVzbOJ6MZgkXLsXBRLy2V21oYcpO13KW2uAS4gAjzyz5eeeN4MqTNYDL3jK4oHUcdXFA+ijq8oHkQdX1E8yKwV91JzJtbcmyxkAMWbLkTiI3LbtFRc3DRJt22sk9sFyOcjidADgHyoSNjXJBItrD+zNNGmIUU0nBypxcfq+BlbzjFCGmrkKomQJnVTALylNmvmwQQ2tm8xAZPtzwSxTI20+XiZRHm8Iue3QCLyfCStF6VdAjD+KXTAYJfBpHFM6SX39I6vKF5EHV9RPIg6vqJ4EHV8RfEg6viK4kFmraqfqwDcK4TvSJ+UNcMXucRs5skQWytD2lLniOLdK7vwWC0xYRu9TbbTBgB/UsZWshz/ECmYGT4n23Zn58iM/Ewtf9uYCl8Iys/2LFPriTIeSJIOQsO8EuXYXDknFmYaGCnt6YztcsU7W03qHZCSA2w9rAgmbV9d5MkFXDJPskZDnviw1tlugIShJ4rci4m5MKkjUoF0hiqG3vEVxYOo4yuKB1HHVxQPoo6vKB5k1op7vszEyEcmFOWiPDYyKPU5oH9ImNw8yZOPSdGOinMXS4z/BJCNyURu1hHGBKVxsoDzeYSGZMymZcjcSe48E9iYCJi6jSerF5jARk5ReECOnSV1S2kYL3jRVRbOzTr7FAt1ngxbC8CLdeYqpY1dq3a2tI49xTrpuEQw9GUnnkujbbIVRfk81PEVxYOo4yuKB5l1v/HNp79JC5mJKbN59vulyG+afEGm4FpG/uA0hvzGd+W++bxM37Xzpf+eypP6euSnN/IFOU6eBJPkc1MI1MiTwBFS7I39xi+Q36UFVgMQQIH9pCa/8QtZUgOQjOOyAwI8XTcr11hg6bIlUiR2COSyQqFIfT5xTBb3xH7PF7usyHrykwLQ8rlL149hF9ckLFPKVn9Fzp49i5aWlhs9DUUpW7q7uzFvHukJfgWzzvFd18X58+cRjUaRSCTQ0tKC7u5uVFXxENlyYmRk5KZZz820FuDmWI8xBolEAs3NzbCvEr47677q27Y9/mllfdoDr6qqqmzfDMbNtJ6baS1A+a8nFpN5JQwV9xTFg6jjK4oHmdWO7zgOXnjhBTgOKUxZhtxM67mZ1gLcfOu5GrNO3FMUZeaZ1Xd8RVFmBnV8RfEg6viK4kHU8RXFg6jjK4oHmbWO//LLL6O1tRWhUAj3338//vCHP9zoKZXEoUOH8Nhjj6G5uRmWZeH111+f8H9jDNra2tDc3IxwOIxVq1bh1KlTN2ayJdDe3o6lS5ciGo2ivr4ea9asQWdn54RtymVNO3fuxD333DMenbd8+XL89re/Hf9/uaxjWjCzkFdffdUEAgHz85//3Jw+fdr84Ac/MBUVFeaTTz650VO7Km+88YbZsmWL2bt3rwFgXnvttQn/37Ztm4lGo2bv3r3mxIkT5oknnjBNTU1mZGTkxkz4Knz96183u3btMidPnjTHjh0z3/jGN8z8+fPN6Ojo+Dblsqb9+/eb3/zmN6azs9N0dnaa559/3gQCAXPy5EljTPmsYzqYlY7/4IMPmnXr1k2w3XHHHea55567QTO6NiY7vuu6prGx0Wzbtm3clk6nTSwWMz/96U9vwAynTl9fnwFgOjo6jDHlv6aamhrzi1/8ouzXMVVm3Vf9bDaLI0eOYPXq1RPsq1evxuHDh2/QrKaHrq4u9Pb2Tlib4zhYuXJl2awtHo8DAGprawGU75oKhQJeffVVJJNJLF++vGzXca3MOsfv7+9HoVBAQ0PDBHtDQwN6e3tv0Kymh8vzL9e1GWOwadMmPPTQQ1iyZAmA8lvTiRMnUFlZCcdxsG7dOrz22mu46667ym4d18usS8u9zOWU3MsYY4StXCnXtW3YsAHHjx/H22+/Lf5XLmu6/fbbcezYMQwPD2Pv3r1Yu3YtOjo6xv9fLuu4XmbdHb+urg4+n098yvb19YlP43KjsbERAMpybc888wz279+Pt956a0J1l3JbUzAYxMKFC/HAAw+gvb0d9957L3784x+X3Tqul1nn+MFgEPfffz8OHjw4wX7w4EGsWLHiBs1qemhtbUVjY+OEtWWzWXR0dMzatRljsGHDBuzbtw9vvvkmWltbJ/y/HNd0JcYYZDKZsl/HlLmBwmJRLj/O++Uvf2lOnz5tNm7caCoqKszHH398o6d2VRKJhDl69Kg5evSoAWC2b99ujh49Ov4octu2bSYWi5l9+/aZEydOmG9961uz+pHR97//fROLxczvf/9709PTM/4aGxsb36Zc1rR582Zz6NAh09XVZY4fP26ef/55Y9u2OXDggDGmfNYxHcxKxzfGmJ/85CdmwYIFJhgMmvvuu2/88dFs56233jK41LNlwmvt2rXGmEuPv1544QXT2NhoHMcxDz/8sDlx4sSNnfTnwNYCwOzatWt8m3JZ0/e+973xa2ru3Lnma1/72rjTG1M+65gONB9fUTzIrPuNryjKzKOOrygeRB1fUTyIOr6ieBB1fEXxIOr4iuJB1PEVxYOo4yuKB1HHVxQPoo6vKB5EHV9RPMj/H1tZT1G1nbB7AAAAAElFTkSuQmCC", + "text/plain": [ + "
" + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], "source": [ "plt.figure(figsize=(10,10))\n", "for i,(x,y) in enumerate(ds_train.unbatch()):\n", @@ -153,10 +195,21 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 9, "id": "a45f7176-6ce8-4a1b-b39f-96f5377b1113", "metadata": {}, - "outputs": [], + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "One element from the training set has shape:\n", + "Input tensor shape: (30, 1, 40)\n", + "Label shape: (3,)\n", + "Label : [1. 0. 0.]\n" + ] + } + ], "source": [ "for dat in ds_train.unbatch().take(1):\n", " print(\"One element from the training set has shape:\")\n", @@ -179,10 +232,21 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 10, "id": "791000c5-750d-4235-a27c-448b98c82c69", "metadata": {}, - "outputs": [], + "outputs": [ + { + "data": { + "image/png": "iVBORw0KGgoAAAANSUhEUgAAAnQAAAHVCAYAAAB4wWYZAAAAOnRFWHRTb2Z0d2FyZQBNYXRwbG90bGliIHZlcnNpb24zLjEwLjAsIGh0dHBzOi8vbWF0cGxvdGxpYi5vcmcvlHJYcgAAAAlwSFlzAAAPYQAAD2EBqD+naQAAbENJREFUeJzt3XuQVOX5L/rv6l59nenpYWaYGzPczKioESMEBJNA8pPJJtlekkrFOqbcmqNVctBEQiVGypyIqWwozQnHGMUkltGcc8RYMd72b5OE2TtxRIkXFLb+GCMKowwMzTD3nunp+3v+IEwcB4X+rrkt+H6q5g+bfnzf7net1W+/6+nntYwxBiIiIiLiWp7J7oCIiIiIOKMJnYiIiIjLaUInIiIi4nKa0ImIiIi4nCZ0IiIiIi6nCZ2IiIiIy2lCJyIiIuJy9mR34KPy+Tza29sRiURgWdZkd0dERERkwhhjEI/HUVtbC4/n1NfdptyErr29HfX19ZPdDREREZFJ09bWhrq6ulN+/pSb0EUiEQDA5/AV2PAVHJ/6Twuodj2ZPBUHAAf+s5eK8w7yd7yz0SwVt3jefrrNi0raqLj2VCkVt/3wWVQcAPS1R6g4fwd/SmRKuWPIlHBjCQDTygeoONvij3d2axl2vf3okSgZCXzl029ScbWBPrrNZ9supOJ8Nn8czJ92mIrryYboNou9SSruH31VVFxpgGsPAKb5B6m4D+JldJvd22qpuKoHXqHblNNDFhm8iK3D86FTNeUmdMdvs9rwwbYKn9DlfEGqXY/hP+A8IW5C58nxEzpPiLv4+4r8dJvBYu5wCfgKH0cA8IYDVBwAeELcceAN8qdELkRO6MixBABvOMPFeRxM6MgZHZtBwY4lAASKuWMvGOCPA28Rd9zaNncdAQA/+Tp9Gf564Le5Y8jOcu+PL8Afs/4Ad57Yef4a5A1wxy3zuSenmX9eYwtNO9OPIkRERERcbsqt0A2zPMf+CpS3uWUAT5oKO4ZcsTA+9uYV4B3kvs2n8/yQz/V3UHH//fAFVFzOwQqm3ce9P5kIPyb5cI6Kc/LTn5CPW3noH+JXvc6uOErFxQa52+Dw8mOSMdxx8H6ynG4zm+eO27CD2+B749OpuFI/fxszRV5LomSbQS+/ks1e9xIOVjCLjvDHrQhDK3QiIiIiLqcJnYiIiIjLaUInIiIi4nJTNofOnl4O21N4/gKbQ9c/i8+VKJ/VybU5wJcMmBZJcG2m+V9ttWemUXE5w31viB8ppuIAwEv+YNBUpOg2LTJ3ynLwi9OeQe4YymT4U783xeXfBW0u3+/z57xLxQFANs8dCC8fnkW3mSLf2+lFXAkaACj2cUnAnckw3WZZgMxXtrjcsmSOP2YP93HlR460l9JtFtdz7w+ZaSqiFToRERERt9OETkRERMTlNKETERERcbkpm0OX7TgKEBWzU6WfotpLVFNhAIBSMgcqm+Irw6fI3SnePcBtuwMA/9e7K6k4bz/XV3/SQYU2MjTwD74+m82lNSJRw9erSpRypzA7JgBweHcR1yZZ8izGp7fCQ6ZEpkv5NlPTuXqE7wzyLzT8Dpcbmy6hm8R75VxOZOgAtxNCehp/nnhS3AWB3GACAFDbzG03JsLSCp2IiIiIy2lCJyIiIuJymtCJiIiIuNyUzaFjhTu4/f76zuLfiqO9XL00M8S32Zfn2vSF+KQQ6wCXp2OTuVN5LtUGAODr4+KCPXyeTjrC5emUvkM3if653DGU8/Ov0xfn4vwDXJt5L59LmSXLrPnJ4wcAMhHue3I+yH+/Zs8Vi0v3AwB4B7hjL9BLNujhj4PQES4u7yB/0/uPD6g4B0MiZzit0ImIiIi4nCZ0IiIiIi43ZW+5egIBeKzC17sDPeQtRYt/K8wRstRFkN/yCeQds8wQfx/TJkMNWTrC18/FAUCO3FUtS5Y3AAAPd7cfXn63MVo+wN9yHapk3yMyzkH1GvY8CXXy749luA6nBvhzM8jtPugorQHk6wx1cte9UBd/IJA7wCHyDwcn58waLm4ev+2c/UEHF5hxUJ+FlB/k6jx5IvyWkAiQ99CT/HGQ7ThKxxZKK3QiIiIiLqcJnYiIiIjLaUInIiIi4nJTN4eurhYeb+FlMvI5LvfFdrBLSz7NzYvTNp+nAx+XT+Lp5YfcYrtLpr7EP8X/gN87LU3FJR2kNV5/4ctU3F+PnE23eeus7VTc3iS/191/KX2VivtvA+dTcWXeASoOAO5979+ouO44mYQJwGJTBT389cB8hjvepxfxF76wzeVdHegrpeL6uvncKYvcnvGIg+0ZK2q561dtMVljBcCeNi5vzxfkEoAzbfyYsNux2UN0k8hxlbfobQuPxTYUHJNLJYF7ny04Tit0IiIiIi6nCZ2IiIiIy2lCJyIiIuJyUzaHzoT8MF6iZkyey0PxOcihG5hFJl6RdZwAAEluLk7nwQHIk9tF5XLc6zQ+B50lX6jVzudOlV3M5Xpl2CJZABr8XL5Nd7aIbnO2HaHi6n1dVFypl6tXBQBBm8sN8kT4Nr1kLlwizReFKwtz/Z0T6abbDHm4HLp4mktkGvDz52a0hHt/kmn+I7K6iNsjb0a4l27zbbuKiqubxrUZ8/JJx4P9XP3W7BB/vfREuGM24yCX0iK2yMsPce+rVuhEREREXE4TOhERERGX04RORERExOWmbA6dNZSG5S0898pEufvyTvY0tAe4eXEuzOeI5Uu53KDorF66zXPKuH0C/R6uHtOOD+ZQcQDgIXM70g72OO3OcjWZllS+T7d5NMe1+engQbrN11JcHspgnsud2tZ7ARUHAL0JLu/K4yDZNDHE7RcZDnG15ADgSD+X18jGAUA0zBXn6kuQuVMJ/uOq14SpuEiEL3r27tHpVNyB3ml0m9lB7th735RTcSbP54FbvdyHrq+fX4cy3dwxZDuoTwoiNkfmyGuFTkRERMTlCprQbdy4EZ/97GcRiURQWVmJq666Cu+8886I5xhjsH79etTW1iIUCmH58uXYs2fPmHZaRERERP6loAldc3Mzbr75Zrz88stoampCNptFY2MjBgf/VfPjnnvuwaZNm3D//ffjtddeQ3V1NVasWIF4nPsJt4iIiIh8MssYQyeLHD16FJWVlWhubsYXvvAFGGNQW1uLNWvW4Ic//CEAIJVKoaqqCnfffTduuummk/4/+/v7EY1GcdncW2ETe7kmZ5cVHAMAh77A5R4AQLqc3HPUQRk6BLib+pU1vXSTl1bvp+Lah0qpuJ0H6qk4AMgNkfk2Cb7ekF3B5RQFAlw+pBNnVxylY9n8srcOc/tMpmNc/hMAwMv11TvoIBuFPK9z5VxuIgAEIikqLnOA34vTF3dyAStcppjPa7TIHKhcMZ88VfIP7lpS8gG/h3UuwG4kzIXlbf4YmPZmLxVnpfnrpTkUo+JyE7wglTUZPI9n0dfXh5KSklOOc5RD19fXBwAoKzs2iWptbUUsFkNjY+PwcwKBAJYtW4YdO3ac8P+RSqXQ398/4k9ERERETh09oTPGYO3atfjc5z6HCy449iu0WOzY7LeqamS16qqqquF/+6iNGzciGo0O/9XX86syIiIiImciekJ3yy234M0338Tjjz8+6t8sa+QyrDFm1GPHrVu3Dn19fcN/bW1tbJdEREREzkhUotF3vvMdPPfcc3jhhRdQV1c3/Hh1dTWAYyt1NTX/ypfp6OgYtWp3XCAQQCAwOlcuu/99wCq8Tk0gyNW2KW7j6vAAQD7G5UrkuLJcx1hcm13dFXST/76bq6tkkSkPRfw2k/CRKQ+RNr4WWLKcq3nmJA/FkF/J3pkRpdtMk6XLwty2s3BymnjIY884qNDJjol3P5/Hm6jlYoPc9sMAgFQFl9OWLeFyxLxhPsdw6Vlc/q+TeoTbh86n4qp+8QrdppvwmYLycQq69BhjcMstt+Cpp57CX//6V8yZM7Lw65w5c1BdXY2mpqbhx9LpNJqbm7F06dKx6bGIiIiIjFDQ99Cbb74ZW7ZswbPPPotIJDKcFxeNRhEKhWBZFtasWYMNGzagoaEBDQ0N2LBhA8LhMK655ppxeQEiIiIiZ7qCJnQPPvggAGD58uUjHn/kkUdw/fXXAwBuu+02DA0NYfXq1ejp6cHixYuxbds2RCL8FjMiIiIi8vEc1aEbD8fr0C3HlbCJHDpWeuVn6VhD7DkLAEPlfM0ztq6Sg5QQ5Mnusm1603xncz5uTDxZvs1UlEyeclDOix2TbBHf5mAdd/Cxx0HwCF9dySa34nSS3+rlSsIhw5eEQ7qUe3PzIb7OmqeEyzf1kXUXc1n+OJhf107FfW7ae3Sb9/+v5VTc3Gt20W3K6WFS6tCJiIiIyOTThE5ERETE5TShExEREXE5B9WWpiZvlKyv5eETmeL13NvoG+TztbJBrr+Rg3wtp2QZ9zqTZVxf7QQ/JrkgFxc5yOcUAVxsupj/XuUluxtq4489fz/X31Qp2aCDHEP2OMiScQCf35rny9DBO8S9SXkHrzMf53KcUwNcnKeIv3b942glFTenqItuM0e+PyIsrdCJiIiIuJwmdCIiIiIud9rdcrWKwlQcW+YCAHwDZMkAB+++n7xdmyznG02Wkrd1yCbpW3QAAn1cXKbISYkM7l5bLsDf/hyq4MbEyfFOl74hm/QmyPYApMgd/bJhB/V9Pmbf6pOGkduUAUCuiOuvv5svnZSJcMc7WyrFGP6YLQ1z9Wve6q05+ZM+RvG7p93Hq0xxWqETERERcTlN6ERERERcThM6EREREZebsjf57bIy2J7Cf8efPG8G1V7X+XwuCZsblHGw/RKbx5SpJfclAuCxyRyxJHeYBdr5n/3nydCsg1IpeQ93DHm5HZQAANkQF5cmq/sAQLoiR8V5Utx7G2rnv3f64lyck5I57Jg4KVsS7OD6y+YYAkCgixuXTAnXVxPnr9GxWBUVlwvyuZQ1jkogiRROK3QiIiIiLqcJnYiIiIjLaUInIiIi4nJTNocu29MLWIUnQgU/KKXay3+ey7EA+Dpr2VIuFwkAQKZ2eAN8m5fMfp+KqwxwiUwd50eoOAD4+745VFzuPTIBCkCgh4tL1NJNIjeXq69VXjpAtzktxBWG2/fKLCpuqIbPYzIeLtYq53NN8ynygpDkv1/nfVxs3s+/t54M1yab7+dxUKePvUZbeQe173Z1UHEOXqac4bRCJyIiIuJymtCJiIiIuJwmdCIiIiIuN2Vz6LxFIXgtojCTIfc0JPf+BPiaZ7mQg/k0mdqRHeBru+3v44pWlVVwOVeLoq1UHAC8P72Mimt3sF+k+SBIxQU/TSbfAVhQ3UbFdSaL6Tb3HCT3twxydbk81VyeIEBvq4pgIEO3Ge8nC8o5yNfKlnKZV5aDS1CG7K4nyzVa/B6f75cp5jqb4bYGP6a710GwSOG0QiciIiLicprQiYiIiLicJnQiIiIiLjdlc+hyA4OwrMI3ufR2ci/Jm6ym4gDAIku7edIO8rXY+lo5vs2ufm7z2aEyLm8vxSYnAij2c3XEAiE+dyrFlVlDQ7SXbjOb5/a3fGsP2VkAdh/XJlvzLNvJ5SYCgF2RpOIGBwN0m8bmXqc9wH+/Njlyn1MHOaPshtLZMBeXqOT7ytaw8/HlGoEicrPuo50OGpUzmVboRERERFxOEzoRERERl9OETkRERMTlpmwOHcsq4epreQtP1xuWJ8tOsfuxAnT6Cqw0P4dPJ7gX2pfm9kd9Jc3txwoAnQky36+Hz9di39vWbq5mHgAc9pdQcXacPw4q3uIOvlQJlwMV7OVzpxIV3HGQnE43CS95VS06xLdpc6mCyNtOcui42Bx5vQz2ONl3lotl4wAAcScJeCKF0wqdiIiIiMsVPKF74YUXcPnll6O2thaWZeGZZ54Z8e/GGKxfvx61tbUIhUJYvnw59uzZM1b9FREREZGPKHhCNzg4iPnz5+P+++8/4b/fc8892LRpE+6//3689tprqK6uxooVKxCPxx13VkRERERGKzjbY+XKlVi5cuUJ/80Yg3vvvRd33HEHvv71rwMAfve736GqqgpbtmzBTTfd5Ky3p8LPJWiEOslicgCMl6sBFeC38KTrR2UifM5MxnDJQWmyVpqHTRQE0Bfn8vac1OljExgSR8l6VQDSUa7eXraE21cVABLTufH0x7nxHCrjM0PY3FgvmZMGABa7tzOfvgkPedwWxfjrXs7HtZkmr0Gho2QxOQDBHf+g4qwgX48wn+D2sBZhjWkOXWtrK2KxGBobG4cfCwQCWLZsGXbs2HHCmFQqhf7+/hF/IiIiInLqxnRCF4vFAABVVVUjHq+qqhr+t4/auHEjotHo8F99ff1YdklERETktDcuv3K1PvJzdmPMqMeOW7duHfr6+ob/2traxqNLIiIiIqetMa1DV119bD/UWCyGmpqa4cc7OjpGrdodFwgEEAjweQpjJdTB5SIBQC7IJb9kQvx8mt3m1EFaGkCmlx2MR6m4kgCfyJQ7wuXQ+fsdjAm5V6l3iM/by3dxp7BVzOfQJcu5ON8gmTvVzfc1XcyNp5Mcujx7VXVybpJyfv7YcxLLSJeQ+9UCCEW4+qRsrT0AMGknSdIihRvTFbo5c+aguroaTU1Nw4+l02k0Nzdj6dKlY9mUiIiIiPxTwd8lBwYG8N577w3/d2trK3bv3o2ysjLMnDkTa9aswYYNG9DQ0ICGhgZs2LAB4XAY11xzzZh2XERERESOKXhCt3PnTnzxi18c/u+1a9cCAK677jo8+uijuO222zA0NITVq1ejp6cHixcvxrZt2xCJRMau158gX8Td/uw9m7tFB/Db52S4XZsAANki7v5MtipDtzmjppuKm13Cxf19P7/1lzfBLT77HPzIOk/egqK3jgOQLeJuR3orh+g20z7uHEv3sOVOqDAAgDfFnScB/i4vjJc8Dsg0CgDwpCf+fq0/zpU8SUzn7knH6/nbn33XcteS8BH+fa3YRl6j2w/TbcqZreAza/ny5TDm4w9Uy7Kwfv16rF+/3km/REREROQUaS9XEREREZfThE5ERETE5ca0bMlU4GnvoOKKp4fpNtmf0wd6+ZyQbJiLHeziE7aOHqym4jpzXFzFPj5/xR7ikqB8Aw62QgqQ34+cVH8g36JEJb/dWIYMZUvmJKfx3zs95G5RvkE+ic6b5gbUy6c1Ihsirwe1/MHnSXPjkpzOHQi56Xz+b7R8gIrrHuBzq1OlXN5e1b3KoROOVuhEREREXE4TOhERERGX04RORERExOVOuxy67NFOKi54cBrdpplVSsX5u/j9hfIhbujsBL/NWrKMm/9bZFpa8aE0FwjAynF5Or6uBN1mZhqZb+NxsL0QWfMs0MPnIxmyv/2zufzNRBX//vi41ClkyC3DANB5jWkHdSlZxsHLzHA7+sHKc+NpH+Hzf4eKuNh81sG5SUeKcLRCJyIiIuJymtCJiIiIuJwmdCIiIiIud9rl0LFyxdz+lAAwWM29jXkfX+OIFa/j5/A5tlQfWdLLP+Bgc0uSr5g/JTwZct/QTr4A2VANNyjpCH8csHXhQt3cgVAUo8IcYfdnBvg9WdlcUwCwyHOMrdMHAMkKLs7H7s3roF5jZn8xFWci/KCEjyqLTiaWVuhEREREXE4TOhERERGX04RORERExOVOuxw6b5QrjtT+uQjdZo4s7ZYu4d9+b4qLy/Gpggh0c3HeFLl3Y4BPmnGSj8S3yb3Ogdlcfg8AZIPke+QgHynQx71OT5qLyzrYy9U3wLWZd3CeZMhcU5svSwkPebzn+dJuKDrExbH5fux1BOCvJZkwt083AETf44ogKvNOWFqhExEREXE5TehEREREXE4TOhERERGXO+1y6Myn6qk4Ng8OAJLTyX1D+/lEpuR0LhElOquXbrNvH7ffrTfBvU52H04A8JL5SJki/pTIkflIbN0yAJj2LldILBviv8uli7nxTJZx+Uhpcs9QgN8H1nKQyGTI03pgNplcBsCKcvse2wf5ZMG5T/ZRcanpXJJh/2z+RBkia+Y5kYlwF4TT7kNZJoxW6ERERERcThM6EREREZfThE5ERETE5U672/XpMi4nhM25AoBcgEu4sUIO6qyROT6VxXxiWnY2lwOVzXHfG5JtfH02O869t05yKdkaf05qgfWnuFM42OMgX4sMpfc45buKTJQ8N6v4C8K5tdzms1nDf78u8XGFKXf5Z9Bt/mM1lwvn7eeO2VwkQ8UBQLSSu+4NxPkcw84Et1d39f+gm5QznFboRERERFxOEzoRERERl9OETkRERMTlTrscOk+K29TQQfoKTJBrM5/hc+iMj9wXM8+/0JnTeqg4D7k74dtkfhgAGDJ/xcOVdQMApMl0m1yYTxIbquLGM1E98d/lDDucTja3JJNNy6J8runc4i4qLudgg90AeeAeKefzVI/6uNhQNZcL1zCtk4oDAD/5/vzDrqTb7Kl2sCGwCEErdCIiIiIuN24Tus2bN2POnDkIBoNYsGABtm/fPl5NiYiIiJzRxuWW6xNPPIE1a9Zg8+bNuPTSS/HrX/8aK1euREtLC2bOnDkeTQ7z7vgPLu6Cz9JtWmluXuxJ87dY8j4utiMeodu8bOY7dCzj6DT+dlBnjLvdkffzY5It4W69g7xlDwAp8i3yFfElIDJD5GWDfGtnVHO3+gFgdkk3FRdL8OdJLFlCxXkc7DcW9HLj2dHHv86An2vT9nApBh4H9WvaBkqpuD4ydQMAAt38tUSEMS4rdJs2bcINN9yAG2+8EfPmzcO9996L+vp6PPjgg6Oem0ql0N/fP+JPRERERE7dmE/o0uk0Xn/9dTQ2No54vLGxETt27Bj1/I0bNyIajQ7/1dfXj3WXRERERE5rY37LtbOzE7lcDlVVVSMer6qqQiw2uoL6unXrsHbt2uH/7uvrw8yZM5FFhvp1G3vXIpfmK8Pnh8hfuSa5nRcAIE/etsgluIryAJAa4G/TMXKDfF/zSW48cykHt8HJ4wCGv+XKylv8WOaTE3vLNevgOMh401ybDs6TTJZr08ktV4+HG89cgr/u5bLcL0dzXu54z/i49xXgjyEn74+H/JV+1kzsdVamniyOHQPGFHZNGLeyJZY18uptjBn1GAAEAgEEAv/ab+n4LdcXsZVrmC078dCTZOCZY2Iz6ESOaXMQ++qY9UIm2xuT3YEJouusHBePxxGNRk/5+WM+oauoqIDX6x21GtfR0TFq1e5Eamtr0dbWhkgkcsIJYH9/P+rr69HW1oaSEi75WCaPxs/9NIbupzF0N42f+33SGBpjEI/HUVtbW9D/c8wndH6/HwsWLEBTUxO+9rWvDT/e1NSEK6+88qTxHo8HdXV1J31eSUmJDmQX0/i5n8bQ/TSG7qbxc7+PG8NCVuaOG5dbrmvXrsW1116LhQsXYsmSJfjNb36DAwcOYNWqVePRnIiIiMgZbVwmdFdffTW6urrwk5/8BIcPH8YFF1yArVu3YtasWePRnIiIiMgZbdx+FLF69WqsXr16zP+/gUAAd95554gfUoh7aPzcT2PofhpDd9P4ud94jKFlCv1drIiIiIhMKeO2l6uIiIiITAxN6ERERERcThM6EREREZfThE5ERETE5TShExEREXG5KTmh27x5M+bMmYNgMIgFCxZg+/btn/j85uZmLFiwAMFgEHPnzsWvfvWrCeqpnEgh4/fUU09hxYoVmD59OkpKSrBkyRL85S9/mcDeyokUeg4e99JLL8G2bVx00UXj20H5RIWOXyqVwh133IFZs2YhEAjgrLPOwm9/+9sJ6q2cSKFj+Nhjj2H+/PkIh8OoqanBt7/9bXR1dU1Qb+XDXnjhBVx++eWora2FZVl45plnThozJvMYM8X8/ve/Nz6fzzz00EOmpaXF3HrrraaoqMh88MEHJ3z+/v37TTgcNrfeeqtpaWkxDz30kPH5fObJJ5+c4J6LMYWP36233mruvvtu8+qrr5q9e/eadevWGZ/PZ954440J7rkcV+gYHtfb22vmzp1rGhsbzfz58yemszIKM35XXHGFWbx4sWlqajKtra3mlVdeMS+99NIE9lo+rNAx3L59u/F4POYXv/iF2b9/v9m+fbs5//zzzVVXXTXBPRdjjNm6dau54447zB//+EcDwDz99NOf+PyxmsdMuQndokWLzKpVq0Y8du6555rbb7/9hM+/7bbbzLnnnjvisZtuuslccskl49ZH+XiFjt+JnHfeeeauu+4a667JKWLH8OqrrzY/+tGPzJ133qkJ3SQqdPz+9Kc/mWg0arq6uiaie3IKCh3Dn/3sZ2bu3LkjHrvvvvtMXV3duPVRTs2pTOjGah4zpW65ptNpvP7662hsbBzxeGNjI3bs2HHCmL///e+jnv/lL38ZO3fuRCaTGbe+ymjM+H1UPp9HPB5HWVnZeHRRToIdw0ceeQT79u3DnXfeOd5dlE/AjN9zzz2HhQsX4p577sGMGTNw9tln4/vf/z6GhoYmosvyEcwYLl26FAcPHsTWrVthjMGRI0fw5JNP4qtf/epEdFkcGqt5zLht/cXo7OxELpdDVVXViMerqqoQi8VOGBOLxU74/Gw2i87OTtTU1Ixbf2UkZvw+6uc//zkGBwfxzW9+czy6KCfBjOG7776L22+/Hdu3b4dtT6lLyhmHGb/9+/fjxRdfRDAYxNNPP43Ozk6sXr0a3d3dyqObBMwYLl26FI899hiuvvpqJJNJZLNZXHHFFfjlL385EV0Wh8ZqHjOlVuiOsyxrxH8bY0Y9drLnn+hxmRiFjt9xjz/+ONavX48nnngClZWV49U9OQWnOoa5XA7XXHMN7rrrLpx99tkT1T05iULOwXw+D8uy8Nhjj2HRokX4yle+gk2bNuHRRx/VKt0kKmQMW1pa8N3vfhc//vGP8frrr+PPf/4zWltbsWrVqonoqoyBsZjHTKmv0xUVFfB6vaO+hXR0dIyavR5XXV19wufbto3y8vJx66uMxozfcU888QRuuOEG/OEPf8Bll102nt2UT1DoGMbjcezcuRO7du3CLbfcAuDYBMEYA9u2sW3bNnzpS1+akL4Ldw7W1NRgxowZiEajw4/NmzcPxhgcPHgQDQ0N49pnGYkZw40bN+LSSy/FD37wAwDAhRdeiKKiInz+85/HT3/6U92pmuLGah4zpVbo/H4/FixYgKamphGPNzU1YenSpSeMWbJkyajnb9u2DQsXLoTP5xu3vspozPgBx1bmrr/+emzZskU5H5Os0DEsKSnBW2+9hd27dw//rVq1Cueccw52796NxYsXT1TXBdw5eOmll6K9vR0DAwPDj+3duxcejwd1dXXj2l8ZjRnDRCIBj2fkx7nX6wXwr5UembrGbB5T0E8oJsDxn2s//PDDpqWlxaxZs8YUFRWZ999/3xhjzO23326uvfba4ecf/7nv9773PdPS0mIefvhhlS2ZRIWO35YtW4xt2+aBBx4whw8fHv7r7e2drJdwxit0DD9Kv3KdXIWOXzweN3V1deYb3/iG2bNnj2lubjYNDQ3mxhtvnKyXcMYrdAwfeeQRY9u22bx5s9m3b5958cUXzcKFC82iRYsm6yWc0eLxuNm1a5fZtWuXAWA2bdpkdu3aNVx2ZrzmMVNuQmeMMQ888ICZNWuW8fv95uKLLzbNzc3D/3bdddeZZcuWjXj+888/bz7zmc8Yv99vZs+ebR588MEJ7rF8WCHjt2zZMgNg1N9111038R2XYYWegx+mCd3kK3T83n77bXPZZZeZUChk6urqzNq1a00ikZjgXsuHFTqG9913nznvvPNMKBQyNTU15lvf+pY5ePDgBPdajDHmb3/72yd+ro3XPMYyRuuxIiIiIm42pXLoRERERKRwmtCJiIiIuJwmdCIiIiIupwmdiIiIiMtpQiciIiLicprQiYiIiLicJnQiIiIiLqcJnYiIiIjLaUInIiIi4nKa0ImIiIi4nCZ0IiIiIi6nCZ2IiIiIy2lCJyIiIuJymtCJiIiIuJwmdCIiIiIuZ092Bz4qn8+jvb0dkUgElmVNdndEREREJowxBvF4HLW1tfB4Tn3dbcpN6Nrb21FfXz/Z3RARERGZNG1tbairqzvl50+5CV0kEgEAfA5fgQ1fwfGDV32Watc4eCe6//MQFVdWMki3OZgKUHGRYJJu8/DhaVTc8nnvUHFfnfa/qDgA+EvvBVTcu/3T6Tbbe6JUXKYrRLdZvovLmuify69+p6dnqDhryEvFnTXvEBUHALXhPiruvT7+OIjt5WJNNEu36QtyY5LP8Vk32QR30bSyZJsew8UBgD/PxeX586S6iTvei555jW5TTg9ZZPAitg7Ph07VlJvQHb/NasMH2yp8Qmf7glS7TiZ0njB3obGL+Au418tN6OwQf1H0hLj31l/sp+LCEe6CCAD+LNemnePeVwDwprj3J5fg4gDA6+c+HD1B/oPKE+LGxQIXZxfxY+IvIo+DLN8me56YEH89YMcEDiZ0HvKieaZM6GwfebwTn3tymvnnoV5o2pl+FCEiIiLiclNuhc4pb4b7FmdyfJu5zMTPi3MOvjmySsq5W8RHhgpbNj7uosBRKg4AXvZxfQ3b3K0rAPD5uIMol+CPn87PkKsWNrliAWBaVZyK83q4Ni8oPUzFAcDBBJcmwPYVAHy1CS7QwQJUOZm+0TMQptvMpbkVKE8ozbWXdPBxleWulx4yTQAAwF6iLQefJ4Y7bi0vOZYF3hL8sFxvLx0rJ6YVOhERERGX04RORERExOU0oRMRERFxudMuhy7n4xIXnPzK1evj8hY8Fp80M7+6nYqbG+6k2/R5uByxCpvLudp45N+oOAD472/Mp+KC7fyBkC7jjoN8CZ/AGSXz2aYXD9BtzizuoeIODpZScX9unUfFAUBqiPvFYJ79JSaAQDGXI5bN8Mde+8EyKs5y8stRMr8s7+XeW7ufz2czZKhvgM9V9vdxx4FdXUm3aRJcCS0rwP0anG0PADxhLn8znyBzVAF4Atwv0PMpvtzXRNIKnYiIiIjLaUInIiIi4nKa0ImIiIi43GmXQ5cNT3x9No+Xy53ye/nK8Gwu3MxAF93m5ne/QMUl01weU7Kb3xLL180d2jl+0waYAHcclFb3022mybyr91qr6TYPHOH2WvaQh3vewVUqX0Lmt5J1ywAgd5jcxSVFNwkUc7lw4faJv16aSVhGyJLl9vz8qYlAJ5lfluU/F+hcOLJNk+Pzf/NDZL4fWTMPcE8uHEsrdCIiIiIupwmdiIiIiMtpQiciIiLiclM2h84TCsJjFZ4PkCdvr6ejfC5JJsW9jU7q0B1Nc3voVfj4+mPLZ7xHxQ3muJyiN4J1VBwAdKe4PTx9/Q6+45B5V4urD9BNtiVKqbi9qSq6zXyAzE8k85hyRXyeTmAalzPjZC/X5MFiKs5ykFxmyMtXspxuEl4yHYmt+enht1mm69Bl+TRe5P3k54LNfyznu3upOJPl3lwn+WxsHTrk+HPTSc6fG2iFTkRERMTlNKETERERcbkpe8s1n0wjT9ySjO7j7gMMzOTrVSQOcOvynhr+luv/ePccKq70PH7blEo/t83UhaE9VNyuozOoOADwV3Gv0xvjbpcBQCbKxdUGe+k2LynZR8U1B7njBwD+7ptNxYWD3FZI+TyfDlEa5kojeC3+tg6iXK2L1kPT6Sbtdi6tIRPlb0Gxx7unlDsOjIPjwGS4W4P+Q1zJJQBIT+NKiNi9XDoNAFhD3OefBe7zz6S5sQQc3K718WNikbeW3XKrVit0IiIiIi6nCZ2IiIiIy2lCJyIiIuJyUzaHzp5eDttTeA5CLsltYVJ0mM8FGKzi8leCDrb+YvNJir38/kK7+7gtny4McWU5SgL8Ni1esiRM73y6SVx5VgsVNy/YTrcZz3O5Lx/EubIuAFBWzOUnhnzcOWY7KCGSypElVhyUEOlPcmNSXdlHtxlLlnGBGT4vLVjNHQds5nBxiL92dcW4hD+2xAoA5H3ce5sr5vO5veXceW3C3GeYJ8ZtQQkApobMGT1wmG7TCnCv0yT43POJpBU6EREREZfThE5ERETE5TShExEREXG5KZtDZ9JpajsbY3O1bbrO5+6tA0DRES4rZCDD1SkCgHAxl09yTpDPP1hZ8iYV99MD/5mK6xzga8JVFHNbnC2cy2/DdV6Yy4V7eeAsus2/HWqg4qaF+JwQNheO5SSH7mAPdwzl8vx33VQfdy3xBvmc2mgNV/suk+W3bkocLeICyfzfdIZsDwC7y6LFDwnf5lvv0m3myDprnhBXSzU3xNV5BAAPWTPPZBwMiofPGXUDrdCJiIiIuJwmdCIiIiIupwmdiIiIiMtN2Rw6ZLOAVfh80z7C1XLK22EqDgA8WS5ZIpnl96S7bOY7VNy/d/GF1n48YysVlyBf50VVh6g4AEjnuUObzYMDgHt2fZmKy2X471WRKJfDYpgE1X+Kp7kcMR+ZCzeQ4vNbM+QentnUJFwaj/L1x/p6yPfIy+8njTCXy+SxuePAdPHHAZvPlufTnJGOcMdeUVkp3WY21kHFmTw3JpbNf4axbcLrYB0q52CPZhfQCp2IiIiIyxU0odu4cSM++9nPIhKJoLKyEldddRXeeWfkSpExBuvXr0dtbS1CoRCWL1+OPXv2jGmnRURERORfCprQNTc34+abb8bLL7+MpqYmZLNZNDY2YnBwcPg599xzDzZt2oT7778fr732Gqqrq7FixQrE4/Ex77yIiIiIAJYxhk6iOHr0KCorK9Hc3IwvfOELMMagtrYWa9aswQ9/+EMAQCqVQlVVFe6++27cdNNNJ/1/9vf3IxqNYjmuhG0Vfn/ebuBqer13fRUVBwDsto92Az/JnV/D5Xr1pvk8ndowl5/4t/+YR8XNnHmUigOAQ52lVFxpCV+fbfCVCiouxKW9AACGKrm4PJ/6AjI9ESDT9rz8lr7IkWlXbM4VAHi4UmBwsM0yPGRpQI+Tkl5kmxm2vKSDMbHI1ClPjm+z+kXu+u4d4A/47D+4GnbeYm5Q8g7q0Fl+LkGR3Y8VAJDjBjQ3wQtSWZPB83gWfX19KCkpOeU4Rzl0fX3HPuDLyo5tDN3a2opYLIbGxsbh5wQCASxbtgw7duw44f8jlUqhv79/xJ+IiIiInDp6QmeMwdq1a/G5z30OF1xwAQAgFosBAKqqRq52VVVVDf/bR23cuBHRaHT4r76+nu2SiIiIyBmJntDdcsstePPNN/H444+P+jfLGnlvxRgz6rHj1q1bh76+vuG/trY2tksiIiIiZyQqG+Y73/kOnnvuObzwwguoq6sbfry6uhrAsZW6mpqa4cc7OjpGrdodFwgEEHByT/wjsu/uo+I+9Rt+f8psbRkVF1scodvc33M2FZcucVB/LMYlolSTOVeJYM3Jn/QxppP5SEMVDuoRkrlBgzPoJpGudJAERbKS3PdANtc07+eP2XwRlzPjoEwfzfI5qJHF9pccSwDwxsl9YMm+5n18Ep2JkOfJEL/XrZ3gru9VT/P7bds11Vzgxyy4nMyk1D0j8+AAIE/uH+sWBY2HMQa33HILnnrqKfz1r3/FnDlzRvz7nDlzUF1djaampuHH0uk0mpubsXTp0rHpsYiIiIiMUNDayc0334wtW7bg2WefRSQSGc6Li0ajCIVCsCwLa9aswYYNG9DQ0ICGhgZs2LAB4XAY11xzzbi8ABEREZEzXUETugcffBAAsHz58hGPP/LII7j++usBALfddhuGhoawevVq9PT0YPHixdi2bRsiEf72ooiIiIh8PEd16MaD0zp0LPvcBjp2aGaUihus4V8fW1cp0MfnH4TbBqi4wdncZD50mM93ML6Jz+4YrOVyQRNVfF9z5F6TTvaonOg2neSz5f3c5S1fThaTAxAo5hI4U0f5/E0EuPPaSd5ePsXll1k5ckBtBx9VGbLNLH/wVb/ExU7bydffRJotDkjmGBY5OGYHuZqfJuGg9p2X3Nu5q4tuk2pvMurQiYiIiMjk04RORERExOU0oRMRERFxOXZXxtOOifF5C2ZOKRXXP5fPzwh2cnFDFfyQ5wKnfi//w0JHuJyivJ//vmHluXwb7xBf1y3UwfW3qJ3PY/ImuFyv3nn8j5TYHLocWU8uVcq1BwDG5tq02/gkw1QFF2vzJc9gvGRtQAefADZ5qhjydRoHOXSeFHcc+Pv4a3S4gyyGmXKwqS+LPPhMjN+Imt3LFR4HSbVOYl1AK3QiIiIiLqcJnYiIiIjLnXa3XA/+iNuRIh118JN4MvRTn/2AbvKdd7j9oqwi/paiJxek4vx93HJ+PsB/38gUcbFD5Xyb0X18qQtW90LuNniKCwMA5EJcnJe8k0QedsdiQ9zJmazkrwdsWY58kL/1bhVxx14+zd/n9XdwZZdy5K1TU8Jfu3KD3Ov0dPLvjzdB9jc5CbdcfdxYWtPL+TY93LXWcvL+ONg2zA20QiciIiLicprQiYiIiLicJnQiIiIiLnfa5dB52DQmB79mzhVzuS9X1+yk2/x/stzQTQ8N0m2+lpnNBRru5+m+QT6PiY2ljx8AqWlkrqDNn4YWmaZT3M6/t5ki7mSxyPSVZAUXBwC5INdX76CT0gjce3v+xXxObYmf2ybv5fdn021m67kBNTmyxAq7fRcAe4hrs/gQf57Y7d1cIFvOAwD85HaSZD7bpOT7ZfiLdK6rZww7MvVohU5ERETE5TShExEREXE5TehEREREXO60y6ELdnFxQ1UOGg1ziUx9uTDd5LTgEBVX7ONybQCgpJzLv8sF2Bw6KgwAMDCD+66Sd3BGZMJkbpCDLZ+8ZDpJ3sfnI7G5cP1zubi8j89jypWQnc3w33VNiGvT9vB16DqTRVScIWvmAUAgRNa+M1yb6QEHuWWkvrP498eT42qFlv5tP90m2C3gevuoOMvr4OJF1r5Dlq8l562u5Jo8eIhucyJphU5ERETE5TShExEREXE5TehEREREXO60y6Hzprl8m9ARPldioJjLI/jd/sV0m337S6k4X5yfw5fu5d7bYA+XY5iK8vkZ1Tu4BLx0eYBuk+VJ8blTLCc5dGlyXMI7yX1VS/ljNlHFXeIsB0PiG+T6++7bn+IbJYezJME3ye7NmydTp0pSfC6lh6zXGOjn87WKWvupOFNRSrdpDXC51VakmG6TZbp7uUC2Zh4AK52mY91AK3QiIiIiLqcJnYiIiIjLaUInIiIi4nKnXQ5dqpRLJklOd5CfQe4TeNY0smgegJ1FESouy79MJCq51zlUzh1mvgEqDAAwWBei4jLFfG4Zu39srpTPFbSTZJsBJ6+TSzDzJrk4v5fvazbExeadlDxzcI7RTZJfzZ3sXcwee1aCi2OPOwCwh7jYDJkfDQDG5gbFwS7CMH1xrk0fORUon8bFAbBCQS6wmKu5CABIOzjgXUArdCIiIiIupwmdiIiIiMtpQiciIiLicqddDp2HLDOTC/H5GcWtXJ6FvZBvc86sDirug1g53eYgGWp6uYQkb5LPJkl1ct9VnOQUxWdy/WWPWQCItHFxTvKRWN3ncgXIUnyaDl1/jK2VBgDZEJcj5uR4Z2vCJarpJun+Zou4OG+aX38IH+bGxD8w8QmRVjdXvw4AQOalmTiXsGw52FcVJVwe+MB5FXSTHrJObfAon++eT/H7pxdKK3QiIiIiLlfwhO6FF17A5ZdfjtraWliWhWeeeWbEvxtjsH79etTW1iIUCmH58uXYs2fPWPVXRERERD6i4And4OAg5s+fj/vvv/+E/37PPfdg06ZNuP/++/Haa6+huroaK1asQDzO/ZxaRERERD5ZwTl0K1euxMqVK0/4b8YY3Hvvvbjjjjvw9a9/HQDwu9/9DlVVVdiyZQtuuukmZ709BUUx7p5+z3y+TTbf5r1ePp/N5+FyoEw/nxxUVMvlWaQOcXkdgR4qDACfl5Z1UOIoU0zmZ3TyuVP9s7nYonY+28J42Nwprr1skYMakWmur+npZPIdAO8gl1Pr4bYfBgD4ye/LxkHRsxy57XH2HG4D2XSGP2b9fdw1qOgwfxxYWTJPla3PBgA57vOPrkPnQHJOGRV39DN8Xy1yOGe95CCp1q05dK2trYjFYmhsbBx+LBAIYNmyZdixY8cJY1KpFPr7+0f8iYiIiMipG9MJXSwWAwBUVVWNeLyqqmr43z5q48aNiEajw3/19fVj2SURERGR0964/MrVskau4xtjRj123Lp169DX1zf819ZG1mEQEREROUON6Y3z6upjRY1isRhqamqGH+/o6Bi1andcIBBAIEAmY5xA5KV9VJz/4rPpNjNcOR1Yz/P1dLrmkvV/HOTMDLWWUHG+T3EJPoNHw1QcAHhKuCQ608kfiyZKFrFz0Ka/j4vL+53sGMmxyRwx3wDf14GZZP6dh8/by0/jjr204TeQDfRw71Gi5uTP+TjZIi5HrPGsvVTcrqMzqDgAGApyeWnZIn4v11yYrL+Z52tEWt1cfiL85LHn5deEvEnuMyzygYOcWvISbUWK6TYxgT8IHdMVujlz5qC6uhpNTU3Dj6XTaTQ3N2Pp0qVj2ZSIiIiI/FPBK3QDAwN47733hv+7tbUVu3fvRllZGWbOnIk1a9Zgw4YNaGhoQENDAzZs2IBwOIxrrrlmTDsuIiIiIscUPKHbuXMnvvjFLw7/99q1awEA1113HR599FHcdtttGBoawurVq9HT04PFixdj27ZtiETI+5IFyh7tpOI8Gf6Wa7qEWyIfLOOX1n3TuL1+wiFyjyAH/F5uab0rwmcE5Ae4n5mbML+Vjd3B3bZwst1YUWzit/BKRbmFfbZEBpvSAPBlS+xeB6URMuQWcHyFDHp7tLyPv31lkaHPv/8pKi7dGeIaBFBGFk8YqOFvYgU7yS0hD3LloQAg38vlYHgqp1NxxubfH99R7nWW9w7RbWaj3K139n2daAVftZYvXw5jPv5MtiwL69evx/r16530S0REREROkfZyFREREXE5TehEREREXG7i9/s4Rd5oCbxW4TlJ+YaZXIMOqjgUHeDmxalLyJ+YAygv4WpADGX4LUzOKTtKxV0UPUDFLZ7HlaABgFt2/29U3LQiPj/jUIbLQ4k30E2i/3wuh87K8gf8WQ2HqLiKIHe8zwp3UXEA8O5AJRW36z3yOgLA6ucuq9FPddNtVoS568G+I3zpJI+XS6JLD3C5plaETzbtvoQ7T+xO/iMy2MuVIypr4fOcTZp8j1Jcm1aa3GMRoLcpQyW3ZRgA+A5wOfbZBP9ZPZG0QiciIiLicprQiYiIiLicJnQiIiIiLjdlc+hyff2wrMLzvewerraNN8UXu7LJtKskW5gLQMDLFa3qeIvLKQKAjs9weQT5Eu57w+JAkooDgP/9nL9TcecEDtNt/tf8V6m4o738tjK5Hi5Pxyrm85HiKa6WUyrHXW6m+ck9wwDUhLj6UT11XL4oAGTyXP2xdJbfZipIXg+ml/I1z/oS3HEwvZbLFewZ5OvQ+aJcvpZdzdd5TMS4/MRpST6HzhMktxH8mL3WT94gvyZkotxnrjXIfy7AwXvrBlqhExEREXE5TehEREREXE4TOhERERGXm7I5dHbDXNjewvMB4vPKqfaGqvg9DQdncnkWAS+fn+H1cLH5aj6HoJTMadvZO4uKs8taqDgAyBguH4mNA4DBFFdfK5fkT0N2r9J8hn+dEy3rYEwuiXC1DOeG+By6La2fpeLCfr6m18F4lIozDvJ4vR7umsleu4J+frPboRRXfzNFnl8AYEq5OIvNgwP4nLYUeeyFuDxKALCyZB26PP9ZDS93LbHIOAAwbL09glboRERERFxOEzoRERERl9OETkRERMTlpmwOXWZ6MYxd+P35+EzuXrcnw9+Xz0/j7pH7bf7eOlt3qno6V5cLAL4z439QcX8f5DYrfS4xjYoDgDf766i451Nn020m9nJ5TFaAP/ZyxWweCt0kusi6eWVRruZZX5qvP5bMc7lT0+043Wb3gVIqrr+fz9OpW8Dtr3vetBjdZjrPfXzsOjqDirPJ3DsAKCvmamgeOsxfg2b9naz1aDv4WCb3cjXkXq5wsJcruw8svV8tAMvHvbcTmQfnhFboRERERFxOEzoRERERl9OETkRERMTlpmwOXWxxCN5A4Tl0gc93Ue3Ni/C5ZUcTXE5RV38R3eY/DldRcZFifh+89fuuoOJivSVUXHqAq+sGAJ6+iT+0vVmuZpVx0FW7mwv2Jvn6WulpXK5XxyDX16NHudxEAHi3nNtPs7eT31/XO8B9T/bxaXs4+EYtFdfRwL/OfJ57nakhLq/R5BysP7Bpqgk+rzFVxvU3NMRfo+lcuElg+rgD3lPKfZ4AAAL8Z4obaIVORERExOU0oRMRERFxOU3oRERERFxuyubQRfflYPsKr/1ypKyMaq+3LkzFAUBplKtxZDuoQ7dq3nYq7vmuc+g2d703k4ozGe57g2eI/77h6yPze+r4Gkdsf/Mhvr5W6CC5N6GDOnRpsjSX5eUSmfxhvtZVPk/mCpL7lAJArpyrEZkMONgvspQ7br1kHhzA13Y7kuRyoPIZPu8zUMrllqUtPucq7+XeW8vJ/qjknqNs7p0V4XMwTZyrS5k90kG36Y3y+bhuoBU6EREREZfThE5ERETE5TShExEREXG5KZtDF3nhXdhE/kLJm1wO3Tv/B1fXDQAGA1zOjPVmhG7z/z78n6i46XO66TaRInPhyDhfLZejAwDBd7ncDs8FQ3Sb2SNcfa35579Pt/m/QtyetYFiPi/Nmyb3QyTz9oxxUDMvw/V1RnUP3WYyy7XZ08vXpVw6t5WKi9h8zbOs4fK1SoPcOVYRGKTiAKDI5nLE3u2fTrd5YF49FVfObZl9DJm3R+8f6yTfLxCg4rwWfz2gWU5qIDpIWC6QVuhEREREXG7cJnSbN2/GnDlzEAwGsWDBAmzfzv0qU0REREQ+2bjccn3iiSewZs0abN68GZdeeil+/etfY+XKlWhpacHMmadW+iL+hQbYvsKXcwdqudsA+SLutikAFIe45fzeEv4n3/5u7nXWXthPt9lN9jeb4A6zeVVHqDgAeC/E9bW0iL/l2l7Blb45J8K/zo5q7nX6vHzJnAN7ufQEi9waLRPlS8mEy7jbdMV+fgsly+JKnsyedZBu89+mvU3FXV/Cl4DoyvO3QBke8LfaEoY73o9O59IoAODmzDVUnHGw9ReyZPpPOETFmaPcVpvHgsnSQA5uueb6uC0+PcQ2pMflUw7Gs0DjskK3adMm3HDDDbjxxhsxb9483Hvvvaivr8eDDz446rmpVAr9/f0j/kRERETk1I35hC6dTuP1119HY2PjiMcbGxuxY8eOUc/fuHEjotHo8F99PZdIKiIiInKmGvNbrp2dncjlcqiqGnlbpqqqCrFYbNTz161bh7Vr1w7/d19fH2bOnIlchlumzKXJW65D/C3XXIK7PZNPOliKTZK3rwYdVN1PcP3ND3GHmZO+5shl7uwgf6stT94qSQ3wtxTZ/loObrmyr5O95Wr8/PvDnptZD38cZDPcraSM4Y/3oSB3/eq3+OMgnp+4X+8BTm+5cn0dyPGvkT03sw6OAxjylmue3GHCUV/Z3Vgc3HI13LXEY/i1rzzRZhbHYkyB79G4lS2xPnKf2xgz6jEACAQCCHzo58vHb7m+/qf/Ol5dG3Ntk92BAuyf7A4UgM8ocuAXE9/kfRPfpJzEnsnuQIH+Gxl3y5j2Qka6d7I7cOq4XbjOHPz3O0fi8TiiBWxXNuYTuoqKCni93lGrcR0dHaNW7U6ktrYWbW1tiEQiJ5wA9vf3o76+Hm1tbSgp4fYElMmj8XM/jaH7aQzdTePnfp80hsYYxONx1NbWFvT/HPMJnd/vx4IFC9DU1ISvfe1rw483NTXhyiuvPGm8x+NBXd3Ji6WWlJToQHYxjZ/7aQzdT2Pobho/9/u4MSxkZe64cbnlunbtWlx77bVYuHAhlixZgt/85jc4cOAAVq1aNR7NiYiIiJzRxmVCd/XVV6Orqws/+clPcPjwYVxwwQXYunUrZs2aNR7NiYiIiJzRxu1HEatXr8bq1avH/P8bCARw5513jvghhbiHxs/9NIbupzF0N42f+43HGFqm0N/FioiIiMiUMm57uYqIiIjIxNCETkRERMTlNKETERERcTlN6ERERERcThM6EREREZebkhO6zZs3Y86cOQgGg1iwYAG2b9/+ic9vbm7GggULEAwGMXfuXPzqV7+aoJ7KiRQyfk899RRWrFiB6dOno6SkBEuWLMFf/vKXCeytnEih5+BxL730EmzbxkUXXTS+HZRPVOj4pVIp3HHHHZg1axYCgQDOOuss/Pa3v52g3sqJFDqGjz32GObPn49wOIyamhp8+9vfRldX1wT1Vj7shRdewOWXX47a2lpYloVnnnnmpDFjMo8xU8zvf/974/P5zEMPPWRaWlrMrbfeaoqKiswHH3xwwufv37/fhMNhc+utt5qWlhbz0EMPGZ/PZ5588skJ7rkYU/j43Xrrrebuu+82r776qtm7d69Zt26d8fl85o033pjgnstxhY7hcb29vWbu3LmmsbHRzJ8/f2I6K6Mw43fFFVeYxYsXm6amJtPa2mpeeeUV89JLL01gr+XDCh3D7du3G4/HY37xi1+Y/fv3m+3bt5vzzz/fXHXVVRPcczHGmK1bt5o77rjD/PGPfzQAzNNPP/2Jzx+recyUm9AtWrTIrFq1asRj5557rrn99ttP+PzbbrvNnHvuuSMeu+mmm8wll1wybn2Uj1fo+J3IeeedZ+66666x7pqcInYMr776avOjH/3I3HnnnZrQTaJCx+9Pf/qTiUajpqurayK6J6eg0DH82c9+ZubOnTvisfvuu8/U1dWNWx/l1JzKhG6s5jFT6pZrOp3G66+/jsbGxhGPNzY2YseOHSeM+fvf/z7q+V/+8pexc+dOZDKZceurjMaM30fl83nE43GUlZWNRxflJNgxfOSRR7Bv3z7ceeed491F+QTM+D333HNYuHAh7rnnHsyYMQNnn302vv/972NoaGgiuiwfwYzh0qVLcfDgQWzduhXGGBw5cgRPPvkkvvrVr05El8WhsZrHjNvWX4zOzk7kcjlUVVWNeLyqqgqxWOyEMbFY7ITPz2az6OzsRE1Nzbj1V0Zixu+jfv7zn2NwcBDf/OY3x6OLchLMGL777ru4/fbbsX37dtj2lLqknHGY8du/fz9efPFFBINBPP300+js7MTq1avR3d2tPLpJwIzh0qVL8dhjj+Hqq69GMplENpvFFVdcgV/+8pcT0WVxaKzmMVNqhe44y7JG/LcxZtRjJ3v+iR6XiVHo+B33+OOPY/369XjiiSdQWVk5Xt2TU3CqY5jL5XDNNdfgrrvuwtlnnz1R3ZOTKOQczOfzsCwLjz32GBYtWoSvfOUr2LRpEx599FGt0k2iQsawpaUF3/3ud/HjH/8Yr7/+Ov785z+jtbUVq1atmoiuyhgYi3nMlPo6XVFRAa/XO+pbSEdHx6jZ63HV1dUnfL5t2ygvLx+3vspozPgd98QTT+CGG27AH/7wB1x22WXj2U35BIWOYTwex86dO7Fr1y7ccsstAI5NEIwxsG0b27Ztw5e+9KUJ6btw52BNTQ1mzJiBaDQ6/Ni8efNgjMHBgwfR0NAwrn2WkZgx3LhxIy699FL84Ac/AABceOGFKCoqwuc//3n89Kc/1Z2qKW6s5jFTaoXO7/djwYIFaGpqGvF4U1MTli5desKYJUuWjHr+tm3bsHDhQvh8vnHrq4zGjB9wbGXu+uuvx5YtW5TzMckKHcOSkhK89dZb2L179/DfqlWrcM4552D37t1YvHjxRHVdwJ2Dl156Kdrb2zEwMDD82N69e+HxeFBXVzeu/ZXRmDFMJBLweEZ+nHu9XgD/WumRqWvM5jEF/YRiAhz/ufbDDz9sWlpazJo1a0xRUZF5//33jTHG3H777ebaa68dfv7xn/t+73vfMy0tLebhhx9W2ZJJVOj4bdmyxdi2bR544AFz+PDh4b/e3t7JeglnvELH8KP0K9fJVej4xeNxU1dXZ77xjW+YPXv2mObmZtPQ0GBuvPHGyXoJZ7xCx/CRRx4xtm2bzZs3m3379pkXX3zRLFy40CxatGiyXsIZLR6Pm127dpldu3YZAGbTpk1m165dw2VnxmseM+UmdMYY88ADD5hZs2YZv99vLr74YtPc3Dz8b9ddd51ZtmzZiOc///zz5jOf+Yzx+/1m9uzZ5sEHH5zgHsuHFTJ+y5YtMwBG/V133XUT33EZVug5+GGa0E2+Qsfv7bffNpdddpkJhUKmrq7OrF271iQSiQnutXxYoWN43333mfPOO8+EQiFTU1NjvvWtb5mDBw9OcK/FGGP+9re/feLn2njNYyxjtB4rIiIi4mZTKodORERERAqnCZ2IiIiIy2lCJyIiIuJymtCJiIiIuJwmdCIiIiIupwmdiIiIiMtpQiciIiLicprQiYiIiLicJnQiIiIiLqcJnYiIiIjLaUInIiIi4nKa0ImIiIi4nCZ0IiIiIi6nCZ2IiIiIy2lCJyIiIuJy9mR34KPy+Tza29sRiURgWdZkd0dERERkwhhjEI/HUVtbC4/n1NfdptyErr29HfX19ZPdDREREZFJ09bWhrq6ulN+/pSb0EUiEQDAsuJvwrZ8BcfHrjmfajdVSoUBAAx547p04VG6zY4jUSpuTn0H3abHMlTc5yr2UXGldoKKA4DD5IBuPcAdPwAwcKiYirPLk3SbwWCWisvl+dXvTNpLxWXT3OXGpLj2AMAbztCxrHyG66/Xn6PbtA4FqbhcgDunAcDKcceQRb5My8ExG+ji4nz8JQjlbw5yga/+B9+onBayyOBFbB2eD52qKTehO36b1bZ8sC1/wfFeP3dh8waoMACAIT9v7CK+UU+Ie52O2iQndMHiwifmABCy+cMz4OPa9IYnfkw8YbpJeIPkhMXBh2OOHBePl5zQefgJnSfMx9LICa8n4GBCF+SOPRN0MKHLumdCx17fvdz3JQCAbbMvlLt2yWnkn6dloWln+lGEiIiIiMtNuRW643LxAVjENxWbvHuVcjC1zRe+kAgAqCqK0212FRVRcQde5vMTjc19m9/v4doM9PDfyENHuLjiwTzdZlkf94087+NXBS3Dxaai/MpVNsCNC5ua4Mnyq0i+BNeoN8W3GejlVk09Kf7Y86S5a0mqIkS3aeW598jXn6bi8n7+mPUd6OQC0/wt++zhGB0rwtAKnYiIiIjLaUInIiIi4nKa0ImIiIi43JTNoWP5ElxeR7Kaz18p3sfldlQF+Ry6c87mksT+2LaEbjNXweWTBFu5JMNUGZ/H5E1weV65IP8dJzGdiy0+5ODXjeRbZA85eG+TXGzPOdz7w5bHAIBAHxcb6OPfn8Ea8tfODiqs5MkruZM2w0e5n4DmbS7v0x7iz5Pc9FIqzjvAlxSCcuhkgmmFTkRERMTlNKETERERcTlN6ERERERc7rTLoQv0cHkdxkFx7iSZO7W7cwbd5kUVh6g4q47fy2ZORQ8V113GbYVwy6deouIA4C9HuS28lpZz25QBwO/3L6DiDrVx27gBgKeUrOnVRxZPBOBJc3lpcz7dRsX9l7qXqTgAeC9ZRcX9NXY23aaV4S4mg0l+TGaVd1NxteE+us2Dg6VU3FCWe39i/dzWegCQGiBrPQ7x27j4updygXzK6MTjU03p/F92pxEAdH8tPsWeis2lksA9zxYcpxU6EREREZfThE5ERETE5TShExEREXG50y6Hzt/D5RRZGa52FAAgzyU9dL9VQTfZcymXz5Y/xOeEtPZxeShWkswxrJ5JxQFA3nBjsqzoH3SbbbVlVNwbPn5/3UiAq5MVKyqh2/T7uDzVldV7qLhvRTqoOAD4o8UVWnvZN5tuM53l6lIuqW+l26wNcLlw54ba6Tb3hbj8xFe6Z1NxneBz6CwvlwRlwnySWMZPtukgL439LKJrPWb5hD9Photlc3iPxXJxTnLoJpJW6ERERERcThM6EREREZc77W65soyPX1M1Pm5e7EnxS8cDWa7EgU1uiQUA6RC5nE/eBmiNc7cwAaA3GaLiBvNkeQMAYS93e29eGb9FkI+8F1DsI+89AKgK9lNx84MHqDiPg++dH6S5tIZ4ik/BsMhTrNQ3RLdZ4++l4iptbiwB4EiWK7dTbHPH3oxpvVQcAPSGuOtBbz+fopLNTPx6CVsK5EzBvj8eLsvkWCxzuKfItrgwEREREZkqNKETERERcTlN6ERERERc7rTLobN7Bqk47wCXYwEA9gCXNJPj07XoPJRMCZ8rGOjgyjHY5G5j8XP4PKYMWTqiyEMmLwCo9HH5SMVervQIAPRlueM25OVz6Mp93DnGvrf9eS43EQA8ZI5hX4I/9nw2tzeR10EC1ME0l2/qcdDmW/E6Ks72cO9PRZDfttD2kMdBnP9csLzsPlN0kwDZpmHLljjYMjPv49rMB/g3KBdm88DpJgHivc0nuXHUCp2IiIiIy2lCJyIiIuJymtCJiIiIuNxpl0Nn/NxLygf5m+TZIu6+fBm3ExIAoP8SLgEvX8TlrwBAZDf3OpPlXJzP66Cv5JZY8TyfO1Xl47Zf+mvPPLrNIpvLS/NZ/HubyHM1EIvIbbheS/FbPnVmIlRcwM8Xngr5uNe5p6+abtMDLufmwto2us3pgQEq7tAQV78unefyYgEgm+fWLqZF+Ly9HvA17CaaIbdKNGSNUYDP2zM5fh0qT9YGtFJ8m1T6Jvm2aoVORERExOU0oRMRERFxOU3oRERERFzutMuhy0XIHKgQn1OUy3I3vLNBPiekn9xr0rL5ulP9c7nXmYly+Ym5AT4H5VMVnVTcv/d8hm6zPthNxbF5cABwKFFKxZUFuFpyABBLcjlQT1oLqbiuTBEVBwAvx2ZTcb1dfJt9ZC2wGLj3FeDziv4a5vM3B8n9pFs6q6i4kI/Pa+zs48Yzm3TwETlIxjrIS2PrpVlkPpuT/chtsvymzaVuAgD85NbFgX4HheiIWo/ZjMEHRFNaoRMRERFxuYImdBs3bsRnP/tZRCIRVFZW4qqrrsI777wz4jnGGKxfvx61tbUIhUJYvnw59uxx8HNOEREREflEBU3ompubcfPNN+Pll19GU1MTstksGhsbMTj4r9s399xzDzZt2oT7778fr732Gqqrq7FixQrE4/Ex77yIiIiIAJYxhk6qOnr0KCorK9Hc3IwvfOELMMagtrYWa9aswQ9/+EMAQCqVQlVVFe6++27cdNNNJ/1/9vf3IxqNYjmuhG0VvlFc4uuLC44BgENX8Dl0ni5uQ7tQjM8/SNRz9/SDR/i77OyWo+x2kV4+tQxprvwYUmV8jmEuxO7dyLdpyPqJFpn3CQCGPISKKri8vXOmH+UaBPBeVwUV19/J59B5+7ncKX+Pgz0qyS1Hs0V8bpAhcwXtOJc77OfKPAIAwh1cX/M2PyYZsnyig62dEermxjMV4U5qw6eBI0umuwf6+etl8UGuRmSotYduM/vuvsJjTAbP41n09fWhpKTklOMc5dD19R07w8rKjm0M3drailgshsbGxuHnBAIBLFu2DDt27Djh/yOVSqG/v3/En4iIiIicOnpCZ4zB2rVr8bnPfQ4XXHABACAWiwEAqqpG/oqpqqpq+N8+auPGjYhGo8N/9fX1bJdEREREzkj0hO6WW27Bm2++iccff3zUv1nWyGVqY8yox45bt24d+vr6hv/a2vitaERERETORFSyx3e+8x0899xzeOGFF1BXVzf8eHX1sb0IY7EYampqhh/v6OgYtWp3XCAQQCDA7Ut6Ink/mfMwwCcDBLq5Nr1pukk6Fy7EpyMhwZWPArn1Jzx82Sn4yN/gRPc5yGusZusR0k0iR9ascrJ3sWWTeTpJ7kA4OsTnsyVTXH5roIRP4MwkuGsJfe0C4B3i4rL8WwsUc3nHJsFdu/I+/v1Jl5D7htItAj6y1KM35SBH7APuQMjP5Wp+piP8mPjIbXLtIQc5x77Tu1JbQa/OGINbbrkFTz31FP76179izpw5I/59zpw5qK6uRlNT0/Bj6XQazc3NWLp06dj0WERERERGKGiF7uabb8aWLVvw7LPPIhKJDOfFRaNRhEIhWJaFNWvWYMOGDWhoaEBDQwM2bNiAcDiMa665ZlxegIiIiMiZrqAJ3YMPPggAWL58+YjHH3nkEVx//fUAgNtuuw1DQ0NYvXo1enp6sHjxYmzbtg2RCFlHQkREREQ+UUETulMpWWdZFtavX4/169ezfZocET5hKzPI3ZcfmsHnMfnKuWJF3T18vqInwtXwiUS4vI5IkM9jOtJz6rV7Pizl4fMzMkNc/bHoNDKZBMDAIDmeGT5nNJ/kYg15uBvD5+lk02Rf2X04AYCsz5aq5s4vALDINr0h/rqX6+NyIn0DZD6bgyFJc5cD5Bykd7Pl5OyEg7y0Aa4gYSpK5v/y223T+87mgnweXI7MU83bXD1LACgKFH7gmlwKaCm8rdM7Q1BERETkDKAJnYiIiIjLaUInIiIi4nIOshLGlz2jBran8ASGkne4rcMO/ydyM0QAuRou1yuymy9AVnIWV2gtHuSL3+Xy3Py/roTbhHFWcTcVBwAr5/6Zins7OYNu84IQVxT7/z3Cl/SxK7hElNnhLrrN3gyXOJMDl7/yZnctFQcAhqzTV1RFFhEDkCfbvKjmEN3mrDB3rgzluDp9ANCR4n7o9h/VNSd/0glkc/z6w1Ccu9ZaHj7PGb1cjmEuyOfQHVlExrL7STso1Och95O2+ZRjuh5hfBafc9xxcXnBMblkUjl0IiIiImciTehEREREXG7K3nLNHjoMWIXfDrBD3NK6HSul4gAgF+aW5S1u5xwAwKGDhS/jAoA/4mBLo8Pcrbb6un1U3Dt9lVQcAFw5jSvHMCfQQbf5yOHPU3GJLH/bqyzA3X8IevgSGeX+ASru93sXUHGpBP/+sFIp/tKYJ28NHhqM0m12DBVTcXMifFpD0sHtWkbeQfkaO8gd79kkfxx4Mmx5Fv4+pkW+R+xnkSfNj0kuyL5Ovk32FjFbYgUAbCJ7w0N+TGuFTkRERMTlNKETERERcTlN6ERERERcbsrm0LHyES6HLvIB3ya7VUuCTxGD3cHlr2Tj/M+vi2dzJWFe65hJxcUTfFmXmw7+FyrO0+MgL4gsV5EPOUjQCHHJL2+WcaUjAMD2cv1NDnBlHOCgXIU3TOZODZJ9BRA4yB1DXW/ypZPY3KCYqaeb9LB5V2T6ZhGf/gtPlnuDjMdB3l6S3AIuyh/vdGos+TLDHXwieJYtz+IghS5Pfvw5yaEraz5QcEw2n8I/iLa0QiciIiLicprQiYiIiLicJnQiIiIiLjdlc+g8oSA8VuF5LJ4YV1cpNY2vATVUyd3Uz/FpOoCHTJrJ8QkIiUThW7EBQG0Nt/VXRZjffqkvyeUjHbFK6DZNP5l/F+Zq5gFAsIjbyq0szO+f05/ichs9PjIRxeYTWAIBLqkozW6FBCDv446DVBnfpjfJndf+XrpJeMldBNPkpTbBp30i+i4XF+rkc8S8GW48vUkHOXQ5rs1EBZdcFq/nc7KHyBzyTIS/HoTbufe25H2+zWxdReEx2SRA7ASoFToRERERl9OETkRERMTlNKETERERcbkpm0OXH0oiT2ww56ks/H41AAR6qDAAQM8iLpnE4+PzM/IDXJ7OvHMP0m3+23SmMg7wj0Eu+WVOqJOKA4AlRVzSzN3BlXSb7L6q6Tx/Gp5VdJSKO5zkc0b3kPmJ/gC5v25FFxUHABUBLg+zJsjlfQLAq+WzqLhUjj8OhjLc9aCqOE63ebC3lIqrKObG5Gg/t18tAHTVcQnLpo9PdC7Zx+WXOal5lieXaAx56OX4UqEwZF+tLJ8HbsiUv8Fqfu0rMb2o4Jhc2gu8VnhbWqETERERcTlN6ERERERcThM6EREREZebsjl03nM+Ba+38LpneT/3ksIdfOJCXzeXv2KmO6ivFeNeZ4t3Bt3m/znrv1Fxnw/vpeIeOrqMigOAALmpYW2Yz516s7OWivtsZeF7/R0X8HB5aXkHGyLGB7nEmW/NI5JCAPyvvjoqDgBscsPR1kEuFxcApgWHqLjpgQG6zaEcdw1qT/B1F8+u4PI3V1S0UHF+i6/X+Leec6m43TH+etkXCnOB5J7QAOAha9h5E1xc3u+gXqOTPaxJKXJf6GQ53ybxUwDkyX2AtUInIiIi4nKa0ImIiIi4nCZ0IiIiIi43ZXPorHQalqfwXILcNC5vITnNwdyW3Pcx9DZfxIfdD/GnX3iKbtNHFkja0n0JFRexk1QcALQly6i4F/Z/im7z3JojVFypj8u5AoAXj86l4jJ5fg/GS2a+T8UNkEWrgl4uHxIA9vZyG0bOjPCFKc8vbqfizgpwxw8AHEhzOX8zQ9ze1wAwkOP2dk7luXy/IjtFxQFAiDyGphXxex4P9nL1GuGgzlo+xOWMmhIyP9HBnsdwEMrKBcj3NsFfLz2ZwucWhixRqxU6EREREZcreEL3wgsv4PLLL0dtbS0sy8Izzzwz4t+NMVi/fj1qa2sRCoWwfPly7NmzZ6z6KyIiIiIfUfCEbnBwEPPnz8f9999/wn+/5557sGnTJtx///147bXXUF1djRUrViAe57eYEREREZGPV3AO3cqVK7Fy5Yn3uzTG4N5778Udd9yBr3/96wCA3/3ud6iqqsKWLVtw0003nXpDlnXsr0B5m7tH3rWQr3FUOqOfiuvzltJtXnTxfiou7+Au+72HV1BxsUSEiptZzOcxvdrO7aeZc7B342AFF7vtIFcjCwC6YlwdMV8xt/8wABzcy+WlwZD5K7aDZBsyF+VQiC88lWjgjoO+YjLnCoCXzGWqD/D75LbH66m43WRcnj1+ALTGuZzaQ7FpdJuhfdxx4GRfcTI9kU5n8zgoJcfu5epg62uqJhwAhI/y1yA7UfiblM3k8QHR1pjm0LW2tiIWi6GxsXH4sUAggGXLlmHHjh0njEmlUujv7x/xJyIiIiKnbkwndLFYDABQVVU14vGqqqrhf/uojRs3IhqNDv/V13Pf3kRERETOVOPyK1frI7dKjTGjHjtu3bp16OvrG/5ra2sbjy6JiIiInLbGtA5ddXU1gGMrdTU1NcOPd3R0jFq1Oy4QCCAQGF3PKLv/A8AqPCHAW/7pgmMAoPRNPn8ls4/LzwjwZejwxj+4HLE3XzmLbjPQxeWwFB3m8g/eGeT3UayJcTWrEtX8d5z+XVx/HWxRidmHuPpa2TB/8AV6uA5ni7laTqF2vhbYUC1Zl7KUvzQeepGrDfj2HP7cTFdyY1I5k0/YSue48cxkubjkEJ/fmktxbfrb+Dbr/ucgF/jyW3SbdiW5B3ERd55kZvA5hulSLuHPF+cvmL43W6k4M8jXCs2nCq+nmjXcdX1MV+jmzJmD6upqNDU1DT+WTqfR3NyMpUuXjmVTIiIiIvJPBX8NHRgYwHvvvTf8362trdi9ezfKysowc+ZMrFmzBhs2bEBDQwMaGhqwYcMGhMNhXHPNNWPacRERERE5puAJ3c6dO/HFL35x+L/Xrl0LALjuuuvw6KOP4rbbbsPQ0BBWr16Nnp4eLF68GNu2bUMkwpWuKFSmhNuOpnQfv71Q56e5pWPD7yaC6ue5W0KD1fxP/3PkXenyN3qpOPMe88Ptf8pyy/JFab6cR4S8h84syTvF30gCYHEL+17D1ThwUBkBgdfJOAdtsqbX1pz8SR8jX8Xd+spGiuk2QWzNCADeBHet9R7ppOIAAH7yiB/kb/dn2w/TsXSbRzomtD1r//t07GScY2TVEtcoeFawfPlyGPPxOVGWZWH9+vVYv369k36JiIiIyCnSXq4iIiIiLqcJnYiIiIjLjWnZkqmg5xwuVyLBp68g7+PKctRd3E63eeTTXE5i5r2JyWX8sEP/Rv60nY0D6L1sio7wGVseMg0zWcZ/rwr2cP31xflskkD3xOb8pafxJVYMuRVgOsKPCbv94FA5n9+anM7FZcP8lkbBTq6/9iA3nja5haAj/JCg6lnuHJvoPDg5fWiFTkRERMTlNKETERERcTlN6ERERERcbsrm0HmnlcLrKTwfziJToNJ1fP2xwAdc3t5XavbQbeZquOSOvXUn3oLtVFQF4lTcE28toOIsD5/fkxvkagMOzOW/4/iqyZpVDvJ0Bsi3KJ/nG83EuRwozxBXeNHK8X3Nl3D1CL1hPk8w18VV2LKifC1M9lyJRPgtjfqiXE6b5eNyy8wAd04DgJXhjiFPysHJedWnqDB/P7d1HADYSe44sHJcnDfFX6M9We7D2so6aDND1sL0Ocip9Rcem80mgb8+W3CcVuhEREREXE4TOhERERGX04RORERExOWmbA6dGUzAWIXnlBTFuPyMeIzf3bLiTe6+/HNLPk23GbK5fJtv1LxBt3lxiNtbdVddHRVXG+6j4gDg1fZZVNwn7Gp3UitmvUPFvdIxm24z5ONyP8uCfO7UQIY7V/a2cfmblu1gUIa4S5zX5usR5oq5vD0T53PETJi77tle/nUWlXE5o8kh7vjJFXHvKwAYMn/T5PkNt3vPJvPSkvw6C5tD7iHfWi+/1S28ZMqoxR8G9PuTJfcxB4A8kVKbS+WBvxYepxU6EREREZfThE5ERETE5TShExEREXG5KZtD5ykvg4eoQzdQw+U8ZEv5G/O9Z3FvYy2ZBwcAxWTu1L93XEi3ua+kkoo72FtKxbX3Rak4AKiMcDXzYn0ldJu9mTAV1zPIJ2jEDldQca0O8tLY2lwmyp1jubyDHDqLi83vL6KbDA5y70/ewdXYm+aue71Hy/lGSb449/6E+/k2PfzWxbRQJ5ewZRwss9hDXJveDHee2An+jfX1cLUePX0OEvcGBqkwU1FKN5mLFH59z2aT2Eu0pRU6EREREZfThE5ERETE5TShExEREXG5KZtDZ0qLYbyFF3AJdXE5BIHtfL0hNk+n7fmZdJO+ATKOSyEAABxOz6HiPKVczoyTvvbYpVybfCkw7MIFVFwRv20oQuQZ7E05aLOLy5sJ9HDnZqaYv0xlg9x3Vid1pzJk+h1bIwsA8uRxa5P5fgCfl8a+t0PVXBwAeMituiNc6U0AQMkfXqfiTJbPrXYT9nB3cJrwjnRMbHuGOwa0QiciIiLicprQiYiIiLicJnQiIiIiLjdlc+hykSAsO1hwXM853Bw1Ve7gzjyZhmICfA0fc5gbuiRXtgwAED5M1h8j0xMDffyYZMJcX7PsYAKY9i6XqDNYzSfusXlMwS6+7qIny43L0HRuD0/2+AH4fR+d5LMVH+YGJRvkj710hLvuOal9N9HJTE7yPi3yPLFTDuo1hgr//AKAXPzMyKGTsacVOhERERGX04RORERExOU0oRMRERFxuSmbQ2e98Q4sq/DcoszXFnINTiMLFQHIp7gkny9cwOzWdswblXVU3AWVMbrNI4liKu7K2jepuCcOLKDiACBsc8lTh7v5/WOLryI3m8zyp2HswDQqzlPM59Dlc9z3QI/NJUFVTCOLLgKYFuL2fexM8Hu5HjnC7QfsDfFjUlrCvc55pV10m//RwRWGKw0PUXFH+7nrDwCkOrjid9kQn8DZ2/BpKs5JXqOHPITY/WPZ9pxg8yEBB7mxTlLsidhcKgnc+2zBcVqhExEREXG5cZvQbd68GXPmzEEwGMSCBQuwffv28WpKRERE5Iw2Lrdcn3jiCaxZswabN2/GpZdeil//+tdYuXIlWlpaMHPmqW135S0tgddTeJkDfx/30/+Ur/Btxo7zeLmftoe8/M/TDflr+hXle+g2/6c1j4qbG+C2TUnn+NsdiTRXCsQit3EDgFSGO50Saa6cBwDYpdxtzJJifr+xkI87btuPlFJx5WF+D7gkeTu7wkGbZ597lIpbFH2fbvPVvtlUXIS8DQ4AS2a8T8VV+bnUhL1FVVQcAOwNcPWa+rr5W+95m7tPlx90sP8gWwqLTBsyHv56aWXI9SS+ST7W8CWFmK1B80PcOI7LCt2mTZtwww034MYbb8S8efNw7733or6+Hg8++OCo56ZSKfT394/4ExEREZFTN+YTunQ6jddffx2NjY0jHm9sbMSOHTtGPX/jxo2IRqPDf/X19WPdJREREZHT2pjfcu3s7EQul0NV1cjl8aqqKsRio39huW7dOqxdu3b4v/v6+jBz5kxk89yvTnMp7lZSPsmv47LLzukB/pe1uQR3q2RogP9ZUmaQ628izi0fs68RAHLkLzFzKf4nVDmL628uzR97+RQ3njkP/95mbe6Wa36IOzezgw76miVvXXj54yCT5c6TpHfiz82018Gv+8ldVVJ+7vhhXyPAX0vyQw62KfGSt1zJ223HgnXLdVxiJ/qWa/LYtdIUmFs1bmVLLGvkG2CMGfUYAAQCAQQC/8pfO37L9fnu/49r+Gdc2GT43SS0+V1H0S9TUX+k2/sPOlJOHwcmuwMThD9PROR0FI/HEY2eeimtMZ/QVVRUwOv1jlqN6+joGLVqdyK1tbVoa2tDJBI54QSwv78f9fX1aGtrQ0kJV+9JJo/Gz/00hu6nMXQ3jZ/7fdIYGmMQj8dRW1tb0P9zzCd0fr8fCxYsQFNTE772ta8NP97U1IQrr7zypPEejwd1dScvmltSUqID2cU0fu6nMXQ/jaG7afzc7+PGsJCVuePG5Zbr2rVrce2112LhwoVYsmQJfvOb3+DAgQNYtWrVeDQnIiIickYblwnd1Vdfja6uLvzkJz/B4cOHccEFF2Dr1q2YNWvWeDQnIiIickYbtx9FrF69GqtXrx7z/28gEMCdd9454ocU4h4aP/fTGLqfxtDdNH7uNx5jaJlCfxcrIiIiIlPKuO3lKiIiIiITQxM6EREREZfThE5ERETE5TShExEREXE5TehEREREXG5KTug2b96MOXPmIBgMYsGCBdi+ffsnPr+5uRkLFixAMBjE3Llz8atf/WqCeionUsj4PfXUU1ixYgWmT5+OkpISLFmyBH/5y18msLdyIoWeg8e99NJLsG0bF1100fh2UD5RoeOXSqVwxx13YNasWQgEAjjrrLPw29/+doJ6KydS6Bg+9thjmD9/PsLhMGpqavDtb38bXV1dE9Rb+bAXXngBl19+OWpra2FZFp555pmTxozJPMZMMb///e+Nz+czDz30kGlpaTG33nqrKSoqMh988MEJn79//34TDofNrbfealpaWsxDDz1kfD6fefLJJye452JM4eN36623mrvvvtu8+uqrZu/evWbdunXG5/OZN954Y4J7LscVOobH9fb2mrlz55rGxkYzf/78iemsjMKM3xVXXGEWL15smpqaTGtrq3nllVfMSy+9NIG9lg8rdAy3b99uPB6P+cUvfmH2799vtm/fbs4//3xz1VVXTXDPxRhjtm7dau644w7zxz/+0QAwTz/99Cc+f6zmMVNuQrdo0SKzatWqEY+de+655vbbbz/h82+77TZz7rnnjnjspptuMpdccsm49VE+XqHjdyLnnXeeueuuu8a6a3KK2DG8+uqrzY9+9CNz5513akI3iQodvz/96U8mGo2arq6uieienIJCx/BnP/uZmTt37ojH7rvvPlNXVzdufZRTcyoTurGax0ypW67pdBqvv/46GhsbRzze2NiIHTt2nDDm73//+6jnf/nLX8bOnTuRyWTGra8yGjN+H5XP5xGPx1FWVjYeXZSTYMfwkUcewb59+3DnnXeOdxflEzDj99xzz2HhwoW45557MGPGDJx99tn4/ve/j6GhoYnosnwEM4ZLly7FwYMHsXXrVhhjcOTIETz55JP46le/OhFdFofGah4zblt/MTo7O5HL5VBVVTXi8aqqKsRisRPGxGKxEz4/m82is7MTNTU149ZfGYkZv4/6+c9/jsHBQXzzm98cjy7KSTBj+O677+L222/H9u3bYdtT6pJyxmHGb//+/XjxxRcRDAbx9NNPo7OzE6tXr0Z3d7fy6CYBM4ZLly7FY489hquvvhrJZBLZbBZXXHEFfvnLX05El8WhsZrHTKkVuuMsyxrx38aYUY+d7PknelwmRqHjd9zjjz+O9evX44knnkBlZeV4dU9OwamOYS6XwzXXXIO77roLZ5999kR1T06ikHMwn8/Dsiw89thjWLRoEb7yla9g06ZNePTRR7VKN4kKGcOWlhZ897vfxY9//GO8/vrr+POf/4zW1lasWrVqIroqY2As5jFT6ut0RUUFvF7vqG8hHR0do2avx1VXV5/w+bZto7y8fNz6KqMx43fcE088gRtuuAF/+MMfcNlll41nN+UTFDqG8XgcO3fuxK5du3DLLbcAODZBMMbAtm1s27YNX/rSlyak78KdgzU1NZgxYwai0ejwY/PmzYMxBgcPHkRDQ8O49llGYsZw48aNuPTSS/GDH/wAAHDhhReiqKgIn//85/HTn/5Ud6qmuLGax0ypFTq/348FCxagqalpxONNTU1YunTpCWOWLFky6vnbtm3DwoUL4fP5xq2vMhozfsCxlbnrr78eW7ZsUc7HJCt0DEtKSvDWW29h9+7dw3+rVq3COeecg927d2Px4sUT1XUBdw5eeumlaG9vx8DAwPBje/fuhcfjQV1d3bj2V0ZjxjCRSMDjGflx7vV6AfxrpUemrjGbxxT0E4oJcPzn2g8//LBpaWkxa9asMUVFReb99983xhhz++23m2uvvXb4+cd/7vu9733PtLS0mIcfflhlSyZRoeO3ZcsWY9u2eeCBB8zhw4eH/3p7eyfrJZzxCh3Dj9KvXCdXoeMXj8dNXV2d+cY3vmH27NljmpubTUNDg7nxxhsn6yWc8Qodw0ceecTYtm02b95s9u3bZ1588UWzcOFCs2jRosl6CWe0eDxudu3aZXbt2mUAmE2bNpldu3YNl50Zr3nMlJvQGWPMAw88YGbNmmX8fr+5+OKLTXNz8/C/XXfddWbZsmUjnv/888+bz3zmM8bv95vZs2ebBx98cIJ7LB9WyPgtW7bMABj1d9111018x2VYoefgh2lCN/kKHb+3337bXHbZZSYUCpm6ujqzdu1ak0gkJrjX8mGFjuF9991nzjvvPBMKhUxNTY351re+ZQ4ePDjBvRZjjPnb3/72iZ9r4zWPsYzReqyIiIiIm02pHDoRERERKZwmdCIiIiIupwmdiIiIiMtpQiciIiLicprQiYiIiLicJnQiIiIiLqcJnYiIiIjLaUInIiIi4nKa0ImIiIi4nCZ0IiIiIi6nCZ2IiIiIy/3/z7YDxXK5kS8AAAAASUVORK5CYII=", + "text/plain": [ + "
" + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], "source": [ "max_target_examples = 3\n", "target_count = 0\n", @@ -207,10 +271,18 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 11, "id": "6fafe720-6a04-4ac0-bf45-8bd8456b5f55", "metadata": {}, - "outputs": [], + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "{0: 400, 2: 1400, 1: 200}\n" + ] + } + ], "source": [ "## look at the label breakdown in the training set\n", "print(get_dataset.count_labels(ds_train))\n", @@ -227,10 +299,25 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 12, "id": "40d88172-df6d-422b-a9ec-a47da6958ec6", "metadata": {}, - "outputs": [], + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "Loading pretrained model from trained_models/str_ww_ref_model.h5\n" + ] + }, + { + "name": "stderr", + "output_type": "stream", + "text": [ + "WARNING:absl:At this time, the v2.11+ optimizer `tf.keras.optimizers.Adam` runs slowly on M1/M2 Macs, please use the legacy Keras optimizer instead, located at `tf.keras.optimizers.legacy.Adam`.\n" + ] + } + ], "source": [ "if load_pretrained_model:\n", " print(f\"Loading pretrained model from {pretrained_model_path}\")\n", @@ -243,17 +330,87 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 13, "id": "fa6d1855-1cc3-4487-a694-525f3349389f", "metadata": {}, - "outputs": [], + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "Model: \"model\"\n", + "_________________________________________________________________\n", + " Layer (type) Output Shape Param # \n", + "=================================================================\n", + " input_1 (InputLayer) [(None, 30, 1, 40)] 0 \n", + " \n", + " depthwise_conv2d (Depthwis (None, 28, 1, 40) 120 \n", + " eConv2D) \n", + " \n", + " conv2d (Conv2D) (None, 28, 1, 128) 5120 \n", + " \n", + " batch_normalization (Batch (None, 28, 1, 128) 512 \n", + " Normalization) \n", + " \n", + " activation (Activation) (None, 28, 1, 128) 0 \n", + " \n", + " dropout (Dropout) (None, 28, 1, 128) 0 \n", + " \n", + " depthwise_conv2d_1 (Depthw (None, 24, 1, 128) 640 \n", + " iseConv2D) \n", + " \n", + " conv2d_1 (Conv2D) (None, 24, 1, 128) 16384 \n", + " \n", + " batch_normalization_1 (Bat (None, 24, 1, 128) 512 \n", + " chNormalization) \n", + " \n", + " activation_1 (Activation) (None, 24, 1, 128) 0 \n", + " \n", + " dropout_1 (Dropout) (None, 24, 1, 128) 0 \n", + " \n", + " depthwise_conv2d_2 (Depthw (None, 15, 1, 128) 1280 \n", + " iseConv2D) \n", + " \n", + " conv2d_2 (Conv2D) (None, 15, 1, 128) 16384 \n", + " \n", + " batch_normalization_2 (Bat (None, 15, 1, 128) 512 \n", + " chNormalization) \n", + " \n", + " activation_2 (Activation) (None, 15, 1, 128) 0 \n", + " \n", + " dropout_2 (Dropout) (None, 15, 1, 128) 0 \n", + " \n", + " depthwise_conv2d_3 (Depthw (None, 1, 1, 128) 1920 \n", + " iseConv2D) \n", + " \n", + " conv2d_3 (Conv2D) (None, 1, 1, 32) 4096 \n", + " \n", + " batch_normalization_3 (Bat (None, 1, 1, 32) 128 \n", + " chNormalization) \n", + " \n", + " activation_3 (Activation) (None, 1, 1, 32) 0 \n", + " \n", + " dropout_3 (Dropout) (None, 1, 1, 32) 0 \n", + " \n", + " flatten (Flatten) (None, 32) 0 \n", + " \n", + " dense (Dense) (None, 3) 99 \n", + " \n", + "=================================================================\n", + "Total params: 47707 (186.36 KB)\n", + "Trainable params: 46875 (183.11 KB)\n", + "Non-trainable params: 832 (3.25 KB)\n", + "_________________________________________________________________\n" + ] + } + ], "source": [ "model.summary()" ] }, { "cell_type": "code", - "execution_count": null, + "execution_count": 14, "id": "1fae82dd-3138-45b0-82d9-51a53b617b24", "metadata": {}, "outputs": [], @@ -266,7 +423,7 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 15, "id": "25d2f3c8-32cc-4f9e-a876-b1345f1849f9", "metadata": {}, "outputs": [], @@ -277,7 +434,7 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 16, "id": "38404fa1-9f9f-4c56-a22e-bfa99cdbcc1f", "metadata": {}, "outputs": [], @@ -297,10 +454,48 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 17, "id": "b3af70d4-dd90-4cc1-96b7-86d79f0f1d02", "metadata": {}, - "outputs": [], + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "Eval on training set\n", + " 1/20 [>.............................] - ETA: 6s - loss: 0.1398 - categorical_accuracy: 0.9700 - precision: 1.0000 - recall: 0.7647" + ] + }, + { + "name": "stderr", + "output_type": "stream", + "text": [ + "2025-05-19 11:33:12.153231: I tensorflow/core/grappler/optimizers/custom_graph_optimizer_registry.cc:117] Plugin optimizer for device_type GPU is enabled.\n" + ] + }, + { + "name": "stdout", + "output_type": "stream", + "text": [ + "20/20 [==============================] - 1s 10ms/step - loss: 0.0997 - categorical_accuracy: 0.9600 - precision: 0.9844 - recall: 0.7875\n", + "Eval on validation set\n", + "140/140 [==============================] - 32s 222ms/step - loss: 0.3406 - categorical_accuracy: 0.9384 - precision: 0.9872 - recall: 0.6874 \n" + ] + }, + { + "data": { + "text/plain": [ + "[0.3405939042568207,\n", + " 0.9384120106697083,\n", + " 0.9871597290039062,\n", + " 0.6874105930328369]" + ] + }, + "execution_count": 17, + "metadata": {}, + "output_type": "execute_result" + } + ], "source": [ "## This cell can be slow with QAT enabled\n", "print(f\"Eval on training set\")\n", @@ -311,7 +506,7 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 18, "id": "17cd9778-5bd9-4e25-ae50-18a93efe06f7", "metadata": {}, "outputs": [], @@ -341,10 +536,29 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 19, "id": "a2407081-1022-4147-b6d3-d489a33f0357", "metadata": {}, - "outputs": [], + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "20/20 [==============================] - 0s 2ms/step\n", + "Accuracy: 96.0%\n" + ] + }, + { + "data": { + "image/png": "iVBORw0KGgoAAAANSUhEUgAAAg4AAAINCAYAAABWL/eXAAAAOnRFWHRTb2Z0d2FyZQBNYXRwbG90bGliIHZlcnNpb24zLjEwLjAsIGh0dHBzOi8vbWF0cGxvdGxpYi5vcmcvlHJYcgAAAAlwSFlzAAAPYQAAD2EBqD+naQAATaFJREFUeJzt3Xt8z3X/x/HnNzuY2cbGNhNyvuSQU85CRF1JUihyiJSE5hB2ySHXxaLQQSddOaQkhVI/OeRyTMRGjglNwtYcZozZ8fP7w9X36mvi+1n77jP7PO7dPrebvT/vz/v7+u7b7OX1fn/eH4dhGIYAAADccIvVAQAAgJsHiQMAAHAbiQMAAHAbiQMAAHAbiQMAAHAbiQMAAHAbiQMAAHAbiQMAAHAbiQMAAHCbl9UBeELxYhWtDgH56HJmutUhIB+lntxkdQjIR96lKnl0/IzTP3tsbE/HbhUqDgAAwG2FsuIAAIBbsrOsjuCmQ+IAALAvI9vqCG46TFUAAAC3UXEAANhXNhUHs6g4AAAAt1FxAADYlsEaB9OoOAAAALdRcQAA2BdrHEyj4gAAANxGxQEAYF+scTCNxAEAYF/sHGkaUxUAAMBtVBwAAPbFVIVpVBwAAIDbqDgAAOyL2zFNo+IAAADcRsUBAGBbbDltHhUHAADgNioOAAD7Yo2DaSQOAAD7YqrCNKYqAACA26g4AADsiy2nTaPiAAAA3EbFAQBgX6xxMI2KAwAAcBsVBwCAfXE7pmlUHAAAgNuoOAAA7Is1DqaROAAA7IupCtOYqgAAAG6j4gAAsC3DYAMos6g4AAAAt1FxAADYF4sjTaPiAAAA3EbFAQBgX9xVYRoVBwAA4DYqDgAA+2KNg2kkDgAA+8rmdkyzmKoAAABuo+IAALAvpipMo+IAAADcRsUBAGBf3I5pGhUHAADgNioOAAD7Yo2DaVQcAACA26g4AADsizUOppE4AADsi8TBNKYqAACA20gcAAC2ZRhZHjvM2Lhxox544AFFRETI4XDo888/d57LyMjQ6NGjVbt2bfn7+ysiIkK9e/fWyZMnXcZIS0vTkCFDVKpUKfn7+6tTp046fvy4S5+kpCT16tVLQUFBCgoKUq9evXTu3DlTsZI4AABgsYsXL+qOO+7QrFmzcpy7dOmSYmNjNW7cOMXGxmrp0qX66aef1KlTJ5d+kZGRWrZsmRYtWqTNmzcrJSVFHTt2VFbW/5KYHj16aNeuXVq5cqVWrlypXbt2qVevXqZidRiGYeTubRZcxYtVtDoE5KPLmelWh4B8lHpyk9UhIB95l6rk0fFT18/x2Nh+rfvl6jqHw6Fly5apc+fOf9pn+/btatSokX755ReVL19eycnJKl26tBYsWKDu3btLkk6ePKly5cppxYoV6tChgw4cOKDbb79dW7duVePGjSVJW7duVdOmTfXjjz+qevXqbsVHxQEAAA9IS0vT+fPnXY60tLQ8GTs5OVkOh0MlSpSQJMXExCgjI0Pt27d39omIiFCtWrW0ZcsWSdJ3332noKAgZ9IgSU2aNFFQUJCzjztIHAAA9mVke+yIjo52riX4/YiOjv7LIV++fFljxoxRjx49FBgYKElKSEiQj4+PSpYs6dI3LCxMCQkJzj6hoaE5xgsNDXX2cQe3YwIA4AFRUVEaPny4S5uvr+9fGjMjI0OPPvqosrOz9dZbb92wv2EYcjgczq//+Oc/63MjJA4AAPvy4D4Ovr6+fzlR+KOMjAx169ZNcXFx+s9//uOsNkhSeHi40tPTlZSU5FJ1SExMVLNmzZx9fvvttxzjnjp1SmFhYW7HwVQFAMC+PDhVkZd+TxoOHTqkb775RiEhIS7nGzRoIG9vb61Zs8bZFh8fr7179zoTh6ZNmyo5OVnff/+9s8+2bduUnJzs7OMOKg4AAFgsJSVFhw8fdn4dFxenXbt2KTg4WBEREXrkkUcUGxurr776SllZWc41CcHBwfLx8VFQUJD69++vESNGKCQkRMHBwRo5cqRq166tdu3aSZJq1Kihe++9VwMGDNC7774rSXrqqafUsWNHt++okEgcAAB2VkC2nN6xY4fatGnj/Pr3tRF9+vTRxIkTtXz5cklS3bp1Xa5bt26dWrduLUmaOXOmvLy81K1bN6Wmpqpt27aaN2+eihQp4uz/0UcfaejQoc67Lzp16nTNvSOuh30ccNNjHwd7YR8He/H4Pg6rb7zAMLf82g/y2NhWsnSNQ2Zmpry8vLR3714rwwAA2NVNssahILE0cfDy8lKFChVctsMEAAAFl+V3VbzwwguKiorS2bNnrQ4FAGA32dmeOwopyxdHvv766zp8+LAiIiJUoUIF+fv7u5yPjY21KDIAAHA1yxOH6z3EAwAAjyrElQFPsTxxmDBhgtUhAADsqhAvYvQUy9c4SNK5c+f073//22WtQ2xsrE6cOGFxZAAA4I8srzjs3r1b7dq1U1BQkI4ePaoBAwYoODhYy5Yt0y+//KIPPvjA6hABAIUVUxWmWV5xGD58uPr27atDhw6paNGizvb77rtPGzdutDAyAABwNcsrDtu3b3fumf1HZcuWNfV8cAAATGONg2mWVxyKFi2q8+fP52g/ePCgSpcubUFEN48RI59RyqU4TZ02zqX9H2Of06EjW3XqzAF9vfJj1ahR1aII4SkDn+6jQwe/U8r5I9q29Wu1aN7I6pBwAzt27dGzoyaoTaeeqtX8Pq3duMXl/Jvvf6gHHhugO9t2VrN7u+rJ56K0e9+POcbZtfeA+g0ZozvbdlbTDo+o7+BRupyW5jyffP6Cxkx6WU3aP6wm7R/WmEkv6/yFFI+/P9iH5YnDgw8+qEmTJikjI0OS5HA4dOzYMY0ZM0YPP/ywxdEVXPUb1NET/R7Tnt0HXNqHDX9ag4f014jhE9Sq5YP67bdTWv7VAhUv7v8nI+Fm07VrJ82YPlHRL72uho06aPPm7/XVlx+qXLkIq0PDdaSmXlb1KpX0j+HXfn7BbeXK6h/DB2npB2/rg7deUUR4mJ4aNlZnk845++zae0ADh7+gZo3q6+P3XtOif7+mHg8/oFscDmef0S9O08FDP+udGf/SOzP+pYOHflbUP1/29Nu7ebEBlGmWJw6vvPKKTp06pdDQUKWmpqpVq1aqUqWKAgICNHnyZKvDK5D8/Yvp/TmvavCzUTp3Ltnl3LOD++nlaW9q+RertH//T3pqwEj5+fmpW/dOFkWLvDbsuQGaM3eR5sz9WD/+eFgjRk7Qr8dPauDTva0ODdfRsumdGvpUH93Tuvk1z9/fvo2a3llP5cqWUZVKFTRq6AClXLykn47EOftMe+1d9XzkQT3Zq5uqVKqgCuXKqn2blvLx8ZEkHTl6TJu37tCLY55T3Vo1VLdWDU0cPVQbvv1ecb8cz5f3icLP8sQhMDBQmzdv1pIlS/TSSy9p8ODBWrFihTZs2JBjF0lcMWPmJK1a+R+tX/etS/ttt5VTeHio1q7939MD09PTtXnzNjVu3CC/w4QHeHt7q379OlrzzQaX9jVrNqhpk4YWRYW8lpGRoU+/+FoBxf1VvcqVp0OeSTqn3fsPKrhkkHo+PVx3dXxMfZ99XrE//O8hgT/sPaCA4v6qU/NvzrY7atVQQHF/7dq7P9/fx02Bh1yZZvniyN/dfffduvvuu60Oo8B75JGOqlu3pu5q+WCOc2FhV9aEJCaedmk/lXha5cqVzZf44FmlSgXLy8tLib+5fsaJiacVFh5qUVTIK+u/3abnJ7yky5fTVDokWLNfnaySJYIkScdPxEuS3przkUYOflJ/q1pJy79eq/7PRenzBe+oQrmyOn0mScElS+QYN7hkCZ0+k5SfbwWFWIFIHNauXau1a9cqMTFR2VfNC82ZM+e616alpSntDwuDJMkwDDn+MOdXWJQtW0bTXp6gTp16Ky0t/U/7GYbh2uBwyJBx7c64KV39GTscjpyfO246jerfoSXz3lTSuWR99uVKjRwXrYXvvaqQkiWU/d/Pt+uDf9dD97eXJNWoVkVbY3Zp6VerNeyZJyRJ1/qbr7D+nZgnCvFaBE+xfKrixRdfVPv27bV27VqdPn1aSUlJLseNREdHKygoyOXIyDzn+cAtUK9+LYWGldLmb5fr3PlDOnf+kFre1UTPDOqrc+cPOSsNv1cefle6dEiOf6Hi5nT69FllZmYqLPxan/Epi6JCXinmV1Tlb43QHbVq6J9Rw1SkSBEt/XKVJKl0SLAkqXLF8i7XVKpQXgm/JUqSSoWU1Jk/LKb8XdK5ZIUEl/Bo7DctFkeaZnnF4Z133tG8efPUq1evXF0fFRWl4cOHu7SVCauTF6EVOOvXbVGjhh1c2t5+d5p+OvizZs54R3Fxx5SQkKi7726p3T9cmc/09vZWixaNNX7cS1aEjDyWkZGh2Njdatf2Ln3xxUpne7t2d+nL//6CQeFhGIbS/3vHWdkyYQotFaKjVy1y/OXX42rR5E5JV9YzXEi5qD37D6r27dUlSbv3/agLKRdVt9bt+Rs8Ci3LE4f09HQ1a9Ys19f7+vrK19fXpa2wluRSUi5q//6fXNouXUzV2bNJzvY3Z83RyOcH6ciROB05fFQjnx+k1NRULf5kuRUhwwNmvvae5s99TTExP2jrthgN6P+4ypcrq3dnL7A6NFzHpUupOnb8pPPrEyd/048/HVFQYICCggI1e/4itWnRWKVLBetc8gUtWvqVfjt1Wh3atJR05e+1J3o8rDff/1DVq1bU36pW1hcrvlHcL8c1419jJUmVbyuvFk0aasLU1zTh+SGSpInTXler5o1UscKt+f+mbwZM8ZlmeeLw5JNPauHChRo3btyNO+OGZs54V35+RTXz1X+qRIkg7di+Sw8+0FspKRetDg155NNPlyskuKReGDtMZcqEau++g3qgUy8dO8ZD4QqyvT8eUr8ho51fT3tjtiTpwfvaafzzQxT3y69a/vU3SkpOVonAQNWqUU3z33pZVSpVcF7Tq/tDSkvP0NTXZ+v8+QuqVqWS3nt1ssrf+r89PKZOGKUpM9/WU8OuJBOtWzTR2D/ZOwLIDYdhwYqqP04tZGdna/78+apTp47q1Kkjb29vl74zZswwPX7xYhX/coy4eVzO/POFoih8Uk9uunEnFBrepSp5dPzUjyd4bGy/x1702NhWsqTisHPnTpev69atK0nau3fvNXoDAICCwpLEYd26dVa8LAAArgrx3Q+eYvntmP369dOFCxdytF+8eFH9+vWzICIAAPBnLE8c5s+fr9TU1Bztqamp+uCDDyyICABgG2w5bZpld1WcP39ehmHIMAxduHBBRYsWdZ7LysrSihUrFBrKFroAAA9iqsI0yxKHEiVKyOFwyOFwqFq1ajnOOxwOvfhi4VyRCgDAzcqyxGHdunUyDEN33323lixZouDgYOc5Hx8fVahQQREREdcZAQCAv4gNoEyzLHFo1aqVJCkuLk6BgYGaM2eODhw4IIfDodtvv1233872qAAAFDSWL448deqUqlatqpkzZ+rs2bM6ffq0ZsyYocqVKys2Ntbq8AAAhRkPuTLN8i2nhw0bpgceeEDvvfeevLyuhJOZmaknn3xSkZGR2rhxo8URAgCA31meOOzYscMlaZAkLy8vjRo1Sg0bNrQwMgBAoVeIKwOeYvlURWBgoI4dO5aj/ddff1VAQIAFEQEAgD9jecWhe/fu6t+/v1555RU1a9ZMDodDmzdv1vPPP6/HHnvM6vAAAIVZId6oyVMsTxxeeeUVORwO9e7dW5mZmZIkb29vPfPMM3rppZcsjg4AUJgZ2dyOaZYlj9W+lkuXLunIkSMyDENVqlRRsWLFcj0Wj9W2Fx6rbS88VttePP1Y7Uuzh3ls7GJPzfTY2FayvOLwu2LFiql27dpWhwEAsBMWR5pm+eJIAABw8ygwFQcAAPIdiyNNo+IAAADcRsUBAGBf3FVhGhUHAADgNioOAAD74q4K00gcAAD2ReJgGlMVAADAbVQcAAD2VTA2T76pUHEAAABuo+IAALAv1jiYRsUBAAC4jYoDAMC+2ADKNCoOAADAbVQcAAD2xUOuTCNxAADYF1MVpjFVAQAA3EbFAQBgWwa3Y5pGxQEAALiNigMAwL5Y42AaFQcAACy2ceNGPfDAA4qIiJDD4dDnn3/uct4wDE2cOFERERHy8/NT69attW/fPpc+aWlpGjJkiEqVKiV/f3916tRJx48fd+mTlJSkXr16KSgoSEFBQerVq5fOnTtnKlYSBwCAfRnZnjtMuHjxou644w7NmjXrmuenTZumGTNmaNasWdq+fbvCw8N1zz336MKFC84+kZGRWrZsmRYtWqTNmzcrJSVFHTt2VFZWlrNPjx49tGvXLq1cuVIrV67Url271KtXL1OxOgyj8D0arHixilaHgHx0OTPd6hCQj1JPbrI6BOQj71KVPDr+xX897rGx/V/4MFfXORwOLVu2TJ07d5Z0pdoQERGhyMhIjR49WtKV6kJYWJimTp2qp59+WsnJySpdurQWLFig7t27S5JOnjypcuXKacWKFerQoYMOHDig22+/XVu3blXjxo0lSVu3blXTpk31448/qnr16m7FR8UBAGBf2YbHjrS0NJ0/f97lSEtLMx1iXFycEhIS1L59e2ebr6+vWrVqpS1btkiSYmJilJGR4dInIiJCtWrVcvb57rvvFBQU5EwaJKlJkyYKCgpy9nEHiQMAwL6ysz12REdHO9cS/H5ER0ebDjEhIUGSFBYW5tIeFhbmPJeQkCAfHx+VLFnyun1CQ0NzjB8aGurs4w7uqgAAwAOioqI0fPhwlzZfX99cj+dwOFy+NgwjR9vVru5zrf7ujPNHJA4AAPvy4O2Yvr6+fylR+F14eLikKxWDMmXKONsTExOdVYjw8HClp6crKSnJpeqQmJioZs2aOfv89ttvOcY/depUjmrG9TBVAQBAAVaxYkWFh4drzZo1zrb09HRt2LDBmRQ0aNBA3t7eLn3i4+O1d+9eZ5+mTZsqOTlZ33//vbPPtm3blJyc7OzjDioOAAD7KiBPx0xJSdHhw4edX8fFxWnXrl0KDg5W+fLlFRkZqSlTpqhq1aqqWrWqpkyZomLFiqlHjx6SpKCgIPXv318jRoxQSEiIgoODNXLkSNWuXVvt2rWTJNWoUUP33nuvBgwYoHfffVeS9NRTT6ljx45u31EhkTgAAGC5HTt2qE2bNs6vf18b0adPH82bN0+jRo1SamqqBg0apKSkJDVu3FirV69WQECA85qZM2fKy8tL3bp1U2pqqtq2bat58+apSJEizj4fffSRhg4d6rz7olOnTn+6d8SfYR8H3PTYx8Fe2MfBXjy+j8PYrh4b23/ypx4b20qscQAAAG5jqgIAYFs8Vts8EgcAgH3xdEzTmKoAAABuo+IAALAvKg6mUXEAAABuo+IAALCvArIB1M2EigMAAHAbFQcAgH2xxsE0Kg4AAMBtVBwAALZlUHEwjcQBAGBfJA6mMVUBAADcRsUBAGBfPKvCNCoOAADAbVQcAAD2xRoH06g4AAAAt1FxAADYFxUH06g4AAAAt1FxAADYlmFQcTCLigMAAHAbFQcAgH2xxsE0EgcAgH2ROJjGVAUAAHAbFQcAgG3xdEzzCmXicDkz3eoQkI8alqpqdQjIR34RLa0OAfkoM/2E1SHgKoUycQAAwC1UHExjjQMAAHAbFQcAgH3xVG3TqDgAAAC3UXEAANgWd1WYR+IAALAvEgfTmKoAAABuo+IAALAvFkeaRsUBAAC4jYoDAMC2WBxpHhUHAADgNioOAAD7Yo2DaVQcAACA26g4AABsizUO5pE4AADsi6kK05iqAAAAbqPiAACwLYOKg2lUHAAAgNuoOAAA7IuKg2lUHAAAgNuoOAAAbIs1DuZRcQAAAG6j4gAAsC8qDqaROAAAbIupCvOYqgAAAG6j4gAAsC0qDuZRcQAAAG6j4gAAsC0qDuZRcQAAAG6j4gAAsC/DYXUENx0qDgAAwG0kDgAA2zKyPXe4KzMzUy+88IIqVqwoPz8/VapUSZMmTVJ29v8GMQxDEydOVEREhPz8/NS6dWvt27fPZZy0tDQNGTJEpUqVkr+/vzp16qTjx4/n1bfKicQBAGBbRrbDY4e7pk6dqnfeeUezZs3SgQMHNG3aNL388st64403nH2mTZumGTNmaNasWdq+fbvCw8N1zz336MKFC84+kZGRWrZsmRYtWqTNmzcrJSVFHTt2VFZWVp5+zxyGYRh5OmIB4OVT1uoQkI8alqpqdQjIRztOH7I6BOSjzPQTHh0/vkUbj41dZvM6t/p17NhRYWFhev/9951tDz/8sIoVK6YFCxbIMAxFREQoMjJSo0ePlnSluhAWFqapU6fq6aefVnJyskqXLq0FCxaoe/fukqSTJ0+qXLlyWrFihTp06JBn74uKAwDAtjw5VZGWlqbz58+7HGlpaTliaNGihdauXauffvpJkvTDDz9o8+bN+vvf/y5JiouLU0JCgtq3b++8xtfXV61atdKWLVskSTExMcrIyHDpExERoVq1ajn75BUSBwAAPCA6OlpBQUEuR3R0dI5+o0eP1mOPPaa//e1v8vb2Vr169RQZGanHHntMkpSQkCBJCgsLc7kuLCzMeS4hIUE+Pj4qWbLkn/bJK9yOCQCwLcODt2NGRUVp+PDhLm2+vr45+n3yySf68MMPtXDhQtWsWVO7du1SZGSkIiIi1KdPH2c/h8M1VsMwcrRdzZ0+ZpE4AADgAb6+vtdMFK72/PPPa8yYMXr00UclSbVr19Yvv/yi6Oho9enTR+Hh4ZKuVBXKlCnjvC4xMdFZhQgPD1d6erqSkpJcqg6JiYlq1qxZXr4tpioAAPZVEG7HvHTpkm65xfXXcZEiRZy3Y1asWFHh4eFas2aN83x6ero2bNjgTAoaNGggb29vlz7x8fHau3dvnicOVBwAALDQAw88oMmTJ6t8+fKqWbOmdu7cqRkzZqhfv36SrkxRREZGasqUKapataqqVq2qKVOmqFixYurRo4ckKSgoSP3799eIESMUEhKi4OBgjRw5UrVr11a7du3yNF4SBwCAbZnZb8FT3njjDY0bN06DBg1SYmKiIiIi9PTTT2v8+PHOPqNGjVJqaqoGDRqkpKQkNW7cWKtXr1ZAQICzz8yZM+Xl5aVu3bopNTVVbdu21bx581SkSJE8jZd9HHDTYx8He2EfB3vx9D4Oxxq29djY5Xes9djYVmKNAwAAcBtTFQAA2yoIUxU3GyoOAADAbVQcAAC2RcXBPCoOAADAbVQcAAC2VfjuK/Q8Kg4AAMBtVBwAALbFGgfzSBwAALblyadjFlZMVQAAALdRcQAA2JaZp1jiCioOAADAbVQcAAC2lc0aB9OoOAAAALdRcQAA2BZ3VZhHxQEAALiNigMAwLbYAMo8yysOGzduVGZmZo72zMxMbdy40YKIAAB2YRieOworyxOHNm3a6OzZsznak5OT1aZNGwsiAgAAf8btqYrly5e7PWinTp3c7msYhhyOnKWiM2fOyN/f3+1xAAAwi6kK89xOHDp37uxWP4fDoaysrBv269Kli7N/37595evr6zyXlZWl3bt3q1mzZu6GBwAA8oHbiUN2dt7uyxkUFCTpSsUhICBAfn5+znM+Pj5q0qSJBgwYkKevCQDAH7EBlHl/+a6Ky5cvq2jRoqavmzt3riTptttu08iRI5mWAADgJpCrxZFZWVn65z//qbJly6p48eL6+eefJUnjxo3T+++/b2qsCRMmkDQAACxhGA6PHYVVrhKHyZMna968eZo2bZp8fHyc7bVr19a///1vU2P99ttv6tWrlyIiIuTl5aUiRYq4HAAAoODI1VTFBx98oNmzZ6tt27YaOHCgs71OnTr68ccfTY3Vt29fHTt2TOPGjVOZMmWueYcFAACeUJj3W/CUXCUOJ06cUJUqVXK0Z2dnKyMjw9RYmzdv1qZNm1S3bt3chAIAAPJRrqYqatasqU2bNuVo//TTT1WvXj1TY5UrV04GKR8AwALZhsNjR2GVq8RhwoQJGjx4sKZOnars7GwtXbpUAwYM0JQpUzR+/HhTY7366qsaM2aMjh49mptQ8F8Dn+6jQwe/U8r5I9q29Wu1aN7I6pBgUu/BPTRnxTta+9MKrdi9TFPn/EvlK5fL0e/JEX31ZexnWn9kld767FVVrHaby3lvH2+N+NdQrdz7hdYd/lovz5us0mVK59O7gCfw8+05LI40L1eJwwMPPKBPPvlEK1askMPh0Pjx43XgwAF9+eWXuueee0yN1b17d61fv16VK1dWQECAgoODXQ7cWNeunTRj+kRFv/S6GjbqoM2bv9dXX36ocuUirA4NJtRrWldL5n2uJzsO0tBHR6pIkSJ67eOXVdTvf7c793r2MT32VFdNH/ua+v19oM6cOqvXF72iYv7/2wdl2IuD1erelhr3zCQ93XmI/Ir5afoH0brlFst3mEcu8PONgsZhWDxPMH/+/Oue79Onj+kxvXzK5jacm9KWzV8qdudeDR4S5Wzbs3u9li9fqbEvvGRhZPmjYamqVofgESWCg7Ry7xca+NBQ7dq2W5L01c4l+uTfn2nBmx9LulJdWPHDMr05+V19/uGX8g/w18o9n+vFoVP0zfJ1kqRSYSH6YsdiDX98jLZt2G7Z+8krO04fsjqEfGX3n+/M9BMeHT+23IMeG7v+r194bGwr/aUNoHbs2KEDBw7I4XCoRo0aatCggekxcpMY4H+8vb1Vv34dTX35TZf2NWs2qGmThhZFhbxQPLC4JOn8uQuSpIjyZVQqLMTll39GeoZ2bt2l2g1r6vMPv9Tf6lSTt4+3S5/Tv53Rzz/GqfadNQtF4mAn/HyjIMpV4nD8+HE99thj+vbbb1WiRAlJ0rlz59SsWTN9/PHHKlcu57zs9Rw5ckRz587VkSNH9Nprryk0NFQrV65UuXLlVLNmzdyEaBulSgXLy8tLib+ddmlPTDytsPBQi6JCXnhu4iDt2rZbPx+MkySFhF6Zujt7Ksml39lTSQq/NczZJz0tXReSU1z7nE5SSGmm/m42/Hx7XmFexOgpuZr07NevnzIyMnTgwAGdPXtWZ8+e1YEDB2QYhvr3729qrA0bNqh27dratm2bli5dqpSUK3/h7d69WxMmTLjh9WlpaTp//rzLYce7NK5+zw6Hw5bfh8Ji5JTnVKVGZY0b9M8c5679WV9/PHf6oODi5xsFSa4Sh02bNuntt99W9erVnW3Vq1fXG2+8cc3bNK9nzJgx+te//qU1a9a47ELZpk0bfffddze8Pjo6WkFBQS6HkX3BVAw3s9OnzyozM1Nh4a6r5kuXDlHib6csigp/xYh/DVXL9s016JFInYr/32d4JvGspP9VHn5XslQJnT111tnHx9dHAUHFXfuElNDZ02c9HDnyGj/fnsddFeblKnEoX778NTd6yszMVNmy5hYm7tmzRw899FCO9tKlS+vMmTM3vD4qKkrJyckuh+OWAFMx3MwyMjIUG7tb7dre5dLert1d+m7rDouiQm6NmPycWt3XUoO7DlP8rwku504ei9fp386o0V3/m9v28vZSvSZ1tWfHPknSj7t/UkZ6hkufkNBgVfpbRe3Zvi9/3gTyDD/fKIhytcZh2rRpGjJkiN588001aNBADodDO3bs0HPPPadXXnnF1FglSpRQfHy8Klas6NK+c+dOt5IQX19f+fr6urTZbdvqma+9p/lzX1NMzA/aui1GA/o/rvLlyurd2QusDg0mPD8lUu0faqdRT4zVxZRUBf93TcLFCylKu5wuSfrk35+pz5DH9evPx/Vr3An1GdpTl1Mva/Wyb/7b96K+/HiFhk4YpOSk8zp/7ryGjHtGR36M0/ZNMZa9N+QeP9+exRoH89xOHEqWLOnyC/nixYtq3LixvLyuDJGZmSkvLy/169dPnTt3djuAHj16aPTo0fr000/lcDiUnZ2tb7/9ViNHjlTv3r3dfyc29umnyxUSXFIvjB2mMmVCtXffQT3QqZeOHfPsbUzIWw/37SxJenvpay7t/4x8Sf+3eKUkacGbH8u3qK+ejx6mgKAA7du5X8899rwuXUx19n914pvKysrS5HcmyNfPVzs2x2pknyhlZ2fn23tB3uHn27NYKWKe2/s43Gi/hT8yc4tlRkaG+vbtq0WLFskwDHl5eSkrK0s9evTQvHnzcvWETLvt42B3hXUfB1yb3fZxsDtP7+OwNaKLx8ZucnKpx8a2kuUbQP3uyJEj2rlzp7Kzs1WvXj1VrZr7XwYkDvZC4mAvJA724unEYUuZhz02drP4JR4b20p/aQMoSUpNTc2xUDIwMND0OJUrV1blypX/ajgAAMCDcpU4XLx4UaNHj9bixYuveedDVlbWda8fPny42681Y8YM0/EBAOCOwnzbpKfkKnEYNWqU1q1bp7feeku9e/fWm2++qRMnTujdd9/VSy/deO/0nTt3uvU6drs7AgCAgi5XicOXX36pDz74QK1bt1a/fv3UsmVLValSRRUqVNBHH32knj17Xvf6devW5SpYAADyEvcamZerDaDOnj3r3HchMDBQZ89e2ZGuRYsW2rhxY95FBwAACpRcVRwqVaqko0ePqkKFCrr99tu1ePFiNWrUSF9++aWCgoJueH2XLl00b948BQYGqkuX698Ks3Rp4bydBQBgPUNMiZuVq8ThiSee0A8//KBWrVopKipK999/v9544w1lZma6tZgxKCjIuX7BnUQDAABPyC4QGxLcXPJkH4djx45px44dKl26tObOnas5c+a4fW1qaqqys7Pl7+8vSTp69Kg+//xz1ahRQx06dMhVPOzjYC/s42Av7ONgL57ex2F9WFePjd36t089NraVcrXG4Wrly5dXly5dFBgYaGqHSUl68MEHtWDBlT3Xz507pyZNmmj69Onq3Lmz3n777bwIDwCAa8qWw2NHYZUnicNfERsbq5YtW0qSPvvsM4WFhemXX37RBx98oNdff93i6AAAwB/95Z0j/6pLly4pIODKY7BXr16tLl266JZbblGTJk30yy+/WBwdAKAwY3GkeZZXHKpUqaLPP/9cv/76q1atWqX27dtLkhITE3O1dTUAAPAcUxWHG906ee7cOdMBjB8/Xj169NCwYcPUtm1bNW3aVNKV6kO9evVMjwcAgLvYAMo8U4nDjW6dDAoKUu/evU0F8Mgjj6hFixaKj4/XHXfc4Wxv27atHnroIVNjAQAAzzKVOMydO9cjQYSHhys8PNylrVGjRh55LQAAfscaB/MsXxwJAIBVmKowz/LFkQAA4OZB4gAAsK1sDx5mnDhxQo8//rhCQkJUrFgx1a1bVzExMc7zhmFo4sSJioiIkJ+fn1q3bq19+/a5jJGWlqYhQ4aoVKlS8vf3V6dOnXT8+HGTkdwYiQMAABZKSkpS8+bN5e3tra+//lr79+/X9OnTVaJECWefadOmacaMGZo1a5a2b9+u8PBw3XPPPbpw4YKzT2RkpJYtW6ZFixZp8+bNSklJUceOHZWVlZWn8ebJsyoKGp5VYS88q8JeeFaFvXj6WRX/F/aYx8a+/7eP3eo3ZswYffvtt9q0adM1zxuGoYiICEVGRmr06NGSrlQXwsLCNHXqVD399NNKTk5W6dKltWDBAnXv3l2SdPLkSZUrV04rVqzI9bOfroWKAwAAHpCWlqbz58+7HGlpaTn6LV++XA0bNlTXrl0VGhqqevXq6b333nOej4uLU0JCgnODREny9fVVq1attGXLFklSTEyMMjIyXPpERESoVq1azj55hcQBAGBb2Q7PHdHR0QoKCnI5oqOjc8Tw888/6+2331bVqlW1atUqDRw4UEOHDtUHH3wgSUpISJAkhYWFuVwXFhbmPJeQkCAfHx+VLFnyT/vkFW7HBADAA6KiojR8+HCXNl9f3xz9srOz1bBhQ02ZMkWSVK9ePe3bt09vv/22y6aKDofrnhOGYeRou5o7fcyi4gAAsC1PPlbb19dXgYGBLse1EocyZcro9ttvd2mrUaOGjh07JknODRKvrhwkJiY6qxDh4eFKT09XUlLSn/bJKyQOAADbMjx4uKt58+Y6ePCgS9tPP/2kChUqSJIqVqyo8PBwrVmzxnk+PT1dGzZsULNmzSRJDRo0kLe3t0uf+Ph47d2719knrzBVAQCAhYYNG6ZmzZppypQp6tatm77//nvNnj1bs2fPlnRliiIyMlJTpkxR1apVVbVqVU2ZMkXFihVTjx49JF15VlT//v01YsQIhYSEKDg4WCNHjlTt2rXVrl27PI2XxAEAYFsFYcvpO++8U8uWLVNUVJQmTZqkihUr6tVXX1XPnj2dfUaNGqXU1FQNGjRISUlJaty4sVavXq2AgABnn5kzZ8rLy0vdunVTamqq2rZtq3nz5qlIkSJ5Gi/7OOCmxz4O9sI+Dvbi6X0clob38NjYXRIWemxsK1FxAADYVnYe33FgByyOBAAAbqPiAACwrUI3V58PqDgAAAC3UXEAANhWQbir4mZD4gAAsK1s1kaaxlQFAABwGxUHAIBtZYuSg1lUHAAAgNuoOAAAbIvbMc2j4gAAANxGxQEAYFvcVWEeFQcAAOA2Kg4AANtiAyjzSBwAALbF4kjzmKoAAABuo+IAALAtFkeaR8UBAAC4jYoDAMC2WBxpHhUHAADgNioOAADbouJgHhUHAADgNioOAADbMrirwjQSBwCAbTFVYR5TFQAAwG1UHAAAtkXFwTwqDgAAwG1UHAAAtsVDrsyj4gAAANxGxQEAYFs85Mo8Kg4AAMBtVBwAALbFXRXmkTgAAGyLxME8pioAAIDbqDgAAGyL2zHNo+IAAADcRsUBAGBb3I5pHhUHAADgNioOAADb4q4K86g4AAAAt1FxAADYFndVmEfFAQAAuI2KAwDAtrKpOZhWKBOH/hHNrA4B+ej9k1usDgH5qKiXj9UhoBBhcaR5TFUAAAC3FcqKAwAA7mCiwjwqDgAAwG1UHAAAtsUaB/OoOAAAALdRcQAA2BYPuTKPigMAAHAbFQcAgG2xAZR5JA4AANsibTCPqQoAAOA2Kg4AANvidkzzqDgAAAC3UXEAANgWiyPNo+IAAEABEh0dLYfDocjISGebYRiaOHGiIiIi5Ofnp9atW2vfvn0u16WlpWnIkCEqVaqU/P391alTJx0/fjzP4yNxAADYluHBIze2b9+u2bNnq06dOi7t06ZN04wZMzRr1ixt375d4eHhuueee3ThwgVnn8jISC1btkyLFi3S5s2blZKSoo4dOyorKyuX0VwbiQMAAAVASkqKevbsqffee08lS5Z0thuGoVdffVVjx45Vly5dVKtWLc2fP1+XLl3SwoULJUnJycl6//33NX36dLVr10716tXThx9+qD179uibb77J0zhJHAAAtpXtwSMtLU3nz593OdLS0v40lmeffVb333+/2rVr59IeFxenhIQEtW/f3tnm6+urVq1aacuWLZKkmJgYZWRkuPSJiIhQrVq1nH3yCokDAMC2smV47IiOjlZQUJDLER0dfc04Fi1apNjY2GueT0hIkCSFhYW5tIeFhTnPJSQkyMfHx6VScXWfvMJdFQAAeEBUVJSGDx/u0ubr65uj36+//qrnnntOq1evVtGiRf90PIfD9YlchmHkaLuaO33MouIAALAtTy6O9PX1VWBgoMtxrcQhJiZGiYmJatCggby8vOTl5aUNGzbo9ddfl5eXl7PScHXlIDEx0XkuPDxc6enpSkpK+tM+eYXEAQAAC7Vt21Z79uzRrl27nEfDhg3Vs2dP7dq1S5UqVVJ4eLjWrFnjvCY9PV0bNmxQs2bNJEkNGjSQt7e3S5/4+Hjt3bvX2SevMFUBALCtgrDldEBAgGrVquXS5u/vr5CQEGd7ZGSkpkyZoqpVq6pq1aqaMmWKihUrph49ekiSgoKC1L9/f40YMUIhISEKDg7WyJEjVbt27RyLLf8qEgcAAAq4UaNGKTU1VYMGDVJSUpIaN26s1atXKyAgwNln5syZ8vLyUrdu3ZSamqq2bdtq3rx5KlKkSJ7G4jAMo9Dtt/n0bV2tDgH56P2TeXurEQq2ol4+VoeAfJRyKc6j4w+9rbvHxn796CceG9tKrHEAAABuY6oCAGBbBWGNw82GxAEAYFs8HdM8pioAAIDbqDgAAGyLeoN5VBwAAIDbqDgAAGyLNQ7mUXEAAABuo+IAALAtbsc0j4oDAABwGxUHAIBtGaxxMI3EAQBgW0xVmMdUBQAAcBsVBwCAbTFVYR4VBwAA4DYqDgAA22KNg3lUHAAAgNuoOAAAbCvbYI2DWVQcAACA26g4AABsi3qDeSQOAADb4umY5jFVAQAA3EbFAQBgW2wAZR4VBwAA4DYqDgAA22IDKPOoOAAAALdRcQAA2BZ3VZhHxQEAALiNigMAwLa4q8I8EgcAgG2xONI8pioAAIDbCkzFYe3atVq7dq0SExOVne2aA86ZM8eiqAAAhZnB0zFNKxCJw4svvqhJkyapYcOGKlOmjBwOh9UhAQCAaygQicM777yjefPmqVevXlaHAgCwEW7HNK9ArHFIT09Xs2bNrA4DAADcQIFIHJ588kktXLjQ6jAAADaT7cGjsCoQUxWXL1/W7Nmz9c0336hOnTry9vZ2OT9jxgyLIgMAAH9UIBKH3bt3q27dupKkvXv3upxjoSQAwFPYAMq8ApE4rFu3zuoQAAA2xOJI8wrEGgcAAHBzsKzi0KVLF82bN0+BgYHq0qXLdfsuXbo0n6ICANgJG0CZZ1niEBQU5Fy/EBQUZFUYAADABMsSh7lz517zzwAA5JfCfNukpxSINQ4vvviijhw5YnUYAADgBgpE4rBkyRJVq1ZNTZo00axZs3Tq1CmrQwIA2IDhwf8KqwKROOzevVu7d+/W3XffrRkzZqhs2bL6+9//roULF+rSpUtWhwcAAP6rQCQOklSzZk1NmTJFP//8s9atW6eKFSsqMjJS4eHhVodmmbseb69xX7+iV/fM16t75mv00smq2bquS5/wymU16L3RenX3fL229wONXjZZJSNKOc97+Xjp0Yn9ND32fb2+f4EGvTdaJcKD8/mdIK8NfLqPDh38Tinnj2jb1q/Vonkjq0NCHhsx8hmlXIrT1GnjXNr/MfY5HTqyVafOHNDXKz9WjRpVLYqwcMiW4bGjsCowicMf+fv7y8/PTz4+PsrIyLA6HMuciz+jZVM/0pROYzSl0xj9uGWvBs0erTJVb5UklSofpuc/+6cSjpzQ9Mcm6J/3jdT/vb5EmWnpzjG6jX9CdTs00ntDXtXLXcfJ17+oBs+JkuOWAvnRww1du3bSjOkTFf3S62rYqIM2b/5eX335ocqVi7A6NOSR+g3q6Il+j2nP7gMu7cOGP63BQ/prxPAJatXyQf322ykt/2qBihf3tyhS2FGB+e0RFxenyZMn6/bbb1fDhg0VGxuriRMnKiEhwerQLLN7bYz2rt+pxLh4JcbF64tXPlbapcuqVK+aJKnz849p77qdWvrSh/p131Gd/jVRe9fF6sKZ85KkogHF1Lzb3fps8gf68ds9+nXfUc2JfF1lq5dXjRa1rXxr+AuGPTdAc+Yu0py5H+vHHw9rxMgJ+vX4SQ18urfVoSEP+PsX0/tzXtXgZ6N07lyyy7lnB/fTy9Pe1PIvVmn//p/01ICR8vPzU7funSyK9uZnGIbHjsKqQCQOTZs2VZUqVfTpp5/qiSee0C+//KL//Oc/evLJJ9nj4b8ct9yihg80k4+fr36O/UkOh0O129TXb3EnNfSDsXp5x7815vMpuqP9nc5rKtSqJC8fL+3f+IOzLTkxSSd+OqbKDapb8TbwF3l7e6t+/Tpa880Gl/Y1azaoaZOGFkWFvDRj5iStWvkfrV/3rUv7bbeVU3h4qNau3eRsS09P1+bN29S4cYP8DrPQYKrCvALxrIo2bdro3//+t2rWrGl1KAVORPXyGr10srx9vZV26bLeefplxR8+rsDSJVS0uJ/ufaazvpi+SEtf+kg1W9XVwHdGasZjL+rQtv0KLF1CGWkZunT+osuYF04lK7B0CWveEP6SUqWC5eXlpcTfTru0JyaeVlh4qEVRIa888khH1a1bU3e1fDDHubCw0pKufNZ/dCrxtMqVK5sv8QFSAUgcMjIytGjRIj3++OO5uj4tLU1paWkubVlGloo4iuRFeJb77eeT+tffn1exwGKqd18T9Z0+WNO7T3AmAz+s2aG17/+fJOn4/qOqXL+67up5jw5t2//ngzochbqMZgdXf34OPtObXtmyZTTt5Qnq1Km30v6wTulqOT5nh6NQ3/rnaXzvzLN8qsLb21tpaWm5fnx2dHS0goKCXI6dyT/mcZTWycrI1KlfEvTLnp/1+bSFOn7gqO7u93elJF1QVkam4g/96tI/4chxBf/3rorzp87J29dbxQJdF04FlArUhdOuc6e4OZw+fVaZmZkKCy/t0l66dIgSf2P/k5tZvfq1FBpWSpu/Xa5z5w/p3PlDanlXEz0zqK/OnT/krDT8Xnn43ZXP/vS1hgQ8wvLEQZKGDBmiqVOnKjMz0/S1UVFRSk5OdjnqBf3NA1EWDA6HQ14+3srKyNTR3UcUVsm1RBlaMUJnT1z5S+SXvT8rMz1TNVrWcZ4PLF1CZauV15GYg/kaN/JGRkaGYmN3q13bu1za27W7S99t3WFRVMgL69dtUaOGHdSsyf3OIybmB32y6As1a3K/4uKOKSEhUXff3dJ5jbe3t1q0aKxt22IsjPzmlm0YHjsKK8unKiRp27ZtWrt2rVavXq3atWvL39/1X8jXezqmr6+vfH19XdoKyzRF5+cf0971O5UUf0a+/n6684Hmqtakpl7vM1mStHr2cg14Y5gOfb9fB7/bp5qt6qpO2waa/uhESdLlC5f07eL/6JGxvXUx6YIuJqfokX/01omDx3Rg8x4L3xn+ipmvvaf5c19TTMwP2rotRgP6P67y5crq3dkLrA4Nf0FKykXt3/+TS9uli6k6ezbJ2f7mrDka+fwgHTkSpyOHj2rk84OUmpqqxZ8styJk2FSBSBxKlCihhx9+2OowCpyAUiX0xMwhCipdUqkXLunEj7/o9T6TdWDzbknSrlXf66Oxs3XvoIfUfWI//fbzSb37zCs6suN/UzWL/zlP2ZlZGvDmcPkU9dGP3+7RvJFvysjm0S43q08/Xa6Q4JJ6YewwlSkTqr37DuqBTr107NgJq0ODh82c8a78/Ipq5qv/VIkSQdqxfZcefKC3UlIu3vhiXFPhrQt4jsMohCuqnr6tq9UhIB+9f3KL1SEgHxX18rE6BOSjlEtxHh2/Zdm2Hht704m1HhvbSgVijQMAAFYoCPs4REdH684771RAQIBCQ0PVuXNnHTzoug7NMAxNnDhRERER8vPzU+vWrbVv3z6XPmlpaRoyZIhKlSolf39/derUScePH8+T79MfFZjE4bPPPlO3bt3UpEkT1a9f3+UAAMATCkLisGHDBj377LPaunWr1qxZo8zMTLVv314XL/5vCmratGmaMWOGZs2ape3btys8PFz33HOPLly44OwTGRmpZcuWadGiRdq8ebNSUlLUsWNHZWVl5en3rEAkDq+//rqeeOIJhYaGaufOnWrUqJFCQkL0888/67777rM6PAAAPGblypXq27evatasqTvuuENz587VsWPHFBNz5W4ZwzD06quvauzYserSpYtq1aql+fPn69KlS1q4cKEkKTk5We+//76mT5+udu3aqV69evrwww+1Z88effPNN3kab4FIHN566y3Nnj1bs2bNko+Pj0aNGqU1a9Zo6NChSk5mvwEAgGd48lkVaWlpOn/+vMtx9YaF1/L7773g4CtPMo6Li1NCQoLat2/v7OPr66tWrVppy5Yra7xiYmKUkZHh0iciIkK1atVy9skrBSJxOHbsmJo1ayZJ8vPzc5ZeevXqpY8//tjK0AAAyJVrbVAYHR193WsMw9Dw4cPVokUL1apVS5KcD3sMCwtz6RsWFuY8l5CQIB8fH5UsWfJP++SVAnE7Znh4uM6cOaMKFSqoQoUK2rp1q+644w7FxcWxjS4AwGM8+TCqqKgoDR8+3KXt6n2HrjZ48GDt3r1bmzdvznHu6h2WDcO44a7L7vQxq0BUHO6++259+eWXkqT+/ftr2LBhuueee9S9e3c99NBDFkcHAIB5vr6+CgwMdDmulzgMGTJEy5cv17p163Trrbc628PDwyUpR+UgMTHRWYUIDw9Xenq6kpKS/rRPXikQicPs2bM1duxYSdLAgQM1f/581ahRQy+++KLeeecdi6MDABRWhgf/czsGw9DgwYO1dOlS/ec//1HFihVdzlesWFHh4eFas2aNsy09PV0bNmxwTvM3aNBA3t7eLn3i4+O1d+9eZ5+8UiCmKm655Ralp6crNjZWiYmJ8vX1Vbt27SRdWW36wAMPWBwhAACe8eyzz2rhwoX64osvFBAQ4KwsBAUFyc/PTw6HQ5GRkZoyZYqqVq2qqlWrasqUKSpWrJh69Ojh7Nu/f3+NGDFCISEhCg4O1siRI1W7dm3n79O8UiASh5UrV6pXr146c+ZMjnMOhyPP70EFAEC6xmPKLfD2229Lklq3bu3SPnfuXPXt21eSNGrUKKWmpmrQoEFKSkpS48aNtXr1agUEBDj7z5w5U15eXurWrZtSU1PVtm1bzZs3T0WK5O3zmwrEltNVqlRRhw4dNH78+DyZi2HLaXthy2l7Yctpe/H0ltP1y7Tw2Nix8TkXOBYGBWKNQ2JiooYPH57nCzgAAEDeKhCJwyOPPKL169dbHQYAwGY8uQFUYVUg1jjMmjVLXbt21aZNm1S7dm15e3u7nB86dKhFkQEAgD8qEInDwoULtWrVKvn5+Wn9+vUum1U4HA4SBwCAR3hyA6jCqkAkDi+88IImTZqkMWPG6JZbCsTsCQAAuIYCkTikp6ere/fuJA0AgHxlZqMmXFEgflP36dNHn3zyidVhAACAGygQFYesrCxNmzZNq1atUp06dXIsjpwxY4ZFkQEACrPsQnz3g6cUiMRhz549qlevniRp7969Lufy+qleAAD8jqkK8wpE4rBu3TqrQwAAAG4oEIkDAABWYKrCvAKxOBIAANwcqDgAAGyLNQ7mUXEAAABuo+IAALAt1jiYR8UBAAC4jYoDAMC2WONgHokDAMC2mKowj6kKAADgNioOAADbYqrCPCoOAADAbVQcAAC2ZRjZVodw06HiAAAA3EbFAQBgW9mscTCNigMAAHAbFQcAgG0Z7ONgGokDAMC2mKowj6kKAADgNioOAADbYqrCPCoOAADAbVQcAAC2xUOuzKPiAAAA3EbFAQBgWzzkyjwqDgAAwG1UHAAAtsVdFeaROAAAbIsNoMxjqgIAALiNigMAwLaYqjCPigMAAHAbFQcAgG2xAZR5VBwAAIDbqDgAAGyLNQ7mUXEAAABuo+IAALAt9nEwj8QBAGBbTFWYx1QFAABwGxUHAIBtcTumeVQcAACA26g4AABsy2BxpGlUHAAAgNuoOAAAbIs1DuZRcQAAAG6j4gAAsC32cTCPigMAAHAbFQcAgG1xV4V5JA4AANtiqsI8pioAAIDbSBwAALZlGIbHDrPeeustVaxYUUWLFlWDBg20adMmD7zjv47EAQAAi33yySeKjIzU2LFjtXPnTrVs2VL33Xefjh07ZnVoOZA4AABsy/DgYcaMGTPUv39/Pfnkk6pRo4ZeffVVlStXTm+//fZffId5j8QBAAAPSEtL0/nz512OtLS0HP3S09MVExOj9u3bu7S3b99eW7Zsya9w3VYo76p49+inVoeQ79LS0hQdHa2oqCj5+vpaHU6+etfqACxg58/bjvi8PScz/YTHxp44caJefPFFl7YJEyZo4sSJLm2nT59WVlaWwsLCXNrDwsKUkJDgsfhyy2FwL0qhcP78eQUFBSk5OVmBgYFWhwMP4/O2Fz7vm1NaWlqOCoOvr2+O5O/kyZMqW7astmzZoqZNmzrbJ0+erAULFujHH3/Ml3jdVSgrDgAAWO1aScK1lCpVSkWKFMlRXUhMTMxRhSgIWOMAAICFfHx81KBBA61Zs8alfc2aNWrWrJlFUf05Kg4AAFhs+PDh6tWrlxo2bKimTZtq9uzZOnbsmAYOHGh1aDmQOBQSvr6+mjBhAgunbILP2174vAu/7t2768yZM5o0aZLi4+NVq1YtrVixQhUqVLA6tBxYHAkAANzGGgcAAOA2EgcAAOA2EgcAAOA2Egcb69u3rzp37mx1GPiDqz+T1q1bKzIy0rJ4YC0+fxRE3FVhY6+99lquHv0Kz8mPz6Rv3746d+6cPv/8c4++Dty3fv16tWnTRklJSSpRooTV4QDXReJQCKWnp8vHx+eG/YKCgvIhGpjBZwJPy8jIkLe3t9Vh4CbGVEU+a926tYYMGaLIyEiVLFlSYWFhmj17ti5evKgnnnhCAQEBqly5sr7++mtJUlZWlvr376+KFSvKz89P1atX12uvveYy5u/l7ejoaEVERKhatWqKiopSkyZNcrx+nTp1NGHCBJfr/hjb0KFDNWrUKAUHBys8PDzHw1iQNz777DPVrl1bfn5+CgkJUbt27XTx4sUbTh+lp6dr1KhRKlu2rPz9/dW4cWOtX7/eeX7evHkqUaKEVq1apRo1aqh48eK69957FR8fL+nKQ3fmz5+vL774Qg6HQw6Hw+V6eE5aWpqGDh2q0NBQFS1aVC1atND27dt19OhRtWnTRpJUsmRJORwO9e3b13lddnb2dX8mk5OT9dRTTyk0NFSBgYG6++679cMPPzjPT5w4UXXr1tWcOXNUqVIl+fr6UmnEX0LiYIH58+erVKlS+v777zVkyBA988wz6tq1q5o1a6bY2Fh16NBBvXr10qVLl5Sdna1bb71Vixcv1v79+zV+/Hj94x//0OLFi13GXLt2rQ4cOKA1a9boq6++Us+ePbVt2zYdOXLE2Wffvn3as2ePevbsed3Y/P39tW3bNk2bNk2TJk3KsQ0q/pr4+Hg99thj6tevnw4cOKD169erS5cubv1l/sQTT+jbb7/VokWLtHv3bnXt2lX33nuvDh065Oxz6dIlvfLKK1qwYIE2btyoY8eOaeTIkZKkkSNHqlu3bs5kIj4+vkBuaVsYjRo1SkuWLNH8+fMVGxurKlWqqEOHDgoICNCSJUskSQcPHlR8fLzLPw6u9zNpGIbuv/9+JSQkaMWKFYqJiVH9+vXVtm1bnT171jnG4cOHtXjxYi1ZskS7du3K1/eNQshAvmrVqpXRokUL59eZmZmGv7+/0atXL2dbfHy8Icn47rvvrjnGoEGDjIcfftj5dZ8+fYywsDAjLS3NpV+dOnWMSZMmOb+Oiooy7rzzTpfrHnzwwT+NzTAM48477zRGjx5t7k3iumJiYgxJxtGjR3Ocu9Zn8txzzxmGYRiHDx82HA6HceLECZdr2rZta0RFRRmGYRhz5841JBmHDx92nn/zzTeNsLCwP30NeF5KSorh7e1tfPTRR8629PR0IyIiwpg2bZqxbt06Q5KRlJTkct2NfibXrl1rBAYGGpcvX3bpU7lyZePdd981DMMwJkyYYHh7exuJiYkeeGewIyoOFqhTp47zz0WKFFFISIhq167tbPv9aWiJiYmSpHfeeUcNGzZU6dKlVbx4cb333ns6duyYy5i1a9fOsa6hZ8+e+uijjyRd+ZfJxx9/fN1qw9WxSVKZMmWccSBv3HHHHWrbtq1q166trl276r333lNSUtINr4uNjZVhGKpWrZqKFy/uPDZs2OBSWSpWrJgqV67s/JrP0HpHjhxRRkaGmjdv7mzz9vZWo0aNdODAgetee72fyZiYGKWkpCgkJMTl/4m4uDiX/ycqVKig0qVL5+E7gp2xONICVy9McjgcLm0Oh0PSlbnNxYsXa9iwYZo+fbqaNm2qgIAAvfzyy9q2bZvLGP7+/jlep0ePHhozZoxiY2OVmpqqX3/9VY8++qjp2LKzs029P1xfkSJFtGbNGm3ZskWrV6/WG2+8obFjx+b4TK+WnZ2tIkWKKCYmRkWKFHE5V7x4ceefr/UZGsxpW+r37//vP9t/bL+67WrX+5nMzs5WmTJlrrlO5Y93Z1zr7wcgt0gcCrhNmzapWbNmGjRokLPtj/+SuJ5bb71Vd911lz766COlpqaqXbt2BfLZ7nbkcDjUvHlzNW/eXOPHj1eFChW0bNmy615Tr149ZWVlKTExUS1btsz1a/v4+CgrKyvX18O8KlWqyMfHR5s3b1aPHj0kXbm7YceOHYqMjHRWC81+LvXr11dCQoK8vLx022235XXYwDUxVVHAValSRTt27NCqVav0008/ady4cdq+fbvb1/fs2VOLFi3Sp59+qscff9yDkcJd27Zt05QpU7Rjxw4dO3ZMS5cu1alTp1SjRo3rXletWjX17NlTvXv31tKlSxUXF6ft27dr6tSpWrFihduvf9ttt2n37t06ePCgTp8+rYyMjL/6lnAD/v7+euaZZ/T8889r5cqV2r9/vwYMGKBLly6pf//+qlChghwOh7766iudOnVKKSkpbo3brl07NW3aVJ07d9aqVat09OhRbdmyRS+88IJ27Njh4XcFuyJxKOAGDhyoLl26qHv37mrcuLHOnDnjUn24ka5du+rMmTO6dOkSu0QWEIGBgdq4caP+/ve/q1q1anrhhRc0ffp03XfffTe8du7cuerdu7dGjBih6tWrq1OnTtq2bZvKlSvn9usPGDBA1atXd66b+fbbb//K24GbXnrpJT388MPq1auX6tevr8OHD2vVqlUqWbKkypYtqxdffFFjxoxRWFiYBg8e7NaYDodDK1as0F133aV+/fqpWrVqevTRR3X06FGqi/AYHqsNAADcRsUBAAC4jcQBAAC4jcQBAAC4jcQBAAC4jcQBAAC4jcQBAAC4jcQBAAC4jcQBKMAmTpyounXrOr/u27fvX97IKy/GAGBfJA5ALvTt21cOh8P5gLJKlSpp5MiRunjxokdf97XXXtO8efPc6nv06FE5HA7t2rUr12MAwNV4yBWQS/fee6/mzp2rjIwMbdq0SU8++aQuXryot99+26VfRkZGjicc5lZQUFCBGAOAfVFxAHLJ19dX4eHhKleunHr06KGePXvq888/d04vzJkzR5UqVZKvr68Mw1BycrKeeuophYaGKjAwUHfffbd++OEHlzFfeuklhYWFKSAgQP3799fly5ddzl89zZCdna2pU6eqSpUq8vX1Vfny5TV58mRJUsWKFSVdeaqmw+FQ69atrzlGWlqahg4dqtDQUBUtWlQtWrRweZDa+vXr5XA4tHbtWjVs2FDFihVTs2bNdPDgwTz8bgK4WZA4AHnEz8/P+aTJw4cPa/HixVqyZIlzquD+++9XQkKCVqxYoZiYGNWvX19t27bV2bNnJUmLFy/WhAkTNHnyZO3YsUNlypTRW2+9dd3XjIqK0tSpUzVu3Djt379fCxcudD7c6Pvvv5ckffPNN4qPj9fSpUuvOcaoUaO0ZMkSzZ8/X7GxsapSpYo6dOjgjOt3Y8eO1fTp07Vjxw55eXmpX79+uf5eAbiJGQBM69Onj/Hggw86v962bZsREhJidOvWzZgwYYLh7e1tJCYmOs+vXbvWCAwMNC5fvuwyTuXKlY13333XMAzDaNq0qTFw4ECX840bNzbuuOOOa77u+fPnDV9fX+O99967ZoxxcXGGJGPnzp1/GntKSorh7e1tfPTRR87z6enpRkREhDFt2jTDMAxj3bp1hiTjm2++cfb5v//7P0OSkZqa+uffJACFEhUHIJe++uorFS9eXEWLFlXTpk1111136Y033pAkVahQQaVLl3b2jYmJUUpKikJCQlS8eHHnERcXpyNHjkiSDhw4oKZNm7q8xtVf/9GBAweUlpamtm3b5vo9HDlyRBkZGWrevLmzzdvbW40aNdKBAwdc+tapU8f55zJlykiSEhMTc/3aAG5OLI4EcqlNmzZ6++235e3trYiICJcFkP7+/i59s7OzVaZMGa1fvz7HOCVKlMjV6/v5+eXquj8yDEOS5HA4crRf3fbH9/f7uezs7L8cA4CbCxUHIJf8/f1VpUoVVahQ4YZ3TdSvX18JCQny8vJSlSpVXI5SpUpJkmrUqKGtW7e6XHf1139UtWpV+fn5ae3atdc87+PjI0nKysr60zGqVKkiHx8fbd682dmWkZGhHTt2qEaNGtd9TwDsiYoDkA/atWunpk2bqnPnzpo6daqqV6+ukydPasWKFercubMaNmyo5557Tn369FHDhg3VokULffTRR9q3b58qVap0zTGLFi2q0aNHa9SoUfLx8VHz5s116tQp7du3T/3791doaKj8/Py0cuVK3XrrrSpatGiOWzH9/f31zDPP6Pnnn1dwcLDKly+vadOm6dKlS+rfv39+fGsA3GRIHIB84HA4tGLFCo0dO1b9+vXTqVOnFB4errvuust5F0T37t115MgRjR49WpcvX9bDDz+sZ555RqtWrfrTcceNGycvLy+NHz9eJ0+eVJkyZTRw4EBJkpeXl15//XVNmjRJ48ePV8uWLa85VfLSSy8pOztbvXr10oULF9SwYUOtWrVKJUuW9Mj3AsDNzWH8PskJAABwA6xxAAAAbiNxAAAAbiNxAAAAbiNxAAAAbiNxAAAAbiNxAAAAbiNxAAAAbiNxAAAAbiNxAAAAbiNxAAAAbiNxAAAAbiNxAAAAbvt/D+IW2EFmXdIAAAAASUVORK5CYII=", + "text/plain": [ + "
" + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], "source": [ "build_and_plot_confusion_matrix(model, ds_train)" ] @@ -359,12 +573,26 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 20, "id": "45495640-7e98-474e-910f-6070f157ad60", "metadata": {}, - "outputs": [], + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "WARNING:absl:At this time, the v2.11+ optimizer `tf.keras.optimizers.Adam` runs slowly on M1/M2 Macs, please use the legacy Keras optimizer instead, located at `tf.keras.optimizers.legacy.Adam`.\n", + "WARNING:absl:At this time, the v2.11+ optimizer `tf.keras.optimizers.RestoredOptimizer` runs slowly on M1/M2 Macs, please use the legacy Keras optimizer instead, located at `tf.keras.optimizers.legacy.RestoredOptimizer`.\n", + "/Users/jeremy/miniforge3/envs/jh_main/lib/python3.11/site-packages/tensorflow/lite/python/convert.py:947: UserWarning: Statistics for quantized inputs were expected, but not specified; continuing anyway.\n", + " warnings.warn(\n", + "fully_quantize: 0, inference_type: 6, input_inference_type: INT8, output_inference_type: INT8\n", + "Wrote to trained_models/str_ww_quant_model.tflite\n" + ] + } + ], "source": [ - "!python quantize.py --saved_model_path=trained_models/str_ww_ref_model.h5\n" + "!python quantize.py --saved_model_path=trained_models/str_ww_ref_model.h5 \\\n", + " --tfl_file_name=$tfl_file_name\n" ] }, { @@ -377,7 +605,7 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 42, "id": "97a9667f-e5f0-4d20-a18b-91203ac8e65b", "metadata": {}, "outputs": [], @@ -395,10 +623,20 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 43, "id": "0e49f1eb-539c-4df4-80ed-cfe497a501f4", "metadata": {}, - "outputs": [], + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "Output = [[-128 -128 127]].\n", + "True (vs predicted) label = 2 (vs 2)\n", + "Dequantized output vector = [[0. 0. 0.99609375]]\n" + ] + } + ], "source": [ "spec, label = next(ds_val.unbatch().batch(1).take(1).as_numpy_iterator())\n", "\n", @@ -425,10 +663,19 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 44, "id": "df1b2884-42dd-4d35-a0b7-adcd9baf4a44", "metadata": {}, - "outputs": [], + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "Accuracy = 0.937 (13096/13980)\n", + "Measured validation accuracy in 19.641629934310913 s\n" + ] + } + ], "source": [ "t0 = time.time(); \n", "predictions = []\n", @@ -465,10 +712,21 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 45, "id": "25950850-87f2-4dda-9965-776f68c25f2e", "metadata": {}, - "outputs": [], + "outputs": [ + { + "data": { + "image/png": "iVBORw0KGgoAAAANSUhEUgAAAg4AAAINCAYAAABWL/eXAAAAOnRFWHRTb2Z0d2FyZQBNYXRwbG90bGliIHZlcnNpb24zLjEwLjAsIGh0dHBzOi8vbWF0cGxvdGxpYi5vcmcvlHJYcgAAAAlwSFlzAAAPYQAAD2EBqD+naQAATMhJREFUeJzt3XmcTvX7x/H3nVmMMTPWmTGWsfsSylKMrFmLJIXQINJOkizf7IUokpSiLFmSQos0SNbshqwpIusYyxjbmBkz5/eHX/e32wydM9xzjzmvZ4/zeJhzPudzX/fcMddcn+U4DMMwBAAAYMJdng4AAADcOUgcAACAaSQOAADANBIHAABgGokDAAAwjcQBAACYRuIAAABMI3EAAACmkTgAAADTvDwdgDv45izq6RCQiRxyeDoEZKILR1d6OgRkIu8CJd3af/LpP93Wt7tj9xQqDgAAwLRsWXEAAMCU1BRPR3DHIXEAANiXkerpCO44DFUAAADTqDgAAOwrlYqDVVQcAACAaVQcAAC2ZTDHwTIqDgAAwDQqDgAA+2KOg2VUHAAAgGlUHAAA9sUcB8tIHAAA9sXOkZYxVAEAAEyj4gAAsC+GKiyj4gAAAEyj4gAAsC+WY1pGxQEAAJhGxQEAYFtsOW0dFQcAAGAaFQcAgH0xx8EyEgcAgH0xVGEZQxUAAMA0Kg4AAPtiy2nLqDgAAADTqDgAAOyLOQ6WUXEAAACmUXEAANgXyzEto+IAAABMo+IAALAv5jhYRuIAALAvhiosY6gCAACYRsUBAGBbhsEGUFZRcQAAAKZRcQAA2BeTIy2j4gAAAEyj4gAAsC9WVVhGxQEAAJhGxQEAYF/McbCMxAEAYF+pLMe0iqEKAABgGhUHAIB9MVRhGRUHAABgGhUHAIB9sRzTMioOAADANCoOAAD7Yo6DZVQcAACAaVQcAAD2xRwHy0gcAAD2ReJgGUMVAADANCoOAADbMgy2nLaKigMAADCNigMAwL6Y42AZFQcAAGAaFQcAgH2xAZRlVBwAAIBpVBwAAPbFHAfLSBwAAPbFUIVlDFUAAADTqDgAAOyLoQrLqDgAAADTPJo4XL16VV5eXtq1a5cnwwAA2JWR6r4jm/Jo4uDl5aXw8HClpLBXOAAAdwKPD1UMHDhQAwYM0NmzZz0dCgDAblJT3XdkUx6fHDlhwgTt379fYWFhCg8Pl7+/v8v16OhoD0UGAACu5/HEoVWrVp4OAQBgV9m4MuAuHk8chgwZ4ukQAAB2lY0nMbqLx+c4SNK5c+f06aefusx1iI6O1rFjxzwcGQAA+CePVxx27NihRo0aKSgoSIcOHVL37t2VL18+LVy4UH/99Zc+//xzT4cIAMiuGKqwzOMVh969e6tLly76448/lDNnTuf5hx56SKtXr/ZgZAAAuN/Vq1c1cOBAlShRQn5+fipZsqSGDx+u1H8kNYZhaOjQoQoLC5Ofn5/q16+v3bt3u/STmJioHj16qECBAvL391fLli119OhRlzZxcXGKjIxUUFCQgoKCFBkZqXPnzlmK1+OJw+bNm/Xcc8+lOV+4cGHFxMR4ICIAgG1kgQ2gRo8erY8//lgTJ07U3r17NWbMGL3zzjv64IMPnG3GjBmjcePGaeLEidq8ebNCQ0PVuHFjXbhwwdmmV69eWrhwoebOnau1a9fq4sWLatGihcteSR06dND27dsVFRWlqKgobd++XZGRkZa+ZR5PHHLmzKnz58+nOb9v3z4VLFjQAxFlLbVr19CC+VN18M8tSrxyRC0faepy/dFHm2nR97N07OivSrxyRJUrV0jTx9Kl85R45YjLMfPzDzPrLcCC2rXv1/z5U/Xnn5t15cphPfJIE5frU6aM1ZUrh12OVau+cWlTsmS4vvxyso4c2abY2N2aNesjBQcXyMR3gfRcunRZb4//WI1bd1a1Bo+q43O9tXPvPuf1N94aq4oPPORydOjey6WPr75drC4v91WNxq1V8YGHdP7CRZfrx06c1KBR76npE11UrcGjatbmaU38dKaSk5Mz4y0ig9avX69HH31UzZs3V/HixfXEE0+oSZMm2rJli6Rr1Ybx48frjTfeUOvWrVWxYkXNmDFDly9f1pw5cyRJ8fHx+uyzzzR27Fg1atRIVapU0axZs7Rz50799NNPkqS9e/cqKipKn376qSIiIhQREaEpU6Zo0aJF2rdv3w3ju57HE4dHH31Uw4cPd/6P7XA4dPjwYfXv31+PP/64h6PzPP9cftqxc696vTow/ev+ubRu/WYNHDTqpv189tlsFQuv6jxeerm/O8LFLcqVK5d27tyjV18ddMM2S5asUHh4NefRqlXnf9zvp0WLZskwDDVr9qQaNGgtHx9vzZ8/VQ6HIzPeAm5g8Nvva/3mbRo1uI8WzpykWvdXVfdX/quTp04729SuWV0rv5vtPCaNfdOljytXElW7RnV17/Rkuq9x8K8jMlINDX69h76Z9bH69XxO875ZrPGfTHfnW7uzuXEDqMTERJ0/f97lSExMTBNC7dq1tXz5cv3++++SpF9//VVr167Vww8/LEk6ePCgYmJi1KTJ/36R8PX1Vb169bRu3TpJ0tatW5WcnOzSJiwsTBUrVnS2Wb9+vYKCglSjRg1nm5o1ayooKMjZxgyPT45899139fDDDys4OFgJCQmqV6+eYmJiFBERoREjRng6PI9bsnSllixdecPrc+YskCSFhxe5aT+XLyfo5MlTtzM0uMHSpSu19CaftyQlJibd8LOsVau6wsOLqEaNh3Th/38bffbZPoqJ2akGDR7Qzz+vvd0hw4QriYn6adVaTXh7iKrfW0mS9FK3p/Tz6vX6cuEP6vnsteTPx9tbBfLnu2E/ke0ekyRtit6R7vXaNaurds3qzq+LFi6kg4ePat43P+j1l7vfrrcDk0aNGqVhw4a5nBsyZIiGDh3qcq5fv36Kj4/Xf/7zH+XIkUMpKSkaMWKE2rdvL0nOYfuQkBCX+0JCQvTXX3852/j4+Chv3rxp2vx9f0xMjIKDg9PEGRwcbGlqgMcTh8DAQK1du1Y///yzoqOjlZqaqqpVq6pRo0aeDi1befLJx9S+fWvFxp7SkiUr9daI93Tx4iVPh4UMqFu3pg4fjlZ8/HmtWbNRQ4aM0alTZyRJPj6+MgxDiYlJzvZXrlxRSkqKatW6j8TBQ1KupiglJVW+Pt4u53P6+ih6x/8muG3etkN1mz+pgIDcqn5vJfV8rrPy581zS6998dIlBQYE3FIf2Zob93EYMGCAevfu7XLO19c3Tbsvv/xSs2bN0pw5c3T33Xdr+/bt6tWrl8LCwtS58/8qitdXDQ3D+NdK4vVt0mtvpp9/8nji8LcHH3xQDz74oKfDyJbmzl2oQ4eOKCbmlO6+u5zeerOfKlcur4ebd/R0aLBoyZKVmj//Bx0+fFTFixfTkCGvKSpqriIimispKUmbNkXr0qXLGjFigAYPHi2Hw6ERIwYoR44cCg1N+5sGMoe/fy7dU7G8Pp7+hUqGF1P+fHm0+KdV2rFnn8KLhEm6Vi1o8mAdhYUG69jxGH0wZaa69eiveVMnyMfHJ0Ove/jocc35+jv1odrgEb6+vukmCtd7/fXX1b9/fz355LUhqEqVKumvv/7SqFGj1LlzZ4WGhkq6VjEoVKiQ877Y2FhnFSI0NFRJSUmKi4tzqTrExsaqVq1azjYnT55M8/qnTp1KU824mSyROCxfvlzLly9XbGysy/ITSZo6depN701MTEwzZmQ1e8rupk79wvnnPXv2af/+g9qwfrHuvbeitm/nkeZ3kq+//t755z17fld09A79/vs6PfTQg/r22yidPn1WHTu+oAkTRuqll55Wamqq5s37TtHRO3kKrYeNGtRHg0e9pwdbPaUcOe5S+bKl9XDj+tr7+35J0kON6jnblilZXHf/p6waP95Zq9ZtVuP6D1h+vdhTZ/T8a4PUpEEdPdGy2W17H9lOFtjH4fLly7rrLtcphzly5HD+PCxRooRCQ0O1bNkyValSRZKUlJSkVatWafTo0ZKkatWqydvbW8uWLVPbtm0lSSdOnNCuXbs0ZswYSVJERITi4+O1adMm3X///ZKkjRs3Kj4+3plcmOHxxGHYsGEaPny4qlevrkKFCln+gZ/eGNJdOQLk5RV0O8PMVrZt26mkpCSVLl2CxOEOFxMTq8OHj6l06RLOcz/9tEYVKtRR/vx5dfVqiuLjz+vQoS06dOiIByNFsSJhmv7hO7qccEWXLl1WwQL59NqgUSpcKDTd9gUL5FNYaLAOH7W+g27sqTPq2qOf7qlYXkP79bzV0LO3LJA4PPLIIxoxYoSKFSumu+++W9u2bdO4cePUtWtXSdeGF3r16qWRI0eqTJkyKlOmjEaOHKlcuXKpQ4cOkqSgoCB169ZNr732mvLnz698+fKpT58+qlSpknPov3z58mrWrJm6d++uTz75RJL07LPPqkWLFipXrpzpeD2eOHz88ceaPn265XWkf0tvDKlAwbRLEvE/FSqUk4+Pj2JiYj0dCm5Rvnx5VKRIoXQ/yzNn4iRJ9evXUnBwAS1atCyzw0M6cvnlVC6/nIo/f0HrNm1V7xe7ptvuXPx5xcSeuulkyfScPHVaXXv0V4VypfXWf19N85sssp4PPvhAgwYN0osvvqjY2FiFhYXpueee0+DBg51t+vbtq4SEBL344ouKi4tTjRo1tHTpUgX8Y/7Ke++9Jy8vL7Vt21YJCQlq2LChpk+frhw5cjjbzJ49Wz179nSuvmjZsqUmTpxoKV6PJw5JSUmWSiTXS28MKTsNU/j751KpUsWdXxcvXlSVK1dQXNw5HTlyXHnz5lHRomEKK3RtfKps2VKSpJMnT+nkyVMqWTJcTz7ZSlFRK3TmzFmV/08ZjR49SNu27dS6dZs98ZZwEzf7vM+ePaeBA1/VN9/8qJiYWIWHF9GwYX11+nScvv02ynlPp05t9Ntv+3X69FnVqFFV7747VBMmfKo//vjTA+8If/tl41YZhqHixYro8NHjGvvhZyperIhaNW+iy5cT9OHUWWpcv7YK5s+nYydO6v1PpitvUKAa1f3fv4+nz5zV6TNxOnz0uCTpjwOH5J/LT4VCgxUUGKDYU2f09Mv9VCikoPq8/IzizsU777WagNiGYXg6AgUEBGj8+PEaP378Dds4HA4NHTo0zYqMf8qZM6c++OADl42jrpcvXz7NmjXrFqKVHIbh2e9av379lDt3bg0adON161b55ix62/rytLp1a2rZ0q/SnP985lfq3r23IiPb6NMp49Jcf/OtcXrrrfdUpEghTZs2QXdXKKfcuXPp6NET+vHH5XprxHjFxZ3LhHfgfg5ln0Sxbt2aWrp0XprzM2d+pR49/quvvvpU99xzt/LkCVRMTKxWrVqvYcPe1dGjJ5xt33yzvyIjn1C+fHn0119HNWXKLE2Y8Glmvg23unB0padDyJCo5as1/uNpOnnqtIICA9S4Xm31fK6zAnL760pionr2H67ffj+g8xcvqWD+fLq/amW93L2TCoX8byO8Dz+bpUlTZ6fp+63/9lar5o31zQ/LNHBk2n8PJGnXLz+67b25k3eBkm7tP+HLYf/eKIP82mXPpz97JHH459BCamqqZsyYocqVK6ty5cry9nZdrjRuXPp/CW4mOyUO+HfZKXHAv7tTEwdkjNsThy/c98Pdr737khJP8shQxbZt21y+vvfeeyVJu3YxUQ8AgKzMI4nDihUrPPGyAAC4ygKrKu40Hp9u27VrV5ene/3t0qVLzqUoAAAga/B44jBjxgwlJCSkOZ+QkKDPP//cAxEBAGwjCzxW+07jseWY58+fl2EYMgxDFy5cUM6cOZ3XUlJStHjx4nQfxgEAwG3DUIVlHksc8uTJI4fDIYfDobJly6a57nA40uwICQAAPMtjicOKFStkGIYefPBBzZ8/X/ny/W9zEh8fH4WHhyssLMxT4QEA7CALbAB1p/FY4lCv3rUHuhw8eFCBgYGaOnWq9u7dK4fDoQoVKqhCBbaNBgAgq/H45MhTp06pTJkyeu+993T27FmdPn1a48aNU6lSpRQdHe3p8AAA2VlqqvuObMrjz6p49dVX9cgjj2jKlCny8roWztWrV/XMM8+oV69eWr16tYcjBAAAf/N44rBlyxaXpEGSvLy81LdvX1WvXt2DkQEAsr1sXBlwF48PVQQGBurw4cNpzh85csTlcaEAAMDzPF5xaNeunbp166Z3331XtWrVksPh0Nq1a/X666+rffv2ng4PAJCdZeONmtzF44nDu+++K4fDoU6dOunq1auSJG9vb73wwgt6++23PRwdACA7M1JZjmmVRx6rnZ7Lly/rwIEDMgxDpUuXVq5cuTLcF4/Vthceq20vPFbbXtz9WO3Lk191W9+5nn3PbX17kscrDn/LlSuXKlWq5OkwAAB2wuRIyzw+ORIAANw5skzFAQCATMfkSMuoOAAAANOoOAAA7ItVFZZRcQAAAKZRcQAA2BerKiwjcQAA2BeJg2UMVQAAANOoOAAA7CtrbJ58R6HiAAAATKPiAACwL+Y4WEbFAQAAmEbFAQBgX2wAZRkVBwAAYBoVBwCAffGQK8tIHAAA9sVQhWUMVQAAANOoOAAAbMtgOaZlVBwAAIBpVBwAAPbFHAfLqDgAAADTqDgAAOyL5ZiWUXEAAACmUXEAANgXcxwsI3EAANgXyzEtY6gCAACYRsUBAGBfDFVYRsUBAACYRsUBAGBfLMe0jIoDAAAwjYoDAMC+mONgGRUHAABgGhUHAIBt8Vht60gcAAD2xVCFZQxVAAAA06g4AADsi4qDZVQcAACAaVQcAAD2xQZQllFxAAAAplFxAADYF3McLKPiAAAATKPiAACwLYOKg2UkDgAA+yJxsIyhCgAAYBoVBwCAffGsCsuoOAAAANOoOAAA7Is5DpZRcQAAAKZRcQAA2BcVB8uoOAAAANOoOAAAbMswqDhYRcUBAACYRsUBAGBfzHGwjMQBAGBfJA6WMVQBAABMo+IAALAtno5pXbZMHFLYe9xWqhYo7ekQkIn8wup4OgRkoqtJxzwdAq6TLRMHAABMoeJgGXMcAACAaVQcAAD2xci2ZVQcAACAaVQcAAC2xaoK60gcAAD2ReJgGUMVAADANCoOAAD7YnKkZVQcAACAaVQcAAC2xeRI66g4AAAA00gcAAD2lerGw4Jjx47pqaeeUv78+ZUrVy7de++92rp1q/O6YRgaOnSowsLC5Ofnp/r162v37t0ufSQmJqpHjx4qUKCA/P391bJlSx09etSlTVxcnCIjIxUUFKSgoCBFRkbq3LlzlmIlcQAAwIPi4uL0wAMPyNvbWz/++KP27NmjsWPHKk+ePM42Y8aM0bhx4zRx4kRt3rxZoaGhaty4sS5cuOBs06tXLy1cuFBz587V2rVrdfHiRbVo0UIpKSnONh06dND27dsVFRWlqKgobd++XZGRkZbidRiGke0GeLx8Cns6BGQino5pL9Gn93s6BGQidz8d8+xj9dzWd76Fq0y169+/v3755RetWbMm3euGYSgsLEy9evVSv379JF2rLoSEhGj06NF67rnnFB8fr4IFC2rmzJlq166dJOn48eMqWrSoFi9erKZNm2rv3r2qUKGCNmzYoBo1akiSNmzYoIiICP32228qV66cqXipOAAA7MuNQxWJiYk6f/68y5GYmJgmhO+++07Vq1dXmzZtFBwcrCpVqmjKlCnO6wcPHlRMTIyaNGniPOfr66t69epp3bp1kqStW7cqOTnZpU1YWJgqVqzobLN+/XoFBQU5kwZJqlmzpoKCgpxtzCBxAADADUaNGuWcS/D3MWrUqDTt/vzzT02aNEllypTRkiVL9Pzzz6tnz576/PPPJUkxMTGSpJCQEJf7QkJCnNdiYmLk4+OjvHnz3rRNcHBwmtcPDg52tjGD5ZgAANsy3LgB1IABA9S7d2+Xc76+vmnapaamqnr16ho5cqQkqUqVKtq9e7cmTZqkTp06Ods5HA6X+wzDSHPuete3Sa+9mX7+iYoDAABu4Ovrq8DAQJcjvcShUKFCqlChgsu58uXL6/Dhw5Kk0NBQSUpTFYiNjXVWIUJDQ5WUlKS4uLibtjl58mSa1z916lSaasbNkDgAAOwrCyzHfOCBB7Rv3z6Xc7///rvCw8MlSSVKlFBoaKiWLVvmvJ6UlKRVq1apVq1akqRq1arJ29vbpc2JEye0a9cuZ5uIiAjFx8dr06ZNzjYbN25UfHy8s40ZDFUAAOBBr776qmrVqqWRI0eqbdu22rRpkyZPnqzJkydLuja80KtXL40cOVJlypRRmTJlNHLkSOXKlUsdOnSQJAUFBalbt2567bXXlD9/fuXLl099+vRRpUqV1KhRI0nXqhjNmjVT9+7d9cknn0iSnn32WbVo0cL0igqJxAEAYGPunONg1n333aeFCxdqwIABGj58uEqUKKHx48erY8eOzjZ9+/ZVQkKCXnzxRcXFxalGjRpaunSpAgICnG3ee+89eXl5qW3btkpISFDDhg01ffp05ciRw9lm9uzZ6tmzp3P1RcuWLTVx4kRL8bKPA+547ONgL+zjYC/u3sfh9EPu28ehwI/m9nG401BxAADYVxaoONxpSBwAALaVFYYq7jSsqgAAAKZRcQAA2BYVB+uoOAAAANOoOAAAbIuKg3VUHAAAgGlUHAAA9mWYf7gTrqHiAAAATKPiAACwLeY4WEfiAACwLSOVoQqrGKoAAACmUXEAANgWQxXWUXEAAACmUXEAANiWwXJMy6g4AAAA06g4AABsizkO1lFxAAAAplFxAADYFvs4WEfiAACwLcPwdAR3HoYqAACAaVQcAAC2xVCFdVQcAACAaVQcAAC2RcXBOioOAADANCoOAADbYlWFdVQcAACAaVQcAAC2xRwH60gcAAC2xdMxrWOoAgAAmEbFAQBgWzwd0zoqDgAAwDQqDgAA20pljoNlVBwAAIBpVBwAALbFqgrrqDgAAADTqDgAAGyLDaCs83jFYfXq1bp69Wqa81evXtXq1as9EBEAwC4Mw31HduXxxKFBgwY6e/ZsmvPx8fFq0KCBByICAAA3Ynqo4rvvvjPdacuWLU23NQxDDkfaUtGZM2fk7+9vuh8AAKxiqMI604lDq1atTLVzOBxKSUn513atW7d2tu/SpYt8fX2d11JSUrRjxw7VqlXLbHgAACATmE4cUlNv776cQUFBkq5VHAICAuTn5+e85uPjo5o1a6p79+639TUBAPgnNoCy7pZXVVy5ckU5c+a0fN+0adMkScWLF1efPn0YlgAA4A6QocmRKSkpevPNN1W4cGHlzp1bf/75pyRp0KBB+uyzzyz1NWTIEJIGAIBHGIbDbUd2laHEYcSIEZo+fbrGjBkjHx8f5/lKlSrp008/tdTXyZMnFRkZqbCwMHl5eSlHjhwuBwAAyDoyNFTx+eefa/LkyWrYsKGef/555/nKlSvrt99+s9RXly5ddPjwYQ0aNEiFChVKd4UFAADukJ33W3CXDCUOx44dU+nSpdOcT01NVXJysqW+1q5dqzVr1ujee+/NSCgAACATZWio4u6779aaNWvSnP/qq69UpUoVS30VLVpUBikfAMADUg2H247sKkOJw5AhQ/Tyyy9r9OjRSk1N1YIFC9S9e3eNHDlSgwcPttTX+PHj1b9/fx06dCgjoeD/Pf9cZ/2xb70unj+gjRt+VO0H7vd0SPgXVWpU1tgZo/RD9HxtOr5K9ZrVdrne/bUumrf6c63aH6Wf9izSxC/H6u4q5Z3XCxUJ1abjq9I9Grao72wzcGxffbNhrlYfWKoF6+aoe5+n5eXNY2qymn59X9b6dT8o7sw+HT/6q+Z//ZnKli2Vpt1//lNaCxdM05lTexV3Zp9+WfO9ihYN80DE2QOTI63L0L8ejzzyiL788kuNHDlSDodDgwcPVtWqVfX999+rcePGlvpq166dLl++rFKlSilXrlzy9vZ2uZ7edtRw1aZNS40bO1Qv9/iv1q3frO7PRGrR97NU6Z76OnLkuKfDww3kzOWnP3bv1/dzF2vMZ2+luX74z6N65433deyv48qZ01ftn22jD754V61rddC5s/E6eTxWD93zmMs9rZ56RJEvPql1P2+UJIWXLibHXXdpVL93deTgMZX6Twn9953X5ZcrpyYMn5Qp7xPm1K1TU5MmzdCWrdvl5eWlN4f1048/zFGle+rr8uUESVLJkuFateIbTZv+hYYNf1fx8RdU/j9ldOVKooejh504DA+PE8yYMeOm1zt37my5Ty+fwhkN5460bu33it62Sy/3GOA8t3PHSn33XZTeGPi2ByPLHFULpJ1vc6fZdHyVXu/6hlZFrb1hG//cubTi9x/1UttXtXltdLptZi79VPt2/q63Xhtzw36eeuFJPd7pUT0W0f6W4/aE6NP7PR1CpihQIJ9iju9Ugwdba83aa4ng7FkfKTn5qro83dPD0WWeq0nH3Np/dNFH3dZ31SPfuq1vT7qleuWWLVu0d+9eORwOlS9fXtWqVbPcR0YSA/yPt7e3qlatrNHvfOhyftmyVYqoWd1DUeF28/L2UqunHtGF+Av6fc+BdNv8p1JZlatYRmP++95N+8od4K/z5867I0zcRkFBgZKks3HnJF3bnv/hhxrq3bGTtHjRbN17b0UdOnRYb4+ZqO++W+LBSGE3GZrjcPToUdWpU0f333+/XnnlFfXs2VP33XefateurSNHjlju78CBAxo4cKDat2+v2NhYSVJUVJR2796dkfBspUCBfPLy8lLsydMu52NjTyskNNhDUeF2qd0oQiv/+FFrDy5T++5t9PKTfRR/Nj7dti3bN9efvx/Szi03/ntTODxMbbu21oKZ5h9aB894950hWrt2o3bv3idJCg4uoICA3Or7+ktasnSlHmreQd98G6Wv532qunVqejjaOxeTI63LUOLQtWtXJScna+/evTp79qzOnj2rvXv3yjAMdevWzVJfq1atUqVKlbRx40YtWLBAFy9elCTt2LFDQ4YM+df7ExMTdf78eZfDjqs0rn/PDofDlt+H7GbLL9v0VONn9EzLl7Rh5SaN+mSo8ubPk6adb04fNX2sob774ocb9lUgJL/en/2Oli9aqW/n3LgdPG/C+yNUqWJ5dYx8yXnurruu/XP93fdL9P6EKfr1190a886H+mHxT3r22UhPhQobylDisGbNGk2aNEnlypVznitXrpw++OCDdJdp3kz//v311ltvadmyZS67UDZo0EDr16//1/tHjRqloKAgl8NIvWAphjvZ6dNndfXqVYWEFnQ5X7BgfsWePOWhqHC7XEm4oqOHjmlX9B699doYXb2aopbtm6dp92Dz+srpl1OLv0q/ZF0gJL8mfT1eu7bu1sjX33V32LgF4997U4+0aKJGTdro2LETzvOnT5/9/1/Y/nBp/9tvf6hYUXvN67qdWFVhXYYSh2LFiqW70dPVq1dVuLC1/4F37typxx57LM35ggUL6syZM/96/4ABAxQfH+9yOO4KsBTDnSw5OVnR0TvUqGFdl/ONGtXV+g1bPBQV3MXhkHx8vdOcb9n+Ya1e+ovOpTOMUTC0gD7++n39tvMPDX/1bSpRWdj749/SY60eUuOmbXXokOuwb3JysrZs+TXNEs0yZUrqr8NHMzNM2FyGJkeOGTNGPXr00Icffqhq1arJ4XBoy5YteuWVV/Tuu9Z+m8mTJ49OnDihEiVKuJzftm2bqSTE19dXvr6+Lufstm31e+9P0Yxp72vr1l+1YeNWde/2lIoVLaxPJs/0dGi4Cb9cfipS4n//j4cVLaQyd5fW+XPnFX/2vJ5+JVJrlv6i0yfPKChfoJ7o3ErBhQpq+fcrXfopUrywqtS8R72e6pfmNa5VGt7XyWMnNWH4Ry7DHGdOsdQ5K/lgwki1f7KVWj/eVRcuXFRIyLUqYnz8BV25ckWS9O64Sfpi9iStWbNBK1etU9Mm9dWieWM1bPSEJ0O/o2XnuQjuYno5Zt68eV1+IF+6dElXr16Vl9e13OPvP/v7+1vae6Fv375av369vvrqK5UtW1bR0dE6efKkOnXqpE6dOpma53A9uy3HlK5tANXntRdUqFCwdu3epz59hjqXcGV3d+pyzKoR9+rj+e+nOb/oyx/1dv9xevPDQbq7SnnlyRek+Ljz2vPrb5o6fqb2/ur6PJgX+nfXw080Ucv72qapJjRv20xDxg9Qeu4Pq3f73kwmyq7LMW+07LBrt1f1+cx5zq+7dG6nfn17qEiRUO37/U8NG/6uvv9+aWaFmencvRxzQ1hrt/Vd8/gCt/XtSaYTh3/bb+GfrCyxTE5OVpcuXTR37lwZhiEvLy+lpKSoQ4cOmj59eoaekGnHxMHO7tTEARmTXRMHpI/EIevx+AZQfztw4IC2bdum1NRUValSRWXKlMlwXyQO9kLiYC8kDvbi7sRhXaHH3dZ3rRPz3da3J93yhvUJCQlpJkoGBgZa7qdUqVIqVSrtvuwAACDryFDicOnSJfXr10/z5s1Ld+VDSkrKTe/v3bu36dcaN26c5fgAADAjOy+bdJcMJQ59+/bVihUr9NFHH6lTp0768MMPdezYMX3yySd6++1/fzbCtm3bTL2O3VZHAACQ1WUocfj+++/1+eefq379+uratavq1Kmj0qVLKzw8XLNnz1bHjh1vev+KFSsyFCwAALdTqqcDuANlaAOos2fPOvddCAwMdC6/rF27tlavXn37ogMAAFlKhioOJUuW1KFDhxQeHq4KFSpo3rx5uv/++/X9998rKCjoX+9v3bq1pk+frsDAQLVuffOlMAsWZM/lLAAAzzPEkLhVGUocnn76af3666+qV6+eBgwYoObNm+uDDz7Q1atXTU1mDAoKcs5fMJNoAADgDqlZYkOCO8tt2cfh8OHD2rJliwoWLKhp06Zp6tSppu9NSEhQamqq/P39JUmHDh3SN998o/Lly6tp06YZiod9HOyFfRzshX0c7MXd+zisDGnjtr7rn/zKbX17UobmOFyvWLFiat26tQIDAy3tMClJjz76qGbOvPZMhXPnzqlmzZoaO3asWrVqpUmTJt2O8AAASFeqHG47sqvbkjjciujoaNWpU0eS9PXXXyskJER//fWXPv/8c02YMMHD0QEAgH+65Z0jb9Xly5cVEHDtMdhLly5V69atddddd6lmzZr666+/PBwdACA7Y3KkdR6vOJQuXVrffPONjhw5oiVLlqhJkyaSpNjY2AxtXQ0AANzHUsXh35ZOnjt3znIAgwcPVocOHfTqq6+qYcOGioiIkHSt+lClShXL/QEAYBYbQFlnKXH4t6WTQUFB6tSpk6UAnnjiCdWuXVsnTpzQPffc4zzfsGFDPfbYY5b6AgAA7mUpcZg2bZpbgggNDVVoaKjLufvvv98trwUAwN+Y42CdxydHAgDgKQxVWOfxyZEAAODOQcUBAGBbVByso+IAAABMo+IAALAtJkdaR8UBAACYRsUBAGBbqRQcLKPiAAAATKPiAACwrez8+Gt3IXEAANiW4ekA7kAMVQAAANNIHAAAtpXqxiOjRo0aJYfDoV69ejnPGYahoUOHKiwsTH5+fqpfv752797tcl9iYqJ69OihAgUKyN/fXy1bttTRo0dd2sTFxSkyMlJBQUEKCgpSZGSk5SdbkzgAAJBFbN68WZMnT1blypVdzo8ZM0bjxo3TxIkTtXnzZoWGhqpx48a6cOGCs02vXr20cOFCzZ07V2vXrtXFixfVokULpaSkONt06NBB27dvV1RUlKKiorR9+3ZFRkZaipHEAQBgW6kOh9sOqy5evKiOHTtqypQpyps3r/O8YRgaP3683njjDbVu3VoVK1bUjBkzdPnyZc2ZM0eSFB8fr88++0xjx45Vo0aNVKVKFc2aNUs7d+7UTz/9JEnau3evoqKi9OmnnyoiIkIRERGaMmWKFi1apH379pmOk8QBAAA3SExM1Pnz512OxMTEG7Z/6aWX1Lx5czVq1Mjl/MGDBxUTE6MmTZo4z/n6+qpevXpat26dJGnr1q1KTk52aRMWFqaKFSs626xfv15BQUGqUaOGs03NmjUVFBTkbGMGiQMAwLYMNx6jRo1yziX4+xg1alS6ccydO1fR0dHpXo+JiZEkhYSEuJwPCQlxXouJiZGPj49LpSK9NsHBwWn6Dw4OdrYxg+WYAAC4wYABA9S7d2+Xc76+vmnaHTlyRK+88oqWLl2qnDlz3rA/x3XDH4ZhpDl3vevbpNfeTD//RMUBAGBb7lxV4evrq8DAQJcjvcRh69atio2NVbVq1eTl5SUvLy+tWrVKEyZMkJeXl7PScH1VIDY21nktNDRUSUlJiouLu2mbkydPpnn9U6dOpalm3AyJAwDAtlId7jvMatiwoXbu3Knt27c7j+rVq6tjx47avn27SpYsqdDQUC1btsx5T1JSklatWqVatWpJkqpVqyZvb2+XNidOnNCuXbucbSIiIhQfH69NmzY522zcuFHx8fHONmYwVAEAgAcFBASoYsWKLuf8/f2VP39+5/levXpp5MiRKlOmjMqUKaORI0cqV65c6tChgyQpKChI3bp102uvvab8+fMrX7586tOnjypVquScbFm+fHk1a9ZM3bt31yeffCJJevbZZ9WiRQuVK1fOdLwkDgAA27pTnlXRt29fJSQk6MUXX1RcXJxq1KihpUuXKiAgwNnmvffek5eXl9q2bauEhAQ1bNhQ06dPV44cOZxtZs+erZ49ezpXX7Rs2VITJ060FIvDMIxst1W3l09hT4eATFS1QGlPh4BMFH16v6dDQCa6mnTMrf3PDnvKbX13PD7LbX17EhUHAIBtZbvfnDMBkyMBAIBpVBwAALZlZfUDrqHiAAAATKPiAACwrVt5/LVdkTgAAGyLyZHWMVQBAABMo+IAALAtJkdaR8UBAACYRsUBAGBbTI60jooDAAAwjYoDAMC2qDhYR8UBAACYRsUBAGBbBqsqLCNxAADYFkMV1jFUAQAATKPiAACwLSoO1lFxAAAAplFxAADYFg+5so6KAwAAMI2KAwDAtnjIlXVUHAAAgGlUHAAAtsWqCutIHAAAtkXiYB1DFQAAwDQqDgAA22I5pnVUHAAAgGlUHAAAtsVyTOuoOAAAANOoOAAAbItVFdZRcQAAAKZRcQAA2BarKqyj4gAAAEyj4gAAsK1Uag6WZcvEoW2h+z0dAjLRvBObPB0CMlGBXIGeDgHZCJMjrWOoAgAAmJYtKw4AAJjBQIV1VBwAAIBpVBwAALbFHAfrqDgAAADTqDgAAGyLh1xZR8UBAACYRsUBAGBbbABlHYkDAMC2SBusY6gCAACYRsUBAGBbLMe0jooDAAAwjYoDAMC2mBxpHRUHAABgGhUHAIBtUW+wjooDAAAwjYoDAMC2WFVhHYkDAMC2mBxpHUMVAADANCoOAADbot5gHRUHAABgGhUHAIBtMTnSOioOAADANCoOAADbMpjlYBkVBwAAYBoVBwCAbTHHwToSBwCAbbEBlHUMVQAAANOoOAAAbIt6g3VUHAAAgGlUHAAAtsUcB+uoOAAAANOoOAAAbIvlmNZRcQAAAKZRcQAA2BZbTltH4gAAsC2GKqxjqAIAAJhGxQEAYFsMVVhHxQEAAJhGxQEAYFvMcbCOigMAADCNigMAwLZSDeY4WEXFAQAAmEbFAQBgW9QbrCNxAADYFk/HtI6hCgAAYBoVBwCAbbEBlHVUHAAAgGlUHAAAtsUGUNZRcQAAAKZRcQAA2BarKqyj4gAAgAeNGjVK9913nwICAhQcHKxWrVpp3759Lm0Mw9DQoUMVFhYmPz8/1a9fX7t373Zpk5iYqB49eqhAgQLy9/dXy5YtdfToUZc2cXFxioyMVFBQkIKCghQZGalz585ZipfEAQBgW4Yb/zNr1apVeumll7RhwwYtW7ZMV69eVZMmTXTp0iVnmzFjxmjcuHGaOHGiNm/erNDQUDVu3FgXLlxwtunVq5cWLlyouXPnau3atbp48aJatGihlJQUZ5sOHTpo+/btioqKUlRUlLZv367IyEhL3zOHYWS/jbo7hD/m6RCQiead2OTpEJCJCuQK9HQIyEQx5/a6tf/W4S3d1veCv77L0H2nTp1ScHCwVq1apbp168owDIWFhalXr17q16+fpGvVhZCQEI0ePVrPPfec4uPjVbBgQc2cOVPt2rWTJB0/flxFixbV4sWL1bRpU+3du1cVKlTQhg0bVKNGDUnShg0bFBERod9++03lypUzFR8VBwAAspD4+HhJUr58+SRJBw8eVExMjJo0aeJs4+vrq3r16mndunWSpK1btyo5OdmlTVhYmCpWrOhss379egUFBTmTBkmqWbOmgoKCnG3MyDKTI5cvX67ly5crNjZWqamuC2SmTp3qoagAANmZO4vuiYmJSkxMdDnn6+srX1/fm8bTu3dv1a5dWxUrVpQkxcTESJJCQkJc2oaEhOivv/5ytvHx8VHevHnTtPn7/piYGAUHB6d5zeDgYGcbM7JExWHYsGFq0qSJli9frtOnTysuLs7lAADgTjNq1CjnJMS/j1GjRt30npdfflk7duzQF198keaaw+Fw+dowjDTnrnd9m/Tam+nnn7JExeHjjz/W9OnTLU/QAADgVrhzOeaAAQPUu3dvl3M3qzb06NFD3333nVavXq0iRYo4z4eGhkq6VjEoVKiQ83xsbKyzChEaGqqkpCTFxcW5VB1iY2NVq1YtZ5uTJ0+med1Tp06lqWbcTJaoOCQlJTnfGAAA2YGvr68CAwNdjvQSB8Mw9PLLL2vBggX6+eefVaJECZfrJUqUUGhoqJYtW+Y8l5SUpFWrVjl/dlarVk3e3t4ubU6cOKFdu3Y520RERCg+Pl6bNv1vQvnGjRsVHx9v6WdwlkgcnnnmGc2ZM8fTYQAAbCbVjYdZL730kmbNmqU5c+YoICBAMTExiomJUUJCgqRrwwu9evXSyJEjtXDhQu3atUtdunRRrly51KFDB0lSUFCQunXrptdee03Lly/Xtm3b9NRTT6lSpUpq1KiRJKl8+fJq1qyZunfvrg0bNmjDhg3q3r27WrRoYXpFhZRFhiquXLmiyZMn66efflLlypXl7e3tcn3cuHEeigwAAPeaNGmSJKl+/fou56dNm6YuXbpIkvr27auEhAS9+OKLiouLU40aNbR06VIFBAQ427/33nvy8vJS27ZtlZCQoIYNG2r69OnKkSOHs83s2bPVs2dP5+qLli1bauLEiZbizRL7ODRo0OCG1xwOh37++WdL/bGPg72wj4O9sI+Dvbh7H4cWxZq7re9Fh39wW9+elCUqDitWrPB0CAAAG+JZFdZliTkOAADgzuCxikPr1q01ffp0BQYGqnXr1jdtu2DBgkyKCgBgJ1lgtP6O47HEISgoyLnhRFBQkKfCAAAAFngscZg2bVq6fwYAILNYWTaJa7LEHIdhw4bpwIEDng4DAAD8iyyROMyfP19ly5ZVzZo1NXHiRJ06dcrTIQEAbMBw43/ZVZZIHHbs2KEdO3bowQcf1Lhx41S4cGE9/PDDmjNnji5fvuzp8AAAwP/LEhtAXe+XX37RnDlz9NVXX+nKlSs6f/68pfvv1A2gWr7YWvc1q6mwUkWUdCVJf2z9TV+8/blO/HlckpTDK4fa9OmgextUU3CxECVcuKxda3/VF2/P1LnY/z1F9MH2jVXr0boqXrGkcgXk0jOVOury+f8lYAWKFNRjPdvq7lqVlKdgHsWdjNPahav0zcSvlZJ8NdPf962y0wZQ+3/foOLFi6Y5/9Gk6er5yhseiCjzZZcNoPr0f0l9+r/sci725ClVLldX0o03Pho+6B199MFUFS0Wps07lqfbpnvnXvr+2yW3N2APcfcGUI2KNnVb3z8dyR6fwfWyxAZQ1/P395efn598fHx04cIFT4eTacrXuFvLPv9RB37drxxeOdT29Y7qP3OI+jbqqcSERPn4+apExZJaOGGeDu89JP+g3Ioc3FV9PvuvBj7yurMfHz9f/bpqm35dtU3t+6d94mhYqSK6y+HQZwMm6eShGBUpV0zd335Rvrl8NWfEjMx8y7CoZq2HXbaPrXj3f7Qkaq7mz1/kwaiQUb/t+UNtWnV1fp2akuL8c6WydVzaNmxcR+M+eEuLvlsqSTp2NCZNm8gubfVSz65a/tMaN0YNu8syicPBgwc1Z84czZ49W7///rvq1q2roUOHqk2bNp4OLdOM7vymy9ef9PlAn2yboRKVSum3TXuUcOGyRj01zKXNjCGf6q3v31H+sAI6c/y0JClq6rUfIuVr3p3u6+xYtU07Vm1zfh175KR+mPKtGj3VlMQhizt9+qzL131ff1n79x/UqtXrPRQRbsXVlKs6FXs63WvXn2/68IP6Zc1GHf7rqCQpNTU1TZuHWjTUtwujdPkSQ7xmZcGie5aXJRKHiIgIbdq0SZUqVdLTTz+tDh06qHDhwp4Oy+NyBeSSJF08d/GmbVJTU3X5/KVbei2/gFw3fR1kPd7e3urYobXGvz/Z06Egg0qWDNf2vauUlJSk6C07NHL4e87E4J8KFMyvRk3qqecLA27YV+V7KqhS5Qoa0OfNG7ZBWmw5bV2WSBwaNGigTz/9VHffnf5vyHb11KCn9dumPTr6++F0r3v7euvJ/pFa9+0aJVxMyPDrBBcLVdPOD2vWiOkZ7gOZ79FHmylPnkDN+Hyep0NBBkRv2aEeL/TXgf2HVLBgAb36+vNatHSO6tVsqbi4cy5t27VvpYsXL2nx98tu2F+HyCf0+2/7tWXTdvcGDtvz+KqK5ORkzZ0717mLpFWJiYk6f/68y5FipPz7jVlclzefVbH/FNfEHuk/UjyHVw71+OA1Oe5yaNrATzL8OnmC86r/54O0cfE6rZz7U4b7Qebr2uVJRS1ZoRMnTno6FGTAzz+t0Q/fLdNve/7QmlXr9VTb5yVJbTs8mqbtk0+11oKvFikxMSndvnLm9NVjbZprzqz5bo05O2I5pnUeTxy8vb2VmJiY4cRh1KhRCgoKcjn2xP9+m6PMXJ2HPaNqje7TW+0H6WzMmTTXc3jlUM8P+6hg0WCN6jgsw9WGPMF5NXDum/ojep8+7T/pVsNGJipWrLAaNqyjz6bO8XQouE0uX07Q3j1/qGTJ4i7na0RUU5myJTX7869veG+LR5vKzy+nvvriWzdHCWSBxEGSevToodGjR+vqVetLAQcMGKD4+HiXo0JQWTdEmTm6DO+u+5rV1Ij2g3XqSGya638nDaElwjSy41BdPJexVSd5Q/Jp0Jdv6dCuP/Vxn4lMELrDdOncTrGxp7V4cfrL8XDn8fHxVpmyJXXypOsGeB0iH9ev23Zpz659N7y3Q+TjWvrjCp05E3fDNkhfqmG47ciussQch40bN2r58uVaunSpKlWqJH9/f5frN3s6pq+vr3x9fV3O5XDkuEHrrO3pt55VrZZ1Nbb7KCVcSlBQwTySpMvnLys5MUl35bhLr0zqqxIVS+qdriN0V467nG0unrvo3IMhqGAe5SmYRyHFC0mSipYL15VLCTp97LQuxV9UnuC8GvTlmzp9/LRmj5iuwPz/Wxcff+pcZr5lZIDD4VDnTu00c9ZXSkm584fl7GrIm69radRKHTt6XPkL5Nerrz+vgIDcmvfFN842uQP89cijTTV04Jgb9lO8RDHVrFVdHds8lwlRA1kkcciTJ48ef/xxT4fhcY0jH5IkDZ73lsv5j1+boNVfr1C+QvlVvcn9kqS3o95zafNmu4Hau2G3JKlRx6Z6/NUnndeGfD3SpZ/Kde9VaIkwhZYI04ebPnPp507dPMtOGjWso/DwIpo2/UtPh4JbUCgsVJM+fVf58ufRmdNx2rrlVzVv/KSOHjnubNOq9cOSw6GF83+4YT/tn2qtE8dPauXPv2RG2NlO9q0LuE+W3DnyVvHDz17stHMkss/OkTDH3TtH1inc0G19rzmWPYcSs0TFAQAAT2AfB+uyTOLw9ddfa968eTp8+LCSklyXHEVHR3soKgBAdkbiYF2WWFUxYcIEPf300woODta2bdt0//33K3/+/Przzz/10EMPeTo8AADw/7JE4vDRRx9p8uTJmjhxonx8fNS3b18tW7ZMPXv2VHx8vKfDAwBkU4ZhuO3IrrJE4nD48GHVqlVLkuTn5+d8ImZkZKS++OILT4YGAAD+IUskDqGhoTpz5toOieHh4dqwYYOka0/MzM5ZGwDAs1JluO3IrrJE4vDggw/q+++/lyR169ZNr776qho3bqx27drpscdYWgkAQFaRJVZVTJ48WampqZKk559/Xvnz59eaNWv0yCOP6IUXXvBwdACA7Co7P4zKXbJE4nDXXXddex59dLRiY2Pl6+urRo0aSZKioqL0yCOPeDhCAAAgZZHEISoqSpGRkc55Dv/kcDjYjx8A4BbMo7MuS8xxePnll9W2bVudOHFCqampLgdJAwDAXZgcaV2WSBxiY2PVu3dvhYSEeDoUAABwE1kicXjiiSe0cuVKT4cBALAZNoCyLkvMcZg4caLatGmjNWvWqFKlSvL29na53rNnTw9FBgAA/ilLJA5z5szRkiVL5Ofnp5UrV8rhcDivORwOEgcAgFtk57kI7pIlEoeBAwdq+PDh6t+/v+66K0uMngAAgHRkicQhKSlJ7dq1I2kAAGQqNoCyLkv8pO7cubO+/PJLT4cBAAD+RZaoOKSkpGjMmDFasmSJKleunGZy5Lhx4zwUGQAgO0vNxqsf3CVLJA47d+5UlSpVJEm7du1yufbPiZIAANxODFVYlyUShxUrVng6BAAAYEKWSBwAAPAEhiqsyxKTIwEAwJ2BigMAwLaY42AdFQcAAGAaFQcAgG0xx8E6Kg4AAMA0Kg4AANtijoN1JA4AANtiqMI6hioAAIBpVBwAALbFUIV1VBwAAIBpVBwAALZlGKmeDuGOQ8UBAACYRsUBAGBbqcxxsIyKAwAAMI2KAwDAtgz2cbCMxAEAYFsMVVjHUAUAADCNigMAwLYYqrCOigMAADCNigMAwLZ4yJV1VBwAAIBpVBwAALbFQ66so+IAAABMo+IAALAtVlVYR+IAALAtNoCyjqEKAABgGhUHAIBtMVRhHRUHAABgGhUHAIBtsQGUdVQcAACAaVQcAAC2xRwH66g4AAAA06g4AABsi30crCNxAADYFkMV1jFUAQAATKPiAACwLZZjWkfFAQAAmEbFAQBgWwaTIy2j4gAAAEyj4gAAsC3mOFhHxQEAAJhGxQEAYFvs42AdFQcAAGAaFQcAgG2xqsI6EgcAgG0xVGEdQxUAAMA0EgcAgG0ZhuG2w6qPPvpIJUqUUM6cOVWtWjWtWbPGDe/41pE4AADgYV9++aV69eqlN954Q9u2bVOdOnX00EMP6fDhw54OLQ0SBwCAbRluPKwYN26cunXrpmeeeUbly5fX+PHjVbRoUU2aNOkW3+HtR+IAAIAbJCYm6vz58y5HYmJimnZJSUnaunWrmjRp4nK+SZMmWrduXWaFa1q2XFUx56+Fng4h0yUmJmrUqFEaMGCAfH19PR1Opprj6QA8wM6ftx3xebvP1aRjbut76NChGjZsmMu5IUOGaOjQoS7nTp8+rZSUFIWEhLicDwkJUUxMjNviyyiHwVqUbOH8+fMKCgpSfHy8AgMDPR0O3IzP2174vO9MiYmJaSoMvr6+aZK/48ePq3Dhwlq3bp0iIiKc50eMGKGZM2fqt99+y5R4zcqWFQcAADwtvSQhPQUKFFCOHDnSVBdiY2PTVCGyAuY4AADgQT4+PqpWrZqWLVvmcn7ZsmWqVauWh6K6MSoOAAB4WO/evRUZGanq1asrIiJCkydP1uHDh/X88897OrQ0SByyCV9fXw0ZMoSJUzbB520vfN7ZX7t27XTmzBkNHz5cJ06cUMWKFbV48WKFh4d7OrQ0mBwJAABMY44DAAAwjcQBAACYRuIAAABMI3GwsS5duqhVq1aeDgP/cP1nUr9+ffXq1ctj8cCz+PyRFbGqwsbef//9DD36Fe6TGZ9Jly5ddO7cOX3zzTdufR2Yt3LlSjVo0EBxcXHKkyePp8MBborEIRtKSkqSj4/Pv7YLCgrKhGhgBZ8J3C05OVne3t6eDgN3MIYqMln9+vXVo0cP9erVS3nz5lVISIgmT56sS5cu6emnn1ZAQIBKlSqlH3/8UZKUkpKibt26qUSJEvLz81O5cuX0/vvvu/T5d3l71KhRCgsLU9myZTVgwADVrFkzzetXrlxZQ4YMcbnvn7H17NlTffv2Vb58+RQaGprmYSy4Pb7++mtVqlRJfn5+yp8/vxo1aqRLly796/BRUlKS+vbtq8KFC8vf3181atTQypUrndenT5+uPHnyaMmSJSpfvrxy586tZs2a6cSJE5KuPXRnxowZ+vbbb+VwOORwOFzuh/skJiaqZ8+eCg4OVs6cOVW7dm1t3rxZhw4dUoMGDSRJefPmlcPhUJcuXZz3paam3vTvZHx8vJ599lkFBwcrMDBQDz74oH799Vfn9aFDh+ree+/V1KlTVbJkSfn6+lJpxC0hcfCAGTNmqECBAtq0aZN69OihF154QW3atFGtWrUUHR2tpk2bKjIyUpcvX1ZqaqqKFCmiefPmac+ePRo8eLD++9//at68eS59Ll++XHv37tWyZcu0aNEidezYURs3btSBAwecbXbv3q2dO3eqY8eON43N399fGzdu1JgxYzR8+PA026Di1pw4cULt27dX165dtXfvXq1cuVKtW7c29Y/5008/rV9++UVz587Vjh071KZNGzVr1kx//PGHs83ly5f17rvvaubMmVq9erUOHz6sPn36SJL69Omjtm3bOpOJEydOZMktbbOjvn37av78+ZoxY4aio6NVunRpNW3aVAEBAZo/f74kad++fTpx4oTLLwc3+ztpGIaaN2+umJgYLV68WFu3blXVqlXVsGFDnT171tnH/v37NW/ePM2fP1/bt2/P1PeNbMhApqpXr55Ru3Zt59dXr141/P39jcjISOe5EydOGJKM9evXp9vHiy++aDz++OPOrzt37myEhIQYiYmJLu0qV65sDB8+3Pn1gAEDjPvuu8/lvkcfffSGsRmGYdx3331Gv379rL1J3NTWrVsNScahQ4fSXEvvM3nllVcMwzCM/fv3Gw6Hwzh27JjLPQ0bNjQGDBhgGIZhTJs2zZBk7N+/33n9ww8/NEJCQm74GnC/ixcvGt7e3sbs2bOd55KSkoywsDBjzJgxxooVKwxJRlxcnMt9//Z3cvny5UZgYKBx5coVlzalSpUyPvnkE8MwDGPIkCGGt7e3ERsb64Z3Bjui4uABlStXdv45R44cyp8/vypVquQ89/fT0GJjYyVJH3/8sapXr66CBQsqd+7cmjJlig4fPuzSZ6VKldLMa+jYsaNmz54t6dpvJl988cVNqw3XxyZJhQoVcsaB2+Oee+5Rw4YNValSJbVp00ZTpkxRXFzcv94XHR0twzBUtmxZ5c6d23msWrXKpbKUK1culSpVyvk1n6HnHThwQMnJyXrggQec57y9vXX//fdr7969N733Zn8nt27dqosXLyp//vwu/08cPHjQ5f+J8PBwFSxY8Da+I9gZkyM94PqJSQ6Hw+Wcw+GQdG1sc968eXr11Vc1duxYRUREKCAgQO+88442btzo0oe/v3+a1+nQoYP69++v6OhoJSQk6MiRI3ryySctx5aammrp/eHmcuTIoWXLlmndunVaunSpPvjgA73xxhtpPtPrpaamKkeOHNq6daty5Mjhci137tzOP6f3GRqMaXvU39//v/9u//P89eeud7O/k6mpqSpUqFC681T+uTojvX8fgIwiccji1qxZo1q1aunFF190nvvnbxI3U6RIEdWtW1ezZ89WQkKCGjVqlCWf7W5HDodDDzzwgB544AENHjxY4eHhWrhw4U3vqVKlilJSUhQbG6s6depk+LV9fHyUkpKS4fthXenSpeXj46O1a9eqQ4cOkq6tbtiyZYt69erlrBZa/VyqVq2qmJgYeXl5qXjx4rc7bCBdDFVkcaVLl9aWLVu0ZMkS/f777xo0aJA2b95s+v6OHTtq7ty5+uqrr/TUU0+5MVKYtXHjRo0cOVJbtmzR4cOHtWDBAp06dUrly5e/6X1ly5ZVx44d1alTJy1YsEAHDx7U5s2bNXr0aC1evNj06xcvXlw7duzQvn37dPr0aSUnJ9/qW8K/8Pf31wsvvKDXX39dUVFR2rNnj7p3767Lly+rW7duCg8Pl8Ph0KJFi3Tq1CldvHjRVL+NGjVSRESEWrVqpSVLlujQoUNat26dBg4cqC1btrj5XcGuSByyuOeff16tW7dWu3btVKNGDZ05c8al+vBv2rRpozNnzujy5cvsEplFBAYGavXq1Xr44YdVtmxZDRw4UGPHjtVDDz30r/dOmzZNnTp10muvvaZy5cqpZcuW2rhxo4oWLWr69bt3765y5co558388ssvt/J2YNLbb7+txx9/XJGRkapatar279+vJUuWKG/evCpcuLCGDRum/v37KyQkRC+//LKpPh0OhxYvXqy6deuqa9euKlu2rJ588kkdOnSI6iLchsdqAwAA06g4AAAA00gcAACAaSQOAADANBIHAABgGokDAAAwjcQBAACYRuIAAABMI3EAsrChQ4fq3nvvdX7dpUuXW97I63b0AcC+SByADOjSpYscDofzAWUlS5ZUnz59dOnSJbe+7vvvv6/p06ebanvo0CE5HA5t3749w30AwPV4yBWQQc2aNdO0adOUnJysNWvW6JlnntGlS5c0adIkl3bJyclpnnCYUUFBQVmiDwD2RcUByCBfX1+FhoaqaNGi6tChgzp27KhvvvnGObwwdepUlSxZUr6+vjIMQ/Hx8Xr22WcVHByswMBAPfjgg/r1119d+nz77bcVEhKigIAAdevWTVeuXHG5fv0wQ2pqqkaPHq3SpUvL19dXxYoV04gRIyRJJUqUkHTtqZoOh0P169dPt4/ExET17NlTwcHBypkzp2rXru3yILWVK1fK4XBo+fLlql69unLlyqVatWpp3759t/G7CeBOQeIA3CZ+fn7OJ03u379f8+bN0/z5851DBc2bN1dMTIwWL16srVu3qmrVqmrYsKHOnj0rSZo3b56GDBmiESNGaMuWLSpUqJA++uijm77mgAEDNHr0aA0aNEh79uzRnDlznA832rRpkyTpp59+0okTJ7RgwYJ0++jbt6/mz5+vGTNmKDo6WqVLl1bTpk2dcf3tjTfe0NixY7VlyxZ5eXmpa9euGf5eAbiDGQAs69y5s/Hoo486v964caORP39+o23btsaQIUMMb29vIzY21nl9+fLlRmBgoHHlyhWXfkqVKmV88sknhmEYRkREhPH888+7XK9Ro4Zxzz33pPu658+fN3x9fY0pU6akG+PBgwcNSca2bdtuGPvFixcNb29vY/bs2c7rSUlJRlhYmDFmzBjDMAxjxYoVhiTjp59+crb54YcfDElGQkLCjb9JALIlKg5ABi1atEi5c+dWzpw5FRERobp16+qDDz6QJIWHh6tgwYLOtlu3btXFixeVP39+5c6d23kcPHhQBw4ckCTt3btXERERLq9x/df/tHfvXiUmJqphw4YZfg8HDhxQcnKyHnjgAec5b29v3X///dq7d69L28qVKzv/XKhQIUlSbGxshl8bwJ2JyZFABjVo0ECTJk2St7e3wsLCXCZA+vv7u7RNTU1VoUKFtHLlyjT95MmTJ0Ov7+fnl6H7/skwDEmSw+FIc/76c/98f39fS01NveUYANxZqDgAGeTv76/SpUsrPDz8X1dNVK1aVTExMfLy8lLp0qVdjgIFCkiSypcvrw0bNrjcd/3X/1SmTBn5+flp+fLl6V738fGRJKWkpNywj9KlS8vHx0dr1651nktOTtaWLVtUvnz5m74nAPZExQHIBI0aNVJERIRatWql0aNHq1y5cjp+/LgWL16sVq1aqXr16nrllVfUuXNnVa9eXbVr19bs2bO1e/dulSxZMt0+c+bMqX79+qlv377y8fHRAw88oFOnTmn37t3q1q2bgoOD5efnp6ioKBUpUkQ5c+ZMsxTT399fL7zwgl5//XXly5dPxYoV05gxY3T58mV169YtM741AO4wJA5AJnA4HFq8eLHeeOMNde3aVadOnVJoaKjq1q3rXAXRrl07HThwQP369dOVK1f0+OOP64UXXtCSJUtu2O+gQYPk5eWlwYMH6/jx4ypUqJCef/55SZKXl5cmTJig4cOHa/DgwapTp066QyVvv/22UlNTFRkZqQsXLqh69epasmSJ8ubN65bvBYA7m8P4e5ATAADgXzDHAQAAmEbiAAAATCNxAAAAppE4AAAA00gcAACAaSQOAADANBIHAABgGokDAAAwjcQBAACYRuIAAABMI3EAAACmkTgAAADT/g+ou2CVVevbhQAAAABJRU5ErkJggg==", + "text/plain": [ + "
" + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], "source": [ "label_list = ['marvin', 'silent', 'other']\n", "confusion_mtx = tf.math.confusion_matrix(labels, predictions)\n", @@ -493,7 +751,7 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 46, "id": "92cfe55f-389f-4256-b6f0-c5cc83d2a7cc", "metadata": {}, "outputs": [], @@ -504,7 +762,7 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 47, "id": "47dfb8a9-f544-482c-a90b-11d9e1fee189", "metadata": {}, "outputs": [], @@ -533,10 +791,19 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 48, "id": "3102a02f-7b4b-4643-8c54-795784b9def3", "metadata": {}, - "outputs": [], + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "Input shape = [None, 1, 40]\n", + "Apple Silicon platform detected. Using legacy adam as standard Keras Adam is slow on this processor.\n" + ] + } + ], "source": [ "pretrained_model_uses_qat = hasattr(model.layers[1], \"quantizer\")\n", "Flags.variable_length=True\n", @@ -558,21 +825,39 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 49, "id": "89f58ec7-8d4c-4ecf-aeb5-fa782ca47941", "metadata": {}, - "outputs": [], + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "min/max of long wav = -32768 / 24076\n" + ] + } + ], "source": [ - "wav_sampling_freq, long_wav = wavfile.read(\"long_wav.wav\")\n", + "test_config_file = '../../runner/sww_data_dir/sww_long_test.json' \n", + "# test_config_file = '../../runner/sww_data_dir/sww_short_test.json'\n", + "# test_config_file = '../../runner/sww_data_dir/sww_5s_dbg.json' \n", + "\n", + "with open(test_config_file, 'r') as fpi:\n", + " stream_test_config = json.load(fpi)\n", + "\n", + "ww_windows = stream_test_config[0]['detection_windows']\n", + "\n", + "wav_file_path = os.path.join(\"../../runner/sd_card/\", stream_test_config[0]['wav_file'], )\n", + "wav_sampling_freq, long_wav = wavfile.read(wav_file_path)\n", + "# wav_sampling_freq, long_wav = wavfile.read(\"../../runner/sd_card/med_5m.wav\")\n", "assert wav_sampling_freq == samp_freq\n", "t = np.arange(len(long_wav))/samp_freq\n", "print(f\"min/max of long wav = {np.min(long_wav)} / {np.max(long_wav)}\")\n", "long_wav = long_wav / 2**15 # scale into [-1.0, +1.0] range\n", "\n", - "ww_windows_file = 'long_wav_ww_windows.json' # start/stop points of wakewords in a list\n", - "with open(ww_windows_file, 'r') as fpi:\n", - " ww_windows = json.load(fpi)\n", - " \n", + "if len(long_wav.shape)==2:\n", + " long_wav = long_wav[:,0]\n", + "\n", "# construct waveform that shows when wakeword is present\n", "ww_present = np.zeros(len(long_wav))\n", "for t_start, t_stop in ww_windows:\n", @@ -583,12 +868,12 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 50, "id": "3aee69ba-3130-4235-b1d2-ab751a25b42b", "metadata": {}, "outputs": [], "source": [ - "## build a feature extractor that can operate on longer waveforms.\n", + "## build a feature extractor that can operate on longer waveforms\n", "## this one can operate on waveforms up to len(long_wav)\n", "data_config_long = get_dataset.get_data_config(Flags, 'training')\n", "\n", @@ -599,8 +884,6 @@ "t = np.arange(len(long_wav))/samp_freq\n", "\n", "feature_extractor_long = get_dataset.get_lfbe_func(data_config_long)\n", - "# the feature extractor needs a label (in 1-hot format), but it doesn't matter what it is\n", - "# long_spec = feature_extractor_long({'audio':long_wav, 'label':[0.0, 0.0, 0.0]})['audio'].numpy()\n", "\n", "# long_spec = feature_extractor_long(np.expand_dims(long_wav, 0)).numpy()\n", "long_spec = feature_extractor_long(long_wav).numpy()" @@ -608,25 +891,42 @@ }, { "cell_type": "code", - "execution_count": null, - "id": "81014678-1bbe-4b59-adf0-70dea14dcd4f", - "metadata": {}, - "outputs": [], - "source": [ - "long_spec_from_file = np.load(\"long_specgram.npz\")[\"specgram\"]\n", - "specgrams_match = np.allclose(long_spec, long_spec_from_file, atol=1e-6)\n", - "\n", - "print(f\"Does spectrogram loaded from file match the one we created?: {specgrams_match}\")" - ] - }, - { - "cell_type": "code", - "execution_count": null, + "execution_count": 51, "id": "97becd93-f5c3-4998-af50-f43bd6fd5f38", "metadata": {}, - "outputs": [], + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "5 false detections.\n", + "44 true detections.\n", + "6 false rejections.\n" + ] + }, + { + "name": "stderr", + "output_type": "stream", + "text": [ + "/Users/jeremy/miniforge3/envs/jh_main/lib/python3.11/site-packages/IPython/core/events.py:82: UserWarning: Creating legend with loc=\"best\" can be slow with large amounts of data.\n", + " func(*args, **kwargs)\n", + "/Users/jeremy/miniforge3/envs/jh_main/lib/python3.11/site-packages/IPython/core/pylabtools.py:170: UserWarning: Creating legend with loc=\"best\" can be slow with large amounts of data.\n", + " fig.canvas.print_figure(bytes_io, **kw)\n" + ] + }, + { + "data": { + "image/png": "iVBORw0KGgoAAAANSUhEUgAAAjAAAAGdCAYAAAAMm0nCAAAAOnRFWHRTb2Z0d2FyZQBNYXRwbG90bGliIHZlcnNpb24zLjEwLjAsIGh0dHBzOi8vbWF0cGxvdGxpYi5vcmcvlHJYcgAAAAlwSFlzAAAPYQAAD2EBqD+naQAAUv5JREFUeJzt3XtcVHX+P/DXAMNwkRlFRSDxuqbiLW8ppogpeE9rTS1X0W3X2lAJt1TMS2jefmWiZXZZg8xMVxG1wlYsAU3UUiFLstwIDSGzkPHCZWA+vz9YzpeBAeYMw8DB17PHPOh85vP5nPfnPUfmzZkzMyohhAARERGRgjg0dABEREREcrGAISIiIsVhAUNERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxnBo6AFsxGo24du0aPDw8oFKpGjocIiIisoAQArdu3YKvry8cHCw/r9JkCphr167Bz8+vocMgIiIiK1y9ehVt27a1uH+TKWA8PDwAlCVAq9VaPY/BYMCRI0cQEhICtVptq/CoBsy5fTHf9sec2x9zbn/W5lyv18PPz096HrdUkylgyl820mq1dS5g3NzcoNVqedDbCXNuX8y3/THn9sec219dcy738g9exEtERESKwwKGiIiIFIcFDBERESlOk7kGhoiIqhJCoKSkBKWlpQ0dil0ZDAY4OTmhsLDwnlt7Q6ku546OjnBycrL5R5ywgCEiaqKKi4uRk5ODu3fvNnQodieEgLe3N65evcrPBrOTmnLu5uYGHx8fODs722x/LGCIiJogo9GIzMxMODo6wtfXF87OzvfUE7nRaMTt27fRrFkzWR+ORtYzl3MhBIqLi/Hbb78hMzMTXbp0sdnjwQKGiKgJKi4uhtFohJ+fH9zc3Bo6HLszGo0oLi6Gi4sLCxg7qS7nrq6uUKvVyMrKku63BT6qRERNGJ+8qTGoj+OQZ2DuUaWlwPHjQE4O4OMDDBsGODo2TAxXr6qQldUSo0cD9fF5U41hrUqKS46msAZL3UtrJVICWSXRtm3b0Lt3b+nTbgMCAnD48OEaxyQnJ6N///5wcXFBp06d8NZbb1XpExcXB39/f2g0Gvj7+yM+Pl7eKkiW/fuBDh2AESOAJ58s+9mhQ1l7Q8Qwa5YTli8fij/9ycnmMTSGtSopLjmawhosdS+tlUgxhAyHDh0Sn376qbh06ZK4dOmSWLp0qVCr1eLbb7812/+nn34Sbm5uIjw8XFy8eFG8++67Qq1Wi3379kl9Tp48KRwdHcXatWtFRkaGWLt2rXBychKnTp2SE5rIz88XAER+fr6scZUVFxeLAwcOiOLi4jrN01jFxQmhUgkBmN5UqrJbXFxDxmC0aQyNYa2NMS5bHOMNvQZ7ssVaG+L3SkFBgbh48aIoKCiw2z4bWkxMjNDpdEIIIUpLS0VeXp4oLS1t2KAagczMTAFAnD9/vl73U1POazoerX3+llXAmNOiRQvxr3/9y+x9ixYtEt26dTNpe/rpp8XgwYOl7alTp4oxY8aY9Bk9erSYPn26rDhYwNSupESItm2r/iKu+AvZz6+sn9JjaAxrbaxx1fUYbwxrsBdbrVWRBczKlUKsWmX+vlWryu6vB6GhoQJAlduPP/5Y69j6LmBiYmKkeBwcHETz5s3Fgw8+KKKiosTNmzdlzXXs2DEBQOTl5dksPiHK8jdp0iSTtpKSEpGTkyMMBoNN91WZvQsYq6+BKS0txd69e3Hnzh0EBASY7ZOamoqQkBCTttGjR2P79u0wGAxQq9VITU1FRERElT7R0dE17r+oqAhFRUXStl6vB1D2QToGg8GKFUEaX/FnU5KcrMIvv1T/kAsBXL0KHDtWguHDhaJjaAxrbaxx1fUYbwxrsBdbrbUhfq8YDAYIIWA0GmE0GuVP4OAAhxUrYBQCWLbs/9pffhkOK1fCGBUFWDNvLYQQGD16NN577z2T9tatW9e6jvL7jUYjhBDSfFatv5r5tVotMjIyIITAzZs3cfLkSWzYsAExMTE4fvw4fH19LZ6r/Ket4gPK1lt5zSqVCl5eXib7rQ815bz8MTEYDHCsdPGYtf8uZBcwFy5cQEBAAAoLC9GsWTPEx8fD39/fbN/c3Fy0adPGpK1NmzYoKSnBjRs34OPjU22f3NzcGuNYt24doqKiqrQfOXLEJm8ZTExMrPMcjU1Kyn0ABtTa7/DhNNy5k63oGBrDWs1pTHFZe4w3pjXUN1uv1Z6/V5ycnODt7Y3bt2+juLhY/gQLFkBTVATXlStRUFSEohdegOaVV+C6di0Kli5F0YIFwP/+cLSl8ie4yr/H79y5g61bt+LDDz9EVlYWmjdvjjFjxiAqKgrNmjUDABQWFkIIIf1Be+HCBSxduhRpaWlQqVTo1KkTNm3ahL59+wIATp8+jaioKJw/fx6enp6YMGECVqxYAXd3d7OxFRYWAoAUm7u7Ox5//HEEBQUhICAACxcuxDvvvAOg7El8y5YtiImJwa+//orOnTvjhRdewKRJk3DlyhWMHDkSANCyZUsAwBNPPIE333yzxnHlMjIysHLlSpw6dQpCCPTs2RNvvvkm9uzZgx07dgCAVCR8/PHHaNeuHfr06YOUlBT06tULAPDll19ixYoV+Pbbb9GiRQtMnz4dy5Ytg5NTWVkwYcIE9OjRAxqNBh988AGcnZ0xZ84cLFmyRIpj/fr12LlzJ3777Td4enrikUcewYYNG3Dr1q0quSsuLkZBQQFSUlJQUlJicp+1H7Qou4Dp2rUr0tLScPPmTcTFxSE0NBTJycnVFjGVPzipvEKr2G6uT20fuBQZGYmFCxdK23q9Hn5+fggJCYFWq5W1pooMBgMSExMRHBzc5L6C3d1dhddeq73f2LEPYPjwPoqOoTGs1ZzGEFddj/HGsAZ7sdVaG+L3SmFhIa5evYpmzZpZ/7kbq1fDqNHAdeVKuLz6KlTFxTBGRUGzbBk0tg1Xolar4eTkZPb3uJubG15//XV06NABmZmZmDdvHtasWYOtW7cCAFxcXKBSqaDVaiGEwNy5c9G/f3+8/fbbcHR0RFpaGpo3bw6tVosLFy5gypQpWLVqFWJiYvDbb79hwYIFePHFF6uc/SlXcf6KtFotZsyYgZiYGLi7u8PR0RHLli1DfHw8tm3bhi5duiAlJQVPP/002rVrh6FDh2Lv3r14/PHHkZGRAa1WC1dXV2i12hrHDR8+HNnZ2ZgwYQKGDx+Oo0ePQqvV4ssvv4SLiwuWLl2Kn376CXq9XlqDp6cnrl27BqCs4NJqtcjOzsbUqVMRGhqKDz74AN9//z2efvpp6HQ6rFy5EkBZAbx7925ERETg1KlTSE1NxV//+leMGDECwcHB2LdvH7Zt24Zdu3ahR48eyM3NRXp6OgDAw8OjynN4YWEhXF1dERgYWOV41FtbCMt6wcmMkSNHirlz55q9b9iwYWLBggUmbfv37xdOTk7Sa8F+fn7itddeM+nz2muviXbt2smKg9fA1K789XxzFyTa+xqY+o6hMay1scZlq2tgGltu64Ot1qrIa2AqcnYuW7Czc93nqkVoaKhwdHQU7u7u0m3KlClm+/773/8WLVu2lLYrXwPj4eEh3nvvPbNjZ86cWeW56/jx48LBwaHanFWcv7Jt27YJAOLXX38Vt2/fFi4uLuLkyZMmfZ566inxxBNPCCHMXwNjybjIyEjRsWPHao8lc9fAVL6Id+nSpaJr167CaDRKfbZu3SqaNWsmXb8yfPhwMXToUJN5Bg4cKBYvXiyEEGLjxo3i/vvvN4nD3tfA1PmTZYQQJteiVBQQEFDllOmRI0cwYMAA6a+Q6voMGTKkrqFRJY6OwObNZf9f+QRX+XZ0dP1+tkXNMQibxdAY1mpOY41LjqawBkvdS2ut1urVQHEx4Oxc9nP16nrf5YgRI5CWlibdtmzZAgA4duwYgoODcd9998HDwwOzZs3C77//jjt37pid59lnn8XcuXMxatQorF+/Hv/973+l+86ePYvY2Fg0a9ZMuo0ePVr6Cga5RIVXFy5evIjCwkIEBwebzL9jxw6TGCqzZFxaWhqGDRtWpzN5GRkZCAgIMDlL8tBDD+H27dv45ZdfpLbevXubjPPx8cH169cBAI8//jgKCgrQqVMn/P3vf0d8fHyVl4bqm6wCZunSpTh+/Dh+/vlnXLhwAS+++CKSkpIwY8YMAGUv68yaNUvq/8wzzyArKwsLFy5ERkYG3nvvPWzfvh3PP/+81Cc8PBxHjhzBhg0b8P3332PDhg04evQonnvuOduskEw89hiwbx9w332m7W3blrU/9ljDxXDffbaNoTGsVUlxydEU1mCpe2mtVaxeDaxYAaxaBRQVlf1csaLeixh3d3f86U9/km4+Pj7IysrCuHHj0LNnT8TFxeHs2bPSS0fVXQS6ZMkSXLhwAePHj8cXX3xh8jljRqMRTz/9tEmhlJ6ejh9//BGdO3eWHXP5S0EtW7aULmD99NNPTea/ePEi9u3bV+0cloxzdXWVHVtlwsxlGhULsHKViySVSiXF6Ofnh0uXLmHr1q1wdXXFs88+i6CgILteqC7rGphff/0VM2fORE5ODnQ6HXr37o3PPvsMwcHBAICcnBxcuXJF6t+xY0ckJCQgIiICW7duha+vL7Zs2YI///nPUp8hQ4Zg9+7dWLZsGZYvX47OnTtjz549GDRokI2WSJU99hgwaVLDfqpoxRiuXi1BVtYpPP/8ILi42Pb6gMawViXFJUdTWIOl7qW1SioWL8uXl7WV/1yxwnTbDr7++muUlJRg48aN0sfS//vf/6513P33349u3bohIiICTzzxBGJiYvDoo4+iX79++O677/CnP/2pzrFdv34du3btwuTJk+Hg4CB9MOuVK1cwfPhws2PKv5W5tLRUarNkXO/evfH+++9L7+Q1N2/FOc3x9/dHXFycSSFz8uRJeHh44L7KlXoNXF1d8cgjj+CRRx5BWFgYunXrhosXL2LYsGEWz1EXsgqY7du313h/bGxslbbhw4fj3LlzNY6bMmUKpkyZIicUqiNHRyAoqHHEYDAIJCT8Xm9PBo1hreY01rjkaAprsNS9tFYAZd+dULF4KVe+XcuTpK117twZJSUleP311zFx4kR8+eWXZj/ZvVxBQQFeeOEFPPHEE+jcuTN++eUXfPXVV9If0IsXL8bgwYMRFhaGv//973B3d0dGRgYSExPx+uuvVzuvEAK5ubnS26hTU1Oxdu1a6HQ6rF+/HkDZRazPP/88IiIiYDQaMXToUOj1epw8eRLNmjVDaGgo2rdvD5VKhU8++QTjxo2Dq6urRePmzZuH119/HdOnT0dkZCR0Oh1OnTqFBx98EF27dkWHDh3wn//8B5cuXULLli2h0+mqrOHZZ59FdHQ05s+fj3nz5uHSpUtYuXIlFi5caPF3FsXGxqK0tBSDBg2Cm5sbPvjgA7i6usLPz8+i8TYh64qZRowX8SoXc25fzLf9Kf4iXjsydxFquddee034+PgIV1dXMXr0aLFjxw6TC2ErXmRbUFAgHnvsMeHn5yecnZ2Fr6+vmDdvnkk+zpw5I4KDg0WzZs2Eu7u76N27t1izZk21sVX8IDuVSiV0Op148MEHxapVq6o89xiNRrF582bRtWtXoVarRevWrcXo0aNFcnKy1GfVqlXC29tbqFQqERoaavG49PR0ERISItzc3ISHh4cYNmyY+O9//yuEEOL69evSmgCIY8eOmf0k3qSkJDFw4EDh7OwsvL29xeLFi00+6G748OEiPDzcZE2TJk2S4oyPjxeDBg0SWq1WuLu7i8GDB4sjR47Y9SJelRBC2Z809T96vR46nQ75+fl1fht1QkICxo0b1+TeRt1YMef2xXzbX0PkvLCwEJmZmejYsaP1b6NWMKPRCL1eD61Wy2/ktpOacl7T8Wjt8zcfVSIiIlIcFjBERESkOCxgiIiISHFYwBAREZHisIAhIiIixWEBQ0RERIrDAoaIiIgUhwUMERERKQ4LGCIioiYiNjYWzZs3b+gw7IIFDBERNQoqlarG2+zZs+0Wy+zZs6X9qtVqtGnTBsHBwXjvvfekb2S21EsvvYQHHnjA5jF26NAB0dHRJm3Tpk3DDz/8YPN9NUYsYIiIqEZfX/saD7//ML6+9nW97icnJ0e6RUdHQ6vVmrRt3rzZpL/BYKjXeMaMGYOcnBz8/PPPOHz4MEaMGIHw8HBMmDABJSUl9bpva7m6usLLy6uhw7ALFjBERFSjHek7cOznY/gg/YN63Y+3t7d00+l0UKlU0nZhYSGaN2+Of//73wgKCoKLiwt27txp9uxGdHQ0OnXqZNIWExOD7t27w8XFBd26dcObb75ZazwajQbe3t6477770K9fPyxduhQHDx7E4cOHERsbK/XLz8/H3Llz4eXlBa1Wi4cffhjp6ekAyl7SiYqKQnp6unRGp3xsTePKHTp0CAMGDICLiwtatWqFxx57DAAQFBSErKwsRERESPOW76/yS0jbtm1D586d4ezsjK5du+KDD0wfR5VKhX/961949NFH4ebmhi5duuDQoUPS/Xl5eZgxYwZat24NV1dXdOnSBTExMbXmr76xgCEioiqybmbh7LWzOJdzDnu+2wMA2P3dbpzLOYez184i62ZWg8S1ePFiLFiwABkZGRg9erRFY9599128+OKLWLNmDTIyMrB27VosX74c77//vuz9P/zww+jTpw/2798PABBCYPz48cjNzUVCQgLOnj2Lfv36YeTIkfjjjz8wbdo0/POf/0SPHj2kM0nTpk2rdRwAfPrpp3jssccwfvx4nD9/Hp9//jkGDBgAANi/fz/atm2LVatWSfOaEx8fj/DwcPzzn//Et99+i6effhpz5szBsWPHTPpFRUVh6tSp+OabbzBu3DjMmDFDimP58uW4ePEiDh8+jIyMDGzbtg2tWrWSnTtbc2roAIiIqPHpsLmD9P8qlP11/9ud39D/nf5Su1gp7B0WnnvuOekshKVWr16NjRs3SuM6duyIixcv4u2330ZoaKjsGLp164ZvvvkGAHDs2DFcuHAB169fh0ajAQC8+uqrOHDgAPbt24e5c+eiWbNmcHJygre3tzTHF198Ueu4NWvWYPr06YiKipLG9enTBwDg6ekJR0dHeHh4mMxb2auvvorZs2fj2WefBQAsXLgQp06dwquvvooRI0ZI/WbPno0nnngCALB27Vq8/vrrOHPmDMaMGYMrV66gb9++UvHUoUMH2TmrDzwDQ0REVex8dCecHMr+xhUQJj+dHJyw89GdDRJX+ZOopX777TdcvXoVTz31FJo1aybdXn75Zfz3v/+1KgYhhPSSzdmzZ3H79m20bNnSZP7MzMwa57dkXFpaGkaOHGlVjOUyMjLw0EMPmbQ99NBDyMjIMGnr3bu39P/u7u7w8PDA9evXAQD/+Mc/sHv3bjzwwANYtGgRTp48WaeYbIVnYIiIqIoZvWege+vuJmdcyp3+22n08+nXAFGVPblW5ODgACFMzwRVvLi3/B1D7777LgYNGmTSz9HR0aoYMjIy0LFjR2l+Hx8fJCUlVelX09uZLRnn6upqVXyVlRdb5SoWYOXUanWVMeW5Gzt2LLKysvDpp5/i6NGjGDlyJMLCwvDqq6/aJD5rsYAhIqIaOcABRhiln41J69atkZuba/KknJaWJt3fpk0b3Hffffjpp58wY8aMOu+v/KWfiIgIAEC/fv2Qm5sLJyenal9acXZ2RmlpqUmbJeN69+6Nzz//HHPmzLF43sq6d++OEydOYNasWVLbyZMn0b179xrHVda6dWvMnj0bs2fPxrBhw/DCCy+wgCEiosbJy90L3s284af1w1N9n8L289txVX8VXu6N5226QUFB+O233/D//t//w5QpU/DZZ5/h8OHD0Gq1Up+XXnoJCxYsgFarxdixY1FUVISvv/4aeXl5WLhwYbVzFxUVITc3F6Wlpfj111/x2WefYd26dZgwYYJUEIwaNQoBAQGYPHkyNmzYgK5du+LatWtISEjA5MmTMWDAAHTo0AGZmZlIS0tD27Zt4eHhYdG4lStXYuTIkejcuTOmT5+OkpISHD58GIsWLQJQdi1KSkoKpk+fDo1GY/bC2hdeeAFTp06VLhD++OOPsX//fhw9etTiHK9YsQL9+/dHjx49UFRUhE8++UR2AVQvRBORn58vAIj8/Pw6zVNcXCwOHDggiouLbRQZ1YY5ty/m2/4aIucFBQXi4sWLoqCgoE7zFBoKhdFoFEIIYTQaRaGh0Bbh1SomJkbodDppOzMzUwAQ58+fr9J327Ztws/PT7i7u4tZs2aJNWvWiPbt24u8vDxRWloqhBDiww8/FA888IBwdnYWLVq0EIGBgWL//v3V7j80NFQAEACEk5OTaN26tRg1apR47733pDnL6fV6MX/+fOHr6yvUarXw8/MTM2bMEFeuXBFCCFFYWCj+/Oc/i+bNmwsAIiYmxqJxQggRFxcnxd2qVSvx2GOPSfelpqaK3r17C41GI8qfzivnTQgh3nzzTdGpUyehVqvF/fffL3bs2GFyPwARHx9v0qbT6aQ4V69eLbp37y5cXV2Fp6enmDRpkvjpp5+q5Ky0tNQk5xXVdDxa+/yt+l/wiqfX66HT6ZCfn29SectlMBiQkJCAcePGVXlNkOoHc25fzLf9NUTOCwsLkZmZiY4dO8LFxcUu+2xMjEYj9Ho9tFotHBz4fhV7qCnnNR2P1j5/81ElIiIixWEBQ0RERIrDAoaIiIgUhwUMERERKQ4LGCIiIlIcFjBERESkOCxgiIiISHFYwBAREZHisIAhIiIixZFVwKxbtw4DBw6Eh4cHvLy8MHnyZFy6dKnGMbNnz4ZKpapy69Gjh9QnNjbWbJ/CwkLrVkVERPec2NjYGr8BurEICgrCc889V6/7SEpKgkqlws2bN+t1Pw1JVgGTnJyMsLAwnDp1ComJiSgpKUFISAju3LlT7ZjNmzcjJydHul29ehWenp54/PHHTfpptVqTfjk5Offkx18TETUmpaVAUhLw0UdlP2v58uM6q+6P3suXL9fvji1Q+Y/tNm3aYOLEifjuu+9kzbN//36sXr3aZnGZK4iGDBmCnJwc6HQ6m+2nsZH1bdSfffaZyXZMTAy8vLxw9uxZBAYGmh2j0+lMEnjgwAHk5eVV+XpwlUoFb29vOeEQEVE92r8fCA8Hfvnl/9ratgU2bwYee6z+9jtmzBjExMSYtLVu3br+diiDVqvFpUuXIIRAdnY2Fi1ahPHjx+OHH36As7OzRXN4enrWc5SAs7Nzk39OrdM1MPn5+QDkPRjbt2/HqFGj0L59e5P227dvo3379mjbti0mTJiA8+fP1zhPUVER9Hq9yQ0o+9K0ut5sNQ9vzHljvTHf90bOhRAwGo1W3fbtM2LKFIFffjH9vt/sbIEpUwT27bNu3tpuQgg4OzvDy8vL5KZSqbBx40b06tUL7u7u8PPzwz/+8Q/o9XqT8QCkeS5cuICHH34YHh4e0Gq16N+/P86cOSP1PXHiBAIDA+Hq6go/Pz/Mnz8ft27dqjE+lUoFLy8vtGnTBv369UN4eDiysrKQkZFh8bxBQUEIDw+XtgsLC/HCCy/gvvvug7u7OwYNGoQvvvjCZL/Hjx/H8OHD4ebmhhYtWiAkJAS///47QkNDkZycjM2bN0tnhn766Sd88cUXUKlU+OOPP6Q59u7dix49ekCj0aBDhw549dVXTfbRoUMHrFmzBnPmzIGHhwfatWuHt956yyTOsLAw+Pj4wMXFBR06dMDatWtNHjsA1R53Qoga/33IJesMTEVCCCxcuBBDhw5Fz549LRqTk5ODw4cPY9euXSbt3bp1Q2xsLHr16gW9Xo/NmzfjoYceQnp6Orp06WJ2rnXr1iEqKqpK+5EjR+Dm5iZ/QZUkJibWeQ6Shzm3L+bb/uyZcycnJ3h7e+P27dsoLi6WNba0FAgP16Ls+Uhlcp8QKqhUAs89B4wYoYejo81CBlBW5JWUlEh/lFZUXFyMtWvXol27dsjKysLzzz+PiIgIbNy4EUDZNx4LIaSxc+fORe/evfH555/D0dERFy5ckP74/e677zB27FgsXboUmzZtwo0bN7Bo0SI888wz2Lp1q9nYKs+fn5+PHTt2AICseUtKSlBcXCzN8/e//x1XrlzBu+++Cx8fH3zyyScYN24cvvzyS3Tu3BkXLlxAcHAwZsyYgZdffhlOTk44fvw4bt68iVWrViEjIwP+/v6IjIwEUPbKx927dwEAt27dgoODA9LS0jB9+nQsWbIEjz76KM6cOYPnn38ebm5uePLJJwGUFX4bN27E0qVLMX/+fBw8eBBhYWHo168f7r//frz++us4ePAgtm/fjrZt2yI7OxvZ2dlVHqtbt26ZfewKCgqQkpKCkpISk/vKY5VLJcpLJpnCwsLw6aef4sSJE2jbtq1FY9atW4eNGzfi2rVrNZ5qMxqN6NevHwIDA7FlyxazfYqKilBUVCRt6/V6+Pn54caNG7K+jrsyg8GAxMREBAcH2+1r7+91zLl9Md/21xA5LywsxNWrV9GhQwfZ1xMmJQEjR9Z+gv7zz40ICrIuvurMmTMHH374oUnMY8aMwb///e8qfffu3YuwsDBcv34dQNk1KgsXLsQff/wBIQRatGiBzZs3IzQ0tMrY0NBQuLq64q233pLaTpw4gREjRuDWrVtmcxYbG4unnnoK7u7uEEJIT7wTJ07EgQMHLJ734YcfRp8+fbBp0yb897//RdeuXXHlyhX4+vpKY0JCQjBw4ECsWbMGM2bMwNWrV5GSkmI2ZxXnK5eUlISRI0fi999/R/PmzfGXv/wFv/32G/7zn/9IfRYvXoyEhARcuHABANCpUycMHTpUKsqEEPD19cXKlSvxzDPPIDw8HBcvXsSRI0egUpkWtuX9b926BQ8Pjyr3FxYW4ueff4afn1+V3Or1erRq1Qr5+fmynr+tOgMzf/58HDp0CCkpKRYXL0IIvPfee5g5c2atrxM6ODhg4MCB+PHHH6vto9FooNFoqrSr1Wqb/IKw1TxkOebcvphv+7NnzktLS6FSqeDg4AAHB3lXC/z6q6X9HCBz6lqpVCqMGDEC27Ztk9rc3d3h4OCAY8eOYe3atbh48SL0ej1KSkpQWFiIgoICqQ9Q9hxiNBrx7LPPYu7cufjwww8xatQoPP744+jcuTMA4Ny5c7h8+bLJKwLlL31kZWWhe/fuVWJzcHCAh4cHzp07h5KSEiQnJ+OVV17B22+/Le3b0nnLH5u0tDQIIdCtWzeTfRUVFaFly5ZwcHBAeno6Hn/88Rofx/L5KsZa/tPBwQHff/89Jk2aZNJn6NCh2Lx5M4QQcPzfqbQ+ffqY9PH29saNGzfg4OCAOXPmIDg4GN27d8eYMWMwYcIEhISESH3LX8KrHEt5HCqVyuy/AWv/TcgqYIQQmD9/PuLj45GUlISOHTtaPDY5ORmXL1/GU089ZdF+0tLS0KtXLznhERGRDfj42LafXO7u7vjTn/5k0paVlYVx48bhmWeewerVq+Hp6YkTJ07gqaeeqvYaiiVLlmD27Nk4fPgwDh8+jJUrV2L37t149NFHYTQa8fTTT2PBggVVxrVr167a2BwcHKTYunXrhtzcXEybNk06OyJ3XqPRCEdHR5w9e1YqIso1a9YMAODq6lptPJYSQlQ5K2LuBZjKxYRKpZIKk379+iEzMxOHDx/G0aNHMXXqVIwaNQr79u2rc3zWkFXAhIWFYdeuXTh48CA8PDyQm5sLoOz1tvIER0ZGIjs7WzoFVW779u0YNGiQ2etloqKiMHjwYHTp0gV6vR5btmxBWlpata9DEhFR/Rk2rOzdRtnZgLmLDFSqsvuHDbNfTF9//TVKSkqwceNG6a97cy8rVXb//fejW7duiIiIwBNPPIGYmBg8+uij6NevH7777rsqhZJcEREReO211xAfH2/VvH379kVpaSmuX7+OYdUktPw6HnPXfQJl7zgqreX97f7+/jhx4oRJ28mTJ3H//fdXKZxqotVqMW3aNEybNg1TpkzBmDFj8Mcff9jlnVWVyTr5t23bNuTn5yMoKAg+Pj7Sbc+ePVKfnJwcXLlyxWRcfn4+4uLiqj37cvPmTcydOxfdu3dHSEgIsrOzkZKSggcffNCKJRERUV04Opa9VRooK1YqKt+OjobNL+CtSefOnVFSUoLXX38dP/30Ez744AOT60wqKygowAsvvICkpCRkZWXhyy+/xFdffSW9hLN48WKkpqYiLCwMaWlp+PHHH3Ho0CHMnz9fVlxarRZ/+9vfsHLlSgghZM97//33Y8aMGZg1axb279+PzMxMfPXVV9iwYQMSEhIAlJ0Y+Oqrr/Dss8/im2++wffff49t27bhxo0bAIAOHTrg9OnT+Pnnn3Hjxg3pjElF//znP/H5559j9erV+OGHH/D+++/jjTfewPPPP2/xWjdt2oTdu3fj+++/xw8//IC9e/fC29u74T48UDQR+fn5AoDIz8+v0zzFxcXiwIEDori42EaRUW2Yc/tivu2vIXJeUFAgLl68KAoKCqyeIy5OiLZthSg7D1N28/Mra68voaGhYtKkSWbve+2114SPj49wdXUVo0ePFjt27BAARF5enhBCiJiYGKHT6YQQZet/7LHHhJ+fn3B2dha+vr5i3rx5Jvk4c+aMCA4OFs2aNRPu7u6id+/eYs2aNdXGVnH+irKysoSTk5PYs2ePRfMOHz5chIeHS9vFxcVixYoVokOHDkKtVgtvb2/x6KOPim+++Ubqk5SUJIYMGSI0Go1o3ry5GD16tLTuS5cuicGDBwtXV1cBQGRmZopjx46Z5EYIIfbt2yf8/f2FWq0W7dq1E6+88orJOtq3by82bdpk0tanTx+xcuVKIYQQ77zzjnjggQeEu7u70Gq1YuTIkeLcuXNS39LSUpGXlydKS0ur5Kim49Ha52+r34XU2Oj1euh0OtlXMVdmMBiQkJCAcePG8QJHO2HO7Yv5tr+GyHlhYSEyMzPRsWPHOn2qeWkpcPw4kJNTds3LsGH2PfNiLaPRCL1eD61WK/si5voWEBCAkSNH4uWXX27oUGyqppzXdDxa+/xt9efAEBFR0+foCJu/VfpeVVRUhAsXLuC7774ze5EvydO4ylIiIqIm6vDhw3j44YcxceJETJkypaHDUTyegSEiIrKDyZMnm/2EYbIOz8AQERGR4rCAISIiIsVhAUNE1IQ1kTeaksLVx3HIAoaIqAkqf7u2td/0S2RL5cehLT9GgBfxEhE1QY6OjmjevLn0Tc1ubm5mv0G4qTIajSguLkZhYWGj+xyYpspczsX/vrX7+vXraN68uayvLagNCxgioibK29sbAKQi5l4ihEBBQQFcXV3vqcKtIdWU8+bNm0vHo62wgCEiaqJUKhV8fHzg5eVV7Tc2N1UGgwEpKSkIDAzkJ07bSXU5V6vVNj3zUo4FDBFRE+fo6FgvTyCNmaOjI0pKSuDi4sICxk7snXO+MEhERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxWMAQERGR4rCAISIiIsVhAUNERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxWMAQERGR4rCAISIiIsVhAUNERESKwwKGiIiIFIcFDBERESmOrAJm3bp1GDhwIDw8PODl5YXJkyfj0qVLNY5JSkqCSqWqcvv+++9N+sXFxcHf3x8ajQb+/v6Ij4+XvxoiIiK6J8gqYJKTkxEWFoZTp04hMTERJSUlCAkJwZ07d2ode+nSJeTk5Ei3Ll26SPelpqZi2rRpmDlzJtLT0zFz5kxMnToVp0+flr8iIiIiavKc5HT+7LPPTLZjYmLg5eWFs2fPIjAwsMaxXl5eaN68udn7oqOjERwcjMjISABAZGQkkpOTER0djY8++khOiERERHQPkFXAVJafnw8A8PT0rLVv3759UVhYCH9/fyxbtgwjRoyQ7ktNTUVERIRJ/9GjRyM6Orra+YqKilBUVCRt6/V6AIDBYIDBYJCzDBPlY+syB8nDnNsX821/zLn9Mef2Z23OrX2MVEIIYc1AIQQmTZqEvLw8HD9+vNp+ly5dQkpKCvr374+ioiJ88MEHeOutt5CUlCSdtXF2dkZsbCyefPJJadyuXbswZ84ckyKlopdeeglRUVFV2nft2gU3NzdrlkRERER2dvfuXTz55JPIz8+HVqu1eJzVZ2DmzZuHb775BidOnKixX9euXdG1a1dpOyAgAFevXsWrr75q8rKTSqUyGSeEqNJWUWRkJBYuXCht6/V6+Pn5ISQkRFYCKjMYDEhMTERwcDDUarXV85DlmHP7Yr7tjzm3P+bc/qzNefkrKHJZVcDMnz8fhw4dQkpKCtq2bSt7/ODBg7Fz505p29vbG7m5uSZ9rl+/jjZt2lQ7h0ajgUajqdKuVqttcrDaah6yHHNuX8y3/THn9sec25/cnFv7+Mh6F5IQAvPmzcP+/fvxxRdfoGPHjlbt9Pz58/Dx8ZG2AwICkJiYaNLnyJEjGDJkiFXzExERUdMm6wxMWFgYdu3ahYMHD8LDw0M6a6LT6eDq6gqg7KWd7Oxs7NixA0DZO4w6dOiAHj16oLi4GDt37kRcXBzi4uKkecPDwxEYGIgNGzZg0qRJOHjwII4ePVrry1NERER0b5JVwGzbtg0AEBQUZNIeExOD2bNnAwBycnJw5coV6b7i4mI8//zzyM7OhqurK3r06IFPP/0U48aNk/oMGTIEu3fvxrJly7B8+XJ07twZe/bswaBBg6xcFhERETVlsgoYS96wFBsba7K9aNEiLFq0qNZxU6ZMwZQpU+SEQ0RERPcofhcSERERKQ4LGCIiIlIcFjBERESkOCxgiIiISHFYwBAREZHisIAhIiIixWEBQ0RERIrDAoaIiIgUhwUMERERKQ4LGCIiIlIcFjBERESkOCxgiIiISHFYwBAREZHisIAhIiIixWEBQ0RERIrDAoaIiIgUhwUMERERKQ4LGCIiIlIcFjBERESkOCxgiIiISHFYwBAREZHisIAhIiIixWEBQ0RERIrDAoaIiIgUhwUMERERKQ4LGCIiIlIcFjBERESkOCxgiIiISHFYwBAREZHisIAhIiIixWEBQ0RERIojq4BZt24dBg4cCA8PD3h5eWHy5Mm4dOlSjWP279+P4OBgtG7dGlqtFgEBAfjPf/5j0ic2NhYqlarKrbCwUP6KiIiIqMmTVcAkJycjLCwMp06dQmJiIkpKShASEoI7d+5UOyYlJQXBwcFISEjA2bNnMWLECEycOBHnz5836afVapGTk2Nyc3FxsW5VRERE1KQ5yen82WefmWzHxMTAy8sLZ8+eRWBgoNkx0dHRJttr167FwYMH8fHHH6Nv375Su0qlgre3t5xwiIiI6B4lq4CpLD8/HwDg6elp8Rij0Yhbt25VGXP79m20b98epaWleOCBB7B69WqTAqeyoqIiFBUVSdt6vR4AYDAYYDAY5CzDRPnYusxB8jDn9sV82x9zbn/Muf1Zm3NrHyOVEEJYM1AIgUmTJiEvLw/Hjx+3eNwrr7yC9evXIyMjA15eXgCAU6dO4fLly+jVqxf0ej02b96MhIQEpKeno0uXLmbneemllxAVFVWlfdeuXXBzc7NmSURERGRnd+/exZNPPon8/HxotVqLx1ldwISFheHTTz/FiRMn0LZtW4vGfPTRR/jb3/6GgwcPYtSoUdX2MxqN6NevHwIDA7FlyxazfcydgfHz88ONGzdkJaAyg8GAxMREBAcHQ61WWz0PWY45ty/m2/6Yc/tjzu3P2pzr9Xq0atVKdgFj1UtI8+fPx6FDh5CSkmJx8bJnzx489dRT2Lt3b43FCwA4ODhg4MCB+PHHH6vto9FooNFoqrSr1WqbHKy2mocsx5zbF/Ntf8y5/THn9ic359Y+PrLehSSEwLx587B//3588cUX6Nixo0XjPvroI8yePRu7du3C+PHjLdpPWloafHx85IRHRERE9whZZ2DCwsKwa9cuHDx4EB4eHsjNzQUA6HQ6uLq6AgAiIyORnZ2NHTt2ACgrXmbNmoXNmzdj8ODB0hhXV1fodDoAQFRUFAYPHowuXbpAr9djy5YtSEtLw9atW222UCIiImo6ZJ2B2bZtG/Lz8xEUFAQfHx/ptmfPHqlPTk4Orly5Im2//fbbKCkpQVhYmMmY8PBwqc/Nmzcxd+5cdO/eHSEhIcjOzkZKSgoefPBBGyyRiIiImhpZZ2Asud43NjbWZDspKanWMZs2bcKmTZvkhEJERET3MH4XEhERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxWMAQERGR4rCAISIiIsVhAUNERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxWMAQERGR4rCAISIiIsVhAUNERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxWMAQERGR4rCAISIiIsVhAUNERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxWMAQERGR4rCAISIiIsVhAUNERESKI6uAWbduHQYOHAgPDw94eXlh8uTJuHTpUq3jkpOT0b9/f7i4uKBTp0546623qvSJi4uDv78/NBoN/P39ER8fLye0evP1ta/x8PsP4+trX5v8f039amqTs88d6TvMjq88b3X7sXT/tcVe2zyW7F/OfHWNvTbV5deSx9DS3MuNTe5jaEk+q4t154WdWH55Oc7mnK3TY2Qta9ZUl9iszWF95oCI6k5WAZOcnIywsDCcOnUKiYmJKCkpQUhICO7cuVPtmMzMTIwbNw7Dhg3D+fPnsXTpUixYsABxcXFSn9TUVEybNg0zZ85Eeno6Zs6cialTp+L06dPWr8xGdqTvwLGfj+GD9A9M/r+mfjW1ydnna6mvmR1fed7q9mPp/muLvbZ5LNm/nPnqGnttqsuvJY+hpbmXG5vcx9CSfFYXa/TpaFy4fQEfXviwTo+RtaxZU11iszaH9ZkDIqo7lRBCWDv4t99+g5eXF5KTkxEYGGi2z+LFi3Ho0CFkZGRIbc888wzS09ORmpoKAJg2bRr0ej0OHz4s9RkzZgxatGiBjz76yKJY9Ho9dDod8vPzodVqrV0SDAYDYg/Eoveg3lCr1Qj5IAS/F/yOFi4tAAB5hXlo6doSR2YewTX9NQCAr9YXYz8ci+t3rqOla0tsHrMZABD+WTh+L/gdXu5eODzjMIQQaOXWCu2bt6+y36ybWbhx9wZyb+diZvxM5BXmQQUVBARauLTAxpCNUDuo0cK1Bf566K+4fuc6Wri0wOvjXsf8hPnIK8yDl7sX3nvkPeQV5Jn0M7f/8v2pVCqzsc9LmIebRTfNrlsIgcKSQrg4uZiMr7z/0AOhUu5KRSn0RXroNDo4qBxM5jMYDPjm9DcYMWIE8ovzq8xpSey15bim/Ho4e2D1iNWISo6S4qr8GFbOtbncH55x2OwxUV1s1a2jusewutxWfHzen/x+lbEtXFpgZdBKLP9iOW4V35Jy4uHsAQC4VXwLOo0OAqLax6imY9cSlqzV3Jp0Gh22jt+KZz99FvoifbXHY+XYrN1fc01zvDHuDdn/fmtjMBiQkJCAcePGQa1WW5VDkoc5tz9rc27t83edCpjLly+jS5cuuHDhAnr27Gm2T2BgIPr27YvNmzdLbfHx8Zg6dSru3r0LtVqNdu3aISIiAhEREVKfTZs2ITo6GllZWWbnLSoqQlFRkbSt1+vh5+eHGzdu1LmAcX/FXfa48idDS+4rXlpcpY/zWuc676tye/m2uf1X3F9NscuJp67zWDJndbHXlmM5+a1LvObaqovNknXUJbe2fDzKmTt2LWHJWuuqYmy23J8l/35rYzAYkJiYiODgYD6Z2glzbn/W5lyv16NVq1b2K2CEEJg0aRLy8vJw/Pjxavvdf//9mD17NpYuXSq1nTx5Eg899BCuXbsGHx8fODs7IzY2Fk8++aTUZ9euXZgzZ45JkVLRSy+9hKioqCrtu3btgpubmzVLkiT/kYwtV7agFKU19lP97z8jjBbN6whHLGi3AMM9h1u9z7qouP+67M8RjghuGYzE3xNtEm95XACqjcnS2KvLsT3yC9R8TFSOzV4x2UJNx64l6nOt5mKrj/3VNQdEZN7du3fx5JNPyi5gnKzd4bx58/DNN9/gxIkTtfZVqVQm2+U1U8V2c30qt1UUGRmJhQsXStvlZ2BCQkLqfAYGicCfg/6MoTuG1tj31F9PAQAGvTfIorlP/vUk+nr3NXvfOIzD9NzpNc71/iPvI/RQaK37qa5fxf1bsr/qlM9zPve82fGWxlkueVYybnxzA8HBwZj+u/mYLI29uhzXZb1y1HRMVI6tppiqy6EluZWbf0vUdOxawpq11iW2+thfXXLAswH2x5zbX13OwFjDqgJm/vz5OHToEFJSUtC2bdsa+3p7eyM3N9ek7fr163ByckLLli1r7NOmTZtq59VoNNBoNFXa1Wq1TQ5WtVPZHA5wqPLXdHmbk5NTlbaK/Su3OTk51Rhb+XzVvYzg6ORoMm/lU+Pl7ZX7Vbf/8v3VFHt161ar1dWOr7z/6pTfX57rmua0NPaaclxdfivn2VweKue6utzXdEyYi83SHFqS2+r61OWlGkuPXUtYc7zU9PJPbbFZs7+6/Pu1hK1+P5HlmHP7k5tzax8fWe9CEkJg3rx52L9/P7744gt07Nix1jEBAQFITEw0aTty5AgGDBggBV1dnyFDhsgJz6Zau7WGdzNv9Pftj3UPr4PaQQ0nByesG7kO/X37w7uZN7zcveDl7iX1e2v8W+jv2x+t3VqjtVtrk7by/jUpn6t3m97QarRwU7tBq9Gid5ve8G7mjfs97zfZV+82veGgckDvNr1N9lO5X3X7ry32mtZd3fjK+684x5KHlpidr7Vb6xpjsjT22nJcXX67t+peJY+VH8PKua4u99UdE9XFZkkOLcltxXxWd5x0b9VdWreLygVOKqcqj0t1j1Ftx64l5B4v60auM8lzbcejLfZXl3+/RGRnQoZ//OMfQqfTiaSkJJGTkyPd7t69K/VZsmSJmDlzprT9008/CTc3NxERESEuXrwotm/fLtRqtdi3b5/U58svvxSOjo5i/fr1IiMjQ6xfv144OTmJU6dOWRxbfn6+ACDy8/PlLKmK4uJiceDAAVFcXCwKDYXCaDQKIYQoKC4QBcUFQgghjEajKDQUSmMq9iu/z1ybJcrHFRoKRWlpqcm2uX3lF+Sb3Y+l+68t9prWXdN+qpvD3HwVc17X2K3Nr7k81pbr6nIvNzZLcmhJbi05TgoNhaKwsFDs3b9X6O/ozT4utT3mdWHNmirmWW5s1ubQ2n+/1al8jFP9Y87tz9qcW/v8LeslpG3btgEAgoKCTNpjYmIwe/ZsAEBOTg6uXLki3dexY0ckJCQgIiICW7duha+vL7Zs2YI///nPUp8hQ4Zg9+7dWLZsGZYvX47OnTtjz549GDSofq9XqI3G6f9eonJRu0j/r1KpTO6r+P+V76uurbZ9Sj8dNGbby+fVumhNtqvrV93+a+tX07prGl9d7szNZzAYZMUkt5+5MZXzW10eK7ZV7lPTGDmxWZJDS3Jb09jyWDVOGhiEAWoHNVzULtJZ0NoeI1uxZk0V8yw3trrkUM5+iMj+ZBUwwoI3LMXGxlZpGz58OM6dO1fjuClTpmDKlClywiEiIqJ7FL8LiYiIiBSHBQwREREpDgsYIiIiUhwWMERERKQ4LGCIiIhIcVjAEBERkeKwgCEiIiLFYQFDREREisMChoiIiBSHBQwREREpDgsYIiIiUhwWMERERKQ4LGCIiIhIcVjAEBERkeKwgCEiIiLFYQFDREREisMChoiIiBSHBQwREREpDgsYIiIiUhwWMERERKQ4LGCIiIhIcVjAEBERkeKwgCEiIiLFYQFDREREisMChoiIiBSHBQwREREpDgsYIiIiUhwWMERERKQ4LGCIiIhIcVjAEBERkeKwgCEiIiLFkV3ApKSkYOLEifD19YVKpcKBAwdq7D979myoVKoqtx49ekh9YmNjzfYpLCyUvSAiIiJq+mQXMHfu3EGfPn3wxhtvWNR/8+bNyMnJkW5Xr16Fp6cnHn/8cZN+Wq3WpF9OTg5cXFzkhkdERET3ACe5A8aOHYuxY8da3F+n00Gn00nbBw4cQF5eHubMmWPST6VSwdvbW244REREdA+SXcDU1fbt2zFq1Ci0b9/epP327dto3749SktL8cADD2D16tXo27dvtfMUFRWhqKhI2tbr9QAAg8EAg8FgdXzlY+syB8nDnNsX821/zLn9Mef2Z23OrX2MVEIIYdVIlJ01iY+Px+TJky3qn5OTAz8/P+zatQtTp06V2k+dOoXLly+jV69e0Ov12Lx5MxISEpCeno4uXbqYneull15CVFRUlfZdu3bBzc3NqvUQERGRfd29exdPPvkk8vPzodVqLR5n1wJm3bp12LhxI65duwZnZ+dq+xmNRvTr1w+BgYHYsmWL2T7mzsD4+fnhxo0bshJQmcFgQGJiIoKDg6FWq62ehyzHnNsX821/zLn9Mef2Z23O9Xo9WrVqJbuAsdtLSEIIvPfee5g5c2aNxQsAODg4YODAgfjxxx+r7aPRaKDRaKq0q9VqmxystpqHLMec2xfzbX/Muf0x5/YnN+fWPj52+xyY5ORkXL58GU899VStfYUQSEtLg4+Pjx0iIyIiIqWRfQbm9u3buHz5srSdmZmJtLQ0eHp6ol27doiMjER2djZ27NhhMm779u0YNGgQevbsWWXOqKgoDB48GF26dIFer8eWLVuQlpaGrVu3WrEkIiIiaupkFzBff/01RowYIW0vXLgQABAaGorY2Fjk5OTgypUrJmPy8/MRFxeHzZs3m53z5s2bmDt3LnJzc6HT6dC3b1+kpKTgwQcflBseERER3QNkFzBBQUGo6brf2NjYKm06nQ53796tdsymTZuwadMmuaEQERHRPYrfhURERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxWMAQERGR4rCAISIiIsVhAUNERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxWMAQERGR4rCAISIiIsVhAUNERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxWMAQERGR4rCAISIiIsVhAUNERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxWMAQERGR4sguYFJSUjBx4kT4+vpCpVLhwIEDNfZPSkqCSqWqcvv+++9N+sXFxcHf3x8ajQb+/v6Ij4+XGxoRERHdI2QXMHfu3EGfPn3wxhtvyBp36dIl5OTkSLcuXbpI96WmpmLatGmYOXMm0tPTMXPmTEydOhWnT5+WGx4RERHdA5zkDhg7dizGjh0re0deXl5o3ry52fuio6MRHByMyMhIAEBkZCSSk5MRHR2Njz76SPa+iIiIqGmTXcBYq2/fvigsLIS/vz+WLVuGESNGSPelpqYiIiLCpP/o0aMRHR1d7XxFRUUoKiqStvV6PQDAYDDAYDBYHWf52LrMQfIw5/bFfNsfc25/zLn9WZtzax+jei9gfHx88M4776B///4oKirCBx98gJEjRyIpKQmBgYEAgNzcXLRp08ZkXJs2bZCbm1vtvOvWrUNUVFSV9iNHjsDNza3OcScmJtZ5DpKHObcv5tv+mHP7Y87tT27O7969a9V+6r2A6dq1K7p27SptBwQE4OrVq3j11VelAgYAVCqVyTghRJW2iiIjI7Fw4UJpW6/Xw8/PDyEhIdBqtVbHazAYkJiYiODgYKjVaqvnIcsx5/bFfNsfc25/zLn9WZvz8ldQ5LLbS0gVDR48GDt37pS2vb29q5xtuX79epWzMhVpNBpoNJoq7Wq12iYHq63mIcsx5/bFfNsfc25/zLn9yc25tY9Pg3wOzPnz5+Hj4yNtBwQEVDnldOTIEQwZMsTeoREREZECyD4Dc/v2bVy+fFnazszMRFpaGjw9PdGuXTtERkYiOzsbO3bsAFD2DqMOHTqgR48eKC4uxs6dOxEXF4e4uDhpjvDwcAQGBmLDhg2YNGkSDh48iKNHj+LEiRM2WCIRERE1NbILmK+//trkHUTl16GEhoYiNjYWOTk5uHLlinR/cXExnn/+eWRnZ8PV1RU9evTAp59+inHjxkl9hgwZgt27d2PZsmVYvnw5OnfujD179mDQoEF1WRsRERE1UbILmKCgIAghqr0/NjbWZHvRokVYtGhRrfNOmTIFU6ZMkRsOERER3YP4XUhERESkOCxgiIiISHFYwBAREZHisIAhIiIixWEBQ0RERIrDAoaIiIgUhwUMERERKQ4LGCIiIlIcFjBERESkOCxgiIiISHFYwBAREZHisIAhIiIixWEBQ0RERIrDAoaIiIgUhwUMERERKQ4LGCIiIlIcFjBERESkOCxgiIiISHFYwBAREZHisIAhIiIixWEBQ0RERIrDAoaIiIgUhwUMERERKQ4LGCIiIlIcFjBERESkOCxgiIiISHFYwBAREZHisIAhIiIixWEBQ0RERIrDAoaIiIgUhwUMERERKY7sAiYlJQUTJ06Er68vVCoVDhw4UGP//fv3Izg4GK1bt4ZWq0VAQAD+85//mPSJjY2FSqWqcissLJQbHhEREd0DZBcwd+7cQZ8+ffDGG29Y1D8lJQXBwcFISEjA2bNnMWLECEycOBHnz5836afVapGTk2Nyc3FxkRseERER3QOc5A4YO3Ysxo4da3H/6Ohok+21a9fi4MGD+Pjjj9G3b1+pXaVSwdvbW244REREdA+SXcDUldFoxK1bt+Dp6WnSfvv2bbRv3x6lpaV44IEHsHr1apMCp7KioiIUFRVJ23q9HgBgMBhgMBisjq98bF3mIHmYc/tivu2PObc/5tz+rM25tY+RSgghrBqJsrMm8fHxmDx5ssVjXnnlFaxfvx4ZGRnw8vICAJw6dQqXL19Gr169oNfrsXnzZiQkJCA9PR1dunQxO89LL72EqKioKu27du2Cm5ubVeshIiIi+7p79y6efPJJ5OfnQ6vVWjzOrgXMRx99hL/97W84ePAgRo0aVW0/o9GIfv36ITAwEFu2bDHbx9wZGD8/P9y4cUNWAiozGAxITExEcHAw1Gq11fOQ5Zhz+2K+7Y85tz/m3P6szbler0erVq1kFzB2ewlpz549eOqpp7B3794aixcAcHBwwMCBA/Hjjz9W20ej0UCj0VRpV6vVNjlYbTUPWY45ty/m2/6Yc/tjzu1Pbs6tfXzs8jkwH330EWbPno1du3Zh/PjxtfYXQiAtLQ0+Pj52iI6IiIiURvYZmNu3b+Py5cvSdmZmJtLS0uDp6Yl27dohMjIS2dnZ2LFjB4Cy4mXWrFnYvHkzBg8ejNzcXACAq6srdDodACAqKgqDBw9Gly5doNfrsWXLFqSlpWHr1q22WCMRERE1MbLPwHz99dfo27ev9A6hhQsXom/fvlixYgUAICcnB1euXJH6v/322ygpKUFYWBh8fHykW3h4uNTn5s2bmDt3Lrp3746QkBBkZ2cjJSUFDz74YF3XR0RERE2Q7DMwQUFBqOm639jYWJPtpKSkWufctGkTNm3aJDcUIiIiukfxu5CIiIhIcVjAEBERkeKwgCEiIiLFYQFDREREisMChoiIiBSHBQwREREpDgsYIiIiUhwWMERERKQ4LGCIiIhIcVjAEBERkeKwgCEiIiLFYQFDREREisMChoiIiBSHBQwREREpDgsYIiIiUhwWMERERKQ4LGCIiIhIcVjAEBERkeKwgCEiIiLFYQFDREREisMChoiIiBSHBQwREREpDgsYIiIiUhwWMERERKQ4LGCIiIhIcVjAEBERkeKwgCEiIiLFYQFDREREisMChoiIiBSHBQwREREpDgsYIiIiUhzZBUxKSgomTpwIX19fqFQqHDhwoNYxycnJ6N+/P1xcXNCpUye89dZbVfrExcXB398fGo0G/v7+iI+PlxsaEVH9eeklYPVq8/etXl12vz3naShKj7+u7qX1N/K1yi5g7ty5gz59+uCNN96wqH9mZibGjRuHYcOG4fz581i6dCkWLFiAuLg4qU9qaiqmTZuGmTNnIj09HTNnzsTUqVNx+vRpueEREdUPR0dgxYqqv9BXry5rd3S07zwNRenx19W9tP7GvlZRBwBEfHx8jX0WLVokunXrZtL29NNPi8GDB0vbU6dOFWPGjDHpM3r0aDF9+nSLY8nPzxcARH5+vsVjzCkuLhYHDhwQxcXFdZqHLMec2xfzXQerVgkBlP00t12NKjm3cp5GQwHx1+txroD124yMtVqbc2ufv53qu0BKTU1FSEiISdvo0aOxfft2GAwGqNVqpKamIiIiokqf6OjoauctKipCUVGRtK3X6wEABoMBBoPB6njLx9ZlDpKHObcv5rsOliyBQ2kpHFesgHj5ZaiKi1G6ciWMS5YANeSzSs6tnKfRUED89XqcK2D9NiNjrdbm3NrHqN4LmNzcXLRp08akrU2bNigpKcGNGzfg4+NTbZ/c3Nxq5123bh2ioqKqtB85cgRubm51jjsxMbHOc5A8zLl9Md9W6tsXE5yc4FhcjFInJ3zSty+QkGDRUJOc12GeRkEh8dfbca6Q9duEzLXKzfndu3etCqveCxgAUKlUJttCiCrt5vpUbqsoMjISCxculLb1ej38/PwQEhICrVZrdawGgwGJiYkIDg6GWq22eh6yHHNuX8x33TisWQPHkhIIZ2c4FhdjwvnzML74Yo1jzOXcmnkak8Yef30f5419/bZk6VqtzXn5Kyhy1XsB4+3tXeVMyvXr1+Hk5ISWLVvW2KfyWZmKNBoNNBpNlXa1Wm2Tg9VW85DlmHP7Yr6tsHo1EBUFrFoF1fLlwOrVcFyxAo6OjsDy5bUOl3Jex3kanILir5fjXEHrrzMr1io359Y+PvVewAQEBODjjz82aTty5AgGDBggBR0QEIDExEST62COHDmCIUOG1Hd4RESWKX/nxapV//eLu/znihWm2/aYp6EoPf66upfW38jXKruAuX37Ni5fvixtZ2ZmIi0tDZ6enmjXrh0iIyORnZ2NHTt2AACeeeYZvPHGG1i4cCH+/ve/IzU1Fdu3b8dHH30kzREeHo7AwEBs2LABkyZNwsGDB3H06FGcOHHCBkskIrKB0lLTX+TlyrdLS+07T0NRevx1dS+tv7GvVdZ7loQQx44dEwCq3EJDQ4UQQoSGhorhw4ebjElKShJ9+/YVzs7OokOHDmLbtm1V5t27d6/o2rWrUKvVolu3biIuLk5WXHwbtXIx5/bFfNsfc25/zLn9Nfq3UQcFBUkX4ZoTGxtbpW348OE4d+5cjfNOmTIFU6ZMkRsOERER3YP4XUhERESkOCxgiIiISHFYwBAREZHisIAhIiIixWEBQ0RERIrDAoaIiIgUhwUMERERKQ4LGCIiIlIcFjBERESkOPX+ZY72Uv7pwNZ+LXc5g8GAu3fvQq/X85t67YQ5ty/m2/6Yc/tjzu3P2pyXP2/X9Cn/5jSZAubWrVsAAD8/vwaOhIiIiOS6desWdDqdxf1VQm7J00gZjUZcu3YNHh4eUKlUVs+j1+vh5+eHq1evQqvV2jBCqg5zbl/Mt/0x5/bHnNuftTkXQuDWrVvw9fWFg4PlV7Y0mTMwDg4OaNu2rc3m02q1POjtjDm3L+bb/phz+2PO7c+anMs581KOF/ESERGR4rCAISIiIsVhAVOJRqPBypUrodFoGjqUewZzbl/Mt/0x5/bHnNufvXPeZC7iJSIionsHz8AQERGR4rCAISIiIsVhAUNERESKwwKGiIiIFIcFTAVvvvkmOnbsCBcXF/Tv3x/Hjx9v6JAUad26dRg4cCA8PDzg5eWFyZMn49KlSyZ9hBB46aWX4OvrC1dXVwQFBeG7774z6VNUVIT58+ejVatWcHd3xyOPPIJffvnFnktRrHXr1kGlUuG5556T2phz28vOzsZf/vIXtGzZEm5ubnjggQdw9uxZ6X7m3LZKSkqwbNkydOzYEa6urujUqRNWrVoFo9Eo9WHO6yYlJQUTJ06Er68vVCoVDhw4YHK/rfKbl5eHmTNnQqfTQafTYebMmbh586a8YAUJIYTYvXu3UKvV4t133xUXL14U4eHhwt3dXWRlZTV0aIozevRoERMTI7799luRlpYmxo8fL9q1aydu374t9Vm/fr3w8PAQcXFx4sKFC2LatGnCx8dH6PV6qc8zzzwj7rvvPpGYmCjOnTsnRowYIfr06SNKSkoaYlmKcebMGdGhQwfRu3dvER4eLrUz57b1xx9/iPbt24vZs2eL06dPi8zMTHH06FFx+fJlqQ9zblsvv/yyaNmypfjkk09EZmam2Lt3r2jWrJmIjo6W+jDndZOQkCBefPFFERcXJwCI+Ph4k/ttld8xY8aInj17ipMnT4qTJ0+Knj17igkTJsiKlQXM/zz44IPimWeeMWnr1q2bWLJkSQNF1HRcv35dABDJyclCCCGMRqPw9vYW69evl/oUFhYKnU4n3nrrLSGEEDdv3hRqtVrs3r1b6pOdnS0cHBzEZ599Zt8FKMitW7dEly5dRGJiohg+fLhUwDDntrd48WIxdOjQau9nzm1v/Pjx4q9//atJ22OPPSb+8pe/CCGYc1urXMDYKr8XL14UAMSpU6ekPqmpqQKA+P777y2Ojy8hASguLsbZs2cREhJi0h4SEoKTJ082UFRNR35+PgDA09MTAJCZmYnc3FyTfGs0GgwfPlzK99mzZ2EwGEz6+Pr6omfPnnxMahAWFobx48dj1KhRJu3Mue0dOnQIAwYMwOOPPw4vLy/07dsX7777rnQ/c257Q4cOxeeff44ffvgBAJCeno4TJ05g3LhxAJjz+mar/KampkKn02HQoEFSn8GDB0On08l6DJrMlznWxY0bN1BaWoo2bdqYtLdp0wa5ubkNFFXTIITAwoULMXToUPTs2RMApJyay3dWVpbUx9nZGS1atKjSh4+Jebt378a5c+fw1VdfVbmPObe9n376Cdu2bcPChQuxdOlSnDlzBgsWLIBGo8GsWbOY83qwePFi5Ofno1u3bnB0dERpaSnWrFmDJ554AgCP8/pmq/zm5ubCy8uryvxeXl6yHgMWMBWoVCqTbSFElTaSZ968efjmm29w4sSJKvdZk28+JuZdvXoV4eHhOHLkCFxcXKrtx5zbjtFoxIABA7B27VoAQN++ffHdd99h27ZtmDVrltSPObedPXv2YOfOndi1axd69OiBtLQ0PPfcc/D19UVoaKjUjzmvX7bIr7n+ch8DvoQEoFWrVnB0dKxS+V2/fr1KpUmWmz9/Pg4dOoRjx46hbdu2Uru3tzcA1Jhvb29vFBcXIy8vr9o+9H/Onj2L69evo3///nBycoKTkxOSk5OxZcsWODk5STljzm3Hx8cH/v7+Jm3du3fHlStXAPA4rw8vvPAClixZgunTp6NXr16YOXMmIiIisG7dOgDMeX2zVX69vb3x66+/Vpn/t99+k/UYsIAB4OzsjP79+yMxMdGkPTExEUOGDGmgqJRLCIF58+Zh//79+OKLL9CxY0eT+zt27Ahvb2+TfBcXFyM5OVnKd//+/aFWq0365OTk4Ntvv+VjYsbIkSNx4cIFpKWlSbcBAwZgxowZSEtLQ6dOnZhzG3vooYeqfDzADz/8gPbt2wPgcV4f7t69CwcH06ctR0dH6W3UzHn9slV+AwICkJ+fjzNnzkh9Tp8+jfz8fHmPgeXXIzdt5W+j3r59u7h48aJ47rnnhLu7u/j5558bOjTF+cc//iF0Op1ISkoSOTk50u3u3btSn/Xr1wudTif2798vLly4IJ544gmzb8Vr27atOHr0qDh37px4+OGH+VZHGSq+C0kI5tzWzpw5I5ycnMSaNWvEjz/+KD788EPh5uYmdu7cKfVhzm0rNDRU3HfffdLbqPfv3y9atWolFi1aJPVhzuvm1q1b4vz58+L8+fMCgHjttdfE+fPnpY8UsVV+x4wZI3r37i1SU1NFamqq6NWrF99GXRdbt24V7du3F87OzqJfv37S235JHgBmbzExMVIfo9EoVq5cKby9vYVGoxGBgYHiwoULJvMUFBSIefPmCU9PT+Hq6iomTJggrly5YufVKFflAoY5t72PP/5Y9OzZU2g0GtGtWzfxzjvvmNzPnNuWXq8X4eHhol27dsLFxUV06tRJvPjii6KoqEjqw5zXzbFjx8z+/g4NDRVC2C6/v//+u5gxY4bw8PAQHh4eYsaMGSIvL09WrCohhLDiTBIRERFRg+E1MERERKQ4LGCIiIhIcVjAEBERkeKwgCEiIiLFYQFDREREisMChoiIiBSHBQwREREpDgsYIiIiUhwWMERERKQ4LGCIiIhIcVjAEBERkeKwgCEiIiLF+f+rzp1mgGX26AAAAABJRU5ErkJggg==", + "text/plain": [ + "
" + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], "source": [ - "# We'll count a detection when the softmax output for the wakeword exceeds the detection threshold det_thresh\n", + "# we'll count a detection when the softmax output for the wakeword exceeds the detection threshold det_thresh\n", "det_thresh = 0.95\n", "\n", "yy = model_tv(np.expand_dims(long_spec, 0))[0].numpy()\n", @@ -655,10 +955,131 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 52, "id": "b7c516d7-fd04-43e6-bfb2-0c92736f7f27", "metadata": {}, - "outputs": [], + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "False positive at 574.21s (sample 9187328)\n" + ] + }, + { + "data": { + "text/html": [ + "\n", + " \n", + " " + ], + "text/plain": [ + "" + ] + }, + "metadata": {}, + "output_type": "display_data" + }, + { + "name": "stdout", + "output_type": "stream", + "text": [ + "False positive at 612.80s (sample 9804800)\n" + ] + }, + { + "data": { + "text/html": [ + "\n", + " \n", + " " + ], + "text/plain": [ + "" + ] + }, + "metadata": {}, + "output_type": "display_data" + }, + { + "name": "stdout", + "output_type": "stream", + "text": [ + "False positive at 715.58s (sample 11449344)\n" + ] + }, + { + "data": { + "text/html": [ + "\n", + " \n", + " " + ], + "text/plain": [ + "" + ] + }, + "metadata": {}, + "output_type": "display_data" + }, + { + "name": "stdout", + "output_type": "stream", + "text": [ + "False positive at 854.14s (sample 13666304)\n" + ] + }, + { + "data": { + "text/html": [ + "\n", + " \n", + " " + ], + "text/plain": [ + "" + ] + }, + "metadata": {}, + "output_type": "display_data" + }, + { + "name": "stdout", + "output_type": "stream", + "text": [ + "False positive at 981.22s (sample 15699456)\n" + ] + }, + { + "data": { + "text/html": [ + "\n", + " \n", + " " + ], + "text/plain": [ + "" + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], "source": [ "num_fp_clips_to_show = np.minimum(5, np.sum(ww_false_detects, dtype=np.int32))\n", "for i in range(num_fp_clips_to_show):\n", @@ -670,10 +1091,131 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 53, "id": "271ea3db-f803-4427-9efa-10c565f4eed1", "metadata": {}, - "outputs": [], + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "False negative at 127.88s (sample 2046032)\n" + ] + }, + { + "data": { + "text/html": [ + "\n", + " \n", + " " + ], + "text/plain": [ + "" + ] + }, + "metadata": {}, + "output_type": "display_data" + }, + { + "name": "stdout", + "output_type": "stream", + "text": [ + "False negative at 198.49s (sample 3175764)\n" + ] + }, + { + "data": { + "text/html": [ + "\n", + " \n", + " " + ], + "text/plain": [ + "" + ] + }, + "metadata": {}, + "output_type": "display_data" + }, + { + "name": "stdout", + "output_type": "stream", + "text": [ + "False negative at 254.19s (sample 4067114)\n" + ] + }, + { + "data": { + "text/html": [ + "\n", + " \n", + " " + ], + "text/plain": [ + "" + ] + }, + "metadata": {}, + "output_type": "display_data" + }, + { + "name": "stdout", + "output_type": "stream", + "text": [ + "False negative at 335.73s (sample 5371610)\n" + ] + }, + { + "data": { + "text/html": [ + "\n", + " \n", + " " + ], + "text/plain": [ + "" + ] + }, + "metadata": {}, + "output_type": "display_data" + }, + { + "name": "stdout", + "output_type": "stream", + "text": [ + "False negative at 441.26s (sample 7060092)\n" + ] + }, + { + "data": { + "text/html": [ + "\n", + " \n", + " " + ], + "text/plain": [ + "" + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], "source": [ "num_fn_clips_to_show = np.minimum(5, np.sum(ww_false_rejects, dtype=np.int32))\n", "for i in range(num_fn_clips_to_show):\n", @@ -685,7 +1227,7 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 54, "id": "b61c2abe-1f3a-4250-b25e-ae5c059fb7b0", "metadata": {}, "outputs": [], @@ -729,18 +1271,54 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 55, "id": "1fcfc9ab-0de7-482e-8a8a-7d79ed8a48b2", "metadata": {}, - "outputs": [], + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "Examining clip from 9155328 to 9219328\n", + "t_yy shape = (95,), yy_clip shape = (95, 3)\n" + ] + }, + { + "data": { + "text/html": [ + "\n", + " \n", + " " + ], + "text/plain": [ + "" + ] + }, + "metadata": {}, + "output_type": "display_data" + }, + { + "data": { + "image/png": "iVBORw0KGgoAAAANSUhEUgAAAnYAAAHWCAYAAAD6oMSKAAAAOnRFWHRTb2Z0d2FyZQBNYXRwbG90bGliIHZlcnNpb24zLjEwLjAsIGh0dHBzOi8vbWF0cGxvdGxpYi5vcmcvlHJYcgAAAAlwSFlzAAAPYQAAD2EBqD+naQAA8u1JREFUeJzsnXd8VtX9xz/PfrL3ggTC3iB7CKKiKI66Wm1tqdZRcSPtz4p0qG3FamvRqlirVVu3Iq1bsDJUQAHZG0lIIHs+SZ48+/7+CBnnfE+SJyHPyJPv21decu9z7r3nnnPuued+p07TNA0MwzAMwzBMr0cf6gowDMMwDMMwPQMv7BiGYRiGYSIEXtgxDMMwDMNECLywYxiGYRiGiRB4YccwDMMwDBMh8MKOYRiGYRgmQuCFHcMwDMMwTITACzuGYRiGYZgIwRjqCvQ0Pp8PRUVFiIuLg06nC3V1GIZhGIZhTgtN01BXV4d+/fpBr+9YJhdxC7uioiLk5OSEuhoMwzAMwzA9SmFhIbKzszssE3ELu7i4OABNNx8fHx/i2jAMwzAMw5weNpsNOTk5LWucjoi4hV2z+jU+Pp4XdgzDMAzDRAz+mJix8wTDMAzDMEyEwAs7hmEYhmH6BNvyq3Dbq9tRVNMY6qoEjIhTxTIMwzAMw7SlvM6JUpsD3392MwCgusGN138+I8S1Cgy8sGMYhmEYJqKZ+sfPhO2CKnuIahJ4WBXLMAzDMAwTIfDCjmEYhmEYJkLghR3DMAwTEWiahmc3fIf1h8pCXRWGCRm8sGMYhgkQtXY3tuVXQdO0UFelT7DxSAUe+fggrn9xa6irwjAhgxd2DMOEJS99lYf3dhWFuhqnxfwVG/D9Zzfj030loa5Kn+BkdeSGsGD8w+H2YmdhDXy+vvsxxQs7hmHCjmPl9Xjg/f246/Udoa7KaVFqcwIAPtnLCzuGCQY3vrwVlz/9FV7enB/qqoQMXtgxTCcEQo3GqrmOqba7QnZtTdOwLb8K1Q0d18Hn0+D0eP06Zx8WHgQVP7ItMRHOV0crAQD/3nK8w3KRPAfzwo5hOuCd7Scw9Y//w+4TNT12zpc35WPQ0o/wlzWHeuycTM+x7lAZvv/sZsx9bF2H5X743BaM+90a1Da6Oz2nL4JfIuFE22Z+7euC0FWECTldeeS2H6/Ci1/ldWuxZ3O4YXd5unxcIOGFHcN0wC/f3oWKeie+99RX+PpYZbfP4/H6sOKzw9iaX4XfvbcPAPC3z4/2VDWZDmhwero0Ya/dXwoAsDk6nqy/ya+Cy+vDxsPlnZ6T13XB5/7Ve0JdBSaEdOVj6qqVm/Hg+/vx6b7SLl3D4fZi/ANrMPq3n3a1egGFF3YM4yfXPLel28e+sbUQKz47gh+cSmcTClweH/7v7V34786TIatDsPmuvB5jfvcpbn3l25DWQwOv7IIBq2KZZjpb16l+XvTKdnxbUO33NcI1ewUv7MIQn0+Dx+sLdTWYTrh/9R4sfXe3X2WPlTco97s8wevnt7cX4u3tJ3D3GzuDds1Q869N+QCATwLolerPYsLHj3PAcXq8LBnt47SVzHcmsWvvsb3ymU3C+YpqGvHWtkJ8tKeYXGvFZ4eV1w41AV/YPfPMMxg0aBCsVismT56ML774ot2yxcXFuPbaazFixAjo9XosXrw40NULOzRNw4VPbMTsP63jxV0YU2t347WvC/D6N4Wo6sTIHmhfYnPJ376AN0iW9ZX1oXNI8Jd/bzmOe9/ZFVJng0DMz2xjF1hWfHYYI379Cb7O6765BNP7aWve0vzIHS2rx4lqtWTN3ck79i9rDmPWI5/j3nd247ZXRan/pu8q8dGe1g/GcHrEA7qwe/PNN7F48WIsW7YMO3bswJw5c7BgwQIUFKiNWp1OJ9LS0rBs2TJMmDAhkFULW3wacLi0HiU2B46HqZiXATxtRDCn89I+XFqPx9cGx4ni7e2FQbnO6fCb/+zFW9tOYN3BnskcoAsT3VwYzfkRR3FtI1Z8dgQA8N+dReS3YPNNXhU7boSIx9eKErQauwvnPb4Bs/9EHaGKah0Ytuxj/H3Dd+S3Oocbe0/W4ql1oh10W6lceZ2zB2veswR0Yff444/jxhtvxE033YRRo0ZhxYoVyMnJwcqVK5Xlc3Nz8cQTT+CnP/0pEhISAlm1sCWcxLnNONzesB7EoaBtL53u0uH5L/JO8wz+UVjV+UvO69PwTV4VGl3+hfEIFHWdOC4EkvYewW35VVjy5s5uPQsbDpVj6bt7Qt6uvQ2H24t9RbUdzoszl3/e7m8HS+oCUa12cXl8uPrvm3H/6j3YchrOVsFi03cVePSTg51KrnojGvyb85Z/fJDsm//Xjbjkb1+S/XVOD/678yRqG93EBCOc3twBW9i5XC5s374d8+fPF/bPnz8fmzZtaucopi21jW68vCnfL1VfIDnv8Q2Y+sfPUFDJEsR3tp8AIL78T1cqZNCHh1QJAJ7beAxX/30zfvbSNyGtR2cxqPylO13Tntr8+89uxrs7TmKZ5G2p82Np7/L68Po3Bfj7RiodYNrnJ89/jYuf/BLvfts9h59gP1mz/9S6yAxXw/q2XPuPr/HM+u/wxjeRJ2H0aVq3nWmKax3K/UtX7cHdb+zEra9sJ7+Fk1AmYAu7iooKeL1eZGRkCPszMjJQUtJzhsxOpxM2m034ixTuen0HfvfePtz8r23K378+VtlhfLVdhTVY8tZOlNrUg9RfTpxK0/P5wa65gocjT31+BOc9vgE1fgTA3X6cekf98u1d+OJIufDy92fu6OiZN4RAXdieNOHVr4+f+r0qmNXpkF++vQu7CmtQ5+g8XlwwOH4aHzhFNZzyqitsO/UMvtbNhcfPXtqKHz+/JWgv3bI20tyteVVwe329wla6NyxCO0LTNDxwKoxUM4Gw0/3wlAPFpu8qw8bMQ0XAnSfkm9c0rUcbZPny5UhISGj5y8nJ6bFzh4JN37W+cJsXVKoFRkW9E9c8twXfe+qrds912dNf4d1vTxKjz+7iDZ8Pkm7z5zWHcbSsHs9tPNZp2fYMbg+X1ksSu9Orkz4EErv2vtDDca56Z/sJXPb0V7j4yVbViKZpeGtrIfaerCXlvzxSgT0nmvb7I02TeWvbiQ5/Px2byjD6qA9bPF4f0VJsP16Nt7d13UZU05oyEQTDlERePL69/QRmPPw/nP3n9eS3oppG3P7qt9iWHx4fUOG8SPGHzccq8dIpD/i2VAZR2xVOj3bAFnapqakwGAxEOldWVkakeKfD0qVLUVtb2/JXWBj+BuLt4fb68NN/+qcC64r9xvbj1djgRxDVzoikpMr+eKK2N9n9/oP9mP7w/9ot9+v/7MHFT37hd7qpYKhiHe7eb9vVVqrwvwNluHfVbmIHc7KmET954Wtc+hS1j+kOz238DrsKa/DSV612kEfK6k/rnMfK6/HZ/t4v/Q4U3392Myb9fi2OlIr2cf/3zu5uz0GHSgNva6datFc2uHCiuhEuSWr3i7d24cM9xfh+iOJa7i+yYflHB1q2m2egL49UYNN3FSGp0+mgssktr3Pijh4SaqgI56VwwBZ2ZrMZkydPxtq1a4X9a9euxaxZs3rsOhaLBfHx8cJfb2WOwnOnPe54rTU5uj9qhgclMXVH5FU04Ol1R/HW1kJhAVRW5/A7+8Jn+0vDOhBuT36hNrq8WPjC13j16+N46P39eGVLAfYV2fDZfv88O/VB+Fqe8ofPhO3evkQ/WKI2uThZ3arqLKyy49PTjF/38EcHcdnTX+GB9/cL+0vascHRNA3rDpa1q3K1u7w49y8bcNO/tmHzd+FvXB8KdhbWAAD+o5g/vv/sJtTam1TyDrcXP3jWP3vthS98g01HO1+wFNc2tiup74yOnilZchxq1edFT36Bv7fRWuh0Otgcbvzkha9x7T++9vujNFxobw6tcwbPCSucpPHGQJ58yZIlWLhwIaZMmYKZM2fiueeeQ0FBARYtWgSgSdp28uRJ/Otf/2o5ZufOnQCA+vp6lJeXY+fOnTCbzRg9enQgqxoWlHRgC3fRE19gf7ENX9x7DnKSo4XfNA1odHsQbW7qTo/Xh9tfk75U2ox7n0/DS5vyMXFAIiYOSCLXOufP61v+3fZL8x9f5OEfX+ThxZ9NxTkj0oVj7C4PbI0eZCZYAQA3nbILHJIWC6tJj6HpcQCa8upFmQwwGUIbG9uftZS/y60XN+XhiyMV+OKI+OJotsM7VFKnVBM0E4ymqJcmuP/uLEK13Y2XfzZVWOR2R3UZTrT9yJnzqP8fSl3lDx+2LvRWfHYY+4pqce+FI7F2fyl+/u8mw+r8Ry4mx33YJsjp7hM1mDkkpUfrdbKmEduPV+PicVlh5ZTTHZ5eRx1Nvi2owS/e3oWnrp2IVd+ewNZ8/7MEfLy3BLOGprb7u8fra/GwPfj7C2Ex6qHT6fDq18fh8Wr4yYyBeHrdUUzJTcKsIfQ8HX1gEw/KEK4CVNfW6cQg6h6vBktAVwc9SyiGOvWKDZ+VXUC77pprrkFlZSUeeughFBcXY+zYsfjoo48wcOBAAE0BieWYdhMnTmz59/bt2/Haa69h4MCByM/PD2RVQ05nD/r+4iYJxZxH12FqrrgYe3rdUfxl7WE8+5NJuHBsFv53sIzkvGs7Bj/cU4yHPmh6MalePm1p9gJty7vfnsQz647iqknZ+OG0AXjt64KWvIz/vnEa5gxLaynbrCq7e94wTM1Nxk9e+BoDU6Kx4f/O6fC6vYl/b1Z7cDYvki5YsbHD4wMtsWvPUWTj4XLc+foOPHXtJABNpgChliT4S9vHpdbuRkK0qWl/kK5vbxO25EhZPY6U1eOG2YMEG9nH13Qcn/D93UW4Ze6QHq3XnD99Dp8G1NpdWDgzt0fPHS58dqAUI3/zSZePkx+z/+48iaRoM84a3jRf2duYK9y3aje+PFqJd2+dhWWr9wIAPtpTjK/zmmzixvVPwPIrx2Fs/9awXP6OPafHi6J2JL7BQHYyAJreDwuf/7plu97pgcWox4d7ijFtUDKyEqKCWMOuEwoTwXAOXRRwWcFtt92G/Px8OJ1ObN++HWeddVbLby+99BLWr18vlNc0jfxF+qIO6JoYV/5K/cupoIz3vdu0uOrMnqqtjVCzqvVgiQ2vfn2c2LA0q0Xa8v6uImzNr8Z97+6B16cJybb/1c4i54n/HcFPXmiaOE7Hq7Cn8OcLz9/Jwt7BA17mh0dye671PcUihWt+Mx/sLsbRU+Phb/87EtB6dMbrfno+1js9LWMeAG55ZRsuf/qrHglq7K8Nl2poyOnhnvz8qKJUK3tP9rwHf3P1vzrKal6Zf20+jor6JieKwio77n5jp2DTrLXpvv/sLEJFvRN/+7z1mWhe1AHAnpO1uOGlrcL5/Z3Dl7y1qxu17zleVszRh0rqBLXl9If/h7+sPYy739gpaHDCFac7+J7H//eOmE4ynFSxnCs2TOiJMeHvwGr7Uhpy/0d4+KMDuHDFF1i2ei+e6OLLXY7ns3Z/aYsNTDjjj8rxdL/Iimsbe8yI/3ToLHTJZweapLty7LiHPzqglNgGguoGF5a+u6fzggD+2mZRBzTd387CGvzspa0tnuTd5d0d/tmF5lXS3L8a0KHKvSc5WGLD2gA5YOTe9yFy7/uQaBE+3F1MHBp6G4tOqcnL6lo/pvYV1cLh9sLbjoqyPcrqnHh/VxEqTy0WO1LFNZ/67W2F+HB3cbvlQsX/FB9FK9c3qcIdbh+u++c3eOHLPKUXels0TeuSB7KmaThYYuuyc5fT48UfPtiPr07ZTYZ6sRxu8MIuTOgJmwufpqG2Ub2oamtH1fzV2kzb0B9dXditUbxcJjy0pkvnCFfkL7Ku8ocPD6DUFtqMHc1hPzrikVOR12VP4ec2HsMv3w7OhNnYhYl9awchIk63vt/4mWu0rT1SMxt7wPPcXy5c8QVu/tc27FJI1LtKc9aBbwuqcXUbL81jFa33uPFwOW5/7Vuc/9eN0DQNv/7PHjy9rmOJZDiyTRE66uInv8T3n92k9Abt7APwztd34Ad/79yzNb+yAVc885VyTglm4He7q3vOBBsOl+P3H+zHJX/7ktjrtmXZf/Zi6h8/wwe7i9otAwCrtp/AD5/bjD9+2CRUuOKZVieYN7cWCFEc3t9VhLe2itEuHvvkEJ7/Mg8/fv5ruDy+Ls0ffYFeZB4Z2fSExK7O4cGEB9dgzjBq2Ftqc+CTvcU4f3QmXg2DPIZHy+oxODVGiOH23q4i/GfHSfz16jNabKYCRWeq2FBn++gp/JUYapoGWwjTePmr9i61ObDbj8Vqd1HFjPSXDYe6vrCzOdyIt9Kx/s72ExiUGoPJA6lzU1sOltgwISeR7Pe3PYtrGzH3sfW4cmJ/vCG9PNuqt/a0kdQcKK7DK1ua5pDbzxnq34XCiCYTH3Hf3pM2IdJAM/60Y/Mi/5Z/t2/yMP+v7dvZnvXYOrx72yxMUjiy9TTPrj/9zCe2RjdMBh0sRgP5rTlH7p8/PYRLxvdTHl9mc+AXpz7AmrUJB4pt2F9kg04H/GpVk+Q+/5GL4fNpuPP1pn7ZUViNynoXnv3JZDz/ZWv4oZU9cE89gdvrg9VE2yQUsMQuApG9M4GmRd+iV77tdgT3nua8xze0OHA0c9frO/D5wbIuSw27w5OfHyWSy7Y0BNFNHgDueO1bYqMVTAYt/ajD3zVNw4dt7PFCxZ8+oXkd/eWd7Sc6VK9vP16F7xSSOH/5pBuhVcY/sAaHpHymW/Or8Mu3d+GqlYFPvfjiV/lweXxkUQe0H4jZEcBQGMHwFj33Lxs6tItti6pdVBwtq8P6bizsm7nymU1ByazSmd2nP8x65HOM+PUnuOKZr4Tn6ZO9rSpmDe3betvauc+LnvwC17SRfv7g2U14e3tr+7/+TSHW7C/FZU+LQfmbTUmYVnhhFyYEy/DyN//ZG5wL+UF79kiVDcFRX963qn1VqzPIi6wPdhdj9Y4me7Z3vz3hV8ytYOFwe7HhlCruvMc3hLQu3c0ZCjSpaeWPibZsCpHDQbPTiNvrw4e7i/FNGyP9UpsDv3hrV7upAzuaN1Z8dhhT/vBZt7MutFXNt5VctZX69KQ9rc+n4fJnAr+Yzato6FRV2FXOe7xjz3d/+Muaw50X8hOH24vqAGsddhTUYNRvP0HufR/ioff3Y9ErrSG2jlfaMfI3n7Qbb7I92moNtuZXt0jv2rJHsvOTt0NFGPlO8MIuXAinGDjBRJVHMVie60fK6uHzaShUhPjoSJoXKOocHuw5UYslb+3CtW1CD4SaZav34voXt3Ze8DQIVvy8178paPdlE4rUbkBTuBtN07DkrV24/bVv8dinrWFSfvn2Lqz69kS7qQPbc+LVNGDFZ0dQUe8UEtN3hV++vQuz//Q5sb1sa1f74qY8+bBu8/Hekh6xGeytHFc45HSXGcv/h4m/Xxs0k5J/fqUeBxeu+CIo1w8H2Cs2gpEnwRe+zMP8v27o9Ks5nAZFMPnHF3RCCFbeQk0Dlv1nD+Y8ug6vfi16hLpDkLj7Dx8eCAsvWplV3/a8Z6zb68P6Q2VBUT/JXBkEqVBX0OuAxz49hPd3USlSZ6rv9h6Vth+KHUmfO3rSjpTV40R1I177pqDdcBIrPjuCsx5dh//uPNnipVvb6Mb249VdUqt+k1dFg6oHkNP1ng4EPRlQuuaUJPV0bEYDRXtxP3s9YfQO54VdD/L8F8cw+refCLHffv/Bfhwurcf1L36DHz23BfuLej52VW/m3QAsGvyloMqO179psuH469rDeOzTg7jsqS/hcHtDsrCLdOoc7hbbxSf/dwTXv7gVPzslCfxoT/BCQNhdXjjcXuwrqhUWH8FI7abixU35eKYdA/DufvD5fZwft/zezpMd2r0WnIoJd/O/tmFfUS3m/3UDrlq5iQRJ74j/BdlOalMYpnP77MDpxWF0eXxEA9I8vh1ub9iEoVLF0YsEwknrxgu7HuQPHx6A0+PD/Yp4XPuKbNh8rBILX1Cr2PqqxO5IWT2eWX8Ua9oYnofm9arD0+u+w64TtXj325Nwe0PfIaFMO9TTuDw+jHtgDcb87lN4fRre2ta0oG4OP9GR7Vsg+NE/tuDiJ78U8pGGaF1HpPxtESVvXlTUOzsMN9GMn3GW/VKBdyVt17HyhpYQP13J0xssKX2k4vb6MP3hzzD3sfXCvNE8Vib9fm3EhKEKV8JpuuZwJ0GmUrJ5aHB68M72E5itCFHSV3j0k45TLwWDtjZ1Hp/P7wwEgUTTTm+xEaiF4dfHKjElN7lLqqO2DjFyLC1/Yu31NDsKagAAb24txBUTswGE6oOiY9p24Yhf0zRa7S8K/ev7nh4j29rEGOzs3I9+chAen4b7LxoVskV1uNG8EFv8xg5cPD6rZWx2RnGNA9V2N6rtbtz1xs6W/e/tKsKVk7L99gIOBAue+ALfm9APt57ds+nzwo3QvzFa4YXdaWJ3eaDX6YT4NY1uLy5+8ouWHIQd8YcPD/idSqnPEKBJ3t9wIu9sP4G80wh70VN4NQ36bjRGYZUdP3tpK6bmJgegVsA1z23BL84fjjvnDfP7mLbrjyZngdbtUNsVapqGRz891CUJU7jw6//sxU9mDCT7ZbXe1vwqZCdFIdZixOvfFOCicVnITorG39sEJ+8J2qrZOpLCNTg9Lernm+YM6tE69GbG/u5TXDQuE58dKMNnB8pwxcRsnKxpxLqDZfj+5GwcKqmDy+sjz3bboN1tbTVPJwRLT3Gg2IYDxbbIX9iFkciOF3angcvjw+jffgqzUY+DD13Ysj/vVMT2fX7Y031+kGPwBAvZQaI9AhkAtyu0F0esMx54bx+OltUHNObcX9Ye7trCrp3QGaFGBx12nagNmyCnMl0ZAR05ovzgVEaJKyf1x7vfnsTDHx3E+3fMPs3adU5RTSM+3luCq6dkI65NIOa26bs8Xi0spaWh4qM94gfGghUbYXN48OJXeS1xFo16HXb9bj5iLEaU1LYG/FURzMwWHeHy+HCiOjzqEgjCZ1nHNnbdRtM03Phyk+G3y+PrctyzY+X1aHR5w0ovHy4EIvTF9uNVePD94NpxnS7dHRuBDCDbln9vzkdJraPTcntP1goORaerYu5JNGiwtZOGLxzoSgy6p9d1vjhtG6sv0JLSDYfLMeuRz/H7D/b7nQeYEXlza0FLbLe2wbM9Pg1jfvcpAOCZ9R0HHT7rsXWBq2AXePXr41j0SvvZOXo74fQuZ4ldN9lRWCNkeOiKR8zW/KqWL2iGEoiX/lUre197d2RUHw785r/78Nv39uHoHy9q197O4/Xhkr+JC4hwu6twWWR2lxe/ysO6Q+V+5aoNZqi+tjHUPthdjGumlmPOMGqe0tvbP5CoAvTK/KuXeJn2tg/rrsJesRGAQzJG7UogyA8U8aoYkS+PVOCpz4/g1le2t5uaJtLprio2WMF+gaav1Bteaj94sVdxD/9sk+cx1OhO/debefD9/X4t6gCgyA8Ja6BY+MI32PRdhdIWKXxeib2L/+7sfiYWpocJo0HMErtuIqu7Zv8pPMTdkcA720/gne2t8e3G9s/DbWcPge5UhP6TNY3onxgV8SESHG4f6p2NyEqI6tJxwW6WDYfL8f2Vm3D3ecOIREa1Nn187WGkx1mCVLvOifBhFFZc+4+vYTbo8dLPprbs+8Vbu8Iyrlxv4O42HrBMaAmjdR1L7LrL6RhbR2qAxkDx2KeHMGjpR3B7fXh63VHM/tM6PPTBfry3q6jDpO7NqNKW9QYuWLERM5d/3pIC64Uv81ryyTbj8frw4Pv78MneJoPrGrtLMBEIFtuOV2PhC9+g1OaAx+vD3pO18Pm0sLI7aQ9e1wUXl9cnpMzjRR0TCYTTXMcSu25SVBM6lUZf5bP9pfjzqUTZL36Vjxe/ykditAmTBiTh6ik52FdUi7vmDYPJIH6v/HtL71xIN6v35XyLbWNbfXagtKUt8h+5GP/3zu6g1lFm+sP/a/n34vOGYVz/BGW5sm4mpu9pvJoWVnl5GYbpnYSTjR0v7LpJOMWs6Svc+irNJVljd+Pzg2X4/GBT3K7kGDN+dqYYF8tf+6PewmtfF2Bc/wSMy05AQZUYPmD9odNLS9STrPis/TRU4cI3eVWdF2IYhumEcFoS8MKum4S5w2Kf5ZgisHBDCKOuB4L7Vzd5yuU/crEwmTg93rBIhcYwDNPXCKeZl23sukmJjVWx4ci/txzHzf/aJgTEjVSpzPu7ivDut61ecaqUUwzDMEzgCSctHkvsmIhj7f5SfJNfhSFpsVj4QuTaT935+o5QV4FhGIYBq2IZJuCsO1iGHz63JdTVYBiGYZigwqpYJiLp6eTmDMMwDNMe4SSx44UdwzAMwzDMaRBO4U4CvrB75plnMGjQIFitVkyePBlffPFFh+U3bNiAyZMnw2q1YvDgwXj22WcDXUWGYRiGYZhu02ckdm+++SYWL16MZcuWYceOHZgzZw4WLFiAgoICZfm8vDxcdNFFmDNnDnbs2IH7778fd911F1atWhXIajIMwzAMw3SbMFrXQacF0Ed3+vTpmDRpElauXNmyb9SoUbj88suxfPlyUv5Xv/oV3nvvPRw4cKBl36JFi7Br1y5s3rzZr2vabDYkJCSgtrYW8fHxp38T7ZB734cBOzfDMAzDML2Hz38xF4PTYgN2/q6sbQImsXO5XNi+fTvmz58v7J8/fz42bdqkPGbz5s2k/AUXXIBt27bB7XYHqqoMwzAMwzDdJpwkdgELd1JRUQGv14uMjAxhf0ZGBkpKSpTHlJSUKMt7PB5UVFQgKyuLHON0OuF0tuadtNlsPVB7hmEYhmEY/+gzNnYAoNPphG1N08i+zsqr9jezfPlyJCQktPzl5OScZo0ZhmEYhmG6Qvis7AK2sEtNTYXBYCDSubKyMiKVayYzM1NZ3mg0IiUlRXnM0qVLUVtb2/JXWFjYMzfAMAzDMAzjB31CYmc2mzF58mSsXbtW2L927VrMmjVLeczMmTNJ+TVr1mDKlCkwmUzKYywWC+Lj44U/hmEYhmGYYBFG67rAqmKXLFmC559/Hv/85z9x4MAB3HPPPSgoKMCiRYsANEnbfvrTn7aUX7RoEY4fP44lS5bgwIED+Oc//4kXXngBv/zlLwNZTYZhGIZhmG4TThK7gOaKveaaa1BZWYmHHnoIxcXFGDt2LD766CMMHDgQAFBcXCzEtBs0aBA++ugj3HPPPXj66afRr18/PPnkk7jqqqsCWc1uMWlAIr4tqAl1NRiGYRiGCTH1zvCJ3BHQOHahIFhx7C5/+ivsLKwJ2PkZhmEYhukdLBibiZU/mRyw84dFHLtIJ6JWwwzDMAzDdJt6pyfUVWiBF3bdJMIEnb2eSQMScfWU7FBXg2EYhumD+MJoTcALu25S2xg++nQGePJHE/Ho9ycg/5GLQ10VhmEYpo/h84W6Bq3wwq6bHK+0h7oKDMMwDMOEAVoYGWjxwq6b3Dh7UKirwLShrRR8YEp0y7/PG6UOht0befmGaaGuAsMwDKMgxhzQICNdghd23eQ3l4wOdRX6NNdMycHeBy9o2U6Ls7T8+8Xrp+KS8Vn4+O45eP66KaGoXo+zdMFIzB6a2mm5Aw9dGITaMAzDMG2Zkpsc6iq0ED5LTIbpIrEWI3Y/MB+aD7CaDC37B6fF4qlrJ4WwZj2PBsCgbz/HcjNRZkOnZYLFmH7x2FdkC3U1mDDkJzMG4JUtBZ0XZJheAqtiGaYDuqI+jbeakBCtTjcXSagcrvonRmHywKSW7RmDw+eLEQD+8dMpfkkZmb6HUc+vHiayCCOnWJbYMeHH8ivH4bM/lnZYpiuSqWmDkvFNXtXpVissOPyHBXB7fdDrdDAb9TDodXB6vNh4uCLsFnZ6nQ6zhqbgy6MVoa4KE0Y8+L0xcHnCyIWQYSIM/mxieg37HrwAv7pwJIamx+LOc4f6fdyrN03H2nvOCmDNAkNbO85mMb/ZqEeMxYgos6FFNWsxGnD+6AzEWUMruTx/dAbeXjSzZVunA26aPRiPXjUev7pwZAhr1jkHf997bROfunZit477vwtG9HBNOmf/Qxfgulm5+OmsgUiJMbfs//5kjkHJMD0FL+x6gJmDU0JdhYhCpzAl65dgRYzFiFvPHoLPlsxFSqyFFmoHk0GPnOTozguGETMGJ/e6INjj+ydgSFpsy7amNS1Er56ag1vPHoJ3b5sVwtp1TFsbzd7GeaMy8MW953T5uMsn9g9AbdrnonGZiD7lOWgxGvDcT1vTL/3h8rFBrUu4s+t383HeqPRQV4PpAuE0X/PCrgdQLUSY7pMUbSb7RvdLOK1z9rYX95SByTh/dKutYRjNGe1iMenRkX/HuP4JgpRmQk5i4CulQJbebl12Xkjq0R1uO3tIqKvQbe6/aFS7v1lNBvz5BxOCWJvwJiHKhL/9KLIcwK6flRvqKgSUcJqjeWHXA3R3YfePn07B/NEZGJER17MV6sWkxlpg0Ovw8g3TMCw9Fn+6ahx+dmYu/nTVuFBXLaho0DAwJSbU1fCbqblJ+MmMgdC1eRhkLzGTQY8t989r2R7TrzWR9bRByeifGBX4igIYlhGH5FMLzF/OHy6Eygl3fO28PFJi6cdQWwamROOv14gLp2B+jz5w6WhkJ4lS81iLaDrA6liRKLMB09oJoRFtNnRLShtKHvjemFBXIaCE0bqOnSdCyfmjM3D+6Aw88N4+HCqtC3V1Qs6Ppw/AzXMGAwDmDk/D3CVzQ1KP80Zl4PODpe2+RIOB/PX3XXl9l88xKDUGeRUNPVSjjnl7UZOatc7RmmpP9QVrMujxwZ2z8f7uItxxzlC89nVTyIufzcqFTqfDole2B6W+W5edB6fH26IaDGf2P3QBRv/2UwDtq3uizcYOnYQ2/F/TImBqbjJ+tWo37jp3WGAq2w5GA5UhjMiMwx3nDEVmgjWodelNyB9HP5o2AHfPG4Y4qxExFiOWLhiJ5R8fBADkJEehsKqRnOPsEWmYkJ2IJ/53JCh1ZkIPS+x6gGHpcfjqvnNx3wK1gfjG/+tdX1ahYP9DF+CPV4xDbmrgpFRv/HxGp2WWnD8cz183BVkJwZEetUeW9LL73oR+IapJ1xAldmrG9k/A0gWjiLNHME0aDHpdWC3qOpJWtq1nR4nGX7lxOu5SOBW1DTmTnRSNV2+agelBtAuOsxhxyfgs5W+/vGAEfjJjYMv2/ReNDIoE9cog2xf6y7XTB+DLX7W+L66fRTMcZZ6yNwaAW+YOwRf3noOP756D5xaqg7G/eP3UwFS2C/QFG0pWxUYIq2+bhZtmD8IvLxiB/olRWDR3CO45bzhSJcP+AW1SXP3+8rFIi7Pgbz9q9WTraLLuKwTjJRtOKV864rqZA/HDaQMAAHsfvACfLj4LZ4/ouiF1IENKXDyu9UU9KqtVpdp2bdYVY+IBKdFBVQ2GG12ZA8Zni/amzfajZqMeS+aPwA1nDkJ2UucfJv4EvO4qi88TJYFRJgO+/e35SFTYzar4+VlD8E0bdX2gGJEZfuYvN5w5CA99b4ygsr54fBY+a6O5UAg+kZMcjVFZ8RiVFY9b5g4m59TpdJ2q6gPJWcPTWhbvbecNJnDwwu40mDggCb++ZDRiLa0LhrvPG4aty9qfmM7ITsQ398/DpW0kMG09CZnAIas1/nv7mSGqSfsc/P2FePCysTCdmsFjLcZuv4SGZQRuXK344Rl4+tpJuHb6APyjjXdjW6mbP2uV/9x+Jp6+dhLG9EuAvodFdheMEQNdnzcqPWztknya5pdE+cyhqfj3jdNbtq9QSJ5+e+lov+4zPc6COcN6NoD0bWe3Sgx/NG0A3r/zzJax7C+6IIhuf3Zm6HJ9D02nz+W/bpiG3146Wqmyblt+QCfe/bHSx+u9FzaFtPnh1AHdqWqPcEmbxVzbPN6RBmeeiHA6mpgsJj35/drpoXvo+jIdeWUuu7h9D75AEW029Ij37ieL5+CnMwfi0e+Px6whgVG5mQx6XDw+Cw9fMU6QMOi6KHc7IycRF59S0/V0MgI5rdzvLh0TtmFvNA2CobzFqG4MvU6HhCgTdvzmfPzlBxPaVXH5szjS6XR49ieTOy3XzFnD0zotYzbqsXXZefhm2Twsv3Ichqb3nGTsonGZPXYus1Hf417Zr7RZcLfHeaPSMX+0+MExIDm607Z95cbpuHH2IFzXiWfpDbPFBWtbae70QaEJYN7WKSaSI0iY23lmQ0H41CTCmDggEUDrZPjri0fh52cNxnCFB2xXv2iZ7uGP3dzMUwuhi3qxymBkZjweumws0uOsQR9bbRckXbWV6uqisCNGZMT1qufKpwF6vQ5bl52HzUvPRW47HtHNKtukGDOumpzdYmvVER29TP190R7+wwI8/1Nqw6UKcpwWZ0F6XM87ROh1OkzIPr2wR21ZMLbnFooAkJXYes9D0tT99/x1U3H1lBxhn8fbucnE7GGp+M0lo2ExdvzhF2Mx4okfnqH8LVTyJH0blf+Ppw/soGTvZuGM8Lm33jPz9TKe/+kUPPi9MXjy1EN205zBHcZxal4IMoGjo4XG1VOy8c6imZjaTniB3kqwJ3O9Xoedvz0f2399Xtelj6e5rnvlxulIjDZh4YyBeKtNBoyW03dy/lW30mOCRXMw2rQ4C7ISooSXIdDkJZ6VYMWMHnZ68HcxrdM1SSQGKxYsvz4l3e7JTBZf3z8P/7n9TMG+DABevmEafn/ZGFwwJgP/vnFaj12vu7S1lW5rU9qRxDQ3NQZL2zjaJQfL/i0MNIX9ghTSKBSEOvNPW3qHNXkvJCXW0qnYvC1v/nwmhv/648BVKMyYOzwNGw6XA4BgoxhsHvzeGPx350ksu3g0EqJC+2AGQksxaUAiNp5q52Dhr6G8zOna2M0eloodvzm/3ZdqZ+rJhKjgG5hfMj4LZw5NxWVniF7PF4zJwIFiGzLjm6RAL/1sKnxa9xweOrJ19LfJm4utWXwWhi4T56mb5gzGDWcOIovR0yEj3oqMeCr1S4w2Y+HMXCycmQugydHo5c3He+y6Mpef0Q//2Vmk/O36Wbm4ZHwWnl53FLWN7i7Fnbxl7hCMz07E0+uO4qHLeja+W3vjnJ30+g68sAsTwkk/HwymD05uWdj9faH/dj6ny7D0WBwpa40Jd92s3C4twANJIKbdW88egjirCb//YH+7ZZ7/6RTc9K9tAbh61zidZcFNp2yLOlq8dXb+UKQEGpkZhx9Noza2t509FINSY1pMA3Q6HQwBtk8yG/RwtaMWbG5Xo0GPzUvPxczln5/a3/R7Ty7q2kPVO4ZuGmb6/AxS2XY89U+MwsmapjhxW5ed16IB+OiuOfBpmuD4oAPwi/OH4y9rD7d77plDUlr6tydprydCsawbFMDwVUz79K3VRJgzuk3YiEgnNaZVLcofkoHDYjTgxtmDMLwDD9nzJGPu9ti67Dz83wUjiHqspzgdgd2d8zoPuNvZ+UMRkPrG2YOV+81GPS47o39AbNXa0rZNzhouesi29dxv23RtbVV70i6yM05Xortobms6tu509Ss3Tcf3J2fjf7+YK5h16PU6pTfrnfOGYcn5w7tT1dOivWYKhcQugn0lwhpe2IURU3OTQnLdC8f0rBGxP1w5qTVMQyR7SnWFQHriPn71Gd067uoprR5taXEW3H7OUGW4hp7gdBYJ7anRf35W68IpLbZjZ45QvPiizOGUw1hs/7/9aCJeuG4KXrlxersSuWA+uyaFyLIr179vwUg8+5PJePFnU/1Wac9sY9M4KDUGf/7BhC6Fp2p7FTnGX6AY11/tYBKSTDo8t4cEVsUy+NP3x8Pj8+GzA2VBu2bbL9xgBgvtnxQlqGLDiUB6jPVEGJVAYwyArvG+C0fionFZGJkZp5SqtCW9F+WMDRbzRvknzQ0k9144Av/efBy/mE+dM+aNSscLX+Z1eo6k6KaF/4Vd9IT9/uRsRJkNOKOboVHaLjwXnxcc6d3AlBh8cOdsGpS4l0nsdj8wH+MfWAOgKRSU3eVt+a2t+YjVpIfDHbhg7L0RltiFEaHSSCZEmfD8dYFNO9PWBX/YKYnPjt+cjy/uPYdk6ggkj1w5HgvGZuL1mzsPBhtJ9Aap6NTcZJw5NAWXn9G19Gm/7kDSqdfrcEZOol8L2xQ/x2Fvs4cd0699Ew9jGxu1tiE6pvkZ82zSgMBrGW47eyg23XeuMu3arCH+BVj++v7zyL62j0R7mTr0eh0undCv2/EPgxFsWcXY/gkkvNM5I7uevaYj/AmCPUwRx7C9mH0Wo17IYhPXxqnuvTtag8mfPzoD543OwOrbZmFabjLevmUW8h+5uCtVj3gCOkNVV1dj4cKFSEhIQEJCAhYuXIiampoOj3n33XdxwQUXIDU1FTqdDjt37gxkFfssdylskuRURT3JZWe0ql6bXxpJMeagB4zNTLBi5U8mB8RouS0TByTivDCQdnTEH68Yiw/unN1hmcwg5sw16HV49aYZWPHDiTi3Cy8hfxchPUV7eXubpULhwkd3zcHd84bh7g5UgAa9Dut+eTbW3nMW7po3DHOHp+E3l4zGG518+Hxx7zn4943Tgtb2p7NAeuG6KSFbjIfTB1XbrCBd5YdTc8i+9uJENoe9SYuz4A9X0ADaL7WTu9ag17V8pMkfI8kxFrz58xm4YmJ/PHLlOABNmZ/eWjQT4zp4b/14+gCcMyKt3biCXeVPV43Dqltn9ci5AklAVbHXXnstTpw4gU8++QQA8POf/xwLFy7E+++/3+4xDQ0NOPPMM/GDH/wAN998cyCr1yf5vwtGwKDXYWSA1Z8Pfm8MfvfePmHf/34xFx/vKcb1IUznEyyeuGYiBqREI/e+D0NdFSV/+9FEwTi+PaYPSsayi0YFzK6uJwi2hqk9W7yv7z8vrEIWje4Xj9EdSOuaaeu5+PIN/sWGy0mODtssHv5yzdQcLP/4YMv2j6bl4PVvClu2eyJrS0/HHTwdzEY9PrhzNi7525edlk2Ls6C8zgmgyanvvgUjMSg1pqW9RmTEEdOFj++eg0GpMbCaDLhpzqB2gynr9TrkJEehsKpR3K/T4cyhqdjwf2cjM8EKnU6HVbfOgtPtRXKMGdMHp2B6F9vzj1c0LQLPf3xDl45rj2tOpWbLf+TisJ3bgQBK7A4cOIBPPvkEzz//PGbOnImZM2fiH//4Bz744AMcOnSo3eMWLlyI3/72tzjvPCo6j3R68uOuPUeM288ZKniHtaUnX5DXzcrFCCnLxpC0WNxx7rCQxq0LFgNO5UTc/uvz8O5tof/Ck/s2SlJNts0q0NaZRq/T4eazBve4GqczOnsW2hrSB9uEob1QGZ1JhX514cgOf2eCS2K0uSW9181zBuOeNjZw9144Aq/1gLnGpAFJWHXrLHxzf/v5w4PJ2HYcK2T+2sbZ6qO75yAx2oyb5gzGW7fMxL4HL8DHd88RHGouHpeFUVnxLSYPnWXI+NcNNP1a89kGpsS0HD95YBJmDe3ZfMY9xbM/mdR5oRARsIXd5s2bkZCQgOnTWztwxowZSEhIwKZNm3rsOk6nEzabTfjrrfTkC+rhU18qoSSckiIHClU4g/PbhA9JibW0a4cUCm/k9pBDnvxo2gBMH5QcdDVnM52psBaMDV3Kt468C5tVPm2dLqfmJuHuecM6TeDOBJ+nfzwJny4+Cz+dORDp8VZ8ce85WHHNGbjlLPXHb3eYPDAJ6Ypgy+HEby4Z3fLvp66dqPxIMeh1mDYoGTEW42nHLRyUGoP37jhTsNNLjw+989Jbt/iffebCEM5BnREw0UlJSQnS0+lXfnp6OkpKSnrsOsuXL8eDDz7YY+frrcwZlgqzQY+fnzUYdQ5P0NUkw9JjYXd5cbKmscXoNVLj003NTcLW/GoAwM/OzMXjp4KQPvb98fjfgTK/I8k/u3By0MT58kKps65ZfmXoPww6ou17JRiBhX8wORtvbz8BQMwJKvPOoln4Oq8SB0vqsOKzIwCAtxc1SWw/3F0c8HoylI6Gh8mgF7zye0rF3JvU1MuvHIcfTRuA5BgTth+vxoKxWdh+vLpL55iQ03X77PHZiQCA12+egb99fgQPXUbt8brCqKx4HChWC3baC7wtYzX1Lseo9ujywu6BBx7odCG1detWAGqDV03TetRTaOnSpViyZEnLts1mQ04ONfTsDZxOq9w6d4ggsnZ6vKRMSkzgUiY9u3AyhqTForzO2aJqjdB1nfD13fYezxyaih9M6d7YC0LgfoGOFkOTB4YmnmJXGJ4Zh3kj03GyprHduF09xfcnZ+OxH0zA7ecMRb3Tgy+PVrT8lpsSjfxKe8t2UowZF47NwrGKBnKeviDBDjVj+sVjSFos3tvVmgYsmLEC37plJv695XiHntrhRnPmkysmZuOKidmdlBZZe89Z+PJoBX4yo/uhmnoqA0dHc6jDTd+HKtpK4++eNwxP/O/IadYqNHR5YXfHHXfghz/8YYdlcnNzsXv3bpSWlpLfysvLkZHRc96CFosFFkvoRbg9wZDTMFCXH4y2wV5X/ngSPt5bgrvmtXpFqRbXst2Vv3yyeE5L0M62EdkHJEfjaJjGjDsd2no/tl0fdScy/juLZuKhD/bjge/1bL5ImWQpf6tqifH5L+Zi03eVuEbhARcuvHvbLKw/VI4bZw/CradsRYMVUiL3lJPBxiOtuXeDkUqL8Z8XrpuKzASrsLCbGUQHhmkhNF8IBcMy4jAsI3hxSLvLlNzkdiXmby+aiZe+ysflE/tjYBtJ6z3nD8c95w8PayeJ9ujywi41NRWpqZ0bM86cORO1tbX45ptvMG1ak6fV119/jdraWsyaFXpj8nDk2mkD8Nv/7uu8oIKOXm5D02Px5I8mCvuapRxtjdCXXzUO8/7S6j100bhMHCmtx6whKR0m2h6Zqfa8e+TKcfjDhwewcGbgAu8Gg7Y5H+eNTMcvzh+BwqpGfH+y+HXb0frCZNDB7aXLqSm5yXjvjo5DjvQESTFmvHbTdFz7/NcA1OqpwWmxGNyFqPqhYNKApKDETmuL3K1XT8nBU58fxfmjMzB3eBqWvLULl4zPko5RZEngMPxBJy3OwovvDrhvgdqhJzel96iS/eGPl4/FiIw4jO0fj42HK3CwxIYtx6oANMXPnJrbuhj/bMlZiDK3Lo3mDk/DhsPlZL4PZwJmYzdq1ChceOGFuPnmm/H3v/8dQFO4k0suuQQjRrRGEB85ciSWL1+OK664AgBQVVWFgoICFBU1fXE1e9BmZmYiMzN8jM0DgdGgx8IZA/HvLe0vovylMyFGcowZW5edJ6gphqTF4rWbp+PafzS9/J/58eSW32IsRmQnReP+1Xv8rkN6vJUsKHs7z183BTqdriUsRK3d7ddxH901B29sLfQrSn6gCFfvMhUxYeQ5LXsEp8ZasOt381vieE3NTUY/RfBcGVbFBh553uMlXce0FyEhPd6K9++YjVhr+DyHp0NitLklduu5IzNQUe/EQ+/vb1FDt2WoFFT56R9PwheHy3H2iOBGBjgdAmop+Oqrr2LcuHGYP38+5s+fj/Hjx+Pf//63UObQoUOora1t2X7vvfcwceJEXHxxUyTpH/7wh5g4cSKeffbZQFY1bOiOVilGYUPiz2nS4ix+hx6598KRuHY6fQhm96LFQndpGwtMloy29R7ryJZnWEac4HkWagaG+Rf5/ReNCmjAbH+Isxjxyo3TsUCRhqptcNac5GiSe7Sz5/iWuYPx7xv9ixnH+I8sie5tWULCiXHZCUKMw3CnK+/O1FgLnvzRRL9s+2ItRiwYlxVmeZ07JqDL8eTkZLzyyisdlpGNuK+//npcf/31AaxVeHPHOUPx6b4SlNqcHZZ75Mpx2PRdJSYPTMK8UR1/SXRlwPtrJ6bTAUsXjMT3J4evPdbpsv3X56HO4emw/aLMBjx17UR4fRrireGVeUDFf28/E0U1jULqnnAkI96K9+6YHVL7lpRYM2YPC8yHy9IFvce4PtzR6eiC7skfTcQjHx3AyjZaByayidQoDN0hMuSsEUR6vBVbls7DoKUfkd+aJ7CfnZmLH04bgB8qxMitZbunhPD3qJGZ8fh5D8Z6CkdSYi0t+UN/ffEoJEWrvYovGd+13KahZEJOIiZ0M6F5KHjhuim48eVtIbl2qPJ8Ml3j3Vtn4YpnxNio35vQr93Ub32d/95+Jv7vnV1YdnH4aBCYnoUXdmFIey+Ug7+/ELWNbqTHdR7ssu0ZuvIl09nL7OUbpuHpz4/ikavCO85ZT3PTnMGhrkKfZF6Y59ttjysn9ccjHx8U8gWzRCEwtDWViBSbsEAyIScRa+6ZG+pq9Dj8HdYKPwW9CIvRgPQ4//T83R3kcv4/mbnD0zB3eFr3Ts60cPG48I1azjRxOu+J9DgrDv3hQpjbSZTO9BwWowGrbp0Jj1frE+kKGaYz+CkIc66ZkgOdDrjoNBYC/njsNZObGoPHvj8eKbGBC2bMAFPayeXLUBaMzcTHe0vwo2nBtedcdPbpmRrI+TJZohA4Jg/sO7HjmPDhgjEZ+HRfqdKxMJTwwi7MiTIbuhW8VqfT4dvfnA+319fl0BHdzZ7AdM66X56NLccq8YNeFBMp1Dx+9Rm4Zmplj0Sn7wpX9/BzwKpYhgkcyy4ajR/9Y0tQr7nimon4Oi/4c1NnsJ4gTGlO/zV/dPdtjJJjzMgI8+TTfY1BqTH40bQBMLKKzm+izAacPSKdSMACyeC03hPmgWGYpuxLBx66MKhhkkIxN/kDS+zClM9/eTYKq+wYG+A8mAzDtLLq1ll46vMj+HUYxRxkGMY/elOsuUDCC7swJSHKhARe1DFMUJk8MAkv/owDBzMM03thfRDDMEwQSI3t2OOcYZjTZ9lFTcG/20uX1hdgiR3DMEwQmDE4GfecNxxD02NDXRWGiVimD07Bwd9fCKup76pleWHHMAwTBHQ6He4+b1ioq8EwEU9fXtQBrIplGIZhGIaJGHhhxzAMwzAMEyFEnCpWOxUF1GazhbgmDMMwDMMwp0/zmkbzI9J5xC3s6urqAAA5OZw9gWEYhmGYyKGurg4JCR2HQtNp/iz/ehE+nw9FRUWIi4uDLoDJGW02G3JyclBYWIj4+PiAXSec6ettwPfft+8f4Dbg++/b9w9wGwTr/jVNQ11dHfr16we9vmMruoiT2On1emRnBy8PZ3x8fJ8czG3p623A99+37x/gNuD779v3D3AbBOP+O5PUNcPOEwzDMAzDMBECL+wYhmEYhmEiBF7YdROLxYLf/e53sFj6bpqgvt4GfP99+/4BbgO+/759/wC3QTjef8Q5TzAMwzAMw/RVWGLHMAzDMAwTIfDCjmEYhmEYJkLghR3DMAzDMEyEwAs7hmEYhmGYCIEXdh3wzDPPYNCgQbBarZg8eTK++OKLDstv2LABkydPhtVqxeDBg/Hss88GqaaBoSv3v379euh0OvJ38ODBINa459i4cSMuvfRS9OvXDzqdDv/5z386PSbS+r+rbRBpY2D58uWYOnUq4uLikJ6ejssvvxyHDh3q9LhIGQfduf9IGgMrV67E+PHjWwLPzpw5Ex9//HGHx0RK3zfT1TaIpP5XsXz5cuh0OixevLjDcqEeB7ywa4c333wTixcvxrJly7Bjxw7MmTMHCxYsQEFBgbJ8Xl4eLrroIsyZMwc7duzA/fffj7vuugurVq0Kcs17hq7efzOHDh1CcXFxy9+wYcOCVOOepaGhARMmTMBTTz3lV/lI63+g623QTKSMgQ0bNuD222/Hli1bsHbtWng8HsyfPx8NDQ3tHhNJ46A7999MJIyB7OxsPPLII9i2bRu2bduGc889F5dddhn27dunLB9Jfd9MV9ugmUjof5mtW7fiueeew/jx4zssFxbjQGOUTJs2TVu0aJGwb+TIkdp9992nLH/vvfdqI0eOFPbdcsst2owZMwJWx0DS1ftft26dBkCrrq4OQu2CCwBt9erVHZaJtP6X8acNInkMaJqmlZWVaQC0DRs2tFsmkseBP/cf6WMgKSlJe/7555W/RXLft6WjNojU/q+rq9OGDRumrV27Vps7d6529913t1s2HMYBS+wUuFwubN++HfPnzxf2z58/H5s2bVIes3nzZlL+ggsuwLZt2+B2uwNW10DQnftvZuLEicjKysK8efOwbt26QFYzrIik/j9dInUM1NbWAgCSk5PbLRPJ48Cf+28m0saA1+vFG2+8gYaGBsycOVNZJpL7HvCvDZqJtP6//fbbcfHFF+O8887rtGw4jANe2CmoqKiA1+tFRkaGsD8jIwMlJSXKY0pKSpTlPR4PKioqAlbXQNCd+8/KysJzzz2HVatW4d1338WIESMwb948bNy4MRhVDjmR1P/dJZLHgKZpWLJkCWbPno2xY8e2Wy5Sx4G/9x9pY2DPnj2IjY2FxWLBokWLsHr1aowePVpZNlL7vittEGn9DwBvvPEGvv32Wyxfvtyv8uEwDoxBuUovRafTCduappF9nZVX7e8tdOX+R4wYgREjRrRsz5w5E4WFhfjzn/+Ms846K6D1DBcirf+7SiSPgTvuuAO7d+/Gl19+2WnZSBwH/t5/pI2BESNGYOfOnaipqcGqVatw3XXXYcOGDe0ubCKx77vSBpHW/4WFhbj77ruxZs0aWK1Wv48L9ThgiZ2C1NRUGAwGIp0qKysjK/FmMjMzleWNRiNSUlICVtdA0J37VzFjxgwcOXKkp6sXlkRS//ckkTAG7rzzTrz33ntYt24dsrOzOywbieOgK/evojePAbPZjKFDh2LKlClYvnw5JkyYgCeeeEJZNhL7HuhaG6jozf2/fft2lJWVYfLkyTAajTAajdiwYQOefPJJGI1GeL1eckw4jANe2Ckwm82YPHky1q5dK+xfu3YtZs2apTxm5syZpPyaNWswZcoUmEymgNU1EHTn/lXs2LEDWVlZPV29sCSS+r8n6c1jQNM03HHHHXj33Xfx+eefY9CgQZ0eE0njoDv3r6I3jwEZTdPgdDqVv0VS33dER22gojf3/7x587Bnzx7s3Lmz5W/KlCn48Y9/jJ07d8JgMJBjwmIcBM1No5fxxhtvaCaTSXvhhRe0/fv3a4sXL9ZiYmK0/Px8TdM07b777tMWLlzYUv7YsWNadHS0ds8992j79+/XXnjhBc1kMmnvvPNOqG7htOjq/f/1r3/VVq9erR0+fFjbu3evdt9992kAtFWrVoXqFk6Luro6bceOHdqOHTs0ANrjjz+u7dixQzt+/LimaZHf/5rW9TaItDFw6623agkJCdr69eu14uLilj+73d5SJpLHQXfuP5LGwNKlS7WNGzdqeXl52u7du7X7779f0+v12po1azRNi+y+b6arbRBJ/d8esldsOI4DXth1wNNPP60NHDhQM5vN2qRJkwQ3/+uuu06bO3euUH79+vXaxIkTNbPZrOXm5morV64Mco17lq7c/5/+9CdtyJAhmtVq1ZKSkrTZs2drH374YQhq3TM0u+3Lf9ddd52maX2j/7vaBpE2BlT3DkB78cUXW8pE8jjozv1H0hi44YYbWua/tLQ0bd68eS0LGk2L7L5vpqttEEn93x7ywi4cx4FO005Z9TEMwzAMwzC9GraxYxiGYRiGiRB4YccwDMMwDBMh8MKOYRiGYRgmQuCFHcMwDMMwTITACzuGYRiGYZgIgRd2DMMwDMMwEQIv7BiGYRiGYSIEXtgxDMMwDMNECLywYxiGYRiGiRB4YccwDMMwDBMh8MKOYRiGYRgmQuCFHcMwDMMwTITACzuGYRiGYZgIgRd2DMMwDMMwEQIv7BiGYRiGYSIEXtgxDMMwDMNECMZQV6Cn8fl8KCoqQlxcHHQ6XairwzAMwzAMc1pomoa6ujr069cPen3HMrmIW9gVFRUhJycn1NVgGIZhGIbpUQoLC5Gdnd1hmYhb2MXFxQEAZk/+PxiNlpb9xnIbKeuLixK28y9NIGXcaR5hWx/tpuexm4RtY7WiWfUa2WWwixJFTwwto/NKZdLo9Q1R4j7NRyWVvlozrZJTXPWbbIrjxFtDwjFax7gCp3heh5eUMZ6sIPsQJba/fVASKWLw+ITtk3MtpEziIbFO0WW0jY5fZKDXN4nH6Rz0K0huEXP/elJmaGqlsN3oof1fWJ1I9nmKYoRtQz29vqWK7CI09hPvI/t/9P6th0qEbVduGilj/PYw2aePEevoqagkZSpuni5sm+x0jCQctgvb+ZdF02u56PjTO6VtOrSgk27X0c9HykSdENu2/+fVpMzhm+LJPkuqWG9HjZVe3yOe2ywdAwBXD90hbO+v60fK7CzoT/ZpleJ4j82nY0QvTlFIPOoiZaqHi89/5luHSBmdkY7b/BuGCNvuJNq3PqPY3uYq+qzppC7x0ccYadtp50Z9sE2qo4mU0Tx0vHeG64LJZN/Jc2i9446JY9JSQ+/fni6W0SnGaOpeh7BtPlZGyhy7aQDZlzutQNjOr0wmZbzSPCLXGQBS9ohj0vRdCSnjKSsXtqtumE7K1MxwkH2x8eI+r4+OUWej2G8+b+faNM1Lz5OUSuff6irx/i3RdPw77eL415yK94H0jjYq3vUD0uiEnF+cKlWIvms1g3huvYfem6FBbBNzrfi71+nAkb8/1LLG6YiIW9g1q1+NRguMxtZJ2Ci/IQD4DOLsYrDSSdsbJS/sFANCEwetvtHPhZ20APNZO1/Y6aPo9eU6qRZ2cCkWdjpxcBmc9DiddJjBTOtoNEp1NCoWdnrFTC61v9FE298A8Y2gt9LzyHUyGhVtpGg3srDTKRZ20u0aoj2kjClGbCS3h758DE56bz5pvBlUD7ui2WT01s7vX25/n5HWxyh3NgC9XtqnU9ybWb4P1RiR+5FeX6+n40++E+XCTmo2vZUu7AwWsZBR0bD6KMX4i5bqrehHeWEnHwMA1lix3Uw+RVtH03NrdmmOsigWdtIuo1E1jsTrGeV+BaDT03nLYBHr5FXMUTCJ92uwKhZ2cr/RW4XRpJg3pPGmU4w/rRsWNz7FXKNX1Ntg1knbinnc0vnCTl4zq+ZD1TNhjJH6v1ExRuR5xEwbRH7+VP0vP9vycw0Aevo9BkO01CaKhZ1enls8ik6Tdmmq+VCx2NJLbWKIVlxfkxZ2+s4Xdqp3vdwfTeWkdnL4sbBzK+5Netcb6BoaAPwyMYu4hV0zDVlWYaEQZaIN6ZUmSVcSfSI1qbM11SxiFMu4U+jLX14gAIA3Sry+Po32pKdKHEj6GtplXknSpFnoi8Wi+IqOLha33bG0jsYG6VqKSaNugDT5uOjNmpOoNMLYKLZ3Yxq9N0+09BUzqpaUcReIklZnAj2PLoF+xckTh6rdUCuey6fo/0Rzo1hHxerDnUAlxnmS9MenmGugiXWUJR8A4E0VJ7vawXRiMdaJX5XGWvqho1MsbBAtSlV1BlrJulyxvy1VtI2S94htElVCy2iq+5fwxNB9ZumxMWQ1kjJ2n/hGcicrJIaKDxtHg7QgUjx/mvSB4HbSMtlm8Ut/DxTPg5mOG2eMuK8hm9bRWi7uk6VzAGAbKg6clAmD6fU37iT79NJ7VJ4PVag0D9YysY6OLHqvXmvnLyzVh523vusSu9IptI+icunc4qgW5xYTFRjBVCduq8Zx1Ujx2dIPHUjKeBUfBANjRMlyrSOKlCmVVluOFNqODdni9RNqFNqRjBRhu2qaYhGl6P86m1gncxQ9zitLyJyKhU29WMabQs9jNiikurHiXObx0A6QJXQ6xcJSJy22vIrFV2x/+h5JThYHRa2J9pFPkj4ajLSvvZJApl6S1vsaFV8M7cBesQzDMAzDMBECL+wYhmEYhmEihIhVxVqr3IKtkcFB1aOeKFHUqSlscyBJnuMTqGF0bblozKgzK87ToLD7kozFvTUKg6pYycavXmEbIYu1XQobA4W2witp3uIKab3r+3euCpSdJ7xmen1zDVX96RvFSqUcLiZlSi8eJGy7XHTIRjvETjLbaF/L/QgAOoN4M1oDtd+RVejOetpHZQ5Rh32sIoWUcRZTHaKxUbKpUKgCDVKzqdpfk/pbpdJtzBI7O/Yo7Q9vFXUogGqfBLFDpNoKQHKCiSmlHdKQQe8/pkQs54pTqEul5h6eQQ3TD38njiPiFQPAVKsw+jZLqngLrbesndeXUJX2hpoRwnZRA3XUcCme7ahCyeicDlHiPKF61rVYUY2j0+h96McMJ/tkJwdTHW0jcv+Kx4+MW8Uc6TX58TpS2BcZcyW1posOQG+Z6LzlU1zKrFfUSb43hTbMIdmyWytp28oORTEnqdlN1Tg6bo7YRBOK8mpqOG8tF/tE5XBlrZA6xasYxybxZo0xtB09qneU9N50KsaxJtuPNdJJylQrvQ8VdtElJYn0+vKQUMz1xDavnLa17DzoSlK8D9303qqqxPnfp7CxJ85DCpMenbvj94HKua89WGLHMAzDMAwTIfDCjmEYhmEYJkKIWFWsN8oAnalVlOuJVYUpETd1Ck8VnSSeV3nlWBPa8Utug9NGVXFEGqtyepE8ZVTehJZa8Ua8FlpGUyzhvZJUWaVCSTgmVsrgVoSyqBNF9iaXwitYsQ8+6VwKjze9pDJw1dIy0eViHWVvWwCIOkg9lUySo6pKzSKPkZpR9JGRvWKjLFQX5jTQdvNmiOV0RfTeVKrXzog7Qds6dp8Yo8qbpHCB7iZySJ6oCoWar1ps7KTdirARI2gcSdnD2qCIdRcvmRAcGJ1Jylglz0VTOXVvNDZQ9YwrUVJPNdAHySppfu3Z9N5ckn68rIaq1AwVVM/qTBbvTeVdb7R3rorXSaYgrgSFucSJGrLPIoUtVD0jHmnYqnxbE4+KY9KVQO/VZO98sHvr6sg+Y2a6sO0rpap42ZtWrzAXUEU8kKMCJB6g1088IG4r5zrJFEFnp57behcNOlvdKHq8emsUYWqkPlF55coRB0wKlapmlrxSFV6hOoU3qzwk9XZFmBC7rIqldbRIVh/uOEUkC5VTdpzY3mZFSBSd5M3rUYxjr9QkqgAYcn8AgGaX3gmqSC5Su6nMvnTJ4qD01ol97TP4/zJgiR3DMAzDMEyEwAs7hmEYhmGYCCFiVbHwaYKqL+Yo9e7zJEupSI5Tdak7VhThlrsVcm5JzCp7twCAPl2hri2UAjtWKwIr2iTxONUowh4lh+ymZWQPWICKmo0KrxtZZaFSxcrR+JUesApvNl2NpNaIpjcnqyL1jYrAlg5R9O6OocPaPozqXvQ1ksehUXFvkupPVjsCQI1LrLfVqFDFKDJWQBLha4rry05YpnqFnF9SMziS6P3HSukJNEV2Ar2Zqnl8Cg9DGauULc6oSCmmxYgqDNtwqnZ1xSrMDCR1uSr4tax6TFR4rjt0Yh9pVnqv9v5U1aFJah6vl6oQG7Ok+iiyE5TYRdVrUhytY2kirVPMMel6KlWspNZSpr2StHwuhZrLl0DVTLI3p8rjVr6+R56PQE1BZLVb07kV6ikpILZhcC4pYx8iptlSJEeAO0Nsf1cKvZbHQfvWKJ3MG6XIztEojZFYhUmJNEf54hJJGdWz7ZaC7areLXJgeZWaU/ZU1x87Qcp4RovexZqNtodekdVIs4p6TZ/C49ktpd5QBbrXpMwzKrMDVRB5Q5X43HgzFM+xnBwjic7H5jgpNeYJuh5wujtfMllKaBl3glQnE62jT1pb6OPkl2/nc3HLsX6XZBiGYRiGYcIaXtgxDMMwDMNECBGrinUmGYWAl9GyByYAnST6V3lK+aIkkalCPiyLx1UiZE8dVbOYJLWeKg9hwyBRZJx4mKprZdWHW5FPU6X68EhqBmVgU2npr0pwLQcN1eSs5AB0jYrGlTNjOxT5XKVTqdSVDVli2ybtojcbtzuZ7JO9x1Qel2bJ47huoCJArke8jwQr1YU0JtNHraZUVA/5FOoJGZXHs04S65vrFGqmNPFahj3f0XP7oXZVIQd7dSTT/k+QdCGNabSMqUGRhzJbUiErPkWTjojPSEYs9Vw8kiD1v4e2UdI+enJ3tKTmUen55GrX0j7KnirmIa2SdXwAGtMUat4qUWVtVKjrfNJz60pQqLkkj3858DWgVjOabeLNRZdQkxJDgzhu5MDjAKBJc0TxmTSId0wJndtk4wytvJKUiTZI/eamajZTvugVrm+kuVqT46l6vEoyIagbSM1FLLXipBhzsIKU8RWViNdXzJFYMJ7syk6sEbZLjXQCrslPFLbNNoW5ikvsf99g6oGrye2owJfU+Ryht9FxZKoRzx1XoIiuIAWaVwUs1w+mA1eO664vV0QXkN+1Dnpul+TNG12hyMs8go5t+ZF0JypUwXKO3QbF0ktaOGheyVSnsfM8zc2wxI5hGIZhGCZC4IUdwzAMwzBMhBCxqtjYwkYY26jtNCtVc/isoujVXEuKoFGSWMs57wBAL4t56xSBLusV6klJqu6YQFV4V4/aIWy/VzyLVlLCXEP3uWg8VBJsVA7QCACmelH8a62kag6jXdxnqFO4ZXkVOtw6SfesUE+UzxLPfc3kraTMx0fFNkmIVuQqVDgzy8iBVgFAPpMc1BgA8ovEfI5KbzJF/t7oSjk3Ij23HCDV1EDLnDt/p7D9wYnppEz2evFRNxj8aBA/kdtWVqkAAKSArLKKDwCMjapEuLIKR6GKSRbb++b+G0mZe5KuFbbdqbSx7TSuMXkmomjsW2LCoAoq/cV+KQ+rIoirKn+qbK5hplpm4gUbXUKf0ZHXHBO2v5Vy1wJATgWtk5yb1jaItltcgRQVQOEVaqwSB27aDtr/CfvpBOyV5g1dAp3IfFFiJfWK4L8y8eOoSrfWTkMHJBzRSdu0A/RSHnJfvMK7v0pqE4W6OOkQ7f8jSTlkn0x0idj+VnprsJaKbaJz0/m4boDoXvvjM78kZV7bcCbZZ5bUrCqTJn8CrRscYqHGdMV4PElNGIwKT2FynOyprog+LOfcVb0Pfz6YtsmfDl8mbBvsijWC1N2qnM8kuoA0jL2Kd0h7sMSOYRiGYRgmQohYiZ07xgTN1LosNuXRT21dnPiF5kij5zHUiWtfT6JCGiEZRlqqFcbLijrKkg6nQtJz3C4aGbvjFLHWckSjX9X3qs+rSAUjfUVp8lclAKN0/+4YhTTKLe7TjPSLNT6fGp1ai8SvL50cbAiATkrFFa2I5SMb79cNol919YPpF6oco04Vx05ORadKM6M1iPdvLadfmq4ERQotZ8fbAOCWBBRmhcSwziOOY5WDgaVUlJj4RgwgZYwVSWSf57s8ejIJuU5x+YqYjVKMwoozaBHNpHAMkOJWlZ2jSIV1UmzvOD29vuxgYqqgT4mjn0KKJl3fnaQoEyWltCtTfI5Lzgs6Rd6vqHyVQbW4qZKGyE4nZht91mxu8dlWjRHVZ37ZNMkxKoUO0nIpzZW5mp7IUi32vyyJ9htVLih5HotTeLhIzhtyfDgA8Lho++skp7v6gdQzrTZXvN+YUvqsxyaJz6glj4rVPFaFY5Qk6TEr3i0J+WIDGBWp2WTHCENlFSmj99LYkuQ8ihiN7njJ6D9VMZFJh7niqXTUVC/2iSeB9rWljPYbkZhPppJfOc1jZTmV/Lod0lyveB8UuxPJPnmOUsXIk59jSwx9kOv6ic+RwSLFB7Q7gOfpqVWwxI5hGIZhGCZC4IUdwzAMwzBMhBBUVezKlSuxcuVK5OfnAwDGjBmD3/72t1iwYAEAQNM0PPjgg3juuedQXV2N6dOn4+mnn8aYMWO6fC1znRtGYxvRahwVocsGvdZyKsL3GSUZapFCXC9texTpu3wKQ8y441IqqFR67lK7aNBqbFDEUasVT65TxWNTpCszSBqr+ONU9FzfT9yOqlSk/ZEk5noPPU9UgcIzRQ4RWEP1jPqqRGH7UH0GKSOrIkwKVQQUGjSdZIyqyHpGUsqZFTHK5PZ2x9D7t5bR45KOiA1XPZRWMuakuK1q2zq3OOAytilUMYdElapOEbPKY6dxvPwheb+oejEfpOmKvJLqx6Cwe9DbaBt5pMfWUqlQYVZKaf+88aRM9CFRzaGvp6ownZMep4sTVTiaQdG2Hsno2qowKZDS11nLVKnxyC6iMjXX03NbqkXVj85FVVhFNvHe4hUadtOm/WRf3JiJwna9wsPIIMUEiy4hRUiaOVVqOJ2t8/HnOVlE9umra4RtldmLj4zt0aSMV2EK444R7y3tv4dJmbiBoteNyjFB5xL7yHMsn5RJiaZta08XTXHiTijMRaTYljqF2Y38rvMpVLFmW39hu1IRENVaRJ8/Rz/xfjUHLSPPtZ442kY+s+SEoUhxqTJX8Ukebj4fPc5WL5kHORUvBLd4nBx7DwAcCq8H2VzJI9sGAdBJqdhctYrz2DuWs+kU7dEeQZXYZWdn45FHHsG2bduwbds2nHvuubjsssuwb98+AMCjjz6Kxx9/HE899RS2bt2KzMxMnH/++airU7iCMQzDMAzDMAJBXdhdeumluOiiizB8+HAMHz4cf/zjHxEbG4stW7ZA0zSsWLECy5Ytw5VXXomxY8fi5Zdfht1ux2uvvRbMajIMwzAMw/RKQuYV6/V68fbbb6OhoQEzZ85EXl4eSkpKMH/+/JYyFosFc+fOxaZNm3DLLbd06fzGqgYYDa3ib18hFeF7J4uxnGSRLgA4xBBlcMdRVYzsBaZKzaVSszgTRfGs6riiatFTSRtJ3cky4kQ1g9lIvXKqG6iauaFK3KfpqXjYkSWKzK1VVISddEiKkaRI16SrpfXWJPWIlkXVc+YasY2+OU5TAWVLqlfbADqs07LLyT5IMQqNCjWbyyveb3U1VU/4GuXr0TZyx1E1oz1VLKcaf26p23wKz9GCukRh26O4ln6QFA+rqoaUoeoq/yibLKqQsitTSRm9U/QCU8WMdCXSfbJaT2XmIKvL1lZTNZsc/8+bSr3iMobTVFBRJrHeLi8dWw0usePqFSq12BhRh1TnpB7Ieg/tN3necCTRMhZJZeSJoc+6QV8jbHsV7aiPpsd5pSnBpFCXG6VhY3B2nvrIZKdlfEn02dIVis+IPoGqy2W8VTSloCExUdiur6MNYKyhfRtbJM4J1RcMJ2W80nOrSrtorRZ36nOnkjJ1KfT6cj85FeniZM1fwnfU49sXI45JXyMto/OKfbKnqh8poylWDCkDFPkq5eO0zr2SG+olkyIDHSMutyJGoPTcWBVp17x6sR89UfT6muSV7I5SqIJl+yHQeVuzKEyBTIp9Ep4YyTRI8hL2Ka7dHkFf2O3ZswczZ86Ew+FAbGwsVq9ejdGjR2PTpk0AgIwM0YYqIyMDx48fb/d8TqcTTmfrpGmzKeJBMAzDMAzD9AGC7hU7YsQI7Ny5E1u2bMGtt96K6667Dvv3txrt6uSE8ppG9rVl+fLlSEhIaPnLyek8UjfDMAzDMEwkEnSJndlsxtChQwEAU6ZMwdatW/HEE0/gV7/6FQCgpKQEWVlZLeXLysqIFK8tS5cuxZIlS1q2bTZb0+LO5RZSVGmjh5BjfUZxXasK/tooaQfnTDlAynxzUgz26lV4JTnqFXo2WfWiSo1iF48bMbCYFLE5RXl9WhRVe45NosfJqkjfOFrvDQViuxmcsaSMwSaqmXSK9GH1k7PJPnOtqHs2H6NBpJOOiOLn4nSFDkkSUdsGURH++Hiq+9PrxHJ6hT8dCeyqiFBcrYkqJE2hQnCbqei/TlLzxlJnUqLmkb1EAaCiVuwT7xn0+qZ60bvO1JBIykTvpqp4lRciPbd0TLwi0HWO6DmYsaCQlMmMpk5SJ+tFUwSdjt5bQXmysH24Jp2UkdMDORTjaHzKUbKv2iWqJx0KVazZIJo+WBWmELJ5RE0MVasYCxXBV+VURKoYxlKTmBQBiov3iP2fUkXbsepCqmYcd5U43w2Mpt6UDZKnrFNRyf014hxeZqPziGlzItmXU5klbNvHUfVgg5R6Kr5AEcVZSnuoL1V49yo8LhtTxDmxchptW0uCdKBCE+2sEcebXuE5qkpF5YkX59IYhVeqU4or3JhBx3bMcfE8jsto2sGaIeK5604mkzJGRXSH7DhxbvUovFKNkiq0zE773yO9N+WgwgBQbVUENu4nvu+mZBWQMgeqxPknJ6mGlJHfo7FmOiDkdwZA53trErW7spgkz3XVeaR3iyNOnI+9doU9VzuEPI6dpmlwOp0YNGgQMjMzsXbt2pbfXC4XNmzYgFmz2s+ParFYEB8fL/wxDMMwDMP0RYIqsbv//vuxYMEC5OTkoK6uDm+88QbWr1+PTz75BDqdDosXL8bDDz+MYcOGYdiwYXj44YcRHR2Na6+9tvOTMwzDMAzD9HGCurArLS3FwoULUVxcjISEBIwfPx6ffPIJzj//fADAvffei8bGRtx2220tAYrXrFmDuDjqwdYpBr2gilXlIbUUi7rXeAPNldcg5W87Xk+92dxOsRl9LkXwQ5fCw6ZBCmyaQkXPesnDRyXmnpspqpCiFQklVeqRao+oZsq01JAyYzNFt8S9Q4eRMvF5Yhu5kqja2Win6llzgajW8Z5UqJkHimpuc2Y9KVOfJQVxVjh3qkT/sjjcq2hbWT1g0Ck8fqVcwXG76f0nHKPqOUu16JnWmEaPs1aJY6JiLFVFyGe2ltL7kAMtOxOp2jV6u8It2w9iSsS+NRVQ71JfkihJd3jo9feWZ5J96bFif9c0Uq84rUTcp0uhanfZU1E1HgvtiWSfTKyRPltmg+TxaKUD8GCFqB7WK+YDoyLJs7VKPLfXqsiVWyP2m6mohpTxxIvX91gV+YzpI4Iks3gvKq/ARiloa6PsSqtAlZfVNUDh9SfZVxvr6XMkOzh6FffmSJLyWSt0VbLZAwDEFYhta8+i9+aqle5FYYoRe1Iy+6HTGMkLCwBVE6QyXnruhDxxn7GBju2S2eI7NPEovZhVCvRttyrcexWY9VLkBAM9t09SM6rUnBbpuCgTnY+qEuhawOsW+/vylB2kzPlJog7ZqzCpcWpi39Z4qZd4ooE+23EDxflmdv9jpIxFsqkocVDNoqzmlT3w3Q0u0DOrCerC7oUXXujwd51OhwceeAAPPPBAcCrEMAzDMAwTQYTcxo5hGIZhGIbpGUIWoDjQeI4dB3QdqwT0w0SPT3M5FbOabaJ8/sQ+qi7SN4rrY6vCu1Yl+o+SnEBdCVQX0CCpJ75ryCJlimtFsa4q0K7KC0cOEmk1UxF6faMowo6iWjaY8sQbMVYr1J41VPfgLSkVtjWFN23KfrFOBQOpKi62WCxjz+zccxEAquyiqL3BrvDmNIptqdcrAlTWd6568ppV6lGxnqZ6ev+GRrHecSdpmbqT4n0kKfJJRpeJ53HFUXWVp4wGcZaD1qqCGMv11hTBj+UAxSfzckmZqDR67sIq0fRBv42qYqKkLqnIoePPInV/fX/6rBWW0gDZWcmimiXdSsexQ1I9Wg1UhSSr9FWekwrtEOKOiNf3xlFVvN4hXc9Lx6i1TGEeIiEHcQaADYVDhe3EaEVgW2luaXQr1JVucayr8rLGnFRMki7x3vRORfBZi9iXDUn0PKYGsY4JhzsP9AsA0fk1wnZiMg2+3ZgsnkvOXQwAXrPkOVlN78OjCIgbf1TsN0stPc7UIPa3ahzJalZXnMI0SMrfqxXTsRaliPNe3ii66scp1KxVDqrWlJHHkay+PVUrssd0SHwn/DN7Nikjm+LIgecB+ozKYxYA4qLovTl2iXPUxzaa294kTUBGRRBlp1N6JqT79/Umr1iGYRiGYRimZ+CFHcMwDMMwTIQQsapYGZ1BoYpoEFU/ujKqZ4wpEdWcmo6uhWXRu1eRz1Ov8GYyNkreTA5FPtF+4j5zFe2yRoeontIrAh2rpNpyOa8iQKcnXqqjwnMPVkmFqUpp56M79bFSYN1a6s1IvBcV+hJjgyjmTviO9tGxXBrk2mATz6XySnN1rmVFdJnYjiYaZxeWGnpyT7RYz9hjNOei55Do8Rw3ZBApoztTMg9Q9LXBIbZjwlE61hW371f+WINDCr6ZQVWanu/yhO30TTRguN5NVahJ20TdT/1oqtKRx3b5NFpHOdBv0i461sonU0+1EyfE6xU7aYBcOcezKuczuTUrfR6iFEGDvbHis2WwKR5AeW5x0gfZEy0F41bUMU4R2PfEPjFSQFUjjRwgB39WBfqV1byKGK6Iz6eV8krmAUaFV2S0SXyOTHb60MpBmx0pVBXvjlW5yko5RlU5dqUpyqU4j6zmVKHKA02mO0UWJnn8W8vpGInOFzvFm0BNWpzJYkeaFCYmcSfouD35TX+pjqQI5EANCssgWKUpqZIGoEBaIT3Q4BLrtDuZzpEGyVwqqpQUgduP4BvVigDNFmkqcdXQseW0iB2pGg46p5QrVmpqzdH5GGqGJXYMwzAMwzARAi/sGIZhGIZhIoSIVcUaB+bAqG8jNzXQNawvVhRH66OpeLp6hHicO07hXRorea8oxLV6F5VPy6JfS5VChp0hitU91CkX8EoqVR89j8FERejuBrH7tRqFN2m1dG5FEE/NKorsdU6q1HOO7E/2Ge2Sx9vOw6RMfap47oQBNaRM2UQxp6HKu23kEJqbNNYk6geUnlKSO/PJWqqKssWLeraockXO1Wg6/moGixV1JlAVZsyARGG7agDtAF+6qNeqGkMHoMci6pCSvfQ+jNVU9+GtouphGb1b8sqLofoqY7bY/2Uz6Hg0V9D2rx4pqtCd6dSbzFgr5dxV5ZicJva12Ubvf9JkmitWDghe7aRzhOy9V1yRSMuUS97lJQqTjjKqQnMliv1tlT1gAejrRN2/lkqv74kX27tmBG1ro+yVByBliqizyoyhdgZyG8nPDAB8VyZ6k3oLaNJjk10x/0ie8g3D6Bg1V4t9K5tmADT4d31/ev+1Z9C2jT0hjpO6AYp5PEF8J6hMOuQmsShMahRx5Ulu6MZUhZpXev/UDqEmBUa77JVLn7+6HLFNnDm0QiWJtN6xA2uEbZPC41MO4u1WBIO3O8Q+UuWKrUym+WtjCqRzKfT8Xp14bmeyYj0g3ZpsvgEAuuGKAPkN4rk1OQc8aBB7Q5UfkRQkcw2fIvB1e7DEjmEYhmEYJkLghR3DMAzDMEyEELGq2PKz+8FgblUJqdRzsjeXylPHkSGKkA2JijysJvFEmlnhAVujUPMlSOd20krKwW/751Jvxhq7qB6KNtM6ehXqEV+cKDJ2pdA6NhbKOQapmLlmQoqwHVVGRejmaioe95mk602geWjlatdWUc/JzBJRZC2rzwEg1Uqjr56sF9UsDS6q5rRL+1yKHJfGGLG9PVYqZjfaqerDJGneVMFHaweJ168eS88zeoCYY7cshbZRWZKowjLZqUoxqZZ6DhtjJV2QUZHj0yL2o6FQEcXUKJbRjPQZmX7+PrIv2Sz2m0kRIPqk5KmZIDcsgI1fTRK2Vd6NVQ7aJo1usf1Vgb5NkprJrFAh2aPFdjM4VKoghbp+mDiWYqMUrnuDRdWbO4Y+oxbJc9taSU/TkEGvPyhaVD1lKKKvN0r2GTUu2o79k2uE7TITHetlFnpvCf8St+v6K8bfSHGfyuNXNo/RFEESrMcV6jGfpI8bS1XRY9LE8Z5opuOvyil6V7t8tAKldfT+68vFZ9mZqYi40CCey6TIQ+uVxntUKb2+/D7UWxS5YqtpG8VHiXO7W2HSIpsHORThBrxSgOCqCjqPGRRVqpsoevymp9I+MqSL84ZBMY/IuVobFXX0KVx+azxivacMo2Y/srmGXZErWz53tFEcyO4GF+iZ1bDEjmEYhmEYJkLghR3DMAzDMEyEELGqWINTg0FrI1pVROiVRc+mOqpm0cyiyDYzhQY2rTCL6ipZpAsAnmSFF1qhlIdT0RumSnFnVSoN0NpYI6o+HFEK11UFmlRNzUvbyFwjrv0NTirClvcZ7dSdSOeg6mFjrVROrhAA5yRRPRF9mN6bTg5+rHAudnlp49qcon7CoVCzyvn7VG3klQKimhXjyHqERsQ0NogeXsYKqkPRaaKauz6b1vFImehN6y6hYySqQvLuHEWKIO441U+aKmrEHQ1UzWSKlh6kKIWe0y2qFeLT6b2qvCm/KBYDGTcqPDdlZJUOAKQfFHU4qoDhZQpVmJw/MlaRK1Iu41V4/BmipFy9ifQ+KsZTb2arFLS4MZXOIwl54rMVt5+qSz1Roldq7En6jNYpxpbNJdbJrKfqMYf0bJXbaRkZ1RwJhee+XvLmNiqCtDZmiM+koYaeWla9eqi2GLEFdF9drnh93R76/O/OVox3CaMi4oCMoZGeO75GOo8iPrWsela1kW2geG5V7nLZm9d0lDaSQXH96gaxnEehipVxO2h7aJJKE42Kd6ZdMbmXi++ESjP1uNYkVbBekU9dk55br5s2kuai+yyJ4pyQE00jCXil9UeVi9ZRnv/Mkluuy6hwm24HltgxDMMwDMNECBErsbPUeGFsY6BrbFDE1qkU0yX5rAqJTZL4FX/SRWONGRrE9bGlmn5VxFBBHyy14peVg4bogU6qtn48tQwePES0hDYqDENVxroOj3i/sqE4AHhTREPUWhu9//7P7BLrmKK4Eb3iS8uhyD0kIadiij1Bv0YdUkwi1dfooUpa7/o68Ut7QEYVvX6M2G4qB4saKYWMyjDbOTid7LMUU8mKTFSROEZjimmMqqosKe2UIqWcPI6MCgNrU6kiF5pJeiYUsR5JmiMbPY/mEsdtncJRY7s7h+xzSdJHVbo8OfWOSvLhklPj2ek4SouljZIWJTpvRCu+muUvbUcClcbJjhl5tVmkjKZIeyinmVKNLUet2EcmG5UgWavERtJ56P2rnA5K1mcL23VF9LgGKe0hFMK41L3iAIyOU8TxU6WiGiDGP5T7GqDpoeJOUGlk2SSxjXwKwa9XMbS9UqVMikfWVyyezJ+UaorpGGbV49cgxZ+roe8xtxQj01RHy1ild5I7ira/PI8aVSkmFTFaG4rESVrvVIkDpW2F85RcRIuj/RhbSBuucpY4cK8YsYeUafSKfeRRPEh17s4lrzUuWibvq4HC9qoimtNQk1MIWmkf6Y1SPFBJyuizK/LwtQNL7BiGYRiGYSIEXtgxDMMwDMNECEFVxS5fvhzvvvsuDh48iKioKMyaNQt/+tOfMGLEiJYymqbhwQcfxHPPPYfq6mpMnz4dTz/9NMaMGdOla+ndPui1VtGm3kNl+D6zePueGKpmiy4TRcYN2XQtLKcLM9fQ+sQWK0SvkjrEHUW7Q1YP6FdRNWeFW9ynimOlUk/KqFLhWOrEdksvp/J5X6NoUes7cbLzi/lJ/7WiCvW7HyaSMrkfide3VlN9QWkMPU5WGR2vVKnHxEKqGIV6yaHCUqOIWWej7aZJcct0tVQXo6+qEbZjBlCj23ophVniYUUcRYeUnsao0HvVUj2TrEL11tSQMnqz+Nx4XQpHmRTRCcRQSp+15B1UP+aKF9vISTOBwSKZOVSNVzxrkgo3upT2x9GTVF1fYJLS1dXTOsp+WfpGhdG1NG6iiqkqKOYk7beYMvFeLKXUet0bI6kCi6lJgWe4OG5Usc6S99FYj44U8ThNVrsDiC0U622x0fFvqRLHRHQ+bX99gyIVVN5xYTspnupL9dXSzShU2pZBourfrFCpxhQp9LzS7VYPp30rq4dVKlXZ6cCuSA2pUuEapEepUeGEZ5bmaJVjkPVgmbDtK6OxJuMHi6YQxWenkDJRlQpV/BBxn9eicJ6TVa+K6UeTnlFVzEiXIoxj3F5xLvmgZDopE1Um7VCYC8SeFNvRa6WVrJfNDgAklognK59Mzy3PESrfIVn1KjuTaAqnsPYIqsRuw4YNuP3227FlyxasXbsWHo8H8+fPR0ND64Ty6KOP4vHHH8dTTz2FrVu3IjMzE+effz7q6hRPC8MwDMMwDNNCUCV2n3zyibD94osvIj09Hdu3b8dZZ50FTdOwYsUKLFu2DFdeeSUA4OWXX0ZGRgZee+013HLLLcGsLsMwDMMwTK8ipF6xtbVNOpTk5CZ1R15eHkpKSjB//vyWMhaLBXPnzsWmTZu6tLCrGGuGwdJGRKuQTeol0bdR4XQii8zjj9IymtSKekXaE9lzCaBx9AwuKp+tGSPui82j5zGKjpPKOGqmBqpmMNeIajadl5YpmyJ6JbqjFSo0SfWheRUN0E1so0QvUG0gVUXlXyJ6KpnqqLjcl6yIASR5bylCHapl5hKyKt6k8MCW1a5N+yRvVo8ijlqyqAorP4OqYqyja4TtymjqOWuuFK/voaHu4I6mKd1klYnKm1RW/cuefADgkdQaPgsdazVXUVVgTrIYE6pRkYrnxAlRZRSdqEjpNFrU4RqcdBzr/YkTpYi1Rrz5FGpuc6pYJ4eLdoA7ho4R22DZ45WOETldlGHaAFLGI3mX12fTdrRW0X2ONMlzn2qrYWyQ4si56Bg11YsqVGMDVanqFHEs43JFVXhDFq2jpVaaoxTtWDddEYBNwjZUEf9TmhQSc6maW05PVV1DzSV8UpskpFBdeG0VPQ514v2q3i2WcvHcSYfp+HNOFc1MvOZ+9ETSYfW5tD8sVYpJ0iSW0+kVHq9S3DhNNdkq1PwyqlivUrg3eGLoMyp7bhuc9FomKbqFW9EdjRkqHao0/9Uq3j+SeYZmpM+IztPx/fscClOBdgjZwk7TNCxZsgSzZ8/G2LFjAQAlJSUAgIwM0R4iIyMDx48fJ+cAAKfTCaezdYVms3UeQoJhGIZhGCYSCZlX7B133IHdu3fj9ddfJ7/ppJW7pmlkXzPLly9HQkJCy19ODo2FxTAMwzAM0xcIicTuzjvvxHvvvYeNGzciO7s1AGZmZpPes6SkBFlZraLjsrIyIsVrZunSpViyZEnLts1mQ05ODnSaqEXTKTyOLDYpaGmjIvhtqhR8NJUUoYE9FdJaX6LCU1WSxuoVmiBDlqhnNe2h8uGEY+LNGRvoiZxpVPVhPi4GNvamUxVe2reiCsN88AQp4+lB1atM2SSx3Yxm6nHlTBM7QD+Y3v+Ph+0g+/IbRRVeWSNNhWSWdB8+hTvXwUJRX186hQaxTD6g8KaWms1qoGV8ZnFfjMLhuCpHVEXFFCnU/lL3qzTMDuoER9R8KjW37HHtTKZlZLMHWX0NAN5DVM143CfukwMtA0CCOIxRq/BK08d1rsbISKXSfpeUHsnhoqpAe72oUpc9qVWovKtVqbBIfZLoPnn+cSXSMj7penK/Auo+Qbb4/EdH0WfLIaV5cylUsXZJpWisU5mU0OsbHeJxKlVcfT9xZ3SZwiu6UHwA3CmK4Lf9qXrU0SiqZ2vKFG6ZkppNFaBXL+2qbaDu3cYGepzBIan5FD6EsldunSJyA4muoHjXyM9WzDCaGstWRN8Rc8ccEo9TRTaWqHTSubbKqYgQLfGdidoCxG4Vj4s/2rm8yqAwu5KDVltq6DNaO0YRILpRHH+uFMUkJQckVsmp5HSVkmrW16gIW9EOQZXYaZqGO+64A++++y4+//xzDBo0SPh90KBByMzMxNq1a1v2uVwubNiwAbNmzVKe02KxID4+XvhjGIZhGIbpiwRVYnf77bfjtddew3//+1/ExcW12NQlJCQgKioKOp0OixcvxsMPP4xhw4Zh2LBhePjhhxEdHY1rr702mFVlGIZhGIbpdQR1Ybdy5UoAwNlnny3sf/HFF3H99dcDAO699140NjbitttuawlQvGbNGsTFKUTgHZC5uQFGY5tcsUeoChFJoji87GwaNVI/WYx+Oj6jiJQpqBP1I1X11OPNqwgu6LSJKhydQoWTHieqYrOuKyFldh8X8ynGxlFRcHpcMdl3rDpR2E6OtZMyRQWifi75W+o5mfmRpIqyKaKfZtFcqboK0cPMU15ByiQdFLer+tMhG3VMVJc0ZtAyh7OoKr+wLlHYrnPQwMY+KWik203VTIYTol7LWkmKwFSv8JQ1SJ5a9QoVhuSFLOfOBQBLvHicO04RaFvqflXAapU3tRzI2OhUBD+tFFUEXotKzSbe//EBtI9UqkCj5Cir8lyX1SqyBx4AWCrEOnkVXrkNiv6vq5HVQ4pctVKuVlWu3pSxNcL2uIHUvf6knarnDpWIz423lKqrLJLHs5k+xnDFd67S8ynygOqPiXNZgyJXsKVSCtCuGMaNWVKA5lKFul6haUrcIT5MFTOovYCsQvRa6LnlZ9Kr8JxtqKX3FrdTCr6t8CaXx6jqOTLb5H2Kse6kc4RB8oQ0l9HOdaeK9XbF0WdLft5VbeRIEgs1OOg8Yqqm89+uctHD1qRw3ZVN5Osa6WBzNoq6UJXnrK6CHmedLwZbPivrO1JmX634bvcpzi173BsUiYmHx1BzjW2fjha2B79FB7J5h1gnXQwdSFqyqG30JIjvFY/HhUJylJqgLuw0hTu7jE6nwwMPPIAHHngg8BViGIZhGIaJIDhXLMMwDMMwTIQQ0gDFgaRoTgwMllZRZlrSYFLGUiXqDFQxEw0bRPXILitVl8iqILPCKUYOIgwAVkm7LAcsBoAyhxigs6acegWNeFtUadpzqQOJPYbu618uutO54ql4ePTXBcK2lqAIolugUHPLKHKM+oOcm9KQ37nnlLmWfq+cqKf9Nkhyp0xPp/opp+SGt7Mim5SpHS52uKuatnV9f+pNGV0hHmcfQNvWZxLv31pFpd71RaKndJKiO5yJ4ralhpZJ2kdV6M5USc1cSoMIe+LEgetMoi6XsupH5RUaq6h38gHx4aoeRs8t5zPWldEHKa5AvJ7Kc/Dy3D1kX7SUrDPLVEPKWCW3VLuPqrBqJB3enjo6juyK4Ms+KV+kTvacA4hWT5XzOT5P3FblM7bl0jbxZEiBZa30OLdDUkXT24BPOs6VoDBpUDlTmsRy7jhF8F3p0dafoGWiS6Wcz7KbKgB3rEL1KMU1VnmTy/WOKaUvAKd0vwaFSYNHYcLgihOPqxqZSMpkbhLVg/Z02gGyVtGZqDANkjyu3VUK1+ks6k47JUNUECab6BxhkfTs9YqXXaNXrLc89wLAl+YhZJ/7ffGd+FECfUdmbRbnEVcCPbes9vZE0TG6aR4N7HzBxd8K24/etIGU8UmhMsp9dIw4JH25QTqmvs6H6WPIYUpYYscwDMMwDBMh8MKOYRiGYRgmQohYVWzqbjeMbcT4KhG6phdF9hkby0iZA3eJXlhZQ6jnZq1dFFk3NFKRvqxSAQCDpLNVlUGD2EWPXfsyKTL3BlGl6AZVl9T56L5CKTdpg0brXeQW5fN/2HIxraNzmrBpLqfDKnUnvX7CVjHari+VqkvrxFCHcKXL0aABQ6EowncrgtF6FF7JxQ2iytTuoffv8Ir3UlJG64g6sUxyDS0Sn6+ICCpVSe+i9dZLQSkbMqi61pQlqj7qa6jrrEVKcWkbRIqgoR89txwQuXpEIikjeyVmbqaeY07Jc8/QQMeISj1oPiy688ZFURWmHBA8dVQNLbNLEVlcQg5YDdAxkRWVSMrIaqYGj8K7Vtq3tyyLlHHsp+eGVQosHE/1rB4pQLBJkVVRDj7tiqPPg1nhKVsfK3ZudJLCKzNR7EvVs4ZK8f7dcXRCjimiKtTq8YnCtsqbW87VbVLkMy65RHz+tDqqrtTMdPy5sqVc3fvpHCGb2ZSd0flrtf8Gmru2/AxqCuORLE9ii+m9yeYqzgRFXmppV9q3VF1aNk006XDG0TlLq6Rje1+V6HEaq3CLthokVaybtmOjtM/tU5gGKLzCh/74sLD9+uC1pIz+LvFc9T7qXm/SiapXn/I9St8/vzq5QNh+qHwmKSPfy4lGGmnc4RHHjV5atLgbXACeI8epYIkdwzAMwzBMhMALO4ZhGIZhmAghYlWxUYU2GNu4K3kTqAjXUCuKw1WeUkNfF8XKXisVocZXS2Ld/QdJGV8jFb1j1hnCpvFkOSly8Peih89JN73+IUMt2SfjkhPTAjjpEc/lVbgFH3dKKixFGX29eG45YCcAmBqoF5CvuFTckUxVgTkzRY+rq/rRnK9lblGlerwxmZTZXpJD9sWYRVXDnkLq8SSr+azHqCrCkS6p1BVPlSuR7jTbRPWEQZHjVzOKY9J6eSkp8+McsU0OD6SBtuX8jVUumnP4yzzqOV41UKy3pgi+q3OJdbRnKdL6SYdZBtMxe9a8fWRf+q9FvWKacRsp83n1KGF7TwVVc9oHihWIpnG+sSWP6qfl3MS7TtA28pmkQaJwXM0aLJpwNDQogmEr8pdCalv4FM+fpB1SmZ3IXtHeaKpmUuXY1FvFOpmMiiC6ekll5KFzjdckqT5VZRRRAWT1sKWa3pw7Rgq+bKf3FhsnztEzR9A5WvbKBIAMq1iBzOk1pIxP0nM65KSjAPIkNf93Z1PTgCgP9UqXA+n6FH17tFo0vbDQWyNjpGwqff5lr9jUZFqfshqqQi3fIQZ/t9EUs/BIl1PlfJbfGw0DaD8m76ZjtGqM+G4/4aEvoDrp/WdX9JGMF3SMQrFvw74RwnbKJnpuvVfsOFUQa71H3GfLEa/ldSmis7cDS+wYhmEYhmEiBF7YMQzDMAzDRAgRq4o9fFc89FFtvFUb6RpW5xNFuHoHVXOkjRPVo+NTaK7YNElfcLCeqsKK6qmar94hqt48W6m60Crlpvv7yu+RMlnrRJdH7x4qi9dHUVW0ziLlqlXkgfQMFHNVDtOoVxC2iOoxYxpVM6jywBJB+479pIzdLQakjNNTlbbdIKoHogy0jqq8gylRojtboY6qcE0WURUlq10BADGSKtakEOErVCh6KTekzkVVcZpRvDc5dy8AlGQkCtuF9kRSpqBa1LM4HIpguG7Vd56sZlToGeUjjPRmdR7xOLuNjrX/HBlP9lkkVahKzec+Jqqi9AMVnpu54pjQu+n9Z6ZQ9bCsCitNpVOm0SiOZL0i57NF8gr0VSn0jiaqejLaxevr6uj1kw6L19N5VepKsW89inFsVMyRKBfraVN4RRrrO5cPyEHb4/NUYQrovoRD4txaNpWq+WW1XtVw2kbyqI0yKLzUFRilkx9uoHN7pWTWcLKOes6XVYpmJj4bVWlGnaRjW85xq1JhZlZLQaQVuZLtGWIfyapZADBIj43NTgMU6+LpgdKjDYNL8YzGin2rV5h0yHXyRdOb1SsCdJvuEueSG1PuJGVcieLzrjJXMNWJz6j5JJ0PDiyjplBmKVf36JsOkzKyKYwKOSCzzS3el7vBhX1/7/Q0AFhixzAMwzAMEzHwwo5hGIZhGCZCiFhVbOx+EwyWVvGrWRG0U/bCUolnS62iWnGdjXoTeSTRs6bwHDJXKwIUS9LZlH1U9Fw5SdxOuvQkKZP2oxph24dEUkalnvRqklemjjaS2yd6GH1bQgPE6v83S9iOL1CoeRpyyT7rAVGtrdVTb6byXaIq+KN4qq47VCWWUQVIrbdRtcL22gHCtq6GqueMBaI4PEbxxCQdErf1HqpStZZQFbI3WjrZcarml9vEevEMUmbV3jOEbV05VZeZa0UVhp4OUVioExzxZnMlKIIoK9QqMrGiczNsFkU+y1yqrvB9lShsO3Lp2IotlTwHh9L2dzvE/vcqUg7Xf6jwJi4S7zclht5rbJH4bFWOoY2bP0QKPqtQaak8XmUXa3MNLVKXLR7njaLncSVK+XQbqLqslqbhRMZI0RTFqwgaK6vsfIr7kPPJ1pjpGNW7FB7XPlGFaWpQqPkldbkq5/fTE/4tbI8wUVXsXhcNELy1UfSUXnNiJClTfUxSzyXSc0fFimPb7qbt70pSmAtJqkf5eQSAqpnieDeW0vEn54pVeYV7pLjmPsU8qi+l/WZolOoYpQiiLHmOexXmGi7JzCPmOzpHOKi1DAovEt/R6RfQpNMj4kWdtl5lGyNR3EjV/pfGFJJ9Hx8VvfK/2EnHiCaZWeiciraV5lG9ZBrhc7BXLMMwDMMwTJ8jYiV2mV/Xw2hs/ZIxVFFpkC9W/PrwxtKvEZ30aa/bRT+ZosvFLybbQLpeNirC2MlGzg2Z9CuusVi8Xn4drWOBUfqMUXyxGmXrZYDaxevpV4xH+rL0OumQyZBiS8Xup44SsNF8RZ5SmsJNJv6YeDObkoaRMtEFUkojhTRGS1XECJOsfnUKSYMcS8kXRSVWjeNF6UvUTlqB7LVHyD6DRzzO61X0kUTmFirpqS0TJSaJRxQSg8Oi5KVhXAYtc4KK7NzJ4r3U91OkVHKI/W9w0XEkjwlnIr2+Q09ToSVKKZR0PvqMJB0R+/ZkNv3SztwqbhuctB9LZtD+rx0hG32TIqiYLMX60ysk1qni17annI6RhEN03kjIF+8t+rhCqp4knsuZQvuovp/YbrFFCsnnkUqyT/dX8XqanU5kCfXiuNFHU8mXz04dWmSMKdQxCGZRanPiRzSOYGOG2EeWKtqPfzl5obA9MpaKrHbWUG2E7AhhO0qN55P3itdzpFDtgCtR3BetSN+m0irJ/e9IpOPfXiX2d2yxIn3jftERwLv7AL2YROUts8g+OR4iADQMlx4KI72+/G7RKdRjctozJ/UlhFeRCi55u/j85Z1IJ2UKzIqxJV9fqrZP8a77LomeJ2qL+I7Ofo3O9d5BYmxN3U7qYOFzdiyR82hu5HVYohWW2DEMwzAMw0QIvLBjGIZhGIaJEHSapggeFEA2btyIxx57DNu3b0dxcTFWr16Nyy+/vOV3TdPw4IMP4rnnnkN1dTWmT5+Op59+GmPGjPHr/DabDQkJCZjw04dhMLeKv02N9Dad8ZLRJ5Wgo36QFCNITh8EwFoiisdVsc70fhhLagpVqLz0Hvoaldc70kXVR/T+YnoeVfwxlyhC9xQrLGoljFnUwNyf47pL7cKZwnbZPEX8KenW9CpVgMouXVLF+hTxlwxSujS9k57IEy32W/Je2tfpXynUXKXiPlWsP5mqG6l6pGq8pC5WxH8yRIsqHU0RD0qzK+J/SSmtVIbp8jiWjakBwGeWjKcVKm3EKlTRcjHVMyLV26CIqxZbINYpqoqep2aYot5Sk6jiiMkqJEX2PphGiaqwWdn5pEylk5p5VDskUxCFCqvRLarizEZqdiAbi3vkSgNwumn/x1pEo//CCqqK1ArE+ceXSZ1gDJIpiCrWn7uIqnANUmxRVbo+eY402Gk/GiVNcMY2qlO3p9OTR5eK5UqnUjW3O168F1W2Kp3cJQqRiir+o4ypVvEekabExKP02bJWSc+/nraRweHttIw9k95c1RixTl5z95YU5LlRtJGqb4e8Js6bvkNUYWnoJ5l+NFK1p7e689Sc9ksnkX1FZ4kVTRxWRco4XOLYcrnoWJNjrcpxRX2NDhT8/CHU1tYiPl6RtrENQZfYNTQ0YMKECXjqqaeUvz/66KN4/PHH8dRTT2Hr1q3IzMzE+eefj7o6hVECwzAMwzAM00LQnScWLFiABQsWKH/TNA0rVqzAsmXLcOWVVwIAXn75ZWRkZOC1117DLbfcEsyqMgzDMAzD9CrCyis2Ly8PJSUlmD9/fss+i8WCuXPnYtOmTV1a2DWmAYY2DqQOhcejLDJ3pHUeoyttC71W0hfHxR1RCp2uW+GV6RbF/FpSHCliGympPv5SQ8qcES8GUmv0UnWBXg5kBKDBI3rYquLf1ThFVdCBHbmkTP/1A4VtnY+K4vUKT0lTrahD0H9LPbUSvhO98GpGUHUNVYXRa6nUgwZJGq/KMhR7Umw3Vxw9jyNJir9UTPvak0TrbXKK5fS1VM2uTxE9nqvHKVSYyWLFVd69sle0yUh1ivZqOm6iiyRVrELGLw8tWe0FAD6jWKfsy2g8qFQL9VwndVSM7bwaqY2qqUrT2SB5JVbQMZK6i7atpUpsW2MdVTPqG8Xn2NmfqknyY8Rne6OXBo2TY70BgCb1pUoVK5sQKLO+Sc+Epog9qHNQHXJ5nHhvhnLa/rEnpHRxbjr/+SySKlihro4t7DweolsRx03GrFLuSM2mUrs2ZClUjxni/fom0pPHWztPTyaruQ16OtZUaQ9l6moVLv8N4rkT8lR6XnHT4KTPvyY9o7W5NAJDfAG915w14rlUz4jOI5k06VUpPsUy3jg6jjxy7E8AB+4RPZdnjFKpKcX3SJWTtqNZLy4Ioo1UXZ9hoOk6Z0fVCNvJRjqPlbnFOpU7aQQAOX1hlVN8Z7gbXCggR6kJq4VdSUmTrVZGhqgPz8jIwPHjx1WHwOl0wulsHUg2m8JnnGEYhmEYpg8Qll6xOumTU9M0sq+Z5cuXIyEhoeUvJ0cR/IZhGIZhGKYPEFYSu8zMJo/LkpISZGW1BvQrKysjUrxmli5diiVLlrRs22w25OTkIK5Qg6GNd44cRBUAjA2iCNmlCP4YXSyKlYtmU/Fw+UQxNZXe07naD6CqYL1CW+vIFUXfd6RTdeVAs+gV5FC4ZZkV7nwNPipqlylwiQEZq0ZRlWL1CbFvVCpN1T5rldjecY1DSZnaIaLIXKXmk7Vzzgyq5siZTD2F3VKw24xoGqDX7hHb0uGhj8xgq1iprTupmm3EP6h6QlbP67PoGPccF1WWAz+gQVRLp4pjUqUuhU7sa4MifVhqDX1GzDbJU85Ax7bXInlzKdRscp1KX88lZRrzFWnvrOKBehft29RK8eFKUwT69CSK2yfOpc/xORd9S4+TXPWMiudILtPoLSdlkrziONpfqggQvVWhwpTaUhXEVvYmVAWItlZLKY2U5hIK9ZykMvNaVeYq4rkSv6N1lFXx8jYAGB30+nK58vF0cMnp4byKuVZWzzamqMYxPU72uNftouYyxFFT5RQqjX+vwqJCU7yNZW/aGNXcKk0tHgutgCdGGseqeNHSYar2OHkzrcDMAfnCtt1D1fUOr3hzstoRAPSSmUGMgY6HI5WpZF+qZFYyN/kQKVMrDZIyF1XXGqTrJylUqrGKF/kLR8RIBbq11HNcfv/FH6dzXV2OOEcYnFIkAVcvTSk2aNAgZGZmYu3atS37XC4XNmzYgFmzaJgHoMkGLz4+XvhjGIZhGIbpiwRdYldfX4+jR4+2bOfl5WHnzp1ITk7GgAEDsHjxYjz88MMYNmwYhg0bhocffhjR0dG49tprg11VhmEYhmGYXkXQF3bbtm3DOeec07LdrEa97rrr8NJLL+Hee+9FY2MjbrvttpYAxWvWrEFcHBWBd0TVAjv00a3ybo8i75smBV+VvXIAQB8jikPnDttNymRba4TtRh8VRde4qRdOo6SecXipCvVguZj37h/vXEjKxB+TRLZmKuZOyKcidLckno89VE3KaFYpsOKkRFImtVA8tyuBtnX8AXpucq1j1FPS9r0zhG1HriJZp+ThF5VG9QxTU6g/UZXkYhdnpKJu2XO42kVV0Qlm0eNKpYrHYUWWv3RJraDwnJYDQtf2o2PEmSzlYVRc3xstjm1HGq2Oq4IK8C214hjxKWT8crNVT6NjTWcSr68KUFs1k6rZTCelANEKd0rZU07puStpdbxxVM0zKoaq66s94hixKJLFuqWouTZZNwigUjFuZFQ5juXgsyo1qztW7G9XPO1/V5zYbrL6DgCsVXT+cyaKjVlPLQHglTTIKpMSk6RCtihiwWaspjpc++RcYVvp8SkRVUb7qGyKOCfLzwwAGOsVz410b4rgAqQtVWV07o63AcBDHSVpfeirhZj0+BTmEnqv2G5VI+lzJKv0VU66BgO9uSyr2Jk2RaR/j2RT4FRGmhaxKAbSXjcNkJ/wgrg2WFU7n5QxNEgNrhhGnhixcVWewyfn0uc4ukQcS3LueICaFFjK6TvK0CheXzOJlfR4Ove+biboC7uzzz4bHSW70Ol0eOCBB/DAAw8Er1IMwzAMwzARQFjZ2DEMwzAMwzDdJ6y8YnsSnUET1T0qIaEsazZTMXNcvKhm2/DlOFLGXCMHqKWXMipy1bpjxONMdlompVYKLFtH1YXmEtHlyxtPReGGMupOZ/VJomanQoUWJeqHkvdTVaCxQPQCVGiU4DlZRI/rlyXuUAStdPST7j9WoVKWArs6Gqi+4q0dU2ilJFV87BH6OGRtEj2jXIn03PXfijEWRxhozEVPYyPZp5cl1x4qwtekPlHlKvWmSmoGO1Wz6KRAs3oTHesuTeGVKakDZC9BAPBIqqisflTtbpI83OJMVBdY56ZueMddoimCnLsXALQ08VyqIL7yHq2R9vWKzxQZcfxIe2muEdsobQftpPKJYr3Tv6VlKsbSc8tqPmeSOuxTW1RaLrdkyWJSqELlYOwA9Z41KnJ1kkDfCuc9o9zdCnUl4qgu0pEs3kzpHMUDYBH36WrpHKVZpGdLkfNb9Tr0SeVUan6TlJs4qlRxZsnDURXoXBWkgFxP0f2Sw6lShSq/a1T5jGVU6nrvt9Q5ce3HZwrbqveYXCeluYR0mOxtDQDJZA9gtkmB7hUqVJ9VvGHNSCsge/z7zKogyvT6ssbYqYiuYa0UC3mjFZErTojzpnNQCinjLyyxYxiGYRiGiRB4YccwDMMwDBMhRKwqFt/FQrO2qpbMCgm+SQpaqXB4gytaFP7220dPFFUi6h7kvHgAYCgoIfuKfzBM2I49QWXfcq7CmsFUXeaVAtSqvNIMTupVLIuVFRosovozNdB7S6qSPIVq/Evr5qsURc8+RWDZUX8uE7bzrs0iZYjgW6GKUKkwicehQvVgGyLeW0MmPbm1SPRu9cZTnYp3TH96/UpJPbuPegXKbZK4l+rQyqaL6hHNqFCFSDlHfW6FKiKeDhyXHCDYodKhSB53X9Pgu3JA1CpFf6hUeMlSlVQmDSZJ9a6Iz42oCvFEKnWltYxGbdbXShU30Pv3WcXr62tpYNPSaWL/l/6EquZ9Xjq2nB7xej5VktU68WaM9bSOJunWVApdZwLda7GJ7R17UjVJSNt+qK9Vc0392HSyT++RCirUxZpO8pxW5ErW28QyniQ61nWKc8eUiPuMtNvIvEHqDBpsNkoRMN9aRc8te1Oa6+n8KwfaN9VRcxU5n7HOqYouILZJ8YX9SJGEY/TBjf9K9Pj3VdeQMj6X/x6dHaGPpl6p9vNF86jaMzoP9K16H8hiLpVKW6XCHn+nGCnjBynfkDIuKfp0vJ5Odi7p5D7pwWqo8+KLCfT6KlhixzAMwzAMEyHwwo5hGIZhGCZCiFxVrAZBJaASvcr7VCoc7wRRh+GdQ9Us+bWiN5dOT2W47sYcss9oEc9VO53KeVNTKoXtu4Z8QSvpB7IoGADcsuhX4apU4RbvbVPFIFLm0HRRZK93UJWK0U7zwCYdEtUKURVUPeCQgiin7qUd2ZgilqmaS8XcM4bQAMFyTkM5LywAuL3iuVUev76LxDrVNtJSFUeph9OI56T7jaHHGYYNFLbrBysCdUtanfhDCq9YVQJXCZUpAlHXq1SokveasowUWFeprmpUmDC4pRyniuNkVWBDP6oKl4O2Hr+YjvWLZhwh+4obE4RtjyJCc7VT7De9jj7//XFS2I4xUdXU0Q302ZKmCGI+AFBNqKr95Uc76bAi0HKMIkC0pObzmei9mWulnMcKr0QZnSKWqUfhKRiTJ6rC476j85ihQjT98CVT71pnqthHFeOpd3v8cTr+THZxn8lG201lekMLie2mb1SoS2W1vwKtvJLuNEltkqGIPi5TR99j8nlqR9L7sl5Kr9//PvFc1a4EUsYlzaMexbtGLqPKJ2vU0zoNjdknbJ+bSPOpOzUpGYDqZe8HVYoo0iccYm7YMg/1HJavX6OjKmWfJGeT69jo9gA47Fc9WWLHMAzDMAwTIfDCjmEYhmEYJkKIWFWsqVb0slN5Ycn5CmuH0DI/GblN2D4r9iApc9ApqiKdCjFvlZRzEqCiZllcCwCfnxQ9Z//w9cWkjByQU+XdpVrC6x1yQEbaSGabWMaRoVCzSN6UvkSFV2aFIsmhVE17Or3/hiyx4rInMwA0SPkr4xOoSuPMxKNkX7ErUdiu9lDxuJwrVqUe0EuDq1Gh0lV5Kuok70nvMKquL7hAFP0nziwjZS5JE/PgHhxHVeH9okV11dHaVFKmxk5Vwdo3VK0iEyPFnnYrgq/aJW/iGRfuJWUGRVeQfbKawylHYwVgc4tecKkG6vH49dFccYdGVTpTYvPJvsNGMTelqv+LHWIbyd5sAFAjqWsLaxNJGa+VPjcu6VnyxdDnzxwnqvW8HjrW4qVA6wWD6fWThtDA0hcOED3+ipx0PJgkfX2Vmz5HRQ2iesqtMA0oKqN18tVJai2rIipBvGie4FWoy/U60XXVp1FVaNFYhXquQRxv48bS6PP9o2uE7VIHVcUlmsU5qchO29FqVOS4tYvPf7KVvkdK6mXzDDqOMmPFibPORc0VkqziGIlXeLemRFEV7hhpAig10/v3SGY/dkVedDl3uso0aE8FjYpQ8MUAYXt9Eo30bayT88KTIsRcQRVdwh1P27b/evFku6PHkzKJu0WXZ/ugRFLGkSS2UcoXYrt6fE4Am2ilFLDEjmEYhmEYJkLQaZrCirUXY7PZkJCQgPMG3AajvvWrRFPEVrPPGSFsxxwoJ2WKFshpr+g1LTVS2h1FrC1VehRHkngyc71CYiYZJpvqFMa73s6Nd90J9AvNVC1+xWpy+ijQNCsqfBbxS0PnpvXRFPG/SFsqbkO+t7pcRRw/s1hHDy2CxDz6+eWQUr/I6ZMAIP478Qv15DnUeSGmSIpRpQjSpmoT2RBbM9K2Lp8kSj9sU6hjyNBsUYpXVKuQqhjFOtXVUemcp55+RcfvFyUWJoXNdepu0cHIkUY7oHKMeJ7M+YWkTHoUjSNXLEl6VJIGl1s8t0qq1lAkSj5St9PxKI8jADBK8ca8CueBxGPic1QyldYxVhojHqsiHpviEfFKTemgglZ4omTHFEWZBLH/o/MVyhrF9e0jxHszlFPJuzdaHNt6l8LBolI8ucKXCwZFjDj7SFGyNmEwHTcj4sQcXrJTGACYlIHLRPIaaONu3ypqTOKHUqlmrEVso3qnYq7Vi9dvcCraUSFp9LjFezEY6TzicYpljHn02ZalwSabwsEvQXKC8tAyw56jqSE9x/LF6w9TqL684v3LxwCAMV10+vCU0fexbgpN6alt2yNs6y2KOHaKGKndoWTJLLJPdrppyOhcXqaKh2etFts/ea0Y19Tjc+GzsudRW1uL+HgqFW0LS+wYhmEYhmEiBF7YMQzDMAzDRAgR6zxRNyELRlOrSFbvpkaXZZPE20+OUqRCkiS4Kbup9b7+sKQe8CrE/tn0+pVXiaL/6F30OKNd1KvYs6iYObpYrKShnubG0ltVug9R1O5KpOoBnVcUD/ujmtWiFHJmVXqWzk8FTS/WW6VmktOcmeppO+pdiphM0r1FHafpuryJUowyRay38vPF9h7+Fyr21ytS+GglkqpBEf8wq0Z0hEjdSQ3TjUViv6UOpWU0SYWYUUDVnt44qor2WsV2U6kL3fFSSi2F2UHKPrHjPLszSZkTCjWnUYptl1ZMn7/6oaJ63FJFDeN9Uk5Bg5OWMRVQ5w13jhR/UBGjznRUNKh3nzuYlLENEo+zKMKRqRy8kg6J40a/V2GuUS2NN0VcNV+UqGY31NbQ61fRfZpd1I/qohUq/FLRFMAQS2N9wSDOCd5a+qwZ06gq1GcTx6l90ghS5ps40enI4FCYQkjN5kihc521ko6JEUfF+JdeRRw5zSP2kSrWpUyiYl/JYqrmM5P4g3QCjNkvtr/n2A4/akCR+02XSmNvwq2YACU8R2hqRH9QqV5lZLWrip5Su6pwK8KIVg8TO8mgiDXpT9g8T6M4R9in5Iq/ux3Ap52fB2CJHcMwDMMwTMTACzuGYRiGYZgIIWxVsc888wwee+wxFBcXY8yYMVixYgXmzJnT7fN5rHQNGy06UyFhewkp402VZK8KVYwuQSzjGE5VupbtVDwdVyCKui0KVUDFeFGtFlVJ1SyNGaJ6NkpRR3MZVb15DooplKKzqHqMqGKs1OMLUhwpNFJRuK+yiuzTR4v35rPT+HO+RvH6vrMnkTLmAyfEMgoPaJV43iLdr5ZCvUn1DkkVplAF6yrENqkfQuXurng6/kz1Yv9bK6maw1IoeuGZdtB4fJpePHd0He1rREkKIg+9Ed0x2m66Okn1qVN8CypiwgUKlW9j7HEpjplcZwB6ud6KOiu6Frrj1AtTRktMFLbNVMuIqArJK7HBv2AEjmRxio4/Rp8RfYPk3W5U9NGW/WKZaKqu9yqeP4Kibcl56hXjzw885VQVTti8i+zqTnKoGD89J1VjoidQeW5GVdExYU+TYp0mUjMXc38x1qOuux6nFnEe8+QfJ2UMCZ3HtYxkokrpPpfkoBpX2HlquqhC+hw19hdV4dFHxXemx0tNrNojLCV2b775JhYvXoxly5Zhx44dmDNnDhYsWICCgoLOD2YYhmEYhumjhOXC7vHHH8eNN96Im266CaNGjcKKFSuQk5ODlStXhrpqDMMwDMMwYUvYqWJdLhe2b9+O++67T9g/f/58bNrkXzoNAIjbVwGjoVW07MhNJmUS9tQI274EhTfhN6IXjizSBgDPEDGlmKbwbtQG9Sf7TPWieNanCFAre9MkfHOSXr8fvTdCJQ2sSc5TTFXRBIWayWiUAsRWULWrSs0hq1n9Qb/+W7Kvu+oScr9+3L/nPOq5liJmXYKlltbI2KgIPhotqlVUHse+k6LHpV9tpugjGUNyEtmnUmESgqh29ZdQ19tbUyNsx5RQlVpjsti3qW9R7z5vg0IV6ke9uzP+VWYPfYlAek529/qqoNX9Nohj2x+vUBX+eJx6KhWu2hIqb+a+RMZX9N1WPUGcS2ML6LNlOCq+t32KOSvKmytsy97FHq1zj+Rmwm5hV1FRAa/Xi4wM0U4tIyMDJSX0xet0OuF0tuqebTZqJ8QwDMMwDNMXCLuFXTM6yQFA0zSyDwCWL1+OBx98kOxvSpjbZtuj+EKSjBF9Xvql7ZNXyT7q4CCf26OII2XwKq4vpYvxeOi5vU4pXZaPGlCq7o2gqncXvgA6PnfnCbZJO/ZSvIovba9LShel6keF04Hc/3qFQ4NeasueakdNMR68EdJHocbrUowR+TlWPCPK9g9DCSkTGFTjxiO9NzR+RkOKpnBgkPtN9T6W51vVPK6Tzi3PBx40bfuTBTbscsW6XC5ER0fj7bffxhVXXNGy/+6778bOnTuxYcMGobwssTt58iRGjx4dtPoyDMMwDMMEg8LCQmRnZ3dYJuwkdmazGZMnT8batWuFhd3atWtx2WWXkfIWiwWWNm7asbGxKCwsRFxcHOrq6pCTk4PCwsJOk+b2NWw2G7dNB3D7tA+3Tftw23QMt0/7cNu0D7dNk6Surq4O/fr167Rs2C3sAGDJkiVYuHAhpkyZgpkzZ+K5555DQUEBFi1a1Omxer2+ZTXbrLqNj4/vs4OhM7htOobbp324bdqH26ZjuH3ah9umffp62yT4GUcwLBd211xzDSorK/HQQw+huLgYY8eOxUcffYSBAweGumoMwzAMwzBhS1gu7ADgtttuw2233RbqajAMwzAMw/QawjJAcU9hsVjwu9/9TrDBY5rgtukYbp/24bZpH26bjuH2aR9um/bhtukaYecVyzAMwzAMw3SPiJbYMQzDMAzD9CV4YccwDMMwDBMh8MKOYRiGYRgmQuCFHcMwDMMwTITQ6xd2zzzzDAYNGgSr1YrJkyfjiy++6LD8hg0bMHnyZFitVgwePBjPPvtskGoafLrSNuvXr4dOpyN/Bw8eDGKNg8PGjRtx6aWXol+/ftDpdPjPf/7T6TF9Zdx0tW360rhZvnw5pk6diri4OKSnp+Pyyy/HoUOHOj2ur4yd7rRPXxk/K1euxPjx41sC7M6cORMff/xxh8f0lXHT1bbpK2PmdOjVC7s333wTixcvxrJly7Bjxw7MmTMHCxYsQEFBgbJ8Xl4eLrroIsyZMwc7duzA/fffj7vuugurVq0Kcs0DT1fbpplDhw6huLi45W/YsGFBqnHwaGhowIQJE/DUU0/5Vb4vjZuutk0zfWHcbNiwAbfffju2bNmCtWvXwuPxYP78+WhoaGj3mL40drrTPs1E+vjJzs7GI488gm3btmHbtm0499xzcdlll2Hfvn3K8n1p3HS1bZqJ9DFzWmi9mGnTpmmLFi0S9o0cOVK77777lOXvvfdebeTIkcK+W265RZsxY0bA6hgquto269at0wBo1dXVQahd+ABAW716dYdl+tK4aYs/bdNXx42maVpZWZkGQNuwYUO7Zfrq2NE0/9qnL4+fpKQk7fnnn1f+1pfHjaZ13DZ9ecz4S6+V2LlcLmzfvh3z588X9s+fPx+bNm1SHrN582ZS/oILLsC2bdvgdrsDVtdg0522aWbixInIysrCvHnzsG7dukBWs9fQV8bN6dAXx01tbS0AIDk5ud0yfXns+NM+zfSl8eP1evHGG2+goaEBM2fOVJbpq+PGn7Zppi+Nma7Saxd2FRUV8Hq9yMjIEPZnZGSgpKREeUxJSYmyvMfjQUVFRcDqGmy60zZZWVl47rnnsGrVKrz77rsYMWIE5s2bh40bNwajymFNXxk33aGvjhtN07BkyRLMnj0bY8eObbdcXx07/rZPXxo/e/bsQWxsLCwWCxYtWoTVq1dj9OjRyrJ9bdx0pW360pjpLmGbK9ZfdDqdsK1pGtnXWXnV/kigK20zYsQIjBgxomV75syZKCwsxJ///GecddZZAa1nb6AvjZuu0FfHzR133IHdu3fjyy+/7LRsXxw7/rZPXxo/I0aMwM6dO1FTU4NVq1bhuuuuw4YNG9pdwPSlcdOVtulLY6a79FqJXWpqKgwGA5FAlZWVkS+dZjIzM5XljUYjUlJSAlbXYNOdtlExY8YMHDlypKer1+voK+Omp4j0cXPnnXfivffew7p165Cdnd1h2b44drrSPioidfyYzWYMHToUU6ZMwfLlyzFhwgQ88cQTyrJ9bdx0pW1UROqY6S69dmFnNpsxefJkrF27Vti/du1azJo1S3nMzJkzSfk1a9ZgypQpMJlMAatrsOlO26jYsWMHsrKyerp6vY6+Mm56ikgdN5qm4Y477sC7776Lzz//HIMGDer0mL40drrTPioidfzIaJoGp9Op/K0vjRsVHbWNir4yZvwmND4bPcMbb7yhmUwm7YUXXtD279+vLV68WIuJidHy8/M1TdO0++67T1u4cGFL+WPHjmnR0dHaPffco+3fv1974YUXNJPJpL3zzjuhuoWA0dW2+etf/6qtXr1aO3z4sLZ3717tvvvu0wBoq1atCtUtBIy6ujptx44d2o4dOzQA2uOPP67t2LFDO378uKZpfXvcdLVt+tK4ufXWW7WEhARt/fr1WnFxccuf3W5vKdOXx0532qevjJ+lS5dqGzdu1PLy8rTdu3dr999/v6bX67U1a9Zomta3x01X26avjJnToVcv7DRN055++mlt4MCBmtls1iZNmiS41l933XXa3LlzhfLr16/XJk6cqJnNZi03N1dbuXJlkGscPLrSNn/605+0IUOGaFarVUtKStJmz56tffjhhyGodeBpdpeX/6677jpN0/r2uOlq2/SlcaNqFwDaiy++2FKmL4+d7rRPXxk/N9xwQ8tcnJaWps2bN69l4aJpfXvcdLVt+sqYOR10mnbKIpNhGIZhGIbp1fRaGzuGYRiGYRhGhBd2DMMwDMMwEQIv7BiGYRiGYSIEXtgxDMMwDMNECLywYxiGYRiGiRB4YccwDMMwDBMh8MKOYRiGYRgmQuCFHcMwDMMwTITACzuGYRiGYZgIgRd2DMMwDMMwEQIv7BiGYRiGYSIEXtgxDMMwDMNECLywYxiGYRiGiRB4YccwDMMwDBMh8MKOYRiGYRgmQuCFHcMwDMMwTIRgDHUFehqfz4eioiLExcVBp9OFujoMwzAMwzCnhaZpqKurQ79+/aDXdyyTi7iFXVFREXJyckJdDYZhGIZhmB6lsLAQ2dnZHZYJ6MJu48aNeOyxx7B9+3YUFxdj9erVuPzyyzs8ZsOGDViyZAn27duHfv364d5778WiRYv8vmZcXByAppuPj48/neozDMMwDMOEHJvNhpycnJY1TkcEdGHX0NCACRMm4Gc/+xmuuuqqTsvn5eXhoosuws0334xXXnkFX331FW677TakpaX5dTyAFvVrfHw8L+wYhmEYhokY/DExC+jCbsGCBViwYIHf5Z999lkMGDAAK1asAACMGjUK27Ztw5///Ge/F3YMwzAMwzB9lbCysdu8eTPmz58v7LvgggvwwgsvwO12w2QyhahmlLXH16LWWdtpOR1aV9c6nQ466IT/G3QGGPVGGPVGmPQmGHVGGPQGGHQGGPQG6HV6GHRN//dpPnh8Hrh9bnh8Hnh8Hvg0X9MffIAG+NC0rUFruqiGln9rmtb67+bfO6h383Wb/8wGM0Ylj0JKVEo3W41hGIaR8fq8qHJUobyxHA6PA26fu+nP2/R/n+ZrKqhrfafooGt5dzS/P0x6U9O8rW99b6j+3/zu0el0Le8QTdOa3h8+H7yat/XP54VPa9pH/u9r3fZoHmG/Bq2l3sI7qR1a7kvXen96nb71/zpdy7tIfjc1bzeX1ev05L3X9v3XvF+4vo5er722a35/66Fv6ZOUqBREGaNOfzD0AGG1sCspKUFGRoawLyMjAx6PBxUVFcjKyiLHOJ1OOJ3Olm2bzRbwegLAyl0rcaT6SFCuFW7kxudicsbklr9+sf1CXSWGCRvcPjfK7GWIMkYh2hgNi8HSYx76drcdhXWFOFF/Aifqmv6KGorQ4G5Ao6cRDo8DDo8DjZ5GeDUvTHoTzAaz8P84cxwSLAmIN8c3/VniW/4dZ45r+Ys1xbbUu+3L0eF1oNpRjRpnTcv/7R47BicMxtiUsciOy+7zEQl8mg82pw2VjkpUOapQ66xt+nPVwua0odZVi6rGpoVcqb0UlY2V8GreUFebOQ2envc0zso+K9TVABBmCzuA6o+bV9XtTRTLly/Hgw8+GPB6yUzLnIbsWOqZ0u5XySnJWfNXjNa0Ax7NQ6RwXl/r11LbLyCD3iB8oRl1xtYvlVNfEXpdkxs0kQ42Sw6lL772aJb8Nf95NS/qXfXIq81Dvi0f+bZ8rDqyCgAwJWMKnp73NKJN0afRogwTXGqdtdheuh317nrUu+rR4G5AvbsedrcdI5JH4MLcCxFrjvX7fCfqTuCdw+9g9dHVqHJUtezX6/SINkYj2hgN6EAkICa9CWnRaUiLTkNGdAbSo9ORYk2BzWVDaUMpSuwlKG0oRam9FDXOmgC0RM+SYEnA2JSxGJM6BhcPuhiDEweHukrdptZZi5KGEiRbk5FsTYZBbxB+r3fV40DVAeyt2It9lfuQV5uHKkcVqh3VXV6o6XV6pFhTEG2KbpG+mfSmlvm+eWENoOXfze+P5j+3z93y/lBJ2drO583/bpZC6aFveZcYdcYWqV/bf7cnLWvWMLUtAx2gx6l3k/wekiCapFPvy2ZJogYNXs0LTdOEe2q73SJx1Hzw+rzkHQhA/Pep34DWD5fmd7N8neZzNl+z5b82HzwGnYHeWIjQabI8MlAX0uk69Yo966yzMHHiRDzxxBMt+1avXo2rr74adrtdqYpVSexycnJQW1vLzhMBoNZZi51lO7G9dDu2l27H/sr98GgenJ19Nlacs4JMfG0prCtElDEKqVGpQawxw4jY3Xa8euBV/HPvP1Hvrm+3XJQxCucPPB9XDrsSk9InKT8uPT4PNp7YiLcOv4VNJze1vJiMOiM8micg9U+0JCI7NhvZcU1//WP7I94cD6vRiihjFKKMUbAarNDr9S2qPLfPDZfXBafXiTpXHWwuG2xOG2wuG2qdtahz1aHOXdf0/1O/N7gbyIe1DjpYDBYkWZOQZElCojURSZYkmA1mHKo6hEPVh+D2uYU2/OCKD5AenR6QtuhJNE1DcUMxvi37FjtKd+Dbsm9xtOZoy+96nR6p1lSkRach2ZqME/UnkF+b36GKMd4cj2RrMhItiS1S0gRLAuIt8Ui0JCI9Oh0Z0RlIi0pDSlQKjPqwk7UwYYLNZkNCQoJfa5uwGkUzZ87E+++/L+xbs2YNpkyZ0q59ncVigcViCUb1GDR9jc/NmYu5OXMBALvKd+GGT27A+hPr8dftf8Uvp/5Sedzbh9/GH7f8EdHGaLy04CUMTxoezGozCmrtbhRU2XG8qgHHK+0orLIjJzkat84dAr0+8lRpbp8bq4+sxspdK1HRWAEAGBA3ANlx2Yg1xSLWHIsYUwxMehPWF67HsdpjeO+79/Ded+8hNz4XZ+ecjUZPY4sKstpZjdKGUthcreYfs/rNwtXDr8bcnLnQQYdGTyPsHjvsbjvsHjsAtEo1Tkk4HB4HKhorUGYva/mraKxAvCUemTGZyIjOQEZ0BjJjMpEZk4k4c+fhDkKFy+vCkeoj2FOxB28cfAPf1X6Hv+/6O34z8zehrlqHVDmqcOtnt2J/5X7yW5IlCbWuWvg0H8oay1DWWCb8nhWThTEpYzAmdQyGJw1HWlRai4TPZAgfu3Cm7xBQiV19fT2OHm364pk4cSIef/xxnHPOOUhOTsaAAQOwdOlSnDx5Ev/6178ANIU7GTt2LG655RbcfPPN2Lx5MxYtWoTXX3/db6/Yrqxqu4umadAaGwNy7t7I2uNrsezLZQCApdPvxxVDL2/5TdM0rNz1LF7a92LLvrToNPzzgn8iIzpDPhUTBL7Oq8Iv396Finqn8vcbZw/CL+ePCHKtAoemafi88HM8s2slCm0FAIB+sf2waMIizB84v8V8QT5mT8UevHfsfazJXwOHp/3nPdGShEuHXIIrhl6B7LiOA4f2JXaU7cAta2+BQWfAm5e+hQFx4Rs4/pmdK/HSvhdh1BkxMnkkJqRNwIT0CRifNh7J1mR4fV5UO6tR3liOcnsFKh2VSItKw6iUkUixsjMZA+iiogJqW9qVtU1AF3br16/HOeecQ/Zfd911eOmll3D99dcjPz8f69evb/ltw4YNuOeee1oCFP/qV7/qUoDiYCzsfHY7Dk2aHJBzMwzDMAzTuxjx7XboowNnZx42C7tQwAs7hmEYhmGCSTgt7MLKxq63oIuKwohvt4e6GmGH0+vCbZ/dij0Ve1r2RRmj8cicRzCz34yWfYerj+CWtbegwV2Pcweciz+e+ccOnS6YnsHn03DFM5twuKwOt84dgrvmDSNlNE3DHz46gNe+LoDZoMfffzoZMwb1LlXT4eoj+OOWP+BA1QEAwKT0SVg6/X4MjB8Q4pr1TX7z1W/waf6nmNlvFp44Z0WoqyPg03z4wfs/QGFdIX455Ze4esTVoa4S00vRRYVHDDuAJXZMD1PZWIkff/RjnKw/ibSoNDxz3jMYmTySlPum+Bvc8tkt8Pg8uHbktbhv2n19PvZVoPlgdxHueG0H4qxGfHnvuUiIVht2e30a7njtW3y8twRxFiPeWjQTo7LC/1nSNA0v7nsRT377JLyaF3GmOCyZsgRXDrtSaUfHBIdCWyG+95/vwaN58M8L/ompmVO7fa4aRw1e3v8ynF4npmZMxeTMyYg3d39sritYh7vW3YU4cxw++/5nHLKJCVtYFcsLu5Byou4EPjz2IS4behkyYzLbLfdx3se4d+O9AIBHz3oUCwb5n36O6Rpen4YLVmzE0bJ63HPecNx9HpXWtcXh9uKn//wG3+RVIT3OgtW3n4n+ieHzRSrj03x4dOujePXAqwCA8weej6XTliItOi3ENWMA4A9b/oA3D72JCWkT8O8F/+7WR9za42vxhy1/IDECRyWPwrTMaZjVfxamZ07v0rmv/+R6bC/djhvH3ojFkxd3uU4MEyy6srbhz1imx8mOy8YtE27pcFEHAAsGLcBN424CgJYXMhMYPthdhKNl9UiIMuFns3M7LW81GfCPhVMwPCMWZXVOPPX50U6POV2+q/kOV713Fa5+/2q8euBVv1L2AYDb68Z9G+9rGUP3Tr0Xj5/9OC/qwohbxt8Cq8GKXeW7sL5wfZeOrWysxJL1S7Bk/f+3d9/xUdT548dfsy29kk6ABAKhppBQEnpVsZezIedhQUQPlVOs51nuxFPP9pVi4fRUPORE/SkigkAAAekBhVCTkIT03pMt8/tjyUokFbJJSN5PH/PAnf3MzGcmn2ze+6kLKKwupJ9HP24acBN93PtgUS0cLjjMh4c/5N719/JdynctPu/h/MPsy9mHTtFx28DbWndDQnRi0sdOdKiZg2by0a8fcTDvIMeLjsv8dnZgMlt460fr8ndzxvfF3bFlc2t5OOt5asYg/vThHjYm5WCxDLXb/HY7Mnfwl4S/2CYMTtqdxOt7X2dK7ylc1/86RgeObrA5tcJYwcObH+bnrJ/RKTr+PvbvXNn3SrvkUVw4X2df7hh8Bx/88gFvH3gbPxc/ssqzyCzPJKsii6yKLLSKliDXIAJcAgh0CSTINYiTxSf55+5/UlxTjFbRcvewu7kv4j4MWgMAORU57M7ezXfJ37E9czsrj67kqr5XtShPHx+xTrN1eejl+LvI1Eui65DATnQoHycfJvWexIbTG1h9fDVPjnqyo7PU5fy/xEyS8yvwctZzZ3xIq46N69cDF4OW3LIafs0sISLYs83zt+rYKl7a9RJm1cxwv+FMD5nO1ye/5mjhUb5P/Z7vU7/H39mfYT7D6O/Vn/5e/QnzDMNV78qDmx7kSMERnHROvDnxTeJ7xrd5/kTbmD10NquOreJk8UluXXNrq44N9wrnxTEvMqjHoHr7/V38ubrf1cQFxTHtf9M4mHeQE0Un6O/VdFeD7Ips1qeuB+CPg//YuhsRopOTwE50uJv638SG0xv4NvlbHo55GCdd5+3Ldakxmi28vclaW3ffhH64OrTuV95Bp2Vcf1/WHc7mx6TcNg3szBYzr+19jU+TPgXgmn7X8Le4v2HQGpg5aCZHCo7w5YkvWZu8lpzKHHLScvgx7cfzzuPl4MXiKYsZ5juszfIm2p67wZ1HYh7hpV0v4engSaBrIEEuQQS6BBLoGojZYiazIpPsimxbTZ7RbGTWkFncM/SeJldx8HHyYUKvCWxM28jqE6t5YuQTTebls6TPMKkmRgaMPC9YFOJSJ4Gd6HCjg0bT07UnZ8rPsD51PdeGXdvRWeoyvtp/htMFlfRwMfDHuD4XdI4pg/ysgd2RHBZMa5um8kpjJQu3LmRLxhYA5kfP555h99Tr+D64x2AG9xjMo7GPsj93PyeKTnCy+CQnik5wqvgU1eZqerr2ZOnUpYR6hLZJvoR93TTgJm7sf2OLBzioqtritDcNuImNaRv59tS3PDz8YRx1jg2mqzBW8MXxLwCprRNdkwR2osNpFA039r+Rtw+8zRfHv2hVYKeqKkmFSfg7+9PD6dKab83eVFVlcYJ10MP9E/vhbLiwX/fJA/1QFDiSVUpmcRVBbTA69pU9r7AlYwsOWgf+PvbvXB5yeaNpHXWOxAfFEx/0WzOrRbWQU5GDn7OfzIF4iWnNqNXWpI0LjCPQJZCsiiw2nN7A1f2ubjDdVye+osxYRoh7COOCx7X4/EJcKmRUrOgUru9/PTpFR2JeIieKTjSbvsZcw1cnvuKmb2/iljW3cPt3t1NhrGiHnF460gorOV1QiUGr4fZRFz45bw9XB4b39gJg49HcZlI3L78qn29OfQPA25PfbjKoa4xG0RDoGihBnbDRarTc0P8GAFafWN1gmvyqfJYdWgbArMGzZH5D0SVJqRadgo+TDxN7TQQa/1AG6wfz0sSlTP9iOs/ueJbjRccByKzI5J0D77RHVi8Ze1OLABja0/2Ca+vqTBnkB8DGpJyLztfKoysxWoxE+kbWq4UT4mJdF3YdGkXDvpx9JJck13tPVVVe2PkCJTUlDPIexPX9r++gXAphXxLYiU7jpgE3AfDNqW+oNlXXe8+iWlh2cBnTv5jOkoNLKKwuJMAlgAUxC3htwmuAdS68X/J+Oe+8zdmasZUXd75IeW35xd9EJ7L3tDWwiw3xvuhzTRtknQ5ix8kCKmpMF3yealM1q46tAqw1JkK0pQCXAMb1tDavfnn8y3rvfZfyHZvTN6PT6HhxzIvoNS2b9keIS40EdqLTiAuKo6drT8pqy1h/er1tf4WxggUJC1icuBijxUiETwSvjn+VtTesZfbQ2VwWchlX9b0KFZXndz6P0WJs8TUP5x/mkc2PsOr4KhYnLrbHbXWYfaetM/TH9PG66HOF+bnS29uZWrOFbSfyL/g8a5LXUFRTRJBLEFN6T7nofAnxe+d+Qaw11wKQV5nHol2LAOtkyeHe4R2WPyHsTQI70WnUDaIAbKPW0svSuWPtHWxM24heo+eF+BdYceUKLg+9vN437sdGPIaHgwfHio7xyZFPWnS9ouoiHkl4hFqL9cN/5bGVpJWmtfFddYySSiPHc6w1kG0R2CmKctHNsaqq2n42MwfNRKeRsVui7Y3tORY/Jz+KaorYlLbJ2gT78wuU1pYyyHsQdw+7u6OzKIRdSWAnOpXrwq5Dp+g4kHuA/x79L7d9dxsni0/i4+TDvy/7d6P9YrwdvXks9jEAliYuJb0svcnrmC1mFm5dSFZFFr3dejMqYBQmi4k397/Z1rfUIfanWZthQ31c8HF1aJNz1jXHbjqai9nS+iWmt2duJ7kkGRe9i62TuxBtTafR2T4nvjjxBWuS15CQnoBOY12ZRJpgRVcngZ3oVHydfW2DKF7a9RIlNSUM7TGUlVeuJMovqsljr+l3DaMCRlFtrubvP/8dVW08+Hgn8R1+zvrZumLBpDd5fOTjaBQNG05vYH/O/ja8o46xtw2bYeuMCPXGzVFHQUUtienFrT7+48PWJZxu6H8DrgbXNsuXEL93Q/8bUFDYlbWLl3a9BMD9kffLkoWiW5DATnQ6dX1kAK7qexUfXv5hi9ZyVBSFv8b9FYPGwI7MHY0uCL4xbSMf/PIBAM/HP29bpur6MOu3/Nf2vtZkUHgpqBsRG9uGgZ1eq2HCAF+g9c2xx4uOszNrJxpFw8xBM9ssT0I0JMg1yLa8XLmxnME9BnPX0Ls6OFdCtA8J7ESnEx8Uz/zo+Twf/zwvjX2p0RnkG9LHvQ9zI+cC8MruV/j3r/9ma8ZWzpSfwaJaSC1J5ZmfngHgjkF3cEXoFbZjH4x+EGedM7/k/8K61HVte1PtyGi2cDCjGIDYkLYL7ACmDbYG2BuTWjef3adHrMuGTek9hZ6uPds0T0I05Kb+1i+Ieo2ev4/5u/TpFN2GlHTR6SiKwr0R917w8X8a8ifWpqzlZPFJ3tj3hm2/s84ZvVZPubGcGP8YFsQuqHecj5MPdw29i3cS3+HNfW8yufdkHLRt0z+tPR3OLKXaaMHTWU9fn7Zt8pw4wA+tRuFYThnphZX08nZu9pj8qnzWJK8BZAkn0X4m957MIzGP0M+jH/29+nd0doRoN1JjJ7ocvVbP8suW8+foP3NFyBWEeYah0+ioNFVSUlOCr5Mvr014rcFO1H8c8kf8nP3IrMjks6TPOiD3F29v6tn+db290GhaviRTS3g4623Nuz+2sDn282OfW6ep8Y1otp+kEG1Fo2i4a+hdTOg1oaOzIkS7kho70SV5O3ozJ2KO7bXRYiS9NJ2U0hQGew/Gx8mnweOcdE7Mj57PM9uf4f1D73Nd2HV4ObZtc6a97Ts7MXFMGzfD1pk22J9dKYVsTMpl9pjQJtPWmmv5/OjngNTWCSFEe5AaO9Et6DV6+nr2ZUrvKQS6BjaZ9up+VzPQeyBlxjIe3PggK5JWkFycfEkMqFBV9bcVJ/pc/IoTDZlydtqTn5MLqDaam0y7O3s3RTVF+Dj5yITEQgjRDqTGTojf0SgaFo5YyJwNcziUf4hD+YcA8HP2Y3TgaCJ9I9FpdCgoKIqCgoJOoyM+KL7Da/fSC6vIK6tBr1WICPawyzVCejjj5aynqNLIydxyhvZs/DoJ6QkATOo1STqvCyFEO5BPWiEaMCJgBF9e8yUJ6QnszNzJ/tz95Fbm8s2pb/jm1DcNHuPn7Mf709+nr0ff9s3sOermrxva0wNHvdYu11AUhQH+buxKKeR4TlmjgZ2qqmxO3wxgm5tQCCGEfUlgJ0QjQj1CCfUIZfbQ2VSbqjmQe4CdWTtJKU5BRcWiWlDP/pdSnEJmRSaz183m3WnvMtB7YIfk+bdmWPvWHNYFdsdyyhpNk1SYRG5lLk46J0YFjrJrfoQQQlhJYCdECzjqHIkLiiMuKK7B94uqi7hvw30kFSZx1w93sWTKkg4ZAbrv7MTEMXbqX1dnQIAbAMezGw/s6mrr4oPiL8lpY4QQ4lIkgyeEaANejl4sv2w50X7RlNWWMWfDHHZl7WrXPJRUGTmeaw202nIpsYaE+58N7HLKG01zbv86IYQQ7UMCOyHaiJvBjWVTlzE6cDRVpirm/TiPLelb2u36+9OKUFXo08MZXzf71pAN8LdOfHymuIqyauN572eVZ3G08CgaRcO44HF2zYsQQojfSGAnRBty1jvzzpR3mNRrErWWWh7e/DDbz2xvl2v/1gxr/5G5ns4G/N2tweOJ3PNr7RIyEgCI8o3C29G+zcJCCCF+I4GdEG3MQevAvyb+i8tDLsekmngk4REOFxy2+3XrRsTaa/663xvg33g/u7pmWBkNK4QQ7UsCOyHsQK/R89LYlxgVOMrWLJtelm636xnNFhLTiwGItdOKE79XF9j9fmRsWW0Zu7N3AxLYCSFEe5PATgg70Wv1vDnxTcK9wimsLuT+H++nqLqoxcfvO13IglWJ/Jxc0GzaI5mlVBstuDvqCPN1vZhst1jdAIoTvxtAsT1zOyaLiRD3EEI9ml5yTAghRNvqdtOdmM1mjMbzO3uL7kWv16PV2mcC33O5GlxZMnUJd6y9g9Olp3lw44N8cNkHOOmcGj0ms7iKl78/yjcHMwFYfziHbx4cQ99GAjZVVfnk59OAtX+dRqO0/Y00oG7Kk9/X2MloWCGE6DjdKrArLy8nIyPjkljzU9iXoigEBwfj6mr/2i0/Zz+WTV3GrO9ncSj/EAu3LuSNiW+ct8RWVa2Zd7eeYtmWU1QbLSgKBLo7kllSzdxP9/H1A2NwNpz/K/ufHal8sS8DjQJ3j22/VS/6+1mfXV5ZDYUVtXi7GDBajGzN2ApIM6wQQnSEbhPYmc1mMjIycHZ2xtfXF0Vpn1oN0fmoqkpeXh4ZGRn079+/XWru+nr25Z0p73Dv+ntJSE9g6cGl/Dn6z7b3d5zM59H/HSSzpBqAkSHePHv1YPzcHLjy/37ieE45T6z+hbdujapXdn86kc+L3yUB8OQVgxjb38fu91LHxUFHsJcTGUVVHM8pY3TfHiTmJlJWW4aXgxeRvpHtlhchhBBW3SawMxqNqKqKr68vTk6NN4OJ7sHX15fU1FSMRmO7BHYA0X7RPDP6Gf66/a+sTV5rC+wsFpX5KxPJL6+hp6cTT84YyJXDAm0B3OLbh3Pb+z/zzcFMhvf25E9jrP3WUvMreOCz/ZgtKjcM78k949q/P1u4v1u9wK5utYnxwePRatrnuQohhPhNtxs8ITV1AjquHEztPRWNoiGjPIPsimzAOg9cfnkNTnotGxaM56qIoHr5GxnqzVMzBgHw9++S2He6kLJqI/d8vJeSKiNRvTx56fphHXJPtqXFcspQVZXNadbATvrXCSFEx+h2gZ0QHcnV4Mpg78EA7MneA8CuFOuo15g+Xg32oQO4a0wIV0UEYrKozFuxn3kr9nMytxx/dwfemxWDo75jasdsS4tll3Oq+BQZ5RkYNIZG19QVQghhXxLYdTN79+5l5syZHZ2Nbi02IBaAfTn7AGzTmYwKbXxiYUVR+OeNEYT5uZJTWsO2E/k46DS8/8dY/Nwd7Z/pRpw7l13daNhRgaNw1jt3WJ6EEKI7k8Cui7FYLFgslkbfj42NZcWKFe2YI/F7sf7WwG5P9h5UVWVXsnXFiNH9ejR5nIuDjmV3xOBisNbOvXJTBBHBnnbNa3P6+rqgUaCkysi+7IMAjA4c3aF5EkKI7qxbBnaqqlJZa7L71pJpVRRFYdGiRYwcOZK+ffvy448/8uSTTxIdHc2QIUM4fNi6FFV2djaTJk0iJiaGIUOGMH/+fNv5n3vuOWbNmsUNN9xAVFQUn3zyCVdffXW9+w0NDeXQoUMkJCQQG2sNLFJTU/Hx8eHZZ58lJiaGsLAw1q5da4cnLs4V7R+NRtGQVpbGrrQUCipqcdBpiAj2aPbYMD9X1j08nq/mxXNtVM92yG3THPVaQnxcADhedBKA/l79OzJLQgjRrXWbUbHnqjKaGfzsD3a/zpEXLmu0z9S53N3d2b17N//73/+49tprWbVqFYsWLeKVV17hH//4B5999hmenp58++23uLq6Yjabufbaa1m9ejU33XQTAJs3b2b//v34+flRVVXFX/7yF7KzswkICCAhIQFvb28iIiJISEiod+2CggJiYmJ44YUXWLduHQ899BAzZsywx+MQZ7kb3An3CiepMIn/d2wb4ENMHy8cdC3rJ9fL25le3p2nqTPc343k/GLyqq0TKktgJ4QQHcfuNXZLliwhNDQUR0dHYmJi2LZtW6NpExISUBTlvO3o0aP2zmaHuuWWWwAYPnw4Go2GK6+8EoCYmBiSk5MBaxPr448/TmRkJNHR0ezdu5fExETbOa666ir8/PwAcHJy4sYbb+TTTz8F4MMPP2T27NkNXtvFxYVrr70WgLi4OE6dOmWXexT1jQgYAcC+nL0AjAptuhm2Mxvg74bGkIuKBU8HT3o4Xrr3IoQQlzq71th9/vnnPPzwwyxZsoQxY8bw7rvvcsUVV3DkyBF69+7d6HHHjh3D3d3d9trX17dN8+Wk13Lkhcva9JyNXaclHB2tnd+1Wi0ODg62/VqtFpPJBMDrr79OQUEBu3btwtHRkQULFlBdXW1L+/sVFGbPns0999zDnDlzWLNmDW+++WaT1667ntlsblGexcWJ9Y/l4yMfk11zBLicUX0bHzjR2YUHuKFxyAGgn2c/mVJICCE6kF0Du9dff527776be+65B4A333yTH374gaVLl7Jo0aJGj/Pz88PT09Nu+VIUpUVNpJ1JUVERAQEBODo6kpOTw//+9z9bTV9DRo8ejcViYeHChUybNg1v70s3cOiKhvsPR0FB1edicCgnqpdnR2fpgg3wd7UFdmEeYR2cGyGE6N7s1hRbW1vLvn37mD59er3906dPZ8eOHU0eGx0dTWBgIFOmTGHz5s1Npq2pqaG0tLTe1hXNnz+fHTt2EBUVxV133cXUqVObPWb27Nm8++67jTbDio7j4eCBr4N1pYi+wTkdNg9dW+jTwwWdozWw83Ho08G5EUKI7s1u1Vb5+fmYzWb8/f3r7ff39yc7O7vBYwIDA3nvvfeIiYmhpqaGTz75hClTppCQkMD48eMbPGbRokU8//zzbZ7/9nLuyNmQkBDy8/NtrydOnMjevdY+WH369GH37t0NnuO5555rcP9jjz3GY489Vm/fuef8/fVcXV1bNJJXtA2DMQxIxs3zdEdn5aLotRoMTrmYAY0psKOzI4QQ3Zrd2yN/399GVdVG++CEh4cTHh5uex0XF0d6ejqvvfZao4Hdk08+yYIFC2yvS0tL6dWrVxvkXAj7UVWV3Lxg6AEl6rGOzs5FKa8tx6y1zsVXXiYDJ4QQoiPZrSnWx8cHrVZ7Xu1cbm7uebV4TRk9ejQnTpxo9H0HBwfc3d3rbUJ0dqkFlRQUWOehy6o6TUFVQQfn6MKdKrGOpLYY3UjL6+DMCCFEN2e3wM5gMBATE8OGDRvq7d+wYQPx8fEtPs+BAwcIDJTmHdG17EouALMLDhZrcLf37LQnl6KTZycmttQEcCynvINzI4QQ3Ztdm2IXLFjArFmziI2NJS4ujvfee4+0tDTmzp0LWJtRz5w5w8cffwxYR82GhIQwZMgQamtr+fTTT1m9ejWrV6+2ZzaFaHd168P2dY0gqfIMe7P3clmI/afgsYeTxXWBnT+nCsoxmS3otN1yURshhOhwdg3sbrnlFgoKCnjhhRfIyspi6NChrF27lj59rCPnsrKySEtLs6Wvra3l0Ucf5cyZMzg5OTFkyBC+++47WQlBdCmqqrIrxdonbVyvUSQd+/7SrrE7G9hpTYFUmi2cLqykn69rM0cJIYSwB7sPnpg3bx7z5s1r8L2PPvqo3uuFCxeycOFCe2dJiA6VXlhFVkk1eq3CjYPH894xa3BUWF2It2Pz8w2uSFpBRlkGD8c8jIPWodn09lYX2PVy7cuxQjieXSaBnRBCdBBpL+lk9u7dy8yZMwFITU3Fx8fnos/53HPPUVtbe9HnEW2jrhk2MtiTIHdfwjytk/ruy9nX7LFfnfiKl3e/zKdJn/L8juc7fHqaouoi8qusU+YM9rGuEftrZklHZkkIIbo1Cew6mdjYWFasWNGm53z++eclsOtEfk6xBnZ1y4jF+McAsDe76ebYpIIk/rHrH7bX3yZ/y38O/8dOuWyZutq6nq49GdvPOhBk01EZGiuEEB2lewZ2qgq1FfbfmqlNqaqq4pZbbmHw4MFERkYyffp0EhISiI2NbTD9nj17mDx5MrGxsQwfPtw2qKSuZu/ZZ58lJiaGsLAw1q5dC2AbqBIfH09UVBS5ublt+CDFhdiVbO1fNyrUOufbiIARQNMjY0tqSngk4RFqzDWMDx7PEyOfAOD1fa+zNWOrnXPcuFPF1qlOwjzDmDTQD40CSVmlZBRVdliehBCiO7u0FkxtK8ZKeCnI/td5KhMMLo2+vW7dOoqKijhy5AgAhYWFHDp0qMG0xcXF3HfffXz33XcEBgaSn59PTEwMY8aMAaCgoICYmBheeOEF1q1bx0MPPcSMGTNYtmwZ7777Ljt27MDVVfo9dbT0wkrOFFeh0yjE9PECfquxO150nB1ndhDfs/50QBbVwpPbnuRM+RmCXYN5aexLuBvcOVl8ki+Of8HjWx9nxZUr6OvRt93vp67GLswzDG8XA7F9vNmdWsjGpFzujA9p9/wIIUR31z1r7DqJyMhIjh49yrx58/j888/R6/WNpt2xYwfJyclcccUVREVFMXXqVFRV5dgx66oFLi4uXHvttYB1xY5Tp061yz2IllNVlbc2WifbHhbsgYuD9XuVj5OPLbi778f7+POmP5NW+tto8XcPvcu2M9tw0DrwxqQ38HDwQFEUnhr5FMP9hlNuLGf+pvmU1LR/37YTRdb7CfOy9hOcOtgPgA1Hcto9L0IIIbprjZ3e2Vqb1h7XaULfvn05cuQImzZt4scff2ThwoW8+eabDaZVVZWIiAi2bj2/2S01NRVHR0fba61Wi9lsvqisi7b3xobjfLEvA40CD03pX++9tya9xdKDS1l5dCUJ6Qn8dOYnZg2axRCfISxNXArAM6OfYaD3QNsxeq2eNya9wW1rbuN06Wke2/IYS6YuQadpn19rVVVtNXb9Pa33M21wAC+tPcrPyQWUVhtxd2z8y4oQQoi21z1r7BTF2kRq762RNXHrZGRkoCgK11xzDa+99hqqqpKent5g2vj4eE6cOMGmTZts+xITE1s0KMLNzY2SEhmp2JFW7DrN25usQdA/rh/GxHC/eu97OHjwxMgnWH3NasYEjcFkMfHh4Q95dMujqKj8YcAfuC7suvPO6+3ozduT38ZJ58TOrJ18dPijdrgbq7yqPEprS9EoGkI8QgAI9XGhn68LJovKlmMyiEIIIdpb9wzsOolffvmF+Ph4IiIiGD58OLNmzSIiIqLBtF5eXnz77be8+OKLREZGMnjwYJ544gksFkuz1/nLX/7C5MmTZfBEB9lwJIe/fv0rAPOn9Oe2kb0bTdvPsx9Lpy5l8ZTFhLiHADC0x1DbYImGhHuH85eYvwCwKW1To+naWt1SYr3detebT2/qYOta0D8mSXOsEEK0N0Xt6Imw2lhpaSkeHh6UlJTg7u5u219dXU1KSgqhoaH1mi1F99Re5WF/WhG3v/8z1UYLN8cG888bI1CaqcmtYzQb2ZO9hyi/KJybadY/U36Gy1dfjk7RseP2HTjpnNoi+036+PDHvLr3Vab1mcbrE1+37d+bWshNy3bi7qhj31+noZflxYQQ4qI0Fts0RD5xhbCT5Lxy7v5oD9VGC5PCffnH9cNaHNSBtQ9dfM/4ZoM6gCCXIPyc/DCpJn7N//Vist1i546IPVd0by96uBgorTax5+zSaUIIIdqHBHZC2EFyXjkzP9hFUaWRyGAPFs8cbteaK0VRiPKLAiAxN9Fu1zlXY4GdVqMweeDZ0bHSHCuEEO1KAjsh2lhSVik3v7uTrJJq+vm6sPxPI3A22H+karRfNAAHcg/Y/VoW1dJoYAf1+9l1sd4eQgjRqUlgJ0QbOpBWxC3v7iS/vJbBge58fl8cPq4OzR/YBuoCu8S8RCxq84NqLkZmeSZVpir0Gj293Hud9/64/j4YdBrSC6s4nlNu17wIIYT4jQR2QrSRnacKuOODXZRWmxje25P/zhndbkEdwADvATjpnCirLSO5ONmu16pbSizUIxS95vy56pwNOsaG+QAyOlYIIdqTBHZCtIKqqlTUmCirNlJSZaSk0khxZS0bjuTwpw93U1FrJr5fDz65exQeTu07Oa9eo2eYzzAADuTZtzn2RPHZFScaaIatM3WQtTl2vaxCIYQQ7aZ7rjwhRCvkl9ew/WQ+207ks/1kPlkl1Y2mnTLQj8Uzh+Oo17ZjDn8T5RfF7uzdJOYm8ocBf7DbdWwrTnj1bzTNlEF+8BUcTC8mt7QaP3eZZkgIIexNArtOKDU1lfXr1zNnzhzbvpCQENasWcPQoUM7MGfdh8lsYWnCKdb+mk1SVmmz6TUK3Dg8mJduGNah87a11wCKusmJ+3n0azSNv7sjkb08OZhezMajuU1OzCyEEKJtSGDXCaWmpvLee+/VC+zagslkQqeTH3lL/Ht7Cv/acNz2enCgO+P6+zC2vw9RvTzRazUoCmgUBQXrdCNaTcvnqLOXSN9IFBTSy9LJr8rHx8mnza9htBhJLrH24QvzarwpFmDaID8Ophfz45EcCeyEEKIddMu/8qqqUmWqsvt1nHROzU5Iu27dOp566ilMJhNeXl4sXbqUuXPnkpaWRlRUFL179+abb74BYPXq1cyZM4esrCzuvvtunnnmGQCys7OZP38+qampVFdXc9111/HCCy8A1pq+e++9lx9//JGgoCBWrFhh35vuAooqavm/s+u6PjSlP7Pi+rTrIIiL4WZwI8wrjBNFJ0jMTWRqn6ltfo3E3ESMFiOeDp70dO3ZZNqpg/15bf1xtp3Mp6C8hh6XyHMUQohLVbcM7KpMVYz6bJTdr7Pr9l1NrhqQm5vLHXfcwebNmxk2bBgrVqzg5ptvZtmyZTz66KPs3bu3Xvri4mJ27NhBXl4eYWFhzJ49m549e3LnnXfy9NNPM378eEwmE1dddRVfffUV119/PQBpaWls2rSpVasedBUWVaXGZKHGaKbaaKHGZMbNUY9zE13g3tp4grJqE4MC3Zk/pX+nqIlrjWjfaE4UneBA7gG7BHYJ6QkAjA8ej0Zputk53N+NiGAPDmWUsGJXGvOnNN4nTwghxMXrloFdZ7Fr1y6ioqIYNsw6knHmzJk88MADZGVlNZh+5syZAPj6+tK3b19SUlLw9PRk06ZN5OT8NvKwvLyco0eP2l7Pnj272wV1pVVGskuqqTFZUKk/QW5JlZGebg1Hdsl55Xz682kAnp4x6JIL6sA6gGLV8VV2WYFCVVVbYDex18Rm0yuKwt1jQ3loZSIf7zzNfRP64qDrmIElQgjRHXTLwM5J58Su23e1y3WaoqpqgwFXY0HYuYvVa7VaTCYTFosFRVHYs2cPen3D02u4urq2IteXvlqThbTCSixnVzzQKgoOei2Oeg0ms0pptZHMkmqwnD+J7z/XHcVkUZkU7svY/m3fP6091A2gOFJ4hGpTNY66thuNmlKaQlpZGnqNnvig+BYdM2NYIIvWHiW7tJpvEjP5Q+z5ExoL0daKKmq5/YNdDAly59WbIrrdl1vRfXXLeewURcFZ72z3rbkPkri4OBITE0lKSgJg5cqVBAcHM2DAAEpKSlp0L25ubowbN46XX37Zti8zM5OMjIwLf0AdzGyxcDynjOS8cozm1q2goKoqmcVVWFQVF4OOgQHuDA5yJ8zPlWAvZ3r3cMbZoMViUSksr6XGaLYduyu5gB8O56BR4KkZg9r6ttpNT9ee+Dr5YrKY+DX/1zY995b0LQCMDBiJi96lRcfotRr+NCYEgOU/pcgSY6JdfL43naSsUr7Yl8H/9l26n4dCtFa3DOw6C19fXz755BNmzpxJZGQkS5cuZdWqVURERBAeHs7QoUO55pprmj3PihUrSEpKYtiwYQwbNowbb7yRgoKCdrgD+yiqNFJtNFNeY+JkbjmVtaYWH1taZaS02oiiKPT0csKg09QLsDWKQm9vF7QaDbVmlbc2nkBVVSwWlX+stQbYt47sTX9/tza/r/aiKApRflGAdXmxtlTXDDuh14RWHXfbiN446bUczS5jx6lLt2yKS4Oqqny+J932+sVvj5BVYv8Bc0J0Bt2yKbYzufzyy7n88svP279mzZp6r1NTU+u9PndgRUBAAJ999lmD5//9cZ2dqqoUVtQC1iDMaLZwKq+CYC8nvJwNTR5rslg4c3byYF83h0YnCTboNAR6OJCdAT8czqZfoBeuDjoOZZTgYtDyyNQBbXtTHSDaL5oNpze06Xx2xdXFtkBxQnDrAjsPZz03xwbzn52n+WBbMmPCLs1mbnFp+Dm5kJT8ClwMWvr5uXIoo4QnVv/CR7NHSJOs6PKkxk50KlW1ZqqNZjSKwgB/V9wd9aiqSnphJVklVU0242WXVGMyW3DQafFrZloNFwc97k7W7zXPfXOYF9dYa+vun9gPX7dLf0qOun52ibmJWNTWNWc3ZtuZbVhUCwO8BhDkGtTq42ePCUVRYPOxPE7mlrVJnoRoyH93pwFwTVRPXr85CoNOw5bjeazam97MkUJc+iSwE51KwdnaOg8nPQadlj49nPE7G2jlldWQWlBZr19cnYoak62mr6eXE5oWjGZ1c9Qzrr8vRrNKfnkNgR6O3D22bxveTccJ9w7HSedEaW0pKSUpbXLOzembgZaNhm1IiI+Lbf3Yf29PbZM8CfF7RRW1rPs1G4DbR/YmzM+Vv0yz1sL/fU0SmcXSJCu6NgnsRKdhtlgoqTIC4O1ibXZVFIUADyd6ezujURTKqo0cyykjNb+C8mqTtX+cqpJRZP2w9nY24OrQ8h4Gj10eTj9f6yCAxy8fiJOha0zFodfoGepjXX6uLZpjjWYjOzJ3ADAxeOIFn+eesaEArN6XYQvEhWhLq/dnUGu2MCTInWHBHgDcM64v0b09Kasx8cSXv8gAHtGlSWAnOo3iSiMWVcVRr8X5dwGWp7OBfr6uuDlap3QprTaSnF/Oydxy0gsrqTGZ0Wk0BHi0bmoPF4OO1ffHs+q+OK6LbnoVhUtNlG8U0DaB3Z6cPVQYK/Bx8mGIz5ALPs/IUG+G9fSgxmRhxdn5AoVoK6qqsvLsoIlzl7DTahRe+0MkDjoNW4/n1RtYIURXI4Gd6BRUVbU1w3q7GBrs4Oxk0BLq48IAfzd6uBjQKApVRrOtli/I0xGdtvVF2tPZwMhQ74u7gU7o3H52F8s2GjZ4QrOrTTSlbsJigI9/Pk2N6fxmdSEu1N7TRZzMLcdJr+XaqPr9QPv5uvLo9HAA/v5dkoySFV2WBHaiUzh30ISnU8MTLddx1Gvp6eXMwAA3AjwccdBp8XY24NHMcd1NpF8kCgppZWmklaZd8HlUVbXNX9fa0bANmTEskAB3R/LKanhl3TEsFmkWE22jbtDE1ZGBttr9c901NpTo3p6U15h4f2vb9D0VorORwE50CoXnDJpoaa2bTqvBz82R8AA3gr2bnxC6u3E3uDOm5xgA3j307gWf50TxCTIrMnHQOjA6aPRF58ug0/DINOuasct/SuHB/+6nqrZlNXdmi0pKfgXrfs1i8eaT7E4pvOj8iK6hpNLId4esyzHeek4z7Lm0GsU2ndHne9Jstf1CdCUS2HWgqKgooqKiGDx4MDqdzvb6lltuISEhgdjYWLtdOzU1FR+f1s8l1lS+mjvnN998w9y5c22v16xZw8CBAwkLC2P2HbdSWVFuGzRxrpycHG644QYiIiIYOHAgb775pu29jz76CE9PT9uzmzRpku29gwcPMmPGjFbfY1fyQNQDAKxJXkNqSeoFnaOuGXZ04Ohml8lrqVtG9OZff4hEr1VY+0s2t763k9zS6vPS1ZosrPs1i8f+d5Cr/+8nhvxtHZNeS2Dup/t59Ydj3PLeTj7emdomeRL2V1lr4vtfsthxKp+0gkpqTedPxVNtNJOcV85PJ/LZdDSnwTQN+TrxDDUmCwMD3Iju5dlounH9fRjg70pFrZnP91x4TbYQnVW3nKBYVVXUKvv3r1CcnJqsRUpMTASsAVFsbKztNVgDqJYymUzodJ3/R/n000/z7bffAlBeXs7dd9/Nli1b8A0O5YEHH+TDxW+w7K3XzjtuwYIFDBs2jC+//JLy8nLi4+MZM2YMI0aMAGDq1Kl88cUX5x0XGRmJTqcjISGBiRMn2vXeOquhPkOZGDyRhIwElh1axsvjXm7+oN+xNcO2crWJ5twYE0wvb2fu+2QvBzNKuG7xdj64cwSDg9w5mVvG53vS+XL/GVvfyzoOOg0D/N1wc9Sx41QBz/6/w+SV1bBg2gCpte3knvryF75OzLS9VhTwc3Ogp6cTZovKmeIq8svr/7zD/d149Q8RRAR7NnpeVVVtzbC3jujVZDlQFIV7xvZl4epDfLQ9ldljQtFfQN9cITqrzh8N2IFaVcWx4TF2v074/n0ozs4XfLzJZGLevHls374dk8nEf/7zH2JjY22B4Pz589mwYQM33HADt912G/Pnzyc1NZXq6mquu+46XnjhBSwWC/Pnz+fHH3/EwcEBnU7H9u3bbdd49tln+e677ygpKeHtt9+21XCtW7eOp556CpPJhJeXF0uXLmXw4MHn5XHx4sW88cYbBAYGMmFC43/4t23bhqenJyEhIQB8//33xMbGEh4ezonccm754908NPsWlLf/dd6xBw8e5KGHHgLA1dWVCRMm8Mknn9gCu6bcfvvtvP/++902sAOYFzWPhIwE1iavZc6wOfT1bPlcfflV+RzKPwS0Tf+63xsZ6s1X88Zw13/2kJxXwR+W7aC/vxuJ6cW2NL5uDlwf3ZPhvT0Z4O9Gnx4uaDUKqqryf5tO8vqG4/zfppPkl9fw4rVDL2gAjbC/w5kltqCur48LZ4qrqDFZyCmtIae0pl5aZ4OWnp5O5JfXcCynjOsWb2fO+H48PLV/gyvKJKYXczS7DAedhuujg5vNy7XRQbzywzEyS6pZ+0sW10Z1rRHxonvrloHdpeLw4cN88MEHLFmyhGXLlvH000/zww8/AFBQUEBYWBjPPvssAJdddhlPP/0048ePx2QycdVVV/HVV18REhLCxo0bOXLkCBqNhpKSEgwGg+0cMTExvPDCC6xbt46HHnqIGTNmkJubyx133MHmzZsZNmwYK1as4Oabb+bXX+svKH/o0CH+8Y9/cODAAfz9/Zk3b16j95KQkEB8fLztdVpaGn369LENmgju3YeszEwsFgsaTf0/zCNGjOCzzz4jNjaW/Px8fvjhBwYOHGh7f8uWLURFReHi4sIjjzzCTTfdZHsvPj6ehx9++MJ+AF3EoB6DmNJ7ChvTNrL04FJenfBqi4/9IdVa3gb3GIyfs59d8hfi48JX94/h/hX72HGqgMT0YrQahckD/bg5theTwn0bDNYURWH+lP74uDrwzNe/8N/d6RSU1/L2bdGNLicnOs6rPxwD4JrIIN6+Ldo2Ev5MURVniqvQaazrO/f0dMLDSY+iKBSU1/Dct0f49mAmy7acYsORbF65KZKoXp78eqaEnckF7DxVwJ5Ua1/LK4cF4uHc/CAqB52WP8b14fUNx1n+UwrXRAZJba/oMrplYKc4ORG+f1+7XOdihIeH2/qzxcXF8dprvzVTOjo6cttttwFQUVHBpk2byMnJsb1fXl7O0aNHmTx5MkajkbvuuotJkyZx5ZVX2gInFxcXrr32Wtv5T506BcCuXbuIiopi2LBhAMycOZMHHniArKysevlLSEjgyiuvxN/fuprAnDlzWLVqVYP3kpGRUS8Yq5N1tl+VRwMj2Or861//4tFHH2X48OEEBAQwefJk8vLyALjqqqu4+eabcXZ2JikpienTpxMcHMzo0dZO/gEBAeTk5GA0GtHru++o2fsj72dj2kZ+SP2BeyPuZYBX8+vh7svZx+t7XwfgipAr7Jo/D2c9/7lrJO9vS0anUbguuid+bi2bk/D2Ub3xdtEzf2Ui64/k8Mflu3lnZnSLjxf2tyu5gIRjeeg0CgvOrgKhKAo+rg74uDoQ2UifuB6uDvzfbdFcFRHIM1//yqm8Cm5atgNXg46yGlO9tL5uDtw7vuW10TNH9Wbx5pMcyihhT2pRl5zySHRP3TOwU5SLaiJtL46Ov/1h0mq1mEy/fZC5uLjYvmFaLBYURWHPnj0NBi+HDx9my5YtbN68mSeffJKtW7ei0+nOO7/ZbB2ZqKpqg99ef7+vsdnbCytqySurwc/NAa+zgyGcnZ2pOqdfY69evfjuhw1U1JjQKAoV+Vn07NnzvNo6AG9vb/7973/bXs+dO9fWLHzuYI1BgwYxY8YMtm/fbgvsqqur0ev13TqoA+sSY9P7TGf96fUsO7iM1ye+3mT6k0Un+fOmP1NrqWVSr0ncMfgOu+dRr9Uwb2LYBR17+dBAPr7LwL3/2cvu1EKm/msLT185iJtjm+5vJexPVVVeOVtbd+vIXoT4uLT6HJcNCWBUqDcvrkli9f4MympMuDnqGBXag7h+PYjr24OBAW4tWkqwTg9XB26MCeazXWm8vy1ZAjvRZUhnlC7Azc2NcePG8fLLv3WMz8zMJCMjg7y8PCoqKpg+fTovvfQSISEhHDlypMnzxcXFkZiYSFJSEgArV64kODiYgICAeukmTZrE2rVryc3NBWD58uWowJmiKmpMZtKLKskprUZVVSIiIjh69Kjt2Oj4iSTu30fqyRP06eHM8vff5dZbb20wPwUFBRiN1mkJ9u/fz9dff21r9j1z5owtXU5ODps2bSI6Otq2LykpiYiIiOYeYbdwf+T9KChsOL2Bo4VHG02XXZHN3B/nUlZbRpRvFK+MfwWdpvN/Bxzdtwer58UztKc7pdUmHl/9C7e9/zMp+RUdnbVubWNSLvtOF+Go1zB/cv8LPo+ns4F/3RzJDw+P59sHx5L47HQ+uDOWu8eGMjjIvVVBXZ27xlgny/4xKUfKiegyJLDrIlasWEFSUhLDhg1j2LBh3HjjjRQUFJCens60adOIiIhg2LBhDB06lCuuaLpZzdfXl08++YSZM2cSGRnJ0qVLG2xijYiI4KmnniI+Pp6xY8fi5x+AxaKiotr6OOWUVnOmqIoZV17Jtm3bMJvN5JXVUIWB5155i0fn3EH00EGcOXOGp556ynbuqKgoMjOtHa13797NoEGDGDRoEHPnzmXVqlUEBgYC1sEbQ4YMISoqimnTpvHII48wefJk23nWrVvHjTfeeNHPtysI8wrj8tDLAViSuKTBNCU1Jdz/4/3kVObQ16Mv70x5B0fdpdOkOcDfja/njeHpGYNw1Gv4ObmQy97cyuLNJzGaWzZthmg7Zotq61t315hQ/NwvviyFB7gxLNgD7QUEcr8X5ufK5IF+qCp8uF0mLBZdg6J2sdWQS0tL8fDwoKSkBHd3d9v+6upqUlJSCA0NrdcEKdqGyWzhZF45tSYLLgYdob4uFFXUkllchQq4Oep55a+PMmrMeIZPtAaWAR6Odu0HVVtby4gRI9i4ceN58+t11/KQXJLM9f/veiyqhUdjHyXcO5xebr3wd/bHrJqZs34O+3P34+fkx6czPiXQNbCjs3zB0goqefrrX9h2Ih+Afr4uPHbZQC4b4i/Ns+3ky/0ZLFh1EA8nPVsXTuqUq8PsOJXP7e/vwkmvZeeTk/F0Pn8uTSE6WmOxTUM6f/uK6PQsqsrps5ONGnQa+vRwRqMo9HB1QK/VkFZYSVm1kTsffJzNG9cD1v4tvq4Ods1XSkoKixYtuqCJmLuqvh59uTL0Sr5N/pbX9v42GEen6HB3cKewuhBXvStLpy29pIM6gN49nPn4rpF8uf8Mf//uCKfyKpj76T6ie3vy+OUDGd23R7PnqDaa+eFwNqv2pnM4sxQPJz1ezga8XQx4ORvo4WpgVKg3E8P92qQGqSupMZl5fcNxAOZO6NcpgzqAuL49GBzozpGsUl794Rj3jutLnx6yko24dNm9xm7JkiW8+uqrZGVlMWTIEN58803GjRvXaPotW7awYMECDh8+TFBQEAsXLqy3WkFzpMaufamqSkZRFUWVtWg1Cv18Xc+baqKy1kRqfiUmi7UpzMNJT+8OXgKsO5eHwupClv+ynJSSFNLL0jlTfgajxdqHUa/R8+60dxkR0PwcgZeS0moj721JZvlPKVQZrYOEJob78tCU/vTp4YKbo67eJLW/nilh1d50vj5whtJqU2Ontenp6cStI3pxy4hebdLcWG0046DTXNLBxUfbU3ju2yP4uTmw5bFJOBk67xQ0dTWLdXzdHBgR4kVsH2/C/Fwpqqwlp7T67Jx71eSX1+Dv7siwnh5E9vJkSJA7zgapJxH205oaO7sGdp9//jmzZs1iyZIljBkzhnfffZcPPviAI0eO0Lv3+Wv5paSkMHToUO69917uu+8+tm/fzrx58/jvf//b4n5SEti1D1VVqTVbKCyvJa+8BgWFEB/nBhfeBqg1mUkvrEKnVejl5XxBHZ3bkpSH35gtZvKq8kgvS8fHyYdQj9COzpLd5JZW8/amE6zcnY7JUv+jz0GnsQV4WSW/LW/W09OJP8QGM3WQPzUmM4UVRgoraiisMHKmuJI1h7IorrQGxjqNwrTB/lw+NACLqlJeY6ayxkRFrfVfsK5XqtEo6DQKGkWhxmQht7Sa7LNbbmkN5TUmDDoNAe6OBHpYtwAPJ3p6OtLL25ne3s4Eezlj0F18N2lVVakymimtMlFabaS0ykhptZGy3wW0iqKgAE56LV4u1lpLb2cDbo46FAVSCyo5lFHMwfQSDmYU80tGCbVmC/+4figzR/W56Hzak8Wi8u/tKaz7NZtDZ/PdGhoF+vu5MTDQDT83B3qcncalh6sBHxcHPJ31eDrrcXXQXdLBuug4nSawGzVqFMOHD2fp0qW2fYMGDeK6665j0aJF56V//PHH+eabb2yjMcE6tcXBgwfZuXNni67ZXGAXEhKC00XOLwdgsZi5kCen/u6Fioqqnt2vqqjWf86+rZ7z/6BgXYJHQaHus6HuQ+K8jwqlgX2NaChdXT7Pvb7FolJZa6ai1kRlrRnTOR9+gZ5O9GjTvimtfbit+7Csqqoi9fRpQnsH4ejQVk3CLc1DZ+nW2tRPvhmNFv62uLdGnmMb/kE8XVDBWxtPknAsl4pa83nvG7Qapg7y46aYYOL69mjyi0i10cwPR7JZuTud/WnFbZbHZikQ5O5ETy8n3B31OBk0OOm1OBq0OOm16DQKNWYLtSYLprP/1pgslFabKK0yUlxlpKzKSEm1EZP5wn9uGo2CQauh2nj+cxwZ6sW/7xxhhyW77BccVZvM/HqmlH2nC9l3upiMokp8XB3wczPg5+6Ir6s1cMsoquSXM6X8eqaY3LKa5k+M9Vl5OOqtTfouBvzcHPBzd8DfzRF/d0d83R1w0WvRazUYdAo6rQa9VoNOozT4t8FkVjFZLJjMKkazBaPZgtkCZlW1bhYVi0XFoqpYzu63WKzvWVRrUK9RlLOb9e+JRgGd9uw+jYJWo6BVrJtGg/X/z34p0Wrqb3VfWOr+Tp17TqWhP0rquf/72wtVtXbxUTn779nXZsvZ/6+7B4v1PiyqaktnPnu/8NuXkd//3axT97ruuVrOeS4WFcznnK/uX/Xsder+btddNyrEBz+P1k/l01Kdoo9dbW0t+/bt44knnqi3f/r06ezYsaPBY3bu3Mn06dPr7bvssstYvnx5oxPM1tTUUFPz2y9VaWlpg+fW660zmefl5eHr63vR35pqc09gwHhR52iM8rt/m6L+7l97UgCXs9t5CqG6sB0y0QZUFfIqzCi5qehXTwLz+YvPi66tD/A6WOcFaKzC9uTZrRmOwLVnt0bPZS81QPZFnkN/drtYDbW0ZgGtX564QzkCsWc3mzKs99LUQS1lASrObrmtzZ3orA6Ofx+/yTd3dDYAOwZ2+fn5mM1m26oEdfz9/cnObviTKDs7u8H0JpOJ/Px82xQX51q0aBHPP/98s/nRarUEBweTkZFBampqy2+kEabiXHQ03/dGdE5KTSnBif9CK0GdEEKIi+TcifqQ2r23Z0OrFTRVW9bY6gaNHfPkk0+yYMEC2+vS0lJ69erVYFpXV1f69+9vm+z2YtRU+qKqDffDaKqmTVHqqqnPqaLuwD4Xzf08uiYFvU6HNq65ZbI6S5NpZ9CKMnIx5cluPUPs27R/8dcToutRz2lGtTTyK2HrVmR7bf2/jv7b2Fr9dRffxaut2C2w8/HxQavVnlc7l5ube16tXJ2AgIAG0+t0Onr0aHhqAgcHBxxa0UdKq9Wi1V58ZN3dO9wLIYQQTVHObrISQvuy2/M2GAzExMSwYcOGevs3bNhAfHx8g8fExcWdl379+vXExsZ2+7U+hRBCCCGaY9em2AULFjBr1ixiY2OJi4vjvffeIy0tzTYv3ZNPPsmZM2f4+OOPAesI2HfeeYcFCxZw7733snPnTpYvX85///vfFl+zrum2sUEUQgghhBCXkrqYpkUTmah2tnjxYrVPnz6qwWBQhw8frm7ZssX23p133qlOmDChXvqEhAQ1OjpaNRgMakhIiLp06dJWXS89PV3F2sFFNtlkk0022WSTrcts6enpzcZBXW6tWIvFQmZmJm5ubnbteFk3SCM9Pb3ZOWVEy8lzbXvyTO1Dnqt9yHNte/JM7aM9n6uqqpSVlREUFIRG03Qvui63BopGoyE4OLjdrufu7i6/KHYgz7XtyTO1D3mu9iHPte3JM7WP9nquHh4eLUong1WEEEIIIboICeyEEEIIIboICewukIODA3/7299aNYeeaJ4817Ynz9Q+5LnahzzXtifP1D4663PtcoMnhBBCCCG6K6mxE0IIIYToIiSwE0IIIYToIiSwE0IIIYToIiSwE0IIIYToIiSwa8KSJUsIDQ3F0dGRmJgYtm3b1mT6LVu2EBMTg6OjI3379mXZsmXtlNNLS2uea0JCAoqinLcdPXq0HXPcuW3dupWrr76aoKAgFEXh66+/bvYYKavNa+1zlbLavEWLFjFixAjc3Nzw8/Pjuuuu49ixY80eJ+W1cRfyTKWsNm/p0qVERETYJh+Oi4vj+++/b/KYzlJOJbBrxOeff87DDz/M008/zYEDBxg3bhxXXHEFaWlpDaZPSUlhxowZjBs3jgMHDvDUU08xf/58Vq9e3c4579xa+1zrHDt2jKysLNvWv3//dspx51dRUUFkZCTvvPNOi9JLWW2Z1j7XOlJWG7dlyxYeeOABfv75ZzZs2IDJZGL69OlUVFQ0eoyU16ZdyDOtI2W1ccHBwbz88svs3buXvXv3MnnyZK699loOHz7cYPpOVU6bXU22mxo5cqQ6d+7cevsGDhyoPvHEEw2mX7hwoTpw4MB6++677z519OjRdsvjpai1z3Xz5s0qoBYVFbVD7i59gPrVV181mUbKauu15LlKWW293NxcFVC3bNnSaBopr63TkmcqZfXCeHl5qR988EGD73Wmcio1dg2ora1l3759TJ8+vd7+6dOns2PHjgaP2blz53npL7vsMvbu3YvRaLRbXi8lF/Jc60RHRxMYGMiUKVPYvHmzPbPZ5UlZtS8pqy1XUlICgLe3d6NppLy2TkueaR0pqy1jNptZuXIlFRUVxMXFNZimM5VTCewakJ+fj9lsxt/fv95+f39/srOzGzwmOzu7wfQmk4n8/Hy75fVSciHPNTAwkPfee4/Vq1fz5ZdfEh4ezpQpU9i6dWt7ZLlLkrJqH1JWW0dVVRYsWMDYsWMZOnRoo+mkvLZcS5+plNWW+eWXX3B1dcXBwYG5c+fy1VdfMXjw4AbTdqZyqmvXq11iFEWp91pV1fP2NZe+of3dXWuea3h4OOHh4bbXcXFxpKen89prrzF+/Hi75rMrk7La9qSsts6DDz7IoUOH+Omnn5pNK+W1ZVr6TKWstkx4eDiJiYkUFxezevVq7rzzTrZs2dJocNdZyqnU2DXAx8cHrVZ7Xi1Sbm7ueRF5nYCAgAbT63Q6evToYbe8Xkou5Lk2ZPTo0Zw4caKts9dtSFltP1JWG/bnP/+Zb775hs2bNxMcHNxkWimvLdOaZ9oQKavnMxgMhIWFERsby6JFi4iMjOStt95qMG1nKqcS2DXAYDAQExPDhg0b6u3fsGED8fHxDR4TFxd3Xvr169cTGxuLXq+3W14vJRfyXBty4MABAgMD2zp73YaU1fYjZbU+VVV58MEH+fLLL9m0aROhoaHNHiPltWkX8kwbImW1eaqqUlNT0+B7naqctvtwjUvEypUrVb1ery5fvlw9cuSI+vDDD6suLi5qamqqqqqq+sQTT6izZs2ypU9OTladnZ3VRx55RD1y5Ii6fPlyVa/Xq1988UVH3UKn1Nrn+sYbb6hfffWVevz4cfXXX39Vn3jiCRVQV69e3VG30OmUlZWpBw4cUA8cOKAC6uuvv64eOHBAPX36tKqqUlYvVGufq5TV5t1///2qh4eHmpCQoGZlZdm2yspKWxopr61zIc9UymrznnzySXXr1q1qSkqKeujQIfWpp55SNRqNun79elVVO3c5lcCuCYsXL1b79OmjGgwGdfjw4fWGj995553qhAkT6qVPSEhQo6OjVYPBoIaEhKhLly5t5xxfGlrzXP/5z3+q/fr1Ux0dHVUvLy917Nix6nfffdcBue686qYu+P125513qqoqZfVCtfa5SlltXkPPE1A//PBDWxopr61zIc9Uymrz7rrrLtvfKV9fX3XKlCm2oE5VO3c5VVT1bO8+IYQQQghxSZM+dkIIIYQQXYQEdkIIIYQQXYQEdkIIIYQQXYQEdkIIIYQQXYQEdkIIIYQQXYQEdkIIIYQQXYQEdkIIIYQQXYQEdkIIIYQQXYQEdkIIIYQQXYQEdkIIIYQQXYQEdkIIIYQQXYQEdkIIIYQQXcT/ByOlds33R5f0AAAAAElFTkSuQmCC", + "text/plain": [ + "
" + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], "source": [ "error_idx = 0 # which false pos/neg to look at\n", "# you can replace ww_false_detects with ww_false_rejects to view false negatives\n", - "clip_idx = np.nonzero(ww_false_rejects)[0][error_idx] \n", + "clip_idx = np.nonzero(ww_false_detects)[0][error_idx] \n", "clip_range = slice(clip_idx-2*Flags.sample_rate,clip_idx+2*Flags.sample_rate)\n", "print(f\"Examining clip from {clip_range.start} to {clip_range.stop}\")\n", "wav_clip = long_wav[clip_range]\n", - "examine_clip(wav_clip, model_tv, feature_extractor_long)" + "examine_clip(wav_clip, model_tv, feature_extractor_long)\n" ] }, { @@ -753,47 +1331,100 @@ }, { "cell_type": "code", - "execution_count": null, - "id": "bbde0e4f-c30e-45c1-aa4f-8afe5b3ef76c", + "execution_count": 56, + "id": "d349c1ed-fa8f-4c3c-91ca-97149d62ad8a", "metadata": {}, "outputs": [], "source": [ - "yy_q = np.nan*np.zeros((long_spec.shape[0]-model.input.shape[1]+1,3))\n", - "t0 = time.time(); \n", - "preds_q = []\n", - "labels = []\n", + "def run_tfl_model(tfl_interpreter, input_features):\n", + " input_details = tfl_interpreter.get_input_details()\n", + " input_shape = input_details[0]['shape']\n", + " input_scale, input_zero_point = input_details[0][\"quantization\"]\n", + " \n", + " output_details = tfl_interpreter.get_output_details()\n", + " output_shape = output_details[0]['shape']\n", "\n", - "for idx in range(long_spec.shape[0]-model.input.shape[1]+1):\n", - " spec = long_spec[idx:idx+input_shape[1],:,:]\n", - " spec = np.expand_dims(spec, 0) # add batch dimension \n", - " spec_q = np.array(spec/input_scale + input_zero_point, dtype=np.int8)\n", + " num_frames = input_features.shape[0]-input_shape[1]+1\n", " \n", - " interpreter.set_tensor(input_details[0]['index'], spec_q)\n", - " interpreter.invoke()\n", - " # The function `get_tensor()` returns a copy of the tensor data.\n", - " # Use `tensor()` in order to get a pointer to the tensor.\n", - " yy_q[idx,:] = interpreter.get_tensor(output_details[0]['index'])\n", + " yy_q = np.nan*np.zeros((num_frames, output_shape[1]), dtype=np.int8)\n", + " if input_features.dtype.kind in ['i', 'u']: # matches any int or unsigned int\n", + " # assume already quantized\n", + " longspec_q = input_features\n", + " elif input_features.dtype.kind == 'f': # matches any float\n", + " # we need to quantize\n", + " longspec_q = np.array(input_features/input_scale + input_zero_point, dtype=np.int8)\n", "\n", - "# Dequantize so that softmax output is in range [0,1]\n", - "yy_q = (yy_q.astype(np.float32) - output_zero_point)*output_scale\n", + " # ensure singleton batch, feature dimension\n", + " longspec_q = np.expand_dims(np.squeeze(longspec_q), [0,2])\n", + " preds_q = []\n", + " labels = []\n", + " \n", + " for idx in range(num_frames):\n", + " spec_q = longspec_q[0:1, idx:idx+input_shape[1],:,:]\n", + " \n", + " tfl_interpreter.set_tensor(input_details[0]['index'], spec_q)\n", + " tfl_interpreter.invoke()\n", + " # The function `get_tensor()` returns a copy of the tensor data.\n", + " # Use `tensor()` in order to get a pointer to the tensor.\n", + " yy_q[idx,:] = tfl_interpreter.get_tensor(output_details[0]['index'])\n", + " \n", + " # Dequantize so that softmax output is in range [0,1]\n", + " # yy_deq = (yy_q.astype(np.float32) - output_zero_point)*output_scale\n", "\n", + " print(f\"type:{yy_q.dtype}, min={np.min(yy_q)}, max={np.max(yy_q)}\")\n", + " \n", + " \n", + " return yy_q" + ] + }, + { + "cell_type": "code", + "execution_count": 58, + "id": "bbde0e4f-c30e-45c1-aa4f-8afe5b3ef76c", + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "Ran quantized model on long wave in 43.52 s\n", + "type:float64, min=-128.0, max=127.0\n" + ] + } + ], + "source": [ + "t0 = time.time();\n", + "yy_q = run_tfl_model(interpreter, long_spec)\n", "t1 = time.time(); \n", - "print(f\"Ran quantized model on long wave in {t1-t0:1.2f} s\")" + "print(f\"Ran quantized model on long wave in {t1-t0:1.2f} s\")\n", + "yy_deq = (yy_q.astype(np.float32) - output_zero_point)*output_scale" ] }, { "cell_type": "code", - "execution_count": null, + "execution_count": 60, "id": "bbbd6f83-22d5-463f-ae1c-1e49a2d2486b", "metadata": {}, - "outputs": [], + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "4 false detections.\n", + "44 true detections.\n", + "6 false rejections.\n" + ] + } + ], "source": [ "det_thresh = 0.95\n", + "det_thresh_q = int(det_thresh/output_scale + output_zero_point)\n", + "\n", "## shows detection when wakeword activation is strongest output\n", "# ww_detected_spec_scale = (np.argmax(yy, axis=1)==0) # detections on the time scale of spectrograms\n", "\n", "## shows detection when ww activation > thresh\n", - "ww_detected_spec_scale = (yy_q[:,0]>det_thresh).astype(int)\n", + "ww_detected_spec_scale = (yy_q[:,0]>det_thresh_q).astype(int)\n", "\n", "ww_true_detects, ww_false_detects, ww_false_rejects = util.get_true_and_false_detections(ww_detected_spec_scale, ww_present, Flags)\n", "\n", @@ -804,10 +1435,21 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 62, "id": "89671bb6-294b-4ead-949d-d38891b2a9f6", "metadata": {}, - "outputs": [], + "outputs": [ + { + "data": { + "image/png": "iVBORw0KGgoAAAANSUhEUgAAAjAAAAGdCAYAAAAMm0nCAAAAOnRFWHRTb2Z0d2FyZQBNYXRwbG90bGliIHZlcnNpb24zLjEwLjAsIGh0dHBzOi8vbWF0cGxvdGxpYi5vcmcvlHJYcgAAAAlwSFlzAAAPYQAAD2EBqD+naQAAUjhJREFUeJzt3XtcVNX6P/DPAMNwkRlFRSDx+vV+Cy8ppqgpeEnTOqaWB8HjyTyhEpxSMW9o3r4nEy2zTj+DzLzkwVuFJZZAJloqkEfJskg8CJGljDdgYNbvDw/768AMzB6G0Y2fd6952V6z1trPevbAPOzZM6MSQggQERERKYjTvQ6AiIiISC4WMERERKQ4LGCIiIhIcVjAEBERkeKwgCEiIiLFYQFDREREisMChoiIiBSHBQwREREpjsu9DsBejEYjLl++DC8vL6hUqnsdDhEREVlBCIHr16/D398fTk7Wn1dpMAXM5cuXERAQcK/DICIiIhtcunQJLVu2tLp/gylgvLy8ANxJgFartXkeg8GAQ4cOITQ0FGq12l7hUQ2Yc8divh2POXc85tzxbM25Xq9HQECA9DxurQZTwFS+bKTVautcwHh4eECr1fJB7yDMuWMx347HnDsec+54dc253Ms/eBEvERERKQ4LGCIiIlIcFjBERESkOA3mGhgiIqpOCIHy8nJUVFTc61AcymAwwMXFBSUlJQ/c2u8VSzl3dnaGi4uL3T/ihAUMEVEDVVZWhoKCAty6deteh+JwQgj4+vri0qVL/GwwB6kp5x4eHvDz84Orq6vd9scChoioATIajcjNzYWzszP8/f3h6ur6QD2RG41G3LhxA40aNZL14WhkO3M5F0KgrKwMv/32G3Jzc9GhQwe7HQ8WMEREDVBZWRmMRiMCAgLg4eFxr8NxOKPRiLKyMri5ubGAcRBLOXd3d4darcbFixel++2BR5WIqAHjkzfdD+rjccgzMA+YvDzgyhXL9zdrBrRq5dgYysuBn37SITMTcHGxXwz3w1rNuV/jkqMhrMFaD9JaiZREVgGzefNmbN68Gb/88gsAoFu3bliyZAlGjx5tcUxaWhpiYmJw9uxZ+Pv7Y968eZg1a5ZJn6SkJCxevBg//fQT2rdvj5UrV+LJJ5+UvxqqUV4e0KkTUFJiuY+bG3D+fP39QjYfgxrAULvGcD+sVUlxydEQ1mCtB2mtREoj65xOy5YtsWbNGpw8eRInT57EY489hvHjx+Ps2bNm++fm5mLMmDEYPHgwMjMzsXDhQsydOxdJSUlSn4yMDEyePBlhYWHIzs5GWFgYJk2ahBMnTtRtZVTNlSs1/yIG7txf01+bSonhflirOfdrXHI0hDVY60Faa0OQmJiIxo0b3+sw7ju//PILVCoVsrKy7nUodiWrgBk3bhzGjBmDjh07omPHjli5ciUaNWqE48ePm+3/9ttvo1WrVoiPj0eXLl3w17/+FX/5y1/w2muvSX3i4+MREhKC2NhYdO7cGbGxsRg+fDji4+PrtDAiIqqDZcuAFSvM37dixZ3760FERARUKlW124ULF+plf3IkJiZK8Tg7O6NJkybo378/li9fjuLiYllzpaamQqVS4dq1a3aNMSIiAhMmTDBpCwgIQEFBAbp3727Xfd1rNl8DU1FRgd27d+PmzZsICgoy2ycjIwOhoaEmbSNHjsSWLVtgMBigVquRkZGB6Ojoan1qK2BKS0tRWloqbev1egB3PkjHYDDYsCJI4+/+tyEpLwfuvFxTWz8D6mv5jorhflir+f0B9zquuj7G74c1OIq91novfq8YDAYIIWA0GmE0GuVP4OQEpyVLYBQCWLTo/9pffRVOS5fCGBcH2DJvLYQQGDlyJN577z2T9ubNm9e6jsr7jUYjhBDSfDat38L8Wq0WOTk5EELg2rVrOHbsGNauXYuEhAR89dVX8Pf3t3quyn/tFR9wZ71V16xSqeDj42Oy3/pQU84rj4nBYICzs7PJfbb+XMguYM6cOYOgoCCUlJSgUaNG2Lt3L7p27Wq2b2FhIVq0aGHS1qJFC5SXl+PKlSvw8/Oz2KewsLDGOFavXo24uLhq7YcOHbLLWwZTUlLqPMf95qefdLj7WhNLjh79GgUF8v6auN9iuB/Was79FJetj/H7aQ31zd5rdeTvFRcXF/j6+uLGjRsoKyuTP8HcudCUlsJ96VLcLi1F6csvQ/OPf8B91SrcXrgQpXPnAv/9w9GeKp/gqv4ev3nzJjZt2oQPP/wQFy9eROPGjTFq1CjExcWhUaNGAICSkhIIIaQ/aM+cOYOFCxciKysLKpUK7dq1w/r16xEYGAgAOHHiBOLi4pCZmQlvb2+MHTsWS5Ysgaenp9nYSv77emJlbJ6ennj66acxdOhQBAUFISYmBv/85z8B3HkS37hxIxISEvDrr7+iffv2ePnllzF+/Hjk5eVh+PDhAICmTZsCAJ555hm89dZbNY6rlJOTg6VLl+L48eMQQqB79+546623sGvXLmzduhUApCLh448/RqtWrdCrVy+kp6ejR48eAICvv/4aS5Yswb///W80adIEU6ZMwaJFi+DicqcsGDt2LLp16waNRoMPPvgArq6umD59OhYsWCDFsWbNGmzbtg2//fYbvL298cQTT2Dt2rW4fv16tdyVlZXh9u3bSE9PR/mdvwwktn7QouwCplOnTsjKysK1a9eQlJSE8PBwpKWlWSxiqn5wUmWFdne7uT61feBSbGwsYmJipG29Xo+AgACEhoZCq9XKWtPdDAYDUlJSEBIS0uC+gj0z07p+gwY9iv/+fCs2hvthrebcD3HV9TF+P6zBUey11nvxe6WkpASXLl1Co0aNbP/cjRUrYNRo4L50Kdxeew2qsjIY4+KgWbQIGvuGK1Gr1XBxcTH7e9zDwwNvvPEG2rRpg9zcXMyePRsrV67Epk2bAABubm5QqVTQarUQQmDmzJno06cP3nnnHTg7OyMrKwuNGzeGVqvFmTNnMHHiRCxfvhwJCQn47bffMHfuXLzyyivVzv5Uunv+u2m1WkydOhUJCQnw9PSEs7MzFi1ahL1792Lz5s3o0KED0tPT8fzzz6NVq1YYNGgQdu/ejaeffho5OTnQarVwd3eHVqutcdyQIUOQn5+PsWPHYsiQITh8+DC0Wi2+/vpruLm5YeHChfj555+h1+ulNXh7e+Py5csA7hRcWq0W+fn5mDRpEsLDw/HBBx/g+++/x/PPPw+dToelS5cCuFMA79y5E9HR0Th+/DgyMjLwl7/8BcOGDUNISAj+9a9/YfPmzdi+fTu6deuGwsJCZGdnAwC8vLyqPYeXlJTA3d0dwcHB1R6PelsLYVFHw4cPFzNnzjR73+DBg8XcuXNN2vbs2SNcXFxEWVmZEEKIgIAA8frrr5v0ef3110WrVq1kxVFcXCwAiOLiYlnjqiorKxP79u2T4mtITp0SAqj9duqU8mO4H9Z6v8ZV18f4/bAGR7HXWu/F75Xbt2+Lc+fOidu3b9d9MlfXOwt1da37XLUIDw8Xzs7OwtPTU7pNnDjRbN+PPvpING3aVNpOSEgQOp1OCCFERUWF8PLyEu+9957ZsWFhYdWeu7766ivh5ORkMWd3z1/V5s2bBQDx66+/ihs3bgg3Nzdx7Ngxkz4zZswQzzzzjBBCiCNHjggA4urVq9L91oyLjY0Vbdu2tfhYCg8PF+PHjzdpy83NFQBEZmamEEKIhQsXik6dOgmj0Sj12bRpk2jUqJGoqKgQQggxZMgQMWjQIJN5+vXrJ+bPny+EEGLdunWiY8eOJnFUVFSIq1evSnPcrabHo63P33X+ZBkhhMm1KHcLCgqqdsr00KFD6Nu3r/RXiKU+AwcOrGtoRERUVytWAGVlgKvrnX8tXdhrR8OGDUNWVpZ027hxIwDgyJEjCAkJwUMPPQQvLy9MmzYNv//+O27evGl2nhdeeAEzZ87EiBEjsGbNGvz000/SfadOnUJiYiIaNWok3UaOHCl9BYNc4q5XF86dO4eSkhKEhISYzL9161aTGKqyZlxWVhYGDx5cpzN5OTk5CAoKMjlL8uijj+LGjRv4z3/+I7X17NnTZJyfnx+KiooAAE8//TRu376Ndu3a4bnnnsPevXurvTRU32S9hLRw4UKMHj0aAQEBuH79Onbu3InU1FR89tlnAO68rJOfny+9Bjdr1iy8+eabiImJwXPPPYeMjAxs2bIFO3bskOaMiopCcHAw1q5di/Hjx2P//v04fPgwjh49asdlEnDnA7fc3Gr/TItmzZQfw/2wVnPu17jkaAhrsNaDtFazVqwAliwBli8HFi/+v23gznY98fT0xP/8z/+YtF28eBFjxozBrFmzsGLFCnh7e+Po0aOYMWOGxYtAFyxYgIiICBw8eBAHDx7E0qVLsXPnTjz55JMwGo14/vnnMXfu3GrjWtnwoT6VLwU1bdoUP//8MwDg008/xUMPPWTST6Ox/OJb5YWvNY1zd3eXHVtVwsxlGncXYJWqFkkqlUqKMSAgAOfPn0dKSgoOHz6MF154AW3btsX+/fvrHJ+1ZBUwv/76K8LCwlBQUACdToeePXvis88+Q0hICACgoKAAeXl5Uv+2bdsiOTkZ0dHR2LRpE/z9/bFx40b86U9/kvoMHDgQO3fuxKJFi7B48WK0b98eu3btQv/+/e20RKrUqtWdD9y6l58qai6G8nIDjh79GoMGPQoXF7VdYrgf1mrO/RqXHA1hDdZ6kNZaTdXiBfi/fx1QxFR18uRJlJeXY926ddLH0n/00Ue1juvYsSM6d+6M6OhoPPPMM0hISMCTTz6J3r174+zZs9UKJVsUFRVh+/btmDBhApycnNC1a1doNBrk5eVhyJAhZsdUfitzRUWF1GbNuJ49e+L999+X3slrbt675zSna9euSEpKMilkjh07Bi8vr2qFU03c3d3xxBNP4IknnkBkZCQ6d+6Mc+fOYfDgwVbPUReyCpgtW7bUeH9iYmK1tiFDhuD06dM1jps4cSImTpwoJxSyUatW9/6XbdUYDAagoKAYgYGAPa9vvB/Was79GpccDWEN1nqQ1mqiosK0eKlUuV3Lk6S9tW/fHuXl5XjjjTcwbtw4fP3113j77bct9r99+zZefvllPPPMM2jfvj3+85//4Ntvv5X+gJ4/fz4GDBiAyMhIPPfcc/D09EROTg5SUlLwxhtvWJxXCIHCwkLpbdQZGRlYtWoVdDod1qxZA+DORawvvfQSoqOjYTQaMWjQIOj1ehw7dgyNGjVCeHg4WrduDZVKhU8++QRjxoyBu7u7VeNmz56NN954A1OmTEFsbCx0Oh2OHz+ORx55BJ06dUKbNm3w+eef4/z582jatCl0Ol21NbzwwguIj4/HnDlzMHv2bJw/fx5Lly5FTEyM1d9ZlJiYiIqKCvTv3x8eHh744IMP4O7ujoCAAKvG24WsK2buY7yIV7mYc8divh1P8RfxOpC5i1Arvf7668LPz0+4u7uLkSNHiq1bt5pcCHv3Rba3b98WTz31lAgICBCurq7C399fzJ492yQf33zzjQgJCRGNGjUSnp6eomfPnmLlypUWY0tISBAABAChUqmETqcTjzzyiFi+fHm15x6j0Sg2bNggOnXqJNRqtWjevLkYOXKkSEtLk/osX75c+Pr6CpVKJcLDw60el52dLUJDQ4WHh4fw8vISgwcPFj/99JMQQoiioiJpTQDEkSNHql3EK4QQqampol+/fsLV1VX4+vqK+fPnC4PBIN0/ZMgQERUVZbKm8ePHS3Hu3btX9O/fX2i1WuHp6SkGDBggDh065NCLeFVC/PeFL4XT6/XQ6XQoLi6u89uok5OTMWbMmAb3Nur7FXPuWMy3492LnJeUlCA3Nxdt27a1/W3UCmY0GqHX66HVavmN3A5SU85rejza+vzNo0pERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxWMAQERGR4rCAISIiIsVhAUNERNRAJCYmonHjxvc6DIdgAUNERPcFlUpV4y0iIsJhsUREREj7VavVaNGiBUJCQvDee+9J38hsrWXLluHhhx+2e4xt2rRBfHy8SdvkyZPxww8/2H1f9yMWMEREVKOTl0/isfcfw8nLJ+t1PwUFBdItPj4eWq3WpG3Dhg0m/Q0GQ73GM2rUKBQUFOCXX37BwYMHMWzYMERFRWHs2LEoLy+v133byt3dHT4+Pvc6DIdgAUNERDXamr0VR345gg+yP6jX/fj6+ko3nU4HlUolbZeUlKBx48b46KOPMHToULi5uWHbtm1mz27Ex8ejXbt2Jm0JCQno0qUL3Nzc0LlzZ7z11lu1xqPRaODr64uHHnoIvXv3xsKFC7F//34cPHgQiYmJUr/i4mLMnDkTPj4+0Gq1eOyxx5CdnQ3gzks6cXFxyM7Ols7oVI6taVylAwcOoG/fvnBzc0OzZs3w1FNPAQCGDh2KixcvIjo6Wpq3cn9VX0LavHkz2rdvD1dXV3Tq1AkffGB6HFUqFf7f//t/ePLJJ+Hh4YEOHTrgwIED0v1Xr17F1KlT0bx5c7i7u6NDhw5ISEioNX/1jQUMERFVc/HaRZy6fAqnC05j19ldAICdZ3fidMFpnLp8ChevXbwncc2fPx9z585FTk4ORo4cadWYd999F6+88gpWrlyJnJwcrFq1CosXL8b7778ve/+PPfYYevXqhT179gAAhBB4/PHHUVhYiOTkZJw6dQq9e/fG8OHD8ccff2Dy5Mn4+9//jm7duklnkiZPnlzrOAD49NNP8dRTT+Hxxx9HZmYmvvjiC/Tt2xcAsGfPHrRs2RLLly+X5jVn7969iIqKwt///nf8+9//xvPPP4/p06fjyJEjJv3i4uIwadIkfPfddxgzZgymTp0qxbF48WKcO3cOBw8eRE5ODjZv3oxmzZrJzp29udzrAIiI6P7TZkMb6f9VuPPX/W83f0Off/aR2sVS4eiw8OKLL0pnIay1YsUKrFu3ThrXtm1bnDt3Du+88w7Cw8Nlx9C5c2d89913AIAjR47gzJkzKCoqgkajAQC89tpr2LdvH/71r39h5syZaNSoEVxcXODr6yvN8eWXX9Y6buXKlZgyZQri4uKkcb169QIAeHt7w9nZGV5eXibzVvXaa68hIiICL7zwAgAgJiYGx48fx2uvvYZhw4ZJ/SIiIvDMM88AAFatWoU33ngD33zzDUaNGoW8vDwEBgZKxVObNm1k56w+8AwMERFVs+3JbXBxuvM3roAw+dfFyQXbntx2T+KqfBK11m+//YZLly5hxowZaNSokXR79dVX8dNPP9kUgxBCesnm1KlTuHHjBpo2bWoyf25ubo3zWzMuKysLw4cPtynGSjk5OXj00UdN2h599FHk5OSYtPXs2VP6f09PT3h5eaGoqAgA8Le//Q07d+7Eww8/jHnz5uHYsWN1isleeAaGiIiqmdpzKro072JyxqXSib+eQG+/3vcgqjtPrndzcnKCEKZngu6+uLfyHUPvvvsu+vfvb9LP2dnZphhycnLQtm1baX4/Pz+kpqZW61fT25mtGefu7m5TfFVVFluV7i7AKqnV6mpjKnM3evRoXLx4EZ9++ikOHz6M4cOHIzIyEq+99ppd4rMVCxgiIqqRE5xghFH6937SvHlzFBYWmjwpZ2VlSfe3aNECDz30EH7++WdMnTq1zvurfOknOjoaANC7d28UFhbCxcXF4ksrrq6uqKioMGmzZlzPnj3xxRdfYPr06VbPW1WXLl1w9OhRTJs2TWo7duwYunTpUuO4qpo3b46IiAhERERg8ODBePnll1nAEBHR/cnH0we+jXwRoA3AjMAZ2JK5BZf0l+Djef+8TXfo0KH47bff8L//+7+YOHEiPvvsMxw8eBBarVbqs2zZMsydOxdarRajR49GaWkpTp48iatXryImJsbi3KWlpSgsLERFRQV+/fVXfPbZZ1i9ejXGjh0rFQQjRoxAUFAQJkyYgLVr16JTp064fPkykpOTMWHCBPTt2xdt2rRBbm4usrKy0LJlS3h5eVk1bunSpRg+fDjat2+PKVOmoLy8HAcPHsS8efMA3LkWJT09HVOmTIFGozF7Ye3LL7+MSZMmSRcIf/zxx9izZw8OHz5sdY6XLFmCPn36oFu3bigtLcUnn3wiuwCqF6KBKC4uFgBEcXFxneYpKysT+/btE2VlZXaKjGrDnDsW8+149yLnt2/fFufOnRO3b9+u0zwlhhJhNBqFEEIYjUZRYiixR3i1SkhIEDqdTtrOzc0VAERmZma1vps3bxYBAQHC09NTTJs2TaxcuVK0bt1aXL16VVRUVAghhPjwww/Fww8/LFxdXUWTJk1EcHCw2LNnj8X9h4eHCwACgHBxcRHNmzcXI0aMEO+99540ZyW9Xi/mzJkj/P39hVqtFgEBAWLq1KkiLy9PCCFESUmJ+NOf/iQaN24sAIiEhASrxgkhRFJSkhR3s2bNxFNPPSXdl5GRIXr27Ck0Go2ofDqvmjchhHjrrbdEu3bthFqtFh07dhRbt241uR+A2Lt3r0mbTqeT4lyxYoXo0qWLcHd3F97e3mL8+PHi559/rpaziooKk5zfrabHo63P36r/Bq94er0eOp0OxcXFJpW3XAaDAcnJyRgzZky11wSpfjDnjsV8O969yHlJSQlyc3PRtm1buLm5OWSf9xOj0Qi9Xg+tVgsnJ75fxRFqynlNj0dbn795VImIiEhxWMAQERGR4rCAISIiIsVhAUNERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxZBUwq1evRr9+/eDl5QUfHx9MmDAB58+fr3FMREQEVCpVtVu3bt2kPomJiWb7lJSU2LYqIiJ64CQmJtb4DdD3i6FDh+LFF1+s132kpqZCpVLh2rVr9bqfe0lWAZOWlobIyEgcP34cKSkpKC8vR2hoKG7evGlxzIYNG1BQUCDdLl26BG9vbzz99NMm/bRarUm/goKCB/Ljr4mI7gd5ecDp05ZveXn1s19Lf/ReuHChfnYoQ9U/tlu0aIFx48bh7NmzsubZs2cPVqxYYbe4zBVEAwcOREFBAXQ6nd32c7+R9W3Un332mcl2QkICfHx8cOrUKQQHB5sdo9PpTBK4b98+XL16tdrXg6tUKvj6+soJh4iI6kFeHtCpE1DTSXA3N+D8eaBVK/vvf9SoUUhISDBpa968uf13ZAOtVovz589DCIH8/HzMmzcPjz/+OH744Qe4urpaNYe3t3c9Rwm4uro2+OfUOl0DU1xcDEDewdiyZQtGjBiB1q1bm7TfuHEDrVu3RsuWLTF27FhkZmbWOE9paSn0er3JDbjzpWl1vdlrHt6Y8/v1xnw/GDkXQsBoNMq+FRUZayxegDvFTVGR/Llruwkh4OrqCh8fH5ObSqXCunXr0KNHD3h6eiIgIAB/+9vfoNfrTcYDkOY5c+YMHnvsMXh5eUGr1aJPnz745ptvpL5Hjx5FcHAw3N3dERAQgDlz5uD69es1xqdSqeDj44MWLVqgd+/eiIqKwsWLF5GTk2P1vEOHDkVUVJS0XVJSgpdffhkPPfQQPD090b9/f3z55Zcm+/3qq68wZMgQeHh4oEmTJggNDcXvv/+O8PBwpKWlYcOGDdKZoZ9//hlffvklVCoV/vjjD2mO3bt3o1u3btBoNGjTpg1ee+01k320adMGK1euxPTp0+Hl5YVWrVrh7bffNokzMjISfn5+cHNzQ5s2bbBq1SqTYwfA4uNOCFHjz4dcss7A3E0IgZiYGAwaNAjdu3e3akxBQQEOHjyI7du3m7R37twZiYmJ6NGjB/R6PTZs2IBHH30U2dnZ6NChg9m5Vq9ejbi4uGrthw4dgoeHh/wFVZGSklLnOUge5tyxmG/Hc2TOXVxc4Ovrixs3bqCsrEzW2Js3nQF4WdHvJvT6ChsjNM9gMKC8vFz6o/RuZWVlWLVqFVq1aoWLFy/ipZdeQnR0NNatWwfgzjceCyGksTNnzkTPnj3xxRdfwNnZGWfOnJH++D179ixGjx6NhQsXYv369bhy5QrmzZuHWbNmYdOmTWZjqzp/cXExtm7dCgCy5i0vL0dZWZk0z3PPPYe8vDy8++678PPzwyeffIIxY8bg66+/Rvv27XHmzBmEhIRg6tSpePXVV+Hi4oKvvvoK165dw/Lly5GTk4OuXbsiNjYWwJ1XPm7dugUAuH79OpycnJCVlYUpU6ZgwYIFePLJJ/HNN9/gpZdegoeHB5599lkAdwq/devWYeHChZgzZw7279+PyMhI9O7dGx07dsQbb7yB/fv3Y8uWLWjZsiXy8/ORn59f7Vhdv37d7LG7ffs20tPTUV5ebnJfZaxyqURlySRTZGQkPv30Uxw9ehQtW7a0aszq1auxbt06XL58ucZTbUajEb1790ZwcDA2btxotk9paSlKS0ulbb1ej4CAAFy5ckXW13FXZTAYkJKSgpCQEId97f2Djjl3LObb8e5FzktKSnDp0iW0adNG9vWEp08D/frVfoL+22+N6N3b1gjNmz59Oj788EOTmEeNGoWPPvqoWt/du3cjMjISRUVFAO5coxITE4M//vgDQgg0adIEGzZsQHh4eLWx4eHhcHd3x9tvvy21HT16FMOGDcP169fN5iwxMREzZsyAp6cnhBDSE++4ceOwb98+q+d97LHH0KtXL6xfvx4//fQTOnXqhLy8PPj7+0tjQkND0a9fP6xcuRJTp07FpUuXkJ6ebjZnd89XKTU1FcOHD8fvv/+Oxo0b489//jN+++03fP7551Kf+fPnIzk5GWfOnAEAtGvXDoMGDZKKMiEE/P39sXTpUsyaNQtRUVE4d+4cDh06BJVKVS0OIQSuX78OLy+vaveXlJTgl19+QUBAQLXc6vV6NGvWDMXFxbKev206AzNnzhwcOHAA6enpVhcvQgi89957CAsLq/V1QicnJ/Tr1w8//vijxT4ajQYajaZau1qttssvCHvNQ9Zjzh2L+XY8R+a8oqICKpUKTk5OcHKSd7WAtd3vzG1DcDVQqVQYNmwYNm/eLLV5enrCyckJR44cwapVq3Du3Dno9XqUl5ejpKQEt2/flvpUxmU0GvHCCy9g5syZ+PDDDzFixAg8/fTTaN++PQDg9OnTuHDhgskrApUvfVy8eBFdunQxu14vLy+cPn0a5eXlSEtLwz/+8Q+888470r6tnbfy2GRlZUEIgc6dO5vsq7S0FE2bNoWTkxOys7Px9NNP13gcK+e7O9bKf52cnPD9999j/PjxJn0GDRqEDRs2QAgBZ2dnAECvXr1M+vj6+uLKlStwcnLC9OnTERISgi5dumDUqFEYO3YsQkNDpb6VL+FVjaUyDpVKZfZnwNafCVkFjBACc+bMwd69e5Gamoq2bdtaPTYtLQ0XLlzAjBkzrNpPVlYWevToISc8IiJqADw9PfE///M/Jm0XL17EmDFjMGvWLKxYsQLe3t44evQoZsyYYfEaigULFiAiIgIHDx7EwYMHsXTpUuzcuRNPPvkkjEYjnn/+ecydO7fauFY1XJns5OQkxda5c2cUFhZi8uTJ0tkRufMajUY4Ozvj1KlTUhFRqVGjRgAAd3d3i/FYSwhR7ayIuRdgqhYTKpVKKkx69+6N3NxcHDx4EIcPH8akSZMwYsQI/Otf/6pzfLaQVcBERkZi+/bt2L9/P7y8vFBYWAjgzuttlQmOjY1Ffn6+dAqq0pYtW9C/f3+z18vExcVhwIAB6NChA/R6PTZu3IisrCyLr0MSEdGD5eTJkygvL8e6deukv+7NvaxUVceOHdG5c2dER0fjmWeeQUJCAp588kn07t0bZ8+erVYoyRUdHY3XX38de/futWnewMBAVFRUoKioCIMHDzbbp/I6HnPXfQJ33nFUUVHztUhdu3bF0aNHTdqOHTuGjh07ViucaqLVajF58mRMnjwZEydOxKhRo/DHH3845J1VVck6+bd582YUFxdj6NCh8PPzk267du2S+hQUFCCvygcEFBcXIykpyeLZl2vXrmHmzJno0qULQkNDkZ+fj/T0dDzyyCM2LImIiBqa9u3bo7y8HG+88QZ+/vlnfPDBBybXmVR1+/ZtvPzyy0hNTcXFixfx9ddf49tvv5Vewpk/fz4yMjIQGRmJrKws/Pjjjzhw4ADmzJkjKy6tVou//vWvWLp0KYQQsuft2LEjpk6dimnTpmHPnj3Izc3Ft99+i7Vr1yI5ORnAnRMD3377LV544QV89913+P7777F582ZcuXIFANCmTRucOHECv/zyC65cuSKdMbnb3//+d3zxxRdYsWIFfvjhB7z//vt488038dJLL1m91vXr12Pnzp34/vvv8cMPP2D37t3w9fW9Zx8eKKuAEUKYvUVEREh9EhMTkZqaajKu8oro5557zuy869evx8WLF1FaWoqioiJ8/vnnCAoKkr0YIiKqu2bN7nzOS03c3O70c5SHH34Yr7/+OtauXYvu3bvjww8/xOrVqy32d3Z2xh9//IGIiAh07NgRkyZNwujRo6WzGD179kRaWhp+/PFHDB48GIGBgVi8eDH8/PxkxxYVFYWcnBzs3r3bpnkTEhIwbdo0/P3vf0enTp3wxBNP4MSJEwgICABwp8g5dOgQsrOz8cgjjyAoKAj79++Hi8udF1FeeuklODs7o2vXrmjevHm1kwjAnZd/PvroI+zcuRPdu3fHkiVLsHz5cpPn79o0atQIa9euRd++fdGvXz/88ssvSE5Oln2Nlb3Y/C6k+41er4dOp5N9FXNVBoMBycnJGDNmDC9wdBDm3LGYb8e7FzkvKSlBbm4u2rZta9OnmuflAf/9A9+sZs3q50Ps7MVoNEKv10Or1d6zJ1hLgoKCMHz4cLz66qv3OhS7qinnNT0ebX3+tvlzYIiIqOFq1er+LlCUqLS0FGfOnMHZs2fNXuRL8txfZSkREVEDdfDgQTz22GMYN24cJk6ceK/DUTyegSEiInKACRMmmP2EYbINz8AQERGR4rCAISIiIsVhAUNE1IA1kDeaksLVx+OQBQwRUQNU+XZtW7/pl8ieKh+H9vwYAV7ES0TUADk7O6Nx48bSNzV7eHiY/QbhhspoNKKsrAwlJSX33efANFTmcl75rd1FRUVo3LixrK8tqA0LGCKiBsrX1xcApCLmQSKEwO3bt+Hu7v5AFW73Uk05b9y4sfR4tBcWMEREDZRKpYKfnx98fHwsfmNzQ2UwGJCeno7g4GB+4rSDWMq5Wq2265mXSixgiIgaOGdn53p5ArmfOTs7o7y8HG5ubixgHMTROecLg0RERKQ4LGCIiIhIcVjAEBERkeKwgCEiIiLFYQFDREREisMChoiIiBSHBQwREREpDgsYIiIiUhwWMERERKQ4LGCIiIhIcVjAEBERkeKwgCEiIiLFYQFDREREisMChoiIiBSHBQwREREpDgsYIiIiUhwWMERERKQ4LGCIiIhIcVjAEBERkeLIKmBWr16Nfv36wcvLCz4+PpgwYQLOnz9f45jU1FSoVKpqt++//96kX1JSErp27QqNRoOuXbti79698ldDREREDwRZBUxaWhoiIyNx/PhxpKSkoLy8HKGhobh582atY8+fP4+CggLp1qFDB+m+jIwMTJ48GWFhYcjOzkZYWBgmTZqEEydOyF8RERERNXgucjp/9tlnJtsJCQnw8fHBqVOnEBwcXONYHx8fNG7c2Ox98fHxCAkJQWxsLAAgNjYWaWlpiI+Px44dO+SESERERA8AWQVMVcXFxQAAb2/vWvsGBgaipKQEXbt2xaJFizBs2DDpvoyMDERHR5v0HzlyJOLj4y3OV1paitLSUmlbr9cDAAwGAwwGg5xlmKgcW5c5SB7m3LGYb8djzh2POXc8W3Nu6zFSCSGELQOFEBg/fjyuXr2Kr776ymK/8+fPIz09HX369EFpaSk++OADvP3220hNTZXO2ri6uiIxMRHPPvusNG779u2YPn26SZFyt2XLliEuLq5a+/bt2+Hh4WHLkoiIiMjBbt26hWeffRbFxcXQarVWj7P5DMzs2bPx3Xff4ejRozX269SpEzp16iRtBwUF4dKlS3jttddMXnZSqVQm44QQ1druFhsbi5iYGGlbr9cjICAAoaGhshJQlcFgQEpKCkJCQqBWq22eh6zHnDsW8+14zLnjMeeOZ2vOK19BkcumAmbOnDk4cOAA0tPT0bJlS9njBwwYgG3btknbvr6+KCwsNOlTVFSEFi1aWJxDo9FAo9FUa1er1XZ5sNprHrIec+5YzLfjMeeOx5w7ntyc23p8ZL0LSQiB2bNnY8+ePfjyyy/Rtm1bm3aamZkJPz8/aTsoKAgpKSkmfQ4dOoSBAwfaND8RERE1bLLOwERGRmL79u3Yv38/vLy8pLMmOp0O7u7uAO68tJOfn4+tW7cCuPMOozZt2qBbt24oKyvDtm3bkJSUhKSkJGneqKgoBAcHY+3atRg/fjz279+Pw4cP1/ryFBERET2YZBUwmzdvBgAMHTrUpD0hIQEREREAgIKCAuTl5Un3lZWV4aWXXkJ+fj7c3d3RrVs3fPrppxgzZozUZ+DAgdi5cycWLVqExYsXo3379ti1axf69+9v47KIiIioIZNVwFjzhqXExEST7Xnz5mHevHm1jps4cSImTpwoJxwiIiJ6QPG7kIiIiEhxWMAQERGR4rCAISIiIsVhAUNERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxWMAQERGR4rCAISIiIsVhAUNERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxWMAQERGR4rCAISIiIsVhAUNERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxWMAQERGR4rCAISIiIsVhAUNERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHFkFzOrVq9GvXz94eXnBx8cHEyZMwPnz52scs2fPHoSEhKB58+bQarUICgrC559/btInMTERKpWq2q2kpET+ioiIiKjBk1XApKWlITIyEsePH0dKSgrKy8sRGhqKmzdvWhyTnp6OkJAQJCcn49SpUxg2bBjGjRuHzMxMk35arRYFBQUmNzc3N9tWRURERA2ai5zOn332mcl2QkICfHx8cOrUKQQHB5sdEx8fb7K9atUq7N+/Hx9//DECAwOldpVKBV9fXznhEBER0QNKVgFTVXFxMQDA29vb6jFGoxHXr1+vNubGjRto3bo1Kioq8PDDD2PFihUmBU5VpaWlKC0tlbb1ej0AwGAwwGAwyFmGicqxdZmD5GHOHYv5djzm3PGYc8ezNee2HiOVEELYMlAIgfHjx+Pq1av46quvrB73j3/8A2vWrEFOTg58fHwAAMePH8eFCxfQo0cP6PV6bNiwAcnJycjOzkaHDh3MzrNs2TLExcVVa9++fTs8PDxsWRIRERE52K1bt/Dss8+iuLgYWq3W6nE2FzCRkZH49NNPcfToUbRs2dKqMTt27MBf//pX7N+/HyNGjLDYz2g0onfv3ggODsbGjRvN9jF3BiYgIABXrlyRlYCqDAYDUlJSEBISArVabfM8ZD3m3LGYb8djzh2POXc8W3Ou1+vRrFkz2QWMTS8hzZkzBwcOHEB6errVxcuuXbswY8YM7N69u8biBQCcnJzQr18//Pjjjxb7aDQaaDSaau1qtdouD1Z7zUPWY84di/l2PObc8Zhzx5Obc1uPj6x3IQkhMHv2bOzZswdffvkl2rZta9W4HTt2ICIiAtu3b8fjjz9u1X6ysrLg5+cnJzwiIiJ6QMg6AxMZGYnt27dj//798PLyQmFhIQBAp9PB3d0dABAbG4v8/Hxs3boVwJ3iZdq0adiwYQMGDBggjXF3d4dOpwMAxMXFYcCAAejQoQP0ej02btyIrKwsbNq0yW4LJSIiooZD1hmYzZs3o7i4GEOHDoWfn59027Vrl9SnoKAAeXl50vY777yD8vJyREZGmoyJioqS+ly7dg0zZ85Ely5dEBoaivz8fKSnp+ORRx6xwxKJiIiooZF1Bsaa630TExNNtlNTU2sds379eqxfv15OKERERPQA43chERERkeKwgCEiIiLFYQFDREREisMChoiIiBSHBQwREREpDgsYIiIiUhwWMERERKQ4LGCIiIhIcVjAEBERkeKwgCEiIiLFYQFDREREisMChoiIiBSHBQwREREpDgsYIiIiUhwWMERERKQ4LGCIiIhIcVjAEBERkeKwgCEiIiLFYQFDREREisMChoiIiBSHBQwREREpDgsYIiIiUhwWMERERKQ4LGCIiIhIcVjAEBERkeKwgCEiIiLFYQFDREREisMChoiIiBSHBQwREREpDgsYIiIiUhwWMERERKQ4sgqY1atXo1+/fvDy8oKPjw8mTJiA8+fP1zouLS0Nffr0gZubG9q1a4e33367Wp+kpCR07doVGo0GXbt2xd69e+WEVm9OXj6Jx95/DCcvnzT5/5r61dQmZ59bs7eaHV91Xkv7sXb/tcVe2zzW7F/OfHWNvTaW8mvNMbQ293Jjk3sMrcmnpVi3ndmGxRcW41TBqTodI1vZsqa6xGZrDuszB0RUd7IKmLS0NERGRuL48eNISUlBeXk5QkNDcfPmTYtjcnNzMWbMGAwePBiZmZlYuHAh5s6di6SkJKlPRkYGJk+ejLCwMGRnZyMsLAyTJk3CiRMnbF+ZnWzN3oojvxzBB9kfmPx/Tf1qapOzz9czXjc7vuq8lvZj7f5ri722eazZv5z56hp7bSzl15pjaG3u5cYm9xhak09LscafiMeZG2fw4ZkP63SMbGXLmuoSm605rM8cEFHdqYQQwtbBv/32G3x8fJCWlobg4GCzfebPn48DBw4gJydHaps1axays7ORkZEBAJg8eTL0ej0OHjwo9Rk1ahSaNGmCHTt2WBWLXq+HTqdDcXExtFqtrUuCwWBA4r5E9OzfE2q1GqEfhOL327+jiVsTAMDVkqto6t4Uh8IO4bL+MgDAX+uP0R+ORtHNIjR1b4oNozYAAKI+i8Lvt3+Hj6cPDk49CCEEmnk0Q+vGravt9+K1i7hy6woKbxQibG8YrpZchQoqCAg0cWuCdaHroHZSo4l7E/zlwF9QdLMITdya4I0xb2BO8hxcLbkKH08fvPfEe7h6+6pJP3P7r9yfSqUyG/vs5Nm4VnrN7LqFECgpL4Gbi5vJ+Kr7D98XLuWuQlRAX6qHTqODk8rJZD6DwYDvTnyHYcOGobisuNqc1sReW45ryq+XqxdWDFuBuLQ4Ka6qx7Bqrs3l/uDUg2YfE5Zis7QOS8fQUm7vPj7vT3i/2tgmbk2wdOhSLP5yMa6XXZdy4uXqBQC4XnYdOo0OAsLiMarpsWsNa9Zqbk06jQ6bHt+EFz59AfpSvcXHY9XYbN1fY01jvDnmTdk/v7UxGAxITk7GmDFjoFarbcohycOcO56tObf1+btOBcyFCxfQoUMHnDlzBt27dzfbJzg4GIGBgdiwYYPUtnfvXkyaNAm3bt2CWq1Gq1atEB0djejoaKnP+vXrER8fj4sXL5qdt7S0FKWlpdK2Xq9HQEAArly5UucCxvMfnrLHVT4ZWnNf2cKyan1cV7nWeV9V2yu3ze3/7v3VFLuceOo6jzVzWoq9thzLyW9d4jXXZik2a9ZRl9za83hUMvfYtYY1a62ru2Oz5/6s+fmtjcFgQEpKCkJCQvhk6iDMuePZmnO9Xo9mzZo5roARQmD8+PG4evUqvvrqK4v9OnbsiIiICCxcuFBqO3bsGB599FFcvnwZfn5+cHV1RWJiIp599lmpz/bt2zF9+nSTIuVuy5YtQ1xcXLX27du3w8PDw5YlSdL+SMPGvI2oQEWN/VT//c8Io1XzOsMZc1vNxRDvITbvsy7u3n9d9ucMZ4Q0DUHK7yl2ibcyLgAWY7I2dks5dkR+gZofE1Vjc1RM9lDTY9ca9blWc7HVx/7qmgMiMu/WrVt49tlnZRcwLrbucPbs2fjuu+9w9OjRWvuqVCqT7cqa6e52c32qtt0tNjYWMTEx0nblGZjQ0NA6n4FBCvCnoX/CoK2Daux7/C/HAQD93+tv1dzH/nIMgb6BZu8bgzGYUjilxrnef+J9hB8Ir3U/lvrdvX9r9mdJ5TyZhZlmx1sbZ6W0aWm48t0VhISEYMrv5mOyNnZLOa7LeuWo6TFRNbaaYrKUQ2tyKzf/1qjpsWsNW9Zal9jqY391yQHPBjgec+54dTkDYwubCpg5c+bgwIEDSE9PR8uWLWvs6+vri8LCQpO2oqIiuLi4oGnTpjX2adGihcV5NRoNNBpNtXa1Wm2XB6va5c4cTnCq9td0ZZuLi0u1trv7V21zcXGpMbbK+Sy9jODs4mwyb9VT45XtVftZ2n/l/mqK3dK61Wq1xfFV929J5f2Vua5pTmtjrynHlvJbNc/m8lA115ZyX9Njwlxs1ubQmtxa6lOXl2qsfexaw5bHS00v/9QWmy37q8vPrzXs9fuJrMecO57cnNt6fGS9C0kIgdmzZ2PPnj348ssv0bZt21rHBAUFISUlxaTt0KFD6Nu3rxS0pT4DBw6UE55dNfdoDt9Gvujj3werH1sNtZMaLk4uWD18Nfr494FvI1/4ePrAx9NH6vf242+jj38fNPdojuYezU3aKvvXpHKuni16QqvRwkPtAa1Gi54tesK3kS86enc02VfPFj3hpHJCzxY9TfZTtZ+l/dcWe03rtjS+6v7vnmPBowvMztfco3mNMVkbe205tpTfLs26VMtj1WNYNdeWcm/pMWEpNmtyaE1u786npcdJl2ZdpHW7qdzgonKpdlwsHaPaHrvWkPt4WT18tUmea3s82mN/dfn5JSIHEzL87W9/EzqdTqSmpoqCggLpduvWLanPggULRFhYmLT9888/Cw8PDxEdHS3OnTsntmzZItRqtfjXv/4l9fn666+Fs7OzWLNmjcjJyRFr1qwRLi4u4vjx41bHVlxcLACI4uJiOUuqpqysTOzbt0+UlZWJEkOJMBqNQgghbpfdFrfLbgshhDAajaLEUCKNubtf5X3m2qxROa7EUCIqKipMts3tq/h2sdn9WLv/2mKvad017cfSHObmuzvndY3d1vyay2NtubaUe7mxWZNDa3JrzeOkxFAiSkpKxO49u4X+pt7scantmNeFLWu6O89yY7M1h7b+/FpS9TFO9Y85dzxbc27r87esl5A2b94MABg6dKhJe0JCAiIiIgAABQUFyMvLk+5r27YtkpOTER0djU2bNsHf3x8bN27En/70J6nPwIEDsXPnTixatAiLFy9G+/btsWvXLvTvX7/XK9RG4/J/L1G5qd2k/1epVCb33f3/Ve+z1FbbPqV/nTRm2yvn1bppTbYt9bO0/9r61bTumsZbyp25+QwGg6yY5PYzN6Zqfi3l8e62qn1qGiMnNmtyaE1uaxpbGavGRQODMEDtpIab2k06C1rbMbIXW9Z0d57lxlaXHMrZDxE5nqwCRljxhqXExMRqbUOGDMHp06drHDdx4kRMnDhRTjhERET0gOJ3IREREZHisIAhIiIixWEBQ0RERIrDAoaIiIgUhwUMERERKQ4LGCIiIlIcFjBERESkOCxgiIiISHFYwBAREZHisIAhIiIixWEBQ0RERIrDAoaIiIgUhwUMERERKQ4LGCIiIlIcFjBERESkOCxgiIiISHFYwBAREZHisIAhIiIixWEBQ0RERIrDAoaIiIgUhwUMERERKQ4LGCIiIlIcFjBERESkOCxgiIiISHFYwBAREZHisIAhIiIixWEBQ0RERIrDAoaIiIgUhwUMERERKQ4LGCIiIlIcFjBERESkOLILmPT0dIwbNw7+/v5QqVTYt29fjf0jIiKgUqmq3bp16yb1SUxMNNunpKRE9oKIiIio4ZNdwNy8eRO9evXCm2++aVX/DRs2oKCgQLpdunQJ3t7eePrpp036abVak34FBQVwc3OTGx4RERE9AFzkDhg9ejRGjx5tdX+dTgedTidt79u3D1evXsX06dNN+qlUKvj6+soNh4iIiB5AsguYutqyZQtGjBiB1q1bm7TfuHEDrVu3RkVFBR5++GGsWLECgYGBFucpLS1FaWmptK3X6wEABoMBBoPB5vgqx9ZlDpKHOXcs5tvxmHPHY84dz9ac23qMVEIIYdNI3DlrsnfvXkyYMMGq/gUFBQgICMD27dsxadIkqf348eO4cOECevToAb1ejw0bNiA5ORnZ2dno0KGD2bmWLVuGuLi4au3bt2+Hh4eHTeshIiIix7p16xaeffZZFBcXQ6vVWj3OoQXM6tWrsW7dOly+fBmurq4W+xmNRvTu3RvBwcHYuHGj2T7mzsAEBATgypUrshJQlcFgQEpKCkJCQqBWq22eh6zHnDsW8+14zLnjMeeOZ2vO9Xo9mjVrJruAcdhLSEIIvPfeewgLC6uxeAEAJycn9OvXDz/++KPFPhqNBhqNplq7Wq22y4PVXvOQ9Zhzx2K+HY85dzzm3PHk5tzW4+Owz4FJS0vDhQsXMGPGjFr7CiGQlZUFPz8/B0RGRERESiP7DMyNGzdw4cIFaTs3NxdZWVnw9vZGq1atEBsbi/z8fGzdutVk3JYtW9C/f39079692pxxcXEYMGAAOnToAL1ej40bNyIrKwubNm2yYUlERETU0MkuYE6ePIlhw4ZJ2zExMQCA8PBwJCYmoqCgAHl5eSZjiouLkZSUhA0bNpid89q1a5g5cyYKCwuh0+kQGBiI9PR0PPLII3LDIyIiogeA7AJm6NChqOm638TExGptOp0Ot27dsjhm/fr1WL9+vdxQiIiI6AHF70IiIiIixWEBQ0RERIrDAoaIiIgUhwUMERERKQ4LGCIiIlIcFjBERESkOCxgiIiISHFYwBAREZHisIAhIiIixWEBQ0RERIrDAoaIiIgUhwUMERERKQ4LGCIiIlIcFjBERESkOCxgiIiISHFYwBAREZHisIAhIiIixWEBQ0RERIrDAoaIiIgUhwUMERERKQ4LGCIiIlIcFjBERESkOCxgiIiISHFYwBAREZHisIAhIiIixWEBQ0RERIrDAoaIiIgUhwUMERERKQ4LGCIiIlIcFjBERESkOCxgiIiISHFkFzDp6ekYN24c/P39oVKpsG/fvhr7p6amQqVSVbt9//33Jv2SkpLQtWtXaDQadO3aFXv37pUbGhERET0gZBcwN2/eRK9evfDmm2/KGnf+/HkUFBRItw4dOkj3ZWRkYPLkyQgLC0N2djbCwsIwadIknDhxQm54RERE9ABwkTtg9OjRGD16tOwd+fj4oHHjxmbvi4+PR0hICGJjYwEAsbGxSEtLQ3x8PHbs2CF7X0RERNSwyS5gbBUYGIiSkhJ07doVixYtwrBhw6T7MjIyEB0dbdJ/5MiRiI+PtzhfaWkpSktLpW29Xg8AMBgMMBgMNsdZObYuc5A8zLljMd+Ox5w7HnPueLbm3NZjVO8FjJ+fH/75z3+iT58+KC0txQcffIDhw4cjNTUVwcHBAIDCwkK0aNHCZFyLFi1QWFhocd7Vq1cjLi6uWvuhQ4fg4eFR57hTUlLqPAfJw5w7FvPteMy54zHnjic357du3bJpP/VewHTq1AmdOnWStoOCgnDp0iW89tprUgEDACqVymScEKJa291iY2MRExMjbev1egQEBCA0NBRardbmeA0GA1JSUhASEgK1Wm3zPGQ95tyxmG/HY84djzl3PFtzXvkKilwOewnpbgMGDMC2bdukbV9f32pnW4qKiqqdlbmbRqOBRqOp1q5Wq+3yYLXXPGQ95tyxmG/HY84djzl3PLk5t/X43JPPgcnMzISfn5+0HRQUVO2U06FDhzBw4EBHh0ZEREQKIPsMzI0bN3DhwgVpOzc3F1lZWfD29karVq0QGxuL/Px8bN26FcCddxi1adMG3bp1Q1lZGbZt24akpCQkJSVJc0RFRSE4OBhr167F+PHjsX//fhw+fBhHjx61wxKJiIiooZFdwJw8edLkHUSV16GEh4cjMTERBQUFyMvLk+4vKyvDSy+9hPz8fLi7u6Nbt2749NNPMWbMGKnPwIEDsXPnTixatAiLFy9G+/btsWvXLvTv378uayMiIqIGSnYBM3ToUAghLN6fmJhosj1v3jzMmzev1nknTpyIiRMnyg2HiIiIHkD8LiQiIiJSHBYwREREpDgsYIiIiEhxWMAQERGR4rCAISIiIsVhAUNERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxWMAQERGR4rCAISIiIsVhAUNERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxWMAQERGR4rCAISIiIsVhAUNERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxWMAQERGR4rCAISIiIsVhAUNERESKwwKGiIiIFEd2AZOeno5x48bB398fKpUK+/btq7H/nj17EBISgubNm0Or1SIoKAiff/65SZ/ExESoVKpqt5KSErnhERER0QNAdgFz8+ZN9OrVC2+++aZV/dPT0xESEoLk5GScOnUKw4YNw7hx45CZmWnST6vVoqCgwOTm5uYmNzwiIiJ6ALjIHTB69GiMHj3a6v7x8fEm26tWrcL+/fvx8ccfIzAwUGpXqVTw9fWVGw4RERE9gGQXMHVlNBpx/fp1eHt7m7TfuHEDrVu3RkVFBR5++GGsWLHCpMCpqrS0FKWlpdK2Xq8HABgMBhgMBpvjqxxblzlIHubcsZhvx2POHY85dzxbc27rMVIJIYRNI3HnrMnevXsxYcIEq8f84x//wJo1a5CTkwMfHx8AwPHjx3HhwgX06NEDer0eGzZsQHJyMrKzs9GhQwez8yxbtgxxcXHV2rdv3w4PDw+b1kNERESOdevWLTz77LMoLi6GVqu1epxDC5gdO3bgr3/9K/bv348RI0ZY7Gc0GtG7d28EBwdj48aNZvuYOwMTEBCAK1euyEpAVQaDASkpKQgJCYFarbZ5HrIec+5YzLfjMeeOx5w7nq051+v1aNasmewCxmEvIe3atQszZszA7t27ayxeAMDJyQn9+vXDjz/+aLGPRqOBRqOp1q5Wq+3yYLXXPGQ95tyxmG/HY84djzl3PLk5t/X4OORzYHbs2IGIiAhs374djz/+eK39hRDIysqCn5+fA6IjIiIipZF9BubGjRu4cOGCtJ2bm4usrCx4e3ujVatWiI2NRX5+PrZu3QrgTvEybdo0bNiwAQMGDEBhYSEAwN3dHTqdDgAQFxeHAQMGoEOHDtDr9di4cSOysrKwadMme6yRiIiIGhjZZ2BOnjyJwMBA6R1CMTExCAwMxJIlSwAABQUFyMvLk/q/8847KC8vR2RkJPz8/KRbVFSU1OfatWuYOXMmunTpgtDQUOTn5yM9PR2PPPJIXddHREREDZDsMzBDhw5FTdf9JiYmmmynpqbWOuf69euxfv16uaEQERHRA4rfhURERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxWMAQERGR4rCAISIiIsVhAUNERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxWMAQERGR4rCAISIiIsVhAUNERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxWMAQERGR4rCAISIiIsVhAUNERESKwwKGiIiIFIcFDBERESkOCxgiIiJSHBYwREREpDgsYIiIiEhxWMAQERGR4sguYNLT0zFu3Dj4+/tDpVJh3759tY5JS0tDnz594Obmhnbt2uHtt9+u1icpKQldu3aFRqNB165dsXfvXrmhERHVn2XLgBUrzN+3YsWd+x8ED3oeHqT13+drlV3A3Lx5E7169cKbb75pVf/c3FyMGTMGgwcPRmZmJhYuXIi5c+ciKSlJ6pORkYHJkycjLCwM2dnZCAsLw6RJk3DixAm54RER1Q9nZ2DJkuq/0FesuNPu7Hxv4nK0Bz0PD9L67/e1ijoAIPbu3Vtjn3nz5onOnTubtD3//PNiwIAB0vakSZPEqFGjTPqMHDlSTJkyxepYiouLBQBRXFxs9RhzysrKxL59+0RZWVmd5iHrMeeOxXzXwfLlQgB3/jW3bUGDy7mNeXCkes25AtZvNzLWamvObX3+dqnvAikjIwOhoaEmbSNHjsSWLVtgMBigVquRkZGB6Ojoan3i4+MtzltaWorS0lJpW6/XAwAMBgMMBoPN8VaOrcscJA9z7ljMdx0sWACnigo4L1kC8eqrUJWVoWLpUhgXLABqyGeDy7mNeXCkes25AtZvNzLWamvObT1G9V7AFBYWokWLFiZtLVq0QHl5Oa5cuQI/Pz+LfQoLCy3Ou3r1asTFxVVrP3ToEDw8POocd0pKSp3nIHmYc8divm0UGIixLi5wLitDhYsLPgkMBJKTrRraoHJehzw4Ur3lXCHrtwuZa5Wb81u3btkUVr0XMACgUqlMtoUQ1drN9anadrfY2FjExMRI23q9HgEBAQgNDYVWq7U5VoPBgJSUFISEhECtVts8D1mPOXcs5rtunFauhHN5OYSrK5zLyjA2MxPGV16pcUxDzLkteXCk+s75/b5+e7J2rbbmvPIVFLnqvYDx9fWtdialqKgILi4uaNq0aY19qp6VuZtGo4FGo6nWrlar7fJgtdc8ZD3m3LGYbxusWAHExQHLl0O1eDGwYgWclyyBs7MzsHhxrcMbTM7rmAdHqpecK2j9dWbDWuXm3NbjU+8FTFBQED7++GOTtkOHDqFv375S0EFBQUhJSTG5DubQoUMYOHBgfYdHRGSdyndeLF/+f7+4K/9dssR0uyF70PPwIK3/Pl+r7ALmxo0buHDhgrSdm5uLrKwseHt7o1WrVoiNjUV+fj62bt0KAJg1axbefPNNxMTE4LnnnkNGRga2bNmCHTt2SHNERUUhODgYa9euxfjx47F//34cPnwYR48etcMSiYjsoKLC9Bd5pcrtigrHx3QvPOh5eJDWf7+vVdZ7loQQR44cEQCq3cLDw4UQQoSHh4shQ4aYjElNTRWBgYHC1dVVtGnTRmzevLnavLt37xadOnUSarVadO7cWSQlJcmKi2+jVi7m3LGYb8djzh2POXe8+/5t1EOHDpUuwjUnMTGxWtuQIUNw+vTpGuedOHEiJk6cKDccIiIiegDxu5CIiIhIcVjAEBERkeKwgCEiIiLFYQFDREREisMChoiIiBSHBQwREREpDgsYIiIiUhwWMERERKQ4LGCIiIhIcer9yxwdpfLTgW39Wu5KBoMBt27dgl6vbxjfGqsAzLljMd+Ox5w7HnPueLbmvPJ5u6ZP+TenwRQw169fBwAEBATc40iIiIhIruvXr0On01ndXyXkljz3KaPRiMuXL8PLywsqlcrmefR6PQICAnDp0iVotVo7RkiWMOeOxXw7HnPueMy549macyEErl+/Dn9/fzg5WX9lS4M5A+Pk5ISWLVvabT6tVssHvYMx547FfDsec+54zLnj2ZJzOWdeKvEiXiIiIlIcFjBERESkOCxgqtBoNFi6dCk0Gs29DuWBwZw7FvPteMy54zHnjufonDeYi3iJiIjowcEzMERERKQ4LGCIiIhIcVjAEBERkeKwgCEiIiLFYQFzl7feegtt27aFm5sb+vTpg6+++upeh6RIq1evRr9+/eDl5QUfHx9MmDAB58+fN+kjhMCyZcvg7+8Pd3d3DB06FGfPnjXpU1paijlz5qBZs2bw9PTEE088gf/85z+OXIpirV69GiqVCi+++KLUxpzbX35+Pv785z+jadOm8PDwwMMPP4xTp05J9zPn9lVeXo5Fixahbdu2cHd3R7t27bB8+XIYjUapD3NeN+np6Rg3bhz8/f2hUqmwb98+k/vtld+rV68iLCwMOp0OOp0OYWFhuHbtmrxgBQkhhNi5c6dQq9Xi3XffFefOnRNRUVHC09NTXLx48V6HpjgjR44UCQkJ4t///rfIysoSjz/+uGjVqpW4ceOG1GfNmjXCy8tLJCUliTNnzojJkycLPz8/odfrpT6zZs0SDz30kEhJSRGnT58Ww4YNE7169RLl5eX3YlmK8c0334g2bdqInj17iqioKKmdObevP/74Q7Ru3VpERESIEydOiNzcXHH48GFx4cIFqQ9zbl+vvvqqaNq0qfjkk09Ebm6u2L17t2jUqJGIj4+X+jDndZOcnCxeeeUVkZSUJACIvXv3mtxvr/yOGjVKdO/eXRw7dkwcO3ZMdO/eXYwdO1ZWrCxg/uuRRx4Rs2bNMmnr3LmzWLBgwT2KqOEoKioSAERaWpoQQgij0Sh8fX3FmjVrpD4lJSVCp9OJt99+WwghxLVr14RarRY7d+6U+uTn5wsnJyfx2WefOXYBCnL9+nXRoUMHkZKSIoYMGSIVMMy5/c2fP18MGjTI4v3Muf09/vjj4i9/+YtJ21NPPSX+/Oc/CyGYc3urWsDYK7/nzp0TAMTx48elPhkZGQKA+P77762Ojy8hASgrK8OpU6cQGhpq0h4aGopjx47do6gajuLiYgCAt7c3ACA3NxeFhYUm+dZoNBgyZIiU71OnTsFgMJj08ff3R/fu3XlMahAZGYnHH38cI0aMMGlnzu3vwIED6Nu3L55++mn4+PggMDAQ7777rnQ/c25/gwYNwhdffIEffvgBAJCdnY2jR49izJgxAJjz+mav/GZkZECn06F///5SnwEDBkCn08k6Bg3myxzr4sqVK6ioqECLFi1M2lu0aIHCwsJ7FFXDIIRATEwMBg0ahO7duwOAlFNz+b548aLUx9XVFU2aNKnWh8fEvJ07d+L06dP49ttvq93HnNvfzz//jM2bNyMmJgYLFy7EN998g7lz50Kj0WDatGnMeT2YP38+iouL0blzZzg7O6OiogIrV67EM888A4CP8/pmr/wWFhbCx8en2vw+Pj6yjgELmLuoVCqTbSFEtTaSZ/bs2fjuu+9w9OjRavfZkm8eE/MuXbqEqKgoHDp0CG5ubhb7Mef2YzQa0bdvX6xatQoAEBgYiLNnz2Lz5s2YNm2a1I85t59du3Zh27Zt2L59O7p164asrCy8+OKL8Pf3R3h4uNSPOa9f9sivuf5yjwFfQgLQrFkzODs7V6v8ioqKqlWaZL05c+bgwIEDOHLkCFq2bCm1+/r6AkCN+fb19UVZWRmuXr1qsQ/9n1OnTqGoqAh9+vSBi4sLXFxckJaWho0bN8LFxUXKGXNuP35+fujatatJW5cuXZCXlweAj/P68PLLL2PBggWYMmUKevTogbCwMERHR2P16tUAmPP6Zq/8+vr64tdff602/2+//SbrGLCAAeDq6oo+ffogJSXFpD0lJQUDBw68R1EplxACs2fPxp49e/Dll1+ibdu2Jve3bdsWvr6+JvkuKytDWlqalO8+ffpArVab9CkoKMC///1vHhMzhg8fjjNnziArK0u69e3bF1OnTkVWVhbatWvHnNvZo48+Wu3jAX744Qe0bt0aAB/n9eHWrVtwcjJ92nJ2dpbeRs2c1y975TcoKAjFxcX45ptvpD4nTpxAcXGxvGNg/fXIDVvl26i3bNkizp07J1588UXh6ekpfvnll3sdmuL87W9/EzqdTqSmpoqCggLpduvWLanPmjVrhE6nE3v27BFnzpwRzzzzjNm34rVs2VIcPnxYnD59Wjz22GN8q6MMd78LSQjm3N6++eYb4eLiIlauXCl+/PFH8eGHHwoPDw+xbds2qQ9zbl/h4eHioYcekt5GvWfPHtGsWTMxb948qQ9zXjfXr18XmZmZIjMzUwAQr7/+usjMzJQ+UsRe+R01apTo2bOnyMjIEBkZGaJHjx58G3VdbNq0SbRu3Vq4urqK3r17S2/7JXkAmL0lJCRIfYxGo1i6dKnw9fUVGo1GBAcHizNnzpjMc/v2bTF79mzh7e0t3N3dxdixY0VeXp6DV6NcVQsY5tz+Pv74Y9G9e3eh0WhE586dxT//+U+T+5lz+9Lr9SIqKkq0atVKuLm5iXbt2olXXnlFlJaWSn2Y87o5cuSI2d/f4eHhQgj75ff3338XU6dOFV5eXsLLy0tMnTpVXL16VVasKiGEsOFMEhEREdE9w2tgiIiISHFYwBAREZHisIAhIiIixWEBQ0RERIrDAoaIiIgUhwUMERERKQ4LGCIiIlIcFjBERESkOCxgiIiISHFYwBAREZHisIAhIiIixWEBQ0RERIrz/wGHP7qru9WAdAAAAABJRU5ErkJggg==", + "text/plain": [ + "
" + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], "source": [ "plt.plot(t, 1*util.zero2nan(ww_false_detects), 'rx', label='False Detections')\n", "plt.plot(t, 2*(util.zero2nan(ww_true_detects)), 'g*', label='True Detections')\n", @@ -827,7 +1469,7 @@ { "cell_type": "code", "execution_count": null, - "id": "5fffca80-705b-46ff-b259-12624d10be62", + "id": "9ed9de86-e0d5-4ec7-a7bb-00b324ac9eef", "metadata": {}, "outputs": [], "source": [] @@ -849,7 +1491,7 @@ "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", - "version": "3.11.8" + "version": "3.11.11" } }, "nbformat": 4, diff --git a/benchmark/training/streaming_wakeword/evaluate.py b/benchmark/training/streaming_wakeword/evaluate.py index 2c1b5a85..231550a8 100644 --- a/benchmark/training/streaming_wakeword/evaluate.py +++ b/benchmark/training/streaming_wakeword/evaluate.py @@ -15,18 +15,49 @@ Flags = util.parse_command("evaluate") -if not Flags.use_tflite_model and Flags.saved_model_path is None: - err_str = "Unless use_tflite_model is specified, saved_model_path is required." -if Flags.use_tflite_model and Flags.tfl_file_name is None: - err_str = "When use_tflite_model is specified, tfl_file_name is required." +if Flags.saved_model_path is None: + err_str = "Model to be evaluated must be specified with --saved_model_path" + raise RuntimeError(err_str) det_thresh = 0.95 samp_freq = Flags.sample_rate -# For wav file 'long_wav.wav', the wakeword windows should be in 'long_wav_ww_windows.json' -ww_windows_file = Flags.test_wav_path.split('.')[0] + '_ww_windows.json' -if Flags.use_tflite_model: - interpreter = tf.lite.Interpreter(model_path=Flags.tfl_file_name) + +if Flags.stream_config is None: + test_streaming = False +else: + test_streaming = True + with open(Flags.stream_config, 'r') as fpi: + stream_test_config = json.load(fpi) + + wav_file = stream_test_config[0]['wav_file'] + wav_file = os.path.join(Flags.wav_dir, wav_file) + ww_windows = stream_test_config[0]['detection_windows'] + +if Flags.specgram: + specgram = np.load(Flags.specgram)['specgram'] + # accept anything that squeezes to Nx, + # set shape to (1,time_steps,1,features) + specgram = np.expand_dims(np.squeeze(specgram), [0,2]) + long_spec = None + long_spec_q = None + if specgram.dtype == np.int8: + long_spec_q = specgram + num_frames = long_spec_q.shape[1] + elif specgram.dtype == np.int16: + long_spec_q = specgram.astype(np.int8) + num_frames = long_spec_q.shape[1] + elif specgram.dtype in [np.dtype('float32'), np.dtype('float64')]: + long_spec = specgram + num_frames = long_spec.shape[1] +else: + long_spec = None + long_spec_q = None + +use_tflite = Flags.saved_model_path.rsplit('.')[-1] in ["tflite", "tfl"] + +if use_tflite: + interpreter = tf.lite.Interpreter(model_path=Flags.saved_model_path) interpreter.allocate_tensors() input_details = interpreter.get_input_details() output_details = interpreter.get_output_details() @@ -35,59 +66,71 @@ labels = [] input_scale, input_zero_point = input_details[0]["quantization"] output_scale, output_zero_point = output_details[0]["quantization"] -else: +elif Flags.saved_model_path.rsplit('.')[-1] in ["h5", "keras"]: with tfmot.quantization.keras.quantize_scope(): # needed for the QAT wrappers model_std = keras.models.load_model(Flags.saved_model_path) # normal model for fixed-length inputs - ## Build a model that can accept variable-length inputs to process the long waveform/spectrogram Flags.variable_length=True model_varlen = models.get_model(args=Flags, use_qat=False) # model with variable-length input Flags.variable_length=False # transfer weights from trained model into variable-length model model_varlen.set_weights(model_std.get_weights()) +else: + raise RuntimeError("Model file ({Flags.saved_model_path}) must end in '.tflite', '.h5', or '.keras'.") + +if test_streaming: + long_wav = None + if long_spec is None and long_spec_q is None: + wav_sampling_freq, long_wav = wavfile.read(wav_file) + assert wav_sampling_freq == samp_freq + + if len(long_wav.shape) > 1: # stereo (or higher multi-channel) wav + long_wav = long_wav[:,0] # just take 1st channel + + long_wav = long_wav / 2**15 # scale into [-1.0, +1.0] range + t = np.arange(len(long_wav))/samp_freq + + data_config = get_dataset.get_data_config(Flags, 'validation') + feature_extractor = get_dataset.get_lfbe_func(data_config) + long_spec = feature_extractor(long_wav).numpy() + long_spec = np.expand_dims(long_spec, 0) # add batch dimension + num_frames = long_spec.shape[1] + if long_wav is not None: + print(f"Long waveform shape = {long_wav.shape}. ") + if long_spec is not None: + print(f"Long spectrogram (float) shape = {long_spec.shape}. ") + if long_spec_q is not None: + print(f"Long spectrogram (quantized) shape = {long_spec_q.shape}. ") + + + + if use_tflite: + yy_q = np.nan*np.zeros((num_frames-input_shape[1]+1,3)) + if long_spec_q is None: + long_spec_q = np.array(long_spec/input_scale + input_zero_point, dtype=np.int8) + + for idx in range(num_frames-input_shape[1]+1): + spec_q = long_spec_q[0:1, idx:idx+input_shape[1],:,:] -wav_sampling_freq, long_wav = wavfile.read(Flags.test_wav_path) -assert wav_sampling_freq == samp_freq - -data_config = get_dataset.get_data_config(Flags, 'validation') - -long_wav = long_wav / np.max(np.abs(long_wav)) # scale into [-1.0, +1.0] range -t = np.arange(len(long_wav))/samp_freq - -feature_extractor = get_dataset.get_lfbe_func(data_config) -long_spec = feature_extractor(long_wav).numpy() -print(f"Long waveform shape = {long_wav.shape}, spectrogram shape = {long_spec.shape}") - -if Flags.use_tflite_model: - yy_q = np.nan*np.zeros((long_spec.shape[0]-input_shape[1]+1,3)) + interpreter.set_tensor(input_details[0]['index'], spec_q) + interpreter.invoke() + # get_tensor() returns a copy of the tensor data. + # Use `tensor()` to get a pointer to it + yy_q[idx,:] = interpreter.get_tensor(output_details[0]['index']) - for idx in range(long_spec.shape[0]-input_shape[1]+1): - spec = long_spec[idx:idx+input_shape[1],:,:] - spec = np.expand_dims(spec, 0) # add batch dimension - spec_q = np.array(spec/input_scale + input_zero_point, dtype=np.int8) - - interpreter.set_tensor(input_details[0]['index'], spec_q) - interpreter.invoke() - # get_tensor() returns a copy of the tensor data. - # Use `tensor()` to get a pointer to it - yy_q[idx,:] = interpreter.get_tensor(output_details[0]['index']) - - # Dequantize so that softmax output is in range [0,1] - yy = (yy_q.astype(np.float32) - output_zero_point)*output_scale -else: - yy = model_varlen(np.expand_dims(long_spec, 0))[0].numpy() + # Dequantize so that softmax output is in range [0,1] + yy = (yy_q.astype(np.float32) - output_zero_point)*output_scale + else: + yy = model_varlen(long_spec)[0].numpy() -## shows detection when ww activation > thresh -with open(ww_windows_file, 'r') as fpi: - ww_windows = json.load(fpi) -ww_present = np.zeros(len(long_wav)) -for t_start, t_stop in ww_windows: - idx_start = int(t_start*samp_freq) - idx_stop = int(t_stop*samp_freq) - ww_present[idx_start:idx_stop] = 1 + ww_present = np.zeros(int(stream_test_config[0]['length_sec']*stream_test_config[0]['sample_rate'])) + for t_start, t_stop in ww_windows: + idx_start = int(t_start*samp_freq) + idx_stop = int(t_stop*samp_freq) + ww_present[idx_start:idx_stop] = 1 -ww_detected_spec_scale = (yy[:,0]>det_thresh).astype(int) -ww_true_detects, ww_false_detects, ww_false_rejects = util.get_true_and_false_detections(ww_detected_spec_scale, ww_present, Flags) + ww_detected_spec_scale = (yy[:,0]>det_thresh).astype(int) + ww_true_detects, ww_false_detects, ww_false_rejects = util.get_true_and_false_detections(ww_detected_spec_scale, ww_present, Flags) flags_validation = get_dataset.get_data_config(Flags, 'validation') flags_validation.batch_size = 50 @@ -97,7 +140,7 @@ _, _, val_files = get_dataset.get_file_lists(data_dir) ds_val = get_dataset.get_data(flags_validation, val_files) -if not Flags.use_tflite_model: +if not use_tflite: val_loss, val_acc, val_prec, val_recl = model_std.evaluate(ds_val) print(f"Results: false_detections={np.sum(ww_false_detects!=0)},", @@ -105,7 +148,7 @@ f"false_rejections={np.sum(ww_false_rejects!=0)},", end="" ) -if not Flags.use_tflite_model: +if not use_tflite: print(f"val_loss={val_loss:5.4f}, val_acc={val_acc:5.4f}, val_precision={val_prec:5.4f}, val_recall={val_recl:5.4f}") else: print("") # We need a newline diff --git a/benchmark/training/streaming_wakeword/get_dataset.py b/benchmark/training/streaming_wakeword/get_dataset.py index d669aa20..747d3861 100644 --- a/benchmark/training/streaming_wakeword/get_dataset.py +++ b/benchmark/training/streaming_wakeword/get_dataset.py @@ -461,6 +461,14 @@ def get_file_lists(data_dir): def get_all_datasets(Flags): + if Flags.saved_datasets_path: + # specified a path to load pre-built datasets from + ds_val = tf.data.Dataset.load(os.path.join(Flags.saved_datasets_path, 'sww_val')) + ds_train = tf.data.Dataset.load(os.path.join(Flags.saved_datasets_path, 'sww_train')) + ds_test = tf.data.Dataset.load(os.path.join(Flags.saved_datasets_path, 'sww_test')) + return ds_train, ds_test, ds_val + + # Otherwise, build the datasets now flags_training = get_data_config(Flags, 'training') flags_validation = get_data_config(Flags, 'validation') flags_test = get_data_config(Flags, 'test') @@ -689,3 +697,8 @@ def count_labels(ds, label_index=1): print(f"Input tensor shape: {dat[0].shape}") print(f"Label shape: {dat[1].shape}") print(f"Number of each class in training set:\n {count_labels(ds_train, label_index=1)}") + + os.makedirs("saved_datasets", exist_ok=True) + ds_train.save("saved_datasets/sww_train") + ds_val.save("saved_datasets/sww_val") + ds_test.save("saved_datasets/sww_test") \ No newline at end of file diff --git a/benchmark/training/streaming_wakeword/keras_model.py b/benchmark/training/streaming_wakeword/keras_model.py index ac912a16..2af82d0f 100644 --- a/benchmark/training/streaming_wakeword/keras_model.py +++ b/benchmark/training/streaming_wakeword/keras_model.py @@ -300,7 +300,7 @@ def apply_qat(float_model, Flags, init_lr=None): qat_model.compile( optimizer=optimizer, # Optimizer # Loss function to minimize - loss=keras.losses.CategoricalCrossentropy(from_logits=True), + loss=keras.losses.CategoricalCrossentropy(from_logits=False), # List of metrics to monitor metrics=[keras.metrics.CategoricalAccuracy(), keras.metrics.Precision(class_id=0, name='precision'), # prec = true_pos / (true_pos + false_pos) diff --git a/benchmark/training/streaming_wakeword/long_wav_spec.json b/benchmark/training/streaming_wakeword/long_wav_spec.json index 999afd23..15248596 100644 --- a/benchmark/training/streaming_wakeword/long_wav_spec.json +++ b/benchmark/training/streaming_wakeword/long_wav_spec.json @@ -19,106 +19,122 @@ ["{musan_path}/music/jamendo/music-jamendo-0000.wav", 450.0, 600.0, 0.5], ["{musan_path}/speech/librivox/speech-librivox-0052.wav", - 600.0, 1200.0, 0.5]], + 600.0, 900.0, 0.75], + ["{musan_path}/music/jamendo/music-jamendo-0001.wav", + 750.0, 900.0, 0.5], + ["{musan_path}/speech/librivox/speech-librivox-0121.wav", + 900.0, 1200.0, 0.2], + ["{musan_path}/speech/librivox/speech-librivox-0122.wav", + 900.0, 1200.0, 0.2], + ["{musan_path}/speech/librivox/speech-librivox-0127.wav", + 900.0, 1200.0, 0.2], + ["{musan_path}/speech/librivox/speech-librivox-0133.wav", + 900.0, 1200.0, 0.2], + ["{musan_path}/speech/librivox/speech-librivox-0134.wav", + 900.0, 1200.0, 0.2], + ["{musan_path}/speech/librivox/speech-librivox-0136.wav", + 900.0, 1200.0, 0.2], + ["{musan_path}/speech/librivox/speech-librivox-0137.wav", + 900.0, 1200.0, 0.2]], "configs_wakeword": [["{speech_commands_path}/marvin/aef8dcf5_nohash_0.wav", - 16.229071575753714, 0.657803189568536], + 9.457699148021609, 0.724306151917079], ["{speech_commands_path}/marvin/24ad3ebe_nohash_1.wav", - 20.000302140306424, 0.6593721253576948], + 14.866165678266617, 0.5608508052203299], ["{speech_commands_path}/marvin/5c8af87a_nohash_0.wav", - 23.97231385867567, 0.7215327660369368], + 29.943786017959138, 0.6480854247044934], ["{speech_commands_path}/marvin/aa48c94a_nohash_0.wav", - 56.577841864814765, 0.7242227184635466], + 40.32364972086644, 0.6132147304608184], ["{speech_commands_path}/marvin/e49428d9_nohash_0.wav", - 63.02169482052869, 0.7344053729516361], + 71.60258229170311, 0.6581556322658568], ["{speech_commands_path}/marvin/881583a6_nohash_2.wav", - 81.38089587308035, 0.6672923811504542], + 75.57735272129615, 0.6457143035991824], ["{speech_commands_path}/marvin/837a0f64_nohash_0.wav", - 89.16674123163172, 0.7190680727442875], + 89.17634151240425, 0.6210875934963049], ["{speech_commands_path}/marvin/e1469561_nohash_0.wav", - 101.55999914967485, 0.5306298499392005], + 97.79050346636096, 0.6303983227874175], ["{speech_commands_path}/marvin/68dd409e_nohash_0.wav", - 124.67982916101138, 0.6598581149477178], + 110.9397651119379, 0.5778624200119693], ["{speech_commands_path}/marvin/82d0d3ba_nohash_0.wav", - 128.88723502000693, 0.7442148316386193], + 127.87707248408691, 0.5361732308275764], ["{speech_commands_path}/marvin/f428ca69_nohash_0.wav", - 133.78392429983631, 0.7066535969357202], + 132.38191493891796, 0.5376488697952397], ["{speech_commands_path}/marvin/af130f12_nohash_0.wav", - 138.76048061963422, 0.5783362195183929], + 141.56004183815355, 0.7491430540063989], ["{speech_commands_path}/marvin/bb05582b_nohash_0.wav", - 147.64029864866458, 0.7460196203469727], + 149.32010817301082, 0.7149132648233256], ["{speech_commands_path}/marvin/adebe223_nohash_0.wav", - 164.6949502906318, 0.6053952662705212], + 166.55561403976228, 0.7345235331171829], ["{speech_commands_path}/marvin/f2e59fea_nohash_0.wav", - 167.98393271859368, 0.697893902963756], + 178.40966631662045, 0.7202401774764929], ["{speech_commands_path}/marvin/84d1e469_nohash_0.wav", - 175.79393706585003, 0.6385902671593385], + 185.4232969562747, 0.6641137751253303], ["{speech_commands_path}/marvin/8fe52b97_nohash_1.wav", - 183.67362158538543, 0.5165426192302494], + 192.904178291618, 0.6764018898421296], ["{speech_commands_path}/marvin/24ad3ebe_nohash_2.wav", - 193.51460376936365, 0.7126459515391874], + 198.48536964291674, 0.5143800329510807], ["{speech_commands_path}/marvin/6f689791_nohash_1.wav", - 202.47788400887646, 0.5160055552728352], + 211.5300562297426, 0.5678860748756083], ["{speech_commands_path}/marvin/8c7f81df_nohash_1.wav", - 226.09126232290848, 0.6002320256490437], + 233.16532782338965, 0.6106377827212875], ["{speech_commands_path}/marvin/f0ae7203_nohash_0.wav", - 234.4500493304255, 0.6498829259398738], + 254.19470632991752, 0.6983615406426421], ["{speech_commands_path}/marvin/881583a6_nohash_0.wav", - 243.74868779866037, 0.5454084302319451], + 260.81755774050254, 0.5622580379337591], ["{speech_commands_path}/marvin/881583a6_nohash_1.wav", - 251.5162013128198, 0.5528983906437042], + 266.34809708416185, 0.5113549584327977], ["{speech_commands_path}/marvin/8c7f81df_nohash_0.wav", - 268.5928641840698, 0.7359596046611364], + 274.67550844370504, 0.5568657072936736], ["{speech_commands_path}/marvin/6f689791_nohash_0.wav", - 272.004333811165, 0.5220865207660534], + 285.39852514726283, 0.6364511186464485], ["{speech_commands_path}/marvin/24ad3ebe_nohash_3.wav", - 288.3300593015517, 0.5892359226842943], + 292.49966340899624, 0.6245386458216131], ["{speech_commands_path}/marvin/8fe52b97_nohash_0.wav", - 293.6091144374838, 0.7477025107447157], + 302.3460304056669, 0.7280558689180203], ["{speech_commands_path}/marvin/97f4c236_nohash_0.wav", - 304.839879841441, 0.706749043113472], + 317.89990745866504, 0.7298172496317112], ["{speech_commands_path}/marvin/9dc1889e_nohash_0.wav", - 310.11538263897836, 0.5516767965938119], + 335.72569960586367, 0.6529979245050829], ["{speech_commands_path}/marvin/4a0e2c16_nohash_0.wav", - 320.9877938139524, 0.7167975421885555], + 339.9323432035216, 0.5209287478614644], ["{speech_commands_path}/marvin/1f653d27_nohash_0.wav", - 324.1341397542963, 0.6913598618935543], + 354.18497848970264, 0.6276412318922729], ["{speech_commands_path}/marvin/2d82a556_nohash_1.wav", - 357.9081050933056, 0.7115740786619087], + 366.49002026148355, 0.6893303011575491], ["{speech_commands_path}/marvin/e71b4ce6_nohash_0.wav", - 362.26344892847663, 0.591941702975159], + 373.16182873429506, 0.7278377797868263], ["{speech_commands_path}/marvin/80c45ed6_nohash_2.wav", - 380.8711044003867, 0.621846821288198], + 386.9434694621524, 0.6623484013902962], ["{speech_commands_path}/marvin/67961766_nohash_2.wav", - 384.2346207845156, 0.6772289173334913], + 395.0541728315638, 0.7328228829654188], ["{speech_commands_path}/marvin/840c366d_nohash_1.wav", - 402.25071019327703, 0.5476676296572367], + 399.2932943605985, 0.716202207123029], ["{speech_commands_path}/marvin/840c366d_nohash_0.wav", - 415.6399291473533, 0.6886462580564907], + 404.3458177829189, 0.6563453758695152], ["{speech_commands_path}/marvin/e41a903b_nohash_0.wav", - 418.71943860239855, 0.5480560273434394], + 410.9040638273914, 0.6109774146574021], ["{speech_commands_path}/marvin/692a88e6_nohash_0.wav", - 442.74351300712686, 0.7255048393335597], + 418.45050278921127, 0.5341640138099255], ["{speech_commands_path}/marvin/2d82a556_nohash_0.wav", - 447.81405528633, 0.6451813529152302], + 441.25585954785487, 0.5332032603233139], ["{speech_commands_path}/marvin/9e2ce5e3_nohash_0.wav", - 459.7354647658462, 0.6259302521599827], + 466.9332413514287, 0.6740075718073801], ["{speech_commands_path}/marvin/67961766_nohash_1.wav", - 465.3119810247103, 0.5943529827466616], + 481.23043434530354, 0.7004036892485519], ["{speech_commands_path}/marvin/80c45ed6_nohash_1.wav", - 480.21827218895436, 0.7251826382892596], + 488.29791732445136, 0.625336027891189], ["{speech_commands_path}/marvin/c0e0f834_nohash_0.wav", - 510.2157607743749, 0.6694475495797485], + 496.47744390720834, 0.6523519033196651], ["{speech_commands_path}/marvin/67961766_nohash_0.wav", - 525.9717529118909, 0.5082332580660699], + 502.42084091952097, 0.5592056535353054], ["{speech_commands_path}/marvin/c0e0f834_nohash_1.wav", - 533.2444344074248, 0.537421565839141], + 528.0783744201342, 0.653409044240299], ["{speech_commands_path}/marvin/fce96bac_nohash_0.wav", - 555.0747689296215, 0.6534650305098237], + 540.616396347511, 0.6071958060590349], ["{speech_commands_path}/marvin/80c45ed6_nohash_0.wav", - 559.2413221205452, 0.7428230359663885], + 546.8588128048474, 0.6097447970804359], ["{speech_commands_path}/marvin/553f1a79_nohash_0.wav", - 565.2280420877757, 0.6657979567340233], + 558.2905924746461, 0.7323179983845585], ["{speech_commands_path}/marvin/c9b5ff26_nohash_0.wav", - 570.0, 0.7426126320610982]], + 570.0, 0.5798377356033875]], "length_sec": 1200.0, "sample_rate": 16000} \ No newline at end of file diff --git a/benchmark/training/streaming_wakeword/long_wav_ww_windows.json b/benchmark/training/streaming_wakeword/long_wav_ww_windows.json deleted file mode 100644 index c753dedc..00000000 --- a/benchmark/training/streaming_wakeword/long_wav_ww_windows.json +++ /dev/null @@ -1,40 +0,0 @@ -[[16.229071575753714, 16.876696575753716], - [20.000302140306424, 20.762052140306423], - [23.97231385867567, 24.33093885867567], - [56.577841864814765, 57.479529364814766], - [63.02169482052869, 63.41588232052869], [81.38089587308035, 81.92202087308034], - [89.16674123163172, 89.61111623163171], - [101.55999914967485, 102.25606164967485], - [124.67982916101138, 125.21839166101138], - [128.88723502000693, 129.77511002000693], - [133.78392429983631, 134.5469867998363], - [138.76048061963422, 139.74973061963422], - [147.64029864866458, 148.1523611486646], - [164.6949502906318, 165.6889502906318], - [167.98393271859368, 168.45787021859368], - [175.79393706585003, 176.26718706585004], - [183.67362158538543, 184.25218408538544], - [193.51460376936365, 194.39829126936365], - [202.47788400887646, 202.97407150887645], - [226.09126232290848, 226.7325123229085], - [234.4500493304255, 235.2081743304255], - [243.74868779866037, 244.68900029866037], - [251.5162013128198, 252.31063881281978], - [268.5928641840698, 269.2106141840698], [272.004333811165, 272.532646311165], - [288.3300593015517, 289.05224680155175], - [293.6091144374838, 294.13936443748383], [304.839879841441, 305.244942341441], - [310.11538263897836, 310.4915701389784], - [320.9877938139524, 321.2801688139524], [324.1341397542963, 324.7345772542963], - [357.9081050933056, 358.8807925933056], - [362.26344892847663, 362.81157392847666], - [380.8711044003867, 381.6713544003867], - [384.2346207845156, 384.92730828451556], - [402.25071019327703, 403.087085193277], [415.6399291473533, 416.6242416473533], - [418.71943860239855, 419.1595636023986], - [442.74351300712686, 443.23957550712686], [447.81405528633, 448.66361778633], - [459.7354647658462, 460.3308397658462], [465.3119810247103, 465.9446060247103], - [480.21827218895436, 481.17839718895436], - [510.2157607743749, 510.62851077437494], [525.9717529118909, 526.859752911891], - [533.2444344074248, 533.6189969074248], [555.0747689296215, 555.4490189296215], - [559.2413221205452, 559.8313221205452], [565.2280420877757, 565.7367920877757], - [570.0, 570.593]] \ No newline at end of file diff --git a/benchmark/training/streaming_wakeword/short_wav_easy10s.wav b/benchmark/training/streaming_wakeword/short_wav_easy10s.wav new file mode 100644 index 00000000..ae40e12b Binary files /dev/null and b/benchmark/training/streaming_wakeword/short_wav_easy10s.wav differ diff --git a/benchmark/training/streaming_wakeword/short_wav_easy10s_spec.json b/benchmark/training/streaming_wakeword/short_wav_easy10s_spec.json new file mode 100644 index 00000000..95ff8b97 --- /dev/null +++ b/benchmark/training/streaming_wakeword/short_wav_easy10s_spec.json @@ -0,0 +1,12 @@ +{"configs_background": [["{musan_path}/music/hd-classical/music-hd-0002.wav", + 5.0, 10.0, 0.05] + ], + "configs_wakeword": [["{speech_commands_path}/marvin/aef8dcf5_nohash_0.wav", + 1.0, 0.7], + ["{speech_commands_path}/marvin/24ad3ebe_nohash_1.wav", + 4.0, 0.8], + ["{speech_commands_path}/marvin/5c8af87a_nohash_0.wav", + 7.0, 0.9] + ], + "length_sec": 10.0, + "sample_rate": 16000} diff --git a/benchmark/training/streaming_wakeword/str_ww_util.py b/benchmark/training/streaming_wakeword/str_ww_util.py index 7373c533..949cbbc4 100644 --- a/benchmark/training/streaming_wakeword/str_ww_util.py +++ b/benchmark/training/streaming_wakeword/str_ww_util.py @@ -6,6 +6,18 @@ from tensorflow import keras def add_dataset_args(parser): + parser.add_argument( + '--saved_datasets_path', + type=str, + default=None, + help="""\ + Loads training, validation, test, datasets from the specified directory. If set, the + given directory should contain sub-directories named 'sww_test', 'sww_train', and 'sww_val', + created by e.g. `ds_train.save("saved_datasets/sww_train")`. The get_datasets.py script + does this. Combined with the get_datasets.py script, this flag allows you to re-use the dataset, + without repeating the (time-consuming) pre-preprocssing. If not set, the datasets will be built + prior to training. + """) parser.add_argument( '--num_background_clips', type=int, @@ -16,7 +28,7 @@ def add_dataset_args(parser): parser.add_argument( '--l2_reg', type=float, - default=0.001, + default=0.0, help='L2 regularization coefficient for conv layers',) parser.add_argument( '--min_snr_training', @@ -233,7 +245,6 @@ def add_dataset_args(parser): default=0.001, help='Initial LR',) - def add_training_args(parser): parser.add_argument( '--use_qat', @@ -253,7 +264,7 @@ def add_training_args(parser): parser.add_argument( '--epochs', type=int, - default=65, + default=100, help="""\ How many (total) epochs to train. If use_qat is enabled, and pretrain_epochs>0 then the model will pretrain (without QAT) for pretrain_epochs, then train @@ -308,10 +319,18 @@ def add_training_args(parser): """) def add_eval_args(parser): + # ../../runner/sww_data_dir/sww_long_test.json parser.add_argument( - '--test_wav_path', + '--stream_config', type=str, - default="long_wav.wav", + default="../../runner/sww_data_dir/sww_long_test.json", + help="""\ + JSON file defining the streaming test. If None, skips the streaming and + """) + parser.add_argument( + '--wav_dir', + type=str, + default="../../runner/sd_card/", help="""\ Wav file to run the model on for the long-wav test. """) @@ -322,15 +341,16 @@ def add_eval_args(parser): default=None, help='Trained model to evaluate') parser.add_argument( - '--use_tflite_model', - action="store_true", - help="""\ - Run the TFLite model. Otherwise, run the standard keras model - """) - parser.add_argument( - '--tfl_file_name', + '--specgram', + type=str, + required=False, default=None, - help='File name from which the TF Lite model is loaded.') + help=""" + Pre-computed spectrogram to use for long-wav test instead of computing features from wav file. + Should specify an npz file with an element named 'specgram'. E.g. `np.savez('test.npz', specgram=specgram)` + Spectrogram should squeeze to shape (N, 40) and correspond to the detection windows specified in stream_config + """) + def add_quantize_args(parser): @@ -345,6 +365,24 @@ def add_quantize_args(parser): default='trained_models/strm_ww_int8.tflite', help='File name to which the TF Lite model will be saved (quantize.py) or loaded (eval_quantized_model)') +def add_long_wav_args(parser): + parser.add_argument( + '--long_wav_name', + type=str, + default="long_wav.wav", + help="File name for the wav file being built") + parser.add_argument( + '--wav_spec', + type=str, + default="long_wav_spec.json", + help="JSON file specifying recipe for the long wav") + parser.add_argument( + '--rel_thresh', + type=float, + default=0.05, + help="Threshold (relative to peak) used to clip wakewords inserted into long wav") + + def parse_command(main_program): parser = argparse.ArgumentParser() @@ -355,6 +393,8 @@ def parse_command(main_program): add_eval_args(parser) if main_program == "quantize": add_quantize_args(parser) + if main_program == "build_long_wav": + add_long_wav_args(parser) Flags = parser.parse_args() diff --git a/benchmark/training/streaming_wakeword/train.py b/benchmark/training/streaming_wakeword/train.py index 141f1ade..502a4815 100644 --- a/benchmark/training/streaming_wakeword/train.py +++ b/benchmark/training/streaming_wakeword/train.py @@ -34,10 +34,13 @@ os.makedirs(Flags.plot_dir) -print("Using speech commands data from {Flags.speech_commands_path} \nand background noise from {Flags.musan_path}") +print(f"Using speech commands data from {Flags.speech_commands_path} \nand background noise from {Flags.musan_path}") print(20*'-') -ds_train, ds_test, ds_val = str_ww_data.get_all_datasets(Flags) +if Flags.saved_datasets_path is None: + ds_train, ds_test, ds_val = str_ww_data.get_all_datasets(Flags) +else: + ds_train, ds_test, ds_val = str_ww_data.get_all_datasets(Flags) print("Done getting data") if Flags.model_init_path is None: @@ -78,10 +81,23 @@ post_train_lr = model.optimizer.lr.numpy() print(f"After initial float training, LR = {post_train_lr}") +# find rate such that over qat_epochs-10, LR decreases by 10x +if qat_epochs >10: + qat_lr_dec_rate = 0.1**(1/(qat_epochs-10)) +else: + qat_lr_dec_rate = 1.0 + +def qat_lr_scheduler(epoch, lr): + if epoch < 10: + return lr + else: + return lr * qat_lr_dec_rate + if qat_epochs > 0: - model_qat = models.apply_qat(model, Flags, init_lr=Flags.learning_rate) # init_lr=post_train_lr) + cb_lr_sched = keras.callbacks.LearningRateScheduler(qat_lr_scheduler) + model_qat = models.apply_qat(model, Flags, init_lr=0.1*Flags.learning_rate) # init_lr=post_train_lr) train_hist_qat = model_qat.fit(ds_train, validation_data=ds_val, - epochs=qat_epochs, callbacks=callbacks) + epochs=qat_epochs, callbacks=[cb_lr_sched]) util.plot_training(Flags.plot_dir,train_hist_qat, suffix='_qat') print(f"After QAT training/fine-tuning. On training set:") model.evaluate(ds_train) diff --git a/benchmark/training/streaming_wakeword/trained_models/str_ww_model.h5 b/benchmark/training/streaming_wakeword/trained_models/str_ww_model.h5 deleted file mode 100644 index 72918af1..00000000 Binary files a/benchmark/training/streaming_wakeword/trained_models/str_ww_model.h5 and /dev/null differ diff --git a/benchmark/training/streaming_wakeword/trained_models/str_ww_ref_model.h5 b/benchmark/training/streaming_wakeword/trained_models/str_ww_ref_model.h5 index baca7960..ddc9b892 100644 Binary files a/benchmark/training/streaming_wakeword/trained_models/str_ww_ref_model.h5 and b/benchmark/training/streaming_wakeword/trained_models/str_ww_ref_model.h5 differ diff --git a/benchmark/training/streaming_wakeword/trained_models/str_ww_ref_model.tflite b/benchmark/training/streaming_wakeword/trained_models/str_ww_ref_model.tflite new file mode 100644 index 00000000..53a7d4dd Binary files /dev/null and b/benchmark/training/streaming_wakeword/trained_models/str_ww_ref_model.tflite differ diff --git a/benchmark/training/streaming_wakeword/trained_models/strm_ww_int8.tflite b/benchmark/training/streaming_wakeword/trained_models/strm_ww_int8.tflite deleted file mode 100644 index 6e4a39e5..00000000 Binary files a/benchmark/training/streaming_wakeword/trained_models/strm_ww_int8.tflite and /dev/null differ